From e20f132f48c869efe34056c185d63784635430b3 Mon Sep 17 00:00:00 2001 From: Richard Barry Date: Wed, 13 Feb 2008 10:36:35 +0000 Subject: [PATCH] made a copy --- .../Demo/ARM7_AT91FR40008_GCC/AT91R40008.h | 707 + .../Demo/ARM7_AT91FR40008_GCC/ATEB40x.cfg | 24 + .../ARM7_AT91FR40008_GCC/FreeRTOSConfig.h | 89 + 20080212/Demo/ARM7_AT91FR40008_GCC/Makefile | 99 + .../ARM7_AT91FR40008_GCC/ParTest/ParTest.c | 130 + 20080212/Demo/ARM7_AT91FR40008_GCC/aic.h | 81 + .../Demo/ARM7_AT91FR40008_GCC/atmel-ram.ld | 48 + .../Demo/ARM7_AT91FR40008_GCC/atmel-rom.ld | 49 + 20080212/Demo/ARM7_AT91FR40008_GCC/boot.s | 157 + 20080212/Demo/ARM7_AT91FR40008_GCC/ebi.h | 121 + 20080212/Demo/ARM7_AT91FR40008_GCC/main.c | 479 + 20080212/Demo/ARM7_AT91FR40008_GCC/pio.h | 149 + .../Demo/ARM7_AT91FR40008_GCC/ram_arm.bat | 6 + .../Demo/ARM7_AT91FR40008_GCC/ram_thumb.bat | 6 + .../Demo/ARM7_AT91FR40008_GCC/rom_arm.bat | 6 + .../Demo/ARM7_AT91FR40008_GCC/rom_thumb.bat | 6 + .../Demo/ARM7_AT91FR40008_GCC/serial/serial.c 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.../uIP/uip-1.0/apps/webserver/httpd.h | 62 + .../uIP/uip-1.0/apps/webserver/makefsdata | 78 + .../uIP/uip-1.0/apps/webserver/makestrings | 40 + .../uIP/uip-1.0/apps/webserver/webserver.h | 49 + .../uIP/uip-1.0/uip-1.0-changelog.txt | 98 + .../ethernet/uIP/uip-1.0/uip/Makefile.include | 47 + .../Common/ethernet/uIP/uip-1.0/uip/clock.h | 88 + .../ethernet/uIP/uip-1.0/uip/lc-addrlabels.h | 83 + .../ethernet/uIP/uip-1.0/uip/lc-switch.h | 76 + .../Demo/Common/ethernet/uIP/uip-1.0/uip/lc.h | 131 + .../Common/ethernet/uIP/uip-1.0/uip/psock.c | 338 + .../Common/ethernet/uIP/uip-1.0/uip/psock.h | 380 + .../Demo/Common/ethernet/uIP/uip-1.0/uip/pt.h | 323 + .../Common/ethernet/uIP/uip-1.0/uip/timer.c | 127 + .../Common/ethernet/uIP/uip-1.0/uip/timer.h | 86 + .../Common/ethernet/uIP/uip-1.0/uip/uip-fw.c | 532 + .../Common/ethernet/uIP/uip-1.0/uip/uip-fw.h | 176 + .../ethernet/uIP/uip-1.0/uip/uip-neighbor.c | 159 + .../ethernet/uIP/uip-1.0/uip/uip-neighbor.h | 61 + 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20080212/Demo/Cygnal/serial/serial.c | 225 + 20080212/Demo/Flshlite/FRConfig.h | 97 + 20080212/Demo/Flshlite/FileIO/fileIO.c | 116 + 20080212/Demo/Flshlite/FreeRTOSConfig.h | 89 + 20080212/Demo/Flshlite/ParTest/ParTest.c | 140 + 20080212/Demo/Flshlite/RTOSDEMO.IDE | Bin 0 -> 41836 bytes 20080212/Demo/Flshlite/main.c | 395 + 20080212/Demo/Flshlite/rtosdemo.DSW | Bin 0 -> 3466 bytes 20080212/Demo/Flshlite/rtosdemo.lk1 | 2 + 20080212/Demo/Flshlite/rtosdemo.mk | 3 + 20080212/Demo/Flshlite/rtosdemo.mk1 | 191 + 20080212/Demo/Flshlite/rtosdemo.tgt | 1159 + 20080212/Demo/Flshlite/rtosdemo.wpj | 43 + 20080212/Demo/Flshlite/serial/serial.c | 490 + 20080212/Demo/H8S/RTOSDemo.hws | 38 + 20080212/Demo/H8S/RTOSDemo.tws | 28 + 20080212/Demo/H8S/RTOSDemo/2329S.h | 142 + 20080212/Demo/H8S/RTOSDemo/Debug/Debug.hdp | Bin 0 -> 1309 bytes 20080212/Demo/H8S/RTOSDemo/Debug/RTOSDemo.x | Bin 0 -> 84377 bytes .../Demo/H8S/RTOSDemo/Debug/gnuconfig.ini | 6 + 20080212/Demo/H8S/RTOSDemo/FreeRTOSConfig.h | 91 + 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20080212/Demo/HCS12_CodeWarrior_banked/main.c | 301 + .../HCS12_CodeWarrior_banked/prm/burner.bbl | 223 + .../Demo/HCS12_CodeWarrior_banked/readme.txt | 121 + .../HCS12_CodeWarrior_banked/serial/serial.c | 187 + .../CODE/ButtonInterrupt.C | 117 + .../CODE/ButtonInterrupt.H | 109 + .../Demo/HCS12_CodeWarrior_small/CODE/Byte1.C | 144 + .../Demo/HCS12_CodeWarrior_small/CODE/Byte1.H | 110 + .../CODE/Copy of Vectors.c | 115 + .../Demo/HCS12_CodeWarrior_small/CODE/Cpu.C | 233 + .../Demo/HCS12_CodeWarrior_small/CODE/Cpu.H | 140 + .../HCS12_CodeWarrior_small/CODE/Events.C | 87 + .../HCS12_CodeWarrior_small/CODE/Events.H | 74 + .../HCS12_CodeWarrior_small/CODE/IO_Map.C | 260 + .../HCS12_CodeWarrior_small/CODE/IO_Map.H | 8072 +++++ .../Demo/HCS12_CodeWarrior_small/CODE/PESL.h | 52 + .../HCS12_CodeWarrior_small/CODE/PE_Const.H | 50 + .../HCS12_CodeWarrior_small/CODE/PE_Error.H | 53 + .../HCS12_CodeWarrior_small/CODE/PE_Timer.C | 69 + .../HCS12_CodeWarrior_small/CODE/PE_Timer.H | 53 + .../HCS12_CodeWarrior_small/CODE/PE_Types.H | 87 + .../HCS12_CodeWarrior_small/CODE/RTOSDemo.C | 66 + .../HCS12_CodeWarrior_small/CODE/RTOSDemo.PRM | 48 + .../HCS12_CodeWarrior_small/CODE/TickTimer.C | 243 + .../HCS12_CodeWarrior_small/CODE/TickTimer.H | 160 + .../HCS12_CodeWarrior_small/CODE/Vectors.c | 115 + .../Demo/HCS12_CodeWarrior_small/C_Layout.hwl | 20 + .../HCS12_CodeWarrior_small/DOC/RTOSDemo.sig | 23 + .../HCS12_CodeWarrior_small/DOC/RTOSDemo.txt | 32 + .../HCS12_CodeWarrior_small/FreeRTOSConfig.h | 98 + .../HCS12_CodeWarrior_small/ParTest/ParTest.c | 79 + .../Demo/HCS12_CodeWarrior_small/RTOSDemo.G_C | 368 + .../Demo/HCS12_CodeWarrior_small/RTOSDemo.dsk | 166 + .../Demo/HCS12_CodeWarrior_small/RTOSDemo.mcp | Bin 0 -> 84225 bytes .../Demo/HCS12_CodeWarrior_small/RTOSDemo.pe | 2387 ++ .../RTOSDemo_Data/CWSettingsWindows.stg | Bin 0 -> 4553 bytes .../Simulator/TargetDataWindows.tdt | Bin 0 -> 73064 bytes .../SofTec/TargetDataWindows.tdt | Bin 0 -> 71603 bytes .../HCS12_CodeWarrior_small/Simulator.ini | 41 + .../Demo/HCS12_CodeWarrior_small/SofTec.ini | 50 + .../HCS12_CodeWarrior_small/Sources/Start12.c | 342 + .../Sources/datapage.c | 843 + .../HCS12_CodeWarrior_small/bin/Simulator.map | 2175 ++ .../HCS12_CodeWarrior_small/bin/SofTec.map | 2175 ++ .../cmd/Simulator_Postload.cmd | 3 + .../cmd/Simulator_Preload.cmd | 1 + .../cmd/Simulator_Reset.cmd | 1 + .../cmd/Simulator_SetCPU.cmd | 1 + .../cmd/Simulator_Startup.cmd | 1 + .../cmd/SofTec_Postload.cmd | 3 + .../cmd/SofTec_Preload.cmd | 1 + .../cmd/SofTec_Reset.cmd | 1 + .../cmd/SofTec_Startup.cmd | 1 + 20080212/Demo/HCS12_CodeWarrior_small/main.c | 374 + .../HCS12_CodeWarrior_small/prm/burner.bbl | 223 + .../Demo/HCS12_CodeWarrior_small/readme.txt | 117 + .../HCS12_CodeWarrior_small/serial/serial.c | 90 + .../Demo/HCS12_GCC_banked/FreeRTOSConfig.h | 102 + 20080212/Demo/HCS12_GCC_banked/Makefile | 64 + 20080212/Demo/HCS12_GCC_banked/PE_Error.h | 53 + 20080212/Demo/HCS12_GCC_banked/ParTest.c | 88 + 20080212/Demo/HCS12_GCC_banked/README.txt | 85 + .../asm-m68hcs12/arch-dragon12/arch/exit.h | 43 + .../arch-dragon12/arch/interrupts.h | 41 + .../asm-m68hcs12/arch-dragon12/arch/param.h | 47 + .../asm-m68hcs12/interrupts-dp256.h | 197 + .../asm-m68hcs12/interrupts.h | 54 + .../HCS12_GCC_banked/asm-m68hcs12/param.h | 99 + .../HCS12_GCC_banked/asm-m68hcs12/ports.h | 192 + .../HCS12_GCC_banked/asm-m68hcs12/ports_def.h | 666 + .../Demo/HCS12_GCC_banked/asm-m68hcs12/sio.h | 81 + 20080212/Demo/HCS12_GCC_banked/cpu.h | 39 + 20080212/Demo/HCS12_GCC_banked/gelfunc.c | 25 + .../Demo/HCS12_GCC_banked/ldscript-rtos.x | 266 + 20080212/Demo/HCS12_GCC_banked/main.c | 301 + 20080212/Demo/HCS12_GCC_banked/memory.x | 63 + 20080212/Demo/HCS12_GCC_banked/sci.c | 75 + 20080212/Demo/HCS12_GCC_banked/sci.h | 34 + 20080212/Demo/HCS12_GCC_banked/serial.c | 150 + 20080212/Demo/HCS12_GCC_banked/startup.c | 96 + .../Demo/HCS12_GCC_banked/sys/interrupts.h | 73 + 20080212/Demo/HCS12_GCC_banked/sys/param.h | 56 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000000000..e99ef0503 --- /dev/null +++ b/20080212/Demo/ARM7_AT91FR40008_GCC/AT91R40008.h @@ -0,0 +1,707 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// The software is delivered "AS IS" without warranty or condition of any +// kind, either express, implied or statutory. This includes without +// limitation any warranty or condition with respect to merchantability or +// fitness for any particular purpose, or against the infringements of +// intellectual property rights of others. +// ---------------------------------------------------------------------------- +// File Name : AT91R40008.h +// Object : AT91R40008 definitions +// Generated : AT91 SW Application Group 02/19/2003 (11:13:31) +// +// CVS Reference : /AT91R40008.pl/1.3/Tue Nov 12 16:01:52 2002// +// CVS Reference : /AIC_1246F.pl/1.4/Mon Nov 04 17:51:00 2002// +// CVS Reference : /WD_1241B.pl/1.1/Mon Nov 04 17:51:00 2002// +// CVS Reference : /PS_x40.pl/1.2/Tue Nov 12 16:01:52 2002// +// CVS Reference : /PIO_1321C.pl/1.5/Tue Oct 29 15:50:24 2002// +// CVS Reference : /TC_1243B.pl/1.4/Tue Nov 05 12:43:10 2002// +// CVS Reference : /PDC_1363D.pl/1.3/Wed Oct 23 14:49:48 2002// +// CVS Reference : /US_1242E.pl/1.5/Thu Nov 21 13:37:56 2002// +// CVS Reference : /SF_x40.pl/1.1/Tue Nov 12 13:27:20 2002// +// CVS Reference : /EBI_x40.pl/1.5/Wed Feb 19 09:25:22 2003// +// ---------------------------------------------------------------------------- + +#ifndef AT91R40008_H +#define AT91R40008_H + +/* AT91 Register type */ +typedef volatile unsigned int AT91_REG; // Hardware register definition +typedef volatile unsigned int at91_reg; + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +typedef struct _AT91S_AIC { + AT91_REG AIC_SMR[32]; // Source Mode egister + AT91_REG AIC_SVR[32]; // Source Vector egister + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command egister + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register +} AT91S_AIC, *AT91PS_AIC; + +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive +#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Interface +// ***************************************************************************** +typedef struct _AT91S_WD { + AT91_REG WD_OMR; // Overflow Mode Register + AT91_REG WD_CMR; // Clock Mode Register + AT91_REG WD_CR; // Control Register + AT91_REG WD_SR; // Status Register +} AT91S_WD, *AT91PS_WD; + +// -------- WD_OMR : (WD Offset: 0x0) Overflow Mode Register -------- +#define AT91C_WD_WDEN ((unsigned int) 0x1 << 0) // (WD) Watchdog Enable +#define AT91C_WD_RSTEN ((unsigned int) 0x1 << 1) // (WD) Reset Enable +#define AT91C_WD_IRQEN ((unsigned int) 0x1 << 2) // (WD) Interrupt Enable +#define AT91C_WD_EXTEN ((unsigned int) 0x1 << 3) // (WD) External Signal Enable +#define AT91C_WD_OKEY ((unsigned int) 0xFFF << 4) // (WD) Watchdog Enable +// -------- WD_CMR : (WD Offset: 0x4) Clock Mode Register -------- +#define AT91C_WD_WDCLKS ((unsigned int) 0x3 << 0) // (WD) Clock Selection +#define AT91C_WD_WDCLKS_MCK32 ((unsigned int) 0x0) // (WD) Master Clock divided by 32 +#define AT91C_WD_WDCLKS_MCK128 ((unsigned int) 0x1) // (WD) Master Clock divided by 128 +#define AT91C_WD_WDCLKS_MCK1024 ((unsigned int) 0x2) // (WD) Master Clock divided by 1024 +#define AT91C_WD_WDCLKS_MCK4096 ((unsigned int) 0x3) // (WD) Master Clock divided by 4096 +#define AT91C_WD_HPCV ((unsigned int) 0xF << 2) // (WD) High Pre-load Counter Value +#define AT91C_WD_CKEY ((unsigned int) 0x1FF << 7) // (WD) Clock Access Key +// -------- WD_CR : (WD Offset: 0x8) Control Register -------- +#define AT91C_WD_RSTKEY ((unsigned int) 0xFFFF << 0) // (WD) Restart Key +// -------- WD_SR : (WD Offset: 0xc) Status Register -------- +#define AT91C_WD_WDOVF ((unsigned int) 0x1 << 0) // (WD) Watchdog Overflow + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Saving Controler +// ***************************************************************************** +typedef struct _AT91S_PS { + AT91_REG PS_CR; // Control Register + AT91_REG PS_PCER; // Peripheral Clock Enable Register + AT91_REG PS_PCDR; // Peripheral Clock Disable Register + AT91_REG PS_PCSR; // Peripheral Clock Status Register +} AT91S_PS, *AT91PS_PS; + +// -------- PS_PCER : (PS Offset: 0x4) Peripheral Clock Enable Register -------- +#define AT91C_PS_US0 ((unsigned int) 0x1 << 2) // (PS) Usart 0 Clock +#define AT91C_PS_US1 ((unsigned int) 0x1 << 3) // (PS) Usart 1 Clock +#define AT91C_PS_TC0 ((unsigned int) 0x1 << 4) // (PS) Timer Counter 0 Clock +#define AT91C_PS_TC1 ((unsigned int) 0x1 << 5) // (PS) Timer Counter 1 Clock +#define AT91C_PS_TC2 ((unsigned int) 0x1 << 6) // (PS) Timer Counter 2 Clock +#define AT91C_PS_PIO ((unsigned int) 0x1 << 8) // (PS) PIO Clock +// -------- PS_PCDR : (PS Offset: 0x8) Peripheral Clock Disable Register -------- +// -------- PS_PCSR : (PS Offset: 0xc) Peripheral Clock Satus Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +typedef struct _AT91S_PIO { + AT91_REG PIO_PER; // PIO Enable Register + AT91_REG PIO_PDR; // PIO Disable Register + AT91_REG PIO_PSR; // PIO Status Register + AT91_REG Reserved0[1]; // + AT91_REG PIO_OER; // Output Enable Register + AT91_REG PIO_ODR; // Output Disable Registerr + AT91_REG PIO_OSR; // Output Status Register + AT91_REG Reserved1[1]; // + AT91_REG PIO_IFER; // Input Filter Enable Register + AT91_REG PIO_IFDR; // Input Filter Disable Register + AT91_REG PIO_IFSR; // Input Filter Status Register + AT91_REG Reserved2[1]; // + AT91_REG PIO_SODR; // Set Output Data Register + AT91_REG PIO_CODR; // Clear Output Data Register + AT91_REG PIO_ODSR; // Output Data Status Register + AT91_REG PIO_PDSR; // Pin Data Status Register + AT91_REG PIO_IER; // Interrupt Enable Register + AT91_REG PIO_IDR; // Interrupt Disable Register + AT91_REG PIO_IMR; // Interrupt Mask Register + AT91_REG PIO_ISR; // Interrupt Status Register + AT91_REG PIO_MDER; // Multi-driver Enable Register + AT91_REG PIO_MDDR; // Multi-driver Disable Register + AT91_REG PIO_MDSR; // Multi-driver Status Register +} AT91S_PIO, *AT91PS_PIO; + + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +typedef struct _AT91S_TC { + AT91_REG TC_CCR; // Channel Control Register + AT91_REG TC_CMR; // Channel Mode Register + AT91_REG Reserved0[2]; // + AT91_REG TC_CV; // Counter Value + AT91_REG TC_RA; // Register A + AT91_REG TC_RB; // Register B + AT91_REG TC_RC; // Register C + AT91_REG TC_SR; // Status Register + AT91_REG TC_IER; // Interrupt Enable Register + AT91_REG TC_IDR; // Interrupt Disable Register + AT91_REG TC_IMR; // Interrupt Mask Register +} AT91S_TC, *AT91PS_TC; + +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_NONE ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_RISING ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_FALLING ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_BOTH ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x1 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x2 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) +#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRCS ((unsigned int) 0x1 << 7) // (TC) External Trigger +#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +typedef struct _AT91S_TCB { + AT91S_TC TCB_TC0; // TC Channel 0 + AT91_REG Reserved0[4]; // + AT91S_TC TCB_TC1; // TC Channel 1 + AT91_REG Reserved1[4]; // + AT91S_TC TCB_TC2; // TC Channel 2 + AT91_REG Reserved2[4]; // + AT91_REG TCB_BCR; // TC Block Control Register + AT91_REG TCB_BMR; // TC Block Mode Register +} AT91S_TCB, *AT91PS_TCB; + +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S ((unsigned int) 0x1 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S ((unsigned int) 0x1 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S ((unsigned int) 0x1 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA2 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral Data Controller +// ***************************************************************************** +typedef struct _AT91S_PDC { + AT91_REG PDC_RPR; // Receive Pointer Register + AT91_REG PDC_RCR; // Receive Counter Register + AT91_REG PDC_TPR; // Transmit Pointer Register + AT91_REG PDC_TCR; // Transmit Counter Register +} AT91S_PDC, *AT91PS_PDC; + + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +typedef struct _AT91S_USART { + AT91_REG US_CR; // Control Register + AT91_REG US_MR; // Mode Register + AT91_REG US_IER; // Interrupt Enable Register + AT91_REG US_IDR; // Interrupt Disable Register + AT91_REG US_IMR; // Interrupt Mask Register + AT91_REG US_CSR; // Channel Status Register + AT91_REG US_RHR; // Receiver Holding Register + AT91_REG US_THR; // Transmitter Holding Register + AT91_REG US_BRGR; // Baud Rate Generator Register + AT91_REG US_RTOR; // Receiver Time-out Register + AT91_REG US_TTGR; // Transmitter Time-guard Register + AT91_REG Reserved0[1]; // + AT91_REG US_RPR; // Receive Pointer Register + AT91_REG US_RCR; // Receive Counter Register + AT91_REG US_TPR; // Transmit Pointer Register + AT91_REG US_TCR; // Transmit Counter Register +} AT91S_USART, *AT91PS_USART; + +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (USART) Reset Receiver +#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (USART) Reset Transmitter +#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (USART) Receiver Enable +#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (USART) Receiver Disable +#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (USART) Transmitter Enable +#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (USART) Transmitter Disable +#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (USART) Reset Status Bits +#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (USART) Parity type +#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (USART) Even Parity +#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (USART) Odd Parity +#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (USART) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (USART) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (USART) No Parity +#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (USART) Multi-drop mode +#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (USART) Channel Mode +#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (USART) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (USART) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (USART) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (USART) Remote Loopback: RXD pin is internally connected to TXD pin. +#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (USART) RXRDY Interrupt +#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (USART) TXRDY Interrupt +#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (USART) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (USART) End of Transmit Interrupt +#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (USART) Overrun Interrupt +#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (USART) Framing Error Interrupt +#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (USART) Parity Error Interrupt +#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (USART) TXEMPTY Interrupt +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Special Function Interface +// ***************************************************************************** +typedef struct _AT91S_SF { + AT91_REG SF_CIDR; // Chip ID Register + AT91_REG SF_EXID; // Chip ID Extension Register + AT91_REG SF_RSR; // Reset Status Register + AT91_REG SF_MMR; // Memory Mode Register + AT91_REG Reserved0[2]; // + AT91_REG SF_PMR; // Protect Mode Register +} AT91S_SF, *AT91PS_SF; + +// -------- SF_CIDR : (SF Offset: 0x0) Chip ID Register -------- +#define AT91C_SF_VERSION ((unsigned int) 0x1F << 0) // (SF) Version of the chip +#define AT91C_SF_BIT5 ((unsigned int) 0x1 << 5) // (SF) Hardwired at 0 +#define AT91C_SF_BIT6 ((unsigned int) 0x1 << 6) // (SF) Hardwired at 1 +#define AT91C_SF_BIT7 ((unsigned int) 0x1 << 7) // (SF) Hardwired at 0 +#define AT91C_SF_NVPSIZ ((unsigned int) 0xF << 8) // (SF) Nonvolatile Program Memory Size +#define AT91C_SF_NVPSIZ_NONE ((unsigned int) 0x0 << 8) // (SF) None +#define AT91C_SF_NVPSIZ_32K ((unsigned int) 0x3 << 8) // (SF) 32K Bytes +#define AT91C_SF_NVPSIZ_64K ((unsigned int) 0x5 << 8) // (SF) 64K Bytes +#define AT91C_SF_NVPSIZ_128K ((unsigned int) 0x7 << 8) // (SF) 128K Bytes +#define AT91C_SF_NVPSIZ_256K ((unsigned int) 0x11 << 8) // (SF) 256K Bytes +#define AT91C_SF_NVDSIZ ((unsigned int) 0xF << 12) // (SF) Nonvolatile Data Memory Size +#define AT91C_SF_NVDSIZ_NONE ((unsigned int) 0x0 << 12) // (SF) None +#define AT91C_SF_VDSIZ ((unsigned int) 0xF << 16) // (SF) Volatile Data Memory Size +#define AT91C_SF_VDSIZ_NONE ((unsigned int) 0x0 << 16) // (SF) None +#define AT91C_SF_VDSIZ_1K ((unsigned int) 0x3 << 16) // (SF) 1K Bytes +#define AT91C_SF_VDSIZ_2K ((unsigned int) 0x5 << 16) // (SF) 2K Bytes +#define AT91C_SF_VDSIZ_4K ((unsigned int) 0x7 << 16) // (SF) 4K Bytes +#define AT91C_SF_VDSIZ_8K ((unsigned int) 0x11 << 16) // (SF) 8K Bytes +#define AT91C_SF_ARCH ((unsigned int) 0xFF << 20) // (SF) Chip Architecture +#define AT91C_SF_ARCH_AT91x40 ((unsigned int) 0x28 << 20) // (SF) AT91x40yyy +#define AT91C_SF_ARCH_AT91x55 ((unsigned int) 0x37 << 20) // (SF) AT91x55yyy +#define AT91C_SF_ARCH_AT91x63 ((unsigned int) 0x3F << 20) // (SF) AT91x63yyy +#define AT91C_SF_NVPTYP ((unsigned int) 0x7 << 28) // (SF) Nonvolatile Program Memory Type +#define AT91C_SF_NVPTYP_NVPTYP_M ((unsigned int) 0x1 << 28) // (SF) 'M' Series or 'F' Series +#define AT91C_SF_NVPTYP_NVPTYP_R ((unsigned int) 0x4 << 28) // (SF) 'R' Series +#define AT91C_SF_EXT ((unsigned int) 0x1 << 31) // (SF) Extension Flag +// -------- SF_RSR : (SF Offset: 0x8) Reset Status Information -------- +#define AT91C_SF_RESET ((unsigned int) 0xFF << 0) // (SF) Cause of Reset +#define AT91C_SF_RESET_WD ((unsigned int) 0x35) // (SF) Internal Watchdog +#define AT91C_SF_RESET_EXT ((unsigned int) 0x6C) // (SF) External Pin +// -------- SF_MMR : (SF Offset: 0xc) Memory Mode Register -------- +#define AT91C_SF_RAMWU ((unsigned int) 0x1 << 0) // (SF) Internal Extended RAM Write Detection +// -------- SF_PMR : (SF Offset: 0x18) Protection Mode Register -------- +#define AT91C_SF_AIC ((unsigned int) 0x1 << 5) // (SF) AIC Protect Mode Enable +#define AT91C_SF_PMRKEY ((unsigned int) 0xFFFF << 16) // (SF) Protect Mode Register Key + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR External Bus Interface +// ***************************************************************************** +typedef struct _AT91S_EBI { + AT91_REG EBI_CSR[8]; // Chip-select Register + AT91_REG EBI_RCR; // Remap Control Register + AT91_REG EBI_MCR; // Memory Control Register +} AT91S_EBI, *AT91PS_EBI; + +// -------- EBI_CSR : (EBI Offset: 0x0) Chip Select Register -------- +#define AT91C_EBI_DBW ((unsigned int) 0x3 << 0) // (EBI) Data Bus Width +#define AT91C_EBI_DBW_16 ((unsigned int) 0x1) // (EBI) 16-bit data bus width +#define AT91C_EBI_DBW_8 ((unsigned int) 0x2) // (EBI) 8-bit data bus width +#define AT91C_EBI_NWS ((unsigned int) 0x7 << 2) // (EBI) Number of wait states +#define AT91C_EBI_NWS_1 ((unsigned int) 0x0 << 2) // (EBI) 1 wait state +#define AT91C_EBI_NWS_2 ((unsigned int) 0x1 << 2) // (EBI) 2 wait state +#define AT91C_EBI_NWS_3 ((unsigned int) 0x2 << 2) // (EBI) 3 wait state +#define AT91C_EBI_NWS_4 ((unsigned int) 0x3 << 2) // (EBI) 4 wait state +#define AT91C_EBI_NWS_5 ((unsigned int) 0x4 << 2) // (EBI) 5 wait state +#define AT91C_EBI_NWS_6 ((unsigned int) 0x5 << 2) // (EBI) 6 wait state +#define AT91C_EBI_NWS_7 ((unsigned int) 0x6 << 2) // (EBI) 7 wait state +#define AT91C_EBI_NWS_8 ((unsigned int) 0x7 << 2) // (EBI) 8 wait state +#define AT91C_EBI_WSE ((unsigned int) 0x1 << 5) // (EBI) Wait State Enable +#define AT91C_EBI_PAGES ((unsigned int) 0x3 << 7) // (EBI) Pages Size +#define AT91C_EBI_PAGES_1M ((unsigned int) 0x0 << 7) // (EBI) 1M Byte +#define AT91C_EBI_PAGES_4M ((unsigned int) 0x1 << 7) // (EBI) 4M Byte +#define AT91C_EBI_PAGES_16M ((unsigned int) 0x2 << 7) // (EBI) 16M Byte +#define AT91C_EBI_PAGES_64M ((unsigned int) 0x3 << 7) // (EBI) 64M Byte +#define AT91C_EBI_TDF ((unsigned int) 0x7 << 9) // (EBI) Data Float Output Time +#define AT91C_EBI_TDF_0 ((unsigned int) 0x0 << 9) // (EBI) 1 TDF +#define AT91C_EBI_TDF_1 ((unsigned int) 0x1 << 9) // (EBI) 2 TDF +#define AT91C_EBI_TDF_2 ((unsigned int) 0x2 << 9) // (EBI) 3 TDF +#define AT91C_EBI_TDF_3 ((unsigned int) 0x3 << 9) // (EBI) 4 TDF +#define AT91C_EBI_TDF_4 ((unsigned int) 0x4 << 9) // (EBI) 5 TDF +#define AT91C_EBI_TDF_5 ((unsigned int) 0x5 << 9) // (EBI) 6 TDF +#define AT91C_EBI_TDF_6 ((unsigned int) 0x6 << 9) // (EBI) 7 TDF +#define AT91C_EBI_TDF_7 ((unsigned int) 0x7 << 9) // (EBI) 8 TDF +#define AT91C_EBI_BAT ((unsigned int) 0x1 << 12) // (EBI) Byte Access Type +#define AT91C_EBI_CSEN ((unsigned int) 0x1 << 13) // (EBI) Chip Select Enable +#define AT91C_EBI_BA ((unsigned int) 0xFFF << 20) // (EBI) Base Address +// -------- EBI_RCR : (EBI Offset: 0x20) Remap Control Register -------- +#define AT91C_EBI_RCB ((unsigned int) 0x1 << 0) // (EBI) 0 = No effect. 1 = Cancels the remapping (performed at reset) of the page zero memory devices. +// -------- EBI_MCR : (EBI Offset: 0x24) Memory Control Register -------- +#define AT91C_EBI_ALE ((unsigned int) 0x7 << 0) // (EBI) Address Line Enable +#define AT91C_EBI_ALE_16M ((unsigned int) 0x0) // (EBI) Valid Address Bits = A20, A21, A22, A23 Max Addressable Space = 16M Bytes Valid Chip Select=None +#define AT91C_EBI_ALE_8M ((unsigned int) 0x4) // (EBI) Valid Address Bits = A20, A21, A22 Max Addressable Space = 8M Bytes Valid Chip Select = CS4 +#define AT91C_EBI_ALE_4M ((unsigned int) 0x5) // (EBI) Valid Address Bits = A20, A21 Max Addressable Space = 4M Bytes Valid Chip Select = CS4, CS5 +#define AT91C_EBI_ALE_2M ((unsigned int) 0x6) // (EBI) Valid Address Bits = A20 Max Addressable Space = 2M Bytes Valid Chip Select = CS4, CS5, CS6 +#define AT91C_EBI_ALE_1M ((unsigned int) 0x7) // (EBI) Valid Address Bits = None Max Addressable Space = 1M Byte Valid Chip Select = CS4, CS5, CS6, CS7 +#define AT91C_EBI_DRP ((unsigned int) 0x1 << 4) // (EBI) + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91R40008 +// ***************************************************************************** +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector egister +#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode egister +#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register +#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register +#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command egister +// ========== Register definition for WD peripheral ========== +#define AT91C_WD_SR ((AT91_REG *) 0xFFFF800C) // (WD) Status Register +#define AT91C_WD_CMR ((AT91_REG *) 0xFFFF8004) // (WD) Clock Mode Register +#define AT91C_WD_CR ((AT91_REG *) 0xFFFF8008) // (WD) Control Register +#define AT91C_WD_OMR ((AT91_REG *) 0xFFFF8000) // (WD) Overflow Mode Register +// ========== Register definition for PS peripheral ========== +#define AT91C_PS_PCDR ((AT91_REG *) 0xFFFF4008) // (PS) Peripheral Clock Disable Register +#define AT91C_PS_CR ((AT91_REG *) 0xFFFF4000) // (PS) Control Register +#define AT91C_PS_PCSR ((AT91_REG *) 0xFFFF400C) // (PS) Peripheral Clock Status Register +#define AT91C_PS_PCER ((AT91_REG *) 0xFFFF4004) // (PS) Peripheral Clock Enable Register +// ========== Register definition for PIO peripheral ========== +#define AT91C_PIO_MDSR ((AT91_REG *) 0xFFFF0058) // (PIO) Multi-driver Status Register +#define AT91C_PIO_IFSR ((AT91_REG *) 0xFFFF0028) // (PIO) Input Filter Status Register +#define AT91C_PIO_IFER ((AT91_REG *) 0xFFFF0020) // (PIO) Input Filter Enable Register +#define AT91C_PIO_OSR ((AT91_REG *) 0xFFFF0018) // (PIO) Output Status Register +#define AT91C_PIO_OER ((AT91_REG *) 0xFFFF0010) // (PIO) Output Enable Register +#define AT91C_PIO_PSR ((AT91_REG *) 0xFFFF0008) // (PIO) PIO Status Register +#define AT91C_PIO_PDSR ((AT91_REG *) 0xFFFF003C) // (PIO) Pin Data Status Register +#define AT91C_PIO_CODR ((AT91_REG *) 0xFFFF0034) // (PIO) Clear Output Data Register +#define AT91C_PIO_IFDR ((AT91_REG *) 0xFFFF0024) // (PIO) Input Filter Disable Register +#define AT91C_PIO_MDER ((AT91_REG *) 0xFFFF0050) // (PIO) Multi-driver Enable Register +#define AT91C_PIO_IMR ((AT91_REG *) 0xFFFF0048) // (PIO) Interrupt Mask Register +#define AT91C_PIO_IER ((AT91_REG *) 0xFFFF0040) // (PIO) Interrupt Enable Register +#define AT91C_PIO_ODSR ((AT91_REG *) 0xFFFF0038) // (PIO) Output Data Status Register +#define AT91C_PIO_SODR ((AT91_REG *) 0xFFFF0030) // (PIO) Set Output Data Register +#define AT91C_PIO_PER ((AT91_REG *) 0xFFFF0000) // (PIO) PIO Enable Register +#define AT91C_PIO_MDDR ((AT91_REG *) 0xFFFF0054) // (PIO) Multi-driver Disable Register +#define AT91C_PIO_ISR ((AT91_REG *) 0xFFFF004C) // (PIO) Interrupt Status Register +#define AT91C_PIO_IDR ((AT91_REG *) 0xFFFF0044) // (PIO) Interrupt Disable Register +#define AT91C_PIO_PDR ((AT91_REG *) 0xFFFF0004) // (PIO) PIO Disable Register +#define AT91C_PIO_ODR ((AT91_REG *) 0xFFFF0014) // (PIO) Output Disable Registerr +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFE00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_SR ((AT91_REG *) 0xFFFE00A0) // (TC2) Status Register +#define AT91C_TC2_RB ((AT91_REG *) 0xFFFE0098) // (TC2) Register B +#define AT91C_TC2_CV ((AT91_REG *) 0xFFFE0090) // (TC2) Counter Value +#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFE0080) // (TC2) Channel Control Register +#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFE00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_IER ((AT91_REG *) 0xFFFE00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_RC ((AT91_REG *) 0xFFFE009C) // (TC2) Register C +#define AT91C_TC2_RA ((AT91_REG *) 0xFFFE0094) // (TC2) Register A +#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFE0084) // (TC2) Channel Mode Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFE0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR ((AT91_REG *) 0xFFFE0060) // (TC1) Status Register +#define AT91C_TC1_RB ((AT91_REG *) 0xFFFE0058) // (TC1) Register B +#define AT91C_TC1_CV ((AT91_REG *) 0xFFFE0050) // (TC1) Counter Value +#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFE0040) // (TC1) Channel Control Register +#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFE006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_IER ((AT91_REG *) 0xFFFE0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_RC ((AT91_REG *) 0xFFFE005C) // (TC1) Register C +#define AT91C_TC1_RA ((AT91_REG *) 0xFFFE0054) // (TC1) Register A +#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFE0044) // (TC1) Channel Mode Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFE0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_SR ((AT91_REG *) 0xFFFE0020) // (TC0) Status Register +#define AT91C_TC0_RB ((AT91_REG *) 0xFFFE0018) // (TC0) Register B +#define AT91C_TC0_CV ((AT91_REG *) 0xFFFE0010) // (TC0) Counter Value +#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFE0000) // (TC0) Channel Control Register +#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFE002C) // (TC0) Interrupt Mask Register +#define AT91C_TC0_IER ((AT91_REG *) 0xFFFE0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RC ((AT91_REG *) 0xFFFE001C) // (TC0) Register C +#define AT91C_TC0_RA ((AT91_REG *) 0xFFFE0014) // (TC0) Register A +#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFE0004) // (TC0) Channel Mode Register +// ========== Register definition for TCB0 peripheral ========== +#define AT91C_TCB0_BCR ((AT91_REG *) 0xFFFE00C0) // (TCB0) TC Block Control Register +#define AT91C_TCB0_BMR ((AT91_REG *) 0xFFFE00C4) // (TCB0) TC Block Mode Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4038) // (PDC_US1) Transmit Pointer Register +#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4030) // (PDC_US1) Receive Pointer Register +#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC403C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4034) // (PDC_US1) Receive Counter Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFCC024) // (US1) Receiver Time-out Register +#define AT91C_US1_THR ((AT91_REG *) 0xFFFCC01C) // (US1) Transmitter Holding Register +#define AT91C_US1_CSR ((AT91_REG *) 0xFFFCC014) // (US1) Channel Status Register +#define AT91C_US1_IDR ((AT91_REG *) 0xFFFCC00C) // (US1) Interrupt Disable Register +#define AT91C_US1_MR ((AT91_REG *) 0xFFFCC004) // (US1) Mode Register +#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFCC028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFCC020) // (US1) Baud Rate Generator Register +#define AT91C_US1_RHR ((AT91_REG *) 0xFFFCC018) // (US1) Receiver Holding Register +#define AT91C_US1_IMR ((AT91_REG *) 0xFFFCC010) // (US1) Interrupt Mask Register +#define AT91C_US1_IER ((AT91_REG *) 0xFFFCC008) // (US1) Interrupt Enable Register +#define AT91C_US1_CR ((AT91_REG *) 0xFFFCC000) // (US1) Control Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0038) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0030) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC003C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0034) // (PDC_US0) Receive Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFD0024) // (US0) Receiver Time-out Register +#define AT91C_US0_THR ((AT91_REG *) 0xFFFD001C) // (US0) Transmitter Holding Register +#define AT91C_US0_CSR ((AT91_REG *) 0xFFFD0014) // (US0) Channel Status Register +#define AT91C_US0_IDR ((AT91_REG *) 0xFFFD000C) // (US0) Interrupt Disable Register +#define AT91C_US0_MR ((AT91_REG *) 0xFFFD0004) // (US0) Mode Register +#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFD0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFD0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_RHR ((AT91_REG *) 0xFFFD0018) // (US0) Receiver Holding Register +#define AT91C_US0_IMR ((AT91_REG *) 0xFFFD0010) // (US0) Interrupt Mask Register +#define AT91C_US0_IER ((AT91_REG *) 0xFFFD0008) // (US0) Interrupt Enable Register +#define AT91C_US0_CR ((AT91_REG *) 0xFFFD0000) // (US0) Control Register +// ========== Register definition for SF peripheral ========== +#define AT91C_SF_PMR ((AT91_REG *) 0xFFF00018) // (SF) Protect Mode Register +#define AT91C_SF_RSR ((AT91_REG *) 0xFFF00008) // (SF) Reset Status Register +#define AT91C_SF_CIDR ((AT91_REG *) 0xFFF00000) // (SF) Chip ID Register +#define AT91C_SF_MMR ((AT91_REG *) 0xFFF0000C) // (SF) Memory Mode Register +#define AT91C_SF_EXID ((AT91_REG *) 0xFFF00004) // (SF) Chip ID Extension Register +// ========== Register definition for EBI peripheral ========== +#define AT91C_EBI_RCR ((AT91_REG *) 0xFFE00020) // (EBI) Remap Control Register +#define AT91C_EBI_CSR ((AT91_REG *) 0xFFE00000) // (EBI) Chip-select Register +#define AT91C_EBI_MCR ((AT91_REG *) 0xFFE00024) // (EBI) Memory Control Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91R40008 +// ***************************************************************************** +#define AT91C_PIO_P0 ((unsigned int) 1 << 0) // Pin Controlled by P0 +#define AT91C_P0_TCLK0 ((unsigned int) AT91C_PIO_P0) // Timer 0 Clock signal +#define AT91C_PIO_P1 ((unsigned int) 1 << 1) // Pin Controlled by P1 +#define AT91C_P1_TIOA0 ((unsigned int) AT91C_PIO_P1) // Timer 0 Signal A +#define AT91C_PIO_P10 ((unsigned int) 1 << 10) // Pin Controlled by P10 +#define AT91C_P10_IRQ1 ((unsigned int) AT91C_PIO_P10) // External Interrupt 1 +#define AT91C_PIO_P11 ((unsigned int) 1 << 11) // Pin Controlled by P11 +#define AT91C_P11_IRQ2 ((unsigned int) AT91C_PIO_P11) // External Interrupt 2 +#define AT91C_PIO_P12 ((unsigned int) 1 << 12) // Pin Controlled by P12 +#define AT91C_P12_FIQ ((unsigned int) AT91C_PIO_P12) // Fast External Interrupt +#define AT91C_PIO_P13 ((unsigned int) 1 << 13) // Pin Controlled by P13 +#define AT91C_P13_SCK0 ((unsigned int) AT91C_PIO_P13) // USART 0 Serial Clock +#define AT91C_PIO_P14 ((unsigned int) 1 << 14) // Pin Controlled by P14 +#define AT91C_P14_TXD0 ((unsigned int) AT91C_PIO_P14) // USART 0 Transmit Data +#define AT91C_PIO_P15 ((unsigned int) 1 << 15) // Pin Controlled by P15 +#define AT91C_P15_RXD0 ((unsigned int) AT91C_PIO_P15) // USART 0 Receive Data +#define AT91C_PIO_P16 ((unsigned int) 1 << 16) // Pin Controlled by P16 +#define AT91C_PIO_P17 ((unsigned int) 1 << 17) // Pin Controlled by P17 +#define AT91C_PIO_P18 ((unsigned int) 1 << 18) // Pin Controlled by P18 +#define AT91C_PIO_P19 ((unsigned int) 1 << 19) // Pin Controlled by P19 +#define AT91C_PIO_P2 ((unsigned int) 1 << 2) // Pin Controlled by P2 +#define AT91C_P2_TIOB0 ((unsigned int) AT91C_PIO_P2) // Timer 0 Signal B +#define AT91C_PIO_P20 ((unsigned int) 1 << 20) // Pin Controlled by P20 +#define AT91C_P20_SCK1 ((unsigned int) AT91C_PIO_P20) // USART 1 Serial Clock +#define AT91C_PIO_P21 ((unsigned int) 1 << 21) // Pin Controlled by P21 +#define AT91C_P21_TXD1 ((unsigned int) AT91C_PIO_P21) // USART 1 Transmit Data +#define AT91C_P21_NTRI ((unsigned int) AT91C_PIO_P21) // Tri-state Mode +#define AT91C_PIO_P22 ((unsigned int) 1 << 22) // Pin Controlled by P22 +#define AT91C_P22_RXD1 ((unsigned int) AT91C_PIO_P22) // USART 1 Receive Data +#define AT91C_PIO_P23 ((unsigned int) 1 << 23) // Pin Controlled by P23 +#define AT91C_PIO_P24 ((unsigned int) 1 << 24) // Pin Controlled by P24 +#define AT91C_P24_BMS ((unsigned int) AT91C_PIO_P24) // Boot Mode Select +#define AT91C_PIO_P25 ((unsigned int) 1 << 25) // Pin Controlled by P25 +#define AT91C_P25_MCKO ((unsigned int) AT91C_PIO_P25) // Master Clock Out +#define AT91C_PIO_P26 ((unsigned int) 1 << 26) // Pin Controlled by P26 +#define AT91C_P26_NCS2 ((unsigned int) AT91C_PIO_P26) // Chip Select 2 +#define AT91C_PIO_P27 ((unsigned int) 1 << 27) // Pin Controlled by P27 +#define AT91C_P27_NCS3 ((unsigned int) AT91C_PIO_P27) // Chip Select 3 +#define AT91C_PIO_P28 ((unsigned int) 1 << 28) // Pin Controlled by P28 +#define AT91C_P28_A20 ((unsigned int) AT91C_PIO_P28) // Address line A20 +#define AT91C_P28_NCS7 ((unsigned int) AT91C_PIO_P28) // Chip Select 7 +#define AT91C_PIO_P29 ((unsigned int) 1 << 29) // Pin Controlled by P29 +#define AT91C_P29_A21 ((unsigned int) AT91C_PIO_P29) // Address line A21 +#define AT91C_P29_NCS6 ((unsigned int) AT91C_PIO_P29) // Chip Select 6 +#define AT91C_PIO_P3 ((unsigned int) 1 << 3) // Pin Controlled by P3 +#define AT91C_P3_TCLK1 ((unsigned int) AT91C_PIO_P3) // Timer 1 Clock signal +#define AT91C_PIO_P30 ((unsigned int) 1 << 30) // Pin Controlled by P30 +#define AT91C_P30_A22 ((unsigned int) AT91C_PIO_P30) // Address line A22 +#define AT91C_P30_NCS5 ((unsigned int) AT91C_PIO_P30) // Chip Select 5 +#define AT91C_PIO_P31 ((unsigned int) 1 << 31) // Pin Controlled by P31 +#define AT91C_P31_A23 ((unsigned int) AT91C_PIO_P31) // Address line A23 +#define AT91C_P31_NCS4 ((unsigned int) AT91C_PIO_P31) // Chip Select 4 +#define AT91C_PIO_P4 ((unsigned int) 1 << 4) // Pin Controlled by P4 +#define AT91C_P4_TIOA1 ((unsigned int) AT91C_PIO_P4) // Timer 1 Signal A +#define AT91C_PIO_P5 ((unsigned int) 1 << 5) // Pin Controlled by P5 +#define AT91C_P5_TIOB1 ((unsigned int) AT91C_PIO_P5) // Timer 1 Signal B +#define AT91C_PIO_P6 ((unsigned int) 1 << 6) // Pin Controlled by P6 +#define AT91C_P6_TCLK2 ((unsigned int) AT91C_PIO_P6) // Timer 2 Clock signal +#define AT91C_PIO_P7 ((unsigned int) 1 << 7) // Pin Controlled by P7 +#define AT91C_P7_TIOA2 ((unsigned int) AT91C_PIO_P7) // Timer 2 Signal A +#define AT91C_PIO_P8 ((unsigned int) 1 << 8) // Pin Controlled by P8 +#define AT91C_P8_TIOB2 ((unsigned int) AT91C_PIO_P8) // Timer 2 Signal B +#define AT91C_PIO_P9 ((unsigned int) 1 << 9) // Pin Controlled by P9 +#define AT91C_P9_IRQ0 ((unsigned int) AT91C_PIO_P9) // External Interrupt 0 + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91R40008 +// ***************************************************************************** +#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ((unsigned int) 1) // SWI +#define AT91C_ID_US0 ((unsigned int) 2) // USART 0 +#define AT91C_ID_US1 ((unsigned int) 3) // USART 1 +#define AT91C_ID_TC0 ((unsigned int) 4) // Timer Counter 0 +#define AT91C_ID_TC1 ((unsigned int) 5) // Timer Counter 1 +#define AT91C_ID_TC2 ((unsigned int) 6) // Timer Counter 2 +#define AT91C_ID_WD ((unsigned int) 7) // Watchdog Timer +#define AT91C_ID_PIO ((unsigned int) 8) // Parallel IO Controller +#define AT91C_ID_IRQ0 ((unsigned int) 16) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 ((unsigned int) 17) // Advanced Interrupt Controller (IRQ1) +#define AT91C_ID_IRQ2 ((unsigned int) 18) // Advanced Interrupt Controller (IRQ2) + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91R40008 +// ***************************************************************************** +#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_WD ((AT91PS_WD) 0xFFFF8000) // (WD) Base Address +#define AT91C_BASE_PS ((AT91PS_PS) 0xFFFF4000) // (PS) Base Address +#define AT91C_BASE_PIO ((AT91PS_PIO) 0xFFFF0000) // (PIO) Base Address +#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFE0080) // (TC2) Base Address +#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFE0040) // (TC1) Base Address +#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFE0000) // (TC0) Base Address +#define AT91C_BASE_TCB0 ((AT91PS_TCB) 0xFFFE0000) // (TCB0) Base Address +#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4030) // (PDC_US1) Base Address +#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFCC000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0030) // (PDC_US0) Base Address +#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFD0000) // (US0) Base Address +#define AT91C_BASE_SF ((AT91PS_SF) 0xFFF00000) // (SF) Base Address +#define AT91C_BASE_EBI ((AT91PS_EBI) 0xFFE00000) // (EBI) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91R40008 +// ***************************************************************************** +#define AT91C_SRAM_BEFORE_REMAP ((char *) 0x00300000) // Internal SRAM before remap base address +#define AT91C_SRAM_BEFORE_REMAP_SIZE ((unsigned int) 0x00040000) // Internal SRAM before remap size in byte (256 Kbyte) +#define AT91C_SRAM_AFTER_REMAP ((char *) 0x00000000) // Internal SRAM after remap base address +#define AT91C_SRAM_AFTER_REMAP_SIZE ((unsigned int) 0x00040000) // Internal SRAM after remap size in byte (256 Kbyte) + +#endif diff --git a/20080212/Demo/ARM7_AT91FR40008_GCC/ATEB40x.cfg b/20080212/Demo/ARM7_AT91FR40008_GCC/ATEB40x.cfg new file mode 100644 index 000000000..756339f29 --- /dev/null +++ b/20080212/Demo/ARM7_AT91FR40008_GCC/ATEB40x.cfg @@ -0,0 +1,24 @@ +[SETUP] +CpuVendor=Atmel +CpuChip=AT91R40807 +FlashVendor=Atmel +FlashChip=AT49BV/F1614A +RamAddress=$00000000 +RamSupport=1 +FlashAddress=$01000000 +FlashWidth=16 +FlashChipsPerSector=1 +LittleEndian=0 +SectStart=0 +SectEnd=38 +AutoErase=0 +AutoVerify=1 +CpuEndian=LITTLE +SimCount=3 +MemoryCount=0 +ProgramFile=E:\temp\embesttest\Demo\ARM7_AT91R40008_GCC_Embest\rtosdemo.hex +UploadFile=c:\EB40_Lower.bin +Format=Intel Hex +Sim3=EBI_RCR:$00000001 +Sim2=EBI_CSR1:$02002122 +Sim1=EBI_CSR0:$01002539 diff --git a/20080212/Demo/ARM7_AT91FR40008_GCC/FreeRTOSConfig.h b/20080212/Demo/ARM7_AT91FR40008_GCC/FreeRTOSConfig.h new file mode 100644 index 000000000..28abb82fa --- /dev/null +++ b/20080212/Demo/ARM7_AT91FR40008_GCC/FreeRTOSConfig.h @@ -0,0 +1,89 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include + +#define configFLASH_SPEED_NSEC 100 /* External flash access speed (for ROM builds) */ + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 66000000 ) /* = 66.000MHz clk gen */ +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 128 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 25 * 1024 ) ) +#define configMAX_TASK_NAME_LEN ( 16 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/ARM7_AT91FR40008_GCC/Makefile b/20080212/Demo/ARM7_AT91FR40008_GCC/Makefile new file mode 100644 index 000000000..abac760b4 --- /dev/null +++ b/20080212/Demo/ARM7_AT91FR40008_GCC/Makefile @@ -0,0 +1,99 @@ +# FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. +# +# This file is part of the FreeRTOS.org distribution. +# +# FreeRTOS.org is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# FreeRTOS.org is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with FreeRTOS.org; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +# +# A special exception to the GPL can be applied should you wish to distribute +# a combined work that includes FreeRTOS.org, without being obliged to provide +# the source code for any proprietary components. See the licensing section +# of http://www.FreeRTOS.org for full details of how and when the exception +# can be applied. +# +# *************************************************************************** +# See http://www.FreeRTOS.org for documentation, latest information, license +# and contact details. Please ensure to read the configuration and relevant +# port sections of the online documentation. +# *************************************************************************** + +CC=arm-elf-gcc +OBJCOPY=arm-elf-objcopy +ARCH=arm-elf-ar +CRT0=boot.s + +# +# CFLAGS common to both the THUMB and ARM mode builds +# +CFLAGS=-Wall -D $(RUN_MODE) -D GCC_AT91FR40008 -I. -I../../Source/include \ + -I../Common/include $(DEBUG) -mcpu=arm7tdmi -T$(LDSCRIPT) \ + -Wcast-align $(OPTIM) -fomit-frame-pointer + +ifeq ($(USE_THUMB_MODE),YES) + CFLAGS += -mthumb-interwork -D THUMB_INTERWORK + THUMB_FLAGS=-mthumb +endif + + +LINKER_FLAGS=-Xlinker -ortosdemo.elf -Xlinker -M -Xlinker -Map=rtosdemo.map + +# +# Source files that can be built to THUMB mode. +# +THUMB_SRC = \ +main.c \ +serial/serial.c \ +ParTest/ParTest.c \ +../Common/Minimal/integer.c \ +../Common/Minimal/flash.c \ +../Common/Minimal/PollQ.c \ +../Common/Minimal/comtest.c \ +../Common/Minimal/flop.c \ +../Common/Minimal/semtest.c \ +../Common/Minimal/dynamic.c \ +../Common/Minimal/BlockQ.c \ +../../Source/tasks.c \ +../../Source/queue.c \ +../../Source/list.c \ +../../Source/portable/MemMang/heap_2.c \ +../../Source/portable/GCC/ARM7_AT91FR40008/port.c + +# +# Source files that must be built to ARM mode. +# +ARM_SRC = \ +../../Source/portable/GCC/ARM7_AT91FR40008/portISR.c \ +serial/serialISR.c + +# +# Define all object files. +# +ARM_OBJ = $(ARM_SRC:.c=.o) +THUMB_OBJ = $(THUMB_SRC:.c=.o) + +rtosdemo.hex : rtosdemo.elf + $(OBJCOPY) rtosdemo.elf -O ihex rtosdemo.hex + +rtosdemo.elf : $(ARM_OBJ) $(THUMB_OBJ) $(CRT0) Makefile + $(CC) $(CFLAGS) $(ARM_OBJ) $(THUMB_OBJ) -nostartfiles $(CRT0) $(LINKER_FLAGS) + +$(THUMB_OBJ) : %.o : %.c $(LDSCRIPT) Makefile + $(CC) -c $(THUMB_FLAGS) $(CFLAGS) $< -o $@ + +$(ARM_OBJ) : %.o : %.c $(LDSCRIPT) Makefile + $(CC) -c $(CFLAGS) $< -o $@ + +clean : + touch Makefile + diff --git a/20080212/Demo/ARM7_AT91FR40008_GCC/ParTest/ParTest.c b/20080212/Demo/ARM7_AT91FR40008_GCC/ParTest/ParTest.c new file mode 100644 index 000000000..d5b810281 --- /dev/null +++ b/20080212/Demo/ARM7_AT91FR40008_GCC/ParTest/ParTest.c @@ -0,0 +1,130 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "portable.h" + +/* Demo app includes. */ +#include "partest.h" + +/* Hardware specific definitions. */ +#include "AT91R40008.h" +#include "pio.h" +#include "aic.h" + +#define partstNUM_LEDS ( 8 ) +#define partstALL_OUTPUTS_OFF ( ( unsigned portLONG ) ~(0xFFFFFFFF << partstNUM_LEDS) ) + +static unsigned portLONG ulLEDReg; + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +static void SetLeds (unsigned int leds) +{ +unsigned portLONG ulPIOSetReg, ulPIOClearReg; + + /* LEDs are grouped in different port bits: P3-P6 and P16-P19. + A port bit set to '0' turns an LED on, '1' turns it off. */ + + ulPIOSetReg = ( (leds & 0xF) << 16 ) | ( (leds & 0xF0) >> 1 ); + ulPIOClearReg = (~ulPIOSetReg) & 0x000F0078; + + AT91C_BASE_PIO->PIO_SODR = ulPIOSetReg; + AT91C_BASE_PIO->PIO_CODR = ulPIOClearReg; +} +/*-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ + /* This is performed from main() as the io bits are shared with other setup + functions. Ensure the outputs are off to start. */ + ulLEDReg = partstALL_OUTPUTS_OFF; + + /* Enable clock to PIO... */ + AT91C_BASE_PS->PS_PCER = AT91C_PS_PIO; + + /* Enable all 8 LEDs and the four switches to be controlled by PIO... */ + AT91C_BASE_PIO->PIO_PER = P3 | P4 | P5 | P6 | P16 | P17 | P18 | P19 | P1 | P2 | P9 | P12; + + /* Configure all LED PIO lines for output... */ + AT91C_BASE_PIO->PIO_OER = P3 | P4 | P5 | P6 | P16 | P17 | P18 | P19; + + /* Configure all switch PIO lines for input... */ + AT91C_BASE_PIO->PIO_ODR = P1 | P2 | P9 | P12; + + /* Set initial state of LEDs. */ + SetLeds( ulLEDReg ); +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ + /* Switch an LED on or off as requested. */ + if (uxLED < partstNUM_LEDS) + { + if( xValue ) + { + ulLEDReg &= ~(1 << uxLED); + } + else + { + ulLEDReg |= (1 << uxLED); + } + + SetLeds( ulLEDReg ); + } +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ + /* Toggle the state of the requested LED. */ + if (uxLED < partstNUM_LEDS) + { + ulLEDReg ^= ( 1 << uxLED ); + SetLeds( ulLEDReg ); + } +} + diff --git a/20080212/Demo/ARM7_AT91FR40008_GCC/aic.h b/20080212/Demo/ARM7_AT91FR40008_GCC/aic.h new file mode 100644 index 000000000..82df09078 --- /dev/null +++ b/20080212/Demo/ARM7_AT91FR40008_GCC/aic.h @@ -0,0 +1,81 @@ +//*---------------------------------------------------------------------------- +//* ATMEL Microcontroller Software Support - ROUSSET - +//*---------------------------------------------------------------------------- +//* The software is delivered "AS IS" without warranty or condition of any +//* kind, either express, implied or statutory. This includes without +//* limitation any warranty or condition with respect to merchantability or +//* fitness for any particular purpose, or against the infringements of +//* intellectual property rights of others. +//*---------------------------------------------------------------------------- +//* File Name : aic.h +//* Object : Advanced Interrupt Controller Definition File. +//* +//* 1.0 01/04/00 JCZ : Creation +//*---------------------------------------------------------------------------- + +#ifndef aic_h +#define aic_h + +//#include "periph/stdc/std_c.h" + +/*-----------------------------------------*/ +/* AIC User Interface Structure Definition */ +/*-----------------------------------------*/ + +typedef struct +{ + at91_reg AIC_SMR[32] ; /* Source Mode Register */ + at91_reg AIC_SVR[32] ; /* Source Vector Register */ + at91_reg AIC_IVR ; /* IRQ Vector Register */ + at91_reg AIC_FVR ; /* FIQ Vector Register */ + at91_reg AIC_ISR ; /* Interrupt Status Register */ + at91_reg AIC_IPR ; /* Interrupt Pending Register */ + at91_reg AIC_IMR ; /* Interrupt Mask Register */ + at91_reg AIC_CISR ; /* Core Interrupt Status Register */ + at91_reg reserved0 ; + at91_reg reserved1 ; + at91_reg AIC_IECR ; /* Interrupt Enable Command Register */ + at91_reg AIC_IDCR ; /* Interrupt Disable Command Register */ + at91_reg AIC_ICCR ; /* Interrupt Clear Command Register */ + at91_reg AIC_ISCR ; /* Interrupt Set Command Register */ + at91_reg AIC_EOICR ; /* End of Interrupt Command Register */ + at91_reg AIC_SPU ; /* Spurious Vector Register */ +} StructAIC ; + +/*--------------------------------------------*/ +/* AIC_SMR[]: Interrupt Source Mode Registers */ +/*--------------------------------------------*/ + +#define AIC_PRIOR 0x07 /* Priority */ + +#define AIC_SRCTYPE 0x60 /* Source Type Definition */ + +/* Internal Interrupts */ +#define AIC_SRCTYPE_INT_LEVEL_SENSITIVE 0x00 /* Level Sensitive */ +#define AIC_SRCTYPE_INT_EDGE_TRIGGERED 0x20 /* Edge Triggered */ + +/* External Interrupts */ +#define AIC_SRCTYPE_EXT_LOW_LEVEL 0x00 /* Low Level */ +#define AIC_SRCTYPE_EXT_NEGATIVE_EDGE 0x20 /* Negative Edge */ +#define AIC_SRCTYPE_EXT_HIGH_LEVEL 0x40 /* High Level */ +#define AIC_SRCTYPE_EXT_POSITIVE_EDGE 0x60 /* Positive Edge */ + +/*------------------------------------*/ +/* AIC_ISR: Interrupt Status Register */ +/*------------------------------------*/ + +#define AIC_IRQID 0x1F /* Current source interrupt */ + +/*------------------------------------------*/ +/* AIC_CISR: Interrupt Core Status Register */ +/*------------------------------------------*/ + +#define AIC_NFIQ 0x01 /* Core FIQ Status */ +#define AIC_NIRQ 0x02 /* Core IRQ Status */ + +/*-------------------------------*/ +/* Advanced Interrupt Controller */ +/*-------------------------------*/ +#define AIC_BASE ((StructAIC *)0xFFFFF000) + +#endif /* aic_h */ diff --git a/20080212/Demo/ARM7_AT91FR40008_GCC/atmel-ram.ld b/20080212/Demo/ARM7_AT91FR40008_GCC/atmel-ram.ld new file mode 100644 index 000000000..692202661 --- /dev/null +++ b/20080212/Demo/ARM7_AT91FR40008_GCC/atmel-ram.ld @@ -0,0 +1,48 @@ +MEMORY +{ + ram : ORIGIN = 0x00000000, LENGTH = 256K +} + +__stack_end__ = 0x00000000 + 256K - 4; + +SECTIONS +{ + . = 0; + startup : { *(.startup)} >ram + + prog : + { + *(.text) + *(.rodata) + *(.rodata*) + *(.glue_7) + *(.glue_7t) + } >ram + + __end_of_text__ = .; + + .data : + { + __data_beg__ = .; + __data_beg_src__ = __end_of_text__; + *(.data) + __data_end__ = .; + } >ram + + .bss : + { + __bss_beg__ = .; + *(.bss) + } >ram + + /* Align here to ensure that the .bss section occupies space up to + _end. Align after .bss to ensure correct alignment even if the + .bss section disappears because there are no input sections. */ + . = ALIGN(32 / 8); +} + . = ALIGN(32 / 8); + _end = .; + _bss_end__ = . ; __bss_end__ = . ; __end__ = . ; + PROVIDE (end = .); + + diff --git a/20080212/Demo/ARM7_AT91FR40008_GCC/atmel-rom.ld b/20080212/Demo/ARM7_AT91FR40008_GCC/atmel-rom.ld new file mode 100644 index 000000000..35578fd96 --- /dev/null +++ b/20080212/Demo/ARM7_AT91FR40008_GCC/atmel-rom.ld @@ -0,0 +1,49 @@ +MEMORY +{ + flash : ORIGIN = 0x00000000, LENGTH = 2048K + ram : ORIGIN = 0x00300000, LENGTH = 256K +} + +__stack_end__ = 0x00300000 + 256K - 4; + +SECTIONS +{ + . = 0; + startup : { *(.startup)} >flash + + prog : + { + *(.text) + *(.rodata) + *(.rodata*) + *(.glue_7) + *(.glue_7t) + } >flash + + __end_of_text__ = .; + + .data : + { + __data_beg__ = .; + __data_beg_src__ = __end_of_text__; + *(.data) + __data_end__ = .; + } >ram AT>flash + + .bss : + { + __bss_beg__ = .; + *(.bss) + } >ram + + /* Align here to ensure that the .bss section occupies space up to + _end. Align after .bss to ensure correct alignment even if the + .bss section disappears because there are no input sections. */ + . = ALIGN(32 / 8); +} + . = ALIGN(32 / 8); + _end = .; + _bss_end__ = . ; __bss_end__ = . ; __end__ = . ; + PROVIDE (end = .); + + diff --git a/20080212/Demo/ARM7_AT91FR40008_GCC/boot.s b/20080212/Demo/ARM7_AT91FR40008_GCC/boot.s new file mode 100644 index 000000000..5947d158f --- /dev/null +++ b/20080212/Demo/ARM7_AT91FR40008_GCC/boot.s @@ -0,0 +1,157 @@ + /* Sample initialization file */ + + .extern main + .extern exit + + .text + .code 32 + + + .align 0 + + .extern __bss_beg__ + .extern __bss_end__ + .extern __stack_end__ + .extern __data_beg__ + .extern __data_end__ + .extern __data+beg_src__ + + .global start + .global endless_loop + + /* Stack Sizes */ + .set UND_STACK_SIZE, 0x00000004 + .set ABT_STACK_SIZE, 0x00000004 + .set FIQ_STACK_SIZE, 0x00000004 + .set IRQ_STACK_SIZE, 0X00000400 + .set SVC_STACK_SIZE, 0x00000400 + + /* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */ + .set MODE_USR, 0x10 /* User Mode */ + .set MODE_FIQ, 0x11 /* FIQ Mode */ + .set MODE_IRQ, 0x12 /* IRQ Mode */ + .set MODE_SVC, 0x13 /* Supervisor Mode */ + .set MODE_ABT, 0x17 /* Abort Mode */ + .set MODE_UND, 0x1B /* Undefined Mode */ + .set MODE_SYS, 0x1F /* System Mode */ + + .equ I_BIT, 0x80 /* when I bit is set, IRQ is disabled */ + .equ F_BIT, 0x40 /* when F bit is set, FIQ is disabled */ + + +start: +_start: +_mainCRTStartup: + + /* Setup a stack for each mode - note that this only sets up a usable stack + for system/user, SWI and IRQ modes. Also each mode is setup with + interrupts initially disabled. */ + ldr r0, .LC6 + msr CPSR_c, #MODE_UND|I_BIT|F_BIT /* Undefined Instruction Mode */ + mov sp, r0 + sub r0, r0, #UND_STACK_SIZE + msr CPSR_c, #MODE_ABT|I_BIT|F_BIT /* Abort Mode */ + mov sp, r0 + sub r0, r0, #ABT_STACK_SIZE + msr CPSR_c, #MODE_FIQ|I_BIT|F_BIT /* FIQ Mode */ + mov sp, r0 + sub r0, r0, #FIQ_STACK_SIZE + msr CPSR_c, #MODE_IRQ|I_BIT|F_BIT /* IRQ Mode */ + mov sp, r0 + sub r0, r0, #IRQ_STACK_SIZE + msr CPSR_c, #MODE_SVC|I_BIT|F_BIT /* Supervisor Mode */ + mov sp, r0 + sub r0, r0, #SVC_STACK_SIZE + msr CPSR_c, #MODE_SYS|I_BIT|F_BIT /* System Mode */ + mov sp, r0 + + /* We want to start in supervisor mode. Operation will switch to system + mode when the first task starts. */ + msr CPSR_c, #MODE_SVC|I_BIT|F_BIT + + /* Clear BSS. */ + + mov a2, #0 /* Fill value */ + mov fp, a2 /* Null frame pointer */ + mov r7, a2 /* Null frame pointer for Thumb */ + + ldr r1, .LC1 /* Start of memory block */ + ldr r3, .LC2 /* End of memory block */ + subs r3, r3, r1 /* Length of block */ + beq .end_clear_loop + mov r2, #0 + +.clear_loop: + strb r2, [r1], #1 + subs r3, r3, #1 + bgt .clear_loop + +.end_clear_loop: + + /* Initialise data. */ + + ldr r1, .LC3 /* Start of memory block */ + ldr r2, .LC4 /* End of memory block */ + ldr r3, .LC5 + subs r3, r3, r1 /* Length of block */ + beq .end_set_loop + +.set_loop: + ldrb r4, [r2], #1 + strb r4, [r1], #1 + subs r3, r3, #1 + bgt .set_loop + +.end_set_loop: + + mov r0, #0 /* no arguments */ + mov r1, #0 /* no argv either */ + + bl main + +endless_loop: + b endless_loop + + + .align 0 + + .LC1: + .word __bss_beg__ + .LC2: + .word __bss_end__ + .LC3: + .word __data_beg__ + .LC4: + .word __data_beg_src__ + .LC5: + .word __data_end__ + .LC6: + .word __stack_end__ + + + /* Setup vector table. Note that undf, pabt, dabt, fiq just execute + a null loop. */ + +.section .startup,"ax" + .code 32 + .align 0 + + b _start /* reset - _start */ + ldr pc, _undf /* undefined - _undf */ + ldr pc, _swi /* SWI - _swi */ + ldr pc, _pabt /* program abort - _pabt */ + ldr pc, _dabt /* data abort - _dabt */ + nop /* reserved */ + ldr pc, [pc,#-0xF20] /* IRQ - read the AIC */ + ldr pc, _fiq /* FIQ - _fiq */ + +_undf: .word __undf /* undefined */ +_swi: .word vPortYieldProcessor /* SWI */ +_pabt: .word __pabt /* program abort */ +_dabt: .word __dabt /* data abort */ +_fiq: .word __fiq /* FIQ */ + +__undf: b . /* undefined */ +__pabt: b . /* program abort */ +__dabt: b . /* data abort */ +__fiq: b . /* FIQ */ diff --git a/20080212/Demo/ARM7_AT91FR40008_GCC/ebi.h b/20080212/Demo/ARM7_AT91FR40008_GCC/ebi.h new file mode 100644 index 000000000..ffa1a5500 --- /dev/null +++ b/20080212/Demo/ARM7_AT91FR40008_GCC/ebi.h @@ -0,0 +1,121 @@ +//*----------------------------------------------------------------------------- +//* ATMEL Microcontroller Software Support - ROUSSET - +//*----------------------------------------------------------------------------- +//* The software is delivered "AS IS" without warranty or condition of any +//* kind, either express, implied or statutory. This includes without +//* limitation any warranty or condition with respect to merchantability or +//* fitness for any particular purpose, or against the infringements of +//* intellectual property rights of others. +//*----------------------------------------------------------------------------- +//* File Name : ebi.h +//* Object : External Bus Interface Definition File +//* Translator : ARM Software Development Toolkit V2.11a +//* +//* 1.0 03/11/97 JCZ : Creation +//* 2.0 21/10/98 JCZ : Clean up +//*----------------------------------------------------------------------------- + +#ifndef ebi_h +#define ebi_h + +/*----------------------------------------*/ +/* Memory Controller Interface Definition */ +/*----------------------------------------*/ + +typedef struct +{ + at91_reg EBI_CSR[8] ; /* Chip Select Register */ + at91_reg EBI_RCR ; /* Remap Control Register */ + at91_reg EBI_MCR ; /* Memory Control Register */ +} StructEBI ; + +/*-----------------------*/ +/* Chip Select Registers */ +/*-----------------------*/ + +/* Data Bus Width */ +#define DataBus16 (1<<0) +#define DataBus8 (2<<0) +#define DBW (3<<0) + +/* Number of Wait States */ +#define B_NWS 2 +#define WaitState1 (0< +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo application includes. */ +#include "partest.h" +#include "flash.h" +#include "integer.h" +#include "PollQ.h" +#include "comtest2.h" +#include "semtest.h" +#include "flop.h" +#include "dynamic.h" +#include "BlockQ.h" +#include "serial.h" + +/* Hardware specific definitions. */ +#include "aic.h" +#include "ebi.h" + +/*-----------------------------------------------------------*/ + +/* Constants for the ComTest tasks. */ +#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 115200 ) +#define mainCOM_TEST_LED ( 5 ) + +/* Priorities for the demo application tasks. */ +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) + +/* The rate at which the on board LED will toggle when there is/is not an +error. */ +#define mainNO_ERROR_FLASH_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS ) +#define mainERROR_FLASH_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS ) +#define mainON_BOARD_LED_BIT ( ( unsigned portLONG ) 7 ) + +/* Constants used by the vMemCheckTask() task. */ +#define mainCOUNT_INITIAL_VALUE ( ( unsigned portLONG ) 0 ) +#define mainNO_TASK ( 0 ) + +/* The size of the memory blocks allocated by the vMemCheckTask() task. */ +#define mainMEM_CHECK_SIZE_1 ( ( size_t ) 51 ) +#define mainMEM_CHECK_SIZE_2 ( ( size_t ) 52 ) +#define mainMEM_CHECK_SIZE_3 ( ( size_t ) 151 ) + +#define MAX_WAIT_STATES 8 +static const unsigned portLONG ululCSRWaitValues[ MAX_WAIT_STATES + 1 ] = +{ + WaitState1,/* There is no "zero wait state" value, so use one wait state */ + WaitState1, + WaitState2, + WaitState3, + WaitState4, + WaitState5, + WaitState6, + WaitState7, + WaitState8 +}; +/*-----------------------------------------------------------*/ + +/* + * Checks that all the demo application tasks are still executing without error + * - as described at the top of the file. + */ +static portLONG prvCheckOtherTasksAreStillRunning( unsigned portLONG ulMemCheckTaskCount ); + +/* + * The task that executes at the highest priority and calls + * prvCheckOtherTasksAreStillRunning(). See the description at the top + * of the file. + */ +static void vErrorChecks( void *pvParameters ); + +/* + * Dynamically created and deleted during each cycle of the vErrorChecks() + * task. This is done to check the operation of the memory allocator. + * See the top of vErrorChecks for more details. + */ +static void vMemCheckTask( void *pvParameters ); + +/* + * Configure the processor for use with the Olimex demo board. This includes + * setup for the I/O, system clock, and access timings. + */ +static void prvSetupHardware( void ); + +/*-----------------------------------------------------------*/ + +/* + * Starts all the other tasks, then starts the scheduler. + */ +int main( void ) +{ + /* Setup the hardware for use with the Olimex demo board. */ + prvSetupHardware(); + + /* Start the demo/test application tasks. */ + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); + vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartMathTasks( tskIDLE_PRIORITY ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartDynamicPriorityTasks(); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + + /* Start the check task - which is defined in this file. */ + xTaskCreate( vErrorChecks, ( signed portCHAR * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Now all the tasks have been started - start the scheduler. + + NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. + The processor MUST be in supervisor mode when vTaskStartScheduler is + called. The demo applications included in the FreeRTOS.org download switch + to supervisor mode prior to main being called. If you are not using one of + these demo application projects then ensure Supervisor mode is used here. */ + vTaskStartScheduler(); + + /* Should never reach here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +static void vErrorChecks( void *pvParameters ) +{ +portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD; +unsigned portLONG ulMemCheckTaskRunningCount; +xTaskHandle xCreatedTask; + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. If an error is detected then the delay period + is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so + the on board LED flash rate will increase. + + In addition to the standard tests the memory allocator is tested through + the dynamic creation and deletion of a task each cycle. Each time the + task is created memory must be allocated for its stack. When the task is + deleted this memory is returned to the heap. If the task cannot be created + then it is likely that the memory allocation failed. */ + + for( ;; ) + { + /* Reset xCreatedTask. This is modified by the task about to be + created so we can tell if it is executing correctly or not. */ + xCreatedTask = mainNO_TASK; + + /* Dynamically create a task - passing ulMemCheckTaskRunningCount as a + parameter. */ + ulMemCheckTaskRunningCount = mainCOUNT_INITIAL_VALUE; + if( xTaskCreate( vMemCheckTask, ( signed portCHAR * ) "MEM_CHECK", configMINIMAL_STACK_SIZE, ( void * ) &ulMemCheckTaskRunningCount, tskIDLE_PRIORITY, &xCreatedTask ) != pdPASS ) + { + /* Could not create the task - we have probably run out of heap. */ + xDelayPeriod = mainERROR_FLASH_PERIOD; + } + + /* Delay until it is time to execute again. */ + vTaskDelay( xDelayPeriod ); + + /* Delete the dynamically created task. */ + if( xCreatedTask != mainNO_TASK ) + { + vTaskDelete( xCreatedTask ); + } + + /* Check all the standard demo application tasks are executing without + error. ulMemCheckTaskRunningCount is checked to ensure it was + modified by the task just deleted. */ + if( prvCheckOtherTasksAreStillRunning( ulMemCheckTaskRunningCount ) != pdPASS ) + { + /* An error has been detected in one of the tasks - flash faster. */ + xDelayPeriod = mainERROR_FLASH_PERIOD; + } + + /* The toggle rate of the LED depends on how long this task delays for. + An error reduces the delay period and so increases the toggle rate. */ + vParTestToggleLED( mainON_BOARD_LED_BIT ); + } +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ +portLONG lCount; + + #ifdef RUN_FROM_ROM + { + portFLOAT nsecsPerClockTick; + portLONG lNumWaitStates; + unsigned portLONG ulCSRWaitValue; + + /* We are compiling to run from ROM (either on-chip or off-chip flash). + Leave the RAM/flash mapped the way they are on reset + (flash @ 0x00000000, RAM @ 0x00300000), and set up the + proper flash wait states (starts out at the maximum number + of wait states on reset, so we should be able to reduce it). + Most of this code will probably get removed by the compiler + if optimization is enabled, since these calculations are + based on constants. But the compiler should still produce + a correct wait state register value. */ + nsecsPerClockTick = ( portFLOAT ) 1000000000 / configCPU_CLOCK_HZ; + lNumWaitStates = ( portLONG )( ( configFLASH_SPEED_NSEC / nsecsPerClockTick ) + 0.5 ) - 1; + + if( lNumWaitStates < 0 ) + { + lNumWaitStates = 0; + } + + if( lNumWaitStates > MAX_WAIT_STATES ) + { + lNumWaitStates = MAX_WAIT_STATES; + } + + ulCSRWaitValue = ululCSRWaitValues[ lNumWaitStates ]; + ulCSRWaitValue = WaitState5; + + AT91C_BASE_EBI->EBI_CSR[ 0 ] = ulCSRWaitValue | DataBus16 | WaitStateEnable + | PageSize1M | tDF_0cycle + | ByteWriteAccessType | CSEnable + | 0x00000000 /* Base Address */; + } + #else /* else we are compiling to run from on-chip RAM */ + { + /* If compiling to run from RAM, we expect the on-chip RAM to already + be mapped at 0x00000000. This is typically done with an initialization + script for the JTAG emulator you are using to download and run the + demo application. So there is nothing to do here in this case. */ + } + #endif + + /* Disable all interrupts at the AIC level initially... */ + AT91C_BASE_AIC->AIC_IDCR = 0xFFFFFFFF; + + /* Set all SVR and SMR entries to default values (start with a clean slate)... */ + for( lCount = 0; lCount < 32; lCount++ ) + { + AT91C_BASE_AIC->AIC_SVR[ lCount ] = (unsigned long) 0; + AT91C_BASE_AIC->AIC_SMR[ lCount ] = AIC_SRCTYPE_INT_EDGE_TRIGGERED; + } + + /* Disable clocks to all peripherals initially... */ + AT91C_BASE_PS->PS_PCDR = 0xFFFFFFFF; + + /* Clear all interrupts at the AIC level initially... */ + AT91C_BASE_AIC->AIC_ICCR = 0xFFFFFFFF; + + /* Perform 8 "End Of Interrupt" cmds to make sure AIC will not Lock out + nIRQ */ + for( lCount = 0; lCount < 8; lCount++ ) + { + AT91C_BASE_AIC->AIC_EOICR = 0; + } + + /* Initialise LED outputs. */ + vParTestInitialise(); +} +/*-----------------------------------------------------------*/ + +static portLONG prvCheckOtherTasksAreStillRunning( unsigned portLONG ulMemCheckTaskCount ) +{ +portLONG lReturn = ( portLONG ) pdPASS; + + /* Check all the demo tasks (other than the flash tasks) to ensure + that they are all still running, and that none of them have detected + an error. */ + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreMathsTaskStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( ulMemCheckTaskCount == mainCOUNT_INITIAL_VALUE ) + { + /* The vMemCheckTask did not increment the counter - it must + have failed. */ + lReturn = ( portLONG ) pdFAIL; + } + + return lReturn; +} +/*-----------------------------------------------------------*/ + +static void vMemCheckTask( void *pvParameters ) +{ +unsigned portLONG *pulMemCheckTaskRunningCounter; +void *pvMem1, *pvMem2, *pvMem3; +static portLONG lErrorOccurred = pdFALSE; + + /* This task is dynamically created then deleted during each cycle of the + vErrorChecks task to check the operation of the memory allocator. Each time + the task is created memory is allocated for the stack and TCB. Each time + the task is deleted this memory is returned to the heap. This task itself + exercises the allocator by allocating and freeing blocks. + + The task executes at the idle priority so does not require a delay. + + pulMemCheckTaskRunningCounter is incremented each cycle to indicate to the + vErrorChecks() task that this task is still executing without error. */ + + pulMemCheckTaskRunningCounter = ( unsigned portLONG * ) pvParameters; + + for( ;; ) + { + if( lErrorOccurred == pdFALSE ) + { + /* We have never seen an error so increment the counter. */ + ( *pulMemCheckTaskRunningCounter )++; + } + else + { + /* There has been an error so reset the counter so the check task + can tell that an error occurred. */ + *pulMemCheckTaskRunningCounter = mainCOUNT_INITIAL_VALUE; + } + + /* Allocate some memory - just to give the allocator some extra + exercise. This has to be in a critical section to ensure the + task does not get deleted while it has memory allocated. */ + vTaskSuspendAll(); + { + pvMem1 = pvPortMalloc( mainMEM_CHECK_SIZE_1 ); + if( pvMem1 == NULL ) + { + lErrorOccurred = pdTRUE; + } + else + { + memset( pvMem1, 0xaa, mainMEM_CHECK_SIZE_1 ); + vPortFree( pvMem1 ); + } + } + xTaskResumeAll(); + + /* Again - with a different size block. */ + vTaskSuspendAll(); + { + pvMem2 = pvPortMalloc( mainMEM_CHECK_SIZE_2 ); + if( pvMem2 == NULL ) + { + lErrorOccurred = pdTRUE; + } + else + { + memset( pvMem2, 0xaa, mainMEM_CHECK_SIZE_2 ); + vPortFree( pvMem2 ); + } + } + xTaskResumeAll(); + + /* Again - with a different size block. */ + vTaskSuspendAll(); + { + pvMem3 = pvPortMalloc( mainMEM_CHECK_SIZE_3 ); + if( pvMem3 == NULL ) + { + lErrorOccurred = pdTRUE; + } + else + { + memset( pvMem3, 0xaa, mainMEM_CHECK_SIZE_3 ); + vPortFree( pvMem3 ); + } + } + xTaskResumeAll(); + } +} + diff --git a/20080212/Demo/ARM7_AT91FR40008_GCC/pio.h b/20080212/Demo/ARM7_AT91FR40008_GCC/pio.h new file mode 100644 index 000000000..d786b883a --- /dev/null +++ b/20080212/Demo/ARM7_AT91FR40008_GCC/pio.h @@ -0,0 +1,149 @@ +//*--------------------------------------------------------------------------- +//* ATMEL Microcontroller Software Support - ROUSSET - +//*--------------------------------------------------------------------------- +//* The software is delivered "AS IS" without warranty or condition of any +//* kind, either express, implied or statutory. This includes without +//* limitation any warranty or condition with respect to merchantability or +//* fitness for any particular purpose, or against the infringements of +//* intellectual property rights of others. +//*----------------------------------------------------------------------------- +//* File Name : pio.h +//* Object : Parallel I/O Definition File +//* Translator : ARM Software Development Toolkit V2.11a +//* +//* 1.0 20/10/97 JCZ : Creation +//* 2.0 21/10/98 JCZ : Clean up +//*--------------------------------------------------------------------------- + +#ifndef pio_h +#define pio_h + +/*---------------------------------------------*/ +/* Parallel I/O Interface Structure Definition */ +/*---------------------------------------------*/ + +typedef struct +{ + at91_reg PIO_PER ; /* PIO Enable Register */ + at91_reg PIO_PDR ; /* PIO Disable Register */ + at91_reg PIO_PSR ; /* PIO Status Register */ + at91_reg Reserved0 ; + at91_reg PIO_OER ; /* Output Enable Register */ + at91_reg PIO_ODR ; /* Output Disable Register */ + at91_reg PIO_OSR ; /* Output Status Register */ + at91_reg Reserved1 ; + at91_reg PIO_IFER ; /* Input Filter Enable Register */ + at91_reg PIO_IFDR ; /* Input Filter Disable Register */ + at91_reg PIO_IFSR ; /* Input Filter Status Register */ + at91_reg Reserved2 ; + at91_reg PIO_SODR ; /* Set Output Data Register */ + at91_reg PIO_CODR ; /* Clear Output Data Register */ + at91_reg PIO_ODSR ; /* Output Data Status Register */ + at91_reg PIO_PDSR ; /* Pin Data Status Register */ + at91_reg PIO_IER ; /* Interrupt Enable Register */ + at91_reg PIO_IDR ; /* Interrupt Disable Register */ + at91_reg PIO_IMR ; /* Interrupt Mask Register */ + at91_reg PIO_ISR ; /* Interrupt Status Register */ +} StructPIO ; + +/*-----------------------------*/ +/* PIO Handler type definition */ +/*-----------------------------*/ + +//typedef void (*TypePIOHandler) ( StructPIO *pio_pt, u_int pio_mask ) ; + +/*--------------------------------*/ +/* Device Dependancies Definition */ +/*--------------------------------*/ + +/* Number of PIO Controller */ +#define NB_PIO_CTRL 1 +/* Base Address */ +#define PIO_BASE ((StructPIO *) 0xFFFF0000 ) +/* Number of PIO Lines */ +#define NB_PIO 32 + +/* Parallel I/O Bits Definition */ +#define P0 (1<<0) +#define P1 (1<<1) +#define P2 (1<<2) +#define P3 (1<<3) +#define P4 (1<<4) +#define P5 (1<<5) +#define P6 (1<<6) +#define P7 (1<<7) +#define P8 (1<<8) +#define P9 (1<<9) +#define P10 (1<<10) +#define P11 (1<<11) +#define P12 (1<<12) +#define P13 (1<<13) +#define P14 (1<<14) +#define P15 (1<<15) +#define P16 (1<<16) +#define P17 (1<<17) +#define P18 (1<<18) +#define P19 (1<<19) +#define P20 (1<<20) +#define P21 (1<<21) +#define P22 (1<<22) +#define P23 (1<<23) +#define P24 (1<<24) +#define P25 (1<<25) +#define P26 (1<<26) +#define P27 (1<<27) +#define P28 (1<<28) +#define P29 (1<<29) +#define P30 (1<<30) +#define P31 (1<<31) + +/* PIO Multiplexing Definition */ + +/* There is only one PIO Controller */ +#define PIO_CTRL 0 + +#define PIO_TC0 PIO_CTRL +#define TCLK0 P0 +#define TIOA0 P1 +#define TIOB0 P2 +#define PIN_TC0 (TIOA0|TIOB0|TCLK0) + +#define PIO_TC1 PIO_CTRL +#define TCLK1 P3 +#define TIOA1 P4 +#define TIOB1 P5 +#define PIN_TC1 (TIOA1|TIOB1|TCLK1) + +#define PIO_TC2 PIO_CTRL +#define TCLK2 P6 +#define TIOA2 P7 +#define TIOB2 P8 +#define PIN_TC2 (TIOA2|TIOB2|TCLK2) + +#define PIO_EXT_IRQ PIO_CTRL +#define PIN_IRQ0 P9 +#define PIN_IRQ1 P10 +#define PIN_IRQ2 P11 +#define PIN_FIQ P12 + +#define PIO_USART0 PIO_CTRL +#define SCK0 P13 +#define TXD0 P14 +#define RXD0 P15 +#define PIN_USART0 (SCK0|TXD0|RXD0) + +#define PIO_USART1 PIO_CTRL +#define SCK1 P20 +#define TXD1 P21 +#define RXD1 P22 +#define PIN_USART1 (SCK1|TXD1|RXD1) + +#define MCKO P25 +#define CS2 P26 +#define CS3 P27 +#define CS4 P31 +#define CS5 P30 +#define CS6 P29 +#define CS7 P28 + +#endif /* pio_h */ diff --git a/20080212/Demo/ARM7_AT91FR40008_GCC/ram_arm.bat b/20080212/Demo/ARM7_AT91FR40008_GCC/ram_arm.bat new file mode 100644 index 000000000..355bb5ec2 --- /dev/null +++ b/20080212/Demo/ARM7_AT91FR40008_GCC/ram_arm.bat @@ -0,0 +1,6 @@ +set USE_THUMB_MODE=NO +set DEBUG=-g +set OPTIM=-O0 +set RUN_MODE=RUN_FROM_RAM +set LDSCRIPT=atmel-ram.ld +make diff --git a/20080212/Demo/ARM7_AT91FR40008_GCC/ram_thumb.bat b/20080212/Demo/ARM7_AT91FR40008_GCC/ram_thumb.bat new file mode 100644 index 000000000..4d5b84593 --- /dev/null +++ b/20080212/Demo/ARM7_AT91FR40008_GCC/ram_thumb.bat @@ -0,0 +1,6 @@ +set USE_THUMB_MODE=YES +set DEBUG=-g +set OPTIM=-O0 +set RUN_MODE=RUN_FROM_RAM +set LDSCRIPT=atmel-ram.ld +make diff --git a/20080212/Demo/ARM7_AT91FR40008_GCC/rom_arm.bat b/20080212/Demo/ARM7_AT91FR40008_GCC/rom_arm.bat new file mode 100644 index 000000000..0499bdbc9 --- /dev/null +++ b/20080212/Demo/ARM7_AT91FR40008_GCC/rom_arm.bat @@ -0,0 +1,6 @@ +set USE_THUMB_MODE=NO +set DEBUG=-g +set OPTIM=-O2 +set RUN_MODE=RUN_FROM_ROM +set LDSCRIPT=atmel-rom.ld +make diff --git a/20080212/Demo/ARM7_AT91FR40008_GCC/rom_thumb.bat b/20080212/Demo/ARM7_AT91FR40008_GCC/rom_thumb.bat new file mode 100644 index 000000000..9c36b6cfe --- /dev/null +++ b/20080212/Demo/ARM7_AT91FR40008_GCC/rom_thumb.bat @@ -0,0 +1,6 @@ +set USE_THUMB_MODE=YES +set DEBUG=-g +set OPTIM=-O2 +set RUN_MODE=RUN_FROM_ROM +set LDSCRIPT=atmel-rom.ld +make diff --git a/20080212/Demo/ARM7_AT91FR40008_GCC/serial/serial.c b/20080212/Demo/ARM7_AT91FR40008_GCC/serial/serial.c new file mode 100644 index 000000000..29fb20ec6 --- /dev/null +++ b/20080212/Demo/ARM7_AT91FR40008_GCC/serial/serial.c @@ -0,0 +1,238 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR USART0. + + This file contains all the serial port components that can be compiled to + either ARM or THUMB mode. Components that must be compiled to ARM mode are + contained in serialISR.c. +*/ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "queue.h" +#include "task.h" + +/* Demo application includes. */ +#include "serial.h" +#include "AT91R40008.h" +#include "usart.h" +#include "pio.h" +#include "aic.h" + +/*-----------------------------------------------------------*/ + +/* Constants to setup and access the UART. */ +#define portUSART0_AIC_CHANNEL ( ( unsigned portLONG ) 2 ) + +#define serINVALID_QUEUE ( ( xQueueHandle ) 0 ) +#define serHANDLE ( ( xComPortHandle ) 1 ) +#define serNO_BLOCK ( ( portTickType ) 0 ) + +/*-----------------------------------------------------------*/ + +/* Queues used to hold received characters, and characters waiting to be +transmitted. */ +static xQueueHandle xRxedChars; +static xQueueHandle xCharsForTx; + +/*-----------------------------------------------------------*/ + +/* + * The queues are created in serialISR.c as they are used from the ISR. + * Obtain references to the queues and THRE Empty flag. + */ +extern void vSerialISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars, xQueueHandle *pxCharsForTx ); + +/*-----------------------------------------------------------*/ + +xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) +{ +unsigned portLONG ulSpeed; +unsigned portLONG ulCD; +xComPortHandle xReturn = serHANDLE; +extern void ( vUART_ISR_Wrapper )( void ); + + /* The queues are used in the serial ISR routine, so are created from + serialISR.c (which is always compiled to ARM mode. */ + vSerialISRCreateQueues( uxQueueLength, &xRxedChars, &xCharsForTx ); + + if( + ( xRxedChars != serINVALID_QUEUE ) && + ( xCharsForTx != serINVALID_QUEUE ) && + ( ulWantedBaud != ( unsigned portLONG ) 0 ) + ) + { + portENTER_CRITICAL(); + { + /* Enable clock to USART0... */ + AT91C_BASE_PS->PS_PCER = AT91C_PS_US0; + + /* Disable all USART0 interrupt sources to begin... */ + AT91C_BASE_US0->US_IDR = 0xFFFFFFFF; + + /* Reset various status bits (just in case)... */ + AT91C_BASE_US0->US_CR = US_RSTSTA; + + AT91C_BASE_PIO->PIO_PDR = TXD0 | RXD0; /* Enable RXD and TXD pins */ + AT91C_BASE_US0->US_CR = US_RSTRX | US_RSTTX | US_RXDIS | US_TXDIS; + + /* Clear Transmit and Receive Counters */ + AT91C_BASE_US0->US_RCR = 0; + AT91C_BASE_US0->US_TCR = 0; + + /* Input clock to baud rate generator is MCK */ + ulSpeed = configCPU_CLOCK_HZ * 10; + ulSpeed = ulSpeed / 16; + ulSpeed = ulSpeed / ulWantedBaud; + + /* compute the error */ + ulCD = ulSpeed / 10; + if ((ulSpeed - (ulCD * 10)) >= 5) + ulCD++; + + /* Define the baud rate divisor register */ + AT91C_BASE_US0->US_BRGR = ulCD; + + /* Define the USART mode */ + AT91C_BASE_US0->US_MR = US_CLKS_MCK | US_CHRL_8 | US_PAR_NO | US_NBSTOP_1 | US_CHMODE_NORMAL; + + /* Write the Timeguard Register */ + AT91C_BASE_US0->US_TTGR = 0; + + /* Setup the interrupt for USART0. + + Store interrupt handler function address in USART0 vector register... */ + AT91C_BASE_AIC->AIC_SVR[ portUSART0_AIC_CHANNEL ] = (unsigned long)vUART_ISR_Wrapper; + + /* USART0 interrupt level-sensitive, priority 1... */ + AT91C_BASE_AIC->AIC_SMR[ portUSART0_AIC_CHANNEL ] = AIC_SRCTYPE_INT_LEVEL_SENSITIVE | 1; + + /* Clear some pending USART0 interrupts (just in case)... */ + AT91C_BASE_US0->US_CR = US_RSTSTA; + + /* Enable USART0 interrupt sources (but not Tx for now)... */ + AT91C_BASE_US0->US_IER = US_RXRDY; + + /* Enable USART0 interrupts in the AIC... */ + AT91C_BASE_AIC->AIC_IECR = ( 1 << portUSART0_AIC_CHANNEL ); + + /* Enable receiver and transmitter... */ + AT91C_BASE_US0->US_CR = US_RXEN | US_TXEN; + } + portEXIT_CRITICAL(); + } + else + { + xReturn = ( xComPortHandle ) 0; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) +{ + /* The port handle is not required as this driver only supports UART0. */ + ( void ) pxPort; + + /* Get the next character from the buffer. Return false if no characters + are available, or arrive before xBlockTime expires. */ + if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) + { + return pdTRUE; + } + else + { + return pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength ) +{ +signed portCHAR *pxNext; + + /* NOTE: This implementation does not handle the queue being full as no + block time is used! */ + + /* The port handle is not required as this driver only supports UART0. */ + ( void ) pxPort; + + /* Send each character in the string, one at a time. */ + pxNext = ( signed portCHAR * ) pcString; + while( *pxNext ) + { + xSerialPutChar( pxPort, *pxNext, serNO_BLOCK ); + pxNext++; + } +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) +{ + /* Place the character in the queue of characters to be transmitted. */ + if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) + { + return pdFAIL; + } + + /* Turn on the Tx interrupt so the ISR will remove the character from the + queue and send it. This does not need to be in a critical section as + if the interrupt has already removed the character the next interrupt + will simply turn off the Tx interrupt again. */ + AT91C_BASE_US0->US_IER = US_TXRDY; + + return pdPASS; +} +/*-----------------------------------------------------------*/ + +void vSerialClose( xComPortHandle xPort ) +{ + /* Not supported as not required by the demo application. */ +} +/*-----------------------------------------------------------*/ + diff --git a/20080212/Demo/ARM7_AT91FR40008_GCC/serial/serialISR.c b/20080212/Demo/ARM7_AT91FR40008_GCC/serial/serialISR.c new file mode 100644 index 000000000..ab051bc62 --- /dev/null +++ b/20080212/Demo/ARM7_AT91FR40008_GCC/serial/serialISR.c @@ -0,0 +1,162 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + + +/* + BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR USART0. + + This file contains all the serial port components that must be compiled + to ARM mode. The components that can be compiled to either ARM or THUMB + mode are contained in serial.c. + +*/ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "queue.h" +#include "task.h" + +/* Demo application includes. */ +#include "serial.h" +#include "AT91R40008.h" +#include "usart.h" + +/*-----------------------------------------------------------*/ + +/* Constant to access the AIC. */ +#define serCLEAR_AIC_INTERRUPT ( ( unsigned portLONG ) 0 ) + +/* Constants to determine the ISR source. */ +#define serSOURCE_THRE ( ( unsigned portCHAR ) 0x02 ) +#define serSOURCE_RX_TIMEOUT ( ( unsigned portCHAR ) 0x0c ) +#define serSOURCE_ERROR ( ( unsigned portCHAR ) 0x06 ) +#define serSOURCE_RX ( ( unsigned portCHAR ) 0x04 ) +#define serINTERRUPT_SOURCE_MASK ( ( unsigned portLONG ) (US_RXRDY | US_TXRDY | US_RXBRK | US_OVRE | US_FRAME | US_PARE) ) + +/* Queues used to hold received characters, and characters waiting to be +transmitted. */ +static xQueueHandle xRxedChars; +static xQueueHandle xCharsForTx; + +/*-----------------------------------------------------------*/ + +/* UART0 interrupt service routine. This can cause a context switch so MUST +be declared "naked". */ +void vUART_ISR_Wrapper( void ) __attribute__ ((naked)); + +/* The ISR function that actually performs the work. This must be separate +from the wrapper to ensure the correct stack frame is set up. */ +void vUART_ISR_Handler( void ); + +/*-----------------------------------------------------------*/ +void vSerialISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars, xQueueHandle *pxCharsForTx ) +{ + /* Create the queues used to hold Rx and Tx characters. */ + xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + + /* Pass back a reference to the queues so the serial API file can + post/receive characters. */ + *pxRxedChars = xRxedChars; + *pxCharsForTx = xCharsForTx; +} +/*-----------------------------------------------------------*/ + +void vUART_ISR_Wrapper( void ) +{ + /* Save the context of the interrupted task. */ + portSAVE_CONTEXT(); + + /* Call the handler. This must be a separate function to ensure the + stack frame is correctly set up. */ + vUART_ISR_Handler(); + + /* Restore the context of whichever task will run next. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +void vUART_ISR_Handler( void ) +{ +/* Now we can declare the local variables. These must be static. */ +signed portCHAR cChar; +portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByRx = pdFALSE; +unsigned portLONG ulStatus; + + /* What caused the interrupt? */ + ulStatus = AT91C_BASE_US0->US_CSR & AT91C_BASE_US0->US_IMR; + + if (ulStatus & US_TXRDY) + { + /* The interrupt was caused by the THR becoming empty. Are there any + more characters to transmit? */ + if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE ) + { + /* A character was retrieved from the queue so can be sent to the + THR now. */ + AT91C_BASE_US0->US_THR = cChar; + } + else + { + /* Queue empty, nothing to send so turn off the Tx interrupt. */ + AT91C_BASE_US0->US_IDR = US_TXRDY; + } + } + + if (ulStatus & US_RXRDY) + { + /* The interrupt was caused by the receiver getting data. */ + cChar = AT91C_BASE_US0->US_RHR; + + if (xQueueSendFromISR(xRxedChars, &cChar, pdFALSE)) + { + xTaskWokenByRx = pdTRUE; + } + } + + /* Acknowledge the interrupt at AIC level... */ + AT91C_BASE_AIC->AIC_EOICR = serCLEAR_AIC_INTERRUPT; + + /* If an event caused a task to unblock then we call "Yield from ISR" to + ensure that the unblocked task is the task that executes when the interrupt + completes if the unblocked task has a priority higher than the interrupted + task. */ + if( xTaskWokenByTx || xTaskWokenByRx ) + { + portYIELD_FROM_ISR(); + } +} +/*-----------------------------------------------------------*/ + diff --git a/20080212/Demo/ARM7_AT91FR40008_GCC/tc.h b/20080212/Demo/ARM7_AT91FR40008_GCC/tc.h new file mode 100644 index 000000000..518220e47 --- /dev/null +++ b/20080212/Demo/ARM7_AT91FR40008_GCC/tc.h @@ -0,0 +1,301 @@ +//*---------------------------------------------------------------------------- +//* ATMEL Microcontroller Software Support - ROUSSET - +//*---------------------------------------------------------------------------- +//* The software is delivered "AS IS" without warranty or condition of any +//* kind, either express, implied or statutory. This includes without +//* limitation any warranty or condition with respect to merchantability or +//* fitness for any particular purpose, or against the infringements of +//* intellectual property rights of others. +//*----------------------------------------------------------------------------- +//* File Name : tc.h +//* Object : Timer Counter Header File +//* +//* 1.0 01/04/00 JCZ : Creation +//* 1.0 01/09/00 JPP : modification TC_BEEVT, TC_BEEVT_SET_OUTPUT, +//* TC_BEEVT_CLEAR_OUTPUT, TC_BEEVT_TOGGLE_OUTPUT +//*----------------------------------------------------------------------------- + +#ifndef tc_h +#define tc_h + +//#include "periph/stdc/std_c.h" +//#include "periph/pio/lib_pio.h" + +/*-------------------------------------------*/ +/* Timer User Interface Structure Definition */ +/*-------------------------------------------*/ + +typedef struct +{ + at91_reg TC_CCR ; /* Control Register */ + at91_reg TC_CMR ; /* Mode Register */ + at91_reg Reserved0 ; + at91_reg Reserved1 ; + at91_reg TC_CV ; /* Counter value */ + at91_reg TC_RA ; /* Register A */ + at91_reg TC_RB ; /* Register B */ + at91_reg TC_RC ; /* Register C */ + at91_reg TC_SR ; /* Status Register */ + at91_reg TC_IER ; /* Interrupt Enable Register */ + at91_reg TC_IDR ; /* Interrupt Disable Register */ + at91_reg TC_IMR ; /* Interrupt Mask Register */ + at91_reg Reserved2 ; + at91_reg Reserved3 ; + at91_reg Reserved4 ; + at91_reg Reserved5 ; +} StructTC ; + +#define NB_TC_CHANNEL 3 + +typedef struct +{ + StructTC TC[NB_TC_CHANNEL] ; + at91_reg TC_BCR ; /* Block Control Register */ + at91_reg TC_BMR ; /* Block Mode Register */ +} StructTCBlock ; + +/*--------------------------------------------------------*/ +/* TC_CCR: Timer Counter Control Register Bits Definition */ +/*--------------------------------------------------------*/ +#define TC_CLKEN 0x1 +#define TC_CLKDIS 0x2 +#define TC_SWTRG 0x4 + +/*---------------------------------------------------------------*/ +/* TC_CMR: Timer Counter Channel Mode Register Bits Definition */ +/*---------------------------------------------------------------*/ + +/*-----------------*/ +/* Clock Selection */ +/*-----------------*/ +#define TC_CLKS 0x7 +#define TC_CLKS_MCK2 0x0 +#define TC_CLKS_MCK8 0x1 +#define TC_CLKS_MCK32 0x2 +#define TC_CLKS_MCK128 0x3 +#define TC_CLKS_MCK1024 0x4 + +#define TC_CLKS_SLCK 0x4 + +#define TC_CLKS_XC0 0x5 +#define TC_CLKS_XC1 0x6 +#define TC_CLKS_XC2 0x7 + + +/*-----------------*/ +/* Clock Inversion */ +/*-----------------*/ +#define TC_CLKI 0x8 + +/*------------------------*/ +/* Burst Signal Selection */ +/*------------------------*/ +#define TC_BURST 0x30 +#define TC_BURST_NONE 0x0 +#define TC_BUSRT_XC0 0x10 +#define TC_BURST_XC1 0x20 +#define TC_BURST_XC2 0x30 + +/*------------------------------------------------------*/ +/* Capture Mode : Counter Clock Stopped with RB Loading */ +/*------------------------------------------------------*/ +#define TC_LDBSTOP 0x40 + +/*-------------------------------------------------------*/ +/* Waveform Mode : Counter Clock Stopped with RC Compare */ +/*-------------------------------------------------------*/ +#define TC_CPCSTOP 0x40 + +/*-------------------------------------------------------*/ +/* Capture Mode : Counter Clock Disabled with RB Loading */ +/*--------------------------------------------------------*/ +#define TC_LDBDIS 0x80 + +/*--------------------------------------------------------*/ +/* Waveform Mode : Counter Clock Disabled with RC Compare */ +/*--------------------------------------------------------*/ +#define TC_CPCDIS 0x80 + +/*------------------------------------------------*/ +/* Capture Mode : External Trigger Edge Selection */ +/*------------------------------------------------*/ +#define TC_ETRGEDG 0x300 +#define TC_ETRGEDG_EDGE_NONE 0x0 +#define TC_ETRGEDG_RISING_EDGE 0x100 +#define TC_ETRGEDG_FALLING_EDGE 0x200 +#define TC_ETRGEDG_BOTH_EDGE 0x300 + +/*-----------------------------------------------*/ +/* Waveform Mode : External Event Edge Selection */ +/*-----------------------------------------------*/ +#define TC_EEVTEDG 0x300 +#define TC_EEVTEDG_EDGE_NONE 0x0 +#define TC_EEVTEDG_RISING_EDGE 0x100 +#define TC_EEVTEDG_FALLING_EDGE 0x200 +#define TC_EEVTEDG_BOTH_EDGE 0x300 + +/*--------------------------------------------------------*/ +/* Capture Mode : TIOA or TIOB External Trigger Selection */ +/*--------------------------------------------------------*/ +#define TC_ABETRG 0x400 +#define TC_ABETRG_TIOB 0x0 +#define TC_ABETRG_TIOA 0x400 + +/*------------------------------------------*/ +/* Waveform Mode : External Event Selection */ +/*------------------------------------------*/ +#define TC_EEVT 0xC00 +#define TC_EEVT_TIOB 0x0 +#define TC_EEVT_XC0 0x400 +#define TC_EEVT_XC1 0x800 +#define TC_EEVT_XC2 0xC00 + +/*--------------------------------------------------*/ +/* Waveform Mode : Enable Trigger on External Event */ +/*--------------------------------------------------*/ +#define TC_ENETRG 0x1000 + +/*----------------------------------*/ +/* RC Compare Enable Trigger Enable */ +/*----------------------------------*/ +#define TC_CPCTRG 0x4000 + +/*----------------*/ +/* Mode Selection */ +/*----------------*/ +#define TC_WAVE 0x8000 +#define TC_CAPT 0x0 + +/*-------------------------------------*/ +/* Capture Mode : RA Loading Selection */ +/*-------------------------------------*/ +#define TC_LDRA 0x30000 +#define TC_LDRA_EDGE_NONE 0x0 +#define TC_LDRA_RISING_EDGE 0x10000 +#define TC_LDRA_FALLING_EDGE 0x20000 +#define TC_LDRA_BOTH_EDGE 0x30000 + +/*-------------------------------------------*/ +/* Waveform Mode : RA Compare Effect on TIOA */ +/*-------------------------------------------*/ +#define TC_ACPA 0x30000 +#define TC_ACPA_OUTPUT_NONE 0x0 +#define TC_ACPA_SET_OUTPUT 0x10000 +#define TC_ACPA_CLEAR_OUTPUT 0x20000 +#define TC_ACPA_TOGGLE_OUTPUT 0x30000 + +/*-------------------------------------*/ +/* Capture Mode : RB Loading Selection */ +/*-------------------------------------*/ +#define TC_LDRB 0xC0000 +#define TC_LDRB_EDGE_NONE 0x0 +#define TC_LDRB_RISING_EDGE 0x40000 +#define TC_LDRB_FALLING_EDGE 0x80000 +#define TC_LDRB_BOTH_EDGE 0xC0000 + +/*-------------------------------------------*/ +/* Waveform Mode : RC Compare Effect on TIOA */ +/*-------------------------------------------*/ +#define TC_ACPC 0xC0000 +#define TC_ACPC_OUTPUT_NONE 0x0 +#define TC_ACPC_SET_OUTPUT 0x40000 +#define TC_ACPC_CLEAR_OUTPUT 0x80000 +#define TC_ACPC_TOGGLE_OUTPUT 0xC0000 + +/*-----------------------------------------------*/ +/* Waveform Mode : External Event Effect on TIOA */ +/*-----------------------------------------------*/ +#define TC_AEEVT 0x300000 +#define TC_AEEVT_OUTPUT_NONE 0x0 +#define TC_AEEVT_SET_OUTPUT 0x100000 +#define TC_AEEVT_CLEAR_OUTPUT 0x200000 +#define TC_AEEVT_TOGGLE_OUTPUT 0x300000 + +/*-------------------------------------------------*/ +/* Waveform Mode : Software Trigger Effect on TIOA */ +/*-------------------------------------------------*/ +#define TC_ASWTRG 0xC00000 +#define TC_ASWTRG_OUTPUT_NONE 0x0 +#define TC_ASWTRG_SET_OUTPUT 0x400000 +#define TC_ASWTRG_CLEAR_OUTPUT 0x800000 +#define TC_ASWTRG_TOGGLE_OUTPUT 0xC00000 + +/*-------------------------------------------*/ +/* Waveform Mode : RB Compare Effect on TIOB */ +/*-------------------------------------------*/ +#define TC_BCPB 0x1000000 +#define TC_BCPB_OUTPUT_NONE 0x0 +#define TC_BCPB_SET_OUTPUT 0x1000000 +#define TC_BCPB_CLEAR_OUTPUT 0x2000000 +#define TC_BCPB_TOGGLE_OUTPUT 0x3000000 + +/*-------------------------------------------*/ +/* Waveform Mode : RC Compare Effect on TIOB */ +/*-------------------------------------------*/ +#define TC_BCPC 0xC000000 +#define TC_BCPC_OUTPUT_NONE 0x0 +#define TC_BCPC_SET_OUTPUT 0x4000000 +#define TC_BCPC_CLEAR_OUTPUT 0x8000000 +#define TC_BCPC_TOGGLE_OUTPUT 0xC000000 + +/*-----------------------------------------------*/ +/* Waveform Mode : External Event Effect on TIOB */ +/*-----------------------------------------------*/ +#define TC_BEEVT 0x30000000 //* bit 29-28 +#define TC_BEEVT_OUTPUT_NONE 0x0 +#define TC_BEEVT_SET_OUTPUT 0x10000000 //* bit 29-28 01 +#define TC_BEEVT_CLEAR_OUTPUT 0x20000000 //* bit 29-28 10 +#define TC_BEEVT_TOGGLE_OUTPUT 0x30000000 //* bit 29-28 11 + +/*- -----------------------------------------------*/ +/* Waveform Mode : Software Trigger Effect on TIOB */ +/*-------------------------------------------------*/ +#define TC_BSWTRG 0xC0000000 +#define TC_BSWTRG_OUTPUT_NONE 0x0 +#define TC_BSWTRG_SET_OUTPUT 0x40000000 +#define TC_BSWTRG_CLEAR_OUTPUT 0x80000000 +#define TC_BSWTRG_TOGGLE_OUTPUT 0xC0000000 + +/*------------------------------------------------------*/ +/* TC_SR: Timer Counter Status Register Bits Definition */ +/*------------------------------------------------------*/ +#define TC_COVFS 0x1 /* Counter Overflow Status */ +#define TC_LOVRS 0x2 /* Load Overrun Status */ +#define TC_CPAS 0x4 /* RA Compare Status */ +#define TC_CPBS 0x8 /* RB Compare Status */ +#define TC_CPCS 0x10 /* RC Compare Status */ +#define TC_LDRAS 0x20 /* RA Loading Status */ +#define TC_LDRBS 0x40 /* RB Loading Status */ +#define TC_ETRGS 0x80 /* External Trigger Status */ +#define TC_CLKSTA 0x10000 /* Clock Status */ +#define TC_MTIOA 0x20000 /* TIOA Mirror */ +#define TC_MTIOB 0x40000 /* TIOB Status */ + +/*--------------------------------------------------------------*/ +/* TC_BCR: Timer Counter Block Control Register Bits Definition */ +/*--------------------------------------------------------------*/ +#define TC_SYNC 0x1 /* Synchronisation Trigger */ + +/*------------------------------------------------------------*/ +/* TC_BMR: Timer Counter Block Mode Register Bits Definition */ +/*------------------------------------------------------------*/ +#define TC_TC0XC0S 0x3 /* External Clock Signal 0 Selection */ +#define TC_TCLK0XC0 0x0 +#define TC_NONEXC0 0x1 +#define TC_TIOA1XC0 0x2 +#define TC_TIOA2XC0 0x3 + +#define TC_TC1XC1S 0xC /* External Clock Signal 1 Selection */ +#define TC_TCLK1XC1 0x0 +#define TC_NONEXC1 0x4 +#define TC_TIOA0XC1 0x8 +#define TC_TIOA2XC1 0xC + +#define TC_TC2XC2S 0x30 /* External Clock Signal 2 Selection */ +#define TC_TCLK2XC2 0x0 +#define TC_NONEXC2 0x10 +#define TC_TIOA0XC2 0x20 +#define TC_TIOA1XC2 0x30 + +#endif /* tc_h */ + diff --git a/20080212/Demo/ARM7_AT91FR40008_GCC/usart.h b/20080212/Demo/ARM7_AT91FR40008_GCC/usart.h new file mode 100644 index 000000000..ad36ef504 --- /dev/null +++ b/20080212/Demo/ARM7_AT91FR40008_GCC/usart.h @@ -0,0 +1,151 @@ +//*---------------------------------------------------------------------------- +//* ATMEL Microcontroller Software Support - ROUSSET - +//*---------------------------------------------------------------------------- +//* The software is delivered "AS IS" without warranty or condition of any +//* kind, either express, implied or statutory. This includes without +//* limitation any warranty or condition with respect to merchantability or +//* fitness for any particular purpose, or against the infringements of +//* intellectual property rights of others. +//*----------------------------------------------------------------------------- +//* File Name : usart.h +//* Object : USART Header File. +//* +//* 1.0 01/04/00 JCZ : Creation +//*---------------------------------------------------------------------------- + +#ifndef usart_h +#define usart_h + +//#include "periph/stdc/std_c.h" +//#include "periph/pio/lib_pio.h" + +/*-------------------------------------------*/ +/* USART User Interface Structure Definition */ +/*-------------------------------------------*/ + +typedef struct +{ + at91_reg US_CR ; /* Control Register */ + at91_reg US_MR ; /* Mode Register */ + at91_reg US_IER ; /* Interrupt Enable Register */ + at91_reg US_IDR ; /* Interrupt Disable Register */ + at91_reg US_IMR ; /* Interrupt Mask Register */ + at91_reg US_CSR ; /* Channel Status Register */ + at91_reg US_RHR ; /* Receive Holding Register */ + at91_reg US_THR ; /* Transmit Holding Register */ + at91_reg US_BRGR ; /* Baud Rate Generator Register */ + at91_reg US_RTOR ; /* Receiver Timeout Register */ + at91_reg US_TTGR ; /* Transmitter Time-guard Register */ + at91_reg Reserved ; + at91_reg US_RPR ; /* Receiver Pointer Register */ + at91_reg US_RCR ; /* Receiver Counter Register */ + at91_reg US_TPR ; /* Transmitter Pointer Register */ + at91_reg US_TCR ; /* Transmitter Counter Register */ +} StructUSART ; + +/*--------------------------*/ +/* US_CR : Control Register */ +/*--------------------------*/ + +#define US_RSTRX 0x0004 /* Reset Receiver */ +#define US_RSTTX 0x0008 /* Reset Transmitter */ +#define US_RXEN 0x0010 /* Receiver Enable */ +#define US_RXDIS 0x0020 /* Receiver Disable */ +#define US_TXEN 0x0040 /* Transmitter Enable */ +#define US_TXDIS 0x0080 /* Transmitter Disable */ +#define US_RSTSTA 0x0100 /* Reset Status Bits */ +#define US_STTBRK 0x0200 /* Start Break */ +#define US_STPBRK 0x0400 /* Stop Break */ +#define US_STTTO 0x0800 /* Start Time-out */ +#define US_SENDA 0x1000 /* Send Address */ + +/*-----------------------*/ +/* US_MR : Mode Register */ +/*-----------------------*/ + +#define US_CLKS 0x0030 /* Clock Selection */ +#define US_CLKS_MCK 0x00 /* Master Clock */ +#define US_CLKS_MCK8 0x10 /* Master Clock divided by 8 */ +#define US_CLKS_SCK 0x20 /* External Clock */ +#define US_CLKS_SLCK 0x30 /* Slow Clock */ + +#define US_CHRL 0x00C0 /* Byte Length */ +#define US_CHRL_5 0x00 /* 5 bits */ +#define US_CHRL_6 0x40 /* 6 bits */ +#define US_CHRL_7 0x80 /* 7 bits */ +#define US_CHRL_8 0xC0 /* 8 bits */ + +#define US_SYNC 0x0100 /* Synchronous Mode Enable */ + +#define US_PAR 0x0E00 /* Parity Mode */ +#define US_PAR_EVEN 0x00 /* Even Parity */ +#define US_PAR_ODD 0x200 /* Odd Parity */ +#define US_PAR_SPACE 0x400 /* Space Parity to 0 */ +#define US_PAR_MARK 0x600 /* Marked Parity to 1 */ +#define US_PAR_NO 0x800 /* No Parity */ +#define US_PAR_MULTIDROP 0xC00 /* Multi-drop Mode */ + +#define US_NBSTOP 0x3000 /* Stop Bit Number */ +#define US_NBSTOP_1 0x0000 /* 1 Stop Bit */ +#define US_NBSTOP_1_5 0x1000 /* 1.5 Stop Bits */ +#define US_NBSTOP_2 0x2000 /* 2 Stop Bits */ + +#define US_CHMODE 0xC000 /* Channel Mode */ +#define US_CHMODE_NORMAL 0x0000 /* Normal Mode */ +#define US_CHMODE_AUTOMATIC_ECHO 0x4000 /* Automatic Echo */ +#define US_CHMODE_LOCAL_LOOPBACK 0x8000 /* Local Loopback */ +#define US_CHMODE_REMOTE_LOOPBACK 0xC000 /* Remote Loopback */ + +#define US_MODE9 0x20000 /* 9 Bit Mode */ + +#define US_CLKO 0x40000 /* Baud Rate Output Enable */ + +/* Mode Register model */ + +/* Standard Asynchronous Mode : 8 bits , 1 stop , no parity */ +#define US_ASYNC_MODE ( US_CHMODE_NORMAL + \ + US_NBSTOP_1 + \ + US_PAR_NO + \ + US_CHRL_8 + \ + US_CLKS_MCK ) + +/* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity */ +#define US_ASYNC_SCK_MODE ( US_CHMODE_NORMAL + \ + US_NBSTOP_1 + \ + US_PAR_NO + \ + US_CHRL_8 + \ + US_CLKS_SCK ) + +/* Standard Synchronous Mode : 8 bits , 1 stop , no parity */ +#define US_SYNC_MODE ( US_SYNC + \ + US_CHMODE_NORMAL + \ + US_NBSTOP_1 + \ + US_PAR_NO + \ + US_CHRL_8 + \ + US_CLKS_MCK ) + +/* SCK used Label */ +#define SCK_USED (US_CLKO | US_CLKS_SCK) + +/*---------------------------------------------------------------*/ +/* US_IER, US_IDR, US_IMR, US_IMR: Status and Interrupt Register */ +/*---------------------------------------------------------------*/ + +#define US_RXRDY 0x1 /* Receiver Ready */ +#define US_TXRDY 0x2 /* Transmitter Ready */ +#define US_RXBRK 0x4 /* Receiver Break */ +#define US_ENDRX 0x8 /* End of Receiver PDC Transfer */ +#define US_ENDTX 0x10 /* End of Transmitter PDC Transfer */ +#define US_OVRE 0x20 /* Overrun Error */ +#define US_FRAME 0x40 /* Framing Error */ +#define US_PARE 0x80 /* Parity Error */ +#define US_TIMEOUT 0x100 /* Receiver Timeout */ +#define US_TXEMPTY 0x200 /* Transmitter Empty */ + +#define US_MASK_IRQ_TX (US_TXRDY | US_ENDTX | US_TXEMPTY) +#define US_MASK_IRQ_RX (US_RXRDY | US_ENDRX | US_TIMEOUT) +#define US_MASK_IRQ_ERROR (US_PARE | US_FRAME | US_OVRE | US_RXBRK) + + + +#endif /* usart_h */ diff --git a/20080212/Demo/ARM7_AT91SAM7S64_IAR/FreeRTOSConfig.h b/20080212/Demo/ARM7_AT91SAM7S64_IAR/FreeRTOSConfig.h new file mode 100644 index 000000000..172583a74 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7S64_IAR/FreeRTOSConfig.h @@ -0,0 +1,88 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include +#include "Board.h" + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 47923200 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 100 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) 14200 ) +#define configMAX_TASK_NAME_LEN ( 16 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/ARM7_AT91SAM7S64_IAR/ParTest/ParTest.c b/20080212/Demo/ARM7_AT91SAM7S64_IAR/ParTest/ParTest.c new file mode 100644 index 000000000..9ec4d4adb --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7S64_IAR/ParTest/ParTest.c @@ -0,0 +1,91 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#include "FreeRTOS.h" +#include "partest.h" +#include "board.h" + +/*----------------------------------------------------------- + * Simple parallel port IO routines for the LED's. + *-----------------------------------------------------------*/ + +const unsigned portLONG led_mask[ NB_LED ]= { LED1, LED2, LED3, LED4 }; + +void vParTestInitialise( void ) +{ + /* Start with all LED's off. */ + AT91F_PIO_SetOutput( AT91C_BASE_PIOA, LED_MASK ); +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ + if( uxLED < ( portBASE_TYPE ) NB_LED ) + { + if( xValue ) + { + AT91F_PIO_SetOutput( AT91C_BASE_PIOA, led_mask[ uxLED ] ); + } + else + { + AT91F_PIO_ClearOutput( AT91C_BASE_PIOA, led_mask[ uxLED ]); + } + } +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ + if( uxLED < ( portBASE_TYPE ) NB_LED ) + { + if( AT91F_PIO_GetInput( AT91C_BASE_PIOA ) & led_mask[ uxLED ] ) + { + AT91F_PIO_ClearOutput( AT91C_BASE_PIOA, led_mask[ uxLED ]); + } + else + { + AT91F_PIO_SetOutput( AT91C_BASE_PIOA, led_mask[ uxLED ] ); + } + } +} + + diff --git a/20080212/Demo/ARM7_AT91SAM7S64_IAR/SrcIAR/Board.h b/20080212/Demo/ARM7_AT91SAM7S64_IAR/SrcIAR/Board.h new file mode 100644 index 000000000..f6da8060c --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7S64_IAR/SrcIAR/Board.h @@ -0,0 +1,89 @@ +/*---------------------------------------------------------------------------- +* ATMEL Microcontroller Software Support - ROUSSET - +*---------------------------------------------------------------------------- +* The software is delivered "AS IS" without warranty or condition of any +* kind, either express, implied or statutory. This includes without +* limitation any warranty or condition with respect to merchantability or +* fitness for any particular purpose, or against the infringements of +* intellectual property rights of others. +*---------------------------------------------------------------------------- +* File Name : Board.h +* Object : AT91SAM7S Evaluation Board Features Definition File. +* +* Creation : JPP 16/Jun/2004 +*---------------------------------------------------------------------------- +*/ +#ifndef Board_h +#define Board_h + +#include "AT91SAM7S64.h" +#define __inline inline +#include "lib_AT91SAM7S64.h" + +#define true -1 +#define false 0 + +/*-------------------------------*/ +/* SAM7Board Memories Definition */ +/*-------------------------------*/ +// The AT91SAM7S64 embeds a 16-Kbyte SRAM bank, and 64 K-Byte Flash + +#define INT_SARM 0x00200000 +#define INT_SARM_REMAP 0x00000000 + +#define INT_FLASH 0x00000000 +#define INT_FLASH_REMAP 0x01000000 + +#define FLASH_PAGE_NB 512 +#define FLASH_PAGE_SIZE 128 + +/*-----------------*/ +/* Leds Definition */ +/*-----------------*/ +/* PIO Flash PA PB PIN */ +#define LED1 (1<<0) /* PA0 / PGMEN0 & PWM0 TIOA0 48 */ +#define LED2 (1<<1) /* PA1 / PGMEN1 & PWM1 TIOB0 47 */ +#define LED3 (1<<2) /* PA2 & PWM2 SCK0 44 */ +#define LED4 (1<<3) /* PA3 & TWD NPCS3 43 */ +#define NB_LED 4 + +#define LED_MASK (LED1|LED2|LED3|LED4) + +/*-------------------------*/ +/* Push Buttons Definition */ +/*-------------------------*/ +/* PIO Flash PA PB PIN */ +#define SW1_MASK (1<<19) /* PA19 / PGMD7 & RK FIQ 13 */ +#define SW2_MASK (1<<20) /* PA20 / PGMD8 & RF IRQ0 16 */ +#define SW3_MASK (1<<15) /* PA15 / PGM3 & TF TIOA1 20 */ +#define SW4_MASK (1<<14) /* PA14 / PGMD2 & SPCK PWM3 21 */ +#define SW_MASK (SW1_MASK|SW2_MASK|SW3_MASK|SW4_MASK) + + +#define SW1 (1<<19) // PA19 +#define SW2 (1<<20) // PA20 +#define SW3 (1<<15) // PA15 +#define SW4 (1<<14) // PA14 + +/*------------------*/ +/* USART Definition */ +/*------------------*/ +/* SUB-D 9 points J3 DBGU*/ +#define DBGU_RXD AT91C_PA9_DRXD /* JP11 must be close */ +#define DBGU_TXD AT91C_PA10_DTXD /* JP12 must be close */ +#define AT91C_DBGU_BAUD 115200 // Baud rate + +#define US_RXD_PIN AT91C_PA5_RXD0 /* JP9 must be close */ +#define US_TXD_PIN AT91C_PA6_TXD0 /* JP7 must be close */ +#define US_RTS_PIN AT91C_PA7_RTS0 /* JP8 must be close */ +#define US_CTS_PIN AT91C_PA8_CTS0 /* JP6 must be close */ + +/*--------------*/ +/* Master Clock */ +/*--------------*/ + +#define EXT_OC 18432000 // Exetrnal ocilator MAINCK +#define MCK 47923200 // MCK (PLLRC div by 2) +#define MCKKHz (MCK/1000) // + +#endif /* Board_h */ diff --git a/20080212/Demo/ARM7_AT91SAM7S64_IAR/SrcIAR/Cstartup.s b/20080212/Demo/ARM7_AT91SAM7S64_IAR/SrcIAR/Cstartup.s new file mode 100644 index 000000000..12842e137 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7S64_IAR/SrcIAR/Cstartup.s @@ -0,0 +1,302 @@ +;* ---------------------------------------------------------------------------- +;* ATMEL Microcontroller Software Support - ROUSSET - +;* ---------------------------------------------------------------------------- +;* Copyright (c) 2006, Atmel Corporation +; +;* All rights reserved. +;* +;* Redistribution and use in source and binary forms, with or without +;* modification, are permitted provided that the following conditions are met: +;* +;* - Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the disclaimer below. +;* +;* - Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the disclaimer below in the documentation and/or +;* other materials provided with the distribution. +;* +;* Atmel's name may not be used to endorse or promote products derived from +;* this software without specific prior written permission. +;* +;* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +;* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +;* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +;* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +;* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +;* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +;* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +;* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +;* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +;* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* ---------------------------------------------------------------------------- + +;------------------------------------------------------------------------------ +; Include your AT91 Library files +;------------------------------------------------------------------------------ +#include "AT91SAM7X256_inc.h" +;------------------------------------------------------------------------------ + +#define TOP_OF_MEMORY (AT91C_ISRAM + AT91C_ISRAM_SIZE) +#define IRQ_STACK_SIZE 200 + ; 3 words to be saved per interrupt priority level + +; Mode, correspords to bits 0-5 in CPSR +MODE_BITS DEFINE 0x1F ; Bit mask for mode bits in CPSR +USR_MODE DEFINE 0x10 ; User mode +FIQ_MODE DEFINE 0x11 ; Fast Interrupt Request mode +IRQ_MODE DEFINE 0x12 ; Interrupt Request mode +SVC_MODE DEFINE 0x13 ; Supervisor mode +ABT_MODE DEFINE 0x17 ; Abort mode +UND_MODE DEFINE 0x1B ; Undefined Instruction mode +SYS_MODE DEFINE 0x1F ; System mode + +I_BIT DEFINE 0x80 +F_BIT DEFINE 0x40 + +;------------------------------------------------------------------------------ +; ?RESET +; Reset Vector. +; Normally, segment INTVEC is linked at address 0. +; For debugging purposes, INTVEC may be placed at other addresses. +; A debugger that honors the entry point will start the +; program in a normal way even if INTVEC is not at address 0. +;------------------------------------------------------------------------------ + SECTION .intvec:CODE:NOROOT(2) + PUBLIC __vector + PUBLIC __iar_program_start + EXTERN vPortYieldProcessor + + ARM +__vector: + ldr pc,[pc,#+24] ;; Reset +__und_handler: + ldr pc,[pc,#+24] ;; Undefined instructions +__swi_handler: + ldr pc,[pc,#+24] ;; Software interrupt (SWI/SVC) +__prefetch_handler: + ldr pc,[pc,#+24] ;; Prefetch abort +__data_handler: + ldr pc,[pc,#+24] ;; Data abort + DC32 0xFFFFFFFF ;; RESERVED +__irq_handler: + LDR PC, [PC, #-0xF20] +__fiq_handler: + ldr pc,[pc,#+24] ;; FIQ + + DC32 __iar_program_start + DC32 __und_handler + DC32 vPortYieldProcessor + DC32 __prefetch_handler + DC32 __data_handler + B . + DC32 IRQ_Handler_Entry + DC32 FIQ_Handler_Entry + +;------------------------------------------------------------------------------ +;- Manage exception: The exception must be ensure in ARM mode +;------------------------------------------------------------------------------ + SECTION text:CODE:NOROOT(2) + ARM +;------------------------------------------------------------------------------ +;- Function : FIQ_Handler_Entry +;- Treatments : FIQ Controller Interrupt Handler. +;- R8 is initialize in Cstartup +;- Called Functions : None only by FIQ +;------------------------------------------------------------------------------ +FIQ_Handler_Entry: + +;- Switch in SVC/User Mode to allow User Stack access for C code +; because the FIQ is not yet acknowledged + +;- Save and r0 in FIQ_Register + mov r9,r0 + ldr r0 , [r8, #AIC_FVR] + msr CPSR_c,#I_BIT | F_BIT | SVC_MODE +;- Save scratch/used registers and LR in User Stack + stmfd sp!, { r1-r3, r12, lr} + +;- Branch to the routine pointed by the AIC_FVR + mov r14, pc + bx r0 + +;- Restore scratch/used registers and LR from User Stack + ldmia sp!, { r1-r3, r12, lr} + +;- Leave Interrupts disabled and switch back in FIQ mode + msr CPSR_c, #I_BIT | F_BIT | FIQ_MODE + +;- Restore the R0 ARM_MODE_SVC register + mov r0,r9 + +;- Restore the Program Counter using the LR_fiq directly in the PC + subs pc,lr,#4 +;------------------------------------------------------------------------------ +;- Function : IRQ_Handler_Entry +;- Treatments : IRQ Controller Interrupt Handler. +;- Called Functions : AIC_IVR[interrupt] +;------------------------------------------------------------------------------ +IRQ_Handler_Entry: +;------------------------- +;- Manage Exception Entry +;------------------------- +;- Adjust and save LR_irq in IRQ stack + sub lr, lr, #4 + stmfd sp!, {lr} + +;- Save r0 and SPSR (need to be saved for nested interrupt) + mrs r14, SPSR + stmfd sp!, {r0,r14} + +;- Write in the IVR to support Protect Mode +;- No effect in Normal Mode +;- De-assert the NIRQ and clear the source in Protect Mode + ldr r14, =AT91C_BASE_AIC + ldr r0 , [r14, #AIC_IVR] + str r14, [r14, #AIC_IVR] + +;- Enable Interrupt and Switch in Supervisor Mode + msr CPSR_c, #SVC_MODE + +;- Save scratch/used registers and LR in User Stack + stmfd sp!, { r1-r3, r12, r14} + +;---------------------------------------------- +;- Branch to the routine pointed by the AIC_IVR +;---------------------------------------------- + mov r14, pc + bx r0 + +;---------------------------------------------- +;- Manage Exception Exit +;---------------------------------------------- +;- Restore scratch/used registers and LR from User Stack + ldmia sp!, { r1-r3, r12, r14} + +;- Disable Interrupt and switch back in IRQ mode + msr CPSR_c, #I_BIT | IRQ_MODE + +;- Mark the End of Interrupt on the AIC + ldr r14, =AT91C_BASE_AIC + str r14, [r14, #AIC_EOICR] + +;- Restore SPSR_irq and r0 from IRQ stack + ldmia sp!, {r0,r14} + msr SPSR_cxsf, r14 + +;- Restore adjusted LR_irq from IRQ stack directly in the PC + ldmia sp!, {pc}^ + +;------------------------------------------------------------------------------ +;- Exception Vectors +;------------------------------------------------------------------------------ + PUBLIC AT91F_Default_FIQ_handler + PUBLIC AT91F_Default_IRQ_handler + PUBLIC AT91F_Spurious_handler + + ARM ; Always ARM mode after exeption + +AT91F_Default_FIQ_handler + b AT91F_Default_FIQ_handler + +AT91F_Default_IRQ_handler + b AT91F_Default_IRQ_handler + +AT91F_Spurious_handler + b AT91F_Spurious_handler + + +;------------------------------------------------------------------------------ +; ?INIT +; Program entry. +;------------------------------------------------------------------------------ + + SECTION FIQ_STACK:DATA:NOROOT(3) + SECTION IRQ_STACK:DATA:NOROOT(3) + SECTION SVC_STACK:DATA:NOROOT(3) + SECTION ABT_STACK:DATA:NOROOT(3) + SECTION UND_STACK:DATA:NOROOT(3) + SECTION CSTACK:DATA:NOROOT(3) + SECTION text:CODE:NOROOT(2) + REQUIRE __vector + EXTERN ?main + PUBLIC __iar_program_start + EXTERN AT91F_LowLevelInit + + +__iar_program_start: + +;------------------------------------------------------------------------------ +;- Low level Init is performed in a C function: AT91F_LowLevelInit +;- Init Stack Pointer to a valid memory area before calling AT91F_LowLevelInit +;------------------------------------------------------------------------------ + +;- Retrieve end of RAM address + + ldr r13,=TOP_OF_MEMORY ;- Temporary stack in internal RAM for Low Level Init execution + ldr r0,=AT91F_LowLevelInit + mov lr, pc + bx r0 ;- Branch on C function (with interworking) + +; Initialize the stack pointers. +; The pattern below can be used for any of the exception stacks: +; FIQ, IRQ, SVC, ABT, UND, SYS. +; The USR mode uses the same stack as SYS. +; The stack segments must be defined in the linker command file, +; and be declared above. + + mrs r0,cpsr ; Original PSR value + bic r0,r0,#MODE_BITS ; Clear the mode bits + orr r0,r0,#SVC_MODE ; Set SVC mode bits + msr cpsr_c,r0 ; Change the mode + ldr sp,=SFE(SVC_STACK) ; End of SVC_STACK + + bic r0,r0,#MODE_BITS ; Clear the mode bits + orr r0,r0,#UND_MODE ; Set UND mode bits + msr cpsr_c,r0 ; Change the mode + ldr sp,=SFE(UND_STACK) ; End of UND_STACK + + bic r0,r0,#MODE_BITS ; Clear the mode bits + orr r0,r0,#ABT_MODE ; Set ABT mode bits + msr cpsr_c,r0 ; Change the mode + ldr sp,=SFE(ABT_STACK) ; End of ABT_STACK + + bic r0,r0,#MODE_BITS ; Clear the mode bits + orr r0,r0,#FIQ_MODE ; Set FIQ mode bits + msr cpsr_c,r0 ; Change the mode + ldr sp,=SFE(FIQ_STACK) ; End of FIQ_STACK + ;- Init the FIQ register + ldr r8, =AT91C_BASE_AIC + + bic r0,r0,#MODE_BITS ; Clear the mode bits + orr r0,r0,#IRQ_MODE ; Set IRQ mode bits + msr cpsr_c,r0 ; Change the mode + ldr sp,=SFE(IRQ_STACK) ; End of IRQ_STACK + + bic r0,r0,#MODE_BITS ; Clear the mode bits + orr r0,r0,#SYS_MODE ; Set System mode bits + msr cpsr_c,r0 ; Change the mode + ldr sp,=SFE(CSTACK) ; End of CSTACK + + +#ifdef __ARMVFP__ +; Enable the VFP coprocessor. + mov r0, #0x40000000 ; Set EN bit in VFP + fmxr fpexc, r0 ; FPEXC, clear others. + +; Disable underflow exceptions by setting flush to zero mode. +; For full IEEE 754 underflow compliance this code should be removed +; and the appropriate exception handler installed. + mov r0, #0x01000000 ; Set FZ bit in VFP + fmxr fpscr, r0 ; FPSCR, clear others. +#endif + +; Add more initialization here + msr CPSR_c,#I_BIT | F_BIT | SVC_MODE + + +; Continue to ?main for more IAR specific system startup + + ldr r0,=?main + bx r0 + + END ;- Terminates the assembly of the last module in a file diff --git a/20080212/Demo/ARM7_AT91SAM7S64_IAR/SrcIAR/Cstartup_SAM7.c b/20080212/Demo/ARM7_AT91SAM7S64_IAR/SrcIAR/Cstartup_SAM7.c new file mode 100644 index 000000000..90b3982b8 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7S64_IAR/SrcIAR/Cstartup_SAM7.c @@ -0,0 +1,84 @@ +//*---------------------------------------------------------------------------- +//* ATMEL Microcontroller Software Support - ROUSSET - +//*---------------------------------------------------------------------------- +//* The software is delivered "AS IS" without warranty or condition of any +//* kind, either express, implied or statutory. This includes without +//* limitation any warranty or condition with respect to merchantability or +//* fitness for any particular purpose, or against the infringements of +//* intellectual property rights of others. +//*---------------------------------------------------------------------------- +//* File Name : Cstartup_SAM7.c +//* Object : Low level initializations written in C for IAR +//* tools +//* Creation : 12/Jun/04 +//* +//*---------------------------------------------------------------------------- + + +// Include the board file description +#include "Board.h" + +// The following functions must be write in ARM mode this function called directly +// by exception vector +extern void AT91F_Spurious_handler(void); +extern void AT91F_Default_IRQ_handler(void); +extern void AT91F_Default_FIQ_handler(void); + +//*---------------------------------------------------------------------------- +//* \fn AT91F_LowLevelInit +//* \brief This function performs very low level HW initialization +//* this function can be use a Stack, depending the compilation +//* optimization mode +//*---------------------------------------------------------------------------- +void AT91F_LowLevelInit( void ); +void AT91F_LowLevelInit( void) @ "ICODE" +{ + int i; + AT91PS_PMC pPMC = AT91C_BASE_PMC; + //* Set Flash Waite sate + // Single Cycle Access at Up to 30 MHz, or 40 + // if MCK = 47923200 I have 50 Cycle for 1 useconde ( flied MC_FMR->FMCN + AT91C_BASE_MC->MC_FMR = ((AT91C_MC_FMCN)&(50 <<16)) | AT91C_MC_FWS_1FWS ; + + //* Watchdog Disable + AT91C_BASE_WDTC->WDTC_WDMR= AT91C_SYSC_WDDIS; + + //* Set MCK at 47 923 200 + // 1 Enabling the Main Oscillator: + // SCK = 1/32768 = 30.51 uSeconde + // Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms + pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) | AT91C_CKGR_MOSCEN )); + // Wait the startup time + while(!(pPMC->PMC_SR & AT91C_PMC_MOSCS)); + // 2 Checking the Main Oscillator Frequency (Optional) + // 3 Setting PLL and divider: + // - div by 5 Fin = 3,6864 =(18,432 / 5) + // - Mul 25+1: Fout = 95,8464 =(3,6864 *26) + // for 96 MHz the erroe is 0.16% + // Field out NOT USED = 0 + // PLLCOUNT pll startup time esrtimate at : 0.844 ms + // PLLCOUNT 28 = 0.000844 /(1/32768) + pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 0x05) | + (AT91C_CKGR_PLLCOUNT & (28<<8)) | + (AT91C_CKGR_MUL & (25<<16))); + + // Wait the startup time + while(!(pPMC->PMC_SR & AT91C_PMC_LOCK)); + // 4. Selection of Master Clock and Processor Clock + // select the PLL clock divided by 2 + pPMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | AT91C_PMC_PRES_CLK_2 ; + + // Enable User Reset and set its minimal assertion to 960 us + AT91C_BASE_RSTC->RSTC_RMR = AT91C_SYSC_URSTEN | (0x4<<8) | (unsigned int) (0xA5<<24); + + + // Set up the default interrupts handler vectors + AT91C_BASE_AIC->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler ; + for (i=1;i < 31; i++) + { + AT91C_BASE_AIC->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler ; + } + AT91C_BASE_AIC->AIC_SPU = (int) AT91F_Spurious_handler ; + +} + diff --git a/20080212/Demo/ARM7_AT91SAM7S64_IAR/USB/USBSample.c b/20080212/Demo/ARM7_AT91SAM7S64_IAR/USB/USBSample.c new file mode 100644 index 000000000..23711e336 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7S64_IAR/USB/USBSample.c @@ -0,0 +1,1283 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + Sample interrupt driven USB device driver. This is a minimal implementation + for demonstration only. Although functional, it is not a full and compliant + implementation. + + The USB device enumerates as a simple 3 axis joystick, and once configured + transmits 3 axis of data which can be viewed from the USB host machine. + + This file implements the USB interrupt service routine, and a demo FreeRTOS + task. The interrupt service routine handles the USB hardware - taking a + snapshot of the USB status at the point of the interrupt. The task receives + the status information from the interrupt for processing at the task level. + + See the FreeRTOS.org WEB documentation for more information. +*/ + +/* + Changes from V2.5.5 + + + Descriptors that have a length that is an exact multiple of usbFIFO_LENGTH + can now be transmitted. To this end an extra parameter has been + added to the prvSendControlData() function, and the state + eSENDING_EVEN_DESCRIPTOR has been introduced. Thanks to Scott Miller for + assisting with this contribution. + + Changes from V2.6.0 + + + Replaced the duplicated RX_DATA_BK0 in the interrupt mask with the + RX_DATA_BK1. +*/ + +/* Standard includes. */ +#include + +/* Demo board includes. */ +#include "board.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + + +/* Descriptor type definitions. */ +#define usbDESCRIPTOR_TYPE_DEVICE ( 0x01 ) +#define usbDESCRIPTOR_TYPE_CONFIGURATION ( 0x02 ) +#define usbDESCRIPTOR_TYPE_STRING ( 0x03 ) + +/* USB request type definitions. */ +#define usbGET_REPORT_REQUEST ( 0x01 ) +#define usbGET_IDLE_REQUEST ( 0x02 ) +#define usbGET_PROTOCOL_REQUEST ( 0x03 ) +#define usbSET_REPORT_REQUEST ( 0x09 ) +#define usbSET_IDLE_REQUEST ( 0x0A ) +#define usbSET_PROTOCOL_REQUEST ( 0x0B ) +#define usbGET_CONFIGURATION_REQUEST ( 0x08 ) +#define usbGET_STATUS_REQUEST ( 0x00 ) +#define usbCLEAR_FEATURE_REQUEST ( 0x01 ) +#define usbSET_FEATURE_REQUEST ( 0x03 ) +#define usbSET_ADDRESS_REQUEST ( 0x05 ) +#define usbGET_DESCRIPTOR_REQUEST ( 0x06 ) +#define usbSET_CONFIGURATION_REQUEST ( 0x09 ) +#define usbGET_INTERFACE_REQUEST ( 0x0A ) +#define usbSET_INTERFACE_REQUEST ( 0x0B ) + + +/* Misc USB definitions. */ +#define usbDEVICE_CLASS_VENDOR_SPECIFIC ( 0xFF ) +#define usbBUS_POWERED ( 0x80 ) +#define usbHID_REPORT_DESCRIPTOR ( 0x22 ) +#define AT91C_UDP_TRANSCEIVER_ENABLE ( *( ( unsigned long * ) 0xfffb0074 ) ) + +/* Index to the various string. */ +#define usbLANGUAGE_STRING ( 0 ) +#define usbMANUFACTURER_STRING ( 1 ) +#define usbPRODUCT_STRING ( 2 ) +#define usbCONFIGURATION_STRING ( 3 ) +#define usbINTERFACE_STRING ( 4 ) + +/* Data indexes for reading the request from the xISRStatus.ucFifoData[] +into xUSB_REQUEST. The data order is designed for speed - so looks a +little odd. */ +#define usbREQUEST_TYPE_INDEX ( 7 ) +#define usbREQUEST_INDEX ( 6 ) +#define usbVALUE_HIGH_BYTE ( 4 ) +#define usbVALUE_LOW_BYTE ( 5 ) +#define usbINDEX_HIGH_BYTE ( 2 ) +#define usbINDEX_LOW_BYTE ( 3 ) +#define usbLENGTH_HIGH_BYTE ( 0 ) +#define usbLENGTH_LOW_BYTE ( 1 ) + +/* Misc application definitions. */ +#define usbINTERRUPT_PRIORITY ( 3 ) +#define usbQUEUE_LENGTH ( 0x3 ) /* Must have all bits set! */ +#define usbFIFO_LENGTH ( ( unsigned portLONG ) 8 ) +#define usbEND_POINT_0 ( 0 ) +#define usbEND_POINT_1 ( 1 ) +#define usbXUP ( 1 ) +#define usbXDOWN ( 2 ) +#define usbYUP ( 3 ) +#define usbYDOWN ( 4 ) +#define usbMAX_COORD ( 120 ) +#define usbMAX_TX_MESSAGE_SIZE ( 128 ) +#define usbRX_COUNT_MASK ( ( unsigned portLONG ) 0x7ff ) +#define AT91C_UDP_STALLSENT AT91C_UDP_ISOERROR +#define usbSHORTEST_DELAY ( ( portTickType ) 1 ) +#define usbINIT_DELAY ( ( portTickType ) 500 / portTICK_RATE_MS ) +#define usbSHORT_DELAY ( ( portTickType ) 50 / portTICK_RATE_MS ) +#define usbEND_POINT_RESET_MASK ( ( unsigned portLONG ) 0x0f ) +#define usbDATA_INC ( ( portCHAR ) 5 ) +#define usbEXPECTED_NUMBER_OF_BYTES ( ( unsigned portLONG ) 8 ) + +/* Control request types. */ +#define usbSTANDARD_DEVICE_REQUEST ( 0 ) +#define usbSTANDARD_INTERFACE_REQUEST ( 1 ) +#define usbSTANDARD_END_POINT_REQUEST ( 2 ) +#define usbCLASS_INTERFACE_REQUEST ( 5 ) + +/*-----------------------------------------------------------*/ + +/* Structure used to take a snapshot of the USB status from within the ISR. */ +typedef struct X_ISR_STATUS +{ + unsigned portLONG ulISR; + unsigned portLONG ulCSR0; + unsigned portCHAR ucFifoData[ 8 ]; +} xISRStatus; + +/* Structure used to hold the received requests. */ +typedef struct +{ + unsigned portCHAR ucReqType; + unsigned portCHAR ucRequest; + unsigned portSHORT usValue; + unsigned portSHORT usIndex; + unsigned portSHORT usLength; +} xUSB_REQUEST; + +typedef enum +{ + eNOTHING, + eJUST_RESET, + eJUST_GOT_CONFIG, + eJUST_GOT_ADDRESS, + eSENDING_EVEN_DESCRIPTOR, + eREADY_TO_SEND +} eDRIVER_STATE; + +/* Structure used to control the data being sent to the host. */ +typedef struct +{ + unsigned portCHAR ucTxBuffer[ usbMAX_TX_MESSAGE_SIZE ]; + unsigned portLONG ulNextCharIndex; + unsigned portLONG ulTotalDataLength; +} xTX_MESSAGE; + +/*-----------------------------------------------------------*/ + +/* + * The USB interrupt service routine. This takes a snapshot of the USB + * device at the time of the interrupt, clears the interrupts, and posts + * the data to the USB processing task. + */ +__arm void vUSB_ISR( void ); + +/* + * Called after the bus reset interrupt - this function readies all the + * end points for communication. + */ +static void prvResetEndPoints( void ); + +/* + * Setup the USB hardware, install the interrupt service routine and + * initialise all the state variables. + */ +static void vInitUSBInterface( void ); + +/* + * Decode and act upon an interrupt generated by the control end point. + */ +static void prvProcessEndPoint0Interrupt( xISRStatus *pxMessage ); + +/* + * For simplicity requests are separated into device, interface, class + * interface and end point requests. + * + * Decode and handle standard device requests originating on the control + * end point. + */ +static void prvHandleStandardDeviceRequest( xUSB_REQUEST *pxRequest ); + +/* + * For simplicity requests are separated into device, interface, class + * interface and end point requests. + * + * Decode and handle standard interface requests originating on the control + * end point. + */ +static void prvHandleStandardInterfaceRequest( xUSB_REQUEST *pxRequest ); + +/* + * For simplicity requests are separated into device, interface, class + * interface and end point requests. + * + * Decode and handle standard end point requests originating on the control + * end point. + */ +static void prvHandleStandardEndPointRequest( xUSB_REQUEST *pxRequest ); + +/* + * For simplicity requests are separated into device, interface, class + * interface and end point requests. + * + * Decode and handle the class interface requests. + */ +static void prvHandleClassInterfaceRequest( xUSB_REQUEST *pxRequest ); + +/* + * Setup the Tx buffer to send data in response to a control request. + * + * The data to be transmitted is buffered, the state variables are updated, + * then prvSendNextSegment() is called to start the transmission off. Once + * the first segment has been sent the remaining segments are transmitted + * in response to TXCOMP interrupts until the entire buffer has been + * sent. + */ +static void prvSendControlData( unsigned portCHAR *pucData, unsigned portSHORT usRequestedLength, unsigned portLONG ulLengthLeftToSend, portLONG lSendingDescriptor ); + +/* + * Examine the Tx buffer to see if there is any more data to be transmitted. + * + * If there is data to be transmitted then send the next segment. A segment + * can have a maximum of 8 bytes (this is defined as the maximum for the end + * point by the descriptor). The final segment may be less than 8 bytes if + * the total data length was not an exact multiple of 8. + */ +static void prvSendNextSegment( void ); + +/* + * A stall condition is forced each time the host makes a request that is not + * supported by this minimal implementation. + * + * A stall is forced by setting the appropriate bit in the end points control + * and status register. + */ +static void prvSendStall( void ); + +/* + * A NULL (or zero length packet) is transmitted in acknowledge the reception + * of certain events from the host. + */ +static void prvUSBTransmitNull( void ); + +/* + * When the host requests a descriptor this function is called to determine + * which descriptor is being requested and start its transmission. + */ +static void prvGetStandardInterfaceDescriptor( xUSB_REQUEST *pxRequest ); + +/* + * This demo USB device enumerates as a simple 3 axis joystick. Once + * configured this function is periodically called to generate some sample + * joystick data. + * + * The x and y axis are made to move in a square. The z axis is made to + * repeatedly increment up to its maximum. + */ +static void prvTransmitSampleValues( void ); + +/* + * The created task to handle the USB demo functionality. + */ +void vUSBDemoTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* + - DESCRIPTOR DEFINITIONS - +*/ + +/* String descriptors used during the enumeration process. +These take the form: + +{ + Length of descriptor, + Descriptor type, + Data +} +*/ +const portCHAR pxLanguageStringDescriptor[] = +{ + 4, + usbDESCRIPTOR_TYPE_STRING, + 0x09, 0x04 +}; + +const portCHAR pxManufacturerStringDescriptor[] = +{ + 18, + usbDESCRIPTOR_TYPE_STRING, + + 'F', 0x00, + 'r', 0x00, + 'e', 0x00, + 'e', 0x00, + 'R', 0x00, + 'T', 0x00, + 'O', 0x00, + 'S', 0x00 +}; + +const portCHAR pxProductStringDescriptor[] = +{ + 44, + usbDESCRIPTOR_TYPE_STRING, + + 'F', 0x00, + 'r', 0x00, + 'e', 0x00, + 'e', 0x00, + 'R', 0x00, + 'T', 0x00, + 'O', 0x00, + 'S', 0x00, + '.', 0x00, + 'o', 0x00, + 'r', 0x00, + 'g', 0x00, + ' ', 0x00, + 'J', 0x00, + 'o', 0x00, + 'y', 0x00, + 's', 0x00, + 't', 0x00, + 'i', 0x00, + 'c', 0x00, + 'k', 0x00 +}; + +const portCHAR pxConfigurationStringDescriptor[] = +{ + 38, + usbDESCRIPTOR_TYPE_STRING, + + 'C', 0x00, + 'o', 0x00, + 'n', 0x00, + 'f', 0x00, + 'i', 0x00, + 'g', 0x00, + 'u', 0x00, + 'r', 0x00, + 'a', 0x00, + 't', 0x00, + 'i', 0x00, + 'o', 0x00, + 'n', 0x00, + ' ', 0x00, + 'N', 0x00, + 'a', 0x00, + 'm', 0x00, + 'e', 0x00 +}; + +const portCHAR pxInterfaceStringDescriptor[] = +{ + 30, + usbDESCRIPTOR_TYPE_STRING, + + 'I', 0x00, + 'n', 0x00, + 't', 0x00, + 'e', 0x00, + 'r', 0x00, + 'f', 0x00, + 'a', 0x00, + 'c', 0x00, + 'e', 0x00, + ' ', 0x00, + 'N', 0x00, + 'a', 0x00, + 'm', 0x00, + 'e', 0x00 +}; + +/* Enumeration descriptors. */ +const portCHAR pxReportDescriptor[] = +{ + 0x05, 0x01, /* USAGE_PAGE (Generic Desktop) */ + 0x09, 0x04, /* USAGE (Joystick) */ + 0xa1, 0x01, /* COLLECTION (Application) */ + 0x05, 0x01, /* USAGE_PAGE (Generic Desktop) */ + 0x09, 0x01, /* USAGE (Pointer) */ + 0xa1, 0x00, /* COLLECTION (Physical) */ + 0x09, 0x30, /* USAGE (X) */ + 0x09, 0x31, /* USAGE (Y) */ + 0x09, 0x32, /* USAGE (Z) */ + 0x15, 0x81, /* LOGICAL_MINIMUM (-127) */ + 0x25, 0x7f, /* LOGICAL_MAXIMUM (127) */ + 0x75, 0x08, /* REPORT_SIZE (8) */ + 0x95, 0x03, /* REPORT_COUNT (3) */ + 0x81, 0x02, /* INPUT (Data,Var,Abs) */ + 0xc0, /* END_COLLECTION */ + 0xc0 /* END_COLLECTION */ +}; + +const char pxDeviceDescriptor[] = +{ + /* Device descriptor */ + 0x12, /* bLength */ + 0x01, /* bDescriptorType */ + 0x10, 0x01, /* bcdUSBL */ + usbDEVICE_CLASS_VENDOR_SPECIFIC, /* bDeviceClass: */ + 0x00, /* bDeviceSubclass: */ + 0x00, /* bDeviceProtocol: */ + 0x08, /* bMaxPacketSize0 */ + 0xFF, 0xFF, /* idVendorL */ + 0x01, 0x00, /* idProductL */ + 0x00, 0x01, /* bcdDeviceL */ + usbMANUFACTURER_STRING, /* iManufacturer */ + usbPRODUCT_STRING, /* iProduct */ + 0x00, /* SerialNumber */ + 0x01 /* bNumConfigs */ +}; + +const char pxConfigDescriptor[] = { + /* Configuration 1 descriptor */ + 0x09, /* CbLength */ + 0x02, /* CbDescriptorType */ + 0x22, 0x00, /* CwTotalLength 2 EP + Control */ + 0x01, /* CbNumInterfaces */ + 0x01, /* CbConfigurationValue */ + usbCONFIGURATION_STRING,/* CiConfiguration */ + usbBUS_POWERED, /* CbmAttributes Bus powered + Remote Wakeup*/ + 0x32, /* CMaxPower: 100mA */ + + /* Joystick Interface Descriptor Requirement */ + 0x09, /* bLength */ + 0x04, /* bDescriptorType */ + 0x00, /* bInterfaceNumber */ + 0x00, /* bAlternateSetting */ + 0x01, /* bNumEndpoints */ + 0x03, /* bInterfaceClass: HID code */ + 0x00, /* bInterfaceSubclass */ + 0x00, /* bInterfaceProtocol */ + usbINTERFACE_STRING,/* iInterface */ + + /* HID Descriptor */ + 0x09, /* bLength */ + 0x21, /* bDescriptor type: HID Descriptor Type */ + 0x00, 0x01, /* bcdHID */ + 0x00, /* bCountryCode */ + 0x01, /* bNumDescriptors */ + usbHID_REPORT_DESCRIPTOR, /* bDescriptorType */ + sizeof( pxReportDescriptor ), 0x00, /* wItemLength */ + + /* Endpoint 1 descriptor */ + 0x07, /* bLength */ + 0x05, /* bDescriptorType */ + 0x81, /* bEndpointAddress, Endpoint 01 - IN */ + 0x03, /* bmAttributes INT */ + 0x03, 0x00, /* wMaxPacketSize: 3 bytes (x, y, z) */ + 0x0A /* bInterval */ +}; + +/*-----------------------------------------------------------*/ + +/* File scope state variables. */ +static unsigned portCHAR ucUSBConfig = ( unsigned portCHAR ) 0; +static unsigned portLONG ulReceivedAddress = ( unsigned portLONG ) 0; +static eDRIVER_STATE eDriverState = eNOTHING; + +/* Array in which the USB interrupt status is passed between the ISR and task. */ +static xISRStatus xISRMessages[ usbQUEUE_LENGTH + 1 ]; + +/* Structure used to control the characters being sent to the host. */ +static xTX_MESSAGE pxCharsForTx; + +/* Queue used to pass messages between the ISR and the task. */ +static xQueueHandle xUSBInterruptQueue; + +/* ISR entry has to be written in the asm file as we want a context switch +to occur from within the ISR. See the port documentation on the FreeRTOS.org +WEB site for more information. */ +extern void vUSBISREntry( void ); + +/*-----------------------------------------------------------*/ + +/* Macros to manipulate the control and status registers. These registers +cannot be accessed using a direct read modify write operation outside of the +ISR as some bits are left unchanged by writing with a 0, and some are left +unchanged by writing with a 1. */ + +#define usbINT_CLEAR_MASK (AT91C_UDP_TXCOMP | AT91C_UDP_STALLSENT | AT91C_UDP_RXSETUP | AT91C_UDP_RX_DATA_BK0 | AT91C_UDP_RX_DATA_BK1 ) + +#define usbCSR_SET_BIT( pulValueNow, ulBit ) \ +{ \ + /* Set TXCOMP, RX_DATA_BK0, RXSETUP, */ \ + /* STALLSENT and RX_DATA_BK1 to 1 so the */ \ + /* write has no effect. */ \ + ( * ( ( unsigned portLONG * ) pulValueNow ) ) |= ( unsigned portLONG ) 0x4f; \ + \ + /* Clear the FORCE_STALL and TXPKTRDY bits */ \ + /* so the write has no effect. */ \ + ( * ( ( unsigned portLONG * ) pulValueNow ) ) &= ( unsigned portLONG ) 0xffffffcf; \ + \ + /* Set whichever bit we want set. */ \ + ( * ( ( unsigned portLONG * ) pulValueNow ) ) |= ( ulBit ); \ +} + +#define usbCSR_CLEAR_BIT( pulValueNow, ulBit ) \ +{ \ + /* Set TXCOMP, RX_DATA_BK0, RXSETUP, */ \ + /* STALLSENT and RX_DATA_BK1 to 1 so the */ \ + /* write has no effect. */ \ + ( * ( ( unsigned portLONG * ) pulValueNow ) ) |= ( unsigned portLONG ) 0x4f; \ + \ + /* Clear the FORCE_STALL and TXPKTRDY bits */ \ + /* so the write has no effect. */ \ + ( * ( ( unsigned portLONG * ) pulValueNow ) ) &= ( unsigned portLONG ) 0xffffffcf; \ + \ + /* Clear whichever bit we want clear. */ \ + ( * ( ( unsigned portLONG * ) pulValueNow ) ) &= ( ~ulBit ); \ +} + +/*-----------------------------------------------------------*/ + +__arm void vUSB_ISR( void ) +{ +portBASE_TYPE xTaskWokenByPost = pdFALSE; +static volatile unsigned portLONG ulNextMessage = 0; +xISRStatus *pxMessage; +unsigned portLONG ulTemp, ulRxBytes; + + /* Take the next message from the queue. Note that usbQUEUE_LENGTH *must* + be all 1's, as in 0x01, 0x03, 0x07, etc. */ + pxMessage = &( xISRMessages[ ( ulNextMessage & usbQUEUE_LENGTH ) ] ); + ulNextMessage++; + + /* Take a snapshot of the current USB state for processing at the task + level. */ + pxMessage->ulISR = AT91C_BASE_UDP->UDP_ISR; + pxMessage->ulCSR0 = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ]; + + /* Clear the interrupts from the ICR register. The bus end interrupt is + cleared separately as it does not appear in the mask register. */ + AT91C_BASE_UDP->UDP_ICR = AT91C_BASE_UDP->UDP_IMR | AT91C_UDP_ENDBUSRES; + + /* If there are bytes in the FIFO then we have to retrieve them here. + Ideally this would be done at the task level. However we need to clear the + RXSETUP interrupt before leaving the ISR, and this may cause the data in + the FIFO to be overwritten. Also the DIR bit has to be changed before the + RXSETUP bit is cleared (as per the SAM7 manual). */ + ulTemp = pxMessage->ulCSR0; + + /* Are there any bytes in the FIFO? */ + ulRxBytes = ulTemp >> 16; + ulRxBytes &= usbRX_COUNT_MASK; + + /* With this minimal implementation we are only interested in receiving + setup bytes on the control end point. */ + if( ( ulRxBytes > 0 ) && ( ulTemp & AT91C_UDP_RXSETUP ) ) + { + /* Take off 1 for a zero based index. */ + while( ulRxBytes > 0 ) + { + ulRxBytes--; + pxMessage->ucFifoData[ ulRxBytes ] = AT91C_BASE_UDP->UDP_FDR[ usbEND_POINT_0 ]; + } + + /* The direction must be changed first. */ + usbCSR_SET_BIT( &ulTemp, ( AT91C_UDP_DIR ) ); + AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulTemp; + } + + /* Must write zero's to TXCOMP, STALLSENT, RXSETUP, and the RX DATA + registers to clear the interrupts in the CSR register. */ + usbCSR_CLEAR_BIT( &ulTemp, usbINT_CLEAR_MASK ); + AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulTemp; + + /* Also clear the interrupts in the CSR1 register. */ + ulTemp = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ]; + usbCSR_CLEAR_BIT( &ulTemp, usbINT_CLEAR_MASK ); + AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] = ulTemp; + + /* The message now contains the entire state and optional data from + the USB interrupt. This can now be posted on the Rx queue ready for + processing at the task level. */ + xTaskWokenByPost = xQueueSendFromISR( xUSBInterruptQueue, &pxMessage, xTaskWokenByPost ); + + /* We may want to switch to the USB task, if this message has made + it the highest priority task that is ready to execute. */ + portEND_SWITCHING_ISR( xTaskWokenByPost ); + + /* Clear the AIC ready for the next interrupt. */ + AT91C_BASE_AIC->AIC_EOICR = 0; +} +/*-----------------------------------------------------------*/ + +void vUSBDemoTask( void *pvParameters ) +{ +xISRStatus *pxMessage; + + /* The parameters are not used in this task. */ + ( void ) pvParameters; + + /* Init USB device */ + portENTER_CRITICAL(); + vInitUSBInterface(); + portEXIT_CRITICAL(); + + /* Process interrupts as they arrive. The ISR takes a snapshot of the + interrupt status then posts the information on this queue for processing + at the task level. This simple demo implementation only processes + a few interrupt sources. */ + for( ;; ) + { + if( xQueueReceive( xUSBInterruptQueue, &pxMessage, usbSHORT_DELAY ) ) + { + if( pxMessage->ulISR & AT91C_UDP_EPINT0 ) + { + /* Process end point 0 interrupt. */ + prvProcessEndPoint0Interrupt( pxMessage ); + } + + if( pxMessage->ulISR & AT91C_UDP_ENDBUSRES ) + { + /* Process an end of bus reset interrupt. */ + prvResetEndPoints(); + } + } + else + { + /* The ISR did not post any data for us to process on the queue, so + just generate and send some sample data. */ + if( eDriverState == eREADY_TO_SEND ) + { + prvTransmitSampleValues(); + } + } + } +} +/*-----------------------------------------------------------*/ + +static void prvTransmitSampleValues( void ) +{ +unsigned portLONG ulStatus; +static portLONG lState = usbXUP; + +/* Variables to hold dummy x, y and z joystick axis data. */ +static signed portCHAR x = 0, y = 0, z = 0; + + /* Generate some sample data in the x and y axis - draw a square. */ + switch( lState ) + { + case usbXUP : x += usbDATA_INC; + if( x >= usbMAX_COORD ) + { + lState = usbYUP; + } + break; + + case usbXDOWN : x -= usbDATA_INC; + if( x <= -usbMAX_COORD ) + { + lState = usbYDOWN; + } + break; + + case usbYUP : y += usbDATA_INC; + if( y >= usbMAX_COORD ) + { + lState = usbXDOWN; + } + break; + + case usbYDOWN : y -= usbDATA_INC; + if( y <= -usbMAX_COORD ) + { + lState = usbXUP; + } + break; + } + + /* Just make the z axis go up and down. */ + z += usbDATA_INC; + + /* Can we place data in the fifo? */ + if( !( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] & AT91C_UDP_TXPKTRDY ) ) + { + /* Write our sample data to the fifo. */ + AT91C_BASE_UDP->UDP_FDR[ usbEND_POINT_1 ] = x; + AT91C_BASE_UDP->UDP_FDR[ usbEND_POINT_1 ] = y; + AT91C_BASE_UDP->UDP_FDR[ usbEND_POINT_1 ] = z; + + /* Send the data. */ + portENTER_CRITICAL(); + { + ulStatus = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ]; + usbCSR_SET_BIT( &ulStatus, ( AT91C_UDP_TXPKTRDY ) ); + AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] = ulStatus; + } + portEXIT_CRITICAL(); + } +} +/*-----------------------------------------------------------*/ + +static void prvUSBTransmitNull( void ) +{ +unsigned portLONG ulStatus; + + /* Wait until the FIFO is free - even though we are not going to use it. + THERE IS NO TIMEOUT HERE! */ + while( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] & AT91C_UDP_TXPKTRDY ) + { + vTaskDelay( usbSHORTEST_DELAY ); + } + + portENTER_CRITICAL(); + { + /* Set the length of data to send to equal the index of the next byte + to send. This will prevent the ACK to this NULL packet causing any + further data transmissions. */ + pxCharsForTx.ulTotalDataLength = pxCharsForTx.ulNextCharIndex; + + /* Set the TXPKTRDY bit to cause a transmission with no data. */ + ulStatus = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ]; + usbCSR_SET_BIT( &ulStatus, ( AT91C_UDP_TXPKTRDY ) ); + AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulStatus; + } + portEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +static void prvSendStall( void ) +{ +unsigned portLONG ulStatus; + + portENTER_CRITICAL(); + { + /* Force a stall by simply setting the FORCESTALL bit in the CSR. */ + ulStatus = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ]; + usbCSR_SET_BIT( &ulStatus, AT91C_UDP_FORCESTALL ); + AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulStatus; + } + portEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +static void prvResetEndPoints( void ) +{ +unsigned portLONG ulTemp; + + eDriverState = eJUST_RESET; + + /* Reset all the end points. */ + AT91C_BASE_UDP->UDP_RSTEP = usbEND_POINT_RESET_MASK; + AT91C_BASE_UDP->UDP_RSTEP = ( unsigned portLONG ) 0x00; + + /* Enable data to be sent and received. */ + AT91C_BASE_UDP->UDP_FADDR = AT91C_UDP_FEN; + + /* Repair the configuration end point. */ + portENTER_CRITICAL(); + { + ulTemp = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ]; + usbCSR_SET_BIT( &ulTemp, ( ( unsigned portLONG ) ( AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_CTRL ) ) ); + AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulTemp; + AT91F_UDP_EnableIt( AT91C_BASE_UDP, AT91C_UDP_EPINT0 ); + } + portEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +static void prvProcessEndPoint0Interrupt( xISRStatus *pxMessage ) +{ + if( pxMessage->ulCSR0 & AT91C_UDP_RX_DATA_BK0 ) + { + /* We only expect to receive zero length data here as ACK's. + Set the data pointer to the end of the current Tx packet to + ensure we don't send out any more data. */ + pxCharsForTx.ulNextCharIndex = pxCharsForTx.ulTotalDataLength; + } + + if( pxMessage->ulCSR0 & AT91C_UDP_TXCOMP ) + { + /* We received a TX complete interrupt. What we do depends on + what we sent to get this interrupt. */ + + if( eDriverState == eJUST_GOT_CONFIG ) + { + /* We sent an acknowledgement of a SET_CONFIG request. We + are now at the end of the enumeration. */ + AT91C_BASE_UDP->UDP_GLBSTATE = AT91C_UDP_CONFG; + + /* Read the end point for data transfer. */ + portENTER_CRITICAL(); + { + unsigned portLONG ulTemp; + + ulTemp = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ]; + usbCSR_SET_BIT( &ulTemp, AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_INT_IN ); + AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] = ulTemp; + AT91F_UDP_EnableIt( AT91C_BASE_UDP, AT91C_UDP_EPINT1 ); + } + portEXIT_CRITICAL(); + + eDriverState = eREADY_TO_SEND; + } + else if( eDriverState == eJUST_GOT_ADDRESS ) + { + /* We sent an acknowledgement of a SET_ADDRESS request. Move + to the addressed state. */ + if( ulReceivedAddress != ( unsigned portLONG ) 0 ) + { + AT91C_BASE_UDP->UDP_GLBSTATE = AT91C_UDP_FADDEN; + } + else + { + AT91C_BASE_UDP->UDP_GLBSTATE = 0; + } + + AT91C_BASE_UDP->UDP_FADDR = ( AT91C_UDP_FEN | ulReceivedAddress ); + eDriverState = eNOTHING; + } + else + { + /* The TXCOMP was not for any special type of transmission. See + if there is any more data to send. */ + prvSendNextSegment(); + } + } + + if( pxMessage->ulCSR0 & AT91C_UDP_RXSETUP ) + { + xUSB_REQUEST xRequest; + unsigned portCHAR ucRequest; + unsigned portLONG ulRxBytes; + + /* A data packet is available. */ + ulRxBytes = pxMessage->ulCSR0 >> 16; + ulRxBytes &= usbRX_COUNT_MASK; + + if( ulRxBytes >= usbEXPECTED_NUMBER_OF_BYTES ) + { + /* Create an xUSB_REQUEST variable from the raw bytes array. */ + + xRequest.ucReqType = pxMessage->ucFifoData[ usbREQUEST_TYPE_INDEX ]; + xRequest.ucRequest = pxMessage->ucFifoData[ usbREQUEST_INDEX ]; + + /* NOT PORTABLE CODE! */ + xRequest.usValue = pxMessage->ucFifoData[ usbVALUE_HIGH_BYTE ]; + xRequest.usValue <<= 8; + xRequest.usValue |= pxMessage->ucFifoData[ usbVALUE_LOW_BYTE ]; + + xRequest.usIndex = pxMessage->ucFifoData[ usbINDEX_HIGH_BYTE ]; + xRequest.usIndex <<= 8; + xRequest.usIndex |= pxMessage->ucFifoData[ usbINDEX_LOW_BYTE ]; + + xRequest.usLength = pxMessage->ucFifoData[ usbLENGTH_HIGH_BYTE ]; + xRequest.usLength <<= 8; + xRequest.usLength |= pxMessage->ucFifoData[ usbLENGTH_LOW_BYTE ]; + + /* Manipulate the ucRequestType and the ucRequest parameters to + generate a zero based request selection. This is just done to + break up the requests into subsections for clarity. The + alternative would be to have more huge switch statement that would + be difficult to optimise. */ + ucRequest = ( ( xRequest.ucReqType & 0x60 ) >> 3 ); + ucRequest |= ( xRequest.ucReqType & 0x03 ); + + switch( ucRequest ) + { + case usbSTANDARD_DEVICE_REQUEST: + /* Standard Device request */ + prvHandleStandardDeviceRequest( &xRequest ); + break; + + case usbSTANDARD_INTERFACE_REQUEST: + /* Standard Interface request */ + prvHandleStandardInterfaceRequest( &xRequest ); + break; + + case usbSTANDARD_END_POINT_REQUEST: + /* Standard Endpoint request */ + prvHandleStandardEndPointRequest( &xRequest ); + break; + + case usbCLASS_INTERFACE_REQUEST: + /* Class Interface request */ + prvHandleClassInterfaceRequest( &xRequest ); + break; + + default: /* This is not something we want to respond to. */ + prvSendStall(); + } + } + } +} +/*-----------------------------------------------------------*/ + +static void prvGetStandardDeviceDescriptor( xUSB_REQUEST *pxRequest ) +{ + /* The type is in the high byte. Return whatever has been requested. */ + switch( ( pxRequest->usValue & 0xff00 ) >> 8 ) + { + case usbDESCRIPTOR_TYPE_DEVICE: + prvSendControlData( ( unsigned portCHAR * ) &pxDeviceDescriptor, pxRequest->usLength, sizeof( pxDeviceDescriptor ), pdTRUE ); + break; + + case usbDESCRIPTOR_TYPE_CONFIGURATION: + prvSendControlData( ( unsigned portCHAR * ) &( pxConfigDescriptor ), pxRequest->usLength, sizeof( pxConfigDescriptor ), pdTRUE ); + break; + + case usbDESCRIPTOR_TYPE_STRING: + + /* The index to the string descriptor is the lower byte. */ + switch( pxRequest->usValue & 0xff ) + { + case usbLANGUAGE_STRING: + prvSendControlData( ( unsigned portCHAR * ) &pxLanguageStringDescriptor, pxRequest->usLength, sizeof(pxLanguageStringDescriptor), pdTRUE ); + break; + + case usbMANUFACTURER_STRING: + prvSendControlData( ( unsigned portCHAR * ) &pxManufacturerStringDescriptor, pxRequest->usLength, sizeof( pxManufacturerStringDescriptor ), pdTRUE ); + break; + + case usbPRODUCT_STRING: + prvSendControlData( ( unsigned portCHAR * ) &pxProductStringDescriptor, pxRequest->usLength, sizeof( pxProductStringDescriptor ), pdTRUE ); + break; + + case usbCONFIGURATION_STRING: + prvSendControlData( ( unsigned portCHAR * ) &pxConfigurationStringDescriptor, pxRequest->usLength, sizeof( pxConfigurationStringDescriptor ), pdTRUE ); + break; + + case usbINTERFACE_STRING: + prvSendControlData( ( unsigned portCHAR * ) &pxInterfaceStringDescriptor, pxRequest->usLength, sizeof( pxInterfaceStringDescriptor ), pdTRUE ); + break; + + default: + /* Don't know what this string is. */ + prvSendStall(); + break; + } + + break; + + default: + /* We are not responding to anything else. */ + prvSendStall(); + break; + } +} +/*-----------------------------------------------------------*/ + +static void prvHandleStandardDeviceRequest( xUSB_REQUEST *pxRequest ) +{ +unsigned portSHORT usStatus = 0; + + switch( pxRequest->ucRequest ) + { + case usbGET_STATUS_REQUEST: + /* Just send two byte dummy status. */ + prvSendControlData( ( unsigned portCHAR * ) &usStatus, sizeof( usStatus ), sizeof( usStatus ), pdFALSE ); + break; + + case usbGET_DESCRIPTOR_REQUEST: + /* Send device descriptor */ + prvGetStandardDeviceDescriptor( pxRequest ); + break; + + case usbGET_CONFIGURATION_REQUEST: + /* Send selected device configuration */ + prvSendControlData( ( unsigned portCHAR * ) &ucUSBConfig, sizeof( ucUSBConfig ), sizeof( ucUSBConfig ), pdFALSE ); + break; + + case usbSET_FEATURE_REQUEST: + prvUSBTransmitNull(); + break; + + case usbSET_ADDRESS_REQUEST: + + /* Acknowledge the SET_ADDRESS, but (according to the manual) we + cannot actually move to the addressed state until we get a TXCOMP + interrupt from this NULL packet. Therefore we just remember the + address and set our state so we know we have received the address. */ + prvUSBTransmitNull(); + eDriverState = eJUST_GOT_ADDRESS; + ulReceivedAddress = ( unsigned portLONG ) pxRequest->usValue; + break; + + case usbSET_CONFIGURATION_REQUEST: + + /* Acknowledge the SET_CONFIGURATION, but (according to the manual) + we cannot actually move to the configured state until we get a + TXCOMP interrupt from this NULL packet. Therefore we just remember the + config and set our state so we know we have received the go ahead. */ + ucUSBConfig = ( unsigned portCHAR ) ( pxRequest->usValue & 0xff ); + eDriverState = eJUST_GOT_CONFIG; + prvUSBTransmitNull(); + break; + + default: + + /* We don't answer to anything else. */ + prvSendStall(); + break; + } +} +/*-----------------------------------------------------------*/ + +static void prvHandleClassInterfaceRequest( xUSB_REQUEST *pxRequest ) +{ + switch( pxRequest->ucRequest ) + { + case usbSET_IDLE_REQUEST: + prvUSBTransmitNull(); + break; + + /* This minimal implementation ignores these. */ + case usbGET_REPORT_REQUEST: + case usbGET_IDLE_REQUEST: + case usbGET_PROTOCOL_REQUEST: + case usbSET_REPORT_REQUEST: + case usbSET_PROTOCOL_REQUEST: + default: + + prvSendStall(); + break; + } +} +/*-----------------------------------------------------------*/ + +static void prvGetStandardInterfaceDescriptor( xUSB_REQUEST *pxRequest ) +{ + switch( ( pxRequest->usValue & ( unsigned portSHORT ) 0xff00 ) >> 8 ) + { + case usbHID_REPORT_DESCRIPTOR: + prvSendControlData( ( unsigned portCHAR * ) pxReportDescriptor, pxRequest->usLength, sizeof( pxReportDescriptor ), pdTRUE ); + break; + + default: + + /* Don't expect to send any others. */ + prvSendStall(); + break; + } +} +/*-----------------------------------------------------------*/ + +static void prvHandleStandardInterfaceRequest( xUSB_REQUEST *pxRequest ) +{ +unsigned portSHORT usStatus = 0; + + switch( pxRequest->ucRequest ) + { + case usbGET_STATUS_REQUEST: + /* Send dummy 2 bytes. */ + prvSendControlData( ( unsigned portCHAR * ) &usStatus, sizeof( usStatus ), sizeof( usStatus ), pdFALSE ); + break; + + case usbGET_DESCRIPTOR_REQUEST: + prvGetStandardInterfaceDescriptor( pxRequest ); + break; + + /* This minimal implementation does not respond to these. */ + case usbGET_INTERFACE_REQUEST: + case usbSET_FEATURE_REQUEST: + case usbSET_INTERFACE_REQUEST: + + default: + prvSendStall(); + break; + } +} +/*-----------------------------------------------------------*/ + +static void prvHandleStandardEndPointRequest( xUSB_REQUEST *pxRequest ) +{ + switch( pxRequest->ucRequest ) + { + /* This minimal implementation does not expect to respond to these. */ + case usbGET_STATUS_REQUEST: + case usbCLEAR_FEATURE_REQUEST: + case usbSET_FEATURE_REQUEST: + + default: + prvSendStall(); + break; + } +} +/*-----------------------------------------------------------*/ + +static void vInitUSBInterface( void ) +{ +volatile unsigned portLONG ulTemp; + + /* Create the queue used to communicate between the USB ISR and task. */ + xUSBInterruptQueue = xQueueCreate( usbQUEUE_LENGTH + 1, sizeof( xISRStatus * ) ); + + /* Initialise a few state variables. */ + pxCharsForTx.ulNextCharIndex = ( unsigned portLONG ) 0; + ucUSBConfig = ( unsigned portCHAR ) 0; + eDriverState = eNOTHING; + + /* HARDWARE SETUP */ + + /* Set the PLL USB Divider */ + AT91C_BASE_CKGR->CKGR_PLLR |= AT91C_CKGR_USBDIV_1; + + /* Enables the 48MHz USB clock UDPCK and System Peripheral USB Clock. */ + AT91C_BASE_PMC->PMC_SCER = AT91C_PMC_UDP; + AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_UDP); + + /* Setup the PIO for the USB pull up resistor. */ + AT91F_PIO_CfgOutput(AT91C_BASE_PIOA,AT91C_PIO_PA16); + + /* Start without the pullup - this will get set at the end of this + function. */ + AT91F_PIO_SetOutput( AT91C_BASE_PIOA, AT91C_PIO_PA16 ); + + /* When using the USB debugger the peripheral registers do not always get + set to the correct default values. To make sure set the relevant registers + manually here. */ + AT91C_BASE_UDP->UDP_IDR = ( unsigned portLONG ) 0xffffffff; + AT91C_BASE_UDP->UDP_ICR = ( unsigned portLONG ) 0xffffffff; + AT91C_BASE_UDP->UDP_CSR[ 0 ] = ( unsigned portLONG ) 0x00; + AT91C_BASE_UDP->UDP_CSR[ 1 ] = ( unsigned portLONG ) 0x00; + AT91C_BASE_UDP->UDP_GLBSTATE = 0; + AT91C_BASE_UDP->UDP_FADDR = 0; + + /* Enable the transceiver. */ + AT91C_UDP_TRANSCEIVER_ENABLE = 0; + + /* Enable the USB interrupts - other interrupts get enabled as the + enumeration process progresses. */ + AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_UDP, usbINTERRUPT_PRIORITY, AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, ( void (*)( void ) ) vUSBISREntry ); + AT91F_AIC_EnableIt( AT91C_BASE_AIC, AT91C_ID_UDP ); + + /* Wait a short while before making our presence known. */ + vTaskDelay( usbINIT_DELAY ); + AT91F_PIO_ClearOutput(AT91C_BASE_PIOA, AT91C_PIO_PA16 ); +} +/*-----------------------------------------------------------*/ + +static void prvSendControlData( unsigned portCHAR *pucData, unsigned portSHORT usRequestedLength, unsigned portLONG ulLengthToSend, portLONG lSendingDescriptor ) +{ + if( ( ( unsigned portLONG ) usRequestedLength < ulLengthToSend ) ) + { + /* Cap the data length to that requested. */ + ulLengthToSend = ( unsigned portSHORT ) usRequestedLength; + } + else if( ( ulLengthToSend < ( unsigned portLONG ) usRequestedLength ) && lSendingDescriptor ) + { + /* We are sending a descriptor. If the descriptor is an exact + multiple of the FIFO length then it will have to be terminated + with a NULL packet. Set the state to indicate this if + necessary. */ + if( ( ulLengthToSend % usbFIFO_LENGTH ) == 0 ) + { + eDriverState = eSENDING_EVEN_DESCRIPTOR; + } + } + + /* Here we assume that the previous message has been sent. THERE IS NO + BUFFER OVERFLOW PROTECTION HERE. + + Copy the data to send into the buffer as we cannot send it all at once + (if it is greater than 8 bytes in length). */ + memcpy( pxCharsForTx.ucTxBuffer, pucData, ulLengthToSend ); + + /* Reinitialise the buffer index so we start sending from the start of + the data. */ + pxCharsForTx.ulTotalDataLength = ulLengthToSend; + pxCharsForTx.ulNextCharIndex = ( unsigned portLONG ) 0; + + /* Send the first 8 bytes now. The rest will get sent in response to + TXCOMP interrupts. */ + prvSendNextSegment(); +} +/*-----------------------------------------------------------*/ + +static void prvSendNextSegment( void ) +{ +volatile unsigned portLONG ulNextLength, ulStatus, ulLengthLeftToSend; + + /* Is there any data to send? */ + if( pxCharsForTx.ulTotalDataLength > pxCharsForTx.ulNextCharIndex ) + { + ulLengthLeftToSend = pxCharsForTx.ulTotalDataLength - pxCharsForTx.ulNextCharIndex; + + /* We can only send 8 bytes to the fifo at a time. */ + if( ulLengthLeftToSend > usbFIFO_LENGTH ) + { + ulNextLength = usbFIFO_LENGTH; + } + else + { + ulNextLength = ulLengthLeftToSend; + } + + /* Wait until we can place data in the fifo. THERE IS NO TIMEOUT + HERE! */ + while( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] & AT91C_UDP_TXPKTRDY ) + { + vTaskDelay( usbSHORTEST_DELAY ); + } + + /* Write the data to the FIFO. */ + while( ulNextLength > ( unsigned portLONG ) 0 ) + { + AT91C_BASE_UDP->UDP_FDR[ usbEND_POINT_0 ] = pxCharsForTx.ucTxBuffer[ pxCharsForTx.ulNextCharIndex ]; + + ulNextLength--; + pxCharsForTx.ulNextCharIndex++; + } + + /* Start the transmission. */ + portENTER_CRITICAL(); + { + ulStatus = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ]; + usbCSR_SET_BIT( &ulStatus, ( ( unsigned portLONG ) 0x10 ) ); + AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulStatus; + } + portEXIT_CRITICAL(); + } + else + { + /* There is no data to send. If we were sending a descriptor and the + descriptor was an exact multiple of the max packet size then we need + to send a null to terminate the transmission. */ + if( eDriverState == eSENDING_EVEN_DESCRIPTOR ) + { + prvUSBTransmitNull(); + eDriverState = eNOTHING; + } + } +} + + + diff --git a/20080212/Demo/ARM7_AT91SAM7S64_IAR/USB/USBSample.h b/20080212/Demo/ARM7_AT91SAM7S64_IAR/USB/USBSample.h new file mode 100644 index 000000000..add756985 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7S64_IAR/USB/USBSample.h @@ -0,0 +1,8 @@ +#ifndef USB_DEMO_H +#define USB_DEMO_H + +void vUSBDemoTask( void *pvParameters ); + + +#endif + diff --git a/20080212/Demo/ARM7_AT91SAM7S64_IAR/USB/USB_ISR.s79 b/20080212/Demo/ARM7_AT91SAM7S64_IAR/USB/USB_ISR.s79 new file mode 100644 index 000000000..8263f71ff --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7S64_IAR/USB/USB_ISR.s79 @@ -0,0 +1,24 @@ + RSEG ICODE:CODE + CODE32 + + EXTERN vUSB_ISR + PUBLIC vUSBISREntry + +; Wrapper for the USB interrupt service routine. This can cause a +; context switch so requires an assembly wrapper. + +; Defines the portSAVE_CONTEXT and portRESTORE_CONTEXT macros. +#include "ISR_Support.h" + +vUSBISREntry: + + portSAVE_CONTEXT ; Save the context of the current task. + + bl vUSB_ISR ; Call the ISR routine. + + portRESTORE_CONTEXT ; Restore the context of the current task - + ; which may be different to the task that + ; was interrupted. + + END + diff --git a/20080212/Demo/ARM7_AT91SAM7S64_IAR/main.c b/20080212/Demo/ARM7_AT91SAM7S64_IAR/main.c new file mode 100644 index 000000000..9519b3e6b --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7S64_IAR/main.c @@ -0,0 +1,262 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. + The processor MUST be in supervisor mode when vTaskStartScheduler is + called. The demo applications included in the FreeRTOS.org download switch + to supervisor mode prior to main being called. If you are not using one of + these demo application projects then ensure Supervisor mode is used. +*/ + +/* + * Creates all the demo application tasks, then starts the scheduler. The WEB + * documentation provides more details of the demo application tasks. The SAM7 + * includes a sample USB that emulates a Joystick input to a USB host. + * + * Main.c also creates a task called "Check". This only executes every three + * seconds but has the highest priority so is guaranteed to get processor time. + * Its main function is to check that all the other tasks are still operational. + * Each task (other than the "flash" tasks) maintains a unique count that is + * incremented each time the task successfully completes its function. Should + * any error occur within such a task the count is permanently halted. The + * check task inspects the count of each task to ensure it has changed since + * the last time the check task executed. If all the count variables have + * changed all the tasks are still executing error free, and the check task + * toggles the onboard LED. Should any task contain an error at any time + * the LED toggle rate will change from 3 seconds to 500ms. + * + */ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo application includes. */ +#include "flash.h" +#include "integer.h" +#include "PollQ.h" +#include "BlockQ.h" +#include "semtest.h" +#include "dynamic.h" +#include "partest.h" +#include "comtest2.h" +#include "USB/USBSample.h" + +/* Priorities for the demo application tasks. */ +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainUSB_PRIORITY ( tskIDLE_PRIORITY + 2 ) + +/* Constants required by the 'Check' task. */ +#define mainNO_ERROR_FLASH_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS ) +#define mainERROR_FLASH_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS ) +#define mainCHECK_TASK_LED ( 3 ) + +/* Constants for the ComTest tasks. */ +#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 115200 ) +#define mainCOM_TEST_LED ( 4 ) /* Off the board. */ + +/* + * The task that executes at the highest priority and calls + * prvCheckOtherTasksAreStillRunning(). See the description at the top + * of the file. + */ +static void vErrorChecks( void *pvParameters ); + +/* + * Configure the processor for use with the Atmel demo board. Setup is minimal + * as the low level init function (called from the startup asm file) takes care + * of most things. + */ +static void prvSetupHardware( void ); + +/* + * Checks that all the demo application tasks are still executing without error + * - as described at the top of the file. + */ +static portLONG prvCheckOtherTasksAreStillRunning( void ); + + +/*-----------------------------------------------------------*/ + +/* + * Starts all the other tasks, then starts the scheduler. + */ +void main( void ) +{ + /* Setup any hardware that has not already been configured by the low + level init routines. */ + prvSetupHardware(); + + /* Initialise the LED outputs for use by the demo application tasks. */ + vParTestInitialise(); + + /* Start all the standard demo application tasks. */ + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vStartDynamicPriorityTasks(); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); + + /* Also start the USB demo which is just for the SAM7. */ + xTaskCreate( vUSBDemoTask, "USB", configMINIMAL_STACK_SIZE, NULL, mainUSB_PRIORITY, NULL ); + + /* Start the check task - which is defined in this file. */ + xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Start the scheduler. + + NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. + The processor MUST be in supervisor mode when vTaskStartScheduler is + called. The demo applications included in the FreeRTOS.org download switch + to supervisor mode prior to main being called. If you are not using one of + these demo application projects then ensure Supervisor mode is used here. */ + + vTaskStartScheduler(); + + /* We should never get here as control is now taken by the scheduler. */ + return; +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* When using the JTAG debugger the hardware is not always initialised to + the correct default state. This line just ensures that this does not + cause all interrupts to be masked at the start. */ + AT91C_BASE_AIC->AIC_EOICR = 0; + + /* Most setup is performed by the low level init function called from the + startup asm file. */ + + /* Configure the PIO Lines corresponding to LED1 to LED4 to be outputs as + well as the UART Tx line. */ + AT91F_PIO_CfgOutput( AT91C_BASE_PIOA, LED_MASK ); + + /* Enable the peripheral clock. */ + AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, 1 << AT91C_ID_PIOA ); +} +/*-----------------------------------------------------------*/ + +static void vErrorChecks( void *pvParameters ) +{ +portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD; + + /* The parameters are not used in this task. */ + ( void ) pvParameters; + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. If an error is detected then the delay period + is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so + the on board LED flash rate will increase. */ + + for( ;; ) + { + /* Delay until it is time to execute again. */ + vTaskDelay( xDelayPeriod ); + + /* Check all the standard demo application tasks are executing without + error. */ + if( prvCheckOtherTasksAreStillRunning() != pdPASS ) + { + /* An error has been detected in one of the tasks - flash faster. */ + xDelayPeriod = mainERROR_FLASH_PERIOD; + } + + vParTestToggleLED( mainCHECK_TASK_LED ); + } +} +/*-----------------------------------------------------------*/ + +static portLONG prvCheckOtherTasksAreStillRunning( void ) +{ +portLONG lReturn = ( portLONG ) pdPASS; + + /* Check all the demo tasks (other than the flash tasks) to ensure + that they are all still running, and that none of them have detected + an error. */ + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + return lReturn; +} +/*-----------------------------------------------------------*/ + + diff --git a/20080212/Demo/ARM7_AT91SAM7S64_IAR/resource/SAM7.mac b/20080212/Demo/ARM7_AT91SAM7S64_IAR/resource/SAM7.mac new file mode 100644 index 000000000..b1c753dc3 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7S64_IAR/resource/SAM7.mac @@ -0,0 +1,180 @@ +// --------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// --------------------------------------------------------- +// The software is delivered "AS IS" without warranty or +// condition of any kind, either express, implied or +// statutory. This includes without limitation any warranty +// or condition with respect to merchantability or fitness +// for any particular purpose, or against the infringements of +// intellectual property rights of others. +// --------------------------------------------------------- +// File: SAM7.mac +// +// User setup file for CSPY debugger to simulate interrupt +// driven Fibonacchi data input. +// 1.1 16/Jun/04 JPP : Creation +// +// $Revision: 1.3 $ +// +// --------------------------------------------------------- + +__var i; +__var pt; + +execUserPreload() +{ +//* Set the RAM memory at 0x0020 0000 for code AT 0 flash area + CheckRemap(); +//* Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R + i=__readMemory32(0xFFFFF240,"Memory"); + __message " ---------------------------------------- Chip ID 0x",i:%X; + i=__readMemory32(0xFFFFF244,"Memory"); + __message " ---------------------------------------- Extention 0x",i:%X; +//* Get the chip status + +//* Init AIC + AIC(); +//* Watchdog Disable + Watchdog(); + +} + + +//----------------------------------------------------------------------------- +// Watchdog +//------------------------------- +// Normally, the Watchdog is enable at the reset for load it's preferable to +// Disable. +//----------------------------------------------------------------------------- +Watchdog() +{ +//* Watchdog Disable +// AT91C_BASE_WDTC->WDTC_WDMR= AT91C_SYSC_WDDIS; + __writeMemory32(0x00008000,0xFFFFFD44,"Memory"); + __message "------------------------------- Watchdog Disable ----------------------------------------"; +} + + +//----------------------------------------------------------------------------- +// Check Remap +//------------- +//----------------------------------------------------------------------------- +CheckRemap() +{ +//* Read the value at 0x0 + i=__readMemory32(0x00000000,"Memory"); + i=i+1; + __writeMemory32(i,0x00,"Memory"); + pt=__readMemory32(0x00000000,"Memory"); + + if (i == pt) + { + __message "------------------------------- The Remap is done ----------------------------------------"; +//* Toggel RESET The remap + __writeMemory32(0x00000001,0xFFFFFF00,"Memory"); + + } else { + __message "------------------------------- The Remap is NOT -----------------------------------------"; + } + +} + + +execUserSetup() +{ + ini(); + __message "-------------------------------Set PC ----------------------------------------"; + __writeMemory32(0x00000000,0xB4,"Register"); +} + + + +//----------------------------------------------------------------------------- +// Reset the Interrupt Controller +//------------------------------- +// Normally, the code is executed only if a reset has been actually performed. +// So, the AIC initialization resumes at setting up the default vectors. +//----------------------------------------------------------------------------- +AIC() +{ +// Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF; + __writeMemory32(0xFFFFFFFF,0xFFFFF124,"Memory"); + + for (i=0;i < 8; i++) + { + // AT91C_BASE_AIC->AIC_EOICR + pt = __readMemory32(0xFFFFF130,"Memory"); + + } + __message "------------------------------- AIC INIT ---------------------------------------------"; +} + +ini() +{ +__writeMemory32(0x0,0x00,"Register"); +__writeMemory32(0x0,0x04,"Register"); +__writeMemory32(0x0,0x08,"Register"); +__writeMemory32(0x0,0x0C,"Register"); +__writeMemory32(0x0,0x10,"Register"); +__writeMemory32(0x0,0x14,"Register"); +__writeMemory32(0x0,0x18,"Register"); +__writeMemory32(0x0,0x1C,"Register"); +__writeMemory32(0x0,0x20,"Register"); +__writeMemory32(0x0,0x24,"Register"); +__writeMemory32(0x0,0x28,"Register"); +__writeMemory32(0x0,0x2C,"Register"); +__writeMemory32(0x0,0x30,"Register"); +__writeMemory32(0x0,0x34,"Register"); +__writeMemory32(0x0,0x38,"Register"); + +// Set CPSR +__writeMemory32(0x0D3,0x98,"Register"); + + +} + +RG() +{ + +i=__readMemory32(0x00,"Register"); __message "R00 0x",i:%X; +i=__readMemory32(0x04,"Register"); __message "R01 0x",i:%X; +i=__readMemory32(0x08,"Register"); __message "R02 0x",i:%X; +i=__readMemory32(0x0C,"Register"); __message "R03 0x",i:%X; +i=__readMemory32(0x10,"Register"); __message "R04 0x",i:%X; +i=__readMemory32(0x14,"Register"); __message "R05 0x",i:%X; +i=__readMemory32(0x18,"Register"); __message "R06 0x",i:%X; +i=__readMemory32(0x1C,"Register"); __message "R07 0x",i:%X; +i=__readMemory32(0x20,"Register"); __message "R08 0x",i:%X; +i=__readMemory32(0x24,"Register"); __message "R09 0x",i:%X; +i=__readMemory32(0x28,"Register"); __message "R10 0x",i:%X; +i=__readMemory32(0x2C,"Register"); __message "R11 0x",i:%X; +i=__readMemory32(0x30,"Register"); __message "R12 0x",i:%X; +i=__readMemory32(0x34,"Register"); __message "R13 0x",i:%X; +i=__readMemory32(0x38,"Register"); __message "R14 0x",i:%X; +i=__readMemory32(0x3C,"Register"); __message "R13 SVC 0x",i:%X; +i=__readMemory32(0x40,"Register"); __message "R14 SVC 0x",i:%X; +i=__readMemory32(0x44,"Register"); __message "R13 ABT 0x",i:%X; +i=__readMemory32(0x48,"Register"); __message "R14 ABT 0x",i:%X; +i=__readMemory32(0x4C,"Register"); __message "R13 UND 0x",i:%X; +i=__readMemory32(0x50,"Register"); __message "R14 UND 0x",i:%X; +i=__readMemory32(0x54,"Register"); __message "R13 IRQ 0x",i:%X; +i=__readMemory32(0x58,"Register"); __message "R14 IRQ 0x",i:%X; +i=__readMemory32(0x5C,"Register"); __message "R08 FIQ 0x",i:%X; +i=__readMemory32(0x60,"Register"); __message "R09 FIQ 0x",i:%X; +i=__readMemory32(0x64,"Register"); __message "R10 FIQ 0x",i:%X; +i=__readMemory32(0x68,"Register"); __message "R11 FIQ 0x",i:%X; +i=__readMemory32(0x6C,"Register"); __message "R12 FIQ 0x",i:%X; +i=__readMemory32(0x70,"Register"); __message "R13 FIQ 0x",i:%X; +i=__readMemory32(0x74,"Register"); __message "R14 FIQ0x",i:%X; +i=__readMemory32(0x98,"Register"); __message "CPSR ",i:%X; +i=__readMemory32(0x94,"Register"); __message "SPSR ",i:%X; +i=__readMemory32(0x9C,"Register"); __message "SPSR ABT ",i:%X; +i=__readMemory32(0xA0,"Register"); __message "SPSR ABT ",i:%X; +i=__readMemory32(0xA4,"Register"); __message "SPSR UND ",i:%X; +i=__readMemory32(0xA8,"Register"); __message "SPSR IRQ ",i:%X; +i=__readMemory32(0xAC,"Register"); __message "SPSR FIQ ",i:%X; + +i=__readMemory32(0xB4,"Register"); __message "PC 0x",i:%X; + +} + diff --git a/20080212/Demo/ARM7_AT91SAM7S64_IAR/resource/SAM7_RAM.mac b/20080212/Demo/ARM7_AT91SAM7S64_IAR/resource/SAM7_RAM.mac new file mode 100644 index 000000000..7471d73b7 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7S64_IAR/resource/SAM7_RAM.mac @@ -0,0 +1,211 @@ +// --------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// --------------------------------------------------------- +// The software is delivered "AS IS" without warranty or +// condition of any kind, either express, implied or +// statutory. This includes without limitation any warranty +// or condition with respect to merchantability or fitness +// for any particular purpose, or against the infringements of +// intellectual property rights of others. +// --------------------------------------------------------- +// File: SAM7_RAM.mac +// +// User setup file for CSPY debugger to simulate interrupt +// driven Fibonacchi data input. +// 1.1 16/Jun/04 JPP : Creation +// 1.2 27/Aug/04 JPP : PLL setting +// +// $Revision: 1.3 $ +// +// --------------------------------------------------------- + +__var i; +__var pt; + +execUserPreload() +{ +//* + PllSetting(); +//* Set the RAM memory at 0x0020 0000 for code AT 0 flash area + CheckNoRemap(); +//* Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R + i=__readMemory32(0xFFFFF240,"Memory"); + __message " ---------------------------------------- Chip ID 0x",i:%X; + i=__readMemory32(0xFFFFF244,"Memory"); + __message " ---------------------------------------- Extention 0x",i:%X; + i=__readMemory32(0xFFFFFF6C,"Memory"); + __message " ---------------------------------------- Flash Version 0x",i:%X; +//* Get the chip status + +//* Init AIC + AIC(); +//* Watchdog Disable + Watchdog(); +} +//----------------------------------------------------------------------------- +// PllSetting +//------------------------------- +// Set PLL +//----------------------------------------------------------------------------- +PllSetting() +{ +// -1- Enabling the Main Oscillator: +//*#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register +//*#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register +//*#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register + +//*pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) | //0x0000 0600 +// AT91C_CKGR_MOSCEN )); //0x0000 0001 +__writeMemory32(0x00000601,0xFFFFFC20,"Memory"); + +// -2- Wait +// -3- Setting PLL and divider: +// - div by 5 Fin = 3,6864 =(18,432 / 5) +// - Mul 25+1: Fout = 95,8464 =(3,6864 *26) +// for 96 MHz the erroe is 0.16% +// Field out NOT USED = 0 +// PLLCOUNT pll startup time esrtimate at : 0.844 ms +// PLLCOUNT 28 = 0.000844 /(1/32768) +// pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 0x05) | //0x0000 0005 +// (AT91C_CKGR_PLLCOUNT & (28<<8)) //0x0000 1C00 +// (AT91C_CKGR_MUL & (25<<16))); //0x0019 0000 +__writeMemory32(0x00191C05,0xFFFFFC2C,"Memory"); +// -2- Wait +// -5- Selection of Master Clock and Processor Clock +// select the PLL clock divided by 2 +// pPMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | //0x0000 0003 +// AT91C_PMC_PRES_CLK_2 ; //0x0000 0004 +__writeMemory32(0x00000007,0xFFFFFC30,"Memory"); + + __message "------------------------------- PLL Enable ----------------------------------------"; +} + +//----------------------------------------------------------------------------- +// Watchdog +//------------------------------- +// Normally, the Watchdog is enable at the reset for load it's preferable to +// Disable. +//----------------------------------------------------------------------------- +Watchdog() +{ +//* Watchdog Disable +// AT91C_BASE_WDTC->WDTC_WDMR= AT91C_SYSC_WDDIS; + __writeMemory32(0x00008000,0xFFFFFD44,"Memory"); + __message "------------------------------- Watchdog Disable ----------------------------------------"; +} + +CheckNoRemap() +{ +//* Read the value at 0x0 + i=__readMemory32(0x00000000,"Memory"); + i=i+1; + __writeMemory32(i,0x00,"Memory"); + pt=__readMemory32(0x00000000,"Memory"); + + if (i == pt) + { + __message "------------------------------- The Remap is done ----------------------------------------"; + + } else { + __message "------------------------------- The Remap is NOT -----------------------------------------"; +//* Toggel RESET The remap + __writeMemory32(0x00000001,0xFFFFFF00,"Memory"); + } + +} + +execUserSetup() +{ + ini(); + __message "-------------------------------Set PC ----------------------------------------"; + __writeMemory32(0x00000000,0xB4,"Register"); +} + +//----------------------------------------------------------------------------- +// Reset the Interrupt Controller +//------------------------------- +// Normally, the code is executed only if a reset has been actually performed. +// So, the AIC initialization resumes at setting up the default vectors. +//----------------------------------------------------------------------------- +AIC() +{ +// Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF; + __writeMemory32(0xFFFFFFFF,0xFFFFF124,"Memory"); + + for (i=0;i < 8; i++) + { + // AT91C_BASE_AIC->AIC_EOICR + pt = __readMemory32(0xFFFFF130,"Memory"); + + } + __message "------------------------------- AIC INIT ---------------------------------------------"; +} + +ini() +{ +__writeMemory32(0x0,0x00,"Register"); +__writeMemory32(0x0,0x04,"Register"); +__writeMemory32(0x0,0x08,"Register"); +__writeMemory32(0x0,0x0C,"Register"); +__writeMemory32(0x0,0x10,"Register"); +__writeMemory32(0x0,0x14,"Register"); +__writeMemory32(0x0,0x18,"Register"); +__writeMemory32(0x0,0x1C,"Register"); +__writeMemory32(0x0,0x20,"Register"); +__writeMemory32(0x0,0x24,"Register"); +__writeMemory32(0x0,0x28,"Register"); +__writeMemory32(0x0,0x2C,"Register"); +__writeMemory32(0x0,0x30,"Register"); +__writeMemory32(0x0,0x34,"Register"); +__writeMemory32(0x0,0x38,"Register"); + +// Set CPSR +__writeMemory32(0x0D3,0x98,"Register"); + +} + +RG() +{ + +i=__readMemory32(0x00,"Register"); __message "R00 0x",i:%X; +i=__readMemory32(0x04,"Register"); __message "R01 0x",i:%X; +i=__readMemory32(0x08,"Register"); __message "R02 0x",i:%X; +i=__readMemory32(0x0C,"Register"); __message "R03 0x",i:%X; +i=__readMemory32(0x10,"Register"); __message "R04 0x",i:%X; +i=__readMemory32(0x14,"Register"); __message "R05 0x",i:%X; +i=__readMemory32(0x18,"Register"); __message "R06 0x",i:%X; +i=__readMemory32(0x1C,"Register"); __message "R07 0x",i:%X; +i=__readMemory32(0x20,"Register"); __message "R08 0x",i:%X; +i=__readMemory32(0x24,"Register"); __message "R09 0x",i:%X; +i=__readMemory32(0x28,"Register"); __message "R10 0x",i:%X; +i=__readMemory32(0x2C,"Register"); __message "R11 0x",i:%X; +i=__readMemory32(0x30,"Register"); __message "R12 0x",i:%X; +i=__readMemory32(0x34,"Register"); __message "R13 0x",i:%X; +i=__readMemory32(0x38,"Register"); __message "R14 0x",i:%X; +i=__readMemory32(0x3C,"Register"); __message "R13 SVC 0x",i:%X; +i=__readMemory32(0x40,"Register"); __message "R14 SVC 0x",i:%X; +i=__readMemory32(0x44,"Register"); __message "R13 ABT 0x",i:%X; +i=__readMemory32(0x48,"Register"); __message "R14 ABT 0x",i:%X; +i=__readMemory32(0x4C,"Register"); __message "R13 UND 0x",i:%X; +i=__readMemory32(0x50,"Register"); __message "R14 UND 0x",i:%X; +i=__readMemory32(0x54,"Register"); __message "R13 IRQ 0x",i:%X; +i=__readMemory32(0x58,"Register"); __message "R14 IRQ 0x",i:%X; +i=__readMemory32(0x5C,"Register"); __message "R08 FIQ 0x",i:%X; +i=__readMemory32(0x60,"Register"); __message "R09 FIQ 0x",i:%X; +i=__readMemory32(0x64,"Register"); __message "R10 FIQ 0x",i:%X; +i=__readMemory32(0x68,"Register"); __message "R11 FIQ 0x",i:%X; +i=__readMemory32(0x6C,"Register"); __message "R12 FIQ 0x",i:%X; +i=__readMemory32(0x70,"Register"); __message "R13 FIQ 0x",i:%X; +i=__readMemory32(0x74,"Register"); __message "R14 FIQ0x",i:%X; +i=__readMemory32(0x98,"Register"); __message "CPSR ",i:%X; +i=__readMemory32(0x94,"Register"); __message "SPSR ",i:%X; +i=__readMemory32(0x9C,"Register"); __message "SPSR ABT ",i:%X; +i=__readMemory32(0xA0,"Register"); __message "SPSR ABT ",i:%X; +i=__readMemory32(0xA4,"Register"); __message "SPSR UND ",i:%X; +i=__readMemory32(0xA8,"Register"); __message "SPSR IRQ ",i:%X; +i=__readMemory32(0xAC,"Register"); __message "SPSR FIQ ",i:%X; + +i=__readMemory32(0xB4,"Register"); __message "PC 0x",i:%X; + +} + diff --git a/20080212/Demo/ARM7_AT91SAM7S64_IAR/resource/at91SAM7S64_FLASH.icf b/20080212/Demo/ARM7_AT91SAM7S64_IAR/resource/at91SAM7S64_FLASH.icf new file mode 100644 index 000000000..def0cf0a1 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7S64_IAR/resource/at91SAM7S64_FLASH.icf @@ -0,0 +1,42 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000100; +define symbol __ICFEDIT_region_ROM_end__ = 0x0000FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x00200000; +define symbol __ICFEDIT_region_RAM_end__ = 0x00203FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x200; +define symbol __ICFEDIT_size_svcstack__ = 0x200; +define symbol __ICFEDIT_size_irqstack__ = 0x200; +define symbol __ICFEDIT_size_fiqstack__ = 0x4; +define symbol __ICFEDIT_size_undstack__ = 0x4; +define symbol __ICFEDIT_size_abtstack__ = 0x4; +define symbol __ICFEDIT_size_heap__ = 0x4; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; +define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; +define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK, + block UND_STACK, block ABT_STACK, block HEAP }; diff --git a/20080212/Demo/ARM7_AT91SAM7S64_IAR/rtosdemo.ewd b/20080212/Demo/ARM7_AT91SAM7S64_IAR/rtosdemo.ewd new file mode 100644 index 000000000..de6ec3f62 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7S64_IAR/rtosdemo.ewd @@ -0,0 +1,1225 @@ + + + + 1 + + Flash Debug + + ARM + + 1 + + C-SPY + 2 + + 15 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IARROM_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + JLINK_ID + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 1 + 1 + 1 + + + + + + + + MACRAIGOR_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin + 0 + + + + + Flash Bin + + ARM + + 1 + + C-SPY + 2 + + 15 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IARROM_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + JLINK_ID + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 1 + 1 + 1 + + + + + + + + MACRAIGOR_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin + 0 + + + + + + diff --git a/20080212/Demo/ARM7_AT91SAM7S64_IAR/rtosdemo.ewp b/20080212/Demo/ARM7_AT91SAM7S64_IAR/rtosdemo.ewp new file mode 100644 index 000000000..0b69546f9 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7S64_IAR/rtosdemo.ewp @@ -0,0 +1,1618 @@ + + + + 1 + + Flash Debug + + ARM + + 1 + + General + 3 + + 14 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 19 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 7 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 5 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Flash Bin + + ARM + + 1 + + General + 3 + + 14 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 19 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 7 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 5 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Demo Source + + $PROJ_DIR$\..\Common\Minimal\BlockQ.c + + + $PROJ_DIR$\..\Common\Minimal\comtest.c + + + $PROJ_DIR$\..\Common\Minimal\dynamic.c + + + $PROJ_DIR$\..\Common\Minimal\flash.c + + + $PROJ_DIR$\..\..\Source\portable\MemMang\heap_1.c + + + $PROJ_DIR$\..\Common\Minimal\integer.c + + + $PROJ_DIR$\main.c + + + $PROJ_DIR$\ParTest\ParTest.c + + + $PROJ_DIR$\..\Common\Minimal\PollQ.c + + + $PROJ_DIR$\..\Common\Minimal\semtest.c + + + $PROJ_DIR$\serial\serial.c + + + $PROJ_DIR$\serial\serialISR.s79 + + + $PROJ_DIR$\USB\USB_ISR.s79 + + + $PROJ_DIR$\USB\USBSample.c + + + + Scheduler Source + + $PROJ_DIR$\..\..\Source\list.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\AtmelSAM7S64\port.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\AtmelSAM7S64\portasm.s79 + + + $PROJ_DIR$\..\..\Source\queue.c + + + $PROJ_DIR$\..\..\Source\tasks.c + + + + System Files + + $PROJ_DIR$\SrcIAR\Cstartup.s + + + $PROJ_DIR$\SrcIAR\Cstartup_SAM7.c + + + + + diff --git a/20080212/Demo/ARM7_AT91SAM7S64_IAR/rtosdemo.eww b/20080212/Demo/ARM7_AT91SAM7S64_IAR/rtosdemo.eww new file mode 100644 index 000000000..2294aacb5 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7S64_IAR/rtosdemo.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\rtosdemo.ewp + + + + + diff --git a/20080212/Demo/ARM7_AT91SAM7S64_IAR/serial/serial.c b/20080212/Demo/ARM7_AT91SAM7S64_IAR/serial/serial.c new file mode 100644 index 000000000..5231cce34 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7S64_IAR/serial/serial.c @@ -0,0 +1,256 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0. +*/ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "queue.h" + +/* Demo application includes. */ +#include "serial.h" + +/*-----------------------------------------------------------*/ + +/* Location of the COM0 registers. */ +#define serCOM0 ( ( AT91PS_USART ) AT91C_BASE_US0 ) + +/* Interrupt control macros. */ +#define serINTERRUPT_LEVEL ( 5 ) +#define vInterruptOn() AT91F_US_EnableIt( serCOM0, AT91C_US_TXRDY | AT91C_US_RXRDY ) +#define vInterruptOff() AT91F_US_DisableIt( serCOM0, AT91C_US_TXRDY ) + +/* Misc constants. */ +#define serINVALID_QUEUE ( ( xQueueHandle ) 0 ) +#define serHANDLE ( ( xComPortHandle ) 1 ) +#define serNO_BLOCK ( ( portTickType ) 0 ) +#define serNO_TIMEGUARD ( ( unsigned portLONG ) 0 ) +#define serNO_PERIPHERAL_B_SETUP ( ( unsigned portLONG ) 0 ) + + +/* Queues used to hold received characters, and characters waiting to be +transmitted. */ +static xQueueHandle xRxedChars; +static xQueueHandle xCharsForTx; + +/*-----------------------------------------------------------*/ + +/* Interrupt entry point written in the assembler file serialISR.s79. */ +extern void vSerialISREntry( void ); + +/* The interrupt service routine - called from the assembly entry point. */ +__arm void vSerialISR( void ); + +/*-----------------------------------------------------------*/ + +/* + * See the serial2.h header file. + */ +xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) +{ +xComPortHandle xReturn = serHANDLE; +extern void ( vUART_ISR )( void ); + + /* Create the queues used to hold Rx and Tx characters. */ + xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + + /* If the queues were created correctly then setup the serial port + hardware. */ + if( ( xRxedChars != serINVALID_QUEUE ) && ( xCharsForTx != serINVALID_QUEUE ) ) + { + portENTER_CRITICAL(); + { + /* Enable the USART clock. */ + AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, 1 << AT91C_ID_US0 ); + + AT91F_PIO_CfgPeriph( AT91C_BASE_PIOA, ( ( unsigned portLONG ) AT91C_PA5_RXD0 ) | ( ( unsigned portLONG ) AT91C_PA6_TXD0 ), serNO_PERIPHERAL_B_SETUP ); + + /* Set the required protocol. */ + AT91F_US_Configure( serCOM0, configCPU_CLOCK_HZ, AT91C_US_ASYNC_MODE, ulWantedBaud, serNO_TIMEGUARD ); + + /* Enable Rx and Tx. */ + serCOM0->US_CR = AT91C_US_RXEN | AT91C_US_TXEN; + + /* Enable the Rx interrupts. The Tx interrupts are not enabled + until there are characters to be transmitted. */ + AT91F_US_EnableIt( serCOM0, AT91C_US_RXRDY ); + + /* Enable the interrupts in the AIC. */ + AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_US0, serINTERRUPT_LEVEL, AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, ( void (*)( void ) ) vSerialISREntry ); + AT91F_AIC_EnableIt( AT91C_BASE_AIC, AT91C_ID_US0 ); + } + portEXIT_CRITICAL(); + } + else + { + xReturn = ( xComPortHandle ) 0; + } + + /* This demo file only supports a single port but we have to return + something to comply with the standard demo header file. */ + return xReturn; +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) +{ + /* The port handle is not required as this driver only supports one port. */ + ( void ) pxPort; + + /* Get the next character from the buffer. Return false if no characters + are available, or arrive before xBlockTime expires. */ + if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) + { + return pdTRUE; + } + else + { + return pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength ) +{ +signed portCHAR *pxNext; + + /* A couple of parameters that this port does not use. */ + ( void ) usStringLength; + ( void ) pxPort; + + /* NOTE: This implementation does not handle the queue being full as no + block time is used! */ + + /* The port handle is not required as this driver only supports UART0. */ + ( void ) pxPort; + + /* Send each character in the string, one at a time. */ + pxNext = ( signed portCHAR * ) pcString; + while( *pxNext ) + { + xSerialPutChar( pxPort, *pxNext, serNO_BLOCK ); + pxNext++; + } +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) +{ + /* Place the character in the queue of characters to be transmitted. */ + if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) + { + return pdFAIL; + } + + /* Turn on the Tx interrupt so the ISR will remove the character from the + queue and send it. This does not need to be in a critical section as + if the interrupt has already removed the character the next interrupt + will simply turn off the Tx interrupt again. */ + vInterruptOn(); + + return pdPASS; +} +/*-----------------------------------------------------------*/ + +void vSerialClose( xComPortHandle xPort ) +{ + /* Not supported as not required by the demo application. */ +} +/*-----------------------------------------------------------*/ + +/* Serial port ISR. This can cause a context switch so is not defined as a +standard ISR using the __irq keyword. Instead a wrapper function is defined +within serialISR.s79 which in turn calls this function. See the port +documentation on the FreeRTOS.org website for more information. */ +__arm void vSerialISR( void ) +{ +unsigned portLONG ulStatus; +signed portCHAR cChar; +portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByPost = pdFALSE; + + /* What caused the interrupt? */ + ulStatus = serCOM0->US_CSR &= serCOM0->US_IMR; + + if( ulStatus & AT91C_US_TXRDY ) + { + /* The interrupt was caused by the THR becoming empty. Are there any + more characters to transmit? */ + if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE ) + { + /* A character was retrieved from the queue so can be sent to the + THR now. */ + serCOM0->US_THR = cChar; + } + else + { + /* Queue empty, nothing to send so turn off the Tx interrupt. */ + vInterruptOff(); + } + } + + if( ulStatus & AT91C_US_RXRDY ) + { + /* The interrupt was caused by a character being received. Grab the + character from the RHR and place it in the queue or received + characters. */ + cChar = serCOM0->US_RHR; + xTaskWokenByPost = xQueueSendFromISR( xRxedChars, &cChar, xTaskWokenByPost ); + } + + /* If a task was woken by either a character being received or a character + being transmitted then we may need to switch to another task. */ + portEND_SWITCHING_ISR( ( xTaskWokenByPost || xTaskWokenByTx ) ); + + /* End the interrupt in the AIC. */ + AT91C_BASE_AIC->AIC_EOICR = 0; +} + + + + + diff --git a/20080212/Demo/ARM7_AT91SAM7S64_IAR/serial/serialISR.s79 b/20080212/Demo/ARM7_AT91SAM7S64_IAR/serial/serialISR.s79 new file mode 100644 index 000000000..da0a0bd17 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7S64_IAR/serial/serialISR.s79 @@ -0,0 +1,24 @@ + RSEG ICODE:CODE + CODE32 + + EXTERN vSerialISR + PUBLIC vSerialISREntry + +; Wrapper for the serial port interrupt service routine. This can cause a +; context switch so requires an assembly wrapper. + +; Defines the portSAVE_CONTEXT and portRESTORE_CONTEXT macros. +#include "ISR_Support.h" + +vSerialISREntry: + + portSAVE_CONTEXT ; Save the context of the current task. + + bl vSerialISR ; Call the ISR routine. + + portRESTORE_CONTEXT ; Restore the context of the current task - + ; which may be different to the task that + ; was interrupted. + + END + diff --git a/20080212/Demo/ARM7_AT91SAM7S64_IAR/settings/Basic.dbgdt b/20080212/Demo/ARM7_AT91SAM7S64_IAR/settings/Basic.dbgdt new file mode 100644 index 000000000..5085f2cdb --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7S64_IAR/settings/Basic.dbgdt @@ -0,0 +1,71 @@ + + + + + + + + + + + 1892727 + + + + + + 200100 + + + 200188171100100010 + + + + + TabID-23416-30482 + Workspace + Workspace + + + rtosdemo + + + + 0 + + + + + TabID-12145-30489 + Debug Log + Debug-Log + + + + TabID-22894-30492 + Build + Build + + + + + 1 + TabID-18780-12821MemoryMemory2097764209776410000TabID-23506-14575WatchWatchpxCurrentTCBulCriticalNesting01761001001000TabID-4859-22480DisassemblyDisassembly0TabID-154-22568RegisterRegister0001CPSR0 + + + + + + TextEditorE:\Dev\FreeRTOS\Demo\ARM7_Ateml_IAR\main.c010378378TextEditorE:\Dev\FreeRTOS\source\include\task.h07782428324283TextEditorE:\Dev\FreeRTOS\Source\tasks.c09393051130511TextEditorE:\Dev\FreeRTOS\Demo\ARM7_Ateml_IAR\SrcIAR\Cstartup.s7904822262226TextEditorE:\Dev\FreeRTOS\Demo\Common\Minimal\flash.c09840254025TextEditorE:\Dev\FreeRTOS\Source\portable\IAR\AtmelSAM7\portasm.s7904110571079TextEditorE:\Dev\FreeRTOS\Demo\ARM7_Ateml_IAR\srciar\lib_AT91SAM7S64.h02778108450108450TextEditorE:\Dev\FreeRTOS\Source\portable\IAR\AtmelSAM7\port.c0136532653267TextEditorE:\Dev\FreeRTOS\Demo\ARM7_Ateml_IAR\ParTest\ParTest.c03600TextEditorE:\Dev\FreeRTOS\Source\portable\IAR\AtmelSAM7\portmacro.h067000100000010000001 + + + + + + + IarIdePM1DebuggerGui1-2-2715263-2-215315395625136729165625640750-2-2715647-2-2190190118750169794405625640750-26457151025645-2190190118750169794237500640750-2-21511602-2-21604153100250013672995625136729149-2333669-21496711844193751644321143751635381496673331602667149935184584375164432115000598748 + + + + diff --git a/20080212/Demo/ARM7_AT91SAM7S64_IAR/settings/Basic.dni b/20080212/Demo/ARM7_AT91SAM7S64_IAR/settings/Basic.dni new file mode 100644 index 000000000..9b68f65a8 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7S64_IAR/settings/Basic.dni @@ -0,0 +1,23 @@ +[DisAssemblyWindow] +NumStates=_ 1 +State 1=_ 1 +[JLinkDriver] +WatchVectorCatch=_ 0 +WatchCond=_ 0 +Watch0=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0 +Watch1=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0 +[Log file] +LoggingEnabled=_ 0 +LogFile=_ "" +Category=_ 0 +[TermIOLog] +LoggingEnabled=_ 0 +LogFile=_ "" +[Disassemble mode] +mode=0 +[Breakpoints] +Bp0=_ "Code" "{E:\Dev\FreeRTOS\Source\portable\IAR\AtmelSAM7\port.c}.141.1@1" 1 0 0 0 "" 0 "" +Count=1 +[Low Level] +Pipeline mode=0 +Initialized=0 diff --git a/20080212/Demo/ARM7_AT91SAM7S64_IAR/settings/BasicSAM7.wsdt b/20080212/Demo/ARM7_AT91SAM7S64_IAR/settings/BasicSAM7.wsdt new file mode 100644 index 000000000..2ce5c4bb0 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7S64_IAR/settings/BasicSAM7.wsdt @@ -0,0 +1,80 @@ + + + + + + rtosdemo/Flash Debug + + + + + + + + 2322727 + + + + + + + + + + + + + + + + 100 + 010 + + + + + + + TabID-29690-30365 + Workspace + Workspace + + + rtosdemo + + + + 0 + + + TabID-27076-30414 + Build + Build + + + + TabID-12668-30479 + Debug Log + Debug-Log + + + + + 1 + + + + + + TextEditorE:\Dev\FreeRTOS\source\include\task.h07782428324283TextEditorE:\Dev\FreeRTOS\Source\portable\IAR\AtmelSAM7\portasm.s790025832583TextEditorE:\Dev\FreeRTOS\Demo\ARM7_Ateml_IAR\main.c0000TextEditorE:\Dev\FreeRTOS\Demo\ARM7_Ateml_IAR\SrcIAR\Cstartup.s79030222622263TextEditorE:\Dev\FreeRTOS\Demo\ARM7_Ateml_IAR\srciar\lib_AT91SAM7S64.h023719263892638TextEditorE:\Dev\FreeRTOS\Demo\Common\Minimal\flash.c09840254025TextEditorE:\Dev\FreeRTOS\Source\portable\IAR\AtmelSAM7\port.c017776627662TextEditorE:\Dev\FreeRTOS\Demo\ARM7_Ateml_IAR\ParTest\ParTest.c03600TextEditorE:\Dev\FreeRTOS\Source\portable\IAR\AtmelSAM7\portmacro.h02121102110TextEditorE:\Dev\FreeRTOS\Demo\ARM7_Ateml_IAR\SrcIAR\Cstartup_SAM7.c02931163116TextEditorE:\Dev\FreeRTOS\Source\portable\MemMang\heap_2.c017073527352TextEditorE:\Dev\FreeRTOS\Source\tasks.c0127040884408840100000010000001 + + + + + + + IarIdePM1-2-2866306-2-248483000042895192500775692-2-22061602-2-2160420810025001858803000042895 + + + + diff --git a/20080212/Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo.dbgdt b/20080212/Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo.dbgdt new file mode 100644 index 000000000..0df6a20f1 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo.dbgdt @@ -0,0 +1,62 @@ + + + + + + + + + + + 204272727 + + + + + + 200100 + 300Build + 300Debug-Log + + + + + + + 200 + + 161100100100300010 + + + + + + + + TabID-22256-14845 + Workspace + Workspace + + + rtosdemortosdemo/USBSample.c + + + + 0TabID-18517-20319Debug LogDebug-Log0 + + + + + + TextEditorC:\E\Dev\FreeRTOS\Demo\ARM7_AT91SAM7S64_IAR\FreeRTOSConfig.h02517261726TextEditorC:\E\Dev\FreeRTOS\Demo\ARM7_AT91SAM7S64_IAR\SrcIAR\Cstartup.s7901915271527TextEditorC:\E\Dev\FreeRTOS\Demo\ARM7_AT91SAM7S64_IAR\SrcIAR\Cstartup.s052325032502TextEditorC:\E\Dev\FreeRTOS\Source\portable\IAR\AtmelSAM7S64\port.c0217834583450100000010000001 + + + + + + + iaridepm.enu1debuggergui.enu1-2-2740278-2-20000166667755601-2-21981682-2-216842001002381203666119048203666 + + + + diff --git a/20080212/Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo.dni b/20080212/Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo.dni new file mode 100644 index 000000000..78681fc3a --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo.dni @@ -0,0 +1,39 @@ +[DisAssemblyWindow] +NumStates=_ 1 +State 1=_ 1 +[JLinkDriver] +WatchVectorCatch=_ 0 +WatchCond=_ 0 +Watch0=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0 +Watch1=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0 +[Low Level] +Pipeline mode=1 +Initialized=0 +[CodeCoverage] +Enabled=_ 0 +[Profiling] +Enabled=0 +[StackPlugin] +Enabled=1 +OverflowWarningsEnabled=1 +WarningThreshold=90 +SpWarningsEnabled=1 +WarnHow=0 +UseTrigger=1 +TriggerName=main +LimitSize=0 +ByteLimit=50 +[Log file] +LoggingEnabled=_ 0 +LogFile=_ "" +Category=_ 0 +[TermIOLog] +LoggingEnabled=_ 0 +LogFile=_ "" +[Disassemble mode] +mode=0 +[Breakpoints] +Count=0 +[TraceHelper] +Enabled=0 +ShowSource=1 diff --git a/20080212/Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo.wsdt b/20080212/Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo.wsdt new file mode 100644 index 000000000..ca9ef47b3 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo.wsdt @@ -0,0 +1,76 @@ + + + + + + rtosdemo/Flash Bin + + + + + + + + 236272727 + + 18115530877 + + + + + + + + + + + 100010 + + + + + + + TabID-17425-14382 + Workspace + Workspace + + + rtosdemo + + + + 0 + + + TabID-4084-16269 + Build + Build + + + + TabID-25581-16276 + Debug Log + Debug-Log + + + + + 0 + + + + + + TextEditorC:\E\Dev\FreeRTOS\Demo\ARM7_AT91SAM7S64_IAR\main.c000000100000010000001 + + + + + + + iaridepm.enu1-2-2576310-2-232261904826477185714588595-2-23621682-2-2168436410023813706721904826477 + + + + diff --git a/20080212/Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo_lnk.par b/20080212/Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo_lnk.par new file mode 100644 index 000000000..dbc316aa7 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo_lnk.par @@ -0,0 +1,17 @@ +// IAR XLINK Setup +// Autogenerated file - do not edit +% +setrangelist($evec_ADR,[0-3F]); +setrangelist($internal_ROM,[8000-FFFFF]); +setrangelist($external_ROM,[]); +setrangelist($internal_RAM,[100000-7FFFFF]); +setrangelist($external_RAM,[]); +$CSTACK_SIZE=200; +$IRQSTACK_SIZE=100; +$HEAP_SIZE=4; +$COMMANDS=""; +$STACK_LOCATION="Internal RAM"; +$IRQSTACK_LOCATION="Internal RAM"; +$HEAP_LOCATION="Internal RAM"; +$iar_saved_xclfilename="E:\Dev\FreeRTOS\Demo\ARM7_AT91SAM7S64_IAR\resource\at91SAM7S64_NoRemap.xcl"; +% \ No newline at end of file diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.cdt.core/.log b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.cdt.core/.log new file mode 100644 index 000000000..128e868b5 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.cdt.core/.log @@ -0,0 +1,17 @@ +*** SESSION Sep 07, 2007 11:40:29.515 ------------------------------------------ +*** SESSION Sep 26, 2007 20:59:04.640 ------------------------------------------ +*** SESSION Sep 27, 2007 17:22:58.687 ------------------------------------------ +*** SESSION Oct 04, 2007 20:29:08.859 ------------------------------------------ +*** SESSION Oct 23, 2007 19:47:01.875 ------------------------------------------ +*** SESSION Oct 23, 2007 21:13:26.296 ------------------------------------------ +*** SESSION Oct 23, 2007 21:22:16.187 ------------------------------------------ +*** SESSION Oct 28, 2007 12:37:13.93 ------------------------------------------- +*** SESSION Nov 06, 2007 16:04:46.31 ------------------------------------------- +*** SESSION Nov 06, 2007 20:19:12.359 ------------------------------------------ +*** SESSION Nov 07, 2007 18:40:55.281 ------------------------------------------ +*** SESSION Nov 13, 2007 20:49:09.875 ------------------------------------------ +*** SESSION Nov 17, 2007 17:59:26.734 ------------------------------------------ +*** SESSION Nov 17, 2007 19:36:59.656 ------------------------------------------ +*** SESSION Nov 21, 2007 08:36:47.312 ------------------------------------------ +*** SESSION Nov 21, 2007 15:42:29.171 ------------------------------------------ +*** SESSION Nov 21, 2007 17:07:49.515 ------------------------------------------ diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.cdt.core/shareddefaults.xml b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.cdt.core/shareddefaults.xml new file mode 100644 index 000000000..c4b91cfab --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.cdt.core/shareddefaults.xml @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.cdt.make.core/.log b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.cdt.make.core/.log new file mode 100644 index 000000000..e69de29bb diff --git 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Izfynve{X`IKL7v# literal 0 HcmV?d00001 diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.core.resources/.safetable/org.eclipse.core.resources b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.core.resources/.safetable/org.eclipse.core.resources new file mode 100644 index 0000000000000000000000000000000000000000..44f79aa39eca60a2980b4d4b9a0d086995993aa7 GIT binary patch literal 520 zcmZ?R*xjhShe1S2b=vdAllRFf=Oz}Hq!uZZBqrsg@^UGMr=}?Q<(DZK87df>TNzkb z8JH=!`-UhO85o%JawX@aCKkD*=9DDH=NF~xr6%WO78IxIC8w0=CFd8V+NLGu6a!7c zp)4gesWe@$G!v#Q1!RzGML}j!Vo7Fx9(E%Q4J}R0%uFmS%*;&<2pEm*27SGfqSRDd a6QHXPMEw2?_H*Fpp6cD@#~en(;1~e>k+mZL literal 0 HcmV?d00001 diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-RTOSDemo.prefs b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-RTOSDemo.prefs new file mode 100644 index 000000000..bb305ff00 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-RTOSDemo.prefs @@ -0,0 +1,3 @@ +#Sun Aug 19 15:20:24 BST 2007 +eclipse.preferences.version=1 +indexer/preferenceScope=0 diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.core.prefs b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.core.prefs new file mode 100644 index 000000000..1c0fdf149 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.core.prefs @@ -0,0 +1,3 @@ +#Sun Aug 19 15:19:23 BST 2007 +org.eclipse.cdt.debug.core.cDebug.common_source_containers=\r\n\r\n\r\n\r\n +eclipse.preferences.version=1 diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.ui.prefs b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.ui.prefs new file mode 100644 index 000000000..d7fcb8db3 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.ui.prefs @@ -0,0 +1,5 @@ +#Tue Oct 23 21:13:09 BST 2007 +pref_state_memento.org.eclipse.cdt.debug.ui.ModulesView=\r\n +eclipse.preferences.version=1 +org.eclipse.debug.ui.DebugView.org.eclipse.cdt.debug.ui.cDebug.show_full_paths=true +org.eclipse.debug.ui.BreakpointView.org.eclipse.cdt.debug.ui.cDebug.show_full_paths=true diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.managedbuilder.core.prefs new file mode 100644 index 000000000..ab5a1605c --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.managedbuilder.core.prefs @@ -0,0 +1,3 @@ +#Wed Nov 21 16:20:43 GMT 2007 +eclipse.preferences.version=1 +properties/RTOSDemo.null.976634949/0.1109417601=\#\r\n\#Wed Nov 21 16\:20\:43 GMT 2007\r\n0.1109417601\=\\\#\\r\\n\\\#Wed Nov 21 16\\\:20\\\:43 GMT 2007\\r\\nrcState\\\=0\\r\\nrebuildState\\\=false\\r\\n\r\norg.eclipse.cdt.build.core.settings.holder.1502006385\=\\\#\\r\\n\\\#Wed Nov 21 16\\\:20\\\:43 GMT 2007\\r\\nrebuildState\\\=false\\r\\n\r\norg.eclipse.cdt.build.core.settings.holder.1021181093\=\\\#\\r\\n\\\#Wed Nov 21 16\\\:20\\\:43 GMT 2007\\r\\nrebuildState\\\=false\\r\\n\r\norg.eclipse.cdt.build.core.settings.holder.164584712\=\\\#\\r\\n\\\#Wed Nov 21 16\\\:20\\\:43 GMT 2007\\r\\nrebuildState\\\=false\\r\\n\r\norg.eclipse.cdt.build.core.settings.holder.libs.260784574\=\\\#\\r\\n\\\#Wed Nov 21 16\\\:20\\\:43 GMT 2007\\r\\nrebuildState\\\=false\\r\\n\r\norg.eclipse.cdt.build.core.prefbase.toolchain.1816209921\=\\\#\\r\\n\\\#Wed Nov 21 16\\\:20\\\:43 GMT 2007\\r\\nrebuildState\\\=false\\r\\n\r\n diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prefs b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prefs new file mode 100644 index 000000000..8a970dac4 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prefs @@ -0,0 +1,12 @@ +#Thu Aug 23 20:22:58 BST 2007 +useQuickDiffPrefPage=true +closeBrackets=false +ensureNewlineAtEOF=true +useAnnotationsPrefPage=true +closeAngularBrackets=false +eclipse.preferences.version=1 +org.eclipse.cdt.ui.text.templates.custom= +hoverModifierMasks=org.eclipse.cdt.ui.BestMatchHover;0;org.eclipse.cdt.ui.CSourceHover;131072;org.eclipse.cdt.debug.internal.ui.editors.DebugTextHover;0;org.eclipse.cdt.ui.CDocHover;0;org.eclipse.cdt.ui.AnnotationHover;0; +hoverModifiers=org.eclipse.cdt.ui.BestMatchHover;0;org.eclipse.cdt.ui.CSourceHover;Shift;org.eclipse.cdt.debug.internal.ui.editors.DebugTextHover;\!0;org.eclipse.cdt.ui.CDocHover;\!0;org.eclipse.cdt.ui.AnnotationHover;\!0; +closeBraces=false +closeStrings=false diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.core.resources.prefs b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 000000000..242e94194 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,5 @@ +#Fri Aug 31 14:25:00 BST 2007 +version=1 +eclipse.preferences.version=1 +pathvariable.FreeRTOS_ROOT=C\:/E/Dev/FreeRTOS +description.autobuilding=false diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.core.prefs b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.core.prefs new file mode 100644 index 000000000..4e5b3d8cb --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.core.prefs @@ -0,0 +1,3 @@ +#Sat Nov 17 13:34:58 GMT 2007 +prefWatchExpressions=\r\n\r\n +eclipse.preferences.version=1 diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs new file mode 100644 index 000000000..c88e84313 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs @@ -0,0 +1,14 @@ +#Wed Nov 07 18:56:22 GMT 2007 +org.eclipse.debug.ui.PREF_FILTER_WORKING_SETS=false +org.eclipse.debug.ui.PREF_LAUNCH_PERSPECTIVES=\r\n\r\n +org.eclipse.debug.ui.BreakpointView+org.eclipse.debug.ui.ShowSupportedBreakpointsAction=true +pref_state_memento.org.eclipse.debug.ui.VariableView=\r\n +pref_state_memento.org.eclipse.debug.ui.RegisterView=\r\n +org.eclipse.debug.ui.memory.columnSize\:org.eclipse.cdt.debug.core=4 +pref_state_memento.org.eclipse.debug.ui.ExpressionView=\r\n +org.eclipse.debug.ui.PREF_FILTER_LAUNCH_CLOSED=false +preferredDetailPanes=DefaultDetailPane\:DefaultDetailPane| +org.eclipse.debug.ui.PREF_FILTER_LAUNCH_DELETED=false +eclipse.preferences.version=1 +org.eclipse.debug.ui.memory.rowSize\:org.eclipse.cdt.debug.core=16 +org.eclipse.debug.ui.user_view_bindings=\r\n\r\n\r\n\r\n\r\n\r\n diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.help.ui.prefs b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.help.ui.prefs new file mode 100644 index 000000000..8d1b31164 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.help.ui.prefs @@ -0,0 +1,7 @@ +#Sun Aug 26 17:32:13 BST 2007 +browser.x=177 +browser.w=1024 +eclipse.preferences.version=1 +browser.h=768 +browser.maximized=false +browser.y=128 diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.search.prefs b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.search.prefs new file mode 100644 index 000000000..2426c2b79 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.search.prefs @@ -0,0 +1,3 @@ +#Sun Aug 19 19:39:29 BST 2007 +org.eclipse.search.defaultPerspective=org.eclipse.search.defaultPerspective.none +eclipse.preferences.version=1 diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.team.ui.prefs b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.team.ui.prefs new file mode 100644 index 000000000..06f8f1043 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.team.ui.prefs @@ -0,0 +1,3 @@ +#Fri Aug 31 18:19:04 BST 2007 +eclipse.preferences.version=1 +org.eclipse.team.ui.first_time=false diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.editors.prefs b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.editors.prefs new file mode 100644 index 000000000..1affd268e --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.editors.prefs @@ -0,0 +1,3 @@ +#Sun Aug 19 20:45:57 BST 2007 +eclipse.preferences.version=1 +overviewRuler_migration=migrated_3.1 diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.ide.prefs b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.ide.prefs new file mode 100644 index 000000000..b96f5d0dd --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.ide.prefs @@ -0,0 +1,4 @@ +#Tue Nov 06 22:57:01 GMT 2007 +eclipse.preferences.version=1 +tipsAndTricks=true +platformState=1187207632259 diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.prefs b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.prefs new file mode 100644 index 000000000..3e5b2b17d --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.prefs @@ -0,0 +1,3 @@ +#Sun Aug 19 20:45:58 BST 2007 +eclipse.preferences.version=1 +showIntro=false diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.workbench.prefs b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.workbench.prefs new file mode 100644 index 000000000..06cd1e9cd --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.workbench.prefs @@ -0,0 +1,3 @@ +#Mon Aug 20 21:59:49 BST 2007 +eclipse.preferences.version=1 +org.eclipse.ui.commands=\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.debug.core/.launches/OpenOCD Programmer.launch b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.debug.core/.launches/OpenOCD Programmer.launch new file mode 100644 index 000000000..822c04f0c --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.debug.core/.launches/OpenOCD Programmer.launch @@ -0,0 +1,7 @@ + + + + + + + diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.debug.core/.launches/OpenOCD Server.launch b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.debug.core/.launches/OpenOCD Server.launch new file mode 100644 index 000000000..6a59edf70 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.debug.core/.launches/OpenOCD Server.launch @@ -0,0 +1,7 @@ + + + + + + + diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.debug.core/.launches/RTOSDemo.elf.launch b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.debug.core/.launches/RTOSDemo.elf.launch new file mode 100644 index 000000000..1c911f23d --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.debug.core/.launches/RTOSDemo.elf.launch @@ -0,0 +1,33 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.debug.core/.launches/RTOSDemo.launch b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.debug.core/.launches/RTOSDemo.launch new file mode 100644 index 000000000..fca7b0ac4 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.debug.core/.launches/RTOSDemo.launch @@ -0,0 +1,26 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.debug.ui/dialog_settings.xml b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.debug.ui/dialog_settings.xml new file mode 100644 index 000000000..4e6586f56 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.debug.ui/dialog_settings.xml @@ -0,0 +1,41 @@ + +
+
+ + + + + +
+
+ + + + + + + + +
+
+ + + + + +
+
+ + + + + +
+
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diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.debug.ui/launchConfigurationHistory.xml b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.debug.ui/launchConfigurationHistory.xml new file mode 100644 index 000000000..aa1b7aaee --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.debug.ui/launchConfigurationHistory.xml @@ -0,0 +1,27 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.help.ui/dialog_settings.xml b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.help.ui/dialog_settings.xml new file mode 100644 index 000000000..1ef2b05b5 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.help.ui/dialog_settings.xml @@ -0,0 +1,3 @@ + +
+
diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.help.ui/scope_sets/Default.pref b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.help.ui/scope_sets/Default.pref new file mode 100644 index 000000000..fc158177d --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.help.ui/scope_sets/Default.pref @@ -0,0 +1,2 @@ +#Sun Aug 26 17:54:18 BST 2007 +__DEFAULT__=true diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.help.ui/scope_sets/relative_path.hist b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.help.ui/scope_sets/relative_path.hist new file mode 100644 index 000000000..713e72168 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.help.ui/scope_sets/relative_path.hist @@ -0,0 +1,4 @@ +#Sun Aug 26 17:36:29 BST 2007 +__DEFAULT__=false +org.eclipse.help.ui.localSearch.master=true +expression=relative path diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.help.ui/scope_sets/working_set.hist b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.help.ui/scope_sets/working_set.hist new file mode 100644 index 000000000..197837b95 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.help.ui/scope_sets/working_set.hist @@ -0,0 +1,4 @@ +#Sun Aug 26 17:29:25 BST 2007 +__DEFAULT__=false +org.eclipse.help.ui.localSearch.master=true +expression=working set diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.help.ui/scope_sets/working_sets.hist b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.help.ui/scope_sets/working_sets.hist new file mode 100644 index 000000000..a88e15eb8 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.help.ui/scope_sets/working_sets.hist @@ -0,0 +1,4 @@ +#Sun Aug 26 17:54:21 BST 2007 +__DEFAULT__=false +org.eclipse.help.ui.localSearch.master=true +expression=working sets diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.ltk.ui.refactoring/dialog_settings.xml b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.ltk.ui.refactoring/dialog_settings.xml new file mode 100644 index 000000000..ac671478c --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.ltk.ui.refactoring/dialog_settings.xml @@ -0,0 +1,6 @@ + +
+
+ +
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diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.search/dialog_settings.xml b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.search/dialog_settings.xml new file mode 100644 index 000000000..839aca5ed --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.search/dialog_settings.xml @@ -0,0 +1,46 @@ + +
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diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.ui.cheatsheets/dialog_settings.xml b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.ui.cheatsheets/dialog_settings.xml new file mode 100644 index 000000000..1df8b48c3 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.ui.cheatsheets/dialog_settings.xml @@ -0,0 +1,10 @@ + +
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diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.ui.ide/dialog_settings.xml b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.ui.ide/dialog_settings.xml new file mode 100644 index 000000000..070a4abfc --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.ui.ide/dialog_settings.xml @@ -0,0 +1,26 @@ + +
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diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.ui.intro/dialog_settings.xml b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.ui.intro/dialog_settings.xml new file mode 100644 index 000000000..d3014f5c1 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.ui.intro/dialog_settings.xml @@ -0,0 +1,4 @@ + +
+ +
diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.ui.workbench.texteditor/dialog_settings.xml b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.ui.workbench.texteditor/dialog_settings.xml new file mode 100644 index 000000000..e891f2879 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.ui.workbench.texteditor/dialog_settings.xml @@ -0,0 +1,38 @@ + +
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diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.ui.workbench/dialog_settings.xml b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.ui.workbench/dialog_settings.xml new file mode 100644 index 000000000..77beade3e --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.ui.workbench/dialog_settings.xml @@ -0,0 +1,19 @@ + +
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diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.ui.workbench/workbench.xml b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.ui.workbench/workbench.xml new file mode 100644 index 000000000..97c7cfce9 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.ui.workbench/workbench.xml @@ -0,0 +1,358 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.ui.workbench/workingsets.xml b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.ui.workbench/workingsets.xml new file mode 100644 index 000000000..a34189f07 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.ui.workbench/workingsets.xml @@ -0,0 +1,64 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.ui/dialog_settings.xml b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.ui/dialog_settings.xml new file mode 100644 index 000000000..64561b65c --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.ui/dialog_settings.xml @@ -0,0 +1,10 @@ + +
+
+ + + + + +
+
diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.update.ui/dialog_settings.xml b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.update.ui/dialog_settings.xml new file mode 100644 index 000000000..86928e08c --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/.plugins/org.eclipse.update.ui/dialog_settings.xml @@ -0,0 +1,5 @@ + +
+
+
+
diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/version.ini b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/version.ini new file mode 100644 index 000000000..c51ff745b --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/.metadata/version.ini @@ -0,0 +1 @@ +org.eclipse.core.runtime=1 \ No newline at end of file diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/.cproject b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/.cproject new file mode 100644 index 000000000..bbcae405f --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/.cproject @@ -0,0 +1,230 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/.project b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/.project new file mode 100644 index 000000000..b3776decb --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/.project @@ -0,0 +1,97 @@ + + + RTOSDemo + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.buildLocation + ${workspace_loc:/RTOSDemo} + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + false + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + ?children? + ?name?=outputEntries\|?children?=?name?=entry\\\\\\\\\\\\\\\|\\\\\\\|\|| + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.core.cnature + + + + Common Demo Files + 2 + FreeRTOS_ROOT/Demo/Common + + + FreeRTOS.org Source + 2 + FreeRTOS_ROOT/Source + + + diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/.settings/org.eclipse.ltk.core.refactoring.prefs b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/.settings/org.eclipse.ltk.core.refactoring.prefs new file mode 100644 index 000000000..a9f7e81cf --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/.settings/org.eclipse.ltk.core.refactoring.prefs @@ -0,0 +1,3 @@ +#Sun Aug 19 20:36:58 BST 2007 +eclipse.preferences.version=1 +org.eclipse.ltk.core.refactoring.enable.project.refactoring.history=false diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/FreeRTOSConfig.h b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/FreeRTOSConfig.h new file mode 100644 index 000000000..73bfd5527 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/FreeRTOSConfig.h @@ -0,0 +1,105 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include +#include "AT91SAM7X256.h" +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 1 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 47923200 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 130 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 24 * 1024 ) ) +#define configMAX_TASK_NAME_LEN ( 10 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 + + + +/* MAC address configuration. */ +#define uipMAC_ADDR0 0x00 +#define uipMAC_ADDR1 0x12 +#define uipMAC_ADDR2 0x13 +#define uipMAC_ADDR3 0x10 +#define uipMAC_ADDR4 0x15 +#define uipMAC_ADDR5 0x11 + +/* IP address configuration. */ +#define uipIP_ADDR0 172 +#define uipIP_ADDR1 25 +#define uipIP_ADDR2 218 +#define uipIP_ADDR3 10 + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/Makefile b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/Makefile new file mode 100644 index 000000000..3146a1118 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/Makefile @@ -0,0 +1,132 @@ +# FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. +# +# This file is part of the FreeRTOS.org distribution. +# +# FreeRTOS.org is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# FreeRTOS.org is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with FreeRTOS.org; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +# +# A special exception to the GPL can be applied should you wish to distribute +# a combined work that includes FreeRTOS.org, without being obliged to provide +# the source code for any proprietary components. See the licensing section +# of http://www.FreeRTOS.org for full details of how and when the exception +# can be applied. +# +# *************************************************************************** +# See http://www.FreeRTOS.org for documentation, latest information, license +# and contact details. Please ensure to read the configuration and relevant +# port sections of the online documentation. +# *************************************************************************** + + +RTOS_SOURCE_DIR=../../../Source +DEMO_COMMON_DIR=../../Common/Minimal +DEMO_INCLUDE_DIR=../../Common/include +UIP_COMMON_DIR=../../Common/ethernet/uIP/uip-1.0/uip + +CC=arm-elf-gcc +OBJCOPY=arm-elf-objcopy +LDSCRIPT=atmel-rom.ld + +LINKER_FLAGS=-mthumb -nostartfiles -Xlinker -oRTOSDemo.elf -Xlinker -M -Xlinker -Map=rtosdemo.map + +DEBUG=-g +OPTIM=-O3 + + +CFLAGS= $(DEBUG) \ + $(OPTIM) \ + -T$(LDSCRIPT) \ + -I . \ + -I $(RTOS_SOURCE_DIR)/include \ + -I $(RTOS_SOURCE_DIR)/portable/GCC/ARM7_AT91SAM7S \ + -I $(DEMO_INCLUDE_DIR) \ + -I ./webserver \ + -I $(UIP_COMMON_DIR) \ + -I ./SrcAtmel \ + -I ./USB \ + -D SAM7_GCC \ + -D THUMB_INTERWORK \ + -mcpu=arm7tdmi \ + -D PACK_STRUCT_END=__attribute\(\(packed\)\) \ + -D ALIGN_STRUCT_END=__attribute\(\(aligned\(4\)\)\) \ + -fomit-frame-pointer \ + -mthumb-interwork + +THUMB_SOURCE= \ + main.c \ + ./ParTest/ParTest.c \ + $(DEMO_COMMON_DIR)/BlockQ.c \ + $(DEMO_COMMON_DIR)/blocktim.c \ + $(DEMO_COMMON_DIR)/flash.c \ + $(DEMO_COMMON_DIR)/integer.c \ + $(DEMO_COMMON_DIR)/GenQTest.c \ + $(DEMO_COMMON_DIR)/QPeek.c \ + $(DEMO_COMMON_DIR)/dynamic.c \ + ./webserver/uIP_Task.c \ + ./webserver/httpd.c \ + ./webserver/httpd-cgi.c \ + ./webserver/httpd-fs.c \ + ./webserver/http-strings.c \ + ./webserver/SAM7_EMAC.c \ + $(UIP_COMMON_DIR)/uip_arp.c \ + $(UIP_COMMON_DIR)/psock.c \ + $(UIP_COMMON_DIR)/timer.c \ + $(UIP_COMMON_DIR)/uip.c \ + $(RTOS_SOURCE_DIR)/list.c \ + $(RTOS_SOURCE_DIR)/queue.c \ + $(RTOS_SOURCE_DIR)/tasks.c \ + $(RTOS_SOURCE_DIR)/portable/GCC/ARM7_AT91SAM7S/port.c \ + $(RTOS_SOURCE_DIR)/portable/MemMang/heap_2.c \ + ./USB/USBSample.c + +ARM_SOURCE= \ + $(RTOS_SOURCE_DIR)/portable/GCC/ARM7_AT91SAM7S/portISR.c \ + ./webserver/emac_isr.c \ + ./SrcAtmel/Cstartup_SAM7.c \ + ./USB/USB_ISR.c + +THUMB_OBJS = $(THUMB_SOURCE:.c=.o) +ARM_OBJS = $(ARM_SOURCE:.c=.o) + + +all: RTOSDemo.bin + +RTOSDemo.bin : RTOSDemo.hex + $(OBJCOPY) RTOSDemo.elf -O binary RTOSDemo.bin + +RTOSDemo.hex : RTOSDemo.elf + $(OBJCOPY) RTOSDemo.elf -O ihex RTOSDemo.hex + +RTOSDemo.elf : $(THUMB_OBJS) $(ARM_OBJS) boot.s Makefile + $(CC) $(CFLAGS) $(ARM_OBJS) $(THUMB_OBJS) $(LIBS) boot.s $(LINKER_FLAGS) + +$(THUMB_OBJS) : %.o : %.c Makefile FreeRTOSConfig.h + $(CC) -c $(CFLAGS) -mthumb $< -o $@ + +$(ARM_OBJS) : %.o : %.c Makefile FreeRTOSConfig.h + $(CC) -c $(CFLAGS) $< -o $@ + +clean : + rm $(THUMB_OBJS) + rm $(ARM_OBJS) + touch Makefile + rm RTOSDemo.elf + rm RTOSDemo.hex + + + + + + + diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/ParTest/ParTest.c b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/ParTest/ParTest.c new file mode 100644 index 000000000..919f9dd84 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/ParTest/ParTest.c @@ -0,0 +1,107 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* Demo application includes. */ +#include "partest.h" + +/*----------------------------------------------------------- + * Simple parallel port IO routines for the LED's. LED's can be set, cleared + * or toggled. + *-----------------------------------------------------------*/ + +#define partstNUM_LEDS ( 4 ) +#define partstALL_LEDS ( ulLED_Mask[ 0 ] | ulLED_Mask[ 1 ] | ulLED_Mask[ 2 ] | ulLED_Mask[ 3 ] ) +const unsigned portLONG ulLED_Mask[ partstNUM_LEDS ]= { (1<<19), (1<<20), (1<<21), (1<<22) }; + + +void vParTestInitialise( void ) +{ + /* Configure the PIO Lines corresponding to LED1 to LED4 to be outputs. */ + AT91C_BASE_PIOB->PIO_PER = partstALL_LEDS; + AT91C_BASE_PIOB->PIO_OER = partstALL_LEDS; + + /* Start with all LED's off. */ + AT91C_BASE_PIOB->PIO_SODR = partstALL_LEDS; +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ + if( uxLED < ( portBASE_TYPE ) partstNUM_LEDS ) + { + if( xValue ) + { + AT91C_BASE_PIOB->PIO_SODR = ulLED_Mask[ uxLED ]; + } + else + { + AT91C_BASE_PIOB->PIO_CODR = ulLED_Mask[ uxLED ]; + } + } +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ + if( uxLED < ( portBASE_TYPE ) partstNUM_LEDS ) + { + if( AT91C_BASE_PIOB->PIO_PDSR & ulLED_Mask[ uxLED ] ) + { + AT91C_BASE_PIOB->PIO_CODR = ulLED_Mask[ uxLED ]; + } + else + { + AT91C_BASE_PIOB->PIO_SODR = ulLED_Mask[ uxLED ]; + } + } +} +/*-----------------------------------------------------------*/ + +unsigned portBASE_TYPE uxParTestGetLED( void ) +{ + /* Return the value of LED DS4 for use by the WEB server. */ + return !( AT91C_BASE_PIOB->PIO_PDSR & ulLED_Mask[ partstNUM_LEDS - 1 ] ); +} + diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/SrcAtmel/Board.h b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/SrcAtmel/Board.h new file mode 100644 index 000000000..8b34427a0 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/SrcAtmel/Board.h @@ -0,0 +1,68 @@ +/*---------------------------------------------------------------------------- +* ATMEL Microcontroller Software Support - ROUSSET - +*---------------------------------------------------------------------------- +* The software is delivered "AS IS" without warranty or condition of any +* kind, either express, implied or statutory. This includes without +* limitation any warranty or condition with respect to merchantability or +* fitness for any particular purpose, or against the infringements of +* intellectual property rights of others. +*---------------------------------------------------------------------------- +* File Name : Board.h +* Object : AT91SAM7X Evaluation Board Features Definition File. +* +* Creation : JG 20/Jun/2005 +*---------------------------------------------------------------------------- +*/ +#ifndef Board_h +#define Board_h + +#include "AT91SAM7X256.h" +#include "ioat91sam7x256.h" + +#define true -1 +#define false 0 + +/*-------------------------------*/ +/* SAM7Board Memories Definition */ +/*-------------------------------*/ +// The AT91SAM7X128 embeds a 32-Kbyte SRAM bank, and 128K-Byte Flash + +#define FLASH_PAGE_NB 256 +#define FLASH_PAGE_SIZE 128 + +/*-----------------*/ +/* Leds Definition */ +/*-----------------*/ +#define LED1 (1<<19) // PB19 +#define LED2 (1<<20) // PB20 +#define LED3 (1<<21) // PB21 +#define LED4 (1<<22) // PB22 +#define NB_LED 4 + +#define LED_MASK (LED1|LED2|LED3|LED4) + +/*-------------------------*/ +/* Push Buttons Definition */ +/*-------------------------*/ + +#define SW1_MASK (1<<21) // PA21 +#define SW2_MASK (1<<22) // PA22 +#define SW3_MASK (1<<23) // PA23 +#define SW4_MASK (1<<24) // PA24 +#define SW_MASK (SW1_MASK|SW2_MASK|SW3_MASK|SW4_MASK) + + +#define SW1 (1<<21) // PA21 +#define SW2 (1<<22) // PA22 +#define SW3 (1<<23) // PA23 +#define SW4 (1<<24) // PA24 +#define SWPUSH (1<<25) // PA25 +/*--------------*/ +/* Master Clock */ +/*--------------*/ + +#define EXT_OC 18432000 // Exetrnal ocilator MAINCK +#define MCK 47923200 // MCK (PLLRC div by 2) +#define MCKKHz (MCK/1000) // + +#endif /* Board_h */ diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/SrcAtmel/Cstartup.s79 b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/SrcAtmel/Cstartup.s79 new file mode 100644 index 000000000..b875618fc --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/SrcAtmel/Cstartup.s79 @@ -0,0 +1,223 @@ +;------------------------------------------------------------------------------ +;- ATMEL Microcontroller Software Support - ROUSSET - +;------------------------------------------------------------------------------ +; The software is delivered "AS IS" without warranty or condition of any +; kind, either express, implied or statutory. This includes without +; limitation any warranty or condition with respect to merchantability or +; fitness for any particular purpose, or against the infringements of +; intellectual property rights of others. +;----------------------------------------------------------------------------- +;- File source : Cstartup.s79 +;- Object : Generic CStartup for IAR No Use REMAP +;- Compilation flag : None +;- +;- 1.0 15/Jun/04 JPP : Creation +;------------------------------------------------------------------------------ + +#include "AT91SAM7X256_inc.h" + +;------------------------------------------------------------------------------ +;- Area Definition +;------------------------------------------------------------------------------ + +;--------------------------------------------------------------- +; ?RESET +; Reset Vector. +; Normally, segment INTVEC is linked at address 0. +; For debugging purposes, INTVEC may be placed at other +; addresses. +; A debugger that honors the entry point will start the +; program in a normal way even if INTVEC is not at address 0. +;------------------------------------------------------------- + + PROGRAM ?RESET + RSEG INTRAMSTART_REMAP + RSEG INTRAMEND_REMAP + + EXTERN vPortYieldProcessor + + RSEG ICODE:CODE:ROOT(2) + CODE32 ; Always ARM mode after reset + org 0 +reset +;------------------------------------------------------------------------------ +;- Exception vectors +;-------------------- +;- These vectors can be read at address 0 or at RAM address +;- They ABSOLUTELY requires to be in relative addresssing mode in order to +;- guarantee a valid jump. For the moment, all are just looping. +;- If an exception occurs before remap, this would result in an infinite loop. +;- To ensure if a exeption occurs before start application to infinite loop. +;------------------------------------------------------------------------------ + + B InitReset ; 0x00 Reset handler +undefvec: + B undefvec ; 0x04 Undefined Instruction +swivec: + B vPortYieldProcessor ; 0x08 Software Interrupt +pabtvec: + B pabtvec ; 0x0C Prefetch Abort +dabtvec: + B dabtvec ; 0x10 Data Abort +rsvdvec: + B rsvdvec ; 0x14 reserved +irqvec: + LDR PC, [PC, #-0xF20] ; Jump directly to the address given by the AIC + +fiqvec: ; 0x1c FIQ + +;------------------------------------------------------------------------------ +;- Function : FIQ_Handler_Entry +;- Treatments : FIQ Controller Interrupt Handler. +;- Called Functions : AIC_FVR[interrupt] +;------------------------------------------------------------------------------ + +FIQ_Handler_Entry: + +;- Switch in SVC/User Mode to allow User Stack access for C code +; because the FIQ is not yet acknowledged + +;- Save and r0 in FIQ_Register + mov r9,r0 + ldr r0 , [r8, #AIC_FVR] + msr CPSR_c,#I_BIT | F_BIT | ARM_MODE_SVC + +;- Save scratch/used registers and LR in User Stack + stmfd sp!, { r1-r3, r12, lr} + +;- Branch to the routine pointed by the AIC_FVR + mov r14, pc + bx r0 + +;- Restore scratch/used registers and LR from User Stack + ldmia sp!, { r1-r3, r12, lr} + +;- Leave Interrupts disabled and switch back in FIQ mode + msr CPSR_c, #I_BIT | F_BIT | ARM_MODE_FIQ + +;- Restore the R0 ARM_MODE_SVC register + mov r0,r9 + +;- Restore the Program Counter using the LR_fiq directly in the PC + subs pc,lr,#4 + +InitReset: +;------------------------------------------------------------------------------ +;- Low level Init (PMC, AIC, ? ....) by C function AT91F_LowLevelInit +;------------------------------------------------------------------------------ + EXTERN AT91F_LowLevelInit + +#define __iramend SFB(INTRAMEND_REMAP) + +;- minumum C initialization +;- call AT91F_LowLevelInit( void) + + ldr r13,=__iramend ; temporary stack in internal RAM +;--Call Low level init function in ABSOLUTE through the Interworking + ldr r0,=AT91F_LowLevelInit + mov lr, pc + bx r0 +;------------------------------------------------------------------------------ +;- Stack Sizes Definition +;------------------------ +;- Interrupt Stack requires 2 words x 8 priority level x 4 bytes when using +;- the vectoring. This assume that the IRQ management. +;- The Interrupt Stack must be adjusted depending on the interrupt handlers. +;- Fast Interrupt not requires stack If in your application it required you must +;- be definehere. +;- The System stack size is not defined and is limited by the free internal +;- SRAM. +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +;- Top of Stack Definition +;------------------------- +;- Interrupt and Supervisor Stack are located at the top of internal memory in +;- order to speed the exception handling context saving and restoring. +;- ARM_MODE_SVC (Application, C) Stack is located at the top of the external memory. +;------------------------------------------------------------------------------ + +IRQ_STACK_SIZE EQU 300 + +ARM_MODE_FIQ EQU 0x11 +ARM_MODE_IRQ EQU 0x12 +ARM_MODE_SVC EQU 0x13 + +I_BIT EQU 0x80 +F_BIT EQU 0x40 + +;------------------------------------------------------------------------------ +;- Setup the stack for each mode +;------------------------------- + ldr r0, =__iramend + +;- Set up Fast Interrupt Mode and set FIQ Mode Stack + msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT +;- Init the FIQ register + ldr r8, =AT91C_BASE_AIC + +;- Set up Interrupt Mode and set IRQ Mode Stack + msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT + mov r13, r0 ; Init stack IRQ + sub r0, r0, #IRQ_STACK_SIZE + +;- Enable interrupt & Set up Supervisor Mode and set Supervisor Mode Stack + msr CPSR_c, #ARM_MODE_SVC + mov r13, r0 + + +;--------------------------------------------------------------- +; ?CSTARTUP +;--------------------------------------------------------------- + EXTERN __segment_init + EXTERN main +; Initialize segments. +; __segment_init is assumed to use +; instruction set and to be reachable by BL from the ICODE segment +; (it is safest to link them in segment ICODE). + ldr r0,=__segment_init + mov lr, pc + bx r0 + + PUBLIC __main +?jump_to_main: + ldr lr,=?call_exit + ldr r0,=main +__main: + bx r0 + +;------------------------------------------------------------------------------ +;- Loop for ever +;--------------- +;- End of application. Normally, never occur. +;- Could jump on Software Reset ( B 0x0 ). +;------------------------------------------------------------------------------ +?call_exit: +End + b End + + + +;--------------------------------------------------------------- +; ?EXEPTION_VECTOR +; This module is only linked if needed for closing files. +;--------------------------------------------------------------- + PUBLIC AT91F_Default_FIQ_handler + PUBLIC AT91F_Default_IRQ_handler + PUBLIC AT91F_Spurious_handler + + CODE32 ; Always ARM mode after exeption + +AT91F_Default_FIQ_handler + b AT91F_Default_FIQ_handler + +AT91F_Default_IRQ_handler + b AT91F_Default_IRQ_handler + +AT91F_Spurious_handler + b AT91F_Spurious_handler + + ENDMOD + + END + diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/SrcAtmel/Cstartup_SAM7.c b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/SrcAtmel/Cstartup_SAM7.c new file mode 100644 index 000000000..d9716c0ef --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/SrcAtmel/Cstartup_SAM7.c @@ -0,0 +1,69 @@ +//*---------------------------------------------------------------------------- +//* ATMEL Microcontroller Software Support - ROUSSET - +//*---------------------------------------------------------------------------- +//* The software is delivered "AS IS" without warranty or condition of any +//* kind, either express, implied or statutory. This includes without +//* limitation any warranty or condition with respect to merchantability or +//* fitness for any particular purpose, or against the infringements of +//* intellectual property rights of others. +//*---------------------------------------------------------------------------- +//* File Name : Cstartup_SAM7.c +//* Object : Low level initializations written in C for IAR +//* tools +//* 1.0 08/Sep/04 JPP : Creation +//* 1.10 10/Sep/04 JPP : Update AT91C_CKGR_PLLCOUNT filed +//*---------------------------------------------------------------------------- + + +// Include the board file description +#include "Board.h" + +//*---------------------------------------------------------------------------- +//* \fn AT91F_LowLevelInit +//* \brief This function performs very low level HW initialization +//* this function can be use a Stack, depending the compilation +//* optimization mode +//*---------------------------------------------------------------------------- +void AT91F_LowLevelInit( void); +void AT91F_LowLevelInit( void ) +{ + AT91PS_PMC pPMC = AT91C_BASE_PMC; + + //* Set Flash Waite sate + // Single Cycle Access at Up to 30 MHz, or 40 + // if MCK = 47923200 I have 50 Cycle for 1 useconde ( flied MC_FMR->FMCN + AT91C_BASE_MC->MC_FMR = ((AT91C_MC_FMCN)&(75 <<16)) | AT91C_MC_FWS_1FWS ; + + //* Watchdog Disable + AT91C_BASE_WDTC->WDTC_WDMR= AT91C_WDTC_WDDIS; + + //* Set MCK at 47 923 200 + // 1 Enabling the Main Oscillator: + // SCK = 1/32768 = 30.51 uSeconde + // Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms + pPMC->PMC_MOR = ((( AT91C_CKGR_OSCOUNT & (0x06 <<8)) | AT91C_CKGR_MOSCEN )); + // Wait the startup time + while(!(pPMC->PMC_SR & AT91C_PMC_MOSCS)); + // 2 Checking the Main Oscillator Frequency (Optional) + // 3 Setting PLL and divider: + // - div by 5 Fin = 3,6864 =(18,432 / 5) + // - Mul 25+1: Fout = 95,8464 =(3,6864 *26) + // for 96 MHz the erroe is 0.16% + //eld out NOT USED = 0 Fi + pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 5) | + (AT91C_CKGR_PLLCOUNT & (28<<8)) | + (AT91C_CKGR_MUL & (25<<16))); + + // Wait the startup time + while(!(pPMC->PMC_SR & AT91C_PMC_LOCK)); + // 4. Selection of Master Clock and Processor Clock + // select the PLL clock divided by 2 + pPMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2 ; + while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY)); + + pPMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK ; + while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY)); +} + + + diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/SrcAtmel/Emac.h b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/SrcAtmel/Emac.h new file mode 100644 index 000000000..7551a3648 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/SrcAtmel/Emac.h @@ -0,0 +1,195 @@ +//*---------------------------------------------------------------------------- +//* ATMEL Microcontroller Software Support - ROUSSET - +//*---------------------------------------------------------------------------- +//* The software is delivered "AS IS" without warranty or condition of any +//* kind, either express, implied or statutory. This includes without +//* limitation any warranty or condition with respect to merchantability or +//* fitness for any particular purpose, or against the infringements of +//* intellectual property rights of others. +//*---------------------------------------------------------------------------- +//* File Name : Emac.h +//* Object : Emac header file +//* Creation : Hi 11/18/2002 +//* +//*---------------------------------------------------------------------------- +#ifndef AT91C_EMAC_H +#define AT91C_EMAC_H + + +//* Allows to display all IP header in the main.c +//* If not defined, only ICMP packets are displayed +#define AT91C_DISPLAY_ALL_IPHEADER 0 + +#define NB_RX_BUFFERS 25 //* Number of receive buffers +#define ETH_RX_BUFFER_SIZE 128 //* + +#define NB_TX_BUFFERS 2 //* Number of Transmit buffers +#define ETH_TX_BUFFER_SIZE UIP_BUFSIZE //* + +#define AT91C_NO_IPPACKET 0 +#define AT91C_IPPACKET 1 + +#define ARP_REQUEST 0x0001 +#define ARP_REPLY 0x0002 +#define PROT_ARP 0x0806 +#define PROT_IP 0x0800 +#define PROT_ICMP 0x01 +#define ICMP_ECHO_REQUEST 0x08 +#define ICMP_ECHO_REPLY 0x00 + +#define AT91C_EMAC_CLKEN 0x2 +#define SWAP16(x) (((x & 0xff) << 8) | (x >> 8)) + +#if 0 +//* Transfer descriptor structure +typedef struct _AT91S_TdDescriptor { + unsigned int addr; + unsigned int status; +}AT91S_TdDescriptor, *AT91PS_TdDescriptor; +#endif + +//* Receive Transfer descriptor structure +typedef struct _AT91S_RxTdDescriptor { + unsigned int addr; + union + { + unsigned int status; + struct { + unsigned int Length:11; + unsigned int Res0:1; + unsigned int Rxbuf_off:2; + unsigned int StartOfFrame:1; + unsigned int EndOfFrame:1; + unsigned int Cfi:1; + unsigned int VlanPriority:3; + unsigned int PriorityTag:1; + unsigned int VlanTag:1; + unsigned int TypeID:1; + unsigned int Sa4Match:1; + unsigned int Sa3Match:1; + unsigned int Sa2Match:1; + unsigned int Sa1Match:1; + unsigned int Res1:1; + unsigned int ExternalAdd:1; + unsigned int UniCast:1; + unsigned int MultiCast:1; + unsigned int BroadCast:1; + }S_Status; + }U_Status; +}AT91S_RxTdDescriptor, *AT91PS_RxTdDescriptor; + + +//* Transmit Transfer descriptor structure +typedef struct _AT91S_TxTdDescriptor { + unsigned int addr; + union + { + unsigned int status; + struct { + unsigned int Length:11; + unsigned int Res0:4; + unsigned int LastBuff:1; + unsigned int NoCrc:1; + unsigned int Res1:10; + unsigned int BufExhausted:1; + unsigned int TransmitUnderrun:1; + unsigned int TransmitError:1; + unsigned int Wrap:1; + unsigned int BuffUsed:1; + }S_Status; + }U_Status; +}AT91S_TxTdDescriptor, *AT91PS_TxTdDescriptor; + +#define AT91C_OWNERSHIP_BIT 0x00000001 + +/* Receive status defintion */ +#define AT91C_BROADCAST_ADDR ((unsigned int) (1 << 31)) //* Broadcat address detected +#define AT91C_MULTICAST_HASH ((unsigned int) (1 << 30)) //* MultiCast hash match +#define AT91C_UNICAST_HASH ((unsigned int) (1 << 29)) //* UniCast hash match +#define AT91C_EXTERNAL_ADDR ((unsigned int) (1 << 28)) //* External Address match +#define AT91C_SA1_ADDR ((unsigned int) (1 << 26)) //* Specific address 1 match +#define AT91C_SA2_ADDR ((unsigned int) (1 << 25)) //* Specific address 2 match +#define AT91C_SA3_ADDR ((unsigned int) (1 << 24)) //* Specific address 3 match +#define AT91C_SA4_ADDR ((unsigned int) (1 << 23)) //* Specific address 4 match +#define AT91C_TYPE_ID ((unsigned int) (1 << 22)) //* Type ID match +#define AT91C_VLAN_TAG ((unsigned int) (1 << 21)) //* VLAN tag detected +#define AT91C_PRIORITY_TAG ((unsigned int) (1 << 20)) //* PRIORITY tag detected +#define AT91C_VLAN_PRIORITY ((unsigned int) (7 << 17)) //* PRIORITY Mask +#define AT91C_CFI_IND ((unsigned int) (1 << 16)) //* CFI indicator +#define AT91C_EOF ((unsigned int) (1 << 15)) //* EOF +#define AT91C_SOF ((unsigned int) (1 << 14)) //* SOF +#define AT91C_RBF_OFFSET ((unsigned int) (3 << 12)) //* Receive Buffer Offset Mask +#define AT91C_LENGTH_FRAME ((unsigned int) 0x07FF) //* Length of frame + +/* Transmit Status definition */ +#define AT91C_TRANSMIT_OK ((unsigned int) (1 << 31)) //* +#define AT91C_TRANSMIT_WRAP ((unsigned int) (1 << 30)) //* Wrap bit: mark the last descriptor +#define AT91C_TRANSMIT_ERR ((unsigned int) (1 << 29)) //* RLE:transmit error +#define AT91C_TRANSMIT_UND ((unsigned int) (1 << 28)) //* Transmit Underrun +#define AT91C_BUF_EX ((unsigned int) (1 << 27)) //* Buffers exhausted in mid frame +#define AT91C_TRANSMIT_NO_CRC ((unsigned int) (1 << 16)) //* No CRC will be appended to the current frame +#define AT91C_LAST_BUFFER ((unsigned int) (1 << 15)) //* + +#define ARP_ETHER 1 /* Ethernet hardware address */ +#define ARPOP_REQUEST 1 /* Request to resolve address */ +#define ARPOP_REPLY 2 /* Response to previous request */ +#define RARPOP_REQUEST 3 /* Request to resolve address */ +#define RARPOP_REPLY 4 /* Response to previous request */ + + +typedef struct _AT91S_EthHdr +{ + unsigned char et_dest[6]; /* Destination node */ + unsigned char et_src[6]; /* Source node */ + unsigned short et_protlen; /* Protocol or length */ +} AT91S_EthHdr, *AT91PS_EthHdr; + +typedef struct _AT91S_ArpHdr +{ + unsigned short ar_hrd; /* Format of hardware address */ + unsigned short ar_pro; /* Format of protocol address */ + unsigned char ar_hln; /* Length of hardware address */ + unsigned char ar_pln; /* Length of protocol address */ + unsigned short ar_op; /* Operation */ + unsigned char ar_sha[6]; /* Sender hardware address */ + unsigned char ar_spa[4]; /* Sender protocol address */ + unsigned char ar_tha[6]; /* Target hardware address */ + unsigned char ar_tpa[4]; /* Target protocol address */ +} AT91S_ArpHdr, *AT91PS_ArpHdr; + +//* IP Header structure +typedef struct _AT91S_IPheader { + unsigned char ip_hl_v; /* header length and version */ + unsigned char ip_tos; /* type of service */ + unsigned short ip_len; /* total length */ + unsigned short ip_id; /* identification */ + unsigned short ip_off; /* fragment offset field */ + unsigned char ip_ttl; /* time to live */ + unsigned char ip_p; /* protocol */ + unsigned short ip_sum; /* checksum */ + unsigned char ip_src[4]; /* Source IP address */ + unsigned char ip_dst[4]; /* Destination IP address */ + unsigned short udp_src; /* UDP source port */ + unsigned short udp_dst; /* UDP destination port */ + unsigned short udp_len; /* Length of UDP packet */ + unsigned short udp_xsum; /* Checksum */ +} AT91S_IPheader, *AT91PS_IPheader; + +//* ICMP echo header structure +typedef struct _AT91S_IcmpEchoHdr { + unsigned char type; /* type of message */ + unsigned char code; /* type subcode */ + unsigned short cksum; /* ones complement cksum of struct */ + unsigned short id; /* identifier */ + unsigned short seq; /* sequence number */ +}AT91S_IcmpEchoHdr, *AT91PS_IcmpEchoHdr; + + +typedef struct _AT91S_EthPack +{ + AT91S_EthHdr EthHdr; + AT91S_ArpHdr ArpHdr; +} AT91S_EthPack, *AT91PS_EthPack; + + +#endif //* AT91C_EMAC_H diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/SrcAtmel/mii.h b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/SrcAtmel/mii.h new file mode 100644 index 000000000..29b2f53d5 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/SrcAtmel/mii.h @@ -0,0 +1,105 @@ +/* Generic MII registers. */ + +#define MII_BMCR 0x00 /* Basic mode control register */ +#define MII_BMSR 0x01 /* Basic mode status register */ +#define MII_PHYSID1 0x02 /* PHYS ID 1 */ +#define MII_PHYSID2 0x03 /* PHYS ID 2 */ +#define MII_ADVERTISE 0x04 /* Advertisement control reg */ +#define MII_LPA 0x05 /* Link partner ability reg */ +#define MII_EXPANSION 0x06 /* Expansion register */ +#define MII_DCOUNTER 0x12 /* Disconnect counter */ +#define MII_FCSCOUNTER 0x13 /* False carrier counter */ +#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */ +#define MII_RERRCOUNTER 0x15 /* Receive error counter */ +#define MII_SREVISION 0x16 /* Silicon revision */ +#define MII_RESV1 0x17 /* Reserved... */ +#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */ +#define MII_PHYADDR 0x19 /* PHY address */ +#define MII_RESV2 0x1a /* Reserved... */ +#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */ +#define MII_NCONFIG 0x1c /* Network interface config */ + +/* Basic mode control register. */ +#define BMCR_RESV 0x007f /* Unused... */ +#define BMCR_CTST 0x0080 /* Collision test */ +#define BMCR_FULLDPLX 0x0100 /* Full duplex */ +#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ +#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */ +#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */ +#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */ +#define BMCR_SPEED100 0x2000 /* Select 100Mbps */ +#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */ +#define BMCR_RESET 0x8000 /* Reset the DP83840 */ + +/* Basic mode status register. */ +#define BMSR_ERCAP 0x0001 /* Ext-reg capability */ +#define BMSR_JCD 0x0002 /* Jabber detected */ +#define BMSR_LSTATUS 0x0004 /* Link status */ +#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */ +#define BMSR_RFAULT 0x0010 /* Remote fault detected */ +#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ +#define BMSR_RESV 0x07c0 /* Unused... */ +#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ +#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */ +#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */ +#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */ +#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */ + +/* Advertisement control register. */ +#define ADVERTISE_SLCT 0x001f /* Selector bits */ +#define ADVERTISE_CSMA 0x0001 /* Only selector supported */ +#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ +#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ +#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ +#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ +#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */ +#define ADVERTISE_RESV 0x1c00 /* Unused... */ +#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */ +#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */ +#define ADVERTISE_NPAGE 0x8000 /* Next page bit */ + +#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ + ADVERTISE_CSMA) +#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ + ADVERTISE_100HALF | ADVERTISE_100FULL) + +/* Link partner ability register. */ +#define LPA_SLCT 0x001f /* Same as advertise selector */ +#define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */ +#define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */ +#define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */ +#define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */ +#define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */ +#define LPA_RESV 0x1c00 /* Unused... */ +#define LPA_RFAULT 0x2000 /* Link partner faulted */ +#define LPA_LPACK 0x4000 /* Link partner acked us */ +#define LPA_NPAGE 0x8000 /* Next page bit */ + +#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) +#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) + +/* Expansion register for auto-negotiation. */ +#define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */ +#define EXPANSION_LCWP 0x0002 /* Got new RX page code word */ +#define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */ +#define EXPANSION_NPCAPABLE 0x0008 /* Link partner supports npage */ +#define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */ +#define EXPANSION_RESV 0xffe0 /* Unused... */ + +/* N-way test register. */ +#define NWAYTEST_RESV1 0x00ff /* Unused... */ +#define NWAYTEST_LOOPBACK 0x0100 /* Enable loopback for N-way */ +#define NWAYTEST_RESV2 0xfe00 /* Unused... */ + +#define SPEED_10 10 +#define SPEED_100 100 + +/* Duplex, half or full. */ +#define DUPLEX_HALF 0x00 +#define DUPLEX_FULL 0x01 + +/* PHY ID */ +#define MII_DM9161_ID 0x0181b8a0 +#define MII_AM79C875_ID 0x00225540 /* 0x00225541 */ + +#define AT91C_PHY_ADDR 31 diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/USB/USBSample.c b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/USB/USBSample.c new file mode 100644 index 000000000..50c7bbe45 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/USB/USBSample.c @@ -0,0 +1,1170 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + Sample interrupt driven mouse device driver. This is a minimal implementation + for demonstration only. Although functional, it may not be a fully and + compliant implementation. The small joystick on the SAM7X EK can be used to + move the mouse cursor, pressing the joystick transmits mouse clicks. Note + that it might be necessary to run the demo stand along (without the + debugger) in order for the USB device to be recognised by the host computer. + + The interrupt handler itself is contained within USB_ISR.c. + + See the FreeRTOS.org online documentation for more information. +*/ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* Demo application includes. */ +#include "USBSample.h" + +/* Joystick inputs used to move the 'mouse' cursor. */ +#define usbSW1 ( 1 << 21 ) /* PA21 */ +#define usbSW2 ( 1 << 22 ) /* PA22 */ +#define usbSW3 ( 1 << 23 ) /* PA23 */ +#define usbSW4 ( 1 << 24 ) /* PA24 */ +#define usbSW_CLICK ( 1 << 25 ) /* PA25 */ + +/* Descriptor type definitions. */ +#define usbDESCRIPTOR_TYPE_DEVICE ( 0x01 ) +#define usbDESCRIPTOR_TYPE_CONFIGURATION ( 0x02 ) +#define usbDESCRIPTOR_TYPE_STRING ( 0x03 ) + +/* USB request type definitions. */ +#define usbGET_REPORT_REQUEST ( 0x01 ) +#define usbGET_IDLE_REQUEST ( 0x02 ) +#define usbGET_PROTOCOL_REQUEST ( 0x03 ) +#define usbSET_REPORT_REQUEST ( 0x09 ) +#define usbSET_IDLE_REQUEST ( 0x0A ) +#define usbSET_PROTOCOL_REQUEST ( 0x0B ) +#define usbGET_CONFIGURATION_REQUEST ( 0x08 ) +#define usbGET_STATUS_REQUEST ( 0x00 ) +#define usbCLEAR_FEATURE_REQUEST ( 0x01 ) +#define usbSET_FEATURE_REQUEST ( 0x03 ) +#define usbSET_ADDRESS_REQUEST ( 0x05 ) +#define usbGET_DESCRIPTOR_REQUEST ( 0x06 ) +#define usbSET_CONFIGURATION_REQUEST ( 0x09 ) +#define usbGET_INTERFACE_REQUEST ( 0x0A ) +#define usbSET_INTERFACE_REQUEST ( 0x0B ) + + +/* Misc USB definitions. */ +#define usbDEVICE_CLASS_VENDOR_SPECIFIC ( 0xFF ) +#define usbBUS_POWERED ( 0x80 ) +#define usbHID_REPORT_DESCRIPTOR ( 0x22 ) +#define AT91C_UDP_TRANSCEIVER_ENABLE ( *( ( unsigned long * ) 0xfffb0074 ) ) + +/* Index to the various string. */ +#define usbLANGUAGE_STRING ( 0 ) +#define usbMANUFACTURER_STRING ( 1 ) +#define usbPRODUCT_STRING ( 2 ) +#define usbCONFIGURATION_STRING ( 3 ) +#define usbINTERFACE_STRING ( 4 ) + +/* Data indexes for reading the request from the xISRStatus.ucFifoData[] +into xUSB_REQUEST. The data order is designed for speed - so looks a +little odd. */ +#define usbREQUEST_TYPE_INDEX ( 7 ) +#define usbREQUEST_INDEX ( 6 ) +#define usbVALUE_HIGH_BYTE ( 4 ) +#define usbVALUE_LOW_BYTE ( 5 ) +#define usbINDEX_HIGH_BYTE ( 2 ) +#define usbINDEX_LOW_BYTE ( 3 ) +#define usbLENGTH_HIGH_BYTE ( 0 ) +#define usbLENGTH_LOW_BYTE ( 1 ) + +/* Misc application definitions. */ +#define usbINTERRUPT_PRIORITY ( 3 ) +#define usbFIFO_LENGTH ( ( unsigned portLONG ) 8 ) +#define usbXUP ( 1 ) +#define usbXDOWN ( 2 ) +#define usbYUP ( 3 ) +#define usbYDOWN ( 4 ) +#define usbMAX_COORD ( 120 ) +#define usbMAX_TX_MESSAGE_SIZE ( 128 ) +#define usbSHORTEST_DELAY ( ( portTickType ) 1 ) +#define usbINIT_DELAY ( ( portTickType ) 1000 / portTICK_RATE_MS ) +#define usbSHORT_DELAY ( ( portTickType ) 50 / portTICK_RATE_MS ) +#define usbEND_POINT_RESET_MASK ( ( unsigned portLONG ) 0x0f ) +#define usbDATA_INC ( ( portCHAR ) 5 ) +#define usbEXPECTED_NUMBER_OF_BYTES ( ( unsigned portLONG ) 8 ) + +/* Control request types. */ +#define usbSTANDARD_DEVICE_REQUEST ( 0 ) +#define usbSTANDARD_INTERFACE_REQUEST ( 1 ) +#define usbSTANDARD_END_POINT_REQUEST ( 2 ) +#define usbCLASS_INTERFACE_REQUEST ( 5 ) + +/* Structure used to hold the received requests. */ +typedef struct +{ + unsigned portCHAR ucReqType; + unsigned portCHAR ucRequest; + unsigned portSHORT usValue; + unsigned portSHORT usIndex; + unsigned portSHORT usLength; +} xUSB_REQUEST; + +typedef enum +{ + eNOTHING, + eJUST_RESET, + eJUST_GOT_CONFIG, + eJUST_GOT_ADDRESS, + eSENDING_EVEN_DESCRIPTOR, + eREADY_TO_SEND +} eDRIVER_STATE; + +/* Structure used to control the data being sent to the host. */ +typedef struct +{ + unsigned portCHAR ucTxBuffer[ usbMAX_TX_MESSAGE_SIZE ]; + unsigned portLONG ulNextCharIndex; + unsigned portLONG ulTotalDataLength; +} xTX_MESSAGE; + +/*-----------------------------------------------------------*/ + +/* + * The USB interrupt service routine. This takes a snapshot of the USB + * device at the time of the interrupt, clears the interrupts, and posts + * the data to the USB processing task. This is implemented in USB_ISR.c. + */ +extern void vUSB_ISR_Wrapper( void ); + +/* + * Called after the bus reset interrupt - this function readies all the + * end points for communication. + */ +static void prvResetEndPoints( void ); + +/* + * Setup the USB hardware, install the interrupt service routine and + * initialise all the state variables. + */ +static void vInitUSBInterface( void ); + +/* + * Decode and act upon an interrupt generated by the control end point. + */ +static void prvProcessEndPoint0Interrupt( xISRStatus *pxMessage ); + +/* + * For simplicity requests are separated into device, interface, class + * interface and end point requests. + * + * Decode and handle standard device requests originating on the control + * end point. + */ +static void prvHandleStandardDeviceRequest( xUSB_REQUEST *pxRequest ); + +/* + * For simplicity requests are separated into device, interface, class + * interface and end point requests. + * + * Decode and handle standard interface requests originating on the control + * end point. + */ +static void prvHandleStandardInterfaceRequest( xUSB_REQUEST *pxRequest ); + +/* + * For simplicity requests are separated into device, interface, class + * interface and end point requests. + * + * Decode and handle standard end point requests originating on the control + * end point. + */ +static void prvHandleStandardEndPointRequest( xUSB_REQUEST *pxRequest ); + +/* + * For simplicity requests are separated into device, interface, class + * interface and end point requests. + * + * Decode and handle the class interface requests. + */ +static void prvHandleClassInterfaceRequest( xUSB_REQUEST *pxRequest ); + +/* + * Setup the Tx buffer to send data in response to a control request. + * + * The data to be transmitted is buffered, the state variables are updated, + * then prvSendNextSegment() is called to start the transmission off. Once + * the first segment has been sent the remaining segments are transmitted + * in response to TXCOMP interrupts until the entire buffer has been + * sent. + */ +static void prvSendControlData( unsigned portCHAR *pucData, unsigned portSHORT usRequestedLength, unsigned portLONG ulLengthLeftToSend, portLONG lSendingDescriptor ); + +/* + * Examine the Tx buffer to see if there is any more data to be transmitted. + * + * If there is data to be transmitted then send the next segment. A segment + * can have a maximum of 8 bytes (this is defined as the maximum for the end + * point by the descriptor). The final segment may be less than 8 bytes if + * the total data length was not an exact multiple of 8. + */ +static void prvSendNextSegment( void ); + +/* + * A stall condition is forced each time the host makes a request that is not + * supported by this minimal implementation. + * + * A stall is forced by setting the appropriate bit in the end points control + * and status register. + */ +static void prvSendStall( void ); + +/* + * A NULL (or zero length packet) is transmitted in acknowledge the reception + * of certain events from the host. + */ +static void prvUSBTransmitNull( void ); + +/* + * When the host requests a descriptor this function is called to determine + * which descriptor is being requested and start its transmission. + */ +static void prvGetStandardInterfaceDescriptor( xUSB_REQUEST *pxRequest ); + +/* + * Transmit movement and clicks on the EK joystick as mouse inputs. + */ +static void prvTransmitSampleValues( void ); + +/* + * The created task to handle the USB demo functionality. + */ +static void vUSBDemoTask( void *pvParameters ); + +/* + * Simple algorithm to ramp up the mouse cursor speed to make it easier to + * use. + */ +static void prvControlCursorSpeed( signed portCHAR *cVal, unsigned portLONG ulInput, unsigned portLONG ulSwitch1, unsigned portLONG ulSwitch2 ); +/*-----------------------------------------------------------*/ + +/* + - DESCRIPTOR DEFINITIONS - +*/ + +/* String descriptors used during the enumeration process. +These take the form: + +{ + Length of descriptor, + Descriptor type, + Data +} +*/ +const portCHAR pxLanguageStringDescriptor[] = +{ + 4, + usbDESCRIPTOR_TYPE_STRING, + 0x09, 0x04 +}; + +const portCHAR pxManufacturerStringDescriptor[] = +{ + 18, + usbDESCRIPTOR_TYPE_STRING, + + 'F', 0x00, + 'r', 0x00, + 'e', 0x00, + 'e', 0x00, + 'R', 0x00, + 'T', 0x00, + 'O', 0x00, + 'S', 0x00 +}; + +const portCHAR pxProductStringDescriptor[] = +{ + 38, + usbDESCRIPTOR_TYPE_STRING, + + 'F', 0x00, + 'r', 0x00, + 'e', 0x00, + 'e', 0x00, + 'R', 0x00, + 'T', 0x00, + 'O', 0x00, + 'S', 0x00, + '.', 0x00, + 'o', 0x00, + 'r', 0x00, + 'g', 0x00, + ' ', 0x00, + 'M', 0x00, + 'o', 0x00, + 'u', 0x00, + 's', 0x00, + 'e', 0x00 +}; + +const portCHAR pxConfigurationStringDescriptor[] = +{ + 38, + usbDESCRIPTOR_TYPE_STRING, + + 'C', 0x00, + 'o', 0x00, + 'n', 0x00, + 'f', 0x00, + 'i', 0x00, + 'g', 0x00, + 'u', 0x00, + 'r', 0x00, + 'a', 0x00, + 't', 0x00, + 'i', 0x00, + 'o', 0x00, + 'n', 0x00, + ' ', 0x00, + 'N', 0x00, + 'a', 0x00, + 'm', 0x00, + 'e', 0x00 +}; + +const portCHAR pxInterfaceStringDescriptor[] = +{ + 30, + usbDESCRIPTOR_TYPE_STRING, + + 'I', 0x00, + 'n', 0x00, + 't', 0x00, + 'e', 0x00, + 'r', 0x00, + 'f', 0x00, + 'a', 0x00, + 'c', 0x00, + 'e', 0x00, + ' ', 0x00, + 'N', 0x00, + 'a', 0x00, + 'm', 0x00, + 'e', 0x00 +}; + +/* Enumeration descriptors. */ +const portCHAR pxReportDescriptor[] = +{ + 0x05, 0x01, /* USAGE_PAGE (Generic Desktop) */ + 0x09, 0x02, /* USAGE (Mouse) */ + 0xa1, 0x01, /* COLLECTION (Application) */ + 0x09, 0x01, /* USAGE (Pointer) */ + 0xa1, 0x00, /* COLLECTION (Physical) */ + 0x95, 0x03, /* REPORT_COUNT (3) */ + 0x75, 0x01, /* REPORT_SIZE (1) */ + 0x05, 0x09, /* USAGE_PAGE (Button) */ + 0x19, 0x01, /* USAGE_MINIMUM (Button 1) */ + 0x29, 0x03, /* USAGE_MAXIMUM (Button 3) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x25, 0x01, /* LOGICAL_MAXIMUM (1) */ + 0x81, 0x02, /* INPUT (Data,Var,Abs) */ + 0x95, 0x01, /* REPORT_COUNT (1) */ + 0x75, 0x05, /* REPORT_SIZE (5) */ + 0x81, 0x01, /* INPUT (Cnst,Ary,Abs) */ + 0x75, 0x08, /* REPORT_SIZE (8) */ + 0x95, 0x02, /* REPORT_COUNT (2) */ + 0x05, 0x01, /* USAGE_PAGE (Generic Desktop) */ + 0x09, 0x30, /* USAGE (X) */ + 0x09, 0x31, /* USAGE (Y) */ + 0x15, 0x81, /* LOGICAL_MINIMUM (-127) */ + 0x25, 0x7f, /* LOGICAL_MAXIMUM (127) */ + 0x81, 0x06, /* INPUT (Data,Var,Rel) */ + 0xc0, /* END_COLLECTION */ + 0xc0 /* END_COLLECTION */ +}; + + + +const char pxDeviceDescriptor[] = +{ + /* Device descriptor */ + 0x12, /* bLength */ + 0x01, /* bDescriptorType */ + 0x10, 0x01, /* bcdUSBL */ + usbDEVICE_CLASS_VENDOR_SPECIFIC, /* bDeviceClass: */ + 0x00, /* bDeviceSubclass: */ + 0x00, /* bDeviceProtocol: */ + 0x08, /* bMaxPacketSize0 */ + 0xFF, 0xFF, /* idVendorL */ + 0x02, 0x00, /* idProductL */ + 0x00, 0x01, /* bcdDeviceL */ + usbMANUFACTURER_STRING, /* iManufacturer */ + usbPRODUCT_STRING, /* iProduct */ + 0x00, /* SerialNumber */ + 0x01 /* bNumConfigs */ +}; + + +const char pxConfigDescriptor[] = { + /* Configuration 1 descriptor */ + 0x09, /* CbLength */ + 0x02, /* CbDescriptorType */ + 0x22, 0x00, /* CwTotalLength 2 EP + Control */ + 0x01, /* CbNumInterfaces */ + 0x01, /* CbConfigurationValue */ + usbCONFIGURATION_STRING,/* CiConfiguration */ + usbBUS_POWERED, /* CbmAttributes Bus powered + Remote Wakeup*/ + 0x32, /* CMaxPower: 100mA */ + + /* Mouse Interface Descriptor Requirement */ + 0x09, /* bLength */ + 0x04, /* bDescriptorType */ + 0x00, /* bInterfaceNumber */ + 0x00, /* bAlternateSetting */ + 0x01, /* bNumEndpoints */ + 0x03, /* bInterfaceClass: HID code */ + 0x01, /* bInterfaceSubclass boot */ + 0x02, /* bInterfaceProtocol mouse boot */ + usbINTERFACE_STRING,/* iInterface */ + + /* HID Descriptor */ + 0x09, /* bLength */ + 0x21, /* bDescriptor type: HID Descriptor Type */ + 0x00, 0x01, /* bcdHID */ + 0x00, /* bCountryCode */ + 0x01, /* bNumDescriptors */ + usbHID_REPORT_DESCRIPTOR, /* bDescriptorType */ + sizeof( pxReportDescriptor ), 0x00, /* wItemLength */ + + /* Endpoint 1 descriptor */ + 0x07, /* bLength */ + 0x05, /* bDescriptorType */ + 0x81, /* bEndpointAddress, Endpoint 01 - IN */ + 0x03, /* bmAttributes INT */ + 0x08, 0x00, /* wMaxPacketSize: 8? */ + 0x0A /* bInterval */ +}; + +/*-----------------------------------------------------------*/ + +/* File scope state variables. */ +static unsigned portCHAR ucUSBConfig = ( unsigned portCHAR ) 0; +static unsigned portLONG ulReceivedAddress = ( unsigned portLONG ) 0; +static eDRIVER_STATE eDriverState = eNOTHING; + +/* Structure used to control the characters being sent to the host. */ +static xTX_MESSAGE pxCharsForTx; + +/* Queue used to pass messages between the ISR and the task. */ +xQueueHandle xUSBInterruptQueue; + +/*-----------------------------------------------------------*/ + +void vStartUSBTask( unsigned portBASE_TYPE uxPriority ) +{ + /* Create the queue used to communicate between the USB ISR and task. */ + xUSBInterruptQueue = xQueueCreate( usbQUEUE_LENGTH + 1, sizeof( xISRStatus * ) ); + + /* Create the task itself. */ + xTaskCreate( vUSBDemoTask, "USB", configMINIMAL_STACK_SIZE, NULL, uxPriority, NULL ); +} +/*-----------------------------------------------------------*/ + +static void vUSBDemoTask( void *pvParameters ) +{ +xISRStatus *pxMessage; + + /* The parameters are not used in this task. */ + ( void ) pvParameters; + + /* Init USB device */ + portENTER_CRITICAL(); + vInitUSBInterface(); + portEXIT_CRITICAL(); + + /* Process interrupts as they arrive. The ISR takes a snapshot of the + interrupt status then posts the information on this queue for processing + at the task level. This simple demo implementation only processes + a few interrupt sources. */ + for( ;; ) + { + if( xQueueReceive( xUSBInterruptQueue, &pxMessage, usbSHORT_DELAY ) ) + { + if( pxMessage->ulISR & AT91C_UDP_EPINT0 ) + { + /* Process end point 0 interrupt. */ + prvProcessEndPoint0Interrupt( pxMessage ); + } + + if( pxMessage->ulISR & AT91C_UDP_ENDBUSRES ) + { + /* Process an end of bus reset interrupt. */ + prvResetEndPoints(); + } + } + else + { + /* The ISR did not post any data for us to process on the queue, so + just generate and send some sample data. */ + if( eDriverState == eREADY_TO_SEND ) + { + prvTransmitSampleValues(); + } + } + } +} +/*-----------------------------------------------------------*/ + +static void prvControlCursorSpeed( signed portCHAR *cVal, unsigned portLONG ulInput, unsigned portLONG ulSwitch1, unsigned portLONG ulSwitch2 ) +{ +const portCHAR cSpeed = 20; + + if( !( ulInput & ulSwitch1 ) ) + { + /* We are going in the decreasing y direction. */ + if( *cVal > 0 ) + { + /* We have changed direction since last time so start from + 0 again. */ + *cVal = 0; + } + + if( *cVal > -cSpeed ) + { + /* Ramp y down to the max speed. */ + (*cVal)--; + } + } + else if( !( ulInput & ulSwitch2 ) ) + { + /* We are going in the increasing y direction. */ + if( *cVal < 0 ) + { + /* We have changed direction since last time, so start from + 0 again. */ + *cVal = 0; + } + + if( *cVal < cSpeed ) + { + /* Ramp y up to the max speed again. */ + (*cVal)++; + } + } + else + { + *cVal = 0; + } +} +/*-----------------------------------------------------------*/ + +static void prvTransmitSampleValues( void ) +{ +/* Variables to hold dummy x, y and z joystick axis data. */ +static signed portCHAR x = 0, y = 0, z = 0; +unsigned portLONG ulStatus; + + ulStatus = AT91C_BASE_PIOA->PIO_PDSR; + + prvControlCursorSpeed( &y, ulStatus, ( unsigned long ) usbSW1, ( unsigned long ) usbSW2 ); + prvControlCursorSpeed( &x, ulStatus, ( unsigned long ) usbSW3, ( unsigned long ) usbSW4 ); + + /* Just make the z axis go up and down. */ + z = ( ( ulStatus & usbSW_CLICK ) == 0 ); + + /* Can we place data in the fifo? */ + if( !( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] & AT91C_UDP_TXPKTRDY ) ) + { + /* Write our sample data to the fifo. */ + AT91C_BASE_UDP->UDP_FDR[ usbEND_POINT_1 ] = z; + AT91C_BASE_UDP->UDP_FDR[ usbEND_POINT_1 ] = x; + AT91C_BASE_UDP->UDP_FDR[ usbEND_POINT_1 ] = y; + + /* Send the data. */ + portENTER_CRITICAL(); + { + ulStatus = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ]; + usbCSR_SET_BIT( &ulStatus, ( AT91C_UDP_TXPKTRDY ) ); + AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] = ulStatus; + } + portEXIT_CRITICAL(); + } +} +/*-----------------------------------------------------------*/ + +static void prvUSBTransmitNull( void ) +{ +unsigned portLONG ulStatus; + + /* Wait until the FIFO is free - even though we are not going to use it. + THERE IS NO TIMEOUT HERE! */ + while( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] & AT91C_UDP_TXPKTRDY ) + { + vTaskDelay( usbSHORTEST_DELAY ); + } + + portENTER_CRITICAL(); + { + /* Set the length of data to send to equal the index of the next byte + to send. This will prevent the ACK to this NULL packet causing any + further data transmissions. */ + pxCharsForTx.ulTotalDataLength = pxCharsForTx.ulNextCharIndex; + + /* Set the TXPKTRDY bit to cause a transmission with no data. */ + ulStatus = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ]; + usbCSR_SET_BIT( &ulStatus, ( AT91C_UDP_TXPKTRDY ) ); + AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulStatus; + } + portEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +static void prvSendStall( void ) +{ +unsigned portLONG ulStatus; + + portENTER_CRITICAL(); + { + /* Force a stall by simply setting the FORCESTALL bit in the CSR. */ + ulStatus = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ]; + usbCSR_SET_BIT( &ulStatus, AT91C_UDP_FORCESTALL ); + AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulStatus; + } + portEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +static void prvResetEndPoints( void ) +{ +unsigned portLONG ulTemp; + + eDriverState = eJUST_RESET; + + /* Reset all the end points. */ + AT91C_BASE_UDP->UDP_RSTEP = usbEND_POINT_RESET_MASK; + AT91C_BASE_UDP->UDP_RSTEP = ( unsigned portLONG ) 0x00; + + /* Enable data to be sent and received. */ + AT91C_BASE_UDP->UDP_FADDR = AT91C_UDP_FEN; + + /* Repair the configuration end point. */ + portENTER_CRITICAL(); + { + ulTemp = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ]; + usbCSR_SET_BIT( &ulTemp, ( ( unsigned portLONG ) ( AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_CTRL ) ) ); + AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulTemp; + AT91C_BASE_UDP->UDP_IER = AT91C_UDP_EPINT0; + } + portEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +static void prvProcessEndPoint0Interrupt( xISRStatus *pxMessage ) +{ + if( pxMessage->ulCSR0 & AT91C_UDP_RX_DATA_BK0 ) + { + /* We only expect to receive zero length data here as ACK's. + Set the data pointer to the end of the current Tx packet to + ensure we don't send out any more data. */ + pxCharsForTx.ulNextCharIndex = pxCharsForTx.ulTotalDataLength; + } + + if( pxMessage->ulCSR0 & AT91C_UDP_TXCOMP ) + { + /* We received a TX complete interrupt. What we do depends on + what we sent to get this interrupt. */ + + if( eDriverState == eJUST_GOT_CONFIG ) + { + /* We sent an acknowledgement of a SET_CONFIG request. We + are now at the end of the enumeration. */ + AT91C_BASE_UDP->UDP_GLBSTATE = AT91C_UDP_CONFG; + + /* Read the end point for data transfer. */ + portENTER_CRITICAL(); + { + unsigned portLONG ulTemp; + + ulTemp = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ]; + usbCSR_SET_BIT( &ulTemp, AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_INT_IN ); + AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] = ulTemp; + AT91C_BASE_UDP->UDP_IER = AT91C_UDP_EPINT1; + } + portEXIT_CRITICAL(); + + eDriverState = eREADY_TO_SEND; + } + else if( eDriverState == eJUST_GOT_ADDRESS ) + { + /* We sent an acknowledgement of a SET_ADDRESS request. Move + to the addressed state. */ + if( ulReceivedAddress != ( unsigned portLONG ) 0 ) + { + AT91C_BASE_UDP->UDP_GLBSTATE = AT91C_UDP_FADDEN; + } + else + { + AT91C_BASE_UDP->UDP_GLBSTATE = 0; + } + + AT91C_BASE_UDP->UDP_FADDR = ( AT91C_UDP_FEN | ulReceivedAddress ); + eDriverState = eNOTHING; + } + else + { + /* The TXCOMP was not for any special type of transmission. See + if there is any more data to send. */ + prvSendNextSegment(); + } + } + + if( pxMessage->ulCSR0 & AT91C_UDP_RXSETUP ) + { + xUSB_REQUEST xRequest; + unsigned portCHAR ucRequest; + unsigned portLONG ulRxBytes; + + /* A data packet is available. */ + ulRxBytes = pxMessage->ulCSR0 >> 16; + ulRxBytes &= usbRX_COUNT_MASK; + + if( ulRxBytes >= usbEXPECTED_NUMBER_OF_BYTES ) + { + /* Create an xUSB_REQUEST variable from the raw bytes array. */ + + xRequest.ucReqType = pxMessage->ucFifoData[ usbREQUEST_TYPE_INDEX ]; + xRequest.ucRequest = pxMessage->ucFifoData[ usbREQUEST_INDEX ]; + + /* NOT PORTABLE CODE! */ + xRequest.usValue = pxMessage->ucFifoData[ usbVALUE_HIGH_BYTE ]; + xRequest.usValue <<= 8; + xRequest.usValue |= pxMessage->ucFifoData[ usbVALUE_LOW_BYTE ]; + + xRequest.usIndex = pxMessage->ucFifoData[ usbINDEX_HIGH_BYTE ]; + xRequest.usIndex <<= 8; + xRequest.usIndex |= pxMessage->ucFifoData[ usbINDEX_LOW_BYTE ]; + + xRequest.usLength = pxMessage->ucFifoData[ usbLENGTH_HIGH_BYTE ]; + xRequest.usLength <<= 8; + xRequest.usLength |= pxMessage->ucFifoData[ usbLENGTH_LOW_BYTE ]; + + /* Manipulate the ucRequestType and the ucRequest parameters to + generate a zero based request selection. This is just done to + break up the requests into subsections for clarity. The + alternative would be to have more huge switch statement that would + be difficult to optimise. */ + ucRequest = ( ( xRequest.ucReqType & 0x60 ) >> 3 ); + ucRequest |= ( xRequest.ucReqType & 0x03 ); + + switch( ucRequest ) + { + case usbSTANDARD_DEVICE_REQUEST: + /* Standard Device request */ + prvHandleStandardDeviceRequest( &xRequest ); + break; + + case usbSTANDARD_INTERFACE_REQUEST: + /* Standard Interface request */ + prvHandleStandardInterfaceRequest( &xRequest ); + break; + + case usbSTANDARD_END_POINT_REQUEST: + /* Standard Endpoint request */ + prvHandleStandardEndPointRequest( &xRequest ); + break; + + case usbCLASS_INTERFACE_REQUEST: + /* Class Interface request */ + prvHandleClassInterfaceRequest( &xRequest ); + break; + + default: /* This is not something we want to respond to. */ + prvSendStall(); + } + } + } +} +/*-----------------------------------------------------------*/ + +static void prvGetStandardDeviceDescriptor( xUSB_REQUEST *pxRequest ) +{ + /* The type is in the high byte. Return whatever has been requested. */ + switch( ( pxRequest->usValue & 0xff00 ) >> 8 ) + { + case usbDESCRIPTOR_TYPE_DEVICE: + prvSendControlData( ( unsigned portCHAR * ) &pxDeviceDescriptor, pxRequest->usLength, sizeof( pxDeviceDescriptor ), pdTRUE ); + break; + + case usbDESCRIPTOR_TYPE_CONFIGURATION: + prvSendControlData( ( unsigned portCHAR * ) &( pxConfigDescriptor ), pxRequest->usLength, sizeof( pxConfigDescriptor ), pdTRUE ); + break; + + case usbDESCRIPTOR_TYPE_STRING: + + /* The index to the string descriptor is the lower byte. */ + switch( pxRequest->usValue & 0xff ) + { + case usbLANGUAGE_STRING: + prvSendControlData( ( unsigned portCHAR * ) &pxLanguageStringDescriptor, pxRequest->usLength, sizeof(pxLanguageStringDescriptor), pdTRUE ); + break; + + case usbMANUFACTURER_STRING: + prvSendControlData( ( unsigned portCHAR * ) &pxManufacturerStringDescriptor, pxRequest->usLength, sizeof( pxManufacturerStringDescriptor ), pdTRUE ); + break; + + case usbPRODUCT_STRING: + prvSendControlData( ( unsigned portCHAR * ) &pxProductStringDescriptor, pxRequest->usLength, sizeof( pxProductStringDescriptor ), pdTRUE ); + break; + + case usbCONFIGURATION_STRING: + prvSendControlData( ( unsigned portCHAR * ) &pxConfigurationStringDescriptor, pxRequest->usLength, sizeof( pxConfigurationStringDescriptor ), pdTRUE ); + break; + + case usbINTERFACE_STRING: + prvSendControlData( ( unsigned portCHAR * ) &pxInterfaceStringDescriptor, pxRequest->usLength, sizeof( pxInterfaceStringDescriptor ), pdTRUE ); + break; + + default: + /* Don't know what this string is. */ + prvSendStall(); + break; + } + + break; + + default: + /* We are not responding to anything else. */ + prvSendStall(); + break; + } +} +/*-----------------------------------------------------------*/ + +static void prvHandleStandardDeviceRequest( xUSB_REQUEST *pxRequest ) +{ +unsigned portSHORT usStatus = 0; + + switch( pxRequest->ucRequest ) + { + case usbGET_STATUS_REQUEST: + /* Just send two byte dummy status. */ + prvSendControlData( ( unsigned portCHAR * ) &usStatus, sizeof( usStatus ), sizeof( usStatus ), pdFALSE ); + break; + + case usbGET_DESCRIPTOR_REQUEST: + /* Send device descriptor */ + prvGetStandardDeviceDescriptor( pxRequest ); + break; + + case usbGET_CONFIGURATION_REQUEST: + /* Send selected device configuration */ + prvSendControlData( ( unsigned portCHAR * ) &ucUSBConfig, sizeof( ucUSBConfig ), sizeof( ucUSBConfig ), pdFALSE ); + break; + + case usbSET_FEATURE_REQUEST: + prvUSBTransmitNull(); + break; + + case usbSET_ADDRESS_REQUEST: + + /* Acknowledge the SET_ADDRESS, but (according to the manual) we + cannot actually move to the addressed state until we get a TXCOMP + interrupt from this NULL packet. Therefore we just remember the + address and set our state so we know we have received the address. */ + prvUSBTransmitNull(); + eDriverState = eJUST_GOT_ADDRESS; + ulReceivedAddress = ( unsigned portLONG ) pxRequest->usValue; + break; + + case usbSET_CONFIGURATION_REQUEST: + + /* Acknowledge the SET_CONFIGURATION, but (according to the manual) + we cannot actually move to the configured state until we get a + TXCOMP interrupt from this NULL packet. Therefore we just remember the + config and set our state so we know we have received the go ahead. */ + ucUSBConfig = ( unsigned portCHAR ) ( pxRequest->usValue & 0xff ); + eDriverState = eJUST_GOT_CONFIG; + prvUSBTransmitNull(); + break; + + default: + + /* We don't answer to anything else. */ + prvSendStall(); + break; + } +} +/*-----------------------------------------------------------*/ + +static void prvHandleClassInterfaceRequest( xUSB_REQUEST *pxRequest ) +{ + switch( pxRequest->ucRequest ) + { + case usbSET_IDLE_REQUEST: + prvUSBTransmitNull(); + break; + + /* This minimal implementation ignores these. */ + case usbGET_REPORT_REQUEST: + case usbGET_IDLE_REQUEST: + case usbGET_PROTOCOL_REQUEST: + case usbSET_REPORT_REQUEST: + case usbSET_PROTOCOL_REQUEST: + default: + + prvSendStall(); + break; + } +} +/*-----------------------------------------------------------*/ + +static void prvGetStandardInterfaceDescriptor( xUSB_REQUEST *pxRequest ) +{ + switch( ( pxRequest->usValue & ( unsigned portSHORT ) 0xff00 ) >> 8 ) + { + case usbHID_REPORT_DESCRIPTOR: + prvSendControlData( ( unsigned portCHAR * ) pxReportDescriptor, pxRequest->usLength, sizeof( pxReportDescriptor ), pdTRUE ); + break; + + default: + + /* Don't expect to send any others. */ + prvSendStall(); + break; + } +} +/*-----------------------------------------------------------*/ + +static void prvHandleStandardInterfaceRequest( xUSB_REQUEST *pxRequest ) +{ +unsigned portSHORT usStatus = 0; + + switch( pxRequest->ucRequest ) + { + case usbGET_STATUS_REQUEST: + /* Send dummy 2 bytes. */ + prvSendControlData( ( unsigned portCHAR * ) &usStatus, sizeof( usStatus ), sizeof( usStatus ), pdFALSE ); + break; + + case usbGET_DESCRIPTOR_REQUEST: + prvGetStandardInterfaceDescriptor( pxRequest ); + break; + + /* This minimal implementation does not respond to these. */ + case usbGET_INTERFACE_REQUEST: + case usbSET_FEATURE_REQUEST: + case usbSET_INTERFACE_REQUEST: + + default: + prvSendStall(); + break; + } +} +/*-----------------------------------------------------------*/ + +static void prvHandleStandardEndPointRequest( xUSB_REQUEST *pxRequest ) +{ + switch( pxRequest->ucRequest ) + { + /* This minimal implementation does not expect to respond to these. */ + case usbGET_STATUS_REQUEST: + case usbCLEAR_FEATURE_REQUEST: + case usbSET_FEATURE_REQUEST: + + default: + prvSendStall(); + break; + } +} +/*-----------------------------------------------------------*/ + +static void vInitUSBInterface( void ) +{ +volatile unsigned portLONG ulTemp; + + /* Initialise a few state variables. */ + pxCharsForTx.ulNextCharIndex = ( unsigned portLONG ) 0; + ucUSBConfig = ( unsigned portCHAR ) 0; + eDriverState = eNOTHING; + + /* HARDWARE SETUP */ + + /* Set the PLL USB Divider */ + AT91C_BASE_CKGR->CKGR_PLLR |= AT91C_CKGR_USBDIV_1; + + /* Enables the 48MHz USB clock UDPCK and System Peripheral USB Clock. */ + AT91C_BASE_PMC->PMC_SCER = AT91C_PMC_UDP; + AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_UDP); + + /* Setup the PIO for the USB pull up resistor. */ + AT91C_BASE_PIOA->PIO_PER = AT91C_PIO_PA16; + AT91C_BASE_PIOA->PIO_OER = AT91C_PIO_PA16; + + + /* Start without the pullup - this will get set at the end of this + function. */ + AT91C_BASE_PIOA->PIO_SODR = AT91C_PIO_PA16; + + /* When using the USB debugger the peripheral registers do not always get + set to the correct default values. To make sure set the relevant registers + manually here. */ + AT91C_BASE_UDP->UDP_IDR = ( unsigned portLONG ) 0xffffffff; + AT91C_BASE_UDP->UDP_ICR = ( unsigned portLONG ) 0xffffffff; + AT91C_BASE_UDP->UDP_CSR[ 0 ] = ( unsigned portLONG ) 0x00; + AT91C_BASE_UDP->UDP_CSR[ 1 ] = ( unsigned portLONG ) 0x00; + AT91C_BASE_UDP->UDP_GLBSTATE = 0; + AT91C_BASE_UDP->UDP_FADDR = 0; + + /* Enable the transceiver. */ + AT91C_UDP_TRANSCEIVER_ENABLE = 0; + + /* Enable the USB interrupts - other interrupts get enabled as the + enumeration process progresses. */ + AT91F_AIC_ConfigureIt( AT91C_ID_UDP, usbINTERRUPT_PRIORITY, AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, ( void (*)( void ) ) vUSB_ISR_Wrapper ); + AT91C_BASE_AIC->AIC_IECR = 0x1 << AT91C_ID_UDP; + + /* Wait a short while before making our presence known. */ + vTaskDelay( usbINIT_DELAY ); + AT91C_BASE_PIOA->PIO_CODR = AT91C_PIO_PA16; +} +/*-----------------------------------------------------------*/ + +static void prvSendControlData( unsigned portCHAR *pucData, unsigned portSHORT usRequestedLength, unsigned portLONG ulLengthToSend, portLONG lSendingDescriptor ) +{ + if( ( ( unsigned portLONG ) usRequestedLength < ulLengthToSend ) ) + { + /* Cap the data length to that requested. */ + ulLengthToSend = ( unsigned portSHORT ) usRequestedLength; + } + else if( ( ulLengthToSend < ( unsigned portLONG ) usRequestedLength ) && lSendingDescriptor ) + { + /* We are sending a descriptor. If the descriptor is an exact + multiple of the FIFO length then it will have to be terminated + with a NULL packet. Set the state to indicate this if + necessary. */ + if( ( ulLengthToSend % usbFIFO_LENGTH ) == 0 ) + { + eDriverState = eSENDING_EVEN_DESCRIPTOR; + } + } + + /* Here we assume that the previous message has been sent. THERE IS NO + BUFFER OVERFLOW PROTECTION HERE. + + Copy the data to send into the buffer as we cannot send it all at once + (if it is greater than 8 bytes in length). */ + memcpy( pxCharsForTx.ucTxBuffer, pucData, ulLengthToSend ); + + /* Reinitialise the buffer index so we start sending from the start of + the data. */ + pxCharsForTx.ulTotalDataLength = ulLengthToSend; + pxCharsForTx.ulNextCharIndex = ( unsigned portLONG ) 0; + + /* Send the first 8 bytes now. The rest will get sent in response to + TXCOMP interrupts. */ + prvSendNextSegment(); +} +/*-----------------------------------------------------------*/ + +static void prvSendNextSegment( void ) +{ +volatile unsigned portLONG ulNextLength, ulStatus, ulLengthLeftToSend; + + /* Is there any data to send? */ + if( pxCharsForTx.ulTotalDataLength > pxCharsForTx.ulNextCharIndex ) + { + ulLengthLeftToSend = pxCharsForTx.ulTotalDataLength - pxCharsForTx.ulNextCharIndex; + + /* We can only send 8 bytes to the fifo at a time. */ + if( ulLengthLeftToSend > usbFIFO_LENGTH ) + { + ulNextLength = usbFIFO_LENGTH; + } + else + { + ulNextLength = ulLengthLeftToSend; + } + + /* Wait until we can place data in the fifo. THERE IS NO TIMEOUT + HERE! */ + while( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] & AT91C_UDP_TXPKTRDY ) + { + vTaskDelay( usbSHORTEST_DELAY ); + } + + /* Write the data to the FIFO. */ + while( ulNextLength > ( unsigned portLONG ) 0 ) + { + AT91C_BASE_UDP->UDP_FDR[ usbEND_POINT_0 ] = pxCharsForTx.ucTxBuffer[ pxCharsForTx.ulNextCharIndex ]; + + ulNextLength--; + pxCharsForTx.ulNextCharIndex++; + } + + /* Start the transmission. */ + portENTER_CRITICAL(); + { + ulStatus = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ]; + usbCSR_SET_BIT( &ulStatus, ( ( unsigned portLONG ) 0x10 ) ); + AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulStatus; + } + portEXIT_CRITICAL(); + } + else + { + /* There is no data to send. If we were sending a descriptor and the + descriptor was an exact multiple of the max packet size then we need + to send a null to terminate the transmission. */ + if( eDriverState == eSENDING_EVEN_DESCRIPTOR ) + { + prvUSBTransmitNull(); + eDriverState = eNOTHING; + } + } +} + + + diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/USB/USBSample.h b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/USB/USBSample.h new file mode 100644 index 000000000..e0b3c1f2b --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/USB/USBSample.h @@ -0,0 +1,90 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef USB_DEMO_H +#define USB_DEMO_H + + +/*-----------------------------------------------------------*/ + +#define usbQUEUE_LENGTH ( 0x3 ) /* Must have all bits set! */ +#define usbEND_POINT_0 ( 0 ) +#define usbEND_POINT_1 ( 1 ) +#define usbRX_COUNT_MASK ( ( unsigned portLONG ) 0x7ff ) +#define AT91C_UDP_STALLSENT AT91C_UDP_ISOERROR + +/* Structure used to take a snapshot of the USB status from within the ISR. */ +typedef struct X_ISR_STATUS +{ + unsigned portLONG ulISR; + unsigned portLONG ulCSR0; + unsigned portCHAR ucFifoData[ 8 ]; +} xISRStatus; + +/* Macros to manipulate the control and status registers. These registers +cannot be accessed using a direct read modify write operation outside of the +ISR as some bits are left unchanged by writing with a 0, and some are left +unchanged by writing with a 1. */ + +#define usbCSR_SET_BIT( pulValueNow, ulBit ) \ +{ \ + /* Set TXCOMP, RX_DATA_BK0, RXSETUP, */ \ + /* STALLSENT and RX_DATA_BK1 to 1 so the */ \ + /* write has no effect. */ \ + ( * ( ( unsigned portLONG * ) pulValueNow ) ) |= ( unsigned portLONG ) 0x4f; \ + \ + /* Clear the FORCE_STALL and TXPKTRDY bits */ \ + /* so the write has no effect. */ \ + ( * ( ( unsigned portLONG * ) pulValueNow ) ) &= ( unsigned portLONG ) 0xffffffcf; \ + \ + /* Set whichever bit we want set. */ \ + ( * ( ( unsigned portLONG * ) pulValueNow ) ) |= ( ulBit ); \ +} + +/* + * Creates the queue used to communicate between the USB task and the USB ISR, then + * createst the task that manages the USB peripheral. + */ +void vStartUSBTask( unsigned portBASE_TYPE uxPriority ); + +#endif + diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/USB/USB_ISR.c b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/USB/USB_ISR.c new file mode 100644 index 000000000..34352895a --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/USB/USB_ISR.c @@ -0,0 +1,186 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* Demo app includes. */ +#include "USBSample.h" + +#define usbINT_CLEAR_MASK (AT91C_UDP_TXCOMP | AT91C_UDP_STALLSENT | AT91C_UDP_RXSETUP | AT91C_UDP_RX_DATA_BK0 | AT91C_UDP_RX_DATA_BK1 ) + +#define usbCSR_CLEAR_BIT( pulValueNow, ulBit ) \ +{ \ + /* Set TXCOMP, RX_DATA_BK0, RXSETUP, */ \ + /* STALLSENT and RX_DATA_BK1 to 1 so the */ \ + /* write has no effect. */ \ + ( * ( ( unsigned portLONG * ) pulValueNow ) ) |= ( unsigned portLONG ) 0x4f; \ + \ + /* Clear the FORCE_STALL and TXPKTRDY bits */ \ + /* so the write has no effect. */ \ + ( * ( ( unsigned portLONG * ) pulValueNow ) ) &= ( unsigned portLONG ) 0xffffffcf; \ + \ + /* Clear whichever bit we want clear. */ \ + ( * ( ( unsigned portLONG * ) pulValueNow ) ) &= ( ~ulBit ); \ +} + + +/*-----------------------------------------------------------*/ + +/* + * ISR entry point. + */ + +void vUSB_ISR_Wrapper( void ) __attribute__((naked)); + +/* + * Actual ISR handler. This must be separate from the entry point as the stack + * is used. + */ +void vUSB_ISR_Handler( void ); + +/*-----------------------------------------------------------*/ + +/* Array in which the USB interrupt status is passed between the ISR and task. */ +static xISRStatus xISRMessages[ usbQUEUE_LENGTH + 1 ]; + +/* Queue used to pass messages between the ISR and the task. */ +extern xQueueHandle xUSBInterruptQueue; + +/*-----------------------------------------------------------*/ + +void vUSB_ISR_Handler( void ) +{ +portBASE_TYPE xTaskWokenByPost = pdFALSE; +static volatile unsigned portLONG ulNextMessage = 0; +xISRStatus *pxMessage; +unsigned portLONG ulTemp, ulRxBytes; + + /* To reduce the amount of time spent in this interrupt it would be + possible to defer the majority of this processing to an 'interrupt task', + that is a task that runs at a higher priority than any of the application + tasks. */ + + /* Take the next message from the queue. Note that usbQUEUE_LENGTH *must* + be all 1's, as in 0x01, 0x03, 0x07, etc. */ + pxMessage = &( xISRMessages[ ( ulNextMessage & usbQUEUE_LENGTH ) ] ); + ulNextMessage++; + + /* Take a snapshot of the current USB state for processing at the task + level. */ + pxMessage->ulISR = AT91C_BASE_UDP->UDP_ISR; + pxMessage->ulCSR0 = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ]; + + /* Clear the interrupts from the ICR register. The bus end interrupt is + cleared separately as it does not appear in the mask register. */ + AT91C_BASE_UDP->UDP_ICR = AT91C_BASE_UDP->UDP_IMR | AT91C_UDP_ENDBUSRES; + + /* If there are bytes in the FIFO then we have to retrieve them here. + Ideally this would be done at the task level. However we need to clear the + RXSETUP interrupt before leaving the ISR, and this may cause the data in + the FIFO to be overwritten. Also the DIR bit has to be changed before the + RXSETUP bit is cleared (as per the SAM7 manual). */ + ulTemp = pxMessage->ulCSR0; + + /* Are there any bytes in the FIFO? */ + ulRxBytes = ulTemp >> 16; + ulRxBytes &= usbRX_COUNT_MASK; + + /* With this minimal implementation we are only interested in receiving + setup bytes on the control end point. */ + if( ( ulRxBytes > 0 ) && ( ulTemp & AT91C_UDP_RXSETUP ) ) + { + /* Take off 1 for a zero based index. */ + while( ulRxBytes > 0 ) + { + ulRxBytes--; + pxMessage->ucFifoData[ ulRxBytes ] = AT91C_BASE_UDP->UDP_FDR[ usbEND_POINT_0 ]; + } + + /* The direction must be changed first. */ + usbCSR_SET_BIT( &ulTemp, ( AT91C_UDP_DIR ) ); + AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulTemp; + } + + /* Must write zero's to TXCOMP, STALLSENT, RXSETUP, and the RX DATA + registers to clear the interrupts in the CSR register. */ + usbCSR_CLEAR_BIT( &ulTemp, usbINT_CLEAR_MASK ); + AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulTemp; + + /* Also clear the interrupts in the CSR1 register. */ + ulTemp = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ]; + usbCSR_CLEAR_BIT( &ulTemp, usbINT_CLEAR_MASK ); + AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] = ulTemp; + + /* The message now contains the entire state and optional data from + the USB interrupt. This can now be posted on the Rx queue ready for + processing at the task level. */ + xTaskWokenByPost = xQueueSendFromISR( xUSBInterruptQueue, &pxMessage, xTaskWokenByPost ); + + /* We may want to switch to the USB task, if this message has made + it the highest priority task that is ready to execute. */ + if( xTaskWokenByPost ) + { + portYIELD_FROM_ISR(); + } + + /* Clear the AIC ready for the next interrupt. */ + AT91C_BASE_AIC->AIC_EOICR = 0; +} +/*-----------------------------------------------------------*/ + +void vUSB_ISR_Wrapper( void ) +{ + /* Save the context of the interrupted task. */ + portSAVE_CONTEXT(); + + /* Call the handler itself. This must be a separate function as it uses + the stack. */ + vUSB_ISR_Handler(); + + /* Restore the context of the task that is going to + execute next. This might not be the same as the originally + interrupted task.*/ + portRESTORE_CONTEXT(); +} diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/atmel-rom.ld b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/atmel-rom.ld new file mode 100644 index 000000000..db22b4acd --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/atmel-rom.ld @@ -0,0 +1,49 @@ +MEMORY +{ + flash : ORIGIN = 0x00100000, LENGTH = 256K + ram : ORIGIN = 0x00200000, LENGTH = 64K +} + +__stack_end__ = 0x00200000 + 64K - 4; + +SECTIONS +{ + . = 0; + startup : { *(.startup)} >flash + + prog : + { + *(.text) + *(.rodata) + *(.rodata*) + *(.glue_7) + *(.glue_7t) + } >flash + + __end_of_text__ = .; + + .data : + { + __data_beg__ = .; + __data_beg_src__ = __end_of_text__; + *(.data) + __data_end__ = .; + } >ram AT>flash + + .bss : + { + __bss_beg__ = .; + *(.bss) + } >ram + + /* Align here to ensure that the .bss section occupies space up to + _end. Align after .bss to ensure correct alignment even if the + .bss section disappears because there are no input sections. */ + . = ALIGN(32 / 8); +} + . = ALIGN(32 / 8); + _end = .; + _bss_end__ = . ; __bss_end__ = . ; __end__ = . ; + PROVIDE (end = .); + + diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/boot.s b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/boot.s new file mode 100644 index 000000000..1d4dfdf0e --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/boot.s @@ -0,0 +1,162 @@ + /* Sample initialization file */ + + .extern main + .extern exit + .extern AT91F_LowLevelInit + .extern vPortYieldProcessor + + .text + .code 32 + + + .align 0 + + .extern __stack_end__ + .extern __bss_beg__ + .extern __bss_end__ + .extern __data_beg__ + .extern __data_end__ + .extern __data+beg_src__ + + .global start + .global endless_loop + + /* Stack Sizes */ + .set UND_STACK_SIZE, 0x00000004 + .set ABT_STACK_SIZE, 0x00000004 + .set FIQ_STACK_SIZE, 0x00000004 + .set IRQ_STACK_SIZE, 0X00000400 + .set SVC_STACK_SIZE, 0x00000400 + + /* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */ + .set MODE_USR, 0x10 /* User Mode */ + .set MODE_FIQ, 0x11 /* FIQ Mode */ + .set MODE_IRQ, 0x12 /* IRQ Mode */ + .set MODE_SVC, 0x13 /* Supervisor Mode */ + .set MODE_ABT, 0x17 /* Abort Mode */ + .set MODE_UND, 0x1B /* Undefined Mode */ + .set MODE_SYS, 0x1F /* System Mode */ + + .equ I_BIT, 0x80 /* when I bit is set, IRQ is disabled */ + .equ F_BIT, 0x40 /* when F bit is set, FIQ is disabled */ + + +start: +_start: +_mainCRTStartup: + + /* Setup a stack for each mode - note that this only sets up a usable stack + for system/user, SWI and IRQ modes. Also each mode is setup with + interrupts initially disabled. */ + ldr r0, .LC6 + msr CPSR_c, #MODE_UND|I_BIT|F_BIT /* Undefined Instruction Mode */ + mov sp, r0 + sub r0, r0, #UND_STACK_SIZE + msr CPSR_c, #MODE_ABT|I_BIT|F_BIT /* Abort Mode */ + mov sp, r0 + sub r0, r0, #ABT_STACK_SIZE + msr CPSR_c, #MODE_FIQ|I_BIT|F_BIT /* FIQ Mode */ + mov sp, r0 + sub r0, r0, #FIQ_STACK_SIZE + msr CPSR_c, #MODE_IRQ|I_BIT|F_BIT /* IRQ Mode */ + mov sp, r0 + sub r0, r0, #IRQ_STACK_SIZE + msr CPSR_c, #MODE_SVC|I_BIT|F_BIT /* Supervisor Mode */ + mov sp, r0 + sub r0, r0, #SVC_STACK_SIZE + msr CPSR_c, #MODE_SYS|I_BIT|F_BIT /* System Mode */ + mov sp, r0 + + /* We want to start in supervisor mode. Operation will switch to system + mode when the first task starts. */ + msr CPSR_c, #MODE_SVC|I_BIT|F_BIT + + bl AT91F_LowLevelInit + + /* Clear BSS. */ + + mov a2, #0 /* Fill value */ + mov fp, a2 /* Null frame pointer */ + mov r7, a2 /* Null frame pointer for Thumb */ + + ldr r1, .LC1 /* Start of memory block */ + ldr r3, .LC2 /* End of memory block */ + subs r3, r3, r1 /* Length of block */ + beq .end_clear_loop + mov r2, #0 + +.clear_loop: + strb r2, [r1], #1 + subs r3, r3, #1 + bgt .clear_loop + +.end_clear_loop: + + /* Initialise data. */ + + ldr r1, .LC3 /* Start of memory block */ + ldr r2, .LC4 /* End of memory block */ + ldr r3, .LC5 + subs r3, r3, r1 /* Length of block */ + beq .end_set_loop + +.set_loop: + ldrb r4, [r2], #1 + strb r4, [r1], #1 + subs r3, r3, #1 + bgt .set_loop + +.end_set_loop: + + mov r0, #0 /* no arguments */ + mov r1, #0 /* no argv either */ + + ldr lr, =main + bx lr + +endless_loop: + b endless_loop + + + .align 0 + + .LC1: + .word __bss_beg__ + .LC2: + .word __bss_end__ + .LC3: + .word __data_beg__ + .LC4: + .word __data_beg_src__ + .LC5: + .word __data_end__ + .LC6: + .word __stack_end__ + + + /* Setup vector table. Note that undf, pabt, dabt, fiq just execute + a null loop. */ + +.section .startup,"ax" + .code 32 + .align 0 + + b _start /* reset - _start */ + ldr pc, _undf /* undefined - _undf */ + ldr pc, _swi /* SWI - _swi */ + ldr pc, _pabt /* program abort - _pabt */ + ldr pc, _dabt /* data abort - _dabt */ + nop /* reserved */ + ldr pc, [pc,#-0xF20] /* IRQ - read the AIC */ + ldr pc, _fiq /* FIQ - _fiq */ + +_undf: .word __undf /* undefined */ +_swi: .word vPortYieldProcessor /* SWI */ +_pabt: .word __pabt /* program abort */ +_dabt: .word __dabt /* data abort */ +_fiq: .word __fiq /* FIQ */ + +__undf: b . /* undefined */ +__pabt: b . /* program abort */ +__dabt: b . /* data abort */ +__fiq: b . /* FIQ */ diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/main.c b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/main.c new file mode 100644 index 000000000..c06345830 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/main.c @@ -0,0 +1,242 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + NOTE : Tasks run in System mode and the scheduler runs in Supervisor mode. + The processor MUST be in supervisor mode when vTaskStartScheduler is + called. The demo applications included in the FreeRTOS.org download switch + to supervisor mode prior to main being called. If you are not using one of + these demo application projects then ensure Supervisor mode is used. +*/ + +/* + * This demo includes a (basic) USB mouse driver and a WEB server. It is + * targeted for the AT91SAM7X EK prototyping board which includes a small + * joystick to provide the mouse inputs. The WEB interface provides some basic + * interactivity through the use of a check box to turn on and off an LED. + * + * main() creates the WEB server, USB, and a set of the standard demo tasks + * before starting the scheduler. See the online FreeRTOS.org documentation + * for more information on the standard demo tasks. + * + * LEDs D1 to D3 are controlled by the standard 'flash' tasks - each will + * toggle at a different fixed frequency. + * + * A tick hook function is used to monitor the standard demo tasks - with LED + * D4 being used to indicate the system status. D4 toggling every 5 seconds + * indicates that all the standard demo tasks are executing without error. The + * toggle rate increasing to 500ms is indicative of an error having been found + * in at least one demo task. + * + * See the online documentation page that accompanies this demo for full setup + * and usage information. + */ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo application includes. */ +#include "partest.h" +#include "USBSample.h" +#include "uip_task.h" +#include "BlockQ.h" +#include "blocktim.h" +#include "flash.h" +#include "QPeek.h" +#include "dynamic.h" + +/* Priorities for the demo application tasks. */ +#define mainUIP_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainUSB_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainFLASH_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY ) + +/* The task allocated to the uIP task is large to account for its use of the +sprintf() library function. Use of a cut down printf() library would allow +the stack usage to be greatly reduced. */ +#define mainUIP_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE * 6 ) + +/* The LED toggle by the tick hook should an error have been found in a task. */ +#define mainERROR_LED ( 3 ) + +/*-----------------------------------------------------------*/ + +/* + * Configure the processor for use with the Atmel demo board. Setup is minimal + * as the low level init function (called from the startup asm file) takes care + * of most things. + */ +static void prvSetupHardware( void ); + +/*-----------------------------------------------------------*/ + +/* + * Starts all the other tasks, then starts the scheduler. + */ +int main( void ) +{ + /* Setup any hardware that has not already been configured by the low + level init routines. */ + prvSetupHardware(); + + /* Start the task that handles the TCP/IP and WEB server functionality. */ + xTaskCreate( vuIP_Task, "uIP", mainUIP_TASK_STACK_SIZE, NULL, mainUIP_PRIORITY, NULL ); + + /* Also start the USB demo which is just for the SAM7. */ + vStartUSBTask( mainUSB_PRIORITY ); + + /* Start the standard demo tasks. */ + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vCreateBlockTimeTasks(); + vStartLEDFlashTasks( mainFLASH_PRIORITY ); + vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY ); + vStartQueuePeekTasks(); + vStartDynamicPriorityTasks(); + + /* Start the scheduler. + + NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. + The processor MUST be in supervisor mode when vTaskStartScheduler is + called. The demo applications included in the FreeRTOS.org download switch + to supervisor mode prior to main being called. If you are not using one of + these demo application projects then ensure Supervisor mode is used here. */ + + vTaskStartScheduler(); + + /* We should never get here as control is now taken by the scheduler. */ + return 0; +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + portDISABLE_INTERRUPTS(); + + /* When using the JTAG debugger the hardware is not always initialised to + the correct default state. This line just ensures that this does not + cause all interrupts to be masked at the start. */ + AT91C_BASE_AIC->AIC_EOICR = 0; + + /* Most setup is performed by the low level init function called from the + startup asm file. */ + + /* Enable the peripheral clock. */ + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOA; + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOB; + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_EMAC; + + /* Initialise the LED outputs for use by the demo application tasks. */ + vParTestInitialise(); +} +/*-----------------------------------------------------------*/ + +void vApplicationTickHook( void ) +{ +static unsigned portLONG ulCallCount = 0, ulErrorFound = pdFALSE; + +/* The rate at which LED D4 will toggle if an error has been found in one or +more of the standard demo tasks. */ +const unsigned portLONG ulErrorFlashRate = 500 / portTICK_RATE_MS; + +/* The rate at which LED D4 will toggle if no errors have been found in any +of the standard demo tasks. */ +const unsigned portLONG ulNoErrorCheckRate = 5000 / portTICK_RATE_MS; + + ulCallCount++; + + if( ulErrorFound != pdFALSE ) + { + /* We have already found an error, so flash the LED with the appropriate + frequency. */ + if( ulCallCount > ulErrorFlashRate ) + { + ulCallCount = 0; + vParTestToggleLED( mainERROR_LED ); + } + } + else + { + if( ulCallCount > ulNoErrorCheckRate ) + { + ulCallCount = 0; + + /* We have not yet found an error. Check all the demo tasks to ensure + this is still the case. */ + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + ulErrorFound |= 0x01; + } + + if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 0x02; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 0x04; + } + + if( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 0x08; + } + + if( xAreQueuePeekTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 0x10; + } + + vParTestToggleLED( mainERROR_LED ); + } + } +} + + + + diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/EMAC_ISR.c b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/EMAC_ISR.c new file mode 100644 index 000000000..a4b2e8daf --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/EMAC_ISR.c @@ -0,0 +1,107 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#include "FreeRTOS.h" +#include "Semphr.h" +#include "Task.h" + +/* Wrapper for the EMAC interrupt. */ +void vEMACISR_Wrapper( void ) __attribute__((naked)); + +/* Handler called by the ISR wrapper. This must be kept a separate +function to ensure the stack frame is correctly set up. */ +void vEMACISR_Handler( void ); + +static xSemaphoreHandle xEMACSemaphore; + +/*-----------------------------------------------------------*/ + +void vPassEMACSemaphore( xSemaphoreHandle xSemaphore ) +{ + xEMACSemaphore = xSemaphore; +} +/*-----------------------------------------------------------*/ + +void vEMACISR_Handler( void ) +{ +volatile unsigned portLONG ulIntStatus, ulRxStatus; +portBASE_TYPE xSwitchRequired = pdFALSE; + + ulIntStatus = AT91C_BASE_EMAC->EMAC_ISR; + ulRxStatus = AT91C_BASE_EMAC->EMAC_RSR; + + if( ( ulIntStatus & AT91C_EMAC_RCOMP ) || ( ulRxStatus & AT91C_EMAC_REC ) ) + { + /* A frame has been received, signal the uIP task so it can process + the Rx descriptors. */ + xSwitchRequired = xSemaphoreGiveFromISR( xEMACSemaphore, pdFALSE ); + AT91C_BASE_EMAC->EMAC_RSR = AT91C_EMAC_REC; + } + + /* Clear the interrupt. */ + AT91C_BASE_AIC->AIC_EOICR = 0; + + /* Switch to the uIP task. */ + if( xSwitchRequired ) + { + /* If a task of higher priority than the interrupted task was + unblocked by the ISR then this call will ensure that the + unblocked task is the task the ISR returns to. */ + portYIELD_FROM_ISR(); + } +} +/*-----------------------------------------------------------*/ + +void vEMACISR_Wrapper( void ) +{ + /* Save the context of the interrupted task. */ + portSAVE_CONTEXT(); + + /* Call the handler task to do the actual work. This must be a separate + function to ensure the stack frame is correctly set up. */ + vEMACISR_Handler(); + + /* Restore the context of whichever task is the next to run. */ + portRESTORE_CONTEXT(); +} + + diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/Makefile.webserver b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/Makefile.webserver new file mode 100644 index 000000000..f38c47a72 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/Makefile.webserver @@ -0,0 +1 @@ +APP_SOURCES += httpd.c http-strings.c httpd-fs.c httpd-cgi.c diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/SAM7_EMAC.c b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/SAM7_EMAC.c new file mode 100644 index 000000000..9dc87359d --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/SAM7_EMAC.c @@ -0,0 +1,680 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "semphr.h" +#include "task.h" + +/* Demo application includes. */ +#include "SAM7_EMAC.h" + +/* uIP includes. */ +#include "uip.h" + +/* Hardware specific includes. */ +#include "Emac.h" +#include "mii.h" +#include "AT91SAM7X256.h" + + +/* USE_RMII_INTERFACE must be defined as 1 to use an RMII interface, or 0 +to use an MII interface. */ +#define USE_RMII_INTERFACE 0 + +/* The buffer addresses written into the descriptors must be aligned so the +last few bits are zero. These bits have special meaning for the EMAC +peripheral and cannot be used as part of the address. */ +#define emacADDRESS_MASK ( ( unsigned portLONG ) 0xFFFFFFFC ) + +/* Bit used within the address stored in the descriptor to mark the last +descriptor in the array. */ +#define emacRX_WRAP_BIT ( ( unsigned portLONG ) 0x02 ) + +/* Bit used within the Tx descriptor status to indicate whether the +descriptor is under the control of the EMAC or the software. */ +#define emacTX_BUF_USED ( ( unsigned portLONG ) 0x80000000 ) + +/* A short delay is used to wait for a buffer to become available, should +one not be immediately available when trying to transmit a frame. */ +#define emacBUFFER_WAIT_DELAY ( 2 ) +#define emacMAX_WAIT_CYCLES ( configTICK_RATE_HZ / 40 ) + +/* Misc defines. */ +#define emacINTERRUPT_LEVEL ( 5 ) +#define emacNO_DELAY ( 0 ) +#define emacTOTAL_FRAME_HEADER_SIZE ( 54 ) +#define emacPHY_INIT_DELAY ( 5000 / portTICK_RATE_MS ) +#define emacRESET_KEY ( ( unsigned portLONG ) 0xA5000000 ) +#define emacRESET_LENGTH ( ( unsigned portLONG ) ( 0x01 << 8 ) ) + +/* The Atmel header file only defines the TX frame length mask. */ +#define emacRX_LENGTH_FRAME ( 0xfff ) + +/* Peripheral setup for the EMAC. */ +#define emacPERIPHERAL_A_SETUP ( ( unsigned portLONG ) AT91C_PB2_ETX0 ) | \ + ( ( unsigned portLONG ) AT91C_PB12_ETXER ) | \ + ( ( unsigned portLONG ) AT91C_PB16_ECOL ) | \ + ( ( unsigned portLONG ) AT91C_PB11_ETX3 ) | \ + ( ( unsigned portLONG ) AT91C_PB6_ERX1 ) | \ + ( ( unsigned portLONG ) AT91C_PB15_ERXDV ) | \ + ( ( unsigned portLONG ) AT91C_PB13_ERX2 ) | \ + ( ( unsigned portLONG ) AT91C_PB3_ETX1 ) | \ + ( ( unsigned portLONG ) AT91C_PB8_EMDC ) | \ + ( ( unsigned portLONG ) AT91C_PB5_ERX0 ) | \ + ( ( unsigned portLONG ) AT91C_PB14_ERX3 ) | \ + ( ( unsigned portLONG ) AT91C_PB4_ECRS_ECRSDV ) | \ + ( ( unsigned portLONG ) AT91C_PB1_ETXEN ) | \ + ( ( unsigned portLONG ) AT91C_PB10_ETX2 ) | \ + ( ( unsigned portLONG ) AT91C_PB0_ETXCK_EREFCK ) | \ + ( ( unsigned portLONG ) AT91C_PB9_EMDIO ) | \ + ( ( unsigned portLONG ) AT91C_PB7_ERXER ) | \ + ( ( unsigned portLONG ) AT91C_PB17_ERXCK ); + +/*-----------------------------------------------------------*/ + +/* + * Prototype for the EMAC interrupt function - called by the asm wrapper. + */ +extern void vEMACISR_Wrapper( void ) __attribute__((naked)); + +/* + * Initialise both the Tx and Rx descriptors used by the EMAC. + */ +static void prvSetupDescriptors(void); + +/* + * Write our MAC address into the EMAC. The MAC address is set as one of the + * uip options. + */ +static void prvSetupMACAddress( void ); + +/* + * Configure the EMAC and AIC for EMAC interrupts. + */ +static void prvSetupEMACInterrupt( void ); + +/* + * Some initialisation functions taken from the Atmel EMAC sample code. + */ +static void vReadPHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG *pulValue ); +#if USE_RMII_INTERFACE != 1 + static void vWritePHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG ulValue); +#endif +static portBASE_TYPE xGetLinkSpeed( void ); +static portBASE_TYPE prvProbePHY( void ); + +/*-----------------------------------------------------------*/ + +/* Buffer written to by the EMAC DMA. Must be aligned as described by the +comment above the emacADDRESS_MASK definition. */ +#pragma data_alignment=8 +static volatile portCHAR pcRxBuffer[ NB_RX_BUFFERS * ETH_RX_BUFFER_SIZE ]; + +/* Buffer read by the EMAC DMA. Must be aligned as described by he comment +above the emacADDRESS_MASK definition. */ +#pragma data_alignment=8 +static portCHAR pcTxBuffer[ NB_TX_BUFFERS * ETH_TX_BUFFER_SIZE ]; + +/* Descriptors used to communicate between the program and the EMAC peripheral. +These descriptors hold the locations and state of the Rx and Tx buffers. */ +static volatile AT91S_TxTdDescriptor xTxDescriptors[ NB_TX_BUFFERS ]; +static volatile AT91S_RxTdDescriptor xRxDescriptors[ NB_RX_BUFFERS ]; + +/* The IP and Ethernet addresses are read from the uIP setup. */ +const portCHAR cMACAddress[ 6 ] = { uipMAC_ADDR0, uipMAC_ADDR1, uipMAC_ADDR2, uipMAC_ADDR3, uipMAC_ADDR4, uipMAC_ADDR5 }; +const unsigned char ucIPAddress[ 4 ] = { uipIP_ADDR0, uipIP_ADDR1, uipIP_ADDR2, uipIP_ADDR3 }; + +/* The semaphore used by the EMAC ISR to wake the EMAC task. */ +static xSemaphoreHandle xSemaphore = NULL; + +/*-----------------------------------------------------------*/ + +xSemaphoreHandle xEMACInit( void ) +{ + /* Code supplied by Atmel -------------------------------*/ + + /* Disable pull up on RXDV => PHY normal mode (not in test mode), + PHY has internal pull down. */ + AT91C_BASE_PIOB->PIO_PPUDR = 1 << 15; + + #if USE_RMII_INTERFACE != 1 + /* PHY has internal pull down : set MII mode. */ + AT91C_BASE_PIOB->PIO_PPUDR = 1 << 16; + #endif + + /* Clear PB18 <=> PHY powerdown. */ + AT91C_BASE_PIOB->PIO_PER = 1 << 18; + AT91C_BASE_PIOB->PIO_OER = 1 << 18; + AT91C_BASE_PIOB->PIO_CODR = 1 << 18; + + /* After PHY power up, hardware reset. */ + AT91C_BASE_RSTC->RSTC_RMR = emacRESET_KEY | emacRESET_LENGTH; + AT91C_BASE_RSTC->RSTC_RCR = emacRESET_KEY | AT91C_RSTC_EXTRST; + + /* Wait for hardware reset end. */ + while( !( AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL ) ) + { + __asm volatile ( "NOP" ); + } + __asm volatile ( "NOP" ); + + /* Setup the pins. */ + AT91C_BASE_PIOB->PIO_ASR = emacPERIPHERAL_A_SETUP; + AT91C_BASE_PIOB->PIO_PDR = emacPERIPHERAL_A_SETUP; + + /* Enable com between EMAC PHY. + + Enable management port. */ + AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE; + + /* MDC = MCK/32. */ + AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10; + + /* Wait for PHY auto init end (rather crude delay!). */ + vTaskDelay( emacPHY_INIT_DELAY ); + + /* PHY configuration. */ + #if USE_RMII_INTERFACE != 1 + { + unsigned portLONG ulControl; + + /* PHY has internal pull down : disable MII isolate. */ + vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl ); + vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl ); + ulControl &= ~BMCR_ISOLATE; + vWritePHY( AT91C_PHY_ADDR, MII_BMCR, ulControl ); + } + #endif + + /* Disable management port again. */ + AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE; + + #if USE_RMII_INTERFACE != 1 + /* Enable EMAC in MII mode, enable clock ERXCK and ETXCK. */ + AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_CLKEN ; + #else + /* Enable EMAC in RMII mode, enable RMII clock (50MHz from oscillator + on ERFCK). */ + AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_RMII | AT91C_EMAC_CLKEN ; + #endif + + /* End of code supplied by Atmel ------------------------*/ + + /* Setup the buffers and descriptors. */ + prvSetupDescriptors(); + + /* Load our MAC address into the EMAC. */ + prvSetupMACAddress(); + + /* Are we connected? */ + if( prvProbePHY() ) + { + /* Enable the interrupt! */ + portENTER_CRITICAL(); + { + prvSetupEMACInterrupt(); + vPassEMACSemaphore( xSemaphore ); + } + portEXIT_CRITICAL(); + } + + return xSemaphore; +} +/*-----------------------------------------------------------*/ + +portLONG lEMACSend( void ) +{ +static unsigned portBASE_TYPE uxTxBufferIndex = 0; +portBASE_TYPE xWaitCycles = 0; +portLONG lReturn = pdPASS; +portCHAR *pcBuffer; + + /* Is a buffer available? */ + while( !( xTxDescriptors[ uxTxBufferIndex ].U_Status.status & AT91C_TRANSMIT_OK ) ) + { + /* There is no room to write the Tx data to the Tx buffer. Wait a + short while, then try again. */ + xWaitCycles++; + if( xWaitCycles > emacMAX_WAIT_CYCLES ) + { + /* Give up. */ + lReturn = pdFAIL; + break; + } + else + { + vTaskDelay( emacBUFFER_WAIT_DELAY ); + } + } + + /* lReturn will only be pdPASS if a buffer is available. */ + if( lReturn == pdPASS ) + { + /* Copy the headers into the Tx buffer. These will be in the uIP buffer. */ + pcBuffer = ( portCHAR * ) xTxDescriptors[ uxTxBufferIndex ].addr; + memcpy( ( void * ) pcBuffer, ( void * ) uip_buf, emacTOTAL_FRAME_HEADER_SIZE ); + + /* If there is room, also copy in the application data if any. */ + if( ( uip_len > emacTOTAL_FRAME_HEADER_SIZE ) && ( uip_len <= ( ETH_TX_BUFFER_SIZE - emacTOTAL_FRAME_HEADER_SIZE ) ) ) + { + memcpy( ( void * ) &( pcBuffer[ emacTOTAL_FRAME_HEADER_SIZE ] ), ( void * ) uip_appdata, ( uip_len - emacTOTAL_FRAME_HEADER_SIZE ) ); + } + + /* Send. */ + portENTER_CRITICAL(); + { + if( uxTxBufferIndex >= ( NB_TX_BUFFERS - 1 ) ) + { + /* Fill out the necessary in the descriptor to get the data sent. */ + xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( uip_len & ( unsigned portLONG ) AT91C_LENGTH_FRAME ) + | AT91C_LAST_BUFFER + | AT91C_TRANSMIT_WRAP; + uxTxBufferIndex = 0; + } + else + { + /* Fill out the necessary in the descriptor to get the data sent. */ + xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( uip_len & ( unsigned portLONG ) AT91C_LENGTH_FRAME ) + | AT91C_LAST_BUFFER; + uxTxBufferIndex++; + } + + AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TSTART; + } + portEXIT_CRITICAL(); + } + + return lReturn; +} +/*-----------------------------------------------------------*/ + +unsigned portLONG ulEMACPoll( void ) +{ +static unsigned portBASE_TYPE ulNextRxBuffer = 0; +unsigned portLONG ulSectionLength = 0, ulLengthSoFar = 0, ulEOF = pdFALSE; +portCHAR *pcSource; + + /* Skip any fragments. */ + while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AT91C_OWNERSHIP_BIT ) && !( xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AT91C_SOF ) ) + { + /* Mark the buffer as free again. */ + xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT ); + ulNextRxBuffer++; + if( ulNextRxBuffer >= NB_RX_BUFFERS ) + { + ulNextRxBuffer = 0; + } + } + + /* Is there a packet ready? */ + + while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AT91C_OWNERSHIP_BIT ) && !ulSectionLength ) + { + pcSource = ( portCHAR * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK ); + ulSectionLength = xRxDescriptors[ ulNextRxBuffer ].U_Status.status & emacRX_LENGTH_FRAME; + + if( ulSectionLength == 0 ) + { + /* The frame is longer than the buffer pointed to by this + descriptor so copy the entire buffer to uIP - then move onto + the next descriptor to get the rest of the frame. */ + if( ( ulLengthSoFar + ETH_RX_BUFFER_SIZE ) <= UIP_BUFSIZE ) + { + memcpy( &( uip_buf[ ulLengthSoFar ] ), pcSource, ETH_RX_BUFFER_SIZE ); + ulLengthSoFar += ETH_RX_BUFFER_SIZE; + } + } + else + { + /* This is the last section of the frame. Copy the section to + uIP. */ + if( ulSectionLength < UIP_BUFSIZE ) + { + /* The section length holds the length of the entire frame. + ulLengthSoFar holds the length of the frame sections already + copied to uIP, so the length of the final section is + ulSectionLength - ulLengthSoFar; */ + if( ulSectionLength > ulLengthSoFar ) + { + memcpy( &( uip_buf[ ulLengthSoFar ] ), pcSource, ( ulSectionLength - ulLengthSoFar ) ); + } + } + + /* Is this the last buffer for the frame? If not why? */ + ulEOF = xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AT91C_EOF; + } + + /* Mark the buffer as free again. */ + xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT ); + + /* Increment to the next buffer, wrapping if necessary. */ + ulNextRxBuffer++; + if( ulNextRxBuffer >= NB_RX_BUFFERS ) + { + ulNextRxBuffer = 0; + } + } + + /* If we obtained data but for some reason did not find the end of the + frame then discard the data as it must contain an error. */ + if( !ulEOF ) + { + ulSectionLength = 0; + } + + return ulSectionLength; +} +/*-----------------------------------------------------------*/ + +static void prvSetupDescriptors(void) +{ +unsigned portBASE_TYPE xIndex; +unsigned portLONG ulAddress; + + /* Initialise xRxDescriptors descriptor. */ + for( xIndex = 0; xIndex < NB_RX_BUFFERS; ++xIndex ) + { + /* Calculate the address of the nth buffer within the array. */ + ulAddress = ( unsigned portLONG )( pcRxBuffer + ( xIndex * ETH_RX_BUFFER_SIZE ) ); + + /* Write the buffer address into the descriptor. The DMA will place + the data at this address when this descriptor is being used. Mask off + the bottom bits of the address as these have special meaning. */ + xRxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK; + } + + /* The last buffer has the wrap bit set so the EMAC knows to wrap back + to the first buffer. */ + xRxDescriptors[ NB_RX_BUFFERS - 1 ].addr |= emacRX_WRAP_BIT; + + /* Initialise xTxDescriptors. */ + for( xIndex = 0; xIndex < NB_TX_BUFFERS; ++xIndex ) + { + /* Calculate the address of the nth buffer within the array. */ + ulAddress = ( unsigned portLONG )( pcTxBuffer + ( xIndex * ETH_TX_BUFFER_SIZE ) ); + + /* Write the buffer address into the descriptor. The DMA will read + data from here when the descriptor is being used. */ + xTxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK; + xTxDescriptors[ xIndex ].U_Status.status = AT91C_TRANSMIT_OK; + } + + /* The last buffer has the wrap bit set so the EMAC knows to wrap back + to the first buffer. */ + xTxDescriptors[ NB_TX_BUFFERS - 1 ].U_Status.status = AT91C_TRANSMIT_WRAP | AT91C_TRANSMIT_OK; + + /* Tell the EMAC where to find the descriptors. */ + AT91C_BASE_EMAC->EMAC_RBQP = ( unsigned portLONG ) xRxDescriptors; + AT91C_BASE_EMAC->EMAC_TBQP = ( unsigned portLONG ) xTxDescriptors; + + /* Clear all the bits in the receive status register. */ + AT91C_BASE_EMAC->EMAC_RSR = ( AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA ); + + /* Enable the copy of data into the buffers, ignore broadcasts, + and don't copy FCS. */ + AT91C_BASE_EMAC->EMAC_NCFGR |= ( AT91C_EMAC_CAF | AT91C_EMAC_NBC | AT91C_EMAC_DRFCS); + + /* Enable Rx and Tx, plus the stats register. */ + AT91C_BASE_EMAC->EMAC_NCR |= ( AT91C_EMAC_TE | AT91C_EMAC_RE | AT91C_EMAC_WESTAT ); +} +/*-----------------------------------------------------------*/ + +static void prvSetupMACAddress( void ) +{ + /* Must be written SA1L then SA1H. */ + AT91C_BASE_EMAC->EMAC_SA1L = ( ( unsigned portLONG ) cMACAddress[ 3 ] << 24 ) | + ( ( unsigned portLONG ) cMACAddress[ 2 ] << 16 ) | + ( ( unsigned portLONG ) cMACAddress[ 1 ] << 8 ) | + cMACAddress[ 0 ]; + + AT91C_BASE_EMAC->EMAC_SA1H = ( ( unsigned portLONG ) cMACAddress[ 5 ] << 8 ) | + cMACAddress[ 4 ]; +} +/*-----------------------------------------------------------*/ + +static void prvSetupEMACInterrupt( void ) +{ + /* Create the semaphore used to trigger the EMAC task. */ + vSemaphoreCreateBinary( xSemaphore ); + if( xSemaphore ) + { + /* We start by 'taking' the semaphore so the ISR can 'give' it when the + first interrupt occurs. */ + xSemaphoreTake( xSemaphore, emacNO_DELAY ); + portENTER_CRITICAL(); + { + /* We want to interrupt on Rx events. */ + AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RCOMP; + + /* Enable the interrupts in the AIC. */ + AT91F_AIC_ConfigureIt( AT91C_ID_EMAC, emacINTERRUPT_LEVEL, AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, ( void (*)( void ) ) vEMACISR_Wrapper ); + AT91C_BASE_AIC->AIC_IECR = 0x1 << AT91C_ID_EMAC; + } + portEXIT_CRITICAL(); + } +} +/*-----------------------------------------------------------*/ + + + + +/* + * The following functions are initialisation functions taken from the Atmel + * EMAC sample code. + */ + +static portBASE_TYPE prvProbePHY( void ) +{ +unsigned portLONG ulPHYId1, ulPHYId2, ulStatus; +portBASE_TYPE xReturn = pdPASS; + + /* Code supplied by Atmel (reformatted) -----------------*/ + + /* Enable management port */ + AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE; + AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10; + + /* Read the PHY ID. */ + vReadPHY( AT91C_PHY_ADDR, MII_PHYSID1, &ulPHYId1 ); + vReadPHY( AT91C_PHY_ADDR, MII_PHYSID2, &ulPHYId2 ); + + /* AMD AM79C875: + PHY_ID1 = 0x0022 + PHY_ID2 = 0x5541 + Bits 3:0 Revision Number Four bit manufacturer’s revision number. + 0001 stands for Rev. A, etc. + */ + if( ( ( ulPHYId1 << 16 ) | ( ulPHYId2 & 0xfff0 ) ) != MII_DM9161_ID ) + { + /* Did not expect this ID. */ + xReturn = pdFAIL; + } + else + { + ulStatus = xGetLinkSpeed(); + + if( ulStatus != pdPASS ) + { + xReturn = pdFAIL; + } + } + + /* Disable management port */ + AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE; + + /* End of code supplied by Atmel ------------------------*/ + + return xReturn; +} +/*-----------------------------------------------------------*/ + +static void vReadPHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG *pulValue ) +{ + /* Code supplied by Atmel (reformatted) ----------------------*/ + + AT91C_BASE_EMAC->EMAC_MAN = (AT91C_EMAC_SOF & (0x01<<30)) + | (2 << 16) | (2 << 28) + | ((ucPHYAddress & 0x1f) << 23) + | (ucAddress << 18); + + /* Wait until IDLE bit in Network Status register is cleared. */ + while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) ) + { + __asm( "NOP" ); + } + + *pulValue = ( AT91C_BASE_EMAC->EMAC_MAN & 0x0000ffff ); + + /* End of code supplied by Atmel ------------------------*/ +} +/*-----------------------------------------------------------*/ + +#if USE_RMII_INTERFACE != 1 +static void vWritePHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG ulValue ) +{ + /* Code supplied by Atmel (reformatted) ----------------------*/ + + AT91C_BASE_EMAC->EMAC_MAN = (( AT91C_EMAC_SOF & (0x01<<30)) + | (2 << 16) | (1 << 28) + | ((ucPHYAddress & 0x1f) << 23) + | (ucAddress << 18)) + | (ulValue & 0xffff); + + /* Wait until IDLE bit in Network Status register is cleared */ + while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) ) + { + __asm( "NOP" ); + }; + + /* End of code supplied by Atmel ------------------------*/ +} +#endif +/*-----------------------------------------------------------*/ + +static portBASE_TYPE xGetLinkSpeed( void ) +{ + unsigned portLONG ulBMSR, ulBMCR, ulLPA, ulMACCfg, ulSpeed, ulDuplex; + + /* Code supplied by Atmel (reformatted) -----------------*/ + + /* Link status is latched, so read twice to get current value */ + vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR); + vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR); + + if( !( ulBMSR & BMSR_LSTATUS ) ) + { + /* No Link. */ + return pdFAIL; + } + + vReadPHY(AT91C_PHY_ADDR, MII_BMCR, &ulBMCR); + if (ulBMCR & BMCR_ANENABLE) + { + /* AutoNegotiation is enabled. */ + if (!(ulBMSR & BMSR_ANEGCOMPLETE)) + { + /* Auto-negotiation in progress. */ + return pdFAIL; + } + + vReadPHY(AT91C_PHY_ADDR, MII_LPA, &ulLPA); + if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_100HALF ) ) + { + ulSpeed = SPEED_100; + } + else + { + ulSpeed = SPEED_10; + } + + if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_10FULL ) ) + { + ulDuplex = DUPLEX_FULL; + } + else + { + ulDuplex = DUPLEX_HALF; + } + } + else + { + ulSpeed = ( ulBMCR & BMCR_SPEED100 ) ? SPEED_100 : SPEED_10; + ulDuplex = ( ulBMCR & BMCR_FULLDPLX ) ? DUPLEX_FULL : DUPLEX_HALF; + } + + /* Update the MAC */ + ulMACCfg = AT91C_BASE_EMAC->EMAC_NCFGR & ~( AT91C_EMAC_SPD | AT91C_EMAC_FD ); + if( ulSpeed == SPEED_100 ) + { + if( ulDuplex == DUPLEX_FULL ) + { + /* 100 Full Duplex */ + AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD | AT91C_EMAC_FD; + } + else + { + /* 100 Half Duplex */ + AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD; + } + } + else + { + if (ulDuplex == DUPLEX_FULL) + { + /* 10 Full Duplex */ + AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_FD; + } + else + { + /* 10 Half Duplex */ + AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg; + } + } + + /* End of code supplied by Atmel ------------------------*/ + + return pdPASS; +} diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/SAM7_EMAC.h b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/SAM7_EMAC.h new file mode 100644 index 000000000..95cee71f2 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/SAM7_EMAC.h @@ -0,0 +1,66 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef SAM_7_EMAC_H +#define SAM_7_EMAC_H + + +/* + * Initialise the EMAC driver. If successful a semaphore is returned that + * is used by the EMAC ISR to indicate that Rx packets have been received. + * If the initialisation fails then NULL is returned. + */ +xSemaphoreHandle xEMACInit( void ); + +/* + * Send the current uIP buffer. This copies the uIP buffer to one of the + * EMAC Tx buffers, then indicates to the EMAC that the buffer is ready. + */ +portLONG lEMACSend( void ); + +/* + * Called in response to an EMAC Rx interrupt. Copies the received frame + * into the uIP buffer. + */ +unsigned portLONG ulEMACPoll( void ); + +#endif diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/clock-arch.h b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/clock-arch.h new file mode 100644 index 000000000..cde657b62 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/clock-arch.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2006, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: clock-arch.h,v 1.2 2006/06/12 08:00:31 adam Exp $ + */ + +#ifndef __CLOCK_ARCH_H__ +#define __CLOCK_ARCH_H__ + +#include "FreeRTOS.h" + +typedef unsigned long clock_time_t; +#define CLOCK_CONF_SECOND configTICK_RATE_HZ + +#endif /* __CLOCK_ARCH_H__ */ diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/emac_atmel.h b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/emac_atmel.h new file mode 100644 index 000000000..7551a3648 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/emac_atmel.h @@ -0,0 +1,195 @@ +//*---------------------------------------------------------------------------- +//* ATMEL Microcontroller Software Support - ROUSSET - +//*---------------------------------------------------------------------------- +//* The software is delivered "AS IS" without warranty or condition of any +//* kind, either express, implied or statutory. This includes without +//* limitation any warranty or condition with respect to merchantability or +//* fitness for any particular purpose, or against the infringements of +//* intellectual property rights of others. +//*---------------------------------------------------------------------------- +//* File Name : Emac.h +//* Object : Emac header file +//* Creation : Hi 11/18/2002 +//* +//*---------------------------------------------------------------------------- +#ifndef AT91C_EMAC_H +#define AT91C_EMAC_H + + +//* Allows to display all IP header in the main.c +//* If not defined, only ICMP packets are displayed +#define AT91C_DISPLAY_ALL_IPHEADER 0 + +#define NB_RX_BUFFERS 25 //* Number of receive buffers +#define ETH_RX_BUFFER_SIZE 128 //* + +#define NB_TX_BUFFERS 2 //* Number of Transmit buffers +#define ETH_TX_BUFFER_SIZE UIP_BUFSIZE //* + +#define AT91C_NO_IPPACKET 0 +#define AT91C_IPPACKET 1 + +#define ARP_REQUEST 0x0001 +#define ARP_REPLY 0x0002 +#define PROT_ARP 0x0806 +#define PROT_IP 0x0800 +#define PROT_ICMP 0x01 +#define ICMP_ECHO_REQUEST 0x08 +#define ICMP_ECHO_REPLY 0x00 + +#define AT91C_EMAC_CLKEN 0x2 +#define SWAP16(x) (((x & 0xff) << 8) | (x >> 8)) + +#if 0 +//* Transfer descriptor structure +typedef struct _AT91S_TdDescriptor { + unsigned int addr; + unsigned int status; +}AT91S_TdDescriptor, *AT91PS_TdDescriptor; +#endif + +//* Receive Transfer descriptor structure +typedef struct _AT91S_RxTdDescriptor { + unsigned int addr; + union + { + unsigned int status; + struct { + unsigned int Length:11; + unsigned int Res0:1; + unsigned int Rxbuf_off:2; + unsigned int StartOfFrame:1; + unsigned int EndOfFrame:1; + unsigned int Cfi:1; + unsigned int VlanPriority:3; + unsigned int PriorityTag:1; + unsigned int VlanTag:1; + unsigned int TypeID:1; + unsigned int Sa4Match:1; + unsigned int Sa3Match:1; + unsigned int Sa2Match:1; + unsigned int Sa1Match:1; + unsigned int Res1:1; + unsigned int ExternalAdd:1; + unsigned int UniCast:1; + unsigned int MultiCast:1; + unsigned int BroadCast:1; + }S_Status; + }U_Status; +}AT91S_RxTdDescriptor, *AT91PS_RxTdDescriptor; + + +//* Transmit Transfer descriptor structure +typedef struct _AT91S_TxTdDescriptor { + unsigned int addr; + union + { + unsigned int status; + struct { + unsigned int Length:11; + unsigned int Res0:4; + unsigned int LastBuff:1; + unsigned int NoCrc:1; + unsigned int Res1:10; + unsigned int BufExhausted:1; + unsigned int TransmitUnderrun:1; + unsigned int TransmitError:1; + unsigned int Wrap:1; + unsigned int BuffUsed:1; + }S_Status; + }U_Status; +}AT91S_TxTdDescriptor, *AT91PS_TxTdDescriptor; + +#define AT91C_OWNERSHIP_BIT 0x00000001 + +/* Receive status defintion */ +#define AT91C_BROADCAST_ADDR ((unsigned int) (1 << 31)) //* Broadcat address detected +#define AT91C_MULTICAST_HASH ((unsigned int) (1 << 30)) //* MultiCast hash match +#define AT91C_UNICAST_HASH ((unsigned int) (1 << 29)) //* UniCast hash match +#define AT91C_EXTERNAL_ADDR ((unsigned int) (1 << 28)) //* External Address match +#define AT91C_SA1_ADDR ((unsigned int) (1 << 26)) //* Specific address 1 match +#define AT91C_SA2_ADDR ((unsigned int) (1 << 25)) //* Specific address 2 match +#define AT91C_SA3_ADDR ((unsigned int) (1 << 24)) //* Specific address 3 match +#define AT91C_SA4_ADDR ((unsigned int) (1 << 23)) //* Specific address 4 match +#define AT91C_TYPE_ID ((unsigned int) (1 << 22)) //* Type ID match +#define AT91C_VLAN_TAG ((unsigned int) (1 << 21)) //* VLAN tag detected +#define AT91C_PRIORITY_TAG ((unsigned int) (1 << 20)) //* PRIORITY tag detected +#define AT91C_VLAN_PRIORITY ((unsigned int) (7 << 17)) //* PRIORITY Mask +#define AT91C_CFI_IND ((unsigned int) (1 << 16)) //* CFI indicator +#define AT91C_EOF ((unsigned int) (1 << 15)) //* EOF +#define AT91C_SOF ((unsigned int) (1 << 14)) //* SOF +#define AT91C_RBF_OFFSET ((unsigned int) (3 << 12)) //* Receive Buffer Offset Mask +#define AT91C_LENGTH_FRAME ((unsigned int) 0x07FF) //* Length of frame + +/* Transmit Status definition */ +#define AT91C_TRANSMIT_OK ((unsigned int) (1 << 31)) //* +#define AT91C_TRANSMIT_WRAP ((unsigned int) (1 << 30)) //* Wrap bit: mark the last descriptor +#define AT91C_TRANSMIT_ERR ((unsigned int) (1 << 29)) //* RLE:transmit error +#define AT91C_TRANSMIT_UND ((unsigned int) (1 << 28)) //* Transmit Underrun +#define AT91C_BUF_EX ((unsigned int) (1 << 27)) //* Buffers exhausted in mid frame +#define AT91C_TRANSMIT_NO_CRC ((unsigned int) (1 << 16)) //* No CRC will be appended to the current frame +#define AT91C_LAST_BUFFER ((unsigned int) (1 << 15)) //* + +#define ARP_ETHER 1 /* Ethernet hardware address */ +#define ARPOP_REQUEST 1 /* Request to resolve address */ +#define ARPOP_REPLY 2 /* Response to previous request */ +#define RARPOP_REQUEST 3 /* Request to resolve address */ +#define RARPOP_REPLY 4 /* Response to previous request */ + + +typedef struct _AT91S_EthHdr +{ + unsigned char et_dest[6]; /* Destination node */ + unsigned char et_src[6]; /* Source node */ + unsigned short et_protlen; /* Protocol or length */ +} AT91S_EthHdr, *AT91PS_EthHdr; + +typedef struct _AT91S_ArpHdr +{ + unsigned short ar_hrd; /* Format of hardware address */ + unsigned short ar_pro; /* Format of protocol address */ + unsigned char ar_hln; /* Length of hardware address */ + unsigned char ar_pln; /* Length of protocol address */ + unsigned short ar_op; /* Operation */ + unsigned char ar_sha[6]; /* Sender hardware address */ + unsigned char ar_spa[4]; /* Sender protocol address */ + unsigned char ar_tha[6]; /* Target hardware address */ + unsigned char ar_tpa[4]; /* Target protocol address */ +} AT91S_ArpHdr, *AT91PS_ArpHdr; + +//* IP Header structure +typedef struct _AT91S_IPheader { + unsigned char ip_hl_v; /* header length and version */ + unsigned char ip_tos; /* type of service */ + unsigned short ip_len; /* total length */ + unsigned short ip_id; /* identification */ + unsigned short ip_off; /* fragment offset field */ + unsigned char ip_ttl; /* time to live */ + unsigned char ip_p; /* protocol */ + unsigned short ip_sum; /* checksum */ + unsigned char ip_src[4]; /* Source IP address */ + unsigned char ip_dst[4]; /* Destination IP address */ + unsigned short udp_src; /* UDP source port */ + unsigned short udp_dst; /* UDP destination port */ + unsigned short udp_len; /* Length of UDP packet */ + unsigned short udp_xsum; /* Checksum */ +} AT91S_IPheader, *AT91PS_IPheader; + +//* ICMP echo header structure +typedef struct _AT91S_IcmpEchoHdr { + unsigned char type; /* type of message */ + unsigned char code; /* type subcode */ + unsigned short cksum; /* ones complement cksum of struct */ + unsigned short id; /* identifier */ + unsigned short seq; /* sequence number */ +}AT91S_IcmpEchoHdr, *AT91PS_IcmpEchoHdr; + + +typedef struct _AT91S_EthPack +{ + AT91S_EthHdr EthHdr; + AT91S_ArpHdr ArpHdr; +} AT91S_EthPack, *AT91PS_EthPack; + + +#endif //* AT91C_EMAC_H diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/http-strings b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/http-strings new file mode 100644 index 000000000..0d3c30cdd --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/http-strings @@ -0,0 +1,35 @@ +http_http "http://" +http_200 "200 " +http_301 "301 " +http_302 "302 " +http_get "GET " +http_10 "HTTP/1.0" +http_11 "HTTP/1.1" +http_content_type "content-type: " +http_texthtml "text/html" +http_location "location: " +http_host "host: " +http_crnl "\r\n" +http_index_html "/index.html" +http_404_html "/404.html" +http_referer "Referer:" +http_header_200 "HTTP/1.0 200 OK\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" +http_header_404 "HTTP/1.0 404 Not found\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" +http_content_type_plain "Content-type: text/plain\r\n\r\n" +http_content_type_html "Content-type: text/html\r\n\r\n" +http_content_type_css "Content-type: text/css\r\n\r\n" +http_content_type_text "Content-type: text/text\r\n\r\n" +http_content_type_png "Content-type: image/png\r\n\r\n" +http_content_type_gif "Content-type: image/gif\r\n\r\n" +http_content_type_jpg "Content-type: image/jpeg\r\n\r\n" +http_content_type_binary "Content-type: application/octet-stream\r\n\r\n" +http_html ".html" +http_shtml ".shtml" +http_htm ".htm" +http_css ".css" +http_png ".png" +http_gif ".gif" +http_jpg ".jpg" +http_text ".txt" +http_txt ".txt" + diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/http-strings.c b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/http-strings.c new file mode 100644 index 000000000..ef7a41c7d --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/http-strings.c @@ -0,0 +1,102 @@ +const char http_http[8] = +/* "http://" */ +{0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, }; +const char http_200[5] = +/* "200 " */ +{0x32, 0x30, 0x30, 0x20, }; +const char http_301[5] = +/* "301 " */ +{0x33, 0x30, 0x31, 0x20, }; +const char http_302[5] = +/* "302 " */ +{0x33, 0x30, 0x32, 0x20, }; +const char http_get[5] = +/* "GET " */ +{0x47, 0x45, 0x54, 0x20, }; +const char http_10[9] = +/* "HTTP/1.0" */ +{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, }; +const char http_11[9] = +/* "HTTP/1.1" */ +{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x31, }; +const char http_content_type[15] = +/* "content-type: " */ +{0x63, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, }; +const char http_texthtml[10] = +/* "text/html" */ +{0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_location[11] = +/* "location: " */ +{0x6c, 0x6f, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, }; +const char http_host[7] = +/* "host: " */ +{0x68, 0x6f, 0x73, 0x74, 0x3a, 0x20, }; +const char http_crnl[3] = +/* "\r\n" */ +{0xd, 0xa, }; +const char http_index_html[12] = +/* "/index.html" */ +{0x2f, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_404_html[10] = +/* "/404.html" */ +{0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_referer[9] = +/* "Referer:" */ +{0x52, 0x65, 0x66, 0x65, 0x72, 0x65, 0x72, 0x3a, }; +const char http_header_200[84] = +/* "HTTP/1.0 200 OK\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */ +{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x32, 0x30, 0x30, 0x20, 0x4f, 0x4b, 0xd, 0xa, 0x53, 0x65, 0x72, 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x73, 0x69, 0x63, 0x73, 0x2e, 0x73, 0x65, 0x2f, 0x7e, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, 0x70, 0x2f, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0xd, 0xa, }; +const char http_header_404[91] = +/* "HTTP/1.0 404 Not found\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */ +{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x34, 0x30, 0x34, 0x20, 0x4e, 0x6f, 0x74, 0x20, 0x66, 0x6f, 0x75, 0x6e, 0x64, 0xd, 0xa, 0x53, 0x65, 0x72, 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x73, 0x69, 0x63, 0x73, 0x2e, 0x73, 0x65, 0x2f, 0x7e, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, 0x70, 0x2f, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0xd, 0xa, }; +const char http_content_type_plain[29] = +/* "Content-type: text/plain\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x70, 0x6c, 0x61, 0x69, 0x6e, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_html[28] = +/* "Content-type: text/html\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_css [27] = +/* "Content-type: text/css\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x63, 0x73, 0x73, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_text[28] = +/* "Content-type: text/text\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x74, 0x65, 0x78, 0x74, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_png [28] = +/* "Content-type: image/png\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x70, 0x6e, 0x67, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_gif [28] = +/* "Content-type: image/gif\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x67, 0x69, 0x66, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_jpg [29] = +/* "Content-type: image/jpeg\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x6a, 0x70, 0x65, 0x67, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_binary[43] = +/* "Content-type: application/octet-stream\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x61, 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x2f, 0x6f, 0x63, 0x74, 0x65, 0x74, 0x2d, 0x73, 0x74, 0x72, 0x65, 0x61, 0x6d, 0xd, 0xa, 0xd, 0xa, }; +const char http_html[6] = +/* ".html" */ +{0x2e, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_shtml[7] = +/* ".shtml" */ +{0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_htm[5] = +/* ".htm" */ +{0x2e, 0x68, 0x74, 0x6d, }; +const char http_css[5] = +/* ".css" */ +{0x2e, 0x63, 0x73, 0x73, }; +const char http_png[5] = +/* ".png" */ +{0x2e, 0x70, 0x6e, 0x67, }; +const char http_gif[5] = +/* ".gif" */ +{0x2e, 0x67, 0x69, 0x66, }; +const char http_jpg[5] = +/* ".jpg" */ +{0x2e, 0x6a, 0x70, 0x67, }; +const char http_text[5] = +/* ".txt" */ +{0x2e, 0x74, 0x78, 0x74, }; +const char http_txt[5] = +/* ".txt" */ +{0x2e, 0x74, 0x78, 0x74, }; diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/http-strings.h b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/http-strings.h new file mode 100644 index 000000000..acbe7e17f --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/http-strings.h @@ -0,0 +1,34 @@ +extern const char http_http[8]; +extern const char http_200[5]; +extern const char http_301[5]; +extern const char http_302[5]; +extern const char http_get[5]; +extern const char http_10[9]; +extern const char http_11[9]; +extern const char http_content_type[15]; +extern const char http_texthtml[10]; +extern const char http_location[11]; +extern const char http_host[7]; +extern const char http_crnl[3]; +extern const char http_index_html[12]; +extern const char http_404_html[10]; +extern const char http_referer[9]; +extern const char http_header_200[84]; +extern const char http_header_404[91]; +extern const char http_content_type_plain[29]; +extern const char http_content_type_html[28]; +extern const char http_content_type_css [27]; +extern const char http_content_type_text[28]; +extern const char http_content_type_png [28]; +extern const char http_content_type_gif [28]; +extern const char http_content_type_jpg [29]; +extern const char http_content_type_binary[43]; +extern const char http_html[6]; +extern const char http_shtml[7]; +extern const char http_htm[5]; +extern const char http_css[5]; +extern const char http_png[5]; +extern const char http_gif[5]; +extern const char http_jpg[5]; +extern const char http_text[5]; +extern const char http_txt[5]; diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/httpd-cgi.c b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/httpd-cgi.c new file mode 100644 index 000000000..43b7afba2 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/httpd-cgi.c @@ -0,0 +1,268 @@ +/** + * \addtogroup httpd + * @{ + */ + +/** + * \file + * Web server script interface + * \author + * Adam Dunkels + * + */ + +/* + * Copyright (c) 2001-2006, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: httpd-cgi.c,v 1.2 2006/06/11 21:46:37 adam Exp $ + * + */ + +#include "uip.h" +#include "psock.h" +#include "httpd.h" +#include "httpd-cgi.h" +#include "httpd-fs.h" + +#include +#include + +HTTPD_CGI_CALL(file, "file-stats", file_stats); +HTTPD_CGI_CALL(tcp, "tcp-connections", tcp_stats); +HTTPD_CGI_CALL(net, "net-stats", net_stats); +HTTPD_CGI_CALL(rtos, "rtos-stats", rtos_stats ); +HTTPD_CGI_CALL(io, "led-io", led_io ); + + +static const struct httpd_cgi_call *calls[] = { &file, &tcp, &net, &rtos, &io, NULL }; + +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(nullfunction(struct httpd_state *s, char *ptr)) +{ + PSOCK_BEGIN(&s->sout); + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +httpd_cgifunction +httpd_cgi(char *name) +{ + const struct httpd_cgi_call **f; + + /* Find the matching name in the table, return the function. */ + for(f = calls; *f != NULL; ++f) { + if(strncmp((*f)->name, name, strlen((*f)->name)) == 0) { + return (*f)->function; + } + } + return nullfunction; +} +/*---------------------------------------------------------------------------*/ +static unsigned short +generate_file_stats(void *arg) +{ + char *f = (char *)arg; + return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, "%5u", httpd_fs_count(f)); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(file_stats(struct httpd_state *s, char *ptr)) +{ + PSOCK_BEGIN(&s->sout); + + PSOCK_GENERATOR_SEND(&s->sout, generate_file_stats, strchr(ptr, ' ') + 1); + + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +static const char closed[] = /* "CLOSED",*/ +{0x43, 0x4c, 0x4f, 0x53, 0x45, 0x44, 0}; +static const char syn_rcvd[] = /* "SYN-RCVD",*/ +{0x53, 0x59, 0x4e, 0x2d, 0x52, 0x43, 0x56, + 0x44, 0}; +static const char syn_sent[] = /* "SYN-SENT",*/ +{0x53, 0x59, 0x4e, 0x2d, 0x53, 0x45, 0x4e, + 0x54, 0}; +static const char established[] = /* "ESTABLISHED",*/ +{0x45, 0x53, 0x54, 0x41, 0x42, 0x4c, 0x49, 0x53, 0x48, + 0x45, 0x44, 0}; +static const char fin_wait_1[] = /* "FIN-WAIT-1",*/ +{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49, + 0x54, 0x2d, 0x31, 0}; +static const char fin_wait_2[] = /* "FIN-WAIT-2",*/ +{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49, + 0x54, 0x2d, 0x32, 0}; +static const char closing[] = /* "CLOSING",*/ +{0x43, 0x4c, 0x4f, 0x53, 0x49, + 0x4e, 0x47, 0}; +static const char time_wait[] = /* "TIME-WAIT,"*/ +{0x54, 0x49, 0x4d, 0x45, 0x2d, 0x57, 0x41, + 0x49, 0x54, 0}; +static const char last_ack[] = /* "LAST-ACK"*/ +{0x4c, 0x41, 0x53, 0x54, 0x2d, 0x41, 0x43, + 0x4b, 0}; + +static const char *states[] = { + closed, + syn_rcvd, + syn_sent, + established, + fin_wait_1, + fin_wait_2, + closing, + time_wait, + last_ack}; + + +static unsigned short +generate_tcp_stats(void *arg) +{ + struct uip_conn *conn; + struct httpd_state *s = (struct httpd_state *)arg; + + conn = &uip_conns[s->count]; + return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, + "%d%u.%u.%u.%u:%u%s%u%u%c %c\r\n", + htons(conn->lport), + htons(conn->ripaddr[0]) >> 8, + htons(conn->ripaddr[0]) & 0xff, + htons(conn->ripaddr[1]) >> 8, + htons(conn->ripaddr[1]) & 0xff, + htons(conn->rport), + states[conn->tcpstateflags & UIP_TS_MASK], + conn->nrtx, + conn->timer, + (uip_outstanding(conn))? '*':' ', + (uip_stopped(conn))? '!':' '); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(tcp_stats(struct httpd_state *s, char *ptr)) +{ + + PSOCK_BEGIN(&s->sout); + + for(s->count = 0; s->count < UIP_CONNS; ++s->count) { + if((uip_conns[s->count].tcpstateflags & UIP_TS_MASK) != UIP_CLOSED) { + PSOCK_GENERATOR_SEND(&s->sout, generate_tcp_stats, s); + } + } + + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +static unsigned short +generate_net_stats(void *arg) +{ + struct httpd_state *s = (struct httpd_state *)arg; + return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, + "%5u\n", ((uip_stats_t *)&uip_stat)[s->count]); +} + +static +PT_THREAD(net_stats(struct httpd_state *s, char *ptr)) +{ + PSOCK_BEGIN(&s->sout); + +#if UIP_STATISTICS + + for(s->count = 0; s->count < sizeof(uip_stat) / sizeof(uip_stats_t); + ++s->count) { + PSOCK_GENERATOR_SEND(&s->sout, generate_net_stats, s); + } + +#endif /* UIP_STATISTICS */ + + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ + +extern void vTaskList( signed char *pcWriteBuffer ); +static char cCountBuf[ 32 ]; +long lRefreshCount = 0; +static unsigned short +generate_rtos_stats(void *arg) +{ + lRefreshCount++; + sprintf( cCountBuf, "


Refresh count = %ld", lRefreshCount ); + vTaskList( uip_appdata ); + strcat( uip_appdata, cCountBuf ); + + return strlen( uip_appdata ); +} +/*---------------------------------------------------------------------------*/ + + +static +PT_THREAD(rtos_stats(struct httpd_state *s, char *ptr)) +{ + PSOCK_BEGIN(&s->sout); + PSOCK_GENERATOR_SEND(&s->sout, generate_rtos_stats, NULL); + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ + +char *pcStatus; +unsigned long ulString; +extern unsigned long uxParTextGetLED( unsigned long uxLED ); + +static unsigned short generate_io_state( void *arg ) +{ + if( uxParTestGetLED() ) + { + pcStatus = "checked"; + } + else + { + pcStatus = ""; + } + + sprintf( uip_appdata, + "LED DS4,"\ + "

", + pcStatus ); + + return strlen( uip_appdata ); +} + +static PT_THREAD(led_io(struct httpd_state *s, char *ptr)) +{ + PSOCK_BEGIN(&s->sout); + PSOCK_GENERATOR_SEND(&s->sout, generate_io_state, NULL); + PSOCK_END(&s->sout); +} + +/** @} */ + + + + + + diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/httpd-cgi.h b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/httpd-cgi.h new file mode 100644 index 000000000..7ae928321 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/httpd-cgi.h @@ -0,0 +1,84 @@ +/** + * \addtogroup httpd + * @{ + */ + +/** + * \file + * Web server script interface header file + * \author + * Adam Dunkels + * + */ + + + +/* + * Copyright (c) 2001, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: httpd-cgi.h,v 1.2 2006/06/11 21:46:38 adam Exp $ + * + */ + +#ifndef __HTTPD_CGI_H__ +#define __HTTPD_CGI_H__ + +#include "psock.h" +#include "httpd.h" + +typedef PT_THREAD((* httpd_cgifunction)(struct httpd_state *, char *)); + +httpd_cgifunction httpd_cgi(char *name); + +struct httpd_cgi_call { + const char *name; + const httpd_cgifunction function; +}; + +/** + * \brief HTTPD CGI function declaration + * \param name The C variable name of the function + * \param str The string name of the function, used in the script file + * \param function A pointer to the function that implements it + * + * This macro is used for declaring a HTTPD CGI + * function. This function is then added to the list of + * HTTPD CGI functions with the httpd_cgi_add() function. + * + * \hideinitializer + */ +#define HTTPD_CGI_CALL(name, str, function) \ +static PT_THREAD(function(struct httpd_state *, char *)); \ +static const struct httpd_cgi_call name = {str, function} + +void httpd_cgi_init(void); +#endif /* __HTTPD_CGI_H__ */ + +/** @} */ diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/httpd-fs.c b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/httpd-fs.c new file mode 100644 index 000000000..dc4aef011 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/httpd-fs.c @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: httpd-fs.c,v 1.1 2006/06/07 09:13:08 adam Exp $ + */ + +#include "httpd.h" +#include "httpd-fs.h" +#include "httpd-fsdata.h" + +#ifndef NULL +#define NULL 0 +#endif /* NULL */ + +#include "httpd-fsdata.c" + +#if HTTPD_FS_STATISTICS +static u16_t count[HTTPD_FS_NUMFILES]; +#endif /* HTTPD_FS_STATISTICS */ + +/*-----------------------------------------------------------------------------------*/ +static u8_t +httpd_fs_strcmp(const char *str1, const char *str2) +{ + u8_t i; + i = 0; + loop: + + if(str2[i] == 0 || + str1[i] == '\r' || + str1[i] == '\n') { + return 0; + } + + if(str1[i] != str2[i]) { + return 1; + } + + + ++i; + goto loop; +} +/*-----------------------------------------------------------------------------------*/ +int +httpd_fs_open(const char *name, struct httpd_fs_file *file) +{ +#if HTTPD_FS_STATISTICS + u16_t i = 0; +#endif /* HTTPD_FS_STATISTICS */ + struct httpd_fsdata_file_noconst *f; + + for(f = (struct httpd_fsdata_file_noconst *)HTTPD_FS_ROOT; + f != NULL; + f = (struct httpd_fsdata_file_noconst *)f->next) { + + if(httpd_fs_strcmp(name, f->name) == 0) { + file->data = f->data; + file->len = f->len; +#if HTTPD_FS_STATISTICS + ++count[i]; +#endif /* HTTPD_FS_STATISTICS */ + return 1; + } +#if HTTPD_FS_STATISTICS + ++i; +#endif /* HTTPD_FS_STATISTICS */ + + } + return 0; +} +/*-----------------------------------------------------------------------------------*/ +void +httpd_fs_init(void) +{ +#if HTTPD_FS_STATISTICS + u16_t i; + for(i = 0; i < HTTPD_FS_NUMFILES; i++) { + count[i] = 0; + } +#endif /* HTTPD_FS_STATISTICS */ +} +/*-----------------------------------------------------------------------------------*/ +#if HTTPD_FS_STATISTICS +u16_t httpd_fs_count +(char *name) +{ + struct httpd_fsdata_file_noconst *f; + u16_t i; + + i = 0; + for(f = (struct httpd_fsdata_file_noconst *)HTTPD_FS_ROOT; + f != NULL; + f = (struct httpd_fsdata_file_noconst *)f->next) { + + if(httpd_fs_strcmp(name, f->name) == 0) { + return count[i]; + } + ++i; + } + return 0; +} +#endif /* HTTPD_FS_STATISTICS */ +/*-----------------------------------------------------------------------------------*/ diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/httpd-fs.h b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/httpd-fs.h new file mode 100644 index 000000000..b594eea56 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/httpd-fs.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: httpd-fs.h,v 1.1 2006/06/07 09:13:08 adam Exp $ + */ +#ifndef __HTTPD_FS_H__ +#define __HTTPD_FS_H__ + +#define HTTPD_FS_STATISTICS 1 + +struct httpd_fs_file { + char *data; + int len; +}; + +/* file must be allocated by caller and will be filled in + by the function. */ +int httpd_fs_open(const char *name, struct httpd_fs_file *file); + +#ifdef HTTPD_FS_STATISTICS +#if HTTPD_FS_STATISTICS == 1 +u16_t httpd_fs_count(char *name); +#endif /* HTTPD_FS_STATISTICS */ +#endif /* HTTPD_FS_STATISTICS */ + +void httpd_fs_init(void); + +#endif /* __HTTPD_FS_H__ */ diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/httpd-fs/404.html b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/httpd-fs/404.html new file mode 100644 index 000000000..43e7f4cad --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/httpd-fs/404.html @@ -0,0 +1,8 @@ + + +

+

404 - file not found

+

Go here instead.

+
+ + \ No newline at end of file diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/httpd-fs/index.html b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/httpd-fs/index.html new file mode 100644 index 000000000..1d3bbeee1 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/httpd-fs/index.html @@ -0,0 +1,13 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +Loading index.shtml. Click here if not automatically redirected. + + + + + diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/httpd-fs/index.shtml b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/httpd-fs/index.shtml new file mode 100644 index 000000000..0ce405ba0 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/httpd-fs/index.shtml @@ -0,0 +1,20 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +RTOS Stats | TCP Stats | Connections | FreeRTOS.org Homepage | IO +

+

+

+

Task statistics

+Page will refresh evey 2 seconds.

+

Task          State  Priority  Stack	#
************************************************

+%! rtos-stats
+
+ + + + diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/httpd-fs/io.shtml b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/httpd-fs/io.shtml new file mode 100644 index 000000000..bacef5f7d --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/httpd-fs/io.shtml @@ -0,0 +1,28 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +RTOS Stats | TCP Stats | Connections | FreeRTOS.org Homepage | IO +

+

+LED IO
+ +

+ +Use the check box to set the LED state, then click "Update IO" to send the new state to the microcontroller. + + +

+

+%! led-io +

+ +

+

+ + + + diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/httpd-fs/stats.shtml b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/httpd-fs/stats.shtml new file mode 100644 index 000000000..d762f40d8 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/httpd-fs/stats.shtml @@ -0,0 +1,41 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +RTOS Stats | TCP Stats | Connections | FreeRTOS.org Homepage | IO +

+

+

+

Network statistics

+ +
+IP           Packets dropped
+             Packets received
+             Packets sent
+IP errors    IP version/header length
+             IP length, high byte
+             IP length, low byte
+             IP fragments
+             Header checksum
+             Wrong protocol
+ICMP	     Packets dropped
+             Packets received
+             Packets sent
+             Type errors
+TCP          Packets dropped
+             Packets received
+             Packets sent
+             Checksum errors
+             Data packets without ACKs
+             Resets
+             Retransmissions
+	     No connection avaliable
+	     Connection attempts to closed ports
+
%! net-stats
+
+ + + diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/httpd-fs/tcp.shtml b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/httpd-fs/tcp.shtml new file mode 100644 index 000000000..654d61f21 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/httpd-fs/tcp.shtml @@ -0,0 +1,21 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +RTOS Stats | TCP Stats | Connections | FreeRTOS.org Homepage | IO +

+

+
+

Network connections

+

+ + +%! tcp-connections + + + + + diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/httpd-fsdata.c b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/httpd-fsdata.c new file mode 100644 index 000000000..481f3af15 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/httpd-fsdata.c @@ -0,0 +1,468 @@ +static const unsigned char data_404_html[] = { + /* /404.html */ + 0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0, + 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xd, 0xa, 0x20, 0x20, + 0x3c, 0x62, 0x6f, 0x64, 0x79, 0x20, 0x62, 0x67, 0x63, 0x6f, + 0x6c, 0x6f, 0x72, 0x3d, 0x22, 0x77, 0x68, 0x69, 0x74, 0x65, + 0x22, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x3c, 0x63, + 0x65, 0x6e, 0x74, 0x65, 0x72, 0x3e, 0xd, 0xa, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x3c, 0x68, 0x31, 0x3e, 0x34, 0x30, + 0x34, 0x20, 0x2d, 0x20, 0x66, 0x69, 0x6c, 0x65, 0x20, 0x6e, + 0x6f, 0x74, 0x20, 0x66, 0x6f, 0x75, 0x6e, 0x64, 0x3c, 0x2f, + 0x68, 0x31, 0x3e, 0xd, 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unsigned char data_tcp_shtml[] = { + /* /tcp.shtml */ + 0x2f, 0x74, 0x63, 0x70, 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0, + 0x3c, 0x21, 0x44, 0x4f, 0x43, 0x54, 0x59, 0x50, 0x45, 0x20, + 0x48, 0x54, 0x4d, 0x4c, 0x20, 0x50, 0x55, 0x42, 0x4c, 0x49, + 0x43, 0x20, 0x22, 0x2d, 0x2f, 0x2f, 0x57, 0x33, 0x43, 0x2f, + 0x2f, 0x44, 0x54, 0x44, 0x20, 0x48, 0x54, 0x4d, 0x4c, 0x20, + 0x34, 0x2e, 0x30, 0x31, 0x20, 0x54, 0x72, 0x61, 0x6e, 0x73, + 0x69, 0x74, 0x69, 0x6f, 0x6e, 0x61, 0x6c, 0x2f, 0x2f, 0x45, + 0x4e, 0x22, 0x20, 0x22, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, + 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x77, 0x33, 0x2e, 0x6f, 0x72, + 0x67, 0x2f, 0x54, 0x52, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x34, + 0x2f, 0x6c, 0x6f, 0x6f, 0x73, 0x65, 0x2e, 0x64, 0x74, 0x64, + 0x22, 0x3e, 0xd, 0xa, 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, + 0xd, 0xa, 0x20, 0x20, 0x3c, 0x68, 0x65, 0x61, 0x64, 0x3e, + 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x3c, 0x74, 0x69, 0x74, + 0x6c, 0x65, 0x3e, 0x46, 0x72, 0x65, 0x65, 0x52, 0x54, 0x4f, + 0x53, 0x2e, 0x6f, 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0x74, + 0x68, 0x3e, 0x3c, 0x2f, 0x74, 0x72, 0x3e, 0xd, 0xa, 0x25, + 0x21, 0x20, 0x74, 0x63, 0x70, 0x2d, 0x63, 0x6f, 0x6e, 0x6e, + 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x73, 0xd, 0xa, 0x3c, + 0x2f, 0x70, 0x72, 0x65, 0x3e, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, + 0x74, 0x3e, 0xd, 0xa, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, 0x74, + 0x3e, 0xd, 0xa, 0x3c, 0x2f, 0x62, 0x6f, 0x64, 0x79, 0x3e, + 0xd, 0xa, 0x3c, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xd, + 0xa, 0xd, 0xa, 0}; + +const struct httpd_fsdata_file file_404_html[] = {{NULL, data_404_html, data_404_html + 10, sizeof(data_404_html) - 10}}; + +const struct httpd_fsdata_file file_index_html[] = {{file_404_html, data_index_html, data_index_html + 12, sizeof(data_index_html) - 12}}; + +const struct httpd_fsdata_file file_index_shtml[] = {{file_index_html, data_index_shtml, data_index_shtml + 13, sizeof(data_index_shtml) - 13}}; + +const struct httpd_fsdata_file file_io_shtml[] = {{file_index_shtml, data_io_shtml, data_io_shtml + 10, sizeof(data_io_shtml) - 10}}; + +const struct httpd_fsdata_file file_stats_shtml[] = {{file_io_shtml, data_stats_shtml, data_stats_shtml + 13, sizeof(data_stats_shtml) - 13}}; + +const struct httpd_fsdata_file file_tcp_shtml[] = {{file_stats_shtml, data_tcp_shtml, data_tcp_shtml + 11, sizeof(data_tcp_shtml) - 11}}; + +#define HTTPD_FS_ROOT file_tcp_shtml + +#define HTTPD_FS_NUMFILES 6 diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/httpd-fsdata.h b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/httpd-fsdata.h new file mode 100644 index 000000000..52d35c265 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/httpd-fsdata.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: httpd-fsdata.h,v 1.1 2006/06/07 09:13:08 adam Exp $ + */ +#ifndef __HTTPD_FSDATA_H__ +#define __HTTPD_FSDATA_H__ + +#include "uip.h" + +struct httpd_fsdata_file { + const struct httpd_fsdata_file *next; + const char *name; + const char *data; + const int len; +#ifdef HTTPD_FS_STATISTICS +#if HTTPD_FS_STATISTICS == 1 + u16_t count; +#endif /* HTTPD_FS_STATISTICS */ +#endif /* HTTPD_FS_STATISTICS */ +}; + +struct httpd_fsdata_file_noconst { + struct httpd_fsdata_file *next; + char *name; + char *data; + int len; +#ifdef HTTPD_FS_STATISTICS +#if HTTPD_FS_STATISTICS == 1 + u16_t count; +#endif /* HTTPD_FS_STATISTICS */ +#endif /* HTTPD_FS_STATISTICS */ +}; + +#endif /* __HTTPD_FSDATA_H__ */ diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/httpd.c b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/httpd.c new file mode 100644 index 000000000..5c0b40933 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/httpd.c @@ -0,0 +1,413 @@ +/*$T httpd.c GC 1.138 11/17/07 13:10:22 */ + +/* + * \addtogroup apps @{ £ + * \defgroup httpd Web server @{ The uIP web server is a very simplistic + * implementation of an HTTP server. It can serve web pages and files from a + * read-only ROM filesystem, and provides a very small scripting language. £ + * \file Web server \author Adam Dunkels £ + * Copyright (c) 2004, Adam Dunkels. All rights reserved. Redistribution and use + * in source and binary forms, with or without modification, are permitted + * provided that the following conditions are met: 1. Redistributions of source + * code must retain the above copyright notice, this list of conditions and the + * following disclaimer. 2. Redistributions in binary form must reproduce the + * above copyright notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the distribution. 3. + * Neither the name of the Institute nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND + * CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT + * NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. This file is part of the uIP TCP/IP stack. Author: Adam Dunkels + * $Id: httpd.c,v 1.2 2006/06/11 21:46:38 adam Exp $ + */ +#include "uip.h" +#include "httpd.h" +#include "httpd-fs.h" +#include "httpd-cgi.h" +#include "http-strings.h" + +#include + +#define STATE_WAITING 0 +#define STATE_OUTPUT 1 + +#define ISO_nl 0x0a +#define ISO_space 0x20 +#define ISO_bang 0x21 +#define ISO_percent 0x25 +#define ISO_period 0x2e +#define ISO_slash 0x2f +#define ISO_colon 0x3a + +/* + ======================================================================================================================= + ======================================================================================================================= + */ +static unsigned short generate_part_of_file(void *state) +{ + /*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/ + struct httpd_state *s = (struct httpd_state *) state; + /*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/ + + if(s->file.len > uip_mss()) + { + s->len = uip_mss(); + } + else + { + s->len = s->file.len; + } + + memcpy(uip_appdata, s->file.data, s->len); + + return s->len; +} + +/* + ======================================================================================================================= + ======================================================================================================================= + */ +static PT_THREAD(send_file (struct httpd_state *s)) +{ + PSOCK_BEGIN(&s->sout); + + do + { + PSOCK_GENERATOR_SEND(&s->sout, generate_part_of_file, s); + s->file.len -= s->len; + s->file.data += s->len; + } while(s->file.len > 0); + + PSOCK_END(&s->sout); +} + +/* + ======================================================================================================================= + ======================================================================================================================= + */ +static PT_THREAD(send_part_of_file (struct httpd_state *s)) +{ + PSOCK_BEGIN(&s->sout); + + PSOCK_SEND(&s->sout, s->file.data, s->len); + + PSOCK_END(&s->sout); +} + +/* + ======================================================================================================================= + ======================================================================================================================= + */ +static void next_scriptstate(struct httpd_state *s) +{ + /*~~~~~~~*/ + char *p; + /*~~~~~~~*/ + + p = strchr(s->scriptptr, ISO_nl) + 1; + s->scriptlen -= (unsigned short) (p - s->scriptptr); + s->scriptptr = p; +} + +/* + ======================================================================================================================= + ======================================================================================================================= + */ +static PT_THREAD(handle_script (struct httpd_state *s)) +{ + /*~~~~~~~~~*/ + char *ptr; + /*~~~~~~~~~*/ + + PT_BEGIN(&s->scriptpt); + + while(s->file.len > 0) + { + /* Check if we should start executing a script. */ + if(*s->file.data == ISO_percent && *(s->file.data + 1) == ISO_bang) + { + s->scriptptr = s->file.data + 3; + s->scriptlen = s->file.len - 3; + if(*(s->scriptptr - 1) == ISO_colon) + { + httpd_fs_open(s->scriptptr + 1, &s->file); + PT_WAIT_THREAD(&s->scriptpt, send_file(s)); + } + else + { + PT_WAIT_THREAD(&s->scriptpt, httpd_cgi(s->scriptptr) (s, s->scriptptr)); + } + + next_scriptstate(s); + + /* + * The script is over, so we reset the pointers and continue sending the rest of + * the file. + */ + s->file.data = s->scriptptr; + s->file.len = s->scriptlen; + } + else + { + /* See if we find the start of script marker in the block of HTML to be sent. */ + if(s->file.len > uip_mss()) + { + s->len = uip_mss(); + } + else + { + s->len = s->file.len; + } + + if(*s->file.data == ISO_percent) + { + ptr = strchr(s->file.data + 1, ISO_percent); + } + else + { + ptr = strchr(s->file.data, ISO_percent); + } + + if(ptr != NULL && ptr != s->file.data) + { + s->len = (int) (ptr - s->file.data); + if(s->len >= uip_mss()) + { + s->len = uip_mss(); + } + } + + PT_WAIT_THREAD(&s->scriptpt, send_part_of_file(s)); + s->file.data += s->len; + s->file.len -= s->len; + } + } + + PT_END(&s->scriptpt); +} + +/* + ======================================================================================================================= + ======================================================================================================================= + */ +static PT_THREAD(send_headers (struct httpd_state *s, const char *statushdr)) +{ + /*~~~~~~~~~*/ + char *ptr; + /*~~~~~~~~~*/ + + PSOCK_BEGIN(&s->sout); + + PSOCK_SEND_STR(&s->sout, statushdr); + + ptr = strrchr(s->filename, ISO_period); + if(ptr == NULL) + { + PSOCK_SEND_STR(&s->sout, http_content_type_binary); + } + else if(strncmp(http_html, ptr, 5) == 0 || strncmp(http_shtml, ptr, 6) == 0) + { + PSOCK_SEND_STR(&s->sout, http_content_type_html); + } + else if(strncmp(http_css, ptr, 4) == 0) + { + PSOCK_SEND_STR(&s->sout, http_content_type_css); + } + else if(strncmp(http_png, ptr, 4) == 0) + { + PSOCK_SEND_STR(&s->sout, http_content_type_png); + } + else if(strncmp(http_gif, ptr, 4) == 0) + { + PSOCK_SEND_STR(&s->sout, http_content_type_gif); + } + else if(strncmp(http_jpg, ptr, 4) == 0) + { + PSOCK_SEND_STR(&s->sout, http_content_type_jpg); + } + else + { + PSOCK_SEND_STR(&s->sout, http_content_type_plain); + } + + PSOCK_END(&s->sout); +} + +/* + ======================================================================================================================= + ======================================================================================================================= + */ +static PT_THREAD(handle_output (struct httpd_state *s)) +{ + /*~~~~~~~~~*/ + char *ptr; + /*~~~~~~~~~*/ + + PT_BEGIN(&s->outputpt); + + if(!httpd_fs_open(s->filename, &s->file)) + { + httpd_fs_open(http_404_html, &s->file); + strcpy(s->filename, http_404_html); + PT_WAIT_THREAD(&s->outputpt, send_headers(s, http_header_404)); + PT_WAIT_THREAD(&s->outputpt, send_file(s)); + } + else + { + PT_WAIT_THREAD(&s->outputpt, send_headers(s, http_header_200)); + ptr = strchr(s->filename, ISO_period); + if(ptr != NULL && strncmp(ptr, http_shtml, 6) == 0) + { + vProcessInput( s->filename ); + PT_INIT(&s->scriptpt); + PT_WAIT_THREAD(&s->outputpt, handle_script(s)); + } + else + { + PT_WAIT_THREAD(&s->outputpt, send_file(s)); + } + } + + PSOCK_CLOSE(&s->sout); + PT_END(&s->outputpt); +} + +/* + ======================================================================================================================= + ======================================================================================================================= + */ +static PT_THREAD(handle_input (struct httpd_state *s)) +{ + PSOCK_BEGIN(&s->sin); + + PSOCK_READTO(&s->sin, ISO_space); + + if(strncmp(s->inputbuf, http_get, 4) != 0) + { + PSOCK_CLOSE_EXIT(&s->sin); + } + + PSOCK_READTO(&s->sin, ISO_space); + + if(s->inputbuf[0] != ISO_slash) + { + PSOCK_CLOSE_EXIT(&s->sin); + } + + if(s->inputbuf[1] == ISO_space) + { + strncpy(s->filename, http_index_html, sizeof(s->filename)); + } + else + { + s->inputbuf[PSOCK_DATALEN(&s->sin) - 1] = 0; + + /* Process any form input being sent to the server. */ + { + /* + * extern void vApplicationProcessFormInput( char *pcInputString, long + * xInputLength ); £ + * vApplicationProcessFormInput( s->inputbuf, PSOCK_DATALEN(&s->sin) ); + */ + } + + strncpy(s->filename, &s->inputbuf[0], sizeof(s->filename)); + } + + /* httpd_log_file(uip_conn->ripaddr, s->filename); */ + s->state = STATE_OUTPUT; + + while(1) + { + PSOCK_READTO(&s->sin, ISO_nl); + + if(strncmp(s->inputbuf, http_referer, 8) == 0) + { + s->inputbuf[PSOCK_DATALEN(&s->sin) - 2] = 0; + + /* httpd_log(&s->inputbuf[9]); */ + } + } + + PSOCK_END(&s->sin); +} + +/* + ======================================================================================================================= + ======================================================================================================================= + */ +static void handle_connection(struct httpd_state *s) +{ + handle_input(s); + if(s->state == STATE_OUTPUT) + { + handle_output(s); + } +} + +/* + ======================================================================================================================= + ======================================================================================================================= + */ +void httpd_appcall(void) +{ + /*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/ + struct httpd_state *s = (struct httpd_state *) &(uip_conn->appstate); + /*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/ + + if(uip_closed() || uip_aborted() || uip_timedout()) + { + } + else if(uip_connected()) + { + PSOCK_INIT(&s->sin, s->inputbuf, sizeof(s->inputbuf) - 1); + PSOCK_INIT(&s->sout, s->inputbuf, sizeof(s->inputbuf) - 1); + PT_INIT(&s->outputpt); + s->state = STATE_WAITING; + + /* timer_set(&s->timer, CLOCK_SECOND * 100); */ + s->timer = 0; + handle_connection(s); + } + else if(s != NULL) + { + if(uip_poll()) + { + ++s->timer; + if(s->timer >= 20) + { + uip_abort(); + } + } + else + { + s->timer = 0; + } + + handle_connection(s); + } + else + { + uip_abort(); + } +} + +/* + ======================================================================================================================= + \brief Initialize the web server This function initializes the web server and should be called at system boot-up. + ======================================================================================================================= + */ +void httpd_init(void) +{ + uip_listen(HTONS(80)); +} + +/* @} */ diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/httpd.h b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/httpd.h new file mode 100644 index 000000000..7f7a6666e --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/httpd.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2001-2005, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: httpd.h,v 1.2 2006/06/11 21:46:38 adam Exp $ + * + */ + +#ifndef __HTTPD_H__ +#define __HTTPD_H__ + +#include "psock.h" +#include "httpd-fs.h" + +struct httpd_state { + unsigned char timer; + struct psock sin, sout; + struct pt outputpt, scriptpt; + char inputbuf[50]; + char filename[20]; + char state; + struct httpd_fs_file file; + int len; + char *scriptptr; + int scriptlen; + + unsigned short count; +}; + +void httpd_init(void); +void httpd_appcall(void); + +void httpd_log(char *msg); +void httpd_log_file(u16_t *requester, char *file); + +#endif /* __HTTPD_H__ */ diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/makefsdata b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/makefsdata new file mode 100644 index 000000000..8d2715a8a --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/makefsdata @@ -0,0 +1,78 @@ +#!/usr/bin/perl + +open(OUTPUT, "> httpd-fsdata.c"); + +chdir("httpd-fs"); + +opendir(DIR, "."); +@files = grep { !/^\./ && !/(CVS|~)/ } readdir(DIR); +closedir(DIR); + +foreach $file (@files) { + + if(-d $file && $file !~ /^\./) { + print "Processing directory $file\n"; + opendir(DIR, $file); + @newfiles = grep { !/^\./ && !/(CVS|~)/ } readdir(DIR); + closedir(DIR); + printf "Adding files @newfiles\n"; + @files = (@files, map { $_ = "$file/$_" } @newfiles); + next; + } +} + +foreach $file (@files) { + if(-f $file) { + + print "Adding file $file\n"; + + open(FILE, $file) || die "Could not open file $file\n"; + + $file =~ s-^-/-; + $fvar = $file; + $fvar =~ s-/-_-g; + $fvar =~ s-\.-_-g; + # for AVR, add PROGMEM here + print(OUTPUT "static const unsigned char data".$fvar."[] = {\n"); + print(OUTPUT "\t/* $file */\n\t"); + for($j = 0; $j < length($file); $j++) { + printf(OUTPUT "%#02x, ", unpack("C", substr($file, $j, 1))); + } + printf(OUTPUT "0,\n"); + + + $i = 0; + while(read(FILE, $data, 1)) { + if($i == 0) { + print(OUTPUT "\t"); + } + printf(OUTPUT "%#02x, ", unpack("C", $data)); + $i++; + if($i == 10) { + print(OUTPUT "\n"); + $i = 0; + } + } + print(OUTPUT "0};\n\n"); + close(FILE); + push(@fvars, $fvar); + push(@pfiles, $file); + } +} + +for($i = 0; $i < @fvars; $i++) { + $file = $pfiles[$i]; + $fvar = $fvars[$i]; + + if($i == 0) { + $prevfile = "NULL"; + } else { + $prevfile = "file" . $fvars[$i - 1]; + } + print(OUTPUT "const struct httpd_fsdata_file file".$fvar."[] = {{$prevfile, data$fvar, "); + print(OUTPUT "data$fvar + ". (length($file) + 1) .", "); + print(OUTPUT "sizeof(data$fvar) - ". (length($file) + 1) ."}};\n\n"); +} + +print(OUTPUT "#define HTTPD_FS_ROOT file$fvars[$i - 1]\n\n"); +print(OUTPUT "#define HTTPD_FS_NUMFILES $i\n"); diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/makestrings b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/makestrings new file mode 100644 index 000000000..8a13c6d29 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/makestrings @@ -0,0 +1,40 @@ +#!/usr/bin/perl + + +sub stringify { + my $name = shift(@_); + open(OUTPUTC, "> $name.c"); + open(OUTPUTH, "> $name.h"); + + open(FILE, "$name"); + + while() { + if(/(.+) "(.+)"/) { + $var = $1; + $data = $2; + + $datan = $data; + $datan =~ s/\\r/\r/g; + $datan =~ s/\\n/\n/g; + $datan =~ s/\\01/\01/g; + $datan =~ s/\\0/\0/g; + + printf(OUTPUTC "const char $var\[%d] = \n", length($datan) + 1); + printf(OUTPUTC "/* \"$data\" */\n"); + printf(OUTPUTC "{"); + for($j = 0; $j < length($datan); $j++) { + printf(OUTPUTC "%#02x, ", unpack("C", substr($datan, $j, 1))); + } + printf(OUTPUTC "};\n"); + + printf(OUTPUTH "extern const char $var\[%d];\n", length($datan) + 1); + + } + } + close(OUTPUTC); + close(OUTPUTH); +} +stringify("http-strings"); + +exit 0; + diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/uIP_Task.c b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/uIP_Task.c new file mode 100644 index 000000000..4f2d2a8bb --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/uIP_Task.c @@ -0,0 +1,197 @@ +/* + * Modified from an original work that is Copyright (c) 2001-2003, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: main.c,v 1.10.2.4 2003/10/21 21:27:51 adam Exp $ + * + */ + +/* Standard includes. */ +#include +#include +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* uip includes. */ +#include "uip.h" +#include "uip_arp.h" +#include "httpd.h" +#include "timer.h" +#include "clock-arch.h" + +/* Demo includes. */ +#include "SAM7_EMAC.h" +#include "partest.h" + +/* How long to wait before attempting to connect the MAC again. */ +#define uipINIT_WAIT ( 100 / portTICK_RATE_MS ) + +/* Shortcut to the header within the Rx buffer. */ +#define xHeader ((struct uip_eth_hdr *) &uip_buf[ 0 ]) + +/* The semaphore used by the ISR to wake the uIP task. */ +static xSemaphoreHandle xEMACSemaphore; + +/*-----------------------------------------------------------*/ + +void vuIP_Task( void *pvParameters ) +{ +portBASE_TYPE i; +uip_ipaddr_t xIPAddr; +struct timer periodic_timer, arp_timer; + + /* Initialise the uIP stack. */ + timer_set( &periodic_timer, configTICK_RATE_HZ / 2 ); + timer_set( &arp_timer, configTICK_RATE_HZ * 10 ); + uip_init(); + uip_ipaddr( xIPAddr, uipIP_ADDR0, uipIP_ADDR1, uipIP_ADDR2, uipIP_ADDR3 ); + uip_sethostaddr( xIPAddr ); + httpd_init(); + + /* Initialise the MAC. */ + do + { + vTaskDelay( uipINIT_WAIT ); + xEMACSemaphore = xEMACInit(); + } while( xEMACSemaphore == NULL ); + + for( ;; ) + { + /* Is there received data ready to be processed? */ + uip_len = ulEMACPoll(); + + if( uip_len > 0 ) + { + /* Standard uIP loop taken from the uIP manual. */ + if( xHeader->type == htons( UIP_ETHTYPE_IP ) ) + { + uip_arp_ipin(); + uip_input(); + + /* If the above function invocation resulted in data that + should be sent out on the network, the global variable + uip_len is set to a value > 0. */ + if( uip_len > 0 ) + { + uip_arp_out(); + lEMACSend(); + } + } + else if( xHeader->type == htons( UIP_ETHTYPE_ARP ) ) + { + uip_arp_arpin(); + + /* If the above function invocation resulted in data that + should be sent out on the network, the global variable + uip_len is set to a value > 0. */ + if( uip_len > 0 ) + { + lEMACSend(); + } + } + } + else + { + if( timer_expired( &periodic_timer ) ) + { + timer_reset( &periodic_timer ); + for( i = 0; i < UIP_CONNS; i++ ) + { + uip_periodic( i ); + + /* If the above function invocation resulted in data that + should be sent out on the network, the global variable + uip_len is set to a value > 0. */ + if( uip_len > 0 ) + { + uip_arp_out(); + lEMACSend(); + } + } + + /* Call the ARP timer function every 10 seconds. */ + if( timer_expired( &arp_timer ) ) + { + timer_reset( &arp_timer ); + uip_arp_timer(); + } + } + else + { + /* We did not receive a packet, and there was no periodic + processing to perform. Block for a fixed period. If a packet + is received during this period we will be woken by the ISR + giving us the Semaphore. */ + xSemaphoreTake( xEMACSemaphore, configTICK_RATE_HZ / 2 ); + } + } + } +} +/*-----------------------------------------------------------------------------------*/ + +void clock_init(void) +{ + /* This is done when the scheduler starts. */ +} +/*-----------------------------------------------------------*/ + +clock_time_t clock_time( void ) +{ + return xTaskGetTickCount(); +} +/*-----------------------------------------------------------*/ + +void vProcessInput( char *pcInput ) +{ +char *c; + + /* Turn the LED on or off depending on the checkbox status. */ + + c = strstr( pcInput, "?" ); + if( c ) + { + if( strstr( c, "LED0=1" ) != NULL ) + { + vParTestSetLED( 3, 0 ); + } + else + { + vParTestSetLED( 3, 1 ); + } + } +} + + + + + diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/uIP_Task.h b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/uIP_Task.h new file mode 100644 index 000000000..567063dae --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/uIP_Task.h @@ -0,0 +1,50 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef UIP_TASK_H +#define UIP_TASK_H + +/* The task that handles all uIP data. */ +void vuIP_Task( void *pvParameters ); + +#endif + diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/uip-conf.h b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/uip-conf.h new file mode 100644 index 000000000..3e6f7f381 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/uip-conf.h @@ -0,0 +1,157 @@ +/** + * \addtogroup uipopt + * @{ + */ + +/** + * \name Project-specific configuration options + * @{ + * + * uIP has a number of configuration options that can be overridden + * for each project. These are kept in a project-specific uip-conf.h + * file and all configuration names have the prefix UIP_CONF. + */ + +/* + * Copyright (c) 2006, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: uip-conf.h,v 1.6 2006/06/12 08:00:31 adam Exp $ + */ + +/** + * \file + * An example uIP configuration file + * \author + * Adam Dunkels + */ + +#ifndef __UIP_CONF_H__ +#define __UIP_CONF_H__ + +#include + +/** + * 8 bit datatype + * + * This typedef defines the 8-bit type used throughout uIP. + * + * \hideinitializer + */ +typedef uint8_t u8_t; + +/** + * 16 bit datatype + * + * This typedef defines the 16-bit type used throughout uIP. + * + * \hideinitializer + */ +typedef uint16_t u16_t; + +/** + * Statistics datatype + * + * This typedef defines the dataype used for keeping statistics in + * uIP. + * + * \hideinitializer + */ +typedef unsigned short uip_stats_t; + +/** + * Maximum number of TCP connections. + * + * \hideinitializer + */ +#define UIP_CONF_MAX_CONNECTIONS 40 + +/** + * Maximum number of listening TCP ports. + * + * \hideinitializer + */ +#define UIP_CONF_MAX_LISTENPORTS 40 + +/** + * uIP buffer size. + * + * \hideinitializer + */ +#define UIP_CONF_BUFFER_SIZE 1480 + +/** + * CPU byte order. + * + * \hideinitializer + */ +#define UIP_CONF_BYTE_ORDER LITTLE_ENDIAN + +/** + * Logging on or off + * + * \hideinitializer + */ +#define UIP_CONF_LOGGING 0 + +/** + * UDP support on or off + * + * \hideinitializer + */ +#define UIP_CONF_UDP 0 + +/** + * UDP checksums on or off + * + * \hideinitializer + */ +#define UIP_CONF_UDP_CHECKSUMS 1 + +/** + * uIP statistics on or off + * + * \hideinitializer + */ +#define UIP_CONF_STATISTICS 1 + +/* Here we include the header file for the application(s) we use in + our project. */ +/*#include "smtp.h"*/ +/*#include "hello-world.h"*/ +/*#include "telnetd.h"*/ +#include "webserver.h" +/*#include "dhcpc.h"*/ +/*#include "resolv.h"*/ +/*#include "webclient.h"*/ + +#endif /* __UIP_CONF_H__ */ + +/** @} */ +/** @} */ diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/webserver.h b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/webserver.h new file mode 100644 index 000000000..1acb290b8 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/RTOSDemo/webserver/webserver.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2002, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: webserver.h,v 1.2 2006/06/11 21:46:38 adam Exp $ + * + */ +#ifndef __WEBSERVER_H__ +#define __WEBSERVER_H__ + +#include "httpd.h" + +typedef struct httpd_state uip_tcp_appstate_t; +/* UIP_APPCALL: the name of the application function. This function + must return void and take no arguments (i.e., C type "void + appfunc(void)"). */ +#ifndef UIP_APPCALL +#define UIP_APPCALL httpd_appcall +#endif + + +#endif /* __WEBSERVER_H__ */ diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/SAM7_flash.cfg b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/SAM7_flash.cfg new file mode 100644 index 000000000..2fb93b3dd --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/SAM7_flash.cfg @@ -0,0 +1,30 @@ +#daemon configuration +telnet_port 4444 +gdb_port 3333 + +#interface +interface parport +parport_port 0x378 +parport_cable wiggler +jtag_speed 2 + +#use combined on interfaces or targets that can't set TRST/SRST separately +reset_config trst_and_srst srst_pulls_trst + +#jtag scan chain +#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) +jtag_device 4 0x1 0xf 0xe + +#target configuration +daemon_startup reset + +#target +#target arm7tdmi +target arm7tdmi little run_and_init 0 arm7tdmi +run_and_halt_time 0 30 +working_area 0 0x40000000 0x40000 nobackup + +#flash configuration +flash bank at91sam7 0 0 0 0 0 + +target_script 0 reset program.script diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/SAM7_pp.cfg b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/SAM7_pp.cfg new file mode 100644 index 000000000..3cb965fec --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/SAM7_pp.cfg @@ -0,0 +1,26 @@ +#daemon configuration +telnet_port 4444 +gdb_port 3333 + +#interface +interface parport +parport_port 0x378 +parport_cable wiggler +jtag_speed 2 +reset_config srst_only + +#jtag scan chain +#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) +jtag_device 4 0x1 0xf 0xe + +#target configuration +daemon_startup reset + +#target +#target arm7tdmi +target arm7tdmi little reset_halt 0 arm7tdmi +target_script 0 reset at91sam7_ecr.script +working_area 0 0x40000000 0x40000 nobackup + +#flash configuration +flash bank at91sam7 0 0 0 0 0 diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/at91sam7_ecr.cfg b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/at91sam7_ecr.cfg new file mode 100644 index 000000000..69a2d4d74 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/at91sam7_ecr.cfg @@ -0,0 +1,25 @@ +#daemon configuration +telnet_port 4444 +gdb_port 3333 + +#interface +interface at91rm9200 +at91rm9200_device rea_ecr +jtag_speed 0 +reset_config srst_only + +#jtag scan chain +#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) +jtag_device 4 0x1 0xf 0xe + +#target configuration +daemon_startup reset + +#target +#target arm7tdmi +target arm7tdmi little reset_halt 0 arm7tdmi +target_script 0 reset at91sam7_ecr.script +working_area 0 0x40000000 0x40000 nobackup + +#flash configuration +flash bank at91sam7 0 0 0 0 0 diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/at91sam7_ecr.script b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/at91sam7_ecr.script new file mode 100644 index 000000000..2d4738093 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/at91sam7_ecr.script @@ -0,0 +1,13 @@ +halt +wait_halt +sleep 10 +mww 0xfffffd44 0x00008000 # disable watchdog +mww 0xfffffd08 0xa5000001 # enable user reset +mww 0xfffffc20 0x00000601 # CKGR_MOR : enable the main oscillator +sleep 10 +mww 0xfffffc2c 0x12560a64 # CKGR_PLLR: 119.8MHz (DIV=100,MUL=598+1) +sleep 10 +mww 0xfffffc30 0x00000007 # PMC_MCKR : MCK = PLL / 2 = 59.9MHz +sleep 10 +mww 0xffffff60 0x003c0100 # MC_FMR: flash mode (FWS=1,FMCN=60) +arm7_9 force_hw_bkpts enable # program resides in flash diff --git a/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/program.script b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/program.script new file mode 100644 index 000000000..a60e13571 --- /dev/null +++ b/20080212/Demo/ARM7_AT91SAM7X256_Eclipse/program.script @@ -0,0 +1,11 @@ +arm7_9 dcc_downloads enable +halt +wait_halt +sleep 10 +poll +flash probe 0 +#flash protect 0 0 26 'off' +flash erase 0 0 15 +flash write 0 ./RTOSDemo/RTOSDemo.bin 0x0 +sleep 10 +shutdown diff --git a/20080212/Demo/ARM7_LPC2106_GCC/FreeRTOSConfig.h b/20080212/Demo/ARM7_LPC2106_GCC/FreeRTOSConfig.h new file mode 100644 index 000000000..291f442e0 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2106_GCC/FreeRTOSConfig.h @@ -0,0 +1,88 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include + + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 58982400 ) /* =14.7456MHz xtal multiplied by 4 using the PLL. */ +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 128 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 24 * 1024 ) ) +#define configMAX_TASK_NAME_LEN ( 16 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/ARM7_LPC2106_GCC/Makefile b/20080212/Demo/ARM7_LPC2106_GCC/Makefile new file mode 100644 index 000000000..d2aa49ccd --- /dev/null +++ b/20080212/Demo/ARM7_LPC2106_GCC/Makefile @@ -0,0 +1,118 @@ +# FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. +# +# This file is part of the FreeRTOS.org distribution. +# +# FreeRTOS.org is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# FreeRTOS.org is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with FreeRTOS.org; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +# +# A special exception to the GPL can be applied should you wish to distribute +# a combined work that includes FreeRTOS.org, without being obliged to provide +# the source code for any proprietary components. See the licensing section +# of http://www.FreeRTOS.org for full details of how and when the exception +# can be applied. +# +# *************************************************************************** +# See http://www.FreeRTOS.org for documentation, latest information, license +# and contact details. Please ensure to read the configuration and relevant +# port sections of the online documentation. +# *************************************************************************** + +# Changes from V2.4.2 +# +# + Replaced source/portable/gcc/arm7/portheap.c with source/portable/memmang/heap_2.c. + +CC=arm-elf-gcc +OBJCOPY=arm-elf-objcopy +ARCH=arm-elf-ar +CRT0=boot.s +WARNINGS=-Wall -Wextra -Wshadow -Wpointer-arith -Wbad-function-cast -Wcast-align -Wsign-compare \ + -Waggregate-return -Wstrict-prototypes -Wmissing-prototypes -Wmissing-declarations -Wunused + +# +# CFLAGS common to both the THUMB and ARM mode builds +# +CFLAGS=$(WARNINGS) -D $(RUN_MODE) -D GCC_ARM7 -I. -I../../Source/include \ + -I../Common/include $(DEBUG) -mcpu=arm7tdmi -T$(LDSCRIPT) \ + $(OPTIM) -fomit-frame-pointer + +ifeq ($(USE_THUMB_MODE),YES) + CFLAGS += -mthumb-interwork -D THUMB_INTERWORK + THUMB_FLAGS=-mthumb +endif + + +LINKER_FLAGS=-Xlinker -ortosdemo.elf -Xlinker -M -Xlinker -Map=rtosdemo.map + +RTOS_SOURCE_DIR=../../Source +DEMO_SOURCE_DIR=../Common/Minimal +# +# Source files that can be built to THUMB mode. +# +THUMB_SRC = \ +main.c \ +serial/serial.c \ +ParTest/ParTest.c \ +$(DEMO_SOURCE_DIR)/integer.c \ +$(DEMO_SOURCE_DIR)/flash.c \ +$(DEMO_SOURCE_DIR)/PollQ.c \ +$(DEMO_SOURCE_DIR)/comtest.c \ +$(DEMO_SOURCE_DIR)/flop.c \ +$(DEMO_SOURCE_DIR)/semtest.c \ +$(DEMO_SOURCE_DIR)/dynamic.c \ +$(DEMO_SOURCE_DIR)/BlockQ.c \ +$(RTOS_SOURCE_DIR)/tasks.c \ +$(RTOS_SOURCE_DIR)/queue.c \ +$(RTOS_SOURCE_DIR)/list.c \ +$(RTOS_SOURCE_DIR)/portable/MemMang/heap_2.c \ +$(RTOS_SOURCE_DIR)/portable/GCC/ARM7_LPC2000/port.c + +# +# Source files that must be built to ARM mode. +# +ARM_SRC = \ +$(RTOS_SOURCE_DIR)/portable/GCC/ARM7_LPC2000/portISR.c \ +serial/serialISR.c + +# +# Define all object files. +# +ARM_OBJ = $(ARM_SRC:.c=.o) +THUMB_OBJ = $(THUMB_SRC:.c=.o) + +rtosdemo.hex : rtosdemo.elf + $(OBJCOPY) rtosdemo.elf -O ihex rtosdemo.hex + +rtosdemo.elf : $(ARM_OBJ) $(THUMB_OBJ) $(CRT0) Makefile + $(CC) $(CFLAGS) $(ARM_OBJ) $(THUMB_OBJ) -nostartfiles $(CRT0) $(LINKER_FLAGS) + +$(THUMB_OBJ) : %.o : %.c $(LDSCRIPT) Makefile + $(CC) -c $(THUMB_FLAGS) $(CFLAGS) $< -o $@ + +$(ARM_OBJ) : %.o : %.c $(LDSCRIPT) Makefile + $(CC) -c $(CFLAGS) $< -o $@ + +clean : + touch Makefile + + + + + + + + + + + + diff --git a/20080212/Demo/ARM7_LPC2106_GCC/ParTest/ParTest.c b/20080212/Demo/ARM7_LPC2106_GCC/ParTest/ParTest.c new file mode 100644 index 000000000..56d069765 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2106_GCC/ParTest/ParTest.c @@ -0,0 +1,116 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + Changes from V2.5.2 + + + All LED's are turned off to start. +*/ + + +#include "FreeRTOS.h" +#include "partest.h" + +#define partstFIRST_IO ( ( unsigned portLONG ) 0x400 ) +#define partstNUM_LEDS ( 4 ) +#define partstALL_OUTPUTS_OFF ( ( unsigned portLONG ) 0xffffffff ) + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ + /* This is performed from main() as the io bits are shared with other setup + functions. */ + + /* Turn all outputs off. */ + GPIO_IOSET = partstALL_OUTPUTS_OFF; +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ +unsigned portLONG ulLED = partstFIRST_IO; + + if( uxLED < partstNUM_LEDS ) + { + /* Rotate to the wanted bit of port 0. Only P10 to P13 have an LED + attached. */ + ulLED <<= ( unsigned portLONG ) uxLED; + + /* Set of clear the output. */ + if( xValue ) + { + GPIO_IOCLR = ulLED; + } + else + { + GPIO_IOSET = ulLED; + } + } +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned portLONG ulLED = partstFIRST_IO, ulCurrentState; + + if( uxLED < partstNUM_LEDS ) + { + /* Rotate to the wanted bit of port 0. Only P10 to P13 have an LED + attached. */ + ulLED <<= ( unsigned portLONG ) uxLED; + + /* If this bit is already set, clear it, and visa versa. */ + ulCurrentState = GPIO0_IOPIN; + if( ulCurrentState & ulLED ) + { + GPIO_IOCLR = ulLED; + } + else + { + GPIO_IOSET = ulLED; + } + } +} + diff --git a/20080212/Demo/ARM7_LPC2106_GCC/boot.s b/20080212/Demo/ARM7_LPC2106_GCC/boot.s new file mode 100644 index 000000000..33e5226eb --- /dev/null +++ b/20080212/Demo/ARM7_LPC2106_GCC/boot.s @@ -0,0 +1,157 @@ + /* Sample initialization file */ + + .extern main + .extern exit + + .text + .code 32 + + + .align 0 + + .extern __bss_beg__ + .extern __bss_end__ + .extern __stack_end__ + .extern __data_beg__ + .extern __data_end__ + .extern __data+beg_src__ + + .global start + .global endless_loop + + /* Stack Sizes */ + .set UND_STACK_SIZE, 0x00000004 + .set ABT_STACK_SIZE, 0x00000004 + .set FIQ_STACK_SIZE, 0x00000004 + .set IRQ_STACK_SIZE, 0X00000400 + .set SVC_STACK_SIZE, 0x00000400 + + /* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */ + .set MODE_USR, 0x10 /* User Mode */ + .set MODE_FIQ, 0x11 /* FIQ Mode */ + .set MODE_IRQ, 0x12 /* IRQ Mode */ + .set MODE_SVC, 0x13 /* Supervisor Mode */ + .set MODE_ABT, 0x17 /* Abort Mode */ + .set MODE_UND, 0x1B /* Undefined Mode */ + .set MODE_SYS, 0x1F /* System Mode */ + + .equ I_BIT, 0x80 /* when I bit is set, IRQ is disabled */ + .equ F_BIT, 0x40 /* when F bit is set, FIQ is disabled */ + + +start: +_start: +_mainCRTStartup: + + /* Setup a stack for each mode - note that this only sets up a usable stack + for system/user, SWI and IRQ modes. Also each mode is setup with + interrupts initially disabled. */ + ldr r0, .LC6 + msr CPSR_c, #MODE_UND|I_BIT|F_BIT /* Undefined Instruction Mode + mov sp, r0 + sub r0, r0, #UND_STACK_SIZE + msr CPSR_c, #MODE_ABT|I_BIT|F_BIT /* Abort Mode */ + mov sp, r0 + sub r0, r0, #ABT_STACK_SIZE + msr CPSR_c, #MODE_FIQ|I_BIT|F_BIT /* FIQ Mode */ + mov sp, r0 + sub r0, r0, #FIQ_STACK_SIZE + msr CPSR_c, #MODE_IRQ|I_BIT|F_BIT /* IRQ Mode */ + mov sp, r0 + sub r0, r0, #IRQ_STACK_SIZE + msr CPSR_c, #MODE_SVC|I_BIT|F_BIT /* Supervisor Mode */ + mov sp, r0 + sub r0, r0, #SVC_STACK_SIZE + msr CPSR_c, #MODE_SYS|I_BIT|F_BIT /* System Mode */ + mov sp, r0 + + /* We want to start in supervisor mode. Operation will switch to system + mode when the first task starts. */ + msr CPSR_c, #MODE_SVC|I_BIT|F_BIT + + /* Clear BSS. */ + + mov a2, #0 /* Fill value */ + mov fp, a2 /* Null frame pointer */ + mov r7, a2 /* Null frame pointer for Thumb */ + + ldr r1, .LC1 /* Start of memory block */ + ldr r3, .LC2 /* End of memory block */ + subs r3, r3, r1 /* Length of block */ + beq .end_clear_loop + mov r2, #0 + +.clear_loop: + strb r2, [r1], #1 + subs r3, r3, #1 + bgt .clear_loop + +.end_clear_loop: + + /* Initialise data. */ + + ldr r1, .LC3 /* Start of memory block */ + ldr r2, .LC4 /* End of memory block */ + ldr r3, .LC5 + subs r3, r3, r1 /* Length of block */ + beq .end_set_loop + +.set_loop: + ldrb r4, [r2], #1 + strb r4, [r1], #1 + subs r3, r3, #1 + bgt .set_loop + +.end_set_loop: + + mov r0, #0 /* no arguments */ + mov r1, #0 /* no argv either */ + + bl main + +endless_loop: + b endless_loop + + + .align 0 + + .LC1: + .word __bss_beg__ + .LC2: + .word __bss_end__ + .LC3: + .word __data_beg__ + .LC4: + .word __data_beg_src__ + .LC5: + .word __data_end__ + .LC6: + .word __stack_end__ + + + /* Setup vector table. Note that undf, pabt, dabt, fiq just execute + a null loop. */ + +.section .startup,"ax" + .code 32 + .align 0 + + b _start /* reset - _start */ + ldr pc, _undf /* undefined - _undf */ + ldr pc, _swi /* SWI - _swi */ + ldr pc, _pabt /* program abort - _pabt */ + ldr pc, _dabt /* data abort - _dabt */ + nop /* reserved */ + ldr pc, [pc,#-0xFF0] /* IRQ - read the VIC */ + ldr pc, _fiq /* FIQ - _fiq */ + +_undf: .word __undf /* undefined */ +_swi: .word vPortYieldProcessor /* SWI */ +_pabt: .word __pabt /* program abort */ +_dabt: .word __dabt /* data abort */ +_fiq: .word __fiq /* FIQ */ + +__undf: b . /* undefined */ +__pabt: b . /* program abort */ +__dabt: b . /* data abort */ +__fiq: b . /* FIQ */ diff --git a/20080212/Demo/ARM7_LPC2106_GCC/lpc2106-ram.ld b/20080212/Demo/ARM7_LPC2106_GCC/lpc2106-ram.ld new file mode 100644 index 000000000..c54802c2f --- /dev/null +++ b/20080212/Demo/ARM7_LPC2106_GCC/lpc2106-ram.ld @@ -0,0 +1,49 @@ +MEMORY +{ + flash : ORIGIN = 0, LENGTH = 120K + ram : ORIGIN = 0x40000000, LENGTH = 64K +} + +__stack_end__ = 0x40000000 + 64K - 4; + +SECTIONS +{ + . = 0; + startup : { *(.startup)} >ram + + prog : + { + *(.text) + *(.rodata) + *(.rodata*) + *(.glue_7) + *(.glue_7t) + } >ram + + __end_of_text__ = .; + + .data : + { + __data_beg__ = .; + __data_beg_src__ = __end_of_text__; + *(.data) + __data_end__ = .; + } >ram + + .bss : + { + __bss_beg__ = .; + *(.bss) + } >ram + + /* Align here to ensure that the .bss section occupies space up to + _end. Align after .bss to ensure correct alignment even if the + .bss section disappears because there are no input sections. */ + . = ALIGN(32 / 8); +} + . = ALIGN(32 / 8); + _end = .; + _bss_end__ = . ; __bss_end__ = . ; __end__ = . ; + PROVIDE (end = .); + + diff --git a/20080212/Demo/ARM7_LPC2106_GCC/lpc2106-rom.ld b/20080212/Demo/ARM7_LPC2106_GCC/lpc2106-rom.ld new file mode 100644 index 000000000..e7cf25a22 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2106_GCC/lpc2106-rom.ld @@ -0,0 +1,49 @@ +MEMORY +{ + flash : ORIGIN = 0, LENGTH = 120K + ram : ORIGIN = 0x40000000, LENGTH = 64K +} + +__stack_end__ = 0x40000000 + 64K - 4; + +SECTIONS +{ + . = 0; + startup : { *(.startup)} >flash + + prog : + { + *(.text) + *(.rodata) + *(.rodata*) + *(.glue_7) + *(.glue_7t) + } >flash + + __end_of_text__ = .; + + .data : + { + __data_beg__ = .; + __data_beg_src__ = __end_of_text__; + *(.data) + __data_end__ = .; + } >ram AT>flash + + .bss : + { + __bss_beg__ = .; + *(.bss) + } >ram + + /* Align here to ensure that the .bss section occupies space up to + _end. Align after .bss to ensure correct alignment even if the + .bss section disappears because there are no input sections. */ + . = ALIGN(32 / 8); +} + . = ALIGN(32 / 8); + _end = .; + _bss_end__ = . ; __bss_end__ = . ; __end__ = . ; + PROVIDE (end = .); + + diff --git a/20080212/Demo/ARM7_LPC2106_GCC/lpc210x.h b/20080212/Demo/ARM7_LPC2106_GCC/lpc210x.h new file mode 100644 index 000000000..3f1e3042d --- /dev/null +++ b/20080212/Demo/ARM7_LPC2106_GCC/lpc210x.h @@ -0,0 +1,321 @@ +#ifndef lpc210x_h +#define lpc210x_h +/******************************************************************************* +lpc210x.h - Register defs for Philips LPC210X: LPC2104, LPC2105 and LPC2106 + + +THE SOFTWARE IS DELIVERED "AS IS" WITHOUT WARRANTY OR CONDITION OF ANY KIND, +EITHER EXPRESS, IMPLIED OR STATUTORY. THIS INCLUDES WITHOUT LIMITATION ANY +WARRANTY OR CONDITION WITH RESPECT TO MERCHANTABILITY OR FITNESS FOR ANY +PARTICULAR PURPOSE, OR AGAINST THE INFRINGEMENTS OF INTELLECTUAL PROPERTY RIGHTS +OF OTHERS. + +This file may be freely used for commercial and non-commercial applications, +including being redistributed with any tools. + +If you find a problem with the file, please report it so that it can be fixed. + +Created by Sten Larsson (sten_larsson at yahoo com) + +Edited by Richard Barry. +*******************************************************************************/ + +#define REG8 (volatile unsigned char*) +#define REG16 (volatile unsigned short*) +#define REG32 (volatile unsigned int*) + + +/*############################################################################## +## MISC +##############################################################################*/ + + /* Constants for data to put in IRQ/FIQ Exception Vectors */ +#define VECTDATA_IRQ 0xE51FFFF0 /* LDR PC,[PC,#-0xFF0] */ +#define VECTDATA_FIQ /* __TODO */ + + +/*############################################################################## +## VECTORED INTERRUPT CONTROLLER +##############################################################################*/ + +#define VICIRQStatus (*(REG32 (0xFFFFF000))) +#define VICFIQStatus (*(REG32 (0xFFFFF004))) +#define VICRawIntr (*(REG32 (0xFFFFF008))) +#define VICIntSelect (*(REG32 (0xFFFFF00C))) +#define VICIntEnable (*(REG32 (0xFFFFF010))) +#define VICIntEnClear (*(REG32 (0xFFFFF014))) +#define VICSoftInt (*(REG32 (0xFFFFF018))) +#define VICSoftIntClear (*(REG32 (0xFFFFF01C))) +#define VICProtection (*(REG32 (0xFFFFF020))) +#define VICVectAddr (*(REG32 (0xFFFFF030))) +#define VICDefVectAddr (*(REG32 (0xFFFFF034))) + +#define VICVectAddr0 (*(REG32 (0xFFFFF100))) +#define VICVectAddr1 (*(REG32 (0xFFFFF104))) +#define VICVectAddr2 (*(REG32 (0xFFFFF108))) +#define VICVectAddr3 (*(REG32 (0xFFFFF10C))) +#define VICVectAddr4 (*(REG32 (0xFFFFF110))) +#define VICVectAddr5 (*(REG32 (0xFFFFF114))) +#define VICVectAddr6 (*(REG32 (0xFFFFF118))) +#define VICVectAddr7 (*(REG32 (0xFFFFF11C))) +#define VICVectAddr8 (*(REG32 (0xFFFFF120))) +#define VICVectAddr9 (*(REG32 (0xFFFFF124))) +#define VICVectAddr10 (*(REG32 (0xFFFFF128))) +#define VICVectAddr11 (*(REG32 (0xFFFFF12C))) +#define VICVectAddr12 (*(REG32 (0xFFFFF130))) +#define VICVectAddr13 (*(REG32 (0xFFFFF134))) +#define VICVectAddr14 (*(REG32 (0xFFFFF138))) +#define VICVectAddr15 (*(REG32 (0xFFFFF13C))) + +#define VICVectCntl0 (*(REG32 (0xFFFFF200))) +#define VICVectCntl1 (*(REG32 (0xFFFFF204))) +#define VICVectCntl2 (*(REG32 (0xFFFFF208))) +#define VICVectCntl3 (*(REG32 (0xFFFFF20C))) +#define VICVectCntl4 (*(REG32 (0xFFFFF210))) +#define VICVectCntl5 (*(REG32 (0xFFFFF214))) +#define VICVectCntl6 (*(REG32 (0xFFFFF218))) +#define VICVectCntl7 (*(REG32 (0xFFFFF21C))) +#define VICVectCntl8 (*(REG32 (0xFFFFF220))) +#define VICVectCntl9 (*(REG32 (0xFFFFF224))) +#define VICVectCntl10 (*(REG32 (0xFFFFF228))) +#define VICVectCntl11 (*(REG32 (0xFFFFF22C))) +#define VICVectCntl12 (*(REG32 (0xFFFFF230))) +#define VICVectCntl13 (*(REG32 (0xFFFFF234))) +#define VICVectCntl14 (*(REG32 (0xFFFFF238))) +#define VICVectCntl15 (*(REG32 (0xFFFFF23C))) + +#define VICITCR (*(REG32 (0xFFFFF300))) +#define VICITIP1 (*(REG32 (0xFFFFF304))) +#define VICITIP2 (*(REG32 (0xFFFFF308))) +#define VICITOP1 (*(REG32 (0xFFFFF30C))) +#define VICITOP2 (*(REG32 (0xFFFFF310))) +#define VICPeriphID0 (*(REG32 (0xFFFFFFE0))) +#define VICPeriphID1 (*(REG32 (0xFFFFFFE4))) +#define VICPeriphID2 (*(REG32 (0xFFFFFFE8))) +#define VICPeriphID3 (*(REG32 (0xFFFFFFEC))) + +#define VICIntEnClr VICIntEnClear +#define VICSoftIntClr VICSoftIntClear + + +/*############################################################################## +## PCB - Pin Connect Block +##############################################################################*/ + +#define PCB_PINSEL0 (*(REG32 (0xE002C000))) +#define PCB_PINSEL1 (*(REG32 (0xE002C004))) + + +/*############################################################################## +## GPIO - General Purpose I/O +##############################################################################*/ + +#define GPIO_IOPIN (*(REG32 (0xE0028000))) /* ALTERNATE NAME GPIO = GPIO0 */ +#define GPIO_IOSET (*(REG32 (0xE0028004))) +#define GPIO_IODIR (*(REG32 (0xE0028008))) +#define GPIO_IOCLR (*(REG32 (0xE002800C))) + +#define GPIO0_IOPIN (*(REG32 (0xE0028000))) /* ALTERNATE NAME GPIO = GPIO0 */ +#define GPIO0_IOSET (*(REG32 (0xE0028004))) +#define GPIO0_IODIR (*(REG32 (0xE0028008))) +#define GPIO0_IOCLR (*(REG32 (0xE002800C))) + + +/*############################################################################## +## UART0 / UART1 +##############################################################################*/ + +/* ---- UART 0 --------------------------------------------- */ +#define UART0_RBR (*(REG32 (0xE000C000))) +#define UART0_THR (*(REG32 (0xE000C000))) +#define UART0_IER (*(REG32 (0xE000C004))) +#define UART0_IIR (*(REG32 (0xE000C008))) +#define UART0_FCR (*(REG32 (0xE000C008))) +#define UART0_LCR (*(REG32 (0xE000C00C))) +#define UART0_LSR (*(REG32 (0xE000C014))) +#define UART0_SCR (*(REG32 (0xE000C01C))) +#define UART0_DLL (*(REG32 (0xE000C000))) +#define UART0_DLM (*(REG32 (0xE000C004))) + +/* ---- UART 1 --------------------------------------------- */ +#define UART1_RBR (*(REG32 (0xE0010000))) +#define UART1_THR (*(REG32 (0xE0010000))) +#define UART1_IER (*(REG32 (0xE0010004))) +#define UART1_IIR (*(REG32 (0xE0010008))) +#define UART1_FCR (*(REG32 (0xE0010008))) +#define UART1_LCR (*(REG32 (0xE001000C))) +#define UART1_LSR (*(REG32 (0xE0010014))) +#define UART1_SCR (*(REG32 (0xE001001C))) +#define UART1_DLL (*(REG32 (0xE0010000))) +#define UART1_DLM (*(REG32 (0xE0010004))) +#define UART1_MCR (*(REG32 (0xE0010010))) +#define UART1_MSR (*(REG32 (0xE0010018))) + + +/*############################################################################## +## I2C +##############################################################################*/ + +#define I2C_I2CONSET (*(REG32 (0xE001C000))) +#define I2C_I2STAT (*(REG32 (0xE001C004))) +#define I2C_I2DAT (*(REG32 (0xE001C008))) +#define I2C_I2ADR (*(REG32 (0xE001C00C))) +#define I2C_I2SCLH (*(REG32 (0xE001C010))) +#define I2C_I2SCLL (*(REG32 (0xE001C014))) +#define I2C_I2CONCLR (*(REG32 (0xE001C018))) + + +/*############################################################################## +## SPI - Serial Peripheral Interface +##############################################################################*/ + +#define SPI_SPCR (*(REG32 (0xE0020000))) +#define SPI_SPSR (*(REG32 (0xE0020004))) +#define SPI_SPDR (*(REG32 (0xE0020008))) +#define SPI_SPCCR (*(REG32 (0xE002000C))) +#define SPI_SPTCR (*(REG32 (0xE0020010))) +#define SPI_SPTSR (*(REG32 (0xE0020014))) +#define SPI_SPTOR (*(REG32 (0xE0020018))) +#define SPI_SPINT (*(REG32 (0xE002001C))) + + +/*############################################################################## +## Timer 0 and Timer 1 +##############################################################################*/ + +/* ---- Timer 0 -------------------------------------------- */ +#define T0_IR (*(REG32 (0xE0004000))) +#define T0_TCR (*(REG32 (0xE0004004))) +#define T0_TC (*(REG32 (0xE0004008))) +#define T0_PR (*(REG32 (0xE000400C))) +#define T0_PC (*(REG32 (0xE0004010))) +#define T0_MCR (*(REG32 (0xE0004014))) +#define T0_MR0 (*(REG32 (0xE0004018))) +#define T0_MR1 (*(REG32 (0xE000401C))) +#define T0_MR2 (*(REG32 (0xE0004020))) +#define T0_MR3 (*(REG32 (0xE0004024))) +#define T0_CCR (*(REG32 (0xE0004028))) +#define T0_CR0 (*(REG32 (0xE000402C))) +#define T0_CR1 (*(REG32 (0xE0004030))) +#define T0_CR2 (*(REG32 (0xE0004034))) +#define T0_CR3 (*(REG32 (0xE0004038))) +#define T0_EMR (*(REG32 (0xE000403C))) + +/* ---- Timer 1 -------------------------------------------- */ +#define T1_IR (*(REG32 (0xE0008000))) +#define T1_TCR (*(REG32 (0xE0008004))) +#define T1_TC (*(REG32 (0xE0008008))) +#define T1_PR (*(REG32 (0xE000800C))) +#define T1_PC (*(REG32 (0xE0008010))) +#define T1_MCR (*(REG32 (0xE0008014))) +#define T1_MR0 (*(REG32 (0xE0008018))) +#define T1_MR1 (*(REG32 (0xE000801C))) +#define T1_MR2 (*(REG32 (0xE0008020))) +#define T1_MR3 (*(REG32 (0xE0008024))) +#define T1_CCR (*(REG32 (0xE0008028))) +#define T1_CR0 (*(REG32 (0xE000802C))) +#define T1_CR1 (*(REG32 (0xE0008030))) +#define T1_CR2 (*(REG32 (0xE0008034))) +#define T1_CR3 (*(REG32 (0xE0008038))) +#define T1_EMR (*(REG32 (0xE000803C))) + + +/*############################################################################## +## PWM +##############################################################################*/ + +#define PWM_IR (*(REG32 (0xE0014000))) +#define PWM_TCR (*(REG32 (0xE0014004))) +#define PWM_TC (*(REG32 (0xE0014008))) +#define PWM_PR (*(REG32 (0xE001400C))) +#define PWM_PC (*(REG32 (0xE0014010))) +#define PWM_MCR (*(REG32 (0xE0014014))) +#define PWM_MR0 (*(REG32 (0xE0014018))) +#define PWM_MR1 (*(REG32 (0xE001401C))) +#define PWM_MR2 (*(REG32 (0xE0014020))) +#define PWM_MR3 (*(REG32 (0xE0014024))) +#define PWM_MR4 (*(REG32 (0xE0014040))) +#define PWM_MR5 (*(REG32 (0xE0014044))) +#define PWM_MR6 (*(REG32 (0xE0014048))) +#define PWM_EMR (*(REG32 (0xE001403C))) +#define PWM_PCR (*(REG32 (0xE001404C))) +#define PWM_LER (*(REG32 (0xE0014050))) +#define PWM_CCR (*(REG32 (0xE0014028))) +#define PWM_CR0 (*(REG32 (0xE001402C))) +#define PWM_CR1 (*(REG32 (0xE0014030))) +#define PWM_CR2 (*(REG32 (0xE0014034))) +#define PWM_CR3 (*(REG32 (0xE0014038))) + +/*############################################################################## +## RTC +##############################################################################*/ + +/* ---- RTC: Miscellaneous Register Group ------------------ */ +#define RTC_ILR (*(REG32 (0xE0024000))) +#define RTC_CTC (*(REG32 (0xE0024004))) +#define RTC_CCR (*(REG32 (0xE0024008))) +#define RTC_CIIR (*(REG32 (0xE002400C))) +#define RTC_AMR (*(REG32 (0xE0024010))) +#define RTC_CTIME0 (*(REG32 (0xE0024014))) +#define RTC_CTIME1 (*(REG32 (0xE0024018))) +#define RTC_CTIME2 (*(REG32 (0xE002401C))) + +/* ---- RTC: Timer Control Group --------------------------- */ +#define RTC_SEC (*(REG32 (0xE0024020))) +#define RTC_MIN (*(REG32 (0xE0024024))) +#define RTC_HOUR (*(REG32 (0xE0024028))) +#define RTC_DOM (*(REG32 (0xE002402C))) +#define RTC_DOW (*(REG32 (0xE0024030))) +#define RTC_DOY (*(REG32 (0xE0024034))) +#define RTC_MONTH (*(REG32 (0xE0024038))) +#define RTC_YEAR (*(REG32 (0xE002403C))) + +/* ---- RTC: Alarm Control Group --------------------------- */ +#define RTC_ALSEC (*(REG32 (0xE0024060))) +#define RTC_ALMIN (*(REG32 (0xE0024064))) +#define RTC_ALHOUR (*(REG32 (0xE0024068))) +#define RTC_ALDOM (*(REG32 (0xE002406C))) +#define RTC_ALDOW (*(REG32 (0xE0024070))) +#define RTC_ALDOY (*(REG32 (0xE0024074))) +#define RTC_ALMON (*(REG32 (0xE0024078))) +#define RTC_ALYEAR (*(REG32 (0xE002407C))) + +/* ---- RTC: Reference Clock Divider Group ----------------- */ +#define RTC_PREINT (*(REG32 (0xE0024080))) +#define RTC_PREFRAC (*(REG32 (0xE0024084))) + + +/*############################################################################## +## WD - Watchdog +##############################################################################*/ + +#define WD_WDMOD (*(REG32 (0xE0000000))) +#define WD_WDTC (*(REG32 (0xE0000004))) +#define WD_WDFEED (*(REG32 (0xE0000008))) +#define WD_WDTV (*(REG32 (0xE000000C))) + + +/*############################################################################## +## System Control Block +##############################################################################*/ + +#define SCB_EXTINT (*(REG32 (0xE01FC140))) +#define SCB_EXTWAKE (*(REG32 (0xE01FC144))) +#define SCB_MEMMAP (*(REG32 (0xE01FC040))) +#define SCB_PLLCON (*(REG32 (0xE01FC080))) +#define SCB_PLLCFG (*(REG32 (0xE01FC084))) +#define SCB_PLLSTAT (*(REG32 (0xE01FC088))) +#define SCB_PLLFEED (*(REG32 (0xE01FC08C))) +#define SCB_PCON (*(REG32 (0xE01FC0C0))) +#define SCB_PCONP (*(REG32 (0xE01FC0C4))) +#define SCB_VPBDIV (*(REG32 (0xE01FC100))) + +/*############################################################################## +## Memory Accelerator Module (MAM) +##############################################################################*/ + +#define MAM_TIM (*(REG32 (0xE01FC004))) +#define MAM_CR (*(REG32 (0xE01FC000))) + +#endif /* lpc210x_h */ + diff --git a/20080212/Demo/ARM7_LPC2106_GCC/lpc221x.h b/20080212/Demo/ARM7_LPC2106_GCC/lpc221x.h new file mode 100644 index 000000000..170bb435f --- /dev/null +++ b/20080212/Demo/ARM7_LPC2106_GCC/lpc221x.h @@ -0,0 +1 @@ +#include "lpc2114.h" \ No newline at end of file diff --git a/20080212/Demo/ARM7_LPC2106_GCC/main.c b/20080212/Demo/ARM7_LPC2106_GCC/main.c new file mode 100644 index 000000000..e01ffa68a --- /dev/null +++ b/20080212/Demo/ARM7_LPC2106_GCC/main.c @@ -0,0 +1,485 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. + The processor MUST be in supervisor mode when vTaskStartScheduler is + called. The demo applications included in the FreeRTOS.org download switch + to supervisor mode prior to main being called. If you are not using one of + these demo application projects then ensure Supervisor mode is used. +*/ + + +/* + * Creates all the demo application tasks, then starts the scheduler. The WEB + * documentation provides more details of the demo application tasks. + * + * Main.c also creates a task called "Check". This only executes every three + * seconds but has the highest priority so is guaranteed to get processor time. + * Its main function is to check that all the other tasks are still operational. + * Each task (other than the "flash" tasks) maintains a unique count that is + * incremented each time the task successfully completes its function. Should + * any error occur within such a task the count is permanently halted. The + * check task inspects the count of each task to ensure it has changed since + * the last time the check task executed. If all the count variables have + * changed all the tasks are still executing error free, and the check task + * toggles the onboard LED. Should any task contain an error at any time + * the LED toggle rate will change from 3 seconds to 500ms. + * + * To check the operation of the memory allocator the check task also + * dynamically creates a task before delaying, and deletes it again when it + * wakes. If memory cannot be allocated for the new task the call to xTaskCreate + * will fail and an error is signalled. The dynamically created task itself + * allocates and frees memory just to give the allocator a bit more exercise. + * + */ + +/* + Changes from V2.4.2 + + + The vErrorChecks() task now dynamically creates then deletes a task each + cycle. This tests the operation of the memory allocator. + + Changes from V2.5.2 + + + vParTestInitialise() is called during initialisation to ensure all the + LED's start off. +*/ + + +/* Standard includes. */ +#include +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo application includes. */ +#include "partest.h" +#include "flash.h" +#include "integer.h" +#include "PollQ.h" +#include "comtest2.h" +#include "semtest.h" +#include "flop.h" +#include "dynamic.h" +#include "BlockQ.h" +#include "serial.h" + +/*-----------------------------------------------------------*/ + +/* Constants to setup I/O. */ +#define mainTX_ENABLE ( ( unsigned portLONG ) 0x0001 ) +#define mainRX_ENABLE ( ( unsigned portLONG ) 0x0004 ) +#define mainP0_14 ( ( unsigned portLONG ) 0x4000 ) +#define mainJTAG_PORT ( ( unsigned portLONG ) 0x3E0000UL ) + +/* Constants to setup the PLL. */ +#define mainPLL_MUL_4 ( ( unsigned portCHAR ) 0x0003 ) +#define mainPLL_DIV_1 ( ( unsigned portCHAR ) 0x0000 ) +#define mainPLL_ENABLE ( ( unsigned portCHAR ) 0x0001 ) +#define mainPLL_CONNECT ( ( unsigned portCHAR ) 0x0003 ) +#define mainPLL_FEED_BYTE1 ( ( unsigned portCHAR ) 0xaa ) +#define mainPLL_FEED_BYTE2 ( ( unsigned portCHAR ) 0x55 ) +#define mainPLL_LOCK ( ( unsigned portLONG ) 0x0400 ) + +/* Constants to setup the MAM. */ +#define mainMAM_TIM_3 ( ( unsigned portCHAR ) 0x03 ) +#define mainMAM_MODE_FULL ( ( unsigned portCHAR ) 0x02 ) + +/* Constants to setup the peripheral bus. */ +#define mainBUS_CLK_FULL ( ( unsigned portCHAR ) 0x01 ) + +/* Constants for the ComTest tasks. */ +#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 115200 ) +#define mainCOM_TEST_LED ( 3 ) + +/* Priorities for the demo application tasks. */ +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 0 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 0 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) + +/* The rate at which the on board LED will toggle when there is/is not an +error. */ +#define mainNO_ERROR_FLASH_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS ) +#define mainERROR_FLASH_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS ) +#define mainON_BOARD_LED_BIT ( ( unsigned portLONG ) 0x80 ) + +/* Constants used by the vMemCheckTask() task. */ +#define mainCOUNT_INITIAL_VALUE ( ( unsigned portLONG ) 0 ) +#define mainNO_TASK ( 0 ) + +/* The size of the memory blocks allocated by the vMemCheckTask() task. */ +#define mainMEM_CHECK_SIZE_1 ( ( size_t ) 51 ) +#define mainMEM_CHECK_SIZE_2 ( ( size_t ) 52 ) +#define mainMEM_CHECK_SIZE_3 ( ( size_t ) 151 ) + +/*-----------------------------------------------------------*/ + +/* + * The Olimex demo board has a single built in LED. This function simply + * toggles its state. + */ +void prvToggleOnBoardLED( void ); + +/* + * Checks that all the demo application tasks are still executing without error + * - as described at the top of the file. + */ +static portLONG prvCheckOtherTasksAreStillRunning( unsigned portLONG ulMemCheckTaskCount ); + +/* + * The task that executes at the highest priority and calls + * prvCheckOtherTasksAreStillRunning(). See the description at the top + * of the file. + */ +static void vErrorChecks( void *pvParameters ); + +/* + * Dynamically created and deleted during each cycle of the vErrorChecks() + * task. This is done to check the operation of the memory allocator. + * See the top of vErrorChecks for more details. + */ +static void vMemCheckTask( void *pvParameters ); + +/* + * Configure the processor for use with the Olimex demo board. This includes + * setup for the I/O, system clock, and access timings. + */ +static void prvSetupHardware( void ); + +/*-----------------------------------------------------------*/ + +/* + * Starts all the other tasks, then starts the scheduler. + */ +int main( void ) +{ + /* Setup the hardware for use with the Olimex demo board. */ + prvSetupHardware(); + + /* Start the demo/test application tasks. */ + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); + vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartMathTasks( tskIDLE_PRIORITY ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartDynamicPriorityTasks(); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + + /* Start the check task - which is defined in this file. */ + xTaskCreate( vErrorChecks, ( signed portCHAR * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Now all the tasks have been started - start the scheduler. + + NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. + The processor MUST be in supervisor mode when vTaskStartScheduler is + called. The demo applications included in the FreeRTOS.org download switch + to supervisor mode prior to main being called. If you are not using one of + these demo application projects then ensure Supervisor mode is used here. */ + vTaskStartScheduler(); + + /* Should never reach here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +static void vErrorChecks( void *pvParameters ) +{ +portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD; +unsigned portLONG ulMemCheckTaskRunningCount; +xTaskHandle xCreatedTask; + + /* The parameters are not used in this function. */ + ( void ) pvParameters; + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. If an error is detected then the delay period + is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so + the on board LED flash rate will increase. + + In addition to the standard tests the memory allocator is tested through + the dynamic creation and deletion of a task each cycle. Each time the + task is created memory must be allocated for its stack. When the task is + deleted this memory is returned to the heap. If the task cannot be created + then it is likely that the memory allocation failed. */ + + for( ;; ) + { + /* Dynamically create a task - passing ulMemCheckTaskRunningCount as a + parameter. */ + ulMemCheckTaskRunningCount = mainCOUNT_INITIAL_VALUE; + xCreatedTask = mainNO_TASK; + + if( xTaskCreate( vMemCheckTask, ( signed portCHAR * ) "MEM_CHECK", configMINIMAL_STACK_SIZE, ( void * ) &ulMemCheckTaskRunningCount, tskIDLE_PRIORITY, &xCreatedTask ) != pdPASS ) + { + /* Could not create the task - we have probably run out of heap. */ + xDelayPeriod = mainERROR_FLASH_PERIOD; + } + + /* Delay until it is time to execute again. */ + vTaskDelay( xDelayPeriod ); + + /* Delete the dynamically created task. */ + if( xCreatedTask != mainNO_TASK ) + { + vTaskDelete( xCreatedTask ); + } + + /* Check all the standard demo application tasks are executing without + error. ulMemCheckTaskRunningCount is checked to ensure it was + modified by the task just deleted. */ + if( prvCheckOtherTasksAreStillRunning( ulMemCheckTaskRunningCount ) != pdPASS ) + { + /* An error has been detected in one of the tasks - flash faster. */ + xDelayPeriod = mainERROR_FLASH_PERIOD; + } + + prvToggleOnBoardLED(); + } +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + #ifdef RUN_FROM_RAM + /* Remap the interrupt vectors to RAM if we are are running from RAM. */ + SCB_MEMMAP = 2; + #endif + + /* Configure the RS2332 pins. All other pins remain at their default of 0. */ + PCB_PINSEL0 |= mainTX_ENABLE; + PCB_PINSEL0 |= mainRX_ENABLE; + + /* Set all GPIO to output other than the P0.14 (BSL), and the JTAG pins. + The JTAG pins are left as input as I'm not sure what will happen if the + Wiggler is connected after powerup - not that it would be a good idea to + do that anyway. */ + GPIO_IODIR = ~( mainP0_14 + mainJTAG_PORT ); + + /* Setup the PLL to multiply the XTAL input by 4. */ + SCB_PLLCFG = ( mainPLL_MUL_4 | mainPLL_DIV_1 ); + + /* Activate the PLL by turning it on then feeding the correct sequence of + bytes. */ + SCB_PLLCON = mainPLL_ENABLE; + SCB_PLLFEED = mainPLL_FEED_BYTE1; + SCB_PLLFEED = mainPLL_FEED_BYTE2; + + /* Wait for the PLL to lock... */ + while( !( SCB_PLLSTAT & mainPLL_LOCK ) ); + + /* ...before connecting it using the feed sequence again. */ + SCB_PLLCON = mainPLL_CONNECT; + SCB_PLLFEED = mainPLL_FEED_BYTE1; + SCB_PLLFEED = mainPLL_FEED_BYTE2; + + /* Setup and turn on the MAM. Three cycle access is used due to the fast + PLL used. It is possible faster overall performance could be obtained by + tuning the MAM and PLL settings. */ + MAM_TIM = mainMAM_TIM_3; + MAM_CR = mainMAM_MODE_FULL; + + /* Setup the peripheral bus to be the same as the PLL output. */ + SCB_VPBDIV = mainBUS_CLK_FULL; + + /* Initialise LED outputs. */ + vParTestInitialise(); +} +/*-----------------------------------------------------------*/ + +void prvToggleOnBoardLED( void ) +{ +unsigned portLONG ulState; + + ulState = GPIO0_IOPIN; + if( ulState & mainON_BOARD_LED_BIT ) + { + GPIO_IOCLR = mainON_BOARD_LED_BIT; + } + else + { + GPIO_IOSET = mainON_BOARD_LED_BIT; + } +} +/*-----------------------------------------------------------*/ + +static portLONG prvCheckOtherTasksAreStillRunning( unsigned portLONG ulMemCheckTaskCount ) +{ +portLONG lReturn = ( portLONG ) pdPASS; + + /* Check all the demo tasks (other than the flash tasks) to ensure + that they are all still running, and that none of them have detected + an error. */ + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreMathsTaskStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( ulMemCheckTaskCount == mainCOUNT_INITIAL_VALUE ) + { + /* The vMemCheckTask did not increment the counter - it must + have failed. */ + lReturn = ( portLONG ) pdFAIL; + } + + return lReturn; +} +/*-----------------------------------------------------------*/ + +static void vMemCheckTask( void *pvParameters ) +{ +unsigned portLONG *pulMemCheckTaskRunningCounter; +void *pvMem1, *pvMem2, *pvMem3; +static portLONG lErrorOccurred = pdFALSE; + + /* This task is dynamically created then deleted during each cycle of the + vErrorChecks task to check the operation of the memory allocator. Each time + the task is created memory is allocated for the stack and TCB. Each time + the task is deleted this memory is returned to the heap. This task itself + exercises the allocator by allocating and freeing blocks. + + The task executes at the idle priority so does not require a delay. + + pulMemCheckTaskRunningCounter is incremented each cycle to indicate to the + vErrorChecks() task that this task is still executing without error. */ + + pulMemCheckTaskRunningCounter = ( unsigned portLONG * ) pvParameters; + + for( ;; ) + { + if( lErrorOccurred == pdFALSE ) + { + /* We have never seen an error so increment the counter. */ + ( *pulMemCheckTaskRunningCounter )++; + } + + /* Allocate some memory - just to give the allocator some extra + exercise. This has to be in a critical section to ensure the + task does not get deleted while it has memory allocated. */ + vTaskSuspendAll(); + { + pvMem1 = pvPortMalloc( mainMEM_CHECK_SIZE_1 ); + if( pvMem1 == NULL ) + { + lErrorOccurred = pdTRUE; + } + else + { + memset( pvMem1, 0xaa, mainMEM_CHECK_SIZE_1 ); + vPortFree( pvMem1 ); + } + } + xTaskResumeAll(); + + /* Again - with a different size block. */ + vTaskSuspendAll(); + { + pvMem2 = pvPortMalloc( mainMEM_CHECK_SIZE_2 ); + if( pvMem2 == NULL ) + { + lErrorOccurred = pdTRUE; + } + else + { + memset( pvMem2, 0xaa, mainMEM_CHECK_SIZE_2 ); + vPortFree( pvMem2 ); + } + } + xTaskResumeAll(); + + /* Again - with a different size block. */ + vTaskSuspendAll(); + { + pvMem3 = pvPortMalloc( mainMEM_CHECK_SIZE_3 ); + if( pvMem3 == NULL ) + { + lErrorOccurred = pdTRUE; + } + else + { + memset( pvMem3, 0xaa, mainMEM_CHECK_SIZE_3 ); + vPortFree( pvMem3 ); + } + } + xTaskResumeAll(); + } +} + + + diff --git a/20080212/Demo/ARM7_LPC2106_GCC/ram_arm.bat b/20080212/Demo/ARM7_LPC2106_GCC/ram_arm.bat new file mode 100644 index 000000000..1f3c5da0a --- /dev/null +++ b/20080212/Demo/ARM7_LPC2106_GCC/ram_arm.bat @@ -0,0 +1,6 @@ +set USE_THUMB_MODE=NO +set DEBUG=-g +set OPTIM=-O0 +set RUN_MODE=RUN_FROM_RAM +set LDSCRIPT=lpc2106-ram.ld +make diff --git a/20080212/Demo/ARM7_LPC2106_GCC/ram_thumb.bat b/20080212/Demo/ARM7_LPC2106_GCC/ram_thumb.bat new file mode 100644 index 000000000..414a3a6b6 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2106_GCC/ram_thumb.bat @@ -0,0 +1,6 @@ +set USE_THUMB_MODE=YES +set DEBUG=-g +set OPTIM=-O0 +set RUN_MODE=RUN_FROM_RAM +set LDSCRIPT=lpc2106-ram.ld +make diff --git a/20080212/Demo/ARM7_LPC2106_GCC/readme.txt b/20080212/Demo/ARM7_LPC2106_GCC/readme.txt new file mode 100644 index 000000000..af4856965 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2106_GCC/readme.txt @@ -0,0 +1,18 @@ +Use one of the following four batch files to build the demo application: + ++ rom_arm.bat + +Creates an ARM mode release build suitable for programming into flash. + ++ ram_arm.bat + +Creates an ARM mode debug build suitable for running from RAM. + ++ rom_thumb.bat + +Creates a THUMB mode release build suitable for programming into flash. + ++ ram_thumb.bat + +Creates a THUMB mode debug build suitable for running from RAM. + diff --git a/20080212/Demo/ARM7_LPC2106_GCC/rom_arm.bat b/20080212/Demo/ARM7_LPC2106_GCC/rom_arm.bat new file mode 100644 index 000000000..7f7d88333 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2106_GCC/rom_arm.bat @@ -0,0 +1,6 @@ +set USE_THUMB_MODE=NO +set DEBUG= +set OPTIM=-O3 +set RUN_MODE=RUN_FROM_ROM +set LDSCRIPT=lpc2106-rom.ld +make diff --git a/20080212/Demo/ARM7_LPC2106_GCC/rom_thumb.bat b/20080212/Demo/ARM7_LPC2106_GCC/rom_thumb.bat new file mode 100644 index 000000000..ea9920402 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2106_GCC/rom_thumb.bat @@ -0,0 +1,6 @@ +set USE_THUMB_MODE=YES +set DEBUG= +set OPTIM=-O3 +set RUN_MODE=RUN_FROM_ROM +set LDSCRIPT=lpc2106-rom.ld +make diff --git a/20080212/Demo/ARM7_LPC2106_GCC/serial/serial.c b/20080212/Demo/ARM7_LPC2106_GCC/serial/serial.c new file mode 100644 index 000000000..15dca4ed1 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2106_GCC/serial/serial.c @@ -0,0 +1,273 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + Changes from V2.4.0 + + + Made serial ISR handling more complete and robust. + + Changes from V2.4.1 + + + Split serial.c into serial.c and serialISR.c. serial.c can be + compiled using ARM or THUMB modes. serialISR.c must always be + compiled in ARM mode. + + Another small change to cSerialPutChar(). + + Changed from V2.5.1 + + + In cSerialPutChar() an extra check is made to ensure the post to + the queue was successful if then attempting to retrieve the posted + character. + +*/ + +/* + BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0. + + This file contains all the serial port components that can be compiled to + either ARM or THUMB mode. Components that must be compiled to ARM mode are + contained in serialISR.c. +*/ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "queue.h" +#include "task.h" + +/* Demo application includes. */ +#include "serial.h" + +/*-----------------------------------------------------------*/ + +/* Constants to setup and access the UART. */ +#define serDLAB ( ( unsigned portCHAR ) 0x80 ) +#define serENABLE_INTERRUPTS ( ( unsigned portCHAR ) 0x03 ) +#define serNO_PARITY ( ( unsigned portCHAR ) 0x00 ) +#define ser1_STOP_BIT ( ( unsigned portCHAR ) 0x00 ) +#define ser8_BIT_CHARS ( ( unsigned portCHAR ) 0x03 ) +#define serFIFO_ON ( ( unsigned portCHAR ) 0x01 ) +#define serCLEAR_FIFO ( ( unsigned portCHAR ) 0x06 ) +#define serWANTED_CLOCK_SCALING ( ( unsigned portLONG ) 16 ) + +/* Constants to setup and access the VIC. */ +#define serUART0_VIC_CHANNEL ( ( unsigned portLONG ) 0x0006 ) +#define serUART0_VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x0040 ) +#define serUART0_VIC_ENABLE ( ( unsigned portLONG ) 0x0020 ) +#define serCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 ) + +#define serINVALID_QUEUE ( ( xQueueHandle ) 0 ) +#define serHANDLE ( ( xComPortHandle ) 1 ) +#define serNO_BLOCK ( ( portTickType ) 0 ) + +/*-----------------------------------------------------------*/ + +/* Queues used to hold received characters, and characters waiting to be +transmitted. */ +static xQueueHandle xRxedChars; +static xQueueHandle xCharsForTx; + +/*-----------------------------------------------------------*/ + +/* Communication flag between the interrupt service routine and serial API. */ +static volatile portLONG *plTHREEmpty; + +/* + * The queues are created in serialISR.c as they are used from the ISR. + * Obtain references to the queues and THRE Empty flag. + */ +extern void vSerialISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars, xQueueHandle *pxCharsForTx, portLONG volatile **pplTHREEmptyFlag ); + +/*-----------------------------------------------------------*/ + +xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) +{ +unsigned portLONG ulDivisor, ulWantedClock; +xComPortHandle xReturn = serHANDLE; +extern void ( vUART_ISR_Wrapper )( void ); + + /* The queues are used in the serial ISR routine, so are created from + serialISR.c (which is always compiled to ARM mode. */ + vSerialISRCreateQueues( uxQueueLength, &xRxedChars, &xCharsForTx, &plTHREEmpty ); + + if( + ( xRxedChars != serINVALID_QUEUE ) && + ( xCharsForTx != serINVALID_QUEUE ) && + ( ulWantedBaud != ( unsigned portLONG ) 0 ) + ) + { + portENTER_CRITICAL(); + { + /* Setup the baud rate: Calculate the divisor value. */ + ulWantedClock = ulWantedBaud * serWANTED_CLOCK_SCALING; + ulDivisor = configCPU_CLOCK_HZ / ulWantedClock; + + /* Set the DLAB bit so we can access the divisor. */ + UART0_LCR |= serDLAB; + + /* Setup the divisor. */ + UART0_DLL = ( unsigned portCHAR ) ( ulDivisor & ( unsigned portLONG ) 0xff ); + ulDivisor >>= 8; + UART0_DLM = ( unsigned portCHAR ) ( ulDivisor & ( unsigned portLONG ) 0xff ); + + /* Turn on the FIFO's and clear the buffers. */ + UART0_FCR = ( serFIFO_ON | serCLEAR_FIFO ); + + /* Setup transmission format. */ + UART0_LCR = serNO_PARITY | ser1_STOP_BIT | ser8_BIT_CHARS; + + /* Setup the VIC for the UART. */ + VICIntSelect &= ~( serUART0_VIC_CHANNEL_BIT ); + VICIntEnable |= serUART0_VIC_CHANNEL_BIT; + VICVectAddr1 = ( portLONG ) vUART_ISR_Wrapper; + VICVectCntl1 = serUART0_VIC_CHANNEL | serUART0_VIC_ENABLE; + + /* Enable UART0 interrupts. */ + UART0_IER |= serENABLE_INTERRUPTS; + } + portEXIT_CRITICAL(); + } + else + { + xReturn = ( xComPortHandle ) 0; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) +{ + /* The port handle is not required as this driver only supports UART0. */ + ( void ) pxPort; + + /* Get the next character from the buffer. Return false if no characters + are available, or arrive before xBlockTime expires. */ + if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) + { + return pdTRUE; + } + else + { + return pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength ) +{ +signed portCHAR *pxNext; + + /* NOTE: This implementation does not handle the queue being full as no + block time is used! */ + + /* The port handle is not required as this driver only supports UART0. */ + ( void ) pxPort; + ( void ) usStringLength; + + /* Send each character in the string, one at a time. */ + pxNext = ( signed portCHAR * ) pcString; + while( *pxNext ) + { + xSerialPutChar( pxPort, *pxNext, serNO_BLOCK ); + pxNext++; + } +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) +{ +signed portBASE_TYPE xReturn; + + /* This demo driver only supports one port so the parameter is not used. */ + ( void ) pxPort; + + portENTER_CRITICAL(); + { + /* Is there space to write directly to the UART? */ + if( *plTHREEmpty == ( portLONG ) pdTRUE ) + { + /* We wrote the character directly to the UART, so was + successful. */ + *plTHREEmpty = pdFALSE; + UART0_THR = cOutChar; + xReturn = pdPASS; + } + else + { + /* We cannot write directly to the UART, so queue the character. + Block for a maximum of xBlockTime if there is no space in the + queue. */ + xReturn = xQueueSend( xCharsForTx, &cOutChar, xBlockTime ); + + /* Depending on queue sizing and task prioritisation: While we + were blocked waiting to post interrupts were not disabled. It is + possible that the serial ISR has emptied the Tx queue, in which + case we need to start the Tx off again. */ + if( ( *plTHREEmpty == ( portLONG ) pdTRUE ) && ( xReturn == pdPASS ) ) + { + xQueueReceive( xCharsForTx, &cOutChar, serNO_BLOCK ); + *plTHREEmpty = pdFALSE; + UART0_THR = cOutChar; + } + } + } + portEXIT_CRITICAL(); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +void vSerialClose( xComPortHandle xPort ) +{ + /* Not supported as not required by the demo application. */ + ( void ) xPort; +} +/*-----------------------------------------------------------*/ + + + + + + diff --git a/20080212/Demo/ARM7_LPC2106_GCC/serial/serialISR.c b/20080212/Demo/ARM7_LPC2106_GCC/serial/serialISR.c new file mode 100644 index 000000000..199a1b436 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2106_GCC/serial/serialISR.c @@ -0,0 +1,184 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +/* + BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0. + + This file contains all the serial port components that must be compiled + to ARM mode. The components that can be compiled to either ARM or THUMB + mode are contained in serial.c. + +*/ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "queue.h" +#include "task.h" + +/* Demo application includes. */ +#include "serial.h" + +/*-----------------------------------------------------------*/ + +/* Constant to access the VIC. */ +#define serCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 ) + +/* Constants to determine the ISR source. */ +#define serSOURCE_THRE ( ( unsigned portCHAR ) 0x02 ) +#define serSOURCE_RX_TIMEOUT ( ( unsigned portCHAR ) 0x0c ) +#define serSOURCE_ERROR ( ( unsigned portCHAR ) 0x06 ) +#define serSOURCE_RX ( ( unsigned portCHAR ) 0x04 ) +#define serINTERRUPT_SOURCE_MASK ( ( unsigned portCHAR ) 0x0f ) + +/* Queues used to hold received characters, and characters waiting to be +transmitted. */ +static xQueueHandle xRxedChars; +static xQueueHandle xCharsForTx; +static volatile portLONG lTHREEmpty; + +/*-----------------------------------------------------------*/ + +/* + * The queues are created in serialISR.c as they are used from the ISR. + * Obtain references to the queues and THRE Empty flag. + */ +void vSerialISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars, xQueueHandle *pxCharsForTx, portLONG volatile **pplTHREEmptyFlag ); + +/* UART0 interrupt service routine entry point. */ +void vUART_ISR_Wrapper( void ) __attribute__ ((naked)); + +/* UART0 interrupt service routine handler. */ +void vUART_ISR_Handler( void ); + +/*-----------------------------------------------------------*/ +void vSerialISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars, + xQueueHandle *pxCharsForTx, portLONG volatile **pplTHREEmptyFlag ) +{ + /* Create the queues used to hold Rx and Tx characters. */ + xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + + /* Pass back a reference to the queues so the serial API file can + post/receive characters. */ + *pxRxedChars = xRxedChars; + *pxCharsForTx = xCharsForTx; + + /* Initialise the THRE empty flag - and pass back a reference. */ + lTHREEmpty = ( portLONG ) pdTRUE; + *pplTHREEmptyFlag = &lTHREEmpty; +} +/*-----------------------------------------------------------*/ + +void vUART_ISR_Wrapper( void ) +{ + /* Save the context of the interrupted task. */ + portSAVE_CONTEXT(); + + /* Call the handler. This must be a separate function from the wrapper + to ensure the correct stack frame is set up. */ + vUART_ISR_Handler(); + + /* Restore the context of whichever task is going to run next. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +void vUART_ISR_Handler( void ) +{ +signed portCHAR cChar; +portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByRx = pdFALSE; + + /* What caused the interrupt? */ + switch( UART0_IIR & serINTERRUPT_SOURCE_MASK ) + { + case serSOURCE_ERROR : /* Not handling this, but clear the interrupt. */ + cChar = UART0_LSR; + break; + + case serSOURCE_THRE : /* The THRE is empty. If there is another + character in the Tx queue, send it now. */ + if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE ) + { + UART0_THR = cChar; + } + else + { + /* There are no further characters + queued to send so we can indicate + that the THRE is available. */ + lTHREEmpty = pdTRUE; + } + break; + + case serSOURCE_RX_TIMEOUT : + case serSOURCE_RX : /* A character was received. Place it in + the queue of received characters. */ + cChar = UART0_RBR; + if( xQueueSendFromISR( xRxedChars, &cChar, ( portBASE_TYPE ) pdFALSE ) ) + { + xTaskWokenByRx = pdTRUE; + } + break; + + default : /* There is nothing to do, leave the ISR. */ + break; + } + + if( xTaskWokenByTx || xTaskWokenByRx ) + { + portYIELD_FROM_ISR(); + } + + /* Clear the ISR in the VIC. */ + VICVectAddr = serCLEAR_VIC_INTERRUPT; +} + + + + + + + diff --git a/20080212/Demo/ARM7_LPC2129_IAR/FreeRTOSConfig.h b/20080212/Demo/ARM7_LPC2129_IAR/FreeRTOSConfig.h new file mode 100644 index 000000000..bbe21fea2 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2129_IAR/FreeRTOSConfig.h @@ -0,0 +1,88 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/* Hardware specifics. */ +#include + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 60000000 ) /* =12.0MHz xtal multiplied by 5 using the PLL. */ +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 100 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) 14200 ) +#define configMAX_TASK_NAME_LEN ( 16 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/ARM7_LPC2129_IAR/ParTest/ParTest.c b/20080212/Demo/ARM7_LPC2129_IAR/ParTest/ParTest.c new file mode 100644 index 000000000..08af251b4 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2129_IAR/ParTest/ParTest.c @@ -0,0 +1,112 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/*----------------------------------------------------------- + * Simple parallel port IO routines for the LED's. + *-----------------------------------------------------------*/ + + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* Demo application includes. */ +#include "partest.h" + +/* Board specific defines. */ +#define partstFIRST_IO ( ( unsigned portLONG ) 0x10000 ) +#define partstNUM_LEDS ( 8 ) + +/*-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ + /* The ports are setup within prvInitialiseHardware(), called by main(). */ +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ +unsigned portLONG ulLED = partstFIRST_IO; + + if( uxLED < partstNUM_LEDS ) + { + /* Rotate to the wanted bit of port 1. Only P16 to P23 have an LED + attached. */ + ulLED <<= ( unsigned portLONG ) uxLED; + + /* Set or clear the output. */ + if( xValue ) + { + IO1SET = ulLED; + } + else + { + IO1CLR = ulLED; + } + } +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned portLONG ulLED = partstFIRST_IO, ulCurrentState; + + if( uxLED < partstNUM_LEDS ) + { + /* Rotate to the wanted bit of port 1. Only P10 to P13 have an LED + attached. */ + ulLED <<= ( unsigned portLONG ) uxLED; + + /* If this bit is already set, clear it, and visa versa. */ + ulCurrentState = IO1PIN; + if( ulCurrentState & ulLED ) + { + IO1CLR = ulLED; + } + else + { + IO1SET = ulLED; + } + } +} + + diff --git a/20080212/Demo/ARM7_LPC2129_IAR/SrcIAR/lpc2xxx_cstartup.s b/20080212/Demo/ARM7_LPC2129_IAR/SrcIAR/lpc2xxx_cstartup.s new file mode 100644 index 000000000..062d7dbf2 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2129_IAR/SrcIAR/lpc2xxx_cstartup.s @@ -0,0 +1,189 @@ +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Part one of the system initialization code, +;; contains low-level +;; initialization. +;; +;; Copyright 2006 IAR Systems. All rights reserved. +;; +;; $Revision: 10608 $ +;; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION IRQ_STACK:DATA:NOROOT(3) + SECTION ABT_STACK:DATA:NOROOT(3) + SECTION SVC_STACK:DATA:NOROOT(3) + SECTION UND_STACK:DATA:NOROOT(3) + SECTION FIQ_STACK:DATA:NOROOT(3) + SECTION CSTACK:DATA:NOROOT(3) + +; +; The module in this file are included in the libraries, and may be +; replaced by any user-defined modules that define the PUBLIC symbol +; __iar_program_start or a user defined start symbol. +; +; To override the cstartup defined in the library, simply add your +; modified version to the workbench project. + + SECTION .intvec:CODE:NOROOT(2) + + PUBLIC __vector + PUBLIC __vector_0x14 + PUBLIC __iar_program_start + EXTERN vPortYieldProcessor + + ARM +__vector: + ;; + ldr pc,[pc,#+24] ;; Reset + ldr pc,[pc,#+24] ;; Undefined instructions +;; ldr pc,[pc,#+24] ;; Software interrupt (SWI/SVC) + b vPortYieldProcessor + ldr pc,[pc,#+24] ;; Prefetch abort + ldr pc,[pc,#+24] ;; Data abort +__vector_0x14 + DC32 0 ;; RESERVED + ldr pc, [PC, #-0xFF0] ;; IRQ + ldr pc,[pc,#+24] ;; FIQ + + DC32 __iar_program_start ;; Reset + DC32 undef_handler ;; Undefined instructions + DC32 0 ;; Software interrupt (SWI/SVC) + DC32 prefetch_handler ;; Prefetch abort + DC32 data_handler ;; Data abort + DC32 0 ;; RESERVED + DC32 0 ;; IRQ + DC32 fiq_handler ;; FIQ + +undef_handler + b undef_handler + +prefetch_handler + b prefetch_handler + +data_handler + b data_handler + +fiq_handler + b fiq_handler +; -------------------------------------------------- +; ?cstartup -- low-level system initialization code. +; +; After a reser execution starts here, the mode is ARM, supervisor +; with interrupts disabled. +; + + + + SECTION .text:CODE:NOROOT(2) + +; PUBLIC ?cstartup + EXTERN ?main + REQUIRE __vector + + ARM + +__iar_program_start: +?cstartup: + +; +; Add initialization needed before setup of stackpointers here. +; + +; Errata MAM.1Incorrect read of data from SRAM after Reset and MAM +; is not enabled or partially enabled. +; Work-around: User code should enable the MAM after Reset and before +; any RAM accesses +MAMCR DEFINE 0xE01FC000 ; MAM Control Register +MAMTIM DEFINE 0xE01FC004 ; MAM Timing register + + ldr r0,=MAMCR + ldr r1,=MAMTIM + ldr r2,=0 + str r2,[r0] + ldr r2,=3 ; 1 < 20 MHz; 20 MHz < 2 < 40 MHz; 40MHz > 3 + str r2,[r1] + ldr r2,=2 + str r2,[r0] + +; Initialize the stack pointers. +; The pattern below can be used for any of the exception stacks: +; FIQ, IRQ, SVC, ABT, UND, SYS. +; The USR mode uses the same stack as SYS. +; The stack segments must be defined in the linker command file, +; and be declared above. +; +; -------------------- +; Mode, correspords to bits 0-5 in CPSR +MODE_BITS DEFINE 0x1F ; Bit mask for mode bits in CPSR +USR_MODE DEFINE 0x10 ; User mode +FIQ_MODE DEFINE 0x11 ; Fast Interrupt Request mode +IRQ_MODE DEFINE 0x12 ; Interrupt Request mode +SVC_MODE DEFINE 0x13 ; Supervisor mode +ABT_MODE DEFINE 0x17 ; Abort mode +UND_MODE DEFINE 0x1B ; Undefined Instruction mode +SYS_MODE DEFINE 0x1F ; System mode + + MRS r0, cpsr ; Original PSR value + + BIC r0, r0, #MODE_BITS ; Clear the mode bits + ORR r0, r0, #ABT_MODE ; Set ABT mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(ABT_STACK) ; End of ABT_STACK + + BIC r0, r0, #MODE_BITS ; Clear the mode bits + ORR r0, r0, #SVC_MODE ; Set SVC mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(SVC_STACK) ; End of SVC_STACK + + BIC r0, r0, #MODE_BITS ; Clear the mode bits + ORR r0, r0, #UND_MODE ; Set UND mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(UND_STACK) ; End of UND_STACK + + BIC r0, r0, #MODE_BITS ; Clear the mode bits + ORR r0, r0, #FIQ_MODE ; Set FIQ mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(FIQ_STACK) ; End of FIQ_STACK + + BIC r0, r0, #MODE_BITS ; Clear the mode bits + ORR r0, r0, #IRQ_MODE ; Set IRQ mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(IRQ_STACK) ; End of IRQ_STACK + + BIC r0 ,r0, #MODE_BITS ; Clear the mode bits + ORR r0 ,r0, #SYS_MODE ; Set System mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(CSTACK) ; End of CSTACK + +#ifdef __ARMVFP__ + ;; Enable the VFP coprocessor. + + MOV r0, #0x40000000 ; Set EN bit in VFP + FMXR fpexc, r0 ; FPEXC, clear others. + +; +; Disable underflow exceptions by setting flush to zero mode. +; For full IEEE 754 underflow compliance this code should be removed +; and the appropriate exception handler installed. +; + + MOV r0, #0x01000000 ; Set FZ bit in VFP + FMXR fpscr, r0 ; FPSCR, clear others. +#endif + +; +; Add more initialization here +; + BIC r0, r0, #MODE_BITS ; Clear the mode bits + ORR r0, r0, #SVC_MODE ; Set SVC mode bits + MSR cpsr_c, r0 ; Change the mode + +; Continue to ?main for C-level initialization. + + LDR r0, =?main + BX r0 + + END diff --git a/20080212/Demo/ARM7_LPC2129_IAR/main.c b/20080212/Demo/ARM7_LPC2129_IAR/main.c new file mode 100644 index 000000000..74e2f9e6d --- /dev/null +++ b/20080212/Demo/ARM7_LPC2129_IAR/main.c @@ -0,0 +1,294 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +/* + NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. + The processor MUST be in supervisor mode when vTaskStartScheduler is + called. The demo applications included in the FreeRTOS.org download switch + to supervisor mode prior to main being called. If you are not using one of + these demo application projects then ensure Supervisor mode is used. +*/ + + +/* + * Creates all the demo application tasks, then starts the scheduler. The WEB + * documentation provides more details of the demo application tasks. + * + * Main.c also creates a task called "Check". This only executes every three + * seconds but has the highest priority so is guaranteed to get processor time. + * Its main function is to check that all the other tasks are still operational. + * Each task (other than the "flash" tasks) maintains a unique count that is + * incremented each time the task successfully completes its function. Should + * any error occur within such a task the count is permanently halted. The + * check task inspects the count of each task to ensure it has changed since + * the last time the check task executed. If all the count variables have + * changed all the tasks are still executing error free, and the check task + * toggles the onboard LED. Should any task contain an error at any time + * the LED toggle rate will change from 3 seconds to 500ms. + * + */ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo application includes. */ +#include "flash.h" +#include "integer.h" +#include "PollQ.h" +#include "BlockQ.h" +#include "semtest.h" +#include "dynamic.h" +#include "partest.h" +#include "comtest2.h" + +/* Priorities for the demo application tasks. */ +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) + +/* Constants required by the 'Check' task. */ +#define mainNO_ERROR_FLASH_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS ) +#define mainERROR_FLASH_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS ) +#define mainCHECK_TASK_LED ( 7 ) + +/* Constants for the ComTest tasks. */ +#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 115200 ) +#define mainCOM_TEST_LED ( 4 ) +#define mainTX_ENABLE ( ( unsigned portLONG ) 0x0001 ) +#define mainRX_ENABLE ( ( unsigned portLONG ) 0x0004 ) + +/* Constants to setup the PLL. */ +#define mainPLL_MUL_4 ( ( unsigned portCHAR ) 0x0003 ) +#define mainPLL_DIV_1 ( ( unsigned portCHAR ) 0x0000 ) +#define mainPLL_ENABLE ( ( unsigned portCHAR ) 0x0001 ) +#define mainPLL_CONNECT ( ( unsigned portCHAR ) 0x0003 ) +#define mainPLL_FEED_BYTE1 ( ( unsigned portCHAR ) 0xaa ) +#define mainPLL_FEED_BYTE2 ( ( unsigned portCHAR ) 0x55 ) +#define mainPLL_LOCK ( ( unsigned portLONG ) 0x0400 ) + +/* Constants to setup the MAM. */ +#define mainMAM_TIM_3 ( ( unsigned portCHAR ) 0x03 ) +#define mainMAM_MODE_FULL ( ( unsigned portCHAR ) 0x02 ) + +/* Constants to setup the peripheral bus. */ +#define mainBUS_CLK_FULL ( ( unsigned portCHAR ) 0x01 ) + +/* And finally, constant to setup the port for the LED's. */ +#define mainLED_TO_OUTPUT ( ( unsigned portLONG ) 0xff0000 ) + +/* + * The task that executes at the highest priority and calls + * prvCheckOtherTasksAreStillRunning(). See the description at the top + * of the file. + */ +static void vErrorChecks( void *pvParameters ); + +/* + * Configures the processor for use with this demo. + */ +static void prvSetupHardware( void ); + +/* + * Checks that all the demo application tasks are still executing without error + * - as described at the top of the file. + */ +static portLONG prvCheckOtherTasksAreStillRunning( void ); + + +/*-----------------------------------------------------------*/ + +/* + * Starts all the other tasks, then starts the scheduler. + */ +void main( void ) +{ + /* Setup the processor. */ + prvSetupHardware(); + + /* Start all the standard demo application tasks. */ + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vStartDynamicPriorityTasks(); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); + + /* Start the check task - which is defined in this file. */ + xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Start the scheduler. + + NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. + The processor MUST be in supervisor mode when vTaskStartScheduler is + called. The demo applications included in the FreeRTOS.org download switch + to supervisor mode prior to main being called. If you are not using one of + these demo application projects then ensure Supervisor mode is used here. + */ + vTaskStartScheduler(); + + /* We should never get here as control is now taken by the scheduler. */ + return; +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Setup the PLL to multiply the XTAL input by 4. */ + PLLCFG = ( mainPLL_MUL_4 | mainPLL_DIV_1 ); + + /* Activate the PLL by turning it on then feeding the correct sequence of + bytes. */ + PLLCON = mainPLL_ENABLE; + PLLFEED = mainPLL_FEED_BYTE1; + PLLFEED = mainPLL_FEED_BYTE2; + + /* Wait for the PLL to lock... */ + while( !( PLLSTAT & mainPLL_LOCK ) ); + + /* ...before connecting it using the feed sequence again. */ + PLLCON = mainPLL_CONNECT; + PLLFEED = mainPLL_FEED_BYTE1; + PLLFEED = mainPLL_FEED_BYTE2; + + /* Setup and turn on the MAM. Three cycle access is used due to the fast + PLL used. It is possible faster overall performance could be obtained by + tuning the MAM and PLL settings. */ + MAMTIM = mainMAM_TIM_3; + MAMCR = mainMAM_MODE_FULL; + + /* Setup the peripheral bus to be the same as the PLL output. */ + VPBDIV = mainBUS_CLK_FULL; + + /* Configure the RS2332 pins. All other pins remain at their default of 0. */ + PINSEL0 |= mainTX_ENABLE; + PINSEL0 |= mainRX_ENABLE; + + /* LED pins need to be output. */ + IO1DIR = mainLED_TO_OUTPUT; + + /* Setup the peripheral bus to be the same as the PLL output. */ + VPBDIV = mainBUS_CLK_FULL; +} +/*-----------------------------------------------------------*/ + +static void vErrorChecks( void *pvParameters ) +{ +portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD; + + /* The parameters are not used in this task. */ + ( void ) pvParameters; + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. If an error is detected then the delay period + is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so + the on board LED flash rate will increase. */ + + for( ;; ) + { + /* Delay until it is time to execute again. */ + vTaskDelay( xDelayPeriod ); + + /* Check all the standard demo application tasks are executing without + error. */ + if( prvCheckOtherTasksAreStillRunning() != pdPASS ) + { + /* An error has been detected in one of the tasks - flash faster. */ + xDelayPeriod = mainERROR_FLASH_PERIOD; + } + + vParTestToggleLED( mainCHECK_TASK_LED ); + } +} +/*-----------------------------------------------------------*/ + +static portLONG prvCheckOtherTasksAreStillRunning( void ) +{ +portLONG lReturn = ( portLONG ) pdPASS; + + /* Check all the demo tasks (other than the flash tasks) to ensure + that they are all still running, and that none of them have detected + an error. */ + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + return lReturn; +} +/*-----------------------------------------------------------*/ + + diff --git a/20080212/Demo/ARM7_LPC2129_IAR/resource/lpc212x.icf b/20080212/Demo/ARM7_LPC2129_IAR/resource/lpc212x.icf new file mode 100644 index 000000000..4c0e3c8ed --- /dev/null +++ b/20080212/Demo/ARM7_LPC2129_IAR/resource/lpc212x.icf @@ -0,0 +1,47 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000044; +define symbol __ICFEDIT_region_ROM_end__ = 0x3FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x40000040; +define symbol __ICFEDIT_region_RAM_end__ = 0x40003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x200; +define symbol __ICFEDIT_size_svcstack__ = 0x200; +define symbol __ICFEDIT_size_irqstack__ = 0x200; +define symbol __ICFEDIT_size_fiqstack__ = 0x00; +define symbol __ICFEDIT_size_undstack__ = 0x0; +define symbol __ICFEDIT_size_abtstack__ = 0x0; +define symbol __ICFEDIT_size_heap__ = 0x0; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; +define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; +define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK, + block UND_STACK, block ABT_STACK, block HEAP }; + + + + + diff --git a/20080212/Demo/ARM7_LPC2129_IAR/rtosdemo.ewd b/20080212/Demo/ARM7_LPC2129_IAR/rtosdemo.ewd new file mode 100644 index 000000000..e75220176 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2129_IAR/rtosdemo.ewd @@ -0,0 +1,1225 @@ + + + + 1 + + Flash Debug + + ARM + + 1 + + C-SPY + 2 + + 15 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IARROM_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + JLINK_ID + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 1 + 1 + 1 + + + + + + + + MACRAIGOR_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin + 0 + + + + + Flash Bin + + ARM + + 0 + + C-SPY + 2 + + 15 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IARROM_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + JLINK_ID + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 1 + 1 + 0 + + + + + + + + MACRAIGOR_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 1 + 1 + 0 + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 0 + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin + 1 + + + + + + diff --git a/20080212/Demo/ARM7_LPC2129_IAR/rtosdemo.ewp b/20080212/Demo/ARM7_LPC2129_IAR/rtosdemo.ewp new file mode 100644 index 000000000..ae58590e1 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2129_IAR/rtosdemo.ewp @@ -0,0 +1,1612 @@ + + + + 1 + + Flash Debug + + ARM + + 1 + + General + 3 + + 14 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 19 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 7 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 5 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Flash Bin + + ARM + + 0 + + General + 3 + + 14 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 19 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 7 + 1 + 0 + + + + + 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$PROJ_DIR$\..\..\Source\portable\IAR\LPC2000\port.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\LPC2000\portasm.s79 + + + $PROJ_DIR$\..\..\Source\queue.c + + + $PROJ_DIR$\..\..\Source\tasks.c + + + + System Files + + $PROJ_DIR$\SrcIAR\lpc2xxx_cstartup.s + + + + + diff --git a/20080212/Demo/ARM7_LPC2129_IAR/rtosdemo.eww b/20080212/Demo/ARM7_LPC2129_IAR/rtosdemo.eww new file mode 100644 index 000000000..2294aacb5 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2129_IAR/rtosdemo.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\rtosdemo.ewp + + + + + diff --git a/20080212/Demo/ARM7_LPC2129_IAR/serial/serial.c b/20080212/Demo/ARM7_LPC2129_IAR/serial/serial.c new file mode 100644 index 000000000..f38949dde --- /dev/null +++ b/20080212/Demo/ARM7_LPC2129_IAR/serial/serial.c @@ -0,0 +1,298 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +/* + BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0. +*/ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "queue.h" +#include "task.h" + +/* Demo application includes. */ +#include "serial.h" + +/*-----------------------------------------------------------*/ + +/* Constants to setup and access the UART. */ +#define serDLAB ( ( unsigned portCHAR ) 0x80 ) +#define serENABLE_INTERRUPTS ( ( unsigned portCHAR ) 0x03 ) +#define serNO_PARITY ( ( unsigned portCHAR ) 0x00 ) +#define ser1_STOP_BIT ( ( unsigned portCHAR ) 0x00 ) +#define ser8_BIT_CHARS ( ( unsigned portCHAR ) 0x03 ) +#define serFIFO_ON ( ( unsigned portCHAR ) 0x01 ) +#define serCLEAR_FIFO ( ( unsigned portCHAR ) 0x06 ) +#define serWANTED_CLOCK_SCALING ( ( unsigned portLONG ) 16 ) + +/* Constants to setup and access the VIC. */ +#define serU0VIC_CHANNEL ( ( unsigned portLONG ) 0x0006 ) +#define serU0VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x0040 ) +#define serU0VIC_ENABLE ( ( unsigned portLONG ) 0x0020 ) +#define serCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 ) + +/* Constants to determine the ISR source. */ +#define serSOURCE_THRE ( ( unsigned portCHAR ) 0x02 ) +#define serSOURCE_RX_TIMEOUT ( ( unsigned portCHAR ) 0x0c ) +#define serSOURCE_ERROR ( ( unsigned portCHAR ) 0x06 ) +#define serSOURCE_RX ( ( unsigned portCHAR ) 0x04 ) +#define serINTERRUPT_SOURCE_MASK ( ( unsigned portCHAR ) 0x0f ) + +/* Misc. */ +#define serINVALID_QUEUE ( ( xQueueHandle ) 0 ) +#define serHANDLE ( ( xComPortHandle ) 1 ) +#define serNO_BLOCK ( ( portTickType ) 0 ) + +/*-----------------------------------------------------------*/ + +/* Queues used to hold received characters, and characters waiting to be +transmitted. */ +static xQueueHandle xRxedChars; +static xQueueHandle xCharsForTx; +static volatile portLONG lTHREEmpty = pdFALSE; + +/*-----------------------------------------------------------*/ + +/* The ISR. Note that this is called by a wrapper written in the file +SerialISR.s79. See the WEB documentation for this port for further +information. */ +__arm void vSerialISR( void ); + +/*-----------------------------------------------------------*/ + +xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) +{ +unsigned portLONG ulDivisor, ulWantedClock; +xComPortHandle xReturn = serHANDLE; +extern void ( vSerialISREntry) ( void ); + + /* Create the queues used to hold Rx and Tx characters. */ + xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + + /* Initialise the THRE empty flag. */ + lTHREEmpty = pdTRUE; + + if( + ( xRxedChars != serINVALID_QUEUE ) && + ( xCharsForTx != serINVALID_QUEUE ) && + ( ulWantedBaud != ( unsigned portLONG ) 0 ) + ) + { + portENTER_CRITICAL(); + { + /* Setup the baud rate: Calculate the divisor value. */ + ulWantedClock = ulWantedBaud * serWANTED_CLOCK_SCALING; + ulDivisor = configCPU_CLOCK_HZ / ulWantedClock; + + /* Set the DLAB bit so we can access the divisor. */ + U0LCR |= serDLAB; + + /* Setup the divisor. */ + U0DLL = ( unsigned portCHAR ) ( ulDivisor & ( unsigned portLONG ) 0xff ); + ulDivisor >>= 8; + U0DLM = ( unsigned portCHAR ) ( ulDivisor & ( unsigned portLONG ) 0xff ); + + /* Turn on the FIFO's and clear the buffers. */ + U0FCR = ( serFIFO_ON | serCLEAR_FIFO ); + + /* Setup transmission format. */ + U0LCR = serNO_PARITY | ser1_STOP_BIT | ser8_BIT_CHARS; + + /* Setup the VIC for the UART. */ + VICIntSelect &= ~( serU0VIC_CHANNEL_BIT ); + VICIntEnable |= serU0VIC_CHANNEL_BIT; + VICVectAddr1 = ( unsigned portLONG ) vSerialISREntry; + VICVectCntl1 = serU0VIC_CHANNEL | serU0VIC_ENABLE; + + /* Enable UART0 interrupts. */ + U0IER |= serENABLE_INTERRUPTS; + } + portEXIT_CRITICAL(); + + xReturn = ( xComPortHandle ) 1; + } + else + { + xReturn = ( xComPortHandle ) 0; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) +{ + /* The port handle is not required as this driver only supports UART0. */ + ( void ) pxPort; + + /* Get the next character from the buffer. Return false if no characters + are available, or arrive before xBlockTime expires. */ + if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) + { + return pdTRUE; + } + else + { + return pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength ) +{ +signed portCHAR *pxNext; + + /* NOTE: This implementation does not handle the queue being full as no + block time is used! */ + + /* The port handle is not required as this driver only supports UART0. */ + ( void ) pxPort; + ( void ) usStringLength; + + /* Send each character in the string, one at a time. */ + pxNext = ( signed portCHAR * ) pcString; + while( *pxNext ) + { + xSerialPutChar( pxPort, *pxNext, serNO_BLOCK ); + pxNext++; + } +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) +{ +signed portBASE_TYPE xReturn; + + /* The port handle is not required as this driver only supports UART0. */ + ( void ) pxPort; + + portENTER_CRITICAL(); + { + /* Is there space to write directly to the UART? */ + if( lTHREEmpty == ( portLONG ) pdTRUE ) + { + /* We wrote the character directly to the UART, so was + successful. */ + lTHREEmpty = pdFALSE; + U0THR = cOutChar; + xReturn = pdPASS; + } + else + { + /* We cannot write directly to the UART, so queue the character. + Block for a maximum of xBlockTime if there is no space in the + queue. It is ok to block within a critical section as each + task has it's own critical section management. */ + xReturn = xQueueSend( xCharsForTx, &cOutChar, xBlockTime ); + + /* Depending on queue sizing and task prioritisation: While we + were blocked waiting to post interrupts were not disabled. It is + possible that the serial ISR has emptied the Tx queue, in which + case we need to start the Tx off again. */ + if( lTHREEmpty == ( portLONG ) pdTRUE ) + { + xQueueReceive( xCharsForTx, &cOutChar, serNO_BLOCK ); + lTHREEmpty = pdFALSE; + U0THR = cOutChar; + } + } + } + portEXIT_CRITICAL(); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +__arm void vSerialISR( void ) +{ +signed portCHAR cChar; +portBASE_TYPE xTaskWokenByRx = pdFALSE, xTaskWokenByTx = pdFALSE; + + /* What caused the interrupt? */ + switch( U0IIR & serINTERRUPT_SOURCE_MASK ) + { + case serSOURCE_ERROR : /* Not handling this, but clear the interrupt. */ + cChar = U0LSR; + break; + + case serSOURCE_THRE : /* The THRE is empty. If there is another + character in the Tx queue, send it now. */ + if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE ) + { + U0THR = cChar; + } + else + { + /* There are no further characters + queued to send so we can indicate + that the THRE is available. */ + lTHREEmpty = pdTRUE; + } + break; + + case serSOURCE_RX_TIMEOUT : + case serSOURCE_RX : /* A character was received. Place it in + the queue of received characters. */ + cChar = U0RBR; + if( xQueueSendFromISR( xRxedChars, &cChar, pdFALSE ) ) + { + xTaskWokenByRx = pdTRUE; + } + break; + + default : /* There is nothing to do, leave the ISR. */ + break; + } + + /* Exit the ISR. If a task was woken by either a character being received + or transmitted then a context switch will occur. */ + portEND_SWITCHING_ISR( ( xTaskWokenByTx || xTaskWokenByRx ) ); + + /* Clear the ISR in the VIC. */ + VICVectAddr = serCLEAR_VIC_INTERRUPT; +} +/*-----------------------------------------------------------*/ diff --git a/20080212/Demo/ARM7_LPC2129_IAR/serial/serialISR.s79 b/20080212/Demo/ARM7_LPC2129_IAR/serial/serialISR.s79 new file mode 100644 index 000000000..da0a0bd17 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2129_IAR/serial/serialISR.s79 @@ -0,0 +1,24 @@ + RSEG ICODE:CODE + CODE32 + + EXTERN vSerialISR + PUBLIC vSerialISREntry + +; Wrapper for the serial port interrupt service routine. This can cause a +; context switch so requires an assembly wrapper. + +; Defines the portSAVE_CONTEXT and portRESTORE_CONTEXT macros. +#include "ISR_Support.h" + +vSerialISREntry: + + portSAVE_CONTEXT ; Save the context of the current task. + + bl vSerialISR ; Call the ISR routine. + + portRESTORE_CONTEXT ; Restore the context of the current task - + ; which may be different to the task that + ; was interrupted. + + END + diff --git a/20080212/Demo/ARM7_LPC2129_IAR/settings/Basic.dbgdt b/20080212/Demo/ARM7_LPC2129_IAR/settings/Basic.dbgdt new file mode 100644 index 000000000..5085f2cdb --- /dev/null +++ b/20080212/Demo/ARM7_LPC2129_IAR/settings/Basic.dbgdt @@ -0,0 +1,71 @@ + + + + + + + + + + + 1892727 + + + + + + 200100 + + + 200188171100100010 + + + + + TabID-23416-30482 + Workspace + Workspace + + + rtosdemo + + + + 0 + + + + + TabID-12145-30489 + Debug Log + Debug-Log + + + + TabID-22894-30492 + Build + Build + + + + + 1 + TabID-18780-12821MemoryMemory2097764209776410000TabID-23506-14575WatchWatchpxCurrentTCBulCriticalNesting01761001001000TabID-4859-22480DisassemblyDisassembly0TabID-154-22568RegisterRegister0001CPSR0 + + + + + + TextEditorE:\Dev\FreeRTOS\Demo\ARM7_Ateml_IAR\main.c010378378TextEditorE:\Dev\FreeRTOS\source\include\task.h07782428324283TextEditorE:\Dev\FreeRTOS\Source\tasks.c09393051130511TextEditorE:\Dev\FreeRTOS\Demo\ARM7_Ateml_IAR\SrcIAR\Cstartup.s7904822262226TextEditorE:\Dev\FreeRTOS\Demo\Common\Minimal\flash.c09840254025TextEditorE:\Dev\FreeRTOS\Source\portable\IAR\AtmelSAM7\portasm.s7904110571079TextEditorE:\Dev\FreeRTOS\Demo\ARM7_Ateml_IAR\srciar\lib_AT91SAM7S64.h02778108450108450TextEditorE:\Dev\FreeRTOS\Source\portable\IAR\AtmelSAM7\port.c0136532653267TextEditorE:\Dev\FreeRTOS\Demo\ARM7_Ateml_IAR\ParTest\ParTest.c03600TextEditorE:\Dev\FreeRTOS\Source\portable\IAR\AtmelSAM7\portmacro.h067000100000010000001 + + + + + + + IarIdePM1DebuggerGui1-2-2715263-2-215315395625136729165625640750-2-2715647-2-2190190118750169794405625640750-26457151025645-2190190118750169794237500640750-2-21511602-2-21604153100250013672995625136729149-2333669-21496711844193751644321143751635381496673331602667149935184584375164432115000598748 + + + + diff --git a/20080212/Demo/ARM7_LPC2129_IAR/settings/Basic.dni b/20080212/Demo/ARM7_LPC2129_IAR/settings/Basic.dni new file mode 100644 index 000000000..9b68f65a8 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2129_IAR/settings/Basic.dni @@ -0,0 +1,23 @@ +[DisAssemblyWindow] +NumStates=_ 1 +State 1=_ 1 +[JLinkDriver] +WatchVectorCatch=_ 0 +WatchCond=_ 0 +Watch0=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0 +Watch1=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0 +[Log file] +LoggingEnabled=_ 0 +LogFile=_ "" +Category=_ 0 +[TermIOLog] +LoggingEnabled=_ 0 +LogFile=_ "" +[Disassemble mode] +mode=0 +[Breakpoints] +Bp0=_ "Code" "{E:\Dev\FreeRTOS\Source\portable\IAR\AtmelSAM7\port.c}.141.1@1" 1 0 0 0 "" 0 "" +Count=1 +[Low Level] +Pipeline mode=0 +Initialized=0 diff --git a/20080212/Demo/ARM7_LPC2129_IAR/settings/rtosdemo.dbgdt b/20080212/Demo/ARM7_LPC2129_IAR/settings/rtosdemo.dbgdt new file mode 100644 index 000000000..3489f2713 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2129_IAR/settings/rtosdemo.dbgdt @@ -0,0 +1,62 @@ + + + + + + + + + + + 181272727 + + + + + + 200010 + 300Build + 300Debug-Log + + + + + + + 200 + + 161100100100300010300300200100100100100200100100100100 + + + + + + + + TabID-22256-14845 + Workspace + Workspace + + + rtosdemortosdemo/Demo Sourcertosdemo/Scheduler Sourcertosdemo/System Filesrtosdemo/USBSample.c + + + + 0TabID-32269-5949Debug LogDebug-LogTabID-30271-4373BreakpointsBreakpoints0TabID-279-12558DisassemblyDisassembly0 + + + + + + TextEditorC:\E\temp\rc\1\Demo\ARM7_LPC2129_IAR\SrcIAR\lpc2xxx_cstartup.s0852866286600100000010000001 + + + + + + + iaridepm.enu1debuggergui.enu1-2-2646255-2-20000183571659878-2-2646198-2-2200200142857203666142857659878-2-22921402-2-21404294100285729938992857132383 + + + + diff --git a/20080212/Demo/ARM7_LPC2129_IAR/settings/rtosdemo.dni b/20080212/Demo/ARM7_LPC2129_IAR/settings/rtosdemo.dni new file mode 100644 index 000000000..e14d72694 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2129_IAR/settings/rtosdemo.dni @@ -0,0 +1,46 @@ +[DisAssemblyWindow] +NumStates=_ 1 +State 1=_ 1 +[JLinkDriver] +WatchVectorCatch=_ 0 +WatchCond=_ 0 +Watch0=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0 +Watch1=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0 +[Low Level] +Pipeline mode=1 +Initialized=0 +[Interrupts] +Enabled=1 +[MemoryMap] +Enabled=0 +TypeVolition=1 +UnspecRange=1 +ActionState=1 +[CodeCoverage] +Enabled=_ 0 +[Profiling] +Enabled=0 +[StackPlugin] +Enabled=1 +OverflowWarningsEnabled=1 +WarningThreshold=90 +SpWarningsEnabled=1 +WarnHow=0 +UseTrigger=1 +TriggerName=main +LimitSize=0 +ByteLimit=50 +[Log file] +LoggingEnabled=_ 0 +LogFile=_ "" +Category=_ 0 +[TermIOLog] +LoggingEnabled=_ 0 +LogFile=_ "" +[Disassemble mode] +mode=0 +[Breakpoints] +Count=0 +[TraceHelper] +Enabled=0 +ShowSource=1 diff --git a/20080212/Demo/ARM7_LPC2129_IAR/settings/rtosdemo.wsdt b/20080212/Demo/ARM7_LPC2129_IAR/settings/rtosdemo.wsdt new file mode 100644 index 000000000..63524ec48 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2129_IAR/settings/rtosdemo.wsdt @@ -0,0 +1,60 @@ + + + + + + rtosdemo/Flash Debug + + + + + + + + 191272727 + + 18115530877 + + + + + + + + + + + 01001055278946 + + + + + + + TabID-17425-14382 + Workspace + Workspace + + + rtosdemortosdemo/Demo Sourcertosdemo/System Files + + + + 0TabID-22109-27077BuildBuildTabID-12074-10873BreakpointsBreakpointsTabID-18349-15872Debug LogDebug-LogTabID-30013-18825Find in FilesFind-in-Files0 + + + + + + TextEditorC:\E\temp\rc\1\Demo\ARM7_LPC2129_IAR\main.c000000100000010000001 + + + + + + + iaridepm.enu1-2-2605265-2-20000190714618126-2-23331402-2-2140433510028573411415500078411 + + + + diff --git a/20080212/Demo/ARM7_LPC2129_IAR/settings/rtosdemo_lnk.par b/20080212/Demo/ARM7_LPC2129_IAR/settings/rtosdemo_lnk.par new file mode 100644 index 000000000..738732e18 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2129_IAR/settings/rtosdemo_lnk.par @@ -0,0 +1,17 @@ +// IAR XLINK Setup +// Autogenerated file - do not edit +% +setrangelist($evec_ADR,[0-3F]); +setrangelist($internal_ROM,[8000-FFFFF]); +setrangelist($external_ROM,[]); +setrangelist($internal_RAM,[100000-7FFFFF]); +setrangelist($external_RAM,[]); +$CSTACK_SIZE=200; +$IRQSTACK_SIZE=400; +$HEAP_SIZE=4; +$COMMANDS=""; +$STACK_LOCATION="Internal RAM"; +$IRQSTACK_LOCATION="Internal RAM"; +$HEAP_LOCATION="Internal RAM"; +$iar_saved_xclfilename="E:\Dev\FreeRTOS\Demo\ARM7_LPC2129_IAR\resource\rtosdemo_lnk.xcl"; +% \ No newline at end of file diff --git a/20080212/Demo/ARM7_LPC2129_Keil/FreeRTOSConfig.h b/20080212/Demo/ARM7_LPC2129_Keil/FreeRTOSConfig.h new file mode 100644 index 000000000..4fe457945 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2129_Keil/FreeRTOSConfig.h @@ -0,0 +1,88 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 60000000 ) /* =12.0MHz xtal multiplied by 5 using the PLL. */ +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 100 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) 14250 ) +#define configMAX_TASK_NAME_LEN ( 16 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/ARM7_LPC2129_Keil/ParTest/ParTest.c b/20080212/Demo/ARM7_LPC2129_Keil/ParTest/ParTest.c new file mode 100644 index 000000000..ee91280f9 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2129_Keil/ParTest/ParTest.c @@ -0,0 +1,107 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +#include "FreeRTOS.h" +#include "portable.h" +#include "partest.h" + +#define partstFIRST_IO ( ( unsigned portLONG ) 0x10000 ) +#define partstNUM_LEDS ( 8 ) + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ + /* This is performed from main() as the io bits are shared with other setup + functions. */ +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ +unsigned portLONG ulLED = partstFIRST_IO; + + if( uxLED < partstNUM_LEDS ) + { + /* Rotate to the wanted bit of port 0. Only P16 to P23 have an LED + attached. */ + ulLED <<= ( unsigned portLONG ) uxLED; + + /* Set or clear the output. */ + if( xValue ) + { + IOSET1 = ulLED; + } + else + { + IOCLR1 = ulLED; + } + } +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned portLONG ulLED = partstFIRST_IO, ulCurrentState; + + if( uxLED < partstNUM_LEDS ) + { + /* Rotate to the wanted bit of port 0. Only P10 to P13 have an LED + attached. */ + ulLED <<= ( unsigned portLONG ) uxLED; + + /* If this bit is already set, clear it, and visa versa. */ + ulCurrentState = IOPIN1; + if( ulCurrentState & ulLED ) + { + IOCLR1 = ulLED; + } + else + { + IOSET1 = ulLED; + } + } +} + diff --git a/20080212/Demo/ARM7_LPC2129_Keil/RTOSDemoSignal.UVL b/20080212/Demo/ARM7_LPC2129_Keil/RTOSDemoSignal.UVL new file mode 100644 index 000000000..7df396ed8 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2129_Keil/RTOSDemoSignal.UVL @@ -0,0 +1,40 @@ +[Signal 1] +DispName=Port1 +PlotType=1 +Color=16711935 +MinDec=0 +MinVal=0. +MaxDec=0 +MaxVal=-1. +Mask=65536 +Offset=16 +[Signal 2] +DispName=Port1 +PlotType=1 +Color=255 +MinDec=0 +MinVal=0. +MaxDec=0 +MaxVal=-1. +Mask=131072 +Offset=17 +[Signal 3] +DispName=Port1 +PlotType=1 +Color=32768 +MinDec=0 +MinVal=0. +MaxDec=0 +MaxVal=-1. +Mask=262144 +Offset=18 +[Signal 4] +DispName=Port1 +PlotType=1 +Color=16711680 +MinDec=0 +MinVal=0. +MaxDec=0 +MaxVal=-1. +Mask=524288 +Offset=19 diff --git a/20080212/Demo/ARM7_LPC2129_Keil/Startup.s b/20080212/Demo/ARM7_LPC2129_Keil/Startup.s new file mode 100644 index 000000000..769ed7890 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2129_Keil/Startup.s @@ -0,0 +1,379 @@ +/***********************************************************************/ +/* This file is part of the uVision/ARM development tools */ +/* Copyright KEIL ELEKTRONIK GmbH 2002-2004 */ +/***********************************************************************/ +/* */ +/* STARTUP.S: Startup file for Philips LPC2000 device series */ +/* */ +/***********************************************************************/ + + +/* +//*** <<< Use Configuration Wizard in Context Menu >>> *** +*/ + + +// *** Startup Code (executed after Reset) *** + + +// Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs + + Mode_USR EQU 0x10 + Mode_FIQ EQU 0x11 + Mode_IRQ EQU 0x12 + Mode_SVC EQU 0x13 + Mode_ABT EQU 0x17 + Mode_UND EQU 0x1B + Mode_SYS EQU 0x1F + + I_Bit EQU 0x80 /* when I bit is set, IRQ is disabled */ + F_Bit EQU 0x40 /* when F bit is set, FIQ is disabled */ + + +/* +// Stack Configuration (Stack Sizes in Bytes) +// Undefined Mode <0x0-0xFFFFFFFF> +// Supervisor Mode <0x0-0xFFFFFFFF> +// Abort Mode <0x0-0xFFFFFFFF> +// Fast Interrupt Mode <0x0-0xFFFFFFFF> +// Interrupt Mode <0x0-0xFFFFFFFF> +// User/System Mode <0x0-0xFFFFFFFF> +// +*/ + UND_Stack_Size EQU 0x00000004 + SVC_Stack_Size EQU 0x00000100 + ABT_Stack_Size EQU 0x00000004 + FIQ_Stack_Size EQU 0x00000004 + IRQ_Stack_Size EQU 0x00000300 + USR_Stack_Size EQU 0x00000200 + +AREA STACK, DATA, READWRITE, ALIGN=2 + DS (USR_Stack_Size+3)&~3 ; Stack for User/System Mode + DS (IRQ_Stack_Size+3)&~3 ; Stack for Interrupt Mode + DS (FIQ_Stack_Size+3)&~3 ; Stack for Fast Interrupt Mode + DS (ABT_Stack_Size+3)&~3 ; Stack for Abort Mode + DS (SVC_Stack_Size+3)&~3 ; Stack for Supervisor Mode + DS (UND_Stack_Size+3)&~3 ; Stack for Undefined Mode +Top_Stack: + + +// Phase Locked Loop (PLL) definitions + PLL_BASE EQU 0xE01FC080 /* PLL Base Address */ + PLLCON_OFS EQU 0x00 /* PLL Control Offset*/ + PLLCFG_OFS EQU 0x04 /* PLL Configuration Offset */ + PLLSTAT_OFS EQU 0x08 /* PLL Status Offset */ + PLLFEED_OFS EQU 0x0C /* PLL Feed Offset */ + PLLCON_PLLE EQU (1<<0) /* PLL Enable */ + PLLCON_PLLC EQU (1<<1) /* PLL Connect */ + PLLCFG_MSEL EQU (0x1F<<0) /* PLL Multiplier */ + PLLCFG_PSEL EQU (0x03<<5) /* PLL Divider */ + PLLSTAT_PLOCK EQU (1<<10) /* PLL Lock Status */ + +/* +// PLL Setup +// Phase Locked Loop +// MSEL: PLL Multiplier Selection +// <1-32><#-1> +// M Value +// PSEL: PLL Divider Selection +// <0=> 1 <1=> 2 <2=> 4 <3=> 8 +// P Value +// +*/ + PLL_SETUP EQU 1 + PLLCFG_Val EQU 0x00000024 + + +// Memory Accelerator Module (MAM) definitions + MAM_BASE EQU 0xE01FC000 /* MAM Base Address */ + MAMCR_OFS EQU 0x00 /* MAM Control Offset*/ + MAMTIM_OFS EQU 0x04 /* MAM Timing Offset */ + +/* +// MAM Setup +// Memory Accelerator Module +// MAM Control +// <0=> Disabled +// <1=> Partially Enabled +// <2=> Fully Enabled +// Mode +// MAM Timing +// <0=> Reserved <1=> 1 <2=> 2 <3=> 3 +// <4=> 4 <5=> 5 <6=> 6 <7=> 7 +// Fetch Cycles +// +*/ + MAM_SETUP EQU 1 + MAMCR_Val EQU 0x00000002 + MAMTIM_Val EQU 0x00000003 + + +// External Memory Controller (EMC) definitions + EMC_BASE EQU 0xFFE00000 /* EMC Base Address */ + BCFG0_OFS EQU 0x00 /* BCFG0 Offset */ + BCFG1_OFS EQU 0x04 /* BCFG1 Offset */ + BCFG2_OFS EQU 0x08 /* BCFG2 Offset */ + BCFG3_OFS EQU 0x0C /* BCFG3 Offset */ + +/* +// External Memory Controller (EMC) +*/ + EMC_SETUP EQU 0 + +/* +// Bank Configuration 0 (BCFG0) +// IDCY: Idle Cycles <0-15> +// WST1: Wait States 1 <0-31> +// WST2: Wait States 2 <0-31> +// RBLE: Read Byte Lane Enable +// WP: Write Protect +// BM: Burst ROM +// MW: Memory Width <0=> 8-bit <1=> 16-bit +// <2=> 32-bit <3=> Reserved +// +*/ + BCFG0_SETUP EQU 0 + BCFG0_Val EQU 0x0000FBEF + +/* +// Bank Configuration 1 (BCFG1) +// IDCY: Idle Cycles <0-15> +// WST1: Wait States 1 <0-31> +// WST2: Wait States 2 <0-31> +// RBLE: Read Byte Lane Enable +// WP: Write Protect +// BM: Burst ROM +// MW: Memory Width <0=> 8-bit <1=> 16-bit +// <2=> 32-bit <3=> Reserved +// +*/ + BCFG1_SETUP EQU 0 + BCFG1_Val EQU 0x0000FBEF + +/* +// Bank Configuration 0 (BCFG2) +// IDCY: Idle Cycles <0-15> +// WST1: Wait States 1 <0-31> +// WST2: Wait States 2 <0-31> +// RBLE: Read Byte Lane Enable +// WP: Write Protect +// BM: Burst ROM +// MW: Memory Width <0=> 8-bit <1=> 16-bit +// <2=> 32-bit <3=> Reserved +// +*/ + BCFG2_SETUP EQU 0 + BCFG2_Val EQU 0x0000FBEF + +/* +// Bank Configuration 3 (BCFG3) +// IDCY: Idle Cycles <0-15> +// WST1: Wait States 1 <0-31> +// WST2: Wait States 2 <0-31> +// RBLE: Read Byte Lane Enable +// WP: Write Protect +// BM: Burst ROM +// MW: Memory Width <0=> 8-bit <1=> 16-bit +// <2=> 32-bit <3=> Reserved +// +*/ + BCFG3_SETUP EQU 0 + BCFG3_Val EQU 0x0000FBEF + +/* +// End of EMC +*/ + + +// External Memory Pins definitions + PINSEL2 EQU 0xE002C014 /* PINSEL2 Address */ + PINSEL2_Val EQU 0x0E6149E4 /* CS0..3, OE, WE, BLS0..3, + D0..31, A2..23, JTAG Pins */ + + +// Starupt Code must be linked first at Address at which it expects to run. + +$IF (EXTERNAL_MODE) + CODE_BASE EQU 0x80000000 +$ELSE + CODE_BASE EQU 0x00000000 +$ENDIF + +AREA STARTUPCODE, CODE, AT CODE_BASE // READONLY, ALIGN=4 + PUBLIC __startup + + EXTERN CODE32 (?C?INIT) + +__startup PROC CODE32 + +// Pre-defined interrupt handlers that may be directly +// overwritten by C interrupt functions +EXTERN CODE32 (Undef_Handler?A) +EXTERN CODE32 (vPortYieldProcessor?A) +EXTERN CODE32 (PAbt_Handler?A) +EXTERN CODE32 (DAbt_Handler?A) +EXTERN CODE32 (IRQ_Handler?A) +EXTERN CODE32 (FIQ_Handler?A) + +// Exception Vectors +// Mapped to Address 0. +// Absolute addressing mode must be used. + +Vectors: LDR PC,Reset_Addr + LDR PC,Undef_Addr + LDR PC,SWI_Addr + LDR PC,PAbt_Addr + LDR PC,DAbt_Addr + NOP /* Reserved Vector */ +; LDR PC,IRQ_Addr + LDR PC,[PC, #-0x0FF0] /* Vector from VicVectAddr */ + LDR PC,FIQ_Addr + +Reset_Addr: DD Reset_Handler +Undef_Addr: DD Undef_Handler?A +SWI_Addr: DD vPortYieldProcessor?A +PAbt_Addr: DD PAbt_Handler?A +DAbt_Addr: DD DAbt_Handler?A + DD 0 /* Reserved Address */ +IRQ_Addr: DD IRQ_Handler?A +FIQ_Addr: DD FIQ_Handler?A + + +// Reset Handler + +Reset_Handler: + + +$IF (EXTERNAL_MODE) + LDR R0, =PINSEL2 + LDR R1, =PINSEL2_Val + STR R1, [R0] +$ENDIF + + +IF (EMC_SETUP != 0) + LDR R0, =EMC_BASE + +IF (BCFG0_SETUP != 0) + LDR R1, =BCFG0_Val + STR R1, [R0, #BCFG0_OFS] +ENDIF + +IF (BCFG1_SETUP != 0) + LDR R1, =BCFG1_Val + STR R1, [R0, #BCFG1_OFS] +ENDIF + +IF (BCFG2_SETUP != 0) + LDR R1, =BCFG2_Val + STR R1, [R0, #BCFG2_OFS] +ENDIF + +IF (BCFG3_SETUP != 0) + LDR R1, =BCFG3_Val + STR R1, [R0, #BCFG3_OFS] +ENDIF + +ENDIF + + +IF (PLL_SETUP != 0) + LDR R0, =PLL_BASE + MOV R1, #0xAA + MOV R2, #0x55 + +// Configure and Enable PLL + MOV R3, #PLLCFG_Val + STR R3, [R0, #PLLCFG_OFS] + MOV R3, #PLLCON_PLLE + STR R3, [R0, #PLLCON_OFS] + STR R1, [R0, #PLLFEED_OFS] + STR R2, [R0, #PLLFEED_OFS] + +// Wait until PLL Locked +PLL_Loop: LDR R3, [R0, #PLLSTAT_OFS] + ANDS R3, R3, #PLLSTAT_PLOCK + BEQ PLL_Loop + +// Switch to PLL Clock + MOV R3, #(PLLCON_PLLE | PLLCON_PLLC) + STR R3, [R0, #PLLCON_OFS] + STR R1, [R0, #PLLFEED_OFS] + STR R2, [R0, #PLLFEED_OFS] +ENDIF + + +IF (MAM_SETUP != 0) + LDR R0, =MAM_BASE + MOV R1, #MAMTIM_Val + STR R1, [R0, #MAMTIM_OFS] + MOV R1, #MAMCR_Val + STR R1, [R0, #MAMCR_OFS] +ENDIF + + +// Memory Mapping (when Interrupt Vectors are in RAM) + MEMMAP EQU 0xE01FC040 /* Memory Mapping Control */ + +$IF (RAM_INTVEC) + LDR R0, =MEMMAP + MOV R1, #2 + STR R1, [R0] +$ENDIF + + +// Setup Stack for each mode + LDR R0, =Top_Stack + +// Enter Undefined Instruction Mode and set its Stack Pointer + MSR CPSR_c, #Mode_UND|I_Bit|F_Bit + MOV SP, R0 + SUB R0, R0, #UND_Stack_Size + +// Enter Abort Mode and set its Stack Pointer + MSR CPSR_c, #Mode_ABT|I_Bit|F_Bit + MOV SP, R0 + SUB R0, R0, #ABT_Stack_Size + +// Enter FIQ Mode and set its Stack Pointer + MSR CPSR_c, #Mode_FIQ|I_Bit|F_Bit + MOV SP, R0 + SUB R0, R0, #FIQ_Stack_Size + +// Enter IRQ Mode and set its Stack Pointer + MSR CPSR_c, #Mode_IRQ|I_Bit|F_Bit + MOV SP, R0 + SUB R0, R0, #IRQ_Stack_Size + +// Enter Supervisor Mode and set its Stack Pointer + MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit + MOV SP, R0 + SUB R0, R0, #SVC_Stack_Size + +// Enter S Mode and set its Stack Pointer + MSR CPSR_c, #Mode_SYS + MOV SP, R0 + +// Start in supervisor mode + MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit + +// Enter the C code + LDR R0,=?C?INIT + TST R0,#1 ; Bit-0 set: INIT is Thumb + LDREQ LR,=exit?A ; ARM Mode + LDRNE LR,=exit?T ; Thumb Mode + BX R0 + ENDP + +PUBLIC exit?A +exit?A PROC CODE32 + B exit?A + ENDP + +PUBLIC exit?T +exit?T PROC CODE16 +exit: B exit?T + ENDP + + + END diff --git a/20080212/Demo/ARM7_LPC2129_Keil/main.c b/20080212/Demo/ARM7_LPC2129_Keil/main.c new file mode 100644 index 000000000..cd61f38dc --- /dev/null +++ b/20080212/Demo/ARM7_LPC2129_Keil/main.c @@ -0,0 +1,292 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. + The processor MUST be in supervisor mode when vTaskStartScheduler is + called. The demo applications included in the FreeRTOS.org download switch + to supervisor mode prior to main being called. If you are not using one of + these demo application projects then ensure Supervisor mode is used. +*/ + + +/* + * Creates all the demo application tasks, then starts the scheduler. The WEB + * documentation provides more details of the demo application tasks. + * + * Main.c also creates a task called "Check". This only executes every three + * seconds but has the highest priority so is guaranteed to get processor time. + * Its main function is to check that all the other tasks are still operational. + * Each task (other than the "flash" tasks) maintains a unique count that is + * incremented each time the task successfully completes its function. Should + * any error occur within such a task the count is permanently halted. The + * check task inspects the count of each task to ensure it has changed since + * the last time the check task executed. If all the count variables have + * changed all the tasks are still executing error free, and the check task + * toggles the onboard LED. Should any task contain an error at any time + * the LED toggle rate will change from 3 seconds to 500ms. + * + */ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo application includes. */ +#include "partest.h" +#include "flash.h" +#include "integer.h" +#include "comtest2.h" +#include "serial.h" + +#ifdef KEIL_THUMB_INTERWORK + /* + THUMB mode allows more tasks to be created without the executable + binary exceeding the limits allowed by the evaluation version of + uVision3. + */ + #include "PollQ.h" + #include "BlockQ.h" + #include "semtest.h" + #include "dynamic.h" + +#endif + +/*-----------------------------------------------------------*/ + +/* Constants to setup I/O and processor. */ +#define mainTX_ENABLE ( ( unsigned portLONG ) 0x0001 ) +#define mainRX_ENABLE ( ( unsigned portLONG ) 0x0004 ) +#define mainBUS_CLK_FULL ( ( unsigned portCHAR ) 0x01 ) +#define mainLED_TO_OUTPUT ( ( unsigned portLONG ) 0xff0000 ) + +/* Constants for the ComTest demo application tasks. */ +#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 115200 ) +#define mainCOM_TEST_LED ( 3 ) + +/* Priorities for the demo application tasks. */ +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) + +/* Constants used by the "check" task. As described at the head of this file +the check task toggles an LED. The rate at which the LED flashes is used to +indicate whether an error has been detected or not. If the LED toggles every +3 seconds then no errors have been detected. If the rate increases to 500ms +then an error has been detected in at least one of the demo application tasks. */ +#define mainCHECK_LED ( 7 ) +#define mainNO_ERROR_FLASH_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS ) +#define mainERROR_FLASH_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS ) + +/*-----------------------------------------------------------*/ + +/* + * Checks that all the demo application tasks are still executing without error + * - as described at the top of the file. + */ +static portLONG prvCheckOtherTasksAreStillRunning( void ); + +/* + * The task that executes at the highest priority and calls + * prvCheckOtherTasksAreStillRunning(). See the description at the top + * of the file. + */ +static void vErrorChecks( void *pvParameters ); + +/* + * Configure the processor for use with the Keil demo board. This is very + * minimal as most of the setup is managed by the settings in the project + * file. + */ +static void prvSetupHardware( void ); + +/*-----------------------------------------------------------*/ + + + +/* + * Application entry point: + * Starts all the other tasks, then starts the scheduler. + */ +int main( void ) +{ + /* Setup the hardware for use with the Keil demo board. */ + prvSetupHardware(); + + /* Start the demo/test application tasks. */ + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); + vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); + + #ifdef KEIL_THUMB_INTERWORK + /* When using THUMB mode we can start more tasks without the executable + exceeding the size limit imposed by the evaluation version of uVision3. */ + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartDynamicPriorityTasks(); + #endif + + /* Start the check task - which is defined in this file. This is the task + that periodically checks to see that all the other tasks are executing + without error. */ + xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Now all the tasks have been started - start the scheduler. + + NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. + The processor MUST be in supervisor mode when vTaskStartScheduler is + called. The demo applications included in the FreeRTOS.org download switch + to supervisor mode prior to main being called. If you are not using one of + these demo application projects then ensure Supervisor mode is used here. */ + vTaskStartScheduler(); + + /* Should never reach here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +static void vErrorChecks( void *pvParameters ) +{ +portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD; + + /* Parameters are not used. */ + ( void ) pvParameters; + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. If an error is detected then the delay period + is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so + the on board LED flash rate will increase. + + This task runs at the highest priority. */ + + for( ;; ) + { + /* The period of the delay depends on whether an error has been + detected or not. If an error has been detected then the period + is reduced to increase the LED flash rate. */ + vTaskDelay( xDelayPeriod ); + + if( prvCheckOtherTasksAreStillRunning() != pdPASS ) + { + /* An error has been detected in one of the tasks - flash faster. */ + xDelayPeriod = mainERROR_FLASH_PERIOD; + } + + /* Toggle the LED before going back to wait for the next cycle. */ + vParTestToggleLED( mainCHECK_LED ); + } +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Perform the hardware setup required. This is minimal as most of the + setup is managed by the settings in the project file. */ + + /* Configure the RS2332 pins. All other pins remain at their default of 0. */ + PINSEL0 |= mainTX_ENABLE; + PINSEL0 |= mainRX_ENABLE; + + /* LED pins need to be output. */ + IODIR1 = mainLED_TO_OUTPUT; + + /* Setup the peripheral bus to be the same as the PLL output. */ + VPBDIV = mainBUS_CLK_FULL; +} +/*-----------------------------------------------------------*/ + +static portLONG prvCheckOtherTasksAreStillRunning( void ) +{ +portLONG lReturn = pdPASS; + + /* Check all the demo tasks (other than the flash tasks) to ensure + that they are all still running, and that none of them have detected + an error. */ + if( xAreIntegerMathsTaskStillRunning() != pdPASS ) + { + lReturn = pdFAIL; + } + + if( xAreComTestTasksStillRunning() != pdPASS ) + { + lReturn = pdFAIL; + } + + #ifdef KEIL_THUMB_INTERWORK + + /* When using THUMB mode we can start more tasks without the executable + exceeding the size limit imposed by the evaluation version of uVision3. */ + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + #endif + + return lReturn; +} +/*-----------------------------------------------------------*/ + + diff --git a/20080212/Demo/ARM7_LPC2129_Keil/rtosdemo_ARM.Opt b/20080212/Demo/ARM7_LPC2129_Keil/rtosdemo_ARM.Opt new file mode 100644 index 000000000..268345f18 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2129_Keil/rtosdemo_ARM.Opt @@ -0,0 +1,58 @@ +### uVision2 Project, (C) Keil Software +### Do not modify ! + + cExt (*.c) + aExt (*.s*; *.src; *.a*) + oExt (*.obj) + lExt (*.lib) + tExt (*.txt; *.h; *.inc) + pExt (*.plm) + CppX (*.cpp) + DaveTm { 0,0,0,0,0,0,0,0 } + +Target (FreeRTOS), 0x0005 // Tools: '' +GRPOPT 1,(ARM_DEMO),1,0,0 + +OPTFFF 1,1,1,2,0,127,137,0,<.\main.c> { 44,0,0,0,2,0,0,0,3,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,228,255,255,255,27,0,0,0,27,0,0,0,41,4,0,0,102,2,0,0 } +OPTFFF 1,2,2,0,0,0,0,0,<.\Startup.s> +OPTFFF 1,3,1,0,0,0,0,0,<.\ParTest\ParTest.c> +OPTFFF 1,4,1,0,0,0,0,0,<.\serial\serial.c> +OPTFFF 1,5,1,0,0,0,0,0,<.\serial\serialISR.c> +OPTFFF 1,6,1,0,0,0,0,0,<..\..\Source\tasks.c> +OPTFFF 1,7,1,0,0,0,0,0,<..\..\Source\queue.c> +OPTFFF 1,8,1,0,0,0,0,0,<..\..\Source\list.c> +OPTFFF 1,9,1,0,0,0,0,0,<..\..\Source\portable\Keil\ARM7\port.c> +OPTFFF 1,10,1,0,0,0,0,0,<..\..\Source\portable\Keil\ARM7\portISR.c> +OPTFFF 1,11,1,0,0,0,0,0,<..\Common\Minimal\flash.c> +OPTFFF 1,12,1,16777216,0,0,0,0,<..\Common\Minimal\comtest.c> +OPTFFF 1,13,1,0,0,0,0,0,<..\Common\Minimal\integer.c> +OPTFFF 1,14,1,0,0,0,0,0,<..\..\Source\portable\MemMang\heap_2.c> + + +TARGOPT 1, (FreeRTOS) + KACLK=12000000 + OPTTT 1,1,1,0 + OPTHX 0,65535,0,0,0 + OPTLX 120,65,8,<.\> + OPTOX 16 + OPTLT 1,1,1,0,1,1,0,1,0,0,0,0 + OPTXL 1,1,1,1,1,1,1,0,0 + OPTFL 1,0,1 + OPTBL 0,(Data Sheet) + OPTBL 1,(User Manual) + OPTDL (SARM.DLL)(-cLPC2100)(DARMP.DLL)(-pLPC21x9)(SARM.DLL)()(TARMP.DLL)(-pLPC21x9) + OPTDBG 44029,-1,()()()()()()()()()() (BIN\UL2ARM.DLL)()()() + OPTKEY 0,(DLGTARM)((134=-1,-1,-1,-1,0)(135=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(108=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(80=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(113=-1,-1,-1,-1,0)(112=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0)(117=-1,-1,-1,-1,0)(118=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(119=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(115=-1,-1,-1,-1,0)(116=-1,-1,-1,-1,0)) + OPTKEY 0,(UL2ARM)(-U174073036 -O7 -S0 -C0 -N00("ARM7TDMI-S Core") -D00(4F1F0F0F) -L00(4) -FO7 -FD40000000 -FC800 -FN1 -FF0LPC_IAP_256 -FS00 -FL03E000) + OPTKEY 0,(DLGDARM)((134=-1,-1,-1,-1,0)(135=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(108=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(80=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(113=-1,-1,-1,-1,0)(112=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0)(117=-1,-1,-1,-1,0)(118=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(119=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(115=-1,-1,-1,-1,0)(116=-1,-1,-1,-1,0)) + OPTKEY 0,(ARMDBGFLAGS)(-T5F) + OPTMM 1,0,(0x40001800) + OPTDF 0x1000080 + OPTLE <> + OPTLC <> + OPTLA 0,((Port1 & 0x10000) >> 16)(FF00FF000000000000000000000000000000F0BF010000006400000000E8764817000000506F72743100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000020370000) + OPTLA 1,((Port1 & 0x20000) >> 17)(FF0000000000000000000000000000000000F0BF010000006400000000E8764817000000506F72743100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000020370000) + OPTLA 2,((Port1 & 0x40000) >> 18)(008000000000000000000000000000000000F0BF010000006400000000E8764817000000506F72743100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000020370000) + OPTLA 3,((Port1 & 0x80000) >> 19)(0000FF000000000000000000000000000000F0BF010000006400000000E8764817000000506F72743100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000020370000) +EndOpt + diff --git a/20080212/Demo/ARM7_LPC2129_Keil/rtosdemo_ARM.Uv2 b/20080212/Demo/ARM7_LPC2129_Keil/rtosdemo_ARM.Uv2 new file mode 100644 index 000000000..2b4655ff1 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2129_Keil/rtosdemo_ARM.Uv2 @@ -0,0 +1,106 @@ +### uVision2 Project, (C) Keil Software +### Do not modify ! + +Target (FreeRTOS), 0x0005 // Tools: '' + +Group (ARM_DEMO) + +File 1,1,<.\main.c> 0x4162D96A +File 1,2,<.\Startup.s> 0x415AF382 +File 1,1,<.\ParTest\ParTest.c> 0x415AF50E +File 1,1,<.\serial\serial.c> 0x4162D488 +File 1,1,<.\serial\serialISR.c> 0x4162D404 +File 1,1,<..\..\Source\tasks.c> 0x4162D9E6 +File 1,1,<..\..\Source\queue.c> 0x411B5F14 +File 1,1,<..\..\Source\list.c> 0x411B5F24 +File 1,1,<..\..\Source\portable\Keil\ARM7\port.c> 0x4162D434 +File 1,1,<..\..\Source\portable\Keil\ARM7\portISR.c> 0x415A85E0 +File 1,1,<..\Common\Minimal\flash.c> 0x411B5F8E +File 1,1,<..\Common\Minimal\comtest.c> 0x413335E6 +File 1,1,<..\Common\Minimal\integer.c> 0x415FB7EE +File 1,1,<..\..\Source\portable\MemMang\heap_2.c> 0x0 + + +Options 1,0,0 // Target 'FreeRTOS' + Device (LPC2129) + Vendor (Philips) + Cpu (IRAM(0x40000000-0x40003FFF) IROM(0-0x3FFFF) CLOCK(12000000) CPUTYPE(ARM7TDMI)) + FlashUt (LPC210x_ISP.EXE ("#H" ^X $D COM1: 9600 1)) + StupF ("STARTUP\Philips\Startup.s" ("Philips LPC2100 Startup Code")) + FlashDR (UL2ARM(-U40296420 -O7 -C0 -FO7 -FD40000000 -FC800 -FN1 -FF0LPC_IAP_256 -FS00 -FL03E000)) + Rgf (LPC21xx.H) + Mem () + C () + A () + RL () + OH () + DBC_IFX () + DBC_CMS () + DBC_AMS () + DBC_LMS () + UseEnv=0 + EnvBin (D:\DevTools\Keil\arm\ARM\BIN\) + EnvInc () + EnvLib () + EnvReg (ÿPhilips\) + OrgReg (ÿPhilips\) + TgStat=16 + OutDir (.\) + OutName (rtosdemo_ARM) + GenApp=1 + GenLib=0 + GenHex=0 + Debug=1 + Browse=0 + LstDir (.\) + HexSel=0 + MG32K=0 + TGMORE=0 + RunUsr 0 0 <> + RunUsr 1 0 <> + BrunUsr 0 0 <> + BrunUsr 1 0 <> + SVCSID <> + KACPU (ARM7TDMI) + TKAFL { 0,27,183,0,0,15,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + KIROM { 1,0,0,0,0,0,0,4,0 } + KIRAM { 0,0,0,0,64,0,64,0,0 } + KXRAM { 0,0,0,0,0,0,0,0,0 } + KAOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + KCAFLG { 197,132,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + KCAMSC (INTERWORK) + KCADEF (KEIL_ARM7) + KCAUDF () + KCAINC (..\Common\include\;..\..\Source\include\;..\..\Source\portable\Keil\ARM7\) + KAAFLG { 20,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + KAAMSC () + KAASET () + KAARST () + KAAINC () + PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + IncBld=1 + AlwaysBuild=0 + GenAsm=0 + AsmAsm=0 + PublicsOnly=0 + StopCode=3 + CustArgs () + LibMods () + KLAFLG { 44,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + KLAMSC () + KLADWN (25) + KLACFI () + KLAASN () + KLARES () + KLACCL () + KLAUCL () + KLACSC () + KLAUCS () + OPTDL (SARM.DLL)(-cLPC2100)(DARMP.DLL)(-pLPC21x9)(SARM.DLL)()(TARMP.DLL)(-pLPC21x9) + OPTDBG 44029,-1,()()()()()()()()()() (BIN\UL2ARM.DLL)()()() + FLASH1 { 1,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + FLASH2 (BIN\UL2ARM.DLL) + FLASH3 ("LPC210x_ISP.EXE" ("#H" ^X $D COM1: 9600 1)) + FLASH4 () +EndOpt + diff --git a/20080212/Demo/ARM7_LPC2129_Keil/rtosdemo_THUMB.Opt b/20080212/Demo/ARM7_LPC2129_Keil/rtosdemo_THUMB.Opt new file mode 100644 index 000000000..39909fa34 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2129_Keil/rtosdemo_THUMB.Opt @@ -0,0 +1,63 @@ +### uVision2 Project, (C) Keil Software +### Do not modify ! + + cExt (*.c) + aExt (*.s*; *.src; *.a*) + oExt (*.obj) + lExt (*.lib) + tExt (*.txt; *.h; *.inc) + pExt (*.plm) + CppX (*.cpp) + DaveTm { 0,0,0,0,0,0,0,0 } + +Target (FreeRTOS), 0x0005 // Tools: '' +GRPOPT 1,(THUMB_DEMO),1,0,0 + +OPTFFF 1,1,1,1,0,121,137,0,<.\main.c> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,228,255,255,255,0,0,0,0,0,0,0,0,14,4,0,0,75,2,0,0 } +OPTFFF 1,2,2,0,0,0,0,0,<.\Startup.s> +OPTFFF 1,3,1,1040187392,0,0,0,0,<.\ParTest\ParTest.c> +OPTFFF 1,4,1,0,0,0,0,0,<.\serial\serial.c> +OPTFFF 1,5,1,0,0,0,0,0,<.\serial\serialISR.c> +OPTFFF 1,6,1,0,0,0,0,0,<..\..\Source\tasks.c> +OPTFFF 1,7,1,0,0,0,0,0,<..\..\Source\queue.c> +OPTFFF 1,8,1,0,0,0,0,0,<..\..\Source\list.c> +OPTFFF 1,9,1,553648128,0,0,0,0,<..\..\Source\portable\Keil\ARM7\port.c> +OPTFFF 1,10,1,0,0,0,0,0,<..\..\Source\portable\Keil\ARM7\portISR.c> +OPTFFF 1,11,1,0,0,0,0,0,<..\Common\Minimal\BlockQ.c> +OPTFFF 1,12,1,402653184,0,0,0,0,<..\Common\Minimal\semtest.c> +OPTFFF 1,13,1,0,0,0,0,0,<..\Common\Minimal\PollQ.c> +OPTFFF 1,14,1,0,0,0,0,0,<..\Common\Minimal\flash.c> +OPTFFF 1,15,1,0,0,0,0,0,<..\Common\Minimal\comtest.c> +OPTFFF 1,16,1,0,0,0,0,0,<..\Common\Minimal\integer.c> +OPTFFF 1,17,1,0,0,0,0,0,<..\..\Source\portable\MemMang\heap_2.c> +OPTFFF 1,18,1,0,0,0,0,0,<..\Common\Minimal\dynamic.c> + +ExtF <..\..\SOURCE\PORTABLE\KEIL\ARM7\PORTMACRO.H> 127,127,0,{ 44,0,0,0,2,0,0,0,3,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,228,255,255,255,27,0,0,0,27,0,0,0,72,4,0,0,33,2,0,0 } + +TARGOPT 1, (FreeRTOS) + KACLK=12000000 + OPTTT 1,1,1,0 + OPTHX 0,65535,0,0,0 + OPTLX 120,65,8,<.\> + OPTOX 16 + OPTLT 1,1,1,0,1,1,0,1,0,0,0,0 + OPTXL 1,1,1,1,1,1,1,0,0 + OPTFL 1,0,1 + OPTBL 0,(Data Sheet) + OPTBL 1,(User Manual) + OPTDL (SARM.DLL)(-cLPC2100)(DARMP.DLL)(-pLPC21x9)(SARM.DLL)()(TARMP.DLL)(-pLPC21x9) + OPTDBG 44029,-1,()()()()()()()()()() (BIN\UL2ARM.DLL)()()() + OPTKEY 0,(DLGTARM)((134=-1,-1,-1,-1,0)(135=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(108=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(80=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(113=-1,-1,-1,-1,0)(112=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0)(117=-1,-1,-1,-1,0)(118=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(119=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(115=-1,-1,-1,-1,0)(116=-1,-1,-1,-1,0)) + OPTKEY 0,(UL2ARM)(-U170927308 -O7 -S0 -C0 -N00("ARM7TDMI-S Core") -D00(4F1F0F0F) -L00(4) -FO7 -FD40000000 -FC800 -FN1 -FF0LPC_IAP_256 -FS00 -FL03E000) + OPTKEY 0,(DLGDARM)((134=-1,-1,-1,-1,0)(135=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(108=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(80=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(113=-1,-1,-1,-1,0)(112=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0)(117=-1,-1,-1,-1,0)(118=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(119=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(115=-1,-1,-1,-1,0)(116=-1,-1,-1,-1,0)) + OPTKEY 0,(ARMDBGFLAGS)(-T5F) + OPTMM 1,0,(0x40000840) + OPTDF 0x1000086 + OPTLE <> + OPTLC <> + OPTLA 0,((Port1 & 0x10000) >> 16)(0000FF000000000000000000000000000000F0BF010000006400000000743BA40B000000506F7274310000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000001C030000) + OPTLA 1,((Port1 & 0x20000) >> 17)(0000FF000000000000000000000000000000F0BF010000006400000000743BA40B000000506F7274310000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000001C030000) + OPTLA 2,((Port1 & 0x40000) >> 18)(0000FF000000000000000000000000000000F0BF010000006400000000743BA40B000000506F7274310000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000001C030000) + OPTLA 3,((Port1 & 0x80000) >> 19)(0000FF000000000000000000000000000000F0BF010000006400000000743BA40B000000506F7274310000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000001C030000) +EndOpt + diff --git a/20080212/Demo/ARM7_LPC2129_Keil/rtosdemo_THUMB.Uv2 b/20080212/Demo/ARM7_LPC2129_Keil/rtosdemo_THUMB.Uv2 new file mode 100644 index 000000000..8e6cb20e7 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2129_Keil/rtosdemo_THUMB.Uv2 @@ -0,0 +1,110 @@ +### uVision2 Project, (C) Keil Software +### Do not modify ! + +Target (FreeRTOS), 0x0005 // Tools: '' + +Group (THUMB_DEMO) + +File 1,1,<.\main.c> 0x4162D96A +File 1,2,<.\Startup.s> 0x415AF382 +File 1,1,<.\ParTest\ParTest.c> 0x415AF50E +File 1,1,<.\serial\serial.c> 0x4162D488 +File 1,1,<.\serial\serialISR.c> 0x4162D404 +File 1,1,<..\..\Source\tasks.c> 0x4162D9E6 +File 1,1,<..\..\Source\queue.c> 0x411B5F14 +File 1,1,<..\..\Source\list.c> 0x411B5F24 +File 1,1,<..\..\Source\portable\Keil\ARM7\port.c> 0x4162D434 +File 1,1,<..\..\Source\portable\Keil\ARM7\portISR.c> 0x415A85E0 +File 1,1,<..\Common\Minimal\BlockQ.c> 0x411B5F8C +File 1,1,<..\Common\Minimal\semtest.c> 0x411B5F8C +File 1,1,<..\Common\Minimal\PollQ.c> 0x411B5F8E +File 1,1,<..\Common\Minimal\flash.c> 0x411B5F8E +File 1,1,<..\Common\Minimal\comtest.c> 0x413335E6 +File 1,1,<..\Common\Minimal\integer.c> 0x415FB7EE +File 1,1,<..\..\Source\portable\MemMang\heap_2.c> 0x0 +File 1,1,<..\Common\Minimal\dynamic.c> 0x0 + + +Options 1,0,0 // Target 'FreeRTOS' + Device (LPC2129) + Vendor (Philips) + Cpu (IRAM(0x40000000-0x40003FFF) IROM(0-0x3FFFF) CLOCK(12000000) CPUTYPE(ARM7TDMI)) + FlashUt (LPC210x_ISP.EXE ("#H" ^X $D COM1: 9600 1)) + StupF ("STARTUP\Philips\Startup.s" ("Philips LPC2100 Startup Code")) + FlashDR (UL2ARM(-U40296420 -O7 -C0 -FO7 -FD40000000 -FC800 -FN1 -FF0LPC_IAP_256 -FS00 -FL03E000)) + Rgf (LPC21xx.H) + Mem () + C () + A () + RL () + OH () + DBC_IFX () + DBC_CMS () + DBC_AMS () + DBC_LMS () + UseEnv=0 + EnvBin (D:\DevTools\Keil\arm\ARM\BIN\) + EnvInc () + EnvLib () + EnvReg (ÿPhilips\) + OrgReg (ÿPhilips\) + TgStat=16 + OutDir (.\) + OutName (rtosdemo_THUMB) + GenApp=1 + GenLib=0 + GenHex=0 + Debug=1 + Browse=0 + LstDir (.\) + HexSel=0 + MG32K=0 + TGMORE=0 + RunUsr 0 0 <> + RunUsr 1 0 <> + BrunUsr 0 0 <> + BrunUsr 1 0 <> + SVCSID <> + KACPU (ARM7TDMI) + TKAFL { 0,27,183,0,0,15,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + KIROM { 1,0,0,0,0,0,0,4,0 } + KIRAM { 0,0,0,0,64,0,64,0,0 } + KXRAM { 0,0,0,0,0,0,0,0,0 } + KAOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + KCAFLG { 197,156,20,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + KCAMSC (INTERWORK) + KCADEF (KEIL_ARM7 KEIL_THUMB_INTERWORK) + KCAUDF () + KCAINC (..\Common\include\;..\..\Source\include\;..\..\Source\portable\Keil\ARM7\) + KAAFLG { 20,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + KAAMSC () + KAASET () + KAARST () + KAAINC () + PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + IncBld=1 + AlwaysBuild=0 + GenAsm=0 + AsmAsm=0 + PublicsOnly=0 + StopCode=3 + CustArgs () + LibMods () + KLAFLG { 44,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + KLAMSC () + KLADWN (25) + KLACFI () + KLAASN () + KLARES () + KLACCL () + KLAUCL () + KLACSC () + KLAUCS () + OPTDL (SARM.DLL)(-cLPC2100)(DARMP.DLL)(-pLPC21x9)(SARM.DLL)()(TARMP.DLL)(-pLPC21x9) + OPTDBG 44029,-1,()()()()()()()()()() (BIN\UL2ARM.DLL)()()() + FLASH1 { 1,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + FLASH2 (BIN\UL2ARM.DLL) + FLASH3 ("LPC210x_ISP.EXE" ("#H" ^X $D COM1: 9600 1)) + FLASH4 () +EndOpt + diff --git a/20080212/Demo/ARM7_LPC2129_Keil/serial/serial.c b/20080212/Demo/ARM7_LPC2129_Keil/serial/serial.c new file mode 100644 index 000000000..078d68bf2 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2129_Keil/serial/serial.c @@ -0,0 +1,257 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +/* + BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0. + + This file contains all the serial port components that can be compiled to + either ARM or THUMB mode. Components that must be compiled to ARM mode are + contained in serialISR.c. +*/ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "queue.h" +#include "task.h" + +/* Demo application includes. */ +#include "serial.h" + +/*-----------------------------------------------------------*/ + +/* Constants to setup and access the UART. */ +#define serDLAB ( ( unsigned portCHAR ) 0x80 ) +#define serENABLE_INTERRUPTS ( ( unsigned portCHAR ) 0x03 ) +#define serNO_PARITY ( ( unsigned portCHAR ) 0x00 ) +#define ser1_STOP_BIT ( ( unsigned portCHAR ) 0x00 ) +#define ser8_BIT_CHARS ( ( unsigned portCHAR ) 0x03 ) +#define serFIFO_ON ( ( unsigned portCHAR ) 0x01 ) +#define serCLEAR_FIFO ( ( unsigned portCHAR ) 0x06 ) +#define serWANTED_CLOCK_SCALING ( ( unsigned portLONG ) 16 ) + +/* Constants to setup and access the VIC. */ +#define serU0VIC_CHANNEL ( ( unsigned portLONG ) 0x0006 ) +#define serU0VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x0040 ) +#define serU0VIC_ENABLE ( ( unsigned portLONG ) 0x0020 ) + +/* Misc. */ +#define serINVALID_QUEUE ( ( xQueueHandle ) 0 ) +#define serHANDLE ( ( xComPortHandle ) 1 ) +#define serNO_BLOCK ( ( portTickType ) 0 ) + +/*-----------------------------------------------------------*/ + +/* Queues used to hold received characters, and characters waiting to be +transmitted. */ +static xQueueHandle xRxedChars; +static xQueueHandle xCharsForTx; + +/*-----------------------------------------------------------*/ + +/* Communication flag between the interrupt service routine and serial API. */ +static volatile portLONG *plTHREEmpty; + +/* + * The queues are created in serialISR.c as they are used from the ISR. + * Obtain references to the queues and THRE Empty flag. + */ +extern void vSerialISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars, xQueueHandle *pxCharsForTx, portLONG volatile **pplTHREEmptyFlag ); + +/*-----------------------------------------------------------*/ + +xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) +{ +unsigned portLONG ulDivisor, ulWantedClock; +xComPortHandle xReturn = serHANDLE; + + /* The queues are used in the serial ISR routine, so are created from + serialISR.c (which is always compiled to ARM mode). */ + vSerialISRCreateQueues( uxQueueLength, &xRxedChars, &xCharsForTx, &plTHREEmpty ); + + if( + ( xRxedChars != serINVALID_QUEUE ) && + ( xCharsForTx != serINVALID_QUEUE ) && + ( ulWantedBaud != ( unsigned portLONG ) 0 ) + ) + { + portENTER_CRITICAL(); + { + /* The reference to the ISR function is required to load into the + interrupt controller. The prototype is slightly different + depending on whether in ARM or THUMB mode. */ + #ifdef KEIL_THUMB_INTERWORK + extern void ( vUART_ISR )( void ) __arm __task; + #else + extern void ( vUART_ISR )( void ) __task; + #endif + + /* Setup the baud rate: Calculate the divisor value. */ + ulWantedClock = ulWantedBaud * serWANTED_CLOCK_SCALING; + ulDivisor = configCPU_CLOCK_HZ / ulWantedClock; + + /* Set the DLAB bit so we can access the divisor. */ + U0LCR |= serDLAB; + + /* Setup the divisor. */ + U0DLL = ( unsigned portCHAR ) ( ulDivisor & ( unsigned portLONG ) 0xff ); + ulDivisor >>= 8; + U0DLM = ( unsigned portCHAR ) ( ulDivisor & ( unsigned portLONG ) 0xff ); + + /* Turn on the FIFO's and clear the buffers. */ + U0FCR = ( serFIFO_ON | serCLEAR_FIFO ); + + /* Setup transmission format. */ + U0LCR = serNO_PARITY | ser1_STOP_BIT | ser8_BIT_CHARS; + + /* Setup the VIC for the UART. */ + VICIntSelect &= ~( serU0VIC_CHANNEL_BIT ); + VICIntEnable |= serU0VIC_CHANNEL_BIT; + VICVectAddr1 = ( unsigned portLONG ) vUART_ISR; + VICVectCntl1 = serU0VIC_CHANNEL | serU0VIC_ENABLE; + + /* Enable UART0 interrupts. */ + U0IER |= serENABLE_INTERRUPTS; + } + portEXIT_CRITICAL(); + } + else + { + xReturn = ( xComPortHandle ) 0; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) +{ + /* The port handle is not required as this driver only supports UART0. */ + ( void ) pxPort; + + /* Get the next character from the buffer. Return false if no characters + are available, or arrive before xBlockTime expires. */ + if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) + { + return pdTRUE; + } + else + { + return pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength ) +{ +signed portCHAR *pxNext; + + /* NOTE: This implementation does not handle the queue being full as no + block time is used! */ + + /* The port handle is not required as this driver only supports UART0. */ + ( void ) pxPort; + ( void ) usStringLength; + + /* Send each character in the string, one at a time. */ + pxNext = ( signed portCHAR * ) pcString; + while( *pxNext ) + { + xSerialPutChar( pxPort, *pxNext, serNO_BLOCK ); + pxNext++; + } +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) +{ +signed portBASE_TYPE xReturn; + + /* The port handle is not required as this driver only supports UART0. */ + ( void ) pxPort; + + portENTER_CRITICAL(); + { + /* Is there space to write directly to the UART? */ + if( *plTHREEmpty == ( portLONG ) pdTRUE ) + { + /* We wrote the character directly to the UART, so was + successful. */ + *plTHREEmpty = pdFALSE; + U0THR = cOutChar; + xReturn = pdPASS; + } + else + { + /* We cannot write directly to the UART, so queue the character. + Block for a maximum of xBlockTime if there is no space in the + queue. It is ok to block within a critical section as each + task has it's own critical section management. */ + xReturn = xQueueSend( xCharsForTx, &cOutChar, xBlockTime ); + + /* Depending on queue sizing and task prioritisation: While we + were blocked waiting to post interrupts were not disabled. It is + possible that the serial ISR has emptied the Tx queue, in which + case we need to start the Tx off again. */ + if( *plTHREEmpty == ( portLONG ) pdTRUE ) + { + xQueueReceive( xCharsForTx, &cOutChar, serNO_BLOCK ); + *plTHREEmpty = pdFALSE; + U0THR = cOutChar; + } + } + } + portEXIT_CRITICAL(); + + return xReturn; +} +/*-----------------------------------------------------------*/ + + + + + + + diff --git a/20080212/Demo/ARM7_LPC2129_Keil/serial/serialISR.c b/20080212/Demo/ARM7_LPC2129_Keil/serial/serialISR.c new file mode 100644 index 000000000..79073c19f --- /dev/null +++ b/20080212/Demo/ARM7_LPC2129_Keil/serial/serialISR.c @@ -0,0 +1,170 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +/* + BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0. + + This file contains all the serial port components that must be compiled + to ARM mode. The components that can be compiled to either ARM or THUMB + mode are contained in serial.c. +*/ + +/* This file must always be compiled to ARM mode as it contains ISR +definitions. */ +#pragma ARM + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "queue.h" +#include "task.h" + +/* Demo application includes. */ +#include "serial.h" + +/*-----------------------------------------------------------*/ + +/* Constant to access the VIC. */ +#define serCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 ) + +/* Constants to determine the ISR source. */ +#define serSOURCE_THRE ( ( unsigned portCHAR ) 0x02 ) +#define serSOURCE_RX_TIMEOUT ( ( unsigned portCHAR ) 0x0c ) +#define serSOURCE_ERROR ( ( unsigned portCHAR ) 0x06 ) +#define serSOURCE_RX ( ( unsigned portCHAR ) 0x04 ) +#define serINTERRUPT_SOURCE_MASK ( ( unsigned portCHAR ) 0x0f ) + +/* Queues used to hold received characters, and characters waiting to be +transmitted. */ +static xQueueHandle xRxedChars; +static xQueueHandle xCharsForTx; +static volatile portLONG lTHREEmpty; + +/*-----------------------------------------------------------*/ + +/* UART0 interrupt service routine. This can cause a context switch so MUST +be declared "naked". */ +void vUART_ISR( void ); + +/*-----------------------------------------------------------*/ +void vSerialISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars, + xQueueHandle *pxCharsForTx, portLONG volatile **pplTHREEmptyFlag ) +{ + /* Create the queues used to hold Rx and Tx characters. */ + xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + + /* Pass back a reference to the queues so the serial API file can + post/receive characters. */ + *pxRxedChars = xRxedChars; + *pxCharsForTx = xCharsForTx; + + /* Initialise the THRE empty flag - and pass back a reference. */ + lTHREEmpty = pdTRUE; + *pplTHREEmptyFlag = &lTHREEmpty; +} +/*-----------------------------------------------------------*/ + +void vUART_ISR( void ) __task +{ + portENTER_SWITCHING_ISR() + + /* Now we can declare the local variables. */ + static signed portCHAR cChar; + static portBASE_TYPE xTaskWokenByRx, xTaskWokenByTx; + + xTaskWokenByTx = pdFALSE; + xTaskWokenByRx = pdFALSE; + + /* What caused the interrupt? */ + switch( U0IIR & serINTERRUPT_SOURCE_MASK ) + { + case serSOURCE_ERROR : /* Not handling this, but clear the interrupt. */ + cChar = U0LSR; + break; + + case serSOURCE_THRE : /* The THRE is empty. If there is another + character in the Tx queue, send it now. */ + if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE ) + { + U0THR = cChar; + } + else + { + /* There are no further characters + queued to send so we can indicate + that the THRE is available. */ + lTHREEmpty = pdTRUE; + } + break; + + case serSOURCE_RX_TIMEOUT : + case serSOURCE_RX : /* A character was received. Place it in + the queue of received characters. */ + cChar = U0RBR; + if( xQueueSendFromISR( xRxedChars, &cChar, pdFALSE ) ) + { + xTaskWokenByRx = pdTRUE; + } + break; + + default : /* There is nothing to do, leave the ISR. */ + break; + } + + /* Clear the ISR in the VIC. */ + VICVectAddr = serCLEAR_VIC_INTERRUPT; + + /* Exit the ISR. If a task was woken by either a character being received + or transmitted then a context switch will occur. */ + portEXIT_SWITCHING_ISR( ( xTaskWokenByTx || xTaskWokenByRx ) ); +} +/*-----------------------------------------------------------*/ + + + + + + diff --git a/20080212/Demo/ARM7_LPC2138_Rowley/FreeRTOSConfig.h b/20080212/Demo/ARM7_LPC2138_Rowley/FreeRTOSConfig.h new file mode 100644 index 000000000..76fe2b327 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2138_Rowley/FreeRTOSConfig.h @@ -0,0 +1,100 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include +#define vPortYieldProcessor swi_handler + +/* For compatability with the LPC2106 header. */ +#define T0_IR T0IR +#define T0_PR T0PR +#define T0_MR0 T0MR0 +#define T0_MCR T0MCR +#define T0_TCR T0TCR + + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +/* In this case configCPU_CLOCK_HZ is actually set to the pclk frequency, not +the CPU frequency. */ +#define configCPU_CLOCK_HZ ( 58982400UL ) /* =14.7456MHz xtal multiplied by 4 using the PLL. */ +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 6 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 128 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 18 * 1024 ) ) +#define configMAX_TASK_NAME_LEN ( 15 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/ARM7_LPC2138_Rowley/RTOSDemo.hzp b/20080212/Demo/ARM7_LPC2138_Rowley/RTOSDemo.hzp new file mode 100644 index 000000000..175dd09b1 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2138_Rowley/RTOSDemo.hzp @@ -0,0 +1,56 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/20080212/Demo/ARM7_LPC2138_Rowley/RTOSDemo.hzs b/20080212/Demo/ARM7_LPC2138_Rowley/RTOSDemo.hzs new file mode 100644 index 000000000..1ac46d239 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2138_Rowley/RTOSDemo.hzs @@ -0,0 +1,101 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/20080212/Demo/ARM7_LPC2138_Rowley/main.c b/20080212/Demo/ARM7_LPC2138_Rowley/main.c new file mode 100644 index 000000000..1b3aa33c0 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2138_Rowley/main.c @@ -0,0 +1,374 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + * This file contains a demo created to execute on the Rowley Associates + * LPC2138 CrossFire development board. + * + * main() creates all the demo application tasks, then starts the scheduler. + * The WEB documentation provides more details of the standard demo application + * tasks. + * + * Main.c also creates a task called "Check". This only executes every few + * seconds but has a high priority so is guaranteed to get processor time. + * Its function is to check that all the other tasks are still operational. + * Each standard demo task maintains a unique count that is incremented each + * time the task successfully completes its function. Should any error occur + * within such a task the count is permanently halted. The check task inspects + * the count of each task to ensure it has changed since the last time the + * check task executed. If all the count variables have changed all the tasks + * are still executing error free, and the check task writes "PASS" to the + * CrossStudio terminal IO window. Should any task contain an error at any time + * the error is latched and "FAIL" written to the terminal IO window. + * + * Finally, main() sets up an interrupt service routine and task to handle + * pushes of the button that is built into the CrossFire board. When the button + * is pushed the ISR wakes the button task - which generates a table of task + * status information which is also displayed on the terminal IO window. + * + * A print task is defined to ensure exclusive and consistent access to the + * terminal IO. This is the only task that is allowed to access the terminal. + * The check and button task therefore do not access the terminal directly but + * instead pass a pointer to the message they wish to display to the print task. + */ + +/* Standard includes. */ +#include <__cross_studio_io.h> + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "Task.h" +#include "queue.h" +#include "semphr.h" + +/* Demo app includes. */ +#include "BlockQ.h" +#include "death.h" +#include "dynamic.h" +#include "integer.h" +#include "PollQ.h" +#include "blocktim.h" +#include "recmutex.h" + +/* Hardware configuration definitions. */ +#define mainBUS_CLK_FULL ( ( unsigned portCHAR ) 0x01 ) +#define mainLED_BIT 0x80000000 +#define mainP0_14__EINT_1 ( 2 << 28 ) +#define mainEINT_1_EDGE_SENSITIVE 2 +#define mainEINT_1_FALLING_EDGE_SENSITIVE 0 +#define mainEINT_1_CHANNEL 15 +#define mainEINT_1_VIC_CHANNEL_BIT ( 1 << mainEINT_1_CHANNEL ) +#define mainEINT_1_ENABLE_BIT ( 1 << 5 ) + +/* Demo application definitions. */ +#define mainQUEUE_SIZE ( 3 ) +#define mainLED_DELAY ( ( portTickType ) 500 / portTICK_RATE_MS ) +#define mainERROR_LED_DELAY ( ( portTickType ) 50 / portTICK_RATE_MS ) +#define mainCHECK_DELAY ( ( portTickType ) 5000 / portTICK_RATE_MS ) +#define mainLIST_BUFFER_SIZE 2048 +#define mainNO_DELAY ( 0 ) +#define mainSHORT_DELAY ( 150 / portTICK_RATE_MS ) + +/* Task priorities. */ +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainPRINT_TASK_PRIORITY ( tskIDLE_PRIORITY + 0 ) + +/*-----------------------------------------------------------*/ + +/* The semaphore used to wake the button task from within the external interrupt +handler. */ +xSemaphoreHandle xButtonSemaphore; + +/* The queue that is used to send message to vPrintTask for display in the +terminal output window. */ +xQueueHandle xPrintQueue; + +/* The rate at which the LED will toggle. The toggle rate increases if an +error is detected in any task. */ +static portTickType xLED_Delay = mainLED_DELAY; +/*-----------------------------------------------------------*/ + +/* + * Simply flashes the on board LED every mainLED_DELAY milliseconds. + */ +static void vLEDTask( void *pvParameters ); + +/* + * Checks the status of all the demo tasks then prints a message to the + * CrossStudio terminal IO windows. The message will be either PASS or FAIL + * depending on the status of the demo applications tasks. A FAIL status will + * be latched. + * + * Messages are not written directly to the terminal, but passed to vPrintTask + * via a queue. + */ +static void vCheckTask( void *pvParameters ); + +/* + * Controls all terminal output. If a task wants to send a message to the + * terminal IO it posts a pointer to the text to vPrintTask via a queue. This + * ensures serial access to the terminal IO. + */ +static void vPrintTask( void *pvParameter ); + +/* + * Simply waits for an interrupt to be generated from the built in button, then + * generates a table of tasks states that is then written by vPrintTask to the + * terminal output window within CrossStudio. + */ +static void vButtonHandlerTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + /* Setup the peripheral bus to be the same as the PLL output. */ + VPBDIV = mainBUS_CLK_FULL; + + /* Create the queue used to pass message to vPrintTask. */ + xPrintQueue = xQueueCreate( mainQUEUE_SIZE, sizeof( portCHAR * ) ); + + /* Create the semaphore used to wake vButtonHandlerTask(). */ + vSemaphoreCreateBinary( xButtonSemaphore ); + xSemaphoreTake( xButtonSemaphore, 0 ); + + /* Start the standard demo tasks. */ + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartDynamicPriorityTasks(); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + + #if configUSE_PREEMPTION == 1 + { + /* The timing of console output when not using the preemptive + scheduler causes the block time tests to detect a timing problem. */ + vCreateBlockTimeTasks(); + } + #endif + + vStartRecursiveMutexTasks(); + + /* Start the tasks defined within this file. */ + xTaskCreate( vLEDTask, "LED", configMINIMAL_STACK_SIZE, NULL, mainLED_TASK_PRIORITY, NULL ); + xTaskCreate( vCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + xTaskCreate( vPrintTask, "Print", configMINIMAL_STACK_SIZE, NULL, mainPRINT_TASK_PRIORITY, NULL ); + xTaskCreate( vButtonHandlerTask, "Button", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* The scheduler should now be running, so we will only ever reach here if we + ran out of heap space. */ + + return 0; +} +/*-----------------------------------------------------------*/ + +static void vLEDTask( void *pvParameters ) +{ + /* Configure IO. */ + IO0DIR |= mainLED_BIT; + IO0SET = mainLED_BIT; + + for( ;; ) + { + /* Not very exiting - just delay... */ + vTaskDelay( xLED_Delay ); + + /* ...set the IO ... */ + IO0CLR = mainLED_BIT; + + /* ...delay again... */ + vTaskDelay( xLED_Delay ); + + /* ...then clear the IO. */ + IO0SET = mainLED_BIT; + } +} +/*-----------------------------------------------------------*/ + +static void vCheckTask( void *pvParameters ) +{ +portBASE_TYPE xErrorOccurred = pdFALSE; +portTickType xLastExecutionTime; +const portCHAR * const pcPassMessage = "PASS\n"; +const portCHAR * const pcFailMessage = "FAIL\n"; + + /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() + works correctly. */ + xLastExecutionTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Perform this check every mainCHECK_DELAY milliseconds. */ + vTaskDelayUntil( &xLastExecutionTime, mainCHECK_DELAY ); + + /* Has an error been found in any task? */ + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + #if configUSE_PREEMPTION == 1 + { + /* The timing of console output when not using the preemptive + scheduler causes the block time tests to detect a timing problem. */ + if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + } + #endif + + if( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + /* Send either a pass or fail message. If an error is found it is + never cleared again. */ + if( xErrorOccurred == pdTRUE ) + { + xLED_Delay = mainERROR_LED_DELAY; + xQueueSend( xPrintQueue, &pcFailMessage, portMAX_DELAY ); + } + else + { + xQueueSend( xPrintQueue, &pcPassMessage, portMAX_DELAY ); + } + } +} +/*-----------------------------------------------------------*/ + +static void vPrintTask( void *pvParameters ) +{ +portCHAR *pcMessage; + + for( ;; ) + { + /* Wait for a message to arrive. */ + while( xQueueReceive( xPrintQueue, &pcMessage, portMAX_DELAY ) != pdPASS ); + + /* Write the message to the terminal IO. */ + #ifndef NDEBUG + debug_printf( "%s", pcMessage ); + #endif + } +} +/*-----------------------------------------------------------*/ + +static void vButtonHandlerTask( void *pvParameters ) +{ +static portCHAR cListBuffer[ mainLIST_BUFFER_SIZE ]; +const portCHAR *pcList = &( cListBuffer[ 0 ] ); +const portCHAR * const pcHeader = "\nTask State Priority Stack #\n************************************************"; +extern void (vButtonISRWrapper) ( void ); + + /* Configure the interrupt. */ + portENTER_CRITICAL(); + { + /* Configure P0.14 to generate interrupts. */ + PINSEL0 |= mainP0_14__EINT_1; + EXTMODE = mainEINT_1_EDGE_SENSITIVE; + EXTPOLAR = mainEINT_1_FALLING_EDGE_SENSITIVE; + + /* Setup the VIC for EINT 1. */ + VICIntSelect &= ~mainEINT_1_VIC_CHANNEL_BIT; + VICIntEnable |= mainEINT_1_VIC_CHANNEL_BIT; + VICVectAddr1 = ( portLONG ) vButtonISRWrapper; + VICVectCntl1 = mainEINT_1_ENABLE_BIT | mainEINT_1_CHANNEL; + } + portEXIT_CRITICAL(); + + for( ;; ) + { + /* For debouncing, wait a while then clear the semaphore. */ + vTaskDelay( mainSHORT_DELAY ); + xSemaphoreTake( xButtonSemaphore, mainNO_DELAY ); + + /* Wait for an interrupt. */ + xSemaphoreTake( xButtonSemaphore, portMAX_DELAY ); + + /* Send the column headers to the print task for display. */ + xQueueSend( xPrintQueue, &pcHeader, portMAX_DELAY ); + + /* Create the list of task states. */ + vTaskList( cListBuffer ); + + /* Send the task status information to the print task for display. */ + xQueueSend( xPrintQueue, &pcList, portMAX_DELAY ); + } +} +/*-----------------------------------------------------------*/ + + + + + + + diff --git a/20080212/Demo/ARM7_LPC2138_Rowley/mainISR.c b/20080212/Demo/ARM7_LPC2138_Rowley/mainISR.c new file mode 100644 index 000000000..cd0b1803d --- /dev/null +++ b/20080212/Demo/ARM7_LPC2138_Rowley/mainISR.c @@ -0,0 +1,89 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ +#include "FreeRTOS.h" +#include "semphr.h" + +#define isrCLEAR_EINT_1 2 + +/* + * Interrupt routine that simply wakes vButtonHandlerTask on each interrupt + * generated by a push of the built in button. The wrapper takes care of + * the ISR entry. This then calls the actual handler function to perform + * the work. This work should not be done in the wrapper itself unless + * you are absolutely sure that no stack space is used. + */ +void vButtonISRWrapper( void ) __attribute__ ((naked)); +void vButtonHandler( void ); + +void vButtonHandler( void ) +{ +extern xSemaphoreHandle xButtonSemaphore; + + if( xSemaphoreGiveFromISR( xButtonSemaphore, pdFALSE ) ) + { + /* We have woken a task. Calling "yield from ISR" here will ensure + the interrupt returns to the woken task if it has a priority higher + than the interrupted task. */ + portYIELD_FROM_ISR(); + } + + EXTINT = isrCLEAR_EINT_1; + VICVectAddr = 0; +} +/*-----------------------------------------------------------*/ + +void vButtonISRWrapper( void ) +{ + /* Save the context of the interrupted task. */ + portSAVE_CONTEXT(); + + /* Call the handler to do the work. This must be a separate function to + the wrapper to ensure the correct stack frame is set up. */ + vButtonHandler(); + + /* Restore the context of whichever task is going to run once the interrupt + completes. */ + portRESTORE_CONTEXT(); +} + + + diff --git a/20080212/Demo/ARM7_LPC2138_Rowley/threads.js b/20080212/Demo/ARM7_LPC2138_Rowley/threads.js new file mode 100644 index 000000000..a790baf78 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2138_Rowley/threads.js @@ -0,0 +1,118 @@ +function decode_stack(sp) +{ + var i; + var a = new Array(); + + var current_task; + + current_task = Debug.evaluate("pxCurrentTCB"); + + if( current_task == 0 ) + return; + + sp += 4; /* skip stored ulCriticalNesting */ + a[16] = Debug.evaluate("*(unsigned long*)" + sp); + + for (i = 0; i <= 15; i++) + { + sp += 4; + a[i] = Debug.evaluate("*(unsigned long*)" + sp); + } + + return a; +} + +function add_task(task, state) +{ + var tcb, task_name; + + var current_task; + + current_task = Debug.evaluate("pxCurrentTCB"); + + if( current_task == 0 ) + return; + + tcb = Debug.evaluate("*(tskTCB *)" + task); + task_name = Debug.evaluate("(char*)&(*(tskTCB *)" + task + ").pcTaskName[0]"); + Threads.add("#" + tcb.uxTCBNumber + " \"" + task_name + "\"", tcb.uxPriority, state, decode_stack(tcb.pxTopOfStack)); +} + +function add_list(list, state, current_task) +{ + var i, index, item, end; + var current_task; + + current_task = Debug.evaluate("pxCurrentTCB"); + + if( current_task == 0 ) + return; + + if (list.uxNumberOfItems) + { + index = list.pxIndex; + end = list.xListEnd; + for (i = 0; i < list.uxNumberOfItems; i++) + { + item = Debug.evaluate("*(xListItem *)" + index); + if (index != end) + { + task = item.pvOwner; + if (task) add_task(task, (task == current_task) ? "executing" : state); + } + index = item.pxNext; + } + } +} + +function update() +{ + var i, current_task, list, lists, max_priority; + + Threads.clear(); + + current_task = Debug.evaluate("pxCurrentTCB"); + + if( current_task == 0 ) + return; + + Threads.newqueue("Ready"); + lists = Debug.evaluate("pxReadyTasksLists"); + if (lists) + { + max_priority = Debug.evaluate("uxTopUsedPriority"); + max_priority = Debug.evaluate("*(long *)" + max_priority); + + for (i = 0; i <= max_priority; i++) + { + list = Debug.evaluate("((xList*)" + lists + ")[" + (max_priority - i) + "]"); + add_list(list, "ready", current_task); + } + } + + Threads.newqueue("Blocked"); + + list = Debug.evaluate("pxDelayedTaskList"); + if (list) + { + list = Debug.evaluate("**(xList **)" + list); + add_list(list, "blocked"); + } + + list = Debug.evaluate("pxOverflowDelayedTaskList"); + if (list) + { + list = Debug.evaluate("**(xList **)" + list); + add_list(list, "blocked"); + } + + Threads.newqueue("Suspended"); + + list = Debug.evaluate("xSuspendedTaskList"); + if (list) + { + list = Debug.evaluate("*(xList *)" + list); + add_list(list, "suspended"); + } +} + diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.cdt.core/shareddefaults.xml b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.cdt.core/shareddefaults.xml new file mode 100644 index 000000000..c4b91cfab --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.cdt.core/shareddefaults.xml @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.cdt.make.core/RTOSDemo.sc b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.cdt.make.core/RTOSDemo.sc new file mode 100644 index 000000000..6643763dc --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.cdt.make.core/RTOSDemo.sc @@ -0,0 +1,155 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.cdt.make.core/specs.c b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.cdt.make.core/specs.c new file mode 100644 index 000000000..8b1378917 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.cdt.make.core/specs.c @@ -0,0 +1 @@ + diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.cdt.make.core/specs.cpp b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.cdt.make.core/specs.cpp new file mode 100644 index 000000000..8b1378917 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.cdt.make.core/specs.cpp @@ -0,0 +1 @@ + diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.cdt.make.ui/dialog_settings.xml b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.cdt.make.ui/dialog_settings.xml new file mode 100644 index 000000000..9e62c4bb5 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.cdt.make.ui/dialog_settings.xml @@ -0,0 +1,5 @@ + +
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b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-RTOSDemo.prefs new file mode 100644 index 000000000..bb305ff00 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-RTOSDemo.prefs @@ -0,0 +1,3 @@ +#Sun Aug 19 15:20:24 BST 2007 +eclipse.preferences.version=1 +indexer/preferenceScope=0 diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.core.prefs b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.core.prefs new file mode 100644 index 000000000..1c0fdf149 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.core.prefs @@ -0,0 +1,3 @@ +#Sun Aug 19 15:19:23 BST 2007 +org.eclipse.cdt.debug.core.cDebug.common_source_containers=\r\n\r\n\r\n\r\n +eclipse.preferences.version=1 diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.ui.prefs b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.ui.prefs new file mode 100644 index 000000000..962a2b7ac --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.ui.prefs @@ -0,0 +1,5 @@ +#Sun Aug 19 23:06:50 BST 2007 +pref_state_memento.org.eclipse.cdt.debug.ui.ModulesView=\r\n +eclipse.preferences.version=1 +org.eclipse.debug.ui.DebugView.org.eclipse.cdt.debug.ui.cDebug.show_full_paths=true +org.eclipse.debug.ui.BreakpointView.org.eclipse.cdt.debug.ui.cDebug.show_full_paths=true diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.managedbuilder.core.prefs new file mode 100644 index 000000000..aa0ab5b81 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.managedbuilder.core.prefs @@ -0,0 +1,3 @@ +#Sun Sep 02 21:22:35 BST 2007 +eclipse.preferences.version=1 +properties/RTOSDemo.null.976634949/0.1109417601=\#\r\n\#Sun Sep 02 21\:22\:35 BST 2007\r\n0.1109417601\=\\\#\\r\\n\\\#Sun Sep 02 21\\\:22\\\:35 BST 2007\\r\\nrcState\\\=0\\r\\nrebuildState\\\=false\\r\\n\r\norg.eclipse.cdt.build.core.settings.holder.1502006385\=\\\#\\r\\n\\\#Sun Sep 02 21\\\:22\\\:35 BST 2007\\r\\nrebuildState\\\=false\\r\\n\r\norg.eclipse.cdt.build.core.settings.holder.1021181093\=\\\#\\r\\n\\\#Sun Sep 02 21\\\:22\\\:35 BST 2007\\r\\nrebuildState\\\=false\\r\\n\r\norg.eclipse.cdt.build.core.settings.holder.164584712\=\\\#\\r\\n\\\#Sun Sep 02 21\\\:22\\\:35 BST 2007\\r\\nrebuildState\\\=false\\r\\n\r\norg.eclipse.cdt.build.core.settings.holder.libs.260784574\=\\\#\\r\\n\\\#Sun Sep 02 21\\\:22\\\:35 BST 2007\\r\\nrebuildState\\\=false\\r\\n\r\norg.eclipse.cdt.build.core.prefbase.toolchain.1816209921\=\\\#\\r\\n\\\#Sun Sep 02 21\\\:22\\\:35 BST 2007\\r\\nrebuildState\\\=false\\r\\n\r\n diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prefs b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prefs new file mode 100644 index 000000000..8a970dac4 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prefs @@ -0,0 +1,12 @@ +#Thu Aug 23 20:22:58 BST 2007 +useQuickDiffPrefPage=true +closeBrackets=false +ensureNewlineAtEOF=true +useAnnotationsPrefPage=true +closeAngularBrackets=false +eclipse.preferences.version=1 +org.eclipse.cdt.ui.text.templates.custom= +hoverModifierMasks=org.eclipse.cdt.ui.BestMatchHover;0;org.eclipse.cdt.ui.CSourceHover;131072;org.eclipse.cdt.debug.internal.ui.editors.DebugTextHover;0;org.eclipse.cdt.ui.CDocHover;0;org.eclipse.cdt.ui.AnnotationHover;0; +hoverModifiers=org.eclipse.cdt.ui.BestMatchHover;0;org.eclipse.cdt.ui.CSourceHover;Shift;org.eclipse.cdt.debug.internal.ui.editors.DebugTextHover;\!0;org.eclipse.cdt.ui.CDocHover;\!0;org.eclipse.cdt.ui.AnnotationHover;\!0; +closeBraces=false +closeStrings=false diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.core.resources.prefs b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 000000000..242e94194 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,5 @@ +#Fri Aug 31 14:25:00 BST 2007 +version=1 +eclipse.preferences.version=1 +pathvariable.FreeRTOS_ROOT=C\:/E/Dev/FreeRTOS +description.autobuilding=false diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.core.prefs b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.core.prefs new file mode 100644 index 000000000..205a07217 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.core.prefs @@ -0,0 +1,3 @@ +#Sun Sep 02 17:49:35 BST 2007 +prefWatchExpressions=\r\n\r\n\r\n\r\n +eclipse.preferences.version=1 diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs new file mode 100644 index 000000000..53bcfe87a --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs @@ -0,0 +1,12 @@ +#Sun Sep 02 17:49:35 BST 2007 +org.eclipse.debug.ui.PREF_FILTER_WORKING_SETS=false +org.eclipse.debug.ui.PREF_LAUNCH_PERSPECTIVES=\r\n\r\n +org.eclipse.debug.ui.BreakpointView+org.eclipse.debug.ui.ShowSupportedBreakpointsAction=true +pref_state_memento.org.eclipse.debug.ui.VariableView=\r\n +pref_state_memento.org.eclipse.debug.ui.RegisterView=\r\n +pref_state_memento.org.eclipse.debug.ui.ExpressionView=\r\n +org.eclipse.debug.ui.PREF_FILTER_LAUNCH_CLOSED=false +preferredDetailPanes=DefaultDetailPane\:DefaultDetailPane| +org.eclipse.debug.ui.PREF_FILTER_LAUNCH_DELETED=false +eclipse.preferences.version=1 +org.eclipse.debug.ui.user_view_bindings=\r\n\r\n\r\n\r\n\r\n\r\n diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.help.ui.prefs b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.help.ui.prefs new file mode 100644 index 000000000..8d1b31164 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.help.ui.prefs @@ -0,0 +1,7 @@ +#Sun Aug 26 17:32:13 BST 2007 +browser.x=177 +browser.w=1024 +eclipse.preferences.version=1 +browser.h=768 +browser.maximized=false +browser.y=128 diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.search.prefs b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.search.prefs new file mode 100644 index 000000000..2426c2b79 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.search.prefs @@ -0,0 +1,3 @@ +#Sun Aug 19 19:39:29 BST 2007 +org.eclipse.search.defaultPerspective=org.eclipse.search.defaultPerspective.none +eclipse.preferences.version=1 diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.team.ui.prefs b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.team.ui.prefs new file mode 100644 index 000000000..06f8f1043 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.team.ui.prefs @@ -0,0 +1,3 @@ +#Fri Aug 31 18:19:04 BST 2007 +eclipse.preferences.version=1 +org.eclipse.team.ui.first_time=false diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.editors.prefs b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.editors.prefs new file mode 100644 index 000000000..1affd268e --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.editors.prefs @@ -0,0 +1,3 @@ +#Sun Aug 19 20:45:57 BST 2007 +eclipse.preferences.version=1 +overviewRuler_migration=migrated_3.1 diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.ide.prefs b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.ide.prefs new file mode 100644 index 000000000..b6611b723 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.ide.prefs @@ -0,0 +1,4 @@ +#Fri Aug 31 14:27:00 BST 2007 +eclipse.preferences.version=1 +tipsAndTricks=true +platformState=1187207632230 diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.prefs b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.prefs new file mode 100644 index 000000000..3e5b2b17d --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.prefs @@ -0,0 +1,3 @@ +#Sun Aug 19 20:45:58 BST 2007 +eclipse.preferences.version=1 +showIntro=false diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.workbench.prefs b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.workbench.prefs new file mode 100644 index 000000000..06cd1e9cd --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.workbench.prefs @@ -0,0 +1,3 @@ +#Mon Aug 20 21:59:49 BST 2007 +eclipse.preferences.version=1 +org.eclipse.ui.commands=\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.debug.core/.launches/OpenOCD Programmer.launch b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.debug.core/.launches/OpenOCD Programmer.launch new file mode 100644 index 000000000..4175eca53 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.debug.core/.launches/OpenOCD Programmer.launch @@ -0,0 +1,7 @@ + + + + + + + diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.debug.core/.launches/OpenOCD Server.launch b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.debug.core/.launches/OpenOCD Server.launch new file mode 100644 index 000000000..f70d8f970 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.debug.core/.launches/OpenOCD Server.launch @@ -0,0 +1,7 @@ + + + + + + + diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.debug.core/.launches/RTOSDemo.launch b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.debug.core/.launches/RTOSDemo.launch new file mode 100644 index 000000000..acc651f5b --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.debug.core/.launches/RTOSDemo.launch @@ -0,0 +1,26 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.debug.ui/dialog_settings.xml b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.debug.ui/dialog_settings.xml new file mode 100644 index 000000000..4b1222134 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.debug.ui/dialog_settings.xml @@ -0,0 +1,34 @@ + +
+
+ + + + + +
+
+ + + + + + + + +
+
+ + + + + +
+
+ + + + + +
+
diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.debug.ui/launchConfigurationHistory.xml b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.debug.ui/launchConfigurationHistory.xml new file mode 100644 index 000000000..598b376c8 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.debug.ui/launchConfigurationHistory.xml @@ -0,0 +1,24 @@ + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.help.ui/dialog_settings.xml b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.help.ui/dialog_settings.xml new file mode 100644 index 000000000..1ef2b05b5 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.help.ui/dialog_settings.xml @@ -0,0 +1,3 @@ + +
+
diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.help.ui/scope_sets/Default.pref b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.help.ui/scope_sets/Default.pref new file mode 100644 index 000000000..fc158177d --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.help.ui/scope_sets/Default.pref @@ -0,0 +1,2 @@ +#Sun Aug 26 17:54:18 BST 2007 +__DEFAULT__=true diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.help.ui/scope_sets/relative_path.hist b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.help.ui/scope_sets/relative_path.hist new file mode 100644 index 000000000..713e72168 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.help.ui/scope_sets/relative_path.hist @@ -0,0 +1,4 @@ +#Sun Aug 26 17:36:29 BST 2007 +__DEFAULT__=false +org.eclipse.help.ui.localSearch.master=true +expression=relative path diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.help.ui/scope_sets/working_set.hist b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.help.ui/scope_sets/working_set.hist new file mode 100644 index 000000000..197837b95 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.help.ui/scope_sets/working_set.hist @@ -0,0 +1,4 @@ +#Sun Aug 26 17:29:25 BST 2007 +__DEFAULT__=false +org.eclipse.help.ui.localSearch.master=true +expression=working set diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.help.ui/scope_sets/working_sets.hist b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.help.ui/scope_sets/working_sets.hist new file mode 100644 index 000000000..a88e15eb8 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.help.ui/scope_sets/working_sets.hist @@ -0,0 +1,4 @@ +#Sun Aug 26 17:54:21 BST 2007 +__DEFAULT__=false +org.eclipse.help.ui.localSearch.master=true +expression=working sets diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.ltk.ui.refactoring/dialog_settings.xml b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.ltk.ui.refactoring/dialog_settings.xml new file mode 100644 index 000000000..ac671478c --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.ltk.ui.refactoring/dialog_settings.xml @@ -0,0 +1,6 @@ + +
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diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.search/dialog_settings.xml b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.search/dialog_settings.xml new file mode 100644 index 000000000..839aca5ed --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.search/dialog_settings.xml @@ -0,0 +1,46 @@ + +
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diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.ui.cheatsheets/dialog_settings.xml b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.ui.cheatsheets/dialog_settings.xml new file mode 100644 index 000000000..1df8b48c3 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.ui.cheatsheets/dialog_settings.xml @@ -0,0 +1,10 @@ + +
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diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.ui.ide/dialog_settings.xml b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.ui.ide/dialog_settings.xml new file mode 100644 index 000000000..127582b33 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.ui.ide/dialog_settings.xml @@ -0,0 +1,26 @@ + +
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diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.ui.intro/dialog_settings.xml b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.ui.intro/dialog_settings.xml new file mode 100644 index 000000000..d3014f5c1 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.ui.intro/dialog_settings.xml @@ -0,0 +1,4 @@ + +
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diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.ui.workbench.texteditor/dialog_settings.xml b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.ui.workbench.texteditor/dialog_settings.xml new file mode 100644 index 000000000..ec032bd0b --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.ui.workbench.texteditor/dialog_settings.xml @@ -0,0 +1,38 @@ + +
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diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.ui.workbench/dialog_settings.xml b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.ui.workbench/dialog_settings.xml new file mode 100644 index 000000000..77beade3e --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.ui.workbench/dialog_settings.xml @@ -0,0 +1,19 @@ + +
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diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.ui.workbench/workbench.xml b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.ui.workbench/workbench.xml new file mode 100644 index 000000000..01621f472 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.ui.workbench/workbench.xml @@ -0,0 +1,530 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.ui.workbench/workingsets.xml b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.ui.workbench/workingsets.xml new file mode 100644 index 000000000..ce2a93059 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.ui.workbench/workingsets.xml @@ -0,0 +1,73 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.ui/dialog_settings.xml b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.ui/dialog_settings.xml new file mode 100644 index 000000000..64561b65c --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.ui/dialog_settings.xml @@ -0,0 +1,10 @@ + +
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diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.update.ui/dialog_settings.xml b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.update.ui/dialog_settings.xml new file mode 100644 index 000000000..86928e08c --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/.plugins/org.eclipse.update.ui/dialog_settings.xml @@ -0,0 +1,5 @@ + +
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diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/version.ini b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/version.ini new file mode 100644 index 000000000..c51ff745b --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/.metadata/version.ini @@ -0,0 +1 @@ +org.eclipse.core.runtime=1 \ No newline at end of file diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/.cproject b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/.cproject new file mode 100644 index 000000000..bbcae405f --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/.cproject @@ -0,0 +1,230 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/.project b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/.project new file mode 100644 index 000000000..b3776decb --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/.project @@ -0,0 +1,97 @@ + + + RTOSDemo + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.buildLocation + ${workspace_loc:/RTOSDemo} + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + false + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + ?children? + ?name?=outputEntries\|?children?=?name?=entry\\\\\\\\\\\\\\\|\\\\\\\|\|| + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.core.cnature + + + + Common Demo Files + 2 + FreeRTOS_ROOT/Demo/Common + + + FreeRTOS.org Source + 2 + FreeRTOS_ROOT/Source + + + diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/.settings/org.eclipse.ltk.core.refactoring.prefs b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/.settings/org.eclipse.ltk.core.refactoring.prefs new file mode 100644 index 000000000..a9f7e81cf --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/.settings/org.eclipse.ltk.core.refactoring.prefs @@ -0,0 +1,3 @@ +#Sun Aug 19 20:36:58 BST 2007 +eclipse.preferences.version=1 +org.eclipse.ltk.core.refactoring.enable.project.refactoring.history=false diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/FreeRTOSConfig.h b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/FreeRTOSConfig.h new file mode 100644 index 000000000..5f972fcf0 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/FreeRTOSConfig.h @@ -0,0 +1,118 @@ +/* + FreeRTOS V4.6.1 - Copyright (C) 2003-2005 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include +#include "lpc23xx.h" +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +/* Value to use on old rev '-' devices. */ +//#define configPINSEL2_VALUE 0x50151105 + +/* Value to use on rev 'A' and newer devices. */ +//#define configPINSEL2_VALUE 0x50150105 + +#ifndef configPINSEL2_VALUE + #error Please uncomment one of the two configPINSEL2_VALUE definitions above, depending on the revision of the LPC2000 device being used. +#endif + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 1 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 48000000 ) /* =12Mhz xtal multiplied by 5 using the PLL. */ +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 104 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 18 * 1024 ) ) +#define configMAX_TASK_NAME_LEN ( 10 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 + + +#endif /* FREERTOS_CONFIG_H */ + + +#ifndef sbi +#define sbi(x,y) x|=(1 << (y)) +#endif + +#ifndef cbi +#define cbi(x,y) x&=~(1 << (y)) +#endif + +#ifndef tstb +#define tstb(x,y) (x & (1 << (y)) ? 1 : 0) +#endif + +#ifndef toggle +#define toggle(x,y) x^=(1 << (y)) +#endif + +#ifndef BIT +#define BIT(x) (1 << (x)) + +typedef struct +{ + long xColumn; + char *pcMessage; +} xLCDMessage; + +#endif diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/LCD/portlcd.c b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/LCD/portlcd.c new file mode 100644 index 000000000..55c538f22 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/LCD/portlcd.c @@ -0,0 +1,391 @@ +/***************************************************************************** + * + * Project : lwIP Web + * Subproject : + * Name : portlcd.c + * Function : Routines for LCD + * Designer : K. Sterckx + * Creation date : 22/01/2007 + * Compiler : GNU ARM + * Processor : LPC2368 + * Last update : + * Last updated by : + * History : + * based on example code from NXP + * + ************************************************************************ + * + * This code is used to place text on the LCD. + * + ************************************************************************/ + +#include "portlcd.h" +#include "FreeRTOS.h" +#include "Task.h" + +/* Please note, on old MCB2300 board, the LCD_E bit is p1.30, on the new board +it's p1.31, please check the schematic carefully, and change LCD_CTRL and LCD_E +accordingly if you have a different board. */ + +/* LCD IO definitions */ +#define LCD_E 0x80000000 /* Enable control pin */ +#define LCD_RW 0x20000000 /* Read/Write control pin */ +#define LCD_RS 0x10000000 /* Data/Instruction control */ +#define LCD_CTRL 0xB0000000 /* Control lines mask */ +#define LCD_DATA 0x0F000000 /* Data lines mask */ + +/* Local variables */ +static unsigned int lcd_ptr; + +/* 8 user defined characters to be loaded into CGRAM (used for bargraph) */ +static const unsigned char UserFont[8][8] = { + { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 }, + { 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10 }, + { 0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18 }, + { 0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C }, + { 0x1E,0x1E,0x1E,0x1E,0x1E,0x1E,0x1E,0x1E }, + { 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F }, + { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 }, + { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } +}; + +/* Local Function Prototypes */ +static void lcd_write( unsigned int c ); +static void lcd_write_4bit( unsigned int c ); +static unsigned int lcd_read_stat( void ); +static void lcd_write_cmd( unsigned int c ); +static void lcd_write_data( unsigned int d ); +static void lcd_wait_busy( void ); + + +/****************************************************************************** +** Function name: lcd_write_4bit +** +** Descriptions: +** +** parameters: four bits to write +** Returned value: None +** +******************************************************************************/ +static void lcd_write_4bit(unsigned int c) +{ + /* Write a 4-bit command to LCD controller. */ + FIO1DIR |= LCD_DATA | LCD_CTRL; + FIO1CLR = LCD_RW | LCD_DATA; + FIO1SET = (c & 0xF) << 24; + FIO1SET = LCD_E; + vTaskDelay(0); + FIO1CLR = LCD_E; + vTaskDelay(0); + return; +} + +/****************************************************************************** +** Function name: lcd_write +** +** Descriptions: +** +** parameters: word to write +** Returned value: None +** +******************************************************************************/ +static void lcd_write(unsigned int c) +{ + /* Write data/command to LCD controller. */ + lcd_write_4bit (c >> 4); + lcd_write_4bit (c); + return; +} + +/****************************************************************************** +** Function name: lcd_read_stat +** +** Descriptions: +** +** parameters: None +** Returned value: status +** +******************************************************************************/ +static unsigned int lcd_read_stat(void) +{ + /* Read status of LCD controller (ST7066) */ + unsigned int stat; + + FIO1DIR &= ~LCD_DATA; + FIO1CLR = LCD_RS; + FIO1SET = LCD_RW; + vTaskDelay( 0 ); + FIO1SET = LCD_E; + vTaskDelay( 0 ); + stat = (FIO1PIN >> 20) & 0xF0; + FIO1CLR = LCD_E; + vTaskDelay( 0 ); + FIO1SET = LCD_E; + vTaskDelay( 0 ); + stat |= (FIO1PIN >> 24) & 0xF; + FIO1CLR = LCD_E; + return (stat); +} + +/****************************************************************************** +** Function name: lcd_wait_busy +** +** Descriptions: +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +static void lcd_wait_busy(void) +{ + /* Wait until LCD controller (ST7066) is busy. */ + unsigned int stat; + + do + { + stat = lcd_read_stat(); + } + while (stat & 0x80); /* Wait for busy flag */ + + return; +} + +/****************************************************************************** +** Function name: lcd_write_cmd +** +** Descriptions: +** +** parameters: command word +** Returned value: None +** +******************************************************************************/ +static void lcd_write_cmd(unsigned int c) +{ + /* Write command to LCD controller. */ + lcd_wait_busy(); + FIO1CLR = LCD_RS; + lcd_write(c); + return; +} + +/****************************************************************************** +** Function name: lcd_write_data +** +** Descriptions: +** +** parameters: data word +** Returned value: None +** +******************************************************************************/ +static void lcd_write_data(unsigned int d) +{ + /* Write data to LCD controller. */ + lcd_wait_busy(); + FIO1SET = LCD_RS; + lcd_write(d); + return; +} + +/****************************************************************************** +** Function name: LCD_init +** +** Descriptions: +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +void LCD_init(void) +{ + /* Initialize the ST7066 LCD controller to 4-bit mode. */ + PINSEL3 = 0x00000000; +#if USE_FIO + SCS |= 0x00000001;/* set GPIOx to use Fast I/O */ +#endif + FIO1DIR |= LCD_CTRL | LCD_DATA; + FIO1CLR = LCD_RW | LCD_RS | LCD_DATA; + + lcd_write_4bit(0x3); /* Select 4-bit interface */ + vTaskDelay(100); + lcd_write_4bit(0x3); + vTaskDelay(100); + lcd_write_4bit(0x3); + lcd_write_4bit(0x2); + + lcd_write_cmd(0x28); /* 2 lines, 5x8 character matrix */ + lcd_write_cmd(0x0e); /* Display ctrl:Disp/Curs/Blnk=ON */ + lcd_write_cmd(0x06); /* Entry mode: Move right, no shift */ + + LCD_load( (unsigned char *)&UserFont, sizeof (UserFont) ); + LCD_cls(); + return; +} + +/****************************************************************************** +** Function name: LCD_load +** +** Descriptions: +** +** parameters: pointer to the buffer and counter +** Returned value: None +** +******************************************************************************/ +void LCD_load(unsigned char *fp, unsigned int cnt) +{ + /* Load user-specific characters into CGRAM */ + unsigned int i; + + lcd_write_cmd( 0x40 ); /* Set CGRAM address counter to 0 */ + for (i = 0; i < cnt; i++, fp++) + { + lcd_write_data( *fp ); + } + return; +} + +/****************************************************************************** +** Function name: LCD_gotoxy +** +** Descriptions: +** +** parameters: pixel X and Y +** Returned value: None +** +******************************************************************************/ +void LCD_gotoxy(unsigned int x, unsigned int y) +{ + /* Set cursor position on LCD display. Left corner: 1,1, right: 16,2 */ + unsigned int c; + + c = --x; + if (--y) + { + c |= 0x40; + } + lcd_write_cmd (c | 0x80); + lcd_ptr = y*16 + x; + return; +} + +/****************************************************************************** +** Function name: LCD_cls +** +** Descriptions: +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +void LCD_cls(void) +{ + /* Clear LCD display, move cursor to home position. */ + lcd_write_cmd (0x01); + LCD_gotoxy (1,1); + return; +} + +/****************************************************************************** +** Function name: LCD_cur_off +** +** Descriptions: +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +void LCD_cur_off(void) +{ + /* Switch off LCD cursor. */ + lcd_write_cmd(0x0c); + return; +} + + +/****************************************************************************** +** Function name: LCD_on +** +** Descriptions: +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +void LCD_on(void) +{ + /* Switch on LCD and enable cursor. */ + lcd_write_cmd (0x0e); + return; +} + +/****************************************************************************** +** Function name: LCD_putc +** +** Descriptions: +** +** parameters: unsigned char character +** Returned value: None +** +******************************************************************************/ +void LCD_putc(unsigned char c) +{ + /* Print a character to LCD at current cursor position. */ + if (lcd_ptr == 16) + { + lcd_write_cmd (0xc0); + } + lcd_write_data(c); + lcd_ptr++; + return; +} + +/****************************************************************************** +** Function name: LCD_puts +** +** Descriptions: +** +** parameters: pointer to the buffer +** Returned value: None +** +******************************************************************************/ +void LCD_puts(char *sp) +{ + /* Print a string to LCD display. */ + while (*sp) + { + LCD_putc (*sp++); + } + return; +} + +/****************************************************************************** +** Function name: LCD_bargraph +** +** Descriptions: +** +** parameters: value and size +** Returned value: None +** +******************************************************************************/ +void LCD_bargraph(unsigned int val, unsigned int size) +{ + /* Print a bargraph to LCD display. */ + /* - val: value 0..100 % */ + /* - size: size of bargraph 1..16 */ + unsigned int i; + + val = val * size / 20; /* Display matrix 5 x 8 pixels */ + for (i = 0; i < size; i++) + { + if (val > 5) + { + LCD_putc(5); + val -= 5; + } + else + { + LCD_putc(val); + break; + } + } + return; +} diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/LCD/portlcd.h b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/LCD/portlcd.h new file mode 100644 index 000000000..76962538f --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/LCD/portlcd.h @@ -0,0 +1,31 @@ +/***************************************************************************** + * rtc.h: Header file for NXP LPC23xx/24xx Family Microprocessors + * + * Copyright(C) 2006, NXP Semiconductor + * All rights reserved. + * + * History + * 2006.07.13 ver 1.00 Prelimnary version, first Release + * +******************************************************************************/ +#ifndef __PORTLCD_H +#define __PORTLCD_H + +extern void LCD_init(void); +extern void LCD_load(unsigned char *fp, unsigned int cnt); +extern void LCD_gotoxy(unsigned int x, unsigned int y); +extern void LCD_cls(void); +extern void LCD_cur_off(void); +extern void LCD_on(void); +extern void LCD_putc(unsigned char c); +extern void LCD_puts(char *sp); +extern void LCD_bargraph(unsigned int val, unsigned int size); + +extern void LCD_putnibble(unsigned char nibble); +extern void LCD_puthexbyte(unsigned char abyte); + + +#endif /* end __PORTLCD_H */ +/***************************************************************************** +** End Of File +******************************************************************************/ diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/LPC23xx.h b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/LPC23xx.h new file mode 100644 index 000000000..d3587f553 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/LPC23xx.h @@ -0,0 +1,1138 @@ +/***************************************************************************** + * + * Project : lwIP Web + * Subproject : + * Name : LPC23xx.h + * Function : register definitions + * Designer : K. Sterckx + * Creation date : 22/01/2007 + * Compiler : GNU ARM + * Processor : LPC23xx + * Last update : + * Last updated by : + * History : + * + ***************************************************************************** + * + * Hardware specific macro's and defines + * + ****************************************************************************/ + +#ifndef __LPC23xx_H +#define __LPC23xx_H + +/* Vectored Interrupt Controller (VIC) */ +#define VIC_BASE_ADDR 0xFFFFF000 +#define VICIRQStatus (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x000)) +#define VICFIQStatus (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x004)) +#define VICRawIntr (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x008)) +#define VICIntSelect (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x00C)) +#define VICIntEnable (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x010)) +#define VICIntEnClr (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x014)) +#define VICSoftInt (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x018)) +#define VICSoftIntClr (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x01C)) +#define VICProtection (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x020)) +#define VICSWPrioMask (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x024)) + +#define VICVectAddr0 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x100)) +#define VICVectAddr1 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x104)) +#define VICVectAddr2 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x108)) +#define VICVectAddr3 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x10C)) +#define VICVectAddr4 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x110)) +#define VICVectAddr5 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x114)) +#define VICVectAddr6 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x118)) +#define VICVectAddr7 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x11C)) +#define VICVectAddr8 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x120)) +#define VICVectAddr9 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x124)) +#define VICVectAddr10 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x128)) +#define VICVectAddr11 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x12C)) +#define VICVectAddr12 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x130)) +#define VICVectAddr13 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x134)) +#define VICVectAddr14 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x138)) +#define VICVectAddr15 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x13C)) +#define VICVectAddr16 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x140)) +#define VICVectAddr17 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x144)) +#define VICVectAddr18 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x148)) +#define VICVectAddr19 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x14C)) +#define VICVectAddr20 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x150)) +#define VICVectAddr21 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x154)) +#define VICVectAddr22 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x158)) +#define VICVectAddr23 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x15C)) +#define VICVectAddr24 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x160)) +#define VICVectAddr25 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x164)) +#define VICVectAddr26 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x168)) +#define VICVectAddr27 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x16C)) +#define VICVectAddr28 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x170)) +#define VICVectAddr29 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x174)) +#define VICVectAddr30 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x178)) +#define VICVectAddr31 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x17C)) + +/* The name convention below is from previous LPC2000 family MCUs, in LPC230x, +these registers are known as "VICVectPriority(x)". */ +#define VICVectCntl0 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x200)) +#define VICVectCntl1 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x204)) +#define VICVectCntl2 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x208)) +#define VICVectCntl3 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x20C)) +#define VICVectCntl4 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x210)) +#define VICVectCntl5 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x214)) +#define VICVectCntl6 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x218)) +#define VICVectCntl7 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x21C)) +#define VICVectCntl8 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x220)) +#define VICVectCntl9 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x224)) +#define VICVectCntl10 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x228)) +#define VICVectCntl11 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x22C)) +#define VICVectCntl12 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x230)) +#define VICVectCntl13 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x234)) +#define VICVectCntl14 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x238)) +#define VICVectCntl15 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x23C)) +#define VICVectCntl16 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x240)) +#define VICVectCntl17 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x244)) +#define VICVectCntl18 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x248)) +#define VICVectCntl19 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x24C)) +#define VICVectCntl20 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x250)) +#define VICVectCntl21 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x254)) +#define VICVectCntl22 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x258)) +#define VICVectCntl23 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x25C)) +#define VICVectCntl24 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x260)) +#define VICVectCntl25 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x264)) +#define VICVectCntl26 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x268)) +#define VICVectCntl27 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x26C)) +#define VICVectCntl28 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x270)) +#define VICVectCntl29 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x274)) +#define VICVectCntl30 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x278)) +#define VICVectCntl31 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x27C)) + +#define VICVectAddr (*(volatile unsigned int *)(VIC_BASE_ADDR + 0xF00)) + + +/* Pin Connect Block */ +#define PINSEL_BASE_ADDR 0xE002C000 +#define PINSEL0 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x00)) +#define PINSEL1 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x04)) +#define PINSEL2 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x08)) +#define PINSEL3 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x0C)) +#define PINSEL4 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x10)) +#define PINSEL5 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x14)) +#define PINSEL6 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x18)) +#define PINSEL7 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x1C)) +#define PINSEL8 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x20)) +#define PINSEL9 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x24)) +#define PINSEL10 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x28)) + +#define PINMODE0 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x40)) +#define PINMODE1 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x44)) +#define PINMODE2 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x48)) +#define PINMODE3 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x4C)) +#define PINMODE4 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x50)) +#define PINMODE5 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x54)) +#define PINMODE6 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x58)) +#define PINMODE7 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x5C)) +#define PINMODE8 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x60)) +#define PINMODE9 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x64)) + +/* General Purpose Input/Output (GPIO) */ +#define GPIO_BASE_ADDR 0xE0028000 +#define IOPIN0 (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x00)) +#define IOSET0 (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x04)) +#define IODIR0 (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x08)) +#define IOCLR0 (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x0C)) +#define IOPIN1 (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x10)) +#define IOSET1 (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x14)) +#define IODIR1 (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x18)) +#define IOCLR1 (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x1C)) + +/* GPIO Interrupt Registers */ +#define IO0_INT_EN_R (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x90)) +#define IO0_INT_EN_F (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x94)) +#define IO0_INT_STAT_R (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x84)) +#define IO0_INT_STAT_F (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x88)) +#define IO0_INT_CLR (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x8C)) + +#define IO2_INT_EN_R (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0xB0)) +#define IO2_INT_EN_F (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0xB4)) +#define IO2_INT_STAT_R (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0xA4)) +#define IO2_INT_STAT_F (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0xA8)) +#define IO2_INT_CLR (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0xAC)) + +#define IO_INT_STAT (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x80)) + +#define PARTCFG_BASE_ADDR 0x3FFF8000 +#define PARTCFG (*(volatile unsigned int *)(PARTCFG_BASE_ADDR + 0x00)) + +/* Fast I/O setup */ +#define FIO_BASE_ADDR 0x3FFFC000 +#define FIO0DIR (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x00)) +#define FIO0MASK (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x10)) +#define FIO0PIN (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x14)) +#define FIO0SET (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x18)) +#define FIO0CLR (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x1C)) + +#define FIO1DIR (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x20)) +#define FIO1MASK (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x30)) +#define FIO1PIN (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x34)) +#define FIO1SET (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x38)) +#define FIO1CLR (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x3C)) + +#define FIO2DIR (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x40)) +#define FIO2MASK (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x50)) +#define FIO2PIN (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x54)) +#define FIO2SET (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x58)) +#define FIO2CLR (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x5C)) + +#define FIO3DIR (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x60)) +#define FIO3MASK (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x70)) +#define FIO3PIN (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x74)) +#define FIO3SET (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x78)) +#define FIO3CLR (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x7C)) + +#define FIO4DIR (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x80)) +#define FIO4MASK (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x90)) +#define FIO4PIN (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x94)) +#define FIO4SET (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x98)) +#define FIO4CLR (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x9C)) + +/* FIOs can be accessed through WORD, HALF-WORD or BYTE. */ +#define FIO0DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x01)) +#define FIO1DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21)) +#define FIO2DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x41)) +#define FIO3DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x61)) +#define FIO4DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x81)) + +#define FIO0DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x02)) +#define FIO1DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x22)) +#define FIO2DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x42)) +#define FIO3DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x62)) +#define FIO4DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x82)) + +#define FIO0DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x03)) +#define FIO1DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x23)) +#define FIO2DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x43)) +#define FIO3DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x63)) +#define FIO4DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x83)) + +#define FIO0DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x04)) +#define FIO1DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x24)) +#define FIO2DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x44)) +#define FIO3DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x64)) +#define FIO4DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x84)) + +#define FIO0DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x00)) +#define FIO1DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x20)) +#define FIO2DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x40)) +#define FIO3DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x60)) +#define FIO4DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x80)) + +#define FIO0DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x02)) +#define FIO1DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x22)) +#define FIO2DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x42)) +#define FIO3DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x62)) +#define FIO4DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x82)) + +#define FIO0MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x10)) +#define FIO1MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x30)) +#define FIO2MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x50)) +#define FIO3MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x70)) +#define FIO4MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x90)) + +#define FIO0MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x11)) +#define FIO1MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21)) +#define FIO2MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x51)) +#define FIO3MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x71)) +#define FIO4MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x91)) + +#define FIO0MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x12)) +#define FIO1MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x32)) +#define FIO2MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x52)) +#define FIO3MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x72)) +#define FIO4MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x92)) + +#define FIO0MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x13)) +#define FIO1MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x33)) +#define FIO2MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x53)) +#define FIO3MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x73)) +#define FIO4MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x93)) + +#define FIO0MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x10)) +#define FIO1MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x30)) +#define FIO2MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x50)) +#define FIO3MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x70)) +#define FIO4MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x90)) + +#define FIO0MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x12)) +#define FIO1MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x32)) +#define FIO2MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x52)) +#define FIO3MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x72)) +#define FIO4MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x92)) + +#define FIO0PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x14)) +#define FIO1PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x34)) +#define FIO2PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x54)) +#define FIO3PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x74)) +#define FIO4PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x94)) + +#define FIO0PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x15)) +#define FIO1PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x25)) +#define FIO2PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x55)) +#define FIO3PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x75)) +#define FIO4PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x95)) + +#define FIO0PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x16)) +#define FIO1PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x36)) +#define FIO2PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x56)) +#define FIO3PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x76)) +#define FIO4PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x96)) + +#define FIO0PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x17)) +#define FIO1PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x37)) +#define FIO2PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x57)) +#define FIO3PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x77)) +#define FIO4PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x97)) + +#define FIO0PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x14)) +#define FIO1PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x34)) +#define FIO2PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x54)) +#define FIO3PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x74)) +#define FIO4PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x94)) + +#define FIO0PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x16)) +#define FIO1PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x36)) +#define FIO2PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x56)) +#define FIO3PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x76)) +#define FIO4PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x96)) + +#define FIO0SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x18)) +#define FIO1SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x38)) +#define FIO2SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x58)) +#define FIO3SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x78)) +#define FIO4SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x98)) + +#define FIO0SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x19)) +#define FIO1SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x29)) +#define FIO2SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x59)) +#define FIO3SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x79)) +#define FIO4SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x99)) + +#define FIO0SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1A)) +#define FIO1SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3A)) +#define FIO2SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5A)) +#define FIO3SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7A)) +#define FIO4SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9A)) + +#define FIO0SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1B)) +#define FIO1SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3B)) +#define FIO2SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5B)) +#define FIO3SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7B)) +#define FIO4SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9B)) + +#define FIO0SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x18)) +#define FIO1SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x38)) +#define FIO2SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x58)) +#define FIO3SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x78)) +#define FIO4SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x98)) + +#define FIO0SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1A)) +#define FIO1SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3A)) +#define FIO2SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5A)) +#define FIO3SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7A)) +#define FIO4SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9A)) + +#define FIO0CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1C)) +#define FIO1CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3C)) +#define FIO2CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5C)) +#define FIO3CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7C)) +#define FIO4CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9C)) + +#define FIO0CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1D)) +#define FIO1CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x2D)) +#define FIO2CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5D)) +#define FIO3CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7D)) +#define FIO4CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9D)) + +#define FIO0CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1E)) +#define FIO1CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3E)) +#define FIO2CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5E)) +#define FIO3CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7E)) +#define FIO4CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9E)) + +#define FIO0CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1F)) +#define FIO1CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3F)) +#define FIO2CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5F)) +#define FIO3CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7F)) +#define FIO4CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9F)) + +#define FIO0CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1C)) +#define FIO1CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3C)) +#define FIO2CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5C)) +#define FIO3CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7C)) +#define FIO4CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9C)) + +#define FIO0CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1E)) +#define FIO1CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3E)) +#define FIO2CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5E)) +#define FIO3CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7E)) +#define FIO4CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9E)) + + +/* System Control Block(SCB) modules include Memory Accelerator Module, +Phase Locked Loop, VPB divider, Power Control, External Interrupt, +Reset, and Code Security/Debugging */ +#define SCB_BASE_ADDR 0xE01FC000 + +/* Memory Accelerator Module (MAM) */ +#define MAMCR (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x000)) +#define MAMTIM (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x004)) +#define MEMMAP (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x040)) + +/* Phase Locked Loop (PLL) */ +#define PLLCON (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x080)) +#define PLLCFG (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x084)) +#define PLLSTAT (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x088)) +#define PLLFEED (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x08C)) + +/* Power Control */ +#define PCON (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x0C0)) +#define PCONP (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x0C4)) + +/* Clock Divider */ +#define APBDIV (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x100)) +#define CCLKCFG (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x104)) +#define USBCLKCFG (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x108)) +#define CLKSRCSEL (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x10C)) +#define PCLKSEL0 (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x1A8)) +#define PCLKSEL1 (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x1AC)) + +/* External Interrupts */ +#define EXTINT (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x140)) +#define INTWAKE (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x144)) +#define EXTMODE (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x148)) +#define EXTPOLAR (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x14C)) + +/* Reset, reset source identification */ +#define RSIR (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x180)) + +/* RSID, code security protection */ +#define CSPR (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x184)) + +/* AHB configuration */ +#define AHBCFG1 (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x188)) +#define AHBCFG2 (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x18C)) + +/* System Controls and Status */ +#define SCS (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x1A0)) + +/*MPMC(EMC) registers*/ +#define STATIC_MEM0_BASE 0x80000000 +#define STATIC_MEM1_BASE 0x81000000 +#define STATIC_MEM2_BASE 0x82000000 +#define STATIC_MEM3_BASE 0x83000000 + +#define DYNAMIC_MEM0_BASE 0xA0000000 +#define DYNAMIC_MEM1_BASE 0xB0000000 +#define DYNAMIC_MEM2_BASE 0xC0000000 +#define DYNAMIC_MEM3_BASE 0xD0000000 + +/* External Memory Controller (EMC) */ +#define EMC_BASE_ADDR 0xFFE08000 +#define EMC_CTRL (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x000)) +#define EMC_STAT (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x004)) +#define EMC_CONFIG (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x008)) + +/* Dynamic RAM access registers */ +#define EMC_DYN_CTRL (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x020)) +#define EMC_DYN_RFSH (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x024)) +#define EMC_DYN_RD_CFG (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x028)) +#define EMC_DYN_RP (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x030)) +#define EMC_DYN_RAS (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x034)) +#define EMC_DYN_SREX (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x038)) +#define EMC_DYN_APR (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x03C)) +#define EMC_DYN_DAL (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x040)) +#define EMC_DYN_WR (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x044)) +#define EMC_DYN_RC (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x048)) +#define EMC_DYN_RFC (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x04C)) +#define EMC_DYN_XSR (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x050)) +#define EMC_DYN_RRD (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x054)) +#define EMC_DYN_MRD (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x058)) + +#define EMC_DYN_CFG0 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x100)) +#define EMC_DYN_RASCAS0 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x104)) +#define EMC_DYN_CFG1 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x140)) +#define EMC_DYN_RASCAS1 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x144)) +#define EMC_DYN_CFG2 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x160)) +#define EMC_DYN_RASCAS2 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x164)) +#define EMC_DYN_CFG3 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x180)) +#define EMC_DYN_RASCAS3 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x184)) + +/* static RAM access registers */ +#define EMC_STA_CFG0 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x200)) +#define EMC_STA_WAITWEN0 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x204)) +#define EMC_STA_WAITOEN0 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x208)) +#define EMC_STA_WAITRD0 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x20C)) +#define EMC_STA_WAITPAGE0 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x210)) +#define EMC_STA_WAITWR0 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x214)) +#define EMC_STA_WAITTURN0 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x218)) + +#define EMC_STA_CFG1 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x220)) +#define EMC_STA_WAITWEN1 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x224)) +#define EMC_STA_WAITOEN1 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x228)) +#define EMC_STA_WAITRD1 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x22C)) +#define EMC_STA_WAITPAGE1 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x230)) +#define EMC_STA_WAITWR1 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x234)) +#define EMC_STA_WAITTURN1 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x238)) + +#define EMC_STA_CFG2 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x240)) +#define EMC_STA_WAITWEN2 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x244)) +#define EMC_STA_WAITOEN2 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x248)) +#define EMC_STA_WAITRD2 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x24C)) +#define EMC_STA_WAITPAGE2 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x250)) +#define EMC_STA_WAITWR2 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x254)) +#define EMC_STA_WAITTURN2 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x258)) + +#define EMC_STA_CFG3 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x260)) +#define EMC_STA_WAITWEN3 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x264)) +#define EMC_STA_WAITOEN3 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x268)) +#define EMC_STA_WAITRD3 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x26C)) +#define EMC_STA_WAITPAGE3 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x270)) +#define EMC_STA_WAITWR3 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x274)) +#define EMC_STA_WAITTURN3 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x278)) + +#define EMC_STA_EXT_WAIT (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x880)) + + +/* Timer 0 */ +#define TMR0_BASE_ADDR 0xE0004000 +#define T0IR (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x00)) +#define T0TCR (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x04)) +#define T0TC (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x08)) +#define T0PR (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x0C)) +#define T0PC (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x10)) +#define T0MCR (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x14)) +#define T0MR0 (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x18)) +#define T0MR1 (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x1C)) +#define T0MR2 (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x20)) +#define T0MR3 (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x24)) +#define T0CCR (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x28)) +#define T0CR0 (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x2C)) +#define T0CR1 (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x30)) +#define T0CR2 (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x34)) +#define T0CR3 (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x38)) +#define T0EMR (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x3C)) +#define T0CTCR (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x70)) + +/* Timer 1 */ +#define TMR1_BASE_ADDR 0xE0008000 +#define T1IR (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x00)) +#define T1TCR (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x04)) +#define T1TC (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x08)) +#define T1PR (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x0C)) +#define T1PC (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x10)) +#define T1MCR (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x14)) +#define T1MR0 (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x18)) +#define T1MR1 (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x1C)) +#define T1MR2 (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x20)) +#define T1MR3 (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x24)) +#define T1CCR (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x28)) +#define T1CR0 (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x2C)) +#define T1CR1 (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x30)) +#define T1CR2 (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x34)) +#define T1CR3 (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x38)) +#define T1EMR (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x3C)) +#define T1CTCR (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x70)) + +/* Timer 2 */ +#define TMR2_BASE_ADDR 0xE0070000 +#define T2IR (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x00)) +#define T2TCR (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x04)) +#define T2TC (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x08)) +#define T2PR (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x0C)) +#define T2PC (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x10)) +#define T2MCR (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x14)) +#define T2MR0 (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x18)) +#define T2MR1 (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x1C)) +#define T2MR2 (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x20)) +#define T2MR3 (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x24)) +#define T2CCR (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x28)) +#define T2CR0 (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x2C)) +#define T2CR1 (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x30)) +#define T2CR2 (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x34)) +#define T2CR3 (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x38)) +#define T2EMR (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x3C)) +#define T2CTCR (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x70)) + +/* Timer 3 */ +#define TMR3_BASE_ADDR 0xE0074000 +#define T3IR (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x00)) +#define T3TCR (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x04)) +#define T3TC (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x08)) +#define T3PR (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x0C)) +#define T3PC (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x10)) +#define T3MCR (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x14)) +#define T3MR0 (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x18)) +#define T3MR1 (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x1C)) +#define T3MR2 (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x20)) +#define T3MR3 (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x24)) +#define T3CCR (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x28)) +#define T3CR0 (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x2C)) +#define T3CR1 (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x30)) +#define T3CR2 (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x34)) +#define T3CR3 (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x38)) +#define T3EMR (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x3C)) +#define T3CTCR (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x70)) + + +/* Pulse Width Modulator (PWM) */ +#define PWM0_BASE_ADDR 0xE0014000 +#define PWM0IR (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x00)) +#define PWM0TCR (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x04)) +#define PWM0TC (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x08)) +#define PWM0PR (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x0C)) +#define PWM0PC (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x10)) +#define PWM0MCR (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x14)) +#define PWM0MR0 (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x18)) +#define PWM0MR1 (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x1C)) +#define PWM0MR2 (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x20)) +#define PWM0MR3 (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x24)) +#define PWM0CCR (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x28)) +#define PWM0CR0 (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x2C)) +#define PWM0CR1 (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x30)) +#define PWM0CR2 (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x34)) +#define PWM0CR3 (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x38)) +#define PWM0EMR (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x3C)) +#define PWM0MR4 (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x40)) +#define PWM0MR5 (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x44)) +#define PWM0MR6 (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x48)) +#define PWM0PCR (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x4C)) +#define PWM0LER (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x50)) +#define PWM0CTCR (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x70)) + +#define PWM1_BASE_ADDR 0xE0018000 +#define PWM1IR (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x00)) +#define PWM1TCR (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x04)) +#define PWM1TC (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x08)) +#define PWM1PR (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x0C)) +#define PWM1PC (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x10)) +#define PWM1MCR (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x14)) +#define PWM1MR0 (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x18)) +#define PWM1MR1 (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x1C)) +#define PWM1MR2 (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x20)) +#define PWM1MR3 (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x24)) +#define PWM1CCR (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x28)) +#define PWM1CR0 (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x2C)) +#define PWM1CR1 (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x30)) +#define PWM1CR2 (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x34)) +#define PWM1CR3 (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x38)) +#define PWM1EMR (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x3C)) +#define PWM1MR4 (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x40)) +#define PWM1MR5 (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x44)) +#define PWM1MR6 (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x48)) +#define PWM1PCR (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x4C)) +#define PWM1LER (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x50)) +#define PWM1CTCR (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x70)) + + +/* Universal Asynchronous Receiver Transmitter 0 (UART0) */ +#define UART0_BASE_ADDR 0xE000C000 +#define U0RBR (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x00)) +#define U0THR (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x00)) +#define U0DLL (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x00)) +#define U0DLM (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x04)) +#define U0IER (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x04)) +#define U0IIR (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x08)) +#define U0FCR (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x08)) +#define U0LCR (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x0C)) +#define U0LSR (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x14)) +#define U0SCR (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x1C)) +#define U0ACR (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x20)) +#define U0ICR (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x24)) +#define U0FDR (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x28)) +#define U0TER (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x30)) + +/* Universal Asynchronous Receiver Transmitter 1 (UART1) */ +#define UART1_BASE_ADDR 0xE0010000 +#define U1RBR (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x00)) +#define U1THR (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x00)) +#define U1DLL (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x00)) +#define U1DLM (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x04)) +#define U1IER (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x04)) +#define U1IIR (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x08)) +#define U1FCR (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x08)) +#define U1LCR (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x0C)) +#define U1MCR (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x10)) +#define U1LSR (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x14)) +#define U1MSR (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x18)) +#define U1SCR (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x1C)) +#define U1ACR (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x20)) +#define U1FDR (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x28)) +#define U1TER (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x30)) + +/* Universal Asynchronous Receiver Transmitter 2 (UART2) */ +#define UART2_BASE_ADDR 0xE0078000 +#define U2RBR (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x00)) +#define U2THR (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x00)) +#define U2DLL (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x00)) +#define U2DLM (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x04)) +#define U2IER (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x04)) +#define U2IIR (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x08)) +#define U2FCR (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x08)) +#define U2LCR (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x0C)) +#define U2LSR (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x14)) +#define U2SCR (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x1C)) +#define U2ACR (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x20)) +#define U2ICR (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x24)) +#define U2FDR (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x28)) +#define U2TER (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x30)) + +/* Universal Asynchronous Receiver Transmitter 3 (UART3) */ +#define UART3_BASE_ADDR 0xE007C000 +#define U3RBR (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x00)) +#define U3THR (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x00)) +#define U3DLL (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x00)) +#define U3DLM (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x04)) +#define U3IER (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x04)) +#define U3IIR (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x08)) +#define U3FCR (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x08)) +#define U3LCR (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x0C)) +#define U3LSR (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x14)) +#define U3SCR (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x1C)) +#define U3ACR (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x20)) +#define U3ICR (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x24)) +#define U3FDR (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x28)) +#define U3TER (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x30)) + +/* I2C Interface 0 */ +#define I2C0_BASE_ADDR 0xE001C000 +#define I20CONSET (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x00)) +#define I20STAT (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x04)) +#define I20DAT (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x08)) +#define I20ADR (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x0C)) +#define I20SCLH (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x10)) +#define I20SCLL (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x14)) +#define I20CONCLR (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x18)) +//Slightly different naming +#define I2C0CONSET (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x00)) +#define I2C0STAT (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x04)) +#define I2C0DAT (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x08)) +#define I2C0ADR (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x0C)) +#define I2C0SCLH (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x10)) +#define I2C0SCLL (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x14)) +#define I2C0CONCLR (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x18)) + + +/* I2C Interface 1 */ +#define I2C1_BASE_ADDR 0xE005C000 +#define I21CONSET (*(volatile unsigned int *)(I2C1_BASE_ADDR + 0x00)) +#define I21STAT (*(volatile unsigned int *)(I2C1_BASE_ADDR + 0x04)) +#define I21DAT (*(volatile unsigned int *)(I2C1_BASE_ADDR + 0x08)) +#define I21ADR (*(volatile unsigned int *)(I2C1_BASE_ADDR + 0x0C)) +#define I21SCLH (*(volatile unsigned int *)(I2C1_BASE_ADDR + 0x10)) +#define I21SCLL (*(volatile unsigned int *)(I2C1_BASE_ADDR + 0x14)) +#define I21CONCLR (*(volatile unsigned int *)(I2C1_BASE_ADDR + 0x18)) + +/* I2C Interface 2 */ +#define I2C2_BASE_ADDR 0xE0080000 +#define I22CONSET (*(volatile unsigned int *)(I2C2_BASE_ADDR + 0x00)) +#define I22STAT (*(volatile unsigned int *)(I2C2_BASE_ADDR + 0x04)) +#define I22DAT (*(volatile unsigned int *)(I2C2_BASE_ADDR + 0x08)) +#define I22ADR (*(volatile unsigned int *)(I2C2_BASE_ADDR + 0x0C)) +#define I22SCLH (*(volatile unsigned int *)(I2C2_BASE_ADDR + 0x10)) +#define I22SCLL (*(volatile unsigned int *)(I2C2_BASE_ADDR + 0x14)) +#define I22CONCLR (*(volatile unsigned int *)(I2C2_BASE_ADDR + 0x18)) + +/* SPI0 (Serial Peripheral Interface 0) */ +#define SPI0_BASE_ADDR 0xE0020000 +#define S0SPCR (*(volatile unsigned int *)(SPI0_BASE_ADDR + 0x00)) +#define S0SPSR (*(volatile unsigned int *)(SPI0_BASE_ADDR + 0x04)) +#define S0SPDR (*(volatile unsigned int *)(SPI0_BASE_ADDR + 0x08)) +#define S0SPCCR (*(volatile unsigned int *)(SPI0_BASE_ADDR + 0x0C)) +#define S0SPINT (*(volatile unsigned int *)(SPI0_BASE_ADDR + 0x1C)) + +/* SSP0 Controller */ +#define SSP0_BASE_ADDR 0xE0068000 +#define SSP0CR0 (*(volatile unsigned int *)(SSP0_BASE_ADDR + 0x00)) +#define SSP0CR1 (*(volatile unsigned int *)(SSP0_BASE_ADDR + 0x04)) +#define SSP0DR (*(volatile unsigned int *)(SSP0_BASE_ADDR + 0x08)) +#define SSP0SR (*(volatile unsigned int *)(SSP0_BASE_ADDR + 0x0C)) +#define SSP0CPSR (*(volatile unsigned int *)(SSP0_BASE_ADDR + 0x10)) +#define SSP0IMSC (*(volatile unsigned int *)(SSP0_BASE_ADDR + 0x14)) +#define SSP0RIS (*(volatile unsigned int *)(SSP0_BASE_ADDR + 0x18)) +#define SSP0MIS (*(volatile unsigned int *)(SSP0_BASE_ADDR + 0x1C)) +#define SSP0ICR (*(volatile unsigned int *)(SSP0_BASE_ADDR + 0x20)) +#define SSP0DMACR (*(volatile unsigned int *)(SSP0_BASE_ADDR + 0x24)) + +/* SSP1 Controller */ +#define SSP1_BASE_ADDR 0xE0030000 +#define SSP1CR0 (*(volatile unsigned int *)(SSP1_BASE_ADDR + 0x00)) +#define SSP1CR1 (*(volatile unsigned int *)(SSP1_BASE_ADDR + 0x04)) +#define SSP1DR (*(volatile unsigned int *)(SSP1_BASE_ADDR + 0x08)) +#define SSP1SR (*(volatile unsigned int *)(SSP1_BASE_ADDR + 0x0C)) +#define SSP1CPSR (*(volatile unsigned int *)(SSP1_BASE_ADDR + 0x10)) +#define SSP1IMSC (*(volatile unsigned int *)(SSP1_BASE_ADDR + 0x14)) +#define SSP1RIS (*(volatile unsigned int *)(SSP1_BASE_ADDR + 0x18)) +#define SSP1MIS (*(volatile unsigned int *)(SSP1_BASE_ADDR + 0x1C)) +#define SSP1ICR (*(volatile unsigned int *)(SSP1_BASE_ADDR + 0x20)) +#define SSP1DMACR (*(volatile unsigned int *)(SSP1_BASE_ADDR + 0x24)) + + +/* Real Time Clock */ +#define RTC_BASE_ADDR 0xE0024000 +#define RTC_ILR (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x00)) +#define RTC_CTC (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x04)) +#define RTC_CCR (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x08)) +#define RTC_CIIR (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x0C)) +#define RTC_AMR (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x10)) +#define RTC_CTIME0 (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x14)) +#define RTC_CTIME1 (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x18)) +#define RTC_CTIME2 (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x1C)) +#define RTC_SEC (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x20)) +#define RTC_MIN (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x24)) +#define RTC_HOUR (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x28)) +#define RTC_DOM (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x2C)) +#define RTC_DOW (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x30)) +#define RTC_DOY (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x34)) +#define RTC_MONTH (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x38)) +#define RTC_YEAR (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x3C)) +#define RTC_CISS (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x40)) +#define RTC_ALSEC (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x60)) +#define RTC_ALMIN (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x64)) +#define RTC_ALHOUR (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x68)) +#define RTC_ALDOM (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x6C)) +#define RTC_ALDOW (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x70)) +#define RTC_ALDOY (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x74)) +#define RTC_ALMON (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x78)) +#define RTC_ALYEAR (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x7C)) +#define RTC_PREINT (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x80)) +#define RTC_PREFRAC (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x84)) + + +/* A/D Converter 0 (AD0) */ +#define AD0_BASE_ADDR 0xE0034000 +#define AD0CR (*(volatile unsigned int *)(AD0_BASE_ADDR + 0x00)) +#define AD0GDR (*(volatile unsigned int *)(AD0_BASE_ADDR + 0x04)) +#define AD0INTEN (*(volatile unsigned int *)(AD0_BASE_ADDR + 0x0C)) +#define AD0DR0 (*(volatile unsigned int *)(AD0_BASE_ADDR + 0x10)) +#define AD0DR1 (*(volatile unsigned int *)(AD0_BASE_ADDR + 0x14)) +#define AD0DR2 (*(volatile unsigned int *)(AD0_BASE_ADDR + 0x18)) +#define AD0DR3 (*(volatile unsigned int *)(AD0_BASE_ADDR + 0x1C)) +#define AD0DR4 (*(volatile unsigned int *)(AD0_BASE_ADDR + 0x20)) +#define AD0DR5 (*(volatile unsigned int *)(AD0_BASE_ADDR + 0x24)) +#define AD0DR6 (*(volatile unsigned int *)(AD0_BASE_ADDR + 0x28)) +#define AD0DR7 (*(volatile unsigned int *)(AD0_BASE_ADDR + 0x2C)) +#define AD0STAT (*(volatile unsigned int *)(AD0_BASE_ADDR + 0x30)) + + +/* D/A Converter */ +#define DAC_BASE_ADDR 0xE006C000 +#define DACR (*(volatile unsigned int *)(DAC_BASE_ADDR + 0x00)) + + +/* Watchdog */ +#define WDG_BASE_ADDR 0xE0000000 +#define WDMOD (*(volatile unsigned int *)(WDG_BASE_ADDR + 0x00)) +#define WDTC (*(volatile unsigned int *)(WDG_BASE_ADDR + 0x04)) +#define WDFEED (*(volatile unsigned int *)(WDG_BASE_ADDR + 0x08)) +#define WDTV (*(volatile unsigned int *)(WDG_BASE_ADDR + 0x0C)) +#define WDCLKSEL (*(volatile unsigned int *)(WDG_BASE_ADDR + 0x10)) + +/* CAN CONTROLLERS AND ACCEPTANCE FILTER */ +#define CAN_ACCEPT_BASE_ADDR 0xE003C000 +#define CAN_AFMR (*(volatile unsigned int *)(CAN_ACCEPT_BASE_ADDR + 0x00)) +#define CAN_SFF_SA (*(volatile unsigned int *)(CAN_ACCEPT_BASE_ADDR + 0x04)) +#define CAN_SFF_GRP_SA (*(volatile unsigned int *)(CAN_ACCEPT_BASE_ADDR + 0x08)) +#define CAN_EFF_SA (*(volatile unsigned int *)(CAN_ACCEPT_BASE_ADDR + 0x0C)) +#define CAN_EFF_GRP_SA (*(volatile unsigned int *)(CAN_ACCEPT_BASE_ADDR + 0x10)) +#define CAN_EOT (*(volatile unsigned int *)(CAN_ACCEPT_BASE_ADDR + 0x14)) +#define CAN_LUT_ERR_ADR (*(volatile unsigned int *)(CAN_ACCEPT_BASE_ADDR + 0x18)) +#define CAN_LUT_ERR (*(volatile unsigned int *)(CAN_ACCEPT_BASE_ADDR + 0x1C)) + +#define CAN_CENTRAL_BASE_ADDR 0xE0040000 +#define CAN_TX_SR (*(volatile unsigned int *)(CAN_CENTRAL_BASE_ADDR + 0x00)) +#define CAN_RX_SR (*(volatile unsigned int *)(CAN_CENTRAL_BASE_ADDR + 0x04)) +#define CAN_MSR (*(volatile unsigned int *)(CAN_CENTRAL_BASE_ADDR + 0x08)) + +#define CAN1_BASE_ADDR 0xE0044000 +#define CAN1MOD (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x00)) +#define CAN1CMR (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x04)) +#define CAN1GSR (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x08)) +#define CAN1ICR (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x0C)) +#define CAN1IER (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x10)) +#define CAN1BTR (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x14)) +#define CAN1EWL (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x18)) +#define CAN1SR (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x1C)) +#define CAN1RFS (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x20)) +#define CAN1RID (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x24)) +#define CAN1RDA (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x28)) +#define CAN1RDB (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x2C)) + +#define CAN1TFI1 (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x30)) +#define CAN1TID1 (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x34)) +#define CAN1TDA1 (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x38)) +#define CAN1TDB1 (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x3C)) +#define CAN1TFI2 (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x40)) +#define CAN1TID2 (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x44)) +#define CAN1TDA2 (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x48)) +#define CAN1TDB2 (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x4C)) +#define CAN1TFI3 (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x50)) +#define CAN1TID3 (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x54)) +#define CAN1TDA3 (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x58)) +#define CAN1TDB3 (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x5C)) + +#define CAN2_BASE_ADDR 0xE0048000 +#define CAN2MOD (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x00)) +#define CAN2CMR (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x04)) +#define CAN2GSR (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x08)) +#define CAN2ICR (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x0C)) +#define CAN2IER (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x10)) +#define CAN2BTR (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x14)) +#define CAN2EWL (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x18)) +#define CAN2SR (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x1C)) +#define CAN2RFS (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x20)) +#define CAN2RID (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x24)) +#define CAN2RDA (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x28)) +#define CAN2RDB (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x2C)) + +#define CAN2TFI1 (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x30)) +#define CAN2TID1 (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x34)) +#define CAN2TDA1 (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x38)) +#define CAN2TDB1 (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x3C)) +#define CAN2TFI2 (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x40)) +#define CAN2TID2 (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x44)) +#define CAN2TDA2 (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x48)) +#define CAN2TDB2 (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x4C)) +#define CAN2TFI3 (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x50)) +#define CAN2TID3 (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x54)) +#define CAN2TDA3 (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x58)) +#define CAN2TDB3 (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x5C)) + + +/* MultiMedia Card Interface(MCI) Controller */ +#define MCI_BASE_ADDR 0xE008C000 +#define MCI_POWER (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x00)) +#define MCI_CLOCK (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x04)) +#define MCI_ARGUMENT (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x08)) +#define MCI_COMMAND (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x0C)) +#define MCI_RESP_CMD (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x10)) +#define MCI_RESP0 (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x14)) +#define MCI_RESP1 (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x18)) +#define MCI_RESP2 (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x1C)) +#define MCI_RESP3 (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x20)) +#define MCI_DATA_TMR (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x24)) +#define MCI_DATA_LEN (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x28)) +#define MCI_DATA_CTRL (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x2C)) +#define MCI_DATA_CNT (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x30)) +#define MCI_STATUS (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x34)) +#define MCI_CLEAR (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x38)) +#define MCI_MASK0 (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x3C)) +#define MCI_MASK1 (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x40)) +#define MCI_FIFO_CNT (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x48)) +#define MCI_FIFO (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x80)) + + +/* I2S Interface Controller (I2S) */ +#define I2S_BASE_ADDR 0xE0088000 +#define I2S_DAO (*(volatile unsigned int *)(I2S_BASE_ADDR + 0x00)) +#define I2S_DAI (*(volatile unsigned int *)(I2S_BASE_ADDR + 0x04)) +#define I2S_TX_FIFO (*(volatile unsigned int *)(I2S_BASE_ADDR + 0x08)) +#define I2S_RX_FIFO (*(volatile unsigned int *)(I2S_BASE_ADDR + 0x0C)) +#define I2S_STATE (*(volatile unsigned int *)(I2S_BASE_ADDR + 0x10)) +#define I2S_DMA1 (*(volatile unsigned int *)(I2S_BASE_ADDR + 0x14)) +#define I2S_DMA2 (*(volatile unsigned int *)(I2S_BASE_ADDR + 0x18)) +#define I2S_IRQ (*(volatile unsigned int *)(I2S_BASE_ADDR + 0x1C)) +#define I2S_TXRATE (*(volatile unsigned int *)(I2S_BASE_ADDR + 0x20)) +#define I2S_RXRATE (*(volatile unsigned int *)(I2S_BASE_ADDR + 0x24)) + + +/* General-purpose DMA Controller */ +#define DMA_BASE_ADDR 0xFFE04000 +#define GPDMA_INT_STAT (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x000)) +#define GPDMA_INT_TCSTAT (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x004)) +#define GPDMA_INT_TCCLR (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x008)) +#define GPDMA_INT_ERR_STAT (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x00C)) +#define GPDMA_INT_ERR_CLR (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x010)) +#define GPDMA_RAW_INT_TCSTAT (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x014)) +#define GPDMA_RAW_INT_ERR_STAT (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x018)) +#define GPDMA_ENABLED_CHNS (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x01C)) +#define GPDMA_SOFT_BREQ (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x020)) +#define GPDMA_SOFT_SREQ (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x024)) +#define GPDMA_SOFT_LBREQ (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x028)) +#define GPDMA_SOFT_LSREQ (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x02C)) +#define GPDMA_CONFIG (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x030)) +#define GPDMA_SYNC (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x034)) + +/* DMA channel 0 registers */ +#define GPDMA_CH0_SRC (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x100)) +#define GPDMA_CH0_DEST (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x104)) +#define GPDMA_CH0_LLI (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x108)) +#define GPDMA_CH0_CTRL (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x10C)) +#define GPDMA_CH0_CFG (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x110)) + +/* DMA channel 1 registers */ +#define GPDMA_CH1_SRC (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x120)) +#define GPDMA_CH1_DEST (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x124)) +#define GPDMA_CH1_LLI (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x128)) +#define GPDMA_CH1_CTRL (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x12C)) +#define GPDMA_CH1_CFG (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x130)) + + +/* USB Controller */ +#define USB_INT_BASE_ADDR 0xE01FC1C0 +#define USB_BASE_ADDR 0xFFE0C200 /* USB Base Address */ + +#define USB_INT_STAT (*(volatile unsigned int *)(USB_INT_BASE_ADDR + 0x00)) + +/* USB Device Interrupt Registers */ +#define DEV_INT_STAT (*(volatile unsigned int *)(USB_BASE_ADDR + 0x00)) +#define DEV_INT_EN (*(volatile unsigned int *)(USB_BASE_ADDR + 0x04)) +#define DEV_INT_CLR (*(volatile unsigned int *)(USB_BASE_ADDR + 0x08)) +#define DEV_INT_SET (*(volatile unsigned int *)(USB_BASE_ADDR + 0x0C)) +#define DEV_INT_PRIO (*(volatile unsigned int *)(USB_BASE_ADDR + 0x2C)) + +/* USB Device Endpoint Interrupt Registers */ +#define EP_INT_STAT (*(volatile unsigned int *)(USB_BASE_ADDR + 0x30)) +#define EP_INT_EN (*(volatile unsigned int *)(USB_BASE_ADDR + 0x34)) +#define EP_INT_CLR (*(volatile unsigned int *)(USB_BASE_ADDR + 0x38)) +#define EP_INT_SET (*(volatile unsigned int *)(USB_BASE_ADDR + 0x3C)) +#define EP_INT_PRIO (*(volatile unsigned int *)(USB_BASE_ADDR + 0x40)) + +/* USB Device Endpoint Realization Registers */ +#define REALIZE_EP (*(volatile unsigned int *)(USB_BASE_ADDR + 0x44)) +#define EP_INDEX (*(volatile unsigned int *)(USB_BASE_ADDR + 0x48)) +#define MAXPACKET_SIZE (*(volatile unsigned int *)(USB_BASE_ADDR + 0x4C)) + +/* USB Device Command Reagisters */ +#define CMD_CODE (*(volatile unsigned int *)(USB_BASE_ADDR + 0x10)) +#define CMD_DATA (*(volatile unsigned int *)(USB_BASE_ADDR + 0x14)) + +/* USB Device Data Transfer Registers */ +#define RX_DATA (*(volatile unsigned int *)(USB_BASE_ADDR + 0x18)) +#define TX_DATA (*(volatile unsigned int *)(USB_BASE_ADDR + 0x1C)) +#define RX_PLENGTH (*(volatile unsigned int *)(USB_BASE_ADDR + 0x20)) +#define TX_PLENGTH (*(volatile unsigned int *)(USB_BASE_ADDR + 0x24)) +#define USB_CTRL (*(volatile unsigned int *)(USB_BASE_ADDR + 0x28)) + +/* USB Device DMA Registers */ +#define DMA_REQ_STAT (*(volatile unsigned int *)(USB_BASE_ADDR + 0x50)) +#define DMA_REQ_CLR (*(volatile unsigned int *)(USB_BASE_ADDR + 0x54)) +#define DMA_REQ_SET (*(volatile unsigned int *)(USB_BASE_ADDR + 0x58)) +#define UDCA_HEAD (*(volatile unsigned int *)(USB_BASE_ADDR + 0x80)) +#define EP_DMA_STAT (*(volatile unsigned int *)(USB_BASE_ADDR + 0x84)) +#define EP_DMA_EN (*(volatile unsigned int *)(USB_BASE_ADDR + 0x88)) +#define EP_DMA_DIS (*(volatile unsigned int *)(USB_BASE_ADDR + 0x8C)) +#define DMA_INT_STAT (*(volatile unsigned int *)(USB_BASE_ADDR + 0x90)) +#define DMA_INT_EN (*(volatile unsigned int *)(USB_BASE_ADDR + 0x94)) +#define EOT_INT_STAT (*(volatile unsigned int *)(USB_BASE_ADDR + 0xA0)) +#define EOT_INT_CLR (*(volatile unsigned int *)(USB_BASE_ADDR + 0xA4)) +#define EOT_INT_SET (*(volatile unsigned int *)(USB_BASE_ADDR + 0xA8)) +#define NDD_REQ_INT_STAT (*(volatile unsigned int *)(USB_BASE_ADDR + 0xAC)) +#define NDD_REQ_INT_CLR (*(volatile unsigned int *)(USB_BASE_ADDR + 0xB0)) +#define NDD_REQ_INT_SET (*(volatile unsigned int *)(USB_BASE_ADDR + 0xB4)) +#define SYS_ERR_INT_STAT (*(volatile unsigned int *)(USB_BASE_ADDR + 0xB8)) +#define SYS_ERR_INT_CLR (*(volatile unsigned int *)(USB_BASE_ADDR + 0xBC)) +#define SYS_ERR_INT_SET (*(volatile unsigned int *)(USB_BASE_ADDR + 0xC0)) + + +/* USB Host Controller */ +#define USBHC_BASE_ADDR 0xFFE0C000 +#define HC_REVISION (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x00)) +#define HC_CONTROL (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x04)) +#define HC_CMD_STAT (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x08)) +#define HC_INT_STAT (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x0C)) +#define HC_INT_EN (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x10)) +#define HC_INT_DIS (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x14)) +#define HC_HCCA (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x18)) +#define HC_PERIOD_CUR_ED (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x1C)) +#define HC_CTRL_HEAD_ED (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x20)) +#define HC_CTRL_CUR_ED (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x24)) +#define HC_BULK_HEAD_ED (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x28)) +#define HC_BULK_CUR_ED (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x2C)) +#define HC_DONE_HEAD (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x30)) +#define HC_FM_INTERVAL (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x34)) +#define HC_FM_REMAINING (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x38)) +#define HC_FM_NUMBER (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x3C)) +#define HC_PERIOD_START (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x40)) +#define HC_LS_THRHLD (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x44)) +#define HC_RH_DESCA (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x48)) +#define HC_RH_DESCB (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x4C)) +#define HC_RH_STAT (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x50)) +#define HC_RH_PORT_STAT1 (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x54)) +#define HC_RH_PORT_STAT2 (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x58)) + +/* USB OTG Controller */ +#define USBOTG_BASE_ADDR 0xFFE0C100 +#define OTG_INT_STAT (*(volatile unsigned int *)(USBOTG_BASE_ADDR + 0x00)) +#define OTG_INT_EN (*(volatile unsigned int *)(USBOTG_BASE_ADDR + 0x04)) +#define OTG_INT_SET (*(volatile unsigned int *)(USBOTG_BASE_ADDR + 0x08)) +#define OTG_INT_CLR (*(volatile unsigned int *)(USBOTG_BASE_ADDR + 0x0C)) +#define OTG_STAT_CTRL (*(volatile unsigned int *)(USBOTG_BASE_ADDR + 0x10)) +#define OTG_TIMER (*(volatile unsigned int *)(USBOTG_BASE_ADDR + 0x14)) + +#define USBOTG_I2C_BASE_ADDR 0xFFE0C300 +#define OTG_I2C_RX (*(volatile unsigned int *)(USBOTG_I2C_BASE_ADDR + 0x00)) +#define OTG_I2C_TX (*(volatile unsigned int *)(USBOTG_I2C_BASE_ADDR + 0x00)) +#define OTG_I2C_STS (*(volatile unsigned int *)(USBOTG_I2C_BASE_ADDR + 0x04)) +#define OTG_I2C_CTL (*(volatile unsigned int *)(USBOTG_I2C_BASE_ADDR + 0x08)) +#define OTG_I2C_CLKHI (*(volatile unsigned int *)(USBOTG_I2C_BASE_ADDR + 0x0C)) +#define OTG_I2C_CLKLO (*(volatile unsigned int *)(USBOTG_I2C_BASE_ADDR + 0x10)) + +#define USBOTG_CLK_BASE_ADDR 0xFFE0CFF0 +#define OTG_CLK_CTRL (*(volatile unsigned int *)(USBOTG_CLK_BASE_ADDR + 0x04)) +#define OTG_CLK_STAT (*(volatile unsigned int *)(USBOTG_CLK_BASE_ADDR + 0x08)) + + +/* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */ +#define MAC_BASE_ADDR 0xFFE00000 /* AHB Peripheral # 0 */ +#define MAC_MAC1 (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x000)) /* MAC config reg 1 */ +#define MAC_MAC2 (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x004)) /* MAC config reg 2 */ +#define MAC_IPGT (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x008)) /* b2b InterPacketGap reg */ +#define MAC_IPGR (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x00C)) /* non b2b InterPacketGap reg */ +#define MAC_CLRT (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x010)) /* CoLlision window/ReTry reg */ +#define MAC_MAXF (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x014)) /* MAXimum Frame reg */ +#define MAC_SUPP (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x018)) /* PHY SUPPort reg */ +#define MAC_TEST (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x01C)) /* TEST reg */ +#define MAC_MCFG (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x020)) /* MII Mgmt ConFiG reg */ +#define MAC_MCMD (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x024)) /* MII Mgmt CoMmanD reg */ +#define MAC_MADR (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x028)) /* MII Mgmt ADdRess reg */ +#define MAC_MWTD (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x02C)) /* MII Mgmt WriTe Data reg (WO) */ +#define MAC_MRDD (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x030)) /* MII Mgmt ReaD Data reg (RO) */ +#define MAC_MIND (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x034)) /* MII Mgmt INDicators reg (RO) */ + +#define MAC_SA0 (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x040)) /* Station Address 0 reg */ +#define MAC_SA1 (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x044)) /* Station Address 1 reg */ +#define MAC_SA2 (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x048)) /* Station Address 2 reg */ + +#define MAC_COMMAND (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x100)) /* Command reg */ +#define MAC_STATUS (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x104)) /* Status reg (RO) */ +#define MAC_RXDESCRIPTOR (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x108)) /* Rx descriptor base address reg */ +#define MAC_RXSTATUS (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x10C)) /* Rx status base address reg */ +#define MAC_RXDESCRIPTORNUM (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x110)) /* Rx number of descriptors reg */ +#define MAC_RXPRODUCEINDEX (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x114)) /* Rx produce index reg (RO) */ +#define MAC_RXCONSUMEINDEX (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x118)) /* Rx consume index reg */ +#define MAC_TXDESCRIPTOR (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x11C)) /* Tx descriptor base address reg */ +#define MAC_TXSTATUS (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x120)) /* Tx status base address reg */ +#define MAC_TXDESCRIPTORNUM (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x124)) /* Tx number of descriptors reg */ +#define MAC_TXPRODUCEINDEX (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x128)) /* Tx produce index reg */ +#define MAC_TXCONSUMEINDEX (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x12C)) /* Tx consume index reg (RO) */ + +#define MAC_TSV0 (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x158)) /* Tx status vector 0 reg (RO) */ +#define MAC_TSV1 (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x15C)) /* Tx status vector 1 reg (RO) */ +#define MAC_RSV (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x160)) /* Rx status vector reg (RO) */ + +#define MAC_FLOWCONTROLCNT (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x170)) /* Flow control counter reg */ +#define MAC_FLOWCONTROLSTS (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x174)) /* Flow control status reg */ + +#define MAC_RXFILTERCTRL (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x200)) /* Rx filter ctrl reg */ +#define MAC_RXFILTERWOLSTS (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x204)) /* Rx filter WoL status reg (RO) */ +#define MAC_RXFILTERWOLCLR (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x208)) /* Rx filter WoL clear reg (WO) */ + +#define MAC_HASHFILTERL (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x210)) /* Hash filter LSBs reg */ +#define MAC_HASHFILTERH (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x214)) /* Hash filter MSBs reg */ + +#define MAC_INTSTATUS (*(volatile unsigned int *)(MAC_BASE_ADDR + 0xFE0)) /* Interrupt status reg (RO) */ +#define MAC_INTENABLE (*(volatile unsigned int *)(MAC_BASE_ADDR + 0xFE4)) /* Interrupt enable reg */ +#define MAC_INTCLEAR (*(volatile unsigned int *)(MAC_BASE_ADDR + 0xFE8)) /* Interrupt clear reg (WO) */ +#define MAC_INTSET (*(volatile unsigned int *)(MAC_BASE_ADDR + 0xFEC)) /* Interrupt set reg (WO) */ + +#define MAC_POWERDOWN (*(volatile unsigned int *)(MAC_BASE_ADDR + 0xFF4)) /* Power-down reg */ +#define MAC_MODULEID (*(volatile unsigned int *)(MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */ + + +#endif /* __LPC23xx_H */ + diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/Makefile b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/Makefile new file mode 100644 index 000000000..257bd9a7f --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/Makefile @@ -0,0 +1,128 @@ +# FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. +# +# This file is part of the FreeRTOS.org distribution. +# +# FreeRTOS.org is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# FreeRTOS.org is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with FreeRTOS.org; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +# +# A special exception to the GPL can be applied should you wish to distribute +# a combined work that includes FreeRTOS.org, without being obliged to provide +# the source code for any proprietary components. See the licensing section +# of http://www.FreeRTOS.org for full details of how and when the exception +# can be applied. +# +# *************************************************************************** +# See http://www.FreeRTOS.org for documentation, latest information, license +# and contact details. Please ensure to read the configuration and relevant +# port sections of the online documentation. +# *************************************************************************** + + +RTOS_SOURCE_DIR=../../../Source +DEMO_COMMON_DIR=../../Common/Minimal +DEMO_INCLUDE_DIR=../../Common/include +UIP_COMMON_DIR=../../Common/ethernet/uIP/uip-1.0/uip + +CC=arm-elf-gcc +OBJCOPY=arm-elf-objcopy +LDSCRIPT=lpc2368.ld + +LINKER_FLAGS=-mthumb -nostartfiles -Xlinker -oRTOSDemo.elf -Xlinker -M -Xlinker -Map=rtosdemo.map + +DEBUG=-g +OPTIM=-O1 + + +CFLAGS= $(DEBUG) \ + $(OPTIM) \ + -T$(LDSCRIPT) \ + -I . \ + -I $(RTOS_SOURCE_DIR)/include \ + -I $(RTOS_SOURCE_DIR)/portable/GCC/ARM7_LPC23xx \ + -I $(DEMO_INCLUDE_DIR) \ + -I ./webserver \ + -I $(UIP_COMMON_DIR) \ + -D ROWLEY_LPC23xx \ + -D THUMB_INTERWORK \ + -mcpu=arm7tdmi \ + -D PACK_STRUCT_END=__attribute\(\(packed\)\) \ + -D ALIGN_STRUCT_END=__attribute\(\(aligned\(4\)\)\) \ + -fomit-frame-pointer \ + -mthumb-interwork + +THUMB_SOURCE= \ + main.c \ + ./ParTest/ParTest.c \ + ./LCD/portlcd.c \ + $(DEMO_COMMON_DIR)/BlockQ.c \ + $(DEMO_COMMON_DIR)/blocktim.c \ + $(DEMO_COMMON_DIR)/flash.c \ + $(DEMO_COMMON_DIR)/integer.c \ + $(DEMO_COMMON_DIR)/GenQTest.c \ + $(DEMO_COMMON_DIR)/QPeek.c \ + $(DEMO_COMMON_DIR)/dynamic.c \ + ./webserver/uIP_Task.c \ + ./webserver/emac.c \ + ./webserver/httpd.c \ + ./webserver/httpd-cgi.c \ + ./webserver/httpd-fs.c \ + ./webserver/http-strings.c \ + $(UIP_COMMON_DIR)/uip_arp.c \ + $(UIP_COMMON_DIR)/psock.c \ + $(UIP_COMMON_DIR)/timer.c \ + $(UIP_COMMON_DIR)/uip.c \ + $(RTOS_SOURCE_DIR)/list.c \ + $(RTOS_SOURCE_DIR)/queue.c \ + $(RTOS_SOURCE_DIR)/tasks.c \ + $(RTOS_SOURCE_DIR)/portable/GCC/ARM7_LPC23xx/port.c \ + $(RTOS_SOURCE_DIR)/portable/MemMang/heap_2.c + +ARM_SOURCE= \ + $(RTOS_SOURCE_DIR)/portable/GCC/ARM7_LPC23xx/portISR.c \ + ./webserver/EMAC_ISR.c + +THUMB_OBJS = $(THUMB_SOURCE:.c=.o) +ARM_OBJS = $(ARM_SOURCE:.c=.o) + + +all: RTOSDemo.bin + +RTOSDemo.bin : RTOSDemo.hex + $(OBJCOPY) RTOSDemo.elf -O binary RTOSDemo.bin + +RTOSDemo.hex : RTOSDemo.elf + $(OBJCOPY) RTOSDemo.elf -O ihex RTOSDemo.hex + +RTOSDemo.elf : $(THUMB_OBJS) $(ARM_OBJS) boot.s Makefile + $(CC) $(CFLAGS) $(ARM_OBJS) $(THUMB_OBJS) $(LIBS) boot.s $(LINKER_FLAGS) + +$(THUMB_OBJS) : %.o : %.c Makefile FreeRTOSConfig.h + $(CC) -c $(CFLAGS) -mthumb $< -o $@ + +$(ARM_OBJS) : %.o : %.c Makefile FreeRTOSConfig.h + $(CC) -c $(CFLAGS) $< -o $@ + +clean : + rm $(THUMB_OBJS) + rm $(ARM_OBJS) + touch Makefile + rm RTOSDemo.elf + rm RTOSDemo.hex + + + + + + + diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/ParTest/ParTest.c b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/ParTest/ParTest.c new file mode 100644 index 000000000..83905dbfd --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/ParTest/ParTest.c @@ -0,0 +1,114 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* FreeRTOS.org includes. */ +#include "FreeRTOS.h" + +/* Demo application includes. */ +#include "partest.h" + +#define partstFIRST_IO ( ( unsigned portLONG ) 0x01 ) +#define partstNUM_LEDS ( 8 ) +#define partstALL_OUTPUTS_OFF ( ( unsigned portLONG ) 0xff ) + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ + PINSEL10 = 0; + FIO2DIR = 0x000000FF; + FIO2MASK = 0x00000000; + FIO2CLR = 0xFF; + SCS |= (1<<0); //fast mode for port 0 and 1 + + FIO2CLR = partstALL_OUTPUTS_OFF; +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ +unsigned portLONG ulLED = partstFIRST_IO; + + if( uxLED < partstNUM_LEDS ) + { + /* Rotate to the wanted bit of port */ + ulLED <<= ( unsigned portLONG ) uxLED; + + /* Set of clear the output. */ + if( xValue ) + { + FIO2CLR = ulLED; + } + else + { + FIO2SET = ulLED; + } + } +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned portLONG ulLED = partstFIRST_IO, ulCurrentState; + + if( uxLED < partstNUM_LEDS ) + { + /* Rotate to the wanted bit of port 0. Only P10 to P13 have an LED + attached. */ + ulLED <<= ( unsigned portLONG ) uxLED; + + /* If this bit is already set, clear it, and visa versa. */ + ulCurrentState = FIO2PIN; + if( ulCurrentState & ulLED ) + { + FIO2CLR = ulLED; + } + else + { + FIO2SET = ulLED; + } + } +} + +/*-----------------------------------------------------------*/ +unsigned portBASE_TYPE uxParTextGetLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned portLONG ulLED = partstFIRST_IO; + + ulLED <<= ( unsigned portLONG ) uxLED; + + return ( FIO2PIN & ulLED ); +} + + diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/boot.s b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/boot.s new file mode 100644 index 000000000..f3c4ab0e3 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/boot.s @@ -0,0 +1,157 @@ + /* Sample initialization file */ + + .extern main + .extern exit + + .text + .code 32 + + + .align 0 + + .extern __bss_beg__ + .extern __bss_end__ + .extern __stack_end__ + .extern __data_beg__ + .extern __data_end__ + .extern __data+beg_src__ + + .global start + .global endless_loop + + /* Stack Sizes */ + .set UND_STACK_SIZE, 0x00000004 + .set ABT_STACK_SIZE, 0x00000004 + .set FIQ_STACK_SIZE, 0x00000004 + .set IRQ_STACK_SIZE, 0X00000100 + .set SVC_STACK_SIZE, 0x00000100 + + /* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */ + .set MODE_USR, 0x10 /* User Mode */ + .set MODE_FIQ, 0x11 /* FIQ Mode */ + .set MODE_IRQ, 0x12 /* IRQ Mode */ + .set MODE_SVC, 0x13 /* Supervisor Mode */ + .set MODE_ABT, 0x17 /* Abort Mode */ + .set MODE_UND, 0x1B /* Undefined Mode */ + .set MODE_SYS, 0x1F /* System Mode */ + + .equ I_BIT, 0x80 /* when I bit is set, IRQ is disabled */ + .equ F_BIT, 0x40 /* when F bit is set, FIQ is disabled */ + + +start: +_start: +_mainCRTStartup: + + /* Setup a stack for each mode - note that this only sets up a usable stack + for system/user, SWI and IRQ modes. Also each mode is setup with + interrupts initially disabled. */ + ldr r0, .LC6 + msr CPSR_c, #MODE_UND|I_BIT|F_BIT /* Undefined Instruction Mode + mov sp, r0 + sub r0, r0, #UND_STACK_SIZE + msr CPSR_c, #MODE_ABT|I_BIT|F_BIT /* Abort Mode */ + mov sp, r0 + sub r0, r0, #ABT_STACK_SIZE + msr CPSR_c, #MODE_FIQ|I_BIT|F_BIT /* FIQ Mode */ + mov sp, r0 + sub r0, r0, #FIQ_STACK_SIZE + msr CPSR_c, #MODE_IRQ|I_BIT|F_BIT /* IRQ Mode */ + mov sp, r0 + sub r0, r0, #IRQ_STACK_SIZE + msr CPSR_c, #MODE_SVC|I_BIT|F_BIT /* Supervisor Mode */ + mov sp, r0 + sub r0, r0, #SVC_STACK_SIZE + msr CPSR_c, #MODE_SYS|I_BIT|F_BIT /* System Mode */ + mov sp, r0 + + /* We want to start in supervisor mode. Operation will switch to system + mode when the first task starts. */ + msr CPSR_c, #MODE_SVC|I_BIT|F_BIT + + /* Clear BSS. */ + + mov a2, #0 /* Fill value */ + mov fp, a2 /* Null frame pointer */ + mov r7, a2 /* Null frame pointer for Thumb */ + + ldr r1, .LC1 /* Start of memory block */ + ldr r3, .LC2 /* End of memory block */ + subs r3, r3, r1 /* Length of block */ + beq .end_clear_loop + mov r2, #0 + +.clear_loop: + strb r2, [r1], #1 + subs r3, r3, #1 + bgt .clear_loop + +.end_clear_loop: + + /* Initialise data. */ + + ldr r1, .LC3 /* Start of memory block */ + ldr r2, .LC4 /* End of memory block */ + ldr r3, .LC5 + subs r3, r3, r1 /* Length of block */ + beq .end_set_loop + +.set_loop: + ldrb r4, [r2], #1 + strb r4, [r1], #1 + subs r3, r3, #1 + bgt .set_loop + +.end_set_loop: + + mov r0, #0 /* no arguments */ + mov r1, #0 /* no argv either */ + + bl main + +endless_loop: + b endless_loop + + + .align 0 + + .LC1: + .word __bss_beg__ + .LC2: + .word __bss_end__ + .LC3: + .word __data_beg__ + .LC4: + .word __data_beg_src__ + .LC5: + .word __data_end__ + .LC6: + .word __stack_end__ + + + /* Setup vector table. Note that undf, pabt, dabt, fiq just execute + a null loop. */ + +.section .startup,"ax" + .code 32 + .align 0 + + b _start /* reset - _start */ + ldr pc, _undf /* undefined - _undf */ + ldr pc, _swi /* SWI - _swi */ + ldr pc, _pabt /* program abort - _pabt */ + ldr pc, _dabt /* data abort - _dabt */ + nop /* reserved */ + ldr pc, [pc,#-0x120] /* IRQ - read the VIC */ + ldr pc, _fiq /* FIQ - _fiq */ + +_undf: .word __undf /* undefined */ +_swi: .word vPortYieldProcessor /* SWI */ +_pabt: .word __pabt /* program abort */ +_dabt: .word __dabt /* data abort */ +_fiq: .word __fiq /* FIQ */ + +__undf: b . /* undefined */ +__pabt: b . /* program abort */ +__dabt: b . /* data abort */ +__fiq: b . /* FIQ */ diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/lpc2368.ld b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/lpc2368.ld new file mode 100644 index 000000000..79a37e6ec --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/lpc2368.ld @@ -0,0 +1,67 @@ +MEMORY +{ + flash : ORIGIN = 0x00000000, LENGTH = 500K + ram : ORIGIN = 0x40000000, LENGTH = 32K + usbram : ORIGIN = 0x7FD00000, LENGTH = 8K + ethram : ORIGIN = 0x7FE00000, LENGTH = 16K +} + +__stack_end__ = 0x40000000 + 32K - 4; + +SECTIONS +{ + . = 0; + startup : { *(.startup)} >flash + + prog : + { + *(.text) + *(.rodata) + *(.rodata*) + *(.glue_7) + *(.glue_7t) + } >flash + + __end_of_text__ = .; + + .data : + { + __data_beg__ = .; + __data_beg_src__ = __end_of_text__; + *(.data) + __data_end__ = .; + } >ram AT>flash + + .bss : + { + __bss_beg__ = .; + *(.bss) + } >ram + + /* Align here to ensure that the .bss section occupies space up to + _end. Align after .bss to ensure correct alignment even if the + .bss section disappears because there are no input sections. */ + . = ALIGN(32 / 8); + + .usbram (NOLOAD): + { + __usbram_beg__ = .; + *(.dmaram) + __usbram_end__ = .; + } >usbram + + .ethram (NOLOAD): + { + __ethram_beg__ = .; + *(.ethram) + __ethram_end__ = .; + } >ethram + + +} + . = ALIGN(32 / 8); + _end = .; + _bss_end__ = . ; __bss_end__ = . ; __end__ = . ; + PROVIDE (end = .); + + diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/main.c b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/main.c new file mode 100644 index 000000000..25b2c120a --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/main.c @@ -0,0 +1,297 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + * Creates all the demo application tasks, then starts the scheduler. The WEB + * documentation provides more details of the standard demo application tasks. + * In addition to the standard demo tasks, the following tasks and tests are + * defined and/or created within this file: + * + * "LCD" task - the LCD task is a 'gatekeeper' task. It is the only task that + * is permitted to access the display directly. Other tasks wishing to write a + * message to the LCD send the message on a queue to the LCD task instead of + * accessing the LCD themselves. The LCD task just blocks on the queue waiting + * for messages - waking and displaying the messages as they arrive. + * + * "Check" hook - This only executes every five seconds from the tick hook. + * Its main function is to check that all the standard demo tasks are still + * operational. Should any unexpected behaviour within a demo task be discovered + * the tick hook will write an error to the LCD (via the LCD task). If all the + * demo tasks are executing with their expected behaviour then the check task + * writes PASS to the LCD (again via the LCD task), as described above. + * + * "uIP" task - This is the task that handles the uIP stack. All TCP/IP + * processing is performed in this task. + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "Task.h" +#include "queue.h" +#include "semphr.h" + +/* Demo app includes. */ +#include "BlockQ.h" +#include "death.h" +#include "blocktim.h" +#include "LCD/portlcd.h" +#include "flash.h" +#include "partest.h" +#include "GenQTest.h" +#include "QPeek.h" +#include "dynamic.h" + +/* Demo application definitions. */ +#define mainQUEUE_SIZE ( 3 ) +#define mainCHECK_DELAY ( ( portTickType ) 5000 / portTICK_RATE_MS ) +#define mainBASIC_WEB_STACK_SIZE ( configMINIMAL_STACK_SIZE * 6 ) + +/* Task priorities. */ +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainFLASH_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY ) + +/* Constants to setup the PLL. */ +#define mainPLL_MUL ( ( unsigned portLONG ) ( 8 - 1 ) ) +#define mainPLL_DIV ( ( unsigned portLONG ) 0x0000 ) +#define mainCPU_CLK_DIV ( ( unsigned portLONG ) 0x0003 ) +#define mainPLL_ENABLE ( ( unsigned portLONG ) 0x0001 ) +#define mainPLL_CONNECT ( ( ( unsigned portLONG ) 0x0002 ) | mainPLL_ENABLE ) +#define mainPLL_FEED_BYTE1 ( ( unsigned portLONG ) 0xaa ) +#define mainPLL_FEED_BYTE2 ( ( unsigned portLONG ) 0x55 ) +#define mainPLL_LOCK ( ( unsigned portLONG ) 0x4000000 ) +#define mainPLL_CONNECTED ( ( unsigned portLONG ) 0x2000000 ) +#define mainOSC_ENABLE ( ( unsigned portLONG ) 0x20 ) +#define mainOSC_STAT ( ( unsigned portLONG ) 0x40 ) +#define mainOSC_SELECT ( ( unsigned portLONG ) 0x01 ) + +/* Constants to setup the MAM. */ +#define mainMAM_TIM_3 ( ( unsigned portCHAR ) 0x03 ) +#define mainMAM_MODE_FULL ( ( unsigned portCHAR ) 0x02 ) + +/* + * The task that handles the uIP stack. All TCP/IP processing is performed in + * this task. + */ +extern void vuIP_Task( void *pvParameters ); + +/* + * The LCD is written two by more than one task so is controlled by a + * 'gatekeeper' task. This is the only task that is actually permitted to + * access the LCD directly. Other tasks wanting to display a message send + * the message to the gatekeeper. + */ +static void vLCDTask( void *pvParameters ); + +/* Configure the hardware as required by the demo. */ +static void prvSetupHardware( void ); + +/* The queue used to send messages to the LCD task. */ +xQueueHandle xLCDQueue; + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + prvSetupHardware(); + + /* Create the queue used by the LCD task. Messages for display on the LCD + are received via this queue. */ + xLCDQueue = xQueueCreate( mainQUEUE_SIZE, sizeof( xLCDMessage ) ); + + /* Create the uIP task. This uses the lwIP RTOS abstraction layer.*/ + xTaskCreate( vuIP_Task, ( signed portCHAR * ) "uIP", mainBASIC_WEB_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY - 1, NULL ); + + /* Start the standard demo tasks. */ + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vCreateBlockTimeTasks(); + vStartLEDFlashTasks( mainFLASH_PRIORITY ); + vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY ); + vStartQueuePeekTasks(); + vStartDynamicPriorityTasks(); + + /* Start the tasks defined within this file/specific to this demo. */ + xTaskCreate( vLCDTask, ( signed portCHAR * ) "LCD", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY - 1, NULL ); + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* Will only get here if there was insufficient memory to create the idle + task. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vApplicationTickHook( void ) +{ +unsigned portBASE_TYPE uxColumn = 0; +static xLCDMessage xMessage = { 0, "PASS" }; +static unsigned portLONG ulTicksSinceLastDisplay = 0; + + /* Called from every tick interrupt. Have enough ticks passed to make it + time to perform our health status check again? */ + ulTicksSinceLastDisplay++; + if( ulTicksSinceLastDisplay >= mainCHECK_DELAY ) + { + ulTicksSinceLastDisplay = 0; + + /* Has an error been found in any task? */ + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR - BLOCKQ"; + } + + if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR - BLOCKTIM"; + } + + if( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR - GENQ"; + } + + if( xAreQueuePeekTasksStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR - PEEKQ"; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR - DYNAMIC"; + } + + xMessage.xColumn++; + + /* Send the message to the LCD gatekeeper for display. */ + xQueueSendToBackFromISR( xLCDQueue, &xMessage, pdFALSE ); + } +} +/*-----------------------------------------------------------*/ + +void vLCDTask( void *pvParameters ) +{ +xLCDMessage xMessage; + + /* Initialise the LCD and display a startup message. */ + LCD_init(); + LCD_cur_off(); + LCD_cls(); + LCD_gotoxy( 1, 1 ); + LCD_puts( "www.FreeRTOS.org" ); + + for( ;; ) + { + /* Wait for a message to arrive that requires displaying. */ + while( xQueueReceive( xLCDQueue, &xMessage, portMAX_DELAY ) != pdPASS ); + + /* Display the message. Print each message to a different position. */ + LCD_cls(); + LCD_gotoxy( ( xMessage.xColumn & 0x07 ) + 1, ( xMessage.xColumn & 0x01 ) + 1 ); + LCD_puts( xMessage.pcMessage ); + } + +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + #ifdef RUN_FROM_RAM + /* Remap the interrupt vectors to RAM if we are are running from RAM. */ + SCB_MEMMAP = 2; + #endif + + /* Disable the PLL. */ + PLLCON = 0; + PLLFEED = mainPLL_FEED_BYTE1; + PLLFEED = mainPLL_FEED_BYTE2; + + /* Configure clock source. */ + SCS |= mainOSC_ENABLE; + while( !( SCS & mainOSC_STAT ) ); + CLKSRCSEL = mainOSC_SELECT; + + /* Setup the PLL to multiply the XTAL input by 4. */ + PLLCFG = ( mainPLL_MUL | mainPLL_DIV ); + PLLFEED = mainPLL_FEED_BYTE1; + PLLFEED = mainPLL_FEED_BYTE2; + + /* Turn on and wait for the PLL to lock... */ + PLLCON = mainPLL_ENABLE; + PLLFEED = mainPLL_FEED_BYTE1; + PLLFEED = mainPLL_FEED_BYTE2; + CCLKCFG = mainCPU_CLK_DIV; + while( !( PLLSTAT & mainPLL_LOCK ) ); + + /* Connecting the clock. */ + PLLCON = mainPLL_CONNECT; + PLLFEED = mainPLL_FEED_BYTE1; + PLLFEED = mainPLL_FEED_BYTE2; + while( !( PLLSTAT & mainPLL_CONNECTED ) ); + + /* + This code is commented out as the MAM does not work on the original revision + LPC2368 chips. If using Rev B chips then you can increase the speed though + the use of the MAM. + + Setup and turn on the MAM. Three cycle access is used due to the fast + PLL used. It is possible faster overall performance could be obtained by + tuning the MAM and PLL settings. + MAMCR = 0; + MAMTIM = mainMAM_TIM_3; + MAMCR = mainMAM_MODE_FULL; + */ + + /* Setup the led's on the MCB2300 board */ + vParTestInitialise(); +} + + + + + + + diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/EMAC_ISR.c b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/EMAC_ISR.c new file mode 100644 index 000000000..b78837d13 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/EMAC_ISR.c @@ -0,0 +1,43 @@ +#include "FreeRTOS.h" +#include "Semphr.h" +#include "Task.h" + +/* The interrupt entry point. */ +void vEMAC_ISR_Wrapper( void ) __attribute__((naked)); + +/* The handler that does the actual work. */ +void vEMAC_ISR_Handler( void ); + +extern xSemaphoreHandle xEMACSemaphore; + + +void vEMAC_ISR_Handler( void ) +{ +portBASE_TYPE xSwitchRequired = pdFALSE; + + /* Clear the interrupt. */ + MAC_INTCLEAR = 0xffff; + VICVectAddr = 0; + + /* Ensure the uIP task is not blocked as data has arrived. */ + if( xSemaphoreGiveFromISR( xEMACSemaphore, pdFALSE ) ) + { + /* Giving the semaphore woke a task. */ + portYIELD_FROM_ISR(); + } +} +/*-----------------------------------------------------------*/ + +void vEMAC_ISR_Wrapper( void ) +{ + /* Save the context of the interrupted task. */ + portSAVE_CONTEXT(); + + /* Call the handler. This must be a separate function unless you can + guarantee that no stack will be used. */ + vEMAC_ISR_Handler(); + + /* Restore the context of whichever task is going to run next. */ + portRESTORE_CONTEXT(); +} + diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/clock-arch.h b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/clock-arch.h new file mode 100644 index 000000000..cde657b62 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/clock-arch.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2006, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: clock-arch.h,v 1.2 2006/06/12 08:00:31 adam Exp $ + */ + +#ifndef __CLOCK_ARCH_H__ +#define __CLOCK_ARCH_H__ + +#include "FreeRTOS.h" + +typedef unsigned long clock_time_t; +#define CLOCK_CONF_SECOND configTICK_RATE_HZ + +#endif /* __CLOCK_ARCH_H__ */ diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/emac.c b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/emac.c new file mode 100644 index 000000000..f6ab537a7 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/emac.c @@ -0,0 +1,411 @@ +/****************************************************************** + ***** ***** + ***** Name: cs8900.c ***** + ***** Ver.: 1.0 ***** + ***** Date: 07/05/2001 ***** + ***** Auth: Andreas Dannenberg ***** + ***** HTWK Leipzig ***** + ***** university of applied sciences ***** + ***** Germany ***** + ***** Func: ethernet packet-driver for use with LAN- ***** + ***** controller CS8900 from Crystal/Cirrus Logic ***** + ***** ***** + ***** Keil: Module modified for use with Philips ***** + ***** LPC2378 EMAC Ethernet controller ***** + ***** ***** + ******************************************************************/ + +/* Adapted from file originally written by Andreas Dannenberg. Supplied with permission. */ + +#include "FreeRTOS.h" +#include "Semphr.h" +#include "task.h" +#include "EMAC.h" + +/* The semaphore used to wake the uIP task when data arives. */ +xSemaphoreHandle xEMACSemaphore = NULL; + +static unsigned short *rptr; +static unsigned short *tptr; + +// easyWEB internal function +// help function to swap the byte order of a WORD + +static unsigned short SwapBytes(unsigned short Data) +{ + return (Data >> 8) | (Data << 8); +} + +// Keil: function added to write PHY +void write_PHY (int PhyReg, int Value) +{ + unsigned int tout; + + MAC_MADR = DP83848C_DEF_ADR | PhyReg; + MAC_MWTD = Value; + + /* Wait utill operation completed */ + tout = 0; + for (tout = 0; tout < MII_WR_TOUT; tout++) { + if ((MAC_MIND & MIND_BUSY) == 0) { + break; + } + } +} + + +// Keil: function added to read PHY +unsigned short read_PHY (unsigned char PhyReg) +{ + unsigned int tout; + + MAC_MADR = DP83848C_DEF_ADR | PhyReg; + MAC_MCMD = MCMD_READ; + + /* Wait until operation completed */ + tout = 0; + for (tout = 0; tout < MII_RD_TOUT; tout++) { + if ((MAC_MIND & MIND_BUSY) == 0) { + break; + } + } + MAC_MCMD = 0; + return (MAC_MRDD); +} + + +// Keil: function added to initialize Rx Descriptors +void rx_descr_init (void) +{ + unsigned int i; + + for (i = 0; i < NUM_RX_FRAG; i++) { + RX_DESC_PACKET(i) = RX_BUF(i); + RX_DESC_CTRL(i) = RCTRL_INT | (ETH_FRAG_SIZE-1); + RX_STAT_INFO(i) = 0; + RX_STAT_HASHCRC(i) = 0; + } + + /* Set EMAC Receive Descriptor Registers. */ + MAC_RXDESCRIPTOR = RX_DESC_BASE; + MAC_RXSTATUS = RX_STAT_BASE; + MAC_RXDESCRIPTORNUM = NUM_RX_FRAG-1; + + /* Rx Descriptors Point to 0 */ + MAC_RXCONSUMEINDEX = 0; +} + + +// Keil: function added to initialize Tx Descriptors +void tx_descr_init (void) { + unsigned int i; + + for (i = 0; i < NUM_TX_FRAG; i++) { + TX_DESC_PACKET(i) = TX_BUF(i); + TX_DESC_CTRL(i) = 0; + TX_STAT_INFO(i) = 0; + } + + /* Set EMAC Transmit Descriptor Registers. */ + MAC_TXDESCRIPTOR = TX_DESC_BASE; + MAC_TXSTATUS = TX_STAT_BASE; + MAC_TXDESCRIPTORNUM = NUM_TX_FRAG-1; + + /* Tx Descriptors Point to 0 */ + MAC_TXPRODUCEINDEX = 0; +} + + +// configure port-pins for use with LAN-controller, +// reset it and send the configuration-sequence + +portBASE_TYPE Init_EMAC(void) +{ +portBASE_TYPE xReturn = pdPASS; + +// Keil: function modified to access the EMAC +// Initializes the EMAC ethernet controller + volatile unsigned int regv,tout,id1,id2; + + /* Enable P1 Ethernet Pins. */ + PINSEL2 = configPINSEL2_VALUE; + PINSEL3 = (PINSEL3 & ~0x0000000F) | 0x00000005; + + /* Power Up the EMAC controller. */ + PCONP |= 0x40000000; + vTaskDelay( 1 ); + + /* Reset all EMAC internal modules. */ + MAC_MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES; + MAC_COMMAND = CR_REG_RES | CR_TX_RES | CR_RX_RES; + + /* A short delay after reset. */ + vTaskDelay( 1 ); + + /* Initialize MAC control registers. */ + MAC_MAC1 = MAC1_PASS_ALL; + MAC_MAC2 = MAC2_CRC_EN | MAC2_PAD_EN; + MAC_MAXF = ETH_MAX_FLEN; + MAC_CLRT = CLRT_DEF; + MAC_IPGR = IPGR_DEF; + + /* Enable Reduced MII interface. */ + MAC_COMMAND = CR_RMII | CR_PASS_RUNT_FRM; + + /* Reset Reduced MII Logic. */ + MAC_SUPP = SUPP_RES_RMII; + MAC_SUPP = 0; + + /* Put the DP83848C in reset mode */ + write_PHY (PHY_REG_BMCR, 0x8000); + write_PHY (PHY_REG_BMCR, 0x8000); + + /* Wait for hardware reset to end. */ + for (tout = 0; tout < 100; tout++) { + vTaskDelay( 10 ); + regv = read_PHY (PHY_REG_BMCR); + if (!(regv & 0x8000)) { + /* Reset complete */ + break; + } + } + + /* Check if this is a DP83848C PHY. */ + id1 = read_PHY (PHY_REG_IDR1); + id2 = read_PHY (PHY_REG_IDR2); + if (((id1 << 16) | (id2 & 0xFFF0)) == DP83848C_ID) { + /* Configure the PHY device */ + + /* Use autonegotiation about the link speed. */ + write_PHY (PHY_REG_BMCR, PHY_AUTO_NEG); + /* Wait to complete Auto_Negotiation. */ + for (tout = 0; tout < 10; tout++) { + vTaskDelay( 100 ); + regv = read_PHY (PHY_REG_BMSR); + if (regv & 0x0020) { + /* Autonegotiation Complete. */ + break; + } + } + } + else + { + xReturn = pdFAIL; + } + + /* Check the link status. */ + if( xReturn == pdPASS ) + { + xReturn = pdFAIL; + for (tout = 0; tout < 10; tout++) { + vTaskDelay( 100 ); + regv = read_PHY (PHY_REG_STS); + if (regv & 0x0001) { + /* Link is on. */ + xReturn = pdPASS; + break; + } + } + } + + if( xReturn == pdPASS ) + { + /* Configure Full/Half Duplex mode. */ + if (regv & 0x0004) { + /* Full duplex is enabled. */ + MAC_MAC2 |= MAC2_FULL_DUP; + MAC_COMMAND |= CR_FULL_DUP; + MAC_IPGT = IPGT_FULL_DUP; + } + else { + /* Half duplex mode. */ + MAC_IPGT = IPGT_HALF_DUP; + } + + /* Configure 100MBit/10MBit mode. */ + if (regv & 0x0002) { + /* 10MBit mode. */ + MAC_SUPP = 0; + } + else { + /* 100MBit mode. */ + MAC_SUPP = SUPP_SPEED; + } + + /* Set the Ethernet MAC Address registers */ + MAC_SA0 = (emacETHADDR0 << 8) | emacETHADDR1; + MAC_SA1 = (emacETHADDR2 << 8) | emacETHADDR3; + MAC_SA2 = (emacETHADDR4 << 8) | emacETHADDR5; + + /* Initialize Tx and Rx DMA Descriptors */ + rx_descr_init (); + tx_descr_init (); + + /* Receive Broadcast and Perfect Match Packets */ + MAC_RXFILTERCTRL = RFC_UCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN; + + /* Create the semaphore used ot wake the uIP task. */ + vSemaphoreCreateBinary( xEMACSemaphore ); + + /* Reset all interrupts */ + MAC_INTCLEAR = 0xFFFF; + + /* Enable receive and transmit mode of MAC Ethernet core */ + MAC_COMMAND |= (CR_RX_EN | CR_TX_EN); + MAC_MAC1 |= MAC1_REC_EN; + } + + return xReturn; +} + + +// reads a word in little-endian byte order from RX_BUFFER + +unsigned short ReadFrame_EMAC(void) +{ + return (*rptr++); +} + +// reads a word in big-endian byte order from RX_FRAME_PORT +// (useful to avoid permanent byte-swapping while reading +// TCP/IP-data) + +unsigned short ReadFrameBE_EMAC(void) +{ + unsigned short ReturnValue; + + ReturnValue = SwapBytes (*rptr++); + return (ReturnValue); +} + + +// copies bytes from frame port to MCU-memory +// NOTES: * an odd number of byte may only be transfered +// if the frame is read to the end! +// * MCU-memory MUST start at word-boundary + +void CopyFromFrame_EMAC(void *Dest, unsigned short Size) +{ + unsigned short * piDest; // Keil: Pointer added to correct expression + + piDest = Dest; // Keil: Line added + while (Size > 1) { + *piDest++ = ReadFrame_EMAC(); + Size -= 2; + } + + if (Size) { // check for leftover byte... + *(unsigned char *)piDest = (char)ReadFrame_EMAC();// the LAN-Controller will return 0 + } // for the highbyte +} + +// does a dummy read on frame-I/O-port +// NOTE: only an even number of bytes is read! + +void DummyReadFrame_EMAC(unsigned short Size) // discards an EVEN number of bytes +{ // from RX-fifo + while (Size > 1) { + ReadFrame_EMAC(); + Size -= 2; + } +} + +// Reads the length of the received ethernet frame and checks if the +// destination address is a broadcast message or not +// returns the frame length +unsigned short StartReadFrame(void) { + unsigned short RxLen; + unsigned int idx; + + idx = MAC_RXCONSUMEINDEX; + RxLen = (RX_STAT_INFO(idx) & RINFO_SIZE) - 3; + rptr = (unsigned short *)RX_DESC_PACKET(idx); + return(RxLen); +} + +void EndReadFrame(void) { + unsigned int idx; + + /* DMA free packet. */ + idx = MAC_RXCONSUMEINDEX; + + if (++idx == NUM_RX_FRAG) + idx = 0; + + MAC_RXCONSUMEINDEX = idx; +} + +unsigned int CheckFrameReceived(void) { // Packet received ? + + if (MAC_RXPRODUCEINDEX != MAC_RXCONSUMEINDEX) // more packets received ? + return(1); + else + return(0); +} + +unsigned int uiGetEMACRxData( unsigned char *ucBuffer ) +{ +unsigned int uiLen = 0; + + if( MAC_RXPRODUCEINDEX != MAC_RXCONSUMEINDEX ) + { + uiLen = StartReadFrame(); + CopyFromFrame_EMAC( ucBuffer, uiLen ); + EndReadFrame(); + } + + return uiLen; +} + +// requests space in EMAC memory for storing an outgoing frame + +void RequestSend(void) +{ + unsigned int idx; + + idx = MAC_TXPRODUCEINDEX; + tptr = (unsigned short *)TX_DESC_PACKET(idx); +} + +// check if ethernet controller is ready to accept the +// frame we want to send + +unsigned int Rdy4Tx(void) +{ + return (1); // the ethernet controller transmits much faster +} // than the CPU can load its buffers + + +// writes a word in little-endian byte order to TX_BUFFER +void WriteFrame_EMAC(unsigned short Data) +{ + *tptr++ = Data; +} + +// copies bytes from MCU-memory to frame port +// NOTES: * an odd number of byte may only be transfered +// if the frame is written to the end! +// * MCU-memory MUST start at word-boundary + +void CopyToFrame_EMAC(void *Source, unsigned int Size) +{ + unsigned short * piSource; + + piSource = Source; + Size = (Size + 1) & 0xFFFE; // round Size up to next even number + while (Size > 0) { + WriteFrame_EMAC(*piSource++); + Size -= 2; + } +} + +void DoSend_EMAC(unsigned short FrameSize) +{ + unsigned int idx; + + idx = MAC_TXPRODUCEINDEX; + TX_DESC_CTRL(idx) = FrameSize | TCTRL_LAST; + if (++idx == NUM_TX_FRAG) idx = 0; + MAC_TXPRODUCEINDEX = idx; +} + diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/emac.h b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/emac.h new file mode 100644 index 000000000..c3634217d --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/emac.h @@ -0,0 +1,322 @@ +/*---------------------------------------------------------------------------- + * LPC2378 Ethernet Definitions + *---------------------------------------------------------------------------- + * Name: EMAC.H + * Purpose: Philips LPC2378 EMAC hardware definitions + *---------------------------------------------------------------------------- + * Copyright (c) 2006 KEIL - An ARM Company. All rights reserved. + *---------------------------------------------------------------------------*/ +#ifndef __EMAC_H +#define __EMAC_H + +/* MAC address definition. The MAC address must be unique on the network. */ +#define emacETHADDR0 0 +#define emacETHADDR1 0xbd +#define emacETHADDR2 0x33 +#define emacETHADDR3 0x02 +#define emacETHADDR4 0x64 +#define emacETHADDR5 0x24 + + +/* EMAC Memory Buffer configuration for 16K Ethernet RAM. */ +#define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */ +#define NUM_TX_FRAG 2 /* Num.of TX Fragments 2*1536= 3.0kB */ +#define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */ + +#define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */ + +/* EMAC variables located in 16K Ethernet SRAM */ +#define RX_DESC_BASE 0x7FE00000 +#define RX_STAT_BASE (RX_DESC_BASE + NUM_RX_FRAG*8) +#define TX_DESC_BASE (RX_STAT_BASE + NUM_RX_FRAG*8) +#define TX_STAT_BASE (TX_DESC_BASE + NUM_TX_FRAG*8) +#define RX_BUF_BASE (TX_STAT_BASE + NUM_TX_FRAG*4) +#define TX_BUF_BASE (RX_BUF_BASE + NUM_RX_FRAG*ETH_FRAG_SIZE) + +/* RX and TX descriptor and status definitions. */ +#define RX_DESC_PACKET(i) (*(unsigned int *)(RX_DESC_BASE + 8*i)) +#define RX_DESC_CTRL(i) (*(unsigned int *)(RX_DESC_BASE+4 + 8*i)) +#define RX_STAT_INFO(i) (*(unsigned int *)(RX_STAT_BASE + 8*i)) +#define RX_STAT_HASHCRC(i) (*(unsigned int *)(RX_STAT_BASE+4 + 8*i)) +#define TX_DESC_PACKET(i) (*(unsigned int *)(TX_DESC_BASE + 8*i)) +#define TX_DESC_CTRL(i) (*(unsigned int *)(TX_DESC_BASE+4 + 8*i)) +#define TX_STAT_INFO(i) (*(unsigned int *)(TX_STAT_BASE + 4*i)) +#define RX_BUF(i) (RX_BUF_BASE + ETH_FRAG_SIZE*i) +#define TX_BUF(i) (TX_BUF_BASE + ETH_FRAG_SIZE*i) + +/* MAC Configuration Register 1 */ +#define MAC1_REC_EN 0x00000001 /* Receive Enable */ +#define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */ +#define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */ +#define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */ +#define MAC1_LOOPB 0x00000010 /* Loop Back Mode */ +#define MAC1_RES_TX 0x00000100 /* Reset TX Logic */ +#define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */ +#define MAC1_RES_RX 0x00000400 /* Reset RX Logic */ +#define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */ +#define MAC1_SIM_RES 0x00004000 /* Simulation Reset */ +#define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */ + +/* MAC Configuration Register 2 */ +#define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */ +#define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */ +#define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */ +#define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */ +#define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */ +#define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */ +#define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */ +#define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */ +#define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */ +#define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */ +#undef MAC2_NO_BACKOFF /* Remove compiler warning. */ +#define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */ +#define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */ +#define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */ + +/* Back-to-Back Inter-Packet-Gap Register */ +#define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */ +#define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */ + +/* Non Back-to-Back Inter-Packet-Gap Register */ +#define IPGR_DEF 0x00000012 /* Recommended value */ + +/* Collision Window/Retry Register */ +#define CLRT_DEF 0x0000370F /* Default value */ + +/* PHY Support Register */ +#undef SUPP_SPEED /* Remove compiler warning. */ +#define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */ +#define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */ + +/* Test Register */ +#define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */ +#define TEST_TST_PAUSE 0x00000002 /* Test Pause */ +#define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */ + +/* MII Management Configuration Register */ +#define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */ +#define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */ +#define MCFG_CLK_SEL 0x0000001C /* Clock Select Mask */ +#define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */ + +/* MII Management Command Register */ +#undef MCMD_READ /* Remove compiler warning. */ +#define MCMD_READ 0x00000001 /* MII Read */ +#undef MCMD_SCAN /* Remove compiler warning. */ +#define MCMD_SCAN 0x00000002 /* MII Scan continuously */ + +#define MII_WR_TOUT 0x00050000 /* MII Write timeout count */ +#define MII_RD_TOUT 0x00050000 /* MII Read timeout count */ + +/* MII Management Address Register */ +#define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */ +#define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */ + +/* MII Management Indicators Register */ +#undef MIND_BUSY /* Remove compiler warning. */ +#define MIND_BUSY 0x00000001 /* MII is Busy */ +#define MIND_SCAN 0x00000002 /* MII Scanning in Progress */ +#define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */ +#define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */ + +/* Command Register */ +#define CR_RX_EN 0x00000001 /* Enable Receive */ +#define CR_TX_EN 0x00000002 /* Enable Transmit */ +#define CR_REG_RES 0x00000008 /* Reset Host Registers */ +#define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */ +#define CR_RX_RES 0x00000020 /* Reset Receive Datapath */ +#define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */ +#define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */ +#define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */ +#define CR_RMII 0x00000200 /* Reduced MII Interface */ +#define CR_FULL_DUP 0x00000400 /* Full Duplex */ + +/* Status Register */ +#define SR_RX_EN 0x00000001 /* Enable Receive */ +#define SR_TX_EN 0x00000002 /* Enable Transmit */ + +/* Transmit Status Vector 0 Register */ +#define TSV0_CRC_ERR 0x00000001 /* CRC error */ +#define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */ +#define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */ +#define TSV0_DONE 0x00000008 /* Tramsmission Completed */ +#define TSV0_MCAST 0x00000010 /* Multicast Destination */ +#define TSV0_BCAST 0x00000020 /* Broadcast Destination */ +#define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */ +#define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */ +#define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */ +#define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */ +#define TSV0_GIANT 0x00000400 /* Giant Frame */ +#define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */ +#define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */ +#define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */ +#define TSV0_PAUSE 0x20000000 /* Pause Frame */ +#define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */ +#define TSV0_VLAN 0x80000000 /* VLAN Frame */ + +/* Transmit Status Vector 1 Register */ +#define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */ +#define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */ + +/* Receive Status Vector Register */ +#define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */ +#define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */ +#define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */ +#define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */ +#define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */ +#define RSV_CRC_ERR 0x00100000 /* CRC Error */ +#define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */ +#define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */ +#define RSV_REC_OK 0x00800000 /* Frame Received OK */ +#define RSV_MCAST 0x01000000 /* Multicast Frame */ +#define RSV_BCAST 0x02000000 /* Broadcast Frame */ +#define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */ +#define RSV_CTRL_FRAME 0x08000000 /* Control Frame */ +#define RSV_PAUSE 0x10000000 /* Pause Frame */ +#define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */ +#define RSV_VLAN 0x40000000 /* VLAN Frame */ + +/* Flow Control Counter Register */ +#define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */ +#define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */ + +/* Flow Control Status Register */ +#define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */ + +/* Receive Filter Control Register */ +#define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */ +#define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */ +#define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */ +#define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */ +#define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/ +#define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */ +#define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */ +#define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */ + +/* Receive Filter WoL Status/Clear Registers */ +#define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */ +#define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */ +#define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */ +#define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */ +#define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */ +#define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */ +#define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */ +#define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */ + +/* Interrupt Status/Enable/Clear/Set Registers */ +#define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */ +#define INT_RX_ERR 0x00000002 /* Receive Error */ +#define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */ +#define INT_RX_DONE 0x00000008 /* Receive Done */ +#define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */ +#define INT_TX_ERR 0x00000020 /* Transmit Error */ +#define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */ +#define INT_TX_DONE 0x00000080 /* Transmit Done */ +#define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */ +#define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */ + +/* Power Down Register */ +#define PD_POWER_DOWN 0x80000000 /* Power Down MAC */ + +/* RX Descriptor Control Word */ +#define RCTRL_SIZE 0x000007FF /* Buffer size mask */ +#define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */ + +/* RX Status Hash CRC Word */ +#define RHASH_SA 0x000001FF /* Hash CRC for Source Address */ +#define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */ + +/* RX Status Information Word */ +#define RINFO_SIZE 0x000007FF /* Data size in bytes */ +#define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */ +#define RINFO_VLAN 0x00080000 /* VLAN Frame */ +#define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */ +#define RINFO_MCAST 0x00200000 /* Multicast Frame */ +#define RINFO_BCAST 0x00400000 /* Broadcast Frame */ +#define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */ +#define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */ +#define RINFO_LEN_ERR 0x02000000 /* Length Error */ +#define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */ +#define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */ +#define RINFO_OVERRUN 0x10000000 /* Receive overrun */ +#define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */ +#define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */ +#define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ + +#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | \ + RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN) + +/* TX Descriptor Control Word */ +#define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */ +#define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */ +#define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */ +#define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */ +#define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */ +#define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */ +#define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */ + +/* TX Status Information Word */ +#define TINFO_COL_CNT 0x01E00000 /* Collision Count */ +#define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */ +#define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */ +#define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */ +#define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */ +#define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */ +#define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */ +#define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ + +/* DP83848C PHY Registers */ +#define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */ +#define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */ +#define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */ +#define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */ +#define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */ +#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */ +#define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */ +#define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */ + +/* PHY Extended Registers */ +#define PHY_REG_STS 0x10 /* Status Register */ +#define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */ +#define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */ +#define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */ +#define PHY_REG_RECR 0x15 /* Receive Error Counter */ +#define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */ +#define PHY_REG_RBR 0x17 /* RMII and Bypass Register */ +#define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */ +#define PHY_REG_PHYCR 0x19 /* PHY Control Register */ +#define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */ +#define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */ +#define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */ + +#define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */ +#define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */ +#define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */ +#define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */ +#define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */ + +#define DP83848C_DEF_ADR 0x0100 /* Default PHY device address */ +#define DP83848C_ID 0x20005C90 /* PHY Identifier */ + +// prototypes +portBASE_TYPE Init_EMAC(void); +unsigned short ReadFrameBE_EMAC(void); +void CopyToFrame_EMAC(void *Source, unsigned int Size); +void CopyFromFrame_EMAC(void *Dest, unsigned short Size); +void DummyReadFrame_EMAC(unsigned short Size); +unsigned short StartReadFrame(void); +void EndReadFrame(void); +unsigned int CheckFrameReceived(void); +void RequestSend(void); +unsigned int Rdy4Tx(void); +void DoSend_EMAC(unsigned short FrameSize); +void vEMACWaitForInput( void ); +unsigned int uiGetEMACRxData( unsigned char *ucBuffer ); + + +#endif + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/http-strings b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/http-strings new file mode 100644 index 000000000..0d3c30cdd --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/http-strings @@ -0,0 +1,35 @@ +http_http "http://" +http_200 "200 " +http_301 "301 " +http_302 "302 " +http_get "GET " +http_10 "HTTP/1.0" +http_11 "HTTP/1.1" +http_content_type "content-type: " +http_texthtml "text/html" +http_location "location: " +http_host "host: " +http_crnl "\r\n" +http_index_html "/index.html" +http_404_html "/404.html" +http_referer "Referer:" +http_header_200 "HTTP/1.0 200 OK\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" +http_header_404 "HTTP/1.0 404 Not found\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" +http_content_type_plain "Content-type: text/plain\r\n\r\n" +http_content_type_html "Content-type: text/html\r\n\r\n" +http_content_type_css "Content-type: text/css\r\n\r\n" +http_content_type_text "Content-type: text/text\r\n\r\n" +http_content_type_png "Content-type: image/png\r\n\r\n" +http_content_type_gif "Content-type: image/gif\r\n\r\n" +http_content_type_jpg "Content-type: image/jpeg\r\n\r\n" +http_content_type_binary "Content-type: application/octet-stream\r\n\r\n" +http_html ".html" +http_shtml ".shtml" +http_htm ".htm" +http_css ".css" +http_png ".png" +http_gif ".gif" +http_jpg ".jpg" +http_text ".txt" +http_txt ".txt" + diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/http-strings.c b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/http-strings.c new file mode 100644 index 000000000..ef7a41c7d --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/http-strings.c @@ -0,0 +1,102 @@ +const char http_http[8] = +/* "http://" */ +{0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, }; +const char http_200[5] = +/* "200 " */ +{0x32, 0x30, 0x30, 0x20, }; +const char http_301[5] = +/* "301 " */ +{0x33, 0x30, 0x31, 0x20, }; +const char http_302[5] = +/* "302 " */ +{0x33, 0x30, 0x32, 0x20, }; +const char http_get[5] = +/* "GET " */ +{0x47, 0x45, 0x54, 0x20, }; +const char http_10[9] = +/* "HTTP/1.0" */ +{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, }; +const char http_11[9] = +/* "HTTP/1.1" */ +{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x31, }; +const char http_content_type[15] = +/* "content-type: " */ +{0x63, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, }; +const char http_texthtml[10] = +/* "text/html" */ +{0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_location[11] = +/* "location: " */ +{0x6c, 0x6f, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, }; +const char http_host[7] = +/* "host: " */ +{0x68, 0x6f, 0x73, 0x74, 0x3a, 0x20, }; +const char http_crnl[3] = +/* "\r\n" */ +{0xd, 0xa, }; +const char http_index_html[12] = +/* "/index.html" */ +{0x2f, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_404_html[10] = +/* "/404.html" */ +{0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_referer[9] = +/* "Referer:" */ +{0x52, 0x65, 0x66, 0x65, 0x72, 0x65, 0x72, 0x3a, }; +const char http_header_200[84] = +/* "HTTP/1.0 200 OK\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */ +{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x32, 0x30, 0x30, 0x20, 0x4f, 0x4b, 0xd, 0xa, 0x53, 0x65, 0x72, 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x73, 0x69, 0x63, 0x73, 0x2e, 0x73, 0x65, 0x2f, 0x7e, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, 0x70, 0x2f, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0xd, 0xa, }; +const char http_header_404[91] = +/* "HTTP/1.0 404 Not found\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */ +{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x34, 0x30, 0x34, 0x20, 0x4e, 0x6f, 0x74, 0x20, 0x66, 0x6f, 0x75, 0x6e, 0x64, 0xd, 0xa, 0x53, 0x65, 0x72, 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x73, 0x69, 0x63, 0x73, 0x2e, 0x73, 0x65, 0x2f, 0x7e, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, 0x70, 0x2f, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0xd, 0xa, }; +const char http_content_type_plain[29] = +/* "Content-type: text/plain\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x70, 0x6c, 0x61, 0x69, 0x6e, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_html[28] = +/* "Content-type: text/html\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_css [27] = +/* "Content-type: text/css\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x63, 0x73, 0x73, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_text[28] = +/* "Content-type: text/text\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x74, 0x65, 0x78, 0x74, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_png [28] = +/* "Content-type: image/png\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x70, 0x6e, 0x67, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_gif [28] = +/* "Content-type: image/gif\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x67, 0x69, 0x66, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_jpg [29] = +/* "Content-type: image/jpeg\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x6a, 0x70, 0x65, 0x67, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_binary[43] = +/* "Content-type: application/octet-stream\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x61, 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x2f, 0x6f, 0x63, 0x74, 0x65, 0x74, 0x2d, 0x73, 0x74, 0x72, 0x65, 0x61, 0x6d, 0xd, 0xa, 0xd, 0xa, }; +const char http_html[6] = +/* ".html" */ +{0x2e, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_shtml[7] = +/* ".shtml" */ +{0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_htm[5] = +/* ".htm" */ +{0x2e, 0x68, 0x74, 0x6d, }; +const char http_css[5] = +/* ".css" */ +{0x2e, 0x63, 0x73, 0x73, }; +const char http_png[5] = +/* ".png" */ +{0x2e, 0x70, 0x6e, 0x67, }; +const char http_gif[5] = +/* ".gif" */ +{0x2e, 0x67, 0x69, 0x66, }; +const char http_jpg[5] = +/* ".jpg" */ +{0x2e, 0x6a, 0x70, 0x67, }; +const char http_text[5] = +/* ".txt" */ +{0x2e, 0x74, 0x78, 0x74, }; +const char http_txt[5] = +/* ".txt" */ +{0x2e, 0x74, 0x78, 0x74, }; diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/http-strings.h b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/http-strings.h new file mode 100644 index 000000000..acbe7e17f --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/http-strings.h @@ -0,0 +1,34 @@ +extern const char http_http[8]; +extern const char http_200[5]; +extern const char http_301[5]; +extern const char http_302[5]; +extern const char http_get[5]; +extern const char http_10[9]; +extern const char http_11[9]; +extern const char http_content_type[15]; +extern const char http_texthtml[10]; +extern const char http_location[11]; +extern const char http_host[7]; +extern const char http_crnl[3]; +extern const char http_index_html[12]; +extern const char http_404_html[10]; +extern const char http_referer[9]; +extern const char http_header_200[84]; +extern const char http_header_404[91]; +extern const char http_content_type_plain[29]; +extern const char http_content_type_html[28]; +extern const char http_content_type_css [27]; +extern const char http_content_type_text[28]; +extern const char http_content_type_png [28]; +extern const char http_content_type_gif [28]; +extern const char http_content_type_jpg [29]; +extern const char http_content_type_binary[43]; +extern const char http_html[6]; +extern const char http_shtml[7]; +extern const char http_htm[5]; +extern const char http_css[5]; +extern const char http_png[5]; +extern const char http_gif[5]; +extern const char http_jpg[5]; +extern const char http_text[5]; +extern const char http_txt[5]; diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/httpd-cgi.c b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/httpd-cgi.c new file mode 100644 index 000000000..62795e71c --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/httpd-cgi.c @@ -0,0 +1,276 @@ +/** + * \addtogroup httpd + * @{ + */ + +/** + * \file + * Web server script interface + * \author + * Adam Dunkels + * + */ + +/* + * Copyright (c) 2001-2006, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: httpd-cgi.c,v 1.2 2006/06/11 21:46:37 adam Exp $ + * + */ + +#include "uip.h" +#include "psock.h" +#include "httpd.h" +#include "httpd-cgi.h" +#include "httpd-fs.h" + +#include +#include + +HTTPD_CGI_CALL(file, "file-stats", file_stats); +HTTPD_CGI_CALL(tcp, "tcp-connections", tcp_stats); +HTTPD_CGI_CALL(net, "net-stats", net_stats); +HTTPD_CGI_CALL(rtos, "rtos-stats", rtos_stats ); +HTTPD_CGI_CALL(io, "led-io", led_io ); + + +static const struct httpd_cgi_call *calls[] = { &file, &tcp, &net, &rtos, &io, NULL }; + +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(nullfunction(struct httpd_state *s, char *ptr)) +{ + PSOCK_BEGIN(&s->sout); + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +httpd_cgifunction +httpd_cgi(char *name) +{ + const struct httpd_cgi_call **f; + + /* Find the matching name in the table, return the function. */ + for(f = calls; *f != NULL; ++f) { + if(strncmp((*f)->name, name, strlen((*f)->name)) == 0) { + return (*f)->function; + } + } + return nullfunction; +} +/*---------------------------------------------------------------------------*/ +static unsigned short +generate_file_stats(void *arg) +{ + char *f = (char *)arg; + return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, "%5u", httpd_fs_count(f)); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(file_stats(struct httpd_state *s, char *ptr)) +{ + PSOCK_BEGIN(&s->sout); + + PSOCK_GENERATOR_SEND(&s->sout, generate_file_stats, strchr(ptr, ' ') + 1); + + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +static const char closed[] = /* "CLOSED",*/ +{0x43, 0x4c, 0x4f, 0x53, 0x45, 0x44, 0}; +static const char syn_rcvd[] = /* "SYN-RCVD",*/ +{0x53, 0x59, 0x4e, 0x2d, 0x52, 0x43, 0x56, + 0x44, 0}; +static const char syn_sent[] = /* "SYN-SENT",*/ +{0x53, 0x59, 0x4e, 0x2d, 0x53, 0x45, 0x4e, + 0x54, 0}; +static const char established[] = /* "ESTABLISHED",*/ +{0x45, 0x53, 0x54, 0x41, 0x42, 0x4c, 0x49, 0x53, 0x48, + 0x45, 0x44, 0}; +static const char fin_wait_1[] = /* "FIN-WAIT-1",*/ +{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49, + 0x54, 0x2d, 0x31, 0}; +static const char fin_wait_2[] = /* "FIN-WAIT-2",*/ +{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49, + 0x54, 0x2d, 0x32, 0}; +static const char closing[] = /* "CLOSING",*/ +{0x43, 0x4c, 0x4f, 0x53, 0x49, + 0x4e, 0x47, 0}; +static const char time_wait[] = /* "TIME-WAIT,"*/ +{0x54, 0x49, 0x4d, 0x45, 0x2d, 0x57, 0x41, + 0x49, 0x54, 0}; +static const char last_ack[] = /* "LAST-ACK"*/ +{0x4c, 0x41, 0x53, 0x54, 0x2d, 0x41, 0x43, + 0x4b, 0}; + +static const char *states[] = { + closed, + syn_rcvd, + syn_sent, + established, + fin_wait_1, + fin_wait_2, + closing, + time_wait, + last_ack}; + + +static unsigned short +generate_tcp_stats(void *arg) +{ + struct uip_conn *conn; + struct httpd_state *s = (struct httpd_state *)arg; + + conn = &uip_conns[s->count]; + return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, + "\r\n", + htons(conn->lport), + htons(conn->ripaddr[0]) >> 8, + htons(conn->ripaddr[0]) & 0xff, + htons(conn->ripaddr[1]) >> 8, + htons(conn->ripaddr[1]) & 0xff, + htons(conn->rport), + states[conn->tcpstateflags & UIP_TS_MASK], + conn->nrtx, + conn->timer, + (uip_outstanding(conn))? '*':' ', + (uip_stopped(conn))? '!':' '); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(tcp_stats(struct httpd_state *s, char *ptr)) +{ + + PSOCK_BEGIN(&s->sout); + + for(s->count = 0; s->count < UIP_CONNS; ++s->count) { + if((uip_conns[s->count].tcpstateflags & UIP_TS_MASK) != UIP_CLOSED) { + PSOCK_GENERATOR_SEND(&s->sout, generate_tcp_stats, s); + } + } + + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +static unsigned short +generate_net_stats(void *arg) +{ + struct httpd_state *s = (struct httpd_state *)arg; + return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, + "%5u\n", ((uip_stats_t *)&uip_stat)[s->count]); +} + +static +PT_THREAD(net_stats(struct httpd_state *s, char *ptr)) +{ + PSOCK_BEGIN(&s->sout); + +#if UIP_STATISTICS + + for(s->count = 0; s->count < sizeof(uip_stat) / sizeof(uip_stats_t); + ++s->count) { + PSOCK_GENERATOR_SEND(&s->sout, generate_net_stats, s); + } + +#endif /* UIP_STATISTICS */ + + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ + +extern void vTaskList( signed char *pcWriteBuffer ); +static char cCountBuf[ 32 ]; +long lRefreshCount = 0; +static unsigned short +generate_rtos_stats(void *arg) +{ + lRefreshCount++; + sprintf( cCountBuf, "


Refresh count = %ld", lRefreshCount ); + vTaskList( uip_appdata ); + strcat( uip_appdata, cCountBuf ); + + return strlen( uip_appdata ); +} +/*---------------------------------------------------------------------------*/ + + +static +PT_THREAD(rtos_stats(struct httpd_state *s, char *ptr)) +{ + PSOCK_BEGIN(&s->sout); + PSOCK_GENERATOR_SEND(&s->sout, generate_rtos_stats, NULL); + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ + +char *pcStatus[ 3 ]; +unsigned long ulString; +extern unsigned long uxParTextGetLED( unsigned long uxLED ); + +static unsigned short generate_io_state( void *arg ) +{ + for( ulString = 0; ulString < 4; ulString++ ) + { + if( uxParTextGetLED( ulString + 5 ) ) + { + pcStatus[ ulString ] = "checked"; + } + else + { + pcStatus[ ulString ] = ""; + } + } + + sprintf( uip_appdata, + "LED 2.5,"\ + "LED 2.6,"\ + "LED 2.7"\ + "

"\ + "", + pcStatus[ 0 ], + pcStatus[ 1 ], + pcStatus[ 2 ] ); + + return strlen( uip_appdata ); +} + +static PT_THREAD(led_io(struct httpd_state *s, char *ptr)) +{ + PSOCK_BEGIN(&s->sout); + PSOCK_GENERATOR_SEND(&s->sout, generate_io_state, NULL); + PSOCK_END(&s->sout); +} + +/** @} */ + + + + + + diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/httpd-cgi.h b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/httpd-cgi.h new file mode 100644 index 000000000..7ae928321 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/httpd-cgi.h @@ -0,0 +1,84 @@ +/** + * \addtogroup httpd + * @{ + */ + +/** + * \file + * Web server script interface header file + * \author + * Adam Dunkels + * + */ + + + +/* + * Copyright (c) 2001, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: httpd-cgi.h,v 1.2 2006/06/11 21:46:38 adam Exp $ + * + */ + +#ifndef __HTTPD_CGI_H__ +#define __HTTPD_CGI_H__ + +#include "psock.h" +#include "httpd.h" + +typedef PT_THREAD((* httpd_cgifunction)(struct httpd_state *, char *)); + +httpd_cgifunction httpd_cgi(char *name); + +struct httpd_cgi_call { + const char *name; + const httpd_cgifunction function; +}; + +/** + * \brief HTTPD CGI function declaration + * \param name The C variable name of the function + * \param str The string name of the function, used in the script file + * \param function A pointer to the function that implements it + * + * This macro is used for declaring a HTTPD CGI + * function. This function is then added to the list of + * HTTPD CGI functions with the httpd_cgi_add() function. + * + * \hideinitializer + */ +#define HTTPD_CGI_CALL(name, str, function) \ +static PT_THREAD(function(struct httpd_state *, char *)); \ +static const struct httpd_cgi_call name = {str, function} + +void httpd_cgi_init(void); +#endif /* __HTTPD_CGI_H__ */ + +/** @} */ diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/httpd-fs.c b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/httpd-fs.c new file mode 100644 index 000000000..dc4aef011 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/httpd-fs.c @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: httpd-fs.c,v 1.1 2006/06/07 09:13:08 adam Exp $ + */ + +#include "httpd.h" +#include "httpd-fs.h" +#include "httpd-fsdata.h" + +#ifndef NULL +#define NULL 0 +#endif /* NULL */ + +#include "httpd-fsdata.c" + +#if HTTPD_FS_STATISTICS +static u16_t count[HTTPD_FS_NUMFILES]; +#endif /* HTTPD_FS_STATISTICS */ + +/*-----------------------------------------------------------------------------------*/ +static u8_t +httpd_fs_strcmp(const char *str1, const char *str2) +{ + u8_t i; + i = 0; + loop: + + if(str2[i] == 0 || + str1[i] == '\r' || + str1[i] == '\n') { + return 0; + } + + if(str1[i] != str2[i]) { + return 1; + } + + + ++i; + goto loop; +} +/*-----------------------------------------------------------------------------------*/ +int +httpd_fs_open(const char *name, struct httpd_fs_file *file) +{ +#if HTTPD_FS_STATISTICS + u16_t i = 0; +#endif /* HTTPD_FS_STATISTICS */ + struct httpd_fsdata_file_noconst *f; + + for(f = (struct httpd_fsdata_file_noconst *)HTTPD_FS_ROOT; + f != NULL; + f = (struct httpd_fsdata_file_noconst *)f->next) { + + if(httpd_fs_strcmp(name, f->name) == 0) { + file->data = f->data; + file->len = f->len; +#if HTTPD_FS_STATISTICS + ++count[i]; +#endif /* HTTPD_FS_STATISTICS */ + return 1; + } +#if HTTPD_FS_STATISTICS + ++i; +#endif /* HTTPD_FS_STATISTICS */ + + } + return 0; +} +/*-----------------------------------------------------------------------------------*/ +void +httpd_fs_init(void) +{ +#if HTTPD_FS_STATISTICS + u16_t i; + for(i = 0; i < HTTPD_FS_NUMFILES; i++) { + count[i] = 0; + } +#endif /* HTTPD_FS_STATISTICS */ +} +/*-----------------------------------------------------------------------------------*/ +#if HTTPD_FS_STATISTICS +u16_t httpd_fs_count +(char *name) +{ + struct httpd_fsdata_file_noconst *f; + u16_t i; + + i = 0; + for(f = (struct httpd_fsdata_file_noconst *)HTTPD_FS_ROOT; + f != NULL; + f = (struct httpd_fsdata_file_noconst *)f->next) { + + if(httpd_fs_strcmp(name, f->name) == 0) { + return count[i]; + } + ++i; + } + return 0; +} +#endif /* HTTPD_FS_STATISTICS */ +/*-----------------------------------------------------------------------------------*/ diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/httpd-fs.h b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/httpd-fs.h new file mode 100644 index 000000000..b594eea56 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/httpd-fs.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: httpd-fs.h,v 1.1 2006/06/07 09:13:08 adam Exp $ + */ +#ifndef __HTTPD_FS_H__ +#define __HTTPD_FS_H__ + +#define HTTPD_FS_STATISTICS 1 + +struct httpd_fs_file { + char *data; + int len; +}; + +/* file must be allocated by caller and will be filled in + by the function. */ +int httpd_fs_open(const char *name, struct httpd_fs_file *file); + +#ifdef HTTPD_FS_STATISTICS +#if HTTPD_FS_STATISTICS == 1 +u16_t httpd_fs_count(char *name); +#endif /* HTTPD_FS_STATISTICS */ +#endif /* HTTPD_FS_STATISTICS */ + +void httpd_fs_init(void); + +#endif /* __HTTPD_FS_H__ */ diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/httpd-fs/404.html b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/httpd-fs/404.html new file mode 100644 index 000000000..43e7f4cad --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/httpd-fs/404.html @@ -0,0 +1,8 @@ + + +

+

404 - file not found

+

Go here instead.

+
+ + \ No newline at end of file diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/httpd-fs/index.html b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/httpd-fs/index.html new file mode 100644 index 000000000..1d3bbeee1 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/httpd-fs/index.html @@ -0,0 +1,13 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +Loading index.shtml. Click here if not automatically redirected. + + + + + diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/httpd-fs/index.shtml b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/httpd-fs/index.shtml new file mode 100644 index 000000000..0ce405ba0 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/httpd-fs/index.shtml @@ -0,0 +1,20 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +RTOS Stats | TCP Stats | Connections | FreeRTOS.org Homepage | IO +

+

+

+

Task statistics

+Page will refresh evey 2 seconds.

+

Task          State  Priority  Stack	#
************************************************

+%! rtos-stats
+
+ + + + diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/httpd-fs/io.shtml b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/httpd-fs/io.shtml new file mode 100644 index 000000000..0ffdbff7c --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/httpd-fs/io.shtml @@ -0,0 +1,28 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +RTOS Stats | TCP Stats | Connections | FreeRTOS.org Homepage | IO +

+

+LED and LCD IO
+ +

+ +Use the check boxes to select the LED's to turn on or off, enter text to display on the LCD, then click "Update IO". + + +

+
+%! led-io +

+ + +

+ + + + diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/httpd-fs/stats.shtml b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/httpd-fs/stats.shtml new file mode 100644 index 000000000..d762f40d8 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/httpd-fs/stats.shtml @@ -0,0 +1,41 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +RTOS Stats | TCP Stats | Connections | FreeRTOS.org Homepage | IO +

+

+

+

Network statistics

+
LocalRemoteStateRetransmissionsTimerFlags
%d%u.%u.%u.%u:%u%s%u%u%c %c
+
+IP           Packets dropped
+             Packets received
+             Packets sent
+IP errors    IP version/header length
+             IP length, high byte
+             IP length, low byte
+             IP fragments
+             Header checksum
+             Wrong protocol
+ICMP	     Packets dropped
+             Packets received
+             Packets sent
+             Type errors
+TCP          Packets dropped
+             Packets received
+             Packets sent
+             Checksum errors
+             Data packets without ACKs
+             Resets
+             Retransmissions
+	     No connection avaliable
+	     Connection attempts to closed ports
+
%! net-stats
+
+ + + diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/httpd-fs/tcp.shtml b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/httpd-fs/tcp.shtml new file mode 100644 index 000000000..654d61f21 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/httpd-fs/tcp.shtml @@ -0,0 +1,21 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +RTOS Stats | TCP Stats | Connections | FreeRTOS.org Homepage | IO +

+

+
+

Network connections

+

+ + +%! tcp-connections + + + + + diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/httpd-fsdata.c b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/httpd-fsdata.c new file mode 100644 index 000000000..e7e29e344 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/httpd-fsdata.c @@ -0,0 +1,470 @@ +static const unsigned char data_404_html[] = { + /* /404.html */ + 0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0, + 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xd, 0xa, 0x20, 0x20, + 0x3c, 0x62, 0x6f, 0x64, 0x79, 0x20, 0x62, 0x67, 0x63, 0x6f, + 0x6c, 0x6f, 0x72, 0x3d, 0x22, 0x77, 0x68, 0x69, 0x74, 0x65, + 0x22, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x3c, 0x63, + 0x65, 0x6e, 0x74, 0x65, 0x72, 0x3e, 0xd, 0xa, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x3c, 0x68, 0x31, 0x3e, 0x34, 0x30, + 0x34, 0x20, 0x2d, 0x20, 0x66, 0x69, 0x6c, 0x65, 0x20, 0x6e, + 0x6f, 0x74, 0x20, 0x66, 0x6f, 0x75, 0x6e, 0x64, 0x3c, 0x2f, + 0x68, 0x31, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x3c, 0x68, 0x33, 0x3e, 0x47, 0x6f, 0x20, 0x3c, 0x61, + 0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, 0x2f, 0x22, 0x3e, + 0x68, 0x65, 0x72, 0x65, 0x3c, 0x2f, 0x61, 0x3e, 0x20, 0x69, + 0x6e, 0x73, 0x74, 0x65, 0x61, 0x64, 0x2e, 0x3c, 0x2f, 0x68, + 0x33, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x3c, 0x2f, + 0x63, 0x65, 0x6e, 0x74, 0x65, 0x72, 0x3e, 0xd, 0xa, 0x20, + 0x20, 0x3c, 0x2f, 0x62, 0x6f, 0x64, 0x79, 0x3e, 0xd, 0xa, + 0x3c, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0}; + +static const unsigned char data_index_html[] = { + /* /index.html */ + 0x2f, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0, + 0x3c, 0x21, 0x44, 0x4f, 0x43, 0x54, 0x59, 0x50, 0x45, 0x20, + 0x48, 0x54, 0x4d, 0x4c, 0x20, 0x50, 0x55, 0x42, 0x4c, 0x49, + 0x43, 0x20, 0x22, 0x2d, 0x2f, 0x2f, 0x57, 0x33, 0x43, 0x2f, + 0x2f, 0x44, 0x54, 0x44, 0x20, 0x48, 0x54, 0x4d, 0x4c, 0x20, + 0x34, 0x2e, 0x30, 0x31, 0x20, 0x54, 0x72, 0x61, 0x6e, 0x73, + 0x69, 0x74, 0x69, 0x6f, 0x6e, 0x61, 0x6c, 0x2f, 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0xa, 0x3c, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x3e, + 0xd, 0xa, 0}; + +static const unsigned char data_tcp_shtml[] = { + /* /tcp.shtml */ + 0x2f, 0x74, 0x63, 0x70, 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0, + 0x3c, 0x21, 0x44, 0x4f, 0x43, 0x54, 0x59, 0x50, 0x45, 0x20, + 0x48, 0x54, 0x4d, 0x4c, 0x20, 0x50, 0x55, 0x42, 0x4c, 0x49, + 0x43, 0x20, 0x22, 0x2d, 0x2f, 0x2f, 0x57, 0x33, 0x43, 0x2f, + 0x2f, 0x44, 0x54, 0x44, 0x20, 0x48, 0x54, 0x4d, 0x4c, 0x20, + 0x34, 0x2e, 0x30, 0x31, 0x20, 0x54, 0x72, 0x61, 0x6e, 0x73, + 0x69, 0x74, 0x69, 0x6f, 0x6e, 0x61, 0x6c, 0x2f, 0x2f, 0x45, + 0x4e, 0x22, 0x20, 0x22, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, + 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x77, 0x33, 0x2e, 0x6f, 0x72, + 0x67, 0x2f, 0x54, 0x52, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x34, + 0x2f, 0x6c, 0x6f, 0x6f, 0x73, 0x65, 0x2e, 0x64, 0x74, 0x64, + 0x22, 0x3e, 0xd, 0xa, 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, + 0xd, 0xa, 0x20, 0x20, 0x3c, 0x68, 0x65, 0x61, 0x64, 0x3e, + 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x3c, 0x74, 0x69, 0x74, + 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0x73, 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, + 0x49, 0x4f, 0x3c, 0x2f, 0x61, 0x3e, 0xd, 0xa, 0x3c, 0x62, + 0x72, 0x3e, 0x3c, 0x70, 0x3e, 0xd, 0xa, 0x3c, 0x68, 0x72, + 0x3e, 0xd, 0xa, 0x3c, 0x62, 0x72, 0x3e, 0xd, 0xa, 0x3c, + 0x68, 0x32, 0x3e, 0x4e, 0x65, 0x74, 0x77, 0x6f, 0x72, 0x6b, + 0x20, 0x63, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, + 0x6e, 0x73, 0x3c, 0x2f, 0x68, 0x32, 0x3e, 0xd, 0xa, 0x3c, + 0x70, 0x3e, 0xd, 0xa, 0x3c, 0x74, 0x61, 0x62, 0x6c, 0x65, + 0x3e, 0xd, 0xa, 0x3c, 0x74, 0x72, 0x3e, 0x3c, 0x74, 0x68, + 0x3e, 0x4c, 0x6f, 0x63, 0x61, 0x6c, 0x3c, 0x2f, 0x74, 0x68, + 0x3e, 0x3c, 0x74, 0x68, 0x3e, 0x52, 0x65, 0x6d, 0x6f, 0x74, + 0x65, 0x3c, 0x2f, 0x74, 0x68, 0x3e, 0x3c, 0x74, 0x68, 0x3e, + 0x53, 0x74, 0x61, 0x74, 0x65, 0x3c, 0x2f, 0x74, 0x68, 0x3e, + 0x3c, 0x74, 0x68, 0x3e, 0x52, 0x65, 0x74, 0x72, 0x61, 0x6e, + 0x73, 0x6d, 0x69, 0x73, 0x73, 0x69, 0x6f, 0x6e, 0x73, 0x3c, + 0x2f, 0x74, 0x68, 0x3e, 0x3c, 0x74, 0x68, 0x3e, 0x54, 0x69, + 0x6d, 0x65, 0x72, 0x3c, 0x2f, 0x74, 0x68, 0x3e, 0x3c, 0x74, + 0x68, 0x3e, 0x46, 0x6c, 0x61, 0x67, 0x73, 0x3c, 0x2f, 0x74, + 0x68, 0x3e, 0x3c, 0x2f, 0x74, 0x72, 0x3e, 0xd, 0xa, 0x25, + 0x21, 0x20, 0x74, 0x63, 0x70, 0x2d, 0x63, 0x6f, 0x6e, 0x6e, + 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x73, 0xd, 0xa, 0x3c, + 0x2f, 0x70, 0x72, 0x65, 0x3e, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, + 0x74, 0x3e, 0xd, 0xa, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, 0x74, + 0x3e, 0xd, 0xa, 0x3c, 0x2f, 0x62, 0x6f, 0x64, 0x79, 0x3e, + 0xd, 0xa, 0x3c, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xd, + 0xa, 0xd, 0xa, 0}; + +const struct httpd_fsdata_file file_404_html[] = {{NULL, data_404_html, data_404_html + 10, sizeof(data_404_html) - 10}}; + +const struct httpd_fsdata_file file_index_html[] = {{file_404_html, data_index_html, data_index_html + 12, sizeof(data_index_html) - 12}}; + +const struct httpd_fsdata_file file_index_shtml[] = {{file_index_html, data_index_shtml, data_index_shtml + 13, sizeof(data_index_shtml) - 13}}; + +const struct httpd_fsdata_file file_io_shtml[] = {{file_index_shtml, data_io_shtml, data_io_shtml + 10, sizeof(data_io_shtml) - 10}}; + +const struct httpd_fsdata_file file_stats_shtml[] = {{file_io_shtml, data_stats_shtml, data_stats_shtml + 13, sizeof(data_stats_shtml) - 13}}; + +const struct httpd_fsdata_file file_tcp_shtml[] = {{file_stats_shtml, data_tcp_shtml, data_tcp_shtml + 11, sizeof(data_tcp_shtml) - 11}}; + +#define HTTPD_FS_ROOT file_tcp_shtml + +#define HTTPD_FS_NUMFILES 6 diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/httpd-fsdata.h b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/httpd-fsdata.h new file mode 100644 index 000000000..52d35c265 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/httpd-fsdata.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: httpd-fsdata.h,v 1.1 2006/06/07 09:13:08 adam Exp $ + */ +#ifndef __HTTPD_FSDATA_H__ +#define __HTTPD_FSDATA_H__ + +#include "uip.h" + +struct httpd_fsdata_file { + const struct httpd_fsdata_file *next; + const char *name; + const char *data; + const int len; +#ifdef HTTPD_FS_STATISTICS +#if HTTPD_FS_STATISTICS == 1 + u16_t count; +#endif /* HTTPD_FS_STATISTICS */ +#endif /* HTTPD_FS_STATISTICS */ +}; + +struct httpd_fsdata_file_noconst { + struct httpd_fsdata_file *next; + char *name; + char *data; + int len; +#ifdef HTTPD_FS_STATISTICS +#if HTTPD_FS_STATISTICS == 1 + u16_t count; +#endif /* HTTPD_FS_STATISTICS */ +#endif /* HTTPD_FS_STATISTICS */ +}; + +#endif /* __HTTPD_FSDATA_H__ */ diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/httpd.c b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/httpd.c new file mode 100644 index 000000000..644cf16b7 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/httpd.c @@ -0,0 +1,346 @@ +/** + * \addtogroup apps + * @{ + */ + +/** + * \defgroup httpd Web server + * @{ + * The uIP web server is a very simplistic implementation of an HTTP + * server. It can serve web pages and files from a read-only ROM + * filesystem, and provides a very small scripting language. + + */ + +/** + * \file + * Web server + * \author + * Adam Dunkels + */ + + +/* + * Copyright (c) 2004, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: httpd.c,v 1.2 2006/06/11 21:46:38 adam Exp $ + */ + +#include "uip.h" +#include "httpd.h" +#include "httpd-fs.h" +#include "httpd-cgi.h" +#include "http-strings.h" + +#include + +#define STATE_WAITING 0 +#define STATE_OUTPUT 1 + +#define ISO_nl 0x0a +#define ISO_space 0x20 +#define ISO_bang 0x21 +#define ISO_percent 0x25 +#define ISO_period 0x2e +#define ISO_slash 0x2f +#define ISO_colon 0x3a + + +/*---------------------------------------------------------------------------*/ +static unsigned short +generate_part_of_file(void *state) +{ + struct httpd_state *s = (struct httpd_state *)state; + + if(s->file.len > uip_mss()) { + s->len = uip_mss(); + } else { + s->len = s->file.len; + } + memcpy(uip_appdata, s->file.data, s->len); + + return s->len; +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(send_file(struct httpd_state *s)) +{ + PSOCK_BEGIN(&s->sout); + + do { + PSOCK_GENERATOR_SEND(&s->sout, generate_part_of_file, s); + s->file.len -= s->len; + s->file.data += s->len; + } while(s->file.len > 0); + + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(send_part_of_file(struct httpd_state *s)) +{ + PSOCK_BEGIN(&s->sout); + + PSOCK_SEND(&s->sout, s->file.data, s->len); + + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +static void +next_scriptstate(struct httpd_state *s) +{ + char *p; + p = strchr(s->scriptptr, ISO_nl) + 1; + s->scriptlen -= (unsigned short)(p - s->scriptptr); + s->scriptptr = p; +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(handle_script(struct httpd_state *s)) +{ + char *ptr; + + PT_BEGIN(&s->scriptpt); + + + while(s->file.len > 0) { + + /* Check if we should start executing a script. */ + if(*s->file.data == ISO_percent && + *(s->file.data + 1) == ISO_bang) { + s->scriptptr = s->file.data + 3; + s->scriptlen = s->file.len - 3; + if(*(s->scriptptr - 1) == ISO_colon) { + httpd_fs_open(s->scriptptr + 1, &s->file); + PT_WAIT_THREAD(&s->scriptpt, send_file(s)); + } else { + PT_WAIT_THREAD(&s->scriptpt, + httpd_cgi(s->scriptptr)(s, s->scriptptr)); + } + next_scriptstate(s); + + /* The script is over, so we reset the pointers and continue + sending the rest of the file. */ + s->file.data = s->scriptptr; + s->file.len = s->scriptlen; + } else { + /* See if we find the start of script marker in the block of HTML + to be sent. */ + + if(s->file.len > uip_mss()) { + s->len = uip_mss(); + } else { + s->len = s->file.len; + } + + if(*s->file.data == ISO_percent) { + ptr = strchr(s->file.data + 1, ISO_percent); + } else { + ptr = strchr(s->file.data, ISO_percent); + } + if(ptr != NULL && + ptr != s->file.data) { + s->len = (int)(ptr - s->file.data); + if(s->len >= uip_mss()) { + s->len = uip_mss(); + } + } + PT_WAIT_THREAD(&s->scriptpt, send_part_of_file(s)); + s->file.data += s->len; + s->file.len -= s->len; + + } + } + + PT_END(&s->scriptpt); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(send_headers(struct httpd_state *s, const char *statushdr)) +{ + char *ptr; + + PSOCK_BEGIN(&s->sout); + + PSOCK_SEND_STR(&s->sout, statushdr); + + ptr = strrchr(s->filename, ISO_period); + if(ptr == NULL) { + PSOCK_SEND_STR(&s->sout, http_content_type_binary); + } else if(strncmp(http_html, ptr, 5) == 0 || + strncmp(http_shtml, ptr, 6) == 0) { + PSOCK_SEND_STR(&s->sout, http_content_type_html); + } else if(strncmp(http_css, ptr, 4) == 0) { + PSOCK_SEND_STR(&s->sout, http_content_type_css); + } else if(strncmp(http_png, ptr, 4) == 0) { + PSOCK_SEND_STR(&s->sout, http_content_type_png); + } else if(strncmp(http_gif, ptr, 4) == 0) { + PSOCK_SEND_STR(&s->sout, http_content_type_gif); + } else if(strncmp(http_jpg, ptr, 4) == 0) { + PSOCK_SEND_STR(&s->sout, http_content_type_jpg); + } else { + PSOCK_SEND_STR(&s->sout, http_content_type_plain); + } + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(handle_output(struct httpd_state *s)) +{ + char *ptr; + + PT_BEGIN(&s->outputpt); + + if(!httpd_fs_open(s->filename, &s->file)) { + httpd_fs_open(http_404_html, &s->file); + strcpy(s->filename, http_404_html); + PT_WAIT_THREAD(&s->outputpt, + send_headers(s, + http_header_404)); + PT_WAIT_THREAD(&s->outputpt, + send_file(s)); + } else { + PT_WAIT_THREAD(&s->outputpt, + send_headers(s, + http_header_200)); + ptr = strchr(s->filename, ISO_period); + if(ptr != NULL && strncmp(ptr, http_shtml, 6) == 0) { + PT_INIT(&s->scriptpt); + PT_WAIT_THREAD(&s->outputpt, handle_script(s)); + } else { + PT_WAIT_THREAD(&s->outputpt, + send_file(s)); + } + } + PSOCK_CLOSE(&s->sout); + PT_END(&s->outputpt); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(handle_input(struct httpd_state *s)) +{ + PSOCK_BEGIN(&s->sin); + + PSOCK_READTO(&s->sin, ISO_space); + + + if(strncmp(s->inputbuf, http_get, 4) != 0) { + PSOCK_CLOSE_EXIT(&s->sin); + } + PSOCK_READTO(&s->sin, ISO_space); + + if(s->inputbuf[0] != ISO_slash) { + PSOCK_CLOSE_EXIT(&s->sin); + } + + if(s->inputbuf[1] == ISO_space) { + strncpy(s->filename, http_index_html, sizeof(s->filename)); + } else { + + s->inputbuf[PSOCK_DATALEN(&s->sin) - 1] = 0; + + /* Process any form input being sent to the server. */ + { + extern void vApplicationProcessFormInput( char *pcInputString, long xInputLength ); + vApplicationProcessFormInput( s->inputbuf, PSOCK_DATALEN(&s->sin) ); + } + + strncpy(s->filename, &s->inputbuf[0], sizeof(s->filename)); + } + + /* httpd_log_file(uip_conn->ripaddr, s->filename);*/ + + s->state = STATE_OUTPUT; + + while(1) { + PSOCK_READTO(&s->sin, ISO_nl); + + if(strncmp(s->inputbuf, http_referer, 8) == 0) { + s->inputbuf[PSOCK_DATALEN(&s->sin) - 2] = 0; + /* httpd_log(&s->inputbuf[9]);*/ + } + } + + PSOCK_END(&s->sin); +} +/*---------------------------------------------------------------------------*/ +static void +handle_connection(struct httpd_state *s) +{ + handle_input(s); + if(s->state == STATE_OUTPUT) { + handle_output(s); + } +} +/*---------------------------------------------------------------------------*/ +void +httpd_appcall(void) +{ + struct httpd_state *s = (struct httpd_state *)&(uip_conn->appstate); + + if(uip_closed() || uip_aborted() || uip_timedout()) { + } else if(uip_connected()) { + PSOCK_INIT(&s->sin, s->inputbuf, sizeof(s->inputbuf) - 1); + PSOCK_INIT(&s->sout, s->inputbuf, sizeof(s->inputbuf) - 1); + PT_INIT(&s->outputpt); + s->state = STATE_WAITING; + /* timer_set(&s->timer, CLOCK_SECOND * 100);*/ + s->timer = 0; + handle_connection(s); + } else if(s != NULL) { + if(uip_poll()) { + ++s->timer; + if(s->timer >= 20) { + uip_abort(); + } + } else { + s->timer = 0; + } + handle_connection(s); + } else { + uip_abort(); + } +} +/*---------------------------------------------------------------------------*/ +/** + * \brief Initialize the web server + * + * This function initializes the web server and should be + * called at system boot-up. + */ +void +httpd_init(void) +{ + uip_listen(HTONS(80)); +} +/*---------------------------------------------------------------------------*/ +/** @} */ diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/httpd.h b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/httpd.h new file mode 100644 index 000000000..7f7a6666e --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/httpd.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2001-2005, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: httpd.h,v 1.2 2006/06/11 21:46:38 adam Exp $ + * + */ + +#ifndef __HTTPD_H__ +#define __HTTPD_H__ + +#include "psock.h" +#include "httpd-fs.h" + +struct httpd_state { + unsigned char timer; + struct psock sin, sout; + struct pt outputpt, scriptpt; + char inputbuf[50]; + char filename[20]; + char state; + struct httpd_fs_file file; + int len; + char *scriptptr; + int scriptlen; + + unsigned short count; +}; + +void httpd_init(void); +void httpd_appcall(void); + +void httpd_log(char *msg); +void httpd_log_file(u16_t *requester, char *file); + +#endif /* __HTTPD_H__ */ diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/makefsdata b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/makefsdata new file mode 100644 index 000000000..8d2715a8a --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/makefsdata @@ -0,0 +1,78 @@ +#!/usr/bin/perl + +open(OUTPUT, "> httpd-fsdata.c"); + +chdir("httpd-fs"); + +opendir(DIR, "."); +@files = grep { !/^\./ && !/(CVS|~)/ } readdir(DIR); +closedir(DIR); + +foreach $file (@files) { + + if(-d $file && $file !~ /^\./) { + print "Processing directory $file\n"; + opendir(DIR, $file); + @newfiles = grep { !/^\./ && !/(CVS|~)/ } readdir(DIR); + closedir(DIR); + printf "Adding files @newfiles\n"; + @files = (@files, map { $_ = "$file/$_" } @newfiles); + next; + } +} + +foreach $file (@files) { + if(-f $file) { + + print "Adding file $file\n"; + + open(FILE, $file) || die "Could not open file $file\n"; + + $file =~ s-^-/-; + $fvar = $file; + $fvar =~ s-/-_-g; + $fvar =~ s-\.-_-g; + # for AVR, add PROGMEM here + print(OUTPUT "static const unsigned char data".$fvar."[] = {\n"); + print(OUTPUT "\t/* $file */\n\t"); + for($j = 0; $j < length($file); $j++) { + printf(OUTPUT "%#02x, ", unpack("C", substr($file, $j, 1))); + } + printf(OUTPUT "0,\n"); + + + $i = 0; + while(read(FILE, $data, 1)) { + if($i == 0) { + print(OUTPUT "\t"); + } + printf(OUTPUT "%#02x, ", unpack("C", $data)); + $i++; + if($i == 10) { + print(OUTPUT "\n"); + $i = 0; + } + } + print(OUTPUT "0};\n\n"); + close(FILE); + push(@fvars, $fvar); + push(@pfiles, $file); + } +} + +for($i = 0; $i < @fvars; $i++) { + $file = $pfiles[$i]; + $fvar = $fvars[$i]; + + if($i == 0) { + $prevfile = "NULL"; + } else { + $prevfile = "file" . $fvars[$i - 1]; + } + print(OUTPUT "const struct httpd_fsdata_file file".$fvar."[] = {{$prevfile, data$fvar, "); + print(OUTPUT "data$fvar + ". (length($file) + 1) .", "); + print(OUTPUT "sizeof(data$fvar) - ". (length($file) + 1) ."}};\n\n"); +} + +print(OUTPUT "#define HTTPD_FS_ROOT file$fvars[$i - 1]\n\n"); +print(OUTPUT "#define HTTPD_FS_NUMFILES $i\n"); diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/makestrings b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/makestrings new file mode 100644 index 000000000..8a13c6d29 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/makestrings @@ -0,0 +1,40 @@ +#!/usr/bin/perl + + +sub stringify { + my $name = shift(@_); + open(OUTPUTC, "> $name.c"); + open(OUTPUTH, "> $name.h"); + + open(FILE, "$name"); + + while() { + if(/(.+) "(.+)"/) { + $var = $1; + $data = $2; + + $datan = $data; + $datan =~ s/\\r/\r/g; + $datan =~ s/\\n/\n/g; + $datan =~ s/\\01/\01/g; + $datan =~ s/\\0/\0/g; + + printf(OUTPUTC "const char $var\[%d] = \n", length($datan) + 1); + printf(OUTPUTC "/* \"$data\" */\n"); + printf(OUTPUTC "{"); + for($j = 0; $j < length($datan); $j++) { + printf(OUTPUTC "%#02x, ", unpack("C", substr($datan, $j, 1))); + } + printf(OUTPUTC "};\n"); + + printf(OUTPUTH "extern const char $var\[%d];\n", length($datan) + 1); + + } + } + close(OUTPUTC); + close(OUTPUTH); +} +stringify("http-strings"); + +exit 0; + diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/uIP_Task.c b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/uIP_Task.c new file mode 100644 index 000000000..8fdea019c --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/uIP_Task.c @@ -0,0 +1,318 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* uip includes. */ +#include "uip.h" +#include "uip_arp.h" +#include "httpd.h" +#include "timer.h" +#include "clock-arch.h" + +/* Demo includes. */ +#include "emac.h" +#include "partest.h" + +/*-----------------------------------------------------------*/ + +/* MAC address configuration. */ +#define uipMAC_ADDR0 0x00 +#define uipMAC_ADDR1 0x12 +#define uipMAC_ADDR2 0x13 +#define uipMAC_ADDR3 0x10 +#define uipMAC_ADDR4 0x15 +#define uipMAC_ADDR5 0x11 + +/* IP address configuration. */ +#define uipIP_ADDR0 172 +#define uipIP_ADDR1 25 +#define uipIP_ADDR2 218 +#define uipIP_ADDR3 16 + +/* How long to wait before attempting to connect the MAC again. */ +#define uipINIT_WAIT 100 + +/* Shortcut to the header within the Rx buffer. */ +#define xHeader ((struct uip_eth_hdr *) &uip_buf[ 0 ]) + +/* Standard constant. */ +#define uipTOTAL_FRAME_HEADER_SIZE 54 + +/*-----------------------------------------------------------*/ + +/* + * Send the uIP buffer to the MAC. + */ +static void prvENET_Send(void); + +/* + * Setup the MAC address in the MAC itself, and in the uIP stack. + */ +static void prvSetMACAddress( void ); + +/* + * Port functions required by the uIP stack. + */ +void clock_init( void ); +clock_time_t clock_time( void ); + +/*-----------------------------------------------------------*/ + +/* The semaphore used by the ISR to wake the uIP task. */ +extern xSemaphoreHandle xEMACSemaphore; + +/*-----------------------------------------------------------*/ + +void clock_init(void) +{ + /* This is done when the scheduler starts. */ +} +/*-----------------------------------------------------------*/ + +clock_time_t clock_time( void ) +{ + return xTaskGetTickCount(); +} +/*-----------------------------------------------------------*/ + +void vuIP_Task( void *pvParameters ) +{ +portBASE_TYPE i; +uip_ipaddr_t xIPAddr; +struct timer periodic_timer, arp_timer; +extern void ( vEMAC_ISR_Wrapper )( void ); + + /* Create the semaphore used by the ISR to wake this task. */ + vSemaphoreCreateBinary( xEMACSemaphore ); + + /* Initialise the uIP stack. */ + timer_set( &periodic_timer, configTICK_RATE_HZ / 2 ); + timer_set( &arp_timer, configTICK_RATE_HZ * 10 ); + uip_init(); + uip_ipaddr( xIPAddr, uipIP_ADDR0, uipIP_ADDR1, uipIP_ADDR2, uipIP_ADDR3 ); + uip_sethostaddr( xIPAddr ); + httpd_init(); + + /* Initialise the MAC. */ + while( Init_EMAC() != pdPASS ) + { + vTaskDelay( uipINIT_WAIT ); + } + + portENTER_CRITICAL(); + { + MAC_INTENABLE = INT_RX_DONE; + VICIntEnable |= 0x00200000; + VICVectAddr21 = ( portLONG ) vEMAC_ISR_Wrapper; + prvSetMACAddress(); + } + portEXIT_CRITICAL(); + + + for( ;; ) + { + /* Is there received data ready to be processed? */ + uip_len = uiGetEMACRxData( uip_buf ); + + if( uip_len > 0 ) + { + /* Standard uIP loop taken from the uIP manual. */ + if( xHeader->type == htons( UIP_ETHTYPE_IP ) ) + { + uip_arp_ipin(); + uip_input(); + + /* If the above function invocation resulted in data that + should be sent out on the network, the global variable + uip_len is set to a value > 0. */ + if( uip_len > 0 ) + { + uip_arp_out(); + prvENET_Send(); + } + } + else if( xHeader->type == htons( UIP_ETHTYPE_ARP ) ) + { + uip_arp_arpin(); + + /* If the above function invocation resulted in data that + should be sent out on the network, the global variable + uip_len is set to a value > 0. */ + if( uip_len > 0 ) + { + prvENET_Send(); + } + } + } + else + { + if( timer_expired( &periodic_timer ) ) + { + timer_reset( &periodic_timer ); + for( i = 0; i < UIP_CONNS; i++ ) + { + uip_periodic( i ); + + /* If the above function invocation resulted in data that + should be sent out on the network, the global variable + uip_len is set to a value > 0. */ + if( uip_len > 0 ) + { + uip_arp_out(); + prvENET_Send(); + } + } + + /* Call the ARP timer function every 10 seconds. */ + if( timer_expired( &arp_timer ) ) + { + timer_reset( &arp_timer ); + uip_arp_timer(); + } + } + else + { + /* We did not receive a packet, and there was no periodic + processing to perform. Block for a fixed period. If a packet + is received during this period we will be woken by the ISR + giving us the Semaphore. */ + xSemaphoreTake( xEMACSemaphore, configTICK_RATE_HZ / 2 ); + } + } + } +} +/*-----------------------------------------------------------*/ + +static void prvENET_Send(void) +{ + RequestSend(); + + /* Copy the header into the Tx buffer. */ + CopyToFrame_EMAC( uip_buf, uipTOTAL_FRAME_HEADER_SIZE ); + if( uip_len > uipTOTAL_FRAME_HEADER_SIZE ) + { + CopyToFrame_EMAC( uip_appdata, ( uip_len - uipTOTAL_FRAME_HEADER_SIZE ) ); + } + + DoSend_EMAC( uip_len ); +} +/*-----------------------------------------------------------*/ + +static void prvSetMACAddress( void ) +{ +struct uip_eth_addr xAddr; + + /* Configure the MAC address in the uIP stack. */ + xAddr.addr[ 0 ] = uipMAC_ADDR0; + xAddr.addr[ 1 ] = uipMAC_ADDR1; + xAddr.addr[ 2 ] = uipMAC_ADDR2; + xAddr.addr[ 3 ] = uipMAC_ADDR3; + xAddr.addr[ 4 ] = uipMAC_ADDR4; + xAddr.addr[ 5 ] = uipMAC_ADDR5; + uip_setethaddr( xAddr ); +} +/*-----------------------------------------------------------*/ + +void vApplicationProcessFormInput( portCHAR *pcInputString, portBASE_TYPE xInputLength ) +{ +char *c, *pcText; +static portCHAR cMessageForDisplay[ 32 ]; +extern xQueueHandle xLCDQueue; +xLCDMessage xLCDMessage; + + /* Process the form input sent by the IO page of the served HTML. */ + + c = strstr( pcInputString, "?" ); + if( c ) + { + /* Turn LED's on or off in accordance with the check box status. */ + if( strstr( c, "LED0=1" ) != NULL ) + { + vParTestSetLED( 5, 0 ); + } + else + { + vParTestSetLED( 5, 1 ); + } + + if( strstr( c, "LED1=1" ) != NULL ) + { + vParTestSetLED( 6, 0 ); + } + else + { + vParTestSetLED( 6, 1 ); + } + + if( strstr( c, "LED2=1" ) != NULL ) + { + vParTestSetLED( 7, 0 ); + } + else + { + vParTestSetLED( 7, 1 ); + } + + /* Find the start of the text to be displayed on the LCD. */ + pcText = strstr( c, "LCD=" ); + pcText += strlen( "LCD=" ); + + /* Terminate the file name for further processing within uIP. */ + *c = 0x00; + + /* Terminate the LCD string. */ + c = strstr( pcText, " " ); + if( c != NULL ) + { + *c = 0x00; + } + + /* Add required spaces. */ + while( ( c = strstr( pcText, "+" ) ) != NULL ) + { + *c = ' '; + } + + /* Write the message to the LCD. */ + strcpy( cMessageForDisplay, pcText ); + xLCDMessage.xColumn = 0; + xLCDMessage.pcMessage = cMessageForDisplay; + xQueueSend( xLCDQueue, &xLCDMessage, portMAX_DELAY ); + } +} + diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/uip-conf.h b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/uip-conf.h new file mode 100644 index 000000000..3e6f7f381 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/uip-conf.h @@ -0,0 +1,157 @@ +/** + * \addtogroup uipopt + * @{ + */ + +/** + * \name Project-specific configuration options + * @{ + * + * uIP has a number of configuration options that can be overridden + * for each project. These are kept in a project-specific uip-conf.h + * file and all configuration names have the prefix UIP_CONF. + */ + +/* + * Copyright (c) 2006, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: uip-conf.h,v 1.6 2006/06/12 08:00:31 adam Exp $ + */ + +/** + * \file + * An example uIP configuration file + * \author + * Adam Dunkels + */ + +#ifndef __UIP_CONF_H__ +#define __UIP_CONF_H__ + +#include + +/** + * 8 bit datatype + * + * This typedef defines the 8-bit type used throughout uIP. + * + * \hideinitializer + */ +typedef uint8_t u8_t; + +/** + * 16 bit datatype + * + * This typedef defines the 16-bit type used throughout uIP. + * + * \hideinitializer + */ +typedef uint16_t u16_t; + +/** + * Statistics datatype + * + * This typedef defines the dataype used for keeping statistics in + * uIP. + * + * \hideinitializer + */ +typedef unsigned short uip_stats_t; + +/** + * Maximum number of TCP connections. + * + * \hideinitializer + */ +#define UIP_CONF_MAX_CONNECTIONS 40 + +/** + * Maximum number of listening TCP ports. + * + * \hideinitializer + */ +#define UIP_CONF_MAX_LISTENPORTS 40 + +/** + * uIP buffer size. + * + * \hideinitializer + */ +#define UIP_CONF_BUFFER_SIZE 1480 + +/** + * CPU byte order. + * + * \hideinitializer + */ +#define UIP_CONF_BYTE_ORDER LITTLE_ENDIAN + +/** + * Logging on or off + * + * \hideinitializer + */ +#define UIP_CONF_LOGGING 0 + +/** + * UDP support on or off + * + * \hideinitializer + */ +#define UIP_CONF_UDP 0 + +/** + * UDP checksums on or off + * + * \hideinitializer + */ +#define UIP_CONF_UDP_CHECKSUMS 1 + +/** + * uIP statistics on or off + * + * \hideinitializer + */ +#define UIP_CONF_STATISTICS 1 + +/* Here we include the header file for the application(s) we use in + our project. */ +/*#include "smtp.h"*/ +/*#include "hello-world.h"*/ +/*#include "telnetd.h"*/ +#include "webserver.h" +/*#include "dhcpc.h"*/ +/*#include "resolv.h"*/ +/*#include "webclient.h"*/ + +#endif /* __UIP_CONF_H__ */ + +/** @} */ +/** @} */ diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/webserver.h b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/webserver.h new file mode 100644 index 000000000..1acb290b8 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/webserver/webserver.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2002, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: webserver.h,v 1.2 2006/06/11 21:46:38 adam Exp $ + * + */ +#ifndef __WEBSERVER_H__ +#define __WEBSERVER_H__ + +#include "httpd.h" + +typedef struct httpd_state uip_tcp_appstate_t; +/* UIP_APPCALL: the name of the application function. This function + must return void and take no arguments (i.e., C type "void + appfunc(void)"). */ +#ifndef UIP_APPCALL +#define UIP_APPCALL httpd_appcall +#endif + + +#endif /* __WEBSERVER_H__ */ diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/lpc2368_flash.cfg b/20080212/Demo/ARM7_LPC2368_Eclipse/lpc2368_flash.cfg new file mode 100644 index 000000000..c45e902a8 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/lpc2368_flash.cfg @@ -0,0 +1,35 @@ +#daemon configuration +telnet_port 4444 +gdb_port 3333 + +#interface +interface parport +parport_port 0x378 +parport_cable wiggler +jtag_speed 2 + +#use combined on interfaces or targets that can't set TRST/SRST separately +reset_config trst_and_srst srst_pulls_trst + +#jtag scan chain +#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) +jtag_device 4 0x1 0xf 0xe + +#target configuration +daemon_startup reset + +#target +#target arm7tdmi +target arm7tdmi little run_and_init 0 arm7tdmi-s_r4 +run_and_halt_time 0 30 + +working_area 0 0x40000000 0x40000 nobackup + +#flash configuration +flash bank lpc2000 0x0 0x80000 0 0 0 lpc2000_v2 12000 calc_checksum +flash bank cfi 0x80000000 0x400000 2 2 0 + +# For more information about the configuration files, take a look at: +# http://openfacts.berlios.de/index-en.phtml?title=Open+On-Chip+Debugger + +target_script 0 reset program.script diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/lpc2xxx_pp.cfg b/20080212/Demo/ARM7_LPC2368_Eclipse/lpc2xxx_pp.cfg new file mode 100644 index 000000000..4c3b0ceb9 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/lpc2xxx_pp.cfg @@ -0,0 +1,33 @@ +#daemon configuration +telnet_port 4444 +gdb_port 3333 + +#interface +interface parport +parport_port 0x378 +parport_cable wiggler +jtag_speed 2 + +#use combined on interfaces or targets that can't set TRST/SRST separately +reset_config trst_and_srst srst_pulls_trst + +#jtag scan chain +#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) +jtag_device 4 0x1 0xf 0xe + +#target configuration +daemon_startup reset + +#target +#target arm7tdmi +target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4 +run_and_halt_time 0 30 + +working_area 0 0x40000000 0x40000 nobackup + +#flash configuration +flash bank lpc2000 0x0 0x80000 0 0 0 lpc2000_v2 12000 calc_checksum +flash bank cfi 0x80000000 0x400000 2 2 0 + +# For more information about the configuration files, take a look at: +# http://openfacts.berlios.de/index-en.phtml?title=Open+On-Chip+Debugger diff --git a/20080212/Demo/ARM7_LPC2368_Eclipse/program.script b/20080212/Demo/ARM7_LPC2368_Eclipse/program.script new file mode 100644 index 000000000..363913c7c --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Eclipse/program.script @@ -0,0 +1,11 @@ +arm7_9 dcc_downloads enable +wait_halt +sleep 10 +poll +flash probe 0 +#flash protect 0 0 26 'off' +flash erase 0 0 26 +flash write 0 ./RTOSDemo/RTOSDemo.bin 0x0 +reset run +sleep 10 +shutdown diff --git a/20080212/Demo/ARM7_LPC2368_Rowley/FreeRTOSConfig.h b/20080212/Demo/ARM7_LPC2368_Rowley/FreeRTOSConfig.h new file mode 100644 index 000000000..41a5f62a4 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Rowley/FreeRTOSConfig.h @@ -0,0 +1,121 @@ +/* + FreeRTOS V4.6.1 - Copyright (C) 2003-2005 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include +#include +#define vPortYieldProcessor swi_handler +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +/* Value to use on old rev '-' devices. */ +//#define configPINSEL2_VALUE 0x50151105 + +/* Value to use on rev 'A' and newer devices. */ +//#define configPINSEL2_VALUE 0x50150105 + +#ifndef configPINSEL2_VALUE + #error Please uncomment one of the two configPINSEL2_VALUE definitions above, depending on the revision of the LPC2000 device being used. +#endif + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 57600000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 120 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 18 * 1024 ) ) +#define configMAX_TASK_NAME_LEN ( 16 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 + + +#endif /* FREERTOS_CONFIG_H */ + + +#ifndef sbi +#define sbi(x,y) x|=(1 << (y)) +#endif + +#ifndef cbi +#define cbi(x,y) x&=~(1 << (y)) +#endif + +#ifndef tstb +#define tstb(x,y) (x & (1 << (y)) ? 1 : 0) +#endif + +#ifndef toggle +#define toggle(x,y) x^=(1 << (y)) +#endif + +#ifndef BIT +#define BIT(x) (1 << (x)) + + +#define VICVectAddr VICAddress +#define VICVectCntl4 VICVectPriority4 +typedef struct +{ + long xColumn; + signed char *pcMessage; +} xLCDMessage; + +#endif diff --git a/20080212/Demo/ARM7_LPC2368_Rowley/LCD/portlcd.c b/20080212/Demo/ARM7_LPC2368_Rowley/LCD/portlcd.c new file mode 100644 index 000000000..77219ffaa --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Rowley/LCD/portlcd.c @@ -0,0 +1,392 @@ +/***************************************************************************** + * + * Project : lwIP Web + * Subproject : + * Name : portlcd.c + * Function : Routines for LCD + * Designer : K. Sterckx + * Creation date : 22/01/2007 + * Compiler : GNU ARM + * Processor : LPC2368 + * Last update : + * Last updated by : + * History : + * based on example code from NXP + * + ************************************************************************ + * + * This code is used to place text on the LCD. + * + ************************************************************************/ + +#include +#include "portlcd.h" +#include "FreeRTOS.h" +#include "Task.h" + +/* Please note, on old MCB2300 board, the LCD_E bit is p1.30, on the new board +it's p1.31, please check the schematic carefully, and change LCD_CTRL and LCD_E +accordingly if you have a different board. */ + +/* LCD IO definitions */ +#define LCD_E 0x80000000 /* Enable control pin */ +#define LCD_RW 0x20000000 /* Read/Write control pin */ +#define LCD_RS 0x10000000 /* Data/Instruction control */ +#define LCD_CTRL 0xB0000000 /* Control lines mask */ +#define LCD_DATA 0x0F000000 /* Data lines mask */ + +/* Local variables */ +static unsigned int lcd_ptr; + +/* 8 user defined characters to be loaded into CGRAM (used for bargraph) */ +static const unsigned char UserFont[8][8] = { + { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 }, + { 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10 }, + { 0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18 }, + { 0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C }, + { 0x1E,0x1E,0x1E,0x1E,0x1E,0x1E,0x1E,0x1E }, + { 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F }, + { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 }, + { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } +}; + +/* Local Function Prototypes */ +static void lcd_write( unsigned int c ); +static void lcd_write_4bit( unsigned int c ); +static unsigned int lcd_read_stat( void ); +static void lcd_write_cmd( unsigned int c ); +static void lcd_write_data( unsigned int d ); +static void lcd_wait_busy( void ); + + +/****************************************************************************** +** Function name: lcd_write_4bit +** +** Descriptions: +** +** parameters: four bits to write +** Returned value: None +** +******************************************************************************/ +static void lcd_write_4bit(unsigned int c) +{ + /* Write a 4-bit command to LCD controller. */ + FIO1DIR |= LCD_DATA | LCD_CTRL; + FIO1CLR = LCD_RW | LCD_DATA; + FIO1SET = (c & 0xF) << 24; + FIO1SET = LCD_E; + vTaskDelay(0); + FIO1CLR = LCD_E; + vTaskDelay(0); + return; +} + +/****************************************************************************** +** Function name: lcd_write +** +** Descriptions: +** +** parameters: word to write +** Returned value: None +** +******************************************************************************/ +static void lcd_write(unsigned int c) +{ + /* Write data/command to LCD controller. */ + lcd_write_4bit (c >> 4); + lcd_write_4bit (c); + return; +} + +/****************************************************************************** +** Function name: lcd_read_stat +** +** Descriptions: +** +** parameters: None +** Returned value: status +** +******************************************************************************/ +static unsigned int lcd_read_stat(void) +{ + /* Read status of LCD controller (ST7066) */ + unsigned int stat; + + FIO1DIR &= ~LCD_DATA; + FIO1CLR = LCD_RS; + FIO1SET = LCD_RW; + vTaskDelay( 0 ); + FIO1SET = LCD_E; + vTaskDelay( 0 ); + stat = (FIO1PIN >> 20) & 0xF0; + FIO1CLR = LCD_E; + vTaskDelay( 0 ); + FIO1SET = LCD_E; + vTaskDelay( 0 ); + stat |= (FIO1PIN >> 24) & 0xF; + FIO1CLR = LCD_E; + return (stat); +} + +/****************************************************************************** +** Function name: lcd_wait_busy +** +** Descriptions: +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +static void lcd_wait_busy(void) +{ + /* Wait until LCD controller (ST7066) is busy. */ + unsigned int stat; + + do + { + stat = lcd_read_stat(); + } + while (stat & 0x80); /* Wait for busy flag */ + + return; +} + +/****************************************************************************** +** Function name: lcd_write_cmd +** +** Descriptions: +** +** parameters: command word +** Returned value: None +** +******************************************************************************/ +static void lcd_write_cmd(unsigned int c) +{ + /* Write command to LCD controller. */ + lcd_wait_busy(); + FIO1CLR = LCD_RS; + lcd_write(c); + return; +} + +/****************************************************************************** +** Function name: lcd_write_data +** +** Descriptions: +** +** parameters: data word +** Returned value: None +** +******************************************************************************/ +static void lcd_write_data(unsigned int d) +{ + /* Write data to LCD controller. */ + lcd_wait_busy(); + FIO1SET = LCD_RS; + lcd_write(d); + return; +} + +/****************************************************************************** +** Function name: LCD_init +** +** Descriptions: +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +void LCD_init(void) +{ + /* Initialize the ST7066 LCD controller to 4-bit mode. */ + PINSEL3 = 0x00000000; +#if USE_FIO + SCS |= 0x00000001;/* set GPIOx to use Fast I/O */ +#endif + FIO1DIR |= LCD_CTRL | LCD_DATA; + FIO1CLR = LCD_RW | LCD_RS | LCD_DATA; + + lcd_write_4bit(0x3); /* Select 4-bit interface */ + vTaskDelay(100); + lcd_write_4bit(0x3); + vTaskDelay(100); + lcd_write_4bit(0x3); + lcd_write_4bit(0x2); + + lcd_write_cmd(0x28); /* 2 lines, 5x8 character matrix */ + lcd_write_cmd(0x0e); /* Display ctrl:Disp/Curs/Blnk=ON */ + lcd_write_cmd(0x06); /* Entry mode: Move right, no shift */ + + LCD_load( (unsigned char *)&UserFont, sizeof (UserFont) ); + LCD_cls(); + return; +} + +/****************************************************************************** +** Function name: LCD_load +** +** Descriptions: +** +** parameters: pointer to the buffer and counter +** Returned value: None +** +******************************************************************************/ +void LCD_load(unsigned char *fp, unsigned int cnt) +{ + /* Load user-specific characters into CGRAM */ + unsigned int i; + + lcd_write_cmd( 0x40 ); /* Set CGRAM address counter to 0 */ + for (i = 0; i < cnt; i++, fp++) + { + lcd_write_data( *fp ); + } + return; +} + +/****************************************************************************** +** Function name: LCD_gotoxy +** +** Descriptions: +** +** parameters: pixel X and Y +** Returned value: None +** +******************************************************************************/ +void LCD_gotoxy(unsigned int x, unsigned int y) +{ + /* Set cursor position on LCD display. Left corner: 1,1, right: 16,2 */ + unsigned int c; + + c = --x; + if (--y) + { + c |= 0x40; + } + lcd_write_cmd (c | 0x80); + lcd_ptr = y*16 + x; + return; +} + +/****************************************************************************** +** Function name: LCD_cls +** +** Descriptions: +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +void LCD_cls(void) +{ + /* Clear LCD display, move cursor to home position. */ + lcd_write_cmd (0x01); + LCD_gotoxy (1,1); + return; +} + +/****************************************************************************** +** Function name: LCD_cur_off +** +** Descriptions: +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +void LCD_cur_off(void) +{ + /* Switch off LCD cursor. */ + lcd_write_cmd(0x0c); + return; +} + + +/****************************************************************************** +** Function name: LCD_on +** +** Descriptions: +** +** parameters: None +** Returned value: None +** +******************************************************************************/ +void LCD_on(void) +{ + /* Switch on LCD and enable cursor. */ + lcd_write_cmd (0x0e); + return; +} + +/****************************************************************************** +** Function name: LCD_putc +** +** Descriptions: +** +** parameters: unsigned char character +** Returned value: None +** +******************************************************************************/ +void LCD_putc(unsigned char c) +{ + /* Print a character to LCD at current cursor position. */ + if (lcd_ptr == 16) + { + lcd_write_cmd (0xc0); + } + lcd_write_data(c); + lcd_ptr++; + return; +} + +/****************************************************************************** +** Function name: LCD_puts +** +** Descriptions: +** +** parameters: pointer to the buffer +** Returned value: None +** +******************************************************************************/ +void LCD_puts(unsigned char *sp) +{ + /* Print a string to LCD display. */ + while (*sp) + { + LCD_putc (*sp++); + } + return; +} + +/****************************************************************************** +** Function name: LCD_bargraph +** +** Descriptions: +** +** parameters: value and size +** Returned value: None +** +******************************************************************************/ +void LCD_bargraph(unsigned int val, unsigned int size) +{ + /* Print a bargraph to LCD display. */ + /* - val: value 0..100 % */ + /* - size: size of bargraph 1..16 */ + unsigned int i; + + val = val * size / 20; /* Display matrix 5 x 8 pixels */ + for (i = 0; i < size; i++) + { + if (val > 5) + { + LCD_putc(5); + val -= 5; + } + else + { + LCD_putc(val); + break; + } + } + return; +} diff --git a/20080212/Demo/ARM7_LPC2368_Rowley/LCD/portlcd.h b/20080212/Demo/ARM7_LPC2368_Rowley/LCD/portlcd.h new file mode 100644 index 000000000..4742e4484 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Rowley/LCD/portlcd.h @@ -0,0 +1,31 @@ +/***************************************************************************** + * rtc.h: Header file for NXP LPC23xx/24xx Family Microprocessors + * + * Copyright(C) 2006, NXP Semiconductor + * All rights reserved. + * + * History + * 2006.07.13 ver 1.00 Prelimnary version, first Release + * +******************************************************************************/ +#ifndef __PORTLCD_H +#define __PORTLCD_H + +extern void LCD_init(void); +extern void LCD_load(unsigned char *fp, unsigned int cnt); +extern void LCD_gotoxy(unsigned int x, unsigned int y); +extern void LCD_cls(void); +extern void LCD_cur_off(void); +extern void LCD_on(void); +extern void LCD_putc(unsigned char c); +extern void LCD_puts(unsigned char *sp); +extern void LCD_bargraph(unsigned int val, unsigned int size); + +extern void LCD_putnibble(unsigned char nibble); +extern void LCD_puthexbyte(unsigned char abyte); + + +#endif /* end __PORTLCD_H */ +/***************************************************************************** +** End Of File +******************************************************************************/ diff --git a/20080212/Demo/ARM7_LPC2368_Rowley/ParTest/ParTest.c b/20080212/Demo/ARM7_LPC2368_Rowley/ParTest/ParTest.c new file mode 100644 index 000000000..83905dbfd --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Rowley/ParTest/ParTest.c @@ -0,0 +1,114 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* FreeRTOS.org includes. */ +#include "FreeRTOS.h" + +/* Demo application includes. */ +#include "partest.h" + +#define partstFIRST_IO ( ( unsigned portLONG ) 0x01 ) +#define partstNUM_LEDS ( 8 ) +#define partstALL_OUTPUTS_OFF ( ( unsigned portLONG ) 0xff ) + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ + PINSEL10 = 0; + FIO2DIR = 0x000000FF; + FIO2MASK = 0x00000000; + FIO2CLR = 0xFF; + SCS |= (1<<0); //fast mode for port 0 and 1 + + FIO2CLR = partstALL_OUTPUTS_OFF; +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ +unsigned portLONG ulLED = partstFIRST_IO; + + if( uxLED < partstNUM_LEDS ) + { + /* Rotate to the wanted bit of port */ + ulLED <<= ( unsigned portLONG ) uxLED; + + /* Set of clear the output. */ + if( xValue ) + { + FIO2CLR = ulLED; + } + else + { + FIO2SET = ulLED; + } + } +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned portLONG ulLED = partstFIRST_IO, ulCurrentState; + + if( uxLED < partstNUM_LEDS ) + { + /* Rotate to the wanted bit of port 0. Only P10 to P13 have an LED + attached. */ + ulLED <<= ( unsigned portLONG ) uxLED; + + /* If this bit is already set, clear it, and visa versa. */ + ulCurrentState = FIO2PIN; + if( ulCurrentState & ulLED ) + { + FIO2CLR = ulLED; + } + else + { + FIO2SET = ulLED; + } + } +} + +/*-----------------------------------------------------------*/ +unsigned portBASE_TYPE uxParTextGetLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned portLONG ulLED = partstFIRST_IO; + + ulLED <<= ( unsigned portLONG ) uxLED; + + return ( FIO2PIN & ulLED ); +} + + diff --git a/20080212/Demo/ARM7_LPC2368_Rowley/RTOSDemo.hzp b/20080212/Demo/ARM7_LPC2368_Rowley/RTOSDemo.hzp new file mode 100644 index 000000000..ab0dc7b71 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Rowley/RTOSDemo.hzp @@ -0,0 +1,103 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/20080212/Demo/ARM7_LPC2368_Rowley/RTOSDemo.hzs b/20080212/Demo/ARM7_LPC2368_Rowley/RTOSDemo.hzs new file mode 100644 index 000000000..2a058a243 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Rowley/RTOSDemo.hzs @@ -0,0 +1,74 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/20080212/Demo/ARM7_LPC2368_Rowley/main.c b/20080212/Demo/ARM7_LPC2368_Rowley/main.c new file mode 100644 index 000000000..8a368b57a --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Rowley/main.c @@ -0,0 +1,245 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* Environment includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "Task.h" +#include "queue.h" +#include "semphr.h" + +/* Demo app includes. */ +#include "BlockQ.h" +#include "death.h" +#include "integer.h" +#include "blocktim.h" +#include "portlcd.h" +#include "flash.h" +#include "partest.h" +#include "semtest.h" +#include "pollq.h" + +/* Demo application definitions. */ +#define mainQUEUE_SIZE ( 3 ) +#define mainCHECK_DELAY ( ( portTickType ) 5000 / portTICK_RATE_MS ) +#define mainBASIC_WEB_STACK_SIZE ( configMINIMAL_STACK_SIZE * 2 ) + +/* Task priorities. */ +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainFLASH_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainINTEGER_TASK_PRIORITY ( tskIDLE_PRIORITY ) + + +/* + * Checks the status of all the demo tasks then prints a message to the + * CrossStudio terminal IO windows. The message will be either PASS or FAIL + * depending on the status of the demo applications tasks. A FAIL status will + * be latched. + * + * Messages are not written directly to the terminal, but passed to vPrintTask + * via a queue. + */ +static void vCheckTask( void *pvParameters ); + +/* + * The task that handles the uIP stack. All TCP/IP processing is performed in + * this task. + */ +extern void vuIP_Task( void *pvParameters ); + +/* + * The LCD is written two by more than one task so is controlled by a + * 'gatekeeper' task. This is the only task that is actually permitted to + * access the LCD directly. Other tasks wanting to display a message send + * the message to the gatekeeper. + */ +static void vLCDTask( void *pvParameters ); + +/* The queue used to send messages to the LCD task. */ +xQueueHandle xLCDQueue; + +/*-----------------------------------------------------------*/ + +int main (void) +{ + /* Setup the led's on the MCB2300 board */ + vParTestInitialise(); + + /* Create the queue used by the LCD task. Messages for display on the LCD + are received via this queue. */ + xLCDQueue = xQueueCreate( mainQUEUE_SIZE, sizeof( xLCDMessage ) ); + + /* Create the lwIP task. This uses the lwIP RTOS abstraction layer.*/ + xTaskCreate( vuIP_Task, ( signed portCHAR * ) "uIP", mainBASIC_WEB_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY - 1, NULL ); + + /* Start the standard demo tasks. */ + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vCreateBlockTimeTasks(); + vStartLEDFlashTasks( mainFLASH_PRIORITY ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartIntegerMathTasks( mainINTEGER_TASK_PRIORITY ); + + /* Start the tasks defined within this file/specific to this demo. */ + xTaskCreate( vCheckTask, ( signed portCHAR * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + xTaskCreate( vLCDTask, ( signed portCHAR * ) "LCD", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY - 1, NULL ); + + /* The suicide tasks must be created last as they need to know how many + tasks were running prior to their creation in order to ascertain whether + or not the correct/expected number of tasks are running at any given time. */ + vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* Will only get here if there was insufficient memory to create the idle + task. */ + return 0; +} +/*-----------------------------------------------------------*/ + +static void vCheckTask( void *pvParameters ) +{ +portBASE_TYPE xErrorOccurred = pdFALSE; +portTickType xLastExecutionTime; +unsigned portBASE_TYPE uxColumn = 0; +xLCDMessage xMessage; + + xLastExecutionTime = xTaskGetTickCount(); + + xMessage.xColumn = 0; + xMessage.pcMessage = "PASS"; + + for( ;; ) + { + /* Perform this check every mainCHECK_DELAY milliseconds. */ + vTaskDelayUntil( &xLastExecutionTime, mainCHECK_DELAY ); + + /* Has an error been found in any task? */ + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + if( xIsCreateTaskStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + LCD_cls(); + xMessage.xColumn++; + LCD_gotoxy( ( uxColumn & 0x07 ) + 1, ( uxColumn & 0x01 ) + 1 ); + + if( xErrorOccurred == pdTRUE ) + { + xMessage.pcMessage = "FAIL"; + } + + /* Send the message to the LCD gatekeeper for display. */ + xQueueSend( xLCDQueue, &xMessage, portMAX_DELAY ); + } +} +/*-----------------------------------------------------------*/ + +void vLCDTask( void *pvParameters ) +{ +xLCDMessage xMessage; + + /* Initialise the LCD and display a startup message. */ + LCD_init(); + LCD_cur_off(); + LCD_cls(); + LCD_gotoxy( 1, 1 ); + LCD_puts( ( signed portCHAR * ) "www.FreeRTOS.org" ); + + for( ;; ) + { + /* Wait for a message to arrive that requires displaying. */ + while( xQueueReceive( xLCDQueue, &xMessage, portMAX_DELAY ) != pdPASS ); + + /* Display the message. Print each message to a different position. */ + LCD_cls(); + LCD_gotoxy( ( xMessage.xColumn & 0x07 ) + 1, ( xMessage.xColumn & 0x01 ) + 1 ); + LCD_puts( xMessage.pcMessage ); + } + +} +/*-----------------------------------------------------------*/ + +/* Keep the compiler quiet. */ +#include +int __putchar( int c ) +{ + return EOF; +} + + + + + diff --git a/20080212/Demo/ARM7_LPC2368_Rowley/webserver/EMAC_ISR.c b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/EMAC_ISR.c new file mode 100644 index 000000000..1796ce757 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/EMAC_ISR.c @@ -0,0 +1,46 @@ +#include "FreeRTOS.h" +#include "Semphr.h" +#include "Task.h" + +/* The interrupt entry point. */ +void vEMAC_ISR_Wrapper( void ) __attribute__((naked)); + +/* The function that actually performs the interrupt processing. This must be +separate to the wrapper to ensure the correct stack frame is set up. */ +void vEMAC_ISR_Handler( void ); + +extern xSemaphoreHandle xEMACSemaphore; + +void vEMAC_ISR_Handler( void ) +{ + /* Clear the interrupt. */ + IntClear = 0xffff; + VICVectAddr = 0; + + /* Ensure the uIP task is not blocked as data has arrived. */ + if( xSemaphoreGiveFromISR( xEMACSemaphore, pdFALSE ) ) + { + /* If the uIP task was unblocked then calling "Yield from ISR" here + will ensure the interrupt returns directly to the uIP task, if it + is the highest priority read task. */ + portYIELD_FROM_ISR(); + } +} +/*-----------------------------------------------------------*/ + +void vEMAC_ISR_Wrapper( void ) +{ + /* Save the context of the interrupted task. */ + portSAVE_CONTEXT(); + + /* Call the handler function. This must be separate from the wrapper + function to ensure the correct stack frame is set up. */ + vEMAC_ISR_Handler(); + + /* Restore the context of whichever task is going to run next. */ + portRESTORE_CONTEXT(); +} + + + + diff --git a/20080212/Demo/ARM7_LPC2368_Rowley/webserver/clock-arch.h b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/clock-arch.h new file mode 100644 index 000000000..cde657b62 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/clock-arch.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2006, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: clock-arch.h,v 1.2 2006/06/12 08:00:31 adam Exp $ + */ + +#ifndef __CLOCK_ARCH_H__ +#define __CLOCK_ARCH_H__ + +#include "FreeRTOS.h" + +typedef unsigned long clock_time_t; +#define CLOCK_CONF_SECOND configTICK_RATE_HZ + +#endif /* __CLOCK_ARCH_H__ */ diff --git a/20080212/Demo/ARM7_LPC2368_Rowley/webserver/emac.c b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/emac.c new file mode 100644 index 000000000..926a506fa --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/emac.c @@ -0,0 +1,412 @@ +/****************************************************************** + ***** ***** + ***** Name: cs8900.c ***** + ***** Ver.: 1.0 ***** + ***** Date: 07/05/2001 ***** + ***** Auth: Andreas Dannenberg ***** + ***** HTWK Leipzig ***** + ***** university of applied sciences ***** + ***** Germany ***** + ***** Func: ethernet packet-driver for use with LAN- ***** + ***** controller CS8900 from Crystal/Cirrus Logic ***** + ***** ***** + ***** Keil: Module modified for use with Philips ***** + ***** LPC2378 EMAC Ethernet controller ***** + ***** ***** + ******************************************************************/ + +/* Adapted from file originally written by Andreas Dannenberg. Supplied with permission. */ + +#include "FreeRTOS.h" +#include "Semphr.h" +#include "task.h" +#include "EMAC.h" + +/* The semaphore used to wake the uIP task when data arives. */ +xSemaphoreHandle xEMACSemaphore = NULL; + +static unsigned short *rptr; +static unsigned short *tptr; + +// easyWEB internal function +// help function to swap the byte order of a WORD + +static unsigned short SwapBytes(unsigned short Data) +{ + return (Data >> 8) | (Data << 8); +} + +// Keil: function added to write PHY +void write_PHY (int PhyReg, int Value) +{ + unsigned int tout; + + MADR = DP83848C_DEF_ADR | PhyReg; + MWTD = Value; + + /* Wait utill operation completed */ + tout = 0; + for (tout = 0; tout < MII_WR_TOUT; tout++) { + if ((MIND & MIND_BUSY) == 0) { + break; + } + } +} + + +// Keil: function added to read PHY +unsigned short read_PHY (unsigned char PhyReg) +{ + unsigned int tout; + + MADR = DP83848C_DEF_ADR | PhyReg; + MCMD = MCMD_READ; + + /* Wait until operation completed */ + tout = 0; + for (tout = 0; tout < MII_RD_TOUT; tout++) { + if ((MIND & MIND_BUSY) == 0) { + break; + } + } + MCMD = 0; + return (MRDD); +} + + +// Keil: function added to initialize Rx Descriptors +void rx_descr_init (void) +{ + unsigned int i; + + for (i = 0; i < NUM_RX_FRAG; i++) { + RX_DESC_PACKET(i) = RX_BUF(i); + RX_DESC_CTRL(i) = RCTRL_INT | (ETH_FRAG_SIZE-1); + RX_STAT_INFO(i) = 0; + RX_STAT_HASHCRC(i) = 0; + } + + /* Set EMAC Receive Descriptor Registers. */ + RxDescriptor = RX_DESC_BASE; + RxStatus = RX_STAT_BASE; + RxDescriptorNumber = NUM_RX_FRAG-1; + + /* Rx Descriptors Point to 0 */ + RxConsumeIndex = 0; +} + + +// Keil: function added to initialize Tx Descriptors +void tx_descr_init (void) { + unsigned int i; + + for (i = 0; i < NUM_TX_FRAG; i++) { + TX_DESC_PACKET(i) = TX_BUF(i); + TX_DESC_CTRL(i) = 0; + TX_STAT_INFO(i) = 0; + } + + /* Set EMAC Transmit Descriptor Registers. */ + TxDescriptor = TX_DESC_BASE; + TxStatus = TX_STAT_BASE; + TxDescriptorNumber = NUM_TX_FRAG-1; + + /* Tx Descriptors Point to 0 */ + TxProduceIndex = 0; +} + + +// configure port-pins for use with LAN-controller, +// reset it and send the configuration-sequence + +portBASE_TYPE Init_EMAC(void) +{ +portBASE_TYPE xReturn = pdPASS; +static portBASE_TYPE xAttempt = 0; +// Keil: function modified to access the EMAC +// Initializes the EMAC ethernet controller + volatile unsigned int regv,tout,id1,id2; + + /* Enable P1 Ethernet Pins. */ + PINSEL2 = configPINSEL2_VALUE; + PINSEL3 = (PINSEL3 & ~0x0000000F) | 0x00000005; + + /* Power Up the EMAC controller. */ + PCONP |= 0x40000000; + vTaskDelay( 1 ); + + /* Reset all EMAC internal modules. */ + MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | + MAC1_SIM_RES | MAC1_SOFT_RES; + Command = CR_REG_RES | CR_TX_RES | CR_RX_RES; + + /* A short delay after reset. */ + vTaskDelay( 1 ); + + /* Initialize MAC control registers. */ + MAC1 = MAC1_PASS_ALL; + MAC2 = MAC2_CRC_EN | MAC2_PAD_EN; + MAXF = ETH_MAX_FLEN; + CLRT = CLRT_DEF; + IPGR = IPGR_DEF; + + /* Enable Reduced MII interface. */ + Command = CR_RMII | CR_PASS_RUNT_FRM; + + /* Reset Reduced MII Logic. */ + SUPP = SUPP_RES_RMII; + SUPP = 0; + + /* Put the DP83848C in reset mode */ + write_PHY (PHY_REG_BMCR, 0x8000); + write_PHY (PHY_REG_BMCR, 0x8000); + + /* Wait for hardware reset to end. */ + for (tout = 0; tout < 100; tout++) { + vTaskDelay( 10 ); + regv = read_PHY (PHY_REG_BMCR); + if (!(regv & 0x8000)) { + /* Reset complete */ + break; + } + } + + /* Check if this is a DP83848C PHY. */ + id1 = read_PHY (PHY_REG_IDR1); + id2 = read_PHY (PHY_REG_IDR2); + if (((id1 << 16) | (id2 & 0xFFF0)) == DP83848C_ID) { + /* Configure the PHY device */ + + /* Use autonegotiation about the link speed. */ + write_PHY (PHY_REG_BMCR, PHY_AUTO_NEG); + /* Wait to complete Auto_Negotiation. */ + for (tout = 0; tout < 10; tout++) { + vTaskDelay( 100 ); + regv = read_PHY (PHY_REG_BMSR); + if (regv & 0x0020) { + /* Autonegotiation Complete. */ + break; + } + } + } + else + { + xReturn = pdFAIL; + } + + /* Check the link status. */ + if( xReturn == pdPASS ) + { + xReturn = pdFAIL; + for (tout = 0; tout < 10; tout++) { + vTaskDelay( 100 ); + regv = read_PHY (PHY_REG_STS); + if (regv & 0x0001) { + /* Link is on. */ + xReturn = pdPASS; + break; + } + } + } + + if( xReturn == pdPASS ) + { + /* Configure Full/Half Duplex mode. */ + if (regv & 0x0004) { + /* Full duplex is enabled. */ + MAC2 |= MAC2_FULL_DUP; + Command |= CR_FULL_DUP; + IPGT = IPGT_FULL_DUP; + } + else { + /* Half duplex mode. */ + IPGT = IPGT_HALF_DUP; + } + + /* Configure 100MBit/10MBit mode. */ + if (regv & 0x0002) { + /* 10MBit mode. */ + SUPP = 0; + } + else { + /* 100MBit mode. */ + SUPP = SUPP_SPEED; + } + + /* Set the Ethernet MAC Address registers */ + SA0 = (emacETHADDR0 << 8) | emacETHADDR1; + SA1 = (emacETHADDR2 << 8) | emacETHADDR3; + SA2 = (emacETHADDR4 << 8) | emacETHADDR5; + + /* Initialize Tx and Rx DMA Descriptors */ + rx_descr_init (); + tx_descr_init (); + + /* Receive Broadcast and Perfect Match Packets */ + RxFilterCtrl = RFC_UCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN; + + /* Create the semaphore used ot wake the uIP task. */ + vSemaphoreCreateBinary( xEMACSemaphore ); + + /* Reset all interrupts */ + IntClear = 0xFFFF; + + /* Enable receive and transmit mode of MAC Ethernet core */ + Command |= (CR_RX_EN | CR_TX_EN); + MAC1 |= MAC1_REC_EN; + } + + return xReturn; +} + + +// reads a word in little-endian byte order from RX_BUFFER + +unsigned short ReadFrame_EMAC(void) +{ + return (*rptr++); +} + +// reads a word in big-endian byte order from RX_FRAME_PORT +// (useful to avoid permanent byte-swapping while reading +// TCP/IP-data) + +unsigned short ReadFrameBE_EMAC(void) +{ + unsigned short ReturnValue; + + ReturnValue = SwapBytes (*rptr++); + return (ReturnValue); +} + + +// copies bytes from frame port to MCU-memory +// NOTES: * an odd number of byte may only be transfered +// if the frame is read to the end! +// * MCU-memory MUST start at word-boundary + +void CopyFromFrame_EMAC(void *Dest, unsigned short Size) +{ + unsigned short * piDest; // Keil: Pointer added to correct expression + + piDest = Dest; // Keil: Line added + while (Size > 1) { + *piDest++ = ReadFrame_EMAC(); + Size -= 2; + } + + if (Size) { // check for leftover byte... + *(unsigned char *)piDest = (char)ReadFrame_EMAC();// the LAN-Controller will return 0 + } // for the highbyte +} + +// does a dummy read on frame-I/O-port +// NOTE: only an even number of bytes is read! + +void DummyReadFrame_EMAC(unsigned short Size) // discards an EVEN number of bytes +{ // from RX-fifo + while (Size > 1) { + ReadFrame_EMAC(); + Size -= 2; + } +} + +// Reads the length of the received ethernet frame and checks if the +// destination address is a broadcast message or not +// returns the frame length +unsigned short StartReadFrame(void) { + unsigned short RxLen; + unsigned int idx; + + idx = RxConsumeIndex; + RxLen = (RX_STAT_INFO(idx) & RINFO_SIZE) - 3; + rptr = (unsigned short *)RX_DESC_PACKET(idx); + return(RxLen); +} + +void EndReadFrame(void) { + unsigned int idx; + + /* DMA free packet. */ + idx = RxConsumeIndex; + + if (++idx == NUM_RX_FRAG) + idx = 0; + + RxConsumeIndex = idx; +} + +unsigned int CheckFrameReceived(void) { // Packet received ? + + if (RxProduceIndex != RxConsumeIndex) // more packets received ? + return(1); + else + return(0); +} + +unsigned int uiGetEMACRxData( unsigned char *ucBuffer ) +{ +unsigned int uiLen = 0; + + if( RxProduceIndex != RxConsumeIndex ) + { + uiLen = StartReadFrame(); + CopyFromFrame_EMAC( ucBuffer, uiLen ); + EndReadFrame(); + } + + return uiLen; +} + +// requests space in EMAC memory for storing an outgoing frame + +void RequestSend(void) +{ + unsigned int idx; + + idx = TxProduceIndex; + tptr = (unsigned short *)TX_DESC_PACKET(idx); +} + +// check if ethernet controller is ready to accept the +// frame we want to send + +unsigned int Rdy4Tx(void) +{ + return (1); // the ethernet controller transmits much faster +} // than the CPU can load its buffers + + +// writes a word in little-endian byte order to TX_BUFFER +void WriteFrame_EMAC(unsigned short Data) +{ + *tptr++ = Data; +} + +// copies bytes from MCU-memory to frame port +// NOTES: * an odd number of byte may only be transfered +// if the frame is written to the end! +// * MCU-memory MUST start at word-boundary + +void CopyToFrame_EMAC(void *Source, unsigned int Size) +{ + unsigned short * piSource; + + piSource = Source; + Size = (Size + 1) & 0xFFFE; // round Size up to next even number + while (Size > 0) { + WriteFrame_EMAC(*piSource++); + Size -= 2; + } +} + +void DoSend_EMAC(unsigned short FrameSize) +{ + unsigned int idx; + + idx = TxProduceIndex; + TX_DESC_CTRL(idx) = FrameSize | TCTRL_LAST; + if (++idx == NUM_TX_FRAG) idx = 0; + TxProduceIndex = idx; +} + diff --git a/20080212/Demo/ARM7_LPC2368_Rowley/webserver/emac.h b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/emac.h new file mode 100644 index 000000000..c3634217d --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/emac.h @@ -0,0 +1,322 @@ +/*---------------------------------------------------------------------------- + * LPC2378 Ethernet Definitions + *---------------------------------------------------------------------------- + * Name: EMAC.H + * Purpose: Philips LPC2378 EMAC hardware definitions + *---------------------------------------------------------------------------- + * Copyright (c) 2006 KEIL - An ARM Company. All rights reserved. + *---------------------------------------------------------------------------*/ +#ifndef __EMAC_H +#define __EMAC_H + +/* MAC address definition. The MAC address must be unique on the network. */ +#define emacETHADDR0 0 +#define emacETHADDR1 0xbd +#define emacETHADDR2 0x33 +#define emacETHADDR3 0x02 +#define emacETHADDR4 0x64 +#define emacETHADDR5 0x24 + + +/* EMAC Memory Buffer configuration for 16K Ethernet RAM. */ +#define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */ +#define NUM_TX_FRAG 2 /* Num.of TX Fragments 2*1536= 3.0kB */ +#define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */ + +#define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */ + +/* EMAC variables located in 16K Ethernet SRAM */ +#define RX_DESC_BASE 0x7FE00000 +#define RX_STAT_BASE (RX_DESC_BASE + NUM_RX_FRAG*8) +#define TX_DESC_BASE (RX_STAT_BASE + NUM_RX_FRAG*8) +#define TX_STAT_BASE (TX_DESC_BASE + NUM_TX_FRAG*8) +#define RX_BUF_BASE (TX_STAT_BASE + NUM_TX_FRAG*4) +#define TX_BUF_BASE (RX_BUF_BASE + NUM_RX_FRAG*ETH_FRAG_SIZE) + +/* RX and TX descriptor and status definitions. */ +#define RX_DESC_PACKET(i) (*(unsigned int *)(RX_DESC_BASE + 8*i)) +#define RX_DESC_CTRL(i) (*(unsigned int *)(RX_DESC_BASE+4 + 8*i)) +#define RX_STAT_INFO(i) (*(unsigned int *)(RX_STAT_BASE + 8*i)) +#define RX_STAT_HASHCRC(i) (*(unsigned int *)(RX_STAT_BASE+4 + 8*i)) +#define TX_DESC_PACKET(i) (*(unsigned int *)(TX_DESC_BASE + 8*i)) +#define TX_DESC_CTRL(i) (*(unsigned int *)(TX_DESC_BASE+4 + 8*i)) +#define TX_STAT_INFO(i) (*(unsigned int *)(TX_STAT_BASE + 4*i)) +#define RX_BUF(i) (RX_BUF_BASE + ETH_FRAG_SIZE*i) +#define TX_BUF(i) (TX_BUF_BASE + ETH_FRAG_SIZE*i) + +/* MAC Configuration Register 1 */ +#define MAC1_REC_EN 0x00000001 /* Receive Enable */ +#define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */ +#define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */ +#define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */ +#define MAC1_LOOPB 0x00000010 /* Loop Back Mode */ +#define MAC1_RES_TX 0x00000100 /* Reset TX Logic */ +#define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */ +#define MAC1_RES_RX 0x00000400 /* Reset RX Logic */ +#define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */ +#define MAC1_SIM_RES 0x00004000 /* Simulation Reset */ +#define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */ + +/* MAC Configuration Register 2 */ +#define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */ +#define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */ +#define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */ +#define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */ +#define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */ +#define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */ +#define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */ +#define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */ +#define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */ +#define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */ +#undef MAC2_NO_BACKOFF /* Remove compiler warning. */ +#define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */ +#define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */ +#define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */ + +/* Back-to-Back Inter-Packet-Gap Register */ +#define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */ +#define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */ + +/* Non Back-to-Back Inter-Packet-Gap Register */ +#define IPGR_DEF 0x00000012 /* Recommended value */ + +/* Collision Window/Retry Register */ +#define CLRT_DEF 0x0000370F /* Default value */ + +/* PHY Support Register */ +#undef SUPP_SPEED /* Remove compiler warning. */ +#define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */ +#define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */ + +/* Test Register */ +#define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */ +#define TEST_TST_PAUSE 0x00000002 /* Test Pause */ +#define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */ + +/* MII Management Configuration Register */ +#define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */ +#define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */ +#define MCFG_CLK_SEL 0x0000001C /* Clock Select Mask */ +#define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */ + +/* MII Management Command Register */ +#undef MCMD_READ /* Remove compiler warning. */ +#define MCMD_READ 0x00000001 /* MII Read */ +#undef MCMD_SCAN /* Remove compiler warning. */ +#define MCMD_SCAN 0x00000002 /* MII Scan continuously */ + +#define MII_WR_TOUT 0x00050000 /* MII Write timeout count */ +#define MII_RD_TOUT 0x00050000 /* MII Read timeout count */ + +/* MII Management Address Register */ +#define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */ +#define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */ + +/* MII Management Indicators Register */ +#undef MIND_BUSY /* Remove compiler warning. */ +#define MIND_BUSY 0x00000001 /* MII is Busy */ +#define MIND_SCAN 0x00000002 /* MII Scanning in Progress */ +#define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */ +#define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */ + +/* Command Register */ +#define CR_RX_EN 0x00000001 /* Enable Receive */ +#define CR_TX_EN 0x00000002 /* Enable Transmit */ +#define CR_REG_RES 0x00000008 /* Reset Host Registers */ +#define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */ +#define CR_RX_RES 0x00000020 /* Reset Receive Datapath */ +#define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */ +#define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */ +#define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */ +#define CR_RMII 0x00000200 /* Reduced MII Interface */ +#define CR_FULL_DUP 0x00000400 /* Full Duplex */ + +/* Status Register */ +#define SR_RX_EN 0x00000001 /* Enable Receive */ +#define SR_TX_EN 0x00000002 /* Enable Transmit */ + +/* Transmit Status Vector 0 Register */ +#define TSV0_CRC_ERR 0x00000001 /* CRC error */ +#define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */ +#define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */ +#define TSV0_DONE 0x00000008 /* Tramsmission Completed */ +#define TSV0_MCAST 0x00000010 /* Multicast Destination */ +#define TSV0_BCAST 0x00000020 /* Broadcast Destination */ +#define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */ +#define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */ +#define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */ +#define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */ +#define TSV0_GIANT 0x00000400 /* Giant Frame */ +#define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */ +#define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */ +#define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */ +#define TSV0_PAUSE 0x20000000 /* Pause Frame */ +#define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */ +#define TSV0_VLAN 0x80000000 /* VLAN Frame */ + +/* Transmit Status Vector 1 Register */ +#define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */ +#define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */ + +/* Receive Status Vector Register */ +#define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */ +#define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */ +#define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */ +#define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */ +#define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */ +#define RSV_CRC_ERR 0x00100000 /* CRC Error */ +#define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */ +#define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */ +#define RSV_REC_OK 0x00800000 /* Frame Received OK */ +#define RSV_MCAST 0x01000000 /* Multicast Frame */ +#define RSV_BCAST 0x02000000 /* Broadcast Frame */ +#define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */ +#define RSV_CTRL_FRAME 0x08000000 /* Control Frame */ +#define RSV_PAUSE 0x10000000 /* Pause Frame */ +#define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */ +#define RSV_VLAN 0x40000000 /* VLAN Frame */ + +/* Flow Control Counter Register */ +#define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */ +#define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */ + +/* Flow Control Status Register */ +#define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */ + +/* Receive Filter Control Register */ +#define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */ +#define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */ +#define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */ +#define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */ +#define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/ +#define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */ +#define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */ +#define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */ + +/* Receive Filter WoL Status/Clear Registers */ +#define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */ +#define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */ +#define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */ +#define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */ +#define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */ +#define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */ +#define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */ +#define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */ + +/* Interrupt Status/Enable/Clear/Set Registers */ +#define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */ +#define INT_RX_ERR 0x00000002 /* Receive Error */ +#define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */ +#define INT_RX_DONE 0x00000008 /* Receive Done */ +#define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */ +#define INT_TX_ERR 0x00000020 /* Transmit Error */ +#define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */ +#define INT_TX_DONE 0x00000080 /* Transmit Done */ +#define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */ +#define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */ + +/* Power Down Register */ +#define PD_POWER_DOWN 0x80000000 /* Power Down MAC */ + +/* RX Descriptor Control Word */ +#define RCTRL_SIZE 0x000007FF /* Buffer size mask */ +#define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */ + +/* RX Status Hash CRC Word */ +#define RHASH_SA 0x000001FF /* Hash CRC for Source Address */ +#define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */ + +/* RX Status Information Word */ +#define RINFO_SIZE 0x000007FF /* Data size in bytes */ +#define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */ +#define RINFO_VLAN 0x00080000 /* VLAN Frame */ +#define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */ +#define RINFO_MCAST 0x00200000 /* Multicast Frame */ +#define RINFO_BCAST 0x00400000 /* Broadcast Frame */ +#define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */ +#define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */ +#define RINFO_LEN_ERR 0x02000000 /* Length Error */ +#define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */ +#define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */ +#define RINFO_OVERRUN 0x10000000 /* Receive overrun */ +#define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */ +#define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */ +#define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ + +#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | \ + RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN) + +/* TX Descriptor Control Word */ +#define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */ +#define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */ +#define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */ +#define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */ +#define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */ +#define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */ +#define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */ + +/* TX Status Information Word */ +#define TINFO_COL_CNT 0x01E00000 /* Collision Count */ +#define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */ +#define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */ +#define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */ +#define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */ +#define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */ +#define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */ +#define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ + +/* DP83848C PHY Registers */ +#define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */ +#define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */ +#define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */ +#define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */ +#define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */ +#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */ +#define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */ +#define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */ + +/* PHY Extended Registers */ +#define PHY_REG_STS 0x10 /* Status Register */ +#define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */ +#define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */ +#define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */ +#define PHY_REG_RECR 0x15 /* Receive Error Counter */ +#define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */ +#define PHY_REG_RBR 0x17 /* RMII and Bypass Register */ +#define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */ +#define PHY_REG_PHYCR 0x19 /* PHY Control Register */ +#define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */ +#define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */ +#define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */ + +#define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */ +#define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */ +#define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */ +#define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */ +#define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */ + +#define DP83848C_DEF_ADR 0x0100 /* Default PHY device address */ +#define DP83848C_ID 0x20005C90 /* PHY Identifier */ + +// prototypes +portBASE_TYPE Init_EMAC(void); +unsigned short ReadFrameBE_EMAC(void); +void CopyToFrame_EMAC(void *Source, unsigned int Size); +void CopyFromFrame_EMAC(void *Dest, unsigned short Size); +void DummyReadFrame_EMAC(unsigned short Size); +unsigned short StartReadFrame(void); +void EndReadFrame(void); +unsigned int CheckFrameReceived(void); +void RequestSend(void); +unsigned int Rdy4Tx(void); +void DoSend_EMAC(unsigned short FrameSize); +void vEMACWaitForInput( void ); +unsigned int uiGetEMACRxData( unsigned char *ucBuffer ); + + +#endif + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/20080212/Demo/ARM7_LPC2368_Rowley/webserver/http-strings b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/http-strings new file mode 100644 index 000000000..0d3c30cdd --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/http-strings @@ -0,0 +1,35 @@ +http_http "http://" +http_200 "200 " +http_301 "301 " +http_302 "302 " +http_get "GET " +http_10 "HTTP/1.0" +http_11 "HTTP/1.1" +http_content_type "content-type: " +http_texthtml "text/html" +http_location "location: " +http_host "host: " +http_crnl "\r\n" +http_index_html "/index.html" +http_404_html "/404.html" +http_referer "Referer:" +http_header_200 "HTTP/1.0 200 OK\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" +http_header_404 "HTTP/1.0 404 Not found\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" +http_content_type_plain "Content-type: text/plain\r\n\r\n" +http_content_type_html "Content-type: text/html\r\n\r\n" +http_content_type_css "Content-type: text/css\r\n\r\n" +http_content_type_text "Content-type: text/text\r\n\r\n" +http_content_type_png "Content-type: image/png\r\n\r\n" +http_content_type_gif "Content-type: image/gif\r\n\r\n" +http_content_type_jpg "Content-type: image/jpeg\r\n\r\n" +http_content_type_binary "Content-type: application/octet-stream\r\n\r\n" +http_html ".html" +http_shtml ".shtml" +http_htm ".htm" +http_css ".css" +http_png ".png" +http_gif ".gif" +http_jpg ".jpg" +http_text ".txt" +http_txt ".txt" + diff --git a/20080212/Demo/ARM7_LPC2368_Rowley/webserver/http-strings.c b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/http-strings.c new file mode 100644 index 000000000..ef7a41c7d --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/http-strings.c @@ -0,0 +1,102 @@ +const char http_http[8] = +/* "http://" */ +{0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, }; +const char http_200[5] = +/* "200 " */ +{0x32, 0x30, 0x30, 0x20, }; +const char http_301[5] = +/* "301 " */ +{0x33, 0x30, 0x31, 0x20, }; +const char http_302[5] = +/* "302 " */ +{0x33, 0x30, 0x32, 0x20, }; +const char http_get[5] = +/* "GET " */ +{0x47, 0x45, 0x54, 0x20, }; +const char http_10[9] = +/* "HTTP/1.0" */ +{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, }; +const char http_11[9] = +/* "HTTP/1.1" */ +{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x31, }; +const char http_content_type[15] = +/* "content-type: " */ +{0x63, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, }; +const char http_texthtml[10] = +/* "text/html" */ +{0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_location[11] = +/* "location: " */ +{0x6c, 0x6f, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, }; +const char http_host[7] = +/* "host: " */ +{0x68, 0x6f, 0x73, 0x74, 0x3a, 0x20, }; +const char http_crnl[3] = +/* "\r\n" */ +{0xd, 0xa, }; +const char http_index_html[12] = +/* "/index.html" */ +{0x2f, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_404_html[10] = +/* "/404.html" */ +{0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_referer[9] = +/* "Referer:" */ +{0x52, 0x65, 0x66, 0x65, 0x72, 0x65, 0x72, 0x3a, }; +const char http_header_200[84] = +/* "HTTP/1.0 200 OK\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */ +{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x32, 0x30, 0x30, 0x20, 0x4f, 0x4b, 0xd, 0xa, 0x53, 0x65, 0x72, 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x73, 0x69, 0x63, 0x73, 0x2e, 0x73, 0x65, 0x2f, 0x7e, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, 0x70, 0x2f, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0xd, 0xa, }; +const char http_header_404[91] = +/* "HTTP/1.0 404 Not found\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */ +{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x34, 0x30, 0x34, 0x20, 0x4e, 0x6f, 0x74, 0x20, 0x66, 0x6f, 0x75, 0x6e, 0x64, 0xd, 0xa, 0x53, 0x65, 0x72, 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x73, 0x69, 0x63, 0x73, 0x2e, 0x73, 0x65, 0x2f, 0x7e, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, 0x70, 0x2f, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0xd, 0xa, }; +const char http_content_type_plain[29] = +/* "Content-type: text/plain\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x70, 0x6c, 0x61, 0x69, 0x6e, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_html[28] = +/* "Content-type: text/html\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_css [27] = +/* "Content-type: text/css\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x63, 0x73, 0x73, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_text[28] = +/* "Content-type: text/text\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x74, 0x65, 0x78, 0x74, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_png [28] = +/* "Content-type: image/png\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x70, 0x6e, 0x67, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_gif [28] = +/* "Content-type: image/gif\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x67, 0x69, 0x66, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_jpg [29] = +/* "Content-type: image/jpeg\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x6a, 0x70, 0x65, 0x67, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_binary[43] = +/* "Content-type: application/octet-stream\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x61, 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x2f, 0x6f, 0x63, 0x74, 0x65, 0x74, 0x2d, 0x73, 0x74, 0x72, 0x65, 0x61, 0x6d, 0xd, 0xa, 0xd, 0xa, }; +const char http_html[6] = +/* ".html" */ +{0x2e, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_shtml[7] = +/* ".shtml" */ +{0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_htm[5] = +/* ".htm" */ +{0x2e, 0x68, 0x74, 0x6d, }; +const char http_css[5] = +/* ".css" */ +{0x2e, 0x63, 0x73, 0x73, }; +const char http_png[5] = +/* ".png" */ +{0x2e, 0x70, 0x6e, 0x67, }; +const char http_gif[5] = +/* ".gif" */ +{0x2e, 0x67, 0x69, 0x66, }; +const char http_jpg[5] = +/* ".jpg" */ +{0x2e, 0x6a, 0x70, 0x67, }; +const char http_text[5] = +/* ".txt" */ +{0x2e, 0x74, 0x78, 0x74, }; +const char http_txt[5] = +/* ".txt" */ +{0x2e, 0x74, 0x78, 0x74, }; diff --git a/20080212/Demo/ARM7_LPC2368_Rowley/webserver/http-strings.h b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/http-strings.h new file mode 100644 index 000000000..acbe7e17f --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/http-strings.h @@ -0,0 +1,34 @@ +extern const char http_http[8]; +extern const char http_200[5]; +extern const char http_301[5]; +extern const char http_302[5]; +extern const char http_get[5]; +extern const char http_10[9]; +extern const char http_11[9]; +extern const char http_content_type[15]; +extern const char http_texthtml[10]; +extern const char http_location[11]; +extern const char http_host[7]; +extern const char http_crnl[3]; +extern const char http_index_html[12]; +extern const char http_404_html[10]; +extern const char http_referer[9]; +extern const char http_header_200[84]; +extern const char http_header_404[91]; +extern const char http_content_type_plain[29]; +extern const char http_content_type_html[28]; +extern const char http_content_type_css [27]; +extern const char http_content_type_text[28]; +extern const char http_content_type_png [28]; +extern const char http_content_type_gif [28]; +extern const char http_content_type_jpg [29]; +extern const char http_content_type_binary[43]; +extern const char http_html[6]; +extern const char http_shtml[7]; +extern const char http_htm[5]; +extern const char http_css[5]; +extern const char http_png[5]; +extern const char http_gif[5]; +extern const char http_jpg[5]; +extern const char http_text[5]; +extern const char http_txt[5]; diff --git a/20080212/Demo/ARM7_LPC2368_Rowley/webserver/httpd-cgi.c b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/httpd-cgi.c new file mode 100644 index 000000000..fb87c478f --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/httpd-cgi.c @@ -0,0 +1,276 @@ +/** + * \addtogroup httpd + * @{ + */ + +/** + * \file + * Web server script interface + * \author + * Adam Dunkels + * + */ + +/* + * Copyright (c) 2001-2006, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: httpd-cgi.c,v 1.2 2006/06/11 21:46:37 adam Exp $ + * + */ + +#include "uip.h" +#include "psock.h" +#include "httpd.h" +#include "httpd-cgi.h" +#include "httpd-fs.h" + +#include +#include + +HTTPD_CGI_CALL(file, "file-stats", file_stats); +HTTPD_CGI_CALL(tcp, "tcp-connections", tcp_stats); +HTTPD_CGI_CALL(net, "net-stats", net_stats); +HTTPD_CGI_CALL(rtos, "rtos-stats", rtos_stats ); +HTTPD_CGI_CALL(io, "led-io", led_io ); + + +static const struct httpd_cgi_call *calls[] = { &file, &tcp, &net, &rtos, &io, NULL }; + +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(nullfunction(struct httpd_state *s, char *ptr)) +{ + PSOCK_BEGIN(&s->sout); + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +httpd_cgifunction +httpd_cgi(char *name) +{ + const struct httpd_cgi_call **f; + + /* Find the matching name in the table, return the function. */ + for(f = calls; *f != NULL; ++f) { + if(strncmp((*f)->name, name, strlen((*f)->name)) == 0) { + return (*f)->function; + } + } + return nullfunction; +} +/*---------------------------------------------------------------------------*/ +static unsigned short +generate_file_stats(void *arg) +{ + char *f = (char *)arg; + return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, "%5u", httpd_fs_count(f)); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(file_stats(struct httpd_state *s, char *ptr)) +{ + PSOCK_BEGIN(&s->sout); + + PSOCK_GENERATOR_SEND(&s->sout, generate_file_stats, strchr(ptr, ' ') + 1); + + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +static const char closed[] = /* "CLOSED",*/ +{0x43, 0x4c, 0x4f, 0x53, 0x45, 0x44, 0}; +static const char syn_rcvd[] = /* "SYN-RCVD",*/ +{0x53, 0x59, 0x4e, 0x2d, 0x52, 0x43, 0x56, + 0x44, 0}; +static const char syn_sent[] = /* "SYN-SENT",*/ +{0x53, 0x59, 0x4e, 0x2d, 0x53, 0x45, 0x4e, + 0x54, 0}; +static const char established[] = /* "ESTABLISHED",*/ +{0x45, 0x53, 0x54, 0x41, 0x42, 0x4c, 0x49, 0x53, 0x48, + 0x45, 0x44, 0}; +static const char fin_wait_1[] = /* "FIN-WAIT-1",*/ +{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49, + 0x54, 0x2d, 0x31, 0}; +static const char fin_wait_2[] = /* "FIN-WAIT-2",*/ +{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49, + 0x54, 0x2d, 0x32, 0}; +static const char closing[] = /* "CLOSING",*/ +{0x43, 0x4c, 0x4f, 0x53, 0x49, + 0x4e, 0x47, 0}; +static const char time_wait[] = /* "TIME-WAIT,"*/ +{0x54, 0x49, 0x4d, 0x45, 0x2d, 0x57, 0x41, + 0x49, 0x54, 0}; +static const char last_ack[] = /* "LAST-ACK"*/ +{0x4c, 0x41, 0x53, 0x54, 0x2d, 0x41, 0x43, + 0x4b, 0}; + +static const char *states[] = { + closed, + syn_rcvd, + syn_sent, + established, + fin_wait_1, + fin_wait_2, + closing, + time_wait, + last_ack}; + + +static unsigned short +generate_tcp_stats(void *arg) +{ + struct uip_conn *conn; + struct httpd_state *s = (struct httpd_state *)arg; + + conn = &uip_conns[s->count]; + return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, + "\r\n", + htons(conn->lport), + htons(conn->ripaddr[0]) >> 8, + htons(conn->ripaddr[0]) & 0xff, + htons(conn->ripaddr[1]) >> 8, + htons(conn->ripaddr[1]) & 0xff, + htons(conn->rport), + states[conn->tcpstateflags & UIP_TS_MASK], + conn->nrtx, + conn->timer, + (uip_outstanding(conn))? '*':' ', + (uip_stopped(conn))? '!':' '); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(tcp_stats(struct httpd_state *s, char *ptr)) +{ + + PSOCK_BEGIN(&s->sout); + + for(s->count = 0; s->count < UIP_CONNS; ++s->count) { + if((uip_conns[s->count].tcpstateflags & UIP_TS_MASK) != UIP_CLOSED) { + PSOCK_GENERATOR_SEND(&s->sout, generate_tcp_stats, s); + } + } + + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +static unsigned short +generate_net_stats(void *arg) +{ + struct httpd_state *s = (struct httpd_state *)arg; + return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, + "%5u\n", ((uip_stats_t *)&uip_stat)[s->count]); +} + +static +PT_THREAD(net_stats(struct httpd_state *s, char *ptr)) +{ + PSOCK_BEGIN(&s->sout); + +#if UIP_STATISTICS + + for(s->count = 0; s->count < sizeof(uip_stat) / sizeof(uip_stats_t); + ++s->count) { + PSOCK_GENERATOR_SEND(&s->sout, generate_net_stats, s); + } + +#endif /* UIP_STATISTICS */ + + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ + +extern void vTaskList( signed char *pcWriteBuffer ); +static char cCountBuf[ 32 ]; +long lRefreshCount = 0; +static unsigned short +generate_rtos_stats(void *arg) +{ + lRefreshCount++; + sprintf( cCountBuf, "


Refresh count = %d", lRefreshCount ); + vTaskList( uip_appdata ); + strcat( uip_appdata, cCountBuf ); + + return strlen( uip_appdata ); +} +/*---------------------------------------------------------------------------*/ + + +static +PT_THREAD(rtos_stats(struct httpd_state *s, char *ptr)) +{ + PSOCK_BEGIN(&s->sout); + PSOCK_GENERATOR_SEND(&s->sout, generate_rtos_stats, NULL); + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ + +char *pcStatus[ 3 ]; +unsigned long ulString; +extern unsigned long uxParTextGetLED( unsigned long uxLED ); + +static unsigned short generate_io_state( void *arg ) +{ + for( ulString = 0; ulString < 4; ulString++ ) + { + if( uxParTextGetLED( ulString + 5 ) ) + { + pcStatus[ ulString ] = "checked"; + } + else + { + pcStatus[ ulString ] = ""; + } + } + + sprintf( uip_appdata, + "LED 2.5,"\ + "LED 2.6,"\ + "LED 2.7"\ + "

"\ + "", + pcStatus[ 0 ], + pcStatus[ 1 ], + pcStatus[ 2 ] ); + + return strlen( uip_appdata ); +} + +static PT_THREAD(led_io(struct httpd_state *s, char *ptr)) +{ + PSOCK_BEGIN(&s->sout); + PSOCK_GENERATOR_SEND(&s->sout, generate_io_state, NULL); + PSOCK_END(&s->sout); +} + +/** @} */ + + + + + + diff --git a/20080212/Demo/ARM7_LPC2368_Rowley/webserver/httpd-cgi.h b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/httpd-cgi.h new file mode 100644 index 000000000..7ae928321 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/httpd-cgi.h @@ -0,0 +1,84 @@ +/** + * \addtogroup httpd + * @{ + */ + +/** + * \file + * Web server script interface header file + * \author + * Adam Dunkels + * + */ + + + +/* + * Copyright (c) 2001, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: httpd-cgi.h,v 1.2 2006/06/11 21:46:38 adam Exp $ + * + */ + +#ifndef __HTTPD_CGI_H__ +#define __HTTPD_CGI_H__ + +#include "psock.h" +#include "httpd.h" + +typedef PT_THREAD((* httpd_cgifunction)(struct httpd_state *, char *)); + +httpd_cgifunction httpd_cgi(char *name); + +struct httpd_cgi_call { + const char *name; + const httpd_cgifunction function; +}; + +/** + * \brief HTTPD CGI function declaration + * \param name The C variable name of the function + * \param str The string name of the function, used in the script file + * \param function A pointer to the function that implements it + * + * This macro is used for declaring a HTTPD CGI + * function. This function is then added to the list of + * HTTPD CGI functions with the httpd_cgi_add() function. + * + * \hideinitializer + */ +#define HTTPD_CGI_CALL(name, str, function) \ +static PT_THREAD(function(struct httpd_state *, char *)); \ +static const struct httpd_cgi_call name = {str, function} + +void httpd_cgi_init(void); +#endif /* __HTTPD_CGI_H__ */ + +/** @} */ diff --git a/20080212/Demo/ARM7_LPC2368_Rowley/webserver/httpd-fs.c b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/httpd-fs.c new file mode 100644 index 000000000..dc4aef011 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/httpd-fs.c @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: httpd-fs.c,v 1.1 2006/06/07 09:13:08 adam Exp $ + */ + +#include "httpd.h" +#include "httpd-fs.h" +#include "httpd-fsdata.h" + +#ifndef NULL +#define NULL 0 +#endif /* NULL */ + +#include "httpd-fsdata.c" + +#if HTTPD_FS_STATISTICS +static u16_t count[HTTPD_FS_NUMFILES]; +#endif /* HTTPD_FS_STATISTICS */ + +/*-----------------------------------------------------------------------------------*/ +static u8_t +httpd_fs_strcmp(const char *str1, const char *str2) +{ + u8_t i; + i = 0; + loop: + + if(str2[i] == 0 || + str1[i] == '\r' || + str1[i] == '\n') { + return 0; + } + + if(str1[i] != str2[i]) { + return 1; + } + + + ++i; + goto loop; +} +/*-----------------------------------------------------------------------------------*/ +int +httpd_fs_open(const char *name, struct httpd_fs_file *file) +{ +#if HTTPD_FS_STATISTICS + u16_t i = 0; +#endif /* HTTPD_FS_STATISTICS */ + struct httpd_fsdata_file_noconst *f; + + for(f = (struct httpd_fsdata_file_noconst *)HTTPD_FS_ROOT; + f != NULL; + f = (struct httpd_fsdata_file_noconst *)f->next) { + + if(httpd_fs_strcmp(name, f->name) == 0) { + file->data = f->data; + file->len = f->len; +#if HTTPD_FS_STATISTICS + ++count[i]; +#endif /* HTTPD_FS_STATISTICS */ + return 1; + } +#if HTTPD_FS_STATISTICS + ++i; +#endif /* HTTPD_FS_STATISTICS */ + + } + return 0; +} +/*-----------------------------------------------------------------------------------*/ +void +httpd_fs_init(void) +{ +#if HTTPD_FS_STATISTICS + u16_t i; + for(i = 0; i < HTTPD_FS_NUMFILES; i++) { + count[i] = 0; + } +#endif /* HTTPD_FS_STATISTICS */ +} +/*-----------------------------------------------------------------------------------*/ +#if HTTPD_FS_STATISTICS +u16_t httpd_fs_count +(char *name) +{ + struct httpd_fsdata_file_noconst *f; + u16_t i; + + i = 0; + for(f = (struct httpd_fsdata_file_noconst *)HTTPD_FS_ROOT; + f != NULL; + f = (struct httpd_fsdata_file_noconst *)f->next) { + + if(httpd_fs_strcmp(name, f->name) == 0) { + return count[i]; + } + ++i; + } + return 0; +} +#endif /* HTTPD_FS_STATISTICS */ +/*-----------------------------------------------------------------------------------*/ diff --git a/20080212/Demo/ARM7_LPC2368_Rowley/webserver/httpd-fs.h b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/httpd-fs.h new file mode 100644 index 000000000..b594eea56 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/httpd-fs.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: httpd-fs.h,v 1.1 2006/06/07 09:13:08 adam Exp $ + */ +#ifndef __HTTPD_FS_H__ +#define __HTTPD_FS_H__ + +#define HTTPD_FS_STATISTICS 1 + +struct httpd_fs_file { + char *data; + int len; +}; + +/* file must be allocated by caller and will be filled in + by the function. */ +int httpd_fs_open(const char *name, struct httpd_fs_file *file); + +#ifdef HTTPD_FS_STATISTICS +#if HTTPD_FS_STATISTICS == 1 +u16_t httpd_fs_count(char *name); +#endif /* HTTPD_FS_STATISTICS */ +#endif /* HTTPD_FS_STATISTICS */ + +void httpd_fs_init(void); + +#endif /* __HTTPD_FS_H__ */ diff --git a/20080212/Demo/ARM7_LPC2368_Rowley/webserver/httpd-fs/404.html b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/httpd-fs/404.html new file mode 100644 index 000000000..43e7f4cad --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/httpd-fs/404.html @@ -0,0 +1,8 @@ + + +

+

404 - file not found

+

Go here instead.

+
+ + \ No newline at end of file diff --git a/20080212/Demo/ARM7_LPC2368_Rowley/webserver/httpd-fs/index.html b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/httpd-fs/index.html new file mode 100644 index 000000000..1d3bbeee1 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/httpd-fs/index.html @@ -0,0 +1,13 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +Loading index.shtml. Click here if not automatically redirected. + + + + + diff --git a/20080212/Demo/ARM7_LPC2368_Rowley/webserver/httpd-fs/index.shtml b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/httpd-fs/index.shtml new file mode 100644 index 000000000..0ce405ba0 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/httpd-fs/index.shtml @@ -0,0 +1,20 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +RTOS Stats | TCP Stats | Connections | FreeRTOS.org Homepage | IO +

+

+

+

Task statistics

+Page will refresh evey 2 seconds.

+

Task          State  Priority  Stack	#
************************************************

+%! rtos-stats
+
+ + + + diff --git a/20080212/Demo/ARM7_LPC2368_Rowley/webserver/httpd-fs/io.shtml b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/httpd-fs/io.shtml new file mode 100644 index 000000000..0ffdbff7c --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/httpd-fs/io.shtml @@ -0,0 +1,28 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +RTOS Stats | TCP Stats | Connections | FreeRTOS.org Homepage | IO +

+

+LED and LCD IO
+ +

+ +Use the check boxes to select the LED's to turn on or off, enter text to display on the LCD, then click "Update IO". + + +

+
+%! led-io +

+ + +

+ + + + diff --git a/20080212/Demo/ARM7_LPC2368_Rowley/webserver/httpd-fs/stats.shtml b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/httpd-fs/stats.shtml new file mode 100644 index 000000000..d762f40d8 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/httpd-fs/stats.shtml @@ -0,0 +1,41 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +RTOS Stats | TCP Stats | Connections | FreeRTOS.org Homepage | IO +

+

+

+

Network statistics

+
LocalRemoteStateRetransmissionsTimerFlags
%d%u.%u.%u.%u:%u%s%u%u%c %c
+
+IP           Packets dropped
+             Packets received
+             Packets sent
+IP errors    IP version/header length
+             IP length, high byte
+             IP length, low byte
+             IP fragments
+             Header checksum
+             Wrong protocol
+ICMP	     Packets dropped
+             Packets received
+             Packets sent
+             Type errors
+TCP          Packets dropped
+             Packets received
+             Packets sent
+             Checksum errors
+             Data packets without ACKs
+             Resets
+             Retransmissions
+	     No connection avaliable
+	     Connection attempts to closed ports
+
%! net-stats
+
+ + + diff --git a/20080212/Demo/ARM7_LPC2368_Rowley/webserver/httpd-fs/tcp.shtml b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/httpd-fs/tcp.shtml new file mode 100644 index 000000000..654d61f21 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/httpd-fs/tcp.shtml @@ -0,0 +1,21 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +RTOS Stats | TCP Stats | Connections | FreeRTOS.org Homepage | IO +

+

+
+

Network connections

+

+ + +%! tcp-connections + + + + + diff --git a/20080212/Demo/ARM7_LPC2368_Rowley/webserver/httpd-fsdata.c b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/httpd-fsdata.c new file mode 100644 index 000000000..e7e29e344 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/httpd-fsdata.c @@ -0,0 +1,470 @@ +static const unsigned char data_404_html[] = { + /* /404.html */ + 0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0, + 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xd, 0xa, 0x20, 0x20, + 0x3c, 0x62, 0x6f, 0x64, 0x79, 0x20, 0x62, 0x67, 0x63, 0x6f, + 0x6c, 0x6f, 0x72, 0x3d, 0x22, 0x77, 0x68, 0x69, 0x74, 0x65, + 0x22, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x3c, 0x63, + 0x65, 0x6e, 0x74, 0x65, 0x72, 0x3e, 0xd, 0xa, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x3c, 0x68, 0x31, 0x3e, 0x34, 0x30, + 0x34, 0x20, 0x2d, 0x20, 0x66, 0x69, 0x6c, 0x65, 0x20, 0x6e, + 0x6f, 0x74, 0x20, 0x66, 0x6f, 0x75, 0x6e, 0x64, 0x3c, 0x2f, + 0x68, 0x31, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x3c, 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0x68, 0x74, 0x6d, + 0x6c, 0x22, 0x3e, 0x54, 0x43, 0x50, 0x20, 0x53, 0x74, 0x61, + 0x74, 0x73, 0x3c, 0x2f, 0x61, 0x3e, 0x20, 0x3c, 0x62, 0x3e, + 0x7c, 0x3c, 0x2f, 0x62, 0x3e, 0x20, 0x3c, 0x61, 0x20, 0x68, + 0x72, 0x65, 0x66, 0x3d, 0x22, 0x74, 0x63, 0x70, 0x2e, 0x73, + 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, 0x43, 0x6f, 0x6e, 0x6e, + 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x73, 0x3c, 0x2f, 0x61, + 0x3e, 0x20, 0x3c, 0x62, 0x3e, 0x7c, 0x3c, 0x2f, 0x62, 0x3e, + 0x20, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, + 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, + 0x2e, 0x66, 0x72, 0x65, 0x65, 0x72, 0x74, 0x6f, 0x73, 0x2e, + 0x6f, 0x72, 0x67, 0x2f, 0x22, 0x3e, 0x46, 0x72, 0x65, 0x65, + 0x52, 0x54, 0x4f, 0x53, 0x2e, 0x6f, 0x72, 0x67, 0x20, 0x48, + 0x6f, 0x6d, 0x65, 0x70, 0x61, 0x67, 0x65, 0x3c, 0x2f, 0x61, + 0x3e, 0x20, 0x3c, 0x62, 0x3e, 0x7c, 0x3c, 0x2f, 0x62, 0x3e, + 0x20, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, + 0x69, 0x6f, 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, + 0x49, 0x4f, 0x3c, 0x2f, 0x61, 0x3e, 0xd, 0xa, 0x3c, 0x62, + 0x72, 0x3e, 0x3c, 0x70, 0x3e, 0xd, 0xa, 0x3c, 0x68, 0x72, + 0x3e, 0xd, 0xa, 0x3c, 0x62, 0x72, 0x3e, 0xd, 0xa, 0x3c, + 0x68, 0x32, 0x3e, 0x4e, 0x65, 0x74, 0x77, 0x6f, 0x72, 0x6b, + 0x20, 0x63, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, + 0x6e, 0x73, 0x3c, 0x2f, 0x68, 0x32, 0x3e, 0xd, 0xa, 0x3c, + 0x70, 0x3e, 0xd, 0xa, 0x3c, 0x74, 0x61, 0x62, 0x6c, 0x65, + 0x3e, 0xd, 0xa, 0x3c, 0x74, 0x72, 0x3e, 0x3c, 0x74, 0x68, + 0x3e, 0x4c, 0x6f, 0x63, 0x61, 0x6c, 0x3c, 0x2f, 0x74, 0x68, + 0x3e, 0x3c, 0x74, 0x68, 0x3e, 0x52, 0x65, 0x6d, 0x6f, 0x74, + 0x65, 0x3c, 0x2f, 0x74, 0x68, 0x3e, 0x3c, 0x74, 0x68, 0x3e, + 0x53, 0x74, 0x61, 0x74, 0x65, 0x3c, 0x2f, 0x74, 0x68, 0x3e, + 0x3c, 0x74, 0x68, 0x3e, 0x52, 0x65, 0x74, 0x72, 0x61, 0x6e, + 0x73, 0x6d, 0x69, 0x73, 0x73, 0x69, 0x6f, 0x6e, 0x73, 0x3c, + 0x2f, 0x74, 0x68, 0x3e, 0x3c, 0x74, 0x68, 0x3e, 0x54, 0x69, + 0x6d, 0x65, 0x72, 0x3c, 0x2f, 0x74, 0x68, 0x3e, 0x3c, 0x74, + 0x68, 0x3e, 0x46, 0x6c, 0x61, 0x67, 0x73, 0x3c, 0x2f, 0x74, + 0x68, 0x3e, 0x3c, 0x2f, 0x74, 0x72, 0x3e, 0xd, 0xa, 0x25, + 0x21, 0x20, 0x74, 0x63, 0x70, 0x2d, 0x63, 0x6f, 0x6e, 0x6e, + 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x73, 0xd, 0xa, 0x3c, + 0x2f, 0x70, 0x72, 0x65, 0x3e, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, + 0x74, 0x3e, 0xd, 0xa, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, 0x74, + 0x3e, 0xd, 0xa, 0x3c, 0x2f, 0x62, 0x6f, 0x64, 0x79, 0x3e, + 0xd, 0xa, 0x3c, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xd, + 0xa, 0xd, 0xa, 0}; + +const struct httpd_fsdata_file file_404_html[] = {{NULL, data_404_html, data_404_html + 10, sizeof(data_404_html) - 10}}; + +const struct httpd_fsdata_file file_index_html[] = {{file_404_html, data_index_html, data_index_html + 12, sizeof(data_index_html) - 12}}; + +const struct httpd_fsdata_file file_index_shtml[] = {{file_index_html, data_index_shtml, data_index_shtml + 13, sizeof(data_index_shtml) - 13}}; + +const struct httpd_fsdata_file file_io_shtml[] = {{file_index_shtml, data_io_shtml, data_io_shtml + 10, sizeof(data_io_shtml) - 10}}; + +const struct httpd_fsdata_file file_stats_shtml[] = {{file_io_shtml, data_stats_shtml, data_stats_shtml + 13, sizeof(data_stats_shtml) - 13}}; + +const struct httpd_fsdata_file file_tcp_shtml[] = {{file_stats_shtml, data_tcp_shtml, data_tcp_shtml + 11, sizeof(data_tcp_shtml) - 11}}; + +#define HTTPD_FS_ROOT file_tcp_shtml + +#define HTTPD_FS_NUMFILES 6 diff --git a/20080212/Demo/ARM7_LPC2368_Rowley/webserver/httpd-fsdata.h b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/httpd-fsdata.h new file mode 100644 index 000000000..52d35c265 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/httpd-fsdata.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: httpd-fsdata.h,v 1.1 2006/06/07 09:13:08 adam Exp $ + */ +#ifndef __HTTPD_FSDATA_H__ +#define __HTTPD_FSDATA_H__ + +#include "uip.h" + +struct httpd_fsdata_file { + const struct httpd_fsdata_file *next; + const char *name; + const char *data; + const int len; +#ifdef HTTPD_FS_STATISTICS +#if HTTPD_FS_STATISTICS == 1 + u16_t count; +#endif /* HTTPD_FS_STATISTICS */ +#endif /* HTTPD_FS_STATISTICS */ +}; + +struct httpd_fsdata_file_noconst { + struct httpd_fsdata_file *next; + char *name; + char *data; + int len; +#ifdef HTTPD_FS_STATISTICS +#if HTTPD_FS_STATISTICS == 1 + u16_t count; +#endif /* HTTPD_FS_STATISTICS */ +#endif /* HTTPD_FS_STATISTICS */ +}; + +#endif /* __HTTPD_FSDATA_H__ */ diff --git a/20080212/Demo/ARM7_LPC2368_Rowley/webserver/httpd.c b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/httpd.c new file mode 100644 index 000000000..644cf16b7 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/httpd.c @@ -0,0 +1,346 @@ +/** + * \addtogroup apps + * @{ + */ + +/** + * \defgroup httpd Web server + * @{ + * The uIP web server is a very simplistic implementation of an HTTP + * server. It can serve web pages and files from a read-only ROM + * filesystem, and provides a very small scripting language. + + */ + +/** + * \file + * Web server + * \author + * Adam Dunkels + */ + + +/* + * Copyright (c) 2004, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: httpd.c,v 1.2 2006/06/11 21:46:38 adam Exp $ + */ + +#include "uip.h" +#include "httpd.h" +#include "httpd-fs.h" +#include "httpd-cgi.h" +#include "http-strings.h" + +#include + +#define STATE_WAITING 0 +#define STATE_OUTPUT 1 + +#define ISO_nl 0x0a +#define ISO_space 0x20 +#define ISO_bang 0x21 +#define ISO_percent 0x25 +#define ISO_period 0x2e +#define ISO_slash 0x2f +#define ISO_colon 0x3a + + +/*---------------------------------------------------------------------------*/ +static unsigned short +generate_part_of_file(void *state) +{ + struct httpd_state *s = (struct httpd_state *)state; + + if(s->file.len > uip_mss()) { + s->len = uip_mss(); + } else { + s->len = s->file.len; + } + memcpy(uip_appdata, s->file.data, s->len); + + return s->len; +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(send_file(struct httpd_state *s)) +{ + PSOCK_BEGIN(&s->sout); + + do { + PSOCK_GENERATOR_SEND(&s->sout, generate_part_of_file, s); + s->file.len -= s->len; + s->file.data += s->len; + } while(s->file.len > 0); + + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(send_part_of_file(struct httpd_state *s)) +{ + PSOCK_BEGIN(&s->sout); + + PSOCK_SEND(&s->sout, s->file.data, s->len); + + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +static void +next_scriptstate(struct httpd_state *s) +{ + char *p; + p = strchr(s->scriptptr, ISO_nl) + 1; + s->scriptlen -= (unsigned short)(p - s->scriptptr); + s->scriptptr = p; +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(handle_script(struct httpd_state *s)) +{ + char *ptr; + + PT_BEGIN(&s->scriptpt); + + + while(s->file.len > 0) { + + /* Check if we should start executing a script. */ + if(*s->file.data == ISO_percent && + *(s->file.data + 1) == ISO_bang) { + s->scriptptr = s->file.data + 3; + s->scriptlen = s->file.len - 3; + if(*(s->scriptptr - 1) == ISO_colon) { + httpd_fs_open(s->scriptptr + 1, &s->file); + PT_WAIT_THREAD(&s->scriptpt, send_file(s)); + } else { + PT_WAIT_THREAD(&s->scriptpt, + httpd_cgi(s->scriptptr)(s, s->scriptptr)); + } + next_scriptstate(s); + + /* The script is over, so we reset the pointers and continue + sending the rest of the file. */ + s->file.data = s->scriptptr; + s->file.len = s->scriptlen; + } else { + /* See if we find the start of script marker in the block of HTML + to be sent. */ + + if(s->file.len > uip_mss()) { + s->len = uip_mss(); + } else { + s->len = s->file.len; + } + + if(*s->file.data == ISO_percent) { + ptr = strchr(s->file.data + 1, ISO_percent); + } else { + ptr = strchr(s->file.data, ISO_percent); + } + if(ptr != NULL && + ptr != s->file.data) { + s->len = (int)(ptr - s->file.data); + if(s->len >= uip_mss()) { + s->len = uip_mss(); + } + } + PT_WAIT_THREAD(&s->scriptpt, send_part_of_file(s)); + s->file.data += s->len; + s->file.len -= s->len; + + } + } + + PT_END(&s->scriptpt); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(send_headers(struct httpd_state *s, const char *statushdr)) +{ + char *ptr; + + PSOCK_BEGIN(&s->sout); + + PSOCK_SEND_STR(&s->sout, statushdr); + + ptr = strrchr(s->filename, ISO_period); + if(ptr == NULL) { + PSOCK_SEND_STR(&s->sout, http_content_type_binary); + } else if(strncmp(http_html, ptr, 5) == 0 || + strncmp(http_shtml, ptr, 6) == 0) { + PSOCK_SEND_STR(&s->sout, http_content_type_html); + } else if(strncmp(http_css, ptr, 4) == 0) { + PSOCK_SEND_STR(&s->sout, http_content_type_css); + } else if(strncmp(http_png, ptr, 4) == 0) { + PSOCK_SEND_STR(&s->sout, http_content_type_png); + } else if(strncmp(http_gif, ptr, 4) == 0) { + PSOCK_SEND_STR(&s->sout, http_content_type_gif); + } else if(strncmp(http_jpg, ptr, 4) == 0) { + PSOCK_SEND_STR(&s->sout, http_content_type_jpg); + } else { + PSOCK_SEND_STR(&s->sout, http_content_type_plain); + } + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(handle_output(struct httpd_state *s)) +{ + char *ptr; + + PT_BEGIN(&s->outputpt); + + if(!httpd_fs_open(s->filename, &s->file)) { + httpd_fs_open(http_404_html, &s->file); + strcpy(s->filename, http_404_html); + PT_WAIT_THREAD(&s->outputpt, + send_headers(s, + http_header_404)); + PT_WAIT_THREAD(&s->outputpt, + send_file(s)); + } else { + PT_WAIT_THREAD(&s->outputpt, + send_headers(s, + http_header_200)); + ptr = strchr(s->filename, ISO_period); + if(ptr != NULL && strncmp(ptr, http_shtml, 6) == 0) { + PT_INIT(&s->scriptpt); + PT_WAIT_THREAD(&s->outputpt, handle_script(s)); + } else { + PT_WAIT_THREAD(&s->outputpt, + send_file(s)); + } + } + PSOCK_CLOSE(&s->sout); + PT_END(&s->outputpt); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(handle_input(struct httpd_state *s)) +{ + PSOCK_BEGIN(&s->sin); + + PSOCK_READTO(&s->sin, ISO_space); + + + if(strncmp(s->inputbuf, http_get, 4) != 0) { + PSOCK_CLOSE_EXIT(&s->sin); + } + PSOCK_READTO(&s->sin, ISO_space); + + if(s->inputbuf[0] != ISO_slash) { + PSOCK_CLOSE_EXIT(&s->sin); + } + + if(s->inputbuf[1] == ISO_space) { + strncpy(s->filename, http_index_html, sizeof(s->filename)); + } else { + + s->inputbuf[PSOCK_DATALEN(&s->sin) - 1] = 0; + + /* Process any form input being sent to the server. */ + { + extern void vApplicationProcessFormInput( char *pcInputString, long xInputLength ); + vApplicationProcessFormInput( s->inputbuf, PSOCK_DATALEN(&s->sin) ); + } + + strncpy(s->filename, &s->inputbuf[0], sizeof(s->filename)); + } + + /* httpd_log_file(uip_conn->ripaddr, s->filename);*/ + + s->state = STATE_OUTPUT; + + while(1) { + PSOCK_READTO(&s->sin, ISO_nl); + + if(strncmp(s->inputbuf, http_referer, 8) == 0) { + s->inputbuf[PSOCK_DATALEN(&s->sin) - 2] = 0; + /* httpd_log(&s->inputbuf[9]);*/ + } + } + + PSOCK_END(&s->sin); +} +/*---------------------------------------------------------------------------*/ +static void +handle_connection(struct httpd_state *s) +{ + handle_input(s); + if(s->state == STATE_OUTPUT) { + handle_output(s); + } +} +/*---------------------------------------------------------------------------*/ +void +httpd_appcall(void) +{ + struct httpd_state *s = (struct httpd_state *)&(uip_conn->appstate); + + if(uip_closed() || uip_aborted() || uip_timedout()) { + } else if(uip_connected()) { + PSOCK_INIT(&s->sin, s->inputbuf, sizeof(s->inputbuf) - 1); + PSOCK_INIT(&s->sout, s->inputbuf, sizeof(s->inputbuf) - 1); + PT_INIT(&s->outputpt); + s->state = STATE_WAITING; + /* timer_set(&s->timer, CLOCK_SECOND * 100);*/ + s->timer = 0; + handle_connection(s); + } else if(s != NULL) { + if(uip_poll()) { + ++s->timer; + if(s->timer >= 20) { + uip_abort(); + } + } else { + s->timer = 0; + } + handle_connection(s); + } else { + uip_abort(); + } +} +/*---------------------------------------------------------------------------*/ +/** + * \brief Initialize the web server + * + * This function initializes the web server and should be + * called at system boot-up. + */ +void +httpd_init(void) +{ + uip_listen(HTONS(80)); +} +/*---------------------------------------------------------------------------*/ +/** @} */ diff --git a/20080212/Demo/ARM7_LPC2368_Rowley/webserver/httpd.h b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/httpd.h new file mode 100644 index 000000000..7f7a6666e --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/httpd.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2001-2005, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: httpd.h,v 1.2 2006/06/11 21:46:38 adam Exp $ + * + */ + +#ifndef __HTTPD_H__ +#define __HTTPD_H__ + +#include "psock.h" +#include "httpd-fs.h" + +struct httpd_state { + unsigned char timer; + struct psock sin, sout; + struct pt outputpt, scriptpt; + char inputbuf[50]; + char filename[20]; + char state; + struct httpd_fs_file file; + int len; + char *scriptptr; + int scriptlen; + + unsigned short count; +}; + +void httpd_init(void); +void httpd_appcall(void); + +void httpd_log(char *msg); +void httpd_log_file(u16_t *requester, char *file); + +#endif /* __HTTPD_H__ */ diff --git a/20080212/Demo/ARM7_LPC2368_Rowley/webserver/makefsdata b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/makefsdata new file mode 100644 index 000000000..8d2715a8a --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/makefsdata @@ -0,0 +1,78 @@ +#!/usr/bin/perl + +open(OUTPUT, "> httpd-fsdata.c"); + +chdir("httpd-fs"); + +opendir(DIR, "."); +@files = grep { !/^\./ && !/(CVS|~)/ } readdir(DIR); +closedir(DIR); + +foreach $file (@files) { + + if(-d $file && $file !~ /^\./) { + print "Processing directory $file\n"; + opendir(DIR, $file); + @newfiles = grep { !/^\./ && !/(CVS|~)/ } readdir(DIR); + closedir(DIR); + printf "Adding files @newfiles\n"; + @files = (@files, map { $_ = "$file/$_" } @newfiles); + next; + } +} + +foreach $file (@files) { + if(-f $file) { + + print "Adding file $file\n"; + + open(FILE, $file) || die "Could not open file $file\n"; + + $file =~ s-^-/-; + $fvar = $file; + $fvar =~ s-/-_-g; + $fvar =~ s-\.-_-g; + # for AVR, add PROGMEM here + print(OUTPUT "static const unsigned char data".$fvar."[] = {\n"); + print(OUTPUT "\t/* $file */\n\t"); + for($j = 0; $j < length($file); $j++) { + printf(OUTPUT "%#02x, ", unpack("C", substr($file, $j, 1))); + } + printf(OUTPUT "0,\n"); + + + $i = 0; + while(read(FILE, $data, 1)) { + if($i == 0) { + print(OUTPUT "\t"); + } + printf(OUTPUT "%#02x, ", unpack("C", $data)); + $i++; + if($i == 10) { + print(OUTPUT "\n"); + $i = 0; + } + } + print(OUTPUT "0};\n\n"); + close(FILE); + push(@fvars, $fvar); + push(@pfiles, $file); + } +} + +for($i = 0; $i < @fvars; $i++) { + $file = $pfiles[$i]; + $fvar = $fvars[$i]; + + if($i == 0) { + $prevfile = "NULL"; + } else { + $prevfile = "file" . $fvars[$i - 1]; + } + print(OUTPUT "const struct httpd_fsdata_file file".$fvar."[] = {{$prevfile, data$fvar, "); + print(OUTPUT "data$fvar + ". (length($file) + 1) .", "); + print(OUTPUT "sizeof(data$fvar) - ". (length($file) + 1) ."}};\n\n"); +} + +print(OUTPUT "#define HTTPD_FS_ROOT file$fvars[$i - 1]\n\n"); +print(OUTPUT "#define HTTPD_FS_NUMFILES $i\n"); diff --git a/20080212/Demo/ARM7_LPC2368_Rowley/webserver/makestrings b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/makestrings new file mode 100644 index 000000000..8a13c6d29 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/makestrings @@ -0,0 +1,40 @@ +#!/usr/bin/perl + + +sub stringify { + my $name = shift(@_); + open(OUTPUTC, "> $name.c"); + open(OUTPUTH, "> $name.h"); + + open(FILE, "$name"); + + while() { + if(/(.+) "(.+)"/) { + $var = $1; + $data = $2; + + $datan = $data; + $datan =~ s/\\r/\r/g; + $datan =~ s/\\n/\n/g; + $datan =~ s/\\01/\01/g; + $datan =~ s/\\0/\0/g; + + printf(OUTPUTC "const char $var\[%d] = \n", length($datan) + 1); + printf(OUTPUTC "/* \"$data\" */\n"); + printf(OUTPUTC "{"); + for($j = 0; $j < length($datan); $j++) { + printf(OUTPUTC "%#02x, ", unpack("C", substr($datan, $j, 1))); + } + printf(OUTPUTC "};\n"); + + printf(OUTPUTH "extern const char $var\[%d];\n", length($datan) + 1); + + } + } + close(OUTPUTC); + close(OUTPUTH); +} +stringify("http-strings"); + +exit 0; + diff --git a/20080212/Demo/ARM7_LPC2368_Rowley/webserver/uIP_Task.c b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/uIP_Task.c new file mode 100644 index 000000000..b0a966e63 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/uIP_Task.c @@ -0,0 +1,318 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* uip includes. */ +#include "uip.h" +#include "uip_arp.h" +#include "httpd.h" +#include "timer.h" +#include "clock-arch.h" + +/* Demo includes. */ +#include "emac.h" +#include "partest.h" + +/*-----------------------------------------------------------*/ + +/* MAC address configuration. */ +#define uipMAC_ADDR0 0x00 +#define uipMAC_ADDR1 0x12 +#define uipMAC_ADDR2 0x13 +#define uipMAC_ADDR3 0x10 +#define uipMAC_ADDR4 0x15 +#define uipMAC_ADDR5 0x11 + +/* IP address configuration. */ +#define uipIP_ADDR0 172 +#define uipIP_ADDR1 25 +#define uipIP_ADDR2 218 +#define uipIP_ADDR3 10 + +/* How long to wait before attempting to connect the MAC again. */ +#define uipINIT_WAIT 100 + +/* Shortcut to the header within the Rx buffer. */ +#define xHeader ((struct uip_eth_hdr *) &uip_buf[ 0 ]) + +/* Standard constant. */ +#define uipTOTAL_FRAME_HEADER_SIZE 54 + +/*-----------------------------------------------------------*/ + +/* + * Send the uIP buffer to the MAC. + */ +static void prvENET_Send(void); + +/* + * Setup the MAC address in the MAC itself, and in the uIP stack. + */ +static void prvSetMACAddress( void ); + +/* + * Port functions required by the uIP stack. + */ +void clock_init( void ); +clock_time_t clock_time( void ); + +/*-----------------------------------------------------------*/ + +/* The semaphore used by the ISR to wake the uIP task. */ +extern xSemaphoreHandle xEMACSemaphore; + +/*-----------------------------------------------------------*/ + +void clock_init(void) +{ + /* This is done when the scheduler starts. */ +} +/*-----------------------------------------------------------*/ + +clock_time_t clock_time( void ) +{ + return xTaskGetTickCount(); +} +/*-----------------------------------------------------------*/ + +void vuIP_Task( void *pvParameters ) +{ +portBASE_TYPE i; +uip_ipaddr_t xIPAddr; +struct timer periodic_timer, arp_timer; +extern void ( vEMAC_ISR_Wrapper )( void ); + + /* Create the semaphore used by the ISR to wake this task. */ + vSemaphoreCreateBinary( xEMACSemaphore ); + + /* Initialise the uIP stack. */ + timer_set( &periodic_timer, configTICK_RATE_HZ / 2 ); + timer_set( &arp_timer, configTICK_RATE_HZ * 10 ); + uip_init(); + uip_ipaddr( xIPAddr, uipIP_ADDR0, uipIP_ADDR1, uipIP_ADDR2, uipIP_ADDR3 ); + uip_sethostaddr( xIPAddr ); + httpd_init(); + + /* Initialise the MAC. */ + while( Init_EMAC() != pdPASS ) + { + vTaskDelay( uipINIT_WAIT ); + } + + portENTER_CRITICAL(); + { + IntEnable = INT_RX_DONE; + VICIntEnable |= 0x00200000; + VICVectAddr21 = ( portLONG ) vEMAC_ISR_Wrapper; + prvSetMACAddress(); + } + portEXIT_CRITICAL(); + + + for( ;; ) + { + /* Is there received data ready to be processed? */ + uip_len = uiGetEMACRxData( uip_buf ); + + if( uip_len > 0 ) + { + /* Standard uIP loop taken from the uIP manual. */ + if( xHeader->type == htons( UIP_ETHTYPE_IP ) ) + { + uip_arp_ipin(); + uip_input(); + + /* If the above function invocation resulted in data that + should be sent out on the network, the global variable + uip_len is set to a value > 0. */ + if( uip_len > 0 ) + { + uip_arp_out(); + prvENET_Send(); + } + } + else if( xHeader->type == htons( UIP_ETHTYPE_ARP ) ) + { + uip_arp_arpin(); + + /* If the above function invocation resulted in data that + should be sent out on the network, the global variable + uip_len is set to a value > 0. */ + if( uip_len > 0 ) + { + prvENET_Send(); + } + } + } + else + { + if( timer_expired( &periodic_timer ) ) + { + timer_reset( &periodic_timer ); + for( i = 0; i < UIP_CONNS; i++ ) + { + uip_periodic( i ); + + /* If the above function invocation resulted in data that + should be sent out on the network, the global variable + uip_len is set to a value > 0. */ + if( uip_len > 0 ) + { + uip_arp_out(); + prvENET_Send(); + } + } + + /* Call the ARP timer function every 10 seconds. */ + if( timer_expired( &arp_timer ) ) + { + timer_reset( &arp_timer ); + uip_arp_timer(); + } + } + else + { + /* We did not receive a packet, and there was no periodic + processing to perform. Block for a fixed period. If a packet + is received during this period we will be woken by the ISR + giving us the Semaphore. */ + xSemaphoreTake( xEMACSemaphore, configTICK_RATE_HZ / 2 ); + } + } + } +} +/*-----------------------------------------------------------*/ + +static void prvENET_Send(void) +{ + RequestSend(); + + /* Copy the header into the Tx buffer. */ + CopyToFrame_EMAC( uip_buf, uipTOTAL_FRAME_HEADER_SIZE ); + if( uip_len > uipTOTAL_FRAME_HEADER_SIZE ) + { + CopyToFrame_EMAC( uip_appdata, ( uip_len - uipTOTAL_FRAME_HEADER_SIZE ) ); + } + + DoSend_EMAC( uip_len ); +} +/*-----------------------------------------------------------*/ + +static void prvSetMACAddress( void ) +{ +struct uip_eth_addr xAddr; + + /* Configure the MAC address in the uIP stack. */ + xAddr.addr[ 0 ] = uipMAC_ADDR0; + xAddr.addr[ 1 ] = uipMAC_ADDR1; + xAddr.addr[ 2 ] = uipMAC_ADDR2; + xAddr.addr[ 3 ] = uipMAC_ADDR3; + xAddr.addr[ 4 ] = uipMAC_ADDR4; + xAddr.addr[ 5 ] = uipMAC_ADDR5; + uip_setethaddr( xAddr ); +} +/*-----------------------------------------------------------*/ + +void vApplicationProcessFormInput( portCHAR *pcInputString, portBASE_TYPE xInputLength ) +{ +char *c, *pcText; +static portCHAR cMessageForDisplay[ 32 ]; +extern xQueueHandle xLCDQueue; +xLCDMessage xLCDMessage; + + /* Process the form input sent by the IO page of the served HTML. */ + + c = strstr( pcInputString, "?" ); + if( c ) + { + /* Turn LED's on or off in accordance with the check box status. */ + if( strstr( c, "LED0=1" ) != NULL ) + { + vParTestSetLED( 5, 0 ); + } + else + { + vParTestSetLED( 5, 1 ); + } + + if( strstr( c, "LED1=1" ) != NULL ) + { + vParTestSetLED( 6, 0 ); + } + else + { + vParTestSetLED( 6, 1 ); + } + + if( strstr( c, "LED2=1" ) != NULL ) + { + vParTestSetLED( 7, 0 ); + } + else + { + vParTestSetLED( 7, 1 ); + } + + /* Find the start of the text to be displayed on the LCD. */ + pcText = strstr( c, "LCD=" ); + pcText += strlen( "LCD=" ); + + /* Terminate the file name for further processing within uIP. */ + *c = 0x00; + + /* Terminate the LCD string. */ + c = strstr( pcText, " " ); + if( c != NULL ) + { + *c = 0x00; + } + + /* Add required spaces. */ + while( ( c = strstr( pcText, "+" ) ) != NULL ) + { + *c = ' '; + } + + /* Write the message to the LCD. */ + strcpy( cMessageForDisplay, pcText ); + xLCDMessage.xColumn = 0; + xLCDMessage.pcMessage = cMessageForDisplay; + xQueueSend( xLCDQueue, &xLCDMessage, portMAX_DELAY ); + } +} + diff --git a/20080212/Demo/ARM7_LPC2368_Rowley/webserver/uip-conf.h b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/uip-conf.h new file mode 100644 index 000000000..3e6f7f381 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/uip-conf.h @@ -0,0 +1,157 @@ +/** + * \addtogroup uipopt + * @{ + */ + +/** + * \name Project-specific configuration options + * @{ + * + * uIP has a number of configuration options that can be overridden + * for each project. These are kept in a project-specific uip-conf.h + * file and all configuration names have the prefix UIP_CONF. + */ + +/* + * Copyright (c) 2006, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: uip-conf.h,v 1.6 2006/06/12 08:00:31 adam Exp $ + */ + +/** + * \file + * An example uIP configuration file + * \author + * Adam Dunkels + */ + +#ifndef __UIP_CONF_H__ +#define __UIP_CONF_H__ + +#include + +/** + * 8 bit datatype + * + * This typedef defines the 8-bit type used throughout uIP. + * + * \hideinitializer + */ +typedef uint8_t u8_t; + +/** + * 16 bit datatype + * + * This typedef defines the 16-bit type used throughout uIP. + * + * \hideinitializer + */ +typedef uint16_t u16_t; + +/** + * Statistics datatype + * + * This typedef defines the dataype used for keeping statistics in + * uIP. + * + * \hideinitializer + */ +typedef unsigned short uip_stats_t; + +/** + * Maximum number of TCP connections. + * + * \hideinitializer + */ +#define UIP_CONF_MAX_CONNECTIONS 40 + +/** + * Maximum number of listening TCP ports. + * + * \hideinitializer + */ +#define UIP_CONF_MAX_LISTENPORTS 40 + +/** + * uIP buffer size. + * + * \hideinitializer + */ +#define UIP_CONF_BUFFER_SIZE 1480 + +/** + * CPU byte order. + * + * \hideinitializer + */ +#define UIP_CONF_BYTE_ORDER LITTLE_ENDIAN + +/** + * Logging on or off + * + * \hideinitializer + */ +#define UIP_CONF_LOGGING 0 + +/** + * UDP support on or off + * + * \hideinitializer + */ +#define UIP_CONF_UDP 0 + +/** + * UDP checksums on or off + * + * \hideinitializer + */ +#define UIP_CONF_UDP_CHECKSUMS 1 + +/** + * uIP statistics on or off + * + * \hideinitializer + */ +#define UIP_CONF_STATISTICS 1 + +/* Here we include the header file for the application(s) we use in + our project. */ +/*#include "smtp.h"*/ +/*#include "hello-world.h"*/ +/*#include "telnetd.h"*/ +#include "webserver.h" +/*#include "dhcpc.h"*/ +/*#include "resolv.h"*/ +/*#include "webclient.h"*/ + +#endif /* __UIP_CONF_H__ */ + +/** @} */ +/** @} */ diff --git a/20080212/Demo/ARM7_LPC2368_Rowley/webserver/webserver.h b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/webserver.h new file mode 100644 index 000000000..1acb290b8 --- /dev/null +++ b/20080212/Demo/ARM7_LPC2368_Rowley/webserver/webserver.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2002, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: webserver.h,v 1.2 2006/06/11 21:46:38 adam Exp $ + * + */ +#ifndef __WEBSERVER_H__ +#define __WEBSERVER_H__ + +#include "httpd.h" + +typedef struct httpd_state uip_tcp_appstate_t; +/* UIP_APPCALL: the name of the application function. This function + must return void and take no arguments (i.e., C type "void + appfunc(void)"). */ +#ifndef UIP_APPCALL +#define UIP_APPCALL httpd_appcall +#endif + + +#endif /* __WEBSERVER_H__ */ diff --git a/20080212/Demo/ARM7_STR71x_IAR/71x_init.s b/20080212/Demo/ARM7_STR71x_IAR/71x_init.s new file mode 100644 index 000000000..b53e1e52b --- /dev/null +++ b/20080212/Demo/ARM7_STR71x_IAR/71x_init.s @@ -0,0 +1,297 @@ +;******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** +;* File Name : 71x_init.s +;* Author : MCD Application Team +;* Date First Issued : 06/23/2004 +;* Description : This is the first code executed after RESET. +;* This code used to initialize system stacks +;* and critical peripherals before entering the C code. +;******************************************************************************* +;* History: +;* 13/01/2006 : V3.1 +;* 24/05/2005 : V3.0 +;* 30/11/2004 : V2.0 +;* 14/07/2004 : V1.3 +;* 01/01/2004 : V1.2 +;******************************************************************************* +; THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +; CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +; OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +; OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +; CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;*******************************************************************************/ + + +; --- Standard definitions of mode bits and interrupt (I & F) flags in PSRs + +Mode_USR EQU 0x10 +Mode_FIQ EQU 0x11 +Mode_IRQ EQU 0x12 +Mode_SVC EQU 0x13 +Mode_ABT EQU 0x17 +Mode_UNDEF EQU 0x1B +Mode_SYS EQU 0x1F ; available on ARM Arch 4 and later + +I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled +F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled + + + +EIC_Base_addr EQU 0xFFFFF800; EIC base address +ICR_off_addr EQU 0x00 ; Interrupt Control register offset +CIPR_off_addr EQU 0x08 ; Current Interrupt Priority Register offset +IVR_off_addr EQU 0x18 ; Interrupt Vector Register offset +FIR_off_addr EQU 0x1C ; Fast Interrupt Register offset +IER_off_addr EQU 0x20 ; Interrupt Enable Register offset +IPR_off_addr EQU 0x40 ; Interrupt Pending Bit Register offset +SIR0_off_addr EQU 0x60 ; Source Interrupt Register 0 + +EMI_Base_addr EQU 0x6C000000; EMI base address +BCON0_off_addr EQU 0x00 ; Bank 0 configuration register offset +BCON1_off_addr EQU 0x04 ; Bank 1 configuration register offset +BCON2_off_addr EQU 0x08 ; Bank 2 configuration register offset +BCON3_off_addr EQU 0x0C ; Bank 3 configuration register offset + +EMI_ENABLE EQU 0x8000 +EMI_SIZE_16 EQU 0x0001 + +GPIO2_Base_addr EQU 0xE0005000; GPIO2 base address +PC0_off_addr EQU 0x00 ; Port Configuration Register 0 offset +PC1_off_addr EQU 0x04 ; Port Configuration Register 1 offset +PC2_off_addr EQU 0x08 ; Port Configuration Register 2 offset +PD_off_addr EQU 0x0C ; Port Data Register offset + +CPM_Base_addr EQU 0xA0000040; CPM Base Address +BOOTCR_off_addr EQU 0x10 ; CPM - Boot Configuration Register +FLASH_mask EQU 0x0000 ; to remap FLASH at 0x0 +RAM_mask EQU 0x0002 ; to remap RAM at 0x0 + +;|----------------------------------------------------------------------------------| +;| - APB Bridge (System Peripheral) | +;|----------------------------------------------------------------------------------| +APB1_base_addr EQU 0xC0000000 ; APB Bridge1 Base Address +APB2_base_addr EQU 0xE0000000 ; APB Bridge2 Base Address +CKDIS_off_addr EQU 0x10 ; APB Bridge1 - Clock Disable Register +SWRES_off_addr EQU 0x14 ; APB Bridge1 - Software Reset Register +CKDIS1_config_all EQU 0x27FB ; To enable/disable clock of all APB1's peripherals +SWRES1_config_all EQU 0x27FB ; To reset all APB1's peripherals +CKDIS2_config_all EQU 0x7FDD ; To enable/disable clock of all APB2's peripherals +SWRES2_config_all EQU 0x7FDD ; To reset all APB2's peripherals + + + +;--------------------------------------------------------------- +; ?program_start +;--------------------------------------------------------------- + MODULE ?program_start + SECTION IRQ_STACK:DATA:NOROOT(3) + SECTION FIQ_STACK:DATA:NOROOT(3) + SECTION UND_STACK:DATA:NOROOT(3) + SECTION ABT_STACK:DATA:NOROOT(3) + SECTION SVC_STACK:DATA:NOROOT(3) + SECTION CSTACK:DATA:NOROOT(3) + SECTION .text:CODE(2) + PUBLIC __iar_program_start + EXTERN ?main + EXTERN ?main + CODE32 + + +;******************************************************************************* +;******* -- MACROS -- ******* +;******************************************************************************* +;******************************************************************************* +;* Macro Name : EMI_INIT +;* Description : This macro Initialize EMI bank 1: 16-bit 7 wait state +;* Input : None. +;* Output : None. +;******************************************************************************* +EMI_INIT MACRO + LDR r0, =GPIO2_Base_addr ; Configure P2.0 -> 3 in AF_PP mode + LDR r2, [r0, #PC0_off_addr] + ORR r2, r2,#0x0000000F + STR r2, [r0, #PC0_off_addr] + LDR r2, [r0, #PC1_off_addr] + ORR r2, r2,#0x0000000F + STR r2, [r0, #PC1_off_addr] + LDR r2, [r0, #PC2_off_addr] + ORR r2, r2,#0x0000000F + STR r2, [r0, #PC2_off_addr] + LDR r0, =EMI_Base_addr + LDR r1, =0x18|EMI_ENABLE|EMI_SIZE_16 + STR r1, [r0, #BCON1_off_addr] ; Enable bank 1 16-bit 7 wait state + ENDM +;******************************************************************************* +;* Macro Name : EIC_INIT +;* Description : This macro Initialize the EIC as following : +; - IRQ disabled +; - FIQ disabled +; - IVR contain the load PC opcode (0xE59FFXXX) +; - Current priority level equal to 0 +; - All channels are disabled +; - All channels priority equal to 0 +; - All SIR registers contain offset to the related IRQ +; table entry +;* Input : None. +;* Output : None. +;******************************************************************************* +EIC_INIT MACRO + + LDR r3, =EIC_Base_addr + LDR r4, =0xE59F0000 + STR r4, [r3, #IVR_off_addr]; Write the LDR pc,[pc,#offset] + ; instruction code in IVR[31:16] + LDR r2, =32 ; 32 Channel to initialize + LDR r0, =T0TIMI_Addr ; Read the address of the IRQs + ; address table + LDR r1, =0x00000FFF + AND r0,r0,r1 + LDR r5, =SIR0_off_addr ; Read SIR0 address + SUB r4,r0,#8 ; subtract 8 for prefetch + LDR r1, =0xF7E8 ; Add the offset from IVR to 0x00000000 + ; address(IVR address + 7E8 = 0x00000000) + ; 0xF7E8 used to complete the + ; LDR pc,[pc,#offset] opcode (0xE59FFXXX) + ADD r1,r4,r1 ; Compute the jump offset from IVR to the + ; IRQ table entry. +EIC_INI MOV r4, r1, LSL #16 ; Left shift the result + STR r4, [r3, r5] ; Store the result in SIRx register + ADD r1, r1, #4 ; Next IRQ address + ADD r5, r5, #4 ; Next SIR + SUBS r2, r2, #1 ; Decrement the number of SIR registers + ; to initialize + BNE EIC_INI ; If more then continue + ENDM +;******************************************************************************* +;* Macro Name : PERIPHERAL_INIT +;* Description : This macro reset all device peripherals. +;* Input : None. +;* Output : None. +;******************************************************************************* +PERIPHERAL_INIT MACRO + + LDR r1, =APB1_base_addr ; r0= APB1 base address + LDR r2, =APB2_base_addr ; r0= APB2 base address + LDR r0, =CKDIS1_config_all + STRH r0, [r1, #CKDIS_off_addr]; Clock Disabling for all APB1 peripherals + LDR r0, =CKDIS2_config_all + STRH r0, [r2, #CKDIS_off_addr]; Clock Disabling for all APB2 peripherals + LDR r0, =SWRES1_config_all + STRH r0, [r1, #SWRES_off_addr]; Keep all APB1 peripherals under reset + LDR r0, =SWRES2_config_all + STRH r0, [r2, #SWRES_off_addr]; Keep all APB2 peripherals under reset + MOV r7, #10 ; Wait that the selected macrocells exit from reset +loop1 SUBS r7, r7, #1 + BNE loop1 + MOV r0, #0 + STRH r0, [r1, #SWRES_off_addr]; Enable all all APB1 peripherals + STRH r0, [r2, #SWRES_off_addr]; Enable all all APB2 peripherals + STRH r0, [r1, #CKDIS_off_addr]; Clock Enabling for all APB1 peripherals + STRH r0, [r2, #CKDIS_off_addr]; Clock Enabling for all APB2 peripherals + MOV r7, #10 ; Wait that the selected macrocells exit from reset +loop2 SUBS r7, r7, #1 + BNE loop2 + ENDM +;******************************************************************************************** + +; define remapping +; If you need to remap memory before entring the main program +; uncomment next ligne +; #define remapping + +; Then define which memory to remap to address 0x00000000 +; Uncomment next line if you want to remap RAM +; #define remap_ram + +; Uncomment next line if you want to remap FLASH +; #define remap_flash + + + IMPORT T0TIMI_Addr +__iar_program_start + LDR pc, =NextInst +NextInst + NOP ; Wait for OSC stabilization + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + + MSR CPSR_c, #Mode_ABT|F_Bit|I_Bit + ldr sp,=SFE(ABT_STACK) ; End of ABT_STACK + + MSR CPSR_c, #Mode_UNDEF|F_Bit|I_Bit + ldr sp,=SFE(UND_STACK) ; End of UNDEF_STACK + + MSR CPSR_c, #Mode_SVC|F_Bit|I_Bit + ldr sp,=SFE(SVC_STACK) ; End of SVC_STACK + + + +; Uncomment next ligne if you need to reset all device pripherals + ; PERIPHERAL_INIT ; Reset all device peripherals + +; Uncomment next ligne if you need to enable the EMI Bank 1 + ; EMI_INIT ; Initialize EIM Bank 1 + +;Uncomment next ligne if you need to initialize the EIC + EIC_INIT ; Initialize EIC + +;****************************************************************************** +;REMAPPING +;Description : Remapping memory whether RAM,FLASH +; at Address 0x0 after the application has started executing. +; Remapping is generally done to allow RAM to replace FLASH +; at 0x0. +; the remapping of RAM allow copying of vector table into RAM +; To enable the memory remapping uncomment: (see above) +; #define remapping to enable memory remapping +; AND +; #define remap_ram to remap RAM +; OR +; #define remap_flash to remap FLASH +;****************************************************************************** +#ifdef remapping + #ifdef remap_flash + MOV r0, #FLASH_mask + #endif + #ifdef remap_ram + MOV r0, #RAM_mask + #endif + + LDR r1, =CPM_Base_addr + LDRH r2, [r1, #BOOTCR_off_addr]; Read BOOTCR Register + BIC r2, r2, #0x03 ; Reset the two LSB bits of BOOTCR + ORR r2, r2, r0 ; change the two LSB bits of BOOTCR + STRH r2, [r1, #BOOTCR_off_addr]; Write BOOTCR Register +#endif + + MSR CPSR_c, #Mode_FIQ|I_Bit; Change to FIQ mode + ldr sp,=SFE(FIQ_STACK) ; End of FIQ_STACK + + MSR CPSR_c, #Mode_IRQ|I_Bit; Change to IRQ mode + ldr sp,=SFE(IRQ_STACK) ; End of IRQ_STACK + + MSR CPSR_c, #Mode_SYS ; Change to system mode, Enable IRQ and FIQ + ldr sp,=SFE(CSTACK) ; End of CSTACK(user) + + + +; --- Now branches to a C lib function that copies RO data from their +; load region to their execute region, create the RW and ZI regions +; then jumps to user C main program. + + ; main() must be called from Supervisor mode + MSR CPSR_c, #Mode_SVC|F_Bit|I_Bit + + b ?main ; Note : use B not BL, because an application will + ; never return this way + + LTORG + + END +;******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE**** diff --git a/20080212/Demo/ARM7_STR71x_IAR/71x_vect.s b/20080212/Demo/ARM7_STR71x_IAR/71x_vect.s new file mode 100644 index 000000000..da2dd6ab8 --- /dev/null +++ b/20080212/Demo/ARM7_STR71x_IAR/71x_vect.s @@ -0,0 +1,253 @@ +#include "FreeRTOSConfig.h" +;******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** +;* File Name : 71x_vect.s +;* Author : MCD Application Team +;* Date First Issued : 16/05/2003 +;* Description : This file used to initialize the exception and IRQ +;* vectors, and to enter/return to/from exceptions handlers. +;******************************************************************************* +;* History: +;* 13/01/2006 : V3.1 +;* 24/05/2005 : V3.0 +;* 30/11/2004 : V2.0 +;* 14/07/2004 : V1.3 +;* 01/01/2004 : V1.2 +;******************************************************************************* +; THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +; CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +; OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +; OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +; CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;*******************************************************************************/ + + MODULE ?RESET + SECTION .intvec:CODE(2) + CODE32 + +EIC_base_addr EQU 0xFFFFF800; EIC base address. +CICR_off_addr EQU 0x04 ; Current Interrupt Channel Register. +IVR_off_addr EQU 0x18 ; Interrupt Vector Register. +IPR_off_addr EQU 0x40 ; Interrupt Pending Register. + + +;******************************************************************************* +; Import the __iar_program_start address from 71x_init.s +;******************************************************************************* + + IMPORT __iar_program_start + +;******************************************************************************* +; Import exception handlers +;******************************************************************************* + + IMPORT Undefined_Handler + IMPORT Prefetch_Handler + IMPORT Abort_Handler + IMPORT FIQ_Handler + +;******************************************************************************* +; Import IRQ handlers from 71x_it.c +;******************************************************************************* + + IMPORT Default_Handler + IMPORT vPortYieldProcessor + IMPORT vSerialISREntry + IMPORT vPortPreemptiveTickISR + IMPORT vPortNonPreemptiveTick + +;******************************************************************************* +; Export Peripherals IRQ handlers table address +;******************************************************************************* + + EXPORT T0TIMI_Addr + +;******************************************************************************* +; Exception vectors +;******************************************************************************* +IVR_ADDR DEFINE 0xFFFFF818 + + LDR PC, Reset_Addr + LDR PC, Undefined_Addr + LDR PC, SWI_Addr + LDR PC, Prefetch_Addr + LDR PC, Abort_Addr + NOP ; Reserved vector + LDR PC, =IVR_ADDR + LDR PC, FIQ_Addr + +;******************************************************************************* +; Exception handlers address table +;******************************************************************************* + +Reset_Addr DCD __iar_program_start +Undefined_Addr DCD UndefinedHandler +SWI_Addr DCD vPortYieldProcessor +Prefetch_Addr DCD PrefetchAbortHandler +Abort_Addr DCD DataAbortHandler + DCD 0 ; Reserved vector +IRQ_Addr DCD 0 ; Direct vectors are used. See the STR75x demo for an alternative implementation +FIQ_Addr DCD FIQHandler + +;******************************************************************************* +; Peripherals IRQ handlers address table +;******************************************************************************* + +T0TIMI_Addr DCD Default_Handler +FLASH_Addr DCD Default_Handler +RCCU_Addr DCD Default_Handler +RTC_Addr DCD Default_Handler +#if configUSE_PREEMPTION == 0 +WDG_Addr DCD vPortNonPreemptiveTick ; Tick ISR if the cooperative scheduler is used. +#else +WDG_Addr DCD vPortPreemptiveTickISR ; Tick ISR if the preemptive scheduler is used. +#endif +XTI_Addr DCD Default_Handler +USBHP_Addr DCD Default_Handler +I2C0ITERR_Addr DCD Default_Handler +I2C1ITERR_ADDR DCD Default_Handler +UART0_Addr DCD vSerialISREntry +UART1_Addr DCD Default_Handler +UART2_ADDR DCD Default_Handler +UART3_ADDR DCD Default_Handler +BSPI0_ADDR DCD Default_Handler +BSPI1_Addr DCD Default_Handler +I2C0_Addr DCD Default_Handler +I2C1_Addr DCD Default_Handler +CAN_Addr DCD Default_Handler +ADC12_Addr DCD Default_Handler +T1TIMI_Addr DCD Default_Handler +T2TIMI_Addr DCD Default_Handler +T3TIMI_Addr DCD Default_Handler + DCD 0 ; reserved + DCD 0 ; reserved + DCD 0 ; reserved +HDLC_Addr DCD Default_Handler +USBLP_Addr DCD Default_Handler + DCD 0 ; reserved + DCD 0 ; reserved +T0TOI_Addr DCD Default_Handler +T0OC1_Addr DCD Default_Handler +T0OC2_Addr DCD Default_Handler + + +;******************************************************************************* +; Exception Handlers +;******************************************************************************* + +;******************************************************************************* +;* Macro Name : SaveContext +;* Description : This macro used to save the context before entering +; an exception handler. +;* Input : The range of registers to store. +;* Output : none +;******************************************************************************* + +SaveContext MACRO reg1,reg2 + + STMFD sp!,{reg1-reg2,lr} ; Save The workspace plus the current return + ; address lr_ mode into the stack. + MRS r1,spsr ; Save the spsr_mode into r1. + STMFD sp!,{r1} ; Save spsr. + ENDM + +;******************************************************************************* +;* Macro Name : RestoreContext +;* Description : This macro used to restore the context to return from +; an exception handler and continue the program execution. +;* Input : The range of registers to restore. +;* Output : none +;******************************************************************************* + +RestoreContext MACRO reg1,reg2 + + LDMFD sp!,{r1} ; Restore the saved spsr_mode into r1. + MSR spsr_cxsf,r1 ; Restore spsr_mode. + LDMFD sp!,{reg1-reg2,pc}^; Return to the instruction following... + ; ...the exception interrupt. + ENDM + +;******************************************************************************* +;* Function Name : UndefinedHandler +;* Description : This function called when undefined instruction +; exception is entered. +;* Input : none +;* Output : none +;******************************************************************************* +UndefinedHandler + SaveContext r0,r12 ; Save the workspace plus the current + ; return address lr_ und and spsr_und. + ldr r0,=Undefined_Handler + ldr lr,=Undefined_Handler_end + bx r0 ; Branch to Undefined_Handler +Undefined_Handler_end: + RestoreContext r0,r12 ; Return to the instruction following... + ; ...the undefined instruction. + + +;******************************************************************************* +;* Function Name : PrefetchAbortHandler +;* Description : This function called when Prefetch Abort +; exception is entered. +;* Input : none +;* Output : none +;******************************************************************************* + +PrefetchAbortHandler + SUB lr,lr,#4 ; Update the link register. + SaveContext r0,r12 ; Save the workspace plus the current + ; return address lr_abt and spsr_abt. + ldr r0,=Prefetch_Handler + ldr lr,=Prefetch_Handler_end + + bx r0 ; Branch to Prefetch_Handler. +Prefetch_Handler_end: + RestoreContext r0,r12 ; Return to the instruction following that... + ; ...has generated the prefetch abort exception. + +;******************************************************************************* +;* Function Name : DataAbortHandler +;* Description : This function is called when Data Abort +; exception is entered. +;* Input : none +;* Output : none +;******************************************************************************* + +DataAbortHandler + SUB lr,lr,#8 ; Update the link register. + SaveContext r0,r12 ; Save the workspace plus the current + ; return address lr_ abt and spsr_abt. + ldr r0,=Abort_Handler + ldr lr,=Abort_Handler_end + + bx r0 ; Branch to Abort_Handler. +Abort_Handler_end: + RestoreContext r0,r12 ; Return to the instruction following that... + ; ...has generated the data abort exception. + +;******************************************************************************* +;* Function Name : FIQHandler +;* Description : This function is called when FIQ +; exception is entered. +;* Input : none +;* Output : none +;******************************************************************************* + +FIQHandler + SUB lr,lr,#4 ; Update the link register. + SaveContext r0,r7 ; Save the workspace plus the current + ; return address lr_ fiq and spsr_fiq. + ldr r0,=FIQ_Handler + ldr lr,=FIQ_Handler_end + + bx r0 ; Branch to FIQ_Handler. +FIQ_Handler_end: + RestoreContext r0,r7 ; Restore the context and return to the... + ; ...program execution. + + + + LTORG + + END +;******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE**** \ No newline at end of file diff --git a/20080212/Demo/ARM7_STR71x_IAR/FreeRTOSConfig.h b/20080212/Demo/ARM7_STR71x_IAR/FreeRTOSConfig.h new file mode 100644 index 000000000..bb3801c82 --- /dev/null +++ b/20080212/Demo/ARM7_STR71x_IAR/FreeRTOSConfig.h @@ -0,0 +1,85 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 48000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 100 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) 20480 ) +#define configMAX_TASK_NAME_LEN ( 16 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/ARM7_STR71x_IAR/Library/71x_it.c b/20080212/Demo/ARM7_STR71x_IAR/Library/71x_it.c new file mode 100644 index 000000000..cc4b2b50a --- /dev/null +++ b/20080212/Demo/ARM7_STR71x_IAR/Library/71x_it.c @@ -0,0 +1,78 @@ +/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** +* File Name : 71x_it.c +* Author : MCD Application Team +* Date First Issued : 16/05/2003 +* Description : Main Interrupt Service Routines +******************************************************************************* +* History: +* 24/05/05 : V3.0 +* 30/11/04 : V2.0 +* 16/05/03 : Created +******************************************************************************* + THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH + CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. + AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT + OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ +#include "71x_it.h" + + + u32 counter=1; +/******************************************************************************* +* Function Name : Undefined_Handler +* Description : This function handles Undefined instruction exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void Undefined_Handler(void) +{ + for( ;; ); +} + +/******************************************************************************* +* Function Name : FIQ_Handler +* Description : This function handles FIQ exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void FIQ_Handler(void) +{ + for( ;; ); +} + +/******************************************************************************* +* Function Name : Prefetch_Handler +* Description : This function handles Prefetch Abort exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void Prefetch_Handler(void) +{ + for( ;; ); +} + +/******************************************************************************* +* Function Name : Abort_Handler +* Description : This function handles Data Abort exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void Abort_Handler(void) +{ + for( ;; ); +} + +void Default_Handler( void ); +void Default_Handler( void ) +{ + for( ;; ); +} + + +/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR71x_IAR/Library/71x_lib.c b/20080212/Demo/ARM7_STR71x_IAR/Library/71x_lib.c new file mode 100644 index 000000000..53af3c5f0 --- /dev/null +++ b/20080212/Demo/ARM7_STR71x_IAR/Library/71x_lib.c @@ -0,0 +1,157 @@ +/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** +* File Name : 71x_lib.c +* Author : MCD Application Team +* Date First Issued : 05/16/2003 +* Description : Peripherals pointers initialization +******************************************************************************** +* History: +* 30/11/2004 : V2.0 +* 14/07/2004 : V1.3 +* 01/01/2004 : V1.2 +******************************************************************************* + THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH + CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. + AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT + OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ +#define EXT + +#include "71x_map.h" + +#ifdef DEBUG + +extern u32 T0TIMI_Addr; + +/******************************************************************************* +* Function Name : debug +* Description : Initialize the pointers to peripherals +* Input : none +* Output : none +* Return : none +*******************************************************************************/ +void debug(void) +{ + #ifdef _ADC12 + ADC12 = (ADC12_TypeDef *)ADC12_BASE; + #endif + + #ifdef _APB + #ifdef _APB1 + APB1 = (APB_TypeDef *)APB1_BASE; + #endif + #ifdef _APB2 + APB2 = (APB_TypeDef *)APB2_BASE; + #endif + #endif + + #ifdef _BSPI + #ifdef _BSPI0 + BSPI0 = (BSPI_TypeDef *)BSPI0_BASE; + #endif + #ifdef _BSPI1 + BSPI1 = (BSPI_TypeDef *)BSPI1_BASE; + #endif + #endif + + #ifdef _CAN + CAN = (CAN_TypeDef *)CAN_BASE; + #endif + + #ifdef _EIC + EIC = (EIC_TypeDef *)EIC_BASE; + #endif + + #ifdef _EMI + EMI = (EMI_TypeDef *)EMI_BASE; + #endif + + #ifdef _FLASH + FLASHR = (FLASHR_TypeDef *)FLASHR_BASE; + FLASHPR = (FLASHPR_TypeDef *)FLASHPR_BASE; + #endif + + #ifdef _GPIO + #ifdef _GPIO0 + GPIO0 = (GPIO_TypeDef *)GPIO0_BASE; + #endif + #ifdef _GPIO1 + GPIO1 = (GPIO_TypeDef *)GPIO1_BASE; + #endif + #ifdef _GPIO2 + GPIO2 = (GPIO_TypeDef *)GPIO2_BASE; + #endif + #endif + + #ifdef _I2C + #ifdef _I2C0 + I2C0 = (I2C_TypeDef *)I2C0_BASE; + #endif + #ifdef _I2C1 + I2C1 = (I2C_TypeDef *)I2C1_BASE; + #endif + #endif + + #ifdef _PCU + PCU = (PCU_TypeDef *)PCU_BASE; + #endif + + #ifdef _RCCU + RCCU = (RCCU_TypeDef *)RCCU_BASE; + #endif + + #ifdef _RTC + RTC = (RTC_TypeDef *)RTC_BASE; + #endif + + #ifdef _TIM + #ifdef _TIM0 + TIM0 = (TIM_TypeDef *)TIM0_BASE; + #endif + #ifdef _TIM1 + TIM1 = (TIM_TypeDef *)TIM1_BASE; + #endif + #ifdef _TIM2 + TIM2 = (TIM_TypeDef *)TIM2_BASE; + #endif + #ifdef _TIM3 + TIM3 = (TIM_TypeDef *)TIM3_BASE; + #endif + #endif + + #ifdef _UART + #ifdef _UART0 + UART0 = (UART_TypeDef *)UART0_BASE; + #endif + #ifdef _UART1 + UART1 = (UART_TypeDef *)UART1_BASE; + #endif + #ifdef _UART2 + UART2 = (UART_TypeDef *)UART2_BASE; + #endif + #ifdef _UART3 + UART3 = (UART_TypeDef *)UART3_BASE; + #endif + #endif + + #ifdef _USB + USB = (USB_TypeDef *)USB_BASE; + #endif + + #ifdef _WDG + WDG = (WDG_TypeDef *)WDG_BASE; + #endif + + #ifdef _XTI + XTI = (XTI_TypeDef *)XTI_BASE; + #endif + + #ifdef _IRQVectors + IRQVectors = (IRQVectors_TypeDef *)&T0TIMI_Addr; + #endif +} + +#endif /* DEBUG */ + +/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR71x_IAR/Library/gpio.c b/20080212/Demo/ARM7_STR71x_IAR/Library/gpio.c new file mode 100644 index 000000000..7c1bbb119 --- /dev/null +++ b/20080212/Demo/ARM7_STR71x_IAR/Library/gpio.c @@ -0,0 +1,114 @@ +/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** +* File Name : gpio.c +* Author : MCD Application Team +* Date First Issued : 06/08/2003 +* Description : This file provides all the GPIO software functions +******************************************************************************** +* History: +* 30/11/2004 : V2.0 +* 14/07/2004 : V1.3 +* 01/01/2004 : V1.2 +******************************************************************************* + THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH + CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. + AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT + OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +#include "gpio.h" + +/******************************************************************************* +* Function Name : GPIO_Config +* Description : Configure the GPIO port pins +* Input 1 : GPIOx (x can be 0,1 or 2) the desired port +* Input 2 : Port_Pins : pins placements +* Input 3 : Pins Mode +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_Config (GPIO_TypeDef *GPIOx, u16 Port_Pins, GpioPinMode_TypeDef GPIO_Mode) +{ + switch (GPIO_Mode) + { + case GPIO_HI_AIN_TRI: + GPIOx->PC0&=~Port_Pins; + GPIOx->PC1&=~Port_Pins; + GPIOx->PC2&=~Port_Pins; + break; + + case GPIO_IN_TRI_TTL: + GPIOx->PC0|=Port_Pins; + GPIOx->PC1&=~Port_Pins; + GPIOx->PC2&=~Port_Pins; + break; + + case GPIO_IN_TRI_CMOS: + GPIOx->PC0&=~Port_Pins; + GPIOx->PC1|=Port_Pins; + GPIOx->PC2&=~Port_Pins; + break; + + case GPIO_IPUPD_WP: + GPIOx->PC0|=Port_Pins; + GPIOx->PC1|=Port_Pins; + GPIOx->PC2&=~Port_Pins; + break; + + case GPIO_OUT_OD: + GPIOx->PC0&=~Port_Pins; + GPIOx->PC1&=~Port_Pins; + GPIOx->PC2|=Port_Pins; + break; + + case GPIO_OUT_PP: + GPIOx->PC0|=Port_Pins; + GPIOx->PC1&=~Port_Pins; + GPIOx->PC2|=Port_Pins; + break; + + case GPIO_AF_OD: + GPIOx->PC0&=~Port_Pins; + GPIOx->PC1|=Port_Pins; + GPIOx->PC2|=Port_Pins; + break; + + case GPIO_AF_PP: + GPIOx->PC0|=Port_Pins; + GPIOx->PC1|=Port_Pins; + GPIOx->PC2|=Port_Pins; + break; + } +} + +/******************************************************************************* +* Function Name : GPIO_BitWrite +* Description : Set or reset the selected port pin +* Input 1 : Selected GPIO port +* Input 2 : Pin number +* Input 3 : bit value +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_BitWrite(GPIO_TypeDef *GPIOx, u8 Port_Pin, u8 Port_Val) +{ + if (Port_Val&0x01) GPIOx->PD |= 1<PD &= ~(1<PD = Port_Byte ? (GPIOx->PD&0x00FF) | ((u16)Port_Val<<8) + : (GPIOx->PD&0xFF00) | Port_Val; +} + +/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR71x_IAR/Library/include/71x_conf.h b/20080212/Demo/ARM7_STR71x_IAR/Library/include/71x_conf.h new file mode 100644 index 000000000..26e5383a3 --- /dev/null +++ b/20080212/Demo/ARM7_STR71x_IAR/Library/include/71x_conf.h @@ -0,0 +1,91 @@ +/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** +* File Name : 71x_conf.h +* Author : MCD Application Team +* Date First Issued : 16/05/2003 +* Description : Library configuration for the ADC12 example +******************************************************************************** +* History: +* 16/05/2003 : Created +* 30/11/2004 : V2.0 +******************************************************************************* + THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH + CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. + AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT + OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ +#ifndef __71x_CONF_H +#define __71x_CONF_H + + +/* Comment the line below to put the library in release mode */ +//#define DEBUG + +//#define inline inline + +//#define USE_SERIAL_PORT +//#define USE_UART0 + +// Main Oscillator Frequency value = 4 Mhz +#define RCCU_Main_Osc 4000000 + +/* Comment the lines below corresponding to unwanted peripherals */ +//#define _ADC12 + +//#define _APB +//#define _APB1 +//#define _APB2 + +//#define _BSPI +//#define _BSPI0 +//#define _BSPI1 + +//#define _CAN + +//#define _EIC + +//#define _EMI + +//#define _FLASH + +#define _GPIO +#define _GPIO0 +#define _GPIO1 +#define _GPIO2 + +//#define _I2C +//#define _I2C0 +//#define _I2C1 + +#define _PCU + +#define _RCCU + +//#define _RTC + +#define _TIM +#define _TIM0 +//#define _TIM1 +//#define _TIM2 +//#define _TIM3 + +//#define _UART +//#define _UART0 +//#define _UART1 +//#define _UART2 +//#define _UART3 + +//#define _USB + +//#define _WDG + +//#define _XTI + + +//#define _IRQVectors + + +#endif /* __71x_CONF_H */ + +/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR71x_IAR/Library/include/71x_it.h b/20080212/Demo/ARM7_STR71x_IAR/Library/include/71x_it.h new file mode 100644 index 000000000..ebfc97296 --- /dev/null +++ b/20080212/Demo/ARM7_STR71x_IAR/Library/include/71x_it.h @@ -0,0 +1,61 @@ +/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** +* File Name : 71x_it.h +* Author : MCD Application Team +* Date First Issued : 05/16/2003 +* Description : Interrupt handlers +******************************************************************************** +* History: +* 30/11/2004 : V2.0 +* 14/07/2004 : V1.3 +* 01/01/2004 : V1.2 +******************************************************************************* + THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH + CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. + AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT + OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +#ifndef _71x_IT_H +#define _71x_IT_H + +#include "71x_lib.h" + + +void Undefined_Handler (void); +void FIQ_Handler (void); +void SWI_Handler (void); +void Prefetch_Handler (void); +void Abort_Handler (void); +void T0TIMI_IRQHandler (void); +void FLASH_IRQHandler (void); +void RCCU_IRQHandler (void); +void RTC_IRQHandler (void); +void WDG_IRQHandler (void); +void XTI_IRQHandler (void); +void USBHP_IRQHandler (void); +void I2C0ITERR_IRQHandler(void); +void I2C1ITERR_IRQHandler(void); +void UART0_IRQHandler (void); +void UART1_IRQHandler (void); +void UART2_IRQHandler (void); +void UART3_IRQHandler (void); +void BSPI0_IRQHandler (void); +void BSPI1_IRQHandler (void); +void I2C0_IRQHandler (void); +void I2C1_IRQHandler (void); +void CAN_IRQHandler (void); +void ADC12_IRQHandler (void); +void T1TIMI_IRQHandler (void); +void T2TIMI_IRQHandler (void); +void T3TIMI_IRQHandler (void); +void HDLC_IRQHandler (void); +void USBLP_IRQHandler (void); +void T0TOI_IRQHandler (void); +void T0OC1_IRQHandler (void); +void T0OC2_IRQHandler (void); + +#endif /* _71x_IT_H */ + +/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR71x_IAR/Library/include/71x_lib.h b/20080212/Demo/ARM7_STR71x_IAR/Library/include/71x_lib.h new file mode 100644 index 000000000..8da0d658c --- /dev/null +++ b/20080212/Demo/ARM7_STR71x_IAR/Library/include/71x_lib.h @@ -0,0 +1,99 @@ +/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** +* File Name : 71x_lib.h +* Author : MCD Application Team +* Date First Issued : 05/16/2003 +* Description : Global include for all peripherals +******************************************************************************** +* 30/11/2004 : V2.0 +* 14/07/2004 : V1.3 +* 01/01/2004 : V1.2 +******************************************************************************* + THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH + CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. + AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT + OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ +#ifndef __71x_LIB_H +#define __71x_LIB_H + +#include "71x_map.h" +#include "71x_conf.h" + + +#ifdef _ADC12 + #include "adc12.h" +#endif + +#ifdef _APB + #include "apb.h" +#endif + +#ifdef _BSPI + #include "bspi.h" +#endif + +#ifdef _CAN + #include "can.h" +#endif + +#ifdef _EIC + #include "eic.h" +#endif + +#ifdef _EMI + #include "emi.h" +#endif + +#ifdef _FLASH + #include "flash.h" +#endif + +#ifdef _GPIO + #include "gpio.h" +#endif + +#ifdef _I2C + #include "i2c.h" +#endif + +#ifdef _PCU + #include "pcu.h" +#endif + +#ifdef _RCCU + #include "rccu.h" +#endif + +#ifdef _RTC + #include "rtc.h" +#endif + +#ifdef _TIM + #include "tim.h" +#endif + +#ifdef _UART + #include "uart.h" +#endif + +#ifdef _USB +#endif + +#ifdef _WDG + #include "wdg.h" +#endif + +#ifdef _XTI + #include "xti.h" +#endif + + +#ifdef DEBUG + void debug(void); +#endif + +#endif /* __71x_LIB_H */ + +/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR71x_IAR/Library/include/71x_map.h b/20080212/Demo/ARM7_STR71x_IAR/Library/include/71x_map.h new file mode 100644 index 000000000..fe1089ece --- /dev/null +++ b/20080212/Demo/ARM7_STR71x_IAR/Library/include/71x_map.h @@ -0,0 +1,610 @@ +/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** +* File Name : 71x_map.h +* Author : MCD Application Team +* Date First Issued : 05/16/2003 +* Description : Peripherals memory mapping and registers structures +******************************************************************************** +* History: +* 30/11/2004 : V2.0 +* 14/07/2004 : V1.3 +* 01/01/2004 : V1.2 +******************************************************************************* + THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH + CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. + AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT + OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +#ifndef __71x_map_H +#define __71x_map_H + +#ifndef EXT + #define EXT extern +#endif + +#include "71x_conf.h" +#include "71x_type.h" + + +/* IP registers structures */ + +typedef volatile struct +{ + vu16 DATA0; + vu16 EMPTY1[3]; + vu16 DATA1; + vu16 EMPTY2[3]; + vu16 DATA2; + vu16 EMPTY3[3]; + vu16 DATA3; + vu16 EMPTY4[3]; + vu16 CSR; + vu16 EMPTY5[7]; + vu16 CPR; +} ADC12_TypeDef; + +typedef volatile struct +{ + vu32 CKDIS; + vu32 SWRES; +} APB_TypeDef; + +typedef volatile struct +{ + vu16 RXR; + vu16 EMPTY1; + vu16 TXR; + vu16 EMPTY2; + vu16 CSR1; + vu16 EMPTY3; + vu16 CSR2; + vu16 EMPTY4; + vu16 CLK; +} BSPI_TypeDef; + +typedef volatile struct +{ + vu16 CRR; + vu16 EMPTY1; + vu16 CMR; + vu16 EMPTY2; + vu16 M1R; + vu16 EMPTY3; + vu16 M2R; + vu16 EMPTY4; + vu16 A1R; + vu16 EMPTY5; + vu16 A2R; + vu16 EMPTY6; + vu16 MCR; + vu16 EMPTY7; + vu16 DA1R; + vu16 EMPTY8; + vu16 DA2R; + vu16 EMPTY9; + vu16 DB1R; + vu16 EMPTY10; + vu16 DB2R; + vu16 EMPTY11[27]; +} CAN_MsgObj_TypeDef; + +typedef volatile struct +{ + vu16 CR; + vu16 EMPTY1; + vu16 SR; + vu16 EMPTY2; + vu16 ERR; + vu16 EMPTY3; + vu16 BTR; + vu16 EMPTY4; + vu16 IDR; + vu16 EMPTY5; + vu16 TESTR; + vu16 EMPTY6; + vu16 BRPR; + vu16 EMPTY7[3]; + CAN_MsgObj_TypeDef sMsgObj[2]; + vu16 EMPTY8[16]; + vu16 TR1R; + vu16 EMPTY9; + vu16 TR2R; + vu16 EMPTY10[13]; + vu16 ND1R; + vu16 EMPTY11; + vu16 ND2R; + vu16 EMPTY12[13]; + vu16 IP1R; + vu16 EMPTY13; + vu16 IP2R; + vu16 EMPTY14[13]; + vu16 MV1R; + vu16 EMPTY15; + vu16 MV2R; + vu16 EMPTY16; +} CAN_TypeDef; + +typedef volatile struct +{ + vu32 ICR; + vu32 CICR; + vu32 CIPR; + vu32 EMPTY1[3]; + vu32 IVR; + vu32 FIR; + vu32 IER; + vu32 EMPTY2[7]; + vu32 IPR; + vu32 EMPTY3[7]; + vu32 SIR[32]; +} EIC_TypeDef; + +typedef volatile struct +{ + vu16 BCON0; + vu16 EMPTY1; + vu16 BCON1; + vu16 EMPTY2; + vu16 BCON2; + vu16 EMPTY3; + vu16 BCON3; + vu16 EMPTY4; +} EMI_TypeDef; + +typedef volatile struct +{ + vu32 CR0; + vu32 CR1; + vu32 DR0; + vu32 DR1; + vu32 AR; + vu32 ER; +} FLASHR_TypeDef; + +typedef volatile struct +{ + vu32 NVWPAR; + vu32 EMPTY; + vu32 NVAPR0; + vu32 NVAPR1; +} FLASHPR_TypeDef; + +typedef volatile struct +{ + vu16 PC0; + vu16 EMPTY1; + vu16 PC1; + vu16 EMPTY2; + vu16 PC2; + vu16 EMPTY3; + vu16 PD; + vu16 EMPTY4; +} GPIO_TypeDef; + +typedef volatile struct +{ + vu8 CR; + vu8 EMPTY1[3]; + vu8 SR1; + vu8 EMPTY2[3]; + vu8 SR2; + vu8 EMPTY3[3]; + vu8 CCR; + vu8 EMPTY4[3]; + vu8 OAR1; + vu8 EMPTY5[3]; + vu8 OAR2; + vu8 EMPTY6[3]; + vu8 DR; + vu8 EMPTY7[3]; + vu8 ECCR; +} I2C_TypeDef; + +typedef volatile struct +{ + vu32 CCR; + vu32 EMPTY1; + vu32 CFR; + vu32 EMPTY2[3]; + vu32 PLL1CR; + vu32 PER; + vu32 SMR; +} RCCU_TypeDef; + +typedef volatile struct +{ + vu16 MDIVR; + vu16 EMPTY1; + vu16 PDIVR; + vu16 EMPTY2; + vu16 RSTR; + vu16 EMPTY3; + vu16 PLL2CR; + vu16 EMPTY4; + vu16 BOOTCR; + vu16 EMPTY5; + vu16 PWRCR; +} PCU_TypeDef; + +typedef volatile struct +{ + vu16 CRH; + vu16 EMPTY1; + vu16 CRL; + vu16 EMPTY2; + vu16 PRLH; + vu16 EMPTY3; + vu16 PRLL; + vu16 EMPTY4; + vu16 DIVH; + vu16 EMPTY5; + vu16 DIVL; + vu16 EMPTY6; + vu16 CNTH; + vu16 EMPTY7; + vu16 CNTL; + vu16 EMPTY8; + vu16 ALRH; + vu16 EMPTY9; + vu16 ALRL; +} RTC_TypeDef; + +typedef volatile struct +{ + vu16 ICAR; + vu16 EMPTY1; + vu16 ICBR; + vu16 EMPTY2; + vu16 OCAR; + vu16 EMPTY3; + vu16 OCBR; + vu16 EMPTY4; + vu16 CNTR; + vu16 EMPTY5; + vu16 CR1; + vu16 EMPTY6; + vu16 CR2; + vu16 EMPTY7; + vu16 SR; +} TIM_TypeDef; + +typedef volatile struct +{ + vu16 BR; + vu16 EMPTY1; + vu16 TxBUFR; + vu16 EMPTY2; + vu16 RxBUFR; + vu16 EMPTY3; + vu16 CR; + vu16 EMPTY4; + vu16 IER; + vu16 EMPTY5; + vu16 SR; + vu16 EMPTY6; + vu16 GTR; + vu16 EMPTY7; + vu16 TOR; + vu16 EMPTY8; + vu16 TxRSTR; + vu16 EMPTY9; + vu16 RxRSTR; +} UART_TypeDef; + +typedef volatile struct +{ + vu32 EP0R; + vu32 EP1R; + vu32 EP2R; + vu32 EP3R; + vu32 EP4R; + vu32 EP5R; + vu32 EP6R; + vu32 EP7R; + vu32 EP8R; + vu32 EP9R; + vu32 EP10R; + vu32 EP11R; + vu32 EP12R; + vu32 EP13R; + vu32 EP14R; + vu32 EP15R; + vu32 CNTR; + vu32 ISTR; + vu32 FNR; + vu32 DADDR; + vu32 BTABLE; +} USB_TypeDef; + +typedef volatile struct +{ + vu16 CR; + vu16 EMPTY1; + vu16 PR; + vu16 EMPTY2; + vu16 VR; + vu16 EMPTY3; + vu16 CNT; + vu16 EMPTY4; + vu16 SR; + vu16 EMPTY5; + vu16 MR; + vu16 EMPTY6; + vu16 KR; +} WDG_TypeDef; + +typedef volatile struct +{ + vu8 SR; + vu8 EMPTY1[7]; + vu8 CTRL; + vu8 EMPTY2[3]; + vu8 MRH; + vu8 EMPTY3[3]; + vu8 MRL; + vu8 EMPTY4[3]; + vu8 TRH; + vu8 EMPTY5[3]; + vu8 TRL; + vu8 EMPTY6[3]; + vu8 PRH; + vu8 EMPTY7[3]; + vu8 PRL; +} XTI_TypeDef; + + +/* IRQ vectors */ +typedef volatile struct +{ + vu32 T0TIMI_IRQHandler; + vu32 FLASH_IRQHandler; + vu32 RCCU_IRQHandler; + vu32 RTC_IRQHandler; + vu32 WDG_IRQHandler; + vu32 XTI_IRQHandler; + vu32 USBHP_IRQHandler; + vu32 I2C0ITERR_IRQHandler; + vu32 I2C1ITERR_IRQHandler; + vu32 UART0_IRQHandler; + vu32 UART1_IRQHandler; + vu32 UART2_IRQHandler; + vu32 UART3_IRQHandler; + vu32 BSPI0_IRQHandler; + vu32 BSPI1_IRQHandler; + vu32 I2C0_IRQHandler; + vu32 I2C1_IRQHandler; + vu32 CAN_IRQHandler; + vu32 ADC12_IRQHandler; + vu32 T1TIMI_IRQHandler; + vu32 T2TIMI_IRQHandler; + vu32 T3TIMI_IRQHandler; + vu32 EMPTY1[3]; + vu32 HDLC_IRQHandler; + vu32 USBLP_IRQHandler; + vu32 EMPTY2[2]; + vu32 T0TOI_IRQHandler; + vu32 T0OC1_IRQHandler; + vu32 T0OC2_IRQHandler; +} IRQVectors_TypeDef; + +/*===================================================================*/ + +/* Memory mapping */ + +#define RAM_BASE 0x20000000 + +#define FLASHR_BASE 0x40100000 +#define FLASHPR_BASE 0x4010DFB0 + +#define EXTMEM_BASE 0x60000000 +#define RCCU_BASE 0xA0000000 +#define PCU_BASE 0xA0000040 +#define APB1_BASE 0xC0000000 +#define APB2_BASE 0xE0000000 +#define EIC_BASE 0xFFFFF800 + +#define I2C0_BASE (APB1_BASE + 0x1000) +#define I2C1_BASE (APB1_BASE + 0x2000) +#define UART0_BASE (APB1_BASE + 0x4000) +#define UART1_BASE (APB1_BASE + 0x5000) +#define UART2_BASE (APB1_BASE + 0x6000) +#define UART3_BASE (APB1_BASE + 0x7000) +#define CAN_BASE (APB1_BASE + 0x9000) +#define BSPI0_BASE (APB1_BASE + 0xA000) +#define BSPI1_BASE (APB1_BASE + 0xB000) +#define USB_BASE (APB1_BASE + 0x8800) + +#define XTI_BASE (APB2_BASE + 0x101C) +#define GPIO0_BASE (APB2_BASE + 0x3000) +#define GPIO1_BASE (APB2_BASE + 0x4000) +#define GPIO2_BASE (APB2_BASE + 0x5000) +#define ADC12_BASE (APB2_BASE + 0x7000) +#define TIM0_BASE (APB2_BASE + 0x9000) +#define TIM1_BASE (APB2_BASE + 0xA000) +#define TIM2_BASE (APB2_BASE + 0xB000) +#define TIM3_BASE (APB2_BASE + 0xC000) +#define RTC_BASE (APB2_BASE + 0xD000) +#define WDG_BASE (APB2_BASE + 0xE000) + +#define EMI_BASE (EXTMEM_BASE + 0x0C000000) + +/*===================================================================*/ + +/* IP data access */ + +#ifndef DEBUG + #define ADC12 ((ADC12_TypeDef *)ADC12_BASE) + + #define APB1 ((APB_TypeDef *)APB1_BASE) + #define APB2 ((APB_TypeDef *)APB2_BASE+0x10) + + #define BSPI0 ((BSPI_TypeDef *)BSPI0_BASE) + #define BSPI1 ((BSPI_TypeDef *)BSPI1_BASE) + + #define CAN ((CAN_TypeDef *)CAN_BASE) + + #define EIC ((EIC_TypeDef *)EIC_BASE) + + #define EMI ((EMI_TypeDef *)EMI_BASE) + + #define FLASHR ((FLASHR_TypeDef *)FLASHR_BASE) + #define FLASHPR ((FLASHPR_TypeDef *)FLASHPR_BASE) + + #define GPIO0 ((GPIO_TypeDef *)GPIO0_BASE) + #define GPIO1 ((GPIO_TypeDef *)GPIO1_BASE) + #define GPIO2 ((GPIO_TypeDef *)GPIO2_BASE) + + #define I2C0 ((I2C_TypeDef *)I2C0_BASE) + #define I2C1 ((I2C_TypeDef *)I2C1_BASE) + + #define PCU ((PCU_TypeDef *)PCU_BASE) + + #define RCCU ((RCCU_TypeDef *)RCCU_BASE) + + #define RTC ((RTC_TypeDef *)RTC_BASE) + + #define TIM0 ((TIM_TypeDef *)TIM0_BASE) + #define TIM1 ((TIM_TypeDef *)TIM1_BASE) + #define TIM2 ((TIM_TypeDef *)TIM2_BASE) + #define TIM3 ((TIM_TypeDef *)TIM3_BASE) + + #define UART0 ((UART_TypeDef *)UART0_BASE) + #define UART1 ((UART_TypeDef *)UART1_BASE) + #define UART2 ((UART_TypeDef *)UART2_BASE) + #define UART3 ((UART_TypeDef *)UART3_BASE) + + #define USB ((USB_TypeDef *)USB_BASE) + + #define WDG ((WDG_TypeDef *)WDG_BASE) + + #define XTI ((XTI_TypeDef *)XTI_BASE) + + #define IRQVectors ((IRQVectors_TypeDef *)&T0TIMI_Addr) + +#else /* DEBUG */ + + #ifdef _ADC12 + EXT ADC12_TypeDef *ADC12; + #endif + + #ifdef _APB + #ifdef _APB1 + EXT APB_TypeDef *APB1; + #endif + #ifdef _APB2 + EXT APB_TypeDef *APB2; + #endif + #endif + + #ifdef _BSPI + #ifdef _BSPI0 + EXT BSPI_TypeDef *BSPI0; + #endif + #ifdef _BSPI1 + EXT BSPI_TypeDef *BSPI1; + #endif + #endif + + #ifdef _CAN + EXT CAN_TypeDef *CAN; + #endif + + #ifdef _EIC + EXT EIC_TypeDef *EIC; + #endif + + #ifdef _EMI + EXT EMI_TypeDef *EMI; + #endif + + #ifdef _FLASH + EXT FLASHR_TypeDef *FLASHR; + EXT FLASHPR_TypeDef *FLASHPR; + #endif + + #ifdef _GPIO + #ifdef _GPIO0 + EXT GPIO_TypeDef *GPIO0; + #endif + #ifdef _GPIO1 + EXT GPIO_TypeDef *GPIO1; + #endif + #ifdef _GPIO2 + EXT GPIO_TypeDef *GPIO2; + #endif + #endif + + #ifdef _I2C + #ifdef _I2C0 + EXT I2C_TypeDef *I2C0; + #endif + #ifdef _I2C1 + EXT I2C_TypeDef *I2C1; + #endif + #endif + + #ifdef _PCU + EXT PCU_TypeDef *PCU; + #endif + + #ifdef _RCCU + EXT RCCU_TypeDef *RCCU; + #endif + + #ifdef _RTC + EXT RTC_TypeDef *RTC; + #endif + + #ifdef _TIM + #ifdef _TIM0 + EXT TIM_TypeDef *TIM0; + #endif + #ifdef _TIM1 + EXT TIM_TypeDef *TIM1; + #endif + #ifdef _TIM2 + EXT TIM_TypeDef *TIM2; + #endif + #ifdef _TIM3 + EXT TIM_TypeDef *TIM3; + #endif + #endif + + #ifdef _UART + #ifdef _UART0 + EXT UART_TypeDef *UART0; + #endif + #ifdef _UART1 + EXT UART_TypeDef *UART1; + #endif + #ifdef _UART2 + EXT UART_TypeDef *UART2; + #endif + #ifdef _UART3 + EXT UART_TypeDef *UART3; + #endif + #endif + + #ifdef _USB + EXT USB_TypeDef *USB; + #endif + + #ifdef _WDG + EXT WDG_TypeDef *WDG; + #endif + + #ifdef _XTI + EXT XTI_TypeDef *XTI; + #endif + + #ifdef _IRQVectors + EXT IRQVectors_TypeDef *IRQVectors; + #endif + +#endif /* DEBUG */ + +#endif /* __71x_map_H */ + +/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR71x_IAR/Library/include/71x_type.h b/20080212/Demo/ARM7_STR71x_IAR/Library/include/71x_type.h new file mode 100644 index 000000000..39e2175f2 --- /dev/null +++ b/20080212/Demo/ARM7_STR71x_IAR/Library/include/71x_type.h @@ -0,0 +1,50 @@ +/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** +* File Name : 71x_type.h +* Author : MCD Application Team +* Date First Issued : 05/16/2003 +* Description : Common data types +******************************************************************************** +* History: +* 30/11/2004 : V2.0 +* 14/07/2004 : V1.3 +* 01/01/2004 : V1.2 +******************************************************************************* + THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH + CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. + AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT + OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ +#ifndef _71x_type_H +#define _71x_type_H + +typedef unsigned long u32; +typedef unsigned short u16; +typedef unsigned char u8; + +typedef signed long s32; +typedef signed short s16; +typedef signed char s8; + +typedef volatile unsigned long vu32; +typedef volatile unsigned short vu16; +typedef volatile unsigned char vu8; + +typedef volatile signed long vs32; +typedef volatile signed short vs16; +typedef volatile signed char vs8; + +/*===================================================================*/ +typedef enum { FALSE = 0, TRUE = !FALSE } bool; +/*===================================================================*/ +typedef enum { RESET = 0, SET = !RESET } FlagStatus; +/*===================================================================*/ +typedef enum { DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +/*===================================================================*/ +typedef enum { INDIRECT = 0, DIRECT = !INDIRECT} RegisterAccess; +/*===================================================================*/ + +#endif /* _71x_type_H */ + +/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR71x_IAR/Library/include/eic.h b/20080212/Demo/ARM7_STR71x_IAR/Library/include/eic.h new file mode 100644 index 000000000..cbe149b56 --- /dev/null +++ b/20080212/Demo/ARM7_STR71x_IAR/Library/include/eic.h @@ -0,0 +1,199 @@ +/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** +* File Name : eic.h +* Author : MCD Application Team +* Date First Issued : 25/06/2003 +* Description : This file contains all the functions prototypes for the +* EIC software library. +******************************************************************************** +* History: +* 30/11/2004 : V2.0 +* 14/07/2004 : V1.3 +* 01/01/2004 : V1.2 +******************************************************************************* + THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH + CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. + AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT + OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ +#ifndef __eic_H +#define __eic_H + +#include "71x_map.h" + +typedef enum +{ + T0TIMI_IRQChannel = 0, + FLASH_IRQChannel = 1, + RCCU_IRQChannel = 2, + RTC_IRQChannel = 3, + WDG_IRQChannel = 4, + XTI_IRQChannel = 5, + USBHP_IRQChannel = 6, + I2C0ITERR_IRQChannel = 7, + I2C1ITERR_IRQChannel = 8, + UART0_IRQChannel = 9, + UART1_IRQChannel = 10, + UART2_IRQChannel = 11, + UART3_IRQChannel = 12, + SPI0_IRQChannel = 13, + SPI1_IRQChannel = 14, + I2C0_IRQChannel = 15, + I2C1_IRQChannel = 16, + CAN_IRQChannel = 17, + ADC_IRQChannel = 18, + T1TIMI_IRQChannel = 19, + T2TIMI_IRQChannel = 20, + T3TIMI_IRQChannel = 21, + HDLC_IRQChannel = 25, + USBLP_IRQChannel = 26, + T0TOI_IRQChannel = 29, + T0OC1_IRQChannel = 30, + T0OC2_IRQChannel = 31 +} IRQChannel_TypeDef; + +typedef enum +{ + T0TIMI_FIQChannel = 0x00000001, + WDG_FIQChannel = 0x00000002, + WDGT0TIMI_FIQChannels = 0x00000003 +} FIQChannel_TypeDef; + +/******************************************************************************* +* Function Name : EIC_Init +* Description : Initialise the EIC using the load PC instruction +* (PC = PC +offset) +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void EIC_Init(void); + +/******************************************************************************* +* Function Name : EIC_IRQConfig +* Description : Enable or Disable IRQ interrupts +* Input 1 : New status : can be ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +inline void EIC_IRQConfig(FunctionalState NewState) +{ + if (NewState==ENABLE) EIC->ICR |= 0x0001; else EIC->ICR &= ~0x0001; +} + +/******************************************************************************* +* Function Name : EIC_FIQConfig +* Description : Enable or Disable FIQ interrupts +* Input 1 : New status : can be ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +inline void EIC_FIQConfig(FunctionalState NewState) +{ + if (NewState==ENABLE) EIC->ICR |= 0x0002; else EIC->ICR &= ~0x0002; +} + +/******************************************************************************* +* Function Name : EIC_IRQChannelConfig +* Description : Configure the IRQ Channel +* Input 1 : IRQ channel name +* Input 2 : Channel New status : can be ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +inline void EIC_IRQChannelConfig(IRQChannel_TypeDef IRQChannel, FunctionalState NewState) +{ + if (NewState==ENABLE) EIC->IER |= 0x0001 << IRQChannel; + else EIC->IER &= ~(0x0001 << IRQChannel); +} + +/******************************************************************************* +* Function Name : EIC_FIQChannelConfig +* Description : Configure the FIQ Channel +* Input 1 : FIQ channel name +* Input 2 : Channel New status : can be ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +inline void EIC_FIQChannelConfig(FIQChannel_TypeDef FIQChannel, + FunctionalState NewState) +{ + if (NewState==ENABLE) EIC->FIR |= FIQChannel; + else EIC->FIR &= ~FIQChannel; +} + +/******************************************************************************* +* Function Name : EIC_IRQChannelPriorityConfig +* Description : Configure the selected IRQ channel priority +* Input 1 : IRQ channel name +* Input 2 : IRQ channel priority +* Output : None +* Return : None +*******************************************************************************/ +inline void EIC_IRQChannelPriorityConfig(IRQChannel_TypeDef IRQChannel, u8 Priority) +{ + EIC->SIR[IRQChannel] = (EIC->SIR[IRQChannel]&0xFFFF0000) | (u16)Priority & 0x000F; +} + +/******************************************************************************* +* Function Name : EIC_CurrentPriorityLevelConfig +* Description : Change the current priority level of the srved IRQ routine +* Input 1 : New priority +* Output : None +* Return : None +*******************************************************************************/ +void EIC_CurrentPriorityLevelConfig(u8 NewPriorityLevel); + +/******************************************************************************* +* Function Name : EIC_CurrentPriorityLevelValue +* Description : Return the current priority level of the current served IRQ +* routine +* Input : None +* Output : None +* Return : The current priority level +*******************************************************************************/ +inline u8 EIC_CurrentPriorityLevelValue(void) +{ + return EIC->CIPR & 0xF; +} + +/******************************************************************************* +* Function Name : EIC_CurrentIRQChannelValue +* Description : Return the current served IRQ channel number +* Input 0 : None +* Output : None +* Return : The current served IRQ channel number +*******************************************************************************/ +inline IRQChannel_TypeDef EIC_CurrentIRQChannelValue(void) +{ + return (IRQChannel_TypeDef)(EIC->CICR & 0x1F); +} + +/******************************************************************************* +* Function Name : EIC_CurrentFIQChannelValue +* Description : Return the current served FIQ channel number +* Input : None +* Output : None +* Return : The current served FIQ channel number +*******************************************************************************/ +inline FIQChannel_TypeDef EIC_CurrentFIQChannelValue(void) +{ + return (FIQChannel_TypeDef)((EIC->FIR >> 2) & 0x0003); +} + +/******************************************************************************* +* Function Name : EIC_FIPendingBitClear +* Description : Clear the FIQ pending bit +* Input 1 : FIQ channel +* Output : None +* Return : None +*******************************************************************************/ +inline void EIC_FIQPendingBitClear(FIQChannel_TypeDef FIQChannel) +{ + EIC->FIR = (EIC->FIR & 0x0003) | (FIQChannel << 2); +} + +#endif /* __eic_H */ + +/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR71x_IAR/Library/include/gpio.h b/20080212/Demo/ARM7_STR71x_IAR/Library/include/gpio.h new file mode 100644 index 000000000..2ea6decf6 --- /dev/null +++ b/20080212/Demo/ARM7_STR71x_IAR/Library/include/gpio.h @@ -0,0 +1,126 @@ +/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** +* File Name : gpio.h +* Author : MCD Application Team +* Date First Issued : 08/06/2003 +* Description : This file contains all the functions prototypes for the +* GPIO software library. +******************************************************************************** +* History: +* 30/11/2004 : V2.0 +* 14/07/2004 : V1.3 +* 01/01/2004 : V1.2 +******************************************************************************* + THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH + CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. + AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT + OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ +#ifndef __gpio_H +#define __gpio_H + +#include "71x_map.h" + +typedef enum +{ + GPIO_HI_AIN_TRI, + GPIO_IN_TRI_TTL, + GPIO_IN_TRI_CMOS, + GPIO_IPUPD_WP, + GPIO_OUT_OD, + GPIO_OUT_PP, + GPIO_AF_OD, + GPIO_AF_PP +} GpioPinMode_TypeDef; + +#define GPIO_LSB 0x00 +#define GPIO_MSB 0x08 + +/******************************************************************************* +* Function Name : GPIO_Config +* Description : Configure the GPIO port pins +* Input 1 : GPIOx (x can be 0,1 or 2) the desired port +* Input 2 : Port_Pins : pins placements +* Input 3 : Pins Mode +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_Config (GPIO_TypeDef *GPIOx, u16 Port_Pins, GpioPinMode_TypeDef GPIO_Mode); + +/******************************************************************************* +* Function Name : GPIO_BitRead +* Description : Read the desired port pin value +* Input 1 : Selected GPIO port +* Input 2 : Pin number +* Output : None +* Return : The selected pin value +*******************************************************************************/ +inline u8 GPIO_BitRead(GPIO_TypeDef *GPIOx, u8 Port_Pin) +{ + return (GPIOx->PD >> Port_Pin) & 0x0001; +} + +/******************************************************************************* +* Function Name : GPIO_ByteRead +* Description : Read the desired port Byte value +* Input 1 : Selected GPIO port +* Input 2 : GPIO_MSB or GPIO_LSB +* Output : None +* Return : The GPIO_MSB or GPIO_LSB of the selected PD register +*******************************************************************************/ +inline u8 GPIO_ByteRead(GPIO_TypeDef *GPIOx, u8 Port_Byte) +{ + return (u8)(GPIOx->PD >> Port_Byte); +} + +/******************************************************************************* +* Function Name : GPIO_WordRead +* Description : Read the desired port word value +* Input 1 : Selected GPIO port +* Output : None +* Return : The selected PD register value +*******************************************************************************/ +inline u16 GPIO_WordRead(GPIO_TypeDef *GPIOx) +{ + return GPIOx->PD; +} + +/******************************************************************************* +* Function Name : GPIO_BitWrite +* Description : Set or reset the selected port pin +* Input 1 : Selected GPIO port +* Input 2 : Pin number +* Input 3 : bit value +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_BitWrite(GPIO_TypeDef *GPIOx, u8 Port_Pin, u8 Port_Val); + +/******************************************************************************* +* Function Name : GPIO_ByteWrite +* Description : Write byte value to the selected PD register +* Input 1 : Selected GPIO port +* Input 2 : GPIO_MSB or GPIO_LSB +* Input 3 : Byte value +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_ByteWrite(GPIO_TypeDef *GPIOx, u8 Port_Byte, u8 Port_Val); + +/******************************************************************************* +* Function Name : GPIO_WordWrite +* Description : Write word value to the selected PD register +* Input 1 : Selected GPIO port +* Input 2 : Value +* Output : None +* Return : None +*******************************************************************************/ +inline void GPIO_WordWrite(GPIO_TypeDef *GPIOx, u16 Port_Val) +{ + GPIOx->PD = Port_Val; +} + +#endif /* __gpio_H */ + +/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR71x_IAR/Library/include/pcu.h b/20080212/Demo/ARM7_STR71x_IAR/Library/include/pcu.h new file mode 100644 index 000000000..b36296330 --- /dev/null +++ b/20080212/Demo/ARM7_STR71x_IAR/Library/include/pcu.h @@ -0,0 +1,193 @@ +/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** +* File Name : pcu.h +* Author : MCD Application Team +* Date First Issued : 30/05/2003 +* Description : This file contains all the functions prototypes for the +* PCU software library. +******************************************************************************** +* History: +* 30/11/2004 : V2.0 +* 14/07/2004 : V1.3 +* 01/01/2004 : V1.2 +******************************************************************************* + THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH + CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. + AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT + OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ +#ifndef __PCU_H +#define __PCU_H + +#include "71x_map.h" + +typedef enum +{ + PCU_WREN = 0x8000, + PCU_VROK = 0x1000 +} PCU_Flags; + +typedef enum +{ + PCU_STABLE, + PCU_UNSTABLE +} PCU_VR_Status; + +typedef enum +{ + PCU_MVR = 0x0008, + PCU_LPR = 0x0020 +} PCU_VR; + +typedef enum +{ + WFI_CLOCK2_16, + WFI_EXTERNAL +} WFI_CLOCKS; + +typedef enum +{ + PCU_SLOW, + PCU_STOP, + PCU_STANDBY +} LPM_MODES; + + +// VR_OK : Voltage Regulator OK +#define PCU_VROK_Mask 0x1000 + +// Main Voltage Regulator +#define PCU_MVR_Mask 0x0008 + +// Low Power Voltage Regulator +#define PCU_LPR_Mask 0x0020 + +// PCU register Write Enable Bit +#define PCU_WREN_Mask 0x8000 + +// Low Voltage Detector +#define PCU_LVD_Mask 0x0100 + +// Power Down Flag +#define PCU_PWRDWN_Mask 0x0040 + +// WFI Mode Clock Selection Bit +#define PCU_WFI_CKSEL_Mask 0x00000002 + +// Halt Mode Enable Bit +#define PCU_EN_HALT_Mask 0x00000800 + +// Halt Mode Flag +#define PCU_HALT_Mask 0x0002 + +// Stop Mode Enable Bit +#define PCU_STOP_EN_Mask 0x00000400 + +// Low Power Regulator in Wait For interrupt Mode +#define PCU_LPRWFI_Mask 0x0020 + +// Low Power Mode in Wait For interrupt Mode +#define PCU_LPOWFI_Mask 0x00000001 + +// Software Reset Enable +#define PCU_SRESEN_Mask 0x00000001 + + +/******************************************************************************* +* Function Name : PCU_MVRStatus +* Description : This routine is used to check the Main Voltage Regulator +* : NewState. +* Input : None +* Return : STABLE, UNSTABLE +*******************************************************************************/ +inline PCU_VR_Status PCU_MVRStatus ( void ) +{ + return (PCU->PWRCR & PCU_VROK_Mask) == 0x00 ? PCU_UNSTABLE : PCU_STABLE; +} + +/******************************************************************************* +* Function Name : PCU_FlagStatus +* Description : This routine is used to return the PCU register flag +* Input 1 : The flag to get +* Return : RESET, SET +*******************************************************************************/ +inline FlagStatus PCU_FlagStatus ( PCU_Flags Xflag ) +{ + return ( PCU->PWRCR & Xflag ) == 0x00 ? RESET : SET; +} + +/******************************************************************************* +* Function Name : PCU_VRConfig +* Description : This routine is used to configure PCU voltage regultors +* Input 1 : MVR : Main voltage Regulator + LPR : Low Power Regulator +* Input 2 : ENABLE : Enable the Voltage Regulator + DISABLE: Disable ( ByPass ) the VR +* Return : None +*******************************************************************************/ +void PCU_VRConfig ( PCU_VR xVR, FunctionalState NewState ); + +/******************************************************************************* +* Function Name : PCU_VRStatus +* Description : This routine is used to get the PCU voltage regultors status +* Input : MVR : Main voltage Regulator + LPR : Low Power Regulator +* Return : ENABLE : Enable the Voltage Regulator + DISABLE: Disable ( ByPass ) the VR +*******************************************************************************/ +inline FunctionalState PCU_VRStatus ( PCU_VR xVR ) +{ + return ( PCU->PWRCR & xVR ) == 0 ? ENABLE : DISABLE; +} + +/******************************************************************************* +* Function Name : PCU_LVDDisable +* Description : This routine is used to disable the Low Voltage Detector. +* Input : None +* Return : None +*******************************************************************************/ +inline void PCU_LVDDisable ( void ) +{ + PCU->PWRCR |= PCU_WREN_Mask; // Unlock Power Control Register + PCU->PWRCR |= PCU_LVD_Mask; // Set the LVD DIS Flag +} + +/******************************************************************************* +* Function Name : PCU_LVDStatus +* Description : This routine is used to get the LVD NewState. +* Input : None +* Return : ENABLE, DISABLE +*******************************************************************************/ +inline FunctionalState PCU_LVDStatus ( void ) +{ + return ( PCU->PWRCR & PCU_LVD_Mask ) == 0 ? ENABLE : DISABLE; +} + +/******************************************************************************* +* Function Name : PCU_WFIEnter +* Description : This routine is used to force the Device to enter in WFI mode +* Input 1 : CLOCK2_16 : Clock2_16 as system clock for WFI mode +* EXTERNAL : external clock as system clock for WFI mode +* Input 2 : ENABLE : Enable Low Power Regulator during Wait For Interrupt Mode +* DISABLE: Disable Low Power Regulator during Wait For Interrupt Mode +* Input 3 : ENABLE : Enable Low Power Mode during Wait For Interrupt Mode +* DISABLE: Disable Low Power Mode during Wait For Interrupt Mode +* Return : None +*******************************************************************************/ +void PCU_WFIEnter ( WFI_CLOCKS Xclock, FunctionalState Xlpr, FunctionalState Xlpm ); + +/******************************************************************************* +* Function Name : PCU_LPMEnter +* Description : This routine is used to force the Device to enter low +* power mode +* Input : SLOW : Slow Mode + STOP : Stop Mode + HALT : Halt Mode +* Return : None +*******************************************************************************/ +void PCU_LPMEnter ( LPM_MODES Xmode); + +#endif // __PCU_H + +/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR71x_IAR/Library/include/rccu.h b/20080212/Demo/ARM7_STR71x_IAR/Library/include/rccu.h new file mode 100644 index 000000000..86c76130a --- /dev/null +++ b/20080212/Demo/ARM7_STR71x_IAR/Library/include/rccu.h @@ -0,0 +1,319 @@ +/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** +* File Name : rccu.h +* Author : MCD Application Team +* Date First Issued : 28/07/2003 +* Description : This file contains all the functions prototypes for the +* RCCU software library. +******************************************************************************** +* History: +* 30/11/2004 : V2.0 +* 14/07/2004 : V1.3 +* 01/01/2004 : V1.2 +******************************************************************************* + THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH + CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. + AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT + OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +#ifndef __RCCU_H +#define __RCCU_H + +#include "71x_map.h" + +typedef enum { + RCCU_DEFAULT=0x00, + RCCU_RCLK_2 =0x01, + RCCU_RCLK_4 =0x02, + RCCU_RCLK_8 =0x03 + } RCCU_Clock_Div; + +typedef enum { + RCCU_PLL1_Output, + RCCU_CLOCK2_16, + RCCU_CLOCK2, + RCCU_RTC_CLOCK + } RCCU_RCLK_Clocks; + + + typedef enum { + RCCU_PLL1_Mul_12=0x01, + RCCU_PLL1_Mul_16=0x03, + RCCU_PLL1_Mul_20=0x00, + RCCU_PLL1_Mul_24=0x02 + } RCCU_PLL1_Mul; + +typedef enum { + RCCU_PLL2_Mul_12=0x01, + RCCU_PLL2_Mul_16=0x03, + RCCU_PLL2_Mul_20=0x00, + RCCU_PLL2_Mul_28=0x02 + } RCCU_PLL2_Mul; + +typedef enum { + RCCU_Div_1=0x00, + RCCU_Div_2=0x01, + RCCU_Div_3=0x02, + RCCU_Div_4=0x03, + RCCU_Div_5=0x04, + RCCU_Div_6=0x05, + RCCU_Div_7=0x06 + } RCCU_PLL_Div; + +typedef enum { + RCCU_PLL2_Output = 0x01, + RCCU_USBCK = 0x00 + } RCCU_USB_Clocks; + +typedef enum { + RCCU_CLK2, + RCCU_RCLK, + RCCU_MCLK, + RCCU_PCLK, + RCCU_FCLK + } RCCU_Clocks; + +typedef enum { + RCCU_PLL1_LOCK_IT = 0x0080, + RCCU_CKAF_IT = 0x0100, + RCCU_CK2_16_IT = 0x0200, + RCCU_STOP_IT = 0x0400 + } RCCU_Interrupts; + +typedef enum { + RCCU_PLL1_LOCK = 0x0002, + RCCU_CKAF_ST = 0x0004, + RCCU_PLL1_LOCK_I = 0x0800, + RCCU_CKAF_I = 0x1000, + RCCU_CK2_16_I = 0x2000, + RCCU_STOP_I = 0x4000 + } RCCU_Flags; + +typedef enum { + RCCU_ExternalReset = 0x00000000, + RCCU_SoftwareReset = 0x00000020, + RCCU_WDGReset = 0x00000040, + RCCU_RTCAlarmReset = 0x00000080, + RCCU_LVDReset = 0x00000200, + RCCU_WKPReset = 0x00000400 + }RCCU_ResetSources; + + +#define RCCU_Div2_Mask 0x00008000 +#define RCCU_Div2_Index 0x0F +#define RCCU_FACT_Mask 0x0003 + +#define RCCU_FACT1_Mask 0x0003 + +#define RCCU_FACT2_Mask 0x0300 +#define RCCU_FACT2_Index 0x08 + +#define RCCU_MX_Mask 0x00000030 +#define RCCU_MX_Index 0x04 + +#define RCCU_DX_Mask 0x00000007 + +#define RCCU_FREEN_Mask 0x00000080 + +#define RCCU_CSU_CKSEL_Mask 0x00000001 + +#define RCCU_CK2_16_Mask 0x00000008 + +#define RCCU_CKAF_SEL_Mask 0x00000004 + +#define RCCU_LOCK_Mask 0x00000002 + +#define RCCU_USBEN_Mask 0x0100 +#define RCCU_USBEN_Index 0x08 +#define RCCU_ResetSources_Mask 0x000006E0 + +// RTC Oscillator Frequency value = 32 768 Hz +#define RCCU_RTC_Osc 32768 + + +/******************************************************************************* +* Function Name : RCCU_Div2Config +* Description : Enables/Disables the clock division by two +* Input : NewState : ENABLE or DISABLE +* Return : None +*******************************************************************************/ +inline void RCCU_Div2Config ( FunctionalState NewState ) +{ + if (NewState == ENABLE) RCCU->CFR |= RCCU_Div2_Mask; + else RCCU->CFR &= ~RCCU_Div2_Mask; +} + +/******************************************************************************* +* Function Name : RCCU_Div2Status +* Description : Gets the Div2 Flag status +* Input : None +* Input : FlagStatus +* Return : None +*******************************************************************************/ +inline FlagStatus RCCU_Div2Status ( void ) +{ + return (RCCU->CFR & RCCU_Div2_Mask) == 0 ? RESET : SET; +} + +/******************************************************************************* +* Function Name : RCCU_MCLKConfig +* Description : Selects the division factor for RCLK to obtain the +* MCLK clock for the CPU +* Input : New_Clock : RCCU_DEFAULT, RCCU_RCLK_2, RCCU_RCLK_4, RCCU_RCLK_8 +* Return : None +*******************************************************************************/ +inline void RCCU_MCLKConfig ( RCCU_Clock_Div New_Clock ) +{ + PCU->MDIVR = ( PCU->MDIVR & ~RCCU_FACT_Mask ) | New_Clock; +} + +/******************************************************************************* +* Function Name : RCCU_FCLKConfig +* Description : Selects the division factor for RCLK to obtain the +* FCLK clock for the APB1 fast peripherals (PCLK1). +* Input : New_Clock : RCCU_DEFAULT, RCCU_RCLK_2, +* RCCU_RCLK_4, RCCU_RCLK_8 +* Return : None +*******************************************************************************/ +inline void RCCU_FCLKConfig ( RCCU_Clock_Div New_Clock ) +{ + PCU->PDIVR = ( PCU->PDIVR & ~RCCU_FACT1_Mask ) | New_Clock; +} + +/******************************************************************************* +* Function Name : RCCU_PCLKConfig +* Description : Selects the division factor for RCLK to obtain the +* PCLK clock for the APB2 peripherals (PCLK2). +* Input : New_Clock : RCCU_DEFAULT, RCCU_RCLK_2, +* RCCU_RCLK_4, RCCU_RCLK_8 +* Return : None +*******************************************************************************/ +inline void RCCU_PCLKConfig ( RCCU_Clock_Div New_Clock ) +{ + PCU->PDIVR =(PCU->PDIVR & ~RCCU_FACT2_Mask)|(New_Clock << RCCU_FACT2_Index); +} + +/******************************************************************************* +* Function Name : RCCU_PLL1Config +* Description : Configures the PLL1 div & mul factors. +* Input : New_Mul : RCCU_Mul_12, RCCU_Mul_16, RCCU_Mul_20, RCCU_Mul_28 +* : New_Div : RCCU_Div_1, RCCU_Div_2, RCCU_Div_3, +* RCCU_Div_4, RCCU_Div_5, RCCU_Div_6, RCCU_Div_7 +* Return : None +*******************************************************************************/ +void RCCU_PLL1Config ( RCCU_PLL1_Mul New_Mul, RCCU_PLL_Div New_Div ); + +/******************************************************************************* +* Function Name : RCCU_PLL2Config +* Description : Configures the PLL2 div & mul factors. +* Input : New_Mul : RCCU_Mul_12, RCCU_Mul_16, RCCU_Mul_20, RCCU_Mul_28 +* : New_Div : RCCU_Div_1, RCCU_Div_2, RCCU_Div_3, RCCU_Div_4, +* RCCU_Div_5, RCCU_Div_6, RCCU_Div_7 +* Return : None +*******************************************************************************/ +void RCCU_PLL2Config ( RCCU_PLL2_Mul New_Mul, RCCU_PLL_Div New_Div ); + +/******************************************************************************* +* Function Name : RCCU_RCLKSourceConfig +* Description : Selects the RCLK source clock +* Input : New_Clock : RCCU_PLL1_OutPut, RCCU_CLOCK2_16, RCCU_CLOCK2 +* Return : None +*******************************************************************************/ +void RCCU_RCLKSourceConfig ( RCCU_RCLK_Clocks New_Clock ); + +/******************************************************************************* +* Function Name : RCCU_RCLKClockSource +* Description : Returns the current RCLK source clock +* Input : None +* Return : RCCU_PLL1_Output, RCCU_CLOCK2_16, RCCU_CLOCK2 +*******************************************************************************/ +RCCU_RCLK_Clocks RCCU_RCLKClockSource ( void ); + +/******************************************************************************* +* Function Name : RCCU_USBCLKConfig +* Description : Selects the USB source clock +* Input : New_Clock : RCCU_PLL2_Output, RCCU_USBCK +* Return : None +*******************************************************************************/ +inline void RCCU_USBCLKConfig ( RCCU_USB_Clocks New_Clock ) +{ + PCU->PLL2CR = (PCU->PLL2CR & ~RCCU_USBEN_Mask)|(New_Clock << RCCU_USBEN_Index); +} + +/******************************************************************************* +* Function Name : RCCU_USBClockSource +* Description : Gets the USB source clock +* Input : None +* Return : RCCU_USB_Clocks +*******************************************************************************/ +RCCU_USB_Clocks RCCU_USBClockSource ( void ); + +/******************************************************************************* +* Function Name : RCCU_FrequencyValue +* Description : Calculates & Returns any internal RCCU clock freuqency +* passed in parametres +* Input : RCCU_Clocks : RCCU_CLK2, RCCU_RCLK, RCCU_MCLK, +* RCCU_PCLK, RCCU_FCLK +* Return : u32 +*******************************************************************************/ +u32 RCCU_FrequencyValue ( RCCU_Clocks Internal_Clk ); + +/******************************************************************************* +* Function Name : RCCU_ITConfig +* Description : Configures the RCCU interrupts +* Input : RCCU interrupts : RCCU_CK2_16_IT, RCCU_CKAF_IT, +* RCCU_PLL1_LOCK_IT +* Return : None +*******************************************************************************/ +inline void RCCU_ITConfig ( RCCU_Interrupts RCCU_IT, FunctionalState NewState) +{ + if (NewState == ENABLE) RCCU->CCR |= RCCU_IT; else RCCU->CCR &= ~RCCU_IT; +} + +/******************************************************************************* +* Function Name : RCCU_FlagStatus +* Description : Checks the RCCU clock flag register status +* Input : RCCU Flags : RCCU_CK2_16, RCCU_CKAF, RCCU_PLL1_LOCK +* Return : FlagStatus : SET or RESET +*******************************************************************************/ +inline FlagStatus RCCU_FlagStatus ( RCCU_Flags RCCU_flag ) +{ + return (RCCU->CFR & RCCU_flag) == 0 ? RESET : SET; +} + +/******************************************************************************* +* Function Name : RCCU_FlagClear +* Description : Clears a specified flag in the RCCU registers +* Input : RCCU Flags : RCCU_CK2_16, RCCU_CKAF, RCCU_PLL1_LOCK +* Return : None +*******************************************************************************/ +inline void RCCU_FlagClear ( RCCU_Interrupts RCCU_IT ) +{ + RCCU->CFR |= RCCU_IT; +} + +/******************************************************************************* +* Function Name : RCCU_ResetSources +* Description : Return the source of the system reset +* Input : None +* Return : The reset source +*******************************************************************************/ +inline RCCU_ResetSources RCCU_ResetSource () +{ + + switch(RCCU->CFR & RCCU_ResetSources_Mask) + { + case 0x00000020: return RCCU_SoftwareReset; + case 0x00000040: return RCCU_WDGReset; + case 0x00000080: return RCCU_RTCAlarmReset; + case 0x00000200: return RCCU_LVDReset; + case 0x00000400: return RCCU_WKPReset; + default : return RCCU_ExternalReset; + } +} + +#endif // __RCCU_H + +/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR71x_IAR/Library/include/tim.h b/20080212/Demo/ARM7_STR71x_IAR/Library/include/tim.h new file mode 100644 index 000000000..fbb3ff080 --- /dev/null +++ b/20080212/Demo/ARM7_STR71x_IAR/Library/include/tim.h @@ -0,0 +1,345 @@ +/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** +* File Name : tim.h +* Author : MCD Application Team +* Date First Issued : 08/09/2003 +* Description : This file contains all the functions prototypes for the +* TIM software library. +******************************************************************************** +* History: +* 30/11/2004 : V2.0 +* 14/07/2004 : V1.3 +* 01/01/2004 : V1.2 +******************************************************************************* + THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH + CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. + AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT + OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +#ifndef __TIM_H +#define __TIM_H + +#include "71x_map.h" + +typedef enum { TIM_EXTERNAL, + TIM_INTERNAL + } TIM_Clocks; + +typedef enum { TIM_RISING, + TIM_FALLING + } TIM_Clock_Edges; + +typedef enum { TIM_CHANNEL_A, + TIM_CHANNEL_B + } TIM_Channels; + +typedef enum { TIM_WITH_IT, + TIM_WITHOUT_IT + } TIM_IT_Mode; + +typedef enum { TIM_TIMING, + TIM_WAVE + } TIM_OC_Modes; + +typedef enum { TIM_HIGH, + TIM_LOW + } TIM_Logic_Levels; + +typedef enum { TIM_START, + TIM_STOP, + TIM_CLEAR + } TIM_CounterOperations; + +typedef enum { TIM_ICFA = 0x8000, + TIM_OCFA = 0x4000, + TIM_TOF = 0x2000, + TIM_ICFB = 0x1000, + TIM_OCFB = 0x0800 + } TIM_Flags; + +typedef struct { u16 Pulse; + u16 Period; + } PWMI_parameters; + +#define TIM_ECKEN_Mask 0x0001 +#define TIM_EXEDG_Mask 0x0002 + +#define TIM_IEDGA_Mask 0x0004 +#define TIM_IEDGB_Mask 0x0008 + +#define TIM_PWM_Mask 0x0010 + +#define TIM_OMP_Mask 0x0020 + +#define TIM_OCAE_Mask 0x0040 +#define TIM_OCBE_Mask 0x0080 + +#define TIM_OLVLA_Mask 0x0100 +#define TIM_OLVLB_Mask 0x0200 + +#define TIM_FOLVA_Mask 0x0400 +#define TIM_FOLVB_Mask 0x0800 + +#define TIM_PWMI_Mask 0x4000 + +#define TIM_EN_Mask 0x8000 + +#define TIM_OCBIE_mask 0x0800 +#define TIM_ICBIE_Mask 0x1000 +#define TIM_TOE_Mask 0x2000 +#define TIM_ICAIE_Mask 0x8000 +#define TIM_OCAIE_mask 0x4000 + +#define TIM_ICA_IT 0x8000 // Input Capture Channel A +#define TIM_OCA_IT 0x4000 // Output Compare Channel A +#define TIM_TO_IT 0x2000 // Timer OverFlow +#define TIM_ICB_IT 0x1000 // Input Capture Channel B +#define TIM_OCB_IT 0x0800 // Input Capture Channel A + + +/******************************************************************************* +* Function Name : TIM_Init +* Description : This routine is used to Initialize the TIM peripheral +* Input : TIM Timer to Initialize +* Return : None +*******************************************************************************/ +void TIM_Init( TIM_TypeDef *TIMx ); + +/******************************************************************************* +* Function Name : TIM_ClockSourceConfig +* Description : This routine is used to configure the TIM clock source +* Input : (1) TIM Timer +* : (2) TIM_Clocks : Specifies the TIM source clock +* - TIM_INTERNAL : The TIM is clocked by the APB2 frequency +* divided by the prescaler value. +* - TIM_EXTERNAL : The TIM is clocked by an external Clock +* Return : None +*******************************************************************************/ +inline void TIM_ClockSourceConfig ( TIM_TypeDef *TIMx, TIM_Clocks Xclock ) +{ + if (Xclock==TIM_EXTERNAL) TIMx->CR1|=TIM_ECKEN_Mask; else TIMx->CR1&=~TIM_ECKEN_Mask; +} + +/******************************************************************************* +* Function Name : TIM_ClockSourceValue +* Description : This routine is used to get the TIM clock source +* Input : TIM Timer +* Return : TIM_Clocks : Specifies the TIM source clock +* - TIM_INTERNAL : The TIM is clocked by the APB2 frequency +* divided by the prescaler value. +* - TIM_EXTERNAL : The TIM is clocked by an external Clock +*******************************************************************************/ +inline TIM_Clocks TIM_ClockSourceValue ( TIM_TypeDef *TIMx ) +{ + return ( TIMx->CR1 & TIM_ECKEN_Mask) == 0 ? TIM_INTERNAL : TIM_EXTERNAL; +} + +/******************************************************************************* +* Function Name : TIM_PrescalerConfig +* Description : This routine is used to configure the TIM prescaler value +* ( using an internal clock ) +* Input : (1) TIM Timer +* : (2) Prescaler ( u8 ) +* Return : None +*******************************************************************************/ +inline void TIM_PrescalerConfig ( TIM_TypeDef *TIMx, u8 Xprescaler ) +{ + TIMx->CR2 = ( TIMx->CR2 & 0xFF00 ) | Xprescaler; +} + +/******************************************************************************* +* Function Name : TIM_PrescalerValue +* Description : This routine is used to get the TIM prescaler value +* ( when using using an internal clock ) +* Input : TIM Timer +* Return : Prescaler ( u8 ) +*******************************************************************************/ +inline u8 TIM_PrescalerValue ( TIM_TypeDef *TIMx ) +{ + return TIMx->CR2 & 0x00FF; +} + +/******************************************************************************* +* Function Name : TIM_ClockLevelConfig +* Description : This routine is used to configure the TIM clock level +* ( using an external clock ) +* Input : TIM Timer +* : TIM_Clock_Edges : Specifies the active adge of the external clock +* - TIM_RISING : The rising edge +* - TIM_FALLING : The falling edge +* Return : None +*******************************************************************************/ +inline void TIM_ClockLevelConfig ( TIM_TypeDef *TIMx, TIM_Clock_Edges Xedge ) +{ + if (Xedge == TIM_RISING) TIMx->CR1 |= TIM_EXEDG_Mask; else TIMx->CR1 &= ~TIM_EXEDG_Mask; +} + +/******************************************************************************* +* Function Name : TIM_ClockLevelValue +* Description : This routine is used to get the TIM clock level +* Input : TIM Timer +* Output : TIM_Clock_Edges : Specifies the active adge of the external clock +* - TIM_RISING : The rising edge +* - TIM_FALLING : The falling edge +*******************************************************************************/ +inline TIM_Clock_Edges TIM_ClockLevelValue ( TIM_TypeDef *TIMx ) +{ + return ( TIMx->CR1 & TIM_EXEDG_Mask ) == 0 ? TIM_FALLING : TIM_RISING; +} + +/******************************************************************************* +* Function Name : TIM_ICAPModeConfig +* Description : This routine is used to configure the input capture feature +* Input : (1) TIM Timer +* : (2) Input Capture Channel ( Channel_A or Channel_B ) +* : (3) Active Edge : Rising edge or Falling edge. +* Output : None +*******************************************************************************/ +void TIM_ICAPModeConfig ( TIM_TypeDef *TIMx, + TIM_Channels Xchannel, + TIM_Clock_Edges Xedge ); + +/******************************************************************************* +* Function Name : TIM_ICAPValue +* Description : This routine is used to get the Input Capture value +* Input : (1) TIM Timer +* : (2) Input Capture Channel ( Channel_A or Channel_B ) +* Output : None +*******************************************************************************/ +inline u16 TIM_ICAPValue ( TIM_TypeDef *TIMx, TIM_Channels Xchannel ) +{ + return Xchannel == TIM_CHANNEL_A ? TIMx->ICAR : TIMx->ICBR; +} + +/******************************************************************************* +* Function Name : TIM_OCMPModeConfig +* Description : This routine is used to configure the output compare feature +* Input : (1) TIM Timer +* : (2) OCMP Channel ( Channel_A or Channel_B ) +* : (3) Pulse Length +* : (4) OC_Mode : output wave, or only timing. +* : (5) Level : Rising edge or Falling edge after the == +* Output : None +*******************************************************************************/ +void TIM_OCMPModeConfig ( TIM_TypeDef *TIMx, + TIM_Channels Xchannel, + u16 XpulseLength, + TIM_OC_Modes Xmode, + TIM_Logic_Levels Xlevel ); + +/******************************************************************************* +* Function Name : TIM_OPModeConfig +* Description : This routine is used to configure the one pulse mode +* Input : (1) TIM Timer +* : (3) XpulseLength : Length of the pulse +* : (4) Level1 : Level during the pulse +* : (5) Level2 : Level after the pulse +* : (6) Activation Edge : High or Low on ICAP A +* Output : None +*******************************************************************************/ +void TIM_OPModeConfig ( TIM_TypeDef *TIMx, + u16 XpulseLength, + TIM_Logic_Levels XLevel1, + TIM_Logic_Levels XLevel2, + TIM_Clock_Edges Xedge ); + +/******************************************************************************* +* Function Name : TIM_PWMOModeConfig +* Description : This routine is used to configure the PWM in output mode +* Input : (1) TIM Timer +* : (2) DutyCycle : u16 +* : (3) Level 1 : During the Duty Cycle +* : (4) Level 2 : During the after the pulse +* : (5) Full period : u16 +* Output : None +*******************************************************************************/ +void TIM_PWMOModeConfig ( TIM_TypeDef *TIMx, + u16 XDutyCycle, + TIM_Logic_Levels XLevel1, + u16 XFullperiod, + TIM_Logic_Levels XLevel2 + ); + +/******************************************************************************* +* Function Name : TIM_PWMInputConfig +* Description : This routine is used to configure the PWM in input mode +* Input : (1) TIM Timer +* : (2) First Activation Edge +* Output : None +*******************************************************************************/ +void TIM_PWMIModeConfig ( TIM_TypeDef *TIMx, TIM_Clock_Edges Xedge ); + +/******************************************************************************* +* Function Name : TIM_PWMIValue +* Description : This routine is used to get the PWMI values +* Input : (1) TIM Timer +* Output : PWMI_parameters : - u16 Dyty cycle + - u16 Full period +*******************************************************************************/ +PWMI_parameters TIM_PWMIValue (TIM_TypeDef *TIMx ); + +/******************************************************************************* +* Function Name : TIM_CounterConfig +* Description : This routine is used to start/stop and clear the selected +* timer counter +* Input : (1) TIM Timer +* : (2) TIM_CounterOperations + TIM_START Enables or resumes the counter +* TIM_STOP Stops the TIM counter +* TIM_CLEAR Set the TIM counter value to FFFCh +* Output : None +*******************************************************************************/ +void TIM_CounterConfig ( TIM_TypeDef *TIMx, TIM_CounterOperations Xoperation ); + +/******************************************************************************* +* Function Name : TIM_ITConfig +* Description : This routine is used to configure the TIM IT +* Input : (1) TIM Timer +* : (2) TIM interrupt +* : (2) ENABLE / DISABLE +* Output : None +*******************************************************************************/ +inline void TIM_ITConfig ( TIM_TypeDef *TIMx, u16 New_IT, FunctionalState NewState ) +{ + if (NewState == ENABLE) TIMx->CR2 |= New_IT; else TIMx->CR2 &= ~New_IT; +} + +/******************************************************************************* +* Function Name : TIM_FlagStatus +* Description : This routine is used to check whether a Flag is Set. +* Input : (1) TIM Timer +* : (2) The TIM FLag +* Output : Flag NewState +*******************************************************************************/ +inline FlagStatus TIM_FlagStatus ( TIM_TypeDef *TIMx, TIM_Flags Xflag ) +{ + return (TIMx->SR & Xflag) == 0 ? RESET : SET; +} + +/******************************************************************************* +* Function Name : TIM_FlagClear +* Description : This routine is used to clear Flags. +* Input : (1) TIM Timer +* : (2) The TIM FLag +* Output : None +*******************************************************************************/ +inline void TIM_FlagClear ( TIM_TypeDef *TIMx, TIM_Flags Xflag ) +{ + TIMx->SR &= ~Xflag; +} + +/******************************************************************************* +* Function Name : TIM_CounterValue +* Description : This routine returns the timer counter value. +* Input : TIM Timer +* Output : The counter value +*******************************************************************************/ +inline u16 TIM_CounterValue(TIM_TypeDef *TIMx) +{ + return TIMx->CNTR; +} +#endif // __TIM_H + +/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR71x_IAR/Library/include/uart.h b/20080212/Demo/ARM7_STR71x_IAR/Library/include/uart.h new file mode 100644 index 000000000..7ca40bc4e --- /dev/null +++ b/20080212/Demo/ARM7_STR71x_IAR/Library/include/uart.h @@ -0,0 +1,390 @@ +/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** +* File Name : uart.h +* Author : MCD Application Team +* Date First Issued : 16/05/2003 +* Description : This file contains all the functions prototypes for the +* UART software library. +******************************************************************************** +* History: +* 30/11/2004 : V2.0 +* 14/07/2004 : V1.3 +* 01/01/2004 : V1.2 +******************************************************************************* + THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH + CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. + AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT + OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ +#ifndef _UART_H +#define _UART_H + +#include "71x_map.h" +#include "rccu.h" + +typedef enum +{ + UART_RxFIFO, + UART_TxFIFO +} UARTFIFO_TypeDef; + +typedef enum +{ + UART_EVEN_PARITY = 0x0000, + UART_ODD_PARITY = 0x0020, + UART_NO_PARITY +} UARTParity_TypeDef; + +typedef enum +{ + UART_0_5_StopBits = 0x00, + UART_1_StopBits = 0x08, + UART_1_5_StopBits = 0x10, + UART_2_StopBits = 0x18 +} UARTStopBits_TypeDef; + +typedef enum +{ + UARTM_8D = 0x01, + UARTM_7D_P = 0x03, + UARTM_9D = 0x04, + UARTM_8D_W = 0x05, + UARTM_8D_P = 0x07 +} UARTMode_TypeDef; + + +#define DUMMY 0 + +// UART flags definition +#define UART_TxFull 0x0200 +#define UART_RxHalfFull 0x0100 +#define UART_TimeOutIdle 0x0080 +#define UART_TimeOutNotEmpty 0x0040 +#define UART_OverrunError 0x0020 +#define UART_FrameError 0x0010 +#define UART_ParityError 0x0008 +#define UART_TxHalfEmpty 0x0004 +#define UART_TxEmpty 0x0002 +#define UART_RxBufFull 0x0001 + +// CR regiter bit definition +#define UART_FIFOEnableBit 10 +#define UART_RxEnableBit 8 +#define UART_RunBit 7 +#define UART_LoopBackBit 6 +#define UART_ParityOddBit 5 +#define UART_StopBits 3 + +// Stop bits definition +#define UART_05StopBits 0x00 +#define UART_1StopBit (0x01<<3) +#define UART_15StopBits (0x02<<3) +#define UART_2StopBits (0x03<<3) + +// Modes definition +#define UART_8BitsData 0x01 +#define UART_7BitsData 0x03 +#define UART_9BitsData 0x04 +#define UART_8BitsDataWakeUp 0x05 +#define UART_8BitsDataParity 0x07 + +/******************************************************************************* +* Function Name : UART_Init +* Description : This function initializes the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Output : None +* Return : None +*******************************************************************************/ +void UART_Init(UART_TypeDef *UARTx); + +/******************************************************************************* +* Function Name : UART_ModeConfig +* Description : This function configures the mode of the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : The UART mode +* Output : None +* Return : None +*******************************************************************************/ +inline void UART_ModeConfig(UART_TypeDef *UARTx, UARTMode_TypeDef UART_Mode) +{ + UARTx->CR = (UARTx->CR&0xFFF8)|(u16)UART_Mode; +} + +/******************************************************************************* +* Function Name : UART_BaudRateConfig +* Description : This function configures the baud rate of the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : The baudrate value +* Output : None +* Return : None +*******************************************************************************/ +void UART_BaudRateConfig(UART_TypeDef *UARTx, u32 BaudRate); + +/******************************************************************************* +* Function Name : UART_ParityConfig +* Description : This function configures the data parity of the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : The parity type +* Output : None +* Return : None +*******************************************************************************/ +inline void UART_ParityConfig(UART_TypeDef *UARTx, UARTParity_TypeDef Parity) +{ + UARTx->CR = (UARTx->CR&0xFFDF)|(u16)Parity; +} + +/******************************************************************************* +* Function Name : UART_StopBitsConfig +* Description : This function configures the number of stop bits of the +* selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : The number of stop bits +* Output : None +* Return : None +*******************************************************************************/ +inline void UART_StopBitsConfig(UART_TypeDef *UARTx, UARTStopBits_TypeDef StopBits) +{ + UARTx->CR = (UARTx->CR&0xFFE7)|(u16)StopBits; +} + +/******************************************************************************* +* Function Name : UART_Config +* Description : This function configures the baudrate, the mode, the data +* parity and the number of stop bits of the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : The baudrate value +* Input 3 : The parity type +* Input 4 : The number of stop bits +* Input 5 : The UART mode +* Output : None +* Return : None +*******************************************************************************/ +void UART_Config(UART_TypeDef *UARTx, u32 BaudRate, UARTParity_TypeDef Parity, + UARTStopBits_TypeDef StopBits, UARTMode_TypeDef Mode); + +/******************************************************************************* +* Function Name : UART_ItConfig +* Description : This function enables or disables the interrupts of the +* selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : The new interrupt flag +* Input 3 : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void UART_ItConfig(UART_TypeDef *UARTx, u16 UART_Flag, FunctionalState NewState); + +/******************************************************************************* +* Function Name : UART_FifoConfig +* Description : This function enables or disables the Rx and Tx FIFOs of +* the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void UART_FifoConfig(UART_TypeDef *UARTx, FunctionalState NewState); + +/******************************************************************************* +* Function Name : UART_FifoReset +* Description : This function resets the Rx and the Tx FIFOs of the +* selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : RxFIFO or TxFIFO +* Output : None +* Return : None +*******************************************************************************/ +void UART_FifoReset(UART_TypeDef *UARTx, UARTFIFO_TypeDef FIFO); + +/******************************************************************************* +* Function Name : UART_LoopBackConfig +* Description : This function enables or disables the loop back mode of +* the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void UART_LoopBackConfig(UART_TypeDef *UARTx, FunctionalState NewState); + +/******************************************************************************* +* Function Name : UART_TimeOutPeriodConfig +* Description : This function configure the Time Out Period. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : The time-out period value +* Output : None +* Return : None +*******************************************************************************/ +inline void UART_TimeOutPeriodConfig(UART_TypeDef *UARTx, u16 TimeOutPeriod) +{ + UARTx->TOR = TimeOutPeriod; +} + +/******************************************************************************* +* Function Name : UART_GuardTimeConfig +* Description : This function configure the Guard Time. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : The guard time value +* Output : None +* Return : None +*******************************************************************************/ +inline void UART_GuardTimeConfig(UART_TypeDef *UARTx, u16 GuardTime) +{ + UARTx->GTR = GuardTime; +} + +/******************************************************************************* +* Function Name : UART_RxConfig +* Description : This function enable and disable the UART data reception. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void UART_RxConfig(UART_TypeDef *UARTx, FunctionalState NewState); + +/******************************************************************************* +* Function Name : UART_OnOffConfig +* Description : This function sets On/Off the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void UART_OnOffConfig(UART_TypeDef *UARTx, FunctionalState NewState); + +/******************************************************************************* +* Function Name : UART_ByteSend +* Description : This function sends a data byte to the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : A pointer to the data byte to send +* Output : None +* Return : None +*******************************************************************************/ +void UART_ByteSend(UART_TypeDef *UARTx, u8 *Data); + +/******************************************************************************* +* Function Name : UART_9BitByteSend +* Description : This function sends a 9 bits data byte to the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : A pointer to the data to send +* Output : None +* Return : None +*******************************************************************************/ +void UART_9BitByteSend(UART_TypeDef *UARTx, u16 *Data); + +/******************************************************************************* +* Function Name : UART_DataSend +* Description : This function sends several data bytes to the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : A pointer to the data to send +* Input 3 : The data length in bytes +* Output : None +* Return : None +*******************************************************************************/ +void UART_DataSend(UART_TypeDef *UARTx, u8 *Data, u8 DataLength); + +/******************************************************************************* +* Function Name : UART_9BitDataSend +* Description : This function sends several 9 bits data bytes to the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : A pointer to the data to send +* Input 3 : The data length +* Output : None +* Return : None +*******************************************************************************/ +void UART_9BitDataSend(UART_TypeDef *UARTx, u16 *Data, u8 DataLength); + +/******************************************************************************* +* Function Name : UART_StringSend +* Description : This function sends a string to the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : A pointer to the string to send +* Output : None +* Return : None +*******************************************************************************/ +void UART_StringSend(UART_TypeDef *UARTx, u8 *String); + +/******************************************************************************* +* Function Name : UART_ByteReceive +* Description : This function gets a data byte from the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : A pointer to the buffer where the data will be stored +* Input 3 : The time-out period +* Output : The received data +* Return : The UARTx.SR register contents +*******************************************************************************/ +u16 UART_ByteReceive(UART_TypeDef *UARTx, u8 *Data, u8 TimeOut); + +/******************************************************************************* +* Function Name : UART_9BitByteReceive +* Description : This function gets a 9 bits data byte from the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : A pointer to the buffer where the data will be stored +* Input 3 : The time-out period value +* Output : The received data +* Return : The UARTx.SR register contents +*******************************************************************************/ +u16 UART_9BitByteReceive(UART_TypeDef *UARTx, u16 *Data, u8 TimeOut); + +/******************************************************************************* +* Function Name : UART_DataReceive +* Description : This function gets 8 bits data bytes from the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : A pointer to the buffer where the data will be stored +* Input 3 : The data length +* Input 4 : The time-out period value +* Output : The received data +* Return : The UARTx.SR register contents +*******************************************************************************/ +u16 UART_DataReceive(UART_TypeDef *UARTx, u8 *Data, u8 DataLength, u8 TimeOut); + +/******************************************************************************* +* Function Name : UART_9BitDataReceive +* Description : This function gets 9 bits data bytes from the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : A pointer to the buffer where the data will be stored +* Input 3 : The data length +* Input 4 : The time-out value +* Output : The received data +* Return : The UARTx.SR register contents +*******************************************************************************/ +u16 UART_9BitDataReceive(UART_TypeDef *UARTx, u16 *Data, u8 DataLength, u8 TimeOut); + +/******************************************************************************* +* Function Name : UART_StringReceive +* Description : This function gets 8 bits data bytes from the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : A pointer to the buffer where the string will be stored +* Output : None +* Return : None +*******************************************************************************/ +u16 UART_StringReceive(UART_TypeDef *UARTx, u8 *Data); + +/******************************************************************************* +* Function Name : UART_FlagStatus +* Description : This function gets the flags status of the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Output : None +* Return : None +*******************************************************************************/ +inline u16 UART_FlagStatus(UART_TypeDef *UARTx) +{ + return UARTx->SR; +} + +#ifdef USE_SERIAL_PORT +/******************************************************************************* +* Function Name : sendchar +* Description : This function sends a character to the selected UART. +* Input 1 : A pointer to the character to send. +* Output : None +* Return : None +*******************************************************************************/ +void sendchar( char *ch ); +#endif /* USE_SERIAL_PORT */ + +#endif /* _UART_H */ + +/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR71x_IAR/Library/include/wdg.h b/20080212/Demo/ARM7_STR71x_IAR/Library/include/wdg.h new file mode 100644 index 000000000..2a592ef79 --- /dev/null +++ b/20080212/Demo/ARM7_STR71x_IAR/Library/include/wdg.h @@ -0,0 +1,129 @@ +/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** +* File Name : wdg.h +* Author : MCD Application Team +* Date First Issued : 25/08/2003 +* Description : This file contains all the functions prototypes for the +* WDG software library. +******************************************************************************** +* History: +* 30/11/2004 : V2.0 +* 14/07/2004 : V1.3 +* 01/01/2004 : V1.2 +******************************************************************************* + THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH + CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. + AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT + OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ +#ifndef __WDG_H +#define __WDG_H + +#include "71x_map.h" +#include "rccu.h" + +/******************************************************************************* +* Function Name : WDG_Enable +* Description : Enable the Watchdog Mode +* Input : None +* Return : None +*******************************************************************************/ +inline void WDG_Enable ( void ) +{ + WDG->CR |= 0x01; +} + +/******************************************************************************* +* Function Name : WDG_CntRefresh +* Description : Refresh and update the WDG counter to avoid a system reset. +* Input : None +* Return : None +*******************************************************************************/ +inline void WDG_CntRefresh ( void ) +{ + //write the first value in the key register + WDG->KR = 0xA55A; + //write the consecutive value + WDG->KR = 0x5AA5; +} + +/******************************************************************************* +* Function Name : WDG_PrescalerConfig +* Description : Set the counter prescaler value. +* Divide the counter clock by (Prescaler + 1) +* Input : Prescaler data value (8 bit) +* Return : None +*******************************************************************************/ +inline void WDG_PrescalerConfig ( u8 Prescaler ) +{ + WDG->PR = Prescaler; +} + +/******************************************************************************* +* Function Name : WDG_CntReloadUpdate +* Description : Update the counter pre-load value. +* Input : Pre-load data value (16 bit) +* Return : None +*******************************************************************************/ +inline void WDG_CntReloadUpdate ( u16 PreLoadValue ) +{ + WDG->VR = PreLoadValue; +} + +/******************************************************************************* +* Function Name : WDG_PeriodValueConfig +* Description : Set the prescaler and counter reload value based on the +* time needed +* Input : Amount of time (us) needed, peripheral clock2 value +* Return : None +*******************************************************************************/ +void WDG_PeriodValueConfig ( u32 Time ); + +/******************************************************************************* +* Function Name : WDG_CntOnOffConfig +* Description : Start or stop the free auto-reload timer to countdown. +* Input : ENABLE or DISABLE +* Return : None +*******************************************************************************/ +inline void WDG_CntOnOffConfig ( FunctionalState NewState ) +{ + if (NewState == ENABLE) WDG->CR |= 0x0002; else WDG->CR &= ~0x0002; +} + +/******************************************************************************* +* Function Name : WDG_ECITConfig +* Description : Enable or Disable the end of count interrupt +* Input : ENABLE or DISABLE +* Return : None +*******************************************************************************/ +inline void WDG_ECITConfig (FunctionalState NewState) +{ + if (NewState == ENABLE) WDG->MR |= 0x0001; else WDG->MR &= ~0x0001; +} + +/******************************************************************************* +* Function Name : WDG_ECFlagClear +* Description : Clear the end of count flag +* Input : None +* Return : None +*******************************************************************************/ +inline void WDG_ECFlagClear ( void ) +{ + WDG->SR = 0x0000; +} + +/******************************************************************************* +* Function Name : WDG_ECStatus +* Description : Return the end of count status +* Input : None +* Return : NewState value +*******************************************************************************/ +inline u16 WDG_ECStatus ( void ) +{ + return WDG->SR; +} + +#endif // __WDG_H + +/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR71x_IAR/Library/rccu.c b/20080212/Demo/ARM7_STR71x_IAR/Library/rccu.c new file mode 100644 index 000000000..70e0aac1c --- /dev/null +++ b/20080212/Demo/ARM7_STR71x_IAR/Library/rccu.c @@ -0,0 +1,183 @@ +/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** +* File Name : rccu.c +* Author : MCD Application Team +* Date First Issued : 07/28/2003 +* Description : This file provides all the RCCU software functions +******************************************************************************** +* History: +* 30/11/2004 : V2.0 +* 14/07/2004 : V1.3 +* 01/01/2004 : V1.2 +******************************************************************************* + THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH + CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. + AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT + OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ +#include "rccu.h" + +/******************************************************************************* +* Function Name : RCCU_PLL1Config +* Description : Configures the PLL1 div & mul factors. +* Input : New_Mul ( RCCU_PLL1_Mul_12, RCCU_PLL1_Mul_16, RCCU_PLL1_Mul_20, +* RCCU_PLL1_Mul_24 ) +* : New_Div ( RCCU_Div_1, RCCU_Div_2, RCCU_Div_3, RCCU_Div_4, +* RCCU_Div_5, RCCU_Div_6, RCCU_Div_7) +* Return : None +*******************************************************************************/ +void RCCU_PLL1Config ( RCCU_PLL1_Mul New_Mul, RCCU_PLL_Div New_Div ) +{ + u32 Tmp = ( RCCU->PLL1CR & ~RCCU_MX_Mask ) | ( New_Mul << RCCU_MX_Index ); + RCCU->PLL1CR = ( Tmp & ~RCCU_DX_Mask ) | New_Div | 0x40; +} + +/******************************************************************************* +* Function Name : RCCU_PLL2Config +* Description : Configures the PLL2 div & mul factors. +* Input : New_Mul ( RCCU_PLL2_Mul_12, RCCU_PLL2_Mul_16, RCCU_PLL2_Mul_20, +* RCCU_Mul_PLL2_28 ) +* : New_Div ( RCCU_Div_1, RCCU_Div_2, RCCU_Div_3, RCCU_Div_4, +* RCCU_Div_5, RCCU_Div_6, RCCU_Div_7) +* Return : None +*******************************************************************************/ +void RCCU_PLL2Config ( RCCU_PLL2_Mul New_Mul, RCCU_PLL_Div New_Div ) +{ + u32 Tmp = ( PCU->PLL2CR & ~RCCU_MX_Mask ) | ( New_Mul << RCCU_MX_Index ); + PCU->PLL2CR = ( Tmp & ~RCCU_DX_Mask ) | ( New_Div | RCCU_FREEN_Mask ); +} + +/******************************************************************************* +* Function Name : RCCU_RCLKSourceConfig +* Description : Selects the RCLK source clock +* Input : New_Clock ( RCCU_PLL1_Output, RCCU_CLOCK2_16, RCCU_CLOCK2 ) +* Return : None +*******************************************************************************/ +void RCCU_RCLKSourceConfig ( RCCU_RCLK_Clocks New_Clock ) +{ + switch ( New_Clock ) + { + case RCCU_CLOCK2 :{// Resets the CSU_Cksel bit in clk_flag + RCCU->CFR &= ~RCCU_CSU_CKSEL_Mask; + // Set the CK2_16 Bit in the CFR + RCCU->CFR |= RCCU_CK2_16_Mask; + // Deselect The CKAF + RCCU->CCR &= ~RCCU_CKAF_SEL_Mask; + // switch off the PLL1 + RCCU->PLL1CR=((RCCU->PLL1CR & ~RCCU_DX_Mask)\ + |0x00000003) & ~RCCU_FREEN_Mask; + break;} + case RCCU_CLOCK2_16 :{// ReSet the CK2_16 Bit in the CFR + RCCU->CFR &= ~RCCU_CK2_16_Mask; + // Deselect The CKAF + RCCU->CCR &= ~RCCU_CKAF_SEL_Mask; + // switch off the PLL1 + RCCU->PLL1CR=((RCCU->PLL1CR & ~RCCU_DX_Mask)\ + |0x00000003) & ~RCCU_FREEN_Mask; + break;} + case RCCU_PLL1_Output:{// Set the CK2_16 Bit in the CFR + RCCU->CFR = RCCU->CFR | RCCU_CK2_16_Mask; + // Waits the PLL1 to lock if DX bits are different from '111' + // If all DX bit are set the PLL lock flag in meaningless + if (( RCCU->PLL1CR & 0x0007 ) != 7) + while(!(RCCU->CFR & RCCU_LOCK_Mask)); + // Deselect The CKAF + RCCU->CCR &= ~RCCU_CKAF_SEL_Mask; + // Select The CSU_CKSEL + RCCU->CFR |= RCCU_CSU_CKSEL_Mask; + break;} + case RCCU_RTC_CLOCK : {RCCU->CCR |= 0x04; + break;} + } +} + +/******************************************************************************* +* Function Name : RCCU_RCLKClockSource +* Description : Returns the current RCLK source clock +* Input : None +* Return : RCCU_PLL1_Output, RCCU_CLOCK2_16, RCCU_CLOCK2, RCCU_RTC_CLOCK +*******************************************************************************/ +RCCU_RCLK_Clocks RCCU_RCLKClockSource ( void ) +{ + if ((RCCU->CCR & 0x04)==0x04) + return RCCU_RTC_CLOCK; + + else if ((RCCU->CFR & RCCU_CK2_16_Mask)==0) + return RCCU_CLOCK2_16; + + else if (RCCU->CFR & RCCU_CSU_CKSEL_Mask) + return RCCU_PLL1_Output; + + else + return RCCU_CLOCK2; +} + +/******************************************************************************* +* Function Name : RCCU_USBClockSource +* Description : Gets the RCLK source clock +* Input : None +* Return : RCCU_USB_Clocks ( RCCU_PLL2_Output, RCCU_USBCK ) +*******************************************************************************/ +RCCU_USB_Clocks RCCU_USBClockSource ( void ) +{ + if ((PCU->PLL2CR & RCCU_USBEN_Mask ) >> RCCU_USBEN_Index == 1 ) + return RCCU_PLL2_Output; + else return RCCU_USBCK; +} + +/******************************************************************************* +* Function Name : RCCU_FrequencyValue +* Description : Calculates & Returns any internal RCCU clock frequency +* passed in parametres +* Input : RCCU_Clocks ( RCCU_CLK2, RCCU_RCLK, RCCU_MCLK, RCCU_PCLK, RCCU_FCLK ) +* Return : u32 +*******************************************************************************/ +u32 RCCU_FrequencyValue ( RCCU_Clocks Internal_Clk ) +{ + u32 Tmp; + u8 Div, Mul; + RCCU_RCLK_Clocks CurrentRCLK; + + Tmp = ( RCCU_Div2Status() == SET )? RCCU_Main_Osc / 2 : RCCU_Main_Osc; + + if ( Internal_Clk == RCCU_CLK2 ) + { + Div = 1; + Mul = 1; + } + else + { CurrentRCLK = RCCU_RCLKClockSource (); + switch ( CurrentRCLK ){ + case RCCU_CLOCK2_16 : Div = 16; + Mul = 1; + break; + case RCCU_CLOCK2 : Div = 1; + Mul = 1; + break; + case RCCU_PLL1_Output :{Mul=(RCCU->PLL1CR & RCCU_MX_Mask ) >> RCCU_MX_Index; + switch ( Mul ) + {case 0: Mul = 20; break; + case 1: Mul = 12; break; + case 2: Mul = 28; break; + case 3: Mul = 16; break; + } + Div = ( RCCU->PLL1CR & RCCU_DX_Mask ) + 1; + break;} + case RCCU_RTC_CLOCK : Mul = 1; + Div = 1; + Tmp = RCCU_RTC_Osc; + break;}} + + switch ( Internal_Clk ){ + case RCCU_MCLK :{Div <<= PCU->MDIVR & RCCU_FACT_Mask; + break;} + case RCCU_PCLK :{Div <<=(PCU->PDIVR & RCCU_FACT2_Mask ) >> RCCU_FACT2_Index; + break;} + case RCCU_FCLK :{Div <<= PCU->PDIVR & 0x3; + break;}} + + return (Tmp * Mul) / Div; +} + +/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR71x_IAR/Library/uart.c b/20080212/Demo/ARM7_STR71x_IAR/Library/uart.c new file mode 100644 index 000000000..c299345ca --- /dev/null +++ b/20080212/Demo/ARM7_STR71x_IAR/Library/uart.c @@ -0,0 +1,365 @@ +/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** +* File Name : uart.c +* Author : MCD Application Team +* Date First Issued : 06/08/2003 +* Description : This file provides all the UART software functions +******************************************************************************** +* History: +* 30/11/2004 : V2.0 +* 14/07/2004 : V1.3 +* 01/01/2004 : V1.2 +******************************************************************************* + THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH + CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. + AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT + OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +#include "uart.h" + +/******************************************************************************* +* Function Name : UART_Init +* Description : This function initializes the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Output : None +* Return : None +*******************************************************************************/ +void UART_Init(UART_TypeDef *UARTx) +{ + UARTx->IER = 0x00; + UARTx->CR = 0x00; + (void)UARTx->RxBUFR; + UARTx->RxRSTR = 0xFFFF; + UARTx->TxRSTR = 0xFFFF; +} + +/******************************************************************************* +* Function Name : UART_BaudRateConfig +* Description : This function configures the baud rate of the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : The baudrate value +* Output : None +* Return : None +*******************************************************************************/ +void UART_BaudRateConfig(UART_TypeDef *UARTx, u32 BaudRate) +{ + UARTx->BR = (u16)(RCCU_FrequencyValue(RCCU_FCLK)/(16*BaudRate)); +} + +/******************************************************************************* +* Function Name : UART_Config +* Description : This function configures the baudrate, the mode, the data +* parity and the number of stop bits of the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : The baudrate value +* Input 3 : The parity type +* Input 4 : The number of stop bits +* Input 5 : The UART mode +* Output : None +* Return : None +*******************************************************************************/ +void UART_Config(UART_TypeDef *UARTx, u32 BaudRate, UARTParity_TypeDef Parity, + UARTStopBits_TypeDef StopBits, UARTMode_TypeDef Mode) +{ + UART_ModeConfig(UARTx, Mode); + UART_BaudRateConfig(UARTx, BaudRate); + UART_ParityConfig(UARTx, Parity); + UART_StopBitsConfig(UARTx, StopBits); +} + +/******************************************************************************* +* Function Name : UART_ItConfig +* Description : This function enables or disables the interrupts of the +* selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : The new interrupt flag +* Input 3 : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void UART_ItConfig(UART_TypeDef *UARTx, u16 UART_Flag, FunctionalState NewState) +{ + if (NewState==ENABLE) UARTx->IER|=UART_Flag; else UARTx->IER&=~UART_Flag; +} + +/******************************************************************************* +* Function Name : UART_FifoConfig +* Description : This function enables or disables the Rx and Tx FIFOs of +* the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void UART_FifoConfig(UART_TypeDef *UARTx, FunctionalState NewState) +{ + if (NewState==ENABLE) UARTx->CR|=0x0400; else UARTx->CR&=~0x0400; +} + +/******************************************************************************* +* Function Name : UART_FifoReset +* Description : This function resets the Rx and the Tx FIFOs of the +* selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : UART_RxFIFO or UART_TxFIFO +* Output : None +* Return : None +*******************************************************************************/ +void UART_FifoReset(UART_TypeDef *UARTx, UARTFIFO_TypeDef FIFO) +{ + if (FIFO==UART_RxFIFO) UARTx->RxRSTR=0xFFFF; else UARTx->TxRSTR=0xFFFF; +} + +/******************************************************************************* +* Function Name : UART_LoopBackConfig +* Description : This function enables or disables the loop back mode of +* the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void UART_LoopBackConfig(UART_TypeDef *UARTx, FunctionalState NewState) +{ + if (NewState==ENABLE) UARTx->CR|=0x0040; else UARTx->CR&=~0x0040; +} + +/******************************************************************************* +* Function Name : UART_RxConfig +* Description : This function enables or disables the UART data reception. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void UART_RxConfig(UART_TypeDef *UARTx, FunctionalState NewState) +{ + if (NewState==ENABLE) UARTx->CR|=0x0100; else UARTx->CR&=~0x0100; +} + +/******************************************************************************* +* Function Name : UART_OnOffConfig +* Description : This function sets On/Off the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void UART_OnOffConfig(UART_TypeDef *UARTx, FunctionalState NewState) +{ + if (NewState==ENABLE) UARTx->CR|=0x0080; else UARTx->CR&=~0x0080; +} + +/******************************************************************************* +* Function Name : UART_ByteSend +* Description : This function sends a data byte to the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : A pointer to the data byte to send +* Output : None +* Return : None +*******************************************************************************/ +void UART_ByteSend(UART_TypeDef *UARTx, u8 *Data) +{ + if (UARTx->CR & (0x0001<SR & UART_TxFull)); // while the UART_TxFIFO contain 16 characters. + else // if FIFO DISABLED + while (!(UARTx->SR & UART_TxEmpty)); // while the transmit shift register not empty + UARTx->TxBUFR = *Data; +} + +/******************************************************************************* +* Function Name : UART_9BitByteSend +* Description : This function sends a 9 bits data byte to the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : A pointer to the data to send +* Output : None +* Return : None +*******************************************************************************/ +void UART_9BitByteSend(UART_TypeDef *UARTx, u16 *Data) +{ + if(UARTx->CR & (0x0001<SR & UART_TxFull)); // while the UART_TxFIFO contain 16 characters. + else // if FIFO DISABLED + while (!(UARTx->SR & UART_TxEmpty)); // while the transmit shift register not empty + UARTx->TxBUFR = *Data; +} + +/******************************************************************************* +* Function Name : UART_DataSend +* Description : This function sends several data bytes to the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : A pointer to the data to send +* Input 3 : The data length in bytes +* Output : None +* Return : None +*******************************************************************************/ +void UART_DataSend(UART_TypeDef *UARTx, u8 *Data, u8 DataLength) +{ + while(DataLength--) + { + UART_ByteSend(UARTx,Data); + Data++; + } +} + +/******************************************************************************* +* Function Name : UART_9BitDataSend +* Description : This function sends several 9 bits data bytes to the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : A pointer to the data to send +* Input 3 : The data length +* Output : None +* Return : None +*******************************************************************************/ +void UART_9BitDataSend(UART_TypeDef *UARTx, u16 *Data, u8 DataLength) +{ + while(DataLength--) + { + UART_9BitByteSend(UARTx,Data); + Data++; + } +} + +/******************************************************************************* +* Function Name : UART_StringSend +* Description : This function sends a string to the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : A pointer to the string to send +* Output : None +* Return : None +*******************************************************************************/ +void UART_StringSend(UART_TypeDef *UARTx, u8 *String) +{ + u8 *Data=String; + while(*Data != '\0') + UART_ByteSend(UARTx, Data++); + *Data='\0'; + UART_ByteSend(UARTx, Data); +} + +/******************************************************************************* +* Function Name : UART_ByteReceive +* Description : This function gets a data byte from the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : A pointer to the buffer where the data will be stored +* Input 3 : The time-out period +* Output : The received data +* Return : The UARTx.SR register contents +*******************************************************************************/ +u16 UART_ByteReceive(UART_TypeDef *UARTx, u8 *Data, u8 TimeOut) +{ + u16 wStatus; + UARTx->TOR=TimeOut;// reload the Timeout counter + while (!((wStatus=UARTx->SR) & (UART_TimeOutIdle|UART_RxHalfFull|UART_RxBufFull)));// while the UART_RxFIFO is empty and no Timeoutidle + *Data = (u8)UARTx->RxBUFR; // then read the Receive Buffer Register + return wStatus; +} + +/******************************************************************************* +* Function Name : UART_9BitByteReceive +* Description : This function gets a 9 bits data byte from the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : A pointer to the buffer where the data will be stored +* Input 3 : The time-out period value +* Output : The received data +* Return : The UARTx.SR register contents +*******************************************************************************/ +u16 UART_9BitByteReceive(UART_TypeDef *UARTx, u16 *Data, u8 TimeOut) +{ + u16 wStatus; + UARTx->TOR=TimeOut;// reload the Timeout counter + while (!((wStatus=UARTx->SR) & (UART_TimeOutIdle|UART_RxHalfFull|UART_RxBufFull)));// while the UART_RxFIFO is empty and no Timeoutidle + *Data = (u16)UARTx->RxBUFR; // then read the RxBUFR + return wStatus; +} + +/******************************************************************************* +* Function Name : UART_DataReceive +* Description : This function gets 8 bits data bytes from the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : A pointer to the buffer where the data will be stored +* Input 3 : The data length +* Input 4 : The time-out period value +* Output : The received data +* Return : The UARTx.SR register contents +*******************************************************************************/ +u16 UART_DataReceive(UART_TypeDef *UARTx, u8 *Data, u8 DataLength, u8 TimeOut) +{ + u16 wStatus; + while(DataLength--) + wStatus=UART_ByteReceive(UARTx,Data++,TimeOut); + return wStatus; +} + +/******************************************************************************* +* Function Name : UART_9BitDataReceive +* Description : This function gets 9 bits data bytes from the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : A pointer to the buffer where the data will be stored +* Input 3 : The data length +* Input 4 : The time-out value +* Output : The received data +* Return : The UARTx.SR register contents +*******************************************************************************/ +u16 UART_9BitDataReceive(UART_TypeDef *UARTx, u16 *Data, u8 DataLength, u8 TimeOut) +{ + u16 wStatus; + while(DataLength--) + wStatus=UART_9BitByteReceive(UARTx,Data++,TimeOut); + return wStatus; +} + +/******************************************************************************* +* Function Name : UART_StringReceive +* Description : This function gets 8 bits data bytes from the selected UART. +* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART +* Input 2 : A pointer to the buffer where the string will be stored +* Output : The received string +* Return : The UARTx.SR register contents +*******************************************************************************/ +u16 UART_StringReceive(UART_TypeDef *UARTx, u8 *Data) +{ + u8 *pSTRING=Data; + u16 wStatus; + do + { + while (!((wStatus=UARTx->SR) & (UART_RxHalfFull|UART_RxBufFull)));// while the UART_RxFIFO is empty and no Timeoutidle + *(pSTRING++) = (u8)UARTx->RxBUFR; // then read the RxBUFR + } while((*(pSTRING - 1)!=0x0D)&(*(pSTRING - 1)!='\0')); + *(pSTRING - 1)='\0'; + return wStatus; +} + +#ifdef USE_SERIAL_PORT +/******************************************************************************* +* Function Name : sendchar +* Description : This function sends a character to the selected UART. +* Input 1 : A pointer to the character to send. +* Output : None +* Return : None +*******************************************************************************/ +void sendchar( char *ch ) +{ + #ifdef USE_UART0 + #define UARTx UART0 + #endif /* Use_UART0 */ + + #ifdef USE_UART1 + #define UARTx UART1 + #endif /* Use_UART1 */ + + #ifdef USE_UART2 + #define UARTx UART2 + #endif /* Use_UART2 */ + + #ifdef USE_UART3 + #define UARTx UART3 + #endif /* Use_UART3 */ + + UART_ByteSend(UARTx,(u8 *)ch); +} +#endif /* USE_SERIAL_PORT */ + +/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR71x_IAR/Library/wdg.c b/20080212/Demo/ARM7_STR71x_IAR/Library/wdg.c new file mode 100644 index 000000000..efd656c49 --- /dev/null +++ b/20080212/Demo/ARM7_STR71x_IAR/Library/wdg.c @@ -0,0 +1,83 @@ +/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** +* File Name : WDG.c +* Author : MCD Application Team +* Date First Issued : 10/24/2003 +* Description : This file provides all the WDG software functions +******************************************************************************** +* History: +* 30/11/2004 : V2.0 +* 14/07/2004 : V1.3 +* 01/01/2004 : V1.2 +******************************************************************************* + THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH + CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. + AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT + OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +#include "wdg.h" + +#ifndef abs + #define abs(x) ((x)>0 ? (x) : -(x)) +#endif + +/******************************************************************************* +* Function Name : FindFactors +* Description : Search for the best (a,b) values that fit n = a*b +* with the following constraints: 1<=a<=256, 1<=b<=65536 +* Input 1 : n: the number to decompose +* Input/Output 2 : a: a pointer to the first factor +* Input/Output 3 : b: a pointer to the second factor +* Return : None +*******************************************************************************/ +static void FindFactors(unsigned long n, unsigned int *a, unsigned long *b) +{ + unsigned long b0; + unsigned int a0; + long err, err_min=n; + + *a = a0 = ((n-1)/65536ul) + 1; + *b = b0 = n / *a; + + for (; *a <= 256; (*a)++) + { + *b = n / *a; + err = (long)*a * (long)*b - (long)n; + if (abs(err) > (*a / 2)) + { + (*b)++; + err = (long)*a * (long)*b - (long)n; + } + if (abs(err) < abs(err_min)) + { + err_min = err; + a0 = *a; + b0 = *b; + if (err == 0) break; + } + } + + *a = a0; + *b = b0; +} + +/******************************************************************************* +* Function Name : WDG_PeriodValueConfig +* Description : Set the prescaler and counter reload value +* Input : Amount of time (us) needed +* Return : None +*******************************************************************************/ +void WDG_PeriodValueConfig ( u32 Time ) +{ + unsigned int a; + unsigned long n, b; + + n = Time * (RCCU_FrequencyValue(RCCU_PCLK) / 1000000); + FindFactors(n, &a, &b); + WDG->PR = a - 1; + WDG->VR = b - 1; +} + +/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR71x_IAR/ParTest/ParTest.c b/20080212/Demo/ARM7_STR71x_IAR/ParTest/ParTest.c new file mode 100644 index 000000000..c50a2e8d0 --- /dev/null +++ b/20080212/Demo/ARM7_STR71x_IAR/ParTest/ParTest.c @@ -0,0 +1,117 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* Library includes. */ +#include "GPIO.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* Demo application includes. */ +#include "partest.h" + +/*----------------------------------------------------------- + * Simple parallel port IO routines for the LED's - which are + * connected to the second nibble of GPIO port 1. + *-----------------------------------------------------------*/ + +#define partstLED_3 0x0080 +#define partstLED_2 0x0040 +#define partstLED_1 0x0020 +#define partstLED_0 0x0010 +#define partstON_BOARD 0x0100 /* The LED built onto the KickStart board. */ + +#define partstALL_LEDs ( partstLED_0 | partstLED_1 | partstLED_2 | partstLED_3 | partstON_BOARD ) + +#define partstFIRST_LED_BIT 4 + +/* This demo application uses files that are common to all port demo +applications. These files assume 6 LED's are available, whereas I have +only 5 (including the LED built onto the development board). To prevent +two tasks trying to use the same LED a bit of remapping is performed. +The ComTest tasks will try and use LED's 6 and 7. LED 6 is ignored and +has no effect, LED 7 is mapped to LED3. The LED usage is described in +the port documentation available from the FreeRTOS.org WEB site. */ +#define partstCOM_TEST_LED 7 +#define partstRX_CHAR_LED 3 + +/*-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ + /* Configure the bits used to flash LED's on port 1 as output. */ + GPIO_Config(GPIO1, partstALL_LEDs, GPIO_OUT_OD); +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ + if( uxLED == partstCOM_TEST_LED ) + { + /* Remap as described above. */ + uxLED = partstRX_CHAR_LED; + } + + /* Adjust the LED value to map to the port pins actually being used, + then write the required value to the port. */ + uxLED += partstFIRST_LED_BIT; + GPIO_BitWrite( GPIO1, uxLED, !xValue ); +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ + if( uxLED == partstCOM_TEST_LED ) + { + /* Remap as described above. */ + uxLED = partstRX_CHAR_LED; + } + + /* Adjust the LED value to map to the port pins actually being used, + then write the opposite value to the current state to the port pin. */ + uxLED += partstFIRST_LED_BIT; + GPIO_BitWrite(GPIO1, uxLED, ~GPIO_BitRead( GPIO1, uxLED ) ); +} + + + + diff --git a/20080212/Demo/ARM7_STR71x_IAR/RTOSDemo.ewd b/20080212/Demo/ARM7_STR71x_IAR/RTOSDemo.ewd new file mode 100644 index 000000000..55ff7b44e --- /dev/null +++ b/20080212/Demo/ARM7_STR71x_IAR/RTOSDemo.ewd @@ -0,0 +1,1225 @@ + + + + 1 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 15 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IARROM_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + JLINK_ID + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 1 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$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin + 0 + + + + + + diff --git a/20080212/Demo/ARM7_STR71x_IAR/RTOSDemo.ewp b/20080212/Demo/ARM7_STR71x_IAR/RTOSDemo.ewp new file mode 100644 index 000000000..4364c7b18 --- /dev/null +++ b/20080212/Demo/ARM7_STR71x_IAR/RTOSDemo.ewp @@ -0,0 +1,1625 @@ + + + + 1 + + Debug + + ARM + + 1 + + General + 3 + + 14 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 19 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 7 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + 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$PROJ_DIR$\..\Common\Minimal\dynamic.c + + + $PROJ_DIR$\..\Common\Minimal\flash.c + + + $PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c + + + $PROJ_DIR$\..\Common\Minimal\integer.c + + + $PROJ_DIR$\main.c + + + $PROJ_DIR$\ParTest\ParTest.c + + + $PROJ_DIR$\..\Common\Minimal\PollQ.c + + + $PROJ_DIR$\..\Common\Minimal\semtest.c + + + $PROJ_DIR$\serial\serial.c + + + $PROJ_DIR$\serial\serialISR.s79 + + + + Library Source + + $PROJ_DIR$\Library\71x_lib.c + + + $PROJ_DIR$\Library\gpio.c + + + $PROJ_DIR$\Library\rccu.c + + + $PROJ_DIR$\Library\uart.c + + + $PROJ_DIR$\Library\wdg.c + + + + RTOS Source + + $PROJ_DIR$\..\..\Source\list.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\STR71x\port.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\STR71x\portasm.s79 + + + $PROJ_DIR$\..\..\Source\queue.c + + + $PROJ_DIR$\..\..\Source\tasks.c + + + + System Files + + $PROJ_DIR$\71x_init.s + + + $PROJ_DIR$\Library\71x_it.c + + + $PROJ_DIR$\71x_vect.s + + + + + diff --git a/20080212/Demo/ARM7_STR71x_IAR/RTOSDemo.eww b/20080212/Demo/ARM7_STR71x_IAR/RTOSDemo.eww new file mode 100644 index 000000000..239a9381e --- /dev/null +++ b/20080212/Demo/ARM7_STR71x_IAR/RTOSDemo.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\RTOSDemo.ewp + + + + + diff --git a/20080212/Demo/ARM7_STR71x_IAR/STR71x_FLASH.icf b/20080212/Demo/ARM7_STR71x_IAR/STR71x_FLASH.icf new file mode 100644 index 000000000..82356bda1 --- /dev/null +++ b/20080212/Demo/ARM7_STR71x_IAR/STR71x_FLASH.icf @@ -0,0 +1,42 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x40000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x4000062C; +define symbol __ICFEDIT_region_ROM_end__ = 0x4003FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x200; +define symbol __ICFEDIT_size_svcstack__ = 0x100; +define symbol __ICFEDIT_size_irqstack__ = 0x200; +define symbol __ICFEDIT_size_fiqstack__ = 0x10; +define symbol __ICFEDIT_size_undstack__ = 0x10; +define symbol __ICFEDIT_size_abtstack__ = 0x10; +define symbol __ICFEDIT_size_heap__ = 0x4; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; +define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; +define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK, + block UND_STACK, block ABT_STACK, block HEAP }; \ No newline at end of file diff --git a/20080212/Demo/ARM7_STR71x_IAR/main.c b/20080212/Demo/ARM7_STR71x_IAR/main.c new file mode 100644 index 000000000..d76acc6ef --- /dev/null +++ b/20080212/Demo/ARM7_STR71x_IAR/main.c @@ -0,0 +1,256 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. + The processor MUST be in supervisor mode when vTaskStartScheduler is + called. The demo applications included in the FreeRTOS.org download switch + to supervisor mode prior to main being called. If you are not using one of + these demo application projects then ensure Supervisor mode is used. +*/ + +/* + * Creates all the demo application tasks, then starts the scheduler. The WEB + * documentation provides more details of the demo application tasks. + * + * Main.c also creates a task called "Check". This only executes every three + * seconds but has the highest priority so is guaranteed to get processor time. + * Its main function is to check that all the other tasks are still operational. + * Each task (other than the "flash" tasks) maintains a unique count that is + * incremented each time the task successfully completes its function. Should + * any error occur within such a task the count is permanently halted. The + * check task inspects the count of each task to ensure it has changed since + * the last time the check task executed. If all the count variables have + * changed all the tasks are still executing error free, and the check task + * toggles the onboard LED. Should any task contain an error at any time + * the LED toggle rate will change from 3 seconds to 500ms. + * + */ + +/* Library includes. */ +#include "RCCU.h" +#include "wdg.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo application includes. */ +#include "flash.h" +#include "integer.h" +#include "PollQ.h" +#include "BlockQ.h" +#include "semtest.h" +#include "dynamic.h" +#include "partest.h" +#include "comtest2.h" + +/* Priorities for the demo application tasks. */ +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) + +/* Constants required by the 'Check' task. */ +#define mainNO_ERROR_FLASH_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS ) +#define mainERROR_FLASH_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS ) +#define mainCHECK_TASK_LED ( 4 ) + +/* Constants for the ComTest tasks. */ +#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 115200 ) +#define mainCOM_TEST_LED ( 6 ) /* The LED built onto the kickstart board. */ + +/* + * The task that executes at the highest priority and calls + * prvCheckOtherTasksAreStillRunning(). See the description at the top + * of the file. + */ +static void vErrorChecks( void *pvParameters ); + +/* + * Configure the processor for use with the IAR STR71x demo board. This + * just sets the PLL for the required frequency. + */ +static void prvSetupHardware( void ); + +/* + * Checks that all the demo application tasks are still executing without error + * - as described at the top of the file. Called by vErrorChecks(). + */ +static portLONG prvCheckOtherTasksAreStillRunning( void ); + + +/*-----------------------------------------------------------*/ + +/* + * Starts all the other tasks, then starts the scheduler. + */ +void main( void ) +{ + /* Setup any hardware that has not already been configured by the low + level init routines. */ + prvSetupHardware(); + + /* Initialise the LED outputs for use by the demo application tasks. */ + vParTestInitialise(); + + /* Start all the standard demo application tasks. */ + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vStartDynamicPriorityTasks(); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); + + /* Start the check task - which is defined in this file. */ + xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Start the scheduler. + + NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. + The processor MUST be in supervisor mode when vTaskStartScheduler is + called. The demo applications included in the FreeRTOS.org download switch + to supervisor mode prior to main being called. If you are not using one of + these demo application projects then ensure Supervisor mode is used here. */ + + vTaskStartScheduler(); + + /* We should never get here as control is now taken by the scheduler. */ + return; +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Setup the PLL to generate a 48MHz clock from the 4MHz CLK. */ + + /* Turn of the div by two. */ + RCCU_Div2Config( DISABLE ); + + /* 48MHz = ( 4MHz * 12 ) / 1 */ + RCCU_PLL1Config( RCCU_PLL1_Mul_12, RCCU_Div_1 ); + RCCU_RCLKSourceConfig( RCCU_PLL1_Output ); +} +/*-----------------------------------------------------------*/ + +static void vErrorChecks( void *pvParameters ) +{ +portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD; +portTickType xLastWakeTime; + + /* The parameters are not used in this task. */ + ( void ) pvParameters; + + /* Initialise xLastWakeTime to ensure the first call to vTaskDelayUntil() + functions correctly. */ + xLastWakeTime = xTaskGetTickCount(); + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. If an error is detected then the delay period + is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so + the on board LED flash rate will increase. */ + + for( ;; ) + { + /* Delay until it is time to execute again. The delay period is + shorter following an error so the LED flashes faster. */ + vTaskDelayUntil( &xLastWakeTime, xDelayPeriod ); + + /* Check all the standard demo application tasks are executing without + error. */ + if( prvCheckOtherTasksAreStillRunning() != pdPASS ) + { + /* An error has been detected in one of the tasks - flash faster. */ + xDelayPeriod = mainERROR_FLASH_PERIOD; + } + + vParTestToggleLED( mainCHECK_TASK_LED ); + } +} +/*-----------------------------------------------------------*/ + +static portLONG prvCheckOtherTasksAreStillRunning( void ) +{ +portLONG lReturn = ( portLONG ) pdPASS; + + /* Check all the demo tasks (other than the flash tasks) to ensure + that they are all still running, and that none of them have detected + an error. */ + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + return lReturn; +} +/*-----------------------------------------------------------*/ + + diff --git a/20080212/Demo/ARM7_STR71x_IAR/serial/serial.c b/20080212/Demo/ARM7_STR71x_IAR/serial/serial.c new file mode 100644 index 000000000..201473a31 --- /dev/null +++ b/20080212/Demo/ARM7_STR71x_IAR/serial/serial.c @@ -0,0 +1,252 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0. +*/ + +/* Library includes. */ +#include "uart.h" +#include "gpio.h" +#include "eic.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "queue.h" + +/* Demo application includes. */ +#include "serial.h" + +#define UART0_Rx_Pin ( 0x0001<< 8 ) +#define UART0_Tx_Pin ( 0x0001<< 9 ) + +#define serINVALID_QUEUE ( ( xQueueHandle ) 0 ) +#define serNO_BLOCK ( ( portTickType ) 0 ) + +/* Macros to turn on and off the Tx empty interrupt. */ +#define serINTERRUPT_ON() UART0->IER |= UART_TxHalfEmpty +#define serINTERRUPT_OFF() UART0->IER &= ~UART_TxHalfEmpty + +/*-----------------------------------------------------------*/ + +/* Queues used to hold received characters, and characters waiting to be +transmitted. */ +static xQueueHandle xRxedChars; +static xQueueHandle xCharsForTx; + +/*-----------------------------------------------------------*/ + +/* Interrupt entry point written in the assembler file serialISR.s79. */ +extern void vSerialISREntry( void ); + +/* The interrupt service routine - called from the assembly entry point. */ +__arm void vSerialISR( void ); + +/*-----------------------------------------------------------*/ + +/* + * See the serial2.h header file. + */ +xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) +{ +xComPortHandle xReturn; + + /* Create the queues used to hold Rx and Tx characters. */ + xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + + /* If the queues were created correctly then setup the serial port + hardware. */ + if( ( xRxedChars != serINVALID_QUEUE ) && ( xCharsForTx != serINVALID_QUEUE ) ) + { + portENTER_CRITICAL(); + { + /* Setup the UART port pins. */ + GPIO_Config( GPIO0, UART0_Tx_Pin, GPIO_AF_PP ); + GPIO_Config( GPIO0, UART0_Rx_Pin, GPIO_IN_TRI_CMOS ); + + /* Configure the UART. */ + UART_OnOffConfig( UART0, ENABLE ); + UART_FifoConfig( UART0, DISABLE ); + UART_FifoReset( UART0, UART_RxFIFO ); + UART_FifoReset( UART0, UART_TxFIFO ); + UART_LoopBackConfig(UART0, DISABLE ); + UART_Config( UART0, ulWantedBaud, UART_NO_PARITY, UART_1_StopBits, UARTM_8D ); + UART_RxConfig( UART0, ENABLE ); + + /* Configure the IEC for the UART interrupts. */ + EIC_IRQChannelPriorityConfig( UART0_IRQChannel, 1 ); + EIC_IRQChannelConfig( UART0_IRQChannel, ENABLE ); + EIC_IRQConfig( ENABLE ); + UART_ItConfig( UART0, UART_RxBufFull, ENABLE ); + } + portEXIT_CRITICAL(); + } + else + { + xReturn = ( xComPortHandle ) 0; + } + + /* This demo file only supports a single port but we have to return + something to comply with the standard demo header file. */ + return xReturn; +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) +{ + /* The port handle is not required as this driver only supports one port. */ + ( void ) pxPort; + + /* Get the next character from the buffer. Return false if no characters + are available, or arrive before xBlockTime expires. */ + if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) + { + return pdTRUE; + } + else + { + return pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength ) +{ +signed portCHAR *pxNext; + + /* A couple of parameters that this port does not use. */ + ( void ) usStringLength; + ( void ) pxPort; + + /* NOTE: This implementation does not handle the queue being full as no + block time is used! */ + + /* The port handle is not required as this driver only supports UART0. */ + ( void ) pxPort; + + /* Send each character in the string, one at a time. */ + pxNext = ( signed portCHAR * ) pcString; + while( *pxNext ) + { + xSerialPutChar( pxPort, *pxNext, serNO_BLOCK ); + pxNext++; + } +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) +{ + /* Place the character in the queue of characters to be transmitted. */ + if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) + { + return pdFAIL; + } + + /* Turn on the Tx interrupt so the ISR will remove the character from the + queue and send it. This does not need to be in a critical section as + if the interrupt has already removed the character the next interrupt + will simply turn off the Tx interrupt again. */ + serINTERRUPT_ON(); + + return pdPASS; +} +/*-----------------------------------------------------------*/ + +void vSerialClose( xComPortHandle xPort ) +{ + /* Not supported as not required by the demo application. */ +} +/*-----------------------------------------------------------*/ + +/* Serial port ISR. This can cause a context switch so is not defined as a +standard ISR using the __irq keyword. Instead a wrapper function is defined +within serialISR.s79 which in turn calls this function. See the port +documentation on the FreeRTOS.org website for more information. */ +__arm void vSerialISR( void ) +{ +unsigned portSHORT usStatus; +signed portCHAR cChar; +portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByPost = pdFALSE; + + /* What caused the interrupt? */ + usStatus = UART_FlagStatus( UART0 ); + + if( usStatus & UART_TxHalfEmpty ) + { + /* The interrupt was caused by the THR becoming empty. Are there any + more characters to transmit? */ + if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE ) + { + /* A character was retrieved from the queue so can be sent to the + THR now. */ + UART0->TxBUFR = cChar; + } + else + { + /* Queue empty, nothing to send so turn off the Tx interrupt. */ + serINTERRUPT_OFF(); + } + } + + if( usStatus & UART_RxBufFull ) + { + /* The interrupt was caused by a character being received. Grab the + character from the RHR and place it in the queue of received + characters. */ + cChar = UART0->RxBUFR; + xTaskWokenByPost = xQueueSendFromISR( xRxedChars, &cChar, xTaskWokenByPost ); + } + + /* If a task was woken by either a character being received or a character + being transmitted then we may need to switch to another task. */ + portEND_SWITCHING_ISR( ( xTaskWokenByPost || xTaskWokenByTx ) ); + + /* End the interrupt in the EIC. */ + portCLEAR_EIC(); +} + + + + + + diff --git a/20080212/Demo/ARM7_STR71x_IAR/serial/serialISR.s79 b/20080212/Demo/ARM7_STR71x_IAR/serial/serialISR.s79 new file mode 100644 index 000000000..da0a0bd17 --- /dev/null +++ b/20080212/Demo/ARM7_STR71x_IAR/serial/serialISR.s79 @@ -0,0 +1,24 @@ + RSEG ICODE:CODE + CODE32 + + EXTERN vSerialISR + PUBLIC vSerialISREntry + +; Wrapper for the serial port interrupt service routine. This can cause a +; context switch so requires an assembly wrapper. + +; Defines the portSAVE_CONTEXT and portRESTORE_CONTEXT macros. +#include "ISR_Support.h" + +vSerialISREntry: + + portSAVE_CONTEXT ; Save the context of the current task. + + bl vSerialISR ; Call the ISR routine. + + portRESTORE_CONTEXT ; Restore the context of the current task - + ; which may be different to the task that + ; was interrupted. + + END + diff --git a/20080212/Demo/ARM7_STR71x_IAR/settings/RTOSDemo.dbgdt b/20080212/Demo/ARM7_STR71x_IAR/settings/RTOSDemo.dbgdt new file mode 100644 index 000000000..7e27d3f4d --- /dev/null +++ b/20080212/Demo/ARM7_STR71x_IAR/settings/RTOSDemo.dbgdt @@ -0,0 +1,81 @@ + + + + + + + + + + + + 273272727 + + + + + + + + 200 + + + + 010 + + + + + + + 20115330776 + 200 + + + + + + + TabID-24393-22702 + Workspace + Workspace + + + RTOSDemoRTOSDemo/Demo SourceRTOSDemo/RTOS SourceRTOSDemo/System FilesRTOSDemo/System Files/vect.s79 + + + + 0 + + + TabID-13122-22708 + Debug Log + Debug-Log + + + + TabID-23870-22711 + Build + Build + + + TabID-19116-28152BreakpointsBreakpoints + + 0TabID-10802-25870DisassemblyDisassembly0 + + + + + + TextEditorC:\E\Dev\FreeRTOS\Demo\ARM7_STR71x_IAR\main.c010449004900TextEditorC:\E\Dev\FreeRTOS\Demo\ARM7_STR71x_IAR\Library\71x_it.c0482578257810100000010000001 + + + + + + + iaridepm.enu1debuggergui.enu1-2-2746347-2-210911077857112016249286761711-2-2746198-2-2200200142857203666142857761711-2-21921402-2-21404194100285719755677857112016 + + + + diff --git a/20080212/Demo/ARM7_STR71x_IAR/settings/RTOSDemo.dni b/20080212/Demo/ARM7_STR71x_IAR/settings/RTOSDemo.dni new file mode 100644 index 000000000..3062e860f --- /dev/null +++ b/20080212/Demo/ARM7_STR71x_IAR/settings/RTOSDemo.dni @@ -0,0 +1,39 @@ +[DisAssemblyWindow] +NumStates=_ 1 +State 1=_ 1 +[JLinkDriver] +WatchVectorCatch=_ 0 +WatchCond=_ 0 +Watch0=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0 +Watch1=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0 +[Low Level] +Pipeline mode=0 +Initialized=0 +[CodeCoverage] +Enabled=_ 0 +[Profiling] +Enabled=0 +[StackPlugin] +Enabled=1 +OverflowWarningsEnabled=1 +WarningThreshold=90 +SpWarningsEnabled=1 +WarnHow=0 +UseTrigger=1 +TriggerName=main +LimitSize=0 +ByteLimit=50 +[Log file] +LoggingEnabled=_ 0 +LogFile=_ "" +Category=_ 0 +[TermIOLog] +LoggingEnabled=_ 0 +LogFile=_ "" +[Disassemble mode] +mode=0 +[Breakpoints] +Count=0 +[TraceHelper] +Enabled=0 +ShowSource=1 diff --git a/20080212/Demo/ARM7_STR71x_IAR/settings/RTOSDemo.wsdt b/20080212/Demo/ARM7_STR71x_IAR/settings/RTOSDemo.wsdt new file mode 100644 index 000000000..f34de69b6 --- /dev/null +++ b/20080212/Demo/ARM7_STR71x_IAR/settings/RTOSDemo.wsdt @@ -0,0 +1,75 @@ + + + + + + RTOSDemo/Release + + + + + + + + + 189272727 + + + + + + + 20115330776 + + + + 10 + + + + + + + TabID-14962-21036 + Workspace + Workspace + + + RTOSDemoRTOSDemo/source + + + + 0 + + + TabID-24623-22493 + Build + Build + + + + TabID-13645-22698 + Debug Log + Debug-Log + + + TabID-25855-25419BreakpointsBreakpoints + + 0 + + + + + + TextEditorC:\E\Dev\FreeRTOS\Demo\ARM7_STR71x_IAR\main.c01044900490000100000010000001 + + + + + + + iaridepm.enu1-2-2590263-2-218181285718330189286602851-2-23481402-2-2140435010028573564151285718330 + + + + diff --git a/20080212/Demo/ARM7_STR75x_GCC/FreeRTOSConfig.h b/20080212/Demo/ARM7_STR75x_GCC/FreeRTOSConfig.h new file mode 100644 index 000000000..79b26ee13 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_GCC/FreeRTOSConfig.h @@ -0,0 +1,87 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include <75x_lib.h> + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 60000000 ) /* Timer clock. */ +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 100 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) 12800 ) +#define configMAX_TASK_NAME_LEN ( 16 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/ARM7_STR75x_GCC/ParTest/ParTest.c b/20080212/Demo/ARM7_STR75x_GCC/ParTest/ParTest.c new file mode 100644 index 000000000..85766ae12 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_GCC/ParTest/ParTest.c @@ -0,0 +1,147 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* Library includes. */ +#include "75x_GPIO.h" +#include "75x_map.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* Demo application includes. */ +#include "partest.h" + +/*----------------------------------------------------------- + * Simple parallel port IO routines for the LED's + *-----------------------------------------------------------*/ + +#define partstNUM_LEDS 4 + +typedef struct GPIOMAP +{ + GPIO_TypeDef *pxPort; + unsigned portLONG ulPin; + unsigned portLONG ulValue; +} GPIO_MAP; + +static GPIO_MAP xLEDMap[ partstNUM_LEDS ] = +{ + { ( GPIO_TypeDef * )GPIO1_BASE, GPIO_Pin_1, 0UL }, + { ( GPIO_TypeDef * )GPIO0_BASE, GPIO_Pin_16, 0UL }, + { ( GPIO_TypeDef * )GPIO2_BASE, GPIO_Pin_18, 0UL }, + { ( GPIO_TypeDef * )GPIO2_BASE, GPIO_Pin_19, 0UL } +}; + +/*-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ +GPIO_InitTypeDef GPIO_InitStructure ; + + /* Configure the bits used to flash LED's on port 1 as output. */ + + /* Configure LED3 */ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_16; + GPIO_Init(GPIO0,&GPIO_InitStructure); + + /* Configure LED2 */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1; + GPIO_Init(GPIO1, &GPIO_InitStructure); + + /* Configure LED4 and LED5 */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_18 | GPIO_Pin_19; + GPIO_Init(GPIO2, &GPIO_InitStructure); + + vParTestSetLED( 0, 0 ); + vParTestSetLED( 1, 0 ); + vParTestSetLED( 2, 0 ); + vParTestSetLED( 3, 0 ); +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ + if( uxLED < partstNUM_LEDS ) + { + portENTER_CRITICAL(); + { + if( xValue ) + { + GPIO_WriteBit( xLEDMap[ uxLED ].pxPort, xLEDMap[ uxLED ].ulPin, Bit_RESET ); + xLEDMap[ uxLED ].ulValue = 0; + } + else + { + GPIO_WriteBit( xLEDMap[ uxLED ].pxPort, xLEDMap[ uxLED ].ulPin, Bit_SET ); + xLEDMap[ uxLED ].ulValue = 1; + } + } + portEXIT_CRITICAL(); + } +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ + if( uxLED < partstNUM_LEDS ) + { + portENTER_CRITICAL(); + { + if( xLEDMap[ uxLED ].ulValue == 1 ) + { + GPIO_WriteBit( xLEDMap[ uxLED ].pxPort, xLEDMap[ uxLED ].ulPin, Bit_RESET ); + xLEDMap[ uxLED ].ulValue = 0; + } + else + { + GPIO_WriteBit( xLEDMap[ uxLED ].pxPort, xLEDMap[ uxLED ].ulPin, Bit_SET ); + xLEDMap[ uxLED ].ulValue = 1; + } + } + portEXIT_CRITICAL(); + } +} + + + + diff --git a/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_adc.h b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_adc.h new file mode 100644 index 000000000..bce23f731 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_adc.h @@ -0,0 +1,177 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_adc.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* ADC software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_ADC_H +#define __75x_ADC_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* ADC Init structure definition */ +typedef struct +{ + u16 ADC_ConversionMode; + u16 ADC_ExtTrigger; + u16 ADC_AutoClockOff; + u8 ADC_SamplingPrescaler; + u8 ADC_ConversionPrescaler; + u8 ADC_FirstChannel; + u8 ADC_ChannelNumber; + }ADC_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* ADC control status flags */ +#define ADC_FLAG_ECH 0x0001 +#define ADC_FLAG_EOC 0x0002 +#define ADC_FLAG_JECH 0x0004 +#define ADC_FLAG_JEOC 0x0008 +#define ADC_FLAG_AnalogWatchdog0_LowThreshold 0x0010 +#define ADC_FLAG_AnalogWatchdog0_HighThreshold 0x0020 +#define ADC_FLAG_AnalogWatchdog1_LowThreshold 0x0040 +#define ADC_FLAG_AnalogWatchdog1_HighThreshold 0x0080 +#define ADC_FLAG_AnalogWatchdog2_LowThreshold 0x0100 +#define ADC_FLAG_AnalogWatchdog2_HighThreshold 0x0200 +#define ADC_FLAG_AnalogWatchdog3_LowThreshold 0x0400 +#define ADC_FLAG_AnalogWatchdog3_HighThreshold 0x0800 + +/* ADC Interrupt sources */ +#define ADC_IT_ECH 0x0001 +#define ADC_IT_EOC 0x0002 +#define ADC_IT_JECH 0x0004 +#define ADC_IT_JEOC 0x0008 +#define ADC_IT_AnalogWatchdog0_LowThreshold 0x0010 +#define ADC_IT_AnalogWatchdog0_HighThreshold 0x0020 +#define ADC_IT_AnalogWatchdog1_LowThreshold 0x0040 +#define ADC_IT_AnalogWatchdog1_HighThreshold 0x0080 +#define ADC_IT_AnalogWatchdog2_LowThreshold 0x0100 +#define ADC_IT_AnalogWatchdog2_HighThreshold 0x0200 +#define ADC_IT_AnalogWatchdog3_LowThreshold 0x0400 +#define ADC_IT_AnalogWatchdog3_HighThreshold 0x0800 +#define ADC_IT_ALL 0x0FFF + +/* ADC Watchdogs Thresholds */ +#define ADC_AnalogWatchdog0 0x0030 +#define ADC_AnalogWatchdog1 0x00C0 +#define ADC_AnalogWatchdog2 0x0300 +#define ADC_AnalogWatchdog3 0x0C00 + +/* ADC Channels */ +#define ADC_CHANNEL0 0x0 +#define ADC_CHANNEL1 0x1 +#define ADC_CHANNEL2 0x2 +#define ADC_CHANNEL3 0x3 +#define ADC_CHANNEL4 0x4 +#define ADC_CHANNEL5 0x5 +#define ADC_CHANNEL6 0x6 +#define ADC_CHANNEL7 0x7 +#define ADC_CHANNEL8 0x8 +#define ADC_CHANNEL9 0x9 +#define ADC_CHANNEL10 0xA +#define ADC_CHANNEL11 0xB +#define ADC_CHANNEL12 0xC +#define ADC_CHANNEL13 0xD +#define ADC_CHANNEL14 0xE +#define ADC_CHANNEL15 0xF + +/* ADC DMA Channels */ +#define ADC_DMA_CHANNEL0 0x0001 +#define ADC_DMA_CHANNEL1 0x0002 +#define ADC_DMA_CHANNEL2 0x0004 +#define ADC_DMA_CHANNEL3 0x0008 +#define ADC_DMA_CHANNEL4 0x0010 +#define ADC_DMA_CHANNEL5 0x0020 +#define ADC_DMA_CHANNEL6 0x0040 +#define ADC_DMA_CHANNEL7 0x0080 +#define ADC_DMA_CHANNEL8 0x0100 +#define ADC_DMA_CHANNEL9 0x0200 +#define ADC_DMA_CHANNEL10 0x0400 +#define ADC_DMA_CHANNEL11 0x0800 +#define ADC_DMA_CHANNEL12 0x1000 +#define ADC_DMA_CHANNEL13 0x2000 +#define ADC_DMA_CHANNEL14 0x4000 +#define ADC_DMA_CHANNEL15 0x8000 + +/* Trigger conversion detection */ +#define ADC_ExtTrigger_LowLevel 0x4FFF +#define ADC_ExtTrigger_HighLevel 0x5000 +#define ADC_ExtTrigger_FallingEdge 0x6000 +#define ADC_ExtTrigger_RisingEdge 0x7000 +#define ADC_ExtTrigger_Disable 0x8FFF + +/* DMA enable config */ +#define ADC_DMA_ExtTrigger_HighLevel 0x6000 +#define ADC_DMA_ExtTrigger_LowLevel 0x4FFF +#define ADC_DMA_Enable 0x8000 +#define ADC_DMA_Disable 0x3FFF + +/* Injected Trigger conversion detection */ +#define ADC_Injec_ExtTrigger_RisingEdge 0x6000 +#define ADC_Injec_ExtTrigger_FallingEdge 0xDFFF +#define ADC_Injec_ExtTrigger_Disable 0x3FFF + +/* Start Conversion */ +#define ADC_Conversion_Start 0x0001 +#define ADC_Conversion_Stop 0xFFFE + +/* ADC Conversion Modes */ +#define ADC_ConversionMode_Scan 0x8000 +#define ADC_ConversionMode_OneShot 0x7FFF + +/* Auto Clock Off */ +#define ADC_AutoClockOff_Enable 0x4000 +#define ADC_AutoClockOff_Disable 0xBFFF + +/* Calibration */ +#define ADC_Calibration_ON 0x0002 +#define ADC_CalibAverage_Disable 0x0020 +#define ADC_CalibAverage_Enable 0xFFDF + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +void ADC_DeInit(void); +void ADC_Init(ADC_InitTypeDef *ADC_InitStruct); +void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct); +void ADC_Cmd(FunctionalState NewState); +void ADC_StartCalibration(u16 ADC_CalibAverage); +FlagStatus ADC_GetCalibrationStatus(void); +void ADC_ConversionCmd(u16 ADC_Conversion); +FlagStatus ADC_GetSTARTBitStatus(void); +void ADC_AutoClockOffConfig(FunctionalState NewState); +u16 ADC_GetConversionValue(u8 ADC_CHANNEL); +void ADC_ITConfig(u16 ADC_IT, FunctionalState NewState); +void ADC_AnalogWatchdogConfig(u16 ADC_AnalogWatchdog, u8 ADC_CHANNEL, + u16 LowThreshold, u16 HighThreshold); +void ADC_AnalogWatchdogCmd(u16 ADC_AnalogWatchdog, FunctionalState NewState); +u16 ADC_GetAnalogWatchdogResult(u16 ADC_AnalogWatchdog); +void ADC_StartInjectedConversion(void); +void ADC_InjectedConversionConfig(u16 ADC_Injec_ExtTrigger, u8 FirstChannel, u8 ChannelNumber); +void ADC_DMAConfig(u16 ADC_DMA_CHANNEL, FunctionalState NewState); +void ADC_DMACmd(u16 ADC_DMA); +u16 ADC_GetDMAFirstEnabledChannel(void); +FlagStatus ADC_GetFlagStatus(u16 ADC_FLAG); +void ADC_ClearFlag(u16 ADC_FLAG); +ITStatus ADC_GetITStatus(u16 ADC_IT); +void ADC_ClearITPendingBit(u16 ADC_IT); + +#endif /*__75x_ADC_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_can.h b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_can.h new file mode 100644 index 000000000..9b630ee0c --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_can.h @@ -0,0 +1,165 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_can.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* CAN bus software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_CAN_H +#define __75x_CAN_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +/* Exported types ------------------------------------------------------------*/ + +/* CAN Init structure define */ +typedef struct +{ + u8 CAN_ConfigParameters; + u32 CAN_Bitrate; +}CAN_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* Standard bitrates available*/ +enum +{ + CAN_BITRATE_100K, + CAN_BITRATE_125K, + CAN_BITRATE_250K, + CAN_BITRATE_500K, + CAN_BITRATE_1M +}; + +/* Control register*/ +#define CAN_CR_TEST 0x0080 +#define CAN_CR_CCE 0x0040 +#define CAN_CR_DAR 0x0020 +#define CAN_CR_EIE 0x0008 +#define CAN_CR_SIE 0x0004 +#define CAN_CR_IE 0x0002 +#define CAN_CR_INIT 0x0001 + +/* Status register */ +#define CAN_SR_BOFF 0x0080 +#define CAN_SR_EWARN 0x0040 +#define CAN_SR_EPASS 0x0020 +#define CAN_SR_RXOK 0x0010 +#define CAN_SR_TXOK 0x0008 +#define CAN_SR_LEC 0x0007 + +/* Test register*/ +#define CAN_TESTR_RX 0x0080 +#define CAN_TESTR_TX1 0x0040 +#define CAN_TESTR_TX0 0x0020 +#define CAN_TESTR_LBACK 0x0010 +#define CAN_TESTR_SILENT 0x0008 +#define CAN_TESTR_BASIC 0x0004 + +/* IFn / Command Request register*/ +#define CAN_CRR_BUSY 0x8000 + +/* IFn / Command Mask register*/ +#define CAN_CMR_WRRD 0x0080 +#define CAN_CMR_MASK 0x0040 +#define CAN_CMR_ARB 0x0020 +#define CAN_CMR_CONTROL 0x0010 +#define CAN_CMR_CLRINTPND 0x0008 +#define CAN_CMR_TXRQSTNEWDAT 0x0004 +#define CAN_CMR_DATAA 0x0002 +#define CAN_CMR_DATAB 0x0001 + +/* IFn / Mask 2 register*/ +#define CAN_M2R_MXTD 0x8000 +#define CAN_M2R_MDIR 0x4000 + +/* IFn / Arbitration 2 register*/ +#define CAN_A2R_MSGVAL 0x8000 +#define CAN_A2R_XTD 0x4000 +#define CAN_A2R_DIR 0x2000 + +/* IFn / Message Control register*/ +#define CAN_MCR_NEWDAT 0x8000 +#define CAN_MCR_MSGLST 0x4000 +#define CAN_MCR_INTPND 0x2000 +#define CAN_MCR_UMASK 0x1000 +#define CAN_MCR_TXIE 0x0800 +#define CAN_MCR_RXIE 0x0400 +#define CAN_MCR_RMTEN 0x0200 +#define CAN_MCR_TXRQST 0x0100 +#define CAN_MCR_EOB 0x0080 + + +/* Wake-up modes*/ +enum +{ + CAN_WAKEUP_ON_EXT, + CAN_WAKEUP_ON_CAN +}; + + +/* CAN message structure*/ +typedef struct +{ + u32 IdType; + u32 Id; + u8 Dlc; + u8 Data[8]; +} canmsg; + +/* Message ID types*/ +enum +{ + CAN_STD_ID, + CAN_EXT_ID +}; + +/* Message ID limits*/ + +#define CAN_LAST_STD_ID ((1<<11) - 1) +#define CAN_LAST_EXT_ID ((1L<<29) - 1) + +/* Exported functions ------------------------------------------------------- */ + +void CAN_Init (CAN_InitTypeDef *CAN_InitStruct); +void CAN_DeInit (void); +void CAN_StructInit(CAN_InitTypeDef *CAN_InitStruct); +void CAN_SetBitrate(u32 bitrate); +void CAN_SetTiming(u32 tseg1, u32 tseg2, u32 sjw, u32 brp); +ErrorStatus CAN_SetUnusedMsgObj(u32 msgobj); +ErrorStatus CAN_SetTxMsgObj(u32 msgobj, u32 idType); +ErrorStatus CAN_SetRxMsgObj(u32 msgobj, u32 idType, u32 idLow, u32 idHigh, bool singleOrFifoLast); +void CAN_InvalidateAllMsgObj(void); +ErrorStatus CAN_ReleaseMessage(u32 msgobj); +ErrorStatus CAN_SendMessage(u32 msgobj, canmsg* pCanMsg); +ErrorStatus CAN_ReceiveMessage(u32 msgobj, bool release, canmsg* pCanMsg); +ErrorStatus CAN_WaitEndOfTx(void); +ErrorStatus CAN_BasicSendMessage(canmsg* pCanMsg); +ErrorStatus CAN_BasicReceiveMessage(canmsg* pCanMsg); +void CAN_EnterTestMode(u8 TestMask); +void CAN_EnterInitMode(u8 InitMask); +void CAN_LeaveInitMode(void); +void CAN_LeaveTestMode(void); +void CAN_ReleaseTxMessage(u32 msgobj); +void CAN_ReleaseRxMessage(u32 msgobj); +u32 CAN_IsMessageWaiting(u32 msgobj); +u32 CAN_IsTransmitRequested(u32 msgobj); +u32 CAN_IsInterruptPending(u32 msgobj); +u32 CAN_IsObjectValid(u32 msgobj); + +#endif /* __75x_CAN_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_cfg.h b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_cfg.h new file mode 100644 index 000000000..e1042a246 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_cfg.h @@ -0,0 +1,48 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_cfg.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* CFG software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_CFG_H +#define __75x_CFG_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +#define CFG_BootSpace_FLASH 0x00000000 +#define CFG_BootSpace_SRAM 0x00000002 +#define CFG_BootSpace_ExtSMI 0x00000003 + +#define CFG_FLASHBurst_Disable 0xFFFFFEFF +#define CFG_FLASHBurst_Enable 0x00000100 + +#define CFG_USBFilter_Disable 0xFFFFFDFF +#define CFG_USBFilter_Enable 0x00000200 + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void CFG_BootSpaceConfig(u32 CFG_BootSpace); +void CFG_FLASHBurstConfig(u32 CFG_FLASHBurst); +void CFG_USBFilterConfig(u32 CFG_USBFilter); +FlagStatus CFG_GetFlagStatus(void); + +#endif /* __75x_CFG_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_conf.h b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_conf.h new file mode 100644 index 000000000..ab3c5394f --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_conf.h @@ -0,0 +1,106 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_conf.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : Library configuration file. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_CONF_H +#define __75x_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Comment the line below to compile the library in release mode */ +//#define DEBUG + +/************************************* SMI ************************************/ +//#define _SMI + +/************************************* CFG ************************************/ +#define _CFG + +/************************************* MRCC ************************************/ +#define _MRCC + +/************************************* ADC ************************************/ +//#define _ADC + +/************************************* TB *************************************/ +#define _TB + +/************************************* TIM ************************************/ +#define _TIM +#define _TIM0 +#define _TIM1 +#define _TIM2 + +/************************************* PWM ************************************/ +#define _PWM + +/************************************* WDG ************************************/ +#define _WDG + +/************************************* SSP ************************************/ +//#define _SSP +//#define _SSP0 +//#define _SSP1 + +/************************************* CAN ************************************/ +//#define _CAN + +/************************************* I2C ************************************/ +//#define _I2C + +/************************************* UART ***********************************/ +#define _UART +#define _UART0 +#define _UART1 +#define _UART2 + +/************************************* GPIO ***********************************/ +#define _GPIO +#define _GPIO0 +#define _GPIO1 +#define _GPIO2 +#define _GPIOREMAP + +/************************************* DMA ************************************/ +//#define _DMA +//#define _DMA_Stream0 +//#define _DMA_Stream1 +//#define _DMA_Stream2 +//#define _DMA_Stream3 + +/************************************* RTC ************************************/ +//#define _RTC + +/************************************* EXTIT **********************************/ +#define _EXTIT + +/************************************* EIC ************************************/ +#define _EIC + +/* Comment the following line, depending on the external Quartz oscillator used + in your application */ +#define Main_Oscillator 4000000 /* 4 MHz Quartz oscillator used */ +//#define Main_Oscillator 8000000 /* 8 MHz Quartz oscillator used */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +#endif /* __75x_CONF_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_dma.h b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_dma.h new file mode 100644 index 000000000..f71b1cad4 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_dma.h @@ -0,0 +1,140 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_dma.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* DMA software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion ------------------------------------ */ +#ifndef __75x_DMA_H +#define __75x_DMA_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* DMA Init structure definition */ +typedef struct +{ + u32 DMA_SRCBaseAddr; + u32 DMA_DSTBaseAddr; + u16 DMA_BufferSize; + u16 DMA_SRC; + u16 DMA_DST; + u16 DMA_SRCSize; + u16 DMA_SRCBurst; + u16 DMA_DSTSize; + u16 DMA_Mode; + u16 DMA_M2M; + u16 DMA_DIR; +}DMA_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* DMA interrupt Mask */ +#define DMA_IT_SI0 0x0001 +#define DMA_IT_SI1 0x0002 +#define DMA_IT_SI2 0x0004 +#define DMA_IT_SI3 0x0008 +#define DMA_IT_SE0 0x0010 +#define DMA_IT_SE1 0x0020 +#define DMA_IT_SE2 0x0040 +#define DMA_IT_SE3 0x0080 +#define DMA_IT_ALL 0x00FF + +/* DMA Flags */ +#define DMA_FLAG_SI0 0x0001 +#define DMA_FLAG_SI1 0x0002 +#define DMA_FLAG_SI2 0x0004 +#define DMA_FLAG_SI3 0x0008 +#define DMA_FLAG_SE0 0x0010 +#define DMA_FLAG_SE1 0x0020 +#define DMA_FLAG_SE2 0x0040 +#define DMA_FLAG_SE3 0x0080 +#define DMA_FLAG_ACT0 0x0100 +#define DMA_FLAG_ACT1 0x0200 +#define DMA_FLAG_ACT2 0x0400 +#define DMA_FLAG_ACT3 0x0800 + +/* DMA Increment Current Source Register */ +#define DMA_SRC_INCR 0x0002 +#define DMA_SRC_NOT_INCR 0xFFFD + +/* DMA Increment Current Destination Register */ +#define DMA_DST_INCR 0x0004 +#define DMA_DST_NOT_INCR 0xFFFB + +/* Source to DMA data width */ +#define DMA_SRCSize_Byte 0x0000 +#define DMA_SRCSize_HalfWord 0x0008 +#define DMA_SRCSize_Word 0x0010 + +/* DMA source burst size */ +#define DMA_SRCBurst_1Data 0x0000 +#define DMA_SRCBurst_4Data 0x0020 +#define DMA_SRCBurst_8Data 0x0040 +#define DMA_SRCBurst_16Data 0x0060 + +/* DMA destination data width */ +#define DMA_DSTSize_Byte 0x0000 +#define DMA_DSTSize_HalfWord 0x0080 +#define DMA_DSTSize_Word 0x0100 + +/* DMA mode */ +#define DMA_Mode_Circular 0x0200 +#define DMA_Mode_Normal 0xFDFF + +/* Memory to Memory Transfer */ +#define DMA_M2M_Enable 0x0800 +#define DMA_M2M_Disable 0xF7FF + +/* Direction Transfer */ +#define DMA_DIR_PeriphDST 0x2000 +#define DMA_DIR_PeriphSRC 0xDFFF + +/* DMA streamx Registers */ +#define DMA_SOURCEL 0x00000000 /* source base address low register */ +#define DMA_SOURCEH 0x00000004 /* source base address high register */ +#define DMA_DESTL 0x00000008 /* destination base address low register */ +#define DMA_DESTH 0x0000000C /* destination base address high register */ +#define DMA_MAX 0x00000010 /* Maximum count register */ +#define DMA_CTRL 0x00000014 /* Control register */ +#define DMA_SOCURRH 0x00000018 /* Current Source address high register */ +#define DMA_SOCURRL 0x0000001C /* Current Source address low register */ +#define DMA_DECURRH 0x00000020 /* Current Destination address high register */ +#define DMA_DECURRL 0x00000024 /* Current Destination address low register */ +#define DMA_TCNT 0x00000028 /* Terminal Counter Register */ +#define DMA_LUBUFF 0x0000002C /* Last Used Buffer location */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void DMA_DeInit(DMA_Stream_TypeDef* DMA_Streamx); +void DMA_Init(DMA_Stream_TypeDef* DMA_Streamx, DMA_InitTypeDef* DMA_InitStruct); +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); +void DMA_Cmd(DMA_Stream_TypeDef* DMA_Streamx, FunctionalState NewState); +void DMA_ITConfig(u16 DMA_IT, FunctionalState NewState); +u32 DMA_GetCurrDSTAddr(DMA_Stream_TypeDef* DMA_Streamx); +u32 DMA_GetCurrSRCAddr(DMA_Stream_TypeDef* DMA_Streamx); +u16 DMA_GetTerminalCounter(DMA_Stream_TypeDef* DMA_Streamx); +void DMA_LastBufferSweepConfig(DMA_Stream_TypeDef* DMA_Streamx, FunctionalState NewState); +void DMA_LastBufferAddrConfig(DMA_Stream_TypeDef* DMA_Streamx, u16 DMA_LastBufferAddr); +FlagStatus DMA_GetFlagStatus(u16 DMA_FLAG); +void DMA_ClearFlag(u16 DMA_FLAG); +ITStatus DMA_GetITStatus(u16 DMA_IT); +void DMA_ClearITPendingBit(u16 DMA_IT); + +#endif /* __75x_DMA_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_eic.h b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_eic.h new file mode 100644 index 000000000..c7e6a07cf --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_eic.h @@ -0,0 +1,97 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_eic.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* EIC software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_EIC_H +#define __75x_EIC_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +/* Exported types ------------------------------------------------------------*/ +typedef struct +{ + u8 EIC_IRQChannel; + u8 EIC_IRQChannelPriority; + FunctionalState EIC_IRQChannelCmd; +}EIC_IRQInitTypeDef; + +typedef struct +{ + u8 EIC_FIQChannel; + FunctionalState EIC_FIQChannelCmd; +}EIC_FIQInitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* IRQ channels */ +#define WAKUP_IRQChannel 0 +#define TIM2_OC2_IRQChannel 1 +#define TIM2_OC1_IRQChannel 2 +#define TIM2_IC12_IRQChannel 3 +#define TIM2_UP_IRQChannel 4 +#define TIM1_OC2_IRQChannel 5 +#define TIM1_OC1_IRQChannel 6 +#define TIM1_IC12_IRQChannel 7 +#define TIM1_UP_IRQChannel 8 +#define TIM0_OC2_IRQChannel 9 +#define TIM0_OC1_IRQChannel 10 +#define TIM0_IC12_IRQChannel 11 +#define TIM0_UP_IRQChannel 12 +#define PWM_OC123_IRQChannel 13 +#define PWM_EM_IRQChannel 14 +#define PWM_UP_IRQChannel 15 +#define I2C_IRQChannel 16 +#define SSP1_IRQChannel 17 +#define SSP0_IRQChannel 18 +#define UART2_IRQChannel 19 +#define UART1_IRQChannel 20 +#define UART0_IRQChannel 21 +#define CAN_IRQChannel 22 +#define USB_LP_IRQChannel 23 +#define USB_HP_IRQChannel 24 +#define ADC_IRQChannel 25 +#define DMA_IRQChannel 26 +#define EXTIT_IRQChannel 27 +#define MRCC_IRQChannel 28 +#define FLASHSMI_IRQChannel 29 +#define RTC_IRQChannel 30 +#define TB_IRQChannel 31 + +/* FIQ channels */ +#define EXTIT_Line0_FIQChannel 0x00000001 +#define WATCHDOG_FIQChannel 0x00000002 + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void EIC_DeInit(void); +void EIC_IRQInit(EIC_IRQInitTypeDef* EIC_IRQInitStruct); +void EIC_FIQInit(EIC_FIQInitTypeDef* EIC_FIQInitStruct); +void EIC_IRQStructInit(EIC_IRQInitTypeDef* EIC_IRQInitStruct); +void EIC_FIQStructInit(EIC_FIQInitTypeDef* EIC_FIQInitStruct); +void EIC_IRQCmd(FunctionalState NewState); +void EIC_FIQCmd(FunctionalState NewState); +u8 EIC_GetCurrentIRQChannel(void); +u8 EIC_GetCurrentIRQChannelPriority(void); +void EIC_CurrentIRQPriorityConfig(u8 NewPriority); +u8 EIC_GetCurrentFIQChannel(void); +void EIC_ClearFIQPendingBit(u8 EIC_FIQChannel); + +#endif /* __75x_EIC_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_extit.h b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_extit.h new file mode 100644 index 000000000..5dbbc3a09 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_extit.h @@ -0,0 +1,77 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_extit.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* EXTIT software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_EXTIT_H +#define __75x_EXTIT_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* EXTIT Trigger enumeration */ +typedef enum +{ + EXTIT_ITTrigger_Falling = 1, + EXTIT_ITTrigger_Rising +}EXTITTrigger_TypeDef; + +/* EXTIT Init Structure definition */ +typedef struct +{ + u32 EXTIT_ITLine; + EXTITTrigger_TypeDef EXTIT_ITTrigger; + FunctionalState EXTIT_ITLineCmd; +}EXTIT_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* EXTIT Lines */ +#define EXTIT_ITLineNone 0x0000 /* No interrupt selected */ +#define EXTIT_ITLine0 0x0001 /* External interrupt line 0 */ +#define EXTIT_ITLine1 0x0002 /* External interrupt line 1 */ +#define EXTIT_ITLine2 0x0004 /* External interrupt line 2 */ +#define EXTIT_ITLine3 0x0008 /* External interrupt line 3 */ +#define EXTIT_ITLine4 0x0010 /* External interrupt line 4 */ +#define EXTIT_ITLine5 0x0020 /* External interrupt line 5 */ +#define EXTIT_ITLine6 0x0040 /* External interrupt line 6 */ +#define EXTIT_ITLine7 0x0080 /* External interrupt line 7 */ +#define EXTIT_ITLine8 0x0100 /* External interrupt line 8 */ +#define EXTIT_ITLine9 0x0200 /* External interrupt line 9 */ +#define EXTIT_ITLine10 0x0400 /* External interrupt line 10 */ +#define EXTIT_ITLine11 0x0800 /* External interrupt line 11 */ +#define EXTIT_ITLine12 0x1000 /* External interrupt line 12 */ +#define EXTIT_ITLine13 0x2000 /* External interrupt line 13 */ +#define EXTIT_ITLine14 0x4000 /* External interrupt line 14 */ +#define EXTIT_ITLine15 0x8000 /* External interrupt line 15 */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void EXTIT_DeInit(void); +void EXTIT_Init(EXTIT_InitTypeDef* EXTIT_InitStruct); +void EXTIT_StructInit(EXTIT_InitTypeDef* EXTIT_InitStruct); +void EXTIT_GenerateSWInterrupt(u16 EXTIT_ITLine); +FlagStatus EXTIT_GetFlagStatus(u16 EXTIT_ITLine); +void EXTIT_ClearFlag(u16 EXTIT_ITLine); +ITStatus EXTIT_GetITStatus(u16 EXTIT_ITLine); +void EXTIT_ClearITPendingBit(u16 EXTIT_ITLine); + +#endif /* __75x_EXTIT_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_gpio.h b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_gpio.h new file mode 100644 index 000000000..53aad69ca --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_gpio.h @@ -0,0 +1,120 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_gpio.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* GPIO software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_GPIO_H +#define __75x_GPIO_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* Configuration Mode enumeration */ +typedef enum +{ GPIO_Mode_AIN = 1, + GPIO_Mode_IN_FLOATING, + GPIO_Mode_IPD, + GPIO_Mode_IPU, + GPIO_Mode_Out_OD, + GPIO_Mode_Out_PP, + GPIO_Mode_AF_OD, + GPIO_Mode_AF_PP +}GPIOMode_TypeDef; + +/* GPIO Init structure definition */ +typedef struct +{ + u32 GPIO_Pin; + GPIOMode_TypeDef GPIO_Mode; +}GPIO_InitTypeDef; + +/* Bit_SET and Bit_RESET enumeration */ +typedef enum +{ Bit_RESET = 0, + Bit_SET +}BitAction; + + +/* Exported constants --------------------------------------------------------*/ +/* GPIO pins define */ +#define GPIO_Pin_None 0x00000000 /* No pin selected */ +#define GPIO_Pin_0 0x00000001 /* Pin 0 selected */ +#define GPIO_Pin_1 0x00000002 /* Pin 1 selected */ +#define GPIO_Pin_2 0x00000004 /* Pin 2 selected */ +#define GPIO_Pin_3 0x00000008 /* Pin 3 selected */ +#define GPIO_Pin_4 0x00000010 /* Pin 4 selected */ +#define GPIO_Pin_5 0x00000020 /* Pin 5 selected */ +#define GPIO_Pin_6 0x00000040 /* Pin 6 selected */ +#define GPIO_Pin_7 0x00000080 /* Pin 7 selected */ +#define GPIO_Pin_8 0x00000100 /* Pin 8 selected */ +#define GPIO_Pin_9 0x00000200 /* Pin 9 selected */ +#define GPIO_Pin_10 0x00000400 /* Pin 10 selected */ +#define GPIO_Pin_11 0x00000800 /* Pin 11 selected */ +#define GPIO_Pin_12 0x00001000 /* Pin 12 selected */ +#define GPIO_Pin_13 0x00002000 /* Pin 13 selected */ +#define GPIO_Pin_14 0x00004000 /* Pin 14 selected */ +#define GPIO_Pin_15 0x00008000 /* Pin 15 selected */ +#define GPIO_Pin_16 0x00010000 /* Pin 16 selected */ +#define GPIO_Pin_17 0x00020000 /* Pin 17 selected */ +#define GPIO_Pin_18 0x00040000 /* Pin 18 selected */ +#define GPIO_Pin_19 0x00080000 /* Pin 19 selected */ +#define GPIO_Pin_20 0x00100000 /* Pin 20 selected */ +#define GPIO_Pin_21 0x00200000 /* Pin 21 selected */ +#define GPIO_Pin_22 0x00400000 /* Pin 22 selected */ +#define GPIO_Pin_23 0x00800000 /* Pin 23 selected */ +#define GPIO_Pin_24 0x01000000 /* Pin 24 selected */ +#define GPIO_Pin_25 0x02000000 /* Pin 25 selected */ +#define GPIO_Pin_26 0x04000000 /* Pin 26 selected */ +#define GPIO_Pin_27 0x08000000 /* Pin 27 selected */ +#define GPIO_Pin_28 0x10000000 /* Pin 28 selected */ +#define GPIO_Pin_29 0x20000000 /* Pin 29 selected */ +#define GPIO_Pin_30 0x40000000 /* Pin 30 selected */ +#define GPIO_Pin_31 0x80000000 /* Pin 31 selected */ +#define GPIO_Pin_All 0xFFFFFFFF /* All pins selected */ + +/* GPIO Remap define */ +#define GPIO_Remap_SMI_CS3_EN 0x23 /* SMI CS3 Enable */ +#define GPIO_Remap_SMI_CS2_EN 0x22 /* SMI CS2 Enable */ +#define GPIO_Remap_SMI_CS1_EN 0x21 /* SMI CS1 Enable */ +#define GPIO_Remap_SMI_EN 0x20 /* SMI Enable */ +#define GPIO_Remap_DBGOFF 0x45 /* JTAG Disable */ +#define GPIO_Remap_UART1 0x44 /* UART1 Alternate Function mapping */ +#define GPIO_Remap_UART2 0x43 /* UART2 Alternate Function mapping */ +#define GPIO_Remap_SSP1 0x42 /* SSP1 Alternate Function mapping */ +#define GPIO_Remap_TIM2 0x41 /* TIM2 Alternate Function mapping */ +#define GPIO_Remap_TIM0 0x40 /* TIM0 Alternate Function mapping */ + + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void GPIO_DeInit(GPIO_TypeDef* GPIOx); +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); +u32 GPIO_Read(GPIO_TypeDef* GPIOx); +u8 GPIO_ReadBit(GPIO_TypeDef* GPIOx, u32 GPIO_Pin); +void GPIO_Write(GPIO_TypeDef* GPIOx, u32 PortVal); +void GPIO_WriteBit(GPIO_TypeDef* GPIOx,u32 GPIO_Pin, BitAction BitVal); +void GPIO_PinMaskConfig(GPIO_TypeDef* GPIOx, u32 GPIO_Pin, FunctionalState NewState); +u32 GPIO_GetPortMask(GPIO_TypeDef* GPIOx); +void GPIO_PinRemapConfig(u16 GPIO_Remap, FunctionalState NewState); + +#endif /* __75x_GPIO_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_i2c.h b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_i2c.h new file mode 100644 index 000000000..0e3a8c511 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_i2c.h @@ -0,0 +1,115 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_i2c.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* I2C software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion ------------------------------------ */ +#ifndef __75x_I2C_H +#define __75x_I2C_H + +/* Includes ----------------------------------------------------------------- */ +#include "75x_map.h" + +/* Exported types ----------------------------------------------------------- */ +/* I2C Init structure definition */ +typedef struct +{ + u32 I2C_CLKSpeed; + u16 I2C_OwnAddress; + u8 I2C_GeneralCall; + u8 I2C_Ack; +}I2C_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* General Call */ +#define I2C_GeneralCall_Enable 0x10 +#define I2C_GeneralCall_Disable 0xEF + +/* Acknowledgement */ +#define I2C_Ack_Enable 0x04 +#define I2C_Ack_Disable 0xFB + +/* I2C Flags */ +#define I2C_FLAG_SB 0x0001 +#define I2C_FLAG_M_SL 0x0002 +#define I2C_FLAG_ADSL 0x0004 +#define I2C_FLAG_BTF 0x0008 +#define I2C_FLAG_BUSY 0x0010 +#define I2C_FLAG_TRA 0x0020 +#define I2C_FLAG_ADD10 0x0040 +#define I2C_FLAG_EVF 0x0080 +#define I2C_FLAG_GCAL 0x0100 +#define I2C_FLAG_BERR 0x0200 +#define I2C_FLAG_ARLO 0x0400 +#define I2C_FLAG_STOPF 0x0800 +#define I2C_FLAG_AF 0x1000 +#define I2C_FLAG_ENDAD 0x2000 +#define I2C_FLAG_ACK 0x4000 + +/* I2C Events */ +#define I2C_EVENT_SLAVE_ADDRESS_MATCHED ( I2C_FLAG_EVF | I2C_FLAG_BUSY |I2C_FLAG_ADSL) +#define I2C_EVENT_SLAVE_BYTE_RECEIVED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_BTF ) +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_BTF | I2C_FLAG_TRA ) +#define I2C_EVENT_MASTER_MODE_SELECT ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL | I2C_FLAG_SB ) +#define I2C_EVENT_MASTER_MODE_SELECTED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL | I2C_FLAG_ENDAD ) +#define I2C_EVENT_MASTER_BYTE_RECEIVED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL | I2C_FLAG_BTF ) +#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL | I2C_FLAG_BTF | I2C_FLAG_TRA ) +#define I2C_EVENT_MASTER_MODE_ADDRESS10 ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL |I2C_FLAG_ADD10 ) +#define I2C_EVENT_SLAVE_STOP_DETECTED I2C_FLAG_STOPF +#define I2C_EVENT_SLAVE_ACK_FAILURE ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_BTF | I2C_FLAG_TRA | I2C_FLAG_AF) + +#define I2C_BUS_ERROR_DETECTED I2C_FLAG_BERR +#define I2C_ARBITRATION_LOST I2C_FLAG_ARLO +#define I2C_SLAVE_GENERAL_CALL (I2C_FLAG_BUSY | I2C_FLAG_GCAL) + +/* Master/Receiver Mode */ +#define I2C_MODE_TRANSMITTER 0x00 +#define I2C_MODE_RECEIVER 0x01 + +/* I2C Registers offset */ +#define I2C_CR 0x00 +#define I2C_SR1 0x04 +#define I2C_SR2 0x08 +#define I2C_CCR 0x0C +#define I2C_OAR1 0x10 +#define I2C_OAR2 0x14 +#define I2C_DR 0x18 +#define I2C_ECCR 0x1C + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void I2C_DeInit(void); +void I2C_Init(I2C_InitTypeDef* I2C_InitStruct); +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); +void I2C_Cmd(FunctionalState NewState); +void I2C_GenerateSTART(FunctionalState NewState); +void I2C_GenerateSTOP(FunctionalState NewState); +void I2C_AcknowledgeConfig(FunctionalState NewState); +void I2C_ITConfig(FunctionalState NewState); +u16 I2C_GetLastEvent(void); +ErrorStatus I2C_CheckEvent(u16 I2C_EVENT); +void I2C_SendData(u8 Data); +u8 I2C_ReceiveData(void); +void I2C_Send7bitAddress(u8 Address, u8 Direction); +u8 I2C_ReadRegister(u8 I2C_Register); +FlagStatus I2C_GetFlagStatus(u16 I2C_FLAG); +void I2C_ClearFlag(u16 I2C_FLAG, ...); + +#endif /* __75x_I2C_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_lib.h b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_lib.h new file mode 100644 index 000000000..8048ffcc3 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_lib.h @@ -0,0 +1,103 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_lib.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file includes the peripherals header files in the +* user application. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_LIB_H +#define __75x_LIB_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +#ifdef _SMI + #include "75x_smi.h" +#endif /*_SMI */ + +#ifdef _CFG + #include "75x_cfg.h" +#endif /*_CFG*/ + +#ifdef _MRCC + #include "75x_mrcc.h" +#endif /*_MRCC */ + +#ifdef _ADC + #include "75x_adc.h" +#endif /*_ADC */ + +#ifdef _TB + #include "75x_tb.h" +#endif /*_TB */ + +#ifdef _TIM + #include "75x_tim.h" +#endif /*_TIM */ + +#ifdef _PWM + #include "75x_pwm.h" +#endif /*_PWM */ + +#ifdef _WDG + #include "75x_wdg.h" +#endif /*_WDG */ + +#ifdef _SSP + #include "75x_ssp.h" +#endif /*_SSP */ + +#ifdef _CAN + #include "75x_can.h" +#endif /*_CAN */ + +#ifdef _I2C + #include "75x_i2c.h" +#endif /*_I2C */ + +#ifdef _UART + #include "75x_uart.h" +#endif /*_UART */ + +#ifdef _GPIO + #include "75x_gpio.h" +#endif /*_GPIO */ + +#ifdef _DMA + #include "75x_dma.h" +#endif /*_DMA */ + +#ifdef _RTC + #include "75x_rtc.h" +#endif /*_RTC */ + +#ifdef _EXTIT + #include "75x_extit.h" +#endif /*_EXTIT */ + +#ifdef _EIC + #include "75x_eic.h" +#endif /*_EIC */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void debug(void); + +#endif /* __75x_LIB_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_map.h b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_map.h new file mode 100644 index 000000000..d000f1b45 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_map.h @@ -0,0 +1,697 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_map.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the peripheral register's definitions +* and memory mapping. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_MAP_H +#define __75x_MAP_H + +#ifndef EXT + #define EXT extern +#endif /* EXT */ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_conf.h" +#include "75x_type.h" + +/* Exported types ------------------------------------------------------------*/ +/******************************************************************************/ +/* IP registers structures */ +/******************************************************************************/ + +/*------------------------ Analog to Digital Converter -----------------------*/ +typedef struct +{ + vu16 CLR0; + u16 EMPTY1; + vu16 CLR1; + u16 EMPTY2; + vu16 CLR2; + u16 EMPTY3; + vu16 CLR3; + u16 EMPTY4; + vu16 CLR4; + u16 EMPTY5; + vu16 TRA0; + u16 EMPTY6; + vu16 TRA1; + u16 EMPTY7; + vu16 TRA2; + u16 EMPTY8; + vu16 TRA3; + u16 EMPTY9; + vu16 TRB0; + u16 EMPTY10; + vu16 TRB1; + u16 EMPTY11; + vu16 TRB2; + u16 EMPTY12; + vu16 TRB3; + u16 EMPTY13; + vu16 DMAR; + u16 EMPTY14[7]; + vu16 DMAE; + u16 EMPTY15 ; + vu16 PBR; + u16 EMPTY16; + vu16 IMR; + u16 EMPTY17; + vu16 D0; + u16 EMPTY18; + vu16 D1; + u16 EMPTY19; + vu16 D2; + u16 EMPTY20; + vu16 D3; + u16 EMPTY21; + vu16 D4; + u16 EMPTY22; + vu16 D5; + u16 EMPTY23; + vu16 D6; + u16 EMPTY24; + vu16 D7; + u16 EMPTY25; + vu16 D8; + u16 EMPTY26; + vu16 D9; + u16 EMPTY27; + vu16 D10; + u16 EMPTY28; + vu16 D11; + u16 EMPTY29; + vu16 D12; + u16 EMPTY30; + vu16 D13; + u16 EMPTY31; + vu16 D14; + u16 EMPTY32; + vu16 D15; + u16 EMPTY33; +} ADC_TypeDef; + +/*------------------------ Controller Area Network ---------------------------*/ +typedef struct +{ + vu16 CRR; + u16 EMPTY1; + vu16 CMR; + u16 EMPTY2; + vu16 M1R; + u16 EMPTY3; + vu16 M2R; + u16 EMPTY4; + vu16 A1R; + u16 EMPTY5; + vu16 A2R; + u16 EMPTY6; + vu16 MCR; + u16 EMPTY7; + vu16 DA1R; + u16 EMPTY8; + vu16 DA2R; + u16 EMPTY9; + vu16 DB1R; + u16 EMPTY10; + vu16 DB2R; + u16 EMPTY11[27]; +} CAN_MsgObj_TypeDef; + +typedef struct +{ + vu16 CR; + u16 EMPTY1; + vu16 SR; + u16 EMPTY2; + vu16 ERR; + u16 EMPTY3; + vu16 BTR; + u16 EMPTY4; + vu16 IDR; + u16 EMPTY5; + vu16 TESTR; + u16 EMPTY6; + vu16 BRPR; + u16 EMPTY7[3]; + CAN_MsgObj_TypeDef sMsgObj[2]; + u16 EMPTY8[16]; + vu16 TXR1R; + u16 EMPTY9; + vu16 TXR2R; + u16 EMPTY10[13]; + vu16 ND1R; + u16 EMPTY11; + vu16 ND2R; + u16 EMPTY12[13]; + vu16 IP1R; + u16 EMPTY13; + vu16 IP2R; + u16 EMPTY14[13]; + vu16 MV1R; + u16 EMPTY15; + vu16 MV2R; + u16 EMPTY16; +} CAN_TypeDef; + +/*--------------------------- Configuration Register -------------------------*/ +typedef struct +{ + vu32 GLCONF; +} CFG_TypeDef; + +/*-------------------------------- DMA Controller ----------------------------*/ +typedef struct +{ + vu16 SOURCEL; + u16 EMPTY1; + vu16 SOURCEH; + u16 EMPTY2; + vu16 DESTL; + u16 EMPTY3; + vu16 DESTH; + u16 EMPTY4; + vu16 MAX; + u16 EMPTY5; + vu16 CTRL; + u16 EMPTY6; + vuc16 SOCURRH; + u16 EMPTY7; + vuc16 SOCURRL; + u16 EMPTY8; + vuc16 DECURRH; + u16 EMPTY9; + vuc16 DECURRL; + u16 EMPTY10; + vuc16 TCNT; + u16 EMPTY11; + vu16 LUBUFF; + u16 EMPTY12; +} DMA_Stream_TypeDef; + +typedef struct +{ + vu16 MASK; + u16 EMPTY4; + vu16 CLR; + u16 EMPTY5; + vuc16 STATUS; + u16 EMPTY6; + vu16 LAST; + u16 EMPTY7; +} DMA_TypeDef; + +/*----------------------- Enhanced Interrupt Controller ----------------------*/ +typedef struct +{ + vu32 ICR; + vuc32 CICR; + vu32 CIPR; + u32 EMPTY1; + vu32 FIER; + vu32 FIPR; + vu32 IVR; + vu32 FIR; + vu32 IER; + u32 EMPTY2[7]; + vu32 IPR; + u32 EMPTY3[7]; + vu32 SIRn[32]; +} EIC_TypeDef; + +/*------------------------- External Interrupt Controller --------------------*/ +typedef struct +{ + vu32 MR; + vu32 TSR; + vu32 SWIR; + vu32 PR; +} EXTIT_TypeDef; + +/*-------------------------- General Purpose IO ports ------------------------*/ +typedef struct +{ + vu32 PC0; + vu32 PC1; + vu32 PC2; + vu32 PD; + vu32 PM; +} GPIO_TypeDef; + +typedef struct +{ + vu32 REMAP0R; + vu32 REMAP1R; +} GPIOREMAP_TypeDef; + +/*--------------------------------- I2C interface ----------------------------*/ +typedef struct +{ + vu8 CR; + u8 EMPTY1[3]; + vu8 SR1; + u8 EMPTY2[3]; + vu8 SR2; + u8 EMPTY3[3]; + vu8 CCR; + u8 EMPTY4[3]; + vu8 OAR1; + u8 EMPTY5[3]; + vu8 OAR2; + u8 EMPTY6[3]; + vu8 DR; + u8 EMPTY7[3]; + vu8 ECCR; + u8 EMPTY8[3]; +} I2C_TypeDef; + +/*---------------------------- Power, Reset and Clocks -----------------------*/ +typedef struct +{ + vu32 CLKCTL; + vu32 RFSR; + vu32 PWRCTRL; + u32 EMPTY1; + vu32 PCLKEN; + vu32 PSWRES; + u32 EMPTY2[2]; + vu32 BKP0; + vu32 BKP1; +} MRCC_TypeDef; + +/*-------------------------------- Real Time Clock ---------------------------*/ +typedef struct +{ + vu16 CRH; + u16 EMPTY; + vu16 CRL; + u16 EMPTY1; + vu16 PRLH; + u16 EMPTY2; + vu16 PRLL; + u16 EMPTY3; + vu16 DIVH; + u16 EMPTY4; + vu16 DIVL; + u16 EMPTY5; + vu16 CNTH; + u16 EMPTY6; + vu16 CNTL; + u16 EMPTY7; + vu16 ALRH; + u16 EMPTY8; + vu16 ALRL; + u16 EMPTY9; +} RTC_TypeDef; + +/*---------------------------- Serial Memory Interface -----------------------*/ +typedef struct +{ + vu32 CR1; + vu32 CR2; + vu32 SR; + vu32 TR; + vuc32 RR; +} SMI_TypeDef; + +/*--------------------------------- Timer Base -------------------------------*/ +typedef struct +{ + vu16 CR; + u16 EMPTY1; + vu16 SCR; + u16 EMPTY2; + vu16 IMCR; + u16 EMPTY3[7]; + vu16 RSR; + u16 EMPTY4; + vu16 RER; + u16 EMPTY5; + vu16 ISR; + u16 EMPTY6; + vu16 CNT; + u16 EMPTY7; + vu16 PSC; + u16 EMPTY8[3]; + vu16 ARR; + u16 EMPTY9[13]; + vu16 ICR1; + u16 EMPTY10; +} TB_TypeDef; + +/*------------------------------------ TIM -----------------------------------*/ +typedef struct +{ + vu16 CR; + u16 EMPTY1; + vu16 SCR; + u16 EMPTY2; + vu16 IMCR; + u16 EMPTY3; + vu16 OMR1; + u16 EMPTY4[5]; + vu16 RSR; + u16 EMPTY5; + vu16 RER; + u16 EMPTY6; + vu16 ISR; + u16 EMPTY7; + vu16 CNT; + u16 EMPTY8; + vu16 PSC; + u16 EMPTY9[3]; + vu16 ARR; + u16 EMPTY10; + vu16 OCR1; + u16 EMPTY11; + vu16 OCR2; + u16 EMPTY12[9]; + vu16 ICR1; + u16 EMPTY13; + vu16 ICR2; + u16 EMPTY14[9]; + vu16 DMAB; + u16 EMPTY15; +} TIM_TypeDef; + +/*------------------------------------ PWM -----------------------------------*/ +typedef struct +{ + vu16 CR; + u16 EMPTY1; + vu16 SCR; + u16 EMPTY2[3]; + vu16 OMR1; + u16 EMPTY3; + vu16 OMR2; + u16 EMPTY4[3]; + vu16 RSR; + u16 EMPTY5; + vu16 RER; + u16 EMPTY6; + vu16 ISR; + u16 EMPTY7; + vu16 CNT; + u16 EMPTY8; + vu16 PSC; + u16 EMPTY9; + vu16 RCR; + u16 EMPTY10; + vu16 ARR; + u16 EMPTY11; + vu16 OCR1; + u16 EMPTY12; + vu16 OCR2; + u16 EMPTY13; + vu16 OCR3; + u16 EMPTY14[15]; + vu16 DTR; + u16 EMPTY15; + vu16 DMAB; + u16 EMPTY16; +} PWM_TypeDef; + +/*----------------------- Synchronous Serial Peripheral ----------------------*/ +typedef struct +{ + vu32 CR0; + vu32 CR1; + vu32 DR; + vu32 SR; + vu32 PR; + vu32 IMSCR; + vu32 RISR; + vu32 MISR; + vu32 ICR; + vu32 DMACR; +} SSP_TypeDef; + +/*---------------- Universal Asynchronous Receiver Transmitter ---------------*/ +typedef struct +{ + vu16 DR; + u16 EMPTY; + vu16 RSR; + u16 EMPTY1[9]; + vu16 FR; + u16 EMPTY2; + vu16 BKR; + u16 EMPTY3[3]; + vu16 IBRD; + u16 EMPTY4; + vu16 FBRD; + u16 EMPTY5; + vu16 LCR; + u16 EMPTY6; + vu16 CR; + u16 EMPTY7; + vu16 IFLS; + u16 EMPTY8; + vu16 IMSC; + u16 EMPTY9; + vu16 RIS; + u16 EMPTY10; + vu16 MIS; + u16 EMPTY11; + vu16 ICR; + u16 EMPTY12; + vu16 DMACR; + u16 EMPTY13; +} UART_TypeDef; + +/*---------------------------------- WATCHDOG --------------------------------*/ +typedef struct +{ + vu16 CR; + u16 EMPTY1; + vu16 PR; + u16 EMPTY2; + vu16 VR; + u16 EMPTY3; + vu16 CNT; + u16 EMPTY4; + vu16 SR; + u16 EMPTY5; + vu16 MR; + u16 EMPTY6; + vu16 KR; + u16 EMPTY7; +} WDG_TypeDef; + +/******************************************************************************* +* Peripherals' Base addresses +*******************************************************************************/ + +#define SRAM_BASE 0x40000000 + +#define CONFIG_BASE 0x60000000 + +#define SMIR_BASE 0x90000000 + +#define PERIPH_BASE 0xFFFF0000 + +#define CFG_BASE (CONFIG_BASE + 0x0010) +#define MRCC_BASE (CONFIG_BASE + 0x0020) +#define ADC_BASE (PERIPH_BASE + 0x8400) +#define TB_BASE (PERIPH_BASE + 0x8800) +#define TIM0_BASE (PERIPH_BASE + 0x8C00) +#define TIM1_BASE (PERIPH_BASE + 0x9000) +#define TIM2_BASE (PERIPH_BASE + 0x9400) +#define PWM_BASE (PERIPH_BASE + 0x9800) +#define WDG_BASE (PERIPH_BASE + 0xB000) +#define SSP0_BASE (PERIPH_BASE + 0xB800) +#define SSP1_BASE (PERIPH_BASE + 0xBC00) +#define CAN_BASE (PERIPH_BASE + 0xC400) +#define I2C_BASE (PERIPH_BASE + 0xCC00) +#define UART0_BASE (PERIPH_BASE + 0xD400) +#define UART1_BASE (PERIPH_BASE + 0xD800) +#define UART2_BASE (PERIPH_BASE + 0xDC00) +#define GPIO0_BASE (PERIPH_BASE + 0xE400) +#define GPIOREMAP_BASE (PERIPH_BASE + 0xE420) +#define GPIO1_BASE (PERIPH_BASE + 0xE440) +#define GPIO2_BASE (PERIPH_BASE + 0xE480) +#define DMA_BASE (PERIPH_BASE + 0xECF0) +#define DMA_Stream0_BASE (PERIPH_BASE + 0xEC00) +#define DMA_Stream1_BASE (PERIPH_BASE + 0xEC40) +#define DMA_Stream2_BASE (PERIPH_BASE + 0xEC80) +#define DMA_Stream3_BASE (PERIPH_BASE + 0xECC0) +#define RTC_BASE (PERIPH_BASE + 0xF000) +#define EXTIT_BASE (PERIPH_BASE + 0xF400) +#define EIC_BASE (PERIPH_BASE + 0xF800) + +/******************************************************************************* + IPs' declaration +*******************************************************************************/ + +/*------------------- Non Debug Mode -----------------------------------------*/ + +#ifndef DEBUG + #define SMI ((SMI_TypeDef *) SMIR_BASE) + #define CFG ((CFG_TypeDef *) CFG_BASE) + #define MRCC ((MRCC_TypeDef *) MRCC_BASE) + #define ADC ((ADC_TypeDef *) ADC_BASE) + #define TB ((TB_TypeDef *) TB_BASE) + #define TIM0 ((TIM_TypeDef *) TIM0_BASE) + #define TIM1 ((TIM_TypeDef *) TIM1_BASE) + #define TIM2 ((TIM_TypeDef *) TIM2_BASE) + #define PWM ((PWM_TypeDef *) PWM_BASE) + #define WDG ((WDG_TypeDef *) WDG_BASE) + #define SSP0 ((SSP_TypeDef *) SSP0_BASE) + #define SSP1 ((SSP_TypeDef *) SSP1_BASE) + #define CAN ((CAN_TypeDef *) CAN_BASE) + #define I2C ((I2C_TypeDef *) I2C_BASE) + #define UART0 ((UART_TypeDef *) UART0_BASE) + #define UART1 ((UART_TypeDef *) UART1_BASE) + #define UART2 ((UART_TypeDef *) UART2_BASE) + #define GPIO0 ((GPIO_TypeDef *) GPIO0_BASE) + #define GPIOREMAP ((GPIOREMAP_TypeDef *) GPIOREMAP_BASE) + #define GPIO1 ((GPIO_TypeDef *) GPIO1_BASE) + #define GPIO2 ((GPIO_TypeDef *) GPIO2_BASE) + #define DMA ((DMA_TypeDef *) DMA_BASE) + #define DMA_Stream0 ((DMA_Stream_TypeDef *) DMA_Stream0_BASE) + #define DMA_Stream1 ((DMA_Stream_TypeDef *) DMA_Stream1_BASE) + #define DMA_Stream2 ((DMA_Stream_TypeDef *) DMA_Stream2_BASE) + #define DMA_Stream3 ((DMA_Stream_TypeDef *) DMA_Stream3_BASE) + #define RTC ((RTC_TypeDef *) RTC_BASE) + #define EXTIT ((EXTIT_TypeDef *) EXTIT_BASE) + #define EIC ((EIC_TypeDef *) EIC_BASE) +#else /* DEBUG */ + #ifdef _SMI + EXT SMI_TypeDef *SMI; + #endif /*_SMI */ + + #ifdef _CFG + EXT CFG_TypeDef *CFG; + #endif /*_CFG */ + + #ifdef _MRCC + EXT MRCC_TypeDef *MRCC; + #endif /*_MRCC */ + + #ifdef _ADC + EXT ADC_TypeDef *ADC; + #endif /*_ADC */ + + #ifdef _TB + EXT TB_TypeDef *TB; + #endif /*_TB */ + + #ifdef _TIM0 + EXT TIM_TypeDef *TIM0; + #endif /*_TIM0 */ + + #ifdef _TIM1 + EXT TIM_TypeDef *TIM1; + #endif /*_TIM1 */ + + #ifdef _TIM2 + EXT TIM_TypeDef *TIM2; + #endif /*_TIM2 */ + + #ifdef _PWM + EXT PWM_TypeDef *PWM; + #endif /*_PWM */ + + #ifdef _WDG + EXT WDG_TypeDef *WDG; + #endif /*_WDG */ + + #ifdef _SSP0 + EXT SSP_TypeDef *SSP0; + #endif /*_SSP0 */ + + #ifdef _SSP1 + EXT SSP_TypeDef *SSP1; + #endif /*_SSP1 */ + + #ifdef _CAN + EXT CAN_TypeDef *CAN; + #endif /*_CAN */ + + #ifdef _I2C + EXT I2C_TypeDef *I2C; + #endif /*_I2C */ + + #ifdef _UART0 + EXT UART_TypeDef *UART0; + #endif /*_UART0 */ + + #ifdef _UART1 + EXT UART_TypeDef *UART1; + #endif /*_UART1 */ + + #ifdef _UART2 + EXT UART_TypeDef *UART2; + #endif /*_UART2 */ + + #ifdef _GPIO0 + EXT GPIO_TypeDef *GPIO0; + #endif /*_GPIO0 */ + + #ifdef _GPIOREMAP + EXT GPIOREMAP_TypeDef *GPIOREMAP; + #endif /*_GPIOREMAP */ + + #ifdef _GPIO1 + EXT GPIO_TypeDef *GPIO1; + #endif /*_GPIO1 */ + + #ifdef _GPIO2 + EXT GPIO_TypeDef *GPIO2; + #endif /*_GPIO2 */ + + #ifdef _DMA + EXT DMA_TypeDef *DMA; + #endif /*_DMA */ + + #ifdef _DMA_Stream0 + EXT DMA_Stream_TypeDef *DMA_Stream0; + #endif /*_DMA_Stream0 */ + + #ifdef _DMA_Stream1 + EXT DMA_Stream_TypeDef *DMA_Stream1; + #endif /*_DMA_Stream1 */ + + #ifdef _DMA_Stream2 + EXT DMA_Stream_TypeDef *DMA_Stream2; + #endif /*_DMA_Stream2 */ + + #ifdef _DMA_Stream3 + EXT DMA_Stream_TypeDef *DMA_Stream3; + #endif /*_DMA_Stream3 */ + + #ifdef _RTC + EXT RTC_TypeDef *RTC; + #endif /*_RTC */ + + #ifdef _EXTIT + EXT EXTIT_TypeDef *EXTIT; + #endif /*_EXTIT */ + + #ifdef _EIC + EXT EIC_TypeDef *EIC; + #endif /*_EIC */ + +#endif /* DEBUG */ + +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +#endif /* __75x_MAP_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_mrcc.h b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_mrcc.h new file mode 100644 index 000000000..91c178429 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_mrcc.h @@ -0,0 +1,241 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_mrcc.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* MRCC software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_MRCC_H +#define __75x_MRCC_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* MRCC Buck-up registers */ +typedef enum +{ + MRCC_BKP0, + MRCC_BKP1 +}MRCC_BKPReg; + +typedef enum +{ + FREEOSC, + OSC4MPLL, + OSC4M, + CKRTC, + Disabled, + OSC4M_Div128, + LPOSC, + OSC32K, + Internal, + External, + ON, + OFF +}CLKSourceTypeDef; + + +typedef struct +{ + CLKSourceTypeDef CKSYS_Source; /* FREEOSC, OSC4MPLL, OSC4M, CKRTC */ + CLKSourceTypeDef CKRTC_Source; /* Disabled, OSC4M_Div128, OSC32K, LPOSC */ + CLKSourceTypeDef CKUSB_Source; /* Disabled, Internal, External */ + CLKSourceTypeDef PLL_Status; /* ON, OFF */ + CLKSourceTypeDef OSC4M_Status; /* ON, OFF */ + CLKSourceTypeDef LPOSC_Status; /* ON, OFF */ + CLKSourceTypeDef OSC32K_Status; /* ON, OFF */ + u32 CKSYS_Frequency; + u32 HCLK_Frequency; + u32 CKTIM_Frequency; + u32 PCLK_Frequency; +}MRCC_ClocksTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* Oscillator divider by 2 */ +#define MRCC_XTDIV2_Disable 0xFFFF7FFF +#define MRCC_XTDIV2_Enable 0x00008000 + +/* System clock source */ +#define MRCC_CKSYS_FREEOSC 0x01 +#define MRCC_CKSYS_OSC4M 0x02 +#define MRCC_CKSYS_OSC4MPLL 0x03 +#define MRCC_CKSYS_RTC 0x04 + +/* PLL multiplication factors */ +#define MRCC_PLL_Disabled 0xFEFFFFFF +#define MRCC_PLL_NoChange 0x00000001 +#define MRCC_PLL_Mul_12 0x18000000 +#define MRCC_PLL_Mul_14 0x10000000 +#define MRCC_PLL_Mul_15 0x08000000 +#define MRCC_PLL_Mul_16 0x00000000 + +/* AHB clock source */ +#define MRCC_CKSYS_Div1 0x00000000 +#define MRCC_CKSYS_Div2 0x00000008 +#define MRCC_CKSYS_Div4 0x00000010 +#define MRCC_CKSYS_Div8 0x00000018 + +/* TIM clock source */ +#define MRCC_HCLK_Div1 0x00000000 +#define MRCC_HCLK_Div2 0x00000001 +#define MRCC_HCLK_Div4 0x00000002 +#define MRCC_HCLK_Div8 0x00000003 + +/* APB clock source */ +#define MRCC_CKTIM_Div1 0xFFFFFFFB +#define MRCC_CKTIM_Div2 0x00000004 + +/* RTC clock sources */ +#define MRCC_CKRTC_OSC4M_Div128 0x01000000 +#define MRCC_CKRTC_OSC32K 0x02000000 +#define MRCC_CKRTC_LPOSC 0x03000000 + +/* USB clock sources */ +#define MRCC_CKUSB_Internal 0xFFBFFFFF +#define MRCC_CKUSB_External 0x00400000 + +/* MRCC Interrupts */ +#define MRCC_IT_LOCK 0x40000000 +#define MRCC_IT_NCKD 0x00080000 + +/* Peripheral Clock */ +#define MRCC_Peripheral_ALL 0x1975623F +#define MRCC_Peripheral_EXTIT 0x10000000 +#define MRCC_Peripheral_RTC 0x08000000 +#define MRCC_Peripheral_GPIO 0x01000000 +#define MRCC_Peripheral_UART2 0x00400000 +#define MRCC_Peripheral_UART1 0x00200000 +#define MRCC_Peripheral_UART0 0x00100000 +#define MRCC_Peripheral_I2C 0x00040000 +#define MRCC_Peripheral_CAN 0x00010000 +#define MRCC_Peripheral_SSP1 0x00004000 +#define MRCC_Peripheral_SSP0 0x00002000 +#define MRCC_Peripheral_USB 0x00000200 +#define MRCC_Peripheral_PWM 0x00000020 +#define MRCC_Peripheral_TIM2 0x00000010 +#define MRCC_Peripheral_TIM1 0x00000008 +#define MRCC_Peripheral_TIM0 0x00000004 +#define MRCC_Peripheral_TB 0x00000002 +#define MRCC_Peripheral_ADC 0x00000001 + +/* Clock sources to measure theire frequency */ +#define MRCC_ClockSource_CKSYS 0x01 +#define MRCC_ClockSource_HCLK 0x02 +#define MRCC_ClockSource_PCLK 0x03 +#define MRCC_ClockSource_CKTIM 0x04 + +/* Low Power Debug Mode */ +#define MRCC_LPDM_Disable 0xFFFFFFF7 +#define MRCC_LPDM_Enable 0x00000008 + +/* WFI Mode parameters */ +#define MRCC_WFIParam_FLASHPowerDown 0x00000000 +#define MRCC_WFIParam_FLASHOn 0x00000010 +#define MRCC_WFIParam_FLASHOff 0x00004000 + +/* STOP Mode parameters */ +#define MRCC_STOPParam_Default 0x00000000 +#define MRCC_STOPParam_OSC4MOff 0x00008000 +#define MRCC_STOPParam_FLASHOff 0x00004000 +#define MRCC_STOPParam_MVREGOff 0x00002000 + +/* I/O Pins voltage range */ +#define MRCC_IOVoltageRange_5V 0xFFFEFFFF +#define MRCC_IOVoltageRange_3V3 0x00010000 + +/* Clock sources to output on MCO pin */ +#define MRCC_MCO_HCLK 0x00000000 +#define MRCC_MCO_PCLK 0x00000040 +#define MRCC_MCO_OSC4M 0x00000080 +#define MRCC_MCO_CKPLL2 0x000000C0 +#define MRCC_MCOPrescaler_1 0xFFFFFFDF +#define MRCC_MCOPrescaler_2 0x00000020 + +/* 4MHz main oscillator configuration */ +#define MRCC_OSC4M_Default 0xFFFCFFFF +#define MRCC_OSC4M_Disable 0x00020000 +#define MRCC_OSC4M_Bypass 0x00010000 + +/* OSC32K oscillator configuration */ +#define MRCC_OSC32K_Disable 0xDFFFFFFF +#define MRCC_OSC32K_Enable 0x20000000 +#define MRCC_OSC32KBypass_Disable 0xBFFFFFFF +#define MRCC_OSC32KBypass_Enable 0x40000000 + +/* LPOSC oscillator configuration */ +#define MRCC_LPOSC_Disable 0xEFFFFFFF +#define MRCC_LPOSC_Enable 0x10000000 + +/* RTC measurement configuration */ +#define MRCC_RTCM_Disable 0xFBFFFFFF +#define MRCC_RTCM_Enable 0x04000000 + +/* MRCC Flags */ +#define MRCC_FLAG_LOCK 0x3F +#define MRCC_FLAG_LOCKIF 0x3D +#define MRCC_FLAG_CKSEL 0x37 +#define MRCC_FLAG_CKOSCSEL 0x35 +#define MRCC_FLAG_NCKD 0x32 +#define MRCC_FLAG_SWR 0x5D +#define MRCC_FLAG_WDGR 0x5C +#define MRCC_FLAG_EXTR 0x5B +#define MRCC_FLAG_WKP 0x5A +#define MRCC_FLAG_STDB 0x59 +#define MRCC_FLAG_BCOUNT 0x58 +#define MRCC_FLAG_OSC32KRDY 0x7F +#define MRCC_FLAG_CKRTCOK 0x7B +#define MRCC_FLAG_LPDONE 0x67 +#define MRCC_FLAG_LP 0x60 + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void MRCC_DeInit(void); +void MRCC_XTDIV2Config(u32 MRCC_XTDIV2); +ErrorStatus MRCC_CKSYSConfig(u32 MRCC_CKSYS, u32 MRCC_PLL); +void MRCC_HCLKConfig(u32 MRCC_HCLK); +void MRCC_CKTIMConfig(u32 MRCC_CKTIM); +void MRCC_PCLKConfig(u32 MRCC_PCLK); +ErrorStatus MRCC_CKRTCConfig(u32 MRCC_CKRTC); +ErrorStatus MRCC_CKUSBConfig(u32 MRCC_CKUSB); +void MRCC_ITConfig(u32 MRCC_IT, FunctionalState NewState); +void MRCC_PeripheralClockConfig(u32 MRCC_Peripheral, FunctionalState NewState); +void MRCC_PeripheralSWResetConfig(u32 MRCC_Peripheral, FunctionalState NewState); +void MRCC_GetClocksStatus(MRCC_ClocksTypeDef* MRCC_ClocksStatus); +void MRCC_LPMC_DBGConfig(u32 MRCC_LPDM); +void MRCC_EnterWFIMode(u32 MRCC_WFIParam); +void MRCC_EnterSTOPMode(u32 MRCC_STOPParam); +void MRCC_EnterSTANDBYMode(void); +void MRCC_GenerateSWReset(void); +void MRCC_WriteBackupRegister(MRCC_BKPReg MRCC_BKP, u32 Data); +u32 MRCC_ReadBackupRegister(MRCC_BKPReg MRCC_BKP); +void MRCC_IOVoltageRangeConfig(u32 MRCC_IOVoltageRange); +void MRCC_MCOConfig(u32 MRCC_MCO, u32 MCO_MCOPrescaler); +ErrorStatus MRCC_OSC4MConfig(u32 MRCC_OSC4M); +ErrorStatus MRCC_OSC32KConfig(u32 MRCC_OSC32K, u32 MRCC_OSC32KBypass); +ErrorStatus MRCC_LPOSCConfig(u32 MRCC_LPOSC); +void MRCC_RTCMConfig(u32 MRCC_RTCM); +void MRCC_SetBuilderCounter(u8 BuilderCounter); +u16 MRCC_GetCKSYSCounter(void); +FlagStatus MRCC_GetFlagStatus(u8 MRCC_FLAG); +void MRCC_ClearFlag(u8 MRCC_FLAG); +ITStatus MRCC_GetITStatus(u32 MRCC_IT); +void MRCC_ClearITPendingBit(u32 MRCC_IT); +ErrorStatus MRCC_WaitForOSC4MStartUp(void); + +#endif /* __75x_MRCC_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_pwm.h b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_pwm.h new file mode 100644 index 000000000..28edba9e8 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_pwm.h @@ -0,0 +1,215 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_pwm.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* PWM software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_PWM_H +#define __75x_PWM_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +/* Exported types ------------------------------------------------------------*/ + +typedef struct +{ + u16 PWM_Mode; /* PWM Mode */ + u16 PWM_Prescaler; /* Prescaler value */ + u16 PWM_CounterMode; /* Counter mode: Up/Down, Edge aligned or center aligned */ + u16 PWM_Period; /* Period value */ + u16 PWM_Complementary; /* Complementary PWM selection */ + u16 PWM_OCState; /* Output compare off-state in Run mode */ + u16 PWM_OCNState; /* Complementary Output compare off-state in Run mode */ + u16 PWM_Channel; /* PWM Channel: 1, 2 or 3 */ + u16 PWM_Pulse1; /* PWM or OCM Channel 1 pulse length */ + u16 PWM_Pulse2; /* PWM or OCM Channel 2 pulse length */ + u16 PWM_Pulse3; /* PWM or OCM Channel 3 pulse length */ + u16 PWM_Polarity1; /* PWM, OCM or OPM Channel 1 polarity */ + u16 PWM_Polarity2; /* PWM or OCM Channel 2 polarity */ + u16 PWM_Polarity3; /* PWM or OCM Channel 3 polarity */ + u16 PWM_Polarity1N; /* PWM or OCM Channel 1N polarity */ + u16 PWM_Polarity2N; /* PWM or OCM Channel 2N polarity */ + u16 PWM_Polarity3N; /* PWM or OCM Channel 3N polarity */ + u16 PWM_DTRAccess; /* Enable or disable the configuration of DTR register parameters: + DeadTime, Emergency, LOCKLevel, OSSIState, OCState and OCNState */ + u16 PWM_DeadTime; /* Dead Time value */ + u16 PWM_Emergency; /* Emergency selection: Enable / Disable */ + u16 PWM_LOCKLevel; /* LOCK level */ + u16 PWM_OSSIState; /* Off-State Selection for Idle state */ + u8 PWM_RepetitionCounter; /* Repetition counter value */ +} PWM_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* PWM modes */ +#define PWM_Mode_OCTiming 0x0001 +#define PWM_Mode_OCActive 0x0002 +#define PWM_Mode_OCInactive 0x0003 +#define PWM_Mode_OCToggle 0x0004 +#define PWM_Mode_PWM 0x0005 + +/* PWM Counter Mode */ +#define PWM_CounterMode_Up 0x0000 +#define PWM_CounterMode_Down 0x0010 +#define PWM_CounterMode_CenterAligned1 0x0020 +#define PWM_CounterMode_CenterAligned2 0x0040 +#define PWM_CounterMode_CenterAligned3 0x0060 + +/* PWM Channel */ +#define PWM_Channel_1 0x0001 +#define PWM_Channel_2 0x0002 +#define PWM_Channel_3 0x0004 +#define PWM_Channel_ALL 0x0007 + +/* PWM Polarity channel 1 */ +#define PWM_Polarity1_High 0x0001 +#define PWM_Polarity1_Low 0x0002 + +/* PWM Polarity channel 2 */ +#define PWM_Polarity2_High 0x0001 +#define PWM_Polarity2_Low 0x0002 + +/* PWM Polarity channel 3 */ +#define PWM_Polarity3_High 0x0001 +#define PWM_Polarity3_Low 0x0002 + +/* PWM Polarity channel 1N */ +#define PWM_Polarity1N_High 0x0001 +#define PWM_Polarity1N_Low 0x0002 + +/* PWM Polarity channel 2N */ +#define PWM_Polarity2N_High 0x0001 +#define PWM_Polarity2N_Low 0x0002 + +/* PWM Polarity channel 3N */ +#define PWM_Polarity3N_High 0x0001 +#define PWM_Polarity3N_Low 0x0002 + +/* PWM interrupt sources */ +#define PWM_IT_OC1 0x0100 +#define PWM_IT_OC2 0x0200 +#define PWM_IT_OC3 0x0400 +#define PWM_IT_Update 0x0001 +#define PWM_IT_GlobalUpdate 0x1001 +#define PWM_IT_Emergency 0x8000 + +/* PWM DMA sources */ +#define PWM_DMASource_OC1 0x0100 +#define PWM_DMASource_OC2 0x0200 +#define PWM_DMASource_OC3 0x0400 +#define PWM_DMASource_Update 0x0001 + +/* PWM DMA Base address */ +#define PWM_DMABase_CR 0x0000 +#define PWM_DMABase_SCR 0x0800 +#define PWM_DMABase_OMR1 0x1800 +#define PWM_DMABase_OMR2 0x2000 +#define PWM_DMABase_RSR 0x3000 +#define PWM_DMABase_RER 0x3800 +#define PWM_DMABase_ISR 0x4000 +#define PWM_DMABase_CNT 0x4800 +#define PWM_DMABase_PSC 0x5000 +#define PWM_DMABase_RCR 0x5800 +#define PWM_DMABase_ARR 0x6000 +#define PWM_DMABase_OCR1 0x6800 +#define PWM_DMABase_OCR2 0x7000 +#define PWM_DMABase_OCR3 0x7800 +#define PWM_DMABase_DTR 0xB800 + +/* PWM OCM state */ +#define PWM_OCRMState_Enable 0x0005 +#define PWM_OCRMState_Disable 0x0006 + +/* PWM Flags */ +#define PWM_FLAG_OC1 0x0100 +#define PWM_FLAG_OC2 0x0200 +#define PWM_FLAG_OC3 0x0400 +#define PWM_FLAG_Update 0x0001 +#define PWM_FLAG_Emergency 0x8000 + +/* PWM_ForcedAction */ +#define PWM_ForcedAction_Active 0x000A +#define PWM_ForcedAction_InActive 0x0008 + +/* PWM TRGO Mode */ +#define PWM_TRGOMode_Enable 0x0100 +#define PWM_TRGOMode_Update 0x0200 +#define PWM_TRGOMode_Reset 0x0000 +#define PWM_TRGOMode_OC 0x0300 + +/* PWM Complementary outputs Enable/Disable */ +#define PWM_Complementary_Disable 0x0001 +#define PWM_Complementary_Enable 0x0002 + +/* PWM DTR Access Enable/Disable */ +#define PWM_DTRAccess_Enable 0x0001 +#define PWM_DTRAccess_Disable 0x0002 + +/* PWM Emergency input Enable/Disable */ +#define PWM_Emergency_Disable 0x0000 +#define PWM_Emergency_Enable 0x1000 + +/* OC states */ +#define PWM_OCNState_Disable 0x0001 +#define PWM_OCNState_Enable 0x0002 +#define PWM_OCNState_OffState 0x0003 + +/* OCN states */ +#define PWM_OCState_Disable 0x0004 +#define PWM_OCState_Enable 0x0005 +#define PWM_OCState_OffState 0x0006 + +/* PWM LOCK level */ +#define PWM_LOCKLevel_1 0x0400 +#define PWM_LOCKLevel_2 0x0800 +#define PWM_LOCKLevel_3 0x0C00 +#define PWM_LOCKLevel_OFF 0x0000 + +/* Off State selection for Idle state */ +#define PWM_OSSIState_Disable 0x0000 +#define PWM_OSSIState_Enable 0x2000 + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +void PWM_DeInit(void); +void PWM_Init(PWM_InitTypeDef* PWM_InitStruct); +void PWM_StructInit(PWM_InitTypeDef *PWM_InitStruct); +void PWM_Cmd(FunctionalState Newstate); +void PWM_CtrlPWMOutputs(FunctionalState Newstate); +void PWM_ITConfig(u16 PWM_IT, FunctionalState Newstate); +void PWM_DMAConfig(u16 PWM_DMASources, u16 PWM_OCRMState, u16 PWM_DMABase); +void PWM_DMACmd(u16 PWM_DMASources, FunctionalState Newstate); +void PWM_SetPrescaler(u16 Prescaler); +void PWM_SetPeriod(u16 Period); +void PWM_SetPulse(u16 PWM_Channel, u16 Pulse); +void PWM_SetPulse1(u16 Pulse); +void PWM_SetPulse2(u16 Pulse); +void PWM_SetPulse3(u16 Pulse); +void PWM_DebugCmd(FunctionalState Newstate); +void PWM_CounterModeConfig(u16 PWM_CounterMode); +void PWM_ForcedOCConfig(u16 PWM_Channel, u16 PWM_ForcedAction); +void PWM_SetDeadTime(u16 DeadTime); +void PWM_ResetCounter(void); +void PWM_TRGOSelection(u16 PWM_TRGOMode); +FlagStatus PWM_GetFlagStatus(u16 PWM_FLAG); +void PWM_ClearFlag(u16 PWM_FLAG); +ITStatus PWM_GetITStatus(u16 PWM_IT); +void PWM_ClearITPendingBit(u16 PWM_IT); + +#endif /* __75x_PWM_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_rtc.h b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_rtc.h new file mode 100644 index 000000000..a54dee958 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_rtc.h @@ -0,0 +1,63 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_rtc.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* RTC software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_RTC_H +#define __75x_RTC_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* RTC interrupts define */ +#define RTC_IT_Overflow 0x0004 /* Overflow interrupt */ +#define RTC_IT_Alarm 0x0002 /* Alarm interrupt */ +#define RTC_IT_Second 0x0001 /* Second interrupt */ + +/* RTC interrupts flags */ +#define RTC_FLAG_RTOFF 0x0020 /* RTC Operation OFF flag */ +#define RTC_FLAG_RSF 0x0008 /* Registers Synchronized flag */ +#define RTC_FLAG_Overflow 0x0004 /* Overflow interrupt flag */ +#define RTC_FLAG_Alarm 0x0002 /* Alarm interrupt flag */ +#define RTC_FLAG_Second 0x0001 /* Second interrupt flag */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void RTC_DeInit(void); +void RTC_ITConfig(u16 RTC_IT, FunctionalState NewState); +void RTC_EnterConfigMode(void); +void RTC_ExitConfigMode(void); +u32 RTC_GetCounter(void); +void RTC_SetCounter(u32 CounterValue); +void RTC_SetPrescaler(u32 PrescalerValue); +u32 RTC_GetPrescaler(void); +void RTC_SetAlarm(u32 AlarmValue); +u32 RTC_GetDivider(void); +void RTC_WaitForLastTask(void); +void RTC_WaitForSynchro(void); +FlagStatus RTC_GetFlagStatus(u16 RTC_FLAG); +void RTC_ClearFlag(u16 RTC_FLAG); +ITStatus RTC_GetITStatus(u16 RTC_IT); +void RTC_ClearITPendingBit(u16 RTC_IT); + +#endif /* __75x_RTC_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_smi.h b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_smi.h new file mode 100644 index 000000000..1e4a71bd2 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_smi.h @@ -0,0 +1,111 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_smi.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* SMI software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_SMI_H +#define __75x_SMI_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +/* Exported types ------------------------------------------------------------*/ +typedef struct +{ + u8 SMI_ClockHold; + u8 SMI_Prescaler; + u8 SMI_DeselectTime; +} SMI_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* SMI mode */ +#define SMI_Mode_HW 0xEFFFFFFF +#define SMI_Mode_SW 0x10000000 + +/* Reception Length */ +#define SMI_RxLength_0Bytes 0x00000000 +#define SMI_RxLength_1Byte 0x00000010 +#define SMI_RxLength_2Bytes 0x00000020 +#define SMI_RxLength_3Bytes 0x00000030 +#define SMI_RxLength_4Bytes 0x00000040 + +/* Transmission Length */ +#define SMI_TxLength_0Bytes 0x00000000 +#define SMI_TxLength_1Byte 0x00000001 +#define SMI_TxLength_2Bytes 0x00000002 +#define SMI_TxLength_3Bytes 0x00000003 +#define SMI_TxLength_4Bytes 0x00000004 + +/* SMI memory Banks */ +#define SMI_Bank_0 0x00000001 +#define SMI_Bank_1 0x00000002 +#define SMI_Bank_2 0x00000004 +#define SMI_Bank_3 0x00000008 + +/* SMI Interrupts */ +#define SMI_IT_WC 0x00000200 +#define SMI_IT_TF 0x00000100 + +/* Fast Read Mode */ +#define SMI_FastRead_Disable 0xFFFF7FFF +#define SMI_FastRead_Enable 0x00008000 + +/* Write Burst Mode */ +#define SMI_WriteBurst_Disable 0xDFFFFFFF +#define SMI_WriteBurst_Enable 0x20000000 + +/* SMI Flags */ +#define SMI_FLAG_Bank3_WM 0x00008000 +#define SMI_FLAG_Bank2_WM 0x00004000 +#define SMI_FLAG_Bank1_WM 0x00002000 +#define SMI_FLAG_Bank0_WM 0x00001000 +#define SMI_FLAG_ERF2 0x00000800 +#define SMI_FLAG_ERF1 0x00000400 +#define SMI_FLAG_WC 0x00000200 +#define SMI_FLAG_TF 0x00000100 + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void SMI_DeInit(void); +void SMI_Init(SMI_InitTypeDef* SMI_InitStruct); +void SMI_StructInit(SMI_InitTypeDef* SMI_InitStruct); +void SMI_ModeConfig(u32 SMI_Mode); +void SMI_TxRxLengthConfig(u32 SMI_TxLength, u32 SMI_RxLength); +void SMI_BankCmd(u32 SMI_Bank, FunctionalState NewState); +void SMI_ITConfig(u32 SMI_IT, FunctionalState NewState); +void SMI_SelectBank(u32 SMI_Bank); +void SMI_SendWENCmd(void); +void SMI_SendRSRCmd(void); +void SMI_SendCmd(u32 Command); +void SMI_FastReadConfig(u32 SMI_FastRead); +void SMI_WriteBurstConfig(u32 SMI_WriteBurst); +void SMI_WriteByte(u32 WriteAddr, u8 Data); +void SMI_WriteHalfWord(u32 WriteAddr, u16 Data); +void SMI_WriteWord(u32 WriteAddr, u32 Data); +u8 SMI_ReadByte(u32 ReadAddr); +u16 SMI_ReadHalfWord(u32 ReadAddr); +u32 SMI_ReadWord(u32 ReadAddr); +u8 SMI_ReadMemoryStatusRegister(void); +FlagStatus SMI_GetFlagStatus(u32 SMI_FLAG); +void SMI_ClearFlag(u32 SMI_FLAG); +ITStatus SMI_GetITStatus(u32 SMI_IT); +void SMI_ClearITPendingBit(u32 SMI_IT); + +#endif /* __75x_SMI_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_ssp.h b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_ssp.h new file mode 100644 index 000000000..96dec886a --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_ssp.h @@ -0,0 +1,135 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_SSP.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* SSP software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_SSP_H +#define __75x_SSP_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* SSP Init structure definition */ +typedef struct +{ + u16 SSP_FrameFormat; + u16 SSP_Mode; + u16 SSP_CPOL; + u16 SSP_CPHA; + u16 SSP_DataSize; + u16 SSP_NSS; + u16 SSP_SlaveOutput; + u8 SSP_ClockRate; + u8 SSP_ClockPrescaler; +}SSP_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* SSP Frame Format Select */ +#define SSP_FrameFormat_TI 0x0010 +#define SSP_FrameFormat_Motorola 0xFFCF + +/* SSP Master/Slave Select */ +#define SSP_Mode_Master 0xFFFB +#define SSP_Mode_Slave 0x0004 + +/* SSP Clock Polarity */ +#define SSP_CPOL_Low 0xFFBF +#define SSP_CPOL_High 0x0040 + +/* SSP Clock Phase */ +#define SSP_CPHA_1Edge 0xFF7F +#define SSP_CPHA_2Edge 0x0080 + +/* SSP Data Size */ +#define SSP_DataSize_16b 0x000F +#define SSP_DataSize_15b 0x000E +#define SSP_DataSize_14b 0x000D +#define SSP_DataSize_13b 0x000C +#define SSP_DataSize_12b 0x000B +#define SSP_DataSize_11b 0x000A +#define SSP_DataSize_10b 0x0009 +#define SSP_DataSize_9b 0x0008 +#define SSP_DataSize_8b 0x0007 +#define SSP_DataSize_7b 0x0006 +#define SSP_DataSize_6b 0x0005 +#define SSP_DataSize_5b 0x0004 +#define SSP_DataSize_4b 0x0003 + +/* SSP Slave Select management config */ +#define SSP_NSS_Hard 0xFFEF +#define SSP_NSS_Soft 0x0010 + +/* SSP NSS internal config */ +#define SSP_NSSInternal_Set 0x0020 +#define SSP_NSSInternal_Reset 0xFFDF + +/* SSP Slave output config */ +#define SSP_SlaveOutput_Enable 0xFFF7 +#define SSP_SlaveOutput_Disable 0x0008 + +/* SSP Interrupts */ +#define SSP_IT_TxFifo 0x0008 +#define SSP_IT_RxFifo 0x0004 +#define SSP_IT_RxTimeOut 0x0002 +#define SSP_IT_RxOverrun 0x0001 + +/* SSP Flags */ +#define SSP_FLAG_Busy 0x0024 +#define SSP_FLAG_RxFifoFull 0x0023 +#define SSP_FLAG_RxFifoNotEmpty 0x0022 +#define SSP_FLAG_TxFifoNotFull 0x0021 +#define SSP_FLAG_TxFifoEmpty 0x0020 +#define SSP_FLAG_TxFifo 0x0043 +#define SSP_FLAG_RxFifo 0x0042 +#define SSP_FLAG_RxTimeOut 0x0041 +#define SSP_FLAG_RxOverrun 0x0040 + +/* SSP DMA Requests */ +#define SSP0_DMA_Transmit 0x0002 +#define SSP0_DMA_Receive 0x0001 + +#define SSP0_DMATxReq_Single 0xFFF7 +#define SSP0_DMATxReq_Burst 0x0008 + +#define SSP0_DMARxReq_Single 0xFFFB +#define SSP0_DMARxReq_Burst 0x0004 + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void SSP_DeInit(SSP_TypeDef* SSPx); +void SSP_Init(SSP_TypeDef* SSPx, SSP_InitTypeDef* SSP_InitStruct); +void SSP_StructInit(SSP_InitTypeDef* SSP_InitStruct); +void SSP_Cmd(SSP_TypeDef* SSPx, FunctionalState NewState); +void SSP_ITConfig(SSP_TypeDef* SSPx, u16 SSP_IT, FunctionalState NewState); +void SSP_DMACmd(u16 SSP0_DMAtransfer, FunctionalState NewState); +void SSP_DMATxConfig(u16 SSP0_DMATxReq); +void SSP_DMARxConfig(u16 SSP0_DMARxReq); +void SSP_SendData(SSP_TypeDef* SSPx, u16 Data); +u16 SSP_ReceiveData(SSP_TypeDef* SSPx); +void SSP_LoopBackConfig(SSP_TypeDef* SSPx, FunctionalState NewState); +void SSP_NSSInternalConfig(SSP_TypeDef* SSPx, u16 SSP_NSSState); +FlagStatus SSP_GetFlagStatus(SSP_TypeDef* SSPx, u16 SSP_FLAG); +void SSP_ClearFlag(SSP_TypeDef* SSPx, u16 SSP_FLAG); +ITStatus SSP_GetITStatus(SSP_TypeDef* SSPx, u16 SSP_IT); +void SSP_ClearITPendingBit(SSP_TypeDef* SSPx, u16 SSP_IT); + +#endif /* __75x_SSP_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_tb.h b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_tb.h new file mode 100644 index 000000000..e5054935d --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_tb.h @@ -0,0 +1,93 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_tb.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* TB software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_TB_H +#define __75x_TB_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +/* Exported types ------------------------------------------------------------*/ +typedef struct +{ + u16 TB_Mode; /* TB mode */ + u16 TB_ClockSource; /* TB clock source: CK_TIM or CK_RTC */ + u16 TB_CounterMode; /* TB counter mode */ + u16 TB_ICAPolarity; /* TB Input Capture signal Polarity */ + u16 TB_Prescaler; /* TB Prescaler factor */ + u16 TB_AutoReload; /* TB AutoReload factor */ +} TB_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* TB modes */ +#define TB_Mode_IC 0x0002 +#define TB_Mode_Timing 0x0001 + +/* TB clock source */ +#define TB_ClockSource_CKTIM 0x0001 +#define TB_ClockSource_CKRTC 0x0002 + +/* TB Input capture polarity */ +#define TB_ICAPolarity_Rising 0x7000 +#define TB_ICAPolarity_Falling 0x8000 + +/* TB counter modes */ +#define TB_CounterMode_Up 0x0000 +#define TB_CounterMode_Down 0x0010 +#define TB_CounterMode_CenterAligned 0x0060 + +/* TB interrupt sources */ +#define TB_IT_Update 0x0001 +#define TB_IT_IC 0x0004 +#define TB_IT_GlobalUpdate 0x8001 + +/* TB Flags */ +#define TB_FLAG_IC 0x0004 +#define TB_FLAG_Update 0x0001 + +/* TB Slave Mode Selection */ +#define TB_SMSMode_Trigger 0x0018 +#define TB_SMSMode_Gated 0x0010 +#define TB_SMSMode_External 0x0008 +#define TB_SMSMode_Reset 0x0000 + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void TB_DeInit(void); +void TB_Init(TB_InitTypeDef* TB_InitStruct); +void TB_StructInit(TB_InitTypeDef *TB_InitStruct); +void TB_Cmd(FunctionalState Newstate ); +void TB_ITConfig(u16 TB_IT, FunctionalState Newstate); +void TB_SetPrescaler(u16 Prescaler); +void TB_ResetCounter(void); +void TB_DebugCmd(FunctionalState Newstate); +void TB_CounterModeConfig(u16 TB_CounterMode); +void TB_SLaveModeConfig(u16 TB_SMSMode); +u16 TB_GetCounter(void); +u16 TB_GetICAP1(void); +void TB_SetCounter(u16 Counter); +FlagStatus TB_GetFlagStatus(u16 TB_FLAG); +void TB_ClearFlag(u16 TB_FLAG); +ITStatus TB_GetITStatus(u16 TB_IT); +void TB_ClearITPendingBit(u16 TB_IT); + +#endif /* __75x_TB_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_tim.h b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_tim.h new file mode 100644 index 000000000..02b51321b --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_tim.h @@ -0,0 +1,232 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_tim.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* TIM software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_TIM_H +#define __75x_TIM_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +/* Exported types ------------------------------------------------------------*/ +typedef struct +{ + u16 TIM_Mode; /* Timer Mode */ + u16 TIM_Prescaler; /* Prescaler value */ + u16 TIM_ClockSource; /* Timer clock source */ + u16 TIM_ExtCLKEdge; /* External clock edge */ + u16 TIM_CounterMode; /* Counter mode: Up/Down, Edge aligned or center aligned */ + u16 TIM_Period; /* Period value */ + u16 TIM_Channel; /* Timer Channel: 1, 2 or All */ + u16 TIM_Pulse1; /* PWM or OCM Channel 1 pulse length */ + u16 TIM_Pulse2; /* PWM or OCM Channel 2 pulse length */ + u16 TIM_RepetitivePulse; /* OPM Repetitive pulse state: enable or disable */ + u16 TIM_Polarity1; /* PWM, OCM or OPM Channel 1 polarity */ + u16 TIM_Polarity2; /* PWM or OCM Channel 2 polarity */ + u16 TIM_IC1Selection; /* Input Capture 1 selection: TI1 or TI2 */ + u16 TIM_IC2Selection; /* Input Capture 2 selection: TI1 or TI2 */ + u16 TIM_IC1Polarity; /* Input Capture 1 polarity */ + u16 TIM_IC2Polarity; /* Input Capture 2 polarity */ + u16 TIM_PWMI_ICSelection; /* PWM Input Capture selection: TI1 or TI2 */ + u16 TIM_PWMI_ICPolarity; /* PWM Input Capture Polarity */ +} TIM_InitTypeDef; + +/* Master and slave synchronized Timer peripherals */ +typedef enum +{ + PWM_Master = 0x01, + TIM0_Master, + TIM1_Master, + TIM2_Master +}Master_TypeDef; + +typedef enum +{ + PWM_Slave = 0x05, + TIM0_Slave, + TIM1_Slave, + TIM2_Slave +}Slave_TypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* TIM modes */ +#define TIM_Mode_OCTiming 0x0001 +#define TIM_Mode_OCActive 0x0002 +#define TIM_Mode_OCInactive 0x0003 +#define TIM_Mode_OCToggle 0x0004 +#define TIM_Mode_PWM 0x0005 +#define TIM_Mode_PWMI 0x0006 +#define TIM_Mode_IC 0x0007 +#define TIM_Mode_Encoder1 0x0008 +#define TIM_Mode_Encoder2 0x0009 +#define TIM_Mode_Encoder3 0x000A +#define TIM_Mode_OPM_PWM 0x000B +#define TIM_Mode_OPM_Toggle 0x000C +#define TIM_Mode_OPM_Active 0x000D + +/* TIM Clock Source */ +#define TIM_ClockSource_Internal 0x0001 +#define TIM_ClockSource_TI11 0x0002 +#define TIM_ClockSource_TI12 0x0003 +#define TIM_ClockSource_TI22 0x0004 +#define TIM_ClockSource_TI21 0x0005 + +/* TIM External Clock Edge */ +#define TIM_ExtCLKEdge_Falling 0x0001 +#define TIM_ExtCLKEdge_Rising 0x0002 + +/* TIM Counter Mode */ +#define TIM_CounterMode_Up 0x0000 +#define TIM_CounterMode_Down 0x0010 +#define TIM_CounterMode_CenterAligned1 0x0020 +#define TIM_CounterMode_CenterAligned2 0x0040 +#define TIM_CounterMode_CenterAligned3 0x0060 + +/* TIM Channel */ +#define TIM_Channel_1 0x0001 +#define TIM_Channel_2 0x0002 +#define TIM_Channel_ALL 0x0003 + +/* TIM Polarity channel 1 */ +#define TIM_Polarity1_High 0x0001 +#define TIM_Polarity1_Low 0x0002 + +/* TIM Polarity channel 2 */ +#define TIM_Polarity2_High 0x0001 +#define TIM_Polarity2_Low 0x0002 + +#define TIM_RepetitivePulse_Disable 0x0005 +#define TIM_RepetitivePulse_Enable 0x0006 + +/* TIM Input Capture channel 1 Selection */ +#define TIM_IC1Selection_TI1 0x0001 +#define TIM_IC1Selection_TI2 0x0002 + +/* TIM Input Capture channel 2 Selection */ +#define TIM_IC2Selection_TI1 0x0001 +#define TIM_IC2Selection_TI2 0x0002 + +/* TIM Input Capture channel 1 Polarity */ +#define TIM_IC1Polarity_Falling 0x0001 +#define TIM_IC1Polarity_Rising 0x0002 + +/* TIM Input Capture channel 2 Polarity */ +#define TIM_IC2Polarity_Falling 0x0001 +#define TIM_IC2Polarity_Rising 0x0002 + +/* TIM PWM Input IC Selection */ +#define TIM_PWMI_ICSelection_TI1 0x0001 +#define TIM_PWMI_ICSelection_TI2 0x0002 + +/* TIM PWM Input IC Polarity */ +#define TIM_PWMI_ICPolarity_Falling 0x0003 +#define TIM_PWMI_ICPolarity_Rising 0x0004 + +/* TIM interrupt sources */ +#define TIM_IT_IC1 0x0004 +#define TIM_IT_IC2 0x0008 +#define TIM_IT_OC1 0x0100 +#define TIM_IT_OC2 0x0200 +#define TIM_IT_Update 0x0001 +#define TIM_IT_GlobalUpdate 0x1001 + +/* TIM DMA sources */ +#define TIM_DMASource_IC1 0x0004 +#define TIM_DMASource_IC2 0x0008 +#define TIM_DMASource_OC1 0x0100 +#define TIM_DMASource_OC2 0x0200 +#define TIM_DMASource_Update 0x0001 + +/* TIM DMA Base address */ +#define TIM_DMABase_CR 0x0000 +#define TIM_DMABase_SCR 0x0800 +#define TIM_DMABase_IMCR 0x1000 +#define TIM_DMABase_OMR1 0x1800 +#define TIM_DMABase_RSR 0x3000 +#define TIM_DMABase_RER 0x3800 +#define TIM_DMABase_ISR 0x4000 +#define TIM_DMABase_CNT 0x4800 +#define TIM_DMABase_PSC 0x5000 +#define TIM_DMABase_ARR 0x6000 +#define TIM_DMABase_OCR1 0x6800 +#define TIM_DMABase_OCR2 0x7000 +#define TIM_DMABase_ICR1 0x9800 +#define TIM_DMABase_ICR2 0xA000 + +/* TIM Flags */ +#define TIM_FLAG_IC1 0x0004 +#define TIM_FLAG_IC2 0x0008 +#define TIM_FLAG_OC1 0x0100 +#define TIM_FLAG_OC2 0x0200 +#define TIM_FLAG_Update 0x0001 + +/* TIM_ForcedAction */ +#define TIM_ForcedAction_Active 0x000A +#define TIM_ForcedAction_InActive 0x0008 + +/* TIM synchronization action */ +#define TIM_SynchroAction_Enable 0x0100 +#define TIM_SynchroAction_Update 0x0200 +#define TIM_SynchroAction_Reset 0x0000 +#define TIM_SynchroAction_OC 0x0300 + +/* TIM synchronization mode */ +#define TIM_SynchroMode_Gated 0x0010 +#define TIM_SynchroMode_Trigger 0x0018 +#define TIM_SynchroMode_External 0x0008 +#define TIM_SynchroMode_Reset 0x0000 + +/* OCRM bit states */ +#define TIM_OCRMState_Enable 0x0005 +#define TIM_OCRMState_Disable 0x0006 + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +void TIM_DeInit(TIM_TypeDef *TIMx); +void TIM_Init(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct); +void TIM_StructInit(TIM_InitTypeDef *TIM_InitStruct); +void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState Newstate); +void TIM_ITConfig(TIM_TypeDef *TIMx, u16 TIM_IT, FunctionalState Newstate); +void TIM_PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_Channel, FunctionalState Newstate); +void TIM_DMAConfig(u16 TIM_DMASources, u16 TIM_OCRMState, u16 TIM_DMABase); +void TIM_DMACmd(u16 TIM_DMASources, FunctionalState Newstate); +void TIM_ClockSourceConfig(TIM_TypeDef *TIMx, u16 TIM_ClockSource, + u16 TIM_ExtCLKEdge); +void TIM_SetPrescaler(TIM_TypeDef* TIMx, u16 Prescaler); +void TIM_SetPeriod(TIM_TypeDef* TIMx, u16 Period); +void TIM_SetPulse(TIM_TypeDef* TIMx, u16 TIM_Channel, u16 Pulse); +u16 TIM_GetICAP1(TIM_TypeDef *TIMx); +u16 TIM_GetICAP2(TIM_TypeDef *TIMx); +u16 TIM_GetPWMIPulse(TIM_TypeDef *TIMx); +u16 TIM_GetPWMIPeriod(TIM_TypeDef *TIMx); +void TIM_DebugCmd(TIM_TypeDef *TIMx, FunctionalState Newstate); +void TIM_CounterModeConfig(TIM_TypeDef* TIMx, u16 TIM_CounterMode); +void TIM_ForcedOCConfig(TIM_TypeDef* TIMx, u16 TIM_Channel, + u16 TIM_ForcedAction); +void TIM_ResetCounter(TIM_TypeDef* TIMx); +void TIM_SynchroConfig(Master_TypeDef Master, Slave_TypeDef Slave, + u16 TIM_SynchroAction, u16 TIM_SynchroMode); +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, u16 TIM_FLAG); +void TIM_ClearFlag(TIM_TypeDef* TIMx, u16 TIM_FLAG); +ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, u16 TIM_IT); +void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, u16 TIM_IT); + +#endif /* __75x_TIM_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_type.h b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_type.h new file mode 100644 index 000000000..6f8842700 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_type.h @@ -0,0 +1,71 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_type.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the common data types used for the +* STR75x software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_TYPE_H +#define __75x_TYPE_H + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +typedef signed long s32; +typedef signed short s16; +typedef signed char s8; + +typedef volatile signed long vs32; +typedef volatile signed short vs16; +typedef volatile signed char vs8; + +typedef unsigned long u32; +typedef unsigned short u16; +typedef unsigned char u8; + +typedef volatile unsigned long vu32; +typedef volatile unsigned short vu16; +typedef volatile unsigned char vu8; + +typedef volatile unsigned long const vuc32; /* Read Only */ +typedef volatile unsigned short const vuc16; /* Read Only */ +typedef volatile unsigned char const vuc8; /* Read Only */ + + +typedef enum { FALSE = 0, TRUE = !FALSE } bool; + +typedef enum { RESET = 0, SET = !RESET } FlagStatus, ITStatus; + +typedef enum { DISABLE = 0, ENABLE = !DISABLE} FunctionalState; + +typedef enum { ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +#define U8_MAX ((u8)255) +#define S8_MAX ((s8)127) +#define S8_MIN ((s8)-128) +#define U16_MAX ((u16)65535u) +#define S16_MAX ((s16)32767) +#define S16_MIN ((s16)-32768) +#define U32_MAX ((u32)4294967295uL) +#define S32_MAX ((s32)2147483647) +#define S32_MIN ((s32)-2147483648) + +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +#endif /* __75x_TYPE_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_uart.h b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_uart.h new file mode 100644 index 000000000..6fc5033ab --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_uart.h @@ -0,0 +1,178 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_uart.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* UART software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_UART_H +#define __75x_UART_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* UART FIFO Level enumeration */ +typedef enum +{ + UART_FIFOLevel_1_8 = 0x0000, /* FIFO size 16 bytes, FIFO level 2 bytes */ + UART_FIFOLevel_1_4 = 0x0001, /* FIFO size 16 bytes, FIFO level 4 bytes */ + UART_FIFOLevel_1_2 = 0x0002, /* FIFO size 16 bytes, FIFO level 8 bytes */ + UART_FIFOLevel_3_4 = 0x0003, /* FIFO size 16 bytes, FIFO level 12 bytes */ + UART_FIFOLevel_7_8 = 0x0004 /* FIFO size 16 bytes, FIFO level 14 bytes */ +}UART_FIFOLevel; + +/* UART Init Structure definition */ +typedef struct +{ + u16 UART_WordLength; + u16 UART_StopBits; + u16 UART_Parity; + u32 UART_BaudRate; + u16 UART_HardwareFlowControl; + u16 UART_Mode; + u16 UART_FIFO; + UART_FIFOLevel UART_TxFIFOLevel; + UART_FIFOLevel UART_RxFIFOLevel; +}UART_InitTypeDef; + + +/* UART RTS enumeration */ +typedef enum +{ + RTSRESET = 1, + RTSSET +}UART_RTSTypeDef; + + +/* Exported constants --------------------------------------------------------*/ +/* UART Data Length */ +#define UART_WordLength_5D 0x0000 /* 5 bits Data */ +#define UART_WordLength_6D 0x0020 /* 6 bits Data */ +#define UART_WordLength_7D 0x0040 /* 7 bits Data */ +#define UART_WordLength_8D 0x0060 /* 8 bits Data */ + +/* UART Stop Bits */ +#define UART_StopBits_1 0xFFF7 /* One stop bit is transmitted at + the end of frame */ +#define UART_StopBits_2 0x0008 /* Tow stop bits are transmitted + at the end of frame */ + +/* UART Parity */ +#define UART_Parity_No 0x0000 /* Parity Disable */ +#define UART_Parity_Even 0x0006 /* Even Parity */ +#define UART_Parity_Odd 0x0002 /* Odd Parity */ +#define UART_Parity_OddStick 0x0082 /* 1 is transmitted as bit parity */ +#define UART_Parity_EvenStick 0x0086 /* 0 is transmitted as bit parity */ + +/* UART Hardware Flow Control */ +#define UART_HardwareFlowControl_None 0x0000/* HFC Disable */ +#define UART_HardwareFlowControl_RTS 0x4000/* RTS Enable */ +#define UART_HardwareFlowControl_CTS 0x8000/* CTS Enable */ +#define UART_HardwareFlowControl_RTS_CTS 0xC000/* CTS and RTS Enable */ + +/* UART Mode */ +#define UART_Mode_Rx 0x0200 /* UART Rx Enabled */ +#define UART_Mode_Tx 0x0100 /* UART Tx Enbled */ +#define UART_Mode_Tx_Rx 0x0300 /* UART Tx and Rx Enabled */ + +/* UART FIFO */ +#define UART_FIFO_Disable 0xFFEF /* FIFOs Disable */ +#define UART_FIFO_Enable 0x0010 /* FIFOs Enable */ + +/* UART Interrupt definition */ +#define UART_IT_OverrunError 0x0400 /* Overrun Error interrupt */ +#define UART_IT_BreakError 0x0200 /* Break Error interrupt */ +#define UART_IT_ParityError 0x0100 /* Parity Error interrupt */ +#define UART_IT_FrameError 0x0080 /* Frame Error interrupt */ +#define UART_IT_ReceiveTimeOut 0x0040 /* Receive Time Out interrupt */ +#define UART_IT_Transmit 0x0020 /* Transmit interrupt */ +#define UART_IT_Receive 0x0010 /* Receive interrupt */ +#define UART_IT_CTS 0x0002 /* CTS interrupt */ + +/* UART0 DMA transfer */ +#define UART0_DMATransfer_Single 0xFFF7 /* Single DMA transfer */ +#define UART0_DMATransfer_Burst 0x0008 /* Burst DMA transfer */ + +/* UART0 DMA On Error */ +#define UART0_DMAOnError_Enable 0xFFFB /* DMA receive request enabled + when the UART0 error interrupt + is asserted. */ +#define UART0_DMAOnError_Disable 0x0004 /* DMA receive request disabled + when the UART0 error interrupt + is asserted. */ + +/* UART0 DMA Request */ +#define UART0_DMAReq_Tx 0x0002 /* Transmit DMA Enable */ +#define UART0_DMAReq_Rx 0x0001 /* Receive DMA Enable */ + +/* UART FLAG */ +#define UART_FLAG_OverrunError 0x23 /* Overrun error flag */ +#define UART_FLAG_Break 0x22 /* break error flag */ +#define UART_FLAG_ParityError 0x21 /* parity error flag */ +#define UART_FLAG_FrameError 0x20 /* frame error flag */ +#define UART_FLAG_TxFIFOEmpty 0x47 /* Transmit FIFO Empty flag */ +#define UART_FLAG_RxFIFOFull 0x46 /* Receive FIFO Full flag */ +#define UART_FLAG_TxFIFOFull 0x45 /* Transmit FIFO Full flag */ +#define UART_FLAG_RxFIFOEmpty 0x44 /* Receive FIFO Empty flag */ +#define UART_FLAG_Busy 0x43 /* UART Busy flag */ +#define UART_FLAG_CTS 0x40 /* CTS flag */ +#define UART_RawIT_OverrunError 0x6A /* Overrun Error Masked IT flag */ +#define UART_RawIT_BreakError 0x69 /* Break Error Masked IT flag */ +#define UART_RawIT_ParityError 0x68 /* Parity Error Masked IT flag */ +#define UART_RawIT_FrameError 0x67 /* Frame Error Masked IT flag */ +#define UART_RawIT_ReceiveTimeOut 0x66 /* ReceiveTimeOut Masked IT flag */ +#define UART_RawIT_Transmit 0x65 /* Transmit Masked IT flag */ +#define UART_RawIT_Receive 0x64 /* Receive Masked IT flag */ +#define UART_RawIT_CTS 0x61 /* CTS Masked IT flag */ + +/* UART LIN break length */ +#define UART_LINBreakLength_10 0x0000 /* 10 low bits */ +#define UART_LINBreakLength_11 0x0200 /* 11 low bits */ +#define UART_LINBreakLength_12 0x0400 /* 12 low bits */ +#define UART_LINBreakLength_13 0x0600 /* 13 low bits */ +#define UART_LINBreakLength_14 0x0800 /* 14 low bits */ +#define UART_LINBreakLength_15 0x0A00 /* 15 low bits */ +#define UART_LINBreakLength_16 0x0C00 /* 16 low bits */ +#define UART_LINBreakLength_17 0x0E00 /* 17 low bits */ +#define UART_LINBreakLength_18 0x1000 /* 18 low bits */ +#define UART_LINBreakLength_19 0x1200 /* 19 low bits */ +#define UART_LINBreakLength_20 0x1400 /* 20 low bits */ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void UART_DeInit(UART_TypeDef* UARTx); +void UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef* UART_InitStruct); +void UART_StructInit(UART_InitTypeDef* UART_InitStruct); +void UART_Cmd(UART_TypeDef* UARTx, FunctionalState NewState); +void UART_ITConfig(UART_TypeDef* UARTx, u16 UART_IT, FunctionalState NewState); +void UART_DMAConfig(u16 UART0_DMATransfer, u16 UART0_DMAOnError); +void UART_DMACmd(u16 UART0_DMAReq, FunctionalState NewState); +void UART_LoopBackConfig(UART_TypeDef* UARTx, FunctionalState NewState); +void UART_LINConfig(UART_TypeDef* UARTx, u16 UART_LINBreakLength); +void UART_LINCmd(UART_TypeDef* UARTx, FunctionalState NewState); +void UART_SendData(UART_TypeDef* UARTx, u8 Data); +u8 UART_ReceiveData(UART_TypeDef* UARTx); +void UART_SendBreak(UART_TypeDef* UARTx); +void UART_RTSConfig(UART_TypeDef* UARTx,UART_RTSTypeDef RTSState); +FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, u16 UART_FLAG); +void UART_ClearFlag(UART_TypeDef* UARTx, u16 UART_FLAG); +ITStatus UART_GetITStatus(UART_TypeDef* UARTx, u16 UART_IT); +void UART_ClearITPendingBit(UART_TypeDef* UARTx, u16 UART_IT); + +#endif /* __75x_UART_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_wdg.h b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_wdg.h new file mode 100644 index 000000000..3390b63f3 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_wdg.h @@ -0,0 +1,62 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_wdg.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* WDG software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_WDG_H +#define __75x_WDG_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +/* Exported types ------------------------------------------------------------*/ + typedef struct +{ + u16 WDG_Mode; /* Watchdog or Timer mode */ + u16 WDG_Preload; /* Preload register */ + u8 WDG_Prescaler; /* Prescaler register */ +}WDG_InitTypeDef; +/* Exported constants --------------------------------------------------------*/ + +/* WDG/Timer Select */ +#define WDG_Mode_WDG 0x0001 +#define WDG_Mode_Timer 0xFFFE + +/* WDG End of Count interrupt request */ +#define WDG_IT_EC 0x0001 + +/* WDG end of count Flag */ +#define WDG_FLAG_EC 0x0001 + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void WDG_DeInit(void); +void WDG_Init(WDG_InitTypeDef* WDG_InitStruct); +void WDG_StructInit(WDG_InitTypeDef* WDG_InitStruct); +void WDG_Cmd(FunctionalState NewState); +void WDG_ITConfig(FunctionalState NewState); +u16 WDG_GetCounter(void); +FlagStatus WDG_GetFlagStatus(void); +void WDG_ClearFlag(void); +ITStatus WDG_GetITStatus(void); +void WDG_ClearITPendingBit(void); + +#endif /* __WDG_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/lcd.h b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/lcd.h new file mode 100644 index 000000000..11df54c1b --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/inc/lcd.h @@ -0,0 +1,120 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : lcd.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* lcd software driver. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion ---------------------------------------*/ +#ifndef __LCD_H +#define __LCD_H + +/* Includes --------------------------------------------------------------------*/ +#include "75x_lib.h" + +/* Exported types --------------------------------------------------------------*/ + + /* Data lines configuration mode */ + typedef enum + { + Input, + Output + } DataConfigMode_TypeDef; + + /* Text color mode */ + typedef enum + { + BlackText=0, + WhiteText=1 + } TextColorMode_TypeDef; + + /* Dot On/Off mode */ + typedef enum + { + Dot_On, + Dot_Off + } DotMode_TypeDef; + +/* Exported constants ----------------------------------------------------------*/ + +/* LCD Control pins */ +#define CtrlPin_E2 0x00000001 +#define CtrlPin_E1 0x00000002 +#define CtrlPin_RW 0x00000004 +#define CtrlPin_DI 0x00000008 + +/* LCD Commands */ +#define DISPLAY_ON 0xAF +#define DISPLAY_OFF 0xAE +#define START_LINE 0xC0 +#define START_COLUMN 0x00 +#define CLOCKWISE_OUTPUT 0xA0 +#define DYNAMIC_DRIVE 0xA4 +#define DUTY_CYCLE 0xA9 +#define READ_MODIFY_WRITE_OFF 0xEE +#define SOFTWARE_RESET 0xE2 + +/* LCD Lines when LCD is managed as 2*17 characters */ +#define Line1 0x0 +#define Line2 0x2 + +/* Exported macro --------------------------------------------------------------*/ +/* Exported functions ----------------------------------------------------------*/ +/*----- Low layer function -----*/ +void LCD_CtrlLinesConfig(void); +void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, u32 CtrlPins, BitAction BitVal); +void LCD_DataLinesConfig(DataConfigMode_TypeDef Mode); +void LCD_DataLinesWrite(GPIO_TypeDef* GPIOx, u32 PortVal); + +/*----- Medium layer function -----*/ +void LCD_CheckMasterStatus(void); +void LCD_CheckSlaveStatus(void); +void LCD_SendMasterCmd(u8 Cmd); +void LCD_SendSlaveCmd(u8 Cmd); +void LCD_SendMasterData(u8 Data); +u32 LCD_ReadMasterData(void); +void LCD_SendSlaveData(u8 Data); +u32 LCD_ReadSlaveData(void); +void LCD_SetMasterPage(u8 Page); +void LCD_SetSlavePage(u8 Page); +void LCD_SetMasterColumn(u8 Address); +void LCD_SetSlaveColumn(u8 Address); +void LCD_DrawChar(u8 Line, u8 Column, u8 Width, u8 *Bmp); +u8 LCD_HexToAsciiLow(u8 byte); +u8 LCD_HexToAsciiHigh(u8 byte); +void LCD_SetTextColor(TextColorMode_TypeDef TextColor); + +/*----- High layer function -----*/ +void LCD_Init(void); +/* LCD managed as 2 Lines, 17 characters each one (2Lines*17Char) */ +void LCD_ClearLine(u8 Line); +void LCD_DisplayChar(u8 Line, u8 Column, u8 Ascii, TextColorMode_TypeDef CharMode); +void LCD_DisplayString(u8 Line, u8 *ptr, TextColorMode_TypeDef CharMode); +void LCD_Printf(u8* ptr, ...); +/* LCD managed as 122*32 dots */ +void LCD_ClearMaster(void); +void LCD_ClearSlave(void); +void LCD_Clear(void); +void LCD_DrawMasterGraphic(u8 *Bmp); +void LCD_DrawSlaveGraphic(u8 *Bmp); +void LCD_DrawGraphic(u8 *Bmp); +void LCD_ScrollGraphic(u8 *Bmp, u32 nCount); +void LCD_DrawPixel(u8 XPos, u8 YPos, DotMode_TypeDef Mode); +void LCD_DrawLine(u8 XPos1, u8 YPos1, u8 XPos2, u8 YPos2); +void LCD_DrawBox(u8 XPos, u8 YPos, u8 Dx, u8 Dy); + +#endif /*__LCD_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE******/ diff --git a/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_adc.c b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_adc.c new file mode 100644 index 000000000..93905cb6c --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_adc.c @@ -0,0 +1,869 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_adc.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the ADC software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_adc.h" +#include "75x_mrcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Mask for Power Down Mode */ +#define ADC_PowerDown_Enable 0x8000 +#define ADC_PowerDown_Disable 0x7FFF + +/* Mask for Watchdog Thresholds Enable */ +#define ADC_AnalogWatchdog_Enable 0x8000 +#define ADC_AnalogWatchdog_Disable 0x7FFF + +/* Mask for Injected conversion start */ +#define ADC_Injec_ConversionStart 0x8000 + +/* DMA enable */ +#define ADC_DMA_ExtEnable_Mask 0x4000 + +/* Injected start trigger enable */ +#define ADC_Injec_ExtTrigger_Enable 0x4000 + +/* ADC Masks */ +#define ADC_DMAFirstEnabledChannel_Mask 0x000F +#define ADC_DataRegisterOffset 0x0050 +#define ADC_FirstChannel_Mask 0xFFF0 +#define ADC_ChannelNumber_Mask 0xFC3F +#define ADC_Threshold_Mask 0xFC00 +#define ADC_AnalogWatchdogChannel_Mask 0xC3FF +#define ADC_Prescalers_Mask 0x7F18 +#define ADC_SPEN_Mask 0x8000 +#define ADC_FallingEdge_Mask 0xEFFF +#define ADC_LowLevel_Mask 0x4000 +#define ADC_HighLevel_Mask 0xDFFF +#define ADC_Calibration_Mask 0x0002 + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : ADC_DeInit +* Description : Deinitializes the ADC peripheral registers to their default +* reset values. +* Input : None. +* Output : None +* Return : None. +*******************************************************************************/ +void ADC_DeInit(void) +{ + /* Reset the ADC registers values*/ + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_ADC,ENABLE); + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_ADC,DISABLE); +} + +/******************************************************************************* +* Function Name : ADC_Init +* Description : Initializes the ADC peripheral according to the specified +* parameters in the ADC_InitStruct. +* Input : - ADC_InitStruct: pointer to an ADC_InitTypeDef structure that + contains the configuration information for the ADC peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_Init(ADC_InitTypeDef* ADC_InitStruct) +{ + /* Configure the conversion mode */ + if(ADC_InitStruct->ADC_ConversionMode == ADC_ConversionMode_Scan) + { + /* Set the scan conversion mode */ + ADC->CLR2 |= ADC_ConversionMode_Scan; + } + else + { + /* Set the one-shot conversion mode */ + ADC->CLR2 &= ADC_ConversionMode_OneShot; + } + + /* Configure the external start conversion trigger */ + switch(ADC_InitStruct->ADC_ExtTrigger) + { + case ADC_ExtTrigger_HighLevel: + /* Start conversion on High level of the external trigger (TIM0) */ + ADC->CLR0 &= ADC_HighLevel_Mask; + ADC->CLR0 |= ADC_ExtTrigger_HighLevel; + break; + + case ADC_ExtTrigger_LowLevel: + /* Start conversion on low level of the external trigger (TIM0) */ + ADC->CLR0 &= ADC_ExtTrigger_LowLevel; + ADC->CLR0 |= ADC_LowLevel_Mask; + break; + + case ADC_ExtTrigger_RisingEdge: + /* Start conversion on rising edge of the external trigger (TIM0) */ + ADC->CLR0 |= ADC_ExtTrigger_RisingEdge; + break; + + case ADC_ExtTrigger_FallingEdge: + /* Start conversion on falling edge of the external trigger (TIM0) */ + ADC->CLR0 &= ADC_FallingEdge_Mask; + ADC->CLR0 |= ADC_ExtTrigger_FallingEdge; + break; + + case ADC_ExtTrigger_Disable: + /* Disable the external trigger and start the conversion by software */ + ADC->CLR0 &= ADC_ExtTrigger_Disable; + break; + + default: + break; + } + + /* Configure the auto clock off feature */ + if (ADC_InitStruct->ADC_AutoClockOff == ADC_AutoClockOff_Enable) + { + /* Enable the auto clock off feature */ + ADC->CLR4 |= ADC_AutoClockOff_Enable; + } + else + { + /* Disable the auto clock off feature */ + ADC->CLR4 &= ADC_AutoClockOff_Disable; + } + + /* Clear conversion prescaler CNVP[2:0], sampling prescaler SMPP[2:0] bits + and Sample prescaler enable SPEN bit */ + ADC->CLR1 &= ADC_Prescalers_Mask; + /* Set conversion prescaler value (sampling and conversion prescalers are equal + while SPEN bit is reset */ + ADC->CLR1 |= (ADC_InitStruct->ADC_ConversionPrescaler<<5); + + /* In case ADC_SamplingPrescaler member is different from the conversion one */ + if(ADC_InitStruct->ADC_SamplingPrescaler != ADC_InitStruct->ADC_ConversionPrescaler) + { + /* Set the sampling prescaler value */ + ADC->CLR1 |= ADC_InitStruct->ADC_SamplingPrescaler; + /* Set SPEN bit (sampling and conversion prescalers are different */ + ADC->CLR1 = (ADC->CLR1 | ADC_SPEN_Mask); + } + + /* Clear first channel to be converted FCH[3:0] bits */ + ADC->CLR2 &= ADC_FirstChannel_Mask; + /* Set the first channel to be converted */ + ADC->CLR2 |= ADC_InitStruct->ADC_FirstChannel; + /* Clear number of channels to be converted NCH[3:0] bits */ + ADC->CLR2 &= ADC_ChannelNumber_Mask; + /* Set the number of channels to be converted */ + ADC->CLR2 |= ((ADC_InitStruct->ADC_ChannelNumber)-1<<6); +} + +/******************************************************************************* +* Function Name : ADC_StructInit +* Description : Fills each ADC_InitStruct member with its default value. +* Input : - ADC_InitStruct: pointer to an ADC_InitTypeDef structure + which will be initialized. +* Output : None +* Return : None. +*******************************************************************************/ +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) +{ + /* Initialize the ADC_ConversionMode member */ + ADC_InitStruct->ADC_ConversionMode = ADC_ConversionMode_OneShot; + + /* Initialize the ADC_ExtTrigger member */ + ADC_InitStruct->ADC_ExtTrigger = ADC_ExtTrigger_Disable; + + /* Initialize the ADC_AutoClockOff member */ + ADC_InitStruct->ADC_AutoClockOff = ADC_AutoClockOff_Disable; + + /* Initialize the ADC_SamplingPrescaler member */ + ADC_InitStruct->ADC_SamplingPrescaler = 0; + + /* Initialize the ADC_ConversionPrescaler member */ + ADC_InitStruct->ADC_ConversionPrescaler = 0; + + /* Initialize the ADC_FirstChannel member */ + ADC_InitStruct->ADC_FirstChannel = ADC_CHANNEL0; + + /* Initialize the ADC_ChannelNumber member */ + ADC_InitStruct->ADC_ChannelNumber = 1; + } + +/******************************************************************************* +* Function Name : ADC_StartCalibration +* Description : Starts the ADC Calibration. Calibration average enabled/disabled. +* Input : - ADC_CalibAverage: Enables or disables ADC calibration average. +* This parameter can be one of the following values: +* - ADC_CalibAverage_Enable: enable calibration average +* - ADC_CalibAverage_Disable: disable calibration average +* Output : None +* Return : None +*******************************************************************************/ +void ADC_StartCalibration(u16 ADC_CalibAverage) +{ + if (ADC_CalibAverage == ADC_CalibAverage_Enable) + { + /* Enable ADC Calibration Average */ + ADC->CLR4 &= ADC_CalibAverage_Enable; + } + else + { + /* Disable ADC Calibration Average */ + ADC->CLR4 |= ADC_CalibAverage_Disable; + } + + /* Start Calibration */ + ADC->CLR0 |= ADC_Calibration_ON; +} + +/******************************************************************************* +* Function Name : ADC_GetCalibrationStatus +* Description : Get the ADC Calibration Status. +* Input : None +* Output : None +* Return : The NewState of the ADC calibration (SET or RESET). +*******************************************************************************/ +FlagStatus ADC_GetCalibrationStatus(void) +{ + /* Check the status of the ADC calibration */ + if((ADC->CLR0 & ADC_Calibration_Mask) != RESET) + { + /* Return SET if ADC Calibration is on going */ + return SET; + } + else + { + /* Return RESET if ADC Calibration is finished */ + return RESET; + } +} + +/******************************************************************************* +* Function Name : ADC_ConversionCmd +* Description : Starts or stops the ADC conversion. +* Input : - ADC_Conversion: specifies the ADC command to apply. +* This parameter can be one of the following values: +* - ADC_Conversion_Start: start conversion +* - ADC_Conversion_Stop: stop conversion +* Output : None +* Return : None +*******************************************************************************/ +void ADC_ConversionCmd (u16 ADC_Conversion) +{ + if (ADC_Conversion == ADC_Conversion_Start) + { + /* Start the ADC Conversion */ + ADC->CLR0 |= ADC_Conversion_Start; + } + else + { + /* Stop the ADC Conversion */ + ADC->CLR0 &= ADC_Conversion_Stop; + } +} + +/******************************************************************************* +* Function Name : ADC_GetSTARTBitStatus +* Description : Gets the ADC START/STOP bit Status. +* Input : None +* Output : None +* Return : The NewState of the ADC START/STOP bit (SET or RESET). +*******************************************************************************/ +FlagStatus ADC_GetSTARTBitStatus(void) +{ + /* Check the status of the ADC START/STOP bit */ + if((ADC->CLR0 & ADC_Conversion_Start) != RESET) + { + /* Return SET if ADC Conversion is started */ + return SET; + } + else + { + /* Return RESET if ADC Conversion is stopped */ + return RESET; + } +} + +/******************************************************************************* +* Function Name : ADC_Cmd +* Description : Enables the ADC peripheral or puts it in power down mode. +* - NewState: new state of the ADC peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void ADC_Cmd(FunctionalState NewState) +{ + if (NewState == DISABLE) + { + /* Enable ADC Power Down Mode */ + ADC->CLR4 |= ADC_PowerDown_Enable; + } + else + { + /* Disable ADC Power Down Mode */ + ADC->CLR4 &= ADC_PowerDown_Disable; + } +} + +/******************************************************************************* +* Function Name : ADC_AutoClockOffConfig +* Description : Enables or disables the Auto clock off feature. +* - NewState: new state of the Auto clock off feature. This +* parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void ADC_AutoClockOffConfig(FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Enable ADC Auto Clock Off */ + ADC->CLR4 |= ADC_AutoClockOff_Enable; + } + else + { + /* Disable ADC Auto Clock Off */ + ADC->CLR4 &= ADC_AutoClockOff_Disable; + } +} + +/******************************************************************************* +* Function Name : ADC_AnalogWatchdogConfig +* Description : Configures the analog input channel to be used for the selected +* Analog Watchdog and defines its corresponding High and Low +* threshold values. +* Input : - ADC_AnalogWatchdog: specifies the analog watchdog which will +* be affected to the desired converted channel. This parameter +* can be one of the following values: +* - ADC_AnalogWatchdog0: select analog watchdog 0 +* - ADC_AnalogWatchdog1: select analog watchdog 1 +* - ADC_AnalogWatchdog2: select analog watchdog 2 +* - ADC_AnalogWatchdog3: select analog watchdog 3 +* - ADC_CHANNEL: specifies the channel linked to the selected +* analog watchdog. This parameter can be ADC_CHANNELx where x +* can be (0..15) +* - LowThreshold: Low Threshold for the selected Analog watchdog +* - HighThreshold: High Threshold for the selected Analog watchdog +* Output : None +* Return : None +*******************************************************************************/ +void ADC_AnalogWatchdogConfig(u16 ADC_AnalogWatchdog, u8 ADC_CHANNEL, + u16 LowThreshold, u16 HighThreshold) +{ + switch (ADC_AnalogWatchdog) + { + /* Set the selected channel and their corresponding High and Low thresholds */ + case ADC_AnalogWatchdog0 : + ADC->TRA0 = (ADC->TRA0 & ADC_AnalogWatchdogChannel_Mask) | ((u16) ADC_CHANNEL<<10); + ADC->TRA0 = (ADC->TRA0 & ADC_Threshold_Mask) | HighThreshold; + ADC->TRB0 = (ADC->TRB0 & ADC_Threshold_Mask) | LowThreshold; + break; + + case ADC_AnalogWatchdog1 : + ADC->TRA1 = (ADC->TRA1 & ADC_AnalogWatchdogChannel_Mask) | ((u16) ADC_CHANNEL<<10); + ADC->TRA1 = (ADC->TRA1 & ADC_Threshold_Mask) | HighThreshold; + ADC->TRB1 = (ADC->TRB1 & ADC_Threshold_Mask) | LowThreshold; + break; + + case ADC_AnalogWatchdog2 : + ADC->TRA2 = (ADC->TRA2 & ADC_AnalogWatchdogChannel_Mask) | ((u16) ADC_CHANNEL<<10); + ADC->TRA2 = (ADC->TRA2 & ADC_Threshold_Mask) | HighThreshold; + ADC->TRB2 = (ADC->TRB2 & ADC_Threshold_Mask) | LowThreshold; + break; + + case ADC_AnalogWatchdog3 : + ADC->TRA3 = (ADC->TRA3 & ADC_AnalogWatchdogChannel_Mask) | ((u16) ADC_CHANNEL<<10); + ADC->TRA3 = (ADC->TRA3 & ADC_Threshold_Mask) | HighThreshold; + ADC->TRB3 = (ADC->TRB3 & ADC_Threshold_Mask) | LowThreshold; + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : ADC_AnalogWatchdogCmd +* Description : Enables or disables the selected analog Watchdog. +* Input : - ADC_AnalogWatchdog: specifies the analog watchdog to be +* enabled or disabled. This parameter can be one of the +* following values: +* - ADC_AnalogWatchdog0: select analog watchdog 0 +* - ADC_AnalogWatchdog1: select analog watchdog 1 +* - ADC_AnalogWatchdog2: select analog watchdog 2 +* - ADC_AnalogWatchdog3: select analog watchdog 3 +* - NewState: new state of the specified analog watchdog. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void ADC_AnalogWatchdogCmd(u16 ADC_AnalogWatchdog, FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Enable the selected ADC AnalogWatchdogx */ + switch (ADC_AnalogWatchdog) + { + case ADC_AnalogWatchdog0 : + ADC->TRB0 |= ADC_AnalogWatchdog_Enable; + break; + + case ADC_AnalogWatchdog1 : + ADC->TRB1 |= ADC_AnalogWatchdog_Enable; + break; + + case ADC_AnalogWatchdog2 : + ADC->TRB2 |= ADC_AnalogWatchdog_Enable; + break; + + case ADC_AnalogWatchdog3 : + ADC->TRB3 |= ADC_AnalogWatchdog_Enable; + break; + + default: + break; + } + } + else + { + /* Disable the selected ADC AnalogWatchdogx */ + switch (ADC_AnalogWatchdog) + { + case ADC_AnalogWatchdog0 : + ADC->TRB0 &= ADC_AnalogWatchdog_Disable; + break; + + case ADC_AnalogWatchdog1 : + ADC->TRB1 &= ADC_AnalogWatchdog_Disable; + break; + + case ADC_AnalogWatchdog2 : + ADC->TRB2 &= ADC_AnalogWatchdog_Disable; + break; + + case ADC_AnalogWatchdog3 : + ADC->TRB3 &= ADC_AnalogWatchdog_Disable; + break; + + default: + break; + } + } +} + +/******************************************************************************* +* Function Name : ADC_GetAnalogWatchdogResult +* Description : Returns the comparison result of the selected analog watchdog. +* Input : - ADC_AnalogWatchdog: specifies the analog watchdog channel +* which its comparison result will be returned. This parameter +* can be one of the following values: +* - ADC_AnalogWatchdog0: select analog watchdog 0 +* - ADC_AnalogWatchdog1: select analog watchdog 1 +* - ADC_AnalogWatchdog2: select analog watchdog 2 +* - ADC_AnalogWatchdog3: select analog watchdog 3 +* Output : None +* Return : The analog watchdog comparaison result value +*******************************************************************************/ +u16 ADC_GetAnalogWatchdogResult(u16 ADC_AnalogWatchdog) +{ + /* Return the selected ADC AnalogWatchdogx comparaison result */ + switch(ADC_AnalogWatchdog) + { + case ADC_AnalogWatchdog0 : + return ((ADC->PBR & ADC_AnalogWatchdog)>>4); + + case ADC_AnalogWatchdog1 : + return ((ADC->PBR & ADC_AnalogWatchdog)>>6); + + case ADC_AnalogWatchdog2 : + return ((ADC->PBR & ADC_AnalogWatchdog)>>8); + + case ADC_AnalogWatchdog3 : + return ((ADC->PBR & ADC_AnalogWatchdog)>>10); + + default : return (0xFF); /* if a wrong value of ADC_AnalogWatchdog is selected */ + } +} + +/******************************************************************************* +* Function Name : ADC_InjectedConversionConfig +* Description : Configures the start trigger level for the injected channels +* and the injected analog input channels to be converted. +* Input : - ADC_Injec_ExtTrigger: specifies the start trigger level. +* This parameter can be one of the following values: +* - ADC_Injec_ExtTrigger_Disable : external trigger disabled +* - ADC_Injec_ExtTrigger_RisingEdge: external trigger +* configured as rising edge of PWM Timer TRGO signal +* - ADC_Injec_ExtTrigger_FallingEdge: external trigger +* configured as falling edge of PWM Timer TRGO signal +* - FirstChannel: specifies the first injected channel to be +* converted. +* This parameter can be ADC_CHANNELx where x can be (0..15). +* - ChannelNumber: specifies the Number of the injected channels +* to be converted. This parameter can be a value from 1 to 16. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_InjectedConversionConfig(u16 ADC_Injec_ExtTrigger, u8 FirstChannel, u8 ChannelNumber) +{ + /* Configure the external start injected conversion trigger */ + switch (ADC_Injec_ExtTrigger) + { + case ADC_Injec_ExtTrigger_Disable : + /* Disable the external trigger and start the injected conversion by software */ + ADC->CLR3 &= ADC_Injec_ExtTrigger_Disable ; + break; + case ADC_Injec_ExtTrigger_RisingEdge : + /* Start injected conversion on rising edge of the external trigger (PWM) */ + ADC->CLR3 |= ADC_Injec_ExtTrigger_RisingEdge; + break; + case ADC_Injec_ExtTrigger_FallingEdge : + /* Start injected conversion on falling edge of the external trigger (PWM) */ + ADC->CLR3 |= ADC_Injec_ExtTrigger_Enable; + ADC->CLR3 &= ADC_Injec_ExtTrigger_FallingEdge; + break; + + default: + break; + } + + /* Clear first injected channel to be converted JFCH[3:0] bits */ + ADC->CLR3 &= ADC_FirstChannel_Mask; + /* Set the first injected channel to be converted */ + ADC->CLR3 |= FirstChannel; + /* Clear number of injected channels to be converted JNCH[3:0] bits */ + ADC->CLR3 &= ADC_ChannelNumber_Mask; + /* Set the number of injected channels to be converted */ + ADC->CLR3 |= ((ChannelNumber-1)<<6); +} + +/******************************************************************************* +* Function Name : ADC_StartInjectedConversion +* Description : Starts by software the conversion of the injected input channels. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void ADC_StartInjectedConversion(void) +{ + /* Start the injected ADC Conversion */ + ADC->CLR3 |= ADC_Injec_ConversionStart; +} + +/******************************************************************************* +* Function Name : ADC_GetConversionValue +* Description : Reads the conversion result from the appropriate data register. +* Input : - ADC_CHANNEL :specifies the ADC channel which its conversion +* value have to be returned. This parameter can be ADC_CHANNELx +* where x can be (0..15) to select channelx +* Output : None +* Return : The returned value holds the conversion result of the selected +* channel. +*******************************************************************************/ +u16 ADC_GetConversionValue(u8 ADC_CHANNEL) +{ + /* Return the conversion result of the selected channel */ + return *((u16 *)(ADC_BASE + ((ADC_CHANNEL<<2) + ADC_DataRegisterOffset))); +} + +/******************************************************************************* +* Function Name : ADC_ITConfig +* Description : Enables or disables the specified ADC interrupts. +* Input : - ADC_IT: specifies the ADC interrupts to be enabled or disabled. +* This parameter can be any combination of the following values: +* - ADC_IT_ECH: End of chain conversion interrupt +* - ADC_IT_EOC: End of channel conversion interrupt +* - ADC_IT_JECH: Injected end of chain conversion interrupt +* - ADC_IT_JEOC: Injected end of channel conversion interrupt +* - ADC_IT_AnalogWatchdog0_LowThreshold: +* Analog Watchdog 0 LowThreshold interrupt +* - ADC_IT_AnalogWatchdog0_HighThreshold: +* Analog Watchdog 0 HighThreshold interrupt +* - ADC_IT_AnalogWatchdog1_LowThreshold: +* Analog Watchdog 1 LowThreshold interrupt +* - ADC_IT_AnalogWatchdog1_HighThreshold: +* Analog Watchdog 1 HighThreshold interrupt +* - ADC_IT_AnalogWatchdog2_LowThreshold: +* Analog Watchdog 2 LowThreshold interrupt +* - ADC_IT_AnalogWatchdog2_HighThreshold: +* Analog Watchdog 2 HighThreshold interrupt +* - ADC_IT_AnalogWatchdog3_LowThreshold: +* Analog Watchdog 3 LowThreshold interrupt +* - ADC_IT_AnalogWatchdog3_HighThreshold: +* Analog Watchdog 5 HighThreshold interrupt +* - ADC_IT_ALL: All interrupts +* - NewState: new state of the specified ADC interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_ITConfig(u16 ADC_IT, FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Enable the selected ADC interrupts */ + ADC->IMR |= ADC_IT; + } + else + { + /* Disable the selected ADC interrupts */ + ADC->IMR &= ~ADC_IT; + } +} + +/******************************************************************************* +* Function Name : ADC_DMAConfig +* Description : Configures the ADC’s DMA interface. +* Input : - ADC_DMA_CHANNEL: specifies the channels to be enabled or +* disabled for DMA transfer. This parameter can be any +* combination of ADC_DMA_CHANNELx where x can be (0..15). +* - NewState: new state of the specified ADC DMA channels. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_DMAConfig(u16 ADC_DMA_CHANNEL, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable DMA for the selected channels */ + ADC->DMAR |= ADC_DMA_CHANNEL ; + } + else + { + /* Disable DMA for the selected channels */ + ADC->DMAR &= ~ADC_DMA_CHANNEL; + } +} + +/******************************************************************************* +* Function Name : ADC_DMACmd +* Description : Enable or disable the DMA transfer for the ADC. +* Input : - ADC_DMA: specifies the DMA command. This parameter can be +* one of the following values: +* - ADC_DMA_Disable: disable the DMA capability +* - ADC_DMA_Enable: enabled by setting the global +* enable bit +* - ADC_DMA_ExtTrigger_HighLevel: enabled by detection of +* high level of TIM2 OC2 signal +* - ADC_DMA_ExtTrigger_LowLevel: enabled by detection of +* low level of TIM2 OC2 signal +* Output : None +* Return : None +*******************************************************************************/ +void ADC_DMACmd(u16 ADC_DMA) +{ + /* Configure the DMA external trigger enable */ + switch (ADC_DMA) + { + case ADC_DMA_Disable : + /* Disable DMA transfer */ + ADC->DMAE &= ADC_DMA_Disable; + break; + + case ADC_DMA_Enable : + /* Enable DMA transfer */ + ADC->DMAE |= ADC_DMA_Enable; + break; + + case ADC_DMA_ExtTrigger_HighLevel : + /* Enable DMA transfer on high level of the external trigger (TIM2) */ + ADC->DMAE &= ADC_DMA_Disable; + ADC->DMAE |= ADC_DMA_ExtTrigger_HighLevel; + break; + + case ADC_DMA_ExtTrigger_LowLevel : + /* Enable DMA transfer on low level of the external trigger (TIM2) */ + ADC->DMAE |= ADC_DMA_ExtEnable_Mask; + ADC->DMAE &= ADC_DMA_ExtTrigger_LowLevel; + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : ADC_GetDMAFirstEnabledChannel +* Description : Gets the first DMA-enabled channel configured at the time that +* DMA was last globally enabled. +* Input : None +* Output : None +* Return : The first DMA enabled channel +*******************************************************************************/ +u16 ADC_GetDMAFirstEnabledChannel(void) +{ + /* Return the DMA first enabled channel */ + return (ADC->DMAE & ADC_DMAFirstEnabledChannel_Mask); +} + +/******************************************************************************* +* Function Name : ADC_GetFlagStatus +* Description : Checks whether the specified ADC flag is set or not. +* Input : - ADC_FLAG: specifies the ADC flag to check. This parameter +* can be one of the following values: +* - ADC_FLAG_ECH: End of chain conversion Flag +* - ADC_FLAG_EOC: End of channel conversion Flag +* - ADC_FLAG_JECH: End of injected chain conversion Flag +* - ADC_FLAG_JEOC: End of injected channel conversion Flag +* - ADC_FLAG_AnalogWatchdog0_LowThreshold: +* Analog Watchdog 0 LowThreshold Flag +* - ADC_FLAG_AnalogWatchdog0_HighThreshold: +* Analog Watchdog 0 HighThreshold Flag +* - ADC_FLAG_AnalogWatchdog1_LowThreshold: +* Analog Watchdog 1 LowThreshold Flag +* - ADC_FLAG_AnalogWatchdog1_HighThreshold: +* Analog Watchdog 1 HighThreshold Flag +* - ADC_FLAG_AnalogWatchdog2_LowThreshold: +* Analog Watchdog 2 LowThreshold Flag +* - ADC_FLAG_AnalogWatchdog2_HighThreshold: +* Analog Watchdog 2 HighThreshold Flag +* - ADC_FLAG_AnalogWatchdog3_LowThreshold: +* Analog Watchdog 3 LowThreshold Flag +* - ADC_FLAG_AnalogWatchdog3_HighThreshold: +* Analog Watchdog 3 HighThreshold Flag +* Output : None +* Return : The new state of the ADC_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus ADC_GetFlagStatus(u16 ADC_FLAG) +{ + /* Check the status of the specified ADC flag */ + if((ADC->PBR & ADC_FLAG) != RESET) + { + /* Return SET if ADC_FLAG is set */ + return SET; + } + else + { + /* Return RESET if ADC_FLAG is reset */ + return RESET; + } +} + +/******************************************************************************* +* Function Name : ADC_ClearFlag +* Description : Clears the ADC’s pending flags. +* Input : - ADC_FLAG: specifies the flag to clear. This parameter can +* be any combination of the following values: +* - ADC_FLAG_ECH: End of chain conversion flag +* - ADC_FLAG_EOC: End of channel conversion flag +* - ADC_FLAG_JECH: Injected end of chain conversion flag +* - ADC_FLAG_JEOC: Injected end of channel conversion flag +* - ADC_FLAG_AnalogWatchdog0_LowThreshold: +* Analog Watchdog 0 LowThreshold flag +* - ADC_FLAG_AnalogWatchdog0_HighThreshold: +* Analog Watchdog 0 HighThreshold flag +* - ADC_FLAG_AnalogWatchdog1_LowThreshold: +* Analog Watchdog 1 LowThreshold flag +* - ADC_FLAG_AnalogWatchdog1_HighThreshold: +* Analog Watchdog 1 HighThreshold flag +* - ADC_FLAG_AnalogWatchdog2_LowThreshold: +* Analog Watchdog 2 LowThreshold flag +* - ADC_FLAG_AnalogWatchdog2_HighThreshold: +* Analog Watchdog 2 HighThreshold flag +* - ADC_FLAG_AnalogWatchdog3_LowThreshold: +* Analog Watchdog 3 LowThreshold flag +* - ADC_FLAG_AnalogWatchdog3_HighThreshold: +* Analog Watchdog 3 HighThreshold flag +* Output : None +* Return : None +*******************************************************************************/ +void ADC_ClearFlag(u16 ADC_FLAG) +{ + /* Clear the selected ADC flag */ + ADC->PBR = ADC_FLAG; +} + +/******************************************************************************* +* Function Name : ADC_GetITStatus +* Description : Checks whether the specified ADC interrupt has occured or not. +* Input : - ADC_IT: specifies the ADC interrupt source to check. This +* parameter can be one of the following values: +* - ADC_IT_ECH :End of chain conversion interrupt +* - ADC_IT_EOC :End of channel conversion interrupt +* - ADC_IT_JECH :End of injected chain conversion interrupt +* - ADC_IT_JEOC :End of injected channel conversion interrupt +* - ADC_IT_AnalogWatchdog0_LowThreshold: +* Analog Watchdog 0 LowThreshold interrupt +* - ADC_IT_AnalogWatchdog0_HighThreshold: +* Analog Watchdog 0 HighThreshold interrupt +* - ADC_IT_AnalogWatchdog1_LowThreshold: +* Analog Watchdog 1 LowThreshold interrupt +* - ADC_IT_AnalogWatchdog1_HighThreshold: +* Analog Watchdog 1 HighThreshold interrupt +* - ADC_IT_AnalogWatchdog2_LowThreshold: +* Analog Watchdog 2 LowThreshold interrupt +* - ADC_IT_AnalogWatchdog2_HighThreshold: +* Analog Watchdog 2 HighThreshold interrupt +* - ADC_IT_AnalogWatchdog3_LowThreshold: +* Analog Watchdog 3 LowThreshold interrupt +* - ADC_IT_AnalogWatchdog3_HighThreshold: +* Analog Watchdog 3 HighThreshold interrupt +* Output : None +* Return : The new state of the ADC_IT (SET or RESET). +*******************************************************************************/ +ITStatus ADC_GetITStatus(u16 ADC_IT) +{ + /* Check the status of the specified ADC interrupt */ + if((ADC->PBR & ADC_IT) != RESET) + { + /* Return SET if the ADC interrupt flag is set */ + return SET; + } + else + { + /* Return RESET if the ADC interrupt flag is reset */ + return RESET; + } +} + +/******************************************************************************* +* Function Name : ADC_ClearITPendingBit +* Description : Clears the ADC’s interrupt pending bits. +* Input : - ADC_IT: specifies the interrupt pending bit to clear. This +* parameter can be can be any combination of the following +* values: +* - ADC_IT_ECH: End of chain conversion interrupt +* - ADC_IT_EOC: End of channel conversion interrupt +* - ADC_IT_JECH: Injected end of chain conversion interrupt +* - ADC_IT_JEOC: Injected end of channel conversion interrupt +* - ADC_IT_AnalogWatchdog0_LowThreshold: +* Analog Watchdog 0 LowThreshold interrupt +* - ADC_IT_AnalogWatchdog0_HighThreshold: +* Analog Watchdog 0 HighThreshold interrupt +* - ADC_IT_AnalogWatchdog1_LowThreshold: +* Analog Watchdog 1 LowThreshold interrupt +* - ADC_IT_AnalogWatchdog1_HighThreshold: +* Analog Watchdog 1 HighThreshold interrupt +* - ADC_IT_AnalogWatchdog2_LowThreshold: +* Analog Watchdog 2 LowThreshold interrupt +* - ADC_IT_AnalogWatchdog2_HighThreshold: +* Analog Watchdog 2 HighThreshold interrupt +* - ADC_IT_AnalogWatchdog3_LowThreshold: +* Analog Watchdog 3 LowThreshold interrupt +* - ADC_IT_AnalogWatchdog3_HighThreshold: +* Analog Watchdog 5 HighThreshold interrupt +* Output : None +* Return : None +*******************************************************************************/ +void ADC_ClearITPendingBit(u16 ADC_IT) +{ + /* Clear the selected ADC interrupts pending bits */ + ADC->PBR = ADC_IT; +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_can.c b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_can.c new file mode 100644 index 000000000..0472200ba --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_can.c @@ -0,0 +1,765 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_can.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the CAN software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_can.h" +#include "75x_mrcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/*----------------------------------------------------------------------------*/ +/* Macro Name : xxx_ID_MSK, xxx_ID_ARB */ +/* Description : Form the Mask and Arbitration registers value to filter */ +/* a range of identifiers or a fixed identifier, for standard*/ +/* and extended IDs */ +/*----------------------------------------------------------------------------*/ +#define RANGE_ID_MSK(range_start, range_end) (~((range_end) - (range_start))) +#define RANGE_ID_ARB(range_start, range_end) ((range_start) & (range_end)) + +#define FIXED_ID_MSK(id) RANGE_ID_MSK((id), (id)) +#define FIXED_ID_ARB(id) RANGE_ID_ARB((id), (id)) + +#define STD_RANGE_ID_MSK(range_start, range_end) ((u16)((RANGE_ID_MSK((range_start), (range_end)) & 0x7FF) << 2)) +#define STD_RANGE_ID_ARB(range_start, range_end) ((u16)(RANGE_ID_ARB((range_start), (range_end)) << 2)) + +#define STD_FIXED_ID_MSK(id) ((u16)((FIXED_ID_MSK(id) & 0x7FF) << 2)) +#define STD_FIXED_ID_ARB(id) ((u16)(FIXED_ID_ARB(id) << 2)) + +#define EXT_RANGE_ID_MSK_L(range_start, range_end) ((u16)(RANGE_ID_MSK((range_start), (range_end)) >> 11)) +#define EXT_RANGE_ID_MSK_H(range_start, range_end) ((u16)(STD_RANGE_ID_MSK((range_start), (range_end)) | ((RANGE_ID_MSK((range_start), (range_end)) >> 27) & 0x03))) +#define EXT_RANGE_ID_ARB_L(range_start, range_end) ((u16)(RANGE_ID_ARB((range_start), (range_end)) >> 11)) +#define EXT_RANGE_ID_ARB_H(range_start, range_end) ((u16)(STD_RANGE_ID_ARB((range_start), (range_end)) | ((RANGE_ID_ARB((range_start), (range_end)) >> 27) & 0x03))) + +#define EXT_FIXED_ID_MSK_L(id) ((u16)(FIXED_ID_MSK(id) >> 11)) +#define EXT_FIXED_ID_MSK_H(id) ((u16)(STD_FIXED_ID_MSK(id) | ((FIXED_ID_MSK(id) >> 27) & 0x03))) +#define EXT_FIXED_ID_ARB_L(id) ((u16)(FIXED_ID_ARB(id) >> 11)) +#define EXT_FIXED_ID_ARB_H(id) ((u16)(STD_FIXED_ID_ARB(id) | ((FIXED_ID_ARB(id) >> 27) & 0x03))) + +/* macro to format the timing register value from the timing parameters*/ +#define CAN_TIMING(tseg1, tseg2, sjw, brp) ((((tseg2-1) & 0x07) << 12) | (((tseg1-1) & 0x0F) << 8) | (((sjw-1) & 0x03) << 6) | ((brp-1) & 0x3F)) + +/* Private variables ---------------------------------------------------------*/ +/* array of pre-defined timing parameters for standard bitrates*/ +u16 CanTimings[] = { /* value bitrate NTQ TSEG1 TSEG2 SJW BRP */ + CAN_TIMING(11, 4, 4, 5), /* 0x3AC4 100 kbit/s 16 11 4 4 5 */ + CAN_TIMING(11, 4, 4, 4), /* 0x3AC3 125 kbit/s 16 11 4 4 4 */ + CAN_TIMING( 4, 3, 3, 4), /* 0x2383 250 kbit/s 8 4 3 3 4 */ + CAN_TIMING(13, 2, 1, 1), /* 0x1C00 500 kbit/s 16 13 2 1 1 */ + CAN_TIMING( 4, 3, 1, 1), /* 0x2300 1 Mbit/s 8 4 3 1 1 */ +}; + +/* Private function prototypes -----------------------------------------------*/ +static u32 GetFreeIF(void); +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : CAN_DeInit +* Description : Deinitializes the CAN peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void CAN_DeInit (void) +{ + /* Reset the CAN registers values*/ + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_CAN,ENABLE); + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_CAN,DISABLE); +} + +/******************************************************************************* +* Function Name : CAN_Init +* Description : Initializes the CAN peripheral according to the specified +* parameters in the CAN_InitStruct. +* Input : CAN_InitStruct: pointer to a CAN_InitTypeDef structure that +* contains the configuration information for the CAN peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void CAN_Init(CAN_InitTypeDef* CAN_InitStruct) +{ + CAN_EnterInitMode(CAN_CR_CCE | CAN_InitStruct->CAN_ConfigParameters); + CAN_SetBitrate(CAN_InitStruct->CAN_Bitrate); + CAN_LeaveInitMode(); + CAN_LeaveTestMode(); +} + +/******************************************************************************* +* Function Name : CAN_StructInit +* Description : Fills each CAN_InitStruct member with its reset value. +* Input : CAN_InitStruct : pointer to a CAN_InitTypeDef structure which +* will be initialized. +* Output : None +* Return : None. +*******************************************************************************/ +void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct) +{ +/* Reset CAN init structure parameters values */ + CAN_InitStruct->CAN_ConfigParameters = 0x0; + CAN_InitStruct->CAN_Bitrate = 0x2301; +} + +/******************************************************************************* +* Function Name : CAN_SetBitrate +* Description : Setups a standard CAN bitrate. +* Input : bitrate: specifies the bit rate. +* Output : None +* Return : None +*******************************************************************************/ +void CAN_SetBitrate(u32 bitrate) +{ + CAN->BTR = CanTimings[bitrate]; /* write the predefined timing value */ + CAN->BRPR = 0; /* clear the Extended Baud Rate Prescaler */ +} + +/******************************************************************************* +* Function Name : CAN_SetTiming +* Description : Setups the CAN timing with specific parameters +* Input : - tseg1: specifies Time Segment before the sample point. +* This parameter must be a number between 1 and 16. +* - tseg2: Time Segment after the sample point. This parameter +* must be a number between 1 and 8. +* - sjw: Synchronisation Jump Width. This parameter must be +* a number between 1 and 4. +* - brp: Baud Rate Prescaler. This parameter must be a number +* between 1 and 1024. +* Output : None +* Return : None +*******************************************************************************/ +void CAN_SetTiming(u32 tseg1, u32 tseg2, u32 sjw, u32 brp) +{ + CAN->BTR = CAN_TIMING(tseg1, tseg2, sjw, brp); + CAN->BRPR = ((brp-1) >> 6) & 0x0F; +} + +/******************************************************************************* +* Function Name : GetFreeIF +* Description : Searchs the first free message interface, starting from 0. +* Input : None +* Output : None +* Return : A free message interface number (0 or 1) if found, else 2 +*******************************************************************************/ +static u32 GetFreeIF(void) +{ + if ((CAN->sMsgObj[0].CRR & CAN_CRR_BUSY) == 0) + return 0; + else if ((CAN->sMsgObj[1].CRR & CAN_CRR_BUSY) == 0) + return 1; + else + return 2; +} + +/******************************************************************************* +* Function Name : CAN_SetUnusedMsgObj +* Description : Configures the message object as unused +* Input : msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Interface to treat the message +* - ERROR: No interface found to treat the message +*******************************************************************************/ +ErrorStatus CAN_SetUnusedMsgObj(u32 msgobj) +{ + u32 msg_if=0; + + if ((msg_if = GetFreeIF()) == 2) + { + return ERROR; + } + + CAN->sMsgObj[msg_if].CMR = CAN_CMR_WRRD + | CAN_CMR_MASK + | CAN_CMR_ARB + | CAN_CMR_CONTROL + | CAN_CMR_DATAA + | CAN_CMR_DATAB; + + CAN->sMsgObj[msg_if].M1R = 0; + CAN->sMsgObj[msg_if].M2R = 0; + + CAN->sMsgObj[msg_if].A1R = 0; + CAN->sMsgObj[msg_if].A2R = 0; + + CAN->sMsgObj[msg_if].MCR = 0; + + CAN->sMsgObj[msg_if].DA1R = 0; + CAN->sMsgObj[msg_if].DA2R = 0; + CAN->sMsgObj[msg_if].DB1R = 0; + CAN->sMsgObj[msg_if].DB2R = 0; + + CAN->sMsgObj[msg_if].CRR = 1 + msgobj; + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_SetTxMsgObj +* Description : Configures the message object as TX. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* - idType: specifies the identifier type of the frames that +* will be transmitted using this message object. +* This parameter can be one of the following values: +* - CAN_STD_ID (standard ID, 11-bit) +* - CAN_EXT_ID (extended ID, 29-bit) +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Interface to treat the message +* - ERROR: No interface found to treat the message +*******************************************************************************/ +ErrorStatus CAN_SetTxMsgObj(u32 msgobj, u32 idType) +{ + u32 msg_if=0; + + if ((msg_if = GetFreeIF()) == 2) + { + return ERROR; + } + + CAN->sMsgObj[msg_if].CMR = CAN_CMR_WRRD + | CAN_CMR_MASK + | CAN_CMR_ARB + | CAN_CMR_CONTROL + | CAN_CMR_DATAA + | CAN_CMR_DATAB; + + CAN->sMsgObj[msg_if].M1R = 0; + CAN->sMsgObj[msg_if].A1R = 0; + + if (idType == CAN_STD_ID) + { + CAN->sMsgObj[msg_if].M2R = CAN_M2R_MDIR; + CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | CAN_A2R_DIR; + } + else + { + CAN->sMsgObj[msg_if].M2R = CAN_M2R_MDIR | CAN_M2R_MXTD; + CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | CAN_A2R_DIR | CAN_A2R_XTD; + } + + CAN->sMsgObj[msg_if].MCR = CAN_MCR_TXIE | CAN_MCR_EOB; + + CAN->sMsgObj[msg_if].DA1R = 0; + CAN->sMsgObj[msg_if].DA2R = 0; + CAN->sMsgObj[msg_if].DB1R = 0; + CAN->sMsgObj[msg_if].DB2R = 0; + + CAN->sMsgObj[msg_if].CRR = 1 + msgobj; + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_SetRxMsgObj +* Description : Configures the message object as RX. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* - idType: specifies the identifier type of the frames that +* will be transmitted using this message object. +* This parameter can be one of the following values: +* - CAN_STD_ID (standard ID, 11-bit) +* - CAN_EXT_ID (extended ID, 29-bit) +* - idLow: specifies the low part of the identifier range used +* for acceptance filtering. +* - idHigh: specifies the high part of the identifier range +* used for acceptance filtering. +* - singleOrFifoLast: specifies the end-of-buffer indicator. +* This parameter can be one of the following values: +* - TRUE: for a single receive object or a FIFO receive +* object that is the last one of the FIFO. +* - FALSE: for a FIFO receive object that is not the +* last one. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Interface to treat the message +* - ERROR: No interface found to treat the message +*******************************************************************************/ +ErrorStatus CAN_SetRxMsgObj(u32 msgobj, u32 idType, u32 idLow, u32 idHigh, bool singleOrFifoLast) +{ + u32 msg_if=0; + + if ((msg_if = GetFreeIF()) == 2) + { + return ERROR; + } + + CAN->sMsgObj[msg_if].CMR = CAN_CMR_WRRD + | CAN_CMR_MASK + | CAN_CMR_ARB + | CAN_CMR_CONTROL + | CAN_CMR_DATAA + | CAN_CMR_DATAB; + + if (idType == CAN_STD_ID) + { + CAN->sMsgObj[msg_if].M1R = 0; + CAN->sMsgObj[msg_if].M2R = STD_RANGE_ID_MSK(idLow, idHigh); + + CAN->sMsgObj[msg_if].A1R = 0; + CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | STD_RANGE_ID_ARB(idLow, idHigh); + } + else + { + CAN->sMsgObj[msg_if].M1R = EXT_RANGE_ID_MSK_L(idLow, idHigh); + CAN->sMsgObj[msg_if].M2R = CAN_M2R_MXTD | EXT_RANGE_ID_MSK_H(idLow, idHigh); + + CAN->sMsgObj[msg_if].A1R = EXT_RANGE_ID_ARB_L(idLow, idHigh); + CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | CAN_A2R_XTD | EXT_RANGE_ID_ARB_H(idLow, idHigh); + } + + CAN->sMsgObj[msg_if].MCR = CAN_MCR_RXIE | CAN_MCR_UMASK | (singleOrFifoLast ? CAN_MCR_EOB : 0); + + CAN->sMsgObj[msg_if].DA1R = 0; + CAN->sMsgObj[msg_if].DA2R = 0; + CAN->sMsgObj[msg_if].DB1R = 0; + CAN->sMsgObj[msg_if].DB2R = 0; + + CAN->sMsgObj[msg_if].CRR = 1 + msgobj; + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_InvalidateAllMsgObj +* Description : Configures all the message objects as unused. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void CAN_InvalidateAllMsgObj(void) +{ + u32 i=0; + for (i = 0; i < 32; i++) + CAN_SetUnusedMsgObj(i); +} + + +/******************************************************************************* +* Function Name : CAN_ReleaseMessage +* Description : Releases the message object +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Interface to treat the message +* - ERROR: No interface found to treat the message +*******************************************************************************/ +ErrorStatus CAN_ReleaseMessage(u32 msgobj) +{ + u32 msg_if=0; + + if ((msg_if = GetFreeIF()) == 2) + { + return ERROR; + } + + CAN->sMsgObj[msg_if].CMR = CAN_CMR_CLRINTPND | CAN_CMR_TXRQSTNEWDAT; + CAN->sMsgObj[msg_if].CRR = 1 + msgobj; + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_SendMessage +* Description : Start transmission of a message +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* : - pCanMsg: pointer to the message structure containing data +* to transmit. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Transmission OK +* - ERROR: No transmission +*******************************************************************************/ +ErrorStatus CAN_SendMessage(u32 msgobj, canmsg* pCanMsg) +{ + if (CAN->sMsgObj[0].CRR & CAN_CRR_BUSY) + { + return ERROR; + } + + CAN->SR &= ~CAN_SR_TXOK; + + /* read the Arbitration and Message Control*/ + CAN->sMsgObj[0].CMR = CAN_CMR_ARB | CAN_CMR_CONTROL; + + CAN->sMsgObj[0].CRR = 1 + msgobj; + + if (CAN->sMsgObj[0].CRR & CAN_CRR_BUSY) + { + return ERROR; + } + + /* update the contents needed for transmission*/ + CAN->sMsgObj[0].CMR = CAN_CMR_WRRD + | CAN_CMR_ARB + | CAN_CMR_CONTROL + | CAN_CMR_DATAA + | CAN_CMR_DATAB; + + if ((CAN->sMsgObj[0].A2R & CAN_A2R_XTD) == 0) + { + /* standard ID*/ + CAN->sMsgObj[0].A1R = 0; + CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | STD_FIXED_ID_ARB(pCanMsg->Id); + } + else + { + /* extended ID*/ + CAN->sMsgObj[0].A1R = EXT_FIXED_ID_ARB_L(pCanMsg->Id); + CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | EXT_FIXED_ID_ARB_H(pCanMsg->Id); + } + + CAN->sMsgObj[0].MCR = (CAN->sMsgObj[0].MCR & 0xFEF0) | CAN_MCR_NEWDAT | CAN_MCR_TXRQST | pCanMsg->Dlc; + + CAN->sMsgObj[0].DA1R = ((u16)pCanMsg->Data[1]<<8) | pCanMsg->Data[0]; + CAN->sMsgObj[0].DA2R = ((u16)pCanMsg->Data[3]<<8) | pCanMsg->Data[2]; + CAN->sMsgObj[0].DB1R = ((u16)pCanMsg->Data[5]<<8) | pCanMsg->Data[4]; + CAN->sMsgObj[0].DB2R = ((u16)pCanMsg->Data[7]<<8) | pCanMsg->Data[6]; + + CAN->sMsgObj[0].CRR = 1 + msgobj; + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_ReceiveMessage +* Description : Gets the message, if received. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* - release: specifies the message release indicator. +* This parameter can be one of the following values: +* - TRUE: the message object is released when getting +* the data. +* - FALSE: the message object is not released. +* - pCanMsg: pointer to the message structure where received +* data is copied. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Reception OK +* - ERROR: No message pending +*******************************************************************************/ +ErrorStatus CAN_ReceiveMessage(u32 msgobj, bool release, canmsg* pCanMsg) +{ + if (!CAN_IsMessageWaiting(msgobj)) + { + return ERROR; + } + + CAN->SR &= ~CAN_SR_RXOK; + + /* read the message contents*/ + CAN->sMsgObj[1].CMR = CAN_CMR_MASK + | CAN_CMR_ARB + | CAN_CMR_CONTROL + | CAN_CMR_CLRINTPND + | (release ? CAN_CMR_TXRQSTNEWDAT : 0) + | CAN_CMR_DATAA + | CAN_CMR_DATAB; + + CAN->sMsgObj[1].CRR = 1 + msgobj; + + if (CAN->sMsgObj[1].CRR & CAN_CRR_BUSY) + { + return ERROR; + } + + if ((CAN->sMsgObj[1].A2R & CAN_A2R_XTD) == 0) + { + /* standard ID*/ + pCanMsg->IdType = CAN_STD_ID; + pCanMsg->Id = (CAN->sMsgObj[1].A2R >> 2) & 0x07FF; + } + else + { + /* extended ID*/ + pCanMsg->IdType = CAN_EXT_ID; + pCanMsg->Id = ((CAN->sMsgObj[1].A2R >> 2) & 0x07FF); + pCanMsg->Id |= ((u32)CAN->sMsgObj[1].A1R << 11); + pCanMsg->Id |= (((u32)CAN->sMsgObj[1].A2R & 0x0003) << 27); + } + + pCanMsg->Dlc = CAN->sMsgObj[1].MCR & 0x0F; + + pCanMsg->Data[0] = (u8) CAN->sMsgObj[1].DA1R; + pCanMsg->Data[1] = (u8)(CAN->sMsgObj[1].DA1R >> 8); + pCanMsg->Data[2] = (u8) CAN->sMsgObj[1].DA2R; + pCanMsg->Data[3] = (u8)(CAN->sMsgObj[1].DA2R >> 8); + pCanMsg->Data[4] = (u8) CAN->sMsgObj[1].DB1R; + pCanMsg->Data[5] = (u8)(CAN->sMsgObj[1].DB1R >> 8); + pCanMsg->Data[6] = (u8) CAN->sMsgObj[1].DB2R; + pCanMsg->Data[7] = (u8)(CAN->sMsgObj[1].DB2R >> 8); + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_WaitEndOfTx +* Description : Waits until current transmission is finished. +* Input : None +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Transmission ended +* - ERROR: Transmission did not occur yet +*******************************************************************************/ +ErrorStatus CAN_WaitEndOfTx(void) +{ + if ((CAN->SR & CAN_SR_TXOK) == 0) + { + return ERROR; + } + CAN->SR &= ~CAN_SR_TXOK; + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_BasicSendMessage +* Description : Starts transmission of a message in BASIC mode. This mode +* does not use the message RAM. +* Input : pCanMsg: Pointer to the message structure containing data to +* transmit. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Transmission OK +* - ERROR: No transmission +*******************************************************************************/ +ErrorStatus CAN_BasicSendMessage(canmsg* pCanMsg) +{ + /* clear NewDat bit in IF2 to detect next reception*/ + CAN->sMsgObj[1].MCR &= ~CAN_MCR_NEWDAT; + + CAN->SR &= ~CAN_SR_TXOK; + CAN->sMsgObj[0].CMR = CAN_CMR_WRRD + | CAN_CMR_ARB + | CAN_CMR_CONTROL + | CAN_CMR_DATAA + | CAN_CMR_DATAB; + + if (pCanMsg->IdType == CAN_STD_ID) + { + /* standard ID*/ + CAN->sMsgObj[0].A1R = 0; + CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | STD_FIXED_ID_ARB(pCanMsg->Id); + } + else + { + /* extended ID*/ + CAN->sMsgObj[0].A1R = EXT_FIXED_ID_ARB_L(pCanMsg->Id); + CAN->sMsgObj[0].A2R = ((CAN->sMsgObj[0].A2R) & 0xE000) | EXT_FIXED_ID_ARB_H(pCanMsg->Id); + } + + CAN->sMsgObj[0].MCR = (CAN->sMsgObj[0].MCR & 0xFCF0) | pCanMsg->Dlc; + + CAN->sMsgObj[0].DA1R = ((u16)pCanMsg->Data[1]<<8) | pCanMsg->Data[0]; + CAN->sMsgObj[0].DA2R = ((u16)pCanMsg->Data[3]<<8) | pCanMsg->Data[2]; + CAN->sMsgObj[0].DB1R = ((u16)pCanMsg->Data[5]<<8) | pCanMsg->Data[4]; + CAN->sMsgObj[0].DB2R = ((u16)pCanMsg->Data[7]<<8) | pCanMsg->Data[6]; + + /* request transmission*/ + if (CAN->sMsgObj[0].CRR == CAN_CRR_BUSY ) + { + return ERROR; + } + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_BasicReceiveMessage +* Description : Gets the message in BASIC mode, if received. This mode does +* not use the message RAM. +* Input : pCanMsg: pointer to the message structure where message is copied. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Reception OK +* - ERROR: No message pending +*******************************************************************************/ +ErrorStatus CAN_BasicReceiveMessage(canmsg* pCanMsg) +{ + if ((CAN->sMsgObj[1].MCR & CAN_MCR_NEWDAT) == 0) + { + return ERROR; + } + + CAN->SR &= ~CAN_SR_RXOK; + + CAN->sMsgObj[1].CMR = CAN_CMR_ARB + | CAN_CMR_CONTROL + | CAN_CMR_DATAA + | CAN_CMR_DATAB; + + if ((CAN->sMsgObj[1].A2R & CAN_A2R_XTD) == 0) + { + /* standard ID*/ + pCanMsg->IdType = CAN_STD_ID; + pCanMsg->Id = (CAN->sMsgObj[1].A2R >> 2) & 0x07FF; + } + else + { + /* extended ID*/ + pCanMsg->IdType = CAN_EXT_ID; + pCanMsg->Id = ((CAN->sMsgObj[1].A2R >> 2) & 0x07FF); + pCanMsg->Id |= ((u32)CAN->sMsgObj[1].A1R << 11); + pCanMsg->Id |= (((u32)CAN->sMsgObj[1].A2R & 0x0003) << 27); + } + + pCanMsg->Dlc = CAN->sMsgObj[1].MCR & 0x0F; + + pCanMsg->Data[0] = (u8) CAN->sMsgObj[1].DA1R; + pCanMsg->Data[1] = (u8)(CAN->sMsgObj[1].DA1R >> 8); + pCanMsg->Data[2] = (u8) CAN->sMsgObj[1].DA2R; + pCanMsg->Data[3] = (u8)(CAN->sMsgObj[1].DA2R >> 8); + pCanMsg->Data[4] = (u8) CAN->sMsgObj[1].DB1R; + pCanMsg->Data[5] = (u8)(CAN->sMsgObj[1].DB1R >> 8); + pCanMsg->Data[6] = (u8) CAN->sMsgObj[1].DB2R; + pCanMsg->Data[7] = (u8)(CAN->sMsgObj[1].DB2R >> 8); + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_EnterInitMode +* Description : Switchs the CAN into initialization mode. This function must +* be used in conjunction with CAN_LeaveInitMode(). +* Input : InitMask: specifies the CAN configuration in normal mode. +* Output : None +* Return : None +*******************************************************************************/ +void CAN_EnterInitMode(u8 InitMask) +{ + CAN->CR = InitMask | CAN_CR_INIT; + CAN->SR = 0; /* reset the status*/ +} + +/******************************************************************************* +* Function Name : CAN_LeaveInitMode +* Description : Leaves the initialization mode (switch into normal mode). +* This function must be used in conjunction with CAN_EnterInitMode(). +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void CAN_LeaveInitMode(void) +{ + CAN->CR &= ~(CAN_CR_INIT | CAN_CR_CCE); +} + +/******************************************************************************* +* Function Name : CAN_EnterTestMode +* Description : Switchs the CAN into test mode. This function must be used in +* conjunction with CAN_LeaveTestMode(). +* Input : TestMask: specifies the configuration in test modes. +* Output : None +* Return : None +*******************************************************************************/ +void CAN_EnterTestMode(u8 TestMask) +{ + CAN->CR |= CAN_CR_TEST; + CAN->TESTR |= TestMask; +} + +/******************************************************************************* +* Function Name : CAN_LeaveTestMode +* Description : Leaves the current test mode (switch into normal mode). +* This function must be used in conjunction with CAN_EnterTestMode(). +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void CAN_LeaveTestMode(void) +{ + CAN->CR |= CAN_CR_TEST; + CAN->TESTR &= ~(CAN_TESTR_LBACK | CAN_TESTR_SILENT | CAN_TESTR_BASIC); + CAN->CR &= ~CAN_CR_TEST; +} + +/******************************************************************************* +* Function Name : CAN_ReleaseTxMessage +* Description : Releases the transmit message object. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : None +*******************************************************************************/ +void CAN_ReleaseTxMessage(u32 msgobj) +{ + CAN->sMsgObj[0].CMR = CAN_CMR_CLRINTPND | CAN_CMR_TXRQSTNEWDAT; + CAN->sMsgObj[0].CRR = 1 + msgobj; +} + +/******************************************************************************* +* Function Name : CAN_ReleaseRxMessage +* Description : Releases the receive message object. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : None +*******************************************************************************/ +void CAN_ReleaseRxMessage(u32 msgobj) +{ + CAN->sMsgObj[1].CMR = CAN_CMR_CLRINTPND | CAN_CMR_TXRQSTNEWDAT; + CAN->sMsgObj[1].CRR = 1 + msgobj; +} + +/******************************************************************************* +* Function Name : CAN_IsMessageWaiting +* Description : Tests the waiting status of a received message. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : A non-zero value if the corresponding message object has +* received a message waiting to be copied, else 0. +*******************************************************************************/ +u32 CAN_IsMessageWaiting(u32 msgobj) +{ + return (msgobj < 16 ? CAN->ND1R & (1 << msgobj) : CAN->ND2R & (1 << (msgobj-16))); +} + +/******************************************************************************* +* Function Name : CAN_IsTransmitRequested +* Description : Tests the request status of a transmitted message. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : A non-zero value if the corresponding message is requested +* to transmit, else 0. +*******************************************************************************/ +u32 CAN_IsTransmitRequested(u32 msgobj) +{ + return (msgobj < 16 ? CAN->TXR1R & (1 << msgobj) : CAN->TXR2R & (1 << (msgobj-16))); +} + +/******************************************************************************* +* Function Name : CAN_IsInterruptPending +* Description : Tests the interrupt status of a message object. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : A non-zero value if the corresponding message has an +* interrupt pending, else 0. +*******************************************************************************/ +u32 CAN_IsInterruptPending(u32 msgobj) +{ + return (msgobj < 16 ? CAN->IP1R & (1 << msgobj) : CAN->IP2R & (1 << (msgobj-16))); +} + +/******************************************************************************* +* Function Name : CAN_IsObjectValid +* Description : Tests the validity of a message object (ready to use). +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : A non-zero value if the corresponding message object is +* valid, else 0. +*******************************************************************************/ +u32 CAN_IsObjectValid(u32 msgobj) +{ + return (msgobj < 16 ? CAN->MV1R & (1 << msgobj) : CAN->MV2R & (1 << (msgobj-16))); +} +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_cfg.c b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_cfg.c new file mode 100644 index 000000000..593e8b84d --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_cfg.c @@ -0,0 +1,122 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_cfg.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the CFG software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_cfg.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define CFG_SWBOOT_Mask 0xFFFFFFFC +#define CFG_FLASHBusy_Mask 0x00000080 + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : CFG_BootSpaceConfig +* Description : Selects which memory space will be remapped at address 0x00. +* Input : - CFG_BootSpace: specifies the memory space to be remapped +* at address 0x00. +* This parameter can be one of the following values: +* - CFG_BootSpace_FLASH +* - CFG_BootSpace_SRAM +* - CFG_BootSpace_ExtSMI +* Output : None +* Return : None +*******************************************************************************/ +void CFG_BootSpaceConfig(u32 CFG_BootSpace) +{ + u32 Temp = 0; + + /* Clear SW_BOOT[1:0] bits */ + Temp = CFG->GLCONF & CFG_SWBOOT_Mask; + + /* Set SW_BOOT[1:0] bits according to CFG_BootSpace parameter value */ + Temp |= CFG_BootSpace; + + /* Store the new value */ + CFG->GLCONF = Temp; +} + +/******************************************************************************* +* Function Name : CFG_FLASHBurstConfig +* Description : Enables or disables the FLASH Burst mode. +* Input : - CCFG_FLASHBurst: specifies the new state of the FLASH Burst +* mode. +* This parameter can be one of the following values: +* - CFG_FLASHBurst_Disable +* - CFG_FLASHBurst_Enable +* Output : None +* Return : None +*******************************************************************************/ +void CFG_FLASHBurstConfig(u32 CFG_FLASHBurst) +{ + if(CFG_FLASHBurst == CFG_FLASHBurst_Enable) + { + CFG->GLCONF |= CFG_FLASHBurst_Enable; + } + else + { + CFG->GLCONF &= CFG_FLASHBurst_Disable; + } +} + +/******************************************************************************* +* Function Name : CFG_USBFilterConfig +* Description : Enables or disables the USB Filter. +* Input : - CFG_USBFilter: specifies the new state of the USB Filter. +* This parameter can be one of the following values: +* - CFG_USBFilter_Disable +* - CFG_USBFilter_Enable +* Output : None +* Return : None +*******************************************************************************/ +void CFG_USBFilterConfig(u32 CFG_USBFilter) +{ + if(CFG_USBFilter == CFG_USBFilter_Enable) + { + CFG->GLCONF |= CFG_USBFilter_Enable; + } + else + { + CFG->GLCONF &= CFG_USBFilter_Disable; + } +} + +/******************************************************************************* +* Function Name : CFG_GetFlagStatus +* Description : Checks whether the FLASH Busy flag is set or not. +* Input : None +* Output : None +* Return : The new state of FLASH Busy flag (SET or RESET). +*******************************************************************************/ +FlagStatus CFG_GetFlagStatus(void) +{ + if((CFG->GLCONF & CFG_FLASHBusy_Mask) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_dma.c b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_dma.c new file mode 100644 index 000000000..7bc09466d --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_dma.c @@ -0,0 +1,596 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_dma.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the DMA software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_dma.h" +#include "75x_mrcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* DMA enable */ +#define DMA_Enable 0x0001 +#define DMA_Disable 0xFFFE + +/* DMA Last Buffer Sweep */ +#define DMA_Last0_Enable_Mask 0x0001 +#define DMA_Last0_Disable_Mask 0xFFFE +#define DMA_Last1_Enable_Mask 0x0002 +#define DMA_Last1_Disable_Mask 0xFFFD +#define DMA_Last2_Enable_Mask 0x0004 +#define DMA_Last2_Disable_Mask 0xFFFB +#define DMA_Last3_Enable_Mask 0x0008 +#define DMA_Last3_Disable_Mask 0xFFF7 + +/* DMA Masks */ +#define DMA_Stream0_MASK_Mask 0xFFEE +#define DMA_Stream0_CLR_Mask 0x0011 +#define DMA_Stream0_LAST_Mask 0xFFFE + +#define DMA_Stream1_MASK_Mask 0xFFDD +#define DMA_Stream1_CLR_Mask 0x0022 +#define DMA_Stream1_LAST_Mask 0xFFFD + +#define DMA_Stream2_MASK_Mask 0xFFBB +#define DMA_Stream2_CLR_Mask 0x0044 +#define DMA_Stream2_LAST_Mask 0xFFFB + +#define DMA_Stream3_MASK_Mask 0xFF77 +#define DMA_Stream3_CLR_Mask 0x0088 +#define DMA_Stream3_LAST_Mask 0xFFF7 + +#define DMA_SRCSize_Mask 0xFFE7 +#define DMA_SRCBurst_Mask 0xFF9F +#define DMA_DSTSize_Mask 0xFE7F + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/******************************************************************************* +* Function Name : DMA_DeInit +* Description : Deinitializes the DMA streamx registers to their default reset +* values. +* Input : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA +* Stream. +* Output : None +* Return : None +*******************************************************************************/ +void DMA_DeInit(DMA_Stream_TypeDef* DMA_Streamx) +{ + /* Reset streamx source base address register */ + DMA_Streamx->SOURCEL = 0; + DMA_Streamx->SOURCEH = 0; + + /* Reset streamx destination base address register */ + DMA_Streamx->DESTL = 0; + DMA_Streamx->DESTH = 0; + + /* Reset streamx maximum count register */ + DMA_Streamx->MAX = 0; + /* Reset streamx control register */ + DMA_Streamx->CTRL = 0; + /* Reset streamx last used buffer location register */ + DMA_Streamx->LUBUFF = 0; + + switch(*(u32*)&DMA_Streamx) + { + case DMA_Stream0_BASE: + /* Reset interrupt mask, clear and flag bits for stream0 */ + DMA->MASK &= DMA_Stream0_MASK_Mask; + DMA->CLR |= DMA_Stream0_CLR_Mask; + DMA->LAST &= DMA_Stream0_LAST_Mask; + break; + + case DMA_Stream1_BASE: + /* Reset interrupt mask, clear and flag bits for stream1 */ + DMA->MASK &= DMA_Stream1_MASK_Mask; + DMA->CLR |= DMA_Stream1_CLR_Mask; + DMA->LAST &= DMA_Stream1_LAST_Mask; + break; + + case DMA_Stream2_BASE: + /* Reset interrupt mask, clear and flag bits for stream2 */ + DMA->MASK &= DMA_Stream2_MASK_Mask; + DMA->CLR |= DMA_Stream2_CLR_Mask; + DMA->LAST &= DMA_Stream2_LAST_Mask; + break; + + case DMA_Stream3_BASE: + /* Reset interrupt mask, clear and flag bits for stream3 */ + DMA->MASK &= DMA_Stream3_MASK_Mask; + DMA->CLR |= DMA_Stream3_CLR_Mask; + DMA->LAST &= DMA_Stream3_LAST_Mask; + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : DMA_Init +* Description : Initializes the DMAx stream according to the specified +* parameters in the DMA_InitStruct. +* Input : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA +* Stream. +* - DMA_InitStruct: pointer to a DMA_InitTypeDef structure that +* contains the configuration information for the specified +* DMA stream. +* Output : None +* Return : None +******************************************************************************/ +void DMA_Init(DMA_Stream_TypeDef* DMA_Streamx, DMA_InitTypeDef* DMA_InitStruct) +{ + /* set the buffer Size */ + DMA_Streamx->MAX = DMA_InitStruct->DMA_BufferSize ; + + /* Configure the incrementation of the current source Register */ + if(DMA_InitStruct->DMA_SRC == DMA_SRC_INCR) + { + /* Increment current source register */ + DMA_Streamx->CTRL |= DMA_SRC_INCR; + } + else + { + /* Current source register unchanged */ + DMA_Streamx->CTRL &= DMA_SRC_NOT_INCR; + } + + /* Configure the incrementation of the current destination Register */ + if(DMA_InitStruct->DMA_DST == DMA_DST_INCR) + { + /* Increment current source register */ + DMA_Streamx->CTRL |= DMA_DST_INCR; + } + else + { + /* Current source register unchanged */ + DMA_Streamx->CTRL &= DMA_DST_NOT_INCR; + } + + /* Clear source to DMA data width SOSIZE[1:0] bits */ + DMA_Streamx->CTRL &= DMA_SRCSize_Mask; + /* Set the source to DMA data width */ + DMA_Streamx->CTRL |= DMA_InitStruct->DMA_SRCSize; + + /* Clear the DMA peripheral burst size SOBURST[1:0] bits */ + DMA_Streamx->CTRL &= DMA_SRCBurst_Mask; + /* Set the DMA peripheral burst size */ + DMA_Streamx->CTRL |= DMA_InitStruct->DMA_SRCBurst; + + /* Clear destination to DMA dat width DESIZE[1:0] bits */ + DMA_Streamx->CTRL &= DMA_DSTSize_Mask; + /* Set the destination to DMA data width */ + DMA_Streamx->CTRL |= DMA_InitStruct->DMA_DSTSize; + + /* Configure the circular mode */ + if(DMA_InitStruct->DMA_Mode == DMA_Mode_Circular) + { + /* Set circular mode */ + DMA_Streamx->CTRL |= DMA_Mode_Circular; + } + else + { + /* Set normal mode */ + DMA_Streamx->CTRL &= DMA_Mode_Normal; + } + + /* Configure the direction transfer */ + if(DMA_InitStruct->DMA_DIR == DMA_DIR_PeriphDST) + { + /* Set peripheral as destination */ + DMA_Streamx->CTRL |= DMA_DIR_PeriphDST; + } + else + { + /* Set peripheral as source */ + DMA_Streamx->CTRL &= DMA_DIR_PeriphSRC; + } + + /* Configure the memory to memory transfer only for stream3 */ + if(DMA_Streamx == DMA_Stream3) + { + if(DMA_InitStruct->DMA_M2M == DMA_M2M_Enable) + { + /* Enable memory to memory transfer for stream3 */ + DMA_Streamx->CTRL |= DMA_M2M_Enable; + } + else + { + /* Disable memory to memory transfer for stream3 */ + DMA_Streamx->CTRL &= DMA_M2M_Disable; + } + } + + /* Configure the source base address */ + DMA_Streamx->SOURCEL = DMA_InitStruct->DMA_SRCBaseAddr; + DMA_Streamx->SOURCEH = DMA_InitStruct->DMA_SRCBaseAddr >> 16; + + /* Configure the destination base address */ + DMA_Streamx->DESTL = DMA_InitStruct->DMA_DSTBaseAddr; + DMA_Streamx->DESTH = DMA_InitStruct->DMA_DSTBaseAddr >> 16; +} + +/******************************************************************************* +* Function Name : DMA_StructInit +* Description : Fills each DMA_InitStruct member with its default value. +* Input : DMA_InitStruct : pointer to a DMA_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) +{ + /* Initialize the DMA_BufferSize member */ + DMA_InitStruct->DMA_BufferSize = 0; + + /* initialize the DMA_SRCBaseAddr member */ + DMA_InitStruct->DMA_SRCBaseAddr = 0; + + /* Initialize the DMA_DSTBaseAddr member */ + DMA_InitStruct ->DMA_DSTBaseAddr = 0; + + /* Initialize the DMA_SRC member */ + DMA_InitStruct->DMA_SRC = DMA_SRC_NOT_INCR; + + /* Initialize the DMA_DST member */ + DMA_InitStruct->DMA_DST = DMA_DST_NOT_INCR; + + /* Initialize the DMA_SRCSize member */ + DMA_InitStruct->DMA_SRCSize = DMA_SRCSize_Byte; + + /* Initialize the DMA_SRCBurst member */ + DMA_InitStruct->DMA_SRCBurst = DMA_SRCBurst_1Data; + + /* Initialize the DMA_DSTSize member */ + DMA_InitStruct->DMA_DSTSize = DMA_DSTSize_Byte; + + /* Initialize the DMA_Mode member */ + DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; + + /* Initialize the DMA_M2M member */ + DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; + + /* Initialize the DMA_DIR member */ + DMA_InitStruct->DMA_DIR = DMA_DIR_PeriphSRC; +} + +/******************************************************************************* +* Function Name : DMA_Cmd +* Description : Enables or disables the specified DMA stream. +* Input : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA +* Stream. +* - NewState: new state of the DMAx stream. This parameter can +* be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void DMA_Cmd(DMA_Stream_TypeDef* DMA_Streamx, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable the selected DMA streamx */ + DMA_Streamx->CTRL |= DMA_Enable; + } + else + { + /* Disable the selected DMA streamx */ + DMA_Streamx->CTRL &= DMA_Disable; + } +} + +/******************************************************************************* +* Function Name : DMA_ITConfig +* Description : Enables or disables the specified DMA interrupts. +* Input : - DMA_IT: specifies the DMA interrupts sources to be enabled +* or disabled. This parameter can be any combination of the +* following values: +* - DMA_IT_SI0: Stream0 transfer end interrupt mask +* - DMA_IT_SI1: Stream1 transfer end interrupt mask +* - DMA_IT_SI2: Stream2 transfer end interrupt mask +* - DMA_IT_SI3: Stream3 transfer end interrupt mask +* - DMA_IT_SE0: Stream0 transfer error interrupt mask +* - DMA_IT_SE1: Stream1 transfer error interrupt mask +* - DMA_IT_SE2: Stream2 transfer error interrupt mask +* - DMA_IT_SE3: Stream3 transfer error interrupt mask +* - DMA_IT_ALL: ALL DMA interrupts mask +* - NewState: new state of the specified DMA interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void DMA_ITConfig(u16 DMA_IT, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable the selected DMA interrupts */ + DMA->MASK |= DMA_IT; + } + else + { + /* Disable the selected DMA interrupts */ + DMA->MASK &= ~DMA_IT; + } +} + +/******************************************************************************* +* Function Name : DMA_GetCurrDSTAddr +* Description : Returns the current value of the destination address pointer +* related to the specified DMA stream. +* Input : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA +* Stream. +* Output : None +* Return : The current value of the destination address pointer related +* to the specified DMA stream. +*******************************************************************************/ +u32 DMA_GetCurrDSTAddr(DMA_Stream_TypeDef* DMA_Streamx) +{ + u32 Tmp = 0; + + /* Get high current destination address */ + Tmp = (DMA_Streamx->DECURRH)<<16; + /* Get low current destination address */ + Tmp |= DMA_Streamx->DECURRL; + + /* Return the current destination address value for streamx */ + return Tmp; +} + +/******************************************************************************* +* Function Name : DMA_GetCurrSRCAddr +* Description : Returns the current value of the source address pointer +* related to the specified DMA stream. +* Input : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA +* Stream. +* Output : None +* Return : The current value of the source address pointer related to +* the specified DMA stream. +*******************************************************************************/ +u32 DMA_GetCurrSRCAddr(DMA_Stream_TypeDef* DMA_Streamx) +{ + u32 Tmp = 0; + + /* Get high current source address */ + Tmp = (DMA_Streamx->SOCURRH)<<16; + /* Get slow current source address */ + Tmp |= DMA_Streamx->SOCURRL; + + /* Return the current source address value for streamx */ + return Tmp; +} + +/******************************************************************************* +* Function Name : DMA_GetTerminalCounter +* Description : Returns the number of data units remaining in the current +* DMA stream transfer. +* Input : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA +* Stream. +* Output : None +* Return : The number of data units remaining in the current DMA stream +* transfer. +*******************************************************************************/ +u16 DMA_GetTerminalCounter(DMA_Stream_TypeDef* DMA_Streamx) +{ + /* Return the terminal counter value for streamx */ + return(DMA_Streamx->TCNT); +} + +/******************************************************************************* +* Function Name : DMA_LastBufferSweepConfig +* Description : Activates or disactivates the last buffer sweep mode for the +* DMA streamx configured in circular buffer mode. +* Input : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA +* Stream. +* - NewState: new state of the Last buffer sweep DMA_Streamx. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void DMA_LastBufferSweepConfig(DMA_Stream_TypeDef* DMA_Streamx, FunctionalState NewState) +{ + switch(*(u32*)&DMA_Streamx) + { + case DMA_Stream0_BASE: + if(NewState == ENABLE) + { + /* Activates the last circular buffer sweep mode for stream0 */ + DMA->LAST |= DMA_Last0_Enable_Mask; + } + else + { + /* Disactivates the last circular buffer sweep mode for stream0 */ + DMA->LAST &= DMA_Last0_Disable_Mask; + } + break; + + case DMA_Stream1_BASE: + if(NewState == ENABLE) + { + /* Activates the last circular buffer sweep mode for stream1 */ + DMA->LAST |= DMA_Last1_Enable_Mask; + } + else + { + /* Disactivates the last circular buffer sweep mode for stream1 */ + DMA->LAST &= DMA_Last1_Disable_Mask; + } + break; + + case DMA_Stream2_BASE: + if(NewState == ENABLE) + { + /* Activates the last circular buffer sweep mode for stream2 */ + DMA->LAST |= DMA_Last2_Enable_Mask; + } + else + { + /* Disactivates the last circular buffer sweep mode for stream2 */ + DMA->LAST &= DMA_Last2_Disable_Mask; + } + break; + + case DMA_Stream3_BASE: + if(NewState == ENABLE) + { + /* Activates the last circular buffer sweep mode for stream3 */ + DMA->LAST |= DMA_Last3_Enable_Mask; + } + else + { + /* Disactivates the last circular buffer sweep mode for stream3 */ + DMA->LAST &= DMA_Last3_Disable_Mask; + } + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : DMA_LastBufferAddrConfig +* Description : Configures the circular buffer position where the last data +* to be used by the specified DMA stream is located. +* Input : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA +* Stream. +* - DMA_LastBufferAddr: specifies the circular buffer position +* where the last data to be used by the specified DMA stream +* is located. +* This member must be a number between 0 and the stream BufferSize-1. +* Output : None +* Return : None +*******************************************************************************/ +void DMA_LastBufferAddrConfig(DMA_Stream_TypeDef* DMA_Streamx, u16 DMA_LastBufferAddr) +{ + /* Set the streamx last data circular buffer location */ + DMA_Streamx->LUBUFF = DMA_LastBufferAddr; +} + +/******************************************************************************* +* Function Name : DMA_GetFlagStatus +* Description : Checks whether the specified DMA flag is set or not. +* Input : - DMA_FLAG: specifies the flag to check. This parameter can +* be one of the following values: +* - DMA_FLAG_SI0: Stream0 transfer end flag. +* - DMA_FLAG_SI1: Stream1 transfer end flag. +* - DMA_FLAG_SI2: Stream2 transfer end flag. +* - DMA_FLAG_SI3: Stream3 transfer end flag. +* - DMA_FLAG_SE0: Stream0 transfer error flag. +* - DMA_FLAG_SE1: Stream1 transfer error flag. +* - DMA_FLAG_SE2: Stream2 transfer error flag. +* - DMA_FLAG_SE3: Stream3 transfer error flag. +* - DMA_FLAG_ACT0: Stream0 status. +* - DMA_FLAG_ACT1: Stream1 status. +* - DMA_FLAG_ACT2: Stream2 status. +* - DMA_FLAG_ACT3: Stream3 status. +* Output : None +* Return : The new state of DMA_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus DMA_GetFlagStatus(u16 DMA_FLAG) +{ + /* Check the status of the specified DMA flag */ + if((DMA->STATUS & DMA_FLAG) != RESET) + { + /* Return SET if DMA_FLAG is set */ + return SET; + } + else + { + /* Return RESET if DMA_FLAG is reset */ + return RESET; + } +} + +/******************************************************************************* +* Function Name : DMA_ClearFlag +* Description : Clears the DMA’s pending flags. +* Input : - DMA_FLAG: specifies the flag to clear. This parameter can +* be any combination of the following values: +* - DMA_FLAG_SI0: Stream0 transfer end flag. +* - DMA_FLAG_SI1: Stream1 transfer end flag. +* - DMA_FLAG_SI2: Stream2 transfer end flag. +* - DMA_FLAG_SI3: Stream3 transfer end flag. +* - DMA_FLAG_SE0: Stream0 transfer error flag. +* - DMA_FLAG_SE1: Stream1 transfer error flag. +* - DMA_FLAG_SE2: Stream2 transfer error flag. +* - DMA_FLAG_SE3: Stream3 transfer error flag. +* Output : None +* Return : None +*******************************************************************************/ +void DMA_ClearFlag(u16 DMA_FLAG) +{ + /* Clear the selected DMA flags */ + DMA->CLR = DMA_FLAG ; +} + +/******************************************************************************* +* Function Name : DMA_GetITStatus +* Description : Checks whether the specified DMA interrupt has occured or not. +* Input : - DMA_IT: specifies the DMA interrupt source to check. +* This parameter can be one of the following values: +* - DMA_IT_SI0: Stream0 transfer end interrupt +* - DMA_IT_SI1: Stream1 transfer end interrupt +* - DMA_IT_SI2: Stream2 transfer end interrupt +* - DMA_IT_SI3: Stream3 transfer end interrupt +* - DMA_IT_SE0: Stream0 transfer error interrupt +* - DMA_IT_SE1: Stream1 transfer error interrupt +* - DMA_IT_SE2: Stream2 transfer error interrupt +* - DMA_IT_SE3: Stream3 transfer error interrupt +* Output : None +* Return : The new state of DMA_IT (SET or RESET). +*******************************************************************************/ +ITStatus DMA_GetITStatus(u16 DMA_IT) +{ + /* Check the status of the specified DMA interrupt */ + if((DMA->STATUS & DMA_IT) != RESET) + { + /* Return SET if the DMA interrupt flag is set */ + return SET; + } + else + { + /* Return RESET if the DMA interrupt flag is reset */ + return RESET; + } +} + +/******************************************************************************* +* Function Name : DMA_ClearITPendingBit +* Description : Clears the DMA’s interrupt pending bits. +* Input : - DMA_IT: specifies the interrupt pending bit to clear. +* This parameter can be any combination of the following values: +* - DMA_IT_SI0: Stream0 transfer end interrupt. +* - DMA_IT_SI1: Stream1 transfer end interrupt. +* - DMA_IT_SI2: Stream2 transfer end interrupt. +* - DMA_IT_SI3: Stream3 transfer end interrupt. +* - DMA_IT_SE0: Stream0 transfer error interrupt. +* - DMA_IT_SE1: Stream1 transfer error interrupt. +* - DMA_IT_SE2: Stream2 transfer error interrupt. +* - DMA_IT_SE3: Stream3 transfer error interrupt. +* - DMA_IT_ALL: All DMA interrupts. +* Output : None +* Return : None +*******************************************************************************/ +void DMA_ClearITPendingBit(u16 DMA_IT) +{ + /* Clear the selected DMA interrupts pending bits */ + DMA->CLR = DMA_IT ; +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_eic.c b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_eic.c new file mode 100644 index 000000000..ca9ead80f --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_eic.c @@ -0,0 +1,258 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_eic.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the EIC software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_eic.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define EIC_IRQEnable_Mask 0x00000001 +#define EIC_IRQDisable_Mask 0xFFFFFFFE + +#define EIC_FIQEnable_Mask 0x00000002 +#define EIC_FIQDisable_Mask 0xFFFFFFFD + +#define EIC_SIPL_Mask 0x0000000F +#define EIC_SIPL_Reset_Mask 0xFFFFFFF0 + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : EIC_DeInit +* Description : Deinitializes the EIC peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void EIC_DeInit(void) +{ + EIC->ICR = 0x00; + EIC->CIPR = 0x00; + EIC->FIR = 0x0C; + EIC->IER = 0x00; + EIC->IPR = 0xFFFFFFFF; +} + +/******************************************************************************* +* Function Name : EIC_IRQInit +* Description : Configures the IRQ channels according to the specified +* parameters in the EIC_IRQInitStruct. +* Input : EIC_IRQInitStruct: pointer to a EIC_IRQInitTypeDef structure. +* Output : None +* Return : None +*******************************************************************************/ +void EIC_IRQInit(EIC_IRQInitTypeDef* EIC_IRQInitStruct) +{ + u32 Tmp = 0; + + if(EIC_IRQInitStruct->EIC_IRQChannelCmd == ENABLE) + { + /* Enable the selected IRQ channel */ + EIC->IER |= 1 << EIC_IRQInitStruct->EIC_IRQChannel; + + /* Configure the selected IRQ channel priority ***************************/ + /* Clear SIPL[3:0] bits */ + EIC->SIRn[EIC_IRQInitStruct->EIC_IRQChannel] &= EIC_SIPL_Reset_Mask; + + /* Configure SIPL[3:0] bits according to EIC_IRQChannelPriority parameter */ + Tmp = EIC_IRQInitStruct->EIC_IRQChannelPriority & EIC_SIPL_Mask; + EIC->SIRn[EIC_IRQInitStruct->EIC_IRQChannel] |= Tmp; + } + else + { + /* Disable the select IRQ channel */ + EIC->IER &=~ (1 << EIC_IRQInitStruct->EIC_IRQChannel); + } +} + +/******************************************************************************* +* Function Name : EIC_FIQInit +* Description : Configures the FIQ channels according to the specified +* parameters in the EIC_FIQInitStruct. +* Input : EIC_FIQInitStruct: pointer to a EIC_FIQInitTypeDef structure. +* Output : None +* Return : None +*******************************************************************************/ +void EIC_FIQInit(EIC_FIQInitTypeDef* EIC_FIQInitStruct) +{ + if(EIC_FIQInitStruct->EIC_FIQChannelCmd == ENABLE) + { + /* Enable the selected FIQ channel */ + EIC->FIER |= EIC_FIQInitStruct->EIC_FIQChannel ; + } + else + { + /* Disable the selected FIQ channel */ + EIC->FIER &= ~EIC_FIQInitStruct->EIC_FIQChannel; + } +} + +/******************************************************************************* +* Function Name : EIC_IRQStructInit +* Description : Fills each EIC_IRQInitStruct member with its default value. +* Input : EIC_IRQInitStruct: pointer to a EIC_IRQInitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void EIC_IRQStructInit(EIC_IRQInitTypeDef* EIC_IRQInitStruct) +{ + EIC_IRQInitStruct->EIC_IRQChannel = 0x1F; + EIC_IRQInitStruct->EIC_IRQChannelPriority = 0; + EIC_IRQInitStruct->EIC_IRQChannelCmd = DISABLE; +} + +/******************************************************************************* +* Function Name : EIC_FIQStructInit +* Description : Fills each EIC_FIQInitStruct member with its default value. +* Input : EIC_FIQInitStruct: pointer to a EIC_FIQInitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void EIC_FIQStructInit(EIC_FIQInitTypeDef* EIC_FIQInitStruct) +{ + EIC_FIQInitStruct->EIC_FIQChannel = 0x03; + EIC_FIQInitStruct->EIC_FIQChannelCmd = DISABLE; +} + +/******************************************************************************* +* Function Name : EIC_IRQCmd +* Description : Enables or disables EIC IRQ output request to CPU. +* Input : NewState: new state of the EIC IRQ output request to CPU. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void EIC_IRQCmd(FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable EIC IRQ output request to CPU */ + EIC->ICR |= EIC_IRQEnable_Mask; + } + else + { + /* Disable EIC IRQ output request to CPU */ + EIC->ICR &= EIC_IRQDisable_Mask; + } +} + +/******************************************************************************* +* Function Name : EIC_FIQCmd +* Description : Enables or disables EIC FIQ output request to CPU. +* Input : NewState: new state of the EIC FIQ output request to CPU. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void EIC_FIQCmd(FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable EIC FIQ output request to CPU */ + EIC->ICR |= EIC_FIQEnable_Mask; + } + else + { + /* Disable EIC FIQ output request to CPU */ + EIC->ICR &= EIC_FIQDisable_Mask; + } +} + +/******************************************************************************* +* Function Name : EIC_GetCurrentIRQChannel +* Description : Returns the current served IRQ channel identifier. +* Input : None +* Output : None +* Return : The current served IRQ channel. +*******************************************************************************/ +u8 EIC_GetCurrentIRQChannel(void) +{ + /* Read and return the CIC[4:0] bits of CICR register */ + return ((u8) (EIC->CICR)); +} + +/******************************************************************************* +* Function Name : EIC_GetCurrentIRQChannelPriority +* Description : Returns the priority level of the current served IRQ channel. +* Input : None +* Output : None +* Return : The priority level of the current served IRQ channel. +*******************************************************************************/ +u8 EIC_GetCurrentIRQChannelPriority(void) +{ + /* Read and return the CIP[3:0] bits of CIPR register */ + return ((u8) (EIC->CIPR)); +} + +/******************************************************************************* +* Function Name : EIC_CurrentIRQPriorityConfig +* Description : Changes the priority of the current served IRQ channel. +* The new priority value must be higher, or equal, than the +* priority value associated to the interrupt channel currently +* serviced. +* Input : NewPriority: new priority value of the IRQ interrupt routine +* currently serviced. +* Output : None +* Return : None +*******************************************************************************/ +void EIC_CurrentIRQPriorityConfig(u8 NewPriority) +{ + /* Disable EIC IRQ output request to CPU */ + EIC->ICR &= EIC_IRQDisable_Mask; + + /* Change the current priority */ + EIC->CIPR = NewPriority; + + /* Enable EIC IRQ output request to CPU */ + EIC->ICR |= EIC_IRQEnable_Mask; +} + +/******************************************************************************* +* Function Name : EIC_GetCurrentFIQChannel +* Description : Returns the current served FIQ channel identifier. +* Input : None +* Output : None +* Return : The current served FIQ channel. +*******************************************************************************/ +u8 EIC_GetCurrentFIQChannel(void) +{ + /* Read and return the FIP[1:0] bits of FIPR register */ + return ((u8) (EIC->FIPR)); +} + +/******************************************************************************* +* Function Name : EIC_ClearFIQPendingBit +* Description : Clears the pending bit of the selected FIQ Channel. +* Input : EIC_FIQChannel: specifies the FIQ channel to clear its +* pending bit. +* Output : None +* Return : None +*******************************************************************************/ +void EIC_ClearFIQPendingBit(u8 EIC_FIQChannel) +{ + /* Clear the correspondent FIQ pending bit */ + EIC->FIPR = EIC_FIQChannel ; +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_extit.c b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_extit.c new file mode 100644 index 000000000..997cb24f2 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_extit.c @@ -0,0 +1,179 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_extit.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the EXTIT software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_extit.h" +#include "75x_mrcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : EXTIT_DeInit +* Description : Deinitializes the EXTIT peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void EXTIT_DeInit(void) +{ + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_EXTIT,ENABLE); + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_EXTIT,DISABLE); +} + +/******************************************************************************* +* Function Name : EXTIT_Init +* Description : Initializes the EXTIT peripheral according to the specified +* parameters in the EXTIT_InitStruct . +* Input : - EXTIT_InitStruct: pointer to a EXTIT_InitTypeDef structure +* that contains the configuration information for the EXTIT +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void EXTIT_Init(EXTIT_InitTypeDef* EXTIT_InitStruct) +{ + if(EXTIT_InitStruct->EXTIT_ITLineCmd == ENABLE) + { + /* Enable the selected external interrupts */ + EXTIT->MR |= EXTIT_InitStruct->EXTIT_ITLine; + + /* Select the trigger for the selected external interrupts */ + if(EXTIT_InitStruct->EXTIT_ITTrigger == EXTIT_ITTrigger_Falling) + { + /* Falling edge */ + EXTIT->TSR &= ~EXTIT_InitStruct->EXTIT_ITLine; + } + else if (EXTIT_InitStruct->EXTIT_ITTrigger == EXTIT_ITTrigger_Rising) + { + /* Rising edge */ + EXTIT->TSR |= EXTIT_InitStruct->EXTIT_ITLine; + } + } + else if(EXTIT_InitStruct->EXTIT_ITLineCmd == DISABLE) + { + /* Disable the selected external interrupts */ + EXTIT->MR &= ~EXTIT_InitStruct->EXTIT_ITLine; + } +} + +/******************************************************************************* +* Function Name : EXTIT_StructInit +* Description : Fills each EXTIT_InitStruct member with its reset value. +* Input : - EXTIT_InitStruct: pointer to a EXTIT_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void EXTIT_StructInit(EXTIT_InitTypeDef* EXTIT_InitStruct) +{ + EXTIT_InitStruct->EXTIT_ITLine = EXTIT_ITLineNone; + EXTIT_InitStruct->EXTIT_ITTrigger = EXTIT_ITTrigger_Falling; + EXTIT_InitStruct->EXTIT_ITLineCmd = DISABLE; +} + +/******************************************************************************* +* Function Name : EXTIT_GenerateSWInterrupt +* Description : Generates a Software interrupt. +* Input : - EXTIT_ITLine: specifies the EXTIT lines to be enabled or +* disabled. This parameter can be: +* - EXTIT_ITLinex: External interrupt line x where x(0..15) +* Output : None +* Return : None +*******************************************************************************/ +void EXTIT_GenerateSWInterrupt(u16 EXTIT_ITLine) +{ + EXTIT->SWIR |= EXTIT_ITLine; +} + +/******************************************************************************* +* Function Name : EXTIT_GetFlagStatus +* Description : Checks whether the specified EXTIT line flag is set or not. +* Input : - EXTIT_ITLine: specifies the EXTIT lines flag to check. +* This parameter can be: +* - EXTIT_ITLinex: External interrupt line x where x(0..15) +* Output : None +* Return : The new state of EXTIT_ITLine (SET or RESET). +*******************************************************************************/ +FlagStatus EXTIT_GetFlagStatus(u16 EXTIT_ITLine) +{ + if((EXTIT->PR & EXTIT_ITLine) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : EXTIT_ClearFlag +* Description : Clears the EXTIT’s line pending flags. +* Input : - EXTIT_ITLine: specifies the EXTIT lines flags to clear. +* This parameter can be: +* - EXTIT_ITLinex: External interrupt line x where x(0..15) +* Output : None +* Return : None +*******************************************************************************/ +void EXTIT_ClearFlag(u16 EXTIT_ITLine) +{ + EXTIT->PR = EXTIT_ITLine; +} + +/******************************************************************************* +* Function Name : EXTIT_GetITStatus +* Description : Checks whether the specified EXTIT line is asserted or not. +* Input : - EXTIT_ITLine: specifies the EXTIT lines to check. +* This parameter can be: +* - EXTIT_ITLinex: External interrupt line x where x(0..15) +* Output : None +* Return : The new state of EXTIT_ITLine (SET or RESET). +*******************************************************************************/ +ITStatus EXTIT_GetITStatus(u16 EXTIT_ITLine) +{ + if(((EXTIT->PR & EXTIT_ITLine) != RESET)&& ((EXTIT->MR & EXTIT_ITLine) != RESET)) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : EXTIT_ClearITPendingBit +* Description : Clears the EXTIT’s line pending bits. +* Input : - EXTIT_ITLine: specifies the EXTIT lines to clear. +* This parameter can be: +* - EXTIT_ITLinex: External interrupt line x where x(0..15) +* Output : None +* Return : None +*******************************************************************************/ +void EXTIT_ClearITPendingBit(u16 EXTIT_ITLine) +{ + EXTIT->PR = EXTIT_ITLine; +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_gpio.c b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_gpio.c new file mode 100644 index 000000000..dcc7d7920 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_gpio.c @@ -0,0 +1,320 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_gpio.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the GPIO software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_gpio.h" +#include "75x_mrcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define GPIO_Remap_Mask 0x1F /* GPIO remapping mask */ +#define GPIO_Pin_Mask 0x000FFFFF /* GPIO1 and GPIO2 all pins mask */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : GPIO_DeInit +* Description : Deinitializes the GPIOx peripheral registers to their default +* reset values. +* The I/O remapping register 0 and 1 are not reset by this function. +* Input : GPIOx: where x can be 0,1 or 2 to select the GPIO peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_DeInit(GPIO_TypeDef* GPIOx) +{ + /* Reset the GPIOx registers values */ + GPIOx->PC0 = 0xFFFFFFFF; + GPIOx->PC1 = 0x0; + GPIOx->PC2 = 0x0; + GPIOx->PM = 0x0; +} + +/******************************************************************************* +* Function Name : GPIO_Init +* Description : Initializes the GPIOx peripheral according to the specified +* parameters in the GPIO_InitStruct. This function will not +* change the configuration for a pin if the corresponding mask +* bit is set, except pins configured as input pull-up or pull-down. +* These pins are automatically masked after each configuration. +* Input :- GPIOx: where x can be (0..2) to select the GPIO peripheral. +* - GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that +* contains the configuration information for the specified GPIO +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) +{ + /* GPIOx Mode and Pins Set */ + if((GPIOx != GPIO0) && (GPIO_InitStruct->GPIO_Pin == GPIO_Pin_All)) + { + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_Mask; + } + + switch(GPIO_InitStruct->GPIO_Mode) + { + case GPIO_Mode_AIN: + GPIOx->PC0 &= ~GPIO_InitStruct->GPIO_Pin; + GPIOx->PC1 &= ~GPIO_InitStruct->GPIO_Pin; + GPIOx->PC2 &= ~GPIO_InitStruct->GPIO_Pin; + break; + + case GPIO_Mode_IN_FLOATING: + GPIOx->PC0 |= GPIO_InitStruct->GPIO_Pin; + GPIOx->PC1 &= ~GPIO_InitStruct->GPIO_Pin; + GPIOx->PC2 &= ~GPIO_InitStruct->GPIO_Pin; + break; + + case GPIO_Mode_IPD: + GPIOx->PM &= ~GPIO_InitStruct->GPIO_Pin; + GPIOx->PC0 |= GPIO_InitStruct->GPIO_Pin; + GPIOx->PC1 |= GPIO_InitStruct->GPIO_Pin; + GPIOx->PC2 &= ~GPIO_InitStruct->GPIO_Pin; + GPIOx->PD &= ~GPIO_InitStruct->GPIO_Pin; + GPIOx->PM |= GPIO_InitStruct->GPIO_Pin; + break; + + case GPIO_Mode_IPU: + GPIOx->PM &= ~GPIO_InitStruct->GPIO_Pin; + GPIOx->PC0 |= GPIO_InitStruct->GPIO_Pin; + GPIOx->PC1 |= GPIO_InitStruct->GPIO_Pin; + GPIOx->PC2 &= ~GPIO_InitStruct->GPIO_Pin; + GPIOx->PD |= GPIO_InitStruct->GPIO_Pin; + GPIOx->PM |= GPIO_InitStruct->GPIO_Pin; + break; + + case GPIO_Mode_Out_OD: + GPIOx->PC0 &= ~GPIO_InitStruct->GPIO_Pin; + GPIOx->PC1 &= ~GPIO_InitStruct->GPIO_Pin; + GPIOx->PC2 |= GPIO_InitStruct->GPIO_Pin; + break; + + case GPIO_Mode_Out_PP: + GPIOx->PC0 |= GPIO_InitStruct->GPIO_Pin; + GPIOx->PC1 &= ~GPIO_InitStruct->GPIO_Pin; + GPIOx->PC2 |= GPIO_InitStruct->GPIO_Pin; + break; + + case GPIO_Mode_AF_OD: + GPIOx->PD |= GPIO_InitStruct->GPIO_Pin; + GPIOx->PC1 |= GPIO_InitStruct->GPIO_Pin; + GPIOx->PC0 &= ~GPIO_InitStruct->GPIO_Pin; + GPIOx->PC2 |= GPIO_InitStruct->GPIO_Pin; + break; + + case GPIO_Mode_AF_PP: + GPIOx->PC0 |= GPIO_InitStruct->GPIO_Pin; + GPIOx->PC1 |= GPIO_InitStruct->GPIO_Pin; + GPIOx->PC2 |= GPIO_InitStruct->GPIO_Pin; + break; + + default : + GPIOx->PC0 |= GPIO_InitStruct->GPIO_Pin; + GPIOx->PC1 &= ~GPIO_InitStruct->GPIO_Pin; + GPIOx->PC2 &= ~GPIO_InitStruct->GPIO_Pin; + break; + } +} + +/******************************************************************************* +* Function Name : GPIO_StructInit +* Description : Fills each GPIO_InitStruct member with its default value. +* Input : GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) +{ + /* Reset GPIO init structure parameters values */ + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; +} + +/******************************************************************************* +* Function Name : GPIO_Read +* Description : Reads the specified GPIO data port. +* Input : GPIOx: where x can be 0,1 or 2 to select the GPIO peripheral. +* Output : None +* Return : GPIO data port word value. +*******************************************************************************/ +u32 GPIO_Read(GPIO_TypeDef* GPIOx) +{ + return GPIOx->PD; +} + +/******************************************************************************* +* Function Name : GPIO_ReadBit +* Description : Reads the specified data port bit. +* Input : - GPIOx: where x can be (0..2) to select the GPIO peripheral. +* : - GPIO_Pin: specifies the port bit to read. +* This parameter can be GPIO_Pin_x where x can be (0..31) for +* GPIO0 and x(0..19) for GPIO1 and GPIO2. +* Output : None +* Return : The port pin value +*******************************************************************************/ +u8 GPIO_ReadBit(GPIO_TypeDef* GPIOx, u32 GPIO_Pin) +{ + if ((GPIOx->PD & GPIO_Pin) != Bit_RESET) + { + return Bit_SET; + } + else + { + return Bit_RESET; + } +} + +/******************************************************************************* +* Function Name : GPIO_Write +* Description : Writes data to the specified GPIO data port. +* Input :- GPIOx: where x can be 0,1 or 2 to select the GPIO peripheral. +* - PortVal: specifies the value to be written to the data port +* register. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_Write(GPIO_TypeDef* GPIOx, u32 PortVal) +{ + GPIOx->PD = PortVal; +} + +/******************************************************************************* +* Function Name : GPIO_WriteBit +* Description : Sets or clears the selected data port bit. +* Input : - GPIOx: where x can be (0..2) to select the GPIO peripheral. +* - GPIO_Pin: specifies the port bit to be written. +* This parameter can be GPIO_Pin_x where x can be (0..31) for +* GPIO0 and x(0..19) for GPIO1 and GPIO2. +* - BitVal: specifies the value to be written to the selected bit. +* This parameter must be one of the BitAction enum values: +* - Bit_RESET: to clear the port pin +* - Bit_SET: to set the port pin +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u32 GPIO_Pin, BitAction BitVal) +{ + if(BitVal != Bit_RESET) + { + GPIOx->PD |= GPIO_Pin; + } + else + { + GPIOx->PD &= ~GPIO_Pin; + } +} + +/******************************************************************************* +* Function Name : GPIO_PinMaskConfig +* Description : Enables or disables write protection to the selected bits in +* the I/O port registers (PxC2, PxC1, PxC0 and PxD). +* Input :- GPIOx: where x can be 0,1 or 2 to select the GPIO peripheral. +* - GPIO_Pin: specifies the port bit to be protected. +* This parameter can be GPIO_Pin_x where x can be (0..31) for +* GPIO0 and x(0..19) for GPIO1 and GPIO2. +* - NewState: new state of the port pin. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_PinMaskConfig(GPIO_TypeDef* GPIOx, u32 GPIO_Pin, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + GPIOx->PM |= GPIO_Pin; + } + else + { + GPIOx->PM &= ~GPIO_Pin; + } +} + +/******************************************************************************* +* Function Name : GPIO_GetPortMask +* Description : Gets the GPIOx port mask value. +* Input : GPIOx: where x can be 0,1 or 2 to select the GPIO peripheral. +* Output : None +* Return : GPIO port mask value. +*******************************************************************************/ +u32 GPIO_GetPortMask(GPIO_TypeDef* GPIOx) +{ + return GPIOx->PM; +} + +/******************************************************************************* +* Function Name : GPIO_PinRemapConfig +* Description : Changes the mapping of the specified pin. +* Input :- GPIO_Remap: selects the pin to remap. +* This parameter can be one of the following values: +* - GPIO_Remap_SMI_CS3_EN: Enable SMI CS3 +* - GPIO_Remap_SMI_CS2_EN: Enable SMI CS2 +* - GPIO_Remap_SMI_CS1_EN: Enable SMI CS1 +* - GPIO_Remap_SMI_EN: Enable SMI Alternate Functions: +* SMI_CS0, SMI_CK, SMI_DIN and SMI_DOUT +* - GPIO_Remap_DBGOFF: JTAG Disable +* - GPIO_Remap_UART1: UART1 Alternate Function mapping +* - GPIO_Remap_UART2: UART2 Alternate Function mapping +* - GPIO_Remap_SSP1: SSP1 Alternate Function mapping +* - GPIO_Remap_TIM2: TIM2 Alternate Function mapping +* - GPIO_Remap_TIM0: TIM0 Alternate Function mapping +* - NewState: new state of the port pin. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_PinRemapConfig(u16 GPIO_Remap, FunctionalState NewState) +{ + u32 GPIOReg = 0; + u32 PinPos = 0; + + /* Get the GPIO register index */ + GPIOReg = GPIO_Remap >> 5; + + /* Get the pin position */ + PinPos = GPIO_Remap & GPIO_Remap_Mask; + + if(GPIOReg == 1) /* The pin to remap is in REMAP0R register */ + { + if(NewState == ENABLE) + { + GPIOREMAP->REMAP0R |= (1 << PinPos); + } + else + { + GPIOREMAP->REMAP0R &= ~(1 << PinPos); + } + } + else if(GPIOReg == 2) /* The pin to remap is in REMAP1R register */ + { + if(NewState == ENABLE) + { + GPIOREMAP->REMAP1R |= (1 << PinPos); + } + else + { + GPIOREMAP->REMAP1R &= ~(1 << PinPos); + } + } +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_i2c.c b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_i2c.c new file mode 100644 index 000000000..e5e5d001c --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_i2c.c @@ -0,0 +1,568 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_i2c.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the I2C software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_i2c.h" +#include "75x_mrcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* I2C IT enable */ +#define I2C_IT_Enable 0x01 +#define I2C_IT_Disable 0xFE + +/* I2C Peripheral Enable/Disable */ +#define I2C_PE_Set 0x20 +#define I2C_PE_Reset 0xDF + +/* I2C START Enable/Disable */ +#define I2C_Start_Enable 0x08 +#define I2C_Start_Disable 0xF7 + +/* I2C STOP Enable/Disable */ +#define I2C_Stop_Enable 0x02 +#define I2C_Stop_Disable 0xFD + +/* Address direction bit */ +#define I2C_ADD0_Set 0x01 +#define I2C_ADD0_Reset 0xFE + +/* I2C Masks */ +#define I2C_Frequency_Mask 0x1F +#define I2C_AddressHigh_Mask 0xF9 +#define I2C_OwnAddress_Mask 0x0300 +#define I2C_StandardMode_Mask 0x7f +#define I2C_FastMode_Mask 0x80 +#define I2C_Event_Mask 0x3FFF + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : I2C_DeInit +* Description : Deinitializes the I2C peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void I2C_DeInit(void) +{ + /* Reset the I2C registers values*/ + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_I2C,ENABLE); + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_I2C,DISABLE); +} + +/******************************************************************************* +* Function Name : I2C_Init +* Description : Initializes the I2C peripheral according to the specified +* parameters in the I2C_Initstruct. +* Input : - I2C_InitStruct: pointer to a I2C_InitTypeDef structure that +* contains the configuration information for the specified I2C +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void I2C_Init(I2C_InitTypeDef* I2C_InitStruct) +{ + u8 ITEState = 0; + u16 Result = 0x0F; + u32 APBClock = 8000000; + MRCC_ClocksTypeDef MRCC_ClocksStatus; + + /* Get APBClock frequency value */ + MRCC_GetClocksStatus(&MRCC_ClocksStatus); + APBClock = MRCC_ClocksStatus.PCLK_Frequency; + /* Save ITE bit state */ + ITEState = I2C->CR & 0xFE; + /* Disable I2C peripheral to set FR[2:0] bits */ + I2C_Cmd(DISABLE); + /* Clear frequency FR[2:0] bits */ + I2C->OAR2 &= I2C_Frequency_Mask; + + /* Set frequency bits depending on APBClock value */ + if (APBClock < 10000000) + I2C->OAR2 &= 0x1F; + else if (APBClock < 16670000) + I2C->OAR2 |= 0x20; + else if (APBClock < 26670000) + I2C->OAR2 |= 0x40; + else if (APBClock < 40000000) + I2C->OAR2 |= 0x60; + else if (APBClock < 53330000) + I2C->OAR2 |= 0x80; + else if (APBClock < 66000000) + I2C->OAR2 |= 0xA0; + else if (APBClock < 80000000) + I2C->OAR2 |= 0xC0; + else if (APBClock < 100000000) + I2C->OAR2 |= 0xE0; + I2C_Cmd(ENABLE); + + /* Restore the ITE bit state */ + I2C->CR |= ITEState; + + /* Configure general call */ + if (I2C_InitStruct->I2C_GeneralCall == I2C_GeneralCall_Enable) + { + /* Enable general call */ + I2C->CR |= I2C_GeneralCall_Enable; + } + else + { + /* Disable general call */ + I2C->CR &= I2C_GeneralCall_Disable; + } + + /* Configure acknowledgement */ + if (I2C_InitStruct->I2C_Ack == I2C_Ack_Enable) + { + /* Enable acknowledgement */ + I2C->CR |= I2C_Ack_Enable; + } + else + { + /* Disable acknowledgement */ + I2C->CR &= I2C_Ack_Disable; + } + + /* Configure LSB own address */ + I2C->OAR1 = I2C_InitStruct->I2C_OwnAddress; + /* Clear MSB own address ADD[9:8] bits */ + I2C->OAR2 &= I2C_AddressHigh_Mask; + /* Set MSB own address value */ + I2C->OAR2 |= (I2C_InitStruct->I2C_OwnAddress & I2C_OwnAddress_Mask)>>7; + + /* Configure speed in standard mode */ + if (I2C_InitStruct->I2C_CLKSpeed <= 100000) + { + /* Standard mode speed calculate */ + Result = ((APBClock/I2C_InitStruct->I2C_CLKSpeed)-7)/2; + /* Set speed value and clear FM/SM bit for standard mode in LSB clock divider */ + I2C->CCR = Result & I2C_StandardMode_Mask; + } + /* Configure speed in fast mode */ + else if (I2C_InitStruct->I2C_CLKSpeed <= 400000) + { + /* Fast mode speed calculate */ + Result = ((APBClock/I2C_InitStruct->I2C_CLKSpeed)-9)/3; + /* Set speed value and set FM/SM bit for fast mode in LSB clock divider */ + I2C->CCR = Result | I2C_FastMode_Mask; + } + /* Set speed in MSB clock divider */ + I2C->ECCR = Result >>7; +} + +/******************************************************************************* +* Function Name : I2C_StructInit +* Description : Fills each I2C_InitStruct member with its default value. +* Input : - I2C_InitStruct: pointer to an I2C_InitTypeDef structure + which will be initialized. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct) +{ + /* Initialize the I2C_CLKSpeed member */ + I2C_InitStruct->I2C_CLKSpeed = 5000; + + /* Initialize the I2C_OwnAddress member */ + I2C_InitStruct->I2C_OwnAddress = 0x0; + + /* Initialize the I2C_GeneralCall member */ + I2C_InitStruct->I2C_GeneralCall = I2C_GeneralCall_Disable; + + /* Initialize the I2C_Ack member */ + I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; +} + +/******************************************************************************* +* Function Name : I2C_Cmd +* Description : Enables or disables the I2C peripheral. +* Input : - NewState: new state of the I2C peripheral. This parameter +* can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_Cmd(FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Enable the I2C peripheral by setting twice the PE bit on the CR register */ + I2C->CR |= I2C_PE_Set; + I2C->CR |= I2C_PE_Set; + } + else + { + /* Disable the I2C peripheral */ + I2C->CR &= I2C_PE_Reset; + } +} + +/******************************************************************************* +* Function Name : I2C_GenerateSTART +* Description : Generates I2C communication START condition. +* Input : - NewState: new state of the I2C START condition generation. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_GenerateSTART(FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Generate a START condition */ + I2C->CR |= I2C_Start_Enable; + } + else + { + /* Disable the START condition generation */ + I2C->CR &= I2C_Start_Disable; + } +} + +/******************************************************************************* +* Function Name : I2C_GenerateSTOP +* Description : Generates I2C communication STOP condition. +* Input : - NewState: new state of the I2C STOP condition generation. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_GenerateSTOP(FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Generate a SIOP condition */ + I2C->CR |= I2C_Stop_Enable; + } + else + { + /* Disable the STOP condition generation */ + I2C->CR &= I2C_Stop_Disable; + } +} + +/******************************************************************************* +* Function Name : I2C_AcknowledgeConfig +* Description : Enables or disables I2C acknowledge feature. +* Input : - NewState: new state of the I2C Acknowledgement. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_AcknowledgeConfig(FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Enable the acknowledgement */ + I2C->CR |= I2C_Ack_Enable; + } + else + { + /* Disable the acknowledgement */ + I2C->CR &= I2C_Ack_Disable; + } +} + +/******************************************************************************* +* Function Name : I2C_ITConfig +* Description : Enables or disables the I2C interrupt. +* Input : - NewState: new state of the I2C interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_ITConfig(FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Enable the I2C interrupt */ + I2C->CR |= I2C_IT_Enable; + } + else + { + /* Disable the I2C interrupt */ + I2C->CR &= I2C_IT_Disable; + } +} + +/******************************************************************************* +* Function Name : I2C_GetLastEvent +* Description : Gets the last I2C event that has occurred. +* Input : None +* Output : None +* Return : The Last happened Event. +*******************************************************************************/ +u16 I2C_GetLastEvent(void) +{ + u16 Flag1 = 0, Flag2 = 0, LastEvent = 0; + + Flag1 = I2C->SR1; + Flag2 = I2C->SR2; + Flag2 = Flag2<<8; + /* Get the last event value from I2C status register */ + LastEvent = (((Flag1 | (Flag2)) & I2C_Event_Mask)); + /* Return the last event */ + return LastEvent; +} + +/******************************************************************************* +* Function Name : I2C_CheckEvent +* Description : Checks whether the Last I2C Event is equal to the one passed +* as parameter. +* Input : - I2C_EVENT: specifies the event to be checked. This parameter +* can be one of the following values: +* - I2C_EVENT_SLAVE_ADDRESS_MATCHED +* - I2C_EVENT_SLAVE_BYTE_RECEIVED +* - I2C_EVENT_SLAVE_BYTE_TRANSMITTED +* - I2C_EVENT_SLAVE_ACK_FAILURE +* - I2C_EVENT_MASTER_MODE_SELECT +* - I2C_EVENT_MASTER_MODE_SELECTED +* - I2C_EVENT_MASTER_BYTE_RECEIVED +* - I2C_EVENT_MASTER_BYTE_TRANSMITTED +* - I2C_EVENT_MASTER_MODE_ADDRESS10 +* - I2C_EVENT_SLAVE_STOP_DETECTED +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Last event is equal to the I2C_Event +* - ERROR: Last event is different from the I2C_Event +*******************************************************************************/ +ErrorStatus I2C_CheckEvent(u16 I2C_EVENT) +{ + u16 LastEvent = I2C_GetLastEvent(); + + /* Check whether the last event is equal to I2C_EVENT */ + if (LastEvent == I2C_EVENT) + { + /* Return SUCCESS when last event is equal to I2C_EVENT */ + return SUCCESS; + } + else + { + /* Return ERROR when last event is different from I2C_EVENT */ + return ERROR; + } +} + +/******************************************************************************* +* Function Name : I2C_SendData +* Description : Sends a data byte. +* Input : - Data: indicates the byte to be transmitted. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_SendData(u8 Data) +{ + /* Write in the DR register the byte to be sent */ + I2C->DR = Data; +} + +/******************************************************************************* +* Function Name : I2C_ReceiveData +* Description : Reads the received byte. +* Input : None +* Output : None +* Return : The received byte +*******************************************************************************/ +u8 I2C_ReceiveData(void) +{ + /* Return from the DR register the received byte */ + return I2C->DR; +} + +/******************************************************************************* +* Function Name : I2C_Send7bitAddress +* Description : Transmits the address byte to select the slave device. +* Input : - Address: specifies the slave address which will be transmitted +* - Direction: specifies whether the I2C device will be a +* Transmitter or a Receiver. This parameter can be one of the +* following values +* - I2C_MODE_TRANSMITTER: Transmitter mode +* - I2C_MODE_RECEIVER: Receiver mode +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_Send7bitAddress(u8 Address, u8 Direction) +{ + /* Test on the direction to define the read/write bit */ + if (Direction == I2C_MODE_RECEIVER) + { + /* Set the address bit0 for read */ + Address |= I2C_ADD0_Set; + } + else + { + /* Reset the address bit0 for write */ + Address &= I2C_ADD0_Reset; + } + /* Send the address */ + I2C->DR = Address; +} + +/******************************************************************************* +* Function Name : I2C_ReadRegister +* Description : Reads the specified I2C register and returns its value. +* Input1 : - I2C_Register: specifies the register to read. +* This parameter can be one of the following values: +* - I2C_CR: CR register. +* - I2C_SR1: SR1 register. +* - I2C_SR2: SR2 register. +* - I2C_CCR: CCR register. +* - I2C_OAR1: OAR1 register. +* - I2C_OAR2: OAR2 register. +* - I2C_DR: DR register. +* - I2C_ECCR: ECCR register. +* Output : None +* Return : The value of the read register. +*******************************************************************************/ +u8 I2C_ReadRegister(u8 I2C_Register) +{ + /* Return the selected register value */ + return (*(u8 *)(I2C_BASE + I2C_Register)); +} + +/******************************************************************************* +* Function Name : I2C_GetFlagStatus +* Description : Checks whether the specified I2C flag is set or not. +* Input : - I2C_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - I2C_FLAG_SB: Start bit flag (Master mode) +* - I2C_FLAG_M_SL: Master/Slave flag +* - I2C_FLAG_ADSL: Address matched flag (Slave mode) +* - I2C_FLAG_BTF: Byte transfer finished flag +* - I2C_FLAG_BUSY: Bus busy flag +* - I2C_FLAG_TRA: Transmitter/Receiver flag +* - I2C_FLAG_ADD10: 10-bit addressing in Master mode flag +* - I2C_FLAG_EVF: Event flag +* - I2C_FLAG_GCAL: General call flag (slave mode) +* - I2C_FLAG_BERR: Bus error flag +* - I2C_FLAG_ARLO: Arbitration lost flag +* - I2C_FLAG_STOPF: Stop detection flag (slave mode) +* - I2C_FLAG_AF: Acknowledge failure flag +* - I2C_FLAG_ENDAD: End of address transmission flag +* - I2C_FLAG_ACK: Acknowledge enable flag +* Output : None +* Return : The NewState of the I2C_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus I2C_GetFlagStatus(u16 I2C_FLAG) +{ + u16 Flag1 = 0, Flag2 = 0, Flag3 = 0, Tmp = 0; + + Flag1 = I2C->SR1; + Flag2 = I2C->SR2; + Flag2 = Flag2<<8; + Flag3 = I2C->CR & 0x04; + + /* Get all the I2C flags in a unique register*/ + Tmp = (((Flag1 | (Flag2)) & I2C_Event_Mask) | (Flag3<<12)); + + /* Check the status of the specified I2C flag */ + if((Tmp & I2C_FLAG) != RESET) + { + /* Return SET if I2C_FLAG is set */ + return SET; + } + else + { + /* Return RESET if I2C_FLAG is reset */ + return RESET; + } +} + +/******************************************************************************* +* Function Name : I2C_ClearFlag +* Description : Clears the I2C’s pending flags +* Input : - I2C_FLAG: specifies the flag to clear. +* This parameter can be one of the following values: +* - I2C_FLAG_SB: Start bit flag +* - I2C_FLAG_M_SL: Master/Slave flag +* - I2C_FLAG_ADSL: Adress matched flag +* - I2C_FLAG_BTF: Byte transfer finished flag +* - I2C_FLAG_BUSY: Bus busy flag +* - I2C_FLAG_TRA: Transmitter/Receiver flag +* - I2C_FLAG_ADD10: 10-bit addressing in Master mode flag +* - I2C_FLAG_EVF: Event flag +* - I2C_FLAG_GCAL: General call flag +* - I2C_FLAG_BERR: Bus error flag +* - I2C_FLAG_ARLO: Arbitration lost flag +* - I2C_FLAG_STOPF: Stop detection flag +* - I2C_FLAG_AF: Acknowledge failure flag +* - I2C_FLAG_ENDAD: End of address transmission flag +* - I2C_FLAG_ACK: Acknowledge enable flag +* - parameter needed in the case that the flag to be cleared +* need a write in one register +* Output : None +* Return : None +*******************************************************************************/ +void I2C_ClearFlag(u16 I2C_FLAG, ...) +{ + u8 Tmp = (u8)*((u32 *) & I2C_FLAG + sizeof(I2C_FLAG)); + + /* flags that need a read of the SR2 register to be cleared */ + if ((I2C_FLAG == I2C_FLAG_ADD10) || (I2C_FLAG == I2C_FLAG_EVF) || + (I2C_FLAG == I2C_FLAG_STOPF) || (I2C_FLAG == I2C_FLAG_AF) || + (I2C_FLAG == I2C_FLAG_BERR) || (I2C_FLAG == I2C_FLAG_ARLO) || + (I2C_FLAG == I2C_FLAG_ENDAD)) + { + /* Read the SR2 register */ + (void)I2C->SR2; + + /* Two flags need a second step to be cleared */ + switch (I2C_FLAG) + { + case I2C_FLAG_ADD10: + /* Send the MSB 10bit address passed as second parameter */ + I2C->DR = Tmp; + break; + case I2C_FLAG_ENDAD: + /* Write to the I2C_CR register by setting PE bit */ + I2C->CR |= I2C_PE_Set; + break; + } + } + /* flags that need a read of the SR1 register to be cleared */ + else if (I2C_FLAG==I2C_FLAG_SB || I2C_FLAG==I2C_FLAG_ADSL || I2C_FLAG==I2C_FLAG_BTF || I2C_FLAG==I2C_FLAG_TRA) + { + /* Read the SR1 register */ + (void)I2C->SR1; + + /* three flags need a second step to be cleared */ + if (I2C_FLAG == I2C_FLAG_SB) + { + /* Send the address byte passed as second parameter */ + I2C->DR=Tmp; + } + else if (I2C_FLAG==I2C_FLAG_BTF || I2C_FLAG==I2C_FLAG_TRA) + { + /* return the received byte in the variable passed as second parameter */ + Tmp=I2C->DR; + } + } + /* flags that need to disable the I2C interface */ + else if ( I2C_FLAG==I2C_FLAG_M_SL || I2C_FLAG==I2C_FLAG_GCAL) + { + I2C_Cmd(DISABLE); + I2C_Cmd(ENABLE); + } +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_it.c b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_it.c new file mode 100644 index 000000000..b73503624 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_it.c @@ -0,0 +1,448 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_it.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : Main Interrupt Service Routines. +* This file can be used to describe all the exceptions +* subroutines that may occur within user application. +* When an interrupt happens, the software will branch +* automatically to the corresponding routine according +* to the interrupt vector loaded in the PC register. +* The following routines are all empty, user can write code +* for exceptions handlers and peripherals IRQ interrupts. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : Undefined_Handler +* Description : This function handles Undefined instruction exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void Undefined_Handler(void) +{ +} + +/******************************************************************************* +* Function Name : FIQ_Handler +* Description : This function handles FIQ exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void FIQ_Handler(void) +{ +} + +/******************************************************************************* +* Function Name : SWI_Handler +* Description : This function handles SW exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SWI_Handler(void) +{ +} + +/******************************************************************************* +* Function Name : Prefetch_Handler +* Description : This function handles preftetch abort exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void Prefetch_Handler(void) +{ +} + +/******************************************************************************* +* Function Name : Abort_Handler +* Description : This function handles data abort exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void Abort_Handler(void) +{ +} + +/******************************************************************************* +* Function Name : WAKUP_IRQHandler +* Description : This function handles External line 15(WAKUP) interrupt +* request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void WAKUP_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : TIM2_OC2_IRQHandler +* Description : This function handles TIM2 Output Compare 2 interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM2_OC2_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : TIM2_OC1_IRQHandler +* Description : This function handles TIM2 Output Compare 1 interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM2_OC1_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : TIM2_IC12_IRQHandler +* Description : This function handles TIM2 Input Capture 1 & 2 interrupt +* request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM2_IC12_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : TIM2_UP_IRQHandler +* Description : This function handles TIM2 Update interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM2_UP_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : TIM1_OC2_IRQHandler +* Description : This function handles TIM1 Output Compare 2 interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_OC2_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : TIM1_OC1_IRQHandler +* Description : This function handles TIM1 Output Compare 1 interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_OC1_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : TIM1_IC12_IRQHandler +* Description : This function handles TIM1 Input Capture 1 & 2 interrupt +* request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_IC12_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : TIM1_UP_IRQHandler +* Description : This function handles TIM1 Update interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_UP_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : TIM0_OC2_IRQHandler +* Description : This function handles TIM0 Output Compare 2 interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM0_OC2_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : TIM0_OC1_IRQHandler +* Description : This function handles TIM0 Output Compare 1 interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM0_OC1_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : TIM0_IC12_IRQHandler +* Description : This function handles TIM0 Input Capture 1 & 2 interrupt +* request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM0_IC12_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : TIM0_UP_IRQHandler +* Description : This function handles TIM0 Update interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM0_UP_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : PWM_OC123_IRQHandler +* Description : This function handles PWM Output Compare 1,2&3 interrupt +* request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void PWM_OC123_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : PWM_EM_IRQHandler +* Description : This function handles PWM Emergency interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void PWM_EM_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : PWM_UP_IRQHandler +* Description : This function handles PWM Update interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void PWM_UP_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : I2C_IRQHandler +* Description : This function handles I2C global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void I2C_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : SSP1_IRQHandler +* Description : This function handles SSP1 interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SSP1_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : SSP0_IRQHandler +* Description : This function handles SSP0 interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SSP0_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : UART2_IRQHandler +* Description : This function handles UART2 global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void UART2_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : UART1_IRQHandler +* Description : This function handles UART1 global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void UART1_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : UART0_IRQHandler +* Description : This function handles UART0 global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void UART0_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : CAN_IRQHandler +* Description : This function handles CAN global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void CAN_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : USBLP_IRQHandler +* Description : This function handles USB Low Priority event interrupt +* request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void USB_LP_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : USBHP_IRQHandler +* Description : This function handles USB High Priority event interrupt +* request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void USB_HP_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : ADC_IRQHandler +* Description : This function handles ADC global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void ADC_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : DMA_IRQHandler +* Description : This function handles DMA global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void DMA_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : EXTIT_IRQHandler +* Description : This function handles External lines 14 to 1 interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void EXTIT_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : MRCC_IRQHandler +* Description : This function handles MRCC interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : FLASHSMI_IRQHandler +* Description : This function handles Flash and SMI global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void FLASHSMI_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : RTC_IRQHandler +* Description : This function handles RTC global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RTC_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : TB_IRQHandler +* Description : This function handles TB global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TB_IRQHandler(void) +{ +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_lib.c b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_lib.c new file mode 100644 index 000000000..16c87f064 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_lib.c @@ -0,0 +1,178 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_lib.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all peripherals pointers initialization. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +#define EXT + +/* Includes ------------------------------------------------------------------*/ +#include "75x_lib.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +#ifdef DEBUG + +/******************************************************************************* +* Function Name : debug +* Description : This function initialize peripherals pointers. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void debug(void) +{ +/************************************* SMI ************************************/ +#ifdef _SMI + SMI = (SMI_TypeDef *) SMIR_BASE; +#endif /*_SMI */ + +/************************************* CFG ************************************/ +#ifdef _CFG + CFG = (CFG_TypeDef *) CFG_BASE; +#endif /*_CFG */ + +/************************************* MRCC ***********************************/ +#ifdef _MRCC + MRCC = (MRCC_TypeDef *) MRCC_BASE; +#endif /*_MRCC */ + +/************************************* ADC ************************************/ +#ifdef _ADC + ADC = (ADC_TypeDef *) ADC_BASE; +#endif /*_ADC */ + +/************************************* TB *************************************/ +#ifdef _TB + TB = (TB_TypeDef *) TB_BASE; +#endif /*_TB */ + +/************************************* TIM ************************************/ +#ifdef _TIM0 + TIM0 = (TIM_TypeDef *) TIM0_BASE; +#endif /*_TIM0 */ + +#ifdef _TIM1 + TIM1 = (TIM_TypeDef *) TIM1_BASE; +#endif /*_TIM1 */ + +#ifdef _TIM2 + TIM2 = (TIM_TypeDef *) TIM2_BASE; +#endif /*_TIM2 */ + +/************************************* PWM ************************************/ +#ifdef _PWM + PWM = (PWM_TypeDef *) PWM_BASE; +#endif /*_PWM */ + +/************************************* WDG ************************************/ +#ifdef _WDG + WDG = (WDG_TypeDef *) WDG_BASE; +#endif /*_WDG */ + +/************************************* SSP ************************************/ +#ifdef _SSP0 + SSP0 = (SSP_TypeDef *) SSP0_BASE; +#endif /*_SSP0 */ + +#ifdef _SSP1 + SSP1 = (SSP_TypeDef *) SSP1_BASE; +#endif /*_SSP1 */ + +/************************************* CAN ************************************/ +#ifdef _CAN + CAN = (CAN_TypeDef *) CAN_BASE; +#endif /*_CAN */ + +/************************************* I2C ************************************/ +#ifdef _I2C + I2C = (I2C_TypeDef *) I2C_BASE; +#endif /*_I2C */ + +/************************************* UART ***********************************/ +#ifdef _UART0 + UART0 = (UART_TypeDef *) UART0_BASE; +#endif /*_UART0 */ + +#ifdef _UART1 + UART1 = (UART_TypeDef *) UART1_BASE; +#endif /*_UART1 */ + +#ifdef _UART2 + UART2 = (UART_TypeDef *) UART2_BASE; +#endif /*_UART2 */ + +/************************************* GPIO ***********************************/ +#ifdef _GPIO0 + GPIO0 = (GPIO_TypeDef *) GPIO0_BASE; +#endif /*_GPIO0 */ + +#ifdef _GPIO1 + GPIO1 = (GPIO_TypeDef *) GPIO1_BASE; +#endif /*_GPIO1 */ + +#ifdef _GPIO2 + GPIO2 = (GPIO_TypeDef *) GPIO2_BASE; +#endif /*_GPIO2 */ + +#ifdef _GPIOREMAP + GPIOREMAP = (GPIOREMAP_TypeDef *) GPIOREMAP_BASE; +#endif /*_GPIOREMAP */ + +/************************************* DMA ************************************/ +#ifdef _DMA + DMA = (DMA_TypeDef *) DMA_BASE; +#endif /*_DMA */ + +#ifdef _DMA_Stream0 + DMA_Stream0 = (DMA_Stream_TypeDef *) DMA_Stream0_BASE; +#endif /*_DMA_Stream0 */ + +#ifdef _DMA_Stream1 + DMA_Stream1 = (DMA_Stream_TypeDef *) DMA_Stream1_BASE; +#endif /*_DMA_Stream1 */ + +#ifdef _DMA_Stream2 + DMA_Stream2 = (DMA_Stream_TypeDef *) DMA_Stream2_BASE; +#endif /*_DMA_Stream2 */ + +#ifdef _DMA_Stream3 + DMA_Stream3 = (DMA_Stream_TypeDef *) DMA_Stream3_BASE; +#endif /*_DMA_Stream3 */ + +/************************************* RTC ************************************/ +#ifdef _RTC + RTC = (RTC_TypeDef *) RTC_BASE; +#endif /*_RTC */ + +/************************************* EXTIT **********************************/ +#ifdef _EXTIT + EXTIT = (EXTIT_TypeDef *) EXTIT_BASE; +#endif /*_EXTIT */ + +/************************************* EIC ************************************/ +#ifdef _EIC + EIC = (EIC_TypeDef *) EIC_BASE; +#endif /*_EIC */ + +} + +#endif + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_mrcc.c b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_mrcc.c new file mode 100644 index 000000000..fadfb73c7 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_mrcc.c @@ -0,0 +1,1673 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_mrcc.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the MRCC software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_mrcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define MRCC_FLAG_Mask 0x1F /* MRCC Flag Mask */ + +/* MRCC_PWRCTRL mask bits */ +#define MRCC_LP_Set_Mask 0x00000001 +#define MRCC_LP_Reset_Mask 0xFFFFFFFE +#define MRCC_SWRESET_Mask 0x00000002 +#define MRCC_WFI_Mask 0x00000004 +#define MRCC_STANDBY_Mask 0x00000006 +#define MRCC_LPMC_Reset_Mask 0xFFFFFFF9 +#define MRCC_LPDONE_Reset_Mask 0xFFFFFF7F +#define MRCC_LPPARAM_Reset_Mask 0xFFFF1FFF +#define MRCC_WFIParam_Reset_Mask 0xFFFF1FEF +#define MRCC_CKRTCSEL_Set_Mask 0x03000000 +#define MRCC_CKRTCSEL_Reset_Mask 0xFCFFFFFF +#define MRCC_CKRTCOK_Mask 0x08000000 +#define MRCC_LPOSCEN_Mask 0x10000000 +#define MRCC_OSC32KEN_Mask 0x20000000 + +/* MRCC_CLKCTL mask bits */ +#define MRCC_PPRESC_Set_Mask 0x00000003 +#define MRCC_PPRESC_Reset_Mask 0xFFFFFFFC +#define MRCC_PPRESC2_Mask 0x00000004 +#define MRCC_HPRESC_Set_Mask 0x00000018 +#define MRCC_HPRESC_Reset_Mask 0xFFFFFFE7 +#define MRCC_MCOS_Reset_Mask 0xFFFFFF3F +#define MRCC_XTDIV2_Set_Mask 0x00008000 +#define MRCC_XTDIV2_Reset_Mask 0xFFFF7FFF +#define MRCC_OSC4MBYP_Set_Mask 0x00010000 +#define MRCC_OSC4MBYP_Reset_Mask 0xFFFEFFFF +#define MRCC_OSC4MOFF_Set_Mask 0x00020000 +#define MRCC_OSC4MOFF_Reset_Mask 0xFFFDFFFF +#define MRCC_NCKDF_Set_Mask 0x00040000 +#define MRCC_NCKDF_Reset_Mask 0xFFFBFFFF +#define MRCC_CKOSCSEL_Set_Mask 0x00200000 +#define MRCC_CKOSCSEL_Reset_Mask 0xFFDFFFFF +#define MRCC_CKUSBSEL_Mask 0x00400000 +#define MRCC_CKSEL_Set_Mask 0x00800000 +#define MRCC_CKSEL_Reset_Mask 0xFF7FFFFF +#define MRCC_CKSEL_CKOSCSEL_Mask 0x00A00000 +#define MRCC_PLLEN_Set_Mask 0x01000000 +#define MRCC_PLLEN_Reset_Mask 0xFEFFFFFF +#define MRCC_PLL2EN_Set_Mask 0x02000000 +#define MRCC_PLL2EN_Reset_Mask 0xFDFFFFFF +#define MRCC_MX_Set_Mask 0x18000000 +#define MRCC_MX_Reset_Mask 0xE7FFFFFF +#define MRCC_LOCK_Mask 0x80000000 +#define MRCC_PLLEN_LOCK_Mask 0x81000000 + +/* Typical Value of the OSC4M in Hz */ +#define OSC4M_Value 4000000 + +/* Typical Value of the OSC4M divided by 128 (used to clock the RTC) in Hz */ +#define OSC4M_Div128_Value 31250 + +/* Typical Value of the OS32K Oscillator Frequency in Hz */ +#define OSC32K_Value 32768 + +/* Typical Reset Value of the Internal LPOSC Oscillator Frequency in Hz */ +#define LPOSC_Value 245000 + +/* Typical Reset Value of the Internal FREEOSC Oscillator Frequency in Hz */ +#define FREEOSC_Value 5000000 + +/* Time out for OSC4M start up */ +#define OSC4MStartUp_TimeOut 0xFE + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static ErrorStatus SetCKSYS_FREEOSC(void); +static ErrorStatus SetCKSYS_OSC4M(u32 PLL_State); +static ErrorStatus SetCKSYS_OSC4MPLL(u32 PLL_Mul); +static ErrorStatus SetCKSYS_RTC(u32 PLL_State); +static void WriteLPBit(void); +static void WriteCKOSCSELBit(void); + +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : MRCC_DeInit +* Description : Deinitializes the MRCC peripheral registers to their default +* reset values. +* - Depending on the system clock state, some bits in MRCC_CLKCTL +* register can’t be reset. +* - The OSC32K, LPOSC and RTC clock selection configuration +* bits in MRCC_PWRCTRL register are not cleared by this +* function. To reset those bits, use the dedicated functions +* available within this driver. +* - The MRCC_RFSR, MRCC_BKP0 and MRCC_BKP1 registers are not +* reset by this function. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_DeInit(void) +{ + /* Try to clear NCKDF bit */ + MRCC->CLKCTL &= MRCC_NCKDF_Reset_Mask; + + if((MRCC->CLKCTL & MRCC_NCKDF_Set_Mask) != RESET) + {/* No clock detected on OSC4M */ + + /* Reset LOCKIE, LOCKIF, CKUSBSEL, NCKDIE, OSC4MOFF, OSC4MBYP, MCOS[1:0], + MCOP, HPRESC[1:0], PPRES[2:0] bits */ + MRCC->CLKCTL &= 0x9FB40000; + + if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET) + { + /* Clear CKOSCSEL bit --------------------------------------------------*/ + /* Execute CKOSCSEL bit writing sequence */ + WriteCKOSCSELBit(); + } + } + else + {/* Clock present on OSC4M */ + + if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET) + { + /* Reset CKSEL bit */ + MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask; + + /* Clear CKOSCSEL bit --------------------------------------------------*/ + /* Execute CKOSCSEL bit writing sequence */ + WriteCKOSCSELBit(); + } + + if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) == RESET) + { + /* Set CKSEL bit */ + MRCC->CLKCTL |= MRCC_CKSEL_Set_Mask; + } + + /* Disable PLL */ + MRCC->CLKCTL &= MRCC_PLLEN_Reset_Mask; + + /* Reset LOCKIE, LOCKIF, MX[1:0], CKUSBSEL, NCKDIE, MCOS[1:0], MCOP, + HPRESC[1:0], PPRES[2:0] bits */ + MRCC->CLKCTL &= 0x87B70000; + + /* Reset CKSEL bit */ + MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask; + + /* Reset OSC4MOFF and OSC4MBYP bits */ + MRCC->CLKCTL &= 0xFFFCFFFF; + } + + /* Reset RTCM, EN33V, LP_PARAM[15:13], WFI_FLASH_EN, LPMC_DBG and LPMC[1:0] bits */ + MRCC->PWRCTRL &= 0xFBFE1FE1; + + /* Reset PCLKEN register bits */ + MRCC->PCLKEN = 0x00; + + /* Reset PSWRES register bits */ + MRCC->PSWRES = 0x00; + + /* Clear NCKDF bit */ + MRCC->CLKCTL &= MRCC_NCKDF_Reset_Mask; +} + +/******************************************************************************* +* Function Name : MRCC_XTDIV2Config +* Description : Enables or disables the oscillator divider by 2. This function +* must not be used when the PLL is enabled. +* Input : - MRCC_XTDIV2: specifies the new state of the oscillator +* divider by 2. +* This parameter can be one of the following values: +* - MRCC_XTDIV2_Disable: oscillator divider by 2 disbaled +* - MRCC_XTDIV2_Enable: oscillator divider by 2 enbaled +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_XTDIV2Config(u32 MRCC_XTDIV2) +{ + if(MRCC_XTDIV2 == MRCC_XTDIV2_Enable) + { + MRCC->CLKCTL |= MRCC_XTDIV2_Enable; + } + else + { + MRCC->CLKCTL &= MRCC_XTDIV2_Disable; + } +} + +/******************************************************************************* +* Function Name : MRCC_CKSYSConfig +* Description : Configures the system clock (CK_SYS). +* Input : - MRCC_CKSYS: specifies the clock source used as system clock. +* This parameter can be one of the following values: +* - MRCC_CKSYS_FREEOSC +* - MRCC_CKSYS_OSC4M +* - MRCC_CKSYS_OSC4MPLL +* - MRCC_CKSYS_RTC (RTC clock source must be previously +* configured using MRCC_CKRTCConfig() function) +* : - MRCC_PLL: specifies the PLL configuration. +* This parameter can be one of the following values: +* - MRCC_PLL_Disabled: PLL disabled +* - MRCC_PLL_NoChange: No change on PLL configuration +* - MRCC_PLL_Mul_12: Multiplication by 12 +* - MRCC_PLL_Mul_14: Multiplication by 14 +* - MRCC_PLL_Mul_15: Multiplication by 15 +* - MRCC_PLL_Mul_16: Multiplication by 16 +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Clock configuration succeeded +* - ERROR: Clock configuration failed +*******************************************************************************/ +ErrorStatus MRCC_CKSYSConfig(u32 MRCC_CKSYS, u32 MRCC_PLL) +{ + ErrorStatus Status = ERROR; + + switch(MRCC_CKSYS) + { + case MRCC_CKSYS_FREEOSC: + if((MRCC_PLL == MRCC_PLL_Disabled) || (MRCC_PLL == MRCC_PLL_NoChange)) + { + Status = SetCKSYS_FREEOSC(); + } + break; + + case MRCC_CKSYS_OSC4M: + if((MRCC_PLL == MRCC_PLL_Disabled) || (MRCC_PLL == MRCC_PLL_NoChange)) + { + Status = SetCKSYS_OSC4M(MRCC_PLL); + } + break; + + case MRCC_CKSYS_OSC4MPLL: + if((MRCC_PLL == MRCC_PLL_Mul_12) || (MRCC_PLL == MRCC_PLL_Mul_14) || + (MRCC_PLL == MRCC_PLL_Mul_15) || (MRCC_PLL == MRCC_PLL_Mul_16)) + { + Status = SetCKSYS_OSC4MPLL(MRCC_PLL); + } + break; + + case MRCC_CKSYS_RTC: + if((MRCC_PLL == MRCC_PLL_Disabled) || (MRCC_PLL == MRCC_PLL_NoChange)) + { + Status = SetCKSYS_RTC(MRCC_PLL); + } + break; + + default: + Status = ERROR; + break; + } + return Status; +} + +/******************************************************************************* +* Function Name : MRCC_HCLKConfig +* Description : Configures the AHB clock (HCLK). +* Input : - MRCC_HCLK: defines the AHB clock. This clock is derived +* from the system clock(CK_SYS). +* This parameter can be one of the following values: +* - MRCC_CKSYS_Div1: AHB clock = CK_SYS +* - MRCC_CKSYS_Div2: AHB clock = CK_SYS/2 +* - MRCC_CKSYS_Div4: AHB clock = CK_SYS/4 +* - MRCC_CKSYS_Div8: AHB clock = CK_SYS/8 +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_HCLKConfig(u32 MRCC_HCLK) +{ + u32 Temp = 0; + + /* Clear HPRESC[1:0] bits */ + Temp = MRCC->CLKCTL & MRCC_HPRESC_Reset_Mask; + + /* Set HPRESC[1:0] bits according to MRCC_HCLK value */ + Temp |= MRCC_HCLK; + + /* Store the new value */ + MRCC->CLKCTL = Temp; +} + +/******************************************************************************* +* Function Name : MRCC_CKTIMConfig +* Description : Configures the TIM clock (CK_TIM). +* Input : - MRCC_CKTIM: defines the TIM clock. This clock is derived +* from the AHB clock(HCLK). +* This parameter can be one of the following values: +* - MRCC_HCLK_Div1: TIM clock = HCLK +* - MRCC_HCLK_Div2: TIM clock = HCLK/2 +* - MRCC_HCLK_Div4: TIM clock = HCLK/4 +* - MRCC_HCLK_Div8: TIM clock = HCLK/8 +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_CKTIMConfig(u32 MRCC_CKTIM) +{ + u32 Temp = 0; + + /* Clear PPRESC[1:0] bits */ + Temp = MRCC->CLKCTL & MRCC_PPRESC_Reset_Mask; + + /* Set PPRESC[1:0] bits according to MRCC_CKTIM value */ + Temp |= MRCC_CKTIM; + + /* Store the new value */ + MRCC->CLKCTL = Temp; +} + +/******************************************************************************* +* Function Name : MRCC_PCLKConfig +* Description : Configures the APB clock (PCLK). +* Input : - MRCC_PCLK: defines the APB clock. This clock is derived +* from the TIM clock(CK_TIM). +* This parameter can be one of the following values: +* - MRCC_CKTIM_Div1: APB clock = CKTIM +* - MRCC_CKTIM_Div2: APB clock = CKTIM/2 +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_PCLKConfig(u32 MRCC_PCLK) +{ + if(MRCC_PCLK == MRCC_CKTIM_Div2) + { + MRCC->CLKCTL |= MRCC_CKTIM_Div2; + } + else + { + MRCC->CLKCTL &= MRCC_CKTIM_Div1; + } +} + +/******************************************************************************* +* Function Name : MRCC_CKRTCConfig +* Description : Configures the RTC clock (CK_RTC). +* Input : - MRCC_CKRTC: specifies the clock source to be used as RTC +* clock. +* This parameter can be one of the following values: +* - MRCC_CKRTC_OSC4M_Div128 +* - MRCC_CKRTC_OSC32K (OSC32K must be previously enabled +* using MRCC_OSC32KConfig() function) +* - MRCC_CKRTC_LPOSC (LPOSC must be previously enabled +* using MRCC_LPOSCConfig() function) +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Clock configuration succeeded +* - ERROR: Clock configuration failed +*******************************************************************************/ +ErrorStatus MRCC_CKRTCConfig(u32 MRCC_CKRTC) +{ + u32 Tmp = 0; + + if(((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET) && + ((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET)) + { + /* CK_RTC used as CK_SYS clock source */ + return ERROR; + } + else + { + /* Clear CKRTCSEL[1:0] bits */ + Tmp = MRCC->PWRCTRL & MRCC_CKRTCSEL_Reset_Mask; + + /* Set CKRTCSEL[1:0] bits according to MRCC_CKRTC value */ + Tmp |= MRCC_CKRTC; + + /* Store the new value */ + MRCC->PWRCTRL = Tmp; + } + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : MRCC_CKUSBConfig +* Description : Configures the USB clock(CK_USB). +* Input : - MRCC_CKUSB: specifies the clock source to be used as USB +* clock. +* This parameter can be one of the following values: +* - MRCC_CKUSB_Internal(CK_PLL2 enabled) +* - MRCC_CKUSB_External(CK_PLL2 disabled) +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Clock configuration succeeded +* - ERROR: Clock configuration failed +*******************************************************************************/ +ErrorStatus MRCC_CKUSBConfig(u32 MRCC_CKUSB) +{ + if(MRCC_CKUSB == MRCC_CKUSB_External) + { + /* Disable CK_PLL2 */ + MRCC->CLKCTL &= MRCC_PLL2EN_Reset_Mask; + + /* External USB clock selected */ + MRCC->CLKCTL |= MRCC_CKUSB_External; + } + else + { + if((MRCC->CLKCTL & MRCC_PLLEN_LOCK_Mask) != RESET) + { /* PLL enabled and locked */ + + /* Enable CK_PLL2 */ + MRCC->CLKCTL |= MRCC_PLL2EN_Set_Mask; + + /* Internal USB clock selected */ + MRCC->CLKCTL &= MRCC_CKUSB_Internal; + } + else + { + /* PLL not enabled */ + return ERROR; + } + } + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : MRCC_ITConfig +* Description : Enables or disables the specified MRCC interrupts. +* Input : - MRCC_IT: specifies the MRCC interrupts sources to be +* enabled or disabled. This parameter can be any combination +* of the following values: +* - MRCC_IT_LOCK: PLL lock interrupt +* - MRCC_IT_NCKD: No Clock detected interrupt +* - NewState: new state of the MRCC interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_ITConfig(u32 MRCC_IT, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + MRCC->CLKCTL |= MRCC_IT; + } + else + { + MRCC->CLKCTL &= ~MRCC_IT; + } +} + +/******************************************************************************* +* Function Name : MRCC_PeripheralClockConfig +* Description : Enables or disables the specified peripheral clock. +* Input : - MRCC_Peripheral: specifies the peripheral to gates its +* clock. More than one peripheral can be selected using +* the “|” operator. +* - NewState: new state of the specified peripheral clock. +* This parameter can be one of the following values: +* - ENABLE: the selected peripheral clock is enabled +* - DISABLE: the selected peripheral clock is disabled +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_PeripheralClockConfig(u32 MRCC_Peripheral, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + MRCC->PCLKEN |= MRCC_Peripheral; + } + else + { + MRCC->PCLKEN &= ~MRCC_Peripheral; + } +} + +/******************************************************************************* +* Function Name : MRCC_PeripheralSWResetConfig +* Description : Forces or releases peripheral software reset. +* Input : - MRCC_Peripheral: specifies the peripheral to reset. More +* than one peripheral can be selected using the “|” operator. +* - NewState: new state of the specified peripheral software +* reset. This parameter can be one of the following values: +* - ENABLE: the selected peripheral is kept under reset +* - DISABLE: the selected peripheral exits from reset +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_PeripheralSWResetConfig(u32 MRCC_Peripheral, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + MRCC->PSWRES |= MRCC_Peripheral; + } + else + { + MRCC->PSWRES &= ~MRCC_Peripheral; + } +} + +/******************************************************************************* +* Function Name : MRCC_GetClocksStatus +* Description : Returns the status and frequencies of different on chip clocks. +* Don’t use this function when CK_SYS is clocked by an external +* clock source (OSC4M bypassed). +* Input : - MRCC_ClocksStatus: pointer to a MRCC_ClocksTypeDef structure +* which will hold the clocks information. +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_GetClocksStatus(MRCC_ClocksTypeDef* MRCC_ClocksStatus) +{ + u32 PLLMul = 0; + u32 Temp = 0; + u32 Presc = 0; + + /* Get the Status of PLL */ + if((MRCC->CLKCTL & MRCC_PLLEN_Set_Mask) == RESET) + { + MRCC_ClocksStatus->PLL_Status = OFF; + } + else + { + MRCC_ClocksStatus->PLL_Status = ON; + } + + /* Get the Status of OSC4M */ + if((MRCC->CLKCTL & MRCC_OSC4MOFF_Set_Mask) == RESET) + { + MRCC_ClocksStatus->OSC4M_Status = ON; + } + else + { + MRCC_ClocksStatus->OSC4M_Status = OFF; + } + + /* Get the Status of LPOSC */ + if((MRCC->PWRCTRL & MRCC_LPOSCEN_Mask) == RESET) + { + MRCC_ClocksStatus->LPOSC_Status = OFF; + } + else + { + MRCC_ClocksStatus->LPOSC_Status = ON; + } + + /* Get the Status of OSC32K */ + if((MRCC->PWRCTRL & MRCC_OSC32KEN_Mask) == RESET) + { + MRCC_ClocksStatus->OSC32K_Status = OFF; + } + else + { + MRCC_ClocksStatus->OSC32K_Status = ON; + } + +/* Get CKU_SB source ---------------------------------------------------------*/ + if((MRCC->CLKCTL & MRCC_CKUSBSEL_Mask) != RESET) + { + MRCC_ClocksStatus->CKUSB_Source = External; + } + else + { + if((MRCC->CLKCTL & MRCC_PLL2EN_Set_Mask) != RESET) + { + MRCC_ClocksStatus->CKUSB_Source = Internal; + + } + else + { + MRCC_ClocksStatus->CKUSB_Source = Disabled; + } + } + +/* Get CK_RTC source ---------------------------------------------------------*/ + Temp = MRCC->PWRCTRL & MRCC_CKRTCSEL_Set_Mask; + Temp = Temp >> 24; + + switch(Temp) + { + case 0x00: + MRCC_ClocksStatus->CKRTC_Source = Disabled; + break; + + case 0x01: + MRCC_ClocksStatus->CKRTC_Source = OSC4M_Div128; + break; + + case 0x02: + MRCC_ClocksStatus->CKRTC_Source = OSC32K; + break; + + case 0x03: + MRCC_ClocksStatus->CKRTC_Source = LPOSC; + break; + + default: + MRCC_ClocksStatus->CKRTC_Source = Disabled; + break; + } + +/* Get CK_SYS source ---------------------------------------------------------*/ + if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET) + {/* CK_OSC used as CK_SYS clock source */ + + if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET) + { /* CK_RTC used as CK_OSC clock source */ + MRCC_ClocksStatus->CKSYS_Source = CKRTC; + + if(MRCC_ClocksStatus->CKRTC_Source == OSC32K) + { + /* CK_SYS clock frequency */ + MRCC_ClocksStatus->CKSYS_Frequency = OSC32K_Value; + } + else if(MRCC_ClocksStatus->CKRTC_Source == LPOSC) + + { + /* CK_SYS clock frequency */ + MRCC_ClocksStatus->CKSYS_Frequency = LPOSC_Value; + } + else if(MRCC_ClocksStatus->CKRTC_Source == OSC4M_Div128) + + { + /* CK_SYS clock frequency */ + MRCC_ClocksStatus->CKSYS_Frequency = OSC4M_Div128_Value; + } + } + else + { /* OSC4M used as CK_OSC clock source */ + MRCC_ClocksStatus->CKSYS_Source = OSC4M; + + if((MRCC->CLKCTL & MRCC_XTDIV2_Set_Mask) != RESET) + { + /* CK_SYS clock frequency */ + MRCC_ClocksStatus->CKSYS_Frequency = Main_Oscillator >> 1; + } + else + { + /* CK_SYS clock frequency */ + MRCC_ClocksStatus->CKSYS_Frequency = Main_Oscillator; + } + } + } + else + {/* CK_PLL1 used as CK_SYS clock */ + + if(MRCC_ClocksStatus->PLL_Status == OFF) + { /* FREEOSC used as CK_PLL1 clock source */ + MRCC_ClocksStatus->CKSYS_Source = FREEOSC; + + /* CK_SYS clock frequency */ + MRCC_ClocksStatus->CKSYS_Frequency = FREEOSC_Value; + } + else + { /* OSC4M followed by PLL used as CK_PLL1 clock source */ + MRCC_ClocksStatus->CKSYS_Source = OSC4MPLL; + + /* Get PLL factor ------------------------------------------------------*/ + Temp = MRCC->CLKCTL & MRCC_MX_Set_Mask; + Temp = Temp >> 27; + + switch(Temp) + { + case 0x00: + PLLMul = 16; + break; + + case 0x01: + PLLMul = 15; + break; + + case 0x02: + PLLMul = 14; + break; + + case 0x03: + PLLMul = 12; + break; + + default: + PLLMul = 16; + break; + } + + /* CK_SYS clock frequency */ + MRCC_ClocksStatus->CKSYS_Frequency = OSC4M_Value * PLLMul; + } + } + +/* Compute HCLK, CKTIM and PCLK clocks frequencies ---------------------------*/ + /* Get HCLK prescaler */ + Presc = MRCC->CLKCTL & MRCC_HPRESC_Set_Mask; + Presc = Presc >> 3; + /* HCLK clock frequency */ + MRCC_ClocksStatus->HCLK_Frequency = MRCC_ClocksStatus->CKSYS_Frequency >> Presc; + + /* Get CK_TIM prescaler */ + Presc = MRCC->CLKCTL & MRCC_PPRESC_Set_Mask; + /* CK_TIM clock frequency */ + MRCC_ClocksStatus->CKTIM_Frequency = MRCC_ClocksStatus->HCLK_Frequency >> Presc; + + /* Get PCLK prescaler */ + Presc = MRCC->CLKCTL & MRCC_PPRESC2_Mask; + Presc = Presc >> 2; + /* PCLK clock frequency */ + MRCC_ClocksStatus->PCLK_Frequency = MRCC_ClocksStatus->CKTIM_Frequency >> Presc; +} + +/******************************************************************************* +* Function Name : MRCC_LPMC_DBGonfig +* Description : Enables or disables the Low Power Debug Mode. +* Input : - MRCC_LPDM: specifies the LPDM new state value. +* This parameter can be one of the following values: +* - MRCC_LPDM_Disable +* - MRCC_LPDM_Enable +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_LPMC_DBGConfig(u32 MRCC_LPDM) +{ + if(MRCC_LPDM == MRCC_LPDM_Enable) + { + MRCC->PWRCTRL |= MRCC_LPDM_Enable; + } + else + { + MRCC->PWRCTRL &= MRCC_LPDM_Disable; + } +} + +/******************************************************************************* +* Function Name : MRCC_EnterWFIMode +* Description : Enters WFI mode. +* If the Flash is used in Burst mode, it must be kept enabled +* in WFI mode(use MRCC_WFIParam_FLASHOn as parameter) +* Input : - MRCC_WFIParam: specifies the WFI mode control parameters. +* This parameter can be one of the following values: +* - MRCC_WFIParam_FLASHPowerDown(DMA not allowed during WFI) +* - MRCC_WFIParam_FLASHOn(DMA allowed during WFI) +* - MRCC_WFIParam_FLASHOff(DMA not allowed during WFI) +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_EnterWFIMode(u32 MRCC_WFIParam) +{ +/* Low Power mode configuration ----------------------------------------------*/ + /* Clear LPMC[1:0] bits */ + MRCC->PWRCTRL &= MRCC_LPMC_Reset_Mask; + + /* Select WFI mode */ + MRCC->PWRCTRL |= MRCC_WFI_Mask; + +/* Low Power mode control parameters configuration ---------------------------*/ + /* Clear LP_PARAM[15:13] and WFI_FLASH_EN bits */ + MRCC->PWRCTRL &= MRCC_WFIParam_Reset_Mask; + + if(MRCC_WFIParam != MRCC_WFIParam_FLASHPowerDown) + { + /* Set LP_PARAM[15:13] and WFI_FLASH_EN bits according to MRCC_WFIParam value */ + MRCC->PWRCTRL |= MRCC_WFIParam; + } + +/* Execute the Low Power bit writing sequence --------------------------------*/ + WriteLPBit(); +} + +/******************************************************************************* +* Function Name : MRCC_EnterSTOPMode +* Description : Enters STOP mode. +* Input : - MRCC_STOPParam: specifies the STOP mode control parameters. +* This parameter can be one of the following values: +* - MRCC_STOPParam_Default (OSC4M On, FLASH On, MVREG On) +* - MRCC_STOPParam_OSC4MOff +* - MRCC_STOPParam_FLASHOff +* - MRCC_STOPParam_MVREGOff +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_EnterSTOPMode(u32 MRCC_STOPParam) +{ +/* Low Power mode configuration ----------------------------------------------*/ + /* Clear LPMC[1:0] bits (STOP mode is selected) */ + MRCC->PWRCTRL &= MRCC_LPMC_Reset_Mask; + +/* Low Power mode control parameters configuration ---------------------------*/ + /* Clear LP_PARAM[15:13] bits */ + MRCC->PWRCTRL &= MRCC_LPPARAM_Reset_Mask; + + if(MRCC_STOPParam != MRCC_STOPParam_Default) + { + /* Set LP_PARAM[15:13] bits according to MRCC_STOPParam value */ + MRCC->PWRCTRL |= MRCC_STOPParam; + } + +/* Execute the Low Power bit writing sequence --------------------------------*/ + WriteLPBit(); +} + +/******************************************************************************* +* Function Name : MRCC_EnterSTANDBYMode +* Description : Enters STANDBY mode. +* Make sure that WKPF flag is cleared before using this function. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_EnterSTANDBYMode(void) +{ +/* Low Power mode configuration ----------------------------------------------*/ + /* Clear LPMC[1:0] bits */ + MRCC->PWRCTRL &= MRCC_LPMC_Reset_Mask; + + /* Select STANDBY mode */ + MRCC->PWRCTRL |= MRCC_STANDBY_Mask; + +/* Execute the Low Power bit writing sequence --------------------------------*/ + WriteLPBit(); +} + +/******************************************************************************* +* Function Name : MRCC_GenerateSWReset +* Description : Generates a system software reset. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_GenerateSWReset(void) +{ +/* Low Power mode configuration ----------------------------------------------*/ + /* Clear LPMC[1:0] bits */ + MRCC->PWRCTRL &= MRCC_LPMC_Reset_Mask; + + /* Select software reset */ + MRCC->PWRCTRL |= MRCC_SWRESET_Mask; + +/* Execute the Low Power bit writing sequence --------------------------------*/ + WriteLPBit(); +} + +/******************************************************************************* +* Function Name : MRCC_WriteBackupRegister +* Description : Writes user data to the specified backup register. +* Input : - MRCC_BKP: specifies the backup register. +* This parameter can be one of the following values: +* - MRCC_BKP0 +* - MRCC_BKP1 +* - Data: data to write. +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_WriteBackupRegister(MRCC_BKPReg MRCC_BKP, u32 Data) +{ + if(MRCC_BKP == MRCC_BKP0) + { + MRCC->BKP0 = Data; + } + else + { + MRCC->BKP1 = Data; + } +} + +/******************************************************************************* +* Function Name : MRCC_ReadBackupRegister +* Description : Reads data from the specified backup register. +* Input : - MRCC_BKP: specifies the backup register. +* This parameter can be one of the following values: +* - MRCC_BKP0 +* - MRCC_BKP1 +* Output : None +* Return : The content of the specified backup register. +*******************************************************************************/ +u32 MRCC_ReadBackupRegister(MRCC_BKPReg MRCC_BKP) +{ + if(MRCC_BKP == MRCC_BKP0) + { + return(MRCC->BKP0); + } + else + { + return(MRCC->BKP1); + } +} + +/******************************************************************************* +* Function Name : MRCC_IOVoltageRangeConfig +* Description : Configures the I/O pins voltage range. +* Input : - MRCC_IOVoltageRange: specifies the I/O pins voltage range. +* This parameter can be one of the following values: +* - MRCC_IOVoltageRange_5V +* - MRCC_IOVoltageRange_3V3 +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_IOVoltageRangeConfig(u32 MRCC_IOVoltageRange) +{ + if(MRCC_IOVoltageRange == MRCC_IOVoltageRange_3V3) + { + MRCC->PWRCTRL |= MRCC_IOVoltageRange_3V3; + } + else + { + MRCC->PWRCTRL &= MRCC_IOVoltageRange_5V; + } +} + +/******************************************************************************* +* Function Name : MRCC_MCOConfig +* Description : Selects the clock source to output on MCO pin (P0.1). +* To output the clock, the associated alternate function must +* be enabled in the I/O port controller. +* Input : - MRCC_MCO: specifies the clock source to output. +* This parameter can be one of the following values: +* - MRCC_MCO_HCLK +* - MRCC_MCO_PCLK +* - MRCC_MCO_OSC4M +* - MRCC_MCO_CKPLL2 +* - MRCC_MCOPrescaler: specifies if prescaler, divide by 1 or 2, +* is applied to this clock before outputting it to MCO pin. +* This parameter can be one of the following values: +* - MRCC_MCOPrescaler_1 +* - MRCC_MCOPrescaler_2 +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_MCOConfig(u32 MRCC_MCO, u32 MCO_MCOPrescaler) +{ + u32 Temp = 0; +/* MCO prescaler configuration -----------------------------------------------*/ + if(MCO_MCOPrescaler == MRCC_MCOPrescaler_2) + { + MRCC->CLKCTL |= MRCC_MCOPrescaler_2; + } + else + { + MRCC->CLKCTL &= MRCC_MCOPrescaler_1; + } + +/* MCO selection configuration -----------------------------------------------*/ + + /* Clear MCOS[1:0] bits */ + Temp = MRCC->CLKCTL & MRCC_MCOS_Reset_Mask; + + /* Set MCOS[1:0] bits according to MRCC_MCO value */ + Temp |= MRCC_MCO; + + /* Store the new value */ + MRCC->CLKCTL = Temp; +} + +/******************************************************************************* +* Function Name : MRCC_OSC4MConfig +* Description : Configures the 4MHz main oscillator (OSC4M). +* This function must be used when the CK_SYS is not clocked +* by the OSC4M and the PLL is not enabled. +* Input : - MRCC_OSC4M: specifies the new state of the OSC4M oscillator. +* This parameter can be one of the following values: +* - MRCC_OSC4M_Default: OSC4M enabled, bypass disabled +* - MRCC_OSC4M_Disable: OSC4M disabled +* - MRCC_OSC4M_Bypass: OSC4M bypassed +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Clock configuration succeeded +* - ERROR: Clock configuration failed +*******************************************************************************/ +ErrorStatus MRCC_OSC4MConfig(u32 MRCC_OSC4M) +{ + ErrorStatus Status = SUCCESS; + +/* If CK_SYS is driven by OSC4M or the PLL is enabled, exit ------------------*/ + if(((MRCC->CLKCTL & MRCC_CKSEL_CKOSCSEL_Mask) == MRCC_CKSEL_Set_Mask) || + (((MRCC->CLKCTL & MRCC_CKSEL_CKOSCSEL_Mask) == MRCC_CKSEL_CKOSCSEL_Mask) && + ((MRCC->PWRCTRL & MRCC_CKRTCSEL_Reset_Mask) != RESET))|| + ((MRCC->CLKCTL & MRCC_PLLEN_Set_Mask) != RESET)) + { + Status = ERROR; + } +/* Else configure the OSC4MOFF and OSC4MBYP bits -----------------------------*/ + else + { + switch(MRCC_OSC4M) + { + case MRCC_OSC4M_Default: + MRCC->CLKCTL &= MRCC_OSC4MOFF_Reset_Mask & MRCC_OSC4MBYP_Reset_Mask; + break; + + case MRCC_OSC4M_Disable: + MRCC->CLKCTL &= MRCC_OSC4MBYP_Reset_Mask; + MRCC->CLKCTL |= MRCC_OSC4MOFF_Set_Mask; + break; + + case MRCC_OSC4M_Bypass: + MRCC->CLKCTL &= MRCC_OSC4MOFF_Reset_Mask; + MRCC->CLKCTL |= MRCC_OSC4MBYP_Set_Mask; + break; + + default: + Status = ERROR; + break; + } + } + + return Status; +} + +/******************************************************************************* +* Function Name : MRCC_OSC32KConfig +* Description : Configures the OSC32K oscillator. +* This function must be used when the CK_SYS is not clocked by +* the CK_RTC. +* Input : - MRCC_OSC32K: specifies the new state of the OSC32K oscillator. +* This parameter can be one of the following values: +* - MRCC_OSC32K_Disable: OSC32K disabled +* - MRCC_OSC32K_Enable: OSC32K enabled +* - MRCC_OSC32KBypass: specifies if the OSC32K oscillator is +* bypassed or not. +* This parameter can be one of the following values: +* - MRCC_OSC32KBypass_Disable: OSC32K selected +* - MRCC_OSC32KBypass_Enable: OSC32K bypassed +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Clock configuration succeeded +* - ERROR: Clock configuration failed +*******************************************************************************/ +ErrorStatus MRCC_OSC32KConfig(u32 MRCC_OSC32K, u32 MRCC_OSC32KBypass) +{ +/* If CK_SYS is driven by CK_RTC, exit ---------------------------------------*/ + if(((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET) && + ((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET)) + { + return ERROR; + } +/* Else configure the OSC32KEN and OSC32KBYP bits ----------------------------*/ + else + { + /* Configure OSC32KEN bit */ + if(MRCC_OSC32K == MRCC_OSC32K_Enable) + { + MRCC->PWRCTRL |= MRCC_OSC32K_Enable; + } + else + { + MRCC->PWRCTRL &= MRCC_OSC32K_Disable; + } + + /* Configure OSC32KBYP bit */ + if(MRCC_OSC32KBypass == MRCC_OSC32KBypass_Enable) + { + MRCC->PWRCTRL |= MRCC_OSC32KBypass_Enable; + } + else + { + MRCC->PWRCTRL &= MRCC_OSC32KBypass_Disable; + } + + return SUCCESS; + } +} + +/******************************************************************************* +* Function Name : MRCC_LPOSCConfig +* Description : Enables or disables the LPOSC oscillator. +* This function must be used when the CK_SYS is not clocked by +* the CK_RTC. +* Input : - MRCC_LPOSC: specifies the new state of the LPOSC oscillator. +* This parameter can be one of the following values: +* - MRCC_LPOSC_Disable: LPOSC disabled +* - MRCC_LPOSC_Enable: LPOSC enabled +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Clock configuration succeeded +* - ERROR: Clock configuration failed +*******************************************************************************/ +ErrorStatus MRCC_LPOSCConfig(u32 MRCC_LPOSC) +{ +/* If CK_SYS is driven by CK_RTC or LPOSC is used as CK_RTC clock source, exit*/ + if((((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET) && + ((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET)) || + ((MRCC->PWRCTRL & MRCC_CKRTCSEL_Set_Mask) == MRCC_CKRTC_LPOSC)) + { + return ERROR; + } +/* Else configure the LPOSCEN bit --------------------------------------------*/ + else + { + if(MRCC_LPOSC == MRCC_LPOSC_Enable) + { + MRCC->PWRCTRL |= MRCC_LPOSC_Enable; + } + else + { + MRCC->PWRCTRL &= MRCC_LPOSC_Disable; + } + + return SUCCESS; + } +} + +/******************************************************************************* +* Function Name : MRCC_RTCMConfig +* Description : Enables or disables RTC clock measurement. +* Input : - MRCC_RTCM: specifies whether CK_RTC is connected to TB +* timer IC1 or not. +* This parameter can be one of the following values: +* - MRCC_RTCM_Disable: CK_RTC not connected to TB timer IC1 +* - MRCC_RTCM_Enable: CK_RTC connected to TB timer IC1 +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_RTCMConfig(u32 MRCC_RTCM) +{ + if(MRCC_RTCM == MRCC_RTCM_Enable) + { + MRCC->PWRCTRL |= MRCC_RTCM_Enable; + } + else + { + MRCC->PWRCTRL &= MRCC_RTCM_Disable; + } +} + +/******************************************************************************* +* Function Name : MRCC_SetBuilderCounter +* Description : Sets the builder counter value which defines the delay for +* the 4MHz main oscillator (OSC4M) clock to be stabilized. +* Input : - BuilderCounter: defines the delay for the OSC4M oscillator +* clock to be stabilized. +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_SetBuilderCounter(u8 BuilderCounter) +{ + *(u8 *) 0x60000026 = BuilderCounter; +} + +/******************************************************************************* +* Function Name : MRCC_GetCKSYSCounter +* Description : Gets the result of the delay applied to CK_SYS before +* starting the CPU. +* Input : None +* Output : None +* Return : SCOUNT value. +*******************************************************************************/ +u16 MRCC_GetCKSYSCounter(void) +{ + return((u16)(MRCC->RFSR & 0x0FFF)); +} + +/******************************************************************************* +* Function Name : MRCC_GetFlagStatus +* Description : Checks whether the specified MRCC flag is set or not. +* Input : - MRCC_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - MRCC_FLAG_LOCK: PLL Locked flag +* - MRCC_FLAG_LOCKIF: PLL Lock Interrupt status flag +* - MRCC_FLAG_CKSEL: CK_SYS source staus flag +* - MRCC_FLAG_CKOSCSEL: CK_OSC clock source staus flag +* - MRCC_FLAG_NCKD: No Clock Detected flag +* - MRCC_FLAG_SWR: Software Reset flag +* - MRCC_FLAG_WDGR: Watchdog Reset flag +* - MRCC_FLAG_EXTR: External Reset flag +* - MRCC_FLAG_WKP: Wake-Up flag +* - MRCC_FLAG_STDB: STANDBY flag +* - MRCC_FLAG_BCOUNT: Builder Counter Flag +* - MRCC_FLAG_OSC32KRDY: Oscillator 32K Ready +* - MRCC_FLAG_CKRTCOK: CK_RTC OK +* - MRCC_FLAG_LPDONE: Low Power Bit Sequence has been performed +* - MRCC_FLAG_LP: Low Power Mode Entry +* Output : None +* Return : The new state of MRCC_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus MRCC_GetFlagStatus(u8 MRCC_FLAG) +{ + u32 MRCCReg = 0, FlagPos = 0; + u32 StatusReg = 0; + + /* Get the MRCC register index */ + MRCCReg = MRCC_FLAG >> 5; + + /* Get the flag position */ + FlagPos = MRCC_FLAG & MRCC_FLAG_Mask; + + if(MRCCReg == 1) /* The flag to check is in CLKCTL register */ + { + StatusReg = MRCC->CLKCTL; + } + else if (MRCCReg == 2) /* The flag to check is in RFSR register */ + { + StatusReg = MRCC->RFSR; + } + else if(MRCCReg == 3) /* The flag to check is in PWRCTRL register */ + { + StatusReg = MRCC->PWRCTRL; + } + + if((StatusReg & (1 << FlagPos))!= RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : MRCC_ClearFlag +* Description : Clears the MRCC’s pending flags. +* Input : - MRCC_FLAG: specifies the flag to clear. +* This parameter can be one of the following values: +* - MRCC_FLAG_NCKD: No Clock Detected flag +* - MRCC_FLAG_SWR: Software Reset flag +* - MRCC_FLAG_WDGR: Watchdog Reset flag +* - MRCC_FLAG_EXTR: External Reset flag +* - MRCC_FLAG_WKP: Wake-Up flag +* - MRCC_FLAG_STDB: STANDBY flag +* - MRCC_FLAG_LPDONE: Low Power Bit Sequence has been performed +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_ClearFlag(u8 MRCC_FLAG) +{ + u32 MRCCReg = 0, FlagPos = 0; + + /* Get the MRCC register index */ + MRCCReg = MRCC_FLAG >> 5; + + /* Get the flag position */ + FlagPos = MRCC_FLAG & MRCC_FLAG_Mask; + + if(MRCCReg == 1) /* The flag to clear is in CLKCTL register */ + { + MRCC->CLKCTL &= ~(1 << FlagPos); + } + else if (MRCCReg == 2) /* The flag to clear is in RFSR register */ + { + MRCC->RFSR &= ~(1 << FlagPos); + } + else if(MRCCReg == 3) /* The flag to clear is in PWRCTRL register */ + { + MRCC->PWRCTRL &= ~(1 << FlagPos); + } +} + +/******************************************************************************* +* Function Name : MRCC_GetITStatus +* Description : Checks whether the specified MRCC interrupt has occurred or not. +* Input : - MRCC_IT: specifies the MRCC interrupt source to check. +* This parameter can be one of the following values: +* - MRCC_IT_LOCK: PLL lock interrupt +* - MRCC_IT_NCKD: No Clock detected interrupt +* Output : None +* Return : The new state of MRCC_IT (SET or RESET). +*******************************************************************************/ +ITStatus MRCC_GetITStatus(u32 MRCC_IT) +{ + /* Check the specified interrupt pending bit */ + if((MRCC->CLKCTL & (MRCC_IT >> 1)) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : MRCC_ClearITPendingBit +* Description : Clears the MRCC’s interrupt pending bits. +* Input : - MRCC_IT: specifies the interrupt pending bit to clear. +* This parameter can be any combination of the following +* values: +* - MRCC_IT_LOCK: PLL lock interrupt +* - MRCC_IT_NCKD: No Clock detected interrupt +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_ClearITPendingBit(u32 MRCC_IT) +{ + /* Clear the specified interrupt pending bit */ + MRCC->CLKCTL &= ~(MRCC_IT >> 1); +} + +/******************************************************************************* +* Function Name : MRCC_WaitForOSC4MStartUp +* Description : Waits for OSC4M start-up. +* Input : None +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: OSC4M oscillator is stable and ready to use +* - ERROR: no clock is detected on OSC4M +*******************************************************************************/ +ErrorStatus MRCC_WaitForOSC4MStartUp(void) +{ + u32 StartUpCounter = 0; + + do + { + /* Clear No Clock Detected flag */ + if(MRCC_GetFlagStatus(MRCC_FLAG_NCKD) != RESET) + { + MRCC_ClearFlag(MRCC_FLAG_NCKD); + } + + StartUpCounter++; + + }while((MRCC_GetFlagStatus(MRCC_FLAG_BCOUNT) == RESET)&& + (StartUpCounter != OSC4MStartUp_TimeOut)); + + if(MRCC_GetFlagStatus(MRCC_FLAG_BCOUNT) != RESET) + { + return SUCCESS; + } + else + { + return ERROR; + } +} + +/******************************************************************************* +* Function Name : SetCKSYS_FREEOSC +* Description : Selects FREEOSC as CK_SYS clock source. +* Input : None +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Clock configuration succeeded +* - ERROR: Clock configuration failed +*******************************************************************************/ +static ErrorStatus SetCKSYS_FREEOSC(void) +{ + /* Check if the PLL is enabled */ + if((MRCC->CLKCTL & MRCC_PLLEN_Set_Mask) != RESET) + { + if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) == RESET) + { /* CK_PLL1 used as Ck_SYS clock source*/ + + if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET) + {/* Check if CK_RTC source clock is present*/ + if((MRCC->PWRCTRL & MRCC_CKRTCSEL_Set_Mask) == RESET) + { + /* CK_RTC disabled*/ + return ERROR; + } + } + + /* Select CK_OSC as CK_SYS clock source */ + MRCC->CLKCTL |= MRCC_CKSEL_Set_Mask; + } + + /* Disable PLL */ + MRCC->CLKCTL &= MRCC_PLLEN_Reset_Mask; + } + + /* Select CK_PLL1 as CK_SYS clock source */ + MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask; + + if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) == RESET) + { + return SUCCESS; + } + else + { + return ERROR; + } +} + +/******************************************************************************* +* Function Name : SetCKSYS_OSC4M +* Description : Selects 4MHz main oscillator (OSC4M) as CK_SYS clock source. +* Input : PLL_State: specifies the PLL state. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Clock configuration succeeded +* - ERROR: Clock configuration failed +*******************************************************************************/ +static ErrorStatus SetCKSYS_OSC4M(u32 PLL_State) +{ +/* If OSC4M is not present, exit ---------------------------------------------*/ + if(((MRCC->CLKCTL & MRCC_NCKDF_Set_Mask) != RESET) || + ((MRCC->CLKCTL & MRCC_OSC4MOFF_Set_Mask) != RESET) ) + { + /* OSC4M disabled or OSC4M clock is not present*/ + return ERROR; + } + +/* Else configure CKSEL and CKOSCSEL bits ------------------------------------*/ + if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET) + { /* CK_RTC used as CK_OSC clock */ + + if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET) + { + /* Select CK_PLL1 as CK_SYS clock source */ + MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask; + } + + /* Clear CKOSCSEL bit ----------------------------------------------------*/ + /* Execute CKOSCSEL bit writing sequence */ + WriteCKOSCSELBit(); + + /* Check if CKOSCSEL is set to 0 */ + if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET) + { + return ERROR; + } + } + + /* Select CK_OSC as CK_SYS clock source */ + MRCC->CLKCTL |= MRCC_CKSEL_Set_Mask; + + if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET) + { + if(PLL_State == MRCC_PLL_Disabled) + { + /* Disable PLL */ + MRCC->CLKCTL &= MRCC_PLLEN_Reset_Mask; + } + + return SUCCESS; + } + else + { + return ERROR; + } +} + +/******************************************************************************* +* Function Name : SetCKSYS_OSC4MPLL +* Description : Selects 4MHz main oscillator (OSC4M) followed by PLL as +* CK_SYS clock source. +* Input : PLL_Mul: specifies the PLL factor. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Clock configuration succeeded +* - ERROR: Clock configuration failed +*******************************************************************************/ +static ErrorStatus SetCKSYS_OSC4MPLL(u32 PLL_Mul) +{ + /* Check if 4MHz main oscillator clock is present */ + if(((MRCC->CLKCTL & MRCC_NCKDF_Set_Mask) == RESET) && + ((MRCC->CLKCTL & MRCC_OSC4MOFF_Set_Mask) == RESET)) + { + if(((MRCC->CLKCTL & MRCC_PLLEN_Set_Mask) != RESET) && + ((MRCC->CLKCTL & MRCC_MX_Set_Mask) == PLL_Mul)) + { + /* Select CK_PLL1 as CK_SYS clock source */ + MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask; + + if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) == RESET) + { + return SUCCESS; + } + else + { + return ERROR; + } + } + else + { + /* If CK_RTC is selected as CK_OSC clock source */ + if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET) + { + if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET) + { + /* Clear CKSEL bit */ + MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask; + } + + /* Clear CKOSCSEL bit ------------------------------------------------*/ + /* Execute CKOSCSEL bit writing sequence */ + WriteCKOSCSELBit(); + + /* Check if CKOSCSEL is set to 0 */ + if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET) + { + return ERROR; + } + } + + /* Select CK_OSC as CK_SYS clock source */ + MRCC->CLKCTL |= MRCC_CKSEL_Set_Mask; + + /* Disable PLL */ + MRCC->CLKCTL &= MRCC_PLLEN_Reset_Mask; + + /* Configure PLL factor */ + if(PLL_Mul == MRCC_PLL_Mul_16) + { + MRCC->CLKCTL &= MRCC_MX_Reset_Mask; + } + else if((PLL_Mul == MRCC_PLL_Mul_15) || (PLL_Mul == MRCC_PLL_Mul_14) || + (PLL_Mul == MRCC_PLL_Mul_12)) + { + /* Clear MX[1:0] bits */ + MRCC->CLKCTL &= MRCC_MX_Reset_Mask; + /* Set MX[1:0] bits according to PLL_Mul value */ + MRCC->CLKCTL |= PLL_Mul; + } + + if(Main_Oscillator == 4000000) + {/* 4 MHz external Quartz oscillator used as main oscillator */ + /* Disable Oscillator Divider by 2 */ + MRCC->CLKCTL &= MRCC_XTDIV2_Reset_Mask; + } + else if(Main_Oscillator == 8000000) + {/* 8 MHz external Quartz oscillator used as main oscillator */ + /* Enable Oscillator Divider by 2 */ + MRCC->CLKCTL |= MRCC_XTDIV2_Set_Mask; + } + + /* Enable PLL */ + MRCC->CLKCTL |= MRCC_PLLEN_Set_Mask; + + /* Wait until the PLL is locked */ + while((MRCC->CLKCTL & MRCC_LOCK_Mask) == RESET) + { + /* If OSC4M clock disapear or the PLL is disabled, exit */ + if(((MRCC->CLKCTL & MRCC_NCKDF_Set_Mask) != RESET) || + ((MRCC->CLKCTL & MRCC_PLLEN_Set_Mask) == RESET)) + { + return ERROR; + } + } + + /* Select CK_PLL1 as CK_SYS clock source */ + MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask; + + if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) == RESET) + { + return SUCCESS; + } + else + { + return ERROR; + } + } + } + else + { + /* OSC4M disabled or OSC4M clock is not present*/ + return ERROR; + } +} + +/******************************************************************************* +* Function Name : SetCKSYS_RTC +* Description : Selects RTC clock (CK_RTC) as CK_SYS clock source. +* Input : PLL_State: specifies the PLL state. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Clock configuration succeeded +* - ERROR: Clock configuration failed +*******************************************************************************/ +static ErrorStatus SetCKSYS_RTC(u32 PLL_State) +{ + /* Check if CK_RTC clock is enabled and ready to use */ + if(((MRCC->PWRCTRL & MRCC_CKRTCSEL_Set_Mask) != RESET)|| + ((MRCC->CLKCTL & MRCC_CKRTCOK_Mask) == RESET)) + { +/* Configure CK_RTC as Ck_SYS clock source -----------------------------------*/ + if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) == RESET) + { + /* Select CK_PLL1 as CK_SYS clock source */ + MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask; + + /* Set CKOSCSEL bit ----------------------------------------------------*/ + /* Execute CKOSCSEL bit writing sequence */ + WriteCKOSCSELBit(); + + /* Check if CKOSCSEL is set to 1 */ + if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) == RESET) + { + return ERROR; + } + } + + /* Select CK_OSC as CK_SYS clock source */ + MRCC->CLKCTL |= MRCC_CKSEL_Set_Mask; + + if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET) + { + if(PLL_State == MRCC_PLL_Disabled) + { + /* Disable PLL */ + MRCC->CLKCTL &= MRCC_PLLEN_Reset_Mask; + } + + return SUCCESS; + } + else + { + return ERROR; + } + } + else + { + /* CK_RTC disabled */ + return ERROR; + } +} + +/******************************************************************************* +* Function Name : WriteLPBit +* Description : Executes the Low Power bit writing sequence. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +static void WriteLPBit(void) +{ + u32 Tmp = 0, Tmp1 = 0, Tmp2 = 0; + + /* Clear LP_DONE flag */ + MRCC->PWRCTRL &= MRCC_LPDONE_Reset_Mask; + + Tmp = MRCC->PWRCTRL; + Tmp1 = Tmp | MRCC_LP_Set_Mask; + Tmp2 = Tmp & MRCC_LP_Reset_Mask; + + /* Set LP bit */ + MRCC->PWRCTRL = Tmp1; + + /* Set LP bit */ + MRCC->PWRCTRL = Tmp1; + + /* Reset LP bit */ + MRCC->PWRCTRL = Tmp2; + + /* Set LP bit */ + MRCC->PWRCTRL = Tmp1; + + /* Read LP bit*/ + Tmp = MRCC->PWRCTRL; +} + +/******************************************************************************* +* Function Name : WriteCKOSCSELBit +* Description : Executes the CKOSCSEL bit writing sequence. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +static void WriteCKOSCSELBit(void) +{ + u32 Tmp = 0, Tmp1 = 0, Tmp2 = 0; + + Tmp = MRCC->CLKCTL; + Tmp1 = Tmp | MRCC_CKOSCSEL_Set_Mask; + Tmp2 = Tmp & MRCC_CKOSCSEL_Reset_Mask; + + /* Set CKOSCSEL bit */ + MRCC->CLKCTL = Tmp1; + + /* Set CKOSCSEL bit */ + MRCC->CLKCTL = Tmp1; + + /* Reset CKOSCSEL bit */ + MRCC->CLKCTL = Tmp2; + + /* Set CKOSCSEL bit */ + MRCC->CLKCTL = Tmp1; + + /* Read CKOSCSEL bit */ + Tmp = MRCC->CLKCTL; +} +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_pwm.c b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_pwm.c new file mode 100644 index 000000000..79c15aa5b --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_pwm.c @@ -0,0 +1,1153 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_pwm.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the PWM software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_pwm.h" +#include "75x_mrcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* PWM interrupt masks */ +#define PWM_IT_Clear_Mask 0x7FFF +#define PWM_IT_Enable_Mask 0xEFFF + +/* PWM_CR Masks bit */ +#define PWM_CounterMode_Mask 0xFF8F +#define PWM_DBASE_Mask 0x077F +#define PWM_MasterModeSelection_Mask 0xFC7F + +/* PWM Update flag selection Set/Reset value */ +#define PWM_UFS_Reset 0xFFFE +#define PWM_UFS_Set 0x0001 + +/* PWM Counter value */ +#define PWM_COUNTER_Reset 0x0002 +#define PWM_COUNTER_Start 0x0004 +#define PWM_COUNTER_Stop 0xFFFB + +/* PWM Debug Mode Set/Reset value */ +#define PWM_DBGC_Set 0x0400 +#define PWM_DBGC_Reset 0xFBFF + +/* PWM Output Compare Polarity Set/Reset value */ +#define PWM_OC1P_Set 0x0020 +#define PWM_OC1P_Reset 0xFFDF + +#define PWM_OC1NP_Set 0x0080 +#define PWM_OC1NP_Reset 0xFF7F + +#define PWM_OC2P_Set 0x2000 +#define PWM_OC2P_Reset 0xDFFF + +#define PWM_OC2NP_Set 0x8000 +#define PWM_OC2NP_Reset 0x7FFF + +#define PWM_OC3P_Set 0x0020 +#define PWM_OC3P_Reset 0xFFDF + +#define PWM_OC3NP_Set 0x0080 +#define PWM_OC3NP_Reset 0xFF7F + +/* PWM Output Compare control mode constant */ +#define PWM_OCControl_PWM 0x000C +#define PWM_OCControl_OCToggle 0x0006 +#define PWM_OCControl_OCInactive 0x0004 +#define PWM_OCControl_OCActive 0x0002 +#define PWM_OCControl_OCTiming 0x0000 + +/* PWM Output Compare mode Enable value */ +#define PWM_OC1_Enable 0x0010 +#define PWM_OC2_Enable 0x1000 +#define PWM_OC3_Enable 0x0010 + +#define PWM_OC1_Disable 0xFFEF +#define PWM_OC2_Disable 0xEFFF +#define PWM_OC3_Disable 0xFFEF + +#define PWM_OC1N_Enable 0x0040 +#define PWM_OC2N_Enable 0x4000 +#define PWM_OC3N_Enable 0x0040 + +#define PWM_OC1N_Disable 0xFFBF +#define PWM_OC2N_Disable 0xBFFF +#define PWM_OC3N_Disable 0xFFBF + +/* PWM Output Compare mode Mask value */ +#define PWM_OC1C_Mask 0xFFF1 +#define PWM_OC2C_Mask 0xF1FF +#define PWM_OC3C_Mask 0xFFF1 + +/* PWM Preload bit Set/Reset value */ +#define PWM_PLD1_Set 0x0001 +#define PWM_PLD2_Set 0x0100 +#define PWM_PLD3_Set 0x0001 + +/* PWM OCRM Set/Reset value */ +#define PWM_OCMR_Set 0x0080 +#define PWM_OCMR_Reset 0xFF7F + +/* PWM_DTR bit Masks value */ +#define PWM_DTR_Mask 0xFC00 +#define PWM_LOCK_Mask 0xF3FF + +/* PWM MOE Set value */ +#define PWM_MOE_Set 0x8000 +#define PWM_MOE_Reset 0x7FFF + +/* PWM OSSR bit Set/Reset value */ +#define PWM_OSSR_Set 0x4000 +#define PWM_OSSR_Reset 0xBFFF + +/* Reset Register Masks */ +#define PWM_Prescaler_Reset_Mask 0x0000 +#define PWM_Pulse1_Reset_Mask 0x0000 +#define PWM_Pulse2_Reset_Mask 0x0000 +#define PWM_Pulse3_Reset_Mask 0x0000 +#define PWM_Period_Reset_Mask 0xFFFF +#define PWM_RepetitionCounter_Reset_Mask 0x0000 +#define PWM_DeadTime_Reset_Mask 0x0000 + +/* Private function prototypes -----------------------------------------------*/ +static void OCM_ModuleConfig(PWM_InitTypeDef* PWM_InitStruct); + +/* Private functions ---------------------------------------------------------*/ + +/****************************************************************************** +* Function Name : PWM_DeInit +* Description : Deinitializes PWM peripheral registers to their default reset +* values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void PWM_DeInit(void) +{ + /* Enters and exits the PWM peripheral to and from reset */ + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_PWM,ENABLE); + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_PWM,DISABLE); +} + +/******************************************************************************* +* Function Name : PWM_Init +* Description : Initializes the PWM peripheral according to the specified +* parameters in the PWM_InitStruct . +* Input : PWM_InitStruct: pointer to a PWM_InitTypeDef structure that +* contains the configuration information for the PWM peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void PWM_Init(PWM_InitTypeDef* PWM_InitStruct) +{ + /* Sets the prescaler value */ + PWM->PSC = PWM_InitStruct->PWM_Prescaler; + + /* Selects the counter mode */ + PWM->CR &= PWM_CounterMode_Mask; + PWM->CR |= PWM_InitStruct->PWM_CounterMode; + + /* Sets the period value */ + PWM->ARR = PWM_InitStruct->PWM_Period; + + /* Sets the repetition counter */ + PWM->RCR &= PWM_RepetitionCounter_Reset_Mask; + PWM->RCR |= PWM_InitStruct->PWM_RepetitionCounter; + + /* Configures the PWM according to the PWM_InitTypeDef structure parameters */ + OCM_ModuleConfig(PWM_InitStruct); +} + +/******************************************************************************* +* Function Name : PWM_StructInit +* Description : Fills each PWM_InitStruct member with its default value. +* Input : PWM_InitStruct : pointer to a PWM_InitTypeDef structure which +* will be initialized. +* Output : None +* Return : None. +*******************************************************************************/ +void PWM_StructInit(PWM_InitTypeDef *PWM_InitStruct) +{ + /* Sets the default configuration */ + PWM_InitStruct->PWM_Mode = PWM_Mode_OCTiming; + PWM_InitStruct->PWM_Prescaler = PWM_Prescaler_Reset_Mask; + PWM_InitStruct->PWM_CounterMode = PWM_CounterMode_Up; + PWM_InitStruct->PWM_Period = PWM_Period_Reset_Mask; + PWM_InitStruct->PWM_Complementary = PWM_Complementary_Disable; + PWM_InitStruct->PWM_OCState = PWM_OCState_Disable; + PWM_InitStruct->PWM_OCNState = PWM_OCNState_Disable; + PWM_InitStruct->PWM_Channel = PWM_Channel_1; + PWM_InitStruct->PWM_Pulse1 = PWM_Pulse1_Reset_Mask; + PWM_InitStruct->PWM_Pulse2 = PWM_Pulse2_Reset_Mask; + PWM_InitStruct->PWM_Pulse3 = PWM_Pulse3_Reset_Mask; + PWM_InitStruct->PWM_Polarity1 = PWM_Polarity1_High; + PWM_InitStruct->PWM_Polarity2 = PWM_Polarity2_High; + PWM_InitStruct->PWM_Polarity3 = PWM_Polarity3_High; + PWM_InitStruct->PWM_Polarity1N = PWM_Polarity1N_High; + PWM_InitStruct->PWM_Polarity2N = PWM_Polarity2N_High; + PWM_InitStruct->PWM_Polarity3N = PWM_Polarity3N_High; + PWM_InitStruct->PWM_DTRAccess = PWM_DTRAccess_Disable; + PWM_InitStruct->PWM_DeadTime = PWM_DeadTime_Reset_Mask; + PWM_InitStruct->PWM_Emergency = PWM_Emergency_Disable; + PWM_InitStruct->PWM_LOCKLevel = PWM_LOCKLevel_OFF; + PWM_InitStruct->PWM_OSSIState = PWM_OSSIState_Disable; + PWM_InitStruct->PWM_RepetitionCounter = PWM_RepetitionCounter_Reset_Mask; +} + +/******************************************************************************* +* Function Name : PWM_Cmd +* Description : Enables or disables the PWM peripheral. +* Input : Newstate: new state of the PWM peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void PWM_Cmd(FunctionalState Newstate) +{ + if(Newstate == ENABLE) + { + PWM->CR |= PWM_COUNTER_Start; + } + else + { + PWM->CR &= PWM_COUNTER_Stop; + } +} + +/******************************************************************************* +* Function Name : PWM_CtrlPWMOutputs +* Description : Enables or disables PWM peripheral Main Outputs. +* Input : Newstate: new state of the PWM peripheral Main Outputs. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void PWM_CtrlPWMOutputs(FunctionalState Newstate) +{ + if(Newstate == ENABLE) + { + PWM->DTR |= PWM_MOE_Set; + } + else + { + PWM->DTR &= PWM_MOE_Reset; + } +} + +/******************************************************************************* +* Function Name : PWM_ITConfig +* Description : Enables or disables the PWM interrupts. +* Input : - PWM_IT: specifies the PWM interrupts sources to be enabled +* or disabled. +* This parameter can be any combination of the following values: +* - PWM_IT_OC1: PWM Output Compare 1 Interrupt source +* - PWM_IT_OC2: PWM Output Compare 2 Interrupt source +* - PWM_IT_OC3: PWM Output Compare 3 Interrupt source +* - PWM_IT_Update: PWM update Interrupt source +* - PWM_IT_Emergency: PWM Emergency interrupt source +* - PWM_IT_GlobalUpdate: PWM global update Interrupt +* source +* - Newstate: new state of PWM interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void PWM_ITConfig(u16 PWM_IT, FunctionalState Newstate) +{ + u16 PWM_IT_Enable = 0; + + PWM_IT_Enable = PWM_IT & PWM_IT_Enable_Mask; + + if(Newstate == ENABLE) + { + /* Update interrupt global source: overflow/undeflow, counter reset operation + or slave mode controller in reset mode */ + if ((PWM_IT & PWM_IT_GlobalUpdate) == PWM_IT_GlobalUpdate) + { + PWM->CR &= PWM_UFS_Reset; + } + /* Update interrupt source: counter overflow/underflow */ + else if ((PWM_IT & PWM_IT_Update) == PWM_IT_Update) + { + PWM->CR |= PWM_UFS_Set; + } + /* Select and enable the interrupts requests */ + PWM->RSR |= PWM_IT_Enable; + PWM->RER |= PWM_IT_Enable; + } + /* Disable the interrupts requests */ + else + { + PWM->RSR &= ~PWM_IT_Enable; + PWM->RER &= ~PWM_IT_Enable; + } +} + +/******************************************************************************* +* Function Name : PWM_DMAConfig +* Description : Configures the PWM’s DMA interface. +* Input : - PWM_DMASources: specifies the DMA Request sources. +* This parameter can be any combination of the following values: +* - PWM_DMASource_OC1: PWM Output Compare 1 DMA source +* - PWM_DMASource_OC2: PWM Output Compare 2 DMA source +* - PWM_DMASource_OC3: PWM Output Compare 3 DMA source +* - PWM_DMASource_Update: PWM Update DMA source +* - PWM_OCRMState: the state of output compare request mode. +* This parameter can be one of the following values: +* - PWM_OCRMState_Enable +* - PWM_OCRMState_Disable +* - PWM_DMABase:DMA Base address. +* This parameter can be one of the following values: +* PWM_DMABase_CR, PWM_DMABase_SCR, PWM_DMABase_OMR1, +* PWM_DMABase_OMR2, PWM_DMABase_RSR, PWM_DMABase_RER, +* PWM_DMABase_ISR, PWM_DMABase_CNT, PWM_DMABase_PSC, +* PWM_DMABase_RCR, PWM_DMABase_ARR, PWM_DMABase_OCR1, +* PWM_DMABase_OCR2, PWM_DMABase_OCR3 ,PWM_DMABase_DTR. +* Output : None +* Return : None +*******************************************************************************/ +void PWM_DMAConfig(u16 PWM_DMASources, u16 PWM_OCRMState, u16 PWM_DMABase) +{ + /* Select the DMA requests */ + PWM->RSR &= ~PWM_DMASources; + + /* Sets the OCRM state */ + if(PWM_OCRMState == PWM_OCRMState_Enable) + { + PWM->RSR |= PWM_OCMR_Set; + } + else + { + PWM->RSR &= PWM_OCMR_Reset; + } + + /* Sets the DMA Base address */ + PWM->CR &= PWM_DBASE_Mask; + PWM->CR |= PWM_DMABase; +} + +/******************************************************************************* +* Function Name : PWM_DMACmd +* Description : Enables or disables the PWM’s DMA interface. +* Input : - PWM_DMASources: specifies the DMA Request sources. +* This parameter can be any combination of the following values: +* - PWM_DMASource_OC1: PWM Output Compare 1 DMA source +* - PWM_DMASource_OC2: PWM Output Compare 2 DMA source +* - PWM_DMASource_OC3: PWM Output Compare 3 DMA source +* - PWM_DMASource_Update: PWM Update DMA source +* - Newstate: new state of the DMA Request sources. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void PWM_DMACmd(u16 PWM_DMASources, FunctionalState Newstate) +{ + if(Newstate == ENABLE) + { + PWM->RER |= PWM_DMASources; + } + else + { + PWM->RER &= ~PWM_DMASources; + } +} + +/******************************************************************************* +* Function Name : PWM_SetPrescaler +* Description : Sets the PWM prescaler value. +* Input : Prescaler: PWM prescaler new value. +* Output : None +* Return : None +*******************************************************************************/ +void PWM_SetPrescaler(u16 Prescaler) +{ + PWM->PSC = Prescaler; +} + +/******************************************************************************* +* Function Name : PWM_SetPeriod +* Description : Sets the PWM period value. +* Input : Period: PWM period new value. +* Output : None +* Return : None +*******************************************************************************/ +void PWM_SetPeriod(u16 Period) +{ + PWM->ARR = Period; +} + +/******************************************************************************* +* Function Name : PWM_SetPulse +* Description : Sets the PWM pulse value. +* Input : - PWM_Channel: specifies the PWM channel to be used. +* This parameter can be one of the following values: +* - PWM_Channel_1: PWM Channel 1 is used +* - PWM_Channel_2: PWM Channel 2 is used +* - PWM_Channel_3: PWM Channel 3 is used +* - PWM_Channel_ALL: PWM Channel 1, Channel 2 and 3 are used +* - Pulse: PWM pulse new value. +* Output : None +* Return : None +*******************************************************************************/ +void PWM_SetPulse(u16 PWM_Channel, u16 Pulse) +{ + /* Sets Channel 1 pulse value */ + if(PWM_Channel == PWM_Channel_1) + { + PWM->OCR1 = Pulse; + } + /* Sets Channel 2 pulse value */ + else if(PWM_Channel == PWM_Channel_2) + { + PWM->OCR2 = Pulse; + } + /* Sets Channel 3 pulse value */ + else if(PWM_Channel == PWM_Channel_3) + { + PWM->OCR3 = Pulse; + } + /* Sets Channel 1, Channel 2 and Channel 3 pulse values */ + else if(PWM_Channel == PWM_Channel_ALL) + { + PWM->OCR1 = Pulse; + PWM->OCR2 = Pulse; + PWM->OCR3 = Pulse; + } +} + +/******************************************************************************* +* Function Name : PWM_SetPulse1 +* Description : Sets the PWM Channel 1 pulse value. +* Input : - Pulse: PWM Channel 1 pulse new value. +* Output : None +* Return : None +*******************************************************************************/ +void PWM_SetPulse1(u16 Pulse) +{ + PWM->OCR1 = Pulse; +} + +/******************************************************************************* +* Function Name : PWM_SetPulse2 +* Description : Sets the PWM Channel 2 pulse value. +* Input : - Pulse: PWM Channel 2 pulse new value. +* Output : None +* Return : None +*******************************************************************************/ +void PWM_SetPulse2(u16 Pulse) +{ + PWM->OCR2 = Pulse; +} + +/******************************************************************************* +* Function Name : PWM_SetPulse3 +* Description : Sets the PWM Channel 3 pulse value. +* Input : - Pulse: PWM Channel 3 pulse new value. +* Output : None +* Return : None +*******************************************************************************/ +void PWM_SetPulse3(u16 Pulse) +{ + PWM->OCR3 = Pulse; +} + +/******************************************************************************* +* Function Name : PWM_DebugCmd +* Description : Enables or disables PWM peripheral Debug control. +* Input : Newstate: new state of the PWM Debug control. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void PWM_DebugCmd(FunctionalState Newstate) +{ + if(Newstate == ENABLE) + { + PWM->CR |= PWM_DBGC_Set; + } + else + { + PWM->CR &= PWM_DBGC_Reset; + } +} + +/******************************************************************************* +* Function Name : PWM_CounterModeConfig +* Description : Specifies the Counter Mode to be used. +* Input : PWM_CounterMode: specifies the Counter Mode to be used +* This parameter can be one of the following values: +* - PWM_CounterMode_Up: PWM Up Counting Mode +* - PWM_CounterMode_Down: PWM Down Counting Mode +* - PWM_CounterMode_CenterAligned1: PWM Center Aligned1 Mode +* - PWM_CounterMode_CenterAligned2: PWM Center Aligned2 Mode +* - PWM_CounterMode_CenterAligned3: PWM Center Aligned3 Mode +* Output : None +* Return : None +*******************************************************************************/ +void PWM_CounterModeConfig(u16 PWM_CounterMode) +{ + /* Counter mode configuration */ + PWM->CR &= PWM_CounterMode_Mask; + PWM->CR |= PWM_CounterMode; +} + +/******************************************************************************* +* Function Name : PWM_ForcedOCConfig +* Description : Forces the PWM output waveform to active or inactive level. +* Input : - PWM_Channel: specifies the PWM channel to be used. +* This parameter can be one of the following values: +* - PWM_Channel_1: PWM Channel 1 is used +* - PWM_Channel_2: PWM Channel 2 is used +* - PWM_Channel_3: PWM Channel 3 is used +* - PWM_Channel_ALL: PWM Channel 1, Channel 2 and 3 are used +* - PWM_ForcedAction: specifies the forced Action to be set to the +* output waveform. +* This parameter can be one of the following values: +* - PWM_ForcedAction_Active: Force active level on OCxREF +* - PWM_ForcedAction_InActive: Force inactive level on +* OCxREF +* Output : None +* Return : None +*******************************************************************************/ +void PWM_ForcedOCConfig(u16 PWM_Channel, u16 PWM_ForcedAction) +{ + /* Channel 1 Forced Output Compare mode configuration */ + if(PWM_Channel == PWM_Channel_1) + { + PWM->OMR1 &= PWM_OC1C_Mask; + PWM->OMR1 |= PWM_ForcedAction; + } + /* Channel 2 Forced Output Compare mode configuration */ + else + { + if(PWM_Channel == PWM_Channel_2) + { + PWM->OMR1 &= PWM_OC2C_Mask; + PWM->OMR1 |= (PWM_ForcedAction<<8); + } + else + { + /* Channel 3 Forced Output Compare mode configuration */ + if(PWM_Channel == PWM_Channel_3) + { + PWM->OMR2 &= PWM_OC3C_Mask; + PWM->OMR2 |= PWM_ForcedAction; + } + /* Channel 1, Channel 2 and Channel 3 Forced Output Compare mode + configuration */ + else + { + PWM->OMR1 &= PWM_OC1C_Mask; + PWM->OMR1 |= PWM_ForcedAction; + + PWM->OMR1 &= PWM_OC2C_Mask; + PWM->OMR1 |= (PWM_ForcedAction<<8); + + PWM->OMR2 &= PWM_OC3C_Mask; + PWM->OMR2 |= PWM_ForcedAction; + } + } + } +} + +/******************************************************************************* +* Function Name : PWM_SetDeadTime +* Description : Inserts dead time between the OCx and OCNx. +* Input : DeadTime: PWM Dead Time value. +* Output : None +* Return : None +*******************************************************************************/ +void PWM_SetDeadTime(u16 DeadTime) +{ + /* Sets the dead time value */ + PWM->DTR &= PWM_DTR_Mask; + PWM->DTR |= DeadTime; +} + +/******************************************************************************* +* Function Name : PWM_ResetCounter +* Description : Re-intializes the PWM counter and generates an update of the +* registers. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void PWM_ResetCounter(void) +{ + /* Resets the PWM counter */ + PWM->CR |= PWM_COUNTER_Reset; +} + +/******************************************************************************* +* Function Name : PWM_TRGOSelection +* Description : Sets the PWM Master Mode selection bits. +* Input : PWM_TRGOMode: specifies the TRGO source. +* This parameter can be one of the following values: +* - PWM_TRGOMode_Enable: The CNT_EN bit is used as TRGO +* - PWM_TRGOMode_Update: The Update event is used as TRGO +* - PWM_TRGOMode_Reset: The CNT_RST bit is used as TRGO +* - PWM_TRGOMode_OC: The OC1 signal is used as TRGO +* Output : None +* Return : None +*******************************************************************************/ +void PWM_TRGOSelection(u16 PWM_TRGOMode) +{ + /* Sets the synchronization action */ + PWM->CR &= PWM_MasterModeSelection_Mask; + PWM->CR |= PWM_TRGOMode; +} + +/******************************************************************************* +* Function Name : PWM_GetFlagStatus +* Description : Checks whether the specified PWM flag is set or not. +* Input : PWM_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - PWM_FLAG_OC1: Output Compare 1 Flag +* - PWM_FLAG_OC2: Output Compare 2 Flag +* - PWM_FLAG_OC3: Output Compare 3 Flag +* - PWM_FLAG_Update: PWM update Flag +* - PWM_FLAG_Emergency: PWM Emergency Flag +* Output : None +* Return : The new state of the PWM_FLAG(SET or RESET). +*******************************************************************************/ +FlagStatus PWM_GetFlagStatus(u16 PWM_FLAG) +{ + if((PWM->ISR & PWM_FLAG) != RESET ) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : PWM_ClearFlag +* Description : Clears the PWM’s pending flags. +* Input : PWM_FLAG: specifies the flag to clear. +* This parameter can be any combination of the following values: +* - PWM_FLAG_OC1: Output Compare 1 flag +* - PWM_FLAG_OC2: Output Compare 2 flag +* - PWM_FLAG_OC3: Output Compare 3 flag +* - PWM_FLAG_Update: PWM update flag +* - PWM_FLAG_Emergency: PWM Emergency flag +* Output : None +* Return : None +*******************************************************************************/ +void PWM_ClearFlag(u16 PWM_FLAG) +{ + /* Clears the flags */ + PWM->ISR &= ~PWM_FLAG; +} + +/******************************************************************************* +* Function Name : PWM_GetITStatus +* Description : Checks whether the PWM interrupt has occurred or not. +* Input : PWM_IT: specifies the PWM interrupt source to check. +* This parameter can be one of the following values: +* - PWM_IT_OC1: PWM Output Compare 1 Interrupt source +* - PWM_IT_OC2: PWM Output Compare 2 Interrupt source +* - PWM_IT_OC3: PWM Output Compare 3 Interrupt source +* - PWM_IT_Update: PWM update Interrupt source +* - PWM_IT_Emergency: PWM Emergency interrupt source +* - PWM_IT_GlobalUpdate: PWM global update Interrupt +* source +* Output : None +* Return : The new state of the PWM_IT(SET or RESET). +*******************************************************************************/ +ITStatus PWM_GetITStatus(u16 PWM_IT) +{ + u16 PWM_IT_Check = 0; + + /* Calculates the pending bits to be checked */ + PWM_IT_Check = PWM_IT & PWM_IT_Clear_Mask; + + if((PWM->ISR & PWM_IT_Check) != RESET ) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : PWM_ClearITPendingBit +* Description : Clears the PWM's interrupt pending bits. +* Input : PWM_IT: specifies the pending bit to clear. +* This parameter can be any combination of the following values: +* - PWM_IT_OC1: PWM Output Compare 1 Interrupt source +* - PWM_IT_OC2: PWM Output Compare 2 Interrupt source +* - PWM_IT_OC3: PWM Output Compare 3 Interrupt source +* - PWM_IT_Update: PWM update Interrupt source +* - PWM_IT_Emergency: PWM Emergency interrupt source +* - PWM_IT_GlobalUpdate: PWM global update Interrupt +* source +* Output : None +* Return : None +*******************************************************************************/ +void PWM_ClearITPendingBit(u16 PWM_IT) +{ + u16 PWM_IT_Clear = 0; + + /* Calculates the pending bits to be cleared */ + PWM_IT_Clear = PWM_IT & PWM_IT_Clear_Mask; + + /* Clears the pending bits */ + PWM->ISR &= ~PWM_IT_Clear; + +} + +/******************************************************************************* +* Function Name : OCM_ModuleConfig +* Description : Output Compare Module configuration. +* Input : PWM_InitStruct: pointer to a PWM_InitTypeDef structure that +* contains the configuration information for the PWM peripheral. +* Output : None +* Return : None +*******************************************************************************/ +static void OCM_ModuleConfig(PWM_InitTypeDef* PWM_InitStruct) +{ + u16 PWM_OCControl = 0x0000; + u16 DTR_REG = 0x0000; + + if(PWM_InitStruct->PWM_Mode == PWM_Mode_OCTiming) + { + PWM_OCControl = PWM_OCControl_OCTiming; + } + else + { + if(PWM_InitStruct->PWM_Mode == PWM_Mode_OCActive) + { + PWM_OCControl = PWM_OCControl_OCActive; + } + else + { + if(PWM_InitStruct->PWM_Mode == PWM_Mode_OCInactive) + { + PWM_OCControl = PWM_OCControl_OCInactive; + } + else + { + if(PWM_InitStruct->PWM_Mode == PWM_Mode_OCToggle) + { + PWM_OCControl = PWM_OCControl_OCToggle; + } + else + { + PWM_OCControl = PWM_OCControl_PWM; + + } + } + } + } + + /* Read DTR register */ + DTR_REG = PWM->DTR & 0x8000; + +/*Channel 1 Configuration-----------------------------------------------------*/ + if(PWM_InitStruct->PWM_Channel == PWM_Channel_1) + { + /* PWM Output Complementary Configuration */ + if(PWM_InitStruct->PWM_Complementary == PWM_Complementary_Enable) + { + /* Configures Channel 1 on Output Compare mode */ + PWM->OMR1 &= PWM_OC1C_Mask; + PWM->OMR1 |= PWM_OCControl|PWM_OC1_Enable|PWM_OC1N_Enable|PWM_PLD1_Set; + PWM->OCR1 = PWM_InitStruct->PWM_Pulse1; + + /* Sets the OC1 wave polarity */ + if(PWM_InitStruct->PWM_Polarity1 == PWM_Polarity1_Low) + { + PWM->OMR1 |= PWM_OC1P_Set; + } + else + { + PWM->OMR1 &= PWM_OC1P_Reset; + } + + /* Sets the OC1N wave polarity */ + if(PWM_InitStruct->PWM_Polarity1N == PWM_Polarity1N_Low) + { + PWM->OMR1 |= PWM_OC1NP_Set; + } + else + { + PWM->OMR1 &= PWM_OC1NP_Reset; + } + }/* End complementary case */ + /* Single PWM Output configuratuion */ + else + { + switch(PWM_InitStruct->PWM_OCState) + { + case PWM_OCState_Enable: + { + /* Configures Channel 1 on Output Compare mode */ + PWM->OMR1 &= PWM_OC1C_Mask; + PWM->OMR1 |= PWM_OCControl|PWM_OC1_Enable; + PWM->OMR1 |= PWM_PLD1_Set; + PWM->OCR1 = PWM_InitStruct->PWM_Pulse1; + + /* Sets the OC1 wave polarity */ + if(PWM_InitStruct->PWM_Polarity1 == PWM_Polarity1_Low) + { + PWM->OMR1 |= PWM_OC1P_Set; + } + else + { + PWM->OMR1 &= PWM_OC1P_Reset; + } + } + break; + case PWM_OCState_Disable: + { + /* OC1E = 0 and OSSR = 0 sets the polarity */ + PWM->OMR1 &= PWM_OC1_Disable; + DTR_REG &= PWM_OSSR_Reset; + } + break; + case PWM_OCState_OffState: + { + /* OC1E = 0 and OSSR = 1 and sets the polarity */ + PWM->OMR1 &= PWM_OC1_Disable; + DTR_REG |= PWM_OSSR_Set; + + /* Sets the OC1 wave polarity */ + if(PWM_InitStruct->PWM_Polarity1 == PWM_Polarity1_Low) + { + PWM->OMR1 |= PWM_OC1P_Set; + } + else + { + PWM->OMR1 &= PWM_OC1P_Reset; + } + } + break; + } + + switch(PWM_InitStruct->PWM_OCNState) + { + case PWM_OCNState_Enable: + { + /* Configures Channel 1N on Output Compare mode */ + PWM->OMR1 &= PWM_OC1C_Mask; + PWM->OMR1 |= PWM_OCControl |PWM_OC1N_Enable |PWM_PLD1_Set; + PWM->OCR1 = PWM_InitStruct->PWM_Pulse1; + + /* Sets the OC1N wave polarity */ + if(PWM_InitStruct->PWM_Polarity1N == PWM_Polarity1N_Low) + { + PWM->OMR1 |= PWM_OC1NP_Set; + } + else + { + PWM->OMR1 &= PWM_OC1NP_Reset; + } + } + break; + case PWM_OCNState_Disable: + { + /* OC1N = 0 OSSR = 0 */ + PWM->OMR1 &= PWM_OC1N_Disable; + DTR_REG &= PWM_OSSR_Reset; + } + break; + case PWM_OCNState_OffState: + { + /* OC1N = 0 OSSR = 1 and sets the polarity */ + PWM->OMR1 &= PWM_OC1N_Disable; + DTR_REG |= PWM_OSSR_Set; + + if(PWM_InitStruct->PWM_Polarity1N == PWM_Polarity1N_Low) + { + PWM->OMR1 |= PWM_OC1NP_Set; + } + else + { + PWM->OMR1 &= PWM_OC1NP_Reset; + } + } + break; + } + } /* End not complementary case */ + }/* end channel 1 */ + +/*Channel 2 Configuration-----------------------------------------------------*/ + if(PWM_InitStruct->PWM_Channel == PWM_Channel_2) + { + /* PWM Output Complementary Configuration */ + if(PWM_InitStruct->PWM_Complementary == PWM_Complementary_Enable) + { + /* Configures Channel 2 on Output Compare mode */ + PWM->OMR1 &= PWM_OC2C_Mask; + PWM->OMR1 |= (PWM_OCControl<<8)|PWM_OC2_Enable|PWM_OC2N_Enable|PWM_PLD2_Set; + PWM->OCR2 = PWM_InitStruct->PWM_Pulse2; + + /* Set the OC2 wave polarity */ + if(PWM_InitStruct->PWM_Polarity2 == PWM_Polarity2_Low) + { + PWM->OMR1 |= PWM_OC2P_Set; + } + else + { + PWM->OMR1 &= PWM_OC2P_Reset; + } + + /* Sets the OC2N wave polarity */ + if(PWM_InitStruct->PWM_Polarity2N == PWM_Polarity2N_Low) + { + PWM->OMR1 |= PWM_OC2NP_Set; + } + else + { + PWM->OMR1 &= PWM_OC2NP_Reset; + } + + }/* End complentary case */ + else + /* Single PWM Output configuratuion */ + { + switch(PWM_InitStruct->PWM_OCState) + { + case PWM_OCState_Enable: + { + /* Configures Channel 2 on Output Compare mode */ + PWM->OMR1 &= PWM_OC2C_Mask; + PWM->OMR1 |= (PWM_OCControl<<8)|PWM_OC2_Enable|PWM_PLD2_Set; + PWM->OCR2 = PWM_InitStruct->PWM_Pulse2; + + /* Sets the OC2 wave polarity */ + if(PWM_InitStruct->PWM_Polarity2 == PWM_Polarity2_Low) + { + PWM->OMR1 |= PWM_OC2P_Set; + } + else + { + PWM->OMR1 &= PWM_OC2P_Reset; + } + } + break; + case PWM_OCState_Disable: + { + /* OC2E = 0 and OSSR = 0 */ + PWM->OMR1 &= PWM_OC2_Disable; + DTR_REG &= PWM_OSSR_Reset; + } + break; + case PWM_OCState_OffState: + { + /* OC2E = 0 and OSSR = 1 sets the polarity */ + PWM->OMR1 &= PWM_OC2_Disable; + DTR_REG |= PWM_OSSR_Set; + + /* Sets the OC2 wave polarity */ + if(PWM_InitStruct->PWM_Polarity2 == PWM_Polarity2_Low) + { + PWM->OMR1 |= PWM_OC2P_Set; + } + else + { + PWM->OMR1 &= PWM_OC2P_Reset; + } + } + break; + } + switch(PWM_InitStruct->PWM_OCNState) + { + case PWM_OCNState_Enable: + { + /* Configures Channel 2N on Output Compare mode */ + PWM->OMR1 &= PWM_OC2C_Mask; + PWM->OMR1 |= (PWM_OCControl<<8)|PWM_OC2N_Enable|PWM_PLD2_Set; + PWM->OCR2 = PWM_InitStruct->PWM_Pulse2; + + /* Sets the OC2 wave polarity */ + if(PWM_InitStruct->PWM_Polarity2N == PWM_Polarity2N_Low) + { + PWM->OMR1 |= PWM_OC2NP_Set; + } + else + { + PWM->OMR1 &= PWM_OC2NP_Reset; + } + } + break; + case PWM_OCNState_Disable: + { + /* OC2N = 0 OSSR = 0 */ + PWM->OMR1 &= PWM_OC2N_Disable; + DTR_REG &= PWM_OSSR_Reset; + } + break; + case PWM_OCNState_OffState: + { + /* OC2N = 0 OSSR = 1 and sets the polarity */ + PWM->OMR1 &= PWM_OC2N_Disable; + DTR_REG |= PWM_OSSR_Set; + + if(PWM_InitStruct->PWM_Polarity2N == PWM_Polarity2N_Low) + { + PWM->OMR1 |= PWM_OC2NP_Set; + } + else + { + PWM->OMR1 &= PWM_OC2NP_Reset; + } + } + break; + } + } /* End not complementary case */ + }/* end channel 2 */ + +/*Channel 3 Configuration-----------------------------------------------------*/ + if(PWM_InitStruct->PWM_Channel == PWM_Channel_3) + { + /* PWM Output Complementary Configuration */ + if(PWM_InitStruct->PWM_Complementary == PWM_Complementary_Enable) + { + /* Configures Channel 3 on Output Compare mode */ + PWM->OMR2 &= PWM_OC3C_Mask; + PWM->OMR2 |= PWM_OCControl|PWM_OC3_Enable|PWM_OC3N_Enable|PWM_PLD3_Set; + PWM->OCR3 = PWM_InitStruct->PWM_Pulse3; + + /* Sets the OC3 wave polarity */ + if(PWM_InitStruct->PWM_Polarity3 == PWM_Polarity3_Low) + { + PWM->OMR2 |= PWM_OC3P_Set; + } + else + { + PWM->OMR2 &= PWM_OC3P_Reset; + } + + /* Sets the OC3N wave polarity */ + if(PWM_InitStruct->PWM_Polarity3N == PWM_Polarity3N_Low) + { + PWM->OMR2 |= PWM_OC3NP_Set; + } + else + { + PWM->OMR2 &= PWM_OC3NP_Reset; + } + }/* End complementary case */ + else + /* Single PWM Output configuratuion */ + { + switch(PWM_InitStruct->PWM_OCState) + { + case PWM_OCState_Enable: + { + /* Configures Channel 3 on Output Compare mode */ + PWM->OMR2 &= PWM_OC3C_Mask; + PWM->OMR2 |= PWM_OCControl|PWM_OC3_Enable|PWM_PLD3_Set; + PWM->OCR3 = PWM_InitStruct->PWM_Pulse3; + + /* Sets the OCC wave polarity */ + if(PWM_InitStruct->PWM_Polarity3 == PWM_Polarity3_Low) + { + PWM->OMR2 |= PWM_OC3P_Set; + } + else + { + PWM->OMR2 &= PWM_OC3P_Reset; + } + } + break; + case PWM_OCState_Disable: + { + /* OC3E = 0 and OSSR = 0 */ + PWM->OMR2 &= PWM_OC3_Disable; + DTR_REG &= PWM_OSSR_Reset; + } + break; + case PWM_OCState_OffState: + { + /* OC3E = 0 and OSSR = 1 sets the polarity */ + PWM->OMR2 &= PWM_OC3_Disable; + DTR_REG |= PWM_OSSR_Set; + + if(PWM_InitStruct->PWM_Polarity3 == PWM_Polarity3_Low) + { + PWM->OMR2 |= PWM_OC3P_Set; + } + else + { + PWM->OMR2 &= PWM_OC3P_Reset; + } + } + break; + } + + switch(PWM_InitStruct->PWM_OCNState) + { + case PWM_OCNState_Enable: + { + /* Configures Channel 3N on Output Compare mode */ + PWM->OMR2 &= PWM_OC3C_Mask; + PWM->OMR2 |= PWM_OCControl |PWM_OC3N_Enable|PWM_PLD3_Set; + PWM->OCR3 = PWM_InitStruct->PWM_Pulse3; + + /* Sets the OC3 wave polarity */ + if(PWM_InitStruct->PWM_Polarity3N == PWM_Polarity3N_Low) + { + PWM->OMR2 |= PWM_OC3NP_Set; + } + else + { + PWM->OMR2 &= PWM_OC3NP_Reset; + } + } + break; + case PWM_OCNState_Disable: + { + /* OC3N = 0 OSSR = 0 */ + PWM->OMR2 &= PWM_OC3N_Disable; + DTR_REG &= PWM_OSSR_Reset; + } + break; + case PWM_OCNState_OffState: + { + /* OC3N = 0 OSSR = 1 and sets the polarity */ + PWM->OMR2 &= PWM_OC3N_Disable; + DTR_REG |= PWM_OSSR_Set; + + if(PWM_InitStruct->PWM_Polarity3N == PWM_Polarity3N_Low) + { + PWM->OMR2 |= PWM_OC3NP_Set; + } + else + { + PWM->OMR2 &= PWM_OC3NP_Reset; + } + } + break; + } + } /* End not complementary case */ + }/* end channel 3 */ + + if(PWM_InitStruct->PWM_DTRAccess == PWM_DTRAccess_Enable) + { + DTR_REG |= PWM_InitStruct->PWM_LOCKLevel | PWM_InitStruct->PWM_Emergency | + PWM_InitStruct->PWM_DeadTime | PWM_InitStruct->PWM_OSSIState; + PWM->DTR = DTR_REG; + } +} +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_rtc.c b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_rtc.c new file mode 100644 index 000000000..ab6da500b --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_rtc.c @@ -0,0 +1,326 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_rtc.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the RTC software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_rtc.h" +#include "75x_mrcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define RTC_CNF_Enable_Mask 0x0010 /* Configuration Flag Enable Mask */ +#define RTC_CNF_Disable_Mask 0xFFEF /* Configuration Flag Disable Mask */ +#define RTC_LSB_Mask 0x0000FFFF /* RTC LSB Mask */ +#define RTC_MSB_Mask 0xFFFF0000 /* RTC MSB Mask */ +#define RTC_Prescaler_MSB_Mask 0x000F0000 /* RTC Prescaler MSB Mask */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/******************************************************************************* +* Function Name : RTC_DeInit +* Description : Deinitializes the RTC peripheral registers to their +* default reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RTC_DeInit(void) +{ + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_RTC,ENABLE); + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_RTC,DISABLE); +} + +/******************************************************************************* +* Function Name : RTC_ITConfig +* Description : Enables or disables the specified RTC interrupts. +* Input : - RTC_IT: specifies the RTC interrupts sources to be enabled +* or disabled. +* This parameter can be a combination of one or more of the +* following values: +* - RTC_IT_Overflow: Overflow interrupt +* - RTC_IT_Alarm: Alarm interrupt +* - RTC_IT_Second: Second interrupt +* - NewState: new state of the specified RTC interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void RTC_ITConfig(u16 RTC_IT, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + RTC->CRH |= RTC_IT; + } + else + { + RTC->CRH &= ~RTC_IT; + } +} + +/******************************************************************************* +* Function Name : RTC_EnterConfigMode +* Description : Enters the RTC configuration mode. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RTC_EnterConfigMode(void) +{ + /* Set the CNF flag to enter in the Configuration Mode */ + RTC->CRL |= RTC_CNF_Enable_Mask; +} + +/******************************************************************************* +* Function Name : RTC_ExitConfigMode +* Description : Exits from the RTC configuration mode. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RTC_ExitConfigMode(void) +{ + /* Reset the CNF flag to exit from the Configuration Mode */ + RTC->CRL &= RTC_CNF_Disable_Mask; +} + +/******************************************************************************* +* Function Name : RTC_GetCounter +* Description : Gets the RTC counter value. +* Input : None +* Output : None +* Return : RTC counter value. +*******************************************************************************/ +u32 RTC_GetCounter(void) +{ + u16 Tmp = 0; + Tmp = RTC->CNTL; + + return (((u32)RTC->CNTH << 16 ) |Tmp) ; +} + +/******************************************************************************* +* Function Name : RTC_SetCounter +* Description : Sets the RTC counter value. +* Input : RTC counter new value. +* Output : None +* Return : None +*******************************************************************************/ +void RTC_SetCounter(u32 CounterValue) +{ + RTC_EnterConfigMode(); + +/* COUNTER Config ------------------------------------------------------------*/ + /* Set RTC COUNTER MSB word */ + RTC->CNTH =(CounterValue & RTC_MSB_Mask) >> 16; + /* Set RTC COUNTER LSB word */ + RTC->CNTL =(CounterValue & RTC_LSB_Mask); + + RTC_ExitConfigMode(); +} + +/******************************************************************************* +* Function Name : RTC_SetPrescaler +* Description : Sets the RTC prescaler value. +* Input : RTC prescaler new value. +* Output : None +* Return : None +*******************************************************************************/ +void RTC_SetPrescaler(u32 PrescalerValue) +{ + RTC_EnterConfigMode(); + +/* PRESCALER Config ----------------------------------------------------------*/ + /* Set RTC PRESCALER MSB word */ + RTC->PRLH = (PrescalerValue & RTC_Prescaler_MSB_Mask) >> 16; + /* Set RTC PRESCALER LSB word */ + RTC->PRLL = (PrescalerValue & RTC_LSB_Mask); + + RTC_ExitConfigMode(); +} + +/******************************************************************************* +* Function Name : RTC_GetPrescaler +* Description : Gets the RTC prescaler value. +* Input : None +* Output : None +* Return : RTC prescaler value. +*******************************************************************************/ +u32 RTC_GetPrescaler(void) +{ + u16 Tmp = 0; + Tmp = RTC->PRLL; + + return (((u32)(RTC->PRLH & 0x000F) << 16 ) | Tmp); +} + +/******************************************************************************* +* Function Name : RTC_SetAlarm +* Description : Sets the RTC alarm value. +* Input : RTC alarm new value. +* Output : None +* Return : None +*******************************************************************************/ +void RTC_SetAlarm(u32 AlarmValue) +{ + RTC_EnterConfigMode(); + +/* ALARM Config --------------------------------------------------------------*/ + /* Set the ALARM MSB word */ + RTC->ALRH = (AlarmValue & RTC_MSB_Mask) >> 16; + /* Set the ALARM LSB word */ + RTC->ALRL = (AlarmValue & RTC_LSB_Mask); + + RTC_ExitConfigMode(); +} + +/******************************************************************************* +* Function Name : RTC_GetDivider +* Description : Gets the RTC divider value. +* Input : None +* Output : None +* Return : RTC Divider value. +*******************************************************************************/ +u32 RTC_GetDivider(void) +{ + u16 Tmp = 0; + Tmp = RTC->DIVL ; + return (((u32)(RTC->DIVH & 0x000F) << 16 ) | Tmp); +} + +/******************************************************************************* +* Function Name : RTC_WaitForLastTask +* Description : Waits until last write operation on RTC registers has finished. +* This function must be called before any write to RTC registers. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RTC_WaitForLastTask(void) +{ + /* Loop until RTOFF flag is set */ + while ((RTC->CRL & RTC_FLAG_RTOFF) == RESET); +} + +/******************************************************************************* +* Function Name : RTC_WaitForSynchro +* Description : Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL) +* are synchronized with RTC APB clock. +* This function must be called before any read operation after +* an APB reset or an APB clock stop. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RTC_WaitForSynchro(void) +{ + /* Clear RSF flag */ + RTC->CRL &= ~RTC_FLAG_RSF; + + /* Loop until RSF flag is set */ + while((RTC->CRL & RTC_FLAG_RSF)== RESET); +} + +/******************************************************************************* +* Function Name : RTC_GetFlagStatus +* Description : Checks whether the specified RTC flag is set or not. +* Input : RTC_FLAG: specifies the flag to check. +* This parameter can be one the following values: +* - RTC_FLAG_RTOFF: RTC Operation OFF flag +* - RTC_FLAG_RSF: Registers Synchronized flag +* - RTC_FLAG_Overflow: Overflow interrupt flag +* - RTC_FLAG_Alarm: Alarm interrupt flag +* - RTC_FLAG_Second: Second interrupt flag +* Output : None +* Return : The new state of RTC_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus RTC_GetFlagStatus(u16 RTC_FLAG) +{ + if((RTC->CRL & RTC_FLAG) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : RTC_ClearFlag +* Description : Clears the RTC’s pending flags. +* Input : RTC_FLAG: specifies the flag to clear. +* This parameter can be a combination of one or more of +* the following values: +* - RTC_FLAG_RSF: Registers Synchronized flag. This flag +* is cleared only after an APB reset or an APB Clock stop. +* - RTC_FLAG_Overflow: Overflow interrupt flag +* - RTC_FLAG_Alarm: Alarm interrupt flag +* - RTC_FLAG_Second: Second interrupt flag +* Output : None +* Return : None +*******************************************************************************/ +void RTC_ClearFlag(u16 RTC_FLAG) +{ + /* Clear the coressponding RTC flag */ + RTC->CRL &= ~RTC_FLAG; +} + +/******************************************************************************* +* Function Name : RTC_GetITStatus +* Description : Checks whether the specified RTC interrupt has occured or not. +* Input : RTC_IT: specifies the RTC interrupts sources to check. +* This parameter can be a combination of one or more of +* the following values: +* - RTC_IT_Overflow: Overflow interrupt +* - RTC_IT_Alarm: Alarm interrupt +* - RTC_IT_Second: Second interrupt +* Output : None +* Return : The new state of the RTC_IT (SET or RESET). +*******************************************************************************/ +ITStatus RTC_GetITStatus(u16 RTC_IT) +{ + if(((RTC->CRH & RTC_IT) != RESET)&& ((RTC->CRL & RTC_IT) != RESET)) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : RTC_ClearITPendingBit +* Description : Clears the RTC’s interrupt pending bits. +* Input : RTC_IT: specifies the interrupt pending bit to clear. +* This parameter can be any combination of one or more of +* the following values: +* - RTC_IT_Overflow: Overflow interrupt +* - RTC_IT_Alarm: Alarm interrupt +* - RTC_IT_Second: Second interrupt +* Output : None +* Return : None +*******************************************************************************/ +void RTC_ClearITPendingBit(u16 RTC_IT) +{ + /* Clear the coressponding RTC pending bit */ + RTC->CRL &= ~RTC_IT; +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_smi.c b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_smi.c new file mode 100644 index 000000000..9af53a9e8 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_smi.c @@ -0,0 +1,551 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_smi.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the SMI software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_smi.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* SMI_CR1 mask bits */ +#define SMI_HOLDPRESCTCS_RESET_Mask 0xFF00800F +#define SMI_Prescaler_MaxValue 0x7F +#define SMI_DeselectTime_MaxValue 0x0F +#define SMI_ClockHold_Mask 0x00 +#define SMI_Prescaler_Mask 0x02 +#define SMI_DeselectTime_Mask 0x5 + +/* SMI_CR2 mask bits */ +#define SMI_BS_RESET_Mask 0xFFFFCFFF +#define SMI_BS_Bank1_Mask 0x00001000 +#define SMI_BS_Bank2_Mask 0x00002000 +#define SMI_BS_Bank3_Mask 0x00003000 +#define SMI_WEN_Mask 0x00000800 +#define SMI_RSR_Mask 0x00000400 +#define SMI_SEND_Mask 0x00000080 +#define SMI_TRARECLENGTH_RESET_Mask 0xFFFFFF88 + +/* SMI_SR mask bits */ +#define SMI_STATUSREGISTER_Mask 0xFF + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : SMI_DeInit +* Description : Deinitializes the SMI peripheral registers to their default +* reset values. This function must not be used when booting +* from the SMI external memory. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SMI_DeInit(void) +{ + SMI->CR1 = 0x00000250; + SMI->CR2 = 0x00; + SMI->SR &= 0xFFFFF0FF; + SMI->TR = 0x00; +} + +/******************************************************************************* +* Function Name : SMI_Init +* Description : Initializes the SMI peripheral according to the specified +* parameters in the SMI_InitStruct. +* Input : - SMI_InitStruct: pointer to a SMI_InitTypeDef structure that +* contains the configuration information for the specified +* SMI peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void SMI_Init(SMI_InitTypeDef* SMI_InitStruct) +{ + u32 Temp = 0; + + /* Clear HOLD[7:0], PRESC[6:0] and TCS[3:0] bits */ + Temp = SMI->CR1 & SMI_HOLDPRESCTCS_RESET_Mask; + + /* Set HOLD[7:0] bits according to SMI_ClockHold value */ + Temp |= SMI_InitStruct->SMI_ClockHold << 16; + + if(SMI_InitStruct->SMI_Prescaler <= SMI_Prescaler_MaxValue) + { + /* Set PRESC[6:0] bits according to SMI_Prescaler value */ + Temp |= SMI_InitStruct->SMI_Prescaler << 8; + } + + if(SMI_InitStruct->SMI_DeselectTime <= SMI_DeselectTime_MaxValue) + { + /* Set TCS[3:0] bits according to SMI_DeselectTime value */ + Temp |= SMI_InitStruct->SMI_DeselectTime << 4; + } + + /* Store the new value */ + SMI->CR1 = Temp; +} + +/******************************************************************************* +* Function Name : SMI_StructInit +* Description : Fills each SMI_InitStruct member with its reset value. +* Input : - SMI_InitStruct: pointer to a SMI_InitTypeDef structure which +* will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void SMI_StructInit(SMI_InitTypeDef* SMI_InitStruct) +{ + /* SMI_CK is sent continuously */ + SMI_InitStruct->SMI_ClockHold = SMI_ClockHold_Mask; + + /* SMI_CK = HCLK/2 */ + SMI_InitStruct->SMI_Prescaler = SMI_Prescaler_Mask; + + /* Deselect Time set to 6*SMI_CK periods */ + SMI_InitStruct->SMI_DeselectTime = SMI_DeselectTime_Mask; +} + +/******************************************************************************* +* Function Name : SMI_ModeConfig +* Description : Selects the SMI mode: hardware or software. +* Input : - SMI_Mode: specifies the SMI mode. +* This parameter can be one of the following values: +* - SMI_Mode_HW: SMI in hardware mode +* - SMI_Mode_SW: SMI in software mode +* Output : None +* Return : None +*******************************************************************************/ +void SMI_ModeConfig(u32 SMI_Mode) +{ + if(SMI_Mode == SMI_Mode_SW) + { + SMI->CR1 |= SMI_Mode_SW; + } + else + { + SMI->CR1 &= SMI_Mode_HW; + } +} + +/******************************************************************************* +* Function Name : SMI_TxRxLengthConfig +* Description : Configures the number of bytes to be transmitted and received +* to/from external memory. This function is used in Software +* mode only. +* Input : - SMI_TxLength: specifies the number of bytes to be transmitted +* to external memory. +* This parameter can be one of the following values: +* - SMI_TxLength_0Bytes: No bytes transmitted +* - SMI_TxLength_1Byte: 1 byte transmitted +* - SMI_TxLength_2Bytes: 2 bytes transmitted +* - SMI_TxLength_3Bytes: 3 bytes transmitted +* - SMI_TxLength_4Bytes: 4 bytes transmitted +* - SMI_RxLength: specifies the number of bytes to be received +* from external memory. +* This parameter can be one of the following values: +* - SMI_RxLength_0Bytes: No bytes received +* - SMI_RxLength_1Byte: 1 byte received +* - SMI_RxLength_2Bytes: 2 bytes received +* - SMI_RxLength_3Bytes: 3 bytes received +* - SMI_RxLength_4Bytes: 4 bytes received +* Output : None +* Return : None +*******************************************************************************/ +void SMI_TxRxLengthConfig(u32 SMI_TxLength, u32 SMI_RxLength) +{ + u32 Temp = 0; + + /* Clear TRA_LENGTH[2:0] and REC_LENGTH[2:0] bits */ + Temp = SMI->CR2 & SMI_TRARECLENGTH_RESET_Mask; + + /* Set TRA_LENGTH[2:0] and REC_LENGTH[2:0] bits according to function parameters */ + Temp |= SMI_TxLength | SMI_RxLength; + + /* Store the new value */ + SMI->CR2 = Temp; +} + +/******************************************************************************* +* Function Name : SMI_BankCmd +* Description : Enables or disables the specified memory Bank. +* Input : - SMI_Bank: specifies the memory Bank to be enabled or disabled. +* This parameter can be any combination of the following values: +* - SMI_Bank_0 +* - SMI_Bank_1 +* - SMI_Bank_2 +* - SMI_Bank_3 +* - NewState: new state of the specified memory Bank. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SMI_BankCmd(u32 SMI_Bank, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + SMI->CR1 |= SMI_Bank; + } + else + { + SMI->CR1 &= ~SMI_Bank; + } +} + +/******************************************************************************* +* Function Name : SMI_ITConfig +* Description : Enables or disables the specified SMI interrupts. +* Input : - SMI_IT: specifies the SMI interrupts sources to be +* enabled or disabled. This parameter can be any combination +* of the following values: +* - SMI_IT_WC : Write Complete Interrupt +* - SMI_IT_TF : Transfer Finished Interrupt +* - NewState: new state of the specified SMI interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SMI_ITConfig(u32 SMI_IT, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + SMI->CR2 |= SMI_IT; + } + else + { + SMI->CR2 &= ~SMI_IT; + } +} + +/******************************************************************************* +* Function Name : SMI_SelectBank +* Description : Selects the memory Bank to be accessed. Only one Bank can be +* selected at a time. +* Input : - SMI_Bank: specifies the memory Bank to be selected. +* This parameter can be one of the following values: +* - SMI_Bank_0 +* - SMI_Bank_1 +* - SMI_Bank_2 +* - SMI_Bank_3 +* Output : None +* Return : None +*******************************************************************************/ +void SMI_SelectBank(u32 SMI_Bank) +{ + /* Clear BS[1:0] bits (Bank0 is selected)*/ + SMI->CR2 &= SMI_BS_RESET_Mask; + + switch(SMI_Bank) + { + case SMI_Bank_1: + /* Select Bank1 */ + SMI->CR2 |= SMI_BS_Bank1_Mask; + break; + + case SMI_Bank_2: + /* Select Bank2 */ + SMI->CR2 |= SMI_BS_Bank2_Mask; + break; + + case SMI_Bank_3: + /* Select Bank3 */ + SMI->CR2 |= SMI_BS_Bank3_Mask; + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : SMI_SendWENCmd +* Description : Sends a Write Enable command to the selected memory Bank. +* This function is used in Hardware mode only. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SMI_SendWENCmd(void) +{ + SMI->CR2 |= SMI_WEN_Mask; +} + +/******************************************************************************* +* Function Name : SMI_SendRSRCmd +* Description : Sends a Read Status Register Command to the selected memory +* Bank. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SMI_SendRSRCmd(void) +{ + SMI->CR2 |= SMI_RSR_Mask; +} + +/******************************************************************************* +* Function Name : SMI_SendCmd +* Description : Sends command to the selected memory Bank. This function is +* used in Software mode only. +* Input : - Command: specifies the command to send to the external memory. +* Output : None +* Return : None +*******************************************************************************/ +void SMI_SendCmd(u32 Command) +{ + /* Load the command in the Transmit Register */ + SMI->TR = Command; + + /* Start transfer */ + SMI->CR2 |= SMI_SEND_Mask; +} + +/******************************************************************************* +* Function Name : SMI_FastReadConfig +* Description : Enables or disables the Fast Read Mode. +* Input : - SMI_FastRead: specifies whether the Fast Read Mode is +* enabled or disabled. +* This parameter can be one of the following values: +* - SMI_FastRead_Disable : Fast Read Mode disabled +* - SMI_FastRead_Enable : Fast Read Mode enabled +* Output : None +* Return : None +*******************************************************************************/ +void SMI_FastReadConfig(u32 SMI_FastRead) +{ + if(SMI_FastRead == SMI_FastRead_Enable) + { + SMI->CR1 |= SMI_FastRead_Enable; + } + else + { + SMI->CR1 &= SMI_FastRead_Disable; + } +} + +/******************************************************************************* +* Function Name : SMI_WriteBurstConfig +* Description : Enables or disables the Write Burst Mode. +* Input : - SMI_WriteBurst: specifies whether the Write Burst Mode is +* enabled or disabled. +* This parameter can be one of the following values: +* - SMI_WriteBurst_Disable : Write Burst Mode disabled +* - SMI_WriteBurst_Enable : Write Burst Mode enabled +* Output : None +* Return : None +*******************************************************************************/ +void SMI_WriteBurstConfig(u32 SMI_WriteBurst) +{ + if(SMI_WriteBurst == SMI_WriteBurst_Enable) + { + SMI->CR1 |= SMI_WriteBurst_Enable; + } + else + { + SMI->CR1 &= SMI_WriteBurst_Disable; + } +} + +/******************************************************************************* +* Function Name : SMI_WriteByte +* Description : Writes a Byte to the selected memory Bank. This function is +* used in Hardware mode only. +* Before calling this function, send a Write Enable command to +* the selected memory Bank using SMI_SendWENCmd() function. +* Input : - WriteAddr: external memory address from which the data will +* be written. +* - Data: data to be written to the external memory. +* Output : None +* Return : None +*******************************************************************************/ +void SMI_WriteByte(u32 WriteAddr, u8 Data) +{ + /* Transfer data to the memory */ + *(u8 *) WriteAddr = Data; +} + +/******************************************************************************* +* Function Name : SMI_WriteHalfWord +* Description : Writes a Half Word to the selected memory Bank. This function +* is used in Hardware mode only. +* Before calling this function, send a Write Enable command to +* the selected memory Bank using SMI_SendWENCmd() function. +* Input : - WriteAddr: external memory address from which the data will +* be written. +* - Data: data to be written to the external memory. +* Output : None +* Return : None +*******************************************************************************/ +void SMI_WriteHalfWord(u32 WriteAddr, u16 Data) +{ + /* Transfer data to the memory */ + *(u16 *) WriteAddr = Data; +} + +/******************************************************************************* +* Function Name : SMI_WriteWord +* Description : Writes a Word to the selected memory Bank. This function is +* used in Hardware mode only. +* Before calling this function, send a Write Enable command to +* the selected memory Bank using SMI_SendWENCmd() function. +* Input : - WriteAddr: external memory address from which the data will +* be written. +* - Data: data to be written to the external memory. +* Output : None +* Return : None +*******************************************************************************/ +void SMI_WriteWord(u32 WriteAddr, u32 Data) +{ + /* Transfer data to the memory */ + *(u32 *) WriteAddr = Data; +} + +/******************************************************************************* +* Function Name : SMI_ReadByte +* Description : Reads a Byte from the selected memory Bank. This function is +* used in Hardware mode only. +* Input : - ReadAddr: external memory address to read from. +* Output : None +* Return : Data read from the external memory. +*******************************************************************************/ +u8 SMI_ReadByte(u32 ReadAddr) +{ + return(*(u8 *) ReadAddr); +} + +/******************************************************************************* +* Function Name : SMI_ReadHalfWord +* Description : Reads a Half Word from the selected memory Bank. This function +* is used in Hardware mode only. +* Input : - ReadAddr: external memory address to read from. +* Output : None +* Return : Data read from the external memory. +*******************************************************************************/ +u16 SMI_ReadHalfWord(u32 ReadAddr) +{ + return(*(u16 *) ReadAddr); +} + +/******************************************************************************* +* Function Name : SMI_ReadWord +* Description : Reads a Word from the selected memory Bank. This function is +* used in Hardware mode only. +* Input : - ReadAddr: external memory address to read from. +* Output : None +* Return : Data read from the external memory. +*******************************************************************************/ +u32 SMI_ReadWord(u32 ReadAddr) +{ + return(*(u32 *) ReadAddr); +} + +/******************************************************************************* +* Function Name : SMI_ReadMemoryStatusRegister +* Description : Reads the status register of the memory connected to the +* selected Bank. +* Input : None +* Output : None +* Return : External memory status register value. +*******************************************************************************/ +u8 SMI_ReadMemoryStatusRegister(void) +{ + return((u8) (SMI->SR & SMI_STATUSREGISTER_Mask)); +} + +/******************************************************************************* +* Function Name : SMI_GetFlagStatus +* Description : Checks whether the specified SMI flag is set or not. +* Input : - SMI_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - SMI_FLAG_Bank3_WM : Memory Bank3 Write Mode flag +* - SMI_FLAG_Bank2_WM : Memory Bank2 Write Mode flag +* - SMI_FLAG_Bank1_WM : Memory Bank1 Write Mode flag +* - SMI_FLAG_Bank0_WM : Memory Bank0 Write Mode flag +* - SMI_FLAG_ERF2 : Error Flag 2: Forbidden Write Request +* - SMI_FLAG_ERF1 : Error Flag 1: Forbidden Access +* - SMI_FLAG_WC : Write Complete flag +* - SMI_FLAG_TF : Transfer Finished flag +* Output : None +* Return : The new state of SMI_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus SMI_GetFlagStatus(u32 SMI_FLAG) +{ + if((SMI->SR & SMI_FLAG) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : SMI_ClearFlag +* Description : Clears the SMI’s pending flags. +* Input : - SMI_FLAG: specifies the flag to clear. +* This parameter can be any combination of the following values: +* - SMI_FLAG_ERF2 : Error Flag 2: Forbidden Write Request +* - SMI_FLAG_ERF1 : Error Flag 1: Forbidden Access +* - SMI_FLAG_WC : Write Complete flag +* - SMI_FLAG_TF : Transfer Finished flag +* Output : None +* Return : None +*******************************************************************************/ +void SMI_ClearFlag(u32 SMI_FLAG) +{ + SMI->SR &= ~SMI_FLAG; +} + +/******************************************************************************* +* Function Name : SMI_GetITStatus +* Description : Checks whether the specified SMI interrupt has occurred or not. +* Input : - SMI_FLAG: specifies the interrupt source to check. +* This parameter can be one of the following values: +* - SMI_IT_WC : Write Complete Interrupt +* - SMI_IT_TF : Transfer Finished Interrupt +* Output : None +* Return : The new state of SMI_IT (SET or RESET). +*******************************************************************************/ +ITStatus SMI_GetITStatus(u32 SMI_IT) +{ + if(((SMI->CR2 & SMI_IT) != RESET) && ((SMI->SR & SMI_IT) != RESET)) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : SMI_ClearITPendingBit +* Description : Clears the SMI’s interrupt pending bits. +* Input : - SMI_FLAG: specifies the interrupts sources to clear. +* This parameter can be any combination of the following values: +* - SMI_IT_WC : Write Complete Interrupt +* - SMI_IT_TF : Transfer Finished Interrupt +* Output : None +* Return : None +*******************************************************************************/ +void SMI_ClearITPendingBit(u32 SMI_IT) +{ + SMI->SR &= ~SMI_IT; +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_ssp.c b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_ssp.c new file mode 100644 index 000000000..b4ccd215e --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_ssp.c @@ -0,0 +1,588 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_ssp.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the SSP software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_ssp.h" +#include "75x_mrcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* SSP peripheral Enable */ +#define SSP_Enable 0x0002 +#define SSP_Disable 0xFFFD + +/* SSP Loop Back Mode Enable */ +#define SSP_LoopBackMode_Enable 0x0001 +#define SSP_LoopBackMode_Disable 0xFFFE + +/* SSP Flag Mask */ +#define SSP_Flag_Mask 0x001F + +/* SSP DMA transmit/ receive enable/disable Masks */ +#define SSP0_DMA_TransmitEnable 0x0002 +#define SSP0_DMA_TransmitDisable 0xFFFD +#define SSP0_DMA_ReceiveEnable 0x0001 +#define SSP0_DMA_ReceiveDisable 0xFFFE + +/* SSP Masks */ +#define SSP_FrameFormat_Mask 0xFFCF +#define SSP_DataSize_Mask 0xFFF0 +#define SSP_ClockRate_Mask 0x00FF +#define SSP_ClockPrescaler_Mask 0xFF00 +#define SSP_SSI_Set_Mask 0x0020 +#define SSP_SSI_Reset_Mask 0xFFDF + + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : SSP_DeInit +* Description : Deinitializes the SSPx peripheral registers to their default +* reset values. +* Input : SSPx: where x can be 0 or 1 to select the SSP peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void SSP_DeInit(SSP_TypeDef* SSPx) +{ + if(SSPx == SSP0) + { + /* Reset the SSP0 registers values*/ + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_SSP0,ENABLE); + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_SSP0,DISABLE); + } + else if (SSPx == SSP1) + { + /* Reset the SSP1 registers values*/ + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_SSP1,ENABLE); + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_SSP1,DISABLE); + } +} + +/******************************************************************************* +* Function Name : SSP_Init +* Description : Initializes the SSPx peripheral according to the specified +* parameters in the SSP_InitTypeDef structure. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - SSP_InitStruct: pointer to a SSP_InitTypeDef structure that +* contains the configuration information for the specified SSP +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void SSP_Init(SSP_TypeDef* SSPx, SSP_InitTypeDef* SSP_InitStruct) +{ + /* Configure the Frame format */ + if(SSP_InitStruct->SSP_FrameFormat == SSP_FrameFormat_TI) + { + /* Clear the FRF[1:0] bits */ + SSPx->CR0 &= SSP_FrameFormat_Mask; + /* Set the TI frame format */ + SSPx->CR0 |= SSP_FrameFormat_TI; + } + else + { + /* Set the Motorola frame format */ + SSPx->CR0 &= SSP_FrameFormat_Motorola; + /* Configure the Clock polarity */ + if(SSP_InitStruct->SSP_CPOL == SSP_CPOL_High) + { + /* SCK is held high when no data is being transfered */ + SSPx->CR0 |= SSP_CPOL_High; + } + else + { + /* SCK is held low when no data is being transfered */ + SSPx->CR0 &= SSP_CPOL_Low; + } + /* Configure the Clock Phase */ + if(SSP_InitStruct->SSP_CPHA == SSP_CPHA_2Edge) + { + /* Data captured on second clock edge */ + SSPx->CR0 |= SSP_CPHA_2Edge; + } + else + { + /* Data captured on first clock edge */ + SSPx->CR0 &= SSP_CPHA_1Edge; + } + } + + /* Configure the Mode */ + if(SSP_InitStruct->SSP_Mode == SSP_Mode_Slave) + { + /* Set the slave mode */ + SSPx->CR1 |= SSP_Mode_Slave; + /* Configure the Slave output */ + if(SSP_InitStruct->SSP_SlaveOutput == SSP_SlaveOutput_Disable) + { + /* Slave output disabled */ + SSPx->CR1 |= SSP_SlaveOutput_Disable; + } + else + { + /* Slave output enabled */ + SSPx->CR1 &= SSP_SlaveOutput_Enable; + } + /* Configure the NSS pin */ + if(SSP_InitStruct->SSP_NSS == SSP_NSS_Soft) + { + /* Slave selected by software through SSI bit */ + SSPx->CR1 |= SSP_NSS_Soft; + SSPx->CR1 &= SSP_SSI_Reset_Mask; + } + else + { + /* Slave selected by hardware through external SSpin */ + SSPx->CR1 &= SSP_NSS_Hard; + } + /* Configure the Clock rate and prescaler in TI slave mode */ + if(SSP_InitStruct->SSP_FrameFormat == SSP_FrameFormat_TI) + { + /* Clear clock rate SCR[7:0] bits */ + SSPx->CR0 &= SSP_ClockRate_Mask; + /* Set the serial clock rate */ + SSPx->CR0 |= (SSP_InitStruct->SSP_ClockRate<<8); + /* Clear clock prescaler CPSDVSR[7:0] bits */ + SSPx->PR &= SSP_ClockPrescaler_Mask; + /* Set the serial clock prescaler */ + SSPx->PR |= SSP_InitStruct->SSP_ClockPrescaler; + } + } + else + { + /* Set the master mode */ + SSPx->CR1 &= SSP_Mode_Master; + /* Configure the NSS pin */ + if(SSP_InitStruct->SSP_NSS == SSP_NSS_Soft) + { + /* Master selected by software through SSI bit */ + SSPx->CR1 |= SSP_NSS_Soft; + SSPx->CR1 |= SSP_SSI_Set_Mask; + } + else + { + /* Master selected by hardware through external SSpin */ + SSPx->CR1 &= SSP_NSS_Hard; + } + /* Clear clock rate SCR[7:0] bits */ + SSPx->CR0 &= SSP_ClockRate_Mask; + /* Set the serial clock rate */ + SSPx->CR0 |= (SSP_InitStruct->SSP_ClockRate<<8); + /* Clear clock prescaler CPSDVSR[7:0] bits */ + SSPx->PR &= SSP_ClockPrescaler_Mask; + /* Set the serial clock prescaler */ + SSPx->PR |= SSP_InitStruct->SSP_ClockPrescaler; + } + + /* Clear data size DSS[3:0] bits */ + SSPx->CR0 &= SSP_DataSize_Mask; + /* Set the data size */ + SSPx->CR0 |= SSP_InitStruct->SSP_DataSize; +} + +/******************************************************************************* +* Function Name : SSP_StructInit +* Description : Fills each SSP_InitStruct member with its default value. +* Input : SSP_InitStruct : pointer to a SSP_InitTypeDef structure + which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void SSP_StructInit(SSP_InitTypeDef* SSP_InitStruct) +{ + /* Initialize the SSP_FrameFormat member */ + SSP_InitStruct->SSP_FrameFormat = SSP_FrameFormat_Motorola; + + /* Initialize the SSP_Mode member */ + SSP_InitStruct->SSP_Mode = SSP_Mode_Master; + + /* Initialize the SSP_CPOL member */ + SSP_InitStruct->SSP_CPOL = SSP_CPOL_Low; + + /* Initialize the SSP_CPHA member */ + SSP_InitStruct->SSP_CPHA = SSP_CPHA_1Edge; + + /* Initialize the SSP_DataSize member */ + SSP_InitStruct->SSP_DataSize = SSP_DataSize_8b; + + /* Initialize the SSP_NSS member */ + SSP_InitStruct->SSP_NSS = SSP_NSS_Hard; + + /* Initialize the SSP_SlaveOutput member */ + SSP_InitStruct->SSP_SlaveOutput = SSP_SlaveOutput_Enable; + + /* Initialize the SSP_ClockRate member */ + SSP_InitStruct->SSP_ClockRate = 0; + + /* Initialize the SSP_ClockPrescaler member */ + SSP_InitStruct->SSP_ClockPrescaler = 0; +} + +/******************************************************************************* +* Function Name : SSP_Cmd +* Description : Enables or disables the specified SSP peripheral. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - NewState: new state of the SSPx peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SSP_Cmd(SSP_TypeDef* SSPx, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable the SSP peripheral */ + SSPx->CR1 |= SSP_Enable; + } + else + { + /* Disable the SSP peripheral */ + SSPx->CR1 &= SSP_Disable; + } +} + +/******************************************************************************* +* Function Name : SSP_ITConfig +* Description : Enables or disables the specified SSP interrupts. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - SSP_IT: specifies the SSP interrupts sources to be enabled +* or disabled. This parameter can be any combination of the +* following values: +* - SSP_IT_TxFifo: Transmit FIFO half empty or less interrupt +* - SSP_IT_RxFifo: Receive FIFO half full or less interrupt +* - SSP_IT_RxTimeOut: Receive timeout interrupt +* - SSP_IT_RxOverrun: Receive overrun interrupt +* - NewState: new state of the specified SSP interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SSP_ITConfig(SSP_TypeDef* SSPx, u16 SSP_IT, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable the selected SSP interrupts */ + SSPx->IMSCR |= SSP_IT; + } + else + { + /* Disable the selected SSP interrupts */ + SSPx->IMSCR &= ~SSP_IT; + } +} + +/******************************************************************************* +* Function Name : SSP_DMACmd +* Description : Configures the SSP0 DMA interface. +* Input : - SSP0_DMAtransfer : specifies the DMA transfer to be +* enabled or disabled. This parameter can be one of the +* following values: +* - SSP0_DMA_Transmit: transmit Fifo DMA transfer +* - SSP0_DMA_Receive: receive Fifo DMA transfer +* - NewState: new state of SSP0 DMA transfer. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SSP_DMACmd(u16 SSP0_DMAtransfer, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + if(SSP0_DMAtransfer == SSP0_DMA_Transmit) + { + /* Enable DMA for the transmit FIFO */ + SSP0->DMACR |= SSP0_DMA_TransmitEnable; + } + else + { + /* Enable DMA for the receive FIFO */ + SSP0->DMACR |= SSP0_DMA_ReceiveEnable; + } + } + else + { + if(SSP0_DMAtransfer == SSP0_DMA_Transmit) + { + /* Disable DMA for the transmit FIFO */ + SSP0->DMACR &= SSP0_DMA_TransmitDisable; + } + else + { + /* Disable DMA for the receive FIFO */ + SSP0->DMACR &= SSP0_DMA_ReceiveDisable; + } + } +} + +/******************************************************************************* +* Function Name : SSP_DMATxConfig +* Description : Configures the SSP0 DMA transmit transfer. +* Input : - SSP0_DMATxReq : specifies the SSP0 DMA transmit request to +* be enabled. This parameter can be one of the following +* values: +* - SSP0_DMATxReq_Single: Transmit FIFO DMA single +* request enabled +* - SSP0_DMATxReq_Burst: Transmit FIFO DMA burst request +* enabled +* Output : None +* Return : None +*******************************************************************************/ +void SSP_DMATxConfig(u16 SSP0_DMATxReq) +{ + if(SSP0_DMATxReq == SSP0_DMATxReq_Burst) + { + /* Enable DMA transmit burst request */ + SSP0->DMACR |= SSP0_DMATxReq_Burst; + } + else + { + /* Enable DMA transmit single request */ + SSP0->DMACR &= SSP0_DMATxReq_Single; + } +} + +/******************************************************************************* +* Function Name : SSP_DMARxConfig +* Description : Configures the SSP0 DMA receive transfer. +* Input : - SSP0_DMARxReq : specifies the SSP0 DMA receive request to +* be enabled. This parameter can be one of the following +* values: +* - SSP0_DMARxReq_Single: Receive FIFO DMA burst request +* enabled +* - SSP0_DMARxReq_Burst: Receive FIFO DMA single request +* enabled +* Output : None +* Return : None +*******************************************************************************/ +void SSP_DMARxConfig(u16 SSP0_DMARxReq) +{ + if(SSP0_DMARxReq == SSP0_DMARxReq_Burst) + { + /* Enable DMA receive burst request */ + SSP0->DMACR |= SSP0_DMARxReq_Burst; + } + else + { + /* Enable DMA receive single request */ + SSP0->DMACR &= SSP0_DMARxReq_Single; + } +} + +/******************************************************************************* +* Function Name : SSP_SendData +* Description : Transmits a Data through the SSP peripheral. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - Data : Data to be transmitted. +* Output : None +* Return : None +*******************************************************************************/ +void SSP_SendData(SSP_TypeDef* SSPx, u16 Data) +{ + /* Write in the DR register the data to be sent */ + SSPx->DR = Data; +} + +/******************************************************************************* +* Function Name : SSP_ReceiveData +* Description : Returns the most recent received data by the SSP peripheral. +* Input : SSPx: where x can be 0 or 1 to select the SSP peripheral. +* Output : None +* Return : The value of the received data. +*******************************************************************************/ +u16 SSP_ReceiveData(SSP_TypeDef* SSPx) +{ + /* Return the data in the DR register */ + return SSPx->DR; +} + +/******************************************************************************* +* Function Name : SSP_LoopBackConfig +* Description : Enables or disables the Loop back mode for the selected SSP +* peripheral. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - NewState: new state of the Loop Back mode. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SSP_LoopBackConfig(SSP_TypeDef* SSPx, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable loop back mode */ + SSPx->CR1 |= SSP_LoopBackMode_Enable; + } + else + { + /* Disable loop back mode */ + SSPx->CR1 &= SSP_LoopBackMode_Disable; + } +} + +/******************************************************************************* +* Function Name : SSP_NSSInternalConfig +* Description : Configures by software the NSS pin. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - SSP_NSSState: NSS internal state.This parameter can be one +* of the following values: +* - SSP_NSSInternal_Set: Set NSS pin internally +* - SSP_NSSInternal_Reset: Reset NSS pin internally +* Output : None +* Return : None +*******************************************************************************/ +void SSP_NSSInternalConfig(SSP_TypeDef* SSPx, u16 SSP_NSSState) +{ + if(SSP_NSSState == SSP_NSSInternal_Set) + { + /* Set NSS pin internally */ + SSPx->CR1 |= SSP_NSSInternal_Set; + } + else + { + /* Reset NSS pin internally */ + SSPx->CR1 &= SSP_NSSInternal_Reset; + } +} + +/******************************************************************************* +* Function Name : SSP_GetFlagStatus +* Description : Checks whether the specified SSP flag is set or not. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - SSP_FLAG: specifies the flag to check. This parameter can +* be one of the following values: +* - SSP_FLAG_Busy: busy flag +* - SSP_FLAG_RxFifoFull: Receive FIFO full flag +* - SSP_FLAG_RxFifoNotEmpty: Receive FIFO not empty flag +* - SSP_FLAG_TxFifoNotFull: Transmit FIFO not full flag +* - SSP_FLAG_TxFifoEmpty: Transmit FIFO empty flag +* - SSP_FLAG_TxFifo: Transmit FIFO half empty or less flag +* - SSP_FLAG_RxFifo: Receive FIFO half full or less flag +* - SSP_FLAG_RxTimeOut: Receive timeout flag +* - SSP_FLAG_RxOverrun: Receive overrun flag +* Output : None +* Return : The new state of SSP_FLAG(SET or RESET). +*******************************************************************************/ +FlagStatus SSP_GetFlagStatus(SSP_TypeDef* SSPx, u16 SSP_FLAG) +{ + u32 SSPReg = 0, FlagPos = 0; + u32 StatusReg = 0; + + /* Get the SSP register index */ + SSPReg = SSP_FLAG >> 5; + + /* Get the flag position */ + FlagPos = SSP_FLAG & SSP_Flag_Mask; + + /* Find the register of the flag to check */ + if(SSPReg == 1) + { + /* The flag to check is in SR register */ + StatusReg = SSPx->SR; + } + else if (SSPReg == 2) + { + /* The flag to check is in RISR register */ + StatusReg = SSPx->RISR; + } + + /* Check the status of the specified SSP flag */ + if((StatusReg & (1 << FlagPos)) != RESET) + { + /* Return SET if the SSP flag is set */ + return SET; + } + else + { + /* Return RESET if the SSP flag is reset */ + return RESET; + } +} + +/******************************************************************************* +* Function Name : SSP_ClearFlag +* Description : Clears the SSPx’s pending flags. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - SSP_FLAG: specifies the flag to clear. This parameter can +* be one of the following values: +* - SSP_FLAG_RxTimeOut: Receive timeout flag +* - SSP_FLAG_RxOverrun: Receive overrun flag +* Output : None +* Return : None +*******************************************************************************/ +void SSP_ClearFlag(SSP_TypeDef* SSPx, u16 SSP_FLAG) +{ + u8 FlagPos = 0; + + /* Get the flag position */ + FlagPos = SSP_FLAG & SSP_Flag_Mask; + + /* Clear the selected SSP flag */ + SSPx->ICR = (1 << FlagPos); +} + +/******************************************************************************* +* Function Name : SSP_GetITStatus +* Description : Checks whether the specified SSP interrupt has occurred or not. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - SSP_IT: specifies the interrupt source to check. +* This parameter can be one of the following values: +* - SSP_IT_TxFifo: Transmit FIFO half empty or less interrupt +* - SSP_IT_RxFifo: Receive FIFO half full or less interrupt +* - SSP_IT_RxTimeOut: Receive timeout interrupt +* - SSP_IT_RxOverrun: Receive overrun interrupt +* Output : None +* Return : The new state of SSP_IT(SET or RESET). +*******************************************************************************/ +ITStatus SSP_GetITStatus(SSP_TypeDef* SSPx, u16 SSP_IT) +{ + /* Check the status of the specified interrupt flag */ + if((SSPx->MISR & SSP_IT) != RESET) + { + /* Return SET if the SSP interrupt flag is set */ + return SET; + } + else + { + /* Return RESET if SSP interrupt flag is reset */ + return RESET; + } +} + +/******************************************************************************* +* Function Name : SSP_ClearITPendingBit +* Description : Clears the SSPx’s interrupt pending bits. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - SSP_IT: specifies the interrupt pending bit to clear. +* This parameter can be any combination of the following values: +* - SSP_IT_RxTimeOut: Receive timeout interrupt +* - SSP_IT_RxOverrun: Receive overrun interrupt +* Output : None +* Return : None +*******************************************************************************/ +void SSP_ClearITPendingBit(SSP_TypeDef* SSPx, u16 SSP_IT) +{ + /* Clear the selected SSP interrupts pending bits */ + SSPx->ICR = SSP_IT; +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_tb.c b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_tb.c new file mode 100644 index 000000000..4f461f997 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_tb.c @@ -0,0 +1,425 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_tb.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the TB software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_tb.h" +#include "75x_mrcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +#define TB_IT_Enable_Mask 0x7FFF +#define TB_IT_Clear_Mask 0x7FFF +#define TB_IC_Enable 0x0004 +#define TB_ICPolarity_Set 0x0008 +#define TB_ICPolarity_Reset 0xFFF7 +#define TB_UFS_Reset 0xFFFE +#define TB_UFS_Set 0x0001 + +/* TB debug state */ +#define TB_DBGC_Set 0x0400 +#define TB_DBGC_Reset 0xFB7F + +/* TB counter state */ +#define TB_COUNTER_Reset 0x0002 +#define TB_COUNTER_Start 0x0004 +#define TB_COUNTER_Stop 0xFFFB + +#define TB_SMS_EXTCLK_Set 0x0008 +#define TB_SMS_RESETCLK_Set 0x0000 + +/* TB Slave Mode Enable Set/Reset value */ +#define TB_SME_Reset 0x731B +#define TB_SME_Set 0x0004 + +/* TB Trigger Selection value */ +#define TB_TS_IC1_Set 0x0200 + +/* TB SCR Masks bit */ +#define TB_SlaveModeSelection_Mask 0x7307 +#define TB_TriggerSelection_Mask 0x701F + +/* Reset Register Masks */ +#define TB_Prescaler_Reset_Mask 0x0000 +#define TB_CounterMode_Mask 0xFF8F +#define TB_AutoReload_Reset_Mask 0xFFFF + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + + /****************************************************************************** +* Function Name : TB_DeInit +* Description : Deinitializes the TB peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TB_DeInit(void) +{ + /* Enters and exits the TB peripheral to and from reset */ + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TB,ENABLE); + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TB,DISABLE); +} + +/******************************************************************************* +* Function Name : TB_Init +* Description : Initializes TB peripheral according to the specified +* parameters in the TB_InitStruct. +* Input : TB_InitStruct: pointer to a TB_InitTypeDef structure that +* contains the configuration information for the TB peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TB_Init(TB_InitTypeDef* TB_InitStruct) +{ + /* Set the TB prescaler value */ + TB->PSC = TB_InitStruct->TB_Prescaler; + + /* Set the TB period value */ + TB->ARR = TB_InitStruct->TB_AutoReload; + + /* Set the corresponding counter mode */ + TB->CR = (TB->CR & TB_CounterMode_Mask) | TB_InitStruct->TB_CounterMode; + + /* Set the corresponding clock source */ + if(TB_InitStruct->TB_ClockSource == TB_ClockSource_CKRTC) + { + TB->SCR &= TB_SME_Reset & TB_SlaveModeSelection_Mask & TB_TriggerSelection_Mask; + TB->SCR |= TB_SMS_EXTCLK_Set | TB_SME_Set | TB_TS_IC1_Set; + } + else + { + TB->SCR &= TB_SME_Reset & TB_SlaveModeSelection_Mask & TB_TriggerSelection_Mask; + } + + if(TB_InitStruct->TB_Mode == TB_Mode_IC) + { + /* Set the corresponding value in TB SCR register */ + TB->SCR &= TB_SME_Reset & TB_SlaveModeSelection_Mask & TB_TriggerSelection_Mask; + TB->SCR |= TB_SMS_RESETCLK_Set | TB_SME_Set | TB_TS_IC1_Set; + + /* Set the IC1 enable bit */ + TB->IMCR |= TB_IC_Enable; + + /* Set the input signal polarity */ + if (TB_InitStruct->TB_ICAPolarity == TB_ICAPolarity_Falling) + { + TB->IMCR |= TB_ICPolarity_Set; + } + else + { + TB->IMCR &= TB_ICPolarity_Reset; + } + } +} + +/******************************************************************************* +* Function Name : TB_StructInit +* Description : Fills each TB_InitStruct member with its default value +* Input : TB_InitStruct : pointer to a TB_InitTypeDef structure which +* will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void TB_StructInit(TB_InitTypeDef *TB_InitStruct) +{ + TB_InitStruct->TB_Mode = TB_Mode_Timing; + TB_InitStruct->TB_ClockSource = TB_ClockSource_CKTIM; + TB_InitStruct->TB_CounterMode = TB_CounterMode_Up; + TB_InitStruct->TB_ICAPolarity = TB_ICAPolarity_Rising; + TB_InitStruct->TB_Prescaler = TB_Prescaler_Reset_Mask; + TB_InitStruct->TB_AutoReload = TB_AutoReload_Reset_Mask; +} + +/******************************************************************************* +* Function Name : TB_Cmd +* Description : Enables or disables the TB peripheral. +* Input : Newstate: new state of the TB peripheral. This parameter can +* be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TB_Cmd(FunctionalState Newstate) +{ + if(Newstate == ENABLE) + { + TB->CR |= TB_COUNTER_Start; + } + else + { + TB->CR &= TB_COUNTER_Stop; + } +} + +/******************************************************************************* +* Function Name : TB_ITConfig +* Description : Enables or disables the specified TB interrupt. +* Input : - TB_IT: specifies the TB interrupt sources to be enabled or +* disabled. +* This parameter can be any combination of the following values: +* - TB_IT_Update: TB Update interrupt +* - TB_IT_GlobalUpdate: TB Global Update interrupt +* - TB_IT_IC: TB Input Capture interrupt +* - Newstate: new state of the specified TB interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TB_ITConfig(u16 TB_IT, FunctionalState Newstate) +{ + u16 TB_IT_Enable = 0; + + TB_IT_Enable = TB_IT & TB_IT_Enable_Mask; + + if(Newstate == ENABLE) + { + /* Update interrupt global source: overflow/undeflow, counter reset operation + or slave mode controller in reset mode */ + if ((TB_IT & TB_IT_GlobalUpdate) == TB_IT_GlobalUpdate) + { + TB->CR &= TB_UFS_Reset; + } + /* Update interrupt source: counter overflow/underflow */ + else if ((TB_IT & TB_IT_Update) == TB_IT_Update) + { + TB->CR |= TB_UFS_Set; + } + /* Select and enable the interrupts requests */ + TB->RSR |= TB_IT_Enable; + TB->RER |= TB_IT_Enable; + } + /* Disable the interrupts requests */ + else + { + TB->RSR &= ~TB_IT_Enable; + TB->RER &= ~TB_IT_Enable; + } +} + +/******************************************************************************* +* Function Name : TB_SetPrescaler +* Description : Sets the TB Prescaler value. +* Input : Prescaler: specifies the TB Prescaler value. +* Output : None +* Return : None +*******************************************************************************/ +void TB_SetPrescaler(u16 Prescaler) +{ + /* Sets the prescaler value */ + TB->PSC = Prescaler; +} + +/******************************************************************************* +* Function Name : TB_ResetCounter +* Description : Re-intializes the counter and generates an update of the +* registers. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TB_ResetCounter(void) +{ + /* Re-intializes TB counter */ + TB->CR |= TB_COUNTER_Reset; +} + +/******************************************************************************* +* Function Name : TB_DebugCmd +* Description : Enables or disables TB peripheral Debug control. +* Input : Newstate: new state of the TB Debug control. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TB_DebugCmd(FunctionalState Newstate) +{ + if(Newstate == ENABLE) + { + TB->CR |= TB_DBGC_Set; + } + else + { + TB->CR &= TB_DBGC_Reset; + } +} + +/******************************************************************************* +* Function Name : TB_CounterModeConfig +* Description : Configures the TB Counter Mode. +* Input : TB_CounterMode: specifies the TB counter mode to be used. +* This parameter can be one of the following values: +* - TB_CounterMode_Up: TB Up Counting Mode +* - TB_CounterMode_Down: TB Down Counting Mode +* - TB_CounterMode_CenterAligned: TB Center Aligned Mode +* Output : None +* Return : None +*******************************************************************************/ +void TB_CounterModeConfig(u16 TB_CounterMode) +{ + /* Counter mode configuration */ + TB->CR &= TB_CounterMode_Mask; + TB->CR |= TB_CounterMode; +} + +/******************************************************************************* +* Function Name : TB_SLaveModeConfig +* Description : Configures the TB slave Mode. +* Input : TB_SMSMode: specifies the TB slave mode to be used. +* This parameter can be one of the following values: +* - TB_SMSMode_Trigger: The counter starts at a rising +* edge of the trigger +* - TB_SMSMode_Gated: The counter clock is enabled when +* trigger signal is high +* - TB_SMSMode_External: The rising edge of selected trigger +* clocks the counter +* - TB_SMSMode_Reset: The rising edge of the selected +* trigger signal resets the counter +* Output : None +* Return : None +*******************************************************************************/ +void TB_SLaveModeConfig(u16 TB_SMSMode) +{ + TB->SCR &= TB_SME_Reset & TB_SlaveModeSelection_Mask & TB_TriggerSelection_Mask; + TB->SCR |= TB_SME_Set | TB_SMSMode | TB_TS_IC1_Set; +} +/******************************************************************************* +* Function Name : TB_GetCounter +* Description : Gets the TB Counter value. +* Input : None +* Output : None +* Return : The TB counter register value. +*******************************************************************************/ +u16 TB_GetCounter(void) +{ + return TB->CNT; +} + +/******************************************************************************* +* Function Name : TB_GetICAP1 +* Description : Gets the TB Input capture value. +* Input : None +* Output : None +* Return : The TB ICR1 register value. +*******************************************************************************/ +u16 TB_GetICAP1(void) +{ + return TB->ICR1; +} + +/******************************************************************************* +* Function Name : TB_SetCounter +* Description : Sets the TB Counter value. +* Input : Counter: specifies the TB Counter value. +* Output : None +* Return : None +*******************************************************************************/ +void TB_SetCounter(u16 Counter) +{ + TB->CNT = Counter; +} + +/******************************************************************************* +* Function Name : TB_GetFlagStatus +* Description : Checks whether the specified TB flag is set or not. +* Input : TB_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - TB_FLAG_IC: TB Input Capture flag +* - TB_FLAG_Update: TB update flag +* Output : None +* Return : The new state of the TB_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus TB_GetFlagStatus(u16 TB_FLAG) +{ + if((TB->ISR & TB_FLAG) != RESET ) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : TB_ClearFlag +* Description : Clears the TB’s pending flags. +* Input : TB_FLAG: specifies the flag to clear. +* This parameter can be any combination of the following values: +* - TB_FLAG_IC: TB Input Capture flag +* - TB_FLAG_Update: TB update flag +* Output : None +* Return : None +*******************************************************************************/ +void TB_ClearFlag(u16 TB_FLAG) +{ + /* Clears the flags */ + TB->ISR &= ~TB_FLAG; +} + +/******************************************************************************* +* Function Name : TB_GetITStatus +* Description : Checks whether the specified TB interrupt has occurred or not. +* Input : TB_IT: specifies the interrupt to check. +* This parameter can be one of the following values: +* - TB_IT_Update: TB Update interrupt +* - TB_IT_GlobalUpdate: TB Global Update interrupt +* - TB_IT_IC: TB Input Capture interrupt +* Output : None +* Return : The new state of the TB_IT (SET or RESET). +*******************************************************************************/ +ITStatus TB_GetITStatus(u16 TB_IT) +{ + u16 TB_IT_Check = 0; + + /* Calculates the pending bits to be checked */ + TB_IT_Check = TB_IT & TB_IT_Clear_Mask; + + if((TB->ISR & TB_IT_Check) != RESET ) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : TB_ClearITPendingBit +* Description : Clears the TB's interrupt pending bits. +* Input : TB_IT: specifies the interrupt pending bit to clear. +* This parameter can be any combination of the following values: +* - TB_IT_Update: TB Update interrupt +* - TB_IT_GlobalUpdate: TB Global Update interrupt +* - TB_IT_IC: TB Input Capture interrupt +* Output : None +* Return : None +*******************************************************************************/ +void TB_ClearITPendingBit(u16 TB_IT) +{ + u16 TB_IT_Clear = 0; + + /* Calculates the pending bits to be cleared */ + TB_IT_Clear = TB_IT & TB_IT_Clear_Mask; + + /* Clears the pending bits */ + TB->ISR &= ~TB_IT_Clear; +} +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_tim.c b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_tim.c new file mode 100644 index 000000000..d23d97965 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_tim.c @@ -0,0 +1,1360 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_tim.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the TIM software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_tim.h" +#include "75x_mrcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* TIM interrupt masks */ +#define TIM_IT_Clear_Mask 0x7FFF +#define TIM_IT_Enable_Mask 0x7FFF + +/* TIM Input Capture Selection Set/Reset */ +#define TIM_IC1S_Set 0x0001 +#define TIM_IC1S_Reset 0x003E + +/* TIM Input Capture Selection Set/Reset */ +#define TIM_IC2S_Set 0x0002 +#define TIM_IC2S_Reset 0x003D + +/* TIM_SCR Masks bit */ +#define TIM_Encoder_Mask 0x731C +#define TIM_SlaveModeSelection_Mask 0x7307 +#define TIM_TriggerSelection_Mask 0x701F +#define TIM_InternalTriggerSelection_Mask 0x031F + +/* TIM Encoder mode Set value */ +#define TIM_Encoder1_Set 0x0001 +#define TIM_Encoder2_Set 0x0002 +#define TIM_Encoder3_Set 0x0003 + +/* TIM Slave Mode Enable Set/Reset value */ +#define TIM_SME_Reset 0x731B +#define TIM_SME_Set 0x0004 + +/* TIM Internal Trigger Selection value */ +#define TIM_ITS_TIM0 0x1000 +#define TIM_ITS_TIM1 0x2000 +#define TIM_ITS_TIM2 0x3000 +#define TIM_ITS_PWM 0x4000 + +/* TIM Trigger Selection value */ +#define TIM_TS_IC1_Set 0x0200 +#define TIM_TS_IC2_Set 0x0300 + +/* TIM Slave Mode selction external clock Set value */ +#define TIM_SMS_EXTCLK_Set 0x0008 +#define TIM_SMS_RESETCLK_Set 0x0000 + +/* TIM_CR Masks bit */ +#define TIM_DBASE_Mask 0x077F +#define TIM_MasterModeSelection_Mask 0xFC7F +#define TIM_CounterMode_Mask 0xFF8F + +/* TIM Update flag selection Set/Reset value */ +#define TIM_UFS_Reset 0xFFFE +#define TIM_UFS_Set 0x0001 + +/* TIM Counter value */ +#define TIM_COUNTER_Reset 0x0002 +#define TIM_COUNTER_Start 0x0004 +#define TIM_COUNTER_Stop 0xFFFB + +/* TIM One pulse Mode set value */ +#define TIM_OPM_Set 0x0008 +#define TIM_OPM_Reset 0xFFF7 + +/* TIM Debug Mode Set/Reset value */ +#define TIM_DBGC_Set 0x0400 +#define TIM_DBGC_Reset 0xFB7F + +/* TIM Input Capture Enable/Disable value */ +#define TIM_IC1_Enable 0x0004 +#define TIM_IC2_Enable 0x0010 + +/* TIM Input Capture Polarity Set/Reset value */ +#define TIM_IC1P_Set 0x0008 +#define TIM_IC2P_Set 0x0020 +#define TIM_IC1P_Reset 0x0037 +#define TIM_IC2P_Reset 0x001F + +/* TIM Output Compare Polarity Set/Reset value */ +#define TIM_OC1P_Set 0x0020 +#define TIM_OC2P_Set 0x2000 +#define TIM_OC1P_Reset 0x3F1F +#define TIM_OC2P_Reset 0x1F3F + +/* TIM Output Compare control mode constant */ +#define TIM_OCControl_PWM 0x000C +#define TIM_OCControl_OCToggle 0x0006 +#define TIM_OCControl_OCInactive 0x0004 +#define TIM_OCControl_OCActive 0x0002 +#define TIM_OCControl_OCTiming 0x0000 + +/* TIM Output Compare mode Enable value */ +#define TIM_OC1_Enable 0x0010 +#define TIM_OC2_Enable 0x1000 + +/* TIM Output Compare mode Mask value */ +#define TIM_OC1C_Mask 0x3F31 +#define TIM_OC2C_Mask 0x313F + +/* TIM Preload bit Set/Reset value */ +#define TIM_PLD1_Set 0x0001 +#define TIM_PLD1_Reset 0xFFFE + +#define TIM_PLD2_Set 0x0100 +#define TIM_PLD2_Reset 0xFEFF + +/* TIM OCRM Set/Reset value */ +#define TIM_OCRM_Set 0x0080 +#define TIM_OCRM_Reset 0x030D + +/* Reset Register Masks */ +#define TIM_Pulse2_Reset_Mask 0x0000 +#define TIM_Prescaler_Reset_Mask 0x0000 +#define TIM_Pulse1_Reset_Mask 0x0000 +#define TIM_Period_Reset_Mask 0xFFFF +#define TIM_Counter_Reset 0x0002 + +/* Private function prototypes -----------------------------------------------*/ +static void ICAP_ModuleConfig(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct); +static void Encoder_ModeConfig(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct); +static void OCM_ModuleConfig(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct); + +/* Private functions ---------------------------------------------------------*/ + +/****************************************************************************** +* Function Name : TIM_DeInit +* Description : Deinitializes TIM peripheral registers to their default reset +* values. +* Input : TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_DeInit(TIM_TypeDef *TIMx) +{ + if(TIMx == TIM0) + { + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TIM0,ENABLE); + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TIM0,DISABLE); + } + else if(TIMx == TIM1) + { + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TIM1,ENABLE); + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TIM1,DISABLE); + } + else if(TIMx == TIM2) + { + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TIM2,ENABLE); + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TIM2,DISABLE); + } +} + +/******************************************************************************* +* Function Name : TIM_Init +* Description : Initializes the TIMx peripheral according to the specified +* parameters in the TIM_InitStruct . +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. +* - TIM_InitStruct: pointer to a TIM_InitTypeDef structure that +* contains the configuration information for the specified TIM +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_Init(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct) +{ + /* Set the prescaler value */ + TIMx->PSC = TIM_InitStruct->TIM_Prescaler; + + /* Select the clock source */ + TIM_ClockSourceConfig(TIMx, TIM_InitStruct->TIM_ClockSource, + TIM_InitStruct->TIM_ExtCLKEdge); + + /* Select the counter mode */ + TIMx->CR &= TIM_CounterMode_Mask; + TIMx->CR |= TIM_InitStruct->TIM_CounterMode; + + /* Set the period value */ + TIMx->ARR = TIM_InitStruct->TIM_Period; + + switch(TIM_InitStruct->TIM_Mode) + { + case TIM_Mode_OCTiming: case TIM_Mode_OCActive: case TIM_Mode_OCInactive: + case TIM_Mode_OCToggle: case TIM_Mode_PWM: + OCM_ModuleConfig(TIMx, TIM_InitStruct); + break; + + case TIM_Mode_PWMI: case TIM_Mode_IC: + ICAP_ModuleConfig(TIMx, TIM_InitStruct); + break; + + case TIM_Mode_Encoder1: case TIM_Mode_Encoder2: case TIM_Mode_Encoder3: + Encoder_ModeConfig(TIMx, TIM_InitStruct); + break; + + case TIM_Mode_OPM_PWM: case TIM_Mode_OPM_Toggle: case TIM_Mode_OPM_Active: + + /* Output module configuration */ + OCM_ModuleConfig(TIMx, TIM_InitStruct); + + /* Input module configuration */ + ICAP_ModuleConfig(TIMx, TIM_InitStruct); + + /* Set the slave mode to trigger Mode */ + TIMx->SCR |= TIM_SynchroMode_Trigger; + + /* Repetitive pulse state selection */ + if(TIM_InitStruct->TIM_RepetitivePulse == TIM_RepetitivePulse_Disable) + { + TIMx->CR |= TIM_OPM_Set; + } + else + { + TIMx->CR &= TIM_OPM_Reset; + } + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : TIM_StructInit +* Description : Fills each TIM_InitStruct member with its default value. +* Input : TIM_InitStruct : pointer to a TIM_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None. +*******************************************************************************/ +void TIM_StructInit(TIM_InitTypeDef *TIM_InitStruct) +{ + /* Set the default configuration */ + TIM_InitStruct->TIM_Mode = TIM_Mode_OCTiming; + TIM_InitStruct->TIM_Prescaler = TIM_Prescaler_Reset_Mask; + TIM_InitStruct->TIM_ClockSource = TIM_ClockSource_Internal; + TIM_InitStruct->TIM_ExtCLKEdge = TIM_ExtCLKEdge_Rising; + TIM_InitStruct->TIM_CounterMode = TIM_CounterMode_Up; + TIM_InitStruct->TIM_Period = TIM_Period_Reset_Mask; + TIM_InitStruct->TIM_Channel = TIM_Channel_ALL; + TIM_InitStruct->TIM_Pulse1 = TIM_Pulse1_Reset_Mask; + TIM_InitStruct->TIM_Pulse2 = TIM_Pulse2_Reset_Mask; + TIM_InitStruct->TIM_RepetitivePulse = TIM_RepetitivePulse_Disable; + TIM_InitStruct->TIM_Polarity1 = TIM_Polarity1_Low; + TIM_InitStruct->TIM_Polarity2 = TIM_Polarity2_Low; + TIM_InitStruct->TIM_IC1Selection = TIM_IC1Selection_TI1; + TIM_InitStruct->TIM_IC2Selection = TIM_IC2Selection_TI1; + TIM_InitStruct->TIM_IC1Polarity = TIM_IC1Polarity_Rising; + TIM_InitStruct->TIM_IC2Polarity = TIM_IC2Polarity_Rising; + TIM_InitStruct->TIM_PWMI_ICSelection = TIM_PWMI_ICSelection_TI1; + TIM_InitStruct->TIM_PWMI_ICPolarity = TIM_PWMI_ICPolarity_Rising; +} + +/******************************************************************************* +* Function Name : TIM_Cmd +* Description : Enables or disables the specified TIM peripheral. +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. +* - Newstate: new state of the TIMx peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState Newstate) +{ + if(Newstate == ENABLE) + { + TIMx->CR |= TIM_COUNTER_Start; + } + else + { + TIMx->CR &= TIM_COUNTER_Stop; + } +} + +/******************************************************************************* +* Function Name : TIM_ITConfig +* Description : Enables or disables the TIM interrupts. +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. +* - TIM_IT: specifies the TIM interrupts sources to be enabled +* or disabled. +* This parameter can be any combination of the following values: +* - TIM_IT_IC1: Input Capture 1 Interrupt +* - TIM_IT_OC1: Output Compare 1 Interrupt +* - TIM_IT_Update: Timer update Interrupt +* - TIM_IT_GlobalUpdate: Timer global update Interrupt +* - TIM_IT_IC2: Input Capture 2 Interrupt +* - TIM_IT_OC2: Output Compare 2 Interrupt +* - Newstate: new state of the specified TIMx interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ITConfig(TIM_TypeDef *TIMx, u16 TIM_IT, FunctionalState Newstate) +{ + u16 TIM_IT_Enable = 0; + + TIM_IT_Enable = TIM_IT & TIM_IT_Enable_Mask; + + if(Newstate == ENABLE) + { + /* Update interrupt global source: overflow/undeflow, counter reset operation + or slave mode controller in reset mode */ + if((TIM_IT & TIM_IT_GlobalUpdate) == TIM_IT_GlobalUpdate) + { + TIMx->CR &= TIM_UFS_Reset; + } + /* Update interrupt source: counter overflow/underflow */ + else if((TIM_IT & TIM_IT_Update) == TIM_IT_Update) + { + TIMx->CR |= TIM_UFS_Set; + } + /* Select and enable the interrupts requests */ + TIMx->RSR |= TIM_IT_Enable; + TIMx->RER |= TIM_IT_Enable; + } + /* Disable the interrupts requests */ + else + { + TIMx->RSR &= ~TIM_IT_Enable; + TIMx->RER &= ~TIM_IT_Enable; + } +} + +/******************************************************************************* +* Function Name : TIM_PreloadConfig +* Description : Enables or disables TIM peripheral Preload register on OCRx. +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. +* - TIM_Channel: specifies the TIM channel to be used. +* This parameter can be one of the following values: +* - TIM_Channel_1: TIM Channel 1 is used +* - TIM_Channel_2: TIM Channel 2 is used +* - TIM_Channel_ALL: TIM Channel 1and 2 are used +* - Newstate: new state of the TIMx peripheral Preload register +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_PreloadConfig(TIM_TypeDef *TIMx, u16 TIM_Channel, FunctionalState Newstate) +{ + if(Newstate == ENABLE) + { + switch (TIM_Channel) + { + case TIM_Channel_1: + TIMx->OMR1 |= TIM_PLD1_Set; + break; + + case TIM_Channel_2: + TIMx->OMR1 |= TIM_PLD2_Set; + break; + + case TIM_Channel_ALL: + TIMx->OMR1 |= TIM_PLD1_Set | TIM_PLD2_Set; + break; + + default: + break; + } + } + else + { + switch (TIM_Channel) + { + case TIM_Channel_1: + TIMx->OMR1 &= TIM_PLD1_Reset; + break; + + case TIM_Channel_2: + TIMx->OMR1 &= TIM_PLD2_Reset; + break; + + case TIM_Channel_ALL: + TIMx->OMR1 &= TIM_PLD1_Reset & TIM_PLD2_Reset; + break; + + default: + break; + } + } +} + +/******************************************************************************* +* Function Name : TIM_DMAConfig +* Description : Configures the TIM0’s DMA interface. +* Input : - TIM_DMASources: specifies the DMA Request sources. +* This parameter can be any combination of the following values: +* - TIM_DMASource_OC1: Output Compare 1 DMA source +* - TIM_DMASource_OC2: Output Compare 2 DMA source +* - TIM_DMASource_IC1: Input Capture 1 DMA source +* - TIM_DMASource_IC2: Input Capture 2 DMA source +* - TIM_DMASource_Update: Timer Update DMA source +* - TIM_OCRMState: the state of output compare request mode. +* This parameter can be one of the following values: +* - TIM_OCRMState_Enable +* - TIM_OCRMState_Disable +* - TIM_DMABase:DMA Base address. +* This parameter can be one of the following values: +* TIM_DMABase_CR, TIM_DMABase_SCR, TIM_DMABase_IMCR, +* TIM_DMABase_OMR1, TIM_DMABase_RSR, +* TIM_DMABase_RER, TIM_DMABase_ISR, TIM_DMABase_CNT, +* TIM_DMABase_PSC, TIM_DMABase_ARR, TIM_DMABase_OCR1, +* TIM_DMABase_OCR2, TIM_DMABase_ICR1, TIM_DMABase_ICR2 +* Output : None +* Return : None +*******************************************************************************/ +void TIM_DMAConfig(u16 TIM_DMASources, u16 TIM_OCRMState, u16 TIM_DMABase) +{ + /* Select the DMA requests */ + TIM0->RSR &= TIM_DMASources; + + /* Set the OCRM state */ + if(TIM_OCRMState == TIM_OCRMState_Enable) + { + TIM0->RSR |= TIM_OCRM_Set; + } + else + { + TIM0->RSR &= TIM_OCRM_Reset; + } + + /* Set the DMA Base address */ + TIM0->CR &= TIM_DBASE_Mask; + TIM0->CR |= TIM_DMABase; +} + +/******************************************************************************* +* Function Name : TIM_DMACmd +* Description : Enables or disables the TIM0’s DMA interface. +* Input : - TIM_DMASources: specifies the DMA Request sources. +* This parameter can be any combination of the following values: +* - TIM_DMASource_OC1: Output Compare 1 DMA source +* - TIM_DMASource_OC2: Output Compare 2 DMA source +* - TIM_DMASource_IC1: Input Capture 1 DMA source +* - TIM_DMASource_IC2: Input Capture 2 DMA source +* - TIM_DMASource_Update: Timer Update DMA source +* - Newstate: new state of the DMA Request sources. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_DMACmd(u16 TIM_DMASources, FunctionalState Newstate) +{ + if(Newstate == ENABLE) + { + TIM0->RER |= TIM_DMASources; + } + else + { + TIM0->RER &= ~TIM_DMASources; + } +} + +/******************************************************************************* +* Function Name : TIM_ClockSourceConfig +* Description : Configures the TIM clock source. +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. +* - TIM_ClockSource: specifies the TIM clock source to be +* selected. +* This parameter can be one of the following values: +* - TIM_ClockSource_Internal: CK_TIM internal clock +* - TIM_ClockSource_TI11: External input pin TI1 +* connected to IC1 channel. +* - TIM_ClockSource_TI12: External input pin TI1 +* connected to IC2 channel. +* - TIM_ClockSource_TI22: External input pin TI2 +* connected to IC2 channel. +* - TIM_ClockSource_TI21: External input pin TI2 +* connected to IC1 channel. +* - TIM_ExtCLKEdge: specifies the External input signal edge. +* This parameter can be one of the following values: +* - TIM_ExtCLKEdge_Falling : Falling edge selected. +* - TIM_ExtCLKEdge_Rising : Rising edge selected. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ClockSourceConfig(TIM_TypeDef *TIMx, u16 TIM_ClockSource, + u16 TIM_ExtCLKEdge) +{ + if(TIM_ClockSource == TIM_ClockSource_Internal) + { + /* CK_TIM is used as clock source */ + TIMx->SCR &= TIM_SME_Reset & TIM_SlaveModeSelection_Mask & TIM_TriggerSelection_Mask; + } + else + /* Input Captures are used as TIM external clock */ + { + TIMx->SCR &= TIM_SME_Reset & TIM_SlaveModeSelection_Mask & TIM_TriggerSelection_Mask; + TIMx->SCR |= TIM_SMS_EXTCLK_Set | TIM_SME_Set; + + if((TIM_ClockSource == TIM_ClockSource_TI11) || + (TIM_ClockSource == TIM_ClockSource_TI21)) + /* Input Capture 1 is selected */ + { + /* Input capture Enable */ + TIMx->IMCR |= TIM_IC1_Enable; + TIMx->SCR |= TIM_TS_IC1_Set; + + if(TIM_ExtCLKEdge == TIM_ExtCLKEdge_Falling) + /* Set the corresponding polarity */ + { + TIMx->IMCR |= TIM_IC1P_Set; + } + else + { + TIMx->IMCR &= TIM_IC1P_Reset; + } + if(TIM_ClockSource == TIM_ClockSource_TI11) + { + /* External signal TI1 connected to IC1 channel */ + TIMx->IMCR &= TIM_IC1S_Reset; + } + else + { + /* External signal TI2 connected to IC1 channel */ + TIMx->IMCR |= TIM_IC1S_Set; + } + } + else + /* Input Capture 2 is selected */ + { + /* Input capture Enable */ + TIMx->IMCR |= TIM_IC2_Enable; + TIMx->SCR |= TIM_TS_IC2_Set; + + if(TIM_ExtCLKEdge == TIM_ExtCLKEdge_Falling) + /* Set the corresponding polarity */ + { + TIMx->IMCR |= TIM_IC2P_Set; + } + else + { + TIMx->IMCR &= TIM_IC2P_Reset; + } + if(TIM_ClockSource == TIM_ClockSource_TI22) + { + /* External signal TI2 connected to IC2 channel */ + TIMx->IMCR &= TIM_IC2S_Reset; + } + else + { + /* External signal TI1 connected to IC2 channel */ + TIMx->IMCR |= TIM_IC2S_Set; + } + } + } +} + +/******************************************************************************* +* Function Name : TIM_SetPrescaler +* Description : Sets the TIM prescaler value. +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral +* - Prescaler: TIM prescaler new value. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetPrescaler(TIM_TypeDef* TIMx, u16 Prescaler) +{ + TIMx->PSC = Prescaler; +} + +/******************************************************************************* +* Function Name : TIM_SetPeriod +* Description : Sets the TIM period value. +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral +* - Period: TIM period new value. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetPeriod(TIM_TypeDef* TIMx, u16 Period) +{ + TIMx->ARR = Period; +} + +/******************************************************************************* +* Function Name : TIM_SetPulse +* Description : Sets the TIM pulse value. +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral +* - TIM_Channel: specifies the TIM channel to be used. +* This parameter can be one of the following values: +* - TIM_Channel_1: TIM Channel 1 is used +* - TIM_Channel_2: TIM Channel 2 is used +* - TIM_Channel_ALL: TIM Channel 1and 2 are used +* - Pulse: TIM pulse new value. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetPulse(TIM_TypeDef* TIMx, u16 TIM_Channel, u16 Pulse) +{ + /* Set Channel 1 pulse value */ + if(TIM_Channel == TIM_Channel_1) + { + TIMx->OCR1 = Pulse; + } + /* Set Channel 2 pulse value */ + else if(TIM_Channel == TIM_Channel_2) + { + TIMx->OCR2 = Pulse; + } + /* Set Channel 1 and Channel 2 pulse values */ + else if(TIM_Channel == TIM_Channel_ALL) + { + TIMx->OCR1 = Pulse; + TIMx->OCR2 = Pulse; + } +} + +/******************************************************************************* +* Function Name : TIM_GetICAP1 +* Description : Gets the Input Capture 1 value. +* Input : TIMx: where x can be 0, 1 or 2 to select the TIM peripheral +* Output : None +* Return : Input Capture 1 Register value. +*******************************************************************************/ +u16 TIM_GetICAP1(TIM_TypeDef *TIMx) +{ + return TIMx->ICR1; +} + +/******************************************************************************* +* Function Name : TIM_GetICAP2 +* Description : Gets the Input Capture 2 value. +* Input : TIMx: where x can be 0, 1 or 2 to select the TIM peripheral +* Output : None +* Return : Input Capture 2 Register value +*******************************************************************************/ +u16 TIM_GetICAP2(TIM_TypeDef *TIMx) +{ + return TIMx->ICR2; +} + +/******************************************************************************* +* Function Name : TIM_GetPWMIPulse +* Description : Gets the PWM Input pulse value. +* Input : TIMx: where x can be 0, 1 or 2 to select the TIM peripheral +* Output : None +* Return : Input Capture 2 Register value +*******************************************************************************/ +u16 TIM_GetPWMIPulse(TIM_TypeDef *TIMx) +{ + return TIMx->ICR2; +} + +/******************************************************************************* +* Function Name : TIM_GetPWMIPeriod +* Description : Gets the PWM Input period value. +* Input : TIMx: where x can be 0, 1 or 2 to select the TIM peripheral +* Output : None +* Return : Input Capture 1 Register value +*******************************************************************************/ +u16 TIM_GetPWMIPeriod(TIM_TypeDef *TIMx) +{ + return TIMx->ICR1; +} + +/******************************************************************************* +* Function Name : TIM_DebugCmd +* Description : Enables or disables the specified TIM peripheral Debug control. +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral +* - Newstate: new state of the TIMx Debug control. + This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_DebugCmd(TIM_TypeDef *TIMx, FunctionalState Newstate) +{ + if(Newstate == ENABLE) + { + TIMx->CR |= TIM_DBGC_Set; + } + else + { + TIMx->CR &= TIM_DBGC_Reset; + } +} + +/******************************************************************************* +* Function Name : TIM_CounterModeConfig +* Description : Specifies the Counter Mode to be used. +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. +* - TIM_CounterMode: specifies the Counter Mode to be used +* This parameter can be one of the following values: +* - TIM_CounterMode_Up: TIM Up Counting Mode +* - TIM_CounterMode_Down: TIM Down Counting Mode +* - TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1 +* - TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 +* - TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 +* Output : None +* Return : None +*******************************************************************************/ +void TIM_CounterModeConfig(TIM_TypeDef* TIMx, u16 TIM_CounterMode) +{ + /* Counter mode configuration */ + TIMx->CR &= TIM_CounterMode_Mask; + TIMx->CR |= TIM_CounterMode; +} + +/******************************************************************************* +* Function Name : TIM_ForcedOCConfig +* Description : Forces the TIM output waveform to active or inactive level. +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. +* - TIM_Channel: specifies the TIM channel to be used. +* This parameter can be one of the following values: +* - TIM_Channel_1: Timer Channel 1 is used +* - TIM_Channel_2: Timer Channel 2 is used +* - TIM_Channel_ALL: Timer Channel 1 and 2 are used +* - TIM_ForcedAction: specifies the forced Action to be set to +* the output waveform. +* This parameter can be one of the following values: +* - TIM_ForcedAction_Active: Force active level on OCxREF +* - TIM_ForcedAction_InActive: Force inactive level on +* OCxREF. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ForcedOCConfig(TIM_TypeDef* TIMx, u16 TIM_Channel,u16 TIM_ForcedAction) +{ + /* Channel 1 Forced Output Compare mode configuration */ + if(TIM_Channel == TIM_Channel_1) + { + TIMx->OMR1 &= TIM_OC1C_Mask; + TIMx->OMR1 |= TIM_ForcedAction; + } + /* Channel 2 Forced Output Compare mode configuration */ + else + { + if(TIM_Channel == TIM_Channel_2) + { + TIMx->OMR1 &= TIM_OC2C_Mask; + TIMx->OMR1 |= (TIM_ForcedAction<<8); + } + /* Channel 1 and Channel 2 Forced Output Compare mode configuration */ + else + { + TIMx->OMR1 &= TIM_OC1C_Mask & TIM_OC2C_Mask; + TIMx->OMR1 |= TIM_ForcedAction |(TIM_ForcedAction<<8); + } + } +} + +/******************************************************************************* +* Function Name : TIM_ResetCounter +* Description : Re-intializes the TIM counter and generates an update of the +* registers. +* Input : TIMx: where x can be 0, 1 or 2 to select the TIM peripheral +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ResetCounter(TIM_TypeDef* TIMx) +{ + /* Re-intialize the TIM counter */ + TIMx->CR |= TIM_COUNTER_Reset; +} + +/******************************************************************************* +* Function Name : TIM_SynchroConfig +* Description : Synchronizes two Timers in a specified mode. +* Input : - Master: specifies the peripheral master. +* This parameter can be one of the following values: +* PWM_Master, TIM0_Master, TIM1_Master or TIM2_Master. +* - Slave: specifies the peripheral slave. +* This parameter can be one of the following values: +* PWM_Slave, TIM0_Slave, TIM1_Slave or TIM2_Slave. +* - TIM_SynchroAction: specifies the synchronization Action to +* be used. +* This parameter can be one of the following values: +* - TIM_SynchroAction_Enable: The CNT_EN bit is used as TRGO +* - TIM_SynchroAction_Update: The Update event is used as TRGO +* - TIM_SynchroAction_Reset: The CNT_RST bit is used as TRGO +* - TIM_SynchroAction_OC: The OC1 signal is used as TRGO +* - TIM_SynchroMode: specifies the synchronization Mode to be used. +* This parameter can be one of the following values: +* - TIM_SynchroMode_Gated: Both start and stop of the +* counter is controlled. +* - TIM_SynchroMode_Trigger: Only the start of the +* counter is controlled. +* - TIM_SynchroMode_External: The rising edge of selected trigger +* clocks the counter. +* - TIM_SynchroMode_Reset: The rising edge of the selected trigger +* signal resets the counter and generates an update of the registers. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SynchroConfig(Master_TypeDef Master, Slave_TypeDef Slave, + u16 TIM_SynchroAction, u16 TIM_SynchroMode) +{ + switch (Slave) + { + case PWM_Slave: + { + PWM->SCR &= TIM_SME_Reset & TIM_TriggerSelection_Mask & TIM_SlaveModeSelection_Mask & + TIM_InternalTriggerSelection_Mask; + PWM->SCR |= TIM_SynchroMode | TIM_SME_Set; + + if(Master == TIM1_Master) + { + /* Set the internal trigger */ + PWM->SCR |= TIM_ITS_TIM1; + + /* Set the synchronization action */ + TIM1->CR &= TIM_MasterModeSelection_Mask; + TIM1->CR |= TIM_SynchroAction; + } + + else if(Master == TIM0_Master) + { + /* Set the internal trigger */ + PWM->SCR |= TIM_ITS_TIM0; + + /* Set the synchronization action */ + TIM0->CR &= TIM_MasterModeSelection_Mask; + TIM0->CR |= TIM_SynchroAction; + } + + else if(Master == TIM2_Master) + { + /* Set the internal trigger */ + PWM->SCR |= TIM_ITS_TIM2; + + /* Set the synchronization action */ + TIM2->CR &= TIM_MasterModeSelection_Mask; + TIM2->CR |= TIM_SynchroAction; + } + } + break; + + case TIM0_Slave: + { + TIM0->SCR &= TIM_SME_Reset & TIM_TriggerSelection_Mask & TIM_SlaveModeSelection_Mask & + TIM_InternalTriggerSelection_Mask; + TIM0->SCR |= TIM_SynchroMode | TIM_SME_Set; + + if(Master == PWM_Master) + { + /* Set the internal trigger */ + TIM0->SCR |= TIM_ITS_PWM; + + /* Set the synchronization action */ + PWM->CR &= TIM_MasterModeSelection_Mask; + PWM->CR |= TIM_SynchroAction; + } + + else if(Master == TIM1_Master) + { + /* Set the internal trigger */ + TIM0->SCR |= TIM_ITS_TIM1; + + /* Set the synchronization action */ + TIM1->CR &= TIM_MasterModeSelection_Mask; + TIM1->CR |= TIM_SynchroAction; + } + + else if(Master == TIM2_Master) + { + /* Set the internal trigger */ + TIM0->SCR |= TIM_ITS_TIM2; + + /* Set the synchronization action */ + TIM2->CR &= TIM_MasterModeSelection_Mask; + TIM2->CR |= TIM_SynchroAction; + } + } + break; + + case TIM1_Slave: + { + + TIM1->SCR &= TIM_SME_Reset & TIM_TriggerSelection_Mask & TIM_SlaveModeSelection_Mask & + TIM_InternalTriggerSelection_Mask; + TIM1->SCR |= TIM_SynchroMode | TIM_SME_Set; + + if(Master == PWM_Master) + { + /* Set the internal trigger */ + TIM1->SCR |= TIM_ITS_PWM; + + /* Set the synchronization action */ + PWM->CR &= TIM_MasterModeSelection_Mask; + PWM->CR |= TIM_SynchroAction; + } + else if(Master == TIM0_Master) + { + /* Set the internal trigger */ + TIM1->SCR |= TIM_ITS_TIM0; + + /* Set the synchronization action */ + TIM0->CR &= TIM_MasterModeSelection_Mask; + TIM0->CR |= TIM_SynchroAction; + } + + else if(Master == TIM2_Master) + { + /* Set the internal trigger */ + TIM1->SCR |= TIM_ITS_TIM2; + + /* Set the synchronization action */ + TIM2->CR &= TIM_MasterModeSelection_Mask; + TIM2->CR |= TIM_SynchroAction; + } + } + break; + + case TIM2_Slave: + { + + TIM2->SCR &= TIM_SME_Reset & TIM_TriggerSelection_Mask & TIM_SlaveModeSelection_Mask & + TIM_InternalTriggerSelection_Mask; + TIM2->SCR |= TIM_SynchroMode | TIM_SME_Set; + + if(Master == PWM_Master) + { + /* Internal trigger selection */ + TIM2->SCR |= TIM_ITS_PWM; + + /* Set the synchronization action */ + PWM->CR &= TIM_MasterModeSelection_Mask; + PWM->CR |= TIM_SynchroAction; + } + + else if(Master == TIM1_Master) + { + /* Internal trigger selection */ + TIM2->SCR |= TIM_ITS_TIM1; + + /* Set the synchronization action */ + TIM1->CR &= TIM_MasterModeSelection_Mask; + TIM1->CR |= TIM_SynchroAction; + } + + else if(Master == TIM0_Master) + { + /* Internal trigger selection */ + TIM2->SCR |= TIM_ITS_TIM0; + + /* Set the synchronization action */ + TIM0->CR &= TIM_MasterModeSelection_Mask; + TIM0->CR |= TIM_SynchroAction; + } + } + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : TIM_GetFlagStatus +* Description : Checks whether the specified TIM flag is set or not. +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. +* - TIM_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - TIM_FLAG_IC1: Input Capture 1 Flag +* - TIM_FLAG_OC1: Output Compare 1 Flag +* - TIM_FLAG_Update: Timer update Flag +* - TIM_FLAG_IC2: Input Capture 2 Flag +* - TIM_FLAG_OC2: Output Compare 2 Flag +* Output : None +* Return : The new state of TIM_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, u16 TIM_FLAG) +{ + if((TIMx->ISR & TIM_FLAG) != RESET ) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : TIM_ClearFlag +* Description : Clears the TIMx's pending flags. +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. +* - TIM_FLAG: specifies the flag bit to clear. +* This parameter can be any combination of the following values: +* - TIM_FLAG_IC1: Timer Input Capture 1 flag +* - TIM_FLAG_OC1: Timer Output Compare 1 flag +* - TIM_FLAG_Update: Timer update flag +* - TIM_FLAG_IC2: Timer Input Capture 2 flag +* - TIM_FLAG_OC2: Timer Output Compare 2 flag +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ClearFlag(TIM_TypeDef* TIMx, u16 TIM_FLAG) +{ + /* Clear the flags */ + TIMx->ISR &= ~TIM_FLAG; +} + +/******************************************************************************* +* Function Name : TIM_GetITStatus +* Description : Checks whether the specified TIM interrupt has occurred or not. +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. +* - TIM_IT: specifies the TIM interrupt source to check. +* This parameter can be one of the following values: +* - TIM_IT_IC1: Input Capture 1 interrupt +* - TIM_IT_OC1: Output Compare 1 interrupt +* - TIM_IT_Update: Timer update interrupt +* - TIM_IT_GlobalUpdate: Timer global update interrupt +* - TIM_IT_IC2: Input Capture 2 interrupt +* - TIM_IT_OC2: Output Compare 2 interrupt +* Output : None +* Return : The new state of TIM_IT(SET or RESET). +*******************************************************************************/ +ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, u16 TIM_IT) +{ + u16 TIM_IT_Check = 0; + + /* Calculates the pending bits to be checked */ + TIM_IT_Check = TIM_IT & TIM_IT_Clear_Mask; + + if((TIMx->ISR & TIM_IT_Check) != RESET ) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : TIM_ClearITPendingBit +* Description : Clears the TIM's interrupt pending bits. +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. +* - TIM_IT: specifies the interrupt pending bit to clear. +* This parameter can be one of the following values: +* - TIM_IT_IC1: Input Capture 1 Interrupt +* - TIM_IT_OC1: Output Compare 1 Interrupt +* - TIM_IT_Update: Timer update Interrupt +* - TIM_IT_GlobalUpdate: Timer global update Interrupt +* - TIM_IT_IC2: Input Capture 2 Interrupt +* - TIM_IT_OC2: Output Compare 2 Interrupt +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, u16 TIM_IT) +{ + u16 TIM_IT_Clear = 0; + + /* Calculate the pending bits to be cleared */ + TIM_IT_Clear = TIM_IT & TIM_IT_Clear_Mask; + + /* Clear the pending bits */ + TIMx->ISR &= ~TIM_IT_Clear; +} + +/******************************************************************************* +* Function Name : OCM_ModuleConfig +* Description : Output Compare Module configuration +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral +* - TIM_InitStruct: pointer to a TIM_InitTypeDef structure that +* contains the configuration information for the specified TIM +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +static void OCM_ModuleConfig(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct) +{ + u16 TIM_OCControl = 0x0000; + + if(TIM_InitStruct->TIM_Mode == TIM_Mode_OCTiming) + { + TIM_OCControl = TIM_OCControl_OCTiming; + } + else + { + if((TIM_InitStruct->TIM_Mode == TIM_Mode_OCActive) || + (TIM_InitStruct->TIM_Mode == TIM_Mode_OPM_Active)) + { + TIM_OCControl = TIM_OCControl_OCActive; + } + else + { + if(TIM_InitStruct->TIM_Mode == TIM_Mode_OCInactive) + { + TIM_OCControl = TIM_OCControl_OCInactive; + } + else + { + if((TIM_InitStruct->TIM_Mode == TIM_Mode_OCToggle) || + (TIM_InitStruct->TIM_Mode == TIM_Mode_OPM_Toggle)) + { + TIM_OCControl = TIM_OCControl_OCToggle; + } + else + { + TIM_OCControl = TIM_OCControl_PWM; + + } + } + } + } + + if(TIM_InitStruct->TIM_Channel == TIM_Channel_1) + { + /* Configure Channel 1 on Output Compare mode */ + TIMx->OMR1 &= TIM_OC1C_Mask; + TIMx->OMR1 |= TIM_OCControl|TIM_OC1_Enable; + TIMx->OMR1 |= TIM_PLD1_Set; + TIMx->OCR1 = TIM_InitStruct->TIM_Pulse1; + + /* Set the OC1 wave polarity */ + if(TIM_InitStruct->TIM_Polarity1 == TIM_Polarity1_Low) + { + TIMx->OMR1 |= TIM_OC1P_Set; + } + else + { + TIMx->OMR1 &= TIM_OC1P_Reset; + } + } + else + { + if(TIM_InitStruct->TIM_Channel == TIM_Channel_2) + { + /* Configure Channel 2 on Output Compare mode */ + TIMx->OMR1 &= TIM_OC2C_Mask; + TIMx->OMR1 |= TIM_OCControl<<8|TIM_OC2_Enable; + TIMx->OMR1 |= TIM_PLD2_Set; + TIMx->OCR2 = TIM_InitStruct->TIM_Pulse2; + + /* Set the OCB wave polarity */ + if(TIM_InitStruct->TIM_Polarity2 == TIM_Polarity2_Low) + { + TIMx->OMR1 |= TIM_OC2P_Set; + } + else + { + TIMx->OMR1 &= TIM_OC2P_Reset; + } + } + /* Configure Channel 1 and Channel 2 on Output Compare mode */ + else + { + TIMx->OMR1 &= TIM_OC1C_Mask & TIM_OC2C_Mask; + TIMx->OMR1 |= TIM_OCControl|(TIM_OCControl<<8)|TIM_OC1_Enable|TIM_OC2_Enable| + TIM_PLD1_Set|TIM_PLD2_Set; + + TIMx->OCR1 = TIM_InitStruct->TIM_Pulse1; + TIMx->OCR2 = TIM_InitStruct->TIM_Pulse2; + + /* Set the OC1 wave polarity */ + if(TIM_InitStruct->TIM_Polarity1 == TIM_Polarity1_Low) + { + TIMx->OMR1 |= TIM_OC1P_Set; + } + else + { + TIMx->OMR1 &= TIM_OC1P_Reset; + } + + /* Set the OC2 wave polarity */ + if(TIM_InitStruct->TIM_Polarity2 == TIM_Polarity2_Low) + { + TIMx->OMR1 |= TIM_OC2P_Set; + } + else + { + TIMx->OMR1 &= TIM_OC2P_Reset; + } + } + } +} + +/******************************************************************************* +* Function Name : ICAP_ModuleConfig +* Description : Input Capture Module configuration +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral +* - TIM_InitStruct: pointer to a TIM_InitTypeDef structure that +* contains the configuration information for the specified TIM +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +static void ICAP_ModuleConfig(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct) +{ + if(TIM_InitStruct->TIM_Mode == TIM_Mode_PWMI) + { /* PWM input mode configuration */ + TIMx->SCR |= TIM_TS_IC1_Set|TIM_SMS_RESETCLK_Set|TIM_SME_Set; + + /* Channel 1 and channel 2 input selection */ + if(TIM_InitStruct->TIM_PWMI_ICSelection == TIM_PWMI_ICSelection_TI1) + { + TIMx->IMCR &= TIM_IC1S_Reset; + TIMx->IMCR |= TIM_IC2S_Set; + } + else + { + TIMx->IMCR |= TIM_IC1S_Set; + TIMx->IMCR &= TIM_IC2S_Reset; + } + + /* Channel polarity */ + if(TIM_InitStruct->TIM_PWMI_ICPolarity == TIM_PWMI_ICPolarity_Rising) + { + TIMx->IMCR &= TIM_IC1P_Reset; + TIMx->IMCR |= TIM_IC2P_Set; + } + else + { + TIMx->IMCR |= TIM_IC1P_Set; + TIMx->IMCR &= TIM_IC2P_Reset; + } + + /* Input capture Enable */ + TIMx->IMCR |= TIM_IC1_Enable |TIM_IC2_Enable; + } + else + { + if(TIM_InitStruct->TIM_Channel == TIM_Channel_1) + { + /* Input Capture 1 mode configuration */ + TIMx->SCR &= TIM_TriggerSelection_Mask & TIM_SlaveModeSelection_Mask; + TIMx->SCR |= TIM_TS_IC1_Set|TIM_SMS_RESETCLK_Set|TIM_SME_Set; + + /* Channel 1 input selection */ + if(TIM_InitStruct->TIM_IC1Selection == TIM_IC1Selection_TI1) + { + TIMx->IMCR &= TIM_IC1S_Reset; + } + else + { + TIMx->IMCR |= TIM_IC1S_Set; + } + /* Channel 1 polarity */ + if(TIM_InitStruct->TIM_IC1Polarity == TIM_IC1Polarity_Rising) + { + TIMx->IMCR &= TIM_IC1P_Reset; + } + else + { + TIMx->IMCR |= TIM_IC1P_Set; + } + + /* Input capture Enable */ + TIMx->IMCR |= TIM_IC1_Enable; + } + else + { + /* Input Capture 2 mode configuration */ + TIMx->SCR &= (TIM_TriggerSelection_Mask & TIM_SlaveModeSelection_Mask); + TIMx->SCR |= TIM_TS_IC2_Set|TIM_SMS_RESETCLK_Set|TIM_SME_Set; + + /* Channel 2 input selection */ + if(TIM_InitStruct->TIM_IC2Selection == TIM_IC2Selection_TI2) + { + TIMx->IMCR &= TIM_IC2S_Reset; + } + else + { + TIMx->IMCR |= TIM_IC2S_Set; + } + + /* Channel 2 polarity */ + if(TIM_InitStruct->TIM_IC2Polarity == TIM_IC2Polarity_Rising) + { + TIMx->IMCR &= TIM_IC2P_Reset; + } + else + { + TIMx->IMCR |= TIM_IC2P_Set; + } + + /* Input capture Enable */ + TIMx->IMCR |= TIM_IC2_Enable; + } + } +} + +/******************************************************************************* +* Function Name : Encoder_ModeConfig +* Description : Encoder Mode configuration +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral +* - TIM_InitStruct: pointer to a TIM_InitTypeDef structure that +* contains the configuration information for the specified TIM +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +static void Encoder_ModeConfig(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct) +{ + /* Set Encoder mode */ + TIMx->SCR &= TIM_Encoder_Mask; + + if(TIM_InitStruct->TIM_Mode == TIM_Mode_Encoder1) + { + TIMx->SCR |= TIM_Encoder1_Set; + } + else if (TIM_InitStruct->TIM_Mode == TIM_Mode_Encoder2) + { + TIMx->SCR |= TIM_Encoder2_Set; + } + else + { + TIMx->SCR |= TIM_Encoder3_Set; + } + + /* Channel 1 input selection */ + if(TIM_InitStruct->TIM_IC1Selection == TIM_IC1Selection_TI2) + { + TIMx->IMCR |= TIM_IC1S_Set; + } + else + { + TIMx->IMCR &= TIM_IC1S_Reset; + } + + /* Channel 2 input selection */ + if(TIM_InitStruct->TIM_IC2Selection == TIM_IC2Selection_TI1) + { + TIMx->IMCR |= TIM_IC2S_Set; + } + else + { + TIMx->IMCR &= TIM_IC2S_Reset; + } + + /* Channel 1 polarity */ + if(TIM_InitStruct->TIM_IC1Polarity == TIM_IC1Polarity_Falling) + { + TIMx->IMCR |= TIM_IC1P_Set; + } + else + { + TIMx->IMCR &= TIM_IC1P_Reset; + } + + /* Channel 2 polarity */ + if(TIM_InitStruct->TIM_IC2Polarity == TIM_IC2Polarity_Falling) + { + TIMx->IMCR |= TIM_IC2P_Set; + } + else + { + TIMx->IMCR &= TIM_IC2P_Reset; + } +} +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_uart.c b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_uart.c new file mode 100644 index 000000000..5494ff335 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_uart.c @@ -0,0 +1,599 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_uart.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the UART software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_uart.h" +#include "75x_mrcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* UART LIN Mask */ +#define UART_LIN_Disable_Mask 0xFEFF /* LIN Disable Mask */ +#define UART_LIN_Enable_Mask 0x0100 /* LIN Enable Mask */ + +/* UART Mask */ +#define UART_Enable_Mask 0x0001 /* UART Enable Mask */ +#define UART_Disable_Mask 0xFFFE /* UART Disable Mask */ + +/* UART LoopBack */ +#define UART_LoopBack_Disable_Mask 0xFF7F/* LoopBack Disable Mask */ +#define UART_LoopBack_Enable_Mask 0x0080/* LoopBack Enable Mask */ + +#define UART_WordLength_Mask 0xFF9F /* UART Word Length Mask */ +#define UART_Parity_Mask 0xFF79 /* UART Parity Mask */ +#define UART_HardwareFlowControl_Mask 0x3FFF /* UART Hardware Flow Control Mask */ +#define UART_TxRxFIFOLevel_Mask 0xFFC0 /* UART Tx Rx FIFO Level Mask */ +#define UART_LINBreakLength_Mask 0xE1FF /* UART LIN Break Length Mask */ +#define UART_BreakChar_Mask 0x0001 /* UART Break Character send Mask */ +#define UART_FLAG_Mask 0x1F /* UART Flag Mask */ +#define UART_Mode_Mask 0xFCFF /* UART Mode Mask */ +#define UART_RTSSET_Mask 0xF7FF /* RTS signal is high */ +#define UART_RTSRESET_Mask 0x0800 /* RTS signal is low */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : UART_DeInit +* Description : Deinitializes the UARTx peripheral registers to their default +* reset values. +* Input : UARTx: where x can be 0,1 or 2 to select the UART peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void UART_DeInit(UART_TypeDef* UARTx) +{ + /* Reset the UARTx registers values */ + if(UARTx == UART0) + { + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_UART0,ENABLE); + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_UART0,DISABLE); + } + else if(UARTx == UART1) + { + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_UART1,ENABLE); + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_UART1,DISABLE); + } + else if(UARTx == UART2) + { + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_UART2,ENABLE); + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_UART2,DISABLE); + } +} + +/******************************************************************************* +* Function Name : UART_Init +* Description : Initializes the UARTx peripheral according to the specified +* parameters in the UART_InitStruct . +* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral. +* - UART_InitStruct: pointer to a UART_InitTypeDef structure +* that contains the configuration information for the +* specified UART peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef* UART_InitStruct) +{ + + u32 APBClock = 0; + u32 IntegerDivider = 0; + u32 FractionalDivider = 0; + MRCC_ClocksTypeDef MRCC_ClocksStatus; + + /* Clear the WLEN bits */ + UARTx->LCR &= UART_WordLength_Mask; + /* Set the WLEN bits according to UART_WordLength value */ + UARTx->LCR |= UART_InitStruct->UART_WordLength; + + /* Choose Stop Bits */ + if(UART_InitStruct->UART_StopBits == UART_StopBits_1) + { + /* One Stop Bit */ + UARTx->LCR &= UART_StopBits_1; + } + else + { + /* Two Stop Bits */ + UARTx->LCR |= UART_StopBits_2; + } + + /* Clear SPS, EPS and PEN bits */ + UARTx->LCR &= UART_Parity_Mask; + /* Set PS, EPS and PEN bits according to UART_Parity value */ + UARTx->LCR |= UART_InitStruct->UART_Parity; + + /* Configure the BaudRate --------------------------------------------------*/ + /* Get the APB frequency */ + MRCC_GetClocksStatus(&MRCC_ClocksStatus); + APBClock = MRCC_ClocksStatus.PCLK_Frequency; + + /* Determine the integer part */ + IntegerDivider = ((100) * (APBClock) / (16 * (UART_InitStruct->UART_BaudRate))); + UARTx->IBRD = IntegerDivider / 100; + + /* Determine the fractional part */ + FractionalDivider = IntegerDivider - (100 * (UARTx->IBRD)); + UARTx->FBRD = ((((FractionalDivider * 64) + 50) / 100)); + + /* Choose the Hardware Flow Control */ + /* Clear RTSEn and CTSEn bits */ + UARTx->CR &= UART_HardwareFlowControl_Mask; + /* Set RTSEn and CTSEn bits according to UART_HardwareFlowControl value */ + UARTx->CR |= UART_InitStruct->UART_HardwareFlowControl; + + /* Configure the UART mode */ + /* Clear TXE and RXE bits */ + UARTx->CR &= UART_Mode_Mask; + /* Set TXE and RXE bits according to UART_Mode value */ + UARTx->CR |= UART_InitStruct->UART_Mode; + + /* Enable or disable the FIFOs */ + /* Set the FIFOs Levels */ + if(UART_InitStruct->UART_FIFO == UART_FIFO_Enable) + { + /* Enable the FIFOs */ + UARTx->LCR |= UART_FIFO_Enable; + + /* Clear TXIFLSEL and RXIFLSEL bits */ + UARTx->IFLS &= UART_TxRxFIFOLevel_Mask; + + /* Set RXIFLSEL bits according to UART_RxFIFOLevel value */ + UARTx->IFLS |= (UART_InitStruct->UART_RxFIFOLevel << 3); + + /* Set TXIFLSEL bits according to UART_TxFIFOLevel value */ + UARTx->IFLS |= UART_InitStruct->UART_TxFIFOLevel; + } + else + { + /* Disable the FIFOs */ + UARTx->LCR &= UART_FIFO_Disable; + } +} + +/******************************************************************************* +* Function Name : UART_StructInit +* Description : Fills each UART_InitStruct member with its default value. +* Input : UART_InitStruct: pointer to a UART_InitTypeDef structure which +* will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void UART_StructInit(UART_InitTypeDef* UART_InitStruct) +{ + /* UART_InitStruct members default value */ + UART_InitStruct->UART_WordLength = UART_WordLength_8D; + UART_InitStruct->UART_StopBits = UART_StopBits_1; + UART_InitStruct->UART_Parity = UART_Parity_Odd ; + UART_InitStruct->UART_BaudRate = 9600; + UART_InitStruct->UART_HardwareFlowControl = UART_HardwareFlowControl_None; + UART_InitStruct->UART_Mode = UART_Mode_Tx_Rx; + UART_InitStruct->UART_FIFO = UART_FIFO_Enable; + UART_InitStruct->UART_TxFIFOLevel = UART_FIFOLevel_1_2; + UART_InitStruct->UART_RxFIFOLevel = UART_FIFOLevel_1_2; +} + +/******************************************************************************* +* Function Name : UART_Cmd +* Description : Enables or disables the specified UART peripheral. +* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral +* - NewState: new state of the UARTx peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void UART_Cmd(UART_TypeDef* UARTx, FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Enable the selected UART by setting the UARTEN bit in the CR register */ + UARTx->CR |= UART_Enable_Mask; + } + else + { + /* Disable the selected UART by clearing the UARTEN bit in the CR register */ + UARTx->CR &= UART_Disable_Mask; + } +} + +/******************************************************************************* +* Function Name : UART_ITConfig +* Description : Enables or disables the specified UART interrupts. +* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral +* - UART_IT: specifies the UART interrupts sources to be +* enabled or disabled. This parameter can be any combination +* of the following values: +* - UART_IT_OverrunError: Overrun Error interrupt +* - UART_IT_BreakError: Break Error interrupt +* - UART_IT_ParityError: Parity Error interrupt +* - UART_IT_FrameError: Frame Error interrupt +* - UART_IT_ReceiveTimeOut: Receive Time Out interrupt +* - UART_IT_Transmit: Transmit interrupt +* - UART_IT_Receive: Receive interrupt +* - UART_IT_CTS: CTS interrupt +* - NewState: new state of the UARTx peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void UART_ITConfig(UART_TypeDef* UARTx, u16 UART_IT, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enables the selected interrupts */ + UARTx->IMSC |= UART_IT; + } + else + { + /* Disables the selected interrupts */ + UARTx->IMSC &= ~UART_IT; + } +} + +/******************************************************************************* +* Function Name : UART_DMAConfig +* Description : Configures the UART0 DMA interface. +* Input : - UART0_DMAtransfer : specifies the configuration of DMA request. +* This parameter can be: +* - UART0_DMATransfer_Single: Single DMA transfer +* - UART0_DMATransfer_Burst: Burst DMA transfer +* - UART0_DMAOnError: specifies the DMA on error request. +* This parameter can be: +* - UART0_DMAOnError_Enable: DMA receive request enabled +* when the UART error interrupt is asserted. +* - UART0_DMAOnError_Disable: DMA receive request disabled +* when the UART error interrupt is asserted. +* Output : None +* Return : None +*******************************************************************************/ +void UART_DMAConfig(u16 UART0_DMATransfer, u16 UART0_DMAOnError) +{ + if(UART0_DMATransfer == UART0_DMATransfer_Single) + { + /* Configure the DMA request from the UART0 as single transfer */ + UART0->DMACR &= UART0_DMATransfer_Single; + } + else + { + UART0->DMACR |= UART0_DMATransfer_Burst; + } + + if(UART0_DMAOnError == UART0_DMAOnError_Enable) + { + UART0->DMACR &= UART0_DMAOnError_Enable; + } + else + { + UART0->DMACR |= UART0_DMAOnError_Disable; + } +} + +/******************************************************************************* +* Function Name : UART_DMACmd +* Description : Enables or disables the UART0’s DMA interface. +* Input : - UART0_DMAReq: specifies the DMA request. +* This parameter can be: +* - UART0_DMAReq_Tx: Transmit DMA request +* - UART0_DMAReq_Rx: Receive DMA request +* - NewState: new state of the UART0’s DMA request. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void UART_DMACmd(u16 UART0_DMAReq, FunctionalState NewState) +{ + if(UART0_DMAReq == UART0_DMAReq_Tx) + { + if(NewState == ENABLE) + { + UART0->DMACR |= UART0_DMAReq_Tx; + } + else + { + UART0->DMACR &= ~UART0_DMAReq_Tx; + } + } + else + { + if(NewState == ENABLE) + { + UART0->DMACR |= UART0_DMAReq_Rx; + } + else + { + UART0->DMACR &= ~UART0_DMAReq_Rx; + } + } +} + +/******************************************************************************* +* Function Name : UART_LoopBackConfig +* Description : Enables or disables LoopBack mode in UARTx. +* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral +* - NewState: new state of the UARTx’s LoopBack mode. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void UART_LoopBackConfig(UART_TypeDef* UARTx, FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Enable the LoopBack mode of the specified UART */ + UARTx->CR |= UART_LoopBack_Enable_Mask; + } + else + { + /* Disable the LoopBack mode of the specified UART */ + UARTx->CR &= UART_LoopBack_Disable_Mask; + } +} + +/******************************************************************************* +* Function Name : UART_LINConfig +* Description : Sets the LIN break length. +* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral. +* - UART_LINBreakLength: Break length value. +* This parameter can be: +* - UART_LINBreakLength_10: 10 low bits +* - UART_LINBreakLength_11: 11 low bits +* - UART_LINBreakLength_12: 12 low bits +* - UART_LINBreakLength_13: 13 low bits +* - UART_LINBreakLength_14: 14 low bits +* - UART_LINBreakLength_15: 15 low bits +* - UART_LINBreakLength_16: 16 low bits +* - UART_LINBreakLength_17: 17 low bits +* - UART_LINBreakLength_18: 18 low bits +* - UART_LINBreakLength_19: 19 low bits +* - UART_LINBreakLength_20: 20 low bits +* Output : None +* Return : None +*******************************************************************************/ +void UART_LINConfig(UART_TypeDef* UARTx, u16 UART_LINBreakLength) +{ + /* Clear LBKLEN bits */ + UARTx->LCR &= UART_LINBreakLength_Mask; + + /* Set LBKLEN bits according to UART_LINBreakLength value */ + UARTx->LCR |= UART_LINBreakLength; +} + +/******************************************************************************* +* Function Name : UART_LINCmd +* Description : Enables or disables LIN master mode in UARTx. +* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral +* - NewState: new state of the UARTx’s LIN interface. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void UART_LINCmd(UART_TypeDef* UARTx, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable the LIN mode of the specified UART */ + UARTx->LCR |= UART_LIN_Enable_Mask; + } + else + { + /* Disable the LIN mode of the specified UART */ + UARTx->LCR &= UART_LIN_Disable_Mask; + } +} + +/******************************************************************************* +* Function Name : UART_SendData +* Description : Transmits a signle Byte of data through the UARTx peripheral. +* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral. +* - Data: the byte to transmit +* Output : None +* Return : None +*******************************************************************************/ +void UART_SendData(UART_TypeDef* UARTx, u8 Data) +{ + /* Transmit one byte */ + UARTx->DR = Data; +} + +/******************************************************************************* +* Function Name : UART_ReceiveData +* Description : Returns the most recent received Byte by the UARTx peripheral. +* Input : UARTx: where x can be 0,1 or 2 to select the UART peripheral. +* Output : None +* Return : The received data +*******************************************************************************/ +u8 UART_ReceiveData(UART_TypeDef* UARTx) +{ + /* Receive one byte */ + return ((u8)UARTx->DR); +} + +/******************************************************************************* +* Function Name : UART_SendBreak +* Description : Transmits break characters. +* Input : UARTx: where x can be 0,1 or 2 to select the UART peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void UART_SendBreak(UART_TypeDef* UARTx) +{ + /* Send break characters */ + UARTx->BKR |= UART_BreakChar_Mask; +} + +/******************************************************************************* +* Function Name : UART_RTSConfig +* Description : Sets or Resets the RTS signal +* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral. +* - RTSState: new state of the RTS signal. +* This parameter can be: RTSSET or RTSRESET +* Output : None +* Return : None +*******************************************************************************/ +void UART_RTSConfig(UART_TypeDef* UARTx, UART_RTSTypeDef RTSState) +{ + if(RTSState == RTSRESET) + { + UARTx->CR |= UART_RTSRESET_Mask; + } + else if(RTSState == RTSSET) + { + UARTx->CR &= UART_RTSSET_Mask; + } +} + +/******************************************************************************* +* Function Name : UART_GetFlagStatus +* Description : Checks whether the specified UART flag is set or not. +* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral +* - UART_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - UART_FLAG_OverrunError: Overrun error flag +* - UART_FLAG_Break: break error flag +* - UART_FLAG_ParityError: parity error flag +* - UART_FLAG_FrameError: frame error flag +* - UART_FLAG_TxFIFOEmpty: Transmit FIFO Empty flag +* - UART_FLAG_RxFIFOFull: Receive FIFO Full flag +* - UART_FLAG_TxFIFOFull: Transmit FIFO Full flag +* - UART_FLAG_RxFIFOEmpty: Receive FIFO Empty flag +* - UART_FLAG_Busy: Busy flag +* - UART_FLAG_CTS: CTS flag +* - UART_RawIT_OverrunError: Overrun Error interrupt flag +* - UART_RawIT_BreakError: Break Error interrupt flag +* - UART_RawIT_ParityError: Parity Error interrupt flag +* - UART_RawIT_FrameError: Frame Error interrupt flag +* - UART_RawIT_ReceiveTimeOut: ReceiveTimeOut interrupt flag +* - UART_RawIT_Transmit: Transmit interrupt flag +* - UART_RawIT_Receive: Receive interrupt flag +* - UART_RawIT_CTS: CTS interrupt flag +* Output : None +* Return : The new state of UART_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, u16 UART_FLAG) +{ + u32 UARTReg = 0, FlagPos = 0; + u32 StatusReg = 0; + + /* Get the UART register index */ + UARTReg = UART_FLAG >> 5; + + /* Get the flag position */ + FlagPos = UART_FLAG & UART_FLAG_Mask; + + if(UARTReg == 1) /* The flag to check is in RSR register */ + { + StatusReg = UARTx->RSR; + } + else if (UARTReg == 2) /* The flag to check is in FR register */ + { + StatusReg = UARTx->FR; + } + else if(UARTReg == 3) /* The flag to check is in RIS register */ + { + StatusReg = UARTx->RIS; + } + + if((StatusReg & (1 << FlagPos))!= RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : UART_ClearFlag +* Description : Clears the UARTx’s pending flags. +* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral. +* - UART_FLAG: specifies the flag to clear. +* This parameter can be one of the following values: +* - UART_FLAG_OverrunError: Overrun error flag +* - UART_FLAG_Break: break error flag +* - UART_FLAG_ParityError: parity error flag +* - UART_FLAG_FrameError: frame error flag +* Output : None +* Return : None +*******************************************************************************/ +void UART_ClearFlag(UART_TypeDef* UARTx, u16 UART_FLAG) +{ + u8 FlagPos = 0; + + /* Get the flag position */ + FlagPos = UART_FLAG & UART_FLAG_Mask; + + /* Clear the sepecified flag */ + UARTx->RSR &= ~(1 << FlagPos); +} + +/******************************************************************************* +* Function Name : UART_GetITStatus +* Description : Checks whether the specified UART interrupt has occurred or not. +* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral. +* - UART_IT: specifies the interrupt source to check. +* This parameter can be one of the following values: +* - UART_IT_OverrunError: Overrun Error interrupt +* - UART_IT_BreakError: Break Error interrupt +* - UART_IT_ParityError: Parity Error interrupt +* - UART_IT_FrameError: Frame Error interrupt +* - UART_IT_ReceiveTimeOut: Receive Time Out interrupt +* - UART_IT_Transmit: Transmit interrupt +* - UART_IT_Receive: Receive interrupt +* - UART_IT_CTS: CTS interrupt +* Output : None +* Return : The new state of UART_IT (SET or RESET). +*******************************************************************************/ +ITStatus UART_GetITStatus(UART_TypeDef* UARTx, u16 UART_IT) +{ + if((UARTx->MIS & UART_IT) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : UART_ClearITPendingBit +* Description : Clears the UARTx’s interrupt pending bits. +* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral. +* - UART_IT: specifies the interrupt pending bit to clear. +* More than one interrupt can be cleared using the “|” operator. +* This parameter can be: +* - UART_IT_OverrunError: Overrun Error interrupt +* - UART_IT_BreakError: Break Error interrupt +* - UART_IT_ParityError: Parity Error interrupt +* - UART_IT_FrameError: Frame Error interrupt +* - UART_IT_ReceiveTimeOut: Receive Time Out interrupt +* - UART_IT_Transmit: Transmit interrupt +* - UART_IT_Receive: Receive interrupt +* - UART_IT_CTS: CTS interrupt +* Output : None +* Return : None +*******************************************************************************/ +void UART_ClearITPendingBit(UART_TypeDef* UARTx, u16 UART_IT) +{ + /* Clear the specified interrupt */ + UARTx->ICR = UART_IT; +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_wdg.c b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_wdg.c new file mode 100644 index 000000000..812d627a9 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_wdg.c @@ -0,0 +1,244 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_wdg.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the WDG software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_wdg.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Registers reset value */ +#define WDG_Preload_Mask 0xFFFF +#define WDG_Prescaler_Mask 0xFF + +/* WDG Start/Stop counter */ +#define WDG_Counter_Start_Mask 0x0002 +#define WDG_Counter_Stop_Mask 0xFFFD + +/* WDG Sequence */ +#define WDG_KeyValue1_Mask 0xA55A +#define WDG_KeyValue2_Mask 0x5AA5 + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/****************************************************************************** +* Function Name : WDG_DeInit +* Description : Deinitializes the WDG peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void WDG_DeInit(void) +{ + /* Reset all the WDG registers */ + WDG->CR = 0x0000; + WDG->PR = 0x00FF; + WDG->VR = 0xFFFF; + WDG->CNT = 0xFFFF; + WDG->SR = 0x0000; + WDG->MR = 0x0000; + WDG->KR = 0x0000; +} + +/******************************************************************************* +* Function Name : WDG_Init +* Description : Initializes WDG peripheral according to the specified +* parameters in the WDG_InitStruct. +* Input : WDG_InitStruct: pointer to a WDG_InitTypeDef structure that +* contains the configuration information for the WDG peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void WDG_Init(WDG_InitTypeDef* WDG_InitStruct) +{ + /* Configure WDG Prescaler register value */ + WDG->PR = WDG_InitStruct->WDG_Prescaler; + + /* Configure WDG Pre-load register value */ + WDG->VR = WDG_InitStruct->WDG_Preload ; + + if(WDG_InitStruct->WDG_Mode == WDG_Mode_WDG) + { + /* Select WDG mode */ + WDG->CR |= WDG_Mode_WDG ; + } + else + { + /* Select Timer mode */ + WDG->CR &= WDG_Mode_Timer; + } +} + +/******************************************************************************* +* Function Name : WDG_StructInit +* Description : Fills each WDG_InitStruct member with its default value. +* Input : WDG_InitStruct : pointer to a WDG_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void WDG_StructInit(WDG_InitTypeDef *WDG_InitStruct) +{ + /* Initialize mode */ + WDG_InitStruct->WDG_Mode = WDG_Mode_Timer; + + /* Initialize Preload */ + WDG_InitStruct->WDG_Preload = WDG_Preload_Mask ; + + /* Initialize Prescaler */ + WDG_InitStruct->WDG_Prescaler = WDG_Prescaler_Mask; +} + +/******************************************************************************* +* Function Name : WDG_Cmd +* Description : Enables or disables the WDG peripheral. +* Input : NewState: new state of the WDG peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void WDG_Cmd(FunctionalState NewState) +{ + if((WDG->CR & WDG_Mode_WDG) == 0) + { + /* Timer mode */ + if(NewState == ENABLE) + { + /* Start timer by setting SC bit in Control register */ + WDG->CR |= WDG_Counter_Start_Mask; + } + else + { + /* Stop timer by clearing SC bit in Control register */ + WDG->CR &= WDG_Counter_Stop_Mask; + } + } + else + { + /* Watchdog mode */ + if(NewState == ENABLE) + { + WDG->KR = WDG_KeyValue1_Mask; + WDG->KR = WDG_KeyValue2_Mask; + } + } +} + +/******************************************************************************* +* Function Name : WDG_ITConfig +* Description : Enables or disables the WDG End of Count(EC) interrupt. +* Input : Newstate: new state of the WDG End of Count(EC) interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void WDG_ITConfig(FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable the End of Count interrupt */ + WDG->MR |= WDG_IT_EC; + } + else + { + /* Disable the End of Count interrupt */ + WDG->MR &= ~WDG_IT_EC; + } +} + +/******************************************************************************* +* Function Name : WDG_GetCounter +* Description : Gets the WDG’s current counter value. +* Input : None +* Output : None +* Return : The WDG current counter value +*******************************************************************************/ +u16 WDG_GetCounter(void) +{ + return WDG->CNT; +} + +/******************************************************************************* +* Function Name : WDG_GetFlagStatus +* Description : Checks whether the WDG End of Count(EC) flag is set or not. +* Input : None +* Output : None +* Return : The new state of WDG End of Count(EC) flag (SET or RESET). +*******************************************************************************/ +FlagStatus WDG_GetFlagStatus(void) +{ + if((WDG->SR & WDG_FLAG_EC) != RESET ) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : WDG_ClearFlag +* Description : Clears the WDG’s End of Count(EC) pending flag. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void WDG_ClearFlag(void) +{ + /* Clear the EC pending bit */ + WDG->SR &= ~WDG_FLAG_EC; +} + +/******************************************************************************* +* Function Name : WDG_GetITStatus +* Description : Checks whether the WDG End of Count(EC) interrupt has +* occurred or not. +* Input : None +* Output : None +* Return : The new state of WDG End of Count(EC) interrupt (SET or RESET). +*******************************************************************************/ +ITStatus WDG_GetITStatus(void) +{ + if(((WDG->SR & WDG_IT_EC) != RESET )&&((WDG->MR & WDG_IT_EC) != RESET )) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : WDG_ClearITPendingBit +* Description : Clears the WDG's End of Count(EC) interrupt pending bit. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void WDG_ClearITPendingBit(void) +{ + /* Clear the EC pending bit */ + WDG->SR &= ~WDG_IT_EC; +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/lcd.c b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/lcd.c new file mode 100644 index 000000000..3436bd22d --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_GCC/STLibrary/src/lcd.c @@ -0,0 +1,1403 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : lcd.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file includes the LCD driver for GXM12232-2SL liquid +* Crystal Display Module of STR75x-EVAL. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "lcd.h" + +/* Private typedef -----------------------------------------------------------*/ + + /* Peripherals InitStructure define */ +GPIO_InitTypeDef GPIO_InitStructure; + +/* Private define ------------------------------------------------------------*/ +#define LCD_GPIO_Pins 0x3FC00 +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + /* Global variable to set the written text color: used for LCD_Printf */ + TextColorMode_TypeDef TextMode = BlackText; + + /* ASCII Table: each character is 7 column (7dots large) on two pages (16dots high) */ + /* 7 column character: Two 8bit data to display one column*/ + const u8 AsciiDotsTable[1778] = { + /* ASCII 0 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 1 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 2 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 3 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 4 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 5 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 6 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 7 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 8 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 9 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + /* ASCII 10 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + /* ASCII 11 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 12 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 13 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + /* ASCII 14 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 15 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 16 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 17 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 18 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 19 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 20 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 21 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 22 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 23 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 24 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 25 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 26 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 27 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 28 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + /* ASCII 29 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + /* ASCII 30 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + /* ASCII 31 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + /* ASCII 32 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + /* ASCII 33 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x13,0xe0,0x00,0x00,0x00,0x00,0x00,0x00, + /* ASCII 34 */ 0x00,0x00,0x00,0xe0,0x00,0x20,0x00,0x00,0x00,0xe0,0x00,0x20,0x00,0x00, + /* ASCII 35 */ 0x00,0x00,0x35,0x00,0x0f,0x80,0x35,0x60,0x0f,0x80,0x05,0x60,0x00,0x00, + /* ASCII 36 */ 0x00,0x00,0x0d,0x80,0x0a,0x40,0x3a,0x60,0x06,0x40,0x00,0x00,0x00,0x00, + /* ASCII 37 */ 0x00,0x00,0x02,0x40,0x02,0xa0,0x0a,0x40,0x15,0x00,0x09,0x00,0x00,0x00, + /* ASCII 38 */ 0x00,0x00,0x0c,0x00,0x13,0x00,0x14,0x80,0x08,0x80,0x14,0x00,0x00,0x00, + /* ASCII 39 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xe0,0x00,0x00,0x00,0x00,0x00,0x00, + /* ASCII 40 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x1f,0x80,0x60,0x60,0x00,0x00,0x00,0x00, + /* ASCII 41 */ 0x00,0x00,0x00,0x00,0x60,0x60,0x1f,0x80,0x00,0x00,0x00,0x00,0x00,0x00, + /* ASCII 42 */ 0x00,0x00,0x00,0x40,0x03,0x40,0x00,0xe0,0x03,0x40,0x00,0x40,0x00,0x00, + /* ASCII 43 */ 0x02,0x00,0x02,0x00,0x02,0x00,0x1f,0xc0,0x02,0x00,0x02,0x00,0x02,0x00, + /* ASCII 44 */ 0x00,0x00,0x00,0x00,0x60,0x00,0x38,0x00,0x08,0x00,0x00,0x00,0x00,0x00, + /* ASCII 45 */ 0x00,0x00,0x02,0x00,0x02,0x00,0x02,0x00,0x02,0x00,0x02,0x00,0x00,0x00, + /* ASCII 46 */ 0x00,0x00,0x00,0x00,0x18,0x00,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + /* ASCII 47 */ 0x00,0x00,0x20,0x00,0x18,0x00,0x06,0x00,0x01,0x80,0x00,0x60,0x00,0x00, + /* ASCII 48 */ 0x00,0x00,0x0f,0xc0,0x10,0x20,0x10,0x20,0x10,0x20,0x0f,0xc0,0x00,0x00, + /* ASCII 49 */ 0x00,0x00,0x10,0x00,0x10,0x20,0x1f,0xe0,0x10,0x00,0x10,0x00,0x00,0x00, + /* ASCII 50 */ 0x00,0x00,0x18,0x40,0x14,0x20,0x12,0x20,0x11,0x20,0x18,0xc0,0x00,0x00, + /* ASCII 51 */ 0x00,0x00,0x08,0x40,0x10,0x20,0x11,0x20,0x11,0x20,0x0e,0xc0,0x00,0x00, + /* ASCII 52 */ 0x00,0x00,0x06,0x00,0x05,0x00,0x04,0xc0,0x14,0x20,0x1f,0xe0,0x14,0x00, + /* ASCII 53 */ 0x00,0x00,0x08,0x00,0x11,0xe0,0x11,0x20,0x11,0x20,0x0e,0x20,0x00,0x00, + /* ASCII 54 */ 0x00,0x00,0x0f,0x80,0x11,0x40,0x11,0x20,0x11,0x20,0x0e,0x20,0x00,0x00, + /* ASCII 55 */ 0x00,0x00,0x00,0x60,0x00,0x20,0x18,0x20,0x07,0x20,0x00,0xe0,0x00,0x00, + /* ASCII 56 */ 0x00,0x00,0x0e,0xc0,0x11,0x20,0x11,0x20,0x11,0x20,0x0e,0xc0,0x00,0x00, + /* ASCII 57 */ 0x00,0x00,0x11,0xc0,0x12,0x20,0x12,0x20,0x0a,0x20,0x07,0xc0,0x00,0x00, + /* ASCII 58 */ 0x00,0x00,0x00,0x00,0x19,0x80,0x19,0x80,0x00,0x00,0x00,0x00,0x00,0x00, + /* ASCII 59 */ 0x00,0x00,0x00,0x00,0x30,0x00,0x19,0x80,0x09,0x80,0x00,0x00,0x00,0x00, + /* ASCII 60 */ 0x02,0x00,0x05,0x00,0x05,0x00,0x08,0x80,0x10,0x40,0x10,0x40,0x00,0x00, + /* ASCII 61 */ 0x00,0x00,0x05,0x00,0x05,0x00,0x05,0x00,0x05,0x00,0x05,0x00,0x00,0x00, + /* ASCII 62 */ 0x10,0x40,0x10,0x40,0x08,0x80,0x05,0x00,0x05,0x00,0x02,0x00,0x00,0x00, + /* ASCII 63 */ 0x00,0x00,0x00,0x00,0x10,0x80,0x14,0x40,0x02,0x40,0x01,0x80,0x00,0x00, + /* ASCII 64 */ 0x00,0x00,0x1f,0xe0,0x20,0x10,0x23,0x10,0x24,0x90,0x17,0xe0,0x00,0x00, + /* ASCII 65 */ 0x10,0x00,0x1c,0x00,0x17,0xa0,0x04,0x60,0x17,0x80,0x1c,0x00,0x10,0x00, + /* ASCII 66 */ 0x10,0x20,0x1f,0xe0,0x11,0x20,0x11,0x20,0x11,0x20,0x0e,0xc0,0x00,0x00, + /* ASCII 67 */ 0x00,0x00,0x0f,0xc0,0x10,0x20,0x10,0x20,0x10,0x20,0x08,0x60,0x00,0x00, + /* ASCII 68 */ 0x10,0x20,0x1f,0xe0,0x10,0x20,0x10,0x20,0x08,0x40,0x07,0x80,0x00,0x00, + /* ASCII 69 */ 0x10,0x20,0x1f,0xe0,0x11,0x20,0x13,0xa0,0x10,0x20,0x18,0x60,0x00,0x00, + /* ASCII 70 */ 0x00,0x00,0x10,0x20,0x1f,0xe0,0x11,0x20,0x03,0xa0,0x00,0x20,0x00,0x60, + /* ASCII 71 */ 0x00,0x00,0x0f,0xc0,0x10,0x20,0x10,0x20,0x12,0x20,0x0e,0x60,0x02,0x00, + /* ASCII 72 */ 0x10,0x20,0x1f,0xe0,0x11,0x20,0x01,0x00,0x11,0x20,0x1f,0xe0,0x10,0x20, + /* ASCII 73 */ 0x00,0x00,0x10,0x20,0x10,0x20,0x1f,0xe0,0x10,0x20,0x10,0x20,0x00,0x00, + /* ASCII 74 */ 0x00,0x00,0x0e,0x00,0x10,0x20,0x10,0x20,0x0f,0xe0,0x00,0x20,0x00,0x00, + /* ASCII 75 */ 0x10,0x20,0x1f,0xe0,0x12,0x20,0x03,0x00,0x04,0xa0,0x18,0x60,0x10,0x20, + /* ASCII 76 */ 0x00,0x00,0x10,0x20,0x1f,0xe0,0x10,0x20,0x10,0x00,0x1c,0x00,0x00,0x00, + /* ASCII 77 */ 0x10,0x20,0x1f,0xe0,0x10,0xe0,0x03,0x00,0x10,0xe0,0x1f,0xe0,0x10,0x20, + /* ASCII 78 */ 0x10,0x20,0x1f,0xe0,0x10,0xe0,0x07,0x00,0x18,0x20,0x1f,0xe0,0x00,0x20, + /* ASCII 79 */ 0x00,0x00,0x0f,0xc0,0x10,0x20,0x10,0x20,0x10,0x20,0x0f,0xc0,0x00,0x00, + /* ASCII 80 */ 0x00,0x00,0x10,0x20,0x1f,0xe0,0x12,0x20,0x02,0x20,0x01,0xc0,0x00,0x00, + /* ASCII 81 */ 0x00,0x00,0x0f,0xc0,0x10,0x20,0x30,0x20,0x30,0x20,0x2f,0xc0,0x00,0x00, + /* ASCII 82 */ 0x10,0x20,0x1f,0xe0,0x12,0x20,0x02,0x20,0x06,0x20,0x09,0xc0,0x10,0x00, + /* ASCII 83 */ 0x00,0x00,0x18,0xc0,0x09,0x20,0x11,0x20,0x11,0x40,0x0e,0x60,0x00,0x00, + /* ASCII 84 */ 0x00,0x60,0x00,0x20,0x10,0x20,0x1f,0xe0,0x10,0x20,0x00,0x20,0x00,0x60, + /* ASCII 85 */ 0x00,0x20,0x0f,0xe0,0x10,0x20,0x10,0x00,0x10,0x20,0x0f,0xe0,0x00,0x20, + /* ASCII 86 */ 0x00,0x20,0x00,0xe0,0x07,0x20,0x18,0x00,0x07,0x20,0x00,0xe0,0x00,0x20, + /* ASCII 87 */ 0x00,0x20,0x0f,0xe0,0x10,0x20,0x0f,0x00,0x10,0x20,0x0f,0xe0,0x00,0x20, + /* ASCII 88 */ 0x10,0x20,0x18,0x60,0x04,0x80,0x03,0x00,0x04,0x80,0x18,0x60,0x10,0x20, + /* ASCII 89 */ 0x00,0x20,0x00,0x60,0x11,0xa0,0x1e,0x00,0x11,0xa0,0x00,0x60,0x00,0x20, + /* ASCII 90 */ 0x00,0x00,0x18,0x60,0x14,0x20,0x13,0x20,0x10,0xa0,0x18,0x60,0x00,0x00, + /* ASCII 91 */ 0x00,0x00,0x00,0x00,0x7f,0xe0,0x40,0x20,0x40,0x20,0x00,0x00,0x00,0x00, + /* ASCII 92 */ 0x00,0x00,0x00,0x20,0x01,0xc0,0x06,0x00,0x38,0x00,0x00,0x00,0x00,0x00, + /* ASCII 93 */ 0x00,0x00,0x00,0x00,0x40,0x20,0x40,0x20,0x7f,0xe0,0x00,0x00,0x00,0x00, + /* ASCII 94 */ 0x00,0x00,0x01,0x00,0x00,0x80,0x00,0x60,0x00,0x80,0x01,0x00,0x00,0x00, + /* ASCII 95 */ 0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00, + /* ASCII 96 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x40,0x00,0x00,0x00,0x00, + /* ASCII 97 */ 0x00,0x00,0x0d,0x00,0x12,0x80,0x12,0x80,0x12,0x80,0x1f,0x00,0x10,0x00, + /* ASCII 98 */ 0x10,0x20,0x1f,0xe0,0x11,0x00,0x10,0x80,0x10,0x80,0x0f,0x00,0x00,0x00, + /* ASCII 99 */ 0x00,0x00,0x0f,0x00,0x10,0x80,0x10,0x80,0x10,0x80,0x09,0x80,0x00,0x00, + /* ASCII 100 */ 0x00,0x00,0x0f,0x00,0x10,0x80,0x10,0x80,0x11,0x20,0x1f,0xe0,0x10,0x00, + /* ASCII 101 */ 0x00,0x00,0x0f,0x00,0x12,0x80,0x12,0x80,0x12,0x80,0x13,0x00,0x00,0x00, + /* ASCII 102 */ 0x00,0x00,0x10,0x80,0x1f,0xc0,0x10,0xa0,0x10,0xa0,0x10,0xa0,0x00,0x00, + /* ASCII 103 */ 0x00,0x00,0x0f,0x00,0x50,0x80,0x50,0x80,0x51,0x00,0x3f,0x80,0x00,0x80, + /* ASCII 104 */ 0x10,0x20,0x1f,0xe0,0x11,0x00,0x00,0x80,0x10,0x80,0x1f,0x00,0x10,0x00, + /* ASCII 105 */ 0x00,0x00,0x10,0x80,0x10,0x80,0x1f,0xa0,0x10,0x00,0x10,0x00,0x00,0x00, + /* ASCII 106 */ 0x00,0x00,0x40,0x80,0x40,0x80,0x40,0xa0,0x3f,0x80,0x00,0x00,0x00,0x00, + /* ASCII 107 */ 0x10,0x20,0x1f,0xe0,0x02,0x00,0x16,0x80,0x19,0x80,0x10,0x80,0x00,0x00, + /* ASCII 108 */ 0x00,0x00,0x10,0x00,0x10,0x20,0x1f,0xe0,0x10,0x00,0x10,0x00,0x00,0x00, + /* ASCII 109 */ 0x10,0x80,0x1f,0x80,0x10,0x80,0x1f,0x00,0x10,0x80,0x1f,0x00,0x10,0x00, + /* ASCII 110 */ 0x10,0x80,0x1f,0x80,0x11,0x00,0x00,0x80,0x10,0x80,0x1f,0x00,0x10,0x00, + /* ASCII 111 */ 0x00,0x00,0x0f,0x00,0x10,0x80,0x10,0x80,0x10,0x80,0x0f,0x00,0x00,0x00, + /* ASCII 112 */ 0x40,0x80,0x7f,0x80,0x51,0x00,0x10,0x80,0x10,0x80,0x0f,0x00,0x00,0x00, + /* ASCII 113 */ 0x00,0x00,0x0f,0x00,0x10,0x80,0x10,0x80,0x51,0x00,0x7f,0x80,0x40,0x80, + /* ASCII 114 */ 0x00,0x00,0x10,0x80,0x1f,0x80,0x11,0x00,0x10,0x80,0x10,0x80,0x00,0x00, + /* ASCII 115 */ 0x00,0x00,0x19,0x00,0x12,0x80,0x12,0x80,0x12,0x80,0x0d,0x80,0x00,0x00, + /* ASCII 116 */ 0x00,0x00,0x00,0x80,0x0f,0xc0,0x10,0x80,0x10,0x80,0x10,0x80,0x08,0x00, + /* ASCII 117 */ 0x00,0x80,0x0f,0x80,0x10,0x00,0x10,0x00,0x08,0x80,0x1f,0x80,0x10,0x00, + /* ASCII 118 */ 0x00,0x80,0x03,0x80,0x0c,0x80,0x10,0x00,0x0c,0x80,0x03,0x80,0x00,0x80, + /* ASCII 119 */ 0x00,0x80,0x0f,0x80,0x10,0x80,0x0e,0x00,0x10,0x80,0x0f,0x80,0x00,0x80, + /* ASCII 120 */ 0x10,0x80,0x19,0x80,0x06,0x00,0x06,0x00,0x19,0x80,0x10,0x80,0x00,0x00, + /* ASCII 121 */ 0x00,0x80,0x41,0x80,0x46,0x80,0x78,0x00,0x4c,0x80,0x03,0x80,0x00,0x80, + /* ASCII 122 */ 0x00,0x00,0x19,0x80,0x14,0x80,0x12,0x80,0x11,0x80,0x18,0x80,0x00,0x00, + /* ASCII 123 */ 0x00,0x00,0x00,0x00,0x04,0x00,0x3b,0xc0,0x40,0x20,0x00,0x00,0x00,0x00, + /* ASCII 124 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x3f,0xe0,0x00,0x00,0x00,0x00,0x00,0x00, + /* ASCII 125 */ 0x00,0x00,0x00,0x00,0x40,0x20,0x3b,0xc0,0x04,0x00,0x00,0x00,0x00,0x00, + /* ASCII 126 */ 0x00,0x00,0x04,0x00,0x02,0x00,0x04,0x00,0x04,0x00,0x02,0x00,0x00,0x00}; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : LCD_DataLinesConfig +* Description : Configure data lines D0~D7 (P2.10~P2.17) in Input Floating mode +* for read from LCD or in Output Push-Pull mode for write on LCD +* Input : - Mode: specifies the configuration mode for data lines D0~D7 +* - Input: configure in Input Floating mode +* - Output: configure in Output Push-Pul mode +* Output : None +* Return : None +*******************************************************************************/ +void LCD_DataLinesConfig(DataConfigMode_TypeDef Mode) +{ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | + GPIO_Pin_14 | GPIO_Pin_15 | GPIO_Pin_16 | GPIO_Pin_17; + if (Mode == Input) + { + /* Configure D0~D7 lines (P2.10~2.17) in Input Floating mode */ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; + } + else + { + /* Configure D0~D7 lines (P2.10~2.17) in Output Push-Pull mode */ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + } + GPIO_Init(GPIO2, &GPIO_InitStructure); +} + +/******************************************************************************* +* Function Name : LCD_DataLinesWrite +* Description : Write a value on D0~D7 (P2.10~P2.17) +* Input : - GPIOx: GPIO port to write on. It could be +* - PortVal: value to write +* Output : None +* Return : None. +*******************************************************************************/ +void LCD_DataLinesWrite(GPIO_TypeDef* GPIOx, u32 PortVal) +{ + u32 Tmp = 0; + + /* Store the PM register value */ + Tmp = GPIO_GetPortMask(GPIOx); + /* Mask the corresponding GPIO pins */ + GPIO_PinMaskConfig(GPIOx, LCD_GPIO_Pins, DISABLE); + GPIO_PinMaskConfig(GPIOx, ~LCD_GPIO_Pins, ENABLE); + /* Write in the hole register */ + GPIO_Write(GPIOx, (PortVal<<10)); + + GPIO_PinMaskConfig(GPIOx, ~LCD_GPIO_Pins, DISABLE); + /* Return the initial PM register value */ + GPIO_PinMaskConfig(GPIOx, Tmp, ENABLE); + +} + +/******************************************************************************* +* Function Name : LCD_CtrlLinesConfig +* Description : Configure control lines E2, E1, RW, DI (P2.0~P2.3) in +* Output Push-Pull mode. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void LCD_CtrlLinesConfig(void) +{ + /* Configure E2, E1, RW, DI lines (P2.0~2.3) in Output Push-Pull mode */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_Init(GPIO2, &GPIO_InitStructure); +} + +/******************************************************************************* +* Function Name : LCD_CtrlLinesWrite +* Description : Set or reset control lines E2, E1, RW, DI (P2.0~P2.3). +* Input : - GPIOx: where x can be 0,1 or 2 to select the GPIO peripheral. +* - CtrlPins: the Control line. This parameter can be: +* - CtrlPin_E2: Enabe clock signal for Slave +* - CtrlPin_E1: Enabe clock signal for Master +* - CtrlPin_RW: Read/Write control line +* - CtrlPin_DI: +* Output : None +* Return : None +*******************************************************************************/ +void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, u32 CtrlPins, BitAction BitVal) +{ + /* Set or Reset the control line */ + if(BitVal != Bit_RESET) + { + GPIOx->PD |= CtrlPins; + } + else + { + GPIOx->PD &= ~CtrlPins; + } +} + +/******************************************************************************* +* Function Name : LCD_CheckMasterStatus +* Description : Check whether master LCD is busy or not +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void LCD_CheckMasterStatus(void) +{ + u8 MasterStatus = 0; + + /* Configure Data lines as Input */ + LCD_DataLinesConfig(Input); + /* Start the master read sequence */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_RW, Bit_SET); /* RW = 1 */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_DI, Bit_RESET); /* DI = 0 */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_SET); /* E1 = 1 */ + MasterStatus = GPIO_Read(GPIO2); + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ + + /* Wait until BF is cleared: D7 line */ + while ((MasterStatus & 0x20000)) + { + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_SET); /* E1 = 1 */ + MasterStatus = GPIO_Read(GPIO2); + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ + } +} + +/******************************************************************************* +* Function Name : LCD_CheckSlaveStatus +* Description : Check whether slave LCD is busy or not +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void LCD_CheckSlaveStatus(void) +{ + u8 SlaveStatus = 0; + + /* Configure Data lines as Input */ + LCD_DataLinesConfig(Input); + /* Start the slave read sequence */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_RW, Bit_SET); /* RW = 1 */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_DI, Bit_RESET); /* DI = 0 */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_SET); /* E2 = 1 */ + SlaveStatus = GPIO_Read(GPIO2); + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ + + /* Wait until BF is cleared: D7 line */ + while ((SlaveStatus & 0x20000)) + { + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_SET); /* E2 = 1 */ + SlaveStatus = GPIO_Read(GPIO2); + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ + } +} + +/******************************************************************************* +* Function Name : LCD_SendMasterCmd +* Description : Send one byte command to master LCD. +* Input : - Cmd: the user expected command to send to master LCD +* Output : None +* Return : None +*******************************************************************************/ +void LCD_SendMasterCmd(u8 Cmd) +{ + /* Check the master status */ + LCD_CheckMasterStatus(); + /* Configure Data lines as Output */ + LCD_DataLinesConfig(Output); + /* Start the master send command sequence */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_RW, Bit_RESET); /* RW = 0 */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_DI, Bit_RESET); /* DI = 0 */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_SET); /* E1 = 1 */ + /* Write master command */ + LCD_DataLinesWrite(GPIO2, (u32)Cmd); + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ +} + +/******************************************************************************* +* Function Name : LCD_SendSlaveCmd +* Description : Send one byte command to slave LCD +* Input : - Cmd: the user expected command to send to slave LCD. +* Output : None +* Return : None +*******************************************************************************/ +void LCD_SendSlaveCmd(u8 Cmd) +{ + /* Check the slave status */ + LCD_CheckSlaveStatus(); + /* Configure Data lines as Output */ + LCD_DataLinesConfig(Output); + /* Start the slave send command sequence */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_RW, Bit_RESET); /* RW = 0 */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_DI, Bit_RESET); /* DI = 0 */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_SET); /* E2 = 1 */ + /* Write slave command */ + LCD_DataLinesWrite(GPIO2, (u32)Cmd); + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ +} + +/******************************************************************************* +* Function Name : LCD_SendMasterData +* Description : Display one byte data to master LCD. +* Input : - Data: the user expected data to display on master LCD. +* Output : None +* Return : None +*******************************************************************************/ +void LCD_SendMasterData(u8 Data) +{ + /* Check the master status */ + LCD_CheckMasterStatus(); + /* Configure Data lines as Output */ + LCD_DataLinesConfig(Output); + /* Start the master send data sequence */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_RW, Bit_RESET); /* RW = 0 */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_DI, Bit_SET); /* DI = 1 */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_SET); /* E1 = 1 */ + /* Write data to the master */ + LCD_DataLinesWrite(GPIO2, (u32)Data); + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ +} + +/******************************************************************************* +* Function Name : LCD_ReadMasterData +* Description : Read master byte data displayed on master LCD. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +u32 LCD_ReadMasterData(void) +{ + u32 MasterData = 0; + + /* Check the master status */ + LCD_CheckMasterStatus(); + /* Configure Data lines as Input */ + LCD_DataLinesConfig(Input); + /* Start the master read data sequence */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_RW, Bit_SET); /* RW = 1 */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_DI, Bit_SET); /* DI = 1 */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_SET); /* E1 = 1 */ + /* Read data from the master */ + MasterData = ((GPIO_Read(GPIO2)&0x3FC00)>>10); + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ + /* Read the master returned data */ + return MasterData; +} + +/******************************************************************************* +* Function Name : LCD_SendSlaveData +* Description : Display one byte data to slave LCD. +* Input : - Data: the user expected data to display on slave LCD. +* Output : None +* Return : None +*******************************************************************************/ +void LCD_SendSlaveData(u8 Data) +{ + /* Check the slave status */ + LCD_CheckSlaveStatus(); + /* Configure Data lines as Output */ + LCD_DataLinesConfig(Output); + /* Start the slave send data sequence */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_RW, Bit_RESET); /* RW = 0 */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_DI, Bit_SET); /* DI = 1 */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_SET); /* E2 = 1 */ + /* Write data to the slave */ + LCD_DataLinesWrite(GPIO2, (u32)Data); + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ +} + +/******************************************************************************* +* Function Name : LCD_ReadSlaveData +* Description : Read slave byte data displayed on slave LCD. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +u32 LCD_ReadSlaveData(void) +{ + u32 SlaveData = 0; + + /* Check the slave status */ + LCD_CheckSlaveStatus(); + /* Configure Data lines as Input */ + LCD_DataLinesConfig(Input); + /* Start the slave read data sequence */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_RW, Bit_SET); /* RW = 1 */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_DI, Bit_SET); /* DI = 1 */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_SET); /* E2 = 1 */ + /* Read data from the slave */ + SlaveData = ((GPIO_Read(GPIO2)&0x3FC00)>>10); + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ + /* Read the slave returned data */ + return SlaveData; +} + +/******************************************************************************* +* Function Name : LCD_Init +* Description : Initialize master and slave LCD. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void LCD_Init(void) +{ + /* Enable GPIO Clock */ + MRCC_PeripheralClockConfig(MRCC_Peripheral_GPIO, ENABLE); + + /* Configure control lines signals as output mode */ + LCD_CtrlLinesConfig(); + + /* Master LCD Init */ + LCD_SendMasterCmd(SOFTWARE_RESET); + LCD_SendMasterCmd(DISPLAY_OFF); + LCD_SendMasterCmd(DYNAMIC_DRIVE); + LCD_SendMasterCmd(DUTY_CYCLE); + LCD_SendMasterCmd(CLOCKWISE_OUTPUT); + LCD_SendMasterCmd(READ_MODIFY_WRITE_OFF); + LCD_SendMasterCmd(START_COLUMN); /* Set master column address to 0 */ + LCD_SendMasterCmd(START_LINE); /* Set master display start line to 0 */ + LCD_SendMasterCmd(DISPLAY_ON ); + + /* Slave LCD Init */ + LCD_SendSlaveCmd(SOFTWARE_RESET); + LCD_SendSlaveCmd(DISPLAY_OFF); + LCD_SendSlaveCmd(DYNAMIC_DRIVE); + LCD_SendSlaveCmd(DUTY_CYCLE); + LCD_SendSlaveCmd(CLOCKWISE_OUTPUT); + LCD_SendSlaveCmd(READ_MODIFY_WRITE_OFF); + LCD_SendSlaveCmd(START_COLUMN ); /* Set slave column address to 0 */ + LCD_SendSlaveCmd(START_LINE); /* Set slave display start line to 0 */ + LCD_SendSlaveCmd(DISPLAY_ON); + + /* Clear LCD */ + LCD_Clear(); + /* Set current Page to 0 for Master and Slave LCDs */ + LCD_SetSlavePage(0); + LCD_SetMasterPage(0); +} + +/******************************************************************************* +* Function Name : LCD_SetSlavePage +* Description : Set the display page of slave LCD, the page range is 0 to 3, +* make sure the input will not exceed this range ,otherwise it +* will reach a undecided result. +* Input : - Page: specifies the expected display page of slave LCD +* Output : None +* Return : None +*******************************************************************************/ +void LCD_SetSlavePage(u8 Page) +{ + /* Set Slave page */ + LCD_SendSlaveCmd(0xB8|Page); +} + +/******************************************************************************* +* Function Name : LCD_SetMasterPage +* Description : Set the display page of master LCD, the page range is 0 to 3, +* make sure the input will not exceed this range ,otherwise it +* will reach a undecided result. +* Input : - Page: specifies the expected display page of master LCD +* Output : None +* Return : None +*******************************************************************************/ +void LCD_SetMasterPage(u8 Page) +{ + /* Set Master page */ + LCD_SendMasterCmd(0xB8|Page); +} + +/******************************************************************************* +* Function Name : SetAddress +* Description : Set the display column of slave LCD. Column range is 0 to 61. +* Input : - Address: specifies the expected display column of slave LCD +* Output : None +* Return : None +*******************************************************************************/ +void LCD_SetSlaveColumn(u8 Address) +{ + /* Set Slave column address */ + LCD_SendSlaveCmd(Address&0x7F); +} + +/******************************************************************************* +* Function Name : LCD_SetMasterColumn +* Description : Set the display column of master LCD. Column range is 0 to 61. +* Input : - Address: specifies the expected display column of slave LCD +* Output : None +* Return : None +*******************************************************************************/ +void LCD_SetMasterColumn(u8 Address) +{ + /* Set Master column address */ + LCD_SendMasterCmd(Address&0x7F); +} + +/******************************************************************************* +* Function Name : LCD_SetTextColor +* Description : Set the text color for LCD. +* Input : - TextColor: BlackText: character on black, bottom on white. +* WhiteText: character on white, bottom on black. +* Output : None +* Return : None +*******************************************************************************/ +void LCD_SetTextColor(TextColorMode_TypeDef TextColor) +{ + if(TextColor) + { + /* Set White Text color */ + TextMode=WhiteText; + } + else + { + /* Set Black Text color */ + TextMode=BlackText; + } +} + +/******************************************************************************* +* Function Name : LCD_Clear +* Description : Clear the Master and Slave LCDs display. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void LCD_Clear(void) +{ + u8 Page = 0, Column = 0; + + /* Clear master and slave LCDs page by page */ + for (Page=0; Page<4; Page++) + { + /* Set master and slave page by page */ + LCD_SetMasterPage(Page); + LCD_SetSlavePage(Page); + /* Set master and slave column address */ + LCD_SetMasterColumn(0); + LCD_SetSlaveColumn(0); + /* Send empty data to master and slave column address on the selected page */ + for (Column=0; Column<61; Column++) + { + LCD_SendSlaveData(0); + LCD_SendMasterData(0); + } + } +} + +/******************************************************************************* +* Function Name : LCD_ClearLine +* Description : Clear the selected line of the LCD. +* Input : - Line: the Line to clear. +* - Line1 (Page0&1): clear the first line +* - Line2 (Page2&3): clear the second line +* Output : None +* Return : None +*******************************************************************************/ +void LCD_ClearLine(u8 Line) +{ + u8 Page = 0, Column = 0; + + /* Clear the slected master and slave line */ + for (Page=Line; Page 121) + { + /* Return if column exceeded 121 */ + return; + } + if (X > 60) + { + /* To be displayed on slave LCD (Window = 1) */ + Window = 1; + /* Get the Slave relative start column */ + ActualColumn = X%61; + } + else + { + /* To be displayed on master LCD (Window = 0) */ + ActualColumn = X; + } + + /* Switch window, display the character upper part */ + if (Window) + { + /* Display it on slave LCD */ + LCD_SetSlavePage(Line); + LCD_SetSlaveColumn(ActualColumn); + LCD_SendSlaveData(Bmp[i]); + } + else + { + /* Display it on master LCD */ + LCD_SetMasterPage(Line); + LCD_SetMasterColumn(ActualColumn); + LCD_SendMasterData(Bmp[i]); + } + /* Switch window, diplay the character lower part */ + if (Window) + { + /* Display it on slave LCD */ + LCD_SetSlavePage(Line+1); + LCD_SetSlaveColumn(ActualColumn); + LCD_SendSlaveData(Bmp[i+1]); + } + else + { + /* Display it on master LCD */ + LCD_SetMasterPage(Line+1); + LCD_SetMasterColumn(ActualColumn); + LCD_SendMasterData(Bmp[i+1]); + } + /* Increment by 2 the character table index */ + i+=2; + } +} + +/******************************************************************************* +* Function Name : LCD_DisplayChar +* Description : Display one character (7dots large, 16dots high). +* Note: +* the LCD can only display two line character,so page 0 and 1 +* is to display the first line, page2 and page 3 is to display +* the second line. +* Input : - Line: the Line where to display the character. +* - Line1 (Page0&1): display character on the first line +* - Line2 (Page2&3): display character on the second line +* - Column: start column address. +* - Ascii: character ascii code. +* - CharMode: BlackText: character on black, bottom on white. +* WhiteText: character on white, bottom on black. +* Output : None +* Return : None +*******************************************************************************/ +void LCD_DisplayChar(u8 Line, u8 Column, u8 Ascii, TextColorMode_TypeDef CharMode) +{ + u8 DotBuffer[14], i = 0; + + /* Display the character lower and upper 8bit parts (2*7columns) */ + for (i=0;i<14;i++) + { + /* Character displayed as white Text on black buttom */ + if(CharMode) + { + if(i%2==0) + { + DotBuffer[i] = ~AsciiDotsTable[Ascii*14+i+1]; + } + else + { + DotBuffer[i] = ~AsciiDotsTable[Ascii*14+i-1]; + } + } + /* Character displayed as black Text on white buttom */ + else + { + if(i%2==0) + { + DotBuffer[i] = AsciiDotsTable[Ascii*14+i+1]; + } + else + { + DotBuffer[i] = AsciiDotsTable[Ascii*14+i-1]; + } + } + } + /* Display the asc code after conversion */ + LCD_DrawChar(Line, Column, 7, DotBuffer); +} + +/******************************************************************************* +* Function Name : LCD_HexToAsciiLow +* Description : This function is used to convert the low nibble of an +* unsigned byte (0-F hex) to ASCII. +* Input : - byte: byte to convert to ASCII. +* Output : None +* Return : ASCII value result of the conversion. +*******************************************************************************/ +u8 LCD_HexToAsciiLow(u8 byte) +{ + /* Keep lower nibble only */ + byte = byte & 0x0F; + /* If the ascii is a number */ + if (byte <= 0x09) + { + /* Add 0x30 to its ascii */ + return(byte + 0x30); + } + else + { + /* Add 0x37 to its ascii */ + return (byte + 0x37); + } +} + +/******************************************************************************* +* Function Name : LCD_HexToAsciiHigh +* Description : This function is used to convert the high nibble of an +* unsigned byte (0-F hex) to ASCII. +* Input : - byte: byte to convert to ASCII. +* Output : None +* Return : ASCII value result of the conversion. +*******************************************************************************/ +u8 LCD_HexToAsciiHigh(u8 byte) +{ + /* Keep upper nibble only */ + byte = byte & 0xF0; + byte = byte >> 4; + /* If the ascii is a number */ + if (byte <= 0x09) + { + /* Add 0x30 to display its ascii */ + return(byte + 0x30); + } + else + { + /* Add 0x37 to display its ascii */ + return (byte + 0x37); + } +} + +/******************************************************************************* +* Function Name : LCD_DisplayString +* Description : This function is used to display a 17char max string of +* characters on the LCD display on the selected line. +* Note: +* this function is the user interface to use the LCD driver. +* Input : - *ptr: pointer to string to display on LCD. +* - Line: the Line where to display the character. +* - Line1 (Page0&1): display character on the first line +* - Line2 (Page2&3): display character on the second line +* Output : None +* Return : None +*******************************************************************************/ +void LCD_DisplayString(u8 Line, u8 *ptr, TextColorMode_TypeDef CharMode) +{ + u8 RefColumn = 0, i = 0; + + /* Send the string character by character on lCD */ + while ((*ptr!=0)&(i<17)) + { + /* Display one character on LCD */ + LCD_DisplayChar(Line, RefColumn, *ptr, CharMode); + /* Increment the column position by 7 */ + RefColumn+=7; + /* Point on the next character */ + ptr++; + /* Increment the character counter */ + i++; + /* If we reach the maximum Line character */ + if(i==17) + { + LCD_DisplayChar(Line, RefColumn-1, 0x1f, CharMode); /* Add missed columns */ + } + } +} + +/******************************************************************************* +* Function Name : LCD_Printf +* Description : This function is used to display a string of characters +* on the LCD display. +* Note: +* this function is the user interface to use the LCD driver. +* Input : - *ptr: pointer to string to display on LCD. +* Output : None +* Return : None +*******************************************************************************/ +void LCD_Printf(u8 *ptr, ...) +{ + u8 RefColumn = 0, RefPage = 0, i = 0, c1 = 0; + u16 var = 0, c2 = 0, c3 = 0, c4 = 0, c5 = 0; + u32 WordVar = 0; + + /* Store pointer on LCD_Printf second parameter (String) */ + u8 *var_ptr=(u8 *)(&ptr+1); + + /* Send String */ + while (*ptr != 0) + { + c1 = *ptr; + /* Limited to AsciiDotsTable code table */ + if(c1 <= 128) + { + /* Carriage return */ + if ( *ptr == '\r') + { + ptr++; + RefColumn = 0; + } + /* Jump to Line2 */ + else if( *ptr == '\n') + { + /* Point on the string to display */ + ptr++; + /* Clear Line2 */ + LCD_ClearLine(Line2); + /* Point on first Line2 column */ + RefColumn = 0; + /* Increment RefPage by 2 */ + RefPage+=2; + } + /* Display value on the passed format */ + else if( *ptr == '%') + { + ptr++; + /* Display decimal value */ + if (*ptr == 'd') + { + ptr++; + /* Get the word value to display */ + WordVar = ((*var_ptr)|(*(var_ptr+1)<<8)|(*(var_ptr+2)<<16)); + c1=WordVar/10000; + c2=(WordVar%10000)/1000; + c3=(WordVar%1000)/100; + c4=(WordVar%100)/10; + c5=(WordVar%10); + /* Display the ten miles digit */ + if (c1!=0) + { + LCD_DisplayChar(RefPage, RefColumn, c1+0x30, TextMode); + RefColumn+=7; + } + /* Display the miles digit */ + if (!((c1==0)&(c2==0))) + { + LCD_DisplayChar(RefPage, RefColumn, c2+0x30, TextMode); + RefColumn+=7; + } + /* Display the hundred digit */ + if (!((c1==0)&(c2==0)&(c3==0))) + { + LCD_DisplayChar(RefPage, RefColumn, c3+0x30, TextMode); + RefColumn+=7; + } + /* Display the tens digit */ + if (!((c1==0)&(c2==0)&(c3==0)&(c4==0))) + { + LCD_DisplayChar(RefPage, RefColumn, c4+0x30, TextMode); + RefColumn+=7; + } + /* Display the rest */ + LCD_DisplayChar(RefPage, RefColumn, c5+0x30, TextMode); + RefColumn+=7; + } + /* Display 16bits Hex value */ + else if (*ptr == 'x') + { + ptr++; + /* Display 8bits MSB */ + var_ptr = var_ptr +1; + var = *var_ptr; + c1 = LCD_HexToAsciiHigh(var); + LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); + RefColumn+=7; + c1 = LCD_HexToAsciiLow(var); + LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); + RefColumn+=7; + /* Display 8bits LSB */ + var_ptr = var_ptr -1; + var = *var_ptr; + var_ptr = var_ptr +4; + c1 = LCD_HexToAsciiHigh(var); + LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); + RefColumn+=7; + c1 = LCD_HexToAsciiLow(var); + LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); + RefColumn+=7; + } + /* Display 32bits Hex value */ + else if (*ptr == 'w') + { + ptr++; + /* Display 16bits MSB */ + var_ptr = var_ptr +3; + var = *var_ptr; + c1 = LCD_HexToAsciiHigh(var); + LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); + RefColumn+=7; + c1 = LCD_HexToAsciiLow(var); + LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); + RefColumn+=7; + var_ptr = var_ptr -1; + var = *var_ptr; + c1 = LCD_HexToAsciiHigh(var); + LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); + RefColumn+=7; + c1 = LCD_HexToAsciiLow(var); + LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); + RefColumn+=7; + /* Display 16bits LSB */ + var_ptr = var_ptr -1; + var = *var_ptr; + var_ptr = var_ptr +4; + c1 = LCD_HexToAsciiHigh(var); + LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); + RefColumn+=7; + c1 = LCD_HexToAsciiLow(var); + LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); + RefColumn+=7; + var_ptr = var_ptr -5; + var = *var_ptr; + var_ptr = var_ptr +4; + c1 = LCD_HexToAsciiHigh(var); + LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); + RefColumn+=7; + c1 = LCD_HexToAsciiLow(var); + LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); + RefColumn+=7; + } + else + { + /* Display '%' character which is followed by (d, x or w) */ + ptr--; + c1 = *ptr; + LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); + RefColumn+=7; + ptr++; + i++; + if(i==17) + { + /* Add missed columns */ + LCD_DisplayChar(RefPage, RefColumn-1, 0x1f, TextMode); + RefColumn = 0; + RefPage+=2; + } + } + } + else + { + /* Display characters different from (\r, \n, %) */ + LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); + RefColumn+=7; + ptr++; + i++; + if(i==17) + { + /* Add missed columns */ + LCD_DisplayChar(RefPage, RefColumn-1, 0x1f, TextMode); + LCD_ClearLine(Line2); + RefColumn = 0; + RefPage+=2; + } + } + } + } + /* Display spaces if string doesn't reach the max LCD characters size */ + while(RefColumn<119) + { + /* Display Spaces */ + LCD_DisplayChar(RefPage, RefColumn, 0x20, TextMode); + RefColumn+=7; + /* Add missed columns */ + LCD_DisplayChar(RefPage, RefColumn, 0x1f, TextMode); + } +} + +/******************************************************************************* +* Function Name : LCD_DrawMasterGraphic +* Description : Draw a Graphic image on master LCD. +* Input : - Bmp: the pointer of the dot matrix data. +* Output : None +* Return : None. +*******************************************************************************/ +void LCD_DrawMasterGraphic(u8 *Bmp) +{ + u8 j = 0, k = 0, ActPage = 0; + + /* Draw graphic on master: 61 Column *4 Pages */ + while(j<244) + { + /* Draw on master page by page */ + LCD_SetMasterPage(ActPage); + for(k=0; k<61; k++) + { + LCD_SetMasterColumn(k); + LCD_SendMasterData(*Bmp++); + j++; + } + ActPage++; + } +} + +/******************************************************************************* +* Function Name : LCD_DrawSlaveGraphic +* Description : Draw a Graphic image on slave LCD. +* Input : - Bmp: the pointer of the dot matrix data. +* Output : None +* Return : None. +*******************************************************************************/ +void LCD_DrawSlaveGraphic(u8 *Bmp) +{ + u8 j = 0, k = 0, ActPage = 0; + + /* Draw graphic on slave: 61 Column *4 Pages */ + while(j<244) + { + /* Draw on slave page by page */ + LCD_SetSlavePage(ActPage); + for(k=0; k<61; k++) + { + LCD_SetSlaveColumn(k); + LCD_SendSlaveData(*Bmp++); + j++; + } + ActPage++; + } +} + +/******************************************************************************* +* Function Name : LCD_DrawGraphic +* Description : Draw a Graphic image on LCD. +* Input : - Bmp: the pointer of the dot matrix data. +* Output : None +* Return : None. +*******************************************************************************/ +void LCD_DrawGraphic(u8 *Bmp) +{ + u8 Pos = 0, ActPage = 0; + u16 j = 0, k = 0; + + /* Draw graphic on LCD: 122 Column *4 Pages */ + while(j<488) + { + if(!Pos) + { + /* Draw on master page by page */ + LCD_SetMasterPage(ActPage); + for(k=0; k<61; k++) + { + LCD_SetMasterColumn(k); + LCD_SendMasterData(*Bmp++); + j++; + } + Pos=1; + } + else + { + /* Draw on slave page by page */ + LCD_SetSlavePage(ActPage); + for(k=0; k<61; k++) + { + LCD_SetSlaveColumn(k); + LCD_SendSlaveData(*Bmp++); + j++; + } + ActPage++; + Pos=0; + } + } +} + +/******************************************************************************* +* Function Name : LCD_ScrollGraphic +* Description : Scroll a Graphic image on LCD. +* Input : - Bmp: the pointer of the dot matrix data. +* - nCount: specifies the delay time length. +* Output : None +* Return : None. +*******************************************************************************/ +void LCD_ScrollGraphic(u8 *Bmp, u32 nCount) +{ + u8 Pos = 0, ActPage = 0; + u16 j = 0, k = 0; + u32 Counter = 0; + + /* Draw graphic on LCD: 122 Column *4 Pages */ + while(j<488) + { + if(!Pos) + { + /* Draw on master page by page */ + LCD_SetMasterPage(ActPage); + for(k=0; k<61; k++) + { + LCD_SetMasterColumn(k); + LCD_SendMasterData(*Bmp++); + Counter = nCount; + /* Set a delay */ + for(; Counter != 0; Counter--); + j++; + } + Pos=1; + } + else + { + /* Draw on slave page by page */ + LCD_SetSlavePage(ActPage); + for(k=0; k<61; k++) + { + LCD_SetSlaveColumn(k); + Counter = nCount; + /* Set a delay */ + for(; Counter != 0; Counter--); + LCD_SendSlaveData(*Bmp++); + j++; + } + ActPage++; + Pos=0; + } + } +} + +/******************************************************************************* +* Function Name : LCD_DrawPixel +* Description : Draw a Graphic image on slave LCD. +* Input : - XPos: the dot line number of the pixel. +* - 1->61 : displayed on master LCD +* - 62->122: displayed on slave LCD +* - YPos: column address of the pixel from 1->32. +* - Mode: Dot_On: Pixel turned on (black). +* Dot_Off: Pixel turned off (black). +* Output : None +* Return : None. +*******************************************************************************/ +void LCD_DrawPixel(u8 XPos, u8 YPos, DotMode_TypeDef Mode) +{ + u8 Page = 0, Position = 0; + u16 Mask = 0; + u32 MasterDataIn = 0, MasterDataOut = 0, SlaveDataIn = 0, SlaveDataOut = 0; + + /* Pixel page */ + Page = (XPos-1)/8; + /* Pixel column */ + Position = (YPos-1)/61; /* 0:Master, 1:Slave */ + /* Mask for the pixel */ + Mask= 1<<((XPos-1)%8); + /* If Position=0 draw pixel on master LCD */ + if(!Position) + { + LCD_SetMasterPage(Page); + LCD_SetMasterColumn(YPos-1); + MasterDataIn = LCD_ReadMasterData(); + MasterDataIn = LCD_ReadMasterData(); + LCD_SetMasterColumn(YPos-1); + if(Mode==Dot_On) + { + MasterDataOut = MasterDataIn | Mask; + } + else + { + MasterDataOut = MasterDataIn & (~Mask); + } + LCD_SendMasterData(MasterDataOut); + } + /* If Position=1 draw pixel on slave LCD */ + else + { + LCD_SetSlavePage(Page); + LCD_SetSlaveColumn(YPos-62); + SlaveDataIn = LCD_ReadSlaveData(); + SlaveDataIn = LCD_ReadSlaveData(); + LCD_SetSlaveColumn(YPos-62); + if(Mode==Dot_On) + { + SlaveDataOut = SlaveDataIn | Mask; + } + else + { + SlaveDataOut = SlaveDataIn & (~Mask); + } + LCD_SendSlaveData(SlaveDataOut); + } +} + +/******************************************************************************* +* Function Name : LCD_DrawLine +* Description : Draw a line on master and slave LCDs. +* Input : - XPos1: the dot line number of the source point . +* - XPos2: the dot line number of the destination point . +* - YPos1: the dot column number of the source point. +* - YPos2: the dot column number of the destination point. +* Output : None +* Return : None. +*******************************************************************************/ +void LCD_DrawLine(u8 XPos1, u8 YPos1, u8 XPos2, u8 YPos2) +{ + u8 XPos = 0, YPos = 0; + + /* Use XPos1, YPos1, XPos2 and YPos2 */ + if((XPos2>=XPos1)&(YPos2>=YPos1)) + { + for(XPos=XPos1; XPos<=XPos2; XPos++) + { + for(YPos=YPos1; YPos<=YPos2; YPos++) + { + LCD_DrawPixel(XPos, YPos, Dot_On); + } + } + } + else if((XPos2=YPos1)) + { + for(XPos=XPos2; XPos<=XPos1; XPos++) + { + for(YPos=YPos1; YPos<=YPos2; YPos++) + { + LCD_DrawPixel(XPos, YPos, Dot_On); + } + } + } + else if((XPos2>=XPos1)&(YPos2FLASH + + + /* the program code is stored in the .text section, which goes to Flash */ + .text : + { + . = ALIGN(4); + + *(.text) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + + . = ALIGN(4); + _etext = .; + /* This is used by the startup in order to initialize the .data secion */ + _sidata = _etext; + } >FLASH + + + + /* This is the initialized data section + The program executes knowing that the data is in the RAM + but the loader puts the initial values in the FLASH (inidata). + It is one task of the startup to copy the initial values from FLASH to RAM. */ + .data : AT ( _sidata ) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >RAM + + + + /* This is the uninitialized data section */ + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + } >RAM + + PROVIDE ( end = _ebss ); + PROVIDE ( _end = _ebss ); + + /* This is the user stack section + This is just to check that there is enough RAM left for the User mode stack + It should generate an error if it's full. + */ + ._usrstack : + { + . = ALIGN(4); + _susrstack = . ; + + . = . + _Minimum_Stack_Size ; + + . = ALIGN(4); + _eusrstack = . ; + } >RAM + + + + /* this is the FLASH Bank1 */ + /* the C or assembly source must explicitly place the code or data there + using the "section" attribute */ + .b1text : + { + *(.b1text) /* remaining code */ + *(.b1rodata) /* read-only data (constants) */ + *(.b1rodata*) + } >FLASHB1 + + /* this is the EXTMEM */ + /* the C or assembly source must explicitly place the code or data there + using the "section" attribute */ + + /* EXTMEM Bank0 */ + .eb0text : + { + *(.eb0text) /* remaining code */ + *(.eb0rodata) /* read-only data (constants) */ + *(.eb0rodata*) + } >EXTMEMB0 + + /* EXTMEM Bank1 */ + .eb1text : + { + *(.eb1text) /* remaining code */ + *(.eb1rodata) /* read-only data (constants) */ + *(.eb1rodata*) + } >EXTMEMB1 + + /* EXTMEM Bank2 */ + .eb2text : + { + *(.eb2text) /* remaining code */ + *(.eb2rodata) /* read-only data (constants) */ + *(.eb2rodata*) + } >EXTMEMB2 + + /* EXTMEM Bank0 */ + .eb3text : + { + *(.eb3text) /* remaining code */ + *(.eb3rodata) /* read-only data (constants) */ + *(.eb3rodata*) + } >EXTMEMB3 + + + + /* after that it's only debugging information. */ + + /* remove the debugging information from the standard libraries */ + DISCARD : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} + + + diff --git a/20080212/Demo/ARM7_STR75x_GCC/main.c b/20080212/Demo/ARM7_STR75x_GCC/main.c new file mode 100644 index 000000000..8e03e03ed --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_GCC/main.c @@ -0,0 +1,328 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + * Creates all the demo application tasks, then starts the scheduler. The WEB + * documentation provides more details of the demo application tasks. + * + * In addition to the standard demo tasks there are two tasks defined within + * this file: + * + * 1 - The check task + * The 'check' task is responsible for ensuring that all the standard demo + * tasks are executing as expected. It only executes every three seconds, but + * has the highest priority within the system so is guaranteed to get execution + * time. Any errors discovered by the check task are latched until the + * processor is reset. At the end of each cycle the check task sends either + * a pass or fail message to the 'print' task for display on the LCD. + * + * 2 - The print task + * The print task is the LCD 'gatekeeper'. That is, it is the only task that + * should access the LCD directly so is always guaranteed exclusive (and + * therefore consistent) access. The print task simply blocks on a queue + * to wait for messages from other tasks wishing to display text on the LCD. + * When a message arrives it displays its contents on the LCD then blocks to + * wait again. + */ + +/* ST includes. */ +#include "lcd.h" + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "Task.h" +#include "Queue.h" + +/* Demo application includes. */ +#include "ParTest.h" +#include "flash.h" +#include "integer.h" +#include "blocktim.h" +#include "BlockQ.h" +#include "comtest2.h" +#include "dynamic.h" + +/* Demo application task priorities. */ +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* How often should we check the other tasks? */ +#define mainCHECK_TASK_CYCLE_TIME ( 3000 ) + +/* The maximum offset into the pass and fail strings sent to the LCD. An +offset is used a simple method of using a different column each time a message +is written to the LCD. */ +#define mainMAX_WRITE_COLUMN ( 14 ) + +/* Baud rate used by the comtest tasks. */ +#define mainCOM_TEST_BAUD_RATE ( 19200 ) + +/* The LED used by the comtest tasks. See the comtest.c file for more +information. */ +#define mainCOM_TEST_LED ( 3 ) + +/* The number of messages that can be queued for display on the LCD at any one +time. */ +#define mainLCD_QUEUE_LENGTH ( 2 ) + +/* The time to wait when sending to mainLCD_QUEUE_LENGTH. */ +#define mainNO_DELAY ( 0 ) + +/*-----------------------------------------------------------*/ + +/* The type that is posted to the LCD queue. */ +typedef struct LCD_MESSAGE +{ + unsigned portCHAR *pucString; /* Points to the string to be displayed. */ + unsigned portCHAR ucLine; /* The line of the LCD that should be used. */ +} LCDMessage; + +/*-----------------------------------------------------------*/ + +/* + * The task that executes at the highest priority and checks the operation of + * all the other tasks in the system. See the description at the top of the + * file. + */ +static void vCheckTask( void *pvParameters ); + +/* + * ST provided routine to configure the processor. + */ +static void prvSetupHardware(void); + +/* + * The only task that should access the LCD. Other tasks wanting to write + * to the LCD should send a message of type LCDMessage containing the + * information to display to the print task. The print task simply blocks + * waiting for the arrival of such messages, displays the message, then blocks + * again. + */ +static void vPrintTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* The queue used to communicate with the LCD print task. */ +static xQueueHandle xLCDQueue; + +/*-----------------------------------------------------------*/ + +/* Create all the demo application tasks, then start the scheduler. */ +int main( void ) +{ + /* Perform any hardware setup necessary. */ + prvSetupHardware(); + vParTestInitialise(); + + /* Create the queue used to communicate with the LCD print task. */ + xLCDQueue = xQueueCreate( mainLCD_QUEUE_LENGTH, sizeof( LCDMessage ) ); + + /* Create the standard demo application tasks. See the WEB documentation + for more information on these tasks. */ + vCreateBlockTimeTasks(); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); + vStartDynamicPriorityTasks(); + vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + + /* Create the tasks defined within this file. */ + xTaskCreate( vPrintTask, ( signed portCHAR * ) "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL ); + xTaskCreate( vCheckTask, ( signed portCHAR * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + vTaskStartScheduler(); + + /* Execution will only reach here if there was insufficient heap to + start the scheduler. */ + return 0; +} +/*-----------------------------------------------------------*/ + +static void vCheckTask( void *pvParameters ) +{ +static unsigned portLONG ulErrorDetected = pdFALSE; +portTickType xLastExecutionTime; +unsigned portCHAR *ucErrorMessage = ( unsigned portCHAR * )" FAIL"; +unsigned portCHAR *ucSuccessMessage = ( unsigned portCHAR * )" PASS"; +unsigned portBASE_TYPE uxColumn = mainMAX_WRITE_COLUMN; +LCDMessage xMessage; + + /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() + works correctly. */ + xLastExecutionTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Wait until it is time for the next cycle. */ + vTaskDelayUntil( &xLastExecutionTime, mainCHECK_TASK_CYCLE_TIME ); + + /* Has an error been found in any of the standard demo tasks? */ + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + ulErrorDetected = pdTRUE; + } + + if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + ulErrorDetected = pdTRUE; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + ulErrorDetected = pdTRUE; + } + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + ulErrorDetected = pdTRUE; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + ulErrorDetected = pdTRUE; + } + + /* Calculate the LCD line on which we would like the message to + be displayed. The column variable is used for convenience as + it is incremented each cycle anyway. */ + xMessage.ucLine = ( unsigned portCHAR ) ( uxColumn & 0x01 ); + + /* The message displayed depends on whether an error was found or + not. Any discovered error is latched. Here the column variable + is used as an index into the text string as a simple way of moving + the text from column to column. */ + if( ulErrorDetected == pdFALSE ) + { + xMessage.pucString = ucSuccessMessage + uxColumn; + } + else + { + xMessage.pucString = ucErrorMessage + uxColumn; + } + + /* Send the message to the print task for display. */ + xQueueSend( xLCDQueue, ( void * ) &xMessage, mainNO_DELAY ); + + /* Make sure the message is printed in a different column the next + time around. */ + uxColumn--; + if( uxColumn == 0 ) + { + uxColumn = mainMAX_WRITE_COLUMN; + } + } +} + +/*-----------------------------------------------------------*/ + +static void vPrintTask( void *pvParameters ) +{ +LCDMessage xMessage; + + for( ;; ) + { + /* Wait until a message arrives. */ + while( xQueueReceive( xLCDQueue, ( void * ) &xMessage, portMAX_DELAY ) != pdPASS ); + + /* The message contains the text to display, and the line on which the + text should be displayed. */ + LCD_Clear(); + LCD_DisplayString( xMessage.ucLine, xMessage.pucString, BlackText ); + } +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware(void) +{ +ErrorStatus OSC4MStartUpStatus01; + + /* ST provided routine. */ + + /* MRCC system reset */ + MRCC_DeInit(); + + /* Wait for OSC4M start-up */ + OSC4MStartUpStatus01 = MRCC_WaitForOSC4MStartUp(); + + if(OSC4MStartUpStatus01 == SUCCESS) + { + /* Set HCLK to 60MHz */ + MRCC_HCLKConfig(MRCC_CKSYS_Div1); + + /* Set CKTIM to 60MHz */ + MRCC_CKTIMConfig(MRCC_HCLK_Div1); + + /* Set PCLK to 30MHz */ + MRCC_PCLKConfig(MRCC_CKTIM_Div2); + + /* Enable Flash Burst mode */ + CFG_FLASHBurstConfig(CFG_FLASHBurst_Enable); + + /* Set CK_SYS to 60 MHz */ + MRCC_CKSYSConfig(MRCC_CKSYS_OSC4MPLL, MRCC_PLL_Mul_15); + } + + /* GPIO pins optimized for 3V3 operation */ + MRCC_IOVoltageRangeConfig(MRCC_IOVoltageRange_3V3); + + /* GPIO clock source enable */ + MRCC_PeripheralClockConfig(MRCC_Peripheral_GPIO, ENABLE); + + /* EXTIT clock source enable */ + MRCC_PeripheralClockConfig(MRCC_Peripheral_EXTIT, ENABLE); + /* TB clock source enable */ + MRCC_PeripheralClockConfig(MRCC_Peripheral_TB, ENABLE); + + /* Initialize the demonstration menu */ + LCD_Init(); + + LCD_DisplayString(Line1, ( unsigned portCHAR * ) "www.FreeRTOS.org", BlackText); + LCD_DisplayString(Line2, ( unsigned portCHAR * ) " STR750 Demo ", BlackText); + + EIC_IRQCmd(ENABLE); +} +/*-----------------------------------------------------------*/ + diff --git a/20080212/Demo/ARM7_STR75x_GCC/rtosdemo.prj b/20080212/Demo/ARM7_STR75x_GCC/rtosdemo.prj new file mode 100644 index 000000000..88882784f --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_GCC/rtosdemo.prj @@ -0,0 +1,1594 @@ +RIDE Project File +File Version=3 +[BN] +Build=BN746-ST7-ARM-80C51-P1-STR750 +[Ref] +Ref=11 +[Type] +Type=0 +[Environment] +Begin Group CompEdit +EditCodeCoverage=0 +TestMakeDate=1 +Promptrebuild=0 +DebugMessage=1000 +Promptdirtyoptions=0 +Prompttoreloadfiles=0 +Promptsucsorfail=0 +Promptenddebug=1 +Promptsave=0 +End Group CompEdit +Begin Group Edit +DocExts=*.pdf;*.htm;*.doc +DocInChild=1 +InsertSpace=0 +Showinfo=1 +Showtool=1 +Showpath=1 +Promptbeforedelete=0 +Oemtoascii=0 +Decalage=4 +Undonumber=10 +TabStop=4 +End Group Edit +Begin Group Font +Height=12 +Name=courier new +Default=1 +End Group Font +Begin Group Colors +Data=14745599 +Code=15658705 +ColorBackground=1 +Error=255 +String=16711680 +Operator=8421504 +Key=0 +Comment=8421376 +Control=32768 +Numeric=16711680 +Identifier=8388608 +Highlight=1 +End Group Colors +End Options Environment + +[Directories] +Begin Group Directories +Source= +LibOpti=c:\devtools\RIDE\Lib\CCLib +List= +Object= +Lib=.;%RIDEDIR%\lib\STRX +Include=..\..\Source\include;.\STLibrary\inc;..\common\include;.;%RIDEDIR%\lib\STRX\include +End Group Directories +End Options Directories + +[Targets] +Number=1 + +Name=ARM +DllName=..\..\..\..\..\DEVTOOLS\RIDE\BIN\targetarm.dll +Begin Group ARM +HBAddr=400000 +FlashMap=0 +Interwork=1 +ThumbMode=0 +BootMode=0 +MicroIndex=0 +MicroName=STR750FV0 +LaunchMode=0 +End Group ARM + + +[Magics] +Number=0 + + +[Nets] +Nb Nets=0 + +[Tools] +Number=5 + +Path=..\..\..\..\..\DEVTOOLS\RIDE\BIN\aarmv32.dll +Name=AS-ARM +SrcExt=*.s +ObjExt=*.o +Target Translate=0 +Begin Options AS-ARM +Begin Group General +More= +Warning=0 +Labels=0 +Dwarf2=0 +BigEndian=0 +LittleEndian=1 +Thumb=0 +End Group General +End Options AS-ARM + +Path=..\..\..\..\..\DEVTOOLS\RIDE\BIN\ccomp51.dll +Name=CodeCompressor51 +SrcExt= +ObjExt= +Target Translate=2 +Begin Options CodeCompressor51 +Begin Group Save +SaveBIN=0 +SaveHEX=0 +SaveOMF=0 +End Group Save +Begin Group Peephole +Valid=1 +Peephole=%RIDEDIR%\EXAMPLES\8051\PEEP51.RPS +End Group Peephole +Begin Group Factorization +MaxFactoDeep=? +MaxFactoSz=? +MaxFactoNr=? +ConfirFacto=1 +End Group Factorization +Begin Group Inlining +MaxPostBlockNr=? +ConfirmPostBlock=0 +MaxInlineNr=? +ConfirmInline=1 +MaxPreBlockNr=? +ConfirmPreBlock=0 +End Group Inlining +Begin Group General +ModeDos=0 +More= +StandaloneAnchored=0 +StandaloneAsk=0 +StandaloneDiscard=1 +NewCode=0 +SameCode=1 +LogFile=0 +VerboseLevel=1 +Verbose=0 +ModeInteractive=0 +Add2Project=1 +AutoPeep=1 +AutoFacto=1 +AutoInline=1 +ModeAuto=1 +End Group General +End Options CodeCompressor51 + +Path=..\..\..\..\..\DEVTOOLS\RIDE\BIN\carmv32.dll +Name=GCC-ARM +SrcExt=*.c;*.h +ObjExt=*.o +Target Translate=0 +Begin Options GCC-ARM +Begin Group More +More=-fomit-frame-pointer +End Group More +Begin Group Warnings +Warnunused=1 +Warnswitch=1 +Warnshad=1 +Supress=0 +Warnall=1 +Pedantic=0 +End Group Warnings +Begin Group Optimisations +Size=4 +Optimlevel=0 +Inlinefunc=0 +Noinlining=0 +Allow=0 +End Group Optimisations +Begin Group Code +Packstruct=0 +Volatileg=0 +Volatile=0 +Shortdouble=0 +Shortenum=0 +End Group Code +Begin Group Debug +Temp=0 +Debug=1 +End Group Debug +Begin Group Defines +Defines=STR75X_GCC;THUMB_INTERWORK +End Group Defines +Begin Group Dialect +Signedchar=0 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+[Dim Views] +Nb Dim Views=13 +0 (0,0-0,0) +1 (0,0-0,0) +2 (0,0-0,0) +3 (0,0-0,0) +4 (76,125-823,634) +5 (553,156-783,399) +6 (220,230-941,725) +7 (0,0-0,0) +8 (0,0-0,0) +9 (0,0-0,0) +10 (0,0-0,0) +11 (0,0-0,0) +12 (0,0-0,0) + +[DebugTool] +Debug= + +[Project Rect] +(0,0-0,0) + +[LastSel] +LastAOF=c:\e\dev\freertos\demo\arm7_str75x_gcc\rtosdemo.elf + diff --git a/20080212/Demo/ARM7_STR75x_GCC/serial/serial.c b/20080212/Demo/ARM7_STR75x_GCC/serial/serial.c new file mode 100644 index 000000000..07bd082ee --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_GCC/serial/serial.c @@ -0,0 +1,245 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0. +*/ + + +/*----------------------------------------------------------- + * Components that can be compiled to either ARM or THUMB mode are + * contained in this file.c The ISR routines, which can only be compiled + * to ARM mode, are contained in serialISR.c. + *----------------------------------------------------------*/ + + + +/* Library includes. */ +#include "75x_uart.h" +#include "75x_gpio.h" +#include "75x_eic.h" +#include "75x_mrcc.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "queue.h" + +/* Demo application includes. */ +#include "serial.h" + +#define serINVALID_QUEUE ( ( xQueueHandle ) 0 ) +#define serNO_BLOCK ( ( portTickType ) 0 ) + +/*-----------------------------------------------------------*/ + +/* Queues used to hold received characters, and characters waiting to be +transmitted. */ +static xQueueHandle xRxedChars; +static xQueueHandle xCharsForTx; + +static volatile portBASE_TYPE xQueueEmpty = pdTRUE; + +/*-----------------------------------------------------------*/ + +/* The interrupt service routine - called from the assembly entry point. */ +void vSerialISR( void ); +void vConfigureQueues( xQueueHandle xQForRx, xQueueHandle xQForTx, volatile portBASE_TYPE *pxEmptyFlag ); + +/*-----------------------------------------------------------*/ + +/* + * See the serial2.h header file. + */ +xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) +{ +xComPortHandle xReturn; +UART_InitTypeDef UART_InitStructure; +GPIO_InitTypeDef GPIO_InitStructure; +EIC_IRQInitTypeDef EIC_IRQInitStructure; + + /* Create the queues used to hold Rx and Tx characters. */ + xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + + /* If the queues were created correctly then setup the serial port + hardware. */ + if( ( xRxedChars != serINVALID_QUEUE ) && ( xCharsForTx != serINVALID_QUEUE ) ) + { + + vConfigureQueues( xRxedChars, xCharsForTx, &xQueueEmpty ); + + portENTER_CRITICAL(); + { + /* Enable the UART0 Clock. */ + MRCC_PeripheralClockConfig( MRCC_Peripheral_UART0, ENABLE ); + + /* Configure the UART0_Tx as alternate function */ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11; + GPIO_Init(GPIO0, &GPIO_InitStructure); + + /* Configure the UART0_Rx as input floating */ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; + GPIO_Init(GPIO0, &GPIO_InitStructure); + + /* Configure UART0. */ + UART_InitStructure.UART_WordLength = UART_WordLength_8D; + UART_InitStructure.UART_StopBits = UART_StopBits_1; + UART_InitStructure.UART_Parity = UART_Parity_No; + UART_InitStructure.UART_BaudRate = ulWantedBaud; + UART_InitStructure.UART_HardwareFlowControl = UART_HardwareFlowControl_None; + UART_InitStructure.UART_Mode = UART_Mode_Tx_Rx; + UART_InitStructure.UART_TxFIFOLevel = UART_FIFOLevel_1_2; /* FIFO size 16 bytes, FIFO level 8 bytes */ + UART_InitStructure.UART_RxFIFOLevel = UART_FIFOLevel_1_2; /* FIFO size 16 bytes, FIFO level 8 bytes */ + UART_Init(UART0, &UART_InitStructure); + + /* Enable the UART0 */ + UART_Cmd(UART0, ENABLE); + + /* Configure the IEC for the UART interrupts. */ + EIC_IRQInitStructure.EIC_IRQChannelCmd = ENABLE; + EIC_IRQInitStructure.EIC_IRQChannel = UART0_IRQChannel; + EIC_IRQInitStructure.EIC_IRQChannelPriority = 1; + EIC_IRQInit(&EIC_IRQInitStructure); + + xQueueEmpty = pdTRUE; + UART_ITConfig( UART0, UART_IT_Transmit | UART_IT_Receive, ENABLE ); + } + portEXIT_CRITICAL(); + } + else + { + xReturn = ( xComPortHandle ) 0; + } + + /* This demo file only supports a single port but we have to return + something to comply with the standard demo header file. */ + return xReturn; +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) +{ + /* The port handle is not required as this driver only supports one port. */ + ( void ) pxPort; + + /* Get the next character from the buffer. Return false if no characters + are available, or arrive before xBlockTime expires. */ + if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) + { + return pdTRUE; + } + else + { + return pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength ) +{ +signed portCHAR *pxNext; + + /* A couple of parameters that this port does not use. */ + ( void ) usStringLength; + ( void ) pxPort; + + /* NOTE: This implementation does not handle the queue being full as no + block time is used! */ + + /* The port handle is not required as this driver only supports UART0. */ + ( void ) pxPort; + + /* Send each character in the string, one at a time. */ + pxNext = ( signed portCHAR * ) pcString; + while( *pxNext ) + { + xSerialPutChar( pxPort, *pxNext, serNO_BLOCK ); + pxNext++; + } +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) +{ +portBASE_TYPE xReturn; + + /* Place the character in the queue of characters to be transmitted. */ + portENTER_CRITICAL(); + { + if( xQueueEmpty == pdTRUE ) + { + UART0->DR = cOutChar; + xReturn = pdPASS; + } + else + { + if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) + { + xReturn = pdFAIL; + } + else + { + xReturn = pdPASS; + } + } + + xQueueEmpty = pdFALSE; + } + portEXIT_CRITICAL(); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +void vSerialClose( xComPortHandle xPort ) +{ + /* Not supported as not required by the demo application. */ +} +/*-----------------------------------------------------------*/ + + + + + + diff --git a/20080212/Demo/ARM7_STR75x_GCC/serial/serialISR.c b/20080212/Demo/ARM7_STR75x_GCC/serial/serialISR.c new file mode 100644 index 000000000..33375dde6 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_GCC/serial/serialISR.c @@ -0,0 +1,111 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/*----------------------------------------------------------- + * Components that can be compiled to either ARM or THUMB mode are + * contained in serial.c The ISR routines, which can only be compiled + * to ARM mode, are contained in this file. + *----------------------------------------------------------*/ + + + +/* Library includes. */ +#include "75x_uart.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "queue.h" + +static xQueueHandle xRxedChars; +static xQueueHandle xCharsForTx; +static portBASE_TYPE volatile *pxQueueEmpty; + +void vConfigureQueues( xQueueHandle xQForRx, xQueueHandle xQForTx, portBASE_TYPE volatile *pxEmptyFlag ) +{ + xRxedChars = xQForRx; + xCharsForTx = xQForTx; + pxQueueEmpty = pxEmptyFlag; +} +/*-----------------------------------------------------------*/ + +void vSerialISR( void ) +{ +signed portCHAR cChar; +portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByPost = pdFALSE; + + do + { + if( UART0->MIS & UART_IT_Transmit ) + { + /* The interrupt was caused by the THR becoming empty. Are there any + more characters to transmit? */ + if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE ) + { + /* A character was retrieved from the queue so can be sent to the + THR now. */ + UART0->DR = cChar; + } + else + { + *pxQueueEmpty = pdTRUE; + } + + UART_ClearITPendingBit( UART0, UART_IT_Transmit ); + } + + if( UART0->MIS & UART_IT_Receive ) + { + /* The interrupt was caused by a character being received. Grab the + character from the RHR and place it in the queue of received + characters. */ + cChar = UART0->DR; + xTaskWokenByPost = xQueueSendFromISR( xRxedChars, &cChar, xTaskWokenByPost ); + UART_ClearITPendingBit( UART0, UART_IT_Receive ); + } + } while( UART0->MIS ); + + /* If a task was woken by either a character being received or a character + being transmitted then we may need to switch to another task. */ + portEND_SWITCHING_ISR( ( xTaskWokenByPost || xTaskWokenByTx ) ); +} + + diff --git a/20080212/Demo/ARM7_STR75x_IAR/75x_init.s b/20080212/Demo/ARM7_STR75x_IAR/75x_init.s new file mode 100644 index 000000000..850cf11a6 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/75x_init.s @@ -0,0 +1,249 @@ +;******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +;* File Name : 75x_init.s +;* Author : MCD Application Team +;* Date First Issued : 03/10/2006 +;* Description : This module performs: +;* - Memory remapping (if required), +;* - Stack pointer initialisation for each mode , +;* - Interrupt Controller Initialisation +;* - Branches to ?main in the C library (which eventually +;* calls main()). +;* On reset, the ARM core starts up in Supervisor (SVC) mode, +;* in ARM state,with IRQ and FIQ disabled. +;******************************************************************************* +; History: +; 07/17/2006 : V1.0 +; 03/10/2006 : V0.1 +;******************************************************************************* +; THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +; CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************* + + IMPORT WAKUP_Addr ; imported from 75x_vect.s + + + + + ; Depending on Your Application, Disable or Enable the following Defines + ; ---------------------------------------------------------------------------- + ; SMI Bank0 configuration + ; ---------------------------------------------------------------------------- + ; If you need to accees the SMI Bank0 + ; uncomment next line + ;#define SMI_Bank0_EN + + ; ---------------------------------------------------------------------------- + ; Memory remapping + ; ---------------------------------------------------------------------------- + ;#define Remap_SRAM ; remap SRAM at address 0x00 + + ; ---------------------------------------------------------------------------- + ; EIC initialization + ; ---------------------------------------------------------------------------- + #define EIC_INIT ; Configure and Initialize EIC + +; Standard definitions of mode bits and interrupt (I & F) flags in PSRs +Mode_USR EQU 0x10 +Mode_FIQ EQU 0x11 +Mode_IRQ EQU 0x12 +Mode_SVC EQU 0x13 +Mode_ABT EQU 0x17 +Mode_UND EQU 0x1B +Mode_SYS EQU 0x1F + +I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled +F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled + + +; MRCC Register +MRCC_PCLKEN_Addr EQU 0x60000030 ; Peripheral Clock Enable register base address + +; CFG Register +CFG_GLCONF_Addr EQU 0x60000010 ; Global Configuration register base address +SRAM_mask EQU 0x0002 ; to remap RAM at 0x0 + +; GPIO Register +GPIOREMAP0R_Addr EQU 0xFFFFE420 +SMI_EN_Mask EQU 0x00000001 + +; SMI Register +SMI_CR1_Addr EQU 0x90000000 + +; EIC Registers offsets +EIC_Base_addr EQU 0xFFFFF800 ; EIC base address +ICR_off_addr EQU 0x00 ; Interrupt Control register offset +CIPR_off_addr EQU 0x08 ; Current Interrupt Priority Register offset +IVR_off_addr EQU 0x18 ; Interrupt Vector Register offset +FIR_off_addr EQU 0x1C ; Fast Interrupt Register offset +IER_off_addr EQU 0x20 ; Interrupt Enable Register offset +IPR_off_addr EQU 0x40 ; Interrupt Pending Bit Register offset +SIR0_off_addr EQU 0x60 ; Source Interrupt Register 0 + + +;--------------------------------------------------------------- +; ?program_start +;--------------------------------------------------------------- + MODULE ?program_start + SECTION IRQ_STACK:DATA:NOROOT(3) + SECTION FIQ_STACK:DATA:NOROOT(3) + SECTION UND_STACK:DATA:NOROOT(3) + SECTION ABT_STACK:DATA:NOROOT(3) + SECTION SVC_STACK:DATA:NOROOT(3) + SECTION CSTACK:DATA:NOROOT(3) + SECTION .text:CODE(2) + PUBLIC __iar_program_start + EXTERN ?main + CODE32 + + +__iar_program_start: + LDR pc, =NextInst + +NextInst +; Reset all Peripheral Clocks +; This is usefull only when using debugger to Reset\Run the application + + #ifdef SMI_Bank0_EN + LDR r0, =0x01000000 ; Disable peripherals clock (except GPIO) + #else + LDR r0, =0x00000000 ; Disable peripherals clock + #endif + LDR r1, =MRCC_PCLKEN_Addr + STR r0, [r1] + + #ifdef SMI_Bank0_EN + LDR r0, =0x1875623F ; Peripherals kept under reset (except GPIO) + #else + LDR r0, =0x1975623F ; Peripherals kept under reset + #endif + + STR r0, [r1,#4] + MOV r0, #0 + NOP ; Wait + NOP + NOP + NOP + STR r0, [r1,#4] ; Disable peripherals reset + +; Initialize stack pointer registers +; Enter each mode in turn and set up the stack pointer + + + MSR CPSR_c, #Mode_FIQ|I_Bit|F_Bit ; No interrupts + ldr sp,=SFE(FIQ_STACK) ; End of FIQ_STACK + + MSR CPSR_c, #Mode_IRQ|I_Bit|F_Bit ; No interrupts + ldr sp,=SFE(IRQ_STACK) ; End of IRQ_STACK + + MSR CPSR_c, #Mode_ABT|I_Bit|F_Bit ; No interrupts + ldr sp,=SFE(ABT_STACK) ; End of ABT_STACK + + MSR CPSR_c, #Mode_UND|I_Bit|F_Bit ; No interrupts + ldr sp,=SFE(UND_STACK) ; End of UND_STACK + + MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit ; No interrupts + ldr sp,=SFE(SVC_STACK) ; End of SVC_STACK + +; ------------------------------------------------------------------------------ +; Description : Enable SMI Bank0: enable GPIOs clock in MRCC_PCLKEN register, +; enable SMI alternate function in GPIO_REMAP register and enable +; Bank0 in SMI_CR1 register. +; ------------------------------------------------------------------------------ + #ifdef SMI_Bank0_EN + MOV r0, #0x01000000 + LDR r1, =MRCC_PCLKEN_Addr + STR r0, [r1] ; Enable GPIOs clock + + LDR r1, =GPIOREMAP0R_Addr + MOV r0, #SMI_EN_Mask + LDR r2, [r1] + ORR r2, r2, r0 + STR r2, [r1] ; Enable SMI alternate function + + LDR r0, =0x251 ; SMI Bank0 enabled, Prescaler = 2, Deselect Time = 5 + LDR r1, =SMI_CR1_Addr + STR r0, [r1] ; Configure CR1 register + LDR r0, =0x00 + STR r0, [r1,#4] ; Reset CR2 register + #endif + +; ------------------------------------------------------------------------------ +; Description : Remapping SRAM at address 0x00 after the application has +; started executing. +; ------------------------------------------------------------------------------ + #ifdef Remap_SRAM + MOV r0, #SRAM_mask + LDR r1, =CFG_GLCONF_Addr + LDR r2, [r1] ; Read GLCONF Register + BIC r2, r2, #0x03 ; Reset the SW_BOOT bits + ORR r2, r2, r0 ; Change the SW_BOOT bits + STR r2, [r1] ; Write GLCONF Register + #endif + +;------------------------------------------------------------------------------- +;Description : Initialize the EIC as following : +; - IRQ disabled +; - FIQ disabled +; - IVR contains the load PC opcode +; - All channels are disabled +; - All channels priority equal to 0 +; - All SIR registers contains offset to the related IRQ table entry +;------------------------------------------------------------------------------- + #ifdef EIC_INIT + LDR r3, =EIC_Base_addr + LDR r4, =0x00000000 + STR r4, [r3, #ICR_off_addr] ; Disable FIQ and IRQ + STR r4, [r3, #IER_off_addr] ; Disable all interrupts channels + + LDR r4, =0xFFFFFFFF + STR r4, [r3, #IPR_off_addr] ; Clear all IRQ pending bits + + LDR r4, =0x18 + STR r4, [r3, #FIR_off_addr] ; Disable FIQ channels and clear FIQ pending bits + + LDR r4, =0x00000000 + STR r4, [r3, #CIPR_off_addr] ; Reset the current priority register + + LDR r4, =0xE59F0000 ; Write the LDR pc,pc,#offset.. + STR r4, [r3, #IVR_off_addr] ; ..instruction code in IVR[31:16] + + + LDR r2,= 32 ; 32 Channel to initialize + LDR r0, =WAKUP_Addr ; Read the address of the IRQs address table + LDR r1, =0x00000FFF + AND r0,r0,r1 + LDR r5,=SIR0_off_addr ; Read SIR0 address + SUB r4,r0,#8 ; subtract 8 for prefetch + LDR r1, =0xF7E8 ; add the offset to the 0x00 address.. + ; ..(IVR address + 7E8 = 0x00) + ; 0xF7E8 used to complete the LDR pc,offset opcode + ADD r1,r4,r1 ; compute the jump offset +EIC_INI + MOV r4, r1, LSL #16 ; Left shift the result + STR r4, [r3, r5] ; Store the result in SIRx register + ADD r1, r1, #4 ; Next IRQ address + ADD r5, r5, #4 ; Next SIR + SUBS r2, r2, #1 ; Decrement the number of SIR registers to initialize + BNE EIC_INI ; If more then continue + + #endif + + +; --- Branch to C Library entry point + + IMPORT ?main + + B ?main ; use B not BL, because an application will never return this way + + + + + LTORG + + + END +;******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE***** diff --git a/20080212/Demo/ARM7_STR75x_IAR/75x_vect.s b/20080212/Demo/ARM7_STR75x_IAR/75x_vect.s new file mode 100644 index 000000000..aceda9657 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/75x_vect.s @@ -0,0 +1,882 @@ +;******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +;* File Name : 75x_vect.c +;* Author : MCD Application Team +;* Date First Issued : 03/10/2006 +;* Description : This file used to initialize the exception and IRQ +;* vectors, and to enter/return to/from exceptions handlers. +;******************************************************************************* +; History: +; 07/17/2006 : V1.0 +; 03/10/2006 : V0.1 +;******************************************************************************* +;* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +;* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************* + +#include "FreeRTOSConfig.h" +#include "ISR_Support.h" + + + PROGRAM ?RESET + SECTION .intvec:CODE(2) + CODE32 + +EIC_base_addr EQU 0xFFFFF800 ; EIC base address +CICR_off_addr EQU 0x04 ; Current Interrupt Channel Register +IVR_off_addr EQU 0x18 ; Interrupt Vector Register +IPR_off_addr EQU 0x40 ; Interrupt Pending Register + + +;******************************************************************************* +; Import the __program_start address from 75x_init.s +;******************************************************************************* + + IMPORT __iar_program_start + + + +;******************************************************************************* +; Import exception handlers +;******************************************************************************* + + IMPORT Undefined_Handler + IMPORT SWI_Handler + IMPORT Prefetch_Handler + IMPORT Abort_Handler + IMPORT FIQ_Handler + +;******************************************************************************* +; Import IRQ handlers from 75x_it.c +;******************************************************************************* + + IMPORT WAKUP_IRQHandler + IMPORT TIM2_OC2_IRQHandler + IMPORT TIM2_OC1_IRQHandler + IMPORT TIM2_IC12_IRQHandler + IMPORT TIM2_UP_IRQHandler + IMPORT TIM1_OC2_IRQHandler + IMPORT TIM1_OC1_IRQHandler + IMPORT TIM1_IC12_IRQHandler + IMPORT TIM1_UP_IRQHandler + IMPORT TIM0_OC2_IRQHandler + IMPORT TIM0_OC1_IRQHandler + IMPORT TIM0_IC12_IRQHandler + IMPORT TIM0_UP_IRQHandler + IMPORT PWM_OC123_IRQHandler + IMPORT PWM_EM_IRQHandler + IMPORT PWM_UP_IRQHandler + IMPORT I2C_IRQHandler + IMPORT SSP1_IRQHandler + IMPORT SSP0_IRQHandler + IMPORT UART2_IRQHandler + IMPORT UART1_IRQHandler + IMPORT vSerialISR + IMPORT CAN_IRQHandler + IMPORT USB_LP_IRQHandler + IMPORT USB_HP_IRQHandler + IMPORT ADC_IRQHandler + IMPORT DMA_IRQHandler + IMPORT EXTIT_IRQHandler + IMPORT MRCC_IRQHandler + IMPORT FLASHSMI_IRQHandler + IMPORT RTC_IRQHandler + IMPORT TB_IRQHandler + IMPORT vPortPreemptiveTick + IMPORT vPortYieldProcessor + IMPORT UART0_IRQHandler + +;******************************************************************************* +; Export Peripherals IRQ handlers table address +;******************************************************************************* + + EXPORT WAKUP_Addr + +;******************************************************************************* +; Exception vectors +;******************************************************************************* + + + LDR PC, Reset_Addr + LDR PC, Undefined_Addr + LDR PC, SWI_Addr + LDR PC, Prefetch_Addr + LDR PC, Abort_Addr + NOP ; Reserved vector + LDR PC, IRQ_Addr + LDR PC, FIQ_Addr + +;******************************************************************************* +; Exception handlers address table +;******************************************************************************* + +Reset_Addr DCD __iar_program_start +Undefined_Addr DCD UndefinedHandler +SWI_Addr DCD vPortYieldProcessor +Prefetch_Addr DCD PrefetchAbortHandler +Abort_Addr DCD DataAbortHandler + DCD 0 ; Reserved vector +IRQ_Addr DCD IRQHandler +FIQ_Addr DCD FIQHandler + +;******************************************************************************* +; Peripherals IRQ handlers address table +;******************************************************************************* + +WAKUP_Addr DCD WAKUPIRQHandler +TIM2_OC2_Addr DCD TIM2_OC2IRQHandler +TIM2_OC1_Addr DCD TIM2_OC1IRQHandler +TIM2_IC12_Addr DCD TIM2_IC12IRQHandler +TIM2_UP_Addr DCD TIM2_UPIRQHandler +TIM1_OC2_Addr DCD TIM1_OC2IRQHandler +TIM1_OC1_Addr DCD TIM1_OC1IRQHandler +TIM1_IC12_Addr DCD TIM1_IC12IRQHandler +TIM1_UP_Addr DCD TIM1_UPIRQHandler +TIM0_OC2_Addr DCD TIM0_OC2IRQHandler +TIM0_OC1_Addr DCD TIM0_OC1IRQHandler +TIM0_IC12_Addr DCD TIM0_IC12IRQHandler +TIM0_UP_Addr DCD TIM0_UPIRQHandler +PWM_OC123_Addr DCD PWM_OC123IRQHandler +PWM_EM_Addr DCD PWM_EMIRQHandler +PWM_UP_Addr DCD PWM_UPIRQHandler +I2C_Addr DCD I2CIRQHandler +SSP1_Addr DCD SSP1IRQHandler +SSP0_Addr DCD SSP0IRQHandler +UART2_Addr DCD UART2IRQHandler +UART1_Addr DCD UART1IRQHandler +UART0_Addr DCD vSerialISR +CAN_Addr DCD CANIRQHandler +USB_LP_Addr DCD USB_LPIRQHandler +USB_HP_Addr DCD USB_HPIRQHandler +ADC_Addr DCD ADCIRQHandler +DMA_Addr DCD DMAIRQHandler +EXTIT_Addr DCD EXTITIRQHandler +MRCC_Addr DCD MRCCIRQHandler +FLASHSMI_Addr DCD FLASHSMIIRQHandler +RTC_Addr DCD RTCIRQHandler +TB_Addr DCD vPortPreemptiveTick + +;******************************************************************************* +; Exception Handlers +;******************************************************************************* + +;******************************************************************************* +;* Macro Name : SaveContext +;* Description : This macro used to save the context before entering +;* an exception handler. +;* Input : The range of registers to store. +;* Output : none +;******************************************************************************* +SaveContext MACRO reg1,reg2 + STMFD sp!,{reg1-reg2,lr} ; Save The workspace plus the current return + ; address lr_ mode into the stack. + MRS r1,spsr ; Save the spsr_mode into r1. + STMFD sp!,{r1} ; Save spsr. + ENDM + +;******************************************************************************* +;* Macro Name : RestoreContext +;* Description : This macro used to restore the context to return from +;* an exception handler and continue the program execution. +;* Input : The range of registers to restore. +;* Output : none +;******************************************************************************* +RestoreContext MACRO reg1,reg2 + LDMFD sp!,{r1} ; Restore the saved spsr_mode into r1. + MSR spsr_cxsf,r1 ; Restore spsr_mode. + LDMFD sp!,{reg1-reg2,pc}^; Return to the instruction following... + ; ...the exception interrupt. + ENDM + +;******************************************************************************* +;* Function Name : UndefinedHandler +;* Description : This function called when undefined instruction exception +;* is entered. +;* Input : none +;* Output : none +;******************************************************************************* +UndefinedHandler + SaveContext r0,r12 ; Save the workspace plus the current + ; return address lr_ und and spsr_und. + ldr r0,=Undefined_Handler + ldr lr,=Undefined_Handler_end + bx r0 ;Branch to Undefined_Handler +Undefined_Handler_end: + RestoreContext r0,r12 ; Return to the instruction following... + ; ...the undefined instruction. + +;******************************************************************************* +;* Function Name : SWIHandler +;* Description : This function called when SWI instruction executed. +;* Input : none +;* Output : none +;******************************************************************************* +SWIHandler + SaveContext r0,r12 ; Save the workspace plus the current + ; return address lr_ svc and spsr_svc. + ldr r0,= SWI_Handler + ldr lr,= SWI_Handler_end + bx r0 ;Branch to SWI_Handler +SWI_Handler_end: + RestoreContext r0,r12 ; Return to the instruction following... + ; ...the SWI instruction. + +;******************************************************************************* +;* Function Name : IRQHandler +;* Description : This function called when IRQ exception is entered. +;* Input : none +;* Output : none +;******************************************************************************* +IRQHandler + portSAVE_CONTEXT ; Save the context of the current task. + + LDR r0, =EIC_base_addr + LDR r1, =IVR_off_addr + LDR lr, =ReturnAddress ; Load the return address. + ADD pc,r0,r1 ; Branch to the IRQ handler. +ReturnAddress + LDR r0, =EIC_base_addr + LDR r2, [r0, #CICR_off_addr] ; Get the IRQ channel number + MOV r3,#1 + MOV r3,r3,LSL r2 + STR r3,[r0, #IPR_off_addr] ; Clear the corresponding IPR bit. + + portRESTORE_CONTEXT ; Restore the context of the selected task. + + +;******************************************************************************* +;* Function Name : PrefetchAbortHandler +;* Description : This function called when Prefetch Abort exception is entered. +;* Input : none +;* Output : none +;******************************************************************************* +PrefetchAbortHandler + SUB lr,lr,#4 ; Update the link register. + SaveContext r0,r7 ; Save the workspace plus the current + ; return address lr_abt and spsr_abt. + ldr r0,= Prefetch_Handler + ldr lr,= Prefetch_Handler_end + bx r0 ;Branch to Prefetch_Handler +Prefetch_Handler_end: + RestoreContext r0,r7 ; Return to the instruction following that... + ; ...has generated the prefetch abort exception. + +;******************************************************************************* +;* Function Name : DataAbortHandler +;* Description : This function is called when Data Abort exception is entered. +;* Input : none +;* Output : none +;******************************************************************************* +DataAbortHandler + SUB lr,lr,#8 ; Update the link register. + SaveContext r0,r12 ; Save the workspace plus the current + ; return address lr_ abt and spsr_abt. + ldr r0,= Abort_Handler + ldr lr,= Abort_Handler_end + bx r0 ;Branch to Abort_Handler +Abort_Handler_end: + RestoreContext r0,r12 ; Return to the instruction following that... + ; ...has generated the data abort exception. + +;******************************************************************************* +;* Function Name : FIQHandler +;* Description : This function is called when FIQ exception is entered. +;* Input : none +;* Output : none +;******************************************************************************* +FIQHandler + SUB lr,lr,#4 ; Update the link register. + SaveContext r0,r7 ; Save the workspace plus the current + ; return address lr_ fiq and spsr_fiq. + ldr r0,= FIQ_Handler + ldr lr,= FIQ_Handler_end + bx r0 ;Branch to FIQ_Handler +FIQ_Handler_end: + RestoreContext r0,r7 ; Restore the context and return to the... + ; ...program execution. + +;******************************************************************************* +;* Macro Name : IRQ_to_SYS +;* Description : This macro used to switch form IRQ mode to SYS mode. +;* Input : none. +;* Output : none +;******************************************************************************* +IRQ_to_SYS MACRO + MSR cpsr_c,#0x1F + STMFD sp!,{lr} + ENDM + +;******************************************************************************* +;* Macro Name : SYS_to_IRQ +;* Description : This macro used to switch from SYS mode to IRQ mode. +;* Input : none. +;* Output : none +;******************************************************************************* +SYS_to_IRQ MACRO + LDMFD sp!,{lr} + MSR cpsr_c,#0xD2 + MOV pc,lr + ENDM + +;******************************************************************************* +;* Function Name : WAKUPIRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the WAKUP_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the WAKUP_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +WAKUPIRQHandler + IRQ_to_SYS + ldr r0,=WAKUP_IRQHandler + ldr lr,=WAKUP_IRQHandler_end + bx r0 +WAKUP_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : TIM2_OC2IRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the TIM2_OC2_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the TIM2_OC2_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +TIM2_OC2IRQHandler + IRQ_to_SYS + ldr r0,=TIM2_OC2_IRQHandler + ldr lr,=TIM2_OC2_IRQHandler_end + bx r0 +TIM2_OC2_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : TIM2_OC1IRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the TIM2_OC1_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the TIM2_OC1_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +TIM2_OC1IRQHandler + IRQ_to_SYS + ldr r0,=TIM2_OC1_IRQHandler + ldr lr,=TIM2_OC1_IRQHandler_end + bx r0 +TIM2_OC1_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : TIM2_IC12IRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the TIM2_IC12_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the TIM2_IC12_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +TIM2_IC12IRQHandler + IRQ_to_SYS + ldr r0,=TIM2_IC12_IRQHandler + ldr lr,=TIM2_IC12_IRQHandler_end + bx r0 +TIM2_IC12_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : TIM2_UPIRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the TIM2_UP_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the TIM2_UP_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +TIM2_UPIRQHandler + IRQ_to_SYS + ldr r0,=TIM2_UP_IRQHandler + ldr lr,=TIM2_UP_IRQHandler_end + bx r0 +TIM2_UP_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : TIM1_OC2IRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the TIM1_OC2_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the TIM1_OC2_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +TIM1_OC2IRQHandler + IRQ_to_SYS + ldr r0,=TIM1_OC2_IRQHandler + ldr lr,=TIM1_OC2_IRQHandler_end + bx r0 +TIM1_OC2_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : TIM1_OC1IRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the TIM1_OC1_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the TIM1_OC1_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +TIM1_OC1IRQHandler + IRQ_to_SYS + ldr r0,=TIM1_OC1_IRQHandler + ldr lr,=TIM1_OC1_IRQHandler_end + bx r0 +TIM1_OC1_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : TIM1_IC12IRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the TIM1_IC12_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the TIM1_IC12_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +TIM1_IC12IRQHandler + IRQ_to_SYS + ldr r0,=TIM1_IC12_IRQHandler + ldr lr,=TIM1_IC12_IRQHandler_end + bx r0 +TIM1_IC12_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : TIM1_UPIRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the TIM1_UP_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the TIM1_UP_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +TIM1_UPIRQHandler + IRQ_to_SYS + ldr r0,=TIM1_UP_IRQHandler + ldr lr,=TIM1_UP_IRQHandler_end + bx r0 +TIM1_UP_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : TIM0_OC2IRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the TIM0_OC2_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the TIM0_OC2_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +TIM0_OC2IRQHandler + IRQ_to_SYS + ldr r0,=TIM0_OC2_IRQHandler + ldr lr,=TIM0_OC2_IRQHandler_end + bx r0 +TIM0_OC2_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : TIM0_OC1IRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the TIM0_OC1_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the TIM0_OC1_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +TIM0_OC1IRQHandler + IRQ_to_SYS + ldr r0,=TIM0_OC1_IRQHandler + ldr lr,=TIM0_OC1_IRQHandler_end + bx r0 +TIM0_OC1_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : TIM0_IC12IRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the TIM0_IC12_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the TIM0_IC12_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +TIM0_IC12IRQHandler + IRQ_to_SYS + ldr r0,=TIM0_IC12_IRQHandler + ldr lr,=TIM0_IC12_IRQHandler_end + bx r0 +TIM0_IC12_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : TIM0_UPIRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the TIM0_UP_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the TIM0_UP_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +TIM0_UPIRQHandler + IRQ_to_SYS + ldr r0,=TIM0_UP_IRQHandler + ldr lr,=TIM0_UP_IRQHandler_end + bx r0 +TIM0_UP_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : PWM_OC123IRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the PWM_OC123_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the PWM_OC123_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +PWM_OC123IRQHandler + IRQ_to_SYS + ldr r0,=PWM_OC123_IRQHandler + ldr lr,=PWM_OC123_IRQHandler_end + bx r0 +PWM_OC123_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : PWM_EMIRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the PWM_EM_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the PWM_EM_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +PWM_EMIRQHandler + IRQ_to_SYS + ldr r0,=PWM_EM_IRQHandler + ldr lr,=PWM_EM_IRQHandler_end + bx r0 +PWM_EM_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : PWM_UPIRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the PWM_UP_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the PWM_UP_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +PWM_UPIRQHandler + IRQ_to_SYS + ldr r0,=PWM_UP_IRQHandler + ldr lr,=PWM_UP_IRQHandler_end + bx r0 +PWM_UP_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : I2CIRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the I2C_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the I2C_IRQHandler function +;* termination. +;* Input : none +;* Output : none +;******************************************************************************* +I2CIRQHandler + IRQ_to_SYS + ldr r0,=I2C_IRQHandler + ldr lr,=I2C_IRQHandler_end + bx r0 +I2C_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : SSP1IRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the SSP1_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the SSP1_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +SSP1IRQHandler + IRQ_to_SYS + ldr r0,=SSP1_IRQHandler + ldr lr,=SSP1_IRQHandler_end + bx r0 +SSP1_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : SSP0IRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the SSP0_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the SSP0_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +SSP0IRQHandler + IRQ_to_SYS + ldr r0,=SSP0_IRQHandler + ldr lr,=SSP0_IRQHandler_end + bx r0 +SSP0_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : UART2IRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the UART2_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the UART2_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +UART2IRQHandler + IRQ_to_SYS + ldr r0,=UART2_IRQHandler + ldr lr,=UART2_IRQHandler_end + bx r0 +UART2_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : UART1IRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the UART1_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the UART1_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +UART1IRQHandler + IRQ_to_SYS + ldr r0,=UART1_IRQHandler + ldr lr,=UART1_IRQHandler_end + bx r0 +UART1_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : UART0IRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the UART0_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the UART0_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +UART0IRQHandler + IRQ_to_SYS + ldr r0,=UART0_IRQHandler + ldr lr,=UART0_IRQHandler_end + bx r0 +UART0_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : CANIRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the CAN_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the CAN_IRQHandler function +;* termination. +;* Input : none +;* Output : none +;******************************************************************************* +CANIRQHandler + IRQ_to_SYS + ldr r0,=CAN_IRQHandler + ldr lr,=CAN_IRQHandler_end + bx r0 +CAN_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : USB_LPIRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the USB_LP_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the USB_LP_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +USB_LPIRQHandler + IRQ_to_SYS + ldr r0,=USB_LP_IRQHandler + ldr lr,=USB_LP_IRQHandler_end + bx r0 +USB_LP_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : USB_HPIRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the USB_HP_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the USB_HP_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +USB_HPIRQHandler + IRQ_to_SYS + ldr r0,=USB_HP_IRQHandler + ldr lr,=USB_HP_IRQHandler_end + bx r0 +USB_HP_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : ADCIRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the ADC_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the ADC_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +ADCIRQHandler + IRQ_to_SYS + ldr r0,=ADC_IRQHandler + ldr lr,=ADC_IRQHandler_end + bx r0 +ADC_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : DMAIRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the DMA_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the DMA_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +DMAIRQHandler + IRQ_to_SYS + ldr r0,=DMA_IRQHandler + ldr lr,=DMA_IRQHandler_end + bx r0 +DMA_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : EXTITIRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the EXTIT_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the EXTIT_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +EXTITIRQHandler + IRQ_to_SYS + ldr r0,=EXTIT_IRQHandler + ldr lr,=EXTIT_IRQHandler_end + bx r0 +EXTIT_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : MRCCIRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the MRCC_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the MRCC_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +MRCCIRQHandler + IRQ_to_SYS + ldr r0,=MRCC_IRQHandler + ldr lr,=MRCC_IRQHandler_end + bx r0 +MRCC_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : FLASHSMIIRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the FLASHSMI_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the FLASHSMI_IRQHandler +;* function termination. +;* Input : none +;* Output : none +;******************************************************************************* +FLASHSMIIRQHandler + IRQ_to_SYS + ldr r0,=FLASHSMI_IRQHandler + ldr lr,=FLASHSMI_IRQHandler_end + bx r0 +FLASHSMI_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : RTCIRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the RTC_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the RTC_IRQHandler function +;* termination. +;* Input : none +;* Output : none +;******************************************************************************* +RTCIRQHandler + IRQ_to_SYS + ldr r0,=RTC_IRQHandler + ldr lr,=RTC_IRQHandler_end + bx r0 +RTC_IRQHandler_end: + SYS_to_IRQ + +;******************************************************************************* +;* Function Name : TBIRQHandler +;* Description : This function used to switch to SYS mode before entering +;* the TB_IRQHandler function located in 75x_it.c. +;* Then to return to IRQ mode after the TB_IRQHandler function +;* termination. +;* Input : none +;* Output : none +;******************************************************************************* +TBIRQHandler + IRQ_to_SYS + ldr r0,=TB_IRQHandler + ldr lr,=TB_IRQHandler_end + bx r0 +TB_IRQHandler_end: + SYS_to_IRQ + + LTORG + + END +;******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE***** + + + + + + + + + + + diff --git a/20080212/Demo/ARM7_STR75x_IAR/FreeRTOSConfig.h b/20080212/Demo/ARM7_STR75x_IAR/FreeRTOSConfig.h new file mode 100644 index 000000000..187d8d8a8 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/FreeRTOSConfig.h @@ -0,0 +1,85 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 60000000 ) /* Timer clock. */ +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 100 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) 12800 ) +#define configMAX_TASK_NAME_LEN ( 16 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/ARM7_STR75x_IAR/ParTest/ParTest.c b/20080212/Demo/ARM7_STR75x_IAR/ParTest/ParTest.c new file mode 100644 index 000000000..85766ae12 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/ParTest/ParTest.c @@ -0,0 +1,147 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* Library includes. */ +#include "75x_GPIO.h" +#include "75x_map.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* Demo application includes. */ +#include "partest.h" + +/*----------------------------------------------------------- + * Simple parallel port IO routines for the LED's + *-----------------------------------------------------------*/ + +#define partstNUM_LEDS 4 + +typedef struct GPIOMAP +{ + GPIO_TypeDef *pxPort; + unsigned portLONG ulPin; + unsigned portLONG ulValue; +} GPIO_MAP; + +static GPIO_MAP xLEDMap[ partstNUM_LEDS ] = +{ + { ( GPIO_TypeDef * )GPIO1_BASE, GPIO_Pin_1, 0UL }, + { ( GPIO_TypeDef * )GPIO0_BASE, GPIO_Pin_16, 0UL }, + { ( GPIO_TypeDef * )GPIO2_BASE, GPIO_Pin_18, 0UL }, + { ( GPIO_TypeDef * )GPIO2_BASE, GPIO_Pin_19, 0UL } +}; + +/*-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ +GPIO_InitTypeDef GPIO_InitStructure ; + + /* Configure the bits used to flash LED's on port 1 as output. */ + + /* Configure LED3 */ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_16; + GPIO_Init(GPIO0,&GPIO_InitStructure); + + /* Configure LED2 */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1; + GPIO_Init(GPIO1, &GPIO_InitStructure); + + /* Configure LED4 and LED5 */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_18 | GPIO_Pin_19; + GPIO_Init(GPIO2, &GPIO_InitStructure); + + vParTestSetLED( 0, 0 ); + vParTestSetLED( 1, 0 ); + vParTestSetLED( 2, 0 ); + vParTestSetLED( 3, 0 ); +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ + if( uxLED < partstNUM_LEDS ) + { + portENTER_CRITICAL(); + { + if( xValue ) + { + GPIO_WriteBit( xLEDMap[ uxLED ].pxPort, xLEDMap[ uxLED ].ulPin, Bit_RESET ); + xLEDMap[ uxLED ].ulValue = 0; + } + else + { + GPIO_WriteBit( xLEDMap[ uxLED ].pxPort, xLEDMap[ uxLED ].ulPin, Bit_SET ); + xLEDMap[ uxLED ].ulValue = 1; + } + } + portEXIT_CRITICAL(); + } +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ + if( uxLED < partstNUM_LEDS ) + { + portENTER_CRITICAL(); + { + if( xLEDMap[ uxLED ].ulValue == 1 ) + { + GPIO_WriteBit( xLEDMap[ uxLED ].pxPort, xLEDMap[ uxLED ].ulPin, Bit_RESET ); + xLEDMap[ uxLED ].ulValue = 0; + } + else + { + GPIO_WriteBit( xLEDMap[ uxLED ].pxPort, xLEDMap[ uxLED ].ulPin, Bit_SET ); + xLEDMap[ uxLED ].ulValue = 1; + } + } + portEXIT_CRITICAL(); + } +} + + + + diff --git a/20080212/Demo/ARM7_STR75x_IAR/RTOSDemo.ewd b/20080212/Demo/ARM7_STR75x_IAR/RTOSDemo.ewd new file mode 100644 index 000000000..324305346 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/RTOSDemo.ewd @@ -0,0 +1,1225 @@ + + + + 1 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 15 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IARROM_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + JLINK_ID + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 1 + 1 + 1 + + + + + + + + MACRAIGOR_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin + 0 + + + + + Release + + ARM + + 1 + + C-SPY + 2 + + 15 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IARROM_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + JLINK_ID + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 1 + 1 + 1 + + + + + + + + MACRAIGOR_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin + 1 + + + + + + diff --git a/20080212/Demo/ARM7_STR75x_IAR/RTOSDemo.ewp b/20080212/Demo/ARM7_STR75x_IAR/RTOSDemo.ewp new file mode 100644 index 000000000..de0c80517 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/RTOSDemo.ewp @@ -0,0 +1,1629 @@ + + + + 1 + + Debug + + ARM + + 1 + + General + 3 + + 14 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 19 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 7 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 5 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 1 + + General + 3 + + 14 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 19 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 7 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 5 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Demo Source + + $PROJ_DIR$\..\Common\Minimal\BlockQ.c + + + $PROJ_DIR$\..\Common\Minimal\blocktim.c + + + $PROJ_DIR$\..\Common\Minimal\comtest.c + + + $PROJ_DIR$\..\Common\Minimal\dynamic.c + + + $PROJ_DIR$\..\Common\Minimal\flash.c + + + $PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c + + + $PROJ_DIR$\..\Common\Minimal\integer.c + + + $PROJ_DIR$\STLibrary\src\lcd.c + + + $PROJ_DIR$\main.c + + + $PROJ_DIR$\ParTest\ParTest.c + + + $PROJ_DIR$\serial\serial.c + + + + Library Source + + $PROJ_DIR$\STLibrary\src\75x_cfg.c + + + $PROJ_DIR$\STLibrary\src\75x_eic.c + + + $PROJ_DIR$\STLibrary\src\75x_gpio.c + + + $PROJ_DIR$\STLibrary\src\75x_it.c + + + $PROJ_DIR$\STLibrary\src\75x_lib.c + + + $PROJ_DIR$\STLibrary\src\75x_mrcc.c + + + $PROJ_DIR$\STLibrary\src\75x_tb.c + + + $PROJ_DIR$\STLibrary\src\75x_uart.c + + + + RTOS Source + + $PROJ_DIR$\..\..\Source\list.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\STR75x\port.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\STR75x\portasm.s79 + + + $PROJ_DIR$\..\..\Source\queue.c + + + $PROJ_DIR$\..\..\Source\tasks.c + + + + startup + + $PROJ_DIR$\75x_init.s + + + $PROJ_DIR$\75x_vect.s + + + + + diff --git a/20080212/Demo/ARM7_STR75x_IAR/RTOSDemo.eww b/20080212/Demo/ARM7_STR75x_IAR/RTOSDemo.eww new file mode 100644 index 000000000..239a9381e --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/RTOSDemo.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\RTOSDemo.ewp + + + + + diff --git a/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_adc.h b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_adc.h new file mode 100644 index 000000000..bce23f731 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_adc.h @@ -0,0 +1,177 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_adc.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* ADC software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_ADC_H +#define __75x_ADC_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* ADC Init structure definition */ +typedef struct +{ + u16 ADC_ConversionMode; + u16 ADC_ExtTrigger; + u16 ADC_AutoClockOff; + u8 ADC_SamplingPrescaler; + u8 ADC_ConversionPrescaler; + u8 ADC_FirstChannel; + u8 ADC_ChannelNumber; + }ADC_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* ADC control status flags */ +#define ADC_FLAG_ECH 0x0001 +#define ADC_FLAG_EOC 0x0002 +#define ADC_FLAG_JECH 0x0004 +#define ADC_FLAG_JEOC 0x0008 +#define ADC_FLAG_AnalogWatchdog0_LowThreshold 0x0010 +#define ADC_FLAG_AnalogWatchdog0_HighThreshold 0x0020 +#define ADC_FLAG_AnalogWatchdog1_LowThreshold 0x0040 +#define ADC_FLAG_AnalogWatchdog1_HighThreshold 0x0080 +#define ADC_FLAG_AnalogWatchdog2_LowThreshold 0x0100 +#define ADC_FLAG_AnalogWatchdog2_HighThreshold 0x0200 +#define ADC_FLAG_AnalogWatchdog3_LowThreshold 0x0400 +#define ADC_FLAG_AnalogWatchdog3_HighThreshold 0x0800 + +/* ADC Interrupt sources */ +#define ADC_IT_ECH 0x0001 +#define ADC_IT_EOC 0x0002 +#define ADC_IT_JECH 0x0004 +#define ADC_IT_JEOC 0x0008 +#define ADC_IT_AnalogWatchdog0_LowThreshold 0x0010 +#define ADC_IT_AnalogWatchdog0_HighThreshold 0x0020 +#define ADC_IT_AnalogWatchdog1_LowThreshold 0x0040 +#define ADC_IT_AnalogWatchdog1_HighThreshold 0x0080 +#define ADC_IT_AnalogWatchdog2_LowThreshold 0x0100 +#define ADC_IT_AnalogWatchdog2_HighThreshold 0x0200 +#define ADC_IT_AnalogWatchdog3_LowThreshold 0x0400 +#define ADC_IT_AnalogWatchdog3_HighThreshold 0x0800 +#define ADC_IT_ALL 0x0FFF + +/* ADC Watchdogs Thresholds */ +#define ADC_AnalogWatchdog0 0x0030 +#define ADC_AnalogWatchdog1 0x00C0 +#define ADC_AnalogWatchdog2 0x0300 +#define ADC_AnalogWatchdog3 0x0C00 + +/* ADC Channels */ +#define ADC_CHANNEL0 0x0 +#define ADC_CHANNEL1 0x1 +#define ADC_CHANNEL2 0x2 +#define ADC_CHANNEL3 0x3 +#define ADC_CHANNEL4 0x4 +#define ADC_CHANNEL5 0x5 +#define ADC_CHANNEL6 0x6 +#define ADC_CHANNEL7 0x7 +#define ADC_CHANNEL8 0x8 +#define ADC_CHANNEL9 0x9 +#define ADC_CHANNEL10 0xA +#define ADC_CHANNEL11 0xB +#define ADC_CHANNEL12 0xC +#define ADC_CHANNEL13 0xD +#define ADC_CHANNEL14 0xE +#define ADC_CHANNEL15 0xF + +/* ADC DMA Channels */ +#define ADC_DMA_CHANNEL0 0x0001 +#define ADC_DMA_CHANNEL1 0x0002 +#define ADC_DMA_CHANNEL2 0x0004 +#define ADC_DMA_CHANNEL3 0x0008 +#define ADC_DMA_CHANNEL4 0x0010 +#define ADC_DMA_CHANNEL5 0x0020 +#define ADC_DMA_CHANNEL6 0x0040 +#define ADC_DMA_CHANNEL7 0x0080 +#define ADC_DMA_CHANNEL8 0x0100 +#define ADC_DMA_CHANNEL9 0x0200 +#define ADC_DMA_CHANNEL10 0x0400 +#define ADC_DMA_CHANNEL11 0x0800 +#define ADC_DMA_CHANNEL12 0x1000 +#define ADC_DMA_CHANNEL13 0x2000 +#define ADC_DMA_CHANNEL14 0x4000 +#define ADC_DMA_CHANNEL15 0x8000 + +/* Trigger conversion detection */ +#define ADC_ExtTrigger_LowLevel 0x4FFF +#define ADC_ExtTrigger_HighLevel 0x5000 +#define ADC_ExtTrigger_FallingEdge 0x6000 +#define ADC_ExtTrigger_RisingEdge 0x7000 +#define ADC_ExtTrigger_Disable 0x8FFF + +/* DMA enable config */ +#define ADC_DMA_ExtTrigger_HighLevel 0x6000 +#define ADC_DMA_ExtTrigger_LowLevel 0x4FFF +#define ADC_DMA_Enable 0x8000 +#define ADC_DMA_Disable 0x3FFF + +/* Injected Trigger conversion detection */ +#define ADC_Injec_ExtTrigger_RisingEdge 0x6000 +#define ADC_Injec_ExtTrigger_FallingEdge 0xDFFF +#define ADC_Injec_ExtTrigger_Disable 0x3FFF + +/* Start Conversion */ +#define ADC_Conversion_Start 0x0001 +#define ADC_Conversion_Stop 0xFFFE + +/* ADC Conversion Modes */ +#define ADC_ConversionMode_Scan 0x8000 +#define ADC_ConversionMode_OneShot 0x7FFF + +/* Auto Clock Off */ +#define ADC_AutoClockOff_Enable 0x4000 +#define ADC_AutoClockOff_Disable 0xBFFF + +/* Calibration */ +#define ADC_Calibration_ON 0x0002 +#define ADC_CalibAverage_Disable 0x0020 +#define ADC_CalibAverage_Enable 0xFFDF + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +void ADC_DeInit(void); +void ADC_Init(ADC_InitTypeDef *ADC_InitStruct); +void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct); +void ADC_Cmd(FunctionalState NewState); +void ADC_StartCalibration(u16 ADC_CalibAverage); +FlagStatus ADC_GetCalibrationStatus(void); +void ADC_ConversionCmd(u16 ADC_Conversion); +FlagStatus ADC_GetSTARTBitStatus(void); +void ADC_AutoClockOffConfig(FunctionalState NewState); +u16 ADC_GetConversionValue(u8 ADC_CHANNEL); +void ADC_ITConfig(u16 ADC_IT, FunctionalState NewState); +void ADC_AnalogWatchdogConfig(u16 ADC_AnalogWatchdog, u8 ADC_CHANNEL, + u16 LowThreshold, u16 HighThreshold); +void ADC_AnalogWatchdogCmd(u16 ADC_AnalogWatchdog, FunctionalState NewState); +u16 ADC_GetAnalogWatchdogResult(u16 ADC_AnalogWatchdog); +void ADC_StartInjectedConversion(void); +void ADC_InjectedConversionConfig(u16 ADC_Injec_ExtTrigger, u8 FirstChannel, u8 ChannelNumber); +void ADC_DMAConfig(u16 ADC_DMA_CHANNEL, FunctionalState NewState); +void ADC_DMACmd(u16 ADC_DMA); +u16 ADC_GetDMAFirstEnabledChannel(void); +FlagStatus ADC_GetFlagStatus(u16 ADC_FLAG); +void ADC_ClearFlag(u16 ADC_FLAG); +ITStatus ADC_GetITStatus(u16 ADC_IT); +void ADC_ClearITPendingBit(u16 ADC_IT); + +#endif /*__75x_ADC_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_can.h b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_can.h new file mode 100644 index 000000000..9b630ee0c --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_can.h @@ -0,0 +1,165 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_can.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* CAN bus software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_CAN_H +#define __75x_CAN_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +/* Exported types ------------------------------------------------------------*/ + +/* CAN Init structure define */ +typedef struct +{ + u8 CAN_ConfigParameters; + u32 CAN_Bitrate; +}CAN_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* Standard bitrates available*/ +enum +{ + CAN_BITRATE_100K, + CAN_BITRATE_125K, + CAN_BITRATE_250K, + CAN_BITRATE_500K, + CAN_BITRATE_1M +}; + +/* Control register*/ +#define CAN_CR_TEST 0x0080 +#define CAN_CR_CCE 0x0040 +#define CAN_CR_DAR 0x0020 +#define CAN_CR_EIE 0x0008 +#define CAN_CR_SIE 0x0004 +#define CAN_CR_IE 0x0002 +#define CAN_CR_INIT 0x0001 + +/* Status register */ +#define CAN_SR_BOFF 0x0080 +#define CAN_SR_EWARN 0x0040 +#define CAN_SR_EPASS 0x0020 +#define CAN_SR_RXOK 0x0010 +#define CAN_SR_TXOK 0x0008 +#define CAN_SR_LEC 0x0007 + +/* Test register*/ +#define CAN_TESTR_RX 0x0080 +#define CAN_TESTR_TX1 0x0040 +#define CAN_TESTR_TX0 0x0020 +#define CAN_TESTR_LBACK 0x0010 +#define CAN_TESTR_SILENT 0x0008 +#define CAN_TESTR_BASIC 0x0004 + +/* IFn / Command Request register*/ +#define CAN_CRR_BUSY 0x8000 + +/* IFn / Command Mask register*/ +#define CAN_CMR_WRRD 0x0080 +#define CAN_CMR_MASK 0x0040 +#define CAN_CMR_ARB 0x0020 +#define CAN_CMR_CONTROL 0x0010 +#define CAN_CMR_CLRINTPND 0x0008 +#define CAN_CMR_TXRQSTNEWDAT 0x0004 +#define CAN_CMR_DATAA 0x0002 +#define CAN_CMR_DATAB 0x0001 + +/* IFn / Mask 2 register*/ +#define CAN_M2R_MXTD 0x8000 +#define CAN_M2R_MDIR 0x4000 + +/* IFn / Arbitration 2 register*/ +#define CAN_A2R_MSGVAL 0x8000 +#define CAN_A2R_XTD 0x4000 +#define CAN_A2R_DIR 0x2000 + +/* IFn / Message Control register*/ +#define CAN_MCR_NEWDAT 0x8000 +#define CAN_MCR_MSGLST 0x4000 +#define CAN_MCR_INTPND 0x2000 +#define CAN_MCR_UMASK 0x1000 +#define CAN_MCR_TXIE 0x0800 +#define CAN_MCR_RXIE 0x0400 +#define CAN_MCR_RMTEN 0x0200 +#define CAN_MCR_TXRQST 0x0100 +#define CAN_MCR_EOB 0x0080 + + +/* Wake-up modes*/ +enum +{ + CAN_WAKEUP_ON_EXT, + CAN_WAKEUP_ON_CAN +}; + + +/* CAN message structure*/ +typedef struct +{ + u32 IdType; + u32 Id; + u8 Dlc; + u8 Data[8]; +} canmsg; + +/* Message ID types*/ +enum +{ + CAN_STD_ID, + CAN_EXT_ID +}; + +/* Message ID limits*/ + +#define CAN_LAST_STD_ID ((1<<11) - 1) +#define CAN_LAST_EXT_ID ((1L<<29) - 1) + +/* Exported functions ------------------------------------------------------- */ + +void CAN_Init (CAN_InitTypeDef *CAN_InitStruct); +void CAN_DeInit (void); +void CAN_StructInit(CAN_InitTypeDef *CAN_InitStruct); +void CAN_SetBitrate(u32 bitrate); +void CAN_SetTiming(u32 tseg1, u32 tseg2, u32 sjw, u32 brp); +ErrorStatus CAN_SetUnusedMsgObj(u32 msgobj); +ErrorStatus CAN_SetTxMsgObj(u32 msgobj, u32 idType); +ErrorStatus CAN_SetRxMsgObj(u32 msgobj, u32 idType, u32 idLow, u32 idHigh, bool singleOrFifoLast); +void CAN_InvalidateAllMsgObj(void); +ErrorStatus CAN_ReleaseMessage(u32 msgobj); +ErrorStatus CAN_SendMessage(u32 msgobj, canmsg* pCanMsg); +ErrorStatus CAN_ReceiveMessage(u32 msgobj, bool release, canmsg* pCanMsg); +ErrorStatus CAN_WaitEndOfTx(void); +ErrorStatus CAN_BasicSendMessage(canmsg* pCanMsg); +ErrorStatus CAN_BasicReceiveMessage(canmsg* pCanMsg); +void CAN_EnterTestMode(u8 TestMask); +void CAN_EnterInitMode(u8 InitMask); +void CAN_LeaveInitMode(void); +void CAN_LeaveTestMode(void); +void CAN_ReleaseTxMessage(u32 msgobj); +void CAN_ReleaseRxMessage(u32 msgobj); +u32 CAN_IsMessageWaiting(u32 msgobj); +u32 CAN_IsTransmitRequested(u32 msgobj); +u32 CAN_IsInterruptPending(u32 msgobj); +u32 CAN_IsObjectValid(u32 msgobj); + +#endif /* __75x_CAN_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_cfg.h b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_cfg.h new file mode 100644 index 000000000..e1042a246 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_cfg.h @@ -0,0 +1,48 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_cfg.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* CFG software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_CFG_H +#define __75x_CFG_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +#define CFG_BootSpace_FLASH 0x00000000 +#define CFG_BootSpace_SRAM 0x00000002 +#define CFG_BootSpace_ExtSMI 0x00000003 + +#define CFG_FLASHBurst_Disable 0xFFFFFEFF +#define CFG_FLASHBurst_Enable 0x00000100 + +#define CFG_USBFilter_Disable 0xFFFFFDFF +#define CFG_USBFilter_Enable 0x00000200 + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void CFG_BootSpaceConfig(u32 CFG_BootSpace); +void CFG_FLASHBurstConfig(u32 CFG_FLASHBurst); +void CFG_USBFilterConfig(u32 CFG_USBFilter); +FlagStatus CFG_GetFlagStatus(void); + +#endif /* __75x_CFG_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_conf.h b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_conf.h new file mode 100644 index 000000000..ab3c5394f --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_conf.h @@ -0,0 +1,106 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_conf.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : Library configuration file. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_CONF_H +#define __75x_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Comment the line below to compile the library in release mode */ +//#define DEBUG + +/************************************* SMI ************************************/ +//#define _SMI + +/************************************* CFG ************************************/ +#define _CFG + +/************************************* MRCC ************************************/ +#define _MRCC + +/************************************* ADC ************************************/ +//#define _ADC + +/************************************* TB *************************************/ +#define _TB + +/************************************* TIM ************************************/ +#define _TIM +#define _TIM0 +#define _TIM1 +#define _TIM2 + +/************************************* PWM ************************************/ +#define _PWM + +/************************************* WDG ************************************/ +#define _WDG + +/************************************* SSP ************************************/ +//#define _SSP +//#define _SSP0 +//#define _SSP1 + +/************************************* CAN ************************************/ +//#define _CAN + +/************************************* I2C ************************************/ +//#define _I2C + +/************************************* UART ***********************************/ +#define _UART +#define _UART0 +#define _UART1 +#define _UART2 + +/************************************* GPIO ***********************************/ +#define _GPIO +#define _GPIO0 +#define _GPIO1 +#define _GPIO2 +#define _GPIOREMAP + +/************************************* DMA ************************************/ +//#define _DMA +//#define _DMA_Stream0 +//#define _DMA_Stream1 +//#define _DMA_Stream2 +//#define _DMA_Stream3 + +/************************************* RTC ************************************/ +//#define _RTC + +/************************************* EXTIT **********************************/ +#define _EXTIT + +/************************************* EIC ************************************/ +#define _EIC + +/* Comment the following line, depending on the external Quartz oscillator used + in your application */ +#define Main_Oscillator 4000000 /* 4 MHz Quartz oscillator used */ +//#define Main_Oscillator 8000000 /* 8 MHz Quartz oscillator used */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +#endif /* __75x_CONF_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_dma.h b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_dma.h new file mode 100644 index 000000000..f71b1cad4 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_dma.h @@ -0,0 +1,140 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_dma.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* DMA software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion ------------------------------------ */ +#ifndef __75x_DMA_H +#define __75x_DMA_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* DMA Init structure definition */ +typedef struct +{ + u32 DMA_SRCBaseAddr; + u32 DMA_DSTBaseAddr; + u16 DMA_BufferSize; + u16 DMA_SRC; + u16 DMA_DST; + u16 DMA_SRCSize; + u16 DMA_SRCBurst; + u16 DMA_DSTSize; + u16 DMA_Mode; + u16 DMA_M2M; + u16 DMA_DIR; +}DMA_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* DMA interrupt Mask */ +#define DMA_IT_SI0 0x0001 +#define DMA_IT_SI1 0x0002 +#define DMA_IT_SI2 0x0004 +#define DMA_IT_SI3 0x0008 +#define DMA_IT_SE0 0x0010 +#define DMA_IT_SE1 0x0020 +#define DMA_IT_SE2 0x0040 +#define DMA_IT_SE3 0x0080 +#define DMA_IT_ALL 0x00FF + +/* DMA Flags */ +#define DMA_FLAG_SI0 0x0001 +#define DMA_FLAG_SI1 0x0002 +#define DMA_FLAG_SI2 0x0004 +#define DMA_FLAG_SI3 0x0008 +#define DMA_FLAG_SE0 0x0010 +#define DMA_FLAG_SE1 0x0020 +#define DMA_FLAG_SE2 0x0040 +#define DMA_FLAG_SE3 0x0080 +#define DMA_FLAG_ACT0 0x0100 +#define DMA_FLAG_ACT1 0x0200 +#define DMA_FLAG_ACT2 0x0400 +#define DMA_FLAG_ACT3 0x0800 + +/* DMA Increment Current Source Register */ +#define DMA_SRC_INCR 0x0002 +#define DMA_SRC_NOT_INCR 0xFFFD + +/* DMA Increment Current Destination Register */ +#define DMA_DST_INCR 0x0004 +#define DMA_DST_NOT_INCR 0xFFFB + +/* Source to DMA data width */ +#define DMA_SRCSize_Byte 0x0000 +#define DMA_SRCSize_HalfWord 0x0008 +#define DMA_SRCSize_Word 0x0010 + +/* DMA source burst size */ +#define DMA_SRCBurst_1Data 0x0000 +#define DMA_SRCBurst_4Data 0x0020 +#define DMA_SRCBurst_8Data 0x0040 +#define DMA_SRCBurst_16Data 0x0060 + +/* DMA destination data width */ +#define DMA_DSTSize_Byte 0x0000 +#define DMA_DSTSize_HalfWord 0x0080 +#define DMA_DSTSize_Word 0x0100 + +/* DMA mode */ +#define DMA_Mode_Circular 0x0200 +#define DMA_Mode_Normal 0xFDFF + +/* Memory to Memory Transfer */ +#define DMA_M2M_Enable 0x0800 +#define DMA_M2M_Disable 0xF7FF + +/* Direction Transfer */ +#define DMA_DIR_PeriphDST 0x2000 +#define DMA_DIR_PeriphSRC 0xDFFF + +/* DMA streamx Registers */ +#define DMA_SOURCEL 0x00000000 /* source base address low register */ +#define DMA_SOURCEH 0x00000004 /* source base address high register */ +#define DMA_DESTL 0x00000008 /* destination base address low register */ +#define DMA_DESTH 0x0000000C /* destination base address high register */ +#define DMA_MAX 0x00000010 /* Maximum count register */ +#define DMA_CTRL 0x00000014 /* Control register */ +#define DMA_SOCURRH 0x00000018 /* Current Source address high register */ +#define DMA_SOCURRL 0x0000001C /* Current Source address low register */ +#define DMA_DECURRH 0x00000020 /* Current Destination address high register */ +#define DMA_DECURRL 0x00000024 /* Current Destination address low register */ +#define DMA_TCNT 0x00000028 /* Terminal Counter Register */ +#define DMA_LUBUFF 0x0000002C /* Last Used Buffer location */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void DMA_DeInit(DMA_Stream_TypeDef* DMA_Streamx); +void DMA_Init(DMA_Stream_TypeDef* DMA_Streamx, DMA_InitTypeDef* DMA_InitStruct); +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); +void DMA_Cmd(DMA_Stream_TypeDef* DMA_Streamx, FunctionalState NewState); +void DMA_ITConfig(u16 DMA_IT, FunctionalState NewState); +u32 DMA_GetCurrDSTAddr(DMA_Stream_TypeDef* DMA_Streamx); +u32 DMA_GetCurrSRCAddr(DMA_Stream_TypeDef* DMA_Streamx); +u16 DMA_GetTerminalCounter(DMA_Stream_TypeDef* DMA_Streamx); +void DMA_LastBufferSweepConfig(DMA_Stream_TypeDef* DMA_Streamx, FunctionalState NewState); +void DMA_LastBufferAddrConfig(DMA_Stream_TypeDef* DMA_Streamx, u16 DMA_LastBufferAddr); +FlagStatus DMA_GetFlagStatus(u16 DMA_FLAG); +void DMA_ClearFlag(u16 DMA_FLAG); +ITStatus DMA_GetITStatus(u16 DMA_IT); +void DMA_ClearITPendingBit(u16 DMA_IT); + +#endif /* __75x_DMA_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_eic.h b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_eic.h new file mode 100644 index 000000000..c7e6a07cf --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_eic.h @@ -0,0 +1,97 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_eic.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* EIC software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_EIC_H +#define __75x_EIC_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +/* Exported types ------------------------------------------------------------*/ +typedef struct +{ + u8 EIC_IRQChannel; + u8 EIC_IRQChannelPriority; + FunctionalState EIC_IRQChannelCmd; +}EIC_IRQInitTypeDef; + +typedef struct +{ + u8 EIC_FIQChannel; + FunctionalState EIC_FIQChannelCmd; +}EIC_FIQInitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* IRQ channels */ +#define WAKUP_IRQChannel 0 +#define TIM2_OC2_IRQChannel 1 +#define TIM2_OC1_IRQChannel 2 +#define TIM2_IC12_IRQChannel 3 +#define TIM2_UP_IRQChannel 4 +#define TIM1_OC2_IRQChannel 5 +#define TIM1_OC1_IRQChannel 6 +#define TIM1_IC12_IRQChannel 7 +#define TIM1_UP_IRQChannel 8 +#define TIM0_OC2_IRQChannel 9 +#define TIM0_OC1_IRQChannel 10 +#define TIM0_IC12_IRQChannel 11 +#define TIM0_UP_IRQChannel 12 +#define PWM_OC123_IRQChannel 13 +#define PWM_EM_IRQChannel 14 +#define PWM_UP_IRQChannel 15 +#define I2C_IRQChannel 16 +#define SSP1_IRQChannel 17 +#define SSP0_IRQChannel 18 +#define UART2_IRQChannel 19 +#define UART1_IRQChannel 20 +#define UART0_IRQChannel 21 +#define CAN_IRQChannel 22 +#define USB_LP_IRQChannel 23 +#define USB_HP_IRQChannel 24 +#define ADC_IRQChannel 25 +#define DMA_IRQChannel 26 +#define EXTIT_IRQChannel 27 +#define MRCC_IRQChannel 28 +#define FLASHSMI_IRQChannel 29 +#define RTC_IRQChannel 30 +#define TB_IRQChannel 31 + +/* FIQ channels */ +#define EXTIT_Line0_FIQChannel 0x00000001 +#define WATCHDOG_FIQChannel 0x00000002 + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void EIC_DeInit(void); +void EIC_IRQInit(EIC_IRQInitTypeDef* EIC_IRQInitStruct); +void EIC_FIQInit(EIC_FIQInitTypeDef* EIC_FIQInitStruct); +void EIC_IRQStructInit(EIC_IRQInitTypeDef* EIC_IRQInitStruct); +void EIC_FIQStructInit(EIC_FIQInitTypeDef* EIC_FIQInitStruct); +void EIC_IRQCmd(FunctionalState NewState); +void EIC_FIQCmd(FunctionalState NewState); +u8 EIC_GetCurrentIRQChannel(void); +u8 EIC_GetCurrentIRQChannelPriority(void); +void EIC_CurrentIRQPriorityConfig(u8 NewPriority); +u8 EIC_GetCurrentFIQChannel(void); +void EIC_ClearFIQPendingBit(u8 EIC_FIQChannel); + +#endif /* __75x_EIC_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_extit.h b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_extit.h new file mode 100644 index 000000000..5dbbc3a09 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_extit.h @@ -0,0 +1,77 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_extit.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* EXTIT software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_EXTIT_H +#define __75x_EXTIT_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* EXTIT Trigger enumeration */ +typedef enum +{ + EXTIT_ITTrigger_Falling = 1, + EXTIT_ITTrigger_Rising +}EXTITTrigger_TypeDef; + +/* EXTIT Init Structure definition */ +typedef struct +{ + u32 EXTIT_ITLine; + EXTITTrigger_TypeDef EXTIT_ITTrigger; + FunctionalState EXTIT_ITLineCmd; +}EXTIT_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* EXTIT Lines */ +#define EXTIT_ITLineNone 0x0000 /* No interrupt selected */ +#define EXTIT_ITLine0 0x0001 /* External interrupt line 0 */ +#define EXTIT_ITLine1 0x0002 /* External interrupt line 1 */ +#define EXTIT_ITLine2 0x0004 /* External interrupt line 2 */ +#define EXTIT_ITLine3 0x0008 /* External interrupt line 3 */ +#define EXTIT_ITLine4 0x0010 /* External interrupt line 4 */ +#define EXTIT_ITLine5 0x0020 /* External interrupt line 5 */ +#define EXTIT_ITLine6 0x0040 /* External interrupt line 6 */ +#define EXTIT_ITLine7 0x0080 /* External interrupt line 7 */ +#define EXTIT_ITLine8 0x0100 /* External interrupt line 8 */ +#define EXTIT_ITLine9 0x0200 /* External interrupt line 9 */ +#define EXTIT_ITLine10 0x0400 /* External interrupt line 10 */ +#define EXTIT_ITLine11 0x0800 /* External interrupt line 11 */ +#define EXTIT_ITLine12 0x1000 /* External interrupt line 12 */ +#define EXTIT_ITLine13 0x2000 /* External interrupt line 13 */ +#define EXTIT_ITLine14 0x4000 /* External interrupt line 14 */ +#define EXTIT_ITLine15 0x8000 /* External interrupt line 15 */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void EXTIT_DeInit(void); +void EXTIT_Init(EXTIT_InitTypeDef* EXTIT_InitStruct); +void EXTIT_StructInit(EXTIT_InitTypeDef* EXTIT_InitStruct); +void EXTIT_GenerateSWInterrupt(u16 EXTIT_ITLine); +FlagStatus EXTIT_GetFlagStatus(u16 EXTIT_ITLine); +void EXTIT_ClearFlag(u16 EXTIT_ITLine); +ITStatus EXTIT_GetITStatus(u16 EXTIT_ITLine); +void EXTIT_ClearITPendingBit(u16 EXTIT_ITLine); + +#endif /* __75x_EXTIT_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_gpio.h b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_gpio.h new file mode 100644 index 000000000..53aad69ca --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_gpio.h @@ -0,0 +1,120 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_gpio.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* GPIO software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_GPIO_H +#define __75x_GPIO_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* Configuration Mode enumeration */ +typedef enum +{ GPIO_Mode_AIN = 1, + GPIO_Mode_IN_FLOATING, + GPIO_Mode_IPD, + GPIO_Mode_IPU, + GPIO_Mode_Out_OD, + GPIO_Mode_Out_PP, + GPIO_Mode_AF_OD, + GPIO_Mode_AF_PP +}GPIOMode_TypeDef; + +/* GPIO Init structure definition */ +typedef struct +{ + u32 GPIO_Pin; + GPIOMode_TypeDef GPIO_Mode; +}GPIO_InitTypeDef; + +/* Bit_SET and Bit_RESET enumeration */ +typedef enum +{ Bit_RESET = 0, + Bit_SET +}BitAction; + + +/* Exported constants --------------------------------------------------------*/ +/* GPIO pins define */ +#define GPIO_Pin_None 0x00000000 /* No pin selected */ +#define GPIO_Pin_0 0x00000001 /* Pin 0 selected */ +#define GPIO_Pin_1 0x00000002 /* Pin 1 selected */ +#define GPIO_Pin_2 0x00000004 /* Pin 2 selected */ +#define GPIO_Pin_3 0x00000008 /* Pin 3 selected */ +#define GPIO_Pin_4 0x00000010 /* Pin 4 selected */ +#define GPIO_Pin_5 0x00000020 /* Pin 5 selected */ +#define GPIO_Pin_6 0x00000040 /* Pin 6 selected */ +#define GPIO_Pin_7 0x00000080 /* Pin 7 selected */ +#define GPIO_Pin_8 0x00000100 /* Pin 8 selected */ +#define GPIO_Pin_9 0x00000200 /* Pin 9 selected */ +#define GPIO_Pin_10 0x00000400 /* Pin 10 selected */ +#define GPIO_Pin_11 0x00000800 /* Pin 11 selected */ +#define GPIO_Pin_12 0x00001000 /* Pin 12 selected */ +#define GPIO_Pin_13 0x00002000 /* Pin 13 selected */ +#define GPIO_Pin_14 0x00004000 /* Pin 14 selected */ +#define GPIO_Pin_15 0x00008000 /* Pin 15 selected */ +#define GPIO_Pin_16 0x00010000 /* Pin 16 selected */ +#define GPIO_Pin_17 0x00020000 /* Pin 17 selected */ +#define GPIO_Pin_18 0x00040000 /* Pin 18 selected */ +#define GPIO_Pin_19 0x00080000 /* Pin 19 selected */ +#define GPIO_Pin_20 0x00100000 /* Pin 20 selected */ +#define GPIO_Pin_21 0x00200000 /* Pin 21 selected */ +#define GPIO_Pin_22 0x00400000 /* Pin 22 selected */ +#define GPIO_Pin_23 0x00800000 /* Pin 23 selected */ +#define GPIO_Pin_24 0x01000000 /* Pin 24 selected */ +#define GPIO_Pin_25 0x02000000 /* Pin 25 selected */ +#define GPIO_Pin_26 0x04000000 /* Pin 26 selected */ +#define GPIO_Pin_27 0x08000000 /* Pin 27 selected */ +#define GPIO_Pin_28 0x10000000 /* Pin 28 selected */ +#define GPIO_Pin_29 0x20000000 /* Pin 29 selected */ +#define GPIO_Pin_30 0x40000000 /* Pin 30 selected */ +#define GPIO_Pin_31 0x80000000 /* Pin 31 selected */ +#define GPIO_Pin_All 0xFFFFFFFF /* All pins selected */ + +/* GPIO Remap define */ +#define GPIO_Remap_SMI_CS3_EN 0x23 /* SMI CS3 Enable */ +#define GPIO_Remap_SMI_CS2_EN 0x22 /* SMI CS2 Enable */ +#define GPIO_Remap_SMI_CS1_EN 0x21 /* SMI CS1 Enable */ +#define GPIO_Remap_SMI_EN 0x20 /* SMI Enable */ +#define GPIO_Remap_DBGOFF 0x45 /* JTAG Disable */ +#define GPIO_Remap_UART1 0x44 /* UART1 Alternate Function mapping */ +#define GPIO_Remap_UART2 0x43 /* UART2 Alternate Function mapping */ +#define GPIO_Remap_SSP1 0x42 /* SSP1 Alternate Function mapping */ +#define GPIO_Remap_TIM2 0x41 /* TIM2 Alternate Function mapping */ +#define GPIO_Remap_TIM0 0x40 /* TIM0 Alternate Function mapping */ + + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void GPIO_DeInit(GPIO_TypeDef* GPIOx); +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); +u32 GPIO_Read(GPIO_TypeDef* GPIOx); +u8 GPIO_ReadBit(GPIO_TypeDef* GPIOx, u32 GPIO_Pin); +void GPIO_Write(GPIO_TypeDef* GPIOx, u32 PortVal); +void GPIO_WriteBit(GPIO_TypeDef* GPIOx,u32 GPIO_Pin, BitAction BitVal); +void GPIO_PinMaskConfig(GPIO_TypeDef* GPIOx, u32 GPIO_Pin, FunctionalState NewState); +u32 GPIO_GetPortMask(GPIO_TypeDef* GPIOx); +void GPIO_PinRemapConfig(u16 GPIO_Remap, FunctionalState NewState); + +#endif /* __75x_GPIO_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_i2c.h b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_i2c.h new file mode 100644 index 000000000..0e3a8c511 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_i2c.h @@ -0,0 +1,115 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_i2c.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* I2C software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion ------------------------------------ */ +#ifndef __75x_I2C_H +#define __75x_I2C_H + +/* Includes ----------------------------------------------------------------- */ +#include "75x_map.h" + +/* Exported types ----------------------------------------------------------- */ +/* I2C Init structure definition */ +typedef struct +{ + u32 I2C_CLKSpeed; + u16 I2C_OwnAddress; + u8 I2C_GeneralCall; + u8 I2C_Ack; +}I2C_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* General Call */ +#define I2C_GeneralCall_Enable 0x10 +#define I2C_GeneralCall_Disable 0xEF + +/* Acknowledgement */ +#define I2C_Ack_Enable 0x04 +#define I2C_Ack_Disable 0xFB + +/* I2C Flags */ +#define I2C_FLAG_SB 0x0001 +#define I2C_FLAG_M_SL 0x0002 +#define I2C_FLAG_ADSL 0x0004 +#define I2C_FLAG_BTF 0x0008 +#define I2C_FLAG_BUSY 0x0010 +#define I2C_FLAG_TRA 0x0020 +#define I2C_FLAG_ADD10 0x0040 +#define I2C_FLAG_EVF 0x0080 +#define I2C_FLAG_GCAL 0x0100 +#define I2C_FLAG_BERR 0x0200 +#define I2C_FLAG_ARLO 0x0400 +#define I2C_FLAG_STOPF 0x0800 +#define I2C_FLAG_AF 0x1000 +#define I2C_FLAG_ENDAD 0x2000 +#define I2C_FLAG_ACK 0x4000 + +/* I2C Events */ +#define I2C_EVENT_SLAVE_ADDRESS_MATCHED ( I2C_FLAG_EVF | I2C_FLAG_BUSY |I2C_FLAG_ADSL) +#define I2C_EVENT_SLAVE_BYTE_RECEIVED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_BTF ) +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_BTF | I2C_FLAG_TRA ) +#define I2C_EVENT_MASTER_MODE_SELECT ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL | I2C_FLAG_SB ) +#define I2C_EVENT_MASTER_MODE_SELECTED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL | I2C_FLAG_ENDAD ) +#define I2C_EVENT_MASTER_BYTE_RECEIVED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL | I2C_FLAG_BTF ) +#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL | I2C_FLAG_BTF | I2C_FLAG_TRA ) +#define I2C_EVENT_MASTER_MODE_ADDRESS10 ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL |I2C_FLAG_ADD10 ) +#define I2C_EVENT_SLAVE_STOP_DETECTED I2C_FLAG_STOPF +#define I2C_EVENT_SLAVE_ACK_FAILURE ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_BTF | I2C_FLAG_TRA | I2C_FLAG_AF) + +#define I2C_BUS_ERROR_DETECTED I2C_FLAG_BERR +#define I2C_ARBITRATION_LOST I2C_FLAG_ARLO +#define I2C_SLAVE_GENERAL_CALL (I2C_FLAG_BUSY | I2C_FLAG_GCAL) + +/* Master/Receiver Mode */ +#define I2C_MODE_TRANSMITTER 0x00 +#define I2C_MODE_RECEIVER 0x01 + +/* I2C Registers offset */ +#define I2C_CR 0x00 +#define I2C_SR1 0x04 +#define I2C_SR2 0x08 +#define I2C_CCR 0x0C +#define I2C_OAR1 0x10 +#define I2C_OAR2 0x14 +#define I2C_DR 0x18 +#define I2C_ECCR 0x1C + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void I2C_DeInit(void); +void I2C_Init(I2C_InitTypeDef* I2C_InitStruct); +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); +void I2C_Cmd(FunctionalState NewState); +void I2C_GenerateSTART(FunctionalState NewState); +void I2C_GenerateSTOP(FunctionalState NewState); +void I2C_AcknowledgeConfig(FunctionalState NewState); +void I2C_ITConfig(FunctionalState NewState); +u16 I2C_GetLastEvent(void); +ErrorStatus I2C_CheckEvent(u16 I2C_EVENT); +void I2C_SendData(u8 Data); +u8 I2C_ReceiveData(void); +void I2C_Send7bitAddress(u8 Address, u8 Direction); +u8 I2C_ReadRegister(u8 I2C_Register); +FlagStatus I2C_GetFlagStatus(u16 I2C_FLAG); +void I2C_ClearFlag(u16 I2C_FLAG, ...); + +#endif /* __75x_I2C_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_lib.h b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_lib.h new file mode 100644 index 000000000..8048ffcc3 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_lib.h @@ -0,0 +1,103 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_lib.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file includes the peripherals header files in the +* user application. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_LIB_H +#define __75x_LIB_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +#ifdef _SMI + #include "75x_smi.h" +#endif /*_SMI */ + +#ifdef _CFG + #include "75x_cfg.h" +#endif /*_CFG*/ + +#ifdef _MRCC + #include "75x_mrcc.h" +#endif /*_MRCC */ + +#ifdef _ADC + #include "75x_adc.h" +#endif /*_ADC */ + +#ifdef _TB + #include "75x_tb.h" +#endif /*_TB */ + +#ifdef _TIM + #include "75x_tim.h" +#endif /*_TIM */ + +#ifdef _PWM + #include "75x_pwm.h" +#endif /*_PWM */ + +#ifdef _WDG + #include "75x_wdg.h" +#endif /*_WDG */ + +#ifdef _SSP + #include "75x_ssp.h" +#endif /*_SSP */ + +#ifdef _CAN + #include "75x_can.h" +#endif /*_CAN */ + +#ifdef _I2C + #include "75x_i2c.h" +#endif /*_I2C */ + +#ifdef _UART + #include "75x_uart.h" +#endif /*_UART */ + +#ifdef _GPIO + #include "75x_gpio.h" +#endif /*_GPIO */ + +#ifdef _DMA + #include "75x_dma.h" +#endif /*_DMA */ + +#ifdef _RTC + #include "75x_rtc.h" +#endif /*_RTC */ + +#ifdef _EXTIT + #include "75x_extit.h" +#endif /*_EXTIT */ + +#ifdef _EIC + #include "75x_eic.h" +#endif /*_EIC */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void debug(void); + +#endif /* __75x_LIB_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_map.h b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_map.h new file mode 100644 index 000000000..d000f1b45 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_map.h @@ -0,0 +1,697 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_map.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the peripheral register's definitions +* and memory mapping. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_MAP_H +#define __75x_MAP_H + +#ifndef EXT + #define EXT extern +#endif /* EXT */ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_conf.h" +#include "75x_type.h" + +/* Exported types ------------------------------------------------------------*/ +/******************************************************************************/ +/* IP registers structures */ +/******************************************************************************/ + +/*------------------------ Analog to Digital Converter -----------------------*/ +typedef struct +{ + vu16 CLR0; + u16 EMPTY1; + vu16 CLR1; + u16 EMPTY2; + vu16 CLR2; + u16 EMPTY3; + vu16 CLR3; + u16 EMPTY4; + vu16 CLR4; + u16 EMPTY5; + vu16 TRA0; + u16 EMPTY6; + vu16 TRA1; + u16 EMPTY7; + vu16 TRA2; + u16 EMPTY8; + vu16 TRA3; + u16 EMPTY9; + vu16 TRB0; + u16 EMPTY10; + vu16 TRB1; + u16 EMPTY11; + vu16 TRB2; + u16 EMPTY12; + vu16 TRB3; + u16 EMPTY13; + vu16 DMAR; + u16 EMPTY14[7]; + vu16 DMAE; + u16 EMPTY15 ; + vu16 PBR; + u16 EMPTY16; + vu16 IMR; + u16 EMPTY17; + vu16 D0; + u16 EMPTY18; + vu16 D1; + u16 EMPTY19; + vu16 D2; + u16 EMPTY20; + vu16 D3; + u16 EMPTY21; + vu16 D4; + u16 EMPTY22; + vu16 D5; + u16 EMPTY23; + vu16 D6; + u16 EMPTY24; + vu16 D7; + u16 EMPTY25; + vu16 D8; + u16 EMPTY26; + vu16 D9; + u16 EMPTY27; + vu16 D10; + u16 EMPTY28; + vu16 D11; + u16 EMPTY29; + vu16 D12; + u16 EMPTY30; + vu16 D13; + u16 EMPTY31; + vu16 D14; + u16 EMPTY32; + vu16 D15; + u16 EMPTY33; +} ADC_TypeDef; + +/*------------------------ Controller Area Network ---------------------------*/ +typedef struct +{ + vu16 CRR; + u16 EMPTY1; + vu16 CMR; + u16 EMPTY2; + vu16 M1R; + u16 EMPTY3; + vu16 M2R; + u16 EMPTY4; + vu16 A1R; + u16 EMPTY5; + vu16 A2R; + u16 EMPTY6; + vu16 MCR; + u16 EMPTY7; + vu16 DA1R; + u16 EMPTY8; + vu16 DA2R; + u16 EMPTY9; + vu16 DB1R; + u16 EMPTY10; + vu16 DB2R; + u16 EMPTY11[27]; +} CAN_MsgObj_TypeDef; + +typedef struct +{ + vu16 CR; + u16 EMPTY1; + vu16 SR; + u16 EMPTY2; + vu16 ERR; + u16 EMPTY3; + vu16 BTR; + u16 EMPTY4; + vu16 IDR; + u16 EMPTY5; + vu16 TESTR; + u16 EMPTY6; + vu16 BRPR; + u16 EMPTY7[3]; + CAN_MsgObj_TypeDef sMsgObj[2]; + u16 EMPTY8[16]; + vu16 TXR1R; + u16 EMPTY9; + vu16 TXR2R; + u16 EMPTY10[13]; + vu16 ND1R; + u16 EMPTY11; + vu16 ND2R; + u16 EMPTY12[13]; + vu16 IP1R; + u16 EMPTY13; + vu16 IP2R; + u16 EMPTY14[13]; + vu16 MV1R; + u16 EMPTY15; + vu16 MV2R; + u16 EMPTY16; +} CAN_TypeDef; + +/*--------------------------- Configuration Register -------------------------*/ +typedef struct +{ + vu32 GLCONF; +} CFG_TypeDef; + +/*-------------------------------- DMA Controller ----------------------------*/ +typedef struct +{ + vu16 SOURCEL; + u16 EMPTY1; + vu16 SOURCEH; + u16 EMPTY2; + vu16 DESTL; + u16 EMPTY3; + vu16 DESTH; + u16 EMPTY4; + vu16 MAX; + u16 EMPTY5; + vu16 CTRL; + u16 EMPTY6; + vuc16 SOCURRH; + u16 EMPTY7; + vuc16 SOCURRL; + u16 EMPTY8; + vuc16 DECURRH; + u16 EMPTY9; + vuc16 DECURRL; + u16 EMPTY10; + vuc16 TCNT; + u16 EMPTY11; + vu16 LUBUFF; + u16 EMPTY12; +} DMA_Stream_TypeDef; + +typedef struct +{ + vu16 MASK; + u16 EMPTY4; + vu16 CLR; + u16 EMPTY5; + vuc16 STATUS; + u16 EMPTY6; + vu16 LAST; + u16 EMPTY7; +} DMA_TypeDef; + +/*----------------------- Enhanced Interrupt Controller ----------------------*/ +typedef struct +{ + vu32 ICR; + vuc32 CICR; + vu32 CIPR; + u32 EMPTY1; + vu32 FIER; + vu32 FIPR; + vu32 IVR; + vu32 FIR; + vu32 IER; + u32 EMPTY2[7]; + vu32 IPR; + u32 EMPTY3[7]; + vu32 SIRn[32]; +} EIC_TypeDef; + +/*------------------------- External Interrupt Controller --------------------*/ +typedef struct +{ + vu32 MR; + vu32 TSR; + vu32 SWIR; + vu32 PR; +} EXTIT_TypeDef; + +/*-------------------------- General Purpose IO ports ------------------------*/ +typedef struct +{ + vu32 PC0; + vu32 PC1; + vu32 PC2; + vu32 PD; + vu32 PM; +} GPIO_TypeDef; + +typedef struct +{ + vu32 REMAP0R; + vu32 REMAP1R; +} GPIOREMAP_TypeDef; + +/*--------------------------------- I2C interface ----------------------------*/ +typedef struct +{ + vu8 CR; + u8 EMPTY1[3]; + vu8 SR1; + u8 EMPTY2[3]; + vu8 SR2; + u8 EMPTY3[3]; + vu8 CCR; + u8 EMPTY4[3]; + vu8 OAR1; + u8 EMPTY5[3]; + vu8 OAR2; + u8 EMPTY6[3]; + vu8 DR; + u8 EMPTY7[3]; + vu8 ECCR; + u8 EMPTY8[3]; +} I2C_TypeDef; + +/*---------------------------- Power, Reset and Clocks -----------------------*/ +typedef struct +{ + vu32 CLKCTL; + vu32 RFSR; + vu32 PWRCTRL; + u32 EMPTY1; + vu32 PCLKEN; + vu32 PSWRES; + u32 EMPTY2[2]; + vu32 BKP0; + vu32 BKP1; +} MRCC_TypeDef; + +/*-------------------------------- Real Time Clock ---------------------------*/ +typedef struct +{ + vu16 CRH; + u16 EMPTY; + vu16 CRL; + u16 EMPTY1; + vu16 PRLH; + u16 EMPTY2; + vu16 PRLL; + u16 EMPTY3; + vu16 DIVH; + u16 EMPTY4; + vu16 DIVL; + u16 EMPTY5; + vu16 CNTH; + u16 EMPTY6; + vu16 CNTL; + u16 EMPTY7; + vu16 ALRH; + u16 EMPTY8; + vu16 ALRL; + u16 EMPTY9; +} RTC_TypeDef; + +/*---------------------------- Serial Memory Interface -----------------------*/ +typedef struct +{ + vu32 CR1; + vu32 CR2; + vu32 SR; + vu32 TR; + vuc32 RR; +} SMI_TypeDef; + +/*--------------------------------- Timer Base -------------------------------*/ +typedef struct +{ + vu16 CR; + u16 EMPTY1; + vu16 SCR; + u16 EMPTY2; + vu16 IMCR; + u16 EMPTY3[7]; + vu16 RSR; + u16 EMPTY4; + vu16 RER; + u16 EMPTY5; + vu16 ISR; + u16 EMPTY6; + vu16 CNT; + u16 EMPTY7; + vu16 PSC; + u16 EMPTY8[3]; + vu16 ARR; + u16 EMPTY9[13]; + vu16 ICR1; + u16 EMPTY10; +} TB_TypeDef; + +/*------------------------------------ TIM -----------------------------------*/ +typedef struct +{ + vu16 CR; + u16 EMPTY1; + vu16 SCR; + u16 EMPTY2; + vu16 IMCR; + u16 EMPTY3; + vu16 OMR1; + u16 EMPTY4[5]; + vu16 RSR; + u16 EMPTY5; + vu16 RER; + u16 EMPTY6; + vu16 ISR; + u16 EMPTY7; + vu16 CNT; + u16 EMPTY8; + vu16 PSC; + u16 EMPTY9[3]; + vu16 ARR; + u16 EMPTY10; + vu16 OCR1; + u16 EMPTY11; + vu16 OCR2; + u16 EMPTY12[9]; + vu16 ICR1; + u16 EMPTY13; + vu16 ICR2; + u16 EMPTY14[9]; + vu16 DMAB; + u16 EMPTY15; +} TIM_TypeDef; + +/*------------------------------------ PWM -----------------------------------*/ +typedef struct +{ + vu16 CR; + u16 EMPTY1; + vu16 SCR; + u16 EMPTY2[3]; + vu16 OMR1; + u16 EMPTY3; + vu16 OMR2; + u16 EMPTY4[3]; + vu16 RSR; + u16 EMPTY5; + vu16 RER; + u16 EMPTY6; + vu16 ISR; + u16 EMPTY7; + vu16 CNT; + u16 EMPTY8; + vu16 PSC; + u16 EMPTY9; + vu16 RCR; + u16 EMPTY10; + vu16 ARR; + u16 EMPTY11; + vu16 OCR1; + u16 EMPTY12; + vu16 OCR2; + u16 EMPTY13; + vu16 OCR3; + u16 EMPTY14[15]; + vu16 DTR; + u16 EMPTY15; + vu16 DMAB; + u16 EMPTY16; +} PWM_TypeDef; + +/*----------------------- Synchronous Serial Peripheral ----------------------*/ +typedef struct +{ + vu32 CR0; + vu32 CR1; + vu32 DR; + vu32 SR; + vu32 PR; + vu32 IMSCR; + vu32 RISR; + vu32 MISR; + vu32 ICR; + vu32 DMACR; +} SSP_TypeDef; + +/*---------------- Universal Asynchronous Receiver Transmitter ---------------*/ +typedef struct +{ + vu16 DR; + u16 EMPTY; + vu16 RSR; + u16 EMPTY1[9]; + vu16 FR; + u16 EMPTY2; + vu16 BKR; + u16 EMPTY3[3]; + vu16 IBRD; + u16 EMPTY4; + vu16 FBRD; + u16 EMPTY5; + vu16 LCR; + u16 EMPTY6; + vu16 CR; + u16 EMPTY7; + vu16 IFLS; + u16 EMPTY8; + vu16 IMSC; + u16 EMPTY9; + vu16 RIS; + u16 EMPTY10; + vu16 MIS; + u16 EMPTY11; + vu16 ICR; + u16 EMPTY12; + vu16 DMACR; + u16 EMPTY13; +} UART_TypeDef; + +/*---------------------------------- WATCHDOG --------------------------------*/ +typedef struct +{ + vu16 CR; + u16 EMPTY1; + vu16 PR; + u16 EMPTY2; + vu16 VR; + u16 EMPTY3; + vu16 CNT; + u16 EMPTY4; + vu16 SR; + u16 EMPTY5; + vu16 MR; + u16 EMPTY6; + vu16 KR; + u16 EMPTY7; +} WDG_TypeDef; + +/******************************************************************************* +* Peripherals' Base addresses +*******************************************************************************/ + +#define SRAM_BASE 0x40000000 + +#define CONFIG_BASE 0x60000000 + +#define SMIR_BASE 0x90000000 + +#define PERIPH_BASE 0xFFFF0000 + +#define CFG_BASE (CONFIG_BASE + 0x0010) +#define MRCC_BASE (CONFIG_BASE + 0x0020) +#define ADC_BASE (PERIPH_BASE + 0x8400) +#define TB_BASE (PERIPH_BASE + 0x8800) +#define TIM0_BASE (PERIPH_BASE + 0x8C00) +#define TIM1_BASE (PERIPH_BASE + 0x9000) +#define TIM2_BASE (PERIPH_BASE + 0x9400) +#define PWM_BASE (PERIPH_BASE + 0x9800) +#define WDG_BASE (PERIPH_BASE + 0xB000) +#define SSP0_BASE (PERIPH_BASE + 0xB800) +#define SSP1_BASE (PERIPH_BASE + 0xBC00) +#define CAN_BASE (PERIPH_BASE + 0xC400) +#define I2C_BASE (PERIPH_BASE + 0xCC00) +#define UART0_BASE (PERIPH_BASE + 0xD400) +#define UART1_BASE (PERIPH_BASE + 0xD800) +#define UART2_BASE (PERIPH_BASE + 0xDC00) +#define GPIO0_BASE (PERIPH_BASE + 0xE400) +#define GPIOREMAP_BASE (PERIPH_BASE + 0xE420) +#define GPIO1_BASE (PERIPH_BASE + 0xE440) +#define GPIO2_BASE (PERIPH_BASE + 0xE480) +#define DMA_BASE (PERIPH_BASE + 0xECF0) +#define DMA_Stream0_BASE (PERIPH_BASE + 0xEC00) +#define DMA_Stream1_BASE (PERIPH_BASE + 0xEC40) +#define DMA_Stream2_BASE (PERIPH_BASE + 0xEC80) +#define DMA_Stream3_BASE (PERIPH_BASE + 0xECC0) +#define RTC_BASE (PERIPH_BASE + 0xF000) +#define EXTIT_BASE (PERIPH_BASE + 0xF400) +#define EIC_BASE (PERIPH_BASE + 0xF800) + +/******************************************************************************* + IPs' declaration +*******************************************************************************/ + +/*------------------- Non Debug Mode -----------------------------------------*/ + +#ifndef DEBUG + #define SMI ((SMI_TypeDef *) SMIR_BASE) + #define CFG ((CFG_TypeDef *) CFG_BASE) + #define MRCC ((MRCC_TypeDef *) MRCC_BASE) + #define ADC ((ADC_TypeDef *) ADC_BASE) + #define TB ((TB_TypeDef *) TB_BASE) + #define TIM0 ((TIM_TypeDef *) TIM0_BASE) + #define TIM1 ((TIM_TypeDef *) TIM1_BASE) + #define TIM2 ((TIM_TypeDef *) TIM2_BASE) + #define PWM ((PWM_TypeDef *) PWM_BASE) + #define WDG ((WDG_TypeDef *) WDG_BASE) + #define SSP0 ((SSP_TypeDef *) SSP0_BASE) + #define SSP1 ((SSP_TypeDef *) SSP1_BASE) + #define CAN ((CAN_TypeDef *) CAN_BASE) + #define I2C ((I2C_TypeDef *) I2C_BASE) + #define UART0 ((UART_TypeDef *) UART0_BASE) + #define UART1 ((UART_TypeDef *) UART1_BASE) + #define UART2 ((UART_TypeDef *) UART2_BASE) + #define GPIO0 ((GPIO_TypeDef *) GPIO0_BASE) + #define GPIOREMAP ((GPIOREMAP_TypeDef *) GPIOREMAP_BASE) + #define GPIO1 ((GPIO_TypeDef *) GPIO1_BASE) + #define GPIO2 ((GPIO_TypeDef *) GPIO2_BASE) + #define DMA ((DMA_TypeDef *) DMA_BASE) + #define DMA_Stream0 ((DMA_Stream_TypeDef *) DMA_Stream0_BASE) + #define DMA_Stream1 ((DMA_Stream_TypeDef *) DMA_Stream1_BASE) + #define DMA_Stream2 ((DMA_Stream_TypeDef *) DMA_Stream2_BASE) + #define DMA_Stream3 ((DMA_Stream_TypeDef *) DMA_Stream3_BASE) + #define RTC ((RTC_TypeDef *) RTC_BASE) + #define EXTIT ((EXTIT_TypeDef *) EXTIT_BASE) + #define EIC ((EIC_TypeDef *) EIC_BASE) +#else /* DEBUG */ + #ifdef _SMI + EXT SMI_TypeDef *SMI; + #endif /*_SMI */ + + #ifdef _CFG + EXT CFG_TypeDef *CFG; + #endif /*_CFG */ + + #ifdef _MRCC + EXT MRCC_TypeDef *MRCC; + #endif /*_MRCC */ + + #ifdef _ADC + EXT ADC_TypeDef *ADC; + #endif /*_ADC */ + + #ifdef _TB + EXT TB_TypeDef *TB; + #endif /*_TB */ + + #ifdef _TIM0 + EXT TIM_TypeDef *TIM0; + #endif /*_TIM0 */ + + #ifdef _TIM1 + EXT TIM_TypeDef *TIM1; + #endif /*_TIM1 */ + + #ifdef _TIM2 + EXT TIM_TypeDef *TIM2; + #endif /*_TIM2 */ + + #ifdef _PWM + EXT PWM_TypeDef *PWM; + #endif /*_PWM */ + + #ifdef _WDG + EXT WDG_TypeDef *WDG; + #endif /*_WDG */ + + #ifdef _SSP0 + EXT SSP_TypeDef *SSP0; + #endif /*_SSP0 */ + + #ifdef _SSP1 + EXT SSP_TypeDef *SSP1; + #endif /*_SSP1 */ + + #ifdef _CAN + EXT CAN_TypeDef *CAN; + #endif /*_CAN */ + + #ifdef _I2C + EXT I2C_TypeDef *I2C; + #endif /*_I2C */ + + #ifdef _UART0 + EXT UART_TypeDef *UART0; + #endif /*_UART0 */ + + #ifdef _UART1 + EXT UART_TypeDef *UART1; + #endif /*_UART1 */ + + #ifdef _UART2 + EXT UART_TypeDef *UART2; + #endif /*_UART2 */ + + #ifdef _GPIO0 + EXT GPIO_TypeDef *GPIO0; + #endif /*_GPIO0 */ + + #ifdef _GPIOREMAP + EXT GPIOREMAP_TypeDef *GPIOREMAP; + #endif /*_GPIOREMAP */ + + #ifdef _GPIO1 + EXT GPIO_TypeDef *GPIO1; + #endif /*_GPIO1 */ + + #ifdef _GPIO2 + EXT GPIO_TypeDef *GPIO2; + #endif /*_GPIO2 */ + + #ifdef _DMA + EXT DMA_TypeDef *DMA; + #endif /*_DMA */ + + #ifdef _DMA_Stream0 + EXT DMA_Stream_TypeDef *DMA_Stream0; + #endif /*_DMA_Stream0 */ + + #ifdef _DMA_Stream1 + EXT DMA_Stream_TypeDef *DMA_Stream1; + #endif /*_DMA_Stream1 */ + + #ifdef _DMA_Stream2 + EXT DMA_Stream_TypeDef *DMA_Stream2; + #endif /*_DMA_Stream2 */ + + #ifdef _DMA_Stream3 + EXT DMA_Stream_TypeDef *DMA_Stream3; + #endif /*_DMA_Stream3 */ + + #ifdef _RTC + EXT RTC_TypeDef *RTC; + #endif /*_RTC */ + + #ifdef _EXTIT + EXT EXTIT_TypeDef *EXTIT; + #endif /*_EXTIT */ + + #ifdef _EIC + EXT EIC_TypeDef *EIC; + #endif /*_EIC */ + +#endif /* DEBUG */ + +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +#endif /* __75x_MAP_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_mrcc.h b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_mrcc.h new file mode 100644 index 000000000..91c178429 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_mrcc.h @@ -0,0 +1,241 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_mrcc.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* MRCC software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_MRCC_H +#define __75x_MRCC_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* MRCC Buck-up registers */ +typedef enum +{ + MRCC_BKP0, + MRCC_BKP1 +}MRCC_BKPReg; + +typedef enum +{ + FREEOSC, + OSC4MPLL, + OSC4M, + CKRTC, + Disabled, + OSC4M_Div128, + LPOSC, + OSC32K, + Internal, + External, + ON, + OFF +}CLKSourceTypeDef; + + +typedef struct +{ + CLKSourceTypeDef CKSYS_Source; /* FREEOSC, OSC4MPLL, OSC4M, CKRTC */ + CLKSourceTypeDef CKRTC_Source; /* Disabled, OSC4M_Div128, OSC32K, LPOSC */ + CLKSourceTypeDef CKUSB_Source; /* Disabled, Internal, External */ + CLKSourceTypeDef PLL_Status; /* ON, OFF */ + CLKSourceTypeDef OSC4M_Status; /* ON, OFF */ + CLKSourceTypeDef LPOSC_Status; /* ON, OFF */ + CLKSourceTypeDef OSC32K_Status; /* ON, OFF */ + u32 CKSYS_Frequency; + u32 HCLK_Frequency; + u32 CKTIM_Frequency; + u32 PCLK_Frequency; +}MRCC_ClocksTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* Oscillator divider by 2 */ +#define MRCC_XTDIV2_Disable 0xFFFF7FFF +#define MRCC_XTDIV2_Enable 0x00008000 + +/* System clock source */ +#define MRCC_CKSYS_FREEOSC 0x01 +#define MRCC_CKSYS_OSC4M 0x02 +#define MRCC_CKSYS_OSC4MPLL 0x03 +#define MRCC_CKSYS_RTC 0x04 + +/* PLL multiplication factors */ +#define MRCC_PLL_Disabled 0xFEFFFFFF +#define MRCC_PLL_NoChange 0x00000001 +#define MRCC_PLL_Mul_12 0x18000000 +#define MRCC_PLL_Mul_14 0x10000000 +#define MRCC_PLL_Mul_15 0x08000000 +#define MRCC_PLL_Mul_16 0x00000000 + +/* AHB clock source */ +#define MRCC_CKSYS_Div1 0x00000000 +#define MRCC_CKSYS_Div2 0x00000008 +#define MRCC_CKSYS_Div4 0x00000010 +#define MRCC_CKSYS_Div8 0x00000018 + +/* TIM clock source */ +#define MRCC_HCLK_Div1 0x00000000 +#define MRCC_HCLK_Div2 0x00000001 +#define MRCC_HCLK_Div4 0x00000002 +#define MRCC_HCLK_Div8 0x00000003 + +/* APB clock source */ +#define MRCC_CKTIM_Div1 0xFFFFFFFB +#define MRCC_CKTIM_Div2 0x00000004 + +/* RTC clock sources */ +#define MRCC_CKRTC_OSC4M_Div128 0x01000000 +#define MRCC_CKRTC_OSC32K 0x02000000 +#define MRCC_CKRTC_LPOSC 0x03000000 + +/* USB clock sources */ +#define MRCC_CKUSB_Internal 0xFFBFFFFF +#define MRCC_CKUSB_External 0x00400000 + +/* MRCC Interrupts */ +#define MRCC_IT_LOCK 0x40000000 +#define MRCC_IT_NCKD 0x00080000 + +/* Peripheral Clock */ +#define MRCC_Peripheral_ALL 0x1975623F +#define MRCC_Peripheral_EXTIT 0x10000000 +#define MRCC_Peripheral_RTC 0x08000000 +#define MRCC_Peripheral_GPIO 0x01000000 +#define MRCC_Peripheral_UART2 0x00400000 +#define MRCC_Peripheral_UART1 0x00200000 +#define MRCC_Peripheral_UART0 0x00100000 +#define MRCC_Peripheral_I2C 0x00040000 +#define MRCC_Peripheral_CAN 0x00010000 +#define MRCC_Peripheral_SSP1 0x00004000 +#define MRCC_Peripheral_SSP0 0x00002000 +#define MRCC_Peripheral_USB 0x00000200 +#define MRCC_Peripheral_PWM 0x00000020 +#define MRCC_Peripheral_TIM2 0x00000010 +#define MRCC_Peripheral_TIM1 0x00000008 +#define MRCC_Peripheral_TIM0 0x00000004 +#define MRCC_Peripheral_TB 0x00000002 +#define MRCC_Peripheral_ADC 0x00000001 + +/* Clock sources to measure theire frequency */ +#define MRCC_ClockSource_CKSYS 0x01 +#define MRCC_ClockSource_HCLK 0x02 +#define MRCC_ClockSource_PCLK 0x03 +#define MRCC_ClockSource_CKTIM 0x04 + +/* Low Power Debug Mode */ +#define MRCC_LPDM_Disable 0xFFFFFFF7 +#define MRCC_LPDM_Enable 0x00000008 + +/* WFI Mode parameters */ +#define MRCC_WFIParam_FLASHPowerDown 0x00000000 +#define MRCC_WFIParam_FLASHOn 0x00000010 +#define MRCC_WFIParam_FLASHOff 0x00004000 + +/* STOP Mode parameters */ +#define MRCC_STOPParam_Default 0x00000000 +#define MRCC_STOPParam_OSC4MOff 0x00008000 +#define MRCC_STOPParam_FLASHOff 0x00004000 +#define MRCC_STOPParam_MVREGOff 0x00002000 + +/* I/O Pins voltage range */ +#define MRCC_IOVoltageRange_5V 0xFFFEFFFF +#define MRCC_IOVoltageRange_3V3 0x00010000 + +/* Clock sources to output on MCO pin */ +#define MRCC_MCO_HCLK 0x00000000 +#define MRCC_MCO_PCLK 0x00000040 +#define MRCC_MCO_OSC4M 0x00000080 +#define MRCC_MCO_CKPLL2 0x000000C0 +#define MRCC_MCOPrescaler_1 0xFFFFFFDF +#define MRCC_MCOPrescaler_2 0x00000020 + +/* 4MHz main oscillator configuration */ +#define MRCC_OSC4M_Default 0xFFFCFFFF +#define MRCC_OSC4M_Disable 0x00020000 +#define MRCC_OSC4M_Bypass 0x00010000 + +/* OSC32K oscillator configuration */ +#define MRCC_OSC32K_Disable 0xDFFFFFFF +#define MRCC_OSC32K_Enable 0x20000000 +#define MRCC_OSC32KBypass_Disable 0xBFFFFFFF +#define MRCC_OSC32KBypass_Enable 0x40000000 + +/* LPOSC oscillator configuration */ +#define MRCC_LPOSC_Disable 0xEFFFFFFF +#define MRCC_LPOSC_Enable 0x10000000 + +/* RTC measurement configuration */ +#define MRCC_RTCM_Disable 0xFBFFFFFF +#define MRCC_RTCM_Enable 0x04000000 + +/* MRCC Flags */ +#define MRCC_FLAG_LOCK 0x3F +#define MRCC_FLAG_LOCKIF 0x3D +#define MRCC_FLAG_CKSEL 0x37 +#define MRCC_FLAG_CKOSCSEL 0x35 +#define MRCC_FLAG_NCKD 0x32 +#define MRCC_FLAG_SWR 0x5D +#define MRCC_FLAG_WDGR 0x5C +#define MRCC_FLAG_EXTR 0x5B +#define MRCC_FLAG_WKP 0x5A +#define MRCC_FLAG_STDB 0x59 +#define MRCC_FLAG_BCOUNT 0x58 +#define MRCC_FLAG_OSC32KRDY 0x7F +#define MRCC_FLAG_CKRTCOK 0x7B +#define MRCC_FLAG_LPDONE 0x67 +#define MRCC_FLAG_LP 0x60 + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void MRCC_DeInit(void); +void MRCC_XTDIV2Config(u32 MRCC_XTDIV2); +ErrorStatus MRCC_CKSYSConfig(u32 MRCC_CKSYS, u32 MRCC_PLL); +void MRCC_HCLKConfig(u32 MRCC_HCLK); +void MRCC_CKTIMConfig(u32 MRCC_CKTIM); +void MRCC_PCLKConfig(u32 MRCC_PCLK); +ErrorStatus MRCC_CKRTCConfig(u32 MRCC_CKRTC); +ErrorStatus MRCC_CKUSBConfig(u32 MRCC_CKUSB); +void MRCC_ITConfig(u32 MRCC_IT, FunctionalState NewState); +void MRCC_PeripheralClockConfig(u32 MRCC_Peripheral, FunctionalState NewState); +void MRCC_PeripheralSWResetConfig(u32 MRCC_Peripheral, FunctionalState NewState); +void MRCC_GetClocksStatus(MRCC_ClocksTypeDef* MRCC_ClocksStatus); +void MRCC_LPMC_DBGConfig(u32 MRCC_LPDM); +void MRCC_EnterWFIMode(u32 MRCC_WFIParam); +void MRCC_EnterSTOPMode(u32 MRCC_STOPParam); +void MRCC_EnterSTANDBYMode(void); +void MRCC_GenerateSWReset(void); +void MRCC_WriteBackupRegister(MRCC_BKPReg MRCC_BKP, u32 Data); +u32 MRCC_ReadBackupRegister(MRCC_BKPReg MRCC_BKP); +void MRCC_IOVoltageRangeConfig(u32 MRCC_IOVoltageRange); +void MRCC_MCOConfig(u32 MRCC_MCO, u32 MCO_MCOPrescaler); +ErrorStatus MRCC_OSC4MConfig(u32 MRCC_OSC4M); +ErrorStatus MRCC_OSC32KConfig(u32 MRCC_OSC32K, u32 MRCC_OSC32KBypass); +ErrorStatus MRCC_LPOSCConfig(u32 MRCC_LPOSC); +void MRCC_RTCMConfig(u32 MRCC_RTCM); +void MRCC_SetBuilderCounter(u8 BuilderCounter); +u16 MRCC_GetCKSYSCounter(void); +FlagStatus MRCC_GetFlagStatus(u8 MRCC_FLAG); +void MRCC_ClearFlag(u8 MRCC_FLAG); +ITStatus MRCC_GetITStatus(u32 MRCC_IT); +void MRCC_ClearITPendingBit(u32 MRCC_IT); +ErrorStatus MRCC_WaitForOSC4MStartUp(void); + +#endif /* __75x_MRCC_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_pwm.h b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_pwm.h new file mode 100644 index 000000000..28edba9e8 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_pwm.h @@ -0,0 +1,215 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_pwm.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* PWM software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_PWM_H +#define __75x_PWM_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +/* Exported types ------------------------------------------------------------*/ + +typedef struct +{ + u16 PWM_Mode; /* PWM Mode */ + u16 PWM_Prescaler; /* Prescaler value */ + u16 PWM_CounterMode; /* Counter mode: Up/Down, Edge aligned or center aligned */ + u16 PWM_Period; /* Period value */ + u16 PWM_Complementary; /* Complementary PWM selection */ + u16 PWM_OCState; /* Output compare off-state in Run mode */ + u16 PWM_OCNState; /* Complementary Output compare off-state in Run mode */ + u16 PWM_Channel; /* PWM Channel: 1, 2 or 3 */ + u16 PWM_Pulse1; /* PWM or OCM Channel 1 pulse length */ + u16 PWM_Pulse2; /* PWM or OCM Channel 2 pulse length */ + u16 PWM_Pulse3; /* PWM or OCM Channel 3 pulse length */ + u16 PWM_Polarity1; /* PWM, OCM or OPM Channel 1 polarity */ + u16 PWM_Polarity2; /* PWM or OCM Channel 2 polarity */ + u16 PWM_Polarity3; /* PWM or OCM Channel 3 polarity */ + u16 PWM_Polarity1N; /* PWM or OCM Channel 1N polarity */ + u16 PWM_Polarity2N; /* PWM or OCM Channel 2N polarity */ + u16 PWM_Polarity3N; /* PWM or OCM Channel 3N polarity */ + u16 PWM_DTRAccess; /* Enable or disable the configuration of DTR register parameters: + DeadTime, Emergency, LOCKLevel, OSSIState, OCState and OCNState */ + u16 PWM_DeadTime; /* Dead Time value */ + u16 PWM_Emergency; /* Emergency selection: Enable / Disable */ + u16 PWM_LOCKLevel; /* LOCK level */ + u16 PWM_OSSIState; /* Off-State Selection for Idle state */ + u8 PWM_RepetitionCounter; /* Repetition counter value */ +} PWM_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* PWM modes */ +#define PWM_Mode_OCTiming 0x0001 +#define PWM_Mode_OCActive 0x0002 +#define PWM_Mode_OCInactive 0x0003 +#define PWM_Mode_OCToggle 0x0004 +#define PWM_Mode_PWM 0x0005 + +/* PWM Counter Mode */ +#define PWM_CounterMode_Up 0x0000 +#define PWM_CounterMode_Down 0x0010 +#define PWM_CounterMode_CenterAligned1 0x0020 +#define PWM_CounterMode_CenterAligned2 0x0040 +#define PWM_CounterMode_CenterAligned3 0x0060 + +/* PWM Channel */ +#define PWM_Channel_1 0x0001 +#define PWM_Channel_2 0x0002 +#define PWM_Channel_3 0x0004 +#define PWM_Channel_ALL 0x0007 + +/* PWM Polarity channel 1 */ +#define PWM_Polarity1_High 0x0001 +#define PWM_Polarity1_Low 0x0002 + +/* PWM Polarity channel 2 */ +#define PWM_Polarity2_High 0x0001 +#define PWM_Polarity2_Low 0x0002 + +/* PWM Polarity channel 3 */ +#define PWM_Polarity3_High 0x0001 +#define PWM_Polarity3_Low 0x0002 + +/* PWM Polarity channel 1N */ +#define PWM_Polarity1N_High 0x0001 +#define PWM_Polarity1N_Low 0x0002 + +/* PWM Polarity channel 2N */ +#define PWM_Polarity2N_High 0x0001 +#define PWM_Polarity2N_Low 0x0002 + +/* PWM Polarity channel 3N */ +#define PWM_Polarity3N_High 0x0001 +#define PWM_Polarity3N_Low 0x0002 + +/* PWM interrupt sources */ +#define PWM_IT_OC1 0x0100 +#define PWM_IT_OC2 0x0200 +#define PWM_IT_OC3 0x0400 +#define PWM_IT_Update 0x0001 +#define PWM_IT_GlobalUpdate 0x1001 +#define PWM_IT_Emergency 0x8000 + +/* PWM DMA sources */ +#define PWM_DMASource_OC1 0x0100 +#define PWM_DMASource_OC2 0x0200 +#define PWM_DMASource_OC3 0x0400 +#define PWM_DMASource_Update 0x0001 + +/* PWM DMA Base address */ +#define PWM_DMABase_CR 0x0000 +#define PWM_DMABase_SCR 0x0800 +#define PWM_DMABase_OMR1 0x1800 +#define PWM_DMABase_OMR2 0x2000 +#define PWM_DMABase_RSR 0x3000 +#define PWM_DMABase_RER 0x3800 +#define PWM_DMABase_ISR 0x4000 +#define PWM_DMABase_CNT 0x4800 +#define PWM_DMABase_PSC 0x5000 +#define PWM_DMABase_RCR 0x5800 +#define PWM_DMABase_ARR 0x6000 +#define PWM_DMABase_OCR1 0x6800 +#define PWM_DMABase_OCR2 0x7000 +#define PWM_DMABase_OCR3 0x7800 +#define PWM_DMABase_DTR 0xB800 + +/* PWM OCM state */ +#define PWM_OCRMState_Enable 0x0005 +#define PWM_OCRMState_Disable 0x0006 + +/* PWM Flags */ +#define PWM_FLAG_OC1 0x0100 +#define PWM_FLAG_OC2 0x0200 +#define PWM_FLAG_OC3 0x0400 +#define PWM_FLAG_Update 0x0001 +#define PWM_FLAG_Emergency 0x8000 + +/* PWM_ForcedAction */ +#define PWM_ForcedAction_Active 0x000A +#define PWM_ForcedAction_InActive 0x0008 + +/* PWM TRGO Mode */ +#define PWM_TRGOMode_Enable 0x0100 +#define PWM_TRGOMode_Update 0x0200 +#define PWM_TRGOMode_Reset 0x0000 +#define PWM_TRGOMode_OC 0x0300 + +/* PWM Complementary outputs Enable/Disable */ +#define PWM_Complementary_Disable 0x0001 +#define PWM_Complementary_Enable 0x0002 + +/* PWM DTR Access Enable/Disable */ +#define PWM_DTRAccess_Enable 0x0001 +#define PWM_DTRAccess_Disable 0x0002 + +/* PWM Emergency input Enable/Disable */ +#define PWM_Emergency_Disable 0x0000 +#define PWM_Emergency_Enable 0x1000 + +/* OC states */ +#define PWM_OCNState_Disable 0x0001 +#define PWM_OCNState_Enable 0x0002 +#define PWM_OCNState_OffState 0x0003 + +/* OCN states */ +#define PWM_OCState_Disable 0x0004 +#define PWM_OCState_Enable 0x0005 +#define PWM_OCState_OffState 0x0006 + +/* PWM LOCK level */ +#define PWM_LOCKLevel_1 0x0400 +#define PWM_LOCKLevel_2 0x0800 +#define PWM_LOCKLevel_3 0x0C00 +#define PWM_LOCKLevel_OFF 0x0000 + +/* Off State selection for Idle state */ +#define PWM_OSSIState_Disable 0x0000 +#define PWM_OSSIState_Enable 0x2000 + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +void PWM_DeInit(void); +void PWM_Init(PWM_InitTypeDef* PWM_InitStruct); +void PWM_StructInit(PWM_InitTypeDef *PWM_InitStruct); +void PWM_Cmd(FunctionalState Newstate); +void PWM_CtrlPWMOutputs(FunctionalState Newstate); +void PWM_ITConfig(u16 PWM_IT, FunctionalState Newstate); +void PWM_DMAConfig(u16 PWM_DMASources, u16 PWM_OCRMState, u16 PWM_DMABase); +void PWM_DMACmd(u16 PWM_DMASources, FunctionalState Newstate); +void PWM_SetPrescaler(u16 Prescaler); +void PWM_SetPeriod(u16 Period); +void PWM_SetPulse(u16 PWM_Channel, u16 Pulse); +void PWM_SetPulse1(u16 Pulse); +void PWM_SetPulse2(u16 Pulse); +void PWM_SetPulse3(u16 Pulse); +void PWM_DebugCmd(FunctionalState Newstate); +void PWM_CounterModeConfig(u16 PWM_CounterMode); +void PWM_ForcedOCConfig(u16 PWM_Channel, u16 PWM_ForcedAction); +void PWM_SetDeadTime(u16 DeadTime); +void PWM_ResetCounter(void); +void PWM_TRGOSelection(u16 PWM_TRGOMode); +FlagStatus PWM_GetFlagStatus(u16 PWM_FLAG); +void PWM_ClearFlag(u16 PWM_FLAG); +ITStatus PWM_GetITStatus(u16 PWM_IT); +void PWM_ClearITPendingBit(u16 PWM_IT); + +#endif /* __75x_PWM_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_rtc.h b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_rtc.h new file mode 100644 index 000000000..a54dee958 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_rtc.h @@ -0,0 +1,63 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_rtc.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* RTC software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_RTC_H +#define __75x_RTC_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* RTC interrupts define */ +#define RTC_IT_Overflow 0x0004 /* Overflow interrupt */ +#define RTC_IT_Alarm 0x0002 /* Alarm interrupt */ +#define RTC_IT_Second 0x0001 /* Second interrupt */ + +/* RTC interrupts flags */ +#define RTC_FLAG_RTOFF 0x0020 /* RTC Operation OFF flag */ +#define RTC_FLAG_RSF 0x0008 /* Registers Synchronized flag */ +#define RTC_FLAG_Overflow 0x0004 /* Overflow interrupt flag */ +#define RTC_FLAG_Alarm 0x0002 /* Alarm interrupt flag */ +#define RTC_FLAG_Second 0x0001 /* Second interrupt flag */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void RTC_DeInit(void); +void RTC_ITConfig(u16 RTC_IT, FunctionalState NewState); +void RTC_EnterConfigMode(void); +void RTC_ExitConfigMode(void); +u32 RTC_GetCounter(void); +void RTC_SetCounter(u32 CounterValue); +void RTC_SetPrescaler(u32 PrescalerValue); +u32 RTC_GetPrescaler(void); +void RTC_SetAlarm(u32 AlarmValue); +u32 RTC_GetDivider(void); +void RTC_WaitForLastTask(void); +void RTC_WaitForSynchro(void); +FlagStatus RTC_GetFlagStatus(u16 RTC_FLAG); +void RTC_ClearFlag(u16 RTC_FLAG); +ITStatus RTC_GetITStatus(u16 RTC_IT); +void RTC_ClearITPendingBit(u16 RTC_IT); + +#endif /* __75x_RTC_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_smi.h b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_smi.h new file mode 100644 index 000000000..1e4a71bd2 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_smi.h @@ -0,0 +1,111 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_smi.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* SMI software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_SMI_H +#define __75x_SMI_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +/* Exported types ------------------------------------------------------------*/ +typedef struct +{ + u8 SMI_ClockHold; + u8 SMI_Prescaler; + u8 SMI_DeselectTime; +} SMI_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* SMI mode */ +#define SMI_Mode_HW 0xEFFFFFFF +#define SMI_Mode_SW 0x10000000 + +/* Reception Length */ +#define SMI_RxLength_0Bytes 0x00000000 +#define SMI_RxLength_1Byte 0x00000010 +#define SMI_RxLength_2Bytes 0x00000020 +#define SMI_RxLength_3Bytes 0x00000030 +#define SMI_RxLength_4Bytes 0x00000040 + +/* Transmission Length */ +#define SMI_TxLength_0Bytes 0x00000000 +#define SMI_TxLength_1Byte 0x00000001 +#define SMI_TxLength_2Bytes 0x00000002 +#define SMI_TxLength_3Bytes 0x00000003 +#define SMI_TxLength_4Bytes 0x00000004 + +/* SMI memory Banks */ +#define SMI_Bank_0 0x00000001 +#define SMI_Bank_1 0x00000002 +#define SMI_Bank_2 0x00000004 +#define SMI_Bank_3 0x00000008 + +/* SMI Interrupts */ +#define SMI_IT_WC 0x00000200 +#define SMI_IT_TF 0x00000100 + +/* Fast Read Mode */ +#define SMI_FastRead_Disable 0xFFFF7FFF +#define SMI_FastRead_Enable 0x00008000 + +/* Write Burst Mode */ +#define SMI_WriteBurst_Disable 0xDFFFFFFF +#define SMI_WriteBurst_Enable 0x20000000 + +/* SMI Flags */ +#define SMI_FLAG_Bank3_WM 0x00008000 +#define SMI_FLAG_Bank2_WM 0x00004000 +#define SMI_FLAG_Bank1_WM 0x00002000 +#define SMI_FLAG_Bank0_WM 0x00001000 +#define SMI_FLAG_ERF2 0x00000800 +#define SMI_FLAG_ERF1 0x00000400 +#define SMI_FLAG_WC 0x00000200 +#define SMI_FLAG_TF 0x00000100 + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void SMI_DeInit(void); +void SMI_Init(SMI_InitTypeDef* SMI_InitStruct); +void SMI_StructInit(SMI_InitTypeDef* SMI_InitStruct); +void SMI_ModeConfig(u32 SMI_Mode); +void SMI_TxRxLengthConfig(u32 SMI_TxLength, u32 SMI_RxLength); +void SMI_BankCmd(u32 SMI_Bank, FunctionalState NewState); +void SMI_ITConfig(u32 SMI_IT, FunctionalState NewState); +void SMI_SelectBank(u32 SMI_Bank); +void SMI_SendWENCmd(void); +void SMI_SendRSRCmd(void); +void SMI_SendCmd(u32 Command); +void SMI_FastReadConfig(u32 SMI_FastRead); +void SMI_WriteBurstConfig(u32 SMI_WriteBurst); +void SMI_WriteByte(u32 WriteAddr, u8 Data); +void SMI_WriteHalfWord(u32 WriteAddr, u16 Data); +void SMI_WriteWord(u32 WriteAddr, u32 Data); +u8 SMI_ReadByte(u32 ReadAddr); +u16 SMI_ReadHalfWord(u32 ReadAddr); +u32 SMI_ReadWord(u32 ReadAddr); +u8 SMI_ReadMemoryStatusRegister(void); +FlagStatus SMI_GetFlagStatus(u32 SMI_FLAG); +void SMI_ClearFlag(u32 SMI_FLAG); +ITStatus SMI_GetITStatus(u32 SMI_IT); +void SMI_ClearITPendingBit(u32 SMI_IT); + +#endif /* __75x_SMI_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_ssp.h b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_ssp.h new file mode 100644 index 000000000..96dec886a --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_ssp.h @@ -0,0 +1,135 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_SSP.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* SSP software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_SSP_H +#define __75x_SSP_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* SSP Init structure definition */ +typedef struct +{ + u16 SSP_FrameFormat; + u16 SSP_Mode; + u16 SSP_CPOL; + u16 SSP_CPHA; + u16 SSP_DataSize; + u16 SSP_NSS; + u16 SSP_SlaveOutput; + u8 SSP_ClockRate; + u8 SSP_ClockPrescaler; +}SSP_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* SSP Frame Format Select */ +#define SSP_FrameFormat_TI 0x0010 +#define SSP_FrameFormat_Motorola 0xFFCF + +/* SSP Master/Slave Select */ +#define SSP_Mode_Master 0xFFFB +#define SSP_Mode_Slave 0x0004 + +/* SSP Clock Polarity */ +#define SSP_CPOL_Low 0xFFBF +#define SSP_CPOL_High 0x0040 + +/* SSP Clock Phase */ +#define SSP_CPHA_1Edge 0xFF7F +#define SSP_CPHA_2Edge 0x0080 + +/* SSP Data Size */ +#define SSP_DataSize_16b 0x000F +#define SSP_DataSize_15b 0x000E +#define SSP_DataSize_14b 0x000D +#define SSP_DataSize_13b 0x000C +#define SSP_DataSize_12b 0x000B +#define SSP_DataSize_11b 0x000A +#define SSP_DataSize_10b 0x0009 +#define SSP_DataSize_9b 0x0008 +#define SSP_DataSize_8b 0x0007 +#define SSP_DataSize_7b 0x0006 +#define SSP_DataSize_6b 0x0005 +#define SSP_DataSize_5b 0x0004 +#define SSP_DataSize_4b 0x0003 + +/* SSP Slave Select management config */ +#define SSP_NSS_Hard 0xFFEF +#define SSP_NSS_Soft 0x0010 + +/* SSP NSS internal config */ +#define SSP_NSSInternal_Set 0x0020 +#define SSP_NSSInternal_Reset 0xFFDF + +/* SSP Slave output config */ +#define SSP_SlaveOutput_Enable 0xFFF7 +#define SSP_SlaveOutput_Disable 0x0008 + +/* SSP Interrupts */ +#define SSP_IT_TxFifo 0x0008 +#define SSP_IT_RxFifo 0x0004 +#define SSP_IT_RxTimeOut 0x0002 +#define SSP_IT_RxOverrun 0x0001 + +/* SSP Flags */ +#define SSP_FLAG_Busy 0x0024 +#define SSP_FLAG_RxFifoFull 0x0023 +#define SSP_FLAG_RxFifoNotEmpty 0x0022 +#define SSP_FLAG_TxFifoNotFull 0x0021 +#define SSP_FLAG_TxFifoEmpty 0x0020 +#define SSP_FLAG_TxFifo 0x0043 +#define SSP_FLAG_RxFifo 0x0042 +#define SSP_FLAG_RxTimeOut 0x0041 +#define SSP_FLAG_RxOverrun 0x0040 + +/* SSP DMA Requests */ +#define SSP0_DMA_Transmit 0x0002 +#define SSP0_DMA_Receive 0x0001 + +#define SSP0_DMATxReq_Single 0xFFF7 +#define SSP0_DMATxReq_Burst 0x0008 + +#define SSP0_DMARxReq_Single 0xFFFB +#define SSP0_DMARxReq_Burst 0x0004 + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void SSP_DeInit(SSP_TypeDef* SSPx); +void SSP_Init(SSP_TypeDef* SSPx, SSP_InitTypeDef* SSP_InitStruct); +void SSP_StructInit(SSP_InitTypeDef* SSP_InitStruct); +void SSP_Cmd(SSP_TypeDef* SSPx, FunctionalState NewState); +void SSP_ITConfig(SSP_TypeDef* SSPx, u16 SSP_IT, FunctionalState NewState); +void SSP_DMACmd(u16 SSP0_DMAtransfer, FunctionalState NewState); +void SSP_DMATxConfig(u16 SSP0_DMATxReq); +void SSP_DMARxConfig(u16 SSP0_DMARxReq); +void SSP_SendData(SSP_TypeDef* SSPx, u16 Data); +u16 SSP_ReceiveData(SSP_TypeDef* SSPx); +void SSP_LoopBackConfig(SSP_TypeDef* SSPx, FunctionalState NewState); +void SSP_NSSInternalConfig(SSP_TypeDef* SSPx, u16 SSP_NSSState); +FlagStatus SSP_GetFlagStatus(SSP_TypeDef* SSPx, u16 SSP_FLAG); +void SSP_ClearFlag(SSP_TypeDef* SSPx, u16 SSP_FLAG); +ITStatus SSP_GetITStatus(SSP_TypeDef* SSPx, u16 SSP_IT); +void SSP_ClearITPendingBit(SSP_TypeDef* SSPx, u16 SSP_IT); + +#endif /* __75x_SSP_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_tb.h b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_tb.h new file mode 100644 index 000000000..e5054935d --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_tb.h @@ -0,0 +1,93 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_tb.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* TB software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_TB_H +#define __75x_TB_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +/* Exported types ------------------------------------------------------------*/ +typedef struct +{ + u16 TB_Mode; /* TB mode */ + u16 TB_ClockSource; /* TB clock source: CK_TIM or CK_RTC */ + u16 TB_CounterMode; /* TB counter mode */ + u16 TB_ICAPolarity; /* TB Input Capture signal Polarity */ + u16 TB_Prescaler; /* TB Prescaler factor */ + u16 TB_AutoReload; /* TB AutoReload factor */ +} TB_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* TB modes */ +#define TB_Mode_IC 0x0002 +#define TB_Mode_Timing 0x0001 + +/* TB clock source */ +#define TB_ClockSource_CKTIM 0x0001 +#define TB_ClockSource_CKRTC 0x0002 + +/* TB Input capture polarity */ +#define TB_ICAPolarity_Rising 0x7000 +#define TB_ICAPolarity_Falling 0x8000 + +/* TB counter modes */ +#define TB_CounterMode_Up 0x0000 +#define TB_CounterMode_Down 0x0010 +#define TB_CounterMode_CenterAligned 0x0060 + +/* TB interrupt sources */ +#define TB_IT_Update 0x0001 +#define TB_IT_IC 0x0004 +#define TB_IT_GlobalUpdate 0x8001 + +/* TB Flags */ +#define TB_FLAG_IC 0x0004 +#define TB_FLAG_Update 0x0001 + +/* TB Slave Mode Selection */ +#define TB_SMSMode_Trigger 0x0018 +#define TB_SMSMode_Gated 0x0010 +#define TB_SMSMode_External 0x0008 +#define TB_SMSMode_Reset 0x0000 + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void TB_DeInit(void); +void TB_Init(TB_InitTypeDef* TB_InitStruct); +void TB_StructInit(TB_InitTypeDef *TB_InitStruct); +void TB_Cmd(FunctionalState Newstate ); +void TB_ITConfig(u16 TB_IT, FunctionalState Newstate); +void TB_SetPrescaler(u16 Prescaler); +void TB_ResetCounter(void); +void TB_DebugCmd(FunctionalState Newstate); +void TB_CounterModeConfig(u16 TB_CounterMode); +void TB_SLaveModeConfig(u16 TB_SMSMode); +u16 TB_GetCounter(void); +u16 TB_GetICAP1(void); +void TB_SetCounter(u16 Counter); +FlagStatus TB_GetFlagStatus(u16 TB_FLAG); +void TB_ClearFlag(u16 TB_FLAG); +ITStatus TB_GetITStatus(u16 TB_IT); +void TB_ClearITPendingBit(u16 TB_IT); + +#endif /* __75x_TB_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_tim.h b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_tim.h new file mode 100644 index 000000000..02b51321b --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_tim.h @@ -0,0 +1,232 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_tim.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* TIM software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_TIM_H +#define __75x_TIM_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +/* Exported types ------------------------------------------------------------*/ +typedef struct +{ + u16 TIM_Mode; /* Timer Mode */ + u16 TIM_Prescaler; /* Prescaler value */ + u16 TIM_ClockSource; /* Timer clock source */ + u16 TIM_ExtCLKEdge; /* External clock edge */ + u16 TIM_CounterMode; /* Counter mode: Up/Down, Edge aligned or center aligned */ + u16 TIM_Period; /* Period value */ + u16 TIM_Channel; /* Timer Channel: 1, 2 or All */ + u16 TIM_Pulse1; /* PWM or OCM Channel 1 pulse length */ + u16 TIM_Pulse2; /* PWM or OCM Channel 2 pulse length */ + u16 TIM_RepetitivePulse; /* OPM Repetitive pulse state: enable or disable */ + u16 TIM_Polarity1; /* PWM, OCM or OPM Channel 1 polarity */ + u16 TIM_Polarity2; /* PWM or OCM Channel 2 polarity */ + u16 TIM_IC1Selection; /* Input Capture 1 selection: TI1 or TI2 */ + u16 TIM_IC2Selection; /* Input Capture 2 selection: TI1 or TI2 */ + u16 TIM_IC1Polarity; /* Input Capture 1 polarity */ + u16 TIM_IC2Polarity; /* Input Capture 2 polarity */ + u16 TIM_PWMI_ICSelection; /* PWM Input Capture selection: TI1 or TI2 */ + u16 TIM_PWMI_ICPolarity; /* PWM Input Capture Polarity */ +} TIM_InitTypeDef; + +/* Master and slave synchronized Timer peripherals */ +typedef enum +{ + PWM_Master = 0x01, + TIM0_Master, + TIM1_Master, + TIM2_Master +}Master_TypeDef; + +typedef enum +{ + PWM_Slave = 0x05, + TIM0_Slave, + TIM1_Slave, + TIM2_Slave +}Slave_TypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* TIM modes */ +#define TIM_Mode_OCTiming 0x0001 +#define TIM_Mode_OCActive 0x0002 +#define TIM_Mode_OCInactive 0x0003 +#define TIM_Mode_OCToggle 0x0004 +#define TIM_Mode_PWM 0x0005 +#define TIM_Mode_PWMI 0x0006 +#define TIM_Mode_IC 0x0007 +#define TIM_Mode_Encoder1 0x0008 +#define TIM_Mode_Encoder2 0x0009 +#define TIM_Mode_Encoder3 0x000A +#define TIM_Mode_OPM_PWM 0x000B +#define TIM_Mode_OPM_Toggle 0x000C +#define TIM_Mode_OPM_Active 0x000D + +/* TIM Clock Source */ +#define TIM_ClockSource_Internal 0x0001 +#define TIM_ClockSource_TI11 0x0002 +#define TIM_ClockSource_TI12 0x0003 +#define TIM_ClockSource_TI22 0x0004 +#define TIM_ClockSource_TI21 0x0005 + +/* TIM External Clock Edge */ +#define TIM_ExtCLKEdge_Falling 0x0001 +#define TIM_ExtCLKEdge_Rising 0x0002 + +/* TIM Counter Mode */ +#define TIM_CounterMode_Up 0x0000 +#define TIM_CounterMode_Down 0x0010 +#define TIM_CounterMode_CenterAligned1 0x0020 +#define TIM_CounterMode_CenterAligned2 0x0040 +#define TIM_CounterMode_CenterAligned3 0x0060 + +/* TIM Channel */ +#define TIM_Channel_1 0x0001 +#define TIM_Channel_2 0x0002 +#define TIM_Channel_ALL 0x0003 + +/* TIM Polarity channel 1 */ +#define TIM_Polarity1_High 0x0001 +#define TIM_Polarity1_Low 0x0002 + +/* TIM Polarity channel 2 */ +#define TIM_Polarity2_High 0x0001 +#define TIM_Polarity2_Low 0x0002 + +#define TIM_RepetitivePulse_Disable 0x0005 +#define TIM_RepetitivePulse_Enable 0x0006 + +/* TIM Input Capture channel 1 Selection */ +#define TIM_IC1Selection_TI1 0x0001 +#define TIM_IC1Selection_TI2 0x0002 + +/* TIM Input Capture channel 2 Selection */ +#define TIM_IC2Selection_TI1 0x0001 +#define TIM_IC2Selection_TI2 0x0002 + +/* TIM Input Capture channel 1 Polarity */ +#define TIM_IC1Polarity_Falling 0x0001 +#define TIM_IC1Polarity_Rising 0x0002 + +/* TIM Input Capture channel 2 Polarity */ +#define TIM_IC2Polarity_Falling 0x0001 +#define TIM_IC2Polarity_Rising 0x0002 + +/* TIM PWM Input IC Selection */ +#define TIM_PWMI_ICSelection_TI1 0x0001 +#define TIM_PWMI_ICSelection_TI2 0x0002 + +/* TIM PWM Input IC Polarity */ +#define TIM_PWMI_ICPolarity_Falling 0x0003 +#define TIM_PWMI_ICPolarity_Rising 0x0004 + +/* TIM interrupt sources */ +#define TIM_IT_IC1 0x0004 +#define TIM_IT_IC2 0x0008 +#define TIM_IT_OC1 0x0100 +#define TIM_IT_OC2 0x0200 +#define TIM_IT_Update 0x0001 +#define TIM_IT_GlobalUpdate 0x1001 + +/* TIM DMA sources */ +#define TIM_DMASource_IC1 0x0004 +#define TIM_DMASource_IC2 0x0008 +#define TIM_DMASource_OC1 0x0100 +#define TIM_DMASource_OC2 0x0200 +#define TIM_DMASource_Update 0x0001 + +/* TIM DMA Base address */ +#define TIM_DMABase_CR 0x0000 +#define TIM_DMABase_SCR 0x0800 +#define TIM_DMABase_IMCR 0x1000 +#define TIM_DMABase_OMR1 0x1800 +#define TIM_DMABase_RSR 0x3000 +#define TIM_DMABase_RER 0x3800 +#define TIM_DMABase_ISR 0x4000 +#define TIM_DMABase_CNT 0x4800 +#define TIM_DMABase_PSC 0x5000 +#define TIM_DMABase_ARR 0x6000 +#define TIM_DMABase_OCR1 0x6800 +#define TIM_DMABase_OCR2 0x7000 +#define TIM_DMABase_ICR1 0x9800 +#define TIM_DMABase_ICR2 0xA000 + +/* TIM Flags */ +#define TIM_FLAG_IC1 0x0004 +#define TIM_FLAG_IC2 0x0008 +#define TIM_FLAG_OC1 0x0100 +#define TIM_FLAG_OC2 0x0200 +#define TIM_FLAG_Update 0x0001 + +/* TIM_ForcedAction */ +#define TIM_ForcedAction_Active 0x000A +#define TIM_ForcedAction_InActive 0x0008 + +/* TIM synchronization action */ +#define TIM_SynchroAction_Enable 0x0100 +#define TIM_SynchroAction_Update 0x0200 +#define TIM_SynchroAction_Reset 0x0000 +#define TIM_SynchroAction_OC 0x0300 + +/* TIM synchronization mode */ +#define TIM_SynchroMode_Gated 0x0010 +#define TIM_SynchroMode_Trigger 0x0018 +#define TIM_SynchroMode_External 0x0008 +#define TIM_SynchroMode_Reset 0x0000 + +/* OCRM bit states */ +#define TIM_OCRMState_Enable 0x0005 +#define TIM_OCRMState_Disable 0x0006 + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +void TIM_DeInit(TIM_TypeDef *TIMx); +void TIM_Init(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct); +void TIM_StructInit(TIM_InitTypeDef *TIM_InitStruct); +void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState Newstate); +void TIM_ITConfig(TIM_TypeDef *TIMx, u16 TIM_IT, FunctionalState Newstate); +void TIM_PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_Channel, FunctionalState Newstate); +void TIM_DMAConfig(u16 TIM_DMASources, u16 TIM_OCRMState, u16 TIM_DMABase); +void TIM_DMACmd(u16 TIM_DMASources, FunctionalState Newstate); +void TIM_ClockSourceConfig(TIM_TypeDef *TIMx, u16 TIM_ClockSource, + u16 TIM_ExtCLKEdge); +void TIM_SetPrescaler(TIM_TypeDef* TIMx, u16 Prescaler); +void TIM_SetPeriod(TIM_TypeDef* TIMx, u16 Period); +void TIM_SetPulse(TIM_TypeDef* TIMx, u16 TIM_Channel, u16 Pulse); +u16 TIM_GetICAP1(TIM_TypeDef *TIMx); +u16 TIM_GetICAP2(TIM_TypeDef *TIMx); +u16 TIM_GetPWMIPulse(TIM_TypeDef *TIMx); +u16 TIM_GetPWMIPeriod(TIM_TypeDef *TIMx); +void TIM_DebugCmd(TIM_TypeDef *TIMx, FunctionalState Newstate); +void TIM_CounterModeConfig(TIM_TypeDef* TIMx, u16 TIM_CounterMode); +void TIM_ForcedOCConfig(TIM_TypeDef* TIMx, u16 TIM_Channel, + u16 TIM_ForcedAction); +void TIM_ResetCounter(TIM_TypeDef* TIMx); +void TIM_SynchroConfig(Master_TypeDef Master, Slave_TypeDef Slave, + u16 TIM_SynchroAction, u16 TIM_SynchroMode); +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, u16 TIM_FLAG); +void TIM_ClearFlag(TIM_TypeDef* TIMx, u16 TIM_FLAG); +ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, u16 TIM_IT); +void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, u16 TIM_IT); + +#endif /* __75x_TIM_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_type.h b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_type.h new file mode 100644 index 000000000..6f8842700 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_type.h @@ -0,0 +1,71 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_type.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the common data types used for the +* STR75x software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_TYPE_H +#define __75x_TYPE_H + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +typedef signed long s32; +typedef signed short s16; +typedef signed char s8; + +typedef volatile signed long vs32; +typedef volatile signed short vs16; +typedef volatile signed char vs8; + +typedef unsigned long u32; +typedef unsigned short u16; +typedef unsigned char u8; + +typedef volatile unsigned long vu32; +typedef volatile unsigned short vu16; +typedef volatile unsigned char vu8; + +typedef volatile unsigned long const vuc32; /* Read Only */ +typedef volatile unsigned short const vuc16; /* Read Only */ +typedef volatile unsigned char const vuc8; /* Read Only */ + + +typedef enum { FALSE = 0, TRUE = !FALSE } bool; + +typedef enum { RESET = 0, SET = !RESET } FlagStatus, ITStatus; + +typedef enum { DISABLE = 0, ENABLE = !DISABLE} FunctionalState; + +typedef enum { ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +#define U8_MAX ((u8)255) +#define S8_MAX ((s8)127) +#define S8_MIN ((s8)-128) +#define U16_MAX ((u16)65535u) +#define S16_MAX ((s16)32767) +#define S16_MIN ((s16)-32768) +#define U32_MAX ((u32)4294967295uL) +#define S32_MAX ((s32)2147483647) +#define S32_MIN ((s32)-2147483648) + +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +#endif /* __75x_TYPE_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_uart.h b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_uart.h new file mode 100644 index 000000000..6fc5033ab --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_uart.h @@ -0,0 +1,178 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_uart.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* UART software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_UART_H +#define __75x_UART_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* UART FIFO Level enumeration */ +typedef enum +{ + UART_FIFOLevel_1_8 = 0x0000, /* FIFO size 16 bytes, FIFO level 2 bytes */ + UART_FIFOLevel_1_4 = 0x0001, /* FIFO size 16 bytes, FIFO level 4 bytes */ + UART_FIFOLevel_1_2 = 0x0002, /* FIFO size 16 bytes, FIFO level 8 bytes */ + UART_FIFOLevel_3_4 = 0x0003, /* FIFO size 16 bytes, FIFO level 12 bytes */ + UART_FIFOLevel_7_8 = 0x0004 /* FIFO size 16 bytes, FIFO level 14 bytes */ +}UART_FIFOLevel; + +/* UART Init Structure definition */ +typedef struct +{ + u16 UART_WordLength; + u16 UART_StopBits; + u16 UART_Parity; + u32 UART_BaudRate; + u16 UART_HardwareFlowControl; + u16 UART_Mode; + u16 UART_FIFO; + UART_FIFOLevel UART_TxFIFOLevel; + UART_FIFOLevel UART_RxFIFOLevel; +}UART_InitTypeDef; + + +/* UART RTS enumeration */ +typedef enum +{ + RTSRESET = 1, + RTSSET +}UART_RTSTypeDef; + + +/* Exported constants --------------------------------------------------------*/ +/* UART Data Length */ +#define UART_WordLength_5D 0x0000 /* 5 bits Data */ +#define UART_WordLength_6D 0x0020 /* 6 bits Data */ +#define UART_WordLength_7D 0x0040 /* 7 bits Data */ +#define UART_WordLength_8D 0x0060 /* 8 bits Data */ + +/* UART Stop Bits */ +#define UART_StopBits_1 0xFFF7 /* One stop bit is transmitted at + the end of frame */ +#define UART_StopBits_2 0x0008 /* Tow stop bits are transmitted + at the end of frame */ + +/* UART Parity */ +#define UART_Parity_No 0x0000 /* Parity Disable */ +#define UART_Parity_Even 0x0006 /* Even Parity */ +#define UART_Parity_Odd 0x0002 /* Odd Parity */ +#define UART_Parity_OddStick 0x0082 /* 1 is transmitted as bit parity */ +#define UART_Parity_EvenStick 0x0086 /* 0 is transmitted as bit parity */ + +/* UART Hardware Flow Control */ +#define UART_HardwareFlowControl_None 0x0000/* HFC Disable */ +#define UART_HardwareFlowControl_RTS 0x4000/* RTS Enable */ +#define UART_HardwareFlowControl_CTS 0x8000/* CTS Enable */ +#define UART_HardwareFlowControl_RTS_CTS 0xC000/* CTS and RTS Enable */ + +/* UART Mode */ +#define UART_Mode_Rx 0x0200 /* UART Rx Enabled */ +#define UART_Mode_Tx 0x0100 /* UART Tx Enbled */ +#define UART_Mode_Tx_Rx 0x0300 /* UART Tx and Rx Enabled */ + +/* UART FIFO */ +#define UART_FIFO_Disable 0xFFEF /* FIFOs Disable */ +#define UART_FIFO_Enable 0x0010 /* FIFOs Enable */ + +/* UART Interrupt definition */ +#define UART_IT_OverrunError 0x0400 /* Overrun Error interrupt */ +#define UART_IT_BreakError 0x0200 /* Break Error interrupt */ +#define UART_IT_ParityError 0x0100 /* Parity Error interrupt */ +#define UART_IT_FrameError 0x0080 /* Frame Error interrupt */ +#define UART_IT_ReceiveTimeOut 0x0040 /* Receive Time Out interrupt */ +#define UART_IT_Transmit 0x0020 /* Transmit interrupt */ +#define UART_IT_Receive 0x0010 /* Receive interrupt */ +#define UART_IT_CTS 0x0002 /* CTS interrupt */ + +/* UART0 DMA transfer */ +#define UART0_DMATransfer_Single 0xFFF7 /* Single DMA transfer */ +#define UART0_DMATransfer_Burst 0x0008 /* Burst DMA transfer */ + +/* UART0 DMA On Error */ +#define UART0_DMAOnError_Enable 0xFFFB /* DMA receive request enabled + when the UART0 error interrupt + is asserted. */ +#define UART0_DMAOnError_Disable 0x0004 /* DMA receive request disabled + when the UART0 error interrupt + is asserted. */ + +/* UART0 DMA Request */ +#define UART0_DMAReq_Tx 0x0002 /* Transmit DMA Enable */ +#define UART0_DMAReq_Rx 0x0001 /* Receive DMA Enable */ + +/* UART FLAG */ +#define UART_FLAG_OverrunError 0x23 /* Overrun error flag */ +#define UART_FLAG_Break 0x22 /* break error flag */ +#define UART_FLAG_ParityError 0x21 /* parity error flag */ +#define UART_FLAG_FrameError 0x20 /* frame error flag */ +#define UART_FLAG_TxFIFOEmpty 0x47 /* Transmit FIFO Empty flag */ +#define UART_FLAG_RxFIFOFull 0x46 /* Receive FIFO Full flag */ +#define UART_FLAG_TxFIFOFull 0x45 /* Transmit FIFO Full flag */ +#define UART_FLAG_RxFIFOEmpty 0x44 /* Receive FIFO Empty flag */ +#define UART_FLAG_Busy 0x43 /* UART Busy flag */ +#define UART_FLAG_CTS 0x40 /* CTS flag */ +#define UART_RawIT_OverrunError 0x6A /* Overrun Error Masked IT flag */ +#define UART_RawIT_BreakError 0x69 /* Break Error Masked IT flag */ +#define UART_RawIT_ParityError 0x68 /* Parity Error Masked IT flag */ +#define UART_RawIT_FrameError 0x67 /* Frame Error Masked IT flag */ +#define UART_RawIT_ReceiveTimeOut 0x66 /* ReceiveTimeOut Masked IT flag */ +#define UART_RawIT_Transmit 0x65 /* Transmit Masked IT flag */ +#define UART_RawIT_Receive 0x64 /* Receive Masked IT flag */ +#define UART_RawIT_CTS 0x61 /* CTS Masked IT flag */ + +/* UART LIN break length */ +#define UART_LINBreakLength_10 0x0000 /* 10 low bits */ +#define UART_LINBreakLength_11 0x0200 /* 11 low bits */ +#define UART_LINBreakLength_12 0x0400 /* 12 low bits */ +#define UART_LINBreakLength_13 0x0600 /* 13 low bits */ +#define UART_LINBreakLength_14 0x0800 /* 14 low bits */ +#define UART_LINBreakLength_15 0x0A00 /* 15 low bits */ +#define UART_LINBreakLength_16 0x0C00 /* 16 low bits */ +#define UART_LINBreakLength_17 0x0E00 /* 17 low bits */ +#define UART_LINBreakLength_18 0x1000 /* 18 low bits */ +#define UART_LINBreakLength_19 0x1200 /* 19 low bits */ +#define UART_LINBreakLength_20 0x1400 /* 20 low bits */ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void UART_DeInit(UART_TypeDef* UARTx); +void UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef* UART_InitStruct); +void UART_StructInit(UART_InitTypeDef* UART_InitStruct); +void UART_Cmd(UART_TypeDef* UARTx, FunctionalState NewState); +void UART_ITConfig(UART_TypeDef* UARTx, u16 UART_IT, FunctionalState NewState); +void UART_DMAConfig(u16 UART0_DMATransfer, u16 UART0_DMAOnError); +void UART_DMACmd(u16 UART0_DMAReq, FunctionalState NewState); +void UART_LoopBackConfig(UART_TypeDef* UARTx, FunctionalState NewState); +void UART_LINConfig(UART_TypeDef* UARTx, u16 UART_LINBreakLength); +void UART_LINCmd(UART_TypeDef* UARTx, FunctionalState NewState); +void UART_SendData(UART_TypeDef* UARTx, u8 Data); +u8 UART_ReceiveData(UART_TypeDef* UARTx); +void UART_SendBreak(UART_TypeDef* UARTx); +void UART_RTSConfig(UART_TypeDef* UARTx,UART_RTSTypeDef RTSState); +FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, u16 UART_FLAG); +void UART_ClearFlag(UART_TypeDef* UARTx, u16 UART_FLAG); +ITStatus UART_GetITStatus(UART_TypeDef* UARTx, u16 UART_IT); +void UART_ClearITPendingBit(UART_TypeDef* UARTx, u16 UART_IT); + +#endif /* __75x_UART_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_wdg.h b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_wdg.h new file mode 100644 index 000000000..3390b63f3 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_wdg.h @@ -0,0 +1,62 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_wdg.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* WDG software library. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __75x_WDG_H +#define __75x_WDG_H + +/* Includes ------------------------------------------------------------------*/ +#include "75x_map.h" + +/* Exported types ------------------------------------------------------------*/ + typedef struct +{ + u16 WDG_Mode; /* Watchdog or Timer mode */ + u16 WDG_Preload; /* Preload register */ + u8 WDG_Prescaler; /* Prescaler register */ +}WDG_InitTypeDef; +/* Exported constants --------------------------------------------------------*/ + +/* WDG/Timer Select */ +#define WDG_Mode_WDG 0x0001 +#define WDG_Mode_Timer 0xFFFE + +/* WDG End of Count interrupt request */ +#define WDG_IT_EC 0x0001 + +/* WDG end of count Flag */ +#define WDG_FLAG_EC 0x0001 + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void WDG_DeInit(void); +void WDG_Init(WDG_InitTypeDef* WDG_InitStruct); +void WDG_StructInit(WDG_InitTypeDef* WDG_InitStruct); +void WDG_Cmd(FunctionalState NewState); +void WDG_ITConfig(FunctionalState NewState); +u16 WDG_GetCounter(void); +FlagStatus WDG_GetFlagStatus(void); +void WDG_ClearFlag(void); +ITStatus WDG_GetITStatus(void); +void WDG_ClearITPendingBit(void); + +#endif /* __WDG_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/lcd.h b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/lcd.h new file mode 100644 index 000000000..11df54c1b --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/inc/lcd.h @@ -0,0 +1,120 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : lcd.h +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file contains all the functions prototypes for the +* lcd software driver. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion ---------------------------------------*/ +#ifndef __LCD_H +#define __LCD_H + +/* Includes --------------------------------------------------------------------*/ +#include "75x_lib.h" + +/* Exported types --------------------------------------------------------------*/ + + /* Data lines configuration mode */ + typedef enum + { + Input, + Output + } DataConfigMode_TypeDef; + + /* Text color mode */ + typedef enum + { + BlackText=0, + WhiteText=1 + } TextColorMode_TypeDef; + + /* Dot On/Off mode */ + typedef enum + { + Dot_On, + Dot_Off + } DotMode_TypeDef; + +/* Exported constants ----------------------------------------------------------*/ + +/* LCD Control pins */ +#define CtrlPin_E2 0x00000001 +#define CtrlPin_E1 0x00000002 +#define CtrlPin_RW 0x00000004 +#define CtrlPin_DI 0x00000008 + +/* LCD Commands */ +#define DISPLAY_ON 0xAF +#define DISPLAY_OFF 0xAE +#define START_LINE 0xC0 +#define START_COLUMN 0x00 +#define CLOCKWISE_OUTPUT 0xA0 +#define DYNAMIC_DRIVE 0xA4 +#define DUTY_CYCLE 0xA9 +#define READ_MODIFY_WRITE_OFF 0xEE +#define SOFTWARE_RESET 0xE2 + +/* LCD Lines when LCD is managed as 2*17 characters */ +#define Line1 0x0 +#define Line2 0x2 + +/* Exported macro --------------------------------------------------------------*/ +/* Exported functions ----------------------------------------------------------*/ +/*----- Low layer function -----*/ +void LCD_CtrlLinesConfig(void); +void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, u32 CtrlPins, BitAction BitVal); +void LCD_DataLinesConfig(DataConfigMode_TypeDef Mode); +void LCD_DataLinesWrite(GPIO_TypeDef* GPIOx, u32 PortVal); + +/*----- Medium layer function -----*/ +void LCD_CheckMasterStatus(void); +void LCD_CheckSlaveStatus(void); +void LCD_SendMasterCmd(u8 Cmd); +void LCD_SendSlaveCmd(u8 Cmd); +void LCD_SendMasterData(u8 Data); +u32 LCD_ReadMasterData(void); +void LCD_SendSlaveData(u8 Data); +u32 LCD_ReadSlaveData(void); +void LCD_SetMasterPage(u8 Page); +void LCD_SetSlavePage(u8 Page); +void LCD_SetMasterColumn(u8 Address); +void LCD_SetSlaveColumn(u8 Address); +void LCD_DrawChar(u8 Line, u8 Column, u8 Width, u8 *Bmp); +u8 LCD_HexToAsciiLow(u8 byte); +u8 LCD_HexToAsciiHigh(u8 byte); +void LCD_SetTextColor(TextColorMode_TypeDef TextColor); + +/*----- High layer function -----*/ +void LCD_Init(void); +/* LCD managed as 2 Lines, 17 characters each one (2Lines*17Char) */ +void LCD_ClearLine(u8 Line); +void LCD_DisplayChar(u8 Line, u8 Column, u8 Ascii, TextColorMode_TypeDef CharMode); +void LCD_DisplayString(u8 Line, u8 *ptr, TextColorMode_TypeDef CharMode); +void LCD_Printf(u8* ptr, ...); +/* LCD managed as 122*32 dots */ +void LCD_ClearMaster(void); +void LCD_ClearSlave(void); +void LCD_Clear(void); +void LCD_DrawMasterGraphic(u8 *Bmp); +void LCD_DrawSlaveGraphic(u8 *Bmp); +void LCD_DrawGraphic(u8 *Bmp); +void LCD_ScrollGraphic(u8 *Bmp, u32 nCount); +void LCD_DrawPixel(u8 XPos, u8 YPos, DotMode_TypeDef Mode); +void LCD_DrawLine(u8 XPos1, u8 YPos1, u8 XPos2, u8 YPos2); +void LCD_DrawBox(u8 XPos, u8 YPos, u8 Dx, u8 Dy); + +#endif /*__LCD_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE******/ diff --git a/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_adc.c b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_adc.c new file mode 100644 index 000000000..93905cb6c --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_adc.c @@ -0,0 +1,869 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_adc.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the ADC software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_adc.h" +#include "75x_mrcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Mask for Power Down Mode */ +#define ADC_PowerDown_Enable 0x8000 +#define ADC_PowerDown_Disable 0x7FFF + +/* Mask for Watchdog Thresholds Enable */ +#define ADC_AnalogWatchdog_Enable 0x8000 +#define ADC_AnalogWatchdog_Disable 0x7FFF + +/* Mask for Injected conversion start */ +#define ADC_Injec_ConversionStart 0x8000 + +/* DMA enable */ +#define ADC_DMA_ExtEnable_Mask 0x4000 + +/* Injected start trigger enable */ +#define ADC_Injec_ExtTrigger_Enable 0x4000 + +/* ADC Masks */ +#define ADC_DMAFirstEnabledChannel_Mask 0x000F +#define ADC_DataRegisterOffset 0x0050 +#define ADC_FirstChannel_Mask 0xFFF0 +#define ADC_ChannelNumber_Mask 0xFC3F +#define ADC_Threshold_Mask 0xFC00 +#define ADC_AnalogWatchdogChannel_Mask 0xC3FF +#define ADC_Prescalers_Mask 0x7F18 +#define ADC_SPEN_Mask 0x8000 +#define ADC_FallingEdge_Mask 0xEFFF +#define ADC_LowLevel_Mask 0x4000 +#define ADC_HighLevel_Mask 0xDFFF +#define ADC_Calibration_Mask 0x0002 + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : ADC_DeInit +* Description : Deinitializes the ADC peripheral registers to their default +* reset values. +* Input : None. +* Output : None +* Return : None. +*******************************************************************************/ +void ADC_DeInit(void) +{ + /* Reset the ADC registers values*/ + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_ADC,ENABLE); + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_ADC,DISABLE); +} + +/******************************************************************************* +* Function Name : ADC_Init +* Description : Initializes the ADC peripheral according to the specified +* parameters in the ADC_InitStruct. +* Input : - ADC_InitStruct: pointer to an ADC_InitTypeDef structure that + contains the configuration information for the ADC peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_Init(ADC_InitTypeDef* ADC_InitStruct) +{ + /* Configure the conversion mode */ + if(ADC_InitStruct->ADC_ConversionMode == ADC_ConversionMode_Scan) + { + /* Set the scan conversion mode */ + ADC->CLR2 |= ADC_ConversionMode_Scan; + } + else + { + /* Set the one-shot conversion mode */ + ADC->CLR2 &= ADC_ConversionMode_OneShot; + } + + /* Configure the external start conversion trigger */ + switch(ADC_InitStruct->ADC_ExtTrigger) + { + case ADC_ExtTrigger_HighLevel: + /* Start conversion on High level of the external trigger (TIM0) */ + ADC->CLR0 &= ADC_HighLevel_Mask; + ADC->CLR0 |= ADC_ExtTrigger_HighLevel; + break; + + case ADC_ExtTrigger_LowLevel: + /* Start conversion on low level of the external trigger (TIM0) */ + ADC->CLR0 &= ADC_ExtTrigger_LowLevel; + ADC->CLR0 |= ADC_LowLevel_Mask; + break; + + case ADC_ExtTrigger_RisingEdge: + /* Start conversion on rising edge of the external trigger (TIM0) */ + ADC->CLR0 |= ADC_ExtTrigger_RisingEdge; + break; + + case ADC_ExtTrigger_FallingEdge: + /* Start conversion on falling edge of the external trigger (TIM0) */ + ADC->CLR0 &= ADC_FallingEdge_Mask; + ADC->CLR0 |= ADC_ExtTrigger_FallingEdge; + break; + + case ADC_ExtTrigger_Disable: + /* Disable the external trigger and start the conversion by software */ + ADC->CLR0 &= ADC_ExtTrigger_Disable; + break; + + default: + break; + } + + /* Configure the auto clock off feature */ + if (ADC_InitStruct->ADC_AutoClockOff == ADC_AutoClockOff_Enable) + { + /* Enable the auto clock off feature */ + ADC->CLR4 |= ADC_AutoClockOff_Enable; + } + else + { + /* Disable the auto clock off feature */ + ADC->CLR4 &= ADC_AutoClockOff_Disable; + } + + /* Clear conversion prescaler CNVP[2:0], sampling prescaler SMPP[2:0] bits + and Sample prescaler enable SPEN bit */ + ADC->CLR1 &= ADC_Prescalers_Mask; + /* Set conversion prescaler value (sampling and conversion prescalers are equal + while SPEN bit is reset */ + ADC->CLR1 |= (ADC_InitStruct->ADC_ConversionPrescaler<<5); + + /* In case ADC_SamplingPrescaler member is different from the conversion one */ + if(ADC_InitStruct->ADC_SamplingPrescaler != ADC_InitStruct->ADC_ConversionPrescaler) + { + /* Set the sampling prescaler value */ + ADC->CLR1 |= ADC_InitStruct->ADC_SamplingPrescaler; + /* Set SPEN bit (sampling and conversion prescalers are different */ + ADC->CLR1 = (ADC->CLR1 | ADC_SPEN_Mask); + } + + /* Clear first channel to be converted FCH[3:0] bits */ + ADC->CLR2 &= ADC_FirstChannel_Mask; + /* Set the first channel to be converted */ + ADC->CLR2 |= ADC_InitStruct->ADC_FirstChannel; + /* Clear number of channels to be converted NCH[3:0] bits */ + ADC->CLR2 &= ADC_ChannelNumber_Mask; + /* Set the number of channels to be converted */ + ADC->CLR2 |= ((ADC_InitStruct->ADC_ChannelNumber)-1<<6); +} + +/******************************************************************************* +* Function Name : ADC_StructInit +* Description : Fills each ADC_InitStruct member with its default value. +* Input : - ADC_InitStruct: pointer to an ADC_InitTypeDef structure + which will be initialized. +* Output : None +* Return : None. +*******************************************************************************/ +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) +{ + /* Initialize the ADC_ConversionMode member */ + ADC_InitStruct->ADC_ConversionMode = ADC_ConversionMode_OneShot; + + /* Initialize the ADC_ExtTrigger member */ + ADC_InitStruct->ADC_ExtTrigger = ADC_ExtTrigger_Disable; + + /* Initialize the ADC_AutoClockOff member */ + ADC_InitStruct->ADC_AutoClockOff = ADC_AutoClockOff_Disable; + + /* Initialize the ADC_SamplingPrescaler member */ + ADC_InitStruct->ADC_SamplingPrescaler = 0; + + /* Initialize the ADC_ConversionPrescaler member */ + ADC_InitStruct->ADC_ConversionPrescaler = 0; + + /* Initialize the ADC_FirstChannel member */ + ADC_InitStruct->ADC_FirstChannel = ADC_CHANNEL0; + + /* Initialize the ADC_ChannelNumber member */ + ADC_InitStruct->ADC_ChannelNumber = 1; + } + +/******************************************************************************* +* Function Name : ADC_StartCalibration +* Description : Starts the ADC Calibration. Calibration average enabled/disabled. +* Input : - ADC_CalibAverage: Enables or disables ADC calibration average. +* This parameter can be one of the following values: +* - ADC_CalibAverage_Enable: enable calibration average +* - ADC_CalibAverage_Disable: disable calibration average +* Output : None +* Return : None +*******************************************************************************/ +void ADC_StartCalibration(u16 ADC_CalibAverage) +{ + if (ADC_CalibAverage == ADC_CalibAverage_Enable) + { + /* Enable ADC Calibration Average */ + ADC->CLR4 &= ADC_CalibAverage_Enable; + } + else + { + /* Disable ADC Calibration Average */ + ADC->CLR4 |= ADC_CalibAverage_Disable; + } + + /* Start Calibration */ + ADC->CLR0 |= ADC_Calibration_ON; +} + +/******************************************************************************* +* Function Name : ADC_GetCalibrationStatus +* Description : Get the ADC Calibration Status. +* Input : None +* Output : None +* Return : The NewState of the ADC calibration (SET or RESET). +*******************************************************************************/ +FlagStatus ADC_GetCalibrationStatus(void) +{ + /* Check the status of the ADC calibration */ + if((ADC->CLR0 & ADC_Calibration_Mask) != RESET) + { + /* Return SET if ADC Calibration is on going */ + return SET; + } + else + { + /* Return RESET if ADC Calibration is finished */ + return RESET; + } +} + +/******************************************************************************* +* Function Name : ADC_ConversionCmd +* Description : Starts or stops the ADC conversion. +* Input : - ADC_Conversion: specifies the ADC command to apply. +* This parameter can be one of the following values: +* - ADC_Conversion_Start: start conversion +* - ADC_Conversion_Stop: stop conversion +* Output : None +* Return : None +*******************************************************************************/ +void ADC_ConversionCmd (u16 ADC_Conversion) +{ + if (ADC_Conversion == ADC_Conversion_Start) + { + /* Start the ADC Conversion */ + ADC->CLR0 |= ADC_Conversion_Start; + } + else + { + /* Stop the ADC Conversion */ + ADC->CLR0 &= ADC_Conversion_Stop; + } +} + +/******************************************************************************* +* Function Name : ADC_GetSTARTBitStatus +* Description : Gets the ADC START/STOP bit Status. +* Input : None +* Output : None +* Return : The NewState of the ADC START/STOP bit (SET or RESET). +*******************************************************************************/ +FlagStatus ADC_GetSTARTBitStatus(void) +{ + /* Check the status of the ADC START/STOP bit */ + if((ADC->CLR0 & ADC_Conversion_Start) != RESET) + { + /* Return SET if ADC Conversion is started */ + return SET; + } + else + { + /* Return RESET if ADC Conversion is stopped */ + return RESET; + } +} + +/******************************************************************************* +* Function Name : ADC_Cmd +* Description : Enables the ADC peripheral or puts it in power down mode. +* - NewState: new state of the ADC peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void ADC_Cmd(FunctionalState NewState) +{ + if (NewState == DISABLE) + { + /* Enable ADC Power Down Mode */ + ADC->CLR4 |= ADC_PowerDown_Enable; + } + else + { + /* Disable ADC Power Down Mode */ + ADC->CLR4 &= ADC_PowerDown_Disable; + } +} + +/******************************************************************************* +* Function Name : ADC_AutoClockOffConfig +* Description : Enables or disables the Auto clock off feature. +* - NewState: new state of the Auto clock off feature. This +* parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void ADC_AutoClockOffConfig(FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Enable ADC Auto Clock Off */ + ADC->CLR4 |= ADC_AutoClockOff_Enable; + } + else + { + /* Disable ADC Auto Clock Off */ + ADC->CLR4 &= ADC_AutoClockOff_Disable; + } +} + +/******************************************************************************* +* Function Name : ADC_AnalogWatchdogConfig +* Description : Configures the analog input channel to be used for the selected +* Analog Watchdog and defines its corresponding High and Low +* threshold values. +* Input : - ADC_AnalogWatchdog: specifies the analog watchdog which will +* be affected to the desired converted channel. This parameter +* can be one of the following values: +* - ADC_AnalogWatchdog0: select analog watchdog 0 +* - ADC_AnalogWatchdog1: select analog watchdog 1 +* - ADC_AnalogWatchdog2: select analog watchdog 2 +* - ADC_AnalogWatchdog3: select analog watchdog 3 +* - ADC_CHANNEL: specifies the channel linked to the selected +* analog watchdog. This parameter can be ADC_CHANNELx where x +* can be (0..15) +* - LowThreshold: Low Threshold for the selected Analog watchdog +* - HighThreshold: High Threshold for the selected Analog watchdog +* Output : None +* Return : None +*******************************************************************************/ +void ADC_AnalogWatchdogConfig(u16 ADC_AnalogWatchdog, u8 ADC_CHANNEL, + u16 LowThreshold, u16 HighThreshold) +{ + switch (ADC_AnalogWatchdog) + { + /* Set the selected channel and their corresponding High and Low thresholds */ + case ADC_AnalogWatchdog0 : + ADC->TRA0 = (ADC->TRA0 & ADC_AnalogWatchdogChannel_Mask) | ((u16) ADC_CHANNEL<<10); + ADC->TRA0 = (ADC->TRA0 & ADC_Threshold_Mask) | HighThreshold; + ADC->TRB0 = (ADC->TRB0 & ADC_Threshold_Mask) | LowThreshold; + break; + + case ADC_AnalogWatchdog1 : + ADC->TRA1 = (ADC->TRA1 & ADC_AnalogWatchdogChannel_Mask) | ((u16) ADC_CHANNEL<<10); + ADC->TRA1 = (ADC->TRA1 & ADC_Threshold_Mask) | HighThreshold; + ADC->TRB1 = (ADC->TRB1 & ADC_Threshold_Mask) | LowThreshold; + break; + + case ADC_AnalogWatchdog2 : + ADC->TRA2 = (ADC->TRA2 & ADC_AnalogWatchdogChannel_Mask) | ((u16) ADC_CHANNEL<<10); + ADC->TRA2 = (ADC->TRA2 & ADC_Threshold_Mask) | HighThreshold; + ADC->TRB2 = (ADC->TRB2 & ADC_Threshold_Mask) | LowThreshold; + break; + + case ADC_AnalogWatchdog3 : + ADC->TRA3 = (ADC->TRA3 & ADC_AnalogWatchdogChannel_Mask) | ((u16) ADC_CHANNEL<<10); + ADC->TRA3 = (ADC->TRA3 & ADC_Threshold_Mask) | HighThreshold; + ADC->TRB3 = (ADC->TRB3 & ADC_Threshold_Mask) | LowThreshold; + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : ADC_AnalogWatchdogCmd +* Description : Enables or disables the selected analog Watchdog. +* Input : - ADC_AnalogWatchdog: specifies the analog watchdog to be +* enabled or disabled. This parameter can be one of the +* following values: +* - ADC_AnalogWatchdog0: select analog watchdog 0 +* - ADC_AnalogWatchdog1: select analog watchdog 1 +* - ADC_AnalogWatchdog2: select analog watchdog 2 +* - ADC_AnalogWatchdog3: select analog watchdog 3 +* - NewState: new state of the specified analog watchdog. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void ADC_AnalogWatchdogCmd(u16 ADC_AnalogWatchdog, FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Enable the selected ADC AnalogWatchdogx */ + switch (ADC_AnalogWatchdog) + { + case ADC_AnalogWatchdog0 : + ADC->TRB0 |= ADC_AnalogWatchdog_Enable; + break; + + case ADC_AnalogWatchdog1 : + ADC->TRB1 |= ADC_AnalogWatchdog_Enable; + break; + + case ADC_AnalogWatchdog2 : + ADC->TRB2 |= ADC_AnalogWatchdog_Enable; + break; + + case ADC_AnalogWatchdog3 : + ADC->TRB3 |= ADC_AnalogWatchdog_Enable; + break; + + default: + break; + } + } + else + { + /* Disable the selected ADC AnalogWatchdogx */ + switch (ADC_AnalogWatchdog) + { + case ADC_AnalogWatchdog0 : + ADC->TRB0 &= ADC_AnalogWatchdog_Disable; + break; + + case ADC_AnalogWatchdog1 : + ADC->TRB1 &= ADC_AnalogWatchdog_Disable; + break; + + case ADC_AnalogWatchdog2 : + ADC->TRB2 &= ADC_AnalogWatchdog_Disable; + break; + + case ADC_AnalogWatchdog3 : + ADC->TRB3 &= ADC_AnalogWatchdog_Disable; + break; + + default: + break; + } + } +} + +/******************************************************************************* +* Function Name : ADC_GetAnalogWatchdogResult +* Description : Returns the comparison result of the selected analog watchdog. +* Input : - ADC_AnalogWatchdog: specifies the analog watchdog channel +* which its comparison result will be returned. This parameter +* can be one of the following values: +* - ADC_AnalogWatchdog0: select analog watchdog 0 +* - ADC_AnalogWatchdog1: select analog watchdog 1 +* - ADC_AnalogWatchdog2: select analog watchdog 2 +* - ADC_AnalogWatchdog3: select analog watchdog 3 +* Output : None +* Return : The analog watchdog comparaison result value +*******************************************************************************/ +u16 ADC_GetAnalogWatchdogResult(u16 ADC_AnalogWatchdog) +{ + /* Return the selected ADC AnalogWatchdogx comparaison result */ + switch(ADC_AnalogWatchdog) + { + case ADC_AnalogWatchdog0 : + return ((ADC->PBR & ADC_AnalogWatchdog)>>4); + + case ADC_AnalogWatchdog1 : + return ((ADC->PBR & ADC_AnalogWatchdog)>>6); + + case ADC_AnalogWatchdog2 : + return ((ADC->PBR & ADC_AnalogWatchdog)>>8); + + case ADC_AnalogWatchdog3 : + return ((ADC->PBR & ADC_AnalogWatchdog)>>10); + + default : return (0xFF); /* if a wrong value of ADC_AnalogWatchdog is selected */ + } +} + +/******************************************************************************* +* Function Name : ADC_InjectedConversionConfig +* Description : Configures the start trigger level for the injected channels +* and the injected analog input channels to be converted. +* Input : - ADC_Injec_ExtTrigger: specifies the start trigger level. +* This parameter can be one of the following values: +* - ADC_Injec_ExtTrigger_Disable : external trigger disabled +* - ADC_Injec_ExtTrigger_RisingEdge: external trigger +* configured as rising edge of PWM Timer TRGO signal +* - ADC_Injec_ExtTrigger_FallingEdge: external trigger +* configured as falling edge of PWM Timer TRGO signal +* - FirstChannel: specifies the first injected channel to be +* converted. +* This parameter can be ADC_CHANNELx where x can be (0..15). +* - ChannelNumber: specifies the Number of the injected channels +* to be converted. This parameter can be a value from 1 to 16. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_InjectedConversionConfig(u16 ADC_Injec_ExtTrigger, u8 FirstChannel, u8 ChannelNumber) +{ + /* Configure the external start injected conversion trigger */ + switch (ADC_Injec_ExtTrigger) + { + case ADC_Injec_ExtTrigger_Disable : + /* Disable the external trigger and start the injected conversion by software */ + ADC->CLR3 &= ADC_Injec_ExtTrigger_Disable ; + break; + case ADC_Injec_ExtTrigger_RisingEdge : + /* Start injected conversion on rising edge of the external trigger (PWM) */ + ADC->CLR3 |= ADC_Injec_ExtTrigger_RisingEdge; + break; + case ADC_Injec_ExtTrigger_FallingEdge : + /* Start injected conversion on falling edge of the external trigger (PWM) */ + ADC->CLR3 |= ADC_Injec_ExtTrigger_Enable; + ADC->CLR3 &= ADC_Injec_ExtTrigger_FallingEdge; + break; + + default: + break; + } + + /* Clear first injected channel to be converted JFCH[3:0] bits */ + ADC->CLR3 &= ADC_FirstChannel_Mask; + /* Set the first injected channel to be converted */ + ADC->CLR3 |= FirstChannel; + /* Clear number of injected channels to be converted JNCH[3:0] bits */ + ADC->CLR3 &= ADC_ChannelNumber_Mask; + /* Set the number of injected channels to be converted */ + ADC->CLR3 |= ((ChannelNumber-1)<<6); +} + +/******************************************************************************* +* Function Name : ADC_StartInjectedConversion +* Description : Starts by software the conversion of the injected input channels. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void ADC_StartInjectedConversion(void) +{ + /* Start the injected ADC Conversion */ + ADC->CLR3 |= ADC_Injec_ConversionStart; +} + +/******************************************************************************* +* Function Name : ADC_GetConversionValue +* Description : Reads the conversion result from the appropriate data register. +* Input : - ADC_CHANNEL :specifies the ADC channel which its conversion +* value have to be returned. This parameter can be ADC_CHANNELx +* where x can be (0..15) to select channelx +* Output : None +* Return : The returned value holds the conversion result of the selected +* channel. +*******************************************************************************/ +u16 ADC_GetConversionValue(u8 ADC_CHANNEL) +{ + /* Return the conversion result of the selected channel */ + return *((u16 *)(ADC_BASE + ((ADC_CHANNEL<<2) + ADC_DataRegisterOffset))); +} + +/******************************************************************************* +* Function Name : ADC_ITConfig +* Description : Enables or disables the specified ADC interrupts. +* Input : - ADC_IT: specifies the ADC interrupts to be enabled or disabled. +* This parameter can be any combination of the following values: +* - ADC_IT_ECH: End of chain conversion interrupt +* - ADC_IT_EOC: End of channel conversion interrupt +* - ADC_IT_JECH: Injected end of chain conversion interrupt +* - ADC_IT_JEOC: Injected end of channel conversion interrupt +* - ADC_IT_AnalogWatchdog0_LowThreshold: +* Analog Watchdog 0 LowThreshold interrupt +* - ADC_IT_AnalogWatchdog0_HighThreshold: +* Analog Watchdog 0 HighThreshold interrupt +* - ADC_IT_AnalogWatchdog1_LowThreshold: +* Analog Watchdog 1 LowThreshold interrupt +* - ADC_IT_AnalogWatchdog1_HighThreshold: +* Analog Watchdog 1 HighThreshold interrupt +* - ADC_IT_AnalogWatchdog2_LowThreshold: +* Analog Watchdog 2 LowThreshold interrupt +* - ADC_IT_AnalogWatchdog2_HighThreshold: +* Analog Watchdog 2 HighThreshold interrupt +* - ADC_IT_AnalogWatchdog3_LowThreshold: +* Analog Watchdog 3 LowThreshold interrupt +* - ADC_IT_AnalogWatchdog3_HighThreshold: +* Analog Watchdog 5 HighThreshold interrupt +* - ADC_IT_ALL: All interrupts +* - NewState: new state of the specified ADC interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_ITConfig(u16 ADC_IT, FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Enable the selected ADC interrupts */ + ADC->IMR |= ADC_IT; + } + else + { + /* Disable the selected ADC interrupts */ + ADC->IMR &= ~ADC_IT; + } +} + +/******************************************************************************* +* Function Name : ADC_DMAConfig +* Description : Configures the ADC’s DMA interface. +* Input : - ADC_DMA_CHANNEL: specifies the channels to be enabled or +* disabled for DMA transfer. This parameter can be any +* combination of ADC_DMA_CHANNELx where x can be (0..15). +* - NewState: new state of the specified ADC DMA channels. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_DMAConfig(u16 ADC_DMA_CHANNEL, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable DMA for the selected channels */ + ADC->DMAR |= ADC_DMA_CHANNEL ; + } + else + { + /* Disable DMA for the selected channels */ + ADC->DMAR &= ~ADC_DMA_CHANNEL; + } +} + +/******************************************************************************* +* Function Name : ADC_DMACmd +* Description : Enable or disable the DMA transfer for the ADC. +* Input : - ADC_DMA: specifies the DMA command. This parameter can be +* one of the following values: +* - ADC_DMA_Disable: disable the DMA capability +* - ADC_DMA_Enable: enabled by setting the global +* enable bit +* - ADC_DMA_ExtTrigger_HighLevel: enabled by detection of +* high level of TIM2 OC2 signal +* - ADC_DMA_ExtTrigger_LowLevel: enabled by detection of +* low level of TIM2 OC2 signal +* Output : None +* Return : None +*******************************************************************************/ +void ADC_DMACmd(u16 ADC_DMA) +{ + /* Configure the DMA external trigger enable */ + switch (ADC_DMA) + { + case ADC_DMA_Disable : + /* Disable DMA transfer */ + ADC->DMAE &= ADC_DMA_Disable; + break; + + case ADC_DMA_Enable : + /* Enable DMA transfer */ + ADC->DMAE |= ADC_DMA_Enable; + break; + + case ADC_DMA_ExtTrigger_HighLevel : + /* Enable DMA transfer on high level of the external trigger (TIM2) */ + ADC->DMAE &= ADC_DMA_Disable; + ADC->DMAE |= ADC_DMA_ExtTrigger_HighLevel; + break; + + case ADC_DMA_ExtTrigger_LowLevel : + /* Enable DMA transfer on low level of the external trigger (TIM2) */ + ADC->DMAE |= ADC_DMA_ExtEnable_Mask; + ADC->DMAE &= ADC_DMA_ExtTrigger_LowLevel; + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : ADC_GetDMAFirstEnabledChannel +* Description : Gets the first DMA-enabled channel configured at the time that +* DMA was last globally enabled. +* Input : None +* Output : None +* Return : The first DMA enabled channel +*******************************************************************************/ +u16 ADC_GetDMAFirstEnabledChannel(void) +{ + /* Return the DMA first enabled channel */ + return (ADC->DMAE & ADC_DMAFirstEnabledChannel_Mask); +} + +/******************************************************************************* +* Function Name : ADC_GetFlagStatus +* Description : Checks whether the specified ADC flag is set or not. +* Input : - ADC_FLAG: specifies the ADC flag to check. This parameter +* can be one of the following values: +* - ADC_FLAG_ECH: End of chain conversion Flag +* - ADC_FLAG_EOC: End of channel conversion Flag +* - ADC_FLAG_JECH: End of injected chain conversion Flag +* - ADC_FLAG_JEOC: End of injected channel conversion Flag +* - ADC_FLAG_AnalogWatchdog0_LowThreshold: +* Analog Watchdog 0 LowThreshold Flag +* - ADC_FLAG_AnalogWatchdog0_HighThreshold: +* Analog Watchdog 0 HighThreshold Flag +* - ADC_FLAG_AnalogWatchdog1_LowThreshold: +* Analog Watchdog 1 LowThreshold Flag +* - ADC_FLAG_AnalogWatchdog1_HighThreshold: +* Analog Watchdog 1 HighThreshold Flag +* - ADC_FLAG_AnalogWatchdog2_LowThreshold: +* Analog Watchdog 2 LowThreshold Flag +* - ADC_FLAG_AnalogWatchdog2_HighThreshold: +* Analog Watchdog 2 HighThreshold Flag +* - ADC_FLAG_AnalogWatchdog3_LowThreshold: +* Analog Watchdog 3 LowThreshold Flag +* - ADC_FLAG_AnalogWatchdog3_HighThreshold: +* Analog Watchdog 3 HighThreshold Flag +* Output : None +* Return : The new state of the ADC_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus ADC_GetFlagStatus(u16 ADC_FLAG) +{ + /* Check the status of the specified ADC flag */ + if((ADC->PBR & ADC_FLAG) != RESET) + { + /* Return SET if ADC_FLAG is set */ + return SET; + } + else + { + /* Return RESET if ADC_FLAG is reset */ + return RESET; + } +} + +/******************************************************************************* +* Function Name : ADC_ClearFlag +* Description : Clears the ADC’s pending flags. +* Input : - ADC_FLAG: specifies the flag to clear. This parameter can +* be any combination of the following values: +* - ADC_FLAG_ECH: End of chain conversion flag +* - ADC_FLAG_EOC: End of channel conversion flag +* - ADC_FLAG_JECH: Injected end of chain conversion flag +* - ADC_FLAG_JEOC: Injected end of channel conversion flag +* - ADC_FLAG_AnalogWatchdog0_LowThreshold: +* Analog Watchdog 0 LowThreshold flag +* - ADC_FLAG_AnalogWatchdog0_HighThreshold: +* Analog Watchdog 0 HighThreshold flag +* - ADC_FLAG_AnalogWatchdog1_LowThreshold: +* Analog Watchdog 1 LowThreshold flag +* - ADC_FLAG_AnalogWatchdog1_HighThreshold: +* Analog Watchdog 1 HighThreshold flag +* - ADC_FLAG_AnalogWatchdog2_LowThreshold: +* Analog Watchdog 2 LowThreshold flag +* - ADC_FLAG_AnalogWatchdog2_HighThreshold: +* Analog Watchdog 2 HighThreshold flag +* - ADC_FLAG_AnalogWatchdog3_LowThreshold: +* Analog Watchdog 3 LowThreshold flag +* - ADC_FLAG_AnalogWatchdog3_HighThreshold: +* Analog Watchdog 3 HighThreshold flag +* Output : None +* Return : None +*******************************************************************************/ +void ADC_ClearFlag(u16 ADC_FLAG) +{ + /* Clear the selected ADC flag */ + ADC->PBR = ADC_FLAG; +} + +/******************************************************************************* +* Function Name : ADC_GetITStatus +* Description : Checks whether the specified ADC interrupt has occured or not. +* Input : - ADC_IT: specifies the ADC interrupt source to check. This +* parameter can be one of the following values: +* - ADC_IT_ECH :End of chain conversion interrupt +* - ADC_IT_EOC :End of channel conversion interrupt +* - ADC_IT_JECH :End of injected chain conversion interrupt +* - ADC_IT_JEOC :End of injected channel conversion interrupt +* - ADC_IT_AnalogWatchdog0_LowThreshold: +* Analog Watchdog 0 LowThreshold interrupt +* - ADC_IT_AnalogWatchdog0_HighThreshold: +* Analog Watchdog 0 HighThreshold interrupt +* - ADC_IT_AnalogWatchdog1_LowThreshold: +* Analog Watchdog 1 LowThreshold interrupt +* - ADC_IT_AnalogWatchdog1_HighThreshold: +* Analog Watchdog 1 HighThreshold interrupt +* - ADC_IT_AnalogWatchdog2_LowThreshold: +* Analog Watchdog 2 LowThreshold interrupt +* - ADC_IT_AnalogWatchdog2_HighThreshold: +* Analog Watchdog 2 HighThreshold interrupt +* - ADC_IT_AnalogWatchdog3_LowThreshold: +* Analog Watchdog 3 LowThreshold interrupt +* - ADC_IT_AnalogWatchdog3_HighThreshold: +* Analog Watchdog 3 HighThreshold interrupt +* Output : None +* Return : The new state of the ADC_IT (SET or RESET). +*******************************************************************************/ +ITStatus ADC_GetITStatus(u16 ADC_IT) +{ + /* Check the status of the specified ADC interrupt */ + if((ADC->PBR & ADC_IT) != RESET) + { + /* Return SET if the ADC interrupt flag is set */ + return SET; + } + else + { + /* Return RESET if the ADC interrupt flag is reset */ + return RESET; + } +} + +/******************************************************************************* +* Function Name : ADC_ClearITPendingBit +* Description : Clears the ADC’s interrupt pending bits. +* Input : - ADC_IT: specifies the interrupt pending bit to clear. This +* parameter can be can be any combination of the following +* values: +* - ADC_IT_ECH: End of chain conversion interrupt +* - ADC_IT_EOC: End of channel conversion interrupt +* - ADC_IT_JECH: Injected end of chain conversion interrupt +* - ADC_IT_JEOC: Injected end of channel conversion interrupt +* - ADC_IT_AnalogWatchdog0_LowThreshold: +* Analog Watchdog 0 LowThreshold interrupt +* - ADC_IT_AnalogWatchdog0_HighThreshold: +* Analog Watchdog 0 HighThreshold interrupt +* - ADC_IT_AnalogWatchdog1_LowThreshold: +* Analog Watchdog 1 LowThreshold interrupt +* - ADC_IT_AnalogWatchdog1_HighThreshold: +* Analog Watchdog 1 HighThreshold interrupt +* - ADC_IT_AnalogWatchdog2_LowThreshold: +* Analog Watchdog 2 LowThreshold interrupt +* - ADC_IT_AnalogWatchdog2_HighThreshold: +* Analog Watchdog 2 HighThreshold interrupt +* - ADC_IT_AnalogWatchdog3_LowThreshold: +* Analog Watchdog 3 LowThreshold interrupt +* - ADC_IT_AnalogWatchdog3_HighThreshold: +* Analog Watchdog 5 HighThreshold interrupt +* Output : None +* Return : None +*******************************************************************************/ +void ADC_ClearITPendingBit(u16 ADC_IT) +{ + /* Clear the selected ADC interrupts pending bits */ + ADC->PBR = ADC_IT; +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_can.c b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_can.c new file mode 100644 index 000000000..0472200ba --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_can.c @@ -0,0 +1,765 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_can.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the CAN software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_can.h" +#include "75x_mrcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/*----------------------------------------------------------------------------*/ +/* Macro Name : xxx_ID_MSK, xxx_ID_ARB */ +/* Description : Form the Mask and Arbitration registers value to filter */ +/* a range of identifiers or a fixed identifier, for standard*/ +/* and extended IDs */ +/*----------------------------------------------------------------------------*/ +#define RANGE_ID_MSK(range_start, range_end) (~((range_end) - (range_start))) +#define RANGE_ID_ARB(range_start, range_end) ((range_start) & (range_end)) + +#define FIXED_ID_MSK(id) RANGE_ID_MSK((id), (id)) +#define FIXED_ID_ARB(id) RANGE_ID_ARB((id), (id)) + +#define STD_RANGE_ID_MSK(range_start, range_end) ((u16)((RANGE_ID_MSK((range_start), (range_end)) & 0x7FF) << 2)) +#define STD_RANGE_ID_ARB(range_start, range_end) ((u16)(RANGE_ID_ARB((range_start), (range_end)) << 2)) + +#define STD_FIXED_ID_MSK(id) ((u16)((FIXED_ID_MSK(id) & 0x7FF) << 2)) +#define STD_FIXED_ID_ARB(id) ((u16)(FIXED_ID_ARB(id) << 2)) + +#define EXT_RANGE_ID_MSK_L(range_start, range_end) ((u16)(RANGE_ID_MSK((range_start), (range_end)) >> 11)) +#define EXT_RANGE_ID_MSK_H(range_start, range_end) ((u16)(STD_RANGE_ID_MSK((range_start), (range_end)) | ((RANGE_ID_MSK((range_start), (range_end)) >> 27) & 0x03))) +#define EXT_RANGE_ID_ARB_L(range_start, range_end) ((u16)(RANGE_ID_ARB((range_start), (range_end)) >> 11)) +#define EXT_RANGE_ID_ARB_H(range_start, range_end) ((u16)(STD_RANGE_ID_ARB((range_start), (range_end)) | ((RANGE_ID_ARB((range_start), (range_end)) >> 27) & 0x03))) + +#define EXT_FIXED_ID_MSK_L(id) ((u16)(FIXED_ID_MSK(id) >> 11)) +#define EXT_FIXED_ID_MSK_H(id) ((u16)(STD_FIXED_ID_MSK(id) | ((FIXED_ID_MSK(id) >> 27) & 0x03))) +#define EXT_FIXED_ID_ARB_L(id) ((u16)(FIXED_ID_ARB(id) >> 11)) +#define EXT_FIXED_ID_ARB_H(id) ((u16)(STD_FIXED_ID_ARB(id) | ((FIXED_ID_ARB(id) >> 27) & 0x03))) + +/* macro to format the timing register value from the timing parameters*/ +#define CAN_TIMING(tseg1, tseg2, sjw, brp) ((((tseg2-1) & 0x07) << 12) | (((tseg1-1) & 0x0F) << 8) | (((sjw-1) & 0x03) << 6) | ((brp-1) & 0x3F)) + +/* Private variables ---------------------------------------------------------*/ +/* array of pre-defined timing parameters for standard bitrates*/ +u16 CanTimings[] = { /* value bitrate NTQ TSEG1 TSEG2 SJW BRP */ + CAN_TIMING(11, 4, 4, 5), /* 0x3AC4 100 kbit/s 16 11 4 4 5 */ + CAN_TIMING(11, 4, 4, 4), /* 0x3AC3 125 kbit/s 16 11 4 4 4 */ + CAN_TIMING( 4, 3, 3, 4), /* 0x2383 250 kbit/s 8 4 3 3 4 */ + CAN_TIMING(13, 2, 1, 1), /* 0x1C00 500 kbit/s 16 13 2 1 1 */ + CAN_TIMING( 4, 3, 1, 1), /* 0x2300 1 Mbit/s 8 4 3 1 1 */ +}; + +/* Private function prototypes -----------------------------------------------*/ +static u32 GetFreeIF(void); +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : CAN_DeInit +* Description : Deinitializes the CAN peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void CAN_DeInit (void) +{ + /* Reset the CAN registers values*/ + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_CAN,ENABLE); + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_CAN,DISABLE); +} + +/******************************************************************************* +* Function Name : CAN_Init +* Description : Initializes the CAN peripheral according to the specified +* parameters in the CAN_InitStruct. +* Input : CAN_InitStruct: pointer to a CAN_InitTypeDef structure that +* contains the configuration information for the CAN peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void CAN_Init(CAN_InitTypeDef* CAN_InitStruct) +{ + CAN_EnterInitMode(CAN_CR_CCE | CAN_InitStruct->CAN_ConfigParameters); + CAN_SetBitrate(CAN_InitStruct->CAN_Bitrate); + CAN_LeaveInitMode(); + CAN_LeaveTestMode(); +} + +/******************************************************************************* +* Function Name : CAN_StructInit +* Description : Fills each CAN_InitStruct member with its reset value. +* Input : CAN_InitStruct : pointer to a CAN_InitTypeDef structure which +* will be initialized. +* Output : None +* Return : None. +*******************************************************************************/ +void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct) +{ +/* Reset CAN init structure parameters values */ + CAN_InitStruct->CAN_ConfigParameters = 0x0; + CAN_InitStruct->CAN_Bitrate = 0x2301; +} + +/******************************************************************************* +* Function Name : CAN_SetBitrate +* Description : Setups a standard CAN bitrate. +* Input : bitrate: specifies the bit rate. +* Output : None +* Return : None +*******************************************************************************/ +void CAN_SetBitrate(u32 bitrate) +{ + CAN->BTR = CanTimings[bitrate]; /* write the predefined timing value */ + CAN->BRPR = 0; /* clear the Extended Baud Rate Prescaler */ +} + +/******************************************************************************* +* Function Name : CAN_SetTiming +* Description : Setups the CAN timing with specific parameters +* Input : - tseg1: specifies Time Segment before the sample point. +* This parameter must be a number between 1 and 16. +* - tseg2: Time Segment after the sample point. This parameter +* must be a number between 1 and 8. +* - sjw: Synchronisation Jump Width. This parameter must be +* a number between 1 and 4. +* - brp: Baud Rate Prescaler. This parameter must be a number +* between 1 and 1024. +* Output : None +* Return : None +*******************************************************************************/ +void CAN_SetTiming(u32 tseg1, u32 tseg2, u32 sjw, u32 brp) +{ + CAN->BTR = CAN_TIMING(tseg1, tseg2, sjw, brp); + CAN->BRPR = ((brp-1) >> 6) & 0x0F; +} + +/******************************************************************************* +* Function Name : GetFreeIF +* Description : Searchs the first free message interface, starting from 0. +* Input : None +* Output : None +* Return : A free message interface number (0 or 1) if found, else 2 +*******************************************************************************/ +static u32 GetFreeIF(void) +{ + if ((CAN->sMsgObj[0].CRR & CAN_CRR_BUSY) == 0) + return 0; + else if ((CAN->sMsgObj[1].CRR & CAN_CRR_BUSY) == 0) + return 1; + else + return 2; +} + +/******************************************************************************* +* Function Name : CAN_SetUnusedMsgObj +* Description : Configures the message object as unused +* Input : msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Interface to treat the message +* - ERROR: No interface found to treat the message +*******************************************************************************/ +ErrorStatus CAN_SetUnusedMsgObj(u32 msgobj) +{ + u32 msg_if=0; + + if ((msg_if = GetFreeIF()) == 2) + { + return ERROR; + } + + CAN->sMsgObj[msg_if].CMR = CAN_CMR_WRRD + | CAN_CMR_MASK + | CAN_CMR_ARB + | CAN_CMR_CONTROL + | CAN_CMR_DATAA + | CAN_CMR_DATAB; + + CAN->sMsgObj[msg_if].M1R = 0; + CAN->sMsgObj[msg_if].M2R = 0; + + CAN->sMsgObj[msg_if].A1R = 0; + CAN->sMsgObj[msg_if].A2R = 0; + + CAN->sMsgObj[msg_if].MCR = 0; + + CAN->sMsgObj[msg_if].DA1R = 0; + CAN->sMsgObj[msg_if].DA2R = 0; + CAN->sMsgObj[msg_if].DB1R = 0; + CAN->sMsgObj[msg_if].DB2R = 0; + + CAN->sMsgObj[msg_if].CRR = 1 + msgobj; + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_SetTxMsgObj +* Description : Configures the message object as TX. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* - idType: specifies the identifier type of the frames that +* will be transmitted using this message object. +* This parameter can be one of the following values: +* - CAN_STD_ID (standard ID, 11-bit) +* - CAN_EXT_ID (extended ID, 29-bit) +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Interface to treat the message +* - ERROR: No interface found to treat the message +*******************************************************************************/ +ErrorStatus CAN_SetTxMsgObj(u32 msgobj, u32 idType) +{ + u32 msg_if=0; + + if ((msg_if = GetFreeIF()) == 2) + { + return ERROR; + } + + CAN->sMsgObj[msg_if].CMR = CAN_CMR_WRRD + | CAN_CMR_MASK + | CAN_CMR_ARB + | CAN_CMR_CONTROL + | CAN_CMR_DATAA + | CAN_CMR_DATAB; + + CAN->sMsgObj[msg_if].M1R = 0; + CAN->sMsgObj[msg_if].A1R = 0; + + if (idType == CAN_STD_ID) + { + CAN->sMsgObj[msg_if].M2R = CAN_M2R_MDIR; + CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | CAN_A2R_DIR; + } + else + { + CAN->sMsgObj[msg_if].M2R = CAN_M2R_MDIR | CAN_M2R_MXTD; + CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | CAN_A2R_DIR | CAN_A2R_XTD; + } + + CAN->sMsgObj[msg_if].MCR = CAN_MCR_TXIE | CAN_MCR_EOB; + + CAN->sMsgObj[msg_if].DA1R = 0; + CAN->sMsgObj[msg_if].DA2R = 0; + CAN->sMsgObj[msg_if].DB1R = 0; + CAN->sMsgObj[msg_if].DB2R = 0; + + CAN->sMsgObj[msg_if].CRR = 1 + msgobj; + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_SetRxMsgObj +* Description : Configures the message object as RX. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* - idType: specifies the identifier type of the frames that +* will be transmitted using this message object. +* This parameter can be one of the following values: +* - CAN_STD_ID (standard ID, 11-bit) +* - CAN_EXT_ID (extended ID, 29-bit) +* - idLow: specifies the low part of the identifier range used +* for acceptance filtering. +* - idHigh: specifies the high part of the identifier range +* used for acceptance filtering. +* - singleOrFifoLast: specifies the end-of-buffer indicator. +* This parameter can be one of the following values: +* - TRUE: for a single receive object or a FIFO receive +* object that is the last one of the FIFO. +* - FALSE: for a FIFO receive object that is not the +* last one. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Interface to treat the message +* - ERROR: No interface found to treat the message +*******************************************************************************/ +ErrorStatus CAN_SetRxMsgObj(u32 msgobj, u32 idType, u32 idLow, u32 idHigh, bool singleOrFifoLast) +{ + u32 msg_if=0; + + if ((msg_if = GetFreeIF()) == 2) + { + return ERROR; + } + + CAN->sMsgObj[msg_if].CMR = CAN_CMR_WRRD + | CAN_CMR_MASK + | CAN_CMR_ARB + | CAN_CMR_CONTROL + | CAN_CMR_DATAA + | CAN_CMR_DATAB; + + if (idType == CAN_STD_ID) + { + CAN->sMsgObj[msg_if].M1R = 0; + CAN->sMsgObj[msg_if].M2R = STD_RANGE_ID_MSK(idLow, idHigh); + + CAN->sMsgObj[msg_if].A1R = 0; + CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | STD_RANGE_ID_ARB(idLow, idHigh); + } + else + { + CAN->sMsgObj[msg_if].M1R = EXT_RANGE_ID_MSK_L(idLow, idHigh); + CAN->sMsgObj[msg_if].M2R = CAN_M2R_MXTD | EXT_RANGE_ID_MSK_H(idLow, idHigh); + + CAN->sMsgObj[msg_if].A1R = EXT_RANGE_ID_ARB_L(idLow, idHigh); + CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | CAN_A2R_XTD | EXT_RANGE_ID_ARB_H(idLow, idHigh); + } + + CAN->sMsgObj[msg_if].MCR = CAN_MCR_RXIE | CAN_MCR_UMASK | (singleOrFifoLast ? CAN_MCR_EOB : 0); + + CAN->sMsgObj[msg_if].DA1R = 0; + CAN->sMsgObj[msg_if].DA2R = 0; + CAN->sMsgObj[msg_if].DB1R = 0; + CAN->sMsgObj[msg_if].DB2R = 0; + + CAN->sMsgObj[msg_if].CRR = 1 + msgobj; + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_InvalidateAllMsgObj +* Description : Configures all the message objects as unused. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void CAN_InvalidateAllMsgObj(void) +{ + u32 i=0; + for (i = 0; i < 32; i++) + CAN_SetUnusedMsgObj(i); +} + + +/******************************************************************************* +* Function Name : CAN_ReleaseMessage +* Description : Releases the message object +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Interface to treat the message +* - ERROR: No interface found to treat the message +*******************************************************************************/ +ErrorStatus CAN_ReleaseMessage(u32 msgobj) +{ + u32 msg_if=0; + + if ((msg_if = GetFreeIF()) == 2) + { + return ERROR; + } + + CAN->sMsgObj[msg_if].CMR = CAN_CMR_CLRINTPND | CAN_CMR_TXRQSTNEWDAT; + CAN->sMsgObj[msg_if].CRR = 1 + msgobj; + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_SendMessage +* Description : Start transmission of a message +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* : - pCanMsg: pointer to the message structure containing data +* to transmit. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Transmission OK +* - ERROR: No transmission +*******************************************************************************/ +ErrorStatus CAN_SendMessage(u32 msgobj, canmsg* pCanMsg) +{ + if (CAN->sMsgObj[0].CRR & CAN_CRR_BUSY) + { + return ERROR; + } + + CAN->SR &= ~CAN_SR_TXOK; + + /* read the Arbitration and Message Control*/ + CAN->sMsgObj[0].CMR = CAN_CMR_ARB | CAN_CMR_CONTROL; + + CAN->sMsgObj[0].CRR = 1 + msgobj; + + if (CAN->sMsgObj[0].CRR & CAN_CRR_BUSY) + { + return ERROR; + } + + /* update the contents needed for transmission*/ + CAN->sMsgObj[0].CMR = CAN_CMR_WRRD + | CAN_CMR_ARB + | CAN_CMR_CONTROL + | CAN_CMR_DATAA + | CAN_CMR_DATAB; + + if ((CAN->sMsgObj[0].A2R & CAN_A2R_XTD) == 0) + { + /* standard ID*/ + CAN->sMsgObj[0].A1R = 0; + CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | STD_FIXED_ID_ARB(pCanMsg->Id); + } + else + { + /* extended ID*/ + CAN->sMsgObj[0].A1R = EXT_FIXED_ID_ARB_L(pCanMsg->Id); + CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | EXT_FIXED_ID_ARB_H(pCanMsg->Id); + } + + CAN->sMsgObj[0].MCR = (CAN->sMsgObj[0].MCR & 0xFEF0) | CAN_MCR_NEWDAT | CAN_MCR_TXRQST | pCanMsg->Dlc; + + CAN->sMsgObj[0].DA1R = ((u16)pCanMsg->Data[1]<<8) | pCanMsg->Data[0]; + CAN->sMsgObj[0].DA2R = ((u16)pCanMsg->Data[3]<<8) | pCanMsg->Data[2]; + CAN->sMsgObj[0].DB1R = ((u16)pCanMsg->Data[5]<<8) | pCanMsg->Data[4]; + CAN->sMsgObj[0].DB2R = ((u16)pCanMsg->Data[7]<<8) | pCanMsg->Data[6]; + + CAN->sMsgObj[0].CRR = 1 + msgobj; + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_ReceiveMessage +* Description : Gets the message, if received. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* - release: specifies the message release indicator. +* This parameter can be one of the following values: +* - TRUE: the message object is released when getting +* the data. +* - FALSE: the message object is not released. +* - pCanMsg: pointer to the message structure where received +* data is copied. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Reception OK +* - ERROR: No message pending +*******************************************************************************/ +ErrorStatus CAN_ReceiveMessage(u32 msgobj, bool release, canmsg* pCanMsg) +{ + if (!CAN_IsMessageWaiting(msgobj)) + { + return ERROR; + } + + CAN->SR &= ~CAN_SR_RXOK; + + /* read the message contents*/ + CAN->sMsgObj[1].CMR = CAN_CMR_MASK + | CAN_CMR_ARB + | CAN_CMR_CONTROL + | CAN_CMR_CLRINTPND + | (release ? CAN_CMR_TXRQSTNEWDAT : 0) + | CAN_CMR_DATAA + | CAN_CMR_DATAB; + + CAN->sMsgObj[1].CRR = 1 + msgobj; + + if (CAN->sMsgObj[1].CRR & CAN_CRR_BUSY) + { + return ERROR; + } + + if ((CAN->sMsgObj[1].A2R & CAN_A2R_XTD) == 0) + { + /* standard ID*/ + pCanMsg->IdType = CAN_STD_ID; + pCanMsg->Id = (CAN->sMsgObj[1].A2R >> 2) & 0x07FF; + } + else + { + /* extended ID*/ + pCanMsg->IdType = CAN_EXT_ID; + pCanMsg->Id = ((CAN->sMsgObj[1].A2R >> 2) & 0x07FF); + pCanMsg->Id |= ((u32)CAN->sMsgObj[1].A1R << 11); + pCanMsg->Id |= (((u32)CAN->sMsgObj[1].A2R & 0x0003) << 27); + } + + pCanMsg->Dlc = CAN->sMsgObj[1].MCR & 0x0F; + + pCanMsg->Data[0] = (u8) CAN->sMsgObj[1].DA1R; + pCanMsg->Data[1] = (u8)(CAN->sMsgObj[1].DA1R >> 8); + pCanMsg->Data[2] = (u8) CAN->sMsgObj[1].DA2R; + pCanMsg->Data[3] = (u8)(CAN->sMsgObj[1].DA2R >> 8); + pCanMsg->Data[4] = (u8) CAN->sMsgObj[1].DB1R; + pCanMsg->Data[5] = (u8)(CAN->sMsgObj[1].DB1R >> 8); + pCanMsg->Data[6] = (u8) CAN->sMsgObj[1].DB2R; + pCanMsg->Data[7] = (u8)(CAN->sMsgObj[1].DB2R >> 8); + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_WaitEndOfTx +* Description : Waits until current transmission is finished. +* Input : None +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Transmission ended +* - ERROR: Transmission did not occur yet +*******************************************************************************/ +ErrorStatus CAN_WaitEndOfTx(void) +{ + if ((CAN->SR & CAN_SR_TXOK) == 0) + { + return ERROR; + } + CAN->SR &= ~CAN_SR_TXOK; + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_BasicSendMessage +* Description : Starts transmission of a message in BASIC mode. This mode +* does not use the message RAM. +* Input : pCanMsg: Pointer to the message structure containing data to +* transmit. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Transmission OK +* - ERROR: No transmission +*******************************************************************************/ +ErrorStatus CAN_BasicSendMessage(canmsg* pCanMsg) +{ + /* clear NewDat bit in IF2 to detect next reception*/ + CAN->sMsgObj[1].MCR &= ~CAN_MCR_NEWDAT; + + CAN->SR &= ~CAN_SR_TXOK; + CAN->sMsgObj[0].CMR = CAN_CMR_WRRD + | CAN_CMR_ARB + | CAN_CMR_CONTROL + | CAN_CMR_DATAA + | CAN_CMR_DATAB; + + if (pCanMsg->IdType == CAN_STD_ID) + { + /* standard ID*/ + CAN->sMsgObj[0].A1R = 0; + CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | STD_FIXED_ID_ARB(pCanMsg->Id); + } + else + { + /* extended ID*/ + CAN->sMsgObj[0].A1R = EXT_FIXED_ID_ARB_L(pCanMsg->Id); + CAN->sMsgObj[0].A2R = ((CAN->sMsgObj[0].A2R) & 0xE000) | EXT_FIXED_ID_ARB_H(pCanMsg->Id); + } + + CAN->sMsgObj[0].MCR = (CAN->sMsgObj[0].MCR & 0xFCF0) | pCanMsg->Dlc; + + CAN->sMsgObj[0].DA1R = ((u16)pCanMsg->Data[1]<<8) | pCanMsg->Data[0]; + CAN->sMsgObj[0].DA2R = ((u16)pCanMsg->Data[3]<<8) | pCanMsg->Data[2]; + CAN->sMsgObj[0].DB1R = ((u16)pCanMsg->Data[5]<<8) | pCanMsg->Data[4]; + CAN->sMsgObj[0].DB2R = ((u16)pCanMsg->Data[7]<<8) | pCanMsg->Data[6]; + + /* request transmission*/ + if (CAN->sMsgObj[0].CRR == CAN_CRR_BUSY ) + { + return ERROR; + } + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_BasicReceiveMessage +* Description : Gets the message in BASIC mode, if received. This mode does +* not use the message RAM. +* Input : pCanMsg: pointer to the message structure where message is copied. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Reception OK +* - ERROR: No message pending +*******************************************************************************/ +ErrorStatus CAN_BasicReceiveMessage(canmsg* pCanMsg) +{ + if ((CAN->sMsgObj[1].MCR & CAN_MCR_NEWDAT) == 0) + { + return ERROR; + } + + CAN->SR &= ~CAN_SR_RXOK; + + CAN->sMsgObj[1].CMR = CAN_CMR_ARB + | CAN_CMR_CONTROL + | CAN_CMR_DATAA + | CAN_CMR_DATAB; + + if ((CAN->sMsgObj[1].A2R & CAN_A2R_XTD) == 0) + { + /* standard ID*/ + pCanMsg->IdType = CAN_STD_ID; + pCanMsg->Id = (CAN->sMsgObj[1].A2R >> 2) & 0x07FF; + } + else + { + /* extended ID*/ + pCanMsg->IdType = CAN_EXT_ID; + pCanMsg->Id = ((CAN->sMsgObj[1].A2R >> 2) & 0x07FF); + pCanMsg->Id |= ((u32)CAN->sMsgObj[1].A1R << 11); + pCanMsg->Id |= (((u32)CAN->sMsgObj[1].A2R & 0x0003) << 27); + } + + pCanMsg->Dlc = CAN->sMsgObj[1].MCR & 0x0F; + + pCanMsg->Data[0] = (u8) CAN->sMsgObj[1].DA1R; + pCanMsg->Data[1] = (u8)(CAN->sMsgObj[1].DA1R >> 8); + pCanMsg->Data[2] = (u8) CAN->sMsgObj[1].DA2R; + pCanMsg->Data[3] = (u8)(CAN->sMsgObj[1].DA2R >> 8); + pCanMsg->Data[4] = (u8) CAN->sMsgObj[1].DB1R; + pCanMsg->Data[5] = (u8)(CAN->sMsgObj[1].DB1R >> 8); + pCanMsg->Data[6] = (u8) CAN->sMsgObj[1].DB2R; + pCanMsg->Data[7] = (u8)(CAN->sMsgObj[1].DB2R >> 8); + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_EnterInitMode +* Description : Switchs the CAN into initialization mode. This function must +* be used in conjunction with CAN_LeaveInitMode(). +* Input : InitMask: specifies the CAN configuration in normal mode. +* Output : None +* Return : None +*******************************************************************************/ +void CAN_EnterInitMode(u8 InitMask) +{ + CAN->CR = InitMask | CAN_CR_INIT; + CAN->SR = 0; /* reset the status*/ +} + +/******************************************************************************* +* Function Name : CAN_LeaveInitMode +* Description : Leaves the initialization mode (switch into normal mode). +* This function must be used in conjunction with CAN_EnterInitMode(). +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void CAN_LeaveInitMode(void) +{ + CAN->CR &= ~(CAN_CR_INIT | CAN_CR_CCE); +} + +/******************************************************************************* +* Function Name : CAN_EnterTestMode +* Description : Switchs the CAN into test mode. This function must be used in +* conjunction with CAN_LeaveTestMode(). +* Input : TestMask: specifies the configuration in test modes. +* Output : None +* Return : None +*******************************************************************************/ +void CAN_EnterTestMode(u8 TestMask) +{ + CAN->CR |= CAN_CR_TEST; + CAN->TESTR |= TestMask; +} + +/******************************************************************************* +* Function Name : CAN_LeaveTestMode +* Description : Leaves the current test mode (switch into normal mode). +* This function must be used in conjunction with CAN_EnterTestMode(). +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void CAN_LeaveTestMode(void) +{ + CAN->CR |= CAN_CR_TEST; + CAN->TESTR &= ~(CAN_TESTR_LBACK | CAN_TESTR_SILENT | CAN_TESTR_BASIC); + CAN->CR &= ~CAN_CR_TEST; +} + +/******************************************************************************* +* Function Name : CAN_ReleaseTxMessage +* Description : Releases the transmit message object. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : None +*******************************************************************************/ +void CAN_ReleaseTxMessage(u32 msgobj) +{ + CAN->sMsgObj[0].CMR = CAN_CMR_CLRINTPND | CAN_CMR_TXRQSTNEWDAT; + CAN->sMsgObj[0].CRR = 1 + msgobj; +} + +/******************************************************************************* +* Function Name : CAN_ReleaseRxMessage +* Description : Releases the receive message object. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : None +*******************************************************************************/ +void CAN_ReleaseRxMessage(u32 msgobj) +{ + CAN->sMsgObj[1].CMR = CAN_CMR_CLRINTPND | CAN_CMR_TXRQSTNEWDAT; + CAN->sMsgObj[1].CRR = 1 + msgobj; +} + +/******************************************************************************* +* Function Name : CAN_IsMessageWaiting +* Description : Tests the waiting status of a received message. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : A non-zero value if the corresponding message object has +* received a message waiting to be copied, else 0. +*******************************************************************************/ +u32 CAN_IsMessageWaiting(u32 msgobj) +{ + return (msgobj < 16 ? CAN->ND1R & (1 << msgobj) : CAN->ND2R & (1 << (msgobj-16))); +} + +/******************************************************************************* +* Function Name : CAN_IsTransmitRequested +* Description : Tests the request status of a transmitted message. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : A non-zero value if the corresponding message is requested +* to transmit, else 0. +*******************************************************************************/ +u32 CAN_IsTransmitRequested(u32 msgobj) +{ + return (msgobj < 16 ? CAN->TXR1R & (1 << msgobj) : CAN->TXR2R & (1 << (msgobj-16))); +} + +/******************************************************************************* +* Function Name : CAN_IsInterruptPending +* Description : Tests the interrupt status of a message object. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : A non-zero value if the corresponding message has an +* interrupt pending, else 0. +*******************************************************************************/ +u32 CAN_IsInterruptPending(u32 msgobj) +{ + return (msgobj < 16 ? CAN->IP1R & (1 << msgobj) : CAN->IP2R & (1 << (msgobj-16))); +} + +/******************************************************************************* +* Function Name : CAN_IsObjectValid +* Description : Tests the validity of a message object (ready to use). +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : A non-zero value if the corresponding message object is +* valid, else 0. +*******************************************************************************/ +u32 CAN_IsObjectValid(u32 msgobj) +{ + return (msgobj < 16 ? CAN->MV1R & (1 << msgobj) : CAN->MV2R & (1 << (msgobj-16))); +} +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_cfg.c b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_cfg.c new file mode 100644 index 000000000..593e8b84d --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_cfg.c @@ -0,0 +1,122 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_cfg.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the CFG software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_cfg.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define CFG_SWBOOT_Mask 0xFFFFFFFC +#define CFG_FLASHBusy_Mask 0x00000080 + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : CFG_BootSpaceConfig +* Description : Selects which memory space will be remapped at address 0x00. +* Input : - CFG_BootSpace: specifies the memory space to be remapped +* at address 0x00. +* This parameter can be one of the following values: +* - CFG_BootSpace_FLASH +* - CFG_BootSpace_SRAM +* - CFG_BootSpace_ExtSMI +* Output : None +* Return : None +*******************************************************************************/ +void CFG_BootSpaceConfig(u32 CFG_BootSpace) +{ + u32 Temp = 0; + + /* Clear SW_BOOT[1:0] bits */ + Temp = CFG->GLCONF & CFG_SWBOOT_Mask; + + /* Set SW_BOOT[1:0] bits according to CFG_BootSpace parameter value */ + Temp |= CFG_BootSpace; + + /* Store the new value */ + CFG->GLCONF = Temp; +} + +/******************************************************************************* +* Function Name : CFG_FLASHBurstConfig +* Description : Enables or disables the FLASH Burst mode. +* Input : - CCFG_FLASHBurst: specifies the new state of the FLASH Burst +* mode. +* This parameter can be one of the following values: +* - CFG_FLASHBurst_Disable +* - CFG_FLASHBurst_Enable +* Output : None +* Return : None +*******************************************************************************/ +void CFG_FLASHBurstConfig(u32 CFG_FLASHBurst) +{ + if(CFG_FLASHBurst == CFG_FLASHBurst_Enable) + { + CFG->GLCONF |= CFG_FLASHBurst_Enable; + } + else + { + CFG->GLCONF &= CFG_FLASHBurst_Disable; + } +} + +/******************************************************************************* +* Function Name : CFG_USBFilterConfig +* Description : Enables or disables the USB Filter. +* Input : - CFG_USBFilter: specifies the new state of the USB Filter. +* This parameter can be one of the following values: +* - CFG_USBFilter_Disable +* - CFG_USBFilter_Enable +* Output : None +* Return : None +*******************************************************************************/ +void CFG_USBFilterConfig(u32 CFG_USBFilter) +{ + if(CFG_USBFilter == CFG_USBFilter_Enable) + { + CFG->GLCONF |= CFG_USBFilter_Enable; + } + else + { + CFG->GLCONF &= CFG_USBFilter_Disable; + } +} + +/******************************************************************************* +* Function Name : CFG_GetFlagStatus +* Description : Checks whether the FLASH Busy flag is set or not. +* Input : None +* Output : None +* Return : The new state of FLASH Busy flag (SET or RESET). +*******************************************************************************/ +FlagStatus CFG_GetFlagStatus(void) +{ + if((CFG->GLCONF & CFG_FLASHBusy_Mask) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_dma.c b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_dma.c new file mode 100644 index 000000000..7bc09466d --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_dma.c @@ -0,0 +1,596 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_dma.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the DMA software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_dma.h" +#include "75x_mrcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* DMA enable */ +#define DMA_Enable 0x0001 +#define DMA_Disable 0xFFFE + +/* DMA Last Buffer Sweep */ +#define DMA_Last0_Enable_Mask 0x0001 +#define DMA_Last0_Disable_Mask 0xFFFE +#define DMA_Last1_Enable_Mask 0x0002 +#define DMA_Last1_Disable_Mask 0xFFFD +#define DMA_Last2_Enable_Mask 0x0004 +#define DMA_Last2_Disable_Mask 0xFFFB +#define DMA_Last3_Enable_Mask 0x0008 +#define DMA_Last3_Disable_Mask 0xFFF7 + +/* DMA Masks */ +#define DMA_Stream0_MASK_Mask 0xFFEE +#define DMA_Stream0_CLR_Mask 0x0011 +#define DMA_Stream0_LAST_Mask 0xFFFE + +#define DMA_Stream1_MASK_Mask 0xFFDD +#define DMA_Stream1_CLR_Mask 0x0022 +#define DMA_Stream1_LAST_Mask 0xFFFD + +#define DMA_Stream2_MASK_Mask 0xFFBB +#define DMA_Stream2_CLR_Mask 0x0044 +#define DMA_Stream2_LAST_Mask 0xFFFB + +#define DMA_Stream3_MASK_Mask 0xFF77 +#define DMA_Stream3_CLR_Mask 0x0088 +#define DMA_Stream3_LAST_Mask 0xFFF7 + +#define DMA_SRCSize_Mask 0xFFE7 +#define DMA_SRCBurst_Mask 0xFF9F +#define DMA_DSTSize_Mask 0xFE7F + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/******************************************************************************* +* Function Name : DMA_DeInit +* Description : Deinitializes the DMA streamx registers to their default reset +* values. +* Input : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA +* Stream. +* Output : None +* Return : None +*******************************************************************************/ +void DMA_DeInit(DMA_Stream_TypeDef* DMA_Streamx) +{ + /* Reset streamx source base address register */ + DMA_Streamx->SOURCEL = 0; + DMA_Streamx->SOURCEH = 0; + + /* Reset streamx destination base address register */ + DMA_Streamx->DESTL = 0; + DMA_Streamx->DESTH = 0; + + /* Reset streamx maximum count register */ + DMA_Streamx->MAX = 0; + /* Reset streamx control register */ + DMA_Streamx->CTRL = 0; + /* Reset streamx last used buffer location register */ + DMA_Streamx->LUBUFF = 0; + + switch(*(u32*)&DMA_Streamx) + { + case DMA_Stream0_BASE: + /* Reset interrupt mask, clear and flag bits for stream0 */ + DMA->MASK &= DMA_Stream0_MASK_Mask; + DMA->CLR |= DMA_Stream0_CLR_Mask; + DMA->LAST &= DMA_Stream0_LAST_Mask; + break; + + case DMA_Stream1_BASE: + /* Reset interrupt mask, clear and flag bits for stream1 */ + DMA->MASK &= DMA_Stream1_MASK_Mask; + DMA->CLR |= DMA_Stream1_CLR_Mask; + DMA->LAST &= DMA_Stream1_LAST_Mask; + break; + + case DMA_Stream2_BASE: + /* Reset interrupt mask, clear and flag bits for stream2 */ + DMA->MASK &= DMA_Stream2_MASK_Mask; + DMA->CLR |= DMA_Stream2_CLR_Mask; + DMA->LAST &= DMA_Stream2_LAST_Mask; + break; + + case DMA_Stream3_BASE: + /* Reset interrupt mask, clear and flag bits for stream3 */ + DMA->MASK &= DMA_Stream3_MASK_Mask; + DMA->CLR |= DMA_Stream3_CLR_Mask; + DMA->LAST &= DMA_Stream3_LAST_Mask; + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : DMA_Init +* Description : Initializes the DMAx stream according to the specified +* parameters in the DMA_InitStruct. +* Input : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA +* Stream. +* - DMA_InitStruct: pointer to a DMA_InitTypeDef structure that +* contains the configuration information for the specified +* DMA stream. +* Output : None +* Return : None +******************************************************************************/ +void DMA_Init(DMA_Stream_TypeDef* DMA_Streamx, DMA_InitTypeDef* DMA_InitStruct) +{ + /* set the buffer Size */ + DMA_Streamx->MAX = DMA_InitStruct->DMA_BufferSize ; + + /* Configure the incrementation of the current source Register */ + if(DMA_InitStruct->DMA_SRC == DMA_SRC_INCR) + { + /* Increment current source register */ + DMA_Streamx->CTRL |= DMA_SRC_INCR; + } + else + { + /* Current source register unchanged */ + DMA_Streamx->CTRL &= DMA_SRC_NOT_INCR; + } + + /* Configure the incrementation of the current destination Register */ + if(DMA_InitStruct->DMA_DST == DMA_DST_INCR) + { + /* Increment current source register */ + DMA_Streamx->CTRL |= DMA_DST_INCR; + } + else + { + /* Current source register unchanged */ + DMA_Streamx->CTRL &= DMA_DST_NOT_INCR; + } + + /* Clear source to DMA data width SOSIZE[1:0] bits */ + DMA_Streamx->CTRL &= DMA_SRCSize_Mask; + /* Set the source to DMA data width */ + DMA_Streamx->CTRL |= DMA_InitStruct->DMA_SRCSize; + + /* Clear the DMA peripheral burst size SOBURST[1:0] bits */ + DMA_Streamx->CTRL &= DMA_SRCBurst_Mask; + /* Set the DMA peripheral burst size */ + DMA_Streamx->CTRL |= DMA_InitStruct->DMA_SRCBurst; + + /* Clear destination to DMA dat width DESIZE[1:0] bits */ + DMA_Streamx->CTRL &= DMA_DSTSize_Mask; + /* Set the destination to DMA data width */ + DMA_Streamx->CTRL |= DMA_InitStruct->DMA_DSTSize; + + /* Configure the circular mode */ + if(DMA_InitStruct->DMA_Mode == DMA_Mode_Circular) + { + /* Set circular mode */ + DMA_Streamx->CTRL |= DMA_Mode_Circular; + } + else + { + /* Set normal mode */ + DMA_Streamx->CTRL &= DMA_Mode_Normal; + } + + /* Configure the direction transfer */ + if(DMA_InitStruct->DMA_DIR == DMA_DIR_PeriphDST) + { + /* Set peripheral as destination */ + DMA_Streamx->CTRL |= DMA_DIR_PeriphDST; + } + else + { + /* Set peripheral as source */ + DMA_Streamx->CTRL &= DMA_DIR_PeriphSRC; + } + + /* Configure the memory to memory transfer only for stream3 */ + if(DMA_Streamx == DMA_Stream3) + { + if(DMA_InitStruct->DMA_M2M == DMA_M2M_Enable) + { + /* Enable memory to memory transfer for stream3 */ + DMA_Streamx->CTRL |= DMA_M2M_Enable; + } + else + { + /* Disable memory to memory transfer for stream3 */ + DMA_Streamx->CTRL &= DMA_M2M_Disable; + } + } + + /* Configure the source base address */ + DMA_Streamx->SOURCEL = DMA_InitStruct->DMA_SRCBaseAddr; + DMA_Streamx->SOURCEH = DMA_InitStruct->DMA_SRCBaseAddr >> 16; + + /* Configure the destination base address */ + DMA_Streamx->DESTL = DMA_InitStruct->DMA_DSTBaseAddr; + DMA_Streamx->DESTH = DMA_InitStruct->DMA_DSTBaseAddr >> 16; +} + +/******************************************************************************* +* Function Name : DMA_StructInit +* Description : Fills each DMA_InitStruct member with its default value. +* Input : DMA_InitStruct : pointer to a DMA_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) +{ + /* Initialize the DMA_BufferSize member */ + DMA_InitStruct->DMA_BufferSize = 0; + + /* initialize the DMA_SRCBaseAddr member */ + DMA_InitStruct->DMA_SRCBaseAddr = 0; + + /* Initialize the DMA_DSTBaseAddr member */ + DMA_InitStruct ->DMA_DSTBaseAddr = 0; + + /* Initialize the DMA_SRC member */ + DMA_InitStruct->DMA_SRC = DMA_SRC_NOT_INCR; + + /* Initialize the DMA_DST member */ + DMA_InitStruct->DMA_DST = DMA_DST_NOT_INCR; + + /* Initialize the DMA_SRCSize member */ + DMA_InitStruct->DMA_SRCSize = DMA_SRCSize_Byte; + + /* Initialize the DMA_SRCBurst member */ + DMA_InitStruct->DMA_SRCBurst = DMA_SRCBurst_1Data; + + /* Initialize the DMA_DSTSize member */ + DMA_InitStruct->DMA_DSTSize = DMA_DSTSize_Byte; + + /* Initialize the DMA_Mode member */ + DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; + + /* Initialize the DMA_M2M member */ + DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; + + /* Initialize the DMA_DIR member */ + DMA_InitStruct->DMA_DIR = DMA_DIR_PeriphSRC; +} + +/******************************************************************************* +* Function Name : DMA_Cmd +* Description : Enables or disables the specified DMA stream. +* Input : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA +* Stream. +* - NewState: new state of the DMAx stream. This parameter can +* be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void DMA_Cmd(DMA_Stream_TypeDef* DMA_Streamx, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable the selected DMA streamx */ + DMA_Streamx->CTRL |= DMA_Enable; + } + else + { + /* Disable the selected DMA streamx */ + DMA_Streamx->CTRL &= DMA_Disable; + } +} + +/******************************************************************************* +* Function Name : DMA_ITConfig +* Description : Enables or disables the specified DMA interrupts. +* Input : - DMA_IT: specifies the DMA interrupts sources to be enabled +* or disabled. This parameter can be any combination of the +* following values: +* - DMA_IT_SI0: Stream0 transfer end interrupt mask +* - DMA_IT_SI1: Stream1 transfer end interrupt mask +* - DMA_IT_SI2: Stream2 transfer end interrupt mask +* - DMA_IT_SI3: Stream3 transfer end interrupt mask +* - DMA_IT_SE0: Stream0 transfer error interrupt mask +* - DMA_IT_SE1: Stream1 transfer error interrupt mask +* - DMA_IT_SE2: Stream2 transfer error interrupt mask +* - DMA_IT_SE3: Stream3 transfer error interrupt mask +* - DMA_IT_ALL: ALL DMA interrupts mask +* - NewState: new state of the specified DMA interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void DMA_ITConfig(u16 DMA_IT, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable the selected DMA interrupts */ + DMA->MASK |= DMA_IT; + } + else + { + /* Disable the selected DMA interrupts */ + DMA->MASK &= ~DMA_IT; + } +} + +/******************************************************************************* +* Function Name : DMA_GetCurrDSTAddr +* Description : Returns the current value of the destination address pointer +* related to the specified DMA stream. +* Input : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA +* Stream. +* Output : None +* Return : The current value of the destination address pointer related +* to the specified DMA stream. +*******************************************************************************/ +u32 DMA_GetCurrDSTAddr(DMA_Stream_TypeDef* DMA_Streamx) +{ + u32 Tmp = 0; + + /* Get high current destination address */ + Tmp = (DMA_Streamx->DECURRH)<<16; + /* Get low current destination address */ + Tmp |= DMA_Streamx->DECURRL; + + /* Return the current destination address value for streamx */ + return Tmp; +} + +/******************************************************************************* +* Function Name : DMA_GetCurrSRCAddr +* Description : Returns the current value of the source address pointer +* related to the specified DMA stream. +* Input : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA +* Stream. +* Output : None +* Return : The current value of the source address pointer related to +* the specified DMA stream. +*******************************************************************************/ +u32 DMA_GetCurrSRCAddr(DMA_Stream_TypeDef* DMA_Streamx) +{ + u32 Tmp = 0; + + /* Get high current source address */ + Tmp = (DMA_Streamx->SOCURRH)<<16; + /* Get slow current source address */ + Tmp |= DMA_Streamx->SOCURRL; + + /* Return the current source address value for streamx */ + return Tmp; +} + +/******************************************************************************* +* Function Name : DMA_GetTerminalCounter +* Description : Returns the number of data units remaining in the current +* DMA stream transfer. +* Input : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA +* Stream. +* Output : None +* Return : The number of data units remaining in the current DMA stream +* transfer. +*******************************************************************************/ +u16 DMA_GetTerminalCounter(DMA_Stream_TypeDef* DMA_Streamx) +{ + /* Return the terminal counter value for streamx */ + return(DMA_Streamx->TCNT); +} + +/******************************************************************************* +* Function Name : DMA_LastBufferSweepConfig +* Description : Activates or disactivates the last buffer sweep mode for the +* DMA streamx configured in circular buffer mode. +* Input : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA +* Stream. +* - NewState: new state of the Last buffer sweep DMA_Streamx. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void DMA_LastBufferSweepConfig(DMA_Stream_TypeDef* DMA_Streamx, FunctionalState NewState) +{ + switch(*(u32*)&DMA_Streamx) + { + case DMA_Stream0_BASE: + if(NewState == ENABLE) + { + /* Activates the last circular buffer sweep mode for stream0 */ + DMA->LAST |= DMA_Last0_Enable_Mask; + } + else + { + /* Disactivates the last circular buffer sweep mode for stream0 */ + DMA->LAST &= DMA_Last0_Disable_Mask; + } + break; + + case DMA_Stream1_BASE: + if(NewState == ENABLE) + { + /* Activates the last circular buffer sweep mode for stream1 */ + DMA->LAST |= DMA_Last1_Enable_Mask; + } + else + { + /* Disactivates the last circular buffer sweep mode for stream1 */ + DMA->LAST &= DMA_Last1_Disable_Mask; + } + break; + + case DMA_Stream2_BASE: + if(NewState == ENABLE) + { + /* Activates the last circular buffer sweep mode for stream2 */ + DMA->LAST |= DMA_Last2_Enable_Mask; + } + else + { + /* Disactivates the last circular buffer sweep mode for stream2 */ + DMA->LAST &= DMA_Last2_Disable_Mask; + } + break; + + case DMA_Stream3_BASE: + if(NewState == ENABLE) + { + /* Activates the last circular buffer sweep mode for stream3 */ + DMA->LAST |= DMA_Last3_Enable_Mask; + } + else + { + /* Disactivates the last circular buffer sweep mode for stream3 */ + DMA->LAST &= DMA_Last3_Disable_Mask; + } + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : DMA_LastBufferAddrConfig +* Description : Configures the circular buffer position where the last data +* to be used by the specified DMA stream is located. +* Input : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA +* Stream. +* - DMA_LastBufferAddr: specifies the circular buffer position +* where the last data to be used by the specified DMA stream +* is located. +* This member must be a number between 0 and the stream BufferSize-1. +* Output : None +* Return : None +*******************************************************************************/ +void DMA_LastBufferAddrConfig(DMA_Stream_TypeDef* DMA_Streamx, u16 DMA_LastBufferAddr) +{ + /* Set the streamx last data circular buffer location */ + DMA_Streamx->LUBUFF = DMA_LastBufferAddr; +} + +/******************************************************************************* +* Function Name : DMA_GetFlagStatus +* Description : Checks whether the specified DMA flag is set or not. +* Input : - DMA_FLAG: specifies the flag to check. This parameter can +* be one of the following values: +* - DMA_FLAG_SI0: Stream0 transfer end flag. +* - DMA_FLAG_SI1: Stream1 transfer end flag. +* - DMA_FLAG_SI2: Stream2 transfer end flag. +* - DMA_FLAG_SI3: Stream3 transfer end flag. +* - DMA_FLAG_SE0: Stream0 transfer error flag. +* - DMA_FLAG_SE1: Stream1 transfer error flag. +* - DMA_FLAG_SE2: Stream2 transfer error flag. +* - DMA_FLAG_SE3: Stream3 transfer error flag. +* - DMA_FLAG_ACT0: Stream0 status. +* - DMA_FLAG_ACT1: Stream1 status. +* - DMA_FLAG_ACT2: Stream2 status. +* - DMA_FLAG_ACT3: Stream3 status. +* Output : None +* Return : The new state of DMA_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus DMA_GetFlagStatus(u16 DMA_FLAG) +{ + /* Check the status of the specified DMA flag */ + if((DMA->STATUS & DMA_FLAG) != RESET) + { + /* Return SET if DMA_FLAG is set */ + return SET; + } + else + { + /* Return RESET if DMA_FLAG is reset */ + return RESET; + } +} + +/******************************************************************************* +* Function Name : DMA_ClearFlag +* Description : Clears the DMA’s pending flags. +* Input : - DMA_FLAG: specifies the flag to clear. This parameter can +* be any combination of the following values: +* - DMA_FLAG_SI0: Stream0 transfer end flag. +* - DMA_FLAG_SI1: Stream1 transfer end flag. +* - DMA_FLAG_SI2: Stream2 transfer end flag. +* - DMA_FLAG_SI3: Stream3 transfer end flag. +* - DMA_FLAG_SE0: Stream0 transfer error flag. +* - DMA_FLAG_SE1: Stream1 transfer error flag. +* - DMA_FLAG_SE2: Stream2 transfer error flag. +* - DMA_FLAG_SE3: Stream3 transfer error flag. +* Output : None +* Return : None +*******************************************************************************/ +void DMA_ClearFlag(u16 DMA_FLAG) +{ + /* Clear the selected DMA flags */ + DMA->CLR = DMA_FLAG ; +} + +/******************************************************************************* +* Function Name : DMA_GetITStatus +* Description : Checks whether the specified DMA interrupt has occured or not. +* Input : - DMA_IT: specifies the DMA interrupt source to check. +* This parameter can be one of the following values: +* - DMA_IT_SI0: Stream0 transfer end interrupt +* - DMA_IT_SI1: Stream1 transfer end interrupt +* - DMA_IT_SI2: Stream2 transfer end interrupt +* - DMA_IT_SI3: Stream3 transfer end interrupt +* - DMA_IT_SE0: Stream0 transfer error interrupt +* - DMA_IT_SE1: Stream1 transfer error interrupt +* - DMA_IT_SE2: Stream2 transfer error interrupt +* - DMA_IT_SE3: Stream3 transfer error interrupt +* Output : None +* Return : The new state of DMA_IT (SET or RESET). +*******************************************************************************/ +ITStatus DMA_GetITStatus(u16 DMA_IT) +{ + /* Check the status of the specified DMA interrupt */ + if((DMA->STATUS & DMA_IT) != RESET) + { + /* Return SET if the DMA interrupt flag is set */ + return SET; + } + else + { + /* Return RESET if the DMA interrupt flag is reset */ + return RESET; + } +} + +/******************************************************************************* +* Function Name : DMA_ClearITPendingBit +* Description : Clears the DMA’s interrupt pending bits. +* Input : - DMA_IT: specifies the interrupt pending bit to clear. +* This parameter can be any combination of the following values: +* - DMA_IT_SI0: Stream0 transfer end interrupt. +* - DMA_IT_SI1: Stream1 transfer end interrupt. +* - DMA_IT_SI2: Stream2 transfer end interrupt. +* - DMA_IT_SI3: Stream3 transfer end interrupt. +* - DMA_IT_SE0: Stream0 transfer error interrupt. +* - DMA_IT_SE1: Stream1 transfer error interrupt. +* - DMA_IT_SE2: Stream2 transfer error interrupt. +* - DMA_IT_SE3: Stream3 transfer error interrupt. +* - DMA_IT_ALL: All DMA interrupts. +* Output : None +* Return : None +*******************************************************************************/ +void DMA_ClearITPendingBit(u16 DMA_IT) +{ + /* Clear the selected DMA interrupts pending bits */ + DMA->CLR = DMA_IT ; +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_eic.c b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_eic.c new file mode 100644 index 000000000..ca9ead80f --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_eic.c @@ -0,0 +1,258 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_eic.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the EIC software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_eic.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define EIC_IRQEnable_Mask 0x00000001 +#define EIC_IRQDisable_Mask 0xFFFFFFFE + +#define EIC_FIQEnable_Mask 0x00000002 +#define EIC_FIQDisable_Mask 0xFFFFFFFD + +#define EIC_SIPL_Mask 0x0000000F +#define EIC_SIPL_Reset_Mask 0xFFFFFFF0 + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : EIC_DeInit +* Description : Deinitializes the EIC peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void EIC_DeInit(void) +{ + EIC->ICR = 0x00; + EIC->CIPR = 0x00; + EIC->FIR = 0x0C; + EIC->IER = 0x00; + EIC->IPR = 0xFFFFFFFF; +} + +/******************************************************************************* +* Function Name : EIC_IRQInit +* Description : Configures the IRQ channels according to the specified +* parameters in the EIC_IRQInitStruct. +* Input : EIC_IRQInitStruct: pointer to a EIC_IRQInitTypeDef structure. +* Output : None +* Return : None +*******************************************************************************/ +void EIC_IRQInit(EIC_IRQInitTypeDef* EIC_IRQInitStruct) +{ + u32 Tmp = 0; + + if(EIC_IRQInitStruct->EIC_IRQChannelCmd == ENABLE) + { + /* Enable the selected IRQ channel */ + EIC->IER |= 1 << EIC_IRQInitStruct->EIC_IRQChannel; + + /* Configure the selected IRQ channel priority ***************************/ + /* Clear SIPL[3:0] bits */ + EIC->SIRn[EIC_IRQInitStruct->EIC_IRQChannel] &= EIC_SIPL_Reset_Mask; + + /* Configure SIPL[3:0] bits according to EIC_IRQChannelPriority parameter */ + Tmp = EIC_IRQInitStruct->EIC_IRQChannelPriority & EIC_SIPL_Mask; + EIC->SIRn[EIC_IRQInitStruct->EIC_IRQChannel] |= Tmp; + } + else + { + /* Disable the select IRQ channel */ + EIC->IER &=~ (1 << EIC_IRQInitStruct->EIC_IRQChannel); + } +} + +/******************************************************************************* +* Function Name : EIC_FIQInit +* Description : Configures the FIQ channels according to the specified +* parameters in the EIC_FIQInitStruct. +* Input : EIC_FIQInitStruct: pointer to a EIC_FIQInitTypeDef structure. +* Output : None +* Return : None +*******************************************************************************/ +void EIC_FIQInit(EIC_FIQInitTypeDef* EIC_FIQInitStruct) +{ + if(EIC_FIQInitStruct->EIC_FIQChannelCmd == ENABLE) + { + /* Enable the selected FIQ channel */ + EIC->FIER |= EIC_FIQInitStruct->EIC_FIQChannel ; + } + else + { + /* Disable the selected FIQ channel */ + EIC->FIER &= ~EIC_FIQInitStruct->EIC_FIQChannel; + } +} + +/******************************************************************************* +* Function Name : EIC_IRQStructInit +* Description : Fills each EIC_IRQInitStruct member with its default value. +* Input : EIC_IRQInitStruct: pointer to a EIC_IRQInitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void EIC_IRQStructInit(EIC_IRQInitTypeDef* EIC_IRQInitStruct) +{ + EIC_IRQInitStruct->EIC_IRQChannel = 0x1F; + EIC_IRQInitStruct->EIC_IRQChannelPriority = 0; + EIC_IRQInitStruct->EIC_IRQChannelCmd = DISABLE; +} + +/******************************************************************************* +* Function Name : EIC_FIQStructInit +* Description : Fills each EIC_FIQInitStruct member with its default value. +* Input : EIC_FIQInitStruct: pointer to a EIC_FIQInitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void EIC_FIQStructInit(EIC_FIQInitTypeDef* EIC_FIQInitStruct) +{ + EIC_FIQInitStruct->EIC_FIQChannel = 0x03; + EIC_FIQInitStruct->EIC_FIQChannelCmd = DISABLE; +} + +/******************************************************************************* +* Function Name : EIC_IRQCmd +* Description : Enables or disables EIC IRQ output request to CPU. +* Input : NewState: new state of the EIC IRQ output request to CPU. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void EIC_IRQCmd(FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable EIC IRQ output request to CPU */ + EIC->ICR |= EIC_IRQEnable_Mask; + } + else + { + /* Disable EIC IRQ output request to CPU */ + EIC->ICR &= EIC_IRQDisable_Mask; + } +} + +/******************************************************************************* +* Function Name : EIC_FIQCmd +* Description : Enables or disables EIC FIQ output request to CPU. +* Input : NewState: new state of the EIC FIQ output request to CPU. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void EIC_FIQCmd(FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable EIC FIQ output request to CPU */ + EIC->ICR |= EIC_FIQEnable_Mask; + } + else + { + /* Disable EIC FIQ output request to CPU */ + EIC->ICR &= EIC_FIQDisable_Mask; + } +} + +/******************************************************************************* +* Function Name : EIC_GetCurrentIRQChannel +* Description : Returns the current served IRQ channel identifier. +* Input : None +* Output : None +* Return : The current served IRQ channel. +*******************************************************************************/ +u8 EIC_GetCurrentIRQChannel(void) +{ + /* Read and return the CIC[4:0] bits of CICR register */ + return ((u8) (EIC->CICR)); +} + +/******************************************************************************* +* Function Name : EIC_GetCurrentIRQChannelPriority +* Description : Returns the priority level of the current served IRQ channel. +* Input : None +* Output : None +* Return : The priority level of the current served IRQ channel. +*******************************************************************************/ +u8 EIC_GetCurrentIRQChannelPriority(void) +{ + /* Read and return the CIP[3:0] bits of CIPR register */ + return ((u8) (EIC->CIPR)); +} + +/******************************************************************************* +* Function Name : EIC_CurrentIRQPriorityConfig +* Description : Changes the priority of the current served IRQ channel. +* The new priority value must be higher, or equal, than the +* priority value associated to the interrupt channel currently +* serviced. +* Input : NewPriority: new priority value of the IRQ interrupt routine +* currently serviced. +* Output : None +* Return : None +*******************************************************************************/ +void EIC_CurrentIRQPriorityConfig(u8 NewPriority) +{ + /* Disable EIC IRQ output request to CPU */ + EIC->ICR &= EIC_IRQDisable_Mask; + + /* Change the current priority */ + EIC->CIPR = NewPriority; + + /* Enable EIC IRQ output request to CPU */ + EIC->ICR |= EIC_IRQEnable_Mask; +} + +/******************************************************************************* +* Function Name : EIC_GetCurrentFIQChannel +* Description : Returns the current served FIQ channel identifier. +* Input : None +* Output : None +* Return : The current served FIQ channel. +*******************************************************************************/ +u8 EIC_GetCurrentFIQChannel(void) +{ + /* Read and return the FIP[1:0] bits of FIPR register */ + return ((u8) (EIC->FIPR)); +} + +/******************************************************************************* +* Function Name : EIC_ClearFIQPendingBit +* Description : Clears the pending bit of the selected FIQ Channel. +* Input : EIC_FIQChannel: specifies the FIQ channel to clear its +* pending bit. +* Output : None +* Return : None +*******************************************************************************/ +void EIC_ClearFIQPendingBit(u8 EIC_FIQChannel) +{ + /* Clear the correspondent FIQ pending bit */ + EIC->FIPR = EIC_FIQChannel ; +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_extit.c b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_extit.c new file mode 100644 index 000000000..997cb24f2 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_extit.c @@ -0,0 +1,179 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_extit.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the EXTIT software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_extit.h" +#include "75x_mrcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : EXTIT_DeInit +* Description : Deinitializes the EXTIT peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void EXTIT_DeInit(void) +{ + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_EXTIT,ENABLE); + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_EXTIT,DISABLE); +} + +/******************************************************************************* +* Function Name : EXTIT_Init +* Description : Initializes the EXTIT peripheral according to the specified +* parameters in the EXTIT_InitStruct . +* Input : - EXTIT_InitStruct: pointer to a EXTIT_InitTypeDef structure +* that contains the configuration information for the EXTIT +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void EXTIT_Init(EXTIT_InitTypeDef* EXTIT_InitStruct) +{ + if(EXTIT_InitStruct->EXTIT_ITLineCmd == ENABLE) + { + /* Enable the selected external interrupts */ + EXTIT->MR |= EXTIT_InitStruct->EXTIT_ITLine; + + /* Select the trigger for the selected external interrupts */ + if(EXTIT_InitStruct->EXTIT_ITTrigger == EXTIT_ITTrigger_Falling) + { + /* Falling edge */ + EXTIT->TSR &= ~EXTIT_InitStruct->EXTIT_ITLine; + } + else if (EXTIT_InitStruct->EXTIT_ITTrigger == EXTIT_ITTrigger_Rising) + { + /* Rising edge */ + EXTIT->TSR |= EXTIT_InitStruct->EXTIT_ITLine; + } + } + else if(EXTIT_InitStruct->EXTIT_ITLineCmd == DISABLE) + { + /* Disable the selected external interrupts */ + EXTIT->MR &= ~EXTIT_InitStruct->EXTIT_ITLine; + } +} + +/******************************************************************************* +* Function Name : EXTIT_StructInit +* Description : Fills each EXTIT_InitStruct member with its reset value. +* Input : - EXTIT_InitStruct: pointer to a EXTIT_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void EXTIT_StructInit(EXTIT_InitTypeDef* EXTIT_InitStruct) +{ + EXTIT_InitStruct->EXTIT_ITLine = EXTIT_ITLineNone; + EXTIT_InitStruct->EXTIT_ITTrigger = EXTIT_ITTrigger_Falling; + EXTIT_InitStruct->EXTIT_ITLineCmd = DISABLE; +} + +/******************************************************************************* +* Function Name : EXTIT_GenerateSWInterrupt +* Description : Generates a Software interrupt. +* Input : - EXTIT_ITLine: specifies the EXTIT lines to be enabled or +* disabled. This parameter can be: +* - EXTIT_ITLinex: External interrupt line x where x(0..15) +* Output : None +* Return : None +*******************************************************************************/ +void EXTIT_GenerateSWInterrupt(u16 EXTIT_ITLine) +{ + EXTIT->SWIR |= EXTIT_ITLine; +} + +/******************************************************************************* +* Function Name : EXTIT_GetFlagStatus +* Description : Checks whether the specified EXTIT line flag is set or not. +* Input : - EXTIT_ITLine: specifies the EXTIT lines flag to check. +* This parameter can be: +* - EXTIT_ITLinex: External interrupt line x where x(0..15) +* Output : None +* Return : The new state of EXTIT_ITLine (SET or RESET). +*******************************************************************************/ +FlagStatus EXTIT_GetFlagStatus(u16 EXTIT_ITLine) +{ + if((EXTIT->PR & EXTIT_ITLine) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : EXTIT_ClearFlag +* Description : Clears the EXTIT’s line pending flags. +* Input : - EXTIT_ITLine: specifies the EXTIT lines flags to clear. +* This parameter can be: +* - EXTIT_ITLinex: External interrupt line x where x(0..15) +* Output : None +* Return : None +*******************************************************************************/ +void EXTIT_ClearFlag(u16 EXTIT_ITLine) +{ + EXTIT->PR = EXTIT_ITLine; +} + +/******************************************************************************* +* Function Name : EXTIT_GetITStatus +* Description : Checks whether the specified EXTIT line is asserted or not. +* Input : - EXTIT_ITLine: specifies the EXTIT lines to check. +* This parameter can be: +* - EXTIT_ITLinex: External interrupt line x where x(0..15) +* Output : None +* Return : The new state of EXTIT_ITLine (SET or RESET). +*******************************************************************************/ +ITStatus EXTIT_GetITStatus(u16 EXTIT_ITLine) +{ + if(((EXTIT->PR & EXTIT_ITLine) != RESET)&& ((EXTIT->MR & EXTIT_ITLine) != RESET)) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : EXTIT_ClearITPendingBit +* Description : Clears the EXTIT’s line pending bits. +* Input : - EXTIT_ITLine: specifies the EXTIT lines to clear. +* This parameter can be: +* - EXTIT_ITLinex: External interrupt line x where x(0..15) +* Output : None +* Return : None +*******************************************************************************/ +void EXTIT_ClearITPendingBit(u16 EXTIT_ITLine) +{ + EXTIT->PR = EXTIT_ITLine; +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_gpio.c b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_gpio.c new file mode 100644 index 000000000..dcc7d7920 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_gpio.c @@ -0,0 +1,320 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_gpio.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the GPIO software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_gpio.h" +#include "75x_mrcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define GPIO_Remap_Mask 0x1F /* GPIO remapping mask */ +#define GPIO_Pin_Mask 0x000FFFFF /* GPIO1 and GPIO2 all pins mask */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : GPIO_DeInit +* Description : Deinitializes the GPIOx peripheral registers to their default +* reset values. +* The I/O remapping register 0 and 1 are not reset by this function. +* Input : GPIOx: where x can be 0,1 or 2 to select the GPIO peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_DeInit(GPIO_TypeDef* GPIOx) +{ + /* Reset the GPIOx registers values */ + GPIOx->PC0 = 0xFFFFFFFF; + GPIOx->PC1 = 0x0; + GPIOx->PC2 = 0x0; + GPIOx->PM = 0x0; +} + +/******************************************************************************* +* Function Name : GPIO_Init +* Description : Initializes the GPIOx peripheral according to the specified +* parameters in the GPIO_InitStruct. This function will not +* change the configuration for a pin if the corresponding mask +* bit is set, except pins configured as input pull-up or pull-down. +* These pins are automatically masked after each configuration. +* Input :- GPIOx: where x can be (0..2) to select the GPIO peripheral. +* - GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that +* contains the configuration information for the specified GPIO +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) +{ + /* GPIOx Mode and Pins Set */ + if((GPIOx != GPIO0) && (GPIO_InitStruct->GPIO_Pin == GPIO_Pin_All)) + { + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_Mask; + } + + switch(GPIO_InitStruct->GPIO_Mode) + { + case GPIO_Mode_AIN: + GPIOx->PC0 &= ~GPIO_InitStruct->GPIO_Pin; + GPIOx->PC1 &= ~GPIO_InitStruct->GPIO_Pin; + GPIOx->PC2 &= ~GPIO_InitStruct->GPIO_Pin; + break; + + case GPIO_Mode_IN_FLOATING: + GPIOx->PC0 |= GPIO_InitStruct->GPIO_Pin; + GPIOx->PC1 &= ~GPIO_InitStruct->GPIO_Pin; + GPIOx->PC2 &= ~GPIO_InitStruct->GPIO_Pin; + break; + + case GPIO_Mode_IPD: + GPIOx->PM &= ~GPIO_InitStruct->GPIO_Pin; + GPIOx->PC0 |= GPIO_InitStruct->GPIO_Pin; + GPIOx->PC1 |= GPIO_InitStruct->GPIO_Pin; + GPIOx->PC2 &= ~GPIO_InitStruct->GPIO_Pin; + GPIOx->PD &= ~GPIO_InitStruct->GPIO_Pin; + GPIOx->PM |= GPIO_InitStruct->GPIO_Pin; + break; + + case GPIO_Mode_IPU: + GPIOx->PM &= ~GPIO_InitStruct->GPIO_Pin; + GPIOx->PC0 |= GPIO_InitStruct->GPIO_Pin; + GPIOx->PC1 |= GPIO_InitStruct->GPIO_Pin; + GPIOx->PC2 &= ~GPIO_InitStruct->GPIO_Pin; + GPIOx->PD |= GPIO_InitStruct->GPIO_Pin; + GPIOx->PM |= GPIO_InitStruct->GPIO_Pin; + break; + + case GPIO_Mode_Out_OD: + GPIOx->PC0 &= ~GPIO_InitStruct->GPIO_Pin; + GPIOx->PC1 &= ~GPIO_InitStruct->GPIO_Pin; + GPIOx->PC2 |= GPIO_InitStruct->GPIO_Pin; + break; + + case GPIO_Mode_Out_PP: + GPIOx->PC0 |= GPIO_InitStruct->GPIO_Pin; + GPIOx->PC1 &= ~GPIO_InitStruct->GPIO_Pin; + GPIOx->PC2 |= GPIO_InitStruct->GPIO_Pin; + break; + + case GPIO_Mode_AF_OD: + GPIOx->PD |= GPIO_InitStruct->GPIO_Pin; + GPIOx->PC1 |= GPIO_InitStruct->GPIO_Pin; + GPIOx->PC0 &= ~GPIO_InitStruct->GPIO_Pin; + GPIOx->PC2 |= GPIO_InitStruct->GPIO_Pin; + break; + + case GPIO_Mode_AF_PP: + GPIOx->PC0 |= GPIO_InitStruct->GPIO_Pin; + GPIOx->PC1 |= GPIO_InitStruct->GPIO_Pin; + GPIOx->PC2 |= GPIO_InitStruct->GPIO_Pin; + break; + + default : + GPIOx->PC0 |= GPIO_InitStruct->GPIO_Pin; + GPIOx->PC1 &= ~GPIO_InitStruct->GPIO_Pin; + GPIOx->PC2 &= ~GPIO_InitStruct->GPIO_Pin; + break; + } +} + +/******************************************************************************* +* Function Name : GPIO_StructInit +* Description : Fills each GPIO_InitStruct member with its default value. +* Input : GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) +{ + /* Reset GPIO init structure parameters values */ + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; +} + +/******************************************************************************* +* Function Name : GPIO_Read +* Description : Reads the specified GPIO data port. +* Input : GPIOx: where x can be 0,1 or 2 to select the GPIO peripheral. +* Output : None +* Return : GPIO data port word value. +*******************************************************************************/ +u32 GPIO_Read(GPIO_TypeDef* GPIOx) +{ + return GPIOx->PD; +} + +/******************************************************************************* +* Function Name : GPIO_ReadBit +* Description : Reads the specified data port bit. +* Input : - GPIOx: where x can be (0..2) to select the GPIO peripheral. +* : - GPIO_Pin: specifies the port bit to read. +* This parameter can be GPIO_Pin_x where x can be (0..31) for +* GPIO0 and x(0..19) for GPIO1 and GPIO2. +* Output : None +* Return : The port pin value +*******************************************************************************/ +u8 GPIO_ReadBit(GPIO_TypeDef* GPIOx, u32 GPIO_Pin) +{ + if ((GPIOx->PD & GPIO_Pin) != Bit_RESET) + { + return Bit_SET; + } + else + { + return Bit_RESET; + } +} + +/******************************************************************************* +* Function Name : GPIO_Write +* Description : Writes data to the specified GPIO data port. +* Input :- GPIOx: where x can be 0,1 or 2 to select the GPIO peripheral. +* - PortVal: specifies the value to be written to the data port +* register. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_Write(GPIO_TypeDef* GPIOx, u32 PortVal) +{ + GPIOx->PD = PortVal; +} + +/******************************************************************************* +* Function Name : GPIO_WriteBit +* Description : Sets or clears the selected data port bit. +* Input : - GPIOx: where x can be (0..2) to select the GPIO peripheral. +* - GPIO_Pin: specifies the port bit to be written. +* This parameter can be GPIO_Pin_x where x can be (0..31) for +* GPIO0 and x(0..19) for GPIO1 and GPIO2. +* - BitVal: specifies the value to be written to the selected bit. +* This parameter must be one of the BitAction enum values: +* - Bit_RESET: to clear the port pin +* - Bit_SET: to set the port pin +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u32 GPIO_Pin, BitAction BitVal) +{ + if(BitVal != Bit_RESET) + { + GPIOx->PD |= GPIO_Pin; + } + else + { + GPIOx->PD &= ~GPIO_Pin; + } +} + +/******************************************************************************* +* Function Name : GPIO_PinMaskConfig +* Description : Enables or disables write protection to the selected bits in +* the I/O port registers (PxC2, PxC1, PxC0 and PxD). +* Input :- GPIOx: where x can be 0,1 or 2 to select the GPIO peripheral. +* - GPIO_Pin: specifies the port bit to be protected. +* This parameter can be GPIO_Pin_x where x can be (0..31) for +* GPIO0 and x(0..19) for GPIO1 and GPIO2. +* - NewState: new state of the port pin. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_PinMaskConfig(GPIO_TypeDef* GPIOx, u32 GPIO_Pin, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + GPIOx->PM |= GPIO_Pin; + } + else + { + GPIOx->PM &= ~GPIO_Pin; + } +} + +/******************************************************************************* +* Function Name : GPIO_GetPortMask +* Description : Gets the GPIOx port mask value. +* Input : GPIOx: where x can be 0,1 or 2 to select the GPIO peripheral. +* Output : None +* Return : GPIO port mask value. +*******************************************************************************/ +u32 GPIO_GetPortMask(GPIO_TypeDef* GPIOx) +{ + return GPIOx->PM; +} + +/******************************************************************************* +* Function Name : GPIO_PinRemapConfig +* Description : Changes the mapping of the specified pin. +* Input :- GPIO_Remap: selects the pin to remap. +* This parameter can be one of the following values: +* - GPIO_Remap_SMI_CS3_EN: Enable SMI CS3 +* - GPIO_Remap_SMI_CS2_EN: Enable SMI CS2 +* - GPIO_Remap_SMI_CS1_EN: Enable SMI CS1 +* - GPIO_Remap_SMI_EN: Enable SMI Alternate Functions: +* SMI_CS0, SMI_CK, SMI_DIN and SMI_DOUT +* - GPIO_Remap_DBGOFF: JTAG Disable +* - GPIO_Remap_UART1: UART1 Alternate Function mapping +* - GPIO_Remap_UART2: UART2 Alternate Function mapping +* - GPIO_Remap_SSP1: SSP1 Alternate Function mapping +* - GPIO_Remap_TIM2: TIM2 Alternate Function mapping +* - GPIO_Remap_TIM0: TIM0 Alternate Function mapping +* - NewState: new state of the port pin. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_PinRemapConfig(u16 GPIO_Remap, FunctionalState NewState) +{ + u32 GPIOReg = 0; + u32 PinPos = 0; + + /* Get the GPIO register index */ + GPIOReg = GPIO_Remap >> 5; + + /* Get the pin position */ + PinPos = GPIO_Remap & GPIO_Remap_Mask; + + if(GPIOReg == 1) /* The pin to remap is in REMAP0R register */ + { + if(NewState == ENABLE) + { + GPIOREMAP->REMAP0R |= (1 << PinPos); + } + else + { + GPIOREMAP->REMAP0R &= ~(1 << PinPos); + } + } + else if(GPIOReg == 2) /* The pin to remap is in REMAP1R register */ + { + if(NewState == ENABLE) + { + GPIOREMAP->REMAP1R |= (1 << PinPos); + } + else + { + GPIOREMAP->REMAP1R &= ~(1 << PinPos); + } + } +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_i2c.c b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_i2c.c new file mode 100644 index 000000000..e5e5d001c --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_i2c.c @@ -0,0 +1,568 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_i2c.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the I2C software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_i2c.h" +#include "75x_mrcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* I2C IT enable */ +#define I2C_IT_Enable 0x01 +#define I2C_IT_Disable 0xFE + +/* I2C Peripheral Enable/Disable */ +#define I2C_PE_Set 0x20 +#define I2C_PE_Reset 0xDF + +/* I2C START Enable/Disable */ +#define I2C_Start_Enable 0x08 +#define I2C_Start_Disable 0xF7 + +/* I2C STOP Enable/Disable */ +#define I2C_Stop_Enable 0x02 +#define I2C_Stop_Disable 0xFD + +/* Address direction bit */ +#define I2C_ADD0_Set 0x01 +#define I2C_ADD0_Reset 0xFE + +/* I2C Masks */ +#define I2C_Frequency_Mask 0x1F +#define I2C_AddressHigh_Mask 0xF9 +#define I2C_OwnAddress_Mask 0x0300 +#define I2C_StandardMode_Mask 0x7f +#define I2C_FastMode_Mask 0x80 +#define I2C_Event_Mask 0x3FFF + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : I2C_DeInit +* Description : Deinitializes the I2C peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void I2C_DeInit(void) +{ + /* Reset the I2C registers values*/ + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_I2C,ENABLE); + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_I2C,DISABLE); +} + +/******************************************************************************* +* Function Name : I2C_Init +* Description : Initializes the I2C peripheral according to the specified +* parameters in the I2C_Initstruct. +* Input : - I2C_InitStruct: pointer to a I2C_InitTypeDef structure that +* contains the configuration information for the specified I2C +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void I2C_Init(I2C_InitTypeDef* I2C_InitStruct) +{ + u8 ITEState = 0; + u16 Result = 0x0F; + u32 APBClock = 8000000; + MRCC_ClocksTypeDef MRCC_ClocksStatus; + + /* Get APBClock frequency value */ + MRCC_GetClocksStatus(&MRCC_ClocksStatus); + APBClock = MRCC_ClocksStatus.PCLK_Frequency; + /* Save ITE bit state */ + ITEState = I2C->CR & 0xFE; + /* Disable I2C peripheral to set FR[2:0] bits */ + I2C_Cmd(DISABLE); + /* Clear frequency FR[2:0] bits */ + I2C->OAR2 &= I2C_Frequency_Mask; + + /* Set frequency bits depending on APBClock value */ + if (APBClock < 10000000) + I2C->OAR2 &= 0x1F; + else if (APBClock < 16670000) + I2C->OAR2 |= 0x20; + else if (APBClock < 26670000) + I2C->OAR2 |= 0x40; + else if (APBClock < 40000000) + I2C->OAR2 |= 0x60; + else if (APBClock < 53330000) + I2C->OAR2 |= 0x80; + else if (APBClock < 66000000) + I2C->OAR2 |= 0xA0; + else if (APBClock < 80000000) + I2C->OAR2 |= 0xC0; + else if (APBClock < 100000000) + I2C->OAR2 |= 0xE0; + I2C_Cmd(ENABLE); + + /* Restore the ITE bit state */ + I2C->CR |= ITEState; + + /* Configure general call */ + if (I2C_InitStruct->I2C_GeneralCall == I2C_GeneralCall_Enable) + { + /* Enable general call */ + I2C->CR |= I2C_GeneralCall_Enable; + } + else + { + /* Disable general call */ + I2C->CR &= I2C_GeneralCall_Disable; + } + + /* Configure acknowledgement */ + if (I2C_InitStruct->I2C_Ack == I2C_Ack_Enable) + { + /* Enable acknowledgement */ + I2C->CR |= I2C_Ack_Enable; + } + else + { + /* Disable acknowledgement */ + I2C->CR &= I2C_Ack_Disable; + } + + /* Configure LSB own address */ + I2C->OAR1 = I2C_InitStruct->I2C_OwnAddress; + /* Clear MSB own address ADD[9:8] bits */ + I2C->OAR2 &= I2C_AddressHigh_Mask; + /* Set MSB own address value */ + I2C->OAR2 |= (I2C_InitStruct->I2C_OwnAddress & I2C_OwnAddress_Mask)>>7; + + /* Configure speed in standard mode */ + if (I2C_InitStruct->I2C_CLKSpeed <= 100000) + { + /* Standard mode speed calculate */ + Result = ((APBClock/I2C_InitStruct->I2C_CLKSpeed)-7)/2; + /* Set speed value and clear FM/SM bit for standard mode in LSB clock divider */ + I2C->CCR = Result & I2C_StandardMode_Mask; + } + /* Configure speed in fast mode */ + else if (I2C_InitStruct->I2C_CLKSpeed <= 400000) + { + /* Fast mode speed calculate */ + Result = ((APBClock/I2C_InitStruct->I2C_CLKSpeed)-9)/3; + /* Set speed value and set FM/SM bit for fast mode in LSB clock divider */ + I2C->CCR = Result | I2C_FastMode_Mask; + } + /* Set speed in MSB clock divider */ + I2C->ECCR = Result >>7; +} + +/******************************************************************************* +* Function Name : I2C_StructInit +* Description : Fills each I2C_InitStruct member with its default value. +* Input : - I2C_InitStruct: pointer to an I2C_InitTypeDef structure + which will be initialized. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct) +{ + /* Initialize the I2C_CLKSpeed member */ + I2C_InitStruct->I2C_CLKSpeed = 5000; + + /* Initialize the I2C_OwnAddress member */ + I2C_InitStruct->I2C_OwnAddress = 0x0; + + /* Initialize the I2C_GeneralCall member */ + I2C_InitStruct->I2C_GeneralCall = I2C_GeneralCall_Disable; + + /* Initialize the I2C_Ack member */ + I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; +} + +/******************************************************************************* +* Function Name : I2C_Cmd +* Description : Enables or disables the I2C peripheral. +* Input : - NewState: new state of the I2C peripheral. This parameter +* can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_Cmd(FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Enable the I2C peripheral by setting twice the PE bit on the CR register */ + I2C->CR |= I2C_PE_Set; + I2C->CR |= I2C_PE_Set; + } + else + { + /* Disable the I2C peripheral */ + I2C->CR &= I2C_PE_Reset; + } +} + +/******************************************************************************* +* Function Name : I2C_GenerateSTART +* Description : Generates I2C communication START condition. +* Input : - NewState: new state of the I2C START condition generation. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_GenerateSTART(FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Generate a START condition */ + I2C->CR |= I2C_Start_Enable; + } + else + { + /* Disable the START condition generation */ + I2C->CR &= I2C_Start_Disable; + } +} + +/******************************************************************************* +* Function Name : I2C_GenerateSTOP +* Description : Generates I2C communication STOP condition. +* Input : - NewState: new state of the I2C STOP condition generation. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_GenerateSTOP(FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Generate a SIOP condition */ + I2C->CR |= I2C_Stop_Enable; + } + else + { + /* Disable the STOP condition generation */ + I2C->CR &= I2C_Stop_Disable; + } +} + +/******************************************************************************* +* Function Name : I2C_AcknowledgeConfig +* Description : Enables or disables I2C acknowledge feature. +* Input : - NewState: new state of the I2C Acknowledgement. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_AcknowledgeConfig(FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Enable the acknowledgement */ + I2C->CR |= I2C_Ack_Enable; + } + else + { + /* Disable the acknowledgement */ + I2C->CR &= I2C_Ack_Disable; + } +} + +/******************************************************************************* +* Function Name : I2C_ITConfig +* Description : Enables or disables the I2C interrupt. +* Input : - NewState: new state of the I2C interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_ITConfig(FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Enable the I2C interrupt */ + I2C->CR |= I2C_IT_Enable; + } + else + { + /* Disable the I2C interrupt */ + I2C->CR &= I2C_IT_Disable; + } +} + +/******************************************************************************* +* Function Name : I2C_GetLastEvent +* Description : Gets the last I2C event that has occurred. +* Input : None +* Output : None +* Return : The Last happened Event. +*******************************************************************************/ +u16 I2C_GetLastEvent(void) +{ + u16 Flag1 = 0, Flag2 = 0, LastEvent = 0; + + Flag1 = I2C->SR1; + Flag2 = I2C->SR2; + Flag2 = Flag2<<8; + /* Get the last event value from I2C status register */ + LastEvent = (((Flag1 | (Flag2)) & I2C_Event_Mask)); + /* Return the last event */ + return LastEvent; +} + +/******************************************************************************* +* Function Name : I2C_CheckEvent +* Description : Checks whether the Last I2C Event is equal to the one passed +* as parameter. +* Input : - I2C_EVENT: specifies the event to be checked. This parameter +* can be one of the following values: +* - I2C_EVENT_SLAVE_ADDRESS_MATCHED +* - I2C_EVENT_SLAVE_BYTE_RECEIVED +* - I2C_EVENT_SLAVE_BYTE_TRANSMITTED +* - I2C_EVENT_SLAVE_ACK_FAILURE +* - I2C_EVENT_MASTER_MODE_SELECT +* - I2C_EVENT_MASTER_MODE_SELECTED +* - I2C_EVENT_MASTER_BYTE_RECEIVED +* - I2C_EVENT_MASTER_BYTE_TRANSMITTED +* - I2C_EVENT_MASTER_MODE_ADDRESS10 +* - I2C_EVENT_SLAVE_STOP_DETECTED +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Last event is equal to the I2C_Event +* - ERROR: Last event is different from the I2C_Event +*******************************************************************************/ +ErrorStatus I2C_CheckEvent(u16 I2C_EVENT) +{ + u16 LastEvent = I2C_GetLastEvent(); + + /* Check whether the last event is equal to I2C_EVENT */ + if (LastEvent == I2C_EVENT) + { + /* Return SUCCESS when last event is equal to I2C_EVENT */ + return SUCCESS; + } + else + { + /* Return ERROR when last event is different from I2C_EVENT */ + return ERROR; + } +} + +/******************************************************************************* +* Function Name : I2C_SendData +* Description : Sends a data byte. +* Input : - Data: indicates the byte to be transmitted. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_SendData(u8 Data) +{ + /* Write in the DR register the byte to be sent */ + I2C->DR = Data; +} + +/******************************************************************************* +* Function Name : I2C_ReceiveData +* Description : Reads the received byte. +* Input : None +* Output : None +* Return : The received byte +*******************************************************************************/ +u8 I2C_ReceiveData(void) +{ + /* Return from the DR register the received byte */ + return I2C->DR; +} + +/******************************************************************************* +* Function Name : I2C_Send7bitAddress +* Description : Transmits the address byte to select the slave device. +* Input : - Address: specifies the slave address which will be transmitted +* - Direction: specifies whether the I2C device will be a +* Transmitter or a Receiver. This parameter can be one of the +* following values +* - I2C_MODE_TRANSMITTER: Transmitter mode +* - I2C_MODE_RECEIVER: Receiver mode +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_Send7bitAddress(u8 Address, u8 Direction) +{ + /* Test on the direction to define the read/write bit */ + if (Direction == I2C_MODE_RECEIVER) + { + /* Set the address bit0 for read */ + Address |= I2C_ADD0_Set; + } + else + { + /* Reset the address bit0 for write */ + Address &= I2C_ADD0_Reset; + } + /* Send the address */ + I2C->DR = Address; +} + +/******************************************************************************* +* Function Name : I2C_ReadRegister +* Description : Reads the specified I2C register and returns its value. +* Input1 : - I2C_Register: specifies the register to read. +* This parameter can be one of the following values: +* - I2C_CR: CR register. +* - I2C_SR1: SR1 register. +* - I2C_SR2: SR2 register. +* - I2C_CCR: CCR register. +* - I2C_OAR1: OAR1 register. +* - I2C_OAR2: OAR2 register. +* - I2C_DR: DR register. +* - I2C_ECCR: ECCR register. +* Output : None +* Return : The value of the read register. +*******************************************************************************/ +u8 I2C_ReadRegister(u8 I2C_Register) +{ + /* Return the selected register value */ + return (*(u8 *)(I2C_BASE + I2C_Register)); +} + +/******************************************************************************* +* Function Name : I2C_GetFlagStatus +* Description : Checks whether the specified I2C flag is set or not. +* Input : - I2C_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - I2C_FLAG_SB: Start bit flag (Master mode) +* - I2C_FLAG_M_SL: Master/Slave flag +* - I2C_FLAG_ADSL: Address matched flag (Slave mode) +* - I2C_FLAG_BTF: Byte transfer finished flag +* - I2C_FLAG_BUSY: Bus busy flag +* - I2C_FLAG_TRA: Transmitter/Receiver flag +* - I2C_FLAG_ADD10: 10-bit addressing in Master mode flag +* - I2C_FLAG_EVF: Event flag +* - I2C_FLAG_GCAL: General call flag (slave mode) +* - I2C_FLAG_BERR: Bus error flag +* - I2C_FLAG_ARLO: Arbitration lost flag +* - I2C_FLAG_STOPF: Stop detection flag (slave mode) +* - I2C_FLAG_AF: Acknowledge failure flag +* - I2C_FLAG_ENDAD: End of address transmission flag +* - I2C_FLAG_ACK: Acknowledge enable flag +* Output : None +* Return : The NewState of the I2C_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus I2C_GetFlagStatus(u16 I2C_FLAG) +{ + u16 Flag1 = 0, Flag2 = 0, Flag3 = 0, Tmp = 0; + + Flag1 = I2C->SR1; + Flag2 = I2C->SR2; + Flag2 = Flag2<<8; + Flag3 = I2C->CR & 0x04; + + /* Get all the I2C flags in a unique register*/ + Tmp = (((Flag1 | (Flag2)) & I2C_Event_Mask) | (Flag3<<12)); + + /* Check the status of the specified I2C flag */ + if((Tmp & I2C_FLAG) != RESET) + { + /* Return SET if I2C_FLAG is set */ + return SET; + } + else + { + /* Return RESET if I2C_FLAG is reset */ + return RESET; + } +} + +/******************************************************************************* +* Function Name : I2C_ClearFlag +* Description : Clears the I2C’s pending flags +* Input : - I2C_FLAG: specifies the flag to clear. +* This parameter can be one of the following values: +* - I2C_FLAG_SB: Start bit flag +* - I2C_FLAG_M_SL: Master/Slave flag +* - I2C_FLAG_ADSL: Adress matched flag +* - I2C_FLAG_BTF: Byte transfer finished flag +* - I2C_FLAG_BUSY: Bus busy flag +* - I2C_FLAG_TRA: Transmitter/Receiver flag +* - I2C_FLAG_ADD10: 10-bit addressing in Master mode flag +* - I2C_FLAG_EVF: Event flag +* - I2C_FLAG_GCAL: General call flag +* - I2C_FLAG_BERR: Bus error flag +* - I2C_FLAG_ARLO: Arbitration lost flag +* - I2C_FLAG_STOPF: Stop detection flag +* - I2C_FLAG_AF: Acknowledge failure flag +* - I2C_FLAG_ENDAD: End of address transmission flag +* - I2C_FLAG_ACK: Acknowledge enable flag +* - parameter needed in the case that the flag to be cleared +* need a write in one register +* Output : None +* Return : None +*******************************************************************************/ +void I2C_ClearFlag(u16 I2C_FLAG, ...) +{ + u8 Tmp = (u8)*((u32 *) & I2C_FLAG + sizeof(I2C_FLAG)); + + /* flags that need a read of the SR2 register to be cleared */ + if ((I2C_FLAG == I2C_FLAG_ADD10) || (I2C_FLAG == I2C_FLAG_EVF) || + (I2C_FLAG == I2C_FLAG_STOPF) || (I2C_FLAG == I2C_FLAG_AF) || + (I2C_FLAG == I2C_FLAG_BERR) || (I2C_FLAG == I2C_FLAG_ARLO) || + (I2C_FLAG == I2C_FLAG_ENDAD)) + { + /* Read the SR2 register */ + (void)I2C->SR2; + + /* Two flags need a second step to be cleared */ + switch (I2C_FLAG) + { + case I2C_FLAG_ADD10: + /* Send the MSB 10bit address passed as second parameter */ + I2C->DR = Tmp; + break; + case I2C_FLAG_ENDAD: + /* Write to the I2C_CR register by setting PE bit */ + I2C->CR |= I2C_PE_Set; + break; + } + } + /* flags that need a read of the SR1 register to be cleared */ + else if (I2C_FLAG==I2C_FLAG_SB || I2C_FLAG==I2C_FLAG_ADSL || I2C_FLAG==I2C_FLAG_BTF || I2C_FLAG==I2C_FLAG_TRA) + { + /* Read the SR1 register */ + (void)I2C->SR1; + + /* three flags need a second step to be cleared */ + if (I2C_FLAG == I2C_FLAG_SB) + { + /* Send the address byte passed as second parameter */ + I2C->DR=Tmp; + } + else if (I2C_FLAG==I2C_FLAG_BTF || I2C_FLAG==I2C_FLAG_TRA) + { + /* return the received byte in the variable passed as second parameter */ + Tmp=I2C->DR; + } + } + /* flags that need to disable the I2C interface */ + else if ( I2C_FLAG==I2C_FLAG_M_SL || I2C_FLAG==I2C_FLAG_GCAL) + { + I2C_Cmd(DISABLE); + I2C_Cmd(ENABLE); + } +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_it.c b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_it.c new file mode 100644 index 000000000..b73503624 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_it.c @@ -0,0 +1,448 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_it.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : Main Interrupt Service Routines. +* This file can be used to describe all the exceptions +* subroutines that may occur within user application. +* When an interrupt happens, the software will branch +* automatically to the corresponding routine according +* to the interrupt vector loaded in the PC register. +* The following routines are all empty, user can write code +* for exceptions handlers and peripherals IRQ interrupts. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : Undefined_Handler +* Description : This function handles Undefined instruction exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void Undefined_Handler(void) +{ +} + +/******************************************************************************* +* Function Name : FIQ_Handler +* Description : This function handles FIQ exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void FIQ_Handler(void) +{ +} + +/******************************************************************************* +* Function Name : SWI_Handler +* Description : This function handles SW exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SWI_Handler(void) +{ +} + +/******************************************************************************* +* Function Name : Prefetch_Handler +* Description : This function handles preftetch abort exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void Prefetch_Handler(void) +{ +} + +/******************************************************************************* +* Function Name : Abort_Handler +* Description : This function handles data abort exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void Abort_Handler(void) +{ +} + +/******************************************************************************* +* Function Name : WAKUP_IRQHandler +* Description : This function handles External line 15(WAKUP) interrupt +* request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void WAKUP_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : TIM2_OC2_IRQHandler +* Description : This function handles TIM2 Output Compare 2 interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM2_OC2_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : TIM2_OC1_IRQHandler +* Description : This function handles TIM2 Output Compare 1 interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM2_OC1_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : TIM2_IC12_IRQHandler +* Description : This function handles TIM2 Input Capture 1 & 2 interrupt +* request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM2_IC12_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : TIM2_UP_IRQHandler +* Description : This function handles TIM2 Update interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM2_UP_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : TIM1_OC2_IRQHandler +* Description : This function handles TIM1 Output Compare 2 interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_OC2_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : TIM1_OC1_IRQHandler +* Description : This function handles TIM1 Output Compare 1 interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_OC1_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : TIM1_IC12_IRQHandler +* Description : This function handles TIM1 Input Capture 1 & 2 interrupt +* request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_IC12_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : TIM1_UP_IRQHandler +* Description : This function handles TIM1 Update interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_UP_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : TIM0_OC2_IRQHandler +* Description : This function handles TIM0 Output Compare 2 interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM0_OC2_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : TIM0_OC1_IRQHandler +* Description : This function handles TIM0 Output Compare 1 interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM0_OC1_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : TIM0_IC12_IRQHandler +* Description : This function handles TIM0 Input Capture 1 & 2 interrupt +* request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM0_IC12_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : TIM0_UP_IRQHandler +* Description : This function handles TIM0 Update interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM0_UP_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : PWM_OC123_IRQHandler +* Description : This function handles PWM Output Compare 1,2&3 interrupt +* request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void PWM_OC123_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : PWM_EM_IRQHandler +* Description : This function handles PWM Emergency interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void PWM_EM_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : PWM_UP_IRQHandler +* Description : This function handles PWM Update interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void PWM_UP_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : I2C_IRQHandler +* Description : This function handles I2C global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void I2C_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : SSP1_IRQHandler +* Description : This function handles SSP1 interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SSP1_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : SSP0_IRQHandler +* Description : This function handles SSP0 interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SSP0_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : UART2_IRQHandler +* Description : This function handles UART2 global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void UART2_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : UART1_IRQHandler +* Description : This function handles UART1 global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void UART1_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : UART0_IRQHandler +* Description : This function handles UART0 global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void UART0_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : CAN_IRQHandler +* Description : This function handles CAN global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void CAN_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : USBLP_IRQHandler +* Description : This function handles USB Low Priority event interrupt +* request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void USB_LP_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : USBHP_IRQHandler +* Description : This function handles USB High Priority event interrupt +* request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void USB_HP_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : ADC_IRQHandler +* Description : This function handles ADC global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void ADC_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : DMA_IRQHandler +* Description : This function handles DMA global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void DMA_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : EXTIT_IRQHandler +* Description : This function handles External lines 14 to 1 interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void EXTIT_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : MRCC_IRQHandler +* Description : This function handles MRCC interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : FLASHSMI_IRQHandler +* Description : This function handles Flash and SMI global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void FLASHSMI_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : RTC_IRQHandler +* Description : This function handles RTC global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RTC_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : TB_IRQHandler +* Description : This function handles TB global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TB_IRQHandler(void) +{ +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_lib.c b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_lib.c new file mode 100644 index 000000000..16c87f064 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_lib.c @@ -0,0 +1,178 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_lib.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all peripherals pointers initialization. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +#define EXT + +/* Includes ------------------------------------------------------------------*/ +#include "75x_lib.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +#ifdef DEBUG + +/******************************************************************************* +* Function Name : debug +* Description : This function initialize peripherals pointers. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void debug(void) +{ +/************************************* SMI ************************************/ +#ifdef _SMI + SMI = (SMI_TypeDef *) SMIR_BASE; +#endif /*_SMI */ + +/************************************* CFG ************************************/ +#ifdef _CFG + CFG = (CFG_TypeDef *) CFG_BASE; +#endif /*_CFG */ + +/************************************* MRCC ***********************************/ +#ifdef _MRCC + MRCC = (MRCC_TypeDef *) MRCC_BASE; +#endif /*_MRCC */ + +/************************************* ADC ************************************/ +#ifdef _ADC + ADC = (ADC_TypeDef *) ADC_BASE; +#endif /*_ADC */ + +/************************************* TB *************************************/ +#ifdef _TB + TB = (TB_TypeDef *) TB_BASE; +#endif /*_TB */ + +/************************************* TIM ************************************/ +#ifdef _TIM0 + TIM0 = (TIM_TypeDef *) TIM0_BASE; +#endif /*_TIM0 */ + +#ifdef _TIM1 + TIM1 = (TIM_TypeDef *) TIM1_BASE; +#endif /*_TIM1 */ + +#ifdef _TIM2 + TIM2 = (TIM_TypeDef *) TIM2_BASE; +#endif /*_TIM2 */ + +/************************************* PWM ************************************/ +#ifdef _PWM + PWM = (PWM_TypeDef *) PWM_BASE; +#endif /*_PWM */ + +/************************************* WDG ************************************/ +#ifdef _WDG + WDG = (WDG_TypeDef *) WDG_BASE; +#endif /*_WDG */ + +/************************************* SSP ************************************/ +#ifdef _SSP0 + SSP0 = (SSP_TypeDef *) SSP0_BASE; +#endif /*_SSP0 */ + +#ifdef _SSP1 + SSP1 = (SSP_TypeDef *) SSP1_BASE; +#endif /*_SSP1 */ + +/************************************* CAN ************************************/ +#ifdef _CAN + CAN = (CAN_TypeDef *) CAN_BASE; +#endif /*_CAN */ + +/************************************* I2C ************************************/ +#ifdef _I2C + I2C = (I2C_TypeDef *) I2C_BASE; +#endif /*_I2C */ + +/************************************* UART ***********************************/ +#ifdef _UART0 + UART0 = (UART_TypeDef *) UART0_BASE; +#endif /*_UART0 */ + +#ifdef _UART1 + UART1 = (UART_TypeDef *) UART1_BASE; +#endif /*_UART1 */ + +#ifdef _UART2 + UART2 = (UART_TypeDef *) UART2_BASE; +#endif /*_UART2 */ + +/************************************* GPIO ***********************************/ +#ifdef _GPIO0 + GPIO0 = (GPIO_TypeDef *) GPIO0_BASE; +#endif /*_GPIO0 */ + +#ifdef _GPIO1 + GPIO1 = (GPIO_TypeDef *) GPIO1_BASE; +#endif /*_GPIO1 */ + +#ifdef _GPIO2 + GPIO2 = (GPIO_TypeDef *) GPIO2_BASE; +#endif /*_GPIO2 */ + +#ifdef _GPIOREMAP + GPIOREMAP = (GPIOREMAP_TypeDef *) GPIOREMAP_BASE; +#endif /*_GPIOREMAP */ + +/************************************* DMA ************************************/ +#ifdef _DMA + DMA = (DMA_TypeDef *) DMA_BASE; +#endif /*_DMA */ + +#ifdef _DMA_Stream0 + DMA_Stream0 = (DMA_Stream_TypeDef *) DMA_Stream0_BASE; +#endif /*_DMA_Stream0 */ + +#ifdef _DMA_Stream1 + DMA_Stream1 = (DMA_Stream_TypeDef *) DMA_Stream1_BASE; +#endif /*_DMA_Stream1 */ + +#ifdef _DMA_Stream2 + DMA_Stream2 = (DMA_Stream_TypeDef *) DMA_Stream2_BASE; +#endif /*_DMA_Stream2 */ + +#ifdef _DMA_Stream3 + DMA_Stream3 = (DMA_Stream_TypeDef *) DMA_Stream3_BASE; +#endif /*_DMA_Stream3 */ + +/************************************* RTC ************************************/ +#ifdef _RTC + RTC = (RTC_TypeDef *) RTC_BASE; +#endif /*_RTC */ + +/************************************* EXTIT **********************************/ +#ifdef _EXTIT + EXTIT = (EXTIT_TypeDef *) EXTIT_BASE; +#endif /*_EXTIT */ + +/************************************* EIC ************************************/ +#ifdef _EIC + EIC = (EIC_TypeDef *) EIC_BASE; +#endif /*_EIC */ + +} + +#endif + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_mrcc.c b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_mrcc.c new file mode 100644 index 000000000..fadfb73c7 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_mrcc.c @@ -0,0 +1,1673 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_mrcc.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the MRCC software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_mrcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define MRCC_FLAG_Mask 0x1F /* MRCC Flag Mask */ + +/* MRCC_PWRCTRL mask bits */ +#define MRCC_LP_Set_Mask 0x00000001 +#define MRCC_LP_Reset_Mask 0xFFFFFFFE +#define MRCC_SWRESET_Mask 0x00000002 +#define MRCC_WFI_Mask 0x00000004 +#define MRCC_STANDBY_Mask 0x00000006 +#define MRCC_LPMC_Reset_Mask 0xFFFFFFF9 +#define MRCC_LPDONE_Reset_Mask 0xFFFFFF7F +#define MRCC_LPPARAM_Reset_Mask 0xFFFF1FFF +#define MRCC_WFIParam_Reset_Mask 0xFFFF1FEF +#define MRCC_CKRTCSEL_Set_Mask 0x03000000 +#define MRCC_CKRTCSEL_Reset_Mask 0xFCFFFFFF +#define MRCC_CKRTCOK_Mask 0x08000000 +#define MRCC_LPOSCEN_Mask 0x10000000 +#define MRCC_OSC32KEN_Mask 0x20000000 + +/* MRCC_CLKCTL mask bits */ +#define MRCC_PPRESC_Set_Mask 0x00000003 +#define MRCC_PPRESC_Reset_Mask 0xFFFFFFFC +#define MRCC_PPRESC2_Mask 0x00000004 +#define MRCC_HPRESC_Set_Mask 0x00000018 +#define MRCC_HPRESC_Reset_Mask 0xFFFFFFE7 +#define MRCC_MCOS_Reset_Mask 0xFFFFFF3F +#define MRCC_XTDIV2_Set_Mask 0x00008000 +#define MRCC_XTDIV2_Reset_Mask 0xFFFF7FFF +#define MRCC_OSC4MBYP_Set_Mask 0x00010000 +#define MRCC_OSC4MBYP_Reset_Mask 0xFFFEFFFF +#define MRCC_OSC4MOFF_Set_Mask 0x00020000 +#define MRCC_OSC4MOFF_Reset_Mask 0xFFFDFFFF +#define MRCC_NCKDF_Set_Mask 0x00040000 +#define MRCC_NCKDF_Reset_Mask 0xFFFBFFFF +#define MRCC_CKOSCSEL_Set_Mask 0x00200000 +#define MRCC_CKOSCSEL_Reset_Mask 0xFFDFFFFF +#define MRCC_CKUSBSEL_Mask 0x00400000 +#define MRCC_CKSEL_Set_Mask 0x00800000 +#define MRCC_CKSEL_Reset_Mask 0xFF7FFFFF +#define MRCC_CKSEL_CKOSCSEL_Mask 0x00A00000 +#define MRCC_PLLEN_Set_Mask 0x01000000 +#define MRCC_PLLEN_Reset_Mask 0xFEFFFFFF +#define MRCC_PLL2EN_Set_Mask 0x02000000 +#define MRCC_PLL2EN_Reset_Mask 0xFDFFFFFF +#define MRCC_MX_Set_Mask 0x18000000 +#define MRCC_MX_Reset_Mask 0xE7FFFFFF +#define MRCC_LOCK_Mask 0x80000000 +#define MRCC_PLLEN_LOCK_Mask 0x81000000 + +/* Typical Value of the OSC4M in Hz */ +#define OSC4M_Value 4000000 + +/* Typical Value of the OSC4M divided by 128 (used to clock the RTC) in Hz */ +#define OSC4M_Div128_Value 31250 + +/* Typical Value of the OS32K Oscillator Frequency in Hz */ +#define OSC32K_Value 32768 + +/* Typical Reset Value of the Internal LPOSC Oscillator Frequency in Hz */ +#define LPOSC_Value 245000 + +/* Typical Reset Value of the Internal FREEOSC Oscillator Frequency in Hz */ +#define FREEOSC_Value 5000000 + +/* Time out for OSC4M start up */ +#define OSC4MStartUp_TimeOut 0xFE + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static ErrorStatus SetCKSYS_FREEOSC(void); +static ErrorStatus SetCKSYS_OSC4M(u32 PLL_State); +static ErrorStatus SetCKSYS_OSC4MPLL(u32 PLL_Mul); +static ErrorStatus SetCKSYS_RTC(u32 PLL_State); +static void WriteLPBit(void); +static void WriteCKOSCSELBit(void); + +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : MRCC_DeInit +* Description : Deinitializes the MRCC peripheral registers to their default +* reset values. +* - Depending on the system clock state, some bits in MRCC_CLKCTL +* register can’t be reset. +* - The OSC32K, LPOSC and RTC clock selection configuration +* bits in MRCC_PWRCTRL register are not cleared by this +* function. To reset those bits, use the dedicated functions +* available within this driver. +* - The MRCC_RFSR, MRCC_BKP0 and MRCC_BKP1 registers are not +* reset by this function. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_DeInit(void) +{ + /* Try to clear NCKDF bit */ + MRCC->CLKCTL &= MRCC_NCKDF_Reset_Mask; + + if((MRCC->CLKCTL & MRCC_NCKDF_Set_Mask) != RESET) + {/* No clock detected on OSC4M */ + + /* Reset LOCKIE, LOCKIF, CKUSBSEL, NCKDIE, OSC4MOFF, OSC4MBYP, MCOS[1:0], + MCOP, HPRESC[1:0], PPRES[2:0] bits */ + MRCC->CLKCTL &= 0x9FB40000; + + if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET) + { + /* Clear CKOSCSEL bit --------------------------------------------------*/ + /* Execute CKOSCSEL bit writing sequence */ + WriteCKOSCSELBit(); + } + } + else + {/* Clock present on OSC4M */ + + if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET) + { + /* Reset CKSEL bit */ + MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask; + + /* Clear CKOSCSEL bit --------------------------------------------------*/ + /* Execute CKOSCSEL bit writing sequence */ + WriteCKOSCSELBit(); + } + + if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) == RESET) + { + /* Set CKSEL bit */ + MRCC->CLKCTL |= MRCC_CKSEL_Set_Mask; + } + + /* Disable PLL */ + MRCC->CLKCTL &= MRCC_PLLEN_Reset_Mask; + + /* Reset LOCKIE, LOCKIF, MX[1:0], CKUSBSEL, NCKDIE, MCOS[1:0], MCOP, + HPRESC[1:0], PPRES[2:0] bits */ + MRCC->CLKCTL &= 0x87B70000; + + /* Reset CKSEL bit */ + MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask; + + /* Reset OSC4MOFF and OSC4MBYP bits */ + MRCC->CLKCTL &= 0xFFFCFFFF; + } + + /* Reset RTCM, EN33V, LP_PARAM[15:13], WFI_FLASH_EN, LPMC_DBG and LPMC[1:0] bits */ + MRCC->PWRCTRL &= 0xFBFE1FE1; + + /* Reset PCLKEN register bits */ + MRCC->PCLKEN = 0x00; + + /* Reset PSWRES register bits */ + MRCC->PSWRES = 0x00; + + /* Clear NCKDF bit */ + MRCC->CLKCTL &= MRCC_NCKDF_Reset_Mask; +} + +/******************************************************************************* +* Function Name : MRCC_XTDIV2Config +* Description : Enables or disables the oscillator divider by 2. This function +* must not be used when the PLL is enabled. +* Input : - MRCC_XTDIV2: specifies the new state of the oscillator +* divider by 2. +* This parameter can be one of the following values: +* - MRCC_XTDIV2_Disable: oscillator divider by 2 disbaled +* - MRCC_XTDIV2_Enable: oscillator divider by 2 enbaled +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_XTDIV2Config(u32 MRCC_XTDIV2) +{ + if(MRCC_XTDIV2 == MRCC_XTDIV2_Enable) + { + MRCC->CLKCTL |= MRCC_XTDIV2_Enable; + } + else + { + MRCC->CLKCTL &= MRCC_XTDIV2_Disable; + } +} + +/******************************************************************************* +* Function Name : MRCC_CKSYSConfig +* Description : Configures the system clock (CK_SYS). +* Input : - MRCC_CKSYS: specifies the clock source used as system clock. +* This parameter can be one of the following values: +* - MRCC_CKSYS_FREEOSC +* - MRCC_CKSYS_OSC4M +* - MRCC_CKSYS_OSC4MPLL +* - MRCC_CKSYS_RTC (RTC clock source must be previously +* configured using MRCC_CKRTCConfig() function) +* : - MRCC_PLL: specifies the PLL configuration. +* This parameter can be one of the following values: +* - MRCC_PLL_Disabled: PLL disabled +* - MRCC_PLL_NoChange: No change on PLL configuration +* - MRCC_PLL_Mul_12: Multiplication by 12 +* - MRCC_PLL_Mul_14: Multiplication by 14 +* - MRCC_PLL_Mul_15: Multiplication by 15 +* - MRCC_PLL_Mul_16: Multiplication by 16 +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Clock configuration succeeded +* - ERROR: Clock configuration failed +*******************************************************************************/ +ErrorStatus MRCC_CKSYSConfig(u32 MRCC_CKSYS, u32 MRCC_PLL) +{ + ErrorStatus Status = ERROR; + + switch(MRCC_CKSYS) + { + case MRCC_CKSYS_FREEOSC: + if((MRCC_PLL == MRCC_PLL_Disabled) || (MRCC_PLL == MRCC_PLL_NoChange)) + { + Status = SetCKSYS_FREEOSC(); + } + break; + + case MRCC_CKSYS_OSC4M: + if((MRCC_PLL == MRCC_PLL_Disabled) || (MRCC_PLL == MRCC_PLL_NoChange)) + { + Status = SetCKSYS_OSC4M(MRCC_PLL); + } + break; + + case MRCC_CKSYS_OSC4MPLL: + if((MRCC_PLL == MRCC_PLL_Mul_12) || (MRCC_PLL == MRCC_PLL_Mul_14) || + (MRCC_PLL == MRCC_PLL_Mul_15) || (MRCC_PLL == MRCC_PLL_Mul_16)) + { + Status = SetCKSYS_OSC4MPLL(MRCC_PLL); + } + break; + + case MRCC_CKSYS_RTC: + if((MRCC_PLL == MRCC_PLL_Disabled) || (MRCC_PLL == MRCC_PLL_NoChange)) + { + Status = SetCKSYS_RTC(MRCC_PLL); + } + break; + + default: + Status = ERROR; + break; + } + return Status; +} + +/******************************************************************************* +* Function Name : MRCC_HCLKConfig +* Description : Configures the AHB clock (HCLK). +* Input : - MRCC_HCLK: defines the AHB clock. This clock is derived +* from the system clock(CK_SYS). +* This parameter can be one of the following values: +* - MRCC_CKSYS_Div1: AHB clock = CK_SYS +* - MRCC_CKSYS_Div2: AHB clock = CK_SYS/2 +* - MRCC_CKSYS_Div4: AHB clock = CK_SYS/4 +* - MRCC_CKSYS_Div8: AHB clock = CK_SYS/8 +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_HCLKConfig(u32 MRCC_HCLK) +{ + u32 Temp = 0; + + /* Clear HPRESC[1:0] bits */ + Temp = MRCC->CLKCTL & MRCC_HPRESC_Reset_Mask; + + /* Set HPRESC[1:0] bits according to MRCC_HCLK value */ + Temp |= MRCC_HCLK; + + /* Store the new value */ + MRCC->CLKCTL = Temp; +} + +/******************************************************************************* +* Function Name : MRCC_CKTIMConfig +* Description : Configures the TIM clock (CK_TIM). +* Input : - MRCC_CKTIM: defines the TIM clock. This clock is derived +* from the AHB clock(HCLK). +* This parameter can be one of the following values: +* - MRCC_HCLK_Div1: TIM clock = HCLK +* - MRCC_HCLK_Div2: TIM clock = HCLK/2 +* - MRCC_HCLK_Div4: TIM clock = HCLK/4 +* - MRCC_HCLK_Div8: TIM clock = HCLK/8 +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_CKTIMConfig(u32 MRCC_CKTIM) +{ + u32 Temp = 0; + + /* Clear PPRESC[1:0] bits */ + Temp = MRCC->CLKCTL & MRCC_PPRESC_Reset_Mask; + + /* Set PPRESC[1:0] bits according to MRCC_CKTIM value */ + Temp |= MRCC_CKTIM; + + /* Store the new value */ + MRCC->CLKCTL = Temp; +} + +/******************************************************************************* +* Function Name : MRCC_PCLKConfig +* Description : Configures the APB clock (PCLK). +* Input : - MRCC_PCLK: defines the APB clock. This clock is derived +* from the TIM clock(CK_TIM). +* This parameter can be one of the following values: +* - MRCC_CKTIM_Div1: APB clock = CKTIM +* - MRCC_CKTIM_Div2: APB clock = CKTIM/2 +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_PCLKConfig(u32 MRCC_PCLK) +{ + if(MRCC_PCLK == MRCC_CKTIM_Div2) + { + MRCC->CLKCTL |= MRCC_CKTIM_Div2; + } + else + { + MRCC->CLKCTL &= MRCC_CKTIM_Div1; + } +} + +/******************************************************************************* +* Function Name : MRCC_CKRTCConfig +* Description : Configures the RTC clock (CK_RTC). +* Input : - MRCC_CKRTC: specifies the clock source to be used as RTC +* clock. +* This parameter can be one of the following values: +* - MRCC_CKRTC_OSC4M_Div128 +* - MRCC_CKRTC_OSC32K (OSC32K must be previously enabled +* using MRCC_OSC32KConfig() function) +* - MRCC_CKRTC_LPOSC (LPOSC must be previously enabled +* using MRCC_LPOSCConfig() function) +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Clock configuration succeeded +* - ERROR: Clock configuration failed +*******************************************************************************/ +ErrorStatus MRCC_CKRTCConfig(u32 MRCC_CKRTC) +{ + u32 Tmp = 0; + + if(((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET) && + ((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET)) + { + /* CK_RTC used as CK_SYS clock source */ + return ERROR; + } + else + { + /* Clear CKRTCSEL[1:0] bits */ + Tmp = MRCC->PWRCTRL & MRCC_CKRTCSEL_Reset_Mask; + + /* Set CKRTCSEL[1:0] bits according to MRCC_CKRTC value */ + Tmp |= MRCC_CKRTC; + + /* Store the new value */ + MRCC->PWRCTRL = Tmp; + } + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : MRCC_CKUSBConfig +* Description : Configures the USB clock(CK_USB). +* Input : - MRCC_CKUSB: specifies the clock source to be used as USB +* clock. +* This parameter can be one of the following values: +* - MRCC_CKUSB_Internal(CK_PLL2 enabled) +* - MRCC_CKUSB_External(CK_PLL2 disabled) +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Clock configuration succeeded +* - ERROR: Clock configuration failed +*******************************************************************************/ +ErrorStatus MRCC_CKUSBConfig(u32 MRCC_CKUSB) +{ + if(MRCC_CKUSB == MRCC_CKUSB_External) + { + /* Disable CK_PLL2 */ + MRCC->CLKCTL &= MRCC_PLL2EN_Reset_Mask; + + /* External USB clock selected */ + MRCC->CLKCTL |= MRCC_CKUSB_External; + } + else + { + if((MRCC->CLKCTL & MRCC_PLLEN_LOCK_Mask) != RESET) + { /* PLL enabled and locked */ + + /* Enable CK_PLL2 */ + MRCC->CLKCTL |= MRCC_PLL2EN_Set_Mask; + + /* Internal USB clock selected */ + MRCC->CLKCTL &= MRCC_CKUSB_Internal; + } + else + { + /* PLL not enabled */ + return ERROR; + } + } + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : MRCC_ITConfig +* Description : Enables or disables the specified MRCC interrupts. +* Input : - MRCC_IT: specifies the MRCC interrupts sources to be +* enabled or disabled. This parameter can be any combination +* of the following values: +* - MRCC_IT_LOCK: PLL lock interrupt +* - MRCC_IT_NCKD: No Clock detected interrupt +* - NewState: new state of the MRCC interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_ITConfig(u32 MRCC_IT, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + MRCC->CLKCTL |= MRCC_IT; + } + else + { + MRCC->CLKCTL &= ~MRCC_IT; + } +} + +/******************************************************************************* +* Function Name : MRCC_PeripheralClockConfig +* Description : Enables or disables the specified peripheral clock. +* Input : - MRCC_Peripheral: specifies the peripheral to gates its +* clock. More than one peripheral can be selected using +* the “|” operator. +* - NewState: new state of the specified peripheral clock. +* This parameter can be one of the following values: +* - ENABLE: the selected peripheral clock is enabled +* - DISABLE: the selected peripheral clock is disabled +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_PeripheralClockConfig(u32 MRCC_Peripheral, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + MRCC->PCLKEN |= MRCC_Peripheral; + } + else + { + MRCC->PCLKEN &= ~MRCC_Peripheral; + } +} + +/******************************************************************************* +* Function Name : MRCC_PeripheralSWResetConfig +* Description : Forces or releases peripheral software reset. +* Input : - MRCC_Peripheral: specifies the peripheral to reset. More +* than one peripheral can be selected using the “|” operator. +* - NewState: new state of the specified peripheral software +* reset. This parameter can be one of the following values: +* - ENABLE: the selected peripheral is kept under reset +* - DISABLE: the selected peripheral exits from reset +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_PeripheralSWResetConfig(u32 MRCC_Peripheral, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + MRCC->PSWRES |= MRCC_Peripheral; + } + else + { + MRCC->PSWRES &= ~MRCC_Peripheral; + } +} + +/******************************************************************************* +* Function Name : MRCC_GetClocksStatus +* Description : Returns the status and frequencies of different on chip clocks. +* Don’t use this function when CK_SYS is clocked by an external +* clock source (OSC4M bypassed). +* Input : - MRCC_ClocksStatus: pointer to a MRCC_ClocksTypeDef structure +* which will hold the clocks information. +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_GetClocksStatus(MRCC_ClocksTypeDef* MRCC_ClocksStatus) +{ + u32 PLLMul = 0; + u32 Temp = 0; + u32 Presc = 0; + + /* Get the Status of PLL */ + if((MRCC->CLKCTL & MRCC_PLLEN_Set_Mask) == RESET) + { + MRCC_ClocksStatus->PLL_Status = OFF; + } + else + { + MRCC_ClocksStatus->PLL_Status = ON; + } + + /* Get the Status of OSC4M */ + if((MRCC->CLKCTL & MRCC_OSC4MOFF_Set_Mask) == RESET) + { + MRCC_ClocksStatus->OSC4M_Status = ON; + } + else + { + MRCC_ClocksStatus->OSC4M_Status = OFF; + } + + /* Get the Status of LPOSC */ + if((MRCC->PWRCTRL & MRCC_LPOSCEN_Mask) == RESET) + { + MRCC_ClocksStatus->LPOSC_Status = OFF; + } + else + { + MRCC_ClocksStatus->LPOSC_Status = ON; + } + + /* Get the Status of OSC32K */ + if((MRCC->PWRCTRL & MRCC_OSC32KEN_Mask) == RESET) + { + MRCC_ClocksStatus->OSC32K_Status = OFF; + } + else + { + MRCC_ClocksStatus->OSC32K_Status = ON; + } + +/* Get CKU_SB source ---------------------------------------------------------*/ + if((MRCC->CLKCTL & MRCC_CKUSBSEL_Mask) != RESET) + { + MRCC_ClocksStatus->CKUSB_Source = External; + } + else + { + if((MRCC->CLKCTL & MRCC_PLL2EN_Set_Mask) != RESET) + { + MRCC_ClocksStatus->CKUSB_Source = Internal; + + } + else + { + MRCC_ClocksStatus->CKUSB_Source = Disabled; + } + } + +/* Get CK_RTC source ---------------------------------------------------------*/ + Temp = MRCC->PWRCTRL & MRCC_CKRTCSEL_Set_Mask; + Temp = Temp >> 24; + + switch(Temp) + { + case 0x00: + MRCC_ClocksStatus->CKRTC_Source = Disabled; + break; + + case 0x01: + MRCC_ClocksStatus->CKRTC_Source = OSC4M_Div128; + break; + + case 0x02: + MRCC_ClocksStatus->CKRTC_Source = OSC32K; + break; + + case 0x03: + MRCC_ClocksStatus->CKRTC_Source = LPOSC; + break; + + default: + MRCC_ClocksStatus->CKRTC_Source = Disabled; + break; + } + +/* Get CK_SYS source ---------------------------------------------------------*/ + if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET) + {/* CK_OSC used as CK_SYS clock source */ + + if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET) + { /* CK_RTC used as CK_OSC clock source */ + MRCC_ClocksStatus->CKSYS_Source = CKRTC; + + if(MRCC_ClocksStatus->CKRTC_Source == OSC32K) + { + /* CK_SYS clock frequency */ + MRCC_ClocksStatus->CKSYS_Frequency = OSC32K_Value; + } + else if(MRCC_ClocksStatus->CKRTC_Source == LPOSC) + + { + /* CK_SYS clock frequency */ + MRCC_ClocksStatus->CKSYS_Frequency = LPOSC_Value; + } + else if(MRCC_ClocksStatus->CKRTC_Source == OSC4M_Div128) + + { + /* CK_SYS clock frequency */ + MRCC_ClocksStatus->CKSYS_Frequency = OSC4M_Div128_Value; + } + } + else + { /* OSC4M used as CK_OSC clock source */ + MRCC_ClocksStatus->CKSYS_Source = OSC4M; + + if((MRCC->CLKCTL & MRCC_XTDIV2_Set_Mask) != RESET) + { + /* CK_SYS clock frequency */ + MRCC_ClocksStatus->CKSYS_Frequency = Main_Oscillator >> 1; + } + else + { + /* CK_SYS clock frequency */ + MRCC_ClocksStatus->CKSYS_Frequency = Main_Oscillator; + } + } + } + else + {/* CK_PLL1 used as CK_SYS clock */ + + if(MRCC_ClocksStatus->PLL_Status == OFF) + { /* FREEOSC used as CK_PLL1 clock source */ + MRCC_ClocksStatus->CKSYS_Source = FREEOSC; + + /* CK_SYS clock frequency */ + MRCC_ClocksStatus->CKSYS_Frequency = FREEOSC_Value; + } + else + { /* OSC4M followed by PLL used as CK_PLL1 clock source */ + MRCC_ClocksStatus->CKSYS_Source = OSC4MPLL; + + /* Get PLL factor ------------------------------------------------------*/ + Temp = MRCC->CLKCTL & MRCC_MX_Set_Mask; + Temp = Temp >> 27; + + switch(Temp) + { + case 0x00: + PLLMul = 16; + break; + + case 0x01: + PLLMul = 15; + break; + + case 0x02: + PLLMul = 14; + break; + + case 0x03: + PLLMul = 12; + break; + + default: + PLLMul = 16; + break; + } + + /* CK_SYS clock frequency */ + MRCC_ClocksStatus->CKSYS_Frequency = OSC4M_Value * PLLMul; + } + } + +/* Compute HCLK, CKTIM and PCLK clocks frequencies ---------------------------*/ + /* Get HCLK prescaler */ + Presc = MRCC->CLKCTL & MRCC_HPRESC_Set_Mask; + Presc = Presc >> 3; + /* HCLK clock frequency */ + MRCC_ClocksStatus->HCLK_Frequency = MRCC_ClocksStatus->CKSYS_Frequency >> Presc; + + /* Get CK_TIM prescaler */ + Presc = MRCC->CLKCTL & MRCC_PPRESC_Set_Mask; + /* CK_TIM clock frequency */ + MRCC_ClocksStatus->CKTIM_Frequency = MRCC_ClocksStatus->HCLK_Frequency >> Presc; + + /* Get PCLK prescaler */ + Presc = MRCC->CLKCTL & MRCC_PPRESC2_Mask; + Presc = Presc >> 2; + /* PCLK clock frequency */ + MRCC_ClocksStatus->PCLK_Frequency = MRCC_ClocksStatus->CKTIM_Frequency >> Presc; +} + +/******************************************************************************* +* Function Name : MRCC_LPMC_DBGonfig +* Description : Enables or disables the Low Power Debug Mode. +* Input : - MRCC_LPDM: specifies the LPDM new state value. +* This parameter can be one of the following values: +* - MRCC_LPDM_Disable +* - MRCC_LPDM_Enable +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_LPMC_DBGConfig(u32 MRCC_LPDM) +{ + if(MRCC_LPDM == MRCC_LPDM_Enable) + { + MRCC->PWRCTRL |= MRCC_LPDM_Enable; + } + else + { + MRCC->PWRCTRL &= MRCC_LPDM_Disable; + } +} + +/******************************************************************************* +* Function Name : MRCC_EnterWFIMode +* Description : Enters WFI mode. +* If the Flash is used in Burst mode, it must be kept enabled +* in WFI mode(use MRCC_WFIParam_FLASHOn as parameter) +* Input : - MRCC_WFIParam: specifies the WFI mode control parameters. +* This parameter can be one of the following values: +* - MRCC_WFIParam_FLASHPowerDown(DMA not allowed during WFI) +* - MRCC_WFIParam_FLASHOn(DMA allowed during WFI) +* - MRCC_WFIParam_FLASHOff(DMA not allowed during WFI) +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_EnterWFIMode(u32 MRCC_WFIParam) +{ +/* Low Power mode configuration ----------------------------------------------*/ + /* Clear LPMC[1:0] bits */ + MRCC->PWRCTRL &= MRCC_LPMC_Reset_Mask; + + /* Select WFI mode */ + MRCC->PWRCTRL |= MRCC_WFI_Mask; + +/* Low Power mode control parameters configuration ---------------------------*/ + /* Clear LP_PARAM[15:13] and WFI_FLASH_EN bits */ + MRCC->PWRCTRL &= MRCC_WFIParam_Reset_Mask; + + if(MRCC_WFIParam != MRCC_WFIParam_FLASHPowerDown) + { + /* Set LP_PARAM[15:13] and WFI_FLASH_EN bits according to MRCC_WFIParam value */ + MRCC->PWRCTRL |= MRCC_WFIParam; + } + +/* Execute the Low Power bit writing sequence --------------------------------*/ + WriteLPBit(); +} + +/******************************************************************************* +* Function Name : MRCC_EnterSTOPMode +* Description : Enters STOP mode. +* Input : - MRCC_STOPParam: specifies the STOP mode control parameters. +* This parameter can be one of the following values: +* - MRCC_STOPParam_Default (OSC4M On, FLASH On, MVREG On) +* - MRCC_STOPParam_OSC4MOff +* - MRCC_STOPParam_FLASHOff +* - MRCC_STOPParam_MVREGOff +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_EnterSTOPMode(u32 MRCC_STOPParam) +{ +/* Low Power mode configuration ----------------------------------------------*/ + /* Clear LPMC[1:0] bits (STOP mode is selected) */ + MRCC->PWRCTRL &= MRCC_LPMC_Reset_Mask; + +/* Low Power mode control parameters configuration ---------------------------*/ + /* Clear LP_PARAM[15:13] bits */ + MRCC->PWRCTRL &= MRCC_LPPARAM_Reset_Mask; + + if(MRCC_STOPParam != MRCC_STOPParam_Default) + { + /* Set LP_PARAM[15:13] bits according to MRCC_STOPParam value */ + MRCC->PWRCTRL |= MRCC_STOPParam; + } + +/* Execute the Low Power bit writing sequence --------------------------------*/ + WriteLPBit(); +} + +/******************************************************************************* +* Function Name : MRCC_EnterSTANDBYMode +* Description : Enters STANDBY mode. +* Make sure that WKPF flag is cleared before using this function. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_EnterSTANDBYMode(void) +{ +/* Low Power mode configuration ----------------------------------------------*/ + /* Clear LPMC[1:0] bits */ + MRCC->PWRCTRL &= MRCC_LPMC_Reset_Mask; + + /* Select STANDBY mode */ + MRCC->PWRCTRL |= MRCC_STANDBY_Mask; + +/* Execute the Low Power bit writing sequence --------------------------------*/ + WriteLPBit(); +} + +/******************************************************************************* +* Function Name : MRCC_GenerateSWReset +* Description : Generates a system software reset. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_GenerateSWReset(void) +{ +/* Low Power mode configuration ----------------------------------------------*/ + /* Clear LPMC[1:0] bits */ + MRCC->PWRCTRL &= MRCC_LPMC_Reset_Mask; + + /* Select software reset */ + MRCC->PWRCTRL |= MRCC_SWRESET_Mask; + +/* Execute the Low Power bit writing sequence --------------------------------*/ + WriteLPBit(); +} + +/******************************************************************************* +* Function Name : MRCC_WriteBackupRegister +* Description : Writes user data to the specified backup register. +* Input : - MRCC_BKP: specifies the backup register. +* This parameter can be one of the following values: +* - MRCC_BKP0 +* - MRCC_BKP1 +* - Data: data to write. +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_WriteBackupRegister(MRCC_BKPReg MRCC_BKP, u32 Data) +{ + if(MRCC_BKP == MRCC_BKP0) + { + MRCC->BKP0 = Data; + } + else + { + MRCC->BKP1 = Data; + } +} + +/******************************************************************************* +* Function Name : MRCC_ReadBackupRegister +* Description : Reads data from the specified backup register. +* Input : - MRCC_BKP: specifies the backup register. +* This parameter can be one of the following values: +* - MRCC_BKP0 +* - MRCC_BKP1 +* Output : None +* Return : The content of the specified backup register. +*******************************************************************************/ +u32 MRCC_ReadBackupRegister(MRCC_BKPReg MRCC_BKP) +{ + if(MRCC_BKP == MRCC_BKP0) + { + return(MRCC->BKP0); + } + else + { + return(MRCC->BKP1); + } +} + +/******************************************************************************* +* Function Name : MRCC_IOVoltageRangeConfig +* Description : Configures the I/O pins voltage range. +* Input : - MRCC_IOVoltageRange: specifies the I/O pins voltage range. +* This parameter can be one of the following values: +* - MRCC_IOVoltageRange_5V +* - MRCC_IOVoltageRange_3V3 +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_IOVoltageRangeConfig(u32 MRCC_IOVoltageRange) +{ + if(MRCC_IOVoltageRange == MRCC_IOVoltageRange_3V3) + { + MRCC->PWRCTRL |= MRCC_IOVoltageRange_3V3; + } + else + { + MRCC->PWRCTRL &= MRCC_IOVoltageRange_5V; + } +} + +/******************************************************************************* +* Function Name : MRCC_MCOConfig +* Description : Selects the clock source to output on MCO pin (P0.1). +* To output the clock, the associated alternate function must +* be enabled in the I/O port controller. +* Input : - MRCC_MCO: specifies the clock source to output. +* This parameter can be one of the following values: +* - MRCC_MCO_HCLK +* - MRCC_MCO_PCLK +* - MRCC_MCO_OSC4M +* - MRCC_MCO_CKPLL2 +* - MRCC_MCOPrescaler: specifies if prescaler, divide by 1 or 2, +* is applied to this clock before outputting it to MCO pin. +* This parameter can be one of the following values: +* - MRCC_MCOPrescaler_1 +* - MRCC_MCOPrescaler_2 +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_MCOConfig(u32 MRCC_MCO, u32 MCO_MCOPrescaler) +{ + u32 Temp = 0; +/* MCO prescaler configuration -----------------------------------------------*/ + if(MCO_MCOPrescaler == MRCC_MCOPrescaler_2) + { + MRCC->CLKCTL |= MRCC_MCOPrescaler_2; + } + else + { + MRCC->CLKCTL &= MRCC_MCOPrescaler_1; + } + +/* MCO selection configuration -----------------------------------------------*/ + + /* Clear MCOS[1:0] bits */ + Temp = MRCC->CLKCTL & MRCC_MCOS_Reset_Mask; + + /* Set MCOS[1:0] bits according to MRCC_MCO value */ + Temp |= MRCC_MCO; + + /* Store the new value */ + MRCC->CLKCTL = Temp; +} + +/******************************************************************************* +* Function Name : MRCC_OSC4MConfig +* Description : Configures the 4MHz main oscillator (OSC4M). +* This function must be used when the CK_SYS is not clocked +* by the OSC4M and the PLL is not enabled. +* Input : - MRCC_OSC4M: specifies the new state of the OSC4M oscillator. +* This parameter can be one of the following values: +* - MRCC_OSC4M_Default: OSC4M enabled, bypass disabled +* - MRCC_OSC4M_Disable: OSC4M disabled +* - MRCC_OSC4M_Bypass: OSC4M bypassed +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Clock configuration succeeded +* - ERROR: Clock configuration failed +*******************************************************************************/ +ErrorStatus MRCC_OSC4MConfig(u32 MRCC_OSC4M) +{ + ErrorStatus Status = SUCCESS; + +/* If CK_SYS is driven by OSC4M or the PLL is enabled, exit ------------------*/ + if(((MRCC->CLKCTL & MRCC_CKSEL_CKOSCSEL_Mask) == MRCC_CKSEL_Set_Mask) || + (((MRCC->CLKCTL & MRCC_CKSEL_CKOSCSEL_Mask) == MRCC_CKSEL_CKOSCSEL_Mask) && + ((MRCC->PWRCTRL & MRCC_CKRTCSEL_Reset_Mask) != RESET))|| + ((MRCC->CLKCTL & MRCC_PLLEN_Set_Mask) != RESET)) + { + Status = ERROR; + } +/* Else configure the OSC4MOFF and OSC4MBYP bits -----------------------------*/ + else + { + switch(MRCC_OSC4M) + { + case MRCC_OSC4M_Default: + MRCC->CLKCTL &= MRCC_OSC4MOFF_Reset_Mask & MRCC_OSC4MBYP_Reset_Mask; + break; + + case MRCC_OSC4M_Disable: + MRCC->CLKCTL &= MRCC_OSC4MBYP_Reset_Mask; + MRCC->CLKCTL |= MRCC_OSC4MOFF_Set_Mask; + break; + + case MRCC_OSC4M_Bypass: + MRCC->CLKCTL &= MRCC_OSC4MOFF_Reset_Mask; + MRCC->CLKCTL |= MRCC_OSC4MBYP_Set_Mask; + break; + + default: + Status = ERROR; + break; + } + } + + return Status; +} + +/******************************************************************************* +* Function Name : MRCC_OSC32KConfig +* Description : Configures the OSC32K oscillator. +* This function must be used when the CK_SYS is not clocked by +* the CK_RTC. +* Input : - MRCC_OSC32K: specifies the new state of the OSC32K oscillator. +* This parameter can be one of the following values: +* - MRCC_OSC32K_Disable: OSC32K disabled +* - MRCC_OSC32K_Enable: OSC32K enabled +* - MRCC_OSC32KBypass: specifies if the OSC32K oscillator is +* bypassed or not. +* This parameter can be one of the following values: +* - MRCC_OSC32KBypass_Disable: OSC32K selected +* - MRCC_OSC32KBypass_Enable: OSC32K bypassed +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Clock configuration succeeded +* - ERROR: Clock configuration failed +*******************************************************************************/ +ErrorStatus MRCC_OSC32KConfig(u32 MRCC_OSC32K, u32 MRCC_OSC32KBypass) +{ +/* If CK_SYS is driven by CK_RTC, exit ---------------------------------------*/ + if(((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET) && + ((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET)) + { + return ERROR; + } +/* Else configure the OSC32KEN and OSC32KBYP bits ----------------------------*/ + else + { + /* Configure OSC32KEN bit */ + if(MRCC_OSC32K == MRCC_OSC32K_Enable) + { + MRCC->PWRCTRL |= MRCC_OSC32K_Enable; + } + else + { + MRCC->PWRCTRL &= MRCC_OSC32K_Disable; + } + + /* Configure OSC32KBYP bit */ + if(MRCC_OSC32KBypass == MRCC_OSC32KBypass_Enable) + { + MRCC->PWRCTRL |= MRCC_OSC32KBypass_Enable; + } + else + { + MRCC->PWRCTRL &= MRCC_OSC32KBypass_Disable; + } + + return SUCCESS; + } +} + +/******************************************************************************* +* Function Name : MRCC_LPOSCConfig +* Description : Enables or disables the LPOSC oscillator. +* This function must be used when the CK_SYS is not clocked by +* the CK_RTC. +* Input : - MRCC_LPOSC: specifies the new state of the LPOSC oscillator. +* This parameter can be one of the following values: +* - MRCC_LPOSC_Disable: LPOSC disabled +* - MRCC_LPOSC_Enable: LPOSC enabled +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Clock configuration succeeded +* - ERROR: Clock configuration failed +*******************************************************************************/ +ErrorStatus MRCC_LPOSCConfig(u32 MRCC_LPOSC) +{ +/* If CK_SYS is driven by CK_RTC or LPOSC is used as CK_RTC clock source, exit*/ + if((((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET) && + ((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET)) || + ((MRCC->PWRCTRL & MRCC_CKRTCSEL_Set_Mask) == MRCC_CKRTC_LPOSC)) + { + return ERROR; + } +/* Else configure the LPOSCEN bit --------------------------------------------*/ + else + { + if(MRCC_LPOSC == MRCC_LPOSC_Enable) + { + MRCC->PWRCTRL |= MRCC_LPOSC_Enable; + } + else + { + MRCC->PWRCTRL &= MRCC_LPOSC_Disable; + } + + return SUCCESS; + } +} + +/******************************************************************************* +* Function Name : MRCC_RTCMConfig +* Description : Enables or disables RTC clock measurement. +* Input : - MRCC_RTCM: specifies whether CK_RTC is connected to TB +* timer IC1 or not. +* This parameter can be one of the following values: +* - MRCC_RTCM_Disable: CK_RTC not connected to TB timer IC1 +* - MRCC_RTCM_Enable: CK_RTC connected to TB timer IC1 +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_RTCMConfig(u32 MRCC_RTCM) +{ + if(MRCC_RTCM == MRCC_RTCM_Enable) + { + MRCC->PWRCTRL |= MRCC_RTCM_Enable; + } + else + { + MRCC->PWRCTRL &= MRCC_RTCM_Disable; + } +} + +/******************************************************************************* +* Function Name : MRCC_SetBuilderCounter +* Description : Sets the builder counter value which defines the delay for +* the 4MHz main oscillator (OSC4M) clock to be stabilized. +* Input : - BuilderCounter: defines the delay for the OSC4M oscillator +* clock to be stabilized. +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_SetBuilderCounter(u8 BuilderCounter) +{ + *(u8 *) 0x60000026 = BuilderCounter; +} + +/******************************************************************************* +* Function Name : MRCC_GetCKSYSCounter +* Description : Gets the result of the delay applied to CK_SYS before +* starting the CPU. +* Input : None +* Output : None +* Return : SCOUNT value. +*******************************************************************************/ +u16 MRCC_GetCKSYSCounter(void) +{ + return((u16)(MRCC->RFSR & 0x0FFF)); +} + +/******************************************************************************* +* Function Name : MRCC_GetFlagStatus +* Description : Checks whether the specified MRCC flag is set or not. +* Input : - MRCC_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - MRCC_FLAG_LOCK: PLL Locked flag +* - MRCC_FLAG_LOCKIF: PLL Lock Interrupt status flag +* - MRCC_FLAG_CKSEL: CK_SYS source staus flag +* - MRCC_FLAG_CKOSCSEL: CK_OSC clock source staus flag +* - MRCC_FLAG_NCKD: No Clock Detected flag +* - MRCC_FLAG_SWR: Software Reset flag +* - MRCC_FLAG_WDGR: Watchdog Reset flag +* - MRCC_FLAG_EXTR: External Reset flag +* - MRCC_FLAG_WKP: Wake-Up flag +* - MRCC_FLAG_STDB: STANDBY flag +* - MRCC_FLAG_BCOUNT: Builder Counter Flag +* - MRCC_FLAG_OSC32KRDY: Oscillator 32K Ready +* - MRCC_FLAG_CKRTCOK: CK_RTC OK +* - MRCC_FLAG_LPDONE: Low Power Bit Sequence has been performed +* - MRCC_FLAG_LP: Low Power Mode Entry +* Output : None +* Return : The new state of MRCC_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus MRCC_GetFlagStatus(u8 MRCC_FLAG) +{ + u32 MRCCReg = 0, FlagPos = 0; + u32 StatusReg = 0; + + /* Get the MRCC register index */ + MRCCReg = MRCC_FLAG >> 5; + + /* Get the flag position */ + FlagPos = MRCC_FLAG & MRCC_FLAG_Mask; + + if(MRCCReg == 1) /* The flag to check is in CLKCTL register */ + { + StatusReg = MRCC->CLKCTL; + } + else if (MRCCReg == 2) /* The flag to check is in RFSR register */ + { + StatusReg = MRCC->RFSR; + } + else if(MRCCReg == 3) /* The flag to check is in PWRCTRL register */ + { + StatusReg = MRCC->PWRCTRL; + } + + if((StatusReg & (1 << FlagPos))!= RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : MRCC_ClearFlag +* Description : Clears the MRCC’s pending flags. +* Input : - MRCC_FLAG: specifies the flag to clear. +* This parameter can be one of the following values: +* - MRCC_FLAG_NCKD: No Clock Detected flag +* - MRCC_FLAG_SWR: Software Reset flag +* - MRCC_FLAG_WDGR: Watchdog Reset flag +* - MRCC_FLAG_EXTR: External Reset flag +* - MRCC_FLAG_WKP: Wake-Up flag +* - MRCC_FLAG_STDB: STANDBY flag +* - MRCC_FLAG_LPDONE: Low Power Bit Sequence has been performed +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_ClearFlag(u8 MRCC_FLAG) +{ + u32 MRCCReg = 0, FlagPos = 0; + + /* Get the MRCC register index */ + MRCCReg = MRCC_FLAG >> 5; + + /* Get the flag position */ + FlagPos = MRCC_FLAG & MRCC_FLAG_Mask; + + if(MRCCReg == 1) /* The flag to clear is in CLKCTL register */ + { + MRCC->CLKCTL &= ~(1 << FlagPos); + } + else if (MRCCReg == 2) /* The flag to clear is in RFSR register */ + { + MRCC->RFSR &= ~(1 << FlagPos); + } + else if(MRCCReg == 3) /* The flag to clear is in PWRCTRL register */ + { + MRCC->PWRCTRL &= ~(1 << FlagPos); + } +} + +/******************************************************************************* +* Function Name : MRCC_GetITStatus +* Description : Checks whether the specified MRCC interrupt has occurred or not. +* Input : - MRCC_IT: specifies the MRCC interrupt source to check. +* This parameter can be one of the following values: +* - MRCC_IT_LOCK: PLL lock interrupt +* - MRCC_IT_NCKD: No Clock detected interrupt +* Output : None +* Return : The new state of MRCC_IT (SET or RESET). +*******************************************************************************/ +ITStatus MRCC_GetITStatus(u32 MRCC_IT) +{ + /* Check the specified interrupt pending bit */ + if((MRCC->CLKCTL & (MRCC_IT >> 1)) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : MRCC_ClearITPendingBit +* Description : Clears the MRCC’s interrupt pending bits. +* Input : - MRCC_IT: specifies the interrupt pending bit to clear. +* This parameter can be any combination of the following +* values: +* - MRCC_IT_LOCK: PLL lock interrupt +* - MRCC_IT_NCKD: No Clock detected interrupt +* Output : None +* Return : None +*******************************************************************************/ +void MRCC_ClearITPendingBit(u32 MRCC_IT) +{ + /* Clear the specified interrupt pending bit */ + MRCC->CLKCTL &= ~(MRCC_IT >> 1); +} + +/******************************************************************************* +* Function Name : MRCC_WaitForOSC4MStartUp +* Description : Waits for OSC4M start-up. +* Input : None +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: OSC4M oscillator is stable and ready to use +* - ERROR: no clock is detected on OSC4M +*******************************************************************************/ +ErrorStatus MRCC_WaitForOSC4MStartUp(void) +{ + u32 StartUpCounter = 0; + + do + { + /* Clear No Clock Detected flag */ + if(MRCC_GetFlagStatus(MRCC_FLAG_NCKD) != RESET) + { + MRCC_ClearFlag(MRCC_FLAG_NCKD); + } + + StartUpCounter++; + + }while((MRCC_GetFlagStatus(MRCC_FLAG_BCOUNT) == RESET)&& + (StartUpCounter != OSC4MStartUp_TimeOut)); + + if(MRCC_GetFlagStatus(MRCC_FLAG_BCOUNT) != RESET) + { + return SUCCESS; + } + else + { + return ERROR; + } +} + +/******************************************************************************* +* Function Name : SetCKSYS_FREEOSC +* Description : Selects FREEOSC as CK_SYS clock source. +* Input : None +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Clock configuration succeeded +* - ERROR: Clock configuration failed +*******************************************************************************/ +static ErrorStatus SetCKSYS_FREEOSC(void) +{ + /* Check if the PLL is enabled */ + if((MRCC->CLKCTL & MRCC_PLLEN_Set_Mask) != RESET) + { + if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) == RESET) + { /* CK_PLL1 used as Ck_SYS clock source*/ + + if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET) + {/* Check if CK_RTC source clock is present*/ + if((MRCC->PWRCTRL & MRCC_CKRTCSEL_Set_Mask) == RESET) + { + /* CK_RTC disabled*/ + return ERROR; + } + } + + /* Select CK_OSC as CK_SYS clock source */ + MRCC->CLKCTL |= MRCC_CKSEL_Set_Mask; + } + + /* Disable PLL */ + MRCC->CLKCTL &= MRCC_PLLEN_Reset_Mask; + } + + /* Select CK_PLL1 as CK_SYS clock source */ + MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask; + + if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) == RESET) + { + return SUCCESS; + } + else + { + return ERROR; + } +} + +/******************************************************************************* +* Function Name : SetCKSYS_OSC4M +* Description : Selects 4MHz main oscillator (OSC4M) as CK_SYS clock source. +* Input : PLL_State: specifies the PLL state. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Clock configuration succeeded +* - ERROR: Clock configuration failed +*******************************************************************************/ +static ErrorStatus SetCKSYS_OSC4M(u32 PLL_State) +{ +/* If OSC4M is not present, exit ---------------------------------------------*/ + if(((MRCC->CLKCTL & MRCC_NCKDF_Set_Mask) != RESET) || + ((MRCC->CLKCTL & MRCC_OSC4MOFF_Set_Mask) != RESET) ) + { + /* OSC4M disabled or OSC4M clock is not present*/ + return ERROR; + } + +/* Else configure CKSEL and CKOSCSEL bits ------------------------------------*/ + if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET) + { /* CK_RTC used as CK_OSC clock */ + + if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET) + { + /* Select CK_PLL1 as CK_SYS clock source */ + MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask; + } + + /* Clear CKOSCSEL bit ----------------------------------------------------*/ + /* Execute CKOSCSEL bit writing sequence */ + WriteCKOSCSELBit(); + + /* Check if CKOSCSEL is set to 0 */ + if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET) + { + return ERROR; + } + } + + /* Select CK_OSC as CK_SYS clock source */ + MRCC->CLKCTL |= MRCC_CKSEL_Set_Mask; + + if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET) + { + if(PLL_State == MRCC_PLL_Disabled) + { + /* Disable PLL */ + MRCC->CLKCTL &= MRCC_PLLEN_Reset_Mask; + } + + return SUCCESS; + } + else + { + return ERROR; + } +} + +/******************************************************************************* +* Function Name : SetCKSYS_OSC4MPLL +* Description : Selects 4MHz main oscillator (OSC4M) followed by PLL as +* CK_SYS clock source. +* Input : PLL_Mul: specifies the PLL factor. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Clock configuration succeeded +* - ERROR: Clock configuration failed +*******************************************************************************/ +static ErrorStatus SetCKSYS_OSC4MPLL(u32 PLL_Mul) +{ + /* Check if 4MHz main oscillator clock is present */ + if(((MRCC->CLKCTL & MRCC_NCKDF_Set_Mask) == RESET) && + ((MRCC->CLKCTL & MRCC_OSC4MOFF_Set_Mask) == RESET)) + { + if(((MRCC->CLKCTL & MRCC_PLLEN_Set_Mask) != RESET) && + ((MRCC->CLKCTL & MRCC_MX_Set_Mask) == PLL_Mul)) + { + /* Select CK_PLL1 as CK_SYS clock source */ + MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask; + + if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) == RESET) + { + return SUCCESS; + } + else + { + return ERROR; + } + } + else + { + /* If CK_RTC is selected as CK_OSC clock source */ + if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET) + { + if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET) + { + /* Clear CKSEL bit */ + MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask; + } + + /* Clear CKOSCSEL bit ------------------------------------------------*/ + /* Execute CKOSCSEL bit writing sequence */ + WriteCKOSCSELBit(); + + /* Check if CKOSCSEL is set to 0 */ + if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET) + { + return ERROR; + } + } + + /* Select CK_OSC as CK_SYS clock source */ + MRCC->CLKCTL |= MRCC_CKSEL_Set_Mask; + + /* Disable PLL */ + MRCC->CLKCTL &= MRCC_PLLEN_Reset_Mask; + + /* Configure PLL factor */ + if(PLL_Mul == MRCC_PLL_Mul_16) + { + MRCC->CLKCTL &= MRCC_MX_Reset_Mask; + } + else if((PLL_Mul == MRCC_PLL_Mul_15) || (PLL_Mul == MRCC_PLL_Mul_14) || + (PLL_Mul == MRCC_PLL_Mul_12)) + { + /* Clear MX[1:0] bits */ + MRCC->CLKCTL &= MRCC_MX_Reset_Mask; + /* Set MX[1:0] bits according to PLL_Mul value */ + MRCC->CLKCTL |= PLL_Mul; + } + + if(Main_Oscillator == 4000000) + {/* 4 MHz external Quartz oscillator used as main oscillator */ + /* Disable Oscillator Divider by 2 */ + MRCC->CLKCTL &= MRCC_XTDIV2_Reset_Mask; + } + else if(Main_Oscillator == 8000000) + {/* 8 MHz external Quartz oscillator used as main oscillator */ + /* Enable Oscillator Divider by 2 */ + MRCC->CLKCTL |= MRCC_XTDIV2_Set_Mask; + } + + /* Enable PLL */ + MRCC->CLKCTL |= MRCC_PLLEN_Set_Mask; + + /* Wait until the PLL is locked */ + while((MRCC->CLKCTL & MRCC_LOCK_Mask) == RESET) + { + /* If OSC4M clock disapear or the PLL is disabled, exit */ + if(((MRCC->CLKCTL & MRCC_NCKDF_Set_Mask) != RESET) || + ((MRCC->CLKCTL & MRCC_PLLEN_Set_Mask) == RESET)) + { + return ERROR; + } + } + + /* Select CK_PLL1 as CK_SYS clock source */ + MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask; + + if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) == RESET) + { + return SUCCESS; + } + else + { + return ERROR; + } + } + } + else + { + /* OSC4M disabled or OSC4M clock is not present*/ + return ERROR; + } +} + +/******************************************************************************* +* Function Name : SetCKSYS_RTC +* Description : Selects RTC clock (CK_RTC) as CK_SYS clock source. +* Input : PLL_State: specifies the PLL state. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Clock configuration succeeded +* - ERROR: Clock configuration failed +*******************************************************************************/ +static ErrorStatus SetCKSYS_RTC(u32 PLL_State) +{ + /* Check if CK_RTC clock is enabled and ready to use */ + if(((MRCC->PWRCTRL & MRCC_CKRTCSEL_Set_Mask) != RESET)|| + ((MRCC->CLKCTL & MRCC_CKRTCOK_Mask) == RESET)) + { +/* Configure CK_RTC as Ck_SYS clock source -----------------------------------*/ + if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) == RESET) + { + /* Select CK_PLL1 as CK_SYS clock source */ + MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask; + + /* Set CKOSCSEL bit ----------------------------------------------------*/ + /* Execute CKOSCSEL bit writing sequence */ + WriteCKOSCSELBit(); + + /* Check if CKOSCSEL is set to 1 */ + if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) == RESET) + { + return ERROR; + } + } + + /* Select CK_OSC as CK_SYS clock source */ + MRCC->CLKCTL |= MRCC_CKSEL_Set_Mask; + + if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET) + { + if(PLL_State == MRCC_PLL_Disabled) + { + /* Disable PLL */ + MRCC->CLKCTL &= MRCC_PLLEN_Reset_Mask; + } + + return SUCCESS; + } + else + { + return ERROR; + } + } + else + { + /* CK_RTC disabled */ + return ERROR; + } +} + +/******************************************************************************* +* Function Name : WriteLPBit +* Description : Executes the Low Power bit writing sequence. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +static void WriteLPBit(void) +{ + u32 Tmp = 0, Tmp1 = 0, Tmp2 = 0; + + /* Clear LP_DONE flag */ + MRCC->PWRCTRL &= MRCC_LPDONE_Reset_Mask; + + Tmp = MRCC->PWRCTRL; + Tmp1 = Tmp | MRCC_LP_Set_Mask; + Tmp2 = Tmp & MRCC_LP_Reset_Mask; + + /* Set LP bit */ + MRCC->PWRCTRL = Tmp1; + + /* Set LP bit */ + MRCC->PWRCTRL = Tmp1; + + /* Reset LP bit */ + MRCC->PWRCTRL = Tmp2; + + /* Set LP bit */ + MRCC->PWRCTRL = Tmp1; + + /* Read LP bit*/ + Tmp = MRCC->PWRCTRL; +} + +/******************************************************************************* +* Function Name : WriteCKOSCSELBit +* Description : Executes the CKOSCSEL bit writing sequence. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +static void WriteCKOSCSELBit(void) +{ + u32 Tmp = 0, Tmp1 = 0, Tmp2 = 0; + + Tmp = MRCC->CLKCTL; + Tmp1 = Tmp | MRCC_CKOSCSEL_Set_Mask; + Tmp2 = Tmp & MRCC_CKOSCSEL_Reset_Mask; + + /* Set CKOSCSEL bit */ + MRCC->CLKCTL = Tmp1; + + /* Set CKOSCSEL bit */ + MRCC->CLKCTL = Tmp1; + + /* Reset CKOSCSEL bit */ + MRCC->CLKCTL = Tmp2; + + /* Set CKOSCSEL bit */ + MRCC->CLKCTL = Tmp1; + + /* Read CKOSCSEL bit */ + Tmp = MRCC->CLKCTL; +} +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_pwm.c b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_pwm.c new file mode 100644 index 000000000..79c15aa5b --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_pwm.c @@ -0,0 +1,1153 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_pwm.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the PWM software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_pwm.h" +#include "75x_mrcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* PWM interrupt masks */ +#define PWM_IT_Clear_Mask 0x7FFF +#define PWM_IT_Enable_Mask 0xEFFF + +/* PWM_CR Masks bit */ +#define PWM_CounterMode_Mask 0xFF8F +#define PWM_DBASE_Mask 0x077F +#define PWM_MasterModeSelection_Mask 0xFC7F + +/* PWM Update flag selection Set/Reset value */ +#define PWM_UFS_Reset 0xFFFE +#define PWM_UFS_Set 0x0001 + +/* PWM Counter value */ +#define PWM_COUNTER_Reset 0x0002 +#define PWM_COUNTER_Start 0x0004 +#define PWM_COUNTER_Stop 0xFFFB + +/* PWM Debug Mode Set/Reset value */ +#define PWM_DBGC_Set 0x0400 +#define PWM_DBGC_Reset 0xFBFF + +/* PWM Output Compare Polarity Set/Reset value */ +#define PWM_OC1P_Set 0x0020 +#define PWM_OC1P_Reset 0xFFDF + +#define PWM_OC1NP_Set 0x0080 +#define PWM_OC1NP_Reset 0xFF7F + +#define PWM_OC2P_Set 0x2000 +#define PWM_OC2P_Reset 0xDFFF + +#define PWM_OC2NP_Set 0x8000 +#define PWM_OC2NP_Reset 0x7FFF + +#define PWM_OC3P_Set 0x0020 +#define PWM_OC3P_Reset 0xFFDF + +#define PWM_OC3NP_Set 0x0080 +#define PWM_OC3NP_Reset 0xFF7F + +/* PWM Output Compare control mode constant */ +#define PWM_OCControl_PWM 0x000C +#define PWM_OCControl_OCToggle 0x0006 +#define PWM_OCControl_OCInactive 0x0004 +#define PWM_OCControl_OCActive 0x0002 +#define PWM_OCControl_OCTiming 0x0000 + +/* PWM Output Compare mode Enable value */ +#define PWM_OC1_Enable 0x0010 +#define PWM_OC2_Enable 0x1000 +#define PWM_OC3_Enable 0x0010 + +#define PWM_OC1_Disable 0xFFEF +#define PWM_OC2_Disable 0xEFFF +#define PWM_OC3_Disable 0xFFEF + +#define PWM_OC1N_Enable 0x0040 +#define PWM_OC2N_Enable 0x4000 +#define PWM_OC3N_Enable 0x0040 + +#define PWM_OC1N_Disable 0xFFBF +#define PWM_OC2N_Disable 0xBFFF +#define PWM_OC3N_Disable 0xFFBF + +/* PWM Output Compare mode Mask value */ +#define PWM_OC1C_Mask 0xFFF1 +#define PWM_OC2C_Mask 0xF1FF +#define PWM_OC3C_Mask 0xFFF1 + +/* PWM Preload bit Set/Reset value */ +#define PWM_PLD1_Set 0x0001 +#define PWM_PLD2_Set 0x0100 +#define PWM_PLD3_Set 0x0001 + +/* PWM OCRM Set/Reset value */ +#define PWM_OCMR_Set 0x0080 +#define PWM_OCMR_Reset 0xFF7F + +/* PWM_DTR bit Masks value */ +#define PWM_DTR_Mask 0xFC00 +#define PWM_LOCK_Mask 0xF3FF + +/* PWM MOE Set value */ +#define PWM_MOE_Set 0x8000 +#define PWM_MOE_Reset 0x7FFF + +/* PWM OSSR bit Set/Reset value */ +#define PWM_OSSR_Set 0x4000 +#define PWM_OSSR_Reset 0xBFFF + +/* Reset Register Masks */ +#define PWM_Prescaler_Reset_Mask 0x0000 +#define PWM_Pulse1_Reset_Mask 0x0000 +#define PWM_Pulse2_Reset_Mask 0x0000 +#define PWM_Pulse3_Reset_Mask 0x0000 +#define PWM_Period_Reset_Mask 0xFFFF +#define PWM_RepetitionCounter_Reset_Mask 0x0000 +#define PWM_DeadTime_Reset_Mask 0x0000 + +/* Private function prototypes -----------------------------------------------*/ +static void OCM_ModuleConfig(PWM_InitTypeDef* PWM_InitStruct); + +/* Private functions ---------------------------------------------------------*/ + +/****************************************************************************** +* Function Name : PWM_DeInit +* Description : Deinitializes PWM peripheral registers to their default reset +* values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void PWM_DeInit(void) +{ + /* Enters and exits the PWM peripheral to and from reset */ + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_PWM,ENABLE); + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_PWM,DISABLE); +} + +/******************************************************************************* +* Function Name : PWM_Init +* Description : Initializes the PWM peripheral according to the specified +* parameters in the PWM_InitStruct . +* Input : PWM_InitStruct: pointer to a PWM_InitTypeDef structure that +* contains the configuration information for the PWM peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void PWM_Init(PWM_InitTypeDef* PWM_InitStruct) +{ + /* Sets the prescaler value */ + PWM->PSC = PWM_InitStruct->PWM_Prescaler; + + /* Selects the counter mode */ + PWM->CR &= PWM_CounterMode_Mask; + PWM->CR |= PWM_InitStruct->PWM_CounterMode; + + /* Sets the period value */ + PWM->ARR = PWM_InitStruct->PWM_Period; + + /* Sets the repetition counter */ + PWM->RCR &= PWM_RepetitionCounter_Reset_Mask; + PWM->RCR |= PWM_InitStruct->PWM_RepetitionCounter; + + /* Configures the PWM according to the PWM_InitTypeDef structure parameters */ + OCM_ModuleConfig(PWM_InitStruct); +} + +/******************************************************************************* +* Function Name : PWM_StructInit +* Description : Fills each PWM_InitStruct member with its default value. +* Input : PWM_InitStruct : pointer to a PWM_InitTypeDef structure which +* will be initialized. +* Output : None +* Return : None. +*******************************************************************************/ +void PWM_StructInit(PWM_InitTypeDef *PWM_InitStruct) +{ + /* Sets the default configuration */ + PWM_InitStruct->PWM_Mode = PWM_Mode_OCTiming; + PWM_InitStruct->PWM_Prescaler = PWM_Prescaler_Reset_Mask; + PWM_InitStruct->PWM_CounterMode = PWM_CounterMode_Up; + PWM_InitStruct->PWM_Period = PWM_Period_Reset_Mask; + PWM_InitStruct->PWM_Complementary = PWM_Complementary_Disable; + PWM_InitStruct->PWM_OCState = PWM_OCState_Disable; + PWM_InitStruct->PWM_OCNState = PWM_OCNState_Disable; + PWM_InitStruct->PWM_Channel = PWM_Channel_1; + PWM_InitStruct->PWM_Pulse1 = PWM_Pulse1_Reset_Mask; + PWM_InitStruct->PWM_Pulse2 = PWM_Pulse2_Reset_Mask; + PWM_InitStruct->PWM_Pulse3 = PWM_Pulse3_Reset_Mask; + PWM_InitStruct->PWM_Polarity1 = PWM_Polarity1_High; + PWM_InitStruct->PWM_Polarity2 = PWM_Polarity2_High; + PWM_InitStruct->PWM_Polarity3 = PWM_Polarity3_High; + PWM_InitStruct->PWM_Polarity1N = PWM_Polarity1N_High; + PWM_InitStruct->PWM_Polarity2N = PWM_Polarity2N_High; + PWM_InitStruct->PWM_Polarity3N = PWM_Polarity3N_High; + PWM_InitStruct->PWM_DTRAccess = PWM_DTRAccess_Disable; + PWM_InitStruct->PWM_DeadTime = PWM_DeadTime_Reset_Mask; + PWM_InitStruct->PWM_Emergency = PWM_Emergency_Disable; + PWM_InitStruct->PWM_LOCKLevel = PWM_LOCKLevel_OFF; + PWM_InitStruct->PWM_OSSIState = PWM_OSSIState_Disable; + PWM_InitStruct->PWM_RepetitionCounter = PWM_RepetitionCounter_Reset_Mask; +} + +/******************************************************************************* +* Function Name : PWM_Cmd +* Description : Enables or disables the PWM peripheral. +* Input : Newstate: new state of the PWM peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void PWM_Cmd(FunctionalState Newstate) +{ + if(Newstate == ENABLE) + { + PWM->CR |= PWM_COUNTER_Start; + } + else + { + PWM->CR &= PWM_COUNTER_Stop; + } +} + +/******************************************************************************* +* Function Name : PWM_CtrlPWMOutputs +* Description : Enables or disables PWM peripheral Main Outputs. +* Input : Newstate: new state of the PWM peripheral Main Outputs. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void PWM_CtrlPWMOutputs(FunctionalState Newstate) +{ + if(Newstate == ENABLE) + { + PWM->DTR |= PWM_MOE_Set; + } + else + { + PWM->DTR &= PWM_MOE_Reset; + } +} + +/******************************************************************************* +* Function Name : PWM_ITConfig +* Description : Enables or disables the PWM interrupts. +* Input : - PWM_IT: specifies the PWM interrupts sources to be enabled +* or disabled. +* This parameter can be any combination of the following values: +* - PWM_IT_OC1: PWM Output Compare 1 Interrupt source +* - PWM_IT_OC2: PWM Output Compare 2 Interrupt source +* - PWM_IT_OC3: PWM Output Compare 3 Interrupt source +* - PWM_IT_Update: PWM update Interrupt source +* - PWM_IT_Emergency: PWM Emergency interrupt source +* - PWM_IT_GlobalUpdate: PWM global update Interrupt +* source +* - Newstate: new state of PWM interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void PWM_ITConfig(u16 PWM_IT, FunctionalState Newstate) +{ + u16 PWM_IT_Enable = 0; + + PWM_IT_Enable = PWM_IT & PWM_IT_Enable_Mask; + + if(Newstate == ENABLE) + { + /* Update interrupt global source: overflow/undeflow, counter reset operation + or slave mode controller in reset mode */ + if ((PWM_IT & PWM_IT_GlobalUpdate) == PWM_IT_GlobalUpdate) + { + PWM->CR &= PWM_UFS_Reset; + } + /* Update interrupt source: counter overflow/underflow */ + else if ((PWM_IT & PWM_IT_Update) == PWM_IT_Update) + { + PWM->CR |= PWM_UFS_Set; + } + /* Select and enable the interrupts requests */ + PWM->RSR |= PWM_IT_Enable; + PWM->RER |= PWM_IT_Enable; + } + /* Disable the interrupts requests */ + else + { + PWM->RSR &= ~PWM_IT_Enable; + PWM->RER &= ~PWM_IT_Enable; + } +} + +/******************************************************************************* +* Function Name : PWM_DMAConfig +* Description : Configures the PWM’s DMA interface. +* Input : - PWM_DMASources: specifies the DMA Request sources. +* This parameter can be any combination of the following values: +* - PWM_DMASource_OC1: PWM Output Compare 1 DMA source +* - PWM_DMASource_OC2: PWM Output Compare 2 DMA source +* - PWM_DMASource_OC3: PWM Output Compare 3 DMA source +* - PWM_DMASource_Update: PWM Update DMA source +* - PWM_OCRMState: the state of output compare request mode. +* This parameter can be one of the following values: +* - PWM_OCRMState_Enable +* - PWM_OCRMState_Disable +* - PWM_DMABase:DMA Base address. +* This parameter can be one of the following values: +* PWM_DMABase_CR, PWM_DMABase_SCR, PWM_DMABase_OMR1, +* PWM_DMABase_OMR2, PWM_DMABase_RSR, PWM_DMABase_RER, +* PWM_DMABase_ISR, PWM_DMABase_CNT, PWM_DMABase_PSC, +* PWM_DMABase_RCR, PWM_DMABase_ARR, PWM_DMABase_OCR1, +* PWM_DMABase_OCR2, PWM_DMABase_OCR3 ,PWM_DMABase_DTR. +* Output : None +* Return : None +*******************************************************************************/ +void PWM_DMAConfig(u16 PWM_DMASources, u16 PWM_OCRMState, u16 PWM_DMABase) +{ + /* Select the DMA requests */ + PWM->RSR &= ~PWM_DMASources; + + /* Sets the OCRM state */ + if(PWM_OCRMState == PWM_OCRMState_Enable) + { + PWM->RSR |= PWM_OCMR_Set; + } + else + { + PWM->RSR &= PWM_OCMR_Reset; + } + + /* Sets the DMA Base address */ + PWM->CR &= PWM_DBASE_Mask; + PWM->CR |= PWM_DMABase; +} + +/******************************************************************************* +* Function Name : PWM_DMACmd +* Description : Enables or disables the PWM’s DMA interface. +* Input : - PWM_DMASources: specifies the DMA Request sources. +* This parameter can be any combination of the following values: +* - PWM_DMASource_OC1: PWM Output Compare 1 DMA source +* - PWM_DMASource_OC2: PWM Output Compare 2 DMA source +* - PWM_DMASource_OC3: PWM Output Compare 3 DMA source +* - PWM_DMASource_Update: PWM Update DMA source +* - Newstate: new state of the DMA Request sources. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void PWM_DMACmd(u16 PWM_DMASources, FunctionalState Newstate) +{ + if(Newstate == ENABLE) + { + PWM->RER |= PWM_DMASources; + } + else + { + PWM->RER &= ~PWM_DMASources; + } +} + +/******************************************************************************* +* Function Name : PWM_SetPrescaler +* Description : Sets the PWM prescaler value. +* Input : Prescaler: PWM prescaler new value. +* Output : None +* Return : None +*******************************************************************************/ +void PWM_SetPrescaler(u16 Prescaler) +{ + PWM->PSC = Prescaler; +} + +/******************************************************************************* +* Function Name : PWM_SetPeriod +* Description : Sets the PWM period value. +* Input : Period: PWM period new value. +* Output : None +* Return : None +*******************************************************************************/ +void PWM_SetPeriod(u16 Period) +{ + PWM->ARR = Period; +} + +/******************************************************************************* +* Function Name : PWM_SetPulse +* Description : Sets the PWM pulse value. +* Input : - PWM_Channel: specifies the PWM channel to be used. +* This parameter can be one of the following values: +* - PWM_Channel_1: PWM Channel 1 is used +* - PWM_Channel_2: PWM Channel 2 is used +* - PWM_Channel_3: PWM Channel 3 is used +* - PWM_Channel_ALL: PWM Channel 1, Channel 2 and 3 are used +* - Pulse: PWM pulse new value. +* Output : None +* Return : None +*******************************************************************************/ +void PWM_SetPulse(u16 PWM_Channel, u16 Pulse) +{ + /* Sets Channel 1 pulse value */ + if(PWM_Channel == PWM_Channel_1) + { + PWM->OCR1 = Pulse; + } + /* Sets Channel 2 pulse value */ + else if(PWM_Channel == PWM_Channel_2) + { + PWM->OCR2 = Pulse; + } + /* Sets Channel 3 pulse value */ + else if(PWM_Channel == PWM_Channel_3) + { + PWM->OCR3 = Pulse; + } + /* Sets Channel 1, Channel 2 and Channel 3 pulse values */ + else if(PWM_Channel == PWM_Channel_ALL) + { + PWM->OCR1 = Pulse; + PWM->OCR2 = Pulse; + PWM->OCR3 = Pulse; + } +} + +/******************************************************************************* +* Function Name : PWM_SetPulse1 +* Description : Sets the PWM Channel 1 pulse value. +* Input : - Pulse: PWM Channel 1 pulse new value. +* Output : None +* Return : None +*******************************************************************************/ +void PWM_SetPulse1(u16 Pulse) +{ + PWM->OCR1 = Pulse; +} + +/******************************************************************************* +* Function Name : PWM_SetPulse2 +* Description : Sets the PWM Channel 2 pulse value. +* Input : - Pulse: PWM Channel 2 pulse new value. +* Output : None +* Return : None +*******************************************************************************/ +void PWM_SetPulse2(u16 Pulse) +{ + PWM->OCR2 = Pulse; +} + +/******************************************************************************* +* Function Name : PWM_SetPulse3 +* Description : Sets the PWM Channel 3 pulse value. +* Input : - Pulse: PWM Channel 3 pulse new value. +* Output : None +* Return : None +*******************************************************************************/ +void PWM_SetPulse3(u16 Pulse) +{ + PWM->OCR3 = Pulse; +} + +/******************************************************************************* +* Function Name : PWM_DebugCmd +* Description : Enables or disables PWM peripheral Debug control. +* Input : Newstate: new state of the PWM Debug control. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void PWM_DebugCmd(FunctionalState Newstate) +{ + if(Newstate == ENABLE) + { + PWM->CR |= PWM_DBGC_Set; + } + else + { + PWM->CR &= PWM_DBGC_Reset; + } +} + +/******************************************************************************* +* Function Name : PWM_CounterModeConfig +* Description : Specifies the Counter Mode to be used. +* Input : PWM_CounterMode: specifies the Counter Mode to be used +* This parameter can be one of the following values: +* - PWM_CounterMode_Up: PWM Up Counting Mode +* - PWM_CounterMode_Down: PWM Down Counting Mode +* - PWM_CounterMode_CenterAligned1: PWM Center Aligned1 Mode +* - PWM_CounterMode_CenterAligned2: PWM Center Aligned2 Mode +* - PWM_CounterMode_CenterAligned3: PWM Center Aligned3 Mode +* Output : None +* Return : None +*******************************************************************************/ +void PWM_CounterModeConfig(u16 PWM_CounterMode) +{ + /* Counter mode configuration */ + PWM->CR &= PWM_CounterMode_Mask; + PWM->CR |= PWM_CounterMode; +} + +/******************************************************************************* +* Function Name : PWM_ForcedOCConfig +* Description : Forces the PWM output waveform to active or inactive level. +* Input : - PWM_Channel: specifies the PWM channel to be used. +* This parameter can be one of the following values: +* - PWM_Channel_1: PWM Channel 1 is used +* - PWM_Channel_2: PWM Channel 2 is used +* - PWM_Channel_3: PWM Channel 3 is used +* - PWM_Channel_ALL: PWM Channel 1, Channel 2 and 3 are used +* - PWM_ForcedAction: specifies the forced Action to be set to the +* output waveform. +* This parameter can be one of the following values: +* - PWM_ForcedAction_Active: Force active level on OCxREF +* - PWM_ForcedAction_InActive: Force inactive level on +* OCxREF +* Output : None +* Return : None +*******************************************************************************/ +void PWM_ForcedOCConfig(u16 PWM_Channel, u16 PWM_ForcedAction) +{ + /* Channel 1 Forced Output Compare mode configuration */ + if(PWM_Channel == PWM_Channel_1) + { + PWM->OMR1 &= PWM_OC1C_Mask; + PWM->OMR1 |= PWM_ForcedAction; + } + /* Channel 2 Forced Output Compare mode configuration */ + else + { + if(PWM_Channel == PWM_Channel_2) + { + PWM->OMR1 &= PWM_OC2C_Mask; + PWM->OMR1 |= (PWM_ForcedAction<<8); + } + else + { + /* Channel 3 Forced Output Compare mode configuration */ + if(PWM_Channel == PWM_Channel_3) + { + PWM->OMR2 &= PWM_OC3C_Mask; + PWM->OMR2 |= PWM_ForcedAction; + } + /* Channel 1, Channel 2 and Channel 3 Forced Output Compare mode + configuration */ + else + { + PWM->OMR1 &= PWM_OC1C_Mask; + PWM->OMR1 |= PWM_ForcedAction; + + PWM->OMR1 &= PWM_OC2C_Mask; + PWM->OMR1 |= (PWM_ForcedAction<<8); + + PWM->OMR2 &= PWM_OC3C_Mask; + PWM->OMR2 |= PWM_ForcedAction; + } + } + } +} + +/******************************************************************************* +* Function Name : PWM_SetDeadTime +* Description : Inserts dead time between the OCx and OCNx. +* Input : DeadTime: PWM Dead Time value. +* Output : None +* Return : None +*******************************************************************************/ +void PWM_SetDeadTime(u16 DeadTime) +{ + /* Sets the dead time value */ + PWM->DTR &= PWM_DTR_Mask; + PWM->DTR |= DeadTime; +} + +/******************************************************************************* +* Function Name : PWM_ResetCounter +* Description : Re-intializes the PWM counter and generates an update of the +* registers. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void PWM_ResetCounter(void) +{ + /* Resets the PWM counter */ + PWM->CR |= PWM_COUNTER_Reset; +} + +/******************************************************************************* +* Function Name : PWM_TRGOSelection +* Description : Sets the PWM Master Mode selection bits. +* Input : PWM_TRGOMode: specifies the TRGO source. +* This parameter can be one of the following values: +* - PWM_TRGOMode_Enable: The CNT_EN bit is used as TRGO +* - PWM_TRGOMode_Update: The Update event is used as TRGO +* - PWM_TRGOMode_Reset: The CNT_RST bit is used as TRGO +* - PWM_TRGOMode_OC: The OC1 signal is used as TRGO +* Output : None +* Return : None +*******************************************************************************/ +void PWM_TRGOSelection(u16 PWM_TRGOMode) +{ + /* Sets the synchronization action */ + PWM->CR &= PWM_MasterModeSelection_Mask; + PWM->CR |= PWM_TRGOMode; +} + +/******************************************************************************* +* Function Name : PWM_GetFlagStatus +* Description : Checks whether the specified PWM flag is set or not. +* Input : PWM_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - PWM_FLAG_OC1: Output Compare 1 Flag +* - PWM_FLAG_OC2: Output Compare 2 Flag +* - PWM_FLAG_OC3: Output Compare 3 Flag +* - PWM_FLAG_Update: PWM update Flag +* - PWM_FLAG_Emergency: PWM Emergency Flag +* Output : None +* Return : The new state of the PWM_FLAG(SET or RESET). +*******************************************************************************/ +FlagStatus PWM_GetFlagStatus(u16 PWM_FLAG) +{ + if((PWM->ISR & PWM_FLAG) != RESET ) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : PWM_ClearFlag +* Description : Clears the PWM’s pending flags. +* Input : PWM_FLAG: specifies the flag to clear. +* This parameter can be any combination of the following values: +* - PWM_FLAG_OC1: Output Compare 1 flag +* - PWM_FLAG_OC2: Output Compare 2 flag +* - PWM_FLAG_OC3: Output Compare 3 flag +* - PWM_FLAG_Update: PWM update flag +* - PWM_FLAG_Emergency: PWM Emergency flag +* Output : None +* Return : None +*******************************************************************************/ +void PWM_ClearFlag(u16 PWM_FLAG) +{ + /* Clears the flags */ + PWM->ISR &= ~PWM_FLAG; +} + +/******************************************************************************* +* Function Name : PWM_GetITStatus +* Description : Checks whether the PWM interrupt has occurred or not. +* Input : PWM_IT: specifies the PWM interrupt source to check. +* This parameter can be one of the following values: +* - PWM_IT_OC1: PWM Output Compare 1 Interrupt source +* - PWM_IT_OC2: PWM Output Compare 2 Interrupt source +* - PWM_IT_OC3: PWM Output Compare 3 Interrupt source +* - PWM_IT_Update: PWM update Interrupt source +* - PWM_IT_Emergency: PWM Emergency interrupt source +* - PWM_IT_GlobalUpdate: PWM global update Interrupt +* source +* Output : None +* Return : The new state of the PWM_IT(SET or RESET). +*******************************************************************************/ +ITStatus PWM_GetITStatus(u16 PWM_IT) +{ + u16 PWM_IT_Check = 0; + + /* Calculates the pending bits to be checked */ + PWM_IT_Check = PWM_IT & PWM_IT_Clear_Mask; + + if((PWM->ISR & PWM_IT_Check) != RESET ) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : PWM_ClearITPendingBit +* Description : Clears the PWM's interrupt pending bits. +* Input : PWM_IT: specifies the pending bit to clear. +* This parameter can be any combination of the following values: +* - PWM_IT_OC1: PWM Output Compare 1 Interrupt source +* - PWM_IT_OC2: PWM Output Compare 2 Interrupt source +* - PWM_IT_OC3: PWM Output Compare 3 Interrupt source +* - PWM_IT_Update: PWM update Interrupt source +* - PWM_IT_Emergency: PWM Emergency interrupt source +* - PWM_IT_GlobalUpdate: PWM global update Interrupt +* source +* Output : None +* Return : None +*******************************************************************************/ +void PWM_ClearITPendingBit(u16 PWM_IT) +{ + u16 PWM_IT_Clear = 0; + + /* Calculates the pending bits to be cleared */ + PWM_IT_Clear = PWM_IT & PWM_IT_Clear_Mask; + + /* Clears the pending bits */ + PWM->ISR &= ~PWM_IT_Clear; + +} + +/******************************************************************************* +* Function Name : OCM_ModuleConfig +* Description : Output Compare Module configuration. +* Input : PWM_InitStruct: pointer to a PWM_InitTypeDef structure that +* contains the configuration information for the PWM peripheral. +* Output : None +* Return : None +*******************************************************************************/ +static void OCM_ModuleConfig(PWM_InitTypeDef* PWM_InitStruct) +{ + u16 PWM_OCControl = 0x0000; + u16 DTR_REG = 0x0000; + + if(PWM_InitStruct->PWM_Mode == PWM_Mode_OCTiming) + { + PWM_OCControl = PWM_OCControl_OCTiming; + } + else + { + if(PWM_InitStruct->PWM_Mode == PWM_Mode_OCActive) + { + PWM_OCControl = PWM_OCControl_OCActive; + } + else + { + if(PWM_InitStruct->PWM_Mode == PWM_Mode_OCInactive) + { + PWM_OCControl = PWM_OCControl_OCInactive; + } + else + { + if(PWM_InitStruct->PWM_Mode == PWM_Mode_OCToggle) + { + PWM_OCControl = PWM_OCControl_OCToggle; + } + else + { + PWM_OCControl = PWM_OCControl_PWM; + + } + } + } + } + + /* Read DTR register */ + DTR_REG = PWM->DTR & 0x8000; + +/*Channel 1 Configuration-----------------------------------------------------*/ + if(PWM_InitStruct->PWM_Channel == PWM_Channel_1) + { + /* PWM Output Complementary Configuration */ + if(PWM_InitStruct->PWM_Complementary == PWM_Complementary_Enable) + { + /* Configures Channel 1 on Output Compare mode */ + PWM->OMR1 &= PWM_OC1C_Mask; + PWM->OMR1 |= PWM_OCControl|PWM_OC1_Enable|PWM_OC1N_Enable|PWM_PLD1_Set; + PWM->OCR1 = PWM_InitStruct->PWM_Pulse1; + + /* Sets the OC1 wave polarity */ + if(PWM_InitStruct->PWM_Polarity1 == PWM_Polarity1_Low) + { + PWM->OMR1 |= PWM_OC1P_Set; + } + else + { + PWM->OMR1 &= PWM_OC1P_Reset; + } + + /* Sets the OC1N wave polarity */ + if(PWM_InitStruct->PWM_Polarity1N == PWM_Polarity1N_Low) + { + PWM->OMR1 |= PWM_OC1NP_Set; + } + else + { + PWM->OMR1 &= PWM_OC1NP_Reset; + } + }/* End complementary case */ + /* Single PWM Output configuratuion */ + else + { + switch(PWM_InitStruct->PWM_OCState) + { + case PWM_OCState_Enable: + { + /* Configures Channel 1 on Output Compare mode */ + PWM->OMR1 &= PWM_OC1C_Mask; + PWM->OMR1 |= PWM_OCControl|PWM_OC1_Enable; + PWM->OMR1 |= PWM_PLD1_Set; + PWM->OCR1 = PWM_InitStruct->PWM_Pulse1; + + /* Sets the OC1 wave polarity */ + if(PWM_InitStruct->PWM_Polarity1 == PWM_Polarity1_Low) + { + PWM->OMR1 |= PWM_OC1P_Set; + } + else + { + PWM->OMR1 &= PWM_OC1P_Reset; + } + } + break; + case PWM_OCState_Disable: + { + /* OC1E = 0 and OSSR = 0 sets the polarity */ + PWM->OMR1 &= PWM_OC1_Disable; + DTR_REG &= PWM_OSSR_Reset; + } + break; + case PWM_OCState_OffState: + { + /* OC1E = 0 and OSSR = 1 and sets the polarity */ + PWM->OMR1 &= PWM_OC1_Disable; + DTR_REG |= PWM_OSSR_Set; + + /* Sets the OC1 wave polarity */ + if(PWM_InitStruct->PWM_Polarity1 == PWM_Polarity1_Low) + { + PWM->OMR1 |= PWM_OC1P_Set; + } + else + { + PWM->OMR1 &= PWM_OC1P_Reset; + } + } + break; + } + + switch(PWM_InitStruct->PWM_OCNState) + { + case PWM_OCNState_Enable: + { + /* Configures Channel 1N on Output Compare mode */ + PWM->OMR1 &= PWM_OC1C_Mask; + PWM->OMR1 |= PWM_OCControl |PWM_OC1N_Enable |PWM_PLD1_Set; + PWM->OCR1 = PWM_InitStruct->PWM_Pulse1; + + /* Sets the OC1N wave polarity */ + if(PWM_InitStruct->PWM_Polarity1N == PWM_Polarity1N_Low) + { + PWM->OMR1 |= PWM_OC1NP_Set; + } + else + { + PWM->OMR1 &= PWM_OC1NP_Reset; + } + } + break; + case PWM_OCNState_Disable: + { + /* OC1N = 0 OSSR = 0 */ + PWM->OMR1 &= PWM_OC1N_Disable; + DTR_REG &= PWM_OSSR_Reset; + } + break; + case PWM_OCNState_OffState: + { + /* OC1N = 0 OSSR = 1 and sets the polarity */ + PWM->OMR1 &= PWM_OC1N_Disable; + DTR_REG |= PWM_OSSR_Set; + + if(PWM_InitStruct->PWM_Polarity1N == PWM_Polarity1N_Low) + { + PWM->OMR1 |= PWM_OC1NP_Set; + } + else + { + PWM->OMR1 &= PWM_OC1NP_Reset; + } + } + break; + } + } /* End not complementary case */ + }/* end channel 1 */ + +/*Channel 2 Configuration-----------------------------------------------------*/ + if(PWM_InitStruct->PWM_Channel == PWM_Channel_2) + { + /* PWM Output Complementary Configuration */ + if(PWM_InitStruct->PWM_Complementary == PWM_Complementary_Enable) + { + /* Configures Channel 2 on Output Compare mode */ + PWM->OMR1 &= PWM_OC2C_Mask; + PWM->OMR1 |= (PWM_OCControl<<8)|PWM_OC2_Enable|PWM_OC2N_Enable|PWM_PLD2_Set; + PWM->OCR2 = PWM_InitStruct->PWM_Pulse2; + + /* Set the OC2 wave polarity */ + if(PWM_InitStruct->PWM_Polarity2 == PWM_Polarity2_Low) + { + PWM->OMR1 |= PWM_OC2P_Set; + } + else + { + PWM->OMR1 &= PWM_OC2P_Reset; + } + + /* Sets the OC2N wave polarity */ + if(PWM_InitStruct->PWM_Polarity2N == PWM_Polarity2N_Low) + { + PWM->OMR1 |= PWM_OC2NP_Set; + } + else + { + PWM->OMR1 &= PWM_OC2NP_Reset; + } + + }/* End complentary case */ + else + /* Single PWM Output configuratuion */ + { + switch(PWM_InitStruct->PWM_OCState) + { + case PWM_OCState_Enable: + { + /* Configures Channel 2 on Output Compare mode */ + PWM->OMR1 &= PWM_OC2C_Mask; + PWM->OMR1 |= (PWM_OCControl<<8)|PWM_OC2_Enable|PWM_PLD2_Set; + PWM->OCR2 = PWM_InitStruct->PWM_Pulse2; + + /* Sets the OC2 wave polarity */ + if(PWM_InitStruct->PWM_Polarity2 == PWM_Polarity2_Low) + { + PWM->OMR1 |= PWM_OC2P_Set; + } + else + { + PWM->OMR1 &= PWM_OC2P_Reset; + } + } + break; + case PWM_OCState_Disable: + { + /* OC2E = 0 and OSSR = 0 */ + PWM->OMR1 &= PWM_OC2_Disable; + DTR_REG &= PWM_OSSR_Reset; + } + break; + case PWM_OCState_OffState: + { + /* OC2E = 0 and OSSR = 1 sets the polarity */ + PWM->OMR1 &= PWM_OC2_Disable; + DTR_REG |= PWM_OSSR_Set; + + /* Sets the OC2 wave polarity */ + if(PWM_InitStruct->PWM_Polarity2 == PWM_Polarity2_Low) + { + PWM->OMR1 |= PWM_OC2P_Set; + } + else + { + PWM->OMR1 &= PWM_OC2P_Reset; + } + } + break; + } + switch(PWM_InitStruct->PWM_OCNState) + { + case PWM_OCNState_Enable: + { + /* Configures Channel 2N on Output Compare mode */ + PWM->OMR1 &= PWM_OC2C_Mask; + PWM->OMR1 |= (PWM_OCControl<<8)|PWM_OC2N_Enable|PWM_PLD2_Set; + PWM->OCR2 = PWM_InitStruct->PWM_Pulse2; + + /* Sets the OC2 wave polarity */ + if(PWM_InitStruct->PWM_Polarity2N == PWM_Polarity2N_Low) + { + PWM->OMR1 |= PWM_OC2NP_Set; + } + else + { + PWM->OMR1 &= PWM_OC2NP_Reset; + } + } + break; + case PWM_OCNState_Disable: + { + /* OC2N = 0 OSSR = 0 */ + PWM->OMR1 &= PWM_OC2N_Disable; + DTR_REG &= PWM_OSSR_Reset; + } + break; + case PWM_OCNState_OffState: + { + /* OC2N = 0 OSSR = 1 and sets the polarity */ + PWM->OMR1 &= PWM_OC2N_Disable; + DTR_REG |= PWM_OSSR_Set; + + if(PWM_InitStruct->PWM_Polarity2N == PWM_Polarity2N_Low) + { + PWM->OMR1 |= PWM_OC2NP_Set; + } + else + { + PWM->OMR1 &= PWM_OC2NP_Reset; + } + } + break; + } + } /* End not complementary case */ + }/* end channel 2 */ + +/*Channel 3 Configuration-----------------------------------------------------*/ + if(PWM_InitStruct->PWM_Channel == PWM_Channel_3) + { + /* PWM Output Complementary Configuration */ + if(PWM_InitStruct->PWM_Complementary == PWM_Complementary_Enable) + { + /* Configures Channel 3 on Output Compare mode */ + PWM->OMR2 &= PWM_OC3C_Mask; + PWM->OMR2 |= PWM_OCControl|PWM_OC3_Enable|PWM_OC3N_Enable|PWM_PLD3_Set; + PWM->OCR3 = PWM_InitStruct->PWM_Pulse3; + + /* Sets the OC3 wave polarity */ + if(PWM_InitStruct->PWM_Polarity3 == PWM_Polarity3_Low) + { + PWM->OMR2 |= PWM_OC3P_Set; + } + else + { + PWM->OMR2 &= PWM_OC3P_Reset; + } + + /* Sets the OC3N wave polarity */ + if(PWM_InitStruct->PWM_Polarity3N == PWM_Polarity3N_Low) + { + PWM->OMR2 |= PWM_OC3NP_Set; + } + else + { + PWM->OMR2 &= PWM_OC3NP_Reset; + } + }/* End complementary case */ + else + /* Single PWM Output configuratuion */ + { + switch(PWM_InitStruct->PWM_OCState) + { + case PWM_OCState_Enable: + { + /* Configures Channel 3 on Output Compare mode */ + PWM->OMR2 &= PWM_OC3C_Mask; + PWM->OMR2 |= PWM_OCControl|PWM_OC3_Enable|PWM_PLD3_Set; + PWM->OCR3 = PWM_InitStruct->PWM_Pulse3; + + /* Sets the OCC wave polarity */ + if(PWM_InitStruct->PWM_Polarity3 == PWM_Polarity3_Low) + { + PWM->OMR2 |= PWM_OC3P_Set; + } + else + { + PWM->OMR2 &= PWM_OC3P_Reset; + } + } + break; + case PWM_OCState_Disable: + { + /* OC3E = 0 and OSSR = 0 */ + PWM->OMR2 &= PWM_OC3_Disable; + DTR_REG &= PWM_OSSR_Reset; + } + break; + case PWM_OCState_OffState: + { + /* OC3E = 0 and OSSR = 1 sets the polarity */ + PWM->OMR2 &= PWM_OC3_Disable; + DTR_REG |= PWM_OSSR_Set; + + if(PWM_InitStruct->PWM_Polarity3 == PWM_Polarity3_Low) + { + PWM->OMR2 |= PWM_OC3P_Set; + } + else + { + PWM->OMR2 &= PWM_OC3P_Reset; + } + } + break; + } + + switch(PWM_InitStruct->PWM_OCNState) + { + case PWM_OCNState_Enable: + { + /* Configures Channel 3N on Output Compare mode */ + PWM->OMR2 &= PWM_OC3C_Mask; + PWM->OMR2 |= PWM_OCControl |PWM_OC3N_Enable|PWM_PLD3_Set; + PWM->OCR3 = PWM_InitStruct->PWM_Pulse3; + + /* Sets the OC3 wave polarity */ + if(PWM_InitStruct->PWM_Polarity3N == PWM_Polarity3N_Low) + { + PWM->OMR2 |= PWM_OC3NP_Set; + } + else + { + PWM->OMR2 &= PWM_OC3NP_Reset; + } + } + break; + case PWM_OCNState_Disable: + { + /* OC3N = 0 OSSR = 0 */ + PWM->OMR2 &= PWM_OC3N_Disable; + DTR_REG &= PWM_OSSR_Reset; + } + break; + case PWM_OCNState_OffState: + { + /* OC3N = 0 OSSR = 1 and sets the polarity */ + PWM->OMR2 &= PWM_OC3N_Disable; + DTR_REG |= PWM_OSSR_Set; + + if(PWM_InitStruct->PWM_Polarity3N == PWM_Polarity3N_Low) + { + PWM->OMR2 |= PWM_OC3NP_Set; + } + else + { + PWM->OMR2 &= PWM_OC3NP_Reset; + } + } + break; + } + } /* End not complementary case */ + }/* end channel 3 */ + + if(PWM_InitStruct->PWM_DTRAccess == PWM_DTRAccess_Enable) + { + DTR_REG |= PWM_InitStruct->PWM_LOCKLevel | PWM_InitStruct->PWM_Emergency | + PWM_InitStruct->PWM_DeadTime | PWM_InitStruct->PWM_OSSIState; + PWM->DTR = DTR_REG; + } +} +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_rtc.c b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_rtc.c new file mode 100644 index 000000000..ab6da500b --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_rtc.c @@ -0,0 +1,326 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_rtc.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the RTC software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_rtc.h" +#include "75x_mrcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define RTC_CNF_Enable_Mask 0x0010 /* Configuration Flag Enable Mask */ +#define RTC_CNF_Disable_Mask 0xFFEF /* Configuration Flag Disable Mask */ +#define RTC_LSB_Mask 0x0000FFFF /* RTC LSB Mask */ +#define RTC_MSB_Mask 0xFFFF0000 /* RTC MSB Mask */ +#define RTC_Prescaler_MSB_Mask 0x000F0000 /* RTC Prescaler MSB Mask */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/******************************************************************************* +* Function Name : RTC_DeInit +* Description : Deinitializes the RTC peripheral registers to their +* default reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RTC_DeInit(void) +{ + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_RTC,ENABLE); + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_RTC,DISABLE); +} + +/******************************************************************************* +* Function Name : RTC_ITConfig +* Description : Enables or disables the specified RTC interrupts. +* Input : - RTC_IT: specifies the RTC interrupts sources to be enabled +* or disabled. +* This parameter can be a combination of one or more of the +* following values: +* - RTC_IT_Overflow: Overflow interrupt +* - RTC_IT_Alarm: Alarm interrupt +* - RTC_IT_Second: Second interrupt +* - NewState: new state of the specified RTC interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void RTC_ITConfig(u16 RTC_IT, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + RTC->CRH |= RTC_IT; + } + else + { + RTC->CRH &= ~RTC_IT; + } +} + +/******************************************************************************* +* Function Name : RTC_EnterConfigMode +* Description : Enters the RTC configuration mode. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RTC_EnterConfigMode(void) +{ + /* Set the CNF flag to enter in the Configuration Mode */ + RTC->CRL |= RTC_CNF_Enable_Mask; +} + +/******************************************************************************* +* Function Name : RTC_ExitConfigMode +* Description : Exits from the RTC configuration mode. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RTC_ExitConfigMode(void) +{ + /* Reset the CNF flag to exit from the Configuration Mode */ + RTC->CRL &= RTC_CNF_Disable_Mask; +} + +/******************************************************************************* +* Function Name : RTC_GetCounter +* Description : Gets the RTC counter value. +* Input : None +* Output : None +* Return : RTC counter value. +*******************************************************************************/ +u32 RTC_GetCounter(void) +{ + u16 Tmp = 0; + Tmp = RTC->CNTL; + + return (((u32)RTC->CNTH << 16 ) |Tmp) ; +} + +/******************************************************************************* +* Function Name : RTC_SetCounter +* Description : Sets the RTC counter value. +* Input : RTC counter new value. +* Output : None +* Return : None +*******************************************************************************/ +void RTC_SetCounter(u32 CounterValue) +{ + RTC_EnterConfigMode(); + +/* COUNTER Config ------------------------------------------------------------*/ + /* Set RTC COUNTER MSB word */ + RTC->CNTH =(CounterValue & RTC_MSB_Mask) >> 16; + /* Set RTC COUNTER LSB word */ + RTC->CNTL =(CounterValue & RTC_LSB_Mask); + + RTC_ExitConfigMode(); +} + +/******************************************************************************* +* Function Name : RTC_SetPrescaler +* Description : Sets the RTC prescaler value. +* Input : RTC prescaler new value. +* Output : None +* Return : None +*******************************************************************************/ +void RTC_SetPrescaler(u32 PrescalerValue) +{ + RTC_EnterConfigMode(); + +/* PRESCALER Config ----------------------------------------------------------*/ + /* Set RTC PRESCALER MSB word */ + RTC->PRLH = (PrescalerValue & RTC_Prescaler_MSB_Mask) >> 16; + /* Set RTC PRESCALER LSB word */ + RTC->PRLL = (PrescalerValue & RTC_LSB_Mask); + + RTC_ExitConfigMode(); +} + +/******************************************************************************* +* Function Name : RTC_GetPrescaler +* Description : Gets the RTC prescaler value. +* Input : None +* Output : None +* Return : RTC prescaler value. +*******************************************************************************/ +u32 RTC_GetPrescaler(void) +{ + u16 Tmp = 0; + Tmp = RTC->PRLL; + + return (((u32)(RTC->PRLH & 0x000F) << 16 ) | Tmp); +} + +/******************************************************************************* +* Function Name : RTC_SetAlarm +* Description : Sets the RTC alarm value. +* Input : RTC alarm new value. +* Output : None +* Return : None +*******************************************************************************/ +void RTC_SetAlarm(u32 AlarmValue) +{ + RTC_EnterConfigMode(); + +/* ALARM Config --------------------------------------------------------------*/ + /* Set the ALARM MSB word */ + RTC->ALRH = (AlarmValue & RTC_MSB_Mask) >> 16; + /* Set the ALARM LSB word */ + RTC->ALRL = (AlarmValue & RTC_LSB_Mask); + + RTC_ExitConfigMode(); +} + +/******************************************************************************* +* Function Name : RTC_GetDivider +* Description : Gets the RTC divider value. +* Input : None +* Output : None +* Return : RTC Divider value. +*******************************************************************************/ +u32 RTC_GetDivider(void) +{ + u16 Tmp = 0; + Tmp = RTC->DIVL ; + return (((u32)(RTC->DIVH & 0x000F) << 16 ) | Tmp); +} + +/******************************************************************************* +* Function Name : RTC_WaitForLastTask +* Description : Waits until last write operation on RTC registers has finished. +* This function must be called before any write to RTC registers. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RTC_WaitForLastTask(void) +{ + /* Loop until RTOFF flag is set */ + while ((RTC->CRL & RTC_FLAG_RTOFF) == RESET); +} + +/******************************************************************************* +* Function Name : RTC_WaitForSynchro +* Description : Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL) +* are synchronized with RTC APB clock. +* This function must be called before any read operation after +* an APB reset or an APB clock stop. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RTC_WaitForSynchro(void) +{ + /* Clear RSF flag */ + RTC->CRL &= ~RTC_FLAG_RSF; + + /* Loop until RSF flag is set */ + while((RTC->CRL & RTC_FLAG_RSF)== RESET); +} + +/******************************************************************************* +* Function Name : RTC_GetFlagStatus +* Description : Checks whether the specified RTC flag is set or not. +* Input : RTC_FLAG: specifies the flag to check. +* This parameter can be one the following values: +* - RTC_FLAG_RTOFF: RTC Operation OFF flag +* - RTC_FLAG_RSF: Registers Synchronized flag +* - RTC_FLAG_Overflow: Overflow interrupt flag +* - RTC_FLAG_Alarm: Alarm interrupt flag +* - RTC_FLAG_Second: Second interrupt flag +* Output : None +* Return : The new state of RTC_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus RTC_GetFlagStatus(u16 RTC_FLAG) +{ + if((RTC->CRL & RTC_FLAG) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : RTC_ClearFlag +* Description : Clears the RTC’s pending flags. +* Input : RTC_FLAG: specifies the flag to clear. +* This parameter can be a combination of one or more of +* the following values: +* - RTC_FLAG_RSF: Registers Synchronized flag. This flag +* is cleared only after an APB reset or an APB Clock stop. +* - RTC_FLAG_Overflow: Overflow interrupt flag +* - RTC_FLAG_Alarm: Alarm interrupt flag +* - RTC_FLAG_Second: Second interrupt flag +* Output : None +* Return : None +*******************************************************************************/ +void RTC_ClearFlag(u16 RTC_FLAG) +{ + /* Clear the coressponding RTC flag */ + RTC->CRL &= ~RTC_FLAG; +} + +/******************************************************************************* +* Function Name : RTC_GetITStatus +* Description : Checks whether the specified RTC interrupt has occured or not. +* Input : RTC_IT: specifies the RTC interrupts sources to check. +* This parameter can be a combination of one or more of +* the following values: +* - RTC_IT_Overflow: Overflow interrupt +* - RTC_IT_Alarm: Alarm interrupt +* - RTC_IT_Second: Second interrupt +* Output : None +* Return : The new state of the RTC_IT (SET or RESET). +*******************************************************************************/ +ITStatus RTC_GetITStatus(u16 RTC_IT) +{ + if(((RTC->CRH & RTC_IT) != RESET)&& ((RTC->CRL & RTC_IT) != RESET)) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : RTC_ClearITPendingBit +* Description : Clears the RTC’s interrupt pending bits. +* Input : RTC_IT: specifies the interrupt pending bit to clear. +* This parameter can be any combination of one or more of +* the following values: +* - RTC_IT_Overflow: Overflow interrupt +* - RTC_IT_Alarm: Alarm interrupt +* - RTC_IT_Second: Second interrupt +* Output : None +* Return : None +*******************************************************************************/ +void RTC_ClearITPendingBit(u16 RTC_IT) +{ + /* Clear the coressponding RTC pending bit */ + RTC->CRL &= ~RTC_IT; +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_smi.c b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_smi.c new file mode 100644 index 000000000..9af53a9e8 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_smi.c @@ -0,0 +1,551 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_smi.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the SMI software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_smi.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* SMI_CR1 mask bits */ +#define SMI_HOLDPRESCTCS_RESET_Mask 0xFF00800F +#define SMI_Prescaler_MaxValue 0x7F +#define SMI_DeselectTime_MaxValue 0x0F +#define SMI_ClockHold_Mask 0x00 +#define SMI_Prescaler_Mask 0x02 +#define SMI_DeselectTime_Mask 0x5 + +/* SMI_CR2 mask bits */ +#define SMI_BS_RESET_Mask 0xFFFFCFFF +#define SMI_BS_Bank1_Mask 0x00001000 +#define SMI_BS_Bank2_Mask 0x00002000 +#define SMI_BS_Bank3_Mask 0x00003000 +#define SMI_WEN_Mask 0x00000800 +#define SMI_RSR_Mask 0x00000400 +#define SMI_SEND_Mask 0x00000080 +#define SMI_TRARECLENGTH_RESET_Mask 0xFFFFFF88 + +/* SMI_SR mask bits */ +#define SMI_STATUSREGISTER_Mask 0xFF + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : SMI_DeInit +* Description : Deinitializes the SMI peripheral registers to their default +* reset values. This function must not be used when booting +* from the SMI external memory. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SMI_DeInit(void) +{ + SMI->CR1 = 0x00000250; + SMI->CR2 = 0x00; + SMI->SR &= 0xFFFFF0FF; + SMI->TR = 0x00; +} + +/******************************************************************************* +* Function Name : SMI_Init +* Description : Initializes the SMI peripheral according to the specified +* parameters in the SMI_InitStruct. +* Input : - SMI_InitStruct: pointer to a SMI_InitTypeDef structure that +* contains the configuration information for the specified +* SMI peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void SMI_Init(SMI_InitTypeDef* SMI_InitStruct) +{ + u32 Temp = 0; + + /* Clear HOLD[7:0], PRESC[6:0] and TCS[3:0] bits */ + Temp = SMI->CR1 & SMI_HOLDPRESCTCS_RESET_Mask; + + /* Set HOLD[7:0] bits according to SMI_ClockHold value */ + Temp |= SMI_InitStruct->SMI_ClockHold << 16; + + if(SMI_InitStruct->SMI_Prescaler <= SMI_Prescaler_MaxValue) + { + /* Set PRESC[6:0] bits according to SMI_Prescaler value */ + Temp |= SMI_InitStruct->SMI_Prescaler << 8; + } + + if(SMI_InitStruct->SMI_DeselectTime <= SMI_DeselectTime_MaxValue) + { + /* Set TCS[3:0] bits according to SMI_DeselectTime value */ + Temp |= SMI_InitStruct->SMI_DeselectTime << 4; + } + + /* Store the new value */ + SMI->CR1 = Temp; +} + +/******************************************************************************* +* Function Name : SMI_StructInit +* Description : Fills each SMI_InitStruct member with its reset value. +* Input : - SMI_InitStruct: pointer to a SMI_InitTypeDef structure which +* will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void SMI_StructInit(SMI_InitTypeDef* SMI_InitStruct) +{ + /* SMI_CK is sent continuously */ + SMI_InitStruct->SMI_ClockHold = SMI_ClockHold_Mask; + + /* SMI_CK = HCLK/2 */ + SMI_InitStruct->SMI_Prescaler = SMI_Prescaler_Mask; + + /* Deselect Time set to 6*SMI_CK periods */ + SMI_InitStruct->SMI_DeselectTime = SMI_DeselectTime_Mask; +} + +/******************************************************************************* +* Function Name : SMI_ModeConfig +* Description : Selects the SMI mode: hardware or software. +* Input : - SMI_Mode: specifies the SMI mode. +* This parameter can be one of the following values: +* - SMI_Mode_HW: SMI in hardware mode +* - SMI_Mode_SW: SMI in software mode +* Output : None +* Return : None +*******************************************************************************/ +void SMI_ModeConfig(u32 SMI_Mode) +{ + if(SMI_Mode == SMI_Mode_SW) + { + SMI->CR1 |= SMI_Mode_SW; + } + else + { + SMI->CR1 &= SMI_Mode_HW; + } +} + +/******************************************************************************* +* Function Name : SMI_TxRxLengthConfig +* Description : Configures the number of bytes to be transmitted and received +* to/from external memory. This function is used in Software +* mode only. +* Input : - SMI_TxLength: specifies the number of bytes to be transmitted +* to external memory. +* This parameter can be one of the following values: +* - SMI_TxLength_0Bytes: No bytes transmitted +* - SMI_TxLength_1Byte: 1 byte transmitted +* - SMI_TxLength_2Bytes: 2 bytes transmitted +* - SMI_TxLength_3Bytes: 3 bytes transmitted +* - SMI_TxLength_4Bytes: 4 bytes transmitted +* - SMI_RxLength: specifies the number of bytes to be received +* from external memory. +* This parameter can be one of the following values: +* - SMI_RxLength_0Bytes: No bytes received +* - SMI_RxLength_1Byte: 1 byte received +* - SMI_RxLength_2Bytes: 2 bytes received +* - SMI_RxLength_3Bytes: 3 bytes received +* - SMI_RxLength_4Bytes: 4 bytes received +* Output : None +* Return : None +*******************************************************************************/ +void SMI_TxRxLengthConfig(u32 SMI_TxLength, u32 SMI_RxLength) +{ + u32 Temp = 0; + + /* Clear TRA_LENGTH[2:0] and REC_LENGTH[2:0] bits */ + Temp = SMI->CR2 & SMI_TRARECLENGTH_RESET_Mask; + + /* Set TRA_LENGTH[2:0] and REC_LENGTH[2:0] bits according to function parameters */ + Temp |= SMI_TxLength | SMI_RxLength; + + /* Store the new value */ + SMI->CR2 = Temp; +} + +/******************************************************************************* +* Function Name : SMI_BankCmd +* Description : Enables or disables the specified memory Bank. +* Input : - SMI_Bank: specifies the memory Bank to be enabled or disabled. +* This parameter can be any combination of the following values: +* - SMI_Bank_0 +* - SMI_Bank_1 +* - SMI_Bank_2 +* - SMI_Bank_3 +* - NewState: new state of the specified memory Bank. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SMI_BankCmd(u32 SMI_Bank, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + SMI->CR1 |= SMI_Bank; + } + else + { + SMI->CR1 &= ~SMI_Bank; + } +} + +/******************************************************************************* +* Function Name : SMI_ITConfig +* Description : Enables or disables the specified SMI interrupts. +* Input : - SMI_IT: specifies the SMI interrupts sources to be +* enabled or disabled. This parameter can be any combination +* of the following values: +* - SMI_IT_WC : Write Complete Interrupt +* - SMI_IT_TF : Transfer Finished Interrupt +* - NewState: new state of the specified SMI interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SMI_ITConfig(u32 SMI_IT, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + SMI->CR2 |= SMI_IT; + } + else + { + SMI->CR2 &= ~SMI_IT; + } +} + +/******************************************************************************* +* Function Name : SMI_SelectBank +* Description : Selects the memory Bank to be accessed. Only one Bank can be +* selected at a time. +* Input : - SMI_Bank: specifies the memory Bank to be selected. +* This parameter can be one of the following values: +* - SMI_Bank_0 +* - SMI_Bank_1 +* - SMI_Bank_2 +* - SMI_Bank_3 +* Output : None +* Return : None +*******************************************************************************/ +void SMI_SelectBank(u32 SMI_Bank) +{ + /* Clear BS[1:0] bits (Bank0 is selected)*/ + SMI->CR2 &= SMI_BS_RESET_Mask; + + switch(SMI_Bank) + { + case SMI_Bank_1: + /* Select Bank1 */ + SMI->CR2 |= SMI_BS_Bank1_Mask; + break; + + case SMI_Bank_2: + /* Select Bank2 */ + SMI->CR2 |= SMI_BS_Bank2_Mask; + break; + + case SMI_Bank_3: + /* Select Bank3 */ + SMI->CR2 |= SMI_BS_Bank3_Mask; + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : SMI_SendWENCmd +* Description : Sends a Write Enable command to the selected memory Bank. +* This function is used in Hardware mode only. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SMI_SendWENCmd(void) +{ + SMI->CR2 |= SMI_WEN_Mask; +} + +/******************************************************************************* +* Function Name : SMI_SendRSRCmd +* Description : Sends a Read Status Register Command to the selected memory +* Bank. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SMI_SendRSRCmd(void) +{ + SMI->CR2 |= SMI_RSR_Mask; +} + +/******************************************************************************* +* Function Name : SMI_SendCmd +* Description : Sends command to the selected memory Bank. This function is +* used in Software mode only. +* Input : - Command: specifies the command to send to the external memory. +* Output : None +* Return : None +*******************************************************************************/ +void SMI_SendCmd(u32 Command) +{ + /* Load the command in the Transmit Register */ + SMI->TR = Command; + + /* Start transfer */ + SMI->CR2 |= SMI_SEND_Mask; +} + +/******************************************************************************* +* Function Name : SMI_FastReadConfig +* Description : Enables or disables the Fast Read Mode. +* Input : - SMI_FastRead: specifies whether the Fast Read Mode is +* enabled or disabled. +* This parameter can be one of the following values: +* - SMI_FastRead_Disable : Fast Read Mode disabled +* - SMI_FastRead_Enable : Fast Read Mode enabled +* Output : None +* Return : None +*******************************************************************************/ +void SMI_FastReadConfig(u32 SMI_FastRead) +{ + if(SMI_FastRead == SMI_FastRead_Enable) + { + SMI->CR1 |= SMI_FastRead_Enable; + } + else + { + SMI->CR1 &= SMI_FastRead_Disable; + } +} + +/******************************************************************************* +* Function Name : SMI_WriteBurstConfig +* Description : Enables or disables the Write Burst Mode. +* Input : - SMI_WriteBurst: specifies whether the Write Burst Mode is +* enabled or disabled. +* This parameter can be one of the following values: +* - SMI_WriteBurst_Disable : Write Burst Mode disabled +* - SMI_WriteBurst_Enable : Write Burst Mode enabled +* Output : None +* Return : None +*******************************************************************************/ +void SMI_WriteBurstConfig(u32 SMI_WriteBurst) +{ + if(SMI_WriteBurst == SMI_WriteBurst_Enable) + { + SMI->CR1 |= SMI_WriteBurst_Enable; + } + else + { + SMI->CR1 &= SMI_WriteBurst_Disable; + } +} + +/******************************************************************************* +* Function Name : SMI_WriteByte +* Description : Writes a Byte to the selected memory Bank. This function is +* used in Hardware mode only. +* Before calling this function, send a Write Enable command to +* the selected memory Bank using SMI_SendWENCmd() function. +* Input : - WriteAddr: external memory address from which the data will +* be written. +* - Data: data to be written to the external memory. +* Output : None +* Return : None +*******************************************************************************/ +void SMI_WriteByte(u32 WriteAddr, u8 Data) +{ + /* Transfer data to the memory */ + *(u8 *) WriteAddr = Data; +} + +/******************************************************************************* +* Function Name : SMI_WriteHalfWord +* Description : Writes a Half Word to the selected memory Bank. This function +* is used in Hardware mode only. +* Before calling this function, send a Write Enable command to +* the selected memory Bank using SMI_SendWENCmd() function. +* Input : - WriteAddr: external memory address from which the data will +* be written. +* - Data: data to be written to the external memory. +* Output : None +* Return : None +*******************************************************************************/ +void SMI_WriteHalfWord(u32 WriteAddr, u16 Data) +{ + /* Transfer data to the memory */ + *(u16 *) WriteAddr = Data; +} + +/******************************************************************************* +* Function Name : SMI_WriteWord +* Description : Writes a Word to the selected memory Bank. This function is +* used in Hardware mode only. +* Before calling this function, send a Write Enable command to +* the selected memory Bank using SMI_SendWENCmd() function. +* Input : - WriteAddr: external memory address from which the data will +* be written. +* - Data: data to be written to the external memory. +* Output : None +* Return : None +*******************************************************************************/ +void SMI_WriteWord(u32 WriteAddr, u32 Data) +{ + /* Transfer data to the memory */ + *(u32 *) WriteAddr = Data; +} + +/******************************************************************************* +* Function Name : SMI_ReadByte +* Description : Reads a Byte from the selected memory Bank. This function is +* used in Hardware mode only. +* Input : - ReadAddr: external memory address to read from. +* Output : None +* Return : Data read from the external memory. +*******************************************************************************/ +u8 SMI_ReadByte(u32 ReadAddr) +{ + return(*(u8 *) ReadAddr); +} + +/******************************************************************************* +* Function Name : SMI_ReadHalfWord +* Description : Reads a Half Word from the selected memory Bank. This function +* is used in Hardware mode only. +* Input : - ReadAddr: external memory address to read from. +* Output : None +* Return : Data read from the external memory. +*******************************************************************************/ +u16 SMI_ReadHalfWord(u32 ReadAddr) +{ + return(*(u16 *) ReadAddr); +} + +/******************************************************************************* +* Function Name : SMI_ReadWord +* Description : Reads a Word from the selected memory Bank. This function is +* used in Hardware mode only. +* Input : - ReadAddr: external memory address to read from. +* Output : None +* Return : Data read from the external memory. +*******************************************************************************/ +u32 SMI_ReadWord(u32 ReadAddr) +{ + return(*(u32 *) ReadAddr); +} + +/******************************************************************************* +* Function Name : SMI_ReadMemoryStatusRegister +* Description : Reads the status register of the memory connected to the +* selected Bank. +* Input : None +* Output : None +* Return : External memory status register value. +*******************************************************************************/ +u8 SMI_ReadMemoryStatusRegister(void) +{ + return((u8) (SMI->SR & SMI_STATUSREGISTER_Mask)); +} + +/******************************************************************************* +* Function Name : SMI_GetFlagStatus +* Description : Checks whether the specified SMI flag is set or not. +* Input : - SMI_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - SMI_FLAG_Bank3_WM : Memory Bank3 Write Mode flag +* - SMI_FLAG_Bank2_WM : Memory Bank2 Write Mode flag +* - SMI_FLAG_Bank1_WM : Memory Bank1 Write Mode flag +* - SMI_FLAG_Bank0_WM : Memory Bank0 Write Mode flag +* - SMI_FLAG_ERF2 : Error Flag 2: Forbidden Write Request +* - SMI_FLAG_ERF1 : Error Flag 1: Forbidden Access +* - SMI_FLAG_WC : Write Complete flag +* - SMI_FLAG_TF : Transfer Finished flag +* Output : None +* Return : The new state of SMI_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus SMI_GetFlagStatus(u32 SMI_FLAG) +{ + if((SMI->SR & SMI_FLAG) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : SMI_ClearFlag +* Description : Clears the SMI’s pending flags. +* Input : - SMI_FLAG: specifies the flag to clear. +* This parameter can be any combination of the following values: +* - SMI_FLAG_ERF2 : Error Flag 2: Forbidden Write Request +* - SMI_FLAG_ERF1 : Error Flag 1: Forbidden Access +* - SMI_FLAG_WC : Write Complete flag +* - SMI_FLAG_TF : Transfer Finished flag +* Output : None +* Return : None +*******************************************************************************/ +void SMI_ClearFlag(u32 SMI_FLAG) +{ + SMI->SR &= ~SMI_FLAG; +} + +/******************************************************************************* +* Function Name : SMI_GetITStatus +* Description : Checks whether the specified SMI interrupt has occurred or not. +* Input : - SMI_FLAG: specifies the interrupt source to check. +* This parameter can be one of the following values: +* - SMI_IT_WC : Write Complete Interrupt +* - SMI_IT_TF : Transfer Finished Interrupt +* Output : None +* Return : The new state of SMI_IT (SET or RESET). +*******************************************************************************/ +ITStatus SMI_GetITStatus(u32 SMI_IT) +{ + if(((SMI->CR2 & SMI_IT) != RESET) && ((SMI->SR & SMI_IT) != RESET)) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : SMI_ClearITPendingBit +* Description : Clears the SMI’s interrupt pending bits. +* Input : - SMI_FLAG: specifies the interrupts sources to clear. +* This parameter can be any combination of the following values: +* - SMI_IT_WC : Write Complete Interrupt +* - SMI_IT_TF : Transfer Finished Interrupt +* Output : None +* Return : None +*******************************************************************************/ +void SMI_ClearITPendingBit(u32 SMI_IT) +{ + SMI->SR &= ~SMI_IT; +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_ssp.c b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_ssp.c new file mode 100644 index 000000000..b4ccd215e --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_ssp.c @@ -0,0 +1,588 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_ssp.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the SSP software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_ssp.h" +#include "75x_mrcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* SSP peripheral Enable */ +#define SSP_Enable 0x0002 +#define SSP_Disable 0xFFFD + +/* SSP Loop Back Mode Enable */ +#define SSP_LoopBackMode_Enable 0x0001 +#define SSP_LoopBackMode_Disable 0xFFFE + +/* SSP Flag Mask */ +#define SSP_Flag_Mask 0x001F + +/* SSP DMA transmit/ receive enable/disable Masks */ +#define SSP0_DMA_TransmitEnable 0x0002 +#define SSP0_DMA_TransmitDisable 0xFFFD +#define SSP0_DMA_ReceiveEnable 0x0001 +#define SSP0_DMA_ReceiveDisable 0xFFFE + +/* SSP Masks */ +#define SSP_FrameFormat_Mask 0xFFCF +#define SSP_DataSize_Mask 0xFFF0 +#define SSP_ClockRate_Mask 0x00FF +#define SSP_ClockPrescaler_Mask 0xFF00 +#define SSP_SSI_Set_Mask 0x0020 +#define SSP_SSI_Reset_Mask 0xFFDF + + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : SSP_DeInit +* Description : Deinitializes the SSPx peripheral registers to their default +* reset values. +* Input : SSPx: where x can be 0 or 1 to select the SSP peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void SSP_DeInit(SSP_TypeDef* SSPx) +{ + if(SSPx == SSP0) + { + /* Reset the SSP0 registers values*/ + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_SSP0,ENABLE); + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_SSP0,DISABLE); + } + else if (SSPx == SSP1) + { + /* Reset the SSP1 registers values*/ + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_SSP1,ENABLE); + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_SSP1,DISABLE); + } +} + +/******************************************************************************* +* Function Name : SSP_Init +* Description : Initializes the SSPx peripheral according to the specified +* parameters in the SSP_InitTypeDef structure. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - SSP_InitStruct: pointer to a SSP_InitTypeDef structure that +* contains the configuration information for the specified SSP +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void SSP_Init(SSP_TypeDef* SSPx, SSP_InitTypeDef* SSP_InitStruct) +{ + /* Configure the Frame format */ + if(SSP_InitStruct->SSP_FrameFormat == SSP_FrameFormat_TI) + { + /* Clear the FRF[1:0] bits */ + SSPx->CR0 &= SSP_FrameFormat_Mask; + /* Set the TI frame format */ + SSPx->CR0 |= SSP_FrameFormat_TI; + } + else + { + /* Set the Motorola frame format */ + SSPx->CR0 &= SSP_FrameFormat_Motorola; + /* Configure the Clock polarity */ + if(SSP_InitStruct->SSP_CPOL == SSP_CPOL_High) + { + /* SCK is held high when no data is being transfered */ + SSPx->CR0 |= SSP_CPOL_High; + } + else + { + /* SCK is held low when no data is being transfered */ + SSPx->CR0 &= SSP_CPOL_Low; + } + /* Configure the Clock Phase */ + if(SSP_InitStruct->SSP_CPHA == SSP_CPHA_2Edge) + { + /* Data captured on second clock edge */ + SSPx->CR0 |= SSP_CPHA_2Edge; + } + else + { + /* Data captured on first clock edge */ + SSPx->CR0 &= SSP_CPHA_1Edge; + } + } + + /* Configure the Mode */ + if(SSP_InitStruct->SSP_Mode == SSP_Mode_Slave) + { + /* Set the slave mode */ + SSPx->CR1 |= SSP_Mode_Slave; + /* Configure the Slave output */ + if(SSP_InitStruct->SSP_SlaveOutput == SSP_SlaveOutput_Disable) + { + /* Slave output disabled */ + SSPx->CR1 |= SSP_SlaveOutput_Disable; + } + else + { + /* Slave output enabled */ + SSPx->CR1 &= SSP_SlaveOutput_Enable; + } + /* Configure the NSS pin */ + if(SSP_InitStruct->SSP_NSS == SSP_NSS_Soft) + { + /* Slave selected by software through SSI bit */ + SSPx->CR1 |= SSP_NSS_Soft; + SSPx->CR1 &= SSP_SSI_Reset_Mask; + } + else + { + /* Slave selected by hardware through external SSpin */ + SSPx->CR1 &= SSP_NSS_Hard; + } + /* Configure the Clock rate and prescaler in TI slave mode */ + if(SSP_InitStruct->SSP_FrameFormat == SSP_FrameFormat_TI) + { + /* Clear clock rate SCR[7:0] bits */ + SSPx->CR0 &= SSP_ClockRate_Mask; + /* Set the serial clock rate */ + SSPx->CR0 |= (SSP_InitStruct->SSP_ClockRate<<8); + /* Clear clock prescaler CPSDVSR[7:0] bits */ + SSPx->PR &= SSP_ClockPrescaler_Mask; + /* Set the serial clock prescaler */ + SSPx->PR |= SSP_InitStruct->SSP_ClockPrescaler; + } + } + else + { + /* Set the master mode */ + SSPx->CR1 &= SSP_Mode_Master; + /* Configure the NSS pin */ + if(SSP_InitStruct->SSP_NSS == SSP_NSS_Soft) + { + /* Master selected by software through SSI bit */ + SSPx->CR1 |= SSP_NSS_Soft; + SSPx->CR1 |= SSP_SSI_Set_Mask; + } + else + { + /* Master selected by hardware through external SSpin */ + SSPx->CR1 &= SSP_NSS_Hard; + } + /* Clear clock rate SCR[7:0] bits */ + SSPx->CR0 &= SSP_ClockRate_Mask; + /* Set the serial clock rate */ + SSPx->CR0 |= (SSP_InitStruct->SSP_ClockRate<<8); + /* Clear clock prescaler CPSDVSR[7:0] bits */ + SSPx->PR &= SSP_ClockPrescaler_Mask; + /* Set the serial clock prescaler */ + SSPx->PR |= SSP_InitStruct->SSP_ClockPrescaler; + } + + /* Clear data size DSS[3:0] bits */ + SSPx->CR0 &= SSP_DataSize_Mask; + /* Set the data size */ + SSPx->CR0 |= SSP_InitStruct->SSP_DataSize; +} + +/******************************************************************************* +* Function Name : SSP_StructInit +* Description : Fills each SSP_InitStruct member with its default value. +* Input : SSP_InitStruct : pointer to a SSP_InitTypeDef structure + which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void SSP_StructInit(SSP_InitTypeDef* SSP_InitStruct) +{ + /* Initialize the SSP_FrameFormat member */ + SSP_InitStruct->SSP_FrameFormat = SSP_FrameFormat_Motorola; + + /* Initialize the SSP_Mode member */ + SSP_InitStruct->SSP_Mode = SSP_Mode_Master; + + /* Initialize the SSP_CPOL member */ + SSP_InitStruct->SSP_CPOL = SSP_CPOL_Low; + + /* Initialize the SSP_CPHA member */ + SSP_InitStruct->SSP_CPHA = SSP_CPHA_1Edge; + + /* Initialize the SSP_DataSize member */ + SSP_InitStruct->SSP_DataSize = SSP_DataSize_8b; + + /* Initialize the SSP_NSS member */ + SSP_InitStruct->SSP_NSS = SSP_NSS_Hard; + + /* Initialize the SSP_SlaveOutput member */ + SSP_InitStruct->SSP_SlaveOutput = SSP_SlaveOutput_Enable; + + /* Initialize the SSP_ClockRate member */ + SSP_InitStruct->SSP_ClockRate = 0; + + /* Initialize the SSP_ClockPrescaler member */ + SSP_InitStruct->SSP_ClockPrescaler = 0; +} + +/******************************************************************************* +* Function Name : SSP_Cmd +* Description : Enables or disables the specified SSP peripheral. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - NewState: new state of the SSPx peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SSP_Cmd(SSP_TypeDef* SSPx, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable the SSP peripheral */ + SSPx->CR1 |= SSP_Enable; + } + else + { + /* Disable the SSP peripheral */ + SSPx->CR1 &= SSP_Disable; + } +} + +/******************************************************************************* +* Function Name : SSP_ITConfig +* Description : Enables or disables the specified SSP interrupts. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - SSP_IT: specifies the SSP interrupts sources to be enabled +* or disabled. This parameter can be any combination of the +* following values: +* - SSP_IT_TxFifo: Transmit FIFO half empty or less interrupt +* - SSP_IT_RxFifo: Receive FIFO half full or less interrupt +* - SSP_IT_RxTimeOut: Receive timeout interrupt +* - SSP_IT_RxOverrun: Receive overrun interrupt +* - NewState: new state of the specified SSP interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SSP_ITConfig(SSP_TypeDef* SSPx, u16 SSP_IT, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable the selected SSP interrupts */ + SSPx->IMSCR |= SSP_IT; + } + else + { + /* Disable the selected SSP interrupts */ + SSPx->IMSCR &= ~SSP_IT; + } +} + +/******************************************************************************* +* Function Name : SSP_DMACmd +* Description : Configures the SSP0 DMA interface. +* Input : - SSP0_DMAtransfer : specifies the DMA transfer to be +* enabled or disabled. This parameter can be one of the +* following values: +* - SSP0_DMA_Transmit: transmit Fifo DMA transfer +* - SSP0_DMA_Receive: receive Fifo DMA transfer +* - NewState: new state of SSP0 DMA transfer. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SSP_DMACmd(u16 SSP0_DMAtransfer, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + if(SSP0_DMAtransfer == SSP0_DMA_Transmit) + { + /* Enable DMA for the transmit FIFO */ + SSP0->DMACR |= SSP0_DMA_TransmitEnable; + } + else + { + /* Enable DMA for the receive FIFO */ + SSP0->DMACR |= SSP0_DMA_ReceiveEnable; + } + } + else + { + if(SSP0_DMAtransfer == SSP0_DMA_Transmit) + { + /* Disable DMA for the transmit FIFO */ + SSP0->DMACR &= SSP0_DMA_TransmitDisable; + } + else + { + /* Disable DMA for the receive FIFO */ + SSP0->DMACR &= SSP0_DMA_ReceiveDisable; + } + } +} + +/******************************************************************************* +* Function Name : SSP_DMATxConfig +* Description : Configures the SSP0 DMA transmit transfer. +* Input : - SSP0_DMATxReq : specifies the SSP0 DMA transmit request to +* be enabled. This parameter can be one of the following +* values: +* - SSP0_DMATxReq_Single: Transmit FIFO DMA single +* request enabled +* - SSP0_DMATxReq_Burst: Transmit FIFO DMA burst request +* enabled +* Output : None +* Return : None +*******************************************************************************/ +void SSP_DMATxConfig(u16 SSP0_DMATxReq) +{ + if(SSP0_DMATxReq == SSP0_DMATxReq_Burst) + { + /* Enable DMA transmit burst request */ + SSP0->DMACR |= SSP0_DMATxReq_Burst; + } + else + { + /* Enable DMA transmit single request */ + SSP0->DMACR &= SSP0_DMATxReq_Single; + } +} + +/******************************************************************************* +* Function Name : SSP_DMARxConfig +* Description : Configures the SSP0 DMA receive transfer. +* Input : - SSP0_DMARxReq : specifies the SSP0 DMA receive request to +* be enabled. This parameter can be one of the following +* values: +* - SSP0_DMARxReq_Single: Receive FIFO DMA burst request +* enabled +* - SSP0_DMARxReq_Burst: Receive FIFO DMA single request +* enabled +* Output : None +* Return : None +*******************************************************************************/ +void SSP_DMARxConfig(u16 SSP0_DMARxReq) +{ + if(SSP0_DMARxReq == SSP0_DMARxReq_Burst) + { + /* Enable DMA receive burst request */ + SSP0->DMACR |= SSP0_DMARxReq_Burst; + } + else + { + /* Enable DMA receive single request */ + SSP0->DMACR &= SSP0_DMARxReq_Single; + } +} + +/******************************************************************************* +* Function Name : SSP_SendData +* Description : Transmits a Data through the SSP peripheral. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - Data : Data to be transmitted. +* Output : None +* Return : None +*******************************************************************************/ +void SSP_SendData(SSP_TypeDef* SSPx, u16 Data) +{ + /* Write in the DR register the data to be sent */ + SSPx->DR = Data; +} + +/******************************************************************************* +* Function Name : SSP_ReceiveData +* Description : Returns the most recent received data by the SSP peripheral. +* Input : SSPx: where x can be 0 or 1 to select the SSP peripheral. +* Output : None +* Return : The value of the received data. +*******************************************************************************/ +u16 SSP_ReceiveData(SSP_TypeDef* SSPx) +{ + /* Return the data in the DR register */ + return SSPx->DR; +} + +/******************************************************************************* +* Function Name : SSP_LoopBackConfig +* Description : Enables or disables the Loop back mode for the selected SSP +* peripheral. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - NewState: new state of the Loop Back mode. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SSP_LoopBackConfig(SSP_TypeDef* SSPx, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable loop back mode */ + SSPx->CR1 |= SSP_LoopBackMode_Enable; + } + else + { + /* Disable loop back mode */ + SSPx->CR1 &= SSP_LoopBackMode_Disable; + } +} + +/******************************************************************************* +* Function Name : SSP_NSSInternalConfig +* Description : Configures by software the NSS pin. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - SSP_NSSState: NSS internal state.This parameter can be one +* of the following values: +* - SSP_NSSInternal_Set: Set NSS pin internally +* - SSP_NSSInternal_Reset: Reset NSS pin internally +* Output : None +* Return : None +*******************************************************************************/ +void SSP_NSSInternalConfig(SSP_TypeDef* SSPx, u16 SSP_NSSState) +{ + if(SSP_NSSState == SSP_NSSInternal_Set) + { + /* Set NSS pin internally */ + SSPx->CR1 |= SSP_NSSInternal_Set; + } + else + { + /* Reset NSS pin internally */ + SSPx->CR1 &= SSP_NSSInternal_Reset; + } +} + +/******************************************************************************* +* Function Name : SSP_GetFlagStatus +* Description : Checks whether the specified SSP flag is set or not. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - SSP_FLAG: specifies the flag to check. This parameter can +* be one of the following values: +* - SSP_FLAG_Busy: busy flag +* - SSP_FLAG_RxFifoFull: Receive FIFO full flag +* - SSP_FLAG_RxFifoNotEmpty: Receive FIFO not empty flag +* - SSP_FLAG_TxFifoNotFull: Transmit FIFO not full flag +* - SSP_FLAG_TxFifoEmpty: Transmit FIFO empty flag +* - SSP_FLAG_TxFifo: Transmit FIFO half empty or less flag +* - SSP_FLAG_RxFifo: Receive FIFO half full or less flag +* - SSP_FLAG_RxTimeOut: Receive timeout flag +* - SSP_FLAG_RxOverrun: Receive overrun flag +* Output : None +* Return : The new state of SSP_FLAG(SET or RESET). +*******************************************************************************/ +FlagStatus SSP_GetFlagStatus(SSP_TypeDef* SSPx, u16 SSP_FLAG) +{ + u32 SSPReg = 0, FlagPos = 0; + u32 StatusReg = 0; + + /* Get the SSP register index */ + SSPReg = SSP_FLAG >> 5; + + /* Get the flag position */ + FlagPos = SSP_FLAG & SSP_Flag_Mask; + + /* Find the register of the flag to check */ + if(SSPReg == 1) + { + /* The flag to check is in SR register */ + StatusReg = SSPx->SR; + } + else if (SSPReg == 2) + { + /* The flag to check is in RISR register */ + StatusReg = SSPx->RISR; + } + + /* Check the status of the specified SSP flag */ + if((StatusReg & (1 << FlagPos)) != RESET) + { + /* Return SET if the SSP flag is set */ + return SET; + } + else + { + /* Return RESET if the SSP flag is reset */ + return RESET; + } +} + +/******************************************************************************* +* Function Name : SSP_ClearFlag +* Description : Clears the SSPx’s pending flags. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - SSP_FLAG: specifies the flag to clear. This parameter can +* be one of the following values: +* - SSP_FLAG_RxTimeOut: Receive timeout flag +* - SSP_FLAG_RxOverrun: Receive overrun flag +* Output : None +* Return : None +*******************************************************************************/ +void SSP_ClearFlag(SSP_TypeDef* SSPx, u16 SSP_FLAG) +{ + u8 FlagPos = 0; + + /* Get the flag position */ + FlagPos = SSP_FLAG & SSP_Flag_Mask; + + /* Clear the selected SSP flag */ + SSPx->ICR = (1 << FlagPos); +} + +/******************************************************************************* +* Function Name : SSP_GetITStatus +* Description : Checks whether the specified SSP interrupt has occurred or not. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - SSP_IT: specifies the interrupt source to check. +* This parameter can be one of the following values: +* - SSP_IT_TxFifo: Transmit FIFO half empty or less interrupt +* - SSP_IT_RxFifo: Receive FIFO half full or less interrupt +* - SSP_IT_RxTimeOut: Receive timeout interrupt +* - SSP_IT_RxOverrun: Receive overrun interrupt +* Output : None +* Return : The new state of SSP_IT(SET or RESET). +*******************************************************************************/ +ITStatus SSP_GetITStatus(SSP_TypeDef* SSPx, u16 SSP_IT) +{ + /* Check the status of the specified interrupt flag */ + if((SSPx->MISR & SSP_IT) != RESET) + { + /* Return SET if the SSP interrupt flag is set */ + return SET; + } + else + { + /* Return RESET if SSP interrupt flag is reset */ + return RESET; + } +} + +/******************************************************************************* +* Function Name : SSP_ClearITPendingBit +* Description : Clears the SSPx’s interrupt pending bits. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - SSP_IT: specifies the interrupt pending bit to clear. +* This parameter can be any combination of the following values: +* - SSP_IT_RxTimeOut: Receive timeout interrupt +* - SSP_IT_RxOverrun: Receive overrun interrupt +* Output : None +* Return : None +*******************************************************************************/ +void SSP_ClearITPendingBit(SSP_TypeDef* SSPx, u16 SSP_IT) +{ + /* Clear the selected SSP interrupts pending bits */ + SSPx->ICR = SSP_IT; +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_tb.c b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_tb.c new file mode 100644 index 000000000..4f461f997 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_tb.c @@ -0,0 +1,425 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_tb.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the TB software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_tb.h" +#include "75x_mrcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +#define TB_IT_Enable_Mask 0x7FFF +#define TB_IT_Clear_Mask 0x7FFF +#define TB_IC_Enable 0x0004 +#define TB_ICPolarity_Set 0x0008 +#define TB_ICPolarity_Reset 0xFFF7 +#define TB_UFS_Reset 0xFFFE +#define TB_UFS_Set 0x0001 + +/* TB debug state */ +#define TB_DBGC_Set 0x0400 +#define TB_DBGC_Reset 0xFB7F + +/* TB counter state */ +#define TB_COUNTER_Reset 0x0002 +#define TB_COUNTER_Start 0x0004 +#define TB_COUNTER_Stop 0xFFFB + +#define TB_SMS_EXTCLK_Set 0x0008 +#define TB_SMS_RESETCLK_Set 0x0000 + +/* TB Slave Mode Enable Set/Reset value */ +#define TB_SME_Reset 0x731B +#define TB_SME_Set 0x0004 + +/* TB Trigger Selection value */ +#define TB_TS_IC1_Set 0x0200 + +/* TB SCR Masks bit */ +#define TB_SlaveModeSelection_Mask 0x7307 +#define TB_TriggerSelection_Mask 0x701F + +/* Reset Register Masks */ +#define TB_Prescaler_Reset_Mask 0x0000 +#define TB_CounterMode_Mask 0xFF8F +#define TB_AutoReload_Reset_Mask 0xFFFF + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + + /****************************************************************************** +* Function Name : TB_DeInit +* Description : Deinitializes the TB peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TB_DeInit(void) +{ + /* Enters and exits the TB peripheral to and from reset */ + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TB,ENABLE); + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TB,DISABLE); +} + +/******************************************************************************* +* Function Name : TB_Init +* Description : Initializes TB peripheral according to the specified +* parameters in the TB_InitStruct. +* Input : TB_InitStruct: pointer to a TB_InitTypeDef structure that +* contains the configuration information for the TB peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TB_Init(TB_InitTypeDef* TB_InitStruct) +{ + /* Set the TB prescaler value */ + TB->PSC = TB_InitStruct->TB_Prescaler; + + /* Set the TB period value */ + TB->ARR = TB_InitStruct->TB_AutoReload; + + /* Set the corresponding counter mode */ + TB->CR = (TB->CR & TB_CounterMode_Mask) | TB_InitStruct->TB_CounterMode; + + /* Set the corresponding clock source */ + if(TB_InitStruct->TB_ClockSource == TB_ClockSource_CKRTC) + { + TB->SCR &= TB_SME_Reset & TB_SlaveModeSelection_Mask & TB_TriggerSelection_Mask; + TB->SCR |= TB_SMS_EXTCLK_Set | TB_SME_Set | TB_TS_IC1_Set; + } + else + { + TB->SCR &= TB_SME_Reset & TB_SlaveModeSelection_Mask & TB_TriggerSelection_Mask; + } + + if(TB_InitStruct->TB_Mode == TB_Mode_IC) + { + /* Set the corresponding value in TB SCR register */ + TB->SCR &= TB_SME_Reset & TB_SlaveModeSelection_Mask & TB_TriggerSelection_Mask; + TB->SCR |= TB_SMS_RESETCLK_Set | TB_SME_Set | TB_TS_IC1_Set; + + /* Set the IC1 enable bit */ + TB->IMCR |= TB_IC_Enable; + + /* Set the input signal polarity */ + if (TB_InitStruct->TB_ICAPolarity == TB_ICAPolarity_Falling) + { + TB->IMCR |= TB_ICPolarity_Set; + } + else + { + TB->IMCR &= TB_ICPolarity_Reset; + } + } +} + +/******************************************************************************* +* Function Name : TB_StructInit +* Description : Fills each TB_InitStruct member with its default value +* Input : TB_InitStruct : pointer to a TB_InitTypeDef structure which +* will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void TB_StructInit(TB_InitTypeDef *TB_InitStruct) +{ + TB_InitStruct->TB_Mode = TB_Mode_Timing; + TB_InitStruct->TB_ClockSource = TB_ClockSource_CKTIM; + TB_InitStruct->TB_CounterMode = TB_CounterMode_Up; + TB_InitStruct->TB_ICAPolarity = TB_ICAPolarity_Rising; + TB_InitStruct->TB_Prescaler = TB_Prescaler_Reset_Mask; + TB_InitStruct->TB_AutoReload = TB_AutoReload_Reset_Mask; +} + +/******************************************************************************* +* Function Name : TB_Cmd +* Description : Enables or disables the TB peripheral. +* Input : Newstate: new state of the TB peripheral. This parameter can +* be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TB_Cmd(FunctionalState Newstate) +{ + if(Newstate == ENABLE) + { + TB->CR |= TB_COUNTER_Start; + } + else + { + TB->CR &= TB_COUNTER_Stop; + } +} + +/******************************************************************************* +* Function Name : TB_ITConfig +* Description : Enables or disables the specified TB interrupt. +* Input : - TB_IT: specifies the TB interrupt sources to be enabled or +* disabled. +* This parameter can be any combination of the following values: +* - TB_IT_Update: TB Update interrupt +* - TB_IT_GlobalUpdate: TB Global Update interrupt +* - TB_IT_IC: TB Input Capture interrupt +* - Newstate: new state of the specified TB interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TB_ITConfig(u16 TB_IT, FunctionalState Newstate) +{ + u16 TB_IT_Enable = 0; + + TB_IT_Enable = TB_IT & TB_IT_Enable_Mask; + + if(Newstate == ENABLE) + { + /* Update interrupt global source: overflow/undeflow, counter reset operation + or slave mode controller in reset mode */ + if ((TB_IT & TB_IT_GlobalUpdate) == TB_IT_GlobalUpdate) + { + TB->CR &= TB_UFS_Reset; + } + /* Update interrupt source: counter overflow/underflow */ + else if ((TB_IT & TB_IT_Update) == TB_IT_Update) + { + TB->CR |= TB_UFS_Set; + } + /* Select and enable the interrupts requests */ + TB->RSR |= TB_IT_Enable; + TB->RER |= TB_IT_Enable; + } + /* Disable the interrupts requests */ + else + { + TB->RSR &= ~TB_IT_Enable; + TB->RER &= ~TB_IT_Enable; + } +} + +/******************************************************************************* +* Function Name : TB_SetPrescaler +* Description : Sets the TB Prescaler value. +* Input : Prescaler: specifies the TB Prescaler value. +* Output : None +* Return : None +*******************************************************************************/ +void TB_SetPrescaler(u16 Prescaler) +{ + /* Sets the prescaler value */ + TB->PSC = Prescaler; +} + +/******************************************************************************* +* Function Name : TB_ResetCounter +* Description : Re-intializes the counter and generates an update of the +* registers. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TB_ResetCounter(void) +{ + /* Re-intializes TB counter */ + TB->CR |= TB_COUNTER_Reset; +} + +/******************************************************************************* +* Function Name : TB_DebugCmd +* Description : Enables or disables TB peripheral Debug control. +* Input : Newstate: new state of the TB Debug control. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TB_DebugCmd(FunctionalState Newstate) +{ + if(Newstate == ENABLE) + { + TB->CR |= TB_DBGC_Set; + } + else + { + TB->CR &= TB_DBGC_Reset; + } +} + +/******************************************************************************* +* Function Name : TB_CounterModeConfig +* Description : Configures the TB Counter Mode. +* Input : TB_CounterMode: specifies the TB counter mode to be used. +* This parameter can be one of the following values: +* - TB_CounterMode_Up: TB Up Counting Mode +* - TB_CounterMode_Down: TB Down Counting Mode +* - TB_CounterMode_CenterAligned: TB Center Aligned Mode +* Output : None +* Return : None +*******************************************************************************/ +void TB_CounterModeConfig(u16 TB_CounterMode) +{ + /* Counter mode configuration */ + TB->CR &= TB_CounterMode_Mask; + TB->CR |= TB_CounterMode; +} + +/******************************************************************************* +* Function Name : TB_SLaveModeConfig +* Description : Configures the TB slave Mode. +* Input : TB_SMSMode: specifies the TB slave mode to be used. +* This parameter can be one of the following values: +* - TB_SMSMode_Trigger: The counter starts at a rising +* edge of the trigger +* - TB_SMSMode_Gated: The counter clock is enabled when +* trigger signal is high +* - TB_SMSMode_External: The rising edge of selected trigger +* clocks the counter +* - TB_SMSMode_Reset: The rising edge of the selected +* trigger signal resets the counter +* Output : None +* Return : None +*******************************************************************************/ +void TB_SLaveModeConfig(u16 TB_SMSMode) +{ + TB->SCR &= TB_SME_Reset & TB_SlaveModeSelection_Mask & TB_TriggerSelection_Mask; + TB->SCR |= TB_SME_Set | TB_SMSMode | TB_TS_IC1_Set; +} +/******************************************************************************* +* Function Name : TB_GetCounter +* Description : Gets the TB Counter value. +* Input : None +* Output : None +* Return : The TB counter register value. +*******************************************************************************/ +u16 TB_GetCounter(void) +{ + return TB->CNT; +} + +/******************************************************************************* +* Function Name : TB_GetICAP1 +* Description : Gets the TB Input capture value. +* Input : None +* Output : None +* Return : The TB ICR1 register value. +*******************************************************************************/ +u16 TB_GetICAP1(void) +{ + return TB->ICR1; +} + +/******************************************************************************* +* Function Name : TB_SetCounter +* Description : Sets the TB Counter value. +* Input : Counter: specifies the TB Counter value. +* Output : None +* Return : None +*******************************************************************************/ +void TB_SetCounter(u16 Counter) +{ + TB->CNT = Counter; +} + +/******************************************************************************* +* Function Name : TB_GetFlagStatus +* Description : Checks whether the specified TB flag is set or not. +* Input : TB_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - TB_FLAG_IC: TB Input Capture flag +* - TB_FLAG_Update: TB update flag +* Output : None +* Return : The new state of the TB_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus TB_GetFlagStatus(u16 TB_FLAG) +{ + if((TB->ISR & TB_FLAG) != RESET ) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : TB_ClearFlag +* Description : Clears the TB’s pending flags. +* Input : TB_FLAG: specifies the flag to clear. +* This parameter can be any combination of the following values: +* - TB_FLAG_IC: TB Input Capture flag +* - TB_FLAG_Update: TB update flag +* Output : None +* Return : None +*******************************************************************************/ +void TB_ClearFlag(u16 TB_FLAG) +{ + /* Clears the flags */ + TB->ISR &= ~TB_FLAG; +} + +/******************************************************************************* +* Function Name : TB_GetITStatus +* Description : Checks whether the specified TB interrupt has occurred or not. +* Input : TB_IT: specifies the interrupt to check. +* This parameter can be one of the following values: +* - TB_IT_Update: TB Update interrupt +* - TB_IT_GlobalUpdate: TB Global Update interrupt +* - TB_IT_IC: TB Input Capture interrupt +* Output : None +* Return : The new state of the TB_IT (SET or RESET). +*******************************************************************************/ +ITStatus TB_GetITStatus(u16 TB_IT) +{ + u16 TB_IT_Check = 0; + + /* Calculates the pending bits to be checked */ + TB_IT_Check = TB_IT & TB_IT_Clear_Mask; + + if((TB->ISR & TB_IT_Check) != RESET ) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : TB_ClearITPendingBit +* Description : Clears the TB's interrupt pending bits. +* Input : TB_IT: specifies the interrupt pending bit to clear. +* This parameter can be any combination of the following values: +* - TB_IT_Update: TB Update interrupt +* - TB_IT_GlobalUpdate: TB Global Update interrupt +* - TB_IT_IC: TB Input Capture interrupt +* Output : None +* Return : None +*******************************************************************************/ +void TB_ClearITPendingBit(u16 TB_IT) +{ + u16 TB_IT_Clear = 0; + + /* Calculates the pending bits to be cleared */ + TB_IT_Clear = TB_IT & TB_IT_Clear_Mask; + + /* Clears the pending bits */ + TB->ISR &= ~TB_IT_Clear; +} +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_tim.c b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_tim.c new file mode 100644 index 000000000..d23d97965 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_tim.c @@ -0,0 +1,1360 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_tim.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the TIM software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_tim.h" +#include "75x_mrcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* TIM interrupt masks */ +#define TIM_IT_Clear_Mask 0x7FFF +#define TIM_IT_Enable_Mask 0x7FFF + +/* TIM Input Capture Selection Set/Reset */ +#define TIM_IC1S_Set 0x0001 +#define TIM_IC1S_Reset 0x003E + +/* TIM Input Capture Selection Set/Reset */ +#define TIM_IC2S_Set 0x0002 +#define TIM_IC2S_Reset 0x003D + +/* TIM_SCR Masks bit */ +#define TIM_Encoder_Mask 0x731C +#define TIM_SlaveModeSelection_Mask 0x7307 +#define TIM_TriggerSelection_Mask 0x701F +#define TIM_InternalTriggerSelection_Mask 0x031F + +/* TIM Encoder mode Set value */ +#define TIM_Encoder1_Set 0x0001 +#define TIM_Encoder2_Set 0x0002 +#define TIM_Encoder3_Set 0x0003 + +/* TIM Slave Mode Enable Set/Reset value */ +#define TIM_SME_Reset 0x731B +#define TIM_SME_Set 0x0004 + +/* TIM Internal Trigger Selection value */ +#define TIM_ITS_TIM0 0x1000 +#define TIM_ITS_TIM1 0x2000 +#define TIM_ITS_TIM2 0x3000 +#define TIM_ITS_PWM 0x4000 + +/* TIM Trigger Selection value */ +#define TIM_TS_IC1_Set 0x0200 +#define TIM_TS_IC2_Set 0x0300 + +/* TIM Slave Mode selction external clock Set value */ +#define TIM_SMS_EXTCLK_Set 0x0008 +#define TIM_SMS_RESETCLK_Set 0x0000 + +/* TIM_CR Masks bit */ +#define TIM_DBASE_Mask 0x077F +#define TIM_MasterModeSelection_Mask 0xFC7F +#define TIM_CounterMode_Mask 0xFF8F + +/* TIM Update flag selection Set/Reset value */ +#define TIM_UFS_Reset 0xFFFE +#define TIM_UFS_Set 0x0001 + +/* TIM Counter value */ +#define TIM_COUNTER_Reset 0x0002 +#define TIM_COUNTER_Start 0x0004 +#define TIM_COUNTER_Stop 0xFFFB + +/* TIM One pulse Mode set value */ +#define TIM_OPM_Set 0x0008 +#define TIM_OPM_Reset 0xFFF7 + +/* TIM Debug Mode Set/Reset value */ +#define TIM_DBGC_Set 0x0400 +#define TIM_DBGC_Reset 0xFB7F + +/* TIM Input Capture Enable/Disable value */ +#define TIM_IC1_Enable 0x0004 +#define TIM_IC2_Enable 0x0010 + +/* TIM Input Capture Polarity Set/Reset value */ +#define TIM_IC1P_Set 0x0008 +#define TIM_IC2P_Set 0x0020 +#define TIM_IC1P_Reset 0x0037 +#define TIM_IC2P_Reset 0x001F + +/* TIM Output Compare Polarity Set/Reset value */ +#define TIM_OC1P_Set 0x0020 +#define TIM_OC2P_Set 0x2000 +#define TIM_OC1P_Reset 0x3F1F +#define TIM_OC2P_Reset 0x1F3F + +/* TIM Output Compare control mode constant */ +#define TIM_OCControl_PWM 0x000C +#define TIM_OCControl_OCToggle 0x0006 +#define TIM_OCControl_OCInactive 0x0004 +#define TIM_OCControl_OCActive 0x0002 +#define TIM_OCControl_OCTiming 0x0000 + +/* TIM Output Compare mode Enable value */ +#define TIM_OC1_Enable 0x0010 +#define TIM_OC2_Enable 0x1000 + +/* TIM Output Compare mode Mask value */ +#define TIM_OC1C_Mask 0x3F31 +#define TIM_OC2C_Mask 0x313F + +/* TIM Preload bit Set/Reset value */ +#define TIM_PLD1_Set 0x0001 +#define TIM_PLD1_Reset 0xFFFE + +#define TIM_PLD2_Set 0x0100 +#define TIM_PLD2_Reset 0xFEFF + +/* TIM OCRM Set/Reset value */ +#define TIM_OCRM_Set 0x0080 +#define TIM_OCRM_Reset 0x030D + +/* Reset Register Masks */ +#define TIM_Pulse2_Reset_Mask 0x0000 +#define TIM_Prescaler_Reset_Mask 0x0000 +#define TIM_Pulse1_Reset_Mask 0x0000 +#define TIM_Period_Reset_Mask 0xFFFF +#define TIM_Counter_Reset 0x0002 + +/* Private function prototypes -----------------------------------------------*/ +static void ICAP_ModuleConfig(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct); +static void Encoder_ModeConfig(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct); +static void OCM_ModuleConfig(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct); + +/* Private functions ---------------------------------------------------------*/ + +/****************************************************************************** +* Function Name : TIM_DeInit +* Description : Deinitializes TIM peripheral registers to their default reset +* values. +* Input : TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_DeInit(TIM_TypeDef *TIMx) +{ + if(TIMx == TIM0) + { + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TIM0,ENABLE); + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TIM0,DISABLE); + } + else if(TIMx == TIM1) + { + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TIM1,ENABLE); + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TIM1,DISABLE); + } + else if(TIMx == TIM2) + { + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TIM2,ENABLE); + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TIM2,DISABLE); + } +} + +/******************************************************************************* +* Function Name : TIM_Init +* Description : Initializes the TIMx peripheral according to the specified +* parameters in the TIM_InitStruct . +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. +* - TIM_InitStruct: pointer to a TIM_InitTypeDef structure that +* contains the configuration information for the specified TIM +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_Init(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct) +{ + /* Set the prescaler value */ + TIMx->PSC = TIM_InitStruct->TIM_Prescaler; + + /* Select the clock source */ + TIM_ClockSourceConfig(TIMx, TIM_InitStruct->TIM_ClockSource, + TIM_InitStruct->TIM_ExtCLKEdge); + + /* Select the counter mode */ + TIMx->CR &= TIM_CounterMode_Mask; + TIMx->CR |= TIM_InitStruct->TIM_CounterMode; + + /* Set the period value */ + TIMx->ARR = TIM_InitStruct->TIM_Period; + + switch(TIM_InitStruct->TIM_Mode) + { + case TIM_Mode_OCTiming: case TIM_Mode_OCActive: case TIM_Mode_OCInactive: + case TIM_Mode_OCToggle: case TIM_Mode_PWM: + OCM_ModuleConfig(TIMx, TIM_InitStruct); + break; + + case TIM_Mode_PWMI: case TIM_Mode_IC: + ICAP_ModuleConfig(TIMx, TIM_InitStruct); + break; + + case TIM_Mode_Encoder1: case TIM_Mode_Encoder2: case TIM_Mode_Encoder3: + Encoder_ModeConfig(TIMx, TIM_InitStruct); + break; + + case TIM_Mode_OPM_PWM: case TIM_Mode_OPM_Toggle: case TIM_Mode_OPM_Active: + + /* Output module configuration */ + OCM_ModuleConfig(TIMx, TIM_InitStruct); + + /* Input module configuration */ + ICAP_ModuleConfig(TIMx, TIM_InitStruct); + + /* Set the slave mode to trigger Mode */ + TIMx->SCR |= TIM_SynchroMode_Trigger; + + /* Repetitive pulse state selection */ + if(TIM_InitStruct->TIM_RepetitivePulse == TIM_RepetitivePulse_Disable) + { + TIMx->CR |= TIM_OPM_Set; + } + else + { + TIMx->CR &= TIM_OPM_Reset; + } + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : TIM_StructInit +* Description : Fills each TIM_InitStruct member with its default value. +* Input : TIM_InitStruct : pointer to a TIM_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None. +*******************************************************************************/ +void TIM_StructInit(TIM_InitTypeDef *TIM_InitStruct) +{ + /* Set the default configuration */ + TIM_InitStruct->TIM_Mode = TIM_Mode_OCTiming; + TIM_InitStruct->TIM_Prescaler = TIM_Prescaler_Reset_Mask; + TIM_InitStruct->TIM_ClockSource = TIM_ClockSource_Internal; + TIM_InitStruct->TIM_ExtCLKEdge = TIM_ExtCLKEdge_Rising; + TIM_InitStruct->TIM_CounterMode = TIM_CounterMode_Up; + TIM_InitStruct->TIM_Period = TIM_Period_Reset_Mask; + TIM_InitStruct->TIM_Channel = TIM_Channel_ALL; + TIM_InitStruct->TIM_Pulse1 = TIM_Pulse1_Reset_Mask; + TIM_InitStruct->TIM_Pulse2 = TIM_Pulse2_Reset_Mask; + TIM_InitStruct->TIM_RepetitivePulse = TIM_RepetitivePulse_Disable; + TIM_InitStruct->TIM_Polarity1 = TIM_Polarity1_Low; + TIM_InitStruct->TIM_Polarity2 = TIM_Polarity2_Low; + TIM_InitStruct->TIM_IC1Selection = TIM_IC1Selection_TI1; + TIM_InitStruct->TIM_IC2Selection = TIM_IC2Selection_TI1; + TIM_InitStruct->TIM_IC1Polarity = TIM_IC1Polarity_Rising; + TIM_InitStruct->TIM_IC2Polarity = TIM_IC2Polarity_Rising; + TIM_InitStruct->TIM_PWMI_ICSelection = TIM_PWMI_ICSelection_TI1; + TIM_InitStruct->TIM_PWMI_ICPolarity = TIM_PWMI_ICPolarity_Rising; +} + +/******************************************************************************* +* Function Name : TIM_Cmd +* Description : Enables or disables the specified TIM peripheral. +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. +* - Newstate: new state of the TIMx peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState Newstate) +{ + if(Newstate == ENABLE) + { + TIMx->CR |= TIM_COUNTER_Start; + } + else + { + TIMx->CR &= TIM_COUNTER_Stop; + } +} + +/******************************************************************************* +* Function Name : TIM_ITConfig +* Description : Enables or disables the TIM interrupts. +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. +* - TIM_IT: specifies the TIM interrupts sources to be enabled +* or disabled. +* This parameter can be any combination of the following values: +* - TIM_IT_IC1: Input Capture 1 Interrupt +* - TIM_IT_OC1: Output Compare 1 Interrupt +* - TIM_IT_Update: Timer update Interrupt +* - TIM_IT_GlobalUpdate: Timer global update Interrupt +* - TIM_IT_IC2: Input Capture 2 Interrupt +* - TIM_IT_OC2: Output Compare 2 Interrupt +* - Newstate: new state of the specified TIMx interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ITConfig(TIM_TypeDef *TIMx, u16 TIM_IT, FunctionalState Newstate) +{ + u16 TIM_IT_Enable = 0; + + TIM_IT_Enable = TIM_IT & TIM_IT_Enable_Mask; + + if(Newstate == ENABLE) + { + /* Update interrupt global source: overflow/undeflow, counter reset operation + or slave mode controller in reset mode */ + if((TIM_IT & TIM_IT_GlobalUpdate) == TIM_IT_GlobalUpdate) + { + TIMx->CR &= TIM_UFS_Reset; + } + /* Update interrupt source: counter overflow/underflow */ + else if((TIM_IT & TIM_IT_Update) == TIM_IT_Update) + { + TIMx->CR |= TIM_UFS_Set; + } + /* Select and enable the interrupts requests */ + TIMx->RSR |= TIM_IT_Enable; + TIMx->RER |= TIM_IT_Enable; + } + /* Disable the interrupts requests */ + else + { + TIMx->RSR &= ~TIM_IT_Enable; + TIMx->RER &= ~TIM_IT_Enable; + } +} + +/******************************************************************************* +* Function Name : TIM_PreloadConfig +* Description : Enables or disables TIM peripheral Preload register on OCRx. +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. +* - TIM_Channel: specifies the TIM channel to be used. +* This parameter can be one of the following values: +* - TIM_Channel_1: TIM Channel 1 is used +* - TIM_Channel_2: TIM Channel 2 is used +* - TIM_Channel_ALL: TIM Channel 1and 2 are used +* - Newstate: new state of the TIMx peripheral Preload register +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_PreloadConfig(TIM_TypeDef *TIMx, u16 TIM_Channel, FunctionalState Newstate) +{ + if(Newstate == ENABLE) + { + switch (TIM_Channel) + { + case TIM_Channel_1: + TIMx->OMR1 |= TIM_PLD1_Set; + break; + + case TIM_Channel_2: + TIMx->OMR1 |= TIM_PLD2_Set; + break; + + case TIM_Channel_ALL: + TIMx->OMR1 |= TIM_PLD1_Set | TIM_PLD2_Set; + break; + + default: + break; + } + } + else + { + switch (TIM_Channel) + { + case TIM_Channel_1: + TIMx->OMR1 &= TIM_PLD1_Reset; + break; + + case TIM_Channel_2: + TIMx->OMR1 &= TIM_PLD2_Reset; + break; + + case TIM_Channel_ALL: + TIMx->OMR1 &= TIM_PLD1_Reset & TIM_PLD2_Reset; + break; + + default: + break; + } + } +} + +/******************************************************************************* +* Function Name : TIM_DMAConfig +* Description : Configures the TIM0’s DMA interface. +* Input : - TIM_DMASources: specifies the DMA Request sources. +* This parameter can be any combination of the following values: +* - TIM_DMASource_OC1: Output Compare 1 DMA source +* - TIM_DMASource_OC2: Output Compare 2 DMA source +* - TIM_DMASource_IC1: Input Capture 1 DMA source +* - TIM_DMASource_IC2: Input Capture 2 DMA source +* - TIM_DMASource_Update: Timer Update DMA source +* - TIM_OCRMState: the state of output compare request mode. +* This parameter can be one of the following values: +* - TIM_OCRMState_Enable +* - TIM_OCRMState_Disable +* - TIM_DMABase:DMA Base address. +* This parameter can be one of the following values: +* TIM_DMABase_CR, TIM_DMABase_SCR, TIM_DMABase_IMCR, +* TIM_DMABase_OMR1, TIM_DMABase_RSR, +* TIM_DMABase_RER, TIM_DMABase_ISR, TIM_DMABase_CNT, +* TIM_DMABase_PSC, TIM_DMABase_ARR, TIM_DMABase_OCR1, +* TIM_DMABase_OCR2, TIM_DMABase_ICR1, TIM_DMABase_ICR2 +* Output : None +* Return : None +*******************************************************************************/ +void TIM_DMAConfig(u16 TIM_DMASources, u16 TIM_OCRMState, u16 TIM_DMABase) +{ + /* Select the DMA requests */ + TIM0->RSR &= TIM_DMASources; + + /* Set the OCRM state */ + if(TIM_OCRMState == TIM_OCRMState_Enable) + { + TIM0->RSR |= TIM_OCRM_Set; + } + else + { + TIM0->RSR &= TIM_OCRM_Reset; + } + + /* Set the DMA Base address */ + TIM0->CR &= TIM_DBASE_Mask; + TIM0->CR |= TIM_DMABase; +} + +/******************************************************************************* +* Function Name : TIM_DMACmd +* Description : Enables or disables the TIM0’s DMA interface. +* Input : - TIM_DMASources: specifies the DMA Request sources. +* This parameter can be any combination of the following values: +* - TIM_DMASource_OC1: Output Compare 1 DMA source +* - TIM_DMASource_OC2: Output Compare 2 DMA source +* - TIM_DMASource_IC1: Input Capture 1 DMA source +* - TIM_DMASource_IC2: Input Capture 2 DMA source +* - TIM_DMASource_Update: Timer Update DMA source +* - Newstate: new state of the DMA Request sources. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_DMACmd(u16 TIM_DMASources, FunctionalState Newstate) +{ + if(Newstate == ENABLE) + { + TIM0->RER |= TIM_DMASources; + } + else + { + TIM0->RER &= ~TIM_DMASources; + } +} + +/******************************************************************************* +* Function Name : TIM_ClockSourceConfig +* Description : Configures the TIM clock source. +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. +* - TIM_ClockSource: specifies the TIM clock source to be +* selected. +* This parameter can be one of the following values: +* - TIM_ClockSource_Internal: CK_TIM internal clock +* - TIM_ClockSource_TI11: External input pin TI1 +* connected to IC1 channel. +* - TIM_ClockSource_TI12: External input pin TI1 +* connected to IC2 channel. +* - TIM_ClockSource_TI22: External input pin TI2 +* connected to IC2 channel. +* - TIM_ClockSource_TI21: External input pin TI2 +* connected to IC1 channel. +* - TIM_ExtCLKEdge: specifies the External input signal edge. +* This parameter can be one of the following values: +* - TIM_ExtCLKEdge_Falling : Falling edge selected. +* - TIM_ExtCLKEdge_Rising : Rising edge selected. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ClockSourceConfig(TIM_TypeDef *TIMx, u16 TIM_ClockSource, + u16 TIM_ExtCLKEdge) +{ + if(TIM_ClockSource == TIM_ClockSource_Internal) + { + /* CK_TIM is used as clock source */ + TIMx->SCR &= TIM_SME_Reset & TIM_SlaveModeSelection_Mask & TIM_TriggerSelection_Mask; + } + else + /* Input Captures are used as TIM external clock */ + { + TIMx->SCR &= TIM_SME_Reset & TIM_SlaveModeSelection_Mask & TIM_TriggerSelection_Mask; + TIMx->SCR |= TIM_SMS_EXTCLK_Set | TIM_SME_Set; + + if((TIM_ClockSource == TIM_ClockSource_TI11) || + (TIM_ClockSource == TIM_ClockSource_TI21)) + /* Input Capture 1 is selected */ + { + /* Input capture Enable */ + TIMx->IMCR |= TIM_IC1_Enable; + TIMx->SCR |= TIM_TS_IC1_Set; + + if(TIM_ExtCLKEdge == TIM_ExtCLKEdge_Falling) + /* Set the corresponding polarity */ + { + TIMx->IMCR |= TIM_IC1P_Set; + } + else + { + TIMx->IMCR &= TIM_IC1P_Reset; + } + if(TIM_ClockSource == TIM_ClockSource_TI11) + { + /* External signal TI1 connected to IC1 channel */ + TIMx->IMCR &= TIM_IC1S_Reset; + } + else + { + /* External signal TI2 connected to IC1 channel */ + TIMx->IMCR |= TIM_IC1S_Set; + } + } + else + /* Input Capture 2 is selected */ + { + /* Input capture Enable */ + TIMx->IMCR |= TIM_IC2_Enable; + TIMx->SCR |= TIM_TS_IC2_Set; + + if(TIM_ExtCLKEdge == TIM_ExtCLKEdge_Falling) + /* Set the corresponding polarity */ + { + TIMx->IMCR |= TIM_IC2P_Set; + } + else + { + TIMx->IMCR &= TIM_IC2P_Reset; + } + if(TIM_ClockSource == TIM_ClockSource_TI22) + { + /* External signal TI2 connected to IC2 channel */ + TIMx->IMCR &= TIM_IC2S_Reset; + } + else + { + /* External signal TI1 connected to IC2 channel */ + TIMx->IMCR |= TIM_IC2S_Set; + } + } + } +} + +/******************************************************************************* +* Function Name : TIM_SetPrescaler +* Description : Sets the TIM prescaler value. +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral +* - Prescaler: TIM prescaler new value. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetPrescaler(TIM_TypeDef* TIMx, u16 Prescaler) +{ + TIMx->PSC = Prescaler; +} + +/******************************************************************************* +* Function Name : TIM_SetPeriod +* Description : Sets the TIM period value. +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral +* - Period: TIM period new value. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetPeriod(TIM_TypeDef* TIMx, u16 Period) +{ + TIMx->ARR = Period; +} + +/******************************************************************************* +* Function Name : TIM_SetPulse +* Description : Sets the TIM pulse value. +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral +* - TIM_Channel: specifies the TIM channel to be used. +* This parameter can be one of the following values: +* - TIM_Channel_1: TIM Channel 1 is used +* - TIM_Channel_2: TIM Channel 2 is used +* - TIM_Channel_ALL: TIM Channel 1and 2 are used +* - Pulse: TIM pulse new value. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetPulse(TIM_TypeDef* TIMx, u16 TIM_Channel, u16 Pulse) +{ + /* Set Channel 1 pulse value */ + if(TIM_Channel == TIM_Channel_1) + { + TIMx->OCR1 = Pulse; + } + /* Set Channel 2 pulse value */ + else if(TIM_Channel == TIM_Channel_2) + { + TIMx->OCR2 = Pulse; + } + /* Set Channel 1 and Channel 2 pulse values */ + else if(TIM_Channel == TIM_Channel_ALL) + { + TIMx->OCR1 = Pulse; + TIMx->OCR2 = Pulse; + } +} + +/******************************************************************************* +* Function Name : TIM_GetICAP1 +* Description : Gets the Input Capture 1 value. +* Input : TIMx: where x can be 0, 1 or 2 to select the TIM peripheral +* Output : None +* Return : Input Capture 1 Register value. +*******************************************************************************/ +u16 TIM_GetICAP1(TIM_TypeDef *TIMx) +{ + return TIMx->ICR1; +} + +/******************************************************************************* +* Function Name : TIM_GetICAP2 +* Description : Gets the Input Capture 2 value. +* Input : TIMx: where x can be 0, 1 or 2 to select the TIM peripheral +* Output : None +* Return : Input Capture 2 Register value +*******************************************************************************/ +u16 TIM_GetICAP2(TIM_TypeDef *TIMx) +{ + return TIMx->ICR2; +} + +/******************************************************************************* +* Function Name : TIM_GetPWMIPulse +* Description : Gets the PWM Input pulse value. +* Input : TIMx: where x can be 0, 1 or 2 to select the TIM peripheral +* Output : None +* Return : Input Capture 2 Register value +*******************************************************************************/ +u16 TIM_GetPWMIPulse(TIM_TypeDef *TIMx) +{ + return TIMx->ICR2; +} + +/******************************************************************************* +* Function Name : TIM_GetPWMIPeriod +* Description : Gets the PWM Input period value. +* Input : TIMx: where x can be 0, 1 or 2 to select the TIM peripheral +* Output : None +* Return : Input Capture 1 Register value +*******************************************************************************/ +u16 TIM_GetPWMIPeriod(TIM_TypeDef *TIMx) +{ + return TIMx->ICR1; +} + +/******************************************************************************* +* Function Name : TIM_DebugCmd +* Description : Enables or disables the specified TIM peripheral Debug control. +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral +* - Newstate: new state of the TIMx Debug control. + This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_DebugCmd(TIM_TypeDef *TIMx, FunctionalState Newstate) +{ + if(Newstate == ENABLE) + { + TIMx->CR |= TIM_DBGC_Set; + } + else + { + TIMx->CR &= TIM_DBGC_Reset; + } +} + +/******************************************************************************* +* Function Name : TIM_CounterModeConfig +* Description : Specifies the Counter Mode to be used. +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. +* - TIM_CounterMode: specifies the Counter Mode to be used +* This parameter can be one of the following values: +* - TIM_CounterMode_Up: TIM Up Counting Mode +* - TIM_CounterMode_Down: TIM Down Counting Mode +* - TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1 +* - TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 +* - TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 +* Output : None +* Return : None +*******************************************************************************/ +void TIM_CounterModeConfig(TIM_TypeDef* TIMx, u16 TIM_CounterMode) +{ + /* Counter mode configuration */ + TIMx->CR &= TIM_CounterMode_Mask; + TIMx->CR |= TIM_CounterMode; +} + +/******************************************************************************* +* Function Name : TIM_ForcedOCConfig +* Description : Forces the TIM output waveform to active or inactive level. +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. +* - TIM_Channel: specifies the TIM channel to be used. +* This parameter can be one of the following values: +* - TIM_Channel_1: Timer Channel 1 is used +* - TIM_Channel_2: Timer Channel 2 is used +* - TIM_Channel_ALL: Timer Channel 1 and 2 are used +* - TIM_ForcedAction: specifies the forced Action to be set to +* the output waveform. +* This parameter can be one of the following values: +* - TIM_ForcedAction_Active: Force active level on OCxREF +* - TIM_ForcedAction_InActive: Force inactive level on +* OCxREF. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ForcedOCConfig(TIM_TypeDef* TIMx, u16 TIM_Channel,u16 TIM_ForcedAction) +{ + /* Channel 1 Forced Output Compare mode configuration */ + if(TIM_Channel == TIM_Channel_1) + { + TIMx->OMR1 &= TIM_OC1C_Mask; + TIMx->OMR1 |= TIM_ForcedAction; + } + /* Channel 2 Forced Output Compare mode configuration */ + else + { + if(TIM_Channel == TIM_Channel_2) + { + TIMx->OMR1 &= TIM_OC2C_Mask; + TIMx->OMR1 |= (TIM_ForcedAction<<8); + } + /* Channel 1 and Channel 2 Forced Output Compare mode configuration */ + else + { + TIMx->OMR1 &= TIM_OC1C_Mask & TIM_OC2C_Mask; + TIMx->OMR1 |= TIM_ForcedAction |(TIM_ForcedAction<<8); + } + } +} + +/******************************************************************************* +* Function Name : TIM_ResetCounter +* Description : Re-intializes the TIM counter and generates an update of the +* registers. +* Input : TIMx: where x can be 0, 1 or 2 to select the TIM peripheral +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ResetCounter(TIM_TypeDef* TIMx) +{ + /* Re-intialize the TIM counter */ + TIMx->CR |= TIM_COUNTER_Reset; +} + +/******************************************************************************* +* Function Name : TIM_SynchroConfig +* Description : Synchronizes two Timers in a specified mode. +* Input : - Master: specifies the peripheral master. +* This parameter can be one of the following values: +* PWM_Master, TIM0_Master, TIM1_Master or TIM2_Master. +* - Slave: specifies the peripheral slave. +* This parameter can be one of the following values: +* PWM_Slave, TIM0_Slave, TIM1_Slave or TIM2_Slave. +* - TIM_SynchroAction: specifies the synchronization Action to +* be used. +* This parameter can be one of the following values: +* - TIM_SynchroAction_Enable: The CNT_EN bit is used as TRGO +* - TIM_SynchroAction_Update: The Update event is used as TRGO +* - TIM_SynchroAction_Reset: The CNT_RST bit is used as TRGO +* - TIM_SynchroAction_OC: The OC1 signal is used as TRGO +* - TIM_SynchroMode: specifies the synchronization Mode to be used. +* This parameter can be one of the following values: +* - TIM_SynchroMode_Gated: Both start and stop of the +* counter is controlled. +* - TIM_SynchroMode_Trigger: Only the start of the +* counter is controlled. +* - TIM_SynchroMode_External: The rising edge of selected trigger +* clocks the counter. +* - TIM_SynchroMode_Reset: The rising edge of the selected trigger +* signal resets the counter and generates an update of the registers. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SynchroConfig(Master_TypeDef Master, Slave_TypeDef Slave, + u16 TIM_SynchroAction, u16 TIM_SynchroMode) +{ + switch (Slave) + { + case PWM_Slave: + { + PWM->SCR &= TIM_SME_Reset & TIM_TriggerSelection_Mask & TIM_SlaveModeSelection_Mask & + TIM_InternalTriggerSelection_Mask; + PWM->SCR |= TIM_SynchroMode | TIM_SME_Set; + + if(Master == TIM1_Master) + { + /* Set the internal trigger */ + PWM->SCR |= TIM_ITS_TIM1; + + /* Set the synchronization action */ + TIM1->CR &= TIM_MasterModeSelection_Mask; + TIM1->CR |= TIM_SynchroAction; + } + + else if(Master == TIM0_Master) + { + /* Set the internal trigger */ + PWM->SCR |= TIM_ITS_TIM0; + + /* Set the synchronization action */ + TIM0->CR &= TIM_MasterModeSelection_Mask; + TIM0->CR |= TIM_SynchroAction; + } + + else if(Master == TIM2_Master) + { + /* Set the internal trigger */ + PWM->SCR |= TIM_ITS_TIM2; + + /* Set the synchronization action */ + TIM2->CR &= TIM_MasterModeSelection_Mask; + TIM2->CR |= TIM_SynchroAction; + } + } + break; + + case TIM0_Slave: + { + TIM0->SCR &= TIM_SME_Reset & TIM_TriggerSelection_Mask & TIM_SlaveModeSelection_Mask & + TIM_InternalTriggerSelection_Mask; + TIM0->SCR |= TIM_SynchroMode | TIM_SME_Set; + + if(Master == PWM_Master) + { + /* Set the internal trigger */ + TIM0->SCR |= TIM_ITS_PWM; + + /* Set the synchronization action */ + PWM->CR &= TIM_MasterModeSelection_Mask; + PWM->CR |= TIM_SynchroAction; + } + + else if(Master == TIM1_Master) + { + /* Set the internal trigger */ + TIM0->SCR |= TIM_ITS_TIM1; + + /* Set the synchronization action */ + TIM1->CR &= TIM_MasterModeSelection_Mask; + TIM1->CR |= TIM_SynchroAction; + } + + else if(Master == TIM2_Master) + { + /* Set the internal trigger */ + TIM0->SCR |= TIM_ITS_TIM2; + + /* Set the synchronization action */ + TIM2->CR &= TIM_MasterModeSelection_Mask; + TIM2->CR |= TIM_SynchroAction; + } + } + break; + + case TIM1_Slave: + { + + TIM1->SCR &= TIM_SME_Reset & TIM_TriggerSelection_Mask & TIM_SlaveModeSelection_Mask & + TIM_InternalTriggerSelection_Mask; + TIM1->SCR |= TIM_SynchroMode | TIM_SME_Set; + + if(Master == PWM_Master) + { + /* Set the internal trigger */ + TIM1->SCR |= TIM_ITS_PWM; + + /* Set the synchronization action */ + PWM->CR &= TIM_MasterModeSelection_Mask; + PWM->CR |= TIM_SynchroAction; + } + else if(Master == TIM0_Master) + { + /* Set the internal trigger */ + TIM1->SCR |= TIM_ITS_TIM0; + + /* Set the synchronization action */ + TIM0->CR &= TIM_MasterModeSelection_Mask; + TIM0->CR |= TIM_SynchroAction; + } + + else if(Master == TIM2_Master) + { + /* Set the internal trigger */ + TIM1->SCR |= TIM_ITS_TIM2; + + /* Set the synchronization action */ + TIM2->CR &= TIM_MasterModeSelection_Mask; + TIM2->CR |= TIM_SynchroAction; + } + } + break; + + case TIM2_Slave: + { + + TIM2->SCR &= TIM_SME_Reset & TIM_TriggerSelection_Mask & TIM_SlaveModeSelection_Mask & + TIM_InternalTriggerSelection_Mask; + TIM2->SCR |= TIM_SynchroMode | TIM_SME_Set; + + if(Master == PWM_Master) + { + /* Internal trigger selection */ + TIM2->SCR |= TIM_ITS_PWM; + + /* Set the synchronization action */ + PWM->CR &= TIM_MasterModeSelection_Mask; + PWM->CR |= TIM_SynchroAction; + } + + else if(Master == TIM1_Master) + { + /* Internal trigger selection */ + TIM2->SCR |= TIM_ITS_TIM1; + + /* Set the synchronization action */ + TIM1->CR &= TIM_MasterModeSelection_Mask; + TIM1->CR |= TIM_SynchroAction; + } + + else if(Master == TIM0_Master) + { + /* Internal trigger selection */ + TIM2->SCR |= TIM_ITS_TIM0; + + /* Set the synchronization action */ + TIM0->CR &= TIM_MasterModeSelection_Mask; + TIM0->CR |= TIM_SynchroAction; + } + } + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : TIM_GetFlagStatus +* Description : Checks whether the specified TIM flag is set or not. +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. +* - TIM_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - TIM_FLAG_IC1: Input Capture 1 Flag +* - TIM_FLAG_OC1: Output Compare 1 Flag +* - TIM_FLAG_Update: Timer update Flag +* - TIM_FLAG_IC2: Input Capture 2 Flag +* - TIM_FLAG_OC2: Output Compare 2 Flag +* Output : None +* Return : The new state of TIM_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, u16 TIM_FLAG) +{ + if((TIMx->ISR & TIM_FLAG) != RESET ) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : TIM_ClearFlag +* Description : Clears the TIMx's pending flags. +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. +* - TIM_FLAG: specifies the flag bit to clear. +* This parameter can be any combination of the following values: +* - TIM_FLAG_IC1: Timer Input Capture 1 flag +* - TIM_FLAG_OC1: Timer Output Compare 1 flag +* - TIM_FLAG_Update: Timer update flag +* - TIM_FLAG_IC2: Timer Input Capture 2 flag +* - TIM_FLAG_OC2: Timer Output Compare 2 flag +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ClearFlag(TIM_TypeDef* TIMx, u16 TIM_FLAG) +{ + /* Clear the flags */ + TIMx->ISR &= ~TIM_FLAG; +} + +/******************************************************************************* +* Function Name : TIM_GetITStatus +* Description : Checks whether the specified TIM interrupt has occurred or not. +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. +* - TIM_IT: specifies the TIM interrupt source to check. +* This parameter can be one of the following values: +* - TIM_IT_IC1: Input Capture 1 interrupt +* - TIM_IT_OC1: Output Compare 1 interrupt +* - TIM_IT_Update: Timer update interrupt +* - TIM_IT_GlobalUpdate: Timer global update interrupt +* - TIM_IT_IC2: Input Capture 2 interrupt +* - TIM_IT_OC2: Output Compare 2 interrupt +* Output : None +* Return : The new state of TIM_IT(SET or RESET). +*******************************************************************************/ +ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, u16 TIM_IT) +{ + u16 TIM_IT_Check = 0; + + /* Calculates the pending bits to be checked */ + TIM_IT_Check = TIM_IT & TIM_IT_Clear_Mask; + + if((TIMx->ISR & TIM_IT_Check) != RESET ) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : TIM_ClearITPendingBit +* Description : Clears the TIM's interrupt pending bits. +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. +* - TIM_IT: specifies the interrupt pending bit to clear. +* This parameter can be one of the following values: +* - TIM_IT_IC1: Input Capture 1 Interrupt +* - TIM_IT_OC1: Output Compare 1 Interrupt +* - TIM_IT_Update: Timer update Interrupt +* - TIM_IT_GlobalUpdate: Timer global update Interrupt +* - TIM_IT_IC2: Input Capture 2 Interrupt +* - TIM_IT_OC2: Output Compare 2 Interrupt +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, u16 TIM_IT) +{ + u16 TIM_IT_Clear = 0; + + /* Calculate the pending bits to be cleared */ + TIM_IT_Clear = TIM_IT & TIM_IT_Clear_Mask; + + /* Clear the pending bits */ + TIMx->ISR &= ~TIM_IT_Clear; +} + +/******************************************************************************* +* Function Name : OCM_ModuleConfig +* Description : Output Compare Module configuration +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral +* - TIM_InitStruct: pointer to a TIM_InitTypeDef structure that +* contains the configuration information for the specified TIM +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +static void OCM_ModuleConfig(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct) +{ + u16 TIM_OCControl = 0x0000; + + if(TIM_InitStruct->TIM_Mode == TIM_Mode_OCTiming) + { + TIM_OCControl = TIM_OCControl_OCTiming; + } + else + { + if((TIM_InitStruct->TIM_Mode == TIM_Mode_OCActive) || + (TIM_InitStruct->TIM_Mode == TIM_Mode_OPM_Active)) + { + TIM_OCControl = TIM_OCControl_OCActive; + } + else + { + if(TIM_InitStruct->TIM_Mode == TIM_Mode_OCInactive) + { + TIM_OCControl = TIM_OCControl_OCInactive; + } + else + { + if((TIM_InitStruct->TIM_Mode == TIM_Mode_OCToggle) || + (TIM_InitStruct->TIM_Mode == TIM_Mode_OPM_Toggle)) + { + TIM_OCControl = TIM_OCControl_OCToggle; + } + else + { + TIM_OCControl = TIM_OCControl_PWM; + + } + } + } + } + + if(TIM_InitStruct->TIM_Channel == TIM_Channel_1) + { + /* Configure Channel 1 on Output Compare mode */ + TIMx->OMR1 &= TIM_OC1C_Mask; + TIMx->OMR1 |= TIM_OCControl|TIM_OC1_Enable; + TIMx->OMR1 |= TIM_PLD1_Set; + TIMx->OCR1 = TIM_InitStruct->TIM_Pulse1; + + /* Set the OC1 wave polarity */ + if(TIM_InitStruct->TIM_Polarity1 == TIM_Polarity1_Low) + { + TIMx->OMR1 |= TIM_OC1P_Set; + } + else + { + TIMx->OMR1 &= TIM_OC1P_Reset; + } + } + else + { + if(TIM_InitStruct->TIM_Channel == TIM_Channel_2) + { + /* Configure Channel 2 on Output Compare mode */ + TIMx->OMR1 &= TIM_OC2C_Mask; + TIMx->OMR1 |= TIM_OCControl<<8|TIM_OC2_Enable; + TIMx->OMR1 |= TIM_PLD2_Set; + TIMx->OCR2 = TIM_InitStruct->TIM_Pulse2; + + /* Set the OCB wave polarity */ + if(TIM_InitStruct->TIM_Polarity2 == TIM_Polarity2_Low) + { + TIMx->OMR1 |= TIM_OC2P_Set; + } + else + { + TIMx->OMR1 &= TIM_OC2P_Reset; + } + } + /* Configure Channel 1 and Channel 2 on Output Compare mode */ + else + { + TIMx->OMR1 &= TIM_OC1C_Mask & TIM_OC2C_Mask; + TIMx->OMR1 |= TIM_OCControl|(TIM_OCControl<<8)|TIM_OC1_Enable|TIM_OC2_Enable| + TIM_PLD1_Set|TIM_PLD2_Set; + + TIMx->OCR1 = TIM_InitStruct->TIM_Pulse1; + TIMx->OCR2 = TIM_InitStruct->TIM_Pulse2; + + /* Set the OC1 wave polarity */ + if(TIM_InitStruct->TIM_Polarity1 == TIM_Polarity1_Low) + { + TIMx->OMR1 |= TIM_OC1P_Set; + } + else + { + TIMx->OMR1 &= TIM_OC1P_Reset; + } + + /* Set the OC2 wave polarity */ + if(TIM_InitStruct->TIM_Polarity2 == TIM_Polarity2_Low) + { + TIMx->OMR1 |= TIM_OC2P_Set; + } + else + { + TIMx->OMR1 &= TIM_OC2P_Reset; + } + } + } +} + +/******************************************************************************* +* Function Name : ICAP_ModuleConfig +* Description : Input Capture Module configuration +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral +* - TIM_InitStruct: pointer to a TIM_InitTypeDef structure that +* contains the configuration information for the specified TIM +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +static void ICAP_ModuleConfig(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct) +{ + if(TIM_InitStruct->TIM_Mode == TIM_Mode_PWMI) + { /* PWM input mode configuration */ + TIMx->SCR |= TIM_TS_IC1_Set|TIM_SMS_RESETCLK_Set|TIM_SME_Set; + + /* Channel 1 and channel 2 input selection */ + if(TIM_InitStruct->TIM_PWMI_ICSelection == TIM_PWMI_ICSelection_TI1) + { + TIMx->IMCR &= TIM_IC1S_Reset; + TIMx->IMCR |= TIM_IC2S_Set; + } + else + { + TIMx->IMCR |= TIM_IC1S_Set; + TIMx->IMCR &= TIM_IC2S_Reset; + } + + /* Channel polarity */ + if(TIM_InitStruct->TIM_PWMI_ICPolarity == TIM_PWMI_ICPolarity_Rising) + { + TIMx->IMCR &= TIM_IC1P_Reset; + TIMx->IMCR |= TIM_IC2P_Set; + } + else + { + TIMx->IMCR |= TIM_IC1P_Set; + TIMx->IMCR &= TIM_IC2P_Reset; + } + + /* Input capture Enable */ + TIMx->IMCR |= TIM_IC1_Enable |TIM_IC2_Enable; + } + else + { + if(TIM_InitStruct->TIM_Channel == TIM_Channel_1) + { + /* Input Capture 1 mode configuration */ + TIMx->SCR &= TIM_TriggerSelection_Mask & TIM_SlaveModeSelection_Mask; + TIMx->SCR |= TIM_TS_IC1_Set|TIM_SMS_RESETCLK_Set|TIM_SME_Set; + + /* Channel 1 input selection */ + if(TIM_InitStruct->TIM_IC1Selection == TIM_IC1Selection_TI1) + { + TIMx->IMCR &= TIM_IC1S_Reset; + } + else + { + TIMx->IMCR |= TIM_IC1S_Set; + } + /* Channel 1 polarity */ + if(TIM_InitStruct->TIM_IC1Polarity == TIM_IC1Polarity_Rising) + { + TIMx->IMCR &= TIM_IC1P_Reset; + } + else + { + TIMx->IMCR |= TIM_IC1P_Set; + } + + /* Input capture Enable */ + TIMx->IMCR |= TIM_IC1_Enable; + } + else + { + /* Input Capture 2 mode configuration */ + TIMx->SCR &= (TIM_TriggerSelection_Mask & TIM_SlaveModeSelection_Mask); + TIMx->SCR |= TIM_TS_IC2_Set|TIM_SMS_RESETCLK_Set|TIM_SME_Set; + + /* Channel 2 input selection */ + if(TIM_InitStruct->TIM_IC2Selection == TIM_IC2Selection_TI2) + { + TIMx->IMCR &= TIM_IC2S_Reset; + } + else + { + TIMx->IMCR |= TIM_IC2S_Set; + } + + /* Channel 2 polarity */ + if(TIM_InitStruct->TIM_IC2Polarity == TIM_IC2Polarity_Rising) + { + TIMx->IMCR &= TIM_IC2P_Reset; + } + else + { + TIMx->IMCR |= TIM_IC2P_Set; + } + + /* Input capture Enable */ + TIMx->IMCR |= TIM_IC2_Enable; + } + } +} + +/******************************************************************************* +* Function Name : Encoder_ModeConfig +* Description : Encoder Mode configuration +* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral +* - TIM_InitStruct: pointer to a TIM_InitTypeDef structure that +* contains the configuration information for the specified TIM +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +static void Encoder_ModeConfig(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct) +{ + /* Set Encoder mode */ + TIMx->SCR &= TIM_Encoder_Mask; + + if(TIM_InitStruct->TIM_Mode == TIM_Mode_Encoder1) + { + TIMx->SCR |= TIM_Encoder1_Set; + } + else if (TIM_InitStruct->TIM_Mode == TIM_Mode_Encoder2) + { + TIMx->SCR |= TIM_Encoder2_Set; + } + else + { + TIMx->SCR |= TIM_Encoder3_Set; + } + + /* Channel 1 input selection */ + if(TIM_InitStruct->TIM_IC1Selection == TIM_IC1Selection_TI2) + { + TIMx->IMCR |= TIM_IC1S_Set; + } + else + { + TIMx->IMCR &= TIM_IC1S_Reset; + } + + /* Channel 2 input selection */ + if(TIM_InitStruct->TIM_IC2Selection == TIM_IC2Selection_TI1) + { + TIMx->IMCR |= TIM_IC2S_Set; + } + else + { + TIMx->IMCR &= TIM_IC2S_Reset; + } + + /* Channel 1 polarity */ + if(TIM_InitStruct->TIM_IC1Polarity == TIM_IC1Polarity_Falling) + { + TIMx->IMCR |= TIM_IC1P_Set; + } + else + { + TIMx->IMCR &= TIM_IC1P_Reset; + } + + /* Channel 2 polarity */ + if(TIM_InitStruct->TIM_IC2Polarity == TIM_IC2Polarity_Falling) + { + TIMx->IMCR |= TIM_IC2P_Set; + } + else + { + TIMx->IMCR &= TIM_IC2P_Reset; + } +} +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_uart.c b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_uart.c new file mode 100644 index 000000000..5494ff335 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_uart.c @@ -0,0 +1,599 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_uart.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the UART software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_uart.h" +#include "75x_mrcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* UART LIN Mask */ +#define UART_LIN_Disable_Mask 0xFEFF /* LIN Disable Mask */ +#define UART_LIN_Enable_Mask 0x0100 /* LIN Enable Mask */ + +/* UART Mask */ +#define UART_Enable_Mask 0x0001 /* UART Enable Mask */ +#define UART_Disable_Mask 0xFFFE /* UART Disable Mask */ + +/* UART LoopBack */ +#define UART_LoopBack_Disable_Mask 0xFF7F/* LoopBack Disable Mask */ +#define UART_LoopBack_Enable_Mask 0x0080/* LoopBack Enable Mask */ + +#define UART_WordLength_Mask 0xFF9F /* UART Word Length Mask */ +#define UART_Parity_Mask 0xFF79 /* UART Parity Mask */ +#define UART_HardwareFlowControl_Mask 0x3FFF /* UART Hardware Flow Control Mask */ +#define UART_TxRxFIFOLevel_Mask 0xFFC0 /* UART Tx Rx FIFO Level Mask */ +#define UART_LINBreakLength_Mask 0xE1FF /* UART LIN Break Length Mask */ +#define UART_BreakChar_Mask 0x0001 /* UART Break Character send Mask */ +#define UART_FLAG_Mask 0x1F /* UART Flag Mask */ +#define UART_Mode_Mask 0xFCFF /* UART Mode Mask */ +#define UART_RTSSET_Mask 0xF7FF /* RTS signal is high */ +#define UART_RTSRESET_Mask 0x0800 /* RTS signal is low */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : UART_DeInit +* Description : Deinitializes the UARTx peripheral registers to their default +* reset values. +* Input : UARTx: where x can be 0,1 or 2 to select the UART peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void UART_DeInit(UART_TypeDef* UARTx) +{ + /* Reset the UARTx registers values */ + if(UARTx == UART0) + { + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_UART0,ENABLE); + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_UART0,DISABLE); + } + else if(UARTx == UART1) + { + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_UART1,ENABLE); + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_UART1,DISABLE); + } + else if(UARTx == UART2) + { + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_UART2,ENABLE); + MRCC_PeripheralSWResetConfig(MRCC_Peripheral_UART2,DISABLE); + } +} + +/******************************************************************************* +* Function Name : UART_Init +* Description : Initializes the UARTx peripheral according to the specified +* parameters in the UART_InitStruct . +* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral. +* - UART_InitStruct: pointer to a UART_InitTypeDef structure +* that contains the configuration information for the +* specified UART peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef* UART_InitStruct) +{ + + u32 APBClock = 0; + u32 IntegerDivider = 0; + u32 FractionalDivider = 0; + MRCC_ClocksTypeDef MRCC_ClocksStatus; + + /* Clear the WLEN bits */ + UARTx->LCR &= UART_WordLength_Mask; + /* Set the WLEN bits according to UART_WordLength value */ + UARTx->LCR |= UART_InitStruct->UART_WordLength; + + /* Choose Stop Bits */ + if(UART_InitStruct->UART_StopBits == UART_StopBits_1) + { + /* One Stop Bit */ + UARTx->LCR &= UART_StopBits_1; + } + else + { + /* Two Stop Bits */ + UARTx->LCR |= UART_StopBits_2; + } + + /* Clear SPS, EPS and PEN bits */ + UARTx->LCR &= UART_Parity_Mask; + /* Set PS, EPS and PEN bits according to UART_Parity value */ + UARTx->LCR |= UART_InitStruct->UART_Parity; + + /* Configure the BaudRate --------------------------------------------------*/ + /* Get the APB frequency */ + MRCC_GetClocksStatus(&MRCC_ClocksStatus); + APBClock = MRCC_ClocksStatus.PCLK_Frequency; + + /* Determine the integer part */ + IntegerDivider = ((100) * (APBClock) / (16 * (UART_InitStruct->UART_BaudRate))); + UARTx->IBRD = IntegerDivider / 100; + + /* Determine the fractional part */ + FractionalDivider = IntegerDivider - (100 * (UARTx->IBRD)); + UARTx->FBRD = ((((FractionalDivider * 64) + 50) / 100)); + + /* Choose the Hardware Flow Control */ + /* Clear RTSEn and CTSEn bits */ + UARTx->CR &= UART_HardwareFlowControl_Mask; + /* Set RTSEn and CTSEn bits according to UART_HardwareFlowControl value */ + UARTx->CR |= UART_InitStruct->UART_HardwareFlowControl; + + /* Configure the UART mode */ + /* Clear TXE and RXE bits */ + UARTx->CR &= UART_Mode_Mask; + /* Set TXE and RXE bits according to UART_Mode value */ + UARTx->CR |= UART_InitStruct->UART_Mode; + + /* Enable or disable the FIFOs */ + /* Set the FIFOs Levels */ + if(UART_InitStruct->UART_FIFO == UART_FIFO_Enable) + { + /* Enable the FIFOs */ + UARTx->LCR |= UART_FIFO_Enable; + + /* Clear TXIFLSEL and RXIFLSEL bits */ + UARTx->IFLS &= UART_TxRxFIFOLevel_Mask; + + /* Set RXIFLSEL bits according to UART_RxFIFOLevel value */ + UARTx->IFLS |= (UART_InitStruct->UART_RxFIFOLevel << 3); + + /* Set TXIFLSEL bits according to UART_TxFIFOLevel value */ + UARTx->IFLS |= UART_InitStruct->UART_TxFIFOLevel; + } + else + { + /* Disable the FIFOs */ + UARTx->LCR &= UART_FIFO_Disable; + } +} + +/******************************************************************************* +* Function Name : UART_StructInit +* Description : Fills each UART_InitStruct member with its default value. +* Input : UART_InitStruct: pointer to a UART_InitTypeDef structure which +* will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void UART_StructInit(UART_InitTypeDef* UART_InitStruct) +{ + /* UART_InitStruct members default value */ + UART_InitStruct->UART_WordLength = UART_WordLength_8D; + UART_InitStruct->UART_StopBits = UART_StopBits_1; + UART_InitStruct->UART_Parity = UART_Parity_Odd ; + UART_InitStruct->UART_BaudRate = 9600; + UART_InitStruct->UART_HardwareFlowControl = UART_HardwareFlowControl_None; + UART_InitStruct->UART_Mode = UART_Mode_Tx_Rx; + UART_InitStruct->UART_FIFO = UART_FIFO_Enable; + UART_InitStruct->UART_TxFIFOLevel = UART_FIFOLevel_1_2; + UART_InitStruct->UART_RxFIFOLevel = UART_FIFOLevel_1_2; +} + +/******************************************************************************* +* Function Name : UART_Cmd +* Description : Enables or disables the specified UART peripheral. +* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral +* - NewState: new state of the UARTx peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void UART_Cmd(UART_TypeDef* UARTx, FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Enable the selected UART by setting the UARTEN bit in the CR register */ + UARTx->CR |= UART_Enable_Mask; + } + else + { + /* Disable the selected UART by clearing the UARTEN bit in the CR register */ + UARTx->CR &= UART_Disable_Mask; + } +} + +/******************************************************************************* +* Function Name : UART_ITConfig +* Description : Enables or disables the specified UART interrupts. +* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral +* - UART_IT: specifies the UART interrupts sources to be +* enabled or disabled. This parameter can be any combination +* of the following values: +* - UART_IT_OverrunError: Overrun Error interrupt +* - UART_IT_BreakError: Break Error interrupt +* - UART_IT_ParityError: Parity Error interrupt +* - UART_IT_FrameError: Frame Error interrupt +* - UART_IT_ReceiveTimeOut: Receive Time Out interrupt +* - UART_IT_Transmit: Transmit interrupt +* - UART_IT_Receive: Receive interrupt +* - UART_IT_CTS: CTS interrupt +* - NewState: new state of the UARTx peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void UART_ITConfig(UART_TypeDef* UARTx, u16 UART_IT, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enables the selected interrupts */ + UARTx->IMSC |= UART_IT; + } + else + { + /* Disables the selected interrupts */ + UARTx->IMSC &= ~UART_IT; + } +} + +/******************************************************************************* +* Function Name : UART_DMAConfig +* Description : Configures the UART0 DMA interface. +* Input : - UART0_DMAtransfer : specifies the configuration of DMA request. +* This parameter can be: +* - UART0_DMATransfer_Single: Single DMA transfer +* - UART0_DMATransfer_Burst: Burst DMA transfer +* - UART0_DMAOnError: specifies the DMA on error request. +* This parameter can be: +* - UART0_DMAOnError_Enable: DMA receive request enabled +* when the UART error interrupt is asserted. +* - UART0_DMAOnError_Disable: DMA receive request disabled +* when the UART error interrupt is asserted. +* Output : None +* Return : None +*******************************************************************************/ +void UART_DMAConfig(u16 UART0_DMATransfer, u16 UART0_DMAOnError) +{ + if(UART0_DMATransfer == UART0_DMATransfer_Single) + { + /* Configure the DMA request from the UART0 as single transfer */ + UART0->DMACR &= UART0_DMATransfer_Single; + } + else + { + UART0->DMACR |= UART0_DMATransfer_Burst; + } + + if(UART0_DMAOnError == UART0_DMAOnError_Enable) + { + UART0->DMACR &= UART0_DMAOnError_Enable; + } + else + { + UART0->DMACR |= UART0_DMAOnError_Disable; + } +} + +/******************************************************************************* +* Function Name : UART_DMACmd +* Description : Enables or disables the UART0’s DMA interface. +* Input : - UART0_DMAReq: specifies the DMA request. +* This parameter can be: +* - UART0_DMAReq_Tx: Transmit DMA request +* - UART0_DMAReq_Rx: Receive DMA request +* - NewState: new state of the UART0’s DMA request. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void UART_DMACmd(u16 UART0_DMAReq, FunctionalState NewState) +{ + if(UART0_DMAReq == UART0_DMAReq_Tx) + { + if(NewState == ENABLE) + { + UART0->DMACR |= UART0_DMAReq_Tx; + } + else + { + UART0->DMACR &= ~UART0_DMAReq_Tx; + } + } + else + { + if(NewState == ENABLE) + { + UART0->DMACR |= UART0_DMAReq_Rx; + } + else + { + UART0->DMACR &= ~UART0_DMAReq_Rx; + } + } +} + +/******************************************************************************* +* Function Name : UART_LoopBackConfig +* Description : Enables or disables LoopBack mode in UARTx. +* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral +* - NewState: new state of the UARTx’s LoopBack mode. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void UART_LoopBackConfig(UART_TypeDef* UARTx, FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Enable the LoopBack mode of the specified UART */ + UARTx->CR |= UART_LoopBack_Enable_Mask; + } + else + { + /* Disable the LoopBack mode of the specified UART */ + UARTx->CR &= UART_LoopBack_Disable_Mask; + } +} + +/******************************************************************************* +* Function Name : UART_LINConfig +* Description : Sets the LIN break length. +* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral. +* - UART_LINBreakLength: Break length value. +* This parameter can be: +* - UART_LINBreakLength_10: 10 low bits +* - UART_LINBreakLength_11: 11 low bits +* - UART_LINBreakLength_12: 12 low bits +* - UART_LINBreakLength_13: 13 low bits +* - UART_LINBreakLength_14: 14 low bits +* - UART_LINBreakLength_15: 15 low bits +* - UART_LINBreakLength_16: 16 low bits +* - UART_LINBreakLength_17: 17 low bits +* - UART_LINBreakLength_18: 18 low bits +* - UART_LINBreakLength_19: 19 low bits +* - UART_LINBreakLength_20: 20 low bits +* Output : None +* Return : None +*******************************************************************************/ +void UART_LINConfig(UART_TypeDef* UARTx, u16 UART_LINBreakLength) +{ + /* Clear LBKLEN bits */ + UARTx->LCR &= UART_LINBreakLength_Mask; + + /* Set LBKLEN bits according to UART_LINBreakLength value */ + UARTx->LCR |= UART_LINBreakLength; +} + +/******************************************************************************* +* Function Name : UART_LINCmd +* Description : Enables or disables LIN master mode in UARTx. +* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral +* - NewState: new state of the UARTx’s LIN interface. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void UART_LINCmd(UART_TypeDef* UARTx, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable the LIN mode of the specified UART */ + UARTx->LCR |= UART_LIN_Enable_Mask; + } + else + { + /* Disable the LIN mode of the specified UART */ + UARTx->LCR &= UART_LIN_Disable_Mask; + } +} + +/******************************************************************************* +* Function Name : UART_SendData +* Description : Transmits a signle Byte of data through the UARTx peripheral. +* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral. +* - Data: the byte to transmit +* Output : None +* Return : None +*******************************************************************************/ +void UART_SendData(UART_TypeDef* UARTx, u8 Data) +{ + /* Transmit one byte */ + UARTx->DR = Data; +} + +/******************************************************************************* +* Function Name : UART_ReceiveData +* Description : Returns the most recent received Byte by the UARTx peripheral. +* Input : UARTx: where x can be 0,1 or 2 to select the UART peripheral. +* Output : None +* Return : The received data +*******************************************************************************/ +u8 UART_ReceiveData(UART_TypeDef* UARTx) +{ + /* Receive one byte */ + return ((u8)UARTx->DR); +} + +/******************************************************************************* +* Function Name : UART_SendBreak +* Description : Transmits break characters. +* Input : UARTx: where x can be 0,1 or 2 to select the UART peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void UART_SendBreak(UART_TypeDef* UARTx) +{ + /* Send break characters */ + UARTx->BKR |= UART_BreakChar_Mask; +} + +/******************************************************************************* +* Function Name : UART_RTSConfig +* Description : Sets or Resets the RTS signal +* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral. +* - RTSState: new state of the RTS signal. +* This parameter can be: RTSSET or RTSRESET +* Output : None +* Return : None +*******************************************************************************/ +void UART_RTSConfig(UART_TypeDef* UARTx, UART_RTSTypeDef RTSState) +{ + if(RTSState == RTSRESET) + { + UARTx->CR |= UART_RTSRESET_Mask; + } + else if(RTSState == RTSSET) + { + UARTx->CR &= UART_RTSSET_Mask; + } +} + +/******************************************************************************* +* Function Name : UART_GetFlagStatus +* Description : Checks whether the specified UART flag is set or not. +* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral +* - UART_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - UART_FLAG_OverrunError: Overrun error flag +* - UART_FLAG_Break: break error flag +* - UART_FLAG_ParityError: parity error flag +* - UART_FLAG_FrameError: frame error flag +* - UART_FLAG_TxFIFOEmpty: Transmit FIFO Empty flag +* - UART_FLAG_RxFIFOFull: Receive FIFO Full flag +* - UART_FLAG_TxFIFOFull: Transmit FIFO Full flag +* - UART_FLAG_RxFIFOEmpty: Receive FIFO Empty flag +* - UART_FLAG_Busy: Busy flag +* - UART_FLAG_CTS: CTS flag +* - UART_RawIT_OverrunError: Overrun Error interrupt flag +* - UART_RawIT_BreakError: Break Error interrupt flag +* - UART_RawIT_ParityError: Parity Error interrupt flag +* - UART_RawIT_FrameError: Frame Error interrupt flag +* - UART_RawIT_ReceiveTimeOut: ReceiveTimeOut interrupt flag +* - UART_RawIT_Transmit: Transmit interrupt flag +* - UART_RawIT_Receive: Receive interrupt flag +* - UART_RawIT_CTS: CTS interrupt flag +* Output : None +* Return : The new state of UART_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, u16 UART_FLAG) +{ + u32 UARTReg = 0, FlagPos = 0; + u32 StatusReg = 0; + + /* Get the UART register index */ + UARTReg = UART_FLAG >> 5; + + /* Get the flag position */ + FlagPos = UART_FLAG & UART_FLAG_Mask; + + if(UARTReg == 1) /* The flag to check is in RSR register */ + { + StatusReg = UARTx->RSR; + } + else if (UARTReg == 2) /* The flag to check is in FR register */ + { + StatusReg = UARTx->FR; + } + else if(UARTReg == 3) /* The flag to check is in RIS register */ + { + StatusReg = UARTx->RIS; + } + + if((StatusReg & (1 << FlagPos))!= RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : UART_ClearFlag +* Description : Clears the UARTx’s pending flags. +* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral. +* - UART_FLAG: specifies the flag to clear. +* This parameter can be one of the following values: +* - UART_FLAG_OverrunError: Overrun error flag +* - UART_FLAG_Break: break error flag +* - UART_FLAG_ParityError: parity error flag +* - UART_FLAG_FrameError: frame error flag +* Output : None +* Return : None +*******************************************************************************/ +void UART_ClearFlag(UART_TypeDef* UARTx, u16 UART_FLAG) +{ + u8 FlagPos = 0; + + /* Get the flag position */ + FlagPos = UART_FLAG & UART_FLAG_Mask; + + /* Clear the sepecified flag */ + UARTx->RSR &= ~(1 << FlagPos); +} + +/******************************************************************************* +* Function Name : UART_GetITStatus +* Description : Checks whether the specified UART interrupt has occurred or not. +* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral. +* - UART_IT: specifies the interrupt source to check. +* This parameter can be one of the following values: +* - UART_IT_OverrunError: Overrun Error interrupt +* - UART_IT_BreakError: Break Error interrupt +* - UART_IT_ParityError: Parity Error interrupt +* - UART_IT_FrameError: Frame Error interrupt +* - UART_IT_ReceiveTimeOut: Receive Time Out interrupt +* - UART_IT_Transmit: Transmit interrupt +* - UART_IT_Receive: Receive interrupt +* - UART_IT_CTS: CTS interrupt +* Output : None +* Return : The new state of UART_IT (SET or RESET). +*******************************************************************************/ +ITStatus UART_GetITStatus(UART_TypeDef* UARTx, u16 UART_IT) +{ + if((UARTx->MIS & UART_IT) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : UART_ClearITPendingBit +* Description : Clears the UARTx’s interrupt pending bits. +* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral. +* - UART_IT: specifies the interrupt pending bit to clear. +* More than one interrupt can be cleared using the “|” operator. +* This parameter can be: +* - UART_IT_OverrunError: Overrun Error interrupt +* - UART_IT_BreakError: Break Error interrupt +* - UART_IT_ParityError: Parity Error interrupt +* - UART_IT_FrameError: Frame Error interrupt +* - UART_IT_ReceiveTimeOut: Receive Time Out interrupt +* - UART_IT_Transmit: Transmit interrupt +* - UART_IT_Receive: Receive interrupt +* - UART_IT_CTS: CTS interrupt +* Output : None +* Return : None +*******************************************************************************/ +void UART_ClearITPendingBit(UART_TypeDef* UARTx, u16 UART_IT) +{ + /* Clear the specified interrupt */ + UARTx->ICR = UART_IT; +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_wdg.c b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_wdg.c new file mode 100644 index 000000000..812d627a9 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_wdg.c @@ -0,0 +1,244 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 75x_wdg.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file provides all the WDG software functions. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "75x_wdg.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Registers reset value */ +#define WDG_Preload_Mask 0xFFFF +#define WDG_Prescaler_Mask 0xFF + +/* WDG Start/Stop counter */ +#define WDG_Counter_Start_Mask 0x0002 +#define WDG_Counter_Stop_Mask 0xFFFD + +/* WDG Sequence */ +#define WDG_KeyValue1_Mask 0xA55A +#define WDG_KeyValue2_Mask 0x5AA5 + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/****************************************************************************** +* Function Name : WDG_DeInit +* Description : Deinitializes the WDG peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void WDG_DeInit(void) +{ + /* Reset all the WDG registers */ + WDG->CR = 0x0000; + WDG->PR = 0x00FF; + WDG->VR = 0xFFFF; + WDG->CNT = 0xFFFF; + WDG->SR = 0x0000; + WDG->MR = 0x0000; + WDG->KR = 0x0000; +} + +/******************************************************************************* +* Function Name : WDG_Init +* Description : Initializes WDG peripheral according to the specified +* parameters in the WDG_InitStruct. +* Input : WDG_InitStruct: pointer to a WDG_InitTypeDef structure that +* contains the configuration information for the WDG peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void WDG_Init(WDG_InitTypeDef* WDG_InitStruct) +{ + /* Configure WDG Prescaler register value */ + WDG->PR = WDG_InitStruct->WDG_Prescaler; + + /* Configure WDG Pre-load register value */ + WDG->VR = WDG_InitStruct->WDG_Preload ; + + if(WDG_InitStruct->WDG_Mode == WDG_Mode_WDG) + { + /* Select WDG mode */ + WDG->CR |= WDG_Mode_WDG ; + } + else + { + /* Select Timer mode */ + WDG->CR &= WDG_Mode_Timer; + } +} + +/******************************************************************************* +* Function Name : WDG_StructInit +* Description : Fills each WDG_InitStruct member with its default value. +* Input : WDG_InitStruct : pointer to a WDG_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void WDG_StructInit(WDG_InitTypeDef *WDG_InitStruct) +{ + /* Initialize mode */ + WDG_InitStruct->WDG_Mode = WDG_Mode_Timer; + + /* Initialize Preload */ + WDG_InitStruct->WDG_Preload = WDG_Preload_Mask ; + + /* Initialize Prescaler */ + WDG_InitStruct->WDG_Prescaler = WDG_Prescaler_Mask; +} + +/******************************************************************************* +* Function Name : WDG_Cmd +* Description : Enables or disables the WDG peripheral. +* Input : NewState: new state of the WDG peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void WDG_Cmd(FunctionalState NewState) +{ + if((WDG->CR & WDG_Mode_WDG) == 0) + { + /* Timer mode */ + if(NewState == ENABLE) + { + /* Start timer by setting SC bit in Control register */ + WDG->CR |= WDG_Counter_Start_Mask; + } + else + { + /* Stop timer by clearing SC bit in Control register */ + WDG->CR &= WDG_Counter_Stop_Mask; + } + } + else + { + /* Watchdog mode */ + if(NewState == ENABLE) + { + WDG->KR = WDG_KeyValue1_Mask; + WDG->KR = WDG_KeyValue2_Mask; + } + } +} + +/******************************************************************************* +* Function Name : WDG_ITConfig +* Description : Enables or disables the WDG End of Count(EC) interrupt. +* Input : Newstate: new state of the WDG End of Count(EC) interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void WDG_ITConfig(FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable the End of Count interrupt */ + WDG->MR |= WDG_IT_EC; + } + else + { + /* Disable the End of Count interrupt */ + WDG->MR &= ~WDG_IT_EC; + } +} + +/******************************************************************************* +* Function Name : WDG_GetCounter +* Description : Gets the WDG’s current counter value. +* Input : None +* Output : None +* Return : The WDG current counter value +*******************************************************************************/ +u16 WDG_GetCounter(void) +{ + return WDG->CNT; +} + +/******************************************************************************* +* Function Name : WDG_GetFlagStatus +* Description : Checks whether the WDG End of Count(EC) flag is set or not. +* Input : None +* Output : None +* Return : The new state of WDG End of Count(EC) flag (SET or RESET). +*******************************************************************************/ +FlagStatus WDG_GetFlagStatus(void) +{ + if((WDG->SR & WDG_FLAG_EC) != RESET ) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : WDG_ClearFlag +* Description : Clears the WDG’s End of Count(EC) pending flag. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void WDG_ClearFlag(void) +{ + /* Clear the EC pending bit */ + WDG->SR &= ~WDG_FLAG_EC; +} + +/******************************************************************************* +* Function Name : WDG_GetITStatus +* Description : Checks whether the WDG End of Count(EC) interrupt has +* occurred or not. +* Input : None +* Output : None +* Return : The new state of WDG End of Count(EC) interrupt (SET or RESET). +*******************************************************************************/ +ITStatus WDG_GetITStatus(void) +{ + if(((WDG->SR & WDG_IT_EC) != RESET )&&((WDG->MR & WDG_IT_EC) != RESET )) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : WDG_ClearITPendingBit +* Description : Clears the WDG's End of Count(EC) interrupt pending bit. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void WDG_ClearITPendingBit(void) +{ + /* Clear the EC pending bit */ + WDG->SR &= ~WDG_IT_EC; +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/lcd.c b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/lcd.c new file mode 100644 index 000000000..3436bd22d --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/STLibrary/src/lcd.c @@ -0,0 +1,1403 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : lcd.c +* Author : MCD Application Team +* Date First Issued : 03/10/2006 +* Description : This file includes the LCD driver for GXM12232-2SL liquid +* Crystal Display Module of STR75x-EVAL. +******************************************************************************** +* History: +* 07/17/2006 : V1.0 +* 03/10/2006 : V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "lcd.h" + +/* Private typedef -----------------------------------------------------------*/ + + /* Peripherals InitStructure define */ +GPIO_InitTypeDef GPIO_InitStructure; + +/* Private define ------------------------------------------------------------*/ +#define LCD_GPIO_Pins 0x3FC00 +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + /* Global variable to set the written text color: used for LCD_Printf */ + TextColorMode_TypeDef TextMode = BlackText; + + /* ASCII Table: each character is 7 column (7dots large) on two pages (16dots high) */ + /* 7 column character: Two 8bit data to display one column*/ + const u8 AsciiDotsTable[1778] = { + /* ASCII 0 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 1 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 2 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 3 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 4 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 5 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 6 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 7 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 8 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 9 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + /* ASCII 10 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + /* ASCII 11 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 12 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 13 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + /* ASCII 14 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 15 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 16 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 17 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 18 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 19 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 20 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 21 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 22 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 23 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 24 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 25 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 26 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 27 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 28 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + /* ASCII 29 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + /* ASCII 30 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + /* ASCII 31 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + /* ASCII 32 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + /* ASCII 33 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x13,0xe0,0x00,0x00,0x00,0x00,0x00,0x00, + /* ASCII 34 */ 0x00,0x00,0x00,0xe0,0x00,0x20,0x00,0x00,0x00,0xe0,0x00,0x20,0x00,0x00, + /* ASCII 35 */ 0x00,0x00,0x35,0x00,0x0f,0x80,0x35,0x60,0x0f,0x80,0x05,0x60,0x00,0x00, + /* ASCII 36 */ 0x00,0x00,0x0d,0x80,0x0a,0x40,0x3a,0x60,0x06,0x40,0x00,0x00,0x00,0x00, + /* ASCII 37 */ 0x00,0x00,0x02,0x40,0x02,0xa0,0x0a,0x40,0x15,0x00,0x09,0x00,0x00,0x00, + /* ASCII 38 */ 0x00,0x00,0x0c,0x00,0x13,0x00,0x14,0x80,0x08,0x80,0x14,0x00,0x00,0x00, + /* ASCII 39 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xe0,0x00,0x00,0x00,0x00,0x00,0x00, + /* ASCII 40 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x1f,0x80,0x60,0x60,0x00,0x00,0x00,0x00, + /* ASCII 41 */ 0x00,0x00,0x00,0x00,0x60,0x60,0x1f,0x80,0x00,0x00,0x00,0x00,0x00,0x00, + /* ASCII 42 */ 0x00,0x00,0x00,0x40,0x03,0x40,0x00,0xe0,0x03,0x40,0x00,0x40,0x00,0x00, + /* ASCII 43 */ 0x02,0x00,0x02,0x00,0x02,0x00,0x1f,0xc0,0x02,0x00,0x02,0x00,0x02,0x00, + /* ASCII 44 */ 0x00,0x00,0x00,0x00,0x60,0x00,0x38,0x00,0x08,0x00,0x00,0x00,0x00,0x00, + /* ASCII 45 */ 0x00,0x00,0x02,0x00,0x02,0x00,0x02,0x00,0x02,0x00,0x02,0x00,0x00,0x00, + /* ASCII 46 */ 0x00,0x00,0x00,0x00,0x18,0x00,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + /* ASCII 47 */ 0x00,0x00,0x20,0x00,0x18,0x00,0x06,0x00,0x01,0x80,0x00,0x60,0x00,0x00, + /* ASCII 48 */ 0x00,0x00,0x0f,0xc0,0x10,0x20,0x10,0x20,0x10,0x20,0x0f,0xc0,0x00,0x00, + /* ASCII 49 */ 0x00,0x00,0x10,0x00,0x10,0x20,0x1f,0xe0,0x10,0x00,0x10,0x00,0x00,0x00, + /* ASCII 50 */ 0x00,0x00,0x18,0x40,0x14,0x20,0x12,0x20,0x11,0x20,0x18,0xc0,0x00,0x00, + /* ASCII 51 */ 0x00,0x00,0x08,0x40,0x10,0x20,0x11,0x20,0x11,0x20,0x0e,0xc0,0x00,0x00, + /* ASCII 52 */ 0x00,0x00,0x06,0x00,0x05,0x00,0x04,0xc0,0x14,0x20,0x1f,0xe0,0x14,0x00, + /* ASCII 53 */ 0x00,0x00,0x08,0x00,0x11,0xe0,0x11,0x20,0x11,0x20,0x0e,0x20,0x00,0x00, + /* ASCII 54 */ 0x00,0x00,0x0f,0x80,0x11,0x40,0x11,0x20,0x11,0x20,0x0e,0x20,0x00,0x00, + /* ASCII 55 */ 0x00,0x00,0x00,0x60,0x00,0x20,0x18,0x20,0x07,0x20,0x00,0xe0,0x00,0x00, + /* ASCII 56 */ 0x00,0x00,0x0e,0xc0,0x11,0x20,0x11,0x20,0x11,0x20,0x0e,0xc0,0x00,0x00, + /* ASCII 57 */ 0x00,0x00,0x11,0xc0,0x12,0x20,0x12,0x20,0x0a,0x20,0x07,0xc0,0x00,0x00, + /* ASCII 58 */ 0x00,0x00,0x00,0x00,0x19,0x80,0x19,0x80,0x00,0x00,0x00,0x00,0x00,0x00, + /* ASCII 59 */ 0x00,0x00,0x00,0x00,0x30,0x00,0x19,0x80,0x09,0x80,0x00,0x00,0x00,0x00, + /* ASCII 60 */ 0x02,0x00,0x05,0x00,0x05,0x00,0x08,0x80,0x10,0x40,0x10,0x40,0x00,0x00, + /* ASCII 61 */ 0x00,0x00,0x05,0x00,0x05,0x00,0x05,0x00,0x05,0x00,0x05,0x00,0x00,0x00, + /* ASCII 62 */ 0x10,0x40,0x10,0x40,0x08,0x80,0x05,0x00,0x05,0x00,0x02,0x00,0x00,0x00, + /* ASCII 63 */ 0x00,0x00,0x00,0x00,0x10,0x80,0x14,0x40,0x02,0x40,0x01,0x80,0x00,0x00, + /* ASCII 64 */ 0x00,0x00,0x1f,0xe0,0x20,0x10,0x23,0x10,0x24,0x90,0x17,0xe0,0x00,0x00, + /* ASCII 65 */ 0x10,0x00,0x1c,0x00,0x17,0xa0,0x04,0x60,0x17,0x80,0x1c,0x00,0x10,0x00, + /* ASCII 66 */ 0x10,0x20,0x1f,0xe0,0x11,0x20,0x11,0x20,0x11,0x20,0x0e,0xc0,0x00,0x00, + /* ASCII 67 */ 0x00,0x00,0x0f,0xc0,0x10,0x20,0x10,0x20,0x10,0x20,0x08,0x60,0x00,0x00, + /* ASCII 68 */ 0x10,0x20,0x1f,0xe0,0x10,0x20,0x10,0x20,0x08,0x40,0x07,0x80,0x00,0x00, + /* ASCII 69 */ 0x10,0x20,0x1f,0xe0,0x11,0x20,0x13,0xa0,0x10,0x20,0x18,0x60,0x00,0x00, + /* ASCII 70 */ 0x00,0x00,0x10,0x20,0x1f,0xe0,0x11,0x20,0x03,0xa0,0x00,0x20,0x00,0x60, + /* ASCII 71 */ 0x00,0x00,0x0f,0xc0,0x10,0x20,0x10,0x20,0x12,0x20,0x0e,0x60,0x02,0x00, + /* ASCII 72 */ 0x10,0x20,0x1f,0xe0,0x11,0x20,0x01,0x00,0x11,0x20,0x1f,0xe0,0x10,0x20, + /* ASCII 73 */ 0x00,0x00,0x10,0x20,0x10,0x20,0x1f,0xe0,0x10,0x20,0x10,0x20,0x00,0x00, + /* ASCII 74 */ 0x00,0x00,0x0e,0x00,0x10,0x20,0x10,0x20,0x0f,0xe0,0x00,0x20,0x00,0x00, + /* ASCII 75 */ 0x10,0x20,0x1f,0xe0,0x12,0x20,0x03,0x00,0x04,0xa0,0x18,0x60,0x10,0x20, + /* ASCII 76 */ 0x00,0x00,0x10,0x20,0x1f,0xe0,0x10,0x20,0x10,0x00,0x1c,0x00,0x00,0x00, + /* ASCII 77 */ 0x10,0x20,0x1f,0xe0,0x10,0xe0,0x03,0x00,0x10,0xe0,0x1f,0xe0,0x10,0x20, + /* ASCII 78 */ 0x10,0x20,0x1f,0xe0,0x10,0xe0,0x07,0x00,0x18,0x20,0x1f,0xe0,0x00,0x20, + /* ASCII 79 */ 0x00,0x00,0x0f,0xc0,0x10,0x20,0x10,0x20,0x10,0x20,0x0f,0xc0,0x00,0x00, + /* ASCII 80 */ 0x00,0x00,0x10,0x20,0x1f,0xe0,0x12,0x20,0x02,0x20,0x01,0xc0,0x00,0x00, + /* ASCII 81 */ 0x00,0x00,0x0f,0xc0,0x10,0x20,0x30,0x20,0x30,0x20,0x2f,0xc0,0x00,0x00, + /* ASCII 82 */ 0x10,0x20,0x1f,0xe0,0x12,0x20,0x02,0x20,0x06,0x20,0x09,0xc0,0x10,0x00, + /* ASCII 83 */ 0x00,0x00,0x18,0xc0,0x09,0x20,0x11,0x20,0x11,0x40,0x0e,0x60,0x00,0x00, + /* ASCII 84 */ 0x00,0x60,0x00,0x20,0x10,0x20,0x1f,0xe0,0x10,0x20,0x00,0x20,0x00,0x60, + /* ASCII 85 */ 0x00,0x20,0x0f,0xe0,0x10,0x20,0x10,0x00,0x10,0x20,0x0f,0xe0,0x00,0x20, + /* ASCII 86 */ 0x00,0x20,0x00,0xe0,0x07,0x20,0x18,0x00,0x07,0x20,0x00,0xe0,0x00,0x20, + /* ASCII 87 */ 0x00,0x20,0x0f,0xe0,0x10,0x20,0x0f,0x00,0x10,0x20,0x0f,0xe0,0x00,0x20, + /* ASCII 88 */ 0x10,0x20,0x18,0x60,0x04,0x80,0x03,0x00,0x04,0x80,0x18,0x60,0x10,0x20, + /* ASCII 89 */ 0x00,0x20,0x00,0x60,0x11,0xa0,0x1e,0x00,0x11,0xa0,0x00,0x60,0x00,0x20, + /* ASCII 90 */ 0x00,0x00,0x18,0x60,0x14,0x20,0x13,0x20,0x10,0xa0,0x18,0x60,0x00,0x00, + /* ASCII 91 */ 0x00,0x00,0x00,0x00,0x7f,0xe0,0x40,0x20,0x40,0x20,0x00,0x00,0x00,0x00, + /* ASCII 92 */ 0x00,0x00,0x00,0x20,0x01,0xc0,0x06,0x00,0x38,0x00,0x00,0x00,0x00,0x00, + /* ASCII 93 */ 0x00,0x00,0x00,0x00,0x40,0x20,0x40,0x20,0x7f,0xe0,0x00,0x00,0x00,0x00, + /* ASCII 94 */ 0x00,0x00,0x01,0x00,0x00,0x80,0x00,0x60,0x00,0x80,0x01,0x00,0x00,0x00, + /* ASCII 95 */ 0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00, + /* ASCII 96 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x40,0x00,0x00,0x00,0x00, + /* ASCII 97 */ 0x00,0x00,0x0d,0x00,0x12,0x80,0x12,0x80,0x12,0x80,0x1f,0x00,0x10,0x00, + /* ASCII 98 */ 0x10,0x20,0x1f,0xe0,0x11,0x00,0x10,0x80,0x10,0x80,0x0f,0x00,0x00,0x00, + /* ASCII 99 */ 0x00,0x00,0x0f,0x00,0x10,0x80,0x10,0x80,0x10,0x80,0x09,0x80,0x00,0x00, + /* ASCII 100 */ 0x00,0x00,0x0f,0x00,0x10,0x80,0x10,0x80,0x11,0x20,0x1f,0xe0,0x10,0x00, + /* ASCII 101 */ 0x00,0x00,0x0f,0x00,0x12,0x80,0x12,0x80,0x12,0x80,0x13,0x00,0x00,0x00, + /* ASCII 102 */ 0x00,0x00,0x10,0x80,0x1f,0xc0,0x10,0xa0,0x10,0xa0,0x10,0xa0,0x00,0x00, + /* ASCII 103 */ 0x00,0x00,0x0f,0x00,0x50,0x80,0x50,0x80,0x51,0x00,0x3f,0x80,0x00,0x80, + /* ASCII 104 */ 0x10,0x20,0x1f,0xe0,0x11,0x00,0x00,0x80,0x10,0x80,0x1f,0x00,0x10,0x00, + /* ASCII 105 */ 0x00,0x00,0x10,0x80,0x10,0x80,0x1f,0xa0,0x10,0x00,0x10,0x00,0x00,0x00, + /* ASCII 106 */ 0x00,0x00,0x40,0x80,0x40,0x80,0x40,0xa0,0x3f,0x80,0x00,0x00,0x00,0x00, + /* ASCII 107 */ 0x10,0x20,0x1f,0xe0,0x02,0x00,0x16,0x80,0x19,0x80,0x10,0x80,0x00,0x00, + /* ASCII 108 */ 0x00,0x00,0x10,0x00,0x10,0x20,0x1f,0xe0,0x10,0x00,0x10,0x00,0x00,0x00, + /* ASCII 109 */ 0x10,0x80,0x1f,0x80,0x10,0x80,0x1f,0x00,0x10,0x80,0x1f,0x00,0x10,0x00, + /* ASCII 110 */ 0x10,0x80,0x1f,0x80,0x11,0x00,0x00,0x80,0x10,0x80,0x1f,0x00,0x10,0x00, + /* ASCII 111 */ 0x00,0x00,0x0f,0x00,0x10,0x80,0x10,0x80,0x10,0x80,0x0f,0x00,0x00,0x00, + /* ASCII 112 */ 0x40,0x80,0x7f,0x80,0x51,0x00,0x10,0x80,0x10,0x80,0x0f,0x00,0x00,0x00, + /* ASCII 113 */ 0x00,0x00,0x0f,0x00,0x10,0x80,0x10,0x80,0x51,0x00,0x7f,0x80,0x40,0x80, + /* ASCII 114 */ 0x00,0x00,0x10,0x80,0x1f,0x80,0x11,0x00,0x10,0x80,0x10,0x80,0x00,0x00, + /* ASCII 115 */ 0x00,0x00,0x19,0x00,0x12,0x80,0x12,0x80,0x12,0x80,0x0d,0x80,0x00,0x00, + /* ASCII 116 */ 0x00,0x00,0x00,0x80,0x0f,0xc0,0x10,0x80,0x10,0x80,0x10,0x80,0x08,0x00, + /* ASCII 117 */ 0x00,0x80,0x0f,0x80,0x10,0x00,0x10,0x00,0x08,0x80,0x1f,0x80,0x10,0x00, + /* ASCII 118 */ 0x00,0x80,0x03,0x80,0x0c,0x80,0x10,0x00,0x0c,0x80,0x03,0x80,0x00,0x80, + /* ASCII 119 */ 0x00,0x80,0x0f,0x80,0x10,0x80,0x0e,0x00,0x10,0x80,0x0f,0x80,0x00,0x80, + /* ASCII 120 */ 0x10,0x80,0x19,0x80,0x06,0x00,0x06,0x00,0x19,0x80,0x10,0x80,0x00,0x00, + /* ASCII 121 */ 0x00,0x80,0x41,0x80,0x46,0x80,0x78,0x00,0x4c,0x80,0x03,0x80,0x00,0x80, + /* ASCII 122 */ 0x00,0x00,0x19,0x80,0x14,0x80,0x12,0x80,0x11,0x80,0x18,0x80,0x00,0x00, + /* ASCII 123 */ 0x00,0x00,0x00,0x00,0x04,0x00,0x3b,0xc0,0x40,0x20,0x00,0x00,0x00,0x00, + /* ASCII 124 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x3f,0xe0,0x00,0x00,0x00,0x00,0x00,0x00, + /* ASCII 125 */ 0x00,0x00,0x00,0x00,0x40,0x20,0x3b,0xc0,0x04,0x00,0x00,0x00,0x00,0x00, + /* ASCII 126 */ 0x00,0x00,0x04,0x00,0x02,0x00,0x04,0x00,0x04,0x00,0x02,0x00,0x00,0x00}; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : LCD_DataLinesConfig +* Description : Configure data lines D0~D7 (P2.10~P2.17) in Input Floating mode +* for read from LCD or in Output Push-Pull mode for write on LCD +* Input : - Mode: specifies the configuration mode for data lines D0~D7 +* - Input: configure in Input Floating mode +* - Output: configure in Output Push-Pul mode +* Output : None +* Return : None +*******************************************************************************/ +void LCD_DataLinesConfig(DataConfigMode_TypeDef Mode) +{ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | + GPIO_Pin_14 | GPIO_Pin_15 | GPIO_Pin_16 | GPIO_Pin_17; + if (Mode == Input) + { + /* Configure D0~D7 lines (P2.10~2.17) in Input Floating mode */ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; + } + else + { + /* Configure D0~D7 lines (P2.10~2.17) in Output Push-Pull mode */ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + } + GPIO_Init(GPIO2, &GPIO_InitStructure); +} + +/******************************************************************************* +* Function Name : LCD_DataLinesWrite +* Description : Write a value on D0~D7 (P2.10~P2.17) +* Input : - GPIOx: GPIO port to write on. It could be +* - PortVal: value to write +* Output : None +* Return : None. +*******************************************************************************/ +void LCD_DataLinesWrite(GPIO_TypeDef* GPIOx, u32 PortVal) +{ + u32 Tmp = 0; + + /* Store the PM register value */ + Tmp = GPIO_GetPortMask(GPIOx); + /* Mask the corresponding GPIO pins */ + GPIO_PinMaskConfig(GPIOx, LCD_GPIO_Pins, DISABLE); + GPIO_PinMaskConfig(GPIOx, ~LCD_GPIO_Pins, ENABLE); + /* Write in the hole register */ + GPIO_Write(GPIOx, (PortVal<<10)); + + GPIO_PinMaskConfig(GPIOx, ~LCD_GPIO_Pins, DISABLE); + /* Return the initial PM register value */ + GPIO_PinMaskConfig(GPIOx, Tmp, ENABLE); + +} + +/******************************************************************************* +* Function Name : LCD_CtrlLinesConfig +* Description : Configure control lines E2, E1, RW, DI (P2.0~P2.3) in +* Output Push-Pull mode. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void LCD_CtrlLinesConfig(void) +{ + /* Configure E2, E1, RW, DI lines (P2.0~2.3) in Output Push-Pull mode */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_Init(GPIO2, &GPIO_InitStructure); +} + +/******************************************************************************* +* Function Name : LCD_CtrlLinesWrite +* Description : Set or reset control lines E2, E1, RW, DI (P2.0~P2.3). +* Input : - GPIOx: where x can be 0,1 or 2 to select the GPIO peripheral. +* - CtrlPins: the Control line. This parameter can be: +* - CtrlPin_E2: Enabe clock signal for Slave +* - CtrlPin_E1: Enabe clock signal for Master +* - CtrlPin_RW: Read/Write control line +* - CtrlPin_DI: +* Output : None +* Return : None +*******************************************************************************/ +void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, u32 CtrlPins, BitAction BitVal) +{ + /* Set or Reset the control line */ + if(BitVal != Bit_RESET) + { + GPIOx->PD |= CtrlPins; + } + else + { + GPIOx->PD &= ~CtrlPins; + } +} + +/******************************************************************************* +* Function Name : LCD_CheckMasterStatus +* Description : Check whether master LCD is busy or not +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void LCD_CheckMasterStatus(void) +{ + u8 MasterStatus = 0; + + /* Configure Data lines as Input */ + LCD_DataLinesConfig(Input); + /* Start the master read sequence */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_RW, Bit_SET); /* RW = 1 */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_DI, Bit_RESET); /* DI = 0 */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_SET); /* E1 = 1 */ + MasterStatus = GPIO_Read(GPIO2); + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ + + /* Wait until BF is cleared: D7 line */ + while ((MasterStatus & 0x20000)) + { + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_SET); /* E1 = 1 */ + MasterStatus = GPIO_Read(GPIO2); + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ + } +} + +/******************************************************************************* +* Function Name : LCD_CheckSlaveStatus +* Description : Check whether slave LCD is busy or not +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void LCD_CheckSlaveStatus(void) +{ + u8 SlaveStatus = 0; + + /* Configure Data lines as Input */ + LCD_DataLinesConfig(Input); + /* Start the slave read sequence */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_RW, Bit_SET); /* RW = 1 */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_DI, Bit_RESET); /* DI = 0 */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_SET); /* E2 = 1 */ + SlaveStatus = GPIO_Read(GPIO2); + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ + + /* Wait until BF is cleared: D7 line */ + while ((SlaveStatus & 0x20000)) + { + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_SET); /* E2 = 1 */ + SlaveStatus = GPIO_Read(GPIO2); + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ + } +} + +/******************************************************************************* +* Function Name : LCD_SendMasterCmd +* Description : Send one byte command to master LCD. +* Input : - Cmd: the user expected command to send to master LCD +* Output : None +* Return : None +*******************************************************************************/ +void LCD_SendMasterCmd(u8 Cmd) +{ + /* Check the master status */ + LCD_CheckMasterStatus(); + /* Configure Data lines as Output */ + LCD_DataLinesConfig(Output); + /* Start the master send command sequence */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_RW, Bit_RESET); /* RW = 0 */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_DI, Bit_RESET); /* DI = 0 */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_SET); /* E1 = 1 */ + /* Write master command */ + LCD_DataLinesWrite(GPIO2, (u32)Cmd); + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ +} + +/******************************************************************************* +* Function Name : LCD_SendSlaveCmd +* Description : Send one byte command to slave LCD +* Input : - Cmd: the user expected command to send to slave LCD. +* Output : None +* Return : None +*******************************************************************************/ +void LCD_SendSlaveCmd(u8 Cmd) +{ + /* Check the slave status */ + LCD_CheckSlaveStatus(); + /* Configure Data lines as Output */ + LCD_DataLinesConfig(Output); + /* Start the slave send command sequence */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_RW, Bit_RESET); /* RW = 0 */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_DI, Bit_RESET); /* DI = 0 */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_SET); /* E2 = 1 */ + /* Write slave command */ + LCD_DataLinesWrite(GPIO2, (u32)Cmd); + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ +} + +/******************************************************************************* +* Function Name : LCD_SendMasterData +* Description : Display one byte data to master LCD. +* Input : - Data: the user expected data to display on master LCD. +* Output : None +* Return : None +*******************************************************************************/ +void LCD_SendMasterData(u8 Data) +{ + /* Check the master status */ + LCD_CheckMasterStatus(); + /* Configure Data lines as Output */ + LCD_DataLinesConfig(Output); + /* Start the master send data sequence */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_RW, Bit_RESET); /* RW = 0 */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_DI, Bit_SET); /* DI = 1 */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_SET); /* E1 = 1 */ + /* Write data to the master */ + LCD_DataLinesWrite(GPIO2, (u32)Data); + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ +} + +/******************************************************************************* +* Function Name : LCD_ReadMasterData +* Description : Read master byte data displayed on master LCD. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +u32 LCD_ReadMasterData(void) +{ + u32 MasterData = 0; + + /* Check the master status */ + LCD_CheckMasterStatus(); + /* Configure Data lines as Input */ + LCD_DataLinesConfig(Input); + /* Start the master read data sequence */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_RW, Bit_SET); /* RW = 1 */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_DI, Bit_SET); /* DI = 1 */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_SET); /* E1 = 1 */ + /* Read data from the master */ + MasterData = ((GPIO_Read(GPIO2)&0x3FC00)>>10); + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ + /* Read the master returned data */ + return MasterData; +} + +/******************************************************************************* +* Function Name : LCD_SendSlaveData +* Description : Display one byte data to slave LCD. +* Input : - Data: the user expected data to display on slave LCD. +* Output : None +* Return : None +*******************************************************************************/ +void LCD_SendSlaveData(u8 Data) +{ + /* Check the slave status */ + LCD_CheckSlaveStatus(); + /* Configure Data lines as Output */ + LCD_DataLinesConfig(Output); + /* Start the slave send data sequence */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_RW, Bit_RESET); /* RW = 0 */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_DI, Bit_SET); /* DI = 1 */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_SET); /* E2 = 1 */ + /* Write data to the slave */ + LCD_DataLinesWrite(GPIO2, (u32)Data); + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ +} + +/******************************************************************************* +* Function Name : LCD_ReadSlaveData +* Description : Read slave byte data displayed on slave LCD. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +u32 LCD_ReadSlaveData(void) +{ + u32 SlaveData = 0; + + /* Check the slave status */ + LCD_CheckSlaveStatus(); + /* Configure Data lines as Input */ + LCD_DataLinesConfig(Input); + /* Start the slave read data sequence */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_RW, Bit_SET); /* RW = 1 */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_DI, Bit_SET); /* DI = 1 */ + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_SET); /* E2 = 1 */ + /* Read data from the slave */ + SlaveData = ((GPIO_Read(GPIO2)&0x3FC00)>>10); + LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ + /* Read the slave returned data */ + return SlaveData; +} + +/******************************************************************************* +* Function Name : LCD_Init +* Description : Initialize master and slave LCD. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void LCD_Init(void) +{ + /* Enable GPIO Clock */ + MRCC_PeripheralClockConfig(MRCC_Peripheral_GPIO, ENABLE); + + /* Configure control lines signals as output mode */ + LCD_CtrlLinesConfig(); + + /* Master LCD Init */ + LCD_SendMasterCmd(SOFTWARE_RESET); + LCD_SendMasterCmd(DISPLAY_OFF); + LCD_SendMasterCmd(DYNAMIC_DRIVE); + LCD_SendMasterCmd(DUTY_CYCLE); + LCD_SendMasterCmd(CLOCKWISE_OUTPUT); + LCD_SendMasterCmd(READ_MODIFY_WRITE_OFF); + LCD_SendMasterCmd(START_COLUMN); /* Set master column address to 0 */ + LCD_SendMasterCmd(START_LINE); /* Set master display start line to 0 */ + LCD_SendMasterCmd(DISPLAY_ON ); + + /* Slave LCD Init */ + LCD_SendSlaveCmd(SOFTWARE_RESET); + LCD_SendSlaveCmd(DISPLAY_OFF); + LCD_SendSlaveCmd(DYNAMIC_DRIVE); + LCD_SendSlaveCmd(DUTY_CYCLE); + LCD_SendSlaveCmd(CLOCKWISE_OUTPUT); + LCD_SendSlaveCmd(READ_MODIFY_WRITE_OFF); + LCD_SendSlaveCmd(START_COLUMN ); /* Set slave column address to 0 */ + LCD_SendSlaveCmd(START_LINE); /* Set slave display start line to 0 */ + LCD_SendSlaveCmd(DISPLAY_ON); + + /* Clear LCD */ + LCD_Clear(); + /* Set current Page to 0 for Master and Slave LCDs */ + LCD_SetSlavePage(0); + LCD_SetMasterPage(0); +} + +/******************************************************************************* +* Function Name : LCD_SetSlavePage +* Description : Set the display page of slave LCD, the page range is 0 to 3, +* make sure the input will not exceed this range ,otherwise it +* will reach a undecided result. +* Input : - Page: specifies the expected display page of slave LCD +* Output : None +* Return : None +*******************************************************************************/ +void LCD_SetSlavePage(u8 Page) +{ + /* Set Slave page */ + LCD_SendSlaveCmd(0xB8|Page); +} + +/******************************************************************************* +* Function Name : LCD_SetMasterPage +* Description : Set the display page of master LCD, the page range is 0 to 3, +* make sure the input will not exceed this range ,otherwise it +* will reach a undecided result. +* Input : - Page: specifies the expected display page of master LCD +* Output : None +* Return : None +*******************************************************************************/ +void LCD_SetMasterPage(u8 Page) +{ + /* Set Master page */ + LCD_SendMasterCmd(0xB8|Page); +} + +/******************************************************************************* +* Function Name : SetAddress +* Description : Set the display column of slave LCD. Column range is 0 to 61. +* Input : - Address: specifies the expected display column of slave LCD +* Output : None +* Return : None +*******************************************************************************/ +void LCD_SetSlaveColumn(u8 Address) +{ + /* Set Slave column address */ + LCD_SendSlaveCmd(Address&0x7F); +} + +/******************************************************************************* +* Function Name : LCD_SetMasterColumn +* Description : Set the display column of master LCD. Column range is 0 to 61. +* Input : - Address: specifies the expected display column of slave LCD +* Output : None +* Return : None +*******************************************************************************/ +void LCD_SetMasterColumn(u8 Address) +{ + /* Set Master column address */ + LCD_SendMasterCmd(Address&0x7F); +} + +/******************************************************************************* +* Function Name : LCD_SetTextColor +* Description : Set the text color for LCD. +* Input : - TextColor: BlackText: character on black, bottom on white. +* WhiteText: character on white, bottom on black. +* Output : None +* Return : None +*******************************************************************************/ +void LCD_SetTextColor(TextColorMode_TypeDef TextColor) +{ + if(TextColor) + { + /* Set White Text color */ + TextMode=WhiteText; + } + else + { + /* Set Black Text color */ + TextMode=BlackText; + } +} + +/******************************************************************************* +* Function Name : LCD_Clear +* Description : Clear the Master and Slave LCDs display. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void LCD_Clear(void) +{ + u8 Page = 0, Column = 0; + + /* Clear master and slave LCDs page by page */ + for (Page=0; Page<4; Page++) + { + /* Set master and slave page by page */ + LCD_SetMasterPage(Page); + LCD_SetSlavePage(Page); + /* Set master and slave column address */ + LCD_SetMasterColumn(0); + LCD_SetSlaveColumn(0); + /* Send empty data to master and slave column address on the selected page */ + for (Column=0; Column<61; Column++) + { + LCD_SendSlaveData(0); + LCD_SendMasterData(0); + } + } +} + +/******************************************************************************* +* Function Name : LCD_ClearLine +* Description : Clear the selected line of the LCD. +* Input : - Line: the Line to clear. +* - Line1 (Page0&1): clear the first line +* - Line2 (Page2&3): clear the second line +* Output : None +* Return : None +*******************************************************************************/ +void LCD_ClearLine(u8 Line) +{ + u8 Page = 0, Column = 0; + + /* Clear the slected master and slave line */ + for (Page=Line; Page 121) + { + /* Return if column exceeded 121 */ + return; + } + if (X > 60) + { + /* To be displayed on slave LCD (Window = 1) */ + Window = 1; + /* Get the Slave relative start column */ + ActualColumn = X%61; + } + else + { + /* To be displayed on master LCD (Window = 0) */ + ActualColumn = X; + } + + /* Switch window, display the character upper part */ + if (Window) + { + /* Display it on slave LCD */ + LCD_SetSlavePage(Line); + LCD_SetSlaveColumn(ActualColumn); + LCD_SendSlaveData(Bmp[i]); + } + else + { + /* Display it on master LCD */ + LCD_SetMasterPage(Line); + LCD_SetMasterColumn(ActualColumn); + LCD_SendMasterData(Bmp[i]); + } + /* Switch window, diplay the character lower part */ + if (Window) + { + /* Display it on slave LCD */ + LCD_SetSlavePage(Line+1); + LCD_SetSlaveColumn(ActualColumn); + LCD_SendSlaveData(Bmp[i+1]); + } + else + { + /* Display it on master LCD */ + LCD_SetMasterPage(Line+1); + LCD_SetMasterColumn(ActualColumn); + LCD_SendMasterData(Bmp[i+1]); + } + /* Increment by 2 the character table index */ + i+=2; + } +} + +/******************************************************************************* +* Function Name : LCD_DisplayChar +* Description : Display one character (7dots large, 16dots high). +* Note: +* the LCD can only display two line character,so page 0 and 1 +* is to display the first line, page2 and page 3 is to display +* the second line. +* Input : - Line: the Line where to display the character. +* - Line1 (Page0&1): display character on the first line +* - Line2 (Page2&3): display character on the second line +* - Column: start column address. +* - Ascii: character ascii code. +* - CharMode: BlackText: character on black, bottom on white. +* WhiteText: character on white, bottom on black. +* Output : None +* Return : None +*******************************************************************************/ +void LCD_DisplayChar(u8 Line, u8 Column, u8 Ascii, TextColorMode_TypeDef CharMode) +{ + u8 DotBuffer[14], i = 0; + + /* Display the character lower and upper 8bit parts (2*7columns) */ + for (i=0;i<14;i++) + { + /* Character displayed as white Text on black buttom */ + if(CharMode) + { + if(i%2==0) + { + DotBuffer[i] = ~AsciiDotsTable[Ascii*14+i+1]; + } + else + { + DotBuffer[i] = ~AsciiDotsTable[Ascii*14+i-1]; + } + } + /* Character displayed as black Text on white buttom */ + else + { + if(i%2==0) + { + DotBuffer[i] = AsciiDotsTable[Ascii*14+i+1]; + } + else + { + DotBuffer[i] = AsciiDotsTable[Ascii*14+i-1]; + } + } + } + /* Display the asc code after conversion */ + LCD_DrawChar(Line, Column, 7, DotBuffer); +} + +/******************************************************************************* +* Function Name : LCD_HexToAsciiLow +* Description : This function is used to convert the low nibble of an +* unsigned byte (0-F hex) to ASCII. +* Input : - byte: byte to convert to ASCII. +* Output : None +* Return : ASCII value result of the conversion. +*******************************************************************************/ +u8 LCD_HexToAsciiLow(u8 byte) +{ + /* Keep lower nibble only */ + byte = byte & 0x0F; + /* If the ascii is a number */ + if (byte <= 0x09) + { + /* Add 0x30 to its ascii */ + return(byte + 0x30); + } + else + { + /* Add 0x37 to its ascii */ + return (byte + 0x37); + } +} + +/******************************************************************************* +* Function Name : LCD_HexToAsciiHigh +* Description : This function is used to convert the high nibble of an +* unsigned byte (0-F hex) to ASCII. +* Input : - byte: byte to convert to ASCII. +* Output : None +* Return : ASCII value result of the conversion. +*******************************************************************************/ +u8 LCD_HexToAsciiHigh(u8 byte) +{ + /* Keep upper nibble only */ + byte = byte & 0xF0; + byte = byte >> 4; + /* If the ascii is a number */ + if (byte <= 0x09) + { + /* Add 0x30 to display its ascii */ + return(byte + 0x30); + } + else + { + /* Add 0x37 to display its ascii */ + return (byte + 0x37); + } +} + +/******************************************************************************* +* Function Name : LCD_DisplayString +* Description : This function is used to display a 17char max string of +* characters on the LCD display on the selected line. +* Note: +* this function is the user interface to use the LCD driver. +* Input : - *ptr: pointer to string to display on LCD. +* - Line: the Line where to display the character. +* - Line1 (Page0&1): display character on the first line +* - Line2 (Page2&3): display character on the second line +* Output : None +* Return : None +*******************************************************************************/ +void LCD_DisplayString(u8 Line, u8 *ptr, TextColorMode_TypeDef CharMode) +{ + u8 RefColumn = 0, i = 0; + + /* Send the string character by character on lCD */ + while ((*ptr!=0)&(i<17)) + { + /* Display one character on LCD */ + LCD_DisplayChar(Line, RefColumn, *ptr, CharMode); + /* Increment the column position by 7 */ + RefColumn+=7; + /* Point on the next character */ + ptr++; + /* Increment the character counter */ + i++; + /* If we reach the maximum Line character */ + if(i==17) + { + LCD_DisplayChar(Line, RefColumn-1, 0x1f, CharMode); /* Add missed columns */ + } + } +} + +/******************************************************************************* +* Function Name : LCD_Printf +* Description : This function is used to display a string of characters +* on the LCD display. +* Note: +* this function is the user interface to use the LCD driver. +* Input : - *ptr: pointer to string to display on LCD. +* Output : None +* Return : None +*******************************************************************************/ +void LCD_Printf(u8 *ptr, ...) +{ + u8 RefColumn = 0, RefPage = 0, i = 0, c1 = 0; + u16 var = 0, c2 = 0, c3 = 0, c4 = 0, c5 = 0; + u32 WordVar = 0; + + /* Store pointer on LCD_Printf second parameter (String) */ + u8 *var_ptr=(u8 *)(&ptr+1); + + /* Send String */ + while (*ptr != 0) + { + c1 = *ptr; + /* Limited to AsciiDotsTable code table */ + if(c1 <= 128) + { + /* Carriage return */ + if ( *ptr == '\r') + { + ptr++; + RefColumn = 0; + } + /* Jump to Line2 */ + else if( *ptr == '\n') + { + /* Point on the string to display */ + ptr++; + /* Clear Line2 */ + LCD_ClearLine(Line2); + /* Point on first Line2 column */ + RefColumn = 0; + /* Increment RefPage by 2 */ + RefPage+=2; + } + /* Display value on the passed format */ + else if( *ptr == '%') + { + ptr++; + /* Display decimal value */ + if (*ptr == 'd') + { + ptr++; + /* Get the word value to display */ + WordVar = ((*var_ptr)|(*(var_ptr+1)<<8)|(*(var_ptr+2)<<16)); + c1=WordVar/10000; + c2=(WordVar%10000)/1000; + c3=(WordVar%1000)/100; + c4=(WordVar%100)/10; + c5=(WordVar%10); + /* Display the ten miles digit */ + if (c1!=0) + { + LCD_DisplayChar(RefPage, RefColumn, c1+0x30, TextMode); + RefColumn+=7; + } + /* Display the miles digit */ + if (!((c1==0)&(c2==0))) + { + LCD_DisplayChar(RefPage, RefColumn, c2+0x30, TextMode); + RefColumn+=7; + } + /* Display the hundred digit */ + if (!((c1==0)&(c2==0)&(c3==0))) + { + LCD_DisplayChar(RefPage, RefColumn, c3+0x30, TextMode); + RefColumn+=7; + } + /* Display the tens digit */ + if (!((c1==0)&(c2==0)&(c3==0)&(c4==0))) + { + LCD_DisplayChar(RefPage, RefColumn, c4+0x30, TextMode); + RefColumn+=7; + } + /* Display the rest */ + LCD_DisplayChar(RefPage, RefColumn, c5+0x30, TextMode); + RefColumn+=7; + } + /* Display 16bits Hex value */ + else if (*ptr == 'x') + { + ptr++; + /* Display 8bits MSB */ + var_ptr = var_ptr +1; + var = *var_ptr; + c1 = LCD_HexToAsciiHigh(var); + LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); + RefColumn+=7; + c1 = LCD_HexToAsciiLow(var); + LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); + RefColumn+=7; + /* Display 8bits LSB */ + var_ptr = var_ptr -1; + var = *var_ptr; + var_ptr = var_ptr +4; + c1 = LCD_HexToAsciiHigh(var); + LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); + RefColumn+=7; + c1 = LCD_HexToAsciiLow(var); + LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); + RefColumn+=7; + } + /* Display 32bits Hex value */ + else if (*ptr == 'w') + { + ptr++; + /* Display 16bits MSB */ + var_ptr = var_ptr +3; + var = *var_ptr; + c1 = LCD_HexToAsciiHigh(var); + LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); + RefColumn+=7; + c1 = LCD_HexToAsciiLow(var); + LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); + RefColumn+=7; + var_ptr = var_ptr -1; + var = *var_ptr; + c1 = LCD_HexToAsciiHigh(var); + LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); + RefColumn+=7; + c1 = LCD_HexToAsciiLow(var); + LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); + RefColumn+=7; + /* Display 16bits LSB */ + var_ptr = var_ptr -1; + var = *var_ptr; + var_ptr = var_ptr +4; + c1 = LCD_HexToAsciiHigh(var); + LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); + RefColumn+=7; + c1 = LCD_HexToAsciiLow(var); + LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); + RefColumn+=7; + var_ptr = var_ptr -5; + var = *var_ptr; + var_ptr = var_ptr +4; + c1 = LCD_HexToAsciiHigh(var); + LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); + RefColumn+=7; + c1 = LCD_HexToAsciiLow(var); + LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); + RefColumn+=7; + } + else + { + /* Display '%' character which is followed by (d, x or w) */ + ptr--; + c1 = *ptr; + LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); + RefColumn+=7; + ptr++; + i++; + if(i==17) + { + /* Add missed columns */ + LCD_DisplayChar(RefPage, RefColumn-1, 0x1f, TextMode); + RefColumn = 0; + RefPage+=2; + } + } + } + else + { + /* Display characters different from (\r, \n, %) */ + LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); + RefColumn+=7; + ptr++; + i++; + if(i==17) + { + /* Add missed columns */ + LCD_DisplayChar(RefPage, RefColumn-1, 0x1f, TextMode); + LCD_ClearLine(Line2); + RefColumn = 0; + RefPage+=2; + } + } + } + } + /* Display spaces if string doesn't reach the max LCD characters size */ + while(RefColumn<119) + { + /* Display Spaces */ + LCD_DisplayChar(RefPage, RefColumn, 0x20, TextMode); + RefColumn+=7; + /* Add missed columns */ + LCD_DisplayChar(RefPage, RefColumn, 0x1f, TextMode); + } +} + +/******************************************************************************* +* Function Name : LCD_DrawMasterGraphic +* Description : Draw a Graphic image on master LCD. +* Input : - Bmp: the pointer of the dot matrix data. +* Output : None +* Return : None. +*******************************************************************************/ +void LCD_DrawMasterGraphic(u8 *Bmp) +{ + u8 j = 0, k = 0, ActPage = 0; + + /* Draw graphic on master: 61 Column *4 Pages */ + while(j<244) + { + /* Draw on master page by page */ + LCD_SetMasterPage(ActPage); + for(k=0; k<61; k++) + { + LCD_SetMasterColumn(k); + LCD_SendMasterData(*Bmp++); + j++; + } + ActPage++; + } +} + +/******************************************************************************* +* Function Name : LCD_DrawSlaveGraphic +* Description : Draw a Graphic image on slave LCD. +* Input : - Bmp: the pointer of the dot matrix data. +* Output : None +* Return : None. +*******************************************************************************/ +void LCD_DrawSlaveGraphic(u8 *Bmp) +{ + u8 j = 0, k = 0, ActPage = 0; + + /* Draw graphic on slave: 61 Column *4 Pages */ + while(j<244) + { + /* Draw on slave page by page */ + LCD_SetSlavePage(ActPage); + for(k=0; k<61; k++) + { + LCD_SetSlaveColumn(k); + LCD_SendSlaveData(*Bmp++); + j++; + } + ActPage++; + } +} + +/******************************************************************************* +* Function Name : LCD_DrawGraphic +* Description : Draw a Graphic image on LCD. +* Input : - Bmp: the pointer of the dot matrix data. +* Output : None +* Return : None. +*******************************************************************************/ +void LCD_DrawGraphic(u8 *Bmp) +{ + u8 Pos = 0, ActPage = 0; + u16 j = 0, k = 0; + + /* Draw graphic on LCD: 122 Column *4 Pages */ + while(j<488) + { + if(!Pos) + { + /* Draw on master page by page */ + LCD_SetMasterPage(ActPage); + for(k=0; k<61; k++) + { + LCD_SetMasterColumn(k); + LCD_SendMasterData(*Bmp++); + j++; + } + Pos=1; + } + else + { + /* Draw on slave page by page */ + LCD_SetSlavePage(ActPage); + for(k=0; k<61; k++) + { + LCD_SetSlaveColumn(k); + LCD_SendSlaveData(*Bmp++); + j++; + } + ActPage++; + Pos=0; + } + } +} + +/******************************************************************************* +* Function Name : LCD_ScrollGraphic +* Description : Scroll a Graphic image on LCD. +* Input : - Bmp: the pointer of the dot matrix data. +* - nCount: specifies the delay time length. +* Output : None +* Return : None. +*******************************************************************************/ +void LCD_ScrollGraphic(u8 *Bmp, u32 nCount) +{ + u8 Pos = 0, ActPage = 0; + u16 j = 0, k = 0; + u32 Counter = 0; + + /* Draw graphic on LCD: 122 Column *4 Pages */ + while(j<488) + { + if(!Pos) + { + /* Draw on master page by page */ + LCD_SetMasterPage(ActPage); + for(k=0; k<61; k++) + { + LCD_SetMasterColumn(k); + LCD_SendMasterData(*Bmp++); + Counter = nCount; + /* Set a delay */ + for(; Counter != 0; Counter--); + j++; + } + Pos=1; + } + else + { + /* Draw on slave page by page */ + LCD_SetSlavePage(ActPage); + for(k=0; k<61; k++) + { + LCD_SetSlaveColumn(k); + Counter = nCount; + /* Set a delay */ + for(; Counter != 0; Counter--); + LCD_SendSlaveData(*Bmp++); + j++; + } + ActPage++; + Pos=0; + } + } +} + +/******************************************************************************* +* Function Name : LCD_DrawPixel +* Description : Draw a Graphic image on slave LCD. +* Input : - XPos: the dot line number of the pixel. +* - 1->61 : displayed on master LCD +* - 62->122: displayed on slave LCD +* - YPos: column address of the pixel from 1->32. +* - Mode: Dot_On: Pixel turned on (black). +* Dot_Off: Pixel turned off (black). +* Output : None +* Return : None. +*******************************************************************************/ +void LCD_DrawPixel(u8 XPos, u8 YPos, DotMode_TypeDef Mode) +{ + u8 Page = 0, Position = 0; + u16 Mask = 0; + u32 MasterDataIn = 0, MasterDataOut = 0, SlaveDataIn = 0, SlaveDataOut = 0; + + /* Pixel page */ + Page = (XPos-1)/8; + /* Pixel column */ + Position = (YPos-1)/61; /* 0:Master, 1:Slave */ + /* Mask for the pixel */ + Mask= 1<<((XPos-1)%8); + /* If Position=0 draw pixel on master LCD */ + if(!Position) + { + LCD_SetMasterPage(Page); + LCD_SetMasterColumn(YPos-1); + MasterDataIn = LCD_ReadMasterData(); + MasterDataIn = LCD_ReadMasterData(); + LCD_SetMasterColumn(YPos-1); + if(Mode==Dot_On) + { + MasterDataOut = MasterDataIn | Mask; + } + else + { + MasterDataOut = MasterDataIn & (~Mask); + } + LCD_SendMasterData(MasterDataOut); + } + /* If Position=1 draw pixel on slave LCD */ + else + { + LCD_SetSlavePage(Page); + LCD_SetSlaveColumn(YPos-62); + SlaveDataIn = LCD_ReadSlaveData(); + SlaveDataIn = LCD_ReadSlaveData(); + LCD_SetSlaveColumn(YPos-62); + if(Mode==Dot_On) + { + SlaveDataOut = SlaveDataIn | Mask; + } + else + { + SlaveDataOut = SlaveDataIn & (~Mask); + } + LCD_SendSlaveData(SlaveDataOut); + } +} + +/******************************************************************************* +* Function Name : LCD_DrawLine +* Description : Draw a line on master and slave LCDs. +* Input : - XPos1: the dot line number of the source point . +* - XPos2: the dot line number of the destination point . +* - YPos1: the dot column number of the source point. +* - YPos2: the dot column number of the destination point. +* Output : None +* Return : None. +*******************************************************************************/ +void LCD_DrawLine(u8 XPos1, u8 YPos1, u8 XPos2, u8 YPos2) +{ + u8 XPos = 0, YPos = 0; + + /* Use XPos1, YPos1, XPos2 and YPos2 */ + if((XPos2>=XPos1)&(YPos2>=YPos1)) + { + for(XPos=XPos1; XPos<=XPos2; XPos++) + { + for(YPos=YPos1; YPos<=YPos2; YPos++) + { + LCD_DrawPixel(XPos, YPos, Dot_On); + } + } + } + else if((XPos2=YPos1)) + { + for(XPos=XPos2; XPos<=XPos1; XPos++) + { + for(YPos=YPos1; YPos<=YPos2; YPos++) + { + LCD_DrawPixel(XPos, YPos, Dot_On); + } + } + } + else if((XPos2>=XPos1)&(YPos2DR = cOutChar; + xReturn = pdPASS; + } + else + { + if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) + { + xReturn = pdFAIL; + } + else + { + xReturn = pdPASS; + } + } + + xQueueEmpty = pdFALSE; + } + portEXIT_CRITICAL(); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +void vSerialClose( xComPortHandle xPort ) +{ + /* Not supported as not required by the demo application. */ +} +/*-----------------------------------------------------------*/ + +__arm void vSerialISR( void ) +{ +signed portCHAR cChar; +portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByPost = pdFALSE; + + do + { + if( UART0->MIS & UART_IT_Transmit ) + { + /* The interrupt was caused by the THR becoming empty. Are there any + more characters to transmit? */ + if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE ) + { + /* A character was retrieved from the queue so can be sent to the + THR now. */ + UART0->DR = cChar; + } + else + { + xQueueEmpty = pdTRUE; + } + + UART_ClearITPendingBit( UART0, UART_IT_Transmit ); + } + + if( UART0->MIS & UART_IT_Receive ) + { + /* The interrupt was caused by a character being received. Grab the + character from the RHR and place it in the queue of received + characters. */ + cChar = UART0->DR; + xTaskWokenByPost = xQueueSendFromISR( xRxedChars, &cChar, xTaskWokenByPost ); + UART_ClearITPendingBit( UART0, UART_IT_Receive ); + } + } while( UART0->MIS ); + + /* If a task was woken by either a character being received or a character + being transmitted then we may need to switch to another task. */ + portEND_SWITCHING_ISR( ( xTaskWokenByPost || xTaskWokenByTx ) ); +} + + + + + + diff --git a/20080212/Demo/ARM7_STR75x_IAR/settings/RTOSDemo.dbgdt b/20080212/Demo/ARM7_STR75x_IAR/settings/RTOSDemo.dbgdt new file mode 100644 index 000000000..276257112 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/settings/RTOSDemo.dbgdt @@ -0,0 +1,88 @@ + + + + + + + + + + + + + 158272727 + + + + + + + + 200 + + + + 010 + + 20 + 1004 + 267 + 66 + + + {W}Watch-0:TB->CR4200143100100100200 + + + + + + + TabID-22366-21915 + Debug Log + Debug-Log + + + + TabID-21843-21924 + Build + Build + + + + TabID-21385-32577 + Breakpoints + Breakpoints + + + + + 0 + + + TabID-346-21918 + Workspace + Workspace + + + RTOSDemo + + + + 0TabID-18851-3390DisassemblyDisassembly0 + + + + + + TextEditorC:\E\temp\rc\1\Demo\ARM7_STR75x_IAR\main.c01265518551800100000010000001 + + + + + + + iaridepm.enu1debuggergui.enu1-2-2807232-2-20000167143823829-2-2807198-2-2200200142857203666142857823829-2-21311402-2-21404133100285713543800 + + + + diff --git a/20080212/Demo/ARM7_STR75x_IAR/settings/RTOSDemo.dni b/20080212/Demo/ARM7_STR75x_IAR/settings/RTOSDemo.dni new file mode 100644 index 000000000..1dcb6aa9e --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/settings/RTOSDemo.dni @@ -0,0 +1,44 @@ +[JLinkDriver] +WatchCond=_ 0 +Watch0=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0 +Watch1=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0 +[DisAssemblyWindow] +NumStates=_ 1 +State 1=_ 1 +[StackPlugin] +Enabled=1 +OverflowWarningsEnabled=1 +WarningThreshold=90 +SpWarningsEnabled=1 +WarnHow=0 +UseTrigger=1 +TriggerName=main +LimitSize=0 +ByteLimit=50 +[Interrupts] +Enabled=1 +[MemoryMap] +Enabled=0 +Base=0 +UseAuto=0 +TypeViolation=1 +UnspecRange=1 +ActionState=1 +[CodeCoverage] +Enabled=_ 0 +[Profiling] +Enabled=0 +[Log file] +LoggingEnabled=_ 0 +LogFile=_ "" +Category=_ 0 +[TermIOLog] +LoggingEnabled=_ 0 +LogFile=_ "" +[Disassemble mode] +mode=0 +[Breakpoints] +Count=0 +[TraceHelper] +Enabled=0 +ShowSource=1 diff --git a/20080212/Demo/ARM7_STR75x_IAR/settings/RTOSDemo.wsdt b/20080212/Demo/ARM7_STR75x_IAR/settings/RTOSDemo.wsdt new file mode 100644 index 000000000..c9147c33a --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/settings/RTOSDemo.wsdt @@ -0,0 +1,64 @@ + + + + + + RTOSDemo/Release + + + + + + + + + 224272727 + + + + + + + 300Find-in-FilesDebug-LogBreakpoints20100426766 + + + + + 48268826300BuildDebug-LogBreakpoints + 300BuildFind-in-FilesBreakpoints + + + 010300BuildFind-in-FilesDebug-Log + + + + + + + TabID-5322-15070 + Workspace + Workspace + + + RTOSDemoRTOSDemo/sourceRTOSDemo/startup + + + + 0TabID-10308-14988BuildBuildTabID-11884-28246BreakpointsBreakpointsTabID-30248-21129Debug LogDebug-Log0 + + + + + + TextEditorC:\E\temp\rc\1\Demo\ARM7_STR75x_IAR\main.c01265518551800100000010000001 + + + + + + + iaridepm.enu1-2-2715298-2-20000214286730143-2-22231402-2-214042251002857229124142857205703 + + + + diff --git a/20080212/Demo/ARM7_STR75x_IAR/settings/RTOSDemo_lnk.par b/20080212/Demo/ARM7_STR75x_IAR/settings/RTOSDemo_lnk.par new file mode 100644 index 000000000..88b582c54 --- /dev/null +++ b/20080212/Demo/ARM7_STR75x_IAR/settings/RTOSDemo_lnk.par @@ -0,0 +1,17 @@ +// IAR XLINK Setup +// Autogenerated file - do not edit +% +setrangelist($evec_ADR,[0-3F]); +setrangelist($internal_ROM,[8000-FFFFF]); +setrangelist($external_ROM,[]); +setrangelist($internal_RAM,[100000-7FFFFF]); +setrangelist($external_RAM,[]); +$CSTACK_SIZE=2000; +$IRQSTACK_SIZE=400; +$HEAP_SIZE=8000; +$COMMANDS=""; +$STACK_LOCATION="Internal RAM"; +$IRQSTACK_LOCATION="Internal RAM"; +$HEAP_LOCATION="Internal RAM"; +$iar_saved_xclfilename="C:\E\Dev\FreeRTOS\Demo\ARM7_STR75x_IAR\RTOSDemo_lnk.xcl"; +% \ No newline at end of file diff --git a/20080212/Demo/ARM9_STR91X_IAR/91x_init.s b/20080212/Demo/ARM9_STR91X_IAR/91x_init.s new file mode 100644 index 000000000..6c74e5272 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/91x_init.s @@ -0,0 +1,242 @@ +;******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +;* File Name : 91x_init.s +;* Author : MCD Application Team +;* Date First Issued : 05/18/2006 : Version 1.0 +;* Description : This module performs: +;* - FLASH/RAM initialization, +;* - Stack pointer initialization for each mode , +;* - Branches to ?main in the C library (which eventually +;* calls main()). +;* +;* On reset, the ARM core starts up in Supervisor (SVC) mode, +;* in ARM state,with IRQ and FIQ disabled. +;******************************************************************************* +;* History: +;* 05/22/2007 : Version 1.2 +;* 05/24/2006 : Version 1.1 +;* 05/18/2006 : Version 1.0 +;******************************************************************************* +;* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +;* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +;* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +;* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +;* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +;* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************/ + +; At power up, the CPU defaults to run on the oscillator clock, so Depending +; of your Application, Disable or Enable the following Define + + #define PLL_Clock ; Use PLL as the default clock source @ 96 MHz only with + ; Bank 0 @ 0x0 and Bank 1 @ 0x80000 +; #define RTC_Clock ; Use RTC as the default clock source +; #define OSC_Clock ; Use OSC as the default clock source + + +; --- Standard definitions of mode bits and interrupt (I & F) flags in PSRs + +Mode_USR EQU 0x10 +Mode_FIQ EQU 0x11 +Mode_IRQ EQU 0x12 +Mode_SVC EQU 0x13 +Mode_ABT EQU 0x17 +Mode_UND EQU 0x1B +Mode_SYS EQU 0x1F ; available on ARM Arch 4 and later + +I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled +F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled + + + +; --- STR9X SCU specific definitions + +SCU_BASE_Address EQU 0x5C002000 ; SCU Base Address +SCU_CLKCNTR_OFST EQU 0x00000000 ; Clock Control register Offset +SCU_PLLCONF_OFST EQU 0x00000004 ; PLL Configuration register Offset +SCU_SYSSTATUS_OFST EQU 0x00000008 ; System Status Register Offset +SCU_SCR0_OFST EQU 0x00000034 ; System Configuration Register 0 Offset + +; --- STR9X FMI specific definitions + +FMI_BASE_Address EQU 0x54000000 ; FMI Base Address +FMI_BBSR_OFST EQU 0x00000000 ; Boot Bank Size Register +FMI_NBBSR_OFST EQU 0x00000004 ; Non-boot Bank Size Register +FMI_BBADR_OFST EQU 0x0000000C ; Boot Bank Base Address Register +FMI_NBBADR_OFST EQU 0x00000010 ; Non-boot Bank Base Address Register +FMI_CR_OFST EQU 0x00000018 ; Control Register + +;--------------------------------------------------------------- +; ?program_start +;--------------------------------------------------------------- + MODULE ?program_start + + SECTION IRQ_STACK:DATA:NOROOT(3) + SECTION FIQ_STACK:DATA:NOROOT(3) + SECTION UND_STACK:DATA:NOROOT(3) + SECTION ABT_STACK:DATA:NOROOT(3) + SECTION SVC_STACK:DATA:NOROOT(3) + SECTION CSTACK:DATA:NOROOT(3) + SECTION .icode:CODE:NOROOT(2) + PUBLIC __iar_program_start + EXTERN ?main + CODE32 + +__iar_program_start: + LDR pc, =NextInst + + +NextInst + + + NOP ; execute some instructions to access CPU registers after wake + NOP ; up from Reset, while waiting for OSC stabilization + NOP + NOP + NOP + NOP + NOP + NOP + NOP + + +; BUFFERED_Mode +; ------------------------------------------------------------------------------ +; Description : Enable the Buffered mode. +; Just enable the buffered define on the 91x_conf.h +; http://www.arm.com/pdfs/DDI0164A_966E_S.pdf +; ------------------------------------------------------------------------------ + + MRC p15, 0, r0, c1, c0, 0 ; Read CP15 register 1 into r0 + ORR r0, r0, #0x8 ; Enable Write Buffer on AHB + MCR p15, 0, r0, c1, c0, 0 ; Write CP15 register 1 + + + +; --- Remap Flash Bank 0 at address 0x0 and Bank 1 at address 0x80000, +; when the bank 0 is the boot bank, then enable the Bank 1. + + LDR R6, =FMI_BASE_Address + + LDR R7, = 0x4 ; BOOT BANK Size = 512KB + STR R7, [R6, #FMI_BBSR_OFST] ; (2^4) * 32 = 512KB + + LDR R7, = 0x2 ; NON BOOT BANK Size = 32KB + STR R7, [R6, #FMI_NBBSR_OFST] ; (2^2) * 8 = 32KB + + LDR R7, = 0x0 ; BOOT BANK Address = 0x0 + STR R7, [R6, #FMI_BBADR_OFST] + + LDR R7, = 0x20000 ; NON BOOT BANK Address = 0x80000 + STR R7, [R6, #FMI_NBBADR_OFST] ; need to put 0x20000 because FMI + ; bus on A[25:2] of CPU bus + + LDR R7, = 0x18 ; Enable CS on both banks + STR R7, [R6, #FMI_CR_OFST] ; LDR R7, = 0x19 ;in RevD + ; to enable 8 words PFQ deepth + +; --- Enable 96K RAM, PFQBC enabled, DTCM & AHB wait-states disabled + LDR R0, = SCU_BASE_Address + LDR R1, = 0x0191 + STR R1, [R0, #SCU_SCR0_OFST] + +; ------------------------------------------------------------------------------ +; --- System clock configuration +; ------------------------------------------------------------------------------ + +#ifdef PLL_Clock ; Use 96 MHZ PLL clock as the default frequency + +; --- wait states Flash confguration + + LDR R6, = 0x00080000 ;Write a Write Flash Configuration + LDR R7, =0x60 ;Register command (60h) to any word + STRH R7, [R6] ;address in Bank 1. + + LDR R6, = 0x00083040 ;Write a Write Flash Configuration + LDR R7, = 0x3 ;Register Confirm command (03h) + STRH R7, [R6] ;2Wstaites in read,PWD,LVD enabled, + ;High BUSCFG. +; --- PLL configuration + LDR R1, = 0x00020002 ;Set OSC as clock source + STR R1, [R0, #SCU_CLKCNTR_OFST ] + + + NOP ; Wait for OSC stabilization + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + + + + + LDR R1, = 0x000ac019 ;Set PLL ENABLE, to 96Mhz + STR R1, [R0, #SCU_PLLCONF_OFST] + +Wait_Loop + LDR R1,[R0, #SCU_SYSSTATUS_OFST] ;Wait until PLL is Locked + ANDS R1, R1, #0x01 + BEQ Wait_Loop + + LDR R1, = 0x00020080 ;Set PLL as clock source after pll + STR R1, [R0, #SCU_CLKCNTR_OFST ] ;is locked and FMICLK=RCLK, + ;PCLK=RCLK/2 +#endif + +#ifdef RTC_Clock ;Use RTC as the default clock source + LDR R1, = 0x00020001 ;Set RTC as clock source and + STR R1, [R0, #SCU_CLKCNTR_OFST ] ;FMICLK=RCLK, PCLK=RCLK +#endif + +#ifdef OSC_Clock ;Use Osc as the default clock source + LDR R1, = 0x00020002 ;Set OSC as clock source and + STR R1, [R0, #SCU_CLKCNTR_OFST ] ;FMICLK=RCLK, PCLK=RCLK +#endif + + +; --- Initialize Stack pointer registers + +; Enter each mode in turn and set up the stack pointer + + MSR CPSR_c, #Mode_FIQ|I_Bit|F_Bit ; No interrupts + LDR SP, =SFE(FIQ_STACK) + + MSR CPSR_c, #Mode_IRQ|I_Bit|F_Bit ; No interrupts + LDR SP, = SFE(IRQ_STACK) + + MSR CPSR_c, #Mode_ABT|I_Bit|F_Bit ; No interrupts + LDR SP, = SFE(ABT_STACK) + + MSR CPSR_c, #Mode_UND|I_Bit|F_Bit ; No interrupts + LDR SP, = SFE(UND_STACK) + + MSR CPSR_c, #Mode_SYS ; IRQs & FIQs are now enabled + LDR SP, = SFE(CSTACK) + + MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit ; No interrupts + LDR SP, = SFE(SVC_STACK) + +; --- Set bits 17-18(DTCM/ITCM order bits)of the Core Configuration Control +; Register + MOV r0, #0x60000 + MCR p15,0x1,r0,c15,c1,0 + +; --- Now enter the C code + B ?main ; Note : use B not BL, because an application will + ; never return this way + + LTORG + + + END +;******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE**** + + + + diff --git a/20080212/Demo/ARM9_STR91X_IAR/91x_init_IAR.s b/20080212/Demo/ARM9_STR91X_IAR/91x_init_IAR.s new file mode 100644 index 000000000..1204e0871 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/91x_init_IAR.s @@ -0,0 +1,175 @@ +;******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +;* File Name : 91x_init.s +;* Author : MCD Application Team +;* Date First Issued : 05/18/2006 : Version 1.0 +;* Description : This module performs: +;* - FLASH/RAM initialization, +;* - Stack pointer initialization for each mode , +;* - Branches to ?main in the C library (which eventually +;* calls main()). +;* +;* On reset, the ARM core starts up in Supervisor (SVC) mode, +;* in ARM state,with IRQ and FIQ disabled. +;******************************************************************************* +; History: +; 05/24/2006 : Version 1.1 +; 05/18/2006 : Version 1.0 +;******************************************************************************* +;* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +;* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +;* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +;* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +;* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +;* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************/ + +; Depending in Your Application, Disable or Enable the following Define + +; #define BUFFERED_Mode ; Work on Buffered mode, when enabling this define + ; just enable the Buffered define on 91x_conf.h + +; --- Standard definitions of mode bits and interrupt (I & F) flags in PSRs + +Mode_USR EQU 0x10 +Mode_FIQ EQU 0x11 +Mode_IRQ EQU 0x12 +Mode_SVC EQU 0x13 +Mode_ABT EQU 0x17 +Mode_UND EQU 0x1B +Mode_SYS EQU 0x1F ; available on ARM Arch 4 and later + +I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled +F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled + +;--- BASE ADDRESSES +; System memory locations + +SRAM_Base EQU 0x04000000 +SRAM_Limit EQU 0x04018000 ; at the top of 96 KB SRAM + +SVC_Stack DEFINE SRAM_Limit ; 512 byte SVC stack at + ; top of memory - used by kernel. +IRQ_Stack DEFINE SVC_Stack-512 ; followed by IRQ stack +USR_Stack DEFINE IRQ_Stack-512 ; followed by USR stack. Tasks run in + ; system mode but task stacks are allocated + ; when the task is created. +FIQ_Stack DEFINE USR_Stack-8 ; followed by FIQ stack +ABT_Stack DEFINE FIQ_Stack-8 ; followed by ABT stack +UND_Stack DEFINE ABT_Stack-8 ; followed by UNDEF stack + + EXTERN main + +; STR9X register specific definition + +FMI_BBSR_AHB_UB EQU 0x54000000 +FMI_BBADR_AHB_UB EQU 0x5400000C +FMI_NBBSR_AHB_UB EQU 0x54000004 +FMI_NBBADR_AHB_UB EQU 0x54000010 + +SCU_SCRO_APB1_UB EQU 0x4C002034 +SCRO_AHB_UNB EQU 0x5C002034 + + + +;--------------------------------------------------------------- +; ?program_start +;--------------------------------------------------------------- + MODULE ?program_start + RSEG ICODE:CODE(2) + IMPORT LINK + PUBLIC __program_start + EXTERN ?main + CODE32 + + +__program_start: + LDR pc, =NextInst + + +NextInst + + + NOP ; execute some instructions to access CPU registers after wake + NOP ; up from Reset, while waiting for OSC stabilization + NOP + NOP + NOP + NOP + NOP + NOP + NOP + ldr r0,=LINK ; to include the vector table inside the final executable. + + + +; --- Remap Flash Bank 0 at address 0x0 and Bank 1 at address 0x80000, +; when the bank 0 is the boot bank, then enable the Bank 1. + + LDR R6, =0x54000000 + LDR R7, =0x4 + STR R7, [R6] + + LDR R6, =0x54000004 + LDR R7, =0x3 + STR R7, [R6] + + LDR R6, =0x5400000C + LDR R7, =0x0 + STR R7, [R6] + + LDR R6, =0x54000010 + LDR R7, =0x20000 + STR R7, [R6] + + LDR R6, =0x54000018 + LDR R7, =0x18 + STR R7, [R6] + +; --- Enable 96K RAM + LDR R0, = SCRO_AHB_UNB + LDR R1, = 0x0196 + STR R1, [R0] + + + /* Setup a stack for each mode - note that this only sets up a usable stack + for system/user, SWI and IRQ modes. Also each mode is setup with + interrupts initially disabled. */ + + MSR CPSR_c, #Mode_FIQ|I_Bit|F_Bit ; No interrupts + LDR SP, =FIQ_Stack + + MSR CPSR_c, #Mode_IRQ|I_Bit|F_Bit ; No interrupts + LDR SP, =IRQ_Stack + + MSR CPSR_c, #Mode_ABT|I_Bit|F_Bit ; No interrupts + LDR SP, =ABT_Stack + + MSR CPSR_c, #Mode_UND|I_Bit|F_Bit ; No interrupts + LDR SP, =UND_Stack + + MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit ; No interrupts + LDR SP, =SVC_Stack + + MSR CPSR_c, #Mode_SYS|I_Bit|F_Bit ; No interrupts + LDR SP, =USR_Stack + + /* We want to start in supervisor mode. Operation will switch to system + mode when the first task starts. */ + MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit + + +; --- Set bits 17-18 of the Core Configuration Control Register + + MOV r0, #0x60000 + MCR p15,0x1,r0,c15,c1,0 + + +; --- Now enter the C code + B ?main ; Note : use B not BL, because an application will + ; never return this way + + LTORG + + END +;******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE**** + diff --git a/20080212/Demo/ARM9_STR91X_IAR/91x_vect.s b/20080212/Demo/ARM9_STR91X_IAR/91x_vect.s new file mode 100644 index 000000000..d1a4b0b2b --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/91x_vect.s @@ -0,0 +1,228 @@ +;******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +;* File Name : 91x_vect.s +;* Author : MCD Application Team +;* Date First Issued : 05/18/2006 : Version 1.0 +;* Description : This File used to initialize the exception and IRQ +;* vectors, and to enter/return to/from exceptions +;* handlers. +;******************************************************************************* +* History: +* 05/22/2007 : Version 1.2 +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +;******************************************************************************* +; THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +; CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +; A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +; OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +; OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +; CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************/ + +#include "FreeRTOSConfig.h" +#include "ISR_Support.h" + + SECTION .intvec:CODE:ROOT(2) + CODE32 + + +VectorAddress EQU 0xFFFFF030 ; VIC Vector address register address. +VectorAddressDaisy EQU 0xFC000030 ; Daisy VIC Vector address register +I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled +F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled + + + + +;******************************************************************************* +; Import the __iar_program_start address from 91x_init.s +;******************************************************************************* + + IMPORT __iar_program_start + +;******************************************************************************* +; Import exception handlers +;******************************************************************************* + + IMPORT Undefined_Handler + IMPORT vPortYieldProcessor ; FreeRTOS SWI handler + IMPORT Prefetch_Handler + IMPORT Abort_Handler + IMPORT FIQ_Handler + + +;******************************************************************************* +; Export Peripherals IRQ handlers table address +;******************************************************************************* + +;******************************************************************************* +; Exception vectors +;******************************************************************************* + + LDR PC, Reset_Addr + LDR PC, Undefined_Addr + LDR PC, SWI_Addr + LDR PC, Prefetch_Addr + LDR PC, Abort_Addr + NOP ; Reserved vector + LDR PC, IRQ_Addr + +;******************************************************************************* +;* Function Name : FIQHandler +;* Description : This function is called when FIQ exception is entered. +;* Input : none +;* Output : none +;******************************************************************************* +FIQHandler + SUB lr,lr,#4 ; Update the link register. + STMFD sp!,{r0-r7,lr} ; Save The workspace plus the current return + ; address lr_fiq into the FIQ stack. + ldr r0,=FIQ_Handler + ldr lr,=FIQ_Handler_end + bx r0 ;Branch to FIQ_Handler. +FIQ_Handler_end: + + LDMFD sp!,{r0-r7,pc}^; Return to the instruction following... + ; ...the exception interrupt. + + +;******************************************************************************* +; Exception handlers address table +;******************************************************************************* + +Reset_Addr DCD __iar_program_start +Undefined_Addr DCD UndefinedHandler +SWI_Addr DCD vPortYieldProcessor +Prefetch_Addr DCD PrefetchAbortHandler +Abort_Addr DCD DataAbortHandler + DCD 0 ; Reserved vector +IRQ_Addr DCD IRQHandler + + +;******************************************************************************* +; MACRO +;******************************************************************************* +;******************************************************************************* +;* Macro Name : SaveContext +;* Description : This macro is used to save the context before entering +; an exception handler. +;* Input : The range of registers to store. +;* Output : none +;******************************************************************************* + +SaveContext MACRO reg1,reg2 + STMFD sp!,{reg1-reg2,lr} ; Save The workspace plus the current return + ; address lr_ mode into the stack. + MRS r1,spsr ; Save the spsr_mode into r1. + STMFD sp!,{r1} ; Save spsr. + ENDM + +;******************************************************************************* +;* Macro Name : RestoreContext +;* Description : This macro is used to restore the context to return from +; an exception handler and continue the program execution. +;* Input : The range of registers to restore. +;* Output : none +;******************************************************************************* + +RestoreContext MACRO reg1,reg2 + LDMFD sp!,{r1} ; Restore the saved spsr_mode into r1. + MSR spsr_cxsf,r1 ; Restore spsr_mode. + LDMFD sp!,{reg1-reg2,pc}^; Return to the instruction following... + ; ...the exception interrupt. + ENDM + + +;******************************************************************************* +; Exception Handlers +;******************************************************************************* + + +;******************************************************************************* +;* Function Name : UndefinedHandler +;* Description : This function is called when undefined instruction +; exception is entered. +;* Input : none +;* Output : none +;******************************************************************************* + +UndefinedHandler + SaveContext r0,r12 ; Save the workspace plus the current + ; return address lr_ und and spsr_und. + + ldr r0,=Undefined_Handler + ldr lr,=Undefined_Handler_end + bx r0 ; Branch to Undefined_Handler. + +Undefined_Handler_end: + RestoreContext r0,r12 ; Return to the instruction following... + ; ...the undefined instruction. + +;******************************************************************************* +;* Function Name : PrefetchAbortHandler +;* Description : This function is called when Prefetch Abort +; exception is entered. +;* Input : none +;* Output : none +;******************************************************************************* + +PrefetchAbortHandler + SUB lr,lr,#4 ; Update the link register. + SaveContext r0,r12 ; Save the workspace plus the current + ; return address lr_abt and spsr_abt. + + ldr r0,=Prefetch_Handler + ldr lr,=Prefetch_Handler_end + bx r0 ; Branch to Prefetch_Handler. + +Prefetch_Handler_end: + RestoreContext r0,r12 ; Return to the instruction following that... + ; ...has generated the prefetch abort exception. + +;******************************************************************************* +;* Function Name : DataAbortHandler +;* Description : This function is called when Data Abort +; exception is entered. +;* Input : none +;* Output : none +;******************************************************************************* + +DataAbortHandler + SUB lr,lr,#8 ; Update the link register. + SaveContext r0,r12 ; Save the workspace plus the current + ; return address lr_ abt and spsr_abt. + ldr r0,=Abort_Handler + ldr lr,=Abort_Handler_end + bx r0 ; Branch to Abort_Handler. + +Abort_Handler_end: + + RestoreContext r0,r12 ; Return to the instruction following that... + ; ...has generated the data abort exception. +;******************************************************************************* +;* Function Name : IRQHandler +;* Description : This function is called when IRQ exception is entered. +;* Input : none +;* Output : none +;******************************************************************************* + +IRQHandler + portSAVE_CONTEXT ; Save the context of the current task. + + LDR r0, = VectorAddress + LDR r0, [r0] ; Read the routine address + LDR r1, = VectorAddressDaisy + LDR r1, [r1] + MOV lr, pc + bx r0 + LDR r0, = VectorAddress ; Write to the VectorAddress to clear the + STR r0, [r0] ; respective interrupt in the internal interrupt + LDR r1, = VectorAddressDaisy ; Write to the VectorAddressDaisy to clear the + STR r1,[r1] ; respective interrupt in the internal interrupt + + portRESTORE_CONTEXT ; Restore the context of the selected task. + + LTORG + + END +;******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE**** diff --git a/20080212/Demo/ARM9_STR91X_IAR/91x_vect_IAR.s b/20080212/Demo/ARM9_STR91X_IAR/91x_vect_IAR.s new file mode 100644 index 000000000..c87b0004b --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/91x_vect_IAR.s @@ -0,0 +1,134 @@ +;******************** (C) COPYRIGHT 2005 STMicroelectronics ******************** +;* File Name : 91x_vect.s +;* Author : MCD Application Team +;* Date First Issued : 10/25/2005 : Beta Version V0.1 +;* Description : This File used to initialize the exception and IRQ +;* vectors, and to enter/return to/from exceptions +;* handlers. +;******************************************************************************* +; History: +; 10/25/2005 : Beta Version V0.1 +;******************************************************************************* +; THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +; CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +; A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +; OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +; OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +; CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************/ + +#include "FreeRTOSConfig.h" +#include "ISR_Support.h" + + MODULE ?RESET + COMMON INTVEC:CODE(2) + CODE32 + EXPORT LINK + +VectorAddress EQU 0xFFFFF030 ; VIC Vector address register address. +VectorAddressDaisy EQU 0xFC000030 ; Daisy VIC Vector address register + ; address. +LINK EQU 0x0 + +I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled +F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled + +;******************************************************************************* +; MACRO +;******************************************************************************* + +;******************************************************************************* +; Import the __program_start address from 91x_init.s +;******************************************************************************* + + IMPORT __program_start + +;******************************************************************************* +; Import exception handlers +;******************************************************************************* + + IMPORT vPortYieldProcessor ; FreeRTOS SWI handler + +;******************************************************************************* +; Export Peripherals IRQ handlers table address +;******************************************************************************* + +;******************************************************************************* +; Exception vectors +;******************************************************************************* + + LDR PC, Reset_Addr + LDR PC, Undefined_Addr + LDR PC, SWI_Addr + LDR PC, Prefetch_Addr + LDR PC, Abort_Addr + NOP ; Reserved vector + LDR PC, IRQ_Addr + LDR PC, FIQ_Addr + +;******************************************************************************* +; Exception handlers address table +;******************************************************************************* + +Reset_Addr DCD __program_start +Undefined_Addr DCD UndefinedHandler +SWI_Addr DCD vPortYieldProcessor +Prefetch_Addr DCD PrefetchAbortHandler +Abort_Addr DCD DataAbortHandler + DCD 0 ; Reserved vector +IRQ_Addr DCD IRQHandler +FIQ_Addr DCD FIQHandler + + +;******************************************************************************* +; Exception Handlers +;******************************************************************************* + +; - NOTE - +; The IRQ and SWI handlers are the only managed exception. + +UndefinedHandler + b UndefinedHandler + +PrefetchAbortHandler + b PrefetchAbortHandler + +DataAbortHandler + b DataAbortHandler + +FIQHandler + b FIQHandler + +DefaultISR + b DefaultISR + + +;******************************************************************************* +;* Function Name : IRQHandler +;* Description : This function called when IRQ exception is entered. +;* Input : none +;* Output : none +;******************************************************************************* + +IRQHandler + portSAVE_CONTEXT ; Save the context of the current task. + + LDR r0, = VectorAddress + LDR r0, [r0] ; Read the routine address + LDR r1, = VectorAddressDaisy + LDR r1, [r1] + MOV lr, pc + bx r0 + LDR r0, = VectorAddress ; Write to the VectorAddress to clear the + STR r0, [r0] ; respective interrupt in the internal interrupt + LDR r1, = VectorAddressDaisy ; Write to the VectorAddressDaisy to clear the + STR r1,[r1] ; respective interrupt in the internal interrupt + + portRESTORE_CONTEXT ; Restore the context of the selected task. + + + LTORG + + END + +;******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE**** diff --git a/20080212/Demo/ARM9_STR91X_IAR/FreeRTOSConfig.h b/20080212/Demo/ARM9_STR91X_IAR/FreeRTOSConfig.h new file mode 100644 index 000000000..e24503cf5 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/FreeRTOSConfig.h @@ -0,0 +1,95 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +/** + * The STR9 port can use either the watchdog or the timer 2 interrupt to generate + * the system tick. Set configUSE_WATCHDOG_TICK to 1 to use the watchdog, or + * 0 to use timer 2. + */ +#define configUSE_WATCHDOG_TICK 1 + + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 96000000 ) +#define configCPU_PERIPH_HZ ( ( unsigned portLONG ) 48000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 100 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 180 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) 52000 ) +#define configMAX_TASK_NAME_LEN ( 16 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/ARM9_STR91X_IAR/Library/include/91x_ahbapb.h b/20080212/Demo/ARM9_STR91X_IAR/Library/include/91x_ahbapb.h new file mode 100644 index 000000000..1828d488e --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/Library/include/91x_ahbapb.h @@ -0,0 +1,60 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_ahbapb.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* AHBAPB software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef _91x_AHBAPB_H +#define _91x_AHBAPB_H + +#include "91x_map.h" + +#define AHBAPB_Split_Enable 0x01000000 +#define AHBAPB_Split_Disable 0xFEFFFFFF +#define AHBAPB_Error_Enable 0x0000100 +#define AHBAPB_Error_Disable 0xFFFFEFF + +/*FLAG*/ +#define AHBAPB_FLAG_ERROR 0x01 /* error flag*/ +#define AHBAPB_FLAG_OUTM 0x10 /* Out of Memory flag */ +#define AHBAPB_FLAG_APBT 0x20 /* APB Time-out flag */ +#define AHBAPB_FLAG_RW 0x40 /*Access type flag*/ + +/* Includes ------------------------------------------------------------------*/ + + +/* AHBAPB Init structure definition */ +typedef struct +{ + u32 AHBAPB_SetTimeOut; + u32 AHBAPB_Error; + u32 AHBAPB_Split; + u8 AHBAPB_SplitCounter; +}AHBAPB_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +void AHBAPB_DeInit(AHBAPB_TypeDef* AHBAPBx); +void AHBAPB_Init(AHBAPB_TypeDef* AHBAPBx, AHBAPB_InitTypeDef* AHBAPB_InitStruct); +void AHBAPB_StructInit(AHBAPB_InitTypeDef* AHBAPB_InitStruct); +FlagStatus AHBAPB_GetFlagStatus(AHBAPB_TypeDef* AHBAPBx, u8 AHBAPB_FLAG); +void AHBAPB_ClearFlag(AHBAPB_TypeDef* AHBAPBx, u8 AHBAPB_FLAG); +u32 AHBAPB_GetPeriphAddrError(AHBAPB_TypeDef* AHBAPBx); + + +#endif /* _91x_AHBAPB_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM9_STR91X_IAR/Library/include/91x_conf.h b/20080212/Demo/ARM9_STR91X_IAR/Library/include/91x_conf.h new file mode 100644 index 000000000..4fc85fff1 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/Library/include/91x_conf.h @@ -0,0 +1,119 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_conf.h +* Author : MCD Application Team +* Date First Issued : 03/31/2006 : Beta Version V0.1 +* Description : Library configuration. +******************************************************************************** +* History: +* 03/31/2006 : Beta Version V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + + +#ifndef __91x_CONF_H +#define __91x_CONF_H + +/* To work in buffered mode just decomment the following line */ + +//#define Buffered + +/* Comment the line below to put the library in release mode */ + +//#ifndef inline +// #define inline inline +//#endif + +/************************* AHBAPB *************************/ +#define _AHBAPB +#define _AHBAPB0 +#define _AHBAPB1 +/************************* VIC *************************/ +#define _VIC +#define _VIC0 +#define _VIC1 +/************************* DMA *************************/ +//#define _DMA +//#define _DMA_Channel0 +//#define _DMA_Channel1 +//#define _DMA_Channel2 +//#define _DMA_Channel3 +//#define _DMA_Channel4 +//#define _DMA_Channel5 +//#define _DMA_Channel6 +//#define _DMA_Channel7 + +/************************* EMI *************************/ +//#define _EMI +//#define _EMI_Bank0 +//#define _EMI_Bank1 +//#define _EMI_Bank2 +//#define _EMI_Bank3 +/************************* FMI *************************/ +#define _FMI +/************************* WIU *************************/ +//#define _WIU +/************************* TIM *************************/ +#define _TIM +//#define _TIM0 +//#define _TIM1 +#define _TIM2 +//#define _TIM3 +/************************* GPIO ************************/ +#define _GPIO +#define _GPIO0 +#define _GPIO1 +#define _GPIO2 +#define _GPIO3 +#define _GPIO4 +#define _GPIO5 +#define _GPIO6 +#define _GPIO7 +#define _GPIO8 +#define _GPIO9 +/************************* RTC *************************/ +//#define _RTC +/************************* SCU *************************/ +#define _SCU +/************************* MC **************************/ +//#define _MC +/************************* UART ************************/ +#define _UART +//#define _UART0 +#define _UART1 +//#define _UART2 +/************************* SSP *************************/ +//#define _SSP +//#define _SSP0 +//#define _SSP1 +/************************* CAN *************************/ +//#define _CAN +/************************* ADC *************************/ +//#define _ADC +/************************* WDG *************************/ +#define _WDG +/************************* I2C *************************/ +//#define _I2C +//#define _I2C0 +//#define _I2C1 +/************************ ENET *************************/ +#define _ENET +/************************ DENET ************************/ +//#define _DENET + +/*---------------------------- _Main_Crystal frequency value (KHz)------------*/ + +#ifndef _Main_Crystal +#define _Main_Crystal 25000 +#endif +/*------------------------------------------------------------------------------*/ + + +#endif /* __91x_CONF_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM9_STR91X_IAR/Library/include/91x_dma.h b/20080212/Demo/ARM9_STR91X_IAR/Library/include/91x_dma.h new file mode 100644 index 000000000..6a383aafe --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/Library/include/91x_dma.h @@ -0,0 +1,247 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : template.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : provide a short description of the source file indicating +* its purpose. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __91x_DMA_H +#define __91x_DMA_H + +/* Includes ------------------------------------------------------------------*/ +#include"91x_map.h" + + +/* Exported types ------------------------------------------------------------*/ + +typedef struct +{ + u32 DMA_Channel_SrcAdd; /* The current source address (byte-aligned) of the data to be transferred.*/ + + u32 DMA_Channel_DesAdd; /* The current destination address (byte-aligned) of the data to be transferred.*/ + + u32 DMA_Channel_LLstItm; /* The word- aligned address for the next Linked List Item. */ + + u32 DMA_Channel_DesWidth; /* Destination transfer width. */ + + u32 DMA_Channel_SrcWidth; /* Source transfer width. */ + + u32 DMA_Channel_DesBstSize; /* The destination burst size which indicates the number of transfers that make up a destination burst transfer request.*/ + + u32 DMA_Channel_SrcBstSize; /* The source burst size.Indicates the number of transfers that make up a source burst */ + + u32 DMA_Channel_TrsfSize; /* Transfer size which indicates the size of the transfer when the DMA controller is the flow controller*/ + + u32 DMA_Channel_FlowCntrl; /* Flow control and transfer type. */ + + u32 DMA_Channel_Src; /* Source peripheral: selects the DMA source request peripheral. */ + + u32 DMA_Channel_Des; /* Destination peripheral:selects the DMA destination request peripheral. */ + +} DMA_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + + /* Interrupts masks */ + +#define DMA_ITMask_IE 0x4000 /* Interrupt error mask. */ +#define DMA_ITMask_ITC 0x8000 /* Terminal count interrupt mask.*/ +#define DMA_ITMask_ALL 0xC000 /* All DMA_Channelx interrupts enable/disable mask*/ + + /* Sources Request (used as masks) */ + +#define DMA_USB_RX_Mask 0x0001 +#define DMA_USB_TX_Mask 0x0002 +#define DMA_TIM0_Mask 0x0004 +#define DMA_TIM1_Mask 0x0008 +#define DMA_UART0_RX_Mask 0x0010 +#define DMA_UART0_TX_Mask 0x0020 +#define DMA_UART1_RX_Mask 0x0040 +#define DMA_UART1_TX_Mask 0x0080 +#define DMA_External_Req0_Mask 0x0100 +#define DMA_External_Req1_Mask 0x0200 +#define DMA_I2C0_Mask 0x0400 +#define DMA_I2C1_Mask 0x0800 +#define DMA_SSP0_RX_Mask 0x1000 +#define DMA_SSP0_TX_Mask 0x2000 +#define DMA_SSP1_RX_Mask 0x4000 +#define DMA_SSP1_TX_Mask 0x8000 + + +/* Previleged Mode and user mode */ + +#define DMA_PrevilegedMode 0x10000000 +#define DMA_UserMode 0xEFFFFFFF + + +/* Error and Terminal Count interrupts Status, after and before"raw" masking */ +#define DMA_IS 0x01 +#define DMA_TCS 0x02 +#define DMA_ES 0x03 +#define DMA_TCRS 0x04 +#define DMA_ERS 0x05 + + +/* interrupt clear: Terminal Count flag Clear and Error flag clear*/ + +#define DMA_TCC 0x01 +#define DMA_EC 0x02 + +/* channel index "0...7"*/ + +#define Channel0 0 +#define Channel1 1 +#define Channel2 2 +#define Channel3 3 +#define Channel4 4 +#define Channel5 5 +#define Channel6 6 +#define Channel7 7 + + + +/* Destination request selection: selects the DMA Destination request peripheral */ + +#define DMA_DES_USB_RX 0x00 +#define DMA_DES_USB_TX 0x40 +#define DMA_DES_TIM1 0x80 +#define DMA_DES_TIM2 0xC0 +#define DMA_DES_UART0_RX 0x100 +#define DMA_DES_UART0_TX 0x140 +#define DMA_DES_UART1_RX 0x180 +#define DMA_DES_UART1_TX 0x1C0 +#define DMA_DES_External_Req0 0x200 +#define DMA_DES_External_Req1 0x240 +#define DMA_DES_I2C0 0x280 +#define DMA_DES_I2C1 0x2C0 +#define DMA_DES_SSP0_RX 0x300 +#define DMA_DES_SSP0_TX 0x340 +#define DMA_DES_SSP1_RX 0x380 +#define DMA_DES_SSP1_TX 0x3C0 + + + + +/* Source request selection: selects the DMA Source request peripheral */ + +#define DMA_SRC_USB_RX 0x00 +#define DMA_SRC_USB_TX 0x02 +#define DMA_SRC_TIM1 0x04 +#define DMA_SRC_TIM2 0x06 +#define DMA_SRC_UART0_RX 0x08 +#define DMA_SRC_UART0_TX 0x0A +#define DMA_SRC_UART1_RX 0x0C +#define DMA_SRC_UART1_TX 0x0E +#define DMA_SRC_External_Req0 0x10 +#define DMA_SRC_External_Req1 0x12 +#define DMA_SRC_I2C0 0x14 +#define DMA_SRC_I2C1 0x16 +#define DMA_SRC_SSP0_RX 0x18 +#define DMA_SRC_SSP0_TX 0x1A +#define DMA_SRC_SSP1_RX 0x1C +#define DMA_SRC_SSP1_TX 0x1E + + + + + +#define DMA_FlowCntrlt0_DMA 0x00000000 /* transfer type :Memory-to-memory, flow controller:DMA */ +#define DMA_FlowCntrl1_DMA 0x00000800 /* transfer type :Memory-to-peripheral, flow controller:DMA */ +#define DMA_FlowCntrl2_DMA 0x00001000 /* transfer type :Peripheral-to-memory, flow controller:DMA */ +#define DMA_FlowCntrl3_DMA 0x00001800 /* transfer type :Source peripheral-to-destination peripheral, flow controller:DMA */ +#define DMA_FlowCntrl_DestPerip 0x00002000 /* transfer type :Source peripheral-to-destination peripheral, flow controller:Destination peripheral */ +#define DMA_FlowCntrl_Perip1 0x00002800 /* transfer type :Memory-to-peripheral, flow controller:peripheral */ +#define DMA_FlowCntrl_Perip2 0x00003000 /* transfer type : Peripheral-to-memory, flow controller:peripheral */ +#define DMA_FlowCntrl_SrcPerip 0x00003800 /* transfer type :Source peripheral-to-destination peripheral, flow controller:Source peripheral */ + + + + +#define DMA_SrcBst_1Data 0x00000000 /* Source Burst transfer request IS 1 Data ( DATA = Source transfer width ) */ +#define DMA_SrcBst_4Data 0x00001000 /* Source Burst transfer request IS 4 Data */ +#define DMA_SrcBst_8Data 0x00002000 /* Source Burst transfer request IS 8 Data */ +#define DMA_SrcBst_16Data 0x00003000 /* Source Burst transfer request IS 16 Data */ +#define DMA_SrcBst_32Data 0x00004000 /* Source Burst transfer request IS 32 Data */ +#define DMA_SrcBst_64Data 0x00005000 /* Source Burst transfer request IS 64Data */ +#define DMA_SrcBst_128Data 0x00006000 /* Source Burst transfer request IS 128 Data */ +#define DMA_SrcBst_256Data 0x00007000 /* Source Burst transfer request IS 256 Data */ + + + + +#define DMA_DesBst_1Data 0x00000000 /*Destination Burst transfer request IS 1Data ( DATA = destination transfer width ) */ +#define DMA_DesBst_4Data 0x00008000 /*Destination Burst transfer request IS 1 Data */ +#define DMA_DesBst_8Data 0x00010000 /*Destination Burst transfer request IS 4 Data */ +#define DMA_DesBst_16Data 0x00018000 /*Destination Burst transfer request IS 8 Data */ +#define DMA_DesBst_32Data 0x00020000 /*Destination Burst transfer request IS 16 Data */ +#define DMA_DesBst_64Data 0x00028000 /*Destination Burst transfer request IS 32 Data */ +#define DMA_DesBst_128Data 0x00030000 /*Destination Burst transfer request IS 128 Data */ +#define DMA_DesBst_256Data 0x00038000 /*Destination Burst transfer request IS 256 Data */ + + + + + +#define DMA_SrcWidth_Byte 0x00000000 /* source Width is one Byte */ +#define DMA_SrcWidth_HalfWord 0x00040000 /* source Width is one HalfWord */ +#define DMA_SrcWidth_Word 0x00080000 /* source Width is one Word */ + + + + +#define DMA_DesWidth_Byte 0x00000000 /* Destination Width is one Byte */ +#define DMA_DesWidth_HalfWord 0x00200000 /* Destination Width is one HalfWord */ +#define DMA_DesWidth_Word 0x00400000 /* Destination Width is one Word */ + + + + + + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void DMA_DeInit(void); +void DMA_Init(DMA_Channel_TypeDef * DMA_Channelx, DMA_InitTypeDef * DMA_InitStruct); +void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct); +void DMA_Cmd(FunctionalState NewState); +void DMA_ITMaskConfig(DMA_Channel_TypeDef * DMA_Channelx, u16 DMA_ITMask, FunctionalState NewState); +void DMA_ITConfig(DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState); +FlagStatus DMA_GetChannelStatus(u8 ChannelIndx ); +ITStatus DMA_GetITStatus(u8 ChannelIndx,u8 DMA_ITReq); +void DMA_ClearIT(u8 ChannelIndx,u8 DMA_ITClr); +void DMA_SyncConfig(u16 DMA_SrcReq, FunctionalState NewState); +FlagStatus DMA_GetSReq(u16 DMA_SrcReq); +FlagStatus DMA_GetLSReq(u16 DMA_SrcReq); +FlagStatus DMA_GetBReq(u16 DMA_SrcReq); +FlagStatus DMA_GetLBReq(u16 DMA_SrcReq); +FlagStatus DMA_GetChannelActiveStatus( DMA_Channel_TypeDef * DMA_Channelx); +void DMA_SetSReq(u16 DMA_SrcReq); +void DMA_SetLSReq(u16 DMA_SrcReq); +void DMA_SetBReq(u16 DMA_SrcReq); +void DMA_SetLBReq(u16 DMA_SrcReq); +void DMA_ChannelCmd (DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState); +void DMA_ChannelHalt (DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState); +void DMA_ChannelBuffering (DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState); +void DMA_ChannelLockTrsf(DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState); +void DMA_ChannelCache(DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState); +void DMA_ChannelProt0Mode(DMA_Channel_TypeDef * DMA_Channelx,u32 Prot0Mode); +void DMA_ChannelSRCIncConfig (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState); +void DMA_ChannelDESIncConfig (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState); + +#endif /* __91x_DMA_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM9_STR91X_IAR/Library/include/91x_enet.h b/20080212/Demo/ARM9_STR91X_IAR/Library/include/91x_enet.h new file mode 100644 index 000000000..7ba5263e1 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/Library/include/91x_enet.h @@ -0,0 +1,358 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_enet.h +* Author : MCD Application Team +* Date First Issued : May 2006 +* Description : ENET driver defines & function prototypes +******************************************************************************** +* History: +* May 2006: v1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +#ifndef _ENET_H_ +#define _ENET_H_ + +#include <91x_lib.h> + +#define ENET_BUFFER_SIZE 1520 +/*Structures typedef----------------------------------------------------------*/ + +/*Struct containing the DMA Descriptor data */ +typedef struct { + volatile u32 dmaStatCntl; /* DMA Status and Control Register */ + volatile u32 dmaAddr; /* DMA Start Address Register */ + volatile u32 dmaNext; /* DMA Next Descriptor Register */ + volatile u32 dmaPackStatus; /* DMA Packet Status and Control Register */ +} ENET_DMADSCRBase; + + +/* ENET_MACConfig Struct*/ +typedef struct { + FunctionalState ReceiveALL; /* Receive All frames: no address rule filtering */ + u32 MIIPrescaler; /* MII Clock Prescaler value */ + FunctionalState LoopbackMode; /* MAC Loopback mode */ + u32 AddressFilteringMode; /* Address Filtering Mode */ + u32 VLANFilteringMode; /* VLAN Filtering Mode */ + FunctionalState PassWrongFrame; /* Pass wrong frame (CRC, overlength, runt..)*/ + FunctionalState LateCollision; /* Retransmit frame when late collision*/ + FunctionalState BroadcastFrameReception; /* Accept broardcast frame */ + FunctionalState PacketRetry; /* Retransmit frame in case of collision */ + FunctionalState RxFrameFiltering; /* Filter early runt frame and address filter fail frames*/ + FunctionalState AutomaticPadRemoval; /* Automatic Padding removal */ + FunctionalState DeferralCheck; /* Excessive Defferal check */ +} ENET_MACConfig; + +/* ENET_TxStatus Struct*/ +typedef struct { + FlagStatus PacketRetry; + u8 ByteCount; + u8 collisionCount; + FlagStatus LateCollisionObserved; + FlagStatus Deffered; + FlagStatus UnderRun; + FlagStatus ExcessiveCollision; + FlagStatus LateCollision; + FlagStatus ExcessiveDefferal; + FlagStatus LossOfCarrier; + FlagStatus NoCarrier; + FlagStatus FrameAborted; +} ENET_TxStatus; + +/* ENET_RxStatus Struct*/ +typedef struct { + FlagStatus FrameAborted; + FlagStatus PacketFilter; + FlagStatus FilteringFail; + FlagStatus BroadCastFrame; + FlagStatus MulticastFrame; + FlagStatus UnsupportedControFrame; + FlagStatus ControlFrame; + FlagStatus LengthError; + FlagStatus Vlan2Tag; + FlagStatus Vlan1Tag; + FlagStatus CRCError; + FlagStatus ExtraBit; + FlagStatus MIIError; + FlagStatus FrameType; + FlagStatus LateCollision; + FlagStatus OverLength; + FlagStatus RuntFrame; + FlagStatus WatchDogTimout; + FlagStatus FalseCarrierIndication; + u16 FrameLength; +} ENET_RxStatus; + +/*Constants-------------------------------------------------------------------*/ + + +/* AddressFilteringMode */ +#define MAC_Perfect_Multicast_Perfect 0x0 +#define MAC_Perfect_Multicast_Hash 0x1<<17 +#define MAC_Hash_Multicast_Hash 0x2<<17 +#define MAC_Inverse 0x3<<17 +#define MAC_Promiscuous 0x4<<17 +#define MAC_Perfect_Multicast_All 0x5<<17 +#define MAC_Hash_Multicast_All 0x6<<17 + +/* VLANFilteringMode */ +#define VLANFilter_VLTAG_VLID 1 +#define VLANfilter_VLTAG 0 + +/* MIIPrescaler */ +#define MIIPrescaler_1 0 /* Prescaler for MDC clock when HCLK < 50 MHz */ +#define MIIPrescaler_2 1 /* Precaler for MDC when HCLK > = 50 MHz */ + + +/* MAC Address*/ +#define MAC_ADDR0 0x00 +#define MAC_ADDR1 0x0A +#define MAC_ADDR2 0x08 +#define MAC_ADDR3 0x04 +#define MAC_ADDR4 0x02 +#define MAC_ADDR5 0x01 + +/* Multicast Address */ +#define MCAST_ADDR0 0xFF +#define MCAST_ADDR1 0x00 +#define MCAST_ADDR2 0xFF +#define MCAST_ADDR3 0x00 +#define MCAST_ADDR4 0xFF +#define MCAST_ADDR5 0x00 + + + +#define ENET_MAX_PACKET_SIZE 1520 +#define ENET_NEXT_ENABLE 0x4000 + +/*ENET_OperatingMode*/ +/* Set the full/half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_100M 0x2100 +#define PHY_HALFDUPLEX_100M 0x2000 +/* Set the full/half-duplex mode at 10 Mb/s */ +#define PHY_FULLDUPLEX_10M 0x0100 +#define PHY_HALFDUPLEX_10M 0x0000 + + +/*----------------------------functions----------------------------------------*/ + +void ENET_MACControlConfig(ENET_MACConfig *MAC_Config); +void ENET_GetRxStatus(ENET_RxStatus * RxStatus); +void ENET_GetTxStatus(ENET_TxStatus * TxStatus); +long ENET_SetOperatingMode(void); +void ENET_InitClocksGPIO(void); +void ENET_MIIWriteReg (u8 phyDev, u8 phyReg, u32 phyVal); +u32 ENET_MIIReadReg (u8 phyDev, u32 phyReg ); +void ENET_RxDscrInit(void); +void ENET_TxDscrInit(void); +void ENET_Init(void); +void ENET_Start(void); +u32 ENET_RxPacketGetSize(void); +void ENET_TxPkt(void *ppkt, u16 size); +u32 ENET_HandleRxPkt(void *ppkt); + + +/*Driver internal constants---------------------------------------------------*/ + +/* MII Address */ +/* Description of bit field values of the MII Address Register */ +#define MAC_MIIA_PADDR 0x0000F800 +#define MAC_MII_ADDR_PHY_ADDR MAC_MIIA_PADDR /* Phy Address (default: 0): select one of 32 dev */ +#define MAC_MII_ADDR_MII_REG 0x000007C0 /* MII Register (default: 0) */ +#define MAC_MII_ADDR_MII_WRITE 0x00000002 /* MII Write */ +#define MAC_MIIA_PHY_DEV_ADDR (0x00005000 & MAC_MIIA_PADDR) /*To be changed if PHY device address changes */ +#define MAC_MII_ADDR_MII_BUSY 0x00000001 /* MII Busy */ + + +/* MII DATA register */ +#define MAC_MII_DATA_REG 0x0000FFFF /* MII Data */ + +/* MII Read / write timeouts*/ +#define MII_READ_TO 0x0004FFFF +#define MII_WRITE_TO 0x0004FFFF + +/* Description of common PHY registers */ +#define MAC_MII_REG_XCR 0x00000000 /* Tranceiver control register */ +#define MAC_MII_REG_XSR 0x00000001 /* Tranceiver status register */ +#define MAC_MII_REG_PID1 0x00000002 /* Tranceiver PHY identifier 1 */ +#define MAC_MII_REG_PID2 0x00000003 /* Tranceiver PHY identifier 2 */ +#define MAC_MII_REG_ANA 0x00000004 /* Auto-Negociation Advertissement register */ +#define MAC_MII_REG_ANLPA 0x00000005 /* Auto-Negociation Link Partner Ability register */ +#define MAC_MII_REG_ANE 0x00000006 /* Auto-Negociation Expansion register */ + + + + +/* MAC_MCR register fields */ +#define MAC_MCR_RA 0x80000000 +#define MAC_MCR_EN 0x40000000 +#define MAC_MCR_PS 0x03000000 +#define MAC_MCR_DRO 0x00800000 +#define MAC_MCR_LM 0x00600000 +#define MAC_MCR_FDM 0x00100000 +#define MAC_MCR_AFM 0x000E0000 +#define MAC_MCR_PWF 0x00010000 +#define MAC_MCR_VFM 0x00008000 +#define MAC_MCR_ELC 0x00001000 +#define MAC_MCR_DBF 0x00000800 +#define MAC_MCR_DPR 0x00000400 +#define MAC_MCR_RVFF 0x00000200 +#define MAC_MCR_APR 0x00000100 +#define MAC_MCR_BL 0x000000C0 +#define MAC_MCR_DCE 0x00000020 +#define MAC_MCR_RVBE 0x00000010 +#define MAC_MCR_TE 0x00000008 +#define MAC_MCR_RE 0x00000004 +#define MAC_MCR_RCFA 0x00000001 + +/* MTS */ +#define MAC_MTS_FA 0x00000001 +#define MAC_MTS_NC 0x00000004 +#define MAC_MTS_LOC 0x00000008 +#define MAC_MTS_ED 0x00000010 +#define MAC_MTS_LC 0x00000020 +#define MAC_MTS_EC 0x00000040 +#define MAC_MTS_UR 0x00000080 +#define MAC_MTS_DEF 0x00000100 +#define MAC_MTS_LCO 0x00000200 +#define MAC_MTS_CC 0x00003C00 +#define MAC_MTS_BC 0x7FFC0000 +#define MAC_MTS_PR 0x80000000 + +/* MRS */ +#define MAC_MRS_FL 0x000007FF +#define MAC_MRS_FCI 0x00002000 +#define MAC_MRS_WT 0x00004000 +#define MAC_MRS_RF 0x00008000 +#define MAC_MRS_OL 0x00010000 +#define MAC_MRS_LC 0x00020000 +#define MAC_MRS_FT 0x00040000 +#define MAC_MRS_ME 0x00080000 +#define MAC_MRS_EB 0x00100000 +#define MAC_MRS_CE 0x00200000 +#define MAC_MRS_VL1 0x00400000 +#define MAC_MRS_VL2 0x00800000 +#define MAC_MRS_LE 0x01000000 +#define MAC_MRS_CF 0x02000000 +#define MAC_MRS_UCF 0x04000000 +#define MAC_MRS_MCF 0x08000000 +#define MAC_MRS_BF 0x10000000 +#define MAC_MRS_FF 0x20000000 +#define MAC_MRS_PF 0x40000000 +#define MAC_MRS_FA 0x80000000 + +/* SCR */ +#define DMA_SCR_SRESET 0x00000001 /* Soft Reset (DMA_SCR_RESET) */ +#define DMA_SCR_LOOPB 0x00000002 /* Loopback mode (DMA_SCR_LOOPB) */ +#define DMA_SCR_RX_MBSIZE 0x00000010 /* Max defined burst length in RX mode (DMA_SCR_RX_MAX_BURST_...) */ +#define DMA_SCR_TX_MBSIZE 0x000000C0 /* Max defined burst length in TX mode (DMA_SCR_TX_MAX_BURST_...) */ +#define DMA_SCR_RX_MAX_BURST_SZ DMA_SCR_RX_MBSIZE /* Maximum value of defined burst length in RX mode */ +#define DMA_SCR_RX_MAX_BURST_SZ_VAL 0x00000000 /* Default value of burst length in RX mode */ +#define DMA_SCR_TX_MAX_BURST_SZ DMA_SCR_TX_MBSIZE /* Maximum value of defined burst length in TX mode */ +#define DMA_SCR_TX_MAX_BURST_SZ_VAL 0x000000C0 /* Default value of burst length in TX mode */ + + +/* DMA_RX_START */ +#define DMA_RX_START_DMAEN 0x00000001 +#define DMA_RX_START_STFETCH 0x00000004 +#define DMA_RX_START_FFAIL 0x00000020 +#define DMA_RX_START_RUNT 0x00000040 +#define DMA_RX_START_COLLS 0x00000080 +#define DMA_RX_START_DMA_EN 0x00000001 /* set = 0 by sw force a DMA abort */ +#define DMA_RX_START_FETCH 0x00000004 /* start fetching the 1st descriptor */ +#define DMA_RX_START_FILTER_FAIL 0x00000020 /* if = 1 the address filtering failed cond */ +#define DMA_RX_START_RUNT 0x00000040 /* discard damaged RX frames from cpu charge */ +#define DMA_RX_START_COLLS_SEEN 0x00000080 /* Late Collision Seen Cond discard frame automat. */ +#define DMA_RX_START_DFETCH_DLY 0x00FFFF00 /* Descriptor Fetch Delay */ +#define DMA_RX_START_DFETCH_DLY_POS 8 +#define DMA_RX_START_DFETCH_DEFAULT 0x00010000 /* Descriptor Fetch Delay default value */ + +/* DMA_DSCR_PACK_STAT */ +#define DMA_DSCR_PACK_STAT 0x00010000 + + +/* DMA_TX_START */ +#define DMA_TX_START_DMAEN 0x00000001 +#define DMA_TX_START_STFETCH 0x00000004 +#define DMA_TX_START_URUN 0x00000020 +#define DMA_TX_START_DISPAD 0x00000040 +#define DMA_TX_START_ADDCTC 0x00000080 +#define DMA_TX_START_DMA_EN 0x00000001 /* set = 0 by sw force a DMA abort */ +#define DMA_TX_START_FETCH 0x00000004 /* start fetching the 1st descriptor */ +#define DMA_RX_START_FILTER_FAIL 0x00000020 /* if = 1 the address filtering failed cond */ +#define DMA_TX_START_DFETCH_DLY 0x00FFFF00 /* Descriptor Fetch Delay */ +#define DMA_TX_START_DFETCH_DEFAULT 0x00010000 /* Descriptor Fetch Delay */ +#define DMA_TX_START_DFETCH_DLY_POS 0x8 +#define DMA_TX_START_URUN 0x00000020 +#define DMA_TX_START_DIS_PADDING 0x00000040 /* Avoid automatic addition of padding bits by MAC*/ +#define DMA_TX_START_ADD_CRC_DIS 0x00000080 /* Tell MAC not to ADD CRC field at end of frame */ + +/* DMA_DSCR_CNTL */ +#define DMA_DSCR_CNTL_XFERCOUNT 0x00000FFF +#define DMA_DSCR_CNTL_NXTEN 0x00004000 + +/* DMA_DSCR_ADDR */ +#define DMA_DSCR_ADDR 0xFFFFFFFC /* for DMA Start Address (32 bit Word Align) */ +#define DMA_DSCR_ADDR_FIX_ADDR 0x00000002 /* Disable incrementing of DMA_ADDR */ +#define DMA_DSCR_ADDR_WRAPEN_SET 0x00000001 +#define DMA_DSCR_ADDR_WRAPEN_RST 0x00000000 + +/* DMA_DSCR_NEXT_ADDR TX/RX */ +#define DMA_DSCR_NXT_DSCR_ADDR 0xFFFFFFFC /* Points to Next descriptor starting address */ +#define DMA_DSCR_NXT_NPOL_EN 0x00000001 /* Next Descriptor Polling Enable */ +#define DMA_DSCR_NXT_NEXT_EN 0x00000002 /* Next Descriptor Fetch mode Enable */ + +/* DMA Descriptor Packet Status: TX */ +#define DMA_DSCR_TX_STATUS_FA_MSK 0x00000001 /* Frame Aborted */ +#define DMA_DSCR_TX_STATUS_JTO_MSK 0x00000002 /* Jabber Timeout. */ +#define DMA_DSCR_TX_STATUS_NOC_MSK 0x00000004 /* No Carrier */ +#define DMA_DSCR_TX_STATUS_LOC_MSK 0x00000008 /* Loss of Carrier */ +#define DMA_DSCR_TX_STATUS_EXCD_MSK 0x00000010 /* Excessive Deferral */ +#define DMA_DSCR_TX_STATUS_LCOLL_MSK 0x00000020 /* Late Collision */ +#define DMA_DSCR_TX_STATUS_ECOLL_MSK 0x00000040 /* Excessive Collisions */ +#define DMA_DSCR_TX_STATUS_URUN_MSK 0x00000080 /* Under Run */ +#define DMA_DSCR_TX_STATUS_DEFER_MSK 0x00000100 /* Deferred */ +#define DMA_DSCR_TX_STATUS_LCOLLO_MSK 0x00000200 /* Late Collision Observed */ +#define DMA_DSCR_TX_STATUS_CCNT_MSK 0x00003C00 /* Collision Count */ +#define DMA_DSCR_TX_STATUS_HBFAIL_MSK 0x00004000 /* Heart Beat Fail */ +#define DMA_DSCR_TX_STATUS_VALID_MSK 0x00010000 /* Valid bit indicator - This bit marks the dscriptors this word belong */ +#define DMA_DSCR_TX_STATUS_PKT_RTRY_MSK 0x80000000 /* Packet Retry */ +#define DMA_DSCR_TX_STATUS_ORED_ERR_MSK 0x000003D7 /* for total number of errors */ + +/* DMA Descriptor Packet Status: RX */ +#define DMA_DSCR_RX_STATUS_FLEN_MSK 0x000007ff /* 0x00003FFF * Frame Length (max 2047) */ +#define DMA_DSCR_RX_STATUS_FTLONG_MSK 0x00001000 /* Over Lenght */ +#define DMA_DSCR_RX_STATUS_FCI_MSK 0x00002000 /* Frame too Long */ +#define DMA_DSCR_RX_STATUS_WDTO_MSK 0x00004000 /* Watchdog Timeout */ +#define DMA_DSCR_RX_STATUS_RUNTFR_MSK 0x00008000 /* Runt Frame */ +#define DMA_DSCR_RX_STATUS_VALID_MSK 0x00010000 /* Valid bit indicator - This bit marks the dscriptors this word */ +#define DMA_DSCR_RX_STATUS_COLLSEEN_MSK 0x00020000 /* Collision Seen */ +#define DMA_DSCR_RX_STATUS_FTYPE_MSK 0x00040000 /* Frame Type */ +#define DMA_DSCR_RX_STATUS_MII_ERR_MSK 0x00080000 /* MII Error */ +#define DMA_DSCR_RX_STATUS_DRBBIT_MSK 0x00100000 /* Dribbling Bit */ +#define DMA_DSCR_RX_STATUS_CRC_ERR_MSK 0x00200000 /* CRC Error */ +#define DMA_DSCR_RX_STATUS_VLAN1_FR_MSK 0x00400000 /* One-Level VLAN Frame */ +#define DMA_DSCR_RX_STATUS_VLAN2_FR_MSK 0x00800000 /* Two-Level VLAN Frame */ +#define DMA_DSCR_RX_STATUS_LEN_ERR_MSK 0x01000000 /* Length Error */ +#define DMA_DSCR_RX_STATUS_CTL_FR_MSK 0x02000000 /* Control Frame */ +#define DMA_DSCR_RX_STATUS_UCTRL_FR_MSK 0x04000000 /* Unsupported Control Frame */ +#define DMA_DSCR_RX_STATUS_MCAST_FR_MSK 0x08000000 /* Multicast Frame */ +#define DMA_DSCR_RX_STATUS_BCAST_FR_MSK 0x10000000 /* BroadCast Frame */ +#define DMA_DSCR_RX_STATUS_FLT_FAIL_MSK 0x20000000 /* Filtering Fail */ +#define DMA_DSCR_RX_STATUS_PKT_FILT_MSK 0x40000000 /* Packet Filter */ +#define DMA_DSCR_RX_STATUS_MIS_FR_MSK 0x80000000 /* Missed Frame */ +#define DMA_DSCR_RX_STATUS_ERROR_MSK (DMA_DSCR_RX_STATUS_LEN_ERR | DMA_DSCR_RX_STATUS_CRC_ERR | \ + DMA_DSCR_RX_STATUS_MII_ERR | DMA_DSCR_RX_STATUS_RUNTFR | \ + DMA_DSCR_RX_STATUS_FTLONG | DMA_DSCR_RX_STATUS_COLLSEEN) +#define DMA_DSCR_RX_STATUS_ORED_ERR_MSK 0x00000000 /*Mask for total number of errors */ + + +#endif /* _ENET_H_ */ + +/******************** (C) COPYRIGHT 2006 STMicroelectronics *******************/ + diff --git a/20080212/Demo/ARM9_STR91X_IAR/Library/include/91x_fmi.h b/20080212/Demo/ARM9_STR91X_IAR/Library/include/91x_fmi.h new file mode 100644 index 000000000..06e811567 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/Library/include/91x_fmi.h @@ -0,0 +1,184 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_fmi.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* FMI software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + + +/* Define to prevent recursive inclusion ------------------------------------ */ + +#ifndef __91x_FMI_H +#define __91x_FMI_H + +/* ========================================================================== */ +/* When bank 1 is remapped at address 0x0, decomment the following line */ +/* ========================================================================== */ + +//#define Remap_Bank_1 + + +/* Includes ------------------------------------------------------------------*/ + +#include "91x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* FMI banks */ + +#ifdef Remap_Bank_1 + +#define FMI_BANK_0 ((*(vu32*)0x54000010) << 2) /* FMI Bank 0 */ +#define FMI_BANK_1 ((*(vu32*)0x5400000C) << 2) /* FMI Bank 1 */ + +#else /* Remap Bank 0 */ + +#define FMI_BANK_0 ((*(vu32*)0x5400000C) << 2) /* FMI Bank 0 */ +#define FMI_BANK_1 ((*(vu32*)0x54000010) << 2) /* FMI Bank 1 */ + +#endif + +/* FMI sectors */ + +#define FMI_B0S0 0x00000000 + FMI_BANK_0 /* Bank 0 sector 0 */ +#define FMI_B0S1 0x00010000 + FMI_BANK_0 /* Bank 0 sector 1 */ +#define FMI_B0S2 0x00020000 + FMI_BANK_0 /* Bank 0 sector 2 */ +#define FMI_B0S3 0x00030000 + FMI_BANK_0 /* Bank 0 sector 3 */ +#define FMI_B0S4 0x00040000 + FMI_BANK_0 /* Bank 0 sector 4 */ +#define FMI_B0S5 0x00050000 + FMI_BANK_0 /* Bank 0 sector 5 */ +#define FMI_B0S6 0x00060000 + FMI_BANK_0 /* Bank 0 sector 6 */ +#define FMI_B0S7 0x00070000 + FMI_BANK_0 /* Bank 0 sector 7 */ + +#define FMI_B1S0 0x00000000 + FMI_BANK_1 /* Bank 1 sector 0 */ +#define FMI_B1S1 0x00002000 + FMI_BANK_1 /* Bank 1 sector 1 */ +#define FMI_B1S2 0x00004000 + FMI_BANK_1 /* Bank 1 sector 2 */ +#define FMI_B1S3 0x00006000 + FMI_BANK_1 /* Bank 1 sector 3 */ + +/* FMI Flags */ + +#define FMI_FLAG_SPS 0x02 /* Sector Protection Status Flag */ +#define FMI_FLAG_PSS 0x04 /* Program Suspend Status Flag */ +#define FMI_FLAG_PS 0x10 /* Program Status Flag */ +#define FMI_FLAG_ES 0x20 /* Erase Status Flag */ +#define FMI_FLAG_ESS 0x40 /* Erase Suspend Status Flag */ +#define FMI_FLAG_PECS 0x80 /* FPEC Status Flag */ + +/* FMI read wait states */ + +#define FMI_READ_WAIT_STATE_1 0x0000 /* One read wait state */ +#define FMI_READ_WAIT_STATE_2 0x2000 /* Two read wait states */ +#define FMI_READ_WAIT_STATE_3 0x4000 /* Three read wait states */ + +/* FMI write wait states */ + +#define FMI_WRITE_WAIT_STATE_0 0xFFFFFEFF /* Zero wait state */ +#define FMI_WRITE_WAIT_STATE_1 0x00000100 /* One wait state */ + +/* FMI power down configuration */ + +#define FMI_PWD_ENABLE 0x1000 /* FMI Power Down Enable */ +#define FMI_PWD_DISABLE 0x0000 /* FMI Power Down Disable */ + +/* FMI low voltage detector */ + +#define FMI_LVD_ENABLE 0x0000 /* FMI Low Voltage Detector Enable */ +#define FMI_LVD_DISABLE 0x0800 /* FMI Low Voltage Detector Disable */ + +/* FMI frequency range */ + +#define FMI_FREQ_LOW 0x0000 /* FMI Low bus working frequency */ +#define FMI_FREQ_HIGH 0x0040 /* FMI High bus working gfrequency */ + /* Above 66 MHz*/ +/* FMI OTP word addresses */ + +#define FMI_OTP_WORD_0 0x00 /* OTP word 0 */ +#define FMI_OTP_WORD_1 0x04 /* OTP word 1 */ +#define FMI_OTP_WORD_2 0x08 /* OTP word 2 */ +#define FMI_OTP_WORD_3 0x0C /* OTP word 3 */ +#define FMI_OTP_WORD_4 0x10 /* OTP word 4 */ +#define FMI_OTP_WORD_5 0x14 /* OTP word 5 */ +#define FMI_OTP_WORD_6 0x18 /* OTP word 6 */ +#define FMI_OTP_WORD_7 0x1C /* OTP word 7 */ + +/* FMI OTP halfword addresses */ + +#define FMI_OTP_LOW_HALFWORD_0 0x00 /* OTP Low halfword 0 */ +#define FMI_OTP_HIGH_HALFWORD_0 0x02 /* OTP High halfword 0 */ +#define FMI_OTP_LOW_HALFWORD_1 0x04 /* OTP Low halfword 1 */ +#define FMI_OTP_HIGH_HALFWORD_1 0x06 /* OTP High halfword 1 */ +#define FMI_OTP_LOW_HALFWORD_2 0x08 /* OTP Low halfword 2 */ +#define FMI_OTP_HIGH_HALFWORD_2 0x0A /* OTP High halfword 2 */ +#define FMI_OTP_LOW_HALFWORD_3 0x0C /* OTP Low halfword 3 */ +#define FMI_OTP_HIGH_HALFWORD_3 0x0E /* OTP High halfword 3 */ +#define FMI_OTP_LOW_HALFWORD_4 0x10 /* OTP Low halfword 4 */ +#define FMI_OTP_HIGH_HALFWORD_4 0x12 /* OTP High halfword 4 */ +#define FMI_OTP_LOW_HALFWORD_5 0x14 /* OTP Low halfword 5 */ +#define FMI_OTP_HIGH_HALFWORD_5 0x16 /* OTP High halfword 5 */ +#define FMI_OTP_LOW_HALFWORD_6 0x18 /* OTP Low halfword 6 */ +#define FMI_OTP_HIGH_HALFWORD_6 0x1A /* OTP High halfword 6 */ +#define FMI_OTP_LOW_HALFWORD_7 0x1C /* OTP Low halfword 7 */ +#define FMI_OTP_HIGH_HALFWORD_7 0x1E /* OTP High halfword 7 */ + +/* FMI sectors Masks */ + +#define FMI_B0S0_MASK 0x0001 /* FMI B0S0 mask */ +#define FMI_B0S1_MASK 0x0002 /* FMI B0S1 mask */ +#define FMI_B0S2_MASK 0x0004 /* FMI B0S2 mask */ +#define FMI_B0S3_MASK 0x0008 /* FMI B0S3 mask */ +#define FMI_B0S4_MASK 0x0010 /* FMI B0S4 mask */ +#define FMI_B0S5_MASK 0x0020 /* FMI B0S5 mask */ +#define FMI_B0S6_MASK 0x0040 /* FMI B0S6 mask */ +#define FMI_B0S7_MASK 0x0080 /* FMI B0S7 mask */ + +#define FMI_B1S0_MASK 0x0100 /* FMI B1S0 mask */ +#define FMI_B1S1_MASK 0x0200 /* FMI B1S1 mask */ +#define FMI_B1S2_MASK 0x0400 /* FMI B1S2 mask */ +#define FMI_B1S3_MASK 0x0800 /* FMI B1S3 mask */ + +/* Timeout error */ + +#define FMI_TIME_OUT_ERROR 0x00 /* Timeout error */ +#define FMI_NO_TIME_OUT_ERROR 0x01 /* No Timeout error */ + +/* Module private variables --------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void FMI_BankRemapConfig(u8 FMI_BootBankSize, u8 FMI_NonBootBankSize, \ + u32 FMI_BootBankAddress, u32 FMI_NonBootBankAddress); +void FMI_Config(u16 FMI_ReadWaitState, u32 FMI_WriteWaitState, u16 FMI_PWD,\ + u16 FMI_LVDEN, u16 FMI_FreqRange); +void FMI_EraseSector(vu32 FMI_Sector); +void FMI_EraseBank(vu32 FMI_Bank); +void FMI_WriteHalfWord(u32 FMI_Address, u16 FMI_Data); +void FMI_WriteOTPHalfWord(u8 FMI_OTPHWAddress, u16 FMI_OTPData); +u32 FMI_ReadWord(u32 FMI_Address); +u32 FMI_ReadOTPData(u8 FMI_OTPAddress); +FlagStatus FMI_GetFlagStatus(u8 FMI_Flag, vu32 FMI_Bank); +u16 FMI_GetReadWaitStateValue(void); +u16 FMI_GetWriteWaitStateValue(void); +void FMI_SuspendEnable(vu32 FMI_Bank); +void FMI_ResumeEnable(vu32 FMI_Bank); +void FMI_ClearFlag(vu32 FMI_Bank); +void FMI_WriteProtectionCmd(vu32 FMI_Sector, FunctionalState FMI_NewState); +FlagStatus FMI_GetWriteProtectionStatus(u32 FMI_Sector_Protection); +u8 FMI_WaitForLastOperation(vu32 FMI_Bank); + +#endif /* __91x_FMI_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ + diff --git a/20080212/Demo/ARM9_STR91X_IAR/Library/include/91x_gpio.h b/20080212/Demo/ARM9_STR91X_IAR/Library/include/91x_gpio.h new file mode 100644 index 000000000..f4e565804 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/Library/include/91x_gpio.h @@ -0,0 +1,93 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_gpio.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* GPIO software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion ------------------------------------ */ + +#ifndef _91x_GPIO_H +#define _91x_GPIO_H + +/* Includes ------------------------------------------------------------------*/ +#include "91x_map.h" + +/* GPIO Init structure definition */ +typedef struct +{ + u8 GPIO_Pin; + u8 GPIO_Direction; + u8 GPIO_Type; + u8 GPIO_IPConnected; + u16 GPIO_Alternate; +}GPIO_InitTypeDef; + +/* Bit_SET and Bit_RESET enumeration */ +typedef enum +{ Bit_RESET = 0, + Bit_SET +}BitAction; + + +/* Exported constants --------------------------------------------------------*/ +#define GPIO_Pin_None 0x00 +#define GPIO_Pin_0 0x01 +#define GPIO_Pin_1 0x02 +#define GPIO_Pin_2 0x04 +#define GPIO_Pin_3 0x08 +#define GPIO_Pin_4 0x10 +#define GPIO_Pin_5 0x20 +#define GPIO_Pin_6 0x40 +#define GPIO_Pin_7 0x80 +#define GPIO_Pin_All 0xFF + +#define GPIO_PinInput 0x00 +#define GPIO_PinOutput 0x01 + +#define GPIO_Type_PushPull 0x00 +#define GPIO_Type_OpenCollector 0x01 + +#define GPIO_IPConnected_Disable 0x00 +#define GPIO_IPConnected_Enable 0x01 + +#define GPIO_InputAlt1 0x00 +#define GPIO_OutputAlt1 0x01 +#define GPIO_OutputAlt2 0x02 +#define GPIO_OutputAlt3 0x03 + +#define GPIO_ANAChannel0 0x01 +#define GPIO_ANAChannel1 0x02 +#define GPIO_ANAChannel2 0x04 +#define GPIO_ANAChannel3 0x08 +#define GPIO_ANAChannel4 0x10 +#define GPIO_ANAChannel5 0x20 +#define GPIO_ANAChannel6 0x40 +#define GPIO_ANAChannel7 0x80 +#define GPIO_ANAChannelALL 0xFF + +void GPIO_DeInit(GPIO_TypeDef* GPIOx); +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); +u8 GPIO_ReadBit(GPIO_TypeDef* GPIOx, u8 GPIO_Pin); +u8 GPIO_Read(GPIO_TypeDef* GPIOx); +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u8 GPIO_Pin, BitAction BitVal); +void GPIO_Write(GPIO_TypeDef* GPIOx, u8 PortVal); +void GPIO_EMIConfig(FunctionalState NewState); +void GPIO_ANAPinConfig(u8 GPIO_ANAChannel, FunctionalState NewState); + +#endif /* _91x_GPIO_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM9_STR91X_IAR/Library/include/91x_it.h b/20080212/Demo/ARM9_STR91X_IAR/Library/include/91x_it.h new file mode 100644 index 000000000..a8e35fcb1 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/Library/include/91x_it.h @@ -0,0 +1,73 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_it.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains the headers of the interrupt +* handlers'routines +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion ------------------------------------ */ +#ifndef _91x_IT_H +#define _91x_IT_H + +/* Includes ------------------------------------------------------------------*/ +#include "91x_lib.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Module private variables --------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void Undefined_Handler (void); +void SWI_Handler (void); +void Prefetch_Handler (void); +void Abort_Handler (void); +void FIQ_Handler (void); +void WDG_IRQHandler (void); +void SW_IRQHandler (void); +void ARMRX_IRQHandler (void); +void ARMTX_IRQHandler (void); +void TIM0_IRQHandler (void); +void TIM1_IRQHandler (void); +void TIM2_IRQHandler (void); +void TIM3_IRQHandler (void); +void USBHP_IRQHandler (void); +void USBLP_IRQHandler (void); +void SCU_IRQHandler (void); +void ENET_IRQHandler (void); +void DMA_IRQHandler (void); +void CAN_IRQHandler (void); +void MC_IRQHandler (void); +void ADC_IRQHandler (void); +void UART0_IRQHandler (void); +void UART1_IRQHandler (void); +void UART2_IRQHandler (void); +void I2C0_IRQHandler (void); +void I2C1_IRQHandler (void); +void SSP0_IRQHandler (void); +void SSP1_IRQHandler (void); +void LVD_IRQHandler (void); +void RTC_IRQHandler (void); +void WIU_IRQHandler (void); +void EXTIT0_IRQHandler (void); +void EXTIT1_IRQHandler (void); +void EXTIT2_IRQHandler (void); +void EXTIT3_IRQHandler (void); +void USBWU_IRQHandler (void); +void PFQBC_IRQHandler (void); + +#endif /* _91x_IT_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM9_STR91X_IAR/Library/include/91x_lib.h b/20080212/Demo/ARM9_STR91X_IAR/Library/include/91x_lib.h new file mode 100644 index 000000000..823b25012 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/Library/include/91x_lib.h @@ -0,0 +1,114 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_lib.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : Used to include the peripherals header file in the +* user application. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +#ifndef __91x_LIB_H +#define __91x_LIB_H + +#include "91x_map.h" +#include "91x_conf.h" + +#ifdef _AHBAPB + #include "91x_ahbapb.h" +#endif /* _AHBAPB */ + +#ifdef _EMI + #include "91x_emi.h" +#endif /* _EMI */ + +#ifdef _DMA + #include "91x_dma.h" +#endif /* _DMA */ + +#ifdef _FMI + #include "91x_fmi.h" +#endif /* _FMI */ + +#ifdef _VIC + #include "91x_vic.h" +#endif /* _VIC */ + +#ifdef _WIU + #include "91x_wiu.h" +#endif /* _WIU */ + +#ifdef _TIM + #include "91x_tim.h" +#endif /* _TIM */ + +#ifdef _GPIO + #include "91x_gpio.h" +#endif /* _GPIO */ + +#ifdef _RTC + #include "91x_rtc.h" +#endif /* _RTC */ + +#ifdef _SCU + #include "91x_scu.h" +#endif /* _SCU */ + +#ifdef _UART + #include "91x_uart.h" +#endif /* _UART */ + +#ifdef _SSP + #include "91x_ssp.h" +#endif /* _SSP */ + +#ifdef _CAN + #include "91x_can.h" +#endif /* _CAN */ + +#ifdef _ADC + #include "91x_adc.h" +#endif /* _ADC */ + +#ifdef _WDG + #include "91x_wdg.h" +#endif /* _WDG */ + +#ifdef _I2C + #include "91x_i2c.h" +#endif /* _I2C */ + +#ifdef _WIU + #include "91x_wiu.h" +#endif + +#ifdef _MC + #include "91x_mc.h" +#endif + +#ifdef _ENET + #include "91x_enet.h" +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Module private variables --------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + + void debug( void ); + + +#endif /* __91x_LIB_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM9_STR91X_IAR/Library/include/91x_map.h b/20080212/Demo/ARM9_STR91X_IAR/Library/include/91x_map.h new file mode 100644 index 000000000..147302ff6 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/Library/include/91x_map.h @@ -0,0 +1,878 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_map.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : Peripherals registers definition and memory mapping. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion ------------------------------------ */ +#ifndef __91x_MAP_H +#define __91x_MAP_H + +#ifndef EXT + #define EXT extern +#endif /* EXT */ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_conf.h" +#include "91x_type.h" + +/******************************************************************************/ +/* IP registers structures */ +/******************************************************************************/ + +/*------------------------------------ FMI -----------------------------------*/ + +typedef struct +{ + vu32 BBSR; /* Boot Bank Size Register */ + vu32 NBBSR; /* Non-Boot Bank Size Register */ + vu32 EMPTY1; + vu32 BBADR; /* Boot Bank Base Address Register */ + vu32 NBBADR; /* Non-Boot Bank Base Address Register */ + vu32 EMPTY2; + vu32 CR; /* Control Register */ + vu32 SR; /* Status Register */ + vu32 BCE5ADDR; /* BC Fifth Entry Target Address Register */ +} FMI_TypeDef; + +/*---------------------- Analog to Digital Convertor ------------------------*/ + +typedef struct +{ + vu16 CR; /* Control Register */ + vu16 EMPTY1; + vu16 CCR; /* Channel Configuration Register */ + vu16 EMPTY2; + vu16 HTR; /* Higher Threshold Register */ + vu16 EMPTY3; + vu16 LTR; /* Lower Threshold Register */ + vu16 EMPTY4; + vu16 CRR; /* Compare Result Register */ + vu16 EMPTY5; + vu16 DR0; /* Data Register for Channel 0 */ + vu16 EMPTY6; + vu16 DR1; /* Data Register for Channel 1 */ + vu16 EMPTY7; + vu16 DR2; /* Data Register for Channel 2 */ + vu16 EMPTY8; + vu16 DR3; /* Data Register for Channel 3 */ + vu16 EMPTY9; + vu16 DR4; /* Data Register for Channel 4 */ + vu16 EMPTY10; + vu16 DR5; /* Data Register for Channel 5 */ + vu16 EMPTY11; + vu16 DR6; /* Data Register for Channel 6 */ + vu16 EMPTY12; + vu16 DR7; /* Data Register for Channel 7 */ + vu16 EMPTY13; + vu16 PRS; /* Prescaler Value Register */ + vu16 EMPTY14; +} ADC_TypeDef; + +/*--------------------- AHB APB BRIDGE registers strcture --------------------*/ + +typedef struct +{ + vu32 BSR; /* Bridge Status Register */ + vu32 BCR; /* Bridge Configuration Register */ + vu32 PAER; /* Peripheral Address Error register */ +} AHBAPB_TypeDef; + +/*--------------- Controller Area Network Interface Register -----------------*/ + +typedef struct +{ + vu16 CRR; /* IFn Command request Register */ + vu16 EMPTY1; + vu16 CMR; /* IFn Command Mask Register */ + vu16 EMPTY2; + vu16 M1R; /* IFn Message Mask 1 Register */ + vu16 EMPTY3; + vu16 M2R; /* IFn Message Mask 2 Register */ + vu16 EMPTY4; + vu16 A1R; /* IFn Message Arbitration 1 Register */ + vu16 EMPTY5; + vu16 A2R; /* IFn Message Arbitration 2 Register */ + vu16 EMPTY6; + vu16 MCR; /* IFn Message Control Register */ + vu16 EMPTY7; + vu16 DA1R; /* IFn DATA A 1 Register */ + vu16 EMPTY8; + vu16 DA2R; /* IFn DATA A 2 Register */ + vu16 EMPTY9; + vu16 DB1R; /* IFn DATA B 1 Register */ + vu16 EMPTY10; + vu16 DB2R; /* IFn DATA B 2 Register */ + vu16 EMPTY11[27]; +} CAN_MsgObj_TypeDef; + +typedef struct +{ + vu16 CR; /* Control Register */ + vu16 EMPTY1; + vu16 SR; /* Status Register */ + vu16 EMPTY2; + vu16 ERR; /* Error counter Register */ + vu16 EMPTY3; + vu16 BTR; /* Bit Timing Register */ + vu16 EMPTY4; + vu16 IDR; /* Interrupt Identifier Register */ + vu16 EMPTY5; + vu16 TESTR; /* Test Register */ + vu16 EMPTY6; + vu16 BRPR; /* BRP Extension Register */ + vu16 EMPTY7[3]; + CAN_MsgObj_TypeDef sMsgObj[2]; + vu16 EMPTY8[16]; + vu16 TXR1R; /* Transmission request 1 Register */ + vu16 EMPTY9; + vu16 TXR2R; /* Transmission Request 2 Register */ + vu16 EMPTY10[13]; + vu16 ND1R; /* New Data 1 Register */ + vu16 EMPTY11; + vu16 ND2R; /* New Data 2 Register */ + vu16 EMPTY12[13]; + vu16 IP1R; /* Interrupt Pending 1 Register */ + vu16 EMPTY13; + vu16 IP2R; /* Interrupt Pending 2 Register */ + vu16 EMPTY14[13]; + vu16 MV1R; /* Message Valid 1 Register */ + vu16 EMPTY15; + vu16 MV2R; /* Message VAlid 2 Register */ + vu16 EMPTY16; +} CAN_TypeDef; + +/*----------------------- System Control Unit---------------------------------*/ + +typedef struct +{ + vu32 CLKCNTR; /* Clock Control Register */ + vu32 PLLCONF; /* PLL Configuration Register */ + vu32 SYSSTATUS; /* System Status Register */ + vu32 PWRMNG; /* Power Management Register */ + vu32 ITCMSK; /* Interrupt Mask Register */ + vu32 PCGRO; /* Peripheral Clock Gating Register 0 */ + vu32 PCGR1; /* Peripheral Clock Gating Register 1 */ + vu32 PRR0; /* Peripheral Reset Register 0 */ + vu32 PRR1; /* Peripheral Reset Register 1 */ + vu32 MGR0; /* Idle Mode Mask Gating Register 0 */ + vu32 MGR1; /* Idle Mode Mask Gating Register 1 */ + vu32 PECGR0; /* Peripheral Emulation Clock Gating Register 0 */ + vu32 PECGR1; /* Peripheral Emulation Clock Gating Register 1 */ + vu32 SCR0; /* System Configuration Register 0 */ + vu32 SCR1; /* System Configuration Register 1 */ + vu32 SCR2; /* System Configuration Register 2 */ + u32 EMPTY1; + vu32 GPIOOUT[8]; /* GPIO Output Registers */ + vu32 GPIOIN[8]; /* GPIO Input Registers */ + vu32 GPIOTYPE[10]; /* GPIO Type Registers */ + vu32 GPIOEMI; /* GPIO EMI Selector Register */ + vu32 WKUPSEL; /* Wake-Up Selection Register */ + u32 EMPTY2[2]; + vu32 GPIOANA; /* GPIO Analag mode Register */ +} SCU_TypeDef; + +/*------------------------- DMA Channelx Registers ---------------------------*/ + +typedef struct +{ + vu32 SRC; /* Channelx Source Address Register */ + vu32 DES; /* Channelx Destination Address Register */ + vu32 LLI; /* Channelx Lincked List Item Register */ + vu32 CC; /* Channelx Contol Register */ + vu32 CCNF; /* Channelx Configuration Register */ +} DMA_Channel_TypeDef; + +/* x can be ,0,1,2,3,4,5,6 or 7. There are eight Channels AHB BUS Master */ + +/*----------------------------- DMA Controller -------------------------------*/ + +typedef struct +{ + vu32 ISR; /* Interrupt Status Register */ + vu32 TCISR; /* Terminal Count Interrupt Status Register */ + vu32 TCICR; /* Terminal CountInterrupt Clear Register */ + vu32 EISR; /* Error Interrupt Status Register */ + vu32 EICR; /* Error Interrupt Clear Register */ + vu32 TCRISR; /* Terminal Count Raw Interrupt Status Register */ + vu32 ERISR; /* Raw Error Interrupt Status Register */ + vu32 ENCSR; /* Enabled Channel Status Register */ + vu32 SBRR; /* Software Burst Request Register */ + vu32 SSRR; /* Software Single Request Register */ + vu32 SLBRR; /* Software Last Burst Request Register */ + vu32 SLSRR; /* Software Last Single Request Register */ + vu32 CNFR; /* Configuration Register */ + vu32 SYNR; /* Syncronization Register */ +} DMA_TypeDef; + +/*--------------------------------- TIM Timer --------------------------------*/ + +typedef struct +{ + vu16 IC1R; /* Input Capture 1 Register */ + vu16 EMPTY1; + vu16 IC2R; /* Input Capture 2 Register */ + vu16 EMPTY2; + vu16 OC1R; /* Output Compare 1 Register */ + vu16 EMPTY3; + vu16 OC2R; /* Output Compare 2 Register */ + vu16 EMPTY4; + vu16 CNTR; /* Counter Register */ + vu16 EMPTY5; + vu16 CR1; /* Control Register 1 */ + vu16 EMPTY6; + vu16 CR2; /* Control Register 2 */ + vu16 EMPTY7; + vu16 SR; /* Status Register */ + vu16 EMPTY8; +} TIM_TypeDef; + +/*---------------------------- EMI Bankx Registers ---------------------------*/ + +typedef struct +{ + vu32 ICR; /* Bankx Idle Cycle Control Register */ + vu32 RCR; /* Bankx Read Wait State Control Register */ + vu32 WCR; /* Bankx Write Wait State Control Register */ + vu32 OECR; /* Bankx Output Enable Assertion Delay Control Register */ + vu32 WECR; /* Bankx Write Enable Assertion Delay Control Register */ + vu32 BCR; /* Bankx Control Register */ + } EMI_Bank_TypeDef; + +/*---------------------------- Ethernet Controller ---------------------------*/ + +/* MAC Registers */ +typedef struct +{ + vu32 MCR; /* ENET Control Register */ + vu32 MAH; /* ENET Address High Register */ + vu32 MAL; /* ENET Address Low Register */ + vu32 MCHA; /* Multicast Address High Register */ + vu32 MCLA; /* Multicast Address Low Register */ + vu32 MIIA; /* MII Address Register */ + vu32 MIID; /* MII Data Register */ + vu32 MCF; /* ENET Control Frame Register */ + vu32 VL1; /* VLAN1 Register */ + vu32 VL2; /* VLAN2 register */ + vu32 MTS; /* ENET Transmission Status Register */ + vu32 MRS; /* ENET Reception Status Register */ +} ENET_MAC_TypeDef; + +/* DMA Registers */ +typedef struct +{ + vu32 SCR; /* DMA Status and Control Register */ + vu32 IER; /* DMA Interrupt Sources Enable Register */ + vu32 ISR; /* DMA Interrupt Status Register */ + vu32 CCR; /* Clock Control Relation : HCLK, PCLK and + ENET_CLK phase relations */ + vu32 RXSTR; /* Rx DMA start Register */ + vu32 RXCR; /* Rx DMA Control Register */ + vu32 RXSAR; /* Rx DMA Base Address Register */ + vu32 RXNDAR; /* Rx DMA Next Descriptor Address Register */ + vu32 RXCAR; /* Rx DMA Current Address Register */ + vu32 RXCTCR; /* Rx DMA Current Transfer Count Register */ + vu32 RXTOR; /* Rx DMA FIFO Time Out Register */ + vu32 RXSR; /* Rx DMA FIFO Status Register */ + vu32 TXSTR; /* Tx DMA start Register */ + vu32 TXCR; /* Tx DMA Control Register */ + vu32 TXSAR; /* Tx DMA Base Address Register */ + vu32 TXNDAR; /* Tx DMA Next Descriptor Address Register */ + vu32 TXCAR; /* Tx DMA Current Address Register */ + vu32 TXTCR; /* Tx DMA Current Transfer Count Register */ + vu32 TXTOR; /* Tx DMA FIFO Time Out Register */ + vu32 TXSR; /* Tx DMA FIFO Status Register */ +} ENET_DMA_TypeDef; + +/*------------------------------------- GPIO ---------------------------------*/ + +typedef struct +{ + vu8 DR[1021]; /* Data Register */ + vu32 DDR; /* Data Direction Register */ +} GPIO_TypeDef; + +/*-------------------------------- I2C interface -----------------------------*/ + +typedef struct +{ + vu8 CR; /* Control Register */ + vu8 EMPTY1[3]; + vu8 SR1; /* Status Register 1 */ + vu8 EMPTY2[3]; + vu8 SR2; /* Status Register 2 */ + vu8 EMPTY3[3]; + vu8 CCR; /* Clock Control Register */ + vu8 EMPTY4[3]; + vu8 OAR1; /* Own Address Register 1 */ + vu8 EMPTY5[3]; + vu8 OAR2; /* Own Address Register 2 */ + vu8 EMPTY6[3]; + vu8 DR; /* Data Register */ + vu8 EMPTY7[3]; + vu8 ECCR; /* Extended Clock Control Register */ + vu8 EMPTY8[3]; +} I2C_TypeDef; + +/*------------------------------------- VIC ----------------------------------*/ + +typedef struct +{ + vu32 ISR; /* IRQ Status Register */ + vu32 FSR; /* FIQ Status Register */ + vu32 RINTSR; /* Raw Interrupt Status Register */ + vu32 INTSR; /* Interrupt Select Register */ + vu32 INTER; /* Interrupt Enable Register */ + vu32 INTECR; /* Interrupt Enable Clear Register */ + vu32 SWINTR; /* Software Interrupt Register */ + vu32 SWINTCR; /* Software Interrupt clear Register */ + vu32 PER; /* Protection Enable Register */ + vu32 EMPTY1[3]; + vu32 VAR; /* Vector Address Register */ + vu32 DVAR; /* Default Vector Address Register */ + vu32 EMPTY2[50]; + vu32 VAiR[16]; /* Vector Address 0-15 Register */ + vu32 EMPTY3[48]; + vu32 VCiR[16]; /* Vector Control 0-15 Register */ +} VIC_TypeDef; + +/*-------------------------------- Motor Control -----------------------------*/ + +typedef struct +{ + vu16 TCPT; /* Tacho Capture Register */ + vu16 EMPTY1; + vu16 TCMP; /* Tacho Compare Register */ + vu16 EMPTY2; + vu16 IPR; /* Input Pending Register */ + vu16 EMPTY3; + vu16 TPRS; /* Tacho Prescaler Register */ + vu16 EMPTY4; + vu16 CPRS; /* PWM Counter Prescaler Register */ + vu16 EMPTY5; + vu16 REP; /* Repetition Counter Register */ + vu16 EMPTY6; + vu16 CMPW; /* Compare Phase W Preload Register */ + vu16 EMPTY7; + vu16 CMPV; /* Compare Phase V Preload Register */ + vu16 EMPTY8; + vu16 CMPU; /* Compare Phase U Preload Register */ + vu16 EMPTY9; + vu16 CMP0; /* Compare 0 Preload Register */ + vu16 EMPTY10; + vu16 PCR0; /* Peripheral Control Register 0 */ + vu16 EMPTY11; + vu16 PCR1; /* Peripheral Control Register 1 */ + vu16 EMPTY12; + vu16 PCR2; /* Peripheral Control Register 2 */ + vu16 EMPTY13; + vu16 PSR; /* Polarity Selection Register */ + vu16 EMPTY14; + vu16 OPR; /* Output Peripheral Register */ + vu16 EMPTY15; + vu16 IMR; /* Interrupt Mask Register */ + vu16 EMPTY16; + vu16 DTG; /* Dead Time Generator Register */ + vu16 EMPTY17; + vu16 ESC; /* Emergency Stop Clear Register */ + vu16 EMPTY18; +}MC_TypeDef; + +/*------------------------------------- RTC ----------------------------------*/ + +typedef struct +{ + vu32 TR; /* Time Register */ + vu32 DTR; /* Date Register */ + vu32 ATR; /* Alarm time Register */ + vu32 CR; /* Control Register */ + vu32 SR; /* Status Register */ + vu32 MILR; /* Millisec Register */ +}RTC_TypeDef; + +/*------------------------------------- SSP ----------------------------------*/ + +typedef struct +{ + vu16 CR0; /* Control Register 1 */ + vu16 EMPTY1; + vu16 CR1; /* Control Register 2 */ + vu16 EMPTY2; + vu16 DR; /* Data Register */ + vu16 EMPTY3; + vu16 SR; /* Status Register */ + vu16 EMPTY4; + vu16 PR; /* Clock Prescale Register */ + vu16 EMPTY5; + vu16 IMSCR; /* Interrupt Mask Set or Clear Register */ + vu16 EMPTY6; + vu16 RISR; /* Raw Interrupt Status Register */ + vu16 EMPTY7; + vu16 MISR; /* Masked Interrupt Status Register */ + vu16 EMPTY8; + vu16 ICR; /* Interrupt Clear Register */ + vu16 EMPTY9; + vu16 DMACR; /* DMA Control Register */ + vu16 EMPTY10; +}SSP_TypeDef; + +/*------------------------------------ UART ----------------------------------*/ + +typedef struct +{ + vu16 DR; /* Data Register */ + vu16 EMPTY1; + vu16 RSECR; /* Receive Status Register (read)/Error Clear Register (write) */ + vu16 EMPTY2[9]; + vu16 FR; /* Flag Register */ + vu16 EMPTY3[3]; + vu16 ILPR; /* IrDA Low-Power counter Register */ + vu16 EMPTY4; + vu16 IBRD; /* Integer Baud Rate Divisor Register */ + vu16 EMPTY5; + vu16 FBRD; /* Fractional Baud Rate Divisor Register */ + vu16 EMPTY6; + vu16 LCR; /* Line Control Register, High byte */ + vu16 EMPTY7; + vu16 CR; /* Control Register */ + vu16 EMPTY8; + vu16 IFLS; /* Interrupt FIFO Level Select Register */ + vu16 EMPTY9; + vu16 IMSC; /* Interrupt Mask Set/Clear Register */ + vu16 EMPTY10; + vu16 RIS; /* Raw Interrupt Status Register */ + vu16 EMPTY11; + vu16 MIS; /* Masked Interrupt Status Register */ + vu16 EMPTY12; + vu16 ICR; /* Interrupt Clear Register */ + vu16 EMPTY13; + vu16 DMACR; /* DMA Control Register */ + vu16 EMPTY14; +}UART_TypeDef; + +/*------------------------------- Wake-up System -----------------------------*/ + +typedef struct +{ + vu32 CTRL; /* Control Register */ + vu32 MR; /* Mask Register */ + vu32 TR; /* Trigger Register */ + vu32 PR; /* Pending Register */ + vu32 INTR; /* Software Interrupt Register */ +} WIU_TypeDef; + +/*------------------------------- WatchDog Timer -----------------------------*/ + +typedef struct +{ + vu16 CR; /* Control Register */ + vu16 EMPTY1; + vu16 PR; /* Presclar Register */ + vu16 EMPTY2; + vu16 VR; /* Pre-load Value Register */ + vu16 EMPTY3; + vu16 CNT; /* Counter Register */ + vu16 EMPTY4; + vu16 SR; /* Status Register */ + vu16 EMPTY5; + vu16 MR; /* Mask Register */ + vu16 EMPTY6; + vu16 KR; /* Key Register */ + vu16 EMPTY7; +} WDG_TypeDef; + +/******************************************************************************* +* Memory Mapping of STR91x * +*******************************************************************************/ + +#define AHB_APB_BRDG0_U (0x58000000) /* AHB/APB Bridge 0 UnBuffered Space */ +#define AHB_APB_BRDG0_B (0x48000000) /* AHB/APB Bridge 0 Buffered Space */ + +#define AHB_APB_BRDG1_U (0x5C000000) /* AHB/APB Bridge 1 UnBuffered Space */ +#define AHB_APB_BRDG1_B (0x4C000000) /* AHB/APB Bridge 1 Buffered Space */ + +#define AHB_EMI_U (0x74000000) /* EMI UnBuffered Space */ +#define AHB_EMI_B (0x64000000) /* EMI Buffered Space */ + +#define AHB_DMA_U (0x78000000) /* DMA UnBuffered Space */ +#define AHB_DMA_B (0x68000000) /* DMA Buffered Space */ + +#define AHB_ENET_MAC_U (0x7C000400) /* ENET_MAC UnBuffered Space */ +#define AHB_ENET_MAC_B (0x6C000400) /* ENET_MAC Buffered Space */ + +#define AHB_ENET_DMA_U (0x7C000000) /* ENET_DMA Unbuffered Space */ +#define AHB_ENET_DMA_B (0x6C000000) /* ENET_DMA Buffered Space */ + +#define AHB_VIC1_U (0xFC000000) /* Secondary VIC1 UnBuffered Space */ +#define AHB_VIC0_U (0xFFFFF000) /* Primary VIC0 UnBuffered Space */ + +#define AHB_FMI_U (0x54000000) /* FMI Unbuffered Space */ +#define AHB_FMI_B (0x44000000) /* FMI buffered Space */ + +/******************************************************************************* +* Addresses related to the VICs' peripherals * +*******************************************************************************/ + +#define VIC0_BASE (AHB_VIC0_U) +#define VIC1_BASE (AHB_VIC1_U) + +/******************************************************************************* +* Addresses related to the EMI banks * +*******************************************************************************/ + +#define AHB_EMIB3_OFST (0x00000040) /* Offset of EMI bank3 */ +#define AHB_EMIB2_OFST (0x00000020) /* Offset of EMI bank2 */ +#define AHB_EMIB1_OFST (0x00000000) /* Offset of EMI bank1 */ +#define AHB_EMIB0_OFST (0x000000E0) /* Offset of EMI bank0 */ + +/******************************************************************************* +* Addresses related to the DMA peripheral * +*******************************************************************************/ + +#define AHB_DMA_Channel0_OFST (0x00000100) /* Offset of Channel 0 */ +#define AHB_DMA_Channel1_OFST (0x00000120) /* Offset of Channel 1 */ +#define AHB_DMA_Channel2_OFST (0x00000140) /* Offset of Channel 2 */ +#define AHB_DMA_Channel3_OFST (0x00000160) /* Offset of Channel 3 */ +#define AHB_DMA_Channel4_OFST (0x00000180) /* Offset of Channel 4 */ +#define AHB_DMA_Channel5_OFST (0x000001A0) /* Offset of Channel 5 */ +#define AHB_DMA_Channel6_OFST (0x000001C0) /* Offset of Channel 6 */ +#define AHB_DMA_Channel7_OFST (0x000001E0) /* Offset of Channel 7 */ + +/******************************************************************************* +* Addresses related to the APB0 sub-system * +*******************************************************************************/ + +#define APB_WIU_OFST (0x00001000) /* Offset of WIU */ +#define APB_TIM0_OFST (0x00002000) /* Offset of TIM0 */ +#define APB_TIM1_OFST (0x00003000) /* Offset of TIM1 */ +#define APB_TIM2_OFST (0x00004000) /* Offset of TIM2 */ +#define APB_TIM3_OFST (0x00005000) /* Offset of TIM3 */ +#define APB_GPIO0_OFST (0x00006000) /* Offset of GPIO0 */ +#define APB_GPIO1_OFST (0x00007000) /* Offset of GPIO1 */ +#define APB_GPIO2_OFST (0x00008000) /* Offset of GPIO2 */ +#define APB_GPIO3_OFST (0x00009000) /* Offset of GPIO3 */ +#define APB_GPIO4_OFST (0x0000A000) /* Offset of GPIO4 */ +#define APB_GPIO5_OFST (0x0000B000) /* Offset of GPIO5 */ +#define APB_GPIO6_OFST (0x0000C000) /* Offset of GPIO6 */ +#define APB_GPIO7_OFST (0x0000D000) /* Offset of GPIO7 */ +#define APB_GPIO8_OFST (0x0000E000) /* Offset of GPIO8 */ +#define APB_GPIO9_OFST (0x0000F000) /* Offset of GPIO9 */ + +/******************************************************************************* +* Addresses related to the APB1 sub-system * +*******************************************************************************/ + +#define APB_RTC_OFST (0x00001000) /* Offset of RTC */ +#define APB_SCU_OFST (0x00002000) /* Offset of System Controller */ +#define APB_MC_OFST (0x00003000) /* Offset of Motor Control */ +#define APB_UART0_OFST (0x00004000) /* Offset of UART0 */ +#define APB_UART1_OFST (0x00005000) /* Offset of UART1 */ +#define APB_UART2_OFST (0x00006000) /* Offset of UART2 */ +#define APB_SSP0_OFST (0x00007000) /* Offset of SSP0 */ +#define APB_SSP1_OFST (0x00008000) /* Offset of SSPI */ +#define APB_CAN_OFST (0x00009000) /* Offset of CAN */ +#define APB_ADC_OFST (0x0000A000) /* Offset of ADC */ +#define APB_WDG_OFST (0x0000B000) /* Offset of WDG */ +#define APB_I2C0_OFST (0x0000C000) /* Offset of I2C0 */ +#define APB_I2C1_OFST (0x0000D000) /* Offset of I2C1 */ + +/*----------------------------------------------------------------------------*/ +/*----------------------------- Unbuffered Mode ------------------------------*/ +/*----------------------------------------------------------------------------*/ + +#ifndef Buffered + +/******************************************************************************* +* AHBAPB peripheral Unbuffered Base Address * +*******************************************************************************/ + +#define AHBAPB0_BASE (AHB_APB_BRDG0_U) +#define AHBAPB1_BASE (AHB_APB_BRDG1_U) + +/******************************************************************************* +* ENET peripheral Unbuffered Base Address * +*******************************************************************************/ + +#define ENET_MAC_BASE (AHB_ENET_MAC_U) +#define ENET_DMA_BASE (AHB_ENET_DMA_U) + +/******************************************************************************* +* DMA peripheral Unbuffered Base Address * +*******************************************************************************/ + +#define DMA_BASE (AHB_DMA_U) + +/******************************************************************************* +* EMI peripheral Unbuffered Base Address * +*******************************************************************************/ + +#define EMI_BASE (AHB_EMI_U) + +/******************************************************************************* +* FMI peripheral Unbuffered Base Address * +*******************************************************************************/ + +#define FMI_BASE (AHB_FMI_U) + + +#else /* Buffered */ + +/*----------------------------------------------------------------------------*/ +/*------------------------------ Buffered Mode -------------------------------*/ +/*----------------------------------------------------------------------------*/ + +/******************************************************************************* +* AHBAPB peripheral Buffered Base Address * +*******************************************************************************/ + +#define AHBAPB0_BASE (AHB_APB_BRDG0_B) +#define AHBAPB1_BASE (AHB_APB_BRDG1_B) + +/******************************************************************************* +* ENET peripheral Unbuffered Base Address * +*******************************************************************************/ + +#define ENET_MAC_BASE (AHB_ENET_MAC_B) +#define ENET_DMA_BASE (AHB_ENET_DMA_B) + +/******************************************************************************* +* DMA peripheral Buffered Base Address * +*******************************************************************************/ + +#define DMA_BASE (AHB_DMA_B) + +/******************************************************************************* +* EMI peripheral Buffered Base Address * +*******************************************************************************/ + +#define EMI_BASE (AHB_EMI_B) + +/******************************************************************************* +* FMI peripheral Buffered Base Address * +*******************************************************************************/ + +#define FMI_BASE (AHB_FMI_B) + +#endif /* Buffered */ + +/******************************************************************************* +* DMA channels Base Address * +*******************************************************************************/ +#define DMA_Channel0_BASE (DMA_BASE + AHB_DMA_Channel0_OFST) +#define DMA_Channel1_BASE (DMA_BASE + AHB_DMA_Channel1_OFST) +#define DMA_Channel2_BASE (DMA_BASE + AHB_DMA_Channel2_OFST) +#define DMA_Channel3_BASE (DMA_BASE + AHB_DMA_Channel3_OFST) +#define DMA_Channel4_BASE (DMA_BASE + AHB_DMA_Channel4_OFST) +#define DMA_Channel5_BASE (DMA_BASE + AHB_DMA_Channel5_OFST) +#define DMA_Channel6_BASE (DMA_BASE + AHB_DMA_Channel6_OFST) +#define DMA_Channel7_BASE (DMA_BASE + AHB_DMA_Channel7_OFST) + +/******************************************************************************* +* EMI Banks peripheral Base Address * +*******************************************************************************/ + +#define EMI_Bank0_BASE (EMI_BASE + AHB_EMIB0_OFST) +#define EMI_Bank1_BASE (EMI_BASE + AHB_EMIB1_OFST) +#define EMI_Bank2_BASE (EMI_BASE + AHB_EMIB2_OFST) +#define EMI_Bank3_BASE (EMI_BASE + AHB_EMIB3_OFST) + +/******************************************************************************* +* APB0 Peripherals' Base addresses * +*******************************************************************************/ + +#define WIU_BASE (AHBAPB0_BASE + APB_WIU_OFST) +#define TIM0_BASE (AHBAPB0_BASE + APB_TIM0_OFST) +#define TIM1_BASE (AHBAPB0_BASE + APB_TIM1_OFST) +#define TIM2_BASE (AHBAPB0_BASE + APB_TIM2_OFST) +#define TIM3_BASE (AHBAPB0_BASE + APB_TIM3_OFST) +#define GPIO0_BASE (AHBAPB0_BASE + APB_GPIO0_OFST) +#define GPIO1_BASE (AHBAPB0_BASE + APB_GPIO1_OFST) +#define GPIO2_BASE (AHBAPB0_BASE + APB_GPIO2_OFST) +#define GPIO3_BASE (AHBAPB0_BASE + APB_GPIO3_OFST) +#define GPIO4_BASE (AHBAPB0_BASE + APB_GPIO4_OFST) +#define GPIO5_BASE (AHBAPB0_BASE + APB_GPIO5_OFST) +#define GPIO6_BASE (AHBAPB0_BASE + APB_GPIO6_OFST) +#define GPIO7_BASE (AHBAPB0_BASE + APB_GPIO7_OFST) +#define GPIO8_BASE (AHBAPB0_BASE + APB_GPIO8_OFST) +#define GPIO9_BASE (AHBAPB0_BASE + APB_GPIO9_OFST) + +/******************************************************************************* +* APB1 Peripherals' Base addresses * +*******************************************************************************/ + +#define RTC_BASE (AHBAPB1_BASE + APB_RTC_OFST) +#define SCU_BASE (AHBAPB1_BASE + APB_SCU_OFST) +#define MC_BASE (AHBAPB1_BASE + APB_MC_OFST) +#define UART0_BASE (AHBAPB1_BASE + APB_UART0_OFST) +#define UART1_BASE (AHBAPB1_BASE + APB_UART1_OFST) +#define UART2_BASE (AHBAPB1_BASE + APB_UART2_OFST) +#define SSP0_BASE (AHBAPB1_BASE + APB_SSP0_OFST) +#define SSP1_BASE (AHBAPB1_BASE + APB_SSP1_OFST) +#define CAN_BASE (AHBAPB1_BASE + APB_CAN_OFST) +#define ADC_BASE (AHBAPB1_BASE + APB_ADC_OFST) +#define WDG_BASE (AHBAPB1_BASE + APB_WDG_OFST) +#define I2C0_BASE (AHBAPB1_BASE + APB_I2C0_OFST) +#define I2C1_BASE (AHBAPB1_BASE + APB_I2C1_OFST) + +/******************************************************************************* +* IPs' declaration * +*******************************************************************************/ + +/*------------------------------ Non Debug Mode ------------------------------*/ + +#ifndef DEBUG + +/*********************************** AHBAPB ***********************************/ + +#define AHBAPB0 ((AHBAPB_TypeDef *)AHBAPB0_BASE) +#define AHBAPB1 ((AHBAPB_TypeDef *)AHBAPB1_BASE) + +/************************************* EMI ************************************/ + +#define EMI ((EMI_TypeDef *)EMI_BASE) + +/************************************* DMA ************************************/ + +#define DMA ((DMA_TypeDef *)DMA_BASE) +#define DMA_Channel0 ((DMA_Channel_TypeDef *)DMA_Channel0_BASE) +#define DMA_Channel1 ((DMA_Channel_TypeDef *)DMA_Channel1_BASE) +#define DMA_Channel2 ((DMA_Channel_TypeDef *)DMA_Channel2_BASE) +#define DMA_Channel3 ((DMA_Channel_TypeDef *)DMA_Channel3_BASE) +#define DMA_Channel4 ((DMA_Channel_TypeDef *)DMA_Channel4_BASE) +#define DMA_Channel5 ((DMA_Channel_TypeDef *)DMA_Channel5_BASE) +#define DMA_Channel6 ((DMA_Channel_TypeDef *)DMA_Channel6_BASE) +#define DMA_Channel7 ((DMA_Channel_TypeDef *)DMA_Channel7_BASE) + +/************************************* EMI ************************************/ + +#define EMI_Bank0 ((EMI_Bank_TypeDef *)EMI_Bank0_BASE) +#define EMI_Bank1 ((EMI_Bank_TypeDef *)EMI_Bank1_BASE) +#define EMI_Bank2 ((EMI_Bank_TypeDef *)EMI_Bank2_BASE) +#define EMI_Bank3 ((EMI_Bank_TypeDef *)EMI_Bank3_BASE) + +/************************************* ENET_MAC ************************************/ + +#define ENET_MAC ((ENET_MAC_TypeDef *)ENET_MAC_BASE) + +/************************************* ENET_DMA ************************************/ + +#define ENET_DMA ((ENET_DMA_TypeDef *)ENET_DMA_BASE) + +/************************************* FMI ************************************/ + +#define FMI ((FMI_TypeDef *)FMI_BASE) + +/************************************* VIC ************************************/ + +#define VIC0 ((VIC_TypeDef *)VIC0_BASE) +#define VIC1 ((VIC_TypeDef *)VIC1_BASE) + +/******************************************************************************* +* APB0 Peripherals' * +*******************************************************************************/ +#define WIU ((WIU_TypeDef *)WIU_BASE) +#define TIM0 ((TIM_TypeDef *)TIM0_BASE) +#define TIM1 ((TIM_TypeDef *)TIM1_BASE) +#define TIM2 ((TIM_TypeDef *)TIM2_BASE) +#define TIM3 ((TIM_TypeDef *)TIM3_BASE) +#define GPIO0 ((GPIO_TypeDef *)GPIO0_BASE) +#define GPIO1 ((GPIO_TypeDef *)GPIO1_BASE) +#define GPIO2 ((GPIO_TypeDef *)GPIO2_BASE) +#define GPIO3 ((GPIO_TypeDef *)GPIO3_BASE) +#define GPIO4 ((GPIO_TypeDef *)GPIO4_BASE) +#define GPIO5 ((GPIO_TypeDef *)GPIO5_BASE) +#define GPIO6 ((GPIO_TypeDef *)GPIO6_BASE) +#define GPIO7 ((GPIO_TypeDef *)GPIO7_BASE) +#define GPIO8 ((GPIO_TypeDef *)GPIO8_BASE) +#define GPIO9 ((GPIO_TypeDef *)GPIO9_BASE) +/******************************************************************************* +* APB1 Peripherals' * +*******************************************************************************/ +#define RTC ((RTC_TypeDef *)RTC_BASE) +#define SCU ((SCU_TypeDef *)SCU_BASE) +#define MC ((MC_TypeDef *)MC_BASE) +#define UART0 ((UART_TypeDef *)UART0_BASE) +#define UART1 ((UART_TypeDef *)UART1_BASE) +#define UART2 ((UART_TypeDef *)UART2_BASE) +#define SSP0 ((SSP_TypeDef *)SSP0_BASE) +#define SSP1 ((SSP_TypeDef *)SSP1_BASE) +#define CAN ((CAN_TypeDef *)CAN_BASE) +#define ADC ((ADC_TypeDef *)ADC_BASE) +#define WDG ((WDG_TypeDef *)WDG_BASE) +#define I2C0 ((I2C_TypeDef *)I2C0_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) +#define ENET_MAC ((ENET_MAC_TypeDef *)ENET_MAC_BASE) +#define ENET_DMA ((ENET_DMA_TypeDef *)ENET_DMA_BASE) + +#else /* DEBUG */ + +/*-------------------------------- Debug Mode --------------------------------*/ + +EXT AHBAPB_TypeDef *AHBAPB0; +EXT AHBAPB_TypeDef *AHBAPB1; +EXT DMA_TypeDef *DMA; +EXT DMA_Channel_TypeDef *DMA_Channel0; +EXT DMA_Channel_TypeDef *DMA_Channel1; +EXT DMA_Channel_TypeDef *DMA_Channel2; +EXT DMA_Channel_TypeDef *DMA_Channel3; +EXT DMA_Channel_TypeDef *DMA_Channel4; +EXT DMA_Channel_TypeDef *DMA_Channel5; +EXT DMA_Channel_TypeDef *DMA_Channel6; +EXT DMA_Channel_TypeDef *DMA_Channel7; +EXT EMI_Bank_TypeDef *EMI_Bank0; +EXT EMI_Bank_TypeDef *EMI_Bank1; +EXT EMI_Bank_TypeDef *EMI_Bank2; +EXT EMI_Bank_TypeDef *EMI_Bank3; +EXT FMI_TypeDef *FMI; +EXT VIC_TypeDef *VIC0; +EXT VIC_TypeDef *VIC1; +EXT WIU_TypeDef *WIU; +EXT TIM_TypeDef *TIM0; +EXT TIM_TypeDef *TIM1; +EXT TIM_TypeDef *TIM2; +EXT TIM_TypeDef *TIM3; +EXT GPIO_TypeDef *GPIO0; +EXT GPIO_TypeDef *GPIO1; +EXT GPIO_TypeDef *GPIO2; +EXT GPIO_TypeDef *GPIO3; +EXT GPIO_TypeDef *GPIO4; +EXT GPIO_TypeDef *GPIO5; +EXT GPIO_TypeDef *GPIO6; +EXT GPIO_TypeDef *GPIO7; +EXT GPIO_TypeDef *GPIO8; +EXT GPIO_TypeDef *GPIO9; +EXT RTC_TypeDef *RTC; +EXT SCU_TypeDef *SCU; +EXT MC_TypeDef *MC; +EXT UART_TypeDef *UART0; +EXT UART_TypeDef *UART1; +EXT UART_TypeDef *UART2; +EXT SSP_TypeDef *SSP0; +EXT SSP_TypeDef *SSP1; +EXT CAN_TypeDef *CAN; +EXT ADC_TypeDef *ADC; +EXT WDG_TypeDef *WDG; +EXT I2C_TypeDef *I2C0; +EXT I2C_TypeDef *I2C1; +EXT ENET_MAC_TypeDef *ENET_MAC; +EXT ENET_DMA_TypeDef *ENET_DMA; + + +#endif /* DEBUG */ + +#endif /* __91x_MAP_H*/ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ + diff --git a/20080212/Demo/ARM9_STR91X_IAR/Library/include/91x_scu.h b/20080212/Demo/ARM9_STR91X_IAR/Library/include/91x_scu.h new file mode 100644 index 000000000..b9d04f558 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/Library/include/91x_scu.h @@ -0,0 +1,196 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_scu.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides the SCU library software functions +* prototypes & definitions +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __91x_SCU_H +#define __91x_SCU_H + +/* Includes ------------------------------------------------------------------*/ +#include "91x_map.h" + +/* Exported constants --------------------------------------------------------*/ + +/*MCLK_Source*/ +#define SCU_MCLK_PLL 0x0 +#define SCU_MCLK_RTC 0x1 +#define SCU_MCLK_OSC 0x2 + +/*RCLK_Divisor*/ +#define SCU_RCLK_Div1 0xFFFFFFE3 +#define SCU_RCLK_Div2 0x4 +#define SCU_RCLK_Div4 0x8 +#define SCU_RCLK_Div8 0xC +#define SCU_RCLK_Div16 0x10 +#define SCU_RCLK_Div1024 0x14 + +/*HCLK_Divisor*/ +#define SCU_HCLK_Div1 0xFFFFFF9F +#define SCU_HCLK_Div2 0x20 +#define SCU_HCLK_Div4 0x40 + +/*PCLK_Divisor*/ +#define SCU_PCLK_Div1 0xFFFFFE7F +#define SCU_PCLK_Div2 0x80 +#define SCU_PCLK_Div4 0x100 +#define SCU_PCLK_Div8 0x180 + +/*FMICLK_Divisor*/ +#define SCU_FMICLK_Div1 0xFFFEFFFF +#define SCU_FMICLK_Div2 0x10000 + +/*BRCLK_Divisor*/ +#define SCU_BRCLK_Div1 0xFFFFFDFF +#define SCU_BRCLK_Div2 0x200 + +/*TIMCLK_Source*/ +#define SCU_TIMCLK_EXT 0x1 +#define SCU_TIMCLK_INT 0x0 + +/*TIMx*/ +#define SCU_TIM01 0x0 +#define SCU_TIM23 0x1 + + +/*USBCLK_Source*/ +#define SCU_USBCLK_MCLK 0xFFFFF3FF +#define SCU_USBCLK_MCLK2 0x400 +#define SCU_USBCLK_EXT 0x800 + +/*SCU_EMIBCLK*/ +#define SCU_EMIBCLK_Div1 0xFFF9FFFF +#define SCU_EMIBCLK_Div2 0x20000 + +/*SCU_EMIMODE*/ +#define SCU_EMI_MUX 0xFFFFFFBF +#define SCU_EMI_DEMUX 0x40 + +/*SCU_EMIALE_LEN*/ +#define SCU_EMIALE_LEN1 0xFFFFFEFF +#define SCU_EMIALE_LEN2 0x100 + +/*SCU_EMIALE_POL*/ +#define SCU_EMIALE_POLLow 0xFFFFFF7F +#define SCU_EMIALE_POLHigh 0x80 + +/*UART_IrDA_Mode*/ +#define SCU_UARTMode_IrDA 0x1 +#define SCU_UARTMode_UART 0x0 + +/*APBPeriph*/ +#define __TIM01 0x1 +#define __TIM23 0x2 +#define __MC 0x4 +#define __UART0 0x8 +#define __UART1 0x10 +#define __UART2 0x20 +#define __I2C0 0x40 +#define __I2C1 0x80 +#define __SSP0 0x100 +#define __SSP1 0x200 +#define __CAN 0x400 +#define __ADC 0x800 +#define __WDG 0x1000 +#define __WIU 0x2000 +#define __GPIO0 0x4000 +#define __GPIO1 0x8000 +#define __GPIO2 0x10000 +#define __GPIO3 0x20000 +#define __GPIO4 0x40000 +#define __GPIO5 0x80000 +#define __GPIO6 0x100000 +#define __GPIO7 0x200000 +#define __GPIO8 0x400000 +#define __GPIO9 0x800000 +#define __RTC 0x1000000 + +/*AHBPeriph*/ +#define __FMI 0x1 +#define __FPQBC 0x2 +#define __SRAM 0x8 +#define __SRAM_ARBITER 0x10 +#define __VIC 0x20 +#define __EMI 0x40 +#define __EMI_MEM_CLK 0x80 +#define __DMA 0x100 +#define __USB 0x200 +#define __USB48M 0x400 +#define __ENET 0x800 +#define __PFQBC_AHB 0x1000 + +/*SCU_IT*/ +#define SCU_IT_LVD_RST 0x10 +#define SCU_IT_SRAM_ERROR 0x8 +#define SCU_IT_ACK_PFQBC 0x4 +#define SCU_IT_LOCK_LOST 0x2 +#define SCU_IT_LOCK 0x1 + +/*SCU_FLAG*/ +#define SCU_FLAG_SRAM_ERROR 0x20 +#define SCU_FLAG_ACK_PFQBC 0x10 +#define SCU_FLAG_LVD_RESET 0x8 +#define SCU_FLAG_WDG_RST 0x4 +#define SCU_FLAG_LOCK_LOST 0x2 +#define SCU_FLAG_LOCK 0x1 + + +/* Module private variables --------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +ErrorStatus SCU_MCLKSourceConfig(u32 MCLK_Source); +ErrorStatus SCU_PLLFactorsConfig(u8 PLLN, u8 PLLM, u8 PLLP); +ErrorStatus SCU_PLLCmd(FunctionalState NewState); +void SCU_RCLKDivisorConfig(u32 RCLK_Divisor); +void SCU_HCLKDivisorConfig(u32 HCLK_Divisor); +void SCU_PCLKDivisorConfig(u32 PCLK_Divisor); +void SCU_APBPeriphClockConfig(u32 APBPeriph, FunctionalState NewState); +void SCU_AHBPeriphClockConfig(u32 AHBPeriph, FunctionalState NewState); +void SCU_APBPeriphReset(u32 APBPeriph, FunctionalState NewState); +void SCU_AHBPeriphReset(u32 AHBPeriph, FunctionalState NewState); +void SCU_APBPeriphIdleConfig(u32 APBPeriph, FunctionalState NewState); +void SCU_AHBPeriphIdleConfig(u32 AHBPeriph, FunctionalState NewState); +void SCU_APBPeriphDebugConfig(u32 APBPeriph, FunctionalState NewState); +void SCU_AHBPeriphDebugConfig(u32 AHBPeriph, FunctionalState NewState); +void SCU_BRCLKDivisorConfig(u32 BRCLK_Divisor); +void SCU_TIMCLKSourceConfig(u8 TIMx, u32 TIMCLK_Source); +void SCU_TIMPresConfig(u8 TIMx, u16 Prescaler); +void SCU_USBCLKConfig(u32 USBCLK_Source); +void SCU_PHYCLKConfig(FunctionalState NewState); +void SCU_FMICLKDivisorConfig(u32 FMICLK_Divisor); +void SCU_EMIBCLKDivisorConfig(u32 SCU_EMIBCLK); +void SCU_EMIModeConfig(u32 SCU_EMIMODE); +void SCU_EMIALEConfig(u32 SCU_EMIALE_LEN, u32 SCU_EMIALE_POL); +void SCU_ITConfig(u32 SCU_IT, FunctionalState NewState); +FlagStatus SCU_GetFlagStatus(u32 SCU_Flag); +void SCU_ClearFlag(u32 SCU_Flag); +u32 SCU_GetPLLFreqValue(void); +u32 SCU_GetMCLKFreqValue(void); +u32 SCU_GetRCLKFreqValue(void); +u32 SCU_GetHCLKFreqValue(void); +u32 SCU_GetPCLKFreqValue(void); +void SCU_WakeUpLineConfig(u8 EXTint); +void SCU_SpecIntRunModeConfig(FunctionalState NewState); +void SCU_EnterIdleMode(void); +void SCU_EnterSleepMode(void); +void SCU_UARTIrDASelect(UART_TypeDef * UARTx, u8 UART_IrDA_Mode); +void SCU_PFQBCCmd(FunctionalState NewState); + +#endif /*__91x_SCU_H*/ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM9_STR91X_IAR/Library/include/91x_tim.h b/20080212/Demo/ARM9_STR91X_IAR/Library/include/91x_tim.h new file mode 100644 index 000000000..b587c27ac --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/Library/include/91x_tim.h @@ -0,0 +1,155 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_tim.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* TIM software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __91x_TIM_H +#define __91x_TIM_H + +/* Includes ------------------------------------------------------------------*/ +#include "91x_map.h" +#include "91x_scu.h" + +/* Exported types ----------------------------------------------------------- */ + +/* TIM Init structure define */ +typedef struct +{ + u16 TIM_Mode; /* Timer mode */ + u16 TIM_OC1_Modes; /* Output Compare 1 Mode: Timing or Wave */ + u16 TIM_OC2_Modes; /* Output Compare 2 Mode: Timing or Wave */ + u16 TIM_Clock_Source; /* Timer Clock source APB/SCU/EXTERNAL */ + u16 TIM_Clock_Edge; /* Timer Clock Edge: Rising or Falling Edge */ + u16 TIM_OPM_INPUT_Edge; /* Timer Input Capture 1 Edge used in OPM Mode */ + u16 TIM_ICAP1_Edge; /* Timer Input Capture 1 Edge used in ICAP1 Mode */ + u16 TIM_ICAP2_Edge; /* Timer Input Capture 2 Edge used in ICAP2 Mode */ + u8 TIM_Prescaler; /* Timer Prescaler factor */ + u16 TIM_Pulse_Level_1; /* Level applied on the Output Compare Pin 1 */ + u16 TIM_Pulse_Level_2; /* Level applied on the Output Compare Pin 2 */ + u16 TIM_Period_Level; /* Level applied during the Period of a PWM Mode */ + u16 TIM_Pulse_Length_1; /* Pulse 1 Length used in Output Compare 1 Mode */ + u16 TIM_Pulse_Length_2; /* Pulse 2 Length used in Output Compare 2 Mode */ + u16 TIM_Full_Period; /* Period Length used in PWM Mode */ +} TIM_InitTypeDef; + +typedef enum +{ + TIM_START, + TIM_STOP, + TIM_CLEAR +} TIM_CounterOperations; + +/* Exported constants --------------------------------------------------------*/ + +/* TIM MODE */ +#define TIM_PWMI 0x4000 /* PWM INPUT Mode */ +#define TIM_OCM_CHANNEL_1 0x0040 /* OUTPUT COMPARE CHANNEL 1 Mode */ +#define TIM_OCM_CHANNEL_2 0x0080 /* OUTPUT COMPARE CHANNEL 2 Mode */ +#define TIM_OCM_CHANNEL_12 0x00C0 /* OUTPUT COMPARE CHANNEL 1 & 2 Mode */ +#define TIM_PWM 0x0010 /* PWM Mode */ +#define TIM_OPM 0x0020 /* ONE PULSE Mode */ +#define TIM_ICAP_CHANNEL_1 0x0400 /* INPUT CAPTURE 1 Mode */ +#define TIM_ICAP_CHANNEL_2 0x0500 /* INPUT CAPTURE 2 Mode */ +#define TIM_ICAP_CHANNEL_12 0x0600 /* INPUT CAPTURE 1 & 2 Mode */ + +/* TIM OUTPUT COMPARE MODE */ +#define TIM_WAVE 0x0001 +#define TIM_TIMING 0x0002 + +/* TIM CLOCK SOURCE */ +#define TIM_CLK_APB 0xFFFE +#define TIM_CLK_EXTERNAL 0x0001 +#define TIM_CLK_SCU 0x0001 + +/* TIM CLOCK EDGE */ +#define TIM_CLK_EDGE_FALLING 0xFFFD +#define TIM_CLK_EDGE_RISING 0x0002 + +/* TIM OPM INPUT EDGE */ +#define TIM_OPM_EDGE_FALLING 0xFFFB +#define TIM_OPM_EDGE_RISING 0x0004 + +/* TIM ICAPA INPUT EDGE */ +#define TIM_ICAP1_EDGE_FALLING 0xFFFB +#define TIM_ICAP1_EDGE_RISING 0x0004 + +/* TIM ICAPB INPUT EDGE */ +#define TIM_ICAP2_EDGE_FALLING 0xFFF7 +#define TIM_ICAP2_EDGE_RISING 0x0008 + +/* TIM OUTPUT LEVEL */ +#define TIM_HIGH 0x0200 +#define TIM_LOW 0x0300 + +/* TIM OUTPUT EDGE */ +#define TIM_OUTPUT_EDGE_RISING 0x8000 +#define TIM_OUTPUT_EDGE_FALLING 0x0800 + +/* TIM channels */ +#define TIM_PWM_OC1_Channel 0x1 /* PWM/Output Compare 1 Channel */ +#define TIM_OC2_Channel 0x2 /* Output Compare 2 Channel */ + +/* TIM DMA SOURCE */ +#define TIM_DMA_IC1 0x0000 /* Input Capture Channel 1 DMA Source */ +#define TIM_DMA_OC1 0x1000 /* OUTPUT Compare Channel 1 DMA Source */ +#define TIM_DMA_IC2 0x2000 /* Input Capture Channel 2 DMA Source */ +#define TIM_DMA_OC2 0x3000 /* OUTPUT Compare Channel 2 DMA Source */ + +/* TIM DMA ENABLE or DISABLE */ +#define TIM_DMA_ENABLE 0x0400 /* DMA Enable */ +#define TIM_DMA_DISABLE 0xFBFF /* DMA Disable */ + +/* TIM Interruption Sources*/ +#define TIM_IT_IC1 0x8000 /* Input Capture Channel 1 Interrupt Source */ +#define TIM_IT_OC1 0x4000 /* Output Compare Channel 1 Interrupt Source */ +#define TIM_IT_TO 0x2000 /* Timer OverFlow Interrupt Source */ +#define TIM_IT_IC2 0x1000 /* Input Capture Channel 2 Interrupt Source */ +#define TIM_IT_OC2 0x0800 /* Output Compare Channel 2 Interrupt Source */ + +/* TIM Flags */ +#define TIM_FLAG_IC1 0x8000 /* Input Capture Channel 1 Flag */ +#define TIM_FLAG_OC1 0x4000 /* Output Compare Channel 1 Flag */ +#define TIM_FLAG_TO 0x2000 /* Timer OverFlow Flag */ +#define TIM_FLAG_IC2 0x1000 /* Input Capture Channel 2 Flag */ +#define TIM_FLAG_OC2 0x0800 /* Output Compare Channel 2 Flag */ + +/* Module private variables --------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void TIM_Init(TIM_TypeDef *TIMx, TIM_InitTypeDef *TIM_InitStruct); +void TIM_DeInit(TIM_TypeDef *TIMx); +void TIM_StructInit(TIM_InitTypeDef *TIM_InitStruct); +void TIM_CounterCmd(TIM_TypeDef *TIMx, TIM_CounterOperations TIM_operation); +void TIM_PrescalerConfig(TIM_TypeDef *TIMx, u8 TIM_Prescaler); +u8 TIM_GetPrescalerValue(TIM_TypeDef *TIMx); +u16 TIM_GetCounterValue(TIM_TypeDef *TIMx); +u16 TIM_GetICAP1Value(TIM_TypeDef *TIMx); +u16 TIM_GetICAP2Value(TIM_TypeDef *TIMx); +void TIM_SetPulse(TIM_TypeDef *TIMx,u16 TIM_Channel ,u16 TIM_Pulse); +FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, u16 TIM_Flag); +void TIM_ClearFlag(TIM_TypeDef *TIMx, u16 TIM_Flag); +u16 TIM_GetPWMIPulse(TIM_TypeDef *TIMx); +u16 TIM_GetPWMIPeriod(TIM_TypeDef *TIMx); +void TIM_ITConfig(TIM_TypeDef *TIMx, u16 TIM_IT, FunctionalState TIM_Newstate); +void TIM_DMAConfig(TIM_TypeDef *TIMx, u16 TIM_DMA_Sources); +void TIM_DMACmd(TIM_TypeDef *TIMx, FunctionalState TIM_Newstate); + +#endif /* __91x_TIM_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM9_STR91X_IAR/Library/include/91x_type.h b/20080212/Demo/ARM9_STR91X_IAR/Library/include/91x_type.h new file mode 100644 index 000000000..916d81c68 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/Library/include/91x_type.h @@ -0,0 +1,50 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_type.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : It contains common types and constants used in all the +* peripherals' drivers. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +********************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*********************************************************************************/ + +#ifndef __91x_type_H +#define __91x_type_H + + typedef long long u64; + typedef unsigned long u32; + typedef unsigned short u16; + typedef unsigned char u8; + + typedef signed long s32; + typedef signed short s16; + typedef signed char s8; + + typedef volatile unsigned long vu32; + typedef volatile unsigned short vu16; + typedef volatile unsigned char vu8; + + typedef volatile signed long vs32; + typedef volatile signed short vs16; + typedef volatile signed char vs8; + +typedef enum { FALSE = 0, TRUE = !FALSE } bool; + +typedef enum { RESET = 0, SET = !RESET } FlagStatus, ITStatus; + +typedef enum { DISABLE = 0, ENABLE = !DISABLE} FunctionalState; + +typedef enum { ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +#endif /* __91x_type_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM9_STR91X_IAR/Library/include/91x_uart.h b/20080212/Demo/ARM9_STR91X_IAR/Library/include/91x_uart.h new file mode 100644 index 000000000..b979438bb --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/Library/include/91x_uart.h @@ -0,0 +1,174 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_uart.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* UART software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __91x_UART_H +#define __91x_UART_H + +/* Includes ------------------------------------------------------------------*/ +#include <91x_map.h> + +/* Exported types ------------------------------------------------------------*/ +/* UART FIFO Level enumeration */ +typedef enum +{ + UART_FIFOLevel_1_8 = 0x0000, /* FIFO size 16 bytes, FIFO level 2 bytes */ + UART_FIFOLevel_1_4 = 0x0001, /* FIFO size 16 bytes, FIFO level 4 bytes */ + UART_FIFOLevel_1_2 = 0x0002, /* FIFO size 16 bytes, FIFO level 8 bytes */ + UART_FIFOLevel_3_4 = 0x0003, /* FIFO size 16 bytes, FIFO level 12 bytes */ + UART_FIFOLevel_7_8 = 0x0004 /* FIFO size 16 bytes, FIFO level 14 bytes */ +}UART_FIFOLevel; + +/* UART Init Structure definition */ +typedef struct +{ + u16 UART_WordLength; + u16 UART_StopBits; + u16 UART_Parity; + u32 UART_BaudRate; + u16 UART_HardwareFlowControl; + u16 UART_Mode; + u16 UART_FIFO; + UART_FIFOLevel UART_TxFIFOLevel; + UART_FIFOLevel UART_RxFIFOLevel; +}UART_InitTypeDef; + + +/* UART RTS enumeration */ +typedef enum +{ + LowLevel = 0, + HighLevel +}UART_LevelTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* UART Data Length */ +#define UART_WordLength_5D 0x0000 /* 5 bits Data */ +#define UART_WordLength_6D 0x0020 /* 6 bits Data */ +#define UART_WordLength_7D 0x0040 /* 7 bits Data */ +#define UART_WordLength_8D 0x0060 /* 8 bits Data */ + +/* UART Stop Bits */ +#define UART_StopBits_1 0xFFF7 /* Disable two stop bit is transmitted + at the end of frame */ +#define UART_StopBits_2 0x0008 /* Enable Two stop bits are transmitted + at the end of frame */ +/* UART Parity */ +#define UART_Parity_No 0x0000 /* Parity Disable */ +#define UART_Parity_Even 0x0006 /* Even Parity */ +#define UART_Parity_Odd 0x0002 /* Odd Parity */ +#define UART_Parity_OddStick 0x0082 /* 1 is transmitted as bit parity */ +#define UART_Parity_EvenStick 0x0086 /* 0 is transmitted as bit parity */ + +/* UART Hardware Flow Control */ +#define UART_HardwareFlowControl_None 0x0000 /* HFC Disable */ +#define UART_HardwareFlowControl_RTS 0x4000 /* RTS Enable */ +#define UART_HardwareFlowControl_CTS 0x8000 /* CTS Enable */ +#define UART_HardwareFlowControl_RTS_CTS 0xC000 /* CTS and RTS Enable */ + +/* UART Mode */ +#define UART_Mode_Rx 0x0200 /* UART Rx Enabled */ +#define UART_Mode_Tx 0x0100 /* UART Tx Enbled */ +#define UART_Mode_Tx_Rx 0x0300 /* UART Tx and Rx Enabled */ + +/* UART FIFO */ +#define UART_FIFO_Disable 0xFFEF /* FIFOs Disable */ +#define UART_FIFO_Enable 0x0010 /* FIFOs Enable */ + +/* UART Interrupt definition */ +#define UART_IT_OverrunError 0x0400 /* Overrun Error interrupt mask */ +#define UART_IT_BreakError 0x0200 /* Break Error interrupt mask */ +#define UART_IT_ParityError 0x0100 /* Parity Error interrupt mask */ +#define UART_IT_FrameError 0x0080 /* Frame Error interrupt mask */ +#define UART_IT_ReceiveTimeOut 0x0040 /* Receive Time Out interrupt mask */ +#define UART_IT_Transmit 0x0020 /* Transmit interrupt mask */ +#define UART_IT_Receive 0x0010 /* Receive interrupt mask */ +#define UART_IT_DSR 0x0008 /* DSR interrupt mask */ +#define UART_IT_DCD 0x0004 /* DCD interrupt mask */ +#define UART_IT_CTS 0x0002 /* CTS interrupt mask */ +#define UART_IT_RI 0x0001 /* RI interrupt mask */ + +/* UART DMA On Error */ +#define UART_DMAOnError_Enable 0xFFFB /* DMA receive request enabled + when the UART error interrupt + is asserted. */ +#define UART_DMAOnError_Disable 0x0004 /* DMA receive request disabled + when the UART error interrupt + is asserted. */ +/* UART DMA Request */ +#define UART_DMAReq_Tx 0x02 /* Transmit DMA Enable */ +#define UART_DMAReq_Rx 0x01 /* Receive DMA Enable */ + +/* UART FLAG */ +#define UART_FLAG_OverrunError 0x23 /* Overrun error flag */ +#define UART_FLAG_Break 0x22 /* break error flag */ +#define UART_FLAG_ParityError 0x21 /* parity error flag */ +#define UART_FLAG_FrameError 0x20 /* frame error flag */ +#define UART_FLAG_RI 0x48 /* RI flag */ +#define UART_FLAG_TxFIFOEmpty 0x47 /* Transmit FIFO Empty flag */ +#define UART_FLAG_RxFIFOFull 0x46 /* Receive FIFO Full flag */ +#define UART_FLAG_TxFIFOFull 0x45 /* Transmit FIFO Full flag */ +#define UART_FLAG_RxFIFOEmpty 0x44 /* Receive FIFO Empty flag */ +#define UART_FLAG_Busy 0x43 /* UART Busy flag */ +#define UART_FLAG_DCD 0x42 /* DCD flag */ +#define UART_FLAG_DSR 0x41 /* DSR flag */ +#define UART_FLAG_CTS 0x40 /* CTS flag */ +#define UART_RawIT_OverrunError 0x6A /* Overrun Error Raw IT flag */ +#define UART_RawIT_BreakError 0x69 /* Break Error Raw IT flag */ +#define UART_RawIT_ParityError 0x68 /* Parity Error Raw IT flag */ +#define UART_RawIT_FrameError 0x67 /* Frame Error Raw IT flag */ +#define UART_RawIT_ReceiveTimeOut 0x66 /* ReceiveTimeOut Raw IT flag */ +#define UART_RawIT_Transmit 0x65 /* Transmit Raw IT flag */ +#define UART_RawIT_Receive 0x64 /* Receive Raw IT flag */ +#define UART_RawIT_DSR 0x63 /* DSR Raw IT flag */ +#define UART_RawIT_DCD 0x62 /* DCD Raw IT flag */ +#define UART_RawIT_CTS 0x61 /* CTS Raw IT flag */ +#define UART_RawIT_RI 0x60 /* RI Raw IT flag */ + +/*IrDAx select*/ +#define IrDA0 0x01 /*IrDA0 select*/ +#define IrDA1 0x02 /*IrDA0 select*/ +#define IrDA2 0x03 /*IrDA0 select*/ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void UART_DeInit(UART_TypeDef* UARTx); +void UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef* UART_InitStruct); +void UART_StructInit(UART_InitTypeDef* UART_InitStruct); +void UART_Cmd(UART_TypeDef* UARTx, FunctionalState NewState); +void UART_ITConfig(UART_TypeDef* UARTx, u16 UART_IT, FunctionalState NewState); +void UART_DMAConfig(UART_TypeDef* UARTx, u16 UART_DMAOnError); +void UART_DMACmd(UART_TypeDef* UARTx, u8 UART_DMAReq, FunctionalState NewState); +void UART_LoopBackConfig(UART_TypeDef* UARTx, FunctionalState NewState); +FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, u16 UART_FLAG); +void UART_ClearFlag(UART_TypeDef* UARTx); +void UART_ClearITPendingBit(UART_TypeDef* UARTx, u16 UART_IT); +void UART_IrDALowPowerConfig(u8 IrDAx, FunctionalState NewState); +void UART_IrDACmd(u8 IrDAx, FunctionalState NewState); +void UART_IrDASetCounter(u8 IrDAx, u32 IrDA_Counter); +void UART_SendData(UART_TypeDef* UARTx, u8 Data); +u8 UART_ReceiveData(UART_TypeDef* UARTx); +void UART_SendBreak(UART_TypeDef* UARTx); +void UART_DTRConfig(UART_LevelTypeDef LevelState); +void UART_RTSConfig(UART_LevelTypeDef LevelState); +ITStatus UART_GetITStatus(UART_TypeDef* UARTx, u16 UART_IT); + +#endif /* __91x_UART_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM9_STR91X_IAR/Library/include/91x_vic.h b/20080212/Demo/ARM9_STR91X_IAR/Library/include/91x_vic.h new file mode 100644 index 000000000..127716a38 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/Library/include/91x_vic.h @@ -0,0 +1,94 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_vic.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* VIC software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + + +/* Define to prevent recursive inclusion ------------------------------------ */ +#ifndef __91x_VIC_H +#define __91x_VIC_H + +/* Includes ------------------------------------------------------------------*/ +#include "91x_map.h" +#include "91x_it.h" + +/* Exported types ------------------------------------------------------------*/ +/* Type of interrupt */ +typedef enum +{ + VIC_IRQ, + VIC_FIQ +} VIC_ITLineMode; + +/* Exported constants --------------------------------------------------------*/ + +/* VIC sources*/ + +#define WDG_ITLine 0 +#define SW_ITLine 1 +#define ARMRX_ITLine 2 +#define ARMTX_ITLine 3 +#define TIM0_ITLine 4 +#define TIM1_ITLine 5 +#define TIM2_ITLine 6 +#define TIM3_ITLine 7 +#define USBHP_ITLine 8 +#define USBLP_ITLine 9 +#define SCU_ITLine 10 +#define ENET_ITLine 11 +#define DMA_ITLine 12 +#define CAN_ITLine 13 +#define MC_ITLine 14 +#define ADC_ITLine 15 +#define UART0_ITLine 16 +#define UART1_ITLine 17 +#define UART2_ITLine 18 +#define I2C0_ITLine 19 +#define I2C1_ITLine 20 +#define SSP0_ITLine 21 +#define SSP1_ITLine 22 +#define LVD_ITLine 23 +#define RTC_ITLine 24 +#define WIU_ITLine 25 +#define EXTIT0_ITLine 26 +#define EXTIT1_ITLine 27 +#define EXTIT2_ITLine 28 +#define EXTIT3_ITLine 29 +#define USBWU_ITLine 30 +#define PFQBC_ITLine 31 + + +/* Module private variables --------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void VIC_DeInit(void); +FlagStatus VIC_GetIRQStatus(u16 VIC_Source); +FlagStatus VIC_GetFIQStatus(u16 VIC_Source); +FlagStatus VIC_GetSourceITStatus(u16 VIC_Source); +void VIC_ITCmd(u16 VIC_Source, FunctionalState VIC_NewState); +void VIC_SWITCmd(u16 VIC_Source, FunctionalState VIC_NewState); +void VIC_ProtectionCmd(FunctionalState VIC_NewState); +u32 VIC_GetCurrentISRAdd(VIC_TypeDef* VICx); +u32 VIC_GetISRVectAdd(u16 VIC_Source); +void VIC_Config(u16 VIC_Source, VIC_ITLineMode VIC_LineMode, u8 VIC_Priority); + +#endif /* __91x_VIC_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ + diff --git a/20080212/Demo/ARM9_STR91X_IAR/Library/include/91x_wdg.h b/20080212/Demo/ARM9_STR91X_IAR/Library/include/91x_wdg.h new file mode 100644 index 000000000..fc70547ad --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/Library/include/91x_wdg.h @@ -0,0 +1,82 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_wdg.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* WDG software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __91x_WDG_H +#define __91x_WDG_H + +/* Includes ------------------------------------------------------------------*/ +#include "91x_map.h" + +/* Exported types ------------------------------------------------------------*/ +typedef struct +{ +u16 WDG_Mode; +u16 WDG_ClockSource; +u16 WDG_Prescaler; +u16 WDG_Preload; + +} WDG_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/* WDG_Mode */ +#define WDG_Mode_Wdg 0x0001 /*WDG configured to run in watchdog mode.*/ +#define WDG_Mode_Timer 0xFFFE /*WDG configured to be in Free-running Timer mode.*/ + + +/* WDG_ClockSource */ +#define WDG_ClockSource_Rtc 0x0004 /* External clock ( 32 khz RTC clock ) will be used as counting clock.*/ +#define WDG_ClockSource_Apb 0xFFFB /*The APB clock signal will be used as counting clock.*/ + +/* WDG_Prescaler */ +/*This member must be a number between 0x00 and 0xFF. +Specifies the Prescaler value to divide the clock source. +The clock of the Watchdog Timer Counter is divided by " WDG_Prescaler + 1".*/ + + + +/* WDG_Preload */ +/*This member must be a number between 0x0000 and 0xFFFF. +This value is loaded in the WDG Counter when it starts counting.*/ + + +/* WDG Sequence */ +#define WDG_KeyValue1 0xA55A +#define WDG_KeyValue2 0x5AA5 + +/* Exported macro ------------------------------------------------------------*/ + + +/* Exported functions ------------------------------------------------------- */ + +void WDG_DeInit(void); +void WDG_Init(WDG_InitTypeDef* WDG_InitStruct); +void WDG_StructInit(WDG_InitTypeDef* WDG_InitStruct); +void WDG_Cmd(FunctionalState NewState); +void WDG_ITConfig(FunctionalState NewState); +u16 WDG_GetCounter(void); +FlagStatus WDG_GetFlagStatus(void); +void WDG_ClearFlag(void); +ITStatus WDG_GetITStatus(void); +void WDG_ClearITPendingBit(void); + +#endif /* __WDG_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_can.c b/20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_can.c new file mode 100644 index 000000000..e560d03c5 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_can.c @@ -0,0 +1,768 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_can.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the CAN software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_can.h" +#include "91x_scu.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/*----------------------------------------------------------------------------*/ +/* Macro Name : xxx_ID_MSK, xxx_ID_ARB */ +/* Description : Form the Mask and Arbitration registers value to filter */ +/* a range of identifiers or a fixed identifier, for standard*/ +/* and extended IDs */ +/*----------------------------------------------------------------------------*/ +#define RANGE_ID_MSK(range_start, range_end) (~((range_end) - (range_start))) +#define RANGE_ID_ARB(range_start, range_end) ((range_start) & (range_end)) + +#define FIXED_ID_MSK(id) RANGE_ID_MSK((id), (id)) +#define FIXED_ID_ARB(id) RANGE_ID_ARB((id), (id)) + +#define STD_RANGE_ID_MSK(range_start, range_end) ((u16)((RANGE_ID_MSK((range_start), (range_end)) & 0x7FF) << 2)) +#define STD_RANGE_ID_ARB(range_start, range_end) ((u16)(RANGE_ID_ARB((range_start), (range_end)) << 2)) + +#define STD_FIXED_ID_MSK(id) ((u16)((FIXED_ID_MSK(id) & 0x7FF) << 2)) +#define STD_FIXED_ID_ARB(id) ((u16)(FIXED_ID_ARB(id) << 2)) + +#define EXT_RANGE_ID_MSK_L(range_start, range_end) ((u16)(RANGE_ID_MSK((range_start), (range_end)) >> 11)) +#define EXT_RANGE_ID_MSK_H(range_start, range_end) ((u16)(STD_RANGE_ID_MSK((range_start), (range_end)) | ((RANGE_ID_MSK((range_start), (range_end)) >> 27) & 0x03))) +#define EXT_RANGE_ID_ARB_L(range_start, range_end) ((u16)(RANGE_ID_ARB((range_start), (range_end)) >> 11)) +#define EXT_RANGE_ID_ARB_H(range_start, range_end) ((u16)(STD_RANGE_ID_ARB((range_start), (range_end)) | ((RANGE_ID_ARB((range_start), (range_end)) >> 27) & 0x03))) + +#define EXT_FIXED_ID_MSK_L(id) ((u16)(FIXED_ID_MSK(id) >> 11)) +#define EXT_FIXED_ID_MSK_H(id) ((u16)(STD_FIXED_ID_MSK(id) | ((FIXED_ID_MSK(id) >> 27) & 0x03))) +#define EXT_FIXED_ID_ARB_L(id) ((u16)(FIXED_ID_ARB(id) >> 11)) +#define EXT_FIXED_ID_ARB_H(id) ((u16)(STD_FIXED_ID_ARB(id) | ((FIXED_ID_ARB(id) >> 27) & 0x03))) + +/* macro to format the timing register value from the timing parameters*/ +#define CAN_TIMING(tseg1, tseg2, sjw, brp) ((((tseg2-1) & 0x07) << 12) | (((tseg1-1) & 0x0F) << 8) | (((sjw-1) & 0x03) << 6) | ((brp-1) & 0x3F)) + +/* Private variables ---------------------------------------------------------*/ +/* array of pre-defined timing parameters for standard bitrates*/ +u16 CanTimings[] = { /* value bitrate NTQ TSEG1 TSEG2 SJW BRP */ + CAN_TIMING(11, 4, 4, 5), /* 0x3AC4 100 kbit/s 16 11 4 4 5 */ + CAN_TIMING(11, 4, 4, 4), /* 0x3AC3 125 kbit/s 16 11 4 4 4 */ + CAN_TIMING( 4, 3, 3, 4), /* 0x2383 250 kbit/s 8 4 3 3 4 */ + CAN_TIMING(13, 2, 1, 1), /* 0x1C00 500 kbit/s 16 13 2 1 1 */ + CAN_TIMING( 4, 3, 1, 1), /* 0x2300 1 Mbit/s 8 4 3 1 1 */ +}; + +/* Private function prototypes -----------------------------------------------*/ +static u32 GetFreeIF(void); +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : CAN_DeInit +* Description : Deinitializes the CAN peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void CAN_DeInit (void) +{ + /* Reset the CAN registers values*/ + + SCU_APBPeriphReset(__CAN,ENABLE); /*CAN peripheral is under Reset */ + SCU_APBPeriphReset(__CAN,DISABLE); /*CAN peripheral Reset off*/ + + +} + +/******************************************************************************* +* Function Name : CAN_Init +* Description : Initializes the CAN peripheral according to the specified +* parameters in the CAN_InitStruct. +* Input : CAN_InitStruct: pointer to a CAN_InitTypeDef structure that +* contains the configuration information for the CAN peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void CAN_Init(CAN_InitTypeDef* CAN_InitStruct) +{ + CAN_EnterInitMode(CAN_CR_CCE | CAN_InitStruct->CAN_ConfigParameters); + CAN_SetBitrate(CAN_InitStruct->CAN_Bitrate); + CAN_LeaveInitMode(); + CAN_LeaveTestMode(); +} + +/******************************************************************************* +* Function Name : CAN_StructInit +* Description : Fills each CAN_InitStruct member with its reset value. +* Input : CAN_InitStruct : pointer to a CAN_InitTypeDef structure which +* will be initialized. +* Output : None +* Return : None. +*******************************************************************************/ +void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct) +{ +/* Reset CAN init structure parameters values */ + CAN_InitStruct->CAN_ConfigParameters = 0x0; + CAN_InitStruct->CAN_Bitrate = 0x2301; +} + +/******************************************************************************* +* Function Name : CAN_SetBitrate +* Description : Setups a standard CAN bitrate. +* Input : bitrate: specifies the bit rate. +* Output : None +* Return : None +*******************************************************************************/ +void CAN_SetBitrate(u32 bitrate) +{ + CAN->BTR = CanTimings[bitrate]; /* write the predefined timing value */ + CAN->BRPR = 0; /* clear the Extended Baud Rate Prescaler */ +} + +/******************************************************************************* +* Function Name : CAN_SetTiming +* Description : Setups the CAN timing with specific parameters +* Input : - tseg1: specifies Time Segment before the sample point. +* This parameter must be a number between 1 and 16. +* - tseg2: Time Segment after the sample point. This parameter +* must be a number between 1 and 8. +* - sjw: Synchronisation Jump Width. This parameter must be +* a number between 1 and 4. +* - brp: Baud Rate Prescaler. This parameter must be a number +* between 1 and 1024. +* Output : None +* Return : None +*******************************************************************************/ +void CAN_SetTiming(u32 tseg1, u32 tseg2, u32 sjw, u32 brp) +{ + CAN->BTR = CAN_TIMING(tseg1, tseg2, sjw, brp); + CAN->BRPR = ((brp-1) >> 6) & 0x0F; +} + +/******************************************************************************* +* Function Name : GetFreeIF +* Description : Searchs the first free message interface, starting from 0. +* Input : None +* Output : None +* Return : A free message interface number (0 or 1) if found, else 2 +*******************************************************************************/ +static u32 GetFreeIF(void) +{ + if ((CAN->sMsgObj[0].CRR & CAN_CRR_BUSY) == 0) + return 0; + else if ((CAN->sMsgObj[1].CRR & CAN_CRR_BUSY) == 0) + return 1; + else + return 2; +} + +/******************************************************************************* +* Function Name : CAN_SetUnusedMsgObj +* Description : Configures the message object as unused +* Input : msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Interface to treat the message +* - ERROR: No interface to treat the message +*******************************************************************************/ +ErrorStatus CAN_SetUnusedMsgObj(u32 msgobj) +{ + u32 msg_if=0; + + if ((msg_if = GetFreeIF()) == 2) + { + return ERROR; + } + + CAN->sMsgObj[msg_if].CMR = CAN_CMR_WRRD + | CAN_CMR_MASK + | CAN_CMR_ARB + | CAN_CMR_CONTROL + | CAN_CMR_DATAA + | CAN_CMR_DATAB; + + CAN->sMsgObj[msg_if].M1R = 0; + CAN->sMsgObj[msg_if].M2R = 0; + + CAN->sMsgObj[msg_if].A1R = 0; + CAN->sMsgObj[msg_if].A2R = 0; + + CAN->sMsgObj[msg_if].MCR = 0; + + CAN->sMsgObj[msg_if].DA1R = 0; + CAN->sMsgObj[msg_if].DA2R = 0; + CAN->sMsgObj[msg_if].DB1R = 0; + CAN->sMsgObj[msg_if].DB2R = 0; + + CAN->sMsgObj[msg_if].CRR = 1 + msgobj; + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_SetTxMsgObj +* Description : Configures the message object as TX. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* - idType: specifies the identifier type of the frames that +* will be transmitted using this message object. +* This parameter can be one of the following values: +* - CAN_STD_ID (standard ID, 11-bit) +* - CAN_EXT_ID (extended ID, 29-bit) +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Interface to treat the message +* - ERROR: No interface to treat the message +*******************************************************************************/ +ErrorStatus CAN_SetTxMsgObj(u32 msgobj, u32 idType) +{ + u32 msg_if=0; + + if ((msg_if = GetFreeIF()) == 2) + { + return ERROR; + } + + CAN->sMsgObj[msg_if].CMR = CAN_CMR_WRRD + | CAN_CMR_MASK + | CAN_CMR_ARB + | CAN_CMR_CONTROL + | CAN_CMR_DATAA + | CAN_CMR_DATAB; + + CAN->sMsgObj[msg_if].M1R = 0; + CAN->sMsgObj[msg_if].A1R = 0; + + if (idType == CAN_STD_ID) + { + CAN->sMsgObj[msg_if].M2R = CAN_M2R_MDIR; + CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | CAN_A2R_DIR; + } + else + { + CAN->sMsgObj[msg_if].M2R = CAN_M2R_MDIR | CAN_M2R_MXTD; + CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | CAN_A2R_DIR | CAN_A2R_XTD; + } + + CAN->sMsgObj[msg_if].MCR = CAN_MCR_TXIE | CAN_MCR_EOB; + + CAN->sMsgObj[msg_if].DA1R = 0; + CAN->sMsgObj[msg_if].DA2R = 0; + CAN->sMsgObj[msg_if].DB1R = 0; + CAN->sMsgObj[msg_if].DB2R = 0; + + CAN->sMsgObj[msg_if].CRR = 1 + msgobj; + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_SetRxMsgObj +* Description : Configures the message object as RX. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* - idType: specifies the identifier type of the frames that +* will be transmitted using this message object. +* This parameter can be one of the following values: +* - CAN_STD_ID (standard ID, 11-bit) +* - CAN_EXT_ID (extended ID, 29-bit) +* - idLow: specifies the low part of the identifier range used +* for acceptance filtering. +* - idHigh: specifies the high part of the identifier range +* used for acceptance filtering. +* - singleOrFifoLast: specifies the end-of-buffer indicator. +* This parameter can be one of the following values: +* - TRUE: for a single receive object or a FIFO receive +* object that is the last one of the FIFO. +* - FALSE: for a FIFO receive object that is not the +* last one. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Interface to treat the message +* - ERROR: No interface to treat the message +*******************************************************************************/ +ErrorStatus CAN_SetRxMsgObj(u32 msgobj, u32 idType, u32 idLow, u32 idHigh, bool singleOrFifoLast) +{ + u32 msg_if=0; + + if ((msg_if = GetFreeIF()) == 2) + { + return ERROR; + } + + CAN->sMsgObj[msg_if].CMR = CAN_CMR_WRRD + | CAN_CMR_MASK + | CAN_CMR_ARB + | CAN_CMR_CONTROL + | CAN_CMR_DATAA + | CAN_CMR_DATAB; + + if (idType == CAN_STD_ID) + { + CAN->sMsgObj[msg_if].M1R = 0; + CAN->sMsgObj[msg_if].M2R = STD_RANGE_ID_MSK(idLow, idHigh); + + CAN->sMsgObj[msg_if].A1R = 0; + CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | STD_RANGE_ID_ARB(idLow, idHigh); + } + else + { + CAN->sMsgObj[msg_if].M1R = EXT_RANGE_ID_MSK_L(idLow, idHigh); + CAN->sMsgObj[msg_if].M2R = CAN_M2R_MXTD | EXT_RANGE_ID_MSK_H(idLow, idHigh); + + CAN->sMsgObj[msg_if].A1R = EXT_RANGE_ID_ARB_L(idLow, idHigh); + CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | CAN_A2R_XTD | EXT_RANGE_ID_ARB_H(idLow, idHigh); + } + + CAN->sMsgObj[msg_if].MCR = CAN_MCR_RXIE | CAN_MCR_UMASK | (singleOrFifoLast ? CAN_MCR_EOB : 0); + + CAN->sMsgObj[msg_if].DA1R = 0; + CAN->sMsgObj[msg_if].DA2R = 0; + CAN->sMsgObj[msg_if].DB1R = 0; + CAN->sMsgObj[msg_if].DB2R = 0; + + CAN->sMsgObj[msg_if].CRR = 1 + msgobj; + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_InvalidateAllMsgObj +* Description : Configures all the message objects as unused. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void CAN_InvalidateAllMsgObj(void) +{ + u32 i=0; + for (i = 0; i < 32; i++) + CAN_SetUnusedMsgObj(i); +} + + +/******************************************************************************* +* Function Name : CAN_ReleaseMessage +* Description : Releases the message object +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Interface to treat the message +* - ERROR: No interface to treat the message +*******************************************************************************/ +ErrorStatus CAN_ReleaseMessage(u32 msgobj) +{ + u32 msg_if=0; + + if ((msg_if = GetFreeIF()) == 2) + { + return ERROR; + } + + CAN->sMsgObj[msg_if].CMR = CAN_CMR_CLRINTPND | CAN_CMR_TXRQSTNEWDAT; + CAN->sMsgObj[msg_if].CRR = 1 + msgobj; + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_SendMessage +* Description : Start transmission of a message +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* : - pCanMsg: pointer to the message structure containing data +* to transmit. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Transmission OK +* - ERROR: No transmission +*******************************************************************************/ +ErrorStatus CAN_SendMessage(u32 msgobj, canmsg* pCanMsg) +{ + if (CAN->sMsgObj[0].CRR & CAN_CRR_BUSY) + { + return ERROR; + } + + CAN->SR &= ~CAN_SR_TXOK; + + /* read the Arbitration and Message Control*/ + CAN->sMsgObj[0].CMR = CAN_CMR_ARB | CAN_CMR_CONTROL; + + CAN->sMsgObj[0].CRR = 1 + msgobj; + + if (CAN->sMsgObj[0].CRR & CAN_CRR_BUSY) + { + return ERROR; + } + + /* update the contents needed for transmission*/ + CAN->sMsgObj[0].CMR = CAN_CMR_WRRD + | CAN_CMR_ARB + | CAN_CMR_CONTROL + | CAN_CMR_DATAA + | CAN_CMR_DATAB; + + if ((CAN->sMsgObj[0].A2R & CAN_A2R_XTD) == 0) + { + /* standard ID*/ + CAN->sMsgObj[0].A1R = 0; + CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | STD_FIXED_ID_ARB(pCanMsg->Id); + } + else + { + /* extended ID*/ + CAN->sMsgObj[0].A1R = EXT_FIXED_ID_ARB_L(pCanMsg->Id); + CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | EXT_FIXED_ID_ARB_H(pCanMsg->Id); + } + + CAN->sMsgObj[0].MCR = (CAN->sMsgObj[0].MCR & 0xFEF0) | CAN_MCR_NEWDAT | CAN_MCR_TXRQST | pCanMsg->Dlc; + + CAN->sMsgObj[0].DA1R = ((u16)pCanMsg->Data[1]<<8) | pCanMsg->Data[0]; + CAN->sMsgObj[0].DA2R = ((u16)pCanMsg->Data[3]<<8) | pCanMsg->Data[2]; + CAN->sMsgObj[0].DB1R = ((u16)pCanMsg->Data[5]<<8) | pCanMsg->Data[4]; + CAN->sMsgObj[0].DB2R = ((u16)pCanMsg->Data[7]<<8) | pCanMsg->Data[6]; + + CAN->sMsgObj[0].CRR = 1 + msgobj; + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_ReceiveMessage +* Description : Gets the message, if received. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* - release: specifies the message release indicator. +* This parameter can be one of the following values: +* - TRUE: the message object is released when getting +* the data. +* - FALSE: the message object is not released. +* - pCanMsg: pointer to the message structure where received +* data is copied. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Reception OK +* - ERROR: No message pending +*******************************************************************************/ +ErrorStatus CAN_ReceiveMessage(u32 msgobj, bool release, canmsg* pCanMsg) +{ + if (!CAN_IsMessageWaiting(msgobj)) + { + return ERROR; + } + + CAN->SR &= ~CAN_SR_RXOK; + + /* read the message contents*/ + CAN->sMsgObj[1].CMR = CAN_CMR_MASK + | CAN_CMR_ARB + | CAN_CMR_CONTROL + | CAN_CMR_CLRINTPND + | (release ? CAN_CMR_TXRQSTNEWDAT : 0) + | CAN_CMR_DATAA + | CAN_CMR_DATAB; + + CAN->sMsgObj[1].CRR = 1 + msgobj; + + if (CAN->sMsgObj[1].CRR & CAN_CRR_BUSY) + { + return ERROR; + } + + if ((CAN->sMsgObj[1].A2R & CAN_A2R_XTD) == 0) + { + /* standard ID*/ + pCanMsg->IdType = CAN_STD_ID; + pCanMsg->Id = (CAN->sMsgObj[1].A2R >> 2) & 0x07FF; + } + else + { + /* extended ID*/ + pCanMsg->IdType = CAN_EXT_ID; + pCanMsg->Id = ((CAN->sMsgObj[1].A2R >> 2) & 0x07FF); + pCanMsg->Id |= ((u32)CAN->sMsgObj[1].A1R << 11); + pCanMsg->Id |= (((u32)CAN->sMsgObj[1].A2R & 0x0003) << 27); + } + + pCanMsg->Dlc = CAN->sMsgObj[1].MCR & 0x0F; + + pCanMsg->Data[0] = (u8) CAN->sMsgObj[1].DA1R; + pCanMsg->Data[1] = (u8)(CAN->sMsgObj[1].DA1R >> 8); + pCanMsg->Data[2] = (u8) CAN->sMsgObj[1].DA2R; + pCanMsg->Data[3] = (u8)(CAN->sMsgObj[1].DA2R >> 8); + pCanMsg->Data[4] = (u8) CAN->sMsgObj[1].DB1R; + pCanMsg->Data[5] = (u8)(CAN->sMsgObj[1].DB1R >> 8); + pCanMsg->Data[6] = (u8) CAN->sMsgObj[1].DB2R; + pCanMsg->Data[7] = (u8)(CAN->sMsgObj[1].DB2R >> 8); + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_WaitEndOfTx +* Description : Waits until current transmission is finished. +* Input : None +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Transmission ended +* - ERROR: Transmission did not occur yet +*******************************************************************************/ +ErrorStatus CAN_WaitEndOfTx(void) +{ + if ((CAN->SR & CAN_SR_TXOK) == 0) + { + return ERROR; + } + CAN->SR &= ~CAN_SR_TXOK; + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_BasicSendMessage +* Description : Starts transmission of a message in BASIC mode. This mode +* does not use the message RAM. +* Input : pCanMsg: Pointer to the message structure containing data to +* transmit. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Transmission OK +* - ERROR: No transmission +*******************************************************************************/ +ErrorStatus CAN_BasicSendMessage(canmsg* pCanMsg) +{ + /* clear NewDat bit in IF2 to detect next reception*/ + CAN->sMsgObj[1].MCR &= ~CAN_MCR_NEWDAT; + + CAN->SR &= ~CAN_SR_TXOK; + CAN->sMsgObj[0].CMR = CAN_CMR_WRRD + | CAN_CMR_ARB + | CAN_CMR_CONTROL + | CAN_CMR_DATAA + | CAN_CMR_DATAB; + + if (pCanMsg->IdType == CAN_STD_ID) + { + /* standard ID*/ + CAN->sMsgObj[0].A1R = 0; + CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | STD_FIXED_ID_ARB(pCanMsg->Id); + } + else + { + /* extended ID*/ + CAN->sMsgObj[0].A1R = EXT_FIXED_ID_ARB_L(pCanMsg->Id); + CAN->sMsgObj[0].A2R = ((CAN->sMsgObj[0].A2R) & 0xE000) | EXT_FIXED_ID_ARB_H(pCanMsg->Id); + } + + CAN->sMsgObj[0].MCR = (CAN->sMsgObj[0].MCR & 0xFCF0) | pCanMsg->Dlc; + + CAN->sMsgObj[0].DA1R = ((u16)pCanMsg->Data[1]<<8) | pCanMsg->Data[0]; + CAN->sMsgObj[0].DA2R = ((u16)pCanMsg->Data[3]<<8) | pCanMsg->Data[2]; + CAN->sMsgObj[0].DB1R = ((u16)pCanMsg->Data[5]<<8) | pCanMsg->Data[4]; + CAN->sMsgObj[0].DB2R = ((u16)pCanMsg->Data[7]<<8) | pCanMsg->Data[6]; + + /* request transmission*/ + if (CAN->sMsgObj[0].CRR == CAN_CRR_BUSY ) + { + return ERROR; + } + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_BasicReceiveMessage +* Description : Gets the message in BASIC mode, if received. This mode does +* not use the message RAM. +* Input : pCanMsg: pointer to the message structure where message is copied. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Reception OK +* - ERROR: No message pending +*******************************************************************************/ +ErrorStatus CAN_BasicReceiveMessage(canmsg* pCanMsg) +{ + if ((CAN->sMsgObj[1].MCR & CAN_MCR_NEWDAT) == 0) + { + return ERROR; + } + + CAN->SR &= ~CAN_SR_RXOK; + + CAN->sMsgObj[1].CMR = CAN_CMR_ARB + | CAN_CMR_CONTROL + | CAN_CMR_DATAA + | CAN_CMR_DATAB; + + if ((CAN->sMsgObj[1].A2R & CAN_A2R_XTD) == 0) + { + /* standard ID*/ + pCanMsg->IdType = CAN_STD_ID; + pCanMsg->Id = (CAN->sMsgObj[1].A2R >> 2) & 0x07FF; + } + else + { + /* extended ID*/ + pCanMsg->IdType = CAN_EXT_ID; + pCanMsg->Id = ((CAN->sMsgObj[1].A2R >> 2) & 0x07FF); + pCanMsg->Id |= ((u32)CAN->sMsgObj[1].A1R << 11); + pCanMsg->Id |= (((u32)CAN->sMsgObj[1].A2R & 0x0003) << 27); + } + + pCanMsg->Dlc = CAN->sMsgObj[1].MCR & 0x0F; + + pCanMsg->Data[0] = (u8) CAN->sMsgObj[1].DA1R; + pCanMsg->Data[1] = (u8)(CAN->sMsgObj[1].DA1R >> 8); + pCanMsg->Data[2] = (u8) CAN->sMsgObj[1].DA2R; + pCanMsg->Data[3] = (u8)(CAN->sMsgObj[1].DA2R >> 8); + pCanMsg->Data[4] = (u8) CAN->sMsgObj[1].DB1R; + pCanMsg->Data[5] = (u8)(CAN->sMsgObj[1].DB1R >> 8); + pCanMsg->Data[6] = (u8) CAN->sMsgObj[1].DB2R; + pCanMsg->Data[7] = (u8)(CAN->sMsgObj[1].DB2R >> 8); + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_EnterInitMode +* Description : Switchs the CAN into initialization mode. This function must +* be used in conjunction with CAN_LeaveInitMode(). +* Input : InitMask: specifies the CAN configuration in normal mode. +* Output : None +* Return : None +*******************************************************************************/ +void CAN_EnterInitMode(u8 InitMask) +{ + CAN->CR = InitMask | CAN_CR_INIT; + CAN->SR = 0; /* reset the status*/ +} + +/******************************************************************************* +* Function Name : CAN_LeaveInitMode +* Description : Leaves the initialization mode (switch into normal mode). +* This function must be used in conjunction with CAN_EnterInitMode(). +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void CAN_LeaveInitMode(void) +{ + CAN->CR &= ~(CAN_CR_INIT | CAN_CR_CCE); +} + +/******************************************************************************* +* Function Name : CAN_EnterTestMode +* Description : Switchs the CAN into test mode. This function must be used in +* conjunction with CAN_LeaveTestMode(). +* Input : TestMask: specifies the configuration in test modes. +* Output : None +* Return : None +*******************************************************************************/ +void CAN_EnterTestMode(u8 TestMask) +{ + CAN->CR |= CAN_CR_TEST; + CAN->TESTR |= TestMask; +} + +/******************************************************************************* +* Function Name : CAN_LeaveTestMode +* Description : Leaves the current test mode (switch into normal mode). +* This function must be used in conjunction with CAN_EnterTestMode(). +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void CAN_LeaveTestMode(void) +{ + CAN->CR |= CAN_CR_TEST; + CAN->TESTR &= ~(CAN_TESTR_LBACK | CAN_TESTR_SILENT | CAN_TESTR_BASIC); + CAN->CR &= ~CAN_CR_TEST; +} + +/******************************************************************************* +* Function Name : CAN_ReleaseTxMessage +* Description : Releases the transmit message object. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : None +*******************************************************************************/ +void CAN_ReleaseTxMessage(u32 msgobj) +{ + CAN->sMsgObj[0].CMR = CAN_CMR_CLRINTPND | CAN_CMR_TXRQSTNEWDAT; + CAN->sMsgObj[0].CRR = 1 + msgobj; +} + +/******************************************************************************* +* Function Name : CAN_ReleaseRxMessage +* Description : Releases the receive message object. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : None +*******************************************************************************/ +void CAN_ReleaseRxMessage(u32 msgobj) +{ + CAN->sMsgObj[1].CMR = CAN_CMR_CLRINTPND | CAN_CMR_TXRQSTNEWDAT; + CAN->sMsgObj[1].CRR = 1 + msgobj; +} + +/******************************************************************************* +* Function Name : CAN_IsMessageWaiting +* Description : Tests the waiting status of a received message. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : A non-zero value if the corresponding message object has +* received a message waiting to be copied, else 0. +*******************************************************************************/ +u32 CAN_IsMessageWaiting(u32 msgobj) +{ + return (msgobj < 16 ? CAN->ND1R & (1 << msgobj) : CAN->ND2R & (1 << (msgobj-16))); +} + +/******************************************************************************* +* Function Name : CAN_IsTransmitRequested +* Description : Tests the request status of a transmitted message. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : A non-zero value if the corresponding message is requested +* to transmit, else 0. +*******************************************************************************/ +u32 CAN_IsTransmitRequested(u32 msgobj) +{ + return (msgobj < 16 ? CAN->TXR1R & (1 << msgobj) : CAN->TXR2R & (1 << (msgobj-16))); +} + +/******************************************************************************* +* Function Name : CAN_IsInterruptPending +* Description : Tests the interrupt status of a message object. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : A non-zero value if the corresponding message has an +* interrupt pending, else 0. +*******************************************************************************/ +u32 CAN_IsInterruptPending(u32 msgobj) +{ + return (msgobj < 16 ? CAN->IP1R & (1 << msgobj) : CAN->IP2R & (1 << (msgobj-16))); +} + +/******************************************************************************* +* Function Name : CAN_IsObjectValid +* Description : Tests the validity of a message object (ready to use). +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : A non-zero value if the corresponding message object is +* valid, else 0. +*******************************************************************************/ +u32 CAN_IsObjectValid(u32 msgobj) +{ + return (msgobj < 16 ? CAN->MV1R & (1 << msgobj) : CAN->MV2R & (1 << (msgobj-16))); +} +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_enet.c b/20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_enet.c new file mode 100644 index 000000000..4a7a99661 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_enet.c @@ -0,0 +1,591 @@ +/******************** +* Original work (C) COPYRIGHT 2006 STMicroelectronics ************************** +* Modifications (C) CopyRight 2006 Richard barry +* File Name : 91x_enet.c +* Author : MCD Application Team +* Date First Issued : May 2006 +* Description : ENET library functions +******************************************************************************** +* History: +* May 2006: v1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + + +/* Includes ------------------------------------------------------------------*/ +#include "FreeRTOS.h" +#include "task.h" +#include "91x_lib.h" +#include "string.h" //include when using memcpy function + +/* Include of other module interface headers ---------------------------------*/ +/* Local includes ------------------------------------------------------------*/ +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#ifndef NULL +#define NULL (0) +#endif +/* Function return values */ +#define ENET_OK (1) +#define ENET_NOK (0) + +/* PHY interface constants. */ +#define STE100P_STATUS_REG 0x01 +#define STE100P_CONTROL_REG 0x00 +#define STE100P_LINK_ABILITY 0x05 +#define STE100P_STATUS_LINKED 0x0004 +#define STE100P_AUTO_NEGOTIATE_ABILITY 0x1000 +#define STE100P_AUTO_NEGOTIATE_COMPLETE 0x20 +#define STE100P_10HALF 0x0020 +#define STE100P_10FULL 0x0040 +#define STE100P_100HALF 0x0080 +#define STE100P_100FULL 0x0100 +#define STE100P_CTRL_FULL 0x0100 + + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +#define ENET_NUM_RX_BUFFERS 8 + +static ENET_DMADSCRBase dmaTxDscrBase, dmaRxDscrBase[ ENET_NUM_RX_BUFFERS ]; +static u8 RxBuff[ ENET_NUM_RX_BUFFERS ][ENET_BUFFER_SIZE]; +u8 TxBuff[ENET_BUFFER_SIZE]; + +/* Private function prototypes -----------------------------------------------*/ +extern MEMCOPY_L2S_BY4(); + +/* Interface functions -------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : ENET_SetMACConfig(ENET_MACConfig * MAC_Config) +* Description : MAC Control Register Configuration +* Input : MAC_Config structure +* Output : None +* Return : None +*******************************************************************************/ +void ENET_MACControlConfig(ENET_MACConfig *MAC_Config) +{ + /* ReceiveALL bit */ + if (MAC_Config->ReceiveALL==ENABLE) ENET_MAC->MCR |= MAC_MCR_RA; + else ENET_MAC->MCR &=~MAC_MCR_RA; + + /* MIIPrescaler */ + ENET_MAC->MCR &=~(0x3<<24); + if ((MAC_Config->MIIPrescaler) == MIIPrescaler_2) + ENET_MAC->MCR |=0x1<<24; + + /* Loopback mode */ + if (MAC_Config->LoopbackMode==ENABLE) + { + ENET_MAC->MCR &=~MAC_MCR_LM; + ENET_MAC->MCR |=0x1<<21; + ENET_MAC->MCR &=~MAC_MCR_DRO; /*enable frame reception during transmission*/ + } + + /* Address filtering mode */ + ENET_MAC->MCR &=~MAC_MCR_AFM; + ENET_MAC->MCR |= MAC_Config->AddressFilteringMode; + + /* VLAN Filtering Mode */ + ENET_MAC->MCR |= (MAC_Config->VLANFilteringMode)<<15; + + /*Wrong Frame Pass */ + if (MAC_Config->PassWrongFrame == ENABLE) ENET_MAC->MCR |=MAC_MCR_PWF; + else ENET_MAC->MCR &=~MAC_MCR_PWF; + + /* Late Collision Retransmission*/ + if (MAC_Config->LateCollision == ENABLE) ENET_MAC->MCR |=MAC_MCR_ELC; + else ENET_MAC->MCR &=~MAC_MCR_ELC; + + /* Broadcast Frame Reception */ + if (MAC_Config->BroadcastFrameReception == ENABLE) ENET_MAC->MCR &=~MAC_MCR_DBF; + else ENET_MAC->MCR |=MAC_MCR_DBF; + + /* PacketRetry */ + if (MAC_Config->PacketRetry == ENABLE) ENET_MAC->MCR &=~MAC_MCR_DPR; + else ENET_MAC->MCR |=MAC_MCR_DPR; + + /* RxFrameFiltering */ + if (MAC_Config->RxFrameFiltering == ENABLE) ENET_MAC->MCR |=MAC_MCR_RVFF; + else ENET_MAC->MCR &=~MAC_MCR_RVFF; + + /* AutomaticPadRemoval */ + if (MAC_Config->AutomaticPadRemoval == ENABLE) ENET_MAC->MCR |=MAC_MCR_APR; + else ENET_MAC->MCR &=~MAC_MCR_APR; + + /* DefferalCheck */ + if (MAC_Config->DeferralCheck == ENABLE) ENET_MAC->MCR |=MAC_MCR_DCE; + else ENET_MAC->MCR &=~MAC_MCR_DCE; + +} + + + +/******************************************************************************* +* Function Name : ENET_SetOperatingMode +* Description : Sets the Operating mode +* Input : ENET_OperatingMode:(see ENET_OperatingMode in 91x_enet.h) +* Output : None +* Return : None +*******************************************************************************/ +portBASE_TYPE ENET_SetOperatingMode( void ) +{ +unsigned portLONG ulStatusReg, ulControlReg, ulLinkAbilityReg; + + /* Link status is latched, so read twice to get current value */ + ulStatusReg = ENET_MIIReadReg(0, STE100P_STATUS_REG); + ulStatusReg = ENET_MIIReadReg(0, STE100P_STATUS_REG); + + if( !( ulStatusReg & STE100P_STATUS_LINKED ) ) + { + /* No Link. */ + return pdFAIL; + } + + ulControlReg = ENET_MIIReadReg(0, STE100P_CONTROL_REG); + if (ulControlReg & STE100P_AUTO_NEGOTIATE_ABILITY) + { + /* AutoNegotiation is enabled. */ + if (!(ulStatusReg & STE100P_AUTO_NEGOTIATE_COMPLETE)) + { + /* Auto-negotiation in progress. */ + return pdFAIL; + } + + ulLinkAbilityReg = ENET_MIIReadReg(0, STE100P_LINK_ABILITY); + if( ( ulLinkAbilityReg & STE100P_100FULL ) || ( ulLinkAbilityReg & STE100P_10FULL ) ) + { + ENET_MAC->MCR |=MAC_MCR_FDM; /* full duplex mode */ + ENET_MAC->MCR &=~MAC_MCR_DRO; /* enable frame reception during transmission */ + } + else + { + ENET_MAC->MCR &=~MAC_MCR_FDM; /* half duplex mode */ + ENET_MAC->MCR |=MAC_MCR_DRO; /* disable frame reception during transmission */ + } + } + else + { + if( ulStatusReg & STE100P_CTRL_FULL ) + { + ENET_MAC->MCR |=MAC_MCR_FDM; /* full duplex mode */ + ENET_MAC->MCR &=~MAC_MCR_DRO; /* enable frame reception during transmission */ + } + else + { + ENET_MAC->MCR &=~MAC_MCR_FDM; /* half duplex mode */ + ENET_MAC->MCR |=MAC_MCR_DRO; /* disable frame reception during transmission */ + } + } + + return pdPASS; +} + +/******************************************************************************* +* Function Name : ENET_MIIWriteReg +* Description : Writes a value on the PHY registers +* Input : phyDev PHY device address + : phyReg PHY register to be written +* : phyVal PHY register value +* Output : None +* Return : None +*******************************************************************************/ +void ENET_MIIWriteReg (u8 phyDev, u8 phyReg, u32 phyVal) +{ + + volatile u32 addr; + volatile u32 res; /* temporary result for address register status */ + volatile u32 timeout; + + /* Prepare the MII register address */ + addr = 0; + addr |= ((phyDev<<11) & MAC_MII_ADDR_PHY_ADDR); /* set the PHY address */ + addr |= ((phyReg<<6) & MAC_MII_ADDR_MII_REG); /* select the corresponding register */ + addr |= MAC_MII_ADDR_MII_WRITE; /* in write mode */ + addr |= MAC_MII_ADDR_MII_BUSY; + + /* Check for the Busy flag */ + timeout=0; + do + { + timeout++; + res = ENET_MAC->MIIA; + } while ((res & MAC_MII_ADDR_MII_BUSY) && (timeout < (u32 )MII_WRITE_TO)); + + /* Give the value to the MII data register */ + ENET_MAC->MIID = (phyVal & 0xFFFF); + + /* write the result value into the MII Address register */ + ENET_MAC->MIIA =addr; + + /* Check for the Busy flag */ + timeout=0; + do + { + timeout++; + res = ENET_MAC->MIIA; + } while ((res & MAC_MII_ADDR_MII_BUSY) && (timeout < (u32 )MII_WRITE_TO)); + +} + +/******************************************************************************* +* Function Name : ENET_MIIReadReg +* Description : Writes a value on the PHY +* Input : phyDev PHY device address +* : phyReg PHY register to be read +* Output : None +* Return : The read value (16 bits) +*******************************************************************************/ +u32 ENET_MIIReadReg (u8 phyDev, u32 phyReg ) +{ + + u32 rValue; + u32 addr; + u32 res; /* temporary result for address register status */ + u32 timeout; /* timeout value for read process */ + + /* prepare the MII register address */ + addr = 0; + addr |= ((phyDev<<11) & MAC_MII_ADDR_PHY_ADDR); /* set the PHY address */ + addr |= ((phyReg<<6) & MAC_MII_ADDR_MII_REG); /* select the corresponding register */ + addr &= ~(MAC_MII_ADDR_MII_WRITE); /* ... in read mode */ + addr |= MAC_MII_ADDR_MII_BUSY; + + /* Check for the Busy flag */ + timeout = 0; + + do + { + timeout++; + res = ENET_MAC->MIIA; + } while ((res & MAC_MII_ADDR_MII_BUSY) && (timeout < (u32 )MII_READ_TO)); + + /* write the result value into the MII Address register */ + ENET_MAC->MIIA = addr; + + /* Check for the Busy flag */ + timeout = 0; + + do + { + timeout++; + res = ENET_MAC->MIIA; + } while ((res & MAC_MII_ADDR_MII_BUSY) && (timeout < (u32 )MII_READ_TO)); + + /* read the result value from data register*/ + rValue = ENET_MAC->MIID; + + return (rValue & 0x0000FFFF); +} + +/******************************************************************************* +* Function Name : ENET_RxDscrInit +* Description : Initializes the Rx ENET descriptor chain. Single Descriptor +* Input : None +* Output : None +* Return : None +*******************************************************************************/ + +void ENET_RxDscrInit(void) +{ +int i; + + for( i = 0; i < ENET_NUM_RX_BUFFERS; i++ ) + { + /* Assign temp Rx array to the ENET buffer */ + dmaRxDscrBase[ i ].dmaAddr = (u32)&(RxBuff[ i ][ 0 ]); + + /* Initialize RX ENET Status and control */ + dmaRxDscrBase[ i ].dmaStatCntl = 0x4000; + + /* Initialize the next descriptor- In our case its single descriptor */ + dmaRxDscrBase[ i ].dmaNext = (u32)&(dmaRxDscrBase[i+1]) | 0x01; + + /* Set the max packet size */ + dmaRxDscrBase[ i ].dmaStatCntl = ENET_MAX_PACKET_SIZE | ENET_NEXT_ENABLE; + + /* Setting the VALID bit */ + dmaRxDscrBase[ i ].dmaPackStatus = DMA_DSCR_RX_STATUS_VALID_MSK; + } + + dmaRxDscrBase[ ENET_NUM_RX_BUFFERS - 1 ].dmaNext = (u32)&(dmaRxDscrBase[ 0 ]); + + /* Setting the RX NEXT Descriptor Register inside the ENET */ + ENET_DMA->RXNDAR = (u32)&(dmaRxDscrBase) | 0x01; +} + +/******************************************************************************* +* Function Name : ENET_TxDscrInit +* Description : Initializes the Tx ENET descriptor chain with single descriptor +* Input : None +* Output : None +* Return : None +*******************************************************************************/ + +void ENET_TxDscrInit(void) +{ + + /* ENET Start Address */ + dmaTxDscrBase.dmaAddr = (u32)TxBuff; + + /* Next Descriptor Address */ + dmaTxDscrBase.dmaNext = (u32)&(dmaTxDscrBase); + + /* Initialize ENET status and control */ + dmaTxDscrBase.dmaStatCntl = 0; + + /* Tx next set to Tx decriptor base */ + ENET_DMA->TXNDAR = (u32)&(dmaTxDscrBase); + + /* Enable next enable */ + ENET_DMA->TXNDAR |= DMA_DSCR_NXT_NPOL_EN; + +} + +/******************************************************************************* +* Function Name : ENET_Init +* Description : ENET MAC, PHY and DMA initializations +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void ENET_Init () +{ + + vu32 regValue; + ENET_MACConfig *MAC_Config; + ENET_MACConfig config; + + /* De-assert the SRESET bit of ENET + MAC devices */ + ENET_DMA->SCR &=~DMA_SCR_SRESET; + MAC_Config =&config; + /* Initialize MAC control register with common values */ + MAC_Config->ReceiveALL = DISABLE; + if (SCU_GetHCLKFreqValue() > 50000) + MAC_Config->MIIPrescaler = MIIPrescaler_2; + MAC_Config->LoopbackMode = DISABLE; + MAC_Config->AddressFilteringMode = MAC_Perfect_Multicast_Perfect; + MAC_Config->VLANFilteringMode = VLANfilter_VLTAG; + MAC_Config->PassWrongFrame = DISABLE; + MAC_Config->LateCollision = DISABLE; + MAC_Config->BroadcastFrameReception = ENABLE; + MAC_Config->PacketRetry = ENABLE; + MAC_Config->RxFrameFiltering = ENABLE; + MAC_Config->AutomaticPadRemoval = ENABLE; + MAC_Config->DeferralCheck = ENABLE; + + /* Configure MAC control register */ + ENET_MACControlConfig(MAC_Config); + + /* DMA initialization */ + /* Read the ENET DMA Status and Control Register */ + regValue = ENET_DMA->SCR; + + /* Setup Tx Max burst size */ + regValue &= ~(u32)DMA_SCR_TX_MAX_BURST_SZ; + regValue |= (u32)DMA_SCR_TX_MAX_BURST_SZ_VAL; + + /* Setup Rx Max Burst size */ + regValue &= ~(u32)DMA_SCR_RX_MAX_BURST_SZ; + regValue |= (u32)DMA_SCR_RX_MAX_BURST_SZ_VAL; + + /* Write Tx & Rx burst size to the ENET status and control register */ + ENET_DMA->SCR = regValue; + + /* Put the PHY in reset mode */ + ENET_MIIWriteReg(0x0,MAC_MII_REG_XCR, 0x8000); + + /* Delay to assure PHY reset */ + vTaskDelay( 3000 / portTICK_RATE_MS ); + + /* initialize the opearting mode */ + while( ENET_SetOperatingMode() == pdFAIL ) + { + vTaskDelay( 3000 / portTICK_RATE_MS ); + } + + /*set MAC physical*/ + //ENET_MAC->MAH = (MAC_ADDR5<<8) + MAC_ADDR4; + //ENET_MAC->MAL = (MAC_ADDR3<<24) + (MAC_ADDR2<<16) + (MAC_ADDR1<<8) + MAC_ADDR0; + + /* Initialize Rx and Tx descriptors in memory */ + ENET_TxDscrInit(); + ENET_RxDscrInit(); + + // What's happening ??? +#ifdef DEBUG + //int pippo = 1; // Do NOT remove!!! +#endif +} + +/******************************************************************************** +* Function Name : ENET_HandleRxPkt +* Description : receive a packet and copy it to memory pointed by ppkt. +* Input : ppkt: pointer on application receive buffer. +* Output : None +* Return : ENET_NOK - If there is no packet +* : ENET_OK - If there is a packet +*******************************************************************************/ +u32 ENET_HandleRxPkt ( void *ppkt) +{ +ENET_DMADSCRBase *pDescr; +u16 size; +static int iNextRx = 0; + + if( dmaRxDscrBase[ iNextRx ].dmaPackStatus & DMA_DSCR_RX_STATUS_VALID_MSK ) + { + return 0; + } + + pDescr = &dmaRxDscrBase[ iNextRx ]; + + /*Get the size of the packet*/ + size = ((pDescr->dmaPackStatus & 0x7ff) - 4); + + //MEMCOPY_L2S_BY4((u8*)ppkt, RxBuff, size); /*optimized memcopy function*/ + memcpy(ppkt, RxBuff[iNextRx], size); //string.h library*/ + + /* Give the buffer back to ENET */ + pDescr->dmaPackStatus = DMA_DSCR_RX_STATUS_VALID_MSK; + + iNextRx++; + + if( iNextRx >= ENET_NUM_RX_BUFFERS ) + { + iNextRx = 0; + } + + /* Return no error */ + return size; +} + +/******************************************************************************* +* Function Name : ENET_TxPkt +* Description : Transmit a packet +* Input : ppkt: pointer to application packet Buffer +* : size: Tx Packet size +* Output : None +* Return : None +*******************************************************************************/ + +u8 *pcGetNextBuffer( void ) +{ + if( dmaTxDscrBase.dmaPackStatus & DMA_DSCR_TX_STATUS_VALID_MSK ) + { + return NULL; + } + else + { + return ( unsigned char * ) TxBuff; + } +} + +void ENET_TxPkt(void *ppkt, u16 size) +{ + /* Setting the Frame Length*/ + dmaTxDscrBase.dmaStatCntl = (size&0xFFF); + + /* Start the ENET by setting the VALID bit in dmaPackStatus of current descr*/ + dmaTxDscrBase.dmaPackStatus = DMA_DSCR_TX_STATUS_VALID_MSK; + + /* Start the transmit operation */ + ENET_DMA->TXSTR|= DMA_TX_START_FETCH; +} + +/******************************************************************************* +* Function Name : ENET_Start +* Description : Enables ENET MAC reception / transmission & starts DMA fetch +* Input : None +* Output : None +* Return : None +*******************************************************************************/ + +void ENET_Start ( void) +{ + u32 value; + + /* Force a ENET abort by software for the receive block */ + ENET_DMA->RXSTR &=~ DMA_RX_START_DMA_EN; + + /* Force a ENET abort by software for the transmit block */ + ENET_DMA->TXSTR &=~DMA_TX_START_DMA_EN; + + /* Reset all interrupts */ + ENET_DMA->ISR = 0xFFFFFFFF; + + /* Setup Descriptor Fetch ENET_PhyDelay for Receive Block */ + value = ENET_DMA->RXSTR; + value &= ~( DMA_RX_START_DFETCH_DLY ); + value |= DMA_RX_START_DFETCH_DEFAULT; + ENET_DMA->RXSTR= value; + + /* Setup Descriptor Fetch ENET_PhyDelay for Transmit Block */ + value = ENET_DMA->TXSTR; + value &= ~( DMA_TX_START_DFETCH_DLY ); + value |= DMA_TX_START_DFETCH_DEFAULT; + ENET_DMA->TXSTR= value; + + /* Set Tx underrun bit */ + value &= ~( DMA_TX_START_URUN ); + value |= DMA_TX_START_URUN; + ENET_DMA->TXSTR = value; + + /* Clear the interrupts */ + ENET_DMA->IER = 0x0; + + /* MAC TX enable */ + ENET_MAC->MCR|= MAC_MCR_TE; + + /* MAC RX enable */ + ENET_MAC->MCR|= MAC_MCR_RE; + + /* Start the DMA Fetch */ + ENET_DMA->RXSTR|= DMA_RX_START_FETCH; +} + + +/******************************************************************************* +* Function Name : ENET_InitClocksGPIO +* Description : Reset, clocks & GPIO Ethernet Pin initializations +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void ENET_InitClocksGPIO(void) +{ + + GPIO_InitTypeDef GPIO_Struct; + + SCU_AHBPeriphClockConfig(__ENET, ENABLE); + SCU_AHBPeriphReset(__ENET,DISABLE); + SCU_PHYCLKConfig(ENABLE); + + GPIO_DeInit(GPIO1); + GPIO_Struct.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 |GPIO_Pin_3 |GPIO_Pin_4 |GPIO_Pin_7 ; + GPIO_Struct.GPIO_Type = GPIO_Type_PushPull; + GPIO_Struct.GPIO_Direction = GPIO_PinOutput; + GPIO_Struct.GPIO_IPConnected = GPIO_IPConnected_Disable; + GPIO_Struct.GPIO_Alternate=GPIO_OutputAlt2; + GPIO_Init(GPIO1, &GPIO_Struct); + + + GPIO_DeInit(GPIO5); + GPIO_Struct.GPIO_Pin = GPIO_Pin_2 | GPIO_Pin_3; + GPIO_Struct.GPIO_Type = GPIO_Type_PushPull; + GPIO_Struct.GPIO_Direction = GPIO_PinOutput; + GPIO_Struct.GPIO_IPConnected = GPIO_IPConnected_Disable; + GPIO_Struct.GPIO_Alternate=GPIO_OutputAlt2; + GPIO_Init(GPIO5, &GPIO_Struct); + +} + +/******************** (C) COPYRIGHT 2006 STMicroelectronics *******************/ + + diff --git a/20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_fmi.c b/20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_fmi.c new file mode 100644 index 000000000..fb558ada6 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_fmi.c @@ -0,0 +1,519 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_fmi.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the FMI software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + + +/* Standard include ----------------------------------------------------------*/ +#include "91x_fmi.h" + +/* Include of other module interface headers ---------------------------------*/ +/* Local includes ------------------------------------------------------------*/ +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +#define TIMEOUT 0xFFFFFF /* Timeout value */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Interface functions -------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + + +/******************************************************************************* +* Function Name : FMI_BankRemapConfig +* Description : Configure the addresses and sizes of bank 0 and bank 1. +* Input1 : FMI_BootBankSize: specifies the boot bank size. +* This parameter can be one of the following values: +* - 0x0: 32KBytes. +* - 0x1: 64KBytes. +* - 0x2: 128KBytes. +* - 0x3: 256KBytes. +* - 0x4: 512KBytes. +* .... +* - 0xB: 64MBytes. +* Input2 : FMI_NonBootBankSize: specifies the non boot bank size. +* This parameter can be one of the following values: +* - 0x0: 8KBytes. +* - 0x1: 16KBytes. +* - 0x2: 32KBytes. +* - 0x3: 64KBytes. +* .... +* - 0xD: 64MBytes. +* Input3 : FMI_BootBankAddress: specifies the address of the boot bank. +* Input4 : FMI_NonBootBankAddress: specifies the address of the non +* boot bank. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_BankRemapConfig(u8 FMI_BootBankSize, u8 FMI_NonBootBankSize, \ + u32 FMI_BootBankAddress, u32 FMI_NonBootBankAddress) +{ + FMI->BBSR = FMI_BootBankSize; + FMI->NBBSR = FMI_NonBootBankSize; + FMI->BBADR = (FMI_BootBankAddress >> 2); + FMI->NBBADR = (FMI_NonBootBankAddress >> 2); + FMI->CR |= 0x18; /* Enable bank 1 */ +} + +/******************************************************************************* +* Function Name : FMI_Config +* Description : Configure the FMI. +* Input1 : FMI_ReadWaitState: specifies the needed read wait states. +* This parameter can be one of the following values: +* - FMI_READ_WAIT_STATE_1: One read wait state. +* - FMI_READ_WAIT_STATE_2: Two read wait states. +* - FMI_READ_WAIT_STATE_3: Three read wait states. +* Input2 : FMI_WriteWaitState: specifies the needed write wait states. +* This parameter can be one of the following values: +* - FMI_WRITE_WAIT_STATE_1: One write wait state. +* - FMI_WRITE_WAIT_STATE_2: Two write wait states. +* Input3 : FMI_PWD: specifies the power down mode status. +* This parameter can be one of the following values: +* - FMI_PWD_ENABLE: Enable the PWD. +* - FMI_PWD_DISABLE: Disable the PWD. +* Input4 : FMI_LVDEN: specifies the low voltage detector status. +* This parameter can be one of the following values: +* - FMI_LVD_ENABLE: Enable the LVD. +* - FMI_LVD_DISABLE: Disable the LVD. +* Input5 : FMI_FreqRange: specifies the working frequency range. +* This parameter can be one of the following values: +* - FMI_FREQ_LOW: Low working frequency (up to 66MHz). +* - FMI_FREQ_HIGH: High working frequency (above 66MHz) . +* Output : None +* Return : None +*******************************************************************************/ +void FMI_Config(u16 FMI_ReadWaitState, u32 FMI_WriteWaitState, u16 FMI_PWD,\ + u16 FMI_LVDEN, u16 FMI_FreqRange) +{ + /* Configure the write wait state value */ + if (FMI_WriteWaitState == FMI_WRITE_WAIT_STATE_1) + { + FMI->CR |= FMI_WRITE_WAIT_STATE_1; + } + else + { + FMI->CR &= FMI_WRITE_WAIT_STATE_0; + } + + /* Write a write flash configuration register command */ + *(vu16 *)FMI_BANK_1 = 0x60; + + /* Configure the flash configuration register */ + *(vu16 *)(FMI_BANK_1|FMI_ReadWaitState|FMI_PWD|FMI_LVDEN|FMI_FreqRange) = 0x03; +} + +/******************************************************************************* +* Function Name : FMI_EraseSector +* Description : Erase the needed sector. +* Input : FMI_Sector: specifies the sector to be erased. +* This parameter can be one of the following values: +* - FMI_B0S0: FMI bank 0 sector 0. +* - FMI_B0S1: FMI bank 0 sector 1. +* - FMI_B0S2: FMI bank 0 sector 2. +* - FMI_B0S3: FMI bank 0 sector 3. +* - FMI_B0S4: FMI bank 0 sector 4. +* - FMI_B0S5: FMI bank 0 sector 5. +* - FMI_B0S6: FMI bank 0 sector 6. +* - FMI_B0S7: FMI bank 0 sector 7. +* - FMI_B1S0: FMI bank 1 sector 0. +* - FMI_B1S1: FMI bank 1 sector 1. +* - FMI_B1S2: FMI bank 1 sector 2. +* - FMI_B1S3: FMI bank 1 sector 3. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_EraseSector(vu32 FMI_Sector) +{ + /* Write an erase set-up command to the sector */ + *(vu16 *)FMI_Sector = 0x20; + + /* Write an erase confirm command to the sector */ + *(vu16 *)FMI_Sector = 0xD0; +} + +/******************************************************************************* +* Function Name : FMI_EraseBank +* Description : Erase the needed bank. +* Input : FMI_Bank: specifies the bank to be erased. +* This parameter can be one of the following values: +* - FMI_BANK_0: FMI bank 0. +* - FMI_BANK_1: FMI bank 1. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_EraseBank(vu32 FMI_Bank) +{ + /* Write a bank erase set-up command to the bank */ + *(vu16 *)FMI_Bank = 0x80; + + /* Write an erase confirm command to the sector */ + *(vu16 *)FMI_Bank = 0xD0; +} + +/******************************************************************************* +* Function Name : FMI_WriteHalfWord +* Description : Write a halfword to the needed Flash memory address. +* Input 1 : FMI_Address: specifies the address offset where the data will +* be written. +* Input 2 : FMI_Data: the needed data. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_WriteHalfWord(u32 FMI_Address, u16 FMI_Data) +{ + /* Write a program command to the sector to be written */ + *(vu16 *)(FMI_Address & 0xFFFFFFFC) = 0x40; + + /* Write the halfword to the destination address */ + *(vu16 *)FMI_Address = FMI_Data; +} + +/******************************************************************************* +* Function Name : FMI_WriteOTPHalfWord +* Description : Write a halfword to the needed OTP sector address. +* Input 1 : FMI_OTPHWAddress: specifies the halfword address offset +* where the data will be written. +* This parameter can be one of the following values: +* - FMI_OTP_LOW_HALFWORD_0: OTP Low halfword 0. +* - FMI_OTP_HIGH_HALFWORD_0: OTP High halfword 0. +* - FMI_OTP_LOW_HALFWORD_1: OTP Low halfword 1. +* - FMI_OTP_HIGH_HALFWORD_1: OTP High halfword 1. +* - FMI_OTP_LOW_HALFWORD_2: OTP Low halfword 2. +* - FMI_OTP_HIGH_HALFWORD_2: OTP High halfword 2. +* - FMI_OTP_LOW_HALFWORD_3: OTP Low halfword 3. +* - FMI_OTP_HIGH_HALFWORD_3: OTP High halfword 3. +* - FMI_OTP_LOW_HALFWORD_4: OTP Low halfword 4. +* - FMI_OTP_HIGH_HALFWORD_4: OTP High halfword 4. +* - FMI_OTP_LOW_HALFWORD_5: OTP Low halfword 5. +* - FMI_OTP_HIGH_HALFWORD_5: OTP High halfword 5. +* - FMI_OTP_LOW_HALFWORD_6: OTP Low halfword 6. +* - FMI_OTP_HIGH_HALFWORD_6: OTP High halfword 6. +* - FMI_OTP_LOW_HALFWORD_7: OTP Low halfword 7. +* - FMI_OTP_HIGH_HALFWORD_7: OTP High halfword 7. +* Input 2 : FMI_OTPData: The needed OTP data. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_WriteOTPHalfWord(u8 FMI_OTPHWAddress, u16 FMI_OTPData) +{ + /* Write a write OTP command to the needed address */ + *(vu16 *)(FMI_BANK_1) = 0xC0; + + /* Write the halfword to the destination address */ + *(vu16 *)(FMI_BANK_1 + FMI_OTPHWAddress) = FMI_OTPData; +} + +/******************************************************************************* +* Function Name : FMI_ReadWord +* Description : Read the correspondent data. +* Input : FMI_Address: specifies the needed address. +* Output : None +* Return : The data contained in the specified address. +*******************************************************************************/ +u32 FMI_ReadWord(u32 FMI_Address) +{ + return(*(u32*)FMI_Address); +} + +/******************************************************************************* +* Function Name : FMI_ReadOTPData +* Description : Read data from the OTP sector. +* Input : FMI_OTPAddress: specifies the address of the data to be read. +* This parameter can be one of the following values: +* - FMI_OTP_WORD_0: FMI bank 0 sector 0. +* - FMI_OTP_WORD_1: FMI bank 0 sector 1. +* - FMI_OTP_WORD_2: FMI bank 0 sector 2. +* - FMI_OTP_WORD_3: FMI bank 0 sector 3. +* - FMI_OTP_WORD_4: FMI bank 0 sector 4. +* - FMI_OTP_WORD_5: FMI bank 0 sector 5. +* - FMI_OTP_WORD_6: FMI bank 0 sector 6. +* - FMI_OTP_WORD_7: FMI bank 0 sector 7. +* Output : None +* Return : The needed OTP words. +*******************************************************************************/ +u32 FMI_ReadOTPData(u8 FMI_OTPAddress) +{ + u32 OTP_Data = 0x0; + /* write a read OTP sector command */ + *(vu16 *)(FMI_BANK_1) = 0x98; + + /* Read the correspondent data */ + OTP_Data = (*(vu32*)(FMI_BANK_1 + FMI_OTPAddress)); + + /* Write a read array command */ + *(vu16 *)(FMI_BANK_1) = 0xFF; + + return OTP_Data; +} + +/******************************************************************************* +* Function Name : FMI_GetFlagStatus +* Description : Check whether the specified FMI flag is set or not. +* Input1 : FMI_Flag: flag to check. +* This parameter can be one of the following values: +* - FMI_FLAG_SPS: Sector Protection Status Flag. +* - FMI_FLAG_PSS: Program Suspend Status Flag. +* - FMI_FLAG_PS: Program Status Flag. +* - FMI_FLAG_ES: Erase Status Flag. +* - FMI_FLAG_ESS: Erase Suspend Status Flag. +* - FMI_FLAG_PECS: FPEC Status Flag. +* Input2 : FMI_Bank: specifies the needed bank. +* This parameter can be one of the following values: +* - FMI_BANK_0: FMI bank 0. +* - FMI_BANK_1: FMI bank 1. +* Output : None +* Return : None +*******************************************************************************/ +FlagStatus FMI_GetFlagStatus(u8 FMI_Flag, vu32 FMI_Bank) +{ + u16 FMI_Status_Register = 0; + + /* Write a read status register command */ + *(vu16 *)FMI_Bank = 0x70; + + /* Wait until operation completion */ + while(!((*(vu16 *)FMI_Bank) & 0x80)); + + /* Read the status register */ + FMI_Status_Register = *(vu16 *)FMI_Bank; + + /* Write a read array command */ + *(vu16 *)FMI_Bank = 0xFF; + + if((FMI_Status_Register & FMI_Flag) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : FMI_GetReadWaitStateValue +* Description : Get the current Read wait state value. +* Input : None +* Output : None +* Return : The current read wait states value. +*******************************************************************************/ +u16 FMI_GetReadWaitStateValue(void) +{ + u16 FMI_Configuration_Register = 0; + /* Write a read flash configuration register command */ + *(vu16 *)FMI_BANK_1 = 0x90; + + /* Read the flash configuration register */ + FMI_Configuration_Register = *(vu16 *)(FMI_BANK_1 + 0x14); + + /* Write a read array command */ + *(vu16 *)FMI_BANK_1 = 0xFF; + + FMI_Configuration_Register = ((FMI_Configuration_Register>>11) + 1) & 0x3; + + /* Return the wait states value */ + return FMI_Configuration_Register; +} + +/******************************************************************************* +* Function Name : FMI_GetWriteWaitStateValue +* Description : Get the current write wait state value. +* Input : None +* Output : None +* Return : The current write wait states value. +*******************************************************************************/ +u16 FMI_GetWriteWaitStateValue(void) +{ + return ((u16)((FMI->CR & 0x100) >> 8)); +} + +/******************************************************************************* +* Function Name : FMI_SuspendEnable +* Description : Suspend command enable. +* Input : FMI_Bank: specifies the bank to be suspended. +* This parameter can be one of the following values: +* - FMI_BANK_0: FMI bank 0. +* - FMI_BANK_1: FMI bank 1. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_SuspendEnable(vu32 FMI_Bank) +{ + /* Write a suspend command to the bank */ + *(vu16 *)FMI_Bank = 0xB0; +} + +/******************************************************************************* +* Function Name : FMI_ResumeEnable +* Description : Resume the suspended command. +* Input : FMI_Bank: specifies the suspended bank. +* This parameter can be one of the following values: +* - FMI_BANK_0: FMI bank 0. +* - FMI_BANK_1: FMI bank 1. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_ResumeEnable(vu32 FMI_Bank) +{ + /* Write a resume command to the bank */ + *(vu16 *)FMI_Bank = 0xD0; +} + +/******************************************************************************* +* Function Name : FMI_ClearFlag +* Description : Clear the FMI Flags on the correspondent bank. +* Input : FMI_Bank: specifies the needed bank. +* This parameter can be one of the following values: +* - FMI_BANK_0: FMI bank 0. +* - FMI_BANK_1: FMI bank 1. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_ClearFlag(vu32 FMI_Bank) +{ + /* Write a clear status register command */ + *(vu16 *)FMI_Bank = 0x50; +} + +/******************************************************************************* +* Function Name : FMI_WriteProtectionCmd +* Description : Enable or disable the write protection for the needed sector. +* Input1 : FMI_Sector: specifies the sector to be protected or +* unprotected. +* This parameter can be one of the following values: +* - FMI_B0S0: FMI bank 0 sector 0. +* - FMI_B0S1: FMI bank 0 sector 1. +* - FMI_B0S2: FMI bank 0 sector 2. +* - FMI_B0S3: FMI bank 0 sector 3. +* - FMI_B0S4: FMI bank 0 sector 4. +* - FMI_B0S5: FMI bank 0 sector 5. +* - FMI_B0S6: FMI bank 0 sector 6. +* - FMI_B0S7: FMI bank 0 sector 7. +* - FMI_B1S0: FMI bank 1 sector 0. +* - FMI_B1S1: FMI bank 1 sector 1. +* - FMI_B1S2: FMI bank 1 sector 2. +* - FMI_B1S3: FMI bank 1 sector 3. +* Input2 : FMI_NewState: specifies the protection status. +* This parameter can be one of the following values: +* - ENABLE: Enable the protection. +* - DISABLE: Disable the protection. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_WriteProtectionCmd(vu32 FMI_Sector, FunctionalState FMI_NewState) +{ + if (FMI_NewState == ENABLE) + { + *(vu16*)FMI_Sector = 0x60; + *(vu16*)FMI_Sector = 0x01; + *(vu16*)FMI_Sector = 0xFF; + } + else /* DISABLE */ + { + *(vu16*)FMI_Sector = 0x60; + *(vu16*)FMI_Sector = 0xD0; + *(vu16*)FMI_Sector = 0xFF; + } +} + +/******************************************************************************* +* Function Name : FMI_GetWriteProtectionStatus +* Description : Get the write protection status for the needed sector. +* Input : FMI_Sector_Mask: specifies the needed sector mask. +* This parameter can be one of the following values: +* - FMI_B0S0_MASK: FMI bank 0 sector 0. +* - FMI_B0S1_MASK: FMI bank 0 sector 1. +* - FMI_B0S2_MASK: FMI bank 0 sector 2. +* - FMI_B0S3_MASK: FMI bank 0 sector 3. +* - FMI_B0S4_MASK: FMI bank 0 sector 4. +* - FMI_B0S5_MASK: FMI bank 0 sector 5. +* - FMI_B0S6_MASK: FMI bank 0 sector 6. +* - FMI_B0S7_MASK: FMI bank 0 sector 7. +* - FMI_B1S0_MASK: FMI bank 1 sector 0. +* - FMI_B1S1_MASK: FMI bank 1 sector 1. +* - FMI_B1S2_MASK: FMI bank 1 sector 2. +* - FMI_B1S3_MASK: FMI bank 1 sector 3. +* Output : None +* Return : The Protection Status of the needed sector. +* - RESET: The needed sector is not write protected. +* - SET : The needed sector is write protected. +*******************************************************************************/ +FlagStatus FMI_GetWriteProtectionStatus(u32 FMI_Sector_Mask) +{ + u16 Protection_Level_1_Register = 0; + /* Write a read flash protection level 1 register command */ + *(vu16 *)FMI_BANK_1 = 0x90; + + /* Read the flash protection level 1 register */ + Protection_Level_1_Register = *(vu16 *)(FMI_BANK_1 + 0x10); + + /* Write a read array command */ + *(vu16 *)FMI_BANK_1 = 0xFF; + + if (Protection_Level_1_Register &= FMI_Sector_Mask) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : FMI_WaitForLastOperation +* Description : Wait until the last operation (Write halfword, Write OTP +* halfword, Erase sector and Erase bank) completion. +* Input : FMI_Bank: specifies the bank where the operation is on going. +* This parameter can be one of the following values: +* - FMI_BANK_0: FMI bank 0. +* - FMI_BANK_1: FMI bank 1. +* Output : None +* Return : The timeout status. +* This parameter can be one of the following values: +* - FMI_TIME_OUT_ERROR: Timeout error occurred. +* - FMI_NO_TIME_OUT_ERROR: No timeout error. +*******************************************************************************/ +u8 FMI_WaitForLastOperation(vu32 FMI_Bank) +{ + u32 Time_Out = 0; + + /* Write a read status register command */ + *(vu16 *)(FMI_Bank) = 0x70; + + /* Wait until operation compeletion */ + while((!((*(vu16 *)FMI_Bank) & 0x80))&&(Time_Out < TIMEOUT )) + { + Time_Out ++; /* Time Out */ + } + + /* Write a read array command */ + *(vu16 *)FMI_Bank = 0xFF; + + if (Time_Out == TIMEOUT) + { + return FMI_TIME_OUT_ERROR; + } + else + { + return FMI_NO_TIME_OUT_ERROR; + } +} + + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_gpio.c b/20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_gpio.c new file mode 100644 index 000000000..f2d094199 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_gpio.c @@ -0,0 +1,407 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_gpio.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the GPIO software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_gpio.h" +#include "91x_scu.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + static u8 GPIO_GetGPIONumber(GPIO_TypeDef* GPIOx); + +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : GPIO_DeInit +* Description : Deinitializes the GPIOx peripheral registers to their default +* reset values. +* Input : GPIOx: where x can be (0..9) to select the GPIO peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_DeInit(GPIO_TypeDef* GPIOx) +{ + + /* Reset the GPIO registers values */ + if(GPIOx == GPIO0) + { + SCU_APBPeriphReset(__GPIO0,ENABLE); + SCU_APBPeriphReset(__GPIO0,DISABLE); + SCU->GPIOTYPE[0x00] = 0x0000 ; + SCU->GPIOOUT[0x00] = 0x0000; + SCU->GPIOIN[0x00] = 0x0000; + } + + if(GPIOx == GPIO1) + { + SCU_APBPeriphReset(__GPIO1,ENABLE); + SCU_APBPeriphReset(__GPIO1,DISABLE); + SCU->GPIOTYPE[0x01] = 0x0000 ; + SCU->GPIOOUT[0x01] = 0x0000; + SCU->GPIOIN[0x01] = 0x0000; + } + + if(GPIOx == GPIO2) + { + SCU_APBPeriphReset(__GPIO2,ENABLE); + SCU_APBPeriphReset(__GPIO2,DISABLE); + SCU->GPIOTYPE[0x02] = 0x0000 ; + SCU->GPIOOUT[0x02] = 0x0000; + SCU->GPIOIN[0x02] = 0x0000; + } + + if(GPIOx == GPIO3) + { + SCU_APBPeriphReset(__GPIO3,ENABLE); + SCU_APBPeriphReset(__GPIO3,DISABLE); + SCU->GPIOTYPE[0x03] = 0x0000 ; + SCU->GPIOOUT[0x03] = 0x0000; + SCU->GPIOIN[0x03] = 0x0000; + } + + if(GPIOx == GPIO4) + { + SCU_APBPeriphReset(__GPIO4,ENABLE); + SCU_APBPeriphReset(__GPIO4,DISABLE); + SCU->GPIOTYPE[0x04] = 0x0000 ; + SCU->GPIOOUT[0x04] = 0x0000; + SCU->GPIOIN[0x04] = 0x0000; + SCU->GPIOANA = 0x00; + } + + if(GPIOx == GPIO5) + { + SCU_APBPeriphReset(__GPIO5,ENABLE); + SCU_APBPeriphReset(__GPIO5,DISABLE); + SCU->GPIOTYPE[0x05] = 0x0000 ; + SCU->GPIOOUT[0x05] = 0x0000; + SCU->GPIOIN[0x05] = 0x0000; + } + + if(GPIOx == GPIO6) + { + SCU_APBPeriphReset(__GPIO6,ENABLE); + SCU_APBPeriphReset(__GPIO6,DISABLE); + SCU->GPIOTYPE[0x06] = 0x0000 ; + SCU->GPIOOUT[0x06] = 0x0000; + SCU->GPIOIN[0x06] = 0x0000; + } + + if(GPIOx == GPIO7) + { + SCU_APBPeriphReset(__GPIO7,ENABLE); + SCU_APBPeriphReset(__GPIO7,DISABLE); + SCU->GPIOOUT[0x07] = 0xAAAA; + SCU->GPIOOUT[0x07] = 0x0000; + SCU->GPIOIN[0x07] = 0x0000; + } + + if(GPIOx == GPIO8) + { + SCU_APBPeriphReset(__GPIO8,ENABLE); + SCU_APBPeriphReset(__GPIO8,DISABLE); + SCU->GPIOEMI = 0x00; + } + + if(GPIOx == GPIO9) + { + SCU_APBPeriphReset(__GPIO9,ENABLE); + SCU_APBPeriphReset(__GPIO9,DISABLE); + SCU->GPIOEMI = 0x00; + } +} +/******************************************************************************* +* Function Name : GPIO_Init +* Description : Initializes the GPIOx peripheral according to the specified +* parameters in the GPIO_InitStruct . +* Input :- GPIOx: where x can be (0..9) to select the GPIO peripheral. +* - GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that +* contains the configuration information for the specified GPIO +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) +{ + /* Select pin direction */ + u8 PinNumber = 0; + u8 Counter = 0; + u8 GPIO_Number = 0; + + GPIO_Number = GPIO_GetGPIONumber(GPIOx); + + + if(GPIO_InitStruct->GPIO_Direction == GPIO_PinOutput) + { + GPIOx->DDR |= GPIO_InitStruct->GPIO_Pin; + } + else + { + GPIOx->DDR &= ~GPIO_InitStruct->GPIO_Pin; + } + + for (Counter = 0; Counter < 8;Counter++) + { + /*Search pin number*/ + PinNumber = (GPIO_InitStruct->GPIO_Pin & (1 <> Counter) == 1) + { + /*Output ALternate 0*/ + SCU->GPIOOUT[GPIO_Number] &= ~(0x3 <<(Counter *2)); + if(GPIO_InitStruct->GPIO_Alternate == GPIO_OutputAlt1) + { + /*Output ALternate 1*/ + SCU->GPIOOUT[GPIO_Number] |= 1 << (Counter *2); + } + if(GPIO_InitStruct->GPIO_Alternate == GPIO_OutputAlt2) + { + /*Output ALternate 2*/ + SCU->GPIOOUT[GPIO_Number] |= 0x2 << (Counter *2); + } + if(GPIO_InitStruct->GPIO_Alternate == GPIO_OutputAlt3) + { + /*Output ALternate 3*/ + SCU->GPIOOUT[GPIO_Number] |= 0x3 << (Counter *2); + } + + /*Type configuration: PushPull or Open Collector*/ + SCU->GPIOTYPE[GPIO_Number] &= ~(0x1 << Counter) ; + if(GPIO_InitStruct->GPIO_Type == GPIO_Type_OpenCollector) + { + /*Open Drain configuration*/ + SCU->GPIOTYPE[GPIO_Number] |= 0x1 << Counter; + } + + /*IP Connected disable*/ + SCU->GPIOIN[GPIO_Number] &= ~(0x1 << Counter) ; + if(GPIO_InitStruct->GPIO_IPConnected == GPIO_IPConnected_Enable) + { + /*IP Connected enable*/ + SCU->GPIOIN[GPIO_Number] |= 0x1 << Counter; + } + } + } +} + +/******************************************************************************* +* Function Name : GPIO_StructInit +* Description : Initialize the GPIO Init Structure parameters +* Input : GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) +{ + /* Reset GPIO init structure parameters values */ + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; + GPIO_InitStruct->GPIO_Direction = GPIO_PinInput; + GPIO_InitStruct->GPIO_Type = GPIO_Type_PushPull; + GPIO_InitStruct->GPIO_IPConnected = GPIO_IPConnected_Disable; + GPIO_InitStruct->GPIO_Alternate = GPIO_InputAlt1; +} + +/******************************************************************************* +* Function Name : GPIO_ReadBit +* Description : Reads the specified port pin +* Input : - GPIOx: where x can be (0..9) to select the GPIO peripheral. +* : - GPIO_Pin: the Pin number. This parameter can be GPIO_Pin_x +* where x can be (0..7). +* Output : None +* Return : The port pin value +*******************************************************************************/ +u8 GPIO_ReadBit(GPIO_TypeDef* GPIOx, u8 GPIO_Pin) +{ + if ((((GPIOx->DR[GPIO_Pin<<2])) & GPIO_Pin) != Bit_RESET ) + { + return Bit_SET; + } + else + { + return Bit_RESET; + } +} + +/******************************************************************************* +* Function Name : GPIO_Read +* Description : Reads the specified GPIO data port +* Input : - GPIOx: where x can be (0..9) to select the GPIO peripheral. +* Output : None +* Return : GPIO data port word value. +*******************************************************************************/ +u8 GPIO_Read(GPIO_TypeDef* GPIOx) +{ + return (GPIOx->DR[0x3FC]); +} + +/******************************************************************************* +* Function Name : GPIO_WriteBit +* Description : Sets or clears the selected data port bit. +* Input : - GPIOx: where x can be (0..9) to select the GPIO peripheral. +* - GPIO_Pin: the Pin number. This parameter can be GPIO_Pin_x +* where x can be (0..7). +* - BitVal: this parameter specifies the value to be written +* to the selected bit. +* BitVal must be one of the BitAction enum values: +* - Bit_RESET: to clear the port pin +* - Bit_SET: to set the port pin +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u8 GPIO_Pin, BitAction BitVal) +{ + if(BitVal == Bit_SET) + { + GPIOx->DR[GPIO_Pin <<2] = GPIO_Pin; + } + else + { + GPIOx->DR[GPIO_Pin <<2] = 0x00; + } +} + +/******************************************************************************* +* Function Name : GPIO_Write +* Description : Writes the passed value in the selected data GPIOx port +* register. +* Input :- GPIOx: where x can be (0..9) to select the GPIO peripheral. +* - PortVal: the value to be written to the data port register. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_Write(GPIO_TypeDef* GPIOx, u8 PortVal) +{ + GPIOx->DR[0x3FC] = PortVal; +} + +/******************************************************************************* +* Function Name : GPIO_EMIConfig +* Description : Enables or disables GPIO 8 and 9 in EMI mode. +* Input : - NewState: new state of the EMI. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_EMIConfig(FunctionalState NewState) +{ + if(NewState == ENABLE) + { + SCU->GPIOEMI = 0x01; + } + else + { + SCU->GPIOEMI = 0x00; + } +} + +/******************************************************************************* +* Function Name : GPIO_ANAPinConfig +* Description : Enables or disables pins from GPIO 4 in Analogue mode. +* Input :- GPIO_ANAChannel: selects the ADC channel pin. +* This parameter can be one of the following values: +* GPIO_ANAChannel0 +* GPIO_ANAChannel1 +* GPIO_ANAChannel2 +* GPIO_ANAChannel3 +* GPIO_ANAChannel4 +* GPIO_ANAChannel5 +* GPIO_ANAChannel6 +* GPIO_ANAChannel7 +* GPIO_ANAChannelALL +* - NewState: new state of the port pin. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_ANAPinConfig(u8 GPIO_ANAChannel, FunctionalState NewState) +{ + + if(NewState == ENABLE) + { + if(GPIO_ANAChannel == GPIO_ANAChannelALL) + { + SCU->GPIOOUT[4] = 0x0000; + SCU->GPIOIN[4] = 0x00; + } + else + { + SCU->GPIOOUT[4] &= ~(0x3<<(GPIO_ANAChannel-1)); + SCU->GPIOIN[4] &= ~GPIO_ANAChannel; + } + SCU->GPIOANA |= GPIO_ANAChannel; + + } + else + { + SCU->GPIOANA &= ~GPIO_ANAChannel; + } +} + +/******************************************************************************* +* Function Name : GPIO_GetGPIONumber +* Description : searche the GPIO number. +* Input : GPIOx: where x can be (0..9) to select the GPIO peripheral. +* Output : None +* Return : GPIO number +*******************************************************************************/ +u8 GPIO_GetGPIONumber(GPIO_TypeDef* GPIOx) +{ + + if(GPIOx == GPIO1) + { + return 1; + } + if(GPIOx == GPIO2) + { + return 2; + } + if(GPIOx == GPIO3) + { + return 3; + } + if(GPIOx == GPIO4) + { + return 4; + } + if(GPIOx == GPIO5) + { + return 5; + } + if(GPIOx == GPIO6) + { + return 6; + } + if(GPIOx == GPIO7) + { + return 7; + } + if(GPIOx == GPIO8) + { + return 8; + } + if(GPIOx == GPIO9) + { + return 9; + } + return 0; +} +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_it.c b/20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_it.c new file mode 100644 index 000000000..adf5696c9 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_it.c @@ -0,0 +1,387 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_it.c +* Author : MCD Application Team +* Date First Issued : 03/31/2006 : Beta Version V0.1 +* Description : Main Interrupt Service Routines. +******************************************************************************** +* This file can be used to describe all the exceptions subroutines +* that may occur within user application. +* When an interrupt happens, the software will branch automatically +* to the corresponding routine according to the interrupt vector +* loaded in the PC register. +* The following routines are all empty, user can write code for +* exceptions handlers and peripherals IRQ interrupts. +******************************************************************************** +* History: +* 03/31/2006 : Beta Version V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ +#include "FreeRTOSConfig.h" +#include "91x_it.h" + +/******************************************************************************* +* Function Name : Undefined_Handler +* Description : This function Undefined instruction exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void Undefined_Handler(void) +{ + // NOT USED. +} +/******************************************************************************* +* Function Name : SWI_Handler +* Description : This function handles SW exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SWI_Handler(void) +{ + // NOT USED. +} +/******************************************************************************* +* Function Name : Prefetch_Handler +* Description : This function handles preftetch abort exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void Prefetch_Handler(void) +{ + // NOT USED. +} +/******************************************************************************* +* Function Name : Abort_Handler +* Description : This function handles data abort exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void Abort_Handler(void) +{ + // NOT USED. +} +/******************************************************************************* +* Function Name : FIQ_Handler +* Description : This function handles FIQ exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void FIQ_Handler(void) +{ + // NOT USED. +} +/******************************************************************************* +* Function Name : SW_IRQHandler +* Description : This function handles the SW interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SW_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : ARMRX_IRQHandler +* Description : This function handles the ARMRX interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void ARMRX_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : ARMTX_IRQHandler +* Description : This function handles the ARMTX interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void ARMTX_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : TIM0_IRQHandler +* Description : This function handles the TIM0 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM0_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : TIM1_IRQHandler +* Description : This function handles the TIM1 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : TIM2_IRQHandler +* Description : This function handles the TIM2 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +//void TIM2_IRQHandler(void) +//{ +//} +/******************************************************************************* +* Function Name : TIM3_IRQHandler +* Description : This function handles the TIM3 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM3_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : USBHP_IRQHandler +* Description : This function handles the USBHP interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void USBHP_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : USBLP_IRQHandler +* Description : This function handles the USBLP interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void USBLP_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : SCU_IRQHandler +* Description : This function handles the SCU interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SCU_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : DMA_IRQHandler +* Description : This function handles the DMA interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void DMA_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : CAN_IRQHandler +* Description : This function handles the CAN interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void CAN_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : MC_IRQHandler +* Description : This function handles the MC interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void MC_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : ADC_IRQHandler +* Description : This function handles the ADC interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void ADC_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : UART0_IRQHandler +* Description : This function handles the UART0 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void UART0_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : UART2_IRQHandler +* Description : This function handles the UART2 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void UART2_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : I2C0_IRQHandler +* Description : This function handles the I2C0 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void I2C0_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : I2C1_IRQHandler +* Description : This function handles the I2C1 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void I2C1_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : SSP0_IRQHandler +* Description : This function handles the SSP0 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SSP0_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : SSP1_IRQHandler +* Description : This function handles the SSP1 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SSP1_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : LVD_IRQHandler +* Description : This function handles the LVD interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void LVD_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : RTC_IRQHandler +* Description : This function handles the RTC interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RTC_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : WIU_IRQHandler +* Description : This function handles the WIU interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void WIU_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : EXTIT0_IRQHandler +* Description : This function handles the EXTIT0 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void EXTIT0_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : EXTIT1_IRQHandler +* Description : This function handles the EXTIT1 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void EXTIT1_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : EXTIT2_IRQHandler +* Description : This function handles the EXTIT2 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void EXTIT2_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : EXTIT3_IRQHandler +* Description : This function handles the EXTIT3 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void EXTIT3_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : USBWU_IRQHandler +* Description : This function handles the USBWU interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void USBWU_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : PFQBC_IRQHandler +* Description : This function handles the PFQBC interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void PFQBC_IRQHandler(void) +{ +} + +#if configUSE_WATCHDOG_TICK == 0 + /* The kernel is not using the watchdog interrupt so it can be defined here. */ + void WDG_IRQHandler( void ) + { + } +#else + /* The kernel is not using the timer 2 interrupt so it can be defined here. */ + void TIM2_IRQHandler( void ) + { + } +#endif /* configUSE_WATCHDOG_TICK */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_lib.c b/20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_lib.c new file mode 100644 index 000000000..c0eadbb94 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_lib.c @@ -0,0 +1,281 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_lib.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all peripherals pointers + : initialization. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ +#define EXT + +/* Standard include ----------------------------------------------------------*/ +#include "91x_map.h" + +/* Include of other module interface headers ---------------------------------*/ +/* Local includes ------------------------------------------------------------*/ +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Interface functions -------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +#ifdef DEBUG + +/******************************************************************************* +* Function Name : debug +* Description : this function initialize peripherals pointers +* Input : no one +* Output : no one +* Return : no one +*******************************************************************************/ +void debug(void) +{ + + +/************************* DMA *************************/ + +#ifdef _DMA + DMA = (DMA_TypeDef *)DMA_BASE; +#endif /* _DMA */ + +/************************* DMA *************************/ + + +#ifdef _DMA_Channel0 + DMA_Channel0= (DMA_Channel_TypeDef *)DMA_Channel0_BASE; +#endif /* _DMA_Channel0 */ + +#ifdef _DMA_Channel1 + DMA_Channel1= (DMA_Channel_TypeDef *)DMA_Channel1_BASE; +#endif /* _DMA_Channel1 */ + +#ifdef _DMA_Channel2 + DMA_Channel2 = (DMA_Channel_TypeDef *)DMA_Channel2_BASE; +#endif /* _DMA_Channel2 */ + +#ifdef _DMA_Channel3 + DMA_Channel3 = (DMA_Channel_TypeDef *)DMA_Channel3_BASE; +#endif /* _DMA_Channel3 */ + +#ifdef _DMA_Channel4 + DMA_Channel4 = (DMA_Channel_TypeDef *)DMA_Channel4_BASE; +#endif /* _DMA_Channel4 */ + +#ifdef _DMA_Channel5 + DMA_Channel5= (DMA_Channel_TypeDef *)DMA_Channel5_BASE; +#endif /* _DMA_Channel5*/ + + +#ifdef _DMA_Channel6 + DMA_Channel6 = (DMA_Channel_TypeDef *)DMA_Channel6_BASE; +#endif /* _DMA_Channel6 */ + +#ifdef _DMA_Channel7 + DMA_Channel7 = (DMA_Channel_TypeDef *)DMA_Channel7_BASE; +#endif /* _DMA_Channel7 */ + + + + /************************* EMI *************************/ + +#ifdef _EMI_Bank0 + EMI_Bank0= (EMI_Bank_TypeDef *)EMI_Bank0_BASE; +#endif /* _EMI_Bank0 */ + +#ifdef _EMI_Bank1 + EMI_Bank1= (EMI_Bank_TypeDef *)EMI_Bank1_BASE; +#endif /* _EMI_Bank1 */ + +#ifdef _EMI_Bank2 + EMI_Bank2 = (EMI_Bank_TypeDef *)EMI_Bank2_BASE; +#endif /* _EMI_Bank2 */ + +#ifdef _EMI_Bank3 + EMI_Bank3 = (EMI_Bank_TypeDef *)EMI_Bank3_BASE; + #endif /* _EMI_Bank3 */ + + + +/************************* AHBAPB *************************/ + +#ifdef _AHBAPB0 + AHBAPB0 = (AHBAPB_TypeDef *)AHBAPB0_BASE; +#endif /* _AHBAPB0 */ + +#ifdef _AHBAPB1 + AHBAPB1 = (AHBAPB_TypeDef *)AHBAPB1_BASE; +#endif /*_AHBAPB1 */ + + + +/************************* FMI *************************/ + +#ifdef _FMI + FMI = (FMI_TypeDef *)FMI_BASE; +#endif /* _FMI */ + +/************************* VIC *************************/ + +#ifdef _VIC0 + VIC0 = (VIC_TypeDef *)VIC0_BASE; +#endif /* _VIC0 */ + +#ifdef _VIC1 + VIC1 = (VIC_TypeDef *)VIC1_BASE; +#endif /* _VIC1 */ + +/************************* WIU *************************/ + +#ifdef _WIU + WIU = (WIU_TypeDef *)WIU_BASE; +#endif /* _WIU */ + +/************************* TIM *************************/ + +#ifdef _TIM0 + TIM0 = (TIM_TypeDef *)TIM0_BASE; +#endif /* _TIM0 */ + +#ifdef _TIM1 + TIM1 = (TIM_TypeDef *)TIM1_BASE; +#endif /* _TIM1 */ + +#ifdef _TIM2 + TIM2 = (TIM_TypeDef *)TIM2_BASE; +#endif /* _TIM2 */ + +#ifdef _TIM3 + TIM3 = (TIM_TypeDef *)TIM3_BASE; +#endif /* _TIM3 */ + +/************************* GPIO ************************/ + +#ifdef _GPIO0 + GPIO0 = (GPIO_TypeDef *)GPIO0_BASE; +#endif /* _GPIO0 */ + +#ifdef _GPIO1 + GPIO1 = (GPIO_TypeDef *)GPIO1_BASE; +#endif /* _GPIO1 */ + +#ifdef _GPIO2 + GPIO2 = (GPIO_TypeDef *)GPIO2_BASE; +#endif /* _GPIO2 */ + +#ifdef _GPIO3 + GPIO3 = (GPIO_TypeDef *)GPIO3_BASE; +#endif /* _GPIO3 */ + +#ifdef _GPIO4 + GPIO4 = (GPIO_TypeDef *)GPIO4_BASE; +#endif /* _GPIO4 */ + +#ifdef _GPIO5 + GPIO5 = (GPIO_TypeDef *)GPIO5_BASE; +#endif /* _GPIO5 */ + +#ifdef _GPIO6 + GPIO6 = (GPIO_TypeDef *)GPIO6_BASE; +#endif /* _GPIO6 */ + +#ifdef _GPIO7 + GPIO7 = (GPIO_TypeDef *)GPIO7_BASE; +#endif /* _GPIO7 */ + +#ifdef _GPIO8 + GPIO8 = (GPIO_TypeDef *)GPIO8_BASE; +#endif /* _GPIO8 */ + +#ifdef _GPIO9 + GPIO9 = (GPIO_TypeDef *)GPIO9_BASE; +#endif /* _GPIO9 */ + +/************************* RTC *************************/ + +#ifdef _RTC + RTC = (RTC_TypeDef *)RTC_BASE; +#endif /* _RTC */ + +/************************* PRCCU ***********************/ + +#ifdef _SCU + SCU = (SCU_TypeDef *)SCU_BASE; +#endif /* _PRCCU */ + +/************************** MC *************************/ + +#ifdef _MC + MC = (MC_TypeDef *)MC_BASE; +#endif /* _MC */ + +/************************* UART ************************/ + +#ifdef _UART0 + UART0 = (UART_TypeDef *)UART0_BASE; +#endif /* _UART0 */ + +#ifdef _UART1 + UART1 = (UART_TypeDef *)UART1_BASE; +#endif /* _UART1 */ + +#ifdef _UART2 + UART2 = (UART_TypeDef *)UART2_BASE; +#endif /* _UART2 */ + +/************************* SSP *************************/ + +#ifdef _SSP0 + SSP0 = (SSP_TypeDef *)SSP0_BASE; +#endif /* _SSP0 */ + +#ifdef _SSP1 + SSP1 = (SSP_TypeDef *)SSP1_BASE; +#endif /* _SSP1 */ + +/************************* CAN *************************/ + +#ifdef _CAN + CAN = (CAN_TypeDef *)CAN_BASE; +#endif /* _CAN */ + +/************************* ADC *************************/ + +#ifdef _ADC + ADC = (ADC_TypeDef *)ADC_BASE; +#endif /* _ADC */ + +/************************* WDG *************************/ + +#ifdef _WDG + WDG = (WDG_TypeDef *)WDG_BASE; +#endif /* _WDG */ + +/************************* I2C *************************/ + +#ifdef _I2C0 + I2C0 = (I2C_TypeDef *)I2C0_BASE; +#endif /* _I2C0 */ + +#ifdef _I2C1 + I2C1 = (I2C_TypeDef *)I2C1_BASE; +#endif /* _I2C1 */ +/********************** ENET **************************/ +#ifdef _ENET + ENET_MAC = (ENET_MAC_TypeDef *)ENET_MAC_BASE; + ENET_DMA = (ENET_DMA_TypeDef *)ENET_DMA_BASE; +#endif /* _ENET */ +} +#endif /* DEBUG */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_scu.c b/20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_scu.c new file mode 100644 index 000000000..21116b2a3 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_scu.c @@ -0,0 +1,661 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_scu.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides the SCU library software functions +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_scu.h" + +/* Include of other module interface headers ---------------------------------*/ +/* Local includes ------------------------------------------------------------*/ +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define SCU_PLLEN 0x80000 +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Interface functions -------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : SCU_MCLKSourceConfig +* Description : Configures the MCLK source clock +* Input : MCLK_Source = SCU_MCLK_OSC, SCU_MCLK_PLL or SCU_MCLK_RTC +* Output : None +* Return : ErrorStatus: SUCCESS or ERROR +* Note : this function returns ERROR if trying to select the PLL as +* clock source while the PLL is disabled or not locked. +*******************************************************************************/ +ErrorStatus SCU_MCLKSourceConfig(u32 MCLK_Source) +{ + u32 CLKCNTR_Value; + + CLKCNTR_Value = SCU->CLKCNTR; /*get CLKCNTR register value*/ + CLKCNTR_Value &=~0x3; /*clear field MCLKSEL*/ + if (MCLK_Source == SCU_MCLK_PLL) /*PLL selected as clock source*/ + { + /*check if PLL enabled & locked*/ + if (!((SCU->PLLCONF&SCU_PLLEN)&&(SCU->SYSSTATUS&SCU_FLAG_LOCK))) + return ERROR; + } + else CLKCNTR_Value |=MCLK_Source; /*OSC or RTC selected as clock source*/ + SCU->CLKCNTR = CLKCNTR_Value; /*Update CLKCNTR register value*/ + return SUCCESS; +} + +/******************************************************************************* +* Function Name : SCU_PLLFactorsConfig +* Description : Sets the PLL factors +* Input : PLLN, PLLM and PLLP +* Output : None +* Return : ErrorStatus: ERROR or SUCCESS +* Notes : -The PLL factors must respect the PLL specification requirements +* -The function returns ERROR if trying to change PLL +* factors while PLL is selected as Main Clock source (MCLK) +* -This function disables the PLL, to enable the PLL use +* function" SCU_PLLCmd(ENABLE)" after setting the PLL factors +******************************************************************************/ +ErrorStatus SCU_PLLFactorsConfig(u8 PLLN, u8 PLLM, u8 PLLP) +{ + if (SCU_PLLCmd(DISABLE)==SUCCESS) /*Disable PLL*/ + { + SCU->PLLCONF =0; /*clear PLLCONF register*/ + SCU->PLLCONF |=(PLLN<<8); /*update PLLN field*/ + SCU->PLLCONF |=PLLM; /*update PLLM field*/ + SCU->PLLCONF |=PLLP<<16; /*update PLLP field*/ + return SUCCESS; + } + return ERROR; +} + +/******************************************************************************* +* Function Name : SCU_PLLCmd +* Description : Enable or Disable the PLL +* Input : NewState = ENABLE or DISABLE +* Output : None +* Return : ErrorStatus: SUCCESS or ERROR +* Note : -The function returns ERROR if: +* *trying to disable the PLL while it is selected as the MCLK +* *trying to enable the PLL while it is already enabled and +* locked +*******************************************************************************/ +ErrorStatus SCU_PLLCmd(FunctionalState NewState) +{ + vu32 i; + if (NewState==ENABLE) + { + if (!((SCU->PLLCONF&SCU_PLLEN)&&(SCU->SYSSTATUS&SCU_FLAG_LOCK))) + { + SCU->SYSSTATUS|=SCU_FLAG_LOCK; /*clear LOCK bit*/ + SCU->PLLCONF |=SCU_PLLEN; /*PLL Enable*/ + while(!SCU->SYSSTATUS&SCU_FLAG_LOCK); /*Wait PLL to lock*/ + return SUCCESS; + } + else return ERROR; + } + else /*NewState = DISABLE*/ + { + if(SCU->CLKCNTR&0x3) /*check if PLL not sys CLK*/ + { + for(i=10;i>0;i--); /*delay before PLL disabling*/ + SCU->PLLCONF &=~SCU_PLLEN; /*PLL Disable*/ + return SUCCESS; + } + else return ERROR; + } +} + +/******************************************************************************* +* Function Name : SCU_RCLKDivisorConfig +* Description : Sets the RCLK divisor value +* Input : RCLK_Divisor +* Output : None +* Return : None +*******************************************************************************/ +void SCU_RCLKDivisorConfig(u32 RCLK_Divisor) +{ + SCU->CLKCNTR &=SCU_RCLK_Div1; /*clear RCLKDIV[2:0] field*/ + if (RCLK_Divisor!=SCU_RCLK_Div1) + SCU->CLKCNTR |= RCLK_Divisor; /*update field with RCLK divisor*/ +} + +/******************************************************************************* +* Function Name : SCU_HCLKDivisorConfig +* Description : Sets the HCLK divisor value +* Input : HCLK_Divisor +* Output : None +* Return : None +*******************************************************************************/ +void SCU_HCLKDivisorConfig(u32 HCLK_Divisor) +{ + SCU->CLKCNTR &=SCU_HCLK_Div1; /*clear AHBDIV[1:0] field*/ + if (HCLK_Divisor!=SCU_HCLK_Div1) + SCU->CLKCNTR |= HCLK_Divisor; /*update field with HCLK divisor*/ +} + +/******************************************************************************* +* Function Name : SCU_PCLKDivisorConfig +* Description : Sets the PCLK divisor value +* Input : PCLK_Divisor +* Output : None +* Return : None +*******************************************************************************/ +void SCU_PCLKDivisorConfig(u32 PCLK_Divisor) +{ + SCU->CLKCNTR &=SCU_PCLK_Div1; /*clear APBDIV[1:0] field*/ + if (PCLK_Divisor!=SCU_PCLK_Div1) + SCU->CLKCNTR |= PCLK_Divisor; /*update field with PCLK Divisor*/ +} + +/******************************************************************************* +* Function Name : SCU_APBPeriphClockConfig +* Description : Enable the clock for an APB peripheral +* Input : -APBPerip : APB peripherals(__RTC, __ADC ,...) +* -NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_APBPeriphClockConfig(u32 APBPeriph, FunctionalState NewState) +{ + if (NewState==ENABLE) /*Enable clock for APB peripheral*/ + SCU->PCGR1 |=APBPeriph; + else + SCU->PCGR1 &=~APBPeriph; /*Disable clock for APB peripheral*/ +} + +/******************************************************************************* +* Function Name : SCU_AHBPeriphClockConfig +* Description : Enable the clock for an AHB peripheral +* Input : -AHBPerip: AHB peripherals(__USB, __DMA,...) +* -NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_AHBPeriphClockConfig(u32 AHBPeriph, FunctionalState NewState) +{ + if (NewState==ENABLE) /*Enable clock for AHB peripheral*/ + SCU->PCGRO |=AHBPeriph; + else + SCU->PCGRO &=~AHBPeriph; /*Disable clock for AHB peripheral*/ +} + +/******************************************************************************* +* Function Name : SCU_APBPeriphReset +* Description : Assert or deassert Reset on APB peripheral +* Input : -APBPeriph: APB peripherals(__RTC, __ADC,...) + -NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_APBPeriphReset(u32 APBPeriph, FunctionalState NewState) +{ + if (NewState==DISABLE) /*APB peripheral not held in Reset*/ + SCU->PRR1 |=APBPeriph; + else + SCU->PRR1 &=~APBPeriph; /*APB peripheral held in Reset*/ +} + +/******************************************************************************* +* Function Name : SCU_AHBPeriphReset +* Description : Assert or deassert Reset on AHB peripheral +* Input : -AHBPeriph: AHB peripherals(__USB, __DMA,...) + -NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_AHBPeriphReset(u32 AHBPeriph, FunctionalState NewState) +{ + if (NewState==DISABLE) + SCU->PRR0 |=AHBPeriph; /*AHB peripheral not held in Reset*/ + else + SCU->PRR0 &=~AHBPeriph; /*AHB peripheral held in Reset*/ +} + +/******************************************************************************* +* Function Name : SCU_APBPeriphIdleConfig +* Description : Enable or Disable Periph Clock during Idle mode +* Input : -APBPeriph: APB peripherals(__RTC, __ADC,...) + -NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_APBPeriphIdleConfig(u32 APBPeriph, FunctionalState NewState) +{ + if (NewState==ENABLE) + SCU->MGR1 |=APBPeriph; /*APB peripheral clock enabled during Idle mode*/ + else + SCU->MGR1 &=~APBPeriph; /*APB peripheral clock disabled during Idle mode*/ +} + +/******************************************************************************* +* Function Name : SCU_AHBPeriphIdleConfig +* Description : Enable or Disable Periph Clock during Idle mode +* Input : -AHBPeriph: AHB peripherals(__USB, __DMA,...) + -NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_AHBPeriphIdleConfig(u32 AHBPeriph, FunctionalState NewState) +{ + if (NewState==ENABLE) + SCU->MGR0 |=AHBPeriph; /*AHB peripheral clock enabled during Idle mode*/ + else + SCU->MGR0 &=~AHBPeriph; /*AHB peripheral clock disabled during Idle mode*/ +} + +/******************************************************************************* +* Function Name : SCU_APBPeriphDebugConfig +* Description : Enable or Disable Periph Clock during ARM debug state +* Input : -APBPeriph: APB peripherals(__RTC, __ADC,...) + -NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_APBPeriphDebugConfig(u32 APBPeriph, FunctionalState NewState) +{ + if (NewState==ENABLE) + SCU->PECGR1 |=APBPeriph; /*APB peripheral clock enabled during ARM debug state*/ + else + SCU->PECGR1 &=~APBPeriph; /*APB peripheral clock disabled during ARM debug state*/ +} + +/******************************************************************************* +* Function Name : SCU_AHBPeriphDebugConfig +* Description : Enable or Disable Periph Clock during ARM debug state +* Input : -AHBPeriph: AHB peripherals(__USB, __DMA,...) + -NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_AHBPeriphDebugConfig(u32 AHBPeriph, FunctionalState NewState) +{ + if (NewState==ENABLE) + SCU->PECGR0 |=AHBPeriph; /*AHB peripheral clock enabled during ARM debug state*/ + else + SCU->PECGR0 &=~AHBPeriph; /*AHB peripheral clock disabled during ARM debug state*/ +} +/******************************************************************************* +* Function Name : SCU_BRCLKDivisorConfig +* Description : Sets the BRCLK divisor value +* Input : BRCLK_Divisor +* Output : None +* Return : None +*******************************************************************************/ +void SCU_BRCLKDivisorConfig(u32 BRCLK_Divisor) +{ + SCU->CLKCNTR &=SCU_BRCLK_Div1; /*Clear BRSEL bit*/ + if (BRCLK_Divisor!=SCU_BRCLK_Div1) + SCU->CLKCNTR |= SCU_BRCLK_Div2; /*set bit BRSEL*/ +} + +/******************************************************************************* +* Function Name : SCU_TIMCLKSourceConfig +* Description : Sets the TIMx clock source +* Input : - TIMx : SCU_TIM01 or SCU_TIM23 +* - TIMCLK_Source = SCU_TIMCLK_EXT or SCU_TIMCLK_INT +* Output : None +* Return : None +*******************************************************************************/ +void SCU_TIMCLKSourceConfig(u8 TIMx, u32 TIMCLK_Source) +{ + if (TIMx== SCU_TIM01) /*TIM01 clock source configuration*/ + { + SCU->CLKCNTR &=0xFFFFDFFF; + if (TIMCLK_Source == SCU_TIMCLK_EXT) + SCU->CLKCNTR |=0x2000; + } + else + { + SCU->CLKCNTR &=0xFFFFBFFF; /*TIM23 clock source configuration*/ + if (TIMCLK_Source == SCU_TIMCLK_EXT) + SCU->CLKCNTR |=0x4000; + } +} + +/******************************************************************************* +* Function Name : SCU_TIMPresConfig +* Description : Sets the TIMx Prescaler Value +* Input : - TIMx : SCU_TIM01 or SCU_TIM23 +* - Prescaler (16 bit value) +* Output : None +* Return : None +*******************************************************************************/ +void SCU_TIMPresConfig(u8 TIMx, u16 Prescaler) +{ + if (TIMx==SCU_TIM01) /*TIM01 Prescaler configuration*/ + SCU->SCR1 = Prescaler&0xFFFF; + else + SCU->SCR2 = Prescaler&0xFFFF; /*TIM23 Prescaler configuration*/ +} + +/******************************************************************************* +* Function Name : SCU_USBCLKConfig +* Description : Configures the clock source for the 48MHz USBCLK +* Input : USBCLK_Source: SCU_USBCLK_MCLK,SCU_USBCLK_MCLK2 or SCU_USBCLK_EXT +* Output : None +* Return : None +*******************************************************************************/ +void SCU_USBCLKConfig(u32 USBCLK_Source) +{ + SCU->CLKCNTR &=SCU_USBCLK_MCLK; /*clear USBSEL[1:0] field*/ + if (USBCLK_Source!=SCU_USBCLK_MCLK) + SCU->CLKCNTR |= USBCLK_Source; /*update field with USBCLK_Source*/ +} + +/******************************************************************************* +* Function Name : SCU_PHYCLKConfig +* Description : Enable or Disable PHY clock output +* Input : NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_PHYCLKConfig(FunctionalState NewState) +{ + if (NewState==ENABLE) + SCU->CLKCNTR |= 0x1000; /*enable MIIPHY clock*/ + else + SCU->CLKCNTR &=~0x1000; /*disable MIIPHY clock*/ +} + +/******************************************************************************* +* Function Name : SCU_FMICLKDivisorConfig +* Description : Set the FMI clock divisor +* Input : FMICLK_Divisor: SCU_FMICLK_Div1 or SCU_FMICLK_DIV2 +* Output : None +* Return : None +*******************************************************************************/ +void SCU_FMICLKDivisorConfig(u32 FMICLK_Divisor) +{ + SCU->CLKCNTR &=SCU_FMICLK_Div1; /*FMICLK = RCLK*/ + if (FMICLK_Divisor!=SCU_FMICLK_Div1) + SCU->CLKCNTR |=SCU_FMICLK_Div2; /*FMICLK = RCLK/2 */ +} + +/******************************************************************************* +* Function Name : SCU_EMIBCLKDivisorConfig +* Description : Set the EMI Bus clock divisor: EMIBCLK = HCLK or HCLK/2 +* Input : SCU_EMICLK: SCU_EMIBCLK_Div1 , SCU_EMIBCLK_Div2 +* Output : None +* Return : None +*******************************************************************************/ +void SCU_EMIBCLKDivisorConfig(u32 SCU_EMIBCLK) +{ + SCU->CLKCNTR &=SCU_EMIBCLK_Div1; /*EMIBCLK = HCLK */ + if (SCU_EMIBCLK!=SCU_EMIBCLK_Div1) + SCU->CLKCNTR |= SCU_EMIBCLK_Div2; /*EMIBCLK = HCLK/2 */ +} + +/******************************************************************************* +* Function Name : SCU_EMIModeConfig +* Description : Configure the EMI as Multiplexed or Demultiplexed +* Input : SCU_EMIMODE : SCU_EMI_MUX or SCU_EMI_DEMUX +* Output : None +* Return : None +*******************************************************************************/ +void SCU_EMIModeConfig(u32 SCU_EMIMODE) +{ + SCU->SCR0 &=SCU_EMI_MUX; /*EMI mode = Multiplexed*/ + if (SCU_EMIMODE!=SCU_EMI_MUX) + SCU->SCR0 |= SCU_EMI_DEMUX; /*EMI mode = Demultiplexed*/ +} + +/******************************************************************************* +* Function Name : SCU_EMIALEConfig +* Description : Configure the ALE signal (length & polarity) +* Input : -SCU_EMIALE_LEN : SCU_EMIALE_LEN1 or SCU_EMIALE_LEN2 +* -SCU_EMIALE_POL : SCU_EMIALE_POLLow or SCU_EMI_POLHigh +* Output : None +* Return : None +*******************************************************************************/ +void SCU_EMIALEConfig(u32 SCU_EMIALE_LEN, u32 SCU_EMIALE_POL) +{ + /*Configure EMI ALE Length*/ + SCU->SCR0 &=SCU_EMIALE_LEN1; + if (SCU_EMIALE_LEN!=SCU_EMIALE_LEN1) + SCU->SCR0 |= SCU_EMIALE_LEN2; + + /*Configure EMI ALE POL*/ + SCU->SCR0 &=SCU_EMIALE_POLLow; + if (SCU_EMIALE_POL!=SCU_EMIALE_POLLow) + SCU->SCR0 |= SCU_EMIALE_POLHigh; +} + +/******************************************************************************* +* Function Name : SCU_ITConfig +* Description : ENBALE or DISABLE an SCU interrupt +* Input : -SCU_IT: interrupt mask +* -NewState: ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_ITConfig(u32 SCU_IT, FunctionalState NewState) +{ + if (NewState==ENABLE) + SCU->ITCMSK&=~SCU_IT; /*IT enable */ + else + SCU->ITCMSK|=SCU_IT; /*IT disable( mask)*/ +} + +/******************************************************************************* +* Function Name : SCU_GetFlagStatus +* Description : Returns flag status +* Input : SCU_Flag +* Output : NONE +* Return : SET or RESET +*******************************************************************************/ +FlagStatus SCU_GetFlagStatus(u32 SCU_Flag) +{ + if (SCU->SYSSTATUS&SCU_Flag) + return SET; + else return RESET; +} + +/******************************************************************************* +* Function Name : SCU_ClearFlag +* Description : Clears a SYSTATUS Flag +* Input : SCU_Flag +* Output : None +* Return : None +*******************************************************************************/ +void SCU_ClearFlag(u32 SCU_Flag) +{ + SCU->SYSSTATUS = SCU_Flag; +} +/******************************************************************************* +* Function Name : SCU_GetPLLfreqValue +* Description : Gets the current PLL frequency +* Input : None +* Output : None +* Return : PLL frequency (KHz) +*******************************************************************************/ +u32 SCU_GetPLLFreqValue(void) +{ + u8 PLL_M; + u8 PLL_N; + u8 PLL_P; + + PLL_M = SCU->PLLCONF&0xFF; + PLL_N = (SCU->PLLCONF&0xFF00)>>8; + PLL_P = (SCU->PLLCONF&0x70000)>>16; + + if ((PLL_M>0)&&(PLL_N>0)) + return (u32)(((_Main_Crystal*2)*PLL_N)/(PLL_M<CLKCNTR&0x3) == 0x2) return (u32)(_Main_Crystal); + if ((SCU->CLKCNTR&0x3) == 0x1) return (u32)(32); + else return (SCU_GetPLLFreqValue()); +} + +/******************************************************************************* +* Function Name : SCU_GetRCLKFreqValue +* Description : Gets the current RCLK frequency +* Input : None +* Output : None +* Return : RCLK frequency (KHz) +*******************************************************************************/ +u32 SCU_GetRCLKFreqValue(void) +{ + u8 RCLK_Div; + RCLK_Div = (SCU->CLKCNTR&0x1C)>>2; + if (RCLK_Div==0x5) RCLK_Div=10; + return (u32)(SCU_GetMCLKFreqValue() >>RCLK_Div); +} + +/******************************************************************************* +* Function Name : SCU_GetHCLKFreqValue +* Description : Gets the current PCLK frequency +* Input : None +* Output : None +* Return : HCLK frequency (KHz) +*******************************************************************************/ +u32 SCU_GetHCLKFreqValue(void) +{ + u8 HCLK_Div; + HCLK_Div = (SCU->CLKCNTR&0x60)>>5; + return (u32)(SCU_GetRCLKFreqValue() >>HCLK_Div); +} + +/******************************************************************************* +* Function Name : SCU_GetPCLKFreqValue +* Description : Gets the current HCLK frequency +* Input : None +* Output : None +* Return : PCLK frequency (KHz) +*******************************************************************************/ +u32 SCU_GetPCLKFreqValue(void) +{ + u8 PCLK_Div; + PCLK_Div = (SCU->CLKCNTR&0x180)>>7; + return (u32)(SCU_GetRCLKFreqValue() >>PCLK_Div); +} + +/******************************************************************************* +* Function Name : SCU_WakeUpLineConfig +* Description : Configures an External interrupt as WakeUp line +* Input : EXTint : 0 -> 31 +* Output : None +* Return : None +*******************************************************************************/ +void SCU_WakeUpLineConfig(u8 EXTint) +{ + if (EXTint < 8) + { + SCU->WKUPSEL&=~0x7; + SCU->WKUPSEL|=EXTint; + } + else if (EXTint<16) + { + SCU->WKUPSEL&=~0x38; + SCU->WKUPSEL|=(EXTint-8)<<3; + } + else if (EXTint<24) + { + SCU->WKUPSEL&=~0x1C0; + SCU->WKUPSEL|=(EXTint-16)<<6; + } + else + { + SCU->WKUPSEL&=~0xE00; + SCU->WKUPSEL|=(EXTint-24)<<9; + } +} + +/******************************************************************************* +* Function Name : SCU_SpecIntRunModeConfig +* Description : Enables or Disables the Special Run mode +* Input : newstate = ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_SpecIntRunModeConfig(FunctionalState NewState) +{ + if (NewState == ENABLE) + SCU->PWRMNG |=0x8; + else + SCU->PWRMNG &=~0x8; +} +/******************************************************************************* +* Function Name : SCU_EnterIdleMode +* Description : Enters in Idle mode +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SCU_EnterIdleMode(void) +{ + SCU->PWRMNG |=0x1; +} +/******************************************************************************* +* Function Name : SCU_EnterSleepMode +* Description : Enters in Sleep mode +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SCU_EnterSleepMode(void) +{ + SCU->PWRMNG |=0x2; +} + +/******************************************************************************* +* Function Name : SCU_UARTIrDAConfig +* Description : Enable or Disable the Irda mode for UARTx +* Input : - UARTx :x=0,1 or 2 +* - UART_IrDA_Mode : SCU_UARTMode_IrDA or SCU_UARTMode_UART +* Output : None +* Return : None +*******************************************************************************/ +void SCU_UARTIrDASelect(UART_TypeDef * UARTx, u8 UART_IrDA_Mode) +{ + if (UART_IrDA_Mode == SCU_UARTMode_IrDA) + { + if (UARTx== UART0) SCU->SCR0 |=0x400; + else if (UARTx==UART1) SCU->SCR0 |=0x800; + else SCU->SCR0 |=0x1000; + } + else + { + if (UARTx== UART0) SCU->SCR0 &=~0x400; + else if (UARTx==UART1) SCU->SCR0 &=~0x800; + else SCU->SCR0 &=~0x1000; + } +} +/******************************************************************************* +* Function Name : SCU_PFQBCCmd +* Description : Enable or Disable PFQBC +* Input : NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_PFQBCCmd(FunctionalState NewState) +{ + if (NewState==ENABLE) + SCU->SCR0 |=0x1; + else SCU->SCR0 &=~0x1; +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_tim.c b/20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_tim.c new file mode 100644 index 000000000..a0e78f0fd --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_tim.c @@ -0,0 +1,692 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_tim.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the TIM software functions. +******************************************************************************** +* History: +* 05/22/2007 : Version 1.2 +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_tim.h" + +/* Include of other module interface headers ---------------------------------*/ +/* Local includes ------------------------------------------------------------*/ +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* TIM Bits Masks */ + +#define TIM_PWM_MASK 0x0010 +#define TIM_OPM_MASK 0x0020 +#define TIM_OC1_ENABLE_MASK 0x0040 +#define TIM_OC1_DISABLE_MASK 0xFFBF +#define TIM_OC2_ENABLE_MASK 0x0080 +#define TIM_OC2_DISABLE_MASK 0xFF7F + +#define TIM_OLVL1_SET_MASK 0x0100 +#define TIM_OLVL1_RESET_MASK 0xFEFF + +#define TIM_OLVL2_SET_MASK 0x0200 +#define TIM_OLVL2_RESET_MASK 0xFDFF + +#define TIM_ENABLE_MASK 0x8000 +#define TIM_DISABLE_MASK 0x7FFF + +#define TIM_DMA_CLEAR_MASK 0xCFFF + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Interface functions -------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/******************************************************************************* +* Function Name : TIM_DeInit +* Description : Initializes TIM peripheral control and registers to their +* : default reset values. +* Input : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_DeInit(TIM_TypeDef *TIMx) +{ + if((TIMx == TIM0)||(TIMx == TIM1)) + { + SCU_APBPeriphReset(__TIM01, DISABLE); /* TIM0 & TIM1 Reset's off */ + } + else + { + SCU_APBPeriphReset(__TIM23, DISABLE); /* TIM2 & TIM3 Reset's off */ + } + + /* Set all the TIMx registers to thier default values */ + TIMx->OC1R = 0x8000; + TIMx->OC2R = 0x8000; + TIMx->CR1 = 0x0; + TIMx->CR2 = 0x1; + TIMx->CNTR = 0x1234; + TIMx->SR = 0x0; +} + +/******************************************************************************* +* Function Name : TIM_StructInit +* Description : Fills in a TIM_InitTypeDef structure with the reset value of +* each parameter. +* Input : TIM_InitStruct : pointer to a TIM_InitTypeDef structure + which will be initialized. +* Output : None +* Return : None. +*******************************************************************************/ +void TIM_StructInit(TIM_InitTypeDef *TIM_InitStruct) +{ + TIM_InitStruct->TIM_Mode = 0x0000; + TIM_InitStruct->TIM_OC1_Modes = 0x0000; + TIM_InitStruct->TIM_OC2_Modes = 0x0000; + TIM_InitStruct->TIM_Clock_Source = 0x0000; + TIM_InitStruct->TIM_Clock_Edge = 0x0000; + TIM_InitStruct->TIM_OPM_INPUT_Edge = 0x0000; + TIM_InitStruct->TIM_ICAP1_Edge = 0x0000; + TIM_InitStruct->TIM_ICAP2_Edge = 0x0000; + TIM_InitStruct->TIM_Prescaler = 0x0000; + TIM_InitStruct->TIM_Pulse_Level_1 = 0x0000; + TIM_InitStruct->TIM_Pulse_Level_2 = 0x0000; + TIM_InitStruct->TIM_Period_Level = 0x0000; + TIM_InitStruct->TIM_Pulse_Length_1 = 0x0000; + TIM_InitStruct->TIM_Pulse_Length_2 = 0x0000; + TIM_InitStruct->TIM_Full_Period = 0x0000; +} + +/******************************************************************************* +* Function Name : TIM_Init +* Description : Initializes TIM peripheral according to the specified +* parameters in the TIM_InitTypeDef structure. +* Input1 : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Input2 : TIM_InitStruct: pointer to a TIM_InitTypeDef structure that +* contains the configuration information for the specified +* TIM peripheral. +* Output : None +* Return : None +*******************************************************************************/ + +void TIM_Init(TIM_TypeDef *TIMx, TIM_InitTypeDef *TIM_InitStruct) +{ +/***************************** Clock configuration ****************************/ + + if (TIM_InitStruct->TIM_Clock_Source == TIM_CLK_APB) + { + /* APB clock */ + TIMx->CR1 &= TIM_CLK_APB; + } + else + { + /* External/SCU clock */ + TIMx->CR1 |= TIM_CLK_EXTERNAL; + if (TIM_InitStruct->TIM_Clock_Edge == TIM_CLK_EDGE_RISING) + { + /* Clock rising edge */ + TIMx->CR1 |= TIM_CLK_EDGE_RISING; + } + else + { + /* Clock falling edge */ + TIMx->CR1 &= TIM_CLK_EDGE_FALLING; + } + } + +/************************** Prescaler configuration ***************************/ + + TIMx->CR2 =( TIMx->CR2 & 0xFF00 )|TIM_InitStruct->TIM_Prescaler ; + +/********************************** TIM Modes *********************************/ + + switch ( TIM_InitStruct->TIM_Mode) + { +/******************************* PWM Input mode *******************************/ + + case TIM_PWMI: + + /* Set the PWMI Bit */ + TIMx->CR1 |= TIM_PWMI; + + /* Set the first edge Level */ + if ( TIM_InitStruct->TIM_ICAP1_Edge == TIM_ICAP1_EDGE_RISING) + { + TIMx->CR1 |= TIM_ICAP1_EDGE_RISING; + } + else + { + TIMx->CR1 &= TIM_ICAP1_EDGE_FALLING; + } + + /* Set the Second edge Level ( Opposite of the first level ) */ + if ( TIM_InitStruct->TIM_ICAP1_Edge == TIM_ICAP1_EDGE_RISING) + { + TIMx->CR1 &= TIM_ICAP2_EDGE_FALLING; + } + else + { + TIMx->CR1 |= TIM_ICAP2_EDGE_RISING; + } + + break; + +/************************** Output compare channel 1 **************************/ + + case TIM_OCM_CHANNEL_1: + + if (TIM_InitStruct->TIM_Pulse_Level_1 == TIM_HIGH) + { + TIMx->CR1 |= TIM_OLVL1_SET_MASK; + } + else + { + TIMx->CR1 &= TIM_OLVL1_RESET_MASK; + } + + TIMx->OC1R = TIM_InitStruct->TIM_Pulse_Length_1; + + if (TIM_InitStruct->TIM_OC1_Modes == TIM_TIMING) + { + TIMx->CR1 &= TIM_OC1_DISABLE_MASK; + } + else + { + TIMx->CR1 |= TIM_OC1_ENABLE_MASK; + } + + break; + +/************************** Output compare channel 2 **************************/ + + case TIM_OCM_CHANNEL_2: + + if (TIM_InitStruct->TIM_Pulse_Level_2 == TIM_HIGH) + { + TIMx->CR1 |= TIM_OLVL2_SET_MASK; + } + else + { + TIMx->CR1 &= TIM_OLVL2_RESET_MASK; + } + + TIMx->OC2R = TIM_InitStruct->TIM_Pulse_Length_2; + + if (TIM_InitStruct->TIM_OC2_Modes == TIM_TIMING) + { + TIMx->CR1 &= TIM_OC2_DISABLE_MASK; + } + else + { + TIMx->CR1 |= TIM_OC2_ENABLE_MASK; + } + + break; + +/************************ Output compare channel 1 & 2 ************************/ + + case TIM_OCM_CHANNEL_12: + + TIMx->OC2R = TIM_InitStruct->TIM_Pulse_Length_2; + TIMx->OC1R = TIM_InitStruct->TIM_Pulse_Length_1; + + if (TIM_InitStruct->TIM_OC2_Modes == TIM_TIMING) + { + TIMx->CR1 &= TIM_OC2_DISABLE_MASK; + } + else + { + TIMx->CR1 |= TIM_OC2_ENABLE_MASK; + } + + if (TIM_InitStruct->TIM_OC1_Modes == TIM_TIMING) + { + TIMx->CR1 &= TIM_OC1_DISABLE_MASK; + } + else + { + TIMx->CR1 |= TIM_OC1_ENABLE_MASK; + } + + if (TIM_InitStruct->TIM_Pulse_Level_1 == TIM_HIGH) + { + TIMx->CR1 |= TIM_OLVL1_SET_MASK; + } + else + { + TIMx->CR1 &= TIM_OLVL1_RESET_MASK; + } + + if (TIM_InitStruct->TIM_Pulse_Level_2 == TIM_HIGH) + { + TIMx->CR1 |= TIM_OLVL2_SET_MASK; + } + else + { + TIMx->CR1 &= TIM_OLVL2_RESET_MASK; + } + + break; + +/********************************** PWM mode **********************************/ + + case TIM_PWM: + + /* Set the Level During the pulse */ + if ( TIM_InitStruct->TIM_Pulse_Level_1 == TIM_HIGH) + { + TIMx->CR1 |= TIM_OLVL2_SET_MASK; + } + else + { + TIMx->CR1 &= TIM_OLVL2_RESET_MASK; + } + + /* Set the Level after the pulse */ + if (TIM_InitStruct->TIM_Period_Level == TIM_HIGH) + { + TIMx->CR1 |= TIM_OLVL1_SET_MASK; + } + else + { + TIMx->CR1 &= TIM_OLVL1_RESET_MASK; + } + + /* Set the OCAE */ + TIMx->CR1 |= TIM_OC1_ENABLE_MASK; + + /* Set the PWM Bit */ + TIMx->CR1 |= TIM_PWM_MASK; + + /* Set the Duty Cycle value */ + + TIMx->OC1R = TIM_InitStruct->TIM_Pulse_Length_1 ; + + /* Set the Full Period */ + + TIMx->OC2R = TIM_InitStruct->TIM_Full_Period ; + + break; + +/******************************* One pulse mode *******************************/ + + case TIM_OPM: + + /* Set the Level During the pulse */ + if (TIM_InitStruct->TIM_Pulse_Level_1 == TIM_HIGH) + { + TIMx->CR1 |= TIM_OLVL2_SET_MASK; + } + + /* Set the Level after the pulse */ + if (TIM_InitStruct->TIM_Period_Level == TIM_HIGH) + { + TIMx->CR1 |= TIM_OLVL1_SET_MASK; + } + + /* Set the Activation Edge on the ICAP 1 */ + if (TIM_InitStruct->TIM_OPM_INPUT_Edge == TIM_OPM_EDGE_RISING) + { + TIMx->CR1 |= TIM_OPM_EDGE_RISING; + } + + /* Set the Output Compare Function */ + TIMx->CR1 |= TIM_OC1_ENABLE_MASK; + + /* Set the One pulse mode */ + TIMx->CR1 |= TIM_OPM_MASK; + + /* Set the Pulse length */ + TIMx->OC1R = TIM_InitStruct->TIM_Pulse_Length_1; + + break; + +/*************************** Input capture channel 1 **************************/ + + case TIM_ICAP_CHANNEL_1: + + if (TIM_InitStruct->TIM_ICAP1_Edge == TIM_ICAP1_EDGE_RISING) + { + TIMx->CR1 |= TIM_ICAP1_EDGE_RISING; + } + else + { + TIMx->CR1 &= TIM_ICAP1_EDGE_FALLING; + } + + break; + +/*************************** Input capture channel 2 **************************/ + + case TIM_ICAP_CHANNEL_2: + + if (TIM_InitStruct->TIM_ICAP2_Edge == TIM_ICAP2_EDGE_RISING) + { + TIMx->CR1 |= TIM_ICAP2_EDGE_RISING; + } + else + { + TIMx->CR1 &= TIM_ICAP2_EDGE_FALLING; + } + + break; + +/************************* Input capture channel 1 & 2 ************************/ + + case TIM_ICAP_CHANNEL_12: + if (TIM_InitStruct->TIM_ICAP2_Edge == TIM_ICAP2_EDGE_RISING) + { + TIMx->CR1 |= TIM_ICAP2_EDGE_RISING; + } + else + { + TIMx->CR1 &= TIM_ICAP2_EDGE_FALLING; + } + + if (TIM_InitStruct->TIM_ICAP1_Edge == TIM_ICAP1_EDGE_RISING) + { + TIMx->CR1 |= TIM_ICAP1_EDGE_RISING; + } + else + { + TIMx->CR1 &= TIM_ICAP1_EDGE_FALLING; + } + + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : TIM_CounterCmd +* Description : Enables or disables TIMx Counter peripheral. +* Input1 : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Input2 : TIM_operation: specifies the new state of the TIMx Counter. +* This parameter can be one of the following values: +* - TIM_START: Start the timer counter. +* - TIM_STOP : Stop the timer counter. +* - TIM_CLEAR: Clear the timer counter. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_CounterCmd(TIM_TypeDef *TIMx, TIM_CounterOperations TIM_operation) +{ + switch (TIM_operation) + { + case TIM_START: + TIMx->CR1 |= TIM_ENABLE_MASK; + break; + + case TIM_STOP: + TIMx->CR1 &= TIM_DISABLE_MASK; + break; + + case TIM_CLEAR: + TIMx->CNTR = 0x1234; + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : TIM_PrescalerConfig +* Description : This routine is used to configure the TIMx prescaler value +* (when using the APB clock). +* Input1 : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Input2 : TIM_Prescaler: specifies the prescaler value. This parameter +* can be a value from 0x0 to 0xFF. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_PrescalerConfig(TIM_TypeDef *TIMx, u8 TIM_Prescaler) +{ + TIMx->CR2 &= 0xFF00; + TIMx->CR2 |= TIM_Prescaler; + +} +/******************************************************************************* +* Function Name : TIM_GetPrescalerValue +* Description : This routine is used to get the TIMx prescaler value +* (when using the APB clock). +* Input : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Output : None +* Return : The prescaler value. +*******************************************************************************/ +u8 TIM_GetPrescalerValue(TIM_TypeDef *TIMx) +{ + return TIMx->CR2 & 0x00FF; +} + +/******************************************************************************* +* Function Name : TIM_GetCounterValue +* Description : This routine is used to get the TIMx counter value. +* Input : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Output : None +* Return : The counter value. +*******************************************************************************/ +u16 TIM_GetCounterValue(TIM_TypeDef *TIMx) +{ + return TIMx->CNTR; +} + +/******************************************************************************* +* Function Name : TIM_GetICAP1Value +* Description : This routine is used to get the Input Capture 1 value. +* Input : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Output : None +* Return : The Input Capture 1 value. +*******************************************************************************/ +u16 TIM_GetICAP1Value(TIM_TypeDef *TIMx) +{ + return TIMx->IC1R; +} + +/******************************************************************************* +* Function Name : TIM_GetICAP2Value +* Description : This routine is used to get the Input Capture 2 value. +* Input : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Output : None +* Return : The Input Capture 2 value. +*******************************************************************************/ +u16 TIM_GetICAP2Value(TIM_TypeDef *TIMx) +{ + return TIMx->IC2R; +} + +/******************************************************************************* +* Function Name : TIM_SetPulse +* Description : This routine is used to set the pulse value. +* Input1 : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Input2 : TIM_Channel: specifies the needed channel. +* This parameter can be one of the following values: +* - TIM_PWM_OC1_Channel: PWM/Output Compare 1 Channel +* - TIM_OC2_Channel : Output Compare 2 Channel +* Input3 : TIM_Pulse: specifies the new pulse value. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetPulse(TIM_TypeDef *TIMx,u16 TIM_Channel ,u16 TIM_Pulse) +{ + if (TIM_Channel == TIM_PWM_OC1_Channel) + { + TIMx->OC1R = TIM_Pulse; + } + else + { + TIMx->OC2R = TIM_Pulse; + } +} +/******************************************************************************* +* Function Name : TIM_GetFlagStatus +* Description : Checks whether the specified TIMx flag is set or not. +* Input1 : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Input2 : TIM_Flag: specifies the flag to check. +* This parameter can be one of the following values: +* - TIM_FLAG_IC1: Input Capture Channel 1 Flag +* - TIM_FLAG_IC2: Input Capture Channel 2 Flag +* - TIM_FLAG_TO : Timer Overflow Flag +* - TIM_FLAG_OC1: Output Compare Channel 1 Flag +* - TIM_FLAG_OC2: Output Compare Channel 2 Flag +* Output : None +* Return : The NewState of the TIM_Flag (SET or RESET). +*******************************************************************************/ +FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, u16 TIM_Flag) +{ + if((TIMx->SR & TIM_Flag) == RESET) + { + return RESET; + } + else + { + return SET; + } +} + +/******************************************************************************* +* Function Name : TIM_ClearFlag +* Description : Clears the TIM Flag passed as a parameter. +* Input1 : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Input2 : TIM_Flag: specifies the flag to clear. +* This parameter can be one of the following values: +* - TIM_FLAG_IC1: Input Capture Channel 1 Flag +* - TIM_FLAG_IC2: Input Capture Channel 2 Flag +* - TIM_FLAG_TO : Timer Overflow Flag +* - TIM_FLAG_OC1: Output Compare Channel 1 Flag +* - TIM_FLAG_OC2: Output Compare Channel 2 Flag +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ClearFlag(TIM_TypeDef *TIMx, u16 TIM_Flag) +{ + /* Clear TIM_Flag */ + TIMx->SR &= ~TIM_Flag; +} + +/******************************************************************************* +* Function Name : TIM_GetPWMIPulse +* Description : This routine is used to get the Pulse value in PWMI Mode. +* Input : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Output : None +* Return : The pulse value. +*******************************************************************************/ +u16 TIM_GetPWMIPulse(TIM_TypeDef *TIMx) +{ + return TIMx->IC2R; +} + +/******************************************************************************* +* Function Name : TIM_GetPWMIPeriod +* Description : This routine is used to get the Period value in PWMI Mode. +* Input : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Output : None +* Return : The period value. +*******************************************************************************/ +u16 TIM_GetPWMIPeriod(TIM_TypeDef *TIMx) +{ + return TIMx->IC1R; +} + +/******************************************************************************* +* Function Name : TIM_ITConfig +* Description : Configures the Timer interrupt source. +* Input1 : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Input2 : TIM_IT: specifies the TIM interrupt source to be enabled. +* This parameter can be one of the following values: +* - TIM_IT_IC1: Input Capture 1 Interrupt source. +* - TIM_IT_OC1: Output Compare 1 Interrupt source. +* - TIM_IT_TO : Timer Overflow Interrupt source. +* - TIM_IT_IC2: Input Capture 2 Interrupt source. +* - TIM_IT_OC2: Output Compare 2 Interrupt source. +* Input3 : TIM_Newstate: specifies the new state of the TIMx IT. +* This parameter can be one of the following values: +* - ENABLE : Enable the needed interrupt. +* - DISABLE: Disable the needed interrupt. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ITConfig(TIM_TypeDef *TIMx, u16 TIM_IT, FunctionalState TIM_Newstate) +{ + if(TIM_Newstate == ENABLE) + { + TIMx->CR2 = (TIMx->CR2 & 0x00FF) | TIM_IT; + } + else + { + TIMx->CR2 &= ~TIM_IT; + } +} + +/******************************************************************************* +* Function Name : TIM_DMAConfig +* Description : Configures the Timer DMA source. +* Input1 : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Input2 : TIM_DMA_Souces: specifies the TIM DMA source to be selected. +* This parameter can be one of the following values: +* - TIM_DMA_IC1: Input Capture 1 DMA source. +* - TIM_DMA_OCA1 Output Compare 1 DMA source. +* - TIM_DMA_TO: Timer Overflow DMA source. +* - TIM_DMA_IC2: Input Capture 2 DMA source. +* - TIM_DMA_OC2: Output Compare 2 DMA source. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_DMAConfig(TIM_TypeDef *TIMx, u16 TIM_DMA_Sources) +{ + /* Reset the DMAS[1:0] bits */ + TIMx->CR1 &= TIM_DMA_CLEAR_MASK; + /* Set the DMAS[1:0] bits according to TIM_DMA_Sources parameter */ + TIMx->CR1 |= TIM_DMA_Sources; +} + +/******************************************************************************* +* Function Name : TIM_DMACmd +* Description : Enables or disables TIMx DMA peripheral. +* Input1 : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Input2 : TIM_Newstate: new state of the TIMx DMA peripheral +* This parameter can be one of the following values: +* - ENABLE : Enable the TIMx DMA. +* - DISABLE: Disable the TIMx DMA. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_DMACmd(TIM_TypeDef *TIMx, FunctionalState TIM_Newstate) +{ + if (TIM_Newstate == ENABLE) + { + TIMx->CR2 |= TIM_DMA_ENABLE; + } + else + { + TIMx->CR2 &= TIM_DMA_DISABLE; + } +} +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_uart.c b/20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_uart.c new file mode 100644 index 000000000..84ef375a3 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_uart.c @@ -0,0 +1,658 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_uart.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the UART software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_uart.h" +#include "91x_scu.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* UART IrDA Mask */ +#define UART_IrDA_Disable_Mask 0xFFFD /* IrDA Disable Mask */ +#define UART_IrDA_Enable_Mask 0x0002 /* IrDA Enable Mask */ +#define IrDA_LowPower_Enable_Mask 0x0004 /*IrDA lower power mode enable*/ +#define IrDA_LowPower_Disable_Mask 0xFFFB /*IrDA lower power mode enable*/ + +/* UART Mask */ +#define UART_Enable_Mask 0x0001 /* UART Enable Mask */ +#define UART_Disable_Mask 0xFFFE /* UART Disable Mask */ + +/* UART LoopBack */ +#define UART_LoopBack_Disable_Mask 0xFF7F /* LoopBack Disable Mask */ +#define UART_LoopBack_Enable_Mask 0x0080 /* LoopBack Enable Mask */ + +#define UART_WordLength_Mask 0xFF9F /* UART Word Length Mask */ +#define UART_Parity_Mask 0xFF79 /* UART Parity Mask */ +#define UART_HardwareFlowControl_Mask 0x3FFF /* UART Hardware Flow Control Mask */ +#define UART_TxRxFIFOLevel_Mask 0xFFC0 /* UART Tx Rx FIFO Level Mask */ +#define UART_BreakChar_Mask 0x0001 /* UART Break Character send Mask*/ +#define UART_FLAG_Mask 0x1F /* UART Flag Mask */ +#define UART_Mode_Mask 0xFCFF /* UART Mode Mask */ +#define UART_RTS_LowLevel_Mask 0x0800 /* RTS signal is low */ +#define UART_RTS_HighLevel_Mask 0xF7FF /* RTS signal is High */ +#define UART_DTR_LowLevel_Mask 0x0400 /* DTR signal is low */ +#define UART_DTR_HighLevel_Mask 0xFBFF /* DTR signal is High */ +#define UART_ClearFlag_Mask 0xAA /* Clear Flag Mask */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + + /******************************************************************************* +* Function Name : UART_DeInit +* Description : Deinitializes the UARTx peripheral registers +* to their default reset values. +* Input : UARTx: where x can be 0,1 or 2 to select the UART peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void UART_DeInit(UART_TypeDef* UARTx) +{ + /* Reset the UARTx registers values */ + if(UARTx == UART0) + { + SCU_APBPeriphReset(__UART0,ENABLE); + SCU_APBPeriphReset(__UART0,DISABLE); + } + else if(UARTx == UART1) + { + SCU_APBPeriphReset(__UART1,ENABLE); + SCU_APBPeriphReset(__UART1,DISABLE); + } + else if(UARTx == UART2) + { + SCU_APBPeriphReset(__UART2,ENABLE); + SCU_APBPeriphReset(__UART2,DISABLE); + } +} + +/******************************************************************************* +* Function Name : UART_Init +* Description : Initializes the UARTx peripheral according to the specified +* parameters in the UART_InitStruct . +* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral. +* - UART_InitStruct: pointer to a UART_InitTypeDef structure +* that contains the configuration information for the +* specified UART peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef* UART_InitStruct) +{ + + u64 UART_MainClock = 0; + u32 IntegerDivider = 0; + u32 FractionalDivider = 0; + + /* Clear the LCR[6:5] bits */ + UARTx->LCR &= UART_WordLength_Mask; + /* Set the LCR[6:5] bits according to UART_WordLength value */ + UARTx->LCR |= UART_InitStruct->UART_WordLength; + + /* Choose Stop Bits */ + if(UART_InitStruct->UART_StopBits == UART_StopBits_2) + { + /* 2 Stop Bit */ + UARTx->LCR |= UART_StopBits_2; + } + else + { + /* One Stop Bits */ + UARTx->LCR &= UART_StopBits_1; + } + + /* Configure the Parity */ + /* Clear the LCR[7]and LCR[2:1] bits */ + UARTx->LCR &= UART_Parity_Mask; + /* Set the LCR[7]and LCR[2:1] bits according to UART_Parity value */ + UARTx->LCR |= UART_InitStruct->UART_Parity; + + /* Configure the BaudRate */ + UART_MainClock = (SCU_GetMCLKFreqValue())*1000; + if((SCU->CLKCNTR & 0x200) != 0x200) + { + UART_MainClock = UART_MainClock/2; + } + /* Determine the integer part */ + IntegerDivider = ((100) * (UART_MainClock) / (16 * (UART_InitStruct->UART_BaudRate))); + UARTx->IBRD = IntegerDivider / 100; + + /* Determine the fractional part */ + FractionalDivider = IntegerDivider - (100 * (UARTx->IBRD)); + UARTx->FBRD = ((((FractionalDivider * 64) + 50) / 100)); + + /* Choose the Hardware Flow Control */ + /* Clear the CR[15:14] bits */ + UARTx->CR &= UART_HardwareFlowControl_Mask; + /* Set the CR[15:14] bits according to UART_HardwareFlowControl value */ + UARTx->CR |= UART_InitStruct->UART_HardwareFlowControl; + + /* Configure the UART mode */ + /* Clear the CR[9:8] bits */ + UARTx->CR &= UART_Mode_Mask; + /* Set the CR[9:8] bits according to UART_Mode value */ + UARTx->CR |= UART_InitStruct->UART_Mode; + + /* Enable or disable the FIFOs */ + /* Set the FIFOs Levels */ + if(UART_InitStruct->UART_FIFO == UART_FIFO_Enable) + { + /* Enable the FIFOs */ + UARTx->LCR |= UART_FIFO_Enable; + + /* Clear TXIFLSEL and RXIFLSEL bits */ + UARTx->IFLS &= UART_TxRxFIFOLevel_Mask; + + /* Set RXIFLSEL bits according to UART_RxFIFOLevel value */ + UARTx->IFLS |= (UART_InitStruct->UART_RxFIFOLevel << 3); + + /* Set TXIFLSEL bits according to UART_TxFIFOLevel value */ + UARTx->IFLS |= UART_InitStruct->UART_TxFIFOLevel; + } + else + { + /* Disable the FIFOs */ + UARTx->LCR &= UART_FIFO_Disable; + } +} + +/******************************************************************************* +* Function Name : UART_StructInit +* Description : Fills each UART_InitStruct member with its reset value. +* Input : UART_InitStruct: pointer to a UART_InitTypeDef structure which +* will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void UART_StructInit(UART_InitTypeDef* UART_InitStruct) +{ + /* Reset the UART_InitStruct members */ + UART_InitStruct->UART_WordLength = UART_WordLength_8D; + UART_InitStruct->UART_StopBits = UART_StopBits_1; + UART_InitStruct->UART_Parity = UART_Parity_Odd ; + UART_InitStruct->UART_BaudRate = 9600; + UART_InitStruct->UART_HardwareFlowControl = UART_HardwareFlowControl_None; + UART_InitStruct->UART_Mode = UART_Mode_Tx_Rx; + UART_InitStruct->UART_FIFO = UART_FIFO_Enable; + UART_InitStruct->UART_TxFIFOLevel = UART_FIFOLevel_1_2; + UART_InitStruct->UART_RxFIFOLevel = UART_FIFOLevel_1_2; +} + +/******************************************************************************* +* Function Name : UART_Cmd +* Description : Enables or disables the specified UART peripheral. +* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral +* - NewState: new state of the UARTx peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void UART_Cmd(UART_TypeDef* UARTx, FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Enable the selected UART by setting the UARTEN bit in the CR register */ + UARTx->CR |= UART_Enable_Mask; + } + else + { + /* Disable the selected UART by clearing the UARTEN bit in the CR register */ + UARTx->CR &= UART_Disable_Mask; + } +} + +/******************************************************************************* +* Function Name : UART_ITConfig +* Description : Enables or disables the specified UART interrupts. +* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral +* - UART_IT: specifies the UART interrupts sources to be +* enabled or disabled. This parameter can be any combination +* of the following values: +* - UART_IT_OverrunError: Overrun Error interrupt +* - UART_IT_BreakError: Break Error interrupt +* - UART_IT_ParityError: Parity Error interrupt +* - UART_IT_FrameError: Frame Error interrupt +* - UART_IT_ReceiveTimeOut: Receive Time Out interrupt +* - UART_IT_Transmit: Transmit interrupt +* - UART_IT_Receive: Receive interrupt +* - UART_IT_DSR: DSR interrupt +* - UART_IT_DCD: DCD interrupt +* - UART_IT_CTS: CTS interrupt +* - UART_IT_RI: RI interrupt +* - NewState: new state of the UARTx peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void UART_ITConfig(UART_TypeDef* UARTx, u16 UART_IT, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enables the selected interrupts */ + UARTx->IMSC |= UART_IT; + } + else + { + /* Disables the selected interrupts */ + UARTx->IMSC &= ~UART_IT; + } +} + +/******************************************************************************* +* Function Name : UART_DMAConfig +* Description : Configures the UARTx’s DMA interface. +* Input : - UARTx: where x can be 1 or 2 to select the UART peripheral +* - UART_DMAOnError: specifies the DMA on error request. +* This parameter can be: +* - UART_DMAOnError_Enable: DMA receive request enabled +* when the UART error interrupt is asserted. +* - UART_DMAOnError_Disable: DMA receive request disabled +* when the UART error interrupt is asserted. +* Output : None +* Return : None +*******************************************************************************/ +void UART_DMAConfig(UART_TypeDef* UARTx, u16 UART_DMAOnError) +{ + if(UART_DMAOnError == UART_DMAOnError_Enable) + { + UARTx->DMACR &= UART_DMAOnError_Enable; + } + else + { + UARTx->DMACR |= UART_DMAOnError_Disable; + } +} + +/******************************************************************************* +* Function Name : UART_DMACmd +* Description : Enables or disables the UARTx’s DMA interface. +* Input : - UARTx: where x can be 1 or 2 to select the UART peripheral +* - UART_DMAReq: enables or disables the request of DMA from UART. +* This parameter can be: +* - UART_DMAReq_Tx: Transmit DMA Enable +* - UART_DMAReq_Rx: Receive DMA Enable +* - NewState: new state of the UARTx peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void UART_DMACmd(UART_TypeDef* UARTx, u8 UART_DMAReq, FunctionalState NewState) +{ + if(UART_DMAReq == UART_DMAReq_Tx) + { + if(NewState == ENABLE) + { + UARTx->DMACR |= UART_DMAReq_Tx; + } + else + { + UARTx->DMACR &= ~UART_DMAReq_Tx; + } + } + + if(UART_DMAReq == UART_DMAReq_Rx) + { + if(NewState == ENABLE) + { + UARTx->DMACR |= UART_DMAReq_Rx; + } + else + { + UARTx->DMACR &= ~UART_DMAReq_Rx; + } + } +} + +/******************************************************************************* +* Function Name : UART_LoopBackConfig +* Description : Enables or disables the LoopBack mode. +* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral +* - NewState: new state of the UARTx peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void UART_LoopBackConfig(UART_TypeDef* UARTx, FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Enable the LoopBack mode of the specified UART */ + UARTx->CR |= UART_LoopBack_Enable_Mask; + } + else + { + /* Disable the LoopBack mode of the specified UART */ + UARTx->CR &= UART_LoopBack_Disable_Mask; + } +} + +/******************************************************************************* +* Function Name : UART_GetFlagStatus +* Description : Checks whether the specified UART flag is set or not. +* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral +* - UART_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - UART_FLAG_OverrunError: Overrun error flag +* - UART_FLAG_Break: break error flag +* - UART_FLAG_ParityError: parity error flag +* - UART_FLAG_FrameError: frame error flag +* - UART_FLAG_RI: RI flag +* - UART_FLAG_TxFIFOEmpty: Transmit FIFO Empty flag +* - UART_FLAG_RxFIFOFull: Receive FIFO Full flag +* - UART_FLAG_TxFIFOFull: Transmit FIFO Full flag +* - UART_FLAG_RxFIFOEmpty: Receive FIFO Empty flag +* - UART_FLAG_Busy: UART Busy flag +* - UART_FLAG_CTS: CTS flag +* - UART_FLAG_DCD: DCD flag +* - UART_FLAG_DSR: DSR flag +* - UART_RawIT_OverrunError: Overrun Error interrupt flag +* - UART_RawIT_BreakError: Break Error interrupt flag +* - UART_RawIT_ParityError: Parity Error interrupt flag +* - UART_RawIT_FrameError: Frame Error interrupt flag +* - UART_RawIT_ReceiveTimeOut: ReceiveTimeOut interrupt flag +* - UART_RawIT_Transmit: Transmit interrupt flag +* - UART_RawIT_Receive: Receive interrupt flag +* - UART_RawIT_DSR: DSR interrupt flag +* - UART_RawIT_DCD: DCD interrupt flag +* - UART_RawIT_CTS: CTS interrupt flag +* - UART_RawIT_RI: RI interrupt flag +* Output : None +* Return : The new state of UART_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, u16 UART_FLAG) +{ + + u32 UARTReg = 0, FlagPos = 0; + u32 StatusReg = 0; + + /* Get the UART register index */ + UARTReg = UART_FLAG >> 5; + + /* Get the flag position */ + FlagPos = UART_FLAG & UART_FLAG_Mask; + + if(UARTReg == 1) /* The flag to check is in RSR register */ + { + StatusReg = UARTx->RSECR; + } + else if (UARTReg == 2) /* The flag to check is in FR register */ + { + StatusReg = UARTx->FR; + } + else if(UARTReg == 3) /* The flag to check is in RIS register */ + { + StatusReg = UARTx->RIS; + } + + if((StatusReg & (1 << FlagPos))!= RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : UART_ClearFlag +* Description : Clears the UARTx’s flags(Frame, Parity, Break, Overrun error). +* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void UART_ClearFlag(UART_TypeDef* UARTx) +{ + /* Clear the flag */ + UARTx->RSECR = UART_ClearFlag_Mask; +} + +/******************************************************************************* +* Function Name : UART_GetITStatus +* Description : Checks whether the specified UART interrupt has occured or not. +* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral. +* - UART_IT: specifies the interrupt pending bit to be checked. +* This parameter can be one of the following values: +* - UART_IT_OverrunError: Overrun Error interrupt +* - UART_IT_BreakError: Break Error interrupt +* - UART_IT_ParityError: Parity Error interrupt +* - UART_IT_FrameError: Frame Error interrupt +* - UART_IT_ReceiveTimeOut: Receive Time Out interrupt +* - UART_IT_Transmit: Transmit interrupt +* - UART_IT_Receive: Receive interrupt +* - UART_IT_DSR: DSR interrupt +* - UART_IT_DCD: DCD interrupt +* - UART_IT_CTS: CTS interrupt +* - UART_IT_RI: RI interrupt +* Output : None +* Return : The new state of UART_IT (SET or RESET). +*******************************************************************************/ +ITStatus UART_GetITStatus(UART_TypeDef* UARTx, u16 UART_IT) +{ + if((UARTx->MIS & UART_IT) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : UART_ClearITPendingBit +* Description : Clears the UARTx’s interrupt pending bits. +* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral. +* - UART_IT: specifies the interrupt pending bit to clear. +* More than one interrupt can be cleared using the “|” operator. +* This parameter can be: +* - UART_IT_OverrunError: Overrun Error interrupt +* - UART_IT_BreakError: Break Error interrupt +* - UART_IT_ParityError: Parity Error interrupt +* - UART_IT_FrameError: Frame Error interrupt +* - UART_IT_ReceiveTimeOut: Receive Time Out interrupt +* - UART_IT_Transmit: Transmit interrupt +* - UART_IT_Receive: Receive interrupt +* - UART_IT_DSR: DSR interrupt +* - UART_IT_DCD: DCD interrupt +* - UART_IT_CTS: CTS interrupt +* - UART_IT_RI: RI interrupt +* Output : None +* Return : None +*******************************************************************************/ +void UART_ClearITPendingBit(UART_TypeDef* UARTx, u16 UART_IT) +{ + /* Clear the specified interrupt */ + UARTx->ICR &= UART_IT; +} + +/******************************************************************************* +* Function Name : UART_IrDALowPowerConfig +* Description : Sets the IrDA low power mode +* Input : - IrDAx: where x can be 0,1 or 2 to select the UART/IrDA peripheral. +* - NewState: new state of the UARTIrDA peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void UART_IrDALowPowerConfig(u8 IrDAx, FunctionalState NewState) +{ + UART_TypeDef* UARTx; + + switch(IrDAx) + { + case IrDA0: UARTx = UART0; + break; + case IrDA1: UARTx = UART1; + break; + case IrDA2: UARTx = UART2; + break; + } + + if (NewState == ENABLE) + { + UARTx->CR |= IrDA_LowPower_Enable_Mask; + } + else + { + UARTx->CR &= IrDA_LowPower_Disable_Mask; + } +} + +/******************************************************************************* +* Function Name : UART_IrDASetCounter +* Description : Sets the IrDA counter divisor value. +* Input : - UARTx: where x can be 0,1 or 2 to select the UART/IrDA peripheral. +* - IrDA_Counter: IrDA counter divisor new value n low power mode(Hz). +* Output : None +* Return : None +*******************************************************************************/ +void UART_IrDASetCounter(u8 IrDAx, u32 IrDA_Counter) +{ + UART_TypeDef* UARTx; + u32 APBClock; + switch(IrDAx) + { + case IrDA0: UARTx = UART0; + break; + case IrDA1: UARTx = UART1; + break; + case IrDA2: UARTx = UART2; + break; + } + /* Get the APB frequency */ + APBClock = (SCU_GetPCLKFreqValue())*1000; + /* Determine the Counter Divisor part */ + UARTx->ILPR = (((APBClock*10) / ( IrDA_Counter)) + 5 )/10; + } + +/******************************************************************************* +* Function Name : UART_IrDACmd +* Description : Enables or disables the UARTx’s IrDA interface. +* Input : - IrDAx: where x can be 0,1 or 2 to select the UART/IrDA peripheral +* - NewState: new state of the UARTx peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void UART_IrDACmd(u8 IrDAx, FunctionalState NewState) +{ + UART_TypeDef* UARTx; + + switch(IrDAx) + { + case IrDA0: UARTx = UART0; + break; + case IrDA1: UARTx = UART1; + break; + case IrDA2: UARTx = UART2; + break; + } + if(NewState == ENABLE) + { + /* Enable the IrDA mode of the specified UART */ + UARTx->CR |= UART_IrDA_Enable_Mask; + } + else + { + /* Disable the IrDA mode of the specified UART */ + UARTx->CR &= UART_IrDA_Disable_Mask; + } +} + +/******************************************************************************* +* Function Name : UART_SendData +* Description : Transmits signle Byte of data through the UARTx peripheral. +* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral. +* - Data: the byte to transmit +* Output : None +* Return : None +*******************************************************************************/ +void UART_SendData(UART_TypeDef* UARTx, u8 Data) +{ + /* Transmit one byte */ + UARTx->DR = Data; +} + +/******************************************************************************* +* Function Name : UART_ReceiveData +* Description : Returns the most recent received Byte by the UARTx peripheral. +* Input : UARTx: where x can be 0,1 or 2 to select the UART peripheral. +* Output : None +* Return : The received data +*******************************************************************************/ +u8 UART_ReceiveData(UART_TypeDef* UARTx) +{ + /* Receive one byte */ + return ((u8)UARTx->DR); +} + +/******************************************************************************* +* Function Name : UART_SendBreak +* Description : Transmits break characters. +* Input : UARTx: where x can be 0,1 or 2 to select the UART peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void UART_SendBreak(UART_TypeDef* UARTx) +{ + /* Send break characters */ + UARTx->LCR |= UART_BreakChar_Mask; +} + +/******************************************************************************* +* Function Name : UART_RTSConfig +* Description : Sets or Resets the RTS signal +* Input : - LevelState: new state of the RTS signal for UART0 only. +* This parameter can be: LowLevel or HighLevel +* Output : None +* Return : None +*******************************************************************************/ +void UART_RTSConfig(UART_LevelTypeDef LevelState) +{ + if(LevelState == LowLevel) + { + UART0->CR |= UART_RTS_LowLevel_Mask; + } + else + { + UART0->CR &= UART_RTS_HighLevel_Mask; + } +} + +/******************************************************************************* +* Function Name : UART_DTRConfig +* Description : Sets or Resets the DTR signal for UART0 only +* Input : - LevelState: new state of the DTR signal. +* This parameter can be: LowLevel or HighLevel +* Output : None +* Return : None +*******************************************************************************/ +void UART_DTRConfig(UART_LevelTypeDef LevelState) +{ + if(LevelState == LowLevel) + { + UART0->CR |= UART_DTR_LowLevel_Mask; + } + else + { + UART0->CR &= UART_DTR_HighLevel_Mask; + } +} +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_vic.c b/20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_vic.c new file mode 100644 index 000000000..fc202e920 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_vic.c @@ -0,0 +1,830 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_vic.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the VIC software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + + +/* Standard include ----------------------------------------------------------*/ +#include "91x_vic.h" + +/* Include of other module interface headers ---------------------------------*/ +/* Local includes ------------------------------------------------------------*/ +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +#define VIC_REGISTER_NUMBER 16 +#define VIC_PROTECTION_ENABLE_MASK 0x1 +#define VIC_PROTECTION_DISABLE_MASK 0xFFFFFFFE +#define VIC_VECTOR_ENABLE_MASK 0x20 +#define VIC_IT_SOURCE_MASK 0xFFFFFFE0 +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +static void VIC_ITModeConfig(u16 VIC_Source, VIC_ITLineMode VIC_LineMode); +static void VIC_ISRVectAddConfig(u16 VIC_Source, u16 VIC_Priority, \ + void (*VIC_VectAddress)(void)); +static void VIC_VectEnableConfig(u16 VIC_Source, u16 VIC_Priority); +static void VIC_ITSourceConfig(u16 VIC_Source, u16 VIC_Priority); + +/* Interface functions -------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : VIC_DeInit +* Description : Deinitialize the VIC module registers to their default reset +* values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void VIC_DeInit(void) +{ + SCU_AHBPeriphReset(__VIC, ENABLE); /* VIC peripheral is under Reset */ + SCU_AHBPeriphReset(__VIC, DISABLE); /* VIC peripheral Reset off */ +} + +/******************************************************************************* +* Function Name : VIC_GetIRQStatus +* Description : Get the status of interrupts after IRQ masking. +* Input : VIC_Source: specifies the number of the source line. +* This parameter can be one of the following values: +* - WDG_ITLine : VIC source 0 +* - SW_ITLine : VIC source 1 +* - ARMRX_ITLine : VIC source 2 +* - ARMTX_ITLine : VIC source 3 +* - TIM0_ITLine : VIC source 4 +* - TIM1_ITLine : VIC source 5 +* - TIM2_ITLine : VIC source 6 +* - TIM3_ITLine : VIC source 7 +* - USBHP_ITLine : VIC source 8 +* - USBLP_ITLine : VIC source 9 +* - SCU_ITLine : VIC source 10 +* - ENET_ITLine : VIC source 11 +* - DMA_ITLine : VIC source 12 +* - CAN_ITLine : VIC source 13 +* - MC_ITLine : VIC source 14 +* - ADC_ITLine : VIC source 15 +* - UART0_ITLine : VIC source 16 +* - UART1_ITLine : VIC source 17 +* - UART2_ITLine : VIC source 18 +* - I2C0_ITLine : VIC source 19 +* - I2C1_ITLine : VIC source 20 +* - SSP0_ITLine : VIC source 21 +* - SSP1_ITLine : VIC source 22 +* - LVD_ITLine : VIC source 23 +* - RTC_ITLine : VIC source 24 +* - WIU_ITLine : VIC source 25 +* - EXTIT0_ITLine: VIC source 26 +* - EXTIT1_ITLine: VIC source 27 +* - EXTIT2_ITLine: VIC source 28 +* - EXTIT3_ITLine: VIC source 29 +* - USBWU_ITLine : VIC source 30 +* - PFQBC_ITLine : VIC source 31 +* Output : None +* Return : The status of the IRQ interrupt after masking (SET or RESET). +*******************************************************************************/ +FlagStatus VIC_GetIRQStatus(u16 VIC_Source) +{ + u32 VIC_Mask = 1; + if (VIC_Source < VIC_REGISTER_NUMBER) + { + if ((VIC0->ISR | VIC_Mask << VIC_Source) != RESET) + return SET; + else + return RESET; + } + else + { + if ((VIC1->ISR | VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)) != RESET) + return SET; + else + return RESET; + } +} + +/******************************************************************************* +* Function Name : VIC_GetFIQStatus +* Description : Get the status of interrupts after FIQ masking +* Input : VIC_Source: specifies the number of the source line. +* This parameter can be one of the following values: +* - WDG_ITLine : VIC source 0 +* - SW_ITLine : VIC source 1 +* - ARMRX_ITLine : VIC source 2 +* - ARMTX_ITLine : VIC source 3 +* - TIM0_ITLine : VIC source 4 +* - TIM1_ITLine : VIC source 5 +* - TIM2_ITLine : VIC source 6 +* - TIM3_ITLine : VIC source 7 +* - USBHP_ITLine : VIC source 8 +* - USBLP_ITLine : VIC source 9 +* - SCU_ITLine : VIC source 10 +* - ENET_ITLine : VIC source 11 +* - DMA_ITLine : VIC source 12 +* - CAN_ITLine : VIC source 13 +* - MC_ITLine : VIC source 14 +* - ADC_ITLine : VIC source 15 +* - UART0_ITLine : VIC source 16 +* - UART1_ITLine : VIC source 17 +* - UART2_ITLine : VIC source 18 +* - I2C0_ITLine : VIC source 19 +* - I2C1_ITLine : VIC source 20 +* - SSP0_ITLine : VIC source 21 +* - SSP1_ITLine : VIC source 22 +* - LVD_ITLine : VIC source 23 +* - RTC_ITLine : VIC source 24 +* - WIU_ITLine : VIC source 25 +* - EXTIT0_ITLine: VIC source 26 +* - EXTIT1_ITLine: VIC source 27 +* - EXTIT2_ITLine: VIC source 28 +* - EXTIT3_ITLine: VIC source 29 +* - USBWU_ITLine : VIC source 30 +* - PFQBC_ITLine : VIC source 31 +* Output : None +* Return : The status of the FIQ interrupt after masking (SET or RESET) +*******************************************************************************/ +FlagStatus VIC_GetFIQStatus(u16 VIC_Source) +{ + u32 VIC_Mask = 1; + if (VIC_Source < VIC_REGISTER_NUMBER) + { + if ((VIC0->RINTSR | VIC_Mask << VIC_Source) != RESET) + return SET; + else + return RESET; + } + else + { + if ((VIC1->RINTSR | VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)) != RESET) + return SET; + else + return RESET; + } +} + +/******************************************************************************* +* Function Name : VIC_GetSourceITStatus +* Description : Get the status of the source interrupts before masking. +* Input : VIC_Source: specifies the number of the source line. +* This parameter can be one of the following values: +* - WDG_ITLine : VIC source 0 +* - SW_ITLine : VIC source 1 +* - ARMRX_ITLine : VIC source 2 +* - ARMTX_ITLine : VIC source 3 +* - TIM0_ITLine : VIC source 4 +* - TIM1_ITLine : VIC source 5 +* - TIM2_ITLine : VIC source 6 +* - TIM3_ITLine : VIC source 7 +* - USBHP_ITLine : VIC source 8 +* - USBLP_ITLine : VIC source 9 +* - SCU_ITLine : VIC source 10 +* - ENET_ITLine : VIC source 11 +* - DMA_ITLine : VIC source 12 +* - CAN_ITLine : VIC source 13 +* - MC_ITLine : VIC source 14 +* - ADC_ITLine : VIC source 15 +* - UART0_ITLine : VIC source 16 +* - UART1_ITLine : VIC source 17 +* - UART2_ITLine : VIC source 18 +* - I2C0_ITLine : VIC source 19 +* - I2C1_ITLine : VIC source 20 +* - SSP0_ITLine : VIC source 21 +* - SSP1_ITLine : VIC source 22 +* - LVD_ITLine : VIC source 23 +* - RTC_ITLine : VIC source 24 +* - WIU_ITLine : VIC source 25 +* - EXTIT0_ITLine: VIC source 26 +* - EXTIT1_ITLine: VIC source 27 +* - EXTIT2_ITLine: VIC source 28 +* - EXTIT3_ITLine: VIC source 29 +* - USBWU_ITLine : VIC source 30 +* - PFQBC_ITLine : VIC source 31 +* Output : None +* Return : The status of the source interrupt before masking +*******************************************************************************/ +FlagStatus VIC_GetSourceITStatus(u16 VIC_Source) +{ + u32 VIC_Mask = 1; + if (VIC_Source < VIC_REGISTER_NUMBER) + { + if ((VIC0->FSR | VIC_Mask << VIC_Source) != RESET) + return SET; + else + return RESET; + } + else + { + if ((VIC1->FSR | VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)) != RESET) + return SET; + else + return RESET; + } +} + +/******************************************************************************* +* Function Name : VIC_ITModeConfig +* Description : Select the type of interrupt (IRQ or FIQ) +* Input1 : VIC_Source: specifies the number of the source line. +* This parameter can be one of the following values: +* - WDG_ITLine : VIC source 0 +* - SW_ITLine : VIC source 1 +* - ARMRX_ITLine : VIC source 2 +* - ARMTX_ITLine : VIC source 3 +* - TIM0_ITLine : VIC source 4 +* - TIM1_ITLine : VIC source 5 +* - TIM2_ITLine : VIC source 6 +* - TIM3_ITLine : VIC source 7 +* - USBHP_ITLine : VIC source 8 +* - USBLP_ITLine : VIC source 9 +* - SCU_ITLine : VIC source 10 +* - ENET_ITLine : VIC source 11 +* - DMA_ITLine : VIC source 12 +* - CAN_ITLine : VIC source 13 +* - MC_ITLine : VIC source 14 +* - ADC_ITLine : VIC source 15 +* - UART0_ITLine : VIC source 16 +* - UART1_ITLine : VIC source 17 +* - UART2_ITLine : VIC source 18 +* - I2C0_ITLine : VIC source 19 +* - I2C1_ITLine : VIC source 20 +* - SSP0_ITLine : VIC source 21 +* - SSP1_ITLine : VIC source 22 +* - LVD_ITLine : VIC source 23 +* - RTC_ITLine : VIC source 24 +* - WIU_ITLine : VIC source 25 +* - EXTIT0_ITLine: VIC source 26 +* - EXTIT1_ITLine: VIC source 27 +* - EXTIT2_ITLine: VIC source 28 +* - EXTIT3_ITLine: VIC source 29 +* - USBWU_ITLine : VIC source 30 +* - PFQBC_ITLine : VIC source 31 +* Input2 : VIC_LineMode :specifies the type of interrupt of the source +* line. This parameter can be one of the following values: +* - VIC_IRQ: the correspondent line is configured as IRQ. +* - VIC_FIQ: the correspondent line is configured as FIQ. +* Output : None +* Return : None +*******************************************************************************/ +static void VIC_ITModeConfig(u16 VIC_Source, VIC_ITLineMode VIC_LineMode) +{ + u32 VIC_Mask = 1; + + if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */ + { + if (VIC_LineMode == VIC_IRQ) + VIC0->INTSR &= ~(VIC_Mask << VIC_Source); + else /* VIC_LineMode == VIC_FIQ */ + VIC0->INTSR |= (VIC_Mask << VIC_Source); + } + else /* VIC1 */ + { + if (VIC_LineMode == VIC_IRQ) + VIC1->INTSR &= ~(VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)); + else /* VIC_LineMode == VIC_FIQ */ + VIC1->INTSR |= (VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)); + } +} + +/******************************************************************************* +* Function Name : VIC_ITCmd +* Description : Enable or disable the interrupt request lines. +* Input1 : VIC_Source: specifies the number of the source line. +* This parameter can be one of the following values: +* - WDG_ITLine : VIC source 0 +* - SW_ITLine : VIC source 1 +* - ARMRX_ITLine : VIC source 2 +* - ARMTX_ITLine : VIC source 3 +* - TIM0_ITLine : VIC source 4 +* - TIM1_ITLine : VIC source 5 +* - TIM2_ITLine : VIC source 6 +* - TIM3_ITLine : VIC source 7 +* - USBHP_ITLine : VIC source 8 +* - USBLP_ITLine : VIC source 9 +* - SCU_ITLine : VIC source 10 +* - ENET_ITLine : VIC source 11 +* - DMA_ITLine : VIC source 12 +* - CAN_ITLine : VIC source 13 +* - MC_ITLine : VIC source 14 +* - ADC_ITLine : VIC source 15 +* - UART0_ITLine : VIC source 16 +* - UART1_ITLine : VIC source 17 +* - UART2_ITLine : VIC source 18 +* - I2C0_ITLine : VIC source 19 +* - I2C1_ITLine : VIC source 20 +* - SSP0_ITLine : VIC source 21 +* - SSP1_ITLine : VIC source 22 +* - LVD_ITLine : VIC source 23 +* - RTC_ITLine : VIC source 24 +* - WIU_ITLine : VIC source 25 +* - EXTIT0_ITLine: VIC source 26 +* - EXTIT1_ITLine: VIC source 27 +* - EXTIT2_ITLine: VIC source 28 +* - EXTIT3_ITLine: VIC source 29 +* - USBWU_ITLine : VIC source 30 +* - PFQBC_ITLine : VIC source 31 +* Input2 : FMI_NewState: specifies the line status. +* This parameter can be one of the following values: +* - ENABLE: The line is enabled. +* - DISABLE: The line is disabled. +* Output : None +* Return : None +*******************************************************************************/ +void VIC_ITCmd(u16 VIC_Source, FunctionalState VIC_NewState) +{ + u32 VIC_Mask = 1; + + if (VIC_NewState == ENABLE) + { + if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */ + VIC0->INTER |= (VIC_Mask << VIC_Source); + else /* VIC1 */ + VIC1->INTER |= (VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)); + } + else /* VIC_NewState == DISABLE */ + { + if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */ + VIC0->INTECR |= (VIC_Mask << VIC_Source); + else /* VIC1 */ + VIC1->INTECR |= (VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)); + } +} + +/******************************************************************************* +* Function Name : VIC_SWITCmd +* Description : Generate a software interrupt for the specific source +* interrupt. +* Input1 : VIC_Source: specifies the number of the source line. +* This parameter can be one of the following values: +* - WDG_ITLine : VIC source 0 +* - SW_ITLine : VIC source 1 +* - ARMRX_ITLine : VIC source 2 +* - ARMTX_ITLine : VIC source 3 +* - TIM0_ITLine : VIC source 4 +* - TIM1_ITLine : VIC source 5 +* - TIM2_ITLine : VIC source 6 +* - TIM3_ITLine : VIC source 7 +* - USBHP_ITLine : VIC source 8 +* - USBLP_ITLine : VIC source 9 +* - SCU_ITLine : VIC source 10 +* - ENET_ITLine : VIC source 11 +* - DMA_ITLine : VIC source 12 +* - CAN_ITLine : VIC source 13 +* - MC_ITLine : VIC source 14 +* - ADC_ITLine : VIC source 15 +* - UART0_ITLine : VIC source 16 +* - UART1_ITLine : VIC source 17 +* - UART2_ITLine : VIC source 18 +* - I2C0_ITLine : VIC source 19 +* - I2C1_ITLine : VIC source 20 +* - SSP0_ITLine : VIC source 21 +* - SSP1_ITLine : VIC source 22 +* - LVD_ITLine : VIC source 23 +* - RTC_ITLine : VIC source 24 +* - WIU_ITLine : VIC source 25 +* - EXTIT0_ITLine: VIC source 26 +* - EXTIT1_ITLine: VIC source 27 +* - EXTIT2_ITLine: VIC source 28 +* - EXTIT3_ITLine: VIC source 29 +* - USBWU_ITLine : VIC source 30 +* - PFQBC_ITLine : VIC source 31 +* Input2 : FMI_NewState: specifies the software interrupt status. +* This parameter can be one of the following values: +* - ENABLE: The software interrupt is enabled. +* - DISABLE: The software interrupt is disabled. +* Output : None +* Return : None +*******************************************************************************/ +void VIC_SWITCmd(u16 VIC_Source, FunctionalState VIC_NewState) +{ + u32 VIC_Mask = 1; + + if (VIC_NewState == ENABLE) + { + if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */ + VIC0->SWINTR |= (VIC_Mask << VIC_Source); + else /* VIC1 */ + VIC1->SWINTR |= (VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)); + } + else /* VIC_NewState == DISABLE */ + { + if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */ + VIC0->SWINTCR = (VIC_Mask << VIC_Source); + else /* VIC1 */ + VIC1->SWINTCR = (VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)); + } +} + +/******************************************************************************* +* Function Name : VIC_ProtectionCmd +* Description : Enable or Disable the register access protection. +* Input : FMI_NewState: specifies the protection status. +* This parameter can be one of the following values: +* - ENABLE: The protection is enabled. +* - DISABLE: The protection is disabled. +* Output : None +* Return : None +*******************************************************************************/ +void VIC_ProtectionCmd(FunctionalState VIC_NewState) +{ + if (VIC_NewState == ENABLE) + { + VIC0->PER |= VIC_PROTECTION_ENABLE_MASK; + VIC1->PER |= VIC_PROTECTION_ENABLE_MASK; + } + else + { + VIC0->PER &= VIC_PROTECTION_DISABLE_MASK; + VIC1->PER &= VIC_PROTECTION_DISABLE_MASK; + } +} + +/******************************************************************************* +* Function Name : VIC_GetCurrentISRAdd +* Description : Get the address of the current active ISR. +* Input : VICx: specifies the VIC peripheral +* This parameter can be one of the following values: +* - VIC0: To select VIC0. +* - VIC1: To select VIC1. +* Output : None +* Return : The Address of the active ISR. +*******************************************************************************/ +u32 VIC_GetCurrentISRAdd(VIC_TypeDef* VICx) +{ + return VICx->VAR; +} + +/******************************************************************************* +* Function Name : VIC_ISRVectAddConfig +* Description : Configuration of the ISR vector address. +* Input1 : VIC_Source: specifies the number of the source line. +* This parameter can be one of the following values: +* - WDG_ITLine : VIC source 0 +* - SW_ITLine : VIC source 1 +* - ARMRX_ITLine : VIC source 2 +* - ARMTX_ITLine : VIC source 3 +* - TIM0_ITLine : VIC source 4 +* - TIM1_ITLine : VIC source 5 +* - TIM2_ITLine : VIC source 6 +* - TIM3_ITLine : VIC source 7 +* - USBHP_ITLine : VIC source 8 +* - USBLP_ITLine : VIC source 9 +* - SCU_ITLine : VIC source 10 +* - ENET_ITLine : VIC source 11 +* - DMA_ITLine : VIC source 12 +* - CAN_ITLine : VIC source 13 +* - MC_ITLine : VIC source 14 +* - ADC_ITLine : VIC source 15 +* - UART0_ITLine : VIC source 16 +* - UART1_ITLine : VIC source 17 +* - UART2_ITLine : VIC source 18 +* - I2C0_ITLine : VIC source 19 +* - I2C1_ITLine : VIC source 20 +* - SSP0_ITLine : VIC source 21 +* - SSP1_ITLine : VIC source 22 +* - LVD_ITLine : VIC source 23 +* - RTC_ITLine : VIC source 24 +* - WIU_ITLine : VIC source 25 +* - EXTIT0_ITLine: VIC source 26 +* - EXTIT1_ITLine: VIC source 27 +* - EXTIT2_ITLine: VIC source 28 +* - EXTIT3_ITLine: VIC source 29 +* - USBWU_ITLine : VIC source 30 +* - PFQBC_ITLine : VIC source 31 +* Input2 : VIC_Priority: specifies the priority of the interrupt. +* It can be a value from 0 to 15. 0 is the highest priority. +* Input3 : void (*VIC_VectAddress)(void): specifies the ISR vector +* address pointer. +* Output : None +* Return : None +*******************************************************************************/ +static void VIC_ISRVectAddConfig(u16 VIC_Source, u16 VIC_Priority, \ + void (*VIC_VectAddress)(void)) +{ + if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */ + VIC0->VAiR[VIC_Priority] = (u32)VIC_VectAddress; + else /* VIC1 */ + VIC1->VAiR[VIC_Priority] = (u32)VIC_VectAddress; +} + +/******************************************************************************* +* Function Name : VIC_GetISRVectAdd +* Description : Get the ISR vector address of the correspondent line. +* Input : VIC_Source: specifies the number of the source line. +* This parameter can be one of the following values: +* - WDG_ITLine : VIC source 0 +* - SW_ITLine : VIC source 1 +* - ARMRX_ITLine : VIC source 2 +* - ARMTX_ITLine : VIC source 3 +* - TIM0_ITLine : VIC source 4 +* - TIM1_ITLine : VIC source 5 +* - TIM2_ITLine : VIC source 6 +* - TIM3_ITLine : VIC source 7 +* - USBHP_ITLine : VIC source 8 +* - USBLP_ITLine : VIC source 9 +* - SCU_ITLine : VIC source 10 +* - ENET_ITLine : VIC source 11 +* - DMA_ITLine : VIC source 12 +* - CAN_ITLine : VIC source 13 +* - MC_ITLine : VIC source 14 +* - ADC_ITLine : VIC source 15 +* - UART0_ITLine : VIC source 16 +* - UART1_ITLine : VIC source 17 +* - UART2_ITLine : VIC source 18 +* - I2C0_ITLine : VIC source 19 +* - I2C1_ITLine : VIC source 20 +* - SSP0_ITLine : VIC source 21 +* - SSP1_ITLine : VIC source 22 +* - LVD_ITLine : VIC source 23 +* - RTC_ITLine : VIC source 24 +* - WIU_ITLine : VIC source 25 +* - EXTIT0_ITLine: VIC source 26 +* - EXTIT1_ITLine: VIC source 27 +* - EXTIT2_ITLine: VIC source 28 +* - EXTIT3_ITLine: VIC source 29 +* - USBWU_ITLine : VIC source 30 +* - PFQBC_ITLine : VIC source 31 +* Output : None +* Return : The correspondent ISR vector address. +*******************************************************************************/ +u32 VIC_GetISRVectAdd(u16 VIC_Source) +{ + if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */ + return VIC0->VAiR[VIC_Source]; + else /* VIC1 */ + return VIC1->VAiR[VIC_Source - VIC_REGISTER_NUMBER]; +} + +/******************************************************************************* +* Function Name : VIC_VectEnableConfig +* Description : Enable the vector interrupt. +* Input1 : VIC_Source: specifies the number of the source line. +* This parameter can be one of the following values: +* - WDG_ITLine : VIC source 0 +* - SW_ITLine : VIC source 1 +* - ARMRX_ITLine : VIC source 2 +* - ARMTX_ITLine : VIC source 3 +* - TIM0_ITLine : VIC source 4 +* - TIM1_ITLine : VIC source 5 +* - TIM2_ITLine : VIC source 6 +* - TIM3_ITLine : VIC source 7 +* - USBHP_ITLine : VIC source 8 +* - USBLP_ITLine : VIC source 9 +* - SCU_ITLine : VIC source 10 +* - ENET_ITLine : VIC source 11 +* - DMA_ITLine : VIC source 12 +* - CAN_ITLine : VIC source 13 +* - MC_ITLine : VIC source 14 +* - ADC_ITLine : VIC source 15 +* - UART0_ITLine : VIC source 16 +* - UART1_ITLine : VIC source 17 +* - UART2_ITLine : VIC source 18 +* - I2C0_ITLine : VIC source 19 +* - I2C1_ITLine : VIC source 20 +* - SSP0_ITLine : VIC source 21 +* - SSP1_ITLine : VIC source 22 +* - LVD_ITLine : VIC source 23 +* - RTC_ITLine : VIC source 24 +* - WIU_ITLine : VIC source 25 +* - EXTIT0_ITLine: VIC source 26 +* - EXTIT1_ITLine: VIC source 27 +* - EXTIT2_ITLine: VIC source 28 +* - EXTIT3_ITLine: VIC source 29 +* - USBWU_ITLine : VIC source 30 +* - PFQBC_ITLine : VIC source 31 +* Input2 : VIC_Priority: specifies the priority of the interrupt. +* It can be a value from 0 to 15. 0 is the highest priority. +* Output : None +* Return : None +*******************************************************************************/ +static void VIC_VectEnableConfig(u16 VIC_Source, u16 VIC_Priority) +{ + if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */ + VIC0->VCiR[VIC_Priority] |= VIC_VECTOR_ENABLE_MASK; + else /* VIC1 */ + VIC1->VCiR[VIC_Priority] |= VIC_VECTOR_ENABLE_MASK; +} + +/******************************************************************************* +* Function Name : VIC_ITSourceConfig +* Description : Select the interrupt source. +* Input1 : VIC_Source: specifies the number of the source line. +* This parameter can be one of the following values: +* - WDG_ITLine : VIC source 0 +* - SW_ITLine : VIC source 1 +* - ARMRX_ITLine : VIC source 2 +* - ARMTX_ITLine : VIC source 3 +* - TIM0_ITLine : VIC source 4 +* - TIM1_ITLine : VIC source 5 +* - TIM2_ITLine : VIC source 6 +* - TIM3_ITLine : VIC source 7 +* - USBHP_ITLine : VIC source 8 +* - USBLP_ITLine : VIC source 9 +* - SCU_ITLine : VIC source 10 +* - ENET_ITLine : VIC source 11 +* - DMA_ITLine : VIC source 12 +* - CAN_ITLine : VIC source 13 +* - MC_ITLine : VIC source 14 +* - ADC_ITLine : VIC source 15 +* - UART0_ITLine : VIC source 16 +* - UART1_ITLine : VIC source 17 +* - UART2_ITLine : VIC source 18 +* - I2C0_ITLine : VIC source 19 +* - I2C1_ITLine : VIC source 20 +* - SSP0_ITLine : VIC source 21 +* - SSP1_ITLine : VIC source 22 +* - LVD_ITLine : VIC source 23 +* - RTC_ITLine : VIC source 24 +* - WIU_ITLine : VIC source 25 +* - EXTIT0_ITLine: VIC source 26 +* - EXTIT1_ITLine: VIC source 27 +* - EXTIT2_ITLine: VIC source 28 +* - EXTIT3_ITLine: VIC source 29 +* - USBWU_ITLine : VIC source 30 +* - PFQBC_ITLine : VIC source 31 +* Input2 : VIC_Priority: specifies the priority of the interrupt. +* It can be a value from 0 to 15. 0 is the highest priority. +* Output : None +* Return : None +*******************************************************************************/ +static void VIC_ITSourceConfig(u16 VIC_Source, u16 VIC_Priority) +{ + if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */ + { + VIC0->VCiR[VIC_Priority] &= VIC_IT_SOURCE_MASK; + VIC0->VCiR[VIC_Priority] |= VIC_Source; + } + else /* VIC1 */ + { + VIC1->VCiR[VIC_Priority] &= VIC_IT_SOURCE_MASK; + VIC1->VCiR[VIC_Priority] |= VIC_Source - VIC_REGISTER_NUMBER; + } +} + +/******************************************************************************* +* Function Name : VIC_Config +* Description : Configure the ISR, the line, the mode and the priority for +* each interrupt source line. +* Input1 : VIC_Source: specifies the number of the source line. +* This parameter can be one of the following values: +* - WDG_ITLine : VIC source 0 +* - SW_ITLine : VIC source 1 +* - ARMRX_ITLine : VIC source 2 +* - ARMTX_ITLine : VIC source 3 +* - TIM0_ITLine : VIC source 4 +* - TIM1_ITLine : VIC source 5 +* - TIM2_ITLine : VIC source 6 +* - TIM3_ITLine : VIC source 7 +* - USBHP_ITLine : VIC source 8 +* - USBLP_ITLine : VIC source 9 +* - SCU_ITLine : VIC source 10 +* - ENET_ITLine : VIC source 11 +* - DMA_ITLine : VIC source 12 +* - CAN_ITLine : VIC source 13 +* - MC_ITLine : VIC source 14 +* - ADC_ITLine : VIC source 15 +* - UART0_ITLine : VIC source 16 +* - UART1_ITLine : VIC source 17 +* - UART2_ITLine : VIC source 18 +* - I2C0_ITLine : VIC source 19 +* - I2C1_ITLine : VIC source 20 +* - SSP0_ITLine : VIC source 21 +* - SSP1_ITLine : VIC source 22 +* - LVD_ITLine : VIC source 23 +* - RTC_ITLine : VIC source 24 +* - WIU_ITLine : VIC source 25 +* - EXTIT0_ITLine: VIC source 26 +* - EXTIT1_ITLine: VIC source 27 +* - EXTIT2_ITLine: VIC source 28 +* - EXTIT3_ITLine: VIC source 29 +* - USBWU_ITLine : VIC source 30 +* - PFQBC_ITLine : VIC source 31 +* Input2 : VIC_LineMode :specifies the type of interrupt of the source +* line. This parameter can be one of the following values: +* - VIC_IRQ: the correspondent line is configured as IRQ. +* - VIC_FIQ: the correspondent line is configured as FIQ. +* Input3 : VIC_Priority: specifies the priority of the interrupt. +* It can be a value from 0 to 15. 0 is the highest priority. +* Output : None +* Return : None +*******************************************************************************/ +void VIC_Config(u16 VIC_Source, VIC_ITLineMode VIC_LineMode, u8 VIC_Priority) +{ + switch (VIC_Source) + { + case 0: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, WDG_IRQHandler); + break; + + case 1: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, SW_IRQHandler); + break; + + case 2: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, ARMRX_IRQHandler); + break; + + case 3: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, ARMTX_IRQHandler); + break; + + case 4: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, TIM0_IRQHandler); + break; + + case 5: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, TIM1_IRQHandler); + break; + + case 6: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, TIM2_IRQHandler); + break; + + case 7: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, TIM3_IRQHandler); + break; + + case 8: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, USBHP_IRQHandler); + break; + + case 9: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, USBLP_IRQHandler); + break; + + case 10: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, SCU_IRQHandler); + break; + + case 11: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, ENET_IRQHandler); + break; + + case 12: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, DMA_IRQHandler); + break; + + case 13: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, CAN_IRQHandler); + break; + + case 14: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, MC_IRQHandler); + break; + + case 15: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, ADC_IRQHandler); + break; + + case 16: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, UART0_IRQHandler); + break; + + case 17: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, UART1_IRQHandler); + break; + + case 18: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, UART2_IRQHandler); + break; + + case 19: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, I2C0_IRQHandler); + break; + + case 20: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, I2C1_IRQHandler); + break; + + case 21: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, SSP0_IRQHandler); + break; + + case 22: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, SSP1_IRQHandler); + break; + + case 23: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, LVD_IRQHandler); + break; + + case 24: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, RTC_IRQHandler); + break; + + case 25: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, WIU_IRQHandler); + break; + + case 26: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, EXTIT0_IRQHandler); + break; + + case 27: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, EXTIT1_IRQHandler); + break; + + case 28: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, EXTIT2_IRQHandler); + break; + + case 29: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, EXTIT3_IRQHandler); + break; + + case 30: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, USBWU_IRQHandler); + break; + + case 31: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, PFQBC_IRQHandler); + break; + + default: break; + } + VIC_ITModeConfig(VIC_Source, VIC_LineMode); + VIC_VectEnableConfig(VIC_Source, VIC_Priority); + VIC_ITSourceConfig(VIC_Source, VIC_Priority); +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_wdg.c b/20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_wdg.c new file mode 100644 index 000000000..f933635d0 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/Library/source/91x_wdg.c @@ -0,0 +1,277 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_wdg.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the WDG software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_wdg.h" +#include "91x_scu.h" +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + + +/* WDG End of Count interrupt Flag */ +#define WDG_FLAG_EC 0x0001 + + +/* WDG End of Count interrupt request */ +#define WDG_IT_EC 0x0001 + + + +/* WDG Start/Stop counter */ +#define WDG_Counter_Start 0x0002 +#define WDG_Counter_Stop 0xFFFD + + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Registers reset value */ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/****************************************************************************** +* Function Name : WDG_DeInit +* Description : Deinitializes the WDG peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void WDG_DeInit(void) +{ + + SCU_APBPeriphReset(__WDG, ENABLE); /*WDG peripheral under Reset */ + SCU_APBPeriphReset(__WDG, DISABLE); /*WDG peripheral Reset off*/ + +} + +/******************************************************************************* +* Function Name : WDG_StructInit +* Description : Fills the WDG_InitTypeDef structure member with its reset +* value. +* Input : WDG_InitStruct : pointer to a WDG_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void WDG_StructInit(WDG_InitTypeDef *WDG_InitStruct) +{ + /* Select the Watchdog running mode*/ + WDG_InitStruct->WDG_Mode = WDG_Mode_Timer; + + /* Select the source clock */ + WDG_InitStruct-> WDG_ClockSource = WDG_ClockSource_Apb; + + /* Initialize Prescaler */ + WDG_InitStruct->WDG_Prescaler =0xFF; + + /* Initialize Preload */ + WDG_InitStruct->WDG_Preload =0xFFFF; + + +} + +/******************************************************************************* +* Function Name : WDG_Init +* Description : Initializes WDG peripheral according to the specified +* parameters in the WDG_InitStruct. +* Input : WDG_InitStruct: pointer to a WDG_InitTypeDef structure that +* contains the configuration information for the WDG peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void WDG_Init(WDG_InitTypeDef* WDG_InitStruct) +{ + + + if(WDG_InitStruct->WDG_ClockSource == WDG_ClockSource_Apb) + { + /* Select The APB clock as clock source */ + WDG->CR &= WDG_ClockSource_Apb; + } + + else + { + /* Select the RTC clock as source */ + WDG->CR |= WDG_ClockSource_Rtc ; + } + + + /* Configure WDG Prescaler register value */ + WDG->PR = WDG_InitStruct->WDG_Prescaler; + + /* Configure WDG Pre-load register value */ + WDG->VR = WDG_InitStruct->WDG_Preload ; + + + if(WDG_InitStruct->WDG_Mode == WDG_Mode_Timer) + { + /* Select Timer mode */ + WDG->CR &= WDG_Mode_Timer; + } + else + { + /* Select WDG mode */ + WDG->CR |= WDG_Mode_Wdg ; + } + + +} + +/******************************************************************************* +* Function Name : WDG_Cmd +* Description : Enables or disables the WDG peripheral. +* Input : NewState: new state of the WDG peripheral (Newstate can be +* ENABLE or DISABLE) +* Output : None +* Return : None +*******************************************************************************/ +void WDG_Cmd(FunctionalState NewState ) +{ + if((WDG->CR & WDG_Mode_Wdg) == 0) + { + /* Timer mode */ + if(NewState == ENABLE) + { + /* Start timer by setting SC bit in Control register */ + WDG->CR |= WDG_Counter_Start; + } + else + { + /* Stop timer by clearning SC bit in Control register */ + WDG->CR &= WDG_Counter_Stop; + } + } + else + { + /* Watchdog mode */ + if(NewState == ENABLE) + { + WDG->KR = WDG_KeyValue1; + WDG->KR = WDG_KeyValue2; + } + } +} + +/******************************************************************************* +* Function Name : WDG_ITConfig +* Description : Enables or disables the WDG End of Count(EC) interrupt. +* Input : Newstate: new state of the End of Count(EC) WDG interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void WDG_ITConfig(FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable the End of Count interrupt */ + WDG->MR |= WDG_IT_EC; + } + else + { + /* Disable the End of Count interrupt */ + WDG->MR &= ~WDG_IT_EC; + } +} + +/******************************************************************************* +* Function Name : WDG_GetCounter +* Description : Gets the WDG’s current counter value. +* Input : None +* Output : None +* Return : The WDG current counter value +*******************************************************************************/ +u16 WDG_GetCounter(void) +{ + return WDG->CNT; +} + + + + +/******************************************************************************* +* Function Name : WDG_GetITStatus +* Description : Checks whether the WDG End of Count(EC) interrupt is occured or not. +* Input : None +* Output : None +* Return : The new state of WDG_IT (SET or RESET). +*******************************************************************************/ +ITStatus WDG_GetITStatus(void) +{ + if(((WDG->SR & WDG_IT_EC) != RESET )&&((WDG->MR & WDG_IT_EC) != RESET )) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : WDG_ClearITPendingBit +* Description : Clears the WDG's End of Count(EC) interrupt pending bit. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void WDG_ClearITPendingBit(void) +{ + /* Clear the EC pending bit */ + WDG->SR &= ~WDG_IT_EC; + +} + +/******************************************************************************* +* Function Name : WDG_ClearFlag +* Description : Clears the WDG's End of Count(EC) Flag. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void WDG_ClearFlag(void) +{ + /* Clear the EC Flag */ + + WDG->SR &= ~WDG_FLAG_EC; + +} + + +/******************************************************************************* +* Function Name : WDG_GetFlagStatus +* Description : Checks whether the WDG End of Count(EC) flag is set or not. +* Input : None +* Output : None +* Return : The new state of the WDG_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus WDG_GetFlagStatus(void) +{ + if((WDG->SR & WDG_FLAG_EC) != RESET ) + { + return SET; + } + else + { + return RESET; + } +} + + + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/ARM9_STR91X_IAR/ParTest/ParTest.c b/20080212/Demo/ARM9_STR91X_IAR/ParTest/ParTest.c new file mode 100644 index 000000000..fd30d041a --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/ParTest/ParTest.c @@ -0,0 +1,118 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* Library includes. */ +#include "91x_lib.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* Demo application includes. */ +#include "partest.h" + +#define partstMAX_LEDs 4 +#define partstLED_PORT *( ( unsigned portSHORT * ) 0x5800f3fc ) + +/*-----------------------------------------------------------*/ + +static GPIO_InitTypeDef GPIO9_InitStruct; + +void vParTestInitialise( void ) +{ + /* Configure the bits used to flash LED's on port 9 as output. */ + GPIO_StructInit( &GPIO9_InitStruct ); + GPIO9_InitStruct.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3; + GPIO9_InitStruct.GPIO_Direction = GPIO_PinOutput; + GPIO_Init( GPIO9, &GPIO9_InitStruct ); +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ +unsigned portSHORT usLED = 0x0001; + + if( uxLED < partstMAX_LEDs ) + { + usLED <<= uxLED; + + portENTER_CRITICAL(); + { + if( xValue ) + { + partstLED_PORT &= ~usLED; + } + else + { + partstLED_PORT |= usLED; + } + } + portEXIT_CRITICAL(); + } +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned portSHORT usLED = 0x0001; + + if( uxLED < partstMAX_LEDs ) + { + usLED <<= uxLED; + + portENTER_CRITICAL(); + { + if( partstLED_PORT & usLED ) + { + partstLED_PORT &= ~usLED; + } + else + { + partstLED_PORT |= usLED; + } + } + portEXIT_CRITICAL(); + } +} + + + + diff --git a/20080212/Demo/ARM9_STR91X_IAR/RTOSDemo.ewd b/20080212/Demo/ARM9_STR91X_IAR/RTOSDemo.ewd new file mode 100644 index 000000000..e00a0c08a --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/RTOSDemo.ewd @@ -0,0 +1,2443 @@ + + + + 1 + + THUMB + + ARM + + 1 + + C-SPY + 2 + + 15 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IARROM_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + JLINK_ID + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 1 + 1 + 1 + + + + + + + + MACRAIGOR_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin + 1 + + + + + ARM - uIP - D + + ARM + + 1 + + C-SPY + 2 + + 15 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + ANGEL_ID + 2 + + 0 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new file mode 100644 index 000000000..496c3bc13 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/RTOSDemo.ewp @@ -0,0 +1,4166 @@ + + + + 1 + + THUMB + + ARM + + 1 + + General + 3 + + 14 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 19 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 7 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 5 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + ARM - uIP - D + + ARM + + 1 + + General + 3 + + 14 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 19 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ $PROJ_DIR$\..\Common\Minimal\GenQTest.c + + + $PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c + + + $PROJ_DIR$\..\Common\Minimal\integer.c + + + $PROJ_DIR$\STCode\lcd.c + + + $PROJ_DIR$\main.c + + + $PROJ_DIR$\ParTest\ParTest.c + + + $PROJ_DIR$\..\Common\Minimal\PollQ.c + + + $PROJ_DIR$\..\Common\Minimal\QPeek.c + + + $PROJ_DIR$\..\Common\Minimal\semtest.c + + + $PROJ_DIR$\serial\serial.c + + + $PROJ_DIR$\webserver\uIP_Task.c + + ARM - lwIP - D + + + + + Library Source + + $PROJ_DIR$\Library\include\91x_conf.h + + + $PROJ_DIR$\Library\source\91x_enet.c + + THUMB + + ICCARM + + 19 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARM - uIP - D + + ICCARM + + 19 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARM - lwIP - D + + ICCARM + + 19 + 0 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARM - uIP - R + + ICCARM + + 19 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$PROJ_DIR$\..\Common\ethernet\lwIP\core\mem.c + + + $PROJ_DIR$\..\Common\ethernet\lwIP\core\memp.c + + + $PROJ_DIR$\..\Common\ethernet\lwIP\core\netif.c + + + $PROJ_DIR$\..\Common\ethernet\lwIP\core\pbuf.c + + + $PROJ_DIR$\..\Common\ethernet\lwIP\core\raw.c + + + $PROJ_DIR$\..\Common\ethernet\lwIP\core\stats.c + + + $PROJ_DIR$\..\Common\ethernet\lwIP\core\sys.c + + + $PROJ_DIR$\..\Common\ethernet\lwIP\core\tcp.c + + + $PROJ_DIR$\..\Common\ethernet\lwIP\core\tcp_in.c + + + $PROJ_DIR$\..\Common\ethernet\lwIP\core\tcp_out.c + + + $PROJ_DIR$\..\Common\ethernet\lwIP\core\udp.c + + + + ipv4 + + $PROJ_DIR$\..\Common\ethernet\lwIP\core\ipv4\icmp.c + + + $PROJ_DIR$\..\Common\ethernet\lwIP\core\ipv4\ip.c + + + $PROJ_DIR$\..\Common\ethernet\lwIP\core\ipv4\ip_addr.c + + + $PROJ_DIR$\..\Common\ethernet\lwIP\core\ipv4\ip_frag.c + + + + netif + + $PROJ_DIR$\..\Common\ethernet\lwIP\netif\etharp.c + + + $PROJ_DIR$\lwip\netif\ethernetif.c + + + + snmp + + $PROJ_DIR$\..\Common\ethernet\lwIP\core\snmp\asn1_dec.c + + + $PROJ_DIR$\..\Common\ethernet\lwIP\core\snmp\asn1_enc.c + + + $PROJ_DIR$\..\Common\ethernet\lwIP\core\snmp\mib2.c + + + $PROJ_DIR$\..\Common\ethernet\lwIP\core\snmp\mib_structs.c + + + $PROJ_DIR$\..\Common\ethernet\lwIP\core\snmp\msg_in.c + + + $PROJ_DIR$\..\Common\ethernet\lwIP\core\snmp\msg_out.c + + + + WebServer + + $PROJ_DIR$\lwip\lwipWebServer\BasicWEB.c + + + $PROJ_DIR$\lwip\lwipWebServer\fs.c + + + $PROJ_DIR$\lwip\lwipWebServer\httpd.c + + + + + RTOS Source + + $PROJ_DIR$\FreeRTOSConfig.h + + + $PROJ_DIR$\..\..\Source\list.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\STR91x\port.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\STR91x\portasm.s79 + + + $PROJ_DIR$\..\..\Source\queue.c + + + $PROJ_DIR$\..\..\Source\tasks.c + + + + System Files + + $PROJ_DIR$\91x_init.s + + + $PROJ_DIR$\91x_vect.s + + + + uIP + + ARM - lwIP - D + + + $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\apps\webserver\http-strings.c + + + $PROJ_DIR$\webserver\httpd-cgi.c + + + $PROJ_DIR$\webserver\httpd-fs.c + + + $PROJ_DIR$\webserver\httpd.c + + + $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\psock.c + + + $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\timer.c + + + $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\uip.c + + + $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\uip_arp.c + + + + + diff --git a/20080212/Demo/ARM9_STR91X_IAR/RTOSDemo.eww b/20080212/Demo/ARM9_STR91X_IAR/RTOSDemo.eww new file mode 100644 index 000000000..239a9381e --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/RTOSDemo.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\RTOSDemo.ewp + + + + + diff --git a/20080212/Demo/ARM9_STR91X_IAR/STCode/lcd.c b/20080212/Demo/ARM9_STR91X_IAR/STCode/lcd.c new file mode 100644 index 000000000..f2f77736f --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/STCode/lcd.c @@ -0,0 +1,1409 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : lcd.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file includes the LCD driver for GXM12232-2SL liquid +* Crystal Display Module of STR75x-EVAL. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_lib.h" +#include "lcd.h" +#include "FreeRTOS.h" +#include "task.h" + +/* Private typedef -----------------------------------------------------------*/ +static GPIO_InitTypeDef GPIO_InitStructure; + +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + /* Global variable to set the written text color: used for LCD_Printf */ + TextColorMode_TypeDef TextMode=BlackText; + + /* ASCII Table: each character is 7 column (7dots large) on two pages (16dots high) */ + /* 7 column character: Two 8bit data to display one column*/ + u8 AsciiDotsTable[1778] = { + /* ASCII 0 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 1 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 2 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 3 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 4 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 5 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 6 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 7 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 8 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 9 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + /* ASCII 10 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + /* ASCII 11 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 12 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 13 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + /* ASCII 14 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 15 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 16 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 17 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 18 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 19 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 20 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 21 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 22 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 23 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 24 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 25 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 26 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 27 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, + /* ASCII 28 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + /* ASCII 29 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + /* ASCII 30 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + /* ASCII 31 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + /* ASCII 32 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + /* ASCII 33 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x13,0xe0,0x00,0x00,0x00,0x00,0x00,0x00, + /* ASCII 34 */ 0x00,0x00,0x00,0xe0,0x00,0x20,0x00,0x00,0x00,0xe0,0x00,0x20,0x00,0x00, + /* ASCII 35 */ 0x00,0x00,0x35,0x00,0x0f,0x80,0x35,0x60,0x0f,0x80,0x05,0x60,0x00,0x00, + /* ASCII 36 */ 0x00,0x00,0x0d,0x80,0x0a,0x40,0x3a,0x60,0x06,0x40,0x00,0x00,0x00,0x00, + /* ASCII 37 */ 0x00,0x00,0x02,0x40,0x02,0xa0,0x0a,0x40,0x15,0x00,0x09,0x00,0x00,0x00, + /* ASCII 38 */ 0x00,0x00,0x0c,0x00,0x13,0x00,0x14,0x80,0x08,0x80,0x14,0x00,0x00,0x00, + /* ASCII 39 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xe0,0x00,0x00,0x00,0x00,0x00,0x00, + /* ASCII 40 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x1f,0x80,0x60,0x60,0x00,0x00,0x00,0x00, + /* ASCII 41 */ 0x00,0x00,0x00,0x00,0x60,0x60,0x1f,0x80,0x00,0x00,0x00,0x00,0x00,0x00, + /* ASCII 42 */ 0x00,0x00,0x00,0x40,0x03,0x40,0x00,0xe0,0x03,0x40,0x00,0x40,0x00,0x00, + /* ASCII 43 */ 0x02,0x00,0x02,0x00,0x02,0x00,0x1f,0xc0,0x02,0x00,0x02,0x00,0x02,0x00, + /* ASCII 44 */ 0x00,0x00,0x00,0x00,0x60,0x00,0x38,0x00,0x08,0x00,0x00,0x00,0x00,0x00, + /* ASCII 45 */ 0x00,0x00,0x02,0x00,0x02,0x00,0x02,0x00,0x02,0x00,0x02,0x00,0x00,0x00, + /* ASCII 46 */ 0x00,0x00,0x00,0x00,0x18,0x00,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + /* ASCII 47 */ 0x00,0x00,0x20,0x00,0x18,0x00,0x06,0x00,0x01,0x80,0x00,0x60,0x00,0x00, + /* ASCII 48 */ 0x00,0x00,0x0f,0xc0,0x10,0x20,0x10,0x20,0x10,0x20,0x0f,0xc0,0x00,0x00, + /* ASCII 49 */ 0x00,0x00,0x10,0x00,0x10,0x20,0x1f,0xe0,0x10,0x00,0x10,0x00,0x00,0x00, + /* ASCII 50 */ 0x00,0x00,0x18,0x40,0x14,0x20,0x12,0x20,0x11,0x20,0x18,0xc0,0x00,0x00, + /* ASCII 51 */ 0x00,0x00,0x08,0x40,0x10,0x20,0x11,0x20,0x11,0x20,0x0e,0xc0,0x00,0x00, + /* ASCII 52 */ 0x00,0x00,0x06,0x00,0x05,0x00,0x04,0xc0,0x14,0x20,0x1f,0xe0,0x14,0x00, + /* ASCII 53 */ 0x00,0x00,0x08,0x00,0x11,0xe0,0x11,0x20,0x11,0x20,0x0e,0x20,0x00,0x00, + /* ASCII 54 */ 0x00,0x00,0x0f,0x80,0x11,0x40,0x11,0x20,0x11,0x20,0x0e,0x20,0x00,0x00, + /* ASCII 55 */ 0x00,0x00,0x00,0x60,0x00,0x20,0x18,0x20,0x07,0x20,0x00,0xe0,0x00,0x00, + /* ASCII 56 */ 0x00,0x00,0x0e,0xc0,0x11,0x20,0x11,0x20,0x11,0x20,0x0e,0xc0,0x00,0x00, + /* ASCII 57 */ 0x00,0x00,0x11,0xc0,0x12,0x20,0x12,0x20,0x0a,0x20,0x07,0xc0,0x00,0x00, + /* ASCII 58 */ 0x00,0x00,0x00,0x00,0x19,0x80,0x19,0x80,0x00,0x00,0x00,0x00,0x00,0x00, + /* ASCII 59 */ 0x00,0x00,0x00,0x00,0x30,0x00,0x19,0x80,0x09,0x80,0x00,0x00,0x00,0x00, + /* ASCII 60 */ 0x02,0x00,0x05,0x00,0x05,0x00,0x08,0x80,0x10,0x40,0x10,0x40,0x00,0x00, + /* ASCII 61 */ 0x00,0x00,0x05,0x00,0x05,0x00,0x05,0x00,0x05,0x00,0x05,0x00,0x00,0x00, + /* ASCII 62 */ 0x10,0x40,0x10,0x40,0x08,0x80,0x05,0x00,0x05,0x00,0x02,0x00,0x00,0x00, + /* ASCII 63 */ 0x00,0x00,0x00,0x00,0x10,0x80,0x14,0x40,0x02,0x40,0x01,0x80,0x00,0x00, + /* ASCII 64 */ 0x00,0x00,0x1f,0xe0,0x20,0x10,0x23,0x10,0x24,0x90,0x17,0xe0,0x00,0x00, + /* ASCII 65 */ 0x10,0x00,0x1c,0x00,0x17,0xa0,0x04,0x60,0x17,0x80,0x1c,0x00,0x10,0x00, + /* ASCII 66 */ 0x10,0x20,0x1f,0xe0,0x11,0x20,0x11,0x20,0x11,0x20,0x0e,0xc0,0x00,0x00, + /* ASCII 67 */ 0x00,0x00,0x0f,0xc0,0x10,0x20,0x10,0x20,0x10,0x20,0x08,0x60,0x00,0x00, + /* ASCII 68 */ 0x10,0x20,0x1f,0xe0,0x10,0x20,0x10,0x20,0x08,0x40,0x07,0x80,0x00,0x00, + /* ASCII 69 */ 0x10,0x20,0x1f,0xe0,0x11,0x20,0x13,0xa0,0x10,0x20,0x18,0x60,0x00,0x00, + /* ASCII 70 */ 0x00,0x00,0x10,0x20,0x1f,0xe0,0x11,0x20,0x03,0xa0,0x00,0x20,0x00,0x60, + /* ASCII 71 */ 0x00,0x00,0x0f,0xc0,0x10,0x20,0x10,0x20,0x12,0x20,0x0e,0x60,0x02,0x00, + /* ASCII 72 */ 0x10,0x20,0x1f,0xe0,0x11,0x20,0x01,0x00,0x11,0x20,0x1f,0xe0,0x10,0x20, + /* ASCII 73 */ 0x00,0x00,0x10,0x20,0x10,0x20,0x1f,0xe0,0x10,0x20,0x10,0x20,0x00,0x00, + /* ASCII 74 */ 0x00,0x00,0x0e,0x00,0x10,0x20,0x10,0x20,0x0f,0xe0,0x00,0x20,0x00,0x00, + /* ASCII 75 */ 0x10,0x20,0x1f,0xe0,0x12,0x20,0x03,0x00,0x04,0xa0,0x18,0x60,0x10,0x20, + /* ASCII 76 */ 0x00,0x00,0x10,0x20,0x1f,0xe0,0x10,0x20,0x10,0x00,0x1c,0x00,0x00,0x00, + /* ASCII 77 */ 0x10,0x20,0x1f,0xe0,0x10,0xe0,0x03,0x00,0x10,0xe0,0x1f,0xe0,0x10,0x20, + /* ASCII 78 */ 0x10,0x20,0x1f,0xe0,0x10,0xe0,0x07,0x00,0x18,0x20,0x1f,0xe0,0x00,0x20, + /* ASCII 79 */ 0x00,0x00,0x0f,0xc0,0x10,0x20,0x10,0x20,0x10,0x20,0x0f,0xc0,0x00,0x00, + /* ASCII 80 */ 0x00,0x00,0x10,0x20,0x1f,0xe0,0x12,0x20,0x02,0x20,0x01,0xc0,0x00,0x00, + /* ASCII 81 */ 0x00,0x00,0x0f,0xc0,0x10,0x20,0x30,0x20,0x30,0x20,0x2f,0xc0,0x00,0x00, + /* ASCII 82 */ 0x10,0x20,0x1f,0xe0,0x12,0x20,0x02,0x20,0x06,0x20,0x09,0xc0,0x10,0x00, + /* ASCII 83 */ 0x00,0x00,0x18,0xc0,0x09,0x20,0x11,0x20,0x11,0x40,0x0e,0x60,0x00,0x00, + /* ASCII 84 */ 0x00,0x60,0x00,0x20,0x10,0x20,0x1f,0xe0,0x10,0x20,0x00,0x20,0x00,0x60, + /* ASCII 85 */ 0x00,0x20,0x0f,0xe0,0x10,0x20,0x10,0x00,0x10,0x20,0x0f,0xe0,0x00,0x20, + /* ASCII 86 */ 0x00,0x20,0x00,0xe0,0x07,0x20,0x18,0x00,0x07,0x20,0x00,0xe0,0x00,0x20, + /* ASCII 87 */ 0x00,0x20,0x0f,0xe0,0x10,0x20,0x0f,0x00,0x10,0x20,0x0f,0xe0,0x00,0x20, + /* ASCII 88 */ 0x10,0x20,0x18,0x60,0x04,0x80,0x03,0x00,0x04,0x80,0x18,0x60,0x10,0x20, + /* ASCII 89 */ 0x00,0x20,0x00,0x60,0x11,0xa0,0x1e,0x00,0x11,0xa0,0x00,0x60,0x00,0x20, + /* ASCII 90 */ 0x00,0x00,0x18,0x60,0x14,0x20,0x13,0x20,0x10,0xa0,0x18,0x60,0x00,0x00, + /* ASCII 91 */ 0x00,0x00,0x00,0x00,0x7f,0xe0,0x40,0x20,0x40,0x20,0x00,0x00,0x00,0x00, + /* ASCII 92 */ 0x00,0x00,0x00,0x20,0x01,0xc0,0x06,0x00,0x38,0x00,0x00,0x00,0x00,0x00, + /* ASCII 93 */ 0x00,0x00,0x00,0x00,0x40,0x20,0x40,0x20,0x7f,0xe0,0x00,0x00,0x00,0x00, + /* ASCII 94 */ 0x00,0x00,0x01,0x00,0x00,0x80,0x00,0x60,0x00,0x80,0x01,0x00,0x00,0x00, + /* ASCII 95 */ 0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00, + /* ASCII 96 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x40,0x00,0x00,0x00,0x00, + /* ASCII 97 */ 0x00,0x00,0x0d,0x00,0x12,0x80,0x12,0x80,0x12,0x80,0x1f,0x00,0x10,0x00, + /* ASCII 98 */ 0x10,0x20,0x1f,0xe0,0x11,0x00,0x10,0x80,0x10,0x80,0x0f,0x00,0x00,0x00, + /* ASCII 99 */ 0x00,0x00,0x0f,0x00,0x10,0x80,0x10,0x80,0x10,0x80,0x09,0x80,0x00,0x00, + /* ASCII 100 */ 0x00,0x00,0x0f,0x00,0x10,0x80,0x10,0x80,0x11,0x20,0x1f,0xe0,0x10,0x00, + /* ASCII 101 */ 0x00,0x00,0x0f,0x00,0x12,0x80,0x12,0x80,0x12,0x80,0x13,0x00,0x00,0x00, + /* ASCII 102 */ 0x00,0x00,0x10,0x80,0x1f,0xc0,0x10,0xa0,0x10,0xa0,0x10,0xa0,0x00,0x00, + /* ASCII 103 */ 0x00,0x00,0x0f,0x00,0x50,0x80,0x50,0x80,0x51,0x00,0x3f,0x80,0x00,0x80, + /* ASCII 104 */ 0x10,0x20,0x1f,0xe0,0x11,0x00,0x00,0x80,0x10,0x80,0x1f,0x00,0x10,0x00, + /* ASCII 105 */ 0x00,0x00,0x10,0x80,0x10,0x80,0x1f,0xa0,0x10,0x00,0x10,0x00,0x00,0x00, + /* ASCII 106 */ 0x00,0x00,0x40,0x80,0x40,0x80,0x40,0xa0,0x3f,0x80,0x00,0x00,0x00,0x00, + /* ASCII 107 */ 0x10,0x20,0x1f,0xe0,0x02,0x00,0x16,0x80,0x19,0x80,0x10,0x80,0x00,0x00, + /* ASCII 108 */ 0x00,0x00,0x10,0x00,0x10,0x20,0x1f,0xe0,0x10,0x00,0x10,0x00,0x00,0x00, + /* ASCII 109 */ 0x10,0x80,0x1f,0x80,0x10,0x80,0x1f,0x00,0x10,0x80,0x1f,0x00,0x10,0x00, + /* ASCII 110 */ 0x10,0x80,0x1f,0x80,0x11,0x00,0x00,0x80,0x10,0x80,0x1f,0x00,0x10,0x00, + /* ASCII 111 */ 0x00,0x00,0x0f,0x00,0x10,0x80,0x10,0x80,0x10,0x80,0x0f,0x00,0x00,0x00, + /* ASCII 112 */ 0x40,0x80,0x7f,0x80,0x51,0x00,0x10,0x80,0x10,0x80,0x0f,0x00,0x00,0x00, + /* ASCII 113 */ 0x00,0x00,0x0f,0x00,0x10,0x80,0x10,0x80,0x51,0x00,0x7f,0x80,0x40,0x80, + /* ASCII 114 */ 0x00,0x00,0x10,0x80,0x1f,0x80,0x11,0x00,0x10,0x80,0x10,0x80,0x00,0x00, + /* ASCII 115 */ 0x00,0x00,0x19,0x00,0x12,0x80,0x12,0x80,0x12,0x80,0x0d,0x80,0x00,0x00, + /* ASCII 116 */ 0x00,0x00,0x00,0x80,0x0f,0xc0,0x10,0x80,0x10,0x80,0x10,0x80,0x08,0x00, + /* ASCII 117 */ 0x00,0x80,0x0f,0x80,0x10,0x00,0x10,0x00,0x08,0x80,0x1f,0x80,0x10,0x00, + /* ASCII 118 */ 0x00,0x80,0x03,0x80,0x0c,0x80,0x10,0x00,0x0c,0x80,0x03,0x80,0x00,0x80, + /* ASCII 119 */ 0x00,0x80,0x0f,0x80,0x10,0x80,0x0e,0x00,0x10,0x80,0x0f,0x80,0x00,0x80, + /* ASCII 120 */ 0x10,0x80,0x19,0x80,0x06,0x00,0x06,0x00,0x19,0x80,0x10,0x80,0x00,0x00, + /* ASCII 121 */ 0x00,0x80,0x41,0x80,0x46,0x80,0x78,0x00,0x4c,0x80,0x03,0x80,0x00,0x80, + /* ASCII 122 */ 0x00,0x00,0x19,0x80,0x14,0x80,0x12,0x80,0x11,0x80,0x18,0x80,0x00,0x00, + /* ASCII 123 */ 0x00,0x00,0x00,0x00,0x04,0x00,0x3b,0xc0,0x40,0x20,0x00,0x00,0x00,0x00, + /* ASCII 124 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x3f,0xe0,0x00,0x00,0x00,0x00,0x00,0x00, + /* ASCII 125 */ 0x00,0x00,0x00,0x00,0x40,0x20,0x3b,0xc0,0x04,0x00,0x00,0x00,0x00,0x00, + /* ASCII 126 */ 0x00,0x00,0x04,0x00,0x02,0x00,0x04,0x00,0x04,0x00,0x02,0x00,0x00,0x00}; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : LCD_DataLinesConfig +* Description : Configure data lines D0~D7 (P8.0~P8.7) in Input Floating mode +* for read from LCD or in Output Push-Pull mode for write on LCD +* Input : - Mode: specifies the configuration mode for data lines D0~D7 +* - Input: configure in Input Floating mode +* - Output: configure in Output Push-Pul mode +* Output : None +* Return : None +*******************************************************************************/ +void LCD_DataLinesConfig(DataConfigMode_TypeDef Mode) +{ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_All; + if (Mode == Input) + { + /* Configure D0~D7 lines (P8.0 ->P8.7) as Input */ + GPIO_InitStructure.GPIO_Direction = GPIO_PinInput; + } + else + { + /* Configure D0~D7 lines in Output Push-Pull mode */ + GPIO_InitStructure.GPIO_Direction = GPIO_PinOutput ; + GPIO_InitStructure.GPIO_Type = GPIO_Type_PushPull ; + } + GPIO_Init(GPIO8, &GPIO_InitStructure); +} + +/******************************************************************************* +* Function Name : LCD_DataLinesWrite +* Description : Write a value on D0~D7 (P8.0~P8.7) +* Input : - GPIOx: GPIO port to write on. It could be +* - PortVal: value to write +* Output : None +* Return : None. +*******************************************************************************/ +void LCD_DataLinesWrite(GPIO_TypeDef* GPIOx, u32 PortVal) +{ + GPIOx->DR[0x3FC] = PortVal; +} + +/******************************************************************************* +* Function Name : LCD_CtrlLinesConfig +* Description : Configure control lines E2, E1, RW, DI (P9.4~P9.7) in +* Output Push-Pull mode. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void LCD_CtrlLinesConfig(void) +{ + /* Configure E2, E1, RW, DI lines (P9.4~P9.7) in Output Push-Pull mode */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7; + GPIO_InitStructure.GPIO_Direction = GPIO_PinOutput ; + GPIO_InitStructure.GPIO_Type = GPIO_Type_PushPull ; + GPIO_Init(GPIO9, &GPIO_InitStructure); +} + +/******************************************************************************* +* Function Name : LCD_CtrlLinesWrite +* Description : Set or reset control lines E2, E1, RW, DI (P9.4~P9.7). +* Input : - GPIOx: where x can be 0,1 or 2 to select the GPIO peripheral. +* - CtrlPins: the Control line. This parameter can be: +* - CtrlPin_E2: Enabe clock signal for Slave +* - CtrlPin_E1: Enabe clock signal for Master +* - CtrlPin_RW: Read/Write control line +* - CtrlPin_DI: +* Output : None +* Return : None +*******************************************************************************/ +void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, u32 CtrlPins, BitAction BitVal) +{ + /* Set or Reset the control line */ + if(BitVal == Bit_SET) + { + GPIOx->DR[CtrlPins <<2] = CtrlPins; + } + else + { + GPIOx->DR[CtrlPins <<2] = 0x00; + } +} + +/******************************************************************************* +* Function Name : LCD_CheckMasterStatus +* Description : Check whether master LCD is busy or not +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void LCD_CheckMasterStatus(void) +{ + u8 MasterStatus = 0; + + /* Configure Data lines as Input */ + LCD_DataLinesConfig(Input); + /* Start the master read sequence */ + LCD_CtrlLinesWrite(GPIO9, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ + LCD_CtrlLinesWrite(GPIO9, CtrlPin_RW, Bit_SET); /* RW = 1 */ + LCD_CtrlLinesWrite(GPIO9, CtrlPin_DI, Bit_RESET); /* DI = 0 */ + LCD_CtrlLinesWrite(GPIO9, CtrlPin_E1, Bit_SET); /* E1 = 1 */ + MasterStatus = GPIO_Read(GPIO8); + LCD_CtrlLinesWrite(GPIO9, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ + + /* Wait until BF is cleared */ + while ((MasterStatus & 0x80)) + { + vTaskDelay( 1 ); + LCD_CtrlLinesWrite(GPIO9, CtrlPin_E1, Bit_SET); /* E1 = 1 */ + MasterStatus = GPIO_Read(GPIO8); + LCD_CtrlLinesWrite(GPIO9, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ + } +} + +/******************************************************************************* +* Function Name : LCD_CheckSlaveStatus +* Description : Check whether slave LCD is busy or not +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void LCD_CheckSlaveStatus(void) +{ + u8 SlaveStatus = 0; + + /* Configure Data lines as Input */ + LCD_DataLinesConfig(Input); + /* Start the slave read sequence */ + LCD_CtrlLinesWrite(GPIO9, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ + LCD_CtrlLinesWrite(GPIO9, CtrlPin_RW, Bit_SET); /* RW = 1 */ + LCD_CtrlLinesWrite(GPIO9, CtrlPin_DI, Bit_RESET); /* DI = 0 */ + LCD_CtrlLinesWrite(GPIO9, CtrlPin_E2, Bit_SET); /* E2 = 1 */ + SlaveStatus = GPIO_Read(GPIO8); + LCD_CtrlLinesWrite(GPIO9, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ + + /* Wait until BF is cleared */ + while ((SlaveStatus & 0x80)) + { + vTaskDelay( 1 ); + LCD_CtrlLinesWrite(GPIO9, CtrlPin_E2, Bit_SET); /* E2 = 1 */ + SlaveStatus = GPIO_Read(GPIO8); + LCD_CtrlLinesWrite(GPIO9, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ + } +} + +/******************************************************************************* +* Function Name : LCD_SendMasterCmd +* Description : Send one byte command to master LCD. +* Input : - Cmd: the user expected command to send to master LCD +* Output : None +* Return : None +*******************************************************************************/ +void LCD_SendMasterCmd(u8 Cmd) +{ + /* Check the master status */ + LCD_CheckMasterStatus(); + /* Configure Data lines as Output */ + LCD_DataLinesConfig(Output); + /* Start the master send command sequence */ + LCD_CtrlLinesWrite(GPIO9, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ + LCD_CtrlLinesWrite(GPIO9, CtrlPin_RW, Bit_RESET); /* RW = 0 */ + LCD_CtrlLinesWrite(GPIO9, CtrlPin_DI, Bit_RESET); /* DI = 0 */ + LCD_CtrlLinesWrite(GPIO9, CtrlPin_E1, Bit_SET); /* E1 = 1 */ + /* Write master command */ + LCD_DataLinesWrite(GPIO8, (u32)Cmd); + LCD_CtrlLinesWrite(GPIO9, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ +} + +/******************************************************************************* +* Function Name : LCD_SendSlaveCmd +* Description : Send one byte command to slave LCD +* Input : - Cmd: the user expected command to send to slave LCD. +* Output : None +* Return : None +*******************************************************************************/ +void LCD_SendSlaveCmd(u8 Cmd) +{ + /* Check the slave status */ + LCD_CheckSlaveStatus(); + /* Configure Data lines as Output */ + LCD_DataLinesConfig(Output); + /* Start the slave send command sequence */ + LCD_CtrlLinesWrite(GPIO9, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ + LCD_CtrlLinesWrite(GPIO9, CtrlPin_RW, Bit_RESET); /* RW = 0 */ + LCD_CtrlLinesWrite(GPIO9, CtrlPin_DI, Bit_RESET); /* DI = 0 */ + LCD_CtrlLinesWrite(GPIO9, CtrlPin_E2, Bit_SET); /* E2 = 1 */ + /* Write slave command */ + LCD_DataLinesWrite(GPIO8, (u32)Cmd); + LCD_CtrlLinesWrite(GPIO9, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ +} + +/******************************************************************************* +* Function Name : LCD_SendMasterData +* Description : Display one byte data to master LCD. +* Input : - Data: the user expected data to display on master LCD. +* Output : None +* Return : None +*******************************************************************************/ +void LCD_SendMasterData(u8 Data) +{ + /* Check the master status */ + LCD_CheckMasterStatus(); + /* Configure Data lines as Output */ + LCD_DataLinesConfig(Output); + /* Start the master send data sequence */ + LCD_CtrlLinesWrite(GPIO9, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ + LCD_CtrlLinesWrite(GPIO9, CtrlPin_RW, Bit_RESET); /* RW = 0 */ + LCD_CtrlLinesWrite(GPIO9, CtrlPin_DI, Bit_SET); /* DI = 1 */ + LCD_CtrlLinesWrite(GPIO9, CtrlPin_E1, Bit_SET); /* E1 = 1 */ + /* Write data to the master */ + LCD_DataLinesWrite(GPIO8, (u32)Data); + LCD_CtrlLinesWrite(GPIO9, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ +} + +/******************************************************************************* +* Function Name : LCD_ReadMasterData +* Description : Read master byte data displayed on master LCD. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +u32 LCD_ReadMasterData(void) +{ + u32 MasterData = 0; + + /* Check the master status */ + LCD_CheckMasterStatus(); + /* Configure Data lines as Input */ + LCD_DataLinesConfig(Input); + /* Start the master read data sequence */ + LCD_CtrlLinesWrite(GPIO9, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ + LCD_CtrlLinesWrite(GPIO9, CtrlPin_RW, Bit_SET); /* RW = 1 */ + LCD_CtrlLinesWrite(GPIO9, CtrlPin_DI, Bit_SET); /* DI = 1 */ + LCD_CtrlLinesWrite(GPIO9, CtrlPin_E1, Bit_SET); /* E1 = 1 */ + /* Read data from the master */ + MasterData = (GPIO_Read(GPIO8)); + LCD_CtrlLinesWrite(GPIO9, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ + /* Read the master returned data */ + return MasterData; +} + +/******************************************************************************* +* Function Name : LCD_SendSlaveData +* Description : Display one byte data to slave LCD. +* Input : - Data: the user expected data to display on slave LCD. +* Output : None +* Return : None +*******************************************************************************/ +void LCD_SendSlaveData(u8 Data) +{ + /* Check the slave status */ + LCD_CheckSlaveStatus(); + /* Configure Data lines as Output */ + LCD_DataLinesConfig(Output); + /* Start the slave send data sequence */ + LCD_CtrlLinesWrite(GPIO9, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ + LCD_CtrlLinesWrite(GPIO9, CtrlPin_RW, Bit_RESET); /* RW = 0 */ + LCD_CtrlLinesWrite(GPIO9, CtrlPin_DI, Bit_SET); /* DI = 1 */ + LCD_CtrlLinesWrite(GPIO9, CtrlPin_E2, Bit_SET); /* E2 = 1 */ + /* Write data to the slave */ + LCD_DataLinesWrite(GPIO8, (u32)Data); + LCD_CtrlLinesWrite(GPIO9, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ +} + +/******************************************************************************* +* Function Name : LCD_ReadSlaveData +* Description : Read slave byte data displayed on slave LCD. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +u32 LCD_ReadSlaveData(void) +{ + u32 SlaveData = 0; + + /* Check the slave status */ + LCD_CheckSlaveStatus(); + /* Configure Data lines as Input */ + LCD_DataLinesConfig(Input); + /* Start the slave read data sequence */ + LCD_CtrlLinesWrite(GPIO9, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ + LCD_CtrlLinesWrite(GPIO9, CtrlPin_RW, Bit_SET); /* RW = 1 */ + LCD_CtrlLinesWrite(GPIO9, CtrlPin_DI, Bit_SET); /* DI = 1 */ + LCD_CtrlLinesWrite(GPIO9, CtrlPin_E2, Bit_SET); /* E2 = 1 */ + /* Read data from the slave */ + SlaveData = GPIO_Read(GPIO8); + LCD_CtrlLinesWrite(GPIO9, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ + /* Read the slave returned data */ + return SlaveData; +} + +/******************************************************************************* +* Function Name : LCD_Init +* Description : Initialize master and slave LCD. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void LCD_Init(void) +{ + /* Enable GPIO Clock */ + + + /* Configure control lines signals as output mode */ + LCD_CtrlLinesConfig(); + + /* Master LCD Init */ + LCD_SendMasterCmd(SOFTWARE_RESET); + LCD_SendMasterCmd(DISPLAY_OFF); + LCD_SendMasterCmd(DYNAMIC_DRIVE); + LCD_SendMasterCmd(DUTY_CYCLE); + LCD_SendMasterCmd(CLOCKWISE_OUTPUT); + LCD_SendMasterCmd(READ_MODIFY_WRITE_OFF); + LCD_SendMasterCmd(START_COLUMN); /* Set master column address to 0 */ + LCD_SendMasterCmd(START_LINE); /* Set master display start line to 0 */ + LCD_SendMasterCmd(DISPLAY_ON ); + + /* Slave LCD Init */ + LCD_SendSlaveCmd(SOFTWARE_RESET); + LCD_SendSlaveCmd(DISPLAY_OFF); + LCD_SendSlaveCmd(DYNAMIC_DRIVE); + LCD_SendSlaveCmd(DUTY_CYCLE); + LCD_SendSlaveCmd(CLOCKWISE_OUTPUT); + LCD_SendSlaveCmd(READ_MODIFY_WRITE_OFF); + LCD_SendSlaveCmd(START_COLUMN ); /* Set slave column address to 0 */ + LCD_SendSlaveCmd(START_LINE); /* Set slave display start line to 0 */ + LCD_SendSlaveCmd(DISPLAY_ON); + + /* Clear LCD */ + LCD_Clear(); + /* Set current Page to 0 for Master and Slave LCDs */ + LCD_SetSlavePage(0); + LCD_SetMasterPage(0); +} + +/******************************************************************************* +* Function Name : LCD_SetSlavePage +* Description : Set the display page of slave LCD, the page range is 0 to 3, +* make sure the input will not exceed this range ,otherwise it +* will reach a undecided result. +* Input : - Page: specifies the expected display page of slave LCD +* Output : None +* Return : None +*******************************************************************************/ +void LCD_SetSlavePage(u8 Page) +{ +static u8 ucLastPage = 255; + + /* Set Slave page */ + if( Page != ucLastPage ) + { + LCD_SendSlaveCmd(0xB8|Page); + ucLastPage = Page; + } +} + +/******************************************************************************* +* Function Name : LCD_SetMasterPage +* Description : Set the display page of master LCD, the page range is 0 to 3, +* make sure the input will not exceed this range ,otherwise it +* will reach a undecided result. +* Input : - Page: specifies the expected display page of master LCD +* Output : None +* Return : None +*******************************************************************************/ +void LCD_SetMasterPage(u8 Page) +{ +static u8 ulLastPage = 255; + + /* Set Master page */ + if( Page != ulLastPage ) + { + LCD_SendMasterCmd(0xB8|Page); + ulLastPage = Page; + } +} + +/******************************************************************************* +* Function Name : SetAddress +* Description : Set the display column of slave LCD. Column range is 0 to 61. +* Input : - Address: specifies the expected display column of slave LCD +* Output : None +* Return : None +*******************************************************************************/ +void LCD_SetSlaveColumn(u8 Address) +{ + /* Set Slave column address */ + LCD_SendSlaveCmd(Address&0x7F); +} + +/******************************************************************************* +* Function Name : LCD_SetMasterColumn +* Description : Set the display column of master LCD. Column range is 0 to 61. +* Input : - Address: specifies the expected display column of slave LCD +* Output : None +* Return : None +*******************************************************************************/ +void LCD_SetMasterColumn(u8 Address) +{ + /* Set Master column address */ + LCD_SendMasterCmd(Address&0x7F); +} + +/******************************************************************************* +* Function Name : LCD_SetTextColor +* Description : Set the text color for LCD. +* Input : - TextColor: BlackText: character on black, bottom on white. +* WhiteText: character on white, bottom on black. +* Output : None +* Return : None +*******************************************************************************/ +void LCD_SetTextColor(TextColorMode_TypeDef TextColor) +{ + if(TextColor) + { + /* Set White Text color */ + TextMode=WhiteText; + } + else + { + /* Set Black Text color */ + TextMode=BlackText; + } +} + +/******************************************************************************* +* Function Name : LCD_Clear +* Description : Clear the Master and Slave LCDs display. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void LCD_Clear(void) +{ + u8 Page = 0, Column = 0; + + /* Clear master and slave LCDs page by page */ + for (Page=0; Page<4; Page++) + { + /* Set master and slave page by page */ + LCD_SetMasterPage(Page); + LCD_SetSlavePage(Page); + /* Set master and slave column address */ + LCD_SetMasterColumn(0); + LCD_SetSlaveColumn(0); + /* Send empty data to master and slave column address on the selected page */ + for (Column=0; Column<61; Column++) + { + LCD_SendSlaveData(0); + LCD_SendMasterData(0); + } + } +} + +/******************************************************************************* +* Function Name : LCD_ClearLine +* Description : Clear the selected line of the LCD. +* Input : - Line: the Line to clear. +* - Line1 (Page0&1): clear the first line +* - Line2 (Page2&3): clear the second line +* Output : None +* Return : None +*******************************************************************************/ +void LCD_ClearLine(u8 Line) +{ + u8 Page = 0, Column = 0; + + /* Clear the slected master and slave line */ + for (Page=Line; Page 121) + { + /* Return if column exceeded 121 */ + return; + } + if (X > 60) + { + /* To be displayed on slave LCD (Window = 1) */ + Window = 1; + /* Get the Slave relative start column */ +// ActualColumn = X%61; + ActualColumn = X - 61; + } + else + { + /* To be displayed on master LCD (Window = 0) */ + ActualColumn = X; + } + + /* Switch window, display the character upper part */ + if (Window) + { + /* Display it on slave LCD */ + LCD_SetSlavePage(Line); + LCD_SetSlaveColumn(ActualColumn); + LCD_SendSlaveData(Bmp[i]); + } + else + { + /* Display it on master LCD */ + LCD_SetMasterPage(Line); + LCD_SetMasterColumn(ActualColumn); + LCD_SendMasterData(Bmp[i]); + } + /* Switch window, diplay the character lower part */ + if (Window) + { + /* Display it on slave LCD */ + LCD_SetSlavePage(Line+1); + LCD_SetSlaveColumn(ActualColumn); + LCD_SendSlaveData(Bmp[i+1]); + } + else + { + /* Display it on master LCD */ + LCD_SetMasterPage(Line+1); + LCD_SetMasterColumn(ActualColumn); + LCD_SendMasterData(Bmp[i+1]); + } + /* Increment by 2 the character table index */ + i+=2; + } +} + +/******************************************************************************* +* Function Name : LCD_DisplayChar +* Description : Display one character (7dots large, 16dots high). +* Note: +* the LCD can only display two line character,so page 0 and 1 +* is to display the first line, page2 and page 3 is to display +* the second line. +* Input : - Line: the Line where to display the character. +* - Line1 (Page0&1): display character on the first line +* - Line2 (Page2&3): display character on the second line +* - Column: start column address. +* - Ascii: character ascii code. +* - CharMode: BlackText: character on black, bottom on white. +* WhiteText: character on white, bottom on black. +* Output : None +* Return : None +*******************************************************************************/ +void LCD_DisplayChar(u8 Line, u8 Column, u8 Ascii, TextColorMode_TypeDef CharMode) +{ + u8 DotBuffer[14], i = 0; + + /* Display the character lower and upper 8bit parts (2*7columns) */ + for (i=0;i<14;i++) + { + /* Character displayed as white Text on black buttom */ + if(CharMode) + { + if( i & 0x01 ) + { + DotBuffer[i] = ~AsciiDotsTable[Ascii*14+i-1]; + } + else + { + DotBuffer[i] = ~AsciiDotsTable[Ascii*14+i+1]; + } + } + /* Character displayed as black Text on white buttom */ + else + { + if( ( u8 ) i & 0x01 ) + { + DotBuffer[i] = AsciiDotsTable[Ascii*14+i-1]; + } + else + { + DotBuffer[i] = AsciiDotsTable[Ascii*14+i+1]; + } + } + } + /* Display the asc code after conversion */ + LCD_DrawChar(Line, Column, 7, DotBuffer); +} + +/******************************************************************************* +* Function Name : LCD_HexToAsciiLow +* Description : This function is used to convert the low nibble of an +* unsigned byte (0-F hex) to ASCII. +* Input : - byte: byte to convert to ASCII. +* Output : None +* Return : ASCII value result of the conversion. +*******************************************************************************/ +char LCD_HexToAsciiLow(u8 byte) +{ + /* Keep lower nibble only */ + byte = byte & 0x0F; + /* If the ascii is a number */ + if (byte <= 0x09) + { + /* Add 0x30 to its ascii */ + return(byte + 0x30); + } + else + { + /* Add 0x37 to its ascii */ + return (byte + 0x37); + } +} + +/******************************************************************************* +* Function Name : LCD_HexToAsciiHigh +* Description : This function is used to convert the high nibble of an +* unsigned byte (0-F hex) to ASCII. +* Input : - byte: byte to convert to ASCII. +* Output : None +* Return : ASCII value result of the conversion. +*******************************************************************************/ +char LCD_HexToAsciiHigh(u8 byte) +{ + /* Keep upper nibble only */ + byte = byte & 0xF0; + byte = byte >> 4; + /* If the ascii is a number */ + if (byte <= 0x09) + { + /* Add 0x30 to display its ascii */ + return(byte + 0x30); + } + else + { + /* Add 0x37 to display its ascii */ + return (byte + 0x37); + } +} + +/******************************************************************************* +* Function Name : LCD_DisplayString +* Description : This function is used to display a 17char max string of +* characters on the LCD display on the selected line. +* Note: +* this function is the user interface to use the LCD driver. +* Input : - *ptr: pointer to string to display on LCD. +* - Line: the Line where to display the character. +* - Line1 (Page0&1): display character on the first line +* - Line2 (Page2&3): display character on the second line +* Output : None +* Return : None +*******************************************************************************/ +void LCD_DisplayString(u8 Line, u8 *ptr, TextColorMode_TypeDef CharMode) +{ + u8 RefColumn = 0, i = 0; + + /* Send the string character by character on lCD */ + while ((*ptr!=0)&(i<17)) + { + vTaskDelay( 1 ); + + /* Display one character on LCD */ + LCD_DisplayChar(Line, RefColumn, *ptr, CharMode); + + /* Increment the column position by 7 */ + RefColumn+=7; + /* Point on the next character */ + ptr++; + /* Increment the character counter */ + i++; + /* If we reach the maximum Line character */ + if(i==17) + { + LCD_DisplayChar(Line, RefColumn-1, 0x1f, CharMode); /* Add missed columns */ + } + } +} + +/******************************************************************************* +* Function Name : LCD_Printf +* Description : This function is used to display a string of characters +* on the LCD display. +* Note: +* this function is the user interface to use the LCD driver. +* Input : - *ptr: pointer to string to display on LCD. +* Output : None +* Return : None +*******************************************************************************/ +void LCD_Printf(u8 *ptr, ...) +{ + u8 RefColumn = 0, RefPage = 0, i = 0, c1 = 0; + u16 var = 0, c2 = 0, c3 = 0, c4 = 0, c5 = 0; + u32 WordVar = 0; + + /* Store pointer on LCD_Printf second parameter (String) */ + u8 *var_ptr=(u8 *)(&ptr+1); + + /* Send String */ + while (*ptr != 0) + { + c1 = *ptr; + /* Limited to AsciiDotsTable code table */ + if(c1 <= 128) + { + /* Carriage return */ + if ( *ptr == '\r') + { + ptr++; + RefColumn = 0; + } + /* Jump to Line2 */ + else if( *ptr == '\n') + { + /* Point on the string to display */ + ptr++; + /* Clear Line2 */ + LCD_ClearLine(Line2); + /* Point on first Line2 column */ + RefColumn = 0; + /* Increment RefPage by 2 */ + RefPage+=2; + } + /* Display value on the passed format */ + else if( *ptr == '%') + { + ptr++; + /* Display decimal value */ + if (*ptr == 'd') + { + ptr++; + /* Get the word value to display */ + WordVar = ((*var_ptr)|(*(var_ptr+1)<<8)|(*(var_ptr+2)<<16)); + c1=WordVar/10000; + c2=(WordVar%10000)/1000; + c3=(WordVar%1000)/100; + c4=(WordVar%100)/10; + c5=(WordVar%10); + /* Display the ten miles digit */ + if (c1!=0) + { + LCD_DisplayChar(RefPage, RefColumn, c1+0x30, TextMode); + RefColumn+=7; + } + /* Display the miles digit */ + if (!((c1==0)&(c2==0))) + { + LCD_DisplayChar(RefPage, RefColumn, c2+0x30, TextMode); + RefColumn+=7; + } + /* Display the hundred digit */ + if (!((c1==0)&(c2==0)&(c3==0))) + { + LCD_DisplayChar(RefPage, RefColumn, c3+0x30, TextMode); + RefColumn+=7; + } + /* Display the tens digit */ + if (!((c1==0)&(c2==0)&(c3==0)&(c4==0))) + { + LCD_DisplayChar(RefPage, RefColumn, c4+0x30, TextMode); + RefColumn+=7; + } + /* Display the rest */ + LCD_DisplayChar(RefPage, RefColumn, c5+0x30, TextMode); + RefColumn+=7; + } + /* Display 16bits Hex value */ + else if (*ptr == 'x') + { + ptr++; + /* Display 8bits MSB */ + var_ptr = var_ptr +1; + var = *var_ptr; + c1 = LCD_HexToAsciiHigh(var); + LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); + RefColumn+=7; + c1 = LCD_HexToAsciiLow(var); + LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); + RefColumn+=7; + /* Display 8bits LSB */ + var_ptr = var_ptr -1; + var = *var_ptr; + var_ptr = var_ptr +4; + c1 = LCD_HexToAsciiHigh(var); + LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); + RefColumn+=7; + c1 = LCD_HexToAsciiLow(var); + LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); + RefColumn+=7; + } + /* Display 32bits Hex value */ + else if (*ptr == 'w') + { + ptr++; + /* Display 16bits MSB */ + var_ptr = var_ptr +3; + var = *var_ptr; + c1 = LCD_HexToAsciiHigh(var); + LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); + RefColumn+=7; + c1 = LCD_HexToAsciiLow(var); + LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); + RefColumn+=7; + var_ptr = var_ptr -1; + var = *var_ptr; + c1 = LCD_HexToAsciiHigh(var); + LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); + RefColumn+=7; + c1 = LCD_HexToAsciiLow(var); + LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); + RefColumn+=7; + /* Display 16bits LSB */ + var_ptr = var_ptr -1; + var = *var_ptr; + var_ptr = var_ptr +4; + c1 = LCD_HexToAsciiHigh(var); + LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); + RefColumn+=7; + c1 = LCD_HexToAsciiLow(var); + LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); + RefColumn+=7; + var_ptr = var_ptr -5; + var = *var_ptr; + var_ptr = var_ptr +4; + c1 = LCD_HexToAsciiHigh(var); + LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); + RefColumn+=7; + c1 = LCD_HexToAsciiLow(var); + LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); + RefColumn+=7; + } + else + { + /* Display '%' character which is followed by (d, x or w) */ + ptr--; + c1 = *ptr; + LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); + RefColumn+=7; + ptr++; + i++; + if(i==17) + { + /* Add missed columns */ + LCD_DisplayChar(RefPage, RefColumn-1, 0x1f, TextMode); + RefColumn = 0; + RefPage+=2; + } + } + } + else + { + /* Display characters different from (\r, \n, %) */ + LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); + RefColumn+=7; + ptr++; + i++; + if(i==17) + { + /* Add missed columns */ + LCD_DisplayChar(RefPage, RefColumn-1, 0x1f, TextMode); + LCD_ClearLine(Line2); + RefColumn = 0; + RefPage+=2; + } + } + } + } + /* Display spaces if string doesn't reach the max LCD characters size */ + while(RefColumn<119) + { + /* Display Spaces */ + LCD_DisplayChar(RefPage, RefColumn, 0x20, TextMode); + RefColumn+=7; + /* Add missed columns */ + LCD_DisplayChar(RefPage, RefColumn, 0x1f, TextMode); + } +} + +/******************************************************************************* +* Function Name : LCD_DrawMasterGraphic +* Description : Draw a Graphic image on master LCD. +* Input : - Bmp: the pointer of the dot matrix data. +* Output : None +* Return : None. +*******************************************************************************/ +void LCD_DrawMasterGraphic(u8 *Bmp) +{ + u8 j = 0, k = 0, ActPage = 0; + + /* Draw graphic on master: 61 Column *4 Pages */ + while(j<244) + { + /* Draw on master page by page */ + LCD_SetMasterPage(ActPage); + for(k=0; k<61; k++) + { + LCD_SetMasterColumn(k); + LCD_SendMasterData(*Bmp++); + j++; + } + ActPage++; + } +} + +/******************************************************************************* +* Function Name : LCD_DrawSlaveGraphic +* Description : Draw a Graphic image on slave LCD. +* Input : - Bmp: the pointer of the dot matrix data. +* Output : None +* Return : None. +*******************************************************************************/ +void LCD_DrawSlaveGraphic(u8 *Bmp) +{ + u8 j = 0, k = 0, ActPage = 0; + + /* Draw graphic on slave: 61 Column *4 Pages */ + while(j<244) + { + /* Draw on slave page by page */ + LCD_SetSlavePage(ActPage); + for(k=0; k<61; k++) + { + LCD_SetSlaveColumn(k); + LCD_SendSlaveData(*Bmp++); + j++; + } + ActPage++; + } +} + +/******************************************************************************* +* Function Name : LCD_DrawGraphic +* Description : Draw a Graphic image on LCD. +* Input : - Bmp: the pointer of the dot matrix data. +* Output : None +* Return : None. +*******************************************************************************/ +void LCD_DrawGraphic(u8 *Bmp) +{ + u8 Pos = 0, ActPage = 0; + u16 j = 0, k = 0; + + /* Draw graphic on LCD: 122 Column *4 Pages */ + while(j<488) + { + if(!Pos) + { + /* Draw on master page by page */ + LCD_SetMasterPage(ActPage); + for(k=0; k<61; k++) + { + LCD_SetMasterColumn(k); + LCD_SendMasterData(*Bmp++); + j++; + } + Pos=1; + } + else + { + /* Draw on slave page by page */ + LCD_SetSlavePage(ActPage); + for(k=0; k<61; k++) + { + LCD_SetSlaveColumn(k); + LCD_SendSlaveData(*Bmp++); + j++; + } + ActPage++; + Pos=0; + } + } +} + +/******************************************************************************* +* Function Name : LCD_ScrollGraphic +* Description : Scroll a Graphic image on LCD. +* Input : - Bmp: the pointer of the dot matrix data. +* - nCount: specifies the delay time length. +* Output : None +* Return : None. +*******************************************************************************/ +void LCD_ScrollGraphic(u8 *Bmp, u32 nCount) +{ + u8 Pos = 0, ActPage = 0; + u16 j = 0, k = 0; + u32 Counter = 0; + + /* Draw graphic on LCD: 122 Column *4 Pages */ + while(j<488) + { + if(!Pos) + { + /* Draw on master page by page */ + LCD_SetMasterPage(ActPage); + for(k=0; k<61; k++) + { + LCD_SetMasterColumn(k); + LCD_SendMasterData(*Bmp++); + Counter = nCount; + /* Set a delay */ + for(; Counter != 0; Counter--); + j++; + } + Pos=1; + } + else + { + /* Draw on slave page by page */ + LCD_SetSlavePage(ActPage); + for(k=0; k<61; k++) + { + LCD_SetSlaveColumn(k); + Counter = nCount; + /* Set a delay */ + for(; Counter != 0; Counter--); + LCD_SendSlaveData(*Bmp++); + j++; + } + ActPage++; + Pos=0; + } + } +} + +/******************************************************************************* +* Function Name : LCD_DrawPixel +* Description : Draw a Graphic image on slave LCD. +* Input : - XPos: the dot line number of the pixel. +* - 1->61 : displayed on master LCD +* - 62->122: displayed on slave LCD +* - YPos: column address of the pixel from 1->32. +* - Mode: Dot_On: Pixel turned on (black). +* Dot_Off: Pixel turned off (black). +* Output : None +* Return : None. +*******************************************************************************/ +void LCD_DrawPixel(u8 XPos, u8 YPos, DotMode_TypeDef Mode) +{ + u8 Page = 0, Position = 0; + u16 Mask = 0; + u32 MasterDataIn = 0, MasterDataOut = 0, SlaveDataIn = 0, SlaveDataOut = 0; + + /* Pixel page */ + Page = (XPos-1)/8; + /* Pixel column */ + Position = (YPos-1)/61; /* 0:Master, 1:Slave */ + /* Mask for the pixel */ + Mask= 1<<((XPos-1)%8); + /* If Position=0 draw pixel on master LCD */ + if(!Position) + { + LCD_SetMasterPage(Page); + LCD_SetMasterColumn(YPos-1); + MasterDataIn = LCD_ReadMasterData(); + MasterDataIn = LCD_ReadMasterData(); + LCD_SetMasterColumn(YPos-1); + if(Mode==Dot_On) + { + MasterDataOut = MasterDataIn | Mask; + } + else + { + MasterDataOut = MasterDataIn & (~Mask); + } + LCD_SendMasterData(MasterDataOut); + } + /* If Position=1 draw pixel on slave LCD */ + else + { + LCD_SetSlavePage(Page); + LCD_SetSlaveColumn(YPos-62); + SlaveDataIn = LCD_ReadSlaveData(); + SlaveDataIn = LCD_ReadSlaveData(); + LCD_SetSlaveColumn(YPos-62); + if(Mode==Dot_On) + { + SlaveDataOut = SlaveDataIn | Mask; + } + else + { + SlaveDataOut = SlaveDataIn & (~Mask); + } + LCD_SendSlaveData(SlaveDataOut); + } +} + +/******************************************************************************* +* Function Name : LCD_DrawLine +* Description : Draw a line on master and slave LCDs. +* Input : - XPos1: the dot line number of the source point . +* - XPos2: the dot line number of the destination point . +* - YPos1: the dot column number of the source point. +* - YPos2: the dot column number of the destination point. +* Output : None +* Return : None. +*******************************************************************************/ +void LCD_DrawLine(u8 XPos1, u8 YPos1, u8 XPos2, u8 YPos2) +{ + u8 XPos = 0, YPos = 0; + + /* Use XPos1, YPos1, XPos2 and YPos2 */ + if((XPos2>=XPos1)&(YPos2>=YPos1)) + { + for(XPos=XPos1; XPos<=XPos2; XPos++) + { + for(YPos=YPos1; YPos<=YPos2; YPos++) + { + LCD_DrawPixel(XPos, YPos, Dot_On); + } + } + } + else if((XPos2=YPos1)) + { + for(XPos=XPos2; XPos<=XPos1; XPos++) + { + for(YPos=YPos1; YPos<=YPos2; YPos++) + { + LCD_DrawPixel(XPos, YPos, Dot_On); + } + } + } + else if((XPos2>=XPos1)&(YPos2 + * + */ + +/* lwIP includes. */ +#include "lwip/debug.h" +#include "lwip/def.h" +#include "lwip/sys.h" +#include "lwip/mem.h" + +#include + +/* Message queue constants. */ +#define archMESG_QUEUE_LENGTH ( 6 ) +#define archPOST_BLOCK_TIME_MS ( ( unsigned portLONG ) 10000 ) + +struct timeoutlist +{ + struct sys_timeouts timeouts; + xTaskHandle pid; +}; + +/* This is the number of threads that can be started with sys_thread_new() */ +#define SYS_THREAD_MAX 4 + +static struct timeoutlist timeoutlist[SYS_THREAD_MAX]; +static u16_t nextthread = 0; +int intlevel = 0; + +static sys_arch_state_t s_sys_arch_state; + +/*-----------------------------------------------------------------------------------*/ +// Creates an empty mailbox. +sys_mbox_t +sys_mbox_new(void) +{ + xQueueHandle mbox; + + mbox = xQueueCreate( archMESG_QUEUE_LENGTH, sizeof( void * ) ); + + return mbox; +} + +/*-----------------------------------------------------------------------------------*/ +/* + Deallocates a mailbox. If there are messages still present in the + mailbox when the mailbox is deallocated, it is an indication of a + programming error in lwIP and the developer should be notified. +*/ +void +sys_mbox_free(sys_mbox_t mbox) +{ + if( uxQueueMessagesWaiting( mbox ) ) + { + /* Line for breakpoint. Should never break here! */ +// __asm volatile ( "NOP" ); + } + + vQueueDelete( mbox ); +} + +/*-----------------------------------------------------------------------------------*/ +// Posts the "msg" to the mailbox. +void +sys_mbox_post(sys_mbox_t mbox, void *data) +{ + xQueueSend( mbox, &data, ( portTickType ) ( archPOST_BLOCK_TIME_MS / portTICK_RATE_MS ) ); +} + + +/*-----------------------------------------------------------------------------------*/ +/* + Blocks the thread until a message arrives in the mailbox, but does + not block the thread longer than "timeout" milliseconds (similar to + the sys_arch_sem_wait() function). The "msg" argument is a result + parameter that is set by the function (i.e., by doing "*msg = + ptr"). The "msg" parameter maybe NULL to indicate that the message + should be dropped. + + The return values are the same as for the sys_arch_sem_wait() function: + Number of milliseconds spent waiting or SYS_ARCH_TIMEOUT if there was a + timeout. + + Note that a function with a similar name, sys_mbox_fetch(), is + implemented by lwIP. +*/ +u32_t sys_arch_mbox_fetch(sys_mbox_t mbox, void **msg, u32_t timeout) +{ +void *dummyptr; +portTickType StartTime, EndTime, Elapsed; + + StartTime = xTaskGetTickCount(); + + if( msg == NULL ) + { + msg = &dummyptr; + } + + if( timeout != 0 ) + { + if(pdTRUE == xQueueReceive( mbox, &(*msg), timeout ) ) + { + EndTime = xTaskGetTickCount(); + Elapsed = EndTime - StartTime; + if( Elapsed == 0 ) + { + Elapsed = 1; + } + return ( Elapsed ); + } + else // timed out blocking for message + { + *msg = NULL; + return SYS_ARCH_TIMEOUT; + } + } + else // block forever for a message. + { + while( pdTRUE != xQueueReceive( mbox, &(*msg), 10000 ) ) // time is arbitrary + { + ; + } + EndTime = xTaskGetTickCount(); + Elapsed = EndTime - StartTime; + if( Elapsed == 0 ) + { + Elapsed = 1; + } + return ( Elapsed ); // return time blocked TBD test + } +} + +/*-----------------------------------------------------------------------------------*/ +// Creates and returns a new semaphore. The "count" argument specifies +// the initial state of the semaphore. TBD finish and test +sys_sem_t +sys_sem_new(u8_t count) +{ + xSemaphoreHandle xSemaphore; + + portENTER_CRITICAL(); + vSemaphoreCreateBinary( xSemaphore ); + if(count == 0) // Means it can't be taken + { + xSemaphoreTake(xSemaphore,1); + } + portEXIT_CRITICAL(); + + if( xSemaphore == NULL ) + { + return NULL; // TBD need assert + } + else + { + return xSemaphore; + } +} + +/*-----------------------------------------------------------------------------------*/ +/* + Blocks the thread while waiting for the semaphore to be + signaled. If the "timeout" argument is non-zero, the thread should + only be blocked for the specified time (measured in + milliseconds). + + If the timeout argument is non-zero, the return value is the number of + milliseconds spent waiting for the semaphore to be signaled. If the + semaphore wasn't signaled within the specified time, the return value is + SYS_ARCH_TIMEOUT. If the thread didn't have to wait for the semaphore + (i.e., it was already signaled), the function may return zero. + + Notice that lwIP implements a function with a similar name, + sys_sem_wait(), that uses the sys_arch_sem_wait() function. +*/ +u32_t +sys_arch_sem_wait(sys_sem_t sem, u32_t timeout) +{ +portTickType StartTime, EndTime, Elapsed; + + StartTime = xTaskGetTickCount(); + + if( timeout != 0) + { + if( xSemaphoreTake( sem, timeout ) == pdTRUE ) + { + EndTime = xTaskGetTickCount(); + Elapsed = EndTime - StartTime; + if( Elapsed == 0 ) + { + Elapsed = 1; + } + return (Elapsed); // return time blocked TBD test + } + else + { + return SYS_ARCH_TIMEOUT; + } + } + else // must block without a timeout + { + while( xSemaphoreTake( sem, 10000 ) != pdTRUE ) + { + ; + } + EndTime = xTaskGetTickCount(); + Elapsed = EndTime - StartTime; + if( Elapsed == 0 ) + { + Elapsed = 1; + } + + return ( Elapsed ); // return time blocked + + } +} + +/*-----------------------------------------------------------------------------------*/ +// Signals a semaphore +void +sys_sem_signal(sys_sem_t sem) +{ + xSemaphoreGive( sem ); +} + +/*-----------------------------------------------------------------------------------*/ +// Deallocates a semaphore +void +sys_sem_free(sys_sem_t sem) +{ + vQueueDelete( sem ); +} + +/*-----------------------------------------------------------------------------------*/ +// Initialize sys arch +void +sys_init(void) +{ + + int i; + + // Initialize the the per-thread sys_timeouts structures + // make sure there are no valid pids in the list + for(i = 0; i < SYS_THREAD_MAX; i++) + { + timeoutlist[i].pid = 0; + } + + // keep track of how many threads have been created + nextthread = 0; + + s_sys_arch_state.nTaskCount = 0; + sys_set_default_state(); +} + +/*-----------------------------------------------------------------------------------*/ +/* + Returns a pointer to the per-thread sys_timeouts structure. In lwIP, + each thread has a list of timeouts which is represented as a linked + list of sys_timeout structures. The sys_timeouts structure holds a + pointer to a linked list of timeouts. This function is called by + the lwIP timeout scheduler and must not return a NULL value. + + In a single threaded sys_arch implementation, this function will + simply return a pointer to a global sys_timeouts variable stored in + the sys_arch module. +*/ +struct sys_timeouts * +sys_arch_timeouts(void) +{ +int i; +xTaskHandle pid; +struct timeoutlist *tl; + + pid = xTaskGetCurrentTaskHandle( ); + + for(i = 0; i < nextthread; i++) + { + tl = &timeoutlist[i]; + if(tl->pid == pid) + { + return &(tl->timeouts); + } + } + + // Error + return NULL; +} + +/*-----------------------------------------------------------------------------------*/ +/*-----------------------------------------------------------------------------------*/ +// TBD +/*-----------------------------------------------------------------------------------*/ +/* + Starts a new thread with priority "prio" that will begin its execution in the + function "thread()". The "arg" argument will be passed as an argument to the + thread() function. The id of the new thread is returned. Both the id and + the priority are system dependent. +*/ +sys_thread_t sys_thread_new(void (* thread)(void *arg), void *arg, int prio) +{ +xTaskHandle CreatedTask; +int result; + + result = xTaskCreate(thread, ( signed portCHAR * ) s_sys_arch_state.cTaskName, s_sys_arch_state.nStackDepth, arg, prio, &CreatedTask ); + + // For each task created, store the task handle (pid) in the timers array. + // This scheme doesn't allow for threads to be deleted + timeoutlist[nextthread++].pid = CreatedTask; + + if(result == pdPASS) + { + ++s_sys_arch_state.nTaskCount; + + return CreatedTask; + } + else + { + return NULL; + } +} + +/* + This optional function does a "fast" critical region protection and returns + the previous protection level. This function is only called during very short + critical regions. An embedded system which supports ISR-based drivers might + want to implement this function by disabling interrupts. Task-based systems + might want to implement this by using a mutex or disabling tasking. This + function should support recursive calls from the same task or interrupt. In + other words, sys_arch_protect() could be called while already protected. In + that case the return value indicates that it is already protected. + + sys_arch_protect() is only required if your port is supporting an operating + system. +*/ +sys_prot_t sys_arch_protect(void) +{ + vPortEnterCritical(); + return 1; +} + +/* + This optional function does a "fast" set of critical region protection to the + value specified by pval. See the documentation for sys_arch_protect() for + more information. This function is only required if your port is supporting + an operating system. +*/ +void sys_arch_unprotect(sys_prot_t pval) +{ + ( void ) pval; + vPortExitCritical(); +} + +void sys_set_default_state() +{ + s_sys_arch_state.nStackDepth = configMINIMAL_STACK_SIZE; + sprintf(s_sys_arch_state.cTaskName, "thread%d", s_sys_arch_state.nTaskCount); +} + +void sys_set_state(signed portCHAR *pTaskName, unsigned portSHORT nStackSize) +{ + s_sys_arch_state.nStackDepth = nStackSize; + sprintf(s_sys_arch_state.cTaskName, "%s", pTaskName); +} diff --git a/20080212/Demo/ARM9_STR91X_IAR/lwip/include/arch/cc.h b/20080212/Demo/ARM9_STR91X_IAR/lwip/include/arch/cc.h new file mode 100644 index 000000000..1e401b04c --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/lwip/include/arch/cc.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * Author: Stefano Oliveri + * + */ +#ifndef __CC_H__ +#define __CC_H__ + +#include "cpu.h" + +//#define LWIP_PROVIDE_ERRNO 1 +#include "lwip_errno.h" + +// Typedefs for the types used by lwip + +typedef unsigned char u8_t; +typedef signed char s8_t; +typedef unsigned short u16_t; +typedef signed short s16_t; +typedef unsigned long u32_t; +typedef signed long s32_t; +typedef u32_t mem_ptr_t; +typedef int sys_prot_t; + +// Compiler hints for packing lwip's structures + +#define PACK_STRUCT_BEGIN +//#define PACK_STRUCT_BEGIN _Pragma("pack(2)") +#define PACK_STRUCT_STRUCT +#define PACK_STRUCT_END +//#define PACK_STRUCT_END _Pragma("pack()") +#define PACK_STRUCT_FIELD(x) x + +// Platform specific diagnostic output + +// non-fatal, print a message. +#define LWIP_PLATFORM_DIAG(x) +// fatal, print message and abandon execution. +#define LWIP_PLATFORM_ASSERT(x) + +// "lightweight" synchronization mechanisms + +// declare a protection state variable. +#define SYS_ARCH_DECL_PROTECT(x) +// enter protection mode. +#define SYS_ARCH_PROTECT(x) +// leave protection mode. +#define SYS_ARCH_UNPROTECT(x) + + +#endif /* __CC_H__ */ diff --git a/20080212/Demo/ARM9_STR91X_IAR/lwip/include/arch/cpu.h b/20080212/Demo/ARM9_STR91X_IAR/lwip/include/arch/cpu.h new file mode 100644 index 000000000..2af31a864 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/lwip/include/arch/cpu.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __CPU_H__ +#define __CPU_H__ + +#define BYTE_ORDER LITTLE_ENDIAN + +#endif /* __CPU_H__ */ diff --git a/20080212/Demo/ARM9_STR91X_IAR/lwip/include/arch/lwip_errno.h b/20080212/Demo/ARM9_STR91X_IAR/lwip/include/arch/lwip_errno.h new file mode 100644 index 000000000..bae240779 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/lwip/include/arch/lwip_errno.h @@ -0,0 +1,153 @@ +#ifndef __LWIP_ERRNO_H_ +#define __LWIP_ERRNO_H_ + +#define EPERM 1 /* Operation not permitted */ +#define ENOENT 2 /* No such file or directory */ +#define ESRCH 3 /* No such process */ +#define EINTR 4 /* Interrupted system call */ +#define EIO 5 /* I/O error */ +#define ENXIO 6 /* No such device or address */ +#define E2BIG 7 /* Arg list too long */ +#define ENOEXEC 8 /* Exec format error */ +#define EBADF 9 /* Bad file number */ +#define ECHILD 10 /* No child processes */ +#define EAGAIN 11 /* Try again */ +#define ENOMEM 12 /* Out of memory */ +#define EACCES 13 /* Permission denied */ +#define EFAULT 14 /* Bad address */ +#define ENOTBLK 15 /* Block device required */ +#define EBUSY 16 /* Device or resource busy */ +#define EEXIST 17 /* File exists */ +#define EXDEV 18 /* Cross-device link */ +#define ENODEV 19 /* No such device */ +#define ENOTDIR 20 /* Not a directory */ +#define EISDIR 21 /* Is a directory */ +#define EINVAL 22 /* Invalid argument */ +#define ENFILE 23 /* File table overflow */ +#define EMFILE 24 /* Too many open files */ +#define ENOTTY 25 /* Not a typewriter */ +#define ETXTBSY 26 /* Text file busy */ +#define EFBIG 27 /* File too large */ +#define ENOSPC 28 /* No space left on device */ +#define ESPIPE 29 /* Illegal seek */ +#define EROFS 30 /* Read-only file system */ +#define EMLINK 31 /* Too many links */ +#define EPIPE 32 /* Broken pipe */ +//#define EDOM 33 /* Math argument out of domain of func */ +//#define ERANGE 34 /* Math result not representable */ +#define EDEADLK 35 /* Resource deadlock would occur */ +#define ENAMETOOLONG 36 /* File name too long */ +#define ENOLCK 37 /* No record locks available */ +#define ENOSYS 38 /* Function not implemented */ +#define ENOTEMPTY 39 /* Directory not empty */ +#define ELOOP 40 /* Too many symbolic links encountered */ +#define EWOULDBLOCK EAGAIN /* Operation would block */ +#define ENOMSG 42 /* No message of desired type */ +#define EIDRM 43 /* Identifier removed */ +#define ECHRNG 44 /* Channel number out of range */ +#define EL2NSYNC 45 /* Level 2 not synchronized */ +#define EL3HLT 46 /* Level 3 halted */ +#define EL3RST 47 /* Level 3 reset */ +#define ELNRNG 48 /* Link number out of range */ +#define EUNATCH 49 /* Protocol driver not attached */ +#define ENOCSI 50 /* No CSI structure available */ +#define EL2HLT 51 /* Level 2 halted */ +#define EBADE 52 /* Invalid exchange */ +#define EBADR 53 /* Invalid request descriptor */ +#define EXFULL 54 /* Exchange full */ +#define ENOANO 55 /* No anode */ +#define EBADRQC 56 /* Invalid request code */ +#define EBADSLT 57 /* Invalid slot */ + +#define EDEADLOCK EDEADLK + +#define EBFONT 59 /* Bad font file format */ +#define ENOSTR 60 /* Device not a stream */ +#define ENODATA 61 /* No data available */ +#define ETIME 62 /* Timer expired */ +#define ENOSR 63 /* Out of streams resources */ +#define ENONET 64 /* Machine is not on the network */ +#define ENOPKG 65 /* Package not installed */ +#define EREMOTE 66 /* Object is remote */ +#define ENOLINK 67 /* Link has been severed */ +#define EADV 68 /* Advertise error */ +#define ESRMNT 69 /* Srmount error */ +#define ECOMM 70 /* Communication error on send */ +#define EPROTO 71 /* Protocol error */ +#define EMULTIHOP 72 /* Multihop attempted */ +#define EDOTDOT 73 /* RFS specific error */ +#define EBADMSG 74 /* Not a data message */ +#define EOVERFLOW 75 /* Value too large for defined data type */ +#define ENOTUNIQ 76 /* Name not unique on network */ +#define EBADFD 77 /* File descriptor in bad state */ +#define EREMCHG 78 /* Remote address changed */ +#define ELIBACC 79 /* Can not access a needed shared library */ +#define ELIBBAD 80 /* Accessing a corrupted shared library */ +#define ELIBSCN 81 /* .lib section in a.out corrupted */ +#define ELIBMAX 82 /* Attempting to link in too many shared libraries */ +#define ELIBEXEC 83 /* Cannot exec a shared library directly */ +// #define EILSEQ 84 /* Illegal byte sequence */ +#define ERESTART 85 /* Interrupted system call should be restarted */ +#define ESTRPIPE 86 /* Streams pipe error */ +#define EUSERS 87 /* Too many users */ +#define ENOTSOCK 88 /* Socket operation on non-socket */ +#define EDESTADDRREQ 89 /* Destination address required */ +#define EMSGSIZE 90 /* Message too long */ +#define EPROTOTYPE 91 /* Protocol wrong type for socket */ +#define ENOPROTOOPT 92 /* Protocol not available */ +#define EPROTONOSUPPORT 93 /* Protocol not supported */ +#define ESOCKTNOSUPPORT 94 /* Socket type not supported */ +#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ +#define EPFNOSUPPORT 96 /* Protocol family not supported */ +#define EAFNOSUPPORT 97 /* Address family not supported by protocol */ +#define EADDRINUSE 98 /* Address already in use */ +#define EADDRNOTAVAIL 99 /* Cannot assign requested address */ +#define ENETDOWN 100 /* Network is down */ +#define ENETUNREACH 101 /* Network is unreachable */ +#define ENETRESET 102 /* Network dropped connection because of reset */ +#define ECONNABORTED 103 /* Software caused connection abort */ +#define ECONNRESET 104 /* Connection reset by peer */ +#define ENOBUFS 105 /* No buffer space available */ +#define EISCONN 106 /* Transport endpoint is already connected */ +#define ENOTCONN 107 /* Transport endpoint is not connected */ +#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */ +#define ETOOMANYREFS 109 /* Too many references: cannot splice */ +#define ETIMEDOUT 110 /* Connection timed out */ +#define ECONNREFUSED 111 /* Connection refused */ +#define EHOSTDOWN 112 /* Host is down */ +#define EHOSTUNREACH 113 /* No route to host */ +#define EALREADY 114 /* Operation already in progress */ +#define EINPROGRESS 115 /* Operation now in progress */ +#define ESTALE 116 /* Stale NFS file handle */ +#define EUCLEAN 117 /* Structure needs cleaning */ +#define ENOTNAM 118 /* Not a XENIX named type file */ +#define ENAVAIL 119 /* No XENIX semaphores available */ +#define EISNAM 120 /* Is a named type file */ +#define EREMOTEIO 121 /* Remote I/O error */ +#define EDQUOT 122 /* Quota exceeded */ + +#define ENOMEDIUM 123 /* No medium found */ +#define EMEDIUMTYPE 124 /* Wrong medium type */ + + +#define ENSROK 0 /* DNS server returned answer with no data */ +#define ENSRNODATA 160 /* DNS server returned answer with no data */ +#define ENSRFORMERR 161 /* DNS server claims query was misformatted */ +#define ENSRSERVFAIL 162 /* DNS server returned general failure */ +#define ENSRNOTFOUND 163 /* Domain name not found */ +#define ENSRNOTIMP 164 /* DNS server does not implement requested operation */ +#define ENSRREFUSED 165 /* DNS server refused query */ +#define ENSRBADQUERY 166 /* Misformatted DNS query */ +#define ENSRBADNAME 167 /* Misformatted domain name */ +#define ENSRBADFAMILY 168 /* Unsupported address family */ +#define ENSRBADRESP 169 /* Misformatted DNS reply */ +#define ENSRCONNREFUSED 170 /* Could not contact DNS servers */ +#define ENSRTIMEOUT 171 /* Timeout while contacting DNS servers */ +#define ENSROF 172 /* End of file */ +#define ENSRFILE 173 /* Error reading file */ +#define ENSRNOMEM 174 /* Out of memory */ +#define ENSRDESTRUCTION 175 /* Application terminated lookup */ +#define ENSRQUERYDOMAINTOOLONG 176 /* Domain name is too long */ +#define ENSRCNAMELOOP 177 /* Domain name is too long */ + +#endif // __LWIP_ERRNO_H_ diff --git a/20080212/Demo/ARM9_STR91X_IAR/lwip/include/arch/perf.h b/20080212/Demo/ARM9_STR91X_IAR/lwip/include/arch/perf.h new file mode 100644 index 000000000..68afdb56f --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/lwip/include/arch/perf.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __PERF_H__ +#define __PERF_H__ + +#define PERF_START /* null definition */ +#define PERF_STOP(x) /* null definition */ + +#endif /* __PERF_H__ */ diff --git a/20080212/Demo/ARM9_STR91X_IAR/lwip/include/arch/sys_arch.h b/20080212/Demo/ARM9_STR91X_IAR/lwip/include/arch/sys_arch.h new file mode 100644 index 000000000..6320c7f01 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/lwip/include/arch/sys_arch.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __SYS_RTXC_H__ +#define __SYS_RTXC_H__ + +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "semphr.h" + +#define SYS_MBOX_NULL (xQueueHandle)0 +#define SYS_SEM_NULL (xSemaphoreHandle)0 +#define SYS_DEFAULT_THREAD_STACK_DEPTH configMINIMAL_STACK_SIZE + +typedef xSemaphoreHandle sys_sem_t; +typedef xQueueHandle sys_mbox_t; +typedef xTaskHandle sys_thread_t; + +typedef struct _sys_arch_state_t +{ + // Task creation data. + portCHAR cTaskName[configMAX_TASK_NAME_LEN]; + unsigned portSHORT nStackDepth; + unsigned short nTaskCount; +} sys_arch_state_t; + +//extern sys_arch_state_t s_sys_arch_state; + +void sys_set_default_state(); +void sys_set_state(signed portCHAR *pTaskName, unsigned portSHORT nStackSize); + +#endif /* __SYS_RTXC_H__ */ + diff --git a/20080212/Demo/ARM9_STR91X_IAR/lwip/include/lwIPWebServer/BasicWEB.h b/20080212/Demo/ARM9_STR91X_IAR/lwip/include/lwIPWebServer/BasicWEB.h new file mode 100644 index 000000000..e5a8a7791 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/lwip/include/lwIPWebServer/BasicWEB.h @@ -0,0 +1,90 @@ +/* + FreeRTOS.org V4.7.0 - copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +#ifndef BASIC_WEB_SERVER_H +#define BASIC_WEB_SERVER_H + +#include <91x_type.h> + +/*------------------------------------------------------------------------------*/ +/* MACROS */ +/*------------------------------------------------------------------------------*/ +#define basicwebWEBSERVER_PRIORITY ( tskIDLE_PRIORITY + 2 ) + +/* The port on which we listen. */ +#define webHTTP_PORT ( 80 ) + +/* Delay on close error. */ +#define webSHORT_DELAY ( 10 / portTICK_RATE_MS ) + +/* The IP address being used. */ +#define emacIPADDR0 172 +#define emacIPADDR1 25 +#define emacIPADDR2 218 +#define emacIPADDR3 17 + +/* The gateway address being used. */ +#define emacGATEWAY_ADDR0 10 +#define emacGATEWAY_ADDR1 52 +#define emacGATEWAY_ADDR2 156 +#define emacGATEWAY_ADDR3 254 + +/* The network mask being used. */ +#define emacNET_MASK0 255 +#define emacNET_MASK1 255 +#define emacNET_MASK2 255 +#define emacNET_MASK3 0 + +#define STATIC_IP 1 +#define DHCP_IP 2 + +#define lwipBASIC_SERVER_STACK_SIZE 250 + +/*------------------------------------------------------------------------------*/ +/* PROTOTYPES */ +/*------------------------------------------------------------------------------*/ +/* The function that implements the WEB server task. */ +void vBasicWEBServer( void *pvParameters ); + +/* Initialisation required by lwIP. */ +void vlwIPInit( void ); + +void PrintIPOnLCD(unsigned int ipAddr); + +void ToDoAfterGettingIP(bool dhcpStaticFlag); + +void InitializeStaticIP(void); + +void DelayForDHCPToCome(void); + +#endif + diff --git a/20080212/Demo/ARM9_STR91X_IAR/lwip/include/lwIPWebServer/fs.h b/20080212/Demo/ARM9_STR91X_IAR/lwip/include/lwIPWebServer/fs.h new file mode 100644 index 000000000..dc848a12f --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/lwip/include/lwIPWebServer/fs.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels <adam@sics.se> + * + */ +#ifndef __FS_H__ +#define __FS_H__ + +struct fs_file { + char *data; + int len; +}; + +/* file must be allocated by caller and will be filled in + by the function. */ +int fs_open(char *name, struct fs_file *file); + +#endif /* __FS_H__ */ + diff --git a/20080212/Demo/ARM9_STR91X_IAR/lwip/include/lwIPWebServer/fsdata.h b/20080212/Demo/ARM9_STR91X_IAR/lwip/include/lwIPWebServer/fsdata.h new file mode 100644 index 000000000..a8cbc84a5 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/lwip/include/lwIPWebServer/fsdata.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels <adam@sics.se> + * + */ +#ifndef __FSDATA_H__ +#define __FSDATA_H__ + +struct httpd_fsdata_file { + const struct httpd_fsdata_file *next; + const unsigned char *name; + const unsigned char *data; + const int len; +}; + +struct httpd_fsdata_file_noconst { + struct httpd_fsdata_file *next; + unsigned char *name; + unsigned char *data; + int len; +}; + +#endif /* __FSDATA_H__ */ + diff --git a/20080212/Demo/ARM9_STR91X_IAR/lwip/include/lwIPWebServer/httpd.h b/20080212/Demo/ARM9_STR91X_IAR/lwip/include/lwIPWebServer/httpd.h new file mode 100644 index 000000000..60f74a9ab --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/lwip/include/lwIPWebServer/httpd.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels <adam@sics.se> + * + */ +#ifndef __HTTPD_H__ +#define __HTTPD_H__ + +void httpd_init(void); + +#endif /* __HTTPD_H__ */ + diff --git a/20080212/Demo/ARM9_STR91X_IAR/lwip/include/lwip/lwipopts.h b/20080212/Demo/ARM9_STR91X_IAR/lwip/include/lwip/lwipopts.h new file mode 100644 index 000000000..6fb319d25 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/lwip/include/lwip/lwipopts.h @@ -0,0 +1,194 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIPOPTS_H__ +#define __LWIPOPTS_H__ + +#define LWIP_NOASSERT 1 // To suppress some errors for now (no debug output) +#define SYS_LIGHTWEIGHT_PROT 1 + +#define TCPIP_THREAD_PRIO 3 + +#define ETH_PAD_SIZE 2 + +/* ---------- Memory options ---------- */ +/* MEM_ALIGNMENT: should be set to the alignment of the CPU for which + lwIP is compiled. 4 byte alignment -> define MEM_ALIGNMENT to 4, 2 + byte alignment -> define MEM_ALIGNMENT to 2. */ +#define MEM_ALIGNMENT 4 + +/* MEM_SIZE: the size of the heap memory. If the application will send +a lot of data that needs to be copied, this should be set high. */ +#define MEM_SIZE 8000 + +/* MEMP_NUM_PBUF: the number of memp struct pbufs. If the application + sends a lot of data out of ROM (or other static memory), this + should be set high. */ +#define MEMP_NUM_PBUF 40 +/* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One + per active UDP "connection". */ +#define MEMP_NUM_UDP_PCB 4 +/* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP + connections. */ +#define MEMP_NUM_TCP_PCB 10 +/* MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP + connections. */ +#define MEMP_NUM_TCP_PCB_LISTEN 8 +/* MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP + segments. */ +#define MEMP_NUM_TCP_SEG 8 +/* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active + timeouts. */ +#define MEMP_NUM_SYS_TIMEOUT 3 + + +/* The following four are used only with the sequential API and can be + set to 0 if the application only will use the raw API. */ +/* MEMP_NUM_NETBUF: the number of struct netbufs. */ +#define MEMP_NUM_NETBUF 4 +/* MEMP_NUM_NETCONN: the number of struct netconns. */ +#define MEMP_NUM_NETCONN 4 +/* MEMP_NUM_APIMSG: the number of struct api_msg, used for + communication between the TCP/IP stack and the sequential + programs. */ +#define MEMP_NUM_API_MSG 8 +/* MEMP_NUM_TCPIPMSG: the number of struct tcpip_msg, which is used + for sequential API communication and incoming packets. Used in + src/api/tcpip.c. */ +#define MEMP_NUM_TCPIP_MSG 8 + +/* These two control is reclaimer functions should be compiled + in. Should always be turned on (1). */ +#define MEM_RECLAIM 1 +#define MEMP_RECLAIM 1 + +/* ---------- Pbuf options ---------- */ +/* PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */ +#define PBUF_POOL_SIZE 8 + +/* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */ +#define PBUF_POOL_BUFSIZE 1500 + +/* PBUF_LINK_HLEN: the number of bytes that should be allocated for a + link level header. */ +#define PBUF_LINK_HLEN 16 + +/* ---------- TCP options ---------- */ +#define LWIP_TCP 1 +#define TCP_TTL 255 + +/* Controls if TCP should queue segments that arrive out of + order. Define to 0 if your device is low on memory. */ +#define TCP_QUEUE_OOSEQ 1 + +/* TCP Maximum segment size. */ +#define TCP_MSS 1500 + +/* TCP sender buffer space (bytes). */ +#define TCP_SND_BUF 1500 + +/* TCP sender buffer space (pbufs). This must be at least = 2 * + TCP_SND_BUF/TCP_MSS for things to work. */ +#define TCP_SND_QUEUELEN 6 * TCP_SND_BUF/TCP_MSS + +/* TCP receive window. */ +#define TCP_WND 1500 + +/* Maximum number of retransmissions of data segments. */ +#define TCP_MAXRTX 12 + +/* Maximum number of retransmissions of SYN segments. */ +#define TCP_SYNMAXRTX 4 + +/* ---------- ARP options ---------- */ +#define ARP_TABLE_SIZE 10 +#define ARP_QUEUEING 1 + +/* ---------- IP options ---------- */ +/* Define IP_FORWARD to 1 if you wish to have the ability to forward + IP packets across network interfaces. If you are going to run lwIP + on a device with only one network interface, define this to 0. */ +#define IP_FORWARD 1 + +/* If defined to 1, IP options are allowed (but not parsed). If + defined to 0, all packets with IP options are dropped. */ +#define IP_OPTIONS 1 + +/** IP reassembly and segmentation. Even if they both deal with IP + * fragments, note that these are orthogonal, one dealing with incoming + * packets, the other with outgoing packets + */ + +/** Reassemble incoming fragmented IP packets */ +#define IP_REASSEMBLY 0 + +/** Fragment outgoing IP packets if their size exceeds MTU */ +#define IP_FRAG 1 + +/* IP reassemly default age in seconds */ +#define IP_REASS_MAXAGE 30 + + +/* ---------- ICMP options ---------- */ +#define ICMP_TTL 255 + + +/* ---------- DHCP options ---------- */ +/* Define LWIP_DHCP to 1 if you want DHCP configuration of + interfaces. DHCP is not implemented in lwIP 0.5.1, however, so + turning this on does currently not work. */ +#define LWIP_DHCP 0 + +/* 1 if you want to do an ARP check on the offered address + (recommended). */ +#define DHCP_DOES_ARP_CHECK 1 + +/* ---------- UDP options ---------- */ +#define LWIP_UDP 1 +#define UDP_TTL 255 + + +/* ---------- Statistics options ---------- */ +#define STATS + +#ifdef STATS +#define LINK_STATS 1 +#define IP_STATS 1 +#define ICMP_STATS 1 +#define UDP_STATS 1 +#define TCP_STATS 1 +#define MEM_STATS 1 +#define MEMP_STATS 1 +#define PBUF_STATS 1 +#define SYS_STATS 1 +#endif /* STATS */ + +#endif /* __LWIPOPTS_H__ */ diff --git a/20080212/Demo/ARM9_STR91X_IAR/lwip/include/lwip/opt.h b/20080212/Demo/ARM9_STR91X_IAR/lwip/include/lwip/opt.h new file mode 100644 index 000000000..48b999629 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/lwip/include/lwip/opt.h @@ -0,0 +1,722 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_OPT_H__ +#define __LWIP_OPT_H__ + +/* Include user defined options first */ +#include "lwipopts.h" +#include "lwip/debug.h" + +/* Define default values for unconfigured parameters. */ + +/* Platform specific locking */ + +/* + * enable SYS_LIGHTWEIGHT_PROT in lwipopts.h if you want inter-task protection + * for certain critical regions during buffer allocation, deallocation and memory + * allocation and deallocation. + */ +#ifndef SYS_LIGHTWEIGHT_PROT +#define SYS_LIGHTWEIGHT_PROT 0 +#endif + +#ifndef NO_SYS +#define NO_SYS 0 +#endif +/* ---------- Memory options ---------- */ +#ifndef MEM_LIBC_MALLOC +#define MEM_LIBC_MALLOC 0 +#endif + +/* MEM_ALIGNMENT: should be set to the alignment of the CPU for which + lwIP is compiled. 4 byte alignment -> define MEM_ALIGNMENT to 4, 2 + byte alignment -> define MEM_ALIGNMENT to 2. */ + +#ifndef MEM_ALIGNMENT +#define MEM_ALIGNMENT 1 +#endif + +/* MEM_SIZE: the size of the heap memory. If the application will send +a lot of data that needs to be copied, this should be set high. */ +#ifndef MEM_SIZE +#define MEM_SIZE 1600 +#endif + +#ifndef MEMP_SANITY_CHECK +#define MEMP_SANITY_CHECK 0 +#endif + +/* MEMP_NUM_PBUF: the number of memp struct pbufs. If the application + sends a lot of data out of ROM (or other static memory), this + should be set high. */ +#ifndef MEMP_NUM_PBUF +#define MEMP_NUM_PBUF 16 +#endif + +/* Number of raw connection PCBs */ +#ifndef MEMP_NUM_RAW_PCB +#define MEMP_NUM_RAW_PCB 4 +#endif + +/* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One + per active UDP "connection". */ +#ifndef MEMP_NUM_UDP_PCB +#define MEMP_NUM_UDP_PCB 4 +#endif +/* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP + connections. */ +#ifndef MEMP_NUM_TCP_PCB +#define MEMP_NUM_TCP_PCB 5 +#endif +/* MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP + connections. */ +#ifndef MEMP_NUM_TCP_PCB_LISTEN +#define MEMP_NUM_TCP_PCB_LISTEN 8 +#endif +/* MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP + segments. */ +#ifndef MEMP_NUM_TCP_SEG +#define MEMP_NUM_TCP_SEG 16 +#endif +/* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active + timeouts. */ +#ifndef MEMP_NUM_SYS_TIMEOUT +#define MEMP_NUM_SYS_TIMEOUT 3 +#endif + +/* The following four are used only with the sequential API and can be + set to 0 if the application only will use the raw API. */ +/* MEMP_NUM_NETBUF: the number of struct netbufs. */ +#ifndef MEMP_NUM_NETBUF +#define MEMP_NUM_NETBUF 2 +#endif +/* MEMP_NUM_NETCONN: the number of struct netconns. */ +#ifndef MEMP_NUM_NETCONN +#define MEMP_NUM_NETCONN 4 +#endif +/* MEMP_NUM_APIMSG: the number of struct api_msg, used for + communication between the TCP/IP stack and the sequential + programs. */ +#ifndef MEMP_NUM_API_MSG +#define MEMP_NUM_API_MSG 8 +#endif +/* MEMP_NUM_TCPIPMSG: the number of struct tcpip_msg, which is used + for sequential API communication and incoming packets. Used in + src/api/tcpip.c. */ +#ifndef MEMP_NUM_TCPIP_MSG +#define MEMP_NUM_TCPIP_MSG 8 +#endif + +/* ---------- Pbuf options ---------- */ +/* PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */ + +#ifndef PBUF_POOL_SIZE +#define PBUF_POOL_SIZE 16 +#endif + +/* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */ + +#ifndef PBUF_POOL_BUFSIZE +#define PBUF_POOL_BUFSIZE 128 +#endif + +/* PBUF_LINK_HLEN: the number of bytes that should be allocated for a + link level header. Defaults to 14 for Ethernet. */ + +#ifndef PBUF_LINK_HLEN +#define PBUF_LINK_HLEN 14 +#endif + + + +/* ---------- ARP options ---------- */ + +/** Number of active hardware address, IP address pairs cached */ +#ifndef ARP_TABLE_SIZE +#define ARP_TABLE_SIZE 10 +#endif + +/** + * If enabled, outgoing packets are queued during hardware address + * resolution. + * + * This feature has not stabilized yet. Single-packet queueing is + * believed to be stable, multi-packet queueing is believed to + * clash with the TCP segment queueing. + * + * As multi-packet-queueing is currently disabled, enabling this + * _should_ work, but we need your testing feedback on lwip-users. + * + */ +#ifndef ARP_QUEUEING +#define ARP_QUEUEING 1 +#endif + +/* This option is deprecated */ +#ifdef ETHARP_QUEUE_FIRST +#error ETHARP_QUEUE_FIRST option is deprecated. Remove it from your lwipopts.h. +#endif + +/* This option is removed to comply with the ARP standard */ +#ifdef ETHARP_ALWAYS_INSERT +#error ETHARP_ALWAYS_INSERT option is deprecated. Remove it from your lwipopts.h. +#endif + +/* ---------- IP options ---------- */ +/* Define IP_FORWARD to 1 if you wish to have the ability to forward + IP packets across network interfaces. If you are going to run lwIP + on a device with only one network interface, define this to 0. */ +#ifndef IP_FORWARD +#define IP_FORWARD 0 +#endif + +/* If defined to 1, IP options are allowed (but not parsed). If + defined to 0, all packets with IP options are dropped. */ +#ifndef IP_OPTIONS +#define IP_OPTIONS 1 +#endif + +/** IP reassembly and segmentation. Even if they both deal with IP + * fragments, note that these are orthogonal, one dealing with incoming + * packets, the other with outgoing packets + */ + +/** Reassemble incoming fragmented IP packets */ +#ifndef IP_REASSEMBLY +#define IP_REASSEMBLY 1 +#endif + +/** Fragment outgoing IP packets if their size exceeds MTU */ +#ifndef IP_FRAG +#define IP_FRAG 1 +#endif + +/* IP reassemly default age in seconds */ +#ifndef IP_REASS_MAXAGE +#define IP_REASS_MAXAGE 3 +#endif + +/* IP reassembly buffer size (minus IP header) */ +#ifndef IP_REASS_BUFSIZE +#define IP_REASS_BUFSIZE 5760 +#endif + +/* Assumed max MTU on any interface for IP frag buffer */ +#ifndef IP_FRAG_MAX_MTU +#define IP_FRAG_MAX_MTU 1500 +#endif + +/** Global default value for Time To Live used by transport layers. */ +#ifndef IP_DEFAULT_TTL +#define IP_DEFAULT_TTL 255 +#endif + +/* ---------- ICMP options ---------- */ + +#ifndef ICMP_TTL +#define ICMP_TTL (IP_DEFAULT_TTL) +#endif + +/* ---------- RAW options ---------- */ + +#ifndef LWIP_RAW +#define LWIP_RAW 1 +#endif + +#ifndef RAW_TTL +#define RAW_TTL (IP_DEFAULT_TTL) +#endif + +/* ---------- DHCP options ---------- */ + +#ifndef LWIP_DHCP +#define LWIP_DHCP 0 +#endif + +/* 1 if you want to do an ARP check on the offered address + (recommended). */ +#ifndef DHCP_DOES_ARP_CHECK +#define DHCP_DOES_ARP_CHECK 1 +#endif + +/* ---------- SNMP options ---------- */ +/** @note UDP must be available for SNMP transport */ +#ifndef LWIP_SNMP +#define LWIP_SNMP 0 +#endif + +/** @note At least one request buffer is required. */ +#ifndef SNMP_CONCURRENT_REQUESTS +#define SNMP_CONCURRENT_REQUESTS 1 +#endif + +/** @note At least one trap destination is required */ +#ifndef SNMP_TRAP_DESTINATIONS +#define SNMP_TRAP_DESTINATIONS 1 +#endif + +#ifndef SNMP_PRIVATE_MIB +#define SNMP_PRIVATE_MIB 0 +#endif + +/* ---------- UDP options ---------- */ +#ifndef LWIP_UDP +#define LWIP_UDP 1 +#endif + +#ifndef UDP_TTL +#define UDP_TTL (IP_DEFAULT_TTL) +#endif + +/* ---------- TCP options ---------- */ +#ifndef LWIP_TCP +#define LWIP_TCP 1 +#endif + +#ifndef TCP_TTL +#define TCP_TTL (IP_DEFAULT_TTL) +#endif + +#ifndef TCP_WND +#define TCP_WND 2048 +#endif + +#ifndef TCP_MAXRTX +#define TCP_MAXRTX 12 +#endif + +#ifndef TCP_SYNMAXRTX +#define TCP_SYNMAXRTX 6 +#endif + + +/* Controls if TCP should queue segments that arrive out of + order. Define to 0 if your device is low on memory. */ +#ifndef TCP_QUEUE_OOSEQ +#define TCP_QUEUE_OOSEQ 1 +#endif + +/* TCP Maximum segment size. */ +#ifndef TCP_MSS +#define TCP_MSS 128 /* A *very* conservative default. */ +#endif + +/* TCP sender buffer space (bytes). */ +#ifndef TCP_SND_BUF +#define TCP_SND_BUF 256 +#endif + +/* TCP sender buffer space (pbufs). This must be at least = 2 * + TCP_SND_BUF/TCP_MSS for things to work. */ +#ifndef TCP_SND_QUEUELEN +#define TCP_SND_QUEUELEN 4 * TCP_SND_BUF/TCP_MSS +#endif + + +/* Maximum number of retransmissions of data segments. */ + +/* Maximum number of retransmissions of SYN segments. */ + +/* TCP writable space (bytes). This must be less than or equal + to TCP_SND_BUF. It is the amount of space which must be + available in the tcp snd_buf for select to return writable */ +#ifndef TCP_SNDLOWAT +#define TCP_SNDLOWAT TCP_SND_BUF/2 +#endif + +/* Support loop interface (127.0.0.1) */ +#ifndef LWIP_HAVE_LOOPIF +#define LWIP_HAVE_LOOPIF 0 +#endif + +#ifndef LWIP_EVENT_API +#define LWIP_EVENT_API 0 +#define LWIP_CALLBACK_API 1 +#else +#define LWIP_EVENT_API 1 +#define LWIP_CALLBACK_API 0 +#endif + +#ifndef LWIP_COMPAT_SOCKETS +#define LWIP_COMPAT_SOCKETS 1 +#endif + + +#ifndef TCPIP_THREAD_PRIO +#define TCPIP_THREAD_PRIO 1 +#endif + +#ifndef SLIPIF_THREAD_PRIO +#define SLIPIF_THREAD_PRIO 1 +#endif + +#ifndef PPP_THREAD_PRIO +#define PPP_THREAD_PRIO 1 +#endif + +#ifndef DEFAULT_THREAD_PRIO +#define DEFAULT_THREAD_PRIO 1 +#endif + + +/* ---------- Socket Options ---------- */ +/* Enable SO_REUSEADDR and SO_REUSEPORT options */ +#ifdef SO_REUSE +/* I removed the lot since this was an ugly hack. It broke the raw-API. + It also came with many ugly goto's, Christiaan Simons. */ +#error "SO_REUSE currently unavailable, this was a hack" +#endif + + +/* ---------- Statistics options ---------- */ +#ifndef LWIP_STATS +#define LWIP_STATS 1 +#endif + +#if LWIP_STATS + +#ifndef LWIP_STATS_DISPLAY +#define LWIP_STATS_DISPLAY 0 +#endif + +#ifndef LINK_STATS +#define LINK_STATS 1 +#endif + +#ifndef IP_STATS +#define IP_STATS 1 +#endif + +#ifndef IPFRAG_STATS +#define IPFRAG_STATS 1 +#endif + +#ifndef ICMP_STATS +#define ICMP_STATS 1 +#endif + +#ifndef UDP_STATS +#define UDP_STATS 1 +#endif + +#ifndef TCP_STATS +#define TCP_STATS 1 +#endif + +#ifndef MEM_STATS +#define MEM_STATS 1 +#endif + +#ifndef MEMP_STATS +#define MEMP_STATS 1 +#endif + +#ifndef PBUF_STATS +#define PBUF_STATS 1 +#endif + +#ifndef SYS_STATS +#define SYS_STATS 1 +#endif + +#ifndef RAW_STATS +#define RAW_STATS 0 +#endif + +#else + +#define LINK_STATS 0 +#define IP_STATS 0 +#define IPFRAG_STATS 0 +#define ICMP_STATS 0 +#define UDP_STATS 0 +#define TCP_STATS 0 +#define MEM_STATS 0 +#define MEMP_STATS 0 +#define PBUF_STATS 0 +#define SYS_STATS 0 +#define RAW_STATS 0 +#define LWIP_STATS_DISPLAY 0 + +#endif /* LWIP_STATS */ + +/* ---------- PPP options ---------- */ + +#ifndef PPP_SUPPORT +#define PPP_SUPPORT 0 /* Set for PPP */ +#endif + +#if PPP_SUPPORT + +#define NUM_PPP 1 /* Max PPP sessions. */ + + + +#ifndef PAP_SUPPORT +#define PAP_SUPPORT 0 /* Set for PAP. */ +#endif + +#ifndef CHAP_SUPPORT +#define CHAP_SUPPORT 0 /* Set for CHAP. */ +#endif + +#define MSCHAP_SUPPORT 0 /* Set for MSCHAP (NOT FUNCTIONAL!) */ +#define CBCP_SUPPORT 0 /* Set for CBCP (NOT FUNCTIONAL!) */ +#define CCP_SUPPORT 0 /* Set for CCP (NOT FUNCTIONAL!) */ + +#ifndef VJ_SUPPORT +#define VJ_SUPPORT 0 /* Set for VJ header compression. */ +#endif + +#ifndef MD5_SUPPORT +#define MD5_SUPPORT 0 /* Set for MD5 (see also CHAP) */ +#endif + + +/* + * Timeouts. + */ +#define FSM_DEFTIMEOUT 6 /* Timeout time in seconds */ +#define FSM_DEFMAXTERMREQS 2 /* Maximum Terminate-Request transmissions */ +#define FSM_DEFMAXCONFREQS 10 /* Maximum Configure-Request transmissions */ +#define FSM_DEFMAXNAKLOOPS 5 /* Maximum number of nak loops */ + +#define UPAP_DEFTIMEOUT 6 /* Timeout (seconds) for retransmitting req */ +#define UPAP_DEFREQTIME 30 /* Time to wait for auth-req from peer */ + +#define CHAP_DEFTIMEOUT 6 /* Timeout time in seconds */ +#define CHAP_DEFTRANSMITS 10 /* max # times to send challenge */ + + +/* Interval in seconds between keepalive echo requests, 0 to disable. */ +#if 1 +#define LCP_ECHOINTERVAL 0 +#else +#define LCP_ECHOINTERVAL 10 +#endif + +/* Number of unanswered echo requests before failure. */ +#define LCP_MAXECHOFAILS 3 + +/* Max Xmit idle time (in jiffies) before resend flag char. */ +#define PPP_MAXIDLEFLAG 100 + +/* + * Packet sizes + * + * Note - lcp shouldn't be allowed to negotiate stuff outside these + * limits. See lcp.h in the pppd directory. + * (XXX - these constants should simply be shared by lcp.c instead + * of living in lcp.h) + */ +#define PPP_MTU 1500 /* Default MTU (size of Info field) */ +#if 0 +#define PPP_MAXMTU 65535 - (PPP_HDRLEN + PPP_FCSLEN) +#else +#define PPP_MAXMTU 1500 /* Largest MTU we allow */ +#endif +#define PPP_MINMTU 64 +#define PPP_MRU 1500 /* default MRU = max length of info field */ +#define PPP_MAXMRU 1500 /* Largest MRU we allow */ +#define PPP_DEFMRU 296 /* Try for this */ +#define PPP_MINMRU 128 /* No MRUs below this */ + + +#define MAXNAMELEN 256 /* max length of hostname or name for auth */ +#define MAXSECRETLEN 256 /* max length of password or secret */ + +#endif /* PPP_SUPPORT */ + +/* checksum options - set to zero for hardware checksum support */ + +#ifndef CHECKSUM_GEN_IP +#define CHECKSUM_GEN_IP 1 +#endif + +#ifndef CHECKSUM_GEN_UDP +#define CHECKSUM_GEN_UDP 1 +#endif + +#ifndef CHECKSUM_GEN_TCP +#define CHECKSUM_GEN_TCP 1 +#endif + +#ifndef CHECKSUM_CHECK_IP +#define CHECKSUM_CHECK_IP 1 +#endif + +#ifndef CHECKSUM_CHECK_UDP +#define CHECKSUM_CHECK_UDP 1 +#endif + +#ifndef CHECKSUM_CHECK_TCP +#define CHECKSUM_CHECK_TCP 1 +#endif + +/* Debugging options all default to off */ + +#ifndef DBG_TYPES_ON +#define DBG_TYPES_ON 0 +#endif + +#ifndef ETHARP_DEBUG +#define ETHARP_DEBUG DBG_OFF +#endif + +#ifndef NETIF_DEBUG +#define NETIF_DEBUG DBG_OFF +#endif + +#ifndef PBUF_DEBUG +#define PBUF_DEBUG DBG_OFF +#endif + +#ifndef API_LIB_DEBUG +#define API_LIB_DEBUG DBG_OFF +#endif + +#ifndef API_MSG_DEBUG +#define API_MSG_DEBUG DBG_OFF +#endif + +#ifndef SOCKETS_DEBUG +#define SOCKETS_DEBUG DBG_OFF +#endif + +#ifndef ICMP_DEBUG +#define ICMP_DEBUG DBG_OFF +#endif + +#ifndef INET_DEBUG +#define INET_DEBUG DBG_OFF +#endif + +#ifndef IP_DEBUG +#define IP_DEBUG DBG_OFF +#endif + +#ifndef IP_REASS_DEBUG +#define IP_REASS_DEBUG DBG_OFF +#endif + +#ifndef RAW_DEBUG +#define RAW_DEBUG DBG_OFF +#endif + +#ifndef MEM_DEBUG +#define MEM_DEBUG DBG_OFF +#endif + +#ifndef MEMP_DEBUG +#define MEMP_DEBUG DBG_OFF +#endif + +#ifndef SYS_DEBUG +#define SYS_DEBUG DBG_OFF +#endif + +#ifndef TCP_DEBUG +#define TCP_DEBUG DBG_OFF +#endif + +#ifndef TCP_INPUT_DEBUG +#define TCP_INPUT_DEBUG DBG_OFF +#endif + +#ifndef TCP_FR_DEBUG +#define TCP_FR_DEBUG DBG_OFF +#endif + +#ifndef TCP_RTO_DEBUG +#define TCP_RTO_DEBUG DBG_OFF +#endif + +#ifndef TCP_REXMIT_DEBUG +#define TCP_REXMIT_DEBUG DBG_OFF +#endif + +#ifndef TCP_CWND_DEBUG +#define TCP_CWND_DEBUG DBG_OFF +#endif + +#ifndef TCP_WND_DEBUG +#define TCP_WND_DEBUG DBG_OFF +#endif + +#ifndef TCP_OUTPUT_DEBUG +#define TCP_OUTPUT_DEBUG DBG_OFF +#endif + +#ifndef TCP_RST_DEBUG +#define TCP_RST_DEBUG DBG_OFF +#endif + +#ifndef TCP_QLEN_DEBUG +#define TCP_QLEN_DEBUG DBG_OFF +#endif + +#ifndef UDP_DEBUG +#define UDP_DEBUG DBG_OFF +#endif + +#ifndef TCPIP_DEBUG +#define TCPIP_DEBUG DBG_OFF +#endif + +#ifndef PPP_DEBUG +#define PPP_DEBUG DBG_OFF +#endif + +#ifndef SLIP_DEBUG +#define SLIP_DEBUG DBG_OFF +#endif + +#ifndef DHCP_DEBUG +#define DHCP_DEBUG DBG_OFF +#endif + +#ifndef SNMP_MSG_DEBUG +#define SNMP_MSG_DEBUG DBG_OFF +#endif + +#ifndef SNMP_MIB_DEBUG +#define SNMP_MIB_DEBUG DBG_OFF +#endif + +#ifndef DBG_MIN_LEVEL +#define DBG_MIN_LEVEL DBG_LEVEL_OFF +#endif + +#endif /* __LWIP_OPT_H__ */ + + + diff --git a/20080212/Demo/ARM9_STR91X_IAR/lwip/lwipWebServer/BasicWEB.c b/20080212/Demo/ARM9_STR91X_IAR/lwip/lwipWebServer/BasicWEB.c new file mode 100644 index 000000000..8903976c4 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/lwip/lwipWebServer/BasicWEB.c @@ -0,0 +1,121 @@ + +/* + FreeRTOS.org V4.7.0 - copyright (C) 2003-2006 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + Implements a simplistic WEB server. Every time a connection is made and + data is received a dynamic page that shows the current TCP/IP statistics + is generated and returned. The connection is then closed. +*/ + + +/*------------------------------------------------------------------------------*/ +/* PROTOTYPES */ +/*------------------------------------------------------------------------------*/ + +/* Standard includes. */ +#include +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Demo includes. */ +#include "BasicWEB.h" + +/* lwIP includes. */ +#include "lwip/api.h" +#include "lwip/tcpip.h" +#include "lwip/memp.h" +#include "lwip/stats.h" +#include "netif/loopif.h" +#include "lcd.h" +#include "httpd.h" + +#define lwipTCP_STACK_SIZE 600 + + +/*------------------------------------------------------------------------------*/ +/* GLOBALS */ +/*------------------------------------------------------------------------------*/ +static struct netif EMAC_if; + +/*------------------------------------------------------------------------------*/ +/* FUNCTIONS */ +/*------------------------------------------------------------------------------*/ + + +void vlwIPInit( void ) +{ + /* Initialize lwIP and its interface layer. */ + sys_init(); + mem_init(); + memp_init(); + pbuf_init(); + netif_init(); + ip_init(); + sys_set_state(( signed portCHAR * ) "lwIP", lwipTCP_STACK_SIZE); + tcpip_init( NULL, NULL ); + sys_set_default_state(); +} +/*------------------------------------------------------------*/ + +void vBasicWEBServer( void *pvParameters ) +{ +struct ip_addr xIpAddr, xNetMast, xGateway; +extern err_t ethernetif_init( struct netif *netif ); + + /* Parameters are not used - suppress compiler error. */ + ( void ) pvParameters; + + /* Create and configure the EMAC interface. */ + IP4_ADDR( &xIpAddr, emacIPADDR0, emacIPADDR1, emacIPADDR2, emacIPADDR3 ); + IP4_ADDR( &xNetMast, emacNET_MASK0, emacNET_MASK1, emacNET_MASK2, emacNET_MASK3 ); + IP4_ADDR( &xGateway, emacGATEWAY_ADDR0, emacGATEWAY_ADDR1, emacGATEWAY_ADDR2, emacGATEWAY_ADDR3 ); + netif_add( &EMAC_if, &xIpAddr, &xNetMast, &xGateway, NULL, ethernetif_init, tcpip_input ); + + /* make it the default interface */ + netif_set_default( &EMAC_if ); + + /* bring it up */ + netif_set_up(&EMAC_if); + + /* Initialize HTTP */ + httpd_init(); + + /* Nothing else to do. No point hanging around. */ + vTaskDelete( NULL ); +} + + diff --git a/20080212/Demo/ARM9_STR91X_IAR/lwip/lwipWebServer/fs.c b/20080212/Demo/ARM9_STR91X_IAR/lwip/lwipWebServer/fs.c new file mode 100644 index 000000000..677155c22 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/lwip/lwipWebServer/fs.c @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels <adam@sics.se> + * + */ +#include "lwip/def.h" +#include "fs.h" +#include "fsdata.h" +#include "fsdata.c" + +// Standard lib include +#include + +/*-----------------------------------------------------------------------------------*/ + + +/*-----------------------------------------------------------------------------------*/ +int +fs_open(char *name, struct fs_file *file) +{ + struct httpd_fsdata_file_noconst *f; + + for(f = (struct httpd_fsdata_file_noconst *)HTTPD_FS_ROOT; + f != NULL; + f = (struct httpd_fsdata_file_noconst *)f->next) { + if (!strcmp(name, (char *)f->name)) { + file->data = (char *)f->data; + file->len = f->len; + return 1; + } + } + return 0; +} +/*-----------------------------------------------------------------------------------*/ + diff --git a/20080212/Demo/ARM9_STR91X_IAR/lwip/lwipWebServer/fs/WS1/404.html b/20080212/Demo/ARM9_STR91X_IAR/lwip/lwipWebServer/fs/WS1/404.html new file mode 100644 index 000000000..43e7f4cad --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/lwip/lwipWebServer/fs/WS1/404.html @@ -0,0 +1,8 @@ + + +
+

404 - file not found

+

Go here instead.

+
+ + \ No newline at end of file diff --git a/20080212/Demo/ARM9_STR91X_IAR/lwip/lwipWebServer/fs/WS1/index.html b/20080212/Demo/ARM9_STR91X_IAR/lwip/lwipWebServer/fs/WS1/index.html new file mode 100644 index 000000000..a41dad2a3 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/lwip/lwipWebServer/fs/WS1/index.html @@ -0,0 +1,50 @@ + + + + FreeRTOS.org STR9 lwIP WEB server demo + + +




+ + FreeRTOS.org lwIP WEB server example running on an STR912 from STMicroelectronics. Page will refresh every 2 seconds (or there abouts).

+ + +
+ FreeRTOS.orgTM is a portable, open source, mini Real Time Kernel - a free to download and royalty free RTOS + that can be used in commercial applications. +

+ Ports exist for many different processor architectures and development tools. Each official port includes a pre-configured + example application demonstrating the kernel features, expediting learning, and permitting 'out of the box' development.

+ + Free support is provided by an active user community. + Commercial support along with a + full development service is also provided.

+ + SafeRTOSTM is a version that has been certified for use + in safety critical applications. It is a functionally similar product for which complete + IEC 61508 compliant development/safety lifecyle documentation is available + (conformance certified by TÜV SÜD, including compiler verification evidence). + While FreeRTOS.org does not contain the same safety features as SafeRTOS there is still commonality - allowing FreeRTOS.org to benefit directly from the + very rigorous SafeRTOS testing and validation activities. +

+ + Here are some reasons why FreeRTOS.org is a good choice for your next application - FreeRTOS.org... + +

    +
  • Provides one solution for many different architectures and development tools.
    • +
  • Is known to be reliable. Confidence is assured by the activities undertaken by the SafeRTOS sister project.
    • +
  • Is undergoing continuous active development.
    • +
  • Has a minimal ROM, RAM and processing overhead.
    • +
  • Is truly free for use in commercial applications (see license conditions for details).
    • +
  • Comes with a porting, platform development, or application development service should it be required.
    • +
  • Is well established with a large and ever growing user base.
    • +
  • Contains a pre-configured example for each port. No need to figure out how to setup a project - just download and compile!
    • +
  • Has an excellent and active free support forum.
    • +
  • Has the assurance that commercial support is available should it be required.
    • +
  • Provides ample documentation.
    • +
  • Is very scalable, simple and easy to use.
    • +
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+ u32_t left; + u8_t retries; +}; +#pragma pack() + +/*-----------------------------------------------------------------------------------*/ +void conn_err(void *arg, err_t err) +{ + struct http_state *hs; + + hs = arg; + mem_free(hs); +} +/*-----------------------------------------------------------------------------------*/ +static void +close_conn(struct tcp_pcb *pcb, struct http_state *hs) +{ + tcp_arg(pcb, NULL); + tcp_sent(pcb, NULL); + tcp_recv(pcb, NULL); + mem_free(hs); + tcp_close(pcb); +} +/*-----------------------------------------------------------------------------------*/ +static void +send_data(struct tcp_pcb *pcb, struct http_state *hs) +{ + err_t err; + u16_t len; + + /* We cannot send more data than space available in the send + buffer. */ + if (tcp_sndbuf(pcb) < hs->left) { + len = tcp_sndbuf(pcb); + } else { + len = hs->left; + } + + do { + err = tcp_write(pcb, hs->file, len, 0); + if (err == ERR_MEM) { + len /= 2; + } + } while (err == ERR_MEM && len > 1); + + if (err == ERR_OK) { + hs->file += len; + hs->left -= len; + /* } else { + printf("send_data: error %s len %d %d\n", lwip_strerr(err), len, tcp_sndbuf(pcb));*/ + } +} +/*-----------------------------------------------------------------------------------*/ +err_t http_poll(void *arg, struct tcp_pcb *pcb) +{ + struct http_state *hs; + + hs = arg; + + /* printf("Polll\n");*/ + if (hs == NULL) { + /* printf("Null, close\n");*/ + tcp_abort(pcb); + return ERR_ABRT; + } else { + ++hs->retries; + if (hs->retries == 4) { + tcp_abort(pcb); + return ERR_ABRT; + } + send_data(pcb, hs); + } + + return ERR_OK; +} +/*-----------------------------------------------------------------------------------*/ +err_t http_sent(void *arg, struct tcp_pcb *pcb, u16_t len) +{ + struct http_state *hs; + + hs = arg; + + hs->retries = 0; + + if (hs->left > 0) { + send_data(pcb, hs); + } else { + close_conn(pcb, hs); + } + + return ERR_OK; +} +/*-----------------------------------------------------------------------------------*/ +err_t http_recv(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err) +{ + int i; + char *data; + struct fs_file file; + struct http_state *hs; + + hs = arg; + + if (err == ERR_OK && p != NULL) { + + /* Inform TCP that we have taken the data. */ + tcp_recved(pcb, p->tot_len); + + if (hs->file == NULL) { + data = p->payload; + + if (strncmp(data, "GET ", 4) == 0) { + for(i = 0; i < 40; i++) { + if (((char *)data + 4)[i] == ' ' || + ((char *)data + 4)[i] == '\r' || + ((char *)data + 4)[i] == '\n') { + ((char *)data + 4)[i] = 0; + } + } + + if (*(char *)(data + 4) == '/' && + *(char *)(data + 5) == 0) { + fs_open("/index.html", &file); + } + else { + if (!fs_open((char *)data + 4, &file)) { + fs_open("/404.html", &file); + } + } + hs->file = file.data; + hs->left = file.len; + /* printf("data %p len %ld\n", hs->file, hs->left);*/ + + pbuf_free(p); + send_data(pcb, hs); + + /* Tell TCP that we wish be to informed of data that has been + successfully sent by a call to the http_sent() function. */ + tcp_sent(pcb, http_sent); + } else { + pbuf_free(p); + close_conn(pcb, hs); + } + } else { + pbuf_free(p); + } + } + + if (err == ERR_OK && p == NULL) { + close_conn(pcb, hs); + } + return ERR_OK; +} +/*-----------------------------------------------------------------------------------*/ +err_t http_accept(void *arg, struct tcp_pcb *pcb, err_t err) +{ + struct http_state *hs; + + tcp_setprio(pcb, TCP_PRIO_MIN); + + /* Allocate memory for the structure that holds the state of the + connection. */ + hs = mem_malloc(sizeof(struct http_state)); + + if (hs == NULL) { +// printf("http_accept: Out of memory\n"); + return ERR_MEM; + } + + /* Initialize the structure. */ + hs->file = NULL; + hs->left = 0; + hs->retries = 0; + + /* Tell TCP that this is the structure we wish to be passed for our + callbacks. */ + tcp_arg(pcb, hs); + + + /* Tell TCP that we wish to be informed of incoming data by a call + to the http_recv() function. */ + tcp_recv(pcb, http_recv); + + tcp_err(pcb, conn_err); + + tcp_poll(pcb, http_poll, 4); + + return ERR_OK; +} + +/*-----------------------------------------------------------------------------------*/ +void httpd_init(void) +{ + struct tcp_pcb *pcb; + + pcb = tcp_new(); + tcp_bind(pcb, NULL, 80); + pcb = tcp_listen(pcb); + tcp_accept(pcb, http_accept); +} +/*-----------------------------------------------------------------------------------*/ + diff --git a/20080212/Demo/ARM9_STR91X_IAR/lwip/netif/ethernetif.c b/20080212/Demo/ARM9_STR91X_IAR/lwip/netif/ethernetif.c new file mode 100644 index 000000000..8279e352b --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/lwip/netif/ethernetif.c @@ -0,0 +1,436 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +/* + * This file is a skeleton for developing Ethernet network interface + * drivers for lwIP. Add code to the low_level functions and do a + * search-and-replace for the word "ethernetif" to replace it with + * something that better describes your network interface. + */ + +#include "lwip/opt.h" +#include "lwip/def.h" +#include "lwip/mem.h" +#include "lwip/pbuf.h" +#include "lwip/sys.h" +#include + +#include "netif/etharp.h" +#include "91x_enet.h" + +// Standard library include +#include + +#define netifMTU ( 1500 ) +#define netifINTERFACE_TASK_STACK_SIZE ( 350 ) +#define netifINTERFACE_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define netifGUARD_BLOCK_TIME ( 250 ) +#define IFNAME0 'e' +#define IFNAME1 'm' + +/* The time to block waiting for input. */ +#define emacBLOCK_TIME_WAITING_FOR_INPUT ( ( portTickType ) 100 ) + +/* Interrupt status bit definition. */ +#define DMI_RX_CURRENT_DONE 0x8000 + +extern u8 TxBuff[1520]; + +static u8_t s_rxBuff[1520]; + +/* The semaphore used by the ISR to wake the lwIP task. */ +static xSemaphoreHandle s_xSemaphore = NULL; + +struct ethernetif { + struct eth_addr *ethaddr; + /* Add whatever per-interface state that is needed here. */ +}; + +static struct netif *s_pxNetIf = NULL; + +/* Forward declarations. */ +static err_t ethernetif_output(struct netif *netif, struct pbuf *p, struct ip_addr *ipaddr); +static void ethernetif_input( void * pvParameters ); +static void vEMACWaitForInput( void ); + + + +static void low_level_init(struct netif *netif) +{ + /* set MAC hardware address length */ + netif->hwaddr_len = 6; + + /* set MAC hardware address */ + netif->hwaddr[0] = MAC_ADDR0; + netif->hwaddr[1] = MAC_ADDR1; + netif->hwaddr[2] = MAC_ADDR2; + netif->hwaddr[3] = MAC_ADDR3; + netif->hwaddr[4] = MAC_ADDR4; + netif->hwaddr[5] = MAC_ADDR5; + + /* maximum transfer unit */ + netif->mtu = netifMTU; + + /* broadcast capability */ + netif->flags = NETIF_FLAG_BROADCAST; + + s_pxNetIf = netif; + + if( s_xSemaphore == NULL ) + { + vSemaphoreCreateBinary( s_xSemaphore ); + xSemaphoreTake( s_xSemaphore, 0); + } + + /* Do whatever else is needed to initialize interface. */ + /* Initialise the MAC. */ + ENET_InitClocksGPIO(); + ENET_Init(); + ENET_Start(); + + portENTER_CRITICAL(); + { + /*set MAC physical*/ + ENET_MAC->MAH = (MAC_ADDR5<<8) + MAC_ADDR4; + ENET_MAC->MAL = (MAC_ADDR3<<24) + (MAC_ADDR2<<16) + (MAC_ADDR1<<8) + MAC_ADDR0; + + VIC_Config( ENET_ITLine, VIC_IRQ, 1 ); + VIC_ITCmd( ENET_ITLine, ENABLE ); + ENET_DMA->ISR = DMI_RX_CURRENT_DONE; + ENET_DMA->IER = DMI_RX_CURRENT_DONE; + } + portEXIT_CRITICAL(); + + /* Create the task that handles the EMAC. */ + xTaskCreate( ethernetif_input, ( signed portCHAR * ) "ETH_INT", netifINTERFACE_TASK_STACK_SIZE, NULL, netifINTERFACE_TASK_PRIORITY, NULL ); +} + + +/* + * low_level_output(): + * + * Should do the actual transmission of the packet. The packet is + * contained in the pbuf that is passed to the function. This pbuf + * might be chained. + * + */ + +static err_t low_level_output(struct netif *netif, struct pbuf *p) +{ + static xSemaphoreHandle xTxSemaphore = NULL; + struct pbuf *q; + u32_t l = 0; + + if( xTxSemaphore == NULL ) + { + vSemaphoreCreateBinary( xTxSemaphore ); + } + + +#if ETH_PAD_SIZE + pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */ +#endif + + + /* Access to the EMAC is guarded using a semaphore. */ + if( xSemaphoreTake( xTxSemaphore, netifGUARD_BLOCK_TIME ) ) + { + for(q = p; q != NULL; q = q->next) { + /* Send the data from the pbuf to the interface, one pbuf at a + time. The size of the data in each pbuf is kept in the ->len + variable. */ + memcpy(&TxBuff[l], (u8_t*)q->payload, q->len); + l += q->len; + } + + ENET_TxPkt(0, l); + + #if ETH_PAD_SIZE + pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */ + #endif + + #if LINK_STATS + lwip_stats.link.xmit++; + #endif /* LINK_STATS */ + + xSemaphoreGive( xTxSemaphore ); + } + + return ERR_OK; +} + +/* + * low_level_input(): + * + * Should allocate a pbuf and transfer the bytes of the incoming + * packet from the interface into the pbuf. + * + */ + +static struct pbuf * +low_level_input(struct netif *netif) +{ + static xSemaphoreHandle xRxSemaphore = NULL; + struct pbuf *p, *q; + u16_t len, l; + + l = 0; + p = NULL; + + if( xRxSemaphore == NULL ) + { + vSemaphoreCreateBinary( xRxSemaphore ); + } + + /* Access to the emac is guarded using a semaphore. */ + if( xSemaphoreTake( xRxSemaphore, netifGUARD_BLOCK_TIME ) ) + { + /* Obtain the size of the packet and put it into the "len" + variable. */ + len = ENET_HandleRxPkt(s_rxBuff); + + if(len) + { + #if ETH_PAD_SIZE + len += ETH_PAD_SIZE; /* allow room for Ethernet padding */ + #endif + + /* We allocate a pbuf chain of pbufs from the pool. */ + p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL); + + if (p != NULL) { + + #if ETH_PAD_SIZE + pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */ + #endif + + /* We iterate over the pbuf chain until we have read the entire + * packet into the pbuf. */ + for(q = p; q != NULL; q = q->next) { + /* Read enough bytes to fill this pbuf in the chain. The + * available data in the pbuf is given by the q->len + * variable. */ + memcpy((u8_t*)q->payload, &s_rxBuff[l], q->len); + l = l + q->len; + } + + + #if ETH_PAD_SIZE + pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */ + #endif + + #if LINK_STATS + lwip_stats.link.recv++; + #endif /* LINK_STATS */ + } else { + #if LINK_STATS + lwip_stats.link.memerr++; + lwip_stats.link.drop++; + #endif /* LINK_STATS */ + } /* End else */ + } /* End if */ + + xSemaphoreGive( xRxSemaphore ); + } + + return p; +} + +/* + * ethernetif_output(): + * + * This function is called by the TCP/IP stack when an IP packet + * should be sent. It calls the function called low_level_output() to + * do the actual transmission of the packet. + * + */ + +static err_t ethernetif_output(struct netif *netif, struct pbuf *p, struct ip_addr *ipaddr) +{ + + /* resolve hardware address, then send (or queue) packet */ + return etharp_output(netif, ipaddr, p); + +} + +/* + * ethernetif_input(): + * + * This function should be called when a packet is ready to be read + * from the interface. It uses the function low_level_input() that + * should handle the actual reception of bytes from the network + * interface. + * + */ + +static void ethernetif_input( void * pvParameters ) +{ + struct ethernetif *ethernetif; + struct eth_hdr *ethhdr; + struct pbuf *p; + + for( ;; ) + { + do + { + ethernetif = s_pxNetIf->state; + + /* move received packet into a new pbuf */ + p = low_level_input( s_pxNetIf ); + + if( p == NULL ) + { + /* No packet could be read. Wait a for an interrupt to tell us + there is more data available. */ + vEMACWaitForInput(); + } + + } while( p == NULL ); + + /* points to packet payload, which starts with an Ethernet header */ + ethhdr = p->payload; + + #if LINK_STATS + lwip_stats.link.recv++; + #endif /* LINK_STATS */ + + ethhdr = p->payload; + + switch (htons(ethhdr->type)) + { + /* IP packet? */ + case ETHTYPE_IP: + /* update ARP table */ + etharp_ip_input(s_pxNetIf, p); + /* skip Ethernet header */ + pbuf_header(p, (s16_t)-sizeof(struct eth_hdr)); + /* pass to network layer */ + s_pxNetIf->input(p, s_pxNetIf); + break; + + case ETHTYPE_ARP: + /* pass p to ARP module */ + etharp_arp_input(s_pxNetIf, ethernetif->ethaddr, p); + break; + + default: + pbuf_free(p); + p = NULL; + break; + } + } +} + +static void +arp_timer(void *arg) +{ + etharp_tmr(); + sys_timeout(ARP_TMR_INTERVAL, arp_timer, NULL); +} + +/* + * ethernetif_init(): + * + * Should be called at the beginning of the program to set up the + * network interface. It calls the function low_level_init() to do the + * actual setup of the hardware. + * + */ + +err_t +ethernetif_init(struct netif *netif) +{ + struct ethernetif *ethernetif; + + ethernetif = mem_malloc(sizeof(struct ethernetif)); + + if (ethernetif == NULL) + { + LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_init: out of memory\n")); + return ERR_MEM; + } + +#if LWIP_SNMP + /* ifType ethernetCsmacd(6) @see RFC1213 */ + netif->link_type = 6; + /* your link speed here */ + netif->link_speed = ; + netif->ts = 0; + netif->ifinoctets = 0; + netif->ifinucastpkts = 0; + netif->ifinnucastpkts = 0; + netif->ifindiscards = 0; + netif->ifoutoctets = 0; + netif->ifoutucastpkts = 0; + netif->ifoutnucastpkts = 0; + netif->ifoutdiscards = 0; +#endif + + netif->state = ethernetif; + netif->name[0] = IFNAME0; + netif->name[1] = IFNAME1; + netif->output = ethernetif_output; + netif->linkoutput = low_level_output; + + ethernetif->ethaddr = (struct eth_addr *)&(netif->hwaddr[0]); + + low_level_init(netif); + + etharp_init(); + + sys_timeout(ARP_TMR_INTERVAL, arp_timer, NULL); + + return ERR_OK; +} +/*-----------------------------------------------------------*/ + +void ENET_IRQHandler(void) +{ +portBASE_TYPE xSwitchRequired; + + /* Give the semaphore in case the lwIP task needs waking. */ + xSwitchRequired = xSemaphoreGiveFromISR( s_xSemaphore, pdFALSE ); + + /* Clear the interrupt. */ + ENET_DMA->ISR = DMI_RX_CURRENT_DONE; + + /* Switch tasks if necessary. */ + portEND_SWITCHING_ISR( xSwitchRequired ); +} +/*-----------------------------------------------------------*/ + +void vEMACWaitForInput( void ) +{ + /* Just wait until we are signled from an ISR that data is available, or + we simply time out. */ + xSemaphoreTake( s_xSemaphore, emacBLOCK_TIME_WAITING_FOR_INPUT ); +} diff --git a/20080212/Demo/ARM9_STR91X_IAR/main.c b/20080212/Demo/ARM9_STR91X_IAR/main.c new file mode 100644 index 000000000..d74edf56a --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/main.c @@ -0,0 +1,459 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. + The processor MUST be in supervisor mode when vTaskStartScheduler is + called. The demo applications included in the FreeRTOS.org download switch + to supervisor mode prior to main being called. If you are not using one of + these demo application projects then ensure Supervisor mode is used. +*/ + +/* + * Creates all the demo application tasks, then starts the scheduler. The WEB + * documentation provides more details of the demo application tasks. + * + * A few tasks are created that are not part of the standard demo. These are + * the 'LCD' task, the 'LCD Message' task, a WEB server task and the 'Check' + * task. + * + * The LCD task is the only task that accesses the LCD directly, so mutual + * exclusion is ensured. Any task wishing to display text sends the LCD task + * a message containing a pointer to the string that should be displayed. + * The LCD task itself just blocks on a queue waiting for such a message to + * arrive - processing each in turn. + * + * The LCD Message task does nothing other than periodically send messages to + * the LCD task. The messages originating from the LCD Message task are + * displayed on the top row of the LCD. + * + * The Check task only executes every three seconds but has the highest + * priority so is guaranteed to get processor time. Its main function is to + * check that all the other tasks are still operational. Most tasks maintain + * a unique count that is incremented each time the task successfully completes + * a cycle of its function. Should any error occur within such a task the + * count is permanently halted. The check task sets a bit in an error status + * flag should it find any counter variable at a value that indicates an + * error has occurred. The error flag value is converted to a string and sent + * to the LCD task for display on the bottom row on the LCD. + */ + +/* Standard includes. */ +#include + +/* Library includes. */ +#include "91x_lib.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* Demo application includes. */ +#include "lcd.h" +#include "flash.h" +#include "integer.h" +#include "PollQ.h" +#include "BlockQ.h" +#include "semtest.h" +#include "dynamic.h" +#include "partest.h" +#include "flop.h" +#include "comtest2.h" +#include "serial.h" +#include "GenQTest.h" +#include "QPeek.h" + +#ifdef STACK_LWIP + #include "BasicWEB.h" + #include "sys.h" +#endif + +/* Priorities for the demo application tasks. */ +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainMSG_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainGENERIC_QUEUE_PRIORITY ( tskIDLE_PRIORITY ) + +/* Delays used by the various tasks defined in this file. */ +#define mainCHECK_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS ) +#define mainSTRING_WRITE_DELAY ( 500 / portTICK_RATE_MS ) +#define mainLCD_DELAY ( 20 / portTICK_RATE_MS ) + +/* Constants for the ComTest tasks. */ +#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 115200 ) +#define mainCOM_TEST_LED ( 3 ) + +/* The maximum number of messages that can be pending to be written to the LCD. */ +#define mainLCD_QUEUE_LEN ( 6 ) + +/* Dimension the buffer used to write the error flag string. */ +#define mainMAX_FLAG_STRING_LEN ( 32 ) + +/* The structure that is passed on the LCD message queue. */ +typedef struct +{ + portCHAR **ppcMessageToDisplay; /*<< Points to a char* pointing to the message to display. */ + portBASE_TYPE xRow; /*<< The row on which the message should be displayed. */ +} xLCDMessage; +/*-----------------------------------------------------------*/ + +/* + * The task that executes at the highest priority and calls + * prvCheckOtherTasksAreStillRunning(). See the description at the top + * of the file. + */ +static void vErrorChecks( void *pvParameters ); + +/* + * Configure the processor clock and ports. + */ +static void prvSetupHardware( void ); + +/* + * Checks that all the demo application tasks are still executing without error + * - as described at the top of the file. Called by vErrorChecks(). + */ +static void prvCheckOtherTasksAreStillRunning( void ); + +#ifdef STACK_UIP + /* + * The WEB server task prototype. The task is created in this file but defined + * elsewhere. STACK_UIP is defined when the uIP stack is used in preference + * to the lwIP stack. + */ + extern void vuIP_Task(void *pvParameters); +#endif + +/* + * The task that displays text on the LCD. + */ +static void prvLCDTask( void * pvParameters ); + +/* + * The task that sends messages to be displayed on the top row of the LCD. + */ +static void prvLCDMessageTask( void * pvParameters ); + +/*-----------------------------------------------------------*/ + +/* The queue used to pass messages to the LCD task. */ +static xQueueHandle xLCDQueue; + +/* Error status flag. */ +static unsigned portLONG ulErrorFlags = 0; + +/*-----------------------------------------------------------*/ + +/* + * Starts all the other tasks, then starts the scheduler. + */ +void main( void ) +{ + #ifdef DEBUG + debug(); + #endif + + /* Setup any hardware that has not already been configured by the low + level init routines. */ + prvSetupHardware(); + /* Create the queue used to send data to the LCD task. */ + xLCDQueue = xQueueCreate( mainLCD_QUEUE_LEN, sizeof( xLCDMessage ) ); + + /* Start all the standard demo application tasks. */ + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vStartDynamicPriorityTasks(); + vStartMathTasks( tskIDLE_PRIORITY ); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); + vStartGenericQueueTasks( mainGENERIC_QUEUE_PRIORITY ); + vStartQueuePeekTasks(); + + /* Start the tasks which are defined in this file. */ + xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + xTaskCreate( prvLCDTask, "LCD", configMINIMAL_STACK_SIZE, ( void * ) &xLCDQueue, mainLCD_TASK_PRIORITY, NULL ); + xTaskCreate( prvLCDMessageTask, "MSG", configMINIMAL_STACK_SIZE, ( void * ) &xLCDQueue, mainMSG_TASK_PRIORITY, NULL ); + + /* Start either the uIP TCP/IP stack or the lwIP TCP/IP stack. */ + #ifdef STACK_UIP + /* Finally, create the WEB server task. */ + xTaskCreate( vuIP_Task, "uIP", configMINIMAL_STACK_SIZE * 3, NULL, mainCHECK_TASK_PRIORITY - 1, NULL ); + #endif + + #ifdef STACK_LWIP + /* Create the lwIP task. This uses the lwIP RTOS abstraction layer.*/ + vlwIPInit(); + sys_set_state( ( signed portCHAR * ) "httpd", lwipBASIC_SERVER_STACK_SIZE ); + sys_thread_new( vBasicWEBServer, ( void * ) NULL, basicwebWEBSERVER_PRIORITY ); + sys_set_default_state(); + #endif + + /* Start the scheduler. + + NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. + The processor MUST be in supervisor mode when vTaskStartScheduler is + called. The demo applications included in the FreeRTOS.org download switch + to supervisor mode prior to main being called. If you are not using one of + these demo application projects then ensure Supervisor mode is used here. */ + + vTaskStartScheduler(); + + /* We should never get here as control is now taken by the scheduler. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Configuration taken from the ST code. + + Set Flash banks size & address */ + FMI_BankRemapConfig( 4, 2, 0, 0x80000 ); + + /* FMI Waite States */ + FMI_Config( FMI_READ_WAIT_STATE_2, FMI_WRITE_WAIT_STATE_0, FMI_PWD_ENABLE, FMI_LVD_ENABLE, FMI_FREQ_HIGH ); + + /* Configure the FPLL = 96MHz, and APB to 48MHz. */ + SCU_PCLKDivisorConfig( SCU_PCLK_Div2 ); + SCU_PLLFactorsConfig( 192, 25, 2 ); + SCU_PLLCmd( ENABLE ); + SCU_MCLKSourceConfig( SCU_MCLK_PLL ); + + WDG_Cmd( DISABLE ); + VIC_DeInit(); + + /* GPIO8 clock source enable, used by the LCD. */ + SCU_APBPeriphClockConfig(__GPIO8, ENABLE); + GPIO_DeInit(GPIO8); + + /* GPIO 9 clock source enable, used by the LCD. */ + SCU_APBPeriphClockConfig(__GPIO9, ENABLE); + GPIO_DeInit(GPIO9); + + /* Enable VIC clock */ + SCU_AHBPeriphClockConfig(__VIC, ENABLE); + SCU_AHBPeriphReset(__VIC, DISABLE); + + /* Peripheral initialisation. */ + vParTestInitialise(); +} +/*-----------------------------------------------------------*/ + +static void vErrorChecks( void *pvParameters ) +{ +static portCHAR cCheckVal[ mainMAX_FLAG_STRING_LEN ]; +portCHAR *pcFlagString; +xLCDMessage xMessageToSend; +portTickType xLastWakeTime; +portCHAR *pcStringsToDisplay[] = { + "Check status flag" + }; + + /* The parameters are not used in this task. */ + ( void ) pvParameters; + + pcFlagString = &cCheckVal[ 0 ]; + + /* Initialise xLastWakeTime to ensure the first call to vTaskDelayUntil() + functions correctly. */ + xLastWakeTime = xTaskGetTickCount(); + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. */ + for( ;; ) + { + /* Delay until it is time to execute again. */ + vTaskDelayUntil( &xLastWakeTime, mainCHECK_PERIOD ); + + /* Check all the other tasks to see if the error flag needs updating. */ + prvCheckOtherTasksAreStillRunning(); + + /* Create a string indicating the error flag status. */ + sprintf( cCheckVal, "equals 0x%x ", ulErrorFlags ); + xMessageToSend.xRow = Line2; + + /* Send the first part of the message to the LCD task. */ + xMessageToSend.ppcMessageToDisplay = &pcStringsToDisplay[ 0 ]; + xQueueSend( xLCDQueue, ( void * ) &xMessageToSend, 0 ); + vTaskDelay( mainSTRING_WRITE_DELAY ); + + /* Send the second part of the message to the LCD task. */ + xMessageToSend.ppcMessageToDisplay = &pcFlagString; + xQueueSend( xLCDQueue, ( void * ) &xMessageToSend, 0 ); + } +} +/*-----------------------------------------------------------*/ + +static void prvCheckOtherTasksAreStillRunning( void ) +{ + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + ulErrorFlags |= 0x01; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + ulErrorFlags |= 0x02; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFlags |= 0x04; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + ulErrorFlags |= 0x08; + } + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + ulErrorFlags |= 0x10; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + ulErrorFlags |= 0x20; + } + + if( xAreMathsTaskStillRunning() != pdTRUE ) + { + ulErrorFlags |= 0x40; + } + + if( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + ulErrorFlags |= 0x80; + } + + if( xAreQueuePeekTasksStillRunning() != pdTRUE ) + { + ulErrorFlags |= 0x100; + } + +} +/*-----------------------------------------------------------*/ + +static void prvLCDMessageTask( void * pvParameters ) +{ +xQueueHandle *pxLCDQueue; +xLCDMessage xMessageToSend; +portBASE_TYPE xIndex = 0; + +/* The strings that are written to the LCD. */ +portCHAR *pcStringsToDisplay[] = { + "IAR ", + "STR912 ", + "Demo ", + "www.FreeRTOS.org", + "" + }; + + + /* To test the parameter passing mechanism, the queue on which messages are + posted is passed in as a parameter even though it is available as a file + scope variable anyway. */ + pxLCDQueue = ( xQueueHandle * ) pvParameters; + + for( ;; ) + { + /* Wait until it is time to move onto the next string. */ + vTaskDelay( mainSTRING_WRITE_DELAY ); + + /* Configure the message object to send to the LCD task. */ + xMessageToSend.ppcMessageToDisplay = &pcStringsToDisplay[ xIndex ]; + xMessageToSend.xRow = Line1; + + /* Post the message to be displayed. */ + xQueueSend( *pxLCDQueue, ( void * ) &xMessageToSend, 0 ); + + /* Move onto the next message, wrapping when necessary. */ + xIndex++; + if( *( pcStringsToDisplay[ xIndex ] ) == 0x00 ) + { + xIndex = 0; + + /* Delay longer before going back to the start of the messages. */ + vTaskDelay( mainSTRING_WRITE_DELAY * 2 ); + } + } +} +/*-----------------------------------------------------------*/ + +void prvLCDTask( void * pvParameters ) +{ +xQueueHandle *pxLCDQueue; +xLCDMessage xReceivedMessage; +portCHAR *pcString; + + /* To test the parameter passing mechanism, the queue on which messages are + received is passed in as a parameter even though it is available as a file + scope variable anyway. */ + pxLCDQueue = ( xQueueHandle * ) pvParameters; + + LCD_Init(); + + for( ;; ) + { + /* Wait for a message to arrive. */ + if( xQueueReceive( *pxLCDQueue, &xReceivedMessage, portMAX_DELAY ) ) + { + /* Where is the string we are going to display? */ + pcString = *xReceivedMessage.ppcMessageToDisplay; + LCD_DisplayString(xReceivedMessage.xRow, pcString, BlackText); + + /* The delay here is just to ensure the LCD task does not starve + out lower priority tasks as writing to the LCD can take a long + time. */ + vTaskDelay( mainLCD_DELAY ); + } + } +} +/*-----------------------------------------------------------*/ diff --git a/20080212/Demo/ARM9_STR91X_IAR/serial/serial.c b/20080212/Demo/ARM9_STR91X_IAR/serial/serial.c new file mode 100644 index 000000000..cfc474a98 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/serial/serial.c @@ -0,0 +1,299 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART1. +*/ + +/* Library includes. */ +#include "91x_lib.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "queue.h" +#include "semphr.h" + +/* Demo application includes. */ +#include "serial.h" +/*-----------------------------------------------------------*/ + +/* Misc defines. */ +#define serINVALID_QUEUE ( ( xQueueHandle ) 0 ) +#define serNO_BLOCK ( ( portTickType ) 0 ) +#define serTX_BLOCK_TIME ( 40 / portTICK_RATE_MS ) + +/* Interrupt and status bit definitions. */ +#define mainTXRIS 0x20 +#define mainRXRIS 0x50 +#define serTX_FIFO_FULL 0x20 +#define serCLEAR_ALL_INTERRUPTS 0x3ff +/*-----------------------------------------------------------*/ + +/* The queue used to hold received characters. */ +static xQueueHandle xRxedChars; + +/* The semaphore used to wake a task waiting for space to become available +in the FIFO. */ +static xSemaphoreHandle xTxFIFOSemaphore; + +/*-----------------------------------------------------------*/ + +/* UART interrupt handler. */ +void UART1_IRQHandler( void ); + +/* The interrupt service routine - called from the assembly entry point. */ +__arm void UART1_IRQHandler( void ); + +/*-----------------------------------------------------------*/ + +/* Flag to indicate whether or not a task is blocked waiting for space on +the FIFO. */ +static portLONG lTaskWaiting = pdFALSE; + +/* + * See the serial2.h header file. + */ +xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) +{ +xComPortHandle xReturn; +UART_InitTypeDef xUART1_Init; +GPIO_InitTypeDef GPIO_InitStructure; + + /* Create the queues used to hold Rx characters. */ + xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + + /* Create the semaphore used to wake a task waiting for space to become + available in the FIFO. */ + vSemaphoreCreateBinary( xTxFIFOSemaphore ); + + /* If the queue/semaphore was created correctly then setup the serial port + hardware. */ + if( ( xRxedChars != serINVALID_QUEUE ) && ( xTxFIFOSemaphore != serINVALID_QUEUE ) ) + { + /* Pre take the semaphore so a task will block if it tries to access + it. */ + xSemaphoreTake( xTxFIFOSemaphore, 0 ); + + /* Configure the UART. */ + xUART1_Init.UART_WordLength = UART_WordLength_8D; + xUART1_Init.UART_StopBits = UART_StopBits_1; + xUART1_Init.UART_Parity = UART_Parity_No; + xUART1_Init.UART_BaudRate = ulWantedBaud; + xUART1_Init.UART_HardwareFlowControl = UART_HardwareFlowControl_None; + xUART1_Init.UART_Mode = UART_Mode_Tx_Rx; + xUART1_Init.UART_FIFO = UART_FIFO_Enable; + + /* Enable the UART1 Clock */ + SCU_APBPeriphClockConfig( __UART1, ENABLE ); + + /* Enable the GPIO3 Clock */ + SCU_APBPeriphClockConfig( __GPIO3, ENABLE ); + + /* Configure UART1_Rx pin GPIO3.2 */ + GPIO_InitStructure.GPIO_Direction = GPIO_PinInput; + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_InitStructure.GPIO_Type = GPIO_Type_PushPull ; + GPIO_InitStructure.GPIO_IPConnected = GPIO_IPConnected_Enable; + GPIO_InitStructure.GPIO_Alternate = GPIO_InputAlt1 ; + GPIO_Init( GPIO3, &GPIO_InitStructure ); + + /* Configure UART1_Tx pin GPIO3.3 */ + GPIO_InitStructure.GPIO_Direction = GPIO_PinOutput; + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3; + GPIO_InitStructure.GPIO_Type = GPIO_Type_PushPull ; + GPIO_InitStructure.GPIO_IPConnected = GPIO_IPConnected_Enable; + GPIO_InitStructure.GPIO_Alternate = GPIO_OutputAlt2 ; + GPIO_Init( GPIO3, &GPIO_InitStructure ); + + + portENTER_CRITICAL(); + { + /* Configure the UART itself. */ + UART_DeInit( UART1 ); + UART_Init( UART1, &xUART1_Init ); + UART_ITConfig( UART1, UART_IT_Receive | UART_IT_Transmit, ENABLE ); + UART1->ICR = serCLEAR_ALL_INTERRUPTS; + UART_LoopBackConfig( UART1, DISABLE ); + UART_IrDACmd( IrDA1, DISABLE ); + + /* Configure the VIC for the UART interrupts. */ + VIC_Config( UART1_ITLine, VIC_IRQ, 9 ); + VIC_ITCmd( UART1_ITLine, ENABLE ); + + UART_Cmd( UART1, ENABLE ); + lTaskWaiting = pdFALSE; + } + portEXIT_CRITICAL(); + } + else + { + xReturn = ( xComPortHandle ) 0; + } + + /* This demo file only supports a single port but we have to return + something to comply with the standard demo header file. */ + return xReturn; +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) +{ + /* The port handle is not required as this driver only supports one port. */ + ( void ) pxPort; + + /* Get the next character from the buffer. Return false if no characters + are available, or arrive before xBlockTime expires. */ + if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) + { + return pdTRUE; + } + else + { + return pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength ) +{ +signed portCHAR *pxNext; + + /* A couple of parameters that this port does not use. */ + ( void ) usStringLength; + ( void ) pxPort; + + /* NOTE: This implementation does not handle the queue being full as no + block time is used! */ + + /* The port handle is not required as this driver only supports UART1. */ + ( void ) pxPort; + + /* Send each character in the string, one at a time. */ + pxNext = ( signed portCHAR * ) pcString; + while( *pxNext ) + { + xSerialPutChar( pxPort, *pxNext, serNO_BLOCK ); + pxNext++; + } +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) +{ +portBASE_TYPE xReturn; + + portENTER_CRITICAL(); + { + /* Can we write to the FIFO? */ + if( UART1->FR & serTX_FIFO_FULL ) + { + /* Wait for the interrupt letting us know there is space on the + FIFO. It is ok to block in a critical section, interrupts will be + enabled for other tasks once we force a switch. */ + lTaskWaiting = pdTRUE; + + /* Just to be a bit different this driver uses a semaphore to + block the sending task when the FIFO is full. The standard COMTest + task assumes a queue of adequate length exists so does not use + a block time. For this demo the block time is therefore hard + coded. */ + xReturn = xSemaphoreTake( xTxFIFOSemaphore, serTX_BLOCK_TIME ); + if( xReturn ) + { + UART1->DR = cOutChar; + } + } + else + { + UART1->DR = cOutChar; + xReturn = pdPASS; + } + } + portEXIT_CRITICAL(); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +void vSerialClose( xComPortHandle xPort ) +{ + /* Not supported as not required by the demo application. */ +} +/*-----------------------------------------------------------*/ + +void UART1_IRQHandler( void ) +{ +signed portCHAR cChar; +portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByPost = pdFALSE; + + while( UART1->RIS & mainRXRIS ) + { + /* The interrupt was caused by a character being received. Grab the + character from the DR and place it in the queue of received + characters. */ + cChar = UART1->DR; + xTaskWokenByPost = xQueueSendFromISR( xRxedChars, &cChar, xTaskWokenByPost ); + } + + if( UART1->RIS & mainTXRIS ) + { + if( lTaskWaiting == pdTRUE ) + { + /* This interrupt was caused by space becoming available on the Tx + FIFO, wake any task that is waiting to post (if any). */ + xTaskWokenByTx = xSemaphoreGiveFromISR( xTxFIFOSemaphore, xTaskWokenByTx ); + lTaskWaiting = pdFALSE; + } + + UART1->ICR = mainTXRIS; + } + + /* If a task was woken by either a character being received or a character + being transmitted then we may need to switch to another task. */ + portEND_SWITCHING_ISR( ( xTaskWokenByPost || xTaskWokenByTx ) ); +} + + + + + + diff --git a/20080212/Demo/ARM9_STR91X_IAR/settings/FreeRTOS.wsdt b/20080212/Demo/ARM9_STR91X_IAR/settings/FreeRTOS.wsdt new file mode 100644 index 000000000..c72818da9 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/settings/FreeRTOS.wsdt @@ -0,0 +1,63 @@ + + + + + + RTOSDemo/Debug + + + + + + + + + 208272727 + + + + + + + 30020100426766 + + 300BuildFind-in-FilesBreakpoints + + + + + 300BuildDebug-LogBreakpoints48268826 + 100300BuildFind-in-FilesDebug-Log + + + + + + + TabID-19472-27051 + Workspace + Workspace + + + RTOSDemoRTOSDemo/Demo Source + + + + 0TabID-17576-32349BuildBuild0 + + + + + + TextEditorC:\E\Dev\FreeRTOS\Source\portable\IAR\STR91x\port.c026282728272TextEditorC:\E\Dev\FreeRTOS\Demo\ARM9_STR91X_IAR\91x_vect_IAR.s09949794979TextEditorC:\E\Dev\FreeRTOS\Source\queue.c04201760317603TextEditorC:\E\Dev\FreeRTOS\Source\portable\IAR\STR91x\portasm.s7902124702470TextEditorC:\E\Dev\FreeRTOS\Source\tasks.c010183428134281TextEditorC:\E\Dev\FreeRTOS\Demo\ARM9_STR91X_IAR\FreeRTOSConfig.h0919681968TextEditorC:\E\Dev\FreeRTOS\Demo\ARM9_STR91X_IAR\91x_init_IAR.s070373237326TextEditorC:\E\Dev\FreeRTOS\Demo\ARM9_STR91X_IAR\Library\source\91x_enet.c14091399713997TextEditorC:\E\Dev\FreeRTOS\Demo\ARM9_STR91X_IAR\webserver\uIP_Task.c025673177317TextEditorC:\E\Dev\FreeRTOS\Demo\ARM9_STR91X_IAR\Library\include\91x_enet.h0126548154810100000010000001 + + + + + + + iaridepm1-2-2695282-2-2200200142857205761202857717078-2-22311402-2-214042331002857239712142857205761 + + + + diff --git a/20080212/Demo/ARM9_STR91X_IAR/settings/RTOSDemo.cspy.bat b/20080212/Demo/ARM9_STR91X_IAR/settings/RTOSDemo.cspy.bat new file mode 100644 index 000000000..7259709f7 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/settings/RTOSDemo.cspy.bat @@ -0,0 +1,32 @@ +@REM This bat file has been generated by the IAR Embeddded Workbench +@REM C-SPY interactive debugger,as an aid to preparing a command +@REM line for running the cspybat command line utility with the +@REM appropriate settings. +@REM +@REM After making some adjustments to this file, you can launch cspybat +@REM by typing the name of this file followed by the name of the debug +@REM file (usually an ubrof file). Note that this file is generated +@REM every time a new debug session is initialized, so you may want to +@REM move or rename the file before making changes. +@REM +@REM Note: some command line arguments cannot be properly generated +@REM by this process. Specifically, the plugin which is responsible +@REM for the Terminal I/O window (and other C runtime functionality) +@REM comes in a special version for cspybat, and the name of that +@REM plugin dll is not known when generating this file. It resides in +@REM the $TOOLKIT_DIR$\bin folder and is usually called XXXbat.dll or +@REM XXXlibsupportbat.dll, where XXX is the name of the corresponding +@REM tool chain. Replace the '' parameter +@REM below with the appropriate file name. Other plugins loaded by +@REM C-SPY are usually not needed by, or will not work in, cspybat +@REM but they are listed at the end of this file for reference. + + +"C:\Devtools\IAR Systems\Embedded Workbench 5.0\common\bin\cspybat" "C:\Devtools\IAR Systems\Embedded Workbench 5.0\ARM\bin\armproc.dll" "C:\Devtools\IAR Systems\Embedded Workbench 5.0\ARM\bin\armjlink.dll" %1 --plugin "C:\Devtools\IAR Systems\Embedded Workbench 5.0\ARM\bin\" --backend -B "--endian" "little" "--cpu" "ARM966E-S" "--fpu" "None" "--proc_device_desc_file" "C:\Devtools\IAR Systems\Embedded Workbench 5.0\ARM\CONFIG\debugger\ST\iostr912f.ddf" "--drv_verify_download" "all" "--proc_no_semihosting" "--proc_driver" "jlink" "--jlink_connection" "USB:0" "--jlink_initial_speed" "32" "--jlink_catch_exceptions" "0x000" + + +@REM Loaded plugins: +@REM armlibsupport.dll +@REM C:\Devtools\IAR Systems\Embedded Workbench 5.0\common\plugins\CodeCoverage\CodeCoverage.dll +@REM C:\Devtools\IAR Systems\Embedded Workbench 5.0\common\plugins\Profiling\Profiling.dll +@REM C:\Devtools\IAR Systems\Embedded Workbench 5.0\common\plugins\stack\stack.dll diff --git a/20080212/Demo/ARM9_STR91X_IAR/settings/RTOSDemo.dbgdt b/20080212/Demo/ARM9_STR91X_IAR/settings/RTOSDemo.dbgdt new file mode 100644 index 000000000..985ff1079 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/settings/RTOSDemo.dbgdt @@ -0,0 +1,81 @@ + + + + + + + + + + + + 20100626867 + + + + + + + 268272727 + + + + + + + + 200 + + + + 010 + 20048268826 + + + + + + + TabID-874-7293 + Debug Log + Debug-Log + + + + TabID-11099-7306 + Build + Build + + + TabID-4501-4793Find in FilesFind-in-FilesTabID-19328-10860BreakpointsBreakpoints + + 0 + + + TabID-11622-7296 + Workspace + Workspace + + + RTOSDemo + + + + 0 + + + + + + TextEditorC:\E\Dev\FreeRTOS\Demo\ARM9_STR91X_IAR\91x_vect.s04527852785TextEditorC:\E\Dev\FreeRTOS\Demo\ARM9_STR91X_IAR\91x_init.s06537043704TextEditorC:\E\Dev\FreeRTOS\Demo\ARM9_STR91X_IAR\main.c0170695269522TextEditorC:\E\Dev\FreeRTOS\Demo\ARM9_STR91X_IAR\webserver\uIP_Task.c03600TextEditorC:\E\Dev\FreeRTOS\Demo\ARM9_STR91X_IAR\lwip\include\lwIPWebServer\BasicWEB.h03420792079TextEditorC:\E\Dev\FreeRTOS\Demo\Common\ethernet\lwIP\core\tcp_in.c028410447104470100000010000001 + + + + + + + iaridepm.enu1debuggergui.enu1-2-2740342-2-2200200142857203666245714755601-2-21981402-2-214042001002857203666142857203666 + + + + diff --git a/20080212/Demo/ARM9_STR91X_IAR/settings/RTOSDemo.dni b/20080212/Demo/ARM9_STR91X_IAR/settings/RTOSDemo.dni new file mode 100644 index 000000000..c18ff2915 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/settings/RTOSDemo.dni @@ -0,0 +1,37 @@ +[JLinkDriver] +WatchCond=_ 0 +Watch0=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0 +Watch1=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0 +[DisAssemblyWindow] +NumStates=_ 1 +State 1=_ 1 +[Profiling] +Enabled=0 +[StackPlugin] +Enabled=1 +OverflowWarningsEnabled=1 +WarningThreshold=90 +SpWarningsEnabled=1 +WarnHow=0 +UseTrigger=1 +TriggerName=main +LimitSize=0 +ByteLimit=50 +[BreakpointUsageDialog] +Placement=_ 144 186 919 647 +[CodeCoverage] +Enabled=_ 0 +[Log file] +LoggingEnabled=_ 0 +LogFile=_ "" +Category=_ 0 +[TermIOLog] +LoggingEnabled=_ 0 +LogFile=_ "" +[Disassemble mode] +mode=0 +[Breakpoints] +Count=0 +[TraceHelper] +Enabled=0 +ShowSource=1 diff --git a/20080212/Demo/ARM9_STR91X_IAR/settings/RTOSDemo.wsdt b/20080212/Demo/ARM9_STR91X_IAR/settings/RTOSDemo.wsdt new file mode 100644 index 000000000..32b6915d1 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/settings/RTOSDemo.wsdt @@ -0,0 +1,68 @@ + + + + + + RTOSDemo/ARM - uIP - R + + + + + + + + + 328272727 + + + + + + + 20100626867 + + + 68268826100 + + + + + + + TabID-13420-7058 + Workspace + Workspace + + + RTOSDemoRTOSDemo/System Files + + + + 0 + + + TabID-22078-7100 + Build + Build + + + TabID-3326-16295Debug LogDebug-LogTabID-12949-6886Find in FilesFind-in-Files + + 0 + + + + + + TextEditorC:\E\Dev\FreeRTOS\Demo\ARM9_STR91X_IAR\91x_vect.s04527852785TextEditorC:\E\Dev\FreeRTOS\Demo\ARM9_STR91X_IAR\91x_init.s06537043704TextEditorC:\E\Dev\FreeRTOS\Demo\ARM9_STR91X_IAR\main.c0170695269522TextEditorC:\E\Dev\FreeRTOS\Demo\ARM9_STR91X_IAR\webserver\uIP_Task.c03600TextEditorC:\E\Dev\FreeRTOS\Demo\ARM9_STR91X_IAR\lwip\include\lwIPWebServer\BasicWEB.h03420792079TextEditorC:\E\Dev\FreeRTOS\Demo\Common\ethernet\lwIP\core\tcp_in.c028410447104470100000010000001 + + + + + + + iaridepm.enu1-2-2606402-2-2200200142857203666288571619145-2-23321402-2-214043341002857340122142857203666 + + + + diff --git a/20080212/Demo/ARM9_STR91X_IAR/webserver/Makefile.webserver b/20080212/Demo/ARM9_STR91X_IAR/webserver/Makefile.webserver new file mode 100644 index 000000000..f38c47a72 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/webserver/Makefile.webserver @@ -0,0 +1 @@ +APP_SOURCES += httpd.c http-strings.c httpd-fs.c httpd-cgi.c diff --git a/20080212/Demo/ARM9_STR91X_IAR/webserver/clock-arch.h b/20080212/Demo/ARM9_STR91X_IAR/webserver/clock-arch.h new file mode 100644 index 000000000..cde657b62 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/webserver/clock-arch.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2006, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: clock-arch.h,v 1.2 2006/06/12 08:00:31 adam Exp $ + */ + +#ifndef __CLOCK_ARCH_H__ +#define __CLOCK_ARCH_H__ + +#include "FreeRTOS.h" + +typedef unsigned long clock_time_t; +#define CLOCK_CONF_SECOND configTICK_RATE_HZ + +#endif /* __CLOCK_ARCH_H__ */ diff --git a/20080212/Demo/ARM9_STR91X_IAR/webserver/http-strings b/20080212/Demo/ARM9_STR91X_IAR/webserver/http-strings new file mode 100644 index 000000000..0d3c30cdd --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/webserver/http-strings @@ -0,0 +1,35 @@ +http_http "http://" +http_200 "200 " +http_301 "301 " +http_302 "302 " +http_get "GET " +http_10 "HTTP/1.0" +http_11 "HTTP/1.1" +http_content_type "content-type: " +http_texthtml "text/html" +http_location "location: " +http_host "host: " +http_crnl "\r\n" +http_index_html "/index.html" +http_404_html "/404.html" +http_referer "Referer:" +http_header_200 "HTTP/1.0 200 OK\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" +http_header_404 "HTTP/1.0 404 Not found\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" +http_content_type_plain "Content-type: text/plain\r\n\r\n" +http_content_type_html "Content-type: text/html\r\n\r\n" +http_content_type_css "Content-type: text/css\r\n\r\n" +http_content_type_text "Content-type: text/text\r\n\r\n" +http_content_type_png "Content-type: image/png\r\n\r\n" +http_content_type_gif "Content-type: image/gif\r\n\r\n" +http_content_type_jpg "Content-type: image/jpeg\r\n\r\n" +http_content_type_binary "Content-type: application/octet-stream\r\n\r\n" +http_html ".html" +http_shtml ".shtml" +http_htm ".htm" +http_css ".css" +http_png ".png" +http_gif ".gif" +http_jpg ".jpg" +http_text ".txt" +http_txt ".txt" + diff --git a/20080212/Demo/ARM9_STR91X_IAR/webserver/http-strings.c b/20080212/Demo/ARM9_STR91X_IAR/webserver/http-strings.c new file mode 100644 index 000000000..ef7a41c7d --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/webserver/http-strings.c @@ -0,0 +1,102 @@ +const char http_http[8] = +/* "http://" */ +{0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, }; +const char http_200[5] = +/* "200 " */ +{0x32, 0x30, 0x30, 0x20, }; +const char http_301[5] = +/* "301 " */ +{0x33, 0x30, 0x31, 0x20, }; +const char http_302[5] = +/* "302 " */ +{0x33, 0x30, 0x32, 0x20, }; +const char http_get[5] = +/* "GET " */ +{0x47, 0x45, 0x54, 0x20, }; +const char http_10[9] = +/* "HTTP/1.0" */ +{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, }; +const char http_11[9] = +/* "HTTP/1.1" */ +{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x31, }; +const char http_content_type[15] = +/* "content-type: " */ +{0x63, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, }; +const char http_texthtml[10] = +/* "text/html" */ +{0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_location[11] = +/* "location: " */ +{0x6c, 0x6f, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, }; +const char http_host[7] = +/* "host: " */ +{0x68, 0x6f, 0x73, 0x74, 0x3a, 0x20, }; +const char http_crnl[3] = +/* "\r\n" */ +{0xd, 0xa, }; +const char http_index_html[12] = +/* "/index.html" */ +{0x2f, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_404_html[10] = +/* "/404.html" */ +{0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_referer[9] = +/* "Referer:" */ +{0x52, 0x65, 0x66, 0x65, 0x72, 0x65, 0x72, 0x3a, }; +const char http_header_200[84] = +/* "HTTP/1.0 200 OK\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */ +{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x32, 0x30, 0x30, 0x20, 0x4f, 0x4b, 0xd, 0xa, 0x53, 0x65, 0x72, 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x73, 0x69, 0x63, 0x73, 0x2e, 0x73, 0x65, 0x2f, 0x7e, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, 0x70, 0x2f, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0xd, 0xa, }; +const char http_header_404[91] = +/* "HTTP/1.0 404 Not found\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */ +{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x34, 0x30, 0x34, 0x20, 0x4e, 0x6f, 0x74, 0x20, 0x66, 0x6f, 0x75, 0x6e, 0x64, 0xd, 0xa, 0x53, 0x65, 0x72, 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x73, 0x69, 0x63, 0x73, 0x2e, 0x73, 0x65, 0x2f, 0x7e, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, 0x70, 0x2f, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0xd, 0xa, }; +const char http_content_type_plain[29] = +/* "Content-type: text/plain\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x70, 0x6c, 0x61, 0x69, 0x6e, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_html[28] = +/* "Content-type: text/html\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_css [27] = +/* "Content-type: text/css\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x63, 0x73, 0x73, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_text[28] = +/* "Content-type: text/text\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x74, 0x65, 0x78, 0x74, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_png [28] = +/* "Content-type: image/png\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x70, 0x6e, 0x67, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_gif [28] = +/* "Content-type: image/gif\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x67, 0x69, 0x66, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_jpg [29] = +/* "Content-type: image/jpeg\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x6a, 0x70, 0x65, 0x67, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_binary[43] = +/* "Content-type: application/octet-stream\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x61, 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x2f, 0x6f, 0x63, 0x74, 0x65, 0x74, 0x2d, 0x73, 0x74, 0x72, 0x65, 0x61, 0x6d, 0xd, 0xa, 0xd, 0xa, }; +const char http_html[6] = +/* ".html" */ +{0x2e, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_shtml[7] = +/* ".shtml" */ +{0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_htm[5] = +/* ".htm" */ +{0x2e, 0x68, 0x74, 0x6d, }; +const char http_css[5] = +/* ".css" */ +{0x2e, 0x63, 0x73, 0x73, }; +const char http_png[5] = +/* ".png" */ +{0x2e, 0x70, 0x6e, 0x67, }; +const char http_gif[5] = +/* ".gif" */ +{0x2e, 0x67, 0x69, 0x66, }; +const char http_jpg[5] = +/* ".jpg" */ +{0x2e, 0x6a, 0x70, 0x67, }; +const char http_text[5] = +/* ".txt" */ +{0x2e, 0x74, 0x78, 0x74, }; +const char http_txt[5] = +/* ".txt" */ +{0x2e, 0x74, 0x78, 0x74, }; diff --git a/20080212/Demo/ARM9_STR91X_IAR/webserver/http-strings.h b/20080212/Demo/ARM9_STR91X_IAR/webserver/http-strings.h new file mode 100644 index 000000000..acbe7e17f --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/webserver/http-strings.h @@ -0,0 +1,34 @@ +extern const char http_http[8]; +extern const char http_200[5]; +extern const char http_301[5]; +extern const char http_302[5]; +extern const char http_get[5]; +extern const char http_10[9]; +extern const char http_11[9]; +extern const char http_content_type[15]; +extern const char http_texthtml[10]; +extern const char http_location[11]; +extern const char http_host[7]; +extern const char http_crnl[3]; +extern const char http_index_html[12]; +extern const char http_404_html[10]; +extern const char http_referer[9]; +extern const char http_header_200[84]; +extern const char http_header_404[91]; +extern const char http_content_type_plain[29]; +extern const char http_content_type_html[28]; +extern const char http_content_type_css [27]; +extern const char http_content_type_text[28]; +extern const char http_content_type_png [28]; +extern const char http_content_type_gif [28]; +extern const char http_content_type_jpg [29]; +extern const char http_content_type_binary[43]; +extern const char http_html[6]; +extern const char http_shtml[7]; +extern const char http_htm[5]; +extern const char http_css[5]; +extern const char http_png[5]; +extern const char http_gif[5]; +extern const char http_jpg[5]; +extern const char http_text[5]; +extern const char http_txt[5]; diff --git a/20080212/Demo/ARM9_STR91X_IAR/webserver/httpd-cgi.c b/20080212/Demo/ARM9_STR91X_IAR/webserver/httpd-cgi.c new file mode 100644 index 000000000..6ad2b9b2d --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/webserver/httpd-cgi.c @@ -0,0 +1,233 @@ +/** + * \addtogroup httpd + * @{ + */ + +/** + * \file + * Web server script interface + * \author + * Adam Dunkels + * + */ + +/* + * Copyright (c) 2001-2006, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: httpd-cgi.c,v 1.2 2006/06/11 21:46:37 adam Exp $ + * + */ + +#include "uip.h" +#include "psock.h" +#include "httpd.h" +#include "httpd-cgi.h" +#include "httpd-fs.h" + +#include +#include + +HTTPD_CGI_CALL(file, "file-stats", file_stats); +HTTPD_CGI_CALL(tcp, "tcp-connections", tcp_stats); +HTTPD_CGI_CALL(net, "net-stats", net_stats); +HTTPD_CGI_CALL(rtos, "rtos-stats", rtos_stats ); + + +static const struct httpd_cgi_call *calls[] = { &file, &tcp, &net, &rtos, NULL }; + +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(nullfunction(struct httpd_state *s, char *ptr)) +{ + PSOCK_BEGIN(&s->sout); + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +httpd_cgifunction +httpd_cgi(char *name) +{ + const struct httpd_cgi_call **f; + + /* Find the matching name in the table, return the function. */ + for(f = calls; *f != NULL; ++f) { + if(strncmp((*f)->name, name, strlen((*f)->name)) == 0) { + return (*f)->function; + } + } + return nullfunction; +} +/*---------------------------------------------------------------------------*/ +static unsigned short +generate_file_stats(void *arg) +{ + char *f = (char *)arg; + return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, "%5u", httpd_fs_count(f)); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(file_stats(struct httpd_state *s, char *ptr)) +{ + PSOCK_BEGIN(&s->sout); + + PSOCK_GENERATOR_SEND(&s->sout, generate_file_stats, strchr(ptr, ' ') + 1); + + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +static const char closed[] = /* "CLOSED",*/ +{0x43, 0x4c, 0x4f, 0x53, 0x45, 0x44, 0}; +static const char syn_rcvd[] = /* "SYN-RCVD",*/ +{0x53, 0x59, 0x4e, 0x2d, 0x52, 0x43, 0x56, + 0x44, 0}; +static const char syn_sent[] = /* "SYN-SENT",*/ +{0x53, 0x59, 0x4e, 0x2d, 0x53, 0x45, 0x4e, + 0x54, 0}; +static const char established[] = /* "ESTABLISHED",*/ +{0x45, 0x53, 0x54, 0x41, 0x42, 0x4c, 0x49, 0x53, 0x48, + 0x45, 0x44, 0}; +static const char fin_wait_1[] = /* "FIN-WAIT-1",*/ +{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49, + 0x54, 0x2d, 0x31, 0}; +static const char fin_wait_2[] = /* "FIN-WAIT-2",*/ +{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49, + 0x54, 0x2d, 0x32, 0}; +static const char closing[] = /* "CLOSING",*/ +{0x43, 0x4c, 0x4f, 0x53, 0x49, + 0x4e, 0x47, 0}; +static const char time_wait[] = /* "TIME-WAIT,"*/ +{0x54, 0x49, 0x4d, 0x45, 0x2d, 0x57, 0x41, + 0x49, 0x54, 0}; +static const char last_ack[] = /* "LAST-ACK"*/ +{0x4c, 0x41, 0x53, 0x54, 0x2d, 0x41, 0x43, + 0x4b, 0}; + +static const char *states[] = { + closed, + syn_rcvd, + syn_sent, + established, + fin_wait_1, + fin_wait_2, + closing, + time_wait, + last_ack}; + + +static unsigned short +generate_tcp_stats(void *arg) +{ + struct uip_conn *conn; + struct httpd_state *s = (struct httpd_state *)arg; + + conn = &uip_conns[s->count]; + return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, + "\r\n", + htons(conn->lport), + htons(conn->ripaddr[0]) >> 8, + htons(conn->ripaddr[0]) & 0xff, + htons(conn->ripaddr[1]) >> 8, + htons(conn->ripaddr[1]) & 0xff, + htons(conn->rport), + states[conn->tcpstateflags & UIP_TS_MASK], + conn->nrtx, + conn->timer, + (uip_outstanding(conn))? '*':' ', + (uip_stopped(conn))? '!':' '); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(tcp_stats(struct httpd_state *s, char *ptr)) +{ + + PSOCK_BEGIN(&s->sout); + + for(s->count = 0; s->count < UIP_CONNS; ++s->count) { + if((uip_conns[s->count].tcpstateflags & UIP_TS_MASK) != UIP_CLOSED) { + PSOCK_GENERATOR_SEND(&s->sout, generate_tcp_stats, s); + } + } + + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +static unsigned short +generate_net_stats(void *arg) +{ + struct httpd_state *s = (struct httpd_state *)arg; + return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, + "%5u\n", ((uip_stats_t *)&uip_stat)[s->count]); +} + +static +PT_THREAD(net_stats(struct httpd_state *s, char *ptr)) +{ + PSOCK_BEGIN(&s->sout); + +#if UIP_STATISTICS + + for(s->count = 0; s->count < sizeof(uip_stat) / sizeof(uip_stats_t); + ++s->count) { + PSOCK_GENERATOR_SEND(&s->sout, generate_net_stats, s); + } + +#endif /* UIP_STATISTICS */ + + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ + +extern void vTaskList( signed char *pcWriteBuffer ); +static char cCountBuf[ 32 ]; +long lRefreshCount = 0; +static unsigned short +generate_rtos_stats(void *arg) +{ + lRefreshCount++; + sprintf( cCountBuf, "


Refresh count = %d", lRefreshCount ); + vTaskList( uip_appdata ); + strcat( uip_appdata, cCountBuf ); + + return strlen( uip_appdata ); +} +/*---------------------------------------------------------------------------*/ + + +static +PT_THREAD(rtos_stats(struct httpd_state *s, char *ptr)) +{ + PSOCK_BEGIN(&s->sout); +// for( s->count = 0; s->count < 4; ++s->count ) +// { + PSOCK_GENERATOR_SEND(&s->sout, generate_rtos_stats, NULL); +// } + PSOCK_END(&s->sout); +} + +/** @} */ diff --git a/20080212/Demo/ARM9_STR91X_IAR/webserver/httpd-cgi.h b/20080212/Demo/ARM9_STR91X_IAR/webserver/httpd-cgi.h new file mode 100644 index 000000000..7ae928321 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/webserver/httpd-cgi.h @@ -0,0 +1,84 @@ +/** + * \addtogroup httpd + * @{ + */ + +/** + * \file + * Web server script interface header file + * \author + * Adam Dunkels + * + */ + + + +/* + * Copyright (c) 2001, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: httpd-cgi.h,v 1.2 2006/06/11 21:46:38 adam Exp $ + * + */ + +#ifndef __HTTPD_CGI_H__ +#define __HTTPD_CGI_H__ + +#include "psock.h" +#include "httpd.h" + +typedef PT_THREAD((* httpd_cgifunction)(struct httpd_state *, char *)); + +httpd_cgifunction httpd_cgi(char *name); + +struct httpd_cgi_call { + const char *name; + const httpd_cgifunction function; +}; + +/** + * \brief HTTPD CGI function declaration + * \param name The C variable name of the function + * \param str The string name of the function, used in the script file + * \param function A pointer to the function that implements it + * + * This macro is used for declaring a HTTPD CGI + * function. This function is then added to the list of + * HTTPD CGI functions with the httpd_cgi_add() function. + * + * \hideinitializer + */ +#define HTTPD_CGI_CALL(name, str, function) \ +static PT_THREAD(function(struct httpd_state *, char *)); \ +static const struct httpd_cgi_call name = {str, function} + +void httpd_cgi_init(void); +#endif /* __HTTPD_CGI_H__ */ + +/** @} */ diff --git a/20080212/Demo/ARM9_STR91X_IAR/webserver/httpd-fs.c b/20080212/Demo/ARM9_STR91X_IAR/webserver/httpd-fs.c new file mode 100644 index 000000000..dc4aef011 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/webserver/httpd-fs.c @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: httpd-fs.c,v 1.1 2006/06/07 09:13:08 adam Exp $ + */ + +#include "httpd.h" +#include "httpd-fs.h" +#include "httpd-fsdata.h" + +#ifndef NULL +#define NULL 0 +#endif /* NULL */ + +#include "httpd-fsdata.c" + +#if HTTPD_FS_STATISTICS +static u16_t count[HTTPD_FS_NUMFILES]; +#endif /* HTTPD_FS_STATISTICS */ + +/*-----------------------------------------------------------------------------------*/ +static u8_t +httpd_fs_strcmp(const char *str1, const char *str2) +{ + u8_t i; + i = 0; + loop: + + if(str2[i] == 0 || + str1[i] == '\r' || + str1[i] == '\n') { + return 0; + } + + if(str1[i] != str2[i]) { + return 1; + } + + + ++i; + goto loop; +} +/*-----------------------------------------------------------------------------------*/ +int +httpd_fs_open(const char *name, struct httpd_fs_file *file) +{ +#if HTTPD_FS_STATISTICS + u16_t i = 0; +#endif /* HTTPD_FS_STATISTICS */ + struct httpd_fsdata_file_noconst *f; + + for(f = (struct httpd_fsdata_file_noconst *)HTTPD_FS_ROOT; + f != NULL; + f = (struct httpd_fsdata_file_noconst *)f->next) { + + if(httpd_fs_strcmp(name, f->name) == 0) { + file->data = f->data; + file->len = f->len; +#if HTTPD_FS_STATISTICS + ++count[i]; +#endif /* HTTPD_FS_STATISTICS */ + return 1; + } +#if HTTPD_FS_STATISTICS + ++i; +#endif /* HTTPD_FS_STATISTICS */ + + } + return 0; +} +/*-----------------------------------------------------------------------------------*/ +void +httpd_fs_init(void) +{ +#if HTTPD_FS_STATISTICS + u16_t i; + for(i = 0; i < HTTPD_FS_NUMFILES; i++) { + count[i] = 0; + } +#endif /* HTTPD_FS_STATISTICS */ +} +/*-----------------------------------------------------------------------------------*/ +#if HTTPD_FS_STATISTICS +u16_t httpd_fs_count +(char *name) +{ + struct httpd_fsdata_file_noconst *f; + u16_t i; + + i = 0; + for(f = (struct httpd_fsdata_file_noconst *)HTTPD_FS_ROOT; + f != NULL; + f = (struct httpd_fsdata_file_noconst *)f->next) { + + if(httpd_fs_strcmp(name, f->name) == 0) { + return count[i]; + } + ++i; + } + return 0; +} +#endif /* HTTPD_FS_STATISTICS */ +/*-----------------------------------------------------------------------------------*/ diff --git a/20080212/Demo/ARM9_STR91X_IAR/webserver/httpd-fs.h b/20080212/Demo/ARM9_STR91X_IAR/webserver/httpd-fs.h new file mode 100644 index 000000000..b594eea56 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/webserver/httpd-fs.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: httpd-fs.h,v 1.1 2006/06/07 09:13:08 adam Exp $ + */ +#ifndef __HTTPD_FS_H__ +#define __HTTPD_FS_H__ + +#define HTTPD_FS_STATISTICS 1 + +struct httpd_fs_file { + char *data; + int len; +}; + +/* file must be allocated by caller and will be filled in + by the function. */ +int httpd_fs_open(const char *name, struct httpd_fs_file *file); + +#ifdef HTTPD_FS_STATISTICS +#if HTTPD_FS_STATISTICS == 1 +u16_t httpd_fs_count(char *name); +#endif /* HTTPD_FS_STATISTICS */ +#endif /* HTTPD_FS_STATISTICS */ + +void httpd_fs_init(void); + +#endif /* __HTTPD_FS_H__ */ diff --git a/20080212/Demo/ARM9_STR91X_IAR/webserver/httpd-fs/404.html b/20080212/Demo/ARM9_STR91X_IAR/webserver/httpd-fs/404.html new file mode 100644 index 000000000..43e7f4cad --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/webserver/httpd-fs/404.html @@ -0,0 +1,8 @@ + + +

+

404 - file not found

+

Go here instead.

+
+ + \ No newline at end of file diff --git a/20080212/Demo/ARM9_STR91X_IAR/webserver/httpd-fs/index.html b/20080212/Demo/ARM9_STR91X_IAR/webserver/httpd-fs/index.html new file mode 100644 index 000000000..1d3bbeee1 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/webserver/httpd-fs/index.html @@ -0,0 +1,13 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +Loading index.shtml. Click here if not automatically redirected. + + + + + diff --git a/20080212/Demo/ARM9_STR91X_IAR/webserver/httpd-fs/index.shtml b/20080212/Demo/ARM9_STR91X_IAR/webserver/httpd-fs/index.shtml new file mode 100644 index 000000000..37afd33a5 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/webserver/httpd-fs/index.shtml @@ -0,0 +1,20 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +RTOS Stats | TCP Stats | Connections | FreeRTOS.org Homepage +

+

+

+

Task statistics

+Page will refresh evey 2 seconds.

+

Task          State  Priority  Stack	#
************************************************

+%! rtos-stats
+
+ + + + diff --git a/20080212/Demo/ARM9_STR91X_IAR/webserver/httpd-fs/stats.shtml b/20080212/Demo/ARM9_STR91X_IAR/webserver/httpd-fs/stats.shtml new file mode 100644 index 000000000..3cc2df397 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/webserver/httpd-fs/stats.shtml @@ -0,0 +1,41 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +RTOS Stats | TCP Stats | Connections | FreeRTOS.org Homepage +

+

+

+

Network statistics

+
LocalRemoteStateRetransmissionsTimerFlags
%d%u.%u.%u.%u:%u%s%u%u%c %c
+
+IP           Packets dropped
+             Packets received
+             Packets sent
+IP errors    IP version/header length
+             IP length, high byte
+             IP length, low byte
+             IP fragments
+             Header checksum
+             Wrong protocol
+ICMP	     Packets dropped
+             Packets received
+             Packets sent
+             Type errors
+TCP          Packets dropped
+             Packets received
+             Packets sent
+             Checksum errors
+             Data packets without ACKs
+             Resets
+             Retransmissions
+	     No connection avaliable
+	     Connection attempts to closed ports
+
%! net-stats
+
+ + + diff --git a/20080212/Demo/ARM9_STR91X_IAR/webserver/httpd-fs/tcp.shtml b/20080212/Demo/ARM9_STR91X_IAR/webserver/httpd-fs/tcp.shtml new file mode 100644 index 000000000..4ed468a88 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/webserver/httpd-fs/tcp.shtml @@ -0,0 +1,21 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +RTOS Stats | TCP Stats | Connections | FreeRTOS.org Homepage +

+

+
+

Network connections

+

+ + +%! tcp-connections + + + + + diff --git a/20080212/Demo/ARM9_STR91X_IAR/webserver/httpd-fsdata.c b/20080212/Demo/ARM9_STR91X_IAR/webserver/httpd-fsdata.c new file mode 100644 index 000000000..d4017cd19 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/webserver/httpd-fsdata.c @@ -0,0 +1,363 @@ +static const unsigned char data_404_html[] = { + /* /404.html */ + 0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0, + 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xa, 0x20, 0x20, 0x3c, + 0x62, 0x6f, 0x64, 0x79, 0x20, 0x62, 0x67, 0x63, 0x6f, 0x6c, + 0x6f, 0x72, 0x3d, 0x22, 0x77, 0x68, 0x69, 0x74, 0x65, 0x22, + 0x3e, 0xa, 0x20, 0x20, 0x20, 0x20, 0x3c, 0x63, 0x65, 0x6e, + 0x74, 0x65, 0x72, 0x3e, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x3c, 0x68, 0x31, 0x3e, 0x34, 0x30, 0x34, 0x20, 0x2d, + 0x20, 0x66, 0x69, 0x6c, 0x65, 0x20, 0x6e, 0x6f, 0x74, 0x20, + 0x66, 0x6f, 0x75, 0x6e, 0x64, 0x3c, 0x2f, 0x68, 0x31, 0x3e, + 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x3c, 0x68, 0x33, + 0x3e, 0x47, 0x6f, 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0x2f, + 0x70, 0x72, 0x65, 0x3e, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, 0x74, + 0x3e, 0xa, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, 0x74, 0x3e, 0xa, + 0x3c, 0x2f, 0x62, 0x6f, 0x64, 0x79, 0x3e, 0xa, 0x3c, 0x2f, + 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xa, 0xa, 0}; + +const struct httpd_fsdata_file file_404_html[] = {{NULL, data_404_html, data_404_html + 10, sizeof(data_404_html) - 10}}; + +const struct httpd_fsdata_file file_index_html[] = {{file_404_html, data_index_html, data_index_html + 12, sizeof(data_index_html) - 12}}; + +const struct httpd_fsdata_file file_index_shtml[] = {{file_index_html, data_index_shtml, data_index_shtml + 13, sizeof(data_index_shtml) - 13}}; + +const struct httpd_fsdata_file file_stats_shtml[] = {{file_index_shtml, data_stats_shtml, data_stats_shtml + 13, sizeof(data_stats_shtml) - 13}}; + +const struct httpd_fsdata_file file_tcp_shtml[] = {{file_stats_shtml, data_tcp_shtml, data_tcp_shtml + 11, sizeof(data_tcp_shtml) - 11}}; + +#define HTTPD_FS_ROOT file_tcp_shtml + +#define HTTPD_FS_NUMFILES 5 diff --git a/20080212/Demo/ARM9_STR91X_IAR/webserver/httpd-fsdata.h b/20080212/Demo/ARM9_STR91X_IAR/webserver/httpd-fsdata.h new file mode 100644 index 000000000..52d35c265 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/webserver/httpd-fsdata.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: httpd-fsdata.h,v 1.1 2006/06/07 09:13:08 adam Exp $ + */ +#ifndef __HTTPD_FSDATA_H__ +#define __HTTPD_FSDATA_H__ + +#include "uip.h" + +struct httpd_fsdata_file { + const struct httpd_fsdata_file *next; + const char *name; + const char *data; + const int len; +#ifdef HTTPD_FS_STATISTICS +#if HTTPD_FS_STATISTICS == 1 + u16_t count; +#endif /* HTTPD_FS_STATISTICS */ +#endif /* HTTPD_FS_STATISTICS */ +}; + +struct httpd_fsdata_file_noconst { + struct httpd_fsdata_file *next; + char *name; + char *data; + int len; +#ifdef HTTPD_FS_STATISTICS +#if HTTPD_FS_STATISTICS == 1 + u16_t count; +#endif /* HTTPD_FS_STATISTICS */ +#endif /* HTTPD_FS_STATISTICS */ +}; + +#endif /* __HTTPD_FSDATA_H__ */ diff --git a/20080212/Demo/ARM9_STR91X_IAR/webserver/httpd.c b/20080212/Demo/ARM9_STR91X_IAR/webserver/httpd.c new file mode 100644 index 000000000..e808688d2 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/webserver/httpd.c @@ -0,0 +1,338 @@ +/** + * \addtogroup apps + * @{ + */ + +/** + * \defgroup httpd Web server + * @{ + * The uIP web server is a very simplistic implementation of an HTTP + * server. It can serve web pages and files from a read-only ROM + * filesystem, and provides a very small scripting language. + + */ + +/** + * \file + * Web server + * \author + * Adam Dunkels + */ + + +/* + * Copyright (c) 2004, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: httpd.c,v 1.2 2006/06/11 21:46:38 adam Exp $ + */ + +#include "uip.h" +#include "httpd.h" +#include "httpd-fs.h" +#include "httpd-cgi.h" +#include "http-strings.h" + +#include + +#define STATE_WAITING 0 +#define STATE_OUTPUT 1 + +#define ISO_nl 0x0a +#define ISO_space 0x20 +#define ISO_bang 0x21 +#define ISO_percent 0x25 +#define ISO_period 0x2e +#define ISO_slash 0x2f +#define ISO_colon 0x3a + + +/*---------------------------------------------------------------------------*/ +static unsigned short +generate_part_of_file(void *state) +{ + struct httpd_state *s = (struct httpd_state *)state; + + if(s->file.len > uip_mss()) { + s->len = uip_mss(); + } else { + s->len = s->file.len; + } + memcpy(uip_appdata, s->file.data, s->len); + + return s->len; +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(send_file(struct httpd_state *s)) +{ + PSOCK_BEGIN(&s->sout); + + do { + PSOCK_GENERATOR_SEND(&s->sout, generate_part_of_file, s); + s->file.len -= s->len; + s->file.data += s->len; + } while(s->file.len > 0); + + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(send_part_of_file(struct httpd_state *s)) +{ + PSOCK_BEGIN(&s->sout); + + PSOCK_SEND(&s->sout, s->file.data, s->len); + + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +static void +next_scriptstate(struct httpd_state *s) +{ + char *p; + p = strchr(s->scriptptr, ISO_nl) + 1; + s->scriptlen -= (unsigned short)(p - s->scriptptr); + s->scriptptr = p; +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(handle_script(struct httpd_state *s)) +{ + char *ptr; + + PT_BEGIN(&s->scriptpt); + + + while(s->file.len > 0) { + + /* Check if we should start executing a script. */ + if(*s->file.data == ISO_percent && + *(s->file.data + 1) == ISO_bang) { + s->scriptptr = s->file.data + 3; + s->scriptlen = s->file.len - 3; + if(*(s->scriptptr - 1) == ISO_colon) { + httpd_fs_open(s->scriptptr + 1, &s->file); + PT_WAIT_THREAD(&s->scriptpt, send_file(s)); + } else { + PT_WAIT_THREAD(&s->scriptpt, + httpd_cgi(s->scriptptr)(s, s->scriptptr)); + } + next_scriptstate(s); + + /* The script is over, so we reset the pointers and continue + sending the rest of the file. */ + s->file.data = s->scriptptr; + s->file.len = s->scriptlen; + } else { + /* See if we find the start of script marker in the block of HTML + to be sent. */ + + if(s->file.len > uip_mss()) { + s->len = uip_mss(); + } else { + s->len = s->file.len; + } + + if(*s->file.data == ISO_percent) { + ptr = strchr(s->file.data + 1, ISO_percent); + } else { + ptr = strchr(s->file.data, ISO_percent); + } + if(ptr != NULL && + ptr != s->file.data) { + s->len = (int)(ptr - s->file.data); + if(s->len >= uip_mss()) { + s->len = uip_mss(); + } + } + PT_WAIT_THREAD(&s->scriptpt, send_part_of_file(s)); + s->file.data += s->len; + s->file.len -= s->len; + + } + } + + PT_END(&s->scriptpt); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(send_headers(struct httpd_state *s, const char *statushdr)) +{ + char *ptr; + + PSOCK_BEGIN(&s->sout); + + PSOCK_SEND_STR(&s->sout, statushdr); + + ptr = strrchr(s->filename, ISO_period); + if(ptr == NULL) { + PSOCK_SEND_STR(&s->sout, http_content_type_binary); + } else if(strncmp(http_html, ptr, 5) == 0 || + strncmp(http_shtml, ptr, 6) == 0) { + PSOCK_SEND_STR(&s->sout, http_content_type_html); + } else if(strncmp(http_css, ptr, 4) == 0) { + PSOCK_SEND_STR(&s->sout, http_content_type_css); + } else if(strncmp(http_png, ptr, 4) == 0) { + PSOCK_SEND_STR(&s->sout, http_content_type_png); + } else if(strncmp(http_gif, ptr, 4) == 0) { + PSOCK_SEND_STR(&s->sout, http_content_type_gif); + } else if(strncmp(http_jpg, ptr, 4) == 0) { + PSOCK_SEND_STR(&s->sout, http_content_type_jpg); + } else { + PSOCK_SEND_STR(&s->sout, http_content_type_plain); + } + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(handle_output(struct httpd_state *s)) +{ + char *ptr; + + PT_BEGIN(&s->outputpt); + + if(!httpd_fs_open(s->filename, &s->file)) { + httpd_fs_open(http_404_html, &s->file); + strcpy(s->filename, http_404_html); + PT_WAIT_THREAD(&s->outputpt, + send_headers(s, + http_header_404)); + PT_WAIT_THREAD(&s->outputpt, + send_file(s)); + } else { + PT_WAIT_THREAD(&s->outputpt, + send_headers(s, + http_header_200)); + ptr = strchr(s->filename, ISO_period); + if(ptr != NULL && strncmp(ptr, http_shtml, 6) == 0) { + PT_INIT(&s->scriptpt); + PT_WAIT_THREAD(&s->outputpt, handle_script(s)); + } else { + PT_WAIT_THREAD(&s->outputpt, + send_file(s)); + } + } + PSOCK_CLOSE(&s->sout); + PT_END(&s->outputpt); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(handle_input(struct httpd_state *s)) +{ + PSOCK_BEGIN(&s->sin); + + PSOCK_READTO(&s->sin, ISO_space); + + + if(strncmp(s->inputbuf, http_get, 4) != 0) { + PSOCK_CLOSE_EXIT(&s->sin); + } + PSOCK_READTO(&s->sin, ISO_space); + + if(s->inputbuf[0] != ISO_slash) { + PSOCK_CLOSE_EXIT(&s->sin); + } + + if(s->inputbuf[1] == ISO_space) { + strncpy(s->filename, http_index_html, sizeof(s->filename)); + } else { + s->inputbuf[PSOCK_DATALEN(&s->sin) - 1] = 0; + strncpy(s->filename, &s->inputbuf[0], sizeof(s->filename)); + } + + /* httpd_log_file(uip_conn->ripaddr, s->filename);*/ + + s->state = STATE_OUTPUT; + + while(1) { + PSOCK_READTO(&s->sin, ISO_nl); + + if(strncmp(s->inputbuf, http_referer, 8) == 0) { + s->inputbuf[PSOCK_DATALEN(&s->sin) - 2] = 0; + /* httpd_log(&s->inputbuf[9]);*/ + } + } + + PSOCK_END(&s->sin); +} +/*---------------------------------------------------------------------------*/ +static void +handle_connection(struct httpd_state *s) +{ + handle_input(s); + if(s->state == STATE_OUTPUT) { + handle_output(s); + } +} +/*---------------------------------------------------------------------------*/ +void +httpd_appcall(void) +{ + struct httpd_state *s = (struct httpd_state *)&(uip_conn->appstate); + + if(uip_closed() || uip_aborted() || uip_timedout()) { + } else if(uip_connected()) { + PSOCK_INIT(&s->sin, s->inputbuf, sizeof(s->inputbuf) - 1); + PSOCK_INIT(&s->sout, s->inputbuf, sizeof(s->inputbuf) - 1); + PT_INIT(&s->outputpt); + s->state = STATE_WAITING; + /* timer_set(&s->timer, CLOCK_SECOND * 100);*/ + s->timer = 0; + handle_connection(s); + } else if(s != NULL) { + if(uip_poll()) { + ++s->timer; + if(s->timer >= 20) { + uip_abort(); + } + } else { + s->timer = 0; + } + handle_connection(s); + } else { + uip_abort(); + } +} +/*---------------------------------------------------------------------------*/ +/** + * \brief Initialize the web server + * + * This function initializes the web server and should be + * called at system boot-up. + */ +void +httpd_init(void) +{ + uip_listen(HTONS(80)); +} +/*---------------------------------------------------------------------------*/ +/** @} */ diff --git a/20080212/Demo/ARM9_STR91X_IAR/webserver/httpd.h b/20080212/Demo/ARM9_STR91X_IAR/webserver/httpd.h new file mode 100644 index 000000000..7f7a6666e --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/webserver/httpd.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2001-2005, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: httpd.h,v 1.2 2006/06/11 21:46:38 adam Exp $ + * + */ + +#ifndef __HTTPD_H__ +#define __HTTPD_H__ + +#include "psock.h" +#include "httpd-fs.h" + +struct httpd_state { + unsigned char timer; + struct psock sin, sout; + struct pt outputpt, scriptpt; + char inputbuf[50]; + char filename[20]; + char state; + struct httpd_fs_file file; + int len; + char *scriptptr; + int scriptlen; + + unsigned short count; +}; + +void httpd_init(void); +void httpd_appcall(void); + +void httpd_log(char *msg); +void httpd_log_file(u16_t *requester, char *file); + +#endif /* __HTTPD_H__ */ diff --git a/20080212/Demo/ARM9_STR91X_IAR/webserver/makefsdata b/20080212/Demo/ARM9_STR91X_IAR/webserver/makefsdata new file mode 100644 index 000000000..8d2715a8a --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/webserver/makefsdata @@ -0,0 +1,78 @@ +#!/usr/bin/perl + +open(OUTPUT, "> httpd-fsdata.c"); + +chdir("httpd-fs"); + +opendir(DIR, "."); +@files = grep { !/^\./ && !/(CVS|~)/ } readdir(DIR); +closedir(DIR); + +foreach $file (@files) { + + if(-d $file && $file !~ /^\./) { + print "Processing directory $file\n"; + opendir(DIR, $file); + @newfiles = grep { !/^\./ && !/(CVS|~)/ } readdir(DIR); + closedir(DIR); + printf "Adding files @newfiles\n"; + @files = (@files, map { $_ = "$file/$_" } @newfiles); + next; + } +} + +foreach $file (@files) { + if(-f $file) { + + print "Adding file $file\n"; + + open(FILE, $file) || die "Could not open file $file\n"; + + $file =~ s-^-/-; + $fvar = $file; + $fvar =~ s-/-_-g; + $fvar =~ s-\.-_-g; + # for AVR, add PROGMEM here + print(OUTPUT "static const unsigned char data".$fvar."[] = {\n"); + print(OUTPUT "\t/* $file */\n\t"); + for($j = 0; $j < length($file); $j++) { + printf(OUTPUT "%#02x, ", unpack("C", substr($file, $j, 1))); + } + printf(OUTPUT "0,\n"); + + + $i = 0; + while(read(FILE, $data, 1)) { + if($i == 0) { + print(OUTPUT "\t"); + } + printf(OUTPUT "%#02x, ", unpack("C", $data)); + $i++; + if($i == 10) { + print(OUTPUT "\n"); + $i = 0; + } + } + print(OUTPUT "0};\n\n"); + close(FILE); + push(@fvars, $fvar); + push(@pfiles, $file); + } +} + +for($i = 0; $i < @fvars; $i++) { + $file = $pfiles[$i]; + $fvar = $fvars[$i]; + + if($i == 0) { + $prevfile = "NULL"; + } else { + $prevfile = "file" . $fvars[$i - 1]; + } + print(OUTPUT "const struct httpd_fsdata_file file".$fvar."[] = {{$prevfile, data$fvar, "); + print(OUTPUT "data$fvar + ". (length($file) + 1) .", "); + print(OUTPUT "sizeof(data$fvar) - ". (length($file) + 1) ."}};\n\n"); +} + +print(OUTPUT "#define HTTPD_FS_ROOT file$fvars[$i - 1]\n\n"); +print(OUTPUT "#define HTTPD_FS_NUMFILES $i\n"); diff --git a/20080212/Demo/ARM9_STR91X_IAR/webserver/makestrings b/20080212/Demo/ARM9_STR91X_IAR/webserver/makestrings new file mode 100644 index 000000000..8a13c6d29 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/webserver/makestrings @@ -0,0 +1,40 @@ +#!/usr/bin/perl + + +sub stringify { + my $name = shift(@_); + open(OUTPUTC, "> $name.c"); + open(OUTPUTH, "> $name.h"); + + open(FILE, "$name"); + + while() { + if(/(.+) "(.+)"/) { + $var = $1; + $data = $2; + + $datan = $data; + $datan =~ s/\\r/\r/g; + $datan =~ s/\\n/\n/g; + $datan =~ s/\\01/\01/g; + $datan =~ s/\\0/\0/g; + + printf(OUTPUTC "const char $var\[%d] = \n", length($datan) + 1); + printf(OUTPUTC "/* \"$data\" */\n"); + printf(OUTPUTC "{"); + for($j = 0; $j < length($datan); $j++) { + printf(OUTPUTC "%#02x, ", unpack("C", substr($datan, $j, 1))); + } + printf(OUTPUTC "};\n"); + + printf(OUTPUTH "extern const char $var\[%d];\n", length($datan) + 1); + + } + } + close(OUTPUTC); + close(OUTPUTH); +} +stringify("http-strings"); + +exit 0; + diff --git a/20080212/Demo/ARM9_STR91X_IAR/webserver/uIP_Task.c b/20080212/Demo/ARM9_STR91X_IAR/webserver/uIP_Task.c new file mode 100644 index 000000000..68f03bb0a --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/webserver/uIP_Task.c @@ -0,0 +1,323 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ +/* Standard includes. */ +#include + +/* Library includes. */ +#include "91x_lib.h" +#include "91x_enet.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* uip includes. */ +#include "uip.h" +#include "uip_arp.h" +#include "httpd.h" +#include "timer.h" +#include "clock-arch.h" + +/*-----------------------------------------------------------*/ + +/* MAC address configuration. */ +#define uipMAC_ADDR0 0x00 +#define uipMAC_ADDR1 0x12 +#define uipMAC_ADDR2 0x13 +#define uipMAC_ADDR3 0x14 +#define uipMAC_ADDR4 0x15 +#define uipMAC_ADDR5 0x20 + +/* IP address configuration. */ +#define uipIP_ADDR0 172 +#define uipIP_ADDR1 25 +#define uipIP_ADDR2 218 +#define uipIP_ADDR3 11 + +/* Netmask configuration. */ +#define uipNET_MASK0 255 +#define uipNET_MASK1 255 +#define uipNET_MASK2 255 +#define uipNET_MASK3 0 + +/* Gateway address configuration. */ +#define uipGATEWAY_ADDR0 172 +#define uipGATEWAY_ADDR1 25 +#define uipGATEWAY_ADDR2 218 +#define uipGATEWAY_ADDR3 1 + +/* Shortcut to the header within the Rx buffer. */ +#define xHeader ((struct uip_eth_hdr *) &uip_buf[ 0 ]) + +/* uIP update frequencies. */ +#define uipMAX_BLOCK_TIME (configTICK_RATE_HZ / 4) + +/* Interrupt status bit definition. */ +#define uipDMI_RX_CURRENT_DONE 0x8000 + +/* If no buffers are available, then wait this long before looking again. */ +#define uipBUFFER_WAIT_DELAY ( 10 / portTICK_RATE_MS ) +#define uipBUFFER_WAIT_ATTEMPTS ( 10 ) + +/* Standard constant. */ +#define uipTOTAL_FRAME_HEADER_SIZE 54 + +/*-----------------------------------------------------------*/ + +/* + * Send the uIP buffer to the MAC. + */ +static void prvENET_Send(void); + +/* + * Setup the MAC address in the MAC itself, and in the uIP stack. + */ +static void prvSetMACAddress( void ); + +/* + * Used to return a pointer to the next buffer to be used. + */ +extern unsigned portCHAR *pcGetNextBuffer( void ); + +/* + * Port functions required by the uIP stack. + */ +void clock_init( void ); +clock_time_t clock_time( void ); + +/*-----------------------------------------------------------*/ + +/* The semaphore used by the ISR to wake the uIP task. */ +xSemaphoreHandle xSemaphore = NULL; + +/*-----------------------------------------------------------*/ + +void clock_init(void) +{ + /* This is done when the scheduler starts. */ +} +/*-----------------------------------------------------------*/ + +clock_time_t clock_time( void ) +{ + return xTaskGetTickCount(); +} +/*-----------------------------------------------------------*/ + +void vuIP_Task( void *pvParameters ) +{ +portBASE_TYPE i; +uip_ipaddr_t xIPAddr; +struct timer periodic_timer, arp_timer; + + /* Create the semaphore used by the ISR to wake this task. */ + vSemaphoreCreateBinary( xSemaphore ); + + /* Initialise the uIP stack. */ + timer_set( &periodic_timer, configTICK_RATE_HZ / 2 ); + timer_set( &arp_timer, configTICK_RATE_HZ * 10 ); + uip_init(); + uip_ipaddr( xIPAddr, uipIP_ADDR0, uipIP_ADDR1, uipIP_ADDR2, uipIP_ADDR3 ); + uip_sethostaddr( xIPAddr ); + uip_ipaddr( xIPAddr, uipNET_MASK0, uipNET_MASK1, uipNET_MASK2, uipNET_MASK3 ); + uip_setnetmask( xIPAddr ); + uip_ipaddr( xIPAddr, uipGATEWAY_ADDR0, uipGATEWAY_ADDR1, uipGATEWAY_ADDR2, uipGATEWAY_ADDR3 ); + uip_setdraddr( xIPAddr ); + httpd_init(); + + /* Initialise the MAC. */ + ENET_InitClocksGPIO(); + ENET_Init(); + portENTER_CRITICAL(); + { + ENET_Start(); + prvSetMACAddress(); + VIC_Config( ENET_ITLine, VIC_IRQ, 1 ); + VIC_ITCmd( ENET_ITLine, ENABLE ); + ENET_DMA->ISR = uipDMI_RX_CURRENT_DONE; + ENET_DMA->IER = uipDMI_RX_CURRENT_DONE; + } + portEXIT_CRITICAL(); + + + while(1) + { + /* Is there received data ready to be processed? */ + uip_len = ENET_HandleRxPkt( uip_buf ); + + if( uip_len > 0 ) + { + /* Standard uIP loop taken from the uIP manual. */ + if( xHeader->type == htons( UIP_ETHTYPE_IP ) ) + { + uip_arp_ipin(); + uip_input(); + + /* If the above function invocation resulted in data that + should be sent out on the network, the global variable + uip_len is set to a value > 0. */ + if( uip_len > 0 ) + { + uip_arp_out(); + prvENET_Send(); + } + } + else if( xHeader->type == htons( UIP_ETHTYPE_ARP ) ) + { + uip_arp_arpin(); + + /* If the above function invocation resulted in data that + should be sent out on the network, the global variable + uip_len is set to a value > 0. */ + if( uip_len > 0 ) + { + prvENET_Send(); + } + } + } + else + { + if( timer_expired( &periodic_timer ) ) + { + timer_reset( &periodic_timer ); + for( i = 0; i < UIP_CONNS; i++ ) + { + uip_periodic( i ); + + /* If the above function invocation resulted in data that + should be sent out on the network, the global variable + uip_len is set to a value > 0. */ + if( uip_len > 0 ) + { + uip_arp_out(); + prvENET_Send(); + } + } + + /* Call the ARP timer function every 10 seconds. */ + if( timer_expired( &arp_timer ) ) + { + timer_reset( &arp_timer ); + uip_arp_timer(); + } + } + else + { + /* We did not receive a packet, and there was no periodic + processing to perform. Block for a fixed period. If a packet + is received during this period we will be woken by the ISR + giving us the Semaphore. */ + xSemaphoreTake( xSemaphore, configTICK_RATE_HZ / 2 ); + } + } + } +} +/*-----------------------------------------------------------*/ + +static void prvENET_Send(void) +{ +portBASE_TYPE i; +static unsigned portCHAR *pcTxData; + + /* Get a DMA buffer into which we can write the data to send. */ + for( i = 0; i < uipBUFFER_WAIT_ATTEMPTS; i++ ) + { + pcTxData = pcGetNextBuffer(); + + if( pcTxData ) + { + break; + } + else + { + vTaskDelay( uipBUFFER_WAIT_DELAY ); + } + } + + if( pcTxData ) + { + /* Copy the header into the Tx buffer. */ + memcpy( ( void * ) pcTxData, ( void * ) uip_buf, uipTOTAL_FRAME_HEADER_SIZE ); + if( uip_len > uipTOTAL_FRAME_HEADER_SIZE ) + { + memcpy( ( void * ) &( pcTxData[ uipTOTAL_FRAME_HEADER_SIZE ] ), ( void * ) uip_appdata, ( uip_len - uipTOTAL_FRAME_HEADER_SIZE ) ); + } + + ENET_TxPkt( &pcTxData, uip_len ); + } +} +/*-----------------------------------------------------------*/ + +void ENET_IRQHandler(void) +{ +portBASE_TYPE xSwitchRequired; + + /* Give the semaphore in case the uIP task needs waking. */ + xSwitchRequired = xSemaphoreGiveFromISR( xSemaphore, pdFALSE ); + + /* Clear the interrupt. */ + ENET_DMA->ISR = uipDMI_RX_CURRENT_DONE; + + /* Switch tasks if necessary. */ + portEND_SWITCHING_ISR( xSwitchRequired ); +} +/*-----------------------------------------------------------*/ + +static void prvSetMACAddress( void ) +{ +struct uip_eth_addr xAddr; + + /* Configure the MAC address in the uIP stack. */ + xAddr.addr[ 0 ] = uipMAC_ADDR0; + xAddr.addr[ 1 ] = uipMAC_ADDR1; + xAddr.addr[ 2 ] = uipMAC_ADDR2; + xAddr.addr[ 3 ] = uipMAC_ADDR3; + xAddr.addr[ 4 ] = uipMAC_ADDR4; + xAddr.addr[ 5 ] = uipMAC_ADDR5; + uip_setethaddr( xAddr ); + + /* Write the MAC address to the MAC. */ + ENET_MAC->MAL = ( uipMAC_ADDR3 << 24 ) | ( uipMAC_ADDR2 << 16 ) | ( uipMAC_ADDR1 << 8 ) | ( uipMAC_ADDR0 ); + ENET_MAC->MAH = ( uipMAC_ADDR5 << 8 ) | ( uipMAC_ADDR4 ); +} + diff --git a/20080212/Demo/ARM9_STR91X_IAR/webserver/uip-conf.h b/20080212/Demo/ARM9_STR91X_IAR/webserver/uip-conf.h new file mode 100644 index 000000000..d514d14d2 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/webserver/uip-conf.h @@ -0,0 +1,157 @@ +/** + * \addtogroup uipopt + * @{ + */ + +/** + * \name Project-specific configuration options + * @{ + * + * uIP has a number of configuration options that can be overridden + * for each project. These are kept in a project-specific uip-conf.h + * file and all configuration names have the prefix UIP_CONF. + */ + +/* + * Copyright (c) 2006, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: uip-conf.h,v 1.6 2006/06/12 08:00:31 adam Exp $ + */ + +/** + * \file + * An example uIP configuration file + * \author + * Adam Dunkels + */ + +#ifndef __UIP_CONF_H__ +#define __UIP_CONF_H__ + +#include + +/** + * 8 bit datatype + * + * This typedef defines the 8-bit type used throughout uIP. + * + * \hideinitializer + */ +typedef uint8_t u8_t; + +/** + * 16 bit datatype + * + * This typedef defines the 16-bit type used throughout uIP. + * + * \hideinitializer + */ +typedef uint16_t u16_t; + +/** + * Statistics datatype + * + * This typedef defines the dataype used for keeping statistics in + * uIP. + * + * \hideinitializer + */ +typedef unsigned short uip_stats_t; + +/** + * Maximum number of TCP connections. + * + * \hideinitializer + */ +#define UIP_CONF_MAX_CONNECTIONS 40 + +/** + * Maximum number of listening TCP ports. + * + * \hideinitializer + */ +#define UIP_CONF_MAX_LISTENPORTS 40 + +/** + * uIP buffer size. + * + * \hideinitializer + */ +#define UIP_CONF_BUFFER_SIZE 1480 + +/** + * CPU byte order. + * + * \hideinitializer + */ +#define UIP_CONF_BYTE_ORDER LITTLE_ENDIAN + +/** + * Logging on or off + * + * \hideinitializer + */ +#define UIP_CONF_LOGGING 0 + +/** + * UDP support on or off + * + * \hideinitializer + */ +#define UIP_CONF_UDP 0 + +/** + * UDP checksums on or off + * + * \hideinitializer + */ +#define UIP_CONF_UDP_CHECKSUMS 1 + +/** + * uIP statistics on or off + * + * \hideinitializer + */ +#define UIP_CONF_STATISTICS 1 + +/* Here we include the header file for the application(s) we use in + our project. */ +/*#include "smtp.h"*/ +/*#include "hello-world.h"*/ +/*#include "telnetd.h"*/ +#include "webserver.h" +/*#include "dhcpc.h"*/ +/*#include "resolv.h"*/ +/*#include "webclient.h"*/ + +#endif /* __UIP_CONF_H__ */ + +/** @} */ +/** @} */ diff --git a/20080212/Demo/ARM9_STR91X_IAR/webserver/webserver.h b/20080212/Demo/ARM9_STR91X_IAR/webserver/webserver.h new file mode 100644 index 000000000..1acb290b8 --- /dev/null +++ b/20080212/Demo/ARM9_STR91X_IAR/webserver/webserver.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2002, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: webserver.h,v 1.2 2006/06/11 21:46:38 adam Exp $ + * + */ +#ifndef __WEBSERVER_H__ +#define __WEBSERVER_H__ + +#include "httpd.h" + +typedef struct httpd_state uip_tcp_appstate_t; +/* UIP_APPCALL: the name of the application function. This function + must return void and take no arguments (i.e., C type "void + appfunc(void)"). */ +#ifndef UIP_APPCALL +#define UIP_APPCALL httpd_appcall +#endif + + +#endif /* __WEBSERVER_H__ */ diff --git a/20080212/Demo/AVR32_UC3/AT32UC3A/GCC/Makefile b/20080212/Demo/AVR32_UC3/AT32UC3A/GCC/Makefile new file mode 100644 index 000000000..6f51ddb10 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/AT32UC3A/GCC/Makefile @@ -0,0 +1,618 @@ +# Hey Emacs, this is a -*- makefile -*- + +# Goals available on make command line: +# +# [all] Default goal: build the project. +# clean Clean up the project. +# rebuild Rebuild the project. +# ccversion Display CC version information. +# cppfiles file.i Generate preprocessed files from C source files. +# asfiles file.x Generate preprocessed assembler files from C and assembler source files. +# objfiles file.o Generate object files from C and assembler source files. +# a file.a Archive: create A output file from object files. +# elf file.elf Link: create ELF output file from object files. +# lss file.lss Create extended listing from target output file. +# sym file.sym Create symbol table from target output file. +# hex file.hex Create Intel HEX image from ELF output file. +# bin file.bin Create binary image from ELF output file. +# sizes Display target size information. +# isp Use ISP instead of JTAGICE mkII when programming. +# cpuinfo Get CPU information. +# halt Stop CPU execution. +# chiperase Perform a JTAG Chip Erase command. +# erase Perform a flash chip erase. +# program Program MCU memory from ELF output file. +# secureflash Protect chip by setting security bit. +# reset Reset MCU. +# debug Open a debug connection with the MCU. +# run Start CPU execution. +# readregs Read CPU registers. +# doc Build the documentation. +# cleandoc Clean up the documentation. +# rebuilddoc Rebuild the documentation. +# verbose Display main executed commands. + +# Copyright (c) 2007, Atmel Corporation All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation and/ +# or other materials provided with the distribution. +# +# 3. The name of ATMEL may not be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND +# SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, +# INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +# OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + +# ** ** ** *** ** ** ** ** ** ** ** ** ** ** ** +# ENVIRONMENT SETTINGS +# ** ** ** *** ** ** ** ** ** ** ** ** ** ** ** + +FirstWord = $(if $(1),$(word 1,$(1))) +LastWord = $(if $(1),$(word $(words $(1)),$(1))) + +MAKE = make +MAKECFG = config.mk +TGTTYPE = $(suffix $(TARGET)) + +RM = rm -Rf + +AR = avr32-ar +ARFLAGS = rcs + +CPP = $(CC) -E +CPPFLAGS = -march=$(ARCH) -mpart=$(PART) $(WARNINGS) $(DEFS) \ + $(PLATFORM_INC_PATH:%=-I%) $(INC_PATH:%=-I%) $(CPP_EXTRA_FLAGS) +DPNDFILES = $(CSRCS:.c=.d) $(ASSRCS:.S=.d) +CPPFILES = $(CSRCS:.c=.i) + +CC = avr32-gcc +CFLAGS = $(DEBUG) $(OPTIMIZATION) $(C_EXTRA_FLAGS) \ + $(PLATFORM_INC_PATH:%=-Wa,-I%) $(INC_PATH:%=-Wa,-I%) $(AS_EXTRA_FLAGS) +ASFILES = $(CSRCS:.c=.x) $(ASSRCS:.S=.x) + +AS = avr32-as +ASFLAGS = $(DEBUG) \ + $(PLATFORM_INC_PATH:%=-Wa,-I%) $(INC_PATH:%=-Wa,-I%) $(AS_EXTRA_FLAGS) +OBJFILES = $(CSRCS:.c=.o) $(ASSRCS:.S=.o) + +LD = avr32-ld +LDFLAGS = -march=$(ARCH) -mpart=$(PART) \ + $(LIB_PATH:%=-L%) $(LINKER_SCRIPT:%=-T%) $(LD_EXTRA_FLAGS) +LOADLIBES = +LDLIBS = $(LIBS:%=-l%) + +OBJDUMP = avr32-objdump +LSS = $(TARGET:$(TGTTYPE)=.lss) + +NM = avr32-nm +SYM = $(TARGET:$(TGTTYPE)=.sym) + +OBJCOPY = avr32-objcopy +HEX = $(TARGET:$(TGTTYPE)=.hex) +BIN = $(TARGET:$(TGTTYPE)=.bin) + +SIZE = avr32-size + +SLEEP = sleep +SLEEPUSB = 9 + +PROGRAM = avr32program + +ISP = batchisp +ISPFLAGS = -device at32$(PART) -hardware usb -operation + +DBGPROXY = avr32gdbproxy + +DOCGEN = doxygen + + +# ** ** ** *** ** ** ** ** ** ** ** ** ** ** ** +# MESSAGES +# ** ** ** *** ** ** ** ** ** ** ** ** ** ** ** + +ERR_TARGET_TYPE = Target type not supported: `$(TGTTYPE)' +MSG_CLEANING = Cleaning project. +MSG_PREPROCESSING = Preprocessing \`$<\' to \`$@\'. +MSG_COMPILING = Compiling \`$<\' to \`$@\'. +MSG_ASSEMBLING = Assembling \`$<\' to \`$@\'. +MSG_ARCHIVING = Archiving to \`$@\'. +MSG_LINKING = Linking to \`$@\'. +MSG_EXTENDED_LISTING = Creating extended listing to \`$@\'. +MSG_SYMBOL_TABLE = Creating symbol table to \`$@\'. +MSG_IHEX_IMAGE = Creating Intel HEX image to \`$@\'. +MSG_BINARY_IMAGE = Creating binary image to \`$@\'. +MSG_GETTING_CPU_INFO = Getting CPU information. +MSG_HALTING = Stopping CPU execution. +MSG_ERASING_CHIP = Performing a JTAG Chip Erase command. +MSG_ERASING = Performing a flash chip erase. +MSG_PROGRAMMING = Programming MCU memory from \`$(TARGET)\'. +MSG_SECURING_FLASH = Protecting chip by setting security bit. +MSG_RESETTING = Resetting MCU. +MSG_DEBUGGING = Opening debug connection with MCU. +MSG_RUNNING = Starting CPU execution. +MSG_READING_CPU_REGS = Reading CPU registers. +MSG_CLEANING_DOC = Cleaning documentation. +MSG_GENERATING_DOC = Generating documentation to \`$(DOC_PATH)\'. + + +# ** ** ** *** ** ** ** ** ** ** ** ** ** ** ** +# MAKE RULES +# ** ** ** *** ** ** ** ** ** ** ** ** ** ** ** + +# Include the make configuration file. +include $(MAKECFG) + +# ** ** TOP-LEVEL RULES ** ** + +# Default goal: build the project. +ifeq ($(TGTTYPE),.a) +.PHONY: all +all: ccversion a lss sym sizes +else +ifeq ($(TGTTYPE),.elf) +.PHONY: all +all: ccversion elf lss sym hex bin sizes +else +$(error $(ERR_TARGET_TYPE)) +endif +endif + +# Clean up the project. +.PHONY: clean +clean: + @echo $(MSG_CLEANING) + -$(VERBOSE_CMD)$(RM) $(BIN) + -$(VERBOSE_CMD)$(RM) $(HEX) + -$(VERBOSE_CMD)$(RM) $(SYM) + -$(VERBOSE_CMD)$(RM) $(LSS) + -$(VERBOSE_CMD)$(RM) $(TARGET) + -$(VERBOSE_CMD)$(RM) $(OBJFILES) + -$(VERBOSE_CMD)$(RM) $(ASFILES) + -$(VERBOSE_CMD)$(RM) $(CPPFILES) + -$(VERBOSE_CMD)$(RM) $(DPNDFILES) + $(VERBOSE_NL) + +# Rebuild the project. +.PHONY: rebuild +rebuild: clean all + +# Display CC version information. +.PHONY: ccversion +ccversion: + @echo + @echo + @$(CC) --version + +# Generate preprocessed files from C source files. +.PHONY: cppfiles +cppfiles: $(CPPFILES) + +# Generate preprocessed assembler files from C and assembler source files. +.PHONY: asfiles +asfiles: $(ASFILES) + +# Generate object files from C and assembler source files. +.PHONY: objfiles +objfiles: $(OBJFILES) + +ifeq ($(TGTTYPE),.a) +# Archive: create A output file from object files. +.PHONY: a +a: $(TARGET) +else +ifeq ($(TGTTYPE),.elf) +# Link: create ELF output file from object files. +.PHONY: elf +elf: $(TARGET) +endif +endif + +# Create extended listing from target output file. +.PHONY: lss +lss: $(LSS) + +# Create symbol table from target output file. +.PHONY: sym +sym: $(SYM) + +ifeq ($(TGTTYPE),.elf) + +# Create Intel HEX image from ELF output file. +.PHONY: hex +hex: $(HEX) + +# Create binary image from ELF output file. +.PHONY: bin +bin: $(BIN) + +endif + +# Display target size information. +.PHONY: sizes +sizes: $(TARGET) + @echo + @echo +ifeq ($(TGTTYPE),.a) + @$(SIZE) -Bxt $< +else +ifeq ($(TGTTYPE),.elf) + @$(SIZE) -Ax $< + @$(SIZE) -Bx $< +endif +endif + @echo + @echo + +ifeq ($(TGTTYPE),.elf) + +# Use ISP instead of JTAGICE mkII when programming. +.PHONY: isp +ifeq ($(filter-out isp verbose,$(MAKECMDGOALS)),) +isp: all +else +isp: + @: +endif + +ifeq ($(findstring isp,$(MAKECMDGOALS)),) + +# Get CPU information. +.PHONY: cpuinfo +cpuinfo: + @echo + @echo $(MSG_GETTING_CPU_INFO) + $(VERBOSE_CMD)$(PROGRAM) cpuinfo +ifneq ($(call LastWord,$(filter cpuinfo chiperase erase program secureflash reset debug run readregs,$(MAKECMDGOALS))),cpuinfo) + @$(SLEEP) $(SLEEPUSB) +else + @echo +endif + +# Stop CPU execution. +.PHONY: halt +halt: +ifeq ($(filter cpuinfo chiperase erase program secureflash reset run readregs,$(MAKECMDGOALS)),) + @echo + @echo $(MSG_HALTING) + $(VERBOSE_CMD)$(PROGRAM) halt +ifneq ($(call LastWord,$(filter halt debug,$(MAKECMDGOALS))),halt) + @$(SLEEP) $(SLEEPUSB) +else + @echo +endif +else + @: +endif + +# Perform a JTAG Chip Erase command. +.PHONY: chiperase +chiperase: + @echo + @echo $(MSG_ERASING_CHIP) + $(VERBOSE_CMD)$(PROGRAM) chiperase +ifneq ($(call LastWord,$(filter cpuinfo chiperase program secureflash reset debug run readregs,$(MAKECMDGOALS))),chiperase) + @$(SLEEP) $(SLEEPUSB) +else + @echo +endif + +# Perform a flash chip erase. +.PHONY: erase +erase: +ifeq ($(filter chiperase program,$(MAKECMDGOALS)),) + @echo + @echo $(MSG_ERASING) + $(VERBOSE_CMD)$(PROGRAM) erase $(FLASH:%=-f%) +ifneq ($(call LastWord,$(filter cpuinfo erase secureflash reset debug run readregs,$(MAKECMDGOALS))),erase) + @$(SLEEP) $(SLEEPUSB) +else + @echo +endif +else + @: +endif + +# Program MCU memory from ELF output file. +.PHONY: program +program: all + @echo + @echo $(MSG_PROGRAMMING) + $(VERBOSE_CMD)$(PROGRAM) program $(FLASH:%=-f%) $(PROG_CLOCK:%=-c%) -e -v -R $(if $(findstring run,$(MAKECMDGOALS)),-r) $(TARGET) +ifneq ($(call LastWord,$(filter cpuinfo chiperase program secureflash debug readregs,$(MAKECMDGOALS))),program) + @$(SLEEP) $(SLEEPUSB) +else + @echo +endif + +# Protect chip by setting security bit. +.PHONY: secureflash +secureflash: + @echo + @echo $(MSG_SECURING_FLASH) + $(VERBOSE_CMD)$(PROGRAM) secureflash +ifneq ($(call LastWord,$(filter cpuinfo chiperase erase program secureflash reset debug run readregs,$(MAKECMDGOALS))),secureflash) + @$(SLEEP) $(SLEEPUSB) +else + @echo +endif + +# Reset MCU. +.PHONY: reset +reset: +ifeq ($(filter program run,$(MAKECMDGOALS)),) + @echo + @echo $(MSG_RESETTING) + $(VERBOSE_CMD)$(PROGRAM) reset +ifneq ($(call LastWord,$(filter cpuinfo chiperase erase secureflash reset debug readregs,$(MAKECMDGOALS))),reset) + @$(SLEEP) $(SLEEPUSB) +else + @echo +endif +else + @: +endif + +# Open a debug connection with the MCU. +.PHONY: debug +debug: + @echo + @echo $(MSG_DEBUGGING) + $(VERBOSE_CMD)$(DBGPROXY) $(FLASH:%=-f%) +ifneq ($(call LastWord,$(filter cpuinfo halt chiperase erase program secureflash reset debug run readregs,$(MAKECMDGOALS))),debug) + @$(SLEEP) $(SLEEPUSB) +else + @echo +endif + +# Start CPU execution. +.PHONY: run +run: +ifeq ($(findstring program,$(MAKECMDGOALS)),) + @echo + @echo $(MSG_RUNNING) + $(VERBOSE_CMD)$(PROGRAM) run $(if $(findstring reset,$(MAKECMDGOALS)),-R) +ifneq ($(call LastWord,$(filter cpuinfo chiperase erase secureflash debug run readregs,$(MAKECMDGOALS))),run) + @$(SLEEP) $(SLEEPUSB) +else + @echo +endif +else + @: +endif + +# Read CPU registers. +.PHONY: readregs +readregs: + @echo + @echo $(MSG_READING_CPU_REGS) + $(VERBOSE_CMD)$(PROGRAM) readregs +ifneq ($(call LastWord,$(filter cpuinfo chiperase erase program secureflash reset debug run readregs,$(MAKECMDGOALS))),readregs) + @$(SLEEP) $(SLEEPUSB) +else + @echo +endif + +else + +# Perform a flash chip erase. +.PHONY: erase +erase: +ifeq ($(findstring program,$(MAKECMDGOALS)),) + @echo + @echo $(MSG_ERASING) + $(VERBOSE_CMD)$(ISP) $(ISPFLAGS) erase f memory flash blankcheck +ifeq ($(call LastWord,$(filter erase secureflash debug run,$(MAKECMDGOALS))),erase) + @echo +endif +else + @: +endif + +# Program MCU memory from ELF output file. +.PHONY: program +program: all + @echo + @echo $(MSG_PROGRAMMING) + $(VERBOSE_CMD)$(ISP) $(ISPFLAGS) erase f memory flash blankcheck loadbuffer $(TARGET) program verify $(if $(findstring run,$(MAKECMDGOALS)),$(if $(findstring secureflash,$(MAKECMDGOALS)),,start $(if $(findstring reset,$(MAKECMDGOALS)),,no)reset 0)) +ifeq ($(call LastWord,$(filter program secureflash debug,$(MAKECMDGOALS))),program) + @echo +endif + +# Protect chip by setting security bit. +.PHONY: secureflash +secureflash: + @echo + @echo $(MSG_SECURING_FLASH) + $(VERBOSE_CMD)$(ISP) $(ISPFLAGS) memory security addrange 0x0 0x0 fillbuffer 0x01 program $(if $(findstring run,$(MAKECMDGOALS)),start $(if $(findstring reset,$(MAKECMDGOALS)),,no)reset 0) +ifeq ($(call LastWord,$(filter erase program secureflash debug,$(MAKECMDGOALS))),secureflash) + @echo +endif + +# Reset MCU. +.PHONY: reset +reset: + @: + +# Open a debug connection with the MCU. +.PHONY: debug +debug: + @echo + @echo $(MSG_DEBUGGING) + $(VERBOSE_CMD)$(DBGPROXY) $(FLASH:%=-f%) +ifeq ($(call LastWord,$(filter erase program secureflash debug run,$(MAKECMDGOALS))),debug) + @echo +endif + +# Start CPU execution. +.PHONY: run +run: +ifeq ($(filter program secureflash,$(MAKECMDGOALS)),) + @echo + @echo $(MSG_RUNNING) + $(VERBOSE_CMD)$(ISP) $(ISPFLAGS) start $(if $(findstring reset,$(MAKECMDGOALS)),,no)reset 0 +ifeq ($(call LastWord,$(filter erase debug run,$(MAKECMDGOALS))),run) + @echo +endif +else + @: +endif + +endif + +endif + +# Build the documentation. +.PHONY: doc +doc: + @echo + @echo $(MSG_GENERATING_DOC) + $(VERBOSE_CMD)cd $(dir $(DOC_CFG)) && $(DOCGEN) $(notdir $(DOC_CFG)) + @echo + +# Clean up the documentation. +.PHONY: cleandoc +cleandoc: + @echo $(MSG_CLEANING_DOC) + -$(VERBOSE_CMD)$(RM) $(DOC_PATH) + $(VERBOSE_NL) + +# Rebuild the documentation. +.PHONY: rebuilddoc +rebuilddoc: cleandoc doc + +# Display main executed commands. +.PHONY: verbose +ifeq ($(filter-out isp verbose,$(MAKECMDGOALS)),) +verbose: all +else +verbose: + @: +endif +ifneq ($(findstring verbose,$(MAKECMDGOALS)),) +# Prefix displaying the following command if and only if verbose is a goal. +VERBOSE_CMD = +# New line displayed if and only if verbose is a goal. +VERBOSE_NL = @echo +else +VERBOSE_CMD = @ +VERBOSE_NL = +endif + +# ** ** COMPILATION RULES ** ** + +# Include silently the dependency files. +-include $(DPNDFILES) + +# The dependency files are not built alone but along with first generation files. +$(DPNDFILES): + +# First generation files depend on make files. +$(CPPFILES) $(ASFILES) $(OBJFILES): Makefile $(MAKECFG) + +ifeq ($(TGTTYPE),.elf) +# Files resulting from linking depend on linker script. +$(TARGET): $(LINKER_SCRIPT) +endif + +# Preprocess: create preprocessed files from C source files. +%.i: %.c %.d + @echo $(MSG_PREPROCESSING) + $(VERBOSE_CMD)$(CPP) $(CPPFLAGS) -MD -MP -MT '$*.i $*.x $*.o' -o $@ $< + @touch $*.d + @touch $@ + $(VERBOSE_NL) + +# Preprocess & compile: create assembler files from C source files. +%.x: %.c %.d + @echo $(MSG_COMPILING) + $(VERBOSE_CMD)$(CC) -S $(CPPFLAGS) -MD -MP -MT '$*.i $*.o' $(CFLAGS) -o $@ $< + @touch $*.d + @touch $@ + $(VERBOSE_NL) + +# Preprocess: create preprocessed files from assembler source files. +%.x: %.S %.d + @echo $(MSG_PREPROCESSING) + $(VERBOSE_CMD)$(CPP) $(CPPFLAGS) -MD -MP -MT '$*.x $*.o' -o $@ $< + @touch $*.d + @touch $@ + $(VERBOSE_NL) + +# Preprocess, compile & assemble: create object files from C source files. +%.o: %.c %.d + @echo $(MSG_COMPILING) + $(VERBOSE_CMD)$(CC) -c $(CPPFLAGS) -MD -MP -MT '$*.i $*.x' $(CFLAGS) -o $@ $< + @touch $*.d + @touch $@ + $(VERBOSE_NL) + +# Preprocess & assemble: create object files from assembler source files. +%.o: %.S %.d + @echo $(MSG_ASSEMBLING) + $(VERBOSE_CMD)$(CC) -c $(CPPFLAGS) -MD -MP -MT '$*.x' $(ASFLAGS) -o $@ $< + @touch $*.d + @touch $@ + $(VERBOSE_NL) + +.PRECIOUS: $(OBJFILES) +ifeq ($(TGTTYPE),.a) +# Archive: create A output file from object files. +.SECONDARY: $(TARGET) +$(TARGET): $(OBJFILES) + @echo $(MSG_ARCHIVING) + $(VERBOSE_CMD)$(AR) $(ARFLAGS) $@ $(filter %.o,$+) + $(VERBOSE_NL) +else +ifeq ($(TGTTYPE),.elf) +# Link: create ELF output file from object files. +.SECONDARY: $(TARGET) +$(TARGET): $(OBJFILES) + @echo $(MSG_LINKING) + $(VERBOSE_CMD)$(CC) $(LDFLAGS) $(filter %.o,$+) $(LOADLIBES) $(LDLIBS) -o $@ + $(VERBOSE_NL) +endif +endif + +# Create extended listing from target output file. +$(LSS): $(TARGET) + @echo $(MSG_EXTENDED_LISTING) + $(VERBOSE_CMD)$(OBJDUMP) -h -S $< > $@ + $(VERBOSE_NL) + +# Create symbol table from target output file. +$(SYM): $(TARGET) + @echo $(MSG_SYMBOL_TABLE) + $(VERBOSE_CMD)$(NM) -n $< > $@ + $(VERBOSE_NL) + +ifeq ($(TGTTYPE),.elf) + +# Create Intel HEX image from ELF output file. +$(HEX): $(TARGET) + @echo $(MSG_IHEX_IMAGE) + $(VERBOSE_CMD)$(OBJCOPY) -O ihex $< $@ + $(VERBOSE_NL) + +# Create binary image from ELF output file. +$(BIN): $(TARGET) + @echo $(MSG_BINARY_IMAGE) + $(VERBOSE_CMD)$(OBJCOPY) -O binary $< $@ + $(VERBOSE_NL) + +endif diff --git a/20080212/Demo/AVR32_UC3/AT32UC3A/GCC/config.mk b/20080212/Demo/AVR32_UC3/AT32UC3A/GCC/config.mk new file mode 100644 index 000000000..16d800543 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/AT32UC3A/GCC/config.mk @@ -0,0 +1,150 @@ +# Hey Emacs, this is a -*- makefile -*- + +# The purpose of this file is to define the build configuration variables used +# by the generic Makefile. See Makefile header for further information. + +# Copyright (c) 2007, Atmel Corporation All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation and/ +# or other materials provided with the distribution. +# +# 3. The name of ATMEL may not be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND +# SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, +# INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +# OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + +# Base paths +PRJ_PATH = ../.. +APPS_PATH = $(PRJ_PATH)/APPLICATIONS +BRDS_PATH = $(PRJ_PATH)/BOARDS +COMP_PATH = $(PRJ_PATH)/COMPONENTS +DRVR_PATH = $(PRJ_PATH)/DRIVERS +SERV_PATH = $(PRJ_PATH)/SERVICES +UTIL_PATH = $(PRJ_PATH)/UTILS + +# CPU architecture: {ap|uc} +ARCH = uc + +# Part: {none|ap7xxx|uc3xxxxx} +PART = uc3a0512 + +# Flash memories: [{cfi|internal}@address,size]... +FLASH = internal@0x80000000,512Kb + +# Clock source to use when programming: [{xtal|extclk|int}] +PROG_CLOCK = xtal + +# Device/Platform/Board include path +PLATFORM_INC_PATH = \ + $(BRDS_PATH)/ + +# Target name: {*.a|*.elf} +TARGET = $(PART)-rtosdemo.elf + +# Definitions: [-D name[=definition]...] [-U name...] +# Things that might be added to DEFS: +# BOARD Board used: {EVKxxxx} +# EXT_BOARD Extension board used (if any): {EXTxxxx} +DEFS = -D BOARD=EVK1100 + +# Include path +INC_PATH = \ + $(UTIL_PATH)/ \ + $(UTIL_PATH)/PREPROCESSOR/ \ + $(SERV_PATH)/USB/CLASS/DFU/EXAMPLES/ISP/BOOT/ \ + $(DRVR_PATH)/INTC/ \ + $(DRVR_PATH)/PM/ \ + $(DRVR_PATH)/GPIO/ \ + $(DRVR_PATH)/TC/ \ + ../../../../Source/portable/GCC/AVR32_UC3/ \ + ../../../../Source/include/ \ + ../../../Common/include/ \ + ../../ + +# C source files +CSRCS = \ + $(BRDS_PATH)/EVK1100/led.c \ + $(DRVR_PATH)/INTC/intc.c \ + $(DRVR_PATH)/PM/pm.c \ + $(DRVR_PATH)/GPIO/gpio.c \ + $(DRVR_PATH)/TC/tc.c \ + ../../../../Source/portable/GCC/AVR32_UC3/port.c \ + ../../../../Source/portable/MemMang/heap_3.c \ + ../../../../Source/list.c \ + ../../../../Source/queue.c \ + ../../../../Source/tasks.c \ + ../../../Common/Minimal/BlockQ.c \ + ../../../Common/Minimal/comtest.c \ + ../../../Common/Minimal/death.c \ + ../../../Common/Minimal/dynamic.c \ + ../../../Common/Minimal/flash.c \ + ../../../Common/Minimal/flop.c \ + ../../../Common/Minimal/integer.c \ + ../../../Common/Minimal/PollQ.c \ + ../../../Common/Minimal/semtest.c \ + ../../ParTest/ParTest.c \ + ../../serial/serial.c \ + ../../main.c + +# Assembler source files +ASSRCS = \ + $(SERV_PATH)/USB/CLASS/DFU/EXAMPLES/ISP/BOOT/trampoline.S \ + ../../../../Source/portable/GCC/AVR32_UC3/exception.S + +# Library path +LIB_PATH = + +# Libraries to link with the project +LIBS = + +# Linker script file if any +LINKER_SCRIPT = $(UTIL_PATH)/LINKER_SCRIPTS/AT32UC3A/0512/GCC/link_uc3a0512.lds + +# Options to request or suppress warnings: [-fsyntax-only] [-pedantic[-errors]] [-w] [-Wwarning...] +# For further details, refer to the chapter "GCC Command Options" of the GCC manual. +WARNINGS = -Wall + +# Options for debugging: [-g]... +# For further details, refer to the chapter "GCC Command Options" of the GCC manual. +DEBUG = -g + +# Options that control optimization: [-O[0|1|2|3|s]]... +# For further details, refer to the chapter "GCC Command Options" of the GCC manual. +OPTIMIZATION = -O0 -ffunction-sections -fdata-sections + +# Extra flags to use when preprocessing +CPP_EXTRA_FLAGS = + +# Extra flags to use when compiling +C_EXTRA_FLAGS = + +# Extra flags to use when assembling +AS_EXTRA_FLAGS = + +# Extra flags to use when linking +LD_EXTRA_FLAGS = -Wl,--gc-sections -Wl,-e,_trampoline + +# Documentation path +DOC_PATH = \ + ../../DOC/ + +# Documentation configuration file +DOC_CFG = \ + ../doxyfile.doxygen diff --git a/20080212/Demo/AVR32_UC3/AT32UC3A/GCC/gdb.ini b/20080212/Demo/AVR32_UC3/AT32UC3A/GCC/gdb.ini new file mode 100644 index 000000000..418c606cf --- /dev/null +++ b/20080212/Demo/AVR32_UC3/AT32UC3A/GCC/gdb.ini @@ -0,0 +1,29 @@ +target extended-remote :1024 +symbol uc3a0512-rtosdemo.elf + +b _handle_Unrecoverable_Exception +b _handle_TLB_Multiple_Hit +b _handle_Bus_Error_Data_Fetch +b _handle_Bus_Error_Instruction_Fetch +b _handle_NMI +b _handle_Instruction_Address +b _handle_ITLB_Protection +b _handle_Breakpoint +b _handle_Illegal_Opcode +b _handle_Unimplemented_Instruction +b _handle_Privilege_Violation +b _handle_Floating_Point +b _handle_Coprocessor_Absent +b _handle_Data_Address_Read +b _handle_Data_Address_Write +b _handle_DTLB_Protection_Read +b _handle_DTLB_Protection_Write +b _handle_DTLB_Modified +b _handle_ITLB_Miss +b _handle_DTLB_Miss_Read +b _handle_DTLB_Miss_Write + +define current_task +printf "Task name: %s\n", ((tskTCB *)pxCurrentTCB)->pcTaskName +printf "pxTopOfStack: %x\n", ((tskTCB *)pxCurrentTCB)->pxTopOfStack +end diff --git a/20080212/Demo/AVR32_UC3/AT32UC3A/GCC/gdb_cmdfile.txt b/20080212/Demo/AVR32_UC3/AT32UC3A/GCC/gdb_cmdfile.txt new file mode 100644 index 000000000..dfe1fc174 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/AT32UC3A/GCC/gdb_cmdfile.txt @@ -0,0 +1,29 @@ +target extended-remote :4711 +symbol uc3a0512-rtosdemo.elf + +b _handle_Unrecoverable_Exception +b _handle_TLB_Multiple_Hit +b _handle_Bus_Error_Data_Fetch +b _handle_Bus_Error_Instruction_Fetch +b _handle_NMI +b _handle_Instruction_Address +b _handle_ITLB_Protection +b _handle_Breakpoint +b _handle_Illegal_Opcode +b _handle_Unimplemented_Instruction +b _handle_Privilege_Violation +b _handle_Floating_Point +b _handle_Coprocessor_Absent +b _handle_Data_Address_Read +b _handle_Data_Address_Write +b _handle_DTLB_Protection_Read +b _handle_DTLB_Protection_Write +b _handle_DTLB_Modified +b _handle_ITLB_Miss +b _handle_DTLB_Miss_Read +b _handle_DTLB_Miss_Write + +define current_task +printf "Task name: %s\n", ((tskTCB *)pxCurrentTCB)->pcTaskName +printf "pxTopOfStack: %x\n", ((tskTCB *)pxCurrentTCB)->pxTopOfStack +end diff --git a/20080212/Demo/AVR32_UC3/AT32UC3A/IAR/Debug/Obj/rtosdemo.pbd b/20080212/Demo/AVR32_UC3/AT32UC3A/IAR/Debug/Obj/rtosdemo.pbd new file mode 100644 index 000000000..235cec16f --- /dev/null +++ b/20080212/Demo/AVR32_UC3/AT32UC3A/IAR/Debug/Obj/rtosdemo.pbd @@ -0,0 +1,27 @@ +This is an internal working file generated by the Source Browser. +20:15 21s +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\AVR32_UC3\AT32UC3A\IAR\Debug\Obj\BlockQ.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\AVR32_UC3\AT32UC3A\IAR\Debug\Obj\ParTest.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\AVR32_UC3\AT32UC3A\IAR\Debug\Obj\PollQ.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\AVR32_UC3\AT32UC3A\IAR\Debug\Obj\comtest.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\AVR32_UC3\AT32UC3A\IAR\Debug\Obj\death.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\AVR32_UC3\AT32UC3A\IAR\Debug\Obj\dynamic.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\AVR32_UC3\AT32UC3A\IAR\Debug\Obj\flash.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\AVR32_UC3\AT32UC3A\IAR\Debug\Obj\flop.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\AVR32_UC3\AT32UC3A\IAR\Debug\Obj\gpio.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\AVR32_UC3\AT32UC3A\IAR\Debug\Obj\heap_3.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\AVR32_UC3\AT32UC3A\IAR\Debug\Obj\intc.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\AVR32_UC3\AT32UC3A\IAR\Debug\Obj\integer.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\AVR32_UC3\AT32UC3A\IAR\Debug\Obj\led.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\AVR32_UC3\AT32UC3A\IAR\Debug\Obj\list.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\AVR32_UC3\AT32UC3A\IAR\Debug\Obj\main.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\AVR32_UC3\AT32UC3A\IAR\Debug\Obj\pm.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\AVR32_UC3\AT32UC3A\IAR\Debug\Obj\port.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\AVR32_UC3\AT32UC3A\IAR\Debug\Obj\queue.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\AVR32_UC3\AT32UC3A\IAR\Debug\Obj\read.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\AVR32_UC3\AT32UC3A\IAR\Debug\Obj\semtest.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\AVR32_UC3\AT32UC3A\IAR\Debug\Obj\serial.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\AVR32_UC3\AT32UC3A\IAR\Debug\Obj\tasks.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\AVR32_UC3\AT32UC3A\IAR\Debug\Obj\tc.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\AVR32_UC3\AT32UC3A\IAR\Debug\Obj\usart.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\AVR32_UC3\AT32UC3A\IAR\Debug\Obj\write.pbi diff --git a/20080212/Demo/AVR32_UC3/AT32UC3A/IAR/rtosdemo.ewd b/20080212/Demo/AVR32_UC3/AT32UC3A/IAR/rtosdemo.ewd new file mode 100644 index 000000000..aeb046dff --- /dev/null +++ b/20080212/Demo/AVR32_UC3/AT32UC3A/IAR/rtosdemo.ewd @@ -0,0 +1,373 @@ + + + + 1 + + Debug + + AVR32 + + 1 + + C-SPY + 2 + + 0 + 1 + 1 + + + + + + + + + + + + + + + + + JTAGICEMKIIAVR32 + 3 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + SIMAVR32 + 2 + + 0 + 1 + 1 + + + + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin + 1 + + + + + Release + + AVR32 + + 0 + + C-SPY + 2 + + 0 + 1 + 0 + + + + + + + + + + + + + + + + + JTAGICEMKIIAVR32 + 3 + + 1 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + SIMAVR32 + 2 + + 0 + 1 + 0 + + + + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin + 1 + + + + + + diff --git a/20080212/Demo/AVR32_UC3/AT32UC3A/IAR/rtosdemo.ewp b/20080212/Demo/AVR32_UC3/AT32UC3A/IAR/rtosdemo.ewp new file mode 100644 index 000000000..c2e97e827 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/AT32UC3A/IAR/rtosdemo.ewp @@ -0,0 +1,1726 @@ + + + + 1 + + Debug + + AVR32 + + 1 + + General + 2 + + 0 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCAVR32 + 3 + + 5 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AAVR32 + 2 + + 0 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JAVATOC + 0 + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + XLINK + 2 + + 14 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + XAR + 2 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + AVR32 + + 0 + + General + 2 + + 0 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCAVR32 + 3 + + 5 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AAVR32 + 2 + + 0 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JAVATOC + 0 + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + XLINK + 2 + + 14 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + XAR + 2 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + DLIB + + $PROJ_DIR$\..\..\..\..\Source\portable\IAR\AVR32_UC3\read.c + + + $PROJ_DIR$\..\..\SERVICES\USB\CLASS\DFU\EXAMPLES\ISP\BOOT\trampoline.s82 + + + $PROJ_DIR$\..\..\..\..\Source\portable\IAR\AVR32_UC3\write.c + + + + Drivers + + $PROJ_DIR$\..\..\DRIVERS\GPIO\gpio.c + + + $PROJ_DIR$\..\..\DRIVERS\INTC\intc.c + + + $PROJ_DIR$\..\..\BOARDS\EVK1100\led.c + + + $PROJ_DIR$\..\..\DRIVERS\PM\pm.c + + + $PROJ_DIR$\..\..\DRIVERS\TC\tc.c + + + $PROJ_DIR$\..\..\DRIVERS\USART\usart.c + + + + FreeRTOS + + AVR32_UC3 + + $PROJ_DIR$\..\..\..\..\Source\portable\IAR\AVR32_UC3\exception.s82 + + + $PROJ_DIR$\..\..\..\..\Source\portable\IAR\AVR32_UC3\port.c + + + + Common_demo + + $PROJ_DIR$\..\..\..\Common\Minimal\BlockQ.c + + + $PROJ_DIR$\..\..\..\Common\Minimal\comtest.c + + + $PROJ_DIR$\..\..\..\Common\Minimal\death.c + + + $PROJ_DIR$\..\..\..\Common\Minimal\dynamic.c + + + $PROJ_DIR$\..\..\..\Common\Minimal\flash.c + + + $PROJ_DIR$\..\..\..\Common\Minimal\flop.c + + + $PROJ_DIR$\..\..\..\Common\Minimal\integer.c + + + $PROJ_DIR$\..\..\..\Common\Minimal\PollQ.c + + + $PROJ_DIR$\..\..\..\Common\Minimal\semtest.c + + + + Source + + $PROJ_DIR$\..\..\..\..\Source\portable\MemMang\heap_3.c + + + $PROJ_DIR$\..\..\..\..\Source\list.c + + + $PROJ_DIR$\..\..\..\..\Source\queue.c + + + $PROJ_DIR$\..\..\..\..\Source\tasks.c + + + + + $PROJ_DIR$\..\..\main.c + + + $PROJ_DIR$\..\..\ParTest\ParTest.c + + + $PROJ_DIR$\..\..\serial\serial.c + + + + diff --git a/20080212/Demo/AVR32_UC3/AT32UC3A/IAR/rtosdemo.eww b/20080212/Demo/AVR32_UC3/AT32UC3A/IAR/rtosdemo.eww new file mode 100644 index 000000000..2294aacb5 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/AT32UC3A/IAR/rtosdemo.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\rtosdemo.ewp + + + + + diff --git a/20080212/Demo/AVR32_UC3/AT32UC3A/IAR/settings/rtosdemo.cspy.bat b/20080212/Demo/AVR32_UC3/AT32UC3A/IAR/settings/rtosdemo.cspy.bat new file mode 100644 index 000000000..410ecbabd --- /dev/null +++ b/20080212/Demo/AVR32_UC3/AT32UC3A/IAR/settings/rtosdemo.cspy.bat @@ -0,0 +1,32 @@ +@REM This bat file has been generated by the IAR Embeddded Workbench +@REM C-SPY interactive debugger,as an aid to preparing a command +@REM line for running the cspybat command line utility with the +@REM appropriate settings. +@REM +@REM After making some adjustments to this file, you can launch cspybat +@REM by typing the name of this file followed by the name of the debug +@REM file (usually an ubrof file). Note that this file is generated +@REM every time a new debug session is initialized, so you may want to +@REM move or rename the file before making changes. +@REM +@REM Note: some command line arguments cannot be properly generated +@REM by this process. Specifically, the plugin which is responsible +@REM for the Terminal I/O window (and other C runtime functionality) +@REM comes in a special version for cspybat, and the name of that +@REM plugin dll is not known when generating this file. It resides in +@REM the $TOOLKIT_DIR$\bin folder and is usually called XXXbat.dll or +@REM XXXlibsupportbat.dll, where XXX is the name of the corresponding +@REM tool chain. Replace the '' parameter +@REM below with the appropriate file name. Other plugins loaded by +@REM C-SPY are usually not needed by, or will not work in, cspybat +@REM but they are listed at the end of this file for reference. + + +"C:\Devtools\IAR Systems\Embedded Workbench 4.0\common\bin\cspybat" "C:\Devtools\IAR Systems\Embedded Workbench 4.0\avr32\bin\avr32proc.dll" "C:\Devtools\IAR Systems\Embedded Workbench 4.0\avr32\bin\avr32jtagicemkII.dll" %1 --plugin "C:\Devtools\IAR Systems\Embedded Workbench 4.0\avr32\bin\" --backend -B "--core" "avr32a" "--avr32_simd_instructions" "disabled" "--avr32_dsp_instructions" "enabled" "--avr32_rmw_instructions" "enabled" "-p" "C:\Devtools\IAR Systems\Embedded Workbench 4.0\avr32\config\iouc3a0512.ddf" "-d" "jtagicemkII" "--drv_communication" "USB" "--jtagice_clock" "100000" + + +@REM loaded plugins: +@REM avr32LibSupport.dll +@REM C:\Devtools\IAR Systems\Embedded Workbench 4.0\common\plugins\CodeCoverage\CodeCoverage.dll +@REM C:\Devtools\IAR Systems\Embedded Workbench 4.0\common\plugins\Profiling\Profiling.dll +@REM C:\Devtools\IAR Systems\Embedded Workbench 4.0\common\plugins\stack\stack.dll diff --git a/20080212/Demo/AVR32_UC3/AT32UC3A/IAR/settings/rtosdemo.dbgdt b/20080212/Demo/AVR32_UC3/AT32UC3A/IAR/settings/rtosdemo.dbgdt new file mode 100644 index 000000000..33f4649c2 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/AT32UC3A/IAR/settings/rtosdemo.dbgdt @@ -0,0 +1,5 @@ + + + + + diff --git a/20080212/Demo/AVR32_UC3/AT32UC3A/IAR/settings/rtosdemo.dni b/20080212/Demo/AVR32_UC3/AT32UC3A/IAR/settings/rtosdemo.dni new file mode 100644 index 000000000..4520689fb --- /dev/null +++ b/20080212/Demo/AVR32_UC3/AT32UC3A/IAR/settings/rtosdemo.dni @@ -0,0 +1,5 @@ +[Breakpoints] +Count=0 +[TraceHelper] +Enabled=0 +ShowSource=1 diff --git a/20080212/Demo/AVR32_UC3/AT32UC3A/IAR/settings/rtosdemo.wsdt b/20080212/Demo/AVR32_UC3/AT32UC3A/IAR/settings/rtosdemo.wsdt new file mode 100644 index 000000000..c5a40e8b6 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/AT32UC3A/IAR/settings/rtosdemo.wsdt @@ -0,0 +1,97 @@ + + + + + + rtosdemo/Debug + + + + + + + 124 + 27 + 27 + 27 + + + + + + + + TabID-27032-1807 + Workspace + Workspace + + + rtosdemo + + + + + 0 + + + + + 0 + + + 1000000 + 1000000 + + + 1 + + + + + + + iaridepm1 + + + + + + + + + + -2 + -2 + 938 + 198 + -2 + -2 + 200 + 200 + 142857 + 203666 + 142857 + 957230 + + + + + + + + + + + + + + + + + + + + + + + diff --git a/20080212/Demo/AVR32_UC3/AT32UC3A/doxyfile.doxygen b/20080212/Demo/AVR32_UC3/AT32UC3A/doxyfile.doxygen new file mode 100644 index 000000000..08f4a05a1 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/AT32UC3A/doxyfile.doxygen @@ -0,0 +1,232 @@ +# Doxyfile 1.4.7 + +#--------------------------------------------------------------------------- +# Project related configuration options +#--------------------------------------------------------------------------- +PROJECT_NAME = "AVR32 UC3 - FreeRTOS Real Time Kernel" +PROJECT_NUMBER = +OUTPUT_DIRECTORY = ../DOC +CREATE_SUBDIRS = NO +OUTPUT_LANGUAGE = English +USE_WINDOWS_ENCODING = YES +BRIEF_MEMBER_DESC = YES +REPEAT_BRIEF = YES +ABBREVIATE_BRIEF = +ALWAYS_DETAILED_SEC = NO +INLINE_INHERITED_MEMB = NO +FULL_PATH_NAMES = NO +STRIP_FROM_PATH = +STRIP_FROM_INC_PATH = +SHORT_NAMES = NO +JAVADOC_AUTOBRIEF = YES +MULTILINE_CPP_IS_BRIEF = NO +DETAILS_AT_TOP = YES +INHERIT_DOCS = YES +SEPARATE_MEMBER_PAGES = NO +TAB_SIZE = 4 +ALIASES = +OPTIMIZE_OUTPUT_FOR_C = YES +OPTIMIZE_OUTPUT_JAVA = NO +BUILTIN_STL_SUPPORT = NO +DISTRIBUTE_GROUP_DOC = NO +SUBGROUPING = YES +#--------------------------------------------------------------------------- +# Build related configuration options +#--------------------------------------------------------------------------- +EXTRACT_ALL = YES +EXTRACT_PRIVATE = NO +EXTRACT_STATIC = YES +EXTRACT_LOCAL_CLASSES = YES +EXTRACT_LOCAL_METHODS = NO +HIDE_UNDOC_MEMBERS = NO +HIDE_UNDOC_CLASSES = NO +HIDE_FRIEND_COMPOUNDS = NO +HIDE_IN_BODY_DOCS = NO +INTERNAL_DOCS = YES +CASE_SENSE_NAMES = YES +HIDE_SCOPE_NAMES = NO +SHOW_INCLUDE_FILES = YES +INLINE_INFO = YES +SORT_MEMBER_DOCS = YES +SORT_BRIEF_DOCS = YES +SORT_BY_SCOPE_NAME = NO +GENERATE_TODOLIST = YES +GENERATE_TESTLIST = YES +GENERATE_BUGLIST = YES +GENERATE_DEPRECATEDLIST= YES +ENABLED_SECTIONS = +MAX_INITIALIZER_LINES = 30 +SHOW_USED_FILES = NO +SHOW_DIRECTORIES = NO +FILE_VERSION_FILTER = +#--------------------------------------------------------------------------- +# configuration options related to warning and progress messages +#--------------------------------------------------------------------------- +QUIET = YES +WARNINGS = YES +WARN_IF_UNDOCUMENTED = YES +WARN_IF_DOC_ERROR = YES +WARN_NO_PARAMDOC = NO +WARN_FORMAT = "$file:$line: $text" +WARN_LOGFILE = +#--------------------------------------------------------------------------- +# configuration options related to the input files +#--------------------------------------------------------------------------- +INPUT = ./../ ./../../../Source ./../../Common/include ./../../Common/Minimal +FILE_PATTERNS = *.c \ + *.h \ + *.S +RECURSIVE = YES +EXCLUDE = +EXCLUDE_SYMLINKS = NO +EXCLUDE_PATTERNS = +EXAMPLE_PATH = +EXAMPLE_PATTERNS = +EXAMPLE_RECURSIVE = NO +IMAGE_PATH = ./../ +INPUT_FILTER = +FILTER_PATTERNS = +FILTER_SOURCE_FILES = NO +#--------------------------------------------------------------------------- +# configuration options related to source browsing +#--------------------------------------------------------------------------- +SOURCE_BROWSER = YES +INLINE_SOURCES = YES +STRIP_CODE_COMMENTS = YES +REFERENCED_BY_RELATION = YES +REFERENCES_RELATION = YES +REFERENCES_LINK_SOURCE = YES +USE_HTAGS = NO +VERBATIM_HEADERS = YES +#--------------------------------------------------------------------------- +# configuration options related to the alphabetical class index +#--------------------------------------------------------------------------- +ALPHABETICAL_INDEX = NO +COLS_IN_ALPHA_INDEX = 5 +IGNORE_PREFIX = +#--------------------------------------------------------------------------- +# configuration options related to the HTML output +#--------------------------------------------------------------------------- +GENERATE_HTML = YES +HTML_OUTPUT = +HTML_FILE_EXTENSION = .html +HTML_HEADER = +HTML_FOOTER = +HTML_STYLESHEET = +HTML_ALIGN_MEMBERS = YES +GENERATE_HTMLHELP = NO +CHM_FILE = +HHC_LOCATION = +GENERATE_CHI = NO +BINARY_TOC = NO +TOC_EXPAND = NO +DISABLE_INDEX = NO +ENUM_VALUES_PER_LINE = 4 +GENERATE_TREEVIEW = YES +TREEVIEW_WIDTH = 250 +#--------------------------------------------------------------------------- +# configuration options related to the LaTeX output +#--------------------------------------------------------------------------- +GENERATE_LATEX = NO +LATEX_OUTPUT = latex +LATEX_CMD_NAME = latex +MAKEINDEX_CMD_NAME = makeindex +COMPACT_LATEX = NO +PAPER_TYPE = a4wide +EXTRA_PACKAGES = +LATEX_HEADER = +PDF_HYPERLINKS = NO +USE_PDFLATEX = NO +LATEX_BATCHMODE = NO +LATEX_HIDE_INDICES = NO +#--------------------------------------------------------------------------- +# configuration options related to the RTF output +#--------------------------------------------------------------------------- +GENERATE_RTF = NO +RTF_OUTPUT = RTF +COMPACT_RTF = NO +RTF_HYPERLINKS = YES +RTF_STYLESHEET_FILE = +RTF_EXTENSIONS_FILE = +#--------------------------------------------------------------------------- +# configuration options related to the man page output +#--------------------------------------------------------------------------- +GENERATE_MAN = NO +MAN_OUTPUT = man +MAN_EXTENSION = .3 +MAN_LINKS = NO +#--------------------------------------------------------------------------- +# configuration options related to the XML output +#--------------------------------------------------------------------------- +GENERATE_XML = NO +XML_OUTPUT = xml +XML_SCHEMA = +XML_DTD = +XML_PROGRAMLISTING = YES +#--------------------------------------------------------------------------- +# configuration options for the AutoGen Definitions output +#--------------------------------------------------------------------------- +GENERATE_AUTOGEN_DEF = NO +#--------------------------------------------------------------------------- +# configuration options related to the Perl module output +#--------------------------------------------------------------------------- +GENERATE_PERLMOD = NO +PERLMOD_LATEX = NO +PERLMOD_PRETTY = YES +PERLMOD_MAKEVAR_PREFIX = +#--------------------------------------------------------------------------- +# Configuration options related to the preprocessor +#--------------------------------------------------------------------------- +ENABLE_PREPROCESSING = YES +MACRO_EXPANSION = YES +EXPAND_ONLY_PREDEF = YES +SEARCH_INCLUDES = YES +INCLUDE_PATH = ../../../../../BOARDS/ +INCLUDE_FILE_PATTERNS = +PREDEFINED = __GNUC__=4 \ + __attribute__()= \ + __AVR32__=1 \ + __AVR32_UC3A0512__=1 \ + __AVR32_ABI_COMPILER__ \ + BOARD=EVK1100 +EXPAND_AS_DEFINED = +SKIP_FUNCTION_MACROS = YES +#--------------------------------------------------------------------------- +# Configuration::additions related to external references +#--------------------------------------------------------------------------- +TAGFILES = +GENERATE_TAGFILE = +ALLEXTERNALS = NO +EXTERNAL_GROUPS = YES +PERL_PATH = /usr/bin/perl +#--------------------------------------------------------------------------- +# Configuration options related to the dot tool +#--------------------------------------------------------------------------- +CLASS_DIAGRAMS = NO +HIDE_UNDOC_RELATIONS = YES +HAVE_DOT = NO +CLASS_GRAPH = NO +COLLABORATION_GRAPH = NO +GROUP_GRAPHS = NO +UML_LOOK = YES +TEMPLATE_RELATIONS = YES +INCLUDE_GRAPH = NO +INCLUDED_BY_GRAPH = NO +CALL_GRAPH = NO +CALLER_GRAPH = NO +GRAPHICAL_HIERARCHY = NO +DIRECTORY_GRAPH = NO +DOT_IMAGE_FORMAT = png +DOT_PATH = +DOTFILE_DIRS = +MAX_DOT_GRAPH_WIDTH = 1024 +MAX_DOT_GRAPH_HEIGHT = 1024 +MAX_DOT_GRAPH_DEPTH = 0 +DOT_TRANSPARENT = NO +DOT_MULTI_TARGETS = NO +GENERATE_LEGEND = YES +DOT_CLEANUP = YES +#--------------------------------------------------------------------------- +# Configuration::additions related to the search engine +#--------------------------------------------------------------------------- +SEARCHENGINE = NO diff --git a/20080212/Demo/AVR32_UC3/AT32UC3B/GCC/Makefile b/20080212/Demo/AVR32_UC3/AT32UC3B/GCC/Makefile new file mode 100644 index 000000000..6f51ddb10 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/AT32UC3B/GCC/Makefile @@ -0,0 +1,618 @@ +# Hey Emacs, this is a -*- makefile -*- + +# Goals available on make command line: +# +# [all] Default goal: build the project. +# clean Clean up the project. +# rebuild Rebuild the project. +# ccversion Display CC version information. +# cppfiles file.i Generate preprocessed files from C source files. +# asfiles file.x Generate preprocessed assembler files from C and assembler source files. +# objfiles file.o Generate object files from C and assembler source files. +# a file.a Archive: create A output file from object files. +# elf file.elf Link: create ELF output file from object files. +# lss file.lss Create extended listing from target output file. +# sym file.sym Create symbol table from target output file. +# hex file.hex Create Intel HEX image from ELF output file. +# bin file.bin Create binary image from ELF output file. +# sizes Display target size information. +# isp Use ISP instead of JTAGICE mkII when programming. +# cpuinfo Get CPU information. +# halt Stop CPU execution. +# chiperase Perform a JTAG Chip Erase command. +# erase Perform a flash chip erase. +# program Program MCU memory from ELF output file. +# secureflash Protect chip by setting security bit. +# reset Reset MCU. +# debug Open a debug connection with the MCU. +# run Start CPU execution. +# readregs Read CPU registers. +# doc Build the documentation. +# cleandoc Clean up the documentation. +# rebuilddoc Rebuild the documentation. +# verbose Display main executed commands. + +# Copyright (c) 2007, Atmel Corporation All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation and/ +# or other materials provided with the distribution. +# +# 3. The name of ATMEL may not be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND +# SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, +# INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +# OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + +# ** ** ** *** ** ** ** ** ** ** ** ** ** ** ** +# ENVIRONMENT SETTINGS +# ** ** ** *** ** ** ** ** ** ** ** ** ** ** ** + +FirstWord = $(if $(1),$(word 1,$(1))) +LastWord = $(if $(1),$(word $(words $(1)),$(1))) + +MAKE = make +MAKECFG = config.mk +TGTTYPE = $(suffix $(TARGET)) + +RM = rm -Rf + +AR = avr32-ar +ARFLAGS = rcs + +CPP = $(CC) -E +CPPFLAGS = -march=$(ARCH) -mpart=$(PART) $(WARNINGS) $(DEFS) \ + $(PLATFORM_INC_PATH:%=-I%) $(INC_PATH:%=-I%) $(CPP_EXTRA_FLAGS) +DPNDFILES = $(CSRCS:.c=.d) $(ASSRCS:.S=.d) +CPPFILES = $(CSRCS:.c=.i) + +CC = avr32-gcc +CFLAGS = $(DEBUG) $(OPTIMIZATION) $(C_EXTRA_FLAGS) \ + $(PLATFORM_INC_PATH:%=-Wa,-I%) $(INC_PATH:%=-Wa,-I%) $(AS_EXTRA_FLAGS) +ASFILES = $(CSRCS:.c=.x) $(ASSRCS:.S=.x) + +AS = avr32-as +ASFLAGS = $(DEBUG) \ + $(PLATFORM_INC_PATH:%=-Wa,-I%) $(INC_PATH:%=-Wa,-I%) $(AS_EXTRA_FLAGS) +OBJFILES = $(CSRCS:.c=.o) $(ASSRCS:.S=.o) + +LD = avr32-ld +LDFLAGS = -march=$(ARCH) -mpart=$(PART) \ + $(LIB_PATH:%=-L%) $(LINKER_SCRIPT:%=-T%) $(LD_EXTRA_FLAGS) +LOADLIBES = +LDLIBS = $(LIBS:%=-l%) + +OBJDUMP = avr32-objdump +LSS = $(TARGET:$(TGTTYPE)=.lss) + +NM = avr32-nm +SYM = $(TARGET:$(TGTTYPE)=.sym) + +OBJCOPY = avr32-objcopy +HEX = $(TARGET:$(TGTTYPE)=.hex) +BIN = $(TARGET:$(TGTTYPE)=.bin) + +SIZE = avr32-size + +SLEEP = sleep +SLEEPUSB = 9 + +PROGRAM = avr32program + +ISP = batchisp +ISPFLAGS = -device at32$(PART) -hardware usb -operation + +DBGPROXY = avr32gdbproxy + +DOCGEN = doxygen + + +# ** ** ** *** ** ** ** ** ** ** ** ** ** ** ** +# MESSAGES +# ** ** ** *** ** ** ** ** ** ** ** ** ** ** ** + +ERR_TARGET_TYPE = Target type not supported: `$(TGTTYPE)' +MSG_CLEANING = Cleaning project. +MSG_PREPROCESSING = Preprocessing \`$<\' to \`$@\'. +MSG_COMPILING = Compiling \`$<\' to \`$@\'. +MSG_ASSEMBLING = Assembling \`$<\' to \`$@\'. +MSG_ARCHIVING = Archiving to \`$@\'. +MSG_LINKING = Linking to \`$@\'. +MSG_EXTENDED_LISTING = Creating extended listing to \`$@\'. +MSG_SYMBOL_TABLE = Creating symbol table to \`$@\'. +MSG_IHEX_IMAGE = Creating Intel HEX image to \`$@\'. +MSG_BINARY_IMAGE = Creating binary image to \`$@\'. +MSG_GETTING_CPU_INFO = Getting CPU information. +MSG_HALTING = Stopping CPU execution. +MSG_ERASING_CHIP = Performing a JTAG Chip Erase command. +MSG_ERASING = Performing a flash chip erase. +MSG_PROGRAMMING = Programming MCU memory from \`$(TARGET)\'. +MSG_SECURING_FLASH = Protecting chip by setting security bit. +MSG_RESETTING = Resetting MCU. +MSG_DEBUGGING = Opening debug connection with MCU. +MSG_RUNNING = Starting CPU execution. +MSG_READING_CPU_REGS = Reading CPU registers. +MSG_CLEANING_DOC = Cleaning documentation. +MSG_GENERATING_DOC = Generating documentation to \`$(DOC_PATH)\'. + + +# ** ** ** *** ** ** ** ** ** ** ** ** ** ** ** +# MAKE RULES +# ** ** ** *** ** ** ** ** ** ** ** ** ** ** ** + +# Include the make configuration file. +include $(MAKECFG) + +# ** ** TOP-LEVEL RULES ** ** + +# Default goal: build the project. +ifeq ($(TGTTYPE),.a) +.PHONY: all +all: ccversion a lss sym sizes +else +ifeq ($(TGTTYPE),.elf) +.PHONY: all +all: ccversion elf lss sym hex bin sizes +else +$(error $(ERR_TARGET_TYPE)) +endif +endif + +# Clean up the project. +.PHONY: clean +clean: + @echo $(MSG_CLEANING) + -$(VERBOSE_CMD)$(RM) $(BIN) + -$(VERBOSE_CMD)$(RM) $(HEX) + -$(VERBOSE_CMD)$(RM) $(SYM) + -$(VERBOSE_CMD)$(RM) $(LSS) + -$(VERBOSE_CMD)$(RM) $(TARGET) + -$(VERBOSE_CMD)$(RM) $(OBJFILES) + -$(VERBOSE_CMD)$(RM) $(ASFILES) + -$(VERBOSE_CMD)$(RM) $(CPPFILES) + -$(VERBOSE_CMD)$(RM) $(DPNDFILES) + $(VERBOSE_NL) + +# Rebuild the project. +.PHONY: rebuild +rebuild: clean all + +# Display CC version information. +.PHONY: ccversion +ccversion: + @echo + @echo + @$(CC) --version + +# Generate preprocessed files from C source files. +.PHONY: cppfiles +cppfiles: $(CPPFILES) + +# Generate preprocessed assembler files from C and assembler source files. +.PHONY: asfiles +asfiles: $(ASFILES) + +# Generate object files from C and assembler source files. +.PHONY: objfiles +objfiles: $(OBJFILES) + +ifeq ($(TGTTYPE),.a) +# Archive: create A output file from object files. +.PHONY: a +a: $(TARGET) +else +ifeq ($(TGTTYPE),.elf) +# Link: create ELF output file from object files. +.PHONY: elf +elf: $(TARGET) +endif +endif + +# Create extended listing from target output file. +.PHONY: lss +lss: $(LSS) + +# Create symbol table from target output file. +.PHONY: sym +sym: $(SYM) + +ifeq ($(TGTTYPE),.elf) + +# Create Intel HEX image from ELF output file. +.PHONY: hex +hex: $(HEX) + +# Create binary image from ELF output file. +.PHONY: bin +bin: $(BIN) + +endif + +# Display target size information. +.PHONY: sizes +sizes: $(TARGET) + @echo + @echo +ifeq ($(TGTTYPE),.a) + @$(SIZE) -Bxt $< +else +ifeq ($(TGTTYPE),.elf) + @$(SIZE) -Ax $< + @$(SIZE) -Bx $< +endif +endif + @echo + @echo + +ifeq ($(TGTTYPE),.elf) + +# Use ISP instead of JTAGICE mkII when programming. +.PHONY: isp +ifeq ($(filter-out isp verbose,$(MAKECMDGOALS)),) +isp: all +else +isp: + @: +endif + +ifeq ($(findstring isp,$(MAKECMDGOALS)),) + +# Get CPU information. +.PHONY: cpuinfo +cpuinfo: + @echo + @echo $(MSG_GETTING_CPU_INFO) + $(VERBOSE_CMD)$(PROGRAM) cpuinfo +ifneq ($(call LastWord,$(filter cpuinfo chiperase erase program secureflash reset debug run readregs,$(MAKECMDGOALS))),cpuinfo) + @$(SLEEP) $(SLEEPUSB) +else + @echo +endif + +# Stop CPU execution. +.PHONY: halt +halt: +ifeq ($(filter cpuinfo chiperase erase program secureflash reset run readregs,$(MAKECMDGOALS)),) + @echo + @echo $(MSG_HALTING) + $(VERBOSE_CMD)$(PROGRAM) halt +ifneq ($(call LastWord,$(filter halt debug,$(MAKECMDGOALS))),halt) + @$(SLEEP) $(SLEEPUSB) +else + @echo +endif +else + @: +endif + +# Perform a JTAG Chip Erase command. +.PHONY: chiperase +chiperase: + @echo + @echo $(MSG_ERASING_CHIP) + $(VERBOSE_CMD)$(PROGRAM) chiperase +ifneq ($(call LastWord,$(filter cpuinfo chiperase program secureflash reset debug run readregs,$(MAKECMDGOALS))),chiperase) + @$(SLEEP) $(SLEEPUSB) +else + @echo +endif + +# Perform a flash chip erase. +.PHONY: erase +erase: +ifeq ($(filter chiperase program,$(MAKECMDGOALS)),) + @echo + @echo $(MSG_ERASING) + $(VERBOSE_CMD)$(PROGRAM) erase $(FLASH:%=-f%) +ifneq ($(call LastWord,$(filter cpuinfo erase secureflash reset debug run readregs,$(MAKECMDGOALS))),erase) + @$(SLEEP) $(SLEEPUSB) +else + @echo +endif +else + @: +endif + +# Program MCU memory from ELF output file. +.PHONY: program +program: all + @echo + @echo $(MSG_PROGRAMMING) + $(VERBOSE_CMD)$(PROGRAM) program $(FLASH:%=-f%) $(PROG_CLOCK:%=-c%) -e -v -R $(if $(findstring run,$(MAKECMDGOALS)),-r) $(TARGET) +ifneq ($(call LastWord,$(filter cpuinfo chiperase program secureflash debug readregs,$(MAKECMDGOALS))),program) + @$(SLEEP) $(SLEEPUSB) +else + @echo +endif + +# Protect chip by setting security bit. +.PHONY: secureflash +secureflash: + @echo + @echo $(MSG_SECURING_FLASH) + $(VERBOSE_CMD)$(PROGRAM) secureflash +ifneq ($(call LastWord,$(filter cpuinfo chiperase erase program secureflash reset debug run readregs,$(MAKECMDGOALS))),secureflash) + @$(SLEEP) $(SLEEPUSB) +else + @echo +endif + +# Reset MCU. +.PHONY: reset +reset: +ifeq ($(filter program run,$(MAKECMDGOALS)),) + @echo + @echo $(MSG_RESETTING) + $(VERBOSE_CMD)$(PROGRAM) reset +ifneq ($(call LastWord,$(filter cpuinfo chiperase erase secureflash reset debug readregs,$(MAKECMDGOALS))),reset) + @$(SLEEP) $(SLEEPUSB) +else + @echo +endif +else + @: +endif + +# Open a debug connection with the MCU. +.PHONY: debug +debug: + @echo + @echo $(MSG_DEBUGGING) + $(VERBOSE_CMD)$(DBGPROXY) $(FLASH:%=-f%) +ifneq ($(call LastWord,$(filter cpuinfo halt chiperase erase program secureflash reset debug run readregs,$(MAKECMDGOALS))),debug) + @$(SLEEP) $(SLEEPUSB) +else + @echo +endif + +# Start CPU execution. +.PHONY: run +run: +ifeq ($(findstring program,$(MAKECMDGOALS)),) + @echo + @echo $(MSG_RUNNING) + $(VERBOSE_CMD)$(PROGRAM) run $(if $(findstring reset,$(MAKECMDGOALS)),-R) +ifneq ($(call LastWord,$(filter cpuinfo chiperase erase secureflash debug run readregs,$(MAKECMDGOALS))),run) + @$(SLEEP) $(SLEEPUSB) +else + @echo +endif +else + @: +endif + +# Read CPU registers. +.PHONY: readregs +readregs: + @echo + @echo $(MSG_READING_CPU_REGS) + $(VERBOSE_CMD)$(PROGRAM) readregs +ifneq ($(call LastWord,$(filter cpuinfo chiperase erase program secureflash reset debug run readregs,$(MAKECMDGOALS))),readregs) + @$(SLEEP) $(SLEEPUSB) +else + @echo +endif + +else + +# Perform a flash chip erase. +.PHONY: erase +erase: +ifeq ($(findstring program,$(MAKECMDGOALS)),) + @echo + @echo $(MSG_ERASING) + $(VERBOSE_CMD)$(ISP) $(ISPFLAGS) erase f memory flash blankcheck +ifeq ($(call LastWord,$(filter erase secureflash debug run,$(MAKECMDGOALS))),erase) + @echo +endif +else + @: +endif + +# Program MCU memory from ELF output file. +.PHONY: program +program: all + @echo + @echo $(MSG_PROGRAMMING) + $(VERBOSE_CMD)$(ISP) $(ISPFLAGS) erase f memory flash blankcheck loadbuffer $(TARGET) program verify $(if $(findstring run,$(MAKECMDGOALS)),$(if $(findstring secureflash,$(MAKECMDGOALS)),,start $(if $(findstring reset,$(MAKECMDGOALS)),,no)reset 0)) +ifeq ($(call LastWord,$(filter program secureflash debug,$(MAKECMDGOALS))),program) + @echo +endif + +# Protect chip by setting security bit. +.PHONY: secureflash +secureflash: + @echo + @echo $(MSG_SECURING_FLASH) + $(VERBOSE_CMD)$(ISP) $(ISPFLAGS) memory security addrange 0x0 0x0 fillbuffer 0x01 program $(if $(findstring run,$(MAKECMDGOALS)),start $(if $(findstring reset,$(MAKECMDGOALS)),,no)reset 0) +ifeq ($(call LastWord,$(filter erase program secureflash debug,$(MAKECMDGOALS))),secureflash) + @echo +endif + +# Reset MCU. +.PHONY: reset +reset: + @: + +# Open a debug connection with the MCU. +.PHONY: debug +debug: + @echo + @echo $(MSG_DEBUGGING) + $(VERBOSE_CMD)$(DBGPROXY) $(FLASH:%=-f%) +ifeq ($(call LastWord,$(filter erase program secureflash debug run,$(MAKECMDGOALS))),debug) + @echo +endif + +# Start CPU execution. +.PHONY: run +run: +ifeq ($(filter program secureflash,$(MAKECMDGOALS)),) + @echo + @echo $(MSG_RUNNING) + $(VERBOSE_CMD)$(ISP) $(ISPFLAGS) start $(if $(findstring reset,$(MAKECMDGOALS)),,no)reset 0 +ifeq ($(call LastWord,$(filter erase debug run,$(MAKECMDGOALS))),run) + @echo +endif +else + @: +endif + +endif + +endif + +# Build the documentation. +.PHONY: doc +doc: + @echo + @echo $(MSG_GENERATING_DOC) + $(VERBOSE_CMD)cd $(dir $(DOC_CFG)) && $(DOCGEN) $(notdir $(DOC_CFG)) + @echo + +# Clean up the documentation. +.PHONY: cleandoc +cleandoc: + @echo $(MSG_CLEANING_DOC) + -$(VERBOSE_CMD)$(RM) $(DOC_PATH) + $(VERBOSE_NL) + +# Rebuild the documentation. +.PHONY: rebuilddoc +rebuilddoc: cleandoc doc + +# Display main executed commands. +.PHONY: verbose +ifeq ($(filter-out isp verbose,$(MAKECMDGOALS)),) +verbose: all +else +verbose: + @: +endif +ifneq ($(findstring verbose,$(MAKECMDGOALS)),) +# Prefix displaying the following command if and only if verbose is a goal. +VERBOSE_CMD = +# New line displayed if and only if verbose is a goal. +VERBOSE_NL = @echo +else +VERBOSE_CMD = @ +VERBOSE_NL = +endif + +# ** ** COMPILATION RULES ** ** + +# Include silently the dependency files. +-include $(DPNDFILES) + +# The dependency files are not built alone but along with first generation files. +$(DPNDFILES): + +# First generation files depend on make files. +$(CPPFILES) $(ASFILES) $(OBJFILES): Makefile $(MAKECFG) + +ifeq ($(TGTTYPE),.elf) +# Files resulting from linking depend on linker script. +$(TARGET): $(LINKER_SCRIPT) +endif + +# Preprocess: create preprocessed files from C source files. +%.i: %.c %.d + @echo $(MSG_PREPROCESSING) + $(VERBOSE_CMD)$(CPP) $(CPPFLAGS) -MD -MP -MT '$*.i $*.x $*.o' -o $@ $< + @touch $*.d + @touch $@ + $(VERBOSE_NL) + +# Preprocess & compile: create assembler files from C source files. +%.x: %.c %.d + @echo $(MSG_COMPILING) + $(VERBOSE_CMD)$(CC) -S $(CPPFLAGS) -MD -MP -MT '$*.i $*.o' $(CFLAGS) -o $@ $< + @touch $*.d + @touch $@ + $(VERBOSE_NL) + +# Preprocess: create preprocessed files from assembler source files. +%.x: %.S %.d + @echo $(MSG_PREPROCESSING) + $(VERBOSE_CMD)$(CPP) $(CPPFLAGS) -MD -MP -MT '$*.x $*.o' -o $@ $< + @touch $*.d + @touch $@ + $(VERBOSE_NL) + +# Preprocess, compile & assemble: create object files from C source files. +%.o: %.c %.d + @echo $(MSG_COMPILING) + $(VERBOSE_CMD)$(CC) -c $(CPPFLAGS) -MD -MP -MT '$*.i $*.x' $(CFLAGS) -o $@ $< + @touch $*.d + @touch $@ + $(VERBOSE_NL) + +# Preprocess & assemble: create object files from assembler source files. +%.o: %.S %.d + @echo $(MSG_ASSEMBLING) + $(VERBOSE_CMD)$(CC) -c $(CPPFLAGS) -MD -MP -MT '$*.x' $(ASFLAGS) -o $@ $< + @touch $*.d + @touch $@ + $(VERBOSE_NL) + +.PRECIOUS: $(OBJFILES) +ifeq ($(TGTTYPE),.a) +# Archive: create A output file from object files. +.SECONDARY: $(TARGET) +$(TARGET): $(OBJFILES) + @echo $(MSG_ARCHIVING) + $(VERBOSE_CMD)$(AR) $(ARFLAGS) $@ $(filter %.o,$+) + $(VERBOSE_NL) +else +ifeq ($(TGTTYPE),.elf) +# Link: create ELF output file from object files. +.SECONDARY: $(TARGET) +$(TARGET): $(OBJFILES) + @echo $(MSG_LINKING) + $(VERBOSE_CMD)$(CC) $(LDFLAGS) $(filter %.o,$+) $(LOADLIBES) $(LDLIBS) -o $@ + $(VERBOSE_NL) +endif +endif + +# Create extended listing from target output file. +$(LSS): $(TARGET) + @echo $(MSG_EXTENDED_LISTING) + $(VERBOSE_CMD)$(OBJDUMP) -h -S $< > $@ + $(VERBOSE_NL) + +# Create symbol table from target output file. +$(SYM): $(TARGET) + @echo $(MSG_SYMBOL_TABLE) + $(VERBOSE_CMD)$(NM) -n $< > $@ + $(VERBOSE_NL) + +ifeq ($(TGTTYPE),.elf) + +# Create Intel HEX image from ELF output file. +$(HEX): $(TARGET) + @echo $(MSG_IHEX_IMAGE) + $(VERBOSE_CMD)$(OBJCOPY) -O ihex $< $@ + $(VERBOSE_NL) + +# Create binary image from ELF output file. +$(BIN): $(TARGET) + @echo $(MSG_BINARY_IMAGE) + $(VERBOSE_CMD)$(OBJCOPY) -O binary $< $@ + $(VERBOSE_NL) + +endif diff --git a/20080212/Demo/AVR32_UC3/AT32UC3B/GCC/config.mk b/20080212/Demo/AVR32_UC3/AT32UC3B/GCC/config.mk new file mode 100644 index 000000000..6caf8ef1c --- /dev/null +++ b/20080212/Demo/AVR32_UC3/AT32UC3B/GCC/config.mk @@ -0,0 +1,150 @@ +# Hey Emacs, this is a -*- makefile -*- + +# The purpose of this file is to define the build configuration variables used +# by the generic Makefile. See Makefile header for further information. + +# Copyright (c) 2007, Atmel Corporation All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation and/ +# or other materials provided with the distribution. +# +# 3. The name of ATMEL may not be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND +# SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, +# INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +# OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + +# Base paths +PRJ_PATH = ../.. +APPS_PATH = $(PRJ_PATH)/APPLICATIONS +BRDS_PATH = $(PRJ_PATH)/BOARDS +COMP_PATH = $(PRJ_PATH)/COMPONENTS +DRVR_PATH = $(PRJ_PATH)/DRIVERS +SERV_PATH = $(PRJ_PATH)/SERVICES +UTIL_PATH = $(PRJ_PATH)/UTILS + +# CPU architecture: {ap|uc} +ARCH = uc + +# Part: {none|ap7xxx|uc3xxxxx} +PART = uc3b0256 + +# Flash memories: [{cfi|internal}@address,size]... +FLASH = internal@0x80000000,256Kb + +# Clock source to use when programming: [{xtal|extclk|int}] +PROG_CLOCK = xtal + +# Device/Platform/Board include path +PLATFORM_INC_PATH = \ + $(BRDS_PATH)/ + +# Target name: {*.a|*.elf} +TARGET = $(PART)-rtosdemo.elf + +# Definitions: [-D name[=definition]...] [-U name...] +# Things that might be added to DEFS: +# BOARD Board used: {EVKxxxx} +# EXT_BOARD Extension board used (if any): {EXTxxxx} +DEFS = -D BOARD=EVK1101 + +# Include path +INC_PATH = \ + $(UTIL_PATH)/ \ + $(UTIL_PATH)/PREPROCESSOR/ \ + $(SERV_PATH)/USB/CLASS/DFU/EXAMPLES/ISP/BOOT/ \ + $(DRVR_PATH)/INTC/ \ + $(DRVR_PATH)/PM/ \ + $(DRVR_PATH)/GPIO/ \ + $(DRVR_PATH)/TC/ \ + ../../../../Source/portable/GCC/AVR32_UC3/ \ + ../../../../Source/include/ \ + ../../../Common/include/ \ + ../../ + +# C source files +CSRCS = \ + $(BRDS_PATH)/EVK1101/led.c \ + $(DRVR_PATH)/INTC/intc.c \ + $(DRVR_PATH)/PM/pm.c \ + $(DRVR_PATH)/GPIO/gpio.c \ + $(DRVR_PATH)/TC/tc.c \ + ../../../../Source/portable/GCC/AVR32_UC3/port.c \ + ../../../../Source/portable/MemMang/heap_3.c \ + ../../../../Source/list.c \ + ../../../../Source/queue.c \ + ../../../../Source/tasks.c \ + ../../../Common/Minimal/BlockQ.c \ + ../../../Common/Minimal/comtest.c \ + ../../../Common/Minimal/death.c \ + ../../../Common/Minimal/dynamic.c \ + ../../../Common/Minimal/flash.c \ + ../../../Common/Minimal/flop.c \ + ../../../Common/Minimal/integer.c \ + ../../../Common/Minimal/PollQ.c \ + ../../../Common/Minimal/semtest.c \ + ../../ParTest/ParTest.c \ + ../../serial/serial.c \ + ../../main.c + +# Assembler source files +ASSRCS = \ + $(SERV_PATH)/USB/CLASS/DFU/EXAMPLES/ISP/BOOT/trampoline.S \ + ../../../../Source/portable/GCC/AVR32_UC3/exception.S + +# Library path +LIB_PATH = + +# Libraries to link with the project +LIBS = + +# Linker script file if any +LINKER_SCRIPT = $(UTIL_PATH)/LINKER_SCRIPTS/AT32UC3B/0256/GCC/link_uc3b0256.lds + +# Options to request or suppress warnings: [-fsyntax-only] [-pedantic[-errors]] [-w] [-Wwarning...] +# For further details, refer to the chapter "GCC Command Options" of the GCC manual. +WARNINGS = -Wall + +# Options for debugging: [-g]... +# For further details, refer to the chapter "GCC Command Options" of the GCC manual. +DEBUG = -g + +# Options that control optimization: [-O[0|1|2|3|s]]... +# For further details, refer to the chapter "GCC Command Options" of the GCC manual. +OPTIMIZATION = -O0 -ffunction-sections -fdata-sections + +# Extra flags to use when preprocessing +CPP_EXTRA_FLAGS = + +# Extra flags to use when compiling +C_EXTRA_FLAGS = + +# Extra flags to use when assembling +AS_EXTRA_FLAGS = + +# Extra flags to use when linking +LD_EXTRA_FLAGS = -Wl,--gc-sections -Wl,-e,_trampoline + +# Documentation path +DOC_PATH = \ + ../../DOC/ + +# Documentation configuration file +DOC_CFG = \ + ../doxyfile.doxygen diff --git a/20080212/Demo/AVR32_UC3/AT32UC3B/GCC/gdb_cmdfile.txt b/20080212/Demo/AVR32_UC3/AT32UC3B/GCC/gdb_cmdfile.txt new file mode 100644 index 000000000..851f6f2e1 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/AT32UC3B/GCC/gdb_cmdfile.txt @@ -0,0 +1,29 @@ +target extended-remote :4711 +symbol uc3b0256-rtosdemo.elf + +b _handle_Unrecoverable_Exception +b _handle_TLB_Multiple_Hit +b _handle_Bus_Error_Data_Fetch +b _handle_Bus_Error_Instruction_Fetch +b _handle_NMI +b _handle_Instruction_Address +b _handle_ITLB_Protection +b _handle_Breakpoint +b _handle_Illegal_Opcode +b _handle_Unimplemented_Instruction +b _handle_Privilege_Violation +b _handle_Floating_Point +b _handle_Coprocessor_Absent +b _handle_Data_Address_Read +b _handle_Data_Address_Write +b _handle_DTLB_Protection_Read +b _handle_DTLB_Protection_Write +b _handle_DTLB_Modified +b _handle_ITLB_Miss +b _handle_DTLB_Miss_Read +b _handle_DTLB_Miss_Write + +define current_task +printf "Task name: %s\n", ((tskTCB *)pxCurrentTCB)->pcTaskName +printf "pxTopOfStack: %x\n", ((tskTCB *)pxCurrentTCB)->pxTopOfStack +end diff --git a/20080212/Demo/AVR32_UC3/AT32UC3B/doxyfile.doxygen b/20080212/Demo/AVR32_UC3/AT32UC3B/doxyfile.doxygen new file mode 100644 index 000000000..411dbadc4 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/AT32UC3B/doxyfile.doxygen @@ -0,0 +1,232 @@ +# Doxyfile 1.4.7 + +#--------------------------------------------------------------------------- +# Project related configuration options +#--------------------------------------------------------------------------- +PROJECT_NAME = "AVR32 UC3 - FreeRTOS Real Time Kernel" +PROJECT_NUMBER = +OUTPUT_DIRECTORY = ../DOC +CREATE_SUBDIRS = NO +OUTPUT_LANGUAGE = English +USE_WINDOWS_ENCODING = YES +BRIEF_MEMBER_DESC = YES +REPEAT_BRIEF = YES +ABBREVIATE_BRIEF = +ALWAYS_DETAILED_SEC = NO +INLINE_INHERITED_MEMB = NO +FULL_PATH_NAMES = NO +STRIP_FROM_PATH = +STRIP_FROM_INC_PATH = +SHORT_NAMES = NO +JAVADOC_AUTOBRIEF = YES +MULTILINE_CPP_IS_BRIEF = NO +DETAILS_AT_TOP = YES +INHERIT_DOCS = YES +SEPARATE_MEMBER_PAGES = NO +TAB_SIZE = 4 +ALIASES = +OPTIMIZE_OUTPUT_FOR_C = YES +OPTIMIZE_OUTPUT_JAVA = NO +BUILTIN_STL_SUPPORT = NO +DISTRIBUTE_GROUP_DOC = NO +SUBGROUPING = YES +#--------------------------------------------------------------------------- +# Build related configuration options +#--------------------------------------------------------------------------- +EXTRACT_ALL = YES +EXTRACT_PRIVATE = NO +EXTRACT_STATIC = YES +EXTRACT_LOCAL_CLASSES = YES +EXTRACT_LOCAL_METHODS = NO +HIDE_UNDOC_MEMBERS = NO +HIDE_UNDOC_CLASSES = NO +HIDE_FRIEND_COMPOUNDS = NO +HIDE_IN_BODY_DOCS = NO +INTERNAL_DOCS = YES +CASE_SENSE_NAMES = YES +HIDE_SCOPE_NAMES = NO +SHOW_INCLUDE_FILES = YES +INLINE_INFO = YES +SORT_MEMBER_DOCS = YES +SORT_BRIEF_DOCS = YES +SORT_BY_SCOPE_NAME = NO +GENERATE_TODOLIST = YES +GENERATE_TESTLIST = YES +GENERATE_BUGLIST = YES +GENERATE_DEPRECATEDLIST= YES +ENABLED_SECTIONS = +MAX_INITIALIZER_LINES = 30 +SHOW_USED_FILES = NO +SHOW_DIRECTORIES = NO +FILE_VERSION_FILTER = +#--------------------------------------------------------------------------- +# configuration options related to warning and progress messages +#--------------------------------------------------------------------------- +QUIET = YES +WARNINGS = YES +WARN_IF_UNDOCUMENTED = YES +WARN_IF_DOC_ERROR = YES +WARN_NO_PARAMDOC = NO +WARN_FORMAT = "$file:$line: $text" +WARN_LOGFILE = +#--------------------------------------------------------------------------- +# configuration options related to the input files +#--------------------------------------------------------------------------- +INPUT = ./../ ./../../../Source ./../../Common/include ./../../Common/Minimal +FILE_PATTERNS = *.c \ + *.h \ + *.S +RECURSIVE = YES +EXCLUDE = +EXCLUDE_SYMLINKS = NO +EXCLUDE_PATTERNS = +EXAMPLE_PATH = +EXAMPLE_PATTERNS = +EXAMPLE_RECURSIVE = NO +IMAGE_PATH = ./../ +INPUT_FILTER = +FILTER_PATTERNS = +FILTER_SOURCE_FILES = NO +#--------------------------------------------------------------------------- +# configuration options related to source browsing +#--------------------------------------------------------------------------- +SOURCE_BROWSER = YES +INLINE_SOURCES = YES +STRIP_CODE_COMMENTS = YES +REFERENCED_BY_RELATION = YES +REFERENCES_RELATION = YES +REFERENCES_LINK_SOURCE = YES +USE_HTAGS = NO +VERBATIM_HEADERS = YES +#--------------------------------------------------------------------------- +# configuration options related to the alphabetical class index +#--------------------------------------------------------------------------- +ALPHABETICAL_INDEX = NO +COLS_IN_ALPHA_INDEX = 5 +IGNORE_PREFIX = +#--------------------------------------------------------------------------- +# configuration options related to the HTML output +#--------------------------------------------------------------------------- +GENERATE_HTML = YES +HTML_OUTPUT = +HTML_FILE_EXTENSION = .html +HTML_HEADER = +HTML_FOOTER = +HTML_STYLESHEET = +HTML_ALIGN_MEMBERS = YES +GENERATE_HTMLHELP = NO +CHM_FILE = +HHC_LOCATION = +GENERATE_CHI = NO +BINARY_TOC = NO +TOC_EXPAND = NO +DISABLE_INDEX = NO +ENUM_VALUES_PER_LINE = 4 +GENERATE_TREEVIEW = YES +TREEVIEW_WIDTH = 250 +#--------------------------------------------------------------------------- +# configuration options related to the LaTeX output +#--------------------------------------------------------------------------- +GENERATE_LATEX = NO +LATEX_OUTPUT = latex +LATEX_CMD_NAME = latex +MAKEINDEX_CMD_NAME = makeindex +COMPACT_LATEX = NO +PAPER_TYPE = a4wide +EXTRA_PACKAGES = +LATEX_HEADER = +PDF_HYPERLINKS = NO +USE_PDFLATEX = NO +LATEX_BATCHMODE = NO +LATEX_HIDE_INDICES = NO +#--------------------------------------------------------------------------- +# configuration options related to the RTF output +#--------------------------------------------------------------------------- +GENERATE_RTF = NO +RTF_OUTPUT = RTF +COMPACT_RTF = NO +RTF_HYPERLINKS = YES +RTF_STYLESHEET_FILE = +RTF_EXTENSIONS_FILE = +#--------------------------------------------------------------------------- +# configuration options related to the man page output +#--------------------------------------------------------------------------- +GENERATE_MAN = NO +MAN_OUTPUT = man +MAN_EXTENSION = .3 +MAN_LINKS = NO +#--------------------------------------------------------------------------- +# configuration options related to the XML output +#--------------------------------------------------------------------------- +GENERATE_XML = NO +XML_OUTPUT = xml +XML_SCHEMA = +XML_DTD = +XML_PROGRAMLISTING = YES +#--------------------------------------------------------------------------- +# configuration options for the AutoGen Definitions output +#--------------------------------------------------------------------------- +GENERATE_AUTOGEN_DEF = NO +#--------------------------------------------------------------------------- +# configuration options related to the Perl module output +#--------------------------------------------------------------------------- +GENERATE_PERLMOD = NO +PERLMOD_LATEX = NO +PERLMOD_PRETTY = YES +PERLMOD_MAKEVAR_PREFIX = +#--------------------------------------------------------------------------- +# Configuration options related to the preprocessor +#--------------------------------------------------------------------------- +ENABLE_PREPROCESSING = YES +MACRO_EXPANSION = YES +EXPAND_ONLY_PREDEF = YES +SEARCH_INCLUDES = YES +INCLUDE_PATH = ../../../../../BOARDS/ +INCLUDE_FILE_PATTERNS = +PREDEFINED = __GNUC__=4 \ + __attribute__()= \ + __AVR32__=1 \ + __AVR32_UC3B0256__=1 \ + __AVR32_ABI_COMPILER__ \ + BOARD=EVK1101 +EXPAND_AS_DEFINED = +SKIP_FUNCTION_MACROS = YES +#--------------------------------------------------------------------------- +# Configuration::additions related to external references +#--------------------------------------------------------------------------- +TAGFILES = +GENERATE_TAGFILE = +ALLEXTERNALS = NO +EXTERNAL_GROUPS = YES +PERL_PATH = /usr/bin/perl +#--------------------------------------------------------------------------- +# Configuration options related to the dot tool +#--------------------------------------------------------------------------- +CLASS_DIAGRAMS = NO +HIDE_UNDOC_RELATIONS = YES +HAVE_DOT = NO +CLASS_GRAPH = NO +COLLABORATION_GRAPH = NO +GROUP_GRAPHS = NO +UML_LOOK = YES +TEMPLATE_RELATIONS = YES +INCLUDE_GRAPH = NO +INCLUDED_BY_GRAPH = NO +CALL_GRAPH = NO +CALLER_GRAPH = NO +GRAPHICAL_HIERARCHY = NO +DIRECTORY_GRAPH = NO +DOT_IMAGE_FORMAT = png +DOT_PATH = +DOTFILE_DIRS = +MAX_DOT_GRAPH_WIDTH = 1024 +MAX_DOT_GRAPH_HEIGHT = 1024 +MAX_DOT_GRAPH_DEPTH = 0 +DOT_TRANSPARENT = NO +DOT_MULTI_TARGETS = NO +GENERATE_LEGEND = YES +DOT_CLEANUP = YES +#--------------------------------------------------------------------------- +# Configuration::additions related to the search engine +#--------------------------------------------------------------------------- +SEARCHENGINE = NO diff --git a/20080212/Demo/AVR32_UC3/BOARDS/EVK1100/evk1100.h b/20080212/Demo/AVR32_UC3/BOARDS/EVK1100/evk1100.h new file mode 100644 index 000000000..2905fff22 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/BOARDS/EVK1100/evk1100.h @@ -0,0 +1,325 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief AT32UC3A EVK1100 board header file. + * + * This file contains definitions and services related to the features of the + * EVK1100 board. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 AT32UC3A devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef _EVK1100_H_ +#define _EVK1100_H_ + +#include "compiler.h" + +#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling. +# include "led.h" +#endif // __AVR32_ABI_COMPILER__ + + +/*! \name Oscillator Definitions + */ +//! @{ + +// RCOsc has no custom calibration by default. Set the following definition to +// the appropriate value if a custom RCOsc calibration has been applied to your +// part. +//#define FRCOSC 115200 //!< RCOsc frequency: Hz. + +#define FOSC32 32768 //!< Osc32 frequency: Hz. +#define OSC32_STARTUP 3 //!< Osc32 startup time: RCOsc periods. + +#define FOSC0 12000000 //!< Osc0 frequency: Hz. +#define OSC0_STARTUP 3 //!< Osc0 startup time: RCOsc periods. + +// Osc1 crystal is not mounted by default. Set the following definitions to the +// appropriate values if a custom Osc1 crystal is mounted on your board. +//#define FOSC1 12000000 //!< Osc1 frequency: Hz. +//#define OSC1_STARTUP 3 //!< Osc1 startup time: RCOsc periods. + +//! @} + + +/*! \name SDRAM Definitions + */ +//! @{ + +//! Part header file of used SDRAM(s). +#define SDRAM_PART_HDR "MT48LC16M16A2TG7E/mt48lc16m16a2tg7e.h" + +//! Data bus width to use the SDRAM(s) with (16 or 32 bits; always 16 bits on +//! UC3). +#define SDRAM_DBW 16 + +//! @} + + +/*! \name USB Definitions + */ +//! @{ + +//! Multiplexed pin used for USB_ID: AVR32_USBB_USB_ID_x_x. +//! To be selected according to the AVR32_USBB_USB_ID_x_x_PIN and +//! AVR32_USBB_USB_ID_x_x_FUNCTION definitions from . +#define USB_ID AVR32_USBB_USB_ID_0_0 + +//! Multiplexed pin used for USB_VBOF: AVR32_USBB_USB_VBOF_x_x. +//! To be selected according to the AVR32_USBB_USB_VBOF_x_x_PIN and +//! AVR32_USBB_USB_VBOF_x_x_FUNCTION definitions from . +#ifdef EVK1100_REVA +# define USB_VBOF AVR32_USBB_USB_VBOF_0_0 +#else +# define USB_VBOF AVR32_USBB_USB_VBOF_0_1 +#endif + +//! Active level of the USB_VBOF output pin. +#ifdef EVK1100_REVA +# define USB_VBOF_ACTIVE_LEVEL HIGH +#else +# define USB_VBOF_ACTIVE_LEVEL LOW +#endif + +//! USB overcurrent detection pin. +#ifdef EVK1100_REVA +# define USB_OVERCURRENT_DETECT_PIN AVR32_PIN_PB18 +#else +# define USB_OVERCURRENT_DETECT_PIN AVR32_PIN_PX33 +#endif + +//! @} + + +//! GPIO connection of the MAC PHY PWR_DOWN/INT signal. +#ifdef EVK1100_REVA +# define MACB_INTERRUPT_PIN AVR32_PIN_PX12 +#else +# define MACB_INTERRUPT_PIN AVR32_PIN_PA24 +#endif + + +//! Number of LEDs. +#define LED_COUNT 8 + +/*! \name GPIO Connections of LEDs + */ +//! @{ +#ifdef EVK1100_REVA +# define LED0_GPIO AVR32_PIN_PX13 +# define LED1_GPIO AVR32_PIN_PX14 +# define LED2_GPIO AVR32_PIN_PX15 +# define LED3_GPIO AVR32_PIN_PX16 +# define LED4_GPIO AVR32_PIN_PB19 +# define LED5_GPIO AVR32_PIN_PB20 +# define LED6_GPIO AVR32_PIN_PB21 +# define LED7_GPIO AVR32_PIN_PB22 +#else +# define LED0_GPIO AVR32_PIN_PB27 +# define LED1_GPIO AVR32_PIN_PB28 +# define LED2_GPIO AVR32_PIN_PB29 +# define LED3_GPIO AVR32_PIN_PB30 +# define LED4_GPIO AVR32_PIN_PB19 +# define LED5_GPIO AVR32_PIN_PB20 +# define LED6_GPIO AVR32_PIN_PB21 +# define LED7_GPIO AVR32_PIN_PB22 +#endif +//! @} + +/*! \name PWM Channels of LEDs + */ +//! @{ +#define LED0_PWM (-1) +#define LED1_PWM (-1) +#define LED2_PWM (-1) +#define LED3_PWM (-1) +#define LED4_PWM 0 +#define LED5_PWM 1 +#define LED6_PWM 2 +#define LED7_PWM 3 +//! @} + +/*! \name PWM Functions of LEDs + */ +//! @{ +#define LED0_PWM_FUNCTION (-1) +#define LED1_PWM_FUNCTION (-1) +#define LED2_PWM_FUNCTION (-1) +#define LED3_PWM_FUNCTION (-1) +#define LED4_PWM_FUNCTION AVR32_PWM_PWM_0_FUNCTION +#define LED5_PWM_FUNCTION AVR32_PWM_PWM_1_FUNCTION +#define LED6_PWM_FUNCTION AVR32_PWM_PWM_2_FUNCTION +#define LED7_PWM_FUNCTION AVR32_PWM_PWM_3_FUNCTION +//! @} + +/*! \name Color Identifiers of LEDs to Use with LED Functions + */ +//! @{ +#ifdef EVK1100_REVA +# define LED_MONO0_GREEN LED4 +# define LED_MONO1_GREEN LED5 +# define LED_MONO2_GREEN LED6 +# define LED_MONO3_GREEN LED7 +# define LED_BI0_GREEN LED1 +# define LED_BI0_RED LED0 +# define LED_BI1_GREEN LED3 +# define LED_BI1_RED LED2 +#else +# define LED_MONO0_GREEN LED0 +# define LED_MONO1_GREEN LED1 +# define LED_MONO2_GREEN LED2 +# define LED_MONO3_GREEN LED3 +# define LED_BI0_GREEN LED5 +# define LED_BI0_RED LED4 +# define LED_BI1_GREEN LED7 +# define LED_BI1_RED LED6 +#endif +//! @} + + +/*! \name GPIO Connections of Push Buttons + */ +//! @{ +#ifdef EVK1100_REVA +# define GPIO_PUSH_BUTTON_0 AVR32_PIN_PB28 +# define GPIO_PUSH_BUTTON_1 AVR32_PIN_PB29 +# define GPIO_PUSH_BUTTON_2 AVR32_PIN_PB27 +#else +# define GPIO_PUSH_BUTTON_0 AVR32_PIN_PX16 +# define GPIO_PUSH_BUTTON_1 AVR32_PIN_PX19 +# define GPIO_PUSH_BUTTON_2 AVR32_PIN_PX22 +#endif +//! @} + + +/*! \name GPIO Connections of the Joystick + */ +//! @{ +#define GPIO_JOYSTICK_PUSH AVR32_PIN_PA20 +#define GPIO_JOYSTICK_LEFT AVR32_PIN_PA25 +#define GPIO_JOYSTICK_RIGHT AVR32_PIN_PA28 +#define GPIO_JOYSTICK_UP AVR32_PIN_PA26 +#define GPIO_JOYSTICK_DOWN AVR32_PIN_PA27 +//! @} + + +/*! \name ADC Connection of the Potentiometer + */ +//! @{ +#define ADC_POTENTIOMETER_CHANNEL 1 +#define ADC_POTENTIOMETER_PIN AVR32_ADC_AD_1_PIN +#define ADC_POTENTIOMETER_FUNCTION AVR32_ADC_AD_1_FUNCTION +//! @} + + +/*! \name ADC Connection of the Temperature Sensor + */ +//! @{ +#define ADC_TEMPERATURE_CHANNEL 0 +#define ADC_TEMPERATURE_PIN AVR32_ADC_AD_0_PIN +#define ADC_TEMPERATURE_FUNCTION AVR32_ADC_AD_0_FUNCTION +//! @} + + +/*! \name ADC Connection of the Light Sensor + */ +//! @{ +#define ADC_LIGHT_CHANNEL 2 +#define ADC_LIGHT_PIN AVR32_ADC_AD_2_PIN +#define ADC_LIGHT_FUNCTION AVR32_ADC_AD_2_FUNCTION +//! @} + + +/*! \name SPI Connections of the DIP204 LCD + */ +//! @{ +#define DIP204_SPI (&AVR32_SPI1) +#define DIP204_SPI_CS 2 +#define DIP204_SPI_SCK_PIN AVR32_SPI1_SCK_0_PIN +#define DIP204_SPI_SCK_FUNCTION AVR32_SPI1_SCK_0_FUNCTION +#define DIP204_SPI_MISO_PIN AVR32_SPI1_MISO_0_PIN +#define DIP204_SPI_MISO_FUNCTION AVR32_SPI1_MISO_0_FUNCTION +#define DIP204_SPI_MOSI_PIN AVR32_SPI1_MOSI_0_PIN +#define DIP204_SPI_MOSI_FUNCTION AVR32_SPI1_MOSI_0_FUNCTION +#define DIP204_SPI_NPCS_PIN AVR32_SPI1_NPCS_2_PIN +#define DIP204_SPI_NPCS_FUNCTION AVR32_SPI1_NPCS_2_FUNCTION +//! @} + +/*! \name GPIO and PWM Connections of the DIP204 LCD Backlight + */ +//! @{ +#define DIP204_BACKLIGHT_PIN AVR32_PIN_PB18 +#define DIP204_PWM_CHANNEL 6 +#define DIP204_PWM_PIN AVR32_PWM_PWM_6_PIN +#define DIP204_PWM_FUNCTION AVR32_PWM_PWM_6_FUNCTION +//! @} + + +/*! \name SPI Connections of the AT45DBX Data Flash Memory + */ +//! @{ +#define AT45DBX_SPI (&AVR32_SPI1) +#define AT45DBX_SPI_SCK_PIN AVR32_SPI1_SCK_0_PIN +#define AT45DBX_SPI_SCK_FUNCTION AVR32_SPI1_SCK_0_FUNCTION +#define AT45DBX_SPI_MISO_PIN AVR32_SPI1_MISO_0_PIN +#define AT45DBX_SPI_MISO_FUNCTION AVR32_SPI1_MISO_0_FUNCTION +#define AT45DBX_SPI_MOSI_PIN AVR32_SPI1_MOSI_0_PIN +#define AT45DBX_SPI_MOSI_FUNCTION AVR32_SPI1_MOSI_0_FUNCTION +#define AT45DBX_SPI_NPCS0_PIN AVR32_SPI1_NPCS_0_PIN +#define AT45DBX_SPI_NPCS0_FUNCTION AVR32_SPI1_NPCS_0_FUNCTION +//! @} + + +/*! \name GPIO and SPI Connections of the SD/MMC Connector + */ +//! @{ +#define SD_MMC_CARD_DETECT_PIN AVR32_PIN_PA02 +#define SD_MMC_WRITE_PROTECT_PIN AVR32_PIN_PA07 +#define SD_MMC_SPI (&AVR32_SPI1) +#define SD_MMC_SPI_CS 1 +#define SD_MMC_SPI_SCK_PIN AVR32_SPI1_SCK_0_PIN +#define SD_MMC_SPI_SCK_FUNCTION AVR32_SPI1_SCK_0_FUNCTION +#define SD_MMC_SPI_MISO_PIN AVR32_SPI1_MISO_0_PIN +#define SD_MMC_SPI_MISO_FUNCTION AVR32_SPI1_MISO_0_FUNCTION +#define SD_MMC_SPI_MOSI_PIN AVR32_SPI1_MOSI_0_PIN +#define SD_MMC_SPI_MOSI_FUNCTION AVR32_SPI1_MOSI_0_FUNCTION +#define SD_MMC_SPI_NPCS_PIN AVR32_SPI1_NPCS_1_PIN +#define SD_MMC_SPI_NPCS_FUNCTION AVR32_SPI1_NPCS_1_FUNCTION +//! @} + + +#endif // _EVK1100_H_ diff --git a/20080212/Demo/AVR32_UC3/BOARDS/EVK1100/led.c b/20080212/Demo/AVR32_UC3/BOARDS/EVK1100/led.c new file mode 100644 index 000000000..9f0952bc9 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/BOARDS/EVK1100/led.c @@ -0,0 +1,305 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief AT32UC3A EVK1100 board LEDs support package. + * + * This file contains definitions and services related to the LED features of + * the EVK1100 board. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 AT32UC3A devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include +#include "preprocessor.h" +#include "compiler.h" +#include "evk1100.h" +#include "led.h" + + +//! Structure describing LED hardware connections. +typedef const struct +{ + struct + { + U32 PORT; //!< LED GPIO port. + U32 PIN_MASK; //!< Bit-mask of LED pin in GPIO port. + } GPIO; //!< LED GPIO descriptor. + struct + { + S32 CHANNEL; //!< LED PWM channel (< 0 if N/A). + S32 FUNCTION; //!< LED pin PWM function (< 0 if N/A). + } PWM; //!< LED PWM descriptor. +} tLED_DESCRIPTOR; + + +//! Hardware descriptors of all LEDs. +static tLED_DESCRIPTOR LED_DESCRIPTOR[LED_COUNT] = +{ +#define INSERT_LED_DESCRIPTOR(LED_NO, unused) \ + { \ + {LED##LED_NO##_GPIO / 32, 1 << (LED##LED_NO##_GPIO % 32)},\ + {LED##LED_NO##_PWM, LED##LED_NO##_PWM_FUNCTION } \ + }, + MREPEAT(LED_COUNT, INSERT_LED_DESCRIPTOR, ~) +#undef INSERT_LED_DESCRIPTOR +}; + + +//! Saved state of all LEDs. +static volatile U32 LED_State = (1 << LED_COUNT) - 1; + + +U32 LED_Read_Display(void) +{ + return LED_State; +} + + +void LED_Display(U32 leds) +{ + tLED_DESCRIPTOR *led_descriptor; + volatile avr32_gpio_port_t *led_gpio_port; + + leds &= (1 << LED_COUNT) - 1; + LED_State = leds; + for (led_descriptor = &LED_DESCRIPTOR[0]; + led_descriptor < LED_DESCRIPTOR + LED_COUNT; + led_descriptor++) + { + led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT]; + if (leds & 1) + { + led_gpio_port->ovrc = led_descriptor->GPIO.PIN_MASK; + } + else + { + led_gpio_port->ovrs = led_descriptor->GPIO.PIN_MASK; + } + led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK; + leds >>= 1; + } +} + + +U32 LED_Read_Display_Mask(U32 mask) +{ + return Rd_bits(LED_State, mask); +} + + +void LED_Display_Mask(U32 mask, U32 leds) +{ + tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1; + volatile avr32_gpio_port_t *led_gpio_port; + U8 led_shift; + + mask &= (1 << LED_COUNT) - 1; + Wr_bits(LED_State, mask, leds); + while (mask) + { + led_shift = 1 + ctz(mask); + led_descriptor += led_shift; + led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT]; + leds >>= led_shift - 1; + if (leds & 1) + { + led_gpio_port->ovrc = led_descriptor->GPIO.PIN_MASK; + } + else + { + led_gpio_port->ovrs = led_descriptor->GPIO.PIN_MASK; + } + led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK; + leds >>= 1; + mask >>= led_shift; + } +} + + +Bool LED_Test(U32 leds) +{ + return Tst_bits(LED_State, leds); +} + + +void LED_Off(U32 leds) +{ + tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1; + volatile avr32_gpio_port_t *led_gpio_port; + U8 led_shift; + + leds &= (1 << LED_COUNT) - 1; + Clr_bits(LED_State, leds); + while (leds) + { + led_shift = 1 + ctz(leds); + led_descriptor += led_shift; + led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT]; + led_gpio_port->ovrs = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK; + leds >>= led_shift; + } +} + + +void LED_On(U32 leds) +{ + tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1; + volatile avr32_gpio_port_t *led_gpio_port; + U8 led_shift; + + leds &= (1 << LED_COUNT) - 1; + Set_bits(LED_State, leds); + while (leds) + { + led_shift = 1 + ctz(leds); + led_descriptor += led_shift; + led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT]; + led_gpio_port->ovrc = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK; + leds >>= led_shift; + } +} + + +void LED_Toggle(U32 leds) +{ + tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1; + volatile avr32_gpio_port_t *led_gpio_port; + U8 led_shift; + + leds &= (1 << LED_COUNT) - 1; + Tgl_bits(LED_State, leds); + while (leds) + { + led_shift = 1 + ctz(leds); + led_descriptor += led_shift; + led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT]; + led_gpio_port->ovrt = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK; + leds >>= led_shift; + } +} + + +U32 LED_Read_Display_Field(U32 field) +{ + return Rd_bitfield(LED_State, field); +} + + +void LED_Display_Field(U32 field, U32 leds) +{ + LED_Display_Mask(field, leds << ctz(field)); +} + + +U8 LED_Get_Intensity(U32 led) +{ + tLED_DESCRIPTOR *led_descriptor; + + // Check that the argument value is valid. + led = ctz(led); + led_descriptor = &LED_DESCRIPTOR[led]; + if (led >= LED_COUNT || led_descriptor->PWM.CHANNEL < 0) return 0; + + // Return the duty cycle value if the LED PWM channel is enabled, else 0. + return (AVR32_PWM.sr & (1 << led_descriptor->PWM.CHANNEL)) ? + AVR32_PWM.channel[led_descriptor->PWM.CHANNEL].cdty : 0; +} + + +void LED_Set_Intensity(U32 leds, U8 intensity) +{ + tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1; + volatile avr32_pwm_channel_t *led_pwm_channel; + volatile avr32_gpio_port_t *led_gpio_port; + U8 led_shift; + + // For each specified LED... + for (leds &= (1 << LED_COUNT) - 1; leds; leds >>= led_shift) + { + // Select the next specified LED and check that it has a PWM channel. + led_shift = 1 + ctz(leds); + led_descriptor += led_shift; + if (led_descriptor->PWM.CHANNEL < 0) continue; + + // Initialize or update the LED PWM channel. + led_pwm_channel = &AVR32_PWM.channel[led_descriptor->PWM.CHANNEL]; + if (!(AVR32_PWM.sr & (1 << led_descriptor->PWM.CHANNEL))) + { + led_pwm_channel->cmr = (AVR32_PWM_CPRE_MCK << AVR32_PWM_CPRE_OFFSET) & + ~(AVR32_PWM_CALG_MASK | + AVR32_PWM_CPOL_MASK | + AVR32_PWM_CPD_MASK); + led_pwm_channel->cprd = 0x000000FF; + led_pwm_channel->cdty = intensity; + AVR32_PWM.ena = 1 << led_descriptor->PWM.CHANNEL; + } + else + { + AVR32_PWM.isr; + while (!(AVR32_PWM.isr & (1 << led_descriptor->PWM.CHANNEL))); + led_pwm_channel->cupd = intensity; + } + + // Switch the LED pin to its PWM function. + led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT]; + if (led_descriptor->PWM.FUNCTION & 0x1) + { + led_gpio_port->pmr0s = led_descriptor->GPIO.PIN_MASK; + } + else + { + led_gpio_port->pmr0c = led_descriptor->GPIO.PIN_MASK; + } + if (led_descriptor->PWM.FUNCTION & 0x2) + { + led_gpio_port->pmr1s = led_descriptor->GPIO.PIN_MASK; + } + else + { + led_gpio_port->pmr1c = led_descriptor->GPIO.PIN_MASK; + } + led_gpio_port->gperc = led_descriptor->GPIO.PIN_MASK; + } +} diff --git a/20080212/Demo/AVR32_UC3/BOARDS/EVK1100/led.h b/20080212/Demo/AVR32_UC3/BOARDS/EVK1100/led.h new file mode 100644 index 000000000..aa26a0af1 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/BOARDS/EVK1100/led.h @@ -0,0 +1,186 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief AT32UC3A EVK1100 board LEDs support package. + * + * This file contains definitions and services related to the LED features of + * the EVK1100 board. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 AT32UC3A devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef _LED_H_ +#define _LED_H_ + +#include "compiler.h" + + +/*! \name Identifiers of LEDs to Use with LED Functions + */ +//! @{ +#define LED0 0x01 +#define LED1 0x02 +#define LED2 0x04 +#define LED3 0x08 +#define LED4 0x10 +#define LED5 0x20 +#define LED6 0x40 +#define LED7 0x80 +//! @} + + +/*! \brief Gets the last state of all LEDs set through the LED API. + * + * \return State of all LEDs (1 bit per LED). + * + * \note The GPIO pin configuration of all LEDs is left unchanged. + */ +extern U32 LED_Read_Display(void); + +/*! \brief Sets the state of all LEDs. + * + * \param leds New state of all LEDs (1 bit per LED). + * + * \note The pins of all LEDs are set to GPIO output mode. + */ +extern void LED_Display(U32 leds); + +/*! \brief Gets the last state of the specified LEDs set through the LED API. + * + * \param mask LEDs of which to get the state (1 bit per LED). + * + * \return State of the specified LEDs (1 bit per LED). + * + * \note The GPIO pin configuration of all LEDs is left unchanged. + */ +extern U32 LED_Read_Display_Mask(U32 mask); + +/*! \brief Sets the state of the specified LEDs. + * + * \param mask LEDs of which to set the state (1 bit per LED). + * + * \param leds New state of the specified LEDs (1 bit per LED). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +extern void LED_Display_Mask(U32 mask, U32 leds); + +/*! \brief Tests the last state of the specified LEDs set through the LED API. + * + * \param leds LEDs of which to test the state (1 bit per LED). + * + * \return \c TRUE if at least one of the specified LEDs has a state on, else + * \c FALSE. + * + * \note The GPIO pin configuration of all LEDs is left unchanged. + */ +extern Bool LED_Test(U32 leds); + +/*! \brief Turns off the specified LEDs. + * + * \param leds LEDs to turn off (1 bit per LED). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +extern void LED_Off(U32 leds); + +/*! \brief Turns on the specified LEDs. + * + * \param leds LEDs to turn on (1 bit per LED). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +extern void LED_On(U32 leds); + +/*! \brief Toggles the specified LEDs. + * + * \param leds LEDs to toggle (1 bit per LED). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +extern void LED_Toggle(U32 leds); + +/*! \brief Gets as a bit-field the last state of the specified LEDs set through + * the LED API. + * + * \param field LEDs of which to get the state (1 bit per LED). + * + * \return State of the specified LEDs (1 bit per LED, beginning with the first + * specified LED). + * + * \note The GPIO pin configuration of all LEDs is left unchanged. + */ +extern U32 LED_Read_Display_Field(U32 field); + +/*! \brief Sets as a bit-field the state of the specified LEDs. + * + * \param field LEDs of which to set the state (1 bit per LED). + * \param leds New state of the specified LEDs (1 bit per LED, beginning with + * the first specified LED). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +extern void LED_Display_Field(U32 field, U32 leds); + +/*! \brief Gets the intensity of the specified LED. + * + * \param led LED of which to get the intensity (1 bit per LED; only the least + * significant set bit is used). + * + * \return Intensity of the specified LED (0x00 to 0xFF). + * + * \warning The PWM channel of the specified LED is supposed to be used only by + * this module. + * + * \note The GPIO pin configuration of all LEDs is left unchanged. + */ +extern U8 LED_Get_Intensity(U32 led); + +/*! \brief Sets the intensity of the specified LEDs. + * + * \param leds LEDs of which to set the intensity (1 bit per LED). + * \param intensity New intensity of the specified LEDs (0x00 to 0xFF). + * + * \warning The PWM channels of the specified LEDs are supposed to be used only + * by this module. + * + * \note The pins of the specified LEDs are set to PWM output mode. + */ +extern void LED_Set_Intensity(U32 leds, U8 intensity); + + +#endif // _LED_H_ diff --git a/20080212/Demo/AVR32_UC3/BOARDS/EVK1101/evk1101.h b/20080212/Demo/AVR32_UC3/BOARDS/EVK1101/evk1101.h new file mode 100644 index 000000000..87291f54f --- /dev/null +++ b/20080212/Demo/AVR32_UC3/BOARDS/EVK1101/evk1101.h @@ -0,0 +1,239 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief AT32UC3B EVK1101 board header file. + * + * This file contains definitions and services related to the features of the + * EVK1101 board. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 AT32UC3B devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef _EVK1101_H_ +#define _EVK1101_H_ + +#include "compiler.h" + +#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling. +# include "led.h" +#endif // __AVR32_ABI_COMPILER__ + + +/*! \name Oscillator Definitions + */ +//! @{ + +// RCOsc has no custom calibration by default. Set the following definition to +// the appropriate value if a custom RCOsc calibration has been applied to your +// part. +//#define FRCOSC 115200 //!< RCOsc frequency: Hz. + +#define FOSC32 32768 //!< Osc32 frequency: Hz. +#define OSC32_STARTUP 3 //!< Osc32 startup time: RCOsc periods. + +#define FOSC0 12000000 //!< Osc0 frequency: Hz. +#define OSC0_STARTUP 3 //!< Osc0 startup time: RCOsc periods. + +// Osc1 crystal is not mounted by default. Set the following definitions to the +// appropriate values if a custom Osc1 crystal is mounted on your board. +//#define FOSC1 12000000 //!< Osc1 frequency: Hz. +//#define OSC1_STARTUP 3 //!< Osc1 startup time: RCOsc periods. + +//! @} + + +/*! \name USB Definitions + */ +//! @{ + +//! Multiplexed pin used for USB_ID: AVR32_USBB_USB_ID_x_x. +//! To be selected according to the AVR32_USBB_USB_ID_x_x_PIN and +//! AVR32_USBB_USB_ID_x_x_FUNCTION definitions from . +#define USB_ID AVR32_USBB_USB_ID_0_0 + +//! Multiplexed pin used for USB_VBOF: AVR32_USBB_USB_VBOF_x_x. +//! To be selected according to the AVR32_USBB_USB_VBOF_x_x_PIN and +//! AVR32_USBB_USB_VBOF_x_x_FUNCTION definitions from . +#define USB_VBOF AVR32_USBB_USB_VBOF_0_0 + +//! Active level of the USB_VBOF output pin. +#define USB_VBOF_ACTIVE_LEVEL LOW + +//! USB overcurrent detection pin. +#define USB_OVERCURRENT_DETECT_PIN AVR32_PIN_PA20 + +//! @} + + +//! Number of LEDs. +#define LED_COUNT 4 + +/*! \name GPIO Connections of LEDs + */ +//! @{ +#define LED0_GPIO AVR32_PIN_PA07 +#define LED1_GPIO AVR32_PIN_PA08 +#define LED2_GPIO AVR32_PIN_PA21 +#define LED3_GPIO AVR32_PIN_PA22 +//! @} + +/*! \name PWM Channels of LEDs + */ +//! @{ +#define LED0_PWM 0 +#define LED1_PWM 1 +#define LED2_PWM 2 +#define LED3_PWM 6 +//! @} + +/*! \name PWM Functions of LEDs + */ +//! @{ +#define LED0_PWM_FUNCTION AVR32_PWM_PWM_0_0_FUNCTION +#define LED1_PWM_FUNCTION AVR32_PWM_PWM_1_0_FUNCTION +#define LED2_PWM_FUNCTION AVR32_PWM_PWM_2_0_FUNCTION +#define LED3_PWM_FUNCTION AVR32_PWM_PWM_6_0_FUNCTION +//! @} + +/*! \name Color Identifiers of LEDs to Use with LED Functions + */ +//! @{ +#define LED_MONO0_GREEN LED0 +#define LED_MONO1_GREEN LED1 +#define LED_MONO2_GREEN LED2 +#define LED_MONO3_GREEN LED3 +//! @} + + +/*! \name GPIO Connections of Push Buttons + */ +//! @{ +#define GPIO_PUSH_BUTTON_0 AVR32_PIN_PB02 +#define GPIO_PUSH_BUTTON_1 AVR32_PIN_PB03 +//! @} + + +/*! \name GPIO Connections of the Joystick + */ +//! @{ +#define GPIO_JOYSTICK_PUSH AVR32_PIN_PA13 +#define GPIO_JOYSTICK_LEFT AVR32_PIN_PB06 +#define GPIO_JOYSTICK_RIGHT AVR32_PIN_PB09 +#define GPIO_JOYSTICK_UP AVR32_PIN_PB07 +#define GPIO_JOYSTICK_DOWN AVR32_PIN_PB08 +//! @} + + +/*! \name ADC Connection of the Temperature Sensor + */ +//! @{ +#define ADC_TEMPERATURE_CHANNEL 7 +#define ADC_TEMPERATURE_PIN AVR32_ADC_AD_7_PIN +#define ADC_TEMPERATURE_FUNCTION AVR32_ADC_AD_7_FUNCTION +//! @} + + +/*! \name ADC Connection of the Light Sensor + */ +//! @{ +#define ADC_LIGHT_CHANNEL 6 +#define ADC_LIGHT_PIN AVR32_ADC_AD_6_PIN +#define ADC_LIGHT_FUNCTION AVR32_ADC_AD_6_FUNCTION +//! @} + + +/*! \name ADC Connections of the Accelerometer + */ +//! @{ +#define ADC_ACC_X_CHANNEL 1 +#define ADC_ACC_X_PIN AVR32_ADC_AD_1_PIN +#define ADC_ACC_X_FUNCTION AVR32_ADC_AD_1_FUNCTION +#define ADC_ACC_Y_CHANNEL 2 +#define ADC_ACC_Y_PIN AVR32_ADC_AD_2_PIN +#define ADC_ACC_Y_FUNCTION AVR32_ADC_AD_2_FUNCTION +#define ADC_ACC_Z_CHANNEL 3 +#define ADC_ACC_Z_PIN AVR32_ADC_AD_3_PIN +#define ADC_ACC_Z_FUNCTION AVR32_ADC_AD_3_FUNCTION +//! @} + + +/*! \name PWM Connections of Audio + */ +//! @{ +#define AUDIO_LOW_PWM_CHANNEL 5 +#define AUDIO_LOW_PWM_PIN AVR32_PWM_PWM_5_0_PIN +#define AUDIO_LOW_PWM_FUNCTION AVR32_PWM_PWM_5_0_FUNCTION +#define AUDIO_HIGH_PWM_CHANNEL 6 +#define AUDIO_HIGH_PWM_PIN AVR32_PWM_PWM_6_1_PIN +#define AUDIO_HIGH_PWM_FUNCTION AVR32_PWM_PWM_6_1_FUNCTION +//! @} + + +/*! \name SPI Connections of the AT45DBX Data Flash Memory + */ +//! @{ +#define AT45DBX_SPI (&AVR32_SPI) +#define AT45DBX_SPI_SCK_PIN AVR32_SPI_SCK_0_0_PIN +#define AT45DBX_SPI_SCK_FUNCTION AVR32_SPI_SCK_0_0_FUNCTION +#define AT45DBX_SPI_MISO_PIN AVR32_SPI_MISO_0_0_PIN +#define AT45DBX_SPI_MISO_FUNCTION AVR32_SPI_MISO_0_0_FUNCTION +#define AT45DBX_SPI_MOSI_PIN AVR32_SPI_MOSI_0_0_PIN +#define AT45DBX_SPI_MOSI_FUNCTION AVR32_SPI_MOSI_0_0_FUNCTION +#define AT45DBX_SPI_NPCS0_PIN AVR32_SPI_NPCS_0_0_PIN +#define AT45DBX_SPI_NPCS0_FUNCTION AVR32_SPI_NPCS_0_0_FUNCTION +//! @} + + +/*! \name GPIO and SPI Connections of the SD/MMC Connector + */ +//! @{ +#define SD_MMC_CARD_DETECT_PIN AVR32_PIN_PB00 +#define SD_MMC_WRITE_PROTECT_PIN AVR32_PIN_PB01 +#define SD_MMC_SPI (&AVR32_SPI) +#define SD_MMC_SPI_CS 1 +#define SD_MMC_SPI_SCK_PIN AVR32_SPI_SCK_0_0_PIN +#define SD_MMC_SPI_SCK_FUNCTION AVR32_SPI_SCK_0_0_FUNCTION +#define SD_MMC_SPI_MISO_PIN AVR32_SPI_MISO_0_0_PIN +#define SD_MMC_SPI_MISO_FUNCTION AVR32_SPI_MISO_0_0_FUNCTION +#define SD_MMC_SPI_MOSI_PIN AVR32_SPI_MOSI_0_0_PIN +#define SD_MMC_SPI_MOSI_FUNCTION AVR32_SPI_MOSI_0_0_FUNCTION +#define SD_MMC_SPI_NPCS_PIN AVR32_SPI_NPCS_1_0_PIN +#define SD_MMC_SPI_NPCS_FUNCTION AVR32_SPI_NPCS_1_0_FUNCTION +//! @} + + +#endif // _EVK1101_H_ diff --git a/20080212/Demo/AVR32_UC3/BOARDS/EVK1101/led.c b/20080212/Demo/AVR32_UC3/BOARDS/EVK1101/led.c new file mode 100644 index 000000000..70705769b --- /dev/null +++ b/20080212/Demo/AVR32_UC3/BOARDS/EVK1101/led.c @@ -0,0 +1,305 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief AT32UC3B EVK1101 board LEDs support package. + * + * This file contains definitions and services related to the LED features of + * the EVK1101 board. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 AT32UC3B devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include +#include "preprocessor.h" +#include "compiler.h" +#include "evk1101.h" +#include "led.h" + + +//! Structure describing LED hardware connections. +typedef const struct +{ + struct + { + U32 PORT; //!< LED GPIO port. + U32 PIN_MASK; //!< Bit-mask of LED pin in GPIO port. + } GPIO; //!< LED GPIO descriptor. + struct + { + S32 CHANNEL; //!< LED PWM channel (< 0 if N/A). + S32 FUNCTION; //!< LED pin PWM function (< 0 if N/A). + } PWM; //!< LED PWM descriptor. +} tLED_DESCRIPTOR; + + +//! Hardware descriptors of all LEDs. +static tLED_DESCRIPTOR LED_DESCRIPTOR[LED_COUNT] = +{ +#define INSERT_LED_DESCRIPTOR(LED_NO, unused) \ + { \ + {LED##LED_NO##_GPIO / 32, 1 << (LED##LED_NO##_GPIO % 32)},\ + {LED##LED_NO##_PWM, LED##LED_NO##_PWM_FUNCTION } \ + }, + MREPEAT(LED_COUNT, INSERT_LED_DESCRIPTOR, ~) +#undef INSERT_LED_DESCRIPTOR +}; + + +//! Saved state of all LEDs. +static volatile U32 LED_State = (1 << LED_COUNT) - 1; + + +U32 LED_Read_Display(void) +{ + return LED_State; +} + + +void LED_Display(U32 leds) +{ + tLED_DESCRIPTOR *led_descriptor; + volatile avr32_gpio_port_t *led_gpio_port; + + leds &= (1 << LED_COUNT) - 1; + LED_State = leds; + for (led_descriptor = &LED_DESCRIPTOR[0]; + led_descriptor < LED_DESCRIPTOR + LED_COUNT; + led_descriptor++) + { + led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT]; + if (leds & 1) + { + led_gpio_port->ovrc = led_descriptor->GPIO.PIN_MASK; + } + else + { + led_gpio_port->ovrs = led_descriptor->GPIO.PIN_MASK; + } + led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK; + leds >>= 1; + } +} + + +U32 LED_Read_Display_Mask(U32 mask) +{ + return Rd_bits(LED_State, mask); +} + + +void LED_Display_Mask(U32 mask, U32 leds) +{ + tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1; + volatile avr32_gpio_port_t *led_gpio_port; + U8 led_shift; + + mask &= (1 << LED_COUNT) - 1; + Wr_bits(LED_State, mask, leds); + while (mask) + { + led_shift = 1 + ctz(mask); + led_descriptor += led_shift; + led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT]; + leds >>= led_shift - 1; + if (leds & 1) + { + led_gpio_port->ovrc = led_descriptor->GPIO.PIN_MASK; + } + else + { + led_gpio_port->ovrs = led_descriptor->GPIO.PIN_MASK; + } + led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK; + leds >>= 1; + mask >>= led_shift; + } +} + + +Bool LED_Test(U32 leds) +{ + return Tst_bits(LED_State, leds); +} + + +void LED_Off(U32 leds) +{ + tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1; + volatile avr32_gpio_port_t *led_gpio_port; + U8 led_shift; + + leds &= (1 << LED_COUNT) - 1; + Clr_bits(LED_State, leds); + while (leds) + { + led_shift = 1 + ctz(leds); + led_descriptor += led_shift; + led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT]; + led_gpio_port->ovrs = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK; + leds >>= led_shift; + } +} + + +void LED_On(U32 leds) +{ + tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1; + volatile avr32_gpio_port_t *led_gpio_port; + U8 led_shift; + + leds &= (1 << LED_COUNT) - 1; + Set_bits(LED_State, leds); + while (leds) + { + led_shift = 1 + ctz(leds); + led_descriptor += led_shift; + led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT]; + led_gpio_port->ovrc = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK; + leds >>= led_shift; + } +} + + +void LED_Toggle(U32 leds) +{ + tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1; + volatile avr32_gpio_port_t *led_gpio_port; + U8 led_shift; + + leds &= (1 << LED_COUNT) - 1; + Tgl_bits(LED_State, leds); + while (leds) + { + led_shift = 1 + ctz(leds); + led_descriptor += led_shift; + led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT]; + led_gpio_port->ovrt = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK; + leds >>= led_shift; + } +} + + +U32 LED_Read_Display_Field(U32 field) +{ + return Rd_bitfield(LED_State, field); +} + + +void LED_Display_Field(U32 field, U32 leds) +{ + LED_Display_Mask(field, leds << ctz(field)); +} + + +U8 LED_Get_Intensity(U32 led) +{ + tLED_DESCRIPTOR *led_descriptor; + + // Check that the argument value is valid. + led = ctz(led); + led_descriptor = &LED_DESCRIPTOR[led]; + if (led >= LED_COUNT || led_descriptor->PWM.CHANNEL < 0) return 0; + + // Return the duty cycle value if the LED PWM channel is enabled, else 0. + return (AVR32_PWM.sr & (1 << led_descriptor->PWM.CHANNEL)) ? + AVR32_PWM.channel[led_descriptor->PWM.CHANNEL].cdty : 0; +} + + +void LED_Set_Intensity(U32 leds, U8 intensity) +{ + tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1; + volatile avr32_pwm_channel_t *led_pwm_channel; + volatile avr32_gpio_port_t *led_gpio_port; + U8 led_shift; + + // For each specified LED... + for (leds &= (1 << LED_COUNT) - 1; leds; leds >>= led_shift) + { + // Select the next specified LED and check that it has a PWM channel. + led_shift = 1 + ctz(leds); + led_descriptor += led_shift; + if (led_descriptor->PWM.CHANNEL < 0) continue; + + // Initialize or update the LED PWM channel. + led_pwm_channel = &AVR32_PWM.channel[led_descriptor->PWM.CHANNEL]; + if (!(AVR32_PWM.sr & (1 << led_descriptor->PWM.CHANNEL))) + { + led_pwm_channel->cmr = (AVR32_PWM_CPRE_MCK << AVR32_PWM_CPRE_OFFSET) & + ~(AVR32_PWM_CALG_MASK | + AVR32_PWM_CPOL_MASK | + AVR32_PWM_CPD_MASK); + led_pwm_channel->cprd = 0x000000FF; + led_pwm_channel->cdty = intensity; + AVR32_PWM.ena = 1 << led_descriptor->PWM.CHANNEL; + } + else + { + AVR32_PWM.isr; + while (!(AVR32_PWM.isr & (1 << led_descriptor->PWM.CHANNEL))); + led_pwm_channel->cupd = intensity; + } + + // Switch the LED pin to its PWM function. + led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT]; + if (led_descriptor->PWM.FUNCTION & 0x1) + { + led_gpio_port->pmr0s = led_descriptor->GPIO.PIN_MASK; + } + else + { + led_gpio_port->pmr0c = led_descriptor->GPIO.PIN_MASK; + } + if (led_descriptor->PWM.FUNCTION & 0x2) + { + led_gpio_port->pmr1s = led_descriptor->GPIO.PIN_MASK; + } + else + { + led_gpio_port->pmr1c = led_descriptor->GPIO.PIN_MASK; + } + led_gpio_port->gperc = led_descriptor->GPIO.PIN_MASK; + } +} diff --git a/20080212/Demo/AVR32_UC3/BOARDS/EVK1101/led.h b/20080212/Demo/AVR32_UC3/BOARDS/EVK1101/led.h new file mode 100644 index 000000000..bf8948712 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/BOARDS/EVK1101/led.h @@ -0,0 +1,182 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief AT32UC3B EVK1101 board LEDs support package. + * + * This file contains definitions and services related to the LED features of + * the EVK1101 board. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 AT32UC3B devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef _LED_H_ +#define _LED_H_ + +#include "compiler.h" + + +/*! \name Identifiers of LEDs to Use with LED Functions + */ +//! @{ +#define LED0 0x01 +#define LED1 0x02 +#define LED2 0x04 +#define LED3 0x08 +//! @} + + +/*! \brief Gets the last state of all LEDs set through the LED API. + * + * \return State of all LEDs (1 bit per LED). + * + * \note The GPIO pin configuration of all LEDs is left unchanged. + */ +extern U32 LED_Read_Display(void); + +/*! \brief Sets the state of all LEDs. + * + * \param leds New state of all LEDs (1 bit per LED). + * + * \note The pins of all LEDs are set to GPIO output mode. + */ +extern void LED_Display(U32 leds); + +/*! \brief Gets the last state of the specified LEDs set through the LED API. + * + * \param mask LEDs of which to get the state (1 bit per LED). + * + * \return State of the specified LEDs (1 bit per LED). + * + * \note The GPIO pin configuration of all LEDs is left unchanged. + */ +extern U32 LED_Read_Display_Mask(U32 mask); + +/*! \brief Sets the state of the specified LEDs. + * + * \param mask LEDs of which to set the state (1 bit per LED). + * + * \param leds New state of the specified LEDs (1 bit per LED). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +extern void LED_Display_Mask(U32 mask, U32 leds); + +/*! \brief Tests the last state of the specified LEDs set through the LED API. + * + * \param leds LEDs of which to test the state (1 bit per LED). + * + * \return \c TRUE if at least one of the specified LEDs has a state on, else + * \c FALSE. + * + * \note The GPIO pin configuration of all LEDs is left unchanged. + */ +extern Bool LED_Test(U32 leds); + +/*! \brief Turns off the specified LEDs. + * + * \param leds LEDs to turn off (1 bit per LED). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +extern void LED_Off(U32 leds); + +/*! \brief Turns on the specified LEDs. + * + * \param leds LEDs to turn on (1 bit per LED). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +extern void LED_On(U32 leds); + +/*! \brief Toggles the specified LEDs. + * + * \param leds LEDs to toggle (1 bit per LED). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +extern void LED_Toggle(U32 leds); + +/*! \brief Gets as a bit-field the last state of the specified LEDs set through + * the LED API. + * + * \param field LEDs of which to get the state (1 bit per LED). + * + * \return State of the specified LEDs (1 bit per LED, beginning with the first + * specified LED). + * + * \note The GPIO pin configuration of all LEDs is left unchanged. + */ +extern U32 LED_Read_Display_Field(U32 field); + +/*! \brief Sets as a bit-field the state of the specified LEDs. + * + * \param field LEDs of which to set the state (1 bit per LED). + * \param leds New state of the specified LEDs (1 bit per LED, beginning with + * the first specified LED). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +extern void LED_Display_Field(U32 field, U32 leds); + +/*! \brief Gets the intensity of the specified LED. + * + * \param led LED of which to get the intensity (1 bit per LED; only the least + * significant set bit is used). + * + * \return Intensity of the specified LED (0x00 to 0xFF). + * + * \warning The PWM channel of the specified LED is supposed to be used only by + * this module. + * + * \note The GPIO pin configuration of all LEDs is left unchanged. + */ +extern U8 LED_Get_Intensity(U32 led); + +/*! \brief Sets the intensity of the specified LEDs. + * + * \param leds LEDs of which to set the intensity (1 bit per LED). + * \param intensity New intensity of the specified LEDs (0x00 to 0xFF). + * + * \warning The PWM channels of the specified LEDs are supposed to be used only + * by this module. + * + * \note The pins of the specified LEDs are set to PWM output mode. + */ +extern void LED_Set_Intensity(U32 leds, U8 intensity); + + +#endif // _LED_H_ diff --git a/20080212/Demo/AVR32_UC3/BOARDS/board.h b/20080212/Demo/AVR32_UC3/BOARDS/board.h new file mode 100644 index 000000000..346165ef6 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/BOARDS/board.h @@ -0,0 +1,82 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Standard board header file. + * + * This file includes the appropriate board header file according to the + * defined board. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include + +/*! \name Base Boards + */ +//! @{ +#define EVK1100 1 //!< AT32UC3A EVK1100 board. +#define EVK1101 2 //!< AT32UC3B EVK1101 board. +//! @} + +/*! \name Extension Boards + */ +//! @{ +#define EXT1102 1 //!< AT32UC3B EXT1102 board. +//! @} + +#if BOARD == EVK1100 +# include "EVK1100/evk1100.h" +#elif BOARD == EVK1101 +# include "EVK1101/evk1101.h" +#else +# error No known AVR32 board defined +#endif + +#if EXT_BOARD == EXT1102 +# include "EXT1102/ext1102.h" +#endif + + +#ifndef FRCOSC +# define FRCOSC AVR32_PM_RCOSC_FREQUENCY //!< Default RCOsc frequency. +#endif + + +#endif // _BOARD_H_ diff --git a/20080212/Demo/AVR32_UC3/DOC/_formulas.tex b/20080212/Demo/AVR32_UC3/DOC/_formulas.tex new file mode 100644 index 000000000..55a7a8474 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/DOC/_formulas.tex @@ -0,0 +1,11 @@ +\documentclass{article} +\usepackage{epsfig} +\pagestyle{empty} +\begin{document} +$ baudrate = \frac{Selected Clock}{16 \times CD} $ +\pagebreak + +$ baudrate = \frac{Selected Clock}{8 \times CD} $ +\pagebreak + +\end{document} diff --git a/20080212/Demo/AVR32_UC3/DOC/doxygen.css b/20080212/Demo/AVR32_UC3/DOC/doxygen.css new file mode 100644 index 000000000..c7db1a8a0 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/DOC/doxygen.css @@ -0,0 +1,358 @@ +BODY,H1,H2,H3,H4,H5,H6,P,CENTER,TD,TH,UL,DL,DIV { + font-family: Geneva, Arial, Helvetica, sans-serif; +} +BODY,TD { + font-size: 90%; +} +H1 { + text-align: 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\file ********************************************************************* + * + * \brief GPIO driver for AVR32 UC3. + * + * This file defines a useful set of functions for the GPIO. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with a GPIO module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + *****************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include "gpio.h" + + +//! GPIO module instance. +#define GPIO AVR32_GPIO + + +int gpio_enable_module(const gpio_map_t gpiomap, unsigned int size) +{ + int status = GPIO_SUCCESS; + unsigned int i; + + for (i = 0; i < size; i++) + { + status |= gpio_enable_module_pin(gpiomap->pin, gpiomap->function); + gpiomap++; + } + + return status; +} + + +int gpio_enable_module_pin(unsigned int pin, unsigned int function) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + + // Enable the correct function. + switch (function) + { + case 0: // A function. + gpio_port->pmr0c = 1 << (pin & 0x1F); + gpio_port->pmr1c = 1 << (pin & 0x1F); + break; + + case 1: // B function. + gpio_port->pmr0s = 1 << (pin & 0x1F); + gpio_port->pmr1c = 1 << (pin & 0x1F); + break; + + case 2: // C function. + gpio_port->pmr0c = 1 << (pin & 0x1F); + gpio_port->pmr1s = 1 << (pin & 0x1F); + break; + + default: + return GPIO_INVALID_ARGUMENT; + } + + // Disable GPIO control. + gpio_port->gperc = 1 << (pin & 0x1F); + + return GPIO_SUCCESS; +} + + +void gpio_enable_gpio(const gpio_map_t gpiomap, unsigned int size) +{ + unsigned int i; + + for (i = 0; i < size; i++) + { + gpio_enable_gpio_pin(gpiomap->pin); + gpiomap++; + } +} + + +void gpio_enable_gpio_pin(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + gpio_port->oderc = 1 << (pin & 0x1F); + gpio_port->gpers = 1 << (pin & 0x1F); +} + + +void gpio_enable_pin_open_drain(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + gpio_port->odmers = 1 << (pin & 0x1F); +} + + +void gpio_disable_pin_open_drain(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + gpio_port->odmerc = 1 << (pin & 0x1F); +} + + +void gpio_enable_pin_pull_up(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + gpio_port->puers = 1 << (pin & 0x1F); +} + + +void gpio_disable_pin_pull_up(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + gpio_port->puerc = 1 << (pin & 0x1F); +} + + +int gpio_get_pin_value(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + return (gpio_port->pvr >> (pin & 0x1F)) & 1; +} + + +int gpio_get_gpio_pin_output_value(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + return (gpio_port->ovr >> (pin & 0x1F)) & 1; +} + + +void gpio_set_gpio_pin(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + + gpio_port->ovrs = 1 << (pin & 0x1F); // Value to be driven on the I/O line: 1. + gpio_port->oders = 1 << (pin & 0x1F); // The GPIO output driver is enabled for that pin. + gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin. +} + + +void gpio_clr_gpio_pin(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + + gpio_port->ovrc = 1 << (pin & 0x1F); // Value to be driven on the I/O line: 0. + gpio_port->oders = 1 << (pin & 0x1F); // The GPIO output driver is enabled for that pin. + gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin. +} + + +void gpio_tgl_gpio_pin(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + + gpio_port->ovrt = 1 << (pin & 0x1F); // Toggle the I/O line. + gpio_port->oders = 1 << (pin & 0x1F); // The GPIO output driver is enabled for that pin. + gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin. +} + + +void gpio_enable_pin_glitch_filter(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + gpio_port->gfers = 1 << (pin & 0x1F); +} + + +void gpio_disable_pin_glitch_filter(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + gpio_port->gferc = 1 << (pin & 0x1F); +} + + +int gpio_enable_pin_interrupt(unsigned int pin, unsigned int mode) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + + // Enable the glitch filter. + gpio_port->gfers = 1 << (pin & 0x1F); + + // Configure the edge detector. + switch (mode) + { + case GPIO_PIN_CHANGE: + gpio_port->imr0c = 1 << (pin & 0x1F); + gpio_port->imr1c = 1 << (pin & 0x1F); + break; + + case GPIO_RISING_EDGE: + gpio_port->imr0s = 1 << (pin & 0x1F); + gpio_port->imr1c = 1 << (pin & 0x1F); + break; + + case GPIO_FALLING_EDGE: + gpio_port->imr0c = 1 << (pin & 0x1F); + gpio_port->imr1s = 1 << (pin & 0x1F); + break; + + default: + return GPIO_INVALID_ARGUMENT; + } + + // Enable interrupt. + gpio_port->iers = 1 << (pin & 0x1F); + + return GPIO_SUCCESS; +} + + +void gpio_disable_pin_interrupt(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + gpio_port->ierc = 1 << (pin & 0x1F); +} + + +int gpio_get_pin_interrupt_flag(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + return (gpio_port->ifr >> (pin & 0x1F)) & 1; +} + + +void gpio_clear_pin_interrupt_flag(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + gpio_port->ifrc = 1 << (pin & 0x1F); +} diff --git a/20080212/Demo/AVR32_UC3/DRIVERS/GPIO/gpio.h b/20080212/Demo/AVR32_UC3/DRIVERS/GPIO/gpio.h new file mode 100644 index 000000000..3e2c6ff07 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/DRIVERS/GPIO/gpio.h @@ -0,0 +1,230 @@ +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief GPIO header for AVR32 UC3. + * + * This file contains basic GPIO driver functions. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with a GPIO module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + *****************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef _GPIO_H_ +#define _GPIO_H_ + +#include + + +/*! \name Return Values of the GPIO API + */ +//! @{ +#define GPIO_SUCCESS 0 //!< Function successfully completed. +#define GPIO_INVALID_ARGUMENT 1 //!< Input parameters are out of range. +//! @} + + +/*! \name Interrupt Trigger Modes + */ +//! @{ +#define GPIO_PIN_CHANGE 0 //!< Interrupt triggered upon pin change. +#define GPIO_RISING_EDGE 1 //!< Interrupt triggered upon rising edge. +#define GPIO_FALLING_EDGE 2 //!< Interrupt triggered upon falling edge. +//! @} + + +//! A type definition of pins and modules connectivity. +typedef struct +{ + unsigned char pin; //!< Module pin. + unsigned char function; //!< Module function. +} gpio_map_t[]; + + +/*! \brief Enables specific module modes for a set of pins. + * + * \param gpiomap The pin map. + * \param size The number of pins in \a gpiomap. + * + * \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT. + */ +extern int gpio_enable_module(const gpio_map_t gpiomap, unsigned int size); + +/*! \brief Enables a specific module mode for a pin. + * + * \param pin The pin number.\n + * Refer to the product header file `uc3x.h' (where x is the part + * number; e.g. x = a0512) for module pins. E.g., to enable a PWM + * channel output, the pin number can be AVR32_PWM_PWM_3_PIN for PWM + * channel 3. + * \param function The pin function.\n + * Refer to the product header file `uc3x.h' (where x is the + * part number; e.g. x = a0512) for module pin functions. E.g., + * to enable a PWM channel output, the pin function can be + * AVR32_PWM_PWM_3_FUNCTION for PWM channel 3. + * + * \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT. + */ +extern int gpio_enable_module_pin(unsigned int pin, unsigned int function); + +/*! \brief Enables the GPIO mode of a set of pins. + * + * \param gpiomap The pin map. + * \param size The number of pins in \a gpiomap. + */ +extern void gpio_enable_gpio(const gpio_map_t gpiomap, unsigned int size); + +/*! \brief Enables the GPIO mode of a pin. + * + * \param pin The pin number.\n + * Refer to the product header file `uc3x.h' (where x is the part + * number; e.g. x = a0512) for pin definitions. E.g., to enable the + * GPIO mode of PX21, AVR32_PIN_PX21 can be used. Module pins such as + * AVR32_PWM_PWM_3_PIN for PWM channel 3 can also be used to release + * module pins for GPIO. + */ +extern void gpio_enable_gpio_pin(unsigned int pin); + +/*! \brief Enables the open-drain mode of a pin. + * + * \param pin The pin number. + */ +extern void gpio_enable_pin_open_drain(unsigned int pin); + +/*! \brief Disables the open-drain mode of a pin. + * + * \param pin The pin number. + */ +extern void gpio_disable_pin_open_drain(unsigned int pin); + +/*! \brief Enables the pull-up resistor of a pin. + * + * \param pin The pin number. + */ +extern void gpio_enable_pin_pull_up(unsigned int pin); + +/*! \brief Disables the pull-up resistor of a pin. + * + * \param pin The pin number. + */ +extern void gpio_disable_pin_pull_up(unsigned int pin); + +/*! \brief Returns the value of a pin. + * + * \param pin The pin number. + * + * \return The pin value. + */ +extern int gpio_get_pin_value(unsigned int pin); + +/*! \brief Returns the output value set for a GPIO pin. + * + * \param pin The pin number. + * + * \return The pin output value. + */ +extern int gpio_get_gpio_pin_output_value(unsigned int pin); + +/*! \brief Drives a GPIO pin to 1. + * + * \param pin The pin number. + */ +extern void gpio_set_gpio_pin(unsigned int pin); + +/*! \brief Drives a GPIO pin to 0. + * + * \param pin The pin number. + */ +extern void gpio_clr_gpio_pin(unsigned int pin); + +/*! \brief Toggles a GPIO pin. + * + * \param pin The pin number. + */ +extern void gpio_tgl_gpio_pin(unsigned int pin); + +/*! \brief Enables the glitch filter of a pin. + * + * When the glitch filter is enabled, a glitch with duration of less than 1 + * clock cycle is automatically rejected, while a pulse with duration of 2 clock + * cycles or more is accepted. For pulse durations between 1 clock cycle and 2 + * clock cycles, the pulse may or may not be taken into account, depending on + * the precise timing of its occurrence. Thus for a pulse to be guaranteed + * visible it must exceed 2 clock cycles, whereas for a glitch to be reliably + * filtered out, its duration must not exceed 1 clock cycle. The filter + * introduces 2 clock cycles latency. + * + * \param pin The pin number. + */ +extern void gpio_enable_pin_glitch_filter(unsigned int pin); + +/*! \brief Disables the glitch filter of a pin. + * + * \param pin The pin number. + */ +extern void gpio_disable_pin_glitch_filter(unsigned int pin); + +/*! \brief Enables the interrupt of a pin with the specified settings. + * + * \param pin The pin number. + * \param mode The trigger mode (\ref GPIO_PIN_CHANGE, \ref GPIO_RISING_EDGE or + * \ref GPIO_FALLING_EDGE). + * + * \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT. + */ +extern int gpio_enable_pin_interrupt(unsigned int pin, unsigned int mode); + +/*! \brief Disables the interrupt of a pin. + * + * \param pin The pin number. + */ +extern void gpio_disable_pin_interrupt(unsigned int pin); + +/*! \brief Gets the interrupt flag of a pin. + * + * \param pin The pin number. + * + * \return The pin interrupt flag. + */ +extern int gpio_get_pin_interrupt_flag(unsigned int pin); + +/*! \brief Clears the interrupt flag of a pin. + * + * \param pin The pin number. + */ +extern void gpio_clear_pin_interrupt_flag(unsigned int pin); + + +#endif // _GPIO_H_ diff --git a/20080212/Demo/AVR32_UC3/DRIVERS/INTC/intc.c b/20080212/Demo/AVR32_UC3/DRIVERS/INTC/intc.c new file mode 100644 index 000000000..8bd9b880e --- /dev/null +++ b/20080212/Demo/AVR32_UC3/DRIVERS/INTC/intc.c @@ -0,0 +1,200 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief INTC driver for AVR32 UC3. + * + * AVR32 Interrupt Controller driver module. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with an INTC module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include +#include "compiler.h" +#include "preprocessor.h" +#include "intc.h" + + +//! Values to store in the interrupt priority registers for the various interrupt priority levels. +extern const unsigned int ipr_val[AVR32_INTC_NUM_INT_LEVELS]; + +//! Creates a table of interrupt line handlers per interrupt group in order to optimize RAM space. +//! Each line handler table contains a set of pointers to interrupt handlers. +#if __GNUC__ +#define DECL_INT_LINE_HANDLER_TABLE(GRP, unused) \ +static volatile __int_handler _int_line_handler_table_##GRP[Max(AVR32_INTC_NUM_IRQS_PER_GRP##GRP, 1)]; +#elif __ICCAVR32__ +#define DECL_INT_LINE_HANDLER_TABLE(GRP, unused) \ +static volatile __no_init __int_handler _int_line_handler_table_##GRP[Max(AVR32_INTC_NUM_IRQS_PER_GRP##GRP, 1)]; +#endif +MREPEAT(AVR32_INTC_NUM_INT_GRPS, DECL_INT_LINE_HANDLER_TABLE, ~); +#undef DECL_INT_LINE_HANDLER_TABLE + +//! Table containing for each interrupt group the number of interrupt request +//! lines and a pointer to the table of interrupt line handlers. +static const struct +{ + unsigned int num_irqs; + volatile __int_handler *_int_line_handler_table; +} _int_handler_table[AVR32_INTC_NUM_INT_GRPS] = +{ +#define INSERT_INT_LINE_HANDLER_TABLE(GRP, unused) \ + {AVR32_INTC_NUM_IRQS_PER_GRP##GRP, _int_line_handler_table_##GRP}, + MREPEAT(AVR32_INTC_NUM_INT_GRPS, INSERT_INT_LINE_HANDLER_TABLE, ~) +#undef INSERT_INT_LINE_HANDLER_TABLE +}; + + +/*! \brief Default interrupt handler. + * + * \note Taken and adapted from Newlib. + */ +#if __GNUC__ +__attribute__((__interrupt__)) +#elif __ICCAVR32__ +__interrupt +#endif +static void _unhandled_interrupt(void) +{ + // Catch unregistered interrupts. + while (TRUE); +} + + +/*! \brief Gets the interrupt handler of the current event at the \a int_lev + * interrupt priority level (called from exception.S). + * + * \param int_lev Interrupt priority level to handle. + * + * \return Interrupt handler to execute. + * + * \note Taken and adapted from Newlib. + */ +__int_handler _get_interrupt_handler(unsigned int int_lev) +{ + // ICR3 is mapped first, ICR0 last. + // Code in exception.S puts int_lev in R12 which is used by AVR32-GCC to pass + // a single argument to a function. + unsigned int int_grp = (&AVR32_INTC.icr3)[INT3 - int_lev]; + unsigned int int_req = AVR32_INTC.irr[int_grp]; + + // As an interrupt may disappear while it is being fetched by the CPU + // (spurious interrupt caused by a delayed response from an MCU peripheral to + // an interrupt flag clear or interrupt disable instruction), check if there + // are remaining interrupt lines to process. + // If a spurious interrupt occurs, the status register (SR) contains an + // execution mode and interrupt level masks corresponding to a level 0 + // interrupt, whatever the interrupt priority level causing the spurious + // event. This behavior has been chosen because a spurious interrupt has not + // to be a priority one and because it may not cause any trouble to other + // interrupts. + // However, these spurious interrupts place the hardware in an unstable state + // and could give problems in other/future versions of the CPU, so the + // software has to be written so that they never occur. The only safe way of + // achieving this is to always clear or disable peripheral interrupts with the + // following sequence: + // 1: Mask the interrupt in the CPU by setting GM (or IxM) in SR. + // 2: Perform the bus access to the peripheral register that clears or + // disables the interrupt. + // 3: Wait until the interrupt has actually been cleared or disabled by the + // peripheral. This is usually performed by reading from a register in the + // same peripheral (it DOES NOT have to be the same register that was + // accessed in step 2, but it MUST be in the same peripheral), what takes + // bus system latencies into account, but peripheral internal latencies + // (generally 0 cycle) also have to be considered. + // 4: Unmask the interrupt in the CPU by clearing GM (or IxM) in SR. + // Note that steps 1 and 4 are useless inside interrupt handlers as the + // corresponding interrupt level is automatically masked by IxM (unless IxM is + // explicitly cleared by the software). + // + // Get the right IRQ handler. + // + // If several interrupt lines are active in the group, the interrupt line with + // the highest number is selected. This is to be coherent with the + // prioritization of interrupt groups performed by the hardware interrupt + // controller. + // + // If no handler has been registered for the pending interrupt, + // _unhandled_interrupt will be selected thanks to the initialization of + // _int_line_handler_table_x by INTC_init_interrupts. + // + // exception.S will provide the interrupt handler with a clean interrupt stack + // frame, with nothing more pushed onto the stack. The interrupt handler must + // manage the `rete' instruction, what can be done thanks to pure assembly, + // inline assembly or the `__attribute__((__interrupt__))' C function + // attribute. + return (int_req) ? _int_handler_table[int_grp]._int_line_handler_table[32 - clz(int_req) - 1] : NULL; +} + + +void INTC_init_interrupts(void) +{ + unsigned int int_grp, int_req; + + // For all interrupt groups, + for (int_grp = 0; int_grp < AVR32_INTC_NUM_INT_GRPS; int_grp++) + { + // For all interrupt request lines of each group, + for (int_req = 0; int_req < _int_handler_table[int_grp].num_irqs; int_req++) + { + // Assign _unhandled_interrupt as default interrupt handler. + _int_handler_table[int_grp]._int_line_handler_table[int_req] = &_unhandled_interrupt; + } + + // Set the interrupt group priority register to its default value. + // By default, all interrupt groups are linked to the interrupt priority + // level 0 and to the interrupt vector _int0. + AVR32_INTC.ipr[int_grp] = ipr_val[INT0]; + } +} + + +void INTC_register_interrupt(__int_handler handler, unsigned int irq, unsigned int int_lev) +{ + // Determine the group of the IRQ. + unsigned int int_grp = irq / AVR32_INTC_MAX_NUM_IRQS_PER_GRP; + + // Store in _int_line_handler_table_x the pointer to the interrupt handler, so + // that _get_interrupt_handler can retrieve it when the interrupt is vectored. + _int_handler_table[int_grp]._int_line_handler_table[irq % AVR32_INTC_MAX_NUM_IRQS_PER_GRP] = handler; + + // Program the corresponding IPRX register to set the interrupt priority level + // and the interrupt vector offset that will be fetched by the core interrupt + // system. + // NOTE: The _intx functions are intermediate assembly functions between the + // core interrupt system and the user interrupt handler. + AVR32_INTC.ipr[int_grp] = ipr_val[int_lev & (AVR32_INTC_IPR0_INTLEV_MASK >> AVR32_INTC_IPR0_INTLEV_OFFSET)]; +} diff --git a/20080212/Demo/AVR32_UC3/DRIVERS/INTC/intc.h b/20080212/Demo/AVR32_UC3/DRIVERS/INTC/intc.h new file mode 100644 index 000000000..93ecef436 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/DRIVERS/INTC/intc.h @@ -0,0 +1,104 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief INTC driver for AVR32 UC3. + * + * AVR32 Interrupt Controller driver module. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with an INTC module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef _INTC_H_ +#define _INTC_H_ + +#include "compiler.h" + + +//! Maximal number of interrupt request lines per group. +#define AVR32_INTC_MAX_NUM_IRQS_PER_GRP 32 + +//! Number of interrupt priority levels. +#define AVR32_INTC_NUM_INT_LEVELS (1 << AVR32_INTC_IPR0_INTLEV_SIZE) + +/*! \name Interrupt Priority Levels + */ +//! @{ +#define INT0 0 //!< Lowest interrupt priority level. +#define INT1 1 +#define INT2 2 +#define INT3 3 //!< Highest interrupt priority level. +//! @} + + +#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling. + +//! Pointer to interrupt handler. +#if __GNUC__ +typedef void (*__int_handler)(void); +#elif __ICCAVR32__ +typedef void (__interrupt *__int_handler)(void); +#endif + + +/*! \brief Initializes the hardware interrupt controller driver. + * + * \note Taken and adapted from Newlib. + */ +extern void INTC_init_interrupts(void); + +/*! \brief Registers an interrupt handler. + * + * \param handler Interrupt handler to register. + * \param irq IRQ of the interrupt handler to register. + * \param int_lev Interrupt priority level to assign to the group of this IRQ. + * + * \warning The interrupt handler must manage the `rete' instruction, what can + * be done thanks to pure assembly, inline assembly or the + * `__attribute__((__interrupt__))' C function attribute. + * + * \warning If several interrupt handlers of a same group are registered with + * different priority levels, only the latest priority level set will + * be effective. + * + * \note Taken and adapted from Newlib. + */ +extern void INTC_register_interrupt(__int_handler handler, unsigned int irq, unsigned int int_lev); + +#endif // __AVR32_ABI_COMPILER__ + + +#endif // _INTC_H_ diff --git a/20080212/Demo/AVR32_UC3/DRIVERS/PM/pm.c b/20080212/Demo/AVR32_UC3/DRIVERS/PM/pm.c new file mode 100644 index 000000000..e2f08d923 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/DRIVERS/PM/pm.c @@ -0,0 +1,510 @@ +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Power Manager driver. + * + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + *****************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include "pm.h" + + +/*! \name PM Writable Bit-Field Registers + */ +//! @{ + +typedef union +{ + unsigned long mcctrl; + avr32_pm_mcctrl_t MCCTRL; +} u_avr32_pm_mcctrl_t; + +typedef union +{ + unsigned long cksel; + avr32_pm_cksel_t CKSEL; +} u_avr32_pm_cksel_t; + +typedef union +{ + unsigned long pll; + avr32_pm_pll_t PLL; +} u_avr32_pm_pll_t; + +typedef union +{ + unsigned long oscctrl0; + avr32_pm_oscctrl0_t OSCCTRL0; +} u_avr32_pm_oscctrl0_t; + +typedef union +{ + unsigned long oscctrl1; + avr32_pm_oscctrl1_t OSCCTRL1; +} u_avr32_pm_oscctrl1_t; + +typedef union +{ + unsigned long oscctrl32; + avr32_pm_oscctrl32_t OSCCTRL32; +} u_avr32_pm_oscctrl32_t; + +typedef union +{ + unsigned long ier; + avr32_pm_ier_t IER; +} u_avr32_pm_ier_t; + +typedef union +{ + unsigned long idr; + avr32_pm_idr_t IDR; +} u_avr32_pm_idr_t; + +typedef union +{ + unsigned long icr; + avr32_pm_icr_t ICR; +} u_avr32_pm_icr_t; + +typedef union +{ + unsigned long gcctrl; + avr32_pm_gcctrl_t GCCTRL; +} u_avr32_pm_gcctrl_t; + +typedef union +{ + unsigned long rccr; + avr32_pm_rccr_t RCCR; +} u_avr32_pm_rccr_t; + +typedef union +{ + unsigned long bgcr; + avr32_pm_bgcr_t BGCR; +} u_avr32_pm_bgcr_t; + +typedef union +{ + unsigned long vregcr; + avr32_pm_vregcr_t VREGCR; +} u_avr32_pm_vregcr_t; + +typedef union +{ + unsigned long bod; + avr32_pm_bod_t BOD; +} u_avr32_pm_bod_t; + +//! @} + + +/*! \brief Sets the mode of the oscillator 0. + * + * \param pm Base address of the Power Manager (i.e. &AVR32_PM). + * \param mode Oscillator 0 mode (i.e. AVR32_PM_OSCCTRL0_MODE_x). + */ +static void pm_set_osc0_mode(volatile avr32_pm_t *pm, unsigned int mode) +{ + // Read + u_avr32_pm_oscctrl0_t u_avr32_pm_oscctrl0 = {pm->oscctrl0}; + // Modify + u_avr32_pm_oscctrl0.OSCCTRL0.mode = mode; + // Write + pm->oscctrl0 = u_avr32_pm_oscctrl0.oscctrl0; +} + + +void pm_enable_osc0_ext_clock(volatile avr32_pm_t *pm) +{ + pm_set_osc0_mode(pm, AVR32_PM_OSCCTRL0_MODE_EXT_CLOCK); +} + + +void pm_enable_osc0_crystal(volatile avr32_pm_t *pm, unsigned int fosc0) +{ + pm_set_osc0_mode(pm, (fosc0 < 8000000) ? AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G2 : + AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G3); +} + + +void pm_enable_clk0(volatile avr32_pm_t *pm, unsigned int startup) +{ + pm_enable_clk0_no_wait(pm, startup); + pm_wait_for_clk0_ready(pm); +} + + +void pm_disable_clk0(volatile avr32_pm_t *pm) +{ + pm->mcctrl &= ~AVR32_PM_MCCTRL_OSC0EN_MASK; +} + + +void pm_enable_clk0_no_wait(volatile avr32_pm_t *pm, unsigned int startup) +{ + // Read register + u_avr32_pm_oscctrl0_t u_avr32_pm_oscctrl0 = {pm->oscctrl0}; + // Modify + u_avr32_pm_oscctrl0.OSCCTRL0.startup = startup; + // Write back + pm->oscctrl0 = u_avr32_pm_oscctrl0.oscctrl0; + + pm->mcctrl |= AVR32_PM_MCCTRL_OSC0EN_MASK; +} + + +void pm_wait_for_clk0_ready(volatile avr32_pm_t *pm) +{ + while (!(pm->poscsr & AVR32_PM_POSCSR_OSC0RDY_MASK)); +} + + +/*! \brief Sets the mode of the oscillator 1. + * + * \param pm Base address of the Power Manager (i.e. &AVR32_PM). + * \param mode Oscillator 1 mode (i.e. AVR32_PM_OSCCTRL1_MODE_x). + */ +static void pm_set_osc1_mode(volatile avr32_pm_t *pm, unsigned int mode) +{ + // Read + u_avr32_pm_oscctrl1_t u_avr32_pm_oscctrl1 = {pm->oscctrl1}; + // Modify + u_avr32_pm_oscctrl1.OSCCTRL1.mode = mode; + // Write + pm->oscctrl1 = u_avr32_pm_oscctrl1.oscctrl1; +} + + +void pm_enable_osc1_ext_clock(volatile avr32_pm_t *pm) +{ + pm_set_osc1_mode(pm, AVR32_PM_OSCCTRL1_MODE_EXT_CLOCK); +} + + +void pm_enable_osc1_crystal(volatile avr32_pm_t *pm, unsigned int fosc1) +{ + pm_set_osc1_mode(pm, (fosc1 < 8000000) ? AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G2 : + AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G3); +} + + +void pm_enable_clk1(volatile avr32_pm_t *pm, unsigned int startup) +{ + pm_enable_clk1_no_wait(pm, startup); + pm_wait_for_clk1_ready(pm); +} + + +void pm_disable_clk1(volatile avr32_pm_t *pm) +{ + pm->mcctrl &= ~AVR32_PM_MCCTRL_OSC1EN_MASK; +} + + +void pm_enable_clk1_no_wait(volatile avr32_pm_t *pm, unsigned int startup) +{ + // Read register + u_avr32_pm_oscctrl1_t u_avr32_pm_oscctrl1 = {pm->oscctrl1}; + // Modify + u_avr32_pm_oscctrl1.OSCCTRL1.startup = startup; + // Write back + pm->oscctrl1 = u_avr32_pm_oscctrl1.oscctrl1; + + pm->mcctrl |= AVR32_PM_MCCTRL_OSC1EN_MASK; +} + + +void pm_wait_for_clk1_ready(volatile avr32_pm_t *pm) +{ + while (!(pm->poscsr & AVR32_PM_POSCSR_OSC1RDY_MASK)); +} + + +/*! \brief Sets the mode of the 32-kHz oscillator. + * + * \param pm Base address of the Power Manager (i.e. &AVR32_PM). + * \param mode 32-kHz oscillator mode (i.e. AVR32_PM_OSCCTRL32_MODE_x). + */ +static void pm_set_osc32_mode(volatile avr32_pm_t *pm, unsigned int mode) +{ + // Read + u_avr32_pm_oscctrl32_t u_avr32_pm_oscctrl32 = {pm->oscctrl32}; + // Modify + u_avr32_pm_oscctrl32.OSCCTRL32.mode = mode; + // Write + pm->oscctrl32 = u_avr32_pm_oscctrl32.oscctrl32; +} + + +void pm_enable_osc32_ext_clock(volatile avr32_pm_t *pm) +{ + pm_set_osc32_mode(pm, AVR32_PM_OSCCTRL32_MODE_EXT_CLOCK); +} + + +void pm_enable_osc32_crystal(volatile avr32_pm_t *pm) +{ + pm_set_osc32_mode(pm, AVR32_PM_OSCCTRL32_MODE_CRYSTAL); +} + + +void pm_enable_clk32(volatile avr32_pm_t *pm, unsigned int startup) +{ + pm_enable_clk32_no_wait(pm, startup); + pm_wait_for_clk32_ready(pm); +} + + +void pm_disable_clk32(volatile avr32_pm_t *pm) +{ + pm->oscctrl32 &= ~AVR32_PM_OSCCTRL32_OSC32EN_MASK; +} + + +void pm_enable_clk32_no_wait(volatile avr32_pm_t *pm, unsigned int startup) +{ + // Read register + u_avr32_pm_oscctrl32_t u_avr32_pm_oscctrl32 = {pm->oscctrl32}; + // Modify + u_avr32_pm_oscctrl32.OSCCTRL32.osc32en = 1; + u_avr32_pm_oscctrl32.OSCCTRL32.startup = startup; + // Write back + pm->oscctrl32 = u_avr32_pm_oscctrl32.oscctrl32; +} + + +void pm_wait_for_clk32_ready(volatile avr32_pm_t *pm) +{ + while (!(pm->poscsr & AVR32_PM_POSCSR_OSC32RDY_MASK)); +} + + +void pm_cksel(volatile avr32_pm_t *pm, + unsigned int pbadiv, + unsigned int pbasel, + unsigned int pbbdiv, + unsigned int pbbsel, + unsigned int hsbdiv, + unsigned int hsbsel) +{ + u_avr32_pm_cksel_t u_avr32_pm_cksel = {0}; + + u_avr32_pm_cksel.CKSEL.cpusel = hsbsel; + u_avr32_pm_cksel.CKSEL.cpudiv = hsbdiv; + u_avr32_pm_cksel.CKSEL.hsbsel = hsbsel; + u_avr32_pm_cksel.CKSEL.hsbdiv = hsbdiv; + u_avr32_pm_cksel.CKSEL.pbasel = pbasel; + u_avr32_pm_cksel.CKSEL.pbadiv = pbadiv; + u_avr32_pm_cksel.CKSEL.pbbsel = pbbsel; + u_avr32_pm_cksel.CKSEL.pbbdiv = pbbdiv; + + pm->cksel = u_avr32_pm_cksel.cksel; + + // Wait for ckrdy bit and then clear it + while (!(pm->poscsr & AVR32_PM_POSCSR_CKRDY_MASK)); +} + + +void pm_gc_setup(volatile avr32_pm_t *pm, + unsigned int gc, + unsigned int osc_or_pll, // Use Osc (=0) or PLL (=1) + unsigned int pll_osc, // Sel Osc0/PLL0 or Osc1/PLL1 + unsigned int diven, + unsigned int div) +{ + u_avr32_pm_gcctrl_t u_avr32_pm_gcctrl = {0}; + + u_avr32_pm_gcctrl.GCCTRL.oscsel = pll_osc; + u_avr32_pm_gcctrl.GCCTRL.pllsel = osc_or_pll; + u_avr32_pm_gcctrl.GCCTRL.diven = diven; + u_avr32_pm_gcctrl.GCCTRL.div = div; + + pm->gcctrl[gc] = u_avr32_pm_gcctrl.gcctrl; +} + + +void pm_gc_enable(volatile avr32_pm_t *pm, + unsigned int gc) +{ + pm->gcctrl[gc] |= AVR32_PM_GCCTRL_CEN_MASK; +} + + +void pm_gc_disable(volatile avr32_pm_t *pm, + unsigned int gc) +{ + pm->gcctrl[gc] &= ~AVR32_PM_GCCTRL_CEN_MASK; +} + + +void pm_pll_setup(volatile avr32_pm_t *pm, + unsigned int pll, + unsigned int mul, + unsigned int div, + unsigned int osc, + unsigned int lockcount) +{ + u_avr32_pm_pll_t u_avr32_pm_pll = {0}; + + u_avr32_pm_pll.PLL.pllosc = osc; + u_avr32_pm_pll.PLL.plldiv = div; + u_avr32_pm_pll.PLL.pllmul = mul; + u_avr32_pm_pll.PLL.pllcount = lockcount; + + pm->pll[pll] = u_avr32_pm_pll.pll; +} + + +void pm_pll_set_option(volatile avr32_pm_t *pm, + unsigned int pll, + unsigned int pll_freq, + unsigned int pll_div2, + unsigned int pll_wbwdisable) +{ + u_avr32_pm_pll_t u_avr32_pm_pll = {pm->pll[pll]}; + u_avr32_pm_pll.PLL.pllopt = pll_freq | (pll_div2 << 1) | (pll_wbwdisable << 2); + pm->pll[pll] = u_avr32_pm_pll.pll; +} + + +unsigned int pm_pll_get_option(volatile avr32_pm_t *pm, + unsigned int pll) +{ + return (pm->pll[pll] & AVR32_PM_PLLOPT_MASK) >> AVR32_PM_PLLOPT_OFFSET; +} + + +void pm_pll_enable(volatile avr32_pm_t *pm, + unsigned int pll) +{ + pm->pll[pll] |= AVR32_PM_PLLEN_MASK; +} + + +void pm_pll_disable(volatile avr32_pm_t *pm, + unsigned int pll) +{ + pm->pll[pll] &= ~AVR32_PM_PLLEN_MASK; +} + + +void pm_wait_for_pll0_locked(volatile avr32_pm_t *pm) +{ + while (!(pm->poscsr & AVR32_PM_POSCSR_LOCK0_MASK)); + + // Bypass the lock signal of the PLL + pm->pll[0] |= AVR32_PM_PLL0_PLLBPL_MASK; +} + + +void pm_wait_for_pll1_locked(volatile avr32_pm_t *pm) +{ + while (!(pm->poscsr & AVR32_PM_POSCSR_LOCK1_MASK)); + + // Bypass the lock signal of the PLL + pm->pll[1] |= AVR32_PM_PLL1_PLLBPL_MASK; +} + + +void pm_switch_to_clock(volatile avr32_pm_t *pm, unsigned long clock) +{ + // Read + u_avr32_pm_mcctrl_t u_avr32_pm_mcctrl = {pm->mcctrl}; + // Modify + u_avr32_pm_mcctrl.MCCTRL.mcsel = clock; + // Write back + pm->mcctrl = u_avr32_pm_mcctrl.mcctrl; +} + + +void pm_switch_to_osc0(volatile avr32_pm_t *pm, unsigned int fosc0, unsigned int startup) +{ + pm_enable_osc0_crystal(pm, fosc0); // Enable the Osc0 in crystal mode + pm_enable_clk0(pm, startup); // Crystal startup time - This parameter is critical and depends on the characteristics of the crystal + pm_switch_to_clock(pm, AVR32_PM_MCSEL_OSC0); // Then switch main clock to Osc0 +} + + +void pm_bod_enable_irq(volatile avr32_pm_t *pm) +{ + pm->ier = AVR32_PM_IER_BODDET_MASK; +} + + +void pm_bod_disable_irq(volatile avr32_pm_t *pm) +{ + pm->idr = AVR32_PM_IDR_BODDET_MASK; +} + + +void pm_bod_clear_irq(volatile avr32_pm_t *pm) +{ + pm->icr = AVR32_PM_ICR_BODDET_MASK; +} + + +unsigned long pm_bod_get_irq_status(volatile avr32_pm_t *pm) +{ + return ((pm->isr & AVR32_PM_ISR_BODDET_MASK) != 0); +} + + +unsigned long pm_bod_get_irq_enable_bit(volatile avr32_pm_t *pm) +{ + return ((pm->imr & AVR32_PM_IMR_BODDET_MASK) != 0); +} + + +unsigned long pm_bod_get_level(volatile avr32_pm_t *pm) +{ + return (pm->bod & AVR32_PM_BOD_LEVEL_MASK) >> AVR32_PM_BOD_LEVEL_OFFSET; +} + + +void pm_write_gplp(volatile avr32_pm_t *pm,unsigned long gplp, unsigned long value) +{ + pm->gplp[gplp] = value; +} + + +unsigned long pm_read_gplp(volatile avr32_pm_t *pm,unsigned long gplp) +{ + return pm->gplp[gplp]; +} diff --git a/20080212/Demo/AVR32_UC3/DRIVERS/PM/pm.h b/20080212/Demo/AVR32_UC3/DRIVERS/PM/pm.h new file mode 100644 index 000000000..12ab46962 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/DRIVERS/PM/pm.h @@ -0,0 +1,335 @@ +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Power Manager driver. + * + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + *****************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef _PM_H_ +#define _PM_H_ + +#include +#include "compiler.h" +#include "preprocessor.h" + + +/*! \brief Sets the MCU in the specified sleep mode. + * + * \param mode Sleep mode: + * \arg \c AVR32_PM_SMODE_IDLE: Idle; + * \arg \c AVR32_PM_SMODE_FROZEN: Frozen; + * \arg \c AVR32_PM_SMODE_STANDBY: Standby; + * \arg \c AVR32_PM_SMODE_STOP: Stop; + * \arg \c AVR32_PM_SMODE_SHUTDOWN: Shutdown (DeepStop); + * \arg \c AVR32_PM_SMODE_STATIC: Static. + */ +#define SLEEP(mode) {__asm__ __volatile__ ("sleep "STRINGZ(mode));} + + +/*! \brief Gets the MCU reset cause. + * + * \param pm Base address of the Power Manager instance (i.e. &AVR32_PM). + * + * \return The MCU reset cause which can be masked with the + * \c AVR32_PM_RCAUSE_x_MASK bit-masks to isolate specific causes. + */ +#if __GNUC__ +__attribute__((__always_inline__)) +#endif +extern __inline__ unsigned int pm_get_reset_cause(volatile avr32_pm_t *pm) +{ + return pm->rcause; +} + + +/*! + * \brief This function will enable the external clock mode of the oscillator 0. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + */ +extern void pm_enable_osc0_ext_clock(volatile avr32_pm_t *pm); + + +/*! + * \brief This function will enable the crystal mode of the oscillator 0. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param fosc0 Oscillator 0 crystal frequency (Hz) + */ +extern void pm_enable_osc0_crystal(volatile avr32_pm_t *pm, unsigned int fosc0); + + +/*! + * \brief This function will enable the oscillator 0 to be used with a startup time. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param startup Clock 0 startup time. Time is expressed in term of RCOsc periods (3-bit value) + */ +extern void pm_enable_clk0(volatile avr32_pm_t *pm, unsigned int startup); + + +/*! + * \brief This function will disable the oscillator 0. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + */ +extern void pm_disable_clk0(volatile avr32_pm_t *pm); + + +/*! + * \brief This function will enable the oscillator 0 to be used with no startup time. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param startup Clock 0 startup time. Time is expressed in term of RCOsc periods (3-bit value) but not checked. + */ +extern void pm_enable_clk0_no_wait(volatile avr32_pm_t *pm, unsigned int startup); + + +/*! + * \brief This function will wait until the Osc0 clock is ready. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + */ +extern void pm_wait_for_clk0_ready(volatile avr32_pm_t *pm); + + +/*! + * \brief This function will enable the external clock mode of the oscillator 1. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + */ +extern void pm_enable_osc1_ext_clock(volatile avr32_pm_t *pm); + + +/*! + * \brief This function will enable the crystal mode of the oscillator 1. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param fosc1 Oscillator 1 crystal frequency (Hz) + */ +extern void pm_enable_osc1_crystal(volatile avr32_pm_t *pm, unsigned int fosc1); + + +/*! + * \brief This function will enable the oscillator 1 to be used with a startup time. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param startup Clock 1 startup time. Time is expressed in term of RCOsc periods (3-bit value) + */ +extern void pm_enable_clk1(volatile avr32_pm_t *pm, unsigned int startup); + + +/*! + * \brief This function will disable the oscillator 1. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + */ +extern void pm_disable_clk1(volatile avr32_pm_t *pm); + + +/*! + * \brief This function will enable the oscillator 1 to be used with no startup time. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param startup Clock 1 startup time. Time is expressed in term of RCOsc periods (3-bit value) but not checked. + */ +extern void pm_enable_clk1_no_wait(volatile avr32_pm_t *pm, unsigned int startup); + + +/*! + * \brief This function will wait until the Osc1 clock is ready. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + */ +extern void pm_wait_for_clk1_ready(volatile avr32_pm_t *pm); + + +/*! + * \brief This function will enable the external clock mode of the 32-kHz oscillator. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + */ +extern void pm_enable_osc32_ext_clock(volatile avr32_pm_t *pm); + + +/*! + * \brief This function will enable the crystal mode of the 32-kHz oscillator. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + */ +extern void pm_enable_osc32_crystal(volatile avr32_pm_t *pm); + + +/*! + * \brief This function will enable the oscillator 32 to be used with a startup time. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param startup Clock 32 kHz startup time. Time is expressed in term of RCOsc periods (3-bit value) + */ +extern void pm_enable_clk32(volatile avr32_pm_t *pm, unsigned int startup); + + +/*! + * \brief This function will disable the oscillator 32. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + */ +extern void pm_disable_clk32(volatile avr32_pm_t *pm); + + +/*! + * \brief This function will enable the oscillator 32 to be used with no startup time. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param startup Clock 32 kHz startup time. Time is expressed in term of RCOsc periods (3-bit value) but not checked. + */ +extern void pm_enable_clk32_no_wait(volatile avr32_pm_t *pm, unsigned int startup); + + +/*! + * \brief This function will wait until the osc32 clock is ready. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + */ +extern void pm_wait_for_clk32_ready(volatile avr32_pm_t *pm); + + +/*! + * \brief This function will select all the power manager clocks. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param pbadiv Peripheral Bus A clock divisor enable + * \param pbasel Peripheral Bus A select + * \param pbbdiv Peripheral Bus B clock divisor enable + * \param pbbsel Peripheral Bus B select + * \param hsbdiv High Speed Bus clock divisor enable (CPU clock = HSB clock) + * \param hsbsel High Speed Bus select (CPU clock = HSB clock ) + */ +extern void pm_cksel(volatile avr32_pm_t *pm, unsigned int pbadiv, unsigned int pbasel, unsigned int pbbdiv, unsigned int pbbsel, unsigned int hsbdiv, unsigned int hsbsel); + + +/*! + * \brief This function will setup a generic clock. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param gc generic clock number (0 for gc0...) + * \param osc_or_pll Use OSC (=0) or PLL (=1) + * \param pll_osc Select Osc0/PLL0 or Osc1/PLL1 + * \param diven Generic clock divisor enable + * \param div Generic clock divisor + */ +extern void pm_gc_setup(volatile avr32_pm_t *pm, unsigned int gc, unsigned int osc_or_pll, unsigned int pll_osc, unsigned int diven, unsigned int div); + + +/*! + * \brief This function will enable a generic clock. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param gc generic clock number (0 for gc0...) + */ +extern void pm_gc_enable(volatile avr32_pm_t *pm, unsigned int gc); + + +/*! + * \brief This function will disable a generic clock. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param gc generic clock number (0 for gc0...) + */ +extern void pm_gc_disable(volatile avr32_pm_t *pm, unsigned int gc); + + +/*! + * \brief This function will setup a PLL. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param pll PLL number(0 for PLL0, 1 for PLL1) + * \param mul PLL MUL in the PLL formula + * \param div PLL DIV in the PLL formula + * \param osc OSC number (0 for osc0, 1 for osc1) + * \param lockcount PLL lockount + */ +extern void pm_pll_setup(volatile avr32_pm_t *pm, unsigned int pll, unsigned int mul, unsigned int div, unsigned int osc, unsigned int lockcount); + + +/*! + * \brief This function will set a PLL option. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param pll PLL number(0 for PLL0, 1 for PLL1) + * \param pll_freq Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz. + * \param pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value) + * \param pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode. + */ +extern void pm_pll_set_option(volatile avr32_pm_t *pm, unsigned int pll, unsigned int pll_freq, unsigned int pll_div2, unsigned int pll_wbwdisable); + + +/*! + * \brief This function will get a PLL option. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param pll PLL number(0 for PLL0, 1 for PLL1) + * \return Option + */ +extern unsigned int pm_pll_get_option(volatile avr32_pm_t *pm, unsigned int pll); + + +/*! + * \brief This function will enable a PLL. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param pll PLL number(0 for PLL0, 1 for PLL1) + */ +extern void pm_pll_enable(volatile avr32_pm_t *pm, unsigned int pll); + + +/*! + * \brief This function will disable a PLL. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param pll PLL number(0 for PLL0, 1 for PLL1) + */ +extern void pm_pll_disable(volatile avr32_pm_t *pm, unsigned int pll); + + +/*! + * \brief This function will wait for PLL0 locked + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + */ +extern void pm_wait_for_pll0_locked(volatile avr32_pm_t *pm); + + +/*! + * \brief This function will wait for PLL1 locked + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + */ +extern void pm_wait_for_pll1_locked(volatile avr32_pm_t *pm); + + +/*! + * \brief This function will switch the power manager main clock. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param clock Clock to be switched on. AVR32_PM_MCSEL_SLOW for RCOsc, AVR32_PM_MCSEL_OSC0 for Osc0, AVR32_PM_MCSEL_PLL0 for PLL0. + */ +extern void pm_switch_to_clock(volatile avr32_pm_t *pm, unsigned long clock); + + +/*! + * \brief Switch main clock to clock Osc0 (crystal mode) + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param fosc0 Oscillator 0 crystal frequency (Hz) + * \param startup Crystal 0 startup time. Time is expressed in term of RCOsc periods (3-bit value) + */ +extern void pm_switch_to_osc0(volatile avr32_pm_t *pm, unsigned int fosc0, unsigned int startup); + + +#endif // _PM_H_ diff --git a/20080212/Demo/AVR32_UC3/DRIVERS/TC/tc.c b/20080212/Demo/AVR32_UC3/DRIVERS/TC/tc.c new file mode 100644 index 000000000..e63cc8f9f --- /dev/null +++ b/20080212/Demo/AVR32_UC3/DRIVERS/TC/tc.c @@ -0,0 +1,292 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief TC driver for AVR32 UC3. + * + * AVR32 Timer/Counter driver module. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with a TC module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include +#include "compiler.h" +#include "tc.h" + + +int tc_get_interrupt_settings(volatile avr32_tc_t *tc, unsigned int channel) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + return tc->channel[channel].imr; +} + + +int tc_configure_interrupts(volatile avr32_tc_t *tc, unsigned int channel, const tc_interrupt_t *bitfield) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + // Enable the appropriate interrupts. + tc->channel[channel].ier = bitfield->etrgs << AVR32_TC_ETRGS_OFFSET | + bitfield->ldrbs << AVR32_TC_LDRBS_OFFSET | + bitfield->ldras << AVR32_TC_LDRAS_OFFSET | + bitfield->cpcs << AVR32_TC_CPCS_OFFSET | + bitfield->cpbs << AVR32_TC_CPBS_OFFSET | + bitfield->cpas << AVR32_TC_CPAS_OFFSET | + bitfield->lovrs << AVR32_TC_LOVRS_OFFSET | + bitfield->covfs << AVR32_TC_COVFS_OFFSET; + + // Disable the appropriate interrupts. + tc->channel[channel].idr = (~bitfield->etrgs & 1) << AVR32_TC_ETRGS_OFFSET | + (~bitfield->ldrbs & 1) << AVR32_TC_LDRBS_OFFSET | + (~bitfield->ldras & 1) << AVR32_TC_LDRAS_OFFSET | + (~bitfield->cpcs & 1) << AVR32_TC_CPCS_OFFSET | + (~bitfield->cpbs & 1) << AVR32_TC_CPBS_OFFSET | + (~bitfield->cpas & 1) << AVR32_TC_CPAS_OFFSET | + (~bitfield->lovrs & 1) << AVR32_TC_LOVRS_OFFSET | + (~bitfield->covfs & 1) << AVR32_TC_COVFS_OFFSET; + + return 0; +} + + +int tc_select_external_clock(volatile avr32_tc_t *tc, unsigned int channel, unsigned int ext_clk_sig_src) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS || ext_clk_sig_src >= 1 << AVR32_TC_BMR_TC0XC0S_SIZE) + return TC_INVALID_ARGUMENT; + + // Clear bit-field and set the correct behavior. + tc->bmr = (tc->bmr & ~(AVR32_TC_BMR_TC0XC0S_MASK << (channel * AVR32_TC_BMR_TC0XC0S_SIZE))) | + (ext_clk_sig_src << (channel * AVR32_TC_BMR_TC0XC0S_SIZE)); + + return 0; +} + + +int tc_init_capture(volatile avr32_tc_t *tc, const tc_capture_opt_t *opt) +{ + // Check for valid input. + if (opt->channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + // MEASURE SIGNALS: Capture operating mode. + tc->channel[opt->channel].cmr = opt->ldrb << AVR32_TC_LDRB_OFFSET | + opt->ldra << AVR32_TC_LDRA_OFFSET | + 0 << AVR32_TC_WAVE_OFFSET | + opt->cpctrg << AVR32_TC_CPCTRG_OFFSET | + opt->abetrg << AVR32_TC_ABETRG_OFFSET | + opt->etrgedg << AVR32_TC_ETRGEDG_OFFSET| + opt->ldbdis << AVR32_TC_LDBDIS_OFFSET | + opt->ldbstop << AVR32_TC_LDBSTOP_OFFSET | + opt->burst << AVR32_TC_BURST_OFFSET | + opt->clki << AVR32_TC_CLKI_OFFSET | + opt->tcclks << AVR32_TC_TCCLKS_OFFSET; + + return 0; +} + + +int tc_init_waveform(volatile avr32_tc_t *tc, const tc_waveform_opt_t *opt) +{ + // Check for valid input. + if (opt->channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + // GENERATE SIGNALS: Waveform operating mode. + tc->channel[opt->channel].cmr = opt->bswtrg << AVR32_TC_BSWTRG_OFFSET | + opt->beevt << AVR32_TC_BEEVT_OFFSET | + opt->bcpc << AVR32_TC_BCPC_OFFSET | + opt->bcpb << AVR32_TC_BCPB_OFFSET | + opt->aswtrg << AVR32_TC_ASWTRG_OFFSET | + opt->aeevt << AVR32_TC_AEEVT_OFFSET | + opt->acpc << AVR32_TC_ACPC_OFFSET | + opt->acpa << AVR32_TC_ACPA_OFFSET | + 1 << AVR32_TC_WAVE_OFFSET | + opt->wavsel << AVR32_TC_WAVSEL_OFFSET | + opt->enetrg << AVR32_TC_ENETRG_OFFSET | + opt->eevt << AVR32_TC_EEVT_OFFSET | + opt->eevtedg << AVR32_TC_EEVTEDG_OFFSET | + opt->cpcdis << AVR32_TC_CPCDIS_OFFSET | + opt->cpcstop << AVR32_TC_CPCSTOP_OFFSET | + opt->burst << AVR32_TC_BURST_OFFSET | + opt->clki << AVR32_TC_CLKI_OFFSET | + opt->tcclks << AVR32_TC_TCCLKS_OFFSET; + + return 0; +} + + +int tc_start(volatile avr32_tc_t *tc, unsigned int channel) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + // Enable, reset and start the selected timer/counter channel. + tc->channel[channel].ccr = AVR32_TC_SWTRG_MASK | AVR32_TC_CLKEN_MASK; + + return 0; +} + + +int tc_stop(volatile avr32_tc_t *tc, unsigned int channel) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + // Disable the selected timer/counter channel. + tc->channel[channel].ccr = AVR32_TC_CLKDIS_MASK; + + return 0; +} + + +int tc_software_trigger(volatile avr32_tc_t *tc, unsigned int channel) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + // Reset the selected timer/counter channel. + tc->channel[channel].ccr = AVR32_TC_SWTRG_MASK; + + return 0; +} + + +void tc_sync_trigger(volatile avr32_tc_t *tc) +{ + // Reset all channels of the selected timer/counter. + tc->bcr = AVR32_TC_BCR_SYNC_MASK; +} + + +int tc_read_sr(volatile avr32_tc_t *tc, unsigned int channel) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + return tc->channel[channel].sr; +} + + +int tc_read_tc(volatile avr32_tc_t *tc, unsigned int channel) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + return Rd_bitfield(tc->channel[channel].cv, AVR32_TC_CV_MASK); +} + + +int tc_read_ra(volatile avr32_tc_t *tc, unsigned int channel) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + return Rd_bitfield(tc->channel[channel].ra, AVR32_TC_RA_MASK); +} + + +int tc_read_rb(volatile avr32_tc_t *tc, unsigned int channel) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + return Rd_bitfield(tc->channel[channel].rb, AVR32_TC_RB_MASK); +} + + +int tc_read_rc(volatile avr32_tc_t *tc, unsigned int channel) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + return Rd_bitfield(tc->channel[channel].rc, AVR32_TC_RC_MASK); +} + + +int tc_write_ra(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + // This function is only available in WAVEFORM mode. + if (Tst_bits(tc->channel[channel].cmr, AVR32_TC_WAVE_MASK)) + Wr_bitfield(tc->channel[channel].ra, AVR32_TC_RA_MASK, value); + + return value; +} + + +int tc_write_rb(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + // This function is only available in WAVEFORM mode. + if (Tst_bits(tc->channel[channel].cmr, AVR32_TC_WAVE_MASK)) + Wr_bitfield(tc->channel[channel].rb, AVR32_TC_RB_MASK, value); + + return value; +} + + +int tc_write_rc(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + // This function is only available in WAVEFORM mode. + if (Tst_bits(tc->channel[channel].cmr, AVR32_TC_WAVE_MASK)) + Wr_bitfield(tc->channel[channel].rc, AVR32_TC_RC_MASK, value); + + return value; +} diff --git a/20080212/Demo/AVR32_UC3/DRIVERS/TC/tc.h b/20080212/Demo/AVR32_UC3/DRIVERS/TC/tc.h new file mode 100644 index 000000000..381008bee --- /dev/null +++ b/20080212/Demo/AVR32_UC3/DRIVERS/TC/tc.h @@ -0,0 +1,580 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Timer/Counter driver for AVR32 UC3. + * + * AVR32 Timer/Counter driver module. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with a TC module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef _TC_H_ +#define _TC_H_ + +#include + + +//! TC driver functions return value in case of invalid argument(s). +#define TC_INVALID_ARGUMENT (-1) + +//! Number of timer/counter channels. +#define TC_NUMBER_OF_CHANNELS (sizeof(((avr32_tc_t *)0)->channel) / sizeof(avr32_tc_channel_t)) + +/*! \name External Clock Signal 0 Selection + */ +//! @{ +#define TC_CH0_EXT_CLK0_SRC_TCLK0 AVR32_TC_TC0XC0S_TCLK0 +#define TC_CH0_EXT_CLK0_SRC_NO_CLK AVR32_TC_TC0XC0S_NO_CLK +#define TC_CH0_EXT_CLK0_SRC_TIOA1 AVR32_TC_TC0XC0S_TIOA1 +#define TC_CH0_EXT_CLK0_SRC_TIOA2 AVR32_TC_TC0XC0S_TIOA2 +//! @} + +/*! \name External Clock Signal 1 Selection + */ +//! @{ +#define TC_CH1_EXT_CLK1_SRC_TCLK1 AVR32_TC_TC1XC1S_TCLK1 +#define TC_CH1_EXT_CLK1_SRC_NO_CLK AVR32_TC_TC1XC1S_NO_CLK +#define TC_CH1_EXT_CLK1_SRC_TIOA0 AVR32_TC_TC1XC1S_TIOA0 +#define TC_CH1_EXT_CLK1_SRC_TIOA2 AVR32_TC_TC1XC1S_TIOA2 +//! @} + +/*! \name External Clock Signal 2 Selection + */ +//! @{ +#define TC_CH2_EXT_CLK2_SRC_TCLK2 AVR32_TC_TC2XC2S_TCLK2 +#define TC_CH2_EXT_CLK2_SRC_NO_CLK AVR32_TC_TC2XC2S_NO_CLK +#define TC_CH2_EXT_CLK2_SRC_TIOA0 AVR32_TC_TC2XC2S_TIOA0 +#define TC_CH2_EXT_CLK2_SRC_TIOA1 AVR32_TC_TC2XC2S_TIOA1 +//! @} + +/*! \name Event/Trigger Actions on Output + */ +//! @{ +#define TC_EVT_EFFECT_NOOP AVR32_TC_NONE +#define TC_EVT_EFFECT_SET AVR32_TC_SET +#define TC_EVT_EFFECT_CLEAR AVR32_TC_CLEAR +#define TC_EVT_EFFECT_TOGGLE AVR32_TC_TOGGLE +//! @} + +/*! \name RC Compare Trigger Enable + */ +//! @{ +#define TC_NO_TRIGGER_COMPARE_RC 0 +#define TC_TRIGGER_COMPARE_RC 1 +//! @} + +/*! \name Waveform Selection + */ +//! @{ +#define TC_WAVEFORM_SEL_UP_MODE AVR32_TC_WAVSEL_UP_NO_AUTO +#define TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER AVR32_TC_WAVSEL_UP_AUTO +#define TC_WAVEFORM_SEL_UPDOWN_MODE AVR32_TC_WAVSEL_UPDOWN_NO_AUTO +#define TC_WAVEFORM_SEL_UPDOWN_MODE_RC_TRIGGER AVR32_TC_WAVSEL_UPDOWN_AUTO +//! @} + +/*! \name TIOA or TIOB External Trigger Selection + */ +//! @{ +#define TC_EXT_TRIG_SEL_TIOA 1 +#define TC_EXT_TRIG_SEL_TIOB 0 +//! @} + +/*! \name External Event Selection + */ +//! @{ +#define TC_EXT_EVENT_SEL_TIOB_INPUT AVR32_TC_EEVT_TIOB_INPUT +#define TC_EXT_EVENT_SEL_XC0_OUTPUT AVR32_TC_EEVT_XC0_OUTPUT +#define TC_EXT_EVENT_SEL_XC1_OUTPUT AVR32_TC_EEVT_XC1_OUTPUT +#define TC_EXT_EVENT_SEL_XC2_OUTPUT AVR32_TC_EEVT_XC2_OUTPUT +//! @} + +/*! \name Edge Selection + */ +//! @{ +#define TC_SEL_NO_EDGE AVR32_TC_EEVTEDG_NO_EDGE +#define TC_SEL_RISING_EDGE AVR32_TC_EEVTEDG_POS_EDGE +#define TC_SEL_FALLING_EDGE AVR32_TC_EEVTEDG_NEG_EDGE +#define TC_SEL_EACH_EDGE AVR32_TC_EEVTEDG_BOTH_EDGES +//! @} + +/*! \name Burst Signal Selection + */ +//! @{ +#define TC_BURST_NOT_GATED AVR32_TC_BURST_NOT_GATED +#define TC_BURST_CLK_AND_XC0 AVR32_TC_BURST_CLK_AND_XC0 +#define TC_BURST_CLK_AND_XC1 AVR32_TC_BURST_CLK_AND_XC1 +#define TC_BURST_CLK_AND_XC2 AVR32_TC_BURST_CLK_AND_XC2 +//! @} + +/*! \name Clock Invert + */ +//! @{ +#define TC_CLOCK_RISING_EDGE 0 +#define TC_CLOCK_FALLING_EDGE 1 +//! @} + +/*! \name Clock Selection + */ +//! @{ +#define TC_CLOCK_SOURCE_TC1 AVR32_TC_TCCLKS_TIMER_DIV1_CLOCK +#define TC_CLOCK_SOURCE_TC2 AVR32_TC_TCCLKS_TIMER_DIV2_CLOCK +#define TC_CLOCK_SOURCE_TC3 AVR32_TC_TCCLKS_TIMER_DIV3_CLOCK +#define TC_CLOCK_SOURCE_TC4 AVR32_TC_TCCLKS_TIMER_DIV4_CLOCK +#define TC_CLOCK_SOURCE_TC5 AVR32_TC_TCCLKS_TIMER_DIV5_CLOCK +#define TC_CLOCK_SOURCE_XC0 AVR32_TC_TCCLKS_XC0 +#define TC_CLOCK_SOURCE_XC1 AVR32_TC_TCCLKS_XC1 +#define TC_CLOCK_SOURCE_XC2 AVR32_TC_TCCLKS_XC2 +//! @} + + +//! Timer/counter interrupts. +typedef struct +{ + unsigned int :24; + + //! External trigger interrupt. + unsigned int etrgs : 1; + + //! RB load interrupt. + unsigned int ldrbs : 1; + + //! RA load interrupt. + unsigned int ldras : 1; + + //! RC compare interrupt. + unsigned int cpcs : 1; + + //! RB compare interrupt. + unsigned int cpbs : 1; + + //! RA compare interrupt. + unsigned int cpas : 1; + + //! Load overrun interrupt. + unsigned int lovrs : 1; + + //! Counter overflow interrupt. + unsigned int covfs : 1; +} tc_interrupt_t; + +//! Parameters when initializing a timer/counter in capture mode. +typedef struct +{ + //! Channel to initialize. + unsigned int channel ; + + unsigned int :12; + + //! RB loading selection:\n + //! - \ref TC_SEL_NO_EDGE;\n + //! - \ref TC_SEL_RISING_EDGE;\n + //! - \ref TC_SEL_FALLING_EDGE;\n + //! - \ref TC_SEL_EACH_EDGE. + unsigned int ldrb : 2; + + //! RA loading selection:\n + //! - \ref TC_SEL_NO_EDGE;\n + //! - \ref TC_SEL_RISING_EDGE;\n + //! - \ref TC_SEL_FALLING_EDGE;\n + //! - \ref TC_SEL_EACH_EDGE. + unsigned int ldra : 2; + + unsigned int : 1; + + //! RC compare trigger enable:\n + //! - \ref TC_NO_TRIGGER_COMPARE_RC;\n + //! - \ref TC_TRIGGER_COMPARE_RC. + unsigned int cpctrg : 1; + + unsigned int : 3; + + //! TIOA or TIOB external trigger selection:\n + //! - \ref TC_EXT_TRIG_SEL_TIOA;\n + //! - \ref TC_EXT_TRIG_SEL_TIOB. + unsigned int abetrg : 1; + + //! External trigger edge selection:\n + //! - \ref TC_SEL_NO_EDGE;\n + //! - \ref TC_SEL_RISING_EDGE;\n + //! - \ref TC_SEL_FALLING_EDGE;\n + //! - \ref TC_SEL_EACH_EDGE. + unsigned int etrgedg : 2; + + //! Counter clock disable with RB loading:\n + //! - \c FALSE;\n + //! - \c TRUE. + unsigned int ldbdis : 1; + + //! Counter clock stopped with RB loading:\n + //! - \c FALSE;\n + //! - \c TRUE. + unsigned int ldbstop : 1; + + //! Burst signal selection:\n + //! - \ref TC_BURST_NOT_GATED;\n + //! - \ref TC_BURST_CLK_AND_XC0;\n + //! - \ref TC_BURST_CLK_AND_XC1;\n + //! - \ref TC_BURST_CLK_AND_XC2. + unsigned int burst : 2; + + //! Clock invert:\n + //! - \ref TC_CLOCK_RISING_EDGE;\n + //! - \ref TC_CLOCK_FALLING_EDGE. + unsigned int clki : 1; + + //! Clock selection:\n + //! - \ref TC_CLOCK_SOURCE_TC1;\n + //! - \ref TC_CLOCK_SOURCE_TC2;\n + //! - \ref TC_CLOCK_SOURCE_TC3;\n + //! - \ref TC_CLOCK_SOURCE_TC4;\n + //! - \ref TC_CLOCK_SOURCE_TC5;\n + //! - \ref TC_CLOCK_SOURCE_XC0;\n + //! - \ref TC_CLOCK_SOURCE_XC1;\n + //! - \ref TC_CLOCK_SOURCE_XC2. + unsigned int tcclks : 3; +} tc_capture_opt_t; + +//! Parameters when initializing a timer/counter in waveform mode. +typedef struct +{ + //! Channel to initialize. + unsigned int channel ; + + //! Software trigger effect on TIOB:\n + //! - \ref TC_EVT_EFFECT_NOOP;\n + //! - \ref TC_EVT_EFFECT_SET;\n + //! - \ref TC_EVT_EFFECT_CLEAR;\n + //! - \ref TC_EVT_EFFECT_TOGGLE. + unsigned int bswtrg : 2; + + //! External event effect on TIOB:\n + //! - \ref TC_EVT_EFFECT_NOOP;\n + //! - \ref TC_EVT_EFFECT_SET;\n + //! - \ref TC_EVT_EFFECT_CLEAR;\n + //! - \ref TC_EVT_EFFECT_TOGGLE. + unsigned int beevt : 2; + + //! RC compare effect on TIOB:\n + //! - \ref TC_EVT_EFFECT_NOOP;\n + //! - \ref TC_EVT_EFFECT_SET;\n + //! - \ref TC_EVT_EFFECT_CLEAR;\n + //! - \ref TC_EVT_EFFECT_TOGGLE. + unsigned int bcpc : 2; + + //! RB compare effect on TIOB:\n + //! - \ref TC_EVT_EFFECT_NOOP;\n + //! - \ref TC_EVT_EFFECT_SET;\n + //! - \ref TC_EVT_EFFECT_CLEAR;\n + //! - \ref TC_EVT_EFFECT_TOGGLE. + unsigned int bcpb : 2; + + //! Software trigger effect on TIOA:\n + //! - \ref TC_EVT_EFFECT_NOOP;\n + //! - \ref TC_EVT_EFFECT_SET;\n + //! - \ref TC_EVT_EFFECT_CLEAR;\n + //! - \ref TC_EVT_EFFECT_TOGGLE. + unsigned int aswtrg : 2; + + //! External event effect on TIOA:\n + //! - \ref TC_EVT_EFFECT_NOOP;\n + //! - \ref TC_EVT_EFFECT_SET;\n + //! - \ref TC_EVT_EFFECT_CLEAR;\n + //! - \ref TC_EVT_EFFECT_TOGGLE. + unsigned int aeevt : 2; + + //! RC compare effect on TIOA:\n + //! - \ref TC_EVT_EFFECT_NOOP;\n + //! - \ref TC_EVT_EFFECT_SET;\n + //! - \ref TC_EVT_EFFECT_CLEAR;\n + //! - \ref TC_EVT_EFFECT_TOGGLE. + unsigned int acpc : 2; + + //! RA compare effect on TIOA:\n + //! - \ref TC_EVT_EFFECT_NOOP;\n + //! - \ref TC_EVT_EFFECT_SET;\n + //! - \ref TC_EVT_EFFECT_CLEAR;\n + //! - \ref TC_EVT_EFFECT_TOGGLE. + unsigned int acpa : 2; + + unsigned int : 1; + + //! Waveform selection:\n + //! - \ref TC_WAVEFORM_SEL_UP_MODE;\n + //! - \ref TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER;\n + //! - \ref TC_WAVEFORM_SEL_UPDOWN_MODE;\n + //! - \ref TC_WAVEFORM_SEL_UPDOWN_MODE_RC_TRIGGER. + unsigned int wavsel : 2; + + //! External event trigger enable:\n + //! - \c FALSE;\n + //! - \c TRUE. + unsigned int enetrg : 1; + + //! External event selection:\n + //! - \ref TC_EXT_EVENT_SEL_TIOB_INPUT;\n + //! - \ref TC_EXT_EVENT_SEL_XC0_OUTPUT;\n + //! - \ref TC_EXT_EVENT_SEL_XC1_OUTPUT;\n + //! - \ref TC_EXT_EVENT_SEL_XC2_OUTPUT. + unsigned int eevt : 2; + + //! External event edge selection:\n + //! - \ref TC_SEL_NO_EDGE;\n + //! - \ref TC_SEL_RISING_EDGE;\n + //! - \ref TC_SEL_FALLING_EDGE;\n + //! - \ref TC_SEL_EACH_EDGE. + unsigned int eevtedg : 2; + + //! Counter clock disable with RC compare:\n + //! - \c FALSE;\n + //! - \c TRUE. + unsigned int cpcdis : 1; + + //! Counter clock stopped with RC compare:\n + //! - \c FALSE;\n + //! - \c TRUE. + unsigned int cpcstop : 1; + + //! Burst signal selection:\n + //! - \ref TC_BURST_NOT_GATED;\n + //! - \ref TC_BURST_CLK_AND_XC0;\n + //! - \ref TC_BURST_CLK_AND_XC1;\n + //! - \ref TC_BURST_CLK_AND_XC2. + unsigned int burst : 2; + + //! Clock invert:\n + //! - \ref TC_CLOCK_RISING_EDGE;\n + //! - \ref TC_CLOCK_FALLING_EDGE. + unsigned int clki : 1; + + //! Clock selection:\n + //! - \ref TC_CLOCK_SOURCE_TC1;\n + //! - \ref TC_CLOCK_SOURCE_TC2;\n + //! - \ref TC_CLOCK_SOURCE_TC3;\n + //! - \ref TC_CLOCK_SOURCE_TC4;\n + //! - \ref TC_CLOCK_SOURCE_TC5;\n + //! - \ref TC_CLOCK_SOURCE_XC0;\n + //! - \ref TC_CLOCK_SOURCE_XC1;\n + //! - \ref TC_CLOCK_SOURCE_XC2. + unsigned int tcclks : 3; +} tc_waveform_opt_t; + + +/*! \brief Reads timer/counter interrupt settings. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * + * \retval >=0 The interrupt enable configuration organized according to \ref tc_interrupt_t. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_get_interrupt_settings(volatile avr32_tc_t *tc, unsigned int channel); + +/*! \brief Enables various timer/counter interrupts. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * \param bitfield The interrupt enable configuration. + * + * \retval 0 Success. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_configure_interrupts(volatile avr32_tc_t *tc, unsigned int channel, const tc_interrupt_t *bitfield); + +/*! \brief Selects which external clock to use and how to configure it. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * \param ext_clk_sig_src External clock signal selection: + * \arg \c TC_CH0_EXT_CLK0_SRC_TCLK0; + * \arg \c TC_CH0_EXT_CLK0_SRC_NO_CLK; + * \arg \c TC_CH0_EXT_CLK0_SRC_TIOA1; + * \arg \c TC_CH0_EXT_CLK0_SRC_TIOA2; + * \arg \c TC_CH1_EXT_CLK1_SRC_TCLK1; + * \arg \c TC_CH1_EXT_CLK1_SRC_NO_CLK; + * \arg \c TC_CH1_EXT_CLK1_SRC_TIOA0; + * \arg \c TC_CH1_EXT_CLK1_SRC_TIOA2; + * \arg \c TC_CH2_EXT_CLK2_SRC_TCLK2; + * \arg \c TC_CH2_EXT_CLK2_SRC_NO_CLK; + * \arg \c TC_CH2_EXT_CLK2_SRC_TIOA0; + * \arg \c TC_CH2_EXT_CLK2_SRC_TIOA1. + * + * \retval 0 Success. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_select_external_clock(volatile avr32_tc_t *tc, unsigned int channel, unsigned int ext_clk_sig_src); + +/*! \brief Sets options for timer/counter capture initialization. + * + * \param tc Pointer to the TC instance to access. + * \param opt Options for capture mode. + * + * \retval 0 Success. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_init_capture(volatile avr32_tc_t *tc, const tc_capture_opt_t *opt); + +/*! \brief Sets options for timer/counter waveform initialization. + * + * \param tc Pointer to the TC instance to access. + * \param opt Options for waveform generation. + * + * \retval 0 Success. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_init_waveform(volatile avr32_tc_t *tc, const tc_waveform_opt_t *opt); + +/*! \brief Starts a timer/counter. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * + * \retval 0 Success. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_start(volatile avr32_tc_t *tc, unsigned int channel); + +/*! \brief Stops a timer/counter. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * + * \retval 0 Success. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_stop(volatile avr32_tc_t *tc, unsigned int channel); + +/*! \brief Performs a software trigger: the counter is reset and the clock is started. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * + * \retval 0 Success. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_software_trigger(volatile avr32_tc_t *tc, unsigned int channel); + +/*! \brief Asserts a SYNC signal to generate a software trigger and reset all channels. + * + * \param tc Pointer to the TC instance to access. + */ +extern void tc_sync_trigger(volatile avr32_tc_t *tc); + +/*! \brief Reads the status register. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * + * \retval >=0 Status register value. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_read_sr(volatile avr32_tc_t *tc, unsigned int channel); + +/*! \brief Reads the channel's TC counter and returns the value. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * + * \retval >=0 TC counter value. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_read_tc(volatile avr32_tc_t *tc, unsigned int channel); + +/*! \brief Reads the channel's RA register and returns the value. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * + * \retval >=0 RA register value. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_read_ra(volatile avr32_tc_t *tc, unsigned int channel); + +/*! \brief Reads the channel's RB register and returns the value. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * + * \retval >=0 RB register value. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_read_rb(volatile avr32_tc_t *tc, unsigned int channel); + +/*! \brief Reads the channel's RC register and returns the value. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * + * \retval >=0 RC register value. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_read_rc(volatile avr32_tc_t *tc, unsigned int channel); + +/*! \brief Writes a value to the channel's RA register. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * \param value Value to write to the RA register. + * + * \retval >=0 Written value. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_write_ra(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value); + +/*! \brief Writes a value to the channel's RB register. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * \param value Value to write to the RB register. + * + * \retval >=0 Written value. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_write_rb(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value); + +/*! \brief Writes a value to the channel's RC register. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * \param value Value to write to the RC register. + * + * \retval >=0 Written value. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_write_rc(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value); + + +#endif // _TC_H_ diff --git a/20080212/Demo/AVR32_UC3/DRIVERS/USART/usart.c b/20080212/Demo/AVR32_UC3/DRIVERS/USART/usart.c new file mode 100644 index 000000000..3110bf5af --- /dev/null +++ b/20080212/Demo/AVR32_UC3/DRIVERS/USART/usart.c @@ -0,0 +1,448 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief USART driver for AVR32 UC3. + * + * This file contains basic functions for the AVR32 USART, with support for all + * modes, settings and clock speeds. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with a USART module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include "usart.h" + + +//------------------------------------------------------------------------------ +/*! \name Private Functions + */ +//! @{ + + +/*! \brief Checks if the USART is in multidrop mode. + * + * \param usart Base address of the USART instance. + * + * \return \c 1 if the USART is in multidrop mode, otherwise \c 0. + */ +#if __GNUC__ +__attribute__((__always_inline__)) +#endif +static __inline__ int usart_mode_is_multidrop(volatile avr32_usart_t *usart) +{ + return ((usart->mr >> AVR32_USART_MR_PAR_OFFSET) & AVR32_USART_MR_PAR_MULTI) == AVR32_USART_MR_PAR_MULTI; +} + + +/*! \brief Calculates a clock divider (\e CD) that gets the USART as close to a + * wanted baudrate as possible. + * + * \todo manage the FP fractal part to avoid big errors + * + * Baudrate calculation: + * \f$ baudrate = \frac{Selected Clock}{16 \times CD} \f$ with 16x oversampling or + * \f$ baudrate = \frac{Selected Clock}{8 \times CD} \f$ with 8x oversampling or + * \f$ baudrate = \frac{Selected Clock}{CD} \f$ with SYNC bit set to allow high speed. + * + * \param usart Base address of the USART instance. + * \param baudrate Wanted baudrate. + * \param pba_hz USART module input clock frequency (PBA clock, Hz). + * + * \retval USART_SUCCESS Baudrate successfully initialized. + * \retval USART_INVALID_INPUT Wanted baudrate is impossible with given clock speed. + */ + +static int usart_set_baudrate(volatile avr32_usart_t *usart, unsigned int baudrate, long pba_hz) +{ + // Clock divider. + int cd; + + // Baudrate calculation. + if (baudrate < pba_hz / 16) + { + // Use 16x oversampling, clear SYNC bit. + usart->mr &=~ (AVR32_USART_MR_OVER_MASK | AVR32_USART_MR_SYNC_MASK); + cd = (pba_hz + 8 * baudrate) / (16 * baudrate); + + if ((cd >65535)) return USART_INVALID_INPUT; + } + else if (baudrate < pba_hz / 8) + { + // Use 8x oversampling. + usart->mr |= AVR32_USART_MR_OVER_MASK; + // clear SYNC bit + usart->mr &=~ AVR32_USART_MR_SYNC_MASK; + + cd = (pba_hz + 4 * baudrate) / (8 * baudrate); + + if ((cd < 1)||(cd >65535)) return USART_INVALID_INPUT; + } + else + { + // set SYNC to 1 + usart->mr |= AVR32_USART_MR_SYNC_MASK; + // use PBA/BaudRate + cd = (pba_hz / baudrate); + } + usart->brgr = cd << AVR32_USART_BRGR_CD_OFFSET; + + return USART_SUCCESS; +} + +//! @} + + +//------------------------------------------------------------------------------ +/*! \name Initialization Functions + */ +//! @{ + + +void usart_reset(volatile avr32_usart_t *usart) +{ + // Disable all USART interrupts. + // Interrupts needed should be set explicitly on every reset. + usart->idr = 0xFFFFFFFF; + + // Reset mode and other registers that could cause unpredictable behavior after reset. + usart->mr = 0; + usart->rtor = 0; + usart->ttgr = 0; + + // Shutdown TX and RX (will be re-enabled when setup has successfully completed), + // reset status bits and turn off DTR and RTS. + usart->cr = AVR32_USART_CR_RSTRX_MASK | + AVR32_USART_CR_RSTTX_MASK | + AVR32_USART_CR_RSTSTA_MASK | + AVR32_USART_CR_RSTIT_MASK | + AVR32_USART_CR_RSTNACK_MASK | + AVR32_USART_CR_DTRDIS_MASK | + AVR32_USART_CR_RTSDIS_MASK; +} + + +int usart_init_rs232(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz) +{ + // Reset the USART and shutdown TX and RX. + usart_reset(usart); + + // Check input values. + if (!opt) // Null pointer. + return USART_INVALID_INPUT; + if (opt->charlength < 5 || opt->charlength > 9 || + opt->paritytype > 7 || + opt->stopbits > 2 + 255 || + opt->channelmode > 3) + return USART_INVALID_INPUT; + + if (usart_set_baudrate(usart, opt->baudrate, pba_hz) == USART_INVALID_INPUT) + return USART_INVALID_INPUT; + + if (opt->charlength == 9) + { + // Character length set to 9 bits. MODE9 dominates CHRL. + usart->mr |= AVR32_USART_MR_MODE9_MASK; + } + else + { + // CHRL gives the character length (- 5) when MODE9 = 0. + usart->mr |= (opt->charlength - 5) << AVR32_USART_MR_CHRL_OFFSET; + } + + usart->mr |= (opt->channelmode << AVR32_USART_MR_CHMODE_OFFSET) | + (opt->paritytype << AVR32_USART_MR_PAR_OFFSET); + + if (opt->stopbits > USART_2_STOPBITS) + { + // Set two stop bits + usart->mr |= AVR32_USART_MR_NBSTOP_2 << AVR32_USART_MR_NBSTOP_OFFSET; + // and a timeguard period gives the rest. + usart->ttgr = opt->stopbits - USART_2_STOPBITS; + } + else + // Insert 1, 1.5 or 2 stop bits. + usart->mr |= opt->stopbits << AVR32_USART_MR_NBSTOP_OFFSET; + + // Setup complete; enable communication. + // Enable input and output. + usart->cr |= AVR32_USART_CR_TXEN_MASK | + AVR32_USART_CR_RXEN_MASK; + + return USART_SUCCESS; +} + + +int usart_init_hw_handshaking(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz) +{ + // First: Setup standard RS232. + if (usart_init_rs232(usart, opt, pba_hz) == USART_INVALID_INPUT) + return USART_INVALID_INPUT; + + // Clear previous mode. + usart->mr &= ~AVR32_USART_MR_MODE_MASK; + // Hardware handshaking. + usart->mr |= USART_MODE_HW_HSH << AVR32_USART_MR_MODE_OFFSET; + + return USART_SUCCESS; +} + + +int usart_init_IrDA(volatile avr32_usart_t *usart, const usart_options_t *opt, + long pba_hz, unsigned char irda_filter) +{ + // First: Setup standard RS232. + if (usart_init_rs232(usart, opt, pba_hz) == USART_INVALID_INPUT) + return USART_INVALID_INPUT; + + // Set IrDA counter. + usart->ifr = irda_filter; + + // Activate "low-pass filtering" of input. + usart->mr |= AVR32_USART_MR_FILTER_MASK; + + return USART_SUCCESS; +} + + +int usart_init_modem(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz) +{ + // First: Setup standard RS232. + if (usart_init_rs232(usart, opt, pba_hz) == USART_INVALID_INPUT) + return USART_INVALID_INPUT; + + // Clear previous mode. + usart->mr &= ~AVR32_USART_MR_MODE_MASK; + // Set modem mode. + usart->mr |= USART_MODE_MODEM << AVR32_USART_MR_MODE_OFFSET; + + return USART_SUCCESS; +} + + +int usart_init_rs485(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz) +{ + // First: Setup standard RS232. + if (usart_init_rs232(usart, opt, pba_hz) == USART_INVALID_INPUT) + return USART_INVALID_INPUT; + + // Clear previous mode. + usart->mr &= ~AVR32_USART_MR_MODE_MASK; + // Set RS485 mode. + usart->mr |= USART_MODE_RS485 << AVR32_USART_MR_MODE_OFFSET; + + return USART_SUCCESS; +} + + +int usart_init_iso7816(volatile avr32_usart_t *usart, const iso7816_options_t *opt, int t, long pba_hz) +{ + // Reset the USART and shutdown TX and RX. + usart_reset(usart); + + // Check input values. + if (!opt) // Null pointer. + return USART_INVALID_INPUT; + + if (t == 0) + { + // Set USART mode to ISO7816, T=0. + // The T=0 protocol always uses 2 stop bits. + usart->mr = (USART_MODE_ISO7816_T0 << AVR32_USART_MR_MODE_OFFSET) | + (AVR32_USART_MR_NBSTOP_2 << AVR32_USART_MR_NBSTOP_OFFSET) | + (opt->bit_order << AVR32_USART_MR_MSBF_OFFSET); // Allow MSBF in T=0. + } + else if (t == 1) + { + // Only LSB first in the T=1 protocol. + // max_iterations field is only used in T=0 mode. + if (opt->bit_order != 0 || + opt->max_iterations != 0) + return USART_INVALID_INPUT; + // Set USART mode to ISO7816, T=1. + // The T=1 protocol always uses 1 stop bit. + usart->mr = (USART_MODE_ISO7816_T1 << AVR32_USART_MR_MODE_OFFSET) | + (AVR32_USART_MR_NBSTOP_1 << AVR32_USART_MR_NBSTOP_OFFSET); + } + else + return USART_INVALID_INPUT; + + if (usart_set_baudrate(usart, opt->iso7816_hz, pba_hz) == USART_INVALID_INPUT) + return USART_INVALID_INPUT; + + // Set FIDI register: bit rate = selected clock/FI_DI_ratio/16. + usart->fidi = opt->fidi_ratio; + // Set ISO7816 spesific options in the MODE register. + usart->mr |= (opt->inhibit_nack << AVR32_USART_MR_INACK_OFFSET) | + (opt->dis_suc_nack << AVR32_USART_MR_DSNACK_OFFSET) | + (opt->max_iterations << AVR32_USART_MR_MAX_ITERATION_OFFSET) | + AVR32_USART_MR_CLKO_MASK; // Enable clock output. + + // Setup complete; enable input. + // Leave TX disabled for now. + usart->cr |= AVR32_USART_CR_RXEN_MASK; + + return USART_SUCCESS; +} +//! @} + + +//------------------------------------------------------------------------------ +/*! \name Transmit/Receive Functions + */ +//! @{ + + +int usart_send_address(volatile avr32_usart_t *usart, int address) +{ + // Check if USART is in multidrop / RS485 mode. + if (!usart_mode_is_multidrop(usart)) return USART_MODE_FAULT; + + // Prepare to send an address. + usart->cr |= AVR32_USART_CR_SENDA_MASK; + + // Write the address to TX. + usart_bw_write_char(usart, address); + + return USART_SUCCESS; +} + + +int usart_write_char(volatile avr32_usart_t *usart, int c) +{ + if (usart->csr & AVR32_USART_CSR_TXRDY_MASK) + { + usart->thr = c; + return USART_SUCCESS; + } + else + return USART_TX_BUSY; +} + + +int usart_putchar(volatile avr32_usart_t *usart, int c) +{ + int timeout = USART_DEFAULT_TIMEOUT; + + if (c == '\n') + { + do + { + if (!timeout--) return USART_FAILURE; + } while (usart_write_char(usart, '\r') != USART_SUCCESS); + + timeout = USART_DEFAULT_TIMEOUT; + } + + do + { + if (!timeout--) return USART_FAILURE; + } while (usart_write_char(usart, c) != USART_SUCCESS); + + return USART_SUCCESS; +} + + +int usart_read_char(volatile avr32_usart_t *usart, int *c) +{ + // Check for errors: frame, parity and overrun. In RS485 mode, a parity error + // would mean that an address char has been received. + if (usart->csr & (AVR32_USART_CSR_OVRE_MASK | + AVR32_USART_CSR_FRAME_MASK | + AVR32_USART_CSR_PARE_MASK)) + return USART_RX_ERROR; + + // No error; if we really did receive a char, read it and return SUCCESS. + if (usart->csr & AVR32_USART_CSR_RXRDY_MASK) + { + *c = (unsigned short)usart->rhr; + return USART_SUCCESS; + } + else + return USART_RX_EMPTY; +} + + +int usart_getchar(volatile avr32_usart_t *usart) +{ + int c, ret; + + while ((ret = usart_read_char(usart, &c)) == USART_RX_EMPTY); + + if (ret == USART_RX_ERROR) + return USART_FAILURE; + + return c; +} + + +void usart_write_line(volatile avr32_usart_t *usart, const char *string) +{ + while (*string != '\0') + usart_putchar(usart, *string++); +} + + +int usart_get_echo_line(volatile avr32_usart_t *usart) +{ + int rx_char; + int retval = USART_SUCCESS; + + while (1) + { + rx_char = usart_getchar(usart); + if (rx_char == USART_FAILURE) + { + usart_write_line(usart, "Error!!!\n"); + break; + } + if (rx_char == '\x03') + { + retval = USART_FAILURE; + break; + } + usart_putchar(usart, rx_char); + if (rx_char == '\r') + { + usart_putchar(usart, '\n'); + break; + } + } + + return retval; +} + + +//! @} diff --git a/20080212/Demo/AVR32_UC3/DRIVERS/USART/usart.h b/20080212/Demo/AVR32_UC3/DRIVERS/USART/usart.h new file mode 100644 index 000000000..1d731f871 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/DRIVERS/USART/usart.h @@ -0,0 +1,475 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief USART driver for AVR32 UC3. + * + * This file contains basic functions for the AVR32 USART, with support for all + * modes, settings and clock speeds. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with a USART module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef _USART_H_ +#define _USART_H_ + +#include +#include "compiler.h" + + +/*! \name Return Values + */ +//! @{ +#define USART_SUCCESS 0 //!< Successful completion. +#define USART_FAILURE -1 //!< Failure because of some unspecified reason. +#define USART_INVALID_INPUT 1 //!< Input value out of range. +#define USART_INVALID_ARGUMENT -1 //!< Argument value out of range. +#define USART_TX_BUSY 2 //!< Transmitter was busy. +#define USART_RX_EMPTY 3 //!< Nothing was received. +#define USART_RX_ERROR 4 //!< Transmission error occurred. +#define USART_MODE_FAULT 5 //!< USART not in the appropriate mode. +//! @} + +//! Default time-out value (number of attempts). +#define USART_DEFAULT_TIMEOUT 10000 + +/*! \name Parity Settings + */ +//! @{ +#define USART_EVEN_PARITY AVR32_USART_MR_PAR_EVEN //!< Use even parity on character transmission. +#define USART_ODD_PARITY AVR32_USART_MR_PAR_ODD //!< Use odd parity on character transmission. +#define USART_SPACE_PARITY AVR32_USART_MR_PAR_SPACE //!< Use a space as parity bit. +#define USART_MARK_PARITY AVR32_USART_MR_PAR_MARK //!< Use a mark as parity bit. +#define USART_NO_PARITY AVR32_USART_MR_PAR_NONE //!< Don't use a parity bit. +#define USART_MULTIDROP_PARITY AVR32_USART_MR_PAR_MULTI //!< Parity bit is used to flag address characters. +//! @} + +/*! \name Operating Modes + */ +//! @{ +#define USART_MODE_NORMAL AVR32_USART_MR_MODE_NORMAL //!< Normal RS232 mode. +#define USART_MODE_RS485 AVR32_USART_MR_MODE_RS485 //!< RS485 mode. +#define USART_MODE_HW_HSH AVR32_USART_MR_MODE_HARDWARE //!< RS232 mode with hardware handshaking. +#define USART_MODE_MODEM AVR32_USART_MR_MODE_MODEM //!< Modem mode. +#define USART_MODE_ISO7816_T0 AVR32_USART_MR_MODE_ISO7816_T0 //!< ISO7816, T = 0 mode. +#define USART_MODE_ISO7816_T1 AVR32_USART_MR_MODE_ISO7816_T1 //!< ISO7816, T = 1 mode. +#define USART_MODE_IRDA AVR32_USART_MR_MODE_IRDA //!< IrDA mode. +#define USART_MODE_SW_HSH AVR32_USART_MR_MODE_SOFTWARE //!< RS232 mode with software handshaking. +//! @} + + +/*! \name Channel Modes + */ +//! @{ +#define USART_NORMAL_CHMODE AVR32_USART_MR_CHMODE_NORMAL //!< Normal communication. +#define USART_AUTO_ECHO AVR32_USART_MR_CHMODE_ECHO //!< Echo data. +#define USART_LOCAL_LOOPBACK AVR32_USART_MR_CHMODE_LOCAL_LOOP //!< Local loopback. +#define USART_REMOTE_LOOPBACK AVR32_USART_MR_CHMODE_REMOTE_LOOP //!< Remote loopback. +//! @} + +/*! \name Stop Bits Settings + */ +//! @{ +#define USART_1_STOPBIT AVR32_USART_MR_NBSTOP_1 //!< Use 1 stop bit. +#define USART_1_5_STOPBITS AVR32_USART_MR_NBSTOP_1_5 //!< Use 1.5 stop bits. +#define USART_2_STOPBITS AVR32_USART_MR_NBSTOP_2 //!< Use 2 stop bits (for more, just give the number of bits). +//! @} + + +//! Input parameters when initializing RS232 and similar modes. +typedef struct +{ + //! Set baudrate of the USART. + unsigned long baudrate; + + //! Number of bits to transmit as a character (5 to 9). + unsigned char charlength; + + //! How to calculate the parity bit: \ref USART_EVEN_PARITY, \ref USART_ODD_PARITY, + //! \ref USART_SPACE_PARITY, \ref USART_MARK_PARITY, \ref USART_NO_PARITY or + //! \ref USART_MULTIDROP_PARITY. + unsigned char paritytype; + + //! Number of stop bits between two characters: \ref USART_1_STOPBIT, + //! \ref USART_1_5_STOPBITS, \ref USART_2_STOPBITS or any number from 3 to 257 + //! which will result in a time guard period of that length between characters. + unsigned short stopbits; + + //! Run the channel in testmode: \ref USART_NORMAL_CHMODE, \ref USART_AUTO_ECHO, + //! \ref USART_LOCAL_LOOPBACK or \ref USART_REMOTE_LOOPBACK. + unsigned char channelmode; +} usart_options_t; + +//! Input parameters when initializing ISO7816 modes. +typedef struct +{ + //! Set the frequency of the ISO7816 clock. + unsigned long iso7816_hz; + + //! The number of ISO7816 clock ticks in every bit period (1 to 2047, 0 = disable clock). + //! Bit rate = \ref iso7816_hz / \ref fidi_ratio. + unsigned short fidi_ratio; + + //! Inhibit Non Acknowledge:\n + //! - 0: the NACK is generated;\n + //! - 1: the NACK is not generated. + //! + //! \note This bit will be used only in ISO7816 mode, protocol T = 0 receiver. + int inhibit_nack; + + //! Disable successive NACKs. + //! Successive parity errors are counted up to the value in the \ref max_iterations field. + //! These parity errors generate a NACK on the ISO line. As soon as this value is reached, + //! no addititional NACK is sent on the ISO line. The ITERATION flag is asserted. + int dis_suc_nack; + + //! Max number of repetitions (0 to 7). + unsigned char max_iterations; + + //! Bit order in transmitted characters:\n + //! - 0: LSB first;\n + //! - 1: MSB first. + int bit_order; +} iso7816_options_t; + +//! Input parameters when initializing ISO7816 modes. +typedef struct +{ + //! Set the frequency of the SPI clock. + unsigned long baudrate; + + //! Number of bits to transmit as a character (5 to 9). + unsigned char charlength; + + //! Run the channel in testmode: \ref USART_NORMAL_CHMODE, \ref USART_AUTO_ECHO, + //! \ref USART_LOCAL_LOOPBACK or \ref USART_REMOTE_LOOPBACK. + unsigned char channelmode; + + //! Which SPI mode to use when transmitting. + unsigned char spimode; +} usart_spi_options_t; + + + + + +//------------------------------------------------------------------------------ +/*! \name Initialization Functions + */ +//! @{ + +/*! \brief Resets the USART and disables TX and RX. + * + * \param usart Base address of the USART instance. + */ +extern void usart_reset(volatile avr32_usart_t *usart); + +/*! \brief Sets up the USART to use the standard RS232 protocol. + * + * \param usart Base address of the USART instance. + * \param opt Options needed to set up RS232 communication (see \ref usart_options_t). + * \param pba_hz USART module input clock frequency (PBA clock, Hz). + * + * \retval USART_SUCCESS Mode successfully initialized. + * \retval USART_INVALID_INPUT One or more of the arguments is out of valid range. + */ +extern int usart_init_rs232(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz); + +/*! \brief Sets up the USART to use hardware handshaking. + * + * \param usart Base address of the USART instance. + * \param opt Options needed to set up RS232 communication (see \ref usart_options_t). + * \param pba_hz USART module input clock frequency (PBA clock, Hz). + * + * \retval USART_SUCCESS Mode successfully initialized. + * \retval USART_INVALID_INPUT One or more of the arguments is out of valid range. + * + * \note \ref usart_init_rs232 does not need to be invoked before this function. + */ +extern int usart_init_hw_handshaking(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz); + +/*! \brief Sets up the USART to use the IrDA protocol. + * + * \param usart Base address of the USART instance. + * \param opt Options needed to set up RS232 communication (see \ref usart_options_t). + * \param pba_hz USART module input clock frequency (PBA clock, Hz). + * \param irda_filter Counter used to distinguish received ones from zeros. + * + * \retval USART_SUCCESS Mode successfully initialized. + * \retval USART_INVALID_INPUT One or more of the arguments is out of valid range. + */ +extern int usart_init_IrDA(volatile avr32_usart_t *usart, const usart_options_t *opt, + long pba_hz, unsigned char irda_filter); + +/*! \brief Sets up the USART to use the modem protocol, activating dedicated inputs/outputs. + * + * \param usart Base address of the USART instance. + * \param opt Options needed to set up RS232 communication (see \ref usart_options_t). + * \param pba_hz USART module input clock frequency (PBA clock, Hz). + * + * \retval USART_SUCCESS Mode successfully initialized. + * \retval USART_INVALID_INPUT One or more of the arguments is out of valid range. + */ +extern int usart_init_modem(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz); + +/*! \brief Sets up the USART to use the RS485 protocol. + * + * \param usart Base address of the USART instance. + * \param opt Options needed to set up RS232 communication (see \ref usart_options_t). + * \param pba_hz USART module input clock frequency (PBA clock, Hz). + * + * \retval USART_SUCCESS Mode successfully initialized. + * \retval USART_INVALID_INPUT One or more of the arguments is out of valid range. + */ +extern int usart_init_rs485(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz); + +/*! \brief Sets up the USART to use the ISO7816 T=0 or T=1 smartcard protocols. + * + * \param usart Base address of the USART instance. + * \param opt Options needed to set up ISO7816 communication (see \ref iso7816_options_t). + * \param t ISO7816 mode to use (T=0 or T=1). + * \param pba_hz USART module input clock frequency (PBA clock, Hz). + * + * \retval USART_SUCCESS Mode successfully initialized. + * \retval USART_INVALID_INPUT One or more of the arguments is out of valid range. + */ +extern int usart_init_iso7816(volatile avr32_usart_t *usart, const iso7816_options_t *opt, int t, long pba_hz); + +/*! \brief Sets up the USART to use the SPI mode as master. + * + * \param usart Base address of the USART instance. + * \param opt Options needed to set up SPI mode (see \ref usart_spi_options_t). + * \param pba_hz USART module input clock frequency (PBA clock, Hz). + * + * \retval USART_SUCCESS Mode successfully initialized. + * \retval USART_INVALID_INPUT One or more of the arguments is out of valid range. + */ +extern int usart_init_spi_master(volatile avr32_usart_t *usart, const usart_spi_options_t *opt, long pba_hz); + + +/*! \brief Sets up the USART to use the SPI mode as slave. + * + * \param usart Base address of the USART instance. + * \param opt Options needed to set up SPI mode (see \ref usart_spi_options_t). + * \param pba_hz USART module input clock frequency (PBA clock, Hz). + * + * \retval USART_SUCCESS Mode successfully initialized. + * \retval USART_INVALID_INPUT One or more of the arguments is out of valid range. + */ +extern int usart_init_spi_slave(volatile avr32_usart_t *usart, const usart_spi_options_t *opt, long pba_hz); + +//! @} + +//------------------------------------------------------------------------------ +/*! \brief Selects slave chip. + * + * \param usart Base address of the USART instance. + * + * \return Status. + * \retval USART_SUCCESS Success. + */ +extern int usart_spi_selectChip(volatile avr32_usart_t *usart); + +/*! \brief Unselects slave chip. + * + * \param usart Base address of the USART instance. + * + * \return Status. + * \retval USART_SUCCESS Success. + * \retval USART_FAILURE Time out. + */ +extern int usart_spi_unselectChip(volatile avr32_usart_t *usart); + +//------------------------------------------------------------------------------ +/*! \name Read and Reset Error Status Bits + */ +//! @{ + +/*! \brief Resets the error status. + * + * This function resets the status bits indicating that a parity error, + * framing error or overrun has occurred. The RXBRK bit, indicating + * a start/end of break condition on the RX line, is also reset. + * + * \param usart Base address of the USART instance. + */ +#if __GNUC__ +__attribute__((__always_inline__)) +#endif +extern __inline__ void usart_reset_status(volatile avr32_usart_t *usart) +{ + usart->cr |= AVR32_USART_CR_RSTSTA_MASK; +} + +/*! \brief Checks if a parity error has occurred since last status reset. + * + * \param usart Base address of the USART instance. + * + * \return \c 1 if a parity error has been detected, otherwise \c 0. + */ +#if __GNUC__ +__attribute__((__always_inline__)) +#endif +extern __inline__ int usart_parity_error(volatile avr32_usart_t *usart) +{ + return (usart->csr & AVR32_USART_CSR_PARE_MASK) != 0; +} + +/*! \brief Checks if a framing error has occurred since last status reset. + * + * \param usart Base address of the USART instance. + * + * \return \c 1 if a framing error has been detected, otherwise \c 0. + */ +#if __GNUC__ +__attribute__((__always_inline__)) +#endif +extern __inline__ int usart_framing_error(volatile avr32_usart_t *usart) +{ + return (usart->csr & AVR32_USART_CSR_FRAME_MASK) != 0; +} + +/*! \brief Checks if an overrun error has occurred since last status reset. + * + * \param usart Base address of the USART instance. + * + * \return \c 1 if a overrun error has been detected, otherwise \c 0. + */ +#if __GNUC__ +__attribute__((__always_inline__)) +#endif +extern __inline__ int usart_overrun_error(volatile avr32_usart_t *usart) +{ + return (usart->csr & AVR32_USART_CSR_OVRE_MASK) != 0; +} + +//! @} + + +//------------------------------------------------------------------------------ +/*! \name Transmit/Receive Functions + */ +//! @{ + +/*! \brief Addresses a receiver. + * + * While in RS485 mode, receivers only accept data addressed to them. + * A packet/char with the address tag set has to precede any data. + * This function is used to address a receiver. This receiver should read + * all the following data, until an address packet addresses another receiver. + * + * \param usart Base address of the USART instance. + * \param address Address of the target device. + * + * \retval USART_SUCCESS Address successfully sent (if current mode is RS485). + * \retval USART_MODE_FAULT Wrong operating mode. + */ +extern int usart_send_address(volatile avr32_usart_t *usart, int address); + +/*! \brief Writes the given character to the TX buffer if the transmitter is ready. + * + * \param usart Base address of the USART instance. + * \param c The character (up to 9 bits) to transmit. + * + * \retval USART_SUCCESS The transmitter was ready. + * \retval USART_TX_BUSY The transmitter was busy. + */ +extern int usart_write_char(volatile avr32_usart_t *usart, int c); + +/*! \brief An active wait writing a character to the USART. + * + * \param usart Base address of the USART instance. + * \param c The character (up to 9 bits) to transmit. + */ +#if __GNUC__ +__attribute__((__always_inline__)) +#endif +extern __inline__ void usart_bw_write_char(volatile avr32_usart_t *usart, int c) +{ + while (usart_write_char(usart, c) != USART_SUCCESS); +} + +/*! \brief Sends a character with the USART. + * + * \param usart Base address of the USART instance. + * \param c Character to write. + * + * \retval USART_SUCCESS The character was written. + * \retval USART_FAILURE The function timed out before the USART transmitter became ready to send. + */ +extern int usart_putchar(volatile avr32_usart_t *usart, int c); + +/*! \brief Checks the RX buffer for a received character, and stores it at the + * given memory location. + * + * \param usart Base address of the USART instance. + * \param c Pointer to the where the read character should be stored + * (must be at least short in order to accept 9-bit characters). + * + * \retval USART_SUCCESS The character was read successfully. + * \retval USART_RX_EMPTY The RX buffer was empty. + * \retval USART_RX_ERROR An error was deteceted. + */ +extern int usart_read_char(volatile avr32_usart_t *usart, int *c); + +/*! \brief Waits until a character is received, and returns it. + * + * \param usart Base address of the USART instance. + * + * \return The received character, or \ref USART_FAILURE upon error. + */ +extern int usart_getchar(volatile avr32_usart_t *usart); + +/*! \brief Writes one character string to the USART. + * + * \param usart Base address of the USART instance. + * \param string String to be written. + */ +extern void usart_write_line(volatile avr32_usart_t *usart, const char *string); + +/*! \brief Gets and echoes characters until end of line. + * + * \param usart Base address of the USART instance. + * + * \retval USART_SUCCESS Success. + * \retval USART_FAILURE ETX character received. + */ +extern int usart_get_echo_line(volatile avr32_usart_t *usart); + +//! @} + + +#endif // _USART_H_ diff --git a/20080212/Demo/AVR32_UC3/FreeRTOSConfig.h b/20080212/Demo/AVR32_UC3/FreeRTOSConfig.h new file mode 100644 index 000000000..723ffb952 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/FreeRTOSConfig.h @@ -0,0 +1,137 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief FreeRTOS demonstration for AVR32 UC3. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include "board.h" + + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( FOSC0 ) /* Hz clk gen */ +#define configPBA_CLOCK_HZ ( FOSC0 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 8 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 128 ) +/* configTOTAL_HEAP_SIZE is not used when heap_3.c is used. */ +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1024*25 ) ) +#define configMAX_TASK_NAME_LEN ( 16 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 0 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 0 +#define INCLUDE_xTaskGetSchedulerState 1 + +/* configTICK_USE_TC is a boolean indicating whether to use a Timer Counter + for the tick generation. Timer Counter will generate an accurate Tick; + otherwise the CPU will generate a tick but with time drift. + configTICK_TC_CHANNEL is the TC channel. */ +#define configTICK_USE_TC 1 +#define configTICK_TC_CHANNEL 2 + +/* configHEAP_INIT is a boolean indicating whether to initialize the heap with + 0xA5 in order to be able to determine the maximal heap consumption. */ +#define configHEAP_INIT 0 + +/* Debug trace configuration. + configDBG is a boolean indicating whether to activate the debug trace. */ +#if BOARD == EVK1100 +#define configDBG 1 +#define configDBG_USART (&AVR32_USART1) +#define configDBG_USART_RX_PIN AVR32_USART1_RXD_0_PIN +#define configDBG_USART_RX_FUNCTION AVR32_USART1_RXD_0_FUNCTION +#define configDBG_USART_TX_PIN AVR32_USART1_TXD_0_PIN +#define configDBG_USART_TX_FUNCTION AVR32_USART1_TXD_0_FUNCTION +#define configDBG_USART_BAUDRATE 57600 +#define serialPORT_USART (&AVR32_USART0) +#define serialPORT_USART_RX_PIN AVR32_USART0_RXD_0_PIN +#define serialPORT_USART_RX_FUNCTION AVR32_USART0_RXD_0_FUNCTION +#define serialPORT_USART_TX_PIN AVR32_USART0_TXD_0_PIN +#define serialPORT_USART_TX_FUNCTION AVR32_USART0_TXD_0_FUNCTION +#define serialPORT_USART_IRQ AVR32_USART0_IRQ +#define serialPORT_USART_BAUDRATE 57600 +#elif BOARD == EVK1101 +#define configDBG 1 +#define configDBG_USART (&AVR32_USART1) +#define configDBG_USART_RX_PIN AVR32_USART1_RXD_0_0_PIN +#define configDBG_USART_RX_FUNCTION AVR32_USART1_RXD_0_0_FUNCTION +#define configDBG_USART_TX_PIN AVR32_USART1_TXD_0_0_PIN +#define configDBG_USART_TX_FUNCTION AVR32_USART1_TXD_0_0_FUNCTION +#define configDBG_USART_BAUDRATE 57600 +#define serialPORT_USART (&AVR32_USART1) +#define serialPORT_USART_RX_PIN AVR32_USART1_RXD_0_0_PIN +#define serialPORT_USART_RX_FUNCTION AVR32_USART1_RXD_0_0_FUNCTION +#define serialPORT_USART_TX_PIN AVR32_USART1_TXD_0_0_PIN +#define serialPORT_USART_TX_FUNCTION AVR32_USART1_TXD_0_0_FUNCTION +#define serialPORT_USART_IRQ AVR32_USART1_IRQ +#define serialPORT_USART_BAUDRATE 57600 +#endif + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/AVR32_UC3/ParTest/ParTest.c b/20080212/Demo/AVR32_UC3/ParTest/ParTest.c new file mode 100644 index 000000000..fd91e87eb --- /dev/null +++ b/20080212/Demo/AVR32_UC3/ParTest/ParTest.c @@ -0,0 +1,117 @@ +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief FreeRTOS LEDs Management for AVR32 UC3. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + *****************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + + +#include +#include "FreeRTOS.h" +#include "task.h" +#include "partest.h" + + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +#define partstALL_OUTPUTS_OFF ( ( unsigned portCHAR ) 0x00 ) +#if( BOARD==EVK1100 ) +# define partstMAX_OUTPUT_LED ( ( unsigned portCHAR ) 8 ) + +#elif( BOARD==EVK1101 ) +# define partstMAX_OUTPUT_LED ( ( unsigned portCHAR ) 4 ) +#endif + +static volatile unsigned portCHAR ucCurrentOutputValue = partstALL_OUTPUTS_OFF; /*lint !e956 File scope parameters okay here. */ + +/*-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ + LED_Display( partstALL_OUTPUTS_OFF ); /* Start with all LEDs off. */ +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ +unsigned portCHAR ucBit; + + if( uxLED >= partstMAX_OUTPUT_LED ) + { + return; + } + + ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED; + + vTaskSuspendAll(); + { + if( xValue == pdTRUE ) + { + ucCurrentOutputValue |= ucBit; + } + else + { + ucCurrentOutputValue &= ~ucBit; + } + + LED_Display(ucCurrentOutputValue); + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned portCHAR ucBit; + + if( uxLED >= partstMAX_OUTPUT_LED ) + { + return; + } + + ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED; + + vTaskSuspendAll(); + { + ucCurrentOutputValue ^= ucBit; + LED_Display(ucCurrentOutputValue); + } + xTaskResumeAll(); +} diff --git a/20080212/Demo/AVR32_UC3/SERVICES/USB/CLASS/DFU/EXAMPLES/ISP/BOOT/trampoline.S b/20080212/Demo/AVR32_UC3/SERVICES/USB/CLASS/DFU/EXAMPLES/ISP/BOOT/trampoline.S new file mode 100644 index 000000000..8c4651659 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/SERVICES/USB/CLASS/DFU/EXAMPLES/ISP/BOOT/trampoline.S @@ -0,0 +1,72 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief AVR32 UC3 ISP trampoline. + * + * In order to be able to program a project with both BatchISP and JTAGICE mkII + * without having to take the general-purpose fuses into consideration, add this + * file to the project and change the program entry point to _trampoline. + * + * The pre-programmed ISP will be erased if JTAGICE mkII is used. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: All AVR32UC devices can be used. + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include "../conf_isp.h" + + +//! @{ +//! \verbatim + + + // This must be linked @ 0x80000000 if it is to be run upon reset. + .section .reset, "ax", @progbits + + + .global _trampoline + .type _trampoline, @function +_trampoline: + // Jump to program start. + rjmp program_start + + .org PROGRAM_START_OFFSET +program_start: + // Jump to the C runtime startup routine. + lda.w pc, _stext + + +//! \endverbatim +//! @} diff --git a/20080212/Demo/AVR32_UC3/SERVICES/USB/CLASS/DFU/EXAMPLES/ISP/BOOT/trampoline.s82 b/20080212/Demo/AVR32_UC3/SERVICES/USB/CLASS/DFU/EXAMPLES/ISP/BOOT/trampoline.s82 new file mode 100644 index 000000000..b9e03b143 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/SERVICES/USB/CLASS/DFU/EXAMPLES/ISP/BOOT/trampoline.s82 @@ -0,0 +1,91 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief AVR32 UC3 ISP trampoline. + * + * In order to be able to program a project with both BatchISP and JTAGICE mkII + * without having to take the general-purpose fuses into consideration, add this + * file to the project and change the program entry point to __trampoline. + * + * The pre-programmed ISP will be erased if JTAGICE mkII is used. + * + * - Compiler: IAR EWAVR32 + * - Supported devices: All AVR32UC devices can be used. + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include "../conf_isp.h" + + +//! @{ +//! \verbatim + + + RSEG SSTACK:DATA:NOROOT(2) + + + // This must be linked @ 0x80000000 if it is to be run upon reset. + RSEG RESET:CODE:NOROOT(1) + + + PUBLIC __trampoline +__trampoline: + // Jump to program start. + rjmp program_start + + ORG PROGRAM_START_OFFSET +program_start: + // Initialize the stack pointer. + lddpc sp, ??SPS + // Jump to the C runtime startup routine. + lddpc pc, ??cmain + + +// Constant data area. + + ALIGN 2 + +??SPS: + DC32 SFE(SSTACK) & ~3 + + EXTERN ?main +??cmain: + DC32 ?main + + + END + + +//! \endverbatim +//! @} diff --git a/20080212/Demo/AVR32_UC3/SERVICES/USB/CLASS/DFU/EXAMPLES/ISP/conf_isp.h b/20080212/Demo/AVR32_UC3/SERVICES/USB/CLASS/DFU/EXAMPLES/ISP/conf_isp.h new file mode 100644 index 000000000..05fd4dcf7 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/SERVICES/USB/CLASS/DFU/EXAMPLES/ISP/conf_isp.h @@ -0,0 +1,119 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ****************************************************************** + * + * \brief ISP configuration file. + * + * This file contains the possible external configuration of the ISP. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with a USB module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ***************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef _CONF_ISP_H_ +#define _CONF_ISP_H_ + +#include +#include "compiler.h" + + +//_____ D E F I N I T I O N S ______________________________________________ + +#define PRODUCT_MANUFACTURER_ID 0x58 +#define PRODUCT_FAMILY_ID 0x20 + +#define ISP_VERSION 0x00 +#define ISP_ID0 0x00 +#define ISP_ID1 0x00 + +#define ISP_GPFB_FORCE 31 +#define ISP_GPFB_FORCE_MASK 0x80000000 +#define ISP_GPFB_FORCE_OFFSET 31 +#define ISP_GPFB_FORCE_SIZE 1 + +#define ISP_GPFB_IO_COND_EN 30 +#define ISP_GPFB_IO_COND_EN_MASK 0x40000000 +#define ISP_GPFB_IO_COND_EN_OFFSET 30 +#define ISP_GPFB_IO_COND_EN_SIZE 1 + +#define ISP_GPFB_BOD_EN 29 +#define ISP_GPFB_BOD_EN_MASK 0x20000000 +#define ISP_GPFB_BOD_EN_OFFSET 29 +#define ISP_GPFB_BOD_EN_SIZE 1 + +#define ISP_CFG (*(volatile U32 *)ISP_CFG_ADDRESS) +#define ISP_CFG_ADDRESS (AVR32_FLASHC_USER_PAGE_ADDRESS + ISP_CFG_OFFSET) +#define ISP_CFG_OFFSET 0x000001FC +#define ISP_CFG_SIZE 4 + +#define ISP_CFG_BOOT_KEY 17 +#define ISP_CFG_BOOT_KEY_MASK 0xFFFE0000 +#define ISP_CFG_BOOT_KEY_OFFSET 17 +#define ISP_CFG_BOOT_KEY_SIZE 15 +#define ISP_CFG_BOOT_KEY_VALUE 0x494F + +#define ISP_CFG_IO_COND_LEVEL 16 +#define ISP_CFG_IO_COND_LEVEL_MASK 0x00010000 +#define ISP_CFG_IO_COND_LEVEL_OFFSET 16 +#define ISP_CFG_IO_COND_LEVEL_SIZE 1 + +#define ISP_CFG_IO_COND_PIN 8 +#define ISP_CFG_IO_COND_PIN_MASK 0x0000FF00 +#define ISP_CFG_IO_COND_PIN_OFFSET 8 +#define ISP_CFG_IO_COND_PIN_SIZE 8 + +#define ISP_CFG_CRC8 0 +#define ISP_CFG_CRC8_MASK 0x000000FF +#define ISP_CFG_CRC8_OFFSET 0 +#define ISP_CFG_CRC8_SIZE 8 +#define ISP_CFG_CRC8_POLYNOMIAL 0x107 + +#define ISP_KEY (*(volatile U32 *)ISP_KEY_ADDRESS) +#define ISP_KEY_ADDRESS (AVR32_SRAM_ADDRESS + ISP_KEY_OFFSET) +#define ISP_KEY_OFFSET 0x00000000 +#define ISP_KEY_SIZE 4 +#define ISP_KEY_VALUE ('I' << 24 | 'S' << 16 | 'P' << 8 | 'K') + +#ifndef ISP_OSC + #define ISP_OSC 0 +#endif + +#define DFU_FRAME_LENGTH 2048 + +#define PROGRAM_START_ADDRESS (AVR32_FLASH_ADDRESS + PROGRAM_START_OFFSET) +#define PROGRAM_START_OFFSET 0x00002000 + + +#endif // _CONF_ISP_H_ diff --git a/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/0128/GCC/link_uc3a0128.lds b/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/0128/GCC/link_uc3a0128.lds new file mode 100644 index 000000000..29c4eb51d --- /dev/null +++ b/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/0128/GCC/link_uc3a0128.lds @@ -0,0 +1,263 @@ +/****************************************************************************** + * AVR32 AT32UC3A0128 GNU LD script file. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: AVR32 AT32UC3A0128 + * + * - author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32") + +OUTPUT_ARCH(avr32:uc) + +ENTRY(_start) + +MEMORY +{ + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00020000 + INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x00007FFC + USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200 + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 0x00000200 +} + +PHDRS +{ + FLASH PT_LOAD; + INTRAM PT_NULL; + USERPAGE PT_LOAD; + FACTORYPAGE PT_LOAD; +} + +SECTIONS +{ + /* If this heap size is selected, all the INTRAM space from the end of the + data area to the beginning of the stack will be allocated for the heap. */ + __max_heap_size__ = -1; + + /* Use a default heap size if heap size was not defined. */ + __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__; + + /* Use a default stack size if stack size was not defined. */ + __stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 4K; + + /* Read-only sections, merged into text segment: */ + PROVIDE (__executable_start = 0x80000000); . = 0x80000000; + .interp : { *(.interp) } >FLASH AT>FLASH :FLASH + .reset : { *(.reset) } >FLASH AT>FLASH :FLASH + .hash : { *(.hash) } >FLASH AT>FLASH :FLASH + .dynsym : { *(.dynsym) } >FLASH AT>FLASH :FLASH + .dynstr : { *(.dynstr) } >FLASH AT>FLASH :FLASH + .gnu.version : { *(.gnu.version) } >FLASH AT>FLASH :FLASH + .gnu.version_d : { *(.gnu.version_d) } >FLASH AT>FLASH :FLASH + .gnu.version_r : { *(.gnu.version_r) } >FLASH AT>FLASH :FLASH + .rel.init : { *(.rel.init) } >FLASH AT>FLASH :FLASH + .rela.init : { *(.rela.init) } >FLASH AT>FLASH :FLASH + .rel.text : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH + .rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH + .rel.fini : { *(.rel.fini) } >FLASH AT>FLASH :FLASH + .rela.fini : { *(.rela.fini) } >FLASH AT>FLASH :FLASH + .rel.rodata : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rela.rodata : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rel.data.rel.ro : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH + .rela.data.rel.ro : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH + .rel.data : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH + .rela.data : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH + .rel.tdata : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH + .rela.tdata : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH + .rel.tbss : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH + .rela.tbss : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH + .rel.ctors : { *(.rel.ctors) } >FLASH AT>FLASH :FLASH + .rela.ctors : { *(.rela.ctors) } >FLASH AT>FLASH :FLASH + .rel.dtors : { *(.rel.dtors) } >FLASH AT>FLASH :FLASH + .rela.dtors : { *(.rela.dtors) } >FLASH AT>FLASH :FLASH + .rel.got : { *(.rel.got) } >FLASH AT>FLASH :FLASH + .rela.got : { *(.rela.got) } >FLASH AT>FLASH :FLASH + .rel.bss : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH + .rela.bss : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH + .rel.plt : { *(.rel.plt) } >FLASH AT>FLASH :FLASH + .rela.plt : { *(.rela.plt) } >FLASH AT>FLASH :FLASH + .init : + { + KEEP (*(.init)) + } >FLASH AT>FLASH :FLASH =0xd703d703 + .plt : { *(.plt) } >FLASH AT>FLASH :FLASH + .text : + { + *(.text .stub .text.* .gnu.linkonce.t.*) + KEEP (*(.text.*personality*)) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + } >FLASH AT>FLASH :FLASH =0xd703d703 + .fini : + { + KEEP (*(.fini)) + } >FLASH AT>FLASH :FLASH =0xd703d703 + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + .rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rodata1 : { *(.rodata1) } >FLASH AT>FLASH :FLASH + .eh_frame_hdr : { *(.eh_frame_hdr) } >FLASH AT>FLASH :FLASH + .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH :FLASH + .gcc_except_table : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH :FLASH + .lalign : { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH :FLASH + . = ORIGIN(INTRAM); + .dalign : { . = ALIGN(8); PROVIDE(_data = .); } >INTRAM AT>INTRAM :INTRAM + /* Exception handling */ + .eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) } >INTRAM AT>FLASH :FLASH + .gcc_except_table : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >INTRAM AT>FLASH :FLASH + /* Thread Local Storage sections */ + .tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >INTRAM AT>FLASH :FLASH + .tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >INTRAM AT>FLASH :FLASH + /* Ensure the __preinit_array_start label is properly aligned. We + could instead move the label definition inside the section, but + the linker would then create the section even if it turns out to + be empty, which isn't pretty. */ + PROVIDE (__preinit_array_start = ALIGN(32 / 8)); + .preinit_array : { KEEP (*(.preinit_array)) } >INTRAM AT>FLASH :FLASH + PROVIDE (__preinit_array_end = .); + PROVIDE (__init_array_start = .); + .init_array : { KEEP (*(.init_array)) } >INTRAM AT>FLASH :FLASH + PROVIDE (__init_array_end = .); + PROVIDE (__fini_array_start = .); + .fini_array : { KEEP (*(.fini_array)) } >INTRAM AT>FLASH :FLASH + PROVIDE (__fini_array_end = .); + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin*.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >INTRAM AT>FLASH :FLASH + .dtors : + { + KEEP (*crtbegin*.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >INTRAM AT>FLASH :FLASH + .jcr : { KEEP (*(.jcr)) } >INTRAM AT>FLASH :FLASH + .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >INTRAM AT>FLASH :FLASH + .dynamic : { *(.dynamic) } >INTRAM AT>FLASH :FLASH + .got : { *(.got.plt) *(.got) } >INTRAM AT>FLASH :FLASH + .data : + { + *(.data .data.* .gnu.linkonce.d.*) + KEEP (*(.gnu.linkonce.d.*personality*)) + SORT(CONSTRUCTORS) + } >INTRAM AT>FLASH :FLASH + .data1 : { *(.data1) } >INTRAM AT>FLASH :FLASH + .balign : { . = ALIGN(8); _edata = .; } >INTRAM AT>FLASH :FLASH + _edata = .; + PROVIDE (edata = .); + __bss_start = .; + .bss : + { + *(.dynbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + /* Align here to ensure that the .bss section occupies space up to + _end. Align after .bss to ensure correct alignment even if the + .bss section disappears because there are no input sections. */ + . = ALIGN(8); + } >INTRAM AT>INTRAM :INTRAM + . = ALIGN(8); + _end = .; + PROVIDE (end = .); + __heap_start__ = ALIGN(8); + .heap : + { + *(.heap) + . = (__heap_size__ == __max_heap_size__) ? + ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ - ABSOLUTE(.) : + __heap_size__; + } >INTRAM AT>INTRAM :INTRAM + __heap_end__ = .; + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + .stack ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ : + { + _stack = .; + *(.stack) + . = __stack_size__; + _estack = .; + } >INTRAM AT>INTRAM :INTRAM + .userpage : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE :USERPAGE + .factorypage : { *(.factorypage .factorypage.*) } >FACTORYPAGE AT>FACTORYPAGE :FACTORYPAGE + /DISCARD/ : { *(.note.GNU-stack) } +} diff --git a/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/0128/IAR/lnkuc3a0128.xcl b/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/0128/IAR/lnkuc3a0128.xcl new file mode 100644 index 000000000..3f42ec322 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/0128/IAR/lnkuc3a0128.xcl @@ -0,0 +1,138 @@ +/****************************************************************************** + * AVR32 AT32UC3A0128 XLINK command file for AVR32 IAR C/C++ Compiler. + * + * The assumed memory layout is the one of the AT32UC3A0128: + * + * Start Stop Name Type + * ---------- ---------- ----- -------------- + * 0x00000000 0x00007FFF SRAM RAM + * 0x80000000 0x8001FFFF FLASH FLASH + * + * Usage: xlink your_file(s) -f xcl-file libraries + * + * - Compiler: IAR EWAVR32 + * - Supported devices: AVR32 AT32UC3A0128 + * + * - author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +/************************************************************************/ +/* The following segments are defined in this link file: */ +/* */ +/* Code segments */ +/* CODE32 -- Program code used by __code32 functions. */ +/* RESET -- Reset code. */ +/* EVSEG -- Exception vector handlers. */ +/* */ +/* Constant segments */ +/* INITTAB -- Segment initializer table. */ +/* DIFUNCT -- Dynamic initialization vector used by C++. */ +/* SWITCH -- Switch tables. */ +/* ACTAB -- Table of pointers to acall functions. */ +/* */ +/* DATA21_ID -- Initialization data for DATA21_I. */ +/* DATA32_ID -- Initialization data for DATA32_I. */ +/* DATA32_C -- Constant __data32 data. */ +/* */ +/* CHECKSUM -- Checksum segment. */ +/* */ +/* Data segments */ +/* DATA21_I -- Initialized __data21 data with non-zero */ +/* initial value. */ +/* DATA32_I -- Initialized __data32 data with non-zero */ +/* initial value. */ +/* DATA21_Z -- Initialized __data21 data with zero initial value. */ +/* DATA32_Z -- Initialized __data32 data with zero initial value. */ +/* DATA21_N -- Non-initialized __data21. */ +/* DATA32_N -- Non-initialized __data32. */ +/* SSTACK -- The system stack. */ +/* CSTACK -- The application stack. */ +/* HEAP -- The heap used by malloc and free. */ +/* */ +/************************************************************************/ + +/************************************************************************/ +/* Define CPU */ +/************************************************************************/ + +-cavr32 + +// Declare the IPR0 memory location +-DIPR0=FFFF0800 + +/************************************************************************/ +/* Reset code is located at address 0x80000000 and up. */ +/************************************************************************/ + +-Z(CODE)RESET=80000000-8001FFFF + +/************************************************************************/ +/* The exception handler code is located at address 0x80000000 */ +/* and up. Make sure that the exception table gets properly */ +/* allocated. By using the special -Z@ allocation primitive, the */ +/* placement is guaranteed to be at _EVBASE and onwards. */ +/************************************************************************/ + +-Z@(CODE)EVTAB=80004000-8001FFFF +-Z@(CODE)EV100=80004100-8001FFFF +-P(CODE)EVSEG=80004000-8001FFFF + +/************************************************************************/ +/* Allocate code and const segments. */ +/************************************************************************/ + +-P(CODE)CODE32=80000000-8001FFFF +-P(CONST)DATA32_C=80000000-8001FFFF + +// Initializers +-Z(CONST)INITTAB,DIFUNCT=80000000-8001FFFF +-Z(CONST)CHECKSUM,SWITCH=80000000-8001FFFF +-Z(CONST)DATA21_ID,DATA32_ID=80000000-8001FFFF + +-Z(CONST)ACTAB,HTAB=80000000-8001FFFF + +/************************************************************************/ +/* Allocate the read/write segments that are mapped to RAM. */ +/************************************************************************/ + +-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-00007FFF +-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-00007FFF +-Z(DATA)TRACEBUFFER=00000004-00007FFF + +-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-00007FFF +-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-00007FFF +-Z(DATA)HEAP+_HEAP_SIZE=00000004-00007FFF + +/************************************************************************/ +/* End of File */ +/************************************************************************/ diff --git a/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/0256/GCC/link_uc3a0256.lds b/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/0256/GCC/link_uc3a0256.lds new file mode 100644 index 000000000..6369fd426 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/0256/GCC/link_uc3a0256.lds @@ -0,0 +1,263 @@ +/****************************************************************************** + * AVR32 AT32UC3A0256 GNU LD script file. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: AVR32 AT32UC3A0256 + * + * - author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32") + +OUTPUT_ARCH(avr32:uc) + +ENTRY(_start) + +MEMORY +{ + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00040000 + INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x0000FFFC + USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200 + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 0x00000200 +} + +PHDRS +{ + FLASH PT_LOAD; + INTRAM PT_NULL; + USERPAGE PT_LOAD; + FACTORYPAGE PT_LOAD; +} + +SECTIONS +{ + /* If this heap size is selected, all the INTRAM space from the end of the + data area to the beginning of the stack will be allocated for the heap. */ + __max_heap_size__ = -1; + + /* Use a default heap size if heap size was not defined. */ + __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__; + + /* Use a default stack size if stack size was not defined. */ + __stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 4K; + + /* Read-only sections, merged into text segment: */ + PROVIDE (__executable_start = 0x80000000); . = 0x80000000; + .interp : { *(.interp) } >FLASH AT>FLASH :FLASH + .reset : { *(.reset) } >FLASH AT>FLASH :FLASH + .hash : { *(.hash) } >FLASH AT>FLASH :FLASH + .dynsym : { *(.dynsym) } >FLASH AT>FLASH :FLASH + .dynstr : { *(.dynstr) } >FLASH AT>FLASH :FLASH + .gnu.version : { *(.gnu.version) } >FLASH AT>FLASH :FLASH + .gnu.version_d : { *(.gnu.version_d) } >FLASH AT>FLASH :FLASH + .gnu.version_r : { *(.gnu.version_r) } >FLASH AT>FLASH :FLASH + .rel.init : { *(.rel.init) } >FLASH AT>FLASH :FLASH + .rela.init : { *(.rela.init) } >FLASH AT>FLASH :FLASH + .rel.text : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH + .rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH + .rel.fini : { *(.rel.fini) } >FLASH AT>FLASH :FLASH + .rela.fini : { *(.rela.fini) } >FLASH AT>FLASH :FLASH + .rel.rodata : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rela.rodata : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rel.data.rel.ro : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH + .rela.data.rel.ro : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH + .rel.data : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH + .rela.data : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH + .rel.tdata : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH + .rela.tdata : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH + .rel.tbss : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH + .rela.tbss : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH + .rel.ctors : { *(.rel.ctors) } >FLASH AT>FLASH :FLASH + .rela.ctors : { *(.rela.ctors) } >FLASH AT>FLASH :FLASH + .rel.dtors : { *(.rel.dtors) } >FLASH AT>FLASH :FLASH + .rela.dtors : { *(.rela.dtors) } >FLASH AT>FLASH :FLASH + .rel.got : { *(.rel.got) } >FLASH AT>FLASH :FLASH + .rela.got : { *(.rela.got) } >FLASH AT>FLASH :FLASH + .rel.bss : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH + .rela.bss : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH + .rel.plt : { *(.rel.plt) } >FLASH AT>FLASH :FLASH + .rela.plt : { *(.rela.plt) } >FLASH AT>FLASH :FLASH + .init : + { + KEEP (*(.init)) + } >FLASH AT>FLASH :FLASH =0xd703d703 + .plt : { *(.plt) } >FLASH AT>FLASH :FLASH + .text : + { + *(.text .stub .text.* .gnu.linkonce.t.*) + KEEP (*(.text.*personality*)) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + } >FLASH AT>FLASH :FLASH =0xd703d703 + .fini : + { + KEEP (*(.fini)) + } >FLASH AT>FLASH :FLASH =0xd703d703 + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + .rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rodata1 : { *(.rodata1) } >FLASH AT>FLASH :FLASH + .eh_frame_hdr : { *(.eh_frame_hdr) } >FLASH AT>FLASH :FLASH + .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH :FLASH + .gcc_except_table : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH :FLASH + .lalign : { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH :FLASH + . = ORIGIN(INTRAM); + .dalign : { . = ALIGN(8); PROVIDE(_data = .); } >INTRAM AT>INTRAM :INTRAM + /* Exception handling */ + .eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) } >INTRAM AT>FLASH :FLASH + .gcc_except_table : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >INTRAM AT>FLASH :FLASH + /* Thread Local Storage sections */ + .tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >INTRAM AT>FLASH :FLASH + .tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >INTRAM AT>FLASH :FLASH + /* Ensure the __preinit_array_start label is properly aligned. We + could instead move the label definition inside the section, but + the linker would then create the section even if it turns out to + be empty, which isn't pretty. */ + PROVIDE (__preinit_array_start = ALIGN(32 / 8)); + .preinit_array : { KEEP (*(.preinit_array)) } >INTRAM AT>FLASH :FLASH + PROVIDE (__preinit_array_end = .); + PROVIDE (__init_array_start = .); + .init_array : { KEEP (*(.init_array)) } >INTRAM AT>FLASH :FLASH + PROVIDE (__init_array_end = .); + PROVIDE (__fini_array_start = .); + .fini_array : { KEEP (*(.fini_array)) } >INTRAM AT>FLASH :FLASH + PROVIDE (__fini_array_end = .); + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin*.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >INTRAM AT>FLASH :FLASH + .dtors : + { + KEEP (*crtbegin*.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >INTRAM AT>FLASH :FLASH + .jcr : { KEEP (*(.jcr)) } >INTRAM AT>FLASH :FLASH + .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >INTRAM AT>FLASH :FLASH + .dynamic : { *(.dynamic) } >INTRAM AT>FLASH :FLASH + .got : { *(.got.plt) *(.got) } >INTRAM AT>FLASH :FLASH + .data : + { + *(.data .data.* .gnu.linkonce.d.*) + KEEP (*(.gnu.linkonce.d.*personality*)) + SORT(CONSTRUCTORS) + } >INTRAM AT>FLASH :FLASH + .data1 : { *(.data1) } >INTRAM AT>FLASH :FLASH + .balign : { . = ALIGN(8); _edata = .; } >INTRAM AT>FLASH :FLASH + _edata = .; + PROVIDE (edata = .); + __bss_start = .; + .bss : + { + *(.dynbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + /* Align here to ensure that the .bss section occupies space up to + _end. Align after .bss to ensure correct alignment even if the + .bss section disappears because there are no input sections. */ + . = ALIGN(8); + } >INTRAM AT>INTRAM :INTRAM + . = ALIGN(8); + _end = .; + PROVIDE (end = .); + __heap_start__ = ALIGN(8); + .heap : + { + *(.heap) + . = (__heap_size__ == __max_heap_size__) ? + ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ - ABSOLUTE(.) : + __heap_size__; + } >INTRAM AT>INTRAM :INTRAM + __heap_end__ = .; + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + .stack ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ : + { + _stack = .; + *(.stack) + . = __stack_size__; + _estack = .; + } >INTRAM AT>INTRAM :INTRAM + .userpage : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE :USERPAGE + .factorypage : { *(.factorypage .factorypage.*) } >FACTORYPAGE AT>FACTORYPAGE :FACTORYPAGE + /DISCARD/ : { *(.note.GNU-stack) } +} diff --git a/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/0256/IAR/lnkuc3a0256.xcl b/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/0256/IAR/lnkuc3a0256.xcl new file mode 100644 index 000000000..d037025d6 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/0256/IAR/lnkuc3a0256.xcl @@ -0,0 +1,138 @@ +/****************************************************************************** + * AVR32 AT32UC3A0256 XLINK command file for AVR32 IAR C/C++ Compiler. + * + * The assumed memory layout is the one of the AT32UC3A0256: + * + * Start Stop Name Type + * ---------- ---------- ----- -------------- + * 0x00000000 0x0000FFFF SRAM RAM + * 0x80000000 0x8003FFFF FLASH FLASH + * + * Usage: xlink your_file(s) -f xcl-file libraries + * + * - Compiler: IAR EWAVR32 + * - Supported devices: AVR32 AT32UC3A0256 + * + * - author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +/************************************************************************/ +/* The following segments are defined in this link file: */ +/* */ +/* Code segments */ +/* CODE32 -- Program code used by __code32 functions. */ +/* RESET -- Reset code. */ +/* EVSEG -- Exception vector handlers. */ +/* */ +/* Constant segments */ +/* INITTAB -- Segment initializer table. */ +/* DIFUNCT -- Dynamic initialization vector used by C++. */ +/* SWITCH -- Switch tables. */ +/* ACTAB -- Table of pointers to acall functions. */ +/* */ +/* DATA21_ID -- Initialization data for DATA21_I. */ +/* DATA32_ID -- Initialization data for DATA32_I. */ +/* DATA32_C -- Constant __data32 data. */ +/* */ +/* CHECKSUM -- Checksum segment. */ +/* */ +/* Data segments */ +/* DATA21_I -- Initialized __data21 data with non-zero */ +/* initial value. */ +/* DATA32_I -- Initialized __data32 data with non-zero */ +/* initial value. */ +/* DATA21_Z -- Initialized __data21 data with zero initial value. */ +/* DATA32_Z -- Initialized __data32 data with zero initial value. */ +/* DATA21_N -- Non-initialized __data21. */ +/* DATA32_N -- Non-initialized __data32. */ +/* SSTACK -- The system stack. */ +/* CSTACK -- The application stack. */ +/* HEAP -- The heap used by malloc and free. */ +/* */ +/************************************************************************/ + +/************************************************************************/ +/* Define CPU */ +/************************************************************************/ + +-cavr32 + +// Declare the IPR0 memory location +-DIPR0=FFFF0800 + +/************************************************************************/ +/* Reset code is located at address 0x80000000 and up. */ +/************************************************************************/ + +-Z(CODE)RESET=80000000-8003FFFF + +/************************************************************************/ +/* The exception handler code is located at address 0x80000000 */ +/* and up. Make sure that the exception table gets properly */ +/* allocated. By using the special -Z@ allocation primitive, the */ +/* placement is guaranteed to be at _EVBASE and onwards. */ +/************************************************************************/ + +-Z@(CODE)EVTAB=80004000-8003FFFF +-Z@(CODE)EV100=80004100-8003FFFF +-P(CODE)EVSEG=80004000-8003FFFF + +/************************************************************************/ +/* Allocate code and const segments. */ +/************************************************************************/ + +-P(CODE)CODE32=80000000-8003FFFF +-P(CONST)DATA32_C=80000000-8003FFFF + +// Initializers +-Z(CONST)INITTAB,DIFUNCT=80000000-8003FFFF +-Z(CONST)CHECKSUM,SWITCH=80000000-8003FFFF +-Z(CONST)DATA21_ID,DATA32_ID=80000000-8003FFFF + +-Z(CONST)ACTAB,HTAB=80000000-8003FFFF + +/************************************************************************/ +/* Allocate the read/write segments that are mapped to RAM. */ +/************************************************************************/ + +-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-0000FFFF +-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-0000FFFF +-Z(DATA)TRACEBUFFER=00000004-0000FFFF + +-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-0000FFFF +-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-0000FFFF +-Z(DATA)HEAP+_HEAP_SIZE=00000004-0000FFFF + +/************************************************************************/ +/* End of File */ +/************************************************************************/ diff --git a/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/0512/GCC/link_uc3a0512.lds b/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/0512/GCC/link_uc3a0512.lds new file mode 100644 index 000000000..d89138cb5 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/0512/GCC/link_uc3a0512.lds @@ -0,0 +1,263 @@ +/****************************************************************************** + * AVR32 AT32UC3A0512 GNU LD script file. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: AVR32 AT32UC3A0512 + * + * - author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32") + +OUTPUT_ARCH(avr32:uc) + +ENTRY(_start) + +MEMORY +{ + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00080000 + INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x0000FFFC + USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200 + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 0x00000200 +} + +PHDRS +{ + FLASH PT_LOAD; + INTRAM PT_NULL; + USERPAGE PT_LOAD; + FACTORYPAGE PT_LOAD; +} + +SECTIONS +{ + /* If this heap size is selected, all the INTRAM space from the end of the + data area to the beginning of the stack will be allocated for the heap. */ + __max_heap_size__ = -1; + + /* Use a default heap size if heap size was not defined. */ + __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__; + + /* Use a default stack size if stack size was not defined. */ + __stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 4K; + + /* Read-only sections, merged into text segment: */ + PROVIDE (__executable_start = 0x80000000); . = 0x80000000; + .interp : { *(.interp) } >FLASH AT>FLASH :FLASH + .reset : { *(.reset) } >FLASH AT>FLASH :FLASH + .hash : { *(.hash) } >FLASH AT>FLASH :FLASH + .dynsym : { *(.dynsym) } >FLASH AT>FLASH :FLASH + .dynstr : { *(.dynstr) } >FLASH AT>FLASH :FLASH + .gnu.version : { *(.gnu.version) } >FLASH AT>FLASH :FLASH + .gnu.version_d : { *(.gnu.version_d) } >FLASH AT>FLASH :FLASH + .gnu.version_r : { *(.gnu.version_r) } >FLASH AT>FLASH :FLASH + .rel.init : { *(.rel.init) } >FLASH AT>FLASH :FLASH + .rela.init : { *(.rela.init) } >FLASH AT>FLASH :FLASH + .rel.text : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH + .rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH + .rel.fini : { *(.rel.fini) } >FLASH AT>FLASH :FLASH + .rela.fini : { *(.rela.fini) } >FLASH AT>FLASH :FLASH + .rel.rodata : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rela.rodata : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rel.data.rel.ro : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH + .rela.data.rel.ro : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH + .rel.data : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH + .rela.data : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH + .rel.tdata : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH + .rela.tdata : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH + .rel.tbss : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH + .rela.tbss : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH + .rel.ctors : { *(.rel.ctors) } >FLASH AT>FLASH :FLASH + .rela.ctors : { *(.rela.ctors) } >FLASH AT>FLASH :FLASH + .rel.dtors : { *(.rel.dtors) } >FLASH AT>FLASH :FLASH + .rela.dtors : { *(.rela.dtors) } >FLASH AT>FLASH :FLASH + .rel.got : { *(.rel.got) } >FLASH AT>FLASH :FLASH + .rela.got : { *(.rela.got) } >FLASH AT>FLASH :FLASH + .rel.bss : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH + .rela.bss : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH + .rel.plt : { *(.rel.plt) } >FLASH AT>FLASH :FLASH + .rela.plt : { *(.rela.plt) } >FLASH AT>FLASH :FLASH + .init : + { + KEEP (*(.init)) + } >FLASH AT>FLASH :FLASH =0xd703d703 + .plt : { *(.plt) } >FLASH AT>FLASH :FLASH + .text : + { + *(.text .stub .text.* .gnu.linkonce.t.*) + KEEP (*(.text.*personality*)) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + } >FLASH AT>FLASH :FLASH =0xd703d703 + .fini : + { + KEEP (*(.fini)) + } >FLASH AT>FLASH :FLASH =0xd703d703 + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + .rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rodata1 : { *(.rodata1) } >FLASH AT>FLASH :FLASH + .eh_frame_hdr : { *(.eh_frame_hdr) } >FLASH AT>FLASH :FLASH + .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH :FLASH + .gcc_except_table : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH :FLASH + .lalign : { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH :FLASH + . = ORIGIN(INTRAM); + .dalign : { . = ALIGN(8); PROVIDE(_data = .); } >INTRAM AT>INTRAM :INTRAM + /* Exception handling */ + .eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) } >INTRAM AT>FLASH :FLASH + .gcc_except_table : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >INTRAM AT>FLASH :FLASH + /* Thread Local Storage sections */ + .tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >INTRAM AT>FLASH :FLASH + .tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >INTRAM AT>FLASH :FLASH + /* Ensure the __preinit_array_start label is properly aligned. We + could instead move the label definition inside the section, but + the linker would then create the section even if it turns out to + be empty, which isn't pretty. */ + PROVIDE (__preinit_array_start = ALIGN(32 / 8)); + .preinit_array : { KEEP (*(.preinit_array)) } >INTRAM AT>FLASH :FLASH + PROVIDE (__preinit_array_end = .); + PROVIDE (__init_array_start = .); + .init_array : { KEEP (*(.init_array)) } >INTRAM AT>FLASH :FLASH + PROVIDE (__init_array_end = .); + PROVIDE (__fini_array_start = .); + .fini_array : { KEEP (*(.fini_array)) } >INTRAM AT>FLASH :FLASH + PROVIDE (__fini_array_end = .); + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin*.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >INTRAM AT>FLASH :FLASH + .dtors : + { + KEEP (*crtbegin*.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >INTRAM AT>FLASH :FLASH + .jcr : { KEEP (*(.jcr)) } >INTRAM AT>FLASH :FLASH + .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >INTRAM AT>FLASH :FLASH + .dynamic : { *(.dynamic) } >INTRAM AT>FLASH :FLASH + .got : { *(.got.plt) *(.got) } >INTRAM AT>FLASH :FLASH + .data : + { + *(.data .data.* .gnu.linkonce.d.*) + KEEP (*(.gnu.linkonce.d.*personality*)) + SORT(CONSTRUCTORS) + } >INTRAM AT>FLASH :FLASH + .data1 : { *(.data1) } >INTRAM AT>FLASH :FLASH + .balign : { . = ALIGN(8); _edata = .; } >INTRAM AT>FLASH :FLASH + _edata = .; + PROVIDE (edata = .); + __bss_start = .; + .bss : + { + *(.dynbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + /* Align here to ensure that the .bss section occupies space up to + _end. Align after .bss to ensure correct alignment even if the + .bss section disappears because there are no input sections. */ + . = ALIGN(8); + } >INTRAM AT>INTRAM :INTRAM + . = ALIGN(8); + _end = .; + PROVIDE (end = .); + __heap_start__ = ALIGN(8); + .heap : + { + *(.heap) + . = (__heap_size__ == __max_heap_size__) ? + ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ - ABSOLUTE(.) : + __heap_size__; + } >INTRAM AT>INTRAM :INTRAM + __heap_end__ = .; + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + .stack ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ : + { + _stack = .; + *(.stack) + . = __stack_size__; + _estack = .; + } >INTRAM AT>INTRAM :INTRAM + .userpage : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE :USERPAGE + .factorypage : { *(.factorypage .factorypage.*) } >FACTORYPAGE AT>FACTORYPAGE :FACTORYPAGE + /DISCARD/ : { *(.note.GNU-stack) } +} diff --git a/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/0512/IAR/lnkuc3a0512.xcl b/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/0512/IAR/lnkuc3a0512.xcl new file mode 100644 index 000000000..d6173e786 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/0512/IAR/lnkuc3a0512.xcl @@ -0,0 +1,138 @@ +/****************************************************************************** + * AVR32 AT32UC3A0512 XLINK command file for AVR32 IAR C/C++ Compiler. + * + * The assumed memory layout is the one of the AT32UC3A0512: + * + * Start Stop Name Type + * ---------- ---------- ----- -------------- + * 0x00000000 0x0000FFFF SRAM RAM + * 0x80000000 0x8007FFFF FLASH FLASH + * + * Usage: xlink your_file(s) -f xcl-file libraries + * + * - Compiler: IAR EWAVR32 + * - Supported devices: AVR32 AT32UC3A0512 + * + * - author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +/************************************************************************/ +/* The following segments are defined in this link file: */ +/* */ +/* Code segments */ +/* CODE32 -- Program code used by __code32 functions. */ +/* RESET -- Reset code. */ +/* EVSEG -- Exception vector handlers. */ +/* */ +/* Constant segments */ +/* INITTAB -- Segment initializer table. */ +/* DIFUNCT -- Dynamic initialization vector used by C++. */ +/* SWITCH -- Switch tables. */ +/* ACTAB -- Table of pointers to acall functions. */ +/* */ +/* DATA21_ID -- Initialization data for DATA21_I. */ +/* DATA32_ID -- Initialization data for DATA32_I. */ +/* DATA32_C -- Constant __data32 data. */ +/* */ +/* CHECKSUM -- Checksum segment. */ +/* */ +/* Data segments */ +/* DATA21_I -- Initialized __data21 data with non-zero */ +/* initial value. */ +/* DATA32_I -- Initialized __data32 data with non-zero */ +/* initial value. */ +/* DATA21_Z -- Initialized __data21 data with zero initial value. */ +/* DATA32_Z -- Initialized __data32 data with zero initial value. */ +/* DATA21_N -- Non-initialized __data21. */ +/* DATA32_N -- Non-initialized __data32. */ +/* SSTACK -- The system stack. */ +/* CSTACK -- The application stack. */ +/* HEAP -- The heap used by malloc and free. */ +/* */ +/************************************************************************/ + +/************************************************************************/ +/* Define CPU */ +/************************************************************************/ + +-cavr32 + +// Declare the IPR0 memory location +-DIPR0=FFFF0800 + +/************************************************************************/ +/* Reset code is located at address 0x80000000 and up. */ +/************************************************************************/ + +-Z(CODE)RESET=80000000-8007FFFF + +/************************************************************************/ +/* The exception handler code is located at address 0x80000000 */ +/* and up. Make sure that the exception table gets properly */ +/* allocated. By using the special -Z@ allocation primitive, the */ +/* placement is guaranteed to be at _EVBASE and onwards. */ +/************************************************************************/ + +-Z@(CODE)EVTAB=80004000-8007FFFF +-Z@(CODE)EV100=80004100-8007FFFF +-P(CODE)EVSEG=80004000-8007FFFF + +/************************************************************************/ +/* Allocate code and const segments. */ +/************************************************************************/ + +-P(CODE)CODE32=80000000-8007FFFF +-P(CONST)DATA32_C=80000000-8007FFFF + +// Initializers +-Z(CONST)INITTAB,DIFUNCT=80000000-8007FFFF +-Z(CONST)CHECKSUM,SWITCH=80000000-8007FFFF +-Z(CONST)DATA21_ID,DATA32_ID=80000000-8007FFFF + +-Z(CONST)ACTAB,HTAB=80000000-8007FFFF + +/************************************************************************/ +/* Allocate the read/write segments that are mapped to RAM. */ +/************************************************************************/ + +-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-0000FFFF +-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-0000FFFF +-Z(DATA)TRACEBUFFER=00000004-0000FFFF + +-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-0000FFFF +-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-0000FFFF +-Z(DATA)HEAP+_HEAP_SIZE=00000004-0000FFFF + +/************************************************************************/ +/* End of File */ +/************************************************************************/ diff --git a/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/1128/GCC/link_uc3a1128.lds b/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/1128/GCC/link_uc3a1128.lds new file mode 100644 index 000000000..ffc92e4da --- /dev/null +++ b/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/1128/GCC/link_uc3a1128.lds @@ -0,0 +1,263 @@ +/****************************************************************************** + * AVR32 AT32UC3A1128 GNU LD script file. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: AVR32 AT32UC3A1128 + * + * - author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32") + +OUTPUT_ARCH(avr32:uc) + +ENTRY(_start) + +MEMORY +{ + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00020000 + INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x00007FFC + USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200 + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 0x00000200 +} + +PHDRS +{ + FLASH PT_LOAD; + INTRAM PT_NULL; + USERPAGE PT_LOAD; + FACTORYPAGE PT_LOAD; +} + +SECTIONS +{ + /* If this heap size is selected, all the INTRAM space from the end of the + data area to the beginning of the stack will be allocated for the heap. */ + __max_heap_size__ = -1; + + /* Use a default heap size if heap size was not defined. */ + __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__; + + /* Use a default stack size if stack size was not defined. */ + __stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 4K; + + /* Read-only sections, merged into text segment: */ + PROVIDE (__executable_start = 0x80000000); . = 0x80000000; + .interp : { *(.interp) } >FLASH AT>FLASH :FLASH + .reset : { *(.reset) } >FLASH AT>FLASH :FLASH + .hash : { *(.hash) } >FLASH AT>FLASH :FLASH + .dynsym : { *(.dynsym) } >FLASH AT>FLASH :FLASH + .dynstr : { *(.dynstr) } >FLASH AT>FLASH :FLASH + .gnu.version : { *(.gnu.version) } >FLASH AT>FLASH :FLASH + .gnu.version_d : { *(.gnu.version_d) } >FLASH AT>FLASH :FLASH + .gnu.version_r : { *(.gnu.version_r) } >FLASH AT>FLASH :FLASH + .rel.init : { *(.rel.init) } >FLASH AT>FLASH :FLASH + .rela.init : { *(.rela.init) } >FLASH AT>FLASH :FLASH + .rel.text : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH + .rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH + .rel.fini : { *(.rel.fini) } >FLASH AT>FLASH :FLASH + .rela.fini : { *(.rela.fini) } >FLASH AT>FLASH :FLASH + .rel.rodata : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rela.rodata : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rel.data.rel.ro : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH + .rela.data.rel.ro : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH + .rel.data : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH + .rela.data : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH + .rel.tdata : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH + .rela.tdata : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH + .rel.tbss : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH + .rela.tbss : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH + .rel.ctors : { *(.rel.ctors) } >FLASH AT>FLASH :FLASH + .rela.ctors : { *(.rela.ctors) } >FLASH AT>FLASH :FLASH + .rel.dtors : { *(.rel.dtors) } >FLASH AT>FLASH :FLASH + .rela.dtors : { *(.rela.dtors) } >FLASH AT>FLASH :FLASH + .rel.got : { *(.rel.got) } >FLASH AT>FLASH :FLASH + .rela.got : { *(.rela.got) } >FLASH AT>FLASH :FLASH + .rel.bss : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH + .rela.bss : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH + .rel.plt : { *(.rel.plt) } >FLASH AT>FLASH :FLASH + .rela.plt : { *(.rela.plt) } >FLASH AT>FLASH :FLASH + .init : + { + KEEP (*(.init)) + } >FLASH AT>FLASH :FLASH =0xd703d703 + .plt : { *(.plt) } >FLASH AT>FLASH :FLASH + .text : + { + *(.text .stub .text.* .gnu.linkonce.t.*) + KEEP (*(.text.*personality*)) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + } >FLASH AT>FLASH :FLASH =0xd703d703 + .fini : + { + KEEP (*(.fini)) + } >FLASH AT>FLASH :FLASH =0xd703d703 + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + .rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rodata1 : { *(.rodata1) } >FLASH AT>FLASH :FLASH + .eh_frame_hdr : { *(.eh_frame_hdr) } >FLASH AT>FLASH :FLASH + .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH :FLASH + .gcc_except_table : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH :FLASH + .lalign : { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH :FLASH + . = ORIGIN(INTRAM); + .dalign : { . = ALIGN(8); PROVIDE(_data = .); } >INTRAM AT>INTRAM :INTRAM + /* Exception handling */ + .eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) } >INTRAM AT>FLASH :FLASH + .gcc_except_table : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >INTRAM AT>FLASH :FLASH + /* Thread Local Storage sections */ + .tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >INTRAM AT>FLASH :FLASH + .tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >INTRAM AT>FLASH :FLASH + /* Ensure the __preinit_array_start label is properly aligned. We + could instead move the label definition inside the section, but + the linker would then create the section even if it turns out to + be empty, which isn't pretty. */ + PROVIDE (__preinit_array_start = ALIGN(32 / 8)); + .preinit_array : { KEEP (*(.preinit_array)) } >INTRAM AT>FLASH :FLASH + PROVIDE (__preinit_array_end = .); + PROVIDE (__init_array_start = .); + .init_array : { KEEP (*(.init_array)) } >INTRAM AT>FLASH :FLASH + PROVIDE (__init_array_end = .); + PROVIDE (__fini_array_start = .); + .fini_array : { KEEP (*(.fini_array)) } >INTRAM AT>FLASH :FLASH + PROVIDE (__fini_array_end = .); + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin*.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >INTRAM AT>FLASH :FLASH + .dtors : + { + KEEP (*crtbegin*.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >INTRAM AT>FLASH :FLASH + .jcr : { KEEP (*(.jcr)) } >INTRAM AT>FLASH :FLASH + .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >INTRAM AT>FLASH :FLASH + .dynamic : { *(.dynamic) } >INTRAM AT>FLASH :FLASH + .got : { *(.got.plt) *(.got) } >INTRAM AT>FLASH :FLASH + .data : + { + *(.data .data.* .gnu.linkonce.d.*) + KEEP (*(.gnu.linkonce.d.*personality*)) + SORT(CONSTRUCTORS) + } >INTRAM AT>FLASH :FLASH + .data1 : { *(.data1) } >INTRAM AT>FLASH :FLASH + .balign : { . = ALIGN(8); _edata = .; } >INTRAM AT>FLASH :FLASH + _edata = .; + PROVIDE (edata = .); + __bss_start = .; + .bss : + { + *(.dynbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + /* Align here to ensure that the .bss section occupies space up to + _end. Align after .bss to ensure correct alignment even if the + .bss section disappears because there are no input sections. */ + . = ALIGN(8); + } >INTRAM AT>INTRAM :INTRAM + . = ALIGN(8); + _end = .; + PROVIDE (end = .); + __heap_start__ = ALIGN(8); + .heap : + { + *(.heap) + . = (__heap_size__ == __max_heap_size__) ? + ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ - ABSOLUTE(.) : + __heap_size__; + } >INTRAM AT>INTRAM :INTRAM + __heap_end__ = .; + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + .stack ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ : + { + _stack = .; + *(.stack) + . = __stack_size__; + _estack = .; + } >INTRAM AT>INTRAM :INTRAM + .userpage : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE :USERPAGE + .factorypage : { *(.factorypage .factorypage.*) } >FACTORYPAGE AT>FACTORYPAGE :FACTORYPAGE + /DISCARD/ : { *(.note.GNU-stack) } +} diff --git a/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/1128/IAR/lnkuc3a1128.xcl b/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/1128/IAR/lnkuc3a1128.xcl new file mode 100644 index 000000000..9f9237cd7 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/1128/IAR/lnkuc3a1128.xcl @@ -0,0 +1,138 @@ +/****************************************************************************** + * AVR32 AT32UC3A1128 XLINK command file for AVR32 IAR C/C++ Compiler. + * + * The assumed memory layout is the one of the AT32UC3A1128: + * + * Start Stop Name Type + * ---------- ---------- ----- -------------- + * 0x00000000 0x00007FFF SRAM RAM + * 0x80000000 0x8001FFFF FLASH FLASH + * + * Usage: xlink your_file(s) -f xcl-file libraries + * + * - Compiler: IAR EWAVR32 + * - Supported devices: AVR32 AT32UC3A1128 + * + * - author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +/************************************************************************/ +/* The following segments are defined in this link file: */ +/* */ +/* Code segments */ +/* CODE32 -- Program code used by __code32 functions. */ +/* RESET -- Reset code. */ +/* EVSEG -- Exception vector handlers. */ +/* */ +/* Constant segments */ +/* INITTAB -- Segment initializer table. */ +/* DIFUNCT -- Dynamic initialization vector used by C++. */ +/* SWITCH -- Switch tables. */ +/* ACTAB -- Table of pointers to acall functions. */ +/* */ +/* DATA21_ID -- Initialization data for DATA21_I. */ +/* DATA32_ID -- Initialization data for DATA32_I. */ +/* DATA32_C -- Constant __data32 data. */ +/* */ +/* CHECKSUM -- Checksum segment. */ +/* */ +/* Data segments */ +/* DATA21_I -- Initialized __data21 data with non-zero */ +/* initial value. */ +/* DATA32_I -- Initialized __data32 data with non-zero */ +/* initial value. */ +/* DATA21_Z -- Initialized __data21 data with zero initial value. */ +/* DATA32_Z -- Initialized __data32 data with zero initial value. */ +/* DATA21_N -- Non-initialized __data21. */ +/* DATA32_N -- Non-initialized __data32. */ +/* SSTACK -- The system stack. */ +/* CSTACK -- The application stack. */ +/* HEAP -- The heap used by malloc and free. */ +/* */ +/************************************************************************/ + +/************************************************************************/ +/* Define CPU */ +/************************************************************************/ + +-cavr32 + +// Declare the IPR0 memory location +-DIPR0=FFFF0800 + +/************************************************************************/ +/* Reset code is located at address 0x80000000 and up. */ +/************************************************************************/ + +-Z(CODE)RESET=80000000-8001FFFF + +/************************************************************************/ +/* The exception handler code is located at address 0x80000000 */ +/* and up. Make sure that the exception table gets properly */ +/* allocated. By using the special -Z@ allocation primitive, the */ +/* placement is guaranteed to be at _EVBASE and onwards. */ +/************************************************************************/ + +-Z@(CODE)EVTAB=80004000-8001FFFF +-Z@(CODE)EV100=80004100-8001FFFF +-P(CODE)EVSEG=80004000-8001FFFF + +/************************************************************************/ +/* Allocate code and const segments. */ +/************************************************************************/ + +-P(CODE)CODE32=80000000-8001FFFF +-P(CONST)DATA32_C=80000000-8001FFFF + +// Initializers +-Z(CONST)INITTAB,DIFUNCT=80000000-8001FFFF +-Z(CONST)CHECKSUM,SWITCH=80000000-8001FFFF +-Z(CONST)DATA21_ID,DATA32_ID=80000000-8001FFFF + +-Z(CONST)ACTAB,HTAB=80000000-8001FFFF + +/************************************************************************/ +/* Allocate the read/write segments that are mapped to RAM. */ +/************************************************************************/ + +-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-00007FFF +-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-00007FFF +-Z(DATA)TRACEBUFFER=00000004-00007FFF + +-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-00007FFF +-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-00007FFF +-Z(DATA)HEAP+_HEAP_SIZE=00000004-00007FFF + +/************************************************************************/ +/* End of File */ +/************************************************************************/ diff --git a/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/1256/GCC/link_uc3a1256.lds b/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/1256/GCC/link_uc3a1256.lds new file mode 100644 index 000000000..1e464f832 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/1256/GCC/link_uc3a1256.lds @@ -0,0 +1,263 @@ +/****************************************************************************** + * AVR32 AT32UC3A1256 GNU LD script file. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: AVR32 AT32UC3A1256 + * + * - author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32") + +OUTPUT_ARCH(avr32:uc) + +ENTRY(_start) + +MEMORY +{ + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00040000 + INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x0000FFFC + USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200 + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 0x00000200 +} + +PHDRS +{ + FLASH PT_LOAD; + INTRAM PT_NULL; + USERPAGE PT_LOAD; + FACTORYPAGE PT_LOAD; +} + +SECTIONS +{ + /* If this heap size is selected, all the INTRAM space from the end of the + data area to the beginning of the stack will be allocated for the heap. */ + __max_heap_size__ = -1; + + /* Use a default heap size if heap size was not defined. */ + __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__; + + /* Use a default stack size if stack size was not defined. */ + __stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 4K; + + /* Read-only sections, merged into text segment: */ + PROVIDE (__executable_start = 0x80000000); . = 0x80000000; + .interp : { *(.interp) } >FLASH AT>FLASH :FLASH + .reset : { *(.reset) } >FLASH AT>FLASH :FLASH + .hash : { *(.hash) } >FLASH AT>FLASH :FLASH + .dynsym : { *(.dynsym) } >FLASH AT>FLASH :FLASH + .dynstr : { *(.dynstr) } >FLASH AT>FLASH :FLASH + .gnu.version : { *(.gnu.version) } >FLASH AT>FLASH :FLASH + .gnu.version_d : { *(.gnu.version_d) } >FLASH AT>FLASH :FLASH + .gnu.version_r : { *(.gnu.version_r) } >FLASH AT>FLASH :FLASH + .rel.init : { *(.rel.init) } >FLASH AT>FLASH :FLASH + .rela.init : { *(.rela.init) } >FLASH AT>FLASH :FLASH + .rel.text : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH + .rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH + .rel.fini : { *(.rel.fini) } >FLASH AT>FLASH :FLASH + .rela.fini : { *(.rela.fini) } >FLASH AT>FLASH :FLASH + .rel.rodata : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rela.rodata : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rel.data.rel.ro : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH + .rela.data.rel.ro : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH + .rel.data : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH + .rela.data : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH + .rel.tdata : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH + .rela.tdata : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH + .rel.tbss : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH + .rela.tbss : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH + .rel.ctors : { *(.rel.ctors) } >FLASH AT>FLASH :FLASH + .rela.ctors : { *(.rela.ctors) } >FLASH AT>FLASH :FLASH + .rel.dtors : { *(.rel.dtors) } >FLASH AT>FLASH :FLASH + .rela.dtors : { *(.rela.dtors) } >FLASH AT>FLASH :FLASH + .rel.got : { *(.rel.got) } >FLASH AT>FLASH :FLASH + .rela.got : { *(.rela.got) } >FLASH AT>FLASH :FLASH + .rel.bss : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH + .rela.bss : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH + .rel.plt : { *(.rel.plt) } >FLASH AT>FLASH :FLASH + .rela.plt : { *(.rela.plt) } >FLASH AT>FLASH :FLASH + .init : + { + KEEP (*(.init)) + } >FLASH AT>FLASH :FLASH =0xd703d703 + .plt : { *(.plt) } >FLASH AT>FLASH :FLASH + .text : + { + *(.text .stub .text.* .gnu.linkonce.t.*) + KEEP (*(.text.*personality*)) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + } >FLASH AT>FLASH :FLASH =0xd703d703 + .fini : + { + KEEP (*(.fini)) + } >FLASH AT>FLASH :FLASH =0xd703d703 + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + .rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rodata1 : { *(.rodata1) } >FLASH AT>FLASH :FLASH + .eh_frame_hdr : { *(.eh_frame_hdr) } >FLASH AT>FLASH :FLASH + .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH :FLASH + .gcc_except_table : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH :FLASH + .lalign : { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH :FLASH + . = ORIGIN(INTRAM); + .dalign : { . = ALIGN(8); PROVIDE(_data = .); } >INTRAM AT>INTRAM :INTRAM + /* Exception handling */ + .eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) } >INTRAM AT>FLASH :FLASH + .gcc_except_table : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >INTRAM AT>FLASH :FLASH + /* Thread Local Storage sections */ + .tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >INTRAM AT>FLASH :FLASH + .tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >INTRAM AT>FLASH :FLASH + /* Ensure the __preinit_array_start label is properly aligned. We + could instead move the label definition inside the section, but + the linker would then create the section even if it turns out to + be empty, which isn't pretty. */ + PROVIDE (__preinit_array_start = ALIGN(32 / 8)); + .preinit_array : { KEEP (*(.preinit_array)) } >INTRAM AT>FLASH :FLASH + PROVIDE (__preinit_array_end = .); + PROVIDE (__init_array_start = .); + .init_array : { KEEP (*(.init_array)) } >INTRAM AT>FLASH :FLASH + PROVIDE (__init_array_end = .); + PROVIDE (__fini_array_start = .); + .fini_array : { KEEP (*(.fini_array)) } >INTRAM AT>FLASH :FLASH + PROVIDE (__fini_array_end = .); + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin*.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >INTRAM AT>FLASH :FLASH + .dtors : + { + KEEP (*crtbegin*.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >INTRAM AT>FLASH :FLASH + .jcr : { KEEP (*(.jcr)) } >INTRAM AT>FLASH :FLASH + .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >INTRAM AT>FLASH :FLASH + .dynamic : { *(.dynamic) } >INTRAM AT>FLASH :FLASH + .got : { *(.got.plt) *(.got) } >INTRAM AT>FLASH :FLASH + .data : + { + *(.data .data.* .gnu.linkonce.d.*) + KEEP (*(.gnu.linkonce.d.*personality*)) + SORT(CONSTRUCTORS) + } >INTRAM AT>FLASH :FLASH + .data1 : { *(.data1) } >INTRAM AT>FLASH :FLASH + .balign : { . = ALIGN(8); _edata = .; } >INTRAM AT>FLASH :FLASH + _edata = .; + PROVIDE (edata = .); + __bss_start = .; + .bss : + { + *(.dynbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + /* Align here to ensure that the .bss section occupies space up to + _end. Align after .bss to ensure correct alignment even if the + .bss section disappears because there are no input sections. */ + . = ALIGN(8); + } >INTRAM AT>INTRAM :INTRAM + . = ALIGN(8); + _end = .; + PROVIDE (end = .); + __heap_start__ = ALIGN(8); + .heap : + { + *(.heap) + . = (__heap_size__ == __max_heap_size__) ? + ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ - ABSOLUTE(.) : + __heap_size__; + } >INTRAM AT>INTRAM :INTRAM + __heap_end__ = .; + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + .stack ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ : + { + _stack = .; + *(.stack) + . = __stack_size__; + _estack = .; + } >INTRAM AT>INTRAM :INTRAM + .userpage : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE :USERPAGE + .factorypage : { *(.factorypage .factorypage.*) } >FACTORYPAGE AT>FACTORYPAGE :FACTORYPAGE + /DISCARD/ : { *(.note.GNU-stack) } +} diff --git a/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/1256/IAR/lnkuc3a1256.xcl b/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/1256/IAR/lnkuc3a1256.xcl new file mode 100644 index 000000000..823654a68 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/1256/IAR/lnkuc3a1256.xcl @@ -0,0 +1,138 @@ +/****************************************************************************** + * AVR32 AT32UC3A1256 XLINK command file for AVR32 IAR C/C++ Compiler. + * + * The assumed memory layout is the one of the AT32UC3A1256: + * + * Start Stop Name Type + * ---------- ---------- ----- -------------- + * 0x00000000 0x0000FFFF SRAM RAM + * 0x80000000 0x8003FFFF FLASH FLASH + * + * Usage: xlink your_file(s) -f xcl-file libraries + * + * - Compiler: IAR EWAVR32 + * - Supported devices: AVR32 AT32UC3A1256 + * + * - author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +/************************************************************************/ +/* The following segments are defined in this link file: */ +/* */ +/* Code segments */ +/* CODE32 -- Program code used by __code32 functions. */ +/* RESET -- Reset code. */ +/* EVSEG -- Exception vector handlers. */ +/* */ +/* Constant segments */ +/* INITTAB -- Segment initializer table. */ +/* DIFUNCT -- Dynamic initialization vector used by C++. */ +/* SWITCH -- Switch tables. */ +/* ACTAB -- Table of pointers to acall functions. */ +/* */ +/* DATA21_ID -- Initialization data for DATA21_I. */ +/* DATA32_ID -- Initialization data for DATA32_I. */ +/* DATA32_C -- Constant __data32 data. */ +/* */ +/* CHECKSUM -- Checksum segment. */ +/* */ +/* Data segments */ +/* DATA21_I -- Initialized __data21 data with non-zero */ +/* initial value. */ +/* DATA32_I -- Initialized __data32 data with non-zero */ +/* initial value. */ +/* DATA21_Z -- Initialized __data21 data with zero initial value. */ +/* DATA32_Z -- Initialized __data32 data with zero initial value. */ +/* DATA21_N -- Non-initialized __data21. */ +/* DATA32_N -- Non-initialized __data32. */ +/* SSTACK -- The system stack. */ +/* CSTACK -- The application stack. */ +/* HEAP -- The heap used by malloc and free. */ +/* */ +/************************************************************************/ + +/************************************************************************/ +/* Define CPU */ +/************************************************************************/ + +-cavr32 + +// Declare the IPR0 memory location +-DIPR0=FFFF0800 + +/************************************************************************/ +/* Reset code is located at address 0x80000000 and up. */ +/************************************************************************/ + +-Z(CODE)RESET=80000000-8003FFFF + +/************************************************************************/ +/* The exception handler code is located at address 0x80000000 */ +/* and up. Make sure that the exception table gets properly */ +/* allocated. By using the special -Z@ allocation primitive, the */ +/* placement is guaranteed to be at _EVBASE and onwards. */ +/************************************************************************/ + +-Z@(CODE)EVTAB=80004000-8003FFFF +-Z@(CODE)EV100=80004100-8003FFFF +-P(CODE)EVSEG=80004000-8003FFFF + +/************************************************************************/ +/* Allocate code and const segments. */ +/************************************************************************/ + +-P(CODE)CODE32=80000000-8003FFFF +-P(CONST)DATA32_C=80000000-8003FFFF + +// Initializers +-Z(CONST)INITTAB,DIFUNCT=80000000-8003FFFF +-Z(CONST)CHECKSUM,SWITCH=80000000-8003FFFF +-Z(CONST)DATA21_ID,DATA32_ID=80000000-8003FFFF + +-Z(CONST)ACTAB,HTAB=80000000-8003FFFF + +/************************************************************************/ +/* Allocate the read/write segments that are mapped to RAM. */ +/************************************************************************/ + +-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-0000FFFF +-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-0000FFFF +-Z(DATA)TRACEBUFFER=00000004-0000FFFF + +-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-0000FFFF +-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-0000FFFF +-Z(DATA)HEAP+_HEAP_SIZE=00000004-0000FFFF + +/************************************************************************/ +/* End of File */ +/************************************************************************/ diff --git a/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/1512/GCC/link_uc3a1512.lds b/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/1512/GCC/link_uc3a1512.lds new file mode 100644 index 000000000..a171bd0b6 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/1512/GCC/link_uc3a1512.lds @@ -0,0 +1,263 @@ +/****************************************************************************** + * AVR32 AT32UC3A1512 GNU LD script file. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: AVR32 AT32UC3A1512 + * + * - author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32") + +OUTPUT_ARCH(avr32:uc) + +ENTRY(_start) + +MEMORY +{ + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00080000 + INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x0000FFFC + USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200 + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 0x00000200 +} + +PHDRS +{ + FLASH PT_LOAD; + INTRAM PT_NULL; + USERPAGE PT_LOAD; + FACTORYPAGE PT_LOAD; +} + +SECTIONS +{ + /* If this heap size is selected, all the INTRAM space from the end of the + data area to the beginning of the stack will be allocated for the heap. */ + __max_heap_size__ = -1; + + /* Use a default heap size if heap size was not defined. */ + __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__; + + /* Use a default stack size if stack size was not defined. */ + __stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 4K; + + /* Read-only sections, merged into text segment: */ + PROVIDE (__executable_start = 0x80000000); . = 0x80000000; + .interp : { *(.interp) } >FLASH AT>FLASH :FLASH + .reset : { *(.reset) } >FLASH AT>FLASH :FLASH + .hash : { *(.hash) } >FLASH AT>FLASH :FLASH + .dynsym : { *(.dynsym) } >FLASH AT>FLASH :FLASH + .dynstr : { *(.dynstr) } >FLASH AT>FLASH :FLASH + .gnu.version : { *(.gnu.version) } >FLASH AT>FLASH :FLASH + .gnu.version_d : { *(.gnu.version_d) } >FLASH AT>FLASH :FLASH + .gnu.version_r : { *(.gnu.version_r) } >FLASH AT>FLASH :FLASH + .rel.init : { *(.rel.init) } >FLASH AT>FLASH :FLASH + .rela.init : { *(.rela.init) } >FLASH AT>FLASH :FLASH + .rel.text : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH + .rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH + .rel.fini : { *(.rel.fini) } >FLASH AT>FLASH :FLASH + .rela.fini : { *(.rela.fini) } >FLASH AT>FLASH :FLASH + .rel.rodata : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rela.rodata : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rel.data.rel.ro : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH + .rela.data.rel.ro : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH + .rel.data : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH + .rela.data : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH + .rel.tdata : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH + .rela.tdata : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH + .rel.tbss : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH + .rela.tbss : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH + .rel.ctors : { *(.rel.ctors) } >FLASH AT>FLASH :FLASH + .rela.ctors : { *(.rela.ctors) } >FLASH AT>FLASH :FLASH + .rel.dtors : { *(.rel.dtors) } >FLASH AT>FLASH :FLASH + .rela.dtors : { *(.rela.dtors) } >FLASH AT>FLASH :FLASH + .rel.got : { *(.rel.got) } >FLASH AT>FLASH :FLASH + .rela.got : { *(.rela.got) } >FLASH AT>FLASH :FLASH + .rel.bss : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH + .rela.bss : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH + .rel.plt : { *(.rel.plt) } >FLASH AT>FLASH :FLASH + .rela.plt : { *(.rela.plt) } >FLASH AT>FLASH :FLASH + .init : + { + KEEP (*(.init)) + } >FLASH AT>FLASH :FLASH =0xd703d703 + .plt : { *(.plt) } >FLASH AT>FLASH :FLASH + .text : + { + *(.text .stub .text.* .gnu.linkonce.t.*) + KEEP (*(.text.*personality*)) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + } >FLASH AT>FLASH :FLASH =0xd703d703 + .fini : + { + KEEP (*(.fini)) + } >FLASH AT>FLASH :FLASH =0xd703d703 + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + .rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rodata1 : { *(.rodata1) } >FLASH AT>FLASH :FLASH + .eh_frame_hdr : { *(.eh_frame_hdr) } >FLASH AT>FLASH :FLASH + .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH :FLASH + .gcc_except_table : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH :FLASH + .lalign : { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH :FLASH + . = ORIGIN(INTRAM); + .dalign : { . = ALIGN(8); PROVIDE(_data = .); } >INTRAM AT>INTRAM :INTRAM + /* Exception handling */ + .eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) } >INTRAM AT>FLASH :FLASH + .gcc_except_table : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >INTRAM AT>FLASH :FLASH + /* Thread Local Storage sections */ + .tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >INTRAM AT>FLASH :FLASH + .tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >INTRAM AT>FLASH :FLASH + /* Ensure the __preinit_array_start label is properly aligned. We + could instead move the label definition inside the section, but + the linker would then create the section even if it turns out to + be empty, which isn't pretty. */ + PROVIDE (__preinit_array_start = ALIGN(32 / 8)); + .preinit_array : { KEEP (*(.preinit_array)) } >INTRAM AT>FLASH :FLASH + PROVIDE (__preinit_array_end = .); + PROVIDE (__init_array_start = .); + .init_array : { KEEP (*(.init_array)) } >INTRAM AT>FLASH :FLASH + PROVIDE (__init_array_end = .); + PROVIDE (__fini_array_start = .); + .fini_array : { KEEP (*(.fini_array)) } >INTRAM AT>FLASH :FLASH + PROVIDE (__fini_array_end = .); + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin*.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >INTRAM AT>FLASH :FLASH + .dtors : + { + KEEP (*crtbegin*.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >INTRAM AT>FLASH :FLASH + .jcr : { KEEP (*(.jcr)) } >INTRAM AT>FLASH :FLASH + .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >INTRAM AT>FLASH :FLASH + .dynamic : { *(.dynamic) } >INTRAM AT>FLASH :FLASH + .got : { *(.got.plt) *(.got) } >INTRAM AT>FLASH :FLASH + .data : + { + *(.data .data.* .gnu.linkonce.d.*) + KEEP (*(.gnu.linkonce.d.*personality*)) + SORT(CONSTRUCTORS) + } >INTRAM AT>FLASH :FLASH + .data1 : { *(.data1) } >INTRAM AT>FLASH :FLASH + .balign : { . = ALIGN(8); _edata = .; } >INTRAM AT>FLASH :FLASH + _edata = .; + PROVIDE (edata = .); + __bss_start = .; + .bss : + { + *(.dynbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + /* Align here to ensure that the .bss section occupies space up to + _end. Align after .bss to ensure correct alignment even if the + .bss section disappears because there are no input sections. */ + . = ALIGN(8); + } >INTRAM AT>INTRAM :INTRAM + . = ALIGN(8); + _end = .; + PROVIDE (end = .); + __heap_start__ = ALIGN(8); + .heap : + { + *(.heap) + . = (__heap_size__ == __max_heap_size__) ? + ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ - ABSOLUTE(.) : + __heap_size__; + } >INTRAM AT>INTRAM :INTRAM + __heap_end__ = .; + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + .stack ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ : + { + _stack = .; + *(.stack) + . = __stack_size__; + _estack = .; + } >INTRAM AT>INTRAM :INTRAM + .userpage : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE :USERPAGE + .factorypage : { *(.factorypage .factorypage.*) } >FACTORYPAGE AT>FACTORYPAGE :FACTORYPAGE + /DISCARD/ : { *(.note.GNU-stack) } +} diff --git a/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/1512/IAR/lnkuc3a1512.xcl b/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/1512/IAR/lnkuc3a1512.xcl new file mode 100644 index 000000000..33ec1d367 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/1512/IAR/lnkuc3a1512.xcl @@ -0,0 +1,138 @@ +/****************************************************************************** + * AVR32 AT32UC3A1512 XLINK command file for AVR32 IAR C/C++ Compiler. + * + * The assumed memory layout is the one of the AT32UC3A1512: + * + * Start Stop Name Type + * ---------- ---------- ----- -------------- + * 0x00000000 0x0000FFFF SRAM RAM + * 0x80000000 0x8007FFFF FLASH FLASH + * + * Usage: xlink your_file(s) -f xcl-file libraries + * + * - Compiler: IAR EWAVR32 + * - Supported devices: AVR32 AT32UC3A1512 + * + * - author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +/************************************************************************/ +/* The following segments are defined in this link file: */ +/* */ +/* Code segments */ +/* CODE32 -- Program code used by __code32 functions. */ +/* RESET -- Reset code. */ +/* EVSEG -- Exception vector handlers. */ +/* */ +/* Constant segments */ +/* INITTAB -- Segment initializer table. */ +/* DIFUNCT -- Dynamic initialization vector used by C++. */ +/* SWITCH -- Switch tables. */ +/* ACTAB -- Table of pointers to acall functions. */ +/* */ +/* DATA21_ID -- Initialization data for DATA21_I. */ +/* DATA32_ID -- Initialization data for DATA32_I. */ +/* DATA32_C -- Constant __data32 data. */ +/* */ +/* CHECKSUM -- Checksum segment. */ +/* */ +/* Data segments */ +/* DATA21_I -- Initialized __data21 data with non-zero */ +/* initial value. */ +/* DATA32_I -- Initialized __data32 data with non-zero */ +/* initial value. */ +/* DATA21_Z -- Initialized __data21 data with zero initial value. */ +/* DATA32_Z -- Initialized __data32 data with zero initial value. */ +/* DATA21_N -- Non-initialized __data21. */ +/* DATA32_N -- Non-initialized __data32. */ +/* SSTACK -- The system stack. */ +/* CSTACK -- The application stack. */ +/* HEAP -- The heap used by malloc and free. */ +/* */ +/************************************************************************/ + +/************************************************************************/ +/* Define CPU */ +/************************************************************************/ + +-cavr32 + +// Declare the IPR0 memory location +-DIPR0=FFFF0800 + +/************************************************************************/ +/* Reset code is located at address 0x80000000 and up. */ +/************************************************************************/ + +-Z(CODE)RESET=80000000-8007FFFF + +/************************************************************************/ +/* The exception handler code is located at address 0x80000000 */ +/* and up. Make sure that the exception table gets properly */ +/* allocated. By using the special -Z@ allocation primitive, the */ +/* placement is guaranteed to be at _EVBASE and onwards. */ +/************************************************************************/ + +-Z@(CODE)EVTAB=80004000-8007FFFF +-Z@(CODE)EV100=80004100-8007FFFF +-P(CODE)EVSEG=80004000-8007FFFF + +/************************************************************************/ +/* Allocate code and const segments. */ +/************************************************************************/ + +-P(CODE)CODE32=80000000-8007FFFF +-P(CONST)DATA32_C=80000000-8007FFFF + +// Initializers +-Z(CONST)INITTAB,DIFUNCT=80000000-8007FFFF +-Z(CONST)CHECKSUM,SWITCH=80000000-8007FFFF +-Z(CONST)DATA21_ID,DATA32_ID=80000000-8007FFFF + +-Z(CONST)ACTAB,HTAB=80000000-8007FFFF + +/************************************************************************/ +/* Allocate the read/write segments that are mapped to RAM. */ +/************************************************************************/ + +-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-0000FFFF +-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-0000FFFF +-Z(DATA)TRACEBUFFER=00000004-0000FFFF + +-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-0000FFFF +-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-0000FFFF +-Z(DATA)HEAP+_HEAP_SIZE=00000004-0000FFFF + +/************************************************************************/ +/* End of File */ +/************************************************************************/ diff --git a/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/0128/GCC/link_uc3b0128.lds b/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/0128/GCC/link_uc3b0128.lds new file mode 100644 index 000000000..cf3a8db14 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/0128/GCC/link_uc3b0128.lds @@ -0,0 +1,263 @@ +/****************************************************************************** + * AVR32 AT32UC3B0128 GNU LD script file. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: AVR32 AT32UC3B0128 + * + * - author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32") + +OUTPUT_ARCH(avr32:uc) + +ENTRY(_start) + +MEMORY +{ + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00020000 + INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x00007FFC + USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200 + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 0x00000200 +} + +PHDRS +{ + FLASH PT_LOAD; + INTRAM PT_NULL; + USERPAGE PT_LOAD; + FACTORYPAGE PT_LOAD; +} + +SECTIONS +{ + /* If this heap size is selected, all the INTRAM space from the end of the + data area to the beginning of the stack will be allocated for the heap. */ + __max_heap_size__ = -1; + + /* Use a default heap size if heap size was not defined. */ + __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__; + + /* Use a default stack size if stack size was not defined. */ + __stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 4K; + + /* Read-only sections, merged into text segment: */ + PROVIDE (__executable_start = 0x80000000); . = 0x80000000; + .interp : { *(.interp) } >FLASH AT>FLASH :FLASH + .reset : { *(.reset) } >FLASH AT>FLASH :FLASH + .hash : { *(.hash) } >FLASH AT>FLASH :FLASH + .dynsym : { *(.dynsym) } >FLASH AT>FLASH :FLASH + .dynstr : { *(.dynstr) } >FLASH AT>FLASH :FLASH + .gnu.version : { *(.gnu.version) } >FLASH AT>FLASH :FLASH + .gnu.version_d : { *(.gnu.version_d) } >FLASH AT>FLASH :FLASH + .gnu.version_r : { *(.gnu.version_r) } >FLASH AT>FLASH :FLASH + .rel.init : { *(.rel.init) } >FLASH AT>FLASH :FLASH + .rela.init : { *(.rela.init) } >FLASH AT>FLASH :FLASH + .rel.text : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH + .rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH + .rel.fini : { *(.rel.fini) } >FLASH AT>FLASH :FLASH + .rela.fini : { *(.rela.fini) } >FLASH AT>FLASH :FLASH + .rel.rodata : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rela.rodata : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rel.data.rel.ro : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH + .rela.data.rel.ro : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH + .rel.data : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH + .rela.data : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH + .rel.tdata : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH + .rela.tdata : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH + .rel.tbss : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH + .rela.tbss : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH + .rel.ctors : { *(.rel.ctors) } >FLASH AT>FLASH :FLASH + .rela.ctors : { *(.rela.ctors) } >FLASH AT>FLASH :FLASH + .rel.dtors : { *(.rel.dtors) } >FLASH AT>FLASH :FLASH + .rela.dtors : { *(.rela.dtors) } >FLASH AT>FLASH :FLASH + .rel.got : { *(.rel.got) } >FLASH AT>FLASH :FLASH + .rela.got : { *(.rela.got) } >FLASH AT>FLASH :FLASH + .rel.bss : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH + .rela.bss : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH + .rel.plt : { *(.rel.plt) } >FLASH AT>FLASH :FLASH + .rela.plt : { *(.rela.plt) } >FLASH AT>FLASH :FLASH + .init : + { + KEEP (*(.init)) + } >FLASH AT>FLASH :FLASH =0xd703d703 + .plt : { *(.plt) } >FLASH AT>FLASH :FLASH + .text : + { + *(.text .stub .text.* .gnu.linkonce.t.*) + KEEP (*(.text.*personality*)) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + } >FLASH AT>FLASH :FLASH =0xd703d703 + .fini : + { + KEEP (*(.fini)) + } >FLASH AT>FLASH :FLASH =0xd703d703 + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + .rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rodata1 : { *(.rodata1) } >FLASH AT>FLASH :FLASH + .eh_frame_hdr : { *(.eh_frame_hdr) } >FLASH AT>FLASH :FLASH + .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH :FLASH + .gcc_except_table : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH :FLASH + .lalign : { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH :FLASH + . = ORIGIN(INTRAM); + .dalign : { . = ALIGN(8); PROVIDE(_data = .); } >INTRAM AT>INTRAM :INTRAM + /* Exception handling */ + .eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) } >INTRAM AT>FLASH :FLASH + .gcc_except_table : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >INTRAM AT>FLASH :FLASH + /* Thread Local Storage sections */ + .tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >INTRAM AT>FLASH :FLASH + .tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >INTRAM AT>FLASH :FLASH + /* Ensure the __preinit_array_start label is properly aligned. We + could instead move the label definition inside the section, but + the linker would then create the section even if it turns out to + be empty, which isn't pretty. */ + PROVIDE (__preinit_array_start = ALIGN(32 / 8)); + .preinit_array : { KEEP (*(.preinit_array)) } >INTRAM AT>FLASH :FLASH + PROVIDE (__preinit_array_end = .); + PROVIDE (__init_array_start = .); + .init_array : { KEEP (*(.init_array)) } >INTRAM AT>FLASH :FLASH + PROVIDE (__init_array_end = .); + PROVIDE (__fini_array_start = .); + .fini_array : { KEEP (*(.fini_array)) } >INTRAM AT>FLASH :FLASH + PROVIDE (__fini_array_end = .); + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin*.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >INTRAM AT>FLASH :FLASH + .dtors : + { + KEEP (*crtbegin*.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >INTRAM AT>FLASH :FLASH + .jcr : { KEEP (*(.jcr)) } >INTRAM AT>FLASH :FLASH + .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >INTRAM AT>FLASH :FLASH + .dynamic : { *(.dynamic) } >INTRAM AT>FLASH :FLASH + .got : { *(.got.plt) *(.got) } >INTRAM AT>FLASH :FLASH + .data : + { + *(.data .data.* .gnu.linkonce.d.*) + KEEP (*(.gnu.linkonce.d.*personality*)) + SORT(CONSTRUCTORS) + } >INTRAM AT>FLASH :FLASH + .data1 : { *(.data1) } >INTRAM AT>FLASH :FLASH + .balign : { . = ALIGN(8); _edata = .; } >INTRAM AT>FLASH :FLASH + _edata = .; + PROVIDE (edata = .); + __bss_start = .; + .bss : + { + *(.dynbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + /* Align here to ensure that the .bss section occupies space up to + _end. Align after .bss to ensure correct alignment even if the + .bss section disappears because there are no input sections. */ + . = ALIGN(8); + } >INTRAM AT>INTRAM :INTRAM + . = ALIGN(8); + _end = .; + PROVIDE (end = .); + __heap_start__ = ALIGN(8); + .heap : + { + *(.heap) + . = (__heap_size__ == __max_heap_size__) ? + ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ - ABSOLUTE(.) : + __heap_size__; + } >INTRAM AT>INTRAM :INTRAM + __heap_end__ = .; + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + .stack ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ : + { + _stack = .; + *(.stack) + . = __stack_size__; + _estack = .; + } >INTRAM AT>INTRAM :INTRAM + .userpage : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE :USERPAGE + .factorypage : { *(.factorypage .factorypage.*) } >FACTORYPAGE AT>FACTORYPAGE :FACTORYPAGE + /DISCARD/ : { *(.note.GNU-stack) } +} diff --git a/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/0128/IAR/lnkuc3b0128.xcl b/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/0128/IAR/lnkuc3b0128.xcl new file mode 100644 index 000000000..f45cf7392 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/0128/IAR/lnkuc3b0128.xcl @@ -0,0 +1,138 @@ +/****************************************************************************** + * AVR32 AT32UC3B0128 XLINK command file for AVR32 IAR C/C++ Compiler. + * + * The assumed memory layout is the one of the AT32UC3B0128: + * + * Start Stop Name Type + * ---------- ---------- ----- -------------- + * 0x00000000 0x00007FFF SRAM RAM + * 0x80000000 0x8001FFFF FLASH FLASH + * + * Usage: xlink your_file(s) -f xcl-file libraries + * + * - Compiler: IAR EWAVR32 + * - Supported devices: AVR32 AT32UC3B0128 + * + * - author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +/************************************************************************/ +/* The following segments are defined in this link file: */ +/* */ +/* Code segments */ +/* CODE32 -- Program code used by __code32 functions. */ +/* RESET -- Reset code. */ +/* EVSEG -- Exception vector handlers. */ +/* */ +/* Constant segments */ +/* INITTAB -- Segment initializer table. */ +/* DIFUNCT -- Dynamic initialization vector used by C++. */ +/* SWITCH -- Switch tables. */ +/* ACTAB -- Table of pointers to acall functions. */ +/* */ +/* DATA21_ID -- Initialization data for DATA21_I. */ +/* DATA32_ID -- Initialization data for DATA32_I. */ +/* DATA32_C -- Constant __data32 data. */ +/* */ +/* CHECKSUM -- Checksum segment. */ +/* */ +/* Data segments */ +/* DATA21_I -- Initialized __data21 data with non-zero */ +/* initial value. */ +/* DATA32_I -- Initialized __data32 data with non-zero */ +/* initial value. */ +/* DATA21_Z -- Initialized __data21 data with zero initial value. */ +/* DATA32_Z -- Initialized __data32 data with zero initial value. */ +/* DATA21_N -- Non-initialized __data21. */ +/* DATA32_N -- Non-initialized __data32. */ +/* SSTACK -- The system stack. */ +/* CSTACK -- The application stack. */ +/* HEAP -- The heap used by malloc and free. */ +/* */ +/************************************************************************/ + +/************************************************************************/ +/* Define CPU */ +/************************************************************************/ + +-cavr32 + +// Declare the IPR0 memory location +-DIPR0=FFFF0800 + +/************************************************************************/ +/* Reset code is located at address 0x80000000 and up. */ +/************************************************************************/ + +-Z(CODE)RESET=80000000-8001FFFF + +/************************************************************************/ +/* The exception handler code is located at address 0x80000000 */ +/* and up. Make sure that the exception table gets properly */ +/* allocated. By using the special -Z@ allocation primitive, the */ +/* placement is guaranteed to be at _EVBASE and onwards. */ +/************************************************************************/ + +-Z@(CODE)EVTAB=80004000-8001FFFF +-Z@(CODE)EV100=80004100-8001FFFF +-P(CODE)EVSEG=80004000-8001FFFF + +/************************************************************************/ +/* Allocate code and const segments. */ +/************************************************************************/ + +-P(CODE)CODE32=80000000-8001FFFF +-P(CONST)DATA32_C=80000000-8001FFFF + +// Initializers +-Z(CONST)INITTAB,DIFUNCT=80000000-8001FFFF +-Z(CONST)CHECKSUM,SWITCH=80000000-8001FFFF +-Z(CONST)DATA21_ID,DATA32_ID=80000000-8001FFFF + +-Z(CONST)ACTAB,HTAB=80000000-8001FFFF + +/************************************************************************/ +/* Allocate the read/write segments that are mapped to RAM. */ +/************************************************************************/ + +-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-00007FFF +-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-00007FFF +-Z(DATA)TRACEBUFFER=00000004-00007FFF + +-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-00007FFF +-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-00007FFF +-Z(DATA)HEAP+_HEAP_SIZE=00000004-00007FFF + +/************************************************************************/ +/* End of File */ +/************************************************************************/ diff --git a/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/0256/GCC/link_uc3b0256.lds b/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/0256/GCC/link_uc3b0256.lds new file mode 100644 index 000000000..e23901562 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/0256/GCC/link_uc3b0256.lds @@ -0,0 +1,263 @@ +/****************************************************************************** + * AVR32 AT32UC3B0256 GNU LD script file. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: AVR32 AT32UC3B0256 + * + * - author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32") + +OUTPUT_ARCH(avr32:uc) + +ENTRY(_start) + +MEMORY +{ + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00040000 + INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x00007FFC + USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200 + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 0x00000200 +} + +PHDRS +{ + FLASH PT_LOAD; + INTRAM PT_NULL; + USERPAGE PT_LOAD; + FACTORYPAGE PT_LOAD; +} + +SECTIONS +{ + /* If this heap size is selected, all the INTRAM space from the end of the + data area to the beginning of the stack will be allocated for the heap. */ + __max_heap_size__ = -1; + + /* Use a default heap size if heap size was not defined. */ + __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__; + + /* Use a default stack size if stack size was not defined. */ + __stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 4K; + + /* Read-only sections, merged into text segment: */ + PROVIDE (__executable_start = 0x80000000); . = 0x80000000; + .interp : { *(.interp) } >FLASH AT>FLASH :FLASH + .reset : { *(.reset) } >FLASH AT>FLASH :FLASH + .hash : { *(.hash) } >FLASH AT>FLASH :FLASH + .dynsym : { *(.dynsym) } >FLASH AT>FLASH :FLASH + .dynstr : { *(.dynstr) } >FLASH AT>FLASH :FLASH + .gnu.version : { *(.gnu.version) } >FLASH AT>FLASH :FLASH + .gnu.version_d : { *(.gnu.version_d) } >FLASH AT>FLASH :FLASH + .gnu.version_r : { *(.gnu.version_r) } >FLASH AT>FLASH :FLASH + .rel.init : { *(.rel.init) } >FLASH AT>FLASH :FLASH + .rela.init : { *(.rela.init) } >FLASH AT>FLASH :FLASH + .rel.text : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH + .rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH + .rel.fini : { *(.rel.fini) } >FLASH AT>FLASH :FLASH + .rela.fini : { *(.rela.fini) } >FLASH AT>FLASH :FLASH + .rel.rodata : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rela.rodata : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rel.data.rel.ro : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH + .rela.data.rel.ro : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH + .rel.data : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH + .rela.data : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH + .rel.tdata : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH + .rela.tdata : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH + .rel.tbss : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH + .rela.tbss : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH + .rel.ctors : { *(.rel.ctors) } >FLASH AT>FLASH :FLASH + .rela.ctors : { *(.rela.ctors) } >FLASH AT>FLASH :FLASH + .rel.dtors : { *(.rel.dtors) } >FLASH AT>FLASH :FLASH + .rela.dtors : { *(.rela.dtors) } >FLASH AT>FLASH :FLASH + .rel.got : { *(.rel.got) } >FLASH AT>FLASH :FLASH + .rela.got : { *(.rela.got) } >FLASH AT>FLASH :FLASH + .rel.bss : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH + .rela.bss : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH + .rel.plt : { *(.rel.plt) } >FLASH AT>FLASH :FLASH + .rela.plt : { *(.rela.plt) } >FLASH AT>FLASH :FLASH + .init : + { + KEEP (*(.init)) + } >FLASH AT>FLASH :FLASH =0xd703d703 + .plt : { *(.plt) } >FLASH AT>FLASH :FLASH + .text : + { + *(.text .stub .text.* .gnu.linkonce.t.*) + KEEP (*(.text.*personality*)) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + } >FLASH AT>FLASH :FLASH =0xd703d703 + .fini : + { + KEEP (*(.fini)) + } >FLASH AT>FLASH :FLASH =0xd703d703 + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + .rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rodata1 : { *(.rodata1) } >FLASH AT>FLASH :FLASH + .eh_frame_hdr : { *(.eh_frame_hdr) } >FLASH AT>FLASH :FLASH + .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH :FLASH + .gcc_except_table : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH :FLASH + .lalign : { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH :FLASH + . = ORIGIN(INTRAM); + .dalign : { . = ALIGN(8); PROVIDE(_data = .); } >INTRAM AT>INTRAM :INTRAM + /* Exception handling */ + .eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) } >INTRAM AT>FLASH :FLASH + .gcc_except_table : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >INTRAM AT>FLASH :FLASH + /* Thread Local Storage sections */ + .tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >INTRAM AT>FLASH :FLASH + .tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >INTRAM AT>FLASH :FLASH + /* Ensure the __preinit_array_start label is properly aligned. We + could instead move the label definition inside the section, but + the linker would then create the section even if it turns out to + be empty, which isn't pretty. */ + PROVIDE (__preinit_array_start = ALIGN(32 / 8)); + .preinit_array : { KEEP (*(.preinit_array)) } >INTRAM AT>FLASH :FLASH + PROVIDE (__preinit_array_end = .); + PROVIDE (__init_array_start = .); + .init_array : { KEEP (*(.init_array)) } >INTRAM AT>FLASH :FLASH + PROVIDE (__init_array_end = .); + PROVIDE (__fini_array_start = .); + .fini_array : { KEEP (*(.fini_array)) } >INTRAM AT>FLASH :FLASH + PROVIDE (__fini_array_end = .); + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin*.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >INTRAM AT>FLASH :FLASH + .dtors : + { + KEEP (*crtbegin*.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >INTRAM AT>FLASH :FLASH + .jcr : { KEEP (*(.jcr)) } >INTRAM AT>FLASH :FLASH + .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >INTRAM AT>FLASH :FLASH + .dynamic : { *(.dynamic) } >INTRAM AT>FLASH :FLASH + .got : { *(.got.plt) *(.got) } >INTRAM AT>FLASH :FLASH + .data : + { + *(.data .data.* .gnu.linkonce.d.*) + KEEP (*(.gnu.linkonce.d.*personality*)) + SORT(CONSTRUCTORS) + } >INTRAM AT>FLASH :FLASH + .data1 : { *(.data1) } >INTRAM AT>FLASH :FLASH + .balign : { . = ALIGN(8); _edata = .; } >INTRAM AT>FLASH :FLASH + _edata = .; + PROVIDE (edata = .); + __bss_start = .; + .bss : + { + *(.dynbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + /* Align here to ensure that the .bss section occupies space up to + _end. Align after .bss to ensure correct alignment even if the + .bss section disappears because there are no input sections. */ + . = ALIGN(8); + } >INTRAM AT>INTRAM :INTRAM + . = ALIGN(8); + _end = .; + PROVIDE (end = .); + __heap_start__ = ALIGN(8); + .heap : + { + *(.heap) + . = (__heap_size__ == __max_heap_size__) ? + ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ - ABSOLUTE(.) : + __heap_size__; + } >INTRAM AT>INTRAM :INTRAM + __heap_end__ = .; + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + .stack ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ : + { + _stack = .; + *(.stack) + . = __stack_size__; + _estack = .; + } >INTRAM AT>INTRAM :INTRAM + .userpage : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE :USERPAGE + .factorypage : { *(.factorypage .factorypage.*) } >FACTORYPAGE AT>FACTORYPAGE :FACTORYPAGE + /DISCARD/ : { *(.note.GNU-stack) } +} diff --git a/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/0256/IAR/lnkuc3b0256.xcl b/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/0256/IAR/lnkuc3b0256.xcl new file mode 100644 index 000000000..46fcbea95 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/0256/IAR/lnkuc3b0256.xcl @@ -0,0 +1,138 @@ +/****************************************************************************** + * AVR32 AT32UC3B0256 XLINK command file for AVR32 IAR C/C++ Compiler. + * + * The assumed memory layout is the one of the AT32UC3B0256: + * + * Start Stop Name Type + * ---------- ---------- ----- -------------- + * 0x00000000 0x00007FFF SRAM RAM + * 0x80000000 0x8003FFFF FLASH FLASH + * + * Usage: xlink your_file(s) -f xcl-file libraries + * + * - Compiler: IAR EWAVR32 + * - Supported devices: AVR32 AT32UC3B0256 + * + * - author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +/************************************************************************/ +/* The following segments are defined in this link file: */ +/* */ +/* Code segments */ +/* CODE32 -- Program code used by __code32 functions. */ +/* RESET -- Reset code. */ +/* EVSEG -- Exception vector handlers. */ +/* */ +/* Constant segments */ +/* INITTAB -- Segment initializer table. */ +/* DIFUNCT -- Dynamic initialization vector used by C++. */ +/* SWITCH -- Switch tables. */ +/* ACTAB -- Table of pointers to acall functions. */ +/* */ +/* DATA21_ID -- Initialization data for DATA21_I. */ +/* DATA32_ID -- Initialization data for DATA32_I. */ +/* DATA32_C -- Constant __data32 data. */ +/* */ +/* CHECKSUM -- Checksum segment. */ +/* */ +/* Data segments */ +/* DATA21_I -- Initialized __data21 data with non-zero */ +/* initial value. */ +/* DATA32_I -- Initialized __data32 data with non-zero */ +/* initial value. */ +/* DATA21_Z -- Initialized __data21 data with zero initial value. */ +/* DATA32_Z -- Initialized __data32 data with zero initial value. */ +/* DATA21_N -- Non-initialized __data21. */ +/* DATA32_N -- Non-initialized __data32. */ +/* SSTACK -- The system stack. */ +/* CSTACK -- The application stack. */ +/* HEAP -- The heap used by malloc and free. */ +/* */ +/************************************************************************/ + +/************************************************************************/ +/* Define CPU */ +/************************************************************************/ + +-cavr32 + +// Declare the IPR0 memory location +-DIPR0=FFFF0800 + +/************************************************************************/ +/* Reset code is located at address 0x80000000 and up. */ +/************************************************************************/ + +-Z(CODE)RESET=80000000-8003FFFF + +/************************************************************************/ +/* The exception handler code is located at address 0x80000000 */ +/* and up. Make sure that the exception table gets properly */ +/* allocated. By using the special -Z@ allocation primitive, the */ +/* placement is guaranteed to be at _EVBASE and onwards. */ +/************************************************************************/ + +-Z@(CODE)EVTAB=80004000-8003FFFF +-Z@(CODE)EV100=80004100-8003FFFF +-P(CODE)EVSEG=80004000-8003FFFF + +/************************************************************************/ +/* Allocate code and const segments. */ +/************************************************************************/ + +-P(CODE)CODE32=80000000-8003FFFF +-P(CONST)DATA32_C=80000000-8003FFFF + +// Initializers +-Z(CONST)INITTAB,DIFUNCT=80000000-8003FFFF +-Z(CONST)CHECKSUM,SWITCH=80000000-8003FFFF +-Z(CONST)DATA21_ID,DATA32_ID=80000000-8003FFFF + +-Z(CONST)ACTAB,HTAB=80000000-8003FFFF + +/************************************************************************/ +/* Allocate the read/write segments that are mapped to RAM. */ +/************************************************************************/ + +-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-00007FFF +-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-00007FFF +-Z(DATA)TRACEBUFFER=00000004-00007FFF + +-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-00007FFF +-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-00007FFF +-Z(DATA)HEAP+_HEAP_SIZE=00000004-00007FFF + +/************************************************************************/ +/* End of File */ +/************************************************************************/ diff --git a/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/064/GCC/link_uc3b064.lds b/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/064/GCC/link_uc3b064.lds new file mode 100644 index 000000000..579a3908c --- /dev/null +++ b/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/064/GCC/link_uc3b064.lds @@ -0,0 +1,263 @@ +/****************************************************************************** + * AVR32 AT32UC3B064 GNU LD script file. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: AVR32 AT32UC3B064 + * + * - author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32") + +OUTPUT_ARCH(avr32:uc) + +ENTRY(_start) + +MEMORY +{ + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00010000 + INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x00003FFC + USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200 + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 0x00000200 +} + +PHDRS +{ + FLASH PT_LOAD; + INTRAM PT_NULL; + USERPAGE PT_LOAD; + FACTORYPAGE PT_LOAD; +} + +SECTIONS +{ + /* If this heap size is selected, all the INTRAM space from the end of the + data area to the beginning of the stack will be allocated for the heap. */ + __max_heap_size__ = -1; + + /* Use a default heap size if heap size was not defined. */ + __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__; + + /* Use a default stack size if stack size was not defined. */ + __stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 4K; + + /* Read-only sections, merged into text segment: */ + PROVIDE (__executable_start = 0x80000000); . = 0x80000000; + .interp : { *(.interp) } >FLASH AT>FLASH :FLASH + .reset : { *(.reset) } >FLASH AT>FLASH :FLASH + .hash : { *(.hash) } >FLASH AT>FLASH :FLASH + .dynsym : { *(.dynsym) } >FLASH AT>FLASH :FLASH + .dynstr : { *(.dynstr) } >FLASH AT>FLASH :FLASH + .gnu.version : { *(.gnu.version) } >FLASH AT>FLASH :FLASH + .gnu.version_d : { *(.gnu.version_d) } >FLASH AT>FLASH :FLASH + .gnu.version_r : { *(.gnu.version_r) } >FLASH AT>FLASH :FLASH + .rel.init : { *(.rel.init) } >FLASH AT>FLASH :FLASH + .rela.init : { *(.rela.init) } >FLASH AT>FLASH :FLASH + .rel.text : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH + .rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH + .rel.fini : { *(.rel.fini) } >FLASH AT>FLASH :FLASH + .rela.fini : { *(.rela.fini) } >FLASH AT>FLASH :FLASH + .rel.rodata : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rela.rodata : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rel.data.rel.ro : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH + .rela.data.rel.ro : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH + .rel.data : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH + .rela.data : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH + .rel.tdata : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH + .rela.tdata : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH + .rel.tbss : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH + .rela.tbss : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH + .rel.ctors : { *(.rel.ctors) } >FLASH AT>FLASH :FLASH + .rela.ctors : { *(.rela.ctors) } >FLASH AT>FLASH :FLASH + .rel.dtors : { *(.rel.dtors) } >FLASH AT>FLASH :FLASH + .rela.dtors : { *(.rela.dtors) } >FLASH AT>FLASH :FLASH + .rel.got : { *(.rel.got) } >FLASH AT>FLASH :FLASH + .rela.got : { *(.rela.got) } >FLASH AT>FLASH :FLASH + .rel.bss : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH + .rela.bss : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH + .rel.plt : { *(.rel.plt) } >FLASH AT>FLASH :FLASH + .rela.plt : { *(.rela.plt) } >FLASH AT>FLASH :FLASH + .init : + { + KEEP (*(.init)) + } >FLASH AT>FLASH :FLASH =0xd703d703 + .plt : { *(.plt) } >FLASH AT>FLASH :FLASH + .text : + { + *(.text .stub .text.* .gnu.linkonce.t.*) + KEEP (*(.text.*personality*)) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + } >FLASH AT>FLASH :FLASH =0xd703d703 + .fini : + { + KEEP (*(.fini)) + } >FLASH AT>FLASH :FLASH =0xd703d703 + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + .rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rodata1 : { *(.rodata1) } >FLASH AT>FLASH :FLASH + .eh_frame_hdr : { *(.eh_frame_hdr) } >FLASH AT>FLASH :FLASH + .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH :FLASH + .gcc_except_table : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH :FLASH + .lalign : { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH :FLASH + . = ORIGIN(INTRAM); + .dalign : { . = ALIGN(8); PROVIDE(_data = .); } >INTRAM AT>INTRAM :INTRAM + /* Exception handling */ + .eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) } >INTRAM AT>FLASH :FLASH + .gcc_except_table : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >INTRAM AT>FLASH :FLASH + /* Thread Local Storage sections */ + .tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >INTRAM AT>FLASH :FLASH + .tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >INTRAM AT>FLASH :FLASH + /* Ensure the __preinit_array_start label is properly aligned. We + could instead move the label definition inside the section, but + the linker would then create the section even if it turns out to + be empty, which isn't pretty. */ + PROVIDE (__preinit_array_start = ALIGN(32 / 8)); + .preinit_array : { KEEP (*(.preinit_array)) } >INTRAM AT>FLASH :FLASH + PROVIDE (__preinit_array_end = .); + PROVIDE (__init_array_start = .); + .init_array : { KEEP (*(.init_array)) } >INTRAM AT>FLASH :FLASH + PROVIDE (__init_array_end = .); + PROVIDE (__fini_array_start = .); + .fini_array : { KEEP (*(.fini_array)) } >INTRAM AT>FLASH :FLASH + PROVIDE (__fini_array_end = .); + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin*.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >INTRAM AT>FLASH :FLASH + .dtors : + { + KEEP (*crtbegin*.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >INTRAM AT>FLASH :FLASH + .jcr : { KEEP (*(.jcr)) } >INTRAM AT>FLASH :FLASH + .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >INTRAM AT>FLASH :FLASH + .dynamic : { *(.dynamic) } >INTRAM AT>FLASH :FLASH + .got : { *(.got.plt) *(.got) } >INTRAM AT>FLASH :FLASH + .data : + { + *(.data .data.* .gnu.linkonce.d.*) + KEEP (*(.gnu.linkonce.d.*personality*)) + SORT(CONSTRUCTORS) + } >INTRAM AT>FLASH :FLASH + .data1 : { *(.data1) } >INTRAM AT>FLASH :FLASH + .balign : { . = ALIGN(8); _edata = .; } >INTRAM AT>FLASH :FLASH + _edata = .; + PROVIDE (edata = .); + __bss_start = .; + .bss : + { + *(.dynbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + /* Align here to ensure that the .bss section occupies space up to + _end. Align after .bss to ensure correct alignment even if the + .bss section disappears because there are no input sections. */ + . = ALIGN(8); + } >INTRAM AT>INTRAM :INTRAM + . = ALIGN(8); + _end = .; + PROVIDE (end = .); + __heap_start__ = ALIGN(8); + .heap : + { + *(.heap) + . = (__heap_size__ == __max_heap_size__) ? + ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ - ABSOLUTE(.) : + __heap_size__; + } >INTRAM AT>INTRAM :INTRAM + __heap_end__ = .; + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + .stack ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ : + { + _stack = .; + *(.stack) + . = __stack_size__; + _estack = .; + } >INTRAM AT>INTRAM :INTRAM + .userpage : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE :USERPAGE + .factorypage : { *(.factorypage .factorypage.*) } >FACTORYPAGE AT>FACTORYPAGE :FACTORYPAGE + /DISCARD/ : { *(.note.GNU-stack) } +} diff --git a/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/064/IAR/lnkuc3b064.xcl b/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/064/IAR/lnkuc3b064.xcl new file mode 100644 index 000000000..ab7b2ee17 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/064/IAR/lnkuc3b064.xcl @@ -0,0 +1,138 @@ +/****************************************************************************** + * AVR32 AT32UC3B064 XLINK command file for AVR32 IAR C/C++ Compiler. + * + * The assumed memory layout is the one of the AT32UC3B064: + * + * Start Stop Name Type + * ---------- ---------- ----- -------------- + * 0x00000000 0x00003FFF SRAM RAM + * 0x80000000 0x8000FFFF FLASH FLASH + * + * Usage: xlink your_file(s) -f xcl-file libraries + * + * - Compiler: IAR EWAVR32 + * - Supported devices: AVR32 AT32UC3B064 + * + * - author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +/************************************************************************/ +/* The following segments are defined in this link file: */ +/* */ +/* Code segments */ +/* CODE32 -- Program code used by __code32 functions. */ +/* RESET -- Reset code. */ +/* EVSEG -- Exception vector handlers. */ +/* */ +/* Constant segments */ +/* INITTAB -- Segment initializer table. */ +/* DIFUNCT -- Dynamic initialization vector used by C++. */ +/* SWITCH -- Switch tables. */ +/* ACTAB -- Table of pointers to acall functions. */ +/* */ +/* DATA21_ID -- Initialization data for DATA21_I. */ +/* DATA32_ID -- Initialization data for DATA32_I. */ +/* DATA32_C -- Constant __data32 data. */ +/* */ +/* CHECKSUM -- Checksum segment. */ +/* */ +/* Data segments */ +/* DATA21_I -- Initialized __data21 data with non-zero */ +/* initial value. */ +/* DATA32_I -- Initialized __data32 data with non-zero */ +/* initial value. */ +/* DATA21_Z -- Initialized __data21 data with zero initial value. */ +/* DATA32_Z -- Initialized __data32 data with zero initial value. */ +/* DATA21_N -- Non-initialized __data21. */ +/* DATA32_N -- Non-initialized __data32. */ +/* SSTACK -- The system stack. */ +/* CSTACK -- The application stack. */ +/* HEAP -- The heap used by malloc and free. */ +/* */ +/************************************************************************/ + +/************************************************************************/ +/* Define CPU */ +/************************************************************************/ + +-cavr32 + +// Declare the IPR0 memory location +-DIPR0=FFFF0800 + +/************************************************************************/ +/* Reset code is located at address 0x80000000 and up. */ +/************************************************************************/ + +-Z(CODE)RESET=80000000-8000FFFF + +/************************************************************************/ +/* The exception handler code is located at address 0x80000000 */ +/* and up. Make sure that the exception table gets properly */ +/* allocated. By using the special -Z@ allocation primitive, the */ +/* placement is guaranteed to be at _EVBASE and onwards. */ +/************************************************************************/ + +-Z@(CODE)EVTAB=80004000-8000FFFF +-Z@(CODE)EV100=80004100-8000FFFF +-P(CODE)EVSEG=80004000-8000FFFF + +/************************************************************************/ +/* Allocate code and const segments. */ +/************************************************************************/ + +-P(CODE)CODE32=80000000-8000FFFF +-P(CONST)DATA32_C=80000000-8000FFFF + +// Initializers +-Z(CONST)INITTAB,DIFUNCT=80000000-8000FFFF +-Z(CONST)CHECKSUM,SWITCH=80000000-8000FFFF +-Z(CONST)DATA21_ID,DATA32_ID=80000000-8000FFFF + +-Z(CONST)ACTAB,HTAB=80000000-8000FFFF + +/************************************************************************/ +/* Allocate the read/write segments that are mapped to RAM. */ +/************************************************************************/ + +-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-00003FFF +-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-00003FFF +-Z(DATA)TRACEBUFFER=00000004-00003FFF + +-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-00003FFF +-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-00003FFF +-Z(DATA)HEAP+_HEAP_SIZE=00000004-00003FFF + +/************************************************************************/ +/* End of File */ +/************************************************************************/ diff --git a/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/1128/GCC/link_uc3b1128.lds b/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/1128/GCC/link_uc3b1128.lds new file mode 100644 index 000000000..dba3d8df4 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/1128/GCC/link_uc3b1128.lds @@ -0,0 +1,263 @@ +/****************************************************************************** + * AVR32 AT32UC3B1128 GNU LD script file. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: AVR32 AT32UC3B1128 + * + * - author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32") + +OUTPUT_ARCH(avr32:uc) + +ENTRY(_start) + +MEMORY +{ + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00020000 + INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x00007FFC + USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200 + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 0x00000200 +} + +PHDRS +{ + FLASH PT_LOAD; + INTRAM PT_NULL; + USERPAGE PT_LOAD; + FACTORYPAGE PT_LOAD; +} + +SECTIONS +{ + /* If this heap size is selected, all the INTRAM space from the end of the + data area to the beginning of the stack will be allocated for the heap. */ + __max_heap_size__ = -1; + + /* Use a default heap size if heap size was not defined. */ + __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__; + + /* Use a default stack size if stack size was not defined. */ + __stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 4K; + + /* Read-only sections, merged into text segment: */ + PROVIDE (__executable_start = 0x80000000); . = 0x80000000; + .interp : { *(.interp) } >FLASH AT>FLASH :FLASH + .reset : { *(.reset) } >FLASH AT>FLASH :FLASH + .hash : { *(.hash) } >FLASH AT>FLASH :FLASH + .dynsym : { *(.dynsym) } >FLASH AT>FLASH :FLASH + .dynstr : { *(.dynstr) } >FLASH AT>FLASH :FLASH + .gnu.version : { *(.gnu.version) } >FLASH AT>FLASH :FLASH + .gnu.version_d : { *(.gnu.version_d) } >FLASH AT>FLASH :FLASH + .gnu.version_r : { *(.gnu.version_r) } >FLASH AT>FLASH :FLASH + .rel.init : { *(.rel.init) } >FLASH AT>FLASH :FLASH + .rela.init : { *(.rela.init) } >FLASH AT>FLASH :FLASH + .rel.text : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH + .rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH + .rel.fini : { *(.rel.fini) } >FLASH AT>FLASH :FLASH + .rela.fini : { *(.rela.fini) } >FLASH AT>FLASH :FLASH + .rel.rodata : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rela.rodata : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rel.data.rel.ro : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH + .rela.data.rel.ro : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH + .rel.data : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH + .rela.data : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH + .rel.tdata : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH + .rela.tdata : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH + .rel.tbss : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH + .rela.tbss : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH + .rel.ctors : { *(.rel.ctors) } >FLASH AT>FLASH :FLASH + .rela.ctors : { *(.rela.ctors) } >FLASH AT>FLASH :FLASH + .rel.dtors : { *(.rel.dtors) } >FLASH AT>FLASH :FLASH + .rela.dtors : { *(.rela.dtors) } >FLASH AT>FLASH :FLASH + .rel.got : { *(.rel.got) } >FLASH AT>FLASH :FLASH + .rela.got : { *(.rela.got) } >FLASH AT>FLASH :FLASH + .rel.bss : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH + .rela.bss : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH + .rel.plt : { *(.rel.plt) } >FLASH AT>FLASH :FLASH + .rela.plt : { *(.rela.plt) } >FLASH AT>FLASH :FLASH + .init : + { + KEEP (*(.init)) + } >FLASH AT>FLASH :FLASH =0xd703d703 + .plt : { *(.plt) } >FLASH AT>FLASH :FLASH + .text : + { + *(.text .stub .text.* .gnu.linkonce.t.*) + KEEP (*(.text.*personality*)) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + } >FLASH AT>FLASH :FLASH =0xd703d703 + .fini : + { + KEEP (*(.fini)) + } >FLASH AT>FLASH :FLASH =0xd703d703 + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + .rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rodata1 : { *(.rodata1) } >FLASH AT>FLASH :FLASH + .eh_frame_hdr : { *(.eh_frame_hdr) } >FLASH AT>FLASH :FLASH + .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH :FLASH + .gcc_except_table : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH :FLASH + .lalign : { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH :FLASH + . = ORIGIN(INTRAM); + .dalign : { . = ALIGN(8); PROVIDE(_data = .); } >INTRAM AT>INTRAM :INTRAM + /* Exception handling */ + .eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) } >INTRAM AT>FLASH :FLASH + .gcc_except_table : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >INTRAM AT>FLASH :FLASH + /* Thread Local Storage sections */ + .tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >INTRAM AT>FLASH :FLASH + .tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >INTRAM AT>FLASH :FLASH + /* Ensure the __preinit_array_start label is properly aligned. We + could instead move the label definition inside the section, but + the linker would then create the section even if it turns out to + be empty, which isn't pretty. */ + PROVIDE (__preinit_array_start = ALIGN(32 / 8)); + .preinit_array : { KEEP (*(.preinit_array)) } >INTRAM AT>FLASH :FLASH + PROVIDE (__preinit_array_end = .); + PROVIDE (__init_array_start = .); + .init_array : { KEEP (*(.init_array)) } >INTRAM AT>FLASH :FLASH + PROVIDE (__init_array_end = .); + PROVIDE (__fini_array_start = .); + .fini_array : { KEEP (*(.fini_array)) } >INTRAM AT>FLASH :FLASH + PROVIDE (__fini_array_end = .); + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin*.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >INTRAM AT>FLASH :FLASH + .dtors : + { + KEEP (*crtbegin*.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >INTRAM AT>FLASH :FLASH + .jcr : { KEEP (*(.jcr)) } >INTRAM AT>FLASH :FLASH + .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >INTRAM AT>FLASH :FLASH + .dynamic : { *(.dynamic) } >INTRAM AT>FLASH :FLASH + .got : { *(.got.plt) *(.got) } >INTRAM AT>FLASH :FLASH + .data : + { + *(.data .data.* .gnu.linkonce.d.*) + KEEP (*(.gnu.linkonce.d.*personality*)) + SORT(CONSTRUCTORS) + } >INTRAM AT>FLASH :FLASH + .data1 : { *(.data1) } >INTRAM AT>FLASH :FLASH + .balign : { . = ALIGN(8); _edata = .; } >INTRAM AT>FLASH :FLASH + _edata = .; + PROVIDE (edata = .); + __bss_start = .; + .bss : + { + *(.dynbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + /* Align here to ensure that the .bss section occupies space up to + _end. Align after .bss to ensure correct alignment even if the + .bss section disappears because there are no input sections. */ + . = ALIGN(8); + } >INTRAM AT>INTRAM :INTRAM + . = ALIGN(8); + _end = .; + PROVIDE (end = .); + __heap_start__ = ALIGN(8); + .heap : + { + *(.heap) + . = (__heap_size__ == __max_heap_size__) ? + ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ - ABSOLUTE(.) : + __heap_size__; + } >INTRAM AT>INTRAM :INTRAM + __heap_end__ = .; + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + .stack ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ : + { + _stack = .; + *(.stack) + . = __stack_size__; + _estack = .; + } >INTRAM AT>INTRAM :INTRAM + .userpage : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE :USERPAGE + .factorypage : { *(.factorypage .factorypage.*) } >FACTORYPAGE AT>FACTORYPAGE :FACTORYPAGE + /DISCARD/ : { *(.note.GNU-stack) } +} diff --git a/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/1128/IAR/lnkuc3b1128.xcl b/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/1128/IAR/lnkuc3b1128.xcl new file mode 100644 index 000000000..4d50bc137 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/1128/IAR/lnkuc3b1128.xcl @@ -0,0 +1,138 @@ +/****************************************************************************** + * AVR32 AT32UC3B1128 XLINK command file for AVR32 IAR C/C++ Compiler. + * + * The assumed memory layout is the one of the AT32UC3B1128: + * + * Start Stop Name Type + * ---------- ---------- ----- -------------- + * 0x00000000 0x00007FFF SRAM RAM + * 0x80000000 0x8001FFFF FLASH FLASH + * + * Usage: xlink your_file(s) -f xcl-file libraries + * + * - Compiler: IAR EWAVR32 + * - Supported devices: AVR32 AT32UC3B1128 + * + * - author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +/************************************************************************/ +/* The following segments are defined in this link file: */ +/* */ +/* Code segments */ +/* CODE32 -- Program code used by __code32 functions. */ +/* RESET -- Reset code. */ +/* EVSEG -- Exception vector handlers. */ +/* */ +/* Constant segments */ +/* INITTAB -- Segment initializer table. */ +/* DIFUNCT -- Dynamic initialization vector used by C++. */ +/* SWITCH -- Switch tables. */ +/* ACTAB -- Table of pointers to acall functions. */ +/* */ +/* DATA21_ID -- Initialization data for DATA21_I. */ +/* DATA32_ID -- Initialization data for DATA32_I. */ +/* DATA32_C -- Constant __data32 data. */ +/* */ +/* CHECKSUM -- Checksum segment. */ +/* */ +/* Data segments */ +/* DATA21_I -- Initialized __data21 data with non-zero */ +/* initial value. */ +/* DATA32_I -- Initialized __data32 data with non-zero */ +/* initial value. */ +/* DATA21_Z -- Initialized __data21 data with zero initial value. */ +/* DATA32_Z -- Initialized __data32 data with zero initial value. */ +/* DATA21_N -- Non-initialized __data21. */ +/* DATA32_N -- Non-initialized __data32. */ +/* SSTACK -- The system stack. */ +/* CSTACK -- The application stack. */ +/* HEAP -- The heap used by malloc and free. */ +/* */ +/************************************************************************/ + +/************************************************************************/ +/* Define CPU */ +/************************************************************************/ + +-cavr32 + +// Declare the IPR0 memory location +-DIPR0=FFFF0800 + +/************************************************************************/ +/* Reset code is located at address 0x80000000 and up. */ +/************************************************************************/ + +-Z(CODE)RESET=80000000-8001FFFF + +/************************************************************************/ +/* The exception handler code is located at address 0x80000000 */ +/* and up. Make sure that the exception table gets properly */ +/* allocated. By using the special -Z@ allocation primitive, the */ +/* placement is guaranteed to be at _EVBASE and onwards. */ +/************************************************************************/ + +-Z@(CODE)EVTAB=80004000-8001FFFF +-Z@(CODE)EV100=80004100-8001FFFF +-P(CODE)EVSEG=80004000-8001FFFF + +/************************************************************************/ +/* Allocate code and const segments. */ +/************************************************************************/ + +-P(CODE)CODE32=80000000-8001FFFF +-P(CONST)DATA32_C=80000000-8001FFFF + +// Initializers +-Z(CONST)INITTAB,DIFUNCT=80000000-8001FFFF +-Z(CONST)CHECKSUM,SWITCH=80000000-8001FFFF +-Z(CONST)DATA21_ID,DATA32_ID=80000000-8001FFFF + +-Z(CONST)ACTAB,HTAB=80000000-8001FFFF + +/************************************************************************/ +/* Allocate the read/write segments that are mapped to RAM. */ +/************************************************************************/ + +-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-00007FFF +-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-00007FFF +-Z(DATA)TRACEBUFFER=00000004-00007FFF + +-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-00007FFF +-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-00007FFF +-Z(DATA)HEAP+_HEAP_SIZE=00000004-00007FFF + +/************************************************************************/ +/* End of File */ +/************************************************************************/ diff --git a/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/1256/GCC/link_uc3b1256.lds b/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/1256/GCC/link_uc3b1256.lds new file mode 100644 index 000000000..619a159a1 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/1256/GCC/link_uc3b1256.lds @@ -0,0 +1,263 @@ +/****************************************************************************** + * AVR32 AT32UC3B1256 GNU LD script file. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: AVR32 AT32UC3B1256 + * + * - author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32") + +OUTPUT_ARCH(avr32:uc) + +ENTRY(_start) + +MEMORY +{ + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00040000 + INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x00007FFC + USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200 + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 0x00000200 +} + +PHDRS +{ + FLASH PT_LOAD; + INTRAM PT_NULL; + USERPAGE PT_LOAD; + FACTORYPAGE PT_LOAD; +} + +SECTIONS +{ + /* If this heap size is selected, all the INTRAM space from the end of the + data area to the beginning of the stack will be allocated for the heap. */ + __max_heap_size__ = -1; + + /* Use a default heap size if heap size was not defined. */ + __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__; + + /* Use a default stack size if stack size was not defined. */ + __stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 4K; + + /* Read-only sections, merged into text segment: */ + PROVIDE (__executable_start = 0x80000000); . = 0x80000000; + .interp : { *(.interp) } >FLASH AT>FLASH :FLASH + .reset : { *(.reset) } >FLASH AT>FLASH :FLASH + .hash : { *(.hash) } >FLASH AT>FLASH :FLASH + .dynsym : { *(.dynsym) } >FLASH AT>FLASH :FLASH + .dynstr : { *(.dynstr) } >FLASH AT>FLASH :FLASH + .gnu.version : { *(.gnu.version) } >FLASH AT>FLASH :FLASH + .gnu.version_d : { *(.gnu.version_d) } >FLASH AT>FLASH :FLASH + .gnu.version_r : { *(.gnu.version_r) } >FLASH AT>FLASH :FLASH + .rel.init : { *(.rel.init) } >FLASH AT>FLASH :FLASH + .rela.init : { *(.rela.init) } >FLASH AT>FLASH :FLASH + .rel.text : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH + .rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH + .rel.fini : { *(.rel.fini) } >FLASH AT>FLASH :FLASH + .rela.fini : { *(.rela.fini) } >FLASH AT>FLASH :FLASH + .rel.rodata : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rela.rodata : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rel.data.rel.ro : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH + .rela.data.rel.ro : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH + .rel.data : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH + .rela.data : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH + .rel.tdata : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH + .rela.tdata : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH + .rel.tbss : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH + .rela.tbss : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH + .rel.ctors : { *(.rel.ctors) } >FLASH AT>FLASH :FLASH + .rela.ctors : { *(.rela.ctors) } >FLASH AT>FLASH :FLASH + .rel.dtors : { *(.rel.dtors) } >FLASH AT>FLASH :FLASH + .rela.dtors : { *(.rela.dtors) } >FLASH AT>FLASH :FLASH + .rel.got : { *(.rel.got) } >FLASH AT>FLASH :FLASH + .rela.got : { *(.rela.got) } >FLASH AT>FLASH :FLASH + .rel.bss : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH + .rela.bss : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH + .rel.plt : { *(.rel.plt) } >FLASH AT>FLASH :FLASH + .rela.plt : { *(.rela.plt) } >FLASH AT>FLASH :FLASH + .init : + { + KEEP (*(.init)) + } >FLASH AT>FLASH :FLASH =0xd703d703 + .plt : { *(.plt) } >FLASH AT>FLASH :FLASH + .text : + { + *(.text .stub .text.* .gnu.linkonce.t.*) + KEEP (*(.text.*personality*)) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + } >FLASH AT>FLASH :FLASH =0xd703d703 + .fini : + { + KEEP (*(.fini)) + } >FLASH AT>FLASH :FLASH =0xd703d703 + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + .rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rodata1 : { *(.rodata1) } >FLASH AT>FLASH :FLASH + .eh_frame_hdr : { *(.eh_frame_hdr) } >FLASH AT>FLASH :FLASH + .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH :FLASH + .gcc_except_table : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH :FLASH + .lalign : { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH :FLASH + . = ORIGIN(INTRAM); + .dalign : { . = ALIGN(8); PROVIDE(_data = .); } >INTRAM AT>INTRAM :INTRAM + /* Exception handling */ + .eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) } >INTRAM AT>FLASH :FLASH + .gcc_except_table : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >INTRAM AT>FLASH :FLASH + /* Thread Local Storage sections */ + .tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >INTRAM AT>FLASH :FLASH + .tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >INTRAM AT>FLASH :FLASH + /* Ensure the __preinit_array_start label is properly aligned. We + could instead move the label definition inside the section, but + the linker would then create the section even if it turns out to + be empty, which isn't pretty. */ + PROVIDE (__preinit_array_start = ALIGN(32 / 8)); + .preinit_array : { KEEP (*(.preinit_array)) } >INTRAM AT>FLASH :FLASH + PROVIDE (__preinit_array_end = .); + PROVIDE (__init_array_start = .); + .init_array : { KEEP (*(.init_array)) } >INTRAM AT>FLASH :FLASH + PROVIDE (__init_array_end = .); + PROVIDE (__fini_array_start = .); + .fini_array : { KEEP (*(.fini_array)) } >INTRAM AT>FLASH :FLASH + PROVIDE (__fini_array_end = .); + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin*.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >INTRAM AT>FLASH :FLASH + .dtors : + { + KEEP (*crtbegin*.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >INTRAM AT>FLASH :FLASH + .jcr : { KEEP (*(.jcr)) } >INTRAM AT>FLASH :FLASH + .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >INTRAM AT>FLASH :FLASH + .dynamic : { *(.dynamic) } >INTRAM AT>FLASH :FLASH + .got : { *(.got.plt) *(.got) } >INTRAM AT>FLASH :FLASH + .data : + { + *(.data .data.* .gnu.linkonce.d.*) + KEEP (*(.gnu.linkonce.d.*personality*)) + SORT(CONSTRUCTORS) + } >INTRAM AT>FLASH :FLASH + .data1 : { *(.data1) } >INTRAM AT>FLASH :FLASH + .balign : { . = ALIGN(8); _edata = .; } >INTRAM AT>FLASH :FLASH + _edata = .; + PROVIDE (edata = .); + __bss_start = .; + .bss : + { + *(.dynbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + /* Align here to ensure that the .bss section occupies space up to + _end. Align after .bss to ensure correct alignment even if the + .bss section disappears because there are no input sections. */ + . = ALIGN(8); + } >INTRAM AT>INTRAM :INTRAM + . = ALIGN(8); + _end = .; + PROVIDE (end = .); + __heap_start__ = ALIGN(8); + .heap : + { + *(.heap) + . = (__heap_size__ == __max_heap_size__) ? + ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ - ABSOLUTE(.) : + __heap_size__; + } >INTRAM AT>INTRAM :INTRAM + __heap_end__ = .; + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + .stack ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ : + { + _stack = .; + *(.stack) + . = __stack_size__; + _estack = .; + } >INTRAM AT>INTRAM :INTRAM + .userpage : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE :USERPAGE + .factorypage : { *(.factorypage .factorypage.*) } >FACTORYPAGE AT>FACTORYPAGE :FACTORYPAGE + /DISCARD/ : { *(.note.GNU-stack) } +} diff --git a/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/1256/IAR/lnkuc3b1256.xcl b/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/1256/IAR/lnkuc3b1256.xcl new file mode 100644 index 000000000..f765e4e9c --- /dev/null +++ b/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/1256/IAR/lnkuc3b1256.xcl @@ -0,0 +1,138 @@ +/****************************************************************************** + * AVR32 AT32UC3B1256 XLINK command file for AVR32 IAR C/C++ Compiler. + * + * The assumed memory layout is the one of the AT32UC3B1256: + * + * Start Stop Name Type + * ---------- ---------- ----- -------------- + * 0x00000000 0x00007FFF SRAM RAM + * 0x80000000 0x8003FFFF FLASH FLASH + * + * Usage: xlink your_file(s) -f xcl-file libraries + * + * - Compiler: IAR EWAVR32 + * - Supported devices: AVR32 AT32UC3B1256 + * + * - author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +/************************************************************************/ +/* The following segments are defined in this link file: */ +/* */ +/* Code segments */ +/* CODE32 -- Program code used by __code32 functions. */ +/* RESET -- Reset code. */ +/* EVSEG -- Exception vector handlers. */ +/* */ +/* Constant segments */ +/* INITTAB -- Segment initializer table. */ +/* DIFUNCT -- Dynamic initialization vector used by C++. */ +/* SWITCH -- Switch tables. */ +/* ACTAB -- Table of pointers to acall functions. */ +/* */ +/* DATA21_ID -- Initialization data for DATA21_I. */ +/* DATA32_ID -- Initialization data for DATA32_I. */ +/* DATA32_C -- Constant __data32 data. */ +/* */ +/* CHECKSUM -- Checksum segment. */ +/* */ +/* Data segments */ +/* DATA21_I -- Initialized __data21 data with non-zero */ +/* initial value. */ +/* DATA32_I -- Initialized __data32 data with non-zero */ +/* initial value. */ +/* DATA21_Z -- Initialized __data21 data with zero initial value. */ +/* DATA32_Z -- Initialized __data32 data with zero initial value. */ +/* DATA21_N -- Non-initialized __data21. */ +/* DATA32_N -- Non-initialized __data32. */ +/* SSTACK -- The system stack. */ +/* CSTACK -- The application stack. */ +/* HEAP -- The heap used by malloc and free. */ +/* */ +/************************************************************************/ + +/************************************************************************/ +/* Define CPU */ +/************************************************************************/ + +-cavr32 + +// Declare the IPR0 memory location +-DIPR0=FFFF0800 + +/************************************************************************/ +/* Reset code is located at address 0x80000000 and up. */ +/************************************************************************/ + +-Z(CODE)RESET=80000000-8003FFFF + +/************************************************************************/ +/* The exception handler code is located at address 0x80000000 */ +/* and up. Make sure that the exception table gets properly */ +/* allocated. By using the special -Z@ allocation primitive, the */ +/* placement is guaranteed to be at _EVBASE and onwards. */ +/************************************************************************/ + +-Z@(CODE)EVTAB=80004000-8003FFFF +-Z@(CODE)EV100=80004100-8003FFFF +-P(CODE)EVSEG=80004000-8003FFFF + +/************************************************************************/ +/* Allocate code and const segments. */ +/************************************************************************/ + +-P(CODE)CODE32=80000000-8003FFFF +-P(CONST)DATA32_C=80000000-8003FFFF + +// Initializers +-Z(CONST)INITTAB,DIFUNCT=80000000-8003FFFF +-Z(CONST)CHECKSUM,SWITCH=80000000-8003FFFF +-Z(CONST)DATA21_ID,DATA32_ID=80000000-8003FFFF + +-Z(CONST)ACTAB,HTAB=80000000-8003FFFF + +/************************************************************************/ +/* Allocate the read/write segments that are mapped to RAM. */ +/************************************************************************/ + +-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-00007FFF +-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-00007FFF +-Z(DATA)TRACEBUFFER=00000004-00007FFF + +-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-00007FFF +-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-00007FFF +-Z(DATA)HEAP+_HEAP_SIZE=00000004-00007FFF + +/************************************************************************/ +/* End of File */ +/************************************************************************/ diff --git a/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/164/GCC/link_uc3b164.lds b/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/164/GCC/link_uc3b164.lds new file mode 100644 index 000000000..cae225d89 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/164/GCC/link_uc3b164.lds @@ -0,0 +1,263 @@ +/****************************************************************************** + * AVR32 AT32UC3B164 GNU LD script file. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: AVR32 AT32UC3B164 + * + * - author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32") + +OUTPUT_ARCH(avr32:uc) + +ENTRY(_start) + +MEMORY +{ + FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00010000 + INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x00003FFC + USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200 + FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 0x00000200 +} + +PHDRS +{ + FLASH PT_LOAD; + INTRAM PT_NULL; + USERPAGE PT_LOAD; + FACTORYPAGE PT_LOAD; +} + +SECTIONS +{ + /* If this heap size is selected, all the INTRAM space from the end of the + data area to the beginning of the stack will be allocated for the heap. */ + __max_heap_size__ = -1; + + /* Use a default heap size if heap size was not defined. */ + __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__; + + /* Use a default stack size if stack size was not defined. */ + __stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 4K; + + /* Read-only sections, merged into text segment: */ + PROVIDE (__executable_start = 0x80000000); . = 0x80000000; + .interp : { *(.interp) } >FLASH AT>FLASH :FLASH + .reset : { *(.reset) } >FLASH AT>FLASH :FLASH + .hash : { *(.hash) } >FLASH AT>FLASH :FLASH + .dynsym : { *(.dynsym) } >FLASH AT>FLASH :FLASH + .dynstr : { *(.dynstr) } >FLASH AT>FLASH :FLASH + .gnu.version : { *(.gnu.version) } >FLASH AT>FLASH :FLASH + .gnu.version_d : { *(.gnu.version_d) } >FLASH AT>FLASH :FLASH + .gnu.version_r : { *(.gnu.version_r) } >FLASH AT>FLASH :FLASH + .rel.init : { *(.rel.init) } >FLASH AT>FLASH :FLASH + .rela.init : { *(.rela.init) } >FLASH AT>FLASH :FLASH + .rel.text : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH + .rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH + .rel.fini : { *(.rel.fini) } >FLASH AT>FLASH :FLASH + .rela.fini : { *(.rela.fini) } >FLASH AT>FLASH :FLASH + .rel.rodata : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rela.rodata : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rel.data.rel.ro : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH + .rela.data.rel.ro : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH + .rel.data : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH + .rela.data : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH + .rel.tdata : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH + .rela.tdata : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH + .rel.tbss : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH + .rela.tbss : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH + .rel.ctors : { *(.rel.ctors) } >FLASH AT>FLASH :FLASH + .rela.ctors : { *(.rela.ctors) } >FLASH AT>FLASH :FLASH + .rel.dtors : { *(.rel.dtors) } >FLASH AT>FLASH :FLASH + .rela.dtors : { *(.rela.dtors) } >FLASH AT>FLASH :FLASH + .rel.got : { *(.rel.got) } >FLASH AT>FLASH :FLASH + .rela.got : { *(.rela.got) } >FLASH AT>FLASH :FLASH + .rel.bss : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH + .rela.bss : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH + .rel.plt : { *(.rel.plt) } >FLASH AT>FLASH :FLASH + .rela.plt : { *(.rela.plt) } >FLASH AT>FLASH :FLASH + .init : + { + KEEP (*(.init)) + } >FLASH AT>FLASH :FLASH =0xd703d703 + .plt : { *(.plt) } >FLASH AT>FLASH :FLASH + .text : + { + *(.text .stub .text.* .gnu.linkonce.t.*) + KEEP (*(.text.*personality*)) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + } >FLASH AT>FLASH :FLASH =0xd703d703 + .fini : + { + KEEP (*(.fini)) + } >FLASH AT>FLASH :FLASH =0xd703d703 + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + .rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH + .rodata1 : { *(.rodata1) } >FLASH AT>FLASH :FLASH + .eh_frame_hdr : { *(.eh_frame_hdr) } >FLASH AT>FLASH :FLASH + .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH :FLASH + .gcc_except_table : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH :FLASH + .lalign : { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH :FLASH + . = ORIGIN(INTRAM); + .dalign : { . = ALIGN(8); PROVIDE(_data = .); } >INTRAM AT>INTRAM :INTRAM + /* Exception handling */ + .eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) } >INTRAM AT>FLASH :FLASH + .gcc_except_table : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >INTRAM AT>FLASH :FLASH + /* Thread Local Storage sections */ + .tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >INTRAM AT>FLASH :FLASH + .tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >INTRAM AT>FLASH :FLASH + /* Ensure the __preinit_array_start label is properly aligned. We + could instead move the label definition inside the section, but + the linker would then create the section even if it turns out to + be empty, which isn't pretty. */ + PROVIDE (__preinit_array_start = ALIGN(32 / 8)); + .preinit_array : { KEEP (*(.preinit_array)) } >INTRAM AT>FLASH :FLASH + PROVIDE (__preinit_array_end = .); + PROVIDE (__init_array_start = .); + .init_array : { KEEP (*(.init_array)) } >INTRAM AT>FLASH :FLASH + PROVIDE (__init_array_end = .); + PROVIDE (__fini_array_start = .); + .fini_array : { KEEP (*(.fini_array)) } >INTRAM AT>FLASH :FLASH + PROVIDE (__fini_array_end = .); + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin*.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >INTRAM AT>FLASH :FLASH + .dtors : + { + KEEP (*crtbegin*.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >INTRAM AT>FLASH :FLASH + .jcr : { KEEP (*(.jcr)) } >INTRAM AT>FLASH :FLASH + .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >INTRAM AT>FLASH :FLASH + .dynamic : { *(.dynamic) } >INTRAM AT>FLASH :FLASH + .got : { *(.got.plt) *(.got) } >INTRAM AT>FLASH :FLASH + .data : + { + *(.data .data.* .gnu.linkonce.d.*) + KEEP (*(.gnu.linkonce.d.*personality*)) + SORT(CONSTRUCTORS) + } >INTRAM AT>FLASH :FLASH + .data1 : { *(.data1) } >INTRAM AT>FLASH :FLASH + .balign : { . = ALIGN(8); _edata = .; } >INTRAM AT>FLASH :FLASH + _edata = .; + PROVIDE (edata = .); + __bss_start = .; + .bss : + { + *(.dynbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + /* Align here to ensure that the .bss section occupies space up to + _end. Align after .bss to ensure correct alignment even if the + .bss section disappears because there are no input sections. */ + . = ALIGN(8); + } >INTRAM AT>INTRAM :INTRAM + . = ALIGN(8); + _end = .; + PROVIDE (end = .); + __heap_start__ = ALIGN(8); + .heap : + { + *(.heap) + . = (__heap_size__ == __max_heap_size__) ? + ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ - ABSOLUTE(.) : + __heap_size__; + } >INTRAM AT>INTRAM :INTRAM + __heap_end__ = .; + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + .stack ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ : + { + _stack = .; + *(.stack) + . = __stack_size__; + _estack = .; + } >INTRAM AT>INTRAM :INTRAM + .userpage : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE :USERPAGE + .factorypage : { *(.factorypage .factorypage.*) } >FACTORYPAGE AT>FACTORYPAGE :FACTORYPAGE + /DISCARD/ : { *(.note.GNU-stack) } +} diff --git a/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/164/IAR/lnkuc3b164.xcl b/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/164/IAR/lnkuc3b164.xcl new file mode 100644 index 000000000..01af490cf --- /dev/null +++ b/20080212/Demo/AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/164/IAR/lnkuc3b164.xcl @@ -0,0 +1,138 @@ +/****************************************************************************** + * AVR32 AT32UC3B164 XLINK command file for AVR32 IAR C/C++ Compiler. + * + * The assumed memory layout is the one of the AT32UC3B164: + * + * Start Stop Name Type + * ---------- ---------- ----- -------------- + * 0x00000000 0x00003FFF SRAM RAM + * 0x80000000 0x8000FFFF FLASH FLASH + * + * Usage: xlink your_file(s) -f xcl-file libraries + * + * - Compiler: IAR EWAVR32 + * - Supported devices: AVR32 AT32UC3B164 + * + * - author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +/************************************************************************/ +/* The following segments are defined in this link file: */ +/* */ +/* Code segments */ +/* CODE32 -- Program code used by __code32 functions. */ +/* RESET -- Reset code. */ +/* EVSEG -- Exception vector handlers. */ +/* */ +/* Constant segments */ +/* INITTAB -- Segment initializer table. */ +/* DIFUNCT -- Dynamic initialization vector used by C++. */ +/* SWITCH -- Switch tables. */ +/* ACTAB -- Table of pointers to acall functions. */ +/* */ +/* DATA21_ID -- Initialization data for DATA21_I. */ +/* DATA32_ID -- Initialization data for DATA32_I. */ +/* DATA32_C -- Constant __data32 data. */ +/* */ +/* CHECKSUM -- Checksum segment. */ +/* */ +/* Data segments */ +/* DATA21_I -- Initialized __data21 data with non-zero */ +/* initial value. */ +/* DATA32_I -- Initialized __data32 data with non-zero */ +/* initial value. */ +/* DATA21_Z -- Initialized __data21 data with zero initial value. */ +/* DATA32_Z -- Initialized __data32 data with zero initial value. */ +/* DATA21_N -- Non-initialized __data21. */ +/* DATA32_N -- Non-initialized __data32. */ +/* SSTACK -- The system stack. */ +/* CSTACK -- The application stack. */ +/* HEAP -- The heap used by malloc and free. */ +/* */ +/************************************************************************/ + +/************************************************************************/ +/* Define CPU */ +/************************************************************************/ + +-cavr32 + +// Declare the IPR0 memory location +-DIPR0=FFFF0800 + +/************************************************************************/ +/* Reset code is located at address 0x80000000 and up. */ +/************************************************************************/ + +-Z(CODE)RESET=80000000-8000FFFF + +/************************************************************************/ +/* The exception handler code is located at address 0x80000000 */ +/* and up. Make sure that the exception table gets properly */ +/* allocated. By using the special -Z@ allocation primitive, the */ +/* placement is guaranteed to be at _EVBASE and onwards. */ +/************************************************************************/ + +-Z@(CODE)EVTAB=80004000-8000FFFF +-Z@(CODE)EV100=80004100-8000FFFF +-P(CODE)EVSEG=80004000-8000FFFF + +/************************************************************************/ +/* Allocate code and const segments. */ +/************************************************************************/ + +-P(CODE)CODE32=80000000-8000FFFF +-P(CONST)DATA32_C=80000000-8000FFFF + +// Initializers +-Z(CONST)INITTAB,DIFUNCT=80000000-8000FFFF +-Z(CONST)CHECKSUM,SWITCH=80000000-8000FFFF +-Z(CONST)DATA21_ID,DATA32_ID=80000000-8000FFFF + +-Z(CONST)ACTAB,HTAB=80000000-8000FFFF + +/************************************************************************/ +/* Allocate the read/write segments that are mapped to RAM. */ +/************************************************************************/ + +-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-00003FFF +-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-00003FFF +-Z(DATA)TRACEBUFFER=00000004-00003FFF + +-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-00003FFF +-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-00003FFF +-Z(DATA)HEAP+_HEAP_SIZE=00000004-00003FFF + +/************************************************************************/ +/* End of File */ +/************************************************************************/ diff --git a/20080212/Demo/AVR32_UC3/UTILS/PREPROCESSOR/mrepeat.h b/20080212/Demo/AVR32_UC3/UTILS/PREPROCESSOR/mrepeat.h new file mode 100644 index 000000000..83b5f4916 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/UTILS/PREPROCESSOR/mrepeat.h @@ -0,0 +1,323 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Preprocessor macro repeating utils. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef _MREPEAT_H_ +#define _MREPEAT_H_ + +#include "preprocessor.h" + + +//! Maximal number of repetitions supported by MREPEAT. +#define MREPEAT_LIMIT 256 + +/*! \brief Macro repeat. + * + * This macro represents a horizontal repetition construct. + * + * \param count The number of repetitious calls to macro. Valid values range from 0 to MREPEAT_LIMIT. + * \param macro A binary operation of the form macro(n, data). This macro is expanded by MREPEAT with + * the current repetition number and the auxiliary data argument. + * \param data Auxiliary data passed to macro. + * + * \return macro(0, data) macro(1, data) ... macro(count - 1, data) + */ +#define MREPEAT(count, macro, data) TPASTE2(MREPEAT, count)(macro, data) + +#define MREPEAT0( macro, data) +#define MREPEAT1( macro, data) MREPEAT0( macro, data) macro( 0, data) +#define MREPEAT2( macro, data) MREPEAT1( macro, data) macro( 1, data) +#define MREPEAT3( macro, data) MREPEAT2( macro, data) macro( 2, data) +#define MREPEAT4( macro, data) MREPEAT3( macro, data) macro( 3, data) +#define MREPEAT5( macro, data) MREPEAT4( macro, data) macro( 4, data) +#define MREPEAT6( macro, data) MREPEAT5( macro, data) macro( 5, data) +#define MREPEAT7( macro, data) MREPEAT6( macro, data) macro( 6, data) +#define MREPEAT8( macro, data) MREPEAT7( macro, data) macro( 7, data) +#define MREPEAT9( macro, data) MREPEAT8( macro, data) macro( 8, data) +#define MREPEAT10( macro, data) MREPEAT9( macro, data) macro( 9, data) +#define MREPEAT11( macro, data) MREPEAT10( macro, data) macro( 10, data) +#define MREPEAT12( macro, data) MREPEAT11( macro, data) macro( 11, data) +#define MREPEAT13( macro, data) MREPEAT12( macro, data) macro( 12, data) +#define MREPEAT14( macro, data) MREPEAT13( macro, data) macro( 13, data) +#define MREPEAT15( macro, data) MREPEAT14( macro, data) macro( 14, data) +#define MREPEAT16( macro, data) MREPEAT15( macro, data) macro( 15, data) +#define MREPEAT17( macro, data) MREPEAT16( macro, data) macro( 16, data) +#define MREPEAT18( macro, data) MREPEAT17( macro, data) macro( 17, data) +#define MREPEAT19( macro, data) MREPEAT18( macro, data) macro( 18, data) +#define MREPEAT20( macro, data) MREPEAT19( macro, data) macro( 19, data) +#define MREPEAT21( macro, data) MREPEAT20( macro, data) macro( 20, data) +#define MREPEAT22( macro, data) MREPEAT21( macro, data) macro( 21, data) +#define MREPEAT23( macro, data) MREPEAT22( macro, data) macro( 22, data) +#define MREPEAT24( macro, data) MREPEAT23( macro, data) macro( 23, data) +#define MREPEAT25( macro, data) MREPEAT24( macro, data) macro( 24, data) +#define MREPEAT26( macro, data) MREPEAT25( macro, data) macro( 25, data) +#define MREPEAT27( macro, data) MREPEAT26( macro, data) macro( 26, data) +#define MREPEAT28( macro, data) MREPEAT27( macro, data) macro( 27, data) +#define MREPEAT29( macro, data) MREPEAT28( macro, data) macro( 28, data) +#define MREPEAT30( macro, data) MREPEAT29( macro, data) macro( 29, data) +#define MREPEAT31( macro, data) MREPEAT30( macro, data) macro( 30, data) +#define MREPEAT32( macro, data) MREPEAT31( macro, data) macro( 31, data) +#define MREPEAT33( macro, data) MREPEAT32( macro, data) macro( 32, data) +#define MREPEAT34( macro, data) MREPEAT33( macro, data) macro( 33, data) +#define MREPEAT35( macro, data) MREPEAT34( macro, data) macro( 34, data) +#define MREPEAT36( macro, data) MREPEAT35( macro, data) macro( 35, data) +#define MREPEAT37( macro, data) MREPEAT36( macro, data) macro( 36, data) +#define MREPEAT38( macro, data) MREPEAT37( macro, data) macro( 37, data) +#define MREPEAT39( macro, data) MREPEAT38( macro, data) macro( 38, data) +#define MREPEAT40( macro, data) MREPEAT39( macro, data) macro( 39, data) +#define MREPEAT41( macro, data) MREPEAT40( macro, data) macro( 40, data) +#define MREPEAT42( macro, data) MREPEAT41( macro, data) macro( 41, data) +#define MREPEAT43( macro, data) MREPEAT42( macro, data) macro( 42, data) +#define MREPEAT44( macro, data) MREPEAT43( macro, data) macro( 43, data) +#define MREPEAT45( macro, data) MREPEAT44( macro, data) macro( 44, data) +#define MREPEAT46( macro, data) MREPEAT45( macro, data) macro( 45, data) +#define MREPEAT47( macro, data) MREPEAT46( macro, data) macro( 46, data) +#define MREPEAT48( macro, data) MREPEAT47( macro, data) macro( 47, data) +#define MREPEAT49( macro, data) MREPEAT48( macro, data) macro( 48, data) +#define MREPEAT50( macro, data) MREPEAT49( macro, data) macro( 49, data) +#define MREPEAT51( macro, data) MREPEAT50( macro, data) macro( 50, data) +#define MREPEAT52( macro, data) MREPEAT51( macro, data) macro( 51, data) +#define MREPEAT53( macro, data) MREPEAT52( macro, data) macro( 52, data) +#define MREPEAT54( macro, data) MREPEAT53( macro, data) macro( 53, data) +#define MREPEAT55( macro, data) MREPEAT54( macro, data) macro( 54, data) +#define MREPEAT56( macro, data) MREPEAT55( macro, data) macro( 55, data) +#define MREPEAT57( macro, data) MREPEAT56( macro, data) macro( 56, data) +#define MREPEAT58( macro, data) MREPEAT57( macro, data) macro( 57, data) +#define MREPEAT59( macro, data) MREPEAT58( macro, data) macro( 58, data) +#define MREPEAT60( macro, data) MREPEAT59( macro, data) macro( 59, data) +#define MREPEAT61( macro, data) MREPEAT60( macro, data) macro( 60, data) +#define MREPEAT62( macro, data) MREPEAT61( macro, data) macro( 61, data) +#define MREPEAT63( macro, data) MREPEAT62( macro, data) macro( 62, data) +#define MREPEAT64( macro, data) MREPEAT63( macro, data) macro( 63, data) +#define MREPEAT65( macro, data) MREPEAT64( macro, data) macro( 64, data) +#define MREPEAT66( macro, data) MREPEAT65( macro, data) macro( 65, data) +#define MREPEAT67( macro, data) MREPEAT66( macro, data) macro( 66, data) +#define MREPEAT68( macro, data) MREPEAT67( macro, data) macro( 67, data) +#define MREPEAT69( macro, data) MREPEAT68( macro, data) macro( 68, data) +#define MREPEAT70( macro, data) MREPEAT69( macro, data) macro( 69, data) +#define MREPEAT71( macro, data) MREPEAT70( macro, data) macro( 70, data) +#define MREPEAT72( macro, data) MREPEAT71( macro, data) macro( 71, data) +#define MREPEAT73( macro, data) MREPEAT72( macro, data) macro( 72, data) +#define MREPEAT74( macro, data) MREPEAT73( macro, data) macro( 73, data) +#define MREPEAT75( macro, data) MREPEAT74( macro, data) macro( 74, data) +#define MREPEAT76( macro, data) MREPEAT75( macro, data) macro( 75, data) +#define MREPEAT77( macro, data) MREPEAT76( macro, data) macro( 76, data) +#define MREPEAT78( macro, data) MREPEAT77( macro, data) macro( 77, data) +#define MREPEAT79( macro, data) MREPEAT78( macro, data) macro( 78, data) +#define MREPEAT80( macro, data) MREPEAT79( macro, data) macro( 79, data) +#define MREPEAT81( macro, data) MREPEAT80( macro, data) macro( 80, data) +#define MREPEAT82( macro, data) MREPEAT81( macro, data) macro( 81, data) +#define MREPEAT83( macro, data) MREPEAT82( macro, data) macro( 82, data) +#define MREPEAT84( macro, data) MREPEAT83( macro, data) macro( 83, data) +#define MREPEAT85( macro, data) MREPEAT84( macro, data) macro( 84, data) +#define MREPEAT86( macro, data) MREPEAT85( macro, data) macro( 85, data) +#define MREPEAT87( macro, data) MREPEAT86( macro, data) macro( 86, data) +#define MREPEAT88( macro, data) MREPEAT87( macro, data) macro( 87, data) +#define MREPEAT89( macro, data) MREPEAT88( macro, data) macro( 88, data) +#define MREPEAT90( macro, data) MREPEAT89( macro, data) macro( 89, data) +#define MREPEAT91( macro, data) MREPEAT90( macro, data) macro( 90, data) +#define MREPEAT92( macro, data) MREPEAT91( macro, data) macro( 91, data) +#define MREPEAT93( macro, data) MREPEAT92( macro, data) macro( 92, data) +#define MREPEAT94( macro, data) MREPEAT93( macro, data) macro( 93, data) +#define MREPEAT95( macro, data) MREPEAT94( macro, data) macro( 94, data) +#define MREPEAT96( macro, data) MREPEAT95( macro, data) macro( 95, data) +#define MREPEAT97( macro, data) MREPEAT96( macro, data) macro( 96, data) +#define MREPEAT98( macro, data) MREPEAT97( macro, data) macro( 97, data) +#define MREPEAT99( macro, data) MREPEAT98( macro, data) macro( 98, data) +#define MREPEAT100(macro, data) MREPEAT99( macro, data) macro( 99, data) +#define MREPEAT101(macro, data) MREPEAT100(macro, data) macro(100, data) +#define MREPEAT102(macro, data) MREPEAT101(macro, data) macro(101, data) +#define MREPEAT103(macro, data) MREPEAT102(macro, data) macro(102, data) +#define MREPEAT104(macro, data) MREPEAT103(macro, data) macro(103, data) +#define MREPEAT105(macro, data) MREPEAT104(macro, data) macro(104, data) +#define MREPEAT106(macro, data) MREPEAT105(macro, data) macro(105, data) +#define MREPEAT107(macro, data) MREPEAT106(macro, data) macro(106, data) +#define MREPEAT108(macro, data) MREPEAT107(macro, data) macro(107, data) +#define MREPEAT109(macro, data) MREPEAT108(macro, data) macro(108, data) +#define MREPEAT110(macro, data) MREPEAT109(macro, data) macro(109, data) +#define MREPEAT111(macro, data) MREPEAT110(macro, data) macro(110, data) +#define MREPEAT112(macro, data) MREPEAT111(macro, data) macro(111, data) +#define MREPEAT113(macro, data) MREPEAT112(macro, data) macro(112, data) +#define MREPEAT114(macro, data) MREPEAT113(macro, data) macro(113, data) +#define MREPEAT115(macro, data) MREPEAT114(macro, data) macro(114, data) +#define MREPEAT116(macro, data) MREPEAT115(macro, data) macro(115, data) +#define MREPEAT117(macro, data) MREPEAT116(macro, data) macro(116, data) +#define MREPEAT118(macro, data) MREPEAT117(macro, data) macro(117, data) +#define MREPEAT119(macro, data) MREPEAT118(macro, data) macro(118, data) +#define MREPEAT120(macro, data) MREPEAT119(macro, data) macro(119, data) +#define MREPEAT121(macro, data) MREPEAT120(macro, data) macro(120, data) +#define MREPEAT122(macro, data) MREPEAT121(macro, data) macro(121, data) +#define MREPEAT123(macro, data) MREPEAT122(macro, data) macro(122, data) +#define MREPEAT124(macro, data) MREPEAT123(macro, data) macro(123, data) +#define MREPEAT125(macro, data) MREPEAT124(macro, data) macro(124, data) +#define MREPEAT126(macro, data) MREPEAT125(macro, data) macro(125, data) +#define MREPEAT127(macro, data) MREPEAT126(macro, data) macro(126, data) +#define MREPEAT128(macro, data) MREPEAT127(macro, data) macro(127, data) +#define MREPEAT129(macro, data) MREPEAT128(macro, data) macro(128, data) +#define MREPEAT130(macro, data) MREPEAT129(macro, data) macro(129, data) +#define MREPEAT131(macro, data) MREPEAT130(macro, data) macro(130, data) +#define MREPEAT132(macro, data) MREPEAT131(macro, data) macro(131, data) +#define MREPEAT133(macro, data) MREPEAT132(macro, data) macro(132, data) +#define MREPEAT134(macro, data) MREPEAT133(macro, data) macro(133, data) +#define MREPEAT135(macro, data) MREPEAT134(macro, data) macro(134, data) +#define MREPEAT136(macro, data) MREPEAT135(macro, data) macro(135, data) +#define MREPEAT137(macro, data) MREPEAT136(macro, data) macro(136, data) +#define MREPEAT138(macro, data) MREPEAT137(macro, data) macro(137, data) +#define MREPEAT139(macro, data) MREPEAT138(macro, data) macro(138, data) +#define MREPEAT140(macro, data) MREPEAT139(macro, data) macro(139, data) +#define MREPEAT141(macro, data) MREPEAT140(macro, data) macro(140, data) +#define MREPEAT142(macro, data) MREPEAT141(macro, data) macro(141, data) +#define MREPEAT143(macro, data) MREPEAT142(macro, data) macro(142, data) +#define MREPEAT144(macro, data) MREPEAT143(macro, data) macro(143, data) +#define MREPEAT145(macro, data) MREPEAT144(macro, data) macro(144, data) +#define MREPEAT146(macro, data) MREPEAT145(macro, data) macro(145, data) +#define MREPEAT147(macro, data) MREPEAT146(macro, data) macro(146, data) +#define MREPEAT148(macro, data) MREPEAT147(macro, data) macro(147, data) +#define MREPEAT149(macro, data) MREPEAT148(macro, data) macro(148, data) +#define MREPEAT150(macro, data) MREPEAT149(macro, data) macro(149, data) +#define MREPEAT151(macro, data) MREPEAT150(macro, data) macro(150, data) +#define MREPEAT152(macro, data) MREPEAT151(macro, data) macro(151, data) +#define MREPEAT153(macro, data) MREPEAT152(macro, data) macro(152, data) +#define MREPEAT154(macro, data) MREPEAT153(macro, data) macro(153, data) +#define MREPEAT155(macro, data) MREPEAT154(macro, data) macro(154, data) +#define MREPEAT156(macro, data) MREPEAT155(macro, data) macro(155, data) +#define MREPEAT157(macro, data) MREPEAT156(macro, data) macro(156, data) +#define MREPEAT158(macro, data) MREPEAT157(macro, data) macro(157, data) +#define MREPEAT159(macro, data) MREPEAT158(macro, data) macro(158, data) +#define MREPEAT160(macro, data) MREPEAT159(macro, data) macro(159, data) +#define MREPEAT161(macro, data) MREPEAT160(macro, data) macro(160, data) +#define MREPEAT162(macro, data) MREPEAT161(macro, data) macro(161, data) +#define MREPEAT163(macro, data) MREPEAT162(macro, data) macro(162, data) +#define MREPEAT164(macro, data) MREPEAT163(macro, data) macro(163, data) +#define MREPEAT165(macro, data) MREPEAT164(macro, data) macro(164, data) +#define MREPEAT166(macro, data) MREPEAT165(macro, data) macro(165, data) +#define MREPEAT167(macro, data) MREPEAT166(macro, data) macro(166, data) +#define MREPEAT168(macro, data) MREPEAT167(macro, data) macro(167, data) +#define MREPEAT169(macro, data) MREPEAT168(macro, data) macro(168, data) +#define MREPEAT170(macro, data) MREPEAT169(macro, data) macro(169, data) +#define MREPEAT171(macro, data) MREPEAT170(macro, data) macro(170, data) +#define MREPEAT172(macro, data) MREPEAT171(macro, data) macro(171, data) +#define MREPEAT173(macro, data) MREPEAT172(macro, data) macro(172, data) +#define MREPEAT174(macro, data) MREPEAT173(macro, data) macro(173, data) +#define MREPEAT175(macro, data) MREPEAT174(macro, data) macro(174, data) +#define MREPEAT176(macro, data) MREPEAT175(macro, data) macro(175, data) +#define MREPEAT177(macro, data) MREPEAT176(macro, data) macro(176, data) +#define MREPEAT178(macro, data) MREPEAT177(macro, data) macro(177, data) +#define MREPEAT179(macro, data) MREPEAT178(macro, data) macro(178, data) +#define MREPEAT180(macro, data) MREPEAT179(macro, data) macro(179, data) +#define MREPEAT181(macro, data) MREPEAT180(macro, data) macro(180, data) +#define MREPEAT182(macro, data) MREPEAT181(macro, data) macro(181, data) +#define MREPEAT183(macro, data) MREPEAT182(macro, data) macro(182, data) +#define MREPEAT184(macro, data) MREPEAT183(macro, data) macro(183, data) +#define MREPEAT185(macro, data) MREPEAT184(macro, data) macro(184, data) +#define MREPEAT186(macro, data) MREPEAT185(macro, data) macro(185, data) +#define MREPEAT187(macro, data) MREPEAT186(macro, data) macro(186, data) +#define MREPEAT188(macro, data) MREPEAT187(macro, data) macro(187, data) +#define MREPEAT189(macro, data) MREPEAT188(macro, data) macro(188, data) +#define MREPEAT190(macro, data) MREPEAT189(macro, data) macro(189, data) +#define MREPEAT191(macro, data) MREPEAT190(macro, data) macro(190, data) +#define MREPEAT192(macro, data) MREPEAT191(macro, data) macro(191, data) +#define MREPEAT193(macro, data) MREPEAT192(macro, data) macro(192, data) +#define MREPEAT194(macro, data) MREPEAT193(macro, data) macro(193, data) +#define MREPEAT195(macro, data) MREPEAT194(macro, data) macro(194, data) +#define MREPEAT196(macro, data) MREPEAT195(macro, data) macro(195, data) +#define MREPEAT197(macro, data) MREPEAT196(macro, data) macro(196, data) +#define MREPEAT198(macro, data) MREPEAT197(macro, data) macro(197, data) +#define MREPEAT199(macro, data) MREPEAT198(macro, data) macro(198, data) +#define MREPEAT200(macro, data) MREPEAT199(macro, data) macro(199, data) +#define MREPEAT201(macro, data) MREPEAT200(macro, data) macro(200, data) +#define MREPEAT202(macro, data) MREPEAT201(macro, data) macro(201, data) +#define MREPEAT203(macro, data) MREPEAT202(macro, data) macro(202, data) +#define MREPEAT204(macro, data) MREPEAT203(macro, data) macro(203, data) +#define MREPEAT205(macro, data) MREPEAT204(macro, data) macro(204, data) +#define MREPEAT206(macro, data) MREPEAT205(macro, data) macro(205, data) +#define MREPEAT207(macro, data) MREPEAT206(macro, data) macro(206, data) +#define MREPEAT208(macro, data) MREPEAT207(macro, data) macro(207, data) +#define MREPEAT209(macro, data) MREPEAT208(macro, data) macro(208, data) +#define MREPEAT210(macro, data) MREPEAT209(macro, data) macro(209, data) +#define MREPEAT211(macro, data) MREPEAT210(macro, data) macro(210, data) +#define MREPEAT212(macro, data) MREPEAT211(macro, data) macro(211, data) +#define MREPEAT213(macro, data) MREPEAT212(macro, data) macro(212, data) +#define MREPEAT214(macro, data) MREPEAT213(macro, data) macro(213, data) +#define MREPEAT215(macro, data) MREPEAT214(macro, data) macro(214, data) +#define MREPEAT216(macro, data) MREPEAT215(macro, data) macro(215, data) +#define MREPEAT217(macro, data) MREPEAT216(macro, data) macro(216, data) +#define MREPEAT218(macro, data) MREPEAT217(macro, data) macro(217, data) +#define MREPEAT219(macro, data) MREPEAT218(macro, data) macro(218, data) +#define MREPEAT220(macro, data) MREPEAT219(macro, data) macro(219, data) +#define MREPEAT221(macro, data) MREPEAT220(macro, data) macro(220, data) +#define MREPEAT222(macro, data) MREPEAT221(macro, data) macro(221, data) +#define MREPEAT223(macro, data) MREPEAT222(macro, data) macro(222, data) +#define MREPEAT224(macro, data) MREPEAT223(macro, data) macro(223, data) +#define MREPEAT225(macro, data) MREPEAT224(macro, data) macro(224, data) +#define MREPEAT226(macro, data) MREPEAT225(macro, data) macro(225, data) +#define MREPEAT227(macro, data) MREPEAT226(macro, data) macro(226, data) +#define MREPEAT228(macro, data) MREPEAT227(macro, data) macro(227, data) +#define MREPEAT229(macro, data) MREPEAT228(macro, data) macro(228, data) +#define MREPEAT230(macro, data) MREPEAT229(macro, data) macro(229, data) +#define MREPEAT231(macro, data) MREPEAT230(macro, data) macro(230, data) +#define MREPEAT232(macro, data) MREPEAT231(macro, data) macro(231, data) +#define MREPEAT233(macro, data) MREPEAT232(macro, data) macro(232, data) +#define MREPEAT234(macro, data) MREPEAT233(macro, data) macro(233, data) +#define MREPEAT235(macro, data) MREPEAT234(macro, data) macro(234, data) +#define MREPEAT236(macro, data) MREPEAT235(macro, data) macro(235, data) +#define MREPEAT237(macro, data) MREPEAT236(macro, data) macro(236, data) +#define MREPEAT238(macro, data) MREPEAT237(macro, data) macro(237, data) +#define MREPEAT239(macro, data) MREPEAT238(macro, data) macro(238, data) +#define MREPEAT240(macro, data) MREPEAT239(macro, data) macro(239, data) +#define MREPEAT241(macro, data) MREPEAT240(macro, data) macro(240, data) +#define MREPEAT242(macro, data) MREPEAT241(macro, data) macro(241, data) +#define MREPEAT243(macro, data) MREPEAT242(macro, data) macro(242, data) +#define MREPEAT244(macro, data) MREPEAT243(macro, data) macro(243, data) +#define MREPEAT245(macro, data) MREPEAT244(macro, data) macro(244, data) +#define MREPEAT246(macro, data) MREPEAT245(macro, data) macro(245, data) +#define MREPEAT247(macro, data) MREPEAT246(macro, data) macro(246, data) +#define MREPEAT248(macro, data) MREPEAT247(macro, data) macro(247, data) +#define MREPEAT249(macro, data) MREPEAT248(macro, data) macro(248, data) +#define MREPEAT250(macro, data) MREPEAT249(macro, data) macro(249, data) +#define MREPEAT251(macro, data) MREPEAT250(macro, data) macro(250, data) +#define MREPEAT252(macro, data) MREPEAT251(macro, data) macro(251, data) +#define MREPEAT253(macro, data) MREPEAT252(macro, data) macro(252, data) +#define MREPEAT254(macro, data) MREPEAT253(macro, data) macro(253, data) +#define MREPEAT255(macro, data) MREPEAT254(macro, data) macro(254, data) +#define MREPEAT256(macro, data) MREPEAT255(macro, data) macro(255, data) + + +#endif // _MREPEAT_H_ diff --git a/20080212/Demo/AVR32_UC3/UTILS/PREPROCESSOR/preprocessor.h b/20080212/Demo/AVR32_UC3/UTILS/PREPROCESSOR/preprocessor.h new file mode 100644 index 000000000..8a5813ef6 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/UTILS/PREPROCESSOR/preprocessor.h @@ -0,0 +1,50 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Preprocessor utils. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef _PREPROCESSOR_H_ +#define _PREPROCESSOR_H_ + +#include "tpaste.h" +#include "stringz.h" +#include "mrepeat.h" + + +#endif // _PREPROCESSOR_H_ diff --git a/20080212/Demo/AVR32_UC3/UTILS/PREPROCESSOR/stringz.h b/20080212/Demo/AVR32_UC3/UTILS/PREPROCESSOR/stringz.h new file mode 100644 index 000000000..8230b69e1 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/UTILS/PREPROCESSOR/stringz.h @@ -0,0 +1,70 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Preprocessor stringizing utils. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef _STRINGZ_H_ +#define _STRINGZ_H_ + + +/*! \brief Stringize. + * + * Stringize a preprocessing token, this token being allowed to be \#defined. + * + * May be used only within macros with the token passed as an argument if the token is \#defined. + * + * For example, writing STRINGZ(PIN) within a macro \#defined by PIN_NAME(PIN) + * and invoked as PIN_NAME(PIN0) with PIN0 \#defined as A0 is equivalent to + * writing "A0". + */ +#define STRINGZ(x) #x + +/*! \brief Absolute stringize. + * + * Stringize a preprocessing token, this token being allowed to be \#defined. + * + * No restriction of use if the token is \#defined. + * + * For example, writing ASTRINGZ(PIN0) anywhere with PIN0 \#defined as A0 is + * equivalent to writing "A0". + */ +#define ASTRINGZ(x) STRINGZ(x) + + +#endif // _STRINGZ_H_ diff --git a/20080212/Demo/AVR32_UC3/UTILS/PREPROCESSOR/tpaste.h b/20080212/Demo/AVR32_UC3/UTILS/PREPROCESSOR/tpaste.h new file mode 100644 index 000000000..ed1fe9cf6 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/UTILS/PREPROCESSOR/tpaste.h @@ -0,0 +1,90 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Preprocessor token pasting utils. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef _TPASTE_H_ +#define _TPASTE_H_ + + +/*! \name Token Paste + * + * Paste N preprocessing tokens together, these tokens being allowed to be \#defined. + * + * May be used only within macros with the tokens passed as arguments if the tokens are \#defined. + * + * For example, writing TPASTE2(U, WIDTH) within a macro \#defined by + * UTYPE(WIDTH) and invoked as UTYPE(UL_WIDTH) with UL_WIDTH \#defined as 32 is + * equivalent to writing U32. + */ +//! @{ +#define TPASTE2( a, b) a##b +#define TPASTE3( a, b, c) a##b##c +#define TPASTE4( a, b, c, d) a##b##c##d +#define TPASTE5( a, b, c, d, e) a##b##c##d##e +#define TPASTE6( a, b, c, d, e, f) a##b##c##d##e##f +#define TPASTE7( a, b, c, d, e, f, g) a##b##c##d##e##f##g +#define TPASTE8( a, b, c, d, e, f, g, h) a##b##c##d##e##f##g##h +#define TPASTE9( a, b, c, d, e, f, g, h, i) a##b##c##d##e##f##g##h##i +#define TPASTE10(a, b, c, d, e, f, g, h, i, j) a##b##c##d##e##f##g##h##i##j +//! @} + +/*! \name Absolute Token Paste + * + * Paste N preprocessing tokens together, these tokens being allowed to be \#defined. + * + * No restriction of use if the tokens are \#defined. + * + * For example, writing ATPASTE2(U, UL_WIDTH) anywhere with UL_WIDTH \#defined + * as 32 is equivalent to writing U32. + */ +//! @{ +#define ATPASTE2( a, b) TPASTE2( a, b) +#define ATPASTE3( a, b, c) TPASTE3( a, b, c) +#define ATPASTE4( a, b, c, d) TPASTE4( a, b, c, d) +#define ATPASTE5( a, b, c, d, e) TPASTE5( a, b, c, d, e) +#define ATPASTE6( a, b, c, d, e, f) TPASTE6( a, b, c, d, e, f) +#define ATPASTE7( a, b, c, d, e, f, g) TPASTE7( a, b, c, d, e, f, g) +#define ATPASTE8( a, b, c, d, e, f, g, h) TPASTE8( a, b, c, d, e, f, g, h) +#define ATPASTE9( a, b, c, d, e, f, g, h, i) TPASTE9( a, b, c, d, e, f, g, h, i) +#define ATPASTE10(a, b, c, d, e, f, g, h, i, j) TPASTE10(a, b, c, d, e, f, g, h, i, j) +//! @} + + +#endif // _TPASTE_H_ diff --git a/20080212/Demo/AVR32_UC3/UTILS/compiler.h b/20080212/Demo/AVR32_UC3/UTILS/compiler.h new file mode 100644 index 000000000..70cc8d05c --- /dev/null +++ b/20080212/Demo/AVR32_UC3/UTILS/compiler.h @@ -0,0 +1,1018 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Compiler file for AVR32. + * + * This file defines commonly used types and macros. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef _COMPILER_H_ +#define _COMPILER_H_ + +#if (__GNUC__ && __AVR32__) || (__ICCAVR32__ || __AAVR32__) +# include +#endif +#if __ICCAVR32__ +# include +#endif +#include "preprocessor.h" + + +//_____ D E C L A R A T I O N S ____________________________________________ + +#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling. + +#include +#include + + +#if __ICCAVR32__ + +/*! \name Compiler Keywords + * + * Port of some keywords from GNU GCC for AVR32 to IAR Embedded Workbench for Atmel AVR32. + */ +//! @{ +#define __asm__ asm +#define __inline__ inline +#define __volatile__ +//! @} + +#endif + + +/*! \name Usual Types + */ +//! @{ +typedef unsigned char Bool; //!< Boolean. +typedef unsigned char U8 ; //!< 8-bit unsigned integer. +typedef unsigned short int U16; //!< 16-bit unsigned integer. +typedef unsigned long int U32; //!< 32-bit unsigned integer. +typedef unsigned long long int U64; //!< 64-bit unsigned integer. +typedef signed char S8 ; //!< 8-bit signed integer. +typedef signed short int S16; //!< 16-bit signed integer. +typedef signed long int S32; //!< 32-bit signed integer. +typedef signed long long int S64; //!< 64-bit signed integer. +typedef float F32; //!< 32-bit floating-point number. +typedef double F64; //!< 64-bit floating-point number. +//! @} + + +/*! \name Status Types + */ +//! @{ +typedef Bool Status_bool_t; //!< Boolean status. +typedef U8 Status_t; //!< 8-bit-coded status. +//! @} + + +/*! \name Aliasing Aggregate Types + */ +//! @{ + +//! 16-bit union. +typedef union +{ + U16 u16 ; + U8 u8 [2]; +} Union16; + +//! 32-bit union. +typedef union +{ + U32 u32 ; + U16 u16[2]; + U8 u8 [4]; +} Union32; + +//! 64-bit union. +typedef union +{ + U64 u64 ; + U32 u32[2]; + U16 u16[4]; + U8 u8 [8]; +} Union64; + +//! Union of pointers to 64-, 32-, 16- and 8-bit unsigned integers. +typedef union +{ + U64 *u64ptr; + U32 *u32ptr; + U16 *u16ptr; + U8 *u8ptr ; +} UnionPtr; + +//! Union of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers. +typedef union +{ + volatile U64 *u64ptr; + volatile U32 *u32ptr; + volatile U16 *u16ptr; + volatile U8 *u8ptr ; +} UnionVPtr; + +//! Union of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers. +typedef union +{ + const U64 *u64ptr; + const U32 *u32ptr; + const U16 *u16ptr; + const U8 *u8ptr ; +} UnionCPtr; + +//! Union of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers. +typedef union +{ + const volatile U64 *u64ptr; + const volatile U32 *u32ptr; + const volatile U16 *u16ptr; + const volatile U8 *u8ptr ; +} UnionCVPtr; + +//! Structure of pointers to 64-, 32-, 16- and 8-bit unsigned integers. +typedef struct +{ + U64 *u64ptr; + U32 *u32ptr; + U16 *u16ptr; + U8 *u8ptr ; +} StructPtr; + +//! Structure of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers. +typedef struct +{ + volatile U64 *u64ptr; + volatile U32 *u32ptr; + volatile U16 *u16ptr; + volatile U8 *u8ptr ; +} StructVPtr; + +//! Structure of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers. +typedef struct +{ + const U64 *u64ptr; + const U32 *u32ptr; + const U16 *u16ptr; + const U8 *u8ptr ; +} StructCPtr; + +//! Structure of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers. +typedef struct +{ + const volatile U64 *u64ptr; + const volatile U32 *u32ptr; + const volatile U16 *u16ptr; + const volatile U8 *u8ptr ; +} StructCVPtr; + +//! @} + +#endif // __AVR32_ABI_COMPILER__ + + +//_____ M A C R O S ________________________________________________________ + +/*! \name Usual Constants + */ +//! @{ +#define DISABLE 0 +#define ENABLE 1 +#define DISABLED 0 +#define ENABLED 1 +#define OFF 0 +#define ON 1 +#define FALSE 0 +#define TRUE 1 +#define KO 0 +#define OK 1 +#define PASS 0 +#define FAIL 1 +#define LOW 0 +#define HIGH 1 +#define CLR 0 +#define SET 1 +//! @} + + +#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling. + +/*! \name Bit-Field Handling + */ +//! @{ + +/*! \brief Reads the bits of a value specified by a given bit-mask. + * + * \param value Value to read bits from. + * \param mask Bit-mask indicating bits to read. + * + * \return Read bits. + */ +#define Rd_bits( value, mask) ((value) & (mask)) + +/*! \brief Writes the bits of a C lvalue specified by a given bit-mask. + * + * \param lvalue C lvalue to write bits to. + * \param mask Bit-mask indicating bits to write. + * \param bits Bits to write. + * + * \return Resulting value with written bits. + */ +#define Wr_bits(lvalue, mask, bits) ((lvalue) = ((lvalue) & ~(mask)) |\ + ((bits ) & (mask))) + +/*! \brief Tests the bits of a value specified by a given bit-mask. + * + * \param value Value of which to test bits. + * \param mask Bit-mask indicating bits to test. + * + * \return \c 1 if at least one of the tested bits is set, else \c 0. + */ +#define Tst_bits( value, mask) (Rd_bits(value, mask) != 0) + +/*! \brief Clears the bits of a C lvalue specified by a given bit-mask. + * + * \param lvalue C lvalue of which to clear bits. + * \param mask Bit-mask indicating bits to clear. + * + * \return Resulting value with cleared bits. + */ +#define Clr_bits(lvalue, mask) ((lvalue) &= ~(mask)) + +/*! \brief Sets the bits of a C lvalue specified by a given bit-mask. + * + * \param lvalue C lvalue of which to set bits. + * \param mask Bit-mask indicating bits to set. + * + * \return Resulting value with set bits. + */ +#define Set_bits(lvalue, mask) ((lvalue) |= (mask)) + +/*! \brief Toggles the bits of a C lvalue specified by a given bit-mask. + * + * \param lvalue C lvalue of which to toggle bits. + * \param mask Bit-mask indicating bits to toggle. + * + * \return Resulting value with toggled bits. + */ +#define Tgl_bits(lvalue, mask) ((lvalue) ^= (mask)) + +/*! \brief Reads the bit-field of a value specified by a given bit-mask. + * + * \param value Value to read a bit-field from. + * \param mask Bit-mask indicating the bit-field to read. + * + * \return Read bit-field. + */ +#define Rd_bitfield( value, mask) (Rd_bits( value, mask) >> ctz(mask)) + +/*! \brief Writes the bit-field of a C lvalue specified by a given bit-mask. + * + * \param lvalue C lvalue to write a bit-field to. + * \param mask Bit-mask indicating the bit-field to write. + * \param bitfield Bit-field to write. + * + * \return Resulting value with written bit-field. + */ +#define Wr_bitfield(lvalue, mask, bitfield) (Wr_bits(lvalue, mask, (U32)(bitfield) << ctz(mask))) + +//! @} + + +/*! \brief This macro is used to test fatal errors. + * + * The macro tests if the expression is FALSE. If it is, a fatal error is + * detected and the application hangs up. + * + * \param expr Expression to evaluate and supposed to be nonzero. + */ +#ifdef _ASSERT_ENABLE_ + #define Assert(expr) \ + {\ + if (!(expr)) while (TRUE);\ + } +#else + #define Assert(expr) +#endif + + +/*! \name Zero-Bit Counting + * + * Under AVR32-GCC, __builtin_clz and __builtin_ctz behave like macros when + * applied to constant expressions (values known at compile time), so they are + * more optimized than the use of the corresponding assembly instructions and + * they can be used as constant expressions e.g. to initialize objects having + * static storage duration, and like the corresponding assembly instructions + * when applied to non-constant expressions (values unknown at compile time), so + * they are more optimized than an assembly periphrasis. Hence, clz and ctz + * ensure a possible and optimized behavior for both constant and non-constant + * expressions. + */ +//! @{ + +/*! \brief Counts the leading zero bits of the given value considered as a 32-bit integer. + * + * \param u Value of which to count the leading zero bits. + * + * \return The count of leading zero bits in \a u. + */ +#if __GNUC__ + #define clz(u) __builtin_clz(u) +#elif __ICCAVR32__ + #define clz(u) __count_leading_zeros(u) +#endif + +/*! \brief Counts the trailing zero bits of the given value considered as a 32-bit integer. + * + * \param u Value of which to count the trailing zero bits. + * + * \return The count of trailing zero bits in \a u. + */ +#if __GNUC__ + #define ctz(u) __builtin_ctz(u) +#elif __ICCAVR32__ + #define ctz(u) __count_trailing_zeros(u) +#endif + +//! @} + + +/*! \name Alignment + */ +//! @{ + +/*! \brief Tests alignment of the number \a val with the \a n boundary. + * + * \param val Input value. + * \param n Boundary. + * + * \return \c 1 if the number \a val is aligned with the \a n boundary, else \c 0. + */ +#define Test_align(val, n ) (!Tst_bits( val, (n) - 1 ) ) + +/*! \brief Gets alignment of the number \a val with respect to the \a n boundary. + * + * \param val Input value. + * \param n Boundary. + * + * \return Alignment of the number \a val with respect to the \a n boundary. + */ +#define Get_align( val, n ) ( Rd_bits( val, (n) - 1 ) ) + +/*! \brief Sets alignment of the lvalue number \a lval to \a alg with respect to the \a n boundary. + * + * \param lval Input/output lvalue. + * \param n Boundary. + * \param alg Alignment. + * + * \return New value of \a lval resulting from its alignment set to \a alg with respect to the \a n boundary. + */ +#define Set_align(lval, n, alg) ( Wr_bits(lval, (n) - 1, alg) ) + +/*! \brief Aligns the number \a val with the upper \a n boundary. + * + * \param val Input value. + * \param n Boundary. + * + * \return Value resulting from the number \a val aligned with the upper \a n boundary. + */ +#define Align_up( val, n ) (((val) + ((n) - 1)) & ~((n) - 1)) + +/*! \brief Aligns the number \a val with the lower \a n boundary. + * + * \param val Input value. + * \param n Boundary. + * + * \return Value resulting from the number \a val aligned with the lower \a n boundary. + */ +#define Align_down(val, n ) ( (val) & ~((n) - 1)) + +//! @} + + +/*! \name Mathematics + * + * The same considerations as for clz and ctz apply here but AVR32-GCC does not + * provide built-in functions to access the assembly instructions abs, min and + * max and it does not produce them by itself in most cases, so two sets of + * macros are defined here: + * - Abs, Min and Max to apply to constant expressions (values known at + * compile time); + * - abs, min and max to apply to non-constant expressions (values unknown at + * compile time). + */ +//! @{ + +/*! \brief Takes the absolute value of \a a. + * + * \param a Input value. + * + * \return Absolute value of \a a. + * + * \note More optimized if only used with values known at compile time. + */ +#define Abs(a) (((a) < 0 ) ? -(a) : (a)) + +/*! \brief Takes the minimal value of \a a and \a b. + * + * \param a Input value. + * \param b Input value. + * + * \return Minimal value of \a a and \a b. + * + * \note More optimized if only used with values known at compile time. + */ +#define Min(a, b) (((a) < (b)) ? (a) : (b)) + +/*! \brief Takes the maximal value of \a a and \a b. + * + * \param a Input value. + * \param b Input value. + * + * \return Maximal value of \a a and \a b. + * + * \note More optimized if only used with values known at compile time. + */ +#define Max(a, b) (((a) > (b)) ? (a) : (b)) + +/*! \brief Takes the absolute value of \a a. + * + * \param a Input value. + * + * \return Absolute value of \a a. + * + * \note More optimized if only used with values unknown at compile time. + */ +#if __GNUC__ + #define abs(a) \ + (\ + {\ + int __value = (a);\ + __asm__ ("abs\t%0" : "+r" (__value) : : "cc");\ + __value;\ + }\ + ) +#elif __ICCAVR32__ + #define abs(a) Abs(a) +#endif + +/*! \brief Takes the minimal value of \a a and \a b. + * + * \param a Input value. + * \param b Input value. + * + * \return Minimal value of \a a and \a b. + * + * \note More optimized if only used with values unknown at compile time. + */ +#if __GNUC__ + #define min(a, b) \ + (\ + {\ + int __value, __arg_a = (a), __arg_b = (b);\ + __asm__ ("min\t%0, %1, %2" : "=r" (__value) : "r" (__arg_a), "r" (__arg_b));\ + __value;\ + }\ + ) +#elif __ICCAVR32__ + #define min(a, b) __min(a, b) +#endif + +/*! \brief Takes the maximal value of \a a and \a b. + * + * \param a Input value. + * \param b Input value. + * + * \return Maximal value of \a a and \a b. + * + * \note More optimized if only used with values unknown at compile time. + */ +#if __GNUC__ + #define max(a, b) \ + (\ + {\ + int __value, __arg_a = (a), __arg_b = (b);\ + __asm__ ("max\t%0, %1, %2" : "=r" (__value) : "r" (__arg_a), "r" (__arg_b));\ + __value;\ + }\ + ) +#elif __ICCAVR32__ + #define max(a, b) __max(a, b) +#endif + +//! @} + + +/*! \brief Calls the routine at address \a addr. + * + * It generates a long call opcode. + * + * For example, `Long_call(0x80000000)' generates a software reset on a UC3 if + * it is invoked from the CPU supervisor mode. + * + * \param addr Address of the routine to call. + * + * \note It may be used as a long jump opcode in some special cases. + */ +#define Long_call(addr) ((*(void (*)(void))(addr))()) + +/*! \brief Resets the CPU by software. + * + * \warning It shall not be called from the CPU application mode. + */ +#if __GNUC__ + #define Reset_CPU() \ + (\ + {\ + __asm__ __volatile__ (\ + "lddpc r9, 3f\n\t"\ + "mfsr r8, %[SR]\n\t"\ + "bfextu r8, r8, %[SR_MX_OFFSET], %[SR_MX_SIZE]\n\t"\ + "cp.w r8, 0b001\n\t"\ + "breq 0f\n\t"\ + "sub r8, pc, $ - 1f\n\t"\ + "pushm r8-r9\n\t"\ + "rete\n"\ + "0:\n\t"\ + "mtsr %[SR], r9\n"\ + "1:\n\t"\ + "mov r0, 0\n\t"\ + "mov r1, 0\n\t"\ + "mov r2, 0\n\t"\ + "mov r3, 0\n\t"\ + "mov r4, 0\n\t"\ + "mov r5, 0\n\t"\ + "mov r6, 0\n\t"\ + "mov r7, 0\n\t"\ + "mov r8, 0\n\t"\ + "mov r9, 0\n\t"\ + "mov r10, 0\n\t"\ + "mov r11, 0\n\t"\ + "mov r12, 0\n\t"\ + "mov sp, 0\n\t"\ + "stdsp sp[0], sp\n\t"\ + "ldmts sp, sp\n\t"\ + "mov lr, 0\n\t"\ + "lddpc pc, 2f\n\t"\ + ".balign 4\n"\ + "2:\n\t"\ + ".word _start\n"\ + "3:\n\t"\ + ".word %[RESET_SR]"\ + :\ + : [SR] "i" (AVR32_SR),\ + [SR_MX_OFFSET] "i" (AVR32_SR_M0_OFFSET),\ + [SR_MX_SIZE] "i" (AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE),\ + [RESET_SR] "i" (AVR32_SR_GM_MASK | AVR32_SR_EM_MASK | AVR32_SR_M0_MASK)\ + );\ + }\ + ) +#elif __ICCAVR32__ + #define Reset_CPU() \ + {\ + extern void *volatile __program_start;\ + __asm__ __volatile__ (\ + "mov r7, LWRD(__program_start)\n\t"\ + "orh r7, HWRD(__program_start)\n\t"\ + "mov r9, LWRD("ASTRINGZ(AVR32_SR_GM_MASK | AVR32_SR_EM_MASK | AVR32_SR_M0_MASK)")\n\t"\ + "orh r9, HWRD("ASTRINGZ(AVR32_SR_GM_MASK | AVR32_SR_EM_MASK | AVR32_SR_M0_MASK)")\n\t"\ + "mfsr r8, "ASTRINGZ(AVR32_SR)"\n\t"\ + "bfextu r8, r8, "ASTRINGZ(AVR32_SR_M0_OFFSET)", "ASTRINGZ(AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE)"\n\t"\ + "cp.w r8, 001b\n\t"\ + "breq $ + 10\n\t"\ + "sub r8, pc, -12\n\t"\ + "pushm r8-r9\n\t"\ + "rete\n\t"\ + "mtsr "ASTRINGZ(AVR32_SR)", r9\n\t"\ + "mov r0, 0\n\t"\ + "mov r1, 0\n\t"\ + "mov r2, 0\n\t"\ + "mov r3, 0\n\t"\ + "mov r4, 0\n\t"\ + "mov r5, 0\n\t"\ + "mov r6, 0\n\t"\ + "st.w r0[4], r7\n\t"\ + "mov r7, 0\n\t"\ + "mov r8, 0\n\t"\ + "mov r9, 0\n\t"\ + "mov r10, 0\n\t"\ + "mov r11, 0\n\t"\ + "mov r12, 0\n\t"\ + "mov sp, 0\n\t"\ + "stdsp sp[0], sp\n\t"\ + "ldmts sp, sp\n\t"\ + "mov lr, 0\n\t"\ + "ld.w pc, lr[4]"\ + );\ + __program_start;\ + } +#endif + + +/*! \name System Register Access + */ +//! @{ + +/*! \brief Gets the value of the \a sysreg system register. + * + * \param sysreg Address of the system register of which to get the value. + * + * \return Value of the \a sysreg system register. + */ +#if __GNUC__ + #define Get_system_register(sysreg) __builtin_mfsr(sysreg) +#elif __ICCAVR32__ + #define Get_system_register(sysreg) __get_system_register(sysreg) +#endif + +/*! \brief Sets the value of the \a sysreg system register to \a value. + * + * \param sysreg Address of the system register of which to set the value. + * \param value Value to set the \a sysreg system register to. + */ +#if __GNUC__ + #define Set_system_register(sysreg, value) __builtin_mtsr(sysreg, value) +#elif __ICCAVR32__ + #define Set_system_register(sysreg, value) __set_system_register(sysreg, value) +#endif + +//! @} + + +/*! \name CPU Status Register Access + */ +//! @{ + +/*! \brief Tells whether exceptions are globally enabled. + * + * \return \c 1 if exceptions are globally enabled, else \c 0. + */ +#define Is_global_exception_enabled() (!Tst_bits(Get_system_register(AVR32_SR), AVR32_SR_EM_MASK)) + +/*! \brief Disables exceptions globally. + */ +#if __GNUC__ + #define Disable_global_exception() ({__asm__ __volatile__ ("ssrf\t%0" : : "i" (AVR32_SR_EM_OFFSET));}) +#elif __ICCAVR32__ + #define Disable_global_exception() (__set_status_flag(AVR32_SR_EM_OFFSET)) +#endif + +/*! \brief Enables exceptions globally. + */ +#if __GNUC__ + #define Enable_global_exception() ({__asm__ __volatile__ ("csrf\t%0" : : "i" (AVR32_SR_EM_OFFSET));}) +#elif __ICCAVR32__ + #define Enable_global_exception() (__clear_status_flag(AVR32_SR_EM_OFFSET)) +#endif + +/*! \brief Tells whether interrupts are globally enabled. + * + * \return \c 1 if interrupts are globally enabled, else \c 0. + */ +#define Is_global_interrupt_enabled() (!Tst_bits(Get_system_register(AVR32_SR), AVR32_SR_GM_MASK)) + +/*! \brief Disables interrupts globally. + */ +#if __GNUC__ + #define Disable_global_interrupt() ({__asm__ __volatile__ ("ssrf\t%0\n\tnop\n\tnop" : : "i" (AVR32_SR_GM_OFFSET));}) +#elif __ICCAVR32__ + #define Disable_global_interrupt() {__asm__ __volatile__ ("ssrf\t"ASTRINGZ(AVR32_SR_GM_OFFSET)"\n\tnop\n\tnop");} +#endif + +/*! \brief Enables interrupts globally. + */ +#if __GNUC__ + #define Enable_global_interrupt() ({__asm__ __volatile__ ("csrf\t%0" : : "i" (AVR32_SR_GM_OFFSET));}) +#elif __ICCAVR32__ + #define Enable_global_interrupt() (__enable_interrupt()) +#endif + +/*! \brief Tells whether interrupt level \a int_lev is enabled. + * + * \param int_lev Interrupt level (0 to 3). + * + * \return \c 1 if interrupt level \a int_lev is enabled, else \c 0. + */ +#define Is_interrupt_level_enabled(int_lev) (!Tst_bits(Get_system_register(AVR32_SR), TPASTE3(AVR32_SR_I, int_lev, M_MASK))) + +/*! \brief Disables interrupt level \a int_lev. + * + * \param int_lev Interrupt level to disable (0 to 3). + */ +#if __GNUC__ + #define Disable_interrupt_level(int_lev) ({__asm__ __volatile__ ("ssrf\t%0\n\tnop\n\tnop" : : "i" (TPASTE3(AVR32_SR_I, int_lev, M_OFFSET)));}) +#elif __ICCAVR32__ + #define Disable_interrupt_level(int_lev) {__asm__ __volatile__ ("ssrf\t"ASTRINGZ(TPASTE3(AVR32_SR_I, int_lev, M_OFFSET))"\n\tnop\n\tnop");} +#endif + +/*! \brief Enables interrupt level \a int_lev. + * + * \param int_lev Interrupt level to enable (0 to 3). + */ +#if __GNUC__ + #define Enable_interrupt_level(int_lev) ({__asm__ __volatile__ ("csrf\t%0" : : "i" (TPASTE3(AVR32_SR_I, int_lev, M_OFFSET)));}) +#elif __ICCAVR32__ + #define Enable_interrupt_level(int_lev) (__clear_status_flag(TPASTE3(AVR32_SR_I, int_lev, M_OFFSET))) +#endif + +//! @} + + +/*! \name Debug Register Access + */ +//! @{ + +/*! \brief Gets the value of the \a dbgreg debug register. + * + * \param dbgreg Address of the debug register of which to get the value. + * + * \return Value of the \a dbgreg debug register. + */ +#if __GNUC__ + #define Get_debug_register(dbgreg) __builtin_mfdr(dbgreg) +#elif __ICCAVR32__ + #define Get_debug_register(dbgreg) __get_debug_register(dbgreg) +#endif + +/*! \brief Sets the value of the \a dbgreg debug register to \a value. + * + * \param dbgreg Address of the debug register of which to set the value. + * \param value Value to set the \a dbgreg debug register to. + */ +#if __GNUC__ + #define Set_debug_register(dbgreg, value) __builtin_mtdr(dbgreg, value) +#elif __ICCAVR32__ + #define Set_debug_register(dbgreg, value) __set_debug_register(dbgreg, value) +#endif + +//! @} + +#endif // __AVR32_ABI_COMPILER__ + + +//! Boolean evaluating MCU little endianism. +#if (__GNUC__ && __AVR32__) || (__ICCAVR32__ || __AAVR32__) + #define LITTLE_ENDIAN_MCU FALSE +#endif + +// Check that MCU endianism is correctly defined. +#ifndef LITTLE_ENDIAN_MCU + #error YOU MUST define the MCU endianism with LITTLE_ENDIAN_MCU: either FALSE or TRUE +#endif + +//! Boolean evaluating MCU big endianism. +#define BIG_ENDIAN_MCU (!LITTLE_ENDIAN_MCU) + + +#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling. + +/*! \name MCU Endianism Handling + */ +//! @{ + +#if LITTLE_ENDIAN_MCU + + #define LSB(u16) (((U8 *)&(u16))[0]) //!< Least significant byte of \a u16. + #define MSB(u16) (((U8 *)&(u16))[1]) //!< Most significant byte of \a u16. + + #define LSH(u32) (((U16 *)&(u32))[0]) //!< Least significant half-word of \a u32. + #define MSH(u32) (((U16 *)&(u32))[1]) //!< Most significant half-word of \a u32. + #define LSB0W(u32) (((U8 *)&(u32))[0]) //!< Least significant byte of 1st rank of \a u32. + #define LSB1W(u32) (((U8 *)&(u32))[1]) //!< Least significant byte of 2nd rank of \a u32. + #define LSB2W(u32) (((U8 *)&(u32))[2]) //!< Least significant byte of 3rd rank of \a u32. + #define LSB3W(u32) (((U8 *)&(u32))[3]) //!< Least significant byte of 4th rank of \a u32. + #define MSB3W(u32) LSB0W(u32) //!< Most significant byte of 4th rank of \a u32. + #define MSB2W(u32) LSB1W(u32) //!< Most significant byte of 3rd rank of \a u32. + #define MSB1W(u32) LSB2W(u32) //!< Most significant byte of 2nd rank of \a u32. + #define MSB0W(u32) LSB3W(u32) //!< Most significant byte of 1st rank of \a u32. + + #define LSW(u64) (((U32 *)&(u64))[0]) //!< Least significant word of \a u64. + #define MSW(u64) (((U32 *)&(u64))[1]) //!< Most significant word of \a u64. + #define LSH0(u64) (((U16 *)&(u64))[0]) //!< Least significant half-word of 1st rank of \a u64. + #define LSH1(u64) (((U16 *)&(u64))[1]) //!< Least significant half-word of 2nd rank of \a u64. + #define LSH2(u64) (((U16 *)&(u64))[2]) //!< Least significant half-word of 3rd rank of \a u64. + #define LSH3(u64) (((U16 *)&(u64))[3]) //!< Least significant half-word of 4th rank of \a u64. + #define MSH3(u64) LSH0(u64) //!< Most significant half-word of 4th rank of \a u64. + #define MSH2(u64) LSH1(u64) //!< Most significant half-word of 3rd rank of \a u64. + #define MSH1(u64) LSH2(u64) //!< Most significant half-word of 2nd rank of \a u64. + #define MSH0(u64) LSH3(u64) //!< Most significant half-word of 1st rank of \a u64. + #define LSB0D(u64) (((U8 *)&(u64))[0]) //!< Least significant byte of 1st rank of \a u64. + #define LSB1D(u64) (((U8 *)&(u64))[1]) //!< Least significant byte of 2nd rank of \a u64. + #define LSB2D(u64) (((U8 *)&(u64))[2]) //!< Least significant byte of 3rd rank of \a u64. + #define LSB3D(u64) (((U8 *)&(u64))[3]) //!< Least significant byte of 4th rank of \a u64. + #define LSB4D(u64) (((U8 *)&(u64))[4]) //!< Least significant byte of 5th rank of \a u64. + #define LSB5D(u64) (((U8 *)&(u64))[5]) //!< Least significant byte of 6th rank of \a u64. + #define LSB6D(u64) (((U8 *)&(u64))[6]) //!< Least significant byte of 7th rank of \a u64. + #define LSB7D(u64) (((U8 *)&(u64))[7]) //!< Least significant byte of 8th rank of \a u64. + #define MSB7D(u64) LSB0D(u64) //!< Most significant byte of 8th rank of \a u64. + #define MSB6D(u64) LSB1D(u64) //!< Most significant byte of 7th rank of \a u64. + #define MSB5D(u64) LSB2D(u64) //!< Most significant byte of 6th rank of \a u64. + #define MSB4D(u64) LSB3D(u64) //!< Most significant byte of 5th rank of \a u64. + #define MSB3D(u64) LSB4D(u64) //!< Most significant byte of 4th rank of \a u64. + #define MSB2D(u64) LSB5D(u64) //!< Most significant byte of 3rd rank of \a u64. + #define MSB1D(u64) LSB6D(u64) //!< Most significant byte of 2nd rank of \a u64. + #define MSB0D(u64) LSB7D(u64) //!< Most significant byte of 1st rank of \a u64. + +#else // BIG_ENDIAN_MCU + + #define MSB(u16) (((U8 *)&(u16))[0]) //!< Most significant byte of \a u16. + #define LSB(u16) (((U8 *)&(u16))[1]) //!< Least significant byte of \a u16. + + #define MSH(u32) (((U16 *)&(u32))[0]) //!< Most significant half-word of \a u32. + #define LSH(u32) (((U16 *)&(u32))[1]) //!< Least significant half-word of \a u32. + #define MSB0W(u32) (((U8 *)&(u32))[0]) //!< Most significant byte of 1st rank of \a u32. + #define MSB1W(u32) (((U8 *)&(u32))[1]) //!< Most significant byte of 2nd rank of \a u32. + #define MSB2W(u32) (((U8 *)&(u32))[2]) //!< Most significant byte of 3rd rank of \a u32. + #define MSB3W(u32) (((U8 *)&(u32))[3]) //!< Most significant byte of 4th rank of \a u32. + #define LSB3W(u32) MSB0W(u32) //!< Least significant byte of 4th rank of \a u32. + #define LSB2W(u32) MSB1W(u32) //!< Least significant byte of 3rd rank of \a u32. + #define LSB1W(u32) MSB2W(u32) //!< Least significant byte of 2nd rank of \a u32. + #define LSB0W(u32) MSB3W(u32) //!< Least significant byte of 1st rank of \a u32. + + #define MSW(u64) (((U32 *)&(u64))[0]) //!< Most significant word of \a u64. + #define LSW(u64) (((U32 *)&(u64))[1]) //!< Least significant word of \a u64. + #define MSH0(u64) (((U16 *)&(u64))[0]) //!< Most significant half-word of 1st rank of \a u64. + #define MSH1(u64) (((U16 *)&(u64))[1]) //!< Most significant half-word of 2nd rank of \a u64. + #define MSH2(u64) (((U16 *)&(u64))[2]) //!< Most significant half-word of 3rd rank of \a u64. + #define MSH3(u64) (((U16 *)&(u64))[3]) //!< Most significant half-word of 4th rank of \a u64. + #define LSH3(u64) MSH0(u64) //!< Least significant half-word of 4th rank of \a u64. + #define LSH2(u64) MSH1(u64) //!< Least significant half-word of 3rd rank of \a u64. + #define LSH1(u64) MSH2(u64) //!< Least significant half-word of 2nd rank of \a u64. + #define LSH0(u64) MSH3(u64) //!< Least significant half-word of 1st rank of \a u64. + #define MSB0D(u64) (((U8 *)&(u64))[0]) //!< Most significant byte of 1st rank of \a u64. + #define MSB1D(u64) (((U8 *)&(u64))[1]) //!< Most significant byte of 2nd rank of \a u64. + #define MSB2D(u64) (((U8 *)&(u64))[2]) //!< Most significant byte of 3rd rank of \a u64. + #define MSB3D(u64) (((U8 *)&(u64))[3]) //!< Most significant byte of 4th rank of \a u64. + #define MSB4D(u64) (((U8 *)&(u64))[4]) //!< Most significant byte of 5th rank of \a u64. + #define MSB5D(u64) (((U8 *)&(u64))[5]) //!< Most significant byte of 6th rank of \a u64. + #define MSB6D(u64) (((U8 *)&(u64))[6]) //!< Most significant byte of 7th rank of \a u64. + #define MSB7D(u64) (((U8 *)&(u64))[7]) //!< Most significant byte of 8th rank of \a u64. + #define LSB7D(u64) MSB0D(u64) //!< Least significant byte of 8th rank of \a u64. + #define LSB6D(u64) MSB1D(u64) //!< Least significant byte of 7th rank of \a u64. + #define LSB5D(u64) MSB2D(u64) //!< Least significant byte of 6th rank of \a u64. + #define LSB4D(u64) MSB3D(u64) //!< Least significant byte of 5th rank of \a u64. + #define LSB3D(u64) MSB4D(u64) //!< Least significant byte of 4th rank of \a u64. + #define LSB2D(u64) MSB5D(u64) //!< Least significant byte of 3rd rank of \a u64. + #define LSB1D(u64) MSB6D(u64) //!< Least significant byte of 2nd rank of \a u64. + #define LSB0D(u64) MSB7D(u64) //!< Least significant byte of 1st rank of \a u64. + +#endif + +//! @} + + +/*! \name Endianism Conversion + * + * The same considerations as for clz and ctz apply here but AVR32-GCC's + * __builtin_bswap_16 and __builtin_bswap_32 do not behave like macros when + * applied to constant expressions, so two sets of macros are defined here: + * - Swap16, Swap32 and Swap64 to apply to constant expressions (values known + * at compile time); + * - swap16, swap32 and swap64 to apply to non-constant expressions (values + * unknown at compile time). + */ +//! @{ + +/*! \brief Toggles the endianism of \a u16 (by swapping its bytes). + * + * \param u16 U16 of which to toggle the endianism. + * + * \return Value resulting from \a u16 with toggled endianism. + * + * \note More optimized if only used with values known at compile time. + */ +#define Swap16(u16) ((U16)(((U16)(u16) >> 8) |\ + ((U16)(u16) << 8))) + +/*! \brief Toggles the endianism of \a u32 (by swapping its bytes). + * + * \param u32 U32 of which to toggle the endianism. + * + * \return Value resulting from \a u32 with toggled endianism. + * + * \note More optimized if only used with values known at compile time. + */ +#define Swap32(u32) ((U32)(((U32)Swap16((U32)(u32) >> 16)) |\ + ((U32)Swap16((U32)(u32)) << 16))) + +/*! \brief Toggles the endianism of \a u64 (by swapping its bytes). + * + * \param u64 U64 of which to toggle the endianism. + * + * \return Value resulting from \a u64 with toggled endianism. + * + * \note More optimized if only used with values known at compile time. + */ +#define Swap64(u64) ((U64)(((U64)Swap32((U64)(u64) >> 32)) |\ + ((U64)Swap32((U64)(u64)) << 32))) + +/*! \brief Toggles the endianism of \a u16 (by swapping its bytes). + * + * \param u16 U16 of which to toggle the endianism. + * + * \return Value resulting from \a u16 with toggled endianism. + * + * \note More optimized if only used with values unknown at compile time. + */ +#if __GNUC__ + #define swap16(u16) ((U16)__builtin_bswap_16((U16)(u16))) +#elif __ICCAVR32__ + #define swap16(u16) ((U16)__swap_bytes_in_halfwords((U16)(u16))) +#endif + +/*! \brief Toggles the endianism of \a u32 (by swapping its bytes). + * + * \param u32 U32 of which to toggle the endianism. + * + * \return Value resulting from \a u32 with toggled endianism. + * + * \note More optimized if only used with values unknown at compile time. + */ +#if __GNUC__ + #define swap32(u32) ((U32)__builtin_bswap_32((U32)(u32))) +#elif __ICCAVR32__ + #define swap32(u32) ((U32)__swap_bytes((U32)(u32))) +#endif + +/*! \brief Toggles the endianism of \a u64 (by swapping its bytes). + * + * \param u64 U64 of which to toggle the endianism. + * + * \return Value resulting from \a u64 with toggled endianism. + * + * \note More optimized if only used with values unknown at compile time. + */ +#define swap64(u64) ((U64)(((U64)swap32((U64)(u64) >> 32)) |\ + ((U64)swap32((U64)(u64)) << 32))) + +//! @} + + +/*! \name Target Abstraction + */ +//! @{ + +#define _GLOBEXT_ extern //!< extern storage-class specifier. +#define _CONST_TYPE_ const //!< const type qualifier. +#define _MEM_TYPE_SLOW_ //!< Slow memory type. +#define _MEM_TYPE_MEDFAST_ //!< Fairly fast memory type. +#define _MEM_TYPE_FAST_ //!< Fast memory type. + +typedef U8 Byte; //!< 8-bit unsigned integer. + +#define memcmp_ram2ram memcmp //!< Target-specific memcmp of RAM to RAM. +#define memcmp_code2ram memcmp //!< Target-specific memcmp of RAM to NVRAM. +#define memcpy_ram2ram memcpy //!< Target-specific memcpy from RAM to RAM. +#define memcpy_code2ram memcpy //!< Target-specific memcpy from NVRAM to RAM. + +#define LSB0(u32) LSB0W(u32) //!< Least significant byte of 1st rank of \a u32. +#define LSB1(u32) LSB1W(u32) //!< Least significant byte of 2nd rank of \a u32. +#define LSB2(u32) LSB2W(u32) //!< Least significant byte of 3rd rank of \a u32. +#define LSB3(u32) LSB3W(u32) //!< Least significant byte of 4th rank of \a u32. +#define MSB3(u32) MSB3W(u32) //!< Most significant byte of 4th rank of \a u32. +#define MSB2(u32) MSB2W(u32) //!< Most significant byte of 3rd rank of \a u32. +#define MSB1(u32) MSB1W(u32) //!< Most significant byte of 2nd rank of \a u32. +#define MSB0(u32) MSB0W(u32) //!< Most significant byte of 1st rank of \a u32. + +//! @} + +#endif // __AVR32_ABI_COMPILER__ + + +#endif // _COMPILER_H_ diff --git a/20080212/Demo/AVR32_UC3/documentation.h b/20080212/Demo/AVR32_UC3/documentation.h new file mode 100644 index 000000000..aefc799be --- /dev/null +++ b/20080212/Demo/AVR32_UC3/documentation.h @@ -0,0 +1,72 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief FreeRTOS application example for AVR32 UC3. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/*! \mainpage + * \section intro Introduction + * + * This is the documentation for the data structures, functions, variables, + * defines, enums, and typedefs for the FreeRTOS application. + * + * \image html freertos.gif + * + * FreeRTOS.orgTM is a portable, open source, mini Real Time Kernel - a + * free to download and royalty free RTOS that can be used in commercial + * applications (see license text). This site shows how a complete embedded + * real time system can be created from a Windows host using quality open + * source development tools (where available). See the FreeRTOS.org features + * summary. + * Highlights include: + * - Free RTOS kernel - preemptive, cooperative and hybrid configuration options. + * - Designed to be small, simple and easy to use. + * - Very portable code structure predominantly written in C. + * - Supports both tasks and co-routines. + * - No software restriction on the number of tasks that can be created. + * - No software restriction on the number of priorities that can be used. + * - No restrictions imposed on priority assignment - more than one task can be assigned the same priority. + * - Queues and semaphores for communication and synchronisation between tasks, or between tasks and interrupts. + * - Free embedded software source code. + * - Royalty free. + * - Cross development from a standard Windows host. + * - Pre-configured demo applications for selected single board computers allowing 'out of the box' operation and fast learning curve. + * - Compile time configuration allows small FLASH footprint + * - The SafeRTOS derivative product provides a high level of confidence in the code integrity. + * + * \section files Main Files + * - main.c : FreeRTOS example + * + * \section compilinfo Compilation Information + * This software is written for GNU GCC for AVR32 and for IAR Embedded Workbench + * for Atmel AVR32. Other compilers may or may not work. + * + * \section deviceinfo Device Information + * All AVR32 devices can be used. + * + * \section configinfo Configuration Information + * This example has been tested with the following configuration: + * - EVK1100 evaluation kit; + * - CPU clock: 12 MHz; + * - USART0 connected to a PC serial port via a standard RS232 DB9 cable; + * - PC terminal settings: + * - 57600 bps, + * - 8 data bits, + * - no parity bit, + * - 1 stop bit, + * - no flow control. + * + * \section contactinfo Contact Information + * For further information, visit + * Atmel AVR32. and + * FreeRTOS home page.\n + * Support and FAQ: http://support.atmel.no/ + */ diff --git a/20080212/Demo/AVR32_UC3/doxyfile.doxygen b/20080212/Demo/AVR32_UC3/doxyfile.doxygen new file mode 100644 index 000000000..17d8679e9 --- /dev/null +++ b/20080212/Demo/AVR32_UC3/doxyfile.doxygen @@ -0,0 +1,231 @@ +# Doxyfile 1.4.7 + +#--------------------------------------------------------------------------- +# Project related configuration options +#--------------------------------------------------------------------------- +PROJECT_NAME = "AVR32 UC3 - FreeRTOS Real Time Kernel" +PROJECT_NUMBER = +OUTPUT_DIRECTORY = +CREATE_SUBDIRS = NO +OUTPUT_LANGUAGE = English +USE_WINDOWS_ENCODING = YES +BRIEF_MEMBER_DESC = YES +REPEAT_BRIEF = YES +ABBREVIATE_BRIEF = +ALWAYS_DETAILED_SEC = NO +INLINE_INHERITED_MEMB = NO +FULL_PATH_NAMES = NO +STRIP_FROM_PATH = +STRIP_FROM_INC_PATH = +SHORT_NAMES = NO +JAVADOC_AUTOBRIEF = YES +MULTILINE_CPP_IS_BRIEF = NO +DETAILS_AT_TOP = YES +INHERIT_DOCS = YES +SEPARATE_MEMBER_PAGES = NO +TAB_SIZE = 4 +ALIASES = +OPTIMIZE_OUTPUT_FOR_C = YES +OPTIMIZE_OUTPUT_JAVA = NO +BUILTIN_STL_SUPPORT = NO +DISTRIBUTE_GROUP_DOC = NO +SUBGROUPING = YES +#--------------------------------------------------------------------------- +# Build related configuration options +#--------------------------------------------------------------------------- +EXTRACT_ALL = YES +EXTRACT_PRIVATE = NO +EXTRACT_STATIC = YES +EXTRACT_LOCAL_CLASSES = YES +EXTRACT_LOCAL_METHODS = NO +HIDE_UNDOC_MEMBERS = NO +HIDE_UNDOC_CLASSES = NO +HIDE_FRIEND_COMPOUNDS = NO +HIDE_IN_BODY_DOCS = NO +INTERNAL_DOCS = YES +CASE_SENSE_NAMES = YES +HIDE_SCOPE_NAMES = NO +SHOW_INCLUDE_FILES = YES +INLINE_INFO = YES +SORT_MEMBER_DOCS = YES +SORT_BRIEF_DOCS = YES +SORT_BY_SCOPE_NAME = NO +GENERATE_TODOLIST = YES +GENERATE_TESTLIST = YES +GENERATE_BUGLIST = YES +GENERATE_DEPRECATEDLIST= YES +ENABLED_SECTIONS = +MAX_INITIALIZER_LINES = 30 +SHOW_USED_FILES = NO +SHOW_DIRECTORIES = NO +FILE_VERSION_FILTER = +#--------------------------------------------------------------------------- +# configuration options related to warning and progress messages +#--------------------------------------------------------------------------- +QUIET = YES +WARNINGS = YES +WARN_IF_UNDOCUMENTED = YES +WARN_IF_DOC_ERROR = YES +WARN_NO_PARAMDOC = NO +WARN_FORMAT = "$file:$line: $text" +WARN_LOGFILE = +#--------------------------------------------------------------------------- +# configuration options related to the input files +#--------------------------------------------------------------------------- +INPUT = ./ ./../../Source ./../Common/include ./../Common/Minimal +FILE_PATTERNS = *.c \ + *.h +RECURSIVE = YES +EXCLUDE = +EXCLUDE_SYMLINKS = NO +EXCLUDE_PATTERNS = +EXAMPLE_PATH = +EXAMPLE_PATTERNS = +EXAMPLE_RECURSIVE = NO +IMAGE_PATH = ./ +INPUT_FILTER = +FILTER_PATTERNS = +FILTER_SOURCE_FILES = NO +#--------------------------------------------------------------------------- +# configuration options related to source browsing +#--------------------------------------------------------------------------- +SOURCE_BROWSER = YES +INLINE_SOURCES = YES +STRIP_CODE_COMMENTS = YES +REFERENCED_BY_RELATION = YES +REFERENCES_RELATION = YES +REFERENCES_LINK_SOURCE = YES +USE_HTAGS = NO +VERBATIM_HEADERS = YES +#--------------------------------------------------------------------------- +# configuration options related to the alphabetical class index +#--------------------------------------------------------------------------- +ALPHABETICAL_INDEX = NO +COLS_IN_ALPHA_INDEX = 5 +IGNORE_PREFIX = +#--------------------------------------------------------------------------- +# configuration options related to the HTML output +#--------------------------------------------------------------------------- +GENERATE_HTML = YES +HTML_OUTPUT = DOC +HTML_FILE_EXTENSION = .html +HTML_HEADER = +HTML_FOOTER = +HTML_STYLESHEET = +HTML_ALIGN_MEMBERS = YES +GENERATE_HTMLHELP = NO +CHM_FILE = +HHC_LOCATION = +GENERATE_CHI = NO +BINARY_TOC = NO +TOC_EXPAND = NO +DISABLE_INDEX = NO +ENUM_VALUES_PER_LINE = 4 +GENERATE_TREEVIEW = YES +TREEVIEW_WIDTH = 250 +#--------------------------------------------------------------------------- +# configuration options related to the LaTeX output +#--------------------------------------------------------------------------- +GENERATE_LATEX = NO +LATEX_OUTPUT = latex +LATEX_CMD_NAME = latex +MAKEINDEX_CMD_NAME = makeindex +COMPACT_LATEX = NO +PAPER_TYPE = a4wide +EXTRA_PACKAGES = +LATEX_HEADER = +PDF_HYPERLINKS = NO +USE_PDFLATEX = NO +LATEX_BATCHMODE = NO +LATEX_HIDE_INDICES = NO +#--------------------------------------------------------------------------- +# configuration options related to the RTF output +#--------------------------------------------------------------------------- +GENERATE_RTF = NO +RTF_OUTPUT = RTF +COMPACT_RTF = NO +RTF_HYPERLINKS = YES +RTF_STYLESHEET_FILE = +RTF_EXTENSIONS_FILE = +#--------------------------------------------------------------------------- +# configuration options related to the man page output +#--------------------------------------------------------------------------- +GENERATE_MAN = NO +MAN_OUTPUT = man +MAN_EXTENSION = .3 +MAN_LINKS = NO +#--------------------------------------------------------------------------- +# configuration options related to the XML output +#--------------------------------------------------------------------------- +GENERATE_XML = NO +XML_OUTPUT = xml +XML_SCHEMA = +XML_DTD = +XML_PROGRAMLISTING = YES +#--------------------------------------------------------------------------- +# configuration options for the AutoGen Definitions output +#--------------------------------------------------------------------------- +GENERATE_AUTOGEN_DEF = NO +#--------------------------------------------------------------------------- +# configuration options related to the Perl module output +#--------------------------------------------------------------------------- +GENERATE_PERLMOD = NO +PERLMOD_LATEX = NO +PERLMOD_PRETTY = YES +PERLMOD_MAKEVAR_PREFIX = +#--------------------------------------------------------------------------- +# Configuration options related to the preprocessor +#--------------------------------------------------------------------------- +ENABLE_PREPROCESSING = YES +MACRO_EXPANSION = YES +EXPAND_ONLY_PREDEF = YES +SEARCH_INCLUDES = YES +INCLUDE_PATH = +INCLUDE_FILE_PATTERNS = +PREDEFINED = __GNUC__=4 \ + __attribute__()= \ + __AVR32__=1 \ + __AVR32_UC3A0512__=1 \ + __AVR32_ABI_COMPILER__ \ + BOARD=EVK1100 +EXPAND_AS_DEFINED = +SKIP_FUNCTION_MACROS = YES +#--------------------------------------------------------------------------- +# Configuration::additions related to external references +#--------------------------------------------------------------------------- +TAGFILES = +GENERATE_TAGFILE = +ALLEXTERNALS = NO +EXTERNAL_GROUPS = YES +PERL_PATH = /usr/bin/perl +#--------------------------------------------------------------------------- +# Configuration options related to the dot tool +#--------------------------------------------------------------------------- +CLASS_DIAGRAMS = NO +HIDE_UNDOC_RELATIONS = YES +HAVE_DOT = NO +CLASS_GRAPH = NO +COLLABORATION_GRAPH = NO +GROUP_GRAPHS = NO +UML_LOOK = YES +TEMPLATE_RELATIONS = YES +INCLUDE_GRAPH = NO +INCLUDED_BY_GRAPH = NO +CALL_GRAPH = NO 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zd&Yx%Hu}FrqLDtXV$Z(wtIqimkX+RtQr+L9{cJPY2t$4oI`bwn>W#Y0m|`(RZ6)to z^yGQWq?BIwEVV27_vDePNv7%B=-qF#qu<`f45K0N$zB*r^KT< z*>iYo$qdi05Z6H`nyISEI-pGeHH}(W*~+%jSX|rhDYo)-hv{^e$8=Bhbo-}v^_J;Z zGtye?~b%>J?V*jK$GsH zB996-o9)?r>d!m6%Ayy4v)-vi@-^5oyhLrSlw3RJ1|DHblnpjp3OTiOWsl53GCZz?avZJ<$bK#`|Dw@6D>QY9?O%h{)vbFVGu7cCdGEf?~a wi~cMZtB7vzkqDrP%CCtkibR!dqAI?qCPU +#include +#include + +/* Environment header files. */ +#include "pm.h" + +/* Scheduler header files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo file headers. */ +#include "partest.h" +#include "serial.h" +#include "integer.h" +#include "comtest.h" +#include "flash.h" +#include "PollQ.h" +#include "semtest.h" +#include "dynamic.h" +#include "BlockQ.h" +#include "death.h" +#include "flop.h" + +/*! \name Priority definitions for most of the tasks in the demo application. + * Some tasks just use the idle priority. + */ +//! @{ +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +//! @} + +//! Baud rate used by the serial port tasks. +#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 57600 ) + +//! LED used by the serial port tasks. This is toggled on each character Tx, +//! and mainCOM_TEST_LED + 1 is toggled on each character Rx. +#define mainCOM_TEST_LED ( 3 ) + +//! LED that is toggled by the check task. The check task periodically checks +//! that all the other tasks are operating without error. If no errors are found +//! the LED is toggled. If an error is found at any time the LED toggles faster. +#define mainCHECK_TASK_LED ( 6 ) + +//! LED that is set upon error. +#define mainERROR_LED ( 7 ) + +//! The period between executions of the check task. +#define mainCHECK_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS ) + +//! If an error is detected in a task, the vErrorChecks task will enter in an +//! infinite loop flashing the LED at this rate. +#define mainERROR_FLASH_RATE ( (portTickType) 500 / portTICK_RATE_MS ) + +/*! \name Constants used by the vMemCheckTask() task. + */ +//! @{ +#define mainCOUNT_INITIAL_VALUE ( ( unsigned portLONG ) 0 ) +#define mainNO_TASK ( 0 ) +//! @} + +/*! \name The size of the memory blocks allocated by the vMemCheckTask() task. + */ +//! @{ +#define mainMEM_CHECK_SIZE_1 ( ( size_t ) 51 ) +#define mainMEM_CHECK_SIZE_2 ( ( size_t ) 52 ) +#define mainMEM_CHECK_SIZE_3 ( ( size_t ) 15 ) +//! @} + + +/*-----------------------------------------------------------*/ + +/* + * The task that executes at the highest priority and calls + * prvCheckOtherTasksAreStillRunning(). See the description at the top + * of the file. + */ +static void vErrorChecks( void *pvParameters ); + +/* + * Checks that all the demo application tasks are still executing without error + * - as described at the top of the file. + */ +static portBASE_TYPE prvCheckOtherTasksAreStillRunning( void ); + +/* + * A task that exercises the memory allocator. + */ +static void vMemCheckTask( void *pvParameters ); + +/* + * Called by the check task following the detection of an error to set the + * LEDs into a state that shows an error has beeen found. + */ +static void prvIndicateError( void ); + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + /* Start the crystal oscillator 0 and switch the main clock to it. */ + pm_switch_to_osc0(&AVR32_PM, FOSC0, OSC0_STARTUP); + + portDBG_TRACE("Starting the FreeRTOS AVR32 UC3 Demo..."); + + /* Setup the LED's for output. */ + vParTestInitialise(); + + /* Start the standard demo tasks. See the WEB documentation for more + information. */ + vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartDynamicPriorityTasks(); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vStartMathTasks( tskIDLE_PRIORITY ); + + /* Start the demo tasks defined within this file, specifically the check + task as described at the top of this file. */ + xTaskCreate( + vErrorChecks + , (const signed portCHAR *)"ErrCheck" + , configMINIMAL_STACK_SIZE + , NULL + , mainCHECK_TASK_PRIORITY + , NULL ); + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* Will only get here if there was insufficient memory to create the idle + task. */ + + return 0; +} +/*-----------------------------------------------------------*/ + +/*! + * \brief The task function for the "Check" task. + */ +static void vErrorChecks( void *pvParameters ) +{ +static volatile unsigned portLONG ulDummyVariable = 3UL; +unsigned portLONG ulMemCheckTaskRunningCount; +xTaskHandle xCreatedTask; +portBASE_TYPE bSuicidalTask = 0; + + /* The parameters are not used. Prevent compiler warnings. */ + ( void ) pvParameters; + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. + + In addition to the standard tests the memory allocator is tested through + the dynamic creation and deletion of a task each cycle. Each time the + task is created memory must be allocated for its stack. When the task is + deleted this memory is returned to the heap. If the task cannot be created + then it is likely that the memory allocation failed. */ + + for( ;; ) + { + /* Do this only once. */ + if( bSuicidalTask == 0 ) + { + bSuicidalTask++; + + /* This task has to be created last as it keeps account of the number of + tasks it expects to see running. However its implementation expects + to be called before vTaskStartScheduler(). We're in the case here where + vTaskStartScheduler() has already been called (thus the hidden IDLE task + has already been spawned). Since vCreateSuicidalTask() supposes that the + IDLE task isn't included in the response from uxTaskGetNumberOfTasks(), + let the MEM_CHECK task play that role. => this is why vCreateSuicidalTasks() + is not called as the last task. */ + vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); + } + + /* Reset xCreatedTask. This is modified by the task about to be + created so we can tell if it is executing correctly or not. */ + xCreatedTask = mainNO_TASK; + + /* Dynamically create a task - passing ulMemCheckTaskRunningCount as a + parameter. */ + ulMemCheckTaskRunningCount = mainCOUNT_INITIAL_VALUE; + + if( xTaskCreate( vMemCheckTask, + ( signed portCHAR * ) "MEM_CHECK", + configMINIMAL_STACK_SIZE, + ( void * ) &ulMemCheckTaskRunningCount, + tskIDLE_PRIORITY, &xCreatedTask ) != pdPASS ) + { + /* Could not create the task - we have probably run out of heap. + Don't go any further and flash the LED faster to provide visual + feedback of the error. */ + prvIndicateError(); + } + + /* Delay until it is time to execute again. */ + vTaskDelay( mainCHECK_PERIOD ); + + /* Delete the dynamically created task. */ + if( xCreatedTask != mainNO_TASK ) + { + vTaskDelete( xCreatedTask ); + } + + /* Perform a bit of 32bit maths to ensure the registers used by the + integer tasks get some exercise. The result here is not important - + see the demo application documentation for more info. */ + ulDummyVariable *= 3; + + /* Check all other tasks are still operating without error. + Check that vMemCheckTask did increment the counter. */ + if( ( prvCheckOtherTasksAreStillRunning() != pdFALSE ) + || ( ulMemCheckTaskRunningCount == mainCOUNT_INITIAL_VALUE ) ) + { + /* An error has occurred in one of the tasks. + Don't go any further and flash the LED faster to give visual + feedback of the error. */ + prvIndicateError(); + } + else + { + /* Toggle the LED if everything is okay. */ + vParTestToggleLED( mainCHECK_TASK_LED ); + } + } +} +/*-----------------------------------------------------------*/ + + +/*! + * \brief Checks that all the demo application tasks are still executing without error. + */ +static portBASE_TYPE prvCheckOtherTasksAreStillRunning( void ) +{ +static portBASE_TYPE xErrorHasOccurred = pdFALSE; + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + if( xAreMathsTaskStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + if( xIsCreateTaskStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + return ( xErrorHasOccurred ); +} +/*-----------------------------------------------------------*/ + + +/*! + * \brief Dynamically created and deleted during each cycle of the vErrorChecks() + * task. This is done to check the operation of the memory allocator. + * See the top of vErrorChecks for more details. + * + * \param *pvParameters Parameters for the task (can be of any kind) + */ +static void vMemCheckTask( void *pvParameters ) +{ +unsigned portLONG *pulMemCheckTaskRunningCounter; +void *pvMem1, *pvMem2, *pvMem3; +static portLONG lErrorOccurred = pdFALSE; + + /* This task is dynamically created then deleted during each cycle of the + vErrorChecks task to check the operation of the memory allocator. Each time + the task is created memory is allocated for the stack and TCB. Each time + the task is deleted this memory is returned to the heap. This task itself + exercises the allocator by allocating and freeing blocks. + + The task executes at the idle priority so does not require a delay. + + pulMemCheckTaskRunningCounter is incremented each cycle to indicate to the + vErrorChecks() task that this task is still executing without error. */ + + pulMemCheckTaskRunningCounter = ( unsigned portLONG * ) pvParameters; + + for( ;; ) + { + if( lErrorOccurred == pdFALSE ) + { + /* We have never seen an error so increment the counter. */ + ( *pulMemCheckTaskRunningCounter )++; + } + else + { + /* There has been an error so reset the counter so the check task + can tell that an error occurred. */ + *pulMemCheckTaskRunningCounter = mainCOUNT_INITIAL_VALUE; + } + + /* Allocate some memory - just to give the allocator some extra + exercise. This has to be in a critical section to ensure the + task does not get deleted while it has memory allocated. */ + + vTaskSuspendAll(); + { + pvMem1 = pvPortMalloc( mainMEM_CHECK_SIZE_1 ); + + if( pvMem1 == NULL ) + { + lErrorOccurred = pdTRUE; + } + else + { + memset( pvMem1, 0xaa, mainMEM_CHECK_SIZE_1 ); + vPortFree( pvMem1 ); + } + } + xTaskResumeAll(); + + /* Again - with a different size block. */ + vTaskSuspendAll(); + { + pvMem2 = pvPortMalloc( mainMEM_CHECK_SIZE_2 ); + + if( pvMem2 == NULL ) + { + lErrorOccurred = pdTRUE; + } + else + { + memset( pvMem2, 0xaa, mainMEM_CHECK_SIZE_2 ); + vPortFree( pvMem2 ); + } + } + xTaskResumeAll(); + + /* Again - with a different size block. */ + vTaskSuspendAll(); + { + pvMem3 = pvPortMalloc( mainMEM_CHECK_SIZE_3 ); + if( pvMem3 == NULL ) + { + lErrorOccurred = pdTRUE; + } + else + { + memset( pvMem3, 0xaa, mainMEM_CHECK_SIZE_3 ); + vPortFree( pvMem3 ); + } + } + xTaskResumeAll(); + } +} +/*-----------------------------------------------------------*/ + +static void prvIndicateError( void ) +{ + /* The check task has found an error in one of the other tasks. + Set the LEDs to a state that indicates this. */ + vParTestSetLED(mainERROR_LED,pdTRUE); + + for(;;) + { + #if( BOARD==EVK1100 ) + vParTestToggleLED( mainCHECK_TASK_LED ); + vTaskDelay( mainERROR_FLASH_RATE ); + #endif + #if ( BOARD==EVK1101 ) + vParTestSetLED( 0, pdTRUE ); + vParTestSetLED( 1, pdTRUE ); + vParTestSetLED( 2, pdTRUE ); + vParTestSetLED( 3, pdTRUE ); + #endif + } +} + diff --git a/20080212/Demo/AVR32_UC3/serial/serial.c b/20080212/Demo/AVR32_UC3/serial/serial.c new file mode 100644 index 000000000..c9424b55d --- /dev/null +++ b/20080212/Demo/AVR32_UC3/serial/serial.c @@ -0,0 +1,378 @@ +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief FreeRTOS Serial Port management example for AVR32 UC3. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + *****************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +/* + BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR USART. +*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "queue.h" +#include "task.h" + +/* Demo application includes. */ +#include "serial.h" +#include +#include "board.h" +#include "gpio.h" + +/*-----------------------------------------------------------*/ + +/* Constants to setup and access the USART. */ +#define serINVALID_COMPORT_HANDLER ( ( xComPortHandle ) 0 ) +#define serINVALID_QUEUE ( ( xQueueHandle ) 0 ) +#define serHANDLE ( ( xComPortHandle ) 1 ) +#define serNO_BLOCK ( ( portTickType ) 0 ) + +/*-----------------------------------------------------------*/ + +/* Queues used to hold received characters, and characters waiting to be +transmitted. */ +static xQueueHandle xRxedChars; +static xQueueHandle xCharsForTx; + +/*-----------------------------------------------------------*/ + +/* Forward declaration. */ +static void vprvSerialCreateQueues( unsigned portBASE_TYPE uxQueueLength, + xQueueHandle *pxRxedChars, + xQueueHandle *pxCharsForTx ); + +/*-----------------------------------------------------------*/ + +#if __GNUC__ + __attribute__((__noinline__)) +#elif __ICCAVR32__ + #pragma optimize = no_inline +#endif + +static portBASE_TYPE prvUSART_ISR_NonNakedBehaviour( void ) +{ + /* Now we can declare the local variables. */ + signed portCHAR cChar; + portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByRx = pdFALSE; + unsigned portLONG ulStatus; + volatile avr32_usart_t *usart = serialPORT_USART; + portBASE_TYPE retstatus; + + /* What caused the interrupt? */ + ulStatus = usart->csr & usart->imr; + + if (ulStatus & AVR32_USART_CSR_TXRDY_MASK) + { + /* The interrupt was caused by the THR becoming empty. Are there any + more characters to transmit? + Because FreeRTOS is not supposed to run with nested interrupts, put all OS + calls in a critical section . */ + portENTER_CRITICAL(); + retstatus = xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ); + portEXIT_CRITICAL(); + + if (retstatus == pdTRUE) + { + /* A character was retrieved from the queue so can be sent to the + THR now. */ + usart->thr = cChar; + } + else + { + /* Queue empty, nothing to send so turn off the Tx interrupt. */ + usart->idr = AVR32_USART_IDR_TXRDY_MASK; + } + } + + if (ulStatus & AVR32_USART_CSR_RXRDY_MASK) + { + /* The interrupt was caused by the receiver getting data. */ + cChar = usart->rhr; //TODO + + /* Because FreeRTOS is not supposed to run with nested interrupts, put all OS + calls in a critical section . */ + portENTER_CRITICAL(); + retstatus = xQueueSendFromISR(xRxedChars, &cChar, pdFALSE); + portEXIT_CRITICAL(); + + if( retstatus ) + { + xTaskWokenByRx = pdTRUE; + } + } + + /* The return value will be used by portEXIT_SWITCHING_ISR() to know if it + should perform a vTaskSwitchContext(). */ + return ( xTaskWokenByTx || xTaskWokenByRx ); +} +/*-----------------------------------------------------------*/ + +/* + * USART interrupt service routine. + */ +#if __GNUC__ + __attribute__((__naked__)) +#elif __ICCAVR32__ + #pragma shadow_registers = full // Naked. +#endif + +static void vUSART_ISR( void ) +{ + /* This ISR can cause a context switch, so the first statement must be a + call to the portENTER_SWITCHING_ISR() macro. This must be BEFORE any + variable declarations. */ + portENTER_SWITCHING_ISR(); + + prvUSART_ISR_NonNakedBehaviour(); + + /* Exit the ISR. If a task was woken by either a character being received + or transmitted then a context switch will occur. */ + portEXIT_SWITCHING_ISR(); +} +/*-----------------------------------------------------------*/ + + +/* + * Init the serial port for the Minimal implementation. + */ +xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) +{ +static const gpio_map_t USART_GPIO_MAP = +{ + { serialPORT_USART_RX_PIN, serialPORT_USART_RX_FUNCTION }, + { serialPORT_USART_TX_PIN, serialPORT_USART_TX_FUNCTION } +}; + +xComPortHandle xReturn = serHANDLE; +volatile avr32_usart_t *usart = serialPORT_USART; +int cd; /* USART Clock Divider. */ + + /* Create the rx and tx queues. */ + vprvSerialCreateQueues( uxQueueLength, &xRxedChars, &xCharsForTx ); + + /* Configure USART. */ + if( ( xRxedChars != serINVALID_QUEUE ) && + ( xCharsForTx != serINVALID_QUEUE ) && + ( ulWantedBaud != ( unsigned portLONG ) 0 ) ) + { + portENTER_CRITICAL(); + { + /** + ** Reset USART. + **/ + /* Disable all USART interrupt sources to begin... */ + usart->idr = 0xFFFFFFFF; + + /* Reset mode and other registers that could cause unpredictable + behaviour after reset */ + usart->mr = 0; /* Reset Mode register. */ + usart->rtor = 0; /* Reset Receiver Time-out register. */ + usart->ttgr = 0; /* Reset Transmitter Timeguard register. */ + + /* Shutdown RX and TX, reset status bits, reset iterations in CSR, reset NACK + and turn off DTR and RTS */ + usart->cr = AVR32_USART_CR_RSTRX_MASK | + AVR32_USART_CR_RSTTX_MASK | + AVR32_USART_CR_RXDIS_MASK | + AVR32_USART_CR_TXDIS_MASK | + AVR32_USART_CR_RSTSTA_MASK | + AVR32_USART_CR_RSTIT_MASK | + AVR32_USART_CR_RSTNACK_MASK | + AVR32_USART_CR_DTRDIS_MASK | + AVR32_USART_CR_RTSDIS_MASK; + + /** + ** Configure USART. + **/ + /* Enable USART RXD & TXD pins. */ + gpio_enable_module( USART_GPIO_MAP, sizeof( USART_GPIO_MAP ) / sizeof( USART_GPIO_MAP[0] ) ); + + /* Set the USART baudrate to be as close as possible to the wanted baudrate. */ + /* + * ** BAUDRATE CALCULATION ** + * + * Selected Clock Selected Clock + * baudrate = ---------------- or baudrate = ---------------- + * 16 x CD 8 x CD + * + * (with 16x oversampling) (with 8x oversampling) + */ + + if( ulWantedBaud < ( configCPU_CLOCK_HZ / 16 ) ) + { + /* Use 8x oversampling */ + usart->mr |= (1<brgr = (cd << AVR32_USART_BRGR_CD_OFFSET); + } + else + { + /* Use 16x oversampling */ + usart->mr &= ~(1< 65535 ) + { + /* Baudrate is too low */ + return serINVALID_COMPORT_HANDLER; + } + } + + usart->brgr = (cd << AVR32_USART_BRGR_CD_OFFSET); + + /* Set the USART Mode register: Mode=Normal(0), Clk selection=MCK(0), + CHRL=8, SYNC=0(asynchronous), PAR=None, NBSTOP=1, CHMODE=0, MSBF=0, + MODE9=0, CKLO=0, OVER(previously done when setting the baudrate), + other fields not used in this mode. */ + usart->mr |= ((8-5) << AVR32_USART_MR_CHRL_OFFSET ) | + ( 4 << AVR32_USART_MR_PAR_OFFSET ) | + ( 1 << AVR32_USART_MR_NBSTOP_OFFSET); + + /* Write the Transmit Timeguard Register */ + usart->ttgr = 0; + + + /* Register the USART interrupt handler to the interrupt controller and + enable the USART interrupt. */ + INTC_register_interrupt((__int_handler)&vUSART_ISR, serialPORT_USART_IRQ, INT1); + + /* Enable USART interrupt sources (but not Tx for now)... */ + usart->ier = AVR32_USART_IER_RXRDY_MASK; + + /* Enable receiver and transmitter... */ + usart->cr |= AVR32_USART_CR_TXEN_MASK | AVR32_USART_CR_RXEN_MASK; + } + portEXIT_CRITICAL(); + } + else + { + xReturn = serINVALID_COMPORT_HANDLER; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) +{ + /* The port handle is not required as this driver only supports UART0. */ + ( void ) pxPort; + + /* Get the next character from the buffer. Return false if no characters + are available, or arrive before xBlockTime expires. */ + if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) + { + return pdTRUE; + } + else + { + return pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength ) +{ +signed portCHAR *pxNext; + + /* NOTE: This implementation does not handle the queue being full as no + block time is used! */ + + /* The port handle is not required as this driver only supports UART0. */ + ( void ) pxPort; + + /* Send each character in the string, one at a time. */ + pxNext = ( signed portCHAR * ) pcString; + while( *pxNext ) + { + xSerialPutChar( pxPort, *pxNext, serNO_BLOCK ); + pxNext++; + } +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) +{ +volatile avr32_usart_t *usart = serialPORT_USART; + + /* Place the character in the queue of characters to be transmitted. */ + if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) + { + return pdFAIL; + } + + /* Turn on the Tx interrupt so the ISR will remove the character from the + queue and send it. This does not need to be in a critical section as + if the interrupt has already removed the character the next interrupt + will simply turn off the Tx interrupt again. */ + usart->ier = (1 << AVR32_USART_IER_TXRDY_OFFSET); + + return pdPASS; +} +/*-----------------------------------------------------------*/ + +void vSerialClose( xComPortHandle xPort ) +{ + /* Not supported as not required by the demo application. */ +} +/*-----------------------------------------------------------*/ + +/*###########################################################*/ + +/* + * Create the rx and tx queues. + */ +static void vprvSerialCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars, xQueueHandle *pxCharsForTx ) +{ + /* Create the queues used to hold Rx and Tx characters. */ + xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + + /* Pass back a reference to the queues so the serial API file can + post/receive characters. */ + *pxRxedChars = xRxedChars; + *pxCharsForTx = xCharsForTx; +} +/*-----------------------------------------------------------*/ diff --git a/20080212/Demo/AVR_ATMega323_IAR/FreeRTOSConfig.h b/20080212/Demo/AVR_ATMega323_IAR/FreeRTOSConfig.h new file mode 100644 index 000000000..6d36cd2b1 --- /dev/null +++ b/20080212/Demo/AVR_ATMega323_IAR/FreeRTOSConfig.h @@ -0,0 +1,89 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include + +#define configCALL_STACK_SIZE 20 + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 8000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 85 ) +#define configTOTAL_HEAP_SIZE ( (size_t ) ( 1500 ) ) +#define configMAX_TASK_NAME_LEN ( 8 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 1 +#define configIDLE_SHOULD_YIELD 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 1 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/AVR_ATMega323_IAR/ParTest/ParTest.c b/20080212/Demo/AVR_ATMega323_IAR/ParTest/ParTest.c new file mode 100644 index 000000000..31d806b5d --- /dev/null +++ b/20080212/Demo/AVR_ATMega323_IAR/ParTest/ParTest.c @@ -0,0 +1,133 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V2.0.0 + + + Use scheduler suspends in place of critical sections. + +Changes from V2.6.0 + + + Replaced the inb() and outb() functions with direct memory + access. This allows the port to be built with the 20050414 build of + WinAVR. +*/ + +#include "FreeRTOS.h" +#include "task.h" +#include "partest.h" + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +#define partstALL_BITS_OUTPUT ( ( unsigned portCHAR ) 0xff ) +#define partstALL_OUTPUTS_OFF ( ( unsigned portCHAR ) 0xff ) +#define partstMAX_OUTPUT_LED ( ( unsigned portCHAR ) 7 ) + +static volatile unsigned portCHAR ucCurrentOutputValue = partstALL_OUTPUTS_OFF; /*lint !e956 File scope parameters okay here. */ + +/*-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ + ucCurrentOutputValue = partstALL_OUTPUTS_OFF; + + /* Set port B direction to outputs. Start with all output off. */ + DDRB = partstALL_BITS_OUTPUT; + PORTB = ucCurrentOutputValue; +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ +unsigned portCHAR ucBit = ( unsigned portCHAR ) 1; + + if( uxLED <= partstMAX_OUTPUT_LED ) + { + ucBit <<= uxLED; + } + + vTaskSuspendAll(); + { + if( xValue == pdTRUE ) + { + ucBit ^= ( unsigned portCHAR ) 0xff; + ucCurrentOutputValue &= ucBit; + } + else + { + ucCurrentOutputValue |= ucBit; + } + + PORTB = ucCurrentOutputValue; + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned portCHAR ucBit; + + if( uxLED <= partstMAX_OUTPUT_LED ) + { + ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED; + + vTaskSuspendAll(); + { + if( ucCurrentOutputValue & ucBit ) + { + ucCurrentOutputValue &= ~ucBit; + } + else + { + ucCurrentOutputValue |= ucBit; + } + + PORTB = ucCurrentOutputValue; + } + xTaskResumeAll(); + } +} + + diff --git a/20080212/Demo/AVR_ATMega323_IAR/main.c b/20080212/Demo/AVR_ATMega323_IAR/main.c new file mode 100644 index 000000000..8467af102 --- /dev/null +++ b/20080212/Demo/AVR_ATMega323_IAR/main.c @@ -0,0 +1,289 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + * Creates all the demo application tasks, then starts the scheduler. The WEB + * documentation provides more details of the demo application tasks. + * + * Main. c also creates a task called "Check". This only executes every three + * seconds but has the highest priority so is guaranteed to get processor time. + * Its main function is to check that all the other tasks are still operational. + * Each task that does not flash an LED maintains a unique count that is + * incremented each time the task successfully completes its function. Should + * any error occur within such a task the count is permanently halted. The + * check task inspects the count of each task to ensure it has changed since + * the last time the check task executed. If all the count variables have + * changed all the tasks are still executing error free, and the check task + * toggles an LED. Should any task contain an error at any time the LED toggle + * will stop. + * + * The LED flash and communications test tasks do not maintain a count. + */ + +/* +Changes from V1.2.0 + + + Changed the baud rate for the serial test from 19200 to 57600. + +Changes from V1.2.3 + + + The integer and comtest tasks are now used when the cooperative scheduler + is being used. Previously they were only used with the preemptive + scheduler. + +Changes from V1.2.5 + + + Set the baud rate to 38400. This has a smaller error percentage with an + 8MHz clock (according to the manual). + +Changes from V2.0.0 + + + Delay periods are now specified using variables and constants of + portTickType rather than unsigned portLONG. + +Changes from V2.2.0 + + + File can now be built using either the IAR or WinAVR compiler. + +Changes from V2.6.1 + + + The IAR and WinAVR AVR ports are now maintained separately. + +Changes from V4.0.5 + + + Modified to demonstrate the use of co-routines. +*/ + +#include +#include + +#ifdef GCC_MEGA_AVR + /* EEPROM routines used only with the WinAVR compiler. */ + #include +#endif + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "croutine.h" + +/* Demo file headers. */ +#include "PollQ.h" +#include "integer.h" +#include "serial.h" +#include "comtest.h" +#include "crflash.h" +#include "print.h" +#include "partest.h" +#include "regtest.h" + +/* Priority definitions for most of the tasks in the demo application. Some +tasks just use the idle priority. */ +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) + +/* Baud rate used by the serial port tasks. */ +#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 38400 ) + +/* LED used by the serial port tasks. This is toggled on each character Tx, +and mainCOM_TEST_LED + 1 is toggles on each character Rx. */ +#define mainCOM_TEST_LED ( 4 ) + +/* LED that is toggled by the check task. The check task periodically checks +that all the other tasks are operating without error. If no errors are found +the LED is toggled. If an error is found at any time the LED is never toggles +again. */ +#define mainCHECK_TASK_LED ( 7 ) + +/* The period between executions of the check task. */ +#define mainCHECK_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS ) + +/* An address in the EEPROM used to count resets. This is used to check that +the demo application is not unexpectedly resetting. */ +#define mainRESET_COUNT_ADDRESS ( ( void * ) 0x50 ) + +/* The number of coroutines to create. */ +#define mainNUM_FLASH_COROUTINES ( 3 ) + +/* + * The task function for the "Check" task. + */ +static void vErrorChecks( void *pvParameters ); + +/* + * Checks the unique counts of other tasks to ensure they are still operational. + * Flashes an LED if everything is okay. + */ +static void prvCheckOtherTasksAreStillRunning( void ); + +/* + * Called on boot to increment a count stored in the EEPROM. This is used to + * ensure the CPU does not reset unexpectedly. + */ +static void prvIncrementResetCount( void ); + +/* + * Idle hook is used to scheduler co-routines. + */ +void vApplicationIdleHook( void ); + +portSHORT main( void ) +{ + prvIncrementResetCount(); + + /* Setup the LED's for output. */ + vParTestInitialise(); + + /* Create the standard demo tasks. */ + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartRegTestTasks(); + + /* Create the tasks defined within this file. */ + xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Create the co-routines that flash the LED's. */ + vStartFlashCoRoutines( mainNUM_FLASH_COROUTINES ); + + /* In this port, to use preemptive scheduler define configUSE_PREEMPTION + as 1 in portmacro.h. To use the cooperative scheduler define + configUSE_PREEMPTION as 0. */ + vTaskStartScheduler(); + + return 0; +} +/*-----------------------------------------------------------*/ + +static void vErrorChecks( void *pvParameters ) +{ +static volatile unsigned portLONG ulDummyVariable = 3UL; + + /* The parameters are not used. */ + ( void ) pvParameters; + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. */ + for( ;; ) + { + vTaskDelay( mainCHECK_PERIOD ); + + /* Perform a bit of 32bit maths to ensure the registers used by the + integer tasks get some exercise. The result here is not important - + see the demo application documentation for more info. */ + ulDummyVariable *= 3; + + prvCheckOtherTasksAreStillRunning(); + } +} +/*-----------------------------------------------------------*/ + +static void prvCheckOtherTasksAreStillRunning( void ) +{ +static portBASE_TYPE xErrorHasOccurred = pdFALSE; + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + if( xAreRegTestTasksStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + if( xErrorHasOccurred == pdFALSE ) + { + /* Toggle the LED if everything is okay so we know if an error occurs even if not + using console IO. */ + vParTestToggleLED( mainCHECK_TASK_LED ); + } +} +/*-----------------------------------------------------------*/ + +static void prvIncrementResetCount( void ) +{ +unsigned portCHAR ucCount; +const unsigned portCHAR ucReadBit = ( unsigned portCHAR ) 0x01; +const unsigned portCHAR ucWrite1 = ( unsigned portCHAR ) 0x04; +const unsigned portCHAR ucWrite2 = ( unsigned portCHAR ) 0x02; + + /* Increment the EEPROM value at 0x00. + + Setup the EEPROM address. */ + EEARH = 0x00; + EEARL = 0x00; + + /* Set the read enable bit. */ + EECR |= ucReadBit; + + /* Wait for the read. */ + while( EECR & ucReadBit ); + + /* The byte is ready. */ + ucCount = EEDR; + + /* Increment the reset count, then write the byte back. */ + ucCount++; + EEDR = ucCount; + EECR = ucWrite1; + EECR = ( ucWrite1 | ucWrite2 ); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ + vCoRoutineSchedule(); +} + diff --git a/20080212/Demo/AVR_ATMega323_IAR/regtest.c b/20080212/Demo/AVR_ATMega323_IAR/regtest.c new file mode 100644 index 000000000..7e2787d47 --- /dev/null +++ b/20080212/Demo/AVR_ATMega323_IAR/regtest.c @@ -0,0 +1,372 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo file headers. */ +#include "regtest.h" + +/* + * Test tasks that sets registers to known values, then checks to ensure the + * values remain as expected. Test 1 and test 2 use different values. + */ +static void prvRegisterCheck1( void *pvParameters ); +static void prvRegisterCheck2( void *pvParameters ); + +/* Set to a non zero value should an error be found. */ +portBASE_TYPE xRegTestError = pdFALSE; + +/*-----------------------------------------------------------*/ + +void vStartRegTestTasks( void ) +{ + xTaskCreate( prvRegisterCheck1, "Reg1", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + xTaskCreate( prvRegisterCheck2, "Reg2", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xAreRegTestTasksStillRunning( void ) +{ +portBASE_TYPE xReturn; + + /* If a register was found to contain an unexpected value then the + xRegTestError variable would have been set to a non zero value. */ + if( xRegTestError == pdFALSE ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +static void prvRegisterCheck1( void *pvParameters ) +{ + ( void ) pvParameters; + + for( ;; ) + { + asm( "LDI r31, 5" ); + asm( "MOV r0, r31" ); + asm( "LDI r31, 6" ); + asm( "MOV r1, r31" ); + asm( "LDI r31, 7" ); + asm( "MOV r2, r31" ); + asm( "LDI r31, 8" ); + asm( "MOV r3, r31" ); + asm( "LDI r31, 9" ); + asm( "MOV r4, r31" ); + asm( "LDI r31, 10" ); + asm( "MOV r5, r31" ); + asm( "LDI r31, 11" ); + asm( "MOV r6, r31" ); + asm( "LDI r31, 12" ); + asm( "MOV r7, r31" ); + asm( "LDI r31, 13" ); + asm( "MOV r8, r31" ); + asm( "LDI r31, 14" ); + asm( "MOV r9, r31" ); + asm( "LDI r31, 15" ); + asm( "MOV r10, r31" ); + asm( "LDI r31, 16" ); + asm( "MOV r11, r31" ); + asm( "LDI r31, 17" ); + asm( "MOV r12, r31" ); + asm( "LDI r31, 18" ); + asm( "MOV r13, r31" ); + asm( "LDI r31, 19" ); + asm( "MOV r14, r31" ); + asm( "LDI r31, 20" ); + asm( "MOV r15, r31" ); + asm( "LDI r16, 21" ); + asm( "LDI r17, 22" ); + asm( "LDI r18, 23" ); + asm( "LDI r19, 24" ); + asm( "LDI r20, 25" ); + asm( "LDI r21, 26" ); + asm( "LDI r22, 27" ); + asm( "LDI r23, 28" ); + asm( "LDI r24, 29" ); + asm( "LDI r25, 30" ); + asm( "LDI r26, 31" ); + asm( "LDI r27, 32" ); + asm( "LDI r30, 33" ); + + asm( "LDI r31, 5" ); + asm( "CPSE r31, r0" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 6" ); + asm( "CPSE r31, r1" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 7" ); + asm( "CPSE r31, r2" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 8" ); + asm( "CPSE r31, r3" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 9" ); + asm( "CPSE r31, r4" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 10" ); + asm( "CPSE r31, r5" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 11" ); + asm( "CPSE r31, r6" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 12" ); + asm( "CPSE r31, r7" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 13" ); + asm( "CPSE r31, r8" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 14" ); + asm( "CPSE r31, r9" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 15" ); + asm( "CPSE r31, r10" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 16" ); + asm( "CPSE r31, r11" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 17" ); + asm( "CPSE r31, r12" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 18" ); + asm( "CPSE r31, r13" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 19" ); + asm( "CPSE r31, r14" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 20" ); + asm( "CPSE r31, r15" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 21" ); + asm( "CPSE r31, r16" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 22" ); + asm( "CPSE r31, r17" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 23" ); + asm( "CPSE r31, r18" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 24" ); + asm( "CPSE r31, r19" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 25" ); + asm( "CPSE r31, r20" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 26" ); + asm( "CPSE r31, r21" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 27" ); + asm( "CPSE r31, r22" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 28" ); + asm( "CPSE r31, r23" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 29" ); + asm( "CPSE r31, r24" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 30" ); + asm( "CPSE r31, r25" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 31" ); + asm( "CPSE r31, r26" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 32" ); + asm( "CPSE r31, r27" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 33" ); + asm( "CPSE r31, r30" ); + asm( "STS xRegTestError, r0" ); + } +} +/*-----------------------------------------------------------*/ + +static void prvRegisterCheck2( void *pvParameters ) +{ + ( void ) pvParameters; + + for( ;; ) + { + asm( "LDI r31, 1" ); + asm( "MOV r0, r31" ); + asm( "LDI r31, 2" ); + asm( "MOV r1, r31" ); + asm( "LDI r31, 3" ); + asm( "MOV r2, r31" ); + asm( "LDI r31, 4" ); + asm( "MOV r3, r31" ); + asm( "LDI r31, 5" ); + asm( "MOV r4, r31" ); + asm( "LDI r31, 6" ); + asm( "MOV r5, r31" ); + asm( "LDI r31, 7" ); + asm( "MOV r6, r31" ); + asm( "LDI r31, 8" ); + asm( "MOV r7, r31" ); + asm( "LDI r31, 9" ); + asm( "MOV r8, r31" ); + asm( "LDI r31, 10" ); + asm( "MOV r9, r31" ); + asm( "LDI r31, 11" ); + asm( "MOV r10, r31" ); + asm( "LDI r31, 12" ); + asm( "MOV r11, r31" ); + asm( "LDI r31, 13" ); + asm( "MOV r12, r31" ); + asm( "LDI r31, 14" ); + asm( "MOV r13, r31" ); + asm( "LDI r31, 15" ); + asm( "MOV r14, r31" ); + asm( "LDI r31, 16" ); + asm( "MOV r15, r31" ); + asm( "LDI r16, 17" ); + asm( "LDI r17, 18" ); + asm( "LDI r18, 19" ); + asm( "LDI r19, 20" ); + asm( "LDI r20, 21" ); + asm( "LDI r21, 22" ); + asm( "LDI r22, 23" ); + asm( "LDI r23, 24" ); + asm( "LDI r24, 25" ); + asm( "LDI r25, 26" ); + asm( "LDI r26, 27" ); + asm( "LDI r27, 28" ); + asm( "LDI r30, 29" ); + + asm( "LDI r31, 1" ); + asm( "CPSE r31, r0" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 2" ); + asm( "CPSE r31, r1" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 3" ); + asm( "CPSE r31, r2" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 4" ); + asm( "CPSE r31, r3" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 5" ); + asm( "CPSE r31, r4" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 6" ); + asm( "CPSE r31, r5" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 7" ); + asm( "CPSE r31, r6" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 8" ); + asm( "CPSE r31, r7" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 9" ); + asm( "CPSE r31, r8" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 10" ); + asm( "CPSE r31, r9" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 11" ); + asm( "CPSE r31, r10" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 12" ); + asm( "CPSE r31, r11" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 13" ); + asm( "CPSE r31, r12" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 14" ); + asm( "CPSE r31, r13" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 15" ); + asm( "CPSE r31, r14" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 16" ); + asm( "CPSE r31, r15" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 17" ); + asm( "CPSE r31, r16" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 18" ); + asm( "CPSE r31, r17" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 19" ); + asm( "CPSE r31, r18" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 20" ); + asm( "CPSE r31, r19" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 21" ); + asm( "CPSE r31, r20" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 22" ); + asm( "CPSE r31, r21" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 23" ); + asm( "CPSE r31, r22" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 24" ); + asm( "CPSE r31, r23" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 25" ); + asm( "CPSE r31, r24" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 26" ); + asm( "CPSE r31, r25" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 27" ); + asm( "CPSE r31, r26" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 28" ); + asm( "CPSE r31, r27" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 29" ); + asm( "CPSE r31, r30" ); + asm( "STS xRegTestError, r0" ); + } +} + diff --git a/20080212/Demo/AVR_ATMega323_IAR/regtest.h b/20080212/Demo/AVR_ATMega323_IAR/regtest.h new file mode 100644 index 000000000..be12e78f4 --- /dev/null +++ b/20080212/Demo/AVR_ATMega323_IAR/regtest.h @@ -0,0 +1,50 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef REG_TEST_H +#define REG_TEST_H + +void vStartRegTestTasks( void ); +portBASE_TYPE xAreRegTestTasksStillRunning( void ); + +#endif + diff --git a/20080212/Demo/AVR_ATMega323_IAR/rtosdemo.ewd b/20080212/Demo/AVR_ATMega323_IAR/rtosdemo.ewd new file mode 100644 index 000000000..736675fdb --- /dev/null +++ b/20080212/Demo/AVR_ATMega323_IAR/rtosdemo.ewd @@ -0,0 +1,641 @@ + + + + 1 + + Debug + + AVR + + 1 + + C-SPY + 3 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + CCRAVR + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + + ICE200AVR + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + JTAGICEAVR + 3 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JTAGICEMKIIAVR + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + SIMAVR + 2 + + 1 + 1 + 1 + + + + + + + THIRDPARTYAVR + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ewplugin + 0 + + + $EW_DIR$\common\plugins\Profiling\Profiling.ewplugin + 1 + + + $EW_DIR$\common\plugins\Stack\stack.ewplugin + 1 + + + + + + diff --git a/20080212/Demo/AVR_ATMega323_IAR/rtosdemo.ewp b/20080212/Demo/AVR_ATMega323_IAR/rtosdemo.ewp new file mode 100644 index 000000000..c1b517e0d --- /dev/null +++ b/20080212/Demo/AVR_ATMega323_IAR/rtosdemo.ewp @@ -0,0 +1,1026 @@ + + + + 1 + + Debug + + AVR + + 1 + + General + 3 + + 6 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCAVR + 3 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AAVR + 3 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + XLINK + 2 + + 13 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + XAR + 2 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Demo Source + + $PROJ_DIR$\..\Common\Minimal\comtest.c + + + $PROJ_DIR$\..\Common\Minimal\crflash.c + + + $PROJ_DIR$\..\..\Source\portable\MemMang\heap_1.c + + + $PROJ_DIR$\..\Common\Minimal\integer.c + + + $PROJ_DIR$\main.c + + + $PROJ_DIR$\ParTest\ParTest.c + + + $PROJ_DIR$\..\Common\Minimal\PollQ.c + + + $PROJ_DIR$\regtest.c + + + $PROJ_DIR$\serial\serial.c + + + + Kernel Source + + $PROJ_DIR$\..\..\Source\croutine.c + + + $PROJ_DIR$\..\..\Source\list.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\ATMega323\port.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\ATMega323\portmacro.s90 + + + $PROJ_DIR$\..\..\Source\queue.c + + + $PROJ_DIR$\..\..\Source\tasks.c + + + + + diff --git a/20080212/Demo/AVR_ATMega323_IAR/rtosdemo.eww b/20080212/Demo/AVR_ATMega323_IAR/rtosdemo.eww new file mode 100644 index 000000000..2294aacb5 --- /dev/null +++ b/20080212/Demo/AVR_ATMega323_IAR/rtosdemo.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\rtosdemo.ewp + + + + + diff --git a/20080212/Demo/AVR_ATMega323_IAR/serial/serial.c b/20080212/Demo/AVR_ATMega323_IAR/serial/serial.c new file mode 100644 index 000000000..6d592fb40 --- /dev/null +++ b/20080212/Demo/AVR_ATMega323_IAR/serial/serial.c @@ -0,0 +1,205 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR IAR AVR PORT. */ + + +#include +#include "FreeRTOS.h" +#include "queue.h" +#include "task.h" +#include "serial.h" + +#define serBAUD_DIV_CONSTANT ( ( unsigned portLONG ) 16 ) + +/* Constants for writing to UCSRB. */ +#define serRX_INT_ENABLE ( ( unsigned portCHAR ) 0x80 ) +#define serRX_ENABLE ( ( unsigned portCHAR ) 0x10 ) +#define serTX_ENABLE ( ( unsigned portCHAR ) 0x08 ) +#define serTX_INT_ENABLE ( ( unsigned portCHAR ) 0x20 ) + +/* Constants for writing to UCSRC. */ +#define serUCSRC_SELECT ( ( unsigned portCHAR ) 0x80 ) +#define serEIGHT_DATA_BITS ( ( unsigned portCHAR ) 0x06 ) + +static xQueueHandle xRxedChars; +static xQueueHandle xCharsForTx; + +#define vInterruptOn() \ +{ \ + unsigned portCHAR ucByte; \ + \ + ucByte = UCSRB; \ + ucByte |= serTX_INT_ENABLE; \ + outb( UCSRB, ucByte ); \ +} +/*-----------------------------------------------------------*/ + +#define vInterruptOff() \ +{ \ + unsigned portCHAR ucByte; \ + \ + ucByte = UCSRB; \ + ucByte &= ~serTX_INT_ENABLE; \ + outb( UCSRB, ucByte ); \ +} +/*-----------------------------------------------------------*/ + +xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) +{ +unsigned portLONG ulBaudRateCounter; +unsigned portCHAR ucByte; + + portENTER_CRITICAL(); + { + /* Create the queues used by the com test task. */ + xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + + /* Calculate the baud rate register value from the equation in the + data sheet. */ + ulBaudRateCounter = ( configCPU_CLOCK_HZ / ( serBAUD_DIV_CONSTANT * ulWantedBaud ) ) - ( unsigned portLONG ) 1; + + /* Set the baud rate. */ + ucByte = ( unsigned portCHAR ) ( ulBaudRateCounter & ( unsigned portLONG ) 0xff ); + outb( UBRRL, ucByte ); + + ulBaudRateCounter >>= ( unsigned portLONG ) 8; + ucByte = ( unsigned portCHAR ) ( ulBaudRateCounter & ( unsigned portLONG ) 0xff ); + outb( UBRRH, ucByte ); + + /* Enable the Rx interrupt. The Tx interrupt will get enabled + later. Also enable the Rx and Tx. */ + outb( UCSRB, serRX_INT_ENABLE | serRX_ENABLE | serTX_ENABLE ); + + /* Set the data bits to 8. */ + outb( UCSRC, serUCSRC_SELECT | serEIGHT_DATA_BITS ); + } + portEXIT_CRITICAL(); + + /* Unlike other ports, this serial code does not allow for more than one + com port. We therefore don't return a pointer to a port structure and can + instead just return NULL. */ + return NULL; +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) +{ + /* Get the next character from the buffer. Return false if no characters + are available, or arrive before xBlockTime expires. */ + if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) + { + return pdTRUE; + } + else + { + return pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) +{ + /* Return false if after the block time there is no room on the Tx queue. */ + if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) + { + return pdFAIL; + } + + vInterruptOn(); + + return pdPASS; +} +/*-----------------------------------------------------------*/ + +void vSerialClose( xComPortHandle xPort ) +{ +unsigned portCHAR ucByte; + + /* Turn off the interrupts. We may also want to delete the queues and/or + re-install the original ISR. */ + + portENTER_CRITICAL(); + { + vInterruptOff(); + ucByte = UCSRB; + ucByte &= ~serRX_INT_ENABLE; + outb( UCSRB, ucByte ); + } + portEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +__interrupt void SIG_UART_RECV( void ) +{ +signed portCHAR cChar; + + /* Get the character and post it on the queue of Rxed characters. + If the post causes a task to wake force a context switch as the woken task + may have a higher priority than the task we have interrupted. */ + cChar = UDR; + + if( xQueueSendFromISR( xRxedChars, &cChar, pdFALSE ) ) + { + taskYIELD(); + } +} +/*-----------------------------------------------------------*/ + +__interrupt void SIG_UART_DATA( void ) +{ +signed portCHAR cChar, cTaskWoken; + + if( xQueueReceiveFromISR( xCharsForTx, &cChar, &cTaskWoken ) == pdTRUE ) + { + /* Send the next character queued for Tx. */ + outb( UDR, cChar ); + } + else + { + /* Queue empty, nothing to send. */ + vInterruptOff(); + } +} + diff --git a/20080212/Demo/AVR_ATMega323_IAR/settings/rtosdemo.dbgdt b/20080212/Demo/AVR_ATMega323_IAR/settings/rtosdemo.dbgdt new file mode 100644 index 000000000..33f4649c2 --- /dev/null +++ b/20080212/Demo/AVR_ATMega323_IAR/settings/rtosdemo.dbgdt @@ -0,0 +1,5 @@ + + + + + diff --git a/20080212/Demo/AVR_ATMega323_IAR/settings/rtosdemo.dni b/20080212/Demo/AVR_ATMega323_IAR/settings/rtosdemo.dni new file mode 100644 index 000000000..9fdf1aa6d --- /dev/null +++ b/20080212/Demo/AVR_ATMega323_IAR/settings/rtosdemo.dni @@ -0,0 +1,41 @@ +[DisAssemblyWindow] +NumStates=_ 1 +State 1=_ 1 +[Watch] +Watch 1=_ 1 "usCurrentNumberOfTasks" +Watch 2= +Watch 3= +[CodeCoverage] +State=_ 0 +[Profiling] +State=_ 0 +[TermIOSettings] +Filename=_ "" +InputMode=_ 1 +[QWatch] +WindowContent=_ 100 100 100 100 +[Desktop-Debug] +Wnd0=_ "Watch" "open" 44 0 1 -1 -1 -1 -1 1139 276 1595 524 100 100 100 100 +Wnd1=_ "Memory" "open" 44 0 1 -1 -1 -1 -1 1139 217 1591 939 1 1872 0 1872 0 1 0 1 0 +Wnd2=_ "CallStack" "open" 44 0 1 -1 -1 -1 -1 30 699 277 1037 1 +Wnd3=_ "Register" "open" 44 0 1 -1 -1 -1 -1 1237 0 1569 1019 0 0 0 0 +Wnd4=_ "Register" "open" 44 0 1 -1 -1 -1 -1 40 264 1312 986 0 0 0 0 +Wnd5=_ "Editor-DebugSource" "open" 44 0 1 -1 -1 -1 -1 169 991 1062 2036 "E:\Dev\FreeRTOS\Source\portable\IAR\ATMega323\portmacro.s90" 1 1 0 206 6825 6825 +Wnd6=_ "Disassembly" "open" 44 0 1 -1 -1 -4 -28 586 28 1196 854 +Wnd7=_ "Log" "closed" 44 0 1 -1 -1 -4 -28 872 845 1595 1069 +Wnd8=_ "Locals" "closed" 44 0 1 -1 -1 -1 -1 1139 0 1595 276 100 100 100 100 +Wnd9=_ "Terminal I/O" "closed" 44 0 1 -1 -1 -1 -1 1138 522 1595 826 +Maximized=_ 0 +Count=_ 10 +[TermIOLog] +LoggingEnabled=_ 0 +LogFile=_ "" +[Log file] +LoggingEnabled=_ 0 +LogFile=_ "" +Category=_ 0 +[Breakpoints] +Count=0 +[TraceHelper] +Enabled=0 +ShowSource=1 diff --git a/20080212/Demo/AVR_ATMega323_IAR/settings/rtosdemo.fmt b/20080212/Demo/AVR_ATMega323_IAR/settings/rtosdemo.fmt new file mode 100644 index 000000000..63403ba0c --- /dev/null +++ b/20080212/Demo/AVR_ATMega323_IAR/settings/rtosdemo.fmt @@ -0,0 +1,4 @@ +[struct types] +Count=_ 0 +[watch formats] +Count=_ 0 diff --git a/20080212/Demo/AVR_ATMega323_IAR/settings/rtosdemo.ini b/20080212/Demo/AVR_ATMega323_IAR/settings/rtosdemo.ini new file mode 100644 index 000000000..e433ec84f --- /dev/null +++ b/20080212/Demo/AVR_ATMega323_IAR/settings/rtosdemo.ini @@ -0,0 +1,10 @@ +[WorkspaceWindow] +ExpandedNodes=_ 1 "rtosdemo" 1 "rtosdemo/Debug" +SelectedTab=_ 0 +[Desktop-Workspace] +Wnd0=_ "TextEditor" "open" 44 0 1 -1 -1 -1 -1 378 14 1227 671 "E:\Dev\FreeRTOS\Source\tasks.c" 1 1 0 1170 37742 37742 +Wnd1=_ "TextEditor" "open" 44 0 1 -1 -1 -1 -1 81 81 930 738 "E:\Dev\FreeRTOS\Source\portable\IAR\ATMega323\portmacro.h" 1 1 0 66 3233 3233 +Wnd2=_ "Workspace2" "open" 44 0 1 -1 -1 -4 -28 0 0 352 713 276 27 27 +Wnd3=_ "Messages2" "open" 44 0 1 -1 -1 -4 -28 -6 714 1590 1104 5 "Build\Messages" 1580 "Find in Files\Line" 79 "Find in Files\Path" 474 "Find in Files\String" 948 "Tool Output\Output" 1560 +Maximized=_ 0 +Count=_ 4 diff --git a/20080212/Demo/AVR_ATMega323_IAR/settings/rtosdemo.wsdt b/20080212/Demo/AVR_ATMega323_IAR/settings/rtosdemo.wsdt new file mode 100644 index 000000000..9f6c956df --- /dev/null +++ b/20080212/Demo/AVR_ATMega323_IAR/settings/rtosdemo.wsdt @@ -0,0 +1,49 @@ + + + + + + rtosdemo/Debug + + + + + + + + + 246272727 + + 20115330776 + + + + + + TabID-12388-19520 + Workspace + Workspace + + + rtosdemortosdemo/Demo Sourcertosdemo/Kernel Sourcertosdemo/portheap.c + + + + 0TabID-19172-8303BuildBuildTabID-954-28216Debug LogDebug-Log0 + + + + + + TextEditorC:\E\Dev\FreeRTOS\Demo\AVR_ATMega323_IAR\regtest.c0190661966190TextEditorC:\E\Dev\FreeRTOS\Demo\AVR_ATMega323_IAR\main.c012355005500TextEditorC:\E\Dev\FreeRTOS\Demo\Common\Minimal\crflash.c0170680768070100000010000001 + + + + + + + iaridepm1-2-2619320-2-2162161115714165638230000638889-2-23071402-2-214043091002857317901116429166667 + + + + diff --git a/20080212/Demo/AVR_ATMega323_WinAVR/FreeRTOSConfig.h b/20080212/Demo/AVR_ATMega323_WinAVR/FreeRTOSConfig.h new file mode 100644 index 000000000..582368163 --- /dev/null +++ b/20080212/Demo/AVR_ATMega323_WinAVR/FreeRTOSConfig.h @@ -0,0 +1,87 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 8000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 85 ) +#define configTOTAL_HEAP_SIZE ( (size_t ) ( 1500 ) ) +#define configMAX_TASK_NAME_LEN ( 8 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 1 +#define configIDLE_SHOULD_YIELD 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 1 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/AVR_ATMega323_WinAVR/ParTest/ParTest.c b/20080212/Demo/AVR_ATMega323_WinAVR/ParTest/ParTest.c new file mode 100644 index 000000000..31d806b5d --- /dev/null +++ b/20080212/Demo/AVR_ATMega323_WinAVR/ParTest/ParTest.c @@ -0,0 +1,133 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V2.0.0 + + + Use scheduler suspends in place of critical sections. + +Changes from V2.6.0 + + + Replaced the inb() and outb() functions with direct memory + access. This allows the port to be built with the 20050414 build of + WinAVR. +*/ + +#include "FreeRTOS.h" +#include "task.h" +#include "partest.h" + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +#define partstALL_BITS_OUTPUT ( ( unsigned portCHAR ) 0xff ) +#define partstALL_OUTPUTS_OFF ( ( unsigned portCHAR ) 0xff ) +#define partstMAX_OUTPUT_LED ( ( unsigned portCHAR ) 7 ) + +static volatile unsigned portCHAR ucCurrentOutputValue = partstALL_OUTPUTS_OFF; /*lint !e956 File scope parameters okay here. */ + +/*-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ + ucCurrentOutputValue = partstALL_OUTPUTS_OFF; + + /* Set port B direction to outputs. Start with all output off. */ + DDRB = partstALL_BITS_OUTPUT; + PORTB = ucCurrentOutputValue; +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ +unsigned portCHAR ucBit = ( unsigned portCHAR ) 1; + + if( uxLED <= partstMAX_OUTPUT_LED ) + { + ucBit <<= uxLED; + } + + vTaskSuspendAll(); + { + if( xValue == pdTRUE ) + { + ucBit ^= ( unsigned portCHAR ) 0xff; + ucCurrentOutputValue &= ucBit; + } + else + { + ucCurrentOutputValue |= ucBit; + } + + PORTB = ucCurrentOutputValue; + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned portCHAR ucBit; + + if( uxLED <= partstMAX_OUTPUT_LED ) + { + ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED; + + vTaskSuspendAll(); + { + if( ucCurrentOutputValue & ucBit ) + { + ucCurrentOutputValue &= ~ucBit; + } + else + { + ucCurrentOutputValue |= ucBit; + } + + PORTB = ucCurrentOutputValue; + } + xTaskResumeAll(); + } +} + + diff --git a/20080212/Demo/AVR_ATMega323_WinAVR/main.c b/20080212/Demo/AVR_ATMega323_WinAVR/main.c new file mode 100644 index 000000000..a712ef1d5 --- /dev/null +++ b/20080212/Demo/AVR_ATMega323_WinAVR/main.c @@ -0,0 +1,268 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + * Creates all the demo application tasks, then starts the scheduler. The WEB + * documentation provides more details of the demo application tasks. + * + * Main. c also creates a task called "Check". This only executes every three + * seconds but has the highest priority so is guaranteed to get processor time. + * Its main function is to check that all the other tasks are still operational. + * Each task that does not flash an LED maintains a unique count that is + * incremented each time the task successfully completes its function. Should + * any error occur within such a task the count is permanently halted. The + * check task inspects the count of each task to ensure it has changed since + * the last time the check task executed. If all the count variables have + * changed all the tasks are still executing error free, and the check task + * toggles an LED. Should any task contain an error at any time the LED toggle + * will stop. + * + * The LED flash and communications test tasks do not maintain a count. + */ + +/* +Changes from V1.2.0 + + + Changed the baud rate for the serial test from 19200 to 57600. + +Changes from V1.2.3 + + + The integer and comtest tasks are now used when the cooperative scheduler + is being used. Previously they were only used with the preemptive + scheduler. + +Changes from V1.2.5 + + + Set the baud rate to 38400. This has a smaller error percentage with an + 8MHz clock (according to the manual). + +Changes from V2.0.0 + + + Delay periods are now specified using variables and constants of + portTickType rather than unsigned portLONG. + +Changes from V2.6.1 + + + The IAR and WinAVR AVR ports are now maintained separately. + +Changes from V4.0.5 + + + Modified to demonstrate the use of co-routines. + +*/ + +#include +#include + +#ifdef GCC_MEGA_AVR + /* EEPROM routines used only with the WinAVR compiler. */ + #include +#endif + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "croutine.h" + +/* Demo file headers. */ +#include "PollQ.h" +#include "integer.h" +#include "serial.h" +#include "comtest.h" +#include "crflash.h" +#include "print.h" +#include "partest.h" +#include "regtest.h" + +/* Priority definitions for most of the tasks in the demo application. Some +tasks just use the idle priority. */ +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) + +/* Baud rate used by the serial port tasks. */ +#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 38400 ) + +/* LED used by the serial port tasks. This is toggled on each character Tx, +and mainCOM_TEST_LED + 1 is toggles on each character Rx. */ +#define mainCOM_TEST_LED ( 4 ) + +/* LED that is toggled by the check task. The check task periodically checks +that all the other tasks are operating without error. If no errors are found +the LED is toggled. If an error is found at any time the LED is never toggles +again. */ +#define mainCHECK_TASK_LED ( 7 ) + +/* The period between executions of the check task. */ +#define mainCHECK_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS ) + +/* An address in the EEPROM used to count resets. This is used to check that +the demo application is not unexpectedly resetting. */ +#define mainRESET_COUNT_ADDRESS ( ( void * ) 0x50 ) + +/* The number of coroutines to create. */ +#define mainNUM_FLASH_COROUTINES ( 3 ) + +/* + * The task function for the "Check" task. + */ +static void vErrorChecks( void *pvParameters ); + +/* + * Checks the unique counts of other tasks to ensure they are still operational. + * Flashes an LED if everything is okay. + */ +static void prvCheckOtherTasksAreStillRunning( void ); + +/* + * Called on boot to increment a count stored in the EEPROM. This is used to + * ensure the CPU does not reset unexpectedly. + */ +static void prvIncrementResetCount( void ); + +/* + * The idle hook is used to scheduler co-routines. + */ +void vApplicationIdleHook( void ); + +/*-----------------------------------------------------------*/ + +portSHORT main( void ) +{ + prvIncrementResetCount(); + + /* Setup the LED's for output. */ + vParTestInitialise(); + + /* Create the standard demo tasks. */ + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartRegTestTasks(); + + /* Create the tasks defined within this file. */ + xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Create the co-routines that flash the LED's. */ + vStartFlashCoRoutines( mainNUM_FLASH_COROUTINES ); + + /* In this port, to use preemptive scheduler define configUSE_PREEMPTION + as 1 in portmacro.h. To use the cooperative scheduler define + configUSE_PREEMPTION as 0. */ + vTaskStartScheduler(); + + return 0; +} +/*-----------------------------------------------------------*/ + +static void vErrorChecks( void *pvParameters ) +{ +static volatile unsigned portLONG ulDummyVariable = 3UL; + + /* The parameters are not used. */ + ( void ) pvParameters; + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. */ + for( ;; ) + { + vTaskDelay( mainCHECK_PERIOD ); + + /* Perform a bit of 32bit maths to ensure the registers used by the + integer tasks get some exercise. The result here is not important - + see the demo application documentation for more info. */ + ulDummyVariable *= 3; + + prvCheckOtherTasksAreStillRunning(); + } +} +/*-----------------------------------------------------------*/ + +static void prvCheckOtherTasksAreStillRunning( void ) +{ +static portBASE_TYPE xErrorHasOccurred = pdFALSE; + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + if( xAreRegTestTasksStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + if( xErrorHasOccurred == pdFALSE ) + { + /* Toggle the LED if everything is okay so we know if an error occurs even if not + using console IO. */ + vParTestToggleLED( mainCHECK_TASK_LED ); + } +} +/*-----------------------------------------------------------*/ + +static void prvIncrementResetCount( void ) +{ +unsigned portCHAR ucCount; + + eeprom_read_block( &ucCount, mainRESET_COUNT_ADDRESS, sizeof( ucCount ) ); + ucCount++; + eeprom_write_byte( mainRESET_COUNT_ADDRESS, ucCount ); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ + vCoRoutineSchedule(); +} + diff --git a/20080212/Demo/AVR_ATMega323_WinAVR/makefile b/20080212/Demo/AVR_ATMega323_WinAVR/makefile new file mode 100644 index 000000000..9bd557d1b --- /dev/null +++ b/20080212/Demo/AVR_ATMega323_WinAVR/makefile @@ -0,0 +1,428 @@ +# WinAVR Sample makefile written by Eric B. Weddington, Jörg Wunsch, et al. +# Released to the Public Domain +# Please read the make user manual! +# +# Additional material for this makefile was submitted by: +# Tim Henigan +# Peter Fleury +# Reiner Patommel +# Sander Pool +# Frederik Rouleau +# Markus Pfaff +# +# On command line: +# +# make all = Make software. +# +# make clean = Clean out built project files. +# +# make coff = Convert ELF to AVR COFF (for use with AVR Studio 3.x or VMLAB). +# +# make extcoff = Convert ELF to AVR Extended COFF (for use with AVR Studio +# 4.07 or greater). +# +# make program = Download the hex file to the device, using avrdude. Please +# customize the avrdude settings below first! +# +# make filename.s = Just compile filename.c into the assembler code only +# +# To rebuild project do "make clean" then "make all". +# + + +# MCU name +MCU = atmega323 + +# Output format. (can be srec, ihex, binary) +FORMAT = ihex + +# Target file name (without extension). +TARGET = rtosdemo + +# Optimization level, can be [0, 1, 2, 3, s]. 0 turns off optimization. +# (Note: 3 is not always the best optimization level. See avr-libc FAQ.) +OPT = s + + +# List C source files here. (C dependencies are automatically generated.) +DEMO_DIR = ../Common/Minimal +SOURCE_DIR = ../../Source +PORT_DIR = ../../Source/portable/GCC/ATMega323 + +SRC = \ +main.c \ +ParTest/ParTest.c \ +serial/serial.c \ +regtest.c \ +$(SOURCE_DIR)/tasks.c \ +$(SOURCE_DIR)/queue.c \ +$(SOURCE_DIR)/list.c \ +$(SOURCE_DIR)/croutine.c \ +$(SOURCE_DIR)/portable/MemMang/heap_1.c \ +$(PORT_DIR)/port.c \ +$(DEMO_DIR)/crflash.c \ +$(DEMO_DIR)/integer.c \ +$(DEMO_DIR)/PollQ.c \ +$(DEMO_DIR)/comtest.c + + +# If there is more than one source file, append them above, or modify and +# uncomment the following: +#SRC += foo.c bar.c + +# You can also wrap lines by appending a backslash to the end of the line: +#SRC += baz.c \ +#xyzzy.c + + + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + + +# List any extra directories to look for include files here. +# Each directory must be seperated by a space. +EXTRAINCDIRS = + + +# Optional compiler flags. +# -g: generate debugging information (for GDB, or for COFF conversion) +# -O*: optimization level +# -f...: tuning, see gcc manual and avr-libc documentation +# -Wall...: warning level +# -Wa,...: tell GCC to pass this to the assembler. +# -ahlms: create assembler listing + +DEBUG_LEVEL=-g +WARNINGS=-Wall -Wextra -Wshadow -Wpointer-arith -Wbad-function-cast -Wcast-align -Wsign-compare \ + -Waggregate-return -Wstrict-prototypes -Wmissing-prototypes -Wmissing-declarations -Wunused + +CFLAGS = -D GCC_MEGA_AVR -I. -I../../Source/include -I../Common/include \ +$(DEBUG_LEVEL) -O$(OPT) \ +-fsigned-char -funsigned-bitfields -fpack-struct -fshort-enums \ +$(WARNINGS) \ +-Wa,-adhlns=$(<:.c=.lst) \ +$(patsubst %,-I%,$(EXTRAINCDIRS)) + + +# Set a "language standard" compiler flag. +# Unremark just one line below to set the language standard to use. +# gnu99 = C99 + GNU extensions. See GCC manual for more information. +#CFLAGS += -std=c89 +#CFLAGS += -std=gnu89 +#CFLAGS += -std=c99 +CFLAGS += -std=gnu99 + + + +# Optional assembler flags. +# -Wa,...: tell GCC to pass this to the assembler. +# -ahlms: create listing +# -gstabs: have the assembler create line number information; note that +# for use in COFF files, additional information about filenames +# and function names needs to be present in the assembler source +# files -- see avr-libc docs [FIXME: not yet described there] +ASFLAGS = -Wa,-adhlns=$(<:.S=.lst),-gstabs + + + +# Optional linker flags. +# -Wl,...: tell GCC to pass this to linker. +# -Map: create map file +# --cref: add cross reference to map file +LDFLAGS = -Wl,-Map=$(TARGET).map,--cref + + + +# Additional libraries + +# Minimalistic printf version +#LDFLAGS += -Wl,-u,vfprintf -lprintf_min + +# Floating point printf version (requires -lm below) +#LDFLAGS += -Wl,-u,vfprintf -lprintf_flt + +# -lm = math library +LDFLAGS += -lm + + + + +# Programming support using avrdude. Settings and variables. + +# Programming hardware: alf avr910 avrisp bascom bsd +# dt006 pavr picoweb pony-stk200 sp12 stk200 stk500 +# +# Type: avrdude -c ? +# to get a full listing. +# +AVRDUDE_PROGRAMMER = stk500 + + +AVRDUDE_PORT = com1 # programmer connected to serial device +#AVRDUDE_PORT = lpt1 # programmer connected to parallel port + +AVRDUDE_WRITE_FLASH = -U flash:w:$(TARGET).hex +#AVRDUDE_WRITE_EEPROM = -U eeprom:w:$(TARGET).eep + +AVRDUDE_FLAGS = -p $(MCU) -P $(AVRDUDE_PORT) -c $(AVRDUDE_PROGRAMMER) + +# Uncomment the following if you want avrdude's erase cycle counter. +# Note that this counter needs to be initialized first using -Yn, +# see avrdude manual. +#AVRDUDE_ERASE += -y + +# Uncomment the following if you do /not/ wish a verification to be +# performed after programming the device. +#AVRDUDE_FLAGS += -V + +# Increase verbosity level. Please use this when submitting bug +# reports about avrdude. See +# to submit bug reports. +#AVRDUDE_FLAGS += -v -v + + + + +# --------------------------------------------------------------------------- + +# Define directories, if needed. +DIRAVR = c:/winavr +DIRAVRBIN = $(DIRAVR)/bin +DIRAVRUTILS = $(DIRAVR)/utils/bin +DIRINC = . +DIRLIB = $(DIRAVR)/avr/lib + + +# Define programs and commands. +SHELL = sh + +CC = avr-gcc + +OBJCOPY = avr-objcopy +OBJDUMP = avr-objdump +SIZE = avr-size + + +# Programming support using avrdude. +AVRDUDE = avrdude + + +REMOVE = rm -f +COPY = cp + +HEXSIZE = $(SIZE) --target=$(FORMAT) $(TARGET).hex +ELFSIZE = $(SIZE) -A $(TARGET).elf + + + +# Define Messages +# English +MSG_ERRORS_NONE = Errors: none +MSG_BEGIN = -------- begin -------- +MSG_END = -------- end -------- +MSG_SIZE_BEFORE = Size before: +MSG_SIZE_AFTER = Size after: +MSG_COFF = Converting to AVR COFF: +MSG_EXTENDED_COFF = Converting to AVR Extended COFF: +MSG_FLASH = Creating load file for Flash: +MSG_EEPROM = Creating load file for EEPROM: +MSG_EXTENDED_LISTING = Creating Extended Listing: +MSG_SYMBOL_TABLE = Creating Symbol Table: +MSG_LINKING = Linking: +MSG_COMPILING = Compiling: +MSG_ASSEMBLING = Assembling: +MSG_CLEANING = Cleaning project: + + + + +# Define all object files. +OBJ = $(SRC:.c=.o) $(ASRC:.S=.o) + +# Define all listing files. +LST = $(ASRC:.S=.lst) $(SRC:.c=.lst) + +# Combine all necessary flags and optional flags. +# Add target processor to flags. +ALL_CFLAGS = -mmcu=$(MCU) -I. $(CFLAGS) +ALL_ASFLAGS = -mmcu=$(MCU) -I. -x assembler-with-cpp $(ASFLAGS) + + + +# Default target. +all: begin gccversion sizebefore $(TARGET).elf $(TARGET).hex $(TARGET).eep \ + $(TARGET).lss $(TARGET).sym sizeafter finished end + + +# Eye candy. +# AVR Studio 3.x does not check make's exit code but relies on +# the following magic strings to be generated by the compile job. +begin: + @echo + @echo $(MSG_BEGIN) + +finished: + @echo $(MSG_ERRORS_NONE) + +end: + @echo $(MSG_END) + @echo + + +# Display size of file. +sizebefore: + @if [ -f $(TARGET).elf ]; then echo; echo $(MSG_SIZE_BEFORE); $(ELFSIZE); echo; fi + +sizeafter: + @if [ -f $(TARGET).elf ]; then echo; echo $(MSG_SIZE_AFTER); $(ELFSIZE); echo; fi + + + +# Display compiler version information. +gccversion : + @$(CC) --version + + + + +# Convert ELF to COFF for use in debugging / simulating in +# AVR Studio or VMLAB. +COFFCONVERT=$(OBJCOPY) --debugging \ + --change-section-address .data-0x800000 \ + --change-section-address .bss-0x800000 \ + --change-section-address .noinit-0x800000 \ + --change-section-address .eeprom-0x810000 + + +coff: $(TARGET).elf + @echo + @echo $(MSG_COFF) $(TARGET).cof + $(COFFCONVERT) -O coff-avr $< $(TARGET).cof + + +extcoff: $(TARGET).elf + @echo + @echo $(MSG_EXTENDED_COFF) $(TARGET).cof + $(COFFCONVERT) -O coff-ext-avr $< $(TARGET).cof + + + + +# Program the device. +program: $(TARGET).hex $(TARGET).eep + $(AVRDUDE) $(AVRDUDE_FLAGS) $(AVRDUDE_WRITE_FLASH) $(AVRDUDE_WRITE_EEPROM) + + + + +# Create final output files (.hex, .eep) from ELF output file. +%.hex: %.elf + @echo + @echo $(MSG_FLASH) $@ + $(OBJCOPY) -O $(FORMAT) -R .eeprom $< $@ + +%.eep: %.elf + @echo + @echo $(MSG_EEPROM) $@ + -$(OBJCOPY) -j .eeprom --set-section-flags=.eeprom="alloc,load" \ + --change-section-lma .eeprom=0 -O $(FORMAT) $< $@ + +# Create extended listing file from ELF output file. +%.lss: %.elf + @echo + @echo $(MSG_EXTENDED_LISTING) $@ + $(OBJDUMP) -h -S $< > $@ + +# Create a symbol table from ELF output file. +%.sym: %.elf + @echo + @echo $(MSG_SYMBOL_TABLE) $@ + avr-nm -n $< > $@ + + + +# Link: create ELF output file from object files. +.SECONDARY : $(TARGET).elf +.PRECIOUS : $(OBJ) +%.elf: $(OBJ) + @echo + @echo $(MSG_LINKING) $@ + $(CC) $(ALL_CFLAGS) $(OBJ) --output $@ $(LDFLAGS) + + +# Compile: create object files from C source files. +%.o : %.c + @echo + @echo $(MSG_COMPILING) $< + $(CC) -c $(ALL_CFLAGS) $< -o $@ + + +# Compile: create assembler files from C source files. +%.s : %.c + $(CC) -S $(ALL_CFLAGS) $< -o $@ + + +# Assemble: create object files from assembler source files. +%.o : %.S + @echo + @echo $(MSG_ASSEMBLING) $< + $(CC) -c $(ALL_ASFLAGS) $< -o $@ + + + + + + +# Target: clean project. +clean: begin clean_list finished end + +clean_list : + @echo + @echo $(MSG_CLEANING) + $(REMOVE) $(TARGET).hex + $(REMOVE) $(TARGET).eep + $(REMOVE) $(TARGET).obj + $(REMOVE) $(TARGET).cof + $(REMOVE) $(TARGET).elf + $(REMOVE) $(TARGET).map + $(REMOVE) $(TARGET).obj + $(REMOVE) $(TARGET).a90 + $(REMOVE) $(TARGET).sym + $(REMOVE) $(TARGET).lnk + $(REMOVE) $(TARGET).lss + $(REMOVE) $(OBJ) + $(REMOVE) $(LST) + $(REMOVE) $(SRC:.c=.s) + $(REMOVE) $(SRC:.c=.d) + + +# Automatically generate C source code dependencies. +# (Code originally taken from the GNU make user manual and modified +# (See README.txt Credits).) +# +# Note that this will work with sh (bash) and sed that is shipped with WinAVR +# (see the SHELL variable defined above). +# This may not work with other shells or other seds. +# +%.d: %.c + set -e; $(CC) -MM $(ALL_CFLAGS) $< \ + | sed 's,\(.*\)\.o[ :]*,\1.o \1.d : ,g' > $@; \ + [ -s $@ ] || rm -f $@ + + +# Remove the '-' if you want to see the dependency files generated. +-include $(SRC:.c=.d) + + + +# Listing of phony targets. +.PHONY : all begin finish end sizebefore sizeafter gccversion coff extcoff \ + clean clean_list program + diff --git a/20080212/Demo/AVR_ATMega323_WinAVR/regtest.c b/20080212/Demo/AVR_ATMega323_WinAVR/regtest.c new file mode 100644 index 000000000..7e2787d47 --- /dev/null +++ b/20080212/Demo/AVR_ATMega323_WinAVR/regtest.c @@ -0,0 +1,372 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo file headers. */ +#include "regtest.h" + +/* + * Test tasks that sets registers to known values, then checks to ensure the + * values remain as expected. Test 1 and test 2 use different values. + */ +static void prvRegisterCheck1( void *pvParameters ); +static void prvRegisterCheck2( void *pvParameters ); + +/* Set to a non zero value should an error be found. */ +portBASE_TYPE xRegTestError = pdFALSE; + +/*-----------------------------------------------------------*/ + +void vStartRegTestTasks( void ) +{ + xTaskCreate( prvRegisterCheck1, "Reg1", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + xTaskCreate( prvRegisterCheck2, "Reg2", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xAreRegTestTasksStillRunning( void ) +{ +portBASE_TYPE xReturn; + + /* If a register was found to contain an unexpected value then the + xRegTestError variable would have been set to a non zero value. */ + if( xRegTestError == pdFALSE ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +static void prvRegisterCheck1( void *pvParameters ) +{ + ( void ) pvParameters; + + for( ;; ) + { + asm( "LDI r31, 5" ); + asm( "MOV r0, r31" ); + asm( "LDI r31, 6" ); + asm( "MOV r1, r31" ); + asm( "LDI r31, 7" ); + asm( "MOV r2, r31" ); + asm( "LDI r31, 8" ); + asm( "MOV r3, r31" ); + asm( "LDI r31, 9" ); + asm( "MOV r4, r31" ); + asm( "LDI r31, 10" ); + asm( "MOV r5, r31" ); + asm( "LDI r31, 11" ); + asm( "MOV r6, r31" ); + asm( "LDI r31, 12" ); + asm( "MOV r7, r31" ); + asm( "LDI r31, 13" ); + asm( "MOV r8, r31" ); + asm( "LDI r31, 14" ); + asm( "MOV r9, r31" ); + asm( "LDI r31, 15" ); + asm( "MOV r10, r31" ); + asm( "LDI r31, 16" ); + asm( "MOV r11, r31" ); + asm( "LDI r31, 17" ); + asm( "MOV r12, r31" ); + asm( "LDI r31, 18" ); + asm( "MOV r13, r31" ); + asm( "LDI r31, 19" ); + asm( "MOV r14, r31" ); + asm( "LDI r31, 20" ); + asm( "MOV r15, r31" ); + asm( "LDI r16, 21" ); + asm( "LDI r17, 22" ); + asm( "LDI r18, 23" ); + asm( "LDI r19, 24" ); + asm( "LDI r20, 25" ); + asm( "LDI r21, 26" ); + asm( "LDI r22, 27" ); + asm( "LDI r23, 28" ); + asm( "LDI r24, 29" ); + asm( "LDI r25, 30" ); + asm( "LDI r26, 31" ); + asm( "LDI r27, 32" ); + asm( "LDI r30, 33" ); + + asm( "LDI r31, 5" ); + asm( "CPSE r31, r0" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 6" ); + asm( "CPSE r31, r1" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 7" ); + asm( "CPSE r31, r2" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 8" ); + asm( "CPSE r31, r3" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 9" ); + asm( "CPSE r31, r4" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 10" ); + asm( "CPSE r31, r5" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 11" ); + asm( "CPSE r31, r6" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 12" ); + asm( "CPSE r31, r7" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 13" ); + asm( "CPSE r31, r8" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 14" ); + asm( "CPSE r31, r9" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 15" ); + asm( "CPSE r31, r10" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 16" ); + asm( "CPSE r31, r11" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 17" ); + asm( "CPSE r31, r12" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 18" ); + asm( "CPSE r31, r13" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 19" ); + asm( "CPSE r31, r14" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 20" ); + asm( "CPSE r31, r15" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 21" ); + asm( "CPSE r31, r16" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 22" ); + asm( "CPSE r31, r17" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 23" ); + asm( "CPSE r31, r18" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 24" ); + asm( "CPSE r31, r19" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 25" ); + asm( "CPSE r31, r20" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 26" ); + asm( "CPSE r31, r21" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 27" ); + asm( "CPSE r31, r22" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 28" ); + asm( "CPSE r31, r23" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 29" ); + asm( "CPSE r31, r24" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 30" ); + asm( "CPSE r31, r25" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 31" ); + asm( "CPSE r31, r26" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 32" ); + asm( "CPSE r31, r27" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 33" ); + asm( "CPSE r31, r30" ); + asm( "STS xRegTestError, r0" ); + } +} +/*-----------------------------------------------------------*/ + +static void prvRegisterCheck2( void *pvParameters ) +{ + ( void ) pvParameters; + + for( ;; ) + { + asm( "LDI r31, 1" ); + asm( "MOV r0, r31" ); + asm( "LDI r31, 2" ); + asm( "MOV r1, r31" ); + asm( "LDI r31, 3" ); + asm( "MOV r2, r31" ); + asm( "LDI r31, 4" ); + asm( "MOV r3, r31" ); + asm( "LDI r31, 5" ); + asm( "MOV r4, r31" ); + asm( "LDI r31, 6" ); + asm( "MOV r5, r31" ); + asm( "LDI r31, 7" ); + asm( "MOV r6, r31" ); + asm( "LDI r31, 8" ); + asm( "MOV r7, r31" ); + asm( "LDI r31, 9" ); + asm( "MOV r8, r31" ); + asm( "LDI r31, 10" ); + asm( "MOV r9, r31" ); + asm( "LDI r31, 11" ); + asm( "MOV r10, r31" ); + asm( "LDI r31, 12" ); + asm( "MOV r11, r31" ); + asm( "LDI r31, 13" ); + asm( "MOV r12, r31" ); + asm( "LDI r31, 14" ); + asm( "MOV r13, r31" ); + asm( "LDI r31, 15" ); + asm( "MOV r14, r31" ); + asm( "LDI r31, 16" ); + asm( "MOV r15, r31" ); + asm( "LDI r16, 17" ); + asm( "LDI r17, 18" ); + asm( "LDI r18, 19" ); + asm( "LDI r19, 20" ); + asm( "LDI r20, 21" ); + asm( "LDI r21, 22" ); + asm( "LDI r22, 23" ); + asm( "LDI r23, 24" ); + asm( "LDI r24, 25" ); + asm( "LDI r25, 26" ); + asm( "LDI r26, 27" ); + asm( "LDI r27, 28" ); + asm( "LDI r30, 29" ); + + asm( "LDI r31, 1" ); + asm( "CPSE r31, r0" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 2" ); + asm( "CPSE r31, r1" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 3" ); + asm( "CPSE r31, r2" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 4" ); + asm( "CPSE r31, r3" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 5" ); + asm( "CPSE r31, r4" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 6" ); + asm( "CPSE r31, r5" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 7" ); + asm( "CPSE r31, r6" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 8" ); + asm( "CPSE r31, r7" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 9" ); + asm( "CPSE r31, r8" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 10" ); + asm( "CPSE r31, r9" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 11" ); + asm( "CPSE r31, r10" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 12" ); + asm( "CPSE r31, r11" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 13" ); + asm( "CPSE r31, r12" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 14" ); + asm( "CPSE r31, r13" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 15" ); + asm( "CPSE r31, r14" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 16" ); + asm( "CPSE r31, r15" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 17" ); + asm( "CPSE r31, r16" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 18" ); + asm( "CPSE r31, r17" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 19" ); + asm( "CPSE r31, r18" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 20" ); + asm( "CPSE r31, r19" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 21" ); + asm( "CPSE r31, r20" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 22" ); + asm( "CPSE r31, r21" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 23" ); + asm( "CPSE r31, r22" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 24" ); + asm( "CPSE r31, r23" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 25" ); + asm( "CPSE r31, r24" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 26" ); + asm( "CPSE r31, r25" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 27" ); + asm( "CPSE r31, r26" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 28" ); + asm( "CPSE r31, r27" ); + asm( "STS xRegTestError, r0" ); + asm( "LDI r31, 29" ); + asm( "CPSE r31, r30" ); + asm( "STS xRegTestError, r0" ); + } +} + diff --git a/20080212/Demo/AVR_ATMega323_WinAVR/regtest.h b/20080212/Demo/AVR_ATMega323_WinAVR/regtest.h new file mode 100644 index 000000000..be12e78f4 --- /dev/null +++ b/20080212/Demo/AVR_ATMega323_WinAVR/regtest.h @@ -0,0 +1,50 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef REG_TEST_H +#define REG_TEST_H + +void vStartRegTestTasks( void ); +portBASE_TYPE xAreRegTestTasksStillRunning( void ); + +#endif + diff --git a/20080212/Demo/AVR_ATMega323_WinAVR/serial/serial.c b/20080212/Demo/AVR_ATMega323_WinAVR/serial/serial.c new file mode 100644 index 000000000..a77c91a70 --- /dev/null +++ b/20080212/Demo/AVR_ATMega323_WinAVR/serial/serial.c @@ -0,0 +1,234 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V1.2.3 + + + The function xPortInitMinimal() has been renamed to + xSerialPortInitMinimal() and the function xPortInit() has been renamed + to xSerialPortInit(). + +Changes from V2.0.0 + + + Delay periods are now specified using variables and constants of + portTickType rather than unsigned portLONG. + + xQueueReceiveFromISR() used in place of xQueueReceive() within the ISR. + +Changes from V2.6.0 + + + Replaced the inb() and outb() functions with direct memory + access. This allows the port to be built with the 20050414 build of + WinAVR. +*/ + +/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER. */ + + +#include +#include +#include "FreeRTOS.h" +#include "queue.h" +#include "task.h" +#include "serial.h" + +#define serBAUD_DIV_CONSTANT ( ( unsigned portLONG ) 16 ) + +/* Constants for writing to UCSRB. */ +#define serRX_INT_ENABLE ( ( unsigned portCHAR ) 0x80 ) +#define serRX_ENABLE ( ( unsigned portCHAR ) 0x10 ) +#define serTX_ENABLE ( ( unsigned portCHAR ) 0x08 ) +#define serTX_INT_ENABLE ( ( unsigned portCHAR ) 0x20 ) + +/* Constants for writing to UCSRC. */ +#define serUCSRC_SELECT ( ( unsigned portCHAR ) 0x80 ) +#define serEIGHT_DATA_BITS ( ( unsigned portCHAR ) 0x06 ) + +static xQueueHandle xRxedChars; +static xQueueHandle xCharsForTx; + +#define vInterruptOn() \ +{ \ + unsigned portCHAR ucByte; \ + \ + ucByte = UCSRB; \ + ucByte |= serTX_INT_ENABLE; \ + UCSRB = ucByte; \ +} +/*-----------------------------------------------------------*/ + +#define vInterruptOff() \ +{ \ + unsigned portCHAR ucInByte; \ + \ + ucInByte = UCSRB; \ + ucInByte &= ~serTX_INT_ENABLE; \ + UCSRB = ucInByte; \ +} +/*-----------------------------------------------------------*/ + +xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) +{ +unsigned portLONG ulBaudRateCounter; +unsigned portCHAR ucByte; + + portENTER_CRITICAL(); + { + /* Create the queues used by the com test task. */ + xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + + /* Calculate the baud rate register value from the equation in the + data sheet. */ + ulBaudRateCounter = ( configCPU_CLOCK_HZ / ( serBAUD_DIV_CONSTANT * ulWantedBaud ) ) - ( unsigned portLONG ) 1; + + /* Set the baud rate. */ + ucByte = ( unsigned portCHAR ) ( ulBaudRateCounter & ( unsigned portLONG ) 0xff ); + UBRRL = ucByte; + + ulBaudRateCounter >>= ( unsigned portLONG ) 8; + ucByte = ( unsigned portCHAR ) ( ulBaudRateCounter & ( unsigned portLONG ) 0xff ); + UBRRH = ucByte; + + /* Enable the Rx interrupt. The Tx interrupt will get enabled + later. Also enable the Rx and Tx. */ + UCSRB = ( serRX_INT_ENABLE | serRX_ENABLE | serTX_ENABLE ); + + /* Set the data bits to 8. */ + UCSRC = ( serUCSRC_SELECT | serEIGHT_DATA_BITS ); + } + portEXIT_CRITICAL(); + + /* Unlike other ports, this serial code does not allow for more than one + com port. We therefore don't return a pointer to a port structure and can + instead just return NULL. */ + return NULL; +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) +{ + /* Only one port is supported. */ + ( void ) pxPort; + + /* Get the next character from the buffer. Return false if no characters + are available, or arrive before xBlockTime expires. */ + if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) + { + return pdTRUE; + } + else + { + return pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) +{ + /* Only one port is supported. */ + ( void ) pxPort; + + /* Return false if after the block time there is no room on the Tx queue. */ + if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) + { + return pdFAIL; + } + + vInterruptOn(); + + return pdPASS; +} +/*-----------------------------------------------------------*/ + +void vSerialClose( xComPortHandle xPort ) +{ +unsigned portCHAR ucByte; + + /* The parameter is not used. */ + ( void ) xPort; + + /* Turn off the interrupts. We may also want to delete the queues and/or + re-install the original ISR. */ + + portENTER_CRITICAL(); + { + vInterruptOff(); + ucByte = UCSRB; + ucByte &= ~serRX_INT_ENABLE; + UCSRB = ucByte; + } + portEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +SIGNAL( SIG_UART_RECV ) +{ +signed portCHAR cChar; + + /* Get the character and post it on the queue of Rxed characters. + If the post causes a task to wake force a context switch as the woken task + may have a higher priority than the task we have interrupted. */ + cChar = UDR; + + if( xQueueSendFromISR( xRxedChars, &cChar, pdFALSE ) ) + { + taskYIELD(); + } +} +/*-----------------------------------------------------------*/ + +SIGNAL( SIG_UART_DATA ) +{ +signed portCHAR cChar, cTaskWoken; + + if( xQueueReceiveFromISR( xCharsForTx, &cChar, &cTaskWoken ) == pdTRUE ) + { + /* Send the next character queued for Tx. */ + UDR = cChar; + } + else + { + /* Queue empty, nothing to send. */ + vInterruptOff(); + } +} + diff --git a/20080212/Demo/CORTEX_LM3S102_GCC/Demo1/FreeRTOSConfig.h b/20080212/Demo/CORTEX_LM3S102_GCC/Demo1/FreeRTOSConfig.h new file mode 100644 index 000000000..e403b289e --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_GCC/Demo1/FreeRTOSConfig.h @@ -0,0 +1,86 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 59 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1468 ) ) +#define configMAX_TASK_NAME_LEN ( 3 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_CO_ROUTINES 1 + +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 0 +#define INCLUDE_vTaskDelayUntil 0 +#define INCLUDE_vTaskDelay 1 + + + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/CORTEX_LM3S102_GCC/Demo1/main.c b/20080212/Demo/CORTEX_LM3S102_GCC/Demo1/main.c new file mode 100644 index 000000000..ad5cc2fa7 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_GCC/Demo1/main.c @@ -0,0 +1,614 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + * This demo application creates six co-routines and two tasks (three including + * the idle task). The co-routines execute as part of the idle task hook. + * + * Five of the created co-routines are the standard 'co-routine flash' + * co-routines contained within the Demo/Common/Minimal/crflash.c file and + * documented on the FreeRTOS.org WEB site. + * + * The 'LCD Task' rotates a string on the LCD, delaying between each character + * as necessitated by the slow interface, and delaying between each string just + * long enough to enable the text to be read. + * + * The sixth co-routine and final task control the transmission and reception + * of a string to UART 0. The co-routine periodically sends the first + * character of the string to the UART, with the UART's TxEnd interrupt being + * used to transmit the remaining characters. The UART's RxEnd interrupt + * receives the characters and places them on a queue to be processed by the + * 'COMs Rx' task. An error is latched should an unexpected character be + * received, or any character be received out of sequence. + * + * A loopback connector is required to ensure that each character transmitted + * on the UART is also received on the same UART. For test purposes the UART + * FIFO's are not utalised in order to maximise the interrupt overhead. Also + * a pseudo random interval is used between the start of each transmission in + * order that the resultant interrupts are more randomly distributed and + * therefore more likely to highlight any problems. + * + * The flash co-routines control LED's zero to four. LED five is toggled each + * time the string is transmitted on the UART. LED six is toggled each time + * the string is CORRECTLY received on the UART. LED seven is latched on should + * an error be detected in any task or co-routine. + * + * In addition the idle task makes repetative calls to + * prvSetAndCheckRegisters(). This simply loads the general purpose registers + * with a known value, then checks each register to ensure the held value is + * still correct. As a low priority task this checking routine is likely to + * get repeatedly swapped in and out. A register being found to contain an + * incorrect value is therefore indicative of an error in the task switching + * mechansim. + * + */ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "croutine.h" + +/* Demo application include files. */ +#include "partest.h" +#include "crflash.h" + +/* Library include files. */ +#include "DriverLib.h" + +/* The time to delay between writing each character to the LCD. */ +#define mainCHAR_WRITE_DELAY ( 2 / portTICK_RATE_MS ) + +/* The time to delay between writing each string to the LCD. */ +#define mainSTRING_WRITE_DELAY ( 400 / portTICK_RATE_MS ) + +/* The number of flash co-routines to create. */ +#define mainNUM_FLASH_CO_ROUTINES ( 5 ) + +/* The length of the queue used to pass received characters to the Comms Rx +task. */ +#define mainRX_QUEUE_LEN ( 5 ) + +/* The priority of the co-routine used to initiate the transmission of the +string on UART 0. */ +#define mainTX_CO_ROUTINE_PRIORITY ( 1 ) + +/* Only one co-routine is created so its index is not important. */ +#define mainTX_CO_ROUTINE_INDEX ( 0 ) + +/* The time between transmissions of the string on UART 0. This is pseudo +random in order to generate a bit or randomness to when the interrupts occur.*/ +#define mainMIN_TX_DELAY ( 40 / portTICK_RATE_MS ) +#define mainMAX_TX_DELAY ( ( portTickType ) 0x7f ) +#define mainOFFSET_TIME ( ( portTickType ) 3 ) + +/* The time the Comms Rx task should wait to receive a character. This should +be slightly longer than the time between transmissions. If we do not receive +a character after this time then there must be an error in the transmission or +the timing of the transmission. */ +#define mainCOMMS_RX_DELAY ( mainMAX_TX_DELAY + 20 ) + +/* The task priorites. */ +#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainCOMMS_RX_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The LED's toggled by the various tasks. */ +#define mainCOMMS_FAIL_LED ( 7 ) +#define mainCOMMS_RX_LED ( 6 ) +#define mainCOMMS_TX_LED ( 5 ) + +/* The baud rate used by the UART comms tasks/co-routine. */ +#define mainBAUD_RATE ( 57600 ) + +/* FIFO setting for the UART. The FIFO is not used to create a better test. */ +#define mainFIFO_SET ( 0x10 ) + +/* The string that is transmitted on the UART contains sequentially the +characters from mainFIRST_TX_CHAR to mainLAST_TX_CHAR. */ +#define mainFIRST_TX_CHAR '0' +#define mainLAST_TX_CHAR 'z' + +/* Just used to walk through the program memory in order that some random data +can be generated. */ +#define mainTOTAL_PROGRAM_MEMORY ( ( unsigned portLONG * ) ( 8 * 1024 ) ) +#define mainFIRST_PROGRAM_BYTES ( ( unsigned portLONG * ) 4 ) + +/* The error routine that is called if the driver library encounters an error. */ +#ifdef DEBUG +void +__error__(char *pcFilename, unsigned long ulLine) +{ +} +#endif + +/*-----------------------------------------------------------*/ + +/* + * The task that rotates text on the LCD. + */ +static void vLCDTask( void * pvParameters ); + +/* + * The task that receives the characters from UART 0. + */ +static void vCommsRxTask( void * pvParameters ); + +/* + * The co-routine that periodically initiates the transmission of the string on + * the UART. + */ +static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + +/* + * Writes a string the the LCD. + */ +static void prvWriteString( const portCHAR *pcString ); + +/* + * Initialisation routine for the UART. + */ +static void vSerialInit( void ); + +/* + * Thread safe write to the PDC. + */ +static void prvPDCWrite( portCHAR cAddress, portCHAR cData ); + +/* + * Function to simply set a known value into the general purpose registers + * then read them back to ensure they remain set correctly. An incorrect value + * being indicative of an error in the task switching mechanism. + */ +void prvSetAndCheckRegisters( void ); + +/* + * Latch the LED that indicates that an error has occurred. + */ +void vSetErrorLED( void ); + +/* + * Sets up the PLL and ports used by the demo. + */ +static void prvSetupHardware( void ); + +/*-----------------------------------------------------------*/ + +/* Error flag set to pdFAIL if an error is encountered in the tasks/co-routines +defined within this file. */ +unsigned portBASE_TYPE uxErrorStatus = pdPASS; + +/* The next character to transmit. */ +static portCHAR cNextChar; + +/* The queue used to transmit characters from the interrupt to the Comms Rx +task. */ +static xQueueHandle xCommsQueue; + +/*-----------------------------------------------------------*/ + +void Main( void ) +{ + /* Create the queue used to communicate between the UART ISR and the Comms + Rx task. */ + xCommsQueue = xQueueCreate( mainRX_QUEUE_LEN, sizeof( portCHAR ) ); + + /* Setup the ports used by the demo and the clock. */ + prvSetupHardware(); + + /* Create the co-routines that flash the LED's. */ + vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES ); + + /* Create the co-routine that initiates the transmission of characters + on the UART. */ + xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX ); + + /* Create the LCD and Comms Rx tasks. */ + xTaskCreate( vLCDTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL ); + xTaskCreate( vCommsRxTask, "CMS", configMINIMAL_STACK_SIZE, NULL, mainCOMMS_RX_TASK_PRIORITY, NULL ); + + /* Start the scheduler running the tasks and co-routines just created. */ + vTaskStartScheduler(); + + /* Should not get here unless we did not have enough memory to start the + scheduler. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Setup the PLL. */ + SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); + + /* Initialise the hardware used to talk to the LCD, LED's and UART. */ + PDCInit(); + vParTestInitialise(); + vSerialInit(); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ + /* The co-routines are executed in the idle task using the idle task + hook. */ + for( ;; ) + { + /* Schedule the co-routines. */ + vCoRoutineSchedule(); + + /* Run the register check function between each co-routine. */ + prvSetAndCheckRegisters(); + } +} +/*-----------------------------------------------------------*/ + +static void prvWriteString( const portCHAR *pcString ) +{ + /* Write pcString to the LED, pausing between each character. */ + prvPDCWrite(PDC_LCD_CSR, LCD_CLEAR); + while( *pcString ) + { + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_RAM, *pcString ); + pcString++; + } +} +/*-----------------------------------------------------------*/ + +void vLCDTask( void * pvParameters ) +{ +unsigned portBASE_TYPE uxIndex; +const unsigned portCHAR ucCFGData[] = { + 0x30, /* Set data bus to 8-bits. */ + 0x30, + 0x30, + 0x3C, /* Number of lines/font. */ + 0x08, /* Display off. */ + 0x01, /* Display clear. */ + 0x06, /* Entry mode [cursor dir][shift]. */ + 0x0C /* Display on [display on][curson on][blinking on]. */ + }; + +/* The strings that are written to the LCD. */ +const portCHAR *pcStringsToDisplay[] = { + "Stellaris", + "Demo", + "One", + "www.FreeRTOS.org", + "" + }; + + /* Configure the LCD. */ + uxIndex = 0; + while( uxIndex < sizeof( ucCFGData ) ) + { + prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] ); + uxIndex++; + vTaskDelay( mainCHAR_WRITE_DELAY ); + } + + /* Turn the LCD Backlight on. */ + prvPDCWrite( PDC_CSR, 0x01 ); + + /* Clear display. */ + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR ); + + uxIndex = 0; + for( ;; ) + { + /* Display the string on the LCD. */ + prvWriteString( pcStringsToDisplay[ uxIndex ] ); + + /* Move on to the next string - wrapping if necessary. */ + uxIndex++; + if( *( pcStringsToDisplay[ uxIndex ] ) == 0x00 ) + { + uxIndex = 0; + /* Longer pause on the last string to be sent. */ + vTaskDelay( mainSTRING_WRITE_DELAY * 2 ); + } + + /* Wait until it is time to move onto the next string. */ + vTaskDelay( mainSTRING_WRITE_DELAY ); + } +} +/*-----------------------------------------------------------*/ + +static void vCommsRxTask( void * pvParameters ) +{ +static portCHAR cRxedChar, cExpectedChar; + + /* Set the char we expect to receive to the start of the string. */ + cExpectedChar = mainFIRST_TX_CHAR; + + for( ;; ) + { + /* Wait for a character to be received. */ + xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY ); + + /* Was the character recived (if any) the expected character. */ + if( cRxedChar != cExpectedChar ) + { + /* Got an unexpected character. This can sometimes occur when + reseting the system using the debugger leaving characters already + in the UART regsters. */ + uxErrorStatus = pdFAIL; + + /* Resync by waiting for the end of the current string. */ + while( cRxedChar != mainLAST_TX_CHAR ) + { + while( !xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, portMAX_DELAY ) ); + } + + /* The next expected character is the start of the string again. */ + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + if( cExpectedChar == mainLAST_TX_CHAR ) + { + /* We have reached the end of the string - we now expect to + receive the first character in the string again. The LED is + toggled to indicate that the entire string was received without + error. */ + vParTestToggleLED( mainCOMMS_RX_LED ); + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + /* We got the expected character, we now expect to receive the + next character in the string. */ + cExpectedChar++; + } + } + } +} +/*-----------------------------------------------------------*/ + +static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +portTickType xDelayPeriod; +static unsigned portLONG *pulRandomBytes = mainFIRST_PROGRAM_BYTES; + + /* Co-routine MUST start with a call to crSTART. */ + crSTART( xHandle ); + + for(;;) + { + /* Was the previously transmitted string received correctly? */ + if( uxErrorStatus != pdPASS ) + { + /* An error was encountered so set the error LED. */ + vSetErrorLED(); + } + + /* The next character to Tx is the first in the string. */ + cNextChar = mainFIRST_TX_CHAR; + + UARTIntDisable( UART0_BASE, UART_INT_TX ); + { + /* Send the first character. */ + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + + /* Move the variable to the char to Tx on so the ISR transmits + the next character in the string once this one has completed. */ + cNextChar++; + } + UARTIntEnable(UART0_BASE, UART_INT_TX); + + /* Toggle the LED to show a new string is being transmitted. */ + vParTestToggleLED( mainCOMMS_TX_LED ); + + /* Delay before we start the string off again. A pseudo-random delay + is used as this will provide a better test. */ + xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes ); + + pulRandomBytes++; + if( pulRandomBytes > mainTOTAL_PROGRAM_MEMORY ) + { + pulRandomBytes = mainFIRST_PROGRAM_BYTES; + } + + /* Make sure we don't wait too long... */ + xDelayPeriod &= mainMAX_TX_DELAY; + + /* ...but we do want to wait. */ + if( xDelayPeriod < mainMIN_TX_DELAY ) + { + xDelayPeriod = mainMIN_TX_DELAY; + } + + /* Block for the random(ish) time. */ + crDELAY( xHandle, xDelayPeriod ); + } + + /* Co-routine MUST end with a call to crEND. */ + crEND(); +} +/*-----------------------------------------------------------*/ + +static void vSerialInit( void ) +{ + /* Enable the UART. GPIOA has already been initialised. */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + + /* Set GPIO A0 and A1 as peripheral function. They are used to output the + UART signals. */ + GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); + + /* Configure the UART for 8-N-1 operation. */ + UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); + + /* We dont want to use the fifo. This is for test purposes to generate + as many interrupts as possible. */ + HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET; + + /* Enable both Rx and Tx interrupts. */ + HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX ); + IntEnable( INT_UART0 ); +} +/*-----------------------------------------------------------*/ + +void vUART_ISR(void) +{ +unsigned portLONG ulStatus; +portCHAR cRxedChar; +portBASE_TYPE xTaskWokenByPost = pdFALSE; + + /* What caused the interrupt. */ + ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); + + /* Clear the interrupt. */ + UARTIntClear( UART0_BASE, ulStatus ); + + /* Was an Rx interrpt pending? */ + if( ulStatus & UART_INT_RX ) + { + if( ( HWREG(UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) ) + { + /* Get the char from the buffer and post it onto the queue of + Rxed chars. Posting the character should wake the task that is + blocked on the queue waiting for characters. */ + cRxedChar = ( portCHAR ) HWREG( UART0_BASE + UART_O_DR ); + xTaskWokenByPost = xQueueSendFromISR( xCommsQueue, &cRxedChar, xTaskWokenByPost ); + } + } + + /* Was a Tx interrupt pending? */ + if( ulStatus & UART_INT_TX ) + { + /* Send the next character in the string. We are not using the FIFO. */ + if( cNextChar <= mainLAST_TX_CHAR ) + { + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + cNextChar++; + } + } + + if( xTaskWokenByPost ) + { + /* If a task was woken by the character being received then we force + a context switch to occur in case the task is of higher priority than + the currently executing task (i.e. the task that this interrupt + interrupted.) */ + portEND_SWITCHING_ISR( xTaskWokenByPost ); + } +} +/*-----------------------------------------------------------*/ + +static void prvPDCWrite( portCHAR cAddress, portCHAR cData ) +{ + vTaskSuspendAll(); + { + PDCWrite( cAddress, cData ); + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vSetErrorLED( void ) +{ + vParTestSetLED( mainCOMMS_FAIL_LED, pdTRUE ); +} +/*-----------------------------------------------------------*/ + +void prvSetAndCheckRegisters( void ) +{ + /* Fill the general purpose registers with known values. */ + __asm volatile( " mov r11, #10\n" + " add r0, r11, #1\n" + " add r1, r11, #2\n" + " add r2, r11, #3\n" + " add r3, r11, #4\n" + " add r4, r11, #5\n" + " add r5, r11, #6\n" + " add r6, r11, #7\n" + " add r7, r11, #8\n" + " add r8, r11, #9\n" + " add r9, r11, #10\n" + " add r10, r11, #11\n" + " add r12, r11, #12" ); + + /* Check the values are as expected. */ + __asm volatile( " cmp r11, #10\n" + " bne set_error_led\n" + " cmp r0, #11\n" + " bne set_error_led\n" + " cmp r1, #12\n" + " bne set_error_led\n" + " cmp r2, #13\n" + " bne set_error_led\n" + " cmp r3, #14\n" + " bne set_error_led\n" + " cmp r4, #15\n" + " bne set_error_led\n" + " cmp r5, #16\n" + " bne set_error_led\n" + " cmp r6, #17\n" + " bne set_error_led\n" + " cmp r7, #18\n" + " bne set_error_led\n" + " cmp r8, #19\n" + " bne set_error_led\n" + " cmp r9, #20\n" + " bne set_error_led\n" + " cmp r10, #21\n" + " bne set_error_led\n" + " cmp r12, #22\n" + " bne set_error_led\n" + " bx lr" ); + + __asm volatile( "set_error_led:\n" + " push {r14}\n" + " ldr r1, =vSetErrorLED\n" + " blx r1\n" + " pop {r14}\n" + " bx lr" ); +} +/*-----------------------------------------------------------*/ diff --git a/20080212/Demo/CORTEX_LM3S102_GCC/Demo1/readme.txt b/20080212/Demo/CORTEX_LM3S102_GCC/Demo1/readme.txt new file mode 100644 index 000000000..208a58805 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_GCC/Demo1/readme.txt @@ -0,0 +1,3 @@ +Move these two fines into the Demo/CORTEX_LM3S102_GCC directory to run Demo 1. + +See the port documentation on the www.FreeRTOS.org site for more information. diff --git a/20080212/Demo/CORTEX_LM3S102_GCC/Demo2/FreeRTOSConfig.h b/20080212/Demo/CORTEX_LM3S102_GCC/Demo2/FreeRTOSConfig.h new file mode 100644 index 000000000..988846de9 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_GCC/Demo2/FreeRTOSConfig.h @@ -0,0 +1,86 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 59 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1240 ) ) +#define configMAX_TASK_NAME_LEN ( 3 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_CO_ROUTINES 1 + +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 3 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 0 +#define INCLUDE_vTaskDelayUntil 0 +#define INCLUDE_vTaskDelay 1 + + + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/CORTEX_LM3S102_GCC/Demo2/main.c b/20080212/Demo/CORTEX_LM3S102_GCC/Demo2/main.c new file mode 100644 index 000000000..3903b61ce --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_GCC/Demo2/main.c @@ -0,0 +1,610 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + * This demo application creates seven co-routines and one task (two including + * the idle task). The co-routines execute as part of the idle task hook. + * + * Five of the created co-routines are the standard 'co-routine flash' + * co-routines contained within the Demo/Common/Minimal/crflash.c file and + * documented on the FreeRTOS.org WEB site. + * + * The 'LCD Task' rotates a string on the LCD, delaying between each character + * as necessitated by the slow interface, and delaying between each string just + * long enough to enable the text to be read. + * + * The sixth co-routine controls the transmission of a string to UART 0. The + * co-routine periodically sends the first character of the string to the UART, + * with the UART's TxEnd interrupt being used to transmit the remaining + * characters. The UART's RxEnd interrupt receives the characters and places + * them on a queue to be processed by the seventh and final co-routine. An + * error is latched should an unexpected character be received, or any + * character be received out of sequence. + * + * A loopback connector is required to ensure that each character transmitted + * on the UART is also received on the same UART. For test purposes the UART + * FIFO's are not utalised in order to maximise the interrupt overhead. Also + * a pseudo random interval is used between the start of each transmission in + * order that the resultant interrupts are more randomly distributed and + * therefore more likely to highlight any problems. + * + * The flash co-routines control LED's zero to four. LED five is toggled each + * time the string is transmitted on the UART. LED six is toggled each time + * the string is CORRECTLY received on the UART. LED seven is latched on should + * an error be detected in any task or co-routine. + * + * In addition the idle task makes repetative calls to + * prvSetAndCheckRegisters(). This simply loads the general purpose registers + * with a known value, then checks each register to ensure the held value is + * still correct. As a low priority task this checking routine is likely to + * get repeatedly swapped in and out. A register being found to contain an + * incorrect value is therefore indicative of an error in the task switching + * mechansim. + * + */ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "croutine.h" + +/* Demo application include files. */ +#include "partest.h" +#include "crflash.h" + +/* Library include files. */ +#include "DriverLib.h" + +/* The time to delay between writing each character to the LCD. */ +#define mainCHAR_WRITE_DELAY ( 2 / portTICK_RATE_MS ) + +/* The time to delay between writing each string to the LCD. */ +#define mainSTRING_WRITE_DELAY ( 400 / portTICK_RATE_MS ) + +/* The number of flash co-routines to create. */ +#define mainNUM_FLASH_CO_ROUTINES ( 5 ) + +/* The length of the queue used to pass received characters to the Comms Rx +task. */ +#define mainRX_QUEUE_LEN ( 5 ) + +/* The priority of the co-routine used to initiate the transmission of the +string on UART 0. */ +#define mainTX_CO_ROUTINE_PRIORITY ( 1 ) + +/* The priority of the co-routine used to receive characters from the UART. */ +#define mainRX_CO_ROUTINE_PRIORITY ( 2 ) + +/* Only one co-routine is created so its index is not important. */ +#define mainTX_CO_ROUTINE_INDEX ( 0 ) +#define mainRX_CO_ROUTINE_INDEX ( 0 ) + +/* The time between transmissions of the string on UART 0. This is pseudo +random in order to generate a bit or randomness to when the interrupts occur.*/ +#define mainMIN_TX_DELAY ( 40 / portTICK_RATE_MS ) +#define mainMAX_TX_DELAY ( ( portTickType ) 0x7f ) +#define mainOFFSET_TIME ( ( portTickType ) 3 ) + +/* The time the Comms Rx task should wait to receive a character. This should +be slightly longer than the time between transmissions. If we do not receive +a character after this time then there must be an error in the transmission or +the timing of the transmission. */ +#define mainCOMMS_RX_DELAY ( mainMAX_TX_DELAY + 20 ) + +/* The task priorites. */ +#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainCOMMS_RX_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The LED's toggled by the various tasks. */ +#define mainCOMMS_FAIL_LED ( 7 ) +#define mainCOMMS_RX_LED ( 6 ) +#define mainCOMMS_TX_LED ( 5 ) + +/* The baud rate used by the UART comms tasks/co-routine. */ +#define mainBAUD_RATE ( 57600 ) + +/* FIFO setting for the UART. The FIFO is not used to create a better test. */ +#define mainFIFO_SET ( 0x10 ) + +/* The string that is transmitted on the UART contains sequentially the +characters from mainFIRST_TX_CHAR to mainLAST_TX_CHAR. */ +#define mainFIRST_TX_CHAR '0' +#define mainLAST_TX_CHAR 'z' + +/* Just used to walk through the program memory in order that some random data +can be generated. */ +#define mainTOTAL_PROGRAM_MEMORY ( ( unsigned portLONG * ) ( 8 * 1024 ) ) +#define mainFIRST_PROGRAM_BYTES ( ( unsigned portLONG * ) 4 ) + +/* The error routine that is called if the driver library encounters an error. */ +#ifdef DEBUG +void +__error__(char *pcFilename, unsigned long ulLine) +{ +} +#endif + +/*-----------------------------------------------------------*/ + +/* + * The task that rotates text on the LCD. + */ +static void vLCDTask( void * pvParameters ); + +/* + * The task that receives the characters from UART 0. + */ +static void vCommsRxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + +/* + * The co-routine that periodically initiates the transmission of the string on + * the UART. + */ +static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + +/* + * Writes a string the the LCD. + */ +static void prvWriteString( const portCHAR *pcString ); + +/* + * Initialisation routine for the UART. + */ +static void vSerialInit( void ); + +/* + * Thread safe write to the PDC. + */ +static void prvPDCWrite( portCHAR cAddress, portCHAR cData ); + +/* + * Function to simply set a known value into the general purpose registers + * then read them back to ensure they remain set correctly. An incorrect value + * being indicative of an error in the task switching mechanism. + */ +void prvSetAndCheckRegisters( void ); + +/* + * Latch the LED that indicates that an error has occurred. + */ +void vSetErrorLED( void ); + +/* + * Sets up the PLL and ports used by the demo. + */ +static void prvSetupHardware( void ); + +/*-----------------------------------------------------------*/ + +/* Error flag set to pdFAIL if an error is encountered in the tasks/co-routines +defined within this file. */ +unsigned portBASE_TYPE uxErrorStatus = pdPASS; + +/* The next character to transmit. */ +static portCHAR cNextChar; + +/* The queue used to transmit characters from the interrupt to the Comms Rx +task. */ +static xQueueHandle xCommsQueue; + +/*-----------------------------------------------------------*/ + +void Main( void ) +{ + /* Create the queue used to communicate between the UART ISR and the Comms + Rx task. */ + xCommsQueue = xQueueCreate( mainRX_QUEUE_LEN, sizeof( portCHAR ) ); + + /* Setup the ports used by the demo and the clock. */ + prvSetupHardware(); + + /* Create the co-routines that flash the LED's. */ + vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES ); + + /* Create the co-routine that initiates the transmission of characters + on the UART. */ + xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX ); + + /* Create the co-routine that receives characters from the UART. */ + xCoRoutineCreate( vCommsRxCoRoutine, mainRX_CO_ROUTINE_PRIORITY, mainRX_CO_ROUTINE_INDEX ); + + /* Create the LCD task. */ + xTaskCreate( vLCDTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL ); + + /* Start the scheduler running the tasks and co-routines just created. */ + vTaskStartScheduler(); + + /* Should not get here unless we did not have enough memory to start the + scheduler. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Setup the PLL. */ + SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); + + /* Initialise the hardware used to talk to the LCD, LED's and UART. */ + PDCInit(); + vParTestInitialise(); + vSerialInit(); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ + /* The co-routines are executed in the idle task using the idle task + hook. */ + for( ;; ) + { + /* Schedule the co-routines. */ + vCoRoutineSchedule(); + + /* Run the register check function between each co-routine. */ + prvSetAndCheckRegisters(); + } +} +/*-----------------------------------------------------------*/ + +static void prvWriteString( const portCHAR *pcString ) +{ + /* Write pcString to the LED, pausing between each character. */ + prvPDCWrite(PDC_LCD_CSR, LCD_CLEAR); + while( *pcString ) + { + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_RAM, *pcString ); + pcString++; + } +} +/*-----------------------------------------------------------*/ + +void vLCDTask( void * pvParameters ) +{ +unsigned portBASE_TYPE uxIndex; +const unsigned portCHAR ucCFGData[] = { + 0x30, /* Set data bus to 8-bits. */ + 0x30, + 0x30, + 0x3C, /* Number of lines/font. */ + 0x08, /* Display off. */ + 0x01, /* Display clear. */ + 0x06, /* Entry mode [cursor dir][shift]. */ + 0x0C /* Display on [display on][curson on][blinking on]. */ + }; + +/* The strings that are written to the LCD. */ +const portCHAR *pcStringsToDisplay[] = { + "Stellaris", + "Demo", + "Two", + "www.FreeRTOS.org", + "" + }; + + /* Configure the LCD. */ + uxIndex = 0; + while( uxIndex < sizeof( ucCFGData ) ) + { + prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] ); + uxIndex++; + vTaskDelay( mainCHAR_WRITE_DELAY ); + } + + /* Turn the LCD Backlight on. */ + prvPDCWrite( PDC_CSR, 0x01 ); + + /* Clear display. */ + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR ); + + uxIndex = 0; + for( ;; ) + { + /* Display the string on the LCD. */ + prvWriteString( pcStringsToDisplay[ uxIndex ] ); + + /* Move on to the next string - wrapping if necessary. */ + uxIndex++; + if( *( pcStringsToDisplay[ uxIndex ] ) == 0x00 ) + { + uxIndex = 0; + /* Longer pause on the last string to be sent. */ + vTaskDelay( mainSTRING_WRITE_DELAY * 2 ); + } + + /* Wait until it is time to move onto the next string. */ + vTaskDelay( mainSTRING_WRITE_DELAY ); + } +} +/*-----------------------------------------------------------*/ + +static void vCommsRxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +static portCHAR cRxedChar, cExpectedChar = mainFIRST_TX_CHAR; +portBASE_TYPE xResult; + + crSTART( xHandle ); + + for( ;; ) + { + /* Wait for a character to be received. */ + crQUEUE_RECEIVE( xHandle, xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY, &xResult ); + + /* Was the character recived (if any) the expected character. */ + if( ( cRxedChar != cExpectedChar ) || ( xResult != pdPASS ) ) + { + /* Got an unexpected character. This can sometimes occur when + reseting the system using the debugger leaving characters already + in the UART regsters. */ + uxErrorStatus = pdFAIL; + + /* Resync by waiting for the end of the current string. */ + while( cRxedChar != mainLAST_TX_CHAR ) + { + crQUEUE_RECEIVE( xHandle, xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY, &xResult ); + } + + /* The next expected character is the start of the string again. */ + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + if( cExpectedChar == mainLAST_TX_CHAR ) + { + /* We have reached the end of the string - we now expect to + receive the first character in the string again. The LED is + toggled to indicate that the entire string was received without + error. */ + vParTestToggleLED( mainCOMMS_RX_LED ); + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + /* We got the expected character, we now expect to receive the + next character in the string. */ + cExpectedChar++; + } + } + } + + crEND(); +} +/*-----------------------------------------------------------*/ + +static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +portTickType xDelayPeriod; +static unsigned portLONG *pulRandomBytes = mainFIRST_PROGRAM_BYTES; + + /* Co-routine MUST start with a call to crSTART. */ + crSTART( xHandle ); + + for(;;) + { + /* Was the previously transmitted string received correctly? */ + if( uxErrorStatus != pdPASS ) + { + /* An error was encountered so set the error LED. */ + vSetErrorLED(); + } + + /* The next character to Tx is the first in the string. */ + cNextChar = mainFIRST_TX_CHAR; + + UARTIntDisable( UART0_BASE, UART_INT_TX ); + { + /* Send the first character. */ + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + + /* Move the variable to the char to Tx on so the ISR transmits + the next character in the string once this one has completed. */ + cNextChar++; + } + UARTIntEnable(UART0_BASE, UART_INT_TX); + + /* Toggle the LED to show a new string is being transmitted. */ + vParTestToggleLED( mainCOMMS_TX_LED ); + + /* Delay before we start the string off again. A pseudo-random delay + is used as this will provide a better test. */ + xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes ); + + pulRandomBytes++; + if( pulRandomBytes > mainTOTAL_PROGRAM_MEMORY ) + { + pulRandomBytes = mainFIRST_PROGRAM_BYTES; + } + + /* Make sure we don't wait too long... */ + xDelayPeriod &= mainMAX_TX_DELAY; + + /* ...but we do want to wait. */ + if( xDelayPeriod < mainMIN_TX_DELAY ) + { + xDelayPeriod = mainMIN_TX_DELAY; + } + + /* Block for the random(ish) time. */ + crDELAY( xHandle, xDelayPeriod ); + } + + /* Co-routine MUST end with a call to crEND. */ + crEND(); +} +/*-----------------------------------------------------------*/ + +static void vSerialInit( void ) +{ + /* Enable the UART. GPIOA has already been initialised. */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + + /* Set GPIO A0 and A1 as peripheral function. They are used to output the + UART signals. */ + GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); + + /* Configure the UART for 8-N-1 operation. */ + UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); + + /* We dont want to use the fifo. This is for test purposes to generate + as many interrupts as possible. */ + HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET; + + /* Enable both Rx and Tx interrupts. */ + HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX ); + IntEnable( INT_UART0 ); +} +/*-----------------------------------------------------------*/ + +void vUART_ISR(void) +{ +unsigned portLONG ulStatus; +portCHAR cRxedChar; +portBASE_TYPE xTaskWokenByPost = pdFALSE; + + /* What caused the interrupt. */ + ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); + + /* Clear the interrupt. */ + UARTIntClear( UART0_BASE, ulStatus ); + + /* Was an Rx interrpt pending? */ + if( ulStatus & UART_INT_RX ) + { + if( ( HWREG(UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) ) + { + /* Get the char from the buffer and post it onto the queue of + Rxed chars. Posting the character should wake the task that is + blocked on the queue waiting for characters. */ + cRxedChar = ( portCHAR ) HWREG( UART0_BASE + UART_O_DR ); + xTaskWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsQueue, &cRxedChar, xTaskWokenByPost ); + } + } + + /* Was a Tx interrupt pending? */ + if( ulStatus & UART_INT_TX ) + { + /* Send the next character in the string. We are not using the FIFO. */ + if( cNextChar <= mainLAST_TX_CHAR ) + { + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + cNextChar++; + } + } + + if( xTaskWokenByPost ) + { + /* We are posting to a co-routine rather than a task so don't bother + causing a task switch. */ + } +} +/*-----------------------------------------------------------*/ + +static void prvPDCWrite( portCHAR cAddress, portCHAR cData ) +{ + vTaskSuspendAll(); + { + PDCWrite( cAddress, cData ); + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vSetErrorLED( void ) +{ + vParTestSetLED( mainCOMMS_FAIL_LED, pdTRUE ); +} +/*-----------------------------------------------------------*/ + +void prvSetAndCheckRegisters( void ) +{ + /* Fill the general purpose registers with known values. */ + __asm volatile( " mov r11, #10\n" + " add r0, r11, #1\n" + " add r1, r11, #2\n" + " add r2, r11, #3\n" + " add r3, r11, #4\n" + " add r4, r11, #5\n" + " add r5, r11, #6\n" + " add r6, r11, #7\n" + " add r7, r11, #8\n" + " add r12, r11, #12" ); + + /* Check the values are as expected. */ + __asm volatile( " cmp r11, #10\n" + " bne set_error_led\n" + " cmp r0, #11\n" + " bne set_error_led\n" + " cmp r1, #12\n" + " bne set_error_led\n" + " cmp r2, #13\n" + " bne set_error_led\n" + " cmp r3, #14\n" + " bne set_error_led\n" + " cmp r4, #15\n" + " bne set_error_led\n" + " cmp r5, #16\n" + " bne set_error_led\n" + " cmp r6, #17\n" + " bne set_error_led\n" + " cmp r7, #18\n" + " bne set_error_led\n" + " cmp r12, #22\n" + " bne set_error_led\n" + " bx lr" ); + + __asm volatile( "set_error_led:\n" + " push {r14}\n" + " ldr r1, =vSetErrorLED\n" + " blx r1\n" + " pop {r14}\n" + " bx lr" ); +} +/*-----------------------------------------------------------*/ diff --git a/20080212/Demo/CORTEX_LM3S102_GCC/Demo2/readme.txt b/20080212/Demo/CORTEX_LM3S102_GCC/Demo2/readme.txt new file mode 100644 index 000000000..e22c810ac --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_GCC/Demo2/readme.txt @@ -0,0 +1,3 @@ +Move these two fines into the Demo/CORTEX_LM3S102_GCC directory to run Demo 2. + +See the port documentation on the www.FreeRTOS.org site for more information. diff --git a/20080212/Demo/CORTEX_LM3S102_GCC/FreeRTOSConfig.h b/20080212/Demo/CORTEX_LM3S102_GCC/FreeRTOSConfig.h new file mode 100644 index 000000000..e403b289e --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_GCC/FreeRTOSConfig.h @@ -0,0 +1,86 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 59 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1468 ) ) +#define configMAX_TASK_NAME_LEN ( 3 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_CO_ROUTINES 1 + +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 0 +#define INCLUDE_vTaskDelayUntil 0 +#define INCLUDE_vTaskDelay 1 + + + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/CORTEX_LM3S102_GCC/Makefile b/20080212/Demo/CORTEX_LM3S102_GCC/Makefile new file mode 100644 index 000000000..d587fd2e7 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_GCC/Makefile @@ -0,0 +1,86 @@ +#****************************************************************************** +# +# Makefile - Rules for building the driver library and examples. +# +# Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +# +# Software License Agreement +# +# Luminary Micro, Inc. (LMI) is supplying this software for use solely and +# exclusively on LMI's Stellaris Family of microcontroller products. +# +# The software is owned by LMI and/or its suppliers, and is protected under +# applicable copyright laws. All rights are reserved. Any use in violation +# of the foregoing restrictions may subject the user to criminal sanctions +# under applicable laws, as well as to civil liability for the breach of the +# terms and conditions of this license. +# +# THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +# OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +# LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +# CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +# +#****************************************************************************** + +include makedefs + +RTOS_SOURCE_DIR=../../Source +DEMO_SOURCE_DIR=../Common/Minimal + +CFLAGS+=-I hw_include -I . -I ${RTOS_SOURCE_DIR}/include -I ${RTOS_SOURCE_DIR}/portable/GCC/ARM_CM3 -I ../Common/include -D GCC_ARMCM3_LM3S102 -D inline= + +VPATH=${RTOS_SOURCE_DIR}:${RTOS_SOURCE_DIR}/portable/MemMang:${RTOS_SOURCE_DIR}/portable/GCC/ARM_CM3:${DEMO_SOURCE_DIR}:init:ParTest:hw_include + + +OBJS= ${COMPILER}/main.o \ + ${COMPILER}/pdc.o \ + ${COMPILER}/list.o \ + ${COMPILER}/queue.o \ + ${COMPILER}/tasks.o \ + ${COMPILER}/port.o \ + ${COMPILER}/heap_1.o \ + ${COMPILER}/ParTest.o \ + ${COMPILER}/crflash.o \ + ${COMPILER}/croutine.o +# ${COMPILER}/pendsv_handler.o + +INIT_OBJS= ${COMPILER}/startup.o + +LIBS= hw_include/libdriver.a + + +# +# The default rule, which causes init to be built. +# +all: ${COMPILER} \ + ${COMPILER}/RTOSDemo.axf \ + +# +# The rule to clean out all the build products +# + +clean: + @rm -rf ${COMPILER} ${wildcard *.bin} RTOSDemo.axf + +# +# The rule to create the target directory +# +${COMPILER}: + @mkdir ${COMPILER} + +${COMPILER}/RTOSDemo.axf: ${INIT_OBJS} ${OBJS} ${LIBS} +SCATTER_RTOSDemo=standalone.ld +ENTRY_RTOSDemo=ResetISR + +# +# +# Include the automatically generated dependency files. +# +-include ${wildcard ${COMPILER}/*.d} __dummy__ + + + + + + diff --git a/20080212/Demo/CORTEX_LM3S102_GCC/ParTest/ParTest.c b/20080212/Demo/CORTEX_LM3S102_GCC/ParTest/ParTest.c new file mode 100644 index 000000000..a95105b84 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_GCC/ParTest/ParTest.c @@ -0,0 +1,122 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +/* +*/ + + +#include "FreeRTOS.h" +#include "Task.h" +#include "partest.h" + +#include "pdc.h" + +#define partstPINS (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 Z | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7) + +#define partstALL_OUTPUTS_OFF ( ( unsigned portCHAR ) 0x00 ) +#define partstMAX_OUTPUT_LED ( ( unsigned portCHAR ) 8 ) + +static volatile unsigned portCHAR ucOutputValue = partstALL_OUTPUTS_OFF; + +void vParTestInitialise( void ) +{ + PDCInit(); + PDCWrite( PDC_LED, ucOutputValue ); +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ +unsigned portCHAR ucBit = ( unsigned portCHAR ) 1; + + vTaskSuspendAll(); + { + if( uxLED < partstMAX_OUTPUT_LED ) + { + ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED; + + if( xValue == pdFALSE ) + { + ucBit ^= ( unsigned portCHAR ) 0xff; + ucOutputValue &= ucBit; + } + else + { + ucOutputValue |= ucBit; + } + + PDCWrite( PDC_LED, ucOutputValue ); + } + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned portCHAR ucBit; + + vTaskSuspendAll(); + { + if( uxLED < partstMAX_OUTPUT_LED ) + { + ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED; + + if( ucOutputValue & ucBit ) + { + ucOutputValue &= ~ucBit; + } + else + { + ucOutputValue |= ucBit; + } + + PDCWrite( PDC_LED, ucOutputValue ); + } + } + xTaskResumeAll(); +} + diff --git a/20080212/Demo/CORTEX_LM3S102_GCC/hw_include/DriverLib.h b/20080212/Demo/CORTEX_LM3S102_GCC/hw_include/DriverLib.h new file mode 100644 index 000000000..f8383de66 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_GCC/hw_include/DriverLib.h @@ -0,0 +1,18 @@ +#ifndef INCLUDE_DRIVER_LIB_H +#define INCLUDE_DRIVER_LIB_H + +#include "hw_ints.h" +#include "hw_uart.h" +#include "hw_memmap.h" +#include "hw_types.h" +#include "hw_nvic.h" +#include "hw_ssi.h" + +#include "gpio.h" +#include "interrupt.h" +#include "sysctl.h" +#include "uart.h" +#include "ssi.h" +#include "pdc.h" + +#endif diff --git a/20080212/Demo/CORTEX_LM3S102_GCC/hw_include/debug.h b/20080212/Demo/CORTEX_LM3S102_GCC/hw_include/debug.h new file mode 100644 index 000000000..2f259bd23 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_GCC/hw_include/debug.h @@ -0,0 +1,56 @@ +//***************************************************************************** +// +// debug.h - Macros for assisting debug of the driver library. +// +// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __DEBUG_H__ +#define __DEBUG_H__ + +//***************************************************************************** +// +// Prototype for the function that is called when an invalid argument is passed +// to an API. This is only used when doing a DEBUG build. +// +//***************************************************************************** +extern void __error__(char *pcFilename, unsigned long ulLine); + +//***************************************************************************** +// +// The ASSERT macro, which does the actual assertion checking. Typically, this +// will be for procedure arguments. +// +//***************************************************************************** +#ifdef DEBUG +#define ASSERT(expr) { \ + if(!(expr)) \ + { \ + __error__(__FILE__, __LINE__); \ + } \ + } +#else +#define ASSERT(expr) +#endif + +#endif // __DEBUG_H__ diff --git a/20080212/Demo/CORTEX_LM3S102_GCC/hw_include/gpio.h b/20080212/Demo/CORTEX_LM3S102_GCC/hw_include/gpio.h new file mode 100644 index 000000000..cdc9a5b19 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_GCC/hw_include/gpio.h @@ -0,0 +1,135 @@ +//***************************************************************************** +// +// gpio.h - Defines and Macros for GPIO API. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __GPIO_H__ +#define __GPIO_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following values define the bit field for the ucPins argument to several +// of the APIs. +// +//***************************************************************************** +#define GPIO_PIN_0 0x00000001 // GPIO pin 0 +#define GPIO_PIN_1 0x00000002 // GPIO pin 1 +#define GPIO_PIN_2 0x00000004 // GPIO pin 2 +#define GPIO_PIN_3 0x00000008 // GPIO pin 3 +#define GPIO_PIN_4 0x00000010 // GPIO pin 4 +#define GPIO_PIN_5 0x00000020 // GPIO pin 5 +#define GPIO_PIN_6 0x00000040 // GPIO pin 6 +#define GPIO_PIN_7 0x00000080 // GPIO pin 7 + +//***************************************************************************** +// +// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and +// returned from GPIODirModeGet. +// +//***************************************************************************** +#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input +#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output +#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function + +//***************************************************************************** +// +// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and +// returned from GPIOIntTypeGet. +// +//***************************************************************************** +#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge +#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge +#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges +#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level +#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level + +//***************************************************************************** +// +// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter, +// and returned by GPIOPadConfigGet in the *pulStrength parameter. +// +//***************************************************************************** +#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength +#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength +#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength +#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control + +//***************************************************************************** +// +// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter, +// and returned by GPIOPadConfigGet in the *pulPadType parameter. +// +//***************************************************************************** +#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull +#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up +#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down +#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain +#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up +#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down +#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulPinIO); +extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin); +extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulIntType); +extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin); +extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulStrength, + unsigned long ulPadType); +extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin, + unsigned long *pulStrength, + unsigned long *pulPadType); +extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins); +extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked); +extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPortIntRegister(unsigned long ulPort, + void (*pfIntHandler)(void)); +extern void GPIOPortIntUnregister(unsigned long ulPort); +extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, + unsigned char ucVal); +extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins); + +#ifdef __cplusplus +} +#endif + +#endif // __GPIO_H__ diff --git a/20080212/Demo/CORTEX_LM3S102_GCC/hw_include/hw_ints.h b/20080212/Demo/CORTEX_LM3S102_GCC/hw_include/hw_ints.h new file mode 100644 index 000000000..d32cec40b --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_GCC/hw_include/hw_ints.h @@ -0,0 +1,82 @@ +//***************************************************************************** +// +// hw_ints.h - Macros that define the interrupt assignment on Stellaris. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_INTS_H__ +#define __HW_INTS_H__ + +//***************************************************************************** +// +// The following define the fault assignments. +// +//***************************************************************************** +#define FAULT_NMI 2 // NMI fault +#define FAULT_HARD 3 // Hard fault +#define FAULT_MPU 4 // MPU fault +#define FAULT_BUS 5 // Bus fault +#define FAULT_USAGE 6 // Usage fault +#define FAULT_SVCALL 11 // SVCall +#define FAULT_DEBUG 12 // Debug monitor +#define FAULT_PENDSV 14 // PendSV +#define FAULT_SYSTICK 15 // System Tick + +//***************************************************************************** +// +// The following define the interrupt assignments. +// +//***************************************************************************** +#define INT_GPIOA 16 // GPIO Port A +#define INT_GPIOB 17 // GPIO Port B +#define INT_GPIOC 18 // GPIO Port C +#define INT_UART0 21 // UART0 Rx and Tx +#define INT_SSI 23 // SSI Rx and Tx +#define INT_I2C 24 // I2C Master and Slave +#define INT_WATCHDOG 34 // Watchdog timer +#define INT_TIMER0A 35 // Timer 0 subtimer A +#define INT_TIMER0B 36 // Timer 0 subtimer B +#define INT_TIMER1A 37 // Timer 1 subtimer A +#define INT_TIMER1B 38 // Timer 1 subtimer B +#define INT_COMP0 41 // Analog Comparator 0 +#define INT_COMP1 42 // Analog Comparator 1 +#define INT_SYSCTL 44 // System Control (PLL, OSC, BO) +#define INT_FLASH 45 // FLASH Control + +//***************************************************************************** +// +// The total number of interrupts. +// +//***************************************************************************** +#define NUM_INTERRUPTS 46 + +//***************************************************************************** +// +// The total number of priority levels. +// +//***************************************************************************** +#define NUM_PRIORITY 8 +#define NUM_PRIORITY_BITS 3 + +#endif // __HW_INTS_H__ diff --git a/20080212/Demo/CORTEX_LM3S102_GCC/hw_include/hw_memmap.h b/20080212/Demo/CORTEX_LM3S102_GCC/hw_include/hw_memmap.h new file mode 100644 index 000000000..bef5dc618 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_GCC/hw_include/hw_memmap.h @@ -0,0 +1,57 @@ +//***************************************************************************** +// +// hw_memmap.h - Macros defining the memory map of Stellaris. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_MEMMAP_H__ +#define __HW_MEMMAP_H__ + +//***************************************************************************** +// +// The following define the base address of the memories and peripherals. +// +//***************************************************************************** +#define FLASH_BASE 0x00000000 // FLASH memory +#define SRAM_BASE 0x20000000 // SRAM memory +#define WATCHDOG_BASE 0x40000000 // Watchdog +#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A +#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B +#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C +#define SSI_BASE 0x40008000 // SSI +#define UART0_BASE 0x4000C000 // UART0 +#define I2C_MASTER_BASE 0x40020000 // I2C Master +#define I2C_SLAVE_BASE 0x40020800 // I2C Slave +#define TIMER0_BASE 0x40030000 // Timer0 +#define TIMER1_BASE 0x40031000 // Timer1 +#define COMP_BASE 0x4003C000 // Analog comparators +#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller +#define SYSCTL_BASE 0x400FE000 // System Control +#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell +#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace +#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint +#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl +#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit + +#endif // __HW_MEMMAP_H__ diff --git a/20080212/Demo/CORTEX_LM3S102_GCC/hw_include/hw_nvic.h b/20080212/Demo/CORTEX_LM3S102_GCC/hw_include/hw_nvic.h new file mode 100644 index 000000000..77dfe716a --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_GCC/hw_include/hw_nvic.h @@ -0,0 +1,830 @@ +//***************************************************************************** +// +// hw_nvic.h - Macros used when accessing the NVIC hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_NVIC_H__ +#define __HW_NVIC_H__ + +//***************************************************************************** +// +// The following define the addresses of the NVIC registers. +// +//***************************************************************************** +#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg. +#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg. +#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register +#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register +#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg. +#define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register +#define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg. +#define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register +#define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg. +#define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register +#define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register +#define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register +#define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register +#define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register +#define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register +#define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register +#define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register +#define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register +#define NVIC_CPUID 0xE000ED00 // CPUID Base Register +#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register +#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register +#define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg. +#define NVIC_SYS_CTRL 0xE000ED10 // System Control Register +#define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register +#define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority +#define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority +#define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority +#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State +#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg. +#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register +#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register +#define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register +#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register +#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register +#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register +#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register +#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register +#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg. +#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg. +#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select +#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data +#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control +#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg. + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_INT_TYPE register. +// +//***************************************************************************** +#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) +#define NVIC_INT_TYPE_LINES_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_CTRL register. +// +//***************************************************************************** +#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag +#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source +#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable +#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_RELOAD register. +// +//***************************************************************************** +#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value +#define NVIC_ST_RELOAD_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_CURRENT register. +// +//***************************************************************************** +#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value +#define NVIC_ST_CURRENT_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_CAL register. +// +//***************************************************************************** +#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock +#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew +#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value +#define NVIC_ST_CAL_ONEMS_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_EN0 register. +// +//***************************************************************************** +#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable +#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable +#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable +#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable +#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable +#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable +#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable +#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable +#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable +#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable +#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable +#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable +#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable +#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable +#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable +#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable +#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable +#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable +#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable +#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable +#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable +#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable +#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable +#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable +#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable +#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable +#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable +#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable +#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable +#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable +#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable +#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DIS0 register. +// +//***************************************************************************** +#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable +#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable +#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable +#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable +#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable +#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable +#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable +#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable +#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable +#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable +#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable +#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable +#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable +#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable +#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable +#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable +#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable +#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable +#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable +#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable +#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable +#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable +#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable +#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable +#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable +#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable +#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable +#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable +#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable +#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable +#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable +#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PEND0 register. +// +//***************************************************************************** +#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend +#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend +#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend +#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend +#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend +#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend +#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend +#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend +#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend +#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend +#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend +#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend +#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend +#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend +#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend +#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend +#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend +#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend +#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend +#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend +#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend +#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend +#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend +#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend +#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend +#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend +#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend +#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend +#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend +#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend +#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend +#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_UNPEND0 register. +// +//***************************************************************************** +#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend +#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend +#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend +#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend +#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend +#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend +#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend +#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend +#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend +#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend +#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend +#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend +#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend +#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend +#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend +#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend +#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend +#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend +#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend +#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend +#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend +#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend +#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend +#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend +#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend +#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend +#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend +#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend +#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend +#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend +#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend +#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ACTIVE0 register. +// +//***************************************************************************** +#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active +#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active +#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active +#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active +#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active +#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active +#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active +#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active +#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active +#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active +#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active +#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active +#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active +#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active +#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active +#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active +#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active +#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active +#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active +#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active +#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active +#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active +#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active +#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active +#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active +#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active +#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active +#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active +#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active +#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active +#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active +#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI0 register. +// +//***************************************************************************** +#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask +#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask +#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask +#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask +#define NVIC_PRI0_INT3_S 24 +#define NVIC_PRI0_INT2_S 16 +#define NVIC_PRI0_INT1_S 8 +#define NVIC_PRI0_INT0_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI1 register. +// +//***************************************************************************** +#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask +#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask +#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask +#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask +#define NVIC_PRI1_INT7_S 24 +#define NVIC_PRI1_INT6_S 16 +#define NVIC_PRI1_INT5_S 8 +#define NVIC_PRI1_INT4_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI2 register. +// +//***************************************************************************** +#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask +#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask +#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask +#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask +#define NVIC_PRI2_INT11_S 24 +#define NVIC_PRI2_INT10_S 16 +#define NVIC_PRI2_INT9_S 8 +#define NVIC_PRI2_INT8_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI3 register. +// +//***************************************************************************** +#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask +#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask +#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask +#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask +#define NVIC_PRI3_INT15_S 24 +#define NVIC_PRI3_INT14_S 16 +#define NVIC_PRI3_INT13_S 8 +#define NVIC_PRI3_INT12_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI4 register. +// +//***************************************************************************** +#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask +#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask +#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask +#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask +#define NVIC_PRI4_INT19_S 24 +#define NVIC_PRI4_INT18_S 16 +#define NVIC_PRI4_INT17_S 8 +#define NVIC_PRI4_INT16_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI5 register. +// +//***************************************************************************** +#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask +#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask +#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask +#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask +#define NVIC_PRI5_INT23_S 24 +#define NVIC_PRI5_INT22_S 16 +#define NVIC_PRI5_INT21_S 8 +#define NVIC_PRI5_INT20_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI6 register. +// +//***************************************************************************** +#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask +#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask +#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask +#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask +#define NVIC_PRI6_INT27_S 24 +#define NVIC_PRI6_INT26_S 16 +#define NVIC_PRI6_INT25_S 8 +#define NVIC_PRI6_INT24_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI7 register. +// +//***************************************************************************** +#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask +#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask +#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask +#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask +#define NVIC_PRI7_INT31_S 24 +#define NVIC_PRI7_INT30_S 16 +#define NVIC_PRI7_INT29_S 8 +#define NVIC_PRI7_INT28_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_CPUID register. +// +//***************************************************************************** +#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer +#define NVIC_CPUID_VAR_M 0x00F00000 // Variant +#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number +#define NVIC_CPUID_REV_M 0x0000000F // Revision + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_INT_CTRL register. +// +//***************************************************************************** +#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI +#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV +#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV +#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling +#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending +#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception +#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base +#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception +#define NVIC_INT_CTRL_VEC_PEN_S 12 +#define NVIC_INT_CTRL_VEC_ACT_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_VTABLE register. +// +//***************************************************************************** +#define NVIC_VTABLE_BASE 0x20000000 // Vector table base +#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset +#define NVIC_VTABLE_OFFSET_S 8 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_APINT register. +// +//***************************************************************************** +#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask +#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key +#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess +#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group +#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split +#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split +#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split +#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split +#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split +#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split +#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split +#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split +#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request +#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info +#define NVIC_APINT_VECT_RESET 0x00000001 // System reset + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend +#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable +#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_CFG_CTRL register. +// +//***************************************************************************** +#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault +#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0 +#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access +#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger +#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger +#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_PRI1 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler +#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler +#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler +#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler +#define NVIC_SYS_PRI1_USAGE_S 16 +#define NVIC_SYS_PRI1_BUS_S 8 +#define NVIC_SYS_PRI1_MEM_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_PRI2 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler +#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers +#define NVIC_SYS_PRI2_SVC_S 24 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_PRI3 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler +#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler +#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler +#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler +#define NVIC_SYS_PRI3_TICK_S 24 +#define NVIC_SYS_PRI3_PENDSV_S 16 +#define NVIC_SYS_PRI3_DEBUG_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_HND_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable +#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable +#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable +#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended +#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended +#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active +#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active +#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active +#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active +#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active +#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active +#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_FAULT_STAT register. +// +//***************************************************************************** +#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault +#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault +#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault +#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault +#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault +#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault +#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid +#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault +#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault +#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error +#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error +#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault +#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid +#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation +#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation +#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation +#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_HFAULT_STAT register. +// +//***************************************************************************** +#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event +#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler +#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DEBUG_STAT register. +// +//***************************************************************************** +#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted +#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch +#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match +#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction +#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MM_ADDR register. +// +//***************************************************************************** +#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address +#define NVIC_MM_ADDR_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_FAULT_ADDR register. +// +//***************************************************************************** +#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address +#define NVIC_FAULT_ADDR_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_EXC_STACK register. +// +//***************************************************************************** +#define NVIC_EXC_STACK_DEEP 0x00000001 // Exception stack + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_EXC_NUM register. +// +//***************************************************************************** +#define NVIC_EXC_NUM_M 0x000003FF // Exception number +#define NVIC_EXC_NUM_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_COPRO register. +// +//***************************************************************************** +#define NVIC_COPRO_15_M 0xC0000000 // Coprocessor 15 access mask +#define NVIC_COPRO_15_DENIED 0x00000000 // Coprocessor 15 access denied +#define NVIC_COPRO_15_PRIV 0x40000000 // Coprocessor 15 privileged addess +#define NVIC_COPRO_15_FULL 0xC0000000 // Coprocessor 15 full access +#define NVIC_COPRO_14_M 0x30000000 // Coprocessor 14 access mask +#define NVIC_COPRO_14_DENIED 0x00000000 // Coprocessor 14 access denied +#define NVIC_COPRO_14_PRIV 0x10000000 // Coprocessor 14 privileged addess +#define NVIC_COPRO_14_FULL 0x30000000 // Coprocessor 14 full access +#define NVIC_COPRO_13_M 0x0C000000 // Coprocessor 13 access mask +#define NVIC_COPRO_13_DENIED 0x00000000 // Coprocessor 13 access denied +#define NVIC_COPRO_13_PRIV 0x04000000 // Coprocessor 13 privileged addess +#define NVIC_COPRO_13_FULL 0x0C000000 // Coprocessor 13 full access +#define NVIC_COPRO_12_M 0x03000000 // Coprocessor 12 access mask +#define NVIC_COPRO_12_DENIED 0x00000000 // Coprocessor 12 access denied +#define NVIC_COPRO_12_PRIV 0x01000000 // Coprocessor 12 privileged addess +#define NVIC_COPRO_12_FULL 0x03000000 // Coprocessor 12 full access +#define NVIC_COPRO_11_M 0x00C00000 // Coprocessor 11 access mask +#define NVIC_COPRO_11_DENIED 0x00000000 // Coprocessor 11 access denied +#define NVIC_COPRO_11_PRIV 0x00400000 // Coprocessor 11 privileged addess +#define NVIC_COPRO_11_FULL 0x00C00000 // Coprocessor 11 full access +#define NVIC_COPRO_10_M 0x00300000 // Coprocessor 10 access mask +#define NVIC_COPRO_10_DENIED 0x00000000 // Coprocessor 10 access denied +#define NVIC_COPRO_10_PRIV 0x00100000 // Coprocessor 10 privileged addess +#define NVIC_COPRO_10_FULL 0x00300000 // Coprocessor 10 full access +#define NVIC_COPRO_9_M 0x000C0000 // Coprocessor 9 access mask +#define NVIC_COPRO_9_DENIED 0x00000000 // Coprocessor 9 access denied +#define NVIC_COPRO_9_PRIV 0x00040000 // Coprocessor 9 privileged addess +#define NVIC_COPRO_9_FULL 0x000C0000 // Coprocessor 9 full access +#define NVIC_COPRO_8_M 0x00030000 // Coprocessor 8 access mask +#define NVIC_COPRO_8_DENIED 0x00000000 // Coprocessor 8 access denied +#define NVIC_COPRO_8_PRIV 0x00010000 // Coprocessor 8 privileged addess +#define NVIC_COPRO_8_FULL 0x00030000 // Coprocessor 8 full access +#define NVIC_COPRO_7_M 0x0000C000 // Coprocessor 7 access mask +#define NVIC_COPRO_7_DENIED 0x00000000 // Coprocessor 7 access denied +#define NVIC_COPRO_7_PRIV 0x00004000 // Coprocessor 7 privileged addess +#define NVIC_COPRO_7_FULL 0x0000C000 // Coprocessor 7 full access +#define NVIC_COPRO_6_M 0x00003000 // Coprocessor 6 access mask +#define NVIC_COPRO_6_DENIED 0x00000000 // Coprocessor 6 access denied +#define NVIC_COPRO_6_PRIV 0x00001000 // Coprocessor 6 privileged addess +#define NVIC_COPRO_6_FULL 0x00003000 // Coprocessor 6 full access +#define NVIC_COPRO_5_M 0x00000C00 // Coprocessor 5 access mask +#define NVIC_COPRO_5_DENIED 0x00000000 // Coprocessor 5 access denied +#define NVIC_COPRO_5_PRIV 0x00000400 // Coprocessor 5 privileged addess +#define NVIC_COPRO_5_FULL 0x00000C00 // Coprocessor 5 full access +#define NVIC_COPRO_4_M 0x00000300 // Coprocessor 4 access mask +#define NVIC_COPRO_4_DENIED 0x00000000 // Coprocessor 4 access denied +#define NVIC_COPRO_4_PRIV 0x00000100 // Coprocessor 4 privileged addess +#define NVIC_COPRO_4_FULL 0x00000300 // Coprocessor 4 full access +#define NVIC_COPRO_3_M 0x000000C0 // Coprocessor 3 access mask +#define NVIC_COPRO_3_DENIED 0x00000000 // Coprocessor 3 access denied +#define NVIC_COPRO_3_PRIV 0x00000040 // Coprocessor 3 privileged addess +#define NVIC_COPRO_3_FULL 0x000000C0 // Coprocessor 3 full access +#define NVIC_COPRO_2_M 0x00000030 // Coprocessor 2 access mask +#define NVIC_COPRO_2_DENIED 0x00000000 // Coprocessor 2 access denied +#define NVIC_COPRO_2_PRIV 0x00000010 // Coprocessor 2 privileged addess +#define NVIC_COPRO_2_FULL 0x00000030 // Coprocessor 2 full access +#define NVIC_COPRO_1_M 0x0000000C // Coprocessor 1 access mask +#define NVIC_COPRO_1_DENIED 0x00000000 // Coprocessor 1 access denied +#define NVIC_COPRO_1_PRIV 0x00000004 // Coprocessor 1 privileged addess +#define NVIC_COPRO_1_FULL 0x0000000C // Coprocessor 1 full access +#define NVIC_COPRO_0_M 0x00000003 // Coprocessor 0 access mask +#define NVIC_COPRO_0_DENIED 0x00000000 // Coprocessor 0 access denied +#define NVIC_COPRO_0_PRIV 0x00000001 // Coprocessor 0 privileged addess +#define NVIC_COPRO_0_FULL 0x00000003 // Coprocessor 0 full access + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_TYPE register. +// +//***************************************************************************** +#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions +#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions +#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU +#define NVIC_MPU_TYPE_IREGION_S 16 +#define NVIC_MPU_TYPE_DREGION_S 8 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_CTRL register. +// +//***************************************************************************** +#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults +#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_NUMBER register. +// +//***************************************************************************** +#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access +#define NVIC_MPU_NUMBER_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_BASE register. +// +//***************************************************************************** +#define NVIC_MPU_BASE_ADDR_M 0xFFFFFF00 // Base address +#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid +#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number +#define NVIC_MPU_BASE_ADDR_S 8 +#define NVIC_MPU_BASE_REGION_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_ATTR register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR_ATTRS 0xFFFF0000 // Attributes +#define NVIC_MPU_ATTR_SRD 0x0000FF00 // Sub-region disable +#define NVIC_MPU_ATTR_SZENABLE 0x000000FF // Region size + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_CTRL register. +// +//***************************************************************************** +#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask +#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key +#define NVIC_DBG_CTRL_MON_PEND 0x00008000 // Pend the monitor +#define NVIC_DBG_CTRL_MON_REQ 0x00004000 // Monitor request +#define NVIC_DBG_CTRL_MON_EN 0x00002000 // Debug monitor enable +#define NVIC_DBG_CTRL_MONSTEP 0x00001000 // Monitor step the core +#define NVIC_DBG_CTRL_S_SLEEP 0x00000400 // Core is sleeping +#define NVIC_DBG_CTRL_S_HALT 0x00000200 // Core status on halt +#define NVIC_DBG_CTRL_S_REGRDY 0x00000100 // Register read/write available +#define NVIC_DBG_CTRL_S_LOCKUP 0x00000080 // Core is locked up +#define NVIC_DBG_CTRL_C_RESET 0x00000010 // Reset the core +#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping +#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core +#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core +#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_XFER register. +// +//***************************************************************************** +#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read +#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register +#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 +#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 +#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 +#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 +#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 +#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 +#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 +#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 +#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 +#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 +#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 +#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 +#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 +#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 +#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 +#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 +#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register +#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP +#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP +#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP +#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_DATA register. +// +//***************************************************************************** +#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache +#define NVIC_DBG_DATA_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_INT register. +// +//***************************************************************************** +#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault +#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors +#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error +#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state +#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check +#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error +#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault +#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status +#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset +#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending +#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SW_TRIG register. +// +//***************************************************************************** +#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger +#define NVIC_SW_TRIG_INTID_S 0 + +#endif // __HW_NVIC_H__ diff --git a/20080212/Demo/CORTEX_LM3S102_GCC/hw_include/hw_ssi.h b/20080212/Demo/CORTEX_LM3S102_GCC/hw_include/hw_ssi.h new file mode 100644 index 000000000..37472329f --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_GCC/hw_include/hw_ssi.h @@ -0,0 +1,113 @@ +//***************************************************************************** +// +// hw_ssi.h - Macros used when accessing the SSI hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_SSI_H__ +#define __HW_SSI_H__ + +//***************************************************************************** +// +// The following define the offsets of the SSI registers. +// +//***************************************************************************** +#define SSI_O_CR0 0x00000000 // Control register 0 +#define SSI_O_CR1 0x00000004 // Control register 1 +#define SSI_O_DR 0x00000008 // Data register +#define SSI_O_SR 0x0000000C // Status register +#define SSI_O_CPSR 0x00000010 // Clock prescale register +#define SSI_O_IM 0x00000014 // Int mask set and clear register +#define SSI_O_RIS 0x00000018 // Raw interrupt register +#define SSI_O_MIS 0x0000001C // Masked interrupt register +#define SSI_O_ICR 0x00000020 // Interrupt clear register + +//***************************************************************************** +// +// The following define the bit fields in the SSI Control register 0. +// +//***************************************************************************** +#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate +#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase +#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity +#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask +#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format +#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format +#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format +#define SSI_CR0_DSS 0x0000000F // Data size select +#define SSI_CR0_DSS_4 0x00000003 // 4 bit data +#define SSI_CR0_DSS_5 0x00000004 // 5 bit data +#define SSI_CR0_DSS_6 0x00000005 // 6 bit data +#define SSI_CR0_DSS_7 0x00000006 // 7 bit data +#define SSI_CR0_DSS_8 0x00000007 // 8 bit data +#define SSI_CR0_DSS_9 0x00000008 // 9 bit data +#define SSI_CR0_DSS_10 0x00000009 // 10 bit data +#define SSI_CR0_DSS_11 0x0000000A // 11 bit data +#define SSI_CR0_DSS_12 0x0000000B // 12 bit data +#define SSI_CR0_DSS_13 0x0000000C // 13 bit data +#define SSI_CR0_DSS_14 0x0000000D // 14 bit data +#define SSI_CR0_DSS_15 0x0000000E // 15 bit data +#define SSI_CR0_DSS_16 0x0000000F // 16 bit data + +//***************************************************************************** +// +// The following define the bit fields in the SSI Control register 1. +// +//***************************************************************************** +#define SSI_CR1_SOD 0x00000008 // Slave mode output disable +#define SSI_CR1_MS 0x00000004 // Master or slave mode select +#define SSI_CR1_SSE 0x00000002 // Sync serial port enable +#define SSI_CR1_LBM 0x00000001 // Loopback mode + +//***************************************************************************** +// +// The following define the bit fields in the SSI Status register +// +//***************************************************************************** +#define SSI_SR_BSY 0x00000010 // SSI busy +#define SSI_SR_RFF 0x00000008 // RX FIFO full +#define SSI_SR_RNE 0x00000004 // RX FIFO not empty +#define SSI_SR_TNF 0x00000002 // TX FIFO not full +#define SSI_SR_TFE 0x00000001 // TX FIFO empty + +//***************************************************************************** +// +// The following define information concerning the SSI Data register. +// +//***************************************************************************** +#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO +#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO + +//***************************************************************************** +// +// The following define the bit fields in the interrupt mask set and clear, +// raw interrupt, masked interrupt, and interrupt clear registers. +// +//***************************************************************************** +#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt +#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt +#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt +#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt + +#endif // __HW_SSI_H__ diff --git a/20080212/Demo/CORTEX_LM3S102_GCC/hw_include/hw_sysctl.h b/20080212/Demo/CORTEX_LM3S102_GCC/hw_include/hw_sysctl.h new file mode 100644 index 000000000..044fec21d --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_GCC/hw_include/hw_sysctl.h @@ -0,0 +1,325 @@ +//***************************************************************************** +// +// hw_sysctl.h - Macros used when accessing the system control hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_SYSCTL_H__ +#define __HW_SYSCTL_H__ + +//***************************************************************************** +// +// The following define the offsets of the system control registers. +// +//***************************************************************************** +#define SYSCTL_DID0 0x400fe000 // Device identification register 0 +#define SYSCTL_DID1 0x400fe004 // Device identification register 1 +#define SYSCTL_DC0 0x400fe008 // Device capabilities register 0 +#define SYSCTL_DC1 0x400fe010 // Device capabilities register 1 +#define SYSCTL_DC2 0x400fe014 // Device capabilities register 2 +#define SYSCTL_DC3 0x400fe018 // Device capabilities register 3 +#define SYSCTL_DC4 0x400fe01C // Device capabilities register 4 +#define SYSCTL_PBORCTL 0x400fe030 // POR/BOR reset control register +#define SYSCTL_LDOPCTL 0x400fe034 // LDO power control register +#define SYSCTL_SRCR0 0x400fe040 // Software reset control reg 0 +#define SYSCTL_SRCR1 0x400fe044 // Software reset control reg 1 +#define SYSCTL_SRCR2 0x400fe048 // Software reset control reg 2 +#define SYSCTL_RIS 0x400fe050 // Raw interrupt status register +#define SYSCTL_IMC 0x400fe054 // Interrupt mask/control register +#define SYSCTL_MISC 0x400fe058 // Interrupt status register +#define SYSCTL_RESC 0x400fe05c // Reset cause register +#define SYSCTL_RCC 0x400fe060 // Run-mode clock config register +#define SYSCTL_PLLCFG 0x400fe064 // PLL configuration register +#define SYSCTL_RCGC0 0x400fe100 // Run-mode clock gating register 0 +#define SYSCTL_RCGC1 0x400fe104 // Run-mode clock gating register 1 +#define SYSCTL_RCGC2 0x400fe108 // Run-mode clock gating register 2 +#define SYSCTL_SCGC0 0x400fe110 // Sleep-mode clock gating reg 0 +#define SYSCTL_SCGC1 0x400fe114 // Sleep-mode clock gating reg 1 +#define SYSCTL_SCGC2 0x400fe118 // Sleep-mode clock gating reg 2 +#define SYSCTL_DCGC0 0x400fe120 // Deep Sleep-mode clock gate reg 0 +#define SYSCTL_DCGC1 0x400fe124 // Deep Sleep-mode clock gate reg 1 +#define SYSCTL_DCGC2 0x400fe128 // Deep Sleep-mode clock gate reg 2 +#define SYSCTL_CLKVCLR 0x400fe150 // Clock verifcation clear register +#define SYSCTL_LDOARST 0x400fe160 // LDO reset control register + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DID0 register. +// +//***************************************************************************** +#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask +#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A +#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B +#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask +#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0 +#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DID1 register. +// +//***************************************************************************** +#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask +#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask +#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family +#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask +#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101 +#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102 +#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask +#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C) +#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C) +#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask +#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC +#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant +#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask +#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified) +#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified) +#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified +#define SYSCTL_DID1_PRTNO_SHIFT 16 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC0 register. +// +//***************************************************************************** +#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask +#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2kB of SRAM +#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask +#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8kB of flash + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC1 register. +// +//***************************************************************************** +#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask +#define SYSCTL_DC1_MPU 0x00000080 // Cortex M3 MPU present +#define SYSCTL_DC1_PLL 0x00000010 // PLL present +#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present +#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present +#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present +#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC2 register. +// +//***************************************************************************** +#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present +#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present +#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present +#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present +#define SYSCTL_DC2_I2C 0x00001000 // I2C present +#define SYSCTL_DC2_SSI 0x00000010 // SSI present +#define SYSCTL_DC2_UART0 0x00000001 // UART 0 present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC3 register. +// +//***************************************************************************** +#define SYSCTL_DC3_32KHZ 0x80000000 // 32kHz pin present +#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present +#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present +#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present +#define SYSCTL_DC3_C0O 0x00000100 // C0o pin present +#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present +#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC4 register. +// +//***************************************************************************** +#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present +#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present +#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_PBORCTL register. +// +//***************************************************************************** +#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer +#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset +#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise +#define SYSCTL_PBORCTL_BOR_SH 2 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_LDOPCTL register. +// +//***************************************************************************** +#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask +#define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V +#define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V +#define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V +#define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V +#define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V +#define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V +#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V +#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V +#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V +#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V +#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_SRCR0, SYSCTL_RCGC0, +// SYSCTL_SCGC0, and SYSCTL_DCGC0 registers. +// +//***************************************************************************** +#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_SRCR1, SYSCTL_RCGC1, +// SYSCTL_SCGC1, and SYSCTL_DCGC1 registers. +// +//***************************************************************************** +#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1 +#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0 +#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1 +#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0 +#define SYSCTL_SET1_I2C 0x00001000 // I2C module +#define SYSCTL_SET1_SSI 0x00000010 // SSI module +#define SYSCTL_SET1_UART0 0x00000001 // UART module 0 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_SRCR2, SYSCTL_RCGC2, +// SYSCTL_SCGC2, and SYSCTL_DCGC2 registers. +// +//***************************************************************************** +#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module +#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module +#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_RIS, SYSCTL_IMC, and +// SYSCTL_IMS registers. +// +//***************************************************************************** +#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt +#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt +#define SYSCTL_INT_BOSC_FAIL 0x00000010 // Boot oscillator failure int +#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int +#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt +#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt +#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_RESC register. +// +//***************************************************************************** +#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset +#define SYSCTL_RESC_SW 0x00000010 // Software reset +#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset +#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset +#define SYSCTL_RESC_POR 0x00000002 // Power on reset +#define SYSCTL_RESC_EXT 0x00000001 // External reset + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_RCC register. +// +//***************************************************************************** +#define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating +#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider +#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2 +#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3 +#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4 +#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5 +#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6 +#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7 +#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8 +#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9 +#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10 +#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11 +#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12 +#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13 +#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14 +#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15 +#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16 +#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider +#define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down +#define SYSCTL_RCC_OE 0x00001000 // PLL output enable +#define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass +#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable +#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc +#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal +#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864MHz crystal +#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4MHz crystal +#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal +#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal +#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal +#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal +#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal +#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal +#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal +#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal +#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal +#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select +#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator +#define SYSCTL_RCC_OSCSRC_BOOT 0x00000010 // Use the boot oscillator +#define SYSCTL_RCC_OSCSRC_BOOT4 0x00000020 // Use the boot oscillator / 4 +#define SYSCTL_RCC_BOSCVER 0x00000008 // Boot osc. verification timer en +#define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en +#define SYSCTL_RCC_BOSCDIS 0x00000002 // Boot oscillator disable +#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable +#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field +#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field +#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_PLLCFG register. +// +//***************************************************************************** +#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider +#define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1 +#define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2 +#define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4 +#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier +#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider +#define SYSCTL_PLLCFG_F_SHIFT 5 +#define SYSCTL_PLLCFG_R_SHIFT 0 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_CLKVCLR register. +// +//***************************************************************************** +#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_LDOARST register. +// +//***************************************************************************** +#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device + +#endif // __HW_SYSCTL_H__ diff --git a/20080212/Demo/CORTEX_LM3S102_GCC/hw_include/hw_types.h b/20080212/Demo/CORTEX_LM3S102_GCC/hw_include/hw_types.h new file mode 100644 index 000000000..a944f6662 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_GCC/hw_include/hw_types.h @@ -0,0 +1,63 @@ +//***************************************************************************** +// +// hw_types.h - Common types and macros. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_TYPES_H__ +#define __HW_TYPES_H__ + +//***************************************************************************** +// +// Define a boolean type, and values for true and false. +// +//***************************************************************************** +typedef unsigned char tBoolean; + +#ifndef true +#define true 1 +#endif + +#ifndef false +#define false 0 +#endif + +//***************************************************************************** +// +// Macros for hardware access, both direct and via the bit-band region. +// +//***************************************************************************** +#define HWREG(x) \ + (*((volatile unsigned long *)(x))) +#define HWREGBITW(x, b) \ + HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITH(x, b) \ + HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITB(x, b) \ + HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) + +#endif // __HW_TYPES_H__ diff --git a/20080212/Demo/CORTEX_LM3S102_GCC/hw_include/hw_uart.h b/20080212/Demo/CORTEX_LM3S102_GCC/hw_include/hw_uart.h new file mode 100644 index 000000000..40b6ab2a6 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_GCC/hw_include/hw_uart.h @@ -0,0 +1,234 @@ +//***************************************************************************** +// +// hw_uart.h - Macros and defines used when accessing the UART hardware +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_UART_H__ +#define __HW_UART_H__ + +//***************************************************************************** +// +// UART Register Offsets. +// +//***************************************************************************** +#define UART_O_DR 0x00000000 // Data Register +#define UART_O_RSR 0x00000004 // Receive Status Register (read) +#define UART_O_ECR 0x00000004 // Error Clear Register (write) +#define UART_O_FR 0x00000018 // Flag Register (read only) +#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg +#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg +#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte +#define UART_O_CTL 0x00000030 // Control Register +#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg +#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg +#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register +#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register +#define UART_O_ICR 0x00000044 // Interrupt Clear Register + +//***************************************************************************** +// +// Data Register bits +// +//***************************************************************************** +#define UART_DR_OE 0x00000800 // Overrun Error +#define UART_DR_BE 0x00000400 // Break Error +#define UART_DR_PE 0x00000200 // Parity Error +#define UART_DR_FE 0x00000100 // Framing Error + +//***************************************************************************** +// +// Receive Status Register bits +// +//***************************************************************************** +#define UART_RSR_OE 0x00000008 // Overrun Error +#define UART_RSR_BE 0x00000004 // Break Error +#define UART_RSR_PE 0x00000002 // Parity Error +#define UART_RSR_FE 0x00000001 // Framing Error + +//***************************************************************************** +// +// Flag Register bits +// +//***************************************************************************** +#define UART_FR_RI 0x100 // Ring Indicator +#define UART_FR_TXFE 0x080 // TX FIFO Empty +#define UART_FR_RXFF 0x040 // RX FIFO Full +#define UART_FR_TXFF 0x020 // TX FIFO Full +#define UART_FR_RXFE 0x010 // RX FIFO Empty +#define UART_FR_BUSY 0x008 // UART Busy + +//***************************************************************************** +// +// Line Control Register High bits +// +//***************************************************************************** +#define UART_LCR_H_SPS 0x80 // Stick Parity Select +#define UART_LCR_H_WLEN 0x60 // Word length +#define UART_LCR_H_WLEN_8 0x60 // 8 bit data +#define UART_LCR_H_WLEN_7 0x40 // 7 bit data +#define UART_LCR_H_WLEN_6 0x20 // 6 bit data +#define UART_LCR_H_WLEN_5 0x00 // 5 bit data +#define UART_LCR_H_FEN 0x10 // Enable FIFO +#define UART_LCR_H_STP2 0x08 // Two Stop Bits Select +#define UART_LCR_H_EPS 0x04 // Even Parity Select +#define UART_LCR_H_PEN 0x02 // Parity Enable +#define UART_LCR_H_BRK 0x01 // Send Break + +//***************************************************************************** +// +// Control Register bits +// +//***************************************************************************** +#define UART_CTL_CTSEN 0x8000 // CTS Hardware Flow Control +#define UART_CTL_RTSEN 0x4000 // RTS Hardware Flow Control +#define UART_CTL_OUT2 0x2000 // OUT2 +#define UART_CTL_OUT1 0x1000 // OUT1 +#define UART_CTL_RTS 0x0800 // Request To Send +#define UART_CTL_DTR 0x0400 // Data Terminal Ready +#define UART_CTL_RXE 0x0200 // Receive Enable +#define UART_CTL_TXE 0x0100 // Transmit Enable +#define UART_CTL_LBE 0x0080 // Loopback Enable +#define UART_CTL_IIRLP 0x0004 // IrDA SIR low power mode +#define UART_CTL_SIREN 0x0002 // SIR Enable +#define UART_CTL_UARTEN 0x0001 // UART Enable + +//***************************************************************************** +// +// Interrupt FIFO Level Select Register bits +// +//***************************************************************************** +#define UART_IFLS_RX1_8 0x00 // 1/8 Full +#define UART_IFLS_RX2_8 0x10 // 1/4 Full +#define UART_IFLS_RX4_8 0x20 // 1/2 Full +#define UART_IFLS_RX6_8 0x30 // 3/4 Full +#define UART_IFLS_RX7_8 0x40 // 7/8 Full +#define UART_IFLS_TX1_8 0x00 // 1/8 Full +#define UART_IFLS_TX2_8 0x01 // 1/4 Full +#define UART_IFLS_TX4_8 0x02 // 1/2 Full +#define UART_IFLS_TX6_8 0x03 // 3/4 Full +#define UART_IFLS_TX7_8 0x04 // 7/8 Full + +//***************************************************************************** +// +// Interrupt Mask Set/Clear Register bits +// +//***************************************************************************** +#define UART_IM_OEIM 0x400 // Overrun Error Interrupt Mask +#define UART_IM_BEIM 0x200 // Break Error Interrupt Mask +#define UART_IM_PEIM 0x100 // Parity Error Interrupt Mask +#define UART_IM_FEIM 0x080 // Framing Error Interrupt Mask +#define UART_IM_RTIM 0x040 // Receive Timeout Interrupt Mask +#define UART_IM_TXIM 0x020 // Transmit Interrupt Mask +#define UART_IM_RXIM 0x010 // Receive Interrupt Mask +#define UART_IM_DSRMIM 0x008 // DSR Interrupt Mask +#define UART_IM_DCDMIM 0x004 // DCD Interrupt Mask +#define UART_IM_CTSMIM 0x002 // CTS Interrupt Mask +#define UART_IM_RIMIM 0x001 // RI Interrupt Mask + +//***************************************************************************** +// +// Raw Interrupt Status Register +// +//***************************************************************************** +#define UART_RIS_OERIS 0x400 // Overrun Error Interrupt Status +#define UART_RIS_BERIS 0x200 // Break Error Interrupt Status +#define UART_RIS_PERIS 0x100 // Parity Error Interrupt Status +#define UART_RIS_FERIS 0x080 // Framing Error Interrupt Status +#define UART_RIS_RTRIS 0x040 // Receive Timeout Interrupt Status +#define UART_RIS_TXRIS 0x020 // Transmit Interrupt Status +#define UART_RIS_RXRIS 0x010 // Receive Interrupt Status +#define UART_RIS_DSRRMIS 0x008 // DSR Interrupt Status +#define UART_RIS_DCDRMIS 0x004 // DCD Interrupt Status +#define UART_RIS_CTSRMIS 0x002 // CTS Interrupt Status +#define UART_RIS_RIRMIS 0x001 // RI Interrupt Status + +//***************************************************************************** +// +// Masked Interrupt Status Register +// +//***************************************************************************** +#define UART_MIS_OEMIS 0x400 // Overrun Error Interrupt Status +#define UART_MIS_BEMIS 0x200 // Break Error Interrupt Status +#define UART_MIS_PEMIS 0x100 // Parity Error Interrupt Status +#define UART_MIS_FEMIS 0x080 // Framing Error Interrupt Status +#define UART_MIS_RTMIS 0x040 // Receive Timeout Interrupt Status +#define UART_MIS_TXMIS 0x020 // Transmit Interrupt Status +#define UART_MIS_RXMIS 0x010 // Receive Interrupt Status +#define UART_MIS_DSRMMIS 0x008 // DSR Interrupt Status +#define UART_MIS_DCDMMIS 0x004 // DCD Interrupt Status +#define UART_MIS_CTSMMIS 0x002 // CTS Interrupt Status +#define UART_MIS_RIMMIS 0x001 // RI Interrupt Status + +//***************************************************************************** +// +// Interrupt Clear Register bits +// +//***************************************************************************** +#define UART_ICR_OEIC 0x200 // Overrun Error Interrupt Clear +#define UART_ICR_BEIC 0x200 // Break Error Interrupt Clear +#define UART_ICR_PEIC 0x200 // Parity Error Interrupt Clear +#define UART_ICR_FEIC 0x200 // Framing Error Interrupt Clear +#define UART_ICR_RTIC 0x200 // Receive Timeout Interrupt Clear +#define UART_ICR_TXIC 0x200 // Transmit Interrupt Clear +#define UART_ICR_RXIC 0x200 // Receive Interrupt Clear +#define UART_ICR_DSRMIC 0x200 // DSR Interrupt Clear +#define UART_ICR_DCDMIC 0x200 // DCD Interrupt Clear +#define UART_ICR_CTSMIC 0x200 // CTS Interrupt Clear +#define UART_ICR_RIMIC 0x200 // RI Interrupt Clear + +//***************************************************************************** +// +// DMA Control Register bits +// +//***************************************************************************** +#define UART_DMACRDMAONERR 0x04 // Disable DMA On Error +#define UART_DMACRTXDMAE 0x02 // Enable Transmit DMA +#define UART_DMACRRXDMAE 0x01 // Enable Receive DMA + +#define UART_RSR_ANY (UART_RSR_OE | \ + UART_RSR_BE | \ + UART_RSR_PE | \ + UART_RSR_FE) + +//***************************************************************************** +// +// Reset Values for UART Registers. +// +//***************************************************************************** +#define UART_RV_DR 0 +#define UART_RV_RSR 0x0 +#define UART_RV_ECR 0 +#define UART_RV_FR 0x90 +#define UART_RV_IBRD 0x0000 +#define UART_RV_FBRD 0x00 +#define UART_RV_LCR_H 0x00 +#define UART_RV_CTL 0x0300 +#define UART_RV_IFLS 0x12 +#define UART_RV_IM 0x000 +#define UART_RV_RIS 0x000 +#define UART_RV_MIS 0x000 +#define UART_RV_ICR 0x000 + +#endif // __HW_UART_H__ diff --git a/20080212/Demo/CORTEX_LM3S102_GCC/hw_include/interrupt.h b/20080212/Demo/CORTEX_LM3S102_GCC/hw_include/interrupt.h new file mode 100644 index 000000000..23424af4e --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_GCC/hw_include/interrupt.h @@ -0,0 +1,57 @@ +//***************************************************************************** +// +// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void IntMasterEnable(void); +extern void IntMasterDisable(void); +extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)); +extern void IntUnregister(unsigned long ulInterrupt); +extern void IntPriorityGroupingSet(unsigned long ulBits); +extern unsigned long IntPriorityGroupingGet(void); +extern void IntPrioritySet(unsigned long ulInterrupt, + unsigned char ucPriority); +extern long IntPriorityGet(unsigned long ulInterrupt); +extern void IntEnable(unsigned long ulInterrupt); +extern void IntDisable(unsigned long ulInterrupt); + +#ifdef __cplusplus +} +#endif + +#endif // __INTERRUPT_H__ diff --git a/20080212/Demo/CORTEX_LM3S102_GCC/hw_include/libdriver.a b/20080212/Demo/CORTEX_LM3S102_GCC/hw_include/libdriver.a new file mode 100644 index 0000000000000000000000000000000000000000..e1c1ec8e76d31120e1eb33f463c2e2ece4d6410f GIT binary patch literal 180452 zcmeIb4|E*Ic_&ys15ywOi;xJ}v?Mz-1np1`O$`2!0Bpq>a!802ND(0@S-X)#41tj_ z5(vP9fo%G0hm^El+w1srUY}2K@_h84_`F_k9^wsmvwqf+YiV=J9fLD*odfSG zu^;WrL3>ofXYaG_`&ISVU0vv!?g4=zG@g1GRMppC*Z*ICUwu_woxUqy8k=}uOJ^$R zy1IIMGQGXM0|Tj4MqbkYr&7IL1AEjRqb)*+{~$#A?LusSj}X6nT!>#G(yr}7bS((c z`-%|#8-;k!9|-ZQ_Y3iB|6PdOKNMo{lR_N&t`LX+R*2ypLX12o#QR5u_=hhE@tZq^ z$UiMaAtl7bVIdyq30vJ3@Tx6GF@r?O*;EA^!D8g!s<4gm~s< zA^siJ(SUCNk7tUR0g!5}(6wbcy3Fp9N;T#geIs9hf z9DSE?j`a)YzG2}!FfN?mxGJ0zZNfSE4dE0hpJKOgCQHJZp)||)3+F?BBb@(Xn{YmU zOgLvLzbC&doKHR|oPR=j{ExlD`P_tX{^u_U=jrE!^Lw`l=YOR#e|4j9zW#OLd~=_0 z{>5Ji=MO2p^S24-kG~_F?^2o35afYN`3=s)~Fh4bSU;r#9Ug!3weUz-xn)pNr6*`EvN^(K)>^oj(vRib%bBsTqA zBsO=8#4Qhr#H}9|iLIX(iQB&=62Cnkw2Q;+vG;AGC)h>zqSbF*|AP%p`F-)v#b z<3>k16 zC{EEmst+ZDjB{)G6t}&6g4q7JPx<*{CKJ4-+pMSsNL)Jg~v=3?hT!0rb%pWk9b@olQjDF zj*pkn*F=?Zt@vKtExn5Sg_m(Z9~tG+x)FEaaN@zTGS9Lkw3135E;!Y+@KAnkvV1T< zH9kpWK~Hb0%;`*(RY!Tv!UUgTxKx~`0drb*)KuAvmZs-sic=3;$g-V$ZbTnGF*7&G zx2qTpyjhgY8-Ntn1{U4%(A2TLNA4&1PnTu|4RQrRgt+zH;JwpR`zEKy9(9YfoQj@t zsT_3shp29KDMTeu2v%Wk7!?b!d4*Qj+?H1ntr8=rXLIGreMd)f_ZLdVhl*qQa&dYJ z4dPxYO@CKWbKrNPf8~;+Oh}wSk7I*=8mRrTnC-H?`l? z!*1RDYhJB`H3?w|)J(h1qe0fkr(4*EONH6O6nBBoevHV=sj@$8C6gC}*%YUY^ba4_ z2LqZ-!fAi*?wkaX8}q}*0#`>F{)3*42xko-%SI zUmlx4Gx#y@8ph06eo_KmUS>k@rT}%>%^u;`=Zch^+kVH6=K@uvxL!rC?V)GvD;4sO z(lbvWlAFkvP+Sfh&*=~{p3Y3x!?SxI%NN~5rTXk8D`O}(ZsTGi>=qG0ugBbo&gS=* zd(rDIH}3Y98`C-ql;J$YBP*Ig3Kwc*CO=kC<$pgqaD4hv5xZJ{N z6s>?vJxmfq=n>pi@F>R$lkSLP9z{XK(^>*#%g`iz=a zX~_}=lc``iUE(b1xXW3o(={SVgR$VvpfJzFGsWo>1ZAA^Uq>Vn5Q`*k2PG9M6=c&QLnTj8g-ULqZE=BsGmzQs>f7) zNP9)1N`xnC)=j3O*OzWAmF8y3C&tx;azafgRY&_5^@?~@Jxh8X?MT$bw+a)}2ME>S*ugSsTG9bHPGa4t>jY?oq`b@ue^Sb6fq$?4g#$FwOdHx*yT zJa&4nte(oo#j(jp^;>;hx;KxZx?WvXev)RSGfvamSt<?Cy%?mK-5j7pKDVoSf80qM7a7 zB&O6Jtht7BljCC{#M0QqVdPm0xinS^N#w(rf9uU68)FO;?`6Z+zhsP_Su&p+5Gd1} zn3OSTtLNk;E!b3&6f)MCzIA5VKM}rDM6LNQ$ z1jwK(^&&tfEKcfVy~2u->gKnjM+)WBTE=4xJOezc_6YE3MoTF==2hHEK80IIQBGk> z7-W*9AQuKRX7@oxriP>uxD=jNkorM2RR32O2P()nTP=PL%dh1D80U$Rp<&u;! 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All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup utilities_api +//! @{ +// +//***************************************************************************** + +#include "hw_memmap.h" +#include "hw_types.h" +#include "gpio.h" +#include "ssi.h" +#include "sysctl.h" +#include "pdc.h" + +//***************************************************************************** +// +//! Initializes the connection to the PDC. +//! +//! This function will enable clocking to the SSI and GPIO A modules, configure +//! the GPIO pins to be used for an SSI interface, and it will configure the +//! SSI as a 1Mb master device, operating in MOTO mode. It will also enable +//! the SSI module, and will enable the chip select for the PDC on the +//! Stellaris development board. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return None. +// +//***************************************************************************** +void +PDCInit(void) +{ + // + // Enable the peripherals used to drive the PDC. + // + SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + + // + // Configure the appropriate pins to be SSI instead of GPIO. + // + GPIODirModeSet(GPIO_PORTA_BASE, SSI_CLK | SSI_TX | SSI_RX, + GPIO_DIR_MODE_HW); + GPIODirModeSet(GPIO_PORTA_BASE, SSI_CS, GPIO_DIR_MODE_OUT); + GPIOPadConfigSet(GPIO_PORTA_BASE, SSI_CLK, GPIO_STRENGTH_4MA, + GPIO_PIN_TYPE_STD_WPU); + + // + // Configure the SSI port. + // + SSIConfig(SSI_BASE, SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 1000000, 8); + SSIEnable(SSI_BASE); + + // + // Reset the PDC SSI state machine. The chip select needs to be held low + // for 100ns; the procedure call overhead more than accounts for this time. + // + GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, 0); + GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, PDC_CS); +} + +//***************************************************************************** +// +//! Write a PDC register. +//! +//! \param ucAddr specifies the PDC register to write. +//! \param ucData specifies the data to write. +//! +//! This function will perform the SSI transfers required to write a register +//! in the PDC on the Stellaris development board. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return None. +// +//***************************************************************************** +void +PDCWrite(unsigned char ucAddr, unsigned char ucData) +{ + unsigned long ulTemp; + + // + // Send address and write command. + // + SSIDataPut(SSI_BASE, (ucAddr & 0x0F) | PDC_WR); + + // + // Write the data. + // + SSIDataPut(SSI_BASE, ucData); + + // + // Flush data read during address write. + // + SSIDataGet(SSI_BASE, &ulTemp); + + // + // Flush data read during data write. + // + SSIDataGet(SSI_BASE, &ulTemp); +} + diff --git a/20080212/Demo/CORTEX_LM3S102_GCC/hw_include/pdc.h b/20080212/Demo/CORTEX_LM3S102_GCC/hw_include/pdc.h new file mode 100644 index 000000000..aba74cd71 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_GCC/hw_include/pdc.h @@ -0,0 +1,124 @@ +//***************************************************************************** +// +// pdc.h - Stellaris development board Peripheral Device Controller definitions +// and prototypes. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __PDC_H__ +#define __PDC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The registers within the peripheral device controller. +// +//***************************************************************************** +#define PDC_VER 0x0 // Version register +#define PDC_CSR 0x1 // Command/Status register +#define PDC_DSW 0x4 // DIP Switch register +#define PDC_LED 0x5 // LED register +#define PDC_LCD_CSR 0x6 // LCD Command/Status register +#define PDC_LCD_RAM 0x7 // LCD RAM register +#define PDC_GPXDAT 0x8 // GPIO X Data register +#define PDC_GPXDIR 0x9 // GPIO X Direction register +#define PDC_GPYDAT 0xA // GPIO Y Data register +#define PDC_GPYDIR 0xB // GPIO Y Direction register +#define PDC_GPZDAT 0xC // GPIO Z Data register +#define PDC_GPZDIR 0xD // GPIO Z Direction register + +//***************************************************************************** +// +// Flags indicating a read or write to the peripheral device controller. +// +//***************************************************************************** +#define PDC_RD 0x80 // PDC read command +#define PDC_WR 0x00 // PDC write command + +//***************************************************************************** +// +// LCD panel (Crystalfontz CFAH1602B) commands, RS = 0 +// +//***************************************************************************** +#define LCD_CLEAR 0x01 // Clear display (0 fill DDRAM). +#define LCD_HOME 0x02 // Cursor home. +#define LCD_MODE 0x04 // Set entry mode (cursor dir) +#define LCD_ON 0x08 // Set display, cursor, blinking + // on/off +#define LCD_CUR 0x10 // Cursor, display shift +#define LCD_IF 0x20 // Set interface data length, + // lines, font +#define LCD_CGADDR 0x40 // Set CGRAM AC address +#define LCD_DDADDR 0x80 // Set DDRAM AC address + +//***************************************************************************** +// +// LCD Status bit +// +//***************************************************************************** +#define LCD_B_BUSY 0x80 // Busy flag. + +//***************************************************************************** +// +// The GPIO port A pin numbers for the various SSI signals. +// +//***************************************************************************** +#define SSI_CS GPIO_PIN_3 +#define PDC_CS GPIO_PIN_3 +#define SSI_CLK GPIO_PIN_2 +#define SSI_TX GPIO_PIN_5 +#define SSI_RX GPIO_PIN_4 + +//***************************************************************************** +// +// Function Prototypes +// +//***************************************************************************** +extern void PDCInit(void); +extern unsigned char PDCRead(unsigned char ucAddr); +extern void PDCWrite(unsigned char ucAddr, unsigned char ucData); +extern unsigned char PDCDIPRead(void); +extern void PDCLEDWrite(unsigned char ucLED); +extern unsigned char PDCLEDRead(void); +extern void PDCLCDInit(void); +extern void PDCLCDBacklightOn(void); +extern void PDCLCDBacklightOff(void); +extern void PDCLCDClear(void); +extern void PDCLCDCreateChar(unsigned char ucChar, unsigned char *pucData); +extern void PDCLCDSetPos(unsigned char ucX, unsigned char ucY); +extern void PDCLCDWrite(const char *pcStr, unsigned long ulCount); +extern unsigned char PDCGPIODirRead(unsigned char ucIdx); +extern void PDCGPIODirWrite(unsigned char ucIdx, unsigned char ucValue); +extern unsigned char PDCGPIORead(unsigned char ucIdx); +extern void PDCGPIOWrite(unsigned char ucIdx, unsigned char ucValue); + +#ifdef __cplusplus +} +#endif + +#endif // __PDC_H__ diff --git a/20080212/Demo/CORTEX_LM3S102_GCC/hw_include/ssi.h b/20080212/Demo/CORTEX_LM3S102_GCC/hw_include/ssi.h new file mode 100644 index 000000000..ef53b348b --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_GCC/hw_include/ssi.h @@ -0,0 +1,88 @@ +//***************************************************************************** +// +// ssi.h - Prototypes for the Synchronous Serial Interface Driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __SSI_H__ +#define __SSI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear +// as the ulIntFlags parameter, and returned by SSIIntStatus. +// +//***************************************************************************** +#define SSI_TXFF 0x00000008 // TX FIFO half empty or less +#define SSI_RXFF 0x00000004 // RX FIFO half full or less +#define SSI_RXTO 0x00000002 // RX timeout +#define SSI_RXOR 0x00000001 // RX overrun + +//***************************************************************************** +// +// Values that can be passed to SSIConfig. +// +//***************************************************************************** +#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0 +#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1 +#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0 +#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1 +#define SSI_FRF_TI 0x00000010 // TI frame format +#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format + +#define SSI_MODE_MASTER 0x00000000 // SSI master +#define SSI_MODE_SLAVE 0x00000001 // SSI slave +#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void SSIConfig(unsigned long ulBase, unsigned long ulProtocol, + unsigned long ulMode, unsigned long ulBitRate, + unsigned long ulDataWidth); +extern void SSIDataGet(unsigned long ulBase, unsigned long *ulData); +extern long SSIDataNonBlockingGet(unsigned long ulBase, unsigned long *ulData); +extern void SSIDataPut(unsigned long ulBase, unsigned long ulData); +extern long SSIDataNonBlockingPut(unsigned long ulBase, unsigned long ulData); +extern void SSIDisable(unsigned long ulBase); +extern void SSIEnable(unsigned long ulBase); +extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void SSIIntUnregister(unsigned long ulBase); + +#ifdef __cplusplus +} +#endif + +#endif // __SSI_H__ diff --git a/20080212/Demo/CORTEX_LM3S102_GCC/hw_include/sysctl.h b/20080212/Demo/CORTEX_LM3S102_GCC/hw_include/sysctl.h new file mode 100644 index 000000000..2e1d1e48c --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_GCC/hw_include/sysctl.h @@ -0,0 +1,221 @@ +//***************************************************************************** +// +// sysctl.h - Prototypes for the system control driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __SYSCTL_H__ +#define __SYSCTL_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed to the +// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(), +// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the +// ulPeripheral parameter. The peripherals in the fourth group (upper nibble +// is 3) can only be used with the SysCtlPeripheralPresent() API. +// +//***************************************************************************** +#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog +#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0 +#define SYSCTL_PERIPH_SSI 0x10000010 // SSI +#define SYSCTL_PERIPH_I2C 0x10001000 // I2C +#define SYSCTL_PERIPH_TIMER0 0x10010000 // Timer 0 +#define SYSCTL_PERIPH_TIMER1 0x10020000 // Timer 1 +#define SYSCTL_PERIPH_COMP0 0x11000000 // Analog comparator 0 +#define SYSCTL_PERIPH_COMP1 0x12000000 // Analog comparator 1 +#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A +#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B +#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C +#define SYSCTL_PERIPH_PLL 0x30000010 // PLL + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlPinPresent() API +// as the ulPin parameter. +// +//***************************************************************************** +#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin +#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin +#define SYSCTL_PIN_C0O 0x00000100 // C0o pin +#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin +#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin +#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin +#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlLDOSet() API as +// the ulVoltage value, or returned by the SysCtlLDOGet() API. +// +//***************************************************************************** +#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V +#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V +#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V +#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V +#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V +#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V +#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V +#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V +#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V +#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V +#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlLDOConfigSet() API. +// +//***************************************************************************** +#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset +#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlIntEnable(), +// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask +// by the SysCtlIntStatus() API. +// +//***************************************************************************** +#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt +#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt +#define SYSCTL_INT_BOSC_FAIL 0x00000010 // Boot oscillator failure int +#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int +#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt +#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt +#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlResetCauseClear() +// API or returned by the SysCtlResetCauseGet() API. +// +//***************************************************************************** +#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset +#define SYSCTL_CAUSE_SW 0x00000010 // Software reset +#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset +#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset +#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset +#define SYSCTL_CAUSE_EXT 0x00000001 // External reset + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlBrownOutConfigSet() +// API as the ulConfig parameter. +// +//***************************************************************************** +#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting +#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlClockSet() API as +// the ulConfig parameter. +// +//***************************************************************************** +#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1 +#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2 +#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3 +#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4 +#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5 +#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6 +#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7 +#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8 +#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9 +#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10 +#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11 +#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12 +#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13 +#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14 +#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15 +#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16 +#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock +#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock +#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz +#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz +#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz +#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz +#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz +#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz +#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz +#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz +#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz +#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz +#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz +#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz +#define SYSCTL_OSC_MAIN 0x00000000 // Oscillator source is main osc +#define SYSCTL_OSC_BOOT 0x00000010 // Oscillator source is boot osc +#define SYSCTL_OSC_BOOT4 0x00000020 // Oscillator source is boot osc /4 +#define SYSCTL_BOOT_OSC_DIS 0x00000002 // Disable boot oscillator +#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern unsigned long SysCtlSRAMSizeGet(void); +extern unsigned long SysCtlFlashSizeGet(void); +extern tBoolean SysCtlPinPresent(unsigned long ulPin); +extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral); +extern void SysCtlPeripheralReset(unsigned long ulPeripheral); +extern void SysCtlPeripheralEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralClockGating(tBoolean bEnable); +extern void SysCtlIntRegister(void (*pfnHandler)(void)); +extern void SysCtlIntUnregister(void); +extern void SysCtlIntEnable(unsigned long ulInts); +extern void SysCtlIntDisable(unsigned long ulInts); +extern void SysCtlIntClear(unsigned long ulInts); +extern unsigned long SysCtlIntStatus(tBoolean bMasked); +extern void SysCtlLDOSet(unsigned long ulVoltage); +extern unsigned long SysCtlLDOGet(void); +extern void SysCtlLDOConfigSet(unsigned long ulConfig); +extern void SysCtlReset(void); +extern void SysCtlSleep(void); +extern void SysCtlDeepSleep(void); +extern unsigned long SysCtlResetCauseGet(void); +extern void SysCtlResetCauseClear(unsigned long ulCauses); +extern void SysCtlBrownOutConfigSet(unsigned long ulConfig, + unsigned long ulDelay); +extern void SysCtlClockSet(unsigned long ulConfig); +extern unsigned long SysCtlClockGet(void); +extern void SysCtlBOSCVerificationSet(tBoolean bEnable); +extern void SysCtlMOSCVerificationSet(tBoolean bEnable); +extern void SysCtlPLLVerificationSet(tBoolean bEnable); +extern void SysCtlClkVerificationClear(void); + +#ifdef __cplusplus +} +#endif + +#endif // __SYSCTL_H__ diff --git a/20080212/Demo/CORTEX_LM3S102_GCC/hw_include/uart.h b/20080212/Demo/CORTEX_LM3S102_GCC/hw_include/uart.h new file mode 100644 index 000000000..ea39859d2 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_GCC/hw_include/uart.h @@ -0,0 +1,102 @@ +//***************************************************************************** +// +// uart.h - Defines and Macros for the UART. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __UART_H__ +#define __UART_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear +// as the ulIntFlags parameter, and returned from UARTIntStatus. +// +//***************************************************************************** +#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask +#define UART_INT_BE 0x200 // Break Error Interrupt Mask +#define UART_INT_PE 0x100 // Parity Error Interrupt Mask +#define UART_INT_FE 0x080 // Framing Error Interrupt Mask +#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask +#define UART_INT_TX 0x020 // Transmit Interrupt Mask +#define UART_INT_RX 0x010 // Receive Interrupt Mask + +//***************************************************************************** +// +// Values that can be passed to UARTConfigSet as the ulConfig parameter and +// returned by UARTConfigGet in the pulConfig parameter. Additionally, the +// UART_CONFIG_PAR_* subset can be passed to UARTParityModeSet as the ulParity +// parameter, and are returned by UARTParityModeGet. +// +//***************************************************************************** +#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data +#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data +#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data +#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data +#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit +#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits +#define UART_CONFIG_PAR_NONE 0x00000000 // No parity +#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity +#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity +#define UART_CONFIG_PAR_ONE 0x00000086 // Parity bit is one +#define UART_CONFIG_PAR_ZERO 0x00000082 // Parity bit is zero + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity); +extern unsigned long UARTParityModeGet(unsigned long ulBase); +extern void UARTConfigSet(unsigned long ulBase, unsigned long ulBaud, + unsigned long ulConfig); +extern void UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud, + unsigned long *pulConfig); +extern void UARTEnable(unsigned long ulBase); +extern void UARTDisable(unsigned long ulBase); +extern tBoolean UARTCharsAvail(unsigned long ulBase); +extern tBoolean UARTSpaceAvail(unsigned long ulBase); +extern long UARTCharNonBlockingGet(unsigned long ulBase); +extern long UARTCharGet(unsigned long ulBase); +extern tBoolean UARTCharNonBlockingPut(unsigned long ulBase, + unsigned char ucData); +extern void UARTCharPut(unsigned long ulBase, unsigned char ucData); +extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState); +extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern void UARTIntUnregister(unsigned long ulBase); +extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags); + +#ifdef __cplusplus +} +#endif + +#endif // __UART_H__ diff --git a/20080212/Demo/CORTEX_LM3S102_GCC/init/startup.c b/20080212/Demo/CORTEX_LM3S102_GCC/init/startup.c new file mode 100644 index 000000000..795896019 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_GCC/init/startup.c @@ -0,0 +1,174 @@ +//***************************************************************************** +// +// startup.c - Boot code for Stellaris. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +//***************************************************************************** + +//***************************************************************************** +// +// Forward declaration of the default fault handlers. +// +//***************************************************************************** +void ResetISR(void); +static void NmiSR(void); +void FaultISR(void); +extern void xPortPendSVHandler(void); +extern void xPortSysTickHandler(void); +extern void vUART_ISR( void ); + +//***************************************************************************** +// +// The entry point for the application. +// +//***************************************************************************** +extern void entry(void); + +//***************************************************************************** +// +// Reserve space for the system stack. +// +//***************************************************************************** +#ifndef STACK_SIZE +#define STACK_SIZE 51 +#endif +static unsigned long pulMainStack[STACK_SIZE]; + +//***************************************************************************** +// +// The minimal vector table for a Cortex M3. Note that the proper constructs +// must be placed on this to ensure that it ends up at physical address +// 0x0000.0000. +// +//***************************************************************************** +__attribute__ ((section("vectors"))) +void (* const g_pfnVectors[])(void) = +{ + (void (*)(void))((unsigned long)pulMainStack + sizeof(pulMainStack)), + ResetISR, + NmiSR, + FaultISR, //FAULT + 0, // The MPU fault handler + 0, // The bus fault handler + 0, // The usage fault handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // SVCall handler + 0, // Debug monitor handler + 0, // Reserved + xPortPendSVHandler, // The PendSV handler + xPortSysTickHandler, // The SysTick handler + 0, // GPIO Port A + 0, // GPIO Port B + 0, // GPIO Port C + 0, // GPIO Port D + 0, // GPIO Port E + vUART_ISR // UART0 Rx and Tx +}; + +//***************************************************************************** +// +// The following are constructs created by the linker, indicating where the +// the "data" and "bss" segments reside in memory. The initializers for the +// for the "data" segment resides immediately following the "text" segment. +// +//***************************************************************************** +extern unsigned long _etext; +extern unsigned long _data; +extern unsigned long _edata; +extern unsigned long _bss; +extern unsigned long _ebss; + +//***************************************************************************** +// +// This is the code that gets called when the processor first starts execution +// following a reset event. Only the absolutely necessary set is performed, +// after which the application supplied entry() routine is called. Any fancy +// actions (such as making decisions based on the reset cause register, and +// resetting the bits in that register) are left solely in the hands of the +// application. +// +//***************************************************************************** +void +ResetISR(void) +{ + unsigned long *pulSrc, *pulDest; + + // + // Copy the data segment initializers from flash to SRAM. + // + pulSrc = &_etext; + for(pulDest = &_data; pulDest < &_edata; ) + { + *pulDest++ = *pulSrc++; + } + + // + // Zero fill the bss segment. + // + for(pulDest = &_bss; pulDest < &_ebss; ) + { + *pulDest++ = 0; + } + + // + // Call the application's entry point. + // + Main(); +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a NMI. This +// simply enters an infinite loop, preserving the system state for examination +// by a debugger. +// +//***************************************************************************** +static void +NmiSR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a fault +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +void +FaultISR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} diff --git a/20080212/Demo/CORTEX_LM3S102_GCC/main.c b/20080212/Demo/CORTEX_LM3S102_GCC/main.c new file mode 100644 index 000000000..ad5cc2fa7 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_GCC/main.c @@ -0,0 +1,614 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + * This demo application creates six co-routines and two tasks (three including + * the idle task). The co-routines execute as part of the idle task hook. + * + * Five of the created co-routines are the standard 'co-routine flash' + * co-routines contained within the Demo/Common/Minimal/crflash.c file and + * documented on the FreeRTOS.org WEB site. + * + * The 'LCD Task' rotates a string on the LCD, delaying between each character + * as necessitated by the slow interface, and delaying between each string just + * long enough to enable the text to be read. + * + * The sixth co-routine and final task control the transmission and reception + * of a string to UART 0. The co-routine periodically sends the first + * character of the string to the UART, with the UART's TxEnd interrupt being + * used to transmit the remaining characters. The UART's RxEnd interrupt + * receives the characters and places them on a queue to be processed by the + * 'COMs Rx' task. An error is latched should an unexpected character be + * received, or any character be received out of sequence. + * + * A loopback connector is required to ensure that each character transmitted + * on the UART is also received on the same UART. For test purposes the UART + * FIFO's are not utalised in order to maximise the interrupt overhead. Also + * a pseudo random interval is used between the start of each transmission in + * order that the resultant interrupts are more randomly distributed and + * therefore more likely to highlight any problems. + * + * The flash co-routines control LED's zero to four. LED five is toggled each + * time the string is transmitted on the UART. LED six is toggled each time + * the string is CORRECTLY received on the UART. LED seven is latched on should + * an error be detected in any task or co-routine. + * + * In addition the idle task makes repetative calls to + * prvSetAndCheckRegisters(). This simply loads the general purpose registers + * with a known value, then checks each register to ensure the held value is + * still correct. As a low priority task this checking routine is likely to + * get repeatedly swapped in and out. A register being found to contain an + * incorrect value is therefore indicative of an error in the task switching + * mechansim. + * + */ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "croutine.h" + +/* Demo application include files. */ +#include "partest.h" +#include "crflash.h" + +/* Library include files. */ +#include "DriverLib.h" + +/* The time to delay between writing each character to the LCD. */ +#define mainCHAR_WRITE_DELAY ( 2 / portTICK_RATE_MS ) + +/* The time to delay between writing each string to the LCD. */ +#define mainSTRING_WRITE_DELAY ( 400 / portTICK_RATE_MS ) + +/* The number of flash co-routines to create. */ +#define mainNUM_FLASH_CO_ROUTINES ( 5 ) + +/* The length of the queue used to pass received characters to the Comms Rx +task. */ +#define mainRX_QUEUE_LEN ( 5 ) + +/* The priority of the co-routine used to initiate the transmission of the +string on UART 0. */ +#define mainTX_CO_ROUTINE_PRIORITY ( 1 ) + +/* Only one co-routine is created so its index is not important. */ +#define mainTX_CO_ROUTINE_INDEX ( 0 ) + +/* The time between transmissions of the string on UART 0. This is pseudo +random in order to generate a bit or randomness to when the interrupts occur.*/ +#define mainMIN_TX_DELAY ( 40 / portTICK_RATE_MS ) +#define mainMAX_TX_DELAY ( ( portTickType ) 0x7f ) +#define mainOFFSET_TIME ( ( portTickType ) 3 ) + +/* The time the Comms Rx task should wait to receive a character. This should +be slightly longer than the time between transmissions. If we do not receive +a character after this time then there must be an error in the transmission or +the timing of the transmission. */ +#define mainCOMMS_RX_DELAY ( mainMAX_TX_DELAY + 20 ) + +/* The task priorites. */ +#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainCOMMS_RX_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The LED's toggled by the various tasks. */ +#define mainCOMMS_FAIL_LED ( 7 ) +#define mainCOMMS_RX_LED ( 6 ) +#define mainCOMMS_TX_LED ( 5 ) + +/* The baud rate used by the UART comms tasks/co-routine. */ +#define mainBAUD_RATE ( 57600 ) + +/* FIFO setting for the UART. The FIFO is not used to create a better test. */ +#define mainFIFO_SET ( 0x10 ) + +/* The string that is transmitted on the UART contains sequentially the +characters from mainFIRST_TX_CHAR to mainLAST_TX_CHAR. */ +#define mainFIRST_TX_CHAR '0' +#define mainLAST_TX_CHAR 'z' + +/* Just used to walk through the program memory in order that some random data +can be generated. */ +#define mainTOTAL_PROGRAM_MEMORY ( ( unsigned portLONG * ) ( 8 * 1024 ) ) +#define mainFIRST_PROGRAM_BYTES ( ( unsigned portLONG * ) 4 ) + +/* The error routine that is called if the driver library encounters an error. */ +#ifdef DEBUG +void +__error__(char *pcFilename, unsigned long ulLine) +{ +} +#endif + +/*-----------------------------------------------------------*/ + +/* + * The task that rotates text on the LCD. + */ +static void vLCDTask( void * pvParameters ); + +/* + * The task that receives the characters from UART 0. + */ +static void vCommsRxTask( void * pvParameters ); + +/* + * The co-routine that periodically initiates the transmission of the string on + * the UART. + */ +static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + +/* + * Writes a string the the LCD. + */ +static void prvWriteString( const portCHAR *pcString ); + +/* + * Initialisation routine for the UART. + */ +static void vSerialInit( void ); + +/* + * Thread safe write to the PDC. + */ +static void prvPDCWrite( portCHAR cAddress, portCHAR cData ); + +/* + * Function to simply set a known value into the general purpose registers + * then read them back to ensure they remain set correctly. An incorrect value + * being indicative of an error in the task switching mechanism. + */ +void prvSetAndCheckRegisters( void ); + +/* + * Latch the LED that indicates that an error has occurred. + */ +void vSetErrorLED( void ); + +/* + * Sets up the PLL and ports used by the demo. + */ +static void prvSetupHardware( void ); + +/*-----------------------------------------------------------*/ + +/* Error flag set to pdFAIL if an error is encountered in the tasks/co-routines +defined within this file. */ +unsigned portBASE_TYPE uxErrorStatus = pdPASS; + +/* The next character to transmit. */ +static portCHAR cNextChar; + +/* The queue used to transmit characters from the interrupt to the Comms Rx +task. */ +static xQueueHandle xCommsQueue; + +/*-----------------------------------------------------------*/ + +void Main( void ) +{ + /* Create the queue used to communicate between the UART ISR and the Comms + Rx task. */ + xCommsQueue = xQueueCreate( mainRX_QUEUE_LEN, sizeof( portCHAR ) ); + + /* Setup the ports used by the demo and the clock. */ + prvSetupHardware(); + + /* Create the co-routines that flash the LED's. */ + vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES ); + + /* Create the co-routine that initiates the transmission of characters + on the UART. */ + xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX ); + + /* Create the LCD and Comms Rx tasks. */ + xTaskCreate( vLCDTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL ); + xTaskCreate( vCommsRxTask, "CMS", configMINIMAL_STACK_SIZE, NULL, mainCOMMS_RX_TASK_PRIORITY, NULL ); + + /* Start the scheduler running the tasks and co-routines just created. */ + vTaskStartScheduler(); + + /* Should not get here unless we did not have enough memory to start the + scheduler. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Setup the PLL. */ + SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); + + /* Initialise the hardware used to talk to the LCD, LED's and UART. */ + PDCInit(); + vParTestInitialise(); + vSerialInit(); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ + /* The co-routines are executed in the idle task using the idle task + hook. */ + for( ;; ) + { + /* Schedule the co-routines. */ + vCoRoutineSchedule(); + + /* Run the register check function between each co-routine. */ + prvSetAndCheckRegisters(); + } +} +/*-----------------------------------------------------------*/ + +static void prvWriteString( const portCHAR *pcString ) +{ + /* Write pcString to the LED, pausing between each character. */ + prvPDCWrite(PDC_LCD_CSR, LCD_CLEAR); + while( *pcString ) + { + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_RAM, *pcString ); + pcString++; + } +} +/*-----------------------------------------------------------*/ + +void vLCDTask( void * pvParameters ) +{ +unsigned portBASE_TYPE uxIndex; +const unsigned portCHAR ucCFGData[] = { + 0x30, /* Set data bus to 8-bits. */ + 0x30, + 0x30, + 0x3C, /* Number of lines/font. */ + 0x08, /* Display off. */ + 0x01, /* Display clear. */ + 0x06, /* Entry mode [cursor dir][shift]. */ + 0x0C /* Display on [display on][curson on][blinking on]. */ + }; + +/* The strings that are written to the LCD. */ +const portCHAR *pcStringsToDisplay[] = { + "Stellaris", + "Demo", + "One", + "www.FreeRTOS.org", + "" + }; + + /* Configure the LCD. */ + uxIndex = 0; + while( uxIndex < sizeof( ucCFGData ) ) + { + prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] ); + uxIndex++; + vTaskDelay( mainCHAR_WRITE_DELAY ); + } + + /* Turn the LCD Backlight on. */ + prvPDCWrite( PDC_CSR, 0x01 ); + + /* Clear display. */ + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR ); + + uxIndex = 0; + for( ;; ) + { + /* Display the string on the LCD. */ + prvWriteString( pcStringsToDisplay[ uxIndex ] ); + + /* Move on to the next string - wrapping if necessary. */ + uxIndex++; + if( *( pcStringsToDisplay[ uxIndex ] ) == 0x00 ) + { + uxIndex = 0; + /* Longer pause on the last string to be sent. */ + vTaskDelay( mainSTRING_WRITE_DELAY * 2 ); + } + + /* Wait until it is time to move onto the next string. */ + vTaskDelay( mainSTRING_WRITE_DELAY ); + } +} +/*-----------------------------------------------------------*/ + +static void vCommsRxTask( void * pvParameters ) +{ +static portCHAR cRxedChar, cExpectedChar; + + /* Set the char we expect to receive to the start of the string. */ + cExpectedChar = mainFIRST_TX_CHAR; + + for( ;; ) + { + /* Wait for a character to be received. */ + xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY ); + + /* Was the character recived (if any) the expected character. */ + if( cRxedChar != cExpectedChar ) + { + /* Got an unexpected character. This can sometimes occur when + reseting the system using the debugger leaving characters already + in the UART regsters. */ + uxErrorStatus = pdFAIL; + + /* Resync by waiting for the end of the current string. */ + while( cRxedChar != mainLAST_TX_CHAR ) + { + while( !xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, portMAX_DELAY ) ); + } + + /* The next expected character is the start of the string again. */ + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + if( cExpectedChar == mainLAST_TX_CHAR ) + { + /* We have reached the end of the string - we now expect to + receive the first character in the string again. The LED is + toggled to indicate that the entire string was received without + error. */ + vParTestToggleLED( mainCOMMS_RX_LED ); + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + /* We got the expected character, we now expect to receive the + next character in the string. */ + cExpectedChar++; + } + } + } +} +/*-----------------------------------------------------------*/ + +static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +portTickType xDelayPeriod; +static unsigned portLONG *pulRandomBytes = mainFIRST_PROGRAM_BYTES; + + /* Co-routine MUST start with a call to crSTART. */ + crSTART( xHandle ); + + for(;;) + { + /* Was the previously transmitted string received correctly? */ + if( uxErrorStatus != pdPASS ) + { + /* An error was encountered so set the error LED. */ + vSetErrorLED(); + } + + /* The next character to Tx is the first in the string. */ + cNextChar = mainFIRST_TX_CHAR; + + UARTIntDisable( UART0_BASE, UART_INT_TX ); + { + /* Send the first character. */ + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + + /* Move the variable to the char to Tx on so the ISR transmits + the next character in the string once this one has completed. */ + cNextChar++; + } + UARTIntEnable(UART0_BASE, UART_INT_TX); + + /* Toggle the LED to show a new string is being transmitted. */ + vParTestToggleLED( mainCOMMS_TX_LED ); + + /* Delay before we start the string off again. A pseudo-random delay + is used as this will provide a better test. */ + xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes ); + + pulRandomBytes++; + if( pulRandomBytes > mainTOTAL_PROGRAM_MEMORY ) + { + pulRandomBytes = mainFIRST_PROGRAM_BYTES; + } + + /* Make sure we don't wait too long... */ + xDelayPeriod &= mainMAX_TX_DELAY; + + /* ...but we do want to wait. */ + if( xDelayPeriod < mainMIN_TX_DELAY ) + { + xDelayPeriod = mainMIN_TX_DELAY; + } + + /* Block for the random(ish) time. */ + crDELAY( xHandle, xDelayPeriod ); + } + + /* Co-routine MUST end with a call to crEND. */ + crEND(); +} +/*-----------------------------------------------------------*/ + +static void vSerialInit( void ) +{ + /* Enable the UART. GPIOA has already been initialised. */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + + /* Set GPIO A0 and A1 as peripheral function. They are used to output the + UART signals. */ + GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); + + /* Configure the UART for 8-N-1 operation. */ + UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); + + /* We dont want to use the fifo. This is for test purposes to generate + as many interrupts as possible. */ + HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET; + + /* Enable both Rx and Tx interrupts. */ + HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX ); + IntEnable( INT_UART0 ); +} +/*-----------------------------------------------------------*/ + +void vUART_ISR(void) +{ +unsigned portLONG ulStatus; +portCHAR cRxedChar; +portBASE_TYPE xTaskWokenByPost = pdFALSE; + + /* What caused the interrupt. */ + ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); + + /* Clear the interrupt. */ + UARTIntClear( UART0_BASE, ulStatus ); + + /* Was an Rx interrpt pending? */ + if( ulStatus & UART_INT_RX ) + { + if( ( HWREG(UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) ) + { + /* Get the char from the buffer and post it onto the queue of + Rxed chars. Posting the character should wake the task that is + blocked on the queue waiting for characters. */ + cRxedChar = ( portCHAR ) HWREG( UART0_BASE + UART_O_DR ); + xTaskWokenByPost = xQueueSendFromISR( xCommsQueue, &cRxedChar, xTaskWokenByPost ); + } + } + + /* Was a Tx interrupt pending? */ + if( ulStatus & UART_INT_TX ) + { + /* Send the next character in the string. We are not using the FIFO. */ + if( cNextChar <= mainLAST_TX_CHAR ) + { + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + cNextChar++; + } + } + + if( xTaskWokenByPost ) + { + /* If a task was woken by the character being received then we force + a context switch to occur in case the task is of higher priority than + the currently executing task (i.e. the task that this interrupt + interrupted.) */ + portEND_SWITCHING_ISR( xTaskWokenByPost ); + } +} +/*-----------------------------------------------------------*/ + +static void prvPDCWrite( portCHAR cAddress, portCHAR cData ) +{ + vTaskSuspendAll(); + { + PDCWrite( cAddress, cData ); + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vSetErrorLED( void ) +{ + vParTestSetLED( mainCOMMS_FAIL_LED, pdTRUE ); +} +/*-----------------------------------------------------------*/ + +void prvSetAndCheckRegisters( void ) +{ + /* Fill the general purpose registers with known values. */ + __asm volatile( " mov r11, #10\n" + " add r0, r11, #1\n" + " add r1, r11, #2\n" + " add r2, r11, #3\n" + " add r3, r11, #4\n" + " add r4, r11, #5\n" + " add r5, r11, #6\n" + " add r6, r11, #7\n" + " add r7, r11, #8\n" + " add r8, r11, #9\n" + " add r9, r11, #10\n" + " add r10, r11, #11\n" + " add r12, r11, #12" ); + + /* Check the values are as expected. */ + __asm volatile( " cmp r11, #10\n" + " bne set_error_led\n" + " cmp r0, #11\n" + " bne set_error_led\n" + " cmp r1, #12\n" + " bne set_error_led\n" + " cmp r2, #13\n" + " bne set_error_led\n" + " cmp r3, #14\n" + " bne set_error_led\n" + " cmp r4, #15\n" + " bne set_error_led\n" + " cmp r5, #16\n" + " bne set_error_led\n" + " cmp r6, #17\n" + " bne set_error_led\n" + " cmp r7, #18\n" + " bne set_error_led\n" + " cmp r8, #19\n" + " bne set_error_led\n" + " cmp r9, #20\n" + " bne set_error_led\n" + " cmp r10, #21\n" + " bne set_error_led\n" + " cmp r12, #22\n" + " bne set_error_led\n" + " bx lr" ); + + __asm volatile( "set_error_led:\n" + " push {r14}\n" + " ldr r1, =vSetErrorLED\n" + " blx r1\n" + " pop {r14}\n" + " bx lr" ); +} +/*-----------------------------------------------------------*/ diff --git a/20080212/Demo/CORTEX_LM3S102_GCC/makedefs b/20080212/Demo/CORTEX_LM3S102_GCC/makedefs new file mode 100644 index 000000000..8f7a62be5 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_GCC/makedefs @@ -0,0 +1,193 @@ +#****************************************************************************** +# +# makedefs - Definitions common to all makefiles. +# +# Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +# +# Software License Agreement +# +# Luminary Micro, Inc. (LMI) is supplying this software for use solely and +# exclusively on LMI's Stellaris Family of microcontroller products. +# +# The software is owned by LMI and/or its suppliers, and is protected under +# applicable copyright laws. All rights are reserved. Any use in violation +# of the foregoing restrictions may subject the user to criminal sanctions +# under applicable laws, as well as to civil liability for the breach of the +# terms and conditions of this license. +# +# THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +# OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +# LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +# CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +# +#****************************************************************************** + +#****************************************************************************** +# +# The compiler to be used. +# +#****************************************************************************** +ifndef COMPILER +COMPILER=gcc +endif + +#****************************************************************************** +# +# The debugger to be used. +# +#****************************************************************************** +ifndef DEBUGGER +DEBUGGER=gdb +endif + +#****************************************************************************** +# +# Definitions for using GCC. +# +#****************************************************************************** +ifeq (${COMPILER}, gcc) + +# +# The command for calling the compiler. +# +CC=arm-stellaris-eabi-gcc + +# +# The flags passed to the assembler. +# +AFLAGS=-mthumb \ + -mcpu=cortex-m3 \ + -MD + +# +# The flags passed to the compiler. +# +CFLAGS=-mthumb \ + -mcpu=cortex-m3 \ + -O2 \ + -MD + +# +# The command for calling the library archiver. +# +AR=arm-stellaris-eabi-ar + +# +# The command for calling the linker. +# +LD=arm-stellaris-eabi-ld + +# +# The flags passed to the linker. +# +LDFLAGS= -Map gcc/out.map + +# +# Get the location of libgcc.a from the GCC front-end. +# +LIBGCC=${shell ${CC} -mthumb -march=armv6t2 -print-libgcc-file-name} + +# +# Get the location of libc.a from the GCC front-end. +# +LIBC=${shell ${CC} -mthumb -march=armv6t2 -print-file-name=libc.a} + +# +# The command for extracting images from the linked executables. +# +OBJCOPY=arm-stellaris-eabi-objcopy + +endif + +#****************************************************************************** +# +# Tell the compiler to include debugging information if the DEBUG environment +# variable is set. +# +#****************************************************************************** +ifdef DEBUG +CFLAGS += -g +endif + +#****************************************************************************** +# +# The rule for building the object file from each C source file. +# +#****************************************************************************** +${COMPILER}/%.o: %.c + @if [ 'x${VERBOSE}' = x ]; \ + then \ + echo " CC ${<}"; \ + else \ + echo ${CC} ${CFLAGS} -D${COMPILER} -o ${@} -c ${<}; \ + fi + @${CC} ${CFLAGS} -D${COMPILER} -o ${@} -c ${<} +ifeq (${COMPILER}, rvds) + @mv -f ${notdir ${@:.o=.d}} ${COMPILER} +endif + +#****************************************************************************** +# +# The rule for building the object file from each assembly source file. +# +#****************************************************************************** +${COMPILER}/%.o: %.S + @if [ 'x${VERBOSE}' = x ]; \ + then \ + echo " CC ${<}"; \ + else \ + echo ${CC} ${AFLAGS} -D${COMPILER} -o ${@} -c ${<}; \ + fi +ifeq (${COMPILER}, rvds) + @${CC} ${AFLAGS} -D${COMPILER} -E ${<} > ${@:.o=_.S} + @${CC} ${AFLAGS} -o ${@} -c ${@:.o=_.S} + @rm ${@:.o=_.S} + @${CC} ${AFLAGS} -D${COMPILER} --md -E ${<} + @sed 's,,${@},g' ${notdir ${<:.S=.d}} > ${@:.o=.d} + @rm ${notdir ${<:.S=.d}} +endif +ifeq (${COMPILER}, gcc) + @${CC} ${AFLAGS} -D${COMPILER} -o ${@} -c ${<} +endif + +#****************************************************************************** +# +# The rule for creating an object library. +# +#****************************************************************************** +${COMPILER}/%.a: + @if [ 'x${VERBOSE}' = x ]; \ + then \ + echo " AR ${@}"; \ + else \ + echo ${AR} -cr ${@} ${^}; \ + fi + @${AR} -cr ${@} ${^} + +#****************************************************************************** +# +# The rule for linking the application. +# +#****************************************************************************** +${COMPILER}/%.axf: + @if [ 'x${VERBOSE}' = x ]; \ + then \ + echo " LD ${@}"; \ + fi +ifeq (${COMPILER}, gcc) + @if [ 'x${VERBOSE}' != x ]; \ + then \ + echo ${LD} -T ${SCATTER_${notdir ${@:.axf=}}} \ + --entry ${ENTRY_${notdir ${@:.axf=}}} \ + ${LDFLAGSgcc_${notdir ${@:.axf=}}} \ + ${LDFLAGS} -o ${@} ${^} \ + '${LIBC}' '${LIBGCC}'; \ + fi + @${LD} -T ${SCATTER_${notdir ${@:.axf=}}} \ + --entry ${ENTRY_${notdir ${@:.axf=}}} \ + ${LDFLAGSgcc_${notdir ${@:.axf=}}} \ + ${LDFLAGS} -o ${@} ${^} \ + '${LIBC}' '${LIBGCC}' + @${OBJCOPY} -O binary ${@} ${@:.axf=.bin} +endif diff --git a/20080212/Demo/CORTEX_LM3S102_GCC/standalone.ld b/20080212/Demo/CORTEX_LM3S102_GCC/standalone.ld new file mode 100644 index 000000000..1f1d7baab --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_GCC/standalone.ld @@ -0,0 +1,58 @@ +/****************************************************************************** + * + * standalone.ld - Linker script for applications using startup.c and + * DriverLib. + * + * Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. + * + * Software License Agreement + * + * Luminary Micro, Inc. (LMI) is supplying this software for use solely and + * exclusively on LMI's Stellaris Family of microcontroller products. + * + * The software is owned by LMI and/or its suppliers, and is protected under + * applicable copyright laws. All rights are reserved. Any use in violation + * of the foregoing restrictions may subject the user to criminal sanctions + * under applicable laws, as well as to civil liability for the breach of the + * terms and conditions of this license. + * + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + *****************************************************************************/ + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 8K + SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 2K +} + +SECTIONS +{ + .text : + { + *(vectors) + *(.text) + *(.rodata*) + *(.constdata*) + _etext = .; + } > FLASH + + .data : AT (ADDR(.text) + SIZEOF(.text)) + { + _data = .; + *(vtable) + *(.data) + _edata = .; + } > SRAM + + .bss : + { + _bss = .; + *(.bss) + _ebss = .; + } > SRAM +} diff --git a/20080212/Demo/CORTEX_LM3S102_KEIL/Demo1/FreeRTOSConfig.h b/20080212/Demo/CORTEX_LM3S102_KEIL/Demo1/FreeRTOSConfig.h new file mode 100644 index 000000000..e403b289e --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_KEIL/Demo1/FreeRTOSConfig.h @@ -0,0 +1,86 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 59 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1468 ) ) +#define configMAX_TASK_NAME_LEN ( 3 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_CO_ROUTINES 1 + +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 0 +#define INCLUDE_vTaskDelayUntil 0 +#define INCLUDE_vTaskDelay 1 + + + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/CORTEX_LM3S102_KEIL/Demo1/main.c b/20080212/Demo/CORTEX_LM3S102_KEIL/Demo1/main.c new file mode 100644 index 000000000..6382d34c4 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_KEIL/Demo1/main.c @@ -0,0 +1,609 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + * This demo application creates six co-routines and two tasks (three including + * the idle task). The co-routines execute as part of the idle task hook. + * + * Five of the created co-routines are the standard 'co-routine flash' + * co-routines contained within the Demo/Common/Minimal/crflash.c file and + * documented on the FreeRTOS.org WEB site. + * + * The 'LCD Task' rotates a string on the LCD, delaying between each character + * as necessitated by the slow interface, and delaying between each string just + * long enough to enable the text to be read. + * + * The sixth co-routine and final task control the transmission and reception + * of a string to UART 0. The co-routine periodically sends the first + * character of the string to the UART, with the UART's TxEnd interrupt being + * used to transmit the remaining characters. The UART's RxEnd interrupt + * receives the characters and places them on a queue to be processed by the + * 'COMs Rx' task. An error is latched should an unexpected character be + * received, or any character be received out of sequence. + * + * A loopback connector is required to ensure that each character transmitted + * on the UART is also received on the same UART. For test purposes the UART + * FIFO's are not utalised in order to maximise the interrupt overhead. Also + * a pseudo random interval is used between the start of each transmission in + * order that the resultant interrupts are more randomly distributed and + * therefore more likely to highlight any problems. + * + * The flash co-routines control LED's zero to four. LED five is toggled each + * time the string is transmitted on the UART. LED six is toggled each time + * the string is CORRECTLY received on the UART. LED seven is latched on should + * an error be detected in any task or co-routine. + * + * In addition the idle task makes repetative calls to + * prvSetAndCheckRegisters(). This simply loads the general purpose registers + * with a known value, then checks each register to ensure the held value is + * still correct. As a low priority task this checking routine is likely to + * get repeatedly swapped in and out. A register being found to contain an + * incorrect value is therefore indicative of an error in the task switching + * mechansim. + * + */ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "croutine.h" + +/* Demo application include files. */ +#include "partest.h" +#include "crflash.h" + +/* Library include files. */ +#include "LM3Sxxx.h" +#include "pdc.h" + +/* The time to delay between writing each character to the LCD. */ +#define mainCHAR_WRITE_DELAY ( 2 / portTICK_RATE_MS ) + +/* The time to delay between writing each string to the LCD. */ +#define mainSTRING_WRITE_DELAY ( 400 / portTICK_RATE_MS ) + +/* The number of flash co-routines to create. */ +#define mainNUM_FLASH_CO_ROUTINES ( 5 ) + +/* The length of the queue used to pass received characters to the Comms Rx +task. */ +#define mainRX_QUEUE_LEN ( 5 ) + +/* The priority of the co-routine used to initiate the transmission of the +string on UART 0. */ +#define mainTX_CO_ROUTINE_PRIORITY ( 1 ) + +/* Only one co-routine is created so its index is not important. */ +#define mainTX_CO_ROUTINE_INDEX ( 0 ) + +/* The time between transmissions of the string on UART 0. This is pseudo +random in order to generate a bit or randomness to when the interrupts occur.*/ +#define mainMIN_TX_DELAY ( 40 / portTICK_RATE_MS ) +#define mainMAX_TX_DELAY ( ( portTickType ) 0x7f ) +#define mainOFFSET_TIME ( ( portTickType ) 3 ) + +/* The time the Comms Rx task should wait to receive a character. This should +be slightly longer than the time between transmissions. If we do not receive +a character after this time then there must be an error in the transmission or +the timing of the transmission. */ +#define mainCOMMS_RX_DELAY ( mainMAX_TX_DELAY + 20 ) + +/* The task priorites. */ +#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainCOMMS_RX_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The LED's toggled by the various tasks. */ +#define mainCOMMS_FAIL_LED ( 7 ) +#define mainCOMMS_RX_LED ( 6 ) +#define mainCOMMS_TX_LED ( 5 ) + +/* The baud rate used by the UART comms tasks/co-routine. */ +#define mainBAUD_RATE ( 57600 ) + +/* FIFO setting for the UART. The FIFO is not used to create a better test. */ +#define mainFIFO_SET ( 0x10 ) + +/* The string that is transmitted on the UART contains sequentially the +characters from mainFIRST_TX_CHAR to mainLAST_TX_CHAR. */ +#define mainFIRST_TX_CHAR '0' +#define mainLAST_TX_CHAR 'z' + +/* Just used to walk through the program memory in order that some random data +can be generated. */ +#define mainTOTAL_PROGRAM_MEMORY ( ( unsigned portLONG * ) ( 8 * 1024 ) ) +#define mainFIRST_PROGRAM_BYTES ( ( unsigned portLONG * ) 4 ) + +/*-----------------------------------------------------------*/ + +/* + * The task that rotates text on the LCD. + */ +static void vLCDTask( void * pvParameters ); + +/* + * The task that receives the characters from UART 0. + */ +static void vCommsRxTask( void * pvParameters ); + +/* + * The co-routine that periodically initiates the transmission of the string on + * the UART. + */ +static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + +/* + * Writes a string the the LCD. + */ +static void prvWriteString( const portCHAR *pcString ); + +/* + * Initialisation routine for the UART. + */ +static void vSerialInit( void ); + +/* + * Thread safe write to the PDC. + */ +static void prvPDCWrite( portCHAR cAddress, portCHAR cData ); + +/* + * Function to simply set a known value into the general purpose registers + * then read them back to ensure they remain set correctly. An incorrect value + * being indicative of an error in the task switching mechanism. + */ +void prvSetAndCheckRegisters( void ); + +/* + * Latch the LED that indicates that an error has occurred. + */ +void vSetErrorLED( void ); + +/* + * Sets up the PLL and ports used by the demo. + */ +static void prvSetupHardware( void ); + +/*-----------------------------------------------------------*/ + +/* Error flag set to pdFAIL if an error is encountered in the tasks/co-routines +defined within this file. */ +unsigned portBASE_TYPE uxErrorStatus = pdPASS; + +/* The next character to transmit. */ +static portCHAR cNextChar; + +/* The queue used to transmit characters from the interrupt to the Comms Rx +task. */ +static xQueueHandle xCommsQueue; + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + /* Create the queue used to communicate between the UART ISR and the Comms + Rx task. */ + xCommsQueue = xQueueCreate( mainRX_QUEUE_LEN, sizeof( portCHAR ) ); + + /* Setup the ports used by the demo and the clock. */ + prvSetupHardware(); + + /* Create the co-routines that flash the LED's. */ + vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES ); + + /* Create the co-routine that initiates the transmission of characters + on the UART. */ + xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX ); + + /* Create the LCD and Comms Rx tasks. */ + xTaskCreate( vLCDTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL ); + xTaskCreate( vCommsRxTask, "CMS", configMINIMAL_STACK_SIZE, NULL, mainCOMMS_RX_TASK_PRIORITY, NULL ); + + /* Start the scheduler running the tasks and co-routines just created. */ + vTaskStartScheduler(); + + /* Should not get here unless we did not have enough memory to start the + scheduler. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Setup the PLL. */ + SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); + + /* Initialise the hardware used to talk to the LCD, LED's and UART. */ + PDCInit(); + vParTestInitialise(); + vSerialInit(); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ + /* The co-routines are executed in the idle task using the idle task + hook. */ + for( ;; ) + { + /* Schedule the co-routines. */ + vCoRoutineSchedule(); + + /* Run the register check function between each co-routine. */ + prvSetAndCheckRegisters(); + } +} +/*-----------------------------------------------------------*/ + +static void prvWriteString( const portCHAR *pcString ) +{ + /* Write pcString to the LED, pausing between each character. */ + prvPDCWrite(PDC_LCD_CSR, LCD_CLEAR); + while( *pcString ) + { + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_RAM, *pcString ); + pcString++; + } +} +/*-----------------------------------------------------------*/ + +void vLCDTask( void * pvParameters ) +{ +unsigned portBASE_TYPE uxIndex; +const unsigned portCHAR ucCFGData[] = { + 0x30, /* Set data bus to 8-bits. */ + 0x30, + 0x30, + 0x3C, /* Number of lines/font. */ + 0x08, /* Display off. */ + 0x01, /* Display clear. */ + 0x06, /* Entry mode [cursor dir][shift]. */ + 0x0C /* Display on [display on][curson on][blinking on]. */ + }; + +/* The strings that are written to the LCD. */ +const portCHAR *pcStringsToDisplay[] = { + "Stellaris", + "Demo", + "One", + "www.FreeRTOS.org", + "" + }; + + /* Configure the LCD. */ + uxIndex = 0; + while( uxIndex < sizeof( ucCFGData ) ) + { + prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] ); + uxIndex++; + vTaskDelay( mainCHAR_WRITE_DELAY ); + } + + /* Turn the LCD Backlight on. */ + prvPDCWrite( PDC_CSR, 0x01 ); + + /* Clear display. */ + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR ); + + uxIndex = 0; + for( ;; ) + { + /* Display the string on the LCD. */ + prvWriteString( pcStringsToDisplay[ uxIndex ] ); + + /* Move on to the next string - wrapping if necessary. */ + uxIndex++; + if( *( pcStringsToDisplay[ uxIndex ] ) == 0x00 ) + { + uxIndex = 0; + /* Longer pause on the last string to be sent. */ + vTaskDelay( mainSTRING_WRITE_DELAY * 2 ); + } + + /* Wait until it is time to move onto the next string. */ + vTaskDelay( mainSTRING_WRITE_DELAY ); + } +} +/*-----------------------------------------------------------*/ + +static void vCommsRxTask( void * pvParameters ) +{ +static portCHAR cRxedChar, cExpectedChar; + + /* Set the char we expect to receive to the start of the string. */ + cExpectedChar = mainFIRST_TX_CHAR; + + for( ;; ) + { + /* Wait for a character to be received. */ + xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY ); + + /* Was the character recived (if any) the expected character. */ + if( cRxedChar != cExpectedChar ) + { + /* Got an unexpected character. This can sometimes occur when + reseting the system using the debugger leaving characters already + in the UART regsters. */ + uxErrorStatus = pdFAIL; + + /* Resync by waiting for the end of the current string. */ + while( cRxedChar != mainLAST_TX_CHAR ) + { + while( !xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, portMAX_DELAY ) ); + } + + /* The next expected character is the start of the string again. */ + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + if( cExpectedChar == mainLAST_TX_CHAR ) + { + /* We have reached the end of the string - we now expect to + receive the first character in the string again. The LED is + toggled to indicate that the entire string was received without + error. */ + vParTestToggleLED( mainCOMMS_RX_LED ); + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + /* We got the expected character, we now expect to receive the + next character in the string. */ + cExpectedChar++; + } + } + } +} +/*-----------------------------------------------------------*/ + +static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +portTickType xDelayPeriod; +static unsigned portLONG *pulRandomBytes = mainFIRST_PROGRAM_BYTES; + + /* Co-routine MUST start with a call to crSTART. */ + crSTART( xHandle ); + + for(;;) + { + /* Was the previously transmitted string received correctly? */ + if( uxErrorStatus != pdPASS ) + { + /* An error was encountered so set the error LED. */ + vSetErrorLED(); + } + + /* The next character to Tx is the first in the string. */ + cNextChar = mainFIRST_TX_CHAR; + + UARTIntDisable( UART0_BASE, UART_INT_TX ); + { + /* Send the first character. */ + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + + /* Move the variable to the char to Tx on so the ISR transmits + the next character in the string once this one has completed. */ + cNextChar++; + } + UARTIntEnable(UART0_BASE, UART_INT_TX); + + /* Toggle the LED to show a new string is being transmitted. */ + vParTestToggleLED( mainCOMMS_TX_LED ); + + /* Delay before we start the string off again. A pseudo-random delay + is used as this will provide a better test. */ + xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes ); + + pulRandomBytes++; + if( pulRandomBytes > mainTOTAL_PROGRAM_MEMORY ) + { + pulRandomBytes = mainFIRST_PROGRAM_BYTES; + } + + /* Make sure we don't wait too long... */ + xDelayPeriod &= mainMAX_TX_DELAY; + + /* ...but we do want to wait. */ + if( xDelayPeriod < mainMIN_TX_DELAY ) + { + xDelayPeriod = mainMIN_TX_DELAY; + } + + /* Block for the random(ish) time. */ + crDELAY( xHandle, xDelayPeriod ); + } + + /* Co-routine MUST end with a call to crEND. */ + crEND(); +} +/*-----------------------------------------------------------*/ + +static void vSerialInit( void ) +{ + /* Enable the UART. GPIOA has already been initialised. */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + + /* Set GPIO A0 and A1 as peripheral function. They are used to output the + UART signals. */ + GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); + + /* Configure the UART for 8-N-1 operation. */ + UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); + + /* We dont want to use the fifo. This is for test purposes to generate + as many interrupts as possible. */ + HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET; + + /* Enable both Rx and Tx interrupts. */ + HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX ); + IntEnable( INT_UART0 ); +} +/*-----------------------------------------------------------*/ + +void vUART_ISR(void) +{ +unsigned portLONG ulStatus; +portCHAR cRxedChar; +portBASE_TYPE xTaskWokenByPost = pdFALSE; + + /* What caused the interrupt. */ + ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); + + /* Clear the interrupt. */ + UARTIntClear( UART0_BASE, ulStatus ); + + /* Was an Rx interrpt pending? */ + if( ulStatus & UART_INT_RX ) + { + if( ( HWREG(UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) ) + { + /* Get the char from the buffer and post it onto the queue of + Rxed chars. Posting the character should wake the task that is + blocked on the queue waiting for characters. */ + cRxedChar = ( portCHAR ) HWREG( UART0_BASE + UART_O_DR ); + xTaskWokenByPost = xQueueSendFromISR( xCommsQueue, &cRxedChar, xTaskWokenByPost ); + } + } + + /* Was a Tx interrupt pending? */ + if( ulStatus & UART_INT_TX ) + { + /* Send the next character in the string. We are not using the FIFO. */ + if( cNextChar <= mainLAST_TX_CHAR ) + { + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + cNextChar++; + } + } + + if( xTaskWokenByPost ) + { + /* If a task was woken by the character being received then we force + a context switch to occur in case the task is of higher priority than + the currently executing task (i.e. the task that this interrupt + interrupted.) */ + portEND_SWITCHING_ISR( xTaskWokenByPost ); + } +} +/*-----------------------------------------------------------*/ + +static void prvPDCWrite( portCHAR cAddress, portCHAR cData ) +{ + vTaskSuspendAll(); + { + PDCWrite( cAddress, cData ); + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vSetErrorLED( void ) +{ + vParTestSetLED( mainCOMMS_FAIL_LED, pdTRUE ); +} +/*-----------------------------------------------------------*/ + +__asm void prvSetAndCheckRegisters( void ) +{ + extern vSetErrorLED + + /* Fill the general purpose registers with known values. */ + mov r11, #10 + add r0, r11, #1 + add r1, r11, #2 + add r2, r11, #3 + add r3, r11, #4 + add r4, r11, #5 + add r5, r11, #6 + add r6, r11, #7 + add r7, r11, #8 + add r8, r11, #9 + add r9, r11, #10 + add r10, r11, #11 + add r12, r11, #12 + + /* Check the values are as expected. */ + cmp r11, #10 + bne set_error_led + cmp r0, #11 + bne set_error_led + cmp r1, #12 + bne set_error_led + cmp r2, #13 + bne set_error_led + cmp r3, #14 + bne set_error_led + cmp r4, #15 + bne set_error_led + cmp r5, #16 + bne set_error_led + cmp r6, #17 + bne set_error_led + cmp r7, #18 + bne set_error_led + cmp r8, #19 + bne set_error_led + cmp r9, #20 + bne set_error_led + cmp r10, #21 + bne set_error_led + cmp r12, #22 + bne set_error_led + bx lr + +set_error_led; + push {r14} + ldr r1, =vSetErrorLED + blx r1 + pop {r14} + bx lr; +} +/*-----------------------------------------------------------*/ diff --git a/20080212/Demo/CORTEX_LM3S102_KEIL/Demo1/readme.txt b/20080212/Demo/CORTEX_LM3S102_KEIL/Demo1/readme.txt new file mode 100644 index 000000000..10334b9be --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_KEIL/Demo1/readme.txt @@ -0,0 +1,3 @@ +Move these two fines into the Demo/CORTEX_LM3S102_KEIL directory to run Demo 1. + +See the port documentation on the www.FreeRTOS.org site for more information. diff --git a/20080212/Demo/CORTEX_LM3S102_KEIL/Demo2/FreeRTOSConfig.h b/20080212/Demo/CORTEX_LM3S102_KEIL/Demo2/FreeRTOSConfig.h new file mode 100644 index 000000000..988846de9 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_KEIL/Demo2/FreeRTOSConfig.h @@ -0,0 +1,86 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 59 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1240 ) ) +#define configMAX_TASK_NAME_LEN ( 3 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_CO_ROUTINES 1 + +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 3 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 0 +#define INCLUDE_vTaskDelayUntil 0 +#define INCLUDE_vTaskDelay 1 + + + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/CORTEX_LM3S102_KEIL/Demo2/main.c b/20080212/Demo/CORTEX_LM3S102_KEIL/Demo2/main.c new file mode 100644 index 000000000..10789768b --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_KEIL/Demo2/main.c @@ -0,0 +1,614 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + * This demo application creates seven co-routines and one task (two including + * the idle task). The co-routines execute as part of the idle task hook. + * + * Five of the created co-routines are the standard 'co-routine flash' + * co-routines contained within the Demo/Common/Minimal/crflash.c file and + * documented on the FreeRTOS.org WEB site. + * + * The 'LCD Task' rotates a string on the LCD, delaying between each character + * as necessitated by the slow interface, and delaying between each string just + * long enough to enable the text to be read. + * + * The sixth co-routine controls the transmission of a string to UART 0. The + * co-routine periodically sends the first character of the string to the UART, + * with the UART's TxEnd interrupt being used to transmit the remaining + * characters. The UART's RxEnd interrupt receives the characters and places + * them on a queue to be processed by the seventh and final co-routine. An + * error is latched should an unexpected character be received, or any + * character be received out of sequence. + * + * A loopback connector is required to ensure that each character transmitted + * on the UART is also received on the same UART. For test purposes the UART + * FIFO's are not utalised in order to maximise the interrupt overhead. Also + * a pseudo random interval is used between the start of each transmission in + * order that the resultant interrupts are more randomly distributed and + * therefore more likely to highlight any problems. + * + * The flash co-routines control LED's zero to four. LED five is toggled each + * time the string is transmitted on the UART. LED six is toggled each time + * the string is CORRECTLY received on the UART. LED seven is latched on should + * an error be detected in any task or co-routine. + * + * In addition the idle task makes repetative calls to + * prvSetAndCheckRegisters(). This simply loads the general purpose registers + * with a known value, then checks each register to ensure the held value is + * still correct. As a low priority task this checking routine is likely to + * get repeatedly swapped in and out. A register being found to contain an + * incorrect value is therefore indicative of an error in the task switching + * mechansim. + * + */ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "croutine.h" + +/* Demo application include files. */ +#include "partest.h" +#include "crflash.h" + +/* Library include files. */ +#include "LM3Sxxx.h" +#include "pdc.h" + +/* The time to delay between writing each character to the LCD. */ +#define mainCHAR_WRITE_DELAY ( 2 / portTICK_RATE_MS ) + +/* The time to delay between writing each string to the LCD. */ +#define mainSTRING_WRITE_DELAY ( 400 / portTICK_RATE_MS ) + +/* The number of flash co-routines to create. */ +#define mainNUM_FLASH_CO_ROUTINES ( 5 ) + +/* The length of the queue used to pass received characters to the Comms Rx +task. */ +#define mainRX_QUEUE_LEN ( 5 ) + +/* The priority of the co-routine used to initiate the transmission of the +string on UART 0. */ +#define mainTX_CO_ROUTINE_PRIORITY ( 1 ) + +/* The priority of the co-routine used to receive characters from the UART. */ +#define mainRX_CO_ROUTINE_PRIORITY ( 2 ) + +/* Only one co-routine is created so its index is not important. */ +#define mainTX_CO_ROUTINE_INDEX ( 0 ) +#define mainRX_CO_ROUTINE_INDEX ( 0 ) + +/* The time between transmissions of the string on UART 0. This is pseudo +random in order to generate a bit or randomness to when the interrupts occur.*/ +#define mainMIN_TX_DELAY ( 40 / portTICK_RATE_MS ) +#define mainMAX_TX_DELAY ( ( portTickType ) 0x7f ) +#define mainOFFSET_TIME ( ( portTickType ) 3 ) + +/* The time the Comms Rx task should wait to receive a character. This should +be slightly longer than the time between transmissions. If we do not receive +a character after this time then there must be an error in the transmission or +the timing of the transmission. */ +#define mainCOMMS_RX_DELAY ( mainMAX_TX_DELAY + 20 ) + +/* The task priorites. */ +#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainCOMMS_RX_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The LED's toggled by the various tasks. */ +#define mainCOMMS_FAIL_LED ( 7 ) +#define mainCOMMS_RX_LED ( 6 ) +#define mainCOMMS_TX_LED ( 5 ) + +/* The baud rate used by the UART comms tasks/co-routine. */ +#define mainBAUD_RATE ( 57600 ) + +/* FIFO setting for the UART. The FIFO is not used to create a better test. */ +#define mainFIFO_SET ( 0x10 ) + +/* The string that is transmitted on the UART contains sequentially the +characters from mainFIRST_TX_CHAR to mainLAST_TX_CHAR. */ +#define mainFIRST_TX_CHAR '0' +#define mainLAST_TX_CHAR 'z' + +/* Just used to walk through the program memory in order that some random data +can be generated. */ +#define mainTOTAL_PROGRAM_MEMORY ( ( unsigned portLONG * ) ( 8 * 1024 ) ) +#define mainFIRST_PROGRAM_BYTES ( ( unsigned portLONG * ) 4 ) + +/*-----------------------------------------------------------*/ + +/* + * The task that rotates text on the LCD. + */ +static void vLCDTask( void * pvParameters ); + +/* + * The task that receives the characters from UART 0. + */ +static void vCommsRxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + +/* + * The co-routine that periodically initiates the transmission of the string on + * the UART. + */ +static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + +/* + * Writes a string the the LCD. + */ +static void prvWriteString( const portCHAR *pcString ); + +/* + * Initialisation routine for the UART. + */ +static void vSerialInit( void ); + +/* + * Thread safe write to the PDC. + */ +static void prvPDCWrite( portCHAR cAddress, portCHAR cData ); + +/* + * Function to simply set a known value into the general purpose registers + * then read them back to ensure they remain set correctly. An incorrect value + * being indicative of an error in the task switching mechanism. + */ +void prvSetAndCheckRegisters( void ); + +/* + * Latch the LED that indicates that an error has occurred. + */ +void vSetErrorLED( void ); + +/* + * Sets up the PLL and ports used by the demo. + */ +static void prvSetupHardware( void ); + +/*-----------------------------------------------------------*/ + +/* Error flag set to pdFAIL if an error is encountered in the tasks/co-routines +defined within this file. */ +unsigned portBASE_TYPE uxErrorStatus = pdPASS; + +/* The next character to transmit. */ +static portCHAR cNextChar; + +/* The queue used to transmit characters from the interrupt to the Comms Rx +task. */ +static xQueueHandle xCommsQueue; + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + /* Create the queue used to communicate between the UART ISR and the Comms + Rx task. */ + xCommsQueue = xQueueCreate( mainRX_QUEUE_LEN, sizeof( portCHAR ) ); + + /* Setup the ports used by the demo and the clock. */ + prvSetupHardware(); + + /* Create the co-routines that flash the LED's. */ + vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES ); + + /* Create the co-routine that initiates the transmission of characters + on the UART. */ + xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX ); + + /* Create the co-routine that receives characters from the UART. */ + xCoRoutineCreate( vCommsRxCoRoutine, mainRX_CO_ROUTINE_PRIORITY, mainRX_CO_ROUTINE_INDEX ); + + /* Create the LCD task. */ + xTaskCreate( vLCDTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL ); + + /* Start the scheduler running the tasks and co-routines just created. */ + vTaskStartScheduler(); + + /* Should not get here unless we did not have enough memory to start the + scheduler. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Setup the PLL. */ + SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); + + /* Initialise the hardware used to talk to the LCD, LED's and UART. */ + PDCInit(); + vParTestInitialise(); + vSerialInit(); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ + /* The co-routines are executed in the idle task using the idle task + hook. */ + for( ;; ) + { + /* Schedule the co-routines. */ + vCoRoutineSchedule(); + + /* Run the register check function between each co-routine. */ + prvSetAndCheckRegisters(); + } +} +/*-----------------------------------------------------------*/ + +static void prvWriteString( const portCHAR *pcString ) +{ + /* Write pcString to the LED, pausing between each character. */ + prvPDCWrite(PDC_LCD_CSR, LCD_CLEAR); + while( *pcString ) + { + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_RAM, *pcString ); + pcString++; + } +} +/*-----------------------------------------------------------*/ + +void vLCDTask( void * pvParameters ) +{ +unsigned portBASE_TYPE uxIndex; +const unsigned portCHAR ucCFGData[] = { + 0x30, /* Set data bus to 8-bits. */ + 0x30, + 0x30, + 0x3C, /* Number of lines/font. */ + 0x08, /* Display off. */ + 0x01, /* Display clear. */ + 0x06, /* Entry mode [cursor dir][shift]. */ + 0x0C /* Display on [display on][curson on][blinking on]. */ + }; + +/* The strings that are written to the LCD. */ +const portCHAR *pcStringsToDisplay[] = { + "Stellaris", + "Demo", + "Two", + "www.FreeRTOS.org", + "" + }; + + /* Configure the LCD. */ + uxIndex = 0; + while( uxIndex < sizeof( ucCFGData ) ) + { + prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] ); + uxIndex++; + vTaskDelay( mainCHAR_WRITE_DELAY ); + } + + /* Turn the LCD Backlight on. */ + prvPDCWrite( PDC_CSR, 0x01 ); + + /* Clear display. */ + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR ); + + uxIndex = 0; + for( ;; ) + { + /* Display the string on the LCD. */ + prvWriteString( pcStringsToDisplay[ uxIndex ] ); + + /* Move on to the next string - wrapping if necessary. */ + uxIndex++; + if( *( pcStringsToDisplay[ uxIndex ] ) == 0x00 ) + { + uxIndex = 0; + /* Longer pause on the last string to be sent. */ + vTaskDelay( mainSTRING_WRITE_DELAY * 2 ); + } + + /* Wait until it is time to move onto the next string. */ + vTaskDelay( mainSTRING_WRITE_DELAY ); + } +} +/*-----------------------------------------------------------*/ + +static void vCommsRxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +static portCHAR cRxedChar, cExpectedChar = mainFIRST_TX_CHAR; +portBASE_TYPE xResult; + + crSTART( xHandle ); + + for( ;; ) + { + /* Wait for a character to be received. */ + crQUEUE_RECEIVE( xHandle, xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY, &xResult ); + + /* Was the character recived (if any) the expected character. */ + if( ( cRxedChar != cExpectedChar ) || ( xResult != pdPASS ) ) + { + /* Got an unexpected character. This can sometimes occur when + reseting the system using the debugger leaving characters already + in the UART regsters. */ + uxErrorStatus = pdFAIL; + + /* Resync by waiting for the end of the current string. */ + while( cRxedChar != mainLAST_TX_CHAR ) + { + crQUEUE_RECEIVE( xHandle, xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY, &xResult ); + } + + /* The next expected character is the start of the string again. */ + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + if( cExpectedChar == mainLAST_TX_CHAR ) + { + /* We have reached the end of the string - we now expect to + receive the first character in the string again. The LED is + toggled to indicate that the entire string was received without + error. */ + vParTestToggleLED( mainCOMMS_RX_LED ); + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + /* We got the expected character, we now expect to receive the + next character in the string. */ + cExpectedChar++; + } + } + } + + crEND(); +} +/*-----------------------------------------------------------*/ + +static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +portTickType xDelayPeriod; +static unsigned portLONG *pulRandomBytes = mainFIRST_PROGRAM_BYTES; + + /* Co-routine MUST start with a call to crSTART. */ + crSTART( xHandle ); + + for(;;) + { + /* Was the previously transmitted string received correctly? */ + if( uxErrorStatus != pdPASS ) + { + /* An error was encountered so set the error LED. */ + vSetErrorLED(); + } + + /* The next character to Tx is the first in the string. */ + cNextChar = mainFIRST_TX_CHAR; + + UARTIntDisable( UART0_BASE, UART_INT_TX ); + { + /* Send the first character. */ + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + + /* Move the variable to the char to Tx on so the ISR transmits + the next character in the string once this one has completed. */ + cNextChar++; + } + UARTIntEnable(UART0_BASE, UART_INT_TX); + + /* Toggle the LED to show a new string is being transmitted. */ + vParTestToggleLED( mainCOMMS_TX_LED ); + + /* Delay before we start the string off again. A pseudo-random delay + is used as this will provide a better test. */ + xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes ); + + pulRandomBytes++; + if( pulRandomBytes > mainTOTAL_PROGRAM_MEMORY ) + { + pulRandomBytes = mainFIRST_PROGRAM_BYTES; + } + + /* Make sure we don't wait too long... */ + xDelayPeriod &= mainMAX_TX_DELAY; + + /* ...but we do want to wait. */ + if( xDelayPeriod < mainMIN_TX_DELAY ) + { + xDelayPeriod = mainMIN_TX_DELAY; + } + + /* Block for the random(ish) time. */ + crDELAY( xHandle, xDelayPeriod ); + } + + /* Co-routine MUST end with a call to crEND. */ + crEND(); +} +/*-----------------------------------------------------------*/ + +static void vSerialInit( void ) +{ + /* Enable the UART. GPIOA has already been initialised. */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + + /* Set GPIO A0 and A1 as peripheral function. They are used to output the + UART signals. */ + GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); + + /* Configure the UART for 8-N-1 operation. */ + UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); + + /* We dont want to use the fifo. This is for test purposes to generate + as many interrupts as possible. */ + HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET; + + /* Enable both Rx and Tx interrupts. */ + HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX ); + IntEnable( INT_UART0 ); +} +/*-----------------------------------------------------------*/ + +void vUART_ISR(void) +{ +unsigned portLONG ulStatus; +portCHAR cRxedChar; +portBASE_TYPE xTaskWokenByPost = pdFALSE; + + /* What caused the interrupt. */ + ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); + + /* Clear the interrupt. */ + UARTIntClear( UART0_BASE, ulStatus ); + + /* Was an Rx interrpt pending? */ + if( ulStatus & UART_INT_RX ) + { + if( ( HWREG(UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) ) + { + /* Get the char from the buffer and post it onto the queue of + Rxed chars. Posting the character should wake the task that is + blocked on the queue waiting for characters. */ + cRxedChar = ( portCHAR ) HWREG( UART0_BASE + UART_O_DR ); + xTaskWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsQueue, &cRxedChar, xTaskWokenByPost ); + } + } + + /* Was a Tx interrupt pending? */ + if( ulStatus & UART_INT_TX ) + { + /* Send the next character in the string. We are not using the FIFO. */ + if( cNextChar <= mainLAST_TX_CHAR ) + { + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + cNextChar++; + } + } + + if( xTaskWokenByPost ) + { + /* We are posting to a co-routine rather than a task so don't bother + causing a task switch. */ + } +} +/*-----------------------------------------------------------*/ + +static void prvPDCWrite( portCHAR cAddress, portCHAR cData ) +{ + vTaskSuspendAll(); + { + PDCWrite( cAddress, cData ); + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vSetErrorLED( void ) +{ + vParTestSetLED( mainCOMMS_FAIL_LED, pdTRUE ); +} +/*-----------------------------------------------------------*/ + +__asm void prvSetAndCheckRegisters( void ) +{ + extern vSetErrorLED + + /* Fill the general purpose registers with known values. */ + mov r11, #10 + add r0, r11, #1 + add r1, r11, #2 + add r2, r11, #3 + add r3, r11, #4 + add r4, r11, #5 + add r5, r11, #6 + add r6, r11, #7 + add r7, r11, #8 + add r8, r11, #9 + add r9, r11, #10 + add r10, r11, #11 + add r12, r11, #12 + + /* Check the values are as expected. */ + cmp r11, #10 + bne set_error_led + cmp r0, #11 + bne set_error_led + cmp r1, #12 + bne set_error_led + cmp r2, #13 + bne set_error_led + cmp r3, #14 + bne set_error_led + cmp r4, #15 + bne set_error_led + cmp r5, #16 + bne set_error_led + cmp r6, #17 + bne set_error_led + cmp r7, #18 + bne set_error_led + cmp r8, #19 + bne set_error_led + cmp r9, #20 + bne set_error_led + cmp r10, #21 + bne set_error_led + cmp r12, #22 + bne set_error_led + bx lr + +set_error_led; + push {r14} + ldr r1, =vSetErrorLED + blx r1 + pop {r14} + bx lr; +} +/*-----------------------------------------------------------*/ diff --git a/20080212/Demo/CORTEX_LM3S102_KEIL/Demo2/readme.txt b/20080212/Demo/CORTEX_LM3S102_KEIL/Demo2/readme.txt new file mode 100644 index 000000000..2ddb358de --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_KEIL/Demo2/readme.txt @@ -0,0 +1,3 @@ +Move these two fines into the Demo/CORTEX_LM3S102_KEIL directory to run Demo 2. + +See the port documentation on the www.FreeRTOS.org site for more information. diff --git a/20080212/Demo/CORTEX_LM3S102_KEIL/FreeRTOS.Opt b/20080212/Demo/CORTEX_LM3S102_KEIL/FreeRTOS.Opt new file mode 100644 index 000000000..548f3b365 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_KEIL/FreeRTOS.Opt @@ -0,0 +1,47 @@ +### uVision2 Project, (C) Keil Software +### Do not modify ! + + cExt (*.c) + aExt (*.s*; *.src; *.a*) + oExt (*.obj) + lExt (*.lib) + tExt (*.txt; *.h; *.inc) + pExt (*.plm) + CppX (*.cpp) + DaveTm { 0,0,0,0,0,0,0,0 } + +Target (LM3S1xx), 0x0004 // Tools: 'ARM-ADS' +GRPOPT 1,(Source),1,0,0 +GRPOPT 2,(Demo),1,0,0 + +OPTFFF 1,1,1,0,0,0,0,0,<..\..\Source\croutine.c> +OPTFFF 1,2,1,0,0,0,0,0,<..\..\Source\list.c> +OPTFFF 1,3,1,0,0,0,0,0,<..\..\Source\queue.c> +OPTFFF 1,4,1,0,0,0,0,0,<..\..\Source\tasks.c> +OPTFFF 1,5,1,0,0,0,0,0,<..\..\Source\portable\MemMang\heap_1.c> +OPTFFF 1,6,1,0,0,0,0,0,<..\..\Source\portable\RVDS\ARM_CM3\port.c> +OPTFFF 2,7,1,0,0,0,0,0,<.\main.c> +OPTFFF 2,8,2,0,0,0,0,0,<.\init\Startup.s> +OPTFFF 2,9,1,0,0,0,0,0,<..\Common\Minimal\crflash.c> +OPTFFF 2,10,1,0,0,0,0,0,<.\ParTest\ParTest.c> +OPTFFF 2,11,1,0,0,0,0,0,<.\include\pdc.c> +OPTFFF 2,12,4,0,0,0,0,0, + + +TARGOPT 1, (LM3S1xx) + ADSCLK=20000000 + OPTTT 1,1,1,0 + OPTHX 1,65535,0,0,0 + OPTLX 79,66,8,<.\uvision\> + OPTOX 16 + OPTLT 1,1,1,0,1,1,0,1,0,0,0,0 + OPTXL 1,1,1,1,1,1,1,0,0 + OPTFL 1,0,1 + OPTDL (SARMCM3.DLL)()(DLM.DLL)(-pLM3S101)(SARMCM3.DLL)()(TLM.DLL)(-pLM3S101) + OPTDBG 49150,1,()()()()()()()()()() (BIN\UL2CM3.DLL)()()() + OPTKEY 0,(UL2CM3)(-U -O14 -S0 -C-1 -FO7 -FD20000000 -FC800 -FN1 -FF0LM3S_8 -FS00 -FL02000) + OPTDF 0x0 + OPTLE <> + OPTLC <> +EndOpt + diff --git a/20080212/Demo/CORTEX_LM3S102_KEIL/FreeRTOS.Uv2 b/20080212/Demo/CORTEX_LM3S102_KEIL/FreeRTOS.Uv2 new file mode 100644 index 000000000..3afecbd5b --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_KEIL/FreeRTOS.Uv2 @@ -0,0 +1,109 @@ +### uVision2 Project, (C) Keil Software +### Do not modify ! + +Target (LM3S1xx), 0x0004 // Tools: 'ARM-ADS' + +Group (Source) +Group (Demo) + +File 1,1,<..\..\Source\croutine.c> 0x440790D8 +File 1,1,<..\..\Source\list.c> 0x440790D8 +File 1,1,<..\..\Source\queue.c> 0x440790D8 +File 1,1,<..\..\Source\tasks.c> 0x440790D8 +File 1,1,<..\..\Source\portable\MemMang\heap_1.c> 0x440790D8 +File 1,1,<..\..\Source\portable\RVDS\ARM_CM3\port.c> 0x440790D8 +File 2,1,<.\main.c> 0x441EE317 +File 2,2,<.\init\Startup.s> 0x44172A20 +File 2,1,<..\Common\Minimal\crflash.c> 0x440790D8 +File 2,1,<.\ParTest\ParTest.c> 0x440790D8 +File 2,1,<.\include\pdc.c> 0x44187439 +File 2,4, 0x44206F94 + + +Options 1,0,0 // Target 'LM3S1xx' + Device (LM3S101) + Vendor (Luminary Micro) + Cpu (IRAM(0x20000000-0x200007FF) IROM(0-0x1FFF) CLOCK(20000000) CPUTYPE("Cortex-M3")) + FlashUt () + StupF ("STARTUP\Luminary\Startup.s" ("Luminary Startup Code")) + FlashDR (UL2CM3(-U40296420 -O7 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0LM3S_8 -FS00 -FL02000)) + DevID (4079) + Rgf (LM3Sxxx.H) + Mem () + C () + A () + RL () + OH () + DBC_IFX () + DBC_CMS () + DBC_AMS () + DBC_LMS () + UseEnv=0 + EnvBin () + EnvInc () + EnvLib () + EnvReg (ÿLuminary\) + OrgReg (ÿLuminary\) + TgStat=0 + OutDir (.\uvision\) + OutName (RTOSDemo) + GenApp=1 + GenLib=0 + GenHex=0 + Debug=1 + Browse=1 + LstDir (.\uvision\) + HexSel=1 + MG32K=0 + TGMORE=0 + RunUsr 0 0 <> + RunUsr 1 0 <> + BrunUsr 0 0 <> + BrunUsr 1 0 <> + SVCSID <> + GLFLAGS=1790 + ADSFLGA { 243,31,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ACPUTYP (Cortex-M3) + ADSTFLGA { 0,12,0,0,99,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + OCMADSOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + OCMADSIRAM { 0,0,0,0,32,0,8,0,0 } + OCMADSIROM { 1,0,0,0,0,0,32,0,0 } + OCMADSXRAM { 0,0,0,0,0,0,0,0,0 } + OCR_RVCT { 1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,32,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,8,0,0,0,0,0,0,0,0,0,0,0 } + RV_STAVEC () + ADSCCFLG { 8,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ADSCMISC () + ADSCDEFN (RVDS_ARMCM3_LM3S102) + ADSCUDEF () + ADSCINCD (C:\Keil\ARM\RV30\LIB\Luminary;..\CORTEX_LM3S102_KEIL;..\..\Source\portable\RVDS\ARM_CM3;..\..\Source\include;..\Common\include;.\include) + ADSASFLG { 65,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ADSAMISC (--diag_suppress 1581) + ADSADEFN () + ADSAUDEF () + ADSAINCD () + PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + IncBld=1 + AlwaysBuild=0 + GenAsm=0 + AsmAsm=0 + PublicsOnly=0 + StopCode=3 + CustArgs () + LibMods () + ADSLDFG { 16,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ADSLDTA (0x00000000) + ADSLDDA (0x20000000) + ADSLDSC () + ADSLDIB () + ADSLDIC () + ADSLDMC (--entry Reset_Handler) + ADSLDIF () + ADSLDDW (6306) + OPTDL (SARMCM3.DLL)()(DLM.DLL)(-pLM3S101)(SARMCM3.DLL)()(TLM.DLL)(-pLM3S101) + OPTDBG 49150,1,()()()()()()()()()() (BIN\UL2CM3.DLL)()()() + FLASH1 { 1,0,0,0,1,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0 } + FLASH2 (BIN\UL2CM3.DLL) + FLASH3 ("" ()) + FLASH4 () +EndOpt + diff --git a/20080212/Demo/CORTEX_LM3S102_KEIL/FreeRTOSConfig.h b/20080212/Demo/CORTEX_LM3S102_KEIL/FreeRTOSConfig.h new file mode 100644 index 000000000..e403b289e --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_KEIL/FreeRTOSConfig.h @@ -0,0 +1,86 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 59 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1468 ) ) +#define configMAX_TASK_NAME_LEN ( 3 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_CO_ROUTINES 1 + +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 0 +#define INCLUDE_vTaskDelayUntil 0 +#define INCLUDE_vTaskDelay 1 + + + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/CORTEX_LM3S102_KEIL/ParTest/ParTest.c b/20080212/Demo/CORTEX_LM3S102_KEIL/ParTest/ParTest.c new file mode 100644 index 000000000..a95105b84 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_KEIL/ParTest/ParTest.c @@ -0,0 +1,122 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +/* +*/ + + +#include "FreeRTOS.h" +#include "Task.h" +#include "partest.h" + +#include "pdc.h" + +#define partstPINS (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 Z | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7) + +#define partstALL_OUTPUTS_OFF ( ( unsigned portCHAR ) 0x00 ) +#define partstMAX_OUTPUT_LED ( ( unsigned portCHAR ) 8 ) + +static volatile unsigned portCHAR ucOutputValue = partstALL_OUTPUTS_OFF; + +void vParTestInitialise( void ) +{ + PDCInit(); + PDCWrite( PDC_LED, ucOutputValue ); +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ +unsigned portCHAR ucBit = ( unsigned portCHAR ) 1; + + vTaskSuspendAll(); + { + if( uxLED < partstMAX_OUTPUT_LED ) + { + ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED; + + if( xValue == pdFALSE ) + { + ucBit ^= ( unsigned portCHAR ) 0xff; + ucOutputValue &= ucBit; + } + else + { + ucOutputValue |= ucBit; + } + + PDCWrite( PDC_LED, ucOutputValue ); + } + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned portCHAR ucBit; + + vTaskSuspendAll(); + { + if( uxLED < partstMAX_OUTPUT_LED ) + { + ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED; + + if( ucOutputValue & ucBit ) + { + ucOutputValue &= ~ucBit; + } + else + { + ucOutputValue |= ucBit; + } + + PDCWrite( PDC_LED, ucOutputValue ); + } + } + xTaskResumeAll(); +} + diff --git a/20080212/Demo/CORTEX_LM3S102_KEIL/include/pdc.c b/20080212/Demo/CORTEX_LM3S102_KEIL/include/pdc.c new file mode 100644 index 000000000..d1c544408 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_KEIL/include/pdc.c @@ -0,0 +1,118 @@ +//***************************************************************************** +// +// pdc.c - Driver for the Peripheral Device Controller (PDC) on the Stellaris +// development board. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +//***************************************************************************** + +#include "LM3Sxxx.h" +#include "pdc.h" + +//***************************************************************************** +// +//! Initializes the connection to the PDC. +//! +//! This function will enable clocking to the SSI and GPIO A modules, configure +//! the GPIO pins to be used for an SSI interface, and it will configure the +//! SSI as a 1Mb master device, operating in MOTO mode. It will also enable +//! the SSI module, and will enable the chip select for the PDC on the +//! Stellaris development board. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return None. +// +//***************************************************************************** +void +PDCInit(void) +{ + // + // Enable the peripherals used to drive the PDC. + // + SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + + // + // Configure the appropriate pins to be SSI instead of GPIO. + // + GPIODirModeSet(GPIO_PORTA_BASE, SSI_CLK | SSI_TX | SSI_RX, + GPIO_DIR_MODE_HW); + GPIODirModeSet(GPIO_PORTA_BASE, SSI_CS, GPIO_DIR_MODE_OUT); + GPIOPadConfigSet(GPIO_PORTA_BASE, SSI_CLK, GPIO_STRENGTH_4MA, + GPIO_PIN_TYPE_STD_WPU); + + // + // Configure the SSI port. + // + SSIConfig(SSI_BASE, SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 1000000, 8); + SSIEnable(SSI_BASE); + + // + // Reset the PDC SSI state machine. The chip select needs to be held low + // for 100ns; the procedure call overhead more than accounts for this time. + // + GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, 0); + GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, PDC_CS); +} + +//***************************************************************************** +// +//! Write a PDC register. +//! +//! \param ucAddr specifies the PDC register to write. +//! \param ucData specifies the data to write. +//! +//! This function will perform the SSI transfers required to write a register +//! in the PDC on the Stellaris development board. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return None. +// +//***************************************************************************** +void +PDCWrite(unsigned char ucAddr, unsigned char ucData) +{ + unsigned long ulTemp; + + // + // Send address and write command. + // + SSIDataPut(SSI_BASE, (ucAddr & 0x0F) | PDC_WR); + + // + // Write the data. + // + SSIDataPut(SSI_BASE, ucData); + + // + // Flush data read during address write. + // + SSIDataGet(SSI_BASE, &ulTemp); + + // + // Flush data read during data write. + // + SSIDataGet(SSI_BASE, &ulTemp); +} diff --git a/20080212/Demo/CORTEX_LM3S102_KEIL/include/pdc.h b/20080212/Demo/CORTEX_LM3S102_KEIL/include/pdc.h new file mode 100644 index 000000000..638080651 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_KEIL/include/pdc.h @@ -0,0 +1,122 @@ +//***************************************************************************** +// +// pdc.h - Stellaris development board Peripheral Device Controller definitions +// and prototypes. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +//***************************************************************************** + +#ifndef __PDC_H__ +#define __PDC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The registers within the peripheral device controller. +// +//***************************************************************************** +#define PDC_VER 0x0 // Version register +#define PDC_CSR 0x1 // Command/Status register +#define PDC_DSW 0x4 // DIP Switch register +#define PDC_LED 0x5 // LED register +#define PDC_LCD_CSR 0x6 // LCD Command/Status register +#define PDC_LCD_RAM 0x7 // LCD RAM register +#define PDC_GPXDAT 0x8 // GPIO X Data register +#define PDC_GPXDIR 0x9 // GPIO X Direction register +#define PDC_GPYDAT 0xA // GPIO Y Data register +#define PDC_GPYDIR 0xB // GPIO Y Direction register +#define PDC_GPZDAT 0xC // GPIO Z Data register +#define PDC_GPZDIR 0xD // GPIO Z Direction register + +//***************************************************************************** +// +// Flags indicating a read or write to the peripheral device controller. +// +//***************************************************************************** +#define PDC_RD 0x80 // PDC read command +#define PDC_WR 0x00 // PDC write command + +//***************************************************************************** +// +// LCD panel (Crystalfontz CFAH1602B) commands, RS = 0 +// +//***************************************************************************** +#define LCD_CLEAR 0x01 // Clear display (0 fill DDRAM). +#define LCD_HOME 0x02 // Cursor home. +#define LCD_MODE 0x04 // Set entry mode (cursor dir) +#define LCD_ON 0x08 // Set display, cursor, blinking + // on/off +#define LCD_CUR 0x10 // Cursor, display shift +#define LCD_IF 0x20 // Set interface data length, + // lines, font +#define LCD_CGADDR 0x40 // Set CGRAM AC address +#define LCD_DDADDR 0x80 // Set DDRAM AC address + +//***************************************************************************** +// +// LCD Status bit +// +//***************************************************************************** +#define LCD_B_BUSY 0x80 // Busy flag. + +//***************************************************************************** +// +// The GPIO port A pin numbers for the various SSI signals. +// +//***************************************************************************** +#define SSI_CS GPIO_PIN_3 +#define PDC_CS GPIO_PIN_3 +#define SSI_CLK GPIO_PIN_2 +#define SSI_TX GPIO_PIN_5 +#define SSI_RX GPIO_PIN_4 + +//***************************************************************************** +// +// Function Prototypes +// +//***************************************************************************** +extern void PDCInit(void); +extern unsigned char PDCRead(unsigned char ucAddr); +extern void PDCWrite(unsigned char ucAddr, unsigned char ucData); +extern unsigned char PDCDIPRead(void); +extern void PDCLEDWrite(unsigned char ucLED); +extern unsigned char PDCLEDRead(void); +extern void PDCLCDInit(void); +extern void PDCLCDBacklightOn(void); +extern void PDCLCDBacklightOff(void); +extern void PDCLCDClear(void); +extern void PDCLCDCreateChar(unsigned char ucChar, unsigned char *pucData); +extern void PDCLCDSetPos(unsigned char ucX, unsigned char ucY); +extern void PDCLCDWrite(const char *pcStr, unsigned long ulCount); +extern unsigned char PDCGPIODirRead(unsigned char ucIdx); +extern void PDCGPIODirWrite(unsigned char ucIdx, unsigned char ucValue); +extern unsigned char PDCGPIORead(unsigned char ucIdx); +extern void PDCGPIOWrite(unsigned char ucIdx, unsigned char ucValue); + +#ifdef __cplusplus +} +#endif + +#endif // __PDC_H__ diff --git a/20080212/Demo/CORTEX_LM3S102_KEIL/init/Startup.s b/20080212/Demo/CORTEX_LM3S102_KEIL/init/Startup.s new file mode 100644 index 000000000..c58ab3d14 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_KEIL/init/Startup.s @@ -0,0 +1,162 @@ +;/*****************************************************************************/ +;/* STARTUP.S: Startup file for Luminary Micro LM3Sxxx */ +;/*****************************************************************************/ +;/* <<< Use Configuration Wizard in Context Menu >>> */ +;/*****************************************************************************/ +;/* This file is part of the uVision/ARM development tools. */ +;/* Copyright (c) 2005-2006 Keil Software. All rights reserved. */ +;/* This software may only be used under the terms of a valid, current, */ +;/* end user licence from KEIL for a compatible version of KEIL software */ +;/* development tools. Nothing else gives you the right to use this software. */ +;/*****************************************************************************/ + + +;/* +; * The STARTUP.S code is executed after CPU Reset. +; */ + + +;// Stack Configuration +;// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +;// + +Stack_Size EQU 51 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size + + +;// Heap Configuration +;// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +;// + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +Heap_Mem SPACE Heap_Size + + +; System Control Register Addresses +SYSCTL_BASE EQU 0x400FE000 ; System Control Base Address +PBORCTL_OFS EQU 0x0030 ; Power-On & Brown-Out Reset Control +LDOPC_OFS EQU 0x0034 ; LDO Power +SRCR0_OFS EQU 0x0040 ; Software Reset Control 0 +SRCR1_OFS EQU 0x0044 ; Software Reset Control 1 +SRCR2_OFS EQU 0x0048 ; Software Reset Control 2 +RCC_OFS EQU 0x0060 ; Run-Mode Clock Control +RCGC0_OFS EQU 0x0100 ; Run-Mode Clock Gating Control 0 +RCGC1_OFS EQU 0x0104 ; Run-Mode Clock Gating Control 1 +RCGC2_OFS EQU 0x0108 ; Run-Mode Clock Gating Control 2 +SCGC0_OFS EQU 0x0110 ; Sleep-Mode Clock Gating Control 0 +SCGC1_OFS EQU 0x0114 ; Sleep-Mode Clock Gating Control 1 +SCGC2_OFS EQU 0x0118 ; Sleep-Mode Clock Gating Control 2 +DCGC0_OFS EQU 0x0120 ; Deep-Sleep-Mode Clock Gating Control 0 +DCGC1_OFS EQU 0x0124 ; Deep-Sleep-Mode Clock Gating Control 1 +DCGC2_OFS EQU 0x0128 ; Deep-Sleep-Mode Clock Gating Control 2 + + + PRESERVE8 + + +; Area Definition and Entry Point +; Startup Code must be linked first at Address 0. + + AREA RESET, CODE, READONLY + THUMB + + IMPORT xPortPendSVHandler + IMPORT xPortSysTickHandler + IMPORT vUART_ISR + +; Vector Table +Vectors DCD Stack_Mem + Stack_Size ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NmiSR ; NMI Handler + DCD DefaultISR ; Hard Fault Handler + DCD DefaultISR ; MPU Fault Handler + DCD DefaultISR ; Bus Fault Handler + DCD DefaultISR ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; SVCall Handler + DCD DefaultISR ; Debug Monitor Handler + DCD 0 ; Reserved + DCD xPortPendSVHandler ; PendSV Handler + DCD xPortSysTickHandler ; SysTick Handler + DCD DefaultISR ; GPIO Port A Handler + DCD DefaultISR ; GPIO Port B Handler + DCD DefaultISR ; GPIO Port C Handler + DCD DefaultISR ; GPIO Port D Handler + DCD DefaultISR ; GPIO Port E Handler + DCD vUART_ISR ; UART0 Rx/Tx Handler + DCD DefaultISR ; UART1 Rx/Tx Handler + DCD DefaultISR ; SSI Rx/Tx Handler + DCD DefaultISR ; I2C Master/Slave Handler + DCD DefaultISR ; PWM Fault Handler + DCD DefaultISR ; PWM Generator 0 Handler + DCD DefaultISR ; PWM Generator 1 Handler + DCD DefaultISR ; PWM Generator 2 Handler + DCD DefaultISR ; Quadrature Encoder Handler + DCD DefaultISR ; ADC Sequence 0 Handler + DCD DefaultISR ; ADC Sequence 1 Handler + DCD DefaultISR ; ADC Sequence 2 Handler + DCD DefaultISR ; ADC Sequence 3 Handler + DCD DefaultISR ; Watchdog Timer Handler + DCD DefaultISR ; Timer 0 Subtimer A Handler + DCD DefaultISR ; Timer 0 Subtimer B Handler + DCD DefaultISR ; Timer 1 Subtimer A Handler + DCD DefaultISR ; Timer 1 Subtimer B Handler + DCD DefaultISR ; Timer 2 Subtimer A Handler + DCD DefaultISR ; Timer 2 Subtimer B Handler + DCD DefaultISR ; Analog Comparator 0 Handler + DCD DefaultISR ; Analog Comparator 1 Handler + DCD DefaultISR ; Analog Comparator 2 Handler + DCD DefaultISR ; System Control Handler + DCD DefaultISR ; Flash Control Handler + +; Dummy Handlers are implemented as infinite loops which can be modified. + +NmiSR B NmiSR +FaultISR B FaultISR + EXPORT FaultISR +DefaultISR B DefaultISR + + +; Reset Handler + + EXPORT Reset_Handler +Reset_Handler + +; Enable Clock Gating for Peripherals +; LDR R0, =SYSCTL_BASE ; System Control Base Address +; MVN R1, #0 ; Value 0xFFFFFFFF +; STR R1, [R0,#RCGC0_OFS] ; Run-Mode Clock Gating Ctrl 0 +; STR R1, [R0,#RCGC1_OFS] ; Run-Mode Clock Gating Ctrl 1 +; STR R1, [R0,#RCGC2_OFS] ; Run-Mode Clock Gating Ctrl 2 + +; Enter the C code + + IMPORT __main + LDR R0, =__main + BX R0 + + +; User Initial Stack & Heap + AREA |.text|, CODE, READONLY + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + + END diff --git a/20080212/Demo/CORTEX_LM3S102_KEIL/main.c b/20080212/Demo/CORTEX_LM3S102_KEIL/main.c new file mode 100644 index 000000000..6382d34c4 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_KEIL/main.c @@ -0,0 +1,609 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + * This demo application creates six co-routines and two tasks (three including + * the idle task). The co-routines execute as part of the idle task hook. + * + * Five of the created co-routines are the standard 'co-routine flash' + * co-routines contained within the Demo/Common/Minimal/crflash.c file and + * documented on the FreeRTOS.org WEB site. + * + * The 'LCD Task' rotates a string on the LCD, delaying between each character + * as necessitated by the slow interface, and delaying between each string just + * long enough to enable the text to be read. + * + * The sixth co-routine and final task control the transmission and reception + * of a string to UART 0. The co-routine periodically sends the first + * character of the string to the UART, with the UART's TxEnd interrupt being + * used to transmit the remaining characters. The UART's RxEnd interrupt + * receives the characters and places them on a queue to be processed by the + * 'COMs Rx' task. An error is latched should an unexpected character be + * received, or any character be received out of sequence. + * + * A loopback connector is required to ensure that each character transmitted + * on the UART is also received on the same UART. For test purposes the UART + * FIFO's are not utalised in order to maximise the interrupt overhead. Also + * a pseudo random interval is used between the start of each transmission in + * order that the resultant interrupts are more randomly distributed and + * therefore more likely to highlight any problems. + * + * The flash co-routines control LED's zero to four. LED five is toggled each + * time the string is transmitted on the UART. LED six is toggled each time + * the string is CORRECTLY received on the UART. LED seven is latched on should + * an error be detected in any task or co-routine. + * + * In addition the idle task makes repetative calls to + * prvSetAndCheckRegisters(). This simply loads the general purpose registers + * with a known value, then checks each register to ensure the held value is + * still correct. As a low priority task this checking routine is likely to + * get repeatedly swapped in and out. A register being found to contain an + * incorrect value is therefore indicative of an error in the task switching + * mechansim. + * + */ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "croutine.h" + +/* Demo application include files. */ +#include "partest.h" +#include "crflash.h" + +/* Library include files. */ +#include "LM3Sxxx.h" +#include "pdc.h" + +/* The time to delay between writing each character to the LCD. */ +#define mainCHAR_WRITE_DELAY ( 2 / portTICK_RATE_MS ) + +/* The time to delay between writing each string to the LCD. */ +#define mainSTRING_WRITE_DELAY ( 400 / portTICK_RATE_MS ) + +/* The number of flash co-routines to create. */ +#define mainNUM_FLASH_CO_ROUTINES ( 5 ) + +/* The length of the queue used to pass received characters to the Comms Rx +task. */ +#define mainRX_QUEUE_LEN ( 5 ) + +/* The priority of the co-routine used to initiate the transmission of the +string on UART 0. */ +#define mainTX_CO_ROUTINE_PRIORITY ( 1 ) + +/* Only one co-routine is created so its index is not important. */ +#define mainTX_CO_ROUTINE_INDEX ( 0 ) + +/* The time between transmissions of the string on UART 0. This is pseudo +random in order to generate a bit or randomness to when the interrupts occur.*/ +#define mainMIN_TX_DELAY ( 40 / portTICK_RATE_MS ) +#define mainMAX_TX_DELAY ( ( portTickType ) 0x7f ) +#define mainOFFSET_TIME ( ( portTickType ) 3 ) + +/* The time the Comms Rx task should wait to receive a character. This should +be slightly longer than the time between transmissions. If we do not receive +a character after this time then there must be an error in the transmission or +the timing of the transmission. */ +#define mainCOMMS_RX_DELAY ( mainMAX_TX_DELAY + 20 ) + +/* The task priorites. */ +#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainCOMMS_RX_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The LED's toggled by the various tasks. */ +#define mainCOMMS_FAIL_LED ( 7 ) +#define mainCOMMS_RX_LED ( 6 ) +#define mainCOMMS_TX_LED ( 5 ) + +/* The baud rate used by the UART comms tasks/co-routine. */ +#define mainBAUD_RATE ( 57600 ) + +/* FIFO setting for the UART. The FIFO is not used to create a better test. */ +#define mainFIFO_SET ( 0x10 ) + +/* The string that is transmitted on the UART contains sequentially the +characters from mainFIRST_TX_CHAR to mainLAST_TX_CHAR. */ +#define mainFIRST_TX_CHAR '0' +#define mainLAST_TX_CHAR 'z' + +/* Just used to walk through the program memory in order that some random data +can be generated. */ +#define mainTOTAL_PROGRAM_MEMORY ( ( unsigned portLONG * ) ( 8 * 1024 ) ) +#define mainFIRST_PROGRAM_BYTES ( ( unsigned portLONG * ) 4 ) + +/*-----------------------------------------------------------*/ + +/* + * The task that rotates text on the LCD. + */ +static void vLCDTask( void * pvParameters ); + +/* + * The task that receives the characters from UART 0. + */ +static void vCommsRxTask( void * pvParameters ); + +/* + * The co-routine that periodically initiates the transmission of the string on + * the UART. + */ +static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + +/* + * Writes a string the the LCD. + */ +static void prvWriteString( const portCHAR *pcString ); + +/* + * Initialisation routine for the UART. + */ +static void vSerialInit( void ); + +/* + * Thread safe write to the PDC. + */ +static void prvPDCWrite( portCHAR cAddress, portCHAR cData ); + +/* + * Function to simply set a known value into the general purpose registers + * then read them back to ensure they remain set correctly. An incorrect value + * being indicative of an error in the task switching mechanism. + */ +void prvSetAndCheckRegisters( void ); + +/* + * Latch the LED that indicates that an error has occurred. + */ +void vSetErrorLED( void ); + +/* + * Sets up the PLL and ports used by the demo. + */ +static void prvSetupHardware( void ); + +/*-----------------------------------------------------------*/ + +/* Error flag set to pdFAIL if an error is encountered in the tasks/co-routines +defined within this file. */ +unsigned portBASE_TYPE uxErrorStatus = pdPASS; + +/* The next character to transmit. */ +static portCHAR cNextChar; + +/* The queue used to transmit characters from the interrupt to the Comms Rx +task. */ +static xQueueHandle xCommsQueue; + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + /* Create the queue used to communicate between the UART ISR and the Comms + Rx task. */ + xCommsQueue = xQueueCreate( mainRX_QUEUE_LEN, sizeof( portCHAR ) ); + + /* Setup the ports used by the demo and the clock. */ + prvSetupHardware(); + + /* Create the co-routines that flash the LED's. */ + vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES ); + + /* Create the co-routine that initiates the transmission of characters + on the UART. */ + xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX ); + + /* Create the LCD and Comms Rx tasks. */ + xTaskCreate( vLCDTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL ); + xTaskCreate( vCommsRxTask, "CMS", configMINIMAL_STACK_SIZE, NULL, mainCOMMS_RX_TASK_PRIORITY, NULL ); + + /* Start the scheduler running the tasks and co-routines just created. */ + vTaskStartScheduler(); + + /* Should not get here unless we did not have enough memory to start the + scheduler. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Setup the PLL. */ + SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); + + /* Initialise the hardware used to talk to the LCD, LED's and UART. */ + PDCInit(); + vParTestInitialise(); + vSerialInit(); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ + /* The co-routines are executed in the idle task using the idle task + hook. */ + for( ;; ) + { + /* Schedule the co-routines. */ + vCoRoutineSchedule(); + + /* Run the register check function between each co-routine. */ + prvSetAndCheckRegisters(); + } +} +/*-----------------------------------------------------------*/ + +static void prvWriteString( const portCHAR *pcString ) +{ + /* Write pcString to the LED, pausing between each character. */ + prvPDCWrite(PDC_LCD_CSR, LCD_CLEAR); + while( *pcString ) + { + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_RAM, *pcString ); + pcString++; + } +} +/*-----------------------------------------------------------*/ + +void vLCDTask( void * pvParameters ) +{ +unsigned portBASE_TYPE uxIndex; +const unsigned portCHAR ucCFGData[] = { + 0x30, /* Set data bus to 8-bits. */ + 0x30, + 0x30, + 0x3C, /* Number of lines/font. */ + 0x08, /* Display off. */ + 0x01, /* Display clear. */ + 0x06, /* Entry mode [cursor dir][shift]. */ + 0x0C /* Display on [display on][curson on][blinking on]. */ + }; + +/* The strings that are written to the LCD. */ +const portCHAR *pcStringsToDisplay[] = { + "Stellaris", + "Demo", + "One", + "www.FreeRTOS.org", + "" + }; + + /* Configure the LCD. */ + uxIndex = 0; + while( uxIndex < sizeof( ucCFGData ) ) + { + prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] ); + uxIndex++; + vTaskDelay( mainCHAR_WRITE_DELAY ); + } + + /* Turn the LCD Backlight on. */ + prvPDCWrite( PDC_CSR, 0x01 ); + + /* Clear display. */ + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR ); + + uxIndex = 0; + for( ;; ) + { + /* Display the string on the LCD. */ + prvWriteString( pcStringsToDisplay[ uxIndex ] ); + + /* Move on to the next string - wrapping if necessary. */ + uxIndex++; + if( *( pcStringsToDisplay[ uxIndex ] ) == 0x00 ) + { + uxIndex = 0; + /* Longer pause on the last string to be sent. */ + vTaskDelay( mainSTRING_WRITE_DELAY * 2 ); + } + + /* Wait until it is time to move onto the next string. */ + vTaskDelay( mainSTRING_WRITE_DELAY ); + } +} +/*-----------------------------------------------------------*/ + +static void vCommsRxTask( void * pvParameters ) +{ +static portCHAR cRxedChar, cExpectedChar; + + /* Set the char we expect to receive to the start of the string. */ + cExpectedChar = mainFIRST_TX_CHAR; + + for( ;; ) + { + /* Wait for a character to be received. */ + xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY ); + + /* Was the character recived (if any) the expected character. */ + if( cRxedChar != cExpectedChar ) + { + /* Got an unexpected character. This can sometimes occur when + reseting the system using the debugger leaving characters already + in the UART regsters. */ + uxErrorStatus = pdFAIL; + + /* Resync by waiting for the end of the current string. */ + while( cRxedChar != mainLAST_TX_CHAR ) + { + while( !xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, portMAX_DELAY ) ); + } + + /* The next expected character is the start of the string again. */ + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + if( cExpectedChar == mainLAST_TX_CHAR ) + { + /* We have reached the end of the string - we now expect to + receive the first character in the string again. The LED is + toggled to indicate that the entire string was received without + error. */ + vParTestToggleLED( mainCOMMS_RX_LED ); + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + /* We got the expected character, we now expect to receive the + next character in the string. */ + cExpectedChar++; + } + } + } +} +/*-----------------------------------------------------------*/ + +static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +portTickType xDelayPeriod; +static unsigned portLONG *pulRandomBytes = mainFIRST_PROGRAM_BYTES; + + /* Co-routine MUST start with a call to crSTART. */ + crSTART( xHandle ); + + for(;;) + { + /* Was the previously transmitted string received correctly? */ + if( uxErrorStatus != pdPASS ) + { + /* An error was encountered so set the error LED. */ + vSetErrorLED(); + } + + /* The next character to Tx is the first in the string. */ + cNextChar = mainFIRST_TX_CHAR; + + UARTIntDisable( UART0_BASE, UART_INT_TX ); + { + /* Send the first character. */ + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + + /* Move the variable to the char to Tx on so the ISR transmits + the next character in the string once this one has completed. */ + cNextChar++; + } + UARTIntEnable(UART0_BASE, UART_INT_TX); + + /* Toggle the LED to show a new string is being transmitted. */ + vParTestToggleLED( mainCOMMS_TX_LED ); + + /* Delay before we start the string off again. A pseudo-random delay + is used as this will provide a better test. */ + xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes ); + + pulRandomBytes++; + if( pulRandomBytes > mainTOTAL_PROGRAM_MEMORY ) + { + pulRandomBytes = mainFIRST_PROGRAM_BYTES; + } + + /* Make sure we don't wait too long... */ + xDelayPeriod &= mainMAX_TX_DELAY; + + /* ...but we do want to wait. */ + if( xDelayPeriod < mainMIN_TX_DELAY ) + { + xDelayPeriod = mainMIN_TX_DELAY; + } + + /* Block for the random(ish) time. */ + crDELAY( xHandle, xDelayPeriod ); + } + + /* Co-routine MUST end with a call to crEND. */ + crEND(); +} +/*-----------------------------------------------------------*/ + +static void vSerialInit( void ) +{ + /* Enable the UART. GPIOA has already been initialised. */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + + /* Set GPIO A0 and A1 as peripheral function. They are used to output the + UART signals. */ + GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); + + /* Configure the UART for 8-N-1 operation. */ + UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); + + /* We dont want to use the fifo. This is for test purposes to generate + as many interrupts as possible. */ + HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET; + + /* Enable both Rx and Tx interrupts. */ + HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX ); + IntEnable( INT_UART0 ); +} +/*-----------------------------------------------------------*/ + +void vUART_ISR(void) +{ +unsigned portLONG ulStatus; +portCHAR cRxedChar; +portBASE_TYPE xTaskWokenByPost = pdFALSE; + + /* What caused the interrupt. */ + ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); + + /* Clear the interrupt. */ + UARTIntClear( UART0_BASE, ulStatus ); + + /* Was an Rx interrpt pending? */ + if( ulStatus & UART_INT_RX ) + { + if( ( HWREG(UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) ) + { + /* Get the char from the buffer and post it onto the queue of + Rxed chars. Posting the character should wake the task that is + blocked on the queue waiting for characters. */ + cRxedChar = ( portCHAR ) HWREG( UART0_BASE + UART_O_DR ); + xTaskWokenByPost = xQueueSendFromISR( xCommsQueue, &cRxedChar, xTaskWokenByPost ); + } + } + + /* Was a Tx interrupt pending? */ + if( ulStatus & UART_INT_TX ) + { + /* Send the next character in the string. We are not using the FIFO. */ + if( cNextChar <= mainLAST_TX_CHAR ) + { + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + cNextChar++; + } + } + + if( xTaskWokenByPost ) + { + /* If a task was woken by the character being received then we force + a context switch to occur in case the task is of higher priority than + the currently executing task (i.e. the task that this interrupt + interrupted.) */ + portEND_SWITCHING_ISR( xTaskWokenByPost ); + } +} +/*-----------------------------------------------------------*/ + +static void prvPDCWrite( portCHAR cAddress, portCHAR cData ) +{ + vTaskSuspendAll(); + { + PDCWrite( cAddress, cData ); + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vSetErrorLED( void ) +{ + vParTestSetLED( mainCOMMS_FAIL_LED, pdTRUE ); +} +/*-----------------------------------------------------------*/ + +__asm void prvSetAndCheckRegisters( void ) +{ + extern vSetErrorLED + + /* Fill the general purpose registers with known values. */ + mov r11, #10 + add r0, r11, #1 + add r1, r11, #2 + add r2, r11, #3 + add r3, r11, #4 + add r4, r11, #5 + add r5, r11, #6 + add r6, r11, #7 + add r7, r11, #8 + add r8, r11, #9 + add r9, r11, #10 + add r10, r11, #11 + add r12, r11, #12 + + /* Check the values are as expected. */ + cmp r11, #10 + bne set_error_led + cmp r0, #11 + bne set_error_led + cmp r1, #12 + bne set_error_led + cmp r2, #13 + bne set_error_led + cmp r3, #14 + bne set_error_led + cmp r4, #15 + bne set_error_led + cmp r5, #16 + bne set_error_led + cmp r6, #17 + bne set_error_led + cmp r7, #18 + bne set_error_led + cmp r8, #19 + bne set_error_led + cmp r9, #20 + bne set_error_led + cmp r10, #21 + bne set_error_led + cmp r12, #22 + bne set_error_led + bx lr + +set_error_led; + push {r14} + ldr r1, =vSetErrorLED + blx r1 + pop {r14} + bx lr; +} +/*-----------------------------------------------------------*/ diff --git a/20080212/Demo/CORTEX_LM3S102_Rowley/Demo1/FreeRTOSConfig.h b/20080212/Demo/CORTEX_LM3S102_Rowley/Demo1/FreeRTOSConfig.h new file mode 100644 index 000000000..e403b289e --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_Rowley/Demo1/FreeRTOSConfig.h @@ -0,0 +1,86 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 59 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1468 ) ) +#define configMAX_TASK_NAME_LEN ( 3 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_CO_ROUTINES 1 + +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 0 +#define INCLUDE_vTaskDelayUntil 0 +#define INCLUDE_vTaskDelay 1 + + + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/CORTEX_LM3S102_Rowley/Demo1/ParTest.c b/20080212/Demo/CORTEX_LM3S102_Rowley/Demo1/ParTest.c new file mode 100644 index 000000000..a95105b84 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_Rowley/Demo1/ParTest.c @@ -0,0 +1,122 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +/* +*/ + + +#include "FreeRTOS.h" +#include "Task.h" +#include "partest.h" + +#include "pdc.h" + +#define partstPINS (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 Z | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7) + +#define partstALL_OUTPUTS_OFF ( ( unsigned portCHAR ) 0x00 ) +#define partstMAX_OUTPUT_LED ( ( unsigned portCHAR ) 8 ) + +static volatile unsigned portCHAR ucOutputValue = partstALL_OUTPUTS_OFF; + +void vParTestInitialise( void ) +{ + PDCInit(); + PDCWrite( PDC_LED, ucOutputValue ); +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ +unsigned portCHAR ucBit = ( unsigned portCHAR ) 1; + + vTaskSuspendAll(); + { + if( uxLED < partstMAX_OUTPUT_LED ) + { + ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED; + + if( xValue == pdFALSE ) + { + ucBit ^= ( unsigned portCHAR ) 0xff; + ucOutputValue &= ucBit; + } + else + { + ucOutputValue |= ucBit; + } + + PDCWrite( PDC_LED, ucOutputValue ); + } + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned portCHAR ucBit; + + vTaskSuspendAll(); + { + if( uxLED < partstMAX_OUTPUT_LED ) + { + ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED; + + if( ucOutputValue & ucBit ) + { + ucOutputValue &= ~ucBit; + } + else + { + ucOutputValue |= ucBit; + } + + PDCWrite( PDC_LED, ucOutputValue ); + } + } + xTaskResumeAll(); +} + diff --git a/20080212/Demo/CORTEX_LM3S102_Rowley/Demo1/main.c b/20080212/Demo/CORTEX_LM3S102_Rowley/Demo1/main.c new file mode 100644 index 000000000..7ec59f58c --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_Rowley/Demo1/main.c @@ -0,0 +1,627 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + * This demo application creates six co-routines and two tasks (three including + * the idle task). The co-routines execute as part of the idle task hook. + * + * Five of the created co-routines are the standard 'co-routine flash' + * co-routines contained within the Demo/Common/Minimal/crflash.c file and + * documented on the FreeRTOS.org WEB site. + * + * The 'LCD Task' rotates a string on the LCD, delaying between each character + * as necessitated by the slow interface, and delaying between each string just + * long enough to enable the text to be read. + * + * The sixth co-routine and final task control the transmission and reception + * of a string to UART 0. The co-routine periodically sends the first + * character of the string to the UART, with the UART's TxEnd interrupt being + * used to transmit the remaining characters. The UART's RxEnd interrupt + * receives the characters and places them on a queue to be processed by the + * 'COMs Rx' task. An error is latched should an unexpected character be + * received, or any character be received out of sequence. + * + * A loopback connector is required to ensure that each character transmitted + * on the UART is also received on the same UART. For test purposes the UART + * FIFO's are not utalised in order to maximise the interrupt overhead. Also + * a pseudo random interval is used between the start of each transmission in + * order that the resultant interrupts are more randomly distributed and + * therefore more likely to highlight any problems. + * + * The flash co-routines control LED's zero to four. LED five is toggled each + * time the string is transmitted on the UART. LED six is toggled each time + * the string is CORRECTLY received on the UART. LED seven is latched on should + * an error be detected in any task or co-routine. + * + * In addition the idle task makes repetative calls to + * prvSetAndCheckRegisters(). This simply loads the general purpose registers + * with a known value, then checks each register to ensure the held value is + * still correct. As a low priority task this checking routine is likely to + * get repeatedly swapped in and out. A register being found to contain an + * incorrect value is therefore indicative of an error in the task switching + * mechansim. + * + */ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "croutine.h" + +/* Demo application include files. */ +#include "partest.h" +#include "crflash.h" + +/* Library include files. */ +#include "DriverLib.h" + +/* The time to delay between writing each character to the LCD. */ +#define mainCHAR_WRITE_DELAY ( 2 / portTICK_RATE_MS ) + +/* The time to delay between writing each string to the LCD. */ +#define mainSTRING_WRITE_DELAY ( 400 / portTICK_RATE_MS ) + +/* The number of flash co-routines to create. */ +#define mainNUM_FLASH_CO_ROUTINES ( 5 ) + +/* The length of the queue used to pass received characters to the Comms Rx +task. */ +#define mainRX_QUEUE_LEN ( 5 ) + +/* The priority of the co-routine used to initiate the transmission of the +string on UART 0. */ +#define mainTX_CO_ROUTINE_PRIORITY ( 1 ) + +/* Only one co-routine is created so its index is not important. */ +#define mainTX_CO_ROUTINE_INDEX ( 0 ) + +/* The time between transmissions of the string on UART 0. This is pseudo +random in order to generate a bit or randomness to when the interrupts occur.*/ +#define mainMIN_TX_DELAY ( 40 / portTICK_RATE_MS ) +#define mainMAX_TX_DELAY ( ( portTickType ) 0x7f ) +#define mainOFFSET_TIME ( ( portTickType ) 3 ) + +/* The time the Comms Rx task should wait to receive a character. This should +be slightly longer than the time between transmissions. If we do not receive +a character after this time then there must be an error in the transmission or +the timing of the transmission. */ +#define mainCOMMS_RX_DELAY ( mainMAX_TX_DELAY + 20 ) + +/* The task priorites. */ +#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainCOMMS_RX_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The LED's toggled by the various tasks. */ +#define mainCOMMS_FAIL_LED ( 7 ) +#define mainCOMMS_RX_LED ( 6 ) +#define mainCOMMS_TX_LED ( 5 ) + +/* The baud rate used by the UART comms tasks/co-routine. */ +#define mainBAUD_RATE ( 57600 ) + +/* FIFO setting for the UART. The FIFO is not used to create a better test. */ +#define mainFIFO_SET ( 0x10 ) + +/* The string that is transmitted on the UART contains sequentially the +characters from mainFIRST_TX_CHAR to mainLAST_TX_CHAR. */ +#define mainFIRST_TX_CHAR '0' +#define mainLAST_TX_CHAR 'z' + +/* Just used to walk through the program memory in order that some random data +can be generated. */ +#define mainTOTAL_PROGRAM_MEMORY ( ( unsigned portLONG * ) ( 8 * 1024 ) ) +#define mainFIRST_PROGRAM_BYTES ( ( unsigned portLONG * ) 4 ) + +/* The error routine that is called if the driver library encounters an error. */ +#ifdef DEBUG +void +__error__(char *pcFilename, unsigned long ulLine) +{ +} +#endif + +/*-----------------------------------------------------------*/ + +/* + * The task that rotates text on the LCD. + */ +static void vLCDTask( void * pvParameters ); + +/* + * The task that receives the characters from UART 0. + */ +static void vCommsRxTask( void * pvParameters ); + +/* + * The co-routine that periodically initiates the transmission of the string on + * the UART. + */ +static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + +/* + * Writes a string the the LCD. + */ +static void prvWriteString( const portCHAR *pcString ); + +/* + * Initialisation routine for the UART. + */ +static void vSerialInit( void ); + +/* + * Thread safe write to the PDC. + */ +static void prvPDCWrite( portCHAR cAddress, portCHAR cData ); + +/* + * Function to simply set a known value into the general purpose registers + * then read them back to ensure they remain set correctly. An incorrect value + * being indicative of an error in the task switching mechanism. + */ +void prvSetAndCheckRegisters( void ); + +/* + * Latch the LED that indicates that an error has occurred. + */ +void vSetErrorLED( void ); + +/* + * Sets up the PLL and ports used by the demo. + */ +static void prvSetupHardware( void ); + +/*-----------------------------------------------------------*/ + +/* Error flag set to pdFAIL if an error is encountered in the tasks/co-routines +defined within this file. */ +unsigned portBASE_TYPE uxErrorStatus = pdPASS; + +/* The next character to transmit. */ +static portCHAR cNextChar; + +/* The queue used to transmit characters from the interrupt to the Comms Rx +task. */ +static xQueueHandle xCommsQueue; + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + /* Create the queue used to communicate between the UART ISR and the Comms + Rx task. */ + xCommsQueue = xQueueCreate( mainRX_QUEUE_LEN, sizeof( portCHAR ) ); + + /* Setup the ports used by the demo and the clock. */ + prvSetupHardware(); + + /* Create the co-routines that flash the LED's. */ + vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES ); + + /* Create the co-routine that initiates the transmission of characters + on the UART. */ + xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX ); + + /* Create the LCD and Comms Rx tasks. */ + xTaskCreate( vLCDTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL ); + xTaskCreate( vCommsRxTask, "CMS", configMINIMAL_STACK_SIZE, NULL, mainCOMMS_RX_TASK_PRIORITY, NULL ); + + /* Start the scheduler running the tasks and co-routines just created. */ + vTaskStartScheduler(); + + /* Should not get here unless we did not have enough memory to start the + scheduler. */ + for( ;; ); + return 0; +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Setup the PLL. */ + SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); + + /* Initialise the hardware used to talk to the LCD, LED's and UART. */ + PDCInit(); + vParTestInitialise(); + vSerialInit(); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ + /* The co-routines are executed in the idle task using the idle task + hook. */ + for( ;; ) + { + /* Schedule the co-routines. */ + vCoRoutineSchedule(); + + /* Run the register check function between each co-routine. */ + prvSetAndCheckRegisters(); + } +} +/*-----------------------------------------------------------*/ + +static void prvWriteString( const portCHAR *pcString ) +{ + /* Write pcString to the LED, pausing between each character. */ + prvPDCWrite(PDC_LCD_CSR, LCD_CLEAR); + while( *pcString ) + { + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_RAM, *pcString ); + pcString++; + } +} +/*-----------------------------------------------------------*/ + +void vLCDTask( void * pvParameters ) +{ +unsigned portBASE_TYPE uxIndex; +const unsigned portCHAR ucCFGData[] = { + 0x30, /* Set data bus to 8-bits. */ + 0x30, + 0x30, + 0x3C, /* Number of lines/font. */ + 0x08, /* Display off. */ + 0x01, /* Display clear. */ + 0x06, /* Entry mode [cursor dir][shift]. */ + 0x0C /* Display on [display on][curson on][blinking on]. */ + }; + +/* The strings that are written to the LCD. */ +const portCHAR *pcStringsToDisplay[] = { + "Stellaris", + "Demo", + "One", + "www.FreeRTOS.org", + "" + }; + + /* Configure the LCD. */ + uxIndex = 0; + while( uxIndex < sizeof( ucCFGData ) ) + { + prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] ); + uxIndex++; + vTaskDelay( mainCHAR_WRITE_DELAY ); + } + + /* Turn the LCD Backlight on. */ + prvPDCWrite( PDC_CSR, 0x01 ); + + /* Clear display. */ + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR ); + + uxIndex = 0; + for( ;; ) + { + /* Display the string on the LCD. */ + prvWriteString( pcStringsToDisplay[ uxIndex ] ); + + /* Move on to the next string - wrapping if necessary. */ + uxIndex++; + if( *( pcStringsToDisplay[ uxIndex ] ) == 0x00 ) + { + uxIndex = 0; + /* Longer pause on the last string to be sent. */ + vTaskDelay( mainSTRING_WRITE_DELAY * 2 ); + } + + /* Wait until it is time to move onto the next string. */ + vTaskDelay( mainSTRING_WRITE_DELAY ); + } +} +/*-----------------------------------------------------------*/ + +static void vCommsRxTask( void * pvParameters ) +{ +static portCHAR cRxedChar, cExpectedChar; + + /* Set the char we expect to receive to the start of the string. */ + cExpectedChar = mainFIRST_TX_CHAR; + + for( ;; ) + { + /* Wait for a character to be received. */ + xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY ); + + /* Was the character recived (if any) the expected character. */ + if( cRxedChar != cExpectedChar ) + { + /* Got an unexpected character. This can sometimes occur when + reseting the system using the debugger leaving characters already + in the UART regsters. */ + uxErrorStatus = pdFAIL; + + /* Resync by waiting for the end of the current string. */ + while( cRxedChar != mainLAST_TX_CHAR ) + { + while( !xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, portMAX_DELAY ) ); + } + + /* The next expected character is the start of the string again. */ + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + if( cExpectedChar == mainLAST_TX_CHAR ) + { + /* We have reached the end of the string - we now expect to + receive the first character in the string again. The LED is + toggled to indicate that the entire string was received without + error. */ + vParTestToggleLED( mainCOMMS_RX_LED ); + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + /* We got the expected character, we now expect to receive the + next character in the string. */ + cExpectedChar++; + } + } + } +} +/*-----------------------------------------------------------*/ + +static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +portTickType xDelayPeriod; +static unsigned portLONG *pulRandomBytes = mainFIRST_PROGRAM_BYTES; + + /* Co-routine MUST start with a call to crSTART. */ + crSTART( xHandle ); + + for(;;) + { + /* Was the previously transmitted string received correctly? */ + if( uxErrorStatus != pdPASS ) + { + /* An error was encountered so set the error LED. */ + vSetErrorLED(); + } + + /* The next character to Tx is the first in the string. */ + cNextChar = mainFIRST_TX_CHAR; + + UARTIntDisable( UART0_BASE, UART_INT_TX ); + { + /* Send the first character. */ + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + + /* Move the variable to the char to Tx on so the ISR transmits + the next character in the string once this one has completed. */ + cNextChar++; + } + UARTIntEnable(UART0_BASE, UART_INT_TX); + + /* Toggle the LED to show a new string is being transmitted. */ + vParTestToggleLED( mainCOMMS_TX_LED ); + + /* Delay before we start the string off again. A pseudo-random delay + is used as this will provide a better test. */ + xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes ); + + pulRandomBytes++; + if( pulRandomBytes > mainTOTAL_PROGRAM_MEMORY ) + { + pulRandomBytes = mainFIRST_PROGRAM_BYTES; + } + + /* Make sure we don't wait too long... */ + xDelayPeriod &= mainMAX_TX_DELAY; + + /* ...but we do want to wait. */ + if( xDelayPeriod < mainMIN_TX_DELAY ) + { + xDelayPeriod = mainMIN_TX_DELAY; + } + + /* Block for the random(ish) time. */ + crDELAY( xHandle, xDelayPeriod ); + } + + /* Co-routine MUST end with a call to crEND. */ + crEND(); +} +/*-----------------------------------------------------------*/ + +static void vSerialInit( void ) +{ + /* Enable the UART. GPIOA has already been initialised. */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + + /* Set GPIO A0 and A1 as peripheral function. They are used to output the + UART signals. */ + GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); + + /* Configure the UART for 8-N-1 operation. */ + UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); + + /* We dont want to use the fifo. This is for test purposes to generate + as many interrupts as possible. */ + HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET; + + /* Enable both Rx and Tx interrupts. */ + HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX ); + IntEnable( INT_UART0 ); +} +/*-----------------------------------------------------------*/ + +void vUART_ISR(void) +{ +unsigned portLONG ulStatus; +portCHAR cRxedChar; +portBASE_TYPE xTaskWokenByPost = pdFALSE; + + /* What caused the interrupt. */ + ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); + + /* Clear the interrupt. */ + UARTIntClear( UART0_BASE, ulStatus ); + + /* Was an Rx interrpt pending? */ + if( ulStatus & UART_INT_RX ) + { + if( ( HWREG(UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) ) + { + /* Get the char from the buffer and post it onto the queue of + Rxed chars. Posting the character should wake the task that is + blocked on the queue waiting for characters. */ + cRxedChar = ( portCHAR ) HWREG( UART0_BASE + UART_O_DR ); + xTaskWokenByPost = xQueueSendFromISR( xCommsQueue, &cRxedChar, xTaskWokenByPost ); + } + } + + /* Was a Tx interrupt pending? */ + if( ulStatus & UART_INT_TX ) + { + /* Send the next character in the string. We are not using the FIFO. */ + if( cNextChar <= mainLAST_TX_CHAR ) + { + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + cNextChar++; + } + } + + if( xTaskWokenByPost ) + { + /* If a task was woken by the character being received then we force + a context switch to occur in case the task is of higher priority than + the currently executing task (i.e. the task that this interrupt + interrupted.) */ + portEND_SWITCHING_ISR( xTaskWokenByPost ); + } +} +/*-----------------------------------------------------------*/ + +static void prvPDCWrite( portCHAR cAddress, portCHAR cData ) +{ + vTaskSuspendAll(); + { + PDCWrite( cAddress, cData ); + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vSetErrorLED( void ) +{ + vParTestSetLED( mainCOMMS_FAIL_LED, pdTRUE ); +} +/*-----------------------------------------------------------*/ + +void prvSetAndCheckRegisters( void ) +{ + /* Fill the general purpose registers with known values. */ + __asm volatile + ( + " mov r11, #10 \n" + " add r0, r11, #1 \n" + " add r1, r11, #2 \n" + " add r2, r11, #3 \n" + " add r3, r11, #4 \n" + " add r4, r11, #5 \n" + " add r5, r11, #6 \n" + " add r6, r11, #7 \n" + " add r7, r11, #8 \n" + " add r8, r11, #9 \n" + " add r9, r11, #10 \n" + " add r10, r11, #11 \n" + " add r12, r11, #12" + ); + + /* Check the values are as expected. */ + __asm volatile + ( + " cmp r11, #10 \n" + " bne set_error_led \n" + " cmp r0, #11 \n" + " bne set_error_led \n" + " cmp r1, #12 \n" + " bne set_error_led \n" + " cmp r2, #13 \n" + " bne set_error_led \n" + " cmp r3, #14 \n" + " bne set_error_led \n" + " cmp r4, #15 \n" + " bne set_error_led \n" + " cmp r5, #16 \n" + " bne set_error_led \n" + " cmp r6, #17 \n" + " bne set_error_led \n" + " cmp r7, #18 \n" + " bne set_error_led \n" + " cmp r8, #19 \n" + " bne set_error_led \n" + " cmp r9, #20 \n" + " bne set_error_led \n" + " cmp r10, #21 \n" + " bne set_error_led \n" + " cmp r12, #22 \n" + " bne set_error_led \n" + " bx lr" + ); + + __asm volatile + ( + "set_error_led: \n" + " push {r14} \n" + " ldr r1, vSetErrorLEDConst\n" + " blx r1 \n" + " pop {r14} \n" + " bx lr \n" + " \n" + " .align 2 \n" + "vSetErrorLEDConst: .word vSetErrorLED" + ); +} +/*-----------------------------------------------------------*/ diff --git a/20080212/Demo/CORTEX_LM3S102_Rowley/Demo1/vectors.s b/20080212/Demo/CORTEX_LM3S102_Rowley/Demo1/vectors.s new file mode 100644 index 000000000..2ff9827a2 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_Rowley/Demo1/vectors.s @@ -0,0 +1,119 @@ +/***************************************************************************** + * Copyright (c) 2006 Rowley Associates Limited. * + * * + * This file may be distributed under the terms of the License Agreement * + * provided with this software. * + * * + * THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE * + * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * + *****************************************************************************/ + .section .vectors, "ax" + .code 16 + .align 0 + .global _vectors + + .extern xPortPendSVHandler + .extern xPortSysTickHandler + .extern vUART_ISR + +.macro DEFAULT_ISR_HANDLER name= + .thumb_func + .weak \name +\name: +1: b 1b /* endless loop */ +.endm + +_vectors: + .word __stack_end__ +#ifdef STARTUP_FROM_RESET + .word _start +#else + .word reset_wait +#endif /* STARTUP_FROM_RESET */ + .word NmiISR + .word FaultISR + .word 0 // Populate if using MemManage (MPU) + .word 0 // Populate if using Bus fault + .word 0 // Populate if using Usage fault + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 + .word 0 // Populate if using a debug monitor + .word 0 // Reserved + .word xPortPendSVHandler // Populate if using pendable service request + .word xPortSysTickHandler + // External interrupts start her + .word GPIO_Port_A_ISR + .word GPIO_Port_B_ISR + .word GPIO_Port_C_ISR + .word GPIO_Port_D_ISR + .word GPIO_Port_E_ISR + .word vUART_ISR + .word UART1_ISR + .word SSI_ISR + .word I2C_ISR + .word PWM_Fault_ISR + .word PWM_Generator_0_ISR + .word PWM_Generator_1_ISR + .word PWM_Generator_2_ISR + .word QEI_ISR + .word ADC_Sequence_0_ISR + .word ADC_Sequence_1_ISR + .word ADC_Sequence_2_ISR + .word ADC_Sequence_3_ISR + .word Watchdog_timer_ISR + .word Timer0a_ISR + .word Timer0b_ISR + .word Timer1a_ISR + .word Timer1b_ISR + .word Timer2a_ISR + .word Timer2b_ISR + .word Analog_Comparator_0_ISR + .word Analog_Comparator_1_ISR + .word Analog_Comparator_2_ISR + .word System_Control_ISR + .word FLASH_Control_ISR + + .section .init, "ax" + .thumb_func + +DEFAULT_ISR_HANDLER NmiISR +DEFAULT_ISR_HANDLER FaultISR +DEFAULT_ISR_HANDLER SVCallISR +DEFAULT_ISR_HANDLER SysTickISR +DEFAULT_ISR_HANDLER GPIO_Port_A_ISR +DEFAULT_ISR_HANDLER GPIO_Port_B_ISR +DEFAULT_ISR_HANDLER GPIO_Port_C_ISR +DEFAULT_ISR_HANDLER GPIO_Port_D_ISR +DEFAULT_ISR_HANDLER GPIO_Port_E_ISR +DEFAULT_ISR_HANDLER UART0_ISR +DEFAULT_ISR_HANDLER UART1_ISR +DEFAULT_ISR_HANDLER SSI_ISR +DEFAULT_ISR_HANDLER I2C_ISR +DEFAULT_ISR_HANDLER PWM_Fault_ISR +DEFAULT_ISR_HANDLER PWM_Generator_0_ISR +DEFAULT_ISR_HANDLER PWM_Generator_1_ISR +DEFAULT_ISR_HANDLER PWM_Generator_2_ISR +DEFAULT_ISR_HANDLER QEI_ISR +DEFAULT_ISR_HANDLER ADC_Sequence_0_ISR +DEFAULT_ISR_HANDLER ADC_Sequence_1_ISR +DEFAULT_ISR_HANDLER ADC_Sequence_2_ISR +DEFAULT_ISR_HANDLER ADC_Sequence_3_ISR +DEFAULT_ISR_HANDLER Watchdog_timer_ISR +DEFAULT_ISR_HANDLER Timer0a_ISR +DEFAULT_ISR_HANDLER Timer0b_ISR +DEFAULT_ISR_HANDLER Timer1a_ISR +DEFAULT_ISR_HANDLER Timer1b_ISR +DEFAULT_ISR_HANDLER Timer2a_ISR +DEFAULT_ISR_HANDLER Timer2b_ISR +DEFAULT_ISR_HANDLER Analog_Comparator_0_ISR +DEFAULT_ISR_HANDLER Analog_Comparator_1_ISR +DEFAULT_ISR_HANDLER Analog_Comparator_2_ISR +DEFAULT_ISR_HANDLER System_Control_ISR +DEFAULT_ISR_HANDLER FLASH_Control_ISR + +#ifndef STARTUP_FROM_RESET +DEFAULT_ISR_HANDLER reset_wait +#endif /* STARTUP_FROM_RESET */ diff --git a/20080212/Demo/CORTEX_LM3S102_Rowley/Demo2/FreeRTOSConfig.h b/20080212/Demo/CORTEX_LM3S102_Rowley/Demo2/FreeRTOSConfig.h new file mode 100644 index 000000000..988846de9 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_Rowley/Demo2/FreeRTOSConfig.h @@ -0,0 +1,86 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 59 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1240 ) ) +#define configMAX_TASK_NAME_LEN ( 3 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_CO_ROUTINES 1 + +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 3 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 0 +#define INCLUDE_vTaskDelayUntil 0 +#define INCLUDE_vTaskDelay 1 + + + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/CORTEX_LM3S102_Rowley/Demo2/ParTest.c b/20080212/Demo/CORTEX_LM3S102_Rowley/Demo2/ParTest.c new file mode 100644 index 000000000..a95105b84 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_Rowley/Demo2/ParTest.c @@ -0,0 +1,122 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +/* +*/ + + +#include "FreeRTOS.h" +#include "Task.h" +#include "partest.h" + +#include "pdc.h" + +#define partstPINS (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 Z | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7) + +#define partstALL_OUTPUTS_OFF ( ( unsigned portCHAR ) 0x00 ) +#define partstMAX_OUTPUT_LED ( ( unsigned portCHAR ) 8 ) + +static volatile unsigned portCHAR ucOutputValue = partstALL_OUTPUTS_OFF; + +void vParTestInitialise( void ) +{ + PDCInit(); + PDCWrite( PDC_LED, ucOutputValue ); +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ +unsigned portCHAR ucBit = ( unsigned portCHAR ) 1; + + vTaskSuspendAll(); + { + if( uxLED < partstMAX_OUTPUT_LED ) + { + ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED; + + if( xValue == pdFALSE ) + { + ucBit ^= ( unsigned portCHAR ) 0xff; + ucOutputValue &= ucBit; + } + else + { + ucOutputValue |= ucBit; + } + + PDCWrite( PDC_LED, ucOutputValue ); + } + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned portCHAR ucBit; + + vTaskSuspendAll(); + { + if( uxLED < partstMAX_OUTPUT_LED ) + { + ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED; + + if( ucOutputValue & ucBit ) + { + ucOutputValue &= ~ucBit; + } + else + { + ucOutputValue |= ucBit; + } + + PDCWrite( PDC_LED, ucOutputValue ); + } + } + xTaskResumeAll(); +} + diff --git a/20080212/Demo/CORTEX_LM3S102_Rowley/Demo2/main.c b/20080212/Demo/CORTEX_LM3S102_Rowley/Demo2/main.c new file mode 100644 index 000000000..3e93d9978 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_Rowley/Demo2/main.c @@ -0,0 +1,632 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + * This demo application creates seven co-routines and one task (two including + * the idle task). The co-routines execute as part of the idle task hook. + * + * Five of the created co-routines are the standard 'co-routine flash' + * co-routines contained within the Demo/Common/Minimal/crflash.c file and + * documented on the FreeRTOS.org WEB site. + * + * The 'LCD Task' rotates a string on the LCD, delaying between each character + * as necessitated by the slow interface, and delaying between each string just + * long enough to enable the text to be read. + * + * The sixth co-routine controls the transmission of a string to UART 0. The + * co-routine periodically sends the first character of the string to the UART, + * with the UART's TxEnd interrupt being used to transmit the remaining + * characters. The UART's RxEnd interrupt receives the characters and places + * them on a queue to be processed by the seventh and final co-routine. An + * error is latched should an unexpected character be received, or any + * character be received out of sequence. + * + * A loopback connector is required to ensure that each character transmitted + * on the UART is also received on the same UART. For test purposes the UART + * FIFO's are not utalised in order to maximise the interrupt overhead. Also + * a pseudo random interval is used between the start of each transmission in + * order that the resultant interrupts are more randomly distributed and + * therefore more likely to highlight any problems. + * + * The flash co-routines control LED's zero to four. LED five is toggled each + * time the string is transmitted on the UART. LED six is toggled each time + * the string is CORRECTLY received on the UART. LED seven is latched on should + * an error be detected in any task or co-routine. + * + * In addition the idle task makes repetative calls to + * prvSetAndCheckRegisters(). This simply loads the general purpose registers + * with a known value, then checks each register to ensure the held value is + * still correct. As a low priority task this checking routine is likely to + * get repeatedly swapped in and out. A register being found to contain an + * incorrect value is therefore indicative of an error in the task switching + * mechansim. + * + */ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "croutine.h" + +/* Demo application include files. */ +#include "partest.h" +#include "crflash.h" + +/* Library include files. */ +#include "DriverLib.h" + +/* The time to delay between writing each character to the LCD. */ +#define mainCHAR_WRITE_DELAY ( 2 / portTICK_RATE_MS ) + +/* The time to delay between writing each string to the LCD. */ +#define mainSTRING_WRITE_DELAY ( 400 / portTICK_RATE_MS ) + +/* The number of flash co-routines to create. */ +#define mainNUM_FLASH_CO_ROUTINES ( 5 ) + +/* The length of the queue used to pass received characters to the Comms Rx +task. */ +#define mainRX_QUEUE_LEN ( 5 ) + +/* The priority of the co-routine used to initiate the transmission of the +string on UART 0. */ +#define mainTX_CO_ROUTINE_PRIORITY ( 1 ) + +/* The priority of the co-routine used to receive characters from the UART. */ +#define mainRX_CO_ROUTINE_PRIORITY ( 2 ) + +/* Only one co-routine is created so its index is not important. */ +#define mainTX_CO_ROUTINE_INDEX ( 0 ) +#define mainRX_CO_ROUTINE_INDEX ( 0 ) + +/* The time between transmissions of the string on UART 0. This is pseudo +random in order to generate a bit or randomness to when the interrupts occur.*/ +#define mainMIN_TX_DELAY ( 40 / portTICK_RATE_MS ) +#define mainMAX_TX_DELAY ( ( portTickType ) 0x7f ) +#define mainOFFSET_TIME ( ( portTickType ) 3 ) + +/* The time the Comms Rx task should wait to receive a character. This should +be slightly longer than the time between transmissions. If we do not receive +a character after this time then there must be an error in the transmission or +the timing of the transmission. */ +#define mainCOMMS_RX_DELAY ( mainMAX_TX_DELAY + 20 ) + +/* The task priorites. */ +#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainCOMMS_RX_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The LED's toggled by the various tasks. */ +#define mainCOMMS_FAIL_LED ( 7 ) +#define mainCOMMS_RX_LED ( 6 ) +#define mainCOMMS_TX_LED ( 5 ) + +/* The baud rate used by the UART comms tasks/co-routine. */ +#define mainBAUD_RATE ( 57600 ) + +/* FIFO setting for the UART. The FIFO is not used to create a better test. */ +#define mainFIFO_SET ( 0x10 ) + +/* The string that is transmitted on the UART contains sequentially the +characters from mainFIRST_TX_CHAR to mainLAST_TX_CHAR. */ +#define mainFIRST_TX_CHAR '0' +#define mainLAST_TX_CHAR 'z' + +/* Just used to walk through the program memory in order that some random data +can be generated. */ +#define mainTOTAL_PROGRAM_MEMORY ( ( unsigned portLONG * ) ( 8 * 1024 ) ) +#define mainFIRST_PROGRAM_BYTES ( ( unsigned portLONG * ) 4 ) + +/* The error routine that is called if the driver library encounters an error. */ +#ifdef DEBUG +void +__error__(char *pcFilename, unsigned long ulLine) +{ +} +#endif + +/*-----------------------------------------------------------*/ + +/* + * The task that rotates text on the LCD. + */ +static void vLCDTask( void * pvParameters ); + +/* + * The task that receives the characters from UART 0. + */ +static void vCommsRxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + +/* + * The co-routine that periodically initiates the transmission of the string on + * the UART. + */ +static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + +/* + * Writes a string the the LCD. + */ +static void prvWriteString( const portCHAR *pcString ); + +/* + * Initialisation routine for the UART. + */ +static void vSerialInit( void ); + +/* + * Thread safe write to the PDC. + */ +static void prvPDCWrite( portCHAR cAddress, portCHAR cData ); + +/* + * Function to simply set a known value into the general purpose registers + * then read them back to ensure they remain set correctly. An incorrect value + * being indicative of an error in the task switching mechanism. + */ +void prvSetAndCheckRegisters( void ); + +/* + * Latch the LED that indicates that an error has occurred. + */ +void vSetErrorLED( void ); + +/* + * Sets up the PLL and ports used by the demo. + */ +static void prvSetupHardware( void ); + +/*-----------------------------------------------------------*/ + +/* Error flag set to pdFAIL if an error is encountered in the tasks/co-routines +defined within this file. */ +unsigned portBASE_TYPE uxErrorStatus = pdPASS; + +/* The next character to transmit. */ +static portCHAR cNextChar; + +/* The queue used to transmit characters from the interrupt to the Comms Rx +task. */ +static xQueueHandle xCommsQueue; + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + /* Create the queue used to communicate between the UART ISR and the Comms + Rx task. */ + xCommsQueue = xQueueCreate( mainRX_QUEUE_LEN, sizeof( portCHAR ) ); + + /* Setup the ports used by the demo and the clock. */ + prvSetupHardware(); + + /* Create the co-routines that flash the LED's. */ + vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES ); + + /* Create the co-routine that initiates the transmission of characters + on the UART. */ + xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX ); + + /* Create the co-routine that receives characters from the UART. */ + xCoRoutineCreate( vCommsRxCoRoutine, mainRX_CO_ROUTINE_PRIORITY, mainRX_CO_ROUTINE_INDEX ); + + /* Create the LCD task. */ + xTaskCreate( vLCDTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL ); + + /* Start the scheduler running the tasks and co-routines just created. */ + vTaskStartScheduler(); + + /* Should not get here unless we did not have enough memory to start the + scheduler. */ + for( ;; ); + return 0; +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Setup the PLL. */ + SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); + + /* Initialise the hardware used to talk to the LCD, LED's and UART. */ + PDCInit(); + vParTestInitialise(); + vSerialInit(); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ + /* The co-routines are executed in the idle task using the idle task + hook. */ + for( ;; ) + { + /* Schedule the co-routines. */ + vCoRoutineSchedule(); + + /* Run the register check function between each co-routine. */ + prvSetAndCheckRegisters(); + } +} +/*-----------------------------------------------------------*/ + +static void prvWriteString( const portCHAR *pcString ) +{ + /* Write pcString to the LED, pausing between each character. */ + prvPDCWrite(PDC_LCD_CSR, LCD_CLEAR); + while( *pcString ) + { + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_RAM, *pcString ); + pcString++; + } +} +/*-----------------------------------------------------------*/ + +void vLCDTask( void * pvParameters ) +{ +unsigned portBASE_TYPE uxIndex; +const unsigned portCHAR ucCFGData[] = { + 0x30, /* Set data bus to 8-bits. */ + 0x30, + 0x30, + 0x3C, /* Number of lines/font. */ + 0x08, /* Display off. */ + 0x01, /* Display clear. */ + 0x06, /* Entry mode [cursor dir][shift]. */ + 0x0C /* Display on [display on][curson on][blinking on]. */ + }; + +/* The strings that are written to the LCD. */ +const portCHAR *pcStringsToDisplay[] = { + "Stellaris", + "Demo", + "Two", + "www.FreeRTOS.org", + "" + }; + + /* Configure the LCD. */ + uxIndex = 0; + while( uxIndex < sizeof( ucCFGData ) ) + { + prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] ); + uxIndex++; + vTaskDelay( mainCHAR_WRITE_DELAY ); + } + + /* Turn the LCD Backlight on. */ + prvPDCWrite( PDC_CSR, 0x01 ); + + /* Clear display. */ + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR ); + + uxIndex = 0; + for( ;; ) + { + /* Display the string on the LCD. */ + prvWriteString( pcStringsToDisplay[ uxIndex ] ); + + /* Move on to the next string - wrapping if necessary. */ + uxIndex++; + if( *( pcStringsToDisplay[ uxIndex ] ) == 0x00 ) + { + uxIndex = 0; + /* Longer pause on the last string to be sent. */ + vTaskDelay( mainSTRING_WRITE_DELAY * 2 ); + } + + /* Wait until it is time to move onto the next string. */ + vTaskDelay( mainSTRING_WRITE_DELAY ); + } +} +/*-----------------------------------------------------------*/ + +static void vCommsRxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +static portCHAR cRxedChar, cExpectedChar = mainFIRST_TX_CHAR; +portBASE_TYPE xResult; + + crSTART( xHandle ); + + for( ;; ) + { + /* Wait for a character to be received. */ + crQUEUE_RECEIVE( xHandle, xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY, &xResult ); + + /* Was the character recived (if any) the expected character. */ + if( ( cRxedChar != cExpectedChar ) || ( xResult != pdPASS ) ) + { + /* Got an unexpected character. This can sometimes occur when + reseting the system using the debugger leaving characters already + in the UART regsters. */ + uxErrorStatus = pdFAIL; + + /* Resync by waiting for the end of the current string. */ + while( cRxedChar != mainLAST_TX_CHAR ) + { + crQUEUE_RECEIVE( xHandle, xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY, &xResult ); + } + + /* The next expected character is the start of the string again. */ + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + if( cExpectedChar == mainLAST_TX_CHAR ) + { + /* We have reached the end of the string - we now expect to + receive the first character in the string again. The LED is + toggled to indicate that the entire string was received without + error. */ + vParTestToggleLED( mainCOMMS_RX_LED ); + cExpectedChar = mainFIRST_TX_CHAR; + } + else + { + /* We got the expected character, we now expect to receive the + next character in the string. */ + cExpectedChar++; + } + } + } + + crEND(); +} +/*-----------------------------------------------------------*/ + +static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +portTickType xDelayPeriod; +static unsigned portLONG *pulRandomBytes = mainFIRST_PROGRAM_BYTES; + + /* Co-routine MUST start with a call to crSTART. */ + crSTART( xHandle ); + + for(;;) + { + /* Was the previously transmitted string received correctly? */ + if( uxErrorStatus != pdPASS ) + { + /* An error was encountered so set the error LED. */ + vSetErrorLED(); + } + + /* The next character to Tx is the first in the string. */ + cNextChar = mainFIRST_TX_CHAR; + + UARTIntDisable( UART0_BASE, UART_INT_TX ); + { + /* Send the first character. */ + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + + /* Move the variable to the char to Tx on so the ISR transmits + the next character in the string once this one has completed. */ + cNextChar++; + } + UARTIntEnable(UART0_BASE, UART_INT_TX); + + /* Toggle the LED to show a new string is being transmitted. */ + vParTestToggleLED( mainCOMMS_TX_LED ); + + /* Delay before we start the string off again. A pseudo-random delay + is used as this will provide a better test. */ + xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes ); + + pulRandomBytes++; + if( pulRandomBytes > mainTOTAL_PROGRAM_MEMORY ) + { + pulRandomBytes = mainFIRST_PROGRAM_BYTES; + } + + /* Make sure we don't wait too long... */ + xDelayPeriod &= mainMAX_TX_DELAY; + + /* ...but we do want to wait. */ + if( xDelayPeriod < mainMIN_TX_DELAY ) + { + xDelayPeriod = mainMIN_TX_DELAY; + } + + /* Block for the random(ish) time. */ + crDELAY( xHandle, xDelayPeriod ); + } + + /* Co-routine MUST end with a call to crEND. */ + crEND(); +} +/*-----------------------------------------------------------*/ + +static void vSerialInit( void ) +{ + /* Enable the UART. GPIOA has already been initialised. */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + + /* Set GPIO A0 and A1 as peripheral function. They are used to output the + UART signals. */ + GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); + + /* Configure the UART for 8-N-1 operation. */ + UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); + + /* We dont want to use the fifo. This is for test purposes to generate + as many interrupts as possible. */ + HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET; + + /* Enable both Rx and Tx interrupts. */ + HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX ); + IntEnable( INT_UART0 ); +} +/*-----------------------------------------------------------*/ + +void vUART_ISR(void) +{ +unsigned portLONG ulStatus; +portCHAR cRxedChar; +portBASE_TYPE xTaskWokenByPost = pdFALSE; + + /* What caused the interrupt. */ + ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); + + /* Clear the interrupt. */ + UARTIntClear( UART0_BASE, ulStatus ); + + /* Was an Rx interrpt pending? */ + if( ulStatus & UART_INT_RX ) + { + if( ( HWREG(UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) ) + { + /* Get the char from the buffer and post it onto the queue of + Rxed chars. Posting the character should wake the task that is + blocked on the queue waiting for characters. */ + cRxedChar = ( portCHAR ) HWREG( UART0_BASE + UART_O_DR ); + xTaskWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsQueue, &cRxedChar, xTaskWokenByPost ); + } + } + + /* Was a Tx interrupt pending? */ + if( ulStatus & UART_INT_TX ) + { + /* Send the next character in the string. We are not using the FIFO. */ + if( cNextChar <= mainLAST_TX_CHAR ) + { + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + cNextChar++; + } + } + + if( xTaskWokenByPost ) + { + /* We are posting to a co-routine rather than a task so don't bother + causing a task switch. */ + } +} +/*-----------------------------------------------------------*/ + +static void prvPDCWrite( portCHAR cAddress, portCHAR cData ) +{ + vTaskSuspendAll(); + { + PDCWrite( cAddress, cData ); + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vSetErrorLED( void ) +{ + vParTestSetLED( mainCOMMS_FAIL_LED, pdTRUE ); +} +/*-----------------------------------------------------------*/ + +void prvSetAndCheckRegisters( void ) +{ + /* Fill the general purpose registers with known values. */ + __asm volatile + ( + " mov r11, #10 \n" + " add r0, r11, #1 \n" + " add r1, r11, #2 \n" + " add r2, r11, #3 \n" + " add r3, r11, #4 \n" + " add r4, r11, #5 \n" + " add r5, r11, #6 \n" + " add r6, r11, #7 \n" + " add r7, r11, #8 \n" + " add r8, r11, #9 \n" + " add r9, r11, #10 \n" + " add r10, r11, #11 \n" + " add r12, r11, #12" + ); + + /* Check the values are as expected. */ + __asm volatile + ( + " cmp r11, #10 \n" + " bne set_error_led \n" + " cmp r0, #11 \n" + " bne set_error_led \n" + " cmp r1, #12 \n" + " bne set_error_led \n" + " cmp r2, #13 \n" + " bne set_error_led \n" + " cmp r3, #14 \n" + " bne set_error_led \n" + " cmp r4, #15 \n" + " bne set_error_led \n" + " cmp r5, #16 \n" + " bne set_error_led \n" + " cmp r6, #17 \n" + " bne set_error_led \n" + " cmp r7, #18 \n" + " bne set_error_led \n" + " cmp r8, #19 \n" + " bne set_error_led \n" + " cmp r9, #20 \n" + " bne set_error_led \n" + " cmp r10, #21 \n" + " bne set_error_led \n" + " cmp r12, #22 \n" + " bne set_error_led \n" + " bx lr" + ); + + __asm volatile + ( + "set_error_led: \n" + " push {r14} \n" + " ldr r1, vSetErrorLEDConst\n" + " blx r1 \n" + " pop {r14} \n" + " bx lr \n" + " \n" + " .align 2 \n" + "vSetErrorLEDConst: .word vSetErrorLED" + ); +} +/*-----------------------------------------------------------*/ diff --git a/20080212/Demo/CORTEX_LM3S102_Rowley/Demo2/vectors.s b/20080212/Demo/CORTEX_LM3S102_Rowley/Demo2/vectors.s new file mode 100644 index 000000000..2ff9827a2 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_Rowley/Demo2/vectors.s @@ -0,0 +1,119 @@ +/***************************************************************************** + * Copyright (c) 2006 Rowley Associates Limited. * + * * + * This file may be distributed under the terms of the License Agreement * + * provided with this software. * + * * + * THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE * + * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * + *****************************************************************************/ + .section .vectors, "ax" + .code 16 + .align 0 + .global _vectors + + .extern xPortPendSVHandler + .extern xPortSysTickHandler + .extern vUART_ISR + +.macro DEFAULT_ISR_HANDLER name= + .thumb_func + .weak \name +\name: +1: b 1b /* endless loop */ +.endm + +_vectors: + .word __stack_end__ +#ifdef STARTUP_FROM_RESET + .word _start +#else + .word reset_wait +#endif /* STARTUP_FROM_RESET */ + .word NmiISR + .word FaultISR + .word 0 // Populate if using MemManage (MPU) + .word 0 // Populate if using Bus fault + .word 0 // Populate if using Usage fault + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 + .word 0 // Populate if using a debug monitor + .word 0 // Reserved + .word xPortPendSVHandler // Populate if using pendable service request + .word xPortSysTickHandler + // External interrupts start her + .word GPIO_Port_A_ISR + .word GPIO_Port_B_ISR + .word GPIO_Port_C_ISR + .word GPIO_Port_D_ISR + .word GPIO_Port_E_ISR + .word vUART_ISR + .word UART1_ISR + .word SSI_ISR + .word I2C_ISR + .word PWM_Fault_ISR + .word PWM_Generator_0_ISR + .word PWM_Generator_1_ISR + .word PWM_Generator_2_ISR + .word QEI_ISR + .word ADC_Sequence_0_ISR + .word ADC_Sequence_1_ISR + .word ADC_Sequence_2_ISR + .word ADC_Sequence_3_ISR + .word Watchdog_timer_ISR + .word Timer0a_ISR + .word Timer0b_ISR + .word Timer1a_ISR + .word Timer1b_ISR + .word Timer2a_ISR + .word Timer2b_ISR + .word Analog_Comparator_0_ISR + .word Analog_Comparator_1_ISR + .word Analog_Comparator_2_ISR + .word System_Control_ISR + .word FLASH_Control_ISR + + .section .init, "ax" + .thumb_func + +DEFAULT_ISR_HANDLER NmiISR +DEFAULT_ISR_HANDLER FaultISR +DEFAULT_ISR_HANDLER SVCallISR +DEFAULT_ISR_HANDLER SysTickISR +DEFAULT_ISR_HANDLER GPIO_Port_A_ISR +DEFAULT_ISR_HANDLER GPIO_Port_B_ISR +DEFAULT_ISR_HANDLER GPIO_Port_C_ISR +DEFAULT_ISR_HANDLER GPIO_Port_D_ISR +DEFAULT_ISR_HANDLER GPIO_Port_E_ISR +DEFAULT_ISR_HANDLER UART0_ISR +DEFAULT_ISR_HANDLER UART1_ISR +DEFAULT_ISR_HANDLER SSI_ISR +DEFAULT_ISR_HANDLER I2C_ISR +DEFAULT_ISR_HANDLER PWM_Fault_ISR +DEFAULT_ISR_HANDLER PWM_Generator_0_ISR +DEFAULT_ISR_HANDLER PWM_Generator_1_ISR +DEFAULT_ISR_HANDLER PWM_Generator_2_ISR +DEFAULT_ISR_HANDLER QEI_ISR +DEFAULT_ISR_HANDLER ADC_Sequence_0_ISR +DEFAULT_ISR_HANDLER ADC_Sequence_1_ISR +DEFAULT_ISR_HANDLER ADC_Sequence_2_ISR +DEFAULT_ISR_HANDLER ADC_Sequence_3_ISR +DEFAULT_ISR_HANDLER Watchdog_timer_ISR +DEFAULT_ISR_HANDLER Timer0a_ISR +DEFAULT_ISR_HANDLER Timer0b_ISR +DEFAULT_ISR_HANDLER Timer1a_ISR +DEFAULT_ISR_HANDLER Timer1b_ISR +DEFAULT_ISR_HANDLER Timer2a_ISR +DEFAULT_ISR_HANDLER Timer2b_ISR +DEFAULT_ISR_HANDLER Analog_Comparator_0_ISR +DEFAULT_ISR_HANDLER Analog_Comparator_1_ISR +DEFAULT_ISR_HANDLER Analog_Comparator_2_ISR +DEFAULT_ISR_HANDLER System_Control_ISR +DEFAULT_ISR_HANDLER FLASH_Control_ISR + +#ifndef STARTUP_FROM_RESET +DEFAULT_ISR_HANDLER reset_wait +#endif /* STARTUP_FROM_RESET */ diff --git a/20080212/Demo/CORTEX_LM3S102_Rowley/Demo3/FreeRTOSConfig.h b/20080212/Demo/CORTEX_LM3S102_Rowley/Demo3/FreeRTOSConfig.h new file mode 100644 index 000000000..1c57db990 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_Rowley/Demo3/FreeRTOSConfig.h @@ -0,0 +1,86 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 0 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 59 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1240 ) ) +#define configMAX_TASK_NAME_LEN ( 3 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_CO_ROUTINES 1 + +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 0 +#define INCLUDE_vTaskDelayUntil 0 +#define INCLUDE_vTaskDelay 0 + + + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/CORTEX_LM3S102_Rowley/Demo3/ParTest.c b/20080212/Demo/CORTEX_LM3S102_Rowley/Demo3/ParTest.c new file mode 100644 index 000000000..a9e8da93d --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_Rowley/Demo3/ParTest.c @@ -0,0 +1,122 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +/* +*/ + +/* Kernel include files. */ +#include "FreeRTOS.h" +#include "Task.h" +#include "partest.h" + +/* Hardware specific include files. */ +#include "DriverLib.h" + +static const unsigned portLONG ulLEDs[] = +{ + GPIO_PIN_6, GPIO_PIN_1, GPIO_PIN_0 +}; + +#define partstLED_PINS ( GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_6 ) + +#define partstMAX_OUTPUT_LED ( ( unsigned portCHAR ) 3 ) + +/*-----------------------------------------------------------*/ +void vParTestInitialise( void ) +{ +portBASE_TYPE xLED; + + /* The LED's are on port B. */ + GPIODirModeSet( GPIO_PORTB_BASE, partstLED_PINS, GPIO_DIR_MODE_OUT ); + + for( xLED = 0; xLED < partstMAX_OUTPUT_LED; xLED++ ) + { + vParTestSetLED( xLED, pdFALSE ); + } +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ + vTaskSuspendAll(); + { + if( uxLED < partstMAX_OUTPUT_LED ) + { + if( xValue == pdFALSE ) + { + GPIOPinWrite( GPIO_PORTB_BASE, ulLEDs[ uxLED ], ulLEDs[ uxLED ] ); + } + else + { + GPIOPinWrite( GPIO_PORTB_BASE, ulLEDs[ uxLED ], ~ulLEDs[ uxLED ] ); + } + } + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +portBASE_TYPE xCurrentValue; + + vTaskSuspendAll(); + { + if( uxLED < partstMAX_OUTPUT_LED ) + { + xCurrentValue = GPIOPinRead( GPIO_PORTB_BASE, ulLEDs[ uxLED ] ); + if( xCurrentValue ) + { + GPIOPinWrite( GPIO_PORTB_BASE, ulLEDs[ uxLED ], ~ulLEDs[ uxLED ] ); + } + else + { + GPIOPinWrite( GPIO_PORTB_BASE, ulLEDs[ uxLED ], ulLEDs[ uxLED ] ); + } + } + } + xTaskResumeAll(); +} diff --git a/20080212/Demo/CORTEX_LM3S102_Rowley/Demo3/main.c b/20080212/Demo/CORTEX_LM3S102_Rowley/Demo3/main.c new file mode 100644 index 000000000..7376c2f1c --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_Rowley/Demo3/main.c @@ -0,0 +1,300 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +/* + * This is a mini co-routine demo for the Rowley CrossFire LM3S102 development + * board. It makes use of the boards tri-colour LED and analogue input. + * + * Four co-routines are created - an 'I2C' co-routine and three 'flash' + * co-routines. + * + * The I2C co-routine triggers an ADC conversion then blocks on a queue to + * wait for the conversion result - which it receives on the queue directly + * from the I2C interrupt service routine. The conversion result is then + * scalled to a delay period. The I2C interrupt then wakes each of the + * flash co-routines before itself delaying for the calculated period and + * then repeating the whole process. + * + * When woken by the I2C co-routine the flash co-routines each block for + * a given period, illuminate an LED for a fixed period, then go back to + * sleep to wait for the next cycle. The uxIndex parameter of the flash + * co-routines is used to ensure that each flashes a different LED, and that + * the delay periods are such that the LED's get flashed in sequence. + */ + + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "croutine.h" + +/* Demo application include files. */ +#include "partest.h" + +/* Library include files. */ +#include "DriverLib.h" + +/* States of the I2C master interface. */ +#define mainI2C_IDLE 0 +#define mainI2C_READ_1 1 +#define mainI2C_READ_2 2 +#define mainI2C_READ_DONE 3 + +#define mainZERO_LENGTH 0 + +/* Address of the A2D IC on the CrossFire board. */ +#define mainI2CAddress 0x4D + +/* The queue used to send data from the I2C ISR to the co-routine should never +contain more than one item as the same co-routine is used to trigger the I2C +activity. */ +#define mainQUEUE_LENGTH 1 + +/* The CrossFire board contains a tri-colour LED. */ +#define mainNUM_LEDs 3 + +/* The I2C co-routine has a higher priority than the flash co-routines. This +is not really necessary as when the I2C co-routine is active the other +co-routines are delaying. */ +#define mainI2c_CO_ROUTINE_PRIORITY 1 + + +/* The current state of the I2C master. */ +static volatile unsigned portBASE_TYPE uxState = mainI2C_IDLE; + +/* The delay period derived from the A2D value. */ +static volatile portBASE_TYPE uxDelay = 250; + +/* The queue used to communicate between the I2C interrupt and the I2C +co-routine. */ +static xQueueHandle xADCQueue; + +/* The queue used to synchronise the flash co-routines. */ +static xQueueHandle xDelayQueue; + +/* + * Sets up the PLL, I2C and GPIO used by the demo. + */ +static void prvSetupHardware( void ); + +/* The co-routines as described at the top of the file. */ +static void vI2CCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); +static void vFlashCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + +/*-----------------------------------------------------------*/ + +int main( void ) +{ +unsigned portBASE_TYPE uxCoRoutine; + + /* Setup all the hardware used by this demo. */ + prvSetupHardware(); + + /* Create the queue used to communicate between the ISR and I2C co-routine. + This can only ever contain one value. */ + xADCQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( portTickType ) ); + + /* Create the queue used to synchronise the flash co-routines. The queue + is used to trigger three tasks, but is for synchronisation only and does + not pass any data. It therefore has three position each of zero length. */ + xDelayQueue = xQueueCreate( mainNUM_LEDs, mainZERO_LENGTH ); + + /* Create the co-routine that initiates the i2c. */ + xCoRoutineCreate( vI2CCoRoutine, mainI2c_CO_ROUTINE_PRIORITY, 0 ); + + /* Create the flash co-routines. */ + for( uxCoRoutine = 0; uxCoRoutine < mainNUM_LEDs; uxCoRoutine++ ) + { + xCoRoutineCreate( vFlashCoRoutine, tskIDLE_PRIORITY, uxCoRoutine ); + } + + /* Start the scheduler. From this point on the co-routines should + execute. */ + vTaskStartScheduler(); + + /* Should not get here unless we did not have enough memory to start the + scheduler. */ + for( ;; ); + return 0; +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Setup the PLL. */ + SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); + + /* Enable the I2C used to read the pot. */ + SysCtlPeripheralEnable( SYSCTL_PERIPH_I2C ); + SysCtlPeripheralEnable( SYSCTL_PERIPH_GPIOB ); + GPIOPinTypeI2C( GPIO_PORTB_BASE, GPIO_PIN_2 | GPIO_PIN_3 ); + + /* Initialize the I2C master. */ + I2CMasterInit( I2C_MASTER_BASE, pdFALSE ); + + /* Enable the I2C master interrupt. */ + I2CMasterIntEnable( I2C_MASTER_BASE ); + IntEnable( INT_I2C ); + + /* Initialise the hardware used to talk to the LED's. */ + vParTestInitialise(); +} +/*-----------------------------------------------------------*/ + +static void vI2CCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +portTickType xADCResult; +static portBASE_TYPE xResult = 0, xMilliSecs, xLED; + + crSTART( xHandle ); + + for( ;; ) + { + /* Start the I2C off to read the ADC. */ + uxState = mainI2C_READ_1; + I2CMasterSlaveAddrSet( I2C_MASTER_BASE, mainI2CAddress, pdTRUE ); + I2CMasterControl( I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_RECEIVE_START ); + + /* Wait to receive the conversion result. */ + crQUEUE_RECEIVE( xHandle, xADCQueue, &xADCResult, portMAX_DELAY, &xResult ); + + /* Scale the result to give a useful range of values for a visual + demo. */ + xADCResult >>= 2; + xMilliSecs = xADCResult / portTICK_RATE_MS; + + /* The delay is split between the four co-routines so they remain in + synch. */ + uxDelay = xMilliSecs / ( mainNUM_LEDs + 1 ); + + /* Trigger each of the flash co-routines. */ + for( xLED = 0; xLED < mainNUM_LEDs; xLED++ ) + { + crQUEUE_SEND( xHandle, xDelayQueue, &xLED, 0, &xResult ); + } + + /* Wait for the full delay time then start again. This delay is long + enough to ensure the flash co-routines have done their thing and gone + back to sleep. */ + crDELAY( xHandle, xMilliSecs ); + } + + crEND(); +} +/*-----------------------------------------------------------*/ + +static void vFlashCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +portBASE_TYPE xResult, xNothing; + + crSTART( xHandle ); + + for( ;; ) + { + /* Wait for start of next round. */ + crQUEUE_RECEIVE( xHandle, xDelayQueue, &xNothing, portMAX_DELAY, &xResult ); + + /* Wait until it is this co-routines turn to flash. */ + crDELAY( xHandle, uxDelay * uxIndex ); + + /* Turn on the LED for a fixed period. */ + vParTestSetLED( uxIndex, pdTRUE ); + crDELAY( xHandle, uxDelay ); + vParTestSetLED( uxIndex, pdFALSE ); + + /* Go back and wait for the next round. */ + } + + crEND(); +} +/*-----------------------------------------------------------*/ + +void vI2C_ISR(void) +{ +static portTickType xReading; + + /* Clear the interrupt. */ + I2CMasterIntClear( I2C_MASTER_BASE ); + + /* Determine what to do based on the current uxState. */ + switch (uxState) + { + case mainI2C_IDLE: break; + + case mainI2C_READ_1: /* Read ADC result high byte. */ + xReading = I2CMasterDataGet( I2C_MASTER_BASE ); + xReading <<= 8; + + /* Continue the burst read. */ + I2CMasterControl( I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_RECEIVE_CONT ); + uxState = mainI2C_READ_2; + break; + + case mainI2C_READ_2: /* Read ADC result low byte. */ + xReading |= I2CMasterDataGet( I2C_MASTER_BASE ); + + /* Finish the burst read. */ + I2CMasterControl( I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_RECEIVE_FINISH ); + uxState = mainI2C_READ_DONE; + break; + + case mainI2C_READ_DONE: /* Complete. */ + I2CMasterDataGet( I2C_MASTER_BASE ); + uxState = mainI2C_IDLE; + + /* Send the result to the co-routine. */ + crQUEUE_SEND_FROM_ISR( xADCQueue, &xReading, pdFALSE ); + break; + } +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ + for( ;; ) + { + vCoRoutineSchedule(); + } +} + diff --git a/20080212/Demo/CORTEX_LM3S102_Rowley/Demo3/vectors.s b/20080212/Demo/CORTEX_LM3S102_Rowley/Demo3/vectors.s new file mode 100644 index 000000000..c06b1fefd --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_Rowley/Demo3/vectors.s @@ -0,0 +1,120 @@ +/***************************************************************************** + * Copyright (c) 2006 Rowley Associates Limited. * + * * + * This file may be distributed under the terms of the License Agreement * + * provided with this software. * + * * + * THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE * + * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * + *****************************************************************************/ + .section .vectors, "ax" + .code 16 + .align 0 + .global _vectors + + .extern xPortPendSVHandler + .extern xPortSysTickHandler + .extern vI2C_ISR + .extern faultisr + +.macro DEFAULT_ISR_HANDLER name= + .thumb_func + .weak \name +\name: +1: b 1b /* endless loop */ +.endm + +_vectors: + .word __stack_end__ +#ifdef STARTUP_FROM_RESET + .word _start +#else + .word reset_wait +#endif /* STARTUP_FROM_RESET */ + .word NmiISR + .word FaultISR + .word 0 // Populate if using MemManage (MPU) + .word 0 // Populate if using Bus fault + .word 0 // Populate if using Usage fault + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 + .word 0 // Populate if using a debug monitor + .word 0 // Reserved + .word xPortPendSVHandler // Populate if using pendable service request + .word xPortSysTickHandler + // External interrupts start her + .word GPIO_Port_A_ISR + .word GPIO_Port_B_ISR + .word GPIO_Port_C_ISR + .word GPIO_Port_D_ISR + .word GPIO_Port_E_ISR + .word UART0_ISR + .word UART1_ISR + .word SSI_ISR + .word vI2C_ISR + .word PWM_Fault_ISR + .word PWM_Generator_0_ISR + .word PWM_Generator_1_ISR + .word PWM_Generator_2_ISR + .word QEI_ISR + .word ADC_Sequence_0_ISR + .word ADC_Sequence_1_ISR + .word ADC_Sequence_2_ISR + .word ADC_Sequence_3_ISR + .word Watchdog_timer_ISR + .word Timer0a_ISR + .word Timer0b_ISR + .word Timer1a_ISR + .word Timer1b_ISR + .word Timer2a_ISR + .word Timer2b_ISR + .word Analog_Comparator_0_ISR + .word Analog_Comparator_1_ISR + .word Analog_Comparator_2_ISR + .word System_Control_ISR + .word FLASH_Control_ISR + + .section .init, "ax" + .thumb_func + +DEFAULT_ISR_HANDLER NmiISR +DEFAULT_ISR_HANDLER FaultISR +DEFAULT_ISR_HANDLER SVCallISR +DEFAULT_ISR_HANDLER SysTickISR +DEFAULT_ISR_HANDLER GPIO_Port_A_ISR +DEFAULT_ISR_HANDLER GPIO_Port_B_ISR +DEFAULT_ISR_HANDLER GPIO_Port_C_ISR +DEFAULT_ISR_HANDLER GPIO_Port_D_ISR +DEFAULT_ISR_HANDLER GPIO_Port_E_ISR +DEFAULT_ISR_HANDLER UART0_ISR +DEFAULT_ISR_HANDLER UART1_ISR +DEFAULT_ISR_HANDLER SSI_ISR +DEFAULT_ISR_HANDLER I2C_ISR +DEFAULT_ISR_HANDLER PWM_Fault_ISR +DEFAULT_ISR_HANDLER PWM_Generator_0_ISR +DEFAULT_ISR_HANDLER PWM_Generator_1_ISR +DEFAULT_ISR_HANDLER PWM_Generator_2_ISR +DEFAULT_ISR_HANDLER QEI_ISR +DEFAULT_ISR_HANDLER ADC_Sequence_0_ISR +DEFAULT_ISR_HANDLER ADC_Sequence_1_ISR +DEFAULT_ISR_HANDLER ADC_Sequence_2_ISR +DEFAULT_ISR_HANDLER ADC_Sequence_3_ISR +DEFAULT_ISR_HANDLER Watchdog_timer_ISR +DEFAULT_ISR_HANDLER Timer0a_ISR +DEFAULT_ISR_HANDLER Timer0b_ISR +DEFAULT_ISR_HANDLER Timer1a_ISR +DEFAULT_ISR_HANDLER Timer1b_ISR +DEFAULT_ISR_HANDLER Timer2a_ISR +DEFAULT_ISR_HANDLER Timer2b_ISR +DEFAULT_ISR_HANDLER Analog_Comparator_0_ISR +DEFAULT_ISR_HANDLER Analog_Comparator_1_ISR +DEFAULT_ISR_HANDLER Analog_Comparator_2_ISR +DEFAULT_ISR_HANDLER System_Control_ISR +DEFAULT_ISR_HANDLER FLASH_Control_ISR + +#ifndef STARTUP_FROM_RESET +DEFAULT_ISR_HANDLER reset_wait +#endif /* STARTUP_FROM_RESET */ diff --git a/20080212/Demo/CORTEX_LM3S102_Rowley/RTOSDemo.hzp b/20080212/Demo/CORTEX_LM3S102_Rowley/RTOSDemo.hzp new file mode 100644 index 000000000..dc51429e9 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_Rowley/RTOSDemo.hzp @@ -0,0 +1,110 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/20080212/Demo/CORTEX_LM3S102_Rowley/RTOSDemo.hzs b/20080212/Demo/CORTEX_LM3S102_Rowley/RTOSDemo.hzs new file mode 100644 index 000000000..db7d6d992 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_Rowley/RTOSDemo.hzs @@ -0,0 +1,90 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/DriverLib.h b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/DriverLib.h new file mode 100644 index 000000000..3eb2ebcb6 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/DriverLib.h @@ -0,0 +1,20 @@ +#ifndef INCLUDE_DRIVER_LIB_H +#define INCLUDE_DRIVER_LIB_H + +#include "hw_ints.h" +#include "hw_uart.h" +#include "hw_memmap.h" +#include "hw_types.h" +#include "hw_nvic.h" +#include "hw_ssi.h" +#include "hw_i2c.h" + +#include "gpio.h" +#include "interrupt.h" +#include "sysctl.h" +#include "uart.h" +#include "ssi.h" +#include "pdc.h" +#include "i2c.h" + +#endif diff --git a/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/EULA.txt b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/EULA.txt new file mode 100644 index 000000000..cba31f7dc --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/EULA.txt @@ -0,0 +1,126 @@ +IMPORTANT. Read the following LMI Software License Agreement ("Agreement") +completely. + +LUMINARY MICRO SOFTWARE LICENSE AGREEMENT + + This is a legal agreement between you (either as an individual or as an +authorized representative of your employer) and Luminary Micro, Inc. ("LMI"). +It concerns your rights to use this file and any accompanying written materials +(the "Software"). In consideration for LMI allowing you to access the +Software, you are agreeing to be bound by the terms of this Agreement. If you +do not agree to all of the terms of this Agreement, do not download or use the +Software. If you change your mind later, stop using the Software and delete +all copies of the Software in your possession or control. Any copies of the +Software that you have already distributed, where permitted, and do not destroy +will continue to be governed by this Agreement. Your prior use will also +continue to be governed by this Agreement. + +1. LICENSE GRANT. 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If any provision of this Agreement is held for any +reason to be invalid or unenforceable, then the remaining provisions of this +Agreement will be unimpaired and, unless a modification or replacement of the +invalid or unenforceable provision is further held to deprive you or LMI of a +material benefit, in which case the Agreement will immediately terminate, the +invalid or unenforceable provision will be replaced with a provision that is +valid and enforceable and that comes closest to the intention underlying the +invalid or unenforceable provision. + +14. NO WAIVER. The waiver by LMI of any breach of any provision of this +Agreement will not operate or be construed as a waiver of any other or a +subsequent breach of the same or a different provision. diff --git a/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/comp.h b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/comp.h new file mode 100644 index 000000000..a4c307b8c --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/comp.h @@ -0,0 +1,112 @@ +//***************************************************************************** +// +// comp.h - Prototypes for the analog comparator driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __COMP_H__ +#define __COMP_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to ComparatorConfigure() as the ulConfig +// parameter. For each group (i.e. COMP_INT_xxx, COMP_ASRCP_xxx, etc.), one of +// the values may be selected and ORed together will values from the other +// groups. +// +//***************************************************************************** +#define COMP_INT_HIGH 0x00000010 // Interrupt when high +#define COMP_INT_LOW 0x00000000 // Interrupt when low +#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge +#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge +#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges +#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin +#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin +#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference +#define COMP_OUTPUT_NONE 0x00000000 // No comparator output +#define COMP_OUTPUT_NORMAL 0x00000100 // Comparator output normal +#define COMP_OUTPUT_INVERT 0x00000102 // Comparator output inverted + +//***************************************************************************** +// +// Values that can be passed to ComparatorSetRef() as the ulRef parameter. +// +//***************************************************************************** +#define COMP_REF_OFF 0x00000000 // Turn off the internal reference +#define COMP_REF_0V 0x00000300 // Internal reference of 0V +#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V +#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V +#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V +#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V +#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V +#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V +#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V +#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V +#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V +#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V +#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V +#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V +#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V +#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V +#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V +#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V +#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V +#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V +#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V +#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V +#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V +#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V +#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V +#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V +#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V +#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V +#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp, + unsigned long ulConfig); +extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef); +extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp); +extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp, + void (*pfnHandler)(void)); +extern void ComparatorIntUnregister(unsigned long ulBase, + unsigned long ulComp); +extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp, + tBoolean bMasked); +extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp); + +#ifdef __cplusplus +} +#endif + +#endif // __COMP_H__ diff --git a/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/cpu.h b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/cpu.h new file mode 100644 index 000000000..a93771bdb --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/cpu.h @@ -0,0 +1,40 @@ +//***************************************************************************** +// +// cpu.h - Prototypes for the CPU instruction wrapper functions. +// +// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __CPU_H__ +#define __CPU_H__ + +//***************************************************************************** +// +// Prototypes. +// +//***************************************************************************** +extern void CPUcpsid(void); +extern void CPUcpsie(void); +extern void CPUwfi(void); + +#endif // __CPU_H__ diff --git a/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/debug.h b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/debug.h new file mode 100644 index 000000000..2f259bd23 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/debug.h @@ -0,0 +1,56 @@ +//***************************************************************************** +// +// debug.h - Macros for assisting debug of the driver library. +// +// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __DEBUG_H__ +#define __DEBUG_H__ + +//***************************************************************************** +// +// Prototype for the function that is called when an invalid argument is passed +// to an API. This is only used when doing a DEBUG build. +// +//***************************************************************************** +extern void __error__(char *pcFilename, unsigned long ulLine); + +//***************************************************************************** +// +// The ASSERT macro, which does the actual assertion checking. Typically, this +// will be for procedure arguments. +// +//***************************************************************************** +#ifdef DEBUG +#define ASSERT(expr) { \ + if(!(expr)) \ + { \ + __error__(__FILE__, __LINE__); \ + } \ + } +#else +#define ASSERT(expr) +#endif + +#endif // __DEBUG_H__ diff --git a/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/flash.h b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/flash.h new file mode 100644 index 000000000..633254874 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/flash.h @@ -0,0 +1,75 @@ +//***************************************************************************** +// +// flash.h - Prototypes for the flash driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __FLASH_H__ +#define __FLASH_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to FlashProtectSet(), and returned by +// FlashProtectGet(). +// +//***************************************************************************** +typedef enum +{ + FlashReadWrite, // Flash can be read and written + FlashReadOnly, // Flash can only be read + FlashExecuteOnly // Flash can only be executed +} +tFlashProtection; + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern unsigned long FlashUsecGet(void); +extern void FlashUsecSet(unsigned long ulClocks); +extern long FlashErase(unsigned long ulAddress); +extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress, + unsigned long ulCount); +extern tFlashProtection FlashProtectGet(unsigned long ulAddress); +extern long FlashProtectSet(unsigned long ulAddress, + tFlashProtection eProtect); +extern long FlashProtectSave(void); +extern void FlashIntRegister(void (*pfnHandler)(void)); +extern void FlashIntUnregister(void); +extern void FlashIntEnable(unsigned long ulIntFlags); +extern void FlashIntDisable(unsigned long ulIntFlags); +extern unsigned long FlashIntGetStatus(tBoolean bMasked); +extern void FlashIntClear(unsigned long ulIntFlags); + +#ifdef __cplusplus +} +#endif + +#endif // __FLASH_H__ diff --git a/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/gpio.h b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/gpio.h new file mode 100644 index 000000000..cdc9a5b19 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/gpio.h @@ -0,0 +1,135 @@ +//***************************************************************************** +// +// gpio.h - Defines and Macros for GPIO API. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __GPIO_H__ +#define __GPIO_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following values define the bit field for the ucPins argument to several +// of the APIs. +// +//***************************************************************************** +#define GPIO_PIN_0 0x00000001 // GPIO pin 0 +#define GPIO_PIN_1 0x00000002 // GPIO pin 1 +#define GPIO_PIN_2 0x00000004 // GPIO pin 2 +#define GPIO_PIN_3 0x00000008 // GPIO pin 3 +#define GPIO_PIN_4 0x00000010 // GPIO pin 4 +#define GPIO_PIN_5 0x00000020 // GPIO pin 5 +#define GPIO_PIN_6 0x00000040 // GPIO pin 6 +#define GPIO_PIN_7 0x00000080 // GPIO pin 7 + +//***************************************************************************** +// +// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and +// returned from GPIODirModeGet. +// +//***************************************************************************** +#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input +#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output +#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function + +//***************************************************************************** +// +// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and +// returned from GPIOIntTypeGet. +// +//***************************************************************************** +#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge +#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge +#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges +#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level +#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level + +//***************************************************************************** +// +// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter, +// and returned by GPIOPadConfigGet in the *pulStrength parameter. +// +//***************************************************************************** +#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength +#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength +#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength +#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control + +//***************************************************************************** +// +// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter, +// and returned by GPIOPadConfigGet in the *pulPadType parameter. +// +//***************************************************************************** +#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull +#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up +#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down +#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain +#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up +#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down +#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulPinIO); +extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin); +extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulIntType); +extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin); +extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulStrength, + unsigned long ulPadType); +extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin, + unsigned long *pulStrength, + unsigned long *pulPadType); +extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins); +extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked); +extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPortIntRegister(unsigned long ulPort, + void (*pfIntHandler)(void)); +extern void GPIOPortIntUnregister(unsigned long ulPort); +extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, + unsigned char ucVal); +extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins); + +#ifdef __cplusplus +} +#endif + +#endif // __GPIO_H__ diff --git a/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_comp.h b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_comp.h new file mode 100644 index 000000000..81fb0b064 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_comp.h @@ -0,0 +1,113 @@ +//***************************************************************************** +// +// hw_comp.h - Macros used when accessing the comparator hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_COMP_H__ +#define __HW_COMP_H__ + +//***************************************************************************** +// +// The following define the offsets of the comparator registers. +// +//***************************************************************************** +#define COMP_O_MIS 0x00000000 // Interrupt status register +#define COMP_O_RIS 0x00000004 // Raw interrupt status register +#define COMP_O_INTEN 0x00000008 // Interrupt enable register +#define COMP_O_REFCTL 0x00000010 // Reference voltage control reg. +#define COMP_O_ACSTAT0 0x00000020 // Comp0 status register +#define COMP_O_ACCTL0 0x00000024 // Comp0 control register +#define COMP_O_ACSTAT1 0x00000040 // Comp1 status register +#define COMP_O_ACCTL1 0x00000044 // Comp1 control register + +//***************************************************************************** +// +// The following define the bit fields in the COMP_MIS, COMP_RIS, and +// COMP_INTEN registers. +// +//***************************************************************************** +#define COMP_INT_1 0x00000002 // Comp1 interrupt +#define COMP_INT_0 0x00000001 // Comp0 interrupt + +//***************************************************************************** +// +// The following define the bit fields in the COMP_REFCTL register. +// +//***************************************************************************** +#define COMP_REFCTL_EN 0x00000200 // Reference voltage enable +#define COMP_REFCTL_RNG 0x00000100 // Reference voltage range +#define COMP_REFCTL_VREF_MASK 0x0000000F // Reference voltage select mask +#define COMP_REFCTL_VREF_SHIFT 0 + +//***************************************************************************** +// +// The following define the bit fields in the COMP_ACSTAT0 and COMP_ACSTAT1 +// registers. +// +//***************************************************************************** +#define COMP_ACSTAT_OVAL 0x00000002 // Comparator output value + +//***************************************************************************** +// +// The following define the bit fields in the COMP_ACCTL0 and COMP_ACCTL1 +// registers. +// +//***************************************************************************** +#define COMP_ACCTL_TMASK 0x00000800 // Trigger enable +#define COMP_ACCTL_ASRCP_MASK 0x00000600 // Vin+ source select mask +#define COMP_ACCTL_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin +#define COMP_ACCTL_ASRCP_PIN0 0x00000200 // Comp0+ pin +#define COMP_ACCTL_ASRCP_REF 0x00000400 // Internal voltage reference +#define COMP_ACCTL_ASRCP_RES 0x00000600 // Reserved +#define COMP_ACCTL_OEN 0x00000100 // Comparator output enable +#define COMP_ACCTL_TSVAL 0x00000080 // Trigger polarity select +#define COMP_ACCTL_TSEN_MASK 0x00000060 // Trigger sense mask +#define COMP_ACCTL_TSEN_LEVEL 0x00000000 // Trigger is level sense +#define COMP_ACCTL_TSEN_FALL 0x00000020 // Trigger is falling edge +#define COMP_ACCTL_TSEN_RISE 0x00000040 // Trigger is rising edge +#define COMP_ACCTL_TSEN_BOTH 0x00000060 // Trigger is both edges +#define COMP_ACCTL_ISLVAL 0x00000010 // Interrupt polarity select +#define COMP_ACCTL_ISEN_MASK 0x0000000C // Interrupt sense mask +#define COMP_ACCTL_ISEN_LEVEL 0x00000000 // Interrupt is level sense +#define COMP_ACCTL_ISEN_FALL 0x00000004 // Interrupt is falling edge +#define COMP_ACCTL_ISEN_RISE 0x00000008 // Interrupt is rising edge +#define COMP_ACCTL_ISEN_BOTH 0x0000000C // Interrupt is both edges +#define COMP_ACCTL_CINV 0x00000002 // Comparator output invert + +//***************************************************************************** +// +// The following define the reset values for the comparator registers. +// +//***************************************************************************** +#define COMP_RV_MIS 0x00000000 // Interrupt status register +#define COMP_RV_RIS 0x00000000 // Raw interrupt status register +#define COMP_RV_INTEN 0x00000000 // Interrupt enable register +#define COMP_RV_REFCTL 0x00000000 // Reference voltage control reg. +#define COMP_RV_ACSTAT0 0x00000000 // Comp0 status register +#define COMP_RV_ACCTL0 0x00000000 // Comp0 control register +#define COMP_RV_ACSTAT1 0x00000000 // Comp1 status register +#define COMP_RV_ACCTL1 0x00000000 // Comp1 control register + +#endif // __HW_COMP_H__ diff --git a/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_flash.h b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_flash.h new file mode 100644 index 000000000..8dd755c2b --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_flash.h @@ -0,0 +1,141 @@ +//***************************************************************************** +// +// hw_flash.h - Macros used when accessing the flash controller. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_FLASH_H__ +#define __HW_FLASH_H__ + +//***************************************************************************** +// +// The following define the offsets of the FLASH registers. +// +//***************************************************************************** +#define FLASH_FMA 0x400FD000 // Memory address register +#define FLASH_FMD 0x400FD004 // Memory data register +#define FLASH_FMC 0x400FD008 // Memory control register +#define FLASH_FCRIS 0x400FD00c // Raw interrupt status register +#define FLASH_FCIM 0x400FD010 // Interrupt mask register +#define FLASH_FCMISC 0x400FD014 // Interrupt status register +#define FLASH_FMPRE 0x400FE130 // FLASH read protect register +#define FLASH_FMPPE 0x400FE134 // FLASH program protect register +#define FLASH_USECRL 0x400FE140 // uSec reload register + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FMC register. +// +//***************************************************************************** +#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask +#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key +#define FLASH_FMC_REG_MASK 0x00000F00 // Register select mask +#define FLASH_FMC_REG_UDFP 0x00000000 // Select FLASH protection register +#define FLASH_FMC_COMT 0x00000008 // Commit user register +#define FLASH_FMC_MERASE 0x00000004 // Mass erase FLASH +#define FLASH_FMC_ERASE 0x00000002 // Erase FLASH page +#define FLASH_FMC_WRITE 0x00000001 // Write FLASH word + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FCRIS register. +// +//***************************************************************************** +#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status +#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FCIM register. +// +//***************************************************************************** +#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask +#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FMIS register. +// +//***************************************************************************** +#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status +#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FMPRE and FLASH_FMPPE +// registers. +// +//***************************************************************************** +#define FLASH_FMP_BLOCK_31 0x80000000 // Enable for block 31 +#define FLASH_FMP_BLOCK_30 0x40000000 // Enable for block 30 +#define FLASH_FMP_BLOCK_29 0x20000000 // Enable for block 29 +#define FLASH_FMP_BLOCK_28 0x10000000 // Enable for block 28 +#define FLASH_FMP_BLOCK_27 0x08000000 // Enable for block 27 +#define FLASH_FMP_BLOCK_26 0x04000000 // Enable for block 26 +#define FLASH_FMP_BLOCK_25 0x02000000 // Enable for block 25 +#define FLASH_FMP_BLOCK_24 0x01000000 // Enable for block 24 +#define FLASH_FMP_BLOCK_23 0x00800000 // Enable for block 23 +#define FLASH_FMP_BLOCK_22 0x00400000 // Enable for block 22 +#define FLASH_FMP_BLOCK_21 0x00200000 // Enable for block 21 +#define FLASH_FMP_BLOCK_20 0x00100000 // Enable for block 20 +#define FLASH_FMP_BLOCK_19 0x00080000 // Enable for block 19 +#define FLASH_FMP_BLOCK_18 0x00040000 // Enable for block 18 +#define FLASH_FMP_BLOCK_17 0x00020000 // Enable for block 17 +#define FLASH_FMP_BLOCK_16 0x00010000 // Enable for block 16 +#define FLASH_FMP_BLOCK_15 0x00008000 // Enable for block 15 +#define FLASH_FMP_BLOCK_14 0x00004000 // Enable for block 14 +#define FLASH_FMP_BLOCK_13 0x00002000 // Enable for block 13 +#define FLASH_FMP_BLOCK_12 0x00001000 // Enable for block 12 +#define FLASH_FMP_BLOCK_11 0x00000800 // Enable for block 11 +#define FLASH_FMP_BLOCK_10 0x00000400 // Enable for block 10 +#define FLASH_FMP_BLOCK_9 0x00000200 // Enable for block 9 +#define FLASH_FMP_BLOCK_8 0x00000100 // Enable for block 8 +#define FLASH_FMP_BLOCK_7 0x00000080 // Enable for block 7 +#define FLASH_FMP_BLOCK_6 0x00000040 // Enable for block 6 +#define FLASH_FMP_BLOCK_5 0x00000020 // Enable for block 5 +#define FLASH_FMP_BLOCK_4 0x00000010 // Enable for block 4 +#define FLASH_FMP_BLOCK_3 0x00000008 // Enable for block 3 +#define FLASH_FMP_BLOCK_2 0x00000004 // Enable for block 2 +#define FLASH_FMP_BLOCK_1 0x00000002 // Enable for block 1 +#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0 + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_USECRL register. +// +//***************************************************************************** +#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec +#define FLASH_USECRL_SHIFT 0 + +//***************************************************************************** +// +// The erase size is the size of the FLASH block that is erased by an erase +// operation, and the protect size is the size of the FLASH block that is +// protected by each protection register. +// +//***************************************************************************** +#define FLASH_ERASE_SIZE 0x00000400 +#define FLASH_PROTECT_SIZE 0x00000800 + +#endif // __HW_FLASH_H__ diff --git a/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_gpio.h b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_gpio.h new file mode 100644 index 000000000..ddba2fd9d --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_gpio.h @@ -0,0 +1,95 @@ +//***************************************************************************** +// +// hw_gpio.h - Defines and Macros for GPIO hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_GPIO_H__ +#define __HW_GPIO_H__ + +//***************************************************************************** +// +// GPIO Register Offsets. +// +//***************************************************************************** +#define GPIO_O_DATA 0x00000000 // Data register. +#define GPIO_O_DIR 0x00000400 // Data direction register. +#define GPIO_O_IS 0x00000404 // Interrupt sense register. +#define GPIO_O_IBE 0x00000408 // Interrupt both edges register. +#define GPIO_O_IEV 0x0000040C // Intterupt event register. +#define GPIO_O_IM 0x00000410 // Interrupt mask register. +#define GPIO_O_RIS 0x00000414 // Raw interrupt status register. +#define GPIO_O_MIS 0x00000418 // Masked interrupt status reg. +#define GPIO_O_ICR 0x0000041C // Interrupt clear register. +#define GPIO_O_AFSEL 0x00000420 // Mode control select register. +#define GPIO_O_DR2R 0x00000500 // 2ma drive select register. +#define GPIO_O_DR4R 0x00000504 // 4ma drive select register. +#define GPIO_O_DR8R 0x00000508 // 8ma drive select register. +#define GPIO_O_ODR 0x0000050C // Open drain select register. +#define GPIO_O_PUR 0x00000510 // Pull up select register. +#define GPIO_O_PDR 0x00000514 // Pull down select register. +#define GPIO_O_SLR 0x00000518 // Slew rate control enable reg. +#define GPIO_O_DEN 0x0000051C // Digital input enable register. +#define GPIO_O_PeriphID0 0x00000FE0 // +#define GPIO_O_PeriphID1 0x00000FE4 // +#define GPIO_O_PeriphID2 0x00000FE8 // +#define GPIO_O_PeriphID3 0x00000FEC // +#define GPIO_O_PCellID0 0x00000FF0 // +#define GPIO_O_PCellID1 0x00000FF4 // +#define GPIO_O_PCellID2 0x00000FF8 // +#define GPIO_O_PCellID3 0x00000FFC // + +//***************************************************************************** +// +// GPIO Register reset values. +// +//***************************************************************************** +#define GPIO_RV_DATA 0x00000000 // Data register reset value. +#define GPIO_RV_DIR 0x00000000 // Data direction reg RV. +#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV. +#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV. +#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV. +#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV. +#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV. +#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV. +#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV. +#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV. +#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV. +#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV. +#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV. +#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV. +#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV. +#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV. +#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV. +#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV. +#define GPIO_RV_PeriphID0 0x00000061 // +#define GPIO_RV_PeriphID1 0x00000010 // +#define GPIO_RV_PeriphID2 0x00000004 // +#define GPIO_RV_PeriphID3 0x00000000 // +#define GPIO_RV_PCellID0 0x0000000D // +#define GPIO_RV_PCellID1 0x000000F0 // +#define GPIO_RV_PCellID2 0x00000005 // +#define GPIO_RV_PCellID3 0x000000B1 // + +#endif // __HW_GPIO_H__ diff --git a/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_i2c.h b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_i2c.h new file mode 100644 index 000000000..3e2e9ee93 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_i2c.h @@ -0,0 +1,157 @@ +//***************************************************************************** +// +// hw_i2c.h - Macros used when accessing the I2C master and slave hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_I2C_H__ +#define __HW_I2C_H__ + +//***************************************************************************** +// +// The following define the offsets of the I2C master registers. +// +//***************************************************************************** +#define I2C_MASTER_O_SA 0x00000000 // Slave address register +#define I2C_MASTER_O_CS 0x00000004 // Control and Status register +#define I2C_MASTER_O_DR 0x00000008 // Data register +#define I2C_MASTER_O_TPR 0x0000000C // Timer period register +#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register +#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register +#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg +#define I2C_MASTER_O_ICR 0x0000001c // Interrupt clear register +#define I2C_MASTER_O_CR 0x00000020 // Configuration register + +//***************************************************************************** +// +// The following define the offsets of the I2C slave registers. +// +//***************************************************************************** +#define I2C_SLAVE_O_OAR 0x00000000 // Own address register +#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register +#define I2C_SLAVE_O_DR 0x00000008 // Data register +#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register +#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register +#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg +#define I2C_SLAVE_O_ICR 0x00000018 // Interrupt clear register + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Control and Status +// register. +// +//***************************************************************************** +#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde +#define I2C_MASTER_CS_STOP 0x00000004 // Stop +#define I2C_MASTER_CS_START 0x00000002 // Start +#define I2C_MASTER_CS_RUN 0x00000001 // Run +#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy +#define I2C_MASTER_CS_IDLE 0x00000020 // Idle +#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration +#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged +#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged +#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred +#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data +#define I2C_MASTER_CS_ERR_MASK 0x0000001C + +//***************************************************************************** +// +// The following define values used in determining the contents of the I2C +// Master Timer Period register. +// +//***************************************************************************** +#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period +#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period +#define I2C_SCL_STANDARD 100000 // SCL standard frequency +#define I2C_SCL_FAST 400000 // SCL fast frequency + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Interrupt Mask +// register. +// +//***************************************************************************** +#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Raw Interrupt Status +// register. +// +//***************************************************************************** +#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Masked Interrupt +// Status register. +// +//***************************************************************************** +#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Configuration +// register. +// +//***************************************************************************** +#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable +#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable +#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Control/Status +// register. +// +//***************************************************************************** +#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device +#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received +#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Interrupt Mask +// register. +// +//***************************************************************************** +#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Raw Interrupt Status +// register. +// +//***************************************************************************** +#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Masked Interrupt +// Status register. +// +//***************************************************************************** +#define I2C_SLAVE_MIS_MIS 0x00000001 // Master masked interrupt status + +#endif // __HW_I2C_H__ diff --git a/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_ints.h b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_ints.h new file mode 100644 index 000000000..d32cec40b --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_ints.h @@ -0,0 +1,82 @@ +//***************************************************************************** +// +// hw_ints.h - Macros that define the interrupt assignment on Stellaris. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_INTS_H__ +#define __HW_INTS_H__ + +//***************************************************************************** +// +// The following define the fault assignments. +// +//***************************************************************************** +#define FAULT_NMI 2 // NMI fault +#define FAULT_HARD 3 // Hard fault +#define FAULT_MPU 4 // MPU fault +#define FAULT_BUS 5 // Bus fault +#define FAULT_USAGE 6 // Usage fault +#define FAULT_SVCALL 11 // SVCall +#define FAULT_DEBUG 12 // Debug monitor +#define FAULT_PENDSV 14 // PendSV +#define FAULT_SYSTICK 15 // System Tick + +//***************************************************************************** +// +// The following define the interrupt assignments. +// +//***************************************************************************** +#define INT_GPIOA 16 // GPIO Port A +#define INT_GPIOB 17 // GPIO Port B +#define INT_GPIOC 18 // GPIO Port C +#define INT_UART0 21 // UART0 Rx and Tx +#define INT_SSI 23 // SSI Rx and Tx +#define INT_I2C 24 // I2C Master and Slave +#define INT_WATCHDOG 34 // Watchdog timer +#define INT_TIMER0A 35 // Timer 0 subtimer A +#define INT_TIMER0B 36 // Timer 0 subtimer B +#define INT_TIMER1A 37 // Timer 1 subtimer A +#define INT_TIMER1B 38 // Timer 1 subtimer B +#define INT_COMP0 41 // Analog Comparator 0 +#define INT_COMP1 42 // Analog Comparator 1 +#define INT_SYSCTL 44 // System Control (PLL, OSC, BO) +#define INT_FLASH 45 // FLASH Control + +//***************************************************************************** +// +// The total number of interrupts. +// +//***************************************************************************** +#define NUM_INTERRUPTS 46 + +//***************************************************************************** +// +// The total number of priority levels. +// +//***************************************************************************** +#define NUM_PRIORITY 8 +#define NUM_PRIORITY_BITS 3 + +#endif // __HW_INTS_H__ diff --git a/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_memmap.h b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_memmap.h new file mode 100644 index 000000000..bef5dc618 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_memmap.h @@ -0,0 +1,57 @@ +//***************************************************************************** +// +// hw_memmap.h - Macros defining the memory map of Stellaris. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_MEMMAP_H__ +#define __HW_MEMMAP_H__ + +//***************************************************************************** +// +// The following define the base address of the memories and peripherals. +// +//***************************************************************************** +#define FLASH_BASE 0x00000000 // FLASH memory +#define SRAM_BASE 0x20000000 // SRAM memory +#define WATCHDOG_BASE 0x40000000 // Watchdog +#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A +#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B +#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C +#define SSI_BASE 0x40008000 // SSI +#define UART0_BASE 0x4000C000 // UART0 +#define I2C_MASTER_BASE 0x40020000 // I2C Master +#define I2C_SLAVE_BASE 0x40020800 // I2C Slave +#define TIMER0_BASE 0x40030000 // Timer0 +#define TIMER1_BASE 0x40031000 // Timer1 +#define COMP_BASE 0x4003C000 // Analog comparators +#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller +#define SYSCTL_BASE 0x400FE000 // System Control +#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell +#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace +#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint +#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl +#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit + +#endif // __HW_MEMMAP_H__ diff --git a/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_nvic.h b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_nvic.h new file mode 100644 index 000000000..77dfe716a --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_nvic.h @@ -0,0 +1,830 @@ +//***************************************************************************** +// +// hw_nvic.h - Macros used when accessing the NVIC hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_NVIC_H__ +#define __HW_NVIC_H__ + +//***************************************************************************** +// +// The following define the addresses of the NVIC registers. +// +//***************************************************************************** +#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg. +#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg. +#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register +#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register +#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg. +#define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register +#define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg. +#define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register +#define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg. +#define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register +#define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register +#define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register +#define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register +#define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register +#define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register +#define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register +#define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register +#define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register +#define NVIC_CPUID 0xE000ED00 // CPUID Base Register +#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register +#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register +#define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg. +#define NVIC_SYS_CTRL 0xE000ED10 // System Control Register +#define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register +#define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority +#define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority +#define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority +#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State +#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg. +#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register +#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register +#define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register +#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register +#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register +#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register +#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register +#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register +#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg. +#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg. +#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select +#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data +#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control +#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg. + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_INT_TYPE register. +// +//***************************************************************************** +#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) +#define NVIC_INT_TYPE_LINES_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_CTRL register. +// +//***************************************************************************** +#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag +#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source +#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable +#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_RELOAD register. +// +//***************************************************************************** +#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value +#define NVIC_ST_RELOAD_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_CURRENT register. +// +//***************************************************************************** +#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value +#define NVIC_ST_CURRENT_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_CAL register. +// +//***************************************************************************** +#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock +#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew +#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value +#define NVIC_ST_CAL_ONEMS_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_EN0 register. +// +//***************************************************************************** +#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable +#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable +#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable +#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable +#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable +#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable +#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable +#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable +#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable +#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable +#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable +#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable +#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable +#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable +#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable +#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable +#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable +#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable +#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable +#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable +#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable +#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable +#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable +#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable +#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable +#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable +#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable +#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable +#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable +#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable +#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable +#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DIS0 register. +// +//***************************************************************************** +#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable +#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable +#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable +#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable +#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable +#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable +#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable +#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable +#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable +#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable +#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable +#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable +#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable +#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable +#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable +#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable +#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable +#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable +#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable +#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable +#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable +#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable +#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable +#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable +#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable +#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable +#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable +#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable +#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable +#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable +#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable +#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PEND0 register. +// +//***************************************************************************** +#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend +#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend +#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend +#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend +#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend +#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend +#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend +#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend +#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend +#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend +#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend +#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend +#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend +#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend +#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend +#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend +#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend +#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend +#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend +#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend +#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend +#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend +#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend +#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend +#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend +#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend +#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend +#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend +#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend +#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend +#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend +#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_UNPEND0 register. +// +//***************************************************************************** +#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend +#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend +#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend +#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend +#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend +#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend +#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend +#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend +#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend +#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend +#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend +#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend +#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend +#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend +#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend +#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend +#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend +#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend +#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend +#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend +#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend +#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend +#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend +#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend +#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend +#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend +#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend +#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend +#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend +#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend +#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend +#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ACTIVE0 register. +// +//***************************************************************************** +#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active +#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active +#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active +#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active +#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active +#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active +#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active +#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active +#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active +#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active +#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active +#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active +#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active +#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active +#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active +#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active +#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active +#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active +#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active +#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active +#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active +#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active +#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active +#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active +#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active +#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active +#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active +#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active +#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active +#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active +#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active +#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI0 register. +// +//***************************************************************************** +#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask +#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask +#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask +#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask +#define NVIC_PRI0_INT3_S 24 +#define NVIC_PRI0_INT2_S 16 +#define NVIC_PRI0_INT1_S 8 +#define NVIC_PRI0_INT0_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI1 register. +// +//***************************************************************************** +#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask +#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask +#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask +#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask +#define NVIC_PRI1_INT7_S 24 +#define NVIC_PRI1_INT6_S 16 +#define NVIC_PRI1_INT5_S 8 +#define NVIC_PRI1_INT4_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI2 register. +// +//***************************************************************************** +#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask +#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask +#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask +#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask +#define NVIC_PRI2_INT11_S 24 +#define NVIC_PRI2_INT10_S 16 +#define NVIC_PRI2_INT9_S 8 +#define NVIC_PRI2_INT8_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI3 register. +// +//***************************************************************************** +#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask +#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask +#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask +#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask +#define NVIC_PRI3_INT15_S 24 +#define NVIC_PRI3_INT14_S 16 +#define NVIC_PRI3_INT13_S 8 +#define NVIC_PRI3_INT12_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI4 register. +// +//***************************************************************************** +#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask +#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask +#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask +#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask +#define NVIC_PRI4_INT19_S 24 +#define NVIC_PRI4_INT18_S 16 +#define NVIC_PRI4_INT17_S 8 +#define NVIC_PRI4_INT16_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI5 register. +// +//***************************************************************************** +#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask +#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask +#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask +#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask +#define NVIC_PRI5_INT23_S 24 +#define NVIC_PRI5_INT22_S 16 +#define NVIC_PRI5_INT21_S 8 +#define NVIC_PRI5_INT20_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI6 register. +// +//***************************************************************************** +#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask +#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask +#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask +#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask +#define NVIC_PRI6_INT27_S 24 +#define NVIC_PRI6_INT26_S 16 +#define NVIC_PRI6_INT25_S 8 +#define NVIC_PRI6_INT24_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI7 register. +// +//***************************************************************************** +#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask +#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask +#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask +#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask +#define NVIC_PRI7_INT31_S 24 +#define NVIC_PRI7_INT30_S 16 +#define NVIC_PRI7_INT29_S 8 +#define NVIC_PRI7_INT28_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_CPUID register. +// +//***************************************************************************** +#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer +#define NVIC_CPUID_VAR_M 0x00F00000 // Variant +#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number +#define NVIC_CPUID_REV_M 0x0000000F // Revision + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_INT_CTRL register. +// +//***************************************************************************** +#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI +#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV +#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV +#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling +#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending +#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception +#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base +#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception +#define NVIC_INT_CTRL_VEC_PEN_S 12 +#define NVIC_INT_CTRL_VEC_ACT_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_VTABLE register. +// +//***************************************************************************** +#define NVIC_VTABLE_BASE 0x20000000 // Vector table base +#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset +#define NVIC_VTABLE_OFFSET_S 8 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_APINT register. +// +//***************************************************************************** +#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask +#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key +#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess +#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group +#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split +#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split +#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split +#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split +#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split +#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split +#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split +#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split +#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request +#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info +#define NVIC_APINT_VECT_RESET 0x00000001 // System reset + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend +#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable +#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_CFG_CTRL register. +// +//***************************************************************************** +#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault +#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0 +#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access +#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger +#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger +#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_PRI1 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler +#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler +#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler +#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler +#define NVIC_SYS_PRI1_USAGE_S 16 +#define NVIC_SYS_PRI1_BUS_S 8 +#define NVIC_SYS_PRI1_MEM_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_PRI2 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler +#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers +#define NVIC_SYS_PRI2_SVC_S 24 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_PRI3 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler +#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler +#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler +#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler +#define NVIC_SYS_PRI3_TICK_S 24 +#define NVIC_SYS_PRI3_PENDSV_S 16 +#define NVIC_SYS_PRI3_DEBUG_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_HND_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable +#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable +#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable +#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended +#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended +#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active +#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active +#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active +#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active +#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active +#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active +#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_FAULT_STAT register. +// +//***************************************************************************** +#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault +#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault +#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault +#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault +#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault +#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault +#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid +#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault +#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault +#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error +#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error +#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault +#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid +#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation +#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation +#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation +#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_HFAULT_STAT register. +// +//***************************************************************************** +#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event +#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler +#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DEBUG_STAT register. +// +//***************************************************************************** +#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted +#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch +#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match +#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction +#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MM_ADDR register. +// +//***************************************************************************** +#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address +#define NVIC_MM_ADDR_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_FAULT_ADDR register. +// +//***************************************************************************** +#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address +#define NVIC_FAULT_ADDR_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_EXC_STACK register. +// +//***************************************************************************** +#define NVIC_EXC_STACK_DEEP 0x00000001 // Exception stack + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_EXC_NUM register. +// +//***************************************************************************** +#define NVIC_EXC_NUM_M 0x000003FF // Exception number +#define NVIC_EXC_NUM_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_COPRO register. +// +//***************************************************************************** +#define NVIC_COPRO_15_M 0xC0000000 // Coprocessor 15 access mask +#define NVIC_COPRO_15_DENIED 0x00000000 // Coprocessor 15 access denied +#define NVIC_COPRO_15_PRIV 0x40000000 // Coprocessor 15 privileged addess +#define NVIC_COPRO_15_FULL 0xC0000000 // Coprocessor 15 full access +#define NVIC_COPRO_14_M 0x30000000 // Coprocessor 14 access mask +#define NVIC_COPRO_14_DENIED 0x00000000 // Coprocessor 14 access denied +#define NVIC_COPRO_14_PRIV 0x10000000 // Coprocessor 14 privileged addess +#define NVIC_COPRO_14_FULL 0x30000000 // Coprocessor 14 full access +#define NVIC_COPRO_13_M 0x0C000000 // Coprocessor 13 access mask +#define NVIC_COPRO_13_DENIED 0x00000000 // Coprocessor 13 access denied +#define NVIC_COPRO_13_PRIV 0x04000000 // Coprocessor 13 privileged addess +#define NVIC_COPRO_13_FULL 0x0C000000 // Coprocessor 13 full access +#define NVIC_COPRO_12_M 0x03000000 // Coprocessor 12 access mask +#define NVIC_COPRO_12_DENIED 0x00000000 // Coprocessor 12 access denied +#define NVIC_COPRO_12_PRIV 0x01000000 // Coprocessor 12 privileged addess +#define NVIC_COPRO_12_FULL 0x03000000 // Coprocessor 12 full access +#define NVIC_COPRO_11_M 0x00C00000 // Coprocessor 11 access mask +#define NVIC_COPRO_11_DENIED 0x00000000 // Coprocessor 11 access denied +#define NVIC_COPRO_11_PRIV 0x00400000 // Coprocessor 11 privileged addess +#define NVIC_COPRO_11_FULL 0x00C00000 // Coprocessor 11 full access +#define NVIC_COPRO_10_M 0x00300000 // Coprocessor 10 access mask +#define NVIC_COPRO_10_DENIED 0x00000000 // Coprocessor 10 access denied +#define NVIC_COPRO_10_PRIV 0x00100000 // Coprocessor 10 privileged addess +#define NVIC_COPRO_10_FULL 0x00300000 // Coprocessor 10 full access +#define NVIC_COPRO_9_M 0x000C0000 // Coprocessor 9 access mask +#define NVIC_COPRO_9_DENIED 0x00000000 // Coprocessor 9 access denied +#define NVIC_COPRO_9_PRIV 0x00040000 // Coprocessor 9 privileged addess +#define NVIC_COPRO_9_FULL 0x000C0000 // Coprocessor 9 full access +#define NVIC_COPRO_8_M 0x00030000 // Coprocessor 8 access mask +#define NVIC_COPRO_8_DENIED 0x00000000 // Coprocessor 8 access denied +#define NVIC_COPRO_8_PRIV 0x00010000 // Coprocessor 8 privileged addess +#define NVIC_COPRO_8_FULL 0x00030000 // Coprocessor 8 full access +#define NVIC_COPRO_7_M 0x0000C000 // Coprocessor 7 access mask +#define NVIC_COPRO_7_DENIED 0x00000000 // Coprocessor 7 access denied +#define NVIC_COPRO_7_PRIV 0x00004000 // Coprocessor 7 privileged addess +#define NVIC_COPRO_7_FULL 0x0000C000 // Coprocessor 7 full access +#define NVIC_COPRO_6_M 0x00003000 // Coprocessor 6 access mask +#define NVIC_COPRO_6_DENIED 0x00000000 // Coprocessor 6 access denied +#define NVIC_COPRO_6_PRIV 0x00001000 // Coprocessor 6 privileged addess +#define NVIC_COPRO_6_FULL 0x00003000 // Coprocessor 6 full access +#define NVIC_COPRO_5_M 0x00000C00 // Coprocessor 5 access mask +#define NVIC_COPRO_5_DENIED 0x00000000 // Coprocessor 5 access denied +#define NVIC_COPRO_5_PRIV 0x00000400 // Coprocessor 5 privileged addess +#define NVIC_COPRO_5_FULL 0x00000C00 // Coprocessor 5 full access +#define NVIC_COPRO_4_M 0x00000300 // Coprocessor 4 access mask +#define NVIC_COPRO_4_DENIED 0x00000000 // Coprocessor 4 access denied +#define NVIC_COPRO_4_PRIV 0x00000100 // Coprocessor 4 privileged addess +#define NVIC_COPRO_4_FULL 0x00000300 // Coprocessor 4 full access +#define NVIC_COPRO_3_M 0x000000C0 // Coprocessor 3 access mask +#define NVIC_COPRO_3_DENIED 0x00000000 // Coprocessor 3 access denied +#define NVIC_COPRO_3_PRIV 0x00000040 // Coprocessor 3 privileged addess +#define NVIC_COPRO_3_FULL 0x000000C0 // Coprocessor 3 full access +#define NVIC_COPRO_2_M 0x00000030 // Coprocessor 2 access mask +#define NVIC_COPRO_2_DENIED 0x00000000 // Coprocessor 2 access denied +#define NVIC_COPRO_2_PRIV 0x00000010 // Coprocessor 2 privileged addess +#define NVIC_COPRO_2_FULL 0x00000030 // Coprocessor 2 full access +#define NVIC_COPRO_1_M 0x0000000C // Coprocessor 1 access mask +#define NVIC_COPRO_1_DENIED 0x00000000 // Coprocessor 1 access denied +#define NVIC_COPRO_1_PRIV 0x00000004 // Coprocessor 1 privileged addess +#define NVIC_COPRO_1_FULL 0x0000000C // Coprocessor 1 full access +#define NVIC_COPRO_0_M 0x00000003 // Coprocessor 0 access mask +#define NVIC_COPRO_0_DENIED 0x00000000 // Coprocessor 0 access denied +#define NVIC_COPRO_0_PRIV 0x00000001 // Coprocessor 0 privileged addess +#define NVIC_COPRO_0_FULL 0x00000003 // Coprocessor 0 full access + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_TYPE register. +// +//***************************************************************************** +#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions +#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions +#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU +#define NVIC_MPU_TYPE_IREGION_S 16 +#define NVIC_MPU_TYPE_DREGION_S 8 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_CTRL register. +// +//***************************************************************************** +#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults +#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_NUMBER register. +// +//***************************************************************************** +#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access +#define NVIC_MPU_NUMBER_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_BASE register. +// +//***************************************************************************** +#define NVIC_MPU_BASE_ADDR_M 0xFFFFFF00 // Base address +#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid +#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number +#define NVIC_MPU_BASE_ADDR_S 8 +#define NVIC_MPU_BASE_REGION_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_ATTR register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR_ATTRS 0xFFFF0000 // Attributes +#define NVIC_MPU_ATTR_SRD 0x0000FF00 // Sub-region disable +#define NVIC_MPU_ATTR_SZENABLE 0x000000FF // Region size + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_CTRL register. +// +//***************************************************************************** +#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask +#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key +#define NVIC_DBG_CTRL_MON_PEND 0x00008000 // Pend the monitor +#define NVIC_DBG_CTRL_MON_REQ 0x00004000 // Monitor request +#define NVIC_DBG_CTRL_MON_EN 0x00002000 // Debug monitor enable +#define NVIC_DBG_CTRL_MONSTEP 0x00001000 // Monitor step the core +#define NVIC_DBG_CTRL_S_SLEEP 0x00000400 // Core is sleeping +#define NVIC_DBG_CTRL_S_HALT 0x00000200 // Core status on halt +#define NVIC_DBG_CTRL_S_REGRDY 0x00000100 // Register read/write available +#define NVIC_DBG_CTRL_S_LOCKUP 0x00000080 // Core is locked up +#define NVIC_DBG_CTRL_C_RESET 0x00000010 // Reset the core +#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping +#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core +#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core +#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_XFER register. +// +//***************************************************************************** +#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read +#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register +#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 +#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 +#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 +#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 +#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 +#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 +#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 +#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 +#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 +#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 +#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 +#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 +#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 +#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 +#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 +#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 +#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register +#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP +#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP +#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP +#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_DATA register. +// +//***************************************************************************** +#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache +#define NVIC_DBG_DATA_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_INT register. +// +//***************************************************************************** +#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault +#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors +#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error +#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state +#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check +#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error +#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault +#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status +#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset +#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending +#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SW_TRIG register. +// +//***************************************************************************** +#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger +#define NVIC_SW_TRIG_INTID_S 0 + +#endif // __HW_NVIC_H__ diff --git a/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_ssi.h b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_ssi.h new file mode 100644 index 000000000..37472329f --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_ssi.h @@ -0,0 +1,113 @@ +//***************************************************************************** +// +// hw_ssi.h - Macros used when accessing the SSI hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_SSI_H__ +#define __HW_SSI_H__ + +//***************************************************************************** +// +// The following define the offsets of the SSI registers. +// +//***************************************************************************** +#define SSI_O_CR0 0x00000000 // Control register 0 +#define SSI_O_CR1 0x00000004 // Control register 1 +#define SSI_O_DR 0x00000008 // Data register +#define SSI_O_SR 0x0000000C // Status register +#define SSI_O_CPSR 0x00000010 // Clock prescale register +#define SSI_O_IM 0x00000014 // Int mask set and clear register +#define SSI_O_RIS 0x00000018 // Raw interrupt register +#define SSI_O_MIS 0x0000001C // Masked interrupt register +#define SSI_O_ICR 0x00000020 // Interrupt clear register + +//***************************************************************************** +// +// The following define the bit fields in the SSI Control register 0. +// +//***************************************************************************** +#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate +#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase +#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity +#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask +#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format +#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format +#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format +#define SSI_CR0_DSS 0x0000000F // Data size select +#define SSI_CR0_DSS_4 0x00000003 // 4 bit data +#define SSI_CR0_DSS_5 0x00000004 // 5 bit data +#define SSI_CR0_DSS_6 0x00000005 // 6 bit data +#define SSI_CR0_DSS_7 0x00000006 // 7 bit data +#define SSI_CR0_DSS_8 0x00000007 // 8 bit data +#define SSI_CR0_DSS_9 0x00000008 // 9 bit data +#define SSI_CR0_DSS_10 0x00000009 // 10 bit data +#define SSI_CR0_DSS_11 0x0000000A // 11 bit data +#define SSI_CR0_DSS_12 0x0000000B // 12 bit data +#define SSI_CR0_DSS_13 0x0000000C // 13 bit data +#define SSI_CR0_DSS_14 0x0000000D // 14 bit data +#define SSI_CR0_DSS_15 0x0000000E // 15 bit data +#define SSI_CR0_DSS_16 0x0000000F // 16 bit data + +//***************************************************************************** +// +// The following define the bit fields in the SSI Control register 1. +// +//***************************************************************************** +#define SSI_CR1_SOD 0x00000008 // Slave mode output disable +#define SSI_CR1_MS 0x00000004 // Master or slave mode select +#define SSI_CR1_SSE 0x00000002 // Sync serial port enable +#define SSI_CR1_LBM 0x00000001 // Loopback mode + +//***************************************************************************** +// +// The following define the bit fields in the SSI Status register +// +//***************************************************************************** +#define SSI_SR_BSY 0x00000010 // SSI busy +#define SSI_SR_RFF 0x00000008 // RX FIFO full +#define SSI_SR_RNE 0x00000004 // RX FIFO not empty +#define SSI_SR_TNF 0x00000002 // TX FIFO not full +#define SSI_SR_TFE 0x00000001 // TX FIFO empty + +//***************************************************************************** +// +// The following define information concerning the SSI Data register. +// +//***************************************************************************** +#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO +#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO + +//***************************************************************************** +// +// The following define the bit fields in the interrupt mask set and clear, +// raw interrupt, masked interrupt, and interrupt clear registers. +// +//***************************************************************************** +#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt +#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt +#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt +#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt + +#endif // __HW_SSI_H__ diff --git a/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_sysctl.h b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_sysctl.h new file mode 100644 index 000000000..044fec21d --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_sysctl.h @@ -0,0 +1,325 @@ +//***************************************************************************** +// +// hw_sysctl.h - Macros used when accessing the system control hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_SYSCTL_H__ +#define __HW_SYSCTL_H__ + +//***************************************************************************** +// +// The following define the offsets of the system control registers. +// +//***************************************************************************** +#define SYSCTL_DID0 0x400fe000 // Device identification register 0 +#define SYSCTL_DID1 0x400fe004 // Device identification register 1 +#define SYSCTL_DC0 0x400fe008 // Device capabilities register 0 +#define SYSCTL_DC1 0x400fe010 // Device capabilities register 1 +#define SYSCTL_DC2 0x400fe014 // Device capabilities register 2 +#define SYSCTL_DC3 0x400fe018 // Device capabilities register 3 +#define SYSCTL_DC4 0x400fe01C // Device capabilities register 4 +#define SYSCTL_PBORCTL 0x400fe030 // POR/BOR reset control register +#define SYSCTL_LDOPCTL 0x400fe034 // LDO power control register +#define SYSCTL_SRCR0 0x400fe040 // Software reset control reg 0 +#define SYSCTL_SRCR1 0x400fe044 // Software reset control reg 1 +#define SYSCTL_SRCR2 0x400fe048 // Software reset control reg 2 +#define SYSCTL_RIS 0x400fe050 // Raw interrupt status register +#define SYSCTL_IMC 0x400fe054 // Interrupt mask/control register +#define SYSCTL_MISC 0x400fe058 // Interrupt status register +#define SYSCTL_RESC 0x400fe05c // Reset cause register +#define SYSCTL_RCC 0x400fe060 // Run-mode clock config register +#define SYSCTL_PLLCFG 0x400fe064 // PLL configuration register +#define SYSCTL_RCGC0 0x400fe100 // Run-mode clock gating register 0 +#define SYSCTL_RCGC1 0x400fe104 // Run-mode clock gating register 1 +#define SYSCTL_RCGC2 0x400fe108 // Run-mode clock gating register 2 +#define SYSCTL_SCGC0 0x400fe110 // Sleep-mode clock gating reg 0 +#define SYSCTL_SCGC1 0x400fe114 // Sleep-mode clock gating reg 1 +#define SYSCTL_SCGC2 0x400fe118 // Sleep-mode clock gating reg 2 +#define SYSCTL_DCGC0 0x400fe120 // Deep Sleep-mode clock gate reg 0 +#define SYSCTL_DCGC1 0x400fe124 // Deep Sleep-mode clock gate reg 1 +#define SYSCTL_DCGC2 0x400fe128 // Deep Sleep-mode clock gate reg 2 +#define SYSCTL_CLKVCLR 0x400fe150 // Clock verifcation clear register +#define SYSCTL_LDOARST 0x400fe160 // LDO reset control register + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DID0 register. +// +//***************************************************************************** +#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask +#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A +#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B +#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask +#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0 +#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DID1 register. +// +//***************************************************************************** +#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask +#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask +#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family +#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask +#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101 +#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102 +#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask +#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C) +#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C) +#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask +#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC +#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant +#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask +#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified) +#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified) +#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified +#define SYSCTL_DID1_PRTNO_SHIFT 16 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC0 register. +// +//***************************************************************************** +#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask +#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2kB of SRAM +#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask +#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8kB of flash + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC1 register. +// +//***************************************************************************** +#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask +#define SYSCTL_DC1_MPU 0x00000080 // Cortex M3 MPU present +#define SYSCTL_DC1_PLL 0x00000010 // PLL present +#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present +#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present +#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present +#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC2 register. +// +//***************************************************************************** +#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present +#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present +#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present +#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present +#define SYSCTL_DC2_I2C 0x00001000 // I2C present +#define SYSCTL_DC2_SSI 0x00000010 // SSI present +#define SYSCTL_DC2_UART0 0x00000001 // UART 0 present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC3 register. +// +//***************************************************************************** +#define SYSCTL_DC3_32KHZ 0x80000000 // 32kHz pin present +#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present +#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present +#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present +#define SYSCTL_DC3_C0O 0x00000100 // C0o pin present +#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present +#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC4 register. +// +//***************************************************************************** +#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present +#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present +#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_PBORCTL register. +// +//***************************************************************************** +#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer +#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset +#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise +#define SYSCTL_PBORCTL_BOR_SH 2 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_LDOPCTL register. +// +//***************************************************************************** +#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask +#define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V +#define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V +#define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V +#define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V +#define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V +#define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V +#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V +#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V +#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V +#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V +#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_SRCR0, SYSCTL_RCGC0, +// SYSCTL_SCGC0, and SYSCTL_DCGC0 registers. +// +//***************************************************************************** +#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_SRCR1, SYSCTL_RCGC1, +// SYSCTL_SCGC1, and SYSCTL_DCGC1 registers. +// +//***************************************************************************** +#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1 +#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0 +#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1 +#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0 +#define SYSCTL_SET1_I2C 0x00001000 // I2C module +#define SYSCTL_SET1_SSI 0x00000010 // SSI module +#define SYSCTL_SET1_UART0 0x00000001 // UART module 0 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_SRCR2, SYSCTL_RCGC2, +// SYSCTL_SCGC2, and SYSCTL_DCGC2 registers. +// +//***************************************************************************** +#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module +#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module +#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_RIS, SYSCTL_IMC, and +// SYSCTL_IMS registers. +// +//***************************************************************************** +#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt +#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt +#define SYSCTL_INT_BOSC_FAIL 0x00000010 // Boot oscillator failure int +#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int +#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt +#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt +#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_RESC register. +// +//***************************************************************************** +#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset +#define SYSCTL_RESC_SW 0x00000010 // Software reset +#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset +#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset +#define SYSCTL_RESC_POR 0x00000002 // Power on reset +#define SYSCTL_RESC_EXT 0x00000001 // External reset + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_RCC register. +// +//***************************************************************************** +#define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating +#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider +#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2 +#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3 +#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4 +#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5 +#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6 +#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7 +#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8 +#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9 +#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10 +#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11 +#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12 +#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13 +#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14 +#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15 +#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16 +#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider +#define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down +#define SYSCTL_RCC_OE 0x00001000 // PLL output enable +#define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass +#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable +#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc +#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal +#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864MHz crystal +#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4MHz crystal +#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal +#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal +#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal +#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal +#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal +#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal +#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal +#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal +#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal +#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select +#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator +#define SYSCTL_RCC_OSCSRC_BOOT 0x00000010 // Use the boot oscillator +#define SYSCTL_RCC_OSCSRC_BOOT4 0x00000020 // Use the boot oscillator / 4 +#define SYSCTL_RCC_BOSCVER 0x00000008 // Boot osc. verification timer en +#define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en +#define SYSCTL_RCC_BOSCDIS 0x00000002 // Boot oscillator disable +#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable +#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field +#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field +#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_PLLCFG register. +// +//***************************************************************************** +#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider +#define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1 +#define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2 +#define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4 +#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier +#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider +#define SYSCTL_PLLCFG_F_SHIFT 5 +#define SYSCTL_PLLCFG_R_SHIFT 0 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_CLKVCLR register. +// +//***************************************************************************** +#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_LDOARST register. +// +//***************************************************************************** +#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device + +#endif // __HW_SYSCTL_H__ diff --git a/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_timer.h b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_timer.h new file mode 100644 index 000000000..9bad906b2 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_timer.h @@ -0,0 +1,233 @@ +//***************************************************************************** +// +// hw_timer.h - Defines and macros used when accessing the timer. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_TIMER_H__ +#define __HW_TIMER_H__ + +//***************************************************************************** +// +// The following define the offsets of the timer registers. +// +//***************************************************************************** +#define TIMER_O_CFG 0x00000000 // Configuration register +#define TIMER_O_TAMR 0x00000004 // TimerA mode register +#define TIMER_O_TBMR 0x00000008 // TimerB mode register +#define TIMER_O_CTL 0x0000000C // Control register +#define TIMER_O_IMR 0x00000018 // Interrupt mask register +#define TIMER_O_RIS 0x0000001C // Interrupt status register +#define TIMER_O_MIS 0x00000020 // Masked interrupt status reg. +#define TIMER_O_ICR 0x00000024 // Interrupt clear register +#define TIMER_O_TAILR 0x00000028 // TimerA interval load register +#define TIMER_O_TBILR 0x0000002C // TimerB interval load register +#define TIMER_O_TAMATCHR 0x00000030 // TimerA match register +#define TIMER_O_TBMATCHR 0x00000034 // TimerB match register +#define TIMER_O_TAPR 0x00000038 // TimerA prescale register +#define TIMER_O_TBPR 0x0000003C // TimerB prescale register +#define TIMER_O_TAPMR 0x00000040 // TimerA prescale match register +#define TIMER_O_TBPMR 0x00000044 // TimerB prescale match register +#define TIMER_O_TAR 0x00000048 // TimerA register +#define TIMER_O_TBR 0x0000004C // TimerB register + +//***************************************************************************** +// +// The following define the reset values of the timer registers. +// +//***************************************************************************** +#define TIMER_RV_CFG 0x00000000 // Configuration register RV +#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV +#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV +#define TIMER_RV_CTL 0x00000000 // Control register RV +#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV +#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV +#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV +#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV +#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV +#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV +#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV +#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV +#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV +#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV +#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV +#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV +#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV +#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_CFG register. +// +//***************************************************************************** +#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask +#define TIMER_CFG_16_BIT 0x00000004 // Two 16 bit timers +#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32 bit RTC +#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32 bit timer + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_TnMR register. +// +//***************************************************************************** +#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select +#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time +#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask +#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture +#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic +#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_CTL register. +// +//***************************************************************************** +#define TIMER_CTL_TBPWML 0x00004000 // TimerB PWM output level invert +#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask +#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // TimerB event mode - both edges +#define TIMER_CTL_TBEVENT_NEG 0x00000400 // TimerB event mode - neg edge +#define TIMER_CTL_TBEVENT_POS 0x00000000 // TimerB event mode - pos edge +#define TIMER_CTL_TBSTALL 0x00000200 // TimerB stall enable +#define TIMER_CTL_TBEN 0x00000100 // TimerB enable +#define TIMER_CTL_TAPWML 0x00000040 // TimerA PWM output level invert +#define TIMER_CTL_RTCEN 0x00000010 // RTC counter enable +#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask +#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // TimerA event mode - both edges +#define TIMER_CTL_TAEVENT_NEG 0x00000004 // TimerA event mode - neg edge +#define TIMER_CTL_TAEVENT_POS 0x00000000 // TimerA event mode - pos edge +#define TIMER_CTL_TASTALL 0x00000002 // TimerA stall enable +#define TIMER_CTL_TAEN 0x00000001 // TimerA enable + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_IMR register. +// +//***************************************************************************** +#define TIMER_IMR_CBEIM 0x00000400 // CaptureB event interrupt mask +#define TIMER_IMR_CBMIM 0x00000200 // CaptureB match interrupt mask +#define TIMER_IMR_TBTOIM 0x00000100 // TimerB time out interrupt mask +#define TIMER_IMR_RTCIM 0x00000008 // RTC interrupt mask +#define TIMER_IMR_CAEIM 0x00000004 // CaptureA event interrupt mask +#define TIMER_IMR_CAMIM 0x00000002 // CaptureA match interrupt mask +#define TIMER_IMR_TATOIM 0x00000001 // TimerA time out interrupt mask + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_RIS register. +// +//***************************************************************************** +#define TIMER_RIS_CBERIS 0x00000400 // CaptureB event raw int status +#define TIMER_RIS_CBMRIS 0x00000200 // CaptureB match raw int status +#define TIMER_RIS_TBTORIS 0x00000100 // TimerB time out raw int status +#define TIMER_RIS_RTCRIS 0x00000008 // RTC raw int status +#define TIMER_RIS_CAERIS 0x00000004 // CaptureA event raw int status +#define TIMER_RIS_CAMRIS 0x00000002 // CaptureA match raw int status +#define TIMER_RIS_TATORIS 0x00000001 // TimerA time out raw int status + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_MIS register. +// +//***************************************************************************** +#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status +#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status +#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat +#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status +#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status +#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status +#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_ICR register. +// +//***************************************************************************** +#define TIMER_ICR_CBECINT 0x00000400 // CaptureB event interrupt clear +#define TIMER_ICR_CBMCINT 0x00000200 // CaptureB match interrupt clear +#define TIMER_ICR_TBTOCINT 0x00000100 // TimerB time out interrupt clear +#define TIMER_ICR_RTCCINT 0x00000008 // RTC interrupt clear +#define TIMER_ICR_CAECINT 0x00000004 // CaptureA event interrupt clear +#define TIMER_ICR_CAMCINT 0x00000002 // CaptureA match interrupt clear +#define TIMER_ICR_TATOCINT 0x00000001 // TimerA time out interrupt clear + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_TAILR register. +// +//***************************************************************************** +#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode +#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TBILR register. +// +//***************************************************************************** +#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_TAMATCHR register. +// +//***************************************************************************** +#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode +#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TBMATCHR register. +// +//***************************************************************************** +#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TnPR register. +// +//***************************************************************************** +#define TIMER_TNPR_TNPSR 0x0000000F // TimerN prescale value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TnPMR register. +// +//***************************************************************************** +#define TIMER_TNPMR_TNPSMR 0x0000000F // TimerN prescale match value + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_TAR register. +// +//***************************************************************************** +#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode +#define TIMER_TAR_TARL 0x0000FFFF // TimerA value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TBR register. +// +//***************************************************************************** +#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value + +#endif // __HW_TIMER_H__ diff --git a/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_types.h b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_types.h new file mode 100644 index 000000000..a944f6662 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_types.h @@ -0,0 +1,63 @@ +//***************************************************************************** +// +// hw_types.h - Common types and macros. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_TYPES_H__ +#define __HW_TYPES_H__ + +//***************************************************************************** +// +// Define a boolean type, and values for true and false. +// +//***************************************************************************** +typedef unsigned char tBoolean; + +#ifndef true +#define true 1 +#endif + +#ifndef false +#define false 0 +#endif + +//***************************************************************************** +// +// Macros for hardware access, both direct and via the bit-band region. +// +//***************************************************************************** +#define HWREG(x) \ + (*((volatile unsigned long *)(x))) +#define HWREGBITW(x, b) \ + HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITH(x, b) \ + HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITB(x, b) \ + HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) + +#endif // __HW_TYPES_H__ diff --git a/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_uart.h b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_uart.h new file mode 100644 index 000000000..40b6ab2a6 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_uart.h @@ -0,0 +1,234 @@ +//***************************************************************************** +// +// hw_uart.h - Macros and defines used when accessing the UART hardware +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_UART_H__ +#define __HW_UART_H__ + +//***************************************************************************** +// +// UART Register Offsets. +// +//***************************************************************************** +#define UART_O_DR 0x00000000 // Data Register +#define UART_O_RSR 0x00000004 // Receive Status Register (read) +#define UART_O_ECR 0x00000004 // Error Clear Register (write) +#define UART_O_FR 0x00000018 // Flag Register (read only) +#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg +#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg +#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte +#define UART_O_CTL 0x00000030 // Control Register +#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg +#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg +#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register +#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register +#define UART_O_ICR 0x00000044 // Interrupt Clear Register + +//***************************************************************************** +// +// Data Register bits +// +//***************************************************************************** +#define UART_DR_OE 0x00000800 // Overrun Error +#define UART_DR_BE 0x00000400 // Break Error +#define UART_DR_PE 0x00000200 // Parity Error +#define UART_DR_FE 0x00000100 // Framing Error + +//***************************************************************************** +// +// Receive Status Register bits +// +//***************************************************************************** +#define UART_RSR_OE 0x00000008 // Overrun Error +#define UART_RSR_BE 0x00000004 // Break Error +#define UART_RSR_PE 0x00000002 // Parity Error +#define UART_RSR_FE 0x00000001 // Framing Error + +//***************************************************************************** +// +// Flag Register bits +// +//***************************************************************************** +#define UART_FR_RI 0x100 // Ring Indicator +#define UART_FR_TXFE 0x080 // TX FIFO Empty +#define UART_FR_RXFF 0x040 // RX FIFO Full +#define UART_FR_TXFF 0x020 // TX FIFO Full +#define UART_FR_RXFE 0x010 // RX FIFO Empty +#define UART_FR_BUSY 0x008 // UART Busy + +//***************************************************************************** +// +// Line Control Register High bits +// +//***************************************************************************** +#define UART_LCR_H_SPS 0x80 // Stick Parity Select +#define UART_LCR_H_WLEN 0x60 // Word length +#define UART_LCR_H_WLEN_8 0x60 // 8 bit data +#define UART_LCR_H_WLEN_7 0x40 // 7 bit data +#define UART_LCR_H_WLEN_6 0x20 // 6 bit data +#define UART_LCR_H_WLEN_5 0x00 // 5 bit data +#define UART_LCR_H_FEN 0x10 // Enable FIFO +#define UART_LCR_H_STP2 0x08 // Two Stop Bits Select +#define UART_LCR_H_EPS 0x04 // Even Parity Select +#define UART_LCR_H_PEN 0x02 // Parity Enable +#define UART_LCR_H_BRK 0x01 // Send Break + +//***************************************************************************** +// +// Control Register bits +// +//***************************************************************************** +#define UART_CTL_CTSEN 0x8000 // CTS Hardware Flow Control +#define UART_CTL_RTSEN 0x4000 // RTS Hardware Flow Control +#define UART_CTL_OUT2 0x2000 // OUT2 +#define UART_CTL_OUT1 0x1000 // OUT1 +#define UART_CTL_RTS 0x0800 // Request To Send +#define UART_CTL_DTR 0x0400 // Data Terminal Ready +#define UART_CTL_RXE 0x0200 // Receive Enable +#define UART_CTL_TXE 0x0100 // Transmit Enable +#define UART_CTL_LBE 0x0080 // Loopback Enable +#define UART_CTL_IIRLP 0x0004 // IrDA SIR low power mode +#define UART_CTL_SIREN 0x0002 // SIR Enable +#define UART_CTL_UARTEN 0x0001 // UART Enable + +//***************************************************************************** +// +// Interrupt FIFO Level Select Register bits +// +//***************************************************************************** +#define UART_IFLS_RX1_8 0x00 // 1/8 Full +#define UART_IFLS_RX2_8 0x10 // 1/4 Full +#define UART_IFLS_RX4_8 0x20 // 1/2 Full +#define UART_IFLS_RX6_8 0x30 // 3/4 Full +#define UART_IFLS_RX7_8 0x40 // 7/8 Full +#define UART_IFLS_TX1_8 0x00 // 1/8 Full +#define UART_IFLS_TX2_8 0x01 // 1/4 Full +#define UART_IFLS_TX4_8 0x02 // 1/2 Full +#define UART_IFLS_TX6_8 0x03 // 3/4 Full +#define UART_IFLS_TX7_8 0x04 // 7/8 Full + +//***************************************************************************** +// +// Interrupt Mask Set/Clear Register bits +// +//***************************************************************************** +#define UART_IM_OEIM 0x400 // Overrun Error Interrupt Mask +#define UART_IM_BEIM 0x200 // Break Error Interrupt Mask +#define UART_IM_PEIM 0x100 // Parity Error Interrupt Mask +#define UART_IM_FEIM 0x080 // Framing Error Interrupt Mask +#define UART_IM_RTIM 0x040 // Receive Timeout Interrupt Mask +#define UART_IM_TXIM 0x020 // Transmit Interrupt Mask +#define UART_IM_RXIM 0x010 // Receive Interrupt Mask +#define UART_IM_DSRMIM 0x008 // DSR Interrupt Mask +#define UART_IM_DCDMIM 0x004 // DCD Interrupt Mask +#define UART_IM_CTSMIM 0x002 // CTS Interrupt Mask +#define UART_IM_RIMIM 0x001 // RI Interrupt Mask + +//***************************************************************************** +// +// Raw Interrupt Status Register +// +//***************************************************************************** +#define UART_RIS_OERIS 0x400 // Overrun Error Interrupt Status +#define UART_RIS_BERIS 0x200 // Break Error Interrupt Status +#define UART_RIS_PERIS 0x100 // Parity Error Interrupt Status +#define UART_RIS_FERIS 0x080 // Framing Error Interrupt Status +#define UART_RIS_RTRIS 0x040 // Receive Timeout Interrupt Status +#define UART_RIS_TXRIS 0x020 // Transmit Interrupt Status +#define UART_RIS_RXRIS 0x010 // Receive Interrupt Status +#define UART_RIS_DSRRMIS 0x008 // DSR Interrupt Status +#define UART_RIS_DCDRMIS 0x004 // DCD Interrupt Status +#define UART_RIS_CTSRMIS 0x002 // CTS Interrupt Status +#define UART_RIS_RIRMIS 0x001 // RI Interrupt Status + +//***************************************************************************** +// +// Masked Interrupt Status Register +// +//***************************************************************************** +#define UART_MIS_OEMIS 0x400 // Overrun Error Interrupt Status +#define UART_MIS_BEMIS 0x200 // Break Error Interrupt Status +#define UART_MIS_PEMIS 0x100 // Parity Error Interrupt Status +#define UART_MIS_FEMIS 0x080 // Framing Error Interrupt Status +#define UART_MIS_RTMIS 0x040 // Receive Timeout Interrupt Status +#define UART_MIS_TXMIS 0x020 // Transmit Interrupt Status +#define UART_MIS_RXMIS 0x010 // Receive Interrupt Status +#define UART_MIS_DSRMMIS 0x008 // DSR Interrupt Status +#define UART_MIS_DCDMMIS 0x004 // DCD Interrupt Status +#define UART_MIS_CTSMMIS 0x002 // CTS Interrupt Status +#define UART_MIS_RIMMIS 0x001 // RI Interrupt Status + +//***************************************************************************** +// +// Interrupt Clear Register bits +// +//***************************************************************************** +#define UART_ICR_OEIC 0x200 // Overrun Error Interrupt Clear +#define UART_ICR_BEIC 0x200 // Break Error Interrupt Clear +#define UART_ICR_PEIC 0x200 // Parity Error Interrupt Clear +#define UART_ICR_FEIC 0x200 // Framing Error Interrupt Clear +#define UART_ICR_RTIC 0x200 // Receive Timeout Interrupt Clear +#define UART_ICR_TXIC 0x200 // Transmit Interrupt Clear +#define UART_ICR_RXIC 0x200 // Receive Interrupt Clear +#define UART_ICR_DSRMIC 0x200 // DSR Interrupt Clear +#define UART_ICR_DCDMIC 0x200 // DCD Interrupt Clear +#define UART_ICR_CTSMIC 0x200 // CTS Interrupt Clear +#define UART_ICR_RIMIC 0x200 // RI Interrupt Clear + +//***************************************************************************** +// +// DMA Control Register bits +// +//***************************************************************************** +#define UART_DMACRDMAONERR 0x04 // Disable DMA On Error +#define UART_DMACRTXDMAE 0x02 // Enable Transmit DMA +#define UART_DMACRRXDMAE 0x01 // Enable Receive DMA + +#define UART_RSR_ANY (UART_RSR_OE | \ + UART_RSR_BE | \ + UART_RSR_PE | \ + UART_RSR_FE) + +//***************************************************************************** +// +// Reset Values for UART Registers. +// +//***************************************************************************** +#define UART_RV_DR 0 +#define UART_RV_RSR 0x0 +#define UART_RV_ECR 0 +#define UART_RV_FR 0x90 +#define UART_RV_IBRD 0x0000 +#define UART_RV_FBRD 0x00 +#define UART_RV_LCR_H 0x00 +#define UART_RV_CTL 0x0300 +#define UART_RV_IFLS 0x12 +#define UART_RV_IM 0x000 +#define UART_RV_RIS 0x000 +#define UART_RV_MIS 0x000 +#define UART_RV_ICR 0x000 + +#endif // __HW_UART_H__ diff --git a/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_watchdog.h b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_watchdog.h new file mode 100644 index 000000000..6ae5dff54 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_watchdog.h @@ -0,0 +1,99 @@ +//***************************************************************************** +// +// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_WATCHDOG_H__ +#define __HW_WATCHDOG_H__ + +//***************************************************************************** +// +// The following define the offsets of the Watchdog Timer registers. +// +//***************************************************************************** +#define WDT_O_LOAD 0x00000000 // Load register +#define WDT_O_VALUE 0x00000004 // Current value register +#define WDT_O_CTL 0x00000008 // Control register +#define WDT_O_ICR 0x0000000C // Interrupt clear register +#define WDT_O_RIS 0x00000010 // Raw interrupt status register +#define WDT_O_MIS 0x00000014 // Masked interrupt status register +#define WDT_O_TEST 0x00000418 // Test register +#define WDT_O_CAUSE 0x0000041C // Cause register +#define WDT_O_LOCK 0x00000C00 // Lock register + +//***************************************************************************** +// +// The following define the bit fields in the WDT_CTL register. +// +//***************************************************************************** +#define WDT_CTL_RESEN 0x00000002 // Enable reset output +#define WDT_CTL_INTEN 0x00000001 // Enable the WDT counter and int + +//***************************************************************************** +// +// The following define the bit fields in the WDT_ISR, WDT_RIS, and WDT_MIS +// registers. +// +//***************************************************************************** +#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired + +//***************************************************************************** +// +// The following define the bit fields in the WDT_TEST register. +// +//***************************************************************************** +#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable +#define WDT_TEST_TEST_EN 0x00000001 // Watchdog timer reset int test + +//***************************************************************************** +// +// The following define the bit fields in the WDT_CAUSE register. +// +//***************************************************************************** +#define WDT_CAUSE_WDR 0x00000002 // Watchdog timer reset occurred +#define WDT_CAUSE_WDI 0x00000001 // Watchdog timer int occurred + +//***************************************************************************** +// +// The following define the bit fields in the WDT_LOCK register. +// +//***************************************************************************** +#define WDT_LOCK_LOCKED 0x00000001 // Watchdog timer is locked +#define WDT_LOCK_UNLOCKED 0x00000000 // Watchdog timer is unlocked +#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer + +//***************************************************************************** +// +// The following define the reset values for the WDT registers. +// +//***************************************************************************** +#define WDT_RV_LOAD 0xFFFFFFFF // Load register +#define WDT_RV_VALUE 0xFFFFFFFF // Current value register +#define WDT_RV_CTL 0x00000000 // Control register +#define WDT_RV_RIS 0x00000000 // Raw interrupt status register +#define WDT_RV_MIS 0x00000000 // Masked interrupt status register +#define WDT_RV_LOCK 0x00000000 // Lock register + +#endif // __HW_WATCHDOG_H__ diff --git a/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/i2c.h b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/i2c.h new file mode 100644 index 000000000..e48c98d87 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/i2c.h @@ -0,0 +1,137 @@ +//***************************************************************************** +// +// i2c.h - Prototypes for the I2C Driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __I2C_H__ +#define __I2C_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Defines for the API. +// +//***************************************************************************** +//***************************************************************************** +// +// Interrupt defines. +// +//***************************************************************************** +#define I2C_INT_MASTER 0x00000001 +#define I2C_INT_SLAVE 0x00000002 + +//***************************************************************************** +// +// I2C Master commands. +// +//***************************************************************************** +#define I2C_MASTER_CMD_SINGLE_SEND \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_SINGLE_RECEIVE \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_SEND_START \ + (I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_SEND_CONT \ + (I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_SEND_FINISH \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \ + (I2C_MASTER_CS_STOP) +#define I2C_MASTER_CMD_BURST_RECEIVE_START \ + (I2C_MASTER_CS_ACK | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \ + (I2C_MASTER_CS_ACK | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) + +//***************************************************************************** +// +// I2C Master error status. +// +//***************************************************************************** +#define I2C_MASTER_ERR_NONE 0 +#define I2C_MASTER_ERR_ADDR_ACK 0x00000004 +#define I2C_MASTER_ERR_DATA_ACK 0x00000008 +#define I2C_MASTER_ERR_ARB_LOST 0x00000010 + +//***************************************************************************** +// +// I2C Slave action requests +// +//***************************************************************************** +#define I2C_SLAVE_ACT_NONE 0 +#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data +#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data + +//***************************************************************************** +// Miscellaneous I2C driver definitions. +//***************************************************************************** +#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void)); +extern void I2CIntUnregister(unsigned long ulBase); +extern tBoolean I2CMasterBusBusy(unsigned long ulBase); +extern tBoolean I2CMasterBusy(unsigned long ulBase); +extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd); +extern unsigned long I2CMasterDataGet(unsigned long ulBase); +extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData); +extern void I2CMasterDisable(unsigned long ulBase); +extern void I2CMasterEnable(unsigned long ulBase); +extern unsigned long I2CMasterErr(unsigned long ulBase); +extern void I2CMasterInit(unsigned long ulBase, tBoolean bFast); +extern void I2CMasterIntClear(unsigned long ulBase); +extern void I2CMasterIntDisable(unsigned long ulBase); +extern void I2CMasterIntEnable(unsigned long ulBase); +extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void I2CMasterSlaveAddrSet(unsigned long ulBase, + unsigned char ucSlaveAddr, + tBoolean bReceive); +extern unsigned long I2CSlaveDataGet(unsigned long ulBase); +extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData); +extern void I2CSlaveDisable(unsigned long ulBase); +extern void I2CSlaveEnable(unsigned long ulBase); +extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr); +extern void I2CSlaveIntClear(unsigned long ulBase); +extern void I2CSlaveIntDisable(unsigned long ulBase); +extern void I2CSlaveIntEnable(unsigned long ulBase); +extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked); +extern unsigned long I2CSlaveStatus(unsigned long ulBase); + +#ifdef __cplusplus +} +#endif + +#endif // __I2C_H__ diff --git a/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/interrupt.h b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/interrupt.h new file mode 100644 index 000000000..23424af4e --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/interrupt.h @@ -0,0 +1,57 @@ +//***************************************************************************** +// +// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void IntMasterEnable(void); +extern void IntMasterDisable(void); +extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)); +extern void IntUnregister(unsigned long ulInterrupt); +extern void IntPriorityGroupingSet(unsigned long ulBits); +extern unsigned long IntPriorityGroupingGet(void); +extern void IntPrioritySet(unsigned long ulInterrupt, + unsigned char ucPriority); +extern long IntPriorityGet(unsigned long ulInterrupt); +extern void IntEnable(unsigned long ulInterrupt); +extern void IntDisable(unsigned long ulInterrupt); + +#ifdef __cplusplus +} +#endif + +#endif // __INTERRUPT_H__ diff --git a/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/libdriver.a b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/libdriver.a new file mode 100644 index 0000000000000000000000000000000000000000..c465e8f71dd00cc7357c7b459daa0c2b87d09020 GIT binary patch literal 46076 zcmdUY4|rY0b?3Z4vSs<%l4TiWW8mozjf`bSwgfmSO=LYG8*F1^8$wgMyk|)u*+LSM zOmIqx5)%p=@@5^`ex?j^mOq%aGm0NuY zjraGPnRD;Vy!UG31e%O}b?2P(n=^mz+_~q>%)PJa+QLNt(7S5hp7q0q4P9LuuGx6? zHJh^84lQ#3X0u%#8#bC0`5L9vaiwaDKmM`$Ri!E&tw)r4qsNBZl=?{>JufTuRvfo< zD|J4{zK4{0qsLuOD)rNJeB?2uDjlCde|j^I&wfLxpUm-|!c_mzz}TI;4~~uwkKU<- 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b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/pdc.c new file mode 100644 index 000000000..1e82ed8a8 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/pdc.c @@ -0,0 +1,132 @@ +//***************************************************************************** +// +// pdc.c - Driver for the Peripheral Device Controller (PDC) on the Stellaris +// development board. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup utilities_api +//! @{ +// +//***************************************************************************** + +#include "hw_memmap.h" +#include "hw_types.h" +#include "gpio.h" +#include "ssi.h" +#include "sysctl.h" +#include "pdc.h" + +//***************************************************************************** +// +//! Initializes the connection to the PDC. +//! +//! This function will enable clocking to the SSI and GPIO A modules, configure +//! the GPIO pins to be used for an SSI interface, and it will configure the +//! SSI as a 1Mb master device, operating in MOTO mode. It will also enable +//! the SSI module, and will enable the chip select for the PDC on the +//! Stellaris development board. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return None. +// +//***************************************************************************** +void +PDCInit(void) +{ + // + // Enable the peripherals used to drive the PDC. + // + SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + + // + // Configure the appropriate pins to be SSI instead of GPIO. + // + GPIODirModeSet(GPIO_PORTA_BASE, SSI_CLK | SSI_TX | SSI_RX, + GPIO_DIR_MODE_HW); + GPIODirModeSet(GPIO_PORTA_BASE, SSI_CS, GPIO_DIR_MODE_OUT); + GPIOPadConfigSet(GPIO_PORTA_BASE, SSI_CLK, GPIO_STRENGTH_4MA, + GPIO_PIN_TYPE_STD_WPU); + + // + // Configure the SSI port. + // + SSIConfig(SSI_BASE, SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 1000000, 8); + SSIEnable(SSI_BASE); + + // + // Reset the PDC SSI state machine. The chip select needs to be held low + // for 100ns; the procedure call overhead more than accounts for this time. + // + GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, 0); + GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, PDC_CS); +} + +//***************************************************************************** +// +//! Write a PDC register. +//! +//! \param ucAddr specifies the PDC register to write. +//! \param ucData specifies the data to write. +//! +//! This function will perform the SSI transfers required to write a register +//! in the PDC on the Stellaris development board. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return None. +// +//***************************************************************************** +void +PDCWrite(unsigned char ucAddr, unsigned char ucData) +{ + unsigned long ulTemp; + + // + // Send address and write command. + // + SSIDataPut(SSI_BASE, (ucAddr & 0x0F) | PDC_WR); + + // + // Write the data. + // + SSIDataPut(SSI_BASE, ucData); + + // + // Flush data read during address write. + // + SSIDataGet(SSI_BASE, &ulTemp); + + // + // Flush data read during data write. + // + SSIDataGet(SSI_BASE, &ulTemp); +} + diff --git a/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/pdc.h b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/pdc.h new file mode 100644 index 000000000..aba74cd71 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/pdc.h @@ -0,0 +1,124 @@ +//***************************************************************************** +// +// pdc.h - Stellaris development board Peripheral Device Controller definitions +// and prototypes. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __PDC_H__ +#define __PDC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The registers within the peripheral device controller. +// +//***************************************************************************** +#define PDC_VER 0x0 // Version register +#define PDC_CSR 0x1 // Command/Status register +#define PDC_DSW 0x4 // DIP Switch register +#define PDC_LED 0x5 // LED register +#define PDC_LCD_CSR 0x6 // LCD Command/Status register +#define PDC_LCD_RAM 0x7 // LCD RAM register +#define PDC_GPXDAT 0x8 // GPIO X Data register +#define PDC_GPXDIR 0x9 // GPIO X Direction register +#define PDC_GPYDAT 0xA // GPIO Y Data register +#define PDC_GPYDIR 0xB // GPIO Y Direction register +#define PDC_GPZDAT 0xC // GPIO Z Data register +#define PDC_GPZDIR 0xD // GPIO Z Direction register + +//***************************************************************************** +// +// Flags indicating a read or write to the peripheral device controller. +// +//***************************************************************************** +#define PDC_RD 0x80 // PDC read command +#define PDC_WR 0x00 // PDC write command + +//***************************************************************************** +// +// LCD panel (Crystalfontz CFAH1602B) commands, RS = 0 +// +//***************************************************************************** +#define LCD_CLEAR 0x01 // Clear display (0 fill DDRAM). +#define LCD_HOME 0x02 // Cursor home. +#define LCD_MODE 0x04 // Set entry mode (cursor dir) +#define LCD_ON 0x08 // Set display, cursor, blinking + // on/off +#define LCD_CUR 0x10 // Cursor, display shift +#define LCD_IF 0x20 // Set interface data length, + // lines, font +#define LCD_CGADDR 0x40 // Set CGRAM AC address +#define LCD_DDADDR 0x80 // Set DDRAM AC address + +//***************************************************************************** +// +// LCD Status bit +// +//***************************************************************************** +#define LCD_B_BUSY 0x80 // Busy flag. + +//***************************************************************************** +// +// The GPIO port A pin numbers for the various SSI signals. +// +//***************************************************************************** +#define SSI_CS GPIO_PIN_3 +#define PDC_CS GPIO_PIN_3 +#define SSI_CLK GPIO_PIN_2 +#define SSI_TX GPIO_PIN_5 +#define SSI_RX GPIO_PIN_4 + +//***************************************************************************** +// +// Function Prototypes +// +//***************************************************************************** +extern void PDCInit(void); +extern unsigned char PDCRead(unsigned char ucAddr); +extern void PDCWrite(unsigned char ucAddr, unsigned char ucData); +extern unsigned char PDCDIPRead(void); +extern void PDCLEDWrite(unsigned char ucLED); +extern unsigned char PDCLEDRead(void); +extern void PDCLCDInit(void); +extern void PDCLCDBacklightOn(void); +extern void PDCLCDBacklightOff(void); +extern void PDCLCDClear(void); +extern void PDCLCDCreateChar(unsigned char ucChar, unsigned char *pucData); +extern void PDCLCDSetPos(unsigned char ucX, unsigned char ucY); +extern void PDCLCDWrite(const char *pcStr, unsigned long ulCount); +extern unsigned char PDCGPIODirRead(unsigned char ucIdx); +extern void PDCGPIODirWrite(unsigned char ucIdx, unsigned char ucValue); +extern unsigned char PDCGPIORead(unsigned char ucIdx); +extern void PDCGPIOWrite(unsigned char ucIdx, unsigned char ucValue); + +#ifdef __cplusplus +} +#endif + +#endif // __PDC_H__ diff --git a/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/ssi.h b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/ssi.h new file mode 100644 index 000000000..ef53b348b --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/ssi.h @@ -0,0 +1,88 @@ +//***************************************************************************** +// +// ssi.h - Prototypes for the Synchronous Serial Interface Driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __SSI_H__ +#define __SSI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear +// as the ulIntFlags parameter, and returned by SSIIntStatus. +// +//***************************************************************************** +#define SSI_TXFF 0x00000008 // TX FIFO half empty or less +#define SSI_RXFF 0x00000004 // RX FIFO half full or less +#define SSI_RXTO 0x00000002 // RX timeout +#define SSI_RXOR 0x00000001 // RX overrun + +//***************************************************************************** +// +// Values that can be passed to SSIConfig. +// +//***************************************************************************** +#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0 +#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1 +#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0 +#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1 +#define SSI_FRF_TI 0x00000010 // TI frame format +#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format + +#define SSI_MODE_MASTER 0x00000000 // SSI master +#define SSI_MODE_SLAVE 0x00000001 // SSI slave +#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void SSIConfig(unsigned long ulBase, unsigned long ulProtocol, + unsigned long ulMode, unsigned long ulBitRate, + unsigned long ulDataWidth); +extern void SSIDataGet(unsigned long ulBase, unsigned long *ulData); +extern long SSIDataNonBlockingGet(unsigned long ulBase, unsigned long *ulData); +extern void SSIDataPut(unsigned long ulBase, unsigned long ulData); +extern long SSIDataNonBlockingPut(unsigned long ulBase, unsigned long ulData); +extern void SSIDisable(unsigned long ulBase); +extern void SSIEnable(unsigned long ulBase); +extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void SSIIntUnregister(unsigned long ulBase); + +#ifdef __cplusplus +} +#endif + +#endif // __SSI_H__ diff --git a/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/sysctl.h b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/sysctl.h new file mode 100644 index 000000000..2e1d1e48c --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/sysctl.h @@ -0,0 +1,221 @@ +//***************************************************************************** +// +// sysctl.h - Prototypes for the system control driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __SYSCTL_H__ +#define __SYSCTL_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed to the +// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(), +// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the +// ulPeripheral parameter. The peripherals in the fourth group (upper nibble +// is 3) can only be used with the SysCtlPeripheralPresent() API. +// +//***************************************************************************** +#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog +#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0 +#define SYSCTL_PERIPH_SSI 0x10000010 // SSI +#define SYSCTL_PERIPH_I2C 0x10001000 // I2C +#define SYSCTL_PERIPH_TIMER0 0x10010000 // Timer 0 +#define SYSCTL_PERIPH_TIMER1 0x10020000 // Timer 1 +#define SYSCTL_PERIPH_COMP0 0x11000000 // Analog comparator 0 +#define SYSCTL_PERIPH_COMP1 0x12000000 // Analog comparator 1 +#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A +#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B +#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C +#define SYSCTL_PERIPH_PLL 0x30000010 // PLL + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlPinPresent() API +// as the ulPin parameter. +// +//***************************************************************************** +#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin +#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin +#define SYSCTL_PIN_C0O 0x00000100 // C0o pin +#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin +#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin +#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin +#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlLDOSet() API as +// the ulVoltage value, or returned by the SysCtlLDOGet() API. +// +//***************************************************************************** +#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V +#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V +#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V +#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V +#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V +#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V +#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V +#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V +#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V +#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V +#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlLDOConfigSet() API. +// +//***************************************************************************** +#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset +#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlIntEnable(), +// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask +// by the SysCtlIntStatus() API. +// +//***************************************************************************** +#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt +#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt +#define SYSCTL_INT_BOSC_FAIL 0x00000010 // Boot oscillator failure int +#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int +#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt +#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt +#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlResetCauseClear() +// API or returned by the SysCtlResetCauseGet() API. +// +//***************************************************************************** +#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset +#define SYSCTL_CAUSE_SW 0x00000010 // Software reset +#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset +#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset +#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset +#define SYSCTL_CAUSE_EXT 0x00000001 // External reset + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlBrownOutConfigSet() +// API as the ulConfig parameter. +// +//***************************************************************************** +#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting +#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlClockSet() API as +// the ulConfig parameter. +// +//***************************************************************************** +#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1 +#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2 +#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3 +#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4 +#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5 +#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6 +#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7 +#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8 +#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9 +#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10 +#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11 +#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12 +#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13 +#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14 +#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15 +#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16 +#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock +#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock +#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz +#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz +#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz +#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz +#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz +#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz +#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz +#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz +#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz +#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz +#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz +#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz +#define SYSCTL_OSC_MAIN 0x00000000 // Oscillator source is main osc +#define SYSCTL_OSC_BOOT 0x00000010 // Oscillator source is boot osc +#define SYSCTL_OSC_BOOT4 0x00000020 // Oscillator source is boot osc /4 +#define SYSCTL_BOOT_OSC_DIS 0x00000002 // Disable boot oscillator +#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern unsigned long SysCtlSRAMSizeGet(void); +extern unsigned long SysCtlFlashSizeGet(void); +extern tBoolean SysCtlPinPresent(unsigned long ulPin); +extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral); +extern void SysCtlPeripheralReset(unsigned long ulPeripheral); +extern void SysCtlPeripheralEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralClockGating(tBoolean bEnable); +extern void SysCtlIntRegister(void (*pfnHandler)(void)); +extern void SysCtlIntUnregister(void); +extern void SysCtlIntEnable(unsigned long ulInts); +extern void SysCtlIntDisable(unsigned long ulInts); +extern void SysCtlIntClear(unsigned long ulInts); +extern unsigned long SysCtlIntStatus(tBoolean bMasked); +extern void SysCtlLDOSet(unsigned long ulVoltage); +extern unsigned long SysCtlLDOGet(void); +extern void SysCtlLDOConfigSet(unsigned long ulConfig); +extern void SysCtlReset(void); +extern void SysCtlSleep(void); +extern void SysCtlDeepSleep(void); +extern unsigned long SysCtlResetCauseGet(void); +extern void SysCtlResetCauseClear(unsigned long ulCauses); +extern void SysCtlBrownOutConfigSet(unsigned long ulConfig, + unsigned long ulDelay); +extern void SysCtlClockSet(unsigned long ulConfig); +extern unsigned long SysCtlClockGet(void); +extern void SysCtlBOSCVerificationSet(tBoolean bEnable); +extern void SysCtlMOSCVerificationSet(tBoolean bEnable); +extern void SysCtlPLLVerificationSet(tBoolean bEnable); +extern void SysCtlClkVerificationClear(void); + +#ifdef __cplusplus +} +#endif + +#endif // __SYSCTL_H__ diff --git a/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/systick.h b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/systick.h new file mode 100644 index 000000000..4f70259ba --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/systick.h @@ -0,0 +1,53 @@ +//***************************************************************************** +// +// systick.h - Prototypes for the SysTick driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __SYSTICK_H__ +#define __SYSTICK_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void SysTickEnable(void); +extern void SysTickDisable(void); +extern void SysTickIntRegister(void (*pfnHandler)(void)); +extern void SysTickIntUnregister(void); +extern void SysTickPeriodSet(unsigned long ulPeriod); +extern unsigned long SysTickPeriodGet(void); +extern unsigned long SysTickValueGet(void); + +#ifdef __cplusplus +} +#endif + +#endif // __SYSTICK_H__ diff --git a/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/timer.h b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/timer.h new file mode 100644 index 000000000..306b141db --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/timer.h @@ -0,0 +1,137 @@ +//***************************************************************************** +// +// timer.h - Prototypes for the timer module +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __TIMER_H__ +#define __TIMER_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to TimerConfigure as the ulConfig parameter. +// +//***************************************************************************** +#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer +#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer +#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer +#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers +#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer +#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer +#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter +#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer +#define TIMER_CFG_A_PWM 0x0000000F // Timer A PWM output +#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer +#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer +#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter +#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer +#define TIMER_CFG_B_PWM 0x00000F00 // Timer B PWM output + +//***************************************************************************** +// +// Values that can be passed to TimerIntEnable, TimerIntDisable, and +// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus. +// +//***************************************************************************** +#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt +#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt +#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt +#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask +#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt +#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt +#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerB time out interrupt + +//***************************************************************************** +// +// Values that can be passed to TimerControlEvent as the ulEvent parameter. +// +//***************************************************************************** +#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges +#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges +#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges + +//***************************************************************************** +// +// Values that can be passed to most of the timer APIs as the ulTimer +// parameter. +// +//***************************************************************************** +#define TIMER_A 0x000000ff // Timer A +#define TIMER_B 0x0000ff00 // Timer B +#define TIMER_BOTH 0x0000ffff // Timer Both + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer); +extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer); +extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig); +extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, + tBoolean bInvert); +extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer, + tBoolean bEnable); +extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulEvent); +extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer, + tBoolean bStall); +extern void TimerRTCEnable(unsigned long ulBase); +extern void TimerRTCDisable(unsigned long ulBase); +extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerPrescaleGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer); +extern unsigned long TimerValueGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerMatchGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, + void (*pfnHandler)(void)); +extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer); +extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void TimerQuiesce(unsigned long ulBase); + +#ifdef __cplusplus +} +#endif + +#endif // __TIMER_H__ diff --git a/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/uart.h b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/uart.h new file mode 100644 index 000000000..ea39859d2 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/uart.h @@ -0,0 +1,102 @@ +//***************************************************************************** +// +// uart.h - Defines and Macros for the UART. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __UART_H__ +#define __UART_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear +// as the ulIntFlags parameter, and returned from UARTIntStatus. +// +//***************************************************************************** +#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask +#define UART_INT_BE 0x200 // Break Error Interrupt Mask +#define UART_INT_PE 0x100 // Parity Error Interrupt Mask +#define UART_INT_FE 0x080 // Framing Error Interrupt Mask +#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask +#define UART_INT_TX 0x020 // Transmit Interrupt Mask +#define UART_INT_RX 0x010 // Receive Interrupt Mask + +//***************************************************************************** +// +// Values that can be passed to UARTConfigSet as the ulConfig parameter and +// returned by UARTConfigGet in the pulConfig parameter. Additionally, the +// UART_CONFIG_PAR_* subset can be passed to UARTParityModeSet as the ulParity +// parameter, and are returned by UARTParityModeGet. +// +//***************************************************************************** +#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data +#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data +#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data +#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data +#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit +#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits +#define UART_CONFIG_PAR_NONE 0x00000000 // No parity +#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity +#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity +#define UART_CONFIG_PAR_ONE 0x00000086 // Parity bit is one +#define UART_CONFIG_PAR_ZERO 0x00000082 // Parity bit is zero + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity); +extern unsigned long UARTParityModeGet(unsigned long ulBase); +extern void UARTConfigSet(unsigned long ulBase, unsigned long ulBaud, + unsigned long ulConfig); +extern void UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud, + unsigned long *pulConfig); +extern void UARTEnable(unsigned long ulBase); +extern void UARTDisable(unsigned long ulBase); +extern tBoolean UARTCharsAvail(unsigned long ulBase); +extern tBoolean UARTSpaceAvail(unsigned long ulBase); +extern long UARTCharNonBlockingGet(unsigned long ulBase); +extern long UARTCharGet(unsigned long ulBase); +extern tBoolean UARTCharNonBlockingPut(unsigned long ulBase, + unsigned char ucData); +extern void UARTCharPut(unsigned long ulBase, unsigned char ucData); +extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState); +extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern void UARTIntUnregister(unsigned long ulBase); +extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags); + +#ifdef __cplusplus +} +#endif + +#endif // __UART_H__ diff --git a/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/watchdog.h b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/watchdog.h new file mode 100644 index 000000000..2a82b7200 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S102_Rowley/hw_include/watchdog.h @@ -0,0 +1,63 @@ +//***************************************************************************** +// +// watchdog.h - Prototypes for the Watchdog Timer API +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 523 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __WATCHDOG_H__ +#define __WATCHDOG_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern tBoolean WatchdogRunning(unsigned long ulBase); +extern void WatchdogEnable(unsigned long ulBase); +extern void WatchdogResetEnable(unsigned long ulBase); +extern void WatchdogResetDisable(unsigned long ulBase); +extern void WatchdogLock(unsigned long ulBase); +extern void WatchdogUnlock(unsigned long ulBase); +extern tBoolean WatchdogLockState(unsigned long ulBase); +extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal); +extern unsigned long WatchdogReloadGet(unsigned long ulBase); +extern unsigned long WatchdogValueGet(unsigned long ulBase); +extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern void WatchdogIntUnregister(unsigned long ulBase); +extern void WatchdogIntEnable(unsigned long ulBase); +extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void WatchdogIntClear(unsigned long ulBase); +extern void WatchdogStallDisable(unsigned long ulBase); +extern void WatchdogStallDisable(unsigned long ulBase); + +#ifdef __cplusplus +} +#endif + +#endif // __WATCHDOG_H__ diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/FreeRTOSConfig.h b/20080212/Demo/CORTEX_LM3S316_IAR/FreeRTOSConfig.h new file mode 100644 index 000000000..ef07e0047 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/FreeRTOSConfig.h @@ -0,0 +1,86 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 80 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 3000 ) ) +#define configMAX_TASK_NAME_LEN ( 3 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_CO_ROUTINES 1 + +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 0 +#define INCLUDE_vTaskDelayUntil 0 +#define INCLUDE_vTaskDelay 1 + +#define configKERNEL_INTERRUPT_PRIORITY 255 + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/LM3S316.icf b/20080212/Demo/CORTEX_LM3S316_IAR/LM3S316.icf new file mode 100644 index 000000000..2c39cba27 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/LM3S316.icf @@ -0,0 +1,58 @@ +//***************************************************************************** +// +// boot_demo1.icf - Linker configuration file for boot_demo1. +// +// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved. +// Luminary Micro Confidential - For Use Under NDA Only +// +//***************************************************************************** + +// +// Define a memory region that covers the entire 4 GB addressible space of the +// processor. +// +define memory mem with size = 4G; + +// +// Define a region for the on-chip flash. +// +define region FLASH = mem:[from 0x00000000 to 0x00003fff]; + +// +// Define a region for the on-chip SRAM. +// +define region SRAM = mem:[from 0x20000000 to 0x20000fff]; + +// +// Define a block for the heap. The size should be set to something other +// than zero if things in the C library that require the heap are used. +// +define block HEAP with alignment = 8, size = 0x00000000 { }; + +// +// Indicate that the read/write values should be initialized by copying from +// flash. +// +initialize by copy { readwrite }; + +// +// Initicate that the noinit values should be left alone. This includes the +// stack, which if initialized will destroy the return address from the +// initialization code, causing the processor to branch to zero and fault. +// +do not initialize { section .noinit }; + +// +// Place the interrupt vectors at the start of flash. +// +place at start of FLASH { readonly section .intvec }; + +// +// Place the remainder of the read-only items into flash. +// +place in FLASH { readonly }; + +// +// Place all read/write items into SRAM. +// +place in SRAM { readwrite, block HEAP }; diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/ParTest/ParTest.c b/20080212/Demo/CORTEX_LM3S316_IAR/ParTest/ParTest.c new file mode 100644 index 000000000..a95105b84 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/ParTest/ParTest.c @@ -0,0 +1,122 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +/* +*/ + + +#include "FreeRTOS.h" +#include "Task.h" +#include "partest.h" + +#include "pdc.h" + +#define partstPINS (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 Z | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7) + +#define partstALL_OUTPUTS_OFF ( ( unsigned portCHAR ) 0x00 ) +#define partstMAX_OUTPUT_LED ( ( unsigned portCHAR ) 8 ) + +static volatile unsigned portCHAR ucOutputValue = partstALL_OUTPUTS_OFF; + +void vParTestInitialise( void ) +{ + PDCInit(); + PDCWrite( PDC_LED, ucOutputValue ); +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ +unsigned portCHAR ucBit = ( unsigned portCHAR ) 1; + + vTaskSuspendAll(); + { + if( uxLED < partstMAX_OUTPUT_LED ) + { + ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED; + + if( xValue == pdFALSE ) + { + ucBit ^= ( unsigned portCHAR ) 0xff; + ucOutputValue &= ucBit; + } + else + { + ucOutputValue |= ucBit; + } + + PDCWrite( PDC_LED, ucOutputValue ); + } + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned portCHAR ucBit; + + vTaskSuspendAll(); + { + if( uxLED < partstMAX_OUTPUT_LED ) + { + ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED; + + if( ucOutputValue & ucBit ) + { + ucOutputValue &= ~ucBit; + } + else + { + ucOutputValue |= ucBit; + } + + PDCWrite( PDC_LED, ucOutputValue ); + } + } + xTaskResumeAll(); +} + diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/RTOSDemo.ewd b/20080212/Demo/CORTEX_LM3S316_IAR/RTOSDemo.ewd new file mode 100644 index 000000000..e68a6ffd2 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/RTOSDemo.ewd @@ -0,0 +1,616 @@ + + + + 1 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 15 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IARROM_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + JLINK_ID + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 1 + 1 + 1 + + + + + + + + MACRAIGOR_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin + 0 + + + + + + diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/RTOSDemo.ewp b/20080212/Demo/CORTEX_LM3S316_IAR/RTOSDemo.ewp new file mode 100644 index 000000000..1a331cba4 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/RTOSDemo.ewp @@ -0,0 +1,829 @@ + + + + 1 + + Debug + + ARM + + 1 + + General + 3 + + 14 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 19 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 7 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 5 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Demo Source + + $PROJ_DIR$\commstest.c + + + $PROJ_DIR$\..\Common\Minimal\crflash.c + + + $PROJ_DIR$\main.c + + + $PROJ_DIR$\ParTest\ParTest.c + + + $PROJ_DIR$\registertest.s + + + + FreeRTOS Source + + $PROJ_DIR$\..\..\Source\croutine.c + + + $PROJ_DIR$\..\..\Source\portable\MemMang\heap_1.c + + + $PROJ_DIR$\..\..\Source\list.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s + + + $PROJ_DIR$\..\..\Source\queue.c + + + $PROJ_DIR$\..\..\Source\tasks.c + + + + Luminary Code + + $PROJ_DIR$\hw_include\cspy.c + + + $PROJ_DIR$\hw_include\pdc.c + + + $PROJ_DIR$\hw_include\startup.c + + + + + diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/RTOSDemo.eww b/20080212/Demo/CORTEX_LM3S316_IAR/RTOSDemo.eww new file mode 100644 index 000000000..239a9381e --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/RTOSDemo.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\RTOSDemo.ewp + + + + + diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/commstest.c b/20080212/Demo/CORTEX_LM3S316_IAR/commstest.c new file mode 100644 index 000000000..cbd16edc9 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/commstest.c @@ -0,0 +1,305 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + * The comms test Rx and Tx task and co-routine. See the comments at the top + * of main.c for full information. + */ + + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "croutine.h" + +/* Demo application include files. */ +#include "partest.h" + +/* Library include files. */ +#include "DriverLib.h" + +/* The LED's toggled by the various tasks. */ +#define commsFAIL_LED ( 7 ) +#define commsRX_LED ( 6 ) +#define commsTX_LED ( 5 ) + +/* The length of the queue used to pass received characters to the Comms Rx +task. */ +#define commsRX_QUEUE_LEN ( 5 ) + +/* The baud rate used by the UART comms tasks/co-routine. */ +#define commsBAUD_RATE ( 57600 ) + +/* FIFO setting for the UART. The FIFO is not used to create a better test. */ +#define commsFIFO_SET ( 0x10 ) + +/* The string that is transmitted on the UART contains sequentially the +characters from commsFIRST_TX_CHAR to commsLAST_TX_CHAR. */ +#define commsFIRST_TX_CHAR '0' +#define commsLAST_TX_CHAR 'z' + +/* Just used to walk through the program memory in order that some random data +can be generated. */ +#define commsTOTAL_PROGRAM_MEMORY ( ( unsigned portLONG * ) ( 8 * 1024 ) ) +#define commsFIRST_PROGRAM_BYTES ( ( unsigned portLONG * ) 4 ) + +/* The time between transmissions of the string on UART 0. This is pseudo +random in order to generate a bit or randomness to when the interrupts occur.*/ +#define commsMIN_TX_DELAY ( 40 / portTICK_RATE_MS ) +#define commsMAX_TX_DELAY ( ( portTickType ) 0x7f ) +#define commsOFFSET_TIME ( ( portTickType ) 3 ) + +/* The time the Comms Rx task should wait to receive a character. This should +be slightly longer than the time between transmissions. If we do not receive +a character after this time then there must be an error in the transmission or +the timing of the transmission. */ +#define commsRX_DELAY ( commsMAX_TX_DELAY + 20 ) + + +static unsigned portBASE_TYPE uxCommsErrorStatus = pdPASS; + +/* The queue used to pass characters out of the ISR. */ +static xQueueHandle xCommsQueue; + +/* The next character to transmit. */ +static portCHAR cNextChar; + +/*-----------------------------------------------------------*/ + +void vSerialInit( void ) +{ + /* Create the queue used to communicate between the UART ISR and the Comms + Rx task. */ + xCommsQueue = xQueueCreate( commsRX_QUEUE_LEN, sizeof( portCHAR ) ); + + /* Enable the UART. GPIOA has already been initialised. */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + + /* Set GPIO A0 and A1 as peripheral function. They are used to output the + UART signals. */ + GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); + + /* Configure the UART for 8-N-1 operation. */ + UARTConfigSetExpClk( UART0_BASE, SysCtlClockGet(), commsBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); + + /* We dont want to use the fifo. This is for test purposes to generate + as many interrupts as possible. */ + HWREG( UART0_BASE + UART_O_LCR_H ) &= ~commsFIFO_SET; + + /* Enable both Rx and Tx interrupts. */ + HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX ); + IntPrioritySet( INT_UART0, configKERNEL_INTERRUPT_PRIORITY ); + IntEnable( INT_UART0 ); +} +/*-----------------------------------------------------------*/ + +void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +portTickType xDelayPeriod; +static unsigned portLONG *pulRandomBytes = commsFIRST_PROGRAM_BYTES; + + /* Co-routine MUST start with a call to crSTART. */ + crSTART( xHandle ); + + for(;;) + { + /* Was the previously transmitted string received correctly? */ + if( uxCommsErrorStatus != pdPASS ) + { + /* An error was encountered so set the error LED. */ + vParTestSetLED( commsFAIL_LED, pdTRUE ); + } + + /* The next character to Tx is the first in the string. */ + cNextChar = commsFIRST_TX_CHAR; + + UARTIntDisable( UART0_BASE, UART_INT_TX ); + { + /* Send the first character. */ + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + + /* Move the variable to the char to Tx on so the ISR transmits + the next character in the string once this one has completed. */ + cNextChar++; + } + UARTIntEnable(UART0_BASE, UART_INT_TX); + + /* Toggle the LED to show a new string is being transmitted. */ + vParTestToggleLED( commsTX_LED ); + + /* Delay before we start the string off again. A pseudo-random delay + is used as this will provide a better test. */ + xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes ); + + pulRandomBytes++; + if( pulRandomBytes > commsTOTAL_PROGRAM_MEMORY ) + { + pulRandomBytes = commsFIRST_PROGRAM_BYTES; + } + + /* Make sure we don't wait too long... */ + xDelayPeriod &= commsMAX_TX_DELAY; + + /* ...but we do want to wait. */ + if( xDelayPeriod < commsMIN_TX_DELAY ) + { + xDelayPeriod = commsMIN_TX_DELAY; + } + + /* Block for the random(ish) time. */ + crDELAY( xHandle, xDelayPeriod ); + } + + /* Co-routine MUST end with a call to crEND. */ + crEND(); +} +/*-----------------------------------------------------------*/ + +void vUART_ISR( void ) +{ +unsigned portLONG ulStatus; +portCHAR cRxedChar; +portBASE_TYPE xTaskWokenByPost = pdFALSE; + + /* What caused the interrupt. */ + ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); + + /* Clear the interrupt. */ + UARTIntClear( UART0_BASE, ulStatus ); + + /* Was an Rx interrpt pending? */ + if( ulStatus & UART_INT_RX ) + { + if( ( HWREG(UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) ) + { + /* Get the char from the buffer and post it onto the queue of + Rxed chars. Posting the character should wake the task that is + blocked on the queue waiting for characters. */ + cRxedChar = ( portCHAR ) HWREG( UART0_BASE + UART_O_DR ); + xTaskWokenByPost = xQueueSendFromISR( xCommsQueue, &cRxedChar, xTaskWokenByPost ); + } + } + + /* Was a Tx interrupt pending? */ + if( ulStatus & UART_INT_TX ) + { + /* Send the next character in the string. We are not using the FIFO. */ + if( cNextChar <= commsLAST_TX_CHAR ) + { + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = cNextChar; + } + cNextChar++; + } + } + + if( xTaskWokenByPost ) + { + /* If a task was woken by the character being received then we force + a context switch to occur in case the task is of higher priority than + the currently executing task (i.e. the task that this interrupt + interrupted.) */ + portEND_SWITCHING_ISR( xTaskWokenByPost ); + } +} +/*-----------------------------------------------------------*/ + +void vCommsRxTask( void * pvParameters ) +{ +static portCHAR cRxedChar, cExpectedChar; + + /* Set the char we expect to receive to the start of the string. */ + cExpectedChar = commsFIRST_TX_CHAR; + + for( ;; ) + { + /* Wait for a character to be received. */ + xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, commsRX_DELAY ); + + /* Was the character recived (if any) the expected character. */ + if( cRxedChar != cExpectedChar ) + { + /* Got an unexpected character. This can sometimes occur when + reseting the system using the debugger leaving characters already + in the UART regsters. */ + uxCommsErrorStatus = pdFAIL; + + /* Resync by waiting for the end of the current string. */ + while( cRxedChar != commsLAST_TX_CHAR ) + { + while( !xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, portMAX_DELAY ) ); + } + + /* The next expected character is the start of the string again. */ + cExpectedChar = commsFIRST_TX_CHAR; + } + else + { + if( cExpectedChar == commsLAST_TX_CHAR ) + { + /* We have reached the end of the string - we now expect to + receive the first character in the string again. The LED is + toggled to indicate that the entire string was received without + error. */ + vParTestToggleLED( commsRX_LED ); + cExpectedChar = commsFIRST_TX_CHAR; + } + else + { + /* We got the expected character, we now expect to receive the + next character in the string. */ + cExpectedChar++; + } + } + } +} +/*-----------------------------------------------------------*/ + +unsigned portBASE_TYPE uxGetCommsStatus( void ) +{ + return uxCommsErrorStatus; +} diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/commstest.h b/20080212/Demo/CORTEX_LM3S316_IAR/commstest.h new file mode 100644 index 000000000..ceaff1e19 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/commstest.h @@ -0,0 +1,64 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef COMMS_TEST_H +#define COMMS_TEST_H + +/* + * Initialisation routine for the UART. + */ +void vSerialInit( void ); + +/* + * The task that receives the characters from UART 0. + */ +void vCommsRxTask( void * pvParameters ); + +/* + * The co-routine that periodically initiates the transmission of the string on + * the UART. + */ +void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + +unsigned portBASE_TYPE uxGetCommsStatus( void ); + +#endif diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/DriverLib.h b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/DriverLib.h new file mode 100644 index 000000000..6374ddca6 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/DriverLib.h @@ -0,0 +1,22 @@ +#ifndef INCLUDE_DRIVER_LIB_H +#define INCLUDE_DRIVER_LIB_H + +#include "hw_ints.h" +#include "hw_uart.h" +#include "hw_memmap.h" +#include "hw_types.h" +#include "hw_nvic.h" +#include "hw_ssi.h" +#include "hw_i2c.h" +#include "hw_adc.h" + +#include "gpio.h" +#include "interrupt.h" +#include "sysctl.h" +#include "uart.h" +#include "ssi.h" +#include "pdc.h" +#include "i2c.h" +#include "adc.h" + +#endif diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/EULA.txt b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/EULA.txt new file mode 100644 index 000000000..cba31f7dc --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/EULA.txt @@ -0,0 +1,126 @@ +IMPORTANT. Read the following LMI Software License Agreement ("Agreement") +completely. + +LUMINARY MICRO SOFTWARE LICENSE AGREEMENT + + This is a legal agreement between you (either as an individual or as an +authorized representative of your employer) and Luminary Micro, Inc. ("LMI"). +It concerns your rights to use this file and any accompanying written materials +(the "Software"). In consideration for LMI allowing you to access the +Software, you are agreeing to be bound by the terms of this Agreement. If you +do not agree to all of the terms of this Agreement, do not download or use the +Software. If you change your mind later, stop using the Software and delete +all copies of the Software in your possession or control. Any copies of the +Software that you have already distributed, where permitted, and do not destroy +will continue to be governed by this Agreement. Your prior use will also +continue to be governed by this Agreement. + +1. LICENSE GRANT. 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If any provision of this Agreement is held for any +reason to be invalid or unenforceable, then the remaining provisions of this +Agreement will be unimpaired and, unless a modification or replacement of the +invalid or unenforceable provision is further held to deprive you or LMI of a +material benefit, in which case the Agreement will immediately terminate, the +invalid or unenforceable provision will be replaced with a provision that is +valid and enforceable and that comes closest to the intention underlying the +invalid or unenforceable provision. + +14. NO WAIVER. The waiver by LMI of any breach of any provision of this +Agreement will not operate or be construed as a waiver of any other or a +subsequent breach of the same or a different provision. diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/adc.h b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/adc.h new file mode 100644 index 000000000..1825664a3 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/adc.h @@ -0,0 +1,120 @@ +//***************************************************************************** +// +// adc.h - ADC headers for using the ADC driver functions. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __ADC_H__ +#define __ADC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to ADCSequenceConfigure as the ulTrigger +// parameter. +// +//***************************************************************************** +#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event +#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event +#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event +#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event +#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event +#define ADC_TRIGGER_TIMER 0x00000005 // Timer event +#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event +#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event +#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event +#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event + +//***************************************************************************** +// +// Values that can be passed to ADCSequenceStepConfigure as the ulConfig +// parameter. +// +//***************************************************************************** +#define ADC_CTL_TS 0x00000080 // Temperature sensor select +#define ADC_CTL_IE 0x00000040 // Interrupt enable +#define ADC_CTL_END 0x00000020 // Sequence end select +#define ADC_CTL_D 0x00000010 // Differential select +#define ADC_CTL_CH0 0x00000000 // Input channel 0 +#define ADC_CTL_CH1 0x00000001 // Input channel 1 +#define ADC_CTL_CH2 0x00000002 // Input channel 2 +#define ADC_CTL_CH3 0x00000003 // Input channel 3 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum, + void (*pfnHandler)(void)); +extern void ADCIntUnregister(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum); +extern void ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum); +extern unsigned long ADCIntStatus(unsigned long ulBase, + unsigned long ulSequenceNum, + tBoolean bMasked); +extern void ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum); +extern void ADCSequenceEnable(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCSequenceDisable(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCSequenceConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulTrigger, + unsigned long ulPriority); +extern void ADCSequenceStepConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulStep, + unsigned long ulConfig); +extern long ADCSequenceOverflow(unsigned long ulBase, + unsigned long ulSequenceNum); +extern long ADCSequenceUnderflow(unsigned long ulBase, + unsigned long ulSequenceNum); +extern long ADCSequenceDataGet(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long *pulBuffer); +extern void ADCProcessorTrigger(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCSoftwareOversampleConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulFactor); +extern void ADCSoftwareOversampleStepConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulStep, + unsigned long ulConfig); +extern void ADCSoftwareOversampleDataGet(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long *pulBuffer, + unsigned long ulCount); + +#ifdef __cplusplus +} +#endif + +#endif // __ADC_H__ diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/asmdefs.h b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/asmdefs.h new file mode 100644 index 000000000..4a1018a64 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/asmdefs.h @@ -0,0 +1,130 @@ +//***************************************************************************** +// +// asmdefs.h - Macros to allow assembly code be portable among toolchains. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __ASMDEFS_H__ +#define __ASMDEFS_H__ + +//***************************************************************************** +// +// The defines required for EW-ARM. +// +//***************************************************************************** +#ifdef ewarm + +// +// Section headers. +// +#define __TEXT__ rseg CODE:CODE(2) +#define __DATA__ rseg DATA:DATA(2) +#define __BSS__ rseg DATA:DATA(2) + +// +// Assembler nmenonics. +// +#define __ALIGN__ alignrom 4 +#define __END__ end +#define __EXPORT__ export +#define __IMPORT__ import +#define __LABEL__ +#define __STR__ dcb +#define __THUMB_LABEL__ +#define __WORD__ dcd + +#endif // ewarm + +//***************************************************************************** +// +// The defines required for GCC. +// +//***************************************************************************** +#ifdef gcc + +// +// The assembly code preamble required to put the assembler into the correct +// configuration. +// + .syntax unified + .thumb + +// +// Section headers. +// +#define __TEXT__ .text +#define __DATA__ .data +#define __BSS__ .bss + +// +// Assembler nmenonics. +// +#define __ALIGN__ .balign 4 +#define __END__ .end +#define __EXPORT__ .globl +#define __IMPORT__ .extern +#define __LABEL__ : +#define __STR__ .ascii +#define __THUMB_LABEL__ .thumb_func +#define __WORD__ .word + +#endif // gcc + +//***************************************************************************** +// +// The defines required for RV-MDK. +// +//***************************************************************************** +#ifdef rvmdk + +// +// The assembly code preamble required to put the assembler into the correct +// configuration. +// + thumb + require8 + preserve8 + +// +// Section headers. +// +#define __TEXT__ area ||.text||, code, readonly, align=2 +#define __DATA__ area ||.data||, data, align=2 +#define __BSS__ area ||.bss||, noinit, align=2 + +// +// Assembler nmenonics. +// +#define __ALIGN__ align 4 +#define __END__ end +#define __EXPORT__ export +#define __IMPORT__ import +#define __LABEL__ +#define __STR__ dcb +#define __THUMB_LABEL__ +#define __WORD__ dcd + +#endif // rvmdk + +#endif // __ASMDEF_H__ diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/comp.h b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/comp.h new file mode 100644 index 000000000..19eda38cc --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/comp.h @@ -0,0 +1,120 @@ +//***************************************************************************** +// +// comp.h - Prototypes for the analog comparator driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __COMP_H__ +#define __COMP_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to ComparatorConfigure() as the ulConfig +// parameter. For each group (i.e. COMP_TRIG_xxx, COMP_INT_xxx, etc.), one of +// the values may be selected and ORed together will values from the other +// groups. +// +//***************************************************************************** +#define COMP_TRIG_NONE 0x00000000 // No ADC trigger +#define COMP_TRIG_HIGH 0x00000880 // Trigger when high +#define COMP_TRIG_LOW 0x00000800 // Trigger when low +#define COMP_TRIG_FALL 0x00000820 // Trigger on falling edge +#define COMP_TRIG_RISE 0x00000840 // Trigger on rising edge +#define COMP_TRIG_BOTH 0x00000860 // Trigger on both edges +#define COMP_INT_HIGH 0x00000010 // Interrupt when high +#define COMP_INT_LOW 0x00000000 // Interrupt when low +#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge +#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge +#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges +#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin +#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin +#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference +#define COMP_OUTPUT_NONE 0x00000000 // No comparator output +#define COMP_OUTPUT_NORMAL 0x00000100 // Comparator output normal +#define COMP_OUTPUT_INVERT 0x00000102 // Comparator output inverted + +//***************************************************************************** +// +// Values that can be passed to ComparatorSetRef() as the ulRef parameter. +// +//***************************************************************************** +#define COMP_REF_OFF 0x00000000 // Turn off the internal reference +#define COMP_REF_0V 0x00000300 // Internal reference of 0V +#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V +#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V +#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V +#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V +#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V +#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V +#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V +#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V +#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V +#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V +#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V +#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V +#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V +#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V +#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V +#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V +#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V +#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V +#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V +#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V +#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V +#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V +#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V +#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V +#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V +#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V +#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp, + unsigned long ulConfig); +extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef); +extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp); +extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp, + void (*pfnHandler)(void)); +extern void ComparatorIntUnregister(unsigned long ulBase, + unsigned long ulComp); +extern void ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp); +extern void ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp); +extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp, + tBoolean bMasked); +extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp); + +#ifdef __cplusplus +} +#endif + +#endif // __COMP_H__ diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/cpu.h b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/cpu.h new file mode 100644 index 000000000..0a2e282c3 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/cpu.h @@ -0,0 +1,40 @@ +//***************************************************************************** +// +// cpu.h - Prototypes for the CPU instruction wrapper functions. +// +// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __CPU_H__ +#define __CPU_H__ + +//***************************************************************************** +// +// Prototypes. +// +//***************************************************************************** +extern void CPUcpsid(void); +extern void CPUcpsie(void); +extern void CPUwfi(void); + +#endif // __CPU_H__ diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/cspy.c b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/cspy.c new file mode 100644 index 000000000..398ae5949 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/cspy.c @@ -0,0 +1,119 @@ +//***************************************************************************** +// +// cspy.c - Routines for simply ignoring the debugger communciation APIs in +// C-Spy for now. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#include "diag.h" + +//***************************************************************************** +// +// Open a handle for stdio functions (both stdin and stdout). +// +//***************************************************************************** +int +DiagOpenStdio(void) +{ + return(-1); +} + +//***************************************************************************** +// +// Open a host file system file. +// +//***************************************************************************** +int +DiagOpen(const char *pcName, int iMode) +{ + return(-1); +} + +//***************************************************************************** +// +// Close a host file system file. +// +//***************************************************************************** +int +DiagClose(int iHandle) +{ + return(-1); +} + +//***************************************************************************** +// +// Write data to a host file system file. +// +//***************************************************************************** +int +DiagWrite(int iHandle, const char *pcBuf, unsigned long ulLen, int iMode) +{ + return(-1); +} + +//***************************************************************************** +// +// Read data from a host file system file. +// +//***************************************************************************** +int +DiagRead(int iHandle, char *pcBuf, unsigned long ulLen, int iMode) +{ + return(-1); +} + +//***************************************************************************** +// +// Get the length of a host file system file. +// +//***************************************************************************** +long +DiagFlen(int iHandle) +{ + return(-1); +} + +//***************************************************************************** +// +// Terminate the application. +// +//***************************************************************************** +void +DiagExit(int iRet) +{ + while(1) + { + } +} + +//***************************************************************************** +// +// Get the command line arguments from the debugger. +// +//***************************************************************************** +char * +DiagCommandString(char *pcBuf, unsigned long ulLen) +{ + return(0); +} diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/debug.h b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/debug.h new file mode 100644 index 000000000..83dbbf3c4 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/debug.h @@ -0,0 +1,56 @@ +//***************************************************************************** +// +// debug.h - Macros for assisting debug of the driver library. +// +// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __DEBUG_H__ +#define __DEBUG_H__ + +//***************************************************************************** +// +// Prototype for the function that is called when an invalid argument is passed +// to an API. This is only used when doing a DEBUG build. +// +//***************************************************************************** +extern void __error__(char *pcFilename, unsigned long ulLine); + +//***************************************************************************** +// +// The ASSERT macro, which does the actual assertion checking. Typically, this +// will be for procedure arguments. +// +//***************************************************************************** +#ifdef DEBUG +#define ASSERT(expr) { \ + if(!(expr)) \ + { \ + __error__(__FILE__, __LINE__); \ + } \ + } +#else +#define ASSERT(expr) +#endif + +#endif // __DEBUG_H__ diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/diag.h b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/diag.h new file mode 100644 index 000000000..5eda186eb --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/diag.h @@ -0,0 +1,67 @@ +//***************************************************************************** +// +// diag.h - Prototypes for the diagnostic functions. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __DIAG_H__ +#define __DIAG_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed as the iMode parater to DiagOpen, DiagRead, and +// DiagWrite. +// +//***************************************************************************** +#define OPEN_R 0 // read access +#define OPEN_W 4 // write access +#define OPEN_A 8 // append to file +#define OPEN_B 1 // binary access +#define OPEN_PLUS 2 // read and write access + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern int DiagOpenStdio(void); +extern int DiagOpen(const char *pcName, int iMode); +extern int DiagClose(int iHandle); +extern int DiagWrite(int iHandle, const char *pcBuf, unsigned long ulLen, + int iMode); +extern int DiagRead(int iHandle, char *pcBuf, unsigned long ulLen, int iMode); +extern long DiagFlen(int iHandle); +extern void DiagExit(int iRet); +extern char *DiagCommandString(char *pcBuf, unsigned long ulLen); + +#ifdef __cplusplus +} +#endif + +#endif // __DIAG_H__ diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/driverlib.r79 b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/driverlib.r79 new file mode 100644 index 0000000000000000000000000000000000000000..188c42ebb71a9ca5bd84c6648549f09eb0c60ff3 GIT binary patch literal 125749 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--git a/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/flash.h b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/flash.h new file mode 100644 index 000000000..72202763d --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/flash.h @@ -0,0 +1,75 @@ +//***************************************************************************** +// +// flash.h - Prototypes for the flash driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __FLASH_H__ +#define __FLASH_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to FlashProtectSet(), and returned by +// FlashProtectGet(). +// +//***************************************************************************** +typedef enum +{ + FlashReadWrite, // Flash can be read and written + FlashReadOnly, // Flash can only be read + FlashExecuteOnly // Flash can only be executed +} +tFlashProtection; + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern unsigned long FlashUsecGet(void); +extern void FlashUsecSet(unsigned long ulClocks); +extern long FlashErase(unsigned long ulAddress); +extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress, + unsigned long ulCount); +extern tFlashProtection FlashProtectGet(unsigned long ulAddress); +extern long FlashProtectSet(unsigned long ulAddress, + tFlashProtection eProtect); +extern long FlashProtectSave(void); +extern void FlashIntRegister(void (*pfnHandler)(void)); +extern void FlashIntUnregister(void); +extern void FlashIntEnable(unsigned long ulIntFlags); +extern void FlashIntDisable(unsigned long ulIntFlags); +extern unsigned long FlashIntGetStatus(tBoolean bMasked); +extern void FlashIntClear(unsigned long ulIntFlags); + +#ifdef __cplusplus +} +#endif + +#endif // __FLASH_H__ diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/gpio.h b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/gpio.h new file mode 100644 index 000000000..598fec8a8 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/gpio.h @@ -0,0 +1,136 @@ +//***************************************************************************** +// +// gpio.h - Defines and Macros for GPIO API. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __GPIO_H__ +#define __GPIO_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following values define the bit field for the ucPins argument to several +// of the APIs. +// +//***************************************************************************** +#define GPIO_PIN_0 0x00000001 // GPIO pin 0 +#define GPIO_PIN_1 0x00000002 // GPIO pin 1 +#define GPIO_PIN_2 0x00000004 // GPIO pin 2 +#define GPIO_PIN_3 0x00000008 // GPIO pin 3 +#define GPIO_PIN_4 0x00000010 // GPIO pin 4 +#define GPIO_PIN_5 0x00000020 // GPIO pin 5 +#define GPIO_PIN_6 0x00000040 // GPIO pin 6 +#define GPIO_PIN_7 0x00000080 // GPIO pin 7 + +//***************************************************************************** +// +// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and +// returned from GPIODirModeGet. +// +//***************************************************************************** +#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input +#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output +#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function + +//***************************************************************************** +// +// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and +// returned from GPIOIntTypeGet. +// +//***************************************************************************** +#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge +#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge +#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges +#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level +#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level + +//***************************************************************************** +// +// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter, +// and returned by GPIOPadConfigGet in the *pulStrength parameter. +// +//***************************************************************************** +#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength +#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength +#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength +#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control + +//***************************************************************************** +// +// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter, +// and returned by GPIOPadConfigGet in the *pulPadType parameter. +// +//***************************************************************************** +#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull +#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up +#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down +#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain +#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up +#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down +#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulPinIO); +extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin); +extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulIntType); +extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin); +extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulStrength, + unsigned long ulPadType); +extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin, + unsigned long *pulStrength, + unsigned long *pulPadType); +extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins); +extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked); +extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPortIntRegister(unsigned long ulPort, + void (*pfIntHandler)(void)); +extern void GPIOPortIntUnregister(unsigned long ulPort); +extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, + unsigned char ucVal); +extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins); + +#ifdef __cplusplus +} +#endif + +#endif // __GPIO_H__ diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/hw_adc.h b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/hw_adc.h new file mode 100644 index 000000000..36b820467 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/hw_adc.h @@ -0,0 +1,329 @@ +//***************************************************************************** +// +// hw_adc.h - Macros used when accessing the ADC hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_ADC_H__ +#define __HW_ADC_H__ + +//***************************************************************************** +// +// The following define the offsets of the ADC registers. +// +//***************************************************************************** +#define ADC_O_ACTSS 0x00000000 // Active sample register +#define ADC_O_RIS 0x00000004 // Raw interrupt status register +#define ADC_O_IM 0x00000008 // Interrupt mask register +#define ADC_O_ISC 0x0000000C // Interrupt status/clear register +#define ADC_O_OSTAT 0x00000010 // Overflow status register +#define ADC_O_EMUX 0x00000014 // Event multiplexer select reg. +#define ADC_O_USTAT 0x00000018 // Underflow status register +#define ADC_O_SSPRI 0x00000020 // Channel priority register +#define ADC_O_PSSI 0x00000028 // Processor sample initiate reg. +#define ADC_O_SSMUX0 0x00000040 // Multiplexer select 0 register +#define ADC_O_SSCTL0 0x00000044 // Sample sequence control 0 reg. +#define ADC_O_SSFIFO0 0x00000048 // Result FIFO 0 register +#define ADC_O_SSFSTAT0 0x0000004C // FIFO 0 status register +#define ADC_O_SSMUX1 0x00000060 // Multiplexer select 1 register +#define ADC_O_SSCTL1 0x00000064 // Sample sequence control 1 reg. +#define ADC_O_SSFIFO1 0x00000068 // Result FIFO 1 register +#define ADC_O_SSFSTAT1 0x0000006C // FIFO 1 status register +#define ADC_O_SSMUX2 0x00000080 // Multiplexer select 2 register +#define ADC_O_SSCTL2 0x00000084 // Sample sequence control 2 reg. +#define ADC_O_SSFIFO2 0x00000088 // Result FIFO 2 register +#define ADC_O_SSFSTAT2 0x0000008C // FIFO 2 status register +#define ADC_O_SSMUX3 0x000000A0 // Multiplexer select 3 register +#define ADC_O_SSCTL3 0x000000A4 // Sample sequence control 3 reg. +#define ADC_O_SSFIFO3 0x000000A8 // Result FIFO 3 register +#define ADC_O_SSFSTAT3 0x000000AC // FIFO 3 status register +#define ADC_O_TMLB 0x00000100 // Test mode loopback register + +//***************************************************************************** +// +// The following define the offsets of the ADC sequence registers. +// +//***************************************************************************** +#define ADC_O_SEQ 0x00000040 // Offset to the first sequence +#define ADC_O_SEQ_STEP 0x00000020 // Increment to the next sequence +#define ADC_O_X_SSMUX 0x00000000 // Multiplexer select register +#define ADC_O_X_SSCTL 0x00000004 // Sample sequence control register +#define ADC_O_X_SSFIFO 0x00000008 // Result FIFO register +#define ADC_O_X_SSFSTAT 0x0000000C // FIFO status register + +//***************************************************************************** +// +// The following define the bit fields in the ADC_ACTSS register. +// +//***************************************************************************** +#define ADC_ACTSS_ASEN3 0x00000008 // Sample sequence 3 enable +#define ADC_ACTSS_ASEN2 0x00000004 // Sample sequence 2 enable +#define ADC_ACTSS_ASEN1 0x00000002 // Sample sequence 1 enable +#define ADC_ACTSS_ASEN0 0x00000001 // Sample sequence 0 enable + +//***************************************************************************** +// +// The following define the bit fields in the ADC_RIS register. +// +//***************************************************************************** +#define ADC_RIS_INR3 0x00000008 // Sample sequence 3 interrupt +#define ADC_RIS_INR2 0x00000004 // Sample sequence 2 interrupt +#define ADC_RIS_INR1 0x00000002 // Sample sequence 1 interrupt +#define ADC_RIS_INR0 0x00000001 // Sample sequence 0 interrupt + +//***************************************************************************** +// +// The following define the bit fields in the ADC_IM register. +// +//***************************************************************************** +#define ADC_IM_MASK3 0x00000008 // Sample sequence 3 mask +#define ADC_IM_MASK2 0x00000004 // Sample sequence 2 mask +#define ADC_IM_MASK1 0x00000002 // Sample sequence 1 mask +#define ADC_IM_MASK0 0x00000001 // Sample sequence 0 mask + +//***************************************************************************** +// +// The following define the bit fields in the ADC_ISC register. +// +//***************************************************************************** +#define ADC_ISC_IN3 0x00000008 // Sample sequence 3 interrupt +#define ADC_ISC_IN2 0x00000004 // Sample sequence 2 interrupt +#define ADC_ISC_IN1 0x00000002 // Sample sequence 1 interrupt +#define ADC_ISC_IN0 0x00000001 // Sample sequence 0 interrupt + +//***************************************************************************** +// +// The following define the bit fields in the ADC_OSTAT register. +// +//***************************************************************************** +#define ADC_OSTAT_OV3 0x00000008 // Sample sequence 3 overflow +#define ADC_OSTAT_OV2 0x00000004 // Sample sequence 2 overflow +#define ADC_OSTAT_OV1 0x00000002 // Sample sequence 1 overflow +#define ADC_OSTAT_OV0 0x00000001 // Sample sequence 0 overflow + +//***************************************************************************** +// +// The following define the bit fields in the ADC_EMUX register. +// +//***************************************************************************** +#define ADC_EMUX_EM3_MASK 0x0000F000 // Event mux 3 mask +#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor event +#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog comparator 0 event +#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog comparator 1 event +#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog comparator 2 event +#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External event +#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer event +#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0 event +#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1 event +#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2 event +#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always event +#define ADC_EMUX_EM2_MASK 0x00000F00 // Event mux 2 mask +#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor event +#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog comparator 0 event +#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog comparator 1 event +#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog comparator 2 event +#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External event +#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer event +#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0 event +#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1 event +#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2 event +#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always event +#define ADC_EMUX_EM1_MASK 0x000000F0 // Event mux 1 mask +#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor event +#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog comparator 0 event +#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog comparator 1 event +#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog comparator 2 event +#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External event +#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer event +#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0 event +#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1 event +#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2 event +#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always event +#define ADC_EMUX_EM0_MASK 0x0000000F // Event mux 0 mask +#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor event +#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog comparator 0 event +#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog comparator 1 event +#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog comparator 2 event +#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External event +#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer event +#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0 event +#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1 event +#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2 event +#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always event +#define ADC_EMUX_EM0_SHIFT 0 // The shift for the first event +#define ADC_EMUX_EM1_SHIFT 4 // The shift for the second event +#define ADC_EMUX_EM2_SHIFT 8 // The shift for the third event +#define ADC_EMUX_EM3_SHIFT 12 // The shift for the fourth event + +//***************************************************************************** +// +// The following define the bit fields in the ADC_USTAT register. +// +//***************************************************************************** +#define ADC_USTAT_UV3 0x00000008 // Sample sequence 3 underflow +#define ADC_USTAT_UV2 0x00000004 // Sample sequence 2 underflow +#define ADC_USTAT_UV1 0x00000002 // Sample sequence 1 underflow +#define ADC_USTAT_UV0 0x00000001 // Sample sequence 0 underflow + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SSPRI register. +// +//***************************************************************************** +#define ADC_SSPRI_SS3_MASK 0x00003000 // Sequencer 3 priority mask +#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority +#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority +#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority +#define ADC_SSPRI_SS2_MASK 0x00000300 // Sequencer 2 priority mask +#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority +#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority +#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority +#define ADC_SSPRI_SS1_MASK 0x00000030 // Sequencer 1 priority mask +#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority +#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority +#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority +#define ADC_SSPRI_SS0_MASK 0x00000003 // Sequencer 0 priority mask +#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority +#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority +#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority + +//***************************************************************************** +// +// The following define the bit fields in the ADC_PSSI register. +// +//***************************************************************************** +#define ADC_PSSI_SS3 0x00000008 // Trigger sample sequencer 3 +#define ADC_PSSI_SS2 0x00000004 // Trigger sample sequencer 2 +#define ADC_PSSI_SS1 0x00000002 // Trigger sample sequencer 1 +#define ADC_PSSI_SS0 0x00000001 // Trigger sample sequencer 0 + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SSMUX0, ADC_SSMUX1, +// ADC_SSMUX2, and ADC_SSMUX3 registers. Not all fields are present in all +// registers. +// +//***************************************************************************** +#define ADC_SSMUX_MUX7_MASK 0x30000000 // 8th mux select mask +#define ADC_SSMUX_MUX6_MASK 0x03000000 // 7th mux select mask +#define ADC_SSMUX_MUX5_MASK 0x00300000 // 6th mux select mask +#define ADC_SSMUX_MUX4_MASK 0x00030000 // 5th mux select mask +#define ADC_SSMUX_MUX3_MASK 0x00003000 // 4th mux select mask +#define ADC_SSMUX_MUX2_MASK 0x00000300 // 3rd mux select mask +#define ADC_SSMUX_MUX1_MASK 0x00000030 // 2nd mux select mask +#define ADC_SSMUX_MUX0_MASK 0x00000003 // 1st mux select mask +#define ADC_SSMUX_MUX7_SHIFT 28 +#define ADC_SSMUX_MUX6_SHIFT 24 +#define ADC_SSMUX_MUX5_SHIFT 20 +#define ADC_SSMUX_MUX4_SHIFT 16 +#define ADC_SSMUX_MUX3_SHIFT 12 +#define ADC_SSMUX_MUX2_SHIFT 8 +#define ADC_SSMUX_MUX1_SHIFT 4 +#define ADC_SSMUX_MUX0_SHIFT 0 + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SSCTL0, ADC_SSCTL1, +// ADC_SSCTL2, and ADC_SSCTL3 registers. Not all fields are present in all +// registers. +// +//***************************************************************************** +#define ADC_SSCTL_TS7 0x80000000 // 8th temperature sensor select +#define ADC_SSCTL_IE7 0x40000000 // 8th interrupt enable +#define ADC_SSCTL_END7 0x20000000 // 8th sequence end select +#define ADC_SSCTL_D7 0x10000000 // 8th differential select +#define ADC_SSCTL_TS6 0x08000000 // 7th temperature sensor select +#define ADC_SSCTL_IE6 0x04000000 // 7th interrupt enable +#define ADC_SSCTL_END6 0x02000000 // 7th sequence end select +#define ADC_SSCTL_D6 0x01000000 // 7th differential select +#define ADC_SSCTL_TS5 0x00800000 // 6th temperature sensor select +#define ADC_SSCTL_IE5 0x00400000 // 6th interrupt enable +#define ADC_SSCTL_END5 0x00200000 // 6th sequence end select +#define ADC_SSCTL_D5 0x00100000 // 6th differential select +#define ADC_SSCTL_TS4 0x00080000 // 5th temperature sensor select +#define ADC_SSCTL_IE4 0x00040000 // 5th interrupt enable +#define ADC_SSCTL_END4 0x00020000 // 5th sequence end select +#define ADC_SSCTL_D4 0x00010000 // 5th differential select +#define ADC_SSCTL_TS3 0x00008000 // 4th temperature sensor select +#define ADC_SSCTL_IE3 0x00004000 // 4th interrupt enable +#define ADC_SSCTL_END3 0x00002000 // 4th sequence end select +#define ADC_SSCTL_D3 0x00001000 // 4th differential select +#define ADC_SSCTL_TS2 0x00000800 // 3rd temperature sensor select +#define ADC_SSCTL_IE2 0x00000400 // 3rd interrupt enable +#define ADC_SSCTL_END2 0x00000200 // 3rd sequence end select +#define ADC_SSCTL_D2 0x00000100 // 3rd differential select +#define ADC_SSCTL_TS1 0x00000080 // 2nd temperature sensor select +#define ADC_SSCTL_IE1 0x00000040 // 2nd interrupt enable +#define ADC_SSCTL_END1 0x00000020 // 2nd sequence end select +#define ADC_SSCTL_D1 0x00000010 // 2nd differential select +#define ADC_SSCTL_TS0 0x00000008 // 1st temperature sensor select +#define ADC_SSCTL_IE0 0x00000004 // 1st interrupt enable +#define ADC_SSCTL_END0 0x00000002 // 1st sequence end select +#define ADC_SSCTL_D0 0x00000001 // 1st differential select + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SSFIFO0, ADC_SSFIFO1, +// ADC_SSFIFO2, and ADC_SSFIFO3 registers. +// +//***************************************************************************** +#define ADC_SSFIFO_DATA_MASK 0x000003FF // Sample data +#define ADC_SSFIFO_DATA_SHIFT 0 + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SSFSTAT0, ADC_SSFSTAT1, +// ADC_SSFSTAT2, and ADC_SSFSTAT3 registers. +// +//***************************************************************************** +#define ADC_SSFSTAT_FULL 0x00001000 // FIFO is full +#define ADC_SSFSTAT_EMPTY 0x00000100 // FIFO is empty +#define ADC_SSFSTAT_HPTR 0x000000F0 // FIFO head pointer +#define ADC_SSFSTAT_TPTR 0x0000000F // FIFO tail pointer + +//***************************************************************************** +// +// The following define the bit fields in the ADC_TMLB register. +// +//***************************************************************************** +#define ADC_TMLB_LB 0x00000001 // Loopback control signals + +//***************************************************************************** +// +// The following define the bit fields in the loopback ADC data. +// +//***************************************************************************** +#define ADC_LB_CNT_MASK 0x000003C0 // Sample counter mask +#define ADC_LB_CONT 0x00000020 // Continuation sample +#define ADC_LB_DIFF 0x00000010 // Differential sample +#define ADC_LB_TS 0x00000008 // Temperature sensor sample +#define ADC_LB_MUX_MASK 0x00000007 // Input channel number mask +#define ADC_LB_CNT_SHIFT 6 // Sample counter shift +#define ADC_LB_MUX_SHIFT 0 // Input channel number shift + +#endif // __HW_ADC_H__ diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/hw_comp.h b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/hw_comp.h new file mode 100644 index 000000000..02487e6e8 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/hw_comp.h @@ -0,0 +1,118 @@ +//***************************************************************************** +// +// hw_comp.h - Macros used when accessing the comparator hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_COMP_H__ +#define __HW_COMP_H__ + +//***************************************************************************** +// +// The following define the offsets of the comparator registers. +// +//***************************************************************************** +#define COMP_O_MIS 0x00000000 // Interrupt status register +#define COMP_O_RIS 0x00000004 // Raw interrupt status register +#define COMP_O_INTEN 0x00000008 // Interrupt enable register +#define COMP_O_REFCTL 0x00000010 // Reference voltage control reg. +#define COMP_O_ACSTAT0 0x00000020 // Comp0 status register +#define COMP_O_ACCTL0 0x00000024 // Comp0 control register +#define COMP_O_ACSTAT1 0x00000040 // Comp1 status register +#define COMP_O_ACCTL1 0x00000044 // Comp1 control register +#define COMP_O_ACSTAT2 0x00000060 // Comp2 status register +#define COMP_O_ACCTL2 0x00000064 // Comp2 control register + +//***************************************************************************** +// +// The following define the bit fields in the COMP_MIS, COMP_RIS, and +// COMP_INTEN registers. +// +//***************************************************************************** +#define COMP_INT_2 0x00000004 // Comp2 interrupt +#define COMP_INT_1 0x00000002 // Comp1 interrupt +#define COMP_INT_0 0x00000001 // Comp0 interrupt + +//***************************************************************************** +// +// The following define the bit fields in the COMP_REFCTL register. +// +//***************************************************************************** +#define COMP_REFCTL_EN 0x00000200 // Reference voltage enable +#define COMP_REFCTL_RNG 0x00000100 // Reference voltage range +#define COMP_REFCTL_VREF_MASK 0x0000000F // Reference voltage select mask +#define COMP_REFCTL_VREF_SHIFT 0 + +//***************************************************************************** +// +// The following define the bit fields in the COMP_ACSTAT0, COMP_ACSTAT1, and +// COMP_ACSTAT2 registers. +// +//***************************************************************************** +#define COMP_ACSTAT_OVAL 0x00000002 // Comparator output value + +//***************************************************************************** +// +// The following define the bit fields in the COMP_ACCTL0, COMP_ACCTL1, and +// COMP_ACCTL2 registers. +// +//***************************************************************************** +#define COMP_ACCTL_TMASK 0x00000800 // Trigger enable +#define COMP_ACCTL_ASRCP_MASK 0x00000600 // Vin+ source select mask +#define COMP_ACCTL_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin +#define COMP_ACCTL_ASRCP_PIN0 0x00000200 // Comp0+ pin +#define COMP_ACCTL_ASRCP_REF 0x00000400 // Internal voltage reference +#define COMP_ACCTL_ASRCP_RES 0x00000600 // Reserved +#define COMP_ACCTL_OEN 0x00000100 // Comparator output enable +#define COMP_ACCTL_TSVAL 0x00000080 // Trigger polarity select +#define COMP_ACCTL_TSEN_MASK 0x00000060 // Trigger sense mask +#define COMP_ACCTL_TSEN_LEVEL 0x00000000 // Trigger is level sense +#define COMP_ACCTL_TSEN_FALL 0x00000020 // Trigger is falling edge +#define COMP_ACCTL_TSEN_RISE 0x00000040 // Trigger is rising edge +#define COMP_ACCTL_TSEN_BOTH 0x00000060 // Trigger is both edges +#define COMP_ACCTL_ISLVAL 0x00000010 // Interrupt polarity select +#define COMP_ACCTL_ISEN_MASK 0x0000000C // Interrupt sense mask +#define COMP_ACCTL_ISEN_LEVEL 0x00000000 // Interrupt is level sense +#define COMP_ACCTL_ISEN_FALL 0x00000004 // Interrupt is falling edge +#define COMP_ACCTL_ISEN_RISE 0x00000008 // Interrupt is rising edge +#define COMP_ACCTL_ISEN_BOTH 0x0000000C // Interrupt is both edges +#define COMP_ACCTL_CINV 0x00000002 // Comparator output invert + +//***************************************************************************** +// +// The following define the reset values for the comparator registers. +// +//***************************************************************************** +#define COMP_RV_MIS 0x00000000 // Interrupt status register +#define COMP_RV_RIS 0x00000000 // Raw interrupt status register +#define COMP_RV_INTEN 0x00000000 // Interrupt enable register +#define COMP_RV_REFCTL 0x00000000 // Reference voltage control reg. +#define COMP_RV_ACSTAT0 0x00000000 // Comp0 status register +#define COMP_RV_ACCTL0 0x00000000 // Comp0 control register +#define COMP_RV_ACSTAT1 0x00000000 // Comp1 status register +#define COMP_RV_ACCTL1 0x00000000 // Comp1 control register +#define COMP_RV_ACSTAT2 0x00000000 // Comp2 status register +#define COMP_RV_ACCTL2 0x00000000 // Comp2 control register + +#endif // __HW_COMP_H__ diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/hw_flash.h b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/hw_flash.h new file mode 100644 index 000000000..214355194 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/hw_flash.h @@ -0,0 +1,139 @@ +//***************************************************************************** +// +// hw_flash.h - Macros used when accessing the flash controller. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_FLASH_H__ +#define __HW_FLASH_H__ + +//***************************************************************************** +// +// The following define the offsets of the FLASH registers. +// +//***************************************************************************** +#define FLASH_FMA 0x400FD000 // Memory address register +#define FLASH_FMD 0x400FD004 // Memory data register +#define FLASH_FMC 0x400FD008 // Memory control register +#define FLASH_FCRIS 0x400FD00c // Raw interrupt status register +#define FLASH_FCIM 0x400FD010 // Interrupt mask register +#define FLASH_FCMISC 0x400FD014 // Interrupt status register +#define FLASH_FMPRE 0x400FE130 // FLASH read protect register +#define FLASH_FMPPE 0x400FE134 // FLASH program protect register +#define FLASH_USECRL 0x400FE140 // uSec reload register + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FMC register. +// +//***************************************************************************** +#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask +#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key +#define FLASH_FMC_COMT 0x00000008 // Commit user register +#define FLASH_FMC_MERASE 0x00000004 // Mass erase FLASH +#define FLASH_FMC_ERASE 0x00000002 // Erase FLASH page +#define FLASH_FMC_WRITE 0x00000001 // Write FLASH word + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FCRIS register. +// +//***************************************************************************** +#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status +#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FCIM register. +// +//***************************************************************************** +#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask +#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FMIS register. +// +//***************************************************************************** +#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status +#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FMPRE and FLASH_FMPPE +// registers. +// +//***************************************************************************** +#define FLASH_FMP_BLOCK_31 0x80000000 // Enable for block 31 +#define FLASH_FMP_BLOCK_30 0x40000000 // Enable for block 30 +#define FLASH_FMP_BLOCK_29 0x20000000 // Enable for block 29 +#define FLASH_FMP_BLOCK_28 0x10000000 // Enable for block 28 +#define FLASH_FMP_BLOCK_27 0x08000000 // Enable for block 27 +#define FLASH_FMP_BLOCK_26 0x04000000 // Enable for block 26 +#define FLASH_FMP_BLOCK_25 0x02000000 // Enable for block 25 +#define FLASH_FMP_BLOCK_24 0x01000000 // Enable for block 24 +#define FLASH_FMP_BLOCK_23 0x00800000 // Enable for block 23 +#define FLASH_FMP_BLOCK_22 0x00400000 // Enable for block 22 +#define FLASH_FMP_BLOCK_21 0x00200000 // Enable for block 21 +#define FLASH_FMP_BLOCK_20 0x00100000 // Enable for block 20 +#define FLASH_FMP_BLOCK_19 0x00080000 // Enable for block 19 +#define FLASH_FMP_BLOCK_18 0x00040000 // Enable for block 18 +#define FLASH_FMP_BLOCK_17 0x00020000 // Enable for block 17 +#define FLASH_FMP_BLOCK_16 0x00010000 // Enable for block 16 +#define FLASH_FMP_BLOCK_15 0x00008000 // Enable for block 15 +#define FLASH_FMP_BLOCK_14 0x00004000 // Enable for block 14 +#define FLASH_FMP_BLOCK_13 0x00002000 // Enable for block 13 +#define FLASH_FMP_BLOCK_12 0x00001000 // Enable for block 12 +#define FLASH_FMP_BLOCK_11 0x00000800 // Enable for block 11 +#define FLASH_FMP_BLOCK_10 0x00000400 // Enable for block 10 +#define FLASH_FMP_BLOCK_9 0x00000200 // Enable for block 9 +#define FLASH_FMP_BLOCK_8 0x00000100 // Enable for block 8 +#define FLASH_FMP_BLOCK_7 0x00000080 // Enable for block 7 +#define FLASH_FMP_BLOCK_6 0x00000040 // Enable for block 6 +#define FLASH_FMP_BLOCK_5 0x00000020 // Enable for block 5 +#define FLASH_FMP_BLOCK_4 0x00000010 // Enable for block 4 +#define FLASH_FMP_BLOCK_3 0x00000008 // Enable for block 3 +#define FLASH_FMP_BLOCK_2 0x00000004 // Enable for block 2 +#define FLASH_FMP_BLOCK_1 0x00000002 // Enable for block 1 +#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0 + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_USECRL register. +// +//***************************************************************************** +#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec +#define FLASH_USECRL_SHIFT 0 + +//***************************************************************************** +// +// The erase size is the size of the FLASH block that is erased by an erase +// operation, and the protect size is the size of the FLASH block that is +// protected by each protection register. +// +//***************************************************************************** +#define FLASH_ERASE_SIZE 0x00000400 +#define FLASH_PROTECT_SIZE 0x00000800 + +#endif // __HW_FLASH_H__ diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/hw_gpio.h b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/hw_gpio.h new file mode 100644 index 000000000..2f85bbc27 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/hw_gpio.h @@ -0,0 +1,103 @@ +//***************************************************************************** +// +// hw_gpio.h - Defines and Macros for GPIO hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_GPIO_H__ +#define __HW_GPIO_H__ + +//***************************************************************************** +// +// GPIO Register Offsets. +// +//***************************************************************************** +#define GPIO_O_DATA 0x00000000 // Data register. +#define GPIO_O_DIR 0x00000400 // Data direction register. +#define GPIO_O_IS 0x00000404 // Interrupt sense register. +#define GPIO_O_IBE 0x00000408 // Interrupt both edges register. +#define GPIO_O_IEV 0x0000040C // Intterupt event register. +#define GPIO_O_IM 0x00000410 // Interrupt mask register. +#define GPIO_O_RIS 0x00000414 // Raw interrupt status register. +#define GPIO_O_MIS 0x00000418 // Masked interrupt status reg. +#define GPIO_O_ICR 0x0000041C // Interrupt clear register. +#define GPIO_O_AFSEL 0x00000420 // Mode control select register. +#define GPIO_O_DR2R 0x00000500 // 2ma drive select register. +#define GPIO_O_DR4R 0x00000504 // 4ma drive select register. +#define GPIO_O_DR8R 0x00000508 // 8ma drive select register. +#define GPIO_O_ODR 0x0000050C // Open drain select register. +#define GPIO_O_PUR 0x00000510 // Pull up select register. +#define GPIO_O_PDR 0x00000514 // Pull down select register. +#define GPIO_O_SLR 0x00000518 // Slew rate control enable reg. +#define GPIO_O_DEN 0x0000051C // Digital input enable register. +#define GPIO_O_PeriphID4 0x00000FD0 // +#define GPIO_O_PeriphID5 0x00000FD4 // +#define GPIO_O_PeriphID6 0x00000FD8 // +#define GPIO_O_PeriphID7 0x00000FDC // +#define GPIO_O_PeriphID0 0x00000FE0 // +#define GPIO_O_PeriphID1 0x00000FE4 // +#define GPIO_O_PeriphID2 0x00000FE8 // +#define GPIO_O_PeriphID3 0x00000FEC // +#define GPIO_O_PCellID0 0x00000FF0 // +#define GPIO_O_PCellID1 0x00000FF4 // +#define GPIO_O_PCellID2 0x00000FF8 // +#define GPIO_O_PCellID3 0x00000FFC // + +//***************************************************************************** +// +// GPIO Register reset values. +// +//***************************************************************************** +#define GPIO_RV_DATA 0x00000000 // Data register reset value. +#define GPIO_RV_DIR 0x00000000 // Data direction reg RV. +#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV. +#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV. +#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV. +#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV. +#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV. +#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV. +#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV. +#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV. +#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV. +#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV. +#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV. +#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV. +#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV. +#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV. +#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV. +#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV. +#define GPIO_RV_PeriphID4 0x00000000 // +#define GPIO_RV_PeriphID5 0x00000000 // +#define GPIO_RV_PeriphID6 0x00000000 // +#define GPIO_RV_PeriphID7 0x00000000 // +#define GPIO_RV_PeriphID0 0x00000061 // +#define GPIO_RV_PeriphID1 0x00000010 // +#define GPIO_RV_PeriphID2 0x00000004 // +#define GPIO_RV_PeriphID3 0x00000000 // +#define GPIO_RV_PCellID0 0x0000000D // +#define GPIO_RV_PCellID1 0x000000F0 // +#define GPIO_RV_PCellID2 0x00000005 // +#define GPIO_RV_PCellID3 0x000000B1 // + +#endif // __HW_GPIO_H__ diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/hw_i2c.h b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/hw_i2c.h new file mode 100644 index 000000000..2a5f4fd42 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/hw_i2c.h @@ -0,0 +1,189 @@ +//***************************************************************************** +// +// hw_i2c.h - Macros used when accessing the I2C master and slave hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_I2C_H__ +#define __HW_I2C_H__ + +//***************************************************************************** +// +// The following define the offsets of the I2C master registers. +// +//***************************************************************************** +#define I2C_MASTER_O_SA 0x00000000 // Slave address register +#define I2C_MASTER_O_CS 0x00000004 // Control and Status register +#define I2C_MASTER_O_DR 0x00000008 // Data register +#define I2C_MASTER_O_TPR 0x0000000C // Timer period register +#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register +#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register +#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg +#define I2C_MASTER_O_MICR 0x0000001c // Interrupt clear register +#define I2C_MASTER_O_CR 0x00000020 // Configuration register + +//***************************************************************************** +// +// The following define the offsets of the I2C slave registers. +// +//***************************************************************************** +#define I2C_SLAVE_O_OAR 0x00000000 // Own address register +#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register +#define I2C_SLAVE_O_DR 0x00000008 // Data register +#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register +#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register +#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg +#define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register + +//***************************************************************************** +// +// The followng define the bit fields in the I2C master slave address register. +// +//***************************************************************************** +#define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address +#define I2C_MASTER_SA_RS 0x00000001 // Receive/send +#define I2C_MASTER_SA_SA_SHIFT 1 + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Control and Status +// register. +// +//***************************************************************************** +#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde +#define I2C_MASTER_CS_STOP 0x00000004 // Stop +#define I2C_MASTER_CS_START 0x00000002 // Start +#define I2C_MASTER_CS_RUN 0x00000001 // Run +#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy +#define I2C_MASTER_CS_IDLE 0x00000020 // Idle +#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration +#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged +#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged +#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred +#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data +#define I2C_MASTER_CS_ERR_MASK 0x0000001C + +//***************************************************************************** +// +// The following define values used in determining the contents of the I2C +// Master Timer Period register. +// +//***************************************************************************** +#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period +#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period +#define I2C_SCL_STANDARD 100000 // SCL standard frequency +#define I2C_SCL_FAST 400000 // SCL fast frequency + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Interrupt Mask +// register. +// +//***************************************************************************** +#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Raw Interrupt Status +// register. +// +//***************************************************************************** +#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Masked Interrupt +// Status register. +// +//***************************************************************************** +#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Interrupt Clear +// register. +// +//***************************************************************************** +#define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Configuration +// register. +// +//***************************************************************************** +#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable +#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable +#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Own Address register. +// +//***************************************************************************** +#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Control/Status +// register. +// +//***************************************************************************** +#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device +#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received +#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Interrupt Mask +// register. +// +//***************************************************************************** +#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Raw Interrupt Status +// register. +// +//***************************************************************************** +#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Masked Interrupt +// Status register. +// +//***************************************************************************** +#define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Interrupt Clear +// register. +// +//***************************************************************************** +#define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear + +#endif // __HW_I2C_H__ diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/hw_ints.h b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/hw_ints.h new file mode 100644 index 000000000..65ce1416d --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/hw_ints.h @@ -0,0 +1,96 @@ +//***************************************************************************** +// +// hw_ints.h - Macros that define the interrupt assignment on Stellaris. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_INTS_H__ +#define __HW_INTS_H__ + +//***************************************************************************** +// +// The following define the fault assignments. +// +//***************************************************************************** +#define FAULT_NMI 2 // NMI fault +#define FAULT_HARD 3 // Hard fault +#define FAULT_MPU 4 // MPU fault +#define FAULT_BUS 5 // Bus fault +#define FAULT_USAGE 6 // Usage fault +#define FAULT_SVCALL 11 // SVCall +#define FAULT_DEBUG 12 // Debug monitor +#define FAULT_PENDSV 14 // PendSV +#define FAULT_SYSTICK 15 // System Tick + +//***************************************************************************** +// +// The following define the interrupt assignments. +// +//***************************************************************************** +#define INT_GPIOA 16 // GPIO Port A +#define INT_GPIOB 17 // GPIO Port B +#define INT_GPIOC 18 // GPIO Port C +#define INT_GPIOD 19 // GPIO Port D +#define INT_GPIOE 20 // GPIO Port E +#define INT_UART0 21 // UART0 Rx and Tx +#define INT_UART1 22 // UART1 Rx and Tx +#define INT_SSI 23 // SSI Rx and Tx +#define INT_I2C 24 // I2C Master and Slave +#define INT_PWM_FAULT 25 // PWM Fault +#define INT_PWM0 26 // PWM Generator 0 +#define INT_PWM1 27 // PWM Generator 1 +#define INT_PWM2 28 // PWM Generator 2 +#define INT_ADC0 30 // ADC Sequence 0 +#define INT_ADC1 31 // ADC Sequence 1 +#define INT_ADC2 32 // ADC Sequence 2 +#define INT_ADC3 33 // ADC Sequence 3 +#define INT_WATCHDOG 34 // Watchdog timer +#define INT_TIMER0A 35 // Timer 0 subtimer A +#define INT_TIMER0B 36 // Timer 0 subtimer B +#define INT_TIMER1A 37 // Timer 1 subtimer A +#define INT_TIMER1B 38 // Timer 1 subtimer B +#define INT_TIMER2A 39 // Timer 2 subtimer A +#define INT_TIMER2B 40 // Timer 2 subtimer B +#define INT_COMP0 41 // Analog Comparator 0 +#define INT_COMP1 42 // Analog Comparator 1 +#define INT_COMP2 43 // Analog Comparator 2 +#define INT_SYSCTL 44 // System Control (PLL, OSC, BO) +#define INT_FLASH 45 // FLASH Control + +//***************************************************************************** +// +// The total number of interrupts. +// +//***************************************************************************** +#define NUM_INTERRUPTS 46 + +//***************************************************************************** +// +// The total number of priority levels. +// +//***************************************************************************** +#define NUM_PRIORITY 8 +#define NUM_PRIORITY_BITS 3 + +#endif // __HW_INTS_H__ diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/hw_memmap.h b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/hw_memmap.h new file mode 100644 index 000000000..9f701fc97 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/hw_memmap.h @@ -0,0 +1,63 @@ +//***************************************************************************** +// +// hw_memmap.h - Macros defining the memory map of Stellaris. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_MEMMAP_H__ +#define __HW_MEMMAP_H__ + +//***************************************************************************** +// +// The following define the base address of the memories and peripherals. +// +//***************************************************************************** +#define FLASH_BASE 0x00000000 // FLASH memory +#define SRAM_BASE 0x20000000 // SRAM memory +#define WATCHDOG_BASE 0x40000000 // Watchdog +#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A +#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B +#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C +#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D +#define SSI_BASE 0x40008000 // SSI +#define UART0_BASE 0x4000C000 // UART0 +#define UART1_BASE 0x4000D000 // UART1 +#define I2C_MASTER_BASE 0x40020000 // I2C Master +#define I2C_SLAVE_BASE 0x40020800 // I2C Slave +#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E +#define PWM_BASE 0x40028000 // PWM +#define TIMER0_BASE 0x40030000 // Timer0 +#define TIMER1_BASE 0x40031000 // Timer1 +#define TIMER2_BASE 0x40032000 // Timer2 +#define ADC_BASE 0x40038000 // ADC +#define COMP_BASE 0x4003C000 // Analog comparators +#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller +#define SYSCTL_BASE 0x400FE000 // System Control +#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell +#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace +#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint +#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl +#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit + +#endif // __HW_MEMMAP_H__ diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/hw_nvic.h b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/hw_nvic.h new file mode 100644 index 000000000..9e3154c88 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/hw_nvic.h @@ -0,0 +1,830 @@ +//***************************************************************************** +// +// hw_nvic.h - Macros used when accessing the NVIC hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_NVIC_H__ +#define __HW_NVIC_H__ + +//***************************************************************************** +// +// The following define the addresses of the NVIC registers. +// +//***************************************************************************** +#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg. +#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg. +#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register +#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register +#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg. +#define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register +#define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg. +#define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register +#define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg. +#define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register +#define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register +#define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register +#define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register +#define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register +#define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register +#define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register +#define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register +#define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register +#define NVIC_CPUID 0xE000ED00 // CPUID Base Register +#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register +#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register +#define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg. +#define NVIC_SYS_CTRL 0xE000ED10 // System Control Register +#define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register +#define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority +#define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority +#define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority +#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State +#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg. +#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register +#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register +#define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register +#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register +#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register +#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register +#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register +#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register +#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg. +#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg. +#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select +#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data +#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control +#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg. + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_INT_TYPE register. +// +//***************************************************************************** +#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) +#define NVIC_INT_TYPE_LINES_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_CTRL register. +// +//***************************************************************************** +#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag +#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source +#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable +#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_RELOAD register. +// +//***************************************************************************** +#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value +#define NVIC_ST_RELOAD_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_CURRENT register. +// +//***************************************************************************** +#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value +#define NVIC_ST_CURRENT_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_CAL register. +// +//***************************************************************************** +#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock +#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew +#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value +#define NVIC_ST_CAL_ONEMS_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_EN0 register. +// +//***************************************************************************** +#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable +#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable +#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable +#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable +#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable +#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable +#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable +#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable +#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable +#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable +#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable +#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable +#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable +#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable +#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable +#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable +#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable +#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable +#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable +#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable +#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable +#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable +#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable +#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable +#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable +#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable +#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable +#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable +#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable +#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable +#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable +#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DIS0 register. +// +//***************************************************************************** +#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable +#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable +#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable +#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable +#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable +#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable +#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable +#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable +#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable +#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable +#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable +#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable +#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable +#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable +#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable +#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable +#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable +#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable +#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable +#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable +#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable +#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable +#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable +#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable +#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable +#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable +#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable +#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable +#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable +#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable +#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable +#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PEND0 register. +// +//***************************************************************************** +#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend +#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend +#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend +#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend +#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend +#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend +#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend +#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend +#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend +#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend +#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend +#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend +#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend +#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend +#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend +#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend +#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend +#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend +#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend +#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend +#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend +#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend +#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend +#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend +#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend +#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend +#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend +#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend +#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend +#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend +#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend +#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_UNPEND0 register. +// +//***************************************************************************** +#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend +#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend +#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend +#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend +#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend +#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend +#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend +#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend +#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend +#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend +#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend +#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend +#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend +#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend +#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend +#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend +#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend +#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend +#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend +#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend +#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend +#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend +#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend +#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend +#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend +#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend +#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend +#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend +#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend +#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend +#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend +#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ACTIVE0 register. +// +//***************************************************************************** +#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active +#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active +#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active +#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active +#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active +#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active +#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active +#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active +#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active +#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active +#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active +#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active +#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active +#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active +#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active +#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active +#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active +#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active +#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active +#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active +#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active +#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active +#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active +#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active +#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active +#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active +#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active +#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active +#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active +#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active +#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active +#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI0 register. +// +//***************************************************************************** +#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask +#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask +#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask +#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask +#define NVIC_PRI0_INT3_S 24 +#define NVIC_PRI0_INT2_S 16 +#define NVIC_PRI0_INT1_S 8 +#define NVIC_PRI0_INT0_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI1 register. +// +//***************************************************************************** +#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask +#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask +#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask +#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask +#define NVIC_PRI1_INT7_S 24 +#define NVIC_PRI1_INT6_S 16 +#define NVIC_PRI1_INT5_S 8 +#define NVIC_PRI1_INT4_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI2 register. +// +//***************************************************************************** +#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask +#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask +#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask +#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask +#define NVIC_PRI2_INT11_S 24 +#define NVIC_PRI2_INT10_S 16 +#define NVIC_PRI2_INT9_S 8 +#define NVIC_PRI2_INT8_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI3 register. +// +//***************************************************************************** +#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask +#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask +#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask +#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask +#define NVIC_PRI3_INT15_S 24 +#define NVIC_PRI3_INT14_S 16 +#define NVIC_PRI3_INT13_S 8 +#define NVIC_PRI3_INT12_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI4 register. +// +//***************************************************************************** +#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask +#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask +#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask +#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask +#define NVIC_PRI4_INT19_S 24 +#define NVIC_PRI4_INT18_S 16 +#define NVIC_PRI4_INT17_S 8 +#define NVIC_PRI4_INT16_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI5 register. +// +//***************************************************************************** +#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask +#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask +#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask +#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask +#define NVIC_PRI5_INT23_S 24 +#define NVIC_PRI5_INT22_S 16 +#define NVIC_PRI5_INT21_S 8 +#define NVIC_PRI5_INT20_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI6 register. +// +//***************************************************************************** +#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask +#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask +#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask +#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask +#define NVIC_PRI6_INT27_S 24 +#define NVIC_PRI6_INT26_S 16 +#define NVIC_PRI6_INT25_S 8 +#define NVIC_PRI6_INT24_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI7 register. +// +//***************************************************************************** +#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask +#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask +#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask +#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask +#define NVIC_PRI7_INT31_S 24 +#define NVIC_PRI7_INT30_S 16 +#define NVIC_PRI7_INT29_S 8 +#define NVIC_PRI7_INT28_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_CPUID register. +// +//***************************************************************************** +#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer +#define NVIC_CPUID_VAR_M 0x00F00000 // Variant +#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number +#define NVIC_CPUID_REV_M 0x0000000F // Revision + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_INT_CTRL register. +// +//***************************************************************************** +#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI +#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV +#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV +#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling +#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending +#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception +#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base +#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception +#define NVIC_INT_CTRL_VEC_PEN_S 12 +#define NVIC_INT_CTRL_VEC_ACT_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_VTABLE register. +// +//***************************************************************************** +#define NVIC_VTABLE_BASE 0x20000000 // Vector table base +#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset +#define NVIC_VTABLE_OFFSET_S 8 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_APINT register. +// +//***************************************************************************** +#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask +#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key +#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess +#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group +#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split +#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split +#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split +#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split +#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split +#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split +#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split +#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split +#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request +#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info +#define NVIC_APINT_VECT_RESET 0x00000001 // System reset + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend +#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable +#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_CFG_CTRL register. +// +//***************************************************************************** +#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault +#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0 +#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access +#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger +#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger +#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_PRI1 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler +#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler +#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler +#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler +#define NVIC_SYS_PRI1_USAGE_S 16 +#define NVIC_SYS_PRI1_BUS_S 8 +#define NVIC_SYS_PRI1_MEM_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_PRI2 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler +#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers +#define NVIC_SYS_PRI2_SVC_S 24 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_PRI3 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler +#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler +#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler +#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler +#define NVIC_SYS_PRI3_TICK_S 24 +#define NVIC_SYS_PRI3_PENDSV_S 16 +#define NVIC_SYS_PRI3_DEBUG_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_HND_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable +#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable +#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable +#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended +#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended +#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active +#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active +#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active +#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active +#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active +#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active +#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_FAULT_STAT register. +// +//***************************************************************************** +#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault +#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault +#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault +#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault +#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault +#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault +#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid +#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault +#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault +#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error +#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error +#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault +#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid +#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation +#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation +#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation +#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_HFAULT_STAT register. +// +//***************************************************************************** +#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event +#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler +#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DEBUG_STAT register. +// +//***************************************************************************** +#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted +#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch +#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match +#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction +#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MM_ADDR register. +// +//***************************************************************************** +#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address +#define NVIC_MM_ADDR_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_FAULT_ADDR register. +// +//***************************************************************************** +#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address +#define NVIC_FAULT_ADDR_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_EXC_STACK register. +// +//***************************************************************************** +#define NVIC_EXC_STACK_DEEP 0x00000001 // Exception stack + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_EXC_NUM register. +// +//***************************************************************************** +#define NVIC_EXC_NUM_M 0x000003FF // Exception number +#define NVIC_EXC_NUM_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_COPRO register. +// +//***************************************************************************** +#define NVIC_COPRO_15_M 0xC0000000 // Coprocessor 15 access mask +#define NVIC_COPRO_15_DENIED 0x00000000 // Coprocessor 15 access denied +#define NVIC_COPRO_15_PRIV 0x40000000 // Coprocessor 15 privileged addess +#define NVIC_COPRO_15_FULL 0xC0000000 // Coprocessor 15 full access +#define NVIC_COPRO_14_M 0x30000000 // Coprocessor 14 access mask +#define NVIC_COPRO_14_DENIED 0x00000000 // Coprocessor 14 access denied +#define NVIC_COPRO_14_PRIV 0x10000000 // Coprocessor 14 privileged addess +#define NVIC_COPRO_14_FULL 0x30000000 // Coprocessor 14 full access +#define NVIC_COPRO_13_M 0x0C000000 // Coprocessor 13 access mask +#define NVIC_COPRO_13_DENIED 0x00000000 // Coprocessor 13 access denied +#define NVIC_COPRO_13_PRIV 0x04000000 // Coprocessor 13 privileged addess +#define NVIC_COPRO_13_FULL 0x0C000000 // Coprocessor 13 full access +#define NVIC_COPRO_12_M 0x03000000 // Coprocessor 12 access mask +#define NVIC_COPRO_12_DENIED 0x00000000 // Coprocessor 12 access denied +#define NVIC_COPRO_12_PRIV 0x01000000 // Coprocessor 12 privileged addess +#define NVIC_COPRO_12_FULL 0x03000000 // Coprocessor 12 full access +#define NVIC_COPRO_11_M 0x00C00000 // Coprocessor 11 access mask +#define NVIC_COPRO_11_DENIED 0x00000000 // Coprocessor 11 access denied +#define NVIC_COPRO_11_PRIV 0x00400000 // Coprocessor 11 privileged addess +#define NVIC_COPRO_11_FULL 0x00C00000 // Coprocessor 11 full access +#define NVIC_COPRO_10_M 0x00300000 // Coprocessor 10 access mask +#define NVIC_COPRO_10_DENIED 0x00000000 // Coprocessor 10 access denied +#define NVIC_COPRO_10_PRIV 0x00100000 // Coprocessor 10 privileged addess +#define NVIC_COPRO_10_FULL 0x00300000 // Coprocessor 10 full access +#define NVIC_COPRO_9_M 0x000C0000 // Coprocessor 9 access mask +#define NVIC_COPRO_9_DENIED 0x00000000 // Coprocessor 9 access denied +#define NVIC_COPRO_9_PRIV 0x00040000 // Coprocessor 9 privileged addess +#define NVIC_COPRO_9_FULL 0x000C0000 // Coprocessor 9 full access +#define NVIC_COPRO_8_M 0x00030000 // Coprocessor 8 access mask +#define NVIC_COPRO_8_DENIED 0x00000000 // Coprocessor 8 access denied +#define NVIC_COPRO_8_PRIV 0x00010000 // Coprocessor 8 privileged addess +#define NVIC_COPRO_8_FULL 0x00030000 // Coprocessor 8 full access +#define NVIC_COPRO_7_M 0x0000C000 // Coprocessor 7 access mask +#define NVIC_COPRO_7_DENIED 0x00000000 // Coprocessor 7 access denied +#define NVIC_COPRO_7_PRIV 0x00004000 // Coprocessor 7 privileged addess +#define NVIC_COPRO_7_FULL 0x0000C000 // Coprocessor 7 full access +#define NVIC_COPRO_6_M 0x00003000 // Coprocessor 6 access mask +#define NVIC_COPRO_6_DENIED 0x00000000 // Coprocessor 6 access denied +#define NVIC_COPRO_6_PRIV 0x00001000 // Coprocessor 6 privileged addess +#define NVIC_COPRO_6_FULL 0x00003000 // Coprocessor 6 full access +#define NVIC_COPRO_5_M 0x00000C00 // Coprocessor 5 access mask +#define NVIC_COPRO_5_DENIED 0x00000000 // Coprocessor 5 access denied +#define NVIC_COPRO_5_PRIV 0x00000400 // Coprocessor 5 privileged addess +#define NVIC_COPRO_5_FULL 0x00000C00 // Coprocessor 5 full access +#define NVIC_COPRO_4_M 0x00000300 // Coprocessor 4 access mask +#define NVIC_COPRO_4_DENIED 0x00000000 // Coprocessor 4 access denied +#define NVIC_COPRO_4_PRIV 0x00000100 // Coprocessor 4 privileged addess +#define NVIC_COPRO_4_FULL 0x00000300 // Coprocessor 4 full access +#define NVIC_COPRO_3_M 0x000000C0 // Coprocessor 3 access mask +#define NVIC_COPRO_3_DENIED 0x00000000 // Coprocessor 3 access denied +#define NVIC_COPRO_3_PRIV 0x00000040 // Coprocessor 3 privileged addess +#define NVIC_COPRO_3_FULL 0x000000C0 // Coprocessor 3 full access +#define NVIC_COPRO_2_M 0x00000030 // Coprocessor 2 access mask +#define NVIC_COPRO_2_DENIED 0x00000000 // Coprocessor 2 access denied +#define NVIC_COPRO_2_PRIV 0x00000010 // Coprocessor 2 privileged addess +#define NVIC_COPRO_2_FULL 0x00000030 // Coprocessor 2 full access +#define NVIC_COPRO_1_M 0x0000000C // Coprocessor 1 access mask +#define NVIC_COPRO_1_DENIED 0x00000000 // Coprocessor 1 access denied +#define NVIC_COPRO_1_PRIV 0x00000004 // Coprocessor 1 privileged addess +#define NVIC_COPRO_1_FULL 0x0000000C // Coprocessor 1 full access +#define NVIC_COPRO_0_M 0x00000003 // Coprocessor 0 access mask +#define NVIC_COPRO_0_DENIED 0x00000000 // Coprocessor 0 access denied +#define NVIC_COPRO_0_PRIV 0x00000001 // Coprocessor 0 privileged addess +#define NVIC_COPRO_0_FULL 0x00000003 // Coprocessor 0 full access + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_TYPE register. +// +//***************************************************************************** +#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions +#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions +#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU +#define NVIC_MPU_TYPE_IREGION_S 16 +#define NVIC_MPU_TYPE_DREGION_S 8 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_CTRL register. +// +//***************************************************************************** +#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults +#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_NUMBER register. +// +//***************************************************************************** +#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access +#define NVIC_MPU_NUMBER_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_BASE register. +// +//***************************************************************************** +#define NVIC_MPU_BASE_ADDR_M 0xFFFFFF00 // Base address +#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid +#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number +#define NVIC_MPU_BASE_ADDR_S 8 +#define NVIC_MPU_BASE_REGION_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_ATTR register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR_ATTRS 0xFFFF0000 // Attributes +#define NVIC_MPU_ATTR_SRD 0x0000FF00 // Sub-region disable +#define NVIC_MPU_ATTR_SZENABLE 0x000000FF // Region size + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_CTRL register. +// +//***************************************************************************** +#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask +#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key +#define NVIC_DBG_CTRL_MON_PEND 0x00008000 // Pend the monitor +#define NVIC_DBG_CTRL_MON_REQ 0x00004000 // Monitor request +#define NVIC_DBG_CTRL_MON_EN 0x00002000 // Debug monitor enable +#define NVIC_DBG_CTRL_MONSTEP 0x00001000 // Monitor step the core +#define NVIC_DBG_CTRL_S_SLEEP 0x00000400 // Core is sleeping +#define NVIC_DBG_CTRL_S_HALT 0x00000200 // Core status on halt +#define NVIC_DBG_CTRL_S_REGRDY 0x00000100 // Register read/write available +#define NVIC_DBG_CTRL_S_LOCKUP 0x00000080 // Core is locked up +#define NVIC_DBG_CTRL_C_RESET 0x00000010 // Reset the core +#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping +#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core +#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core +#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_XFER register. +// +//***************************************************************************** +#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read +#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register +#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 +#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 +#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 +#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 +#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 +#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 +#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 +#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 +#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 +#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 +#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 +#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 +#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 +#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 +#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 +#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 +#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register +#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP +#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP +#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP +#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_DATA register. +// +//***************************************************************************** +#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache +#define NVIC_DBG_DATA_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_INT register. +// +//***************************************************************************** +#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault +#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors +#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error +#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state +#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check +#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error +#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault +#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status +#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset +#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending +#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SW_TRIG register. +// +//***************************************************************************** +#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger +#define NVIC_SW_TRIG_INTID_S 0 + +#endif // __HW_NVIC_H__ diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/hw_pwm.h b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/hw_pwm.h new file mode 100644 index 000000000..b14172acf --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/hw_pwm.h @@ -0,0 +1,260 @@ +//***************************************************************************** +// +// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_PWM_H__ +#define __HW_PWM_H__ + +//***************************************************************************** +// +// PWM Module Register Offsets. +// +//***************************************************************************** +#define PWM_O_CTL 0x00000000 // PWM Master Control register +#define PWM_O_SYNC 0x00000004 // PWM Time Base Sync register +#define PWM_O_ENABLE 0x00000008 // PWM Output Enable register +#define PWM_O_INVERT 0x0000000C // PWM Output Inversion register +#define PWM_O_FAULT 0x00000010 // PWM Output Fault register +#define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable register +#define PWM_O_RIS 0x00000018 // PWM Interrupt Raw Status reg. +#define PWM_O_ISC 0x0000001C // PWM Interrupt Status register +#define PWM_O_STATUS 0x00000020 // PWM Status register + +//***************************************************************************** +// +// The following define the bit fields in the PWM Master Control register. +// +//***************************************************************************** +#define PWM_CTL_GLOBAL_SYNC2 0x00000004 // Global sync generator 2 +#define PWM_CTL_GLOBAL_SYNC1 0x00000002 // Global sync generator 1 +#define PWM_CTL_GLOBAL_SYNC0 0x00000001 // Global sync generator 0 + +//***************************************************************************** +// +// The following define the bit fields in the PWM Time Base Sync register. +// +//***************************************************************************** +#define PWM_SYNC_SYNC2 0x00000004 // Reset generator 2 counter +#define PWM_SYNC_SYNC1 0x00000002 // Reset generator 1 counter +#define PWM_SYNC_SYNC0 0x00000001 // Reset generator 0 counter + +//***************************************************************************** +// +// The following define the bit fields in the PWM Output Enable register. +// +//***************************************************************************** +#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 pin enable +#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 pin enable +#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 pin enable +#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 pin enable +#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 pin enable +#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 pin enable + +//***************************************************************************** +// +// The following define the bit fields in the PWM Inversion register. +// +//***************************************************************************** +#define PWM_INVERT_PWM5INV 0x00000020 // PWM5 pin invert +#define PWM_INVERT_PWM4INV 0x00000010 // PWM4 pin invert +#define PWM_INVERT_PWM3INV 0x00000008 // PWM3 pin invert +#define PWM_INVERT_PWM2INV 0x00000004 // PWM2 pin invert +#define PWM_INVERT_PWM1INV 0x00000002 // PWM1 pin invert +#define PWM_INVERT_PWM0INV 0x00000001 // PWM0 pin invert + +//***************************************************************************** +// +// The following define the bit fields in the PWM Fault register. +// +//***************************************************************************** +#define PWM_FAULT_FAULT5 0x00000020 // PWM5 pin fault +#define PWM_FAULT_FAULT4 0x00000010 // PWM5 pin fault +#define PWM_FAULT_FAULT3 0x00000008 // PWM5 pin fault +#define PWM_FAULT_FAULT2 0x00000004 // PWM5 pin fault +#define PWM_FAULT_FAULT1 0x00000002 // PWM5 pin fault +#define PWM_FAULT_FAULT0 0x00000001 // PWM5 pin fault + +//***************************************************************************** +// +// PWM Interrupt Register bit definitions. +// +//***************************************************************************** +#define PWM_INT_INTFAULT 0x00010000 // Fault interrupt pending + +//***************************************************************************** +// +// The following define the bit fields in the PWM Status register. +// +//***************************************************************************** +#define PWM_STATUS_FAULT 0x00000001 // Fault status + +//***************************************************************************** +// +// PWM Generator standard offsets. +// +//***************************************************************************** +#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base +#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base +#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base + +#define PWM_O_X_CTL 0x00000000 // Gen Control Reg +#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg +#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg +#define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg +#define PWM_O_X_LOAD 0x00000010 // Gen Load Reg +#define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg +#define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg +#define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg +#define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg +#define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg +#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg +#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg +#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg + +//***************************************************************************** +// +// PWM_X Control Register bit definitions. +// +//***************************************************************************** +#define PWM_X_CTL_ENABLE 0x00000001 // Master enable for gen block +#define PWM_X_CTL_MODE 0x00000002 // Counter mode, down or up/down +#define PWM_X_CTL_DEBUG 0x00000004 // Debug mode +#define PWM_X_CTL_LOADUPD 0x00000008 // Update mode for the load reg +#define PWM_X_CTL_CMPAUPD 0x00000010 // Update mode for comp A reg +#define PWM_X_CTL_CMPBUPD 0x00000020 // Update mode for comp B reg + +//***************************************************************************** +// +// PWM_X Interrupt/Trigger Enable Register bit definitions. +// +//***************************************************************************** +#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Int if COUNT = 0 +#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Int if COUNT = LOAD +#define PWM_X_INTEN_INTCMPAU 0x00000004 // Int if COUNT = CMPA U +#define PWM_X_INTEN_INTCMPAD 0x00000008 // Int if COUNT = CMPA D +#define PWM_X_INTEN_INTCMPBU 0x00000010 // Int if COUNT = CMPA U +#define PWM_X_INTEN_INTCMPBD 0x00000020 // Int if COUNT = CMPA D +#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trig if COUNT = 0 +#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trig if COUNT = LOAD +#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trig if COUNT = CMPA U +#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trig if COUNT = CMPA D +#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trig if COUNT = CMPA U +#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trig if COUNT = CMPA D + +//***************************************************************************** +// +// PWM_X Raw Interrupt Status Register bit definitions. +// +//***************************************************************************** +#define PWM_X_RIS_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 int +#define PWM_X_RIS_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD int +#define PWM_X_RIS_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U int +#define PWM_X_RIS_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D int +#define PWM_X_RIS_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U int +#define PWM_X_RIS_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D int + +//***************************************************************************** +// +// PWM_X Interrupt Status Register bit definitions. +// +//***************************************************************************** +#define PWM_X_INT_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 received +#define PWM_X_INT_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD rcvd +#define PWM_X_INT_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U rcvd +#define PWM_X_INT_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D rcvd +#define PWM_X_INT_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U rcvd +#define PWM_X_INT_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D rcvd + +//***************************************************************************** +// +// PWM_X Generator A/B Control Register bit definitions. +// +//***************************************************************************** +#define PWM_X_GEN_Y_ACTZERO 0x00000003 // Act PWM_X_COUNT = 0 +#define PWM_X_GEN_Y_ACTLOAD 0x0000000C // Act PWM_X_COUNT = PWM_X_LOAD +#define PWM_X_GEN_Y_ACTCMPAU 0x00000030 // Act PWM_X_COUNT = PWM_X_CMPA U +#define PWM_X_GEN_Y_ACTCMPAD 0x000000C0 // Act PWM_X_COUNT = PWM_X_CMPA D +#define PWM_X_GEN_Y_ACTCMPBU 0x00000300 // Act PWM_X_COUNT = PWM_X_CMPB U +#define PWM_X_GEN_Y_ACTCMPBD 0x00000C00 // Act PWM_X_COUNT = PWM_X_CMPB D + +//***************************************************************************** +// +// PWM_X Generator A/B Control Register action definitions. +// +//***************************************************************************** +#define PWM_GEN_ACT_NONE 0x0 // Do nothing +#define PWM_GEN_ACT_INV 0x1 // Invert the output signal +#define PWM_GEN_ACT_ZERO 0x2 // Set the output signal to zero +#define PWM_GEN_ACT_ONE 0x3 // Set the output signal to one +#define PWM_GEN_ACT_ZERO_SHIFT 0 // Shift amount for the zero action +#define PWM_GEN_ACT_LOAD_SHIFT 2 // Shift amount for the load action +#define PWM_GEN_ACT_A_UP_SHIFT 4 // Shift amount for the A up action +#define PWM_GEN_ACT_A_DN_SHIFT 6 // Shift amount for the A dn action +#define PWM_GEN_ACT_B_UP_SHIFT 8 // Shift amount for the B up action +#define PWM_GEN_ACT_B_DN_SHIFT 10 // Shift amount for the B dn action + +//***************************************************************************** +// +// PWM_X Dead Band Control Register bit definitions. +// +//***************************************************************************** +#define PWM_DBCTL_ENABLE 0x00000001 // Enable dead band insertion + +//***************************************************************************** +// +// PWM Register reset values. +// +//***************************************************************************** +#define PWM_RV_CTL 0x00000000 // Master control of the PWM module +#define PWM_RV_SYNC 0x00000000 // Counter synch for PWM generators +#define PWM_RV_ENABLE 0x00000000 // Master enable for the PWM + // output pins +#define PWM_RV_INVERT 0x00000000 // Inversion control for + // PWM output pins +#define PWM_RV_FAULT 0x00000000 // Fault handling for the PWM + // output pins +#define PWM_RV_INTEN 0x00000000 // Interrupt enable +#define PWM_RV_RIS 0x00000000 // Raw interrupt status +#define PWM_RV_ISC 0x00000000 // Interrupt status and clearing +#define PWM_RV_STATUS 0x00000000 // Status +#define PWM_RV_X_CTL 0x00000000 // Master control of the PWM + // generator block +#define PWM_RV_X_INTEN 0x00000000 // Interrupt and trigger enable +#define PWM_RV_X_RIS 0x00000000 // Raw interrupt status +#define PWM_RV_X_ISC 0x00000000 // Interrupt status and clearing +#define PWM_RV_X_LOAD 0x00000000 // The load value for the counter +#define PWM_RV_X_COUNT 0x00000000 // The current counter value +#define PWM_RV_X_CMPA 0x00000000 // The comparator A value +#define PWM_RV_X_CMPB 0x00000000 // The comparator B value +#define PWM_RV_X_GENA 0x00000000 // Controls PWM generator A +#define PWM_RV_X_GENB 0x00000000 // Controls PWM generator B +#define PWM_RV_X_DBCTL 0x00000000 // Control the dead band generator +#define PWM_RV_X_DBRISE 0x00000000 // The dead band rising edge delay + // count +#define PWM_RV_X_DBFALL 0x00000000 // The dead band falling edge delay + // count + +#endif // __HW_PWM_H__ diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/hw_ssi.h b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/hw_ssi.h new file mode 100644 index 000000000..c8a18fc29 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/hw_ssi.h @@ -0,0 +1,120 @@ +//***************************************************************************** +// +// hw_ssi.h - Macros used when accessing the SSI hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_SSI_H__ +#define __HW_SSI_H__ + +//***************************************************************************** +// +// The following define the offsets of the SSI registers. +// +//***************************************************************************** +#define SSI_O_CR0 0x00000000 // Control register 0 +#define SSI_O_CR1 0x00000004 // Control register 1 +#define SSI_O_DR 0x00000008 // Data register +#define SSI_O_SR 0x0000000C // Status register +#define SSI_O_CPSR 0x00000010 // Clock prescale register +#define SSI_O_IM 0x00000014 // Int mask set and clear register +#define SSI_O_RIS 0x00000018 // Raw interrupt register +#define SSI_O_MIS 0x0000001C // Masked interrupt register +#define SSI_O_ICR 0x00000020 // Interrupt clear register + +//***************************************************************************** +// +// The following define the bit fields in the SSI Control register 0. +// +//***************************************************************************** +#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate +#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase +#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity +#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask +#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format +#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format +#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format +#define SSI_CR0_DSS 0x0000000F // Data size select +#define SSI_CR0_DSS_4 0x00000003 // 4 bit data +#define SSI_CR0_DSS_5 0x00000004 // 5 bit data +#define SSI_CR0_DSS_6 0x00000005 // 6 bit data +#define SSI_CR0_DSS_7 0x00000006 // 7 bit data +#define SSI_CR0_DSS_8 0x00000007 // 8 bit data +#define SSI_CR0_DSS_9 0x00000008 // 9 bit data +#define SSI_CR0_DSS_10 0x00000009 // 10 bit data +#define SSI_CR0_DSS_11 0x0000000A // 11 bit data +#define SSI_CR0_DSS_12 0x0000000B // 12 bit data +#define SSI_CR0_DSS_13 0x0000000C // 13 bit data +#define SSI_CR0_DSS_14 0x0000000D // 14 bit data +#define SSI_CR0_DSS_15 0x0000000E // 15 bit data +#define SSI_CR0_DSS_16 0x0000000F // 16 bit data + +//***************************************************************************** +// +// The following define the bit fields in the SSI Control register 1. +// +//***************************************************************************** +#define SSI_CR1_SOD 0x00000008 // Slave mode output disable +#define SSI_CR1_MS 0x00000004 // Master or slave mode select +#define SSI_CR1_SSE 0x00000002 // Sync serial port enable +#define SSI_CR1_LBM 0x00000001 // Loopback mode + +//***************************************************************************** +// +// The following define the bit fields in the SSI Status register. +// +//***************************************************************************** +#define SSI_SR_BSY 0x00000010 // SSI busy +#define SSI_SR_RFF 0x00000008 // RX FIFO full +#define SSI_SR_RNE 0x00000004 // RX FIFO not empty +#define SSI_SR_TNF 0x00000002 // TX FIFO not full +#define SSI_SR_TFE 0x00000001 // TX FIFO empty + +//***************************************************************************** +// +// The following define the bit fields in the SSI clock prescale register. +// +//***************************************************************************** +#define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale + +//***************************************************************************** +// +// The following define information concerning the SSI Data register. +// +//***************************************************************************** +#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO +#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO + +//***************************************************************************** +// +// The following define the bit fields in the interrupt mask set and clear, +// raw interrupt, masked interrupt, and interrupt clear registers. +// +//***************************************************************************** +#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt +#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt +#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt +#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt + +#endif // __HW_SSI_H__ diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/hw_sysctl.h b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/hw_sysctl.h new file mode 100644 index 000000000..9a8fff4ee --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/hw_sysctl.h @@ -0,0 +1,380 @@ +//***************************************************************************** +// +// hw_sysctl.h - Macros used when accessing the system control hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_SYSCTL_H__ +#define __HW_SYSCTL_H__ + +//***************************************************************************** +// +// The following define the offsets of the system control registers. +// +//***************************************************************************** +#define SYSCTL_DID0 0x400fe000 // Device identification register 0 +#define SYSCTL_DID1 0x400fe004 // Device identification register 1 +#define SYSCTL_DC0 0x400fe008 // Device capabilities register 0 +#define SYSCTL_DC1 0x400fe010 // Device capabilities register 1 +#define SYSCTL_DC2 0x400fe014 // Device capabilities register 2 +#define SYSCTL_DC3 0x400fe018 // Device capabilities register 3 +#define SYSCTL_DC4 0x400fe01C // Device capabilities register 4 +#define SYSCTL_PBORCTL 0x400fe030 // POR/BOR reset control register +#define SYSCTL_LDOPCTL 0x400fe034 // LDO power control register +#define SYSCTL_SRCR0 0x400fe040 // Software reset control reg 0 +#define SYSCTL_SRCR1 0x400fe044 // Software reset control reg 1 +#define SYSCTL_SRCR2 0x400fe048 // Software reset control reg 2 +#define SYSCTL_RIS 0x400fe050 // Raw interrupt status register +#define SYSCTL_IMC 0x400fe054 // Interrupt mask/control register +#define SYSCTL_MISC 0x400fe058 // Interrupt status register +#define SYSCTL_RESC 0x400fe05c // Reset cause register +#define SYSCTL_RCC 0x400fe060 // Run-mode clock config register +#define SYSCTL_PLLCFG 0x400fe064 // PLL configuration register +#define SYSCTL_RCGC0 0x400fe100 // Run-mode clock gating register 0 +#define SYSCTL_RCGC1 0x400fe104 // Run-mode clock gating register 1 +#define SYSCTL_RCGC2 0x400fe108 // Run-mode clock gating register 2 +#define SYSCTL_SCGC0 0x400fe110 // Sleep-mode clock gating reg 0 +#define SYSCTL_SCGC1 0x400fe114 // Sleep-mode clock gating reg 1 +#define SYSCTL_SCGC2 0x400fe118 // Sleep-mode clock gating reg 2 +#define SYSCTL_DCGC0 0x400fe120 // Deep Sleep-mode clock gate reg 0 +#define SYSCTL_DCGC1 0x400fe124 // Deep Sleep-mode clock gate reg 1 +#define SYSCTL_DCGC2 0x400fe128 // Deep Sleep-mode clock gate reg 2 +#define SYSCTL_CLKVCLR 0x400fe150 // Clock verifcation clear register +#define SYSCTL_LDOARST 0x400fe160 // LDO reset control register + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DID0 register. +// +//***************************************************************************** +#define SYSCTL_DID0_VER_MASK 0x70000000 // DID0 version mask +#define SYSCTL_DID0_VER_0 0x00000000 // DID0 version 0 +#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask +#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A +#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B +#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask +#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0 +#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DID1 register. +// +//***************************************************************************** +#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask +#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask +#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family +#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask +#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101 +#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102 +#define SYSCTL_DID1_PRTNO_301 0x00110000 // LM3S301 +#define SYSCTL_DID1_PRTNO_310 0x00120000 // LM3S310 +#define SYSCTL_DID1_PRTNO_315 0x00130000 // LM3S315 +#define SYSCTL_DID1_PRTNO_316 0x00140000 // LM3S316 +#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask +#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C) +#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C) +#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask +#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC +#define SYSCTL_DID1_PKG_48QFP 0x00000008 // 48-pin QFP +#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant +#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask +#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified) +#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified) +#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified +#define SYSCTL_DID1_PRTNO_SHIFT 16 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC0 register. +// +//***************************************************************************** +#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask +#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2kB of SRAM +#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4kB of SRAM +#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask +#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8kB of flash +#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16kB of flash + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC1 register. +// +//***************************************************************************** +#define SYSCTL_DC1_PWM 0x00100000 // PWM module present +#define SYSCTL_DC1_ADC 0x00010000 // ADC module present +#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask +#define SYSCTL_DC1_ADCSPD_MASK 0x00000F00 // ADC speed mask +#define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250Ksps ADC +#define SYSCTL_DC1_ADCSPD_125K 0x00000000 // 125Ksps ADC +#define SYSCTL_DC1_MPU 0x00000080 // Cortex M3 MPU present +#define SYSCTL_DC1_TEMP 0x00000020 // Temperature sensor present +#define SYSCTL_DC1_PLL 0x00000010 // PLL present +#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present +#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present +#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present +#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC2 register. +// +//***************************************************************************** +#define SYSCTL_DC2_COMP2 0x04000000 // Analog comparator 2 present +#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present +#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present +#define SYSCTL_DC2_TIMER2 0x00040000 // Timer 2 present +#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present +#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present +#define SYSCTL_DC2_I2C 0x00001000 // I2C present +#define SYSCTL_DC2_SSI 0x00000010 // SSI present +#define SYSCTL_DC2_UART1 0x00000002 // UART 1 present +#define SYSCTL_DC2_UART0 0x00000001 // UART 0 present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC3 register. +// +//***************************************************************************** +#define SYSCTL_DC3_32KHZ 0x80000000 // 32kHz pin present +#define SYSCTL_DC3_CCP5 0x20000000 // CCP5 pin present +#define SYSCTL_DC3_CCP4 0x10000000 // CCP4 pin present +#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 pin present +#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 pin present +#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present +#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present +#define SYSCTL_DC3_ADC3 0x00080000 // ADC3 pin present +#define SYSCTL_DC3_ADC2 0x00040000 // ADC2 pin present +#define SYSCTL_DC3_ADC1 0x00020000 // ADC1 pin present +#define SYSCTL_DC3_ADC0 0x00010000 // ADC0 pin present +#define SYSCTL_DC3_C2O 0x00004000 // C2o pin present +#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ pin present +#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- pin present +#define SYSCTL_DC3_C1O 0x00000800 // C1o pin present +#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ pin present +#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present +#define SYSCTL_DC3_C0O 0x00000100 // C0o pin present +#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present +#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present +#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 pin present +#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 pin present +#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 pin present +#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 pin present +#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 pin present +#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 pin present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC4 register. +// +//***************************************************************************** +#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO port E present +#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO port D present +#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present +#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present +#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_PBORCTL register. +// +//***************************************************************************** +#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer +#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset +#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise +#define SYSCTL_PBORCTL_BOR_SH 2 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_LDOPCTL register. +// +//***************************************************************************** +#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask +#define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V +#define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V +#define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V +#define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V +#define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V +#define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V +#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V +#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V +#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V +#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V +#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_SRCR0, SYSCTL_RCGC0, +// SYSCTL_SCGC0, and SYSCTL_DCGC0 registers. +// +//***************************************************************************** +#define SYSCTL_SET0_PWM 0x00100000 // PWM module +#define SYSCTL_SET0_ADC 0x00010000 // ADC module +#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_SRCR1, SYSCTL_RCGC1, +// SYSCTL_SCGC1, and SYSCTL_DCGC1 registers. +// +//***************************************************************************** +#define SYSCTL_SET1_COMP2 0x04000000 // Analog comparator module 2 +#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1 +#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0 +#define SYSCTL_SET1_TIMER2 0x00040000 // Timer module 2 +#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1 +#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0 +#define SYSCTL_SET1_I2C 0x00001000 // I2C module +#define SYSCTL_SET1_SSI 0x00000010 // SSI module +#define SYSCTL_SET1_UART1 0x00000002 // UART module 1 +#define SYSCTL_SET1_UART0 0x00000001 // UART module 0 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_SRCR2, SYSCTL_RCGC2, +// SYSCTL_SCGC2, and SYSCTL_DCGC2 registers. +// +//***************************************************************************** +#define SYSCTL_SET2_GPIOE 0x00000010 // GPIO E module +#define SYSCTL_SET2_GPIOD 0x00000008 // GPIO D module +#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module +#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module +#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_RIS, SYSCTL_IMC, and +// SYSCTL_IMS registers. +// +//***************************************************************************** +#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt +#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt +#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int +#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int +#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt +#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt +#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_RESC register. +// +//***************************************************************************** +#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset +#define SYSCTL_RESC_SW 0x00000010 // Software reset +#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset +#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset +#define SYSCTL_RESC_POR 0x00000002 // Power on reset +#define SYSCTL_RESC_EXT 0x00000001 // External reset + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_RCC register. +// +//***************************************************************************** +#define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating +#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider +#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2 +#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3 +#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4 +#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5 +#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6 +#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7 +#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8 +#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9 +#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10 +#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11 +#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12 +#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13 +#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14 +#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15 +#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16 +#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider +#define SYSCTL_RCC_USE_PWMDIV 0x00100000 // Use PWM clock divider +#define SYSCTL_RCC_PWMDIV_MASK 0x000E0000 // PWM clock divider +#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2 +#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4 +#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8 +#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16 +#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32 +#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64 +#define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down +#define SYSCTL_RCC_OE 0x00001000 // PLL output enable +#define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass +#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable +#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc +#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal +#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864MHz crystal +#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4MHz crystal +#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal +#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal +#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal +#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal +#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal +#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal +#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal +#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal +#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal +#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select +#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator +#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // Use the internal oscillator +#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // Use the internal oscillator / 4 +#define SYSCTL_RCC_IOSCVER 0x00000008 // Int. osc. verification timer en +#define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en +#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal oscillator disable +#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable +#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field +#define SYSCTL_RCC_PWMDIV_SHIFT 17 // Shift to the PWMDIV field +#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field +#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_PLLCFG register. +// +//***************************************************************************** +#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider +#define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1 +#define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2 +#define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4 +#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier +#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider +#define SYSCTL_PLLCFG_F_SHIFT 5 +#define SYSCTL_PLLCFG_R_SHIFT 0 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_CLKVCLR register. +// +//***************************************************************************** +#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_LDOARST register. +// +//***************************************************************************** +#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device + +#endif // __HW_SYSCTL_H__ diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/hw_timer.h b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/hw_timer.h new file mode 100644 index 000000000..9954a9ff1 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/hw_timer.h @@ -0,0 +1,235 @@ +//***************************************************************************** +// +// hw_timer.h - Defines and macros used when accessing the timer. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_TIMER_H__ +#define __HW_TIMER_H__ + +//***************************************************************************** +// +// The following define the offsets of the timer registers. +// +//***************************************************************************** +#define TIMER_O_CFG 0x00000000 // Configuration register +#define TIMER_O_TAMR 0x00000004 // TimerA mode register +#define TIMER_O_TBMR 0x00000008 // TimerB mode register +#define TIMER_O_CTL 0x0000000C // Control register +#define TIMER_O_IMR 0x00000018 // Interrupt mask register +#define TIMER_O_RIS 0x0000001C // Interrupt status register +#define TIMER_O_MIS 0x00000020 // Masked interrupt status reg. +#define TIMER_O_ICR 0x00000024 // Interrupt clear register +#define TIMER_O_TAILR 0x00000028 // TimerA interval load register +#define TIMER_O_TBILR 0x0000002C // TimerB interval load register +#define TIMER_O_TAMATCHR 0x00000030 // TimerA match register +#define TIMER_O_TBMATCHR 0x00000034 // TimerB match register +#define TIMER_O_TAPR 0x00000038 // TimerA prescale register +#define TIMER_O_TBPR 0x0000003C // TimerB prescale register +#define TIMER_O_TAPMR 0x00000040 // TimerA prescale match register +#define TIMER_O_TBPMR 0x00000044 // TimerB prescale match register +#define TIMER_O_TAR 0x00000048 // TimerA register +#define TIMER_O_TBR 0x0000004C // TimerB register + +//***************************************************************************** +// +// The following define the reset values of the timer registers. +// +//***************************************************************************** +#define TIMER_RV_CFG 0x00000000 // Configuration register RV +#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV +#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV +#define TIMER_RV_CTL 0x00000000 // Control register RV +#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV +#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV +#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV +#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV +#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV +#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV +#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV +#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV +#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV +#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV +#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV +#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV +#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV +#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_CFG register. +// +//***************************************************************************** +#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask +#define TIMER_CFG_16_BIT 0x00000004 // Two 16 bit timers +#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32 bit RTC +#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32 bit timer + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_TnMR register. +// +//***************************************************************************** +#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select +#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time +#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask +#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture +#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic +#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_CTL register. +// +//***************************************************************************** +#define TIMER_CTL_TBPWML 0x00004000 // TimerB PWM output level invert +#define TIMER_CTL_TBOTE 0x00002000 // TimerB output trigger enable +#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask +#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // TimerB event mode - both edges +#define TIMER_CTL_TBEVENT_NEG 0x00000400 // TimerB event mode - neg edge +#define TIMER_CTL_TBEVENT_POS 0x00000000 // TimerB event mode - pos edge +#define TIMER_CTL_TBSTALL 0x00000200 // TimerB stall enable +#define TIMER_CTL_TBEN 0x00000100 // TimerB enable +#define TIMER_CTL_TAPWML 0x00000040 // TimerA PWM output level invert +#define TIMER_CTL_TAOTE 0x00000020 // TimerA output trigger enable +#define TIMER_CTL_RTCEN 0x00000010 // RTC counter enable +#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask +#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // TimerA event mode - both edges +#define TIMER_CTL_TAEVENT_NEG 0x00000004 // TimerA event mode - neg edge +#define TIMER_CTL_TAEVENT_POS 0x00000000 // TimerA event mode - pos edge +#define TIMER_CTL_TASTALL 0x00000002 // TimerA stall enable +#define TIMER_CTL_TAEN 0x00000001 // TimerA enable + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_IMR register. +// +//***************************************************************************** +#define TIMER_IMR_CBEIM 0x00000400 // CaptureB event interrupt mask +#define TIMER_IMR_CBMIM 0x00000200 // CaptureB match interrupt mask +#define TIMER_IMR_TBTOIM 0x00000100 // TimerB time out interrupt mask +#define TIMER_IMR_RTCIM 0x00000008 // RTC interrupt mask +#define TIMER_IMR_CAEIM 0x00000004 // CaptureA event interrupt mask +#define TIMER_IMR_CAMIM 0x00000002 // CaptureA match interrupt mask +#define TIMER_IMR_TATOIM 0x00000001 // TimerA time out interrupt mask + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_RIS register. +// +//***************************************************************************** +#define TIMER_RIS_CBERIS 0x00000400 // CaptureB event raw int status +#define TIMER_RIS_CBMRIS 0x00000200 // CaptureB match raw int status +#define TIMER_RIS_TBTORIS 0x00000100 // TimerB time out raw int status +#define TIMER_RIS_RTCRIS 0x00000008 // RTC raw int status +#define TIMER_RIS_CAERIS 0x00000004 // CaptureA event raw int status +#define TIMER_RIS_CAMRIS 0x00000002 // CaptureA match raw int status +#define TIMER_RIS_TATORIS 0x00000001 // TimerA time out raw int status + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_MIS register. +// +//***************************************************************************** +#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status +#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status +#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat +#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status +#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status +#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status +#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_ICR register. +// +//***************************************************************************** +#define TIMER_ICR_CBECINT 0x00000400 // CaptureB event interrupt clear +#define TIMER_ICR_CBMCINT 0x00000200 // CaptureB match interrupt clear +#define TIMER_ICR_TBTOCINT 0x00000100 // TimerB time out interrupt clear +#define TIMER_ICR_RTCCINT 0x00000008 // RTC interrupt clear +#define TIMER_ICR_CAECINT 0x00000004 // CaptureA event interrupt clear +#define TIMER_ICR_CAMCINT 0x00000002 // CaptureA match interrupt clear +#define TIMER_ICR_TATOCINT 0x00000001 // TimerA time out interrupt clear + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_TAILR register. +// +//***************************************************************************** +#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode +#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TBILR register. +// +//***************************************************************************** +#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_TAMATCHR register. +// +//***************************************************************************** +#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode +#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TBMATCHR register. +// +//***************************************************************************** +#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TnPR register. +// +//***************************************************************************** +#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TnPMR register. +// +//***************************************************************************** +#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_TAR register. +// +//***************************************************************************** +#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode +#define TIMER_TAR_TARL 0x0000FFFF // TimerA value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TBR register. +// +//***************************************************************************** +#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value + +#endif // __HW_TIMER_H__ diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/hw_types.h b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/hw_types.h new file mode 100644 index 000000000..a3b9dcbee --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/hw_types.h @@ -0,0 +1,67 @@ +//***************************************************************************** +// +// hw_types.h - Common types and macros. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_TYPES_H__ +#define __HW_TYPES_H__ + +//***************************************************************************** +// +// Define a boolean type, and values for true and false. +// +//***************************************************************************** +typedef unsigned char tBoolean; + +#ifndef true +#define true 1 +#endif + +#ifndef false +#define false 0 +#endif + +//***************************************************************************** +// +// Macros for hardware access, both direct and via the bit-band region. +// +//***************************************************************************** +#define HWREG(x) \ + (*((volatile unsigned long *)(x))) +#define HWREGH(x) \ + (*((volatile unsigned short *)(x))) +#define HWREGB(x) \ + (*((volatile unsigned char *)(x))) +#define HWREGBITW(x, b) \ + HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITH(x, b) \ + HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITB(x, b) \ + HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) + +#endif // __HW_TYPES_H__ diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/hw_uart.h b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/hw_uart.h new file mode 100644 index 000000000..99bdc3c41 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/hw_uart.h @@ -0,0 +1,239 @@ +//***************************************************************************** +// +// hw_uart.h - Macros and defines used when accessing the UART hardware +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_UART_H__ +#define __HW_UART_H__ + +//***************************************************************************** +// +// UART Register Offsets. +// +//***************************************************************************** +#define UART_O_DR 0x00000000 // Data Register +#define UART_O_RSR 0x00000004 // Receive Status Register (read) +#define UART_O_ECR 0x00000004 // Error Clear Register (write) +#define UART_O_FR 0x00000018 // Flag Register (read only) +#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg +#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg +#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte +#define UART_O_CTL 0x00000030 // Control Register +#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg +#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg +#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register +#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register +#define UART_O_ICR 0x00000044 // Interrupt Clear Register +#define UART_O_PeriphID4 0x00000FD0 // +#define UART_O_PeriphID5 0x00000FD4 // +#define UART_O_PeriphID6 0x00000FD8 // +#define UART_O_PeriphID7 0x00000FDC // +#define UART_O_PeriphID0 0x00000FE0 // +#define UART_O_PeriphID1 0x00000FE4 // +#define UART_O_PeriphID2 0x00000FE8 // +#define UART_O_PeriphID3 0x00000FEC // +#define UART_O_PCellID0 0x00000FF0 // +#define UART_O_PCellID1 0x00000FF4 // +#define UART_O_PCellID2 0x00000FF8 // +#define UART_O_PCellID3 0x00000FFC // + +//***************************************************************************** +// +// Data Register bits +// +//***************************************************************************** +#define UART_DR_OE 0x00000800 // Overrun Error +#define UART_DR_BE 0x00000400 // Break Error +#define UART_DR_PE 0x00000200 // Parity Error +#define UART_DR_FE 0x00000100 // Framing Error +#define UART_DR_DATA_MASK 0x000000FF // UART data + +//***************************************************************************** +// +// Receive Status Register bits +// +//***************************************************************************** +#define UART_RSR_OE 0x00000008 // Overrun Error +#define UART_RSR_BE 0x00000004 // Break Error +#define UART_RSR_PE 0x00000002 // Parity Error +#define UART_RSR_FE 0x00000001 // Framing Error + +//***************************************************************************** +// +// Flag Register bits +// +//***************************************************************************** +#define UART_FR_TXFE 0x00000080 // TX FIFO Empty +#define UART_FR_RXFF 0x00000040 // RX FIFO Full +#define UART_FR_TXFF 0x00000020 // TX FIFO Full +#define UART_FR_RXFE 0x00000010 // RX FIFO Empty +#define UART_FR_BUSY 0x00000008 // UART Busy + +//***************************************************************************** +// +// Integer baud-rate divisor +// +//***************************************************************************** +#define UART_IBRD_DIVINT_MASK 0x0000FFFF // Integer baud-rate divisor + +//***************************************************************************** +// +// Fractional baud-rate divisor +// +//***************************************************************************** +#define UART_FBRD_DIVFRAC_MASK 0x0000003F // Fractional baud-rate divisor + +//***************************************************************************** +// +// Line Control Register High bits +// +//***************************************************************************** +#define UART_LCR_H_SPS 0x00000080 // Stick Parity Select +#define UART_LCR_H_WLEN 0x00000060 // Word length +#define UART_LCR_H_WLEN_8 0x00000060 // 8 bit data +#define UART_LCR_H_WLEN_7 0x00000040 // 7 bit data +#define UART_LCR_H_WLEN_6 0x00000020 // 6 bit data +#define UART_LCR_H_WLEN_5 0x00000000 // 5 bit data +#define UART_LCR_H_FEN 0x00000010 // Enable FIFO +#define UART_LCR_H_STP2 0x00000008 // Two Stop Bits Select +#define UART_LCR_H_EPS 0x00000004 // Even Parity Select +#define UART_LCR_H_PEN 0x00000002 // Parity Enable +#define UART_LCR_H_BRK 0x00000001 // Send Break + +//***************************************************************************** +// +// Control Register bits +// +//***************************************************************************** +#define UART_CTL_RXE 0x00000200 // Receive Enable +#define UART_CTL_TXE 0x00000100 // Transmit Enable +#define UART_CTL_LBE 0x00000080 // Loopback Enable +#define UART_CTL_UARTEN 0x00000001 // UART Enable + +//***************************************************************************** +// +// Interrupt FIFO Level Select Register bits +// +//***************************************************************************** +#define UART_IFLS_RX1_8 0x00000000 // 1/8 Full +#define UART_IFLS_RX2_8 0x00000010 // 1/4 Full +#define UART_IFLS_RX4_8 0x00000020 // 1/2 Full +#define UART_IFLS_RX6_8 0x00000030 // 3/4 Full +#define UART_IFLS_RX7_8 0x00000040 // 7/8 Full +#define UART_IFLS_TX1_8 0x00000000 // 1/8 Full +#define UART_IFLS_TX2_8 0x00000001 // 1/4 Full +#define UART_IFLS_TX4_8 0x00000002 // 1/2 Full +#define UART_IFLS_TX6_8 0x00000003 // 3/4 Full +#define UART_IFLS_TX7_8 0x00000004 // 7/8 Full + +//***************************************************************************** +// +// Interrupt Mask Set/Clear Register bits +// +//***************************************************************************** +#define UART_IM_OEIM 0x00000400 // Overrun Error Interrupt Mask +#define UART_IM_BEIM 0x00000200 // Break Error Interrupt Mask +#define UART_IM_PEIM 0x00000100 // Parity Error Interrupt Mask +#define UART_IM_FEIM 0x00000080 // Framing Error Interrupt Mask +#define UART_IM_RTIM 0x00000040 // Receive Timeout Interrupt Mask +#define UART_IM_TXIM 0x00000020 // Transmit Interrupt Mask +#define UART_IM_RXIM 0x00000010 // Receive Interrupt Mask + +//***************************************************************************** +// +// Raw Interrupt Status Register +// +//***************************************************************************** +#define UART_RIS_OERIS 0x00000400 // Overrun Error Interrupt Status +#define UART_RIS_BERIS 0x00000200 // Break Error Interrupt Status +#define UART_RIS_PERIS 0x00000100 // Parity Error Interrupt Status +#define UART_RIS_FERIS 0x00000080 // Framing Error Interrupt Status +#define UART_RIS_RTRIS 0x00000040 // Receive Timeout Interrupt Status +#define UART_RIS_TXRIS 0x00000020 // Transmit Interrupt Status +#define UART_RIS_RXRIS 0x00000010 // Receive Interrupt Status + +//***************************************************************************** +// +// Masked Interrupt Status Register +// +//***************************************************************************** +#define UART_MIS_OEMIS 0x00000400 // Overrun Error Interrupt Status +#define UART_MIS_BEMIS 0x00000200 // Break Error Interrupt Status +#define UART_MIS_PEMIS 0x00000100 // Parity Error Interrupt Status +#define UART_MIS_FEMIS 0x00000080 // Framing Error Interrupt Status +#define UART_MIS_RTMIS 0x00000040 // Receive Timeout Interrupt Status +#define UART_MIS_TXMIS 0x00000020 // Transmit Interrupt Status +#define UART_MIS_RXMIS 0x00000010 // Receive Interrupt Status + +//***************************************************************************** +// +// Interrupt Clear Register bits +// +//***************************************************************************** +#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear +#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear +#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear +#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear +#define UART_ICR_RTIC 0x00000040 // Receive Timeout Interrupt Clear +#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear +#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear + +#define UART_RSR_ANY (UART_RSR_OE | \ + UART_RSR_BE | \ + UART_RSR_PE | \ + UART_RSR_FE) + +//***************************************************************************** +// +// Reset Values for UART Registers. +// +//***************************************************************************** +#define UART_RV_DR 0x00000000 +#define UART_RV_RSR 0x00000000 +#define UART_RV_ECR 0x00000000 +#define UART_RV_FR 0x00000090 +#define UART_RV_IBRD 0x00000000 +#define UART_RV_FBRD 0x00000000 +#define UART_RV_LCR_H 0x00000000 +#define UART_RV_CTL 0x00000300 +#define UART_RV_IFLS 0x00000012 +#define UART_RV_IM 0x00000000 +#define UART_RV_RIS 0x00000000 +#define UART_RV_MIS 0x00000000 +#define UART_RV_ICR 0x00000000 +#define UART_RV_PeriphID4 0x00000000 +#define UART_RV_PeriphID5 0x00000000 +#define UART_RV_PeriphID6 0x00000000 +#define UART_RV_PeriphID7 0x00000000 +#define UART_RV_PeriphID0 0x00000011 +#define UART_RV_PeriphID1 0x00000000 +#define UART_RV_PeriphID2 0x00000018 +#define UART_RV_PeriphID3 0x00000001 +#define UART_RV_PCellID0 0x0000000D +#define UART_RV_PCellID1 0x000000F0 +#define UART_RV_PCellID2 0x00000005 +#define UART_RV_PCellID3 0x000000B1 + +#endif // __HW_UART_H__ diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/hw_watchdog.h b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/hw_watchdog.h new file mode 100644 index 000000000..e9d3f0b5b --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/hw_watchdog.h @@ -0,0 +1,116 @@ +//***************************************************************************** +// +// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_WATCHDOG_H__ +#define __HW_WATCHDOG_H__ + +//***************************************************************************** +// +// The following define the offsets of the Watchdog Timer registers. +// +//***************************************************************************** +#define WDT_O_LOAD 0x00000000 // Load register +#define WDT_O_VALUE 0x00000004 // Current value register +#define WDT_O_CTL 0x00000008 // Control register +#define WDT_O_ICR 0x0000000C // Interrupt clear register +#define WDT_O_RIS 0x00000010 // Raw interrupt status register +#define WDT_O_MIS 0x00000014 // Masked interrupt status register +#define WDT_O_TEST 0x00000418 // Test register +#define WDT_O_LOCK 0x00000C00 // Lock register +#define WDT_O_PeriphID4 0x00000FD0 // +#define WDT_O_PeriphID5 0x00000FD4 // +#define WDT_O_PeriphID6 0x00000FD8 // +#define WDT_O_PeriphID7 0x00000FDC // +#define WDT_O_PeriphID0 0x00000FE0 // +#define WDT_O_PeriphID1 0x00000FE4 // +#define WDT_O_PeriphID2 0x00000FE8 // +#define WDT_O_PeriphID3 0x00000FEC // +#define WDT_O_PCellID0 0x00000FF0 // +#define WDT_O_PCellID1 0x00000FF4 // +#define WDT_O_PCellID2 0x00000FF8 // +#define WDT_O_PCellID3 0x00000FFC // + +//***************************************************************************** +// +// The following define the bit fields in the WDT_CTL register. +// +//***************************************************************************** +#define WDT_CTL_RESEN 0x00000002 // Enable reset output +#define WDT_CTL_INTEN 0x00000001 // Enable the WDT counter and int + +//***************************************************************************** +// +// The following define the bit fields in the WDT_ISR, WDT_RIS, and WDT_MIS +// registers. +// +//***************************************************************************** +#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired + +//***************************************************************************** +// +// The following define the bit fields in the WDT_TEST register. +// +//***************************************************************************** +#define WDT_TEST_STALL 0x00000100 // Watchdog stall enable +#ifndef DEPRECATED +#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable +#endif + +//***************************************************************************** +// +// The following define the bit fields in the WDT_LOCK register. +// +//***************************************************************************** +#define WDT_LOCK_LOCKED 0x00000001 // Watchdog timer is locked +#define WDT_LOCK_UNLOCKED 0x00000000 // Watchdog timer is unlocked +#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer + +//***************************************************************************** +// +// The following define the reset values for the WDT registers. +// +//***************************************************************************** +#define WDT_RV_LOAD 0xFFFFFFFF // Load register +#define WDT_RV_VALUE 0xFFFFFFFF // Current value register +#define WDT_RV_CTL 0x00000000 // Control register +#define WDT_RV_RIS 0x00000000 // Raw interrupt status register +#define WDT_RV_MIS 0x00000000 // Masked interrupt status register +#define WDT_RV_LOCK 0x00000000 // Lock register +#define WDT_RV_PeriphID4 0x00000000 // +#define WDT_RV_PeriphID5 0x00000000 // +#define WDT_RV_PeriphID6 0x00000000 // +#define WDT_RV_PeriphID7 0x00000000 // +#define WDT_RV_PeriphID0 0x00000005 // +#define WDT_RV_PeriphID1 0x00000018 // +#define WDT_RV_PeriphID2 0x00000018 // +#define WDT_RV_PeriphID3 0x00000001 // +#define WDT_RV_PCellID0 0x0000000D // +#define WDT_RV_PCellID1 0x000000F0 // +#define WDT_RV_PCellID2 0x00000005 // +#define WDT_RV_PCellID3 0x000000B1 // + +#endif // __HW_WATCHDOG_H__ diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/i2c.h b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/i2c.h new file mode 100644 index 000000000..26bb1dd63 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/i2c.h @@ -0,0 +1,137 @@ +//***************************************************************************** +// +// i2c.h - Prototypes for the I2C Driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __I2C_H__ +#define __I2C_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Defines for the API. +// +//***************************************************************************** +//***************************************************************************** +// +// Interrupt defines. +// +//***************************************************************************** +#define I2C_INT_MASTER 0x00000001 +#define I2C_INT_SLAVE 0x00000002 + +//***************************************************************************** +// +// I2C Master commands. +// +//***************************************************************************** +#define I2C_MASTER_CMD_SINGLE_SEND \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_SINGLE_RECEIVE \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_SEND_START \ + (I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_SEND_CONT \ + (I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_SEND_FINISH \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \ + (I2C_MASTER_CS_STOP) +#define I2C_MASTER_CMD_BURST_RECEIVE_START \ + (I2C_MASTER_CS_ACK | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \ + (I2C_MASTER_CS_ACK | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) + +//***************************************************************************** +// +// I2C Master error status. +// +//***************************************************************************** +#define I2C_MASTER_ERR_NONE 0 +#define I2C_MASTER_ERR_ADDR_ACK 0x00000004 +#define I2C_MASTER_ERR_DATA_ACK 0x00000008 +#define I2C_MASTER_ERR_ARB_LOST 0x00000010 + +//***************************************************************************** +// +// I2C Slave action requests +// +//***************************************************************************** +#define I2C_SLAVE_ACT_NONE 0 +#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data +#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data + +//***************************************************************************** +// Miscellaneous I2C driver definitions. +//***************************************************************************** +#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void)); +extern void I2CIntUnregister(unsigned long ulBase); +extern tBoolean I2CMasterBusBusy(unsigned long ulBase); +extern tBoolean I2CMasterBusy(unsigned long ulBase); +extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd); +extern unsigned long I2CMasterDataGet(unsigned long ulBase); +extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData); +extern void I2CMasterDisable(unsigned long ulBase); +extern void I2CMasterEnable(unsigned long ulBase); +extern unsigned long I2CMasterErr(unsigned long ulBase); +extern void I2CMasterInit(unsigned long ulBase, tBoolean bFast); +extern void I2CMasterIntClear(unsigned long ulBase); +extern void I2CMasterIntDisable(unsigned long ulBase); +extern void I2CMasterIntEnable(unsigned long ulBase); +extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void I2CMasterSlaveAddrSet(unsigned long ulBase, + unsigned char ucSlaveAddr, + tBoolean bReceive); +extern unsigned long I2CSlaveDataGet(unsigned long ulBase); +extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData); +extern void I2CSlaveDisable(unsigned long ulBase); +extern void I2CSlaveEnable(unsigned long ulBase); +extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr); +extern void I2CSlaveIntClear(unsigned long ulBase); +extern void I2CSlaveIntDisable(unsigned long ulBase); +extern void I2CSlaveIntEnable(unsigned long ulBase); +extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked); +extern unsigned long I2CSlaveStatus(unsigned long ulBase); + +#ifdef __cplusplus +} +#endif + +#endif // __I2C_H__ diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/interrupt.h b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/interrupt.h new file mode 100644 index 000000000..98f0f862c --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/interrupt.h @@ -0,0 +1,57 @@ +//***************************************************************************** +// +// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void IntMasterEnable(void); +extern void IntMasterDisable(void); +extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)); +extern void IntUnregister(unsigned long ulInterrupt); +extern void IntPriorityGroupingSet(unsigned long ulBits); +extern unsigned long IntPriorityGroupingGet(void); +extern void IntPrioritySet(unsigned long ulInterrupt, + unsigned char ucPriority); +extern long IntPriorityGet(unsigned long ulInterrupt); +extern void IntEnable(unsigned long ulInterrupt); +extern void IntDisable(unsigned long ulInterrupt); + +#ifdef __cplusplus +} +#endif + +#endif // __INTERRUPT_H__ diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/libdriver.a b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/libdriver.a new file mode 100644 index 0000000000000000000000000000000000000000..c465e8f71dd00cc7357c7b459daa0c2b87d09020 GIT binary patch literal 46076 zcmdUY4|rY0b?3Z4vSs<%l4TiWW8mozjf`bSwgfmSO=LYG8*F1^8$wgMyk|)u*+LSM zOmIqx5)%p=@@5^`ex?j^mOq%aGm0NuY zjraGPnRD;Vy!UG31e%O}b?2P(n=^mz+_~q>%)PJa+QLNt(7S5hp7q0q4P9LuuGx6? zHJh^84lQ#3X0u%#8#bC0`5L9vaiwaDKmM`$Ri!E&tw)r4qsNBZl=?{>JufTuRvfo< zD|J4{zK4{0qsLuOD)rNJeB?2uDjlCde|j^I&wfLxpUm-|!c_mzz}TI;4~~uwkKU<- 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b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/pdc.c new file mode 100644 index 000000000..dfcf418bc --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/pdc.c @@ -0,0 +1,724 @@ +//***************************************************************************** +// +// pdc.c - Driver for the Peripheral Device Controller (PDC) on the Stellaris +// development board. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup utilities_api +//! @{ +// +//***************************************************************************** + +#include "hw_memmap.h" +#include "hw_types.h" +#include "debug.h" +#include "gpio.h" +#include "ssi.h" +#include "sysctl.h" +#include "pdc.h" + +//***************************************************************************** +// +//! Initializes the connection to the PDC. +//! +//! This function will enable clocking to the SSI and GPIO A modules, configure +//! the GPIO pins to be used for an SSI interface, and it will configure the +//! SSI as a 1 Mbps master device, operating in MOTO mode. It will also enable +//! the SSI module, and will enable the chip select for the PDC on the +//! Stellaris development board. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return None. +// +//***************************************************************************** +void +PDCInit(void) +{ + // + // Enable the peripherals used to drive the PDC. + // + SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + + // + // Configure the appropriate pins to be SSI instead of GPIO. + // + GPIODirModeSet(GPIO_PORTA_BASE, SSI_CLK | SSI_TX | SSI_RX, + GPIO_DIR_MODE_HW); + GPIODirModeSet(GPIO_PORTA_BASE, SSI_CS, GPIO_DIR_MODE_OUT); + GPIOPadConfigSet(GPIO_PORTA_BASE, SSI_CLK, GPIO_STRENGTH_4MA, + GPIO_PIN_TYPE_STD_WPU); + + // + // Configure the SSI port. + // + SSIConfigSetExpClk(SSI_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, + SSI_MODE_MASTER, 1000000, 8); + SSIEnable(SSI_BASE); + + // + // Reset the PDC SSI state machine. The chip select needs to be held low + // for 100ns; the procedure call overhead more than accounts for this time. + // + GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, 0); + GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, PDC_CS); +} + +//***************************************************************************** +// +//! Read a PDC register. +//! +//! \param ucAddr specifies the PDC register to read. +//! +//! This function will perform the SSI transfers required to read a register in +//! the PDC on the Stellaris development board. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return Returns the value read from the PDC. +// +//***************************************************************************** +unsigned char +PDCRead(unsigned char ucAddr) +{ + unsigned long ulTemp; + + // + // Send address and read command. + // + SSIDataPut(SSI_BASE, (ucAddr & 0x0F) | PDC_RD); + + // + // Dummy write to force read. + // + SSIDataPut(SSI_BASE, 0x00); + + // + // Flush data read during address write. + // + SSIDataGet(SSI_BASE, &ulTemp); + + // + // If the LCD control register or RAM is being read, then an additional + // byte needs to be transferred. + // + if((ucAddr == PDC_LCD_CSR) || (ucAddr == PDC_LCD_RAM)) + { + // + // Dummy write to force read. + // + SSIDataPut(SSI_BASE, 0x00); + + // + // Flush read data. + // + SSIDataGet(SSI_BASE, &ulTemp); + } + + // + // Read valid data. + // + SSIDataGet(SSI_BASE, &ulTemp); + + // + // Return the data read. + // + return(ulTemp & 0xFF); +} + +//***************************************************************************** +// +//! Write a PDC register. +//! +//! \param ucAddr specifies the PDC register to write. +//! \param ucData specifies the data to write. +//! +//! This function will perform the SSI transfers required to write a register +//! in the PDC on the Stellaris development board. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return None. +// +//***************************************************************************** +void +PDCWrite(unsigned char ucAddr, unsigned char ucData) +{ + unsigned long ulTemp; + + // + // Send address and write command. + // + SSIDataPut(SSI_BASE, (ucAddr & 0x0F) | PDC_WR); + + // + // Write the data. + // + SSIDataPut(SSI_BASE, ucData); + + // + // Flush data read during address write. + // + SSIDataGet(SSI_BASE, &ulTemp); + + // + // Flush data read during data write. + // + SSIDataGet(SSI_BASE, &ulTemp); +} + +//***************************************************************************** +// +//! Read the current value of the PDC DIP switches. +//! +//! This function will read the current value of the DIP switches attached to +//! the PDC on the Stellaris development board. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return The current state of the DIP switches. +// +//***************************************************************************** +unsigned char +PDCDIPRead(void) +{ + return(PDCRead(PDC_DSW)); +} + +//***************************************************************************** +// +//! Write to the PDC LEDs. +//! +//! \param ucLED value to write to the LEDs. +//! +//! This function set the state of the LEDs connected to the PDC on the +//! Stellaris development board. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return None. +// +//***************************************************************************** +void +PDCLEDWrite(unsigned char ucLED) +{ + PDCWrite(PDC_LED, ucLED); +} + +//***************************************************************************** +// +//! Read the current status of the PDC LEDs. +//! +//! This function will read the state of the LEDs connected to the PDC on the +//! Stellaris development board. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return The value currently displayed by the LEDs. +// +//***************************************************************************** +unsigned char +PDCLEDRead(void) +{ + return(PDCRead(PDC_LED)); +} + +//***************************************************************************** +// +//! Initializes the LCD display. +//! +//! This function will set up the LCD display for writing. It will set the +//! data bus to 8 bits, set the number of lines to 2, and the font size to +//! 5x10. It will also turn the display off, clear the display, turn the +//! display back on, and enable the backlight. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \note The PDC must be initialized via the PDCInit() function before this +//! function can be called. Also, it may be necessary to adjust the contrast +//! potentiometer in order to discern any output on the LCD display. +//! +//! \return None. +// +//***************************************************************************** +void +PDCLCDInit(void) +{ + unsigned char pucCfg[] = + { + 0x3C, // Number of lines = 2 / font = 5x10 + 0x08, // Display off + 0x01, // Display clear + 0x06, // Entry mode [cursor dir][shift] + 0x0C, // Display on [display on][curson on][blinking on] + }; + unsigned long ulIdx; + + // + // Set the data bus width to eight bits. + // + PDCWrite(PDC_LCD_CSR, 0x30); + + // + // Wait for 4.1ms by reading the PDC version register enough times to + // guarantee that amount of time has passed. + // + for(ulIdx = 0; ulIdx < 257; ulIdx++) + { + PDCRead(PDC_VER); + } + + // + // Set the data bus width to eight bits. + // + PDCWrite(PDC_LCD_CSR, 0x30); + + // + // Wait for 100us by reading the PDC version register enough times to + // guarantee that amount of time has passed. This works out to 112us plus + // overhead. + // + for(ulIdx = 0; ulIdx < 7; ulIdx++) + { + PDCRead(PDC_VER); + } + + // + // Set the data bus width to eight bits. + // + PDCWrite(PDC_LCD_CSR, 0x30); + + // + // Configure the LCD. + // + for(ulIdx = 0; ulIdx < (sizeof(pucCfg) / sizeof(pucCfg[0])); ulIdx++) + { + // + // Wait until the LCD has finished executing any previous command. + // + while((PDCRead(PDC_LCD_CSR) & LCD_B_BUSY)) + { + } + + // + // Write the next configuration byte. + // + PDCWrite(PDC_LCD_CSR, pucCfg[ulIdx]); + } +} + +//***************************************************************************** +// +//! Turns on the backlight. +//! +//! This function turns on the backlight on the LCD. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return None. +// +//***************************************************************************** +void +PDCLCDBacklightOn(void) +{ + PDCWrite(PDC_CSR, 0x01); +} + +//***************************************************************************** +// +//! Turn off the backlight. +//! +//! This function turns off the backlight on the LCD. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return None. +// +//***************************************************************************** +void +PDCLCDBacklightOff(void) +{ + PDCWrite(PDC_CSR, 0x00); +} + +//***************************************************************************** +// +//! Clear the screen. +//! +//! This function clears the contents of the LCD screen. The cursor will be +//! returned to the upper left corner. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return None. +// +//***************************************************************************** +void +PDCLCDClear(void) +{ + // + // Wait until the LCD has finished executing any previous command. + // + while((PDCRead(PDC_LCD_CSR) & LCD_B_BUSY)) + { + } + + // + // Write the clear display command. + // + PDCWrite(PDC_LCD_CSR, LCD_CLEAR); +} + +//***************************************************************************** +// +//! Write a character pattern to the LCD. +//! +//! \param ucChar is the character index to create. Valid values are zero +//! through seven. +//! \param pucData is the data for the character pattern. It contains eight +//! bytes, with the first byte being the top row of the pattern. In each byte, +//! the LSB is the right pixel of the pattern. +//! +//! This function will write a character pattern into the LCD for use as a +//! character to be displayed. After writing the pattern, it can be used on +//! the LCD by writing the corresponding character index to the display. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return None. +// +//***************************************************************************** +void +PDCLCDCreateChar(unsigned char ucChar, unsigned char *pucData) +{ + // + // Check the arguments. + // + ASSERT(ucChar < 8); + + // + // Wait until the LCD has finished executing any previous command. + // + while((PDCRead(PDC_LCD_CSR) & LCD_B_BUSY)) + { + } + + // + // Write the character pattern memory address. + // + PDCWrite(PDC_LCD_CSR, LCD_CGADDR + (ucChar * 8)); + + // + // Write the pattern to chacter pattern memory. + // + for(ucChar = 0; ucChar < 8; ucChar++) + { + // + // Wait until the LCD has finished executing any previous command. + // + while((PDCRead(PDC_LCD_CSR) & LCD_B_BUSY)) + { + } + + // + // Write this row of the pattern. + // + PDCWrite(PDC_LCD_RAM, *pucData++); + } +} + +//***************************************************************************** +// +//! Set the position of the cursor. +//! +//! \param ucX is the horizontal position. Valid values are zero through +//! fifteen. +//! \param ucY is the vertical position.. Valid values are zero and one. +//! +//! This function will move the cursor to the specified position. All +//! characters written to the LCD are placed at the current cursor position, +//! which is automatically advanced. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return None. +// +//***************************************************************************** +void +PDCLCDSetPos(unsigned char ucX, unsigned char ucY) +{ + // + // Check the arguments. + // + ASSERT(ucX < 16); + ASSERT(ucY < 2); + + // + // Wait until the LCD has finished executing any previous command. + // + while((PDCRead(PDC_LCD_CSR) & LCD_B_BUSY)) + { + } + + // + // Set the cursor position. + // + PDCWrite(PDC_LCD_CSR, LCD_DDADDR | (0x40 * ucY) + ucX); +} + +//***************************************************************************** +// +//! Writes a string to the LCD display. +//! +//! \param pcStr pointer to the string to be displayed. +//! \param ulCount is the number of characters to be displayed. +//! +//! This function will display a string on the LCD at the current cursor +//! position. It is the caller's responsibility to position the cursor to the +//! place where the string should be displayed (either explicitly via +//! PDCLCDSetPos() or implicitly from where the cursor was left after a +//! previous call to PDCLCDWrite()), and to properly account for the LCD +//! boundary (line wrapping is not automatically performed). Null characters +//! are not treated special and are written to the LCD, which interprets it as +//! a special programmable character glyph (see PDCLCDCreateChar()). +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return None. +// +//***************************************************************************** +void +PDCLCDWrite(const char *pcStr, unsigned long ulCount) +{ + // + // Write the string to the LCD. + // + while(ulCount--) + { + // + // Wait until the LCD has finished executing any previous command. + // + while((PDCRead(PDC_LCD_CSR) & LCD_B_BUSY)) + { + } + + // + // Write this character to the LCD. + // + PDCWrite(PDC_LCD_RAM, *pcStr++); + } +} + +//***************************************************************************** +// +//! Reads a GPIO direction register. +//! +//! \param ucIdx is the index of the GPIO direction register to read; valid +//! values are 0, 1, and 2. +//! +//! This function reads one of the GPIO direction registers in the PDC. The +//! direction bit is set for pins that are outputs and clear for pins that are +//! inputs. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return The contents of the direction register. +// +//***************************************************************************** +unsigned char +PDCGPIODirRead(unsigned char ucIdx) +{ + // + // Check the argument. + // + ASSERT((ucIdx == 0) || (ucIdx == 1) || (ucIdx == 2)); + + // + // Read the requested direction register. + // + if(ucIdx == 0) + { + return(PDCRead(PDC_GPXDIR)); + } + else if(ucIdx == 1) + { + return(PDCRead(PDC_GPYDIR)); + } + else + { + return(PDCRead(PDC_GPZDIR)); + } +} + +//***************************************************************************** +// +//! Write a GPIO direction register. +//! +//! \param ucIdx is the index of the GPIO direction register to write; valid +//! values are 0, 1, and 2. +//! \param ucValue is the value to write to the GPIO direction register. +//! +//! This function writes ones of the GPIO direction registers in the PDC. The +//! direction bit should be set for pins that are to be outputs and clear for +//! pins that are to be inputs. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return None. +// +//***************************************************************************** +void +PDCGPIODirWrite(unsigned char ucIdx, unsigned char ucValue) +{ + // + // Check the arguments. + // + ASSERT((ucIdx == 0) || (ucIdx == 1) || (ucIdx == 2)); + + // + // Write the requested direction register. + // + if(ucIdx == 0) + { + PDCWrite(PDC_GPXDIR, ucValue); + } + else if(ucIdx == 1) + { + PDCWrite(PDC_GPYDIR, ucValue); + } + else + { + PDCWrite(PDC_GPZDIR, ucValue); + } +} + +//***************************************************************************** +// +//! Reads a GPIO data register. +//! +//! \param ucIdx is the index of the GPIO direction register to read; valid +//! values are 0, 1, and 2. +//! +//! This function reads one of the GPIO data registers in the PDC. The value +//! returned for a pin is the value being driven out for outputs or the value +//! being read for inputs. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return The contents of the data register. +// +//***************************************************************************** +unsigned char +PDCGPIORead(unsigned char ucIdx) +{ + // + // Check the argument. + // + ASSERT((ucIdx == 0) || (ucIdx == 1) || (ucIdx == 2)); + + // + // Read the requested data register. + // + if(ucIdx == 0) + { + return(PDCRead(PDC_GPXDAT)); + } + else if(ucIdx == 1) + { + return(PDCRead(PDC_GPYDAT)); + } + else + { + return(PDCRead(PDC_GPZDAT)); + } +} + +//***************************************************************************** +// +//! Write a GPIO data register. +//! +//! \param ucIdx is the index of the GPIO data register to write; valid values +//! are 0, 1, and 2. +//! \param ucValue is the value to write to the GPIO data register. +//! +//! This function writes one of the GPIO direction registers in the PDC. The +//! written to a pin is driven out for output pins and ignored for input pins. +//! +//! This function is contained in utils/pdc.c, with +//! utils/pdc.h containing the API definition for use by applications. +//! +//! \return None. +// +//***************************************************************************** +void +PDCGPIOWrite(unsigned char ucIdx, unsigned char ucValue) +{ + // + // Check the arguments. + // + ASSERT((ucIdx == 0) || (ucIdx == 1) || (ucIdx == 2)); + + // + // Write the requested data register. + // + if(ucIdx == 0) + { + PDCWrite(PDC_GPXDAT, ucValue); + } + else if(ucIdx == 1) + { + PDCWrite(PDC_GPYDAT, ucValue); + } + else + { + PDCWrite(PDC_GPZDAT, ucValue); + } +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/pdc.h b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/pdc.h new file mode 100644 index 000000000..952942446 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/pdc.h @@ -0,0 +1,124 @@ +//***************************************************************************** +// +// pdc.h - Stellaris development board Peripheral Device Controller definitions +// and prototypes. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __PDC_H__ +#define __PDC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The registers within the peripheral device controller. +// +//***************************************************************************** +#define PDC_VER 0x0 // Version register +#define PDC_CSR 0x1 // Command/Status register +#define PDC_DSW 0x4 // DIP Switch register +#define PDC_LED 0x5 // LED register +#define PDC_LCD_CSR 0x6 // LCD Command/Status register +#define PDC_LCD_RAM 0x7 // LCD RAM register +#define PDC_GPXDAT 0x8 // GPIO X Data register +#define PDC_GPXDIR 0x9 // GPIO X Direction register +#define PDC_GPYDAT 0xA // GPIO Y Data register +#define PDC_GPYDIR 0xB // GPIO Y Direction register +#define PDC_GPZDAT 0xC // GPIO Z Data register +#define PDC_GPZDIR 0xD // GPIO Z Direction register + +//***************************************************************************** +// +// Flags indicating a read or write to the peripheral device controller. +// +//***************************************************************************** +#define PDC_RD 0x80 // PDC read command +#define PDC_WR 0x00 // PDC write command + +//***************************************************************************** +// +// LCD panel (Crystalfontz CFAH1602B) commands, RS = 0 +// +//***************************************************************************** +#define LCD_CLEAR 0x01 // Clear display (0 fill DDRAM). +#define LCD_HOME 0x02 // Cursor home. +#define LCD_MODE 0x04 // Set entry mode (cursor dir) +#define LCD_ON 0x08 // Set display, cursor, blinking + // on/off +#define LCD_CUR 0x10 // Cursor, display shift +#define LCD_IF 0x20 // Set interface data length, + // lines, font +#define LCD_CGADDR 0x40 // Set CGRAM AC address +#define LCD_DDADDR 0x80 // Set DDRAM AC address + +//***************************************************************************** +// +// LCD Status bit +// +//***************************************************************************** +#define LCD_B_BUSY 0x80 // Busy flag. + +//***************************************************************************** +// +// The GPIO port A pin numbers for the various SSI signals. +// +//***************************************************************************** +#define SSI_CS GPIO_PIN_3 +#define PDC_CS GPIO_PIN_3 +#define SSI_CLK GPIO_PIN_2 +#define SSI_TX GPIO_PIN_5 +#define SSI_RX GPIO_PIN_4 + +//***************************************************************************** +// +// Function Prototypes +// +//***************************************************************************** +extern void PDCInit(void); +extern unsigned char PDCRead(unsigned char ucAddr); +extern void PDCWrite(unsigned char ucAddr, unsigned char ucData); +extern unsigned char PDCDIPRead(void); +extern void PDCLEDWrite(unsigned char ucLED); +extern unsigned char PDCLEDRead(void); +extern void PDCLCDInit(void); +extern void PDCLCDBacklightOn(void); +extern void PDCLCDBacklightOff(void); +extern void PDCLCDClear(void); +extern void PDCLCDCreateChar(unsigned char ucChar, unsigned char *pucData); +extern void PDCLCDSetPos(unsigned char ucX, unsigned char ucY); +extern void PDCLCDWrite(const char *pcStr, unsigned long ulCount); +extern unsigned char PDCGPIODirRead(unsigned char ucIdx); +extern void PDCGPIODirWrite(unsigned char ucIdx, unsigned char ucValue); +extern unsigned char PDCGPIORead(unsigned char ucIdx); +extern void PDCGPIOWrite(unsigned char ucIdx, unsigned char ucValue); + +#ifdef __cplusplus +} +#endif + +#endif // __PDC_H__ diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/pwm.h b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/pwm.h new file mode 100644 index 000000000..13cd4e1a1 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/pwm.h @@ -0,0 +1,161 @@ +//***************************************************************************** +// +// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __PWM_H__ +#define __PWM_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following defines are passed to PWMGenConfigure() as the ulConfig +// parameter and specify the configuration of the PWM generator. +// +//***************************************************************************** +#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode +#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode +#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates +#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates +#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode +#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode + +//***************************************************************************** +// +// Defines for enabling, disabling, and clearing PWM generator interrupts and +// triggers. +// +//***************************************************************************** +#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0 +#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD +#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U +#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D +#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U +#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D +#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0 +#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD +#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U +#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D +#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U +#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D + +//***************************************************************************** +// +// Defines for enabling, disabling, and clearing PWM interrupts. +// +//***************************************************************************** +#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt +#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt +#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt +#define PWM_INT_FAULT 0x00010000 // Fault interrupt + +//***************************************************************************** +// +// Defines to identify the generators within a module. +// +//***************************************************************************** +#define PWM_GEN_0 0x00000040 // Offset address of Gen0 +#define PWM_GEN_1 0x00000080 // Offset address of Gen1 +#define PWM_GEN_2 0x000000C0 // Offset address of Gen2 + +#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0 +#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1 +#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2 + +//***************************************************************************** +// +// Defines to identify the outputs within a module. +// +//***************************************************************************** +#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0 +#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1 +#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2 +#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3 +#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4 +#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5 + +#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0 +#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1 +#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2 +#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3 +#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4 +#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5 + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen, + unsigned long ulConfig); +extern void PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen, + unsigned long ulPeriod); +extern unsigned long PWMGenPeriodGet(unsigned long ulBase, + unsigned long ulGen); +extern void PWMGenEnable(unsigned long ulBase, unsigned long ulGen); +extern void PWMGenDisable(unsigned long ulBase, unsigned long ulGen); +extern void PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut, + unsigned long ulWidth); +extern unsigned long PWMPulseWidthGet(unsigned long ulBase, + unsigned long ulPWMOut); +extern void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen, + unsigned short usRise, unsigned short usFall); +extern void PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen); +extern void PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits); +extern void PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits); +extern void PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bEnable); +extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bInvert); +extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bFaultKill); +extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen, + void (*pfIntHandler)(void)); +extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen); +extern void PWMFaultIntRegister(unsigned long ulBase, + void (*pfIntHandler)(void)); +extern void PWMFaultIntUnregister(unsigned long ulBase); +extern void PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen, + unsigned long ulIntTrig); +extern void PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen, + unsigned long ulIntTrig); +extern unsigned long PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen, + tBoolean bMasked); +extern void PWMGenIntClear(unsigned long ulBase, unsigned long ulGen, + unsigned long ulInts); +extern void PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault); +extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault); +extern void PWMFaultIntClear(unsigned long ulBase); +extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked); + +#ifdef __cplusplus +} +#endif + +#endif // __PWM_H__ diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/ssi.h b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/ssi.h new file mode 100644 index 000000000..eb1374040 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/ssi.h @@ -0,0 +1,92 @@ +//***************************************************************************** +// +// ssi.h - Prototypes for the Synchronous Serial Interface Driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __SSI_H__ +#define __SSI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear +// as the ulIntFlags parameter, and returned by SSIIntStatus. +// +//***************************************************************************** +#define SSI_TXFF 0x00000008 // TX FIFO half empty or less +#define SSI_RXFF 0x00000004 // RX FIFO half full or less +#define SSI_RXTO 0x00000002 // RX timeout +#define SSI_RXOR 0x00000001 // RX overrun + +//***************************************************************************** +// +// Values that can be passed to SSIConfig. +// +//***************************************************************************** +#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0 +#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1 +#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0 +#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1 +#define SSI_FRF_TI 0x00000010 // TI frame format +#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format + +#define SSI_MODE_MASTER 0x00000000 // SSI master +#define SSI_MODE_SLAVE 0x00000001 // SSI slave +#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void SSIConfig(unsigned long ulBase, unsigned long ulProtocol, + unsigned long ulMode, unsigned long ulBitRate, + unsigned long ulDataWidth); +extern void SSIDataGet(unsigned long ulBase, unsigned long *ulData); +extern long SSIDataNonBlockingGet(unsigned long ulBase, unsigned long *ulData); +extern void SSIDataPut(unsigned long ulBase, unsigned long ulData); +extern long SSIDataNonBlockingPut(unsigned long ulBase, unsigned long ulData); +extern void SSIDisable(unsigned long ulBase); +extern void SSIEnable(unsigned long ulBase); +extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void SSIIntUnregister(unsigned long ulBase); +extern void SSIConfigSetExpClk(unsigned long ulBase, unsigned long ulSSIClk, + unsigned long ulProtocol, unsigned long ulMode, + unsigned long ulBitRate, + unsigned long ulDataWidth); + +#ifdef __cplusplus +} +#endif + +#endif // __SSI_H__ diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/startup.c b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/startup.c new file mode 100644 index 000000000..1fd39f5bf --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/startup.c @@ -0,0 +1,194 @@ +//***************************************************************************** +// +// startup.c - Boot code for Stellaris. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +// Enable the IAR extensions for this source file. +// +//***************************************************************************** +#pragma language=extended + +//***************************************************************************** +// +// Forward declaration of the default fault handlers. +// +//***************************************************************************** +static void NmiSR(void); +static void FaultISR(void); +static void IntDefaultHandler(void); + +//***************************************************************************** +// +// External declaration for the interrupt handler used by the application. +// +//***************************************************************************** +extern void xPortPendSVHandler(void); +extern void xPortSysTickHandler(void); +extern void vUART_ISR( void ); + +//***************************************************************************** +// +// The entry point for the application. +// +//***************************************************************************** +extern void __iar_program_start(void); + +//***************************************************************************** +// +// Reserve space for the system stack. +// +//***************************************************************************** +#ifndef STACK_SIZE +#define STACK_SIZE 50 +#endif +static unsigned long pulStack[STACK_SIZE] @ ".noinit"; +//***************************************************************************** +// +// A union that describes the entries of the vector table. The union is needed +// since the first entry is the stack pointer and the remainder are function +// pointers. +// +//***************************************************************************** +typedef union +{ + void (*pfnHandler)(void); + unsigned long ulPtr; +} +uVectorEntry; + +//***************************************************************************** +// +// The minimal vector table for a Cortex M3. Note that the proper constructs +// must be placed on this to ensure that it ends up at physical address +// 0x0000.0000. +// +//***************************************************************************** +__root const uVectorEntry __vector_table[] @ ".intvec" = +{ + { .ulPtr = (unsigned long)pulStack + sizeof(pulStack) }, + // The initial stack pointer + __iar_program_start, // The reset handler + NmiSR, // The NMI handler + FaultISR, // The hard fault handler + IntDefaultHandler, // The MPU fault handler + IntDefaultHandler, // The bus fault handler + IntDefaultHandler, // The usage fault handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // SVCall handler + IntDefaultHandler, // Debug monitor handler + 0, // Reserved + xPortPendSVHandler, // The PendSV handler + xPortSysTickHandler, // The SysTick handler + IntDefaultHandler, // GPIO Port A + IntDefaultHandler, // GPIO Port B + IntDefaultHandler, // GPIO Port C + IntDefaultHandler, // GPIO Port D + IntDefaultHandler, // GPIO Port E + vUART_ISR, // UART0 Rx and Tx + IntDefaultHandler, // UART1 Rx and Tx + IntDefaultHandler, // SSI Rx and Tx + IntDefaultHandler, // I2C Master and Slave + IntDefaultHandler, // PWM Fault + IntDefaultHandler, // PWM Generator 0 + IntDefaultHandler, // PWM Generator 1 + IntDefaultHandler, // PWM Generator 2 + 0, // Reserved + IntDefaultHandler, // ADC Sequence 0 + IntDefaultHandler, // ADC Sequence 1 + IntDefaultHandler, // ADC Sequence 2 + IntDefaultHandler, // ADC Sequence 3 + IntDefaultHandler, // Watchdog timer + IntDefaultHandler, // Timer 0 subtimer A + IntDefaultHandler, // Timer 0 subtimer B + IntDefaultHandler, // Timer 1 subtimer A + IntDefaultHandler, // Timer 1 subtimer B + IntDefaultHandler, // Timer 2 subtimer A + IntDefaultHandler, // Timer 2 subtimer B + IntDefaultHandler, // Analog Comparator 0 + IntDefaultHandler, // Analog Comparator 1 + IntDefaultHandler, // Analog Comparator 2 + IntDefaultHandler, // System Control (PLL, OSC, BO) + IntDefaultHandler // FLASH Control +}; + + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a NMI. This +// simply enters an infinite loop, preserving the system state for examination +// by a debugger. +// +//***************************************************************************** +static void +NmiSR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a fault +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +FaultISR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives an unexpected +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +IntDefaultHandler(void) +{ + // + // Go into an infinite loop. + // + while(1) + { + } +} diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/sysctl.h b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/sysctl.h new file mode 100644 index 000000000..c5e065012 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/sysctl.h @@ -0,0 +1,266 @@ +//***************************************************************************** +// +// sysctl.h - Prototypes for the system control driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __SYSCTL_H__ +#define __SYSCTL_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed to the +// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(), +// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the +// ulPeripheral parameter. The peripherals in the fourth group (upper nibble +// is 3) can only be used with the SysCtlPeripheralPresent() API. +// +//***************************************************************************** +#define SYSCTL_PERIPH_PWM 0x00100000 // PWM +#define SYSCTL_PERIPH_ADC 0x00010000 // ADC +#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog +#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0 +#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1 +#define SYSCTL_PERIPH_SSI 0x10000010 // SSI +#define SYSCTL_PERIPH_I2C 0x10001000 // I2C +#define SYSCTL_PERIPH_TIMER0 0x10010000 // Timer 0 +#define SYSCTL_PERIPH_TIMER1 0x10020000 // Timer 1 +#define SYSCTL_PERIPH_TIMER2 0x10040000 // Timer 2 +#define SYSCTL_PERIPH_COMP0 0x11000000 // Analog comparator 0 +#define SYSCTL_PERIPH_COMP1 0x12000000 // Analog comparator 1 +#define SYSCTL_PERIPH_COMP2 0x14000000 // Analog comparator 2 +#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A +#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B +#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C +#define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D +#define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E +#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex M3 MPU +#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor +#define SYSCTL_PERIPH_PLL 0x30000010 // PLL + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlPinPresent() API +// as the ulPin parameter. +// +//***************************************************************************** +#define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin +#define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin +#define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin +#define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin +#define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin +#define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin +#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin +#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin +#define SYSCTL_PIN_C0O 0x00000100 // C0o pin +#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin +#define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin +#define SYSCTL_PIN_C1O 0x00000800 // C1o pin +#define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin +#define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin +#define SYSCTL_PIN_C2O 0x00004000 // C2o pin +#define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin +#define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin +#define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin +#define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin +#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin +#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin +#define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin +#define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin +#define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin +#define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin +#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlLDOSet() API as +// the ulVoltage value, or returned by the SysCtlLDOGet() API. +// +//***************************************************************************** +#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V +#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V +#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V +#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V +#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V +#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V +#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V +#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V +#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V +#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V +#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlLDOConfigSet() API. +// +//***************************************************************************** +#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset +#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlIntEnable(), +// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask +// by the SysCtlIntStatus() API. +// +//***************************************************************************** +#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt +#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt +#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int +#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int +#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt +#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt +#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlResetCauseClear() +// API or returned by the SysCtlResetCauseGet() API. +// +//***************************************************************************** +#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset +#define SYSCTL_CAUSE_SW 0x00000010 // Software reset +#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset +#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset +#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset +#define SYSCTL_CAUSE_EXT 0x00000001 // External reset + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlBrownOutConfigSet() +// API as the ulConfig parameter. +// +//***************************************************************************** +#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting +#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlPWMClockSet() API +// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet() +// API. +// +//***************************************************************************** +#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1 +#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2 +#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4 +#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8 +#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16 +#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32 +#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64 + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlClockSet() API as +// the ulConfig parameter. +// +//***************************************************************************** +#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1 +#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2 +#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3 +#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4 +#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5 +#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6 +#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7 +#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8 +#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9 +#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10 +#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11 +#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12 +#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13 +#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14 +#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15 +#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16 +#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock +#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock +#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz +#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz +#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz +#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz +#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz +#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz +#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz +#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz +#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz +#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz +#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz +#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz +#define SYSCTL_OSC_MAIN 0x00000000 // Oscillator source is main osc +#define SYSCTL_OSC_INT 0x00000010 // Oscillator source is int. osc +#define SYSCTL_OSC_INT4 0x00000020 // Oscillator source is int. osc /4 +#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator +#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern unsigned long SysCtlSRAMSizeGet(void); +extern unsigned long SysCtlFlashSizeGet(void); +extern tBoolean SysCtlPinPresent(unsigned long ulPin); +extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral); +extern void SysCtlPeripheralReset(unsigned long ulPeripheral); +extern void SysCtlPeripheralEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralClockGating(tBoolean bEnable); +extern void SysCtlIntRegister(void (*pfnHandler)(void)); +extern void SysCtlIntUnregister(void); +extern void SysCtlIntEnable(unsigned long ulInts); +extern void SysCtlIntDisable(unsigned long ulInts); +extern void SysCtlIntClear(unsigned long ulInts); +extern unsigned long SysCtlIntStatus(tBoolean bMasked); +extern void SysCtlLDOSet(unsigned long ulVoltage); +extern unsigned long SysCtlLDOGet(void); +extern void SysCtlLDOConfigSet(unsigned long ulConfig); +extern void SysCtlReset(void); +extern void SysCtlSleep(void); +extern void SysCtlDeepSleep(void); +extern unsigned long SysCtlResetCauseGet(void); +extern void SysCtlResetCauseClear(unsigned long ulCauses); +extern void SysCtlBrownOutConfigSet(unsigned long ulConfig, + unsigned long ulDelay); +extern void SysCtlClockSet(unsigned long ulConfig); +extern unsigned long SysCtlClockGet(void); +extern void SysCtlPWMClockSet(unsigned long ulConfig); +extern unsigned long SysCtlPWMClockGet(void); +extern void SysCtlIOSCVerificationSet(tBoolean bEnable); +extern void SysCtlMOSCVerificationSet(tBoolean bEnable); +extern void SysCtlPLLVerificationSet(tBoolean bEnable); +extern void SysCtlClkVerificationClear(void); + +#ifdef __cplusplus +} +#endif + +#endif // __SYSCTL_H__ diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/systick.h b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/systick.h new file mode 100644 index 000000000..90560761e --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/systick.h @@ -0,0 +1,55 @@ +//***************************************************************************** +// +// systick.h - Prototypes for the SysTick driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __SYSTICK_H__ +#define __SYSTICK_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void SysTickEnable(void); +extern void SysTickDisable(void); +extern void SysTickIntRegister(void (*pfnHandler)(void)); +extern void SysTickIntUnregister(void); +extern void SysTickIntEnable(void); +extern void SysTickIntDisable(void); +extern void SysTickPeriodSet(unsigned long ulPeriod); +extern unsigned long SysTickPeriodGet(void); +extern unsigned long SysTickValueGet(void); + +#ifdef __cplusplus +} +#endif + +#endif // __SYSTICK_H__ diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/timer.h b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/timer.h new file mode 100644 index 000000000..e60418694 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/timer.h @@ -0,0 +1,137 @@ +//***************************************************************************** +// +// timer.h - Prototypes for the timer module +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __TIMER_H__ +#define __TIMER_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to TimerConfigure as the ulConfig parameter. +// +//***************************************************************************** +#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer +#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer +#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer +#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers +#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer +#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer +#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter +#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer +#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output +#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer +#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer +#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter +#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer +#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output + +//***************************************************************************** +// +// Values that can be passed to TimerIntEnable, TimerIntDisable, and +// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus. +// +//***************************************************************************** +#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt +#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt +#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt +#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask +#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt +#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt +#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt + +//***************************************************************************** +// +// Values that can be passed to TimerControlEvent as the ulEvent parameter. +// +//***************************************************************************** +#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges +#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges +#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges + +//***************************************************************************** +// +// Values that can be passed to most of the timer APIs as the ulTimer +// parameter. +// +//***************************************************************************** +#define TIMER_A 0x000000ff // Timer A +#define TIMER_B 0x0000ff00 // Timer B +#define TIMER_BOTH 0x0000ffff // Timer Both + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer); +extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer); +extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig); +extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, + tBoolean bInvert); +extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer, + tBoolean bEnable); +extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulEvent); +extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer, + tBoolean bStall); +extern void TimerRTCEnable(unsigned long ulBase); +extern void TimerRTCDisable(unsigned long ulBase); +extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerPrescaleGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer); +extern unsigned long TimerValueGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerMatchGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, + void (*pfnHandler)(void)); +extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer); +extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void TimerQuiesce(unsigned long ulBase); + +#ifdef __cplusplus +} +#endif + +#endif // __TIMER_H__ diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/uart.h b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/uart.h new file mode 100644 index 000000000..6047d3a32 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/uart.h @@ -0,0 +1,104 @@ +//***************************************************************************** +// +// uart.h - Defines and Macros for the UART. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __UART_H__ +#define __UART_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear +// as the ulIntFlags parameter, and returned from UARTIntStatus. +// +//***************************************************************************** +#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask +#define UART_INT_BE 0x200 // Break Error Interrupt Mask +#define UART_INT_PE 0x100 // Parity Error Interrupt Mask +#define UART_INT_FE 0x080 // Framing Error Interrupt Mask +#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask +#define UART_INT_TX 0x020 // Transmit Interrupt Mask +#define UART_INT_RX 0x010 // Receive Interrupt Mask + +//***************************************************************************** +// +// Values that can be passed to UARTConfigSet as the ulConfig parameter and +// returned by UARTConfigGet in the pulConfig parameter. Additionally, the +// UART_CONFIG_PAR_* subset can be passed to UARTParityModeSet as the ulParity +// parameter, and are returned by UARTParityModeGet. +// +//***************************************************************************** +#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data +#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data +#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data +#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data +#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit +#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits +#define UART_CONFIG_PAR_NONE 0x00000000 // No parity +#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity +#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity +#define UART_CONFIG_PAR_ONE 0x00000086 // Parity bit is one +#define UART_CONFIG_PAR_ZERO 0x00000082 // Parity bit is zero + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity); +extern unsigned long UARTParityModeGet(unsigned long ulBase); +extern void UARTConfigSet(unsigned long ulBase, unsigned long ulBaud, + unsigned long ulConfig); +extern void UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud, + unsigned long *pulConfig); +extern void UARTEnable(unsigned long ulBase); +extern void UARTDisable(unsigned long ulBase); +extern tBoolean UARTCharsAvail(unsigned long ulBase); +extern tBoolean UARTSpaceAvail(unsigned long ulBase); +extern long UARTCharNonBlockingGet(unsigned long ulBase); +extern long UARTCharGet(unsigned long ulBase); +extern tBoolean UARTCharNonBlockingPut(unsigned long ulBase, + unsigned char ucData); +extern void UARTCharPut(unsigned long ulBase, unsigned char ucData); +extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState); +extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern void UARTIntUnregister(unsigned long ulBase); +extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk, + unsigned long ulBaud, unsigned long ulConfig); + +#ifdef __cplusplus +} +#endif + +#endif // __UART_H__ diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/watchdog.h b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/watchdog.h new file mode 100644 index 000000000..4d6dcd21b --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/hw_include/watchdog.h @@ -0,0 +1,63 @@ +//***************************************************************************** +// +// watchdog.h - Prototypes for the Watchdog Timer API +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 635 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __WATCHDOG_H__ +#define __WATCHDOG_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern tBoolean WatchdogRunning(unsigned long ulBase); +extern void WatchdogEnable(unsigned long ulBase); +extern void WatchdogResetEnable(unsigned long ulBase); +extern void WatchdogResetDisable(unsigned long ulBase); +extern void WatchdogLock(unsigned long ulBase); +extern void WatchdogUnlock(unsigned long ulBase); +extern tBoolean WatchdogLockState(unsigned long ulBase); +extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal); +extern unsigned long WatchdogReloadGet(unsigned long ulBase); +extern unsigned long WatchdogValueGet(unsigned long ulBase); +extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern void WatchdogIntUnregister(unsigned long ulBase); +extern void WatchdogIntEnable(unsigned long ulBase); +extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void WatchdogIntClear(unsigned long ulBase); +extern void WatchdogStallDisable(unsigned long ulBase); +extern void WatchdogStallDisable(unsigned long ulBase); + +#ifdef __cplusplus +} +#endif + +#endif // __WATCHDOG_H__ diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/main.c b/20080212/Demo/CORTEX_LM3S316_IAR/main.c new file mode 100644 index 000000000..aa958f8c3 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/main.c @@ -0,0 +1,454 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + * This demo application creates eight co-routines and four tasks (five + * including the idle task). The co-routines execute as part of the idle task + * hook. The application is limited in size to allow its compilation using + * the KickStart version of the IAR compiler. + * + * Six of the created co-routines are the standard 'co-routine flash' + * co-routines contained within the Demo/Common/Minimal/crflash.c file and + * documented on the FreeRTOS.org WEB site. + * + * The 'LCD Task' waits on a message queue for messages informing it what and + * where to display text. This is the only task that accesses the LCD + * so mutual exclusion is guaranteed. + * + * The 'LCD Message Task' periodically sends strings to the LCD Task using + * the message queue. The strings are rotated to form a short message and + * are written to the top row of the LCD. + * + * The 'ADC Co-routine' periodically reads the ADC input that is connected to + * the light sensor, forms a short message from the value, and then sends this + * message to the LCD Task using the same message queue. The ADC readings are + * displayed on the bottom row of the LCD. + * + * The eighth co-routine and final task control the transmission and reception + * of a string to UART 0. The co-routine periodically sends the first + * character of the string to the UART, with the UART's TxEnd interrupt being + * used to transmit the remaining characters. The UART's RxEnd interrupt + * receives the characters and places them on a queue to be processed by the + * 'COMs Rx' task. An error is latched should an unexpected character be + * received, or any character be received out of sequence. + * + * A loopback connector is required to ensure that each character transmitted + * on the UART is also received on the same UART. For test purposes the UART + * FIFO's are not utalised in order to maximise the interrupt overhead. Also + * a pseudo random interval is used between the start of each transmission in + * order that the resultant interrupts are more randomly distributed and + * therefore more likely to highlight any problems. + * + * The flash co-routines control LED's zero to four. LED five is toggled each + * time the string is transmitted on the UART. LED six is toggled each time + * the string is CORRECTLY received on the UART. LED seven is latched on + * should an error be detected in any task or co-routine. + * + * In addition the idle task makes repetitive calls to + * vSetAndCheckRegisters(). This simply loads the general purpose registers + * with a known value, then checks each register to ensure the held value is + * still correct. As a low priority task this checking routine is likely to + * get repeatedly swapped in and out. A register being found to contain an + * incorrect value is therefore indicative of an error in the task switching + * mechanism. + * + */ + +/* standard include files. */ +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "croutine.h" + +/* Demo application include files. */ +#include "partest.h" +#include "crflash.h" +#include "commstest.h" + +/* Library include files. */ +#include "DriverLib.h" + +/* The time to delay between writing each character to the LCD. */ +#define mainCHAR_WRITE_DELAY ( 2 / portTICK_RATE_MS ) + +/* The time to delay between writing each string to the LCD. */ +#define mainSTRING_WRITE_DELAY ( 400 / portTICK_RATE_MS ) + +#define mainADC_DELAY ( 200 / portTICK_RATE_MS ) + +/* The number of flash co-routines to create. */ +#define mainNUM_FLASH_CO_ROUTINES ( 5 ) + +/* The length of the queue used to send messages to the LCD task. */ +#define mainLCD_QUEUE_LEN ( 3 ) + +/* The priority of the co-routine used to initiate the transmission of the +string on UART 0. */ +#define mainTX_CO_ROUTINE_PRIORITY ( 1 ) +#define mainADC_CO_ROUTINE_PRIORITY ( 2 ) + +/* Only one of each co-routine is created so its index is not important. */ +#define mainTX_CO_ROUTINE_INDEX ( 0 ) +#define mainADC_CO_ROUTINE_INDEX ( 0 ) + +/* The task priorities. */ +#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainMSG_TASK_PRIORITY ( mainLCD_TASK_PRIORITY - 1 ) +#define mainCOMMS_RX_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The LCD had two rows. */ +#define mainTOP_ROW 0 +#define mainBOTTOM_ROW 1 + +/* Dimension for the buffer into which the ADC value string is written. */ +#define mainMAX_ADC_STRING_LEN 20 + +/* The LED that is lit should an error be detected in any of the tasks or +co-routines. */ +#define mainFAIL_LED ( 7 ) + +/*-----------------------------------------------------------*/ + +/* + * The task that displays text on the LCD. + */ +static void prvLCDTask( void * pvParameters ); + +/* + * The task that sends messages to be displayed on the top row of the LCD. + */ +static void prvLCDMessageTask( void * pvParameters ); + +/* + * The co-routine that reads the ADC and sends messages for display on the + * bottom row of the LCD. + */ +static void prvADCCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + +/* + * Function to simply set a known value into the general purpose registers + * then read them back to ensure they remain set correctly. An incorrect value + * being indicative of an error in the task switching mechanism. + */ +extern void vSetAndCheckRegisters( void ); + +/* + * Latch the LED that indicates that an error has occurred. + */ +void vSetErrorLED( void ); + +/* + * Thread safe write to the PDC. + */ +static void prvPDCWrite( portCHAR cAddress, portCHAR cData ); + +/* + * Sets up the hardware used by the demo. + */ +static void prvSetupHardware( void ); + + +/*-----------------------------------------------------------*/ + +/* The structure that is passed on the LCD message queue. */ +typedef struct +{ + portCHAR **ppcMessageToDisplay; /*<< Points to a char* pointing to the message to display. */ + portBASE_TYPE xRow; /*<< The row on which the message should be displayed. */ +} xLCDMessage; + +/* Error flag set to pdFAIL if an error is encountered in the tasks/co-routines +defined within this file. */ +unsigned portBASE_TYPE uxErrorStatus = pdPASS; + +/* The queue used to transmit messages to the LCD task. */ +static xQueueHandle xLCDQueue; + +/*-----------------------------------------------------------*/ + +/* + * Setup the hardware, create the tasks/co-routines, then start the scheduler. + */ +void main( void ) +{ + /* Create the queue used by tasks wanting to write to the LCD. */ + xLCDQueue = xQueueCreate( mainLCD_QUEUE_LEN, sizeof( xLCDMessage ) ); + + /* Setup the ports used by the demo and the clock. */ + prvSetupHardware(); + + /* Create the co-routines that flash the LED's. */ + vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES ); + + /* Create the co-routine that initiates the transmission of characters + on the UART and the task that receives them, as described at the top of + this file. */ + xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX ); + xTaskCreate( vCommsRxTask, "CMS", configMINIMAL_STACK_SIZE, NULL, mainCOMMS_RX_TASK_PRIORITY, NULL ); + + /* Create the task that waits for messages to display on the LCD, plus the + task and co-routine that send messages for display (as described at the top + of this file. */ + xTaskCreate( prvLCDTask, "LCD", configMINIMAL_STACK_SIZE, ( void * ) &xLCDQueue, mainLCD_TASK_PRIORITY, NULL ); + xTaskCreate( prvLCDMessageTask, "MSG", configMINIMAL_STACK_SIZE, ( void * ) &xLCDQueue, mainMSG_TASK_PRIORITY, NULL ); + xCoRoutineCreate( prvADCCoRoutine, mainADC_CO_ROUTINE_PRIORITY, mainADC_CO_ROUTINE_INDEX ); + + /* Start the scheduler running the tasks and co-routines just created. */ + vTaskStartScheduler(); + + /* Should not get here unless we did not have enough memory to start the + scheduler. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvLCDMessageTask( void * pvParameters ) +{ +/* The strings that are written to the LCD. */ +portCHAR *pcStringsToDisplay[] = { + "IAR ", + "Stellaris ", + "Demo ", + "www.FreeRTOS.org", + "" + }; + +xQueueHandle *pxLCDQueue; +xLCDMessage xMessageToSend; +portBASE_TYPE xIndex = 0; + + /* To test the parameter passing mechanism, the queue on which messages are + posted is passed in as a parameter even though it is available as a file + scope variable anyway. */ + pxLCDQueue = ( xQueueHandle * ) pvParameters; + + for( ;; ) + { + /* Wait until it is time to move onto the next string. */ + vTaskDelay( mainSTRING_WRITE_DELAY ); + + /* Create the message object to send to the LCD task. */ + xMessageToSend.ppcMessageToDisplay = &pcStringsToDisplay[ xIndex ]; + xMessageToSend.xRow = mainTOP_ROW; + + /* Post the message to be displayed. */ + if( !xQueueSend( *pxLCDQueue, ( void * ) &xMessageToSend, 0 ) ) + { + uxErrorStatus = pdFAIL; + } + + /* Move onto the next message, wrapping when necessary. */ + xIndex++; + if( *( pcStringsToDisplay[ xIndex ] ) == 0x00 ) + { + xIndex = 0; + + /* Delay longer before going back to the start of the messages. */ + vTaskDelay( mainSTRING_WRITE_DELAY * 2 ); + } + } +} +/*-----------------------------------------------------------*/ + +void prvLCDTask( void * pvParameters ) +{ +unsigned portBASE_TYPE uxIndex; +xQueueHandle *pxLCDQueue; +xLCDMessage xReceivedMessage; +portCHAR *pcString; +const unsigned portCHAR ucCFGData[] = { + 0x30, /* Set data bus to 8-bits. */ + 0x30, + 0x30, + 0x3C, /* Number of lines/font. */ + 0x08, /* Display off. */ + 0x01, /* Display clear. */ + 0x06, /* Entry mode [cursor dir][shift]. */ + 0x0C /* Display on [display on][curson on][blinking on]. */ + }; + + /* To test the parameter passing mechanism, the queue on which messages are + received is passed in as a parameter even though it is available as a file + scope variable anyway. */ + pxLCDQueue = ( xQueueHandle * ) pvParameters; + + /* Configure the LCD. */ + uxIndex = 0; + while( uxIndex < sizeof( ucCFGData ) ) + { + prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] ); + uxIndex++; + vTaskDelay( mainCHAR_WRITE_DELAY ); + } + + /* Turn the LCD Backlight on. */ + prvPDCWrite( PDC_CSR, 0x01 ); + + /* Clear display. */ + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR ); + + uxIndex = 0; + for( ;; ) + { + /* Wait for a message to arrive. */ + if( xQueueReceive( *pxLCDQueue, &xReceivedMessage, portMAX_DELAY ) ) + { + /* Which row does the received message say to write to? */ + PDCLCDSetPos( 0, xReceivedMessage.xRow ); + + /* Where is the string we are going to display? */ + pcString = *xReceivedMessage.ppcMessageToDisplay; + + while( *pcString ) + { + /* Don't write out the string too quickly as LCD's are usually + pretty slow devices. */ + vTaskDelay( mainCHAR_WRITE_DELAY ); + prvPDCWrite( PDC_LCD_RAM, *pcString ); + pcString++; + } + } + } +} +/*-----------------------------------------------------------*/ + +static void prvADCCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +static unsigned portLONG ulADCValue; +static portCHAR cMessageBuffer[ mainMAX_ADC_STRING_LEN ]; +static portCHAR *pcMessage; +static xLCDMessage xMessageToSend; + + /* Co-routines MUST start with a call to crSTART(). */ + crSTART( xHandle ); + + for( ;; ) + { + /* Start an ADC conversion. */ + ADCProcessorTrigger( ADC_BASE, 0 ); + + /* Simply delay - when we unblock the result should be available */ + crDELAY( xHandle, mainADC_DELAY ); + + /* Get the ADC result. */ + ADCSequenceDataGet( ADC_BASE, 0, &ulADCValue ); + + /* Create a string with the result. */ + sprintf( cMessageBuffer, "ADC = %d ", ulADCValue ); + pcMessage = cMessageBuffer; + + /* Configure the message we are going to send for display. */ + xMessageToSend.ppcMessageToDisplay = ( portCHAR** ) &pcMessage; + xMessageToSend.xRow = mainBOTTOM_ROW; + + /* Send the string to the LCD task for display. We are sending + on a task queue so do not have the option to block. */ + if( !xQueueSend( xLCDQueue, ( void * ) &xMessageToSend, 0 ) ) + { + uxErrorStatus = pdFAIL; + } + } + + /* Co-routines MUST end with a call to crEND(). */ + crEND(); +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Setup the PLL. */ + SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); + + /* Initialise the hardware used to talk to the LCD, LED's and UART. */ + PDCInit(); + vParTestInitialise(); + vSerialInit(); + + /* The ADC is used to read the light sensor. */ + SysCtlPeripheralEnable( SYSCTL_PERIPH_ADC ); + ADCSequenceConfigure( ADC_BASE, 3, ADC_TRIGGER_PROCESSOR, 0); + ADCSequenceStepConfigure( ADC_BASE, 0, 0, ADC_CTL_CH0 | ADC_CTL_END ); + ADCSequenceEnable( ADC_BASE, 0 ); + +} +/*-----------------------------------------------------------*/ + +static void prvPDCWrite( portCHAR cAddress, portCHAR cData ) +{ + vTaskSuspendAll(); + { + PDCWrite( cAddress, cData ); + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vSetErrorLED( void ) +{ + vParTestSetLED( mainFAIL_LED, pdTRUE ); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ + /* The co-routines are executed in the idle task using the idle task + hook. */ + for( ;; ) + { + /* Schedule the co-routines. */ + vCoRoutineSchedule(); + + /* Run the register check function between each co-routine. */ + vSetAndCheckRegisters(); + + /* See if the comms task and co-routine has found any errors. */ + if( uxGetCommsStatus() != pdPASS ) + { + vParTestSetLED( mainFAIL_LED, pdTRUE ); + } + } +} +/*-----------------------------------------------------------*/ diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/registertest.s b/20080212/Demo/CORTEX_LM3S316_IAR/registertest.s new file mode 100644 index 000000000..7f27b5f48 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/registertest.s @@ -0,0 +1,60 @@ + RSEG ICODE:CODE + + EXTERN vSetErrorLED + + PUBLIC vSetAndCheckRegisters + +vSetAndCheckRegisters: + /* Fill the general purpose registers with known values. */ + mov r11, #10 + add r0, r11, #1 + add r1, r11, #2 + add r2, r11, #3 + add r3, r11, #4 + add r4, r11, #5 + add r5, r11, #6 + add r6, r11, #7 + add r7, r11, #8 + add r8, r11, #9 + add r9, r11, #10 + add r10, r11, #11 + add r12, r11, #12 + + /* Check the values are as expected. */ + cmp r11, #10 + bne set_error_led + cmp r0, #11 + bne set_error_led + cmp r1, #12 + bne set_error_led + cmp r2, #13 + bne set_error_led + cmp r3, #14 + bne set_error_led + cmp r4, #15 + bne set_error_led + cmp r5, #16 + bne set_error_led + cmp r6, #17 + bne set_error_led + cmp r7, #18 + bne set_error_led + cmp r8, #19 + bne set_error_led + cmp r9, #20 + bne set_error_led + cmp r10, #21 + bne set_error_led + cmp r12, #22 + bne set_error_led + bx lr + +set_error_led: + push {r14} + ldr r1, =vSetErrorLED + blx r1 + pop {r14} + bx lr + + END + diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/settings/RTOSDemo.dbgdt b/20080212/Demo/CORTEX_LM3S316_IAR/settings/RTOSDemo.dbgdt new file mode 100644 index 000000000..408229b41 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/settings/RTOSDemo.dbgdt @@ -0,0 +1,65 @@ + + + + + + 300 + + + + + + + 274272727 + + + + + + + + 200 + + + + 010 + + 20 + 1004 + 267 + 66 + 300Debug-LogBreakpoints + 20011210310010020020014010010010030010300Debug-LogBuild1001001 + + + + + + + TabID-30594-29847 + Workspace + Workspace + + + RTOSDemoRTOSDemo/Demo Source + + + + 0TabID-30273-20034Debug LogDebug-Log0 + + + + + + TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\main.c0189797279720TextEditorC:\E\Dev\FreeRTOS\Source\portable\IAR\ARM_CM3\port.c015359365936TextEditorC:\Devtools\IAR Systems\Embedded Workbench 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0 +LogFile=_ "" +Category=_ 0 +[TermIOLog] +LoggingEnabled=_ 0 +LogFile=_ "" +[Disassemble mode] +mode=1 +[Breakpoints] +Count=0 +[TraceHelper] +Enabled=0 +ShowSource=1 diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/settings/RTOSDemo.wsdt b/20080212/Demo/CORTEX_LM3S316_IAR/settings/RTOSDemo.wsdt new file mode 100644 index 000000000..f13f32b5b --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/settings/RTOSDemo.wsdt @@ -0,0 +1,58 @@ + + + + + + RTOSDemo/Debug + + + + + + + + + 186272727 + + + + + + + 30020100426766 + + + 48268826 + + + + + + + TabID-2928-28933 + Workspace + Workspace + + + RTOSDemoRTOSDemo/Libraries + + + + 0TabID-24894-24921BuildBuildTabID-10790-31422Debug LogDebug-LogTabID-27705-5723Find in FilesFind-in-Files0 + + + + + + TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\main.c01897972797200100000010000001 + + + + + + + iaridepm.enu1-2-2738260-2-2200202142857205703187143753564-2-22001402-2-214042021002857205703142857205703 + + + + diff --git a/20080212/Demo/CORTEX_LM3S316_IAR/settings/driverlib.wsdt b/20080212/Demo/CORTEX_LM3S316_IAR/settings/driverlib.wsdt new file mode 100644 index 000000000..6deb801e8 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S316_IAR/settings/driverlib.wsdt @@ -0,0 +1,51 @@ + + + + + + + + qs_dk-lm3s316/Debug + + + + + + + + + 253272727 + + 20100426766 + + + + + + TabID-9985-21059 + Workspace + Workspace + + + + + + + 0TabID-31963-22489BuildBuildTabID-12860-23630Debug LogDebug-Log0 + + + + + + TextEditorC:\Devtools\IAR Systems\Embedded Workbench 4.0\ARM\examples\Luminary\DK-LM3Sxxx\utils\cspy.c04200TextEditorC:\Devtools\IAR Systems\Embedded Workbench 4.0\ARM\examples\Luminary\DK-LM3Sxxx\examples\qs_dk-lm3s102\startup.c03900TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\examples\qs_dk-lm3s101\qs_dk-lm3s101.c02841017910179TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\utils\pdc.c0615401540TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\src\watchdog.c0014731480TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\src\uart.c0015141514TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\src\timer.c0015241524TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\src\systick.c0015131513TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\src\sysctl.c0015531553TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\src\ssi.c0015301530TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\src\pwm.c0015131513TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\src\interrupt.c0015211521TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\src\i2c.c0015261526TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\src\gpio.c0015111511TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\src\flash.c0015601560TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\src\comp.c0015261526TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\src\adc.c0015091509TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\examples\qs_dk-lm3s316\qs_dk-lm3s316.c05721292312923TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\utils\cspy.c03900180100000010000001 + + + + + + + iaridepm1-2-2728327-2-2200200142857205761235000751029-2-21981402-2-214042001002857205761142857205761 + + + + diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/FreeRTOSConfig.h b/20080212/Demo/CORTEX_LM3S811_GCC/FreeRTOSConfig.h new file mode 100644 index 000000000..0f8d5601d --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/FreeRTOSConfig.h @@ -0,0 +1,86 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 70 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 7000 ) ) +#define configMAX_TASK_NAME_LEN ( 10 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_CO_ROUTINES 0 + +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + +#define configKERNEL_INTERRUPT_PRIORITY 255 + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/Makefile b/20080212/Demo/CORTEX_LM3S811_GCC/Makefile new file mode 100644 index 000000000..814cc6f7e --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/Makefile @@ -0,0 +1,85 @@ +#****************************************************************************** +# +# Makefile - Rules for building the driver library and examples. +# +# Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +# +# Software License Agreement +# +# Luminary Micro, Inc. (LMI) is supplying this software for use solely and +# exclusively on LMI's Stellaris Family of microcontroller products. +# +# The software is owned by LMI and/or its suppliers, and is protected under +# applicable copyright laws. All rights are reserved. Any use in violation +# of the foregoing restrictions may subject the user to criminal sanctions +# under applicable laws, as well as to civil liability for the breach of the +# terms and conditions of this license. +# +# THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +# OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +# LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +# CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +# +#****************************************************************************** + +include makedefs + +RTOS_SOURCE_DIR=../../Source +DEMO_SOURCE_DIR=../Common/Minimal + +CFLAGS+=-I hw_include -I . -I ${RTOS_SOURCE_DIR}/include -I ${RTOS_SOURCE_DIR}/portable/GCC/ARM_CM3 -I ../Common/include -D GCC_ARMCM3_LM3S102 -D inline= + +VPATH=${RTOS_SOURCE_DIR}:${RTOS_SOURCE_DIR}/portable/MemMang:${RTOS_SOURCE_DIR}/portable/GCC/ARM_CM3:${DEMO_SOURCE_DIR}:init:hw_include + +OBJS=${COMPILER}/main.o \ + ${COMPILER}/list.o \ + ${COMPILER}/queue.o \ + ${COMPILER}/tasks.o \ + ${COMPILER}/port.o \ + ${COMPILER}/heap_1.o \ + ${COMPILER}/BlockQ.o \ + ${COMPILER}/PollQ.o \ + ${COMPILER}/integer.o \ + ${COMPILER}/semtest.o \ + ${COMPILER}/osram96x16.o + +INIT_OBJS= ${COMPILER}/startup.o + +LIBS= hw_include/libdriver.a + + +# +# The default rule, which causes init to be built. +# +all: ${COMPILER} \ + ${COMPILER}/RTOSDemo.axf \ + +# +# The rule to clean out all the build products +# + +clean: + @rm -rf ${COMPILER} ${wildcard *.bin} RTOSDemo.axf + +# +# The rule to create the target directory +# +${COMPILER}: + @mkdir ${COMPILER} + +${COMPILER}/RTOSDemo.axf: ${INIT_OBJS} ${OBJS} ${LIBS} +SCATTER_RTOSDemo=standalone.ld +ENTRY_RTOSDemo=ResetISR + +# +# +# Include the automatically generated dependency files. +# +-include ${wildcard ${COMPILER}/*.d} __dummy__ + + + + + + diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/DriverLib.h b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/DriverLib.h new file mode 100644 index 000000000..47531fbe9 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/DriverLib.h @@ -0,0 +1,39 @@ +#ifndef DRIVER_LIB_H +#define DRIVER_LIB_H + +#include "DriverLib.h" +#include "hw_adc.h" +#include "hw_comp.h" +#include "hw_flash.h" +#include "hw_gpio.h" +#include "hw_i2c.h" +#include "hw_ints.h" +#include "hw_memmap.h" +#include "hw_nvic.h" +#include "hw_pwm.h" +#include "hw_qei.h" +#include "hw_ssi.h" +#include "hw_sysctl.h" +#include "hw_timer.h" +#include "hw_types.h" +#include "hw_uart.h" +#include "hw_watchdog.h" +#include "osram96x16.h" +#include "adc.h" +#include "comp.h" +#include "cpu.h" +#include "debug.h" +#include "flash.h" +#include "gpio.h" +#include "i2c.h" +#include "interrupt.h" +#include "pwm.h" +#include "qei.h" +#include "ssi.h" +#include "sysctl.h" +#include "systick.h" +#include "timer.h" +#include "uart.h" +#include "watchdog.h" + +#endif diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/EULA.txt b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/EULA.txt new file mode 100644 index 000000000..02c57b2f9 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/EULA.txt @@ -0,0 +1,126 @@ +IMPORTANT. Read the following LMI Software License Agreement ("Agreement") +completely. + +LUMINARY MICRO SOFTWARE LICENSE AGREEMENT + + This is a legal agreement between you (either as an individual or as an +authorized representative of your employer) and Luminary Micro, Inc. ("LMI"). +It concerns your rights to use this file and any accompanying written materials +(the "Software"). In consideration for LMI allowing you to access the +Software, you are agreeing to be bound by the terms of this Agreement. If you +do not agree to all of the terms of this Agreement, do not download or use the +Software. If you change your mind later, stop using the Software and delete +all copies of the Software in your possession or control. Any copies of the +Software that you have already distributed, where permitted, and do not destroy +will continue to be governed by this Agreement. Your prior use will also +continue to be governed by this Agreement. + +1. LICENSE GRANT. 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Use, duplication or +disclosure by the Government is subject to restrictions as set forth in +subparagraph (c)(1)(ii) of The Rights in Technical Data and Computer Software +clause at DFARS 252.227-7013 or subparagraphs (c)(l) and (2) of the Commercial +Computer Software--Restricted Rights at 48 CFR 52.227-19, as applicable. +Manufacturer is Luminary Micro, Inc., 2499 S. Capital of Texas Hwy Ste A-100, +Austin, Texas 78746. + +9. DISCLAIMER OF WARRANTY. TO THE MAXIMUM EXTENT PERMITTED BY LAW, LMI +EXPRESSLY DISCLAIMS ANY WARRANTY FOR THE SOFTWARE. THE SOFTWARE IS PROVIDED +"AS IS", WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING, +WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A +PARTICULAR PURPOSE, OR NON-INFRINGEMENT. YOU ASSUME THE ENTIRE RISK ARISING +OUT OF THE USE OR PERFORMANCE OF THE SOFTWARE, OR ANY SYSTEMS YOU DESIGN USING +THE SOFTWARE (IF ANY). NOTHING IN THIS AGREEMENT MAY BE CONSTRUED AS A +WARRANTY OR REPRESENTATION BY LMI THAT THE SOFTWARE OR ANY DERIVATIVE WORK +DEVELOPED WITH OR INCORPORATING THE SOFTWARE WILL BE FREE FROM INFRINGEMENT OF +THE INTELLECTUAL PROPERTY RIGHTS OF THIRD PARTIES. + +10. LIMITATION OF LIABILITY. IN NO EVENT WILL LMI BE LIABLE, WHETHER IN +CONTRACT, TORT, OR OTHERWISE, FOR ANY INCIDENTAL, SPECIAL, INDIRECT, +CONSEQUENTIAL OR PUNITIVE DAMAGES, INCLUDING, BUT NOT LIMITED TO, DAMAGES FOR +ANY LOSS OF USE, LOSS OF TIME, INCONVENIENCE, COMMERCIAL LOSS, OR LOST PROFITS, +SAVINGS, OR REVENUES TO THE FULL EXTENT SUCH MAY BE DISCLAIMED BY LAW. + +11. CHOICE OF LAW; VENUE; LIMITATIONS. You agree that the statutes and +laws of the United States and the State of Texas, USA, without regard to +conflicts of laws principles, will apply to all matters relating to this +Agreement or the Software, and you agree that any litigation will be subject to +the exclusive jurisdiction of the state or federal courts in Austin, Travis +County, Texas, USA. You agree that regardless of any statute or law to the +contrary, any claim or cause of action arising out of or related to this +Agreement or the Software must be filed within one (1) year after such claim or +cause of action arose or be forever barred. + +12. ENTIRE AGREEMENT. This Agreement constitutes the entire agreement +between you and LMI regarding the subject matter of this Agreement, and +supersedes all prior communications, negotiations, understandings, agreements +or representations, either written or oral, if any. This Agreement may only be +amended in written form, executed by you and LMI. + +13. SEVERABILITY. If any provision of this Agreement is held for any +reason to be invalid or unenforceable, then the remaining provisions of this +Agreement will be unimpaired and, unless a modification or replacement of the +invalid or unenforceable provision is further held to deprive you or LMI of a +material benefit, in which case the Agreement will immediately terminate, the +invalid or unenforceable provision will be replaced with a provision that is +valid and enforceable and that comes closest to the intention underlying the +invalid or unenforceable provision. + +14. NO WAIVER. The waiver by LMI of any breach of any provision of this +Agreement will not operate or be construed as a waiver of any other or a +subsequent breach of the same or a different provision. diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/adc.c b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/adc.c new file mode 100644 index 000000000..53f3adf5b --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/adc.c @@ -0,0 +1,946 @@ +//***************************************************************************** +// +// adc.c - Driver for the ADC. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup adc_api +//! @{ +// +//***************************************************************************** + +#include "../hw_adc.h" +#include "../hw_ints.h" +#include "../hw_memmap.h" +#include "../hw_types.h" +#include "adc.h" +#include "debug.h" +#include "interrupt.h" + +//***************************************************************************** +// +// The currently configured software oversampling factor for each of the ADC +// sequencers. +// +//***************************************************************************** +#if defined(GROUP_pucoverssamplefactor) || defined(BUILD_ALL) +unsigned char g_pucOversampleFactor[3]; +#else +extern unsigned char g_pucOversampleFactor[3]; +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for an ADC interrupt. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! \param pfnHandler is a pointer to the function to be called when the +//! ADC sample sequence interrupt occurs. +//! +//! This function sets the handler to be called when a sample sequence +//! interrupt occurs. This will enable the global interrupt in the interrupt +//! controller; the sequence interrupt must be enabled with ADCIntEnable(). It +//! is the interrupt handler's responsibility to clear the interrupt source via +//! ADCIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum, + void (*pfnHandler)(void)) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + + // + // Determine the interrupt to register based on the sequence number. + // + ulInt = INT_ADC0 + ulSequenceNum; + + // + // Register the interrupt handler. + // + IntRegister(ulInt, pfnHandler); + + // + // Enable the timer interrupt. + // + IntEnable(ulInt); +} +#endif + +//***************************************************************************** +// +//! Unregisters the interrupt handler for an ADC interrupt. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! This function unregisters the interrupt handler. This will disable the +//! global interrupt in the interrupt controller; the sequence interrupt must +//! be disabled via ADCIntDisable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ADCIntUnregister(unsigned long ulBase, unsigned long ulSequenceNum) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + + // + // Determine the interrupt to unregister based on the sequence number. + // + ulInt = INT_ADC0 + ulSequenceNum; + + // + // Disable the interrupt. + // + IntDisable(ulInt); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulInt); +} +#endif + +//***************************************************************************** +// +//! Disables a sample sequence interrupt. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! This function disables the requested sample sequence interrupt. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + + // + // Disable this sample sequence interrupt. + // + HWREG(ulBase + ADC_O_IM) &= ~(1 << ulSequenceNum); +} +#endif + +//***************************************************************************** +// +//! Enables a sample sequence interrupt. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! This function enables the requested sample sequence interrupt. Any +//! outstanding interrupts are cleared before enabling the sample sequence +//! interrupt. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + + // + // Clear any outstanding interrupts on this sample sequence. + // + HWREG(ulBase + ADC_O_ISC) = 1 << ulSequenceNum; + + // + // Enable this sample sequence interrupt. + // + HWREG(ulBase + ADC_O_IM) |= 1 << ulSequenceNum; +} +#endif + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! \param bMasked is false if the raw interrupt status is required and true if +//! the masked interrupt status is required. +//! +//! This returns the interrupt status for the specified sample sequence. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. +//! +//! \return The current raw or masked interrupt status. +// +//***************************************************************************** +#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +ADCIntStatus(unsigned long ulBase, unsigned long ulSequenceNum, + tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ulBase + ADC_O_ISC) & (1 << ulSequenceNum)); + } + else + { + return(HWREG(ulBase + ADC_O_RIS) & (1 << ulSequenceNum)); + } +} +#endif + +//***************************************************************************** +// +//! Clears sample sequence interrupt source. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! The specified sample sequence interrupt is cleared, so that it no longer +//! asserts. This must be done in the interrupt handler to keep it from being +//! called again immediately upon exit. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arugments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + + // + // Clear the interrupt. + // + HWREG(ulBase + ADC_O_ISC) = 1 << ulSequenceNum; +} +#endif + +//***************************************************************************** +// +//! Enables a sample sequence. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! Allows the specified sample sequence to be captured when its trigger is +//! detected. A sample sequence must be configured before it is enabled. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_sequenceenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ADCSequenceEnable(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arugments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + + // + // Enable the specified sequence. + // + HWREG(ulBase + ADC_O_ACTSS) |= 1 << ulSequenceNum; +} +#endif + +//***************************************************************************** +// +//! Disables a sample sequence. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! Prevents the specified sample sequence from being captured when its trigger +//! is detected. A sample sequence should be disabled before it is configured. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_sequencedisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ADCSequenceDisable(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arugments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + + // + // Disable the specified sequences. + // + HWREG(ulBase + ADC_O_ACTSS) &= ~(1 << ulSequenceNum); +} +#endif + +//***************************************************************************** +// +//! Configures the trigger source and priority of a sample sequence. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! \param ulTrigger is the trigger source that initiates the sample sequence; +//! must be one of the \b ADC_TRIGGER_* values. +//! \param ulPriority is the relative priority of the sample sequence with +//! respect to the other sample sequences. +//! +//! This function configures the initiation criteria for a sample sequence. +//! Valid sample sequences range from zero to three; sequence zero will capture +//! up to eight samples, sequences one and two will capture up to four samples, +//! and sequence three will capture a single sample. The trigger condition and +//! priority (with respect to other sample sequence execution) is set. +//! +//! The parameter \b ulTrigger can take on the following values: +//! +//! - \b ADC_TRIGGER_PROCESSOR - A trigger generated by the processor, via the +//! ADCProcessorTrigger() function. +//! - \b ADC_TRIGGER_COMP0 - A trigger generated by the first analog +//! comparator; configured with ComparatorConfigure(). +//! - \b ADC_TRIGGER_COMP1 - A trigger generated by the second analog +//! comparator; configured with ComparatorConfigure(). +//! - \b ADC_TRIGGER_COMP2 - A trigger generated by the third analog +//! comparator; configured with ComparatorConfigure(). +//! - \b ADC_TRIGGER_EXTERNAL - A trigger generated by an input from the Port +//! B4 pin. +//! - \b ADC_TRIGGER_TIMER - A trigger generated by a timer; configured with +//! TimerControlTrigger(). +//! - \b ADC_TRIGGER_PWM0 - A trigger generated by the first PWM generator; +//! configured with PWMGenIntTrigEnable(). +//! - \b ADC_TRIGGER_PWM1 - A trigger generated by the second PWM generator; +//! configured with PWMGenIntTrigEnable(). +//! - \b ADC_TRIGGER_PWM2 - A trigger generated by the third PWM generator; +//! configured with PWMGenIntTrigEnable(). +//! - \b ADC_TRIGGER_ALWAYS - A trigger that is always asserted, causing the +//! sample sequence to capture repeatedly (so long as +//! there is not a higher priority source active). +//! +//! Note that not all trigger sources are available on all Stellaris family +//! members; consult the data sheet for the device in question to determine the +//! availability of triggers. +//! +//! The parameter \b ulPriority is a value between 0 and 3, where 0 represents +//! the highest priority and 3 the lowest. Note that when programming the +//! priority among a set of sample sequences, each must have unique priority; +//! it is up to the caller to guarantee the uniqueness of the priorities. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_sequenceconfigure) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ADCSequenceConfigure(unsigned long ulBase, unsigned long ulSequenceNum, + unsigned long ulTrigger, unsigned long ulPriority) +{ + // + // Check the arugments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + ASSERT((ulTrigger == ADC_TRIGGER_PROCESSOR) || + (ulTrigger == ADC_TRIGGER_COMP0) || + (ulTrigger == ADC_TRIGGER_COMP1) || + (ulTrigger == ADC_TRIGGER_COMP2) || + (ulTrigger == ADC_TRIGGER_EXTERNAL) || + (ulTrigger == ADC_TRIGGER_TIMER) || + (ulTrigger == ADC_TRIGGER_PWM0) || + (ulTrigger == ADC_TRIGGER_PWM1) || + (ulTrigger == ADC_TRIGGER_PWM2) || + (ulTrigger == ADC_TRIGGER_ALWAYS)); + ASSERT(ulPriority < 4); + + // + // Compute the shift for the bits that control this sample sequence. + // + ulSequenceNum *= 4; + + // + // Set the trigger event for this sample sequence. + // + HWREG(ulBase + ADC_O_EMUX) = ((HWREG(ulBase + ADC_O_EMUX) & + ~(0xf << ulSequenceNum)) | + ((ulTrigger & 0xf) << ulSequenceNum)); + + // + // Set the priority for this sample sequence. + // + HWREG(ulBase + ADC_O_SSPRI) = ((HWREG(ulBase + ADC_O_SSPRI) & + ~(0xf << ulSequenceNum)) | + ((ulPriority & 0x3) << ulSequenceNum)); +} +#endif + +//***************************************************************************** +// +//! Configure a step of the sample sequencer. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! \param ulStep is the step to be configured. +//! \param ulConfig is the configuration of this step; must be a logical OR of +//! \b ADC_CTL_TS, \b ADC_CTL_IE, \b ADC_CTL_END, \b ADC_CTL_D, and one of the +//! input channel selects (\b ADC_CTL_CH0 through \b ADC_CTL_CH7). +//! +//! This function will set the configuration of the ADC for one step of a +//! sample sequence. The ADC can be configured for single-ended or +//! differential operation (the \b ADC_CTL_D bit selects differential +//! operation when set), the channel to be sampled can be chosen (the +//! \b ADC_CTL_CH0 through \b ADC_CTL_CH7 values), and the internal temperature +//! sensor can be selected (the \b ADC_CTL_TS bit). Additionally, this step +//! can be defined as the last in the sequence (the \b ADC_CTL_END bit) and it +//! can be configured to cause an interrupt when the step is complete (the +//! \b ADC_CTL_IE bit). The configuration is used by the ADC at the +//! appropriate time when the trigger for this sequence occurs. +//! +//! The \b ulStep parameter determines the order in which the samples are +//! captured by the ADC when the trigger occurs. It can range from zero to +//! seven for the first sample sequence, from zero to three for the second and +//! third sample sequence, and can only be zero for the fourth sample sequence. +//! +//! Differential mode only works with adjacent channel pairs (e.g. 0 and 1). +//! The channel select must be the number of the channel pair to sample (e.g. +//! \b ADC_CTL_CH0 for 0 and 1, or \b ADC_CTL_CH1 for 2 and 3) or undefined +//! results will be returned by the ADC. Additionally, if differential mode is +//! selected when the temperature sensor is being sampled, undefined results +//! will be returned by the ADC. +//! +//! It is the responsibility of the caller to ensure that a valid configuration +//! is specified; this function does not check the validity of the specified +//! configuration. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_sequencestepconfigure) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +ADCSequenceStepConfigure(unsigned long ulBase, unsigned long ulSequenceNum, + unsigned long ulStep, unsigned long ulConfig) +{ + // + // Check the arugments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + ASSERT(((ulSequenceNum == 0) && (ulStep < 8)) || + ((ulSequenceNum == 1) && (ulStep < 4)) || + ((ulSequenceNum == 2) && (ulStep < 4)) || + ((ulSequenceNum == 3) && (ulStep < 1))); + + // + // Get the offset of the sequence to be configured. + // + ulBase += ADC_O_SEQ + (ADC_O_SEQ_STEP * ulSequenceNum); + + // + // Compute the shift for the bits that control this step. + // + ulStep *= 4; + + // + // Set the analog mux value for this step. + // + HWREG(ulBase + ADC_O_X_SSMUX) = ((HWREG(ulBase + ADC_O_X_SSMUX) & + ~(0x0000000f << ulStep)) | + ((ulConfig & 0x0f) << ulStep)); + + // + // Set the control value for this step. + // + HWREG(ulBase + ADC_O_X_SSCTL) = ((HWREG(ulBase + ADC_O_X_SSCTL) & + ~(0x0000000f << ulStep)) | + (((ulConfig & 0xf0) >> 4) << ulStep)); +} +#endif + +//***************************************************************************** +// +//! Determines if a sample sequence overflow occurred. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! This determines if a sample sequence overflow has occurred. This will +//! happen if the captured samples are not read from the FIFO before the next +//! trigger occurs. +//! +//! \return Returns zero if there was not an overflow, and non-zero if there +//! was. +// +//***************************************************************************** +#if defined(GROUP_sequenceoverflow) || defined(BUILD_ALL) || defined(DOXYGEN) +long +ADCSequenceOverflow(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + + // + // Determine if there was an overflow on this sequence. + // + return(HWREG(ulBase + ADC_O_OSTAT) & (1 << ulSequenceNum)); +} +#endif + +//***************************************************************************** +// +//! Determines if a sample sequence underflow occurred. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! This determines if a sample sequence underflow has occurred. This will +//! happen if too many samples are read from the FIFO. +//! +//! \return Returns zero if there was not an underflow, and non-zero if there +//! was. +// +//***************************************************************************** +#if defined(GROUP_sequenceunderflow) || defined(BUILD_ALL) || defined(DOXYGEN) +long +ADCSequenceUnderflow(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + + // + // Determine if there was an underflow on this sequence. + // + return(HWREG(ulBase + ADC_O_USTAT) & (1 << ulSequenceNum)); +} +#endif + +//***************************************************************************** +// +//! Gets the captured data for a sample sequence. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! \param pulBuffer is the address where the data is stored. +//! +//! This function copies data from the specified sample sequence output FIFO to +//! a memory resident buffer. The number of samples available in the hardware +//! FIFO are copied into the buffer, which is assumed to be large enough to +//! hold that many samples. This will only return the samples that are +//! presently available, which may not be the entire sample sequence if it is +//! in the process of being executed. +//! +//! \return Returns the number of samples copied to the buffer. +// +//***************************************************************************** +#if defined(GROUP_sequencedataget) || defined(BUILD_ALL) || defined(DOXYGEN) +long +ADCSequenceDataGet(unsigned long ulBase, unsigned long ulSequenceNum, + unsigned long *pulBuffer) +{ + unsigned long ulCount; + + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + + // + // Get the offset of the sequence to be read. + // + ulBase += ADC_O_SEQ + (ADC_O_SEQ_STEP * ulSequenceNum); + + // + // Read samples from the FIFO until it is empty. + // + ulCount = 0; + while(!(HWREG(ulBase + ADC_O_X_SSFSTAT) & ADC_SSFSTAT_EMPTY) && + (ulCount < 8)) + { + // + // Read the FIFO and copy it to the destination. + // + *pulBuffer++ = HWREG(ulBase + ADC_O_X_SSFIFO); + + // + // Increment the count of samples read. + // + ulCount++; + } + + // + // Return the number of samples read. + // + return(ulCount); +} +#endif + +//***************************************************************************** +// +//! Causes a processor trigger for a sample sequence. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! This function triggers a processor-initiated sample sequence if the sample +//! sequence trigger is configured to ADC_TRIGGER_PROCESSOR. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_processortrigger) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ADCProcessorTrigger(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + + // + // Generate a processor trigger for this sample sequence. + // + HWREG(ulBase + ADC_O_PSSI) = 1 << ulSequenceNum; +} +#endif + +//***************************************************************************** +// +//! Configures the software oversampling factor of the ADC. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! \param ulFactor is the number of samples to be averaged. +//! +//! This function configures the software oversampling for the ADC, which can +//! be used to provide better resolution on the sampled data. Oversampling is +//! accomplished by averaging multiple samples from the same analog input. +//! Three different oversampling rates are supported; 2x, 4x, and 8x. +//! +//! Oversampling is only supported on the sample sequencers that are more than +//! one sample in depth (i.e. the fourth sample sequencer is not supported). +//! Oversampling by 2x (for example) divides the depth of the sample sequencer +//! by two; so 2x oversampling on the first sample sequencer can only provide +//! four samples per trigger. This also means that 8x oversampling is only +//! available on the first sample sequencer. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_softwareoversampleconfigure) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +ADCSoftwareOversampleConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulFactor) +{ + unsigned long ulValue; + + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 3); + ASSERT(((ulFactor == 2) || (ulFactor == 4) || (ulFactor == 8)) && + ((ulSequenceNum == 0) || (ulFactor != 8))); + + // + // Convert the oversampling factor to a shift factor. + // + for(ulValue = 0, ulFactor >>= 1; ulFactor; ulValue++, ulFactor >>= 1) + { + } + + // + // Save the sfiht factor. + // + g_pucOversampleFactor[ulSequenceNum] = ulValue; +} +#endif + +//***************************************************************************** +// +//! Configures a step of the software oversampled sequencer. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! \param ulStep is the step to be configured. +//! \param ulConfig is the configuration of this step. +//! +//! This function configures a step of the sample sequencer when using the +//! software oversampling feature. The number of steps available depends on +//! the oversampling factor set by ADCSoftwareOversampleConfigure(). The value +//! of \e ulConfig is the same as defined for ADCSequenceStepConfigure(). +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_softwareoversamplestepconfigure) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +ADCSoftwareOversampleStepConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulStep, + unsigned long ulConfig) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 3); + ASSERT(((ulSequenceNum == 0) && + (ulStep < (8 >> g_pucOversampleFactor[ulSequenceNum]))) || + (ulStep < (4 >> g_pucOversampleFactor[ulSequenceNum]))); + + // + // Get the offset of the sequence to be configured. + // + ulBase += ADC_O_SEQ + (ADC_O_SEQ_STEP * ulSequenceNum); + + // + // Compute the shift for the bits that control this step. + // + ulStep *= 4 << g_pucOversampleFactor[ulSequenceNum]; + + // + // Loop through the hardware steps that make up this step of the software + // oversampled sequence. + // + for(ulSequenceNum = 1 << g_pucOversampleFactor[ulSequenceNum]; + ulSequenceNum; ulSequenceNum--) + { + // + // Set the analog mux value for this step. + // + HWREG(ulBase + ADC_O_X_SSMUX) = ((HWREG(ulBase + ADC_O_X_SSMUX) & + ~(0x0000000f << ulStep)) | + ((ulConfig & 0x0f) << ulStep)); + + // + // Set the control value for this step. + // + HWREG(ulBase + ADC_O_X_SSCTL) = ((HWREG(ulBase + ADC_O_X_SSCTL) & + ~(0x0000000f << ulStep)) | + (((ulConfig & 0xf0) >> 4) << ulStep)); + if(ulSequenceNum != 1) + { + HWREG(ulBase + ADC_O_X_SSCTL) &= ~((ADC_SSCTL_IE0 | + ADC_SSCTL_END0) << ulStep); + } + + // + // Go to the next hardware step. + // + ulStep += 4; + } +} +#endif + +//***************************************************************************** +// +//! Gets the captured data for a sample sequence using software oversampling. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! \param pulBuffer is the address where the data is stored. +//! \param ulCount is the number of samples to be read. +//! +//! This function copies data from the specified sample sequence output FIFO to +//! a memory resident buffer with software oversampling applied. The requested +//! number of samples are copied into the data buffer; if there are not enough +//! samples in the hardware FIFO to satisfy this many oversampled data items +//! then incorrect results will be returned. It is the caller's responsibility +//! to read only the samples that are available and wait until enough data is +//! available, for example as a result of receiving an interrupt. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_softwareoversampledataget) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +ADCSoftwareOversampleDataGet(unsigned long ulBase, unsigned long ulSequenceNum, + unsigned long *pulBuffer, unsigned long ulCount) +{ + unsigned long ulIdx, ulAccum; + + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 3); + ASSERT(((ulSequenceNum == 0) && + (ulCount < (8 >> g_pucOversampleFactor[ulSequenceNum]))) || + (ulCount < (4 >> g_pucOversampleFactor[ulSequenceNum]))); + + // + // Get the offset of the sequence to be read. + // + ulBase += ADC_O_SEQ + (ADC_O_SEQ_STEP * ulSequenceNum); + + // + // Read the samples from the FIFO until it is empty. + // + while(ulCount--) + { + // + // Compute the sum of the samples. + // + ulAccum = 0; + for(ulIdx = 1 << g_pucOversampleFactor[ulSequenceNum]; ulIdx; ulIdx--) + { + // + // Read the FIFO and add it to the accumulator. + // + ulAccum += HWREG(ulBase + ADC_O_X_SSFIFO); + } + + // + // Write the averaged sample to the output buffer. + // + *pulBuffer++ = ulAccum >> g_pucOversampleFactor[ulSequenceNum]; + } +} +#endif + +//***************************************************************************** +// +//! Configures the hardware oversampling factor of the ADC. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulFactor is the number of samples to be averaged. +//! +//! This function configures the hardware oversampling for the ADC, which can +//! be used to provide better resolution on the sampled data. Oversampling is +//! accomplished by averaging multiple samples from the same analog input. Six +//! different oversampling rates are supported; 2x, 4x, 8x, 16x, 32x, and 64x. +//! Specifying an oversampling factor of zero will disable the hardware +//! oversampler. +//! +//! Hardware oversampling applies uniformly to all sample sequencers. It does +//! not reduce the depth of the sample sequencers like the software +//! oversampling APIs; each sample written into the sample sequence FIFO is a +//! fully oversampled analog input reading. +//! +//! Enabling hardware averaging increases the precision of the ADC at the cost +//! of throughput. For example, enabling 4x oversampling reduces the +//! throughput of a 250 KSps ADC to 62.5 KSps. +//! +//! \note Hardware oversampling is available beginning with Rev C0 of the +//! Stellaris microcontroller. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_hardwareoversampleconfigure) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +ADCHardwareOversampleConfigure(unsigned long ulBase, + unsigned long ulFactor) +{ + unsigned long ulValue; + + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(((ulFactor == 0) || (ulFactor == 2) || (ulFactor == 4) || + (ulFactor == 8) || (ulFactor == 16) || (ulFactor == 32) || + (ulFactor == 64))); + + // + // Convert the oversampling factor to a shift factor. + // + for(ulValue = 0, ulFactor >>= 1; ulFactor; ulValue++, ulFactor >>= 1) + { + } + + // + // Write the shift factor to the ADC to configure the hardware oversampler. + // + HWREG(ulBase + ADC_O_SAC) = ulValue; +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/adc.h b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/adc.h new file mode 100644 index 000000000..c1fa37da4 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/adc.h @@ -0,0 +1,126 @@ +//***************************************************************************** +// +// adc.h - ADC headers for using the ADC driver functions. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __ADC_H__ +#define __ADC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to ADCSequenceConfigure as the ulTrigger +// parameter. +// +//***************************************************************************** +#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event +#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event +#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event +#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event +#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event +#define ADC_TRIGGER_TIMER 0x00000005 // Timer event +#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event +#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event +#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event +#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event + +//***************************************************************************** +// +// Values that can be passed to ADCSequenceStepConfigure as the ulConfig +// parameter. +// +//***************************************************************************** +#define ADC_CTL_TS 0x00000080 // Temperature sensor select +#define ADC_CTL_IE 0x00000040 // Interrupt enable +#define ADC_CTL_END 0x00000020 // Sequence end select +#define ADC_CTL_D 0x00000010 // Differential select +#define ADC_CTL_CH0 0x00000000 // Input channel 0 +#define ADC_CTL_CH1 0x00000001 // Input channel 1 +#define ADC_CTL_CH2 0x00000002 // Input channel 2 +#define ADC_CTL_CH3 0x00000003 // Input channel 3 +#define ADC_CTL_CH4 0x00000004 // Input channel 4 +#define ADC_CTL_CH5 0x00000005 // Input channel 5 +#define ADC_CTL_CH6 0x00000006 // Input channel 6 +#define ADC_CTL_CH7 0x00000007 // Input channel 7 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum, + void (*pfnHandler)(void)); +extern void ADCIntUnregister(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum); +extern void ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum); +extern unsigned long ADCIntStatus(unsigned long ulBase, + unsigned long ulSequenceNum, + tBoolean bMasked); +extern void ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum); +extern void ADCSequenceEnable(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCSequenceDisable(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCSequenceConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulTrigger, + unsigned long ulPriority); +extern void ADCSequenceStepConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulStep, + unsigned long ulConfig); +extern long ADCSequenceOverflow(unsigned long ulBase, + unsigned long ulSequenceNum); +extern long ADCSequenceUnderflow(unsigned long ulBase, + unsigned long ulSequenceNum); +extern long ADCSequenceDataGet(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long *pulBuffer); +extern void ADCProcessorTrigger(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCSoftwareOversampleConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulFactor); +extern void ADCSoftwareOversampleStepConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulStep, + unsigned long ulConfig); +extern void ADCSoftwareOversampleDataGet(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long *pulBuffer, + unsigned long ulCount); +extern void ADCHardwareOversampleConfigure(unsigned long ulBase, + unsigned long ulFactor); + +#ifdef __cplusplus +} +#endif + +#endif // __ADC_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/comp.c b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/comp.c new file mode 100644 index 000000000..aed156ea5 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/comp.c @@ -0,0 +1,448 @@ +//***************************************************************************** +// +// comp.c - Driver for the analog comparator. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup comp_api +//! @{ +// +//***************************************************************************** + +#include "../hw_comp.h" +#include "../hw_ints.h" +#include "../hw_memmap.h" +#include "../hw_types.h" +#include "comp.h" +#include "debug.h" +#include "interrupt.h" + +//***************************************************************************** +// +//! Configures a comparator. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index of the comparator to configure. +//! \param ulConfig is the configuration of the comparator. +//! +//! This function will configure a comparator. The \e ulConfig parameter is +//! the result of a logical OR operation between the \b COMP_TRIG_xxx, +//! \b COMP_INT_xxx, \b COMP_ASRCP_xxx, and \b COMP_OUTPUT_xxx values. +//! +//! The \b COMP_TRIG_xxx term can take on the following values: +//! +//! - \b COMP_TRIG_NONE to have no trigger to the ADC. +//! - \b COMP_TRIG_HIGH to trigger the ADC when the comparator output is high. +//! - \b COMP_TRIG_LOW to trigger the ADC when the comparator output is low. +//! - \b COMP_TRIG_FALL to trigger the ADC when the comparator output goes low. +//! - \b COMP_TRIG_RISE to trigger the ADC when the comparator output goes +//! high. +//! - \b COMP_TRIG_BOTH to trigger the ADC when the comparator output goes low +//! or high. +//! +//! The \b COMP_INT_xxx term can take on the following values: +//! +//! - \b COMP_INT_HIGH to generate an interrupt when the comparator output is +//! high. +//! - \b COMP_INT_LOW to generate an interrupt when the comparator output is +//! low. +//! - \b COMP_INT_FALL to generate an interrupt when the comparator output goes +//! low. +//! - \b COMP_INT_RISE to generate an interrupt when the comparator output goes +//! high. +//! - \b COMP_INT_BOTH to generate an interrupt when the comparator output goes +//! low or high. +//! +//! The \b COMP_ASRCP_xxx term can take on the following values: +//! +//! - \b COMP_ASRCP_PIN to use the dedicated Comp+ pin as the reference +//! voltage. +//! - \b COMP_ASRCP_PIN0 to use the Comp0+ pin as the reference voltage (this +//! the same as \b COMP_ASRCP_PIN for the comparator 0). +//! - \b COMP_ASRCP_REF to use the internally generated voltage as the +//! reference voltage. +//! +//! The \b COMP_OUTPUT_xxx term can take on the following values: +//! +//! - \b COMP_OUTPUT_NONE to disable the output from the comparator to a device +//! pin. +//! - \b COMP_OUTPUT_NORMAL to enable a non-inverted output from the comparator +//! to a device pin. +//! - \b COMP_OUTPUT_INVERT to enable an inverted output from the comparator to +//! a device pin. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_configure) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ComparatorConfigure(unsigned long ulBase, unsigned long ulComp, + unsigned long ulConfig) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + ASSERT(ulComp < 3); + + // + // Configure this comparator. + // + HWREG(ulBase + (ulComp * 0x20) + COMP_O_ACCTL0) = ulConfig; +} +#endif + +//***************************************************************************** +// +//! Sets the internal reference voltage. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulRef is the desired reference voltage. +//! +//! This function will set the internal reference voltage value. The voltage +//! is specified as one of the following values: +//! +//! - \b COMP_REF_OFF to turn off the reference voltage +//! - \b COMP_REF_0V to set the reference voltage to 0 V +//! - \b COMP_REF_0_1375V to set the reference voltage to 0.1375 V +//! - \b COMP_REF_0_275V to set the reference voltage to 0.275 V +//! - \b COMP_REF_0_4125V to set the reference voltage to 0.4125 V +//! - \b COMP_REF_0_55V to set the reference voltage to 0.55 V +//! - \b COMP_REF_0_6875V to set the reference voltage to 0.6875 V +//! - \b COMP_REF_0_825V to set the reference voltage to 0.825 V +//! - \b COMP_REF_0_928125V to set the reference voltage to 0.928125 V +//! - \b COMP_REF_0_9625V to set the reference voltage to 0.9625 V +//! - \b COMP_REF_1_03125V to set the reference voltage to 1.03125 V +//! - \b COMP_REF_1_134375V to set the reference voltage to 1.134375 V +//! - \b COMP_REF_1_1V to set the reference voltage to 1.1 V +//! - \b COMP_REF_1_2375V to set the reference voltage to 1.2375 V +//! - \b COMP_REF_1_340625V to set the reference voltage to 1.340625 V +//! - \b COMP_REF_1_375V to set the reference voltage to 1.375 V +//! - \b COMP_REF_1_44375V to set the reference voltage to 1.44375 V +//! - \b COMP_REF_1_5125V to set the reference voltage to 1.5125 V +//! - \b COMP_REF_1_546875V to set the reference voltage to 1.546875 V +//! - \b COMP_REF_1_65V to set the reference voltage to 1.65 V +//! - \b COMP_REF_1_753125V to set the reference voltage to 1.753125 V +//! - \b COMP_REF_1_7875V to set the reference voltage to 1.7875 V +//! - \b COMP_REF_1_85625V to set the reference voltage to 1.85625 V +//! - \b COMP_REF_1_925V to set the reference voltage to 1.925 V +//! - \b COMP_REF_1_959375V to set the reference voltage to 1.959375 V +//! - \b COMP_REF_2_0625V to set the reference voltage to 2.0625 V +//! - \b COMP_REF_2_165625V to set the reference voltage to 2.165625 V +//! - \b COMP_REF_2_26875V to set the reference voltage to 2.26875 V +//! - \b COMP_REF_2_371875V to set the reference voltage to 2.371875 V +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_refset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ComparatorRefSet(unsigned long ulBase, unsigned long ulRef) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + + // + // Set the voltage reference voltage as requested. + // + HWREG(ulBase + COMP_O_REFCTL) = ulRef; +} +#endif + +//***************************************************************************** +// +//! Gets the current comparator output value. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index of the comparator. +//! +//! This function retrieves the current value of the comparator output. +//! +//! \return Returns \b true if the comparator output is high and \b false if +//! the comparator output is low. +// +//***************************************************************************** +#if defined(GROUP_valueget) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +ComparatorValueGet(unsigned long ulBase, unsigned long ulComp) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + ASSERT(ulComp < 3); + + // + // Return the appropriate value based on the comparator's present output + // value. + // + if(HWREG(ulBase + (ulComp * 0x20) + COMP_O_ACSTAT0) & COMP_ACSTAT_OVAL) + { + return(true); + } + else + { + return(false); + } +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for the comparator interrupt. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index of the comparator. +//! \param pfnHandler is a pointer to the function to be called when the +//! comparator interrupt occurs. +//! +//! This sets the handler to be called when the comparator interrupt occurs. +//! This will enable the interrupt in the interrupt controller; it is the +//! interrupt-handler's responsibility to clear the interrupt source via +//! ComparatorIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp, + void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + ASSERT(ulComp < 3); + + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(INT_COMP0 + ulComp, pfnHandler); + + // + // Enable the interrupt in the interrupt controller. + // + IntEnable(INT_COMP0 + ulComp); + + // + // Enable the comparator interrupt. + // + HWREG(ulBase + COMP_O_INTEN) |= 1 << ulComp; +} +#endif + +//***************************************************************************** +// +//! Unregisters an interrupt handler for a comparator interrupt. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index of the comparator. +//! +//! This function will clear the handler to be called when a comparator +//! interrupt occurs. This will also mask off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ComparatorIntUnregister(unsigned long ulBase, unsigned long ulComp) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + ASSERT(ulComp < 3); + + // + // Disable the comparator interrupt. + // + HWREG(ulBase + COMP_O_INTEN) &= ~(1 << ulComp); + + // + // Disable the interrupt in the interrupt controller. + // + IntDisable(INT_COMP0 + ulComp); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_COMP0 + ulComp); +} +#endif + +//***************************************************************************** +// +//! Enables the comparator interrupt. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index of the comparator. +//! +//! This function enables generation of an interrupt from the specified +//! comparator. Only comparators whose interrupts are enabled can be reflected +//! to the processor. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + ASSERT(ulComp < 3); + + // + // Enable the comparator interrupt. + // + HWREG(ulBase + COMP_O_INTEN) |= 1 << ulComp; +} +#endif + +//***************************************************************************** +// +//! Disables the comparator interrupt. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index of the comparator. +//! +//! This function disables generation of an interrupt from the specified +//! comparator. Only comparators whose interrupts are enabled can be reflected +//! to the processor. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + ASSERT(ulComp < 3); + + // + // Disable the comparator interrupt. + // + HWREG(ulBase + COMP_O_INTEN) &= ~(1 << ulComp); +} +#endif + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index of the comparator. +//! \param bMasked is \b false if the raw interrupt status is required and +//! \b true if the masked interrupt status is required. +//! +//! This returns the interrupt status for the comparator. Either the raw or +//! the masked interrupt status can be returned. +//! +//! \return \b true if the interrupt is asserted and \b false if it is not +//! asserted. +// +//***************************************************************************** +#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp, + tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + ASSERT(ulComp < 3); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(((HWREG(ulBase + COMP_O_MIS) >> ulComp) & 1) ? true : false); + } + else + { + return(((HWREG(ulBase + COMP_O_RIS) >> ulComp) & 1) ? true : false); + } +} +#endif + +//***************************************************************************** +// +//! Clears a comparator interrupt. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index of the comparator. +//! +//! The comparator interrupt is cleared, so that it no longer asserts. This +//! must be done in the interrupt handler to keep it from being called again +//! immediately upon exit. Note that for a level triggered interrupt, the +//! interrupt cannot be cleared until it stops asserting. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ComparatorIntClear(unsigned long ulBase, unsigned long ulComp) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + ASSERT(ulComp < 3); + + // + // Clear the interrupt. + // + HWREG(ulBase + COMP_O_MIS) = 1 << ulComp; +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/comp.h b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/comp.h new file mode 100644 index 000000000..9349982c4 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/comp.h @@ -0,0 +1,120 @@ +//***************************************************************************** +// +// comp.h - Prototypes for the analog comparator driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __COMP_H__ +#define __COMP_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to ComparatorConfigure() as the ulConfig +// parameter. For each group (i.e. COMP_TRIG_xxx, COMP_INT_xxx, etc.), one of +// the values may be selected and ORed together will values from the other +// groups. +// +//***************************************************************************** +#define COMP_TRIG_NONE 0x00000000 // No ADC trigger +#define COMP_TRIG_HIGH 0x00000880 // Trigger when high +#define COMP_TRIG_LOW 0x00000800 // Trigger when low +#define COMP_TRIG_FALL 0x00000820 // Trigger on falling edge +#define COMP_TRIG_RISE 0x00000840 // Trigger on rising edge +#define COMP_TRIG_BOTH 0x00000860 // Trigger on both edges +#define COMP_INT_HIGH 0x00000010 // Interrupt when high +#define COMP_INT_LOW 0x00000000 // Interrupt when low +#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge +#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge +#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges +#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin +#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin +#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference +#define COMP_OUTPUT_NONE 0x00000000 // No comparator output +#define COMP_OUTPUT_NORMAL 0x00000100 // Comparator output normal +#define COMP_OUTPUT_INVERT 0x00000102 // Comparator output inverted + +//***************************************************************************** +// +// Values that can be passed to ComparatorSetRef() as the ulRef parameter. +// +//***************************************************************************** +#define COMP_REF_OFF 0x00000000 // Turn off the internal reference +#define COMP_REF_0V 0x00000300 // Internal reference of 0V +#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V +#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V +#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V +#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V +#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V +#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V +#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V +#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V +#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V +#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V +#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V +#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V +#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V +#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V +#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V +#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V +#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V +#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V +#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V +#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V +#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V +#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V +#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V +#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V +#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V +#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V +#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp, + unsigned long ulConfig); +extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef); +extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp); +extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp, + void (*pfnHandler)(void)); +extern void ComparatorIntUnregister(unsigned long ulBase, + unsigned long ulComp); +extern void ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp); +extern void ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp); +extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp, + tBoolean bMasked); +extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp); + +#ifdef __cplusplus +} +#endif + +#endif // __COMP_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/cpu.h b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/cpu.h new file mode 100644 index 000000000..688c52223 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/cpu.h @@ -0,0 +1,40 @@ +//***************************************************************************** +// +// cpu.h - Prototypes for the CPU instruction wrapper functions. +// +// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __CPU_H__ +#define __CPU_H__ + +//***************************************************************************** +// +// Prototypes. +// +//***************************************************************************** +extern void CPUcpsid(void); +extern void CPUcpsie(void); +extern void CPUwfi(void); + +#endif // __CPU_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/debug.h b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/debug.h new file mode 100644 index 000000000..e46e2a772 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/debug.h @@ -0,0 +1,56 @@ +//***************************************************************************** +// +// debug.h - Macros for assisting debug of the driver library. +// +// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __DEBUG_H__ +#define __DEBUG_H__ + +//***************************************************************************** +// +// Prototype for the function that is called when an invalid argument is passed +// to an API. This is only used when doing a DEBUG build. +// +//***************************************************************************** +extern void __error__(char *pcFilename, unsigned long ulLine); + +//***************************************************************************** +// +// The ASSERT macro, which does the actual assertion checking. Typically, this +// will be for procedure arguments. +// +//***************************************************************************** +#ifdef DEBUG +#define ASSERT(expr) { \ + if(!(expr)) \ + { \ + __error__(__FILE__, __LINE__); \ + } \ + } +#else +#define ASSERT(expr) +#endif + +#endif // __DEBUG_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/driverlib.r79 b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/driverlib.r79 new file mode 100644 index 0000000000000000000000000000000000000000..074f82f1209c2c2e29d2e3db8dfc459d5fcfd317 GIT binary patch literal 134217 zcmeFa3w$L-l|NqH_jcd+&13S;BxK%?z)X_K+@3*T@*GHJCJ9LfP?1X}$;<>YNyuX! zh%g`^h^Qd?|ERFO-?|R|{yrDv;Q;t+olAGssne&bPE}Xe`JPiEZWJ!oE{$cg<72zBLnFg?$Au;agf`e4i8ZflZfsqD z{)VRiErck?zr?`o(D0?L<70a!nsFQ6IndcbdA0Z#&t`|G=Cb=HM@Dg%%x0&CXR_JZ zy>t6^5y@hiI5IRl#5Ci$j}GmcnH-;+9VLP?O2}qMCq~AGCU9+zkIl}Gb5<#C!Ekyu zyMJ_gW^9tOwah>0Bjf$zsi$;(NBij)c8uxv;CXzi!~r%n-wx`-iZY+`oCO&bykB<&mBw{K|5O>7ZyB+ee1 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wk2hg zvXHmY=l^q#hXf> (ulAddress / FLASH_PROTECT_SIZE)) & + FLASH_FMP_BLOCK_0) << 1) | + ((ulFMPPE >> (ulAddress / FLASH_PROTECT_SIZE)) & FLASH_FMP_BLOCK_0)) + { + // + // This block is marked as execute only (i.e. it can not be erased or + // programmed, and the only reads allowed are via the instruction fecth + // interface). + // + case 0: + case 1: + { + return(FlashExecuteOnly); + } + + // + // This block is marked as read only (i.e. it can not be erased or + // programmed). + // + case 2: + { + return(FlashReadOnly); + } + + // + // This block is read/write; it can be read, erased, and programmed. + // + case 3: + default: + { + return(FlashReadWrite); + } + } +} +#endif + +//***************************************************************************** +// +//! Sets the protection setting for a block of flash. +//! +//! \param ulAddress is the start address of the flash block to be protected. +//! \param eProtect is the protection to be applied to the block. Can be one +//! of \b FlashReadWrite, \b FlashReadOnly, or \b FlashExecuteOnly. +//! +//! This function will set the protection for the specified 2 kB block of +//! flash. Blocks which are read/write can be made read-only or execute-only. +//! Blocks which are read-only can be made execute-only. Blocks which are +//! execute-only cannot have their protection modified. Attempts to make the +//! block protection less stringent (i.e. read-only to read/write) will result +//! in a failure (and be prevented by the hardware). +//! +//! Changes to the flash protection are maintained only until the next reset. +//! This allows the application to be executed in the desired flash protection +//! environment to check for inappropriate flash access (via the flash +//! interrupt). To make the flash protection permanent, use the +//! FlashProtectSave() function. +//! +//! \return Returns 0 on success, or -1 if an invalid address or an invalid +//! protection was specified. +// +//***************************************************************************** +#if defined(GROUP_protectset) || defined(BUILD_ALL) || defined(DOXYGEN) +long +FlashProtectSet(unsigned long ulAddress, tFlashProtection eProtect) +{ + unsigned long ulProtectRE, ulProtectPE; + + // + // Check the argument. + // + ASSERT(!(ulAddress & (FLASH_PROTECT_SIZE - 1))); + ASSERT((eProtect == FlashReadWrite) || (eProtect == FlashReadOnly) || + (eProtect == FlashExecuteOnly)); + + // + // Convert the address into a block number. + // + ulAddress /= FLASH_PROTECT_SIZE; + + // + // Get the current protection. + // + ulProtectRE = HWREG(FLASH_FMPRE); + ulProtectPE = HWREG(FLASH_FMPPE); + + // + // Set the protection based on the requested proection. + // + switch(eProtect) + { + // + // Make this block execute only. + // + case FlashExecuteOnly: + { + // + // Turn off the read and program bits for this block. + // + ulProtectRE &= ~(FLASH_FMP_BLOCK_0 << ulAddress); + ulProtectPE &= ~(FLASH_FMP_BLOCK_0 << ulAddress); + + // + // We're done handling this protection. + // + break; + } + + // + // Make this block read only. + // + case FlashReadOnly: + { + // + // The block can not be made read only if it is execute only. + // + if(((ulProtectRE >> ulAddress) & FLASH_FMP_BLOCK_0) != + FLASH_FMP_BLOCK_0) + { + return(-1); + } + + // + // Make this block read only. + // + ulProtectPE &= ~(FLASH_FMP_BLOCK_0 << ulAddress); + + // + // We're done handling this protection. + // + break; + } + + // + // Make this block read/write. + // + case FlashReadWrite: + default: + { + // + // The block can not be made read/write if it is not already + // read/write. + // + if((((ulProtectRE >> ulAddress) & FLASH_FMP_BLOCK_0) != + FLASH_FMP_BLOCK_0) || + (((ulProtectPE >> ulAddress) & FLASH_FMP_BLOCK_0) != + FLASH_FMP_BLOCK_0)) + { + return(-1); + } + + // + // The block is already read/write, so there is nothing to do. + // + return(0); + } + } + + // + // Set the new protection. + // + HWREG(FLASH_FMPRE) = ulProtectRE; + HWREG(FLASH_FMPPE) = ulProtectPE; + + // + // Success. + // + return(0); +} +#endif + +//***************************************************************************** +// +//! Saves the flash protection settings. +//! +//! This function will make the currently programmed flash protection settings +//! permanent. This is a non-reversible operation; a chip reset or power cycle +//! will not change the flash protection. +//! +//! This function will not return until the protection has been saved. +//! +//! \return Returns 0 on success, or -1 if a hardware error is encountered. +// +//***************************************************************************** +#if defined(GROUP_protectsave) || defined(BUILD_ALL) || defined(DOXYGEN) +long +FlashProtectSave(void) +{ + // + // Tell the flash controller to write the flash read protection register. + // + HWREG(FLASH_FMA) = 0; + HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT; + + // + // Wait until the write has completed. + // + while(HWREG(FLASH_FMC) & FLASH_FMC_COMT) + { + } + + // + // Tell the flash controller to write the flash program protection + // register. + // + HWREG(FLASH_FMA) = 1; + HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT; + + // + // Wait until the write has completed. + // + while(HWREG(FLASH_FMC) & FLASH_FMC_COMT) + { + } + + // + // Success. + // + return(0); +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for the flash interrupt. +//! +//! \param pfnHandler is a pointer to the function to be called when the flash +//! interrupt occurs. +//! +//! This sets the handler to be called when the flash interrupt occurs. The +//! flash controller can generate an interrupt when an invalid flash access +//! occurs, such as trying to program or erase a read-only block, or trying to +//! read from an execute-only block. It can also generate an interrupt when a +//! program or erase operation has completed. The interrupt will be +//! automatically enabled when the handler is registered. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +FlashIntRegister(void (*pfnHandler)(void)) +{ + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(INT_FLASH, pfnHandler); + + // + // Enable the flash interrupt. + // + IntEnable(INT_FLASH); +} +#endif + +//***************************************************************************** +// +//! Unregisters the interrupt handler for the flash interrupt. +//! +//! This function will clear the handler to be called when the flash interrupt +//! occurs. This will also mask off the interrupt in the interrupt controller +//! so that the interrupt handler is no longer called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +FlashIntUnregister(void) +{ + // + // Disable the interrupt. + // + IntDisable(INT_FLASH); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_FLASH); +} +#endif + +//***************************************************************************** +// +//! Enables individual flash controller interrupt sources. +//! +//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. +//! Can be any of the \b FLASH_FCIM_PROGRAM or \b FLASH_FCIM_ACCESS values. +//! +//! Enables the indicated flash controller interrupt sources. Only the sources +//! that are enabled can be reflected to the processor interrupt; disabled +//! sources have no effect on the processor. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +FlashIntEnable(unsigned long ulIntFlags) +{ + // + // Enable the specified interrupts. + // + HWREG(FLASH_FCIM) |= ulIntFlags; +} +#endif + +//***************************************************************************** +// +//! Disables individual flash controller interrupt sources. +//! +//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled. +//! Can be any of the \b FLASH_FCIM_PROGRAM or \b FLASH_FCIM_ACCESS values. +//! +//! Disables the indicated flash controller interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +FlashIntDisable(unsigned long ulIntFlags) +{ + // + // Disable the specified interrupts. + // + HWREG(FLASH_FCIM) &= ~(ulIntFlags); +} +#endif + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param bMasked is false if the raw interrupt status is required and true if +//! the masked interrupt status is required. +//! +//! This returns the interrupt status for the flash controller. Either the raw +//! interrupt status or the status of interrupts that are allowed to reflect to +//! the processor can be returned. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! \b FLASH_FCMISC_PROGRAM and \b FLASH_FCMISC_ACCESS. +// +//***************************************************************************** +#if defined(GROUP_intgetstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +FlashIntGetStatus(tBoolean bMasked) +{ + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(FLASH_FCMISC)); + } + else + { + return(HWREG(FLASH_FCRIS)); + } +} +#endif + +//***************************************************************************** +// +//! Clears flash controller interrupt sources. +//! +//! \param ulIntFlags is the bit mask of the interrupt sources to be cleared. +//! Can be any of the \b FLASH_FCMISC_PROGRAM or \b FLASH_FCMISC_ACCESS +//! values. +//! +//! The specified flash controller interrupt sources are cleared, so that they +//! no longer assert. This must be done in the interrupt handler to keep it +//! from being called again immediately upon exit. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +FlashIntClear(unsigned long ulIntFlags) +{ + // + // Clear the flash interrupt. + // + HWREG(FLASH_FCMISC) = ulIntFlags; +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/flash.h b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/flash.h new file mode 100644 index 000000000..9c41dda4f --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/flash.h @@ -0,0 +1,75 @@ +//***************************************************************************** +// +// flash.h - Prototypes for the flash driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __FLASH_H__ +#define __FLASH_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to FlashProtectSet(), and returned by +// FlashProtectGet(). +// +//***************************************************************************** +typedef enum +{ + FlashReadWrite, // Flash can be read and written + FlashReadOnly, // Flash can only be read + FlashExecuteOnly // Flash can only be executed +} +tFlashProtection; + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern unsigned long FlashUsecGet(void); +extern void FlashUsecSet(unsigned long ulClocks); +extern long FlashErase(unsigned long ulAddress); +extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress, + unsigned long ulCount); +extern tFlashProtection FlashProtectGet(unsigned long ulAddress); +extern long FlashProtectSet(unsigned long ulAddress, + tFlashProtection eProtect); +extern long FlashProtectSave(void); +extern void FlashIntRegister(void (*pfnHandler)(void)); +extern void FlashIntUnregister(void); +extern void FlashIntEnable(unsigned long ulIntFlags); +extern void FlashIntDisable(unsigned long ulIntFlags); +extern unsigned long FlashIntGetStatus(tBoolean bMasked); +extern void FlashIntClear(unsigned long ulIntFlags); + +#ifdef __cplusplus +} +#endif + +#endif // __FLASH_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/gpio.c b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/gpio.c new file mode 100644 index 000000000..a49602e9b --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/gpio.c @@ -0,0 +1,1103 @@ +//***************************************************************************** +// +// gpio.c - API for GPIO ports +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup gpio_api +//! @{ +// +//***************************************************************************** + +#include "../hw_gpio.h" +#include "../hw_ints.h" +#include "../hw_memmap.h" +#include "../hw_types.h" +#include "debug.h" +#include "gpio.h" +#include "interrupt.h" + +//***************************************************************************** +// +//! \internal +//! Get GPIO interrupt number. +//! +//! \param ulPort base address of the selected GPIO port +//! +//! Given a GPIO base address, returns the corresponding interrupt number. +//! +//! \return Returns a GPIO interrupt number, or -1 if \e ulPort is invalid. +// +//***************************************************************************** +#if defined(GROUP_getintnumber) || defined(BUILD_ALL) +long +GPIOGetIntNumber(unsigned long ulPort) +{ + unsigned int ulInt; + + // + // Determine the GPIO interrupt number for the given module. + // + switch(ulPort) + { + case GPIO_PORTA_BASE: + { + ulInt = INT_GPIOA; + break; + } + + case GPIO_PORTB_BASE: + { + ulInt = INT_GPIOB; + break; + } + + case GPIO_PORTC_BASE: + { + ulInt = INT_GPIOC; + break; + } + + case GPIO_PORTD_BASE: + { + ulInt = INT_GPIOD; + break; + } + + case GPIO_PORTE_BASE: + { + ulInt = INT_GPIOE; + break; + } + + default: + { + return(-1); + } + } + + // + // Return GPIO interrupt number. + // + return(ulInt); +} +#else +extern long GPIOGetIntNumber(unsigned long ulPort); +#endif + +//***************************************************************************** +// +//! Sets the direction and mode of the specified pins of the selected +//! GPIO port. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! \param ulPinIO pin direction and/or mode +//! +//! This function will set the specified pins on the selected GPIO port +//! as either an input or output under software control, or it will set the +//! pin to be under hardware control. +//! +//! The parameter \e ulPinIO is an enumerated data type that can be one of +//! the following values: +//! +//! - \b GPIO_DIR_MODE_IN +//! - \b GPIO_DIR_MODE_OUT +//! - \b GPIO_DIR_MODE_HW +//! +//! where \b GPIO_DIR_MODE_IN specifies that the pin will be programmed as +//! a software controlled input, \b GPIO_DIR_MODE_OUT specifies that the pin +//! will be programmed as a software controlled output, and +//! \b GPIO_DIR_MODE_HW specifies that the pin will be placed under +//! hardware control. +//! +//! The pins are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_dirmodeset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIODirModeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulPinIO) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + ASSERT((ulPinIO == GPIO_DIR_MODE_IN) || (ulPinIO == GPIO_DIR_MODE_OUT) || + (ulPinIO == GPIO_DIR_MODE_HW)); + + // + // Set the pin direction and mode. + // + HWREG(ulPort + GPIO_O_DIR) = ((ulPinIO & 1) ? + (HWREG(ulPort + GPIO_O_DIR) | ucPins) : + (HWREG(ulPort + GPIO_O_DIR) & ~(ucPins))); + HWREG(ulPort + GPIO_O_AFSEL) = ((ulPinIO & 2) ? + (HWREG(ulPort + GPIO_O_AFSEL) | ucPins) : + (HWREG(ulPort + GPIO_O_AFSEL) & + ~(ucPins))); +} +#endif + +//***************************************************************************** +// +//! Gets the direction and mode of a specified pin of the selected +//! GPIO port. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPin pin number of the specified pin, relative to the selected +//! GPIO port. +//! +//! This function gets the direction and control mode for a specified pin on +//! the selected GPIO port. The pin can be configured as either an input or +//! output under software control, or it can be under hardware control. The +//! type of control and direction are returned as an enumerated data type. +//! +//! \return Returns one of the enumerated data types described for +//! GPIODirModeSet(). +// +//***************************************************************************** +#if defined(GROUP_dirmodeget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +GPIODirModeGet(unsigned long ulPort, unsigned char ucPin) +{ + unsigned long ulDir, ulAFSEL; + + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + ASSERT(ucPin < 8); + + // + // Convert from a pin number to a bit position. + // + ucPin = 1 << ucPin; + + // + // Return the pin direction and mode. + // + ulDir = HWREG(ulPort + GPIO_O_DIR); + ulAFSEL = HWREG(ulPort + GPIO_O_AFSEL); + return(((ulDir & ucPin) ? 1 : 0) | ((ulAFSEL & ucPin) ? 2 : 0)); +} +#endif + +//***************************************************************************** +// +//! Sets the interrupt type for the specified pins of the selected GPIO +//! port. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! \param ulIntType specifies the type of interrupt trigger mechanism +//! +//! This function sets up the various interrupt trigger mechanisms for the +//! specified pins on the selected GPIO port. +//! +//! The parameter \e ulIntType is an enumerated data type that can be one of +//! the following values: +//! +//! - \b GPIO_FALLING_EDGE +//! - \b GPIO_RISING_EDGE +//! - \b GPIO_BOTH_EDGES +//! - \b GPIO_LOW_LEVEL +//! - \b GPIO_HIGH_LEVEL +//! +//! where the different values describe the interrupt detection mechanism +//! (edge or level) and the particular triggering event (falling, rising, +//! or both edges for edge detect, low or high for level detect). +//! +//! The pins are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. +//! +//! \note In order to avoid any spurious interrupts, the user must +//! ensure that the GPIO inputs remain stable for the duration of +//! this function. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_inttypeset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulIntType) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + ASSERT((ulIntType == GPIO_FALLING_EDGE) || + (ulIntType == GPIO_RISING_EDGE) || + (ulIntType == GPIO_BOTH_EDGES) || + (ulIntType == GPIO_LOW_LEVEL) || + (ulIntType == GPIO_HIGH_LEVEL)); + + // + // Set the pin interrupt type. + // + HWREG(ulPort + GPIO_O_IBE) = ((ulIntType & 1) ? + (HWREG(ulPort + GPIO_O_IBE) | ucPins) : + (HWREG(ulPort + GPIO_O_IBE) & ~(ucPins))); + HWREG(ulPort + GPIO_O_IS) = ((ulIntType & 2) ? + (HWREG(ulPort + GPIO_O_IS) | ucPins) : + (HWREG(ulPort + GPIO_O_IS) & ~(ucPins))); + HWREG(ulPort + GPIO_O_IEV) = ((ulIntType & 4) ? + (HWREG(ulPort + GPIO_O_IEV) | ucPins) : + (HWREG(ulPort + GPIO_O_IEV) & ~(ucPins))); +} +#endif + +//***************************************************************************** +// +//! Gets the interrupt type for the specified pin of the selected GPIO +//! port. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPin pin number of the specified pin, relative to the selected +//! GPIO port. +//! +//! This function gets the interrupt type for a specified pin on the selected +//! GPIO port. The pin can be configured as a falling edge, rising edge, or +//! both edge detected interrupt, or it can be configured as a low level or +//! high level detected interrupt. The type of interrupt detection mechanism +//! is returned as an enumerated data type. +//! +//! \return Returns one of the enumerated data types described for +//! GPIOIntTypeSet(). +// +//***************************************************************************** +#if defined(GROUP_inttypeget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin) +{ + unsigned long ulIBE, ulIS, ulIEV; + + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + ASSERT(ucPin < 8); + + // + // Convert from a pin number to a bit position. + // + ucPin = 1 << ucPin; + + // + // Return the pin interrupt type. + // + ulIBE = HWREG(ulPort + GPIO_O_IBE); + ulIS = HWREG(ulPort + GPIO_O_IS); + ulIEV = HWREG(ulPort + GPIO_O_IEV); + return(((ulIBE & ucPin) ? 1 : 0) | ((ulIS & ucPin) ? 2 : 0) | + ((ulIEV & ucPin) ? 4 : 0)); +} +#endif + +//***************************************************************************** +// +//! Sets the pad configuration for the specified pins of the selected GPIO +//! port. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins bit-packed representation of the specified pins. +//! \param ulStrength specifies the output drive strength. +//! \param ulPinType specifies the pin type. +//! +//! This function sets the drive strength and type for the specified pins +//! on the selected GPIO port. For pins configured as input ports, the +//! pad is configured as requested, but the only real effect on the input +//! is the configuration of the pull-up or pull-down termination. +//! +//! The parameter \e ulStrength can be one of the following values: +//! +//! - \b GPIO_STRENGTH_2MA +//! - \b GPIO_STRENGTH_4MA +//! - \b GPIO_STRENGTH_8MA +//! - \b GPIO_STRENGTH_8MA_SC +//! +//! where \b GPIO_STRENGTH_xMA specifies either 2, 4, or 8 mA output drive +//! strength, and \b GPIO_OUT_STRENGTH_8MA_SC specifies 8 mA output drive with +//! slew control. +//! +//! The parameter \e ulPinType can be one of the following values: +//! +//! - \b GPIO_PIN_TYPE_STD +//! - \b GPIO_PIN_TYPE_STD_WPU +//! - \b GPIO_PIN_TYPE_STD_WPD +//! - \b GPIO_PIN_TYPE_OD +//! - \b GPIO_PIN_TYPE_OD_WPU +//! - \b GPIO_PIN_TYPE_OD_WPD +//! - \b GPIO_PIN_TYPE_ANALOG +//! +//! where \b GPIO_PIN_TYPE_STD* specifies a push-pull pin, \b GPIO_PIN_TYPE_OD* +//! specifies an open-drain pin, \b *_WPU specifies a weak pull-up, \b *_WPD +//! specifies a weak pull-down, and \b GPIO_PIN_TYPE_ANALOG specifies an +//! analog input (for the comparators). +//! +//! The pins are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_padconfigset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulStrength, unsigned long ulPinType) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + ASSERT((ulStrength == GPIO_STRENGTH_2MA) || + (ulStrength == GPIO_STRENGTH_4MA) || + (ulStrength == GPIO_STRENGTH_8MA) || + (ulStrength == GPIO_STRENGTH_8MA_SC)); + ASSERT((ulPinType == GPIO_PIN_TYPE_STD) || + (ulPinType == GPIO_PIN_TYPE_STD_WPU) || + (ulPinType == GPIO_PIN_TYPE_STD_WPD) || + (ulPinType == GPIO_PIN_TYPE_OD) || + (ulPinType == GPIO_PIN_TYPE_OD_WPU) || + (ulPinType == GPIO_PIN_TYPE_OD_WPD) || + (ulPinType == GPIO_PIN_TYPE_ANALOG)) + + // + // Set the output drive strength. + // + HWREG(ulPort + GPIO_O_DR2R) = ((ulStrength & 1) ? + (HWREG(ulPort + GPIO_O_DR2R) | ucPins) : + (HWREG(ulPort + GPIO_O_DR2R) & ~(ucPins))); + HWREG(ulPort + GPIO_O_DR4R) = ((ulStrength & 2) ? + (HWREG(ulPort + GPIO_O_DR4R) | ucPins) : + (HWREG(ulPort + GPIO_O_DR4R) & ~(ucPins))); + HWREG(ulPort + GPIO_O_DR8R) = ((ulStrength & 4) ? + (HWREG(ulPort + GPIO_O_DR8R) | ucPins) : + (HWREG(ulPort + GPIO_O_DR8R) & ~(ucPins))); + HWREG(ulPort + GPIO_O_SLR) = ((ulStrength & 8) ? + (HWREG(ulPort + GPIO_O_SLR) | ucPins) : + (HWREG(ulPort + GPIO_O_SLR) & ~(ucPins))); + + // + // Set the pin type. + // + HWREG(ulPort + GPIO_O_ODR) = ((ulPinType & 1) ? + (HWREG(ulPort + GPIO_O_ODR) | ucPins) : + (HWREG(ulPort + GPIO_O_ODR) & ~(ucPins))); + HWREG(ulPort + GPIO_O_PUR) = ((ulPinType & 2) ? + (HWREG(ulPort + GPIO_O_PUR) | ucPins) : + (HWREG(ulPort + GPIO_O_PUR) & ~(ucPins))); + HWREG(ulPort + GPIO_O_PDR) = ((ulPinType & 4) ? + (HWREG(ulPort + GPIO_O_PDR) | ucPins) : + (HWREG(ulPort + GPIO_O_PDR) & ~(ucPins))); + HWREG(ulPort + GPIO_O_DEN) = ((ulPinType & 8) ? + (HWREG(ulPort + GPIO_O_DEN) | ucPins) : + (HWREG(ulPort + GPIO_O_DEN) & ~(ucPins))); +} +#endif + +//***************************************************************************** +// +//! Gets the pad configuration for the specified pin of the selected GPIO +//! port. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPin pin number of the specified pin, relative to the selected +//! GPIO port. +//! \param pulStrength pointer to storage for the output drive strength +//! \param pulPinType pointer to storage for the output drive type +//! +//! This function gets the pad configuration for a specified pin on the +//! selected GPIO port. The values returned in \e eStrength and \e eOutType +//! correspond to the values used in GPIOPadConfigSet(). This function also +//! works for pins configured as input pins; however, the only meaningful +//! data returned is whether the pin is terminated with a pull-up or +//! down resistor. +//! +//! \return None +// +//***************************************************************************** +#if defined(GROUP_padconfigget) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin, + unsigned long *pulStrength, unsigned long *pulPinType) +{ + unsigned long ulTemp1, ulTemp2, ulTemp3, ulTemp4; + + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + ASSERT(ucPin < 8); + + // + // Convert from a pin number to a bit position. + // + ucPin = (1 << ucPin); + + // + // Get the drive strength for this pin. + // + ulTemp1 = HWREG(ulPort + GPIO_O_DR2R); + ulTemp2 = HWREG(ulPort + GPIO_O_DR4R); + ulTemp3 = HWREG(ulPort + GPIO_O_DR8R); + ulTemp4 = HWREG(ulPort + GPIO_O_SLR); + *pulStrength = (((ulTemp1 & ucPin) ? 1 : 0) | ((ulTemp2 & ucPin) ? 2 : 0) | + ((ulTemp3 & ucPin) ? 4 : 0) | ((ulTemp4 & ucPin) ? 8 : 0)); + + // + // Get the pin type. + // + ulTemp1 = HWREG(ulPort + GPIO_O_ODR); + ulTemp2 = HWREG(ulPort + GPIO_O_PUR); + ulTemp3 = HWREG(ulPort + GPIO_O_PDR); + ulTemp4 = HWREG(ulPort + GPIO_O_DEN); + *pulPinType = (((ulTemp1 & ucPin) ? 1 : 0) | ((ulTemp2 & ucPin) ? 2 : 0) | + ((ulTemp3 & ucPin) ? 4 : 0) | ((ulTemp4 & ucPin) ? 8 : 0)); +} +#endif + +//***************************************************************************** +// +//! Enables interrupts for the specified pins of the selected GPIO port. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! +//! Unmasks the interrupt for the specified pins. +//! +//! The pins are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pinintenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Enable the interrupts. + // + HWREG(ulPort + GPIO_O_IM) |= ucPins; +} +#endif + +//***************************************************************************** +// +//! Disables interrupts for the specified pins of the selected GPIO port. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! +//! Masks the interrupt for the specified pins. +//! +//! The pins are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pinintdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Disable the interrupts. + // + HWREG(ulPort + GPIO_O_IM) &= ~(ucPins); +} +#endif + +//***************************************************************************** +// +//! Gets interrupt status for all the pins of the selected GPIO port. +//! +//! \param ulPort base address of the selected GPIO port +//! \param bMasked specifies whether masked or raw interrupt +//! status is returned +//! +//! If \e bMasked is set as \b true, then the masked interrupt status is +//! returned; otherwise, the raw interrupt status will be returned. +//! +//! \return Returns a bit-packed byte, where each bit that is set identifies +//! an active masked or raw interrupt, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. Bits +//! 31:8 should be ignored. +// +//***************************************************************************** +#if defined(GROUP_pinintstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +long +GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Return the interrupt status. + // + if(bMasked) + { + return(HWREG(ulPort + GPIO_O_MIS)); + } + else + { + return(HWREG(ulPort + GPIO_O_RIS)); + } +} +#endif + +//***************************************************************************** +// +//! Clears the interrupt for the specified pins of the selected GPIO port. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! +//! Clears the interrupt for the specified pins. +//! +//! The pins are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pinintclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Clear the interrupts. + // + HWREG(ulPort + GPIO_O_ICR) = ucPins; +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for the selected GPIO port. +//! +//! \param ulPort base address of the selected GPIO port +//! \param pfIntHandler pointer to the GPIO port interrupt handling function +//! +//! This function will ensure that the interrupt handler specified by \e +//! pfIntHandler is called when an interrupt is detected from the selected +//! GPIO port. This function will also enable the corresponding GPIO +//! interrupt in the interrupt controller; individual pin interrupts and +//! interrupt sources must be enabled with GPIOPinIntEnable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_portintregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPortIntRegister(unsigned long ulPort, void (*pfIntHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Get the interrupt number associated with the specified GPIO. + // + ulPort = GPIOGetIntNumber(ulPort); + + // + // Register the interrupt handler. + // + IntRegister(ulPort, pfIntHandler); + + // + // Enable the GPIO interrupt. + // + IntEnable(ulPort); +} +#endif + +//***************************************************************************** +// +//! Removes an interrupt handler for the selected GPIO port. +//! +//! \param ulPort base address of the selected GPIO port +//! +//! This function will unregister the interrupt handler for the specified +//! GPIO port. This function will also disable the corresponding +//! GPIO port interrupt in the interrupt controller; individual GPIO interrupts +//! and interrupt sources must be disabled with GPIOPinIntDisable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_portintunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPortIntUnregister(unsigned long ulPort) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Get the interrupt number associated with the specified GPIO. + // + ulPort = GPIOGetIntNumber(ulPort); + + // + // Disable the GPIO interrupt. + // + IntDisable(ulPort); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulPort); +} +#endif + +//***************************************************************************** +// +//! Reads the values present at the specified pins of the selected GPIO port. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! +//! The values at the specified pins are read, as specified by \e ucPins. +//! Values are returned for both input and output pins, and the value +//! for pins that are not specified by \e ucPins are set to 0. +//! +//! The pins are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. +//! +//! \return Returns a bit-packed byte providing the state of the specified +//! pin, where bit 0 of the byte represents GPIO port pin 0, bit 1 represents +//! GPIO port pin 1, etc. Any bit that is not specified by \e ucPins +//! is returned as a 0. Bits 31:8 should be ignored. +// +//***************************************************************************** +#if defined(GROUP_pinread) || defined(BUILD_ALL) || defined(DOXYGEN) +long +GPIOPinRead(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Return the pin value(s). + // + return(HWREG(ulPort + (GPIO_O_DATA + (ucPins << 2)))); +} +#endif + +//***************************************************************************** +// +//! Writes a value at the specified pins of the selected GPIO port. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! \param ucVal value to write to the specified pins +//! +//! Writes the corresponding bit values to the output pins specified +//! by \e ucPins. Writing to a pin configured as an input pin has no +//! effect. +//! +//! The pins are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pinwrite) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, unsigned char ucVal) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Write the pins. + // + HWREG(ulPort + (GPIO_O_DATA + (ucPins << 2))) = ucVal; +} +#endif + +//***************************************************************************** +// +//! Configures pin(s) for use as an analog comparator input. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! +//! The analog comparator input pins must be properly configured for the analog +//! comparator to function correctly. This function provides the proper +//! configuration for those pins. +//! +//! \note This cannot be used to turn any pin into an analog comparator input; +//! it only configures an analog comparator pin for proper operation. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pintypecomparator) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Make the pin(s) be inputs. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_IN); + + // + // Set the pad(s) for analog operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_ANALOG); +} +#endif + +//***************************************************************************** +// +//! Configures pin(s) for use by the I2C peripheral. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! +//! The I2C pins must be properly configured for the I2C peripheral to function +//! correctly. This function provides the proper configuration for those pins. +//! +//! \note This cannot be used to turn any pin into an I2C pin; it only +//! configures an I2C pin for proper operation. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pintypei2c) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for open-drain operation with a weak pull-up. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD_WPU); +} +#endif + +//***************************************************************************** +// +//! Configures pin(s) for use by the PWM peripheral. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! +//! The PWM pins must be properly configured for the PWM peripheral to function +//! correctly. This function provides a typical configuration for those pins; +//! other configurations may work as well depending upon the board setup (for +//! example, using the on-chip pull-ups). +//! +//! \note This cannot be used to turn any pin into a PWM pin; it only +//! configures a PWM pin for proper operation. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pintypepwm) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} +#endif + +//***************************************************************************** +// +//! Configures pin(s) for use by the QEI peripheral. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! +//! The QEI pins must be properly configured for the QEI peripheral to function +//! correctly. This function provides a typical configuration for those pins; +//! other configurations may work as well depending upon the board setup (for +//! example, not using the on-chip pull-ups). +//! +//! \note This cannot be used to turn any pin into a QEI pin; it only +//! configures a QEI pin for proper operation. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pintypeqei) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation with a weak pull-up. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU); +} +#endif + +//***************************************************************************** +// +//! Configures pin(s) for use by the SSI peripheral. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! +//! The SSI pins must be properly configured for the SSI peripheral to function +//! correctly. This function provides a typical configuration for those pins; +//! other configurations may work as well depending upon the board setup (for +//! example, using the on-chip pull-ups). +//! +//! \note This cannot be used to turn any pin into a SSI pin; it only +//! configures a SSI pin for proper operation. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pintypessi) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} +#endif + +//***************************************************************************** +// +//! Configures pin(s) for use by the Timer peripheral. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! +//! The CCP pins must be properly configured for the timer peripheral to +//! function correctly. This function provides a typical configuration for +//! those pins; other configurations may work as well depending upon the board +//! setup (for example, using the on-chip pull-ups). +//! +//! \note This cannot be used to turn any pin into a timer pin; it only +//! configures a timer pin for proper operation. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pintypetimer) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} +#endif + +//***************************************************************************** +// +//! Configures pin(s) for use by the UART peripheral. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! +//! The UART pins must be properly configured for the UART peripheral to +//! function correctly. This function provides a typical configuration for +//! those pins; other configurations may work as well depending upon the board +//! setup (for example, using the on-chip pull-ups). +//! +//! \note This cannot be used to turn any pin into a UART pin; it only +//! configures a UART pin for proper operation. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pintypeuart) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/gpio.h b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/gpio.h new file mode 100644 index 000000000..88d657223 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/gpio.h @@ -0,0 +1,137 @@ +//***************************************************************************** +// +// gpio.h - Defines and Macros for GPIO API. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __GPIO_H__ +#define __GPIO_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following values define the bit field for the ucPins argument to several +// of the APIs. +// +//***************************************************************************** +#define GPIO_PIN_0 0x00000001 // GPIO pin 0 +#define GPIO_PIN_1 0x00000002 // GPIO pin 1 +#define GPIO_PIN_2 0x00000004 // GPIO pin 2 +#define GPIO_PIN_3 0x00000008 // GPIO pin 3 +#define GPIO_PIN_4 0x00000010 // GPIO pin 4 +#define GPIO_PIN_5 0x00000020 // GPIO pin 5 +#define GPIO_PIN_6 0x00000040 // GPIO pin 6 +#define GPIO_PIN_7 0x00000080 // GPIO pin 7 + +//***************************************************************************** +// +// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and +// returned from GPIODirModeGet. +// +//***************************************************************************** +#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input +#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output +#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function + +//***************************************************************************** +// +// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and +// returned from GPIOIntTypeGet. +// +//***************************************************************************** +#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge +#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge +#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges +#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level +#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level + +//***************************************************************************** +// +// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter, +// and returned by GPIOPadConfigGet in the *pulStrength parameter. +// +//***************************************************************************** +#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength +#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength +#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength +#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control + +//***************************************************************************** +// +// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter, +// and returned by GPIOPadConfigGet in the *pulPadType parameter. +// +//***************************************************************************** +#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull +#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up +#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down +#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain +#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up +#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down +#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulPinIO); +extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin); +extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulIntType); +extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin); +extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulStrength, + unsigned long ulPadType); +extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin, + unsigned long *pulStrength, + unsigned long *pulPadType); +extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins); +extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked); +extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPortIntRegister(unsigned long ulPort, + void (*pfIntHandler)(void)); +extern void GPIOPortIntUnregister(unsigned long ulPort); +extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, + unsigned char ucVal); +extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins); + +#ifdef __cplusplus +} +#endif + +#endif // __GPIO_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/hw_adc.h b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/hw_adc.h new file mode 100644 index 000000000..022b9e963 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/hw_adc.h @@ -0,0 +1,343 @@ +//***************************************************************************** +// +// hw_adc.h - Macros used when accessing the ADC hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_ADC_H__ +#define __HW_ADC_H__ + +//***************************************************************************** +// +// The following define the offsets of the ADC registers. +// +//***************************************************************************** +#define ADC_O_ACTSS 0x00000000 // Active sample register +#define ADC_O_RIS 0x00000004 // Raw interrupt status register +#define ADC_O_IM 0x00000008 // Interrupt mask register +#define ADC_O_ISC 0x0000000C // Interrupt status/clear register +#define ADC_O_OSTAT 0x00000010 // Overflow status register +#define ADC_O_EMUX 0x00000014 // Event multiplexer select reg. +#define ADC_O_USTAT 0x00000018 // Underflow status register +#define ADC_O_SSPRI 0x00000020 // Channel priority register +#define ADC_O_PSSI 0x00000028 // Processor sample initiate reg. +#define ADC_O_SAC 0x00000030 // Sample Averaging Control reg. +#define ADC_O_SSMUX0 0x00000040 // Multiplexer select 0 register +#define ADC_O_SSCTL0 0x00000044 // Sample sequence control 0 reg. +#define ADC_O_SSFIFO0 0x00000048 // Result FIFO 0 register +#define ADC_O_SSFSTAT0 0x0000004C // FIFO 0 status register +#define ADC_O_SSMUX1 0x00000060 // Multiplexer select 1 register +#define ADC_O_SSCTL1 0x00000064 // Sample sequence control 1 reg. +#define ADC_O_SSFIFO1 0x00000068 // Result FIFO 1 register +#define ADC_O_SSFSTAT1 0x0000006C // FIFO 1 status register +#define ADC_O_SSMUX2 0x00000080 // Multiplexer select 2 register +#define ADC_O_SSCTL2 0x00000084 // Sample sequence control 2 reg. +#define ADC_O_SSFIFO2 0x00000088 // Result FIFO 2 register +#define ADC_O_SSFSTAT2 0x0000008C // FIFO 2 status register +#define ADC_O_SSMUX3 0x000000A0 // Multiplexer select 3 register +#define ADC_O_SSCTL3 0x000000A4 // Sample sequence control 3 reg. +#define ADC_O_SSFIFO3 0x000000A8 // Result FIFO 3 register +#define ADC_O_SSFSTAT3 0x000000AC // FIFO 3 status register +#define ADC_O_TMLB 0x00000100 // Test mode loopback register + +//***************************************************************************** +// +// The following define the offsets of the ADC sequence registers. +// +//***************************************************************************** +#define ADC_O_SEQ 0x00000040 // Offset to the first sequence +#define ADC_O_SEQ_STEP 0x00000020 // Increment to the next sequence +#define ADC_O_X_SSMUX 0x00000000 // Multiplexer select register +#define ADC_O_X_SSCTL 0x00000004 // Sample sequence control register +#define ADC_O_X_SSFIFO 0x00000008 // Result FIFO register +#define ADC_O_X_SSFSTAT 0x0000000C // FIFO status register + +//***************************************************************************** +// +// The following define the bit fields in the ADC_ACTSS register. +// +//***************************************************************************** +#define ADC_ACTSS_ASEN3 0x00000008 // Sample sequence 3 enable +#define ADC_ACTSS_ASEN2 0x00000004 // Sample sequence 2 enable +#define ADC_ACTSS_ASEN1 0x00000002 // Sample sequence 1 enable +#define ADC_ACTSS_ASEN0 0x00000001 // Sample sequence 0 enable + +//***************************************************************************** +// +// The following define the bit fields in the ADC_RIS register. +// +//***************************************************************************** +#define ADC_RIS_INR3 0x00000008 // Sample sequence 3 interrupt +#define ADC_RIS_INR2 0x00000004 // Sample sequence 2 interrupt +#define ADC_RIS_INR1 0x00000002 // Sample sequence 1 interrupt +#define ADC_RIS_INR0 0x00000001 // Sample sequence 0 interrupt + +//***************************************************************************** +// +// The following define the bit fields in the ADC_IM register. +// +//***************************************************************************** +#define ADC_IM_MASK3 0x00000008 // Sample sequence 3 mask +#define ADC_IM_MASK2 0x00000004 // Sample sequence 2 mask +#define ADC_IM_MASK1 0x00000002 // Sample sequence 1 mask +#define ADC_IM_MASK0 0x00000001 // Sample sequence 0 mask + +//***************************************************************************** +// +// The following define the bit fields in the ADC_ISC register. +// +//***************************************************************************** +#define ADC_ISC_IN3 0x00000008 // Sample sequence 3 interrupt +#define ADC_ISC_IN2 0x00000004 // Sample sequence 2 interrupt +#define ADC_ISC_IN1 0x00000002 // Sample sequence 1 interrupt +#define ADC_ISC_IN0 0x00000001 // Sample sequence 0 interrupt + +//***************************************************************************** +// +// The following define the bit fields in the ADC_OSTAT register. +// +//***************************************************************************** +#define ADC_OSTAT_OV3 0x00000008 // Sample sequence 3 overflow +#define ADC_OSTAT_OV2 0x00000004 // Sample sequence 2 overflow +#define ADC_OSTAT_OV1 0x00000002 // Sample sequence 1 overflow +#define ADC_OSTAT_OV0 0x00000001 // Sample sequence 0 overflow + +//***************************************************************************** +// +// The following define the bit fields in the ADC_EMUX register. +// +//***************************************************************************** +#define ADC_EMUX_EM3_MASK 0x0000F000 // Event mux 3 mask +#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor event +#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog comparator 0 event +#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog comparator 1 event +#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog comparator 2 event +#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External event +#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer event +#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0 event +#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1 event +#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2 event +#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always event +#define ADC_EMUX_EM2_MASK 0x00000F00 // Event mux 2 mask +#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor event +#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog comparator 0 event +#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog comparator 1 event +#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog comparator 2 event +#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External event +#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer event +#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0 event +#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1 event +#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2 event +#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always event +#define ADC_EMUX_EM1_MASK 0x000000F0 // Event mux 1 mask +#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor event +#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog comparator 0 event +#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog comparator 1 event +#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog comparator 2 event +#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External event +#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer event +#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0 event +#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1 event +#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2 event +#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always event +#define ADC_EMUX_EM0_MASK 0x0000000F // Event mux 0 mask +#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor event +#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog comparator 0 event +#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog comparator 1 event +#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog comparator 2 event +#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External event +#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer event +#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0 event +#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1 event +#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2 event +#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always event +#define ADC_EMUX_EM0_SHIFT 0 // The shift for the first event +#define ADC_EMUX_EM1_SHIFT 4 // The shift for the second event +#define ADC_EMUX_EM2_SHIFT 8 // The shift for the third event +#define ADC_EMUX_EM3_SHIFT 12 // The shift for the fourth event + +//***************************************************************************** +// +// The following define the bit fields in the ADC_USTAT register. +// +//***************************************************************************** +#define ADC_USTAT_UV3 0x00000008 // Sample sequence 3 underflow +#define ADC_USTAT_UV2 0x00000004 // Sample sequence 2 underflow +#define ADC_USTAT_UV1 0x00000002 // Sample sequence 1 underflow +#define ADC_USTAT_UV0 0x00000001 // Sample sequence 0 underflow + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SSPRI register. +// +//***************************************************************************** +#define ADC_SSPRI_SS3_MASK 0x00003000 // Sequencer 3 priority mask +#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority +#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority +#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority +#define ADC_SSPRI_SS2_MASK 0x00000300 // Sequencer 2 priority mask +#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority +#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority +#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority +#define ADC_SSPRI_SS1_MASK 0x00000030 // Sequencer 1 priority mask +#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority +#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority +#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority +#define ADC_SSPRI_SS0_MASK 0x00000003 // Sequencer 0 priority mask +#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority +#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority +#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority + +//***************************************************************************** +// +// The following define the bit fields in the ADC_PSSI register. +// +//***************************************************************************** +#define ADC_PSSI_SS3 0x00000008 // Trigger sample sequencer 3 +#define ADC_PSSI_SS2 0x00000004 // Trigger sample sequencer 2 +#define ADC_PSSI_SS1 0x00000002 // Trigger sample sequencer 1 +#define ADC_PSSI_SS0 0x00000001 // Trigger sample sequencer 0 + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SAC register. +// +//***************************************************************************** +#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling +#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling +#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling +#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling +#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling +#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling +#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SSMUX0, ADC_SSMUX1, +// ADC_SSMUX2, and ADC_SSMUX3 registers. Not all fields are present in all +// registers. +// +//***************************************************************************** +#define ADC_SSMUX_MUX7_MASK 0x70000000 // 8th mux select mask +#define ADC_SSMUX_MUX6_MASK 0x07000000 // 7th mux select mask +#define ADC_SSMUX_MUX5_MASK 0x00700000 // 6th mux select mask +#define ADC_SSMUX_MUX4_MASK 0x00070000 // 5th mux select mask +#define ADC_SSMUX_MUX3_MASK 0x00007000 // 4th mux select mask +#define ADC_SSMUX_MUX2_MASK 0x00000700 // 3rd mux select mask +#define ADC_SSMUX_MUX1_MASK 0x00000070 // 2nd mux select mask +#define ADC_SSMUX_MUX0_MASK 0x00000007 // 1st mux select mask +#define ADC_SSMUX_MUX7_SHIFT 28 +#define ADC_SSMUX_MUX6_SHIFT 24 +#define ADC_SSMUX_MUX5_SHIFT 20 +#define ADC_SSMUX_MUX4_SHIFT 16 +#define ADC_SSMUX_MUX3_SHIFT 12 +#define ADC_SSMUX_MUX2_SHIFT 8 +#define ADC_SSMUX_MUX1_SHIFT 4 +#define ADC_SSMUX_MUX0_SHIFT 0 + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SSCTL0, ADC_SSCTL1, +// ADC_SSCTL2, and ADC_SSCTL3 registers. Not all fields are present in all +// registers. +// +//***************************************************************************** +#define ADC_SSCTL_TS7 0x80000000 // 8th temperature sensor select +#define ADC_SSCTL_IE7 0x40000000 // 8th interrupt enable +#define ADC_SSCTL_END7 0x20000000 // 8th sequence end select +#define ADC_SSCTL_D7 0x10000000 // 8th differential select +#define ADC_SSCTL_TS6 0x08000000 // 7th temperature sensor select +#define ADC_SSCTL_IE6 0x04000000 // 7th interrupt enable +#define ADC_SSCTL_END6 0x02000000 // 7th sequence end select +#define ADC_SSCTL_D6 0x01000000 // 7th differential select +#define ADC_SSCTL_TS5 0x00800000 // 6th temperature sensor select +#define ADC_SSCTL_IE5 0x00400000 // 6th interrupt enable +#define ADC_SSCTL_END5 0x00200000 // 6th sequence end select +#define ADC_SSCTL_D5 0x00100000 // 6th differential select +#define ADC_SSCTL_TS4 0x00080000 // 5th temperature sensor select +#define ADC_SSCTL_IE4 0x00040000 // 5th interrupt enable +#define ADC_SSCTL_END4 0x00020000 // 5th sequence end select +#define ADC_SSCTL_D4 0x00010000 // 5th differential select +#define ADC_SSCTL_TS3 0x00008000 // 4th temperature sensor select +#define ADC_SSCTL_IE3 0x00004000 // 4th interrupt enable +#define ADC_SSCTL_END3 0x00002000 // 4th sequence end select +#define ADC_SSCTL_D3 0x00001000 // 4th differential select +#define ADC_SSCTL_TS2 0x00000800 // 3rd temperature sensor select +#define ADC_SSCTL_IE2 0x00000400 // 3rd interrupt enable +#define ADC_SSCTL_END2 0x00000200 // 3rd sequence end select +#define ADC_SSCTL_D2 0x00000100 // 3rd differential select +#define ADC_SSCTL_TS1 0x00000080 // 2nd temperature sensor select +#define ADC_SSCTL_IE1 0x00000040 // 2nd interrupt enable +#define ADC_SSCTL_END1 0x00000020 // 2nd sequence end select +#define ADC_SSCTL_D1 0x00000010 // 2nd differential select +#define ADC_SSCTL_TS0 0x00000008 // 1st temperature sensor select +#define ADC_SSCTL_IE0 0x00000004 // 1st interrupt enable +#define ADC_SSCTL_END0 0x00000002 // 1st sequence end select +#define ADC_SSCTL_D0 0x00000001 // 1st differential select + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SSFIFO0, ADC_SSFIFO1, +// ADC_SSFIFO2, and ADC_SSFIFO3 registers. +// +//***************************************************************************** +#define ADC_SSFIFO_DATA_MASK 0x000003FF // Sample data +#define ADC_SSFIFO_DATA_SHIFT 0 + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SSFSTAT0, ADC_SSFSTAT1, +// ADC_SSFSTAT2, and ADC_SSFSTAT3 registers. +// +//***************************************************************************** +#define ADC_SSFSTAT_FULL 0x00001000 // FIFO is full +#define ADC_SSFSTAT_EMPTY 0x00000100 // FIFO is empty +#define ADC_SSFSTAT_HPTR 0x000000F0 // FIFO head pointer +#define ADC_SSFSTAT_TPTR 0x0000000F // FIFO tail pointer + +//***************************************************************************** +// +// The following define the bit fields in the ADC_TMLB register. +// +//***************************************************************************** +#define ADC_TMLB_LB 0x00000001 // Loopback control signals + +//***************************************************************************** +// +// The following define the bit fields in the loopback ADC data. +// +//***************************************************************************** +#define ADC_LB_CNT_MASK 0x000003C0 // Sample counter mask +#define ADC_LB_CONT 0x00000020 // Continuation sample +#define ADC_LB_DIFF 0x00000010 // Differential sample +#define ADC_LB_TS 0x00000008 // Temperature sensor sample +#define ADC_LB_MUX_MASK 0x00000007 // Input channel number mask +#define ADC_LB_CNT_SHIFT 6 // Sample counter shift +#define ADC_LB_MUX_SHIFT 0 // Input channel number shift + +#endif // __HW_ADC_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/hw_comp.h b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/hw_comp.h new file mode 100644 index 000000000..991b7a083 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/hw_comp.h @@ -0,0 +1,118 @@ +//***************************************************************************** +// +// hw_comp.h - Macros used when accessing the comparator hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_COMP_H__ +#define __HW_COMP_H__ + +//***************************************************************************** +// +// The following define the offsets of the comparator registers. +// +//***************************************************************************** +#define COMP_O_MIS 0x00000000 // Interrupt status register +#define COMP_O_RIS 0x00000004 // Raw interrupt status register +#define COMP_O_INTEN 0x00000008 // Interrupt enable register +#define COMP_O_REFCTL 0x00000010 // Reference voltage control reg. +#define COMP_O_ACSTAT0 0x00000020 // Comp0 status register +#define COMP_O_ACCTL0 0x00000024 // Comp0 control register +#define COMP_O_ACSTAT1 0x00000040 // Comp1 status register +#define COMP_O_ACCTL1 0x00000044 // Comp1 control register +#define COMP_O_ACSTAT2 0x00000060 // Comp2 status register +#define COMP_O_ACCTL2 0x00000064 // Comp2 control register + +//***************************************************************************** +// +// The following define the bit fields in the COMP_MIS, COMP_RIS, and +// COMP_INTEN registers. +// +//***************************************************************************** +#define COMP_INT_2 0x00000004 // Comp2 interrupt +#define COMP_INT_1 0x00000002 // Comp1 interrupt +#define COMP_INT_0 0x00000001 // Comp0 interrupt + +//***************************************************************************** +// +// The following define the bit fields in the COMP_REFCTL register. +// +//***************************************************************************** +#define COMP_REFCTL_EN 0x00000200 // Reference voltage enable +#define COMP_REFCTL_RNG 0x00000100 // Reference voltage range +#define COMP_REFCTL_VREF_MASK 0x0000000F // Reference voltage select mask +#define COMP_REFCTL_VREF_SHIFT 0 + +//***************************************************************************** +// +// The following define the bit fields in the COMP_ACSTAT0, COMP_ACSTAT1, and +// COMP_ACSTAT2 registers. +// +//***************************************************************************** +#define COMP_ACSTAT_OVAL 0x00000002 // Comparator output value + +//***************************************************************************** +// +// The following define the bit fields in the COMP_ACCTL0, COMP_ACCTL1, and +// COMP_ACCTL2 registers. +// +//***************************************************************************** +#define COMP_ACCTL_TMASK 0x00000800 // Trigger enable +#define COMP_ACCTL_ASRCP_MASK 0x00000600 // Vin+ source select mask +#define COMP_ACCTL_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin +#define COMP_ACCTL_ASRCP_PIN0 0x00000200 // Comp0+ pin +#define COMP_ACCTL_ASRCP_REF 0x00000400 // Internal voltage reference +#define COMP_ACCTL_ASRCP_RES 0x00000600 // Reserved +#define COMP_ACCTL_OEN 0x00000100 // Comparator output enable +#define COMP_ACCTL_TSVAL 0x00000080 // Trigger polarity select +#define COMP_ACCTL_TSEN_MASK 0x00000060 // Trigger sense mask +#define COMP_ACCTL_TSEN_LEVEL 0x00000000 // Trigger is level sense +#define COMP_ACCTL_TSEN_FALL 0x00000020 // Trigger is falling edge +#define COMP_ACCTL_TSEN_RISE 0x00000040 // Trigger is rising edge +#define COMP_ACCTL_TSEN_BOTH 0x00000060 // Trigger is both edges +#define COMP_ACCTL_ISLVAL 0x00000010 // Interrupt polarity select +#define COMP_ACCTL_ISEN_MASK 0x0000000C // Interrupt sense mask +#define COMP_ACCTL_ISEN_LEVEL 0x00000000 // Interrupt is level sense +#define COMP_ACCTL_ISEN_FALL 0x00000004 // Interrupt is falling edge +#define COMP_ACCTL_ISEN_RISE 0x00000008 // Interrupt is rising edge +#define COMP_ACCTL_ISEN_BOTH 0x0000000C // Interrupt is both edges +#define COMP_ACCTL_CINV 0x00000002 // Comparator output invert + +//***************************************************************************** +// +// The following define the reset values for the comparator registers. +// +//***************************************************************************** +#define COMP_RV_MIS 0x00000000 // Interrupt status register +#define COMP_RV_RIS 0x00000000 // Raw interrupt status register +#define COMP_RV_INTEN 0x00000000 // Interrupt enable register +#define COMP_RV_REFCTL 0x00000000 // Reference voltage control reg. +#define COMP_RV_ACSTAT0 0x00000000 // Comp0 status register +#define COMP_RV_ACCTL0 0x00000000 // Comp0 control register +#define COMP_RV_ACSTAT1 0x00000000 // Comp1 status register +#define COMP_RV_ACCTL1 0x00000000 // Comp1 control register +#define COMP_RV_ACSTAT2 0x00000000 // Comp2 status register +#define COMP_RV_ACCTL2 0x00000000 // Comp2 control register + +#endif // __HW_COMP_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/hw_flash.h b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/hw_flash.h new file mode 100644 index 000000000..53128b436 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/hw_flash.h @@ -0,0 +1,139 @@ +//***************************************************************************** +// +// hw_flash.h - Macros used when accessing the flash controller. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_FLASH_H__ +#define __HW_FLASH_H__ + +//***************************************************************************** +// +// The following define the offsets of the FLASH registers. +// +//***************************************************************************** +#define FLASH_FMA 0x400FD000 // Memory address register +#define FLASH_FMD 0x400FD004 // Memory data register +#define FLASH_FMC 0x400FD008 // Memory control register +#define FLASH_FCRIS 0x400FD00c // Raw interrupt status register +#define FLASH_FCIM 0x400FD010 // Interrupt mask register +#define FLASH_FCMISC 0x400FD014 // Interrupt status register +#define FLASH_FMPRE 0x400FE130 // FLASH read protect register +#define FLASH_FMPPE 0x400FE134 // FLASH program protect register +#define FLASH_USECRL 0x400FE140 // uSec reload register + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FMC register. +// +//***************************************************************************** +#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask +#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key +#define FLASH_FMC_COMT 0x00000008 // Commit user register +#define FLASH_FMC_MERASE 0x00000004 // Mass erase FLASH +#define FLASH_FMC_ERASE 0x00000002 // Erase FLASH page +#define FLASH_FMC_WRITE 0x00000001 // Write FLASH word + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FCRIS register. +// +//***************************************************************************** +#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status +#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FCIM register. +// +//***************************************************************************** +#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask +#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FMIS register. +// +//***************************************************************************** +#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status +#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FMPRE and FLASH_FMPPE +// registers. +// +//***************************************************************************** +#define FLASH_FMP_BLOCK_31 0x80000000 // Enable for block 31 +#define FLASH_FMP_BLOCK_30 0x40000000 // Enable for block 30 +#define FLASH_FMP_BLOCK_29 0x20000000 // Enable for block 29 +#define FLASH_FMP_BLOCK_28 0x10000000 // Enable for block 28 +#define FLASH_FMP_BLOCK_27 0x08000000 // Enable for block 27 +#define FLASH_FMP_BLOCK_26 0x04000000 // Enable for block 26 +#define FLASH_FMP_BLOCK_25 0x02000000 // Enable for block 25 +#define FLASH_FMP_BLOCK_24 0x01000000 // Enable for block 24 +#define FLASH_FMP_BLOCK_23 0x00800000 // Enable for block 23 +#define FLASH_FMP_BLOCK_22 0x00400000 // Enable for block 22 +#define FLASH_FMP_BLOCK_21 0x00200000 // Enable for block 21 +#define FLASH_FMP_BLOCK_20 0x00100000 // Enable for block 20 +#define FLASH_FMP_BLOCK_19 0x00080000 // Enable for block 19 +#define FLASH_FMP_BLOCK_18 0x00040000 // Enable for block 18 +#define FLASH_FMP_BLOCK_17 0x00020000 // Enable for block 17 +#define FLASH_FMP_BLOCK_16 0x00010000 // Enable for block 16 +#define FLASH_FMP_BLOCK_15 0x00008000 // Enable for block 15 +#define FLASH_FMP_BLOCK_14 0x00004000 // Enable for block 14 +#define FLASH_FMP_BLOCK_13 0x00002000 // Enable for block 13 +#define FLASH_FMP_BLOCK_12 0x00001000 // Enable for block 12 +#define FLASH_FMP_BLOCK_11 0x00000800 // Enable for block 11 +#define FLASH_FMP_BLOCK_10 0x00000400 // Enable for block 10 +#define FLASH_FMP_BLOCK_9 0x00000200 // Enable for block 9 +#define FLASH_FMP_BLOCK_8 0x00000100 // Enable for block 8 +#define FLASH_FMP_BLOCK_7 0x00000080 // Enable for block 7 +#define FLASH_FMP_BLOCK_6 0x00000040 // Enable for block 6 +#define FLASH_FMP_BLOCK_5 0x00000020 // Enable for block 5 +#define FLASH_FMP_BLOCK_4 0x00000010 // Enable for block 4 +#define FLASH_FMP_BLOCK_3 0x00000008 // Enable for block 3 +#define FLASH_FMP_BLOCK_2 0x00000004 // Enable for block 2 +#define FLASH_FMP_BLOCK_1 0x00000002 // Enable for block 1 +#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0 + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_USECRL register. +// +//***************************************************************************** +#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec +#define FLASH_USECRL_SHIFT 0 + +//***************************************************************************** +// +// The erase size is the size of the FLASH block that is erased by an erase +// operation, and the protect size is the size of the FLASH block that is +// protected by each protection register. +// +//***************************************************************************** +#define FLASH_ERASE_SIZE 0x00000400 +#define FLASH_PROTECT_SIZE 0x00000800 + +#endif // __HW_FLASH_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/hw_gpio.h b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/hw_gpio.h new file mode 100644 index 000000000..bf25d3f5a --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/hw_gpio.h @@ -0,0 +1,103 @@ +//***************************************************************************** +// +// hw_gpio.h - Defines and Macros for GPIO hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_GPIO_H__ +#define __HW_GPIO_H__ + +//***************************************************************************** +// +// GPIO Register Offsets. +// +//***************************************************************************** +#define GPIO_O_DATA 0x00000000 // Data register. +#define GPIO_O_DIR 0x00000400 // Data direction register. +#define GPIO_O_IS 0x00000404 // Interrupt sense register. +#define GPIO_O_IBE 0x00000408 // Interrupt both edges register. +#define GPIO_O_IEV 0x0000040C // Intterupt event register. +#define GPIO_O_IM 0x00000410 // Interrupt mask register. +#define GPIO_O_RIS 0x00000414 // Raw interrupt status register. +#define GPIO_O_MIS 0x00000418 // Masked interrupt status reg. +#define GPIO_O_ICR 0x0000041C // Interrupt clear register. +#define GPIO_O_AFSEL 0x00000420 // Mode control select register. +#define GPIO_O_DR2R 0x00000500 // 2ma drive select register. +#define GPIO_O_DR4R 0x00000504 // 4ma drive select register. +#define GPIO_O_DR8R 0x00000508 // 8ma drive select register. +#define GPIO_O_ODR 0x0000050C // Open drain select register. +#define GPIO_O_PUR 0x00000510 // Pull up select register. +#define GPIO_O_PDR 0x00000514 // Pull down select register. +#define GPIO_O_SLR 0x00000518 // Slew rate control enable reg. +#define GPIO_O_DEN 0x0000051C // Digital input enable register. +#define GPIO_O_PeriphID4 0x00000FD0 // +#define GPIO_O_PeriphID5 0x00000FD4 // +#define GPIO_O_PeriphID6 0x00000FD8 // +#define GPIO_O_PeriphID7 0x00000FDC // +#define GPIO_O_PeriphID0 0x00000FE0 // +#define GPIO_O_PeriphID1 0x00000FE4 // +#define GPIO_O_PeriphID2 0x00000FE8 // +#define GPIO_O_PeriphID3 0x00000FEC // +#define GPIO_O_PCellID0 0x00000FF0 // +#define GPIO_O_PCellID1 0x00000FF4 // +#define GPIO_O_PCellID2 0x00000FF8 // +#define GPIO_O_PCellID3 0x00000FFC // + +//***************************************************************************** +// +// GPIO Register reset values. +// +//***************************************************************************** +#define GPIO_RV_DATA 0x00000000 // Data register reset value. +#define GPIO_RV_DIR 0x00000000 // Data direction reg RV. +#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV. +#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV. +#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV. +#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV. +#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV. +#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV. +#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV. +#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV. +#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV. +#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV. +#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV. +#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV. +#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV. +#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV. +#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV. +#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV. +#define GPIO_RV_PeriphID4 0x00000000 // +#define GPIO_RV_PeriphID5 0x00000000 // +#define GPIO_RV_PeriphID6 0x00000000 // +#define GPIO_RV_PeriphID7 0x00000000 // +#define GPIO_RV_PeriphID0 0x00000061 // +#define GPIO_RV_PeriphID1 0x00000010 // +#define GPIO_RV_PeriphID2 0x00000004 // +#define GPIO_RV_PeriphID3 0x00000000 // +#define GPIO_RV_PCellID0 0x0000000D // +#define GPIO_RV_PCellID1 0x000000F0 // +#define GPIO_RV_PCellID2 0x00000005 // +#define GPIO_RV_PCellID3 0x000000B1 // + +#endif // __HW_GPIO_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/hw_i2c.h b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/hw_i2c.h new file mode 100644 index 000000000..2c9f46dab --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/hw_i2c.h @@ -0,0 +1,197 @@ +//***************************************************************************** +// +// hw_i2c.h - Macros used when accessing the I2C master and slave hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_I2C_H__ +#define __HW_I2C_H__ + +//***************************************************************************** +// +// The following defines the offset between the I2C master and slave registers. +// +//***************************************************************************** +#define I2C_O_SLAVE 0x00000800 // Offset from master to slave + +//***************************************************************************** +// +// The following define the offsets of the I2C master registers. +// +//***************************************************************************** +#define I2C_MASTER_O_SA 0x00000000 // Slave address register +#define I2C_MASTER_O_CS 0x00000004 // Control and Status register +#define I2C_MASTER_O_DR 0x00000008 // Data register +#define I2C_MASTER_O_TPR 0x0000000C // Timer period register +#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register +#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register +#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg +#define I2C_MASTER_O_MICR 0x0000001c // Interrupt clear register +#define I2C_MASTER_O_CR 0x00000020 // Configuration register + +//***************************************************************************** +// +// The following define the offsets of the I2C slave registers. +// +//***************************************************************************** +#define I2C_SLAVE_O_OAR 0x00000000 // Own address register +#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register +#define I2C_SLAVE_O_DR 0x00000008 // Data register +#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register +#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register +#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg +#define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register + +//***************************************************************************** +// +// The followng define the bit fields in the I2C master slave address register. +// +//***************************************************************************** +#define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address +#define I2C_MASTER_SA_RS 0x00000001 // Receive/send +#define I2C_MASTER_SA_SA_SHIFT 1 + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Control and Status +// register. +// +//***************************************************************************** +#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde +#define I2C_MASTER_CS_STOP 0x00000004 // Stop +#define I2C_MASTER_CS_START 0x00000002 // Start +#define I2C_MASTER_CS_RUN 0x00000001 // Run +#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy +#define I2C_MASTER_CS_IDLE 0x00000020 // Idle +#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration +#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged +#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged +#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred +#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data +#define I2C_MASTER_CS_ERR_MASK 0x0000001C + +//***************************************************************************** +// +// The following define values used in determining the contents of the I2C +// Master Timer Period register. +// +//***************************************************************************** +#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period +#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period +#define I2C_MASTER_TPR_SCL (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP) +#define I2C_SCL_STANDARD 100000 // SCL standard frequency +#define I2C_SCL_FAST 400000 // SCL fast frequency + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Interrupt Mask +// register. +// +//***************************************************************************** +#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Raw Interrupt Status +// register. +// +//***************************************************************************** +#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Masked Interrupt +// Status register. +// +//***************************************************************************** +#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Interrupt Clear +// register. +// +//***************************************************************************** +#define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Configuration +// register. +// +//***************************************************************************** +#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable +#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable +#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Own Address register. +// +//***************************************************************************** +#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Control/Status +// register. +// +//***************************************************************************** +#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device +#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received +#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Interrupt Mask +// register. +// +//***************************************************************************** +#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Raw Interrupt Status +// register. +// +//***************************************************************************** +#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Masked Interrupt +// Status register. +// +//***************************************************************************** +#define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Interrupt Clear +// register. +// +//***************************************************************************** +#define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear + +#endif // __HW_I2C_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/hw_ints.h b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/hw_ints.h new file mode 100644 index 000000000..2204a2c07 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/hw_ints.h @@ -0,0 +1,97 @@ +//***************************************************************************** +// +// hw_ints.h - Macros that define the interrupt assignment on Stellaris. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_INTS_H__ +#define __HW_INTS_H__ + +//***************************************************************************** +// +// The following define the fault assignments. +// +//***************************************************************************** +#define FAULT_NMI 2 // NMI fault +#define FAULT_HARD 3 // Hard fault +#define FAULT_MPU 4 // MPU fault +#define FAULT_BUS 5 // Bus fault +#define FAULT_USAGE 6 // Usage fault +#define FAULT_SVCALL 11 // SVCall +#define FAULT_DEBUG 12 // Debug monitor +#define FAULT_PENDSV 14 // PendSV +#define FAULT_SYSTICK 15 // System Tick + +//***************************************************************************** +// +// The following define the interrupt assignments. +// +//***************************************************************************** +#define INT_GPIOA 16 // GPIO Port A +#define INT_GPIOB 17 // GPIO Port B +#define INT_GPIOC 18 // GPIO Port C +#define INT_GPIOD 19 // GPIO Port D +#define INT_GPIOE 20 // GPIO Port E +#define INT_UART0 21 // UART0 Rx and Tx +#define INT_UART1 22 // UART1 Rx and Tx +#define INT_SSI 23 // SSI Rx and Tx +#define INT_I2C 24 // I2C Master and Slave +#define INT_PWM_FAULT 25 // PWM Fault +#define INT_PWM0 26 // PWM Generator 0 +#define INT_PWM1 27 // PWM Generator 1 +#define INT_PWM2 28 // PWM Generator 2 +#define INT_QEI 29 // Quadrature Encoder +#define INT_ADC0 30 // ADC Sequence 0 +#define INT_ADC1 31 // ADC Sequence 1 +#define INT_ADC2 32 // ADC Sequence 2 +#define INT_ADC3 33 // ADC Sequence 3 +#define INT_WATCHDOG 34 // Watchdog timer +#define INT_TIMER0A 35 // Timer 0 subtimer A +#define INT_TIMER0B 36 // Timer 0 subtimer B +#define INT_TIMER1A 37 // Timer 1 subtimer A +#define INT_TIMER1B 38 // Timer 1 subtimer B +#define INT_TIMER2A 39 // Timer 2 subtimer A +#define INT_TIMER2B 40 // Timer 2 subtimer B +#define INT_COMP0 41 // Analog Comparator 0 +#define INT_COMP1 42 // Analog Comparator 1 +#define INT_COMP2 43 // Analog Comparator 2 +#define INT_SYSCTL 44 // System Control (PLL, OSC, BO) +#define INT_FLASH 45 // FLASH Control + +//***************************************************************************** +// +// The total number of interrupts. +// +//***************************************************************************** +#define NUM_INTERRUPTS 46 + +//***************************************************************************** +// +// The total number of priority levels. +// +//***************************************************************************** +#define NUM_PRIORITY 8 +#define NUM_PRIORITY_BITS 3 + +#endif // __HW_INTS_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/hw_memmap.h b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/hw_memmap.h new file mode 100644 index 000000000..2b11f3513 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/hw_memmap.h @@ -0,0 +1,64 @@ +//***************************************************************************** +// +// hw_memmap.h - Macros defining the memory map of Stellaris. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_MEMMAP_H__ +#define __HW_MEMMAP_H__ + +//***************************************************************************** +// +// The following define the base address of the memories and peripherals. +// +//***************************************************************************** +#define FLASH_BASE 0x00000000 // FLASH memory +#define SRAM_BASE 0x20000000 // SRAM memory +#define WATCHDOG_BASE 0x40000000 // Watchdog +#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A +#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B +#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C +#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D +#define SSI_BASE 0x40008000 // SSI +#define UART0_BASE 0x4000C000 // UART0 +#define UART1_BASE 0x4000D000 // UART1 +#define I2C_MASTER_BASE 0x40020000 // I2C Master +#define I2C_SLAVE_BASE 0x40020800 // I2C Slave +#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E +#define PWM_BASE 0x40028000 // PWM +#define QEI_BASE 0x4002C000 // QEI +#define TIMER0_BASE 0x40030000 // Timer0 +#define TIMER1_BASE 0x40031000 // Timer1 +#define TIMER2_BASE 0x40032000 // Timer2 +#define ADC_BASE 0x40038000 // ADC +#define COMP_BASE 0x4003C000 // Analog comparators +#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller +#define SYSCTL_BASE 0x400FE000 // System Control +#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell +#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace +#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint +#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl +#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit + +#endif // __HW_MEMMAP_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/hw_nvic.h b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/hw_nvic.h new file mode 100644 index 000000000..6598ef88b --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/hw_nvic.h @@ -0,0 +1,830 @@ +//***************************************************************************** +// +// hw_nvic.h - Macros used when accessing the NVIC hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_NVIC_H__ +#define __HW_NVIC_H__ + +//***************************************************************************** +// +// The following define the addresses of the NVIC registers. +// +//***************************************************************************** +#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg. +#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg. +#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register +#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register +#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg. +#define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register +#define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg. +#define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register +#define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg. +#define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register +#define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register +#define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register +#define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register +#define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register +#define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register +#define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register +#define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register +#define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register +#define NVIC_CPUID 0xE000ED00 // CPUID Base Register +#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register +#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register +#define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg. +#define NVIC_SYS_CTRL 0xE000ED10 // System Control Register +#define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register +#define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority +#define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority +#define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority +#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State +#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg. +#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register +#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register +#define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register +#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register +#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register +#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register +#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register +#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register +#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg. +#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg. +#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select +#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data +#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control +#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg. + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_INT_TYPE register. +// +//***************************************************************************** +#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) +#define NVIC_INT_TYPE_LINES_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_CTRL register. +// +//***************************************************************************** +#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag +#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source +#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable +#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_RELOAD register. +// +//***************************************************************************** +#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value +#define NVIC_ST_RELOAD_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_CURRENT register. +// +//***************************************************************************** +#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value +#define NVIC_ST_CURRENT_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_CAL register. +// +//***************************************************************************** +#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock +#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew +#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value +#define NVIC_ST_CAL_ONEMS_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_EN0 register. +// +//***************************************************************************** +#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable +#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable +#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable +#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable +#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable +#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable +#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable +#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable +#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable +#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable +#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable +#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable +#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable +#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable +#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable +#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable +#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable +#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable +#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable +#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable +#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable +#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable +#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable +#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable +#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable +#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable +#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable +#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable +#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable +#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable +#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable +#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DIS0 register. +// +//***************************************************************************** +#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable +#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable +#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable +#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable +#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable +#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable +#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable +#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable +#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable +#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable +#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable +#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable +#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable +#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable +#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable +#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable +#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable +#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable +#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable +#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable +#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable +#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable +#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable +#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable +#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable +#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable +#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable +#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable +#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable +#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable +#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable +#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PEND0 register. +// +//***************************************************************************** +#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend +#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend +#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend +#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend +#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend +#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend +#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend +#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend +#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend +#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend +#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend +#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend +#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend +#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend +#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend +#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend +#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend +#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend +#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend +#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend +#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend +#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend +#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend +#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend +#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend +#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend +#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend +#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend +#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend +#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend +#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend +#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_UNPEND0 register. +// +//***************************************************************************** +#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend +#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend +#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend +#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend +#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend +#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend +#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend +#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend +#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend +#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend +#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend +#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend +#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend +#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend +#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend +#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend +#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend +#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend +#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend +#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend +#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend +#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend +#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend +#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend +#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend +#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend +#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend +#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend +#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend +#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend +#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend +#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ACTIVE0 register. +// +//***************************************************************************** +#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active +#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active +#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active +#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active +#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active +#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active +#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active +#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active +#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active +#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active +#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active +#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active +#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active +#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active +#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active +#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active +#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active +#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active +#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active +#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active +#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active +#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active +#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active +#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active +#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active +#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active +#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active +#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active +#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active +#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active +#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active +#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI0 register. +// +//***************************************************************************** +#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask +#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask +#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask +#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask +#define NVIC_PRI0_INT3_S 24 +#define NVIC_PRI0_INT2_S 16 +#define NVIC_PRI0_INT1_S 8 +#define NVIC_PRI0_INT0_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI1 register. +// +//***************************************************************************** +#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask +#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask +#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask +#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask +#define NVIC_PRI1_INT7_S 24 +#define NVIC_PRI1_INT6_S 16 +#define NVIC_PRI1_INT5_S 8 +#define NVIC_PRI1_INT4_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI2 register. +// +//***************************************************************************** +#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask +#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask +#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask +#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask +#define NVIC_PRI2_INT11_S 24 +#define NVIC_PRI2_INT10_S 16 +#define NVIC_PRI2_INT9_S 8 +#define NVIC_PRI2_INT8_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI3 register. +// +//***************************************************************************** +#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask +#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask +#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask +#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask +#define NVIC_PRI3_INT15_S 24 +#define NVIC_PRI3_INT14_S 16 +#define NVIC_PRI3_INT13_S 8 +#define NVIC_PRI3_INT12_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI4 register. +// +//***************************************************************************** +#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask +#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask +#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask +#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask +#define NVIC_PRI4_INT19_S 24 +#define NVIC_PRI4_INT18_S 16 +#define NVIC_PRI4_INT17_S 8 +#define NVIC_PRI4_INT16_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI5 register. +// +//***************************************************************************** +#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask +#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask +#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask +#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask +#define NVIC_PRI5_INT23_S 24 +#define NVIC_PRI5_INT22_S 16 +#define NVIC_PRI5_INT21_S 8 +#define NVIC_PRI5_INT20_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI6 register. +// +//***************************************************************************** +#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask +#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask +#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask +#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask +#define NVIC_PRI6_INT27_S 24 +#define NVIC_PRI6_INT26_S 16 +#define NVIC_PRI6_INT25_S 8 +#define NVIC_PRI6_INT24_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI7 register. +// +//***************************************************************************** +#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask +#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask +#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask +#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask +#define NVIC_PRI7_INT31_S 24 +#define NVIC_PRI7_INT30_S 16 +#define NVIC_PRI7_INT29_S 8 +#define NVIC_PRI7_INT28_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_CPUID register. +// +//***************************************************************************** +#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer +#define NVIC_CPUID_VAR_M 0x00F00000 // Variant +#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number +#define NVIC_CPUID_REV_M 0x0000000F // Revision + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_INT_CTRL register. +// +//***************************************************************************** +#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI +#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV +#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV +#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling +#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending +#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception +#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base +#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception +#define NVIC_INT_CTRL_VEC_PEN_S 12 +#define NVIC_INT_CTRL_VEC_ACT_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_VTABLE register. +// +//***************************************************************************** +#define NVIC_VTABLE_BASE 0x20000000 // Vector table base +#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset +#define NVIC_VTABLE_OFFSET_S 8 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_APINT register. +// +//***************************************************************************** +#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask +#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key +#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess +#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group +#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split +#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split +#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split +#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split +#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split +#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split +#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split +#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split +#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request +#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info +#define NVIC_APINT_VECT_RESET 0x00000001 // System reset + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend +#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable +#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_CFG_CTRL register. +// +//***************************************************************************** +#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault +#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0 +#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access +#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger +#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger +#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_PRI1 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler +#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler +#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler +#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler +#define NVIC_SYS_PRI1_USAGE_S 16 +#define NVIC_SYS_PRI1_BUS_S 8 +#define NVIC_SYS_PRI1_MEM_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_PRI2 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler +#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers +#define NVIC_SYS_PRI2_SVC_S 24 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_PRI3 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler +#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler +#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler +#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler +#define NVIC_SYS_PRI3_TICK_S 24 +#define NVIC_SYS_PRI3_PENDSV_S 16 +#define NVIC_SYS_PRI3_DEBUG_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_HND_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable +#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable +#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable +#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended +#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended +#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active +#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active +#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active +#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active +#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active +#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active +#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_FAULT_STAT register. +// +//***************************************************************************** +#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault +#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault +#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault +#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault +#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault +#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault +#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid +#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault +#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault +#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error +#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error +#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault +#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid +#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation +#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation +#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation +#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_HFAULT_STAT register. +// +//***************************************************************************** +#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event +#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler +#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DEBUG_STAT register. +// +//***************************************************************************** +#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted +#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch +#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match +#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction +#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MM_ADDR register. +// +//***************************************************************************** +#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address +#define NVIC_MM_ADDR_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_FAULT_ADDR register. +// +//***************************************************************************** +#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address +#define NVIC_FAULT_ADDR_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_EXC_STACK register. +// +//***************************************************************************** +#define NVIC_EXC_STACK_DEEP 0x00000001 // Exception stack + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_EXC_NUM register. +// +//***************************************************************************** +#define NVIC_EXC_NUM_M 0x000003FF // Exception number +#define NVIC_EXC_NUM_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_COPRO register. +// +//***************************************************************************** +#define NVIC_COPRO_15_M 0xC0000000 // Coprocessor 15 access mask +#define NVIC_COPRO_15_DENIED 0x00000000 // Coprocessor 15 access denied +#define NVIC_COPRO_15_PRIV 0x40000000 // Coprocessor 15 privileged addess +#define NVIC_COPRO_15_FULL 0xC0000000 // Coprocessor 15 full access +#define NVIC_COPRO_14_M 0x30000000 // Coprocessor 14 access mask +#define NVIC_COPRO_14_DENIED 0x00000000 // Coprocessor 14 access denied +#define NVIC_COPRO_14_PRIV 0x10000000 // Coprocessor 14 privileged addess +#define NVIC_COPRO_14_FULL 0x30000000 // Coprocessor 14 full access +#define NVIC_COPRO_13_M 0x0C000000 // Coprocessor 13 access mask +#define NVIC_COPRO_13_DENIED 0x00000000 // Coprocessor 13 access denied +#define NVIC_COPRO_13_PRIV 0x04000000 // Coprocessor 13 privileged addess +#define NVIC_COPRO_13_FULL 0x0C000000 // Coprocessor 13 full access +#define NVIC_COPRO_12_M 0x03000000 // Coprocessor 12 access mask +#define NVIC_COPRO_12_DENIED 0x00000000 // Coprocessor 12 access denied +#define NVIC_COPRO_12_PRIV 0x01000000 // Coprocessor 12 privileged addess +#define NVIC_COPRO_12_FULL 0x03000000 // Coprocessor 12 full access +#define NVIC_COPRO_11_M 0x00C00000 // Coprocessor 11 access mask +#define NVIC_COPRO_11_DENIED 0x00000000 // Coprocessor 11 access denied +#define NVIC_COPRO_11_PRIV 0x00400000 // Coprocessor 11 privileged addess +#define NVIC_COPRO_11_FULL 0x00C00000 // Coprocessor 11 full access +#define NVIC_COPRO_10_M 0x00300000 // Coprocessor 10 access mask +#define NVIC_COPRO_10_DENIED 0x00000000 // Coprocessor 10 access denied +#define NVIC_COPRO_10_PRIV 0x00100000 // Coprocessor 10 privileged addess +#define NVIC_COPRO_10_FULL 0x00300000 // Coprocessor 10 full access +#define NVIC_COPRO_9_M 0x000C0000 // Coprocessor 9 access mask +#define NVIC_COPRO_9_DENIED 0x00000000 // Coprocessor 9 access denied +#define NVIC_COPRO_9_PRIV 0x00040000 // Coprocessor 9 privileged addess +#define NVIC_COPRO_9_FULL 0x000C0000 // Coprocessor 9 full access +#define NVIC_COPRO_8_M 0x00030000 // Coprocessor 8 access mask +#define NVIC_COPRO_8_DENIED 0x00000000 // Coprocessor 8 access denied +#define NVIC_COPRO_8_PRIV 0x00010000 // Coprocessor 8 privileged addess +#define NVIC_COPRO_8_FULL 0x00030000 // Coprocessor 8 full access +#define NVIC_COPRO_7_M 0x0000C000 // Coprocessor 7 access mask +#define NVIC_COPRO_7_DENIED 0x00000000 // Coprocessor 7 access denied +#define NVIC_COPRO_7_PRIV 0x00004000 // Coprocessor 7 privileged addess +#define NVIC_COPRO_7_FULL 0x0000C000 // Coprocessor 7 full access +#define NVIC_COPRO_6_M 0x00003000 // Coprocessor 6 access mask +#define NVIC_COPRO_6_DENIED 0x00000000 // Coprocessor 6 access denied +#define NVIC_COPRO_6_PRIV 0x00001000 // Coprocessor 6 privileged addess +#define NVIC_COPRO_6_FULL 0x00003000 // Coprocessor 6 full access +#define NVIC_COPRO_5_M 0x00000C00 // Coprocessor 5 access mask +#define NVIC_COPRO_5_DENIED 0x00000000 // Coprocessor 5 access denied +#define NVIC_COPRO_5_PRIV 0x00000400 // Coprocessor 5 privileged addess +#define NVIC_COPRO_5_FULL 0x00000C00 // Coprocessor 5 full access +#define NVIC_COPRO_4_M 0x00000300 // Coprocessor 4 access mask +#define NVIC_COPRO_4_DENIED 0x00000000 // Coprocessor 4 access denied +#define NVIC_COPRO_4_PRIV 0x00000100 // Coprocessor 4 privileged addess +#define NVIC_COPRO_4_FULL 0x00000300 // Coprocessor 4 full access +#define NVIC_COPRO_3_M 0x000000C0 // Coprocessor 3 access mask +#define NVIC_COPRO_3_DENIED 0x00000000 // Coprocessor 3 access denied +#define NVIC_COPRO_3_PRIV 0x00000040 // Coprocessor 3 privileged addess +#define NVIC_COPRO_3_FULL 0x000000C0 // Coprocessor 3 full access +#define NVIC_COPRO_2_M 0x00000030 // Coprocessor 2 access mask +#define NVIC_COPRO_2_DENIED 0x00000000 // Coprocessor 2 access denied +#define NVIC_COPRO_2_PRIV 0x00000010 // Coprocessor 2 privileged addess +#define NVIC_COPRO_2_FULL 0x00000030 // Coprocessor 2 full access +#define NVIC_COPRO_1_M 0x0000000C // Coprocessor 1 access mask +#define NVIC_COPRO_1_DENIED 0x00000000 // Coprocessor 1 access denied +#define NVIC_COPRO_1_PRIV 0x00000004 // Coprocessor 1 privileged addess +#define NVIC_COPRO_1_FULL 0x0000000C // Coprocessor 1 full access +#define NVIC_COPRO_0_M 0x00000003 // Coprocessor 0 access mask +#define NVIC_COPRO_0_DENIED 0x00000000 // Coprocessor 0 access denied +#define NVIC_COPRO_0_PRIV 0x00000001 // Coprocessor 0 privileged addess +#define NVIC_COPRO_0_FULL 0x00000003 // Coprocessor 0 full access + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_TYPE register. +// +//***************************************************************************** +#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions +#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions +#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU +#define NVIC_MPU_TYPE_IREGION_S 16 +#define NVIC_MPU_TYPE_DREGION_S 8 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_CTRL register. +// +//***************************************************************************** +#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults +#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_NUMBER register. +// +//***************************************************************************** +#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access +#define NVIC_MPU_NUMBER_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_BASE register. +// +//***************************************************************************** +#define NVIC_MPU_BASE_ADDR_M 0xFFFFFF00 // Base address +#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid +#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number +#define NVIC_MPU_BASE_ADDR_S 8 +#define NVIC_MPU_BASE_REGION_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_ATTR register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR_ATTRS 0xFFFF0000 // Attributes +#define NVIC_MPU_ATTR_SRD 0x0000FF00 // Sub-region disable +#define NVIC_MPU_ATTR_SZENABLE 0x000000FF // Region size + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_CTRL register. +// +//***************************************************************************** +#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask +#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key +#define NVIC_DBG_CTRL_MON_PEND 0x00008000 // Pend the monitor +#define NVIC_DBG_CTRL_MON_REQ 0x00004000 // Monitor request +#define NVIC_DBG_CTRL_MON_EN 0x00002000 // Debug monitor enable +#define NVIC_DBG_CTRL_MONSTEP 0x00001000 // Monitor step the core +#define NVIC_DBG_CTRL_S_SLEEP 0x00000400 // Core is sleeping +#define NVIC_DBG_CTRL_S_HALT 0x00000200 // Core status on halt +#define NVIC_DBG_CTRL_S_REGRDY 0x00000100 // Register read/write available +#define NVIC_DBG_CTRL_S_LOCKUP 0x00000080 // Core is locked up +#define NVIC_DBG_CTRL_C_RESET 0x00000010 // Reset the core +#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping +#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core +#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core +#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_XFER register. +// +//***************************************************************************** +#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read +#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register +#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 +#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 +#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 +#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 +#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 +#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 +#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 +#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 +#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 +#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 +#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 +#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 +#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 +#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 +#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 +#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 +#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register +#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP +#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP +#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP +#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_DATA register. +// +//***************************************************************************** +#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache +#define NVIC_DBG_DATA_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_INT register. +// +//***************************************************************************** +#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault +#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors +#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error +#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state +#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check +#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error +#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault +#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status +#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset +#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending +#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SW_TRIG register. +// +//***************************************************************************** +#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger +#define NVIC_SW_TRIG_INTID_S 0 + +#endif // __HW_NVIC_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/hw_pwm.h b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/hw_pwm.h new file mode 100644 index 000000000..cc42015ab --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/hw_pwm.h @@ -0,0 +1,260 @@ +//***************************************************************************** +// +// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_PWM_H__ +#define __HW_PWM_H__ + +//***************************************************************************** +// +// PWM Module Register Offsets. +// +//***************************************************************************** +#define PWM_O_CTL 0x00000000 // PWM Master Control register +#define PWM_O_SYNC 0x00000004 // PWM Time Base Sync register +#define PWM_O_ENABLE 0x00000008 // PWM Output Enable register +#define PWM_O_INVERT 0x0000000C // PWM Output Inversion register +#define PWM_O_FAULT 0x00000010 // PWM Output Fault register +#define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable register +#define PWM_O_RIS 0x00000018 // PWM Interrupt Raw Status reg. +#define PWM_O_ISC 0x0000001C // PWM Interrupt Status register +#define PWM_O_STATUS 0x00000020 // PWM Status register + +//***************************************************************************** +// +// The following define the bit fields in the PWM Master Control register. +// +//***************************************************************************** +#define PWM_CTL_GLOBAL_SYNC2 0x00000004 // Global sync generator 2 +#define PWM_CTL_GLOBAL_SYNC1 0x00000002 // Global sync generator 1 +#define PWM_CTL_GLOBAL_SYNC0 0x00000001 // Global sync generator 0 + +//***************************************************************************** +// +// The following define the bit fields in the PWM Time Base Sync register. +// +//***************************************************************************** +#define PWM_SYNC_SYNC2 0x00000004 // Reset generator 2 counter +#define PWM_SYNC_SYNC1 0x00000002 // Reset generator 1 counter +#define PWM_SYNC_SYNC0 0x00000001 // Reset generator 0 counter + +//***************************************************************************** +// +// The following define the bit fields in the PWM Output Enable register. +// +//***************************************************************************** +#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 pin enable +#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 pin enable +#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 pin enable +#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 pin enable +#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 pin enable +#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 pin enable + +//***************************************************************************** +// +// The following define the bit fields in the PWM Inversion register. +// +//***************************************************************************** +#define PWM_INVERT_PWM5INV 0x00000020 // PWM5 pin invert +#define PWM_INVERT_PWM4INV 0x00000010 // PWM4 pin invert +#define PWM_INVERT_PWM3INV 0x00000008 // PWM3 pin invert +#define PWM_INVERT_PWM2INV 0x00000004 // PWM2 pin invert +#define PWM_INVERT_PWM1INV 0x00000002 // PWM1 pin invert +#define PWM_INVERT_PWM0INV 0x00000001 // PWM0 pin invert + +//***************************************************************************** +// +// The following define the bit fields in the PWM Fault register. +// +//***************************************************************************** +#define PWM_FAULT_FAULT5 0x00000020 // PWM5 pin fault +#define PWM_FAULT_FAULT4 0x00000010 // PWM5 pin fault +#define PWM_FAULT_FAULT3 0x00000008 // PWM5 pin fault +#define PWM_FAULT_FAULT2 0x00000004 // PWM5 pin fault +#define PWM_FAULT_FAULT1 0x00000002 // PWM5 pin fault +#define PWM_FAULT_FAULT0 0x00000001 // PWM5 pin fault + +//***************************************************************************** +// +// PWM Interrupt Register bit definitions. +// +//***************************************************************************** +#define PWM_INT_INTFAULT 0x00010000 // Fault interrupt pending + +//***************************************************************************** +// +// The following define the bit fields in the PWM Status register. +// +//***************************************************************************** +#define PWM_STATUS_FAULT 0x00000001 // Fault status + +//***************************************************************************** +// +// PWM Generator standard offsets. +// +//***************************************************************************** +#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base +#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base +#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base + +#define PWM_O_X_CTL 0x00000000 // Gen Control Reg +#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg +#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg +#define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg +#define PWM_O_X_LOAD 0x00000010 // Gen Load Reg +#define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg +#define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg +#define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg +#define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg +#define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg +#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg +#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg +#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg + +//***************************************************************************** +// +// PWM_X Control Register bit definitions. +// +//***************************************************************************** +#define PWM_X_CTL_ENABLE 0x00000001 // Master enable for gen block +#define PWM_X_CTL_MODE 0x00000002 // Counter mode, down or up/down +#define PWM_X_CTL_DEBUG 0x00000004 // Debug mode +#define PWM_X_CTL_LOADUPD 0x00000008 // Update mode for the load reg +#define PWM_X_CTL_CMPAUPD 0x00000010 // Update mode for comp A reg +#define PWM_X_CTL_CMPBUPD 0x00000020 // Update mode for comp B reg + +//***************************************************************************** +// +// PWM_X Interrupt/Trigger Enable Register bit definitions. +// +//***************************************************************************** +#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Int if COUNT = 0 +#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Int if COUNT = LOAD +#define PWM_X_INTEN_INTCMPAU 0x00000004 // Int if COUNT = CMPA U +#define PWM_X_INTEN_INTCMPAD 0x00000008 // Int if COUNT = CMPA D +#define PWM_X_INTEN_INTCMPBU 0x00000010 // Int if COUNT = CMPA U +#define PWM_X_INTEN_INTCMPBD 0x00000020 // Int if COUNT = CMPA D +#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trig if COUNT = 0 +#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trig if COUNT = LOAD +#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trig if COUNT = CMPA U +#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trig if COUNT = CMPA D +#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trig if COUNT = CMPA U +#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trig if COUNT = CMPA D + +//***************************************************************************** +// +// PWM_X Raw Interrupt Status Register bit definitions. +// +//***************************************************************************** +#define PWM_X_RIS_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 int +#define PWM_X_RIS_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD int +#define PWM_X_RIS_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U int +#define PWM_X_RIS_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D int +#define PWM_X_RIS_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U int +#define PWM_X_RIS_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D int + +//***************************************************************************** +// +// PWM_X Interrupt Status Register bit definitions. +// +//***************************************************************************** +#define PWM_X_INT_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 received +#define PWM_X_INT_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD rcvd +#define PWM_X_INT_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U rcvd +#define PWM_X_INT_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D rcvd +#define PWM_X_INT_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U rcvd +#define PWM_X_INT_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D rcvd + +//***************************************************************************** +// +// PWM_X Generator A/B Control Register bit definitions. +// +//***************************************************************************** +#define PWM_X_GEN_Y_ACTZERO 0x00000003 // Act PWM_X_COUNT = 0 +#define PWM_X_GEN_Y_ACTLOAD 0x0000000C // Act PWM_X_COUNT = PWM_X_LOAD +#define PWM_X_GEN_Y_ACTCMPAU 0x00000030 // Act PWM_X_COUNT = PWM_X_CMPA U +#define PWM_X_GEN_Y_ACTCMPAD 0x000000C0 // Act PWM_X_COUNT = PWM_X_CMPA D +#define PWM_X_GEN_Y_ACTCMPBU 0x00000300 // Act PWM_X_COUNT = PWM_X_CMPB U +#define PWM_X_GEN_Y_ACTCMPBD 0x00000C00 // Act PWM_X_COUNT = PWM_X_CMPB D + +//***************************************************************************** +// +// PWM_X Generator A/B Control Register action definitions. +// +//***************************************************************************** +#define PWM_GEN_ACT_NONE 0x0 // Do nothing +#define PWM_GEN_ACT_INV 0x1 // Invert the output signal +#define PWM_GEN_ACT_ZERO 0x2 // Set the output signal to zero +#define PWM_GEN_ACT_ONE 0x3 // Set the output signal to one +#define PWM_GEN_ACT_ZERO_SHIFT 0 // Shift amount for the zero action +#define PWM_GEN_ACT_LOAD_SHIFT 2 // Shift amount for the load action +#define PWM_GEN_ACT_A_UP_SHIFT 4 // Shift amount for the A up action +#define PWM_GEN_ACT_A_DN_SHIFT 6 // Shift amount for the A dn action +#define PWM_GEN_ACT_B_UP_SHIFT 8 // Shift amount for the B up action +#define PWM_GEN_ACT_B_DN_SHIFT 10 // Shift amount for the B dn action + +//***************************************************************************** +// +// PWM_X Dead Band Control Register bit definitions. +// +//***************************************************************************** +#define PWM_DBCTL_ENABLE 0x00000001 // Enable dead band insertion + +//***************************************************************************** +// +// PWM Register reset values. +// +//***************************************************************************** +#define PWM_RV_CTL 0x00000000 // Master control of the PWM module +#define PWM_RV_SYNC 0x00000000 // Counter synch for PWM generators +#define PWM_RV_ENABLE 0x00000000 // Master enable for the PWM + // output pins +#define PWM_RV_INVERT 0x00000000 // Inversion control for + // PWM output pins +#define PWM_RV_FAULT 0x00000000 // Fault handling for the PWM + // output pins +#define PWM_RV_INTEN 0x00000000 // Interrupt enable +#define PWM_RV_RIS 0x00000000 // Raw interrupt status +#define PWM_RV_ISC 0x00000000 // Interrupt status and clearing +#define PWM_RV_STATUS 0x00000000 // Status +#define PWM_RV_X_CTL 0x00000000 // Master control of the PWM + // generator block +#define PWM_RV_X_INTEN 0x00000000 // Interrupt and trigger enable +#define PWM_RV_X_RIS 0x00000000 // Raw interrupt status +#define PWM_RV_X_ISC 0x00000000 // Interrupt status and clearing +#define PWM_RV_X_LOAD 0x00000000 // The load value for the counter +#define PWM_RV_X_COUNT 0x00000000 // The current counter value +#define PWM_RV_X_CMPA 0x00000000 // The comparator A value +#define PWM_RV_X_CMPB 0x00000000 // The comparator B value +#define PWM_RV_X_GENA 0x00000000 // Controls PWM generator A +#define PWM_RV_X_GENB 0x00000000 // Controls PWM generator B +#define PWM_RV_X_DBCTL 0x00000000 // Control the dead band generator +#define PWM_RV_X_DBRISE 0x00000000 // The dead band rising edge delay + // count +#define PWM_RV_X_DBFALL 0x00000000 // The dead band falling edge delay + // count + +#endif // __HW_PWM_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/hw_qei.h b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/hw_qei.h new file mode 100644 index 000000000..864459f48 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/hw_qei.h @@ -0,0 +1,176 @@ +//***************************************************************************** +// +// hw_qei.h - Macros used when accessing the QEI hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_QEI_H__ +#define __HW_QEI_H__ + +//***************************************************************************** +// +// The following define the offsets of the QEI registers. +// +//***************************************************************************** +#define QEI_O_CTL 0x00000000 // Configuration and control reg. +#define QEI_O_STAT 0x00000004 // Status register +#define QEI_O_POS 0x00000008 // Current position register +#define QEI_O_MAXPOS 0x0000000C // Maximum position register +#define QEI_O_LOAD 0x00000010 // Velocity timer load register +#define QEI_O_TIME 0x00000014 // Velocity timer register +#define QEI_O_COUNT 0x00000018 // Velocity pulse count register +#define QEI_O_SPEED 0x0000001C // Velocity speed register +#define QEI_O_INTEN 0x00000020 // Interrupt enable register +#define QEI_O_RIS 0x00000024 // Raw interrupt status register +#define QEI_O_ISC 0x00000028 // Interrupt status register + +//***************************************************************************** +// +// The following define the bit fields in the QEI_CTL register. +// +//***************************************************************************** +#define QEI_CTL_STALLEN 0x00001000 // Stall enable +#define QEI_CTL_INVI 0x00000800 // Invert Index input +#define QEI_CTL_INVB 0x00000400 // Invert PhB input +#define QEI_CTL_INVA 0x00000200 // Invert PhA input +#define QEI_CTL_VELDIV_M 0x000001C0 // Velocity predivider mask +#define QEI_CTL_VELDIV_1 0x00000000 // Predivide by 1 +#define QEI_CTL_VELDIV_2 0x00000040 // Predivide by 2 +#define QEI_CTL_VELDIV_4 0x00000080 // Predivide by 4 +#define QEI_CTL_VELDIV_8 0x000000C0 // Predivide by 8 +#define QEI_CTL_VELDIV_16 0x00000100 // Predivide by 16 +#define QEI_CTL_VELDIV_32 0x00000140 // Predivide by 32 +#define QEI_CTL_VELDIV_64 0x00000180 // Predivide by 64 +#define QEI_CTL_VELDIV_128 0x000001C0 // Predivide by 128 +#define QEI_CTL_VELEN 0x00000020 // Velocity enable +#define QEI_CTL_RESMODE 0x00000010 // Position counter reset mode +#define QEI_CTL_CAPMODE 0x00000008 // Edge capture mode +#define QEI_CTL_SIGMODE 0x00000004 // Encoder signaling mode +#define QEI_CTL_SWAP 0x00000002 // Swap input signals +#define QEI_CTL_ENABLE 0x00000001 // QEI enable + +//***************************************************************************** +// +// The following define the bit fields in the QEI_STAT register. +// +//***************************************************************************** +#define QEI_STAT_DIRECTION 0x00000002 // Direction of rotation +#define QEI_STAT_ERROR 0x00000001 // Signalling error detected + +//***************************************************************************** +// +// The following define the bit fields in the QEI_POS register. +// +//***************************************************************************** +#define QEI_POS_M 0xFFFFFFFF // Current encoder position +#define QEI_POS_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the QEI_MAXPOS register. +// +//***************************************************************************** +#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum encoder position +#define QEI_MAXPOS_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the QEI_LOAD register. +// +//***************************************************************************** +#define QEI_LOAD_M 0xFFFFFFFF // Velocity timer load value +#define QEI_LOAD_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the QEI_TIME register. +// +//***************************************************************************** +#define QEI_TIME_M 0xFFFFFFFF // Velocity timer current value +#define QEI_TIME_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the QEI_COUNT register. +// +//***************************************************************************** +#define QEI_COUNT_M 0xFFFFFFFF // Encoder running pulse count +#define QEI_COUNT_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the QEI_SPEED register. +// +//***************************************************************************** +#define QEI_SPEED_M 0xFFFFFFFF // Encoder pulse count +#define QEI_SPEED_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the QEI_INTEN register. +// +//***************************************************************************** +#define QEI_INTEN_ERROR 0x00000008 // Phase error detected +#define QEI_INTEN_DIR 0x00000004 // Direction change +#define QEI_INTEN_TIMER 0x00000002 // Velocity timer expired +#define QEI_INTEN_INDEX 0x00000001 // Index pulse detected + +//***************************************************************************** +// +// The following define the bit fields in the QEI_RIS register. +// +//***************************************************************************** +#define QEI_RIS_ERROR 0x00000008 // Phase error detected +#define QEI_RIS_DIR 0x00000004 // Direction change +#define QEI_RIS_TIMER 0x00000002 // Velocity timer expired +#define QEI_RIS_INDEX 0x00000001 // Index pulse detected + +//***************************************************************************** +// +// The following define the bit fields in the QEI_ISC register. +// +//***************************************************************************** +#define QEI_INT_ERROR 0x00000008 // Phase error detected +#define QEI_INT_DIR 0x00000004 // Direction change +#define QEI_INT_TIMER 0x00000002 // Velocity timer expired +#define QEI_INT_INDEX 0x00000001 // Index pulse detected + +//***************************************************************************** +// +// The following define the reset values for the QEI registers. +// +//***************************************************************************** +#define QEI_RV_CTL 0x00000000 // Configuration and control reg. +#define QEI_RV_STAT 0x00000000 // Status register +#define QEI_RV_POS 0x00000000 // Current position register +#define QEI_RV_MAXPOS 0x00000000 // Maximum position register +#define QEI_RV_LOAD 0x00000000 // Velocity timer load register +#define QEI_RV_TIME 0x00000000 // Velocity timer register +#define QEI_RV_COUNT 0x00000000 // Velocity pulse count register +#define QEI_RV_SPEED 0x00000000 // Velocity speed register +#define QEI_RV_INTEN 0x00000000 // Interrupt enable register +#define QEI_RV_RIS 0x00000000 // Raw interrupt status register +#define QEI_RV_ISC 0x00000000 // Interrupt status register + +#endif // __HW_QEI_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/hw_ssi.h b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/hw_ssi.h new file mode 100644 index 000000000..e4650af40 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/hw_ssi.h @@ -0,0 +1,120 @@ +//***************************************************************************** +// +// hw_ssi.h - Macros used when accessing the SSI hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_SSI_H__ +#define __HW_SSI_H__ + +//***************************************************************************** +// +// The following define the offsets of the SSI registers. +// +//***************************************************************************** +#define SSI_O_CR0 0x00000000 // Control register 0 +#define SSI_O_CR1 0x00000004 // Control register 1 +#define SSI_O_DR 0x00000008 // Data register +#define SSI_O_SR 0x0000000C // Status register +#define SSI_O_CPSR 0x00000010 // Clock prescale register +#define SSI_O_IM 0x00000014 // Int mask set and clear register +#define SSI_O_RIS 0x00000018 // Raw interrupt register +#define SSI_O_MIS 0x0000001C // Masked interrupt register +#define SSI_O_ICR 0x00000020 // Interrupt clear register + +//***************************************************************************** +// +// The following define the bit fields in the SSI Control register 0. +// +//***************************************************************************** +#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate +#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase +#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity +#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask +#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format +#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format +#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format +#define SSI_CR0_DSS 0x0000000F // Data size select +#define SSI_CR0_DSS_4 0x00000003 // 4 bit data +#define SSI_CR0_DSS_5 0x00000004 // 5 bit data +#define SSI_CR0_DSS_6 0x00000005 // 6 bit data +#define SSI_CR0_DSS_7 0x00000006 // 7 bit data +#define SSI_CR0_DSS_8 0x00000007 // 8 bit data +#define SSI_CR0_DSS_9 0x00000008 // 9 bit data +#define SSI_CR0_DSS_10 0x00000009 // 10 bit data +#define SSI_CR0_DSS_11 0x0000000A // 11 bit data +#define SSI_CR0_DSS_12 0x0000000B // 12 bit data +#define SSI_CR0_DSS_13 0x0000000C // 13 bit data +#define SSI_CR0_DSS_14 0x0000000D // 14 bit data +#define SSI_CR0_DSS_15 0x0000000E // 15 bit data +#define SSI_CR0_DSS_16 0x0000000F // 16 bit data + +//***************************************************************************** +// +// The following define the bit fields in the SSI Control register 1. +// +//***************************************************************************** +#define SSI_CR1_SOD 0x00000008 // Slave mode output disable +#define SSI_CR1_MS 0x00000004 // Master or slave mode select +#define SSI_CR1_SSE 0x00000002 // Sync serial port enable +#define SSI_CR1_LBM 0x00000001 // Loopback mode + +//***************************************************************************** +// +// The following define the bit fields in the SSI Status register. +// +//***************************************************************************** +#define SSI_SR_BSY 0x00000010 // SSI busy +#define SSI_SR_RFF 0x00000008 // RX FIFO full +#define SSI_SR_RNE 0x00000004 // RX FIFO not empty +#define SSI_SR_TNF 0x00000002 // TX FIFO not full +#define SSI_SR_TFE 0x00000001 // TX FIFO empty + +//***************************************************************************** +// +// The following define the bit fields in the SSI clock prescale register. +// +//***************************************************************************** +#define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale + +//***************************************************************************** +// +// The following define information concerning the SSI Data register. +// +//***************************************************************************** +#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO +#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO + +//***************************************************************************** +// +// The following define the bit fields in the interrupt mask set and clear, +// raw interrupt, masked interrupt, and interrupt clear registers. +// +//***************************************************************************** +#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt +#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt +#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt +#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt + +#endif // __HW_SSI_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/hw_sysctl.h b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/hw_sysctl.h new file mode 100644 index 000000000..cce5ad214 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/hw_sysctl.h @@ -0,0 +1,409 @@ +//***************************************************************************** +// +// hw_sysctl.h - Macros used when accessing the system control hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_SYSCTL_H__ +#define __HW_SYSCTL_H__ + +//***************************************************************************** +// +// The following define the offsets of the system control registers. +// +//***************************************************************************** +#define SYSCTL_DID0 0x400fe000 // Device identification register 0 +#define SYSCTL_DID1 0x400fe004 // Device identification register 1 +#define SYSCTL_DC0 0x400fe008 // Device capabilities register 0 +#define SYSCTL_DC1 0x400fe010 // Device capabilities register 1 +#define SYSCTL_DC2 0x400fe014 // Device capabilities register 2 +#define SYSCTL_DC3 0x400fe018 // Device capabilities register 3 +#define SYSCTL_DC4 0x400fe01C // Device capabilities register 4 +#define SYSCTL_PBORCTL 0x400fe030 // POR/BOR reset control register +#define SYSCTL_LDOPCTL 0x400fe034 // LDO power control register +#define SYSCTL_SRCR0 0x400fe040 // Software reset control reg 0 +#define SYSCTL_SRCR1 0x400fe044 // Software reset control reg 1 +#define SYSCTL_SRCR2 0x400fe048 // Software reset control reg 2 +#define SYSCTL_RIS 0x400fe050 // Raw interrupt status register +#define SYSCTL_IMC 0x400fe054 // Interrupt mask/control register +#define SYSCTL_MISC 0x400fe058 // Interrupt status register +#define SYSCTL_RESC 0x400fe05c // Reset cause register +#define SYSCTL_RCC 0x400fe060 // Run-mode clock config register +#define SYSCTL_PLLCFG 0x400fe064 // PLL configuration register +#define SYSCTL_RCGC0 0x400fe100 // Run-mode clock gating register 0 +#define SYSCTL_RCGC1 0x400fe104 // Run-mode clock gating register 1 +#define SYSCTL_RCGC2 0x400fe108 // Run-mode clock gating register 2 +#define SYSCTL_SCGC0 0x400fe110 // Sleep-mode clock gating reg 0 +#define SYSCTL_SCGC1 0x400fe114 // Sleep-mode clock gating reg 1 +#define SYSCTL_SCGC2 0x400fe118 // Sleep-mode clock gating reg 2 +#define SYSCTL_DCGC0 0x400fe120 // Deep Sleep-mode clock gate reg 0 +#define SYSCTL_DCGC1 0x400fe124 // Deep Sleep-mode clock gate reg 1 +#define SYSCTL_DCGC2 0x400fe128 // Deep Sleep-mode clock gate reg 2 +#define SYSCTL_CLKVCLR 0x400fe150 // Clock verifcation clear register +#define SYSCTL_LDOARST 0x400fe160 // LDO reset control register + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DID0 register. +// +//***************************************************************************** +#define SYSCTL_DID0_VER_MASK 0x70000000 // DID0 version mask +#define SYSCTL_DID0_VER_0 0x00000000 // DID0 version 0 +#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask +#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A +#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B +#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask +#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0 +#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DID1 register. +// +//***************************************************************************** +#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask +#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask +#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family +#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask +#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101 +#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102 +#define SYSCTL_DID1_PRTNO_301 0x00110000 // LM3S301 +#define SYSCTL_DID1_PRTNO_310 0x00120000 // LM3S310 +#define SYSCTL_DID1_PRTNO_315 0x00130000 // LM3S315 +#define SYSCTL_DID1_PRTNO_316 0x00140000 // LM3S316 +#define SYSCTL_DID1_PRTNO_328 0x00150000 // LM3S328 +#define SYSCTL_DID1_PRTNO_601 0x00210000 // LM3S601 +#define SYSCTL_DID1_PRTNO_610 0x00220000 // LM3S610 +#define SYSCTL_DID1_PRTNO_611 0x00230000 // LM3S611 +#define SYSCTL_DID1_PRTNO_612 0x00240000 // LM3S612 +#define SYSCTL_DID1_PRTNO_613 0x00250000 // LM3S613 +#define SYSCTL_DID1_PRTNO_615 0x00260000 // LM3S615 +#define SYSCTL_DID1_PRTNO_628 0x00270000 // LM3S628 +#define SYSCTL_DID1_PRTNO_801 0x00310000 // LM3S801 +#define SYSCTL_DID1_PRTNO_811 0x00320000 // LM3S811 +#define SYSCTL_DID1_PRTNO_812 0x00330000 // LM3S812 +#define SYSCTL_DID1_PRTNO_815 0x00340000 // LM3S815 +#define SYSCTL_DID1_PRTNO_828 0x00350000 // LM3S828 +#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask +#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C) +#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C) +#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask +#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC +#define SYSCTL_DID1_PKG_48QFP 0x00000008 // 48-pin QFP +#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant +#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask +#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified) +#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified) +#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified +#define SYSCTL_DID1_PRTNO_SHIFT 16 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC0 register. +// +//***************************************************************************** +#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask +#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2kB of SRAM +#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4kB of SRAM +#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8kB of SRAM +#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask +#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8kB of flash +#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16kB of flash +#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32kB of flash +#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64kB of flash + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC1 register. +// +//***************************************************************************** +#define SYSCTL_DC1_PWM 0x00100000 // PWM module present +#define SYSCTL_DC1_ADC 0x00010000 // ADC module present +#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask +#define SYSCTL_DC1_ADCSPD_MASK 0x00000F00 // ADC speed mask +#define SYSCTL_DC1_ADCSPD_1M 0x00000300 // 1Msps ADC +#define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500Ksps ADC +#define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250Ksps ADC +#define SYSCTL_DC1_ADCSPD_125K 0x00000000 // 125Ksps ADC +#define SYSCTL_DC1_MPU 0x00000080 // Cortex M3 MPU present +#define SYSCTL_DC1_TEMP 0x00000020 // Temperature sensor present +#define SYSCTL_DC1_PLL 0x00000010 // PLL present +#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present +#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present +#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present +#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC2 register. +// +//***************************************************************************** +#define SYSCTL_DC2_COMP2 0x04000000 // Analog comparator 2 present +#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present +#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present +#define SYSCTL_DC2_TIMER2 0x00040000 // Timer 2 present +#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present +#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present +#define SYSCTL_DC2_I2C 0x00001000 // I2C present +#define SYSCTL_DC2_QEI 0x00000100 // QEI present +#define SYSCTL_DC2_SSI 0x00000010 // SSI present +#define SYSCTL_DC2_UART1 0x00000002 // UART 1 present +#define SYSCTL_DC2_UART0 0x00000001 // UART 0 present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC3 register. +// +//***************************************************************************** +#define SYSCTL_DC3_32KHZ 0x80000000 // 32kHz pin present +#define SYSCTL_DC3_CCP5 0x20000000 // CCP5 pin present +#define SYSCTL_DC3_CCP4 0x10000000 // CCP4 pin present +#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 pin present +#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 pin present +#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present +#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present +#define SYSCTL_DC3_ADC7 0x00800000 // ADC7 pin present +#define SYSCTL_DC3_ADC6 0x00400000 // ADC6 pin present +#define SYSCTL_DC3_ADC5 0x00200000 // ADC5 pin present +#define SYSCTL_DC3_ADC4 0x00100000 // ADC4 pin present +#define SYSCTL_DC3_ADC3 0x00080000 // ADC3 pin present +#define SYSCTL_DC3_ADC2 0x00040000 // ADC2 pin present +#define SYSCTL_DC3_ADC1 0x00020000 // ADC1 pin present +#define SYSCTL_DC3_ADC0 0x00010000 // ADC0 pin present +#define SYSCTL_DC3_C2O 0x00004000 // C2o pin present +#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ pin present +#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- pin present +#define SYSCTL_DC3_C1O 0x00000800 // C1o pin present +#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ pin present +#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present +#define SYSCTL_DC3_C0O 0x00000100 // C0o pin present +#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present +#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present +#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 pin present +#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 pin present +#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 pin present +#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 pin present +#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 pin present +#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 pin present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC4 register. +// +//***************************************************************************** +#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO port E present +#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO port D present +#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present +#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present +#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_PBORCTL register. +// +//***************************************************************************** +#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer +#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset +#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise +#define SYSCTL_PBORCTL_BOR_SH 2 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_LDOPCTL register. +// +//***************************************************************************** +#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask +#define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V +#define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V +#define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V +#define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V +#define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V +#define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V +#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V +#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V +#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V +#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V +#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_SRCR0, SYSCTL_RCGC0, +// SYSCTL_SCGC0, and SYSCTL_DCGC0 registers. +// +//***************************************************************************** +#define SYSCTL_SET0_PWM 0x00100000 // PWM module +#define SYSCTL_SET0_ADC 0x00010000 // ADC module +#define SYSCTL_SET0_ADCSPD_MASK 0x00000F00 // ADC speed mask +#define SYSCTL_SET0_ADCSPD_1M 0x00000300 // 1Msps ADC +#define SYSCTL_SET0_ADCSPD_500K 0x00000200 // 500Ksps ADC +#define SYSCTL_SET0_ADCSPD_250K 0x00000100 // 250Ksps ADC +#define SYSCTL_SET0_ADCSPD_125K 0x00000000 // 125Ksps ADC +#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_SRCR1, SYSCTL_RCGC1, +// SYSCTL_SCGC1, and SYSCTL_DCGC1 registers. +// +//***************************************************************************** +#define SYSCTL_SET1_COMP2 0x04000000 // Analog comparator module 2 +#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1 +#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0 +#define SYSCTL_SET1_TIMER2 0x00040000 // Timer module 2 +#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1 +#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0 +#define SYSCTL_SET1_I2C 0x00001000 // I2C module +#define SYSCTL_SET1_QEI 0x00000100 // QEI module +#define SYSCTL_SET1_SSI 0x00000010 // SSI module +#define SYSCTL_SET1_UART1 0x00000002 // UART module 1 +#define SYSCTL_SET1_UART0 0x00000001 // UART module 0 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_SRCR2, SYSCTL_RCGC2, +// SYSCTL_SCGC2, and SYSCTL_DCGC2 registers. +// +//***************************************************************************** +#define SYSCTL_SET2_GPIOE 0x00000010 // GPIO E module +#define SYSCTL_SET2_GPIOD 0x00000008 // GPIO D module +#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module +#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module +#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_RIS, SYSCTL_IMC, and +// SYSCTL_IMS registers. +// +//***************************************************************************** +#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt +#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt +#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int +#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int +#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt +#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt +#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_RESC register. +// +//***************************************************************************** +#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset +#define SYSCTL_RESC_SW 0x00000010 // Software reset +#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset +#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset +#define SYSCTL_RESC_POR 0x00000002 // Power on reset +#define SYSCTL_RESC_EXT 0x00000001 // External reset + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_RCC register. +// +//***************************************************************************** +#define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating +#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider +#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2 +#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3 +#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4 +#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5 +#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6 +#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7 +#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8 +#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9 +#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10 +#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11 +#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12 +#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13 +#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14 +#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15 +#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16 +#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider +#define SYSCTL_RCC_USE_PWMDIV 0x00100000 // Use PWM clock divider +#define SYSCTL_RCC_PWMDIV_MASK 0x000E0000 // PWM clock divider +#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2 +#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4 +#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8 +#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16 +#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32 +#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64 +#define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down +#define SYSCTL_RCC_OE 0x00001000 // PLL output enable +#define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass +#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable +#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc +#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal +#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864MHz crystal +#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4MHz crystal +#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal +#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal +#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal +#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal +#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal +#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal +#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal +#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal +#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal +#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select +#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator +#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // Use the internal oscillator +#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // Use the internal oscillator / 4 +#define SYSCTL_RCC_IOSCVER 0x00000008 // Int. osc. verification timer en +#define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en +#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal oscillator disable +#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable +#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field +#define SYSCTL_RCC_PWMDIV_SHIFT 17 // Shift to the PWMDIV field +#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field +#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_PLLCFG register. +// +//***************************************************************************** +#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider +#define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1 +#define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2 +#define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4 +#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier +#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider +#define SYSCTL_PLLCFG_F_SHIFT 5 +#define SYSCTL_PLLCFG_R_SHIFT 0 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_CLKVCLR register. +// +//***************************************************************************** +#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_LDOARST register. +// +//***************************************************************************** +#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device + +#endif // __HW_SYSCTL_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/hw_timer.h b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/hw_timer.h new file mode 100644 index 000000000..210c3408e --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/hw_timer.h @@ -0,0 +1,235 @@ +//***************************************************************************** +// +// hw_timer.h - Defines and macros used when accessing the timer. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_TIMER_H__ +#define __HW_TIMER_H__ + +//***************************************************************************** +// +// The following define the offsets of the timer registers. +// +//***************************************************************************** +#define TIMER_O_CFG 0x00000000 // Configuration register +#define TIMER_O_TAMR 0x00000004 // TimerA mode register +#define TIMER_O_TBMR 0x00000008 // TimerB mode register +#define TIMER_O_CTL 0x0000000C // Control register +#define TIMER_O_IMR 0x00000018 // Interrupt mask register +#define TIMER_O_RIS 0x0000001C // Interrupt status register +#define TIMER_O_MIS 0x00000020 // Masked interrupt status reg. +#define TIMER_O_ICR 0x00000024 // Interrupt clear register +#define TIMER_O_TAILR 0x00000028 // TimerA interval load register +#define TIMER_O_TBILR 0x0000002C // TimerB interval load register +#define TIMER_O_TAMATCHR 0x00000030 // TimerA match register +#define TIMER_O_TBMATCHR 0x00000034 // TimerB match register +#define TIMER_O_TAPR 0x00000038 // TimerA prescale register +#define TIMER_O_TBPR 0x0000003C // TimerB prescale register +#define TIMER_O_TAPMR 0x00000040 // TimerA prescale match register +#define TIMER_O_TBPMR 0x00000044 // TimerB prescale match register +#define TIMER_O_TAR 0x00000048 // TimerA register +#define TIMER_O_TBR 0x0000004C // TimerB register + +//***************************************************************************** +// +// The following define the reset values of the timer registers. +// +//***************************************************************************** +#define TIMER_RV_CFG 0x00000000 // Configuration register RV +#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV +#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV +#define TIMER_RV_CTL 0x00000000 // Control register RV +#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV +#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV +#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV +#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV +#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV +#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV +#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV +#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV +#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV +#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV +#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV +#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV +#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV +#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_CFG register. +// +//***************************************************************************** +#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask +#define TIMER_CFG_16_BIT 0x00000004 // Two 16 bit timers +#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32 bit RTC +#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32 bit timer + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_TnMR register. +// +//***************************************************************************** +#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select +#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time +#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask +#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture +#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic +#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_CTL register. +// +//***************************************************************************** +#define TIMER_CTL_TBPWML 0x00004000 // TimerB PWM output level invert +#define TIMER_CTL_TBOTE 0x00002000 // TimerB output trigger enable +#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask +#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // TimerB event mode - both edges +#define TIMER_CTL_TBEVENT_NEG 0x00000400 // TimerB event mode - neg edge +#define TIMER_CTL_TBEVENT_POS 0x00000000 // TimerB event mode - pos edge +#define TIMER_CTL_TBSTALL 0x00000200 // TimerB stall enable +#define TIMER_CTL_TBEN 0x00000100 // TimerB enable +#define TIMER_CTL_TAPWML 0x00000040 // TimerA PWM output level invert +#define TIMER_CTL_TAOTE 0x00000020 // TimerA output trigger enable +#define TIMER_CTL_RTCEN 0x00000010 // RTC counter enable +#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask +#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // TimerA event mode - both edges +#define TIMER_CTL_TAEVENT_NEG 0x00000004 // TimerA event mode - neg edge +#define TIMER_CTL_TAEVENT_POS 0x00000000 // TimerA event mode - pos edge +#define TIMER_CTL_TASTALL 0x00000002 // TimerA stall enable +#define TIMER_CTL_TAEN 0x00000001 // TimerA enable + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_IMR register. +// +//***************************************************************************** +#define TIMER_IMR_CBEIM 0x00000400 // CaptureB event interrupt mask +#define TIMER_IMR_CBMIM 0x00000200 // CaptureB match interrupt mask +#define TIMER_IMR_TBTOIM 0x00000100 // TimerB time out interrupt mask +#define TIMER_IMR_RTCIM 0x00000008 // RTC interrupt mask +#define TIMER_IMR_CAEIM 0x00000004 // CaptureA event interrupt mask +#define TIMER_IMR_CAMIM 0x00000002 // CaptureA match interrupt mask +#define TIMER_IMR_TATOIM 0x00000001 // TimerA time out interrupt mask + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_RIS register. +// +//***************************************************************************** +#define TIMER_RIS_CBERIS 0x00000400 // CaptureB event raw int status +#define TIMER_RIS_CBMRIS 0x00000200 // CaptureB match raw int status +#define TIMER_RIS_TBTORIS 0x00000100 // TimerB time out raw int status +#define TIMER_RIS_RTCRIS 0x00000008 // RTC raw int status +#define TIMER_RIS_CAERIS 0x00000004 // CaptureA event raw int status +#define TIMER_RIS_CAMRIS 0x00000002 // CaptureA match raw int status +#define TIMER_RIS_TATORIS 0x00000001 // TimerA time out raw int status + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_MIS register. +// +//***************************************************************************** +#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status +#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status +#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat +#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status +#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status +#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status +#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_ICR register. +// +//***************************************************************************** +#define TIMER_ICR_CBECINT 0x00000400 // CaptureB event interrupt clear +#define TIMER_ICR_CBMCINT 0x00000200 // CaptureB match interrupt clear +#define TIMER_ICR_TBTOCINT 0x00000100 // TimerB time out interrupt clear +#define TIMER_ICR_RTCCINT 0x00000008 // RTC interrupt clear +#define TIMER_ICR_CAECINT 0x00000004 // CaptureA event interrupt clear +#define TIMER_ICR_CAMCINT 0x00000002 // CaptureA match interrupt clear +#define TIMER_ICR_TATOCINT 0x00000001 // TimerA time out interrupt clear + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_TAILR register. +// +//***************************************************************************** +#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode +#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TBILR register. +// +//***************************************************************************** +#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_TAMATCHR register. +// +//***************************************************************************** +#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode +#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TBMATCHR register. +// +//***************************************************************************** +#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TnPR register. +// +//***************************************************************************** +#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TnPMR register. +// +//***************************************************************************** +#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_TAR register. +// +//***************************************************************************** +#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode +#define TIMER_TAR_TARL 0x0000FFFF // TimerA value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TBR register. +// +//***************************************************************************** +#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value + +#endif // __HW_TIMER_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/hw_types.h b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/hw_types.h new file mode 100644 index 000000000..ec05e5415 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/hw_types.h @@ -0,0 +1,67 @@ +//***************************************************************************** +// +// hw_types.h - Common types and macros. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_TYPES_H__ +#define __HW_TYPES_H__ + +//***************************************************************************** +// +// Define a boolean type, and values for true and false. +// +//***************************************************************************** +typedef unsigned char tBoolean; + +#ifndef true +#define true 1 +#endif + +#ifndef false +#define false 0 +#endif + +//***************************************************************************** +// +// Macros for hardware access, both direct and via the bit-band region. +// +//***************************************************************************** +#define HWREG(x) \ + (*((volatile unsigned long *)(x))) +#define HWREGH(x) \ + (*((volatile unsigned short *)(x))) +#define HWREGB(x) \ + (*((volatile unsigned char *)(x))) +#define HWREGBITW(x, b) \ + HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITH(x, b) \ + HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITB(x, b) \ + HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) + +#endif // __HW_TYPES_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/hw_uart.h b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/hw_uart.h new file mode 100644 index 000000000..6f421b64e --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/hw_uart.h @@ -0,0 +1,239 @@ +//***************************************************************************** +// +// hw_uart.h - Macros and defines used when accessing the UART hardware +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_UART_H__ +#define __HW_UART_H__ + +//***************************************************************************** +// +// UART Register Offsets. +// +//***************************************************************************** +#define UART_O_DR 0x00000000 // Data Register +#define UART_O_RSR 0x00000004 // Receive Status Register (read) +#define UART_O_ECR 0x00000004 // Error Clear Register (write) +#define UART_O_FR 0x00000018 // Flag Register (read only) +#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg +#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg +#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte +#define UART_O_CTL 0x00000030 // Control Register +#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg +#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg +#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register +#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register +#define UART_O_ICR 0x00000044 // Interrupt Clear Register +#define UART_O_PeriphID4 0x00000FD0 // +#define UART_O_PeriphID5 0x00000FD4 // +#define UART_O_PeriphID6 0x00000FD8 // +#define UART_O_PeriphID7 0x00000FDC // +#define UART_O_PeriphID0 0x00000FE0 // +#define UART_O_PeriphID1 0x00000FE4 // +#define UART_O_PeriphID2 0x00000FE8 // +#define UART_O_PeriphID3 0x00000FEC // +#define UART_O_PCellID0 0x00000FF0 // +#define UART_O_PCellID1 0x00000FF4 // +#define UART_O_PCellID2 0x00000FF8 // +#define UART_O_PCellID3 0x00000FFC // + +//***************************************************************************** +// +// Data Register bits +// +//***************************************************************************** +#define UART_DR_OE 0x00000800 // Overrun Error +#define UART_DR_BE 0x00000400 // Break Error +#define UART_DR_PE 0x00000200 // Parity Error +#define UART_DR_FE 0x00000100 // Framing Error +#define UART_DR_DATA_MASK 0x000000FF // UART data + +//***************************************************************************** +// +// Receive Status Register bits +// +//***************************************************************************** +#define UART_RSR_OE 0x00000008 // Overrun Error +#define UART_RSR_BE 0x00000004 // Break Error +#define UART_RSR_PE 0x00000002 // Parity Error +#define UART_RSR_FE 0x00000001 // Framing Error + +//***************************************************************************** +// +// Flag Register bits +// +//***************************************************************************** +#define UART_FR_TXFE 0x00000080 // TX FIFO Empty +#define UART_FR_RXFF 0x00000040 // RX FIFO Full +#define UART_FR_TXFF 0x00000020 // TX FIFO Full +#define UART_FR_RXFE 0x00000010 // RX FIFO Empty +#define UART_FR_BUSY 0x00000008 // UART Busy + +//***************************************************************************** +// +// Integer baud-rate divisor +// +//***************************************************************************** +#define UART_IBRD_DIVINT_MASK 0x0000FFFF // Integer baud-rate divisor + +//***************************************************************************** +// +// Fractional baud-rate divisor +// +//***************************************************************************** +#define UART_FBRD_DIVFRAC_MASK 0x0000003F // Fractional baud-rate divisor + +//***************************************************************************** +// +// Line Control Register High bits +// +//***************************************************************************** +#define UART_LCR_H_SPS 0x00000080 // Stick Parity Select +#define UART_LCR_H_WLEN 0x00000060 // Word length +#define UART_LCR_H_WLEN_8 0x00000060 // 8 bit data +#define UART_LCR_H_WLEN_7 0x00000040 // 7 bit data +#define UART_LCR_H_WLEN_6 0x00000020 // 6 bit data +#define UART_LCR_H_WLEN_5 0x00000000 // 5 bit data +#define UART_LCR_H_FEN 0x00000010 // Enable FIFO +#define UART_LCR_H_STP2 0x00000008 // Two Stop Bits Select +#define UART_LCR_H_EPS 0x00000004 // Even Parity Select +#define UART_LCR_H_PEN 0x00000002 // Parity Enable +#define UART_LCR_H_BRK 0x00000001 // Send Break + +//***************************************************************************** +// +// Control Register bits +// +//***************************************************************************** +#define UART_CTL_RXE 0x00000200 // Receive Enable +#define UART_CTL_TXE 0x00000100 // Transmit Enable +#define UART_CTL_LBE 0x00000080 // Loopback Enable +#define UART_CTL_UARTEN 0x00000001 // UART Enable + +//***************************************************************************** +// +// Interrupt FIFO Level Select Register bits +// +//***************************************************************************** +#define UART_IFLS_RX1_8 0x00000000 // 1/8 Full +#define UART_IFLS_RX2_8 0x00000010 // 1/4 Full +#define UART_IFLS_RX4_8 0x00000020 // 1/2 Full +#define UART_IFLS_RX6_8 0x00000030 // 3/4 Full +#define UART_IFLS_RX7_8 0x00000040 // 7/8 Full +#define UART_IFLS_TX1_8 0x00000000 // 1/8 Full +#define UART_IFLS_TX2_8 0x00000001 // 1/4 Full +#define UART_IFLS_TX4_8 0x00000002 // 1/2 Full +#define UART_IFLS_TX6_8 0x00000003 // 3/4 Full +#define UART_IFLS_TX7_8 0x00000004 // 7/8 Full + +//***************************************************************************** +// +// Interrupt Mask Set/Clear Register bits +// +//***************************************************************************** +#define UART_IM_OEIM 0x00000400 // Overrun Error Interrupt Mask +#define UART_IM_BEIM 0x00000200 // Break Error Interrupt Mask +#define UART_IM_PEIM 0x00000100 // Parity Error Interrupt Mask +#define UART_IM_FEIM 0x00000080 // Framing Error Interrupt Mask +#define UART_IM_RTIM 0x00000040 // Receive Timeout Interrupt Mask +#define UART_IM_TXIM 0x00000020 // Transmit Interrupt Mask +#define UART_IM_RXIM 0x00000010 // Receive Interrupt Mask + +//***************************************************************************** +// +// Raw Interrupt Status Register +// +//***************************************************************************** +#define UART_RIS_OERIS 0x00000400 // Overrun Error Interrupt Status +#define UART_RIS_BERIS 0x00000200 // Break Error Interrupt Status +#define UART_RIS_PERIS 0x00000100 // Parity Error Interrupt Status +#define UART_RIS_FERIS 0x00000080 // Framing Error Interrupt Status +#define UART_RIS_RTRIS 0x00000040 // Receive Timeout Interrupt Status +#define UART_RIS_TXRIS 0x00000020 // Transmit Interrupt Status +#define UART_RIS_RXRIS 0x00000010 // Receive Interrupt Status + +//***************************************************************************** +// +// Masked Interrupt Status Register +// +//***************************************************************************** +#define UART_MIS_OEMIS 0x00000400 // Overrun Error Interrupt Status +#define UART_MIS_BEMIS 0x00000200 // Break Error Interrupt Status +#define UART_MIS_PEMIS 0x00000100 // Parity Error Interrupt Status +#define UART_MIS_FEMIS 0x00000080 // Framing Error Interrupt Status +#define UART_MIS_RTMIS 0x00000040 // Receive Timeout Interrupt Status +#define UART_MIS_TXMIS 0x00000020 // Transmit Interrupt Status +#define UART_MIS_RXMIS 0x00000010 // Receive Interrupt Status + +//***************************************************************************** +// +// Interrupt Clear Register bits +// +//***************************************************************************** +#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear +#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear +#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear +#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear +#define UART_ICR_RTIC 0x00000040 // Receive Timeout Interrupt Clear +#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear +#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear + +#define UART_RSR_ANY (UART_RSR_OE | \ + UART_RSR_BE | \ + UART_RSR_PE | \ + UART_RSR_FE) + +//***************************************************************************** +// +// Reset Values for UART Registers. +// +//***************************************************************************** +#define UART_RV_DR 0x00000000 +#define UART_RV_RSR 0x00000000 +#define UART_RV_ECR 0x00000000 +#define UART_RV_FR 0x00000090 +#define UART_RV_IBRD 0x00000000 +#define UART_RV_FBRD 0x00000000 +#define UART_RV_LCR_H 0x00000000 +#define UART_RV_CTL 0x00000300 +#define UART_RV_IFLS 0x00000012 +#define UART_RV_IM 0x00000000 +#define UART_RV_RIS 0x00000000 +#define UART_RV_MIS 0x00000000 +#define UART_RV_ICR 0x00000000 +#define UART_RV_PeriphID4 0x00000000 +#define UART_RV_PeriphID5 0x00000000 +#define UART_RV_PeriphID6 0x00000000 +#define UART_RV_PeriphID7 0x00000000 +#define UART_RV_PeriphID0 0x00000011 +#define UART_RV_PeriphID1 0x00000000 +#define UART_RV_PeriphID2 0x00000018 +#define UART_RV_PeriphID3 0x00000001 +#define UART_RV_PCellID0 0x0000000D +#define UART_RV_PCellID1 0x000000F0 +#define UART_RV_PCellID2 0x00000005 +#define UART_RV_PCellID3 0x000000B1 + +#endif // __HW_UART_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/hw_watchdog.h b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/hw_watchdog.h new file mode 100644 index 000000000..2b013ad84 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/hw_watchdog.h @@ -0,0 +1,116 @@ +//***************************************************************************** +// +// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_WATCHDOG_H__ +#define __HW_WATCHDOG_H__ + +//***************************************************************************** +// +// The following define the offsets of the Watchdog Timer registers. +// +//***************************************************************************** +#define WDT_O_LOAD 0x00000000 // Load register +#define WDT_O_VALUE 0x00000004 // Current value register +#define WDT_O_CTL 0x00000008 // Control register +#define WDT_O_ICR 0x0000000C // Interrupt clear register +#define WDT_O_RIS 0x00000010 // Raw interrupt status register +#define WDT_O_MIS 0x00000014 // Masked interrupt status register +#define WDT_O_TEST 0x00000418 // Test register +#define WDT_O_LOCK 0x00000C00 // Lock register +#define WDT_O_PeriphID4 0x00000FD0 // +#define WDT_O_PeriphID5 0x00000FD4 // +#define WDT_O_PeriphID6 0x00000FD8 // +#define WDT_O_PeriphID7 0x00000FDC // +#define WDT_O_PeriphID0 0x00000FE0 // +#define WDT_O_PeriphID1 0x00000FE4 // +#define WDT_O_PeriphID2 0x00000FE8 // +#define WDT_O_PeriphID3 0x00000FEC // +#define WDT_O_PCellID0 0x00000FF0 // +#define WDT_O_PCellID1 0x00000FF4 // +#define WDT_O_PCellID2 0x00000FF8 // +#define WDT_O_PCellID3 0x00000FFC // + +//***************************************************************************** +// +// The following define the bit fields in the WDT_CTL register. +// +//***************************************************************************** +#define WDT_CTL_RESEN 0x00000002 // Enable reset output +#define WDT_CTL_INTEN 0x00000001 // Enable the WDT counter and int + +//***************************************************************************** +// +// The following define the bit fields in the WDT_ISR, WDT_RIS, and WDT_MIS +// registers. +// +//***************************************************************************** +#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired + +//***************************************************************************** +// +// The following define the bit fields in the WDT_TEST register. +// +//***************************************************************************** +#define WDT_TEST_STALL 0x00000100 // Watchdog stall enable +#ifndef DEPRECATED +#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable +#endif + +//***************************************************************************** +// +// The following define the bit fields in the WDT_LOCK register. +// +//***************************************************************************** +#define WDT_LOCK_LOCKED 0x00000001 // Watchdog timer is locked +#define WDT_LOCK_UNLOCKED 0x00000000 // Watchdog timer is unlocked +#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer + +//***************************************************************************** +// +// The following define the reset values for the WDT registers. +// +//***************************************************************************** +#define WDT_RV_LOAD 0xFFFFFFFF // Load register +#define WDT_RV_VALUE 0xFFFFFFFF // Current value register +#define WDT_RV_CTL 0x00000000 // Control register +#define WDT_RV_RIS 0x00000000 // Raw interrupt status register +#define WDT_RV_MIS 0x00000000 // Masked interrupt status register +#define WDT_RV_LOCK 0x00000000 // Lock register +#define WDT_RV_PeriphID4 0x00000000 // +#define WDT_RV_PeriphID5 0x00000000 // +#define WDT_RV_PeriphID6 0x00000000 // +#define WDT_RV_PeriphID7 0x00000000 // +#define WDT_RV_PeriphID0 0x00000005 // +#define WDT_RV_PeriphID1 0x00000018 // +#define WDT_RV_PeriphID2 0x00000018 // +#define WDT_RV_PeriphID3 0x00000001 // +#define WDT_RV_PCellID0 0x0000000D // +#define WDT_RV_PCellID1 0x000000F0 // +#define WDT_RV_PCellID2 0x00000005 // +#define WDT_RV_PCellID3 0x000000B1 // + +#endif // __HW_WATCHDOG_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/i2c.c b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/i2c.c new file mode 100644 index 000000000..b460ad603 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/i2c.c @@ -0,0 +1,972 @@ +//***************************************************************************** +// +// i2c.c - Driver for Inter-IC (I2C) bus block. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup i2c_api +//! @{ +// +//***************************************************************************** + +#include "../hw_i2c.h" +#include "../hw_ints.h" +#include "../hw_memmap.h" +#include "../hw_types.h" +#include "debug.h" +#include "i2c.h" +#include "interrupt.h" +#include "sysctl.h" + +//***************************************************************************** +// +//! Initializes the I2C Master block. +//! +//! \param ulBase base address of the I2C Master module +//! \param bFast set up for fast data transfers +//! +//! This function initializes operation of the I2C Master block. Upon +//! successful initialization of the I2C block, this function will have +//! set the bus speed for the master, and will have enabled the I2C Master +//! block. +//! +//! If the parameter \e bFast is \b true, then the master block will be +//! set up to transfer data at 400 kbps; otherwise, it will be set up to +//! transfer data at 100 kbps. +//! +//! The I2C clocking is dependent upon the system clock rate returned by +//! SysCtlClockGet(); if it does not return the correct system clock rate then +//! the I2C clock rate will be incorrect. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_masterinit) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CMasterInit(unsigned long ulBase, tBoolean bFast) +{ + unsigned long ulSysClk; + unsigned long ulSCLFreq; + unsigned long ulTPR; + + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Must enable the device before doing anything else. + // + I2CMasterEnable(ulBase); + + // + // Get the system clock speed. + // + ulSysClk = SysCtlClockGet(); + + // + // Get the desired SCL speed. + // + if(bFast == true) + { + ulSCLFreq = I2C_SCL_FAST; + } + else + { + ulSCLFreq = I2C_SCL_STANDARD; + } + + // + // Compute the clock divider that achieves the fastest speed less than or + // equal to the desired speed. The numerator is biases to favor a larger + // clock divider so that the resulting clock is always less than or equal + // to the desired clock, never greater. + // + ulTPR = (((ulSysClk + (2 * I2C_MASTER_TPR_SCL * ulSCLFreq) - 1) / + (2 * I2C_MASTER_TPR_SCL * ulSCLFreq)) - 1); + HWREG(ulBase + I2C_MASTER_O_TPR) = ulTPR; +} +#endif + +//***************************************************************************** +// +//! Initializes the I2C Slave block. +//! +//! \param ulBase base address of the I2C Slave module +//! \param ucSlaveAddr 7-bit slave address +//! +//! This function initializes operation of the I2C Slave block. Upon +//! successful initialization of the I2C blocks, this function will have +//! set the slave address and have enabled the I2C Slave block. +//! +//! The parameter \e ucSlaveAddr is the value that will be compared +//! against the slave address sent by an I2C master. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_slaveinit) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_SLAVE_BASE); + ASSERT(!(ucSlaveAddr & 0x80)); + + // + // Must enable the device before doing anything else. + // + I2CSlaveEnable(ulBase); + + // + // Set up the slave address. + // + HWREG(ulBase + I2C_SLAVE_O_OAR) = ucSlaveAddr; +} +#endif + +//***************************************************************************** +// +//! Enables the I2C Master block. +//! +//! \param ulBase base address of the I2C Master module +//! +//! This will enable operation of the I2C Master block. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_masterenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CMasterEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Enable the master block. + // + HWREG(ulBase + I2C_MASTER_O_CR) |= I2C_MASTER_CR_MFE; +} +#endif + +//***************************************************************************** +// +//! Enables the I2C Slave block. +//! +//! \param ulBase base address of the I2C Slave module +//! +//! This will enable operation of the I2C Slave block. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_slaveenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CSlaveEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_SLAVE_BASE); + + // + // Enable the clock to the slave block. + // + HWREG(ulBase - I2C_O_SLAVE + I2C_MASTER_O_CR) |= I2C_MASTER_CR_SFE; + + // + // Enable the slave. + // + HWREG(ulBase + I2C_SLAVE_O_CSR) = I2C_SLAVE_CSR_DA; +} +#endif + +//***************************************************************************** +// +//! Disables the I2C master block. +//! +//! \param ulBase base address of the I2C Master module +//! +//! This will disable operation of the I2C master block. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_masterdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CMasterDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Disable the master block. + // + HWREG(ulBase + I2C_MASTER_O_CR) &= ~(I2C_MASTER_CR_MFE); +} +#endif + +//***************************************************************************** +// +//! Disables the I2C slave block. +//! +//! \param ulBase base address of the I2C Slave module +//! +//! This will disable operation of the I2C slave block. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_slavedisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CSlaveDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_SLAVE_BASE); + + // + // Disable the slave. + // + HWREG(ulBase + I2C_SLAVE_O_CSR) = 0; + + // + // Disable the clock to the slave block. + // + HWREG(ulBase - I2C_O_SLAVE + I2C_MASTER_O_CR) &= ~(I2C_MASTER_CR_SFE); +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for the I2C module +//! +//! \param ulBase base address of the I2C module +//! \param pfnHandler is a pointer to the function to be called when the +//! synchronous serial interface interrupt occurs. +//! +//! This sets the handler to be called when an I2C interrupt occurs. This +//! will enable the global interrupt in the interrupt controller; specific I2C +//! interrupts must be enabled via I2CMasterIntEnable() and +//! I2CSlaveIntEnable(). If necessary, it is the interrupt handler's +//! responsibility to clear the interrupt source via I2CMasterIntClear() and +//! I2CSlaveIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(INT_I2C, pfnHandler); + + // + // Enable the I2C interrupt. + // + IntEnable(INT_I2C); +} +#endif + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the I2C module. +//! +//! \param ulBase base address of the I2C module +//! +//! This function will clear the handler to be called when an I2C +//! interrupt occurs. This will also mask off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CIntUnregister(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Disable the interrupt. + // + IntDisable(INT_I2C); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_I2C); +} +#endif + +//***************************************************************************** +// +//! Enables the I2C Master interrupt. +//! +//! \param ulBase base address of the I2C Master module +//! +//! Enables the I2C Master interrupt source. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_masterintenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CMasterIntEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Enable the master interrupt. + // + HWREG(ulBase + I2C_MASTER_O_IMR) = 1; +} +#endif + +//***************************************************************************** +// +//! Enables the I2C Slave interrupt. +//! +//! \param ulBase base address of the I2C Slave module +//! +//! Enables the I2C Slave interrupt source. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_slaveintenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CSlaveIntEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_SLAVE_BASE); + + // + // Enable the slave interrupt. + // + HWREG(ulBase + I2C_SLAVE_O_IM) = 1; +} +#endif + +//***************************************************************************** +// +//! Disables the I2C Master interrupt. +//! +//! \param ulBase base address of the I2C Master module +//! +//! Disables the I2C Master interrupt source. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_masterintdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CMasterIntDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Disable the master interrupt. + // + HWREG(ulBase + I2C_MASTER_O_IMR) = 0; +} +#endif + +//***************************************************************************** +// +//! Disables the I2C Slave interrupt. +//! +//! \param ulBase base address of the I2C Slave module +//! +//! Disables the I2C Slave interrupt source. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_slaveintdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CSlaveIntDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_SLAVE_BASE); + + // + // Disable the slave interrupt. + // + HWREG(ulBase + I2C_SLAVE_O_IM) = 0; +} +#endif + +//***************************************************************************** +// +//! Gets the current I2C Master interrupt status. +//! +//! \param ulBase base address of the I2C Master module +//! \param bMasked is false if the raw interrupt status is requested and +//! true if the masked interrupt status is requested. +//! +//! This returns the interrupt status for the I2C Master module. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. +//! +//! \return The current interrupt status, returned as \b true if active +//! or \b false if not active. +// +//***************************************************************************** +#if defined(GROUP_masterintstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return((HWREG(ulBase + I2C_MASTER_O_MIS)) ? true : false); + } + else + { + return((HWREG(ulBase + I2C_MASTER_O_RIS)) ? true : false); + } +} +#endif + +//***************************************************************************** +// +//! Gets the current I2C Slave interrupt status. +//! +//! \param ulBase base address of the I2C Slave module +//! \param bMasked is false if the raw interrupt status is requested and +//! true if the masked interrupt status is requested. +//! +//! This returns the interrupt status for the I2C Slave module. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. +//! +//! \return The current interrupt status, returned as \b true if active +//! or \b false if not active. +// +//***************************************************************************** +#if defined(GROUP_slaveintstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_SLAVE_BASE); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return((HWREG(ulBase + I2C_SLAVE_O_MIS)) ? true : false); + } + else + { + return((HWREG(ulBase + I2C_SLAVE_O_RIS)) ? true : false); + } +} +#endif + +//***************************************************************************** +// +//! Clears I2C Master interrupt sources. +//! +//! \param ulBase base address of the I2C Master module +//! +//! The I2C Master interrupt source is cleared, so that it no longer asserts. +//! This must be done in the interrupt handler to keep it from being called +//! again immediately upon exit. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_masterintclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CMasterIntClear(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Clear the I2C master interrupt source. + // + HWREG(ulBase + I2C_MASTER_O_MICR) = I2C_MASTER_MICR_IC; + + // + // Workaround for I2C master interrupt clear errata for rev B Stellaris + // devices. For later devices, this write is ignored and therefore + // harmless (other than the slight performance hit). + // + HWREG(ulBase + I2C_MASTER_O_MIS) = I2C_MASTER_MICR_IC; +} +#endif + +//***************************************************************************** +// +//! Clears I2C Slave interrupt sources. +//! +//! \param ulBase base address of the I2C Slave module +//! +//! The I2C Slave interrupt source is cleared, so that it no longer asserts. +//! This must be done in the interrupt handler to keep it from being called +//! again immediately upon exit. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_slaveintclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CSlaveIntClear(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_SLAVE_BASE); + + // + // Clear the I2C slave interrupt source. + // + HWREG(ulBase + I2C_SLAVE_O_SICR) = I2C_SLAVE_SICR_IC; +} +#endif + +//***************************************************************************** +// +//! Sets the address that the I2C Master will place on the bus. +//! +//! \param ulBase base address of the I2C Master module +//! \param ucSlaveAddr 7-bit slave address +//! \param bReceive flag indicating the type of communication with the slave +//! +//! This function will set the address that the I2C Master will place on the +//! bus when initiating a transaction. When the parameter \e bReceive is set +//! to \b true, the address will indicate that the I2C Master is initiating +//! a read from the slave; otherwise the address will indicate that the I2C +//! Master is initiating a write to the slave. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_masterslaveaddrset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CMasterSlaveAddrSet(unsigned long ulBase, unsigned char ucSlaveAddr, + tBoolean bReceive) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + ASSERT(!(ucSlaveAddr & 0x80)); + + // + // Set the address of the slave with which the master will communicate. + // + HWREG(ulBase + I2C_MASTER_O_SA) = (ucSlaveAddr << 1) | bReceive; +} +#endif + +//***************************************************************************** +// +//! Indicates whether or not the I2C Master is busy. +//! +//! \param ulBase base address of the I2C Master module +//! +//! This function returns an indication of whether or not the I2C Master is +//! busy transmitting or receiving data. +//! +//! \return Returns \b true if the I2C Master is busy; otherwise, returns +//! \b false. +// +//***************************************************************************** +#if defined(GROUP_masterbusy) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +I2CMasterBusy(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Return the busy status. + // + if(HWREG(ulBase + I2C_MASTER_O_CS) & I2C_MASTER_CS_BUSY) + { + return(true); + } + else + { + return(false); + } +} +#endif + +//***************************************************************************** +// +//! Indicates whether or not the I2C bus is busy. +//! +//! \param ulBase base address of the I2C Master module +//! +//! This function returns an indication of whether or not the I2C bus is +//! busy. This function can be used in a multi-master environment to +//! determine if another master is currently using the bus. +//! +//! \return Returns \b true if the I2C bus is busy; otherwise, returns +//! \b false. +// +//***************************************************************************** +#if defined(GROUP_masterbusbusy) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +I2CMasterBusBusy(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Return the bus busy status. + // + if(HWREG(ulBase + I2C_MASTER_O_CS) & I2C_MASTER_CS_BUS_BUSY) + { + return(true); + } + else + { + return(false); + } +} +#endif + +//***************************************************************************** +// +//! Controls the state of the I2C Master module. +//! +//! \param ulBase base address of the I2C Master module +//! \param ulCmd command to be issued to the I2C Master module +//! +//! This function is used to control the state of the Master module send and +//! receive operations. The parameter \e ucCmd can be one of the following +//! values: +//! +//! - I2C_MASTER_CMD_SINGLE_SEND +//! - I2C_MASTER_CMD_SINGLE_RECEIVE +//! - I2C_MASTER_CMD_BURST_SEND_START +//! - I2C_MASTER_CMD_BURST_SEND_CONT +//! - I2C_MASTER_CMD_BURST_SEND_FINISH +//! - I2C_MASTER_CMD_BURST_SEND_ERROR_STOP +//! - I2C_MASTER_CMD_BURST_RECEIVE_START +//! - I2C_MASTER_CMD_BURST_RECEIVE_CONT +//! - I2C_MASTER_CMD_BURST_RECEIVE_FINISH +//! - I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_mastercontrol) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CMasterControl(unsigned long ulBase, unsigned long ulCmd) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + ASSERT((ulCmd == I2C_MASTER_CMD_SINGLE_SEND) || + (ulCmd == I2C_MASTER_CMD_SINGLE_RECEIVE) || + (ulCmd == I2C_MASTER_CMD_BURST_SEND_START) || + (ulCmd == I2C_MASTER_CMD_BURST_SEND_CONT) || + (ulCmd == I2C_MASTER_CMD_BURST_SEND_FINISH) || + (ulCmd == I2C_MASTER_CMD_BURST_SEND_ERROR_STOP) || + (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_START) || + (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_CONT) || + (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_FINISH) || + (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP)); + + // + // Send the command. + // + HWREG(ulBase + I2C_MASTER_O_CS) = ulCmd; +} +#endif + +//***************************************************************************** +// +//! Gets the error status of the I2C Master module. +//! +//! \param ulBase base address of the I2C Master module +//! +//! This function is used to obtain the error status of the Master module +//! send and receive operations. It returns one of the following values: +//! +//! - I2C_MASTER_ERR_NONE +//! - I2C_MASTER_ERR_ADDR_ACK +//! - I2C_MASTER_ERR_DATA_ACK +//! - I2C_MASTER_ERR_ARB_LOST +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_mastererr) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +I2CMasterErr(unsigned long ulBase) +{ + unsigned long ulErr; + + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Get the raw error state + // + ulErr = HWREG(ulBase + I2C_MASTER_O_CS); + + // + // If the I2C master is busy, then all the other bit are invalid, and + // don't have an error to report. + // + if(ulErr & I2C_MASTER_CS_BUSY) + { + return(I2C_MASTER_ERR_NONE); + } + + // + // Check for errors. + // + if(ulErr & I2C_MASTER_CS_ERROR) + { + return(ulErr & (I2C_MASTER_CS_ERR_MASK)); + } + else + { + return(I2C_MASTER_ERR_NONE); + } +} +#endif + +//***************************************************************************** +// +//! Transmits a byte from the I2C Master. +//! +//! \param ulBase base address of the I2C Master module +//! \param ucData data to be transmitted from the I2C Master +//! +//! This function will place the supplied data into I2C Master Data Register. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_masterdataput) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CMasterDataPut(unsigned long ulBase, unsigned char ucData) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Write the byte. + // + HWREG(ulBase + I2C_MASTER_O_DR) = ucData; +} +#endif + +//***************************************************************************** +// +//! Receives a byte that has been sent to the I2C Master. +//! +//! \param ulBase base address of the I2C Master module +//! +//! This function reads a byte of data from the I2C Master Data Register. +//! +//! \return Returns the byte received from by the I2C Master, cast as an +//! unsigned long. +// +//***************************************************************************** +#if defined(GROUP_masterdataget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +I2CMasterDataGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Read a byte. + // + return(HWREG(ulBase + I2C_MASTER_O_DR)); +} +#endif + +//***************************************************************************** +// +//! Gets the I2C Slave module status +//! +//! \param ulBase base address of the I2C Slave module +//! +//! This function will return the action requested from a master, if any. The +//! possible values returned are: +//! +//! - I2C_SLAVE_ACT_NONE +//! - I2C_SLAVE_ACT_RREQ +//! - I2C_SLAVE_ACT_TREQ +//! +//! where I2C_SLAVE_ACT_NONE means that no action has been requested of the +//! I2C Slave module, I2C_SLAVE_ACT_RREQ means that an I2C master has sent +//! data to the I2C Slave module, and I2C_SLAVE_ACT_TREQ means that an I2C +//! master has requested that the I2C Slave module send data. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_slavestatus) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +I2CSlaveStatus(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_SLAVE_BASE); + + // + // Return the slave status. + // + return(HWREG(ulBase + I2C_SLAVE_O_CSR)); +} +#endif + +//***************************************************************************** +// +//! Transmits a byte from the I2C Slave. +//! +//! \param ulBase base address of the I2C Slave module +//! \param ucData data to be transmitted from the I2C Slave +//! +//! This function will place the supplied data into I2C Slave Data Register. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_slavedataput) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_SLAVE_BASE); + + // + // Write the byte. + // + HWREG(ulBase + I2C_SLAVE_O_DR) = ucData; +} +#endif + +//***************************************************************************** +// +//! Receives a byte that has been sent to the I2C Slave. +//! +//! \param ulBase base address of the I2C Slave module +//! +//! This function reads a byte of data from the I2C Slave Data Register. +//! +//! \return Returns the byte received from by the I2C Slave, cast as an +//! unsigned long. +// +//***************************************************************************** +#if defined(GROUP_slavedataget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +I2CSlaveDataGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_SLAVE_BASE); + + // + // Read a byte. + // + return(HWREG(ulBase + I2C_SLAVE_O_DR)); +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/i2c.h b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/i2c.h new file mode 100644 index 000000000..bfe8c8563 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/i2c.h @@ -0,0 +1,137 @@ +//***************************************************************************** +// +// i2c.h - Prototypes for the I2C Driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __I2C_H__ +#define __I2C_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Defines for the API. +// +//***************************************************************************** +//***************************************************************************** +// +// Interrupt defines. +// +//***************************************************************************** +#define I2C_INT_MASTER 0x00000001 +#define I2C_INT_SLAVE 0x00000002 + +//***************************************************************************** +// +// I2C Master commands. +// +//***************************************************************************** +#define I2C_MASTER_CMD_SINGLE_SEND \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_SINGLE_RECEIVE \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_SEND_START \ + (I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_SEND_CONT \ + (I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_SEND_FINISH \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \ + (I2C_MASTER_CS_STOP) +#define I2C_MASTER_CMD_BURST_RECEIVE_START \ + (I2C_MASTER_CS_ACK | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \ + (I2C_MASTER_CS_ACK | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) + +//***************************************************************************** +// +// I2C Master error status. +// +//***************************************************************************** +#define I2C_MASTER_ERR_NONE 0 +#define I2C_MASTER_ERR_ADDR_ACK 0x00000004 +#define I2C_MASTER_ERR_DATA_ACK 0x00000008 +#define I2C_MASTER_ERR_ARB_LOST 0x00000010 + +//***************************************************************************** +// +// I2C Slave action requests +// +//***************************************************************************** +#define I2C_SLAVE_ACT_NONE 0 +#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data +#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data + +//***************************************************************************** +// Miscellaneous I2C driver definitions. +//***************************************************************************** +#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void)); +extern void I2CIntUnregister(unsigned long ulBase); +extern tBoolean I2CMasterBusBusy(unsigned long ulBase); +extern tBoolean I2CMasterBusy(unsigned long ulBase); +extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd); +extern unsigned long I2CMasterDataGet(unsigned long ulBase); +extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData); +extern void I2CMasterDisable(unsigned long ulBase); +extern void I2CMasterEnable(unsigned long ulBase); +extern unsigned long I2CMasterErr(unsigned long ulBase); +extern void I2CMasterInit(unsigned long ulBase, tBoolean bFast); +extern void I2CMasterIntClear(unsigned long ulBase); +extern void I2CMasterIntDisable(unsigned long ulBase); +extern void I2CMasterIntEnable(unsigned long ulBase); +extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void I2CMasterSlaveAddrSet(unsigned long ulBase, + unsigned char ucSlaveAddr, + tBoolean bReceive); +extern unsigned long I2CSlaveDataGet(unsigned long ulBase); +extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData); +extern void I2CSlaveDisable(unsigned long ulBase); +extern void I2CSlaveEnable(unsigned long ulBase); +extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr); +extern void I2CSlaveIntClear(unsigned long ulBase); +extern void I2CSlaveIntDisable(unsigned long ulBase); +extern void I2CSlaveIntEnable(unsigned long ulBase); +extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked); +extern unsigned long I2CSlaveStatus(unsigned long ulBase); + +#ifdef __cplusplus +} +#endif + +#endif // __I2C_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/interrupt.c b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/interrupt.c new file mode 100644 index 000000000..7224a05d8 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/interrupt.c @@ -0,0 +1,552 @@ +//***************************************************************************** +// +// interrupt.c - Driver for the NVIC Interrupt Controller. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup interrupt_api +//! @{ +// +//***************************************************************************** + +#include "../hw_ints.h" +#include "../hw_nvic.h" +#include "../hw_types.h" +#include "cpu.h" +#include "debug.h" +#include "interrupt.h" + +//***************************************************************************** +// +// This is a mapping between priority grouping encodings and the number of +// preemption priority bits. +// +//***************************************************************************** +#if defined(GROUP_pulpriority) || defined(BUILD_ALL) +const unsigned long g_pulPriority[] = +{ + NVIC_APINT_PRIGROUP_0_8, NVIC_APINT_PRIGROUP_1_7, NVIC_APINT_PRIGROUP_2_6, + NVIC_APINT_PRIGROUP_3_5, NVIC_APINT_PRIGROUP_4_4, NVIC_APINT_PRIGROUP_5_3, + NVIC_APINT_PRIGROUP_6_2, NVIC_APINT_PRIGROUP_7_1 +}; +#else +extern const unsigned long g_pulPriority[]; +#endif + +//***************************************************************************** +// +// This is a mapping between interrupt number and the register that contains +// the priority encoding for that interrupt. +// +//***************************************************************************** +#if defined(GROUP_pulregs) || defined(BUILD_ALL) +const unsigned long g_pulRegs[12] = +{ + 0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1, + NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7 +}; +#else +extern const unsigned long g_pulRegs[12]; +#endif + +//***************************************************************************** +// +//! \internal +//! The default interrupt handler. +//! +//! This is the default interrupt handler for all interrupts. It simply loops +//! forever so that the system state is preserved for observation by a +//! debugger. Since interrupts should be disabled before unregistering the +//! corresponding handler, this should never be called. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_defaulthandler) || defined(BUILD_ALL) +void +IntDefaultHandler(void) +{ + // + // Go into an infinite loop. + // + while(1) + { + } +} +#else +extern void IntDefaultHandler(void); +#endif + +//***************************************************************************** +// +// The processor vector table. +// +// This contains a list of the handlers for the various interrupt sources in +// the system. The layout of this list is defined by the hardware; assertion +// of an interrupt causes the processor to start executing directly at the +// address given in the corresponding location in this list. +// +//***************************************************************************** +#if defined(GROUP_vtable) || defined(BUILD_ALL) +#ifdef ewarm +__no_init void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) @ "VTABLE"; +#else +__attribute__((section("vtable"))) +void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void); +#endif +#else +extern void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void); +#endif + +//***************************************************************************** +// +//! Enables the processor interrupt. +//! +//! Allows the processor to respond to interrupts. This does not affect the +//! set of interrupts enabled in the interrupt controller; it just gates the +//! single interrupt from the controller to the processor. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_masterenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +IntMasterEnable(void) +{ + // + // Enable processor interrupts. + // + CPUcpsie(); +} +#endif + +//***************************************************************************** +// +//! Disables the processor interrupt. +//! +//! Prevents the processor from receiving interrupts. This does not affect the +//! set of interrupts enabled in the interrupt controller; it just gates the +//! single interrupt from the controller to the processor. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_masterdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +IntMasterDisable(void) +{ + // + // Disable processor interrupts. + // + CPUcpsid(); +} +#endif + +//***************************************************************************** +// +//! Registers a function to be called when an interrupt occurs. +//! +//! \param ulInterrupt specifies the interrupt in question. +//! \param pfnHandler is a pointer to the function to be called. +//! +//! This function is used to specify the handler function to be called when the +//! given interrupt is asserted to the processor. When the interrupt occurs, +//! if it is enabled (via IntEnable()), the handler function will be called in +//! interrupt context. Since the handler function can preempt other code, care +//! must be taken to protect memory or peripherals that are accessed by the +//! handler and other non-handler code. +//! +//! \note The use of this function (directly or indirectly via a peripheral +//! driver interrupt register function) moves the interrupt vector table from +//! flash to SRAM. Therefore, care must be taken when linking the application +//! to ensure that the SRAM vector table is located at the beginning of SRAM; +//! otherwise NVIC will not look in the correct portion of memory for the +//! vector table (it requires the vector table be on a 1 kB memory alignment). +//! Normally, the SRAM vector table is so placed via the use of linker scripts; +//! some tool chains, such as the evaluation version of RV-MDK, do not support +//! linker scripts and therefore will not produce a valid executable. See the +//! discussion of compile-time versus run-time interrupt handler registration +//! in the introduction to this chapter. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_register) || defined(BUILD_ALL) || defined(DOXYGEN) +void +IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)) +{ + unsigned long ulIdx; + + // + // Check the arguments. + // + ASSERT(ulInterrupt < NUM_INTERRUPTS); + + // + // Make sure that the RAM vector table is correctly aligned. + // + ASSERT(((unsigned long)g_pfnRAMVectors & 0x000003ff) == 0); + + // + // See if the RAM vector table has been initialized. + // + if(HWREG(NVIC_VTABLE) != (unsigned long)g_pfnRAMVectors) + { + // + // Copy the vector table from the beginning of FLASH to the RAM vector + // table. + // + for(ulIdx = 0; ulIdx < NUM_INTERRUPTS; ulIdx++) + { + g_pfnRAMVectors[ulIdx] = (void (*)(void))HWREG(ulIdx * 4); + } + + // + // Point NVIC at the RAM vector table. + // + HWREG(NVIC_VTABLE) = (unsigned long)g_pfnRAMVectors; + } + + // + // Save the interrupt handler. + // + g_pfnRAMVectors[ulInterrupt] = pfnHandler; +} +#endif + +//***************************************************************************** +// +//! Unregisters the function to be called when an interrupt occurs. +//! +//! \param ulInterrupt specifies the interrupt in question. +//! +//! This function is used to indicate that no handler should be called when the +//! given interrupt is asserted to the processor. The interrupt source will be +//! automatically disabled (via IntDisable()) if necessary. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_unregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +IntUnregister(unsigned long ulInterrupt) +{ + // + // Check the arguments. + // + ASSERT(ulInterrupt < NUM_INTERRUPTS); + + // + // Reset the interrupt handler. + // + g_pfnRAMVectors[ulInterrupt] = IntDefaultHandler; +} +#endif + +//***************************************************************************** +// +//! Sets the priority grouping of the interrupt controller. +//! +//! \param ulBits specifies the number of bits of preemptable priority. +//! +//! This function specifies the split between preemptable priority levels and +//! subpriority levels in the interrupt priority specification. The range of +//! the grouping values are dependent upon the hardware implementation; on +//! the Stellaris family it can range from 0 to 3. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_prioritygroupingset) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +IntPriorityGroupingSet(unsigned long ulBits) +{ + // + // Check the arguments. + // + ASSERT(ulBits < NUM_PRIORITY_BITS); + + // + // Set the priority grouping. + // + HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | g_pulPriority[ulBits]; +} +#endif + +//***************************************************************************** +// +//! Gets the priority grouping of the interrupt controller. +//! +//! This function returns the split between preemptable priority levels and +//! subpriority levels in the interrupt priority specification. +//! +//! \return The number of bits of preemptable priority. +// +//***************************************************************************** +#if defined(GROUP_prioritygroupingget) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +unsigned long +IntPriorityGroupingGet(void) +{ + unsigned long ulLoop, ulValue; + + // + // Read the priority grouping. + // + ulValue = HWREG(NVIC_APINT) & NVIC_APINT_PRIGROUP_M; + + // + // Loop through the priority grouping values. + // + for(ulLoop = 0; ulLoop < 8; ulLoop++) + { + // + // Stop looping if this value matches. + // + if(ulValue == g_pulPriority[ulLoop]) + { + break; + } + } + + // + // Return the number of priority bits. + // + return(ulLoop); +} +#endif + +//***************************************************************************** +// +//! Sets the priority of an interrupt. +//! +//! \param ulInterrupt specifies the interrupt in question. +//! \param ucPriority specifies the priority of the interrupt. +//! +//! This function is used to set the priority of an interrupt. When multiple +//! interrupts are asserted simultaneously, the ones with the highest priority +//! are processed before the lower priority interrupts. Smaller numbers +//! correspond to higher interrupt priorities; priority 0 is the highest +//! interrupt priority. +//! +//! The hardware priority mechanism will only look at the upper N bits of the +//! priority level (where N is 3 for the Stellaris family), so any +//! prioritization must be performed in those bits. The remaining bits can be +//! used to sub-prioritize the interrupt sources, and may be used by the +//! hardware priority mechanism on a future part. This arrangement allows +//! priorities to migrate to different NVIC implementations without changing +//! the gross prioritization of the interrupts. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_priorityset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +IntPrioritySet(unsigned long ulInterrupt, unsigned char ucPriority) +{ + unsigned long ulTemp; + + // + // Check the arguments. + // + ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS)); + + // + // Set the interrupt priority. + // + ulTemp = HWREG(g_pulRegs[ulInterrupt >> 2]); + ulTemp &= ~(0xFF << (8 * (ulInterrupt & 3))); + ulTemp |= ucPriority << (8 * (ulInterrupt & 3)); + HWREG(g_pulRegs[ulInterrupt >> 2]) = ulTemp; +} +#endif + +//***************************************************************************** +// +//! Gets the priority of an interrupt. +//! +//! \param ulInterrupt specifies the interrupt in question. +//! +//! This function gets the priority of an interrupt. See IntPrioritySet() for +//! a definition of the priority value. +//! +//! \return Returns the interrupt priority, or -1 if an invalid interrupt was +//! specified. +// +//***************************************************************************** +#if defined(GROUP_priorityget) || defined(BUILD_ALL) || defined(DOXYGEN) +long +IntPriorityGet(unsigned long ulInterrupt) +{ + // + // Check the arguments. + // + ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS)); + + // + // Return the interrupt priority. + // + return((HWREG(g_pulRegs[ulInterrupt >> 2]) >> (8 * (ulInterrupt & 3))) & + 0xFF); +} +#endif + +//***************************************************************************** +// +//! Enables an interrupt. +//! +//! \param ulInterrupt specifies the interrupt to be enabled. +//! +//! The specified interrupt is enabled in the interrupt controller. Other +//! enables for the interrupt (such as at the peripheral level) are unaffected +//! by this function. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +IntEnable(unsigned long ulInterrupt) +{ + // + // Check the arguments. + // + ASSERT(ulInterrupt < NUM_INTERRUPTS); + + // + // Determine the interrupt to enable. + // + if(ulInterrupt == FAULT_MPU) + { + // + // Enable the MemManage interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_MEM; + } + else if(ulInterrupt == FAULT_BUS) + { + // + // Enable the bus fault interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_BUS; + } + else if(ulInterrupt == FAULT_USAGE) + { + // + // Enable the usage fault interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_USAGE; + } + else if(ulInterrupt == FAULT_SYSTICK) + { + // + // Enable the System Tick interrupt. + // + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; + } + else if(ulInterrupt >= INT_GPIOA) + { + // + // Enable the general interrupt. + // + HWREG(NVIC_EN0) = 1 << (ulInterrupt - INT_GPIOA); + } +} +#endif + +//***************************************************************************** +// +//! Disables an interrupt. +//! +//! \param ulInterrupt specifies the interrupt to be disabled. +//! +//! The specified interrupt is disabled in the interrupt controller. Other +//! enables for the interrupt (such as at the peripheral level) are unaffected +//! by this function. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +IntDisable(unsigned long ulInterrupt) +{ + // + // Check the arguments. + // + ASSERT(ulInterrupt < NUM_INTERRUPTS); + + // + // Determine the interrupt to disable. + // + if(ulInterrupt == FAULT_MPU) + { + // + // Disable the MemManage interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_MEM); + } + else if(ulInterrupt == FAULT_BUS) + { + // + // Disable the bus fault interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_BUS); + } + else if(ulInterrupt == FAULT_USAGE) + { + // + // Disable the usage fault interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_USAGE); + } + else if(ulInterrupt == FAULT_SYSTICK) + { + // + // Disable the System Tick interrupt. + // + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); + } + else if(ulInterrupt >= INT_GPIOA) + { + // + // Disable the general interrupt. + // + HWREG(NVIC_DIS0) = 1 << (ulInterrupt - INT_GPIOA); + } +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/interrupt.h b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/interrupt.h new file mode 100644 index 000000000..37d414dab --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/interrupt.h @@ -0,0 +1,57 @@ +//***************************************************************************** +// +// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void IntMasterEnable(void); +extern void IntMasterDisable(void); +extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)); +extern void IntUnregister(unsigned long ulInterrupt); +extern void IntPriorityGroupingSet(unsigned long ulBits); +extern unsigned long IntPriorityGroupingGet(void); +extern void IntPrioritySet(unsigned long ulInterrupt, + unsigned char ucPriority); +extern long IntPriorityGet(unsigned long ulInterrupt); +extern void IntEnable(unsigned long ulInterrupt); +extern void IntDisable(unsigned long ulInterrupt); + +#ifdef __cplusplus +} +#endif + +#endif // __INTERRUPT_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/libdriver.a b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/libdriver.a new file mode 100644 index 0000000000000000000000000000000000000000..85385dcf1a336a1677b09502467c8df716bd416e GIT binary patch literal 246310 zcmeFa3v?XEc_vyt15zM3CP9(5Acj^3B;`;tMGhXs!%NMpFlas`~ry>Uw?s|Ml0S8*lH+4GjH!-PUB-H8r)T zIyzEKtu4u9%D<%lPbRmuw>8T2fi=FFVnq!IU%y^g&1BT#EJI^G2So4#K(oW z?;Aoq_?!^G@_8XnJ}tx}r-bxU3-LJJ`{#81|E?9{$-_eY)deB``r|_U z?Rg>oo}T&r>xK9MrTg45AuiIhUZ8yb%TI-P`A>xSF_r1ncM0*ozArrQv%;(S6XDhV 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0x41, 0x00 }, // I + { 0x20, 0x40, 0x41, 0x3f, 0x01 }, // J + { 0x7f, 0x08, 0x14, 0x22, 0x41 }, // K + { 0x7f, 0x40, 0x40, 0x40, 0x40 }, // L + { 0x7f, 0x02, 0x0c, 0x02, 0x7f }, // M + { 0x7f, 0x04, 0x08, 0x10, 0x7f }, // N + { 0x3e, 0x41, 0x41, 0x41, 0x3e }, // O + { 0x7f, 0x09, 0x09, 0x09, 0x06 }, // P + { 0x3e, 0x41, 0x51, 0x21, 0x5e }, // Q + { 0x7f, 0x09, 0x19, 0x29, 0x46 }, // R + { 0x46, 0x49, 0x49, 0x49, 0x31 }, // S + { 0x01, 0x01, 0x7f, 0x01, 0x01 }, // T + { 0x3f, 0x40, 0x40, 0x40, 0x3f }, // U + { 0x1f, 0x20, 0x40, 0x20, 0x1f }, // V + { 0x3f, 0x40, 0x38, 0x40, 0x3f }, // W + { 0x63, 0x14, 0x08, 0x14, 0x63 }, // X + { 0x07, 0x08, 0x70, 0x08, 0x07 }, // Y + { 0x61, 0x51, 0x49, 0x45, 0x43 }, // Z + { 0x00, 0x7f, 0x41, 0x41, 0x00 }, // [ + { 0x02, 0x04, 0x08, 0x10, 0x20 }, // "\" + { 0x00, 0x41, 0x41, 0x7f, 0x00 }, // ] + { 0x04, 0x02, 0x01, 0x02, 0x04 }, // ^ + { 0x40, 0x40, 0x40, 0x40, 0x40 }, // _ + { 0x00, 0x01, 0x02, 0x04, 0x00 }, // ` + { 0x20, 0x54, 0x54, 0x54, 0x78 }, // a + { 0x7f, 0x48, 0x44, 0x44, 0x38 }, // b + { 0x38, 0x44, 0x44, 0x44, 0x20 }, // c + { 0x38, 0x44, 0x44, 0x48, 0x7f }, // d + { 0x38, 0x54, 0x54, 0x54, 0x18 }, // e + { 0x08, 0x7e, 0x09, 0x01, 0x02 }, // f + { 0x0c, 0x52, 0x52, 0x52, 0x3e }, // g + { 0x7f, 0x08, 0x04, 0x04, 0x78 }, // h + { 0x00, 0x44, 0x7d, 0x40, 0x00 }, // i + { 0x20, 0x40, 0x44, 0x3d, 0x00 }, // j + { 0x7f, 0x10, 0x28, 0x44, 0x00 }, // k + { 0x00, 0x41, 0x7f, 0x40, 0x00 }, // l + { 0x7c, 0x04, 0x18, 0x04, 0x78 }, // m + { 0x7c, 0x08, 0x04, 0x04, 0x78 }, // n + { 0x38, 0x44, 0x44, 0x44, 0x38 }, // o + { 0x7c, 0x14, 0x14, 0x14, 0x08 }, // p + { 0x08, 0x14, 0x14, 0x18, 0x7c }, // q + { 0x7c, 0x08, 0x04, 0x04, 0x08 }, // r + { 0x48, 0x54, 0x54, 0x54, 0x20 }, // s + { 0x04, 0x3f, 0x44, 0x40, 0x20 }, // t + { 0x3c, 0x40, 0x40, 0x20, 0x7c }, // u + { 0x1c, 0x20, 0x40, 0x20, 0x1c }, // v + { 0x3c, 0x40, 0x30, 0x40, 0x3c }, // w + { 0x44, 0x28, 0x10, 0x28, 0x44 }, // x + { 0x0c, 0x50, 0x50, 0x50, 0x3c }, // y + { 0x44, 0x64, 0x54, 0x4c, 0x44 }, // z + { 0x00, 0x08, 0x36, 0x41, 0x00 }, // { + { 0x00, 0x00, 0x7f, 0x00, 0x00 }, // | + { 0x00, 0x41, 0x36, 0x08, 0x00 }, // } + { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~ +}; + +//***************************************************************************** +// +// The sequence of commands used to initialize the SSD0303 controller. Each +// command is described as follows: there is a byte specifying the number of +// bytes in the I2C transfer, followed by that many bytes of command data. +// +//***************************************************************************** +static const unsigned char g_pucOSRAMInit[] = +{ + // + // Turn off the panel + // + 0x04, 0x80, 0xae, 0x80, 0xe3, + + // + // Set lower column address + // + 0x04, 0x80, 0x04, 0x80, 0xe3, + + // + // Set higher column address + // + 0x04, 0x80, 0x12, 0x80, 0xe3, + + // + // Set contrast control register + // + 0x06, 0x80, 0x81, 0x80, 0x2b, 0x80, 0xe3, + + // + // Set segment re-map + // + 0x04, 0x80, 0xa1, 0x80, 0xe3, + + // + // Set display start line + // + 0x04, 0x80, 0x40, 0x80, 0xe3, + + // + // Set display offset + // + 0x06, 0x80, 0xd3, 0x80, 0x00, 0x80, 0xe3, + + // + // Set multiplex ratio + // + 0x06, 0x80, 0xa8, 0x80, 0x0f, 0x80, 0xe3, + + // + // Set the display to normal mode + // + 0x04, 0x80, 0xa4, 0x80, 0xe3, + + // + // Non-inverted display + // + 0x04, 0x80, 0xa6, 0x80, 0xe3, + + // + // Set the page address + // + 0x04, 0x80, 0xb0, 0x80, 0xe3, + + // + // Set COM output scan direction + // + 0x04, 0x80, 0xc8, 0x80, 0xe3, + + // + // Set display clock divide ratio/oscillator frequency + // + 0x06, 0x80, 0xd5, 0x80, 0x72, 0x80, 0xe3, + + // + // Enable mono mode + // + 0x06, 0x80, 0xd8, 0x80, 0x00, 0x80, 0xe3, + + // + // Set pre-charge period + // + 0x06, 0x80, 0xd9, 0x80, 0x22, 0x80, 0xe3, + + // + // Set COM pins hardware configuration + // + 0x06, 0x80, 0xda, 0x80, 0x12, 0x80, 0xe3, + + // + // Set VCOM deslect level + // + 0x06, 0x80, 0xdb, 0x80, 0x0f, 0x80, 0xe3, + + // + // Set DC-DC on + // + 0x06, 0x80, 0xad, 0x80, 0x8b, 0x80, 0xe3, + + // + // Turn on the panel + // + 0x04, 0x80, 0xaf, 0x80, 0xe3, +}; + +//***************************************************************************** +// +// The inter-byte delay required by the SSD0303 OLED controller. +// +//***************************************************************************** +static unsigned long g_ulDelay; + +//***************************************************************************** +// +//! \internal +//! +//! Provide a small delay. +//! +//! \param ulCount is the number of delay loop iterations to perform. +//! +//! Since the SSD0303 controller needs a delay between bytes written to it over +//! the I2C bus, this function provides a means of generating that delay. It +//! is written in assembly to keep the delay consistent across tool chains, +//! avoiding the need to tune the delay based on the tool chain in use. +//! +//! \return None. +// +//***************************************************************************** +#if defined(ewarm) +static void +OSRAMDelay(unsigned long ulCount) +{ + __asm(" subs r0, #1\n" + " bne OSRAMDelay\n" + " bx lr"); +} +#endif +#if defined(gcc) +static void __attribute__((naked)) +OSRAMDelay(unsigned long ulCount) +{ + __asm(" subs r0, #1\n" + " bne OSRAMDelay\n" + " bx lr"); +} +#endif +#if defined(rvmdk) || defined(__ARMCC_VERSION) +__asm void +OSRAMDelay(unsigned long ulCount) +{ + subs r0, #1; + bne OSRAMDelay; + bx lr; +} +#endif + +//***************************************************************************** +// +//! \internal +//! +//! Start a transfer to the SSD0303 controller. +//! +//! \param ucChar is the first byte to be written to the controller. +//! +//! This function will start a transfer to the SSD0303 controller via the I2C +//! bus. +//! +//! The data is written in a polled fashion; this function will not return +//! until the byte has been written to the controller. +//! +//! \return None. +// +//***************************************************************************** +static void +OSRAMWriteFirst(unsigned char ucChar) +{ + // + // Set the slave address. + // + I2CMasterSlaveAddrSet(I2C_MASTER_BASE, SSD0303_ADDR, false); + + // + // Write the first byte to the controller. + // + I2CMasterDataPut(I2C_MASTER_BASE, ucChar); + + // + // Start the transfer. + // + I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_START); +} + +//***************************************************************************** +// +//! \internal +//! +//! Write a byte to the SSD0303 controller. +//! +//! \param ucChar is the byte to be transmitted to the controller. +//! +//! This function continues a transfer to the SSD0303 controller by writing +//! another byte over the I2C bus. This must only be called after calling +//! OSRAMWriteFirst(), but before calling OSRAMWriteFinal(). +//! +//! The data is written in a polled faashion; this function will not return +//! until the byte has been written to the controller. +//! +//! \return None. +// +//***************************************************************************** +static void +OSRAMWriteByte(unsigned char ucChar) +{ + // + // Wait until the current byte has been transferred. + // + while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0) + { + } + + // + // Provide the required inter-byte delay. + // + OSRAMDelay(g_ulDelay); + + // + // Write the next byte to the controller. + // + I2CMasterDataPut(I2C_MASTER_BASE, ucChar); + + // + // Continue the transfer. + // + I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_CONT); +} + +//***************************************************************************** +// +//! \internal +//! +//! Write a sequence of bytes to the SSD0303 controller. +//! +//! This function continues a transfer to the SSD0303 controller by writing a +//! sequence of bytes over the I2C bus. This must only be called after calling +//! OSRAMWriteFirst(), but before calling OSRAMWriteFinal(). +//! +//! The data is written in a polled fashion; this function will not return +//! until the entire byte sequence has been written to the controller. +//! +//! \return None. +// +//***************************************************************************** +static void +OSRAMWriteArray(const unsigned char *pucBuffer, unsigned long ulCount) +{ + // + // Loop while there are more bytes left to be transferred. + // + while(ulCount != 0) + { + // + // Wait until the current byte has been transferred. + // + while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0) + { + } + + // + // Provide the required inter-byte delay. + // + OSRAMDelay(g_ulDelay); + + // + // Write the next byte to the controller. + // + I2CMasterDataPut(I2C_MASTER_BASE, *pucBuffer++); + ulCount--; + + // + // Continue the transfer. + // + I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_CONT); + } +} + +//***************************************************************************** +// +//! \internal +//! +//! Finish a transfer to the SSD0303 controller. +//! +//! \param ucChar is the final byte to be written to the controller. +//! +//! This function will finish a transfer to the SSD0303 controller via the I2C +//! bus. This must only be called after calling OSRAMWriteFirst(). +//! +//! The data is written in a polled fashion; this function will not return +//! until the byte has been written to the controller. +//! +//! \return None. +// +//***************************************************************************** +static void +OSRAMWriteFinal(unsigned char ucChar) +{ + // + // Wait until the current byte has been transferred. + // + while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0) + { + } + + // + // Provide the required inter-byte delay. + // + OSRAMDelay(g_ulDelay); + + // + // Write the final byte to the controller. + // + I2CMasterDataPut(I2C_MASTER_BASE, ucChar); + + // + // Finish the transfer. + // + I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_FINISH); + + // + // Wait until the final byte has been transferred. + // + while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0) + { + } + + // + // Provide the required inter-byte delay. + // + OSRAMDelay(g_ulDelay); +} + +//***************************************************************************** +// +//! Clears the OLED display. +//! +//! This function will clear the display. All pixels in the display will be +//! turned off. +//! +//! This function is contained in osram96x16.c, with +//! osram96x16.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAMClear(void) +{ + static const unsigned char pucRow1[] = + { + 0xb0, 0x80, 0x04, 0x80, 0x12, 0x40 + }; + static const unsigned char pucRow2[] = + { + 0xb1, 0x80, 0x04, 0x80, 0x12, 0x40 + }; + unsigned long ulIdx; + + // + // Move the display cursor to the first column of the first row. + // + OSRAMWriteFirst(0x80); + OSRAMWriteArray(pucRow1, sizeof(pucRow1)); + + // + // Fill this row with zeros. + // + for(ulIdx = 0; ulIdx < 95; ulIdx++) + { + OSRAMWriteByte(0x00); + } + OSRAMWriteFinal(0x00); + + // + // Move the display cursor to the first column of the second row. + // + OSRAMWriteFirst(0x80); + OSRAMWriteArray(pucRow2, sizeof(pucRow2)); + + // + // Fill this row with zeros. + // + for(ulIdx = 0; ulIdx < 95; ulIdx++) + { + OSRAMWriteByte(0x00); + } + OSRAMWriteFinal(0x00); +} + +//***************************************************************************** +// +//! Displays a string on the OLED display. +//! +//! \param pcStr is a pointer to the string to display. +//! \param ulX is the horizontal position to display the string, specified in +//! columns from the left edge of the display. +//! \param ulY is the vertical position to display the string, specified in +//! eight scan line blocks from the top of the display (i.e. only 0 and 1 are +//! valid). +//! +//! This function will draw a string on the display. Only the ASCII characters +//! between 32 (space) and 126 (tilde) are supported; other characters will +//! result in random data being draw on the display (based on whatever appears +//! before/after the font in memory). The font is mono-spaced, so characters +//! such as "i" and "l" have more white space around them than characters such +//! as "m" or "w". +//! +//! If the drawing of the string reaches the right edge of the display, no more +//! characters will be drawn. Therefore, special care is not required to avoid +//! supplying a string that is "too long" to display. +//! +//! This function is contained in osram96x16.c, with +//! osram96x16.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAMStringDraw(const char *pcStr, unsigned long ulX, unsigned long ulY) +{ + // + // Check the arguments. + // + ASSERT(ulX < 96); + ASSERT(ulY < 2); + + // + // Move the display cursor to the requested position on the display. + // + OSRAMWriteFirst(0x80); + OSRAMWriteByte((ulY == 0) ? 0xb0 : 0xb1); + OSRAMWriteByte(0x80); + OSRAMWriteByte((ulX + 36) & 0x0f); + OSRAMWriteByte(0x80); + OSRAMWriteByte(0x10 | (((ulX + 36) >> 4) & 0x0f)); + OSRAMWriteByte(0x40); + + // + // Loop while there are more characters in the string. + // + while(*pcStr != 0) + { + // + // See if there is enough space on the display for this entire + // character. + // + if(ulX <= 90) + { + // + // Write the contents of this character to the display. + // + OSRAMWriteArray(g_pucFont[*pcStr - ' '], 5); + + // + // See if this is the last character to display (either because the + // right edge has been reached or because there are no more + // characters). + // + if((ulX == 90) || (pcStr[1] == 0)) + { + // + // Write the final column of the display. + // + OSRAMWriteFinal(0x00); + + // + // The string has been displayed. + // + return; + } + + // + // Write the inter-character padding column. + // + OSRAMWriteByte(0x00); + } + else + { + // + // Write the portion of the character that will fit onto the + // display. + // + OSRAMWriteArray(g_pucFont[*pcStr - ' '], 95 - ulX); + OSRAMWriteFinal(g_pucFont[*pcStr - ' '][95 - ulX]); + + // + // The string has been displayed. + // + return; + } + + // + // Advance to the next character. + // + pcStr++; + + // + // Increment the X coordinate by the six columns that were just + // written. + // + ulX += 6; + } +} + +//***************************************************************************** +// +//! Displays an image on the OLED display. +//! +//! \param pucImage is a pointer to the image data. +//! \param ulX is the horizontal position to display this image, specified in +//! columns from the left edge of the display. +//! \param ulY is the vertical position to display this image, specified in +//! eight scan line blocks from the top of the display (i.e. only 0 and 1 are +//! valid). +//! \param ulWidth is the width of the image, specified in columns. +//! \param ulHeight is the height of the image, specified in eight row blocks +//! (i.e. only 1 and 2 are valid). +//! +//! This function will display a bitmap graphic on the display. The image to +//! be displayed must be a multiple of eight scan lines high (i.e. one row) and +//! will be drawn at a vertical position that is a multiple of eight scan lines +//! (i.e. scan line zero or scan line eight, corresponding to row zero or row +//! one). +//! +//! The image data is organized with the first row of image data appearing left +//! to right, followed immediately by the second row of image data. Each byte +//! contains the data for the eight scan lines of the column, with the top scan +//! line being in the least significant bit of the byte and the bottom scan +//! line being in the most significant bit of the byte. +//! +//! For example, an image four columns wide and sixteen scan lines tall would +//! be arranged as follows (showing how the eight bytes of the image would +//! appear on the display): +//! +//! \verbatim +//! +-------+ +-------+ +-------+ +-------+ +//! | | 0 | | | 0 | | | 0 | | | 0 | +//! | B | 1 | | B | 1 | | B | 1 | | B | 1 | +//! | y | 2 | | y | 2 | | y | 2 | | y | 2 | +//! | t | 3 | | t | 3 | | t | 3 | | t | 3 | +//! | e | 4 | | e | 4 | | e | 4 | | e | 4 | +//! | | 5 | | | 5 | | | 5 | | | 5 | +//! | 0 | 6 | | 1 | 6 | | 2 | 6 | | 3 | 6 | +//! | | 7 | | | 7 | | | 7 | | | 7 | +//! +-------+ +-------+ +-------+ +-------+ +//! +//! +-------+ +-------+ +-------+ +-------+ +//! | | 0 | | | 0 | | | 0 | | | 0 | +//! | B | 1 | | B | 1 | | B | 1 | | B | 1 | +//! | y | 2 | | y | 2 | | y | 2 | | y | 2 | +//! | t | 3 | | t | 3 | | t | 3 | | t | 3 | +//! | e | 4 | | e | 4 | | e | 4 | | e | 4 | +//! | | 5 | | | 5 | | | 5 | | | 5 | +//! | 4 | 6 | | 5 | 6 | | 6 | 6 | | 7 | 6 | +//! | | 7 | | | 7 | | | 7 | | | 7 | +//! +-------+ +-------+ +-------+ +-------+ +//! \endverbatim +//! +//! This function is contained in osram96x16.c, with +//! osram96x16.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAMImageDraw(const unsigned char *pucImage, unsigned long ulX, + unsigned long ulY, unsigned long ulWidth, + unsigned long ulHeight) +{ + // + // Check the arguments. + // + ASSERT(ulX < 96); + ASSERT(ulY < 2); + ASSERT((ulX + ulWidth) <= 96); + ASSERT((ulY + ulHeight) <= 2); + + // + // The first 36 columns of the LCD buffer are not displayed, so increment + // the X coorddinate by 36 to account for the non-displayed frame buffer + // memory. + // + ulX += 36; + + // + // Loop while there are more rows to display. + // + while(ulHeight--) + { + // + // Write the starting address within this row. + // + OSRAMWriteFirst(0x80); + OSRAMWriteByte((ulY == 0) ? 0xb0 : 0xb1); + OSRAMWriteByte(0x80); + OSRAMWriteByte(ulX & 0x0f); + OSRAMWriteByte(0x80); + OSRAMWriteByte(0x10 | ((ulX >> 4) & 0x0f)); + OSRAMWriteByte(0x40); + + // + // Write this row of image data. + // + OSRAMWriteArray(pucImage, ulWidth - 1); + OSRAMWriteFinal(pucImage[ulWidth - 1]); + + // + // Advance to the next row of the image. + // + pucImage += ulWidth; + ulY++; + } +} + +//***************************************************************************** +// +//! Initialize the OLED display. +//! +//! \param bFast is a boolean that is \e true if the I2C interface should be +//! run at 400 kbps and \e false if it should be run at 100 kbps. +//! +//! This function initializes the I2C interface to the OLED display and +//! configures the SSD0303 controller on the panel. +//! +//! This function is contained in osram96x16.c, with +//! osram96x16.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAMInit(tBoolean bFast) +{ + unsigned long ulIdx; + + // + // Enable the I2C and GPIO port B blocks as they are needed by this driver. + // + SysCtlPeripheralEnable(SYSCTL_PERIPH_I2C); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB); + + // + // Configure the I2C SCL and SDA pins for I2C operation. + // + GPIOPinTypeI2C(GPIO_PORTB_BASE, GPIO_PIN_2 | GPIO_PIN_3); + + // + // Initialize the I2C master. + // + I2CMasterInit(I2C_MASTER_BASE, bFast); + + // + // Compute the inter-byte delay for the SSD0303 controller. This delay is + // dependent upon the I2C bus clock rate; the slower the clock the longer + // the delay required. + // + // The derivation of this formula is based on a measured delay of + // OSRAMDelay(1700) for a 100 kHz I2C bus with the CPU running at 50 MHz + // (referred to as C). To scale this to the delay for a different CPU + // speed (since this is just a CPU-based delay loop) is: + // + // f(CPU) + // C * ---------- + // 50,000,000 + // + // To then scale this to the actual I2C rate (since it won't always be + // precisely 100 kHz): + // + // f(CPU) 100,000 + // C * ---------- * ------- + // 50,000,000 f(I2C) + // + // This equation will give the inter-byte delay required for any + // configuration of the I2C master. But, as arranged it is impossible to + // directly compute in 32-bit arithmetic (without loosing a lot of + // accuracy). So, the equation is simplified. + // + // Since f(I2C) is generated by dividing down from f(CPU), replace it with + // the equivalent (where TPR is the value programmed into the Master Timer + // Period Register of the I2C master, with the 1 added back): + // + // 100,000 + // f(CPU) ------- + // C * ---------- * f(CPU) + // 50,000,000 ------------ + // 2 * 10 * TPR + // + // Inverting the dividend in the last term: + // + // f(CPU) 100,000 * 2 * 10 * TPR + // C * ---------- * ---------------------- + // 50,000,000 f(CPU) + // + // The f(CPU) now cancels out. + // + // 100,000 * 2 * 10 * TPR + // C * ---------------------- + // 50,000,000 + // + // Since there are no clock frequencies left in the equation, this equation + // also works for 400 kHz bus operation as well, since the 100,000 in the + // numerator becomes 400,000 but C is 1/4, which cancel out each other. + // Reducing the constants gives: + // + // TPR TPR TPR + // C * --- = 1700 * --- = 340 * --- = 68 * TPR + // 25 25 5 + // + // Note that the constant C is actually a bit larger than it needs to be in + // order to provide some safety margin. + // + g_ulDelay = 68 * (HWREG(I2C_MASTER_BASE + I2C_MASTER_O_TPR) + 1); + + // + // Initialize the SSD0303 controller. Loop through the initialization + // sequence doing a single I2C transfer for each command. + // + for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAMInit); + ulIdx += g_pucOSRAMInit[ulIdx] + 1) + { + // + // Send this command. + // + OSRAMWriteFirst(g_pucOSRAMInit[ulIdx + 1]); + OSRAMWriteArray(g_pucOSRAMInit + ulIdx + 2, g_pucOSRAMInit[ulIdx] - 2); + OSRAMWriteFinal(g_pucOSRAMInit[ulIdx + g_pucOSRAMInit[ulIdx]]); + } + + // + // Clear the frame buffer. + // + OSRAMClear(); +} + +//***************************************************************************** +// +//! Turns on the OLED display. +//! +//! This function will turn on the OLED display, causing it to display the +//! contents of its internal frame buffer. +//! +//! This function is contained in osram96x16.c, with +//! osram96x16.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAMDisplayOn(void) +{ + unsigned long ulIdx; + + // + // Re-initialize the SSD0303 controller. Loop through the initialization + // sequence doing a single I2C transfer for each command. + // + for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAMInit); + ulIdx += g_pucOSRAMInit[ulIdx] + 1) + { + // + // Send this command. + // + OSRAMWriteFirst(g_pucOSRAMInit[ulIdx + 1]); + OSRAMWriteArray(g_pucOSRAMInit + ulIdx + 2, g_pucOSRAMInit[ulIdx] - 2); + OSRAMWriteFinal(g_pucOSRAMInit[ulIdx + g_pucOSRAMInit[ulIdx]]); + } +} + +//***************************************************************************** +// +//! Turns off the OLED display. +//! +//! This function will turn off the OLED display. This will stop the scanning +//! of the panel and turn off the on-chip DC-DC converter, preventing damage to +//! the panel due to burn-in (it has similar characters to a CRT in this +//! respect). +//! +//! This function is contained in osram96x16.c, with +//! osram96x16.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAMDisplayOff(void) +{ + // + // Turn off the DC-DC converter and the display. + // + OSRAMWriteFirst(0x80); + OSRAMWriteByte(0xae); + OSRAMWriteByte(0x80); + OSRAMWriteByte(0xad); + OSRAMWriteByte(0x80); + OSRAMWriteFinal(0x8a); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/osram96x16.h b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/osram96x16.h new file mode 100644 index 000000000..0c9cd3692 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/osram96x16.h @@ -0,0 +1,47 @@ +//***************************************************************************** +// +// osram96x16.h - Prototypes for the driver for the OSRAM 96x16 graphical OLED +// display. +// +// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __OSRAM96X16_H__ +#define __OSRAM96X16_H__ + +//***************************************************************************** +// +// Prototypes for the driver APIs. +// +//***************************************************************************** +extern void OSRAMClear(void); +extern void OSRAMStringDraw(const char *pcStr, unsigned long ulX, + unsigned long ulY); +extern void OSRAMImageDraw(const unsigned char *pucImage, unsigned long ulX, + unsigned long ulY, unsigned long ulWidth, + unsigned long ulHeight); +extern void OSRAMInit(tBoolean bFast); +extern void OSRAMDisplayOn(void); +extern void OSRAMDisplayOff(void); + +#endif // __OSRAM96X16_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/pwm.c b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/pwm.c new file mode 100644 index 000000000..6697566ea --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/pwm.c @@ -0,0 +1,1291 @@ +//***************************************************************************** +// +// pwm.c - API for the PWM modules +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup pwm_api +//! @{ +// +//***************************************************************************** + +#include "../hw_ints.h" +#include "../hw_memmap.h" +#include "../hw_pwm.h" +#include "../hw_types.h" +#include "debug.h" +#include "interrupt.h" +#include "pwm.h" + +//***************************************************************************** +// +// Misc macros for manipulating the encoded generator and output defines used +// by the API. +// +//***************************************************************************** +#define PWM_GEN_BADDR(_mod_, _gen_) \ + ((_mod_) + (_gen_)) +#define PWM_OUT_BADDR(_mod_, _out_) \ + ((_mod_) + ((_out_) & 0xFFFFFFC0)) +#define PWM_IS_OUTPUT_ODD(_out_) \ + ((_out_) & 0x00000001) + +//***************************************************************************** +// +//! Configures a PWM generator. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to configure. Must be one of +//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. +//! \param ulConfig is the configuration for the PWM generator. +//! +//! This function is used to set the mode of operation for a PWM generator. +//! The counting mode, synchronization mode, and debug behavior are all +//! configured. After configuration, the generator is left in the disabled +//! state. +//! +//! A PWM generator can count in two different modes: count down mode or count +//! up/down mode. In count down mode, it will count from a value down to zero, +//! and then reset to the preset value. This will produce left-aligned PWM +//! signals (i.e. the rising edge of the two PWM signals produced by the +//! generator will occur at the same time). In count up/down mode, it will +//! count up from zero to the preset value, count back down to zero, and then +//! repeat the process. This will produce center-aligned PWM signals (i.e. the +//! middle of the high/low period of the PWM signals produced by the generator +//! will occur at the same time). +//! +//! When the PWM generator parameters (period and pulse width) are modified, +//! their affect on the output PWM signals can be delayed. In synchronous +//! mode, the parameter updates are not applied until a synchronization event +//! occurs. This allows multiple parameters to be modified and take affect +//! simultaneously, instead of one at a time. Additionally, parameters to +//! multiple PWM generators in synchronous mode can be updated simultaneously, +//! allowing them to be treated as if they were a unified generator. In +//! non-synchronous mode, the parameter updates are not delayed until a +//! synchronization event. In either mode, the parameter updates only occur +//! when the counter is at zero to help prevent oddly formed PWM signals during +//! the update (i.e. a PWM pulse that is too short or too long). +//! +//! The PWM generator can either pause or continue running when the processor +//! is stopped via the debugger. If configured to pause, it will continue to +//! count until it reaches zero, at which point it will pause until the +//! processor is restarted. If configured to continue running, it will keep +//! counting as if nothing had happened. +//! +//! The \b ulConfig parameter contains the desired configuration. It is the +//! logical OR of the following: \b PWM_GEN_MODE_DOWN or +//! \b PWM_GEN_MODE_UP_DOWN to specify the counting mode, \b PWM_GEN_MODE_SYNC +//! or \b PWM_GEN_MODE_NO_SYNC to specify the synchronization mode, and +//! \b PWM_GEN_MODE_DBG_RUN or \b PWM_GEN_MODE_DBG_STOP to specify the debug +//! behavior. +//! +//! \note Changes to the counter mode will affect the period of the PWM signals +//! produced. PWMGenPeriodSet() and PWMPulseWidthSet() should be called after +//! any changes to the counter mode of a generator. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_genconfigure) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMGenConfigure(unsigned long ulBase, unsigned long ulGen, + unsigned long ulConfig) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + + // + // Compute the generator's base address. + // + ulGen = PWM_GEN_BADDR(ulBase, ulGen); + + // + // Change the global configuration of the generator. + // + HWREG(ulGen + PWM_O_X_CTL) = ((HWREG(ulGen + PWM_O_X_CTL) & + ~(PWM_X_CTL_MODE | PWM_X_CTL_DEBUG | + PWM_X_CTL_LOADUPD | PWM_X_CTL_CMPAUPD | + PWM_X_CTL_CMPBUPD)) | ulConfig); + + // + // Set the individual PWM generator controls. + // + if(ulConfig & PWM_X_CTL_MODE) + { + // + // In up/down count mode, set the signal high on up count comparison + // and low on down count comparison (i.e. center align the signals). + // + HWREG(ulGen + PWM_O_X_GENA) = ((PWM_GEN_ACT_ONE << + PWM_GEN_ACT_A_UP_SHIFT) | + (PWM_GEN_ACT_ZERO << + PWM_GEN_ACT_A_DN_SHIFT)); + HWREG(ulGen + PWM_O_X_GENB) = ((PWM_GEN_ACT_ONE << + PWM_GEN_ACT_B_UP_SHIFT) | + (PWM_GEN_ACT_ZERO << + PWM_GEN_ACT_B_DN_SHIFT)); + } + else + { + // + // In down count mode, set the signal high on load and low on count + // comparison (i.e. left align the signals). + // + HWREG(ulGen + PWM_O_X_GENA) = ((PWM_GEN_ACT_ONE << + PWM_GEN_ACT_LOAD_SHIFT) | + (PWM_GEN_ACT_ZERO << + PWM_GEN_ACT_A_DN_SHIFT)); + HWREG(ulGen + PWM_O_X_GENB) = ((PWM_GEN_ACT_ONE << + PWM_GEN_ACT_LOAD_SHIFT) | + (PWM_GEN_ACT_ZERO << + PWM_GEN_ACT_B_DN_SHIFT)); + } +} +#endif + +//***************************************************************************** +// +//! Set the period of a PWM generator. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to be modified. Must be one of +//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. +//! \param ulPeriod specifies the period of PWM generator output, measured +//! in clock ticks. +//! +//! This function sets the period of the specified PWM generator block, where +//! the period of the generator block is defined as the number of \b PWM +//! clock ticks between pulses on the generator block \b zero signal. +//! +//! \note Any subsequent calls made to this function before an update occurs +//! will cause the previous values to be overwritten. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_genperiodset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen, + unsigned long ulPeriod) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + + // + // Compute the generator's base address. + // + ulGen = PWM_GEN_BADDR(ulBase, ulGen); + + // + // Set the reload register based on the mode. + // + if(HWREG(ulGen + PWM_O_X_CTL) & PWM_X_CTL_MODE) + { + // + // In up/down count mode, set the reload register to half the requested + // period. + // + ASSERT((ulPeriod / 2) < 65536); + HWREG(ulGen + PWM_O_X_LOAD) = ulPeriod / 2; + } + else + { + // + // In down count mode, set the reload register to the requested period + // minus one. + // + ASSERT((ulPeriod <= 65536) && (ulPeriod != 0)); + HWREG(ulGen + PWM_O_X_LOAD) = ulPeriod - 1; + } +} +#endif + +//***************************************************************************** +// +//! Gets the period of a PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to query. Must be one of +//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. +//! +//! This function gets the period of the specified PWM generator block. The +//! period of the generator block is defined as the number of \b PWM clock +//! ticks between pulses on the generator block \b zero signal. +//! +//! If the update of the counter for the specified PWM generator has yet +//! to be completed, the value returned may not be the active period. The +//! value returned is the programmed period, measured in \b PWM clock ticks. +//! +//! \return Returns the programmed period of the specified generator block +//! in \b PWM clock ticks. +// +//***************************************************************************** +#if defined(GROUP_genperiodget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +PWMGenPeriodGet(unsigned long ulBase, unsigned long ulGen) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + + // + // Compute the generator's base address. + // + ulGen = PWM_GEN_BADDR(ulBase, ulGen); + + // + // Figure out the counter mode. + // + if(HWREG(ulGen + PWM_O_X_CTL) & PWM_X_CTL_MODE) + { + // + // The period is twice the reload register value. + // + return(HWREG(ulGen + PWM_O_X_LOAD) * 2); + } + else + { + // + // The period is the reload register value plus one. + // + return(HWREG(ulGen + PWM_O_X_LOAD) + 1); + } +} +#endif + +//***************************************************************************** +// +//! Enables the timer/counter for a PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to be enabled. Must be one of +//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. +//! +//! This function allows the \b PWM clock to drive the timer/counter for the +//! specified generator block. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_genenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMGenEnable(unsigned long ulBase, unsigned long ulGen) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + + // + // Enable the PWM generator. + // + HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_CTL) |= PWM_X_CTL_ENABLE; +} +#endif + +//***************************************************************************** +// +//! Disables the timer/counter for a PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to be disabled. Must be one of +//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. +//! +//! This function blocks the \b PWM clock from driving the timer/counter for +//! the specified generator block. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_gendisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMGenDisable(unsigned long ulBase, unsigned long ulGen) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + + // + // Disable the PWM generator. + // + HWREG(PWM_GEN_BADDR(ulBase, + ulGen) + PWM_O_X_CTL) &= ~(PWM_X_CTL_ENABLE); +} +#endif + +//***************************************************************************** +// +//! Sets the pulse width for the specified PWM output. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulPWMOut is the PWM output to modify. Must be one of \b PWM_OUT_0, +//! \b PWM_OUT_1, \b PWM_OUT_2, \b PWM_OUT_3, \b PWM_OUT_4, or \b PWM_OUT_5. +//! \param ulWidth specifies the width of the positive portion of the pulse. +//! +//! This function sets the pulse width for the specified PWM output, where the +//! pulse width is defined as the number of \b PWM clock ticks. +//! +//! \note Any subsequent calls made to this function before an update occurs +//! will cause the previous values to be overwritten. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pulsewidthset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut, + unsigned long ulWidth) +{ + unsigned long ulGenBase, ulReg; + + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulPWMOut == PWM_OUT_0) || (ulPWMOut == PWM_OUT_1) || + (ulPWMOut == PWM_OUT_2) || (ulPWMOut == PWM_OUT_3) || + (ulPWMOut == PWM_OUT_4) || (ulPWMOut == PWM_OUT_5)); + + // + // Compute the generator's base address. + // + ulGenBase = PWM_OUT_BADDR(ulBase, ulPWMOut); + + // + // If the counter is in up/down count mode, divide the width by two. + // + if(HWREG(ulGenBase + PWM_O_X_CTL) & PWM_X_CTL_MODE) + { + ulWidth /= 2; + } + + // + // Get the period. + // + ulReg = HWREG(ulGenBase + PWM_O_X_LOAD); + + // + // Make sure the width is not too large. + // + ASSERT(ulWidth < ulReg); + + // + // Compute the compare value. + // + ulReg = ulReg - ulWidth; + + // + // Write to the appropriate registers. + // + if(PWM_IS_OUTPUT_ODD(ulPWMOut)) + { + HWREG(ulGenBase + PWM_O_X_CMPB) = ulReg; + } + else + { + HWREG(ulGenBase + PWM_O_X_CMPA) = ulReg; + } +} +#endif + +//***************************************************************************** +// +//! Gets the pulse width of a PWM output. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulPWMOut is the PWM output to query. Must be one of \b PWM_OUT_0, +//! \b PWM_OUT_1, \b PWM_OUT_2, \b PWM_OUT_3, \b PWM_OUT_4, or \b PWM_OUT_5. +//! +//! This function gets the currently programmed pulse width for the +//! specified PWM output. If the update of the comparator for the specified +//! output has yet to be completed, the value returned may not be the active +//! pulse width. The value returned is the programmed pulse width, measured +//! in \b PWM clock ticks. +//! +//! \return Returns the width of the pulse in \b PWM clock ticks. +// +//***************************************************************************** +#if defined(GROUP_pulsewidthget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +PWMPulseWidthGet(unsigned long ulBase, unsigned long ulPWMOut) +{ + unsigned long ulGenBase, ulReg, ulLoad; + + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulPWMOut == PWM_OUT_0) || (ulPWMOut == PWM_OUT_1) || + (ulPWMOut == PWM_OUT_2) || (ulPWMOut == PWM_OUT_3) || + (ulPWMOut == PWM_OUT_4) || (ulPWMOut == PWM_OUT_5)); + + // + // Compute the generator's base address. + // + ulGenBase = PWM_OUT_BADDR(ulBase, ulPWMOut); + + // + // Then compute the pulse width. If mode is UpDown, set + // width = (load-compare)*2. Otherwise, set width = load - compare + // + ulLoad = HWREG(ulGenBase + PWM_O_X_LOAD); + if(PWM_IS_OUTPUT_ODD(ulPWMOut)) + { + ulReg = HWREG(ulGenBase + PWM_O_X_CMPB); + } + else + { + ulReg = HWREG(ulGenBase + PWM_O_X_CMPA); + } + ulReg = ulLoad - ulReg; + + // + // If in up/down count mode, double the pulse width. + // + if(HWREG(ulGenBase + PWM_O_X_CTL) & PWM_X_CTL_MODE) + { + ulReg = ulReg * 2; + } + + // + // Return the pulse width. + // + return(ulReg); +} +#endif + +//***************************************************************************** +// +//! Enables the PWM dead band output, and sets the dead band delays. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to modify. Must be one of +//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. +//! \param usRise specifies the width of delay from the rising edge. +//! \param usFall specifies the width of delay from the falling edge. +//! +//! This function sets the dead bands for the specified PWM generator, +//! where the dead bands are defined as the number of \b PWM clock ticks +//! from the rising or falling edge of the generator's \b OutA signal. +//! Note that this function causes the coupling of \b OutB to \b OutA. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_deadbandenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen, + unsigned short usRise, unsigned short usFall) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + ASSERT(usRise < 4096); + ASSERT(usFall < 4096); + + // + // Compute the generator's base address. + // + ulGen = PWM_GEN_BADDR(ulBase, ulGen); + + // + // Write the dead band delay values. + // + HWREG(ulGen + PWM_O_X_DBRISE) = usRise; + HWREG(ulGen + PWM_O_X_DBFALL) = usFall; + + // + // Enable the deadband functionality. + // + HWREG(ulGen + PWM_O_X_DBCTL) |= PWM_DBCTL_ENABLE; +} +#endif + +//***************************************************************************** +// +//! Disables the PWM dead band output. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to modify. Must be one of +//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. +//! +//! This function disables the dead band mode for the specified PWM generator. +//! Doing so decouples the \b OutA and \b OutB signals. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_deadbanddisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + + // + // Disable the deadband functionality. + // + HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_DBCTL) &= ~(PWM_DBCTL_ENABLE); +} +#endif + +//***************************************************************************** +// +//! Synchronizes all pending updates. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGenBits are the PWM generator blocks to be updated. Must be the +//! logical OR of any of \b PWM_GEN_0_BIT, \b PWM_GEN_1_BIT, or +//! \b PWM_GEN_2_BIT. +//! +//! For the selected PWM generators, this function causes all queued updates to +//! the period or pulse width to be applied the next time the corresponding +//! counter becomes zero. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_syncupdate) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT(!(ulGenBits & ~(PWM_GEN_0_BIT | PWM_GEN_1_BIT | PWM_GEN_2_BIT))); + + // + // Update the PWM timing registers. + // + HWREG(ulBase + PWM_O_CTL) = ulGenBits; +} +#endif + +//***************************************************************************** +// +//! Synchronizes the counters in one or multiple PWM generator blocks. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGenBits are the PWM generator blocks to be synchronized. Must be +//! the logical OR of any of \b PWM_GEN_0_BIT, \b PWM_GEN_1_BIT, or +//! \b PWM_GEN_2_BIT. +//! +//! For the selected PWM module, this function synchronizes the time base +//! of the generator blocks by causing the specified generator counters to be +//! reset to zero. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_synctimebase) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT(!(ulGenBits & ~(PWM_GEN_0_BIT | PWM_GEN_1_BIT | PWM_GEN_2_BIT))); + + // + // Synchronize the counters in the specified generators by writing to + // the module's synchronization register. + // + HWREG(ulBase + PWM_O_SYNC) = ulGenBits; +} +#endif + +//***************************************************************************** +// +//! Enables or disables PWM outputs. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the +//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT, +//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, or \b PWM_OUT_5_BIT. +//! \param bEnable determines if the signal is enabled or disabled. +//! +//! This function is used to enable or disable the selected PWM outputs. The +//! outputs are selected using the parameter \e ulPWMOutBits. The parameter +//! \e bEnable determines the state of the selected outputs. If \e bEnable is +//! \b true, then the selected PWM outputs are enabled, or placed in the active +//! state. If \e bEnable is \b false, then the selected outputs are disabled, +//! or placed in the inactive state. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_outputstate) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bEnable) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT | + PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT))); + + // + // Read the module's ENABLE output control register, and set or clear + // the requested bits. + // + if(bEnable == true) + { + HWREG(ulBase + PWM_O_ENABLE) |= ulPWMOutBits; + } + else + { + HWREG(ulBase + PWM_O_ENABLE) &= ~(ulPWMOutBits); + } +} +#endif + +//***************************************************************************** +// +//! Selects the inversion mode for PWM outputs. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the +//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT, +//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, or \b PWM_OUT_5_BIT. +//! \param bInvert determines if the signal is inverted or passed through. +//! +//! This function is used to select the inversion mode for the selected PWM +//! outputs. The outputs are selected using the parameter \e ulPWMOutBits. +//! The parameter \e bInvert determines the inversion mode for the selected +//! outputs. If \e bInvert is \b true, this function will cause the specified +//! PWM output signals to be inverted, or made active low. If \e bInvert is +//! \b false, the specified output will be passed through as is, or be made +//! active high. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_outputinvert) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bInvert) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT | + PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT))); + + // + // Read the module's INVERT output control register, and set or clear + // the requested bits. + // + if(bInvert == true) + { + HWREG(ulBase + PWM_O_INVERT) |= ulPWMOutBits; + } + else + { + HWREG(ulBase + PWM_O_INVERT) &= ~(ulPWMOutBits); + } +} +#endif + +//***************************************************************************** +// +//! Specifies the state of PWM outputs in response to a fault condition. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the +//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT, +//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, or \b PWM_OUT_5_BIT. +//! \param bFaultKill determines if the signal is killed or passed through +//! during an active fault condition. +//! +//! This function sets the fault handling characteristics of the selected PWM +//! outputs. The outputs are selected using the parameter \e ulPWMOutBits. +//! The parameter \e bFaultKill determines the fault handling characteristics +//! for the selected outputs. If \e bFaultKill is \b true, then the selected +//! outputs will be made inactive. If \e bFaultKill is \b false, then the +//! selected outputs are unaffected by the detected fault. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_outputfault) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bFaultKill) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT | + PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT))); + + // + // Read the module's FAULT output control register, and set or clear + // the requested bits. + // + if(bFaultKill == true) + { + HWREG(ulBase + PWM_O_FAULT) |= ulPWMOutBits; + } + else + { + HWREG(ulBase + PWM_O_FAULT) &= ~(ulPWMOutBits); + } +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for the specified PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator in question. +//! \param pfnIntHandler is a pointer to the function to be called when the PWM +//! generator interrupt occurs. +//! +//! This function will ensure that the interrupt handler specified by +//! \e pfnIntHandler is called when an interrupt is detected for the specified +//! PWM generator block. This function will also enable the corresponding +//! PWM generator interrupt in the interrupt controller; individual generator +//! interrupts and interrupt sources must be enabled with PWMIntEnable() and +//! PWMGenIntTrigEnable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_genintregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen, + void (*pfnIntHandler)(void)) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + + // + // Get the interrupt number associated with the specified generator. + // + ulInt = INT_PWM0 + (ulGen >> 6) - 1; + + // + // Register the interrupt handler. + // + IntRegister(ulInt, pfnIntHandler); + + // + // Enable the PWMx interrupt. + // + IntEnable(ulInt); +} +#endif + +//***************************************************************************** +// +//! Removes an interrupt handler for the specified PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator in question. +//! +//! This function will unregister the interrupt handler for the specified +//! PWM generator block. This function will also disable the corresponding +//! PWM generator interrupt in the interrupt controller; individual generator +//! interrupts and interrupt sources must be disabled with PWMIntDisable() and +//! PWMGenIntTrigDisable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_genintunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + + // + // Get the interrupt number associated with the specified generator. + // + ulInt = INT_PWM0 + (ulGen >> 6) - 1; + + // + // Disable the PWMx interrupt. + // + IntDisable(ulInt); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulInt); +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for a fault condition detected in a PWM +//! module. +//! +//! \param ulBase is the base address of the PWM module. +//! \param pfnIntHandler is a pointer to the function to be called when the PWM +//! fault interrupt occurs. +//! +//! This function will ensure that the interrupt handler specified by +//! \e pfnIntHandler is called when a fault interrupt is detected for the +//! selected PWM module. This function will also enable the PWM fault +//! interrupt in the NVIC; the PWM fault interrupt must also be enabled at the +//! module level using PWMIntEnable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_faultintregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMFaultIntRegister(unsigned long ulBase, void (*pfnIntHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + + // + // Register the interrupt handler, returning an error if one occurs. + // + IntRegister(INT_PWM_FAULT, pfnIntHandler); + + // + // Enable the PWM fault interrupt. + // + IntEnable(INT_PWM_FAULT); +} +#endif + +//***************************************************************************** +// +//! Removes the PWM fault condition interrupt handler. +//! +//! \param ulBase is the base address of the PWM module. +//! +//! This function will remove the interrupt handler for a PWM fault interrupt +//! from the selected PWM module. This function will also disable the PWM +//! fault interrupt in the NVIC; the PWM fault interrupt must also be disabled +//! at the module level using PWMIntDisable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_faultintunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMFaultIntUnregister(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + + // + // Disable the PWM fault interrupt. + // + IntDisable(INT_PWM_FAULT); + + // + // Unregister the interrupt handler, returning an error if one occurs. + // + IntUnregister(INT_PWM_FAULT); +} +#endif + +//***************************************************************************** +// +//! Enables interrupts and triggers for the specified PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to have interrupts and triggers enabled. +//! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. +//! \param ulIntTrig specifies the interrupts and triggers to be enabled. +//! +//! Unmasks the specified interrupt(s) and trigger(s) by setting the +//! specified bits of the interrupt/trigger enable register for the specified +//! PWM generator. The defined values for the bits are as follows: +//! +//! - PWM_INT_CNT_ZERO +//! - PWM_INT_CNT_LOAD +//! - PWM_INT_CMP_AU +//! - PWM_INT_CMP_AD +//! - PWM_INT_CMP_BU +//! - PWM_INT_CMP_BD +//! - PWM_TR_CNT_ZERO +//! - PWM_TR_CNT_LOAD +//! - PWM_TR_CMP_AU +//! - PWM_TR_CMP_AD +//! - PWM_TR_CMP_BU +//! - PWM_TR_CMP_BD +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_geninttrigenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen, + unsigned long ulIntTrig) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + + // + // Enable the specified interrupts/triggers. + // + HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_INTEN) |= ulIntTrig; +} +#endif + +//***************************************************************************** +// +//! Disables interrupts for the specified PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to have interrupts and triggers disabled. +//! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. +//! \param ulIntTrig specifies the interrupts and triggers to be disabled. +//! +//! Masks the specified interrupt(s) and trigger(s) by clearing the +//! specified bits of the interrupt/trigger enable register for the specified +//! PWM generator. The defined values for the bits are as follows: +//! +//! - PWM_INT_CNT_ZERO +//! - PWM_INT_CNT_LOAD +//! - PWM_INT_CMP_AU +//! - PWM_INT_CMP_AD +//! - PWM_INT_CMP_BU +//! - PWM_INT_CMP_BD +//! - PWM_TR_CNT_ZERO +//! - PWM_TR_CNT_LOAD +//! - PWM_TR_CMP_AU +//! - PWM_TR_CMP_AD +//! - PWM_TR_CMP_BU +//! - PWM_TR_CMP_BD +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_geninttrigdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen, + unsigned long ulIntTrig) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + + // + // Disable the specified interrupts/triggers. + // + HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_INTEN) &= ~(ulIntTrig); +} +#endif + +//***************************************************************************** +// +//! Gets interrupt status for the specified PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to query. Must be one of \b PWM_GEN_0, +//! \b PWM_GEN_1, or \b PWM_GEN_2. +//! \param bMasked specifies whether masked or raw interrupt status is +//! returned. +//! +//! If \e bMasked is set as \b true, then the masked interrupt status is +//! returned; otherwise, the raw interrupt status will be returned. +//! +//! \return Returns the contents of the interrupt status register, or the +//! contents of the raw interrupt status register, for the specified +//! PWM generator. +// +//***************************************************************************** +#if defined(GROUP_genintstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + + // + // Compute the generator's base address. + // + ulGen = PWM_GEN_BADDR(ulBase, ulGen); + + // + // Read and return the specified generator's raw or enabled interrupt + // status. + // + if(bMasked == true) + { + return(HWREG(ulGen + PWM_O_X_ISC)); + } + else + { + return(HWREG(ulGen + PWM_O_X_RIS)); + } +} +#endif + +//***************************************************************************** +// +//! Clears the specified interrupt(s) for the specified PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to query. Must be one of \b PWM_GEN_0, +//! \b PWM_GEN_1, or \b PWM_GEN_2. +//! \param ulInts specifies the interrupts to be cleared. +//! +//! Clears the specified interrupt(s) by writing a 1 to the specified bits +//! of the interrupt status register for the specified PWM generator. The +//! defined values for the bits are as follows: +//! +//! - PWM_INT_CNT_ZERO +//! - PWM_INT_CNT_LOAD +//! - PWM_INT_CMP_AU +//! - PWM_INT_CMP_AD +//! - PWM_INT_CMP_BU +//! - PWM_INT_CMP_BD +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_genintclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMGenIntClear(unsigned long ulBase, unsigned long ulGen, unsigned long ulInts) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + + // + // Clear the requested interrupts by writing ones to the specified bit + // of the module's interrupt enable register. + // + HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_ISC) = ulInts; +} +#endif + +//***************************************************************************** +// +//! Enables generator and fault interrupts for a PWM module. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGenFault contains the interrupts to be enabled. Must be a logical +//! OR of any of \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2, or +//! \b PWM_INT_FAULT. +//! +//! Unmasks the specified interrupt(s) by setting the specified bits of +//! the interrupt enable register for the selected PWM module. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + + // + // Read the module's interrupt enable register, and enable interrupts + // for the specified PWM generators. + // + HWREG(ulBase + PWM_O_INTEN) |= ulGenFault; +} +#endif + +//***************************************************************************** +// +//! Disables generator and fault interrupts for a PWM module. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGenFault contains the interrupts to be disabled. Must be a +//! logical OR of any of \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2, +//! or \b PWM_INT_FAULT. +//! +//! Masks the specified interrupt(s) by clearing the specified bits of +//! the interrupt enable register for the selected PWM module. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + + // + // Read the module's interrupt enable register, and disable interrupts + // for the specified PWM generators. + // + HWREG(ulBase + PWM_O_INTEN) &= ~(ulGenFault); +} +#endif + +//***************************************************************************** +// +//! Clears the fault interrupt for a PWM module. +//! +//! \param ulBase is the base address of the PWM module. +//! +//! Clears the fault interrupt by writing to the appropriate bit of the +//! interrupt status register for the selected PWM module. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_faultintclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMFaultIntClear(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + + // + // Write the only writeable bit in the module's interrupt register. + // + HWREG(ulBase + PWM_O_ISC) = PWM_INT_INTFAULT; +} +#endif + +//***************************************************************************** +// +//! Gets the interrupt status for a PWM module. +//! +//! \param ulBase is the base address of the PWM module. +//! \param bMasked specifies whether masked or raw interrupt status is +//! returned. +//! +//! If \e bMasked is set as \b true, then the masked interrupt status is +//! returned; otherwise, the raw interrupt status will be returned. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2, and \b PWM_INT_FAULT. +//! +//***************************************************************************** +#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +PWMIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + + // + // Read and return either the module's raw or enabled interrupt status. + // + if(bMasked == true) + { + return(HWREG(ulBase + PWM_O_ISC)); + } + else + { + return(HWREG(ulBase + PWM_O_RIS)); + } +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/pwm.h b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/pwm.h new file mode 100644 index 000000000..db835bacd --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/pwm.h @@ -0,0 +1,161 @@ +//***************************************************************************** +// +// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __PWM_H__ +#define __PWM_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following defines are passed to PWMGenConfigure() as the ulConfig +// parameter and specify the configuration of the PWM generator. +// +//***************************************************************************** +#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode +#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode +#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates +#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates +#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode +#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode + +//***************************************************************************** +// +// Defines for enabling, disabling, and clearing PWM generator interrupts and +// triggers. +// +//***************************************************************************** +#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0 +#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD +#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U +#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D +#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U +#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D +#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0 +#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD +#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U +#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D +#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U +#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D + +//***************************************************************************** +// +// Defines for enabling, disabling, and clearing PWM interrupts. +// +//***************************************************************************** +#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt +#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt +#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt +#define PWM_INT_FAULT 0x00010000 // Fault interrupt + +//***************************************************************************** +// +// Defines to identify the generators within a module. +// +//***************************************************************************** +#define PWM_GEN_0 0x00000040 // Offset address of Gen0 +#define PWM_GEN_1 0x00000080 // Offset address of Gen1 +#define PWM_GEN_2 0x000000C0 // Offset address of Gen2 + +#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0 +#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1 +#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2 + +//***************************************************************************** +// +// Defines to identify the outputs within a module. +// +//***************************************************************************** +#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0 +#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1 +#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2 +#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3 +#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4 +#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5 + +#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0 +#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1 +#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2 +#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3 +#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4 +#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5 + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen, + unsigned long ulConfig); +extern void PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen, + unsigned long ulPeriod); +extern unsigned long PWMGenPeriodGet(unsigned long ulBase, + unsigned long ulGen); +extern void PWMGenEnable(unsigned long ulBase, unsigned long ulGen); +extern void PWMGenDisable(unsigned long ulBase, unsigned long ulGen); +extern void PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut, + unsigned long ulWidth); +extern unsigned long PWMPulseWidthGet(unsigned long ulBase, + unsigned long ulPWMOut); +extern void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen, + unsigned short usRise, unsigned short usFall); +extern void PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen); +extern void PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits); +extern void PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits); +extern void PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bEnable); +extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bInvert); +extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bFaultKill); +extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen, + void (*pfnIntHandler)(void)); +extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen); +extern void PWMFaultIntRegister(unsigned long ulBase, + void (*pfnIntHandler)(void)); +extern void PWMFaultIntUnregister(unsigned long ulBase); +extern void PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen, + unsigned long ulIntTrig); +extern void PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen, + unsigned long ulIntTrig); +extern unsigned long PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen, + tBoolean bMasked); +extern void PWMGenIntClear(unsigned long ulBase, unsigned long ulGen, + unsigned long ulInts); +extern void PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault); +extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault); +extern void PWMFaultIntClear(unsigned long ulBase); +extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked); + +#ifdef __cplusplus +} +#endif + +#endif // __PWM_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/qei.c b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/qei.c new file mode 100644 index 000000000..eb982de39 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/qei.c @@ -0,0 +1,630 @@ +//***************************************************************************** +// +// qei.c - Driver for the Quadrature Encoder with Index. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup qei_api +//! @{ +// +//***************************************************************************** + +#include "../hw_ints.h" +#include "../hw_memmap.h" +#include "../hw_qei.h" +#include "../hw_types.h" +#include "debug.h" +#include "interrupt.h" +#include "qei.h" + +//***************************************************************************** +// +//! Enables the quadrature encoder. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This will enable operation of the quadrature encoder module. It must be +//! configured before it is enabled. +//! +//! \sa QEIConfigure() +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +QEIEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Enable the QEI module. + // + HWREG(ulBase + QEI_O_CTL) |= QEI_CTL_ENABLE; +} +#endif + +//***************************************************************************** +// +//! Disables the quadrature encoder. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This will disable operation of the quadrature encoder module. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +QEIDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Disable the QEI module. + // + HWREG(ulBase + QEI_O_CTL) &= ~(QEI_CTL_ENABLE); +} +#endif + +//***************************************************************************** +// +//! Configures the quadrature encoder. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! \param ulConfig is the configuration for the quadrature encoder. See below +//! for a description of this parameter. +//! \param ulMaxPosition specifies the maximum position value. +//! +//! This will configure the operation of the quadrature encoder. The +//! \e ulConfig parameter provides the configuration of the encoder and is the +//! logical OR of several values: +//! +//! - \b QEI_CONFIG_CAPTURE_A or \b QEI_CONFIG_CAPTURE_A_B to specify if edges +//! on channel A or on both channels A and B should be counted by the +//! position integrator and velocity accumulator. +//! - \b QEI_CONFIG_NO_RESET or \b QEI_CONFIG_RESET_IDX to specify if the +//! position integrator should be reset when the index pulse is detected. +//! - \b QEI_CONFIG_QUADRATURE or \b QEI_CONFIG_CLOCK_DIR to specify if +//! quadrature signals are being provided on ChA and ChB, or if a direction +//! signal and a clock are being provided instead. +//! - \b QEI_CONFIG_NO_SWAP or \b QEI_CONFIG_SWAP to specify if the signals +//! provided on ChA and ChB should be swapped before being processed. +//! +//! \e ulMaxPosition is the maximum value of the position integrator, and is +//! the value used to reset the position capture when in index reset mode and +//! moving in the reverse (negative) direction. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_configure) || defined(BUILD_ALL) || defined(DOXYGEN) +void +QEIConfigure(unsigned long ulBase, unsigned long ulConfig, + unsigned long ulMaxPosition) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Write the new configuration to the hardware. + // + HWREG(ulBase + QEI_O_CTL) = ((HWREG(ulBase + QEI_O_CTL) & + ~(QEI_CTL_CAPMODE | QEI_CTL_RESMODE | + QEI_CTL_SIGMODE | QEI_CTL_SWAP)) | + ulConfig); + + // + // Set the maximum position. + // + HWREG(ulBase + QEI_O_MAXPOS) = ulMaxPosition; +} +#endif + +//***************************************************************************** +// +//! Gets the current encoder position. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This returns the current position of the encoder. Depending upon the +//! configuration of the encoder, and the incident of an index pulse, this +//! value may or may not contain the expected data (i.e. if in reset on index +//! mode, if an index pulse has not been encountered, the position counter will +//! not be aligned with the index pulse yet). +//! +//! \return The current position of the encoder. +// +//***************************************************************************** +#if defined(GROUP_positionget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +QEIPositionGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Return the current position counter. + // + return(HWREG(ulBase + QEI_O_POS)); +} +#endif + +//***************************************************************************** +// +//! Sets the current encoder position. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! \param ulPosition is the new position for the encoder. +//! +//! This sets the current position of the encoder; the encoder position will +//! then be measured relative to this value. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_positionset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +QEIPositionSet(unsigned long ulBase, unsigned long ulPosition) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Set the position counter. + // + HWREG(ulBase + QEI_O_POS) = ulPosition; +} +#endif + +//***************************************************************************** +// +//! Gets the current direction of rotation. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This returns the current direction of rotation. In this case, current +//! means the most recently detected direction of the encoder; it may not be +//! presently moving but this is the direction it last moved before it stopped. +//! +//! \return 1 if moving in the forward direction or -1 if moving in the reverse +//! direction. +// +//***************************************************************************** +#if defined(GROUP_directionget) || defined(BUILD_ALL) || defined(DOXYGEN) +long +QEIDirectionGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Return the direction of rotation. + // + return((HWREG(ulBase + QEI_O_STAT) & QEI_STAT_DIRECTION) ? -1 : 1); +} +#endif + +//***************************************************************************** +// +//! Gets the encoder error indicator. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This returns the error indicator for the quadrature encoder. It is an +//! error for both of the signals of the quadrature input to change at the same +//! time. +//! +//! \return true if an error has occurred and false otherwise. +// +//***************************************************************************** +#if defined(GROUP_errorget) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +QEIErrorGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Return the error indicator. + // + return((HWREG(ulBase + QEI_O_STAT) & QEI_STAT_ERROR) ? true : false); +} +#endif + +//***************************************************************************** +// +//! Enables the velocity capture. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This will enable operation of the velocity capture in the quadrature +//! encoder module. It must be configured before it is enabled. Velocity +//! capture will not occur if the quadrature encoder is not enabled. +//! +//! \sa QEIVelocityConfigure() and QEIEnable() +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_velocityenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +QEIVelocityEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Enable the velocity capture. + // + HWREG(ulBase + QEI_O_CTL) |= QEI_CTL_VELEN; +} +#endif + +//***************************************************************************** +// +//! Disables the velocity capture. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This will disable operation of the velocity capture in the quadrature +//! encoder module. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_velocitydisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +QEIVelocityDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Disable the velocity capture. + // + HWREG(ulBase + QEI_O_CTL) &= ~(QEI_CTL_VELEN); +} +#endif + +//***************************************************************************** +// +//! Configures the velocity capture. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! \param ulPreDiv specifies the predivider applied to the input quadrature +//! signal before it is counted; can be one of QEI_VELDIV_1, QEI_VELDIV_2, +//! QEI_VELDIV_4, QEI_VELDIV_8, QEI_VELDIV_16, QEI_VELDIV_32, QEI_VELDIV_64, or +//! QEI_VELDIV_128. +//! \param ulPeriod specifies the number of clock ticks over which to measure +//! the velocity; must be non-zero. +//! +//! This will configure the operation of the velocity capture portion of the +//! quadrature encoder. The position increment signal is predivided as +//! specified by \e ulPreDiv before being accumulated by the velocity capture. +//! The divided signal is accumulated over \e ulPeriod system clock before +//! being saved and resetting the accumulator. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_velocityconfigure) || defined(BUILD_ALL) || defined(DOXYGEN) +void +QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv, + unsigned long ulPeriod) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + ASSERT(!(ulPreDiv & ~(QEI_CTL_VELDIV_M))); + ASSERT(ulPeriod != 0); + + // + // Set the velocity predivider. + // + HWREG(ulBase + QEI_O_CTL) = ((HWREG(ulBase + QEI_O_CTL) & + ~(QEI_CTL_VELDIV_M)) | ulPreDiv); + + // + // Set the timer period. + // + HWREG(ulBase + QEI_O_LOAD) = ulPeriod - 1; +} +#endif + +//***************************************************************************** +// +//! Gets the current encoder speed. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This returns the current speed of the encoder. The value returned is the +//! number of pulses detected in the specified time period; this number can be +//! multiplied by the number of time periods per second and divided by the +//! number of pulses per revolution to obtain the number of revolutions per +//! second. +//! +//! \return The number of pulses captured in the given time period. +// +//***************************************************************************** +#if defined(GROUP_velocityget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +QEIVelocityGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Return the speed capture value. + // + return(HWREG(ulBase + QEI_O_SPEED)); +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for the quadrature encoder interrupt. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! \param pfnHandler is a pointer to the function to be called when the +//! quadrature encoder interrupt occurs. +//! +//! This sets the handler to be called when a quadrature encoder interrupt +//! occurs. This will enable the global interrupt in the interrupt controller; +//! specific quadrature encoder interrupts must be enabled via QEIIntEnable(). +//! It is the interrupt handler's responsibility to clear the interrupt source +//! via QEIIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(INT_QEI, pfnHandler); + + // + // Enable the quadrature encoder interrupt. + // + IntEnable(INT_QEI); +} +#endif + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the quadrature encoder interrupt. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This function will clear the handler to be called when a quadrature encoder +//! interrupt occurs. This will also mask off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +QEIIntUnregister(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Disable the interrupt. + // + IntDisable(INT_QEI); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_QEI); +} +#endif + +//***************************************************************************** +// +//! Enables individual quadrature encoder interrupt sources. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. +//! Can be any of the QEI_INTERROR, QEI_INTDIR, QEI_INTTIMER, or QEI_INTINDEX +//! values. +//! +//! Enables the indicated quadrature encoder interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Enable the specified interrupts. + // + HWREG(ulBase + QEI_O_INTEN) |= ulIntFlags; +} +#endif + +//***************************************************************************** +// +//! Disables individual quadrature encoder interrupt sources. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled. +//! Can be any of the QEI_INTERROR, QEI_INTDIR, QEI_INTTIMER, or QEI_INTINDEX +//! values. +//! +//! Disables the indicated quadrature encoder interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Disable the specified interrupts. + // + HWREG(ulBase + QEI_O_INTEN) &= ~(ulIntFlags); +} +#endif + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! \param bMasked is false if the raw interrupt status is required and true if +//! the masked interrupt status is required. +//! +//! This returns the interrupt status for the quadrature encoder module. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! QEI_INTERROR, QEI_INTDIR, QEI_INTTIMER, and QEI_INTINDEX. +// +//***************************************************************************** +#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +QEIIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ulBase + QEI_O_ISC)); + } + else + { + return(HWREG(ulBase + QEI_O_RIS)); + } +} +#endif + +//***************************************************************************** +// +//! Clears quadrature encoder interrupt sources. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. +//! Can be any of the QEI_INTERROR, QEI_INTDIR, QEI_INTTIMER, or QEI_INTINDEX +//! values. +//! +//! The specified quadrature encoder interrupt sources are cleared, so that +//! they no longer assert. This must be done in the interrupt handler to keep +//! it from being called again immediately upon exit. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Clear the requested interrupt sources. + // + HWREG(ulBase + QEI_O_ISC) = ulIntFlags; +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/qei.h b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/qei.h new file mode 100644 index 000000000..3eaafaeef --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/qei.h @@ -0,0 +1,104 @@ +//***************************************************************************** +// +// qei.h - Prototypes for the Quadrature Encoder Driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __QEI_H__ +#define __QEI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to QEIConfigure as the ulConfig paramater. +// +//***************************************************************************** +#define QEI_CONFIG_CAPTURE_A 0x00000000 // Count on ChA edges only +#define QEI_CONFIG_CAPTURE_A_B 0x00000008 // Count on ChA and ChB edges +#define QEI_CONFIG_NO_RESET 0x00000000 // Do not reset on index pulse +#define QEI_CONFIG_RESET_IDX 0x00000010 // Reset position on index pulse +#define QEI_CONFIG_QUADRATURE 0x00000000 // ChA and ChB are quadrature +#define QEI_CONFIG_CLOCK_DIR 0x00000004 // ChA and ChB are clock and dir +#define QEI_CONFIG_NO_SWAP 0x00000000 // Do not swap ChA and ChB +#define QEI_CONFIG_SWAP 0x00000002 // Swap ChA and ChB + +//***************************************************************************** +// +// Values that can be passed to QEIVelocityConfigure as the ulPreDiv parameter. +// +//***************************************************************************** +#define QEI_VELDIV_1 0x00000000 // Predivide by 1 +#define QEI_VELDIV_2 0x00000040 // Predivide by 2 +#define QEI_VELDIV_4 0x00000080 // Predivide by 4 +#define QEI_VELDIV_8 0x000000C0 // Predivide by 8 +#define QEI_VELDIV_16 0x00000100 // Predivide by 16 +#define QEI_VELDIV_32 0x00000140 // Predivide by 32 +#define QEI_VELDIV_64 0x00000180 // Predivide by 64 +#define QEI_VELDIV_128 0x000001C0 // Predivide by 128 + +//***************************************************************************** +// +// Values that can be passed to QEIEnableInts, QEIDisableInts, and QEIClearInts +// as the ulIntFlags parameter, and returned by QEIGetIntStatus. +// +//***************************************************************************** +#define QEI_INTERROR 0x00000008 // Phase error detected +#define QEI_INTDIR 0x00000004 // Direction change +#define QEI_INTTIMER 0x00000002 // Velocity timer expired +#define QEI_INTINDEX 0x00000001 // Index pulse detected + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void QEIEnable(unsigned long ulBase); +extern void QEIDisable(unsigned long ulBase); +extern void QEIConfigure(unsigned long ulBase, unsigned long ulConfig, + unsigned long ulMaxPosition); +extern unsigned long QEIPositionGet(unsigned long ulBase); +extern void QEIPositionSet(unsigned long ulBase, unsigned long ulPosition); +extern long QEIDirectionGet(unsigned long ulBase); +extern tBoolean QEIErrorGet(unsigned long ulBase); +extern void QEIVelocityEnable(unsigned long ulBase); +extern void QEIVelocityDisable(unsigned long ulBase); +extern void QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv, + unsigned long ulPeriod); +extern unsigned long QEIVelocityGet(unsigned long ulBase); +extern void QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); +extern void QEIIntUnregister(unsigned long ulBase); +extern void QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long QEIIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags); + +#ifdef __cplusplus +} +#endif + +#endif // __QEI_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/ssi.c b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/ssi.c new file mode 100644 index 000000000..095aaab33 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/ssi.c @@ -0,0 +1,609 @@ +//***************************************************************************** +// +// ssi.c - Driver for Synchronous Serial Interface. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup ssi_api +//! @{ +// +//***************************************************************************** + +#include "../hw_ints.h" +#include "../hw_memmap.h" +#include "../hw_ssi.h" +#include "../hw_types.h" +#include "debug.h" +#include "interrupt.h" +#include "ssi.h" +#include "sysctl.h" + +//***************************************************************************** +// +//! Configures the synchronous serial interface. +//! +//! \param ulBase specifies the SSI module base address. +//! \param ulProtocol specifies the data transfer protocol. +//! \param ulMode specifies the mode of operation. +//! \param ulBitRate specifies the clock rate. +//! \param ulDataWidth specifies number of bits transfered per frame. +//! +//! This function configures the synchronous serial interface. It sets +//! the SSI protocol, mode of operation, bit rate, and data width. +//! +//! The parameter \e ulProtocol defines the data frame format. The parameter +//! \e ulProtocol can be one of the following values: SSI_FRF_MOTO_MODE_0, +//! SSI_FRF_MOTO_MODE_1, SSI_FRF_MOTO_MODE_2, SSI_FRF_MOTO_MODE_3, +//! SSI_FRF_TI, or SSI_FRF_NMW. The Motorola frame formats imply the +//! following polarity and phase configurations: +//! 

+//! Polarity Phase       Mode
+//!   0       0   SSI_FRF_MOTO_MODE_0
+//!   0       1   SSI_FRF_MOTO_MODE_1
+//!   1       0   SSI_FRF_MOTO_MODE_2
+//!   1       1   SSI_FRF_MOTO_MODE_3
+//!
+//! +//! The parameter \e ulMode defines the operating mode of the SSI module. The +//! SSI module can operate as a master or slave; if a slave, the SSI can be +//! configured to disable output on its serial output line. The parameter +//! \e ulMode can be one of the following values: SSI_MODE_MASTER, +//! SSI_MODE_SLAVE, or SSI_MODE_SLAVE_OD. +//! +//! The parameter \e ulBitRate defines the bit rate for the SSI. This bit rate +//! must satisfy the following clock ratio criteria: +//! - FSSI >= 2 * bit rate (master mode) +//! - FSSI >= 12 * bit rate (slave modes) +//! +//! where FSSI is the frequency of the clock supplied to the SSI module. +//! +//! The parameter \e ulDataWidth defines the width of the data transfers. +//! The parameter \e ulDataWidth can be a value between 4 and 16, inclusive. +//! +//! The SSI clocking is dependent upon the system clock rate returned by +//! SysCtlClockGet(); if it does not return the correct system clock rate then +//! the SSI clock rate will be incorrect. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_config) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SSIConfig(unsigned long ulBase, unsigned long ulProtocol, unsigned long ulMode, + unsigned long ulBitRate, unsigned long ulDataWidth) +{ + unsigned long ulMaxBitRate; + unsigned long ulRegVal; + unsigned long ulPreDiv; + unsigned long ulSCR; + unsigned long ulSPH_SPO; + unsigned long ulClock; + + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + ASSERT((ulProtocol == SSI_FRF_MOTO_MODE_0) || + (ulProtocol == SSI_FRF_MOTO_MODE_1) || + (ulProtocol == SSI_FRF_MOTO_MODE_2) || + (ulProtocol == SSI_FRF_MOTO_MODE_3) || + (ulProtocol == SSI_FRF_TI) || + (ulProtocol == SSI_FRF_NMW)); + ASSERT((ulMode == SSI_MODE_MASTER) || + (ulMode == SSI_MODE_SLAVE) || + (ulMode == SSI_MODE_SLAVE_OD)); + ASSERT((ulDataWidth >= 4) && (ulDataWidth <= 16)); + + // + // Get the processor clock rate. + // + ulClock = SysCtlClockGet(); + + // + // Validate the clock speed. + // + ASSERT(((ulMode == SSI_MODE_MASTER) && (ulBitRate <= (ulClock / 2))) || + ((ulMode != SSI_MODE_MASTER) && (ulBitRate <= (ulClock / 12)))); + ASSERT((ulClock / ulBitRate) <= (254 * 256)); + + // + // Set the mode. + // + ulRegVal = (ulMode == SSI_MODE_SLAVE_OD) ? SSI_CR1_SOD : 0; + ulRegVal |= (ulMode == SSI_MODE_MASTER) ? 0 : SSI_CR1_MS; + HWREG(ulBase + SSI_O_CR1) = ulRegVal; + + // + // Set the clock predivider. + // + ulMaxBitRate = ulClock / ulBitRate; + ulPreDiv = 0; + do + { + ulPreDiv += 2; + ulSCR = (ulMaxBitRate / ulPreDiv) - 1; + } + while(ulSCR > 255); + HWREG(ulBase + SSI_O_CPSR) = ulPreDiv; + + // + // Set protocol and clock rate. + // + ulSPH_SPO = ulProtocol << 6; + ulProtocol &= SSI_CR0_FRF_MASK; + ulRegVal = (ulSCR << 8) | ulSPH_SPO | ulProtocol | (ulDataWidth - 1); + HWREG(ulBase + SSI_O_CR0) = ulRegVal; +} +#endif + +//***************************************************************************** +// +//! Enables the synchronous serial interface. +//! +//! \param ulBase specifies the SSI module base address. +//! +//! This will enable operation of the synchronous serial interface. It must be +//! configured before it is enabled. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SSIEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + + // + // Read-modify-write the enable bit. + // + HWREG(ulBase + SSI_O_CR1) |= SSI_CR1_SSE; +} +#endif + +//***************************************************************************** +// +//! Disables the synchronous serial interface. +//! +//! \param ulBase specifies the SSI module base address. +//! +//! This will disable operation of the synchronous serial interface. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SSIDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + + // + // Read-modify-write the enable bit. + // + HWREG(ulBase + SSI_O_CR1) &= ~(SSI_CR1_SSE); +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for the synchronous serial interface. +//! +//! \param ulBase specifies the SSI module base address. +//! \param pfnHandler is a pointer to the function to be called when the +//! synchronous serial interface interrupt occurs. +//! +//! This sets the handler to be called when an SSI interrupt +//! occurs. This will enable the global interrupt in the interrupt controller; +//! specific SSI interrupts must be enabled via SSIIntEnable(). If necessary, +//! it is the interrupt handler's responsibility to clear the interrupt source +//! via SSIIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SSIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(INT_SSI, pfnHandler); + + // + // Enable the synchronous serial interface interrupt. + // + IntEnable(INT_SSI); +} +#endif + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the synchronous serial interface. +//! +//! \param ulBase specifies the SSI module base address. +//! +//! This function will clear the handler to be called when a SSI +//! interrupt occurs. This will also mask off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SSIIntUnregister(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + + // + // Disable the interrupt. + // + IntDisable(INT_SSI); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_SSI); +} +#endif + +//***************************************************************************** +// +//! Enables individual SSI interrupt sources. +//! +//! \param ulBase specifies the SSI module base address. +//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. +//! +//! Enables the indicated SSI interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources +//! have no effect on the processor. The parameter \e ulIntFlags Can be +//! any of the SSI_TXFF, SSI_RXFF, SSI_RXTO, or SSI_RXOR values. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + + // + // Enable the specified interrupts. + // + HWREG(ulBase + SSI_O_IM) |= ulIntFlags; +} +#endif + +//***************************************************************************** +// +//! Disables individual SSI interrupt sources. +//! +//! \param ulBase specifies the SSI module base address. +//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled. +//! +//! Disables the indicated SSI interrupt sources. The parameter +//! \e ulIntFlags Can be any of the SSI_TXFF, SSI_RXFF, SSI_RXTO, +//! or SSI_RXOR values. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + + // + // Disable the specified interrupts. + // + HWREG(ulBase + SSI_O_IM) &= ~(ulIntFlags); +} +#endif + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ulBase specifies the SSI module base address. +//! \param bMasked is false if the raw interrupt status is required and +//! true if the masked interrupt status is required. +//! +//! This returns the interrupt status for the SSI module. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! SSI_TXFF, SSI_RXFF, SSI_RXTO, and SSI_RXOR. +// +//***************************************************************************** +#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +SSIIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ulBase + SSI_O_MIS)); + } + else + { + return(HWREG(ulBase + SSI_O_RIS)); + } +} +#endif + +//***************************************************************************** +// +//! Clears SSI interrupt sources. +//! +//! \param ulBase specifies the SSI module base address. +//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! The specified SSI interrupt sources are cleared, so that +//! they no longer assert. This must be done in the interrupt handler to +//! keep it from being called again immediately upon exit. +//! The parameter \e ulIntFlags can consist of either or both the SSI_RXTO +//! and SSI_RXOR values. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + + // + // Clear the requested interrupt sources. + // + HWREG(ulBase + SSI_O_ICR) = ulIntFlags; +} +#endif + +//***************************************************************************** +// +//! Puts a data element into the SSI transmit FIFO. +//! +//! \param ulBase specifies the SSI module base address. +//! \param ulData data to be transmitted over the SSI interface. +//! +//! This function will place the supplied data into the transmit FIFO of +//! the specified SSI module. +//! +//! \note The upper 32 - N bits of the \e ulData will be discarded by the +//! hardware, where N is the data width as configured by SSIConfig(). For +//! example, if the interface is configured for 8 bit data width, the upper 24 +//! bits of \e ulData will be discarded. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_dataput) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SSIDataPut(unsigned long ulBase, unsigned long ulData) +{ + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + ASSERT((ulData & (0xfffffffe << (HWREG(ulBase + SSI_O_CR0) & + SSI_CR0_DSS))) == 0); + + // + // Wait until there is space. + // + while(!(HWREG(ulBase + SSI_O_SR) & SSI_SR_TNF)) + { + } + + // + // Write the data to the SSI. + // + HWREG(ulBase + SSI_O_DR) = ulData; +} +#endif + +//***************************************************************************** +// +//! Puts a data element into the SSI transmit FIFO. +//! +//! \param ulBase specifies the SSI module base address. +//! \param ulData data to be transmitted over the SSI interface. +//! +//! This function will place the supplied data into the transmit FIFO of +//! the specified SSI module. If there is no space in the FIFO, then this +//! function will return a zero. +//! +//! \note The upper 32 - N bits of the \e ulData will be discarded by the +//! hardware, where N is the data width as configured by SSIConfig(). For +//! example, if the interface is configured for 8 bit data width, the upper 24 +//! bits of \e ulData will be discarded. +//! +//! \return Returns the number of elements written to the SSI transmit FIFO. +// +//***************************************************************************** +#if defined(GROUP_datanonblockingput) || defined(BUILD_ALL) || defined(DOXYGEN) +long +SSIDataNonBlockingPut(unsigned long ulBase, unsigned long ulData) +{ + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + ASSERT((ulData & (0xfffffffe << (HWREG(ulBase + SSI_O_CR0) & + SSI_CR0_DSS))) == 0); + + // + // Check for space to write. + // + if(HWREG(ulBase + SSI_O_SR) & SSI_SR_TNF) + { + HWREG(ulBase + SSI_O_DR) = ulData; + return(1); + } + else + { + return(0); + } +} +#endif + +//***************************************************************************** +// +//! Gets a data element from the SSI receive FIFO. +//! +//! \param ulBase specifies the SSI module base address. +//! \param pulData pointer to a storage location for data that was received +//! over the SSI interface. +//! +//! This function will get received data from the receive FIFO of the specified +//! SSI module, and place that data into the location specified by the +//! \e pulData parameter. +//! +//! \note Only the lower N bits of the value written to \e pulData will contain +//! valid data, where N is the data width as configured by SSIConfig(). For +//! example, if the interface is configured for 8 bit data width, only the +//! lower 8 bits of the value written to \e pulData will contain valid data. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_dataget) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SSIDataGet(unsigned long ulBase, unsigned long *pulData) +{ + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + + // + // Wait until there is data to be read. + // + while(!(HWREG(ulBase + SSI_O_SR) & SSI_SR_RNE)) + { + } + + // + // Read data from SSI. + // + *pulData = HWREG(ulBase + SSI_O_DR); +} +#endif + +//***************************************************************************** +// +//! Gets a data element from the SSI receive FIFO. +//! +//! \param ulBase specifies the SSI module base address. +//! \param pulData pointer to a storage location for data that was received +//! over the SSI interface. +//! +//! This function will get received data from the receive FIFO of +//! the specified SSI module, and place that data into the location specified +//! by the \e ulData parameter. If there is no data in the FIFO, then this +//! function will return a zero. +//! +//! \note Only the lower N bits of the value written to \e pulData will contain +//! valid data, where N is the data width as configured by SSIConfig(). For +//! example, if the interface is configured for 8 bit data width, only the +//! lower 8 bits of the value written to \e pulData will contain valid data. +//! +//! \return Returns the number of elements read from the SSI receive FIFO. +// +//***************************************************************************** +#if defined(GROUP_datanonblockingget) || defined(BUILD_ALL) || defined(DOXYGEN) +long +SSIDataNonBlockingGet(unsigned long ulBase, unsigned long *pulData) +{ + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + + // + // Check for data to read. + // + if(HWREG(ulBase + SSI_O_SR) & SSI_SR_RNE) + { + *pulData = HWREG(ulBase + SSI_O_DR); + return(1); + } + else + { + return(0); + } +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/ssi.h b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/ssi.h new file mode 100644 index 000000000..045d8cb02 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/ssi.h @@ -0,0 +1,89 @@ +//***************************************************************************** +// +// ssi.h - Prototypes for the Synchronous Serial Interface Driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __SSI_H__ +#define __SSI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear +// as the ulIntFlags parameter, and returned by SSIIntStatus. +// +//***************************************************************************** +#define SSI_TXFF 0x00000008 // TX FIFO half empty or less +#define SSI_RXFF 0x00000004 // RX FIFO half full or less +#define SSI_RXTO 0x00000002 // RX timeout +#define SSI_RXOR 0x00000001 // RX overrun + +//***************************************************************************** +// +// Values that can be passed to SSIConfig. +// +//***************************************************************************** +#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0 +#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1 +#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0 +#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1 +#define SSI_FRF_TI 0x00000010 // TI frame format +#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format + +#define SSI_MODE_MASTER 0x00000000 // SSI master +#define SSI_MODE_SLAVE 0x00000001 // SSI slave +#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void SSIConfig(unsigned long ulBase, unsigned long ulProtocol, + unsigned long ulMode, unsigned long ulBitRate, + unsigned long ulDataWidth); +extern void SSIDataGet(unsigned long ulBase, unsigned long *pulData); +extern long SSIDataNonBlockingGet(unsigned long ulBase, + unsigned long *pulData); +extern void SSIDataPut(unsigned long ulBase, unsigned long ulData); +extern long SSIDataNonBlockingPut(unsigned long ulBase, unsigned long ulData); +extern void SSIDisable(unsigned long ulBase); +extern void SSIEnable(unsigned long ulBase); +extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void SSIIntUnregister(unsigned long ulBase); + +#ifdef __cplusplus +} +#endif + +#endif // __SSI_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/sysctl.c b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/sysctl.c new file mode 100644 index 000000000..539d0f76d --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/sysctl.c @@ -0,0 +1,1889 @@ +//***************************************************************************** +// +// sysctl.c - Driver for the system controller. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. ALl rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup sysctl_api +//! @{ +// +//***************************************************************************** + +#include "../hw_ints.h" +#include "../hw_memmap.h" +#include "../hw_nvic.h" +#include "../hw_sysctl.h" +#include "../hw_types.h" +#include "cpu.h" +#include "debug.h" +#include "interrupt.h" +#include "sysctl.h" + +//***************************************************************************** +// +// An array that maps the "peripheral set" number (which is stored in the upper +// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL DC? register that +// contains the peripheral present bit for that peripheral. +// +//***************************************************************************** +#if defined(GROUP_puldcregs) || defined(BUILD_ALL) +const unsigned long g_pulDCRegs[] = +{ + SYSCTL_DC1, + SYSCTL_DC2, + SYSCTL_DC4, + SYSCTL_DC1 +}; +#else +extern const unsigned long g_pulDCRegs[]; +#endif + +//***************************************************************************** +// +// An array that maps the "peripheral set" number (which is stored in the upper +// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_SRCR? register that +// controls the software reset for that peripheral. +// +//***************************************************************************** +#if defined(GROUP_pulsrcrregs) || defined(BUILD_ALL) +const unsigned long g_pulSRCRRegs[] = +{ + SYSCTL_SRCR0, + SYSCTL_SRCR1, + SYSCTL_SRCR2 +}; +#else +extern const unsigned long g_pulSRCRRegs[]; +#endif + +//***************************************************************************** +// +// An array that maps the "peripheral set" number (which is stored in the upper +// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_RCGC? register that +// controls the run-mode enable for that peripheral. +// +//***************************************************************************** +#if defined(GROUP_pulrcgcregs) || defined(BUILD_ALL) +const unsigned long g_pulRCGCRegs[] = +{ + SYSCTL_RCGC0, + SYSCTL_RCGC1, + SYSCTL_RCGC2 +}; +#else +extern const unsigned long g_pulRCGCRegs[]; +#endif + +//***************************************************************************** +// +// An array that maps the "peripheral set" number (which is stored in the upper +// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_SCGC? register that +// controls the sleep-mode enable for that peripheral. +// +//***************************************************************************** +#if defined(GROUP_pulscgcregs) || defined(BUILD_ALL) +const unsigned long g_pulSCGCRegs[] = +{ + SYSCTL_SCGC0, + SYSCTL_SCGC1, + SYSCTL_SCGC2 +}; +#else +extern const unsigned long g_pulSCGCRegs[]; +#endif + +//***************************************************************************** +// +// An array that maps the "peripheral set" number (which is stored in the upper +// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_DCGC? register that +// controls the deep-sleep-mode enable for that peripheral. +// +//***************************************************************************** +#if defined(GROUP_pulDCGCregs) || defined(BUILD_ALL) +const unsigned long g_pulDCGCRegs[] = +{ + SYSCTL_DCGC0, + SYSCTL_DCGC1, + SYSCTL_DCGC2 +}; +#else +extern const unsigned long g_pulDCGCRegs[]; +#endif + +//***************************************************************************** +// +// An array that maps the crystal number in RCC to a frequency. +// +//***************************************************************************** +#if defined(GROUP_pulxtals) || defined(BUILD_ALL) +const unsigned long g_pulXtals[] = +{ + 3579545, + 3686400, + 4000000, + 4096000, + 4915200, + 5000000, + 5120000, + 6000000, + 6144000, + 7372800, + 8000000, + 8192000 +}; +#else +extern const unsigned long g_pulXtals[]; +#endif + +//***************************************************************************** +// +//! Gets the size of the SRAM. +//! +//! This function determines the size of the SRAM on the Stellaris device. +//! +//! \return The total number of bytes of SRAM. +// +//***************************************************************************** +#if defined(GROUP_sramsizeget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +SysCtlSRAMSizeGet(void) +{ + // + // Compute the size of the SRAM. + // + return(((HWREG(SYSCTL_DC0) & SYSCTL_DC0_SRAMSZ_MASK) >> 8) + 0x100); +} +#endif + +//***************************************************************************** +// +//! Gets the size of the flash. +//! +//! This function determines the size of the flash on the Stellaris device. +//! +//! \return The total number of bytes of flash. +// +//***************************************************************************** +#if defined(GROUP_flashsizeget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +SysCtlFlashSizeGet(void) +{ + // + // Compute the size of the flash. + // + return(((HWREG(SYSCTL_DC0) & SYSCTL_DC0_FLASHSZ_MASK) << 11) + 0x800); +} +#endif + +//***************************************************************************** +// +//! Determines if a pin is present. +//! +//! \param ulPin is the pin in question. +//! +//! Determines if a particular pin is present in the device. The PWM, analog +//! comparators, ADC, and timers have a varying number of pins across members +//! of the Stellaris family; this will determine which are present on this +//! device. +//! +//! The \b ulPin argument must be only one of the following values: +//! \b SYSCTL_PIN_PWM0, \b SYSCTL_PIN_PWM1, \b SYSCTL_PIN_PWM2, +//! \b SYSCTL_PIN_PWM3, \b SYSCTL_PIN_PWM4, \b SYSCTL_PIN_PWM5, +//! \b SYSCTL_PIN_C0MINUS, \b SYSCTL_PIN_C0PLUS, \b SYSCTL_PIN_C0O, +//! \b SYSCTL_PIN_C1MINUS, \b SYSCTL_PIN_C1PLUS, \b SYSCTL_PIN_C1O, +//! \b SYSCTL_PIN_C2MINUS, \b SYSCTL_PIN_C2PLUS, \b SYSCTL_PIN_C2O, +//! \b SYSCTL_PIN_ADC0, \b SYSCTL_PIN_ADC1, \b SYSCTL_PIN_ADC2, +//! \b SYSCTL_PIN_ADC3, \b SYSCTL_PIN_ADC4, \b SYSCTL_PIN_ADC5, +//! \b SYSCTL_PIN_ADC6, \b SYSCTL_PIN_ADC7, \b SYSCTL_PIN_CCP0, +//! \b SYSCTL_PIN_CCP1, \b SYSCTL_PIN_CCP2, \b SYSCTL_PIN_CCP3, +//! \b SYSCTL_PIN_CCP4, \b SYSCTL_PIN_CCP5, or \b SYSCTL_PIN_32KHZ. +//! +//! \return Returns \b true if the specified pin is present and \b false if it +//! is not. +// +//***************************************************************************** +#if defined(GROUP_pinpresent) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +SysCtlPinPresent(unsigned long ulPin) +{ + // + // Check the arguments. + // + ASSERT((ulPin == SYSCTL_PIN_PWM0) || + (ulPin == SYSCTL_PIN_PWM1) || + (ulPin == SYSCTL_PIN_PWM2) || + (ulPin == SYSCTL_PIN_PWM3) || + (ulPin == SYSCTL_PIN_PWM4) || + (ulPin == SYSCTL_PIN_PWM5) || + (ulPin == SYSCTL_PIN_C0MINUS) || + (ulPin == SYSCTL_PIN_C0PLUS) || + (ulPin == SYSCTL_PIN_C0O) || + (ulPin == SYSCTL_PIN_C1MINUS) || + (ulPin == SYSCTL_PIN_C1PLUS) || + (ulPin == SYSCTL_PIN_C1O) || + (ulPin == SYSCTL_PIN_C2MINUS) || + (ulPin == SYSCTL_PIN_C2PLUS) || + (ulPin == SYSCTL_PIN_C2O) || + (ulPin == SYSCTL_PIN_ADC0) || + (ulPin == SYSCTL_PIN_ADC1) || + (ulPin == SYSCTL_PIN_ADC2) || + (ulPin == SYSCTL_PIN_ADC3) || + (ulPin == SYSCTL_PIN_ADC4) || + (ulPin == SYSCTL_PIN_ADC5) || + (ulPin == SYSCTL_PIN_ADC6) || + (ulPin == SYSCTL_PIN_ADC7) || + (ulPin == SYSCTL_PIN_CCP0) || + (ulPin == SYSCTL_PIN_CCP1) || + (ulPin == SYSCTL_PIN_CCP2) || + (ulPin == SYSCTL_PIN_CCP3) || + (ulPin == SYSCTL_PIN_CCP4) || + (ulPin == SYSCTL_PIN_CCP5) || + (ulPin == SYSCTL_PIN_32KHZ)) + + // + // Determine if this pin is present. + // + if(HWREG(SYSCTL_DC3) & ulPin) + { + return(true); + } + else + { + return(false); + } +} +#endif + +//***************************************************************************** +// +//! Determines if a peripheral is present. +//! +//! \param ulPeripheral is the peripheral in question. +//! +//! Determines if a particular peripheral is present in the device. Each +//! member of the Stellaris family has a different peripheral set; this will +//! determine which are present on this device. +//! +//! The \b ulPeripheral argument must be only one of the following values: +//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG, +//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI, +//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0, +//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA, +//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, +//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_MPU, \b SYSCTL_PERIPH_TEMP, or +//! \b SYSCTL_PERIPH_PLL. +//! +//! \return Returns \b true if the specified peripheral is present and \b false +//! if it is not. +// +//***************************************************************************** +#if defined(GROUP_peripheralpresent) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +SysCtlPeripheralPresent(unsigned long ulPeripheral) +{ + // + // Check the arguments. + // + ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) || + (ulPeripheral == SYSCTL_PERIPH_ADC) || + (ulPeripheral == SYSCTL_PERIPH_WDOG) || + (ulPeripheral == SYSCTL_PERIPH_UART0) || + (ulPeripheral == SYSCTL_PERIPH_UART1) || + (ulPeripheral == SYSCTL_PERIPH_SSI) || + (ulPeripheral == SYSCTL_PERIPH_QEI) || + (ulPeripheral == SYSCTL_PERIPH_I2C) || + (ulPeripheral == SYSCTL_PERIPH_TIMER0) || + (ulPeripheral == SYSCTL_PERIPH_TIMER1) || + (ulPeripheral == SYSCTL_PERIPH_TIMER2) || + (ulPeripheral == SYSCTL_PERIPH_COMP0) || + (ulPeripheral == SYSCTL_PERIPH_COMP1) || + (ulPeripheral == SYSCTL_PERIPH_COMP2) || + (ulPeripheral == SYSCTL_PERIPH_GPIOA) || + (ulPeripheral == SYSCTL_PERIPH_GPIOB) || + (ulPeripheral == SYSCTL_PERIPH_GPIOC) || + (ulPeripheral == SYSCTL_PERIPH_GPIOD) || + (ulPeripheral == SYSCTL_PERIPH_GPIOE) || + (ulPeripheral == SYSCTL_PERIPH_MPU) || + (ulPeripheral == SYSCTL_PERIPH_TEMP) || + (ulPeripheral == SYSCTL_PERIPH_PLL)); + + // + // Read the correct DC register and determine if this peripheral exists. + // + if(HWREG(g_pulDCRegs[ulPeripheral >> 28]) & ulPeripheral & 0x0fffffff) + { + return(true); + } + else + { + return(false); + } +} +#endif + +//***************************************************************************** +// +//! Performs a software reset of a peripheral. +//! +//! \param ulPeripheral is the peripheral to reset. +//! +//! This function performs a software reset of the specified peripheral. An +//! individual peripheral reset signal is asserted for a brief period and then +//! deasserted, leaving the peripheral in a operating state but in its reset +//! condition. +//! +//! The \b ulPeripheral argument must be only one of the following values: +//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG, +//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI, +//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0, +//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA, +//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or +//! \b SYSCTL_PERIPH_GPIOE. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_peripheralreset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlPeripheralReset(unsigned long ulPeripheral) +{ + volatile unsigned long ulDelay; + + // + // Check the arguments. + // + ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) || + (ulPeripheral == SYSCTL_PERIPH_ADC) || + (ulPeripheral == SYSCTL_PERIPH_WDOG) || + (ulPeripheral == SYSCTL_PERIPH_UART0) || + (ulPeripheral == SYSCTL_PERIPH_UART1) || + (ulPeripheral == SYSCTL_PERIPH_SSI) || + (ulPeripheral == SYSCTL_PERIPH_QEI) || + (ulPeripheral == SYSCTL_PERIPH_I2C) || + (ulPeripheral == SYSCTL_PERIPH_TIMER0) || + (ulPeripheral == SYSCTL_PERIPH_TIMER1) || + (ulPeripheral == SYSCTL_PERIPH_TIMER2) || + (ulPeripheral == SYSCTL_PERIPH_COMP0) || + (ulPeripheral == SYSCTL_PERIPH_COMP1) || + (ulPeripheral == SYSCTL_PERIPH_COMP2) || + (ulPeripheral == SYSCTL_PERIPH_GPIOA) || + (ulPeripheral == SYSCTL_PERIPH_GPIOB) || + (ulPeripheral == SYSCTL_PERIPH_GPIOC) || + (ulPeripheral == SYSCTL_PERIPH_GPIOD) || + (ulPeripheral == SYSCTL_PERIPH_GPIOE)); + + // + // Put the peripheral into the reset state. + // + HWREG(g_pulSRCRRegs[ulPeripheral >> 28]) |= ulPeripheral & 0x0fffffff; + + // + // Delay for a little bit. + // + for(ulDelay = 0; ulDelay < 16; ulDelay++) + { + } + + // + // Take the peripheral out of the reset state. + // + HWREG(g_pulSRCRRegs[ulPeripheral >> 28]) &= ~(ulPeripheral); +} +#endif + +//***************************************************************************** +// +//! Enables a peripheral. +//! +//! \param ulPeripheral is the peripheral to enable. +//! +//! Peripherals are enabled with this function. At power-up, all peripherals +//! are disabled; they must be enabled in order to operate or respond to +//! register reads/writes. +//! +//! The \b ulPeripheral argument must be only one of the following values: +//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG, +//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI, +//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0, +//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA, +//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or +//! \b SYSCTL_PERIPH_GPIOE. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_peripheralenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlPeripheralEnable(unsigned long ulPeripheral) +{ + // + // Check the arguments. + // + ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) || + (ulPeripheral == SYSCTL_PERIPH_ADC) || + (ulPeripheral == SYSCTL_PERIPH_WDOG) || + (ulPeripheral == SYSCTL_PERIPH_UART0) || + (ulPeripheral == SYSCTL_PERIPH_UART1) || + (ulPeripheral == SYSCTL_PERIPH_SSI) || + (ulPeripheral == SYSCTL_PERIPH_QEI) || + (ulPeripheral == SYSCTL_PERIPH_I2C) || + (ulPeripheral == SYSCTL_PERIPH_TIMER0) || + (ulPeripheral == SYSCTL_PERIPH_TIMER1) || + (ulPeripheral == SYSCTL_PERIPH_TIMER2) || + (ulPeripheral == SYSCTL_PERIPH_COMP0) || + (ulPeripheral == SYSCTL_PERIPH_COMP1) || + (ulPeripheral == SYSCTL_PERIPH_COMP2) || + (ulPeripheral == SYSCTL_PERIPH_GPIOA) || + (ulPeripheral == SYSCTL_PERIPH_GPIOB) || + (ulPeripheral == SYSCTL_PERIPH_GPIOC) || + (ulPeripheral == SYSCTL_PERIPH_GPIOD) || + (ulPeripheral == SYSCTL_PERIPH_GPIOE)); + + // + // Enable this peripheral. + // + HWREG(g_pulRCGCRegs[ulPeripheral >> 28]) |= ulPeripheral & 0x0fffffff; +} +#endif + +//***************************************************************************** +// +//! Disables a peripheral. +//! +//! \param ulPeripheral is the peripheral to disable. +//! +//! Peripherals are disabled with this function. Once disabled, they will not +//! operate or respond to register reads/writes. +//! +//! The \b ulPeripheral argument must be only one of the following values: +//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG, +//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI, +//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0, +//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA, +//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or +//! \b SYSCTL_PERIPH_GPIOE. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_peripheraldisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlPeripheralDisable(unsigned long ulPeripheral) +{ + // + // Check the arguments. + // + ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) || + (ulPeripheral == SYSCTL_PERIPH_ADC) || + (ulPeripheral == SYSCTL_PERIPH_WDOG) || + (ulPeripheral == SYSCTL_PERIPH_UART0) || + (ulPeripheral == SYSCTL_PERIPH_UART1) || + (ulPeripheral == SYSCTL_PERIPH_SSI) || + (ulPeripheral == SYSCTL_PERIPH_QEI) || + (ulPeripheral == SYSCTL_PERIPH_I2C) || + (ulPeripheral == SYSCTL_PERIPH_TIMER0) || + (ulPeripheral == SYSCTL_PERIPH_TIMER1) || + (ulPeripheral == SYSCTL_PERIPH_TIMER2) || + (ulPeripheral == SYSCTL_PERIPH_COMP0) || + (ulPeripheral == SYSCTL_PERIPH_COMP1) || + (ulPeripheral == SYSCTL_PERIPH_COMP2) || + (ulPeripheral == SYSCTL_PERIPH_GPIOA) || + (ulPeripheral == SYSCTL_PERIPH_GPIOB) || + (ulPeripheral == SYSCTL_PERIPH_GPIOC) || + (ulPeripheral == SYSCTL_PERIPH_GPIOD) || + (ulPeripheral == SYSCTL_PERIPH_GPIOE)); + + // + // Disable this peripheral. + // + HWREG(g_pulRCGCRegs[ulPeripheral >> 28]) &= ~(ulPeripheral & 0x0fffffff); +} +#endif + +//***************************************************************************** +// +//! Enables a peripheral in sleep mode. +//! +//! \param ulPeripheral is the peripheral to enable in sleep mode. +//! +//! This function allows a peripheral to continue operating when the processor +//! goes into sleep mode. Since the clocking configuration of the device does +//! not change, any peripheral can safely continue operating while the +//! processor is in sleep mode, and can therefore wake the processor from sleep +//! mode. +//! +//! Sleep mode clocking of peripherals must be enabled via +//! SysCtlPeripheralClockGating(); if disabled, the peripheral sleep mode +//! configuration is maintained but has no effect when sleep mode is entered. +//! +//! The \b ulPeripheral argument must be only one of the following values: +//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG, +//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI, +//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0, +//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA, +//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or +//! \b SYSCTL_PERIPH_GPIOE. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_peripheralsleepenable) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +SysCtlPeripheralSleepEnable(unsigned long ulPeripheral) +{ + // + // Check the arguments. + // + ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) || + (ulPeripheral == SYSCTL_PERIPH_ADC) || + (ulPeripheral == SYSCTL_PERIPH_WDOG) || + (ulPeripheral == SYSCTL_PERIPH_UART0) || + (ulPeripheral == SYSCTL_PERIPH_UART1) || + (ulPeripheral == SYSCTL_PERIPH_SSI) || + (ulPeripheral == SYSCTL_PERIPH_QEI) || + (ulPeripheral == SYSCTL_PERIPH_I2C) || + (ulPeripheral == SYSCTL_PERIPH_TIMER0) || + (ulPeripheral == SYSCTL_PERIPH_TIMER1) || + (ulPeripheral == SYSCTL_PERIPH_TIMER2) || + (ulPeripheral == SYSCTL_PERIPH_COMP0) || + (ulPeripheral == SYSCTL_PERIPH_COMP1) || + (ulPeripheral == SYSCTL_PERIPH_COMP2) || + (ulPeripheral == SYSCTL_PERIPH_GPIOA) || + (ulPeripheral == SYSCTL_PERIPH_GPIOB) || + (ulPeripheral == SYSCTL_PERIPH_GPIOC) || + (ulPeripheral == SYSCTL_PERIPH_GPIOD) || + (ulPeripheral == SYSCTL_PERIPH_GPIOE)); + + // + // Enable this peripheral in sleep mode. + // + HWREG(g_pulSCGCRegs[ulPeripheral >> 28]) |= ulPeripheral & 0x0fffffff; +} +#endif + +//***************************************************************************** +// +//! Disables a peripheral in sleep mode. +//! +//! \param ulPeripheral is the peripheral to disable in sleep mode. +//! +//! This function causes a peripheral to stop operating when the processor goes +//! into sleep mode. Disabling peripherals while in sleep mode helps to lower +//! the current draw of the device. If enabled (via SysCtlPeripheralEnable()), +//! the peripheral will automatically resume operation when the processor +//! leaves sleep mode, maintaining its entire state from before sleep mode was +//! entered. +//! +//! Sleep mode clocking of peripherals must be enabled via +//! SysCtlPeripheralClockGating(); if disabled, the peripheral sleep mode +//! configuration is maintained but has no effect when sleep mode is entered. +//! +//! The \b ulPeripheral argument must be only one of the following values: +//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG, +//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI, +//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0, +//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA, +//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or +//! \b SYSCTL_PERIPH_GPIOE. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_peripheralsleepdisable) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +SysCtlPeripheralSleepDisable(unsigned long ulPeripheral) +{ + // + // Check the arguments. + // + ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) || + (ulPeripheral == SYSCTL_PERIPH_ADC) || + (ulPeripheral == SYSCTL_PERIPH_WDOG) || + (ulPeripheral == SYSCTL_PERIPH_UART0) || + (ulPeripheral == SYSCTL_PERIPH_UART1) || + (ulPeripheral == SYSCTL_PERIPH_SSI) || + (ulPeripheral == SYSCTL_PERIPH_QEI) || + (ulPeripheral == SYSCTL_PERIPH_I2C) || + (ulPeripheral == SYSCTL_PERIPH_TIMER0) || + (ulPeripheral == SYSCTL_PERIPH_TIMER1) || + (ulPeripheral == SYSCTL_PERIPH_TIMER2) || + (ulPeripheral == SYSCTL_PERIPH_COMP0) || + (ulPeripheral == SYSCTL_PERIPH_COMP1) || + (ulPeripheral == SYSCTL_PERIPH_COMP2) || + (ulPeripheral == SYSCTL_PERIPH_GPIOA) || + (ulPeripheral == SYSCTL_PERIPH_GPIOB) || + (ulPeripheral == SYSCTL_PERIPH_GPIOC) || + (ulPeripheral == SYSCTL_PERIPH_GPIOD) || + (ulPeripheral == SYSCTL_PERIPH_GPIOE)); + + // + // Disable this peripheral in sleep mode. + // + HWREG(g_pulSCGCRegs[ulPeripheral >> 28]) &= ~(ulPeripheral & 0x0fffffff); +} +#endif + +//***************************************************************************** +// +//! Enables a peripheral in deep-sleep mode. +//! +//! \param ulPeripheral is the peripheral to enable in deep-sleep mode. +//! +//! This function allows a peripheral to continue operating when the processor +//! goes into deep-sleep mode. Since the clocking configuration of the device +//! may change, not all peripherals can safely continue operating while the +//! processor is in sleep mode. Those that must run at a particular frequency +//! (such as a UART) will not work as expected if the clock changes. It is the +//! responsibility of the caller to make sensible choices. +//! +//! Deep-sleep mode clocking of peripherals must be enabled via +//! SysCtlPeripheralClockGating(); if disabled, the peripheral deep-sleep mode +//! configuration is maintained but has no effect when deep-sleep mode is +//! entered. +//! +//! The \b ulPeripheral argument must be one of the following values: +//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG, +//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI, +//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0, +//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA, +//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or +//! \b SYSCTL_PERIPH_GPIOE. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_peripheraldeepsleepenable) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral) +{ + // + // Check the arguments. + // + ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) || + (ulPeripheral == SYSCTL_PERIPH_ADC) || + (ulPeripheral == SYSCTL_PERIPH_WDOG) || + (ulPeripheral == SYSCTL_PERIPH_UART0) || + (ulPeripheral == SYSCTL_PERIPH_UART1) || + (ulPeripheral == SYSCTL_PERIPH_SSI) || + (ulPeripheral == SYSCTL_PERIPH_QEI) || + (ulPeripheral == SYSCTL_PERIPH_I2C) || + (ulPeripheral == SYSCTL_PERIPH_TIMER0) || + (ulPeripheral == SYSCTL_PERIPH_TIMER1) || + (ulPeripheral == SYSCTL_PERIPH_TIMER2) || + (ulPeripheral == SYSCTL_PERIPH_COMP0) || + (ulPeripheral == SYSCTL_PERIPH_COMP1) || + (ulPeripheral == SYSCTL_PERIPH_COMP2) || + (ulPeripheral == SYSCTL_PERIPH_GPIOA) || + (ulPeripheral == SYSCTL_PERIPH_GPIOB) || + (ulPeripheral == SYSCTL_PERIPH_GPIOC) || + (ulPeripheral == SYSCTL_PERIPH_GPIOD) || + (ulPeripheral == SYSCTL_PERIPH_GPIOE)); + + // + // Enable this peripheral in deep-sleep mode. + // + HWREG(g_pulDCGCRegs[ulPeripheral >> 28]) |= ulPeripheral & 0x0fffffff; +} +#endif + +//***************************************************************************** +// +//! Disables a peripheral in deep-sleep mode. +//! +//! \param ulPeripheral is the peripheral to disable in deep-sleep mode. +//! +//! This function causes a peripheral to stop operating when the processor goes +//! into deep-sleep mode. Disabling peripherals while in deep-sleep mode helps +//! to lower the current draw of the device, and can keep peripherals that +//! require a particular clock frequency from operating when the clock changes +//! as a result of entering deep-sleep mode. If enabled (via +//! SysCtlPeripheralEnable()), the peripheral will automatically resume +//! operation when the processor leaves deep-sleep mode, maintaining its entire +//! state from before deep-sleep mode was entered. +//! +//! Deep-sleep mode clocking of peripherals must be enabled via +//! SysCtlPeripheralClockGating(); if disabled, the peripheral deep-sleep mode +//! configuration is maintained but has no effect when deep-sleep mode is +//! entered. +//! +//! The \b ulPeripheral argument must be one of the following values: +//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG, +//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI, +//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0, +//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA, +//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or +//! \b SYSCTL_PERIPH_GPIOE. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_peripheraldeepsleepdisable) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral) +{ + // + // Check the arguments. + // + ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) || + (ulPeripheral == SYSCTL_PERIPH_ADC) || + (ulPeripheral == SYSCTL_PERIPH_WDOG) || + (ulPeripheral == SYSCTL_PERIPH_UART0) || + (ulPeripheral == SYSCTL_PERIPH_UART1) || + (ulPeripheral == SYSCTL_PERIPH_SSI) || + (ulPeripheral == SYSCTL_PERIPH_QEI) || + (ulPeripheral == SYSCTL_PERIPH_I2C) || + (ulPeripheral == SYSCTL_PERIPH_TIMER0) || + (ulPeripheral == SYSCTL_PERIPH_TIMER1) || + (ulPeripheral == SYSCTL_PERIPH_TIMER2) || + (ulPeripheral == SYSCTL_PERIPH_COMP0) || + (ulPeripheral == SYSCTL_PERIPH_COMP1) || + (ulPeripheral == SYSCTL_PERIPH_COMP2) || + (ulPeripheral == SYSCTL_PERIPH_GPIOA) || + (ulPeripheral == SYSCTL_PERIPH_GPIOB) || + (ulPeripheral == SYSCTL_PERIPH_GPIOC) || + (ulPeripheral == SYSCTL_PERIPH_GPIOD) || + (ulPeripheral == SYSCTL_PERIPH_GPIOE)); + + // + // Disable this peripheral in deep-sleep mode. + // + HWREG(g_pulDCGCRegs[ulPeripheral >> 28]) &= ~(ulPeripheral & 0x0fffffff); +} +#endif + +//***************************************************************************** +// +//! Controls peripheral clock gating in sleep and deep-sleep mode. +//! +//! \param bEnable is a boolean that is \b true if the sleep and deep-sleep +//! peripheral configuration should be used and \b false if not. +//! +//! This function controls how peripherals are clocked when the processor goes +//! into sleep or deep-sleep mode. By default, the peripherals are clocked the +//! same as in run mode; if peripheral clock gating is enabled they are clocked +//! according to the configuration set by SysCtlPeripheralSleepEnable(), +//! SysCtlPeripheralSleepDisable(), SysCtlPeripheralDeepSleepEnable(), and +//! SysCtlPeripheralDeepSleepDisable(). +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_peripheralclockgating) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +SysCtlPeripheralClockGating(tBoolean bEnable) +{ + // + // Enable peripheral clock gating as requested. + // + if(bEnable) + { + HWREG(SYSCTL_RCC) |= SYSCTL_RCC_ACG; + } + else + { + HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_ACG); + } +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for the system control interrupt. +//! +//! \param pfnHandler is a pointer to the function to be called when the system +//! control interrupt occurs. +//! +//! This sets the handler to be called when a system control interrupt occurs. +//! This will enable the global interrupt in the interrupt controller; specific +//! system control interrupts must be enabled via SysCtlIntEnable(). It is the +//! interrupt handler's responsibility to clear the interrupt source via +//! SysCtlIntClear(). +//! +//! System control can generate interrupts when the PLL achieves lock, if the +//! internal LDO current limit is exceeded, if the internal oscillator fails, +//! if the main oscillator fails, if the internal LDO output voltage droops too +//! much, if the external voltage droops too much, or if the PLL fails. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlIntRegister(void (*pfnHandler)(void)) +{ + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(INT_SYSCTL, pfnHandler); + + // + // Enable the system control interrupt. + // + IntEnable(INT_SYSCTL); +} +#endif + +//***************************************************************************** +// +//! Unregisters the interrupt handler for the system control interrupt. +//! +//! This function will clear the handler to be called when a system control +//! interrupt occurs. This will also mask off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlIntUnregister(void) +{ + // + // Disable the interrupt. + // + IntDisable(INT_SYSCTL); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_SYSCTL); +} +#endif + +//***************************************************************************** +// +//! Enables individual system control interrupt sources. +//! +//! \param ulInts is a bit mask of the interrupt sources to be enabled. Must +//! be a logical OR of \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT, +//! \b SYSCTL_INT_IOSC_FAIL, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR, +//! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL. +//! +//! Enables the indicated system control interrupt sources. Only the sources +//! that are enabled can be reflected to the processor interrupt; disabled +//! sources have no effect on the processor. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlIntEnable(unsigned long ulInts) +{ + // + // Enable the specified interrupts. + // + HWREG(SYSCTL_IMC) |= ulInts; +} +#endif + +//***************************************************************************** +// +//! Disables individual system control interrupt sources. +//! +//! \param ulInts is a bit mask of the interrupt sources to be disabled. Must +//! be a logical OR of \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT, +//! \b SYSCTL_INT_IOSC_FAIL, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR, +//! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL. +//! +//! Disables the indicated system control interrupt sources. Only the sources +//! that are enabled can be reflected to the processor interrupt; disabled +//! sources have no effect on the processor. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlIntDisable(unsigned long ulInts) +{ + // + // Disable the specified interrupts. + // + HWREG(SYSCTL_IMC) &= ~(ulInts); +} +#endif + +//***************************************************************************** +// +//! Clears system control interrupt sources. +//! +//! \param ulInts is a bit mask of the interrupt sources to be cleared. Must +//! be a logical OR of \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT, +//! \b SYSCTL_INT_IOSC_FAIL, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR, +//! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL. +//! +//! The specified system control interrupt sources are cleared, so that they no +//! longer assert. This must be done in the interrupt handler to keep it from +//! being called again immediately upon exit. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlIntClear(unsigned long ulInts) +{ + // + // Clear the requested interrupt sources. + // + HWREG(SYSCTL_MISC) = ulInts; +} +#endif + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param bMasked is false if the raw interrupt status is required and true if +//! the masked interrupt status is required. +//! +//! This returns the interrupt status for the system controller. Either the +//! raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT, \b SYSCTL_INT_IOSC_FAIL, +//! \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR, \b SYSCTL_INT_BOR, and +//! \b SYSCTL_INT_PLL_FAIL. +// +//***************************************************************************** +#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +SysCtlIntStatus(tBoolean bMasked) +{ + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(SYSCTL_MISC)); + } + else + { + return(HWREG(SYSCTL_RIS)); + } +} +#endif + +//***************************************************************************** +// +//! Sets the output voltage of the LDO. +//! +//! \param ulVoltage is the required output voltage from the LDO. Must be one +//! of \b SYSCTL_LDO_2_25V, \b SYSCTL_LDO_2_30V, \b SYSCTL_LDO_2_35V, +//! \b SYSCTL_LDO_2_40V, \b SYSCTL_LDO_2_45V, \b SYSCTL_LDO_2_50V, +//! \b SYSCTL_LDO_2_55V, \b SYSCTL_LDO_2_60V, \b SYSCTL_LDO_2_65V, +//! \b SYSCTL_LDO_2_70V, or \b SYSCTL_LDO_2_75V. +//! +//! This function sets the output voltage of the LDO. The default voltage is +//! 2.5 V; it can be adjusted +/- 10%. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_ldoset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlLDOSet(unsigned long ulVoltage) +{ + // + // Check the arguments. + // + ASSERT((ulVoltage == SYSCTL_LDO_2_25V) || + (ulVoltage == SYSCTL_LDO_2_30V) || + (ulVoltage == SYSCTL_LDO_2_35V) || + (ulVoltage == SYSCTL_LDO_2_40V) || + (ulVoltage == SYSCTL_LDO_2_45V) || + (ulVoltage == SYSCTL_LDO_2_50V) || + (ulVoltage == SYSCTL_LDO_2_55V) || + (ulVoltage == SYSCTL_LDO_2_60V) || + (ulVoltage == SYSCTL_LDO_2_65V) || + (ulVoltage == SYSCTL_LDO_2_70V) || + (ulVoltage == SYSCTL_LDO_2_75V)); + + // + // Set the LDO voltage to the requested value. + // + HWREG(SYSCTL_LDOPCTL) = ulVoltage; +} +#endif + +//***************************************************************************** +// +//! Gets the output voltage of the LDO. +//! +//! This function determines the output voltage of the LDO, as specified by the +//! control register. +//! +//! \return Returns the current voltage of the LDO; will be one of +//! \b SYSCTL_LDO_2_25V, \b SYSCTL_LDO_2_30V, \b SYSCTL_LDO_2_35V, +//! \b SYSCTL_LDO_2_40V, \b SYSCTL_LDO_2_45V, \b SYSCTL_LDO_2_50V, +//! \b SYSCTL_LDO_2_55V, \b SYSCTL_LDO_2_60V, \b SYSCTL_LDO_2_65V, +//! \b SYSCTL_LDO_2_70V, or \b SYSCTL_LDO_2_75V. +// +//***************************************************************************** +#if defined(GROUP_ldoget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +SysCtlLDOGet(void) +{ + // + // Return the LDO voltage setting. + // + return(HWREG(SYSCTL_LDOPCTL)); +} +#endif + +//***************************************************************************** +// +//! Configures the LDO failure control. +//! +//! \param ulConfig is the required LDO failure control setting; can be either +//! \b SYSCTL_LDOCFG_ARST or \b SYSCTL_LDOCFG_NORST. +//! +//! This function allows the LDO to be configured to cause a processor reset +//! when the output voltage becomes unregulated. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_ldoconfigset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlLDOConfigSet(unsigned long ulConfig) +{ + // + // Check hte arguments. + // + ASSERT((ulConfig == SYSCTL_LDOCFG_ARST) || + (ulConfig == SYSCTL_LDOCFG_NORST)); + + // + // Set the reset control as requested. + // + HWREG(SYSCTL_LDOARST) = ulConfig; +} +#endif + +//***************************************************************************** +// +//! Resets the device. +//! +//! This function will perform a software reset of the entire device. The +//! processor and all peripherals will be reset and all device registers will +//! return to their default values (with the exception of the reset cause +//! register, which will maintain its current value but have the software reset +//! bit set as well). +//! +//! \return This function does not return. +// +//***************************************************************************** +#if defined(GROUP_reset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlReset(void) +{ + // + // Perform a software reset request. This will cause the device to reset, + // no further code will be executed. + // + HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | NVIC_APINT_SYSRESETREQ; + + // + // The device should have reset, so this should never be reached. Just in + // case, loop forever. + // + while(1) + { + } +} +#endif + +//***************************************************************************** +// +//! Puts the processor into sleep mode. +//! +//! This function places the processor into sleep mode; it will not return +//! until the processor returns to run mode. The peripherals that are enabled +//! via SysCtlPeripheralSleepEnable() continue to operate and can wake up the +//! processor (if automatic clock gating is enabled with +//! SysCtlPeripheralClockGating(), otherwise all peripherals continue to +//! operate). +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_sleep) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlSleep(void) +{ + // + // Wait for an interrupt. + // + CPUwfi(); +} +#endif + +//***************************************************************************** +// +//! Puts the processor into deep-sleep mode. +//! +//! This function places the processor into deep-sleep mode; it will not return +//! until the processor returns to run mode. The peripherals that are enabled +//! via SysCtlPeripheralDeepSleepEnable() continue to operate and can wake up +//! the processor (if automatic clock gating is enabled with +//! SysCtlPeripheralClockGating(), otherwise all peripherals continue to +//! operate). +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_deepsleep) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlDeepSleep(void) +{ + // + // Enable deep-sleep. + // + HWREG(NVIC_SYS_CTRL) |= NVIC_SYS_CTRL_SLEEPDEEP; + + // + // Wait for an interrupt. + // + CPUwfi(); + + // + // Disable deep-sleep so that a future sleep will work correctly. + // + HWREG(NVIC_SYS_CTRL) &= ~(NVIC_SYS_CTRL_SLEEPDEEP); +} +#endif + +//***************************************************************************** +// +//! Gets the reason for a reset. +//! +//! This function will return the reason(s) for a reset. Since the reset +//! reasons are sticky until either cleared by software or an external reset, +//! multiple reset reasons may be returned if multiple resets have occurred. +//! The reset reason will be a logical OR of \b SYSCTL_CAUSE_LDO, +//! \b SYSCTL_CAUSE_SW, \b SYSCTL_CAUSE_WDOG, \b SYSCTL_CAUSE_BOR, +//! \b SYSCTL_CAUSE_POR, and/or \b SYSCTL_CAUSE_EXT. +//! +//! \return The reason(s) for a reset. +// +//***************************************************************************** +#if defined(GROUP_resetcauseget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +SysCtlResetCauseGet(void) +{ + // + // Return the reset reasons. + // + return(HWREG(SYSCTL_RESC)); +} +#endif + +//***************************************************************************** +// +//! Clears reset reasons. +//! +//! \param ulCauses are the reset causes to be cleared; must be a logical OR of +//! \b SYSCTL_CAUSE_LDO, \b SYSCTL_CAUSE_SW, \b SYSCTL_CAUSE_WDOG, +//! \b SYSCTL_CAUSE_BOR, \b SYSCTL_CAUSE_POR, and/or \b SYSCTL_CAUSE_EXT. +//! +//! This function clears the specified sticky reset reasons. Once cleared, +//! another reset for the same reason can be detected, and a reset for a +//! different reason can be distinguished (instead of having two reset causes +//! set). If the reset reason is used by an application, all reset causes +//! should be cleared after they are retrieved with SysCtlResetCauseGet(). +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_resetcauseclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlResetCauseClear(unsigned long ulCauses) +{ + // + // Clear the given reset reasons. + // + HWREG(SYSCTL_RESC) &= ~(ulCauses); +} +#endif + +//***************************************************************************** +// +//! Configures the brown-out control. +//! +//! \param ulConfig is the desired configuration of the brown-out control. +//! Must be the logical OR of \b SYSCTL_BOR_RESET and/or +//! \b SYSCTL_BOR_RESAMPLE. +//! \param ulDelay is the number of internal oscillator cycles to wait before +//! resampling an asserted brown-out signal. This value only has meaning when +//! \b SYSCTL_BOR_RESAMPLE is set and must be less than 8192. +//! +//! This function configures how the brown-out control operates. It can detect +//! a brown-out by looking at only the brown-out output, or it can wait for it +//! to be active for two consecutive samples separated by a configurable time. +//! When it detects a brown-out condition, it can either reset the device or +//! generate a processor interrupt. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_brownoutconfigset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlBrownOutConfigSet(unsigned long ulConfig, unsigned long ulDelay) +{ + // + // Check the arguments. + // + ASSERT(!(ulConfig & ~(SYSCTL_BOR_RESET | SYSCTL_BOR_RESAMPLE))); + ASSERT(ulDelay < 8192); + + // + // Configure the brown-out reset control. + // + HWREG(SYSCTL_PBORCTL) = (ulDelay << SYSCTL_PBORCTL_BOR_SH) | ulConfig; +} +#endif + +//***************************************************************************** +// +//! Sets the clocking of the device. +//! +//! \param ulConfig is the required configuration of the device clocking. +//! +//! This function configures the clocking of the device. The input crystal +//! frequency, oscillator to be used, use of the PLL, and the system clock +//! divider are all configured with this function. +//! +//! The \b ulConfig parameter is the logical OR of several different values, +//! many of which are grouped into sets where only one can be chosen. +//! +//! The system clock divider is chosen with one of the following values: +//! \b SYSCTL_SYSDIV_1, \b SYSCTL_SYSDIV_2, \b SYSCTL_SYSDIV_3, +//! \b SYSCTL_SYSDIV_4, \b SYSCTL_SYSDIV_5, \b SYSCTL_SYSDIV_6, +//! \b SYSCTL_SYSDIV_7, \b SYSCTL_SYSDIV_8, \b SYSCTL_SYSDIV_9, +//! \b SYSCTL_SYSDIV_10, \b SYSCTL_SYSDIV_11, \b SYSCTL_SYSDIV_12, +//! \b SYSCTL_SYSDIV_13, \b SYSCTL_SYSDIV_14, \b SYSCTL_SYSDIV_15, or +//! \b SYSCTL_SYSDIV_16. +//! +//! The use of the PLL is chosen with either \b SYSCTL_USE_PLL or +//! \b SYSCTL_USE_OSC. +//! +//! The external crystal frequency is chosen with one of the following values: +//! \b SYSCTL_XTAL_3_57MHZ, \b SYSCTL_XTAL_3_68MHZ, \b SYSCTL_XTAL_4MHZ, +//! \b SYSCTL_XTAL_4_09MHZ, \b SYSCTL_XTAL_4_91MHZ, \b SYSCTL_XTAL_5MHZ, +//! \b SYSCTL_XTAL_5_12MHZ, \b SYSCTL_XTAL_6MHZ, \b SYSCTL_XTAL_6_14MHZ, +//! \b SYSCTL_XTAL_7_37MHZ, \b SYSCTL_XTAL_8MHZ, or \b SYSCTL_XTAL_8_19MHZ. +//! +//! The oscillator source is chosen with one of the following values: +//! \b SYSCTL_OSC_MAIN, \b SYSCTL_OSC_INT, or \b SYSCTL_OSC_INT4. +//! +//! The internal and main oscillators are disabled with the +//! \b SYSCTL_INT_OSC_DIS and \b SYSCTL_MAIN_OSC_DIS flags, respectively. +//! The external oscillator must be enabled in order to use an external clock +//! source. Note that attempts to disable the oscillator used to clock the +//! device will be prevented by the hardware. +//! +//! To clock the system from an external source (such as an external crystal +//! oscillator), use \b SYSCTL_USE_OSC \b | \b SYSCTL_OSC_MAIN. To clock the +//! system from the main oscillator, use \b SYSCTL_USE_OSC \b | +//! \b SYSCTL_OSC_MAIN. To clock the system from the PLL, use +//! \b SYSCTL_USE_PLL \b | \b SYSCTL_OSC_MAIN, and select the appropriate +//! crystal with one of the \b SYSCTL_XTAL_xxx values. +//! +//! \note If selecting the PLL as the system clock source (i.e. via +//! \b SYSCTL_USE_PLL), this function will poll the PLL lock interrupt to +//! determine when the PLL has locked. If an interrupt handler for the +//! system control interrupt is in place, and it responds to and clears the +//! PLL lock interrupt, this function will delay until its timeout has occurred +//! instead of completing as soon as PLL lock is achieved. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_clockset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlClockSet(unsigned long ulConfig) +{ + volatile unsigned long ulDelay; + unsigned long ulRCC; + + // + // Get the current value of the RCC register. + // + ulRCC = HWREG(SYSCTL_RCC); + + // + // Bypass the PLL and system clock dividers for now. + // + ulRCC |= SYSCTL_RCC_BYPASS; + ulRCC &= ~(SYSCTL_RCC_USE_SYSDIV); + + // + // Write the new RCC value. + // + HWREG(SYSCTL_RCC) = ulRCC; + + // + // Make sure that the PLL and system clock dividers are bypassed for now. + // + ulRCC |= SYSCTL_RCC_BYPASS; + ulRCC &= ~(SYSCTL_RCC_USE_SYSDIV); + + // + // Make sure that the required oscillators are enabled. For now, the + // previously enabled oscillators must be enabled along with the newly + // requested oscillators. + // + ulRCC &= (~(SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS) | + (ulConfig & (SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS))); + + // + // Set the new crystal value, oscillator source, and PLL configuration. + // + ulRCC &= ~(SYSCTL_RCC_XTAL_MASK | SYSCTL_RCC_OSCSRC_MASK | + SYSCTL_RCC_PWRDN | SYSCTL_RCC_OE); + ulRCC |= ulConfig & (SYSCTL_RCC_XTAL_MASK | SYSCTL_RCC_OSCSRC_MASK | + SYSCTL_RCC_PWRDN | SYSCTL_RCC_OE); + + // + // Clear the PLL lock interrupt. + // + HWREG(SYSCTL_MISC) = SYSCTL_INT_PLL_LOCK; + + // + // Write the new RCC value. + // + HWREG(SYSCTL_RCC) = ulRCC; + + // + // Wait for a bit so that new crystal value and oscillator source can take + // effect. One of the oscillators may need to be started as well. + // + for(ulDelay = 0; ulDelay < 16; ulDelay++) + { + } + + // + // Disable the appropriate oscillators. + // + ulRCC &= ~(SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS); + ulRCC |= ulConfig & (SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS); + + // + // Write the new RCC value. + // + HWREG(SYSCTL_RCC) = ulRCC; + + // + // Set the requested system divider. This will not get written + // immediately. + // + ulRCC &= ~(SYSCTL_RCC_SYSDIV_MASK | SYSCTL_RCC_USE_SYSDIV); + ulRCC |= ulConfig & (SYSCTL_RCC_SYSDIV_MASK | SYSCTL_RCC_USE_SYSDIV); + + // + // See if the PLL output is being used to clock the system. + // + if(!(ulConfig & SYSCTL_RCC_BYPASS)) + { + // + // Wait until the PLL has locked. + // + for(ulDelay = 32768; ulDelay > 0; ulDelay--) + { + if(HWREG(SYSCTL_RIS) & SYSCTL_INT_PLL_LOCK) + { + break; + } + } + + // + // Enable use of the PLL. + // + ulRCC &= ~(SYSCTL_RCC_BYPASS); + } + + // + // Write the final RCC value. + // + HWREG(SYSCTL_RCC) = ulRCC; + + // + // Delay for a little bit so that the system divider takes effect. + // + for(ulDelay = 0; ulDelay < 16; ulDelay++) + { + } +} +#endif + +//***************************************************************************** +// +//! Gets the processor clock rate. +//! +//! This function determines the clock rate of the processor clock. This is +//! also the clock rate of all the peripheral modules (with the exception of +//! PWM, which has its own clock divider). +//! +//! \note This will not return accurate results if SysCtlClockSet() has not +//! been called to configure the clocking of the device, or if the device is +//! directly clocked from a crystal (or a clock source) that is not one of the +//! supported crystal frequencies. In the later case, this function should be +//! modified to directly return the correct system clock rate. +//! +//! \return The processor clock rate. +// +//***************************************************************************** +#if defined(GROUP_clockget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +SysCtlClockGet(void) +{ + unsigned long ulRCC, ulPLL, ulClk; + + // + // Read RCC. + // + ulRCC = HWREG(SYSCTL_RCC); + + // + // Get the base clock rate. + // + switch(ulRCC & SYSCTL_RCC_OSCSRC_MASK) + { + // + // The main oscillator is the clock source. Determine its rate from + // the crystal setting field. + // + case SYSCTL_RCC_OSCSRC_MAIN: + { + ulClk = g_pulXtals[((ulRCC & SYSCTL_RCC_XTAL_MASK) >> + SYSCTL_RCC_XTAL_SHIFT) - + (SYSCTL_RCC_XTAL_3_57MHZ >> + SYSCTL_RCC_XTAL_SHIFT)]; + break; + } + + // + // The internal oscillator is the source clock. This is not an + // accurate clock (it is +/- 50%); what is used is the nominal. + // + case SYSCTL_RCC_OSCSRC_INT: + { + ulClk = 15000000; + break; + } + + // + // The internal oscillator divided by four is the source clock. This + // is not an accurate clock (it is +/- 50%); what is used is the + // nominal. + // + case SYSCTL_RCC_OSCSRC_INT4: + { + ulClk = 15000000 / 4; + break; + } + + // + // An unknown setting, so return a zero clock (i.e. an unknown clock + // rate). + // + default: + { + return(0); + } + } + + // + // See if the PLL is being used. + // + if(!(ulRCC & SYSCTL_RCC_BYPASS)) + { + // + // Get the PLL configuration. + // + ulPLL = HWREG(SYSCTL_PLLCFG); + + // + // Compute the PLL output frequency based on its input frequency. + // + ulClk = ((ulClk * (((ulPLL & SYSCTL_PLLCFG_F_MASK) >> + SYSCTL_PLLCFG_F_SHIFT) + 2)) / + (((ulPLL & SYSCTL_PLLCFG_R_MASK) >> + SYSCTL_PLLCFG_R_SHIFT) + 2)); + + // + // See if the optional output divide by 2 is being used. + // + if(ulPLL & SYSCTL_PLLCFG_OD_2) + { + ulClk /= 2; + } + + // + // See if the optional output divide by 4 is being used. + // + if(ulPLL & SYSCTL_PLLCFG_OD_4) + { + ulClk /= 4; + } + } + + // + // See if the system divider is being used. + // + if(ulRCC & SYSCTL_RCC_USE_SYSDIV) + { + // + // Adjust the clock rate by the system clock divider. + // + ulClk /= ((ulRCC & SYSCTL_RCC_SYSDIV_MASK) >> + SYSCTL_RCC_SYSDIV_SHIFT) + 1; + } + + // + // Return the computed clock rate. + // + return(ulClk); +} +#endif + +//***************************************************************************** +// +//! Sets the PWM clock configuration. +//! +//! \param ulConfig is the configuration for the PWM clock; it must be one of +//! \b SYSCTL_PWMDIV_1, \b SYSCTL_PWMDIV_2, \b SYSCTL_PWMDIV_4, +//! \b SYSCTL_PWMDIV_8, \b SYSCTL_PWMDIV_16, \b SYSCTL_PWMDIV_32, or +//! \b SYSCTL_PWMDIV_64. +//! +//! This function sets the rate of the clock provided to the PWM module as a +//! ratio of the processor clock. This clock is used by the PWM module to +//! generate PWM signals; its rate forms the basis for all PWM signals. +//! +//! \note The clocking of the PWM is dependent upon the system clock rate as +//! configured by SysCtlClockSet(). +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pwmclockset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlPWMClockSet(unsigned long ulConfig) +{ + // + // Check the arguments. + // + ASSERT((ulConfig == SYSCTL_PWMDIV_1) || + (ulConfig == SYSCTL_PWMDIV_2) || + (ulConfig == SYSCTL_PWMDIV_4) || + (ulConfig == SYSCTL_PWMDIV_8) || + (ulConfig == SYSCTL_PWMDIV_16) || + (ulConfig == SYSCTL_PWMDIV_32) || + (ulConfig == SYSCTL_PWMDIV_64)); + + // + // Check that there is a PWM block on this part. + // + ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_PWM); + + // + // Set the PWM clock configuration into the run-mode clock configuration + // register. + // + HWREG(SYSCTL_RCC) = ((HWREG(SYSCTL_RCC) & + ~(SYSCTL_RCC_USE_PWMDIV | SYSCTL_RCC_PWMDIV_MASK)) | + ulConfig); +} +#endif + +//***************************************************************************** +// +//! Gets the current PWM clock configuration. +//! +//! This function returns the current PWM clock configuration. +//! +//! \return The current PWM clock configuration; will be one of +//! \b SYSCTL_PWMDIV_1, \b SYSCTL_PWMDIV_2, \b SYSCTL_PWMDIV_4, +//! \b SYSCTL_PWMDIV_8, \b SYSCTL_PWMDIV_16, \b SYSCTL_PWMDIV_32, or +//! \b SYSCTL_PWMDIV_64. +// +//***************************************************************************** +#if defined(GROUP_pwmclockget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +SysCtlPWMClockGet(void) +{ + // + // Check that there is a PWM block on this part. + // + ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_PWM); + + // + // Return the current PWM clock configuration. + // + return(HWREG(SYSCTL_RCC) & + (SYSCTL_RCC_USE_PWMDIV | SYSCTL_RCC_PWMDIV_MASK)); +} +#endif + +//***************************************************************************** +// +//! Sets the sample rate of the ADC. +//! +//! \param ulSpeed is the desired sample rate of the ADC; must be one of +//! \b SYSCTL_ADCSPEED_1MSPS, \b SYSCTL_ADCSPEED_500KSPS, +//! \b SYSCTL_ADCSPEED_250KSPS, or \b SYSCTL_ADCSPEED_125KSPS. +//! +//! This function sets the rate at which the ADC samples are captured by the +//! ADC block. The sampling speed may be limited by the hardware, so the +//! sample rate may end up being slower than requested. SysCtlADCSpeedGet() +//! will return the actual speed in use. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_adcspeedset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlADCSpeedSet(unsigned long ulSpeed) +{ + // + // Check the arguments. + // + ASSERT((ulSpeed == SYSCTL_ADCSPEED_1MSPS) || + (ulSpeed == SYSCTL_ADCSPEED_500KSPS) || + (ulSpeed == SYSCTL_ADCSPEED_250KSPS) || + (ulSpeed == SYSCTL_ADCSPEED_125KSPS)); + + // + // Check that there is an ADC block on this part. + // + ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_ADC); + + // + // Set the ADC speed in run, sleep, and deep-sleep mode. + // + HWREG(SYSCTL_RCGC0) = ((HWREG(SYSCTL_RCGC0) & ~(SYSCTL_SET0_ADCSPD_MASK)) | + ulSpeed); + HWREG(SYSCTL_SCGC0) = ((HWREG(SYSCTL_SCGC0) & ~(SYSCTL_SET0_ADCSPD_MASK)) | + ulSpeed); + HWREG(SYSCTL_DCGC0) = ((HWREG(SYSCTL_DCGC0) & ~(SYSCTL_SET0_ADCSPD_MASK)) | + ulSpeed); +} +#endif + +//***************************************************************************** +// +//! Gets the sample rate of the ADC. +//! +//! This function gets the current sample rate of the ADC. +//! +//! \return Returns the current ADC sample rate; will be one of +//! \b SYSCTL_ADCSPEED_1MSPS, \b SYSCTL_ADCSPEED_500KSPS, +//! \b SYSCTL_ADCSPEED_250KSPS, or \b SYSCTL_ADCSPEED_125KSPS. +// +//***************************************************************************** +#if defined(GROUP_adcspeedget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +SysCtlADCSpeedGet(void) +{ + // + // Check that there is an ADC block on this part. + // + ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_ADC); + + // + // Return the current ADC speed. + // + return(HWREG(SYSCTL_RCGC0) & SYSCTL_SET0_ADCSPD_MASK); +} +#endif + +//***************************************************************************** +// +//! Configures the internal oscillator verification timer. +//! +//! \param bEnable is a boolean that is \b true if the internal oscillator +//! verification timer should be enabled. +//! +//! This function allows the internal oscillator verification timer to be +//! enabled or disabled. When enabled, an interrupt will be generated if the +//! internal oscillator ceases to operate. +//! +//! \note Both oscillators (main and internal) must be enabled for this +//! verification timer to operate as the main oscillator will verify the +//! internal oscillator. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_boscverificationset) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +SysCtlIOSCVerificationSet(tBoolean bEnable) +{ + // + // Enable or disable the internal oscillator verification timer as + // requested. + // + if(bEnable) + { + HWREG(SYSCTL_RCC) |= SYSCTL_RCC_IOSCVER; + } + else + { + HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_IOSCVER); + } +} +#endif + +//***************************************************************************** +// +//! Configures the main oscillator verification timer. +//! +//! \param bEnable is a boolean that is \b true if the main oscillator +//! verification timer should be enabled. +//! +//! This function allows the main oscillator verification timer to be enabled +//! or disabled. When enabled, an interrupt will be generated if the main +//! oscillator ceases to operate. +//! +//! \note Both oscillators (main and internal) must be enabled for this +//! verification timer to operate as the internal oscillator will verify the +//! main oscillator. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_moscverificationset) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +SysCtlMOSCVerificationSet(tBoolean bEnable) +{ + // + // Enable or disable the main oscillator verification timer as requested. + // + if(bEnable) + { + HWREG(SYSCTL_RCC) |= SYSCTL_RCC_MOSCVER; + } + else + { + HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_MOSCVER); + } +} +#endif + +//***************************************************************************** +// +//! Configures the PLL verification timer. +//! +//! \param bEnable is a boolean that is \b true if the PLL verification timer +//! should be enabled. +//! +//! This function allows the PLL verification timer to be enabled or disabled. +//! When enabled, an interrupt will be generated if the PLL ceases to operate. +//! +//! \note The main oscillator must be enabled for this verification timer to +//! operate as it is used to check the PLL. Also, the verification timer +//! should be disabled while the PLL is being reconfigured via +//! SysCtlClockSet(). +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pllverificationset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlPLLVerificationSet(tBoolean bEnable) +{ + // + // Enable or disable the PLL verification timer as requested. + // + if(bEnable) + { + HWREG(SYSCTL_RCC) |= SYSCTL_RCC_PLLVER; + } + else + { + HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_PLLVER); + } +} +#endif + +//***************************************************************************** +// +//! Clears the clock verification status. +//! +//! This function clears the status of the clock verification timers, allowing +//! them to assert another failure if detected. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_clkverificationclear) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +SysCtlClkVerificationClear(void) +{ + // + // Clear the clock verification. + // + HWREG(SYSCTL_CLKVCLR) = SYSCTL_CLKVCLR_CLR; + + // + // The bit does not self-reset, so clear it. + // + HWREG(SYSCTL_CLKVCLR) = 0; +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/sysctl.h b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/sysctl.h new file mode 100644 index 000000000..94b147084 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/sysctl.h @@ -0,0 +1,285 @@ +//***************************************************************************** +// +// sysctl.h - Prototypes for the system control driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __SYSCTL_H__ +#define __SYSCTL_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed to the +// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(), +// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the +// ulPeripheral parameter. The peripherals in the fourth group (upper nibble +// is 3) can only be used with the SysCtlPeripheralPresent() API. +// +//***************************************************************************** +#define SYSCTL_PERIPH_PWM 0x00100000 // PWM +#define SYSCTL_PERIPH_ADC 0x00010000 // ADC +#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog +#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0 +#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1 +#define SYSCTL_PERIPH_SSI 0x10000010 // SSI +#define SYSCTL_PERIPH_QEI 0x10000100 // QEI +#define SYSCTL_PERIPH_I2C 0x10001000 // I2C +#define SYSCTL_PERIPH_TIMER0 0x10010000 // Timer 0 +#define SYSCTL_PERIPH_TIMER1 0x10020000 // Timer 1 +#define SYSCTL_PERIPH_TIMER2 0x10040000 // Timer 2 +#define SYSCTL_PERIPH_COMP0 0x11000000 // Analog comparator 0 +#define SYSCTL_PERIPH_COMP1 0x12000000 // Analog comparator 1 +#define SYSCTL_PERIPH_COMP2 0x14000000 // Analog comparator 2 +#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A +#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B +#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C +#define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D +#define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E +#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex M3 MPU +#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor +#define SYSCTL_PERIPH_PLL 0x30000010 // PLL + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlPinPresent() API +// as the ulPin parameter. +// +//***************************************************************************** +#define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin +#define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin +#define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin +#define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin +#define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin +#define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin +#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin +#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin +#define SYSCTL_PIN_C0O 0x00000100 // C0o pin +#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin +#define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin +#define SYSCTL_PIN_C1O 0x00000800 // C1o pin +#define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin +#define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin +#define SYSCTL_PIN_C2O 0x00004000 // C2o pin +#define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin +#define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin +#define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin +#define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin +#define SYSCTL_PIN_ADC4 0x00100000 // ADC4 pin +#define SYSCTL_PIN_ADC5 0x00200000 // ADC5 pin +#define SYSCTL_PIN_ADC6 0x00400000 // ADC6 pin +#define SYSCTL_PIN_ADC7 0x00800000 // ADC7 pin +#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin +#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin +#define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin +#define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin +#define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin +#define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin +#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlLDOSet() API as +// the ulVoltage value, or returned by the SysCtlLDOGet() API. +// +//***************************************************************************** +#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V +#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V +#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V +#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V +#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V +#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V +#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V +#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V +#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V +#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V +#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlLDOConfigSet() API. +// +//***************************************************************************** +#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset +#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlIntEnable(), +// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask +// by the SysCtlIntStatus() API. +// +//***************************************************************************** +#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt +#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt +#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int +#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int +#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt +#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt +#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlResetCauseClear() +// API or returned by the SysCtlResetCauseGet() API. +// +//***************************************************************************** +#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset +#define SYSCTL_CAUSE_SW 0x00000010 // Software reset +#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset +#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset +#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset +#define SYSCTL_CAUSE_EXT 0x00000001 // External reset + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlBrownOutConfigSet() +// API as the ulConfig parameter. +// +//***************************************************************************** +#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting +#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlPWMClockSet() API +// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet() +// API. +// +//***************************************************************************** +#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1 +#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2 +#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4 +#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8 +#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16 +#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32 +#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64 + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlADCSpeedSet() API +// as the ulSpeed parameter, and can be returned by the SyCtlADCSpeedGet() +// API. +// +//***************************************************************************** +#define SYSCTL_ADCSPEED_1MSPS 0x00000300 // 1,000,000 samples per second +#define SYSCTL_ADCSPEED_500KSPS 0x00000200 // 500,000 samples per second +#define SYSCTL_ADCSPEED_250KSPS 0x00000100 // 250,000 samples per second +#define SYSCTL_ADCSPEED_125KSPS 0x00000000 // 125,000 samples per second + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlClockSet() API as +// the ulConfig parameter. +// +//***************************************************************************** +#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1 +#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2 +#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3 +#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4 +#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5 +#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6 +#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7 +#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8 +#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9 +#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10 +#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11 +#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12 +#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13 +#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14 +#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15 +#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16 +#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock +#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock +#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz +#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz +#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz +#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz +#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz +#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz +#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz +#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz +#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz +#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz +#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz +#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz +#define SYSCTL_OSC_MAIN 0x00000000 // Oscillator source is main osc +#define SYSCTL_OSC_INT 0x00000010 // Oscillator source is int. osc +#define SYSCTL_OSC_INT4 0x00000020 // Oscillator source is int. osc /4 +#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator +#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern unsigned long SysCtlSRAMSizeGet(void); +extern unsigned long SysCtlFlashSizeGet(void); +extern tBoolean SysCtlPinPresent(unsigned long ulPin); +extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral); +extern void SysCtlPeripheralReset(unsigned long ulPeripheral); +extern void SysCtlPeripheralEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralClockGating(tBoolean bEnable); +extern void SysCtlIntRegister(void (*pfnHandler)(void)); +extern void SysCtlIntUnregister(void); +extern void SysCtlIntEnable(unsigned long ulInts); +extern void SysCtlIntDisable(unsigned long ulInts); +extern void SysCtlIntClear(unsigned long ulInts); +extern unsigned long SysCtlIntStatus(tBoolean bMasked); +extern void SysCtlLDOSet(unsigned long ulVoltage); +extern unsigned long SysCtlLDOGet(void); +extern void SysCtlLDOConfigSet(unsigned long ulConfig); +extern void SysCtlReset(void); +extern void SysCtlSleep(void); +extern void SysCtlDeepSleep(void); +extern unsigned long SysCtlResetCauseGet(void); +extern void SysCtlResetCauseClear(unsigned long ulCauses); +extern void SysCtlBrownOutConfigSet(unsigned long ulConfig, + unsigned long ulDelay); +extern void SysCtlClockSet(unsigned long ulConfig); +extern unsigned long SysCtlClockGet(void); +extern void SysCtlPWMClockSet(unsigned long ulConfig); +extern unsigned long SysCtlPWMClockGet(void); +extern void SysCtlADCSpeedSet(unsigned long ulSpeed); +extern unsigned long SysCtlADCSpeedGet(void); +extern void SysCtlIOSCVerificationSet(tBoolean bEnable); +extern void SysCtlMOSCVerificationSet(tBoolean bEnable); +extern void SysCtlPLLVerificationSet(tBoolean bEnable); +extern void SysCtlClkVerificationClear(void); + +#ifdef __cplusplus +} +#endif + +#endif // __SYSCTL_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/systick.c b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/systick.c new file mode 100644 index 000000000..382533513 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/systick.c @@ -0,0 +1,262 @@ +//***************************************************************************** +// +// systick.c - Driver for the SysTick timer in NVIC. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup systick_api +//! @{ +// +//***************************************************************************** + +#include "../hw_ints.h" +#include "../hw_nvic.h" +#include "../hw_types.h" +#include "debug.h" +#include "interrupt.h" +#include "systick.h" + +//***************************************************************************** +// +//! Enables the SysTick counter. +//! +//! This will start the SysTick counter. If an interrupt handler has been +//! registered, it will be called when the SysTick counter rolls over. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysTickEnable(void) +{ + // + // Enable SysTick. + // + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_CLK_SRC | NVIC_ST_CTRL_ENABLE; +} +#endif + +//***************************************************************************** +// +//! Disables the SysTick counter. +//! +//! This will stop the SysTick counter. If an interrupt handler has been +//! registered, it will no longer be called until SysTick is restarted. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysTickDisable(void) +{ + // + // Disable SysTick. + // + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_ENABLE); +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for the SysTick interrupt. +//! +//! \param pfnHandler is a pointer to the function to be called when the +//! SysTick interrupt occurs. +//! +//! This sets the handler to be called when a SysTick interrupt occurs. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysTickIntRegister(void (*pfnHandler)(void)) +{ + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(FAULT_SYSTICK, pfnHandler); + + // + // Enable the SysTick interrupt. + // + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; +} +#endif + +//***************************************************************************** +// +//! Unregisters the interrupt handler for the SysTick interrupt. +//! +//! This function will clear the handler to be called when a SysTick interrupt +//! occurs. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysTickIntUnregister(void) +{ + // + // Disable the SysTick interrupt. + // + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); + + // + // Unregister the interrupt handler. + // + IntUnregister(FAULT_SYSTICK); +} +#endif + +//***************************************************************************** +// +//! Enables the SysTick interrupt. +//! +//! This function will enable the SysTick interrupt, allowing it to be +//! reflected to the processor. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysTickIntEnable(void) +{ + // + // Enable the SysTick interrupt. + // + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; +} +#endif + +//***************************************************************************** +// +//! Disables the SysTick interrupt. +//! +//! This function will disable the SysTick interrupt, preventing it from being +//! reflected to the processor. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysTickIntDisable(void) +{ + // + // Disable the SysTick interrupt. + // + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); +} +#endif + +//***************************************************************************** +// +//! Sets the period of the SysTick counter. +//! +//! \param ulPeriod is the number of clock ticks in each period of the SysTick +//! counter; must be between 1 and 16,777,216, inclusive. +//! +//! This function sets the rate at which the SysTick counter wraps; this +//! equates to the number of processor clocks between interrupts. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_periodset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysTickPeriodSet(unsigned long ulPeriod) +{ + // + // Check the arguments. + // + ASSERT((ulPeriod > 0) && (ulPeriod <= 16777216)); + + // + // Set the period of the SysTick counter. + // + HWREG(NVIC_ST_RELOAD) = ulPeriod - 1; +} +#endif + +//***************************************************************************** +// +//! Gets the period of the SysTick counter. +//! +//! This function returns the rate at which the SysTick counter wraps; this +//! equates to the number of processor clocks between interrupts. +//! +//! \return Returns the period of the SysTick counter. +// +//***************************************************************************** +#if defined(GROUP_periodget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +SysTickPeriodGet(void) +{ + // + // Return the period of the SysTick counter. + // + return(HWREG(NVIC_ST_RELOAD) + 1); +} +#endif + +//***************************************************************************** +// +//! Gets the current value of the SysTick counter. +//! +//! This function returns the current value of the SysTick counter; this will +//! be a value between the period - 1 and zero, inclusive. +//! +//! \return Returns the current value of the SysTick counter. +// +//***************************************************************************** +#if defined(GROUP_valueget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +SysTickValueGet(void) +{ + // + // Return the current value of the SysTick counter. + // + return(HWREG(NVIC_ST_CURRENT)); +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/systick.h b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/systick.h new file mode 100644 index 000000000..bfddfb16f --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/systick.h @@ -0,0 +1,55 @@ +//***************************************************************************** +// +// systick.h - Prototypes for the SysTick driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __SYSTICK_H__ +#define __SYSTICK_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void SysTickEnable(void); +extern void SysTickDisable(void); +extern void SysTickIntRegister(void (*pfnHandler)(void)); +extern void SysTickIntUnregister(void); +extern void SysTickIntEnable(void); +extern void SysTickIntDisable(void); +extern void SysTickPeriodSet(unsigned long ulPeriod); +extern unsigned long SysTickPeriodGet(void); +extern unsigned long SysTickValueGet(void); + +#ifdef __cplusplus +} +#endif + +#endif // __SYSTICK_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/timer.c b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/timer.c new file mode 100644 index 000000000..46ce19a30 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/timer.c @@ -0,0 +1,1125 @@ +//***************************************************************************** +// +// timer.c - Driver for the timer module. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup timer_api +//! @{ +// +//***************************************************************************** + +#include "../hw_ints.h" +#include "../hw_memmap.h" +#include "../hw_timer.h" +#include "../hw_types.h" +#include "debug.h" +#include "interrupt.h" +#include "timer.h" + +//***************************************************************************** +// +//! Enables the timer(s). +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to enable; must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! +//! This will enable operation of the timer module. The timer must be +//! configured before it is enabled. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerEnable(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Enable the timer(s) module. + // + HWREG(ulBase + TIMER_O_CTL) |= ulTimer & (TIMER_CTL_TAEN | TIMER_CTL_TBEN); +} +#endif + +//***************************************************************************** +// +//! Disables the timer(s). +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to disable; must be one of +//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. +//! +//! This will disable operation of the timer module. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerDisable(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Disable the timer module. + // + HWREG(ulBase + TIMER_O_CTL) &= ~(ulTimer & + (TIMER_CTL_TAEN | TIMER_CTL_TBEN)); +} +#endif + +//***************************************************************************** +// +//! Configures the timer(s). +//! +//! \param ulBase is the base address of the timer module. +//! \param ulConfig is the configuration for the timer. +//! +//! This function configures the operating mode of the timer(s). The timer +//! module is disabled before being configured, and is left in the disabled +//! state. The configuration is specified in \e ulConfig as one of the +//! following values: +//! +//! - \b TIMER_CFG_32_BIT_OS - 32-bit one shot timer +//! - \b TIMER_CFG_32_BIT_PER - 32-bit periodic timer +//! - \b TIMER_CFG_32_RTC - 32-bit real time clock timer +//! - \b TIMER_CFG_16_BIT_PAIR - Two 16-bit timers +//! +//! When configured for a pair of 16-bit timers, each timer is separately +//! configured. The first timer is configured by setting \e ulConfig to +//! the result of a logical OR operation between one of the following values +//! and \e ulConfig: +//! +//! - \b TIMER_CFG_A_ONE_SHOT - 16-bit one shot timer +//! - \b TIMER_CFG_A_PERIODIC - 16-bit periodic timer +//! - \b TIMER_CFG_A_CAP_COUNT - 16-bit edge count capture +//! - \b TIMER_CFG_A_CAP_TIME - 16-bit edge time capture +//! - \b TIMER_CFG_A_PWM - 16-bit PWM output +//! +//! Similarly, the second timer is configured by setting \e ulConfig to +//! the result of a logical OR operation between one of the corresponding +//! \b TIMER_CFG_B_* values and \e ulConfig. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_configure) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerConfigure(unsigned long ulBase, unsigned long ulConfig) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulConfig == TIMER_CFG_32_BIT_OS) || + (ulConfig == TIMER_CFG_32_BIT_PER) || + (ulConfig == TIMER_CFG_32_RTC) || + ((ulConfig & 0xff000000) == TIMER_CFG_16_BIT_PAIR)); + ASSERT(((ulConfig & 0xff000000) != TIMER_CFG_16_BIT_PAIR) || + ((((ulConfig & 0x000000ff) == TIMER_CFG_A_ONE_SHOT) || + ((ulConfig & 0x000000ff) == TIMER_CFG_A_PERIODIC) || + ((ulConfig & 0x000000ff) == TIMER_CFG_A_CAP_COUNT) || + ((ulConfig & 0x000000ff) == TIMER_CFG_A_CAP_TIME) || + ((ulConfig & 0x000000ff) == TIMER_CFG_A_PWM)) && + (((ulConfig & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT) || + ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PERIODIC) || + ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_COUNT) || + ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_TIME) || + ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PWM)))); + + // + // Disable the timers. + // + HWREG(ulBase + TIMER_O_CTL) &= ~(TIMER_CTL_TAEN | TIMER_CTL_TBEN); + + // + // Set the global timer configuration. + // + HWREG(ulBase + TIMER_O_CFG) = ulConfig >> 24; + + // + // Set the configuration of the A and B timers. Note that the B timer + // configuration is ignored by the hardware in 32-bit modes. + // + HWREG(ulBase + TIMER_O_TAMR) = ulConfig & 255; + HWREG(ulBase + TIMER_O_TBMR) = (ulConfig >> 8) & 255; +} +#endif + +//***************************************************************************** +// +//! Controls the output level. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! \param bInvert specifies the output level. +//! +//! This function sets the PWM output level for the specified timer. If the +//! parameter \e bInvert is \b true, then the timer's output will be made +//! active low; otherwise, it will be made active high. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_controllevel) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, + tBoolean bInvert) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Set the output levels as requested. + // + ulTimer &= TIMER_CTL_TAPWML | TIMER_CTL_TBPWML; + HWREG(ulBase + TIMER_O_CTL) = (bInvert ? + (HWREG(ulBase + TIMER_O_CTL) | ulTimer) : + (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer))); +} +#endif + +//***************************************************************************** +// +//! Enables or disables the trigger output. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer to adjust; must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! \param bEnable specifies the desired trigger state. +//! +//! This function controls the trigger output for the specified timer. If the +//! parameter \e bEnable is \b true, then the timer's output trigger is +//! enabled; otherwise it is disabled. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_controltrigger) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer, + tBoolean bEnable) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Set the trigger output as requested. + // + ulTimer &= TIMER_CTL_TAOTE | TIMER_CTL_TBOTE; + HWREG(ulBase + TIMER_O_CTL) = (bEnable ? + (HWREG(ulBase + TIMER_O_CTL) | ulTimer) : + (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer))); +} +#endif + +//***************************************************************************** +// +//! Controls the event type. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to be adjusted; must be one of +//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. +//! \param ulEvent specifies the type of event; must be one of +//! \b TIMER_EVENT_POS_EDGE, \b TIMER_EVENT_NEG_EDGE, or +//! \b TIMER_EVENT_BOTH_EDGES. +//! +//! This function sets the signal edge(s) that will trigger the timer when in +//! capture mode. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_controlevent) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulEvent) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Set the event type. + // + ulEvent &= ulTimer & (TIMER_CTL_TAEVENT_MSK | TIMER_CTL_TBEVENT_MSK); + HWREG(ulBase + TIMER_O_CTL) = ((HWREG(ulBase + TIMER_O_CTL) & + ~(TIMER_CTL_TAEVENT_MSK | + TIMER_CTL_TBEVENT_MSK)) | ulEvent); +} +#endif + +//***************************************************************************** +// +//! Controls the stall handling. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to be adjusted; must be one of +//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. +//! \param bStall specifies the response to a stall signal. +//! +//! This function controls the stall response for the specified timer. If the +//! parameter \e bStall is \b true, then the timer will stop counting if the +//! processor enters debug mode; otherwise the timer will keep running while in +//! debug mode. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_controlstall) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerControlStall(unsigned long ulBase, unsigned long ulTimer, + tBoolean bStall) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Set the stall mode. + // + ulTimer &= TIMER_CTL_TASTALL | TIMER_CTL_TBSTALL; + HWREG(ulBase + TIMER_O_CTL) = (bStall ? + (HWREG(ulBase + TIMER_O_CTL) | ulTimer) : + (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer))); +} +#endif + +//***************************************************************************** +// +//! Enable RTC counting. +//! +//! \param ulBase is the base address of the timer module. +//! +//! This function causes the timer to start counting when in RTC mode. If not +//! configured for RTC mode, this will do nothing. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_rtcenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerRTCEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + + // + // Enable RTC counting. + // + HWREG(ulBase + TIMER_O_CTL) |= TIMER_CTL_RTCEN; +} +#endif + +//***************************************************************************** +// +//! Disable RTC counting. +//! +//! \param ulBase is the base address of the timer module. +//! +//! This function causes the timer to stop counting when in RTC mode. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_rtcdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerRTCDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + + // + // Disable RTC counting. + // + HWREG(ulBase + TIMER_O_CTL) &= ~(TIMER_CTL_RTCEN); +} +#endif + +//***************************************************************************** +// +//! Set the timer prescale value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! \param ulValue is the timer prescale value; must be between 0 and 255, +//! inclusive. +//! +//! This function sets the value of the input clock prescaler. The prescaler +//! is only operational when in 16-bit mode and is used to extend the range of +//! the 16-bit timer modes. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_prescaleset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + ASSERT(ulValue < 256); + + // + // Set the timer A prescaler if requested. + // + if(ulTimer & TIMER_A) + { + HWREG(ulBase + TIMER_O_TAPR) = ulValue; + } + + // + // Set the timer B prescaler if requested. + // + if(ulTimer & TIMER_B) + { + HWREG(ulBase + TIMER_O_TBPR) = ulValue; + } +} +#endif + +//***************************************************************************** +// +//! Get the timer prescale value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer; must be one of \b TIMER_A or +//! \b TIMER_B. +//! +//! This function gets the value of the input clock prescaler. The prescaler +//! is only operational when in 16-bit mode and is used to extend the range of +//! the 16-bit timer modes. +//! +//! \return The value of the timer prescaler. +// +//***************************************************************************** +#if defined(GROUP_prescaleget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +TimerPrescaleGet(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Return the appropriate prescale value. + // + return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAPR) : + HWREG(ulBase + TIMER_O_TBPR)); +} +#endif + +//***************************************************************************** +// +//! Set the timer prescale match value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! \param ulValue is the timer prescale match value; must be between 0 and +//! 255, inclusive. +//! +//! This function sets the value of the input clock prescaler match value. +//! When in a 16-bit mode that uses the counter match (edge count or PWM), the +//! prescale match effectively extends the range of the counter to 24-bits. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_prescalematchset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + ASSERT(ulValue < 256); + + // + // Set the timer A prescale match if requested. + // + if(ulTimer & TIMER_A) + { + HWREG(ulBase + TIMER_O_TAPMR) = ulValue; + } + + // + // Set the timer B prescale match if requested. + // + if(ulTimer & TIMER_B) + { + HWREG(ulBase + TIMER_O_TBPMR) = ulValue; + } +} +#endif + +//***************************************************************************** +// +//! Get the timer prescale match value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer; must be one of \b TIMER_A or +//! \b TIMER_B. +//! +//! This function gets the value of the input clock prescaler match value. +//! When in a 16-bit mode that uses the counter match (edge count or PWM), the +//! prescale match effectively extends the range of the counter to 24-bits. +//! +//! \return The value of the timer prescale match. +// +//***************************************************************************** +#if defined(GROUP_prescalematchget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +TimerPrescaleMatchGet(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Return the appropriate prescale match value. + // + return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAPMR) : + HWREG(ulBase + TIMER_O_TBPMR)); +} +#endif + +//***************************************************************************** +// +//! Sets the timer load value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. Only \b TIMER_A should be used when the +//! timer is configured for 32-bit operation. +//! \param ulValue is the load value. +//! +//! This function sets the timer load value; if the timer is running then the +//! value will be immediately loaded into the timer. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_loadset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Set the timer A load value if requested. + // + if(ulTimer & TIMER_A) + { + HWREG(ulBase + TIMER_O_TAILR) = ulValue; + } + + // + // Set the timer B load value if requested. + // + if(ulTimer & TIMER_B) + { + HWREG(ulBase + TIMER_O_TBILR) = ulValue; + } +} +#endif + +//***************************************************************************** +// +//! Gets the timer load value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer; must be one of \b TIMER_A or +//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured +//! for 32-bit operation. +//! +//! This function gets the currently programmed interval load value for the +//! specified timer. +//! +//! \return Returns the load value for the timer. +// +//***************************************************************************** +#if defined(GROUP_loadget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +TimerLoadGet(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B)); + + // + // Return the appropriate load value. + // + return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAILR) : + HWREG(ulBase + TIMER_O_TBILR)); +} +#endif + +//***************************************************************************** +// +//! Gets the current timer value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer; must be one of \b TIMER_A or +//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured +//! for 32-bit operation. +//! +//! This function reads the current value of the specified timer. +//! +//! \return Returns the current value of the timer. +// +//***************************************************************************** +#if defined(GROUP_valueget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +TimerValueGet(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B)); + + // + // Return the appropriate timer value. + // + return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAR) : + HWREG(ulBase + TIMER_O_TBR)); +} +#endif + +//***************************************************************************** +// +//! Sets the timer match value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. Only \b TIMER_A should be used when the +//! timer is configured for 32-bit operation. +//! \param ulValue is the match value. +//! +//! This function sets the match value for a timer. This is used in capture +//! count mode to determine when to interrupt the processor and in PWM mode to +//! determine the duty cycle of the output signal. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_matchset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Set the timer A match value if requested. + // + if(ulTimer & TIMER_A) + { + HWREG(ulBase + TIMER_O_TAMATCHR) = ulValue; + } + + // + // Set the timer B match value if requested. + // + if(ulTimer & TIMER_B) + { + HWREG(ulBase + TIMER_O_TBMATCHR) = ulValue; + } +} +#endif + +//***************************************************************************** +// +//! Gets the timer match value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer; must be one of \b TIMER_A or +//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured +//! for 32-bit operation. +//! +//! This function gets the match value for the specified timer. +//! +//! \return Returns the match value for the timer. +// +//***************************************************************************** +#if defined(GROUP_matchget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +TimerMatchGet(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B)); + + // + // Return the appropriate match value. + // + return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAMATCHR) : + HWREG(ulBase + TIMER_O_TBMATCHR)); +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for the timer interrupt. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s); must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! \param pfnHandler is a pointer to the function to be called when the timer +//! interrupt occurs. +//! +//! This sets the handler to be called when a timer interrupt occurs. This +//! will enable the global interrupt in the interrupt controller; specific +//! timer interrupts must be enabled via TimerIntEnable(). It is the interrupt +//! handler's responsibility to clear the interrupt source via TimerIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, + void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Get the interrupt number for this timer module. + // + ulBase = ((ulBase == TIMER0_BASE) ? INT_TIMER0A : + ((ulBase == TIMER1_BASE) ? INT_TIMER1A : INT_TIMER2A)); + + // + // Register an interrupt handler for timer A if requested. + // + if(ulTimer & TIMER_A) + { + // + // Register the interrupt handler. + // + IntRegister(ulBase, pfnHandler); + + // + // Enable the interrupt. + // + IntEnable(ulBase); + } + + // + // Register an interrupt handler for timer B if requested. + // + if(ulTimer & TIMER_B) + { + // + // Register the interrupt handler. + // + IntRegister(ulBase + 1, pfnHandler); + + // + // Enable the interrupt. + // + IntEnable(ulBase + 1); + } +} +#endif + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the timer interrupt. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s); must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! +//! This function will clear the handler to be called when a timer interrupt +//! occurs. This will also mask off the interrupt in the interrupt controller +//! so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Get the interrupt number for this timer module. + // + ulBase = ((ulBase == TIMER0_BASE) ? INT_TIMER0A : + ((ulBase == TIMER1_BASE) ? INT_TIMER1A : INT_TIMER2A)); + + // + // Unregister the interrupt handler for timer A if requested. + // + if(ulTimer & TIMER_A) + { + // + // Disable the interrupt. + // + IntDisable(ulBase); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulBase); + } + + // + // Unregister the interrupt handler for timer B if requested. + // + if(ulTimer & TIMER_B) + { + // + // Disable the interrupt. + // + IntDisable(ulBase + 1); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulBase + 1); + } +} +#endif + +//***************************************************************************** +// +//! Enables individual timer interrupt sources. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! Enables the indicated timer interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! The parameter \e ulIntFlags must be the logical OR of any combination of +//! the following: +//! +//! - TIMER_CAPB_EVENT - Capture B event interrupt +//! - TIMER_CAPB_MATCH - Capture B match interrupt +//! - TIMER_TIMB_TIMEOUT - Timer B timeout interrupt +//! - TIMER_RTC_MATCH - RTC interrupt mask +//! - TIMER_CAPA_EVENT - Capture A event interrupt +//! - TIMER_CAPA_MATCH - Capture A match interrupt +//! - TIMER_TIMA_TIMEOUT - Timer A timeout interrupt +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + + // + // Enable the specified interrupts. + // + HWREG(ulBase + TIMER_O_IMR) |= ulIntFlags; +} +#endif + +//***************************************************************************** +// +//! Disables individual timer interrupt sources. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. +//! +//! Disables the indicated timer interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! The parameter \e ulIntFlags has the same definition as the \e ulIntFlags +//! parameter to TimerIntEnable(). +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + + // + // Disable the specified interrupts. + // + HWREG(ulBase + TIMER_O_IMR) &= ~(ulIntFlags); +} +#endif + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ulBase is the base address of the timer module. +//! \param bMasked is false if the raw interrupt status is required and true if +//! the masked interrupt status is required. +//! +//! This returns the interrupt status for the timer module. Either the raw +//! interrupt status or the status of interrupts that are allowed to reflect to +//! the processor can be returned. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! values described in TimerIntEnable(). +// +//***************************************************************************** +#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +TimerIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + return(bMasked ? HWREG(ulBase + TIMER_O_MIS) : + HWREG(ulBase + TIMER_O_RIS)); +} +#endif + +//***************************************************************************** +// +//! Clears timer interrupt sources. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! The specified timer interrupt sources are cleared, so that they no longer +//! assert. This must be done in the interrupt handler to keep it from being +//! called again immediately upon exit. +//! +//! The parameter \e ulIntFlags has the same definition as the \e ulIntFlags +//! parameter to TimerIntEnable(). +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + + // + // Clear the requested interrupt sources. + // + HWREG(ulBase + TIMER_O_ICR) = ulIntFlags; +} +#endif + +//***************************************************************************** +// +//! Puts the timer into its reset state. +//! +//! \param ulBase is the base address of the timer module. +//! +//! The specified timer is disabled, and all its interrupts are disabled, +//! cleared, and unregistered. Then the timer registers are set to their reset +//! value. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_quiesce) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerQuiesce(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + + // + // Disable the timer. + // + HWREG(ulBase + TIMER_O_CTL) = TIMER_RV_CTL; + + // + // Disable all the timer interrupts. + // + HWREG(ulBase + TIMER_O_IMR) = TIMER_RV_IMR; + + // + // Clear all the timer interrupts. + // + HWREG(ulBase + TIMER_O_ICR) = 0xFFFFFFFF; + + // + // Unregister the interrupt handler. This also disables interrupts to the + // core. + // + TimerIntUnregister(ulBase, TIMER_BOTH); + + // + // Set all the registers to their reset value. + // + HWREG(ulBase + TIMER_O_CFG) = TIMER_RV_CFG; + HWREG(ulBase + TIMER_O_TAMR) = TIMER_RV_TAMR; + HWREG(ulBase + TIMER_O_TBMR) = TIMER_RV_TBMR; + HWREG(ulBase + TIMER_O_RIS) = TIMER_RV_RIS; + HWREG(ulBase + TIMER_O_MIS) = TIMER_RV_MIS; + HWREG(ulBase + TIMER_O_TAILR) = TIMER_RV_TAILR; + HWREG(ulBase + TIMER_O_TBILR) = TIMER_RV_TBILR; + HWREG(ulBase + TIMER_O_TAMATCHR) = TIMER_RV_TAMATCHR; + HWREG(ulBase + TIMER_O_TBMATCHR) = TIMER_RV_TBMATCHR; + HWREG(ulBase + TIMER_O_TAPR) = TIMER_RV_TAPR; + HWREG(ulBase + TIMER_O_TBPR) = TIMER_RV_TBPR; + HWREG(ulBase + TIMER_O_TAPMR) = TIMER_RV_TAPMR; + HWREG(ulBase + TIMER_O_TBPMR) = TIMER_RV_TBPMR; + HWREG(ulBase + TIMER_O_TAR) = TIMER_RV_TAR; + HWREG(ulBase + TIMER_O_TBR) = TIMER_RV_TBR; +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/timer.h b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/timer.h new file mode 100644 index 000000000..660c325f4 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/timer.h @@ -0,0 +1,137 @@ +//***************************************************************************** +// +// timer.h - Prototypes for the timer module +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __TIMER_H__ +#define __TIMER_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to TimerConfigure as the ulConfig parameter. +// +//***************************************************************************** +#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer +#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer +#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer +#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers +#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer +#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer +#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter +#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer +#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output +#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer +#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer +#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter +#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer +#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output + +//***************************************************************************** +// +// Values that can be passed to TimerIntEnable, TimerIntDisable, and +// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus. +// +//***************************************************************************** +#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt +#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt +#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt +#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask +#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt +#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt +#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt + +//***************************************************************************** +// +// Values that can be passed to TimerControlEvent as the ulEvent parameter. +// +//***************************************************************************** +#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges +#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges +#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges + +//***************************************************************************** +// +// Values that can be passed to most of the timer APIs as the ulTimer +// parameter. +// +//***************************************************************************** +#define TIMER_A 0x000000ff // Timer A +#define TIMER_B 0x0000ff00 // Timer B +#define TIMER_BOTH 0x0000ffff // Timer Both + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer); +extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer); +extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig); +extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, + tBoolean bInvert); +extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer, + tBoolean bEnable); +extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulEvent); +extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer, + tBoolean bStall); +extern void TimerRTCEnable(unsigned long ulBase); +extern void TimerRTCDisable(unsigned long ulBase); +extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerPrescaleGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer); +extern unsigned long TimerValueGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerMatchGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, + void (*pfnHandler)(void)); +extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer); +extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void TimerQuiesce(unsigned long ulBase); + +#ifdef __cplusplus +} +#endif + +#endif // __TIMER_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/uart.c b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/uart.c new file mode 100644 index 000000000..cbae1b0ca --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/uart.c @@ -0,0 +1,821 @@ +//***************************************************************************** +// +// uart.c - Driver for the UART. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup uart_api +//! @{ +// +//***************************************************************************** + +#include "../hw_ints.h" +#include "../hw_memmap.h" +#include "../hw_types.h" +#include "../hw_uart.h" +#include "debug.h" +#include "interrupt.h" +#include "sysctl.h" +#include "uart.h" + +//***************************************************************************** +// +//! Sets the type of parity. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulParity specifies the type of parity to use. +//! +//! Sets the type of parity to use for transmitting and expect when receiving. +//! The \e ulParity parameter must be one of \b UART_CONFIG_PAR_NONE, +//! \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE, +//! or \b UART_CONFIG_PAR_ZERO. The last two allow direct control of the +//! parity bit; it will always be either be one or zero based on the mode. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_paritymodeset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +UARTParityModeSet(unsigned long ulBase, unsigned long ulParity) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + ASSERT((ulParity == UART_CONFIG_PAR_NONE) || + (ulParity == UART_CONFIG_PAR_EVEN) || + (ulParity == UART_CONFIG_PAR_ODD) || + (ulParity == UART_CONFIG_PAR_ONE) || + (ulParity == UART_CONFIG_PAR_ZERO)); + + // + // Set the parity mode. + // + HWREG(ulBase + UART_O_LCR_H) = ((HWREG(ulBase + UART_O_LCR_H) & + ~(UART_LCR_H_SPS | UART_LCR_H_EPS | + UART_LCR_H_PEN)) | ulParity); +} +#endif + +//***************************************************************************** +// +//! Gets the type of parity currently being used. +//! +//! \param ulBase is the base address of the UART port. +//! +//! \return The current parity settings, specified as one of +//! \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, +//! \b UART_CONFIG_PAR_ONE, or \b UART_CONFIG_PAR_ZERO. +// +//***************************************************************************** +#if defined(GROUP_paritymodeget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +UARTParityModeGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Return the current parity setting. + // + return(HWREG(ulBase + UART_O_LCR_H) & + (UART_LCR_H_SPS | UART_LCR_H_EPS | UART_LCR_H_PEN)); +} +#endif + +//***************************************************************************** +// +//! Sets the configuration of a UART. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulBaud is the desired baud rate. +//! \param ulConfig is the data format for the port (number of data bits, +//! number of stop bits, and parity). +//! +//! This function will configure the UART for operation in the specified data +//! format. The baud rate is provided in the \e ulBaud parameter and the +//! data format in the \e ulConfig parameter. +//! +//! The \e ulConfig parameter is the logical OR of three values: the number of +//! data bits, the number of stop bits, and the parity. \b UART_CONFIG_WLEN_8, +//! \b UART_CONFIG_WLEN_7, \b UART_CONFIG_WLEN_6, and \b UART_CONFIG_WLEN_5 +//! select from eight to five data bits per byte (respectively). +//! \b UART_CONFIG_STOP_ONE and \b UART_CONFIG_STOP_TWO select one or two stop +//! bits (respectively). \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, +//! \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE, and \b UART_CONFIG_PAR_ZERO +//! select the parity mode (no parity bit, even parity bit, odd parity bit, +//! parity bit always one, and parity bit always zero, respectively). +//! +//! The baud rate is dependent upon the system clock rate returned by +//! SysCtlClockGet(); if it does not return the correct system clock rate then +//! the baud rate will be incorrect. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_configset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +UARTConfigSet(unsigned long ulBase, unsigned long ulBaud, + unsigned long ulConfig) +{ + unsigned long ulUARTClk, ulInt, ulFrac; + + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Stop the UART. + // + UARTDisable(ulBase); + + // + // Determine the UART clock rate. + // + ulUARTClk = SysCtlClockGet(); + + // + // Compute the fractional baud rate divider. + // + ulInt = ulUARTClk / (16 * ulBaud); + ulFrac = ulUARTClk % (16 * ulBaud); + ulFrac = ((((2 * ulFrac * 4) / ulBaud) + 1) / 2); + + // + // Set the baud rate. + // + HWREG(ulBase + UART_O_IBRD) = ulInt; + HWREG(ulBase + UART_O_FBRD) = ulFrac; + + // + // Set parity, data length, and number of stop bits. + // + HWREG(ulBase + UART_O_LCR_H) = ulConfig; + + // + // Clear the flags register. + // + HWREG(ulBase + UART_O_FR) = 0; + + // + // Start the UART. + // + UARTEnable(ulBase); +} +#endif + +//***************************************************************************** +// +//! Gets the current configuration of a UART. +//! +//! \param ulBase is the base address of the UART port. +//! \param pulBaud is a pointer to storage for the baud rate. +//! \param pulConfig is a pointer to storage for the data format. +//! +//! The baud rate and data format for the UART is determined. The returned +//! baud rate is the actual baud rate; it may not be the exact baud rate +//! requested or an ``official'' baud rate. The data format returned in +//! \e pulConfig is enumerated the same as the \e ulConfig parameter of +//! UARTConfigSet(). +//! +//! The baud rate is dependent upon the system clock rate returned by +//! SysCtlClockGet(); if it does not return the correct system clock rate then +//! the baud rate will be computed incorrectly. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_configget) || defined(BUILD_ALL) || defined(DOXYGEN) +void +UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud, + unsigned long *pulConfig) + +{ + unsigned long ulInt, ulFrac; + + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Compute the baud rate. + // + ulInt = HWREG(ulBase + UART_O_IBRD); + ulFrac = HWREG(ulBase + UART_O_FBRD); + *pulBaud = (SysCtlClockGet() * 4) / ((64 * ulInt) + ulFrac); + + // + // Get the parity, data length, and number of stop bits. + // + *pulConfig = (HWREG(ulBase + UART_O_LCR_H) & + (UART_LCR_H_SPS | UART_LCR_H_WLEN | UART_LCR_H_STP2 | + UART_LCR_H_EPS | UART_LCR_H_PEN)); +} +#endif + +//***************************************************************************** +// +//! Enables transmitting and receiving. +//! +//! \param ulBase is the base address of the UART port. +//! +//! Sets the UARTEN, TXE, and RXE bits, and enables the transmit and receive +//! FIFOs. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +UARTEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Enable the FIFO. + // + HWREG(ulBase + UART_O_LCR_H) |= UART_LCR_H_FEN; + + // + // Enable RX, TX, and the UART. + // + HWREG(ulBase + UART_O_CTL) |= (UART_CTL_UARTEN | UART_CTL_TXE | + UART_CTL_RXE); +} +#endif + +//***************************************************************************** +// +//! Disables transmitting and receiving. +//! +//! \param ulBase is the base address of the UART port. +//! +//! Clears the UARTEN, TXE, and RXE bits, then waits for the end of +//! transmission of the current character, and flushes the transmit FIFO. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +UARTDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Wait for end of TX. + // + while(HWREG(ulBase + UART_O_FR) & UART_FR_BUSY) + { + } + + // + // Disable the FIFO. + // + HWREG(ulBase + UART_O_LCR_H) &= ~(UART_LCR_H_FEN); + + // + // Disable the UART. + // + HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_UARTEN | UART_CTL_TXE | + UART_CTL_RXE); +} +#endif + +//***************************************************************************** +// +//! Determines if there are any characters in the receive FIFO. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function returns a flag indicating whether or not there is data +//! available in the receive FIFO. +//! +//! \return Returns \b true if there is data in the receive FIFO, and \b false +//! if there is no data in the receive FIFO. +// +//***************************************************************************** +#if defined(GROUP_charsavail) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +UARTCharsAvail(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Return the availability of characters. + // + return((HWREG(ulBase + UART_O_FR) & UART_FR_RXFE) ? false : true); +} +#endif + +//***************************************************************************** +// +//! Determines if there is any space in the transmit FIFO. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function returns a flag indicating whether or not there is space +//! available in the transmit FIFO. +//! +//! \return Returns \b true if there is space available in the transmit FIFO, +//! and \b false if there is no space available in the transmit FIFO. +// +//***************************************************************************** +#if defined(GROUP_spaceavail) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +UARTSpaceAvail(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Return the availability of space. + // + return((HWREG(ulBase + UART_O_FR) & UART_FR_TXFF) ? false : true); +} +#endif + +//***************************************************************************** +// +//! Receives a character from the specified port. +//! +//! \param ulBase is the base address of the UART port. +//! +//! Gets a character from the receive FIFO for the specified port. +//! +//! \return Returns the character read from the specified port, cast as a +//! \e long. A \b -1 will be returned if there are no characters present in +//! the receive FIFO. The UARTCharsAvail() function should be called before +//! attempting to call this function. +// +//***************************************************************************** +#if defined(GROUP_charnonblockingget) || defined(BUILD_ALL) || defined(DOXYGEN) +long +UARTCharNonBlockingGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // See if there are any characters in the receive FIFO. + // + if(!(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE)) + { + // + // Read and return the next character. + // + return(HWREG(ulBase + UART_O_DR)); + } + else + { + // + // There are no characters, so return a failure. + // + return(-1); + } +} +#endif + +//***************************************************************************** +// +//! Waits for a character from the specified port. +//! +//! \param ulBase is the base address of the UART port. +//! +//! Gets a character from the receive FIFO for the specified port. If there +//! are no characters available, this function will wait until a character is +//! received before returning. +//! +//! \return Returns the character read from the specified port, cast as an +//! \e int. +// +//***************************************************************************** +#if defined(GROUP_charget) || defined(BUILD_ALL) || defined(DOXYGEN) +long +UARTCharGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Wait until a char is available. + // + while(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE) + { + } + + // + // Now get the char. + // + return(HWREG(ulBase + UART_O_DR)); +} +#endif + +//***************************************************************************** +// +//! Sends a character to the specified port. +//! +//! \param ulBase is the base address of the UART port. +//! \param ucData is the character to be transmitted. +//! +//! Writes the character \e ucData to the transmit FIFO for the specified port. +//! This function does not block, so if there is no space available, then a +//! \b false is returned, and the application will have to retry the function +//! later. +//! +//! \return Returns \b true if the character was successfully placed in the +//! transmit FIFO, and \b false if there was no space available in the transmit +//! FIFO. +// +//***************************************************************************** +#if defined(GROUP_charnonblockingput) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +UARTCharNonBlockingPut(unsigned long ulBase, unsigned char ucData) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // See if there is space in the transmit FIFO. + // + if(!(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF)) + { + // + // Write this character to the transmit FIFO. + // + HWREG(ulBase + UART_O_DR) = ucData; + + // + // Success. + // + return(true); + } + else + { + // + // There is no space in the transmit FIFO, so return a failure. + // + return(false); + } +} +#endif + +//***************************************************************************** +// +//! Waits to send a character from the specified port. +//! +//! \param ulBase is the base address of the UART port. +//! \param ucData is the character to be transmitted. +//! +//! Sends the character \e ucData to the transmit FIFO for the specified port. +//! If there is no space available in the transmit FIFO, this function will +//! wait until there is space available before returning. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_charput) || defined(BUILD_ALL) || defined(DOXYGEN) +void +UARTCharPut(unsigned long ulBase, unsigned char ucData) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Wait until space is available. + // + while(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF) + { + } + + // + // Send the char. + // + HWREG(ulBase + UART_O_DR) = ucData; +} +#endif + +//***************************************************************************** +// +//! Causes a BREAK to be sent. +//! +//! \param ulBase is the base address of the UART port. +//! \param bBreakState controls the output level. +//! +//! Calling this function with \e bBreakState set to \b true will assert a +//! break condition on the UART. Calling this function with \e bBreakState set +//! to \b false will remove the break condition. For proper transmission of a +//! break command, the break must be asserted for at least two complete frames. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_breakctl) || defined(BUILD_ALL) || defined(DOXYGEN) +void +UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Set the break condition as requested. + // + HWREG(ulBase + UART_O_LCR_H) = + (bBreakState ? + (HWREG(ulBase + UART_O_LCR_H) | UART_LCR_H_BRK) : + (HWREG(ulBase + UART_O_LCR_H) & ~(UART_LCR_H_BRK))); +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for a UART interrupt. +//! +//! \param ulBase is the base address of the UART port. +//! \param pfnHandler is a pointer to the function to be called when the +//! UART interrupt occurs. +//! +//! This function does the actual registering of the interrupt handler. This +//! will enable the global interrupt in the interrupt controller; specific UART +//! interrupts must be enabled via UARTIntEnable(). It is the interrupt +//! handler's responsibility to clear the interrupt source. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +UARTIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Determine the interrupt number based on the UART port. + // + ulInt = (ulBase == UART0_BASE) ? INT_UART0 : INT_UART1; + + // + // Register the interrupt handler. + // + IntRegister(ulInt, pfnHandler); + + // + // Enable the UART interrupt. + // + IntEnable(ulInt); +} +#endif + +//***************************************************************************** +// +//! Unregisters an interrupt handler for a UART interrupt. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function does the actual unregistering of the interrupt handler. It +//! will clear the handler to be called when a UART interrupt occurs. This +//! will also mask off the interrupt in the interrupt controller so that the +//! interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +UARTIntUnregister(unsigned long ulBase) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Determine the interrupt number based on the UART port. + // + ulInt = (ulBase == UART0_BASE) ? INT_UART0 : INT_UART1; + + // + // Disable the interrupt. + // + IntDisable(ulInt); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulInt); +} +#endif + +//***************************************************************************** +// +//! Enables individual UART interrupt sources. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! Enables the indicated UART interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! The parameter \e ulIntFlags is the logical OR of any of the following: +//! +//! - UART_INT_OE - Overrun Error interrupt +//! - UART_INT_BE - Break Error interrupt +//! - UART_INT_PE - Parity Error interrupt +//! - UART_INT_FE - Framing Error interrupt +//! - UART_INT_RT - Receive Timeout interrupt +//! - UART_INT_TX - Transmit interrupt +//! - UART_INT_RX - Receive interrupt +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Enable the specified interrupts. + // + HWREG(ulBase + UART_O_IM) |= ulIntFlags; +} +#endif + +//***************************************************************************** +// +//! Disables individual UART interrupt sources. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. +//! +//! Disables the indicated UART interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! The parameter \e ulIntFlags has the same definition as the same parameter +//! to UARTIntEnable(). +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Disable the specified interrupts. + // + HWREG(ulBase + UART_O_IM) &= ~(ulIntFlags); +} +#endif + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ulBase is the base address of the UART port. +//! \param bMasked is false if the raw interrupt status is required and true +//! if the masked interrupt status is required. +//! +//! This returns the interrupt status for the specified UART. Either the raw +//! interrupt status or the status of interrupts that are allowed to reflect to +//! the processor can be returned. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! values described in UARTIntEnable(). +// +//***************************************************************************** +#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +UARTIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ulBase + UART_O_MIS)); + } + else + { + return(HWREG(ulBase + UART_O_RIS)); + } +} +#endif + +//***************************************************************************** +// +//! Clears UART interrupt sources. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! The specified UART interrupt sources are cleared, so that they no longer +//! assert. This must be done in the interrupt handler to keep it from being +//! called again immediately upon exit. +//! +//! The parameter \e ulIntFlags has the same definition as the same parameter +//! to UARTIntEnable(). +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Clear the requested interrupt sources. + // + HWREG(ulBase + UART_O_ICR) = ulIntFlags; +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/uart.h b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/uart.h new file mode 100644 index 000000000..b82f2eec5 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/uart.h @@ -0,0 +1,102 @@ +//***************************************************************************** +// +// uart.h - Defines and Macros for the UART. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __UART_H__ +#define __UART_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear +// as the ulIntFlags parameter, and returned from UARTIntStatus. +// +//***************************************************************************** +#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask +#define UART_INT_BE 0x200 // Break Error Interrupt Mask +#define UART_INT_PE 0x100 // Parity Error Interrupt Mask +#define UART_INT_FE 0x080 // Framing Error Interrupt Mask +#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask +#define UART_INT_TX 0x020 // Transmit Interrupt Mask +#define UART_INT_RX 0x010 // Receive Interrupt Mask + +//***************************************************************************** +// +// Values that can be passed to UARTConfigSet as the ulConfig parameter and +// returned by UARTConfigGet in the pulConfig parameter. Additionally, the +// UART_CONFIG_PAR_* subset can be passed to UARTParityModeSet as the ulParity +// parameter, and are returned by UARTParityModeGet. +// +//***************************************************************************** +#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data +#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data +#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data +#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data +#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit +#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits +#define UART_CONFIG_PAR_NONE 0x00000000 // No parity +#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity +#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity +#define UART_CONFIG_PAR_ONE 0x00000086 // Parity bit is one +#define UART_CONFIG_PAR_ZERO 0x00000082 // Parity bit is zero + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity); +extern unsigned long UARTParityModeGet(unsigned long ulBase); +extern void UARTConfigSet(unsigned long ulBase, unsigned long ulBaud, + unsigned long ulConfig); +extern void UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud, + unsigned long *pulConfig); +extern void UARTEnable(unsigned long ulBase); +extern void UARTDisable(unsigned long ulBase); +extern tBoolean UARTCharsAvail(unsigned long ulBase); +extern tBoolean UARTSpaceAvail(unsigned long ulBase); +extern long UARTCharNonBlockingGet(unsigned long ulBase); +extern long UARTCharGet(unsigned long ulBase); +extern tBoolean UARTCharNonBlockingPut(unsigned long ulBase, + unsigned char ucData); +extern void UARTCharPut(unsigned long ulBase, unsigned char ucData); +extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState); +extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern void UARTIntUnregister(unsigned long ulBase); +extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags); + +#ifdef __cplusplus +} +#endif + +#endif // __UART_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/watchdog.c b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/watchdog.c new file mode 100644 index 000000000..53332d051 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/watchdog.c @@ -0,0 +1,592 @@ +//***************************************************************************** +// +// watchdog.c - Driver for the Watchdog Timer Module. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup watchdog_api +//! @{ +// +//***************************************************************************** + +#include "../hw_ints.h" +#include "../hw_memmap.h" +#include "../hw_types.h" +#include "../hw_watchdog.h" +#include "debug.h" +#include "interrupt.h" +#include "watchdog.h" + +//***************************************************************************** +// +//! Determines if the watchdog timer is enabled. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This will check to see if the watchdog timer is enabled. +//! +//! \return Returns \b true if the watchdog timer is enabled, and \b false +//! if it is not. +// +//***************************************************************************** +#if defined(GROUP_running) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +WatchdogRunning(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // See if the watchdog timer module is enabled, and return. + // + return(HWREG(ulBase + WDT_O_CTL) & WDT_CTL_INTEN); +} +#endif + +//***************************************************************************** +// +//! Enables the watchdog timer. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This will enable the watchdog timer counter and interrupt. +//! +//! \note This function will have no effect if the watchdog timer has +//! been locked. +//! +//! \sa WatchdogLock(), WatchdogUnlock() +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +WatchdogEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Enable the watchdog timer module. + // + HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_INTEN; +} +#endif + +//***************************************************************************** +// +//! Enables the watchdog timer reset. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! Enables the capability of the watchdog timer to issue a reset to the +//! processor upon a second timeout condition. +//! +//! \note This function will have no effect if the watchdog timer has +//! been locked. +//! +//! \sa WatchdogLock(), WatchdogUnlock() +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_resetenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +WatchdogResetEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Enable the watchdog reset. + // + HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_RESEN; +} +#endif + +//***************************************************************************** +// +//! Disables the watchdog timer reset. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! Disables the capability of the watchdog timer to issue a reset to the +//! processor upon a second timeout condition. +//! +//! \note This function will have no effect if the watchdog timer has +//! been locked. +//! +//! \sa WatchdogLock(), WatchdogUnlock() +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_resetdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +WatchdogResetDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Disable the watchdog reset. + // + HWREG(ulBase + WDT_O_CTL) &= ~(WDT_CTL_RESEN); +} +#endif + +//***************************************************************************** +// +//! Enables the watchdog timer lock mechanism. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! Locks out write access to the watchdog timer configuration registers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_lock) || defined(BUILD_ALL) || defined(DOXYGEN) +void +WatchdogLock(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Lock out watchdog register writes. Writing anything to the WDT_O_LOCK + // register causes the lock to go into effect. + // + HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_LOCKED; +} +#endif + +//***************************************************************************** +// +//! Disables the watchdog timer lock mechanism. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! Enables write access to the watchdog timer configuration registers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_unlock) || defined(BUILD_ALL) || defined(DOXYGEN) +void +WatchdogUnlock(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Unlock watchdog register writes. + // + HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_UNLOCK; +} +#endif + +//***************************************************************************** +// +//! Gets the state of the watchdog timer lock mechanism. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! Returns the lock state of the watchdog timer registers. +//! +//! \return Returns \b true if the watchdog timer registers are locked, and +//! \b false if they are not locked. +// +//***************************************************************************** +#if defined(GROUP_lockstate) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +WatchdogLockState(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Get the lock state. + // + return((HWREG(ulBase + WDT_O_LOCK) == WDT_LOCK_LOCKED) ? true : false); +} +#endif + +//***************************************************************************** +// +//! Sets the watchdog timer reload value. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! \param ulLoadVal is the load value for the watchdog timer. +//! +//! This function sets the value to load into the watchdog timer when the count +//! reaches zero for the first time; if the watchdog timer is running when this +//! function is called, then the value will be immediately loaded into the +//! watchdog timer counter. If the parameter \e ulLoadVal is 0, then an +//! interrupt is immediately generated. +//! +//! \note This function will have no effect if the watchdog timer has +//! been locked. +//! +//! \sa WatchdogLock(), WatchdogUnlock(), WatchdogReloadGet() +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_reloadset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Set the load register. + // + HWREG(ulBase + WDT_O_LOAD) = ulLoadVal; +} +#endif + +//***************************************************************************** +// +//! Gets the watchdog timer reload value. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This function gets the value that is loaded into the watchdog timer when +//! the count reaches zero for the first time. +//! +//! \sa WatchdogReloadSet() +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_reloadget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +WatchdogReloadGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Get the load register. + // + return(HWREG(ulBase + WDT_O_LOAD)); +} +#endif + +//***************************************************************************** +// +//! Gets the current watchdog timer value. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This function reads the current value of the watchdog timer. +//! +//! \return Returns the current value of the watchdog timer. +// +//***************************************************************************** +#if defined(GROUP_valueget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +WatchdogValueGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Get the current watchdog timer register value. + // + return(HWREG(ulBase + WDT_O_VALUE)); +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for watchdog timer interrupt. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! \param pfnHandler is a pointer to the function to be called when the +//! watchdog timer interrupt occurs. +//! +//! This function does the actual registering of the interrupt handler. This +//! will enable the global interrupt in the interrupt controller; the watchdog +//! timer interrupt must be enabled via WatchdogEnable(). It is the interrupt +//! handler's responsibility to clear the interrupt source via +//! WatchdogIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +WatchdogIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Register the interrupt handler. + // + IntRegister(INT_WATCHDOG, pfnHandler); + + // + // Enable the watchdog timer interrupt. + // + IntEnable(INT_WATCHDOG); +} +#endif + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the watchdog timer interrupt. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This function does the actual unregistering of the interrupt handler. This +//! function will clear the handler to be called when a watchdog timer +//! interrupt occurs. This will also mask off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +WatchdogIntUnregister(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Disable the interrupt. + // + IntDisable(INT_WATCHDOG); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_WATCHDOG); +} +#endif + +//***************************************************************************** +// +//! Enables the watchdog timer interrupt. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! Enables the watchdog timer interrupt. +//! +//! \note This function will have no effect if the watchdog timer has +//! been locked. +//! +//! \sa WatchdogLock(), WatchdogUnlock(), WatchdogEnable() +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +WatchdogIntEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Enable the watchdog interrupt. + // + HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_INTEN; +} +#endif + +//***************************************************************************** +// +//! Gets the current watchdog timer interrupt status. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! \param bMasked is \b false if the raw interrupt status is required and +//! \b true if the masked interrupt status is required. +//! +//! This returns the interrupt status for the watchdog timer module. Either +//! the raw interrupt status or the status of interrupt that is allowed to +//! reflect to the processor can be returned. +//! +//! \return The current interrupt status, where a 1 indicates that the watchdog +//! interrupt is active, and a 0 indicates that it is not active. +// +//***************************************************************************** +#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ulBase + WDT_O_MIS)); + } + else + { + return(HWREG(ulBase + WDT_O_RIS)); + } +} +#endif + +//***************************************************************************** +// +//! Clears the watchdog timer interrupt. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! The watchdog timer interrupt source is cleared, so that it no longer +//! asserts. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +WatchdogIntClear(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Clear the interrupt source. + // + HWREG(ulBase + WDT_O_ICR) = WDT_INT_TIMEOUT; +} +#endif + +//***************************************************************************** +// +//! Enables stalling of the watchdog timer during debug events. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This function allows the watchdog timer to stop counting when the processor +//! is stopped by the debugger. By doing so, the watchdog is prevented from +//! expiring (typically almost immediately from a human time perspective) and +//! resetting the system (if reset is enabled). The watchdog will instead +//! expired after the appropriate number of processor cycles have been executed +//! while debugging (or at the appropriate time after the processor has been +//! restarted). +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_stallenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +WatchdogStallEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Enable timer stalling. + // + HWREG(ulBase + WDT_O_TEST) |= WDT_TEST_STALL; +} +#endif + +//***************************************************************************** +// +//! Disables stalling of the watchdog timer during debug events. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This function disables the debug mode stall of the watchdog timer. By +//! doing so, the watchdog timer continues to count regardless of the processor +//! debug state. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_stalldisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +WatchdogStallDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Disable timer stalling. + // + HWREG(ulBase + WDT_O_TEST) &= ~(WDT_TEST_STALL); +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/watchdog.h b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/watchdog.h new file mode 100644 index 000000000..9378504a0 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/hw_include/watchdog.h @@ -0,0 +1,63 @@ +//***************************************************************************** +// +// watchdog.h - Prototypes for the Watchdog Timer API +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __WATCHDOG_H__ +#define __WATCHDOG_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern tBoolean WatchdogRunning(unsigned long ulBase); +extern void WatchdogEnable(unsigned long ulBase); +extern void WatchdogResetEnable(unsigned long ulBase); +extern void WatchdogResetDisable(unsigned long ulBase); +extern void WatchdogLock(unsigned long ulBase); +extern void WatchdogUnlock(unsigned long ulBase); +extern tBoolean WatchdogLockState(unsigned long ulBase); +extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal); +extern unsigned long WatchdogReloadGet(unsigned long ulBase); +extern unsigned long WatchdogValueGet(unsigned long ulBase); +extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern void WatchdogIntUnregister(unsigned long ulBase); +extern void WatchdogIntEnable(unsigned long ulBase); +extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void WatchdogIntClear(unsigned long ulBase); +extern void WatchdogStallDisable(unsigned long ulBase); +extern void WatchdogStallDisable(unsigned long ulBase); + +#ifdef __cplusplus +} +#endif + +#endif // __WATCHDOG_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/init/startup.c b/20080212/Demo/CORTEX_LM3S811_GCC/init/startup.c new file mode 100644 index 000000000..407a49792 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/init/startup.c @@ -0,0 +1,221 @@ +//***************************************************************************** +// +// startup.c - Boot code for Stellaris. +// +// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1049 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +// Forward declaration of the default fault handlers. +// +//***************************************************************************** +void ResetISR(void); +static void NmiSR(void); +static void FaultISR(void); +static void IntDefaultHandler(void); +extern void xPortPendSVHandler(void); +extern void xPortSysTickHandler(void); +extern void vUART_ISR( void ); +extern void vGPIO_ISR( void ); + +//***************************************************************************** +// +// The entry point for the application. +// +//***************************************************************************** +extern int main(void); + +//***************************************************************************** +// +// Reserve space for the system stack. +// +//***************************************************************************** +#ifndef STACK_SIZE +#define STACK_SIZE 64 +#endif +static unsigned long pulStack[STACK_SIZE]; + +//***************************************************************************** +// +// The minimal vector table for a Cortex M3. Note that the proper constructs +// must be placed on this to ensure that it ends up at physical address +// 0x0000.0000. +// +//***************************************************************************** +__attribute__ ((section(".isr_vector"))) +void (* const g_pfnVectors[])(void) = +{ + (void (*)(void))((unsigned long)pulStack + sizeof(pulStack)), + // The initial stack pointer + ResetISR, // The reset handler + NmiSR, // The NMI handler + FaultISR, // The hard fault handler + IntDefaultHandler, // The MPU fault handler + IntDefaultHandler, // The bus fault handler + IntDefaultHandler, // The usage fault handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // SVCall handler + IntDefaultHandler, // Debug monitor handler + 0, // Reserved + xPortPendSVHandler, // The PendSV handler + xPortSysTickHandler, // The SysTick handler + IntDefaultHandler, // GPIO Port A + IntDefaultHandler, // GPIO Port B + vGPIO_ISR, // GPIO Port C + IntDefaultHandler, // GPIO Port D + IntDefaultHandler, // GPIO Port E + vUART_ISR, // UART0 Rx and Tx + IntDefaultHandler, // UART1 Rx and Tx + IntDefaultHandler, // SSI Rx and Tx + IntDefaultHandler, // I2C Master and Slave + IntDefaultHandler, // PWM Fault + IntDefaultHandler, // PWM Generator 0 + IntDefaultHandler, // PWM Generator 1 + IntDefaultHandler, // PWM Generator 2 + IntDefaultHandler, // Quadrature Encoder + IntDefaultHandler, // ADC Sequence 0 + IntDefaultHandler, // ADC Sequence 1 + IntDefaultHandler, // ADC Sequence 2 + IntDefaultHandler, // ADC Sequence 3 + IntDefaultHandler, // Watchdog timer + IntDefaultHandler, // Timer 0 subtimer A + IntDefaultHandler, // Timer 0 subtimer B + IntDefaultHandler, // Timer 1 subtimer A + IntDefaultHandler, // Timer 1 subtimer B + IntDefaultHandler, // Timer 2 subtimer A + IntDefaultHandler, // Timer 2 subtimer B + IntDefaultHandler, // Analog Comparator 0 + IntDefaultHandler, // Analog Comparator 1 + IntDefaultHandler, // Analog Comparator 2 + IntDefaultHandler, // System Control (PLL, OSC, BO) + IntDefaultHandler // FLASH Control +}; + +//***************************************************************************** +// +// The following are constructs created by the linker, indicating where the +// the "data" and "bss" segments reside in memory. The initializers for the +// for the "data" segment resides immediately following the "text" segment. +// +//***************************************************************************** +extern unsigned long _etext; +extern unsigned long _data; +extern unsigned long _edata; +extern unsigned long _bss; +extern unsigned long _ebss; + +//***************************************************************************** +// +// This is the code that gets called when the processor first starts execution +// following a reset event. Only the absolutely necessary set is performed, +// after which the application supplied main() routine is called. Any fancy +// actions (such as making decisions based on the reset cause register, and +// resetting the bits in that register) are left solely in the hands of the +// application. +// +//***************************************************************************** +void +ResetISR(void) +{ + unsigned long *pulSrc, *pulDest; + + // + // Copy the data segment initializers from flash to SRAM. + // + pulSrc = &_etext; + for(pulDest = &_data; pulDest < &_edata; ) + { + *pulDest++ = *pulSrc++; + } + + // + // Zero fill the bss segment. + // + for(pulDest = &_bss; pulDest < &_ebss; ) + { + *pulDest++ = 0; + } + + // + // Call the application's entry point. + // + main(); +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a NMI. This +// simply enters an infinite loop, preserving the system state for examination +// by a debugger. +// +//***************************************************************************** +static void +NmiSR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a fault +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +FaultISR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives an unexpected +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +IntDefaultHandler(void) +{ + // + // Go into an infinite loop. + // + while(1) + { + } +} diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/main.c b/20080212/Demo/CORTEX_LM3S811_GCC/main.c new file mode 100644 index 000000000..e54465824 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/main.c @@ -0,0 +1,374 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +/* + * This project contains an application demonstrating the use of the + * FreeRTOS.org mini real time scheduler on the Luminary Micro LM3S811 Eval + * board. See http://www.FreeRTOS.org for more information. + * + * main() simply sets up the hardware, creates all the demo application tasks, + * then starts the scheduler. http://www.freertos.org/a00102.html provides + * more information on the standard demo tasks. + * + * In addition to a subset of the standard demo application tasks, main.c also + * defines the following tasks: + * + * + A 'Print' task. The print task is the only task permitted to access the + * LCD - thus ensuring mutual exclusion and consistent access to the resource. + * Other tasks do not access the LCD directly, but instead send the text they + * wish to display to the print task. The print task spends most of its time + * blocked - only waking when a message is queued for display. + * + * + A 'Button handler' task. The eval board contains a user push button that + * is configured to generate interrupts. The interrupt handler uses a + * semaphore to wake the button handler task - demonstrating how the priority + * mechanism can be used to defer interrupt processing to the task level. The + * button handler task sends a message both to the LCD (via the print task) and + * the UART where it can be viewed using a dumb terminal (via the UART to USB + * converter on the eval board). NOTES: The dumb terminal must be closed in + * order to reflash the microcontroller. A very basic interrupt driven UART + * driver is used that does not use the FIFO. 19200 baud is used. + * + * + A 'check' task. The check task only executes every five seconds but has a + * high priority so is guaranteed to get processor time. Its function is to + * check that all the other tasks are still operational and that no errors have + * been detected at any time. If no errors have every been detected 'PASS' is + * written to the display (via the print task) - if an error has ever been + * detected the message is changed to 'FAIL'. The position of the message is + * changed for each write. + */ + + + +/* Environment includes. */ +#include "DriverLib.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "semphr.h" + +/* Demo app includes. */ +#include "integer.h" +#include "PollQ.h" +#include "semtest.h" +#include "BlockQ.h" + +/* Delay between cycles of the 'check' task. */ +#define mainCHECK_DELAY ( ( portTickType ) 5000 / portTICK_RATE_MS ) + +/* UART configuration - note this does not use the FIFO so is not very +efficient. */ +#define mainBAUD_RATE ( 19200 ) +#define mainFIFO_SET ( 0x10 ) + +/* Demo task priorities. */ +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) + +/* Demo board specifics. */ +#define mainPUSH_BUTTON GPIO_PIN_4 + +/* Misc. */ +#define mainQUEUE_SIZE ( 3 ) +#define mainDEBOUNCE_DELAY ( ( portTickType ) 150 / portTICK_RATE_MS ) +#define mainNO_DELAY ( ( portTickType ) 0 ) +/* + * Configure the processor and peripherals for this demo. + */ +static void prvSetupHardware( void ); + +/* + * The 'check' task, as described at the top of this file. + */ +static void vCheckTask( void *pvParameters ); + +/* + * The task that is woken by the ISR that processes GPIO interrupts originating + * from the push button. + */ +static void vButtonHandlerTask( void *pvParameters ); + +/* + * The task that controls access to the LCD. + */ +static void vPrintTask( void *pvParameter ); + +/* String that is transmitted on the UART. */ +static portCHAR *cMessage = "Task woken by button interrupt! --- "; +static volatile portCHAR *pcNextChar; + +/* The semaphore used to wake the button handler task from within the GPIO +interrupt handler. */ +xSemaphoreHandle xButtonSemaphore; + +/* The queue used to send strings to the print task for display on the LCD. */ +xQueueHandle xPrintQueue; + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + /* Configure the clocks, UART and GPIO. */ + prvSetupHardware(); + + /* Create the semaphore used to wake the button handler task from the GPIO + ISR. */ + vSemaphoreCreateBinary( xButtonSemaphore ); + xSemaphoreTake( xButtonSemaphore, 0 ); + + /* Create the queue used to pass message to vPrintTask. */ + xPrintQueue = xQueueCreate( mainQUEUE_SIZE, sizeof( portCHAR * ) ); + + /* Start the standard demo tasks. */ + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + + /* Start the tasks defined within the file. */ + xTaskCreate( vCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + xTaskCreate( vButtonHandlerTask, "Status", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY + 1, NULL ); + xTaskCreate( vPrintTask, "Print", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY - 1, NULL ); + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* Will only get here if there was insufficient heap to start the + scheduler. */ + + return 0; +} +/*-----------------------------------------------------------*/ + +static void vCheckTask( void *pvParameters ) +{ +portBASE_TYPE xErrorOccurred = pdFALSE; +portTickType xLastExecutionTime; +const portCHAR *pcPassMessage = "PASS"; +const portCHAR *pcFailMessage = "FAIL"; + + /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() + works correctly. */ + xLastExecutionTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Perform this check every mainCHECK_DELAY milliseconds. */ + vTaskDelayUntil( &xLastExecutionTime, mainCHECK_DELAY ); + + /* Has an error been found in any task? */ + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + /* Send either a pass or fail message. If an error is found it is + never cleared again. We do not write directly to the LCD, but instead + queue a message for display by the print task. */ + if( xErrorOccurred == pdTRUE ) + { + xQueueSend( xPrintQueue, &pcFailMessage, portMAX_DELAY ); + } + else + { + xQueueSend( xPrintQueue, &pcPassMessage, portMAX_DELAY ); + } + } +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Setup the PLL. */ + SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); + + /* Setup the push button. */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC); + GPIODirModeSet(GPIO_PORTC_BASE, mainPUSH_BUTTON, GPIO_DIR_MODE_IN); + GPIOIntTypeSet( GPIO_PORTC_BASE, mainPUSH_BUTTON,GPIO_FALLING_EDGE ); + IntPrioritySet( INT_GPIOC, configKERNEL_INTERRUPT_PRIORITY ); + GPIOPinIntEnable( GPIO_PORTC_BASE, mainPUSH_BUTTON ); + IntEnable( INT_GPIOC ); + + + + /* Enable the UART. */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + + /* Set GPIO A0 and A1 as peripheral function. They are used to output the + UART signals. */ + GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); + + /* Configure the UART for 8-N-1 operation. */ + UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); + + /* We don't want to use the fifo. This is for test purposes to generate + as many interrupts as possible. */ + HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET; + + /* Enable Tx interrupts. */ + HWREG( UART0_BASE + UART_O_IM ) |= UART_INT_TX; + IntPrioritySet( INT_UART0, configKERNEL_INTERRUPT_PRIORITY ); + IntEnable( INT_UART0 ); + + + /* Initialise the LCD> */ + OSRAMInit( false ); + OSRAMStringDraw("www.FreeRTOS.org", 0, 0); + OSRAMStringDraw("LM3S811 demo", 16, 1); +} +/*-----------------------------------------------------------*/ + +static void vButtonHandlerTask( void *pvParameters ) +{ +const portCHAR *pcInterruptMessage = "Int"; + + for( ;; ) + { + /* Wait for a GPIO interrupt to wake this task. */ + while( xSemaphoreTake( xButtonSemaphore, portMAX_DELAY ) != pdPASS ); + + /* Start the Tx of the message on the UART. */ + UARTIntDisable( UART0_BASE, UART_INT_TX ); + { + pcNextChar = cMessage; + + /* Send the first character. */ + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = *pcNextChar; + } + + pcNextChar++; + } + UARTIntEnable(UART0_BASE, UART_INT_TX); + + /* Queue a message for the print task to display on the LCD. */ + xQueueSend( xPrintQueue, &pcInterruptMessage, portMAX_DELAY ); + + /* Make sure we don't process bounces. */ + vTaskDelay( mainDEBOUNCE_DELAY ); + xSemaphoreTake( xButtonSemaphore, mainNO_DELAY ); + } +} + +/*-----------------------------------------------------------*/ + +void vUART_ISR(void) +{ +unsigned portLONG ulStatus; + + /* What caused the interrupt. */ + ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); + + /* Clear the interrupt. */ + UARTIntClear( UART0_BASE, ulStatus ); + + /* Was a Tx interrupt pending? */ + if( ulStatus & UART_INT_TX ) + { + /* Send the next character in the string. We are not using the FIFO. */ + if( *pcNextChar != 0 ) + { + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = *pcNextChar; + } + pcNextChar++; + } + } +} +/*-----------------------------------------------------------*/ + +void vGPIO_ISR( void ) +{ + /* Clear the interrupt. */ + GPIOPinIntClear(GPIO_PORTC_BASE, mainPUSH_BUTTON); + + /* Wake the button handler task. */ + if( xSemaphoreGiveFromISR( xButtonSemaphore, pdFALSE ) ) + { + portEND_SWITCHING_ISR( pdTRUE ); + } +} +/*-----------------------------------------------------------*/ + +static void vPrintTask( void *pvParameters ) +{ +portCHAR *pcMessage; +unsigned portBASE_TYPE uxLine = 0, uxRow = 0; + + for( ;; ) + { + /* Wait for a message to arrive. */ + xQueueReceive( xPrintQueue, &pcMessage, portMAX_DELAY ); + + /* Write the message to the LCD. */ + uxRow++; + uxLine++; + OSRAMClear(); + OSRAMStringDraw( pcMessage, uxLine & 0x3f, uxRow & 0x01); + } +} + diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/makedefs b/20080212/Demo/CORTEX_LM3S811_GCC/makedefs new file mode 100644 index 000000000..efd7530d4 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/makedefs @@ -0,0 +1,208 @@ +#****************************************************************************** +# +# makedefs - Definitions common to all makefiles. +# +# Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +# +# Software License Agreement +# +# Luminary Micro, Inc. (LMI) is supplying this software for use solely and +# exclusively on LMI's Stellaris Family of microcontroller products. +# +# The software is owned by LMI and/or its suppliers, and is protected under +# applicable copyright laws. All rights are reserved. Any use in violation +# of the foregoing restrictions may subject the user to criminal sanctions +# under applicable laws, as well as to civil liability for the breach of the +# terms and conditions of this license. +# +# THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +# OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +# LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +# CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +# +#****************************************************************************** + +#****************************************************************************** +# +# Get the operating system name. If this is Cygwin, the .d files will be +# munged to convert c: into /cygdrive/c so that "make" will be happy with the +# auto-generated dependencies. +# +#****************************************************************************** +os:=${shell uname -s} + +#****************************************************************************** +# +# The compiler to be used. +# +#****************************************************************************** +ifndef COMPILER +COMPILER=gcc +endif + +#****************************************************************************** +# +# The debugger to be used. +# +#****************************************************************************** +ifndef DEBUGGER +DEBUGGER=gdb +endif + +#****************************************************************************** +# +# Definitions for using GCC. +# +#****************************************************************************** +ifeq (${COMPILER}, gcc) + +# +# The command for calling the compiler. +# +CC=arm-stellaris-eabi-gcc + +# +# The flags passed to the assembler. +# +AFLAGS=-mthumb \ + -mcpu=cortex-m3 \ + -MD + +# +# The flags passed to the compiler. +# +CFLAGS=-mthumb \ + -mcpu=cortex-m3 \ + -O2 \ + -MD + +# +# The command for calling the library archiver. +# +AR=arm-stellaris-eabi-ar + +# +# The command for calling the linker. +# +LD=arm-stellaris-eabi-ld + +# +# The flags passed to the linker. +# +LDFLAGS= -Map gcc/out.map + +# +# Get the location of libgcc.a from the GCC front-end. +# +LIBGCC=${shell ${CC} -mthumb -march=armv6t2 -print-libgcc-file-name} + +# +# Get the location of libc.a from the GCC front-end. +# +LIBC=${shell ${CC} -mthumb -march=armv6t2 -print-file-name=libc.a} + +# +# The command for extracting images from the linked executables. +# +OBJCOPY=arm-stellaris-eabi-objcopy + +endif + +#****************************************************************************** +# +# Tell the compiler to include debugging information if the DEBUG environment +# variable is set. +# +#****************************************************************************** +ifdef DEBUG +CFLAGS += -g +endif + +#****************************************************************************** +# +# The rule for building the object file from each C source file. +# +#****************************************************************************** +${COMPILER}/%.o: %.c + @if [ 'x${VERBOSE}' = x ]; \ + then \ + echo " CC ${<}"; \ + else \ + echo ${CC} ${CFLAGS} -D${COMPILER} -o ${@} -c ${<}; \ + fi + @${CC} ${CFLAGS} -D${COMPILER} -o ${@} -c ${<} +ifeq (${COMPILER}, rvds) + @mv -f ${notdir ${@:.o=.d}} ${COMPILER} +endif +ifneq ($(findstring CYGWIN, ${os}), ) + @perl -i.bak -p -e 's/[Cc]:/\/cygdrive\/c/g' ${@:.o=.d} +endif + +#****************************************************************************** +# +# The rule for building the object file from each assembly source file. +# +#****************************************************************************** +${COMPILER}/%.o: %.S + @if [ 'x${VERBOSE}' = x ]; \ + then \ + echo " CC ${<}"; \ + else \ + echo ${CC} ${AFLAGS} -D${COMPILER} -o ${@} -c ${<}; \ + fi +ifeq (${COMPILER}, rvds) + @${CC} ${AFLAGS} -D${COMPILER} -E ${<} > ${@:.o=_.S} + @${CC} ${AFLAGS} -o ${@} -c ${@:.o=_.S} + @rm ${@:.o=_.S} + @${CC} ${AFLAGS} -D${COMPILER} --md -E ${<} + @sed 's,,${@},g' ${notdir ${<:.S=.d}} > ${@:.o=.d} + @rm ${notdir ${<:.S=.d}} +endif +ifeq (${COMPILER}, gcc) + @${CC} ${AFLAGS} -D${COMPILER} -o ${@} -c ${<} +endif +ifneq ($(findstring CYGWIN, ${os}), ) + @perl -i.bak -p -e 's/[Cc]:/\/cygdrive\/c/g' ${@:.o=.d} +endif + +#****************************************************************************** +# +# The rule for creating an object library. +# +#****************************************************************************** +${COMPILER}/%.a: + @if [ 'x${VERBOSE}' = x ]; \ + then \ + echo " AR ${@}"; \ + else \ + echo ${AR} -cr ${@} ${^}; \ + fi + @${AR} -cr ${@} ${^} + +#****************************************************************************** +# +# The rule for linking the application. +# +#****************************************************************************** +${COMPILER}/%.axf: + @if [ 'x${VERBOSE}' = x ]; \ + then \ + echo " LD ${@}"; \ + fi +ifeq (${COMPILER}, gcc) + @if [ 'x${VERBOSE}' != x ]; \ + then \ + echo ${LD} -T ${SCATTER_${notdir ${@:.axf=}}} \ + --entry ${ENTRY_${notdir ${@:.axf=}}} \ + ${LDFLAGSgcc_${notdir ${@:.axf=}}} \ + ${LDFLAGS} -o ${@} ${^} \ + '${LIBC}' '${LIBGCC}'; \ + fi + @${LD} -T ${SCATTER_${notdir ${@:.axf=}}} \ + --entry ${ENTRY_${notdir ${@:.axf=}}} \ + ${LDFLAGSgcc_${notdir ${@:.axf=}}} \ + ${LDFLAGS} -o ${@} ${^} \ + '${LIBC}' '${LIBGCC}' + @${OBJCOPY} -O binary ${@} ${@:.axf=.bin} +endif diff --git a/20080212/Demo/CORTEX_LM3S811_GCC/standalone.ld b/20080212/Demo/CORTEX_LM3S811_GCC/standalone.ld new file mode 100644 index 000000000..8ee3fe2f8 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_GCC/standalone.ld @@ -0,0 +1,60 @@ +/****************************************************************************** + * + * standalone.ld - Linker script for applications using startup.c and + * DriverLib. + * + * Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. + * + * Software License Agreement + * + * Luminary Micro, Inc. (LMI) is supplying this software for use solely and + * exclusively on LMI's microcontroller products. + * + * The software is owned by LMI and/or its suppliers, and is protected under + * applicable copyright laws. All rights are reserved. Any use in violation + * of the foregoing restrictions may subject the user to criminal sanctions + * under applicable laws, as well as to civil liability for the breach of the + * terms and conditions of this license. + * + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + * This is part of revision 1049 of the Stellaris Driver Library. + * + *****************************************************************************/ + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K + SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 8K +} + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text) + *(.rodata*) + _etext = .; + } > FLASH + + .data : AT (ADDR(.text) + SIZEOF(.text)) + { + _data = .; + *(vtable) + *(.data) + _edata = .; + } > SRAM + + .bss : + { + _bss = .; + *(.bss) + *(COMMON) + _ebss = .; + } > SRAM +} diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/FreeRTOSConfig.h b/20080212/Demo/CORTEX_LM3S811_IAR/FreeRTOSConfig.h new file mode 100644 index 000000000..e5f3824e7 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/FreeRTOSConfig.h @@ -0,0 +1,86 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 70 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 7000 ) ) +#define configMAX_TASK_NAME_LEN ( 10 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_CO_ROUTINES 1 + +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + +#define configKERNEL_INTERRUPT_PRIORITY 255 + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LM3S811.icf b/20080212/Demo/CORTEX_LM3S811_IAR/LM3S811.icf new file mode 100644 index 000000000..5131af05e --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LM3S811.icf @@ -0,0 +1,58 @@ +//***************************************************************************** +// +// boot_demo1.icf - Linker configuration file for boot_demo1. +// +// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved. +// Luminary Micro Confidential - For Use Under NDA Only +// +//***************************************************************************** + +// +// Define a memory region that covers the entire 4 GB addressible space of the +// processor. +// +define memory mem with size = 4G; + +// +// Define a region for the on-chip flash. +// +define region FLASH = mem:[from 0x00000000 to 0x0000ffff]; + +// +// Define a region for the on-chip SRAM. +// +define region SRAM = mem:[from 0x20000000 to 0x20001fff]; + +// +// Define a block for the heap. The size should be set to something other +// than zero if things in the C library that require the heap are used. +// +define block HEAP with alignment = 8, size = 0x00000000 { }; + +// +// Indicate that the read/write values should be initialized by copying from +// flash. +// +initialize by copy { readwrite }; + +// +// Initicate that the noinit values should be left alone. This includes the +// stack, which if initialized will destroy the return address from the +// initialization code, causing the processor to branch to zero and fault. +// +do not initialize { section .noinit }; + +// +// Place the interrupt vectors at the start of flash. +// +place at start of FLASH { readonly section .intvec }; + +// +// Place the remainder of the read-only items into flash. +// +place in FLASH { readonly }; + +// +// Place all read/write items into SRAM. +// +place in SRAM { readwrite, block HEAP }; diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/DriverLib.h b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/DriverLib.h new file mode 100644 index 000000000..47531fbe9 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/DriverLib.h @@ -0,0 +1,39 @@ +#ifndef DRIVER_LIB_H +#define DRIVER_LIB_H + +#include "DriverLib.h" +#include "hw_adc.h" +#include "hw_comp.h" +#include "hw_flash.h" +#include "hw_gpio.h" +#include "hw_i2c.h" +#include "hw_ints.h" +#include "hw_memmap.h" +#include "hw_nvic.h" +#include "hw_pwm.h" +#include "hw_qei.h" +#include "hw_ssi.h" +#include "hw_sysctl.h" +#include "hw_timer.h" +#include "hw_types.h" +#include "hw_uart.h" +#include "hw_watchdog.h" +#include "osram96x16.h" +#include "adc.h" +#include "comp.h" +#include "cpu.h" +#include "debug.h" +#include "flash.h" +#include "gpio.h" +#include "i2c.h" +#include "interrupt.h" +#include "pwm.h" +#include "qei.h" +#include "ssi.h" +#include "sysctl.h" +#include "systick.h" +#include "timer.h" +#include "uart.h" +#include "watchdog.h" + +#endif diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/EULA.txt b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/EULA.txt new file mode 100644 index 000000000..02c57b2f9 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/EULA.txt @@ -0,0 +1,126 @@ +IMPORTANT. Read the following LMI Software License Agreement ("Agreement") +completely. + +LUMINARY MICRO SOFTWARE LICENSE AGREEMENT + + This is a legal agreement between you (either as an individual or as an +authorized representative of your employer) and Luminary Micro, Inc. ("LMI"). +It concerns your rights to use this file and any accompanying written materials +(the "Software"). In consideration for LMI allowing you to access the +Software, you are agreeing to be bound by the terms of this Agreement. If you +do not agree to all of the terms of this Agreement, do not download or use the +Software. If you change your mind later, stop using the Software and delete +all copies of the Software in your possession or control. Any copies of the +Software that you have already distributed, where permitted, and do not destroy +will continue to be governed by this Agreement. Your prior use will also +continue to be governed by this Agreement. + +1. LICENSE GRANT. LMI grants to you, free of charge, the non-exclusive, +non-transferable right (1) to use the Software, (2) to reproduce the Software, +(3) to prepare derivative works of the Software, (4) to distribute the Software +and derivative works thereof in source (human-readable) form and object +(machine-readable) form, and (5) to sublicense to others the right to use the +distributed Software. If you violate any of the terms or restrictions of this +Agreement, LMI may immediately terminate this Agreement, and require that you +stop using and delete all copies of the Software in your possession or control. + +2. COPYRIGHT. The Software is licensed to you, not sold. LMI owns the +Software, and United States copyright laws and international treaty provisions +protect the Software. Therefore, you must treat the Software like any other +copyrighted material (e.g. a book or musical recording). You may not use or +copy the Software for any other purpose than what is described in this +Agreement. Except as expressly provided herein, LMI does not grant to you any +express or implied rights under any LMI or third-party patents, copyrights, +trademarks, or trade secrets. Additionally, you must reproduce and apply any +copyright or other proprietary rights notices included on or embedded in the +Software to any copies or derivative works made thereof, in whole or in part, +if any. + +3. SUPPORT. LMI is NOT obligated to provide any support, upgrades or new +releases of the Software. If you wish, you may contact LMI and report problems +and provide suggestions regarding the Software. LMI has no obligation +whatsoever to respond in any way to such a problem report or suggestion. LMI +may make changes to the Software at any time, without any obligation to notify +or provide updated versions of the Software to you. + +4. INDEMNITY. You agree to fully defend and indemnify LMI from any and +all claims, liabilities, and costs (including reasonable attorney's fees) +related to (1) your use (including your sub-licensee's use, if permitted) of +the Software or (2) your violation of the terms and conditions of this +Agreement. + +5. HIGH RISK ACTIVITIES. You acknowledge that the Software is not fault +tolerant and is not designed, manufactured or intended by LMI for incorporation +into products intended for use or resale in on-line control equipment in +hazardous, dangerous to life or potentially life-threatening environments +requiring fail-safe performance, such as in the operation of nuclear +facilities, aircraft navigation or communication systems, air traffic control, +direct life support machines or weapons systems, in which the failure of +products could lead directly to death, personal injury or severe physical or +environmental damage ("High Risk Activities"). You specifically represent and +warrant that you will not use the Software or any derivative work of the +Software for High Risk Activities. + +6. PRODUCT LABELING. You are not authorized to use any LMI trademarks, +brand names, or logos. + +7. COMPLIANCE WITH LAWS; EXPORT RESTRICTIONS. You must use the Software +in accordance with all applicable U.S. laws, regulations and statutes. You +agree that neither you nor your licensees (if any) intend to or will, directly +or indirectly, export or transmit the Software to any country in violation of +U.S. export restrictions. + +8. GOVERNMENT USE. Use of the Software and any corresponding +documentation, if any, is provided with RESTRICTED RIGHTS. Use, duplication or +disclosure by the Government is subject to restrictions as set forth in +subparagraph (c)(1)(ii) of The Rights in Technical Data and Computer Software +clause at DFARS 252.227-7013 or subparagraphs (c)(l) and (2) of the Commercial +Computer Software--Restricted Rights at 48 CFR 52.227-19, as applicable. +Manufacturer is Luminary Micro, Inc., 2499 S. Capital of Texas Hwy Ste A-100, +Austin, Texas 78746. + +9. DISCLAIMER OF WARRANTY. TO THE MAXIMUM EXTENT PERMITTED BY LAW, LMI +EXPRESSLY DISCLAIMS ANY WARRANTY FOR THE SOFTWARE. THE SOFTWARE IS PROVIDED +"AS IS", WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING, +WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A +PARTICULAR PURPOSE, OR NON-INFRINGEMENT. YOU ASSUME THE ENTIRE RISK ARISING +OUT OF THE USE OR PERFORMANCE OF THE SOFTWARE, OR ANY SYSTEMS YOU DESIGN USING +THE SOFTWARE (IF ANY). NOTHING IN THIS AGREEMENT MAY BE CONSTRUED AS A +WARRANTY OR REPRESENTATION BY LMI THAT THE SOFTWARE OR ANY DERIVATIVE WORK +DEVELOPED WITH OR INCORPORATING THE SOFTWARE WILL BE FREE FROM INFRINGEMENT OF +THE INTELLECTUAL PROPERTY RIGHTS OF THIRD PARTIES. + +10. LIMITATION OF LIABILITY. IN NO EVENT WILL LMI BE LIABLE, WHETHER IN +CONTRACT, TORT, OR OTHERWISE, FOR ANY INCIDENTAL, SPECIAL, INDIRECT, +CONSEQUENTIAL OR PUNITIVE DAMAGES, INCLUDING, BUT NOT LIMITED TO, DAMAGES FOR +ANY LOSS OF USE, LOSS OF TIME, INCONVENIENCE, COMMERCIAL LOSS, OR LOST PROFITS, +SAVINGS, OR REVENUES TO THE FULL EXTENT SUCH MAY BE DISCLAIMED BY LAW. + +11. CHOICE OF LAW; VENUE; LIMITATIONS. You agree that the statutes and +laws of the United States and the State of Texas, USA, without regard to +conflicts of laws principles, will apply to all matters relating to this +Agreement or the Software, and you agree that any litigation will be subject to +the exclusive jurisdiction of the state or federal courts in Austin, Travis +County, Texas, USA. You agree that regardless of any statute or law to the +contrary, any claim or cause of action arising out of or related to this +Agreement or the Software must be filed within one (1) year after such claim or +cause of action arose or be forever barred. + +12. ENTIRE AGREEMENT. This Agreement constitutes the entire agreement +between you and LMI regarding the subject matter of this Agreement, and +supersedes all prior communications, negotiations, understandings, agreements +or representations, either written or oral, if any. This Agreement may only be +amended in written form, executed by you and LMI. + +13. SEVERABILITY. If any provision of this Agreement is held for any +reason to be invalid or unenforceable, then the remaining provisions of this +Agreement will be unimpaired and, unless a modification or replacement of the +invalid or unenforceable provision is further held to deprive you or LMI of a +material benefit, in which case the Agreement will immediately terminate, the +invalid or unenforceable provision will be replaced with a provision that is +valid and enforceable and that comes closest to the intention underlying the +invalid or unenforceable provision. + +14. NO WAIVER. The waiver by LMI of any breach of any provision of this +Agreement will not operate or be construed as a waiver of any other or a +subsequent breach of the same or a different provision. diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/adc.c b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/adc.c new file mode 100644 index 000000000..53f3adf5b --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/adc.c @@ -0,0 +1,946 @@ +//***************************************************************************** +// +// adc.c - Driver for the ADC. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup adc_api +//! @{ +// +//***************************************************************************** + +#include "../hw_adc.h" +#include "../hw_ints.h" +#include "../hw_memmap.h" +#include "../hw_types.h" +#include "adc.h" +#include "debug.h" +#include "interrupt.h" + +//***************************************************************************** +// +// The currently configured software oversampling factor for each of the ADC +// sequencers. +// +//***************************************************************************** +#if defined(GROUP_pucoverssamplefactor) || defined(BUILD_ALL) +unsigned char g_pucOversampleFactor[3]; +#else +extern unsigned char g_pucOversampleFactor[3]; +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for an ADC interrupt. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! \param pfnHandler is a pointer to the function to be called when the +//! ADC sample sequence interrupt occurs. +//! +//! This function sets the handler to be called when a sample sequence +//! interrupt occurs. This will enable the global interrupt in the interrupt +//! controller; the sequence interrupt must be enabled with ADCIntEnable(). It +//! is the interrupt handler's responsibility to clear the interrupt source via +//! ADCIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum, + void (*pfnHandler)(void)) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + + // + // Determine the interrupt to register based on the sequence number. + // + ulInt = INT_ADC0 + ulSequenceNum; + + // + // Register the interrupt handler. + // + IntRegister(ulInt, pfnHandler); + + // + // Enable the timer interrupt. + // + IntEnable(ulInt); +} +#endif + +//***************************************************************************** +// +//! Unregisters the interrupt handler for an ADC interrupt. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! This function unregisters the interrupt handler. This will disable the +//! global interrupt in the interrupt controller; the sequence interrupt must +//! be disabled via ADCIntDisable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ADCIntUnregister(unsigned long ulBase, unsigned long ulSequenceNum) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + + // + // Determine the interrupt to unregister based on the sequence number. + // + ulInt = INT_ADC0 + ulSequenceNum; + + // + // Disable the interrupt. + // + IntDisable(ulInt); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulInt); +} +#endif + +//***************************************************************************** +// +//! Disables a sample sequence interrupt. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! This function disables the requested sample sequence interrupt. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + + // + // Disable this sample sequence interrupt. + // + HWREG(ulBase + ADC_O_IM) &= ~(1 << ulSequenceNum); +} +#endif + +//***************************************************************************** +// +//! Enables a sample sequence interrupt. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! This function enables the requested sample sequence interrupt. Any +//! outstanding interrupts are cleared before enabling the sample sequence +//! interrupt. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + + // + // Clear any outstanding interrupts on this sample sequence. + // + HWREG(ulBase + ADC_O_ISC) = 1 << ulSequenceNum; + + // + // Enable this sample sequence interrupt. + // + HWREG(ulBase + ADC_O_IM) |= 1 << ulSequenceNum; +} +#endif + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! \param bMasked is false if the raw interrupt status is required and true if +//! the masked interrupt status is required. +//! +//! This returns the interrupt status for the specified sample sequence. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. +//! +//! \return The current raw or masked interrupt status. +// +//***************************************************************************** +#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +ADCIntStatus(unsigned long ulBase, unsigned long ulSequenceNum, + tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ulBase + ADC_O_ISC) & (1 << ulSequenceNum)); + } + else + { + return(HWREG(ulBase + ADC_O_RIS) & (1 << ulSequenceNum)); + } +} +#endif + +//***************************************************************************** +// +//! Clears sample sequence interrupt source. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! The specified sample sequence interrupt is cleared, so that it no longer +//! asserts. This must be done in the interrupt handler to keep it from being +//! called again immediately upon exit. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arugments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + + // + // Clear the interrupt. + // + HWREG(ulBase + ADC_O_ISC) = 1 << ulSequenceNum; +} +#endif + +//***************************************************************************** +// +//! Enables a sample sequence. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! Allows the specified sample sequence to be captured when its trigger is +//! detected. A sample sequence must be configured before it is enabled. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_sequenceenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ADCSequenceEnable(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arugments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + + // + // Enable the specified sequence. + // + HWREG(ulBase + ADC_O_ACTSS) |= 1 << ulSequenceNum; +} +#endif + +//***************************************************************************** +// +//! Disables a sample sequence. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! Prevents the specified sample sequence from being captured when its trigger +//! is detected. A sample sequence should be disabled before it is configured. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_sequencedisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ADCSequenceDisable(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arugments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + + // + // Disable the specified sequences. + // + HWREG(ulBase + ADC_O_ACTSS) &= ~(1 << ulSequenceNum); +} +#endif + +//***************************************************************************** +// +//! Configures the trigger source and priority of a sample sequence. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! \param ulTrigger is the trigger source that initiates the sample sequence; +//! must be one of the \b ADC_TRIGGER_* values. +//! \param ulPriority is the relative priority of the sample sequence with +//! respect to the other sample sequences. +//! +//! This function configures the initiation criteria for a sample sequence. +//! Valid sample sequences range from zero to three; sequence zero will capture +//! up to eight samples, sequences one and two will capture up to four samples, +//! and sequence three will capture a single sample. The trigger condition and +//! priority (with respect to other sample sequence execution) is set. +//! +//! The parameter \b ulTrigger can take on the following values: +//! +//! - \b ADC_TRIGGER_PROCESSOR - A trigger generated by the processor, via the +//! ADCProcessorTrigger() function. +//! - \b ADC_TRIGGER_COMP0 - A trigger generated by the first analog +//! comparator; configured with ComparatorConfigure(). +//! - \b ADC_TRIGGER_COMP1 - A trigger generated by the second analog +//! comparator; configured with ComparatorConfigure(). +//! - \b ADC_TRIGGER_COMP2 - A trigger generated by the third analog +//! comparator; configured with ComparatorConfigure(). +//! - \b ADC_TRIGGER_EXTERNAL - A trigger generated by an input from the Port +//! B4 pin. +//! - \b ADC_TRIGGER_TIMER - A trigger generated by a timer; configured with +//! TimerControlTrigger(). +//! - \b ADC_TRIGGER_PWM0 - A trigger generated by the first PWM generator; +//! configured with PWMGenIntTrigEnable(). +//! - \b ADC_TRIGGER_PWM1 - A trigger generated by the second PWM generator; +//! configured with PWMGenIntTrigEnable(). +//! - \b ADC_TRIGGER_PWM2 - A trigger generated by the third PWM generator; +//! configured with PWMGenIntTrigEnable(). +//! - \b ADC_TRIGGER_ALWAYS - A trigger that is always asserted, causing the +//! sample sequence to capture repeatedly (so long as +//! there is not a higher priority source active). +//! +//! Note that not all trigger sources are available on all Stellaris family +//! members; consult the data sheet for the device in question to determine the +//! availability of triggers. +//! +//! The parameter \b ulPriority is a value between 0 and 3, where 0 represents +//! the highest priority and 3 the lowest. Note that when programming the +//! priority among a set of sample sequences, each must have unique priority; +//! it is up to the caller to guarantee the uniqueness of the priorities. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_sequenceconfigure) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ADCSequenceConfigure(unsigned long ulBase, unsigned long ulSequenceNum, + unsigned long ulTrigger, unsigned long ulPriority) +{ + // + // Check the arugments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + ASSERT((ulTrigger == ADC_TRIGGER_PROCESSOR) || + (ulTrigger == ADC_TRIGGER_COMP0) || + (ulTrigger == ADC_TRIGGER_COMP1) || + (ulTrigger == ADC_TRIGGER_COMP2) || + (ulTrigger == ADC_TRIGGER_EXTERNAL) || + (ulTrigger == ADC_TRIGGER_TIMER) || + (ulTrigger == ADC_TRIGGER_PWM0) || + (ulTrigger == ADC_TRIGGER_PWM1) || + (ulTrigger == ADC_TRIGGER_PWM2) || + (ulTrigger == ADC_TRIGGER_ALWAYS)); + ASSERT(ulPriority < 4); + + // + // Compute the shift for the bits that control this sample sequence. + // + ulSequenceNum *= 4; + + // + // Set the trigger event for this sample sequence. + // + HWREG(ulBase + ADC_O_EMUX) = ((HWREG(ulBase + ADC_O_EMUX) & + ~(0xf << ulSequenceNum)) | + ((ulTrigger & 0xf) << ulSequenceNum)); + + // + // Set the priority for this sample sequence. + // + HWREG(ulBase + ADC_O_SSPRI) = ((HWREG(ulBase + ADC_O_SSPRI) & + ~(0xf << ulSequenceNum)) | + ((ulPriority & 0x3) << ulSequenceNum)); +} +#endif + +//***************************************************************************** +// +//! Configure a step of the sample sequencer. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! \param ulStep is the step to be configured. +//! \param ulConfig is the configuration of this step; must be a logical OR of +//! \b ADC_CTL_TS, \b ADC_CTL_IE, \b ADC_CTL_END, \b ADC_CTL_D, and one of the +//! input channel selects (\b ADC_CTL_CH0 through \b ADC_CTL_CH7). +//! +//! This function will set the configuration of the ADC for one step of a +//! sample sequence. The ADC can be configured for single-ended or +//! differential operation (the \b ADC_CTL_D bit selects differential +//! operation when set), the channel to be sampled can be chosen (the +//! \b ADC_CTL_CH0 through \b ADC_CTL_CH7 values), and the internal temperature +//! sensor can be selected (the \b ADC_CTL_TS bit). Additionally, this step +//! can be defined as the last in the sequence (the \b ADC_CTL_END bit) and it +//! can be configured to cause an interrupt when the step is complete (the +//! \b ADC_CTL_IE bit). The configuration is used by the ADC at the +//! appropriate time when the trigger for this sequence occurs. +//! +//! The \b ulStep parameter determines the order in which the samples are +//! captured by the ADC when the trigger occurs. It can range from zero to +//! seven for the first sample sequence, from zero to three for the second and +//! third sample sequence, and can only be zero for the fourth sample sequence. +//! +//! Differential mode only works with adjacent channel pairs (e.g. 0 and 1). +//! The channel select must be the number of the channel pair to sample (e.g. +//! \b ADC_CTL_CH0 for 0 and 1, or \b ADC_CTL_CH1 for 2 and 3) or undefined +//! results will be returned by the ADC. Additionally, if differential mode is +//! selected when the temperature sensor is being sampled, undefined results +//! will be returned by the ADC. +//! +//! It is the responsibility of the caller to ensure that a valid configuration +//! is specified; this function does not check the validity of the specified +//! configuration. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_sequencestepconfigure) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +ADCSequenceStepConfigure(unsigned long ulBase, unsigned long ulSequenceNum, + unsigned long ulStep, unsigned long ulConfig) +{ + // + // Check the arugments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + ASSERT(((ulSequenceNum == 0) && (ulStep < 8)) || + ((ulSequenceNum == 1) && (ulStep < 4)) || + ((ulSequenceNum == 2) && (ulStep < 4)) || + ((ulSequenceNum == 3) && (ulStep < 1))); + + // + // Get the offset of the sequence to be configured. + // + ulBase += ADC_O_SEQ + (ADC_O_SEQ_STEP * ulSequenceNum); + + // + // Compute the shift for the bits that control this step. + // + ulStep *= 4; + + // + // Set the analog mux value for this step. + // + HWREG(ulBase + ADC_O_X_SSMUX) = ((HWREG(ulBase + ADC_O_X_SSMUX) & + ~(0x0000000f << ulStep)) | + ((ulConfig & 0x0f) << ulStep)); + + // + // Set the control value for this step. + // + HWREG(ulBase + ADC_O_X_SSCTL) = ((HWREG(ulBase + ADC_O_X_SSCTL) & + ~(0x0000000f << ulStep)) | + (((ulConfig & 0xf0) >> 4) << ulStep)); +} +#endif + +//***************************************************************************** +// +//! Determines if a sample sequence overflow occurred. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! This determines if a sample sequence overflow has occurred. This will +//! happen if the captured samples are not read from the FIFO before the next +//! trigger occurs. +//! +//! \return Returns zero if there was not an overflow, and non-zero if there +//! was. +// +//***************************************************************************** +#if defined(GROUP_sequenceoverflow) || defined(BUILD_ALL) || defined(DOXYGEN) +long +ADCSequenceOverflow(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + + // + // Determine if there was an overflow on this sequence. + // + return(HWREG(ulBase + ADC_O_OSTAT) & (1 << ulSequenceNum)); +} +#endif + +//***************************************************************************** +// +//! Determines if a sample sequence underflow occurred. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! This determines if a sample sequence underflow has occurred. This will +//! happen if too many samples are read from the FIFO. +//! +//! \return Returns zero if there was not an underflow, and non-zero if there +//! was. +// +//***************************************************************************** +#if defined(GROUP_sequenceunderflow) || defined(BUILD_ALL) || defined(DOXYGEN) +long +ADCSequenceUnderflow(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + + // + // Determine if there was an underflow on this sequence. + // + return(HWREG(ulBase + ADC_O_USTAT) & (1 << ulSequenceNum)); +} +#endif + +//***************************************************************************** +// +//! Gets the captured data for a sample sequence. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! \param pulBuffer is the address where the data is stored. +//! +//! This function copies data from the specified sample sequence output FIFO to +//! a memory resident buffer. The number of samples available in the hardware +//! FIFO are copied into the buffer, which is assumed to be large enough to +//! hold that many samples. This will only return the samples that are +//! presently available, which may not be the entire sample sequence if it is +//! in the process of being executed. +//! +//! \return Returns the number of samples copied to the buffer. +// +//***************************************************************************** +#if defined(GROUP_sequencedataget) || defined(BUILD_ALL) || defined(DOXYGEN) +long +ADCSequenceDataGet(unsigned long ulBase, unsigned long ulSequenceNum, + unsigned long *pulBuffer) +{ + unsigned long ulCount; + + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + + // + // Get the offset of the sequence to be read. + // + ulBase += ADC_O_SEQ + (ADC_O_SEQ_STEP * ulSequenceNum); + + // + // Read samples from the FIFO until it is empty. + // + ulCount = 0; + while(!(HWREG(ulBase + ADC_O_X_SSFSTAT) & ADC_SSFSTAT_EMPTY) && + (ulCount < 8)) + { + // + // Read the FIFO and copy it to the destination. + // + *pulBuffer++ = HWREG(ulBase + ADC_O_X_SSFIFO); + + // + // Increment the count of samples read. + // + ulCount++; + } + + // + // Return the number of samples read. + // + return(ulCount); +} +#endif + +//***************************************************************************** +// +//! Causes a processor trigger for a sample sequence. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! +//! This function triggers a processor-initiated sample sequence if the sample +//! sequence trigger is configured to ADC_TRIGGER_PROCESSOR. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_processortrigger) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ADCProcessorTrigger(unsigned long ulBase, unsigned long ulSequenceNum) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 4); + + // + // Generate a processor trigger for this sample sequence. + // + HWREG(ulBase + ADC_O_PSSI) = 1 << ulSequenceNum; +} +#endif + +//***************************************************************************** +// +//! Configures the software oversampling factor of the ADC. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! \param ulFactor is the number of samples to be averaged. +//! +//! This function configures the software oversampling for the ADC, which can +//! be used to provide better resolution on the sampled data. Oversampling is +//! accomplished by averaging multiple samples from the same analog input. +//! Three different oversampling rates are supported; 2x, 4x, and 8x. +//! +//! Oversampling is only supported on the sample sequencers that are more than +//! one sample in depth (i.e. the fourth sample sequencer is not supported). +//! Oversampling by 2x (for example) divides the depth of the sample sequencer +//! by two; so 2x oversampling on the first sample sequencer can only provide +//! four samples per trigger. This also means that 8x oversampling is only +//! available on the first sample sequencer. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_softwareoversampleconfigure) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +ADCSoftwareOversampleConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulFactor) +{ + unsigned long ulValue; + + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 3); + ASSERT(((ulFactor == 2) || (ulFactor == 4) || (ulFactor == 8)) && + ((ulSequenceNum == 0) || (ulFactor != 8))); + + // + // Convert the oversampling factor to a shift factor. + // + for(ulValue = 0, ulFactor >>= 1; ulFactor; ulValue++, ulFactor >>= 1) + { + } + + // + // Save the sfiht factor. + // + g_pucOversampleFactor[ulSequenceNum] = ulValue; +} +#endif + +//***************************************************************************** +// +//! Configures a step of the software oversampled sequencer. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! \param ulStep is the step to be configured. +//! \param ulConfig is the configuration of this step. +//! +//! This function configures a step of the sample sequencer when using the +//! software oversampling feature. The number of steps available depends on +//! the oversampling factor set by ADCSoftwareOversampleConfigure(). The value +//! of \e ulConfig is the same as defined for ADCSequenceStepConfigure(). +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_softwareoversamplestepconfigure) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +ADCSoftwareOversampleStepConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulStep, + unsigned long ulConfig) +{ + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 3); + ASSERT(((ulSequenceNum == 0) && + (ulStep < (8 >> g_pucOversampleFactor[ulSequenceNum]))) || + (ulStep < (4 >> g_pucOversampleFactor[ulSequenceNum]))); + + // + // Get the offset of the sequence to be configured. + // + ulBase += ADC_O_SEQ + (ADC_O_SEQ_STEP * ulSequenceNum); + + // + // Compute the shift for the bits that control this step. + // + ulStep *= 4 << g_pucOversampleFactor[ulSequenceNum]; + + // + // Loop through the hardware steps that make up this step of the software + // oversampled sequence. + // + for(ulSequenceNum = 1 << g_pucOversampleFactor[ulSequenceNum]; + ulSequenceNum; ulSequenceNum--) + { + // + // Set the analog mux value for this step. + // + HWREG(ulBase + ADC_O_X_SSMUX) = ((HWREG(ulBase + ADC_O_X_SSMUX) & + ~(0x0000000f << ulStep)) | + ((ulConfig & 0x0f) << ulStep)); + + // + // Set the control value for this step. + // + HWREG(ulBase + ADC_O_X_SSCTL) = ((HWREG(ulBase + ADC_O_X_SSCTL) & + ~(0x0000000f << ulStep)) | + (((ulConfig & 0xf0) >> 4) << ulStep)); + if(ulSequenceNum != 1) + { + HWREG(ulBase + ADC_O_X_SSCTL) &= ~((ADC_SSCTL_IE0 | + ADC_SSCTL_END0) << ulStep); + } + + // + // Go to the next hardware step. + // + ulStep += 4; + } +} +#endif + +//***************************************************************************** +// +//! Gets the captured data for a sample sequence using software oversampling. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulSequenceNum is the sample sequence number. +//! \param pulBuffer is the address where the data is stored. +//! \param ulCount is the number of samples to be read. +//! +//! This function copies data from the specified sample sequence output FIFO to +//! a memory resident buffer with software oversampling applied. The requested +//! number of samples are copied into the data buffer; if there are not enough +//! samples in the hardware FIFO to satisfy this many oversampled data items +//! then incorrect results will be returned. It is the caller's responsibility +//! to read only the samples that are available and wait until enough data is +//! available, for example as a result of receiving an interrupt. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_softwareoversampledataget) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +ADCSoftwareOversampleDataGet(unsigned long ulBase, unsigned long ulSequenceNum, + unsigned long *pulBuffer, unsigned long ulCount) +{ + unsigned long ulIdx, ulAccum; + + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(ulSequenceNum < 3); + ASSERT(((ulSequenceNum == 0) && + (ulCount < (8 >> g_pucOversampleFactor[ulSequenceNum]))) || + (ulCount < (4 >> g_pucOversampleFactor[ulSequenceNum]))); + + // + // Get the offset of the sequence to be read. + // + ulBase += ADC_O_SEQ + (ADC_O_SEQ_STEP * ulSequenceNum); + + // + // Read the samples from the FIFO until it is empty. + // + while(ulCount--) + { + // + // Compute the sum of the samples. + // + ulAccum = 0; + for(ulIdx = 1 << g_pucOversampleFactor[ulSequenceNum]; ulIdx; ulIdx--) + { + // + // Read the FIFO and add it to the accumulator. + // + ulAccum += HWREG(ulBase + ADC_O_X_SSFIFO); + } + + // + // Write the averaged sample to the output buffer. + // + *pulBuffer++ = ulAccum >> g_pucOversampleFactor[ulSequenceNum]; + } +} +#endif + +//***************************************************************************** +// +//! Configures the hardware oversampling factor of the ADC. +//! +//! \param ulBase is the base address of the ADC module. +//! \param ulFactor is the number of samples to be averaged. +//! +//! This function configures the hardware oversampling for the ADC, which can +//! be used to provide better resolution on the sampled data. Oversampling is +//! accomplished by averaging multiple samples from the same analog input. Six +//! different oversampling rates are supported; 2x, 4x, 8x, 16x, 32x, and 64x. +//! Specifying an oversampling factor of zero will disable the hardware +//! oversampler. +//! +//! Hardware oversampling applies uniformly to all sample sequencers. It does +//! not reduce the depth of the sample sequencers like the software +//! oversampling APIs; each sample written into the sample sequence FIFO is a +//! fully oversampled analog input reading. +//! +//! Enabling hardware averaging increases the precision of the ADC at the cost +//! of throughput. For example, enabling 4x oversampling reduces the +//! throughput of a 250 KSps ADC to 62.5 KSps. +//! +//! \note Hardware oversampling is available beginning with Rev C0 of the +//! Stellaris microcontroller. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_hardwareoversampleconfigure) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +ADCHardwareOversampleConfigure(unsigned long ulBase, + unsigned long ulFactor) +{ + unsigned long ulValue; + + // + // Check the arguments. + // + ASSERT(ulBase == ADC_BASE); + ASSERT(((ulFactor == 0) || (ulFactor == 2) || (ulFactor == 4) || + (ulFactor == 8) || (ulFactor == 16) || (ulFactor == 32) || + (ulFactor == 64))); + + // + // Convert the oversampling factor to a shift factor. + // + for(ulValue = 0, ulFactor >>= 1; ulFactor; ulValue++, ulFactor >>= 1) + { + } + + // + // Write the shift factor to the ADC to configure the hardware oversampler. + // + HWREG(ulBase + ADC_O_SAC) = ulValue; +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/adc.h b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/adc.h new file mode 100644 index 000000000..c1fa37da4 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/adc.h @@ -0,0 +1,126 @@ +//***************************************************************************** +// +// adc.h - ADC headers for using the ADC driver functions. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __ADC_H__ +#define __ADC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to ADCSequenceConfigure as the ulTrigger +// parameter. +// +//***************************************************************************** +#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event +#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event +#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event +#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event +#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event +#define ADC_TRIGGER_TIMER 0x00000005 // Timer event +#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event +#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event +#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event +#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event + +//***************************************************************************** +// +// Values that can be passed to ADCSequenceStepConfigure as the ulConfig +// parameter. +// +//***************************************************************************** +#define ADC_CTL_TS 0x00000080 // Temperature sensor select +#define ADC_CTL_IE 0x00000040 // Interrupt enable +#define ADC_CTL_END 0x00000020 // Sequence end select +#define ADC_CTL_D 0x00000010 // Differential select +#define ADC_CTL_CH0 0x00000000 // Input channel 0 +#define ADC_CTL_CH1 0x00000001 // Input channel 1 +#define ADC_CTL_CH2 0x00000002 // Input channel 2 +#define ADC_CTL_CH3 0x00000003 // Input channel 3 +#define ADC_CTL_CH4 0x00000004 // Input channel 4 +#define ADC_CTL_CH5 0x00000005 // Input channel 5 +#define ADC_CTL_CH6 0x00000006 // Input channel 6 +#define ADC_CTL_CH7 0x00000007 // Input channel 7 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum, + void (*pfnHandler)(void)); +extern void ADCIntUnregister(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum); +extern void ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum); +extern unsigned long ADCIntStatus(unsigned long ulBase, + unsigned long ulSequenceNum, + tBoolean bMasked); +extern void ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum); +extern void ADCSequenceEnable(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCSequenceDisable(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCSequenceConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulTrigger, + unsigned long ulPriority); +extern void ADCSequenceStepConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulStep, + unsigned long ulConfig); +extern long ADCSequenceOverflow(unsigned long ulBase, + unsigned long ulSequenceNum); +extern long ADCSequenceUnderflow(unsigned long ulBase, + unsigned long ulSequenceNum); +extern long ADCSequenceDataGet(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long *pulBuffer); +extern void ADCProcessorTrigger(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCSoftwareOversampleConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulFactor); +extern void ADCSoftwareOversampleStepConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulStep, + unsigned long ulConfig); +extern void ADCSoftwareOversampleDataGet(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long *pulBuffer, + unsigned long ulCount); +extern void ADCHardwareOversampleConfigure(unsigned long ulBase, + unsigned long ulFactor); + +#ifdef __cplusplus +} +#endif + +#endif // __ADC_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/comp.c b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/comp.c new file mode 100644 index 000000000..aed156ea5 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/comp.c @@ -0,0 +1,448 @@ +//***************************************************************************** +// +// comp.c - Driver for the analog comparator. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup comp_api +//! @{ +// +//***************************************************************************** + +#include "../hw_comp.h" +#include "../hw_ints.h" +#include "../hw_memmap.h" +#include "../hw_types.h" +#include "comp.h" +#include "debug.h" +#include "interrupt.h" + +//***************************************************************************** +// +//! Configures a comparator. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index of the comparator to configure. +//! \param ulConfig is the configuration of the comparator. +//! +//! This function will configure a comparator. The \e ulConfig parameter is +//! the result of a logical OR operation between the \b COMP_TRIG_xxx, +//! \b COMP_INT_xxx, \b COMP_ASRCP_xxx, and \b COMP_OUTPUT_xxx values. +//! +//! The \b COMP_TRIG_xxx term can take on the following values: +//! +//! - \b COMP_TRIG_NONE to have no trigger to the ADC. +//! - \b COMP_TRIG_HIGH to trigger the ADC when the comparator output is high. +//! - \b COMP_TRIG_LOW to trigger the ADC when the comparator output is low. +//! - \b COMP_TRIG_FALL to trigger the ADC when the comparator output goes low. +//! - \b COMP_TRIG_RISE to trigger the ADC when the comparator output goes +//! high. +//! - \b COMP_TRIG_BOTH to trigger the ADC when the comparator output goes low +//! or high. +//! +//! The \b COMP_INT_xxx term can take on the following values: +//! +//! - \b COMP_INT_HIGH to generate an interrupt when the comparator output is +//! high. +//! - \b COMP_INT_LOW to generate an interrupt when the comparator output is +//! low. +//! - \b COMP_INT_FALL to generate an interrupt when the comparator output goes +//! low. +//! - \b COMP_INT_RISE to generate an interrupt when the comparator output goes +//! high. +//! - \b COMP_INT_BOTH to generate an interrupt when the comparator output goes +//! low or high. +//! +//! The \b COMP_ASRCP_xxx term can take on the following values: +//! +//! - \b COMP_ASRCP_PIN to use the dedicated Comp+ pin as the reference +//! voltage. +//! - \b COMP_ASRCP_PIN0 to use the Comp0+ pin as the reference voltage (this +//! the same as \b COMP_ASRCP_PIN for the comparator 0). +//! - \b COMP_ASRCP_REF to use the internally generated voltage as the +//! reference voltage. +//! +//! The \b COMP_OUTPUT_xxx term can take on the following values: +//! +//! - \b COMP_OUTPUT_NONE to disable the output from the comparator to a device +//! pin. +//! - \b COMP_OUTPUT_NORMAL to enable a non-inverted output from the comparator +//! to a device pin. +//! - \b COMP_OUTPUT_INVERT to enable an inverted output from the comparator to +//! a device pin. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_configure) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ComparatorConfigure(unsigned long ulBase, unsigned long ulComp, + unsigned long ulConfig) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + ASSERT(ulComp < 3); + + // + // Configure this comparator. + // + HWREG(ulBase + (ulComp * 0x20) + COMP_O_ACCTL0) = ulConfig; +} +#endif + +//***************************************************************************** +// +//! Sets the internal reference voltage. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulRef is the desired reference voltage. +//! +//! This function will set the internal reference voltage value. The voltage +//! is specified as one of the following values: +//! +//! - \b COMP_REF_OFF to turn off the reference voltage +//! - \b COMP_REF_0V to set the reference voltage to 0 V +//! - \b COMP_REF_0_1375V to set the reference voltage to 0.1375 V +//! - \b COMP_REF_0_275V to set the reference voltage to 0.275 V +//! - \b COMP_REF_0_4125V to set the reference voltage to 0.4125 V +//! - \b COMP_REF_0_55V to set the reference voltage to 0.55 V +//! - \b COMP_REF_0_6875V to set the reference voltage to 0.6875 V +//! - \b COMP_REF_0_825V to set the reference voltage to 0.825 V +//! - \b COMP_REF_0_928125V to set the reference voltage to 0.928125 V +//! - \b COMP_REF_0_9625V to set the reference voltage to 0.9625 V +//! - \b COMP_REF_1_03125V to set the reference voltage to 1.03125 V +//! - \b COMP_REF_1_134375V to set the reference voltage to 1.134375 V +//! - \b COMP_REF_1_1V to set the reference voltage to 1.1 V +//! - \b COMP_REF_1_2375V to set the reference voltage to 1.2375 V +//! - \b COMP_REF_1_340625V to set the reference voltage to 1.340625 V +//! - \b COMP_REF_1_375V to set the reference voltage to 1.375 V +//! - \b COMP_REF_1_44375V to set the reference voltage to 1.44375 V +//! - \b COMP_REF_1_5125V to set the reference voltage to 1.5125 V +//! - \b COMP_REF_1_546875V to set the reference voltage to 1.546875 V +//! - \b COMP_REF_1_65V to set the reference voltage to 1.65 V +//! - \b COMP_REF_1_753125V to set the reference voltage to 1.753125 V +//! - \b COMP_REF_1_7875V to set the reference voltage to 1.7875 V +//! - \b COMP_REF_1_85625V to set the reference voltage to 1.85625 V +//! - \b COMP_REF_1_925V to set the reference voltage to 1.925 V +//! - \b COMP_REF_1_959375V to set the reference voltage to 1.959375 V +//! - \b COMP_REF_2_0625V to set the reference voltage to 2.0625 V +//! - \b COMP_REF_2_165625V to set the reference voltage to 2.165625 V +//! - \b COMP_REF_2_26875V to set the reference voltage to 2.26875 V +//! - \b COMP_REF_2_371875V to set the reference voltage to 2.371875 V +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_refset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ComparatorRefSet(unsigned long ulBase, unsigned long ulRef) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + + // + // Set the voltage reference voltage as requested. + // + HWREG(ulBase + COMP_O_REFCTL) = ulRef; +} +#endif + +//***************************************************************************** +// +//! Gets the current comparator output value. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index of the comparator. +//! +//! This function retrieves the current value of the comparator output. +//! +//! \return Returns \b true if the comparator output is high and \b false if +//! the comparator output is low. +// +//***************************************************************************** +#if defined(GROUP_valueget) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +ComparatorValueGet(unsigned long ulBase, unsigned long ulComp) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + ASSERT(ulComp < 3); + + // + // Return the appropriate value based on the comparator's present output + // value. + // + if(HWREG(ulBase + (ulComp * 0x20) + COMP_O_ACSTAT0) & COMP_ACSTAT_OVAL) + { + return(true); + } + else + { + return(false); + } +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for the comparator interrupt. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index of the comparator. +//! \param pfnHandler is a pointer to the function to be called when the +//! comparator interrupt occurs. +//! +//! This sets the handler to be called when the comparator interrupt occurs. +//! This will enable the interrupt in the interrupt controller; it is the +//! interrupt-handler's responsibility to clear the interrupt source via +//! ComparatorIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp, + void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + ASSERT(ulComp < 3); + + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(INT_COMP0 + ulComp, pfnHandler); + + // + // Enable the interrupt in the interrupt controller. + // + IntEnable(INT_COMP0 + ulComp); + + // + // Enable the comparator interrupt. + // + HWREG(ulBase + COMP_O_INTEN) |= 1 << ulComp; +} +#endif + +//***************************************************************************** +// +//! Unregisters an interrupt handler for a comparator interrupt. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index of the comparator. +//! +//! This function will clear the handler to be called when a comparator +//! interrupt occurs. This will also mask off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ComparatorIntUnregister(unsigned long ulBase, unsigned long ulComp) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + ASSERT(ulComp < 3); + + // + // Disable the comparator interrupt. + // + HWREG(ulBase + COMP_O_INTEN) &= ~(1 << ulComp); + + // + // Disable the interrupt in the interrupt controller. + // + IntDisable(INT_COMP0 + ulComp); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_COMP0 + ulComp); +} +#endif + +//***************************************************************************** +// +//! Enables the comparator interrupt. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index of the comparator. +//! +//! This function enables generation of an interrupt from the specified +//! comparator. Only comparators whose interrupts are enabled can be reflected +//! to the processor. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + ASSERT(ulComp < 3); + + // + // Enable the comparator interrupt. + // + HWREG(ulBase + COMP_O_INTEN) |= 1 << ulComp; +} +#endif + +//***************************************************************************** +// +//! Disables the comparator interrupt. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index of the comparator. +//! +//! This function disables generation of an interrupt from the specified +//! comparator. Only comparators whose interrupts are enabled can be reflected +//! to the processor. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + ASSERT(ulComp < 3); + + // + // Disable the comparator interrupt. + // + HWREG(ulBase + COMP_O_INTEN) &= ~(1 << ulComp); +} +#endif + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index of the comparator. +//! \param bMasked is \b false if the raw interrupt status is required and +//! \b true if the masked interrupt status is required. +//! +//! This returns the interrupt status for the comparator. Either the raw or +//! the masked interrupt status can be returned. +//! +//! \return \b true if the interrupt is asserted and \b false if it is not +//! asserted. +// +//***************************************************************************** +#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp, + tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + ASSERT(ulComp < 3); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(((HWREG(ulBase + COMP_O_MIS) >> ulComp) & 1) ? true : false); + } + else + { + return(((HWREG(ulBase + COMP_O_RIS) >> ulComp) & 1) ? true : false); + } +} +#endif + +//***************************************************************************** +// +//! Clears a comparator interrupt. +//! +//! \param ulBase is the base address of the comparator module. +//! \param ulComp is the index of the comparator. +//! +//! The comparator interrupt is cleared, so that it no longer asserts. This +//! must be done in the interrupt handler to keep it from being called again +//! immediately upon exit. Note that for a level triggered interrupt, the +//! interrupt cannot be cleared until it stops asserting. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +ComparatorIntClear(unsigned long ulBase, unsigned long ulComp) +{ + // + // Check the arguments. + // + ASSERT(ulBase == COMP_BASE); + ASSERT(ulComp < 3); + + // + // Clear the interrupt. + // + HWREG(ulBase + COMP_O_MIS) = 1 << ulComp; +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/comp.h b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/comp.h new file mode 100644 index 000000000..9349982c4 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/comp.h @@ -0,0 +1,120 @@ +//***************************************************************************** +// +// comp.h - Prototypes for the analog comparator driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __COMP_H__ +#define __COMP_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to ComparatorConfigure() as the ulConfig +// parameter. For each group (i.e. COMP_TRIG_xxx, COMP_INT_xxx, etc.), one of +// the values may be selected and ORed together will values from the other +// groups. +// +//***************************************************************************** +#define COMP_TRIG_NONE 0x00000000 // No ADC trigger +#define COMP_TRIG_HIGH 0x00000880 // Trigger when high +#define COMP_TRIG_LOW 0x00000800 // Trigger when low +#define COMP_TRIG_FALL 0x00000820 // Trigger on falling edge +#define COMP_TRIG_RISE 0x00000840 // Trigger on rising edge +#define COMP_TRIG_BOTH 0x00000860 // Trigger on both edges +#define COMP_INT_HIGH 0x00000010 // Interrupt when high +#define COMP_INT_LOW 0x00000000 // Interrupt when low +#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge +#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge +#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges +#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin +#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin +#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference +#define COMP_OUTPUT_NONE 0x00000000 // No comparator output +#define COMP_OUTPUT_NORMAL 0x00000100 // Comparator output normal +#define COMP_OUTPUT_INVERT 0x00000102 // Comparator output inverted + +//***************************************************************************** +// +// Values that can be passed to ComparatorSetRef() as the ulRef parameter. +// +//***************************************************************************** +#define COMP_REF_OFF 0x00000000 // Turn off the internal reference +#define COMP_REF_0V 0x00000300 // Internal reference of 0V +#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V +#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V +#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V +#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V +#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V +#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V +#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V +#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V +#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V +#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V +#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V +#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V +#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V +#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V +#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V +#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V +#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V +#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V +#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V +#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V +#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V +#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V +#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V +#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V +#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V +#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V +#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp, + unsigned long ulConfig); +extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef); +extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp); +extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp, + void (*pfnHandler)(void)); +extern void ComparatorIntUnregister(unsigned long ulBase, + unsigned long ulComp); +extern void ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp); +extern void ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp); +extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp, + tBoolean bMasked); +extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp); + +#ifdef __cplusplus +} +#endif + +#endif // __COMP_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/cpu.h b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/cpu.h new file mode 100644 index 000000000..688c52223 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/cpu.h @@ -0,0 +1,40 @@ +//***************************************************************************** +// +// cpu.h - Prototypes for the CPU instruction wrapper functions. +// +// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __CPU_H__ +#define __CPU_H__ + +//***************************************************************************** +// +// Prototypes. +// +//***************************************************************************** +extern void CPUcpsid(void); +extern void CPUcpsie(void); +extern void CPUwfi(void); + +#endif // __CPU_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/debug.h b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/debug.h new file mode 100644 index 000000000..e46e2a772 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/debug.h @@ -0,0 +1,56 @@ +//***************************************************************************** +// +// debug.h - Macros for assisting debug of the driver library. +// +// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __DEBUG_H__ +#define __DEBUG_H__ + +//***************************************************************************** +// +// Prototype for the function that is called when an invalid argument is passed +// to an API. This is only used when doing a DEBUG build. +// +//***************************************************************************** +extern void __error__(char *pcFilename, unsigned long ulLine); + +//***************************************************************************** +// +// The ASSERT macro, which does the actual assertion checking. Typically, this +// will be for procedure arguments. +// +//***************************************************************************** +#ifdef DEBUG +#define ASSERT(expr) { \ + if(!(expr)) \ + { \ + __error__(__FILE__, __LINE__); \ + } \ + } +#else +#define ASSERT(expr) +#endif + +#endif // __DEBUG_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/driverlib.r79 b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/driverlib.r79 new file mode 100644 index 0000000000000000000000000000000000000000..074f82f1209c2c2e29d2e3db8dfc459d5fcfd317 GIT binary patch literal 134217 zcmeFa3w$L-l|NqH_jcd+&13S;BxK%?z)X_K+@3*T@*GHJCJ9LfP?1X}$;<>YNyuX! zh%g`^h^Qd?|ERFO-?|R|{yrDv;Q;t+olAGssne&bPE}Xe`JPiEZWJ!oE{$cg<72zBLnFg?$Au;agf`e4i8ZflZfsqD z{)VRiErck?zr?`o(D0?L<70a!nsFQ6IndcbdA0Z#&t`|G=Cb=HM@Dg%%x0&CXR_JZ zy>t6^5y@hiI5IRl#5Ci$j}GmcnH-;+9VLP?O2}qMCq~AGCU9+zkIl}Gb5<#C!Ekyu zyMJ_gW^9tOwah>0Bjf$zsi$;(NBij)c8uxv;CXzi!~r%n-wx`-iZY+`oCO&bykB<&mBw{K|5O>7ZyB+ee1 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wk2hg zvXHmY=l^q#hXf> (ulAddress / FLASH_PROTECT_SIZE)) & + FLASH_FMP_BLOCK_0) << 1) | + ((ulFMPPE >> (ulAddress / FLASH_PROTECT_SIZE)) & FLASH_FMP_BLOCK_0)) + { + // + // This block is marked as execute only (i.e. it can not be erased or + // programmed, and the only reads allowed are via the instruction fecth + // interface). + // + case 0: + case 1: + { + return(FlashExecuteOnly); + } + + // + // This block is marked as read only (i.e. it can not be erased or + // programmed). + // + case 2: + { + return(FlashReadOnly); + } + + // + // This block is read/write; it can be read, erased, and programmed. + // + case 3: + default: + { + return(FlashReadWrite); + } + } +} +#endif + +//***************************************************************************** +// +//! Sets the protection setting for a block of flash. +//! +//! \param ulAddress is the start address of the flash block to be protected. +//! \param eProtect is the protection to be applied to the block. Can be one +//! of \b FlashReadWrite, \b FlashReadOnly, or \b FlashExecuteOnly. +//! +//! This function will set the protection for the specified 2 kB block of +//! flash. Blocks which are read/write can be made read-only or execute-only. +//! Blocks which are read-only can be made execute-only. Blocks which are +//! execute-only cannot have their protection modified. Attempts to make the +//! block protection less stringent (i.e. read-only to read/write) will result +//! in a failure (and be prevented by the hardware). +//! +//! Changes to the flash protection are maintained only until the next reset. +//! This allows the application to be executed in the desired flash protection +//! environment to check for inappropriate flash access (via the flash +//! interrupt). To make the flash protection permanent, use the +//! FlashProtectSave() function. +//! +//! \return Returns 0 on success, or -1 if an invalid address or an invalid +//! protection was specified. +// +//***************************************************************************** +#if defined(GROUP_protectset) || defined(BUILD_ALL) || defined(DOXYGEN) +long +FlashProtectSet(unsigned long ulAddress, tFlashProtection eProtect) +{ + unsigned long ulProtectRE, ulProtectPE; + + // + // Check the argument. + // + ASSERT(!(ulAddress & (FLASH_PROTECT_SIZE - 1))); + ASSERT((eProtect == FlashReadWrite) || (eProtect == FlashReadOnly) || + (eProtect == FlashExecuteOnly)); + + // + // Convert the address into a block number. + // + ulAddress /= FLASH_PROTECT_SIZE; + + // + // Get the current protection. + // + ulProtectRE = HWREG(FLASH_FMPRE); + ulProtectPE = HWREG(FLASH_FMPPE); + + // + // Set the protection based on the requested proection. + // + switch(eProtect) + { + // + // Make this block execute only. + // + case FlashExecuteOnly: + { + // + // Turn off the read and program bits for this block. + // + ulProtectRE &= ~(FLASH_FMP_BLOCK_0 << ulAddress); + ulProtectPE &= ~(FLASH_FMP_BLOCK_0 << ulAddress); + + // + // We're done handling this protection. + // + break; + } + + // + // Make this block read only. + // + case FlashReadOnly: + { + // + // The block can not be made read only if it is execute only. + // + if(((ulProtectRE >> ulAddress) & FLASH_FMP_BLOCK_0) != + FLASH_FMP_BLOCK_0) + { + return(-1); + } + + // + // Make this block read only. + // + ulProtectPE &= ~(FLASH_FMP_BLOCK_0 << ulAddress); + + // + // We're done handling this protection. + // + break; + } + + // + // Make this block read/write. + // + case FlashReadWrite: + default: + { + // + // The block can not be made read/write if it is not already + // read/write. + // + if((((ulProtectRE >> ulAddress) & FLASH_FMP_BLOCK_0) != + FLASH_FMP_BLOCK_0) || + (((ulProtectPE >> ulAddress) & FLASH_FMP_BLOCK_0) != + FLASH_FMP_BLOCK_0)) + { + return(-1); + } + + // + // The block is already read/write, so there is nothing to do. + // + return(0); + } + } + + // + // Set the new protection. + // + HWREG(FLASH_FMPRE) = ulProtectRE; + HWREG(FLASH_FMPPE) = ulProtectPE; + + // + // Success. + // + return(0); +} +#endif + +//***************************************************************************** +// +//! Saves the flash protection settings. +//! +//! This function will make the currently programmed flash protection settings +//! permanent. This is a non-reversible operation; a chip reset or power cycle +//! will not change the flash protection. +//! +//! This function will not return until the protection has been saved. +//! +//! \return Returns 0 on success, or -1 if a hardware error is encountered. +// +//***************************************************************************** +#if defined(GROUP_protectsave) || defined(BUILD_ALL) || defined(DOXYGEN) +long +FlashProtectSave(void) +{ + // + // Tell the flash controller to write the flash read protection register. + // + HWREG(FLASH_FMA) = 0; + HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT; + + // + // Wait until the write has completed. + // + while(HWREG(FLASH_FMC) & FLASH_FMC_COMT) + { + } + + // + // Tell the flash controller to write the flash program protection + // register. + // + HWREG(FLASH_FMA) = 1; + HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT; + + // + // Wait until the write has completed. + // + while(HWREG(FLASH_FMC) & FLASH_FMC_COMT) + { + } + + // + // Success. + // + return(0); +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for the flash interrupt. +//! +//! \param pfnHandler is a pointer to the function to be called when the flash +//! interrupt occurs. +//! +//! This sets the handler to be called when the flash interrupt occurs. The +//! flash controller can generate an interrupt when an invalid flash access +//! occurs, such as trying to program or erase a read-only block, or trying to +//! read from an execute-only block. It can also generate an interrupt when a +//! program or erase operation has completed. The interrupt will be +//! automatically enabled when the handler is registered. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +FlashIntRegister(void (*pfnHandler)(void)) +{ + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(INT_FLASH, pfnHandler); + + // + // Enable the flash interrupt. + // + IntEnable(INT_FLASH); +} +#endif + +//***************************************************************************** +// +//! Unregisters the interrupt handler for the flash interrupt. +//! +//! This function will clear the handler to be called when the flash interrupt +//! occurs. This will also mask off the interrupt in the interrupt controller +//! so that the interrupt handler is no longer called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +FlashIntUnregister(void) +{ + // + // Disable the interrupt. + // + IntDisable(INT_FLASH); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_FLASH); +} +#endif + +//***************************************************************************** +// +//! Enables individual flash controller interrupt sources. +//! +//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. +//! Can be any of the \b FLASH_FCIM_PROGRAM or \b FLASH_FCIM_ACCESS values. +//! +//! Enables the indicated flash controller interrupt sources. Only the sources +//! that are enabled can be reflected to the processor interrupt; disabled +//! sources have no effect on the processor. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +FlashIntEnable(unsigned long ulIntFlags) +{ + // + // Enable the specified interrupts. + // + HWREG(FLASH_FCIM) |= ulIntFlags; +} +#endif + +//***************************************************************************** +// +//! Disables individual flash controller interrupt sources. +//! +//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled. +//! Can be any of the \b FLASH_FCIM_PROGRAM or \b FLASH_FCIM_ACCESS values. +//! +//! Disables the indicated flash controller interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +FlashIntDisable(unsigned long ulIntFlags) +{ + // + // Disable the specified interrupts. + // + HWREG(FLASH_FCIM) &= ~(ulIntFlags); +} +#endif + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param bMasked is false if the raw interrupt status is required and true if +//! the masked interrupt status is required. +//! +//! This returns the interrupt status for the flash controller. Either the raw +//! interrupt status or the status of interrupts that are allowed to reflect to +//! the processor can be returned. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! \b FLASH_FCMISC_PROGRAM and \b FLASH_FCMISC_ACCESS. +// +//***************************************************************************** +#if defined(GROUP_intgetstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +FlashIntGetStatus(tBoolean bMasked) +{ + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(FLASH_FCMISC)); + } + else + { + return(HWREG(FLASH_FCRIS)); + } +} +#endif + +//***************************************************************************** +// +//! Clears flash controller interrupt sources. +//! +//! \param ulIntFlags is the bit mask of the interrupt sources to be cleared. +//! Can be any of the \b FLASH_FCMISC_PROGRAM or \b FLASH_FCMISC_ACCESS +//! values. +//! +//! The specified flash controller interrupt sources are cleared, so that they +//! no longer assert. This must be done in the interrupt handler to keep it +//! from being called again immediately upon exit. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +FlashIntClear(unsigned long ulIntFlags) +{ + // + // Clear the flash interrupt. + // + HWREG(FLASH_FCMISC) = ulIntFlags; +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/flash.h b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/flash.h new file mode 100644 index 000000000..9c41dda4f --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/flash.h @@ -0,0 +1,75 @@ +//***************************************************************************** +// +// flash.h - Prototypes for the flash driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __FLASH_H__ +#define __FLASH_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to FlashProtectSet(), and returned by +// FlashProtectGet(). +// +//***************************************************************************** +typedef enum +{ + FlashReadWrite, // Flash can be read and written + FlashReadOnly, // Flash can only be read + FlashExecuteOnly // Flash can only be executed +} +tFlashProtection; + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern unsigned long FlashUsecGet(void); +extern void FlashUsecSet(unsigned long ulClocks); +extern long FlashErase(unsigned long ulAddress); +extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress, + unsigned long ulCount); +extern tFlashProtection FlashProtectGet(unsigned long ulAddress); +extern long FlashProtectSet(unsigned long ulAddress, + tFlashProtection eProtect); +extern long FlashProtectSave(void); +extern void FlashIntRegister(void (*pfnHandler)(void)); +extern void FlashIntUnregister(void); +extern void FlashIntEnable(unsigned long ulIntFlags); +extern void FlashIntDisable(unsigned long ulIntFlags); +extern unsigned long FlashIntGetStatus(tBoolean bMasked); +extern void FlashIntClear(unsigned long ulIntFlags); + +#ifdef __cplusplus +} +#endif + +#endif // __FLASH_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/gpio.c b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/gpio.c new file mode 100644 index 000000000..a49602e9b --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/gpio.c @@ -0,0 +1,1103 @@ +//***************************************************************************** +// +// gpio.c - API for GPIO ports +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup gpio_api +//! @{ +// +//***************************************************************************** + +#include "../hw_gpio.h" +#include "../hw_ints.h" +#include "../hw_memmap.h" +#include "../hw_types.h" +#include "debug.h" +#include "gpio.h" +#include "interrupt.h" + +//***************************************************************************** +// +//! \internal +//! Get GPIO interrupt number. +//! +//! \param ulPort base address of the selected GPIO port +//! +//! Given a GPIO base address, returns the corresponding interrupt number. +//! +//! \return Returns a GPIO interrupt number, or -1 if \e ulPort is invalid. +// +//***************************************************************************** +#if defined(GROUP_getintnumber) || defined(BUILD_ALL) +long +GPIOGetIntNumber(unsigned long ulPort) +{ + unsigned int ulInt; + + // + // Determine the GPIO interrupt number for the given module. + // + switch(ulPort) + { + case GPIO_PORTA_BASE: + { + ulInt = INT_GPIOA; + break; + } + + case GPIO_PORTB_BASE: + { + ulInt = INT_GPIOB; + break; + } + + case GPIO_PORTC_BASE: + { + ulInt = INT_GPIOC; + break; + } + + case GPIO_PORTD_BASE: + { + ulInt = INT_GPIOD; + break; + } + + case GPIO_PORTE_BASE: + { + ulInt = INT_GPIOE; + break; + } + + default: + { + return(-1); + } + } + + // + // Return GPIO interrupt number. + // + return(ulInt); +} +#else +extern long GPIOGetIntNumber(unsigned long ulPort); +#endif + +//***************************************************************************** +// +//! Sets the direction and mode of the specified pins of the selected +//! GPIO port. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! \param ulPinIO pin direction and/or mode +//! +//! This function will set the specified pins on the selected GPIO port +//! as either an input or output under software control, or it will set the +//! pin to be under hardware control. +//! +//! The parameter \e ulPinIO is an enumerated data type that can be one of +//! the following values: +//! +//! - \b GPIO_DIR_MODE_IN +//! - \b GPIO_DIR_MODE_OUT +//! - \b GPIO_DIR_MODE_HW +//! +//! where \b GPIO_DIR_MODE_IN specifies that the pin will be programmed as +//! a software controlled input, \b GPIO_DIR_MODE_OUT specifies that the pin +//! will be programmed as a software controlled output, and +//! \b GPIO_DIR_MODE_HW specifies that the pin will be placed under +//! hardware control. +//! +//! The pins are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_dirmodeset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIODirModeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulPinIO) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + ASSERT((ulPinIO == GPIO_DIR_MODE_IN) || (ulPinIO == GPIO_DIR_MODE_OUT) || + (ulPinIO == GPIO_DIR_MODE_HW)); + + // + // Set the pin direction and mode. + // + HWREG(ulPort + GPIO_O_DIR) = ((ulPinIO & 1) ? + (HWREG(ulPort + GPIO_O_DIR) | ucPins) : + (HWREG(ulPort + GPIO_O_DIR) & ~(ucPins))); + HWREG(ulPort + GPIO_O_AFSEL) = ((ulPinIO & 2) ? + (HWREG(ulPort + GPIO_O_AFSEL) | ucPins) : + (HWREG(ulPort + GPIO_O_AFSEL) & + ~(ucPins))); +} +#endif + +//***************************************************************************** +// +//! Gets the direction and mode of a specified pin of the selected +//! GPIO port. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPin pin number of the specified pin, relative to the selected +//! GPIO port. +//! +//! This function gets the direction and control mode for a specified pin on +//! the selected GPIO port. The pin can be configured as either an input or +//! output under software control, or it can be under hardware control. The +//! type of control and direction are returned as an enumerated data type. +//! +//! \return Returns one of the enumerated data types described for +//! GPIODirModeSet(). +// +//***************************************************************************** +#if defined(GROUP_dirmodeget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +GPIODirModeGet(unsigned long ulPort, unsigned char ucPin) +{ + unsigned long ulDir, ulAFSEL; + + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + ASSERT(ucPin < 8); + + // + // Convert from a pin number to a bit position. + // + ucPin = 1 << ucPin; + + // + // Return the pin direction and mode. + // + ulDir = HWREG(ulPort + GPIO_O_DIR); + ulAFSEL = HWREG(ulPort + GPIO_O_AFSEL); + return(((ulDir & ucPin) ? 1 : 0) | ((ulAFSEL & ucPin) ? 2 : 0)); +} +#endif + +//***************************************************************************** +// +//! Sets the interrupt type for the specified pins of the selected GPIO +//! port. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! \param ulIntType specifies the type of interrupt trigger mechanism +//! +//! This function sets up the various interrupt trigger mechanisms for the +//! specified pins on the selected GPIO port. +//! +//! The parameter \e ulIntType is an enumerated data type that can be one of +//! the following values: +//! +//! - \b GPIO_FALLING_EDGE +//! - \b GPIO_RISING_EDGE +//! - \b GPIO_BOTH_EDGES +//! - \b GPIO_LOW_LEVEL +//! - \b GPIO_HIGH_LEVEL +//! +//! where the different values describe the interrupt detection mechanism +//! (edge or level) and the particular triggering event (falling, rising, +//! or both edges for edge detect, low or high for level detect). +//! +//! The pins are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. +//! +//! \note In order to avoid any spurious interrupts, the user must +//! ensure that the GPIO inputs remain stable for the duration of +//! this function. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_inttypeset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulIntType) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + ASSERT((ulIntType == GPIO_FALLING_EDGE) || + (ulIntType == GPIO_RISING_EDGE) || + (ulIntType == GPIO_BOTH_EDGES) || + (ulIntType == GPIO_LOW_LEVEL) || + (ulIntType == GPIO_HIGH_LEVEL)); + + // + // Set the pin interrupt type. + // + HWREG(ulPort + GPIO_O_IBE) = ((ulIntType & 1) ? + (HWREG(ulPort + GPIO_O_IBE) | ucPins) : + (HWREG(ulPort + GPIO_O_IBE) & ~(ucPins))); + HWREG(ulPort + GPIO_O_IS) = ((ulIntType & 2) ? + (HWREG(ulPort + GPIO_O_IS) | ucPins) : + (HWREG(ulPort + GPIO_O_IS) & ~(ucPins))); + HWREG(ulPort + GPIO_O_IEV) = ((ulIntType & 4) ? + (HWREG(ulPort + GPIO_O_IEV) | ucPins) : + (HWREG(ulPort + GPIO_O_IEV) & ~(ucPins))); +} +#endif + +//***************************************************************************** +// +//! Gets the interrupt type for the specified pin of the selected GPIO +//! port. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPin pin number of the specified pin, relative to the selected +//! GPIO port. +//! +//! This function gets the interrupt type for a specified pin on the selected +//! GPIO port. The pin can be configured as a falling edge, rising edge, or +//! both edge detected interrupt, or it can be configured as a low level or +//! high level detected interrupt. The type of interrupt detection mechanism +//! is returned as an enumerated data type. +//! +//! \return Returns one of the enumerated data types described for +//! GPIOIntTypeSet(). +// +//***************************************************************************** +#if defined(GROUP_inttypeget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin) +{ + unsigned long ulIBE, ulIS, ulIEV; + + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + ASSERT(ucPin < 8); + + // + // Convert from a pin number to a bit position. + // + ucPin = 1 << ucPin; + + // + // Return the pin interrupt type. + // + ulIBE = HWREG(ulPort + GPIO_O_IBE); + ulIS = HWREG(ulPort + GPIO_O_IS); + ulIEV = HWREG(ulPort + GPIO_O_IEV); + return(((ulIBE & ucPin) ? 1 : 0) | ((ulIS & ucPin) ? 2 : 0) | + ((ulIEV & ucPin) ? 4 : 0)); +} +#endif + +//***************************************************************************** +// +//! Sets the pad configuration for the specified pins of the selected GPIO +//! port. +//! +//! \param ulPort is the base address of the GPIO port. +//! \param ucPins bit-packed representation of the specified pins. +//! \param ulStrength specifies the output drive strength. +//! \param ulPinType specifies the pin type. +//! +//! This function sets the drive strength and type for the specified pins +//! on the selected GPIO port. For pins configured as input ports, the +//! pad is configured as requested, but the only real effect on the input +//! is the configuration of the pull-up or pull-down termination. +//! +//! The parameter \e ulStrength can be one of the following values: +//! +//! - \b GPIO_STRENGTH_2MA +//! - \b GPIO_STRENGTH_4MA +//! - \b GPIO_STRENGTH_8MA +//! - \b GPIO_STRENGTH_8MA_SC +//! +//! where \b GPIO_STRENGTH_xMA specifies either 2, 4, or 8 mA output drive +//! strength, and \b GPIO_OUT_STRENGTH_8MA_SC specifies 8 mA output drive with +//! slew control. +//! +//! The parameter \e ulPinType can be one of the following values: +//! +//! - \b GPIO_PIN_TYPE_STD +//! - \b GPIO_PIN_TYPE_STD_WPU +//! - \b GPIO_PIN_TYPE_STD_WPD +//! - \b GPIO_PIN_TYPE_OD +//! - \b GPIO_PIN_TYPE_OD_WPU +//! - \b GPIO_PIN_TYPE_OD_WPD +//! - \b GPIO_PIN_TYPE_ANALOG +//! +//! where \b GPIO_PIN_TYPE_STD* specifies a push-pull pin, \b GPIO_PIN_TYPE_OD* +//! specifies an open-drain pin, \b *_WPU specifies a weak pull-up, \b *_WPD +//! specifies a weak pull-down, and \b GPIO_PIN_TYPE_ANALOG specifies an +//! analog input (for the comparators). +//! +//! The pins are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_padconfigset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulStrength, unsigned long ulPinType) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + ASSERT((ulStrength == GPIO_STRENGTH_2MA) || + (ulStrength == GPIO_STRENGTH_4MA) || + (ulStrength == GPIO_STRENGTH_8MA) || + (ulStrength == GPIO_STRENGTH_8MA_SC)); + ASSERT((ulPinType == GPIO_PIN_TYPE_STD) || + (ulPinType == GPIO_PIN_TYPE_STD_WPU) || + (ulPinType == GPIO_PIN_TYPE_STD_WPD) || + (ulPinType == GPIO_PIN_TYPE_OD) || + (ulPinType == GPIO_PIN_TYPE_OD_WPU) || + (ulPinType == GPIO_PIN_TYPE_OD_WPD) || + (ulPinType == GPIO_PIN_TYPE_ANALOG)) + + // + // Set the output drive strength. + // + HWREG(ulPort + GPIO_O_DR2R) = ((ulStrength & 1) ? + (HWREG(ulPort + GPIO_O_DR2R) | ucPins) : + (HWREG(ulPort + GPIO_O_DR2R) & ~(ucPins))); + HWREG(ulPort + GPIO_O_DR4R) = ((ulStrength & 2) ? + (HWREG(ulPort + GPIO_O_DR4R) | ucPins) : + (HWREG(ulPort + GPIO_O_DR4R) & ~(ucPins))); + HWREG(ulPort + GPIO_O_DR8R) = ((ulStrength & 4) ? + (HWREG(ulPort + GPIO_O_DR8R) | ucPins) : + (HWREG(ulPort + GPIO_O_DR8R) & ~(ucPins))); + HWREG(ulPort + GPIO_O_SLR) = ((ulStrength & 8) ? + (HWREG(ulPort + GPIO_O_SLR) | ucPins) : + (HWREG(ulPort + GPIO_O_SLR) & ~(ucPins))); + + // + // Set the pin type. + // + HWREG(ulPort + GPIO_O_ODR) = ((ulPinType & 1) ? + (HWREG(ulPort + GPIO_O_ODR) | ucPins) : + (HWREG(ulPort + GPIO_O_ODR) & ~(ucPins))); + HWREG(ulPort + GPIO_O_PUR) = ((ulPinType & 2) ? + (HWREG(ulPort + GPIO_O_PUR) | ucPins) : + (HWREG(ulPort + GPIO_O_PUR) & ~(ucPins))); + HWREG(ulPort + GPIO_O_PDR) = ((ulPinType & 4) ? + (HWREG(ulPort + GPIO_O_PDR) | ucPins) : + (HWREG(ulPort + GPIO_O_PDR) & ~(ucPins))); + HWREG(ulPort + GPIO_O_DEN) = ((ulPinType & 8) ? + (HWREG(ulPort + GPIO_O_DEN) | ucPins) : + (HWREG(ulPort + GPIO_O_DEN) & ~(ucPins))); +} +#endif + +//***************************************************************************** +// +//! Gets the pad configuration for the specified pin of the selected GPIO +//! port. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPin pin number of the specified pin, relative to the selected +//! GPIO port. +//! \param pulStrength pointer to storage for the output drive strength +//! \param pulPinType pointer to storage for the output drive type +//! +//! This function gets the pad configuration for a specified pin on the +//! selected GPIO port. The values returned in \e eStrength and \e eOutType +//! correspond to the values used in GPIOPadConfigSet(). This function also +//! works for pins configured as input pins; however, the only meaningful +//! data returned is whether the pin is terminated with a pull-up or +//! down resistor. +//! +//! \return None +// +//***************************************************************************** +#if defined(GROUP_padconfigget) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin, + unsigned long *pulStrength, unsigned long *pulPinType) +{ + unsigned long ulTemp1, ulTemp2, ulTemp3, ulTemp4; + + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + ASSERT(ucPin < 8); + + // + // Convert from a pin number to a bit position. + // + ucPin = (1 << ucPin); + + // + // Get the drive strength for this pin. + // + ulTemp1 = HWREG(ulPort + GPIO_O_DR2R); + ulTemp2 = HWREG(ulPort + GPIO_O_DR4R); + ulTemp3 = HWREG(ulPort + GPIO_O_DR8R); + ulTemp4 = HWREG(ulPort + GPIO_O_SLR); + *pulStrength = (((ulTemp1 & ucPin) ? 1 : 0) | ((ulTemp2 & ucPin) ? 2 : 0) | + ((ulTemp3 & ucPin) ? 4 : 0) | ((ulTemp4 & ucPin) ? 8 : 0)); + + // + // Get the pin type. + // + ulTemp1 = HWREG(ulPort + GPIO_O_ODR); + ulTemp2 = HWREG(ulPort + GPIO_O_PUR); + ulTemp3 = HWREG(ulPort + GPIO_O_PDR); + ulTemp4 = HWREG(ulPort + GPIO_O_DEN); + *pulPinType = (((ulTemp1 & ucPin) ? 1 : 0) | ((ulTemp2 & ucPin) ? 2 : 0) | + ((ulTemp3 & ucPin) ? 4 : 0) | ((ulTemp4 & ucPin) ? 8 : 0)); +} +#endif + +//***************************************************************************** +// +//! Enables interrupts for the specified pins of the selected GPIO port. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! +//! Unmasks the interrupt for the specified pins. +//! +//! The pins are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pinintenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Enable the interrupts. + // + HWREG(ulPort + GPIO_O_IM) |= ucPins; +} +#endif + +//***************************************************************************** +// +//! Disables interrupts for the specified pins of the selected GPIO port. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! +//! Masks the interrupt for the specified pins. +//! +//! The pins are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pinintdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Disable the interrupts. + // + HWREG(ulPort + GPIO_O_IM) &= ~(ucPins); +} +#endif + +//***************************************************************************** +// +//! Gets interrupt status for all the pins of the selected GPIO port. +//! +//! \param ulPort base address of the selected GPIO port +//! \param bMasked specifies whether masked or raw interrupt +//! status is returned +//! +//! If \e bMasked is set as \b true, then the masked interrupt status is +//! returned; otherwise, the raw interrupt status will be returned. +//! +//! \return Returns a bit-packed byte, where each bit that is set identifies +//! an active masked or raw interrupt, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. Bits +//! 31:8 should be ignored. +// +//***************************************************************************** +#if defined(GROUP_pinintstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +long +GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Return the interrupt status. + // + if(bMasked) + { + return(HWREG(ulPort + GPIO_O_MIS)); + } + else + { + return(HWREG(ulPort + GPIO_O_RIS)); + } +} +#endif + +//***************************************************************************** +// +//! Clears the interrupt for the specified pins of the selected GPIO port. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! +//! Clears the interrupt for the specified pins. +//! +//! The pins are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pinintclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Clear the interrupts. + // + HWREG(ulPort + GPIO_O_ICR) = ucPins; +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for the selected GPIO port. +//! +//! \param ulPort base address of the selected GPIO port +//! \param pfIntHandler pointer to the GPIO port interrupt handling function +//! +//! This function will ensure that the interrupt handler specified by \e +//! pfIntHandler is called when an interrupt is detected from the selected +//! GPIO port. This function will also enable the corresponding GPIO +//! interrupt in the interrupt controller; individual pin interrupts and +//! interrupt sources must be enabled with GPIOPinIntEnable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_portintregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPortIntRegister(unsigned long ulPort, void (*pfIntHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Get the interrupt number associated with the specified GPIO. + // + ulPort = GPIOGetIntNumber(ulPort); + + // + // Register the interrupt handler. + // + IntRegister(ulPort, pfIntHandler); + + // + // Enable the GPIO interrupt. + // + IntEnable(ulPort); +} +#endif + +//***************************************************************************** +// +//! Removes an interrupt handler for the selected GPIO port. +//! +//! \param ulPort base address of the selected GPIO port +//! +//! This function will unregister the interrupt handler for the specified +//! GPIO port. This function will also disable the corresponding +//! GPIO port interrupt in the interrupt controller; individual GPIO interrupts +//! and interrupt sources must be disabled with GPIOPinIntDisable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_portintunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPortIntUnregister(unsigned long ulPort) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Get the interrupt number associated with the specified GPIO. + // + ulPort = GPIOGetIntNumber(ulPort); + + // + // Disable the GPIO interrupt. + // + IntDisable(ulPort); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulPort); +} +#endif + +//***************************************************************************** +// +//! Reads the values present at the specified pins of the selected GPIO port. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! +//! The values at the specified pins are read, as specified by \e ucPins. +//! Values are returned for both input and output pins, and the value +//! for pins that are not specified by \e ucPins are set to 0. +//! +//! The pins are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. +//! +//! \return Returns a bit-packed byte providing the state of the specified +//! pin, where bit 0 of the byte represents GPIO port pin 0, bit 1 represents +//! GPIO port pin 1, etc. Any bit that is not specified by \e ucPins +//! is returned as a 0. Bits 31:8 should be ignored. +// +//***************************************************************************** +#if defined(GROUP_pinread) || defined(BUILD_ALL) || defined(DOXYGEN) +long +GPIOPinRead(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Return the pin value(s). + // + return(HWREG(ulPort + (GPIO_O_DATA + (ucPins << 2)))); +} +#endif + +//***************************************************************************** +// +//! Writes a value at the specified pins of the selected GPIO port. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! \param ucVal value to write to the specified pins +//! +//! Writes the corresponding bit values to the output pins specified +//! by \e ucPins. Writing to a pin configured as an input pin has no +//! effect. +//! +//! The pins are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pinwrite) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, unsigned char ucVal) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Write the pins. + // + HWREG(ulPort + (GPIO_O_DATA + (ucPins << 2))) = ucVal; +} +#endif + +//***************************************************************************** +// +//! Configures pin(s) for use as an analog comparator input. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! +//! The analog comparator input pins must be properly configured for the analog +//! comparator to function correctly. This function provides the proper +//! configuration for those pins. +//! +//! \note This cannot be used to turn any pin into an analog comparator input; +//! it only configures an analog comparator pin for proper operation. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pintypecomparator) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Make the pin(s) be inputs. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_IN); + + // + // Set the pad(s) for analog operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_ANALOG); +} +#endif + +//***************************************************************************** +// +//! Configures pin(s) for use by the I2C peripheral. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! +//! The I2C pins must be properly configured for the I2C peripheral to function +//! correctly. This function provides the proper configuration for those pins. +//! +//! \note This cannot be used to turn any pin into an I2C pin; it only +//! configures an I2C pin for proper operation. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pintypei2c) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for open-drain operation with a weak pull-up. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD_WPU); +} +#endif + +//***************************************************************************** +// +//! Configures pin(s) for use by the PWM peripheral. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! +//! The PWM pins must be properly configured for the PWM peripheral to function +//! correctly. This function provides a typical configuration for those pins; +//! other configurations may work as well depending upon the board setup (for +//! example, using the on-chip pull-ups). +//! +//! \note This cannot be used to turn any pin into a PWM pin; it only +//! configures a PWM pin for proper operation. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pintypepwm) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} +#endif + +//***************************************************************************** +// +//! Configures pin(s) for use by the QEI peripheral. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! +//! The QEI pins must be properly configured for the QEI peripheral to function +//! correctly. This function provides a typical configuration for those pins; +//! other configurations may work as well depending upon the board setup (for +//! example, not using the on-chip pull-ups). +//! +//! \note This cannot be used to turn any pin into a QEI pin; it only +//! configures a QEI pin for proper operation. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pintypeqei) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation with a weak pull-up. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU); +} +#endif + +//***************************************************************************** +// +//! Configures pin(s) for use by the SSI peripheral. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! +//! The SSI pins must be properly configured for the SSI peripheral to function +//! correctly. This function provides a typical configuration for those pins; +//! other configurations may work as well depending upon the board setup (for +//! example, using the on-chip pull-ups). +//! +//! \note This cannot be used to turn any pin into a SSI pin; it only +//! configures a SSI pin for proper operation. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pintypessi) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} +#endif + +//***************************************************************************** +// +//! Configures pin(s) for use by the Timer peripheral. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! +//! The CCP pins must be properly configured for the timer peripheral to +//! function correctly. This function provides a typical configuration for +//! those pins; other configurations may work as well depending upon the board +//! setup (for example, using the on-chip pull-ups). +//! +//! \note This cannot be used to turn any pin into a timer pin; it only +//! configures a timer pin for proper operation. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pintypetimer) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} +#endif + +//***************************************************************************** +// +//! Configures pin(s) for use by the UART peripheral. +//! +//! \param ulPort base address of the selected GPIO port +//! \param ucPins bit-packed representation of the specified pins +//! +//! The UART pins must be properly configured for the UART peripheral to +//! function correctly. This function provides a typical configuration for +//! those pins; other configurations may work as well depending upon the board +//! setup (for example, using the on-chip pull-ups). +//! +//! \note This cannot be used to turn any pin into a UART pin; it only +//! configures a UART pin for proper operation. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pintypeuart) || defined(BUILD_ALL) || defined(DOXYGEN) +void +GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins) +{ + // + // Check the arguments. + // + ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || + (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || + (ulPort == GPIO_PORTE_BASE)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/gpio.h b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/gpio.h new file mode 100644 index 000000000..88d657223 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/gpio.h @@ -0,0 +1,137 @@ +//***************************************************************************** +// +// gpio.h - Defines and Macros for GPIO API. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __GPIO_H__ +#define __GPIO_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following values define the bit field for the ucPins argument to several +// of the APIs. +// +//***************************************************************************** +#define GPIO_PIN_0 0x00000001 // GPIO pin 0 +#define GPIO_PIN_1 0x00000002 // GPIO pin 1 +#define GPIO_PIN_2 0x00000004 // GPIO pin 2 +#define GPIO_PIN_3 0x00000008 // GPIO pin 3 +#define GPIO_PIN_4 0x00000010 // GPIO pin 4 +#define GPIO_PIN_5 0x00000020 // GPIO pin 5 +#define GPIO_PIN_6 0x00000040 // GPIO pin 6 +#define GPIO_PIN_7 0x00000080 // GPIO pin 7 + +//***************************************************************************** +// +// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and +// returned from GPIODirModeGet. +// +//***************************************************************************** +#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input +#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output +#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function + +//***************************************************************************** +// +// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and +// returned from GPIOIntTypeGet. +// +//***************************************************************************** +#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge +#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge +#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges +#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level +#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level + +//***************************************************************************** +// +// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter, +// and returned by GPIOPadConfigGet in the *pulStrength parameter. +// +//***************************************************************************** +#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength +#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength +#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength +#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control + +//***************************************************************************** +// +// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter, +// and returned by GPIOPadConfigGet in the *pulPadType parameter. +// +//***************************************************************************** +#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull +#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up +#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down +#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain +#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up +#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down +#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulPinIO); +extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin); +extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulIntType); +extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin); +extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulStrength, + unsigned long ulPadType); +extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin, + unsigned long *pulStrength, + unsigned long *pulPadType); +extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins); +extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked); +extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPortIntRegister(unsigned long ulPort, + void (*pfIntHandler)(void)); +extern void GPIOPortIntUnregister(unsigned long ulPort); +extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, + unsigned char ucVal); +extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins); + +#ifdef __cplusplus +} +#endif + +#endif // __GPIO_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_adc.h b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_adc.h new file mode 100644 index 000000000..022b9e963 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_adc.h @@ -0,0 +1,343 @@ +//***************************************************************************** +// +// hw_adc.h - Macros used when accessing the ADC hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_ADC_H__ +#define __HW_ADC_H__ + +//***************************************************************************** +// +// The following define the offsets of the ADC registers. +// +//***************************************************************************** +#define ADC_O_ACTSS 0x00000000 // Active sample register +#define ADC_O_RIS 0x00000004 // Raw interrupt status register +#define ADC_O_IM 0x00000008 // Interrupt mask register +#define ADC_O_ISC 0x0000000C // Interrupt status/clear register +#define ADC_O_OSTAT 0x00000010 // Overflow status register +#define ADC_O_EMUX 0x00000014 // Event multiplexer select reg. +#define ADC_O_USTAT 0x00000018 // Underflow status register +#define ADC_O_SSPRI 0x00000020 // Channel priority register +#define ADC_O_PSSI 0x00000028 // Processor sample initiate reg. +#define ADC_O_SAC 0x00000030 // Sample Averaging Control reg. +#define ADC_O_SSMUX0 0x00000040 // Multiplexer select 0 register +#define ADC_O_SSCTL0 0x00000044 // Sample sequence control 0 reg. +#define ADC_O_SSFIFO0 0x00000048 // Result FIFO 0 register +#define ADC_O_SSFSTAT0 0x0000004C // FIFO 0 status register +#define ADC_O_SSMUX1 0x00000060 // Multiplexer select 1 register +#define ADC_O_SSCTL1 0x00000064 // Sample sequence control 1 reg. +#define ADC_O_SSFIFO1 0x00000068 // Result FIFO 1 register +#define ADC_O_SSFSTAT1 0x0000006C // FIFO 1 status register +#define ADC_O_SSMUX2 0x00000080 // Multiplexer select 2 register +#define ADC_O_SSCTL2 0x00000084 // Sample sequence control 2 reg. +#define ADC_O_SSFIFO2 0x00000088 // Result FIFO 2 register +#define ADC_O_SSFSTAT2 0x0000008C // FIFO 2 status register +#define ADC_O_SSMUX3 0x000000A0 // Multiplexer select 3 register +#define ADC_O_SSCTL3 0x000000A4 // Sample sequence control 3 reg. +#define ADC_O_SSFIFO3 0x000000A8 // Result FIFO 3 register +#define ADC_O_SSFSTAT3 0x000000AC // FIFO 3 status register +#define ADC_O_TMLB 0x00000100 // Test mode loopback register + +//***************************************************************************** +// +// The following define the offsets of the ADC sequence registers. +// +//***************************************************************************** +#define ADC_O_SEQ 0x00000040 // Offset to the first sequence +#define ADC_O_SEQ_STEP 0x00000020 // Increment to the next sequence +#define ADC_O_X_SSMUX 0x00000000 // Multiplexer select register +#define ADC_O_X_SSCTL 0x00000004 // Sample sequence control register +#define ADC_O_X_SSFIFO 0x00000008 // Result FIFO register +#define ADC_O_X_SSFSTAT 0x0000000C // FIFO status register + +//***************************************************************************** +// +// The following define the bit fields in the ADC_ACTSS register. +// +//***************************************************************************** +#define ADC_ACTSS_ASEN3 0x00000008 // Sample sequence 3 enable +#define ADC_ACTSS_ASEN2 0x00000004 // Sample sequence 2 enable +#define ADC_ACTSS_ASEN1 0x00000002 // Sample sequence 1 enable +#define ADC_ACTSS_ASEN0 0x00000001 // Sample sequence 0 enable + +//***************************************************************************** +// +// The following define the bit fields in the ADC_RIS register. +// +//***************************************************************************** +#define ADC_RIS_INR3 0x00000008 // Sample sequence 3 interrupt +#define ADC_RIS_INR2 0x00000004 // Sample sequence 2 interrupt +#define ADC_RIS_INR1 0x00000002 // Sample sequence 1 interrupt +#define ADC_RIS_INR0 0x00000001 // Sample sequence 0 interrupt + +//***************************************************************************** +// +// The following define the bit fields in the ADC_IM register. +// +//***************************************************************************** +#define ADC_IM_MASK3 0x00000008 // Sample sequence 3 mask +#define ADC_IM_MASK2 0x00000004 // Sample sequence 2 mask +#define ADC_IM_MASK1 0x00000002 // Sample sequence 1 mask +#define ADC_IM_MASK0 0x00000001 // Sample sequence 0 mask + +//***************************************************************************** +// +// The following define the bit fields in the ADC_ISC register. +// +//***************************************************************************** +#define ADC_ISC_IN3 0x00000008 // Sample sequence 3 interrupt +#define ADC_ISC_IN2 0x00000004 // Sample sequence 2 interrupt +#define ADC_ISC_IN1 0x00000002 // Sample sequence 1 interrupt +#define ADC_ISC_IN0 0x00000001 // Sample sequence 0 interrupt + +//***************************************************************************** +// +// The following define the bit fields in the ADC_OSTAT register. +// +//***************************************************************************** +#define ADC_OSTAT_OV3 0x00000008 // Sample sequence 3 overflow +#define ADC_OSTAT_OV2 0x00000004 // Sample sequence 2 overflow +#define ADC_OSTAT_OV1 0x00000002 // Sample sequence 1 overflow +#define ADC_OSTAT_OV0 0x00000001 // Sample sequence 0 overflow + +//***************************************************************************** +// +// The following define the bit fields in the ADC_EMUX register. +// +//***************************************************************************** +#define ADC_EMUX_EM3_MASK 0x0000F000 // Event mux 3 mask +#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor event +#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog comparator 0 event +#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog comparator 1 event +#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog comparator 2 event +#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External event +#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer event +#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0 event +#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1 event +#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2 event +#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always event +#define ADC_EMUX_EM2_MASK 0x00000F00 // Event mux 2 mask +#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor event +#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog comparator 0 event +#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog comparator 1 event +#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog comparator 2 event +#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External event +#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer event +#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0 event +#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1 event +#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2 event +#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always event +#define ADC_EMUX_EM1_MASK 0x000000F0 // Event mux 1 mask +#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor event +#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog comparator 0 event +#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog comparator 1 event +#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog comparator 2 event +#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External event +#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer event +#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0 event +#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1 event +#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2 event +#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always event +#define ADC_EMUX_EM0_MASK 0x0000000F // Event mux 0 mask +#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor event +#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog comparator 0 event +#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog comparator 1 event +#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog comparator 2 event +#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External event +#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer event +#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0 event +#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1 event +#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2 event +#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always event +#define ADC_EMUX_EM0_SHIFT 0 // The shift for the first event +#define ADC_EMUX_EM1_SHIFT 4 // The shift for the second event +#define ADC_EMUX_EM2_SHIFT 8 // The shift for the third event +#define ADC_EMUX_EM3_SHIFT 12 // The shift for the fourth event + +//***************************************************************************** +// +// The following define the bit fields in the ADC_USTAT register. +// +//***************************************************************************** +#define ADC_USTAT_UV3 0x00000008 // Sample sequence 3 underflow +#define ADC_USTAT_UV2 0x00000004 // Sample sequence 2 underflow +#define ADC_USTAT_UV1 0x00000002 // Sample sequence 1 underflow +#define ADC_USTAT_UV0 0x00000001 // Sample sequence 0 underflow + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SSPRI register. +// +//***************************************************************************** +#define ADC_SSPRI_SS3_MASK 0x00003000 // Sequencer 3 priority mask +#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority +#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority +#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority +#define ADC_SSPRI_SS2_MASK 0x00000300 // Sequencer 2 priority mask +#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority +#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority +#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority +#define ADC_SSPRI_SS1_MASK 0x00000030 // Sequencer 1 priority mask +#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority +#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority +#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority +#define ADC_SSPRI_SS0_MASK 0x00000003 // Sequencer 0 priority mask +#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority +#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority +#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority + +//***************************************************************************** +// +// The following define the bit fields in the ADC_PSSI register. +// +//***************************************************************************** +#define ADC_PSSI_SS3 0x00000008 // Trigger sample sequencer 3 +#define ADC_PSSI_SS2 0x00000004 // Trigger sample sequencer 2 +#define ADC_PSSI_SS1 0x00000002 // Trigger sample sequencer 1 +#define ADC_PSSI_SS0 0x00000001 // Trigger sample sequencer 0 + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SAC register. +// +//***************************************************************************** +#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling +#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling +#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling +#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling +#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling +#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling +#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SSMUX0, ADC_SSMUX1, +// ADC_SSMUX2, and ADC_SSMUX3 registers. Not all fields are present in all +// registers. +// +//***************************************************************************** +#define ADC_SSMUX_MUX7_MASK 0x70000000 // 8th mux select mask +#define ADC_SSMUX_MUX6_MASK 0x07000000 // 7th mux select mask +#define ADC_SSMUX_MUX5_MASK 0x00700000 // 6th mux select mask +#define ADC_SSMUX_MUX4_MASK 0x00070000 // 5th mux select mask +#define ADC_SSMUX_MUX3_MASK 0x00007000 // 4th mux select mask +#define ADC_SSMUX_MUX2_MASK 0x00000700 // 3rd mux select mask +#define ADC_SSMUX_MUX1_MASK 0x00000070 // 2nd mux select mask +#define ADC_SSMUX_MUX0_MASK 0x00000007 // 1st mux select mask +#define ADC_SSMUX_MUX7_SHIFT 28 +#define ADC_SSMUX_MUX6_SHIFT 24 +#define ADC_SSMUX_MUX5_SHIFT 20 +#define ADC_SSMUX_MUX4_SHIFT 16 +#define ADC_SSMUX_MUX3_SHIFT 12 +#define ADC_SSMUX_MUX2_SHIFT 8 +#define ADC_SSMUX_MUX1_SHIFT 4 +#define ADC_SSMUX_MUX0_SHIFT 0 + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SSCTL0, ADC_SSCTL1, +// ADC_SSCTL2, and ADC_SSCTL3 registers. Not all fields are present in all +// registers. +// +//***************************************************************************** +#define ADC_SSCTL_TS7 0x80000000 // 8th temperature sensor select +#define ADC_SSCTL_IE7 0x40000000 // 8th interrupt enable +#define ADC_SSCTL_END7 0x20000000 // 8th sequence end select +#define ADC_SSCTL_D7 0x10000000 // 8th differential select +#define ADC_SSCTL_TS6 0x08000000 // 7th temperature sensor select +#define ADC_SSCTL_IE6 0x04000000 // 7th interrupt enable +#define ADC_SSCTL_END6 0x02000000 // 7th sequence end select +#define ADC_SSCTL_D6 0x01000000 // 7th differential select +#define ADC_SSCTL_TS5 0x00800000 // 6th temperature sensor select +#define ADC_SSCTL_IE5 0x00400000 // 6th interrupt enable +#define ADC_SSCTL_END5 0x00200000 // 6th sequence end select +#define ADC_SSCTL_D5 0x00100000 // 6th differential select +#define ADC_SSCTL_TS4 0x00080000 // 5th temperature sensor select +#define ADC_SSCTL_IE4 0x00040000 // 5th interrupt enable +#define ADC_SSCTL_END4 0x00020000 // 5th sequence end select +#define ADC_SSCTL_D4 0x00010000 // 5th differential select +#define ADC_SSCTL_TS3 0x00008000 // 4th temperature sensor select +#define ADC_SSCTL_IE3 0x00004000 // 4th interrupt enable +#define ADC_SSCTL_END3 0x00002000 // 4th sequence end select +#define ADC_SSCTL_D3 0x00001000 // 4th differential select +#define ADC_SSCTL_TS2 0x00000800 // 3rd temperature sensor select +#define ADC_SSCTL_IE2 0x00000400 // 3rd interrupt enable +#define ADC_SSCTL_END2 0x00000200 // 3rd sequence end select +#define ADC_SSCTL_D2 0x00000100 // 3rd differential select +#define ADC_SSCTL_TS1 0x00000080 // 2nd temperature sensor select +#define ADC_SSCTL_IE1 0x00000040 // 2nd interrupt enable +#define ADC_SSCTL_END1 0x00000020 // 2nd sequence end select +#define ADC_SSCTL_D1 0x00000010 // 2nd differential select +#define ADC_SSCTL_TS0 0x00000008 // 1st temperature sensor select +#define ADC_SSCTL_IE0 0x00000004 // 1st interrupt enable +#define ADC_SSCTL_END0 0x00000002 // 1st sequence end select +#define ADC_SSCTL_D0 0x00000001 // 1st differential select + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SSFIFO0, ADC_SSFIFO1, +// ADC_SSFIFO2, and ADC_SSFIFO3 registers. +// +//***************************************************************************** +#define ADC_SSFIFO_DATA_MASK 0x000003FF // Sample data +#define ADC_SSFIFO_DATA_SHIFT 0 + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SSFSTAT0, ADC_SSFSTAT1, +// ADC_SSFSTAT2, and ADC_SSFSTAT3 registers. +// +//***************************************************************************** +#define ADC_SSFSTAT_FULL 0x00001000 // FIFO is full +#define ADC_SSFSTAT_EMPTY 0x00000100 // FIFO is empty +#define ADC_SSFSTAT_HPTR 0x000000F0 // FIFO head pointer +#define ADC_SSFSTAT_TPTR 0x0000000F // FIFO tail pointer + +//***************************************************************************** +// +// The following define the bit fields in the ADC_TMLB register. +// +//***************************************************************************** +#define ADC_TMLB_LB 0x00000001 // Loopback control signals + +//***************************************************************************** +// +// The following define the bit fields in the loopback ADC data. +// +//***************************************************************************** +#define ADC_LB_CNT_MASK 0x000003C0 // Sample counter mask +#define ADC_LB_CONT 0x00000020 // Continuation sample +#define ADC_LB_DIFF 0x00000010 // Differential sample +#define ADC_LB_TS 0x00000008 // Temperature sensor sample +#define ADC_LB_MUX_MASK 0x00000007 // Input channel number mask +#define ADC_LB_CNT_SHIFT 6 // Sample counter shift +#define ADC_LB_MUX_SHIFT 0 // Input channel number shift + +#endif // __HW_ADC_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_comp.h b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_comp.h new file mode 100644 index 000000000..991b7a083 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_comp.h @@ -0,0 +1,118 @@ +//***************************************************************************** +// +// hw_comp.h - Macros used when accessing the comparator hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_COMP_H__ +#define __HW_COMP_H__ + +//***************************************************************************** +// +// The following define the offsets of the comparator registers. +// +//***************************************************************************** +#define COMP_O_MIS 0x00000000 // Interrupt status register +#define COMP_O_RIS 0x00000004 // Raw interrupt status register +#define COMP_O_INTEN 0x00000008 // Interrupt enable register +#define COMP_O_REFCTL 0x00000010 // Reference voltage control reg. +#define COMP_O_ACSTAT0 0x00000020 // Comp0 status register +#define COMP_O_ACCTL0 0x00000024 // Comp0 control register +#define COMP_O_ACSTAT1 0x00000040 // Comp1 status register +#define COMP_O_ACCTL1 0x00000044 // Comp1 control register +#define COMP_O_ACSTAT2 0x00000060 // Comp2 status register +#define COMP_O_ACCTL2 0x00000064 // Comp2 control register + +//***************************************************************************** +// +// The following define the bit fields in the COMP_MIS, COMP_RIS, and +// COMP_INTEN registers. +// +//***************************************************************************** +#define COMP_INT_2 0x00000004 // Comp2 interrupt +#define COMP_INT_1 0x00000002 // Comp1 interrupt +#define COMP_INT_0 0x00000001 // Comp0 interrupt + +//***************************************************************************** +// +// The following define the bit fields in the COMP_REFCTL register. +// +//***************************************************************************** +#define COMP_REFCTL_EN 0x00000200 // Reference voltage enable +#define COMP_REFCTL_RNG 0x00000100 // Reference voltage range +#define COMP_REFCTL_VREF_MASK 0x0000000F // Reference voltage select mask +#define COMP_REFCTL_VREF_SHIFT 0 + +//***************************************************************************** +// +// The following define the bit fields in the COMP_ACSTAT0, COMP_ACSTAT1, and +// COMP_ACSTAT2 registers. +// +//***************************************************************************** +#define COMP_ACSTAT_OVAL 0x00000002 // Comparator output value + +//***************************************************************************** +// +// The following define the bit fields in the COMP_ACCTL0, COMP_ACCTL1, and +// COMP_ACCTL2 registers. +// +//***************************************************************************** +#define COMP_ACCTL_TMASK 0x00000800 // Trigger enable +#define COMP_ACCTL_ASRCP_MASK 0x00000600 // Vin+ source select mask +#define COMP_ACCTL_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin +#define COMP_ACCTL_ASRCP_PIN0 0x00000200 // Comp0+ pin +#define COMP_ACCTL_ASRCP_REF 0x00000400 // Internal voltage reference +#define COMP_ACCTL_ASRCP_RES 0x00000600 // Reserved +#define COMP_ACCTL_OEN 0x00000100 // Comparator output enable +#define COMP_ACCTL_TSVAL 0x00000080 // Trigger polarity select +#define COMP_ACCTL_TSEN_MASK 0x00000060 // Trigger sense mask +#define COMP_ACCTL_TSEN_LEVEL 0x00000000 // Trigger is level sense +#define COMP_ACCTL_TSEN_FALL 0x00000020 // Trigger is falling edge +#define COMP_ACCTL_TSEN_RISE 0x00000040 // Trigger is rising edge +#define COMP_ACCTL_TSEN_BOTH 0x00000060 // Trigger is both edges +#define COMP_ACCTL_ISLVAL 0x00000010 // Interrupt polarity select +#define COMP_ACCTL_ISEN_MASK 0x0000000C // Interrupt sense mask +#define COMP_ACCTL_ISEN_LEVEL 0x00000000 // Interrupt is level sense +#define COMP_ACCTL_ISEN_FALL 0x00000004 // Interrupt is falling edge +#define COMP_ACCTL_ISEN_RISE 0x00000008 // Interrupt is rising edge +#define COMP_ACCTL_ISEN_BOTH 0x0000000C // Interrupt is both edges +#define COMP_ACCTL_CINV 0x00000002 // Comparator output invert + +//***************************************************************************** +// +// The following define the reset values for the comparator registers. +// +//***************************************************************************** +#define COMP_RV_MIS 0x00000000 // Interrupt status register +#define COMP_RV_RIS 0x00000000 // Raw interrupt status register +#define COMP_RV_INTEN 0x00000000 // Interrupt enable register +#define COMP_RV_REFCTL 0x00000000 // Reference voltage control reg. +#define COMP_RV_ACSTAT0 0x00000000 // Comp0 status register +#define COMP_RV_ACCTL0 0x00000000 // Comp0 control register +#define COMP_RV_ACSTAT1 0x00000000 // Comp1 status register +#define COMP_RV_ACCTL1 0x00000000 // Comp1 control register +#define COMP_RV_ACSTAT2 0x00000000 // Comp2 status register +#define COMP_RV_ACCTL2 0x00000000 // Comp2 control register + +#endif // __HW_COMP_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_flash.h b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_flash.h new file mode 100644 index 000000000..53128b436 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_flash.h @@ -0,0 +1,139 @@ +//***************************************************************************** +// +// hw_flash.h - Macros used when accessing the flash controller. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_FLASH_H__ +#define __HW_FLASH_H__ + +//***************************************************************************** +// +// The following define the offsets of the FLASH registers. +// +//***************************************************************************** +#define FLASH_FMA 0x400FD000 // Memory address register +#define FLASH_FMD 0x400FD004 // Memory data register +#define FLASH_FMC 0x400FD008 // Memory control register +#define FLASH_FCRIS 0x400FD00c // Raw interrupt status register +#define FLASH_FCIM 0x400FD010 // Interrupt mask register +#define FLASH_FCMISC 0x400FD014 // Interrupt status register +#define FLASH_FMPRE 0x400FE130 // FLASH read protect register +#define FLASH_FMPPE 0x400FE134 // FLASH program protect register +#define FLASH_USECRL 0x400FE140 // uSec reload register + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FMC register. +// +//***************************************************************************** +#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask +#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key +#define FLASH_FMC_COMT 0x00000008 // Commit user register +#define FLASH_FMC_MERASE 0x00000004 // Mass erase FLASH +#define FLASH_FMC_ERASE 0x00000002 // Erase FLASH page +#define FLASH_FMC_WRITE 0x00000001 // Write FLASH word + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FCRIS register. +// +//***************************************************************************** +#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status +#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FCIM register. +// +//***************************************************************************** +#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask +#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FMIS register. +// +//***************************************************************************** +#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status +#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FMPRE and FLASH_FMPPE +// registers. +// +//***************************************************************************** +#define FLASH_FMP_BLOCK_31 0x80000000 // Enable for block 31 +#define FLASH_FMP_BLOCK_30 0x40000000 // Enable for block 30 +#define FLASH_FMP_BLOCK_29 0x20000000 // Enable for block 29 +#define FLASH_FMP_BLOCK_28 0x10000000 // Enable for block 28 +#define FLASH_FMP_BLOCK_27 0x08000000 // Enable for block 27 +#define FLASH_FMP_BLOCK_26 0x04000000 // Enable for block 26 +#define FLASH_FMP_BLOCK_25 0x02000000 // Enable for block 25 +#define FLASH_FMP_BLOCK_24 0x01000000 // Enable for block 24 +#define FLASH_FMP_BLOCK_23 0x00800000 // Enable for block 23 +#define FLASH_FMP_BLOCK_22 0x00400000 // Enable for block 22 +#define FLASH_FMP_BLOCK_21 0x00200000 // Enable for block 21 +#define FLASH_FMP_BLOCK_20 0x00100000 // Enable for block 20 +#define FLASH_FMP_BLOCK_19 0x00080000 // Enable for block 19 +#define FLASH_FMP_BLOCK_18 0x00040000 // Enable for block 18 +#define FLASH_FMP_BLOCK_17 0x00020000 // Enable for block 17 +#define FLASH_FMP_BLOCK_16 0x00010000 // Enable for block 16 +#define FLASH_FMP_BLOCK_15 0x00008000 // Enable for block 15 +#define FLASH_FMP_BLOCK_14 0x00004000 // Enable for block 14 +#define FLASH_FMP_BLOCK_13 0x00002000 // Enable for block 13 +#define FLASH_FMP_BLOCK_12 0x00001000 // Enable for block 12 +#define FLASH_FMP_BLOCK_11 0x00000800 // Enable for block 11 +#define FLASH_FMP_BLOCK_10 0x00000400 // Enable for block 10 +#define FLASH_FMP_BLOCK_9 0x00000200 // Enable for block 9 +#define FLASH_FMP_BLOCK_8 0x00000100 // Enable for block 8 +#define FLASH_FMP_BLOCK_7 0x00000080 // Enable for block 7 +#define FLASH_FMP_BLOCK_6 0x00000040 // Enable for block 6 +#define FLASH_FMP_BLOCK_5 0x00000020 // Enable for block 5 +#define FLASH_FMP_BLOCK_4 0x00000010 // Enable for block 4 +#define FLASH_FMP_BLOCK_3 0x00000008 // Enable for block 3 +#define FLASH_FMP_BLOCK_2 0x00000004 // Enable for block 2 +#define FLASH_FMP_BLOCK_1 0x00000002 // Enable for block 1 +#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0 + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_USECRL register. +// +//***************************************************************************** +#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec +#define FLASH_USECRL_SHIFT 0 + +//***************************************************************************** +// +// The erase size is the size of the FLASH block that is erased by an erase +// operation, and the protect size is the size of the FLASH block that is +// protected by each protection register. +// +//***************************************************************************** +#define FLASH_ERASE_SIZE 0x00000400 +#define FLASH_PROTECT_SIZE 0x00000800 + +#endif // __HW_FLASH_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_gpio.h b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_gpio.h new file mode 100644 index 000000000..bf25d3f5a --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_gpio.h @@ -0,0 +1,103 @@ +//***************************************************************************** +// +// hw_gpio.h - Defines and Macros for GPIO hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_GPIO_H__ +#define __HW_GPIO_H__ + +//***************************************************************************** +// +// GPIO Register Offsets. +// +//***************************************************************************** +#define GPIO_O_DATA 0x00000000 // Data register. +#define GPIO_O_DIR 0x00000400 // Data direction register. +#define GPIO_O_IS 0x00000404 // Interrupt sense register. +#define GPIO_O_IBE 0x00000408 // Interrupt both edges register. +#define GPIO_O_IEV 0x0000040C // Intterupt event register. +#define GPIO_O_IM 0x00000410 // Interrupt mask register. +#define GPIO_O_RIS 0x00000414 // Raw interrupt status register. +#define GPIO_O_MIS 0x00000418 // Masked interrupt status reg. +#define GPIO_O_ICR 0x0000041C // Interrupt clear register. +#define GPIO_O_AFSEL 0x00000420 // Mode control select register. +#define GPIO_O_DR2R 0x00000500 // 2ma drive select register. +#define GPIO_O_DR4R 0x00000504 // 4ma drive select register. +#define GPIO_O_DR8R 0x00000508 // 8ma drive select register. +#define GPIO_O_ODR 0x0000050C // Open drain select register. +#define GPIO_O_PUR 0x00000510 // Pull up select register. +#define GPIO_O_PDR 0x00000514 // Pull down select register. +#define GPIO_O_SLR 0x00000518 // Slew rate control enable reg. +#define GPIO_O_DEN 0x0000051C // Digital input enable register. +#define GPIO_O_PeriphID4 0x00000FD0 // +#define GPIO_O_PeriphID5 0x00000FD4 // +#define GPIO_O_PeriphID6 0x00000FD8 // +#define GPIO_O_PeriphID7 0x00000FDC // +#define GPIO_O_PeriphID0 0x00000FE0 // +#define GPIO_O_PeriphID1 0x00000FE4 // +#define GPIO_O_PeriphID2 0x00000FE8 // +#define GPIO_O_PeriphID3 0x00000FEC // +#define GPIO_O_PCellID0 0x00000FF0 // +#define GPIO_O_PCellID1 0x00000FF4 // +#define GPIO_O_PCellID2 0x00000FF8 // +#define GPIO_O_PCellID3 0x00000FFC // + +//***************************************************************************** +// +// GPIO Register reset values. +// +//***************************************************************************** +#define GPIO_RV_DATA 0x00000000 // Data register reset value. +#define GPIO_RV_DIR 0x00000000 // Data direction reg RV. +#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV. +#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV. +#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV. +#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV. +#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV. +#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV. +#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV. +#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV. +#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV. +#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV. +#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV. +#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV. +#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV. +#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV. +#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV. +#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV. +#define GPIO_RV_PeriphID4 0x00000000 // +#define GPIO_RV_PeriphID5 0x00000000 // +#define GPIO_RV_PeriphID6 0x00000000 // +#define GPIO_RV_PeriphID7 0x00000000 // +#define GPIO_RV_PeriphID0 0x00000061 // +#define GPIO_RV_PeriphID1 0x00000010 // +#define GPIO_RV_PeriphID2 0x00000004 // +#define GPIO_RV_PeriphID3 0x00000000 // +#define GPIO_RV_PCellID0 0x0000000D // +#define GPIO_RV_PCellID1 0x000000F0 // +#define GPIO_RV_PCellID2 0x00000005 // +#define GPIO_RV_PCellID3 0x000000B1 // + +#endif // __HW_GPIO_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_i2c.h b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_i2c.h new file mode 100644 index 000000000..2c9f46dab --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_i2c.h @@ -0,0 +1,197 @@ +//***************************************************************************** +// +// hw_i2c.h - Macros used when accessing the I2C master and slave hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_I2C_H__ +#define __HW_I2C_H__ + +//***************************************************************************** +// +// The following defines the offset between the I2C master and slave registers. +// +//***************************************************************************** +#define I2C_O_SLAVE 0x00000800 // Offset from master to slave + +//***************************************************************************** +// +// The following define the offsets of the I2C master registers. +// +//***************************************************************************** +#define I2C_MASTER_O_SA 0x00000000 // Slave address register +#define I2C_MASTER_O_CS 0x00000004 // Control and Status register +#define I2C_MASTER_O_DR 0x00000008 // Data register +#define I2C_MASTER_O_TPR 0x0000000C // Timer period register +#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register +#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register +#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg +#define I2C_MASTER_O_MICR 0x0000001c // Interrupt clear register +#define I2C_MASTER_O_CR 0x00000020 // Configuration register + +//***************************************************************************** +// +// The following define the offsets of the I2C slave registers. +// +//***************************************************************************** +#define I2C_SLAVE_O_OAR 0x00000000 // Own address register +#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register +#define I2C_SLAVE_O_DR 0x00000008 // Data register +#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register +#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register +#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg +#define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register + +//***************************************************************************** +// +// The followng define the bit fields in the I2C master slave address register. +// +//***************************************************************************** +#define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address +#define I2C_MASTER_SA_RS 0x00000001 // Receive/send +#define I2C_MASTER_SA_SA_SHIFT 1 + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Control and Status +// register. +// +//***************************************************************************** +#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde +#define I2C_MASTER_CS_STOP 0x00000004 // Stop +#define I2C_MASTER_CS_START 0x00000002 // Start +#define I2C_MASTER_CS_RUN 0x00000001 // Run +#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy +#define I2C_MASTER_CS_IDLE 0x00000020 // Idle +#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration +#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged +#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged +#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred +#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data +#define I2C_MASTER_CS_ERR_MASK 0x0000001C + +//***************************************************************************** +// +// The following define values used in determining the contents of the I2C +// Master Timer Period register. +// +//***************************************************************************** +#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period +#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period +#define I2C_MASTER_TPR_SCL (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP) +#define I2C_SCL_STANDARD 100000 // SCL standard frequency +#define I2C_SCL_FAST 400000 // SCL fast frequency + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Interrupt Mask +// register. +// +//***************************************************************************** +#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Raw Interrupt Status +// register. +// +//***************************************************************************** +#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Masked Interrupt +// Status register. +// +//***************************************************************************** +#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Interrupt Clear +// register. +// +//***************************************************************************** +#define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Configuration +// register. +// +//***************************************************************************** +#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable +#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable +#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Own Address register. +// +//***************************************************************************** +#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Control/Status +// register. +// +//***************************************************************************** +#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device +#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received +#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Interrupt Mask +// register. +// +//***************************************************************************** +#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Raw Interrupt Status +// register. +// +//***************************************************************************** +#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Masked Interrupt +// Status register. +// +//***************************************************************************** +#define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Interrupt Clear +// register. +// +//***************************************************************************** +#define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear + +#endif // __HW_I2C_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_ints.h b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_ints.h new file mode 100644 index 000000000..2204a2c07 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_ints.h @@ -0,0 +1,97 @@ +//***************************************************************************** +// +// hw_ints.h - Macros that define the interrupt assignment on Stellaris. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_INTS_H__ +#define __HW_INTS_H__ + +//***************************************************************************** +// +// The following define the fault assignments. +// +//***************************************************************************** +#define FAULT_NMI 2 // NMI fault +#define FAULT_HARD 3 // Hard fault +#define FAULT_MPU 4 // MPU fault +#define FAULT_BUS 5 // Bus fault +#define FAULT_USAGE 6 // Usage fault +#define FAULT_SVCALL 11 // SVCall +#define FAULT_DEBUG 12 // Debug monitor +#define FAULT_PENDSV 14 // PendSV +#define FAULT_SYSTICK 15 // System Tick + +//***************************************************************************** +// +// The following define the interrupt assignments. +// +//***************************************************************************** +#define INT_GPIOA 16 // GPIO Port A +#define INT_GPIOB 17 // GPIO Port B +#define INT_GPIOC 18 // GPIO Port C +#define INT_GPIOD 19 // GPIO Port D +#define INT_GPIOE 20 // GPIO Port E +#define INT_UART0 21 // UART0 Rx and Tx +#define INT_UART1 22 // UART1 Rx and Tx +#define INT_SSI 23 // SSI Rx and Tx +#define INT_I2C 24 // I2C Master and Slave +#define INT_PWM_FAULT 25 // PWM Fault +#define INT_PWM0 26 // PWM Generator 0 +#define INT_PWM1 27 // PWM Generator 1 +#define INT_PWM2 28 // PWM Generator 2 +#define INT_QEI 29 // Quadrature Encoder +#define INT_ADC0 30 // ADC Sequence 0 +#define INT_ADC1 31 // ADC Sequence 1 +#define INT_ADC2 32 // ADC Sequence 2 +#define INT_ADC3 33 // ADC Sequence 3 +#define INT_WATCHDOG 34 // Watchdog timer +#define INT_TIMER0A 35 // Timer 0 subtimer A +#define INT_TIMER0B 36 // Timer 0 subtimer B +#define INT_TIMER1A 37 // Timer 1 subtimer A +#define INT_TIMER1B 38 // Timer 1 subtimer B +#define INT_TIMER2A 39 // Timer 2 subtimer A +#define INT_TIMER2B 40 // Timer 2 subtimer B +#define INT_COMP0 41 // Analog Comparator 0 +#define INT_COMP1 42 // Analog Comparator 1 +#define INT_COMP2 43 // Analog Comparator 2 +#define INT_SYSCTL 44 // System Control (PLL, OSC, BO) +#define INT_FLASH 45 // FLASH Control + +//***************************************************************************** +// +// The total number of interrupts. +// +//***************************************************************************** +#define NUM_INTERRUPTS 46 + +//***************************************************************************** +// +// The total number of priority levels. +// +//***************************************************************************** +#define NUM_PRIORITY 8 +#define NUM_PRIORITY_BITS 3 + +#endif // __HW_INTS_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_memmap.h b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_memmap.h new file mode 100644 index 000000000..2b11f3513 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_memmap.h @@ -0,0 +1,64 @@ +//***************************************************************************** +// +// hw_memmap.h - Macros defining the memory map of Stellaris. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_MEMMAP_H__ +#define __HW_MEMMAP_H__ + +//***************************************************************************** +// +// The following define the base address of the memories and peripherals. +// +//***************************************************************************** +#define FLASH_BASE 0x00000000 // FLASH memory +#define SRAM_BASE 0x20000000 // SRAM memory +#define WATCHDOG_BASE 0x40000000 // Watchdog +#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A +#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B +#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C +#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D +#define SSI_BASE 0x40008000 // SSI +#define UART0_BASE 0x4000C000 // UART0 +#define UART1_BASE 0x4000D000 // UART1 +#define I2C_MASTER_BASE 0x40020000 // I2C Master +#define I2C_SLAVE_BASE 0x40020800 // I2C Slave +#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E +#define PWM_BASE 0x40028000 // PWM +#define QEI_BASE 0x4002C000 // QEI +#define TIMER0_BASE 0x40030000 // Timer0 +#define TIMER1_BASE 0x40031000 // Timer1 +#define TIMER2_BASE 0x40032000 // Timer2 +#define ADC_BASE 0x40038000 // ADC +#define COMP_BASE 0x4003C000 // Analog comparators +#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller +#define SYSCTL_BASE 0x400FE000 // System Control +#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell +#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace +#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint +#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl +#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit + +#endif // __HW_MEMMAP_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_nvic.h b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_nvic.h new file mode 100644 index 000000000..6598ef88b --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_nvic.h @@ -0,0 +1,830 @@ +//***************************************************************************** +// +// hw_nvic.h - Macros used when accessing the NVIC hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_NVIC_H__ +#define __HW_NVIC_H__ + +//***************************************************************************** +// +// The following define the addresses of the NVIC registers. +// +//***************************************************************************** +#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg. +#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg. +#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register +#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register +#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg. +#define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register +#define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg. +#define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register +#define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg. +#define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register +#define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register +#define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register +#define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register +#define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register +#define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register +#define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register +#define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register +#define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register +#define NVIC_CPUID 0xE000ED00 // CPUID Base Register +#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register +#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register +#define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg. +#define NVIC_SYS_CTRL 0xE000ED10 // System Control Register +#define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register +#define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority +#define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority +#define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority +#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State +#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg. +#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register +#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register +#define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register +#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register +#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register +#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register +#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register +#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register +#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg. +#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg. +#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select +#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data +#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control +#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg. + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_INT_TYPE register. +// +//***************************************************************************** +#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) +#define NVIC_INT_TYPE_LINES_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_CTRL register. +// +//***************************************************************************** +#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag +#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source +#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable +#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_RELOAD register. +// +//***************************************************************************** +#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value +#define NVIC_ST_RELOAD_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_CURRENT register. +// +//***************************************************************************** +#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value +#define NVIC_ST_CURRENT_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_CAL register. +// +//***************************************************************************** +#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock +#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew +#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value +#define NVIC_ST_CAL_ONEMS_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_EN0 register. +// +//***************************************************************************** +#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable +#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable +#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable +#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable +#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable +#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable +#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable +#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable +#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable +#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable +#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable +#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable +#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable +#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable +#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable +#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable +#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable +#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable +#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable +#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable +#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable +#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable +#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable +#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable +#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable +#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable +#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable +#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable +#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable +#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable +#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable +#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DIS0 register. +// +//***************************************************************************** +#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable +#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable +#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable +#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable +#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable +#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable +#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable +#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable +#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable +#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable +#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable +#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable +#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable +#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable +#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable +#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable +#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable +#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable +#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable +#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable +#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable +#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable +#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable +#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable +#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable +#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable +#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable +#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable +#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable +#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable +#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable +#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PEND0 register. +// +//***************************************************************************** +#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend +#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend +#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend +#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend +#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend +#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend +#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend +#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend +#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend +#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend +#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend +#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend +#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend +#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend +#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend +#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend +#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend +#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend +#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend +#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend +#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend +#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend +#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend +#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend +#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend +#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend +#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend +#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend +#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend +#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend +#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend +#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_UNPEND0 register. +// +//***************************************************************************** +#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend +#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend +#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend +#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend +#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend +#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend +#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend +#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend +#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend +#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend +#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend +#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend +#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend +#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend +#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend +#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend +#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend +#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend +#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend +#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend +#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend +#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend +#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend +#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend +#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend +#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend +#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend +#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend +#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend +#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend +#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend +#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ACTIVE0 register. +// +//***************************************************************************** +#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active +#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active +#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active +#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active +#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active +#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active +#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active +#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active +#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active +#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active +#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active +#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active +#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active +#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active +#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active +#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active +#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active +#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active +#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active +#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active +#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active +#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active +#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active +#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active +#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active +#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active +#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active +#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active +#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active +#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active +#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active +#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI0 register. +// +//***************************************************************************** +#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask +#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask +#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask +#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask +#define NVIC_PRI0_INT3_S 24 +#define NVIC_PRI0_INT2_S 16 +#define NVIC_PRI0_INT1_S 8 +#define NVIC_PRI0_INT0_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI1 register. +// +//***************************************************************************** +#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask +#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask +#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask +#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask +#define NVIC_PRI1_INT7_S 24 +#define NVIC_PRI1_INT6_S 16 +#define NVIC_PRI1_INT5_S 8 +#define NVIC_PRI1_INT4_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI2 register. +// +//***************************************************************************** +#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask +#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask +#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask +#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask +#define NVIC_PRI2_INT11_S 24 +#define NVIC_PRI2_INT10_S 16 +#define NVIC_PRI2_INT9_S 8 +#define NVIC_PRI2_INT8_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI3 register. +// +//***************************************************************************** +#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask +#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask +#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask +#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask +#define NVIC_PRI3_INT15_S 24 +#define NVIC_PRI3_INT14_S 16 +#define NVIC_PRI3_INT13_S 8 +#define NVIC_PRI3_INT12_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI4 register. +// +//***************************************************************************** +#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask +#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask +#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask +#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask +#define NVIC_PRI4_INT19_S 24 +#define NVIC_PRI4_INT18_S 16 +#define NVIC_PRI4_INT17_S 8 +#define NVIC_PRI4_INT16_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI5 register. +// +//***************************************************************************** +#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask +#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask +#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask +#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask +#define NVIC_PRI5_INT23_S 24 +#define NVIC_PRI5_INT22_S 16 +#define NVIC_PRI5_INT21_S 8 +#define NVIC_PRI5_INT20_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI6 register. +// +//***************************************************************************** +#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask +#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask +#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask +#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask +#define NVIC_PRI6_INT27_S 24 +#define NVIC_PRI6_INT26_S 16 +#define NVIC_PRI6_INT25_S 8 +#define NVIC_PRI6_INT24_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI7 register. +// +//***************************************************************************** +#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask +#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask +#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask +#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask +#define NVIC_PRI7_INT31_S 24 +#define NVIC_PRI7_INT30_S 16 +#define NVIC_PRI7_INT29_S 8 +#define NVIC_PRI7_INT28_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_CPUID register. +// +//***************************************************************************** +#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer +#define NVIC_CPUID_VAR_M 0x00F00000 // Variant +#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number +#define NVIC_CPUID_REV_M 0x0000000F // Revision + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_INT_CTRL register. +// +//***************************************************************************** +#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI +#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV +#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV +#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling +#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending +#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception +#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base +#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception +#define NVIC_INT_CTRL_VEC_PEN_S 12 +#define NVIC_INT_CTRL_VEC_ACT_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_VTABLE register. +// +//***************************************************************************** +#define NVIC_VTABLE_BASE 0x20000000 // Vector table base +#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset +#define NVIC_VTABLE_OFFSET_S 8 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_APINT register. +// +//***************************************************************************** +#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask +#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key +#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess +#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group +#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split +#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split +#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split +#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split +#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split +#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split +#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split +#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split +#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request +#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info +#define NVIC_APINT_VECT_RESET 0x00000001 // System reset + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend +#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable +#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_CFG_CTRL register. +// +//***************************************************************************** +#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault +#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0 +#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access +#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger +#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger +#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_PRI1 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler +#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler +#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler +#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler +#define NVIC_SYS_PRI1_USAGE_S 16 +#define NVIC_SYS_PRI1_BUS_S 8 +#define NVIC_SYS_PRI1_MEM_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_PRI2 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler +#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers +#define NVIC_SYS_PRI2_SVC_S 24 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_PRI3 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler +#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler +#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler +#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler +#define NVIC_SYS_PRI3_TICK_S 24 +#define NVIC_SYS_PRI3_PENDSV_S 16 +#define NVIC_SYS_PRI3_DEBUG_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_HND_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable +#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable +#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable +#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended +#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended +#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active +#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active +#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active +#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active +#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active +#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active +#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_FAULT_STAT register. +// +//***************************************************************************** +#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault +#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault +#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault +#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault +#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault +#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault +#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid +#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault +#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault +#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error +#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error +#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault +#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid +#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation +#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation +#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation +#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_HFAULT_STAT register. +// +//***************************************************************************** +#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event +#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler +#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DEBUG_STAT register. +// +//***************************************************************************** +#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted +#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch +#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match +#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction +#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MM_ADDR register. +// +//***************************************************************************** +#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address +#define NVIC_MM_ADDR_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_FAULT_ADDR register. +// +//***************************************************************************** +#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address +#define NVIC_FAULT_ADDR_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_EXC_STACK register. +// +//***************************************************************************** +#define NVIC_EXC_STACK_DEEP 0x00000001 // Exception stack + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_EXC_NUM register. +// +//***************************************************************************** +#define NVIC_EXC_NUM_M 0x000003FF // Exception number +#define NVIC_EXC_NUM_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_COPRO register. +// +//***************************************************************************** +#define NVIC_COPRO_15_M 0xC0000000 // Coprocessor 15 access mask +#define NVIC_COPRO_15_DENIED 0x00000000 // Coprocessor 15 access denied +#define NVIC_COPRO_15_PRIV 0x40000000 // Coprocessor 15 privileged addess +#define NVIC_COPRO_15_FULL 0xC0000000 // Coprocessor 15 full access +#define NVIC_COPRO_14_M 0x30000000 // Coprocessor 14 access mask +#define NVIC_COPRO_14_DENIED 0x00000000 // Coprocessor 14 access denied +#define NVIC_COPRO_14_PRIV 0x10000000 // Coprocessor 14 privileged addess +#define NVIC_COPRO_14_FULL 0x30000000 // Coprocessor 14 full access +#define NVIC_COPRO_13_M 0x0C000000 // Coprocessor 13 access mask +#define NVIC_COPRO_13_DENIED 0x00000000 // Coprocessor 13 access denied +#define NVIC_COPRO_13_PRIV 0x04000000 // Coprocessor 13 privileged addess +#define NVIC_COPRO_13_FULL 0x0C000000 // Coprocessor 13 full access +#define NVIC_COPRO_12_M 0x03000000 // Coprocessor 12 access mask +#define NVIC_COPRO_12_DENIED 0x00000000 // Coprocessor 12 access denied +#define NVIC_COPRO_12_PRIV 0x01000000 // Coprocessor 12 privileged addess +#define NVIC_COPRO_12_FULL 0x03000000 // Coprocessor 12 full access +#define NVIC_COPRO_11_M 0x00C00000 // Coprocessor 11 access mask +#define NVIC_COPRO_11_DENIED 0x00000000 // Coprocessor 11 access denied +#define NVIC_COPRO_11_PRIV 0x00400000 // Coprocessor 11 privileged addess +#define NVIC_COPRO_11_FULL 0x00C00000 // Coprocessor 11 full access +#define NVIC_COPRO_10_M 0x00300000 // Coprocessor 10 access mask +#define NVIC_COPRO_10_DENIED 0x00000000 // Coprocessor 10 access denied +#define NVIC_COPRO_10_PRIV 0x00100000 // Coprocessor 10 privileged addess +#define NVIC_COPRO_10_FULL 0x00300000 // Coprocessor 10 full access +#define NVIC_COPRO_9_M 0x000C0000 // Coprocessor 9 access mask +#define NVIC_COPRO_9_DENIED 0x00000000 // Coprocessor 9 access denied +#define NVIC_COPRO_9_PRIV 0x00040000 // Coprocessor 9 privileged addess +#define NVIC_COPRO_9_FULL 0x000C0000 // Coprocessor 9 full access +#define NVIC_COPRO_8_M 0x00030000 // Coprocessor 8 access mask +#define NVIC_COPRO_8_DENIED 0x00000000 // Coprocessor 8 access denied +#define NVIC_COPRO_8_PRIV 0x00010000 // Coprocessor 8 privileged addess +#define NVIC_COPRO_8_FULL 0x00030000 // Coprocessor 8 full access +#define NVIC_COPRO_7_M 0x0000C000 // Coprocessor 7 access mask +#define NVIC_COPRO_7_DENIED 0x00000000 // Coprocessor 7 access denied +#define NVIC_COPRO_7_PRIV 0x00004000 // Coprocessor 7 privileged addess +#define NVIC_COPRO_7_FULL 0x0000C000 // Coprocessor 7 full access +#define NVIC_COPRO_6_M 0x00003000 // Coprocessor 6 access mask +#define NVIC_COPRO_6_DENIED 0x00000000 // Coprocessor 6 access denied +#define NVIC_COPRO_6_PRIV 0x00001000 // Coprocessor 6 privileged addess +#define NVIC_COPRO_6_FULL 0x00003000 // Coprocessor 6 full access +#define NVIC_COPRO_5_M 0x00000C00 // Coprocessor 5 access mask +#define NVIC_COPRO_5_DENIED 0x00000000 // Coprocessor 5 access denied +#define NVIC_COPRO_5_PRIV 0x00000400 // Coprocessor 5 privileged addess +#define NVIC_COPRO_5_FULL 0x00000C00 // Coprocessor 5 full access +#define NVIC_COPRO_4_M 0x00000300 // Coprocessor 4 access mask +#define NVIC_COPRO_4_DENIED 0x00000000 // Coprocessor 4 access denied +#define NVIC_COPRO_4_PRIV 0x00000100 // Coprocessor 4 privileged addess +#define NVIC_COPRO_4_FULL 0x00000300 // Coprocessor 4 full access +#define NVIC_COPRO_3_M 0x000000C0 // Coprocessor 3 access mask +#define NVIC_COPRO_3_DENIED 0x00000000 // Coprocessor 3 access denied +#define NVIC_COPRO_3_PRIV 0x00000040 // Coprocessor 3 privileged addess +#define NVIC_COPRO_3_FULL 0x000000C0 // Coprocessor 3 full access +#define NVIC_COPRO_2_M 0x00000030 // Coprocessor 2 access mask +#define NVIC_COPRO_2_DENIED 0x00000000 // Coprocessor 2 access denied +#define NVIC_COPRO_2_PRIV 0x00000010 // Coprocessor 2 privileged addess +#define NVIC_COPRO_2_FULL 0x00000030 // Coprocessor 2 full access +#define NVIC_COPRO_1_M 0x0000000C // Coprocessor 1 access mask +#define NVIC_COPRO_1_DENIED 0x00000000 // Coprocessor 1 access denied +#define NVIC_COPRO_1_PRIV 0x00000004 // Coprocessor 1 privileged addess +#define NVIC_COPRO_1_FULL 0x0000000C // Coprocessor 1 full access +#define NVIC_COPRO_0_M 0x00000003 // Coprocessor 0 access mask +#define NVIC_COPRO_0_DENIED 0x00000000 // Coprocessor 0 access denied +#define NVIC_COPRO_0_PRIV 0x00000001 // Coprocessor 0 privileged addess +#define NVIC_COPRO_0_FULL 0x00000003 // Coprocessor 0 full access + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_TYPE register. +// +//***************************************************************************** +#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions +#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions +#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU +#define NVIC_MPU_TYPE_IREGION_S 16 +#define NVIC_MPU_TYPE_DREGION_S 8 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_CTRL register. +// +//***************************************************************************** +#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults +#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_NUMBER register. +// +//***************************************************************************** +#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access +#define NVIC_MPU_NUMBER_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_BASE register. +// +//***************************************************************************** +#define NVIC_MPU_BASE_ADDR_M 0xFFFFFF00 // Base address +#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid +#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number +#define NVIC_MPU_BASE_ADDR_S 8 +#define NVIC_MPU_BASE_REGION_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_ATTR register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR_ATTRS 0xFFFF0000 // Attributes +#define NVIC_MPU_ATTR_SRD 0x0000FF00 // Sub-region disable +#define NVIC_MPU_ATTR_SZENABLE 0x000000FF // Region size + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_CTRL register. +// +//***************************************************************************** +#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask +#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key +#define NVIC_DBG_CTRL_MON_PEND 0x00008000 // Pend the monitor +#define NVIC_DBG_CTRL_MON_REQ 0x00004000 // Monitor request +#define NVIC_DBG_CTRL_MON_EN 0x00002000 // Debug monitor enable +#define NVIC_DBG_CTRL_MONSTEP 0x00001000 // Monitor step the core +#define NVIC_DBG_CTRL_S_SLEEP 0x00000400 // Core is sleeping +#define NVIC_DBG_CTRL_S_HALT 0x00000200 // Core status on halt +#define NVIC_DBG_CTRL_S_REGRDY 0x00000100 // Register read/write available +#define NVIC_DBG_CTRL_S_LOCKUP 0x00000080 // Core is locked up +#define NVIC_DBG_CTRL_C_RESET 0x00000010 // Reset the core +#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping +#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core +#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core +#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_XFER register. +// +//***************************************************************************** +#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read +#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register +#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 +#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 +#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 +#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 +#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 +#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 +#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 +#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 +#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 +#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 +#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 +#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 +#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 +#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 +#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 +#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 +#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register +#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP +#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP +#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP +#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_DATA register. +// +//***************************************************************************** +#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache +#define NVIC_DBG_DATA_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_INT register. +// +//***************************************************************************** +#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault +#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors +#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error +#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state +#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check +#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error +#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault +#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status +#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset +#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending +#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SW_TRIG register. +// +//***************************************************************************** +#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger +#define NVIC_SW_TRIG_INTID_S 0 + +#endif // __HW_NVIC_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_pwm.h b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_pwm.h new file mode 100644 index 000000000..cc42015ab --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_pwm.h @@ -0,0 +1,260 @@ +//***************************************************************************** +// +// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_PWM_H__ +#define __HW_PWM_H__ + +//***************************************************************************** +// +// PWM Module Register Offsets. +// +//***************************************************************************** +#define PWM_O_CTL 0x00000000 // PWM Master Control register +#define PWM_O_SYNC 0x00000004 // PWM Time Base Sync register +#define PWM_O_ENABLE 0x00000008 // PWM Output Enable register +#define PWM_O_INVERT 0x0000000C // PWM Output Inversion register +#define PWM_O_FAULT 0x00000010 // PWM Output Fault register +#define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable register +#define PWM_O_RIS 0x00000018 // PWM Interrupt Raw Status reg. +#define PWM_O_ISC 0x0000001C // PWM Interrupt Status register +#define PWM_O_STATUS 0x00000020 // PWM Status register + +//***************************************************************************** +// +// The following define the bit fields in the PWM Master Control register. +// +//***************************************************************************** +#define PWM_CTL_GLOBAL_SYNC2 0x00000004 // Global sync generator 2 +#define PWM_CTL_GLOBAL_SYNC1 0x00000002 // Global sync generator 1 +#define PWM_CTL_GLOBAL_SYNC0 0x00000001 // Global sync generator 0 + +//***************************************************************************** +// +// The following define the bit fields in the PWM Time Base Sync register. +// +//***************************************************************************** +#define PWM_SYNC_SYNC2 0x00000004 // Reset generator 2 counter +#define PWM_SYNC_SYNC1 0x00000002 // Reset generator 1 counter +#define PWM_SYNC_SYNC0 0x00000001 // Reset generator 0 counter + +//***************************************************************************** +// +// The following define the bit fields in the PWM Output Enable register. +// +//***************************************************************************** +#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 pin enable +#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 pin enable +#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 pin enable +#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 pin enable +#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 pin enable +#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 pin enable + +//***************************************************************************** +// +// The following define the bit fields in the PWM Inversion register. +// +//***************************************************************************** +#define PWM_INVERT_PWM5INV 0x00000020 // PWM5 pin invert +#define PWM_INVERT_PWM4INV 0x00000010 // PWM4 pin invert +#define PWM_INVERT_PWM3INV 0x00000008 // PWM3 pin invert +#define PWM_INVERT_PWM2INV 0x00000004 // PWM2 pin invert +#define PWM_INVERT_PWM1INV 0x00000002 // PWM1 pin invert +#define PWM_INVERT_PWM0INV 0x00000001 // PWM0 pin invert + +//***************************************************************************** +// +// The following define the bit fields in the PWM Fault register. +// +//***************************************************************************** +#define PWM_FAULT_FAULT5 0x00000020 // PWM5 pin fault +#define PWM_FAULT_FAULT4 0x00000010 // PWM5 pin fault +#define PWM_FAULT_FAULT3 0x00000008 // PWM5 pin fault +#define PWM_FAULT_FAULT2 0x00000004 // PWM5 pin fault +#define PWM_FAULT_FAULT1 0x00000002 // PWM5 pin fault +#define PWM_FAULT_FAULT0 0x00000001 // PWM5 pin fault + +//***************************************************************************** +// +// PWM Interrupt Register bit definitions. +// +//***************************************************************************** +#define PWM_INT_INTFAULT 0x00010000 // Fault interrupt pending + +//***************************************************************************** +// +// The following define the bit fields in the PWM Status register. +// +//***************************************************************************** +#define PWM_STATUS_FAULT 0x00000001 // Fault status + +//***************************************************************************** +// +// PWM Generator standard offsets. +// +//***************************************************************************** +#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base +#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base +#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base + +#define PWM_O_X_CTL 0x00000000 // Gen Control Reg +#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg +#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg +#define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg +#define PWM_O_X_LOAD 0x00000010 // Gen Load Reg +#define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg +#define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg +#define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg +#define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg +#define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg +#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg +#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg +#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg + +//***************************************************************************** +// +// PWM_X Control Register bit definitions. +// +//***************************************************************************** +#define PWM_X_CTL_ENABLE 0x00000001 // Master enable for gen block +#define PWM_X_CTL_MODE 0x00000002 // Counter mode, down or up/down +#define PWM_X_CTL_DEBUG 0x00000004 // Debug mode +#define PWM_X_CTL_LOADUPD 0x00000008 // Update mode for the load reg +#define PWM_X_CTL_CMPAUPD 0x00000010 // Update mode for comp A reg +#define PWM_X_CTL_CMPBUPD 0x00000020 // Update mode for comp B reg + +//***************************************************************************** +// +// PWM_X Interrupt/Trigger Enable Register bit definitions. +// +//***************************************************************************** +#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Int if COUNT = 0 +#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Int if COUNT = LOAD +#define PWM_X_INTEN_INTCMPAU 0x00000004 // Int if COUNT = CMPA U +#define PWM_X_INTEN_INTCMPAD 0x00000008 // Int if COUNT = CMPA D +#define PWM_X_INTEN_INTCMPBU 0x00000010 // Int if COUNT = CMPA U +#define PWM_X_INTEN_INTCMPBD 0x00000020 // Int if COUNT = CMPA D +#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trig if COUNT = 0 +#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trig if COUNT = LOAD +#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trig if COUNT = CMPA U +#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trig if COUNT = CMPA D +#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trig if COUNT = CMPA U +#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trig if COUNT = CMPA D + +//***************************************************************************** +// +// PWM_X Raw Interrupt Status Register bit definitions. +// +//***************************************************************************** +#define PWM_X_RIS_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 int +#define PWM_X_RIS_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD int +#define PWM_X_RIS_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U int +#define PWM_X_RIS_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D int +#define PWM_X_RIS_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U int +#define PWM_X_RIS_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D int + +//***************************************************************************** +// +// PWM_X Interrupt Status Register bit definitions. +// +//***************************************************************************** +#define PWM_X_INT_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 received +#define PWM_X_INT_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD rcvd +#define PWM_X_INT_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U rcvd +#define PWM_X_INT_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D rcvd +#define PWM_X_INT_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U rcvd +#define PWM_X_INT_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D rcvd + +//***************************************************************************** +// +// PWM_X Generator A/B Control Register bit definitions. +// +//***************************************************************************** +#define PWM_X_GEN_Y_ACTZERO 0x00000003 // Act PWM_X_COUNT = 0 +#define PWM_X_GEN_Y_ACTLOAD 0x0000000C // Act PWM_X_COUNT = PWM_X_LOAD +#define PWM_X_GEN_Y_ACTCMPAU 0x00000030 // Act PWM_X_COUNT = PWM_X_CMPA U +#define PWM_X_GEN_Y_ACTCMPAD 0x000000C0 // Act PWM_X_COUNT = PWM_X_CMPA D +#define PWM_X_GEN_Y_ACTCMPBU 0x00000300 // Act PWM_X_COUNT = PWM_X_CMPB U +#define PWM_X_GEN_Y_ACTCMPBD 0x00000C00 // Act PWM_X_COUNT = PWM_X_CMPB D + +//***************************************************************************** +// +// PWM_X Generator A/B Control Register action definitions. +// +//***************************************************************************** +#define PWM_GEN_ACT_NONE 0x0 // Do nothing +#define PWM_GEN_ACT_INV 0x1 // Invert the output signal +#define PWM_GEN_ACT_ZERO 0x2 // Set the output signal to zero +#define PWM_GEN_ACT_ONE 0x3 // Set the output signal to one +#define PWM_GEN_ACT_ZERO_SHIFT 0 // Shift amount for the zero action +#define PWM_GEN_ACT_LOAD_SHIFT 2 // Shift amount for the load action +#define PWM_GEN_ACT_A_UP_SHIFT 4 // Shift amount for the A up action +#define PWM_GEN_ACT_A_DN_SHIFT 6 // Shift amount for the A dn action +#define PWM_GEN_ACT_B_UP_SHIFT 8 // Shift amount for the B up action +#define PWM_GEN_ACT_B_DN_SHIFT 10 // Shift amount for the B dn action + +//***************************************************************************** +// +// PWM_X Dead Band Control Register bit definitions. +// +//***************************************************************************** +#define PWM_DBCTL_ENABLE 0x00000001 // Enable dead band insertion + +//***************************************************************************** +// +// PWM Register reset values. +// +//***************************************************************************** +#define PWM_RV_CTL 0x00000000 // Master control of the PWM module +#define PWM_RV_SYNC 0x00000000 // Counter synch for PWM generators +#define PWM_RV_ENABLE 0x00000000 // Master enable for the PWM + // output pins +#define PWM_RV_INVERT 0x00000000 // Inversion control for + // PWM output pins +#define PWM_RV_FAULT 0x00000000 // Fault handling for the PWM + // output pins +#define PWM_RV_INTEN 0x00000000 // Interrupt enable +#define PWM_RV_RIS 0x00000000 // Raw interrupt status +#define PWM_RV_ISC 0x00000000 // Interrupt status and clearing +#define PWM_RV_STATUS 0x00000000 // Status +#define PWM_RV_X_CTL 0x00000000 // Master control of the PWM + // generator block +#define PWM_RV_X_INTEN 0x00000000 // Interrupt and trigger enable +#define PWM_RV_X_RIS 0x00000000 // Raw interrupt status +#define PWM_RV_X_ISC 0x00000000 // Interrupt status and clearing +#define PWM_RV_X_LOAD 0x00000000 // The load value for the counter +#define PWM_RV_X_COUNT 0x00000000 // The current counter value +#define PWM_RV_X_CMPA 0x00000000 // The comparator A value +#define PWM_RV_X_CMPB 0x00000000 // The comparator B value +#define PWM_RV_X_GENA 0x00000000 // Controls PWM generator A +#define PWM_RV_X_GENB 0x00000000 // Controls PWM generator B +#define PWM_RV_X_DBCTL 0x00000000 // Control the dead band generator +#define PWM_RV_X_DBRISE 0x00000000 // The dead band rising edge delay + // count +#define PWM_RV_X_DBFALL 0x00000000 // The dead band falling edge delay + // count + +#endif // __HW_PWM_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_qei.h b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_qei.h new file mode 100644 index 000000000..864459f48 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_qei.h @@ -0,0 +1,176 @@ +//***************************************************************************** +// +// hw_qei.h - Macros used when accessing the QEI hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_QEI_H__ +#define __HW_QEI_H__ + +//***************************************************************************** +// +// The following define the offsets of the QEI registers. +// +//***************************************************************************** +#define QEI_O_CTL 0x00000000 // Configuration and control reg. +#define QEI_O_STAT 0x00000004 // Status register +#define QEI_O_POS 0x00000008 // Current position register +#define QEI_O_MAXPOS 0x0000000C // Maximum position register +#define QEI_O_LOAD 0x00000010 // Velocity timer load register +#define QEI_O_TIME 0x00000014 // Velocity timer register +#define QEI_O_COUNT 0x00000018 // Velocity pulse count register +#define QEI_O_SPEED 0x0000001C // Velocity speed register +#define QEI_O_INTEN 0x00000020 // Interrupt enable register +#define QEI_O_RIS 0x00000024 // Raw interrupt status register +#define QEI_O_ISC 0x00000028 // Interrupt status register + +//***************************************************************************** +// +// The following define the bit fields in the QEI_CTL register. +// +//***************************************************************************** +#define QEI_CTL_STALLEN 0x00001000 // Stall enable +#define QEI_CTL_INVI 0x00000800 // Invert Index input +#define QEI_CTL_INVB 0x00000400 // Invert PhB input +#define QEI_CTL_INVA 0x00000200 // Invert PhA input +#define QEI_CTL_VELDIV_M 0x000001C0 // Velocity predivider mask +#define QEI_CTL_VELDIV_1 0x00000000 // Predivide by 1 +#define QEI_CTL_VELDIV_2 0x00000040 // Predivide by 2 +#define QEI_CTL_VELDIV_4 0x00000080 // Predivide by 4 +#define QEI_CTL_VELDIV_8 0x000000C0 // Predivide by 8 +#define QEI_CTL_VELDIV_16 0x00000100 // Predivide by 16 +#define QEI_CTL_VELDIV_32 0x00000140 // Predivide by 32 +#define QEI_CTL_VELDIV_64 0x00000180 // Predivide by 64 +#define QEI_CTL_VELDIV_128 0x000001C0 // Predivide by 128 +#define QEI_CTL_VELEN 0x00000020 // Velocity enable +#define QEI_CTL_RESMODE 0x00000010 // Position counter reset mode +#define QEI_CTL_CAPMODE 0x00000008 // Edge capture mode +#define QEI_CTL_SIGMODE 0x00000004 // Encoder signaling mode +#define QEI_CTL_SWAP 0x00000002 // Swap input signals +#define QEI_CTL_ENABLE 0x00000001 // QEI enable + +//***************************************************************************** +// +// The following define the bit fields in the QEI_STAT register. +// +//***************************************************************************** +#define QEI_STAT_DIRECTION 0x00000002 // Direction of rotation +#define QEI_STAT_ERROR 0x00000001 // Signalling error detected + +//***************************************************************************** +// +// The following define the bit fields in the QEI_POS register. +// +//***************************************************************************** +#define QEI_POS_M 0xFFFFFFFF // Current encoder position +#define QEI_POS_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the QEI_MAXPOS register. +// +//***************************************************************************** +#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum encoder position +#define QEI_MAXPOS_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the QEI_LOAD register. +// +//***************************************************************************** +#define QEI_LOAD_M 0xFFFFFFFF // Velocity timer load value +#define QEI_LOAD_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the QEI_TIME register. +// +//***************************************************************************** +#define QEI_TIME_M 0xFFFFFFFF // Velocity timer current value +#define QEI_TIME_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the QEI_COUNT register. +// +//***************************************************************************** +#define QEI_COUNT_M 0xFFFFFFFF // Encoder running pulse count +#define QEI_COUNT_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the QEI_SPEED register. +// +//***************************************************************************** +#define QEI_SPEED_M 0xFFFFFFFF // Encoder pulse count +#define QEI_SPEED_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the QEI_INTEN register. +// +//***************************************************************************** +#define QEI_INTEN_ERROR 0x00000008 // Phase error detected +#define QEI_INTEN_DIR 0x00000004 // Direction change +#define QEI_INTEN_TIMER 0x00000002 // Velocity timer expired +#define QEI_INTEN_INDEX 0x00000001 // Index pulse detected + +//***************************************************************************** +// +// The following define the bit fields in the QEI_RIS register. +// +//***************************************************************************** +#define QEI_RIS_ERROR 0x00000008 // Phase error detected +#define QEI_RIS_DIR 0x00000004 // Direction change +#define QEI_RIS_TIMER 0x00000002 // Velocity timer expired +#define QEI_RIS_INDEX 0x00000001 // Index pulse detected + +//***************************************************************************** +// +// The following define the bit fields in the QEI_ISC register. +// +//***************************************************************************** +#define QEI_INT_ERROR 0x00000008 // Phase error detected +#define QEI_INT_DIR 0x00000004 // Direction change +#define QEI_INT_TIMER 0x00000002 // Velocity timer expired +#define QEI_INT_INDEX 0x00000001 // Index pulse detected + +//***************************************************************************** +// +// The following define the reset values for the QEI registers. +// +//***************************************************************************** +#define QEI_RV_CTL 0x00000000 // Configuration and control reg. +#define QEI_RV_STAT 0x00000000 // Status register +#define QEI_RV_POS 0x00000000 // Current position register +#define QEI_RV_MAXPOS 0x00000000 // Maximum position register +#define QEI_RV_LOAD 0x00000000 // Velocity timer load register +#define QEI_RV_TIME 0x00000000 // Velocity timer register +#define QEI_RV_COUNT 0x00000000 // Velocity pulse count register +#define QEI_RV_SPEED 0x00000000 // Velocity speed register +#define QEI_RV_INTEN 0x00000000 // Interrupt enable register +#define QEI_RV_RIS 0x00000000 // Raw interrupt status register +#define QEI_RV_ISC 0x00000000 // Interrupt status register + +#endif // __HW_QEI_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_ssi.h b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_ssi.h new file mode 100644 index 000000000..e4650af40 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_ssi.h @@ -0,0 +1,120 @@ +//***************************************************************************** +// +// hw_ssi.h - Macros used when accessing the SSI hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_SSI_H__ +#define __HW_SSI_H__ + +//***************************************************************************** +// +// The following define the offsets of the SSI registers. +// +//***************************************************************************** +#define SSI_O_CR0 0x00000000 // Control register 0 +#define SSI_O_CR1 0x00000004 // Control register 1 +#define SSI_O_DR 0x00000008 // Data register +#define SSI_O_SR 0x0000000C // Status register +#define SSI_O_CPSR 0x00000010 // Clock prescale register +#define SSI_O_IM 0x00000014 // Int mask set and clear register +#define SSI_O_RIS 0x00000018 // Raw interrupt register +#define SSI_O_MIS 0x0000001C // Masked interrupt register +#define SSI_O_ICR 0x00000020 // Interrupt clear register + +//***************************************************************************** +// +// The following define the bit fields in the SSI Control register 0. +// +//***************************************************************************** +#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate +#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase +#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity +#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask +#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format +#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format +#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format +#define SSI_CR0_DSS 0x0000000F // Data size select +#define SSI_CR0_DSS_4 0x00000003 // 4 bit data +#define SSI_CR0_DSS_5 0x00000004 // 5 bit data +#define SSI_CR0_DSS_6 0x00000005 // 6 bit data +#define SSI_CR0_DSS_7 0x00000006 // 7 bit data +#define SSI_CR0_DSS_8 0x00000007 // 8 bit data +#define SSI_CR0_DSS_9 0x00000008 // 9 bit data +#define SSI_CR0_DSS_10 0x00000009 // 10 bit data +#define SSI_CR0_DSS_11 0x0000000A // 11 bit data +#define SSI_CR0_DSS_12 0x0000000B // 12 bit data +#define SSI_CR0_DSS_13 0x0000000C // 13 bit data +#define SSI_CR0_DSS_14 0x0000000D // 14 bit data +#define SSI_CR0_DSS_15 0x0000000E // 15 bit data +#define SSI_CR0_DSS_16 0x0000000F // 16 bit data + +//***************************************************************************** +// +// The following define the bit fields in the SSI Control register 1. +// +//***************************************************************************** +#define SSI_CR1_SOD 0x00000008 // Slave mode output disable +#define SSI_CR1_MS 0x00000004 // Master or slave mode select +#define SSI_CR1_SSE 0x00000002 // Sync serial port enable +#define SSI_CR1_LBM 0x00000001 // Loopback mode + +//***************************************************************************** +// +// The following define the bit fields in the SSI Status register. +// +//***************************************************************************** +#define SSI_SR_BSY 0x00000010 // SSI busy +#define SSI_SR_RFF 0x00000008 // RX FIFO full +#define SSI_SR_RNE 0x00000004 // RX FIFO not empty +#define SSI_SR_TNF 0x00000002 // TX FIFO not full +#define SSI_SR_TFE 0x00000001 // TX FIFO empty + +//***************************************************************************** +// +// The following define the bit fields in the SSI clock prescale register. +// +//***************************************************************************** +#define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale + +//***************************************************************************** +// +// The following define information concerning the SSI Data register. +// +//***************************************************************************** +#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO +#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO + +//***************************************************************************** +// +// The following define the bit fields in the interrupt mask set and clear, +// raw interrupt, masked interrupt, and interrupt clear registers. +// +//***************************************************************************** +#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt +#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt +#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt +#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt + +#endif // __HW_SSI_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_sysctl.h b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_sysctl.h new file mode 100644 index 000000000..cce5ad214 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_sysctl.h @@ -0,0 +1,409 @@ +//***************************************************************************** +// +// hw_sysctl.h - Macros used when accessing the system control hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_SYSCTL_H__ +#define __HW_SYSCTL_H__ + +//***************************************************************************** +// +// The following define the offsets of the system control registers. +// +//***************************************************************************** +#define SYSCTL_DID0 0x400fe000 // Device identification register 0 +#define SYSCTL_DID1 0x400fe004 // Device identification register 1 +#define SYSCTL_DC0 0x400fe008 // Device capabilities register 0 +#define SYSCTL_DC1 0x400fe010 // Device capabilities register 1 +#define SYSCTL_DC2 0x400fe014 // Device capabilities register 2 +#define SYSCTL_DC3 0x400fe018 // Device capabilities register 3 +#define SYSCTL_DC4 0x400fe01C // Device capabilities register 4 +#define SYSCTL_PBORCTL 0x400fe030 // POR/BOR reset control register +#define SYSCTL_LDOPCTL 0x400fe034 // LDO power control register +#define SYSCTL_SRCR0 0x400fe040 // Software reset control reg 0 +#define SYSCTL_SRCR1 0x400fe044 // Software reset control reg 1 +#define SYSCTL_SRCR2 0x400fe048 // Software reset control reg 2 +#define SYSCTL_RIS 0x400fe050 // Raw interrupt status register +#define SYSCTL_IMC 0x400fe054 // Interrupt mask/control register +#define SYSCTL_MISC 0x400fe058 // Interrupt status register +#define SYSCTL_RESC 0x400fe05c // Reset cause register +#define SYSCTL_RCC 0x400fe060 // Run-mode clock config register +#define SYSCTL_PLLCFG 0x400fe064 // PLL configuration register +#define SYSCTL_RCGC0 0x400fe100 // Run-mode clock gating register 0 +#define SYSCTL_RCGC1 0x400fe104 // Run-mode clock gating register 1 +#define SYSCTL_RCGC2 0x400fe108 // Run-mode clock gating register 2 +#define SYSCTL_SCGC0 0x400fe110 // Sleep-mode clock gating reg 0 +#define SYSCTL_SCGC1 0x400fe114 // Sleep-mode clock gating reg 1 +#define SYSCTL_SCGC2 0x400fe118 // Sleep-mode clock gating reg 2 +#define SYSCTL_DCGC0 0x400fe120 // Deep Sleep-mode clock gate reg 0 +#define SYSCTL_DCGC1 0x400fe124 // Deep Sleep-mode clock gate reg 1 +#define SYSCTL_DCGC2 0x400fe128 // Deep Sleep-mode clock gate reg 2 +#define SYSCTL_CLKVCLR 0x400fe150 // Clock verifcation clear register +#define SYSCTL_LDOARST 0x400fe160 // LDO reset control register + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DID0 register. +// +//***************************************************************************** +#define SYSCTL_DID0_VER_MASK 0x70000000 // DID0 version mask +#define SYSCTL_DID0_VER_0 0x00000000 // DID0 version 0 +#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask +#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A +#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B +#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask +#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0 +#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DID1 register. +// +//***************************************************************************** +#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask +#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask +#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family +#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask +#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101 +#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102 +#define SYSCTL_DID1_PRTNO_301 0x00110000 // LM3S301 +#define SYSCTL_DID1_PRTNO_310 0x00120000 // LM3S310 +#define SYSCTL_DID1_PRTNO_315 0x00130000 // LM3S315 +#define SYSCTL_DID1_PRTNO_316 0x00140000 // LM3S316 +#define SYSCTL_DID1_PRTNO_328 0x00150000 // LM3S328 +#define SYSCTL_DID1_PRTNO_601 0x00210000 // LM3S601 +#define SYSCTL_DID1_PRTNO_610 0x00220000 // LM3S610 +#define SYSCTL_DID1_PRTNO_611 0x00230000 // LM3S611 +#define SYSCTL_DID1_PRTNO_612 0x00240000 // LM3S612 +#define SYSCTL_DID1_PRTNO_613 0x00250000 // LM3S613 +#define SYSCTL_DID1_PRTNO_615 0x00260000 // LM3S615 +#define SYSCTL_DID1_PRTNO_628 0x00270000 // LM3S628 +#define SYSCTL_DID1_PRTNO_801 0x00310000 // LM3S801 +#define SYSCTL_DID1_PRTNO_811 0x00320000 // LM3S811 +#define SYSCTL_DID1_PRTNO_812 0x00330000 // LM3S812 +#define SYSCTL_DID1_PRTNO_815 0x00340000 // LM3S815 +#define SYSCTL_DID1_PRTNO_828 0x00350000 // LM3S828 +#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask +#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C) +#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C) +#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask +#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC +#define SYSCTL_DID1_PKG_48QFP 0x00000008 // 48-pin QFP +#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant +#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask +#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified) +#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified) +#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified +#define SYSCTL_DID1_PRTNO_SHIFT 16 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC0 register. +// +//***************************************************************************** +#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask +#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2kB of SRAM +#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4kB of SRAM +#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8kB of SRAM +#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask +#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8kB of flash +#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16kB of flash +#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32kB of flash +#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64kB of flash + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC1 register. +// +//***************************************************************************** +#define SYSCTL_DC1_PWM 0x00100000 // PWM module present +#define SYSCTL_DC1_ADC 0x00010000 // ADC module present +#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask +#define SYSCTL_DC1_ADCSPD_MASK 0x00000F00 // ADC speed mask +#define SYSCTL_DC1_ADCSPD_1M 0x00000300 // 1Msps ADC +#define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500Ksps ADC +#define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250Ksps ADC +#define SYSCTL_DC1_ADCSPD_125K 0x00000000 // 125Ksps ADC +#define SYSCTL_DC1_MPU 0x00000080 // Cortex M3 MPU present +#define SYSCTL_DC1_TEMP 0x00000020 // Temperature sensor present +#define SYSCTL_DC1_PLL 0x00000010 // PLL present +#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present +#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present +#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present +#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC2 register. +// +//***************************************************************************** +#define SYSCTL_DC2_COMP2 0x04000000 // Analog comparator 2 present +#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present +#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present +#define SYSCTL_DC2_TIMER2 0x00040000 // Timer 2 present +#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present +#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present +#define SYSCTL_DC2_I2C 0x00001000 // I2C present +#define SYSCTL_DC2_QEI 0x00000100 // QEI present +#define SYSCTL_DC2_SSI 0x00000010 // SSI present +#define SYSCTL_DC2_UART1 0x00000002 // UART 1 present +#define SYSCTL_DC2_UART0 0x00000001 // UART 0 present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC3 register. +// +//***************************************************************************** +#define SYSCTL_DC3_32KHZ 0x80000000 // 32kHz pin present +#define SYSCTL_DC3_CCP5 0x20000000 // CCP5 pin present +#define SYSCTL_DC3_CCP4 0x10000000 // CCP4 pin present +#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 pin present +#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 pin present +#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present +#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present +#define SYSCTL_DC3_ADC7 0x00800000 // ADC7 pin present +#define SYSCTL_DC3_ADC6 0x00400000 // ADC6 pin present +#define SYSCTL_DC3_ADC5 0x00200000 // ADC5 pin present +#define SYSCTL_DC3_ADC4 0x00100000 // ADC4 pin present +#define SYSCTL_DC3_ADC3 0x00080000 // ADC3 pin present +#define SYSCTL_DC3_ADC2 0x00040000 // ADC2 pin present +#define SYSCTL_DC3_ADC1 0x00020000 // ADC1 pin present +#define SYSCTL_DC3_ADC0 0x00010000 // ADC0 pin present +#define SYSCTL_DC3_C2O 0x00004000 // C2o pin present +#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ pin present +#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- pin present +#define SYSCTL_DC3_C1O 0x00000800 // C1o pin present +#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ pin present +#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present +#define SYSCTL_DC3_C0O 0x00000100 // C0o pin present +#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present +#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present +#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 pin present +#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 pin present +#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 pin present +#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 pin present +#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 pin present +#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 pin present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC4 register. +// +//***************************************************************************** +#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO port E present +#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO port D present +#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present +#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present +#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_PBORCTL register. +// +//***************************************************************************** +#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer +#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset +#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise +#define SYSCTL_PBORCTL_BOR_SH 2 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_LDOPCTL register. +// +//***************************************************************************** +#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask +#define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V +#define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V +#define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V +#define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V +#define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V +#define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V +#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V +#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V +#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V +#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V +#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_SRCR0, SYSCTL_RCGC0, +// SYSCTL_SCGC0, and SYSCTL_DCGC0 registers. +// +//***************************************************************************** +#define SYSCTL_SET0_PWM 0x00100000 // PWM module +#define SYSCTL_SET0_ADC 0x00010000 // ADC module +#define SYSCTL_SET0_ADCSPD_MASK 0x00000F00 // ADC speed mask +#define SYSCTL_SET0_ADCSPD_1M 0x00000300 // 1Msps ADC +#define SYSCTL_SET0_ADCSPD_500K 0x00000200 // 500Ksps ADC +#define SYSCTL_SET0_ADCSPD_250K 0x00000100 // 250Ksps ADC +#define SYSCTL_SET0_ADCSPD_125K 0x00000000 // 125Ksps ADC +#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_SRCR1, SYSCTL_RCGC1, +// SYSCTL_SCGC1, and SYSCTL_DCGC1 registers. +// +//***************************************************************************** +#define SYSCTL_SET1_COMP2 0x04000000 // Analog comparator module 2 +#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1 +#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0 +#define SYSCTL_SET1_TIMER2 0x00040000 // Timer module 2 +#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1 +#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0 +#define SYSCTL_SET1_I2C 0x00001000 // I2C module +#define SYSCTL_SET1_QEI 0x00000100 // QEI module +#define SYSCTL_SET1_SSI 0x00000010 // SSI module +#define SYSCTL_SET1_UART1 0x00000002 // UART module 1 +#define SYSCTL_SET1_UART0 0x00000001 // UART module 0 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_SRCR2, SYSCTL_RCGC2, +// SYSCTL_SCGC2, and SYSCTL_DCGC2 registers. +// +//***************************************************************************** +#define SYSCTL_SET2_GPIOE 0x00000010 // GPIO E module +#define SYSCTL_SET2_GPIOD 0x00000008 // GPIO D module +#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module +#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module +#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_RIS, SYSCTL_IMC, and +// SYSCTL_IMS registers. +// +//***************************************************************************** +#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt +#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt +#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int +#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int +#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt +#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt +#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_RESC register. +// +//***************************************************************************** +#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset +#define SYSCTL_RESC_SW 0x00000010 // Software reset +#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset +#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset +#define SYSCTL_RESC_POR 0x00000002 // Power on reset +#define SYSCTL_RESC_EXT 0x00000001 // External reset + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_RCC register. +// +//***************************************************************************** +#define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating +#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider +#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2 +#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3 +#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4 +#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5 +#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6 +#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7 +#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8 +#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9 +#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10 +#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11 +#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12 +#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13 +#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14 +#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15 +#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16 +#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider +#define SYSCTL_RCC_USE_PWMDIV 0x00100000 // Use PWM clock divider +#define SYSCTL_RCC_PWMDIV_MASK 0x000E0000 // PWM clock divider +#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2 +#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4 +#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8 +#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16 +#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32 +#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64 +#define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down +#define SYSCTL_RCC_OE 0x00001000 // PLL output enable +#define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass +#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable +#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc +#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal +#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864MHz crystal +#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4MHz crystal +#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal +#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal +#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal +#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal +#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal +#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal +#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal +#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal +#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal +#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select +#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator +#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // Use the internal oscillator +#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // Use the internal oscillator / 4 +#define SYSCTL_RCC_IOSCVER 0x00000008 // Int. osc. verification timer en +#define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en +#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal oscillator disable +#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable +#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field +#define SYSCTL_RCC_PWMDIV_SHIFT 17 // Shift to the PWMDIV field +#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field +#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_PLLCFG register. +// +//***************************************************************************** +#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider +#define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1 +#define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2 +#define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4 +#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier +#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider +#define SYSCTL_PLLCFG_F_SHIFT 5 +#define SYSCTL_PLLCFG_R_SHIFT 0 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_CLKVCLR register. +// +//***************************************************************************** +#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_LDOARST register. +// +//***************************************************************************** +#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device + +#endif // __HW_SYSCTL_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_timer.h b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_timer.h new file mode 100644 index 000000000..210c3408e --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_timer.h @@ -0,0 +1,235 @@ +//***************************************************************************** +// +// hw_timer.h - Defines and macros used when accessing the timer. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_TIMER_H__ +#define __HW_TIMER_H__ + +//***************************************************************************** +// +// The following define the offsets of the timer registers. +// +//***************************************************************************** +#define TIMER_O_CFG 0x00000000 // Configuration register +#define TIMER_O_TAMR 0x00000004 // TimerA mode register +#define TIMER_O_TBMR 0x00000008 // TimerB mode register +#define TIMER_O_CTL 0x0000000C // Control register +#define TIMER_O_IMR 0x00000018 // Interrupt mask register +#define TIMER_O_RIS 0x0000001C // Interrupt status register +#define TIMER_O_MIS 0x00000020 // Masked interrupt status reg. +#define TIMER_O_ICR 0x00000024 // Interrupt clear register +#define TIMER_O_TAILR 0x00000028 // TimerA interval load register +#define TIMER_O_TBILR 0x0000002C // TimerB interval load register +#define TIMER_O_TAMATCHR 0x00000030 // TimerA match register +#define TIMER_O_TBMATCHR 0x00000034 // TimerB match register +#define TIMER_O_TAPR 0x00000038 // TimerA prescale register +#define TIMER_O_TBPR 0x0000003C // TimerB prescale register +#define TIMER_O_TAPMR 0x00000040 // TimerA prescale match register +#define TIMER_O_TBPMR 0x00000044 // TimerB prescale match register +#define TIMER_O_TAR 0x00000048 // TimerA register +#define TIMER_O_TBR 0x0000004C // TimerB register + +//***************************************************************************** +// +// The following define the reset values of the timer registers. +// +//***************************************************************************** +#define TIMER_RV_CFG 0x00000000 // Configuration register RV +#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV +#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV +#define TIMER_RV_CTL 0x00000000 // Control register RV +#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV +#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV +#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV +#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV +#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV +#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV +#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV +#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV +#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV +#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV +#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV +#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV +#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV +#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_CFG register. +// +//***************************************************************************** +#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask +#define TIMER_CFG_16_BIT 0x00000004 // Two 16 bit timers +#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32 bit RTC +#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32 bit timer + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_TnMR register. +// +//***************************************************************************** +#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select +#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time +#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask +#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture +#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic +#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_CTL register. +// +//***************************************************************************** +#define TIMER_CTL_TBPWML 0x00004000 // TimerB PWM output level invert +#define TIMER_CTL_TBOTE 0x00002000 // TimerB output trigger enable +#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask +#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // TimerB event mode - both edges +#define TIMER_CTL_TBEVENT_NEG 0x00000400 // TimerB event mode - neg edge +#define TIMER_CTL_TBEVENT_POS 0x00000000 // TimerB event mode - pos edge +#define TIMER_CTL_TBSTALL 0x00000200 // TimerB stall enable +#define TIMER_CTL_TBEN 0x00000100 // TimerB enable +#define TIMER_CTL_TAPWML 0x00000040 // TimerA PWM output level invert +#define TIMER_CTL_TAOTE 0x00000020 // TimerA output trigger enable +#define TIMER_CTL_RTCEN 0x00000010 // RTC counter enable +#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask +#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // TimerA event mode - both edges +#define TIMER_CTL_TAEVENT_NEG 0x00000004 // TimerA event mode - neg edge +#define TIMER_CTL_TAEVENT_POS 0x00000000 // TimerA event mode - pos edge +#define TIMER_CTL_TASTALL 0x00000002 // TimerA stall enable +#define TIMER_CTL_TAEN 0x00000001 // TimerA enable + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_IMR register. +// +//***************************************************************************** +#define TIMER_IMR_CBEIM 0x00000400 // CaptureB event interrupt mask +#define TIMER_IMR_CBMIM 0x00000200 // CaptureB match interrupt mask +#define TIMER_IMR_TBTOIM 0x00000100 // TimerB time out interrupt mask +#define TIMER_IMR_RTCIM 0x00000008 // RTC interrupt mask +#define TIMER_IMR_CAEIM 0x00000004 // CaptureA event interrupt mask +#define TIMER_IMR_CAMIM 0x00000002 // CaptureA match interrupt mask +#define TIMER_IMR_TATOIM 0x00000001 // TimerA time out interrupt mask + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_RIS register. +// +//***************************************************************************** +#define TIMER_RIS_CBERIS 0x00000400 // CaptureB event raw int status +#define TIMER_RIS_CBMRIS 0x00000200 // CaptureB match raw int status +#define TIMER_RIS_TBTORIS 0x00000100 // TimerB time out raw int status +#define TIMER_RIS_RTCRIS 0x00000008 // RTC raw int status +#define TIMER_RIS_CAERIS 0x00000004 // CaptureA event raw int status +#define TIMER_RIS_CAMRIS 0x00000002 // CaptureA match raw int status +#define TIMER_RIS_TATORIS 0x00000001 // TimerA time out raw int status + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_MIS register. +// +//***************************************************************************** +#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status +#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status +#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat +#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status +#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status +#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status +#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_ICR register. +// +//***************************************************************************** +#define TIMER_ICR_CBECINT 0x00000400 // CaptureB event interrupt clear +#define TIMER_ICR_CBMCINT 0x00000200 // CaptureB match interrupt clear +#define TIMER_ICR_TBTOCINT 0x00000100 // TimerB time out interrupt clear +#define TIMER_ICR_RTCCINT 0x00000008 // RTC interrupt clear +#define TIMER_ICR_CAECINT 0x00000004 // CaptureA event interrupt clear +#define TIMER_ICR_CAMCINT 0x00000002 // CaptureA match interrupt clear +#define TIMER_ICR_TATOCINT 0x00000001 // TimerA time out interrupt clear + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_TAILR register. +// +//***************************************************************************** +#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode +#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TBILR register. +// +//***************************************************************************** +#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_TAMATCHR register. +// +//***************************************************************************** +#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode +#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TBMATCHR register. +// +//***************************************************************************** +#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TnPR register. +// +//***************************************************************************** +#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TnPMR register. +// +//***************************************************************************** +#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_TAR register. +// +//***************************************************************************** +#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode +#define TIMER_TAR_TARL 0x0000FFFF // TimerA value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TBR register. +// +//***************************************************************************** +#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value + +#endif // __HW_TIMER_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_types.h b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_types.h new file mode 100644 index 000000000..ec05e5415 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_types.h @@ -0,0 +1,67 @@ +//***************************************************************************** +// +// hw_types.h - Common types and macros. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_TYPES_H__ +#define __HW_TYPES_H__ + +//***************************************************************************** +// +// Define a boolean type, and values for true and false. +// +//***************************************************************************** +typedef unsigned char tBoolean; + +#ifndef true +#define true 1 +#endif + +#ifndef false +#define false 0 +#endif + +//***************************************************************************** +// +// Macros for hardware access, both direct and via the bit-band region. +// +//***************************************************************************** +#define HWREG(x) \ + (*((volatile unsigned long *)(x))) +#define HWREGH(x) \ + (*((volatile unsigned short *)(x))) +#define HWREGB(x) \ + (*((volatile unsigned char *)(x))) +#define HWREGBITW(x, b) \ + HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITH(x, b) \ + HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITB(x, b) \ + HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) + +#endif // __HW_TYPES_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_uart.h b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_uart.h new file mode 100644 index 000000000..6f421b64e --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_uart.h @@ -0,0 +1,239 @@ +//***************************************************************************** +// +// hw_uart.h - Macros and defines used when accessing the UART hardware +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_UART_H__ +#define __HW_UART_H__ + +//***************************************************************************** +// +// UART Register Offsets. +// +//***************************************************************************** +#define UART_O_DR 0x00000000 // Data Register +#define UART_O_RSR 0x00000004 // Receive Status Register (read) +#define UART_O_ECR 0x00000004 // Error Clear Register (write) +#define UART_O_FR 0x00000018 // Flag Register (read only) +#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg +#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg +#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte +#define UART_O_CTL 0x00000030 // Control Register +#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg +#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg +#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register +#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register +#define UART_O_ICR 0x00000044 // Interrupt Clear Register +#define UART_O_PeriphID4 0x00000FD0 // +#define UART_O_PeriphID5 0x00000FD4 // +#define UART_O_PeriphID6 0x00000FD8 // +#define UART_O_PeriphID7 0x00000FDC // +#define UART_O_PeriphID0 0x00000FE0 // +#define UART_O_PeriphID1 0x00000FE4 // +#define UART_O_PeriphID2 0x00000FE8 // +#define UART_O_PeriphID3 0x00000FEC // +#define UART_O_PCellID0 0x00000FF0 // +#define UART_O_PCellID1 0x00000FF4 // +#define UART_O_PCellID2 0x00000FF8 // +#define UART_O_PCellID3 0x00000FFC // + +//***************************************************************************** +// +// Data Register bits +// +//***************************************************************************** +#define UART_DR_OE 0x00000800 // Overrun Error +#define UART_DR_BE 0x00000400 // Break Error +#define UART_DR_PE 0x00000200 // Parity Error +#define UART_DR_FE 0x00000100 // Framing Error +#define UART_DR_DATA_MASK 0x000000FF // UART data + +//***************************************************************************** +// +// Receive Status Register bits +// +//***************************************************************************** +#define UART_RSR_OE 0x00000008 // Overrun Error +#define UART_RSR_BE 0x00000004 // Break Error +#define UART_RSR_PE 0x00000002 // Parity Error +#define UART_RSR_FE 0x00000001 // Framing Error + +//***************************************************************************** +// +// Flag Register bits +// +//***************************************************************************** +#define UART_FR_TXFE 0x00000080 // TX FIFO Empty +#define UART_FR_RXFF 0x00000040 // RX FIFO Full +#define UART_FR_TXFF 0x00000020 // TX FIFO Full +#define UART_FR_RXFE 0x00000010 // RX FIFO Empty +#define UART_FR_BUSY 0x00000008 // UART Busy + +//***************************************************************************** +// +// Integer baud-rate divisor +// +//***************************************************************************** +#define UART_IBRD_DIVINT_MASK 0x0000FFFF // Integer baud-rate divisor + +//***************************************************************************** +// +// Fractional baud-rate divisor +// +//***************************************************************************** +#define UART_FBRD_DIVFRAC_MASK 0x0000003F // Fractional baud-rate divisor + +//***************************************************************************** +// +// Line Control Register High bits +// +//***************************************************************************** +#define UART_LCR_H_SPS 0x00000080 // Stick Parity Select +#define UART_LCR_H_WLEN 0x00000060 // Word length +#define UART_LCR_H_WLEN_8 0x00000060 // 8 bit data +#define UART_LCR_H_WLEN_7 0x00000040 // 7 bit data +#define UART_LCR_H_WLEN_6 0x00000020 // 6 bit data +#define UART_LCR_H_WLEN_5 0x00000000 // 5 bit data +#define UART_LCR_H_FEN 0x00000010 // Enable FIFO +#define UART_LCR_H_STP2 0x00000008 // Two Stop Bits Select +#define UART_LCR_H_EPS 0x00000004 // Even Parity Select +#define UART_LCR_H_PEN 0x00000002 // Parity Enable +#define UART_LCR_H_BRK 0x00000001 // Send Break + +//***************************************************************************** +// +// Control Register bits +// +//***************************************************************************** +#define UART_CTL_RXE 0x00000200 // Receive Enable +#define UART_CTL_TXE 0x00000100 // Transmit Enable +#define UART_CTL_LBE 0x00000080 // Loopback Enable +#define UART_CTL_UARTEN 0x00000001 // UART Enable + +//***************************************************************************** +// +// Interrupt FIFO Level Select Register bits +// +//***************************************************************************** +#define UART_IFLS_RX1_8 0x00000000 // 1/8 Full +#define UART_IFLS_RX2_8 0x00000010 // 1/4 Full +#define UART_IFLS_RX4_8 0x00000020 // 1/2 Full +#define UART_IFLS_RX6_8 0x00000030 // 3/4 Full +#define UART_IFLS_RX7_8 0x00000040 // 7/8 Full +#define UART_IFLS_TX1_8 0x00000000 // 1/8 Full +#define UART_IFLS_TX2_8 0x00000001 // 1/4 Full +#define UART_IFLS_TX4_8 0x00000002 // 1/2 Full +#define UART_IFLS_TX6_8 0x00000003 // 3/4 Full +#define UART_IFLS_TX7_8 0x00000004 // 7/8 Full + +//***************************************************************************** +// +// Interrupt Mask Set/Clear Register bits +// +//***************************************************************************** +#define UART_IM_OEIM 0x00000400 // Overrun Error Interrupt Mask +#define UART_IM_BEIM 0x00000200 // Break Error Interrupt Mask +#define UART_IM_PEIM 0x00000100 // Parity Error Interrupt Mask +#define UART_IM_FEIM 0x00000080 // Framing Error Interrupt Mask +#define UART_IM_RTIM 0x00000040 // Receive Timeout Interrupt Mask +#define UART_IM_TXIM 0x00000020 // Transmit Interrupt Mask +#define UART_IM_RXIM 0x00000010 // Receive Interrupt Mask + +//***************************************************************************** +// +// Raw Interrupt Status Register +// +//***************************************************************************** +#define UART_RIS_OERIS 0x00000400 // Overrun Error Interrupt Status +#define UART_RIS_BERIS 0x00000200 // Break Error Interrupt Status +#define UART_RIS_PERIS 0x00000100 // Parity Error Interrupt Status +#define UART_RIS_FERIS 0x00000080 // Framing Error Interrupt Status +#define UART_RIS_RTRIS 0x00000040 // Receive Timeout Interrupt Status +#define UART_RIS_TXRIS 0x00000020 // Transmit Interrupt Status +#define UART_RIS_RXRIS 0x00000010 // Receive Interrupt Status + +//***************************************************************************** +// +// Masked Interrupt Status Register +// +//***************************************************************************** +#define UART_MIS_OEMIS 0x00000400 // Overrun Error Interrupt Status +#define UART_MIS_BEMIS 0x00000200 // Break Error Interrupt Status +#define UART_MIS_PEMIS 0x00000100 // Parity Error Interrupt Status +#define UART_MIS_FEMIS 0x00000080 // Framing Error Interrupt Status +#define UART_MIS_RTMIS 0x00000040 // Receive Timeout Interrupt Status +#define UART_MIS_TXMIS 0x00000020 // Transmit Interrupt Status +#define UART_MIS_RXMIS 0x00000010 // Receive Interrupt Status + +//***************************************************************************** +// +// Interrupt Clear Register bits +// +//***************************************************************************** +#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear +#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear +#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear +#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear +#define UART_ICR_RTIC 0x00000040 // Receive Timeout Interrupt Clear +#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear +#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear + +#define UART_RSR_ANY (UART_RSR_OE | \ + UART_RSR_BE | \ + UART_RSR_PE | \ + UART_RSR_FE) + +//***************************************************************************** +// +// Reset Values for UART Registers. +// +//***************************************************************************** +#define UART_RV_DR 0x00000000 +#define UART_RV_RSR 0x00000000 +#define UART_RV_ECR 0x00000000 +#define UART_RV_FR 0x00000090 +#define UART_RV_IBRD 0x00000000 +#define UART_RV_FBRD 0x00000000 +#define UART_RV_LCR_H 0x00000000 +#define UART_RV_CTL 0x00000300 +#define UART_RV_IFLS 0x00000012 +#define UART_RV_IM 0x00000000 +#define UART_RV_RIS 0x00000000 +#define UART_RV_MIS 0x00000000 +#define UART_RV_ICR 0x00000000 +#define UART_RV_PeriphID4 0x00000000 +#define UART_RV_PeriphID5 0x00000000 +#define UART_RV_PeriphID6 0x00000000 +#define UART_RV_PeriphID7 0x00000000 +#define UART_RV_PeriphID0 0x00000011 +#define UART_RV_PeriphID1 0x00000000 +#define UART_RV_PeriphID2 0x00000018 +#define UART_RV_PeriphID3 0x00000001 +#define UART_RV_PCellID0 0x0000000D +#define UART_RV_PCellID1 0x000000F0 +#define UART_RV_PCellID2 0x00000005 +#define UART_RV_PCellID3 0x000000B1 + +#endif // __HW_UART_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_watchdog.h b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_watchdog.h new file mode 100644 index 000000000..2b013ad84 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_watchdog.h @@ -0,0 +1,116 @@ +//***************************************************************************** +// +// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_WATCHDOG_H__ +#define __HW_WATCHDOG_H__ + +//***************************************************************************** +// +// The following define the offsets of the Watchdog Timer registers. +// +//***************************************************************************** +#define WDT_O_LOAD 0x00000000 // Load register +#define WDT_O_VALUE 0x00000004 // Current value register +#define WDT_O_CTL 0x00000008 // Control register +#define WDT_O_ICR 0x0000000C // Interrupt clear register +#define WDT_O_RIS 0x00000010 // Raw interrupt status register +#define WDT_O_MIS 0x00000014 // Masked interrupt status register +#define WDT_O_TEST 0x00000418 // Test register +#define WDT_O_LOCK 0x00000C00 // Lock register +#define WDT_O_PeriphID4 0x00000FD0 // +#define WDT_O_PeriphID5 0x00000FD4 // +#define WDT_O_PeriphID6 0x00000FD8 // +#define WDT_O_PeriphID7 0x00000FDC // +#define WDT_O_PeriphID0 0x00000FE0 // +#define WDT_O_PeriphID1 0x00000FE4 // +#define WDT_O_PeriphID2 0x00000FE8 // +#define WDT_O_PeriphID3 0x00000FEC // +#define WDT_O_PCellID0 0x00000FF0 // +#define WDT_O_PCellID1 0x00000FF4 // +#define WDT_O_PCellID2 0x00000FF8 // +#define WDT_O_PCellID3 0x00000FFC // + +//***************************************************************************** +// +// The following define the bit fields in the WDT_CTL register. +// +//***************************************************************************** +#define WDT_CTL_RESEN 0x00000002 // Enable reset output +#define WDT_CTL_INTEN 0x00000001 // Enable the WDT counter and int + +//***************************************************************************** +// +// The following define the bit fields in the WDT_ISR, WDT_RIS, and WDT_MIS +// registers. +// +//***************************************************************************** +#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired + +//***************************************************************************** +// +// The following define the bit fields in the WDT_TEST register. +// +//***************************************************************************** +#define WDT_TEST_STALL 0x00000100 // Watchdog stall enable +#ifndef DEPRECATED +#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable +#endif + +//***************************************************************************** +// +// The following define the bit fields in the WDT_LOCK register. +// +//***************************************************************************** +#define WDT_LOCK_LOCKED 0x00000001 // Watchdog timer is locked +#define WDT_LOCK_UNLOCKED 0x00000000 // Watchdog timer is unlocked +#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer + +//***************************************************************************** +// +// The following define the reset values for the WDT registers. +// +//***************************************************************************** +#define WDT_RV_LOAD 0xFFFFFFFF // Load register +#define WDT_RV_VALUE 0xFFFFFFFF // Current value register +#define WDT_RV_CTL 0x00000000 // Control register +#define WDT_RV_RIS 0x00000000 // Raw interrupt status register +#define WDT_RV_MIS 0x00000000 // Masked interrupt status register +#define WDT_RV_LOCK 0x00000000 // Lock register +#define WDT_RV_PeriphID4 0x00000000 // +#define WDT_RV_PeriphID5 0x00000000 // +#define WDT_RV_PeriphID6 0x00000000 // +#define WDT_RV_PeriphID7 0x00000000 // +#define WDT_RV_PeriphID0 0x00000005 // +#define WDT_RV_PeriphID1 0x00000018 // +#define WDT_RV_PeriphID2 0x00000018 // +#define WDT_RV_PeriphID3 0x00000001 // +#define WDT_RV_PCellID0 0x0000000D // +#define WDT_RV_PCellID1 0x000000F0 // +#define WDT_RV_PCellID2 0x00000005 // +#define WDT_RV_PCellID3 0x000000B1 // + +#endif // __HW_WATCHDOG_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/i2c.c b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/i2c.c new file mode 100644 index 000000000..b460ad603 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/i2c.c @@ -0,0 +1,972 @@ +//***************************************************************************** +// +// i2c.c - Driver for Inter-IC (I2C) bus block. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup i2c_api +//! @{ +// +//***************************************************************************** + +#include "../hw_i2c.h" +#include "../hw_ints.h" +#include "../hw_memmap.h" +#include "../hw_types.h" +#include "debug.h" +#include "i2c.h" +#include "interrupt.h" +#include "sysctl.h" + +//***************************************************************************** +// +//! Initializes the I2C Master block. +//! +//! \param ulBase base address of the I2C Master module +//! \param bFast set up for fast data transfers +//! +//! This function initializes operation of the I2C Master block. Upon +//! successful initialization of the I2C block, this function will have +//! set the bus speed for the master, and will have enabled the I2C Master +//! block. +//! +//! If the parameter \e bFast is \b true, then the master block will be +//! set up to transfer data at 400 kbps; otherwise, it will be set up to +//! transfer data at 100 kbps. +//! +//! The I2C clocking is dependent upon the system clock rate returned by +//! SysCtlClockGet(); if it does not return the correct system clock rate then +//! the I2C clock rate will be incorrect. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_masterinit) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CMasterInit(unsigned long ulBase, tBoolean bFast) +{ + unsigned long ulSysClk; + unsigned long ulSCLFreq; + unsigned long ulTPR; + + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Must enable the device before doing anything else. + // + I2CMasterEnable(ulBase); + + // + // Get the system clock speed. + // + ulSysClk = SysCtlClockGet(); + + // + // Get the desired SCL speed. + // + if(bFast == true) + { + ulSCLFreq = I2C_SCL_FAST; + } + else + { + ulSCLFreq = I2C_SCL_STANDARD; + } + + // + // Compute the clock divider that achieves the fastest speed less than or + // equal to the desired speed. The numerator is biases to favor a larger + // clock divider so that the resulting clock is always less than or equal + // to the desired clock, never greater. + // + ulTPR = (((ulSysClk + (2 * I2C_MASTER_TPR_SCL * ulSCLFreq) - 1) / + (2 * I2C_MASTER_TPR_SCL * ulSCLFreq)) - 1); + HWREG(ulBase + I2C_MASTER_O_TPR) = ulTPR; +} +#endif + +//***************************************************************************** +// +//! Initializes the I2C Slave block. +//! +//! \param ulBase base address of the I2C Slave module +//! \param ucSlaveAddr 7-bit slave address +//! +//! This function initializes operation of the I2C Slave block. Upon +//! successful initialization of the I2C blocks, this function will have +//! set the slave address and have enabled the I2C Slave block. +//! +//! The parameter \e ucSlaveAddr is the value that will be compared +//! against the slave address sent by an I2C master. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_slaveinit) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_SLAVE_BASE); + ASSERT(!(ucSlaveAddr & 0x80)); + + // + // Must enable the device before doing anything else. + // + I2CSlaveEnable(ulBase); + + // + // Set up the slave address. + // + HWREG(ulBase + I2C_SLAVE_O_OAR) = ucSlaveAddr; +} +#endif + +//***************************************************************************** +// +//! Enables the I2C Master block. +//! +//! \param ulBase base address of the I2C Master module +//! +//! This will enable operation of the I2C Master block. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_masterenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CMasterEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Enable the master block. + // + HWREG(ulBase + I2C_MASTER_O_CR) |= I2C_MASTER_CR_MFE; +} +#endif + +//***************************************************************************** +// +//! Enables the I2C Slave block. +//! +//! \param ulBase base address of the I2C Slave module +//! +//! This will enable operation of the I2C Slave block. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_slaveenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CSlaveEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_SLAVE_BASE); + + // + // Enable the clock to the slave block. + // + HWREG(ulBase - I2C_O_SLAVE + I2C_MASTER_O_CR) |= I2C_MASTER_CR_SFE; + + // + // Enable the slave. + // + HWREG(ulBase + I2C_SLAVE_O_CSR) = I2C_SLAVE_CSR_DA; +} +#endif + +//***************************************************************************** +// +//! Disables the I2C master block. +//! +//! \param ulBase base address of the I2C Master module +//! +//! This will disable operation of the I2C master block. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_masterdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CMasterDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Disable the master block. + // + HWREG(ulBase + I2C_MASTER_O_CR) &= ~(I2C_MASTER_CR_MFE); +} +#endif + +//***************************************************************************** +// +//! Disables the I2C slave block. +//! +//! \param ulBase base address of the I2C Slave module +//! +//! This will disable operation of the I2C slave block. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_slavedisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CSlaveDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_SLAVE_BASE); + + // + // Disable the slave. + // + HWREG(ulBase + I2C_SLAVE_O_CSR) = 0; + + // + // Disable the clock to the slave block. + // + HWREG(ulBase - I2C_O_SLAVE + I2C_MASTER_O_CR) &= ~(I2C_MASTER_CR_SFE); +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for the I2C module +//! +//! \param ulBase base address of the I2C module +//! \param pfnHandler is a pointer to the function to be called when the +//! synchronous serial interface interrupt occurs. +//! +//! This sets the handler to be called when an I2C interrupt occurs. This +//! will enable the global interrupt in the interrupt controller; specific I2C +//! interrupts must be enabled via I2CMasterIntEnable() and +//! I2CSlaveIntEnable(). If necessary, it is the interrupt handler's +//! responsibility to clear the interrupt source via I2CMasterIntClear() and +//! I2CSlaveIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(INT_I2C, pfnHandler); + + // + // Enable the I2C interrupt. + // + IntEnable(INT_I2C); +} +#endif + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the I2C module. +//! +//! \param ulBase base address of the I2C module +//! +//! This function will clear the handler to be called when an I2C +//! interrupt occurs. This will also mask off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CIntUnregister(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Disable the interrupt. + // + IntDisable(INT_I2C); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_I2C); +} +#endif + +//***************************************************************************** +// +//! Enables the I2C Master interrupt. +//! +//! \param ulBase base address of the I2C Master module +//! +//! Enables the I2C Master interrupt source. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_masterintenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CMasterIntEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Enable the master interrupt. + // + HWREG(ulBase + I2C_MASTER_O_IMR) = 1; +} +#endif + +//***************************************************************************** +// +//! Enables the I2C Slave interrupt. +//! +//! \param ulBase base address of the I2C Slave module +//! +//! Enables the I2C Slave interrupt source. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_slaveintenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CSlaveIntEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_SLAVE_BASE); + + // + // Enable the slave interrupt. + // + HWREG(ulBase + I2C_SLAVE_O_IM) = 1; +} +#endif + +//***************************************************************************** +// +//! Disables the I2C Master interrupt. +//! +//! \param ulBase base address of the I2C Master module +//! +//! Disables the I2C Master interrupt source. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_masterintdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CMasterIntDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Disable the master interrupt. + // + HWREG(ulBase + I2C_MASTER_O_IMR) = 0; +} +#endif + +//***************************************************************************** +// +//! Disables the I2C Slave interrupt. +//! +//! \param ulBase base address of the I2C Slave module +//! +//! Disables the I2C Slave interrupt source. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_slaveintdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CSlaveIntDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_SLAVE_BASE); + + // + // Disable the slave interrupt. + // + HWREG(ulBase + I2C_SLAVE_O_IM) = 0; +} +#endif + +//***************************************************************************** +// +//! Gets the current I2C Master interrupt status. +//! +//! \param ulBase base address of the I2C Master module +//! \param bMasked is false if the raw interrupt status is requested and +//! true if the masked interrupt status is requested. +//! +//! This returns the interrupt status for the I2C Master module. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. +//! +//! \return The current interrupt status, returned as \b true if active +//! or \b false if not active. +// +//***************************************************************************** +#if defined(GROUP_masterintstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return((HWREG(ulBase + I2C_MASTER_O_MIS)) ? true : false); + } + else + { + return((HWREG(ulBase + I2C_MASTER_O_RIS)) ? true : false); + } +} +#endif + +//***************************************************************************** +// +//! Gets the current I2C Slave interrupt status. +//! +//! \param ulBase base address of the I2C Slave module +//! \param bMasked is false if the raw interrupt status is requested and +//! true if the masked interrupt status is requested. +//! +//! This returns the interrupt status for the I2C Slave module. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. +//! +//! \return The current interrupt status, returned as \b true if active +//! or \b false if not active. +// +//***************************************************************************** +#if defined(GROUP_slaveintstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_SLAVE_BASE); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return((HWREG(ulBase + I2C_SLAVE_O_MIS)) ? true : false); + } + else + { + return((HWREG(ulBase + I2C_SLAVE_O_RIS)) ? true : false); + } +} +#endif + +//***************************************************************************** +// +//! Clears I2C Master interrupt sources. +//! +//! \param ulBase base address of the I2C Master module +//! +//! The I2C Master interrupt source is cleared, so that it no longer asserts. +//! This must be done in the interrupt handler to keep it from being called +//! again immediately upon exit. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_masterintclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CMasterIntClear(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Clear the I2C master interrupt source. + // + HWREG(ulBase + I2C_MASTER_O_MICR) = I2C_MASTER_MICR_IC; + + // + // Workaround for I2C master interrupt clear errata for rev B Stellaris + // devices. For later devices, this write is ignored and therefore + // harmless (other than the slight performance hit). + // + HWREG(ulBase + I2C_MASTER_O_MIS) = I2C_MASTER_MICR_IC; +} +#endif + +//***************************************************************************** +// +//! Clears I2C Slave interrupt sources. +//! +//! \param ulBase base address of the I2C Slave module +//! +//! The I2C Slave interrupt source is cleared, so that it no longer asserts. +//! This must be done in the interrupt handler to keep it from being called +//! again immediately upon exit. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_slaveintclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CSlaveIntClear(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_SLAVE_BASE); + + // + // Clear the I2C slave interrupt source. + // + HWREG(ulBase + I2C_SLAVE_O_SICR) = I2C_SLAVE_SICR_IC; +} +#endif + +//***************************************************************************** +// +//! Sets the address that the I2C Master will place on the bus. +//! +//! \param ulBase base address of the I2C Master module +//! \param ucSlaveAddr 7-bit slave address +//! \param bReceive flag indicating the type of communication with the slave +//! +//! This function will set the address that the I2C Master will place on the +//! bus when initiating a transaction. When the parameter \e bReceive is set +//! to \b true, the address will indicate that the I2C Master is initiating +//! a read from the slave; otherwise the address will indicate that the I2C +//! Master is initiating a write to the slave. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_masterslaveaddrset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CMasterSlaveAddrSet(unsigned long ulBase, unsigned char ucSlaveAddr, + tBoolean bReceive) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + ASSERT(!(ucSlaveAddr & 0x80)); + + // + // Set the address of the slave with which the master will communicate. + // + HWREG(ulBase + I2C_MASTER_O_SA) = (ucSlaveAddr << 1) | bReceive; +} +#endif + +//***************************************************************************** +// +//! Indicates whether or not the I2C Master is busy. +//! +//! \param ulBase base address of the I2C Master module +//! +//! This function returns an indication of whether or not the I2C Master is +//! busy transmitting or receiving data. +//! +//! \return Returns \b true if the I2C Master is busy; otherwise, returns +//! \b false. +// +//***************************************************************************** +#if defined(GROUP_masterbusy) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +I2CMasterBusy(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Return the busy status. + // + if(HWREG(ulBase + I2C_MASTER_O_CS) & I2C_MASTER_CS_BUSY) + { + return(true); + } + else + { + return(false); + } +} +#endif + +//***************************************************************************** +// +//! Indicates whether or not the I2C bus is busy. +//! +//! \param ulBase base address of the I2C Master module +//! +//! This function returns an indication of whether or not the I2C bus is +//! busy. This function can be used in a multi-master environment to +//! determine if another master is currently using the bus. +//! +//! \return Returns \b true if the I2C bus is busy; otherwise, returns +//! \b false. +// +//***************************************************************************** +#if defined(GROUP_masterbusbusy) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +I2CMasterBusBusy(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Return the bus busy status. + // + if(HWREG(ulBase + I2C_MASTER_O_CS) & I2C_MASTER_CS_BUS_BUSY) + { + return(true); + } + else + { + return(false); + } +} +#endif + +//***************************************************************************** +// +//! Controls the state of the I2C Master module. +//! +//! \param ulBase base address of the I2C Master module +//! \param ulCmd command to be issued to the I2C Master module +//! +//! This function is used to control the state of the Master module send and +//! receive operations. The parameter \e ucCmd can be one of the following +//! values: +//! +//! - I2C_MASTER_CMD_SINGLE_SEND +//! - I2C_MASTER_CMD_SINGLE_RECEIVE +//! - I2C_MASTER_CMD_BURST_SEND_START +//! - I2C_MASTER_CMD_BURST_SEND_CONT +//! - I2C_MASTER_CMD_BURST_SEND_FINISH +//! - I2C_MASTER_CMD_BURST_SEND_ERROR_STOP +//! - I2C_MASTER_CMD_BURST_RECEIVE_START +//! - I2C_MASTER_CMD_BURST_RECEIVE_CONT +//! - I2C_MASTER_CMD_BURST_RECEIVE_FINISH +//! - I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_mastercontrol) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CMasterControl(unsigned long ulBase, unsigned long ulCmd) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + ASSERT((ulCmd == I2C_MASTER_CMD_SINGLE_SEND) || + (ulCmd == I2C_MASTER_CMD_SINGLE_RECEIVE) || + (ulCmd == I2C_MASTER_CMD_BURST_SEND_START) || + (ulCmd == I2C_MASTER_CMD_BURST_SEND_CONT) || + (ulCmd == I2C_MASTER_CMD_BURST_SEND_FINISH) || + (ulCmd == I2C_MASTER_CMD_BURST_SEND_ERROR_STOP) || + (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_START) || + (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_CONT) || + (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_FINISH) || + (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP)); + + // + // Send the command. + // + HWREG(ulBase + I2C_MASTER_O_CS) = ulCmd; +} +#endif + +//***************************************************************************** +// +//! Gets the error status of the I2C Master module. +//! +//! \param ulBase base address of the I2C Master module +//! +//! This function is used to obtain the error status of the Master module +//! send and receive operations. It returns one of the following values: +//! +//! - I2C_MASTER_ERR_NONE +//! - I2C_MASTER_ERR_ADDR_ACK +//! - I2C_MASTER_ERR_DATA_ACK +//! - I2C_MASTER_ERR_ARB_LOST +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_mastererr) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +I2CMasterErr(unsigned long ulBase) +{ + unsigned long ulErr; + + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Get the raw error state + // + ulErr = HWREG(ulBase + I2C_MASTER_O_CS); + + // + // If the I2C master is busy, then all the other bit are invalid, and + // don't have an error to report. + // + if(ulErr & I2C_MASTER_CS_BUSY) + { + return(I2C_MASTER_ERR_NONE); + } + + // + // Check for errors. + // + if(ulErr & I2C_MASTER_CS_ERROR) + { + return(ulErr & (I2C_MASTER_CS_ERR_MASK)); + } + else + { + return(I2C_MASTER_ERR_NONE); + } +} +#endif + +//***************************************************************************** +// +//! Transmits a byte from the I2C Master. +//! +//! \param ulBase base address of the I2C Master module +//! \param ucData data to be transmitted from the I2C Master +//! +//! This function will place the supplied data into I2C Master Data Register. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_masterdataput) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CMasterDataPut(unsigned long ulBase, unsigned char ucData) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Write the byte. + // + HWREG(ulBase + I2C_MASTER_O_DR) = ucData; +} +#endif + +//***************************************************************************** +// +//! Receives a byte that has been sent to the I2C Master. +//! +//! \param ulBase base address of the I2C Master module +//! +//! This function reads a byte of data from the I2C Master Data Register. +//! +//! \return Returns the byte received from by the I2C Master, cast as an +//! unsigned long. +// +//***************************************************************************** +#if defined(GROUP_masterdataget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +I2CMasterDataGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_MASTER_BASE); + + // + // Read a byte. + // + return(HWREG(ulBase + I2C_MASTER_O_DR)); +} +#endif + +//***************************************************************************** +// +//! Gets the I2C Slave module status +//! +//! \param ulBase base address of the I2C Slave module +//! +//! This function will return the action requested from a master, if any. The +//! possible values returned are: +//! +//! - I2C_SLAVE_ACT_NONE +//! - I2C_SLAVE_ACT_RREQ +//! - I2C_SLAVE_ACT_TREQ +//! +//! where I2C_SLAVE_ACT_NONE means that no action has been requested of the +//! I2C Slave module, I2C_SLAVE_ACT_RREQ means that an I2C master has sent +//! data to the I2C Slave module, and I2C_SLAVE_ACT_TREQ means that an I2C +//! master has requested that the I2C Slave module send data. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_slavestatus) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +I2CSlaveStatus(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_SLAVE_BASE); + + // + // Return the slave status. + // + return(HWREG(ulBase + I2C_SLAVE_O_CSR)); +} +#endif + +//***************************************************************************** +// +//! Transmits a byte from the I2C Slave. +//! +//! \param ulBase base address of the I2C Slave module +//! \param ucData data to be transmitted from the I2C Slave +//! +//! This function will place the supplied data into I2C Slave Data Register. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_slavedataput) || defined(BUILD_ALL) || defined(DOXYGEN) +void +I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_SLAVE_BASE); + + // + // Write the byte. + // + HWREG(ulBase + I2C_SLAVE_O_DR) = ucData; +} +#endif + +//***************************************************************************** +// +//! Receives a byte that has been sent to the I2C Slave. +//! +//! \param ulBase base address of the I2C Slave module +//! +//! This function reads a byte of data from the I2C Slave Data Register. +//! +//! \return Returns the byte received from by the I2C Slave, cast as an +//! unsigned long. +// +//***************************************************************************** +#if defined(GROUP_slavedataget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +I2CSlaveDataGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == I2C_SLAVE_BASE); + + // + // Read a byte. + // + return(HWREG(ulBase + I2C_SLAVE_O_DR)); +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/i2c.h b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/i2c.h new file mode 100644 index 000000000..a9b4ad9e9 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/i2c.h @@ -0,0 +1,139 @@ +//***************************************************************************** +// +// i2c.h - Prototypes for the I2C Driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __I2C_H__ +#define __I2C_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Defines for the API. +// +//***************************************************************************** +//***************************************************************************** +// +// Interrupt defines. +// +//***************************************************************************** +#define I2C_INT_MASTER 0x00000001 +#define I2C_INT_SLAVE 0x00000002 + +//***************************************************************************** +// +// I2C Master commands. +// +//***************************************************************************** +#define I2C_MASTER_CMD_SINGLE_SEND \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_SINGLE_RECEIVE \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_SEND_START \ + (I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_SEND_CONT \ + (I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_SEND_FINISH \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \ + (I2C_MASTER_CS_STOP) +#define I2C_MASTER_CMD_BURST_RECEIVE_START \ + (I2C_MASTER_CS_ACK | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \ + (I2C_MASTER_CS_ACK | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) + +//***************************************************************************** +// +// I2C Master error status. +// +//***************************************************************************** +#define I2C_MASTER_ERR_NONE 0 +#define I2C_MASTER_ERR_ADDR_ACK 0x00000004 +#define I2C_MASTER_ERR_DATA_ACK 0x00000008 +#define I2C_MASTER_ERR_ARB_LOST 0x00000010 + +//***************************************************************************** +// +// I2C Slave action requests +// +//***************************************************************************** +#define I2C_SLAVE_ACT_NONE 0 +#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data +#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data + +//***************************************************************************** +// Miscellaneous I2C driver definitions. +//***************************************************************************** +#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void)); +extern void I2CIntUnregister(unsigned long ulBase); +extern tBoolean I2CMasterBusBusy(unsigned long ulBase); +extern tBoolean I2CMasterBusy(unsigned long ulBase); +extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd); +extern unsigned long I2CMasterDataGet(unsigned long ulBase); +extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData); +extern void I2CMasterDisable(unsigned long ulBase); +extern void I2CMasterEnable(unsigned long ulBase); +extern unsigned long I2CMasterErr(unsigned long ulBase); +extern void I2CMasterInit(unsigned long ulBase, tBoolean bFast); +extern void I2CMasterIntClear(unsigned long ulBase); +extern void I2CMasterIntDisable(unsigned long ulBase); +extern void I2CMasterIntEnable(unsigned long ulBase); +extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void I2CMasterSlaveAddrSet(unsigned long ulBase, + unsigned char ucSlaveAddr, + tBoolean bReceive); +extern unsigned long I2CSlaveDataGet(unsigned long ulBase); +extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData); +extern void I2CSlaveDisable(unsigned long ulBase); +extern void I2CSlaveEnable(unsigned long ulBase); +extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr); +extern void I2CSlaveIntClear(unsigned long ulBase); +extern void I2CSlaveIntDisable(unsigned long ulBase); +extern void I2CSlaveIntEnable(unsigned long ulBase); +extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked); +extern unsigned long I2CSlaveStatus(unsigned long ulBase); +extern void I2CMasterInitExpClk(unsigned long ulBase, unsigned long ulI2CClk, + tBoolean bFast); + +#ifdef __cplusplus +} +#endif + +#endif // __I2C_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/interrupt.c b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/interrupt.c new file mode 100644 index 000000000..7224a05d8 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/interrupt.c @@ -0,0 +1,552 @@ +//***************************************************************************** +// +// interrupt.c - Driver for the NVIC Interrupt Controller. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup interrupt_api +//! @{ +// +//***************************************************************************** + +#include "../hw_ints.h" +#include "../hw_nvic.h" +#include "../hw_types.h" +#include "cpu.h" +#include "debug.h" +#include "interrupt.h" + +//***************************************************************************** +// +// This is a mapping between priority grouping encodings and the number of +// preemption priority bits. +// +//***************************************************************************** +#if defined(GROUP_pulpriority) || defined(BUILD_ALL) +const unsigned long g_pulPriority[] = +{ + NVIC_APINT_PRIGROUP_0_8, NVIC_APINT_PRIGROUP_1_7, NVIC_APINT_PRIGROUP_2_6, + NVIC_APINT_PRIGROUP_3_5, NVIC_APINT_PRIGROUP_4_4, NVIC_APINT_PRIGROUP_5_3, + NVIC_APINT_PRIGROUP_6_2, NVIC_APINT_PRIGROUP_7_1 +}; +#else +extern const unsigned long g_pulPriority[]; +#endif + +//***************************************************************************** +// +// This is a mapping between interrupt number and the register that contains +// the priority encoding for that interrupt. +// +//***************************************************************************** +#if defined(GROUP_pulregs) || defined(BUILD_ALL) +const unsigned long g_pulRegs[12] = +{ + 0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1, + NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7 +}; +#else +extern const unsigned long g_pulRegs[12]; +#endif + +//***************************************************************************** +// +//! \internal +//! The default interrupt handler. +//! +//! This is the default interrupt handler for all interrupts. It simply loops +//! forever so that the system state is preserved for observation by a +//! debugger. Since interrupts should be disabled before unregistering the +//! corresponding handler, this should never be called. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_defaulthandler) || defined(BUILD_ALL) +void +IntDefaultHandler(void) +{ + // + // Go into an infinite loop. + // + while(1) + { + } +} +#else +extern void IntDefaultHandler(void); +#endif + +//***************************************************************************** +// +// The processor vector table. +// +// This contains a list of the handlers for the various interrupt sources in +// the system. The layout of this list is defined by the hardware; assertion +// of an interrupt causes the processor to start executing directly at the +// address given in the corresponding location in this list. +// +//***************************************************************************** +#if defined(GROUP_vtable) || defined(BUILD_ALL) +#ifdef ewarm +__no_init void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) @ "VTABLE"; +#else +__attribute__((section("vtable"))) +void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void); +#endif +#else +extern void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void); +#endif + +//***************************************************************************** +// +//! Enables the processor interrupt. +//! +//! Allows the processor to respond to interrupts. This does not affect the +//! set of interrupts enabled in the interrupt controller; it just gates the +//! single interrupt from the controller to the processor. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_masterenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +IntMasterEnable(void) +{ + // + // Enable processor interrupts. + // + CPUcpsie(); +} +#endif + +//***************************************************************************** +// +//! Disables the processor interrupt. +//! +//! Prevents the processor from receiving interrupts. This does not affect the +//! set of interrupts enabled in the interrupt controller; it just gates the +//! single interrupt from the controller to the processor. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_masterdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +IntMasterDisable(void) +{ + // + // Disable processor interrupts. + // + CPUcpsid(); +} +#endif + +//***************************************************************************** +// +//! Registers a function to be called when an interrupt occurs. +//! +//! \param ulInterrupt specifies the interrupt in question. +//! \param pfnHandler is a pointer to the function to be called. +//! +//! This function is used to specify the handler function to be called when the +//! given interrupt is asserted to the processor. When the interrupt occurs, +//! if it is enabled (via IntEnable()), the handler function will be called in +//! interrupt context. Since the handler function can preempt other code, care +//! must be taken to protect memory or peripherals that are accessed by the +//! handler and other non-handler code. +//! +//! \note The use of this function (directly or indirectly via a peripheral +//! driver interrupt register function) moves the interrupt vector table from +//! flash to SRAM. Therefore, care must be taken when linking the application +//! to ensure that the SRAM vector table is located at the beginning of SRAM; +//! otherwise NVIC will not look in the correct portion of memory for the +//! vector table (it requires the vector table be on a 1 kB memory alignment). +//! Normally, the SRAM vector table is so placed via the use of linker scripts; +//! some tool chains, such as the evaluation version of RV-MDK, do not support +//! linker scripts and therefore will not produce a valid executable. See the +//! discussion of compile-time versus run-time interrupt handler registration +//! in the introduction to this chapter. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_register) || defined(BUILD_ALL) || defined(DOXYGEN) +void +IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)) +{ + unsigned long ulIdx; + + // + // Check the arguments. + // + ASSERT(ulInterrupt < NUM_INTERRUPTS); + + // + // Make sure that the RAM vector table is correctly aligned. + // + ASSERT(((unsigned long)g_pfnRAMVectors & 0x000003ff) == 0); + + // + // See if the RAM vector table has been initialized. + // + if(HWREG(NVIC_VTABLE) != (unsigned long)g_pfnRAMVectors) + { + // + // Copy the vector table from the beginning of FLASH to the RAM vector + // table. + // + for(ulIdx = 0; ulIdx < NUM_INTERRUPTS; ulIdx++) + { + g_pfnRAMVectors[ulIdx] = (void (*)(void))HWREG(ulIdx * 4); + } + + // + // Point NVIC at the RAM vector table. + // + HWREG(NVIC_VTABLE) = (unsigned long)g_pfnRAMVectors; + } + + // + // Save the interrupt handler. + // + g_pfnRAMVectors[ulInterrupt] = pfnHandler; +} +#endif + +//***************************************************************************** +// +//! Unregisters the function to be called when an interrupt occurs. +//! +//! \param ulInterrupt specifies the interrupt in question. +//! +//! This function is used to indicate that no handler should be called when the +//! given interrupt is asserted to the processor. The interrupt source will be +//! automatically disabled (via IntDisable()) if necessary. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_unregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +IntUnregister(unsigned long ulInterrupt) +{ + // + // Check the arguments. + // + ASSERT(ulInterrupt < NUM_INTERRUPTS); + + // + // Reset the interrupt handler. + // + g_pfnRAMVectors[ulInterrupt] = IntDefaultHandler; +} +#endif + +//***************************************************************************** +// +//! Sets the priority grouping of the interrupt controller. +//! +//! \param ulBits specifies the number of bits of preemptable priority. +//! +//! This function specifies the split between preemptable priority levels and +//! subpriority levels in the interrupt priority specification. The range of +//! the grouping values are dependent upon the hardware implementation; on +//! the Stellaris family it can range from 0 to 3. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_prioritygroupingset) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +IntPriorityGroupingSet(unsigned long ulBits) +{ + // + // Check the arguments. + // + ASSERT(ulBits < NUM_PRIORITY_BITS); + + // + // Set the priority grouping. + // + HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | g_pulPriority[ulBits]; +} +#endif + +//***************************************************************************** +// +//! Gets the priority grouping of the interrupt controller. +//! +//! This function returns the split between preemptable priority levels and +//! subpriority levels in the interrupt priority specification. +//! +//! \return The number of bits of preemptable priority. +// +//***************************************************************************** +#if defined(GROUP_prioritygroupingget) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +unsigned long +IntPriorityGroupingGet(void) +{ + unsigned long ulLoop, ulValue; + + // + // Read the priority grouping. + // + ulValue = HWREG(NVIC_APINT) & NVIC_APINT_PRIGROUP_M; + + // + // Loop through the priority grouping values. + // + for(ulLoop = 0; ulLoop < 8; ulLoop++) + { + // + // Stop looping if this value matches. + // + if(ulValue == g_pulPriority[ulLoop]) + { + break; + } + } + + // + // Return the number of priority bits. + // + return(ulLoop); +} +#endif + +//***************************************************************************** +// +//! Sets the priority of an interrupt. +//! +//! \param ulInterrupt specifies the interrupt in question. +//! \param ucPriority specifies the priority of the interrupt. +//! +//! This function is used to set the priority of an interrupt. When multiple +//! interrupts are asserted simultaneously, the ones with the highest priority +//! are processed before the lower priority interrupts. Smaller numbers +//! correspond to higher interrupt priorities; priority 0 is the highest +//! interrupt priority. +//! +//! The hardware priority mechanism will only look at the upper N bits of the +//! priority level (where N is 3 for the Stellaris family), so any +//! prioritization must be performed in those bits. The remaining bits can be +//! used to sub-prioritize the interrupt sources, and may be used by the +//! hardware priority mechanism on a future part. This arrangement allows +//! priorities to migrate to different NVIC implementations without changing +//! the gross prioritization of the interrupts. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_priorityset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +IntPrioritySet(unsigned long ulInterrupt, unsigned char ucPriority) +{ + unsigned long ulTemp; + + // + // Check the arguments. + // + ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS)); + + // + // Set the interrupt priority. + // + ulTemp = HWREG(g_pulRegs[ulInterrupt >> 2]); + ulTemp &= ~(0xFF << (8 * (ulInterrupt & 3))); + ulTemp |= ucPriority << (8 * (ulInterrupt & 3)); + HWREG(g_pulRegs[ulInterrupt >> 2]) = ulTemp; +} +#endif + +//***************************************************************************** +// +//! Gets the priority of an interrupt. +//! +//! \param ulInterrupt specifies the interrupt in question. +//! +//! This function gets the priority of an interrupt. See IntPrioritySet() for +//! a definition of the priority value. +//! +//! \return Returns the interrupt priority, or -1 if an invalid interrupt was +//! specified. +// +//***************************************************************************** +#if defined(GROUP_priorityget) || defined(BUILD_ALL) || defined(DOXYGEN) +long +IntPriorityGet(unsigned long ulInterrupt) +{ + // + // Check the arguments. + // + ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS)); + + // + // Return the interrupt priority. + // + return((HWREG(g_pulRegs[ulInterrupt >> 2]) >> (8 * (ulInterrupt & 3))) & + 0xFF); +} +#endif + +//***************************************************************************** +// +//! Enables an interrupt. +//! +//! \param ulInterrupt specifies the interrupt to be enabled. +//! +//! The specified interrupt is enabled in the interrupt controller. Other +//! enables for the interrupt (such as at the peripheral level) are unaffected +//! by this function. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +IntEnable(unsigned long ulInterrupt) +{ + // + // Check the arguments. + // + ASSERT(ulInterrupt < NUM_INTERRUPTS); + + // + // Determine the interrupt to enable. + // + if(ulInterrupt == FAULT_MPU) + { + // + // Enable the MemManage interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_MEM; + } + else if(ulInterrupt == FAULT_BUS) + { + // + // Enable the bus fault interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_BUS; + } + else if(ulInterrupt == FAULT_USAGE) + { + // + // Enable the usage fault interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_USAGE; + } + else if(ulInterrupt == FAULT_SYSTICK) + { + // + // Enable the System Tick interrupt. + // + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; + } + else if(ulInterrupt >= INT_GPIOA) + { + // + // Enable the general interrupt. + // + HWREG(NVIC_EN0) = 1 << (ulInterrupt - INT_GPIOA); + } +} +#endif + +//***************************************************************************** +// +//! Disables an interrupt. +//! +//! \param ulInterrupt specifies the interrupt to be disabled. +//! +//! The specified interrupt is disabled in the interrupt controller. Other +//! enables for the interrupt (such as at the peripheral level) are unaffected +//! by this function. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +IntDisable(unsigned long ulInterrupt) +{ + // + // Check the arguments. + // + ASSERT(ulInterrupt < NUM_INTERRUPTS); + + // + // Determine the interrupt to disable. + // + if(ulInterrupt == FAULT_MPU) + { + // + // Disable the MemManage interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_MEM); + } + else if(ulInterrupt == FAULT_BUS) + { + // + // Disable the bus fault interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_BUS); + } + else if(ulInterrupt == FAULT_USAGE) + { + // + // Disable the usage fault interrupt. + // + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_USAGE); + } + else if(ulInterrupt == FAULT_SYSTICK) + { + // + // Disable the System Tick interrupt. + // + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); + } + else if(ulInterrupt >= INT_GPIOA) + { + // + // Disable the general interrupt. + // + HWREG(NVIC_DIS0) = 1 << (ulInterrupt - INT_GPIOA); + } +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/interrupt.h b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/interrupt.h new file mode 100644 index 000000000..37d414dab --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/interrupt.h @@ -0,0 +1,57 @@ +//***************************************************************************** +// +// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void IntMasterEnable(void); +extern void IntMasterDisable(void); +extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)); +extern void IntUnregister(unsigned long ulInterrupt); +extern void IntPriorityGroupingSet(unsigned long ulBits); +extern unsigned long IntPriorityGroupingGet(void); +extern void IntPrioritySet(unsigned long ulInterrupt, + unsigned char ucPriority); +extern long IntPriorityGet(unsigned long ulInterrupt); +extern void IntEnable(unsigned long ulInterrupt); +extern void IntDisable(unsigned long ulInterrupt); + +#ifdef __cplusplus +} +#endif + +#endif // __INTERRUPT_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/osram96x16.c b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/osram96x16.c new file mode 100644 index 000000000..1af1b6c2f --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/osram96x16.c @@ -0,0 +1,968 @@ +//***************************************************************************** +// +// osram96x16.c - Driver for the OSRAM 96x16 graphical OLED display. +// +// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup ev_lm3s811_api +//! @{ +// +//***************************************************************************** + +#include "DriverLib.h" +#include "osram96x16.h" +#define ewarm +//***************************************************************************** +// +// The I2C slave address of the SSD0303 controller on the OLED display. +// +//***************************************************************************** +#define SSD0303_ADDR 0x3d + +//***************************************************************************** +// +// A 5x7 font (in a 6x8 cell, where the sixth column is omitted from this +// table) for displaying text on the OLED display. The data is organized as +// bytes from the left column to the right column, with each byte containing +// the top row in the LSB and the bottom row in the MSB. +// +//***************************************************************************** +static const unsigned char g_pucFont[95][5] = +{ + { 0x00, 0x00, 0x00, 0x00, 0x00 }, // " " + { 0x00, 0x00, 0x4f, 0x00, 0x00 }, // ! + { 0x00, 0x07, 0x00, 0x07, 0x00 }, // " + { 0x14, 0x7f, 0x14, 0x7f, 0x14 }, // # + { 0x24, 0x2a, 0x7f, 0x2a, 0x12 }, // $ + { 0x23, 0x13, 0x08, 0x64, 0x62 }, // % + { 0x36, 0x49, 0x55, 0x22, 0x50 }, // & + { 0x00, 0x05, 0x03, 0x00, 0x00 }, // ' + { 0x00, 0x1c, 0x22, 0x41, 0x00 }, // ( + { 0x00, 0x41, 0x22, 0x1c, 0x00 }, // ) + { 0x14, 0x08, 0x3e, 0x08, 0x14 }, // * + { 0x08, 0x08, 0x3e, 0x08, 0x08 }, // + + { 0x00, 0x50, 0x30, 0x00, 0x00 }, // , + { 0x08, 0x08, 0x08, 0x08, 0x08 }, // - + { 0x00, 0x60, 0x60, 0x00, 0x00 }, // . + { 0x20, 0x10, 0x08, 0x04, 0x02 }, // / + { 0x3e, 0x51, 0x49, 0x45, 0x3e }, // 0 + { 0x00, 0x42, 0x7f, 0x40, 0x00 }, // 1 + { 0x42, 0x61, 0x51, 0x49, 0x46 }, // 2 + { 0x21, 0x41, 0x45, 0x4b, 0x31 }, // 3 + { 0x18, 0x14, 0x12, 0x7f, 0x10 }, // 4 + { 0x27, 0x45, 0x45, 0x45, 0x39 }, // 5 + { 0x3c, 0x4a, 0x49, 0x49, 0x30 }, // 6 + { 0x01, 0x71, 0x09, 0x05, 0x03 }, // 7 + { 0x36, 0x49, 0x49, 0x49, 0x36 }, // 8 + { 0x06, 0x49, 0x49, 0x29, 0x1e }, // 9 + { 0x00, 0x36, 0x36, 0x00, 0x00 }, // : + { 0x00, 0x56, 0x36, 0x00, 0x00 }, // ; + { 0x08, 0x14, 0x22, 0x41, 0x00 }, // < + { 0x14, 0x14, 0x14, 0x14, 0x14 }, // = + { 0x00, 0x41, 0x22, 0x14, 0x08 }, // > + { 0x02, 0x01, 0x51, 0x09, 0x06 }, // ? + { 0x32, 0x49, 0x79, 0x41, 0x3e }, // @ + { 0x7e, 0x11, 0x11, 0x11, 0x7e }, // A + { 0x7f, 0x49, 0x49, 0x49, 0x36 }, // B + { 0x3e, 0x41, 0x41, 0x41, 0x22 }, // C + { 0x7f, 0x41, 0x41, 0x22, 0x1c }, // D + { 0x7f, 0x49, 0x49, 0x49, 0x41 }, // E + { 0x7f, 0x09, 0x09, 0x09, 0x01 }, // F + { 0x3e, 0x41, 0x49, 0x49, 0x7a }, // G + { 0x7f, 0x08, 0x08, 0x08, 0x7f }, // H + { 0x00, 0x41, 0x7f, 0x41, 0x00 }, // I + { 0x20, 0x40, 0x41, 0x3f, 0x01 }, // J + { 0x7f, 0x08, 0x14, 0x22, 0x41 }, // K + { 0x7f, 0x40, 0x40, 0x40, 0x40 }, // L + { 0x7f, 0x02, 0x0c, 0x02, 0x7f }, // M + { 0x7f, 0x04, 0x08, 0x10, 0x7f }, // N + { 0x3e, 0x41, 0x41, 0x41, 0x3e }, // O + { 0x7f, 0x09, 0x09, 0x09, 0x06 }, // P + { 0x3e, 0x41, 0x51, 0x21, 0x5e }, // Q + { 0x7f, 0x09, 0x19, 0x29, 0x46 }, // R + { 0x46, 0x49, 0x49, 0x49, 0x31 }, // S + { 0x01, 0x01, 0x7f, 0x01, 0x01 }, // T + { 0x3f, 0x40, 0x40, 0x40, 0x3f }, // U + { 0x1f, 0x20, 0x40, 0x20, 0x1f }, // V + { 0x3f, 0x40, 0x38, 0x40, 0x3f }, // W + { 0x63, 0x14, 0x08, 0x14, 0x63 }, // X + { 0x07, 0x08, 0x70, 0x08, 0x07 }, // Y + { 0x61, 0x51, 0x49, 0x45, 0x43 }, // Z + { 0x00, 0x7f, 0x41, 0x41, 0x00 }, // [ + { 0x02, 0x04, 0x08, 0x10, 0x20 }, // "\" + { 0x00, 0x41, 0x41, 0x7f, 0x00 }, // ] + { 0x04, 0x02, 0x01, 0x02, 0x04 }, // ^ + { 0x40, 0x40, 0x40, 0x40, 0x40 }, // _ + { 0x00, 0x01, 0x02, 0x04, 0x00 }, // ` + { 0x20, 0x54, 0x54, 0x54, 0x78 }, // a + { 0x7f, 0x48, 0x44, 0x44, 0x38 }, // b + { 0x38, 0x44, 0x44, 0x44, 0x20 }, // c + { 0x38, 0x44, 0x44, 0x48, 0x7f }, // d + { 0x38, 0x54, 0x54, 0x54, 0x18 }, // e + { 0x08, 0x7e, 0x09, 0x01, 0x02 }, // f + { 0x0c, 0x52, 0x52, 0x52, 0x3e }, // g + { 0x7f, 0x08, 0x04, 0x04, 0x78 }, // h + { 0x00, 0x44, 0x7d, 0x40, 0x00 }, // i + { 0x20, 0x40, 0x44, 0x3d, 0x00 }, // j + { 0x7f, 0x10, 0x28, 0x44, 0x00 }, // k + { 0x00, 0x41, 0x7f, 0x40, 0x00 }, // l + { 0x7c, 0x04, 0x18, 0x04, 0x78 }, // m + { 0x7c, 0x08, 0x04, 0x04, 0x78 }, // n + { 0x38, 0x44, 0x44, 0x44, 0x38 }, // o + { 0x7c, 0x14, 0x14, 0x14, 0x08 }, // p + { 0x08, 0x14, 0x14, 0x18, 0x7c }, // q + { 0x7c, 0x08, 0x04, 0x04, 0x08 }, // r + { 0x48, 0x54, 0x54, 0x54, 0x20 }, // s + { 0x04, 0x3f, 0x44, 0x40, 0x20 }, // t + { 0x3c, 0x40, 0x40, 0x20, 0x7c }, // u + { 0x1c, 0x20, 0x40, 0x20, 0x1c }, // v + { 0x3c, 0x40, 0x30, 0x40, 0x3c }, // w + { 0x44, 0x28, 0x10, 0x28, 0x44 }, // x + { 0x0c, 0x50, 0x50, 0x50, 0x3c }, // y + { 0x44, 0x64, 0x54, 0x4c, 0x44 }, // z + { 0x00, 0x08, 0x36, 0x41, 0x00 }, // { + { 0x00, 0x00, 0x7f, 0x00, 0x00 }, // | + { 0x00, 0x41, 0x36, 0x08, 0x00 }, // } + { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~ +}; + +//***************************************************************************** +// +// The sequence of commands used to initialize the SSD0303 controller. Each +// command is described as follows: there is a byte specifying the number of +// bytes in the I2C transfer, followed by that many bytes of command data. +// +//***************************************************************************** +static const unsigned char g_pucOSRAMInit[] = +{ + // + // Turn off the panel + // + 0x04, 0x80, 0xae, 0x80, 0xe3, + + // + // Set lower column address + // + 0x04, 0x80, 0x04, 0x80, 0xe3, + + // + // Set higher column address + // + 0x04, 0x80, 0x12, 0x80, 0xe3, + + // + // Set contrast control register + // + 0x06, 0x80, 0x81, 0x80, 0x2b, 0x80, 0xe3, + + // + // Set segment re-map + // + 0x04, 0x80, 0xa1, 0x80, 0xe3, + + // + // Set display start line + // + 0x04, 0x80, 0x40, 0x80, 0xe3, + + // + // Set display offset + // + 0x06, 0x80, 0xd3, 0x80, 0x00, 0x80, 0xe3, + + // + // Set multiplex ratio + // + 0x06, 0x80, 0xa8, 0x80, 0x0f, 0x80, 0xe3, + + // + // Set the display to normal mode + // + 0x04, 0x80, 0xa4, 0x80, 0xe3, + + // + // Non-inverted display + // + 0x04, 0x80, 0xa6, 0x80, 0xe3, + + // + // Set the page address + // + 0x04, 0x80, 0xb0, 0x80, 0xe3, + + // + // Set COM output scan direction + // + 0x04, 0x80, 0xc8, 0x80, 0xe3, + + // + // Set display clock divide ratio/oscillator frequency + // + 0x06, 0x80, 0xd5, 0x80, 0x72, 0x80, 0xe3, + + // + // Enable mono mode + // + 0x06, 0x80, 0xd8, 0x80, 0x00, 0x80, 0xe3, + + // + // Set pre-charge period + // + 0x06, 0x80, 0xd9, 0x80, 0x22, 0x80, 0xe3, + + // + // Set COM pins hardware configuration + // + 0x06, 0x80, 0xda, 0x80, 0x12, 0x80, 0xe3, + + // + // Set VCOM deslect level + // + 0x06, 0x80, 0xdb, 0x80, 0x0f, 0x80, 0xe3, + + // + // Set DC-DC on + // + 0x06, 0x80, 0xad, 0x80, 0x8b, 0x80, 0xe3, + + // + // Turn on the panel + // + 0x04, 0x80, 0xaf, 0x80, 0xe3, +}; + +//***************************************************************************** +// +// The inter-byte delay required by the SSD0303 OLED controller. +// +//***************************************************************************** +static unsigned long g_ulDelay; + +//***************************************************************************** +// +//! \internal +//! +//! Provide a small delay. +//! +//! \param ulCount is the number of delay loop iterations to perform. +//! +//! Since the SSD0303 controller needs a delay between bytes written to it over +//! the I2C bus, this function provides a means of generating that delay. It +//! is written in assembly to keep the delay consistent across tool chains, +//! avoiding the need to tune the delay based on the tool chain in use. +//! +//! \return None. +// +//***************************************************************************** +#if defined(ewarm) +static void +OSRAMDelay(unsigned long ulCount) +{ + __asm(" subs r0, #1\n" + " bne.n OSRAMDelay\n" + " bx lr"); +} +#endif +#if defined(gcc) +static void __attribute__((naked)) +OSRAMDelay(unsigned long ulCount) +{ + __asm(" subs r0, #1\n" + " bne OSRAMDelay\n" + " bx lr"); +} +#endif +#if defined(rvmdk) || defined(__ARMCC_VERSION) +__asm void +OSRAMDelay(unsigned long ulCount) +{ + subs r0, #1; + bne OSRAMDelay; + bx lr; +} +#endif + +//***************************************************************************** +// +//! \internal +//! +//! Start a transfer to the SSD0303 controller. +//! +//! \param ucChar is the first byte to be written to the controller. +//! +//! This function will start a transfer to the SSD0303 controller via the I2C +//! bus. +//! +//! The data is written in a polled fashion; this function will not return +//! until the byte has been written to the controller. +//! +//! \return None. +// +//***************************************************************************** +static void +OSRAMWriteFirst(unsigned char ucChar) +{ + // + // Set the slave address. + // + I2CMasterSlaveAddrSet(I2C_MASTER_BASE, SSD0303_ADDR, false); + + // + // Write the first byte to the controller. + // + I2CMasterDataPut(I2C_MASTER_BASE, ucChar); + + // + // Start the transfer. + // + I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_START); +} + +//***************************************************************************** +// +//! \internal +//! +//! Write a byte to the SSD0303 controller. +//! +//! \param ucChar is the byte to be transmitted to the controller. +//! +//! This function continues a transfer to the SSD0303 controller by writing +//! another byte over the I2C bus. This must only be called after calling +//! OSRAMWriteFirst(), but before calling OSRAMWriteFinal(). +//! +//! The data is written in a polled faashion; this function will not return +//! until the byte has been written to the controller. +//! +//! \return None. +// +//***************************************************************************** +static void +OSRAMWriteByte(unsigned char ucChar) +{ + // + // Wait until the current byte has been transferred. + // + while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0) + { + } + + // + // Provide the required inter-byte delay. + // + OSRAMDelay(g_ulDelay); + + // + // Write the next byte to the controller. + // + I2CMasterDataPut(I2C_MASTER_BASE, ucChar); + + // + // Continue the transfer. + // + I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_CONT); +} + +//***************************************************************************** +// +//! \internal +//! +//! Write a sequence of bytes to the SSD0303 controller. +//! +//! This function continues a transfer to the SSD0303 controller by writing a +//! sequence of bytes over the I2C bus. This must only be called after calling +//! OSRAMWriteFirst(), but before calling OSRAMWriteFinal(). +//! +//! The data is written in a polled fashion; this function will not return +//! until the entire byte sequence has been written to the controller. +//! +//! \return None. +// +//***************************************************************************** +static void +OSRAMWriteArray(const unsigned char *pucBuffer, unsigned long ulCount) +{ + // + // Loop while there are more bytes left to be transferred. + // + while(ulCount != 0) + { + // + // Wait until the current byte has been transferred. + // + while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0) + { + } + + // + // Provide the required inter-byte delay. + // + OSRAMDelay(g_ulDelay); + + // + // Write the next byte to the controller. + // + I2CMasterDataPut(I2C_MASTER_BASE, *pucBuffer++); + ulCount--; + + // + // Continue the transfer. + // + I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_CONT); + } +} + +//***************************************************************************** +// +//! \internal +//! +//! Finish a transfer to the SSD0303 controller. +//! +//! \param ucChar is the final byte to be written to the controller. +//! +//! This function will finish a transfer to the SSD0303 controller via the I2C +//! bus. This must only be called after calling OSRAMWriteFirst(). +//! +//! The data is written in a polled fashion; this function will not return +//! until the byte has been written to the controller. +//! +//! \return None. +// +//***************************************************************************** +static void +OSRAMWriteFinal(unsigned char ucChar) +{ + // + // Wait until the current byte has been transferred. + // + while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0) + { + } + + // + // Provide the required inter-byte delay. + // + OSRAMDelay(g_ulDelay); + + // + // Write the final byte to the controller. + // + I2CMasterDataPut(I2C_MASTER_BASE, ucChar); + + // + // Finish the transfer. + // + I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_FINISH); + + // + // Wait until the final byte has been transferred. + // + while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0) + { + } + + // + // Provide the required inter-byte delay. + // + OSRAMDelay(g_ulDelay); +} + +//***************************************************************************** +// +//! Clears the OLED display. +//! +//! This function will clear the display. All pixels in the display will be +//! turned off. +//! +//! This function is contained in osram96x16.c, with +//! osram96x16.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAMClear(void) +{ + static const unsigned char pucRow1[] = + { + 0xb0, 0x80, 0x04, 0x80, 0x12, 0x40 + }; + static const unsigned char pucRow2[] = + { + 0xb1, 0x80, 0x04, 0x80, 0x12, 0x40 + }; + unsigned long ulIdx; + + // + // Move the display cursor to the first column of the first row. + // + OSRAMWriteFirst(0x80); + OSRAMWriteArray(pucRow1, sizeof(pucRow1)); + + // + // Fill this row with zeros. + // + for(ulIdx = 0; ulIdx < 95; ulIdx++) + { + OSRAMWriteByte(0x00); + } + OSRAMWriteFinal(0x00); + + // + // Move the display cursor to the first column of the second row. + // + OSRAMWriteFirst(0x80); + OSRAMWriteArray(pucRow2, sizeof(pucRow2)); + + // + // Fill this row with zeros. + // + for(ulIdx = 0; ulIdx < 95; ulIdx++) + { + OSRAMWriteByte(0x00); + } + OSRAMWriteFinal(0x00); +} + +//***************************************************************************** +// +//! Displays a string on the OLED display. +//! +//! \param pcStr is a pointer to the string to display. +//! \param ulX is the horizontal position to display the string, specified in +//! columns from the left edge of the display. +//! \param ulY is the vertical position to display the string, specified in +//! eight scan line blocks from the top of the display (i.e. only 0 and 1 are +//! valid). +//! +//! This function will draw a string on the display. Only the ASCII characters +//! between 32 (space) and 126 (tilde) are supported; other characters will +//! result in random data being draw on the display (based on whatever appears +//! before/after the font in memory). The font is mono-spaced, so characters +//! such as "i" and "l" have more white space around them than characters such +//! as "m" or "w". +//! +//! If the drawing of the string reaches the right edge of the display, no more +//! characters will be drawn. Therefore, special care is not required to avoid +//! supplying a string that is "too long" to display. +//! +//! This function is contained in osram96x16.c, with +//! osram96x16.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAMStringDraw(const char *pcStr, unsigned long ulX, unsigned long ulY) +{ + // + // Check the arguments. + // + ASSERT(ulX < 96); + ASSERT(ulY < 2); + + // + // Move the display cursor to the requested position on the display. + // + OSRAMWriteFirst(0x80); + OSRAMWriteByte((ulY == 0) ? 0xb0 : 0xb1); + OSRAMWriteByte(0x80); + OSRAMWriteByte((ulX + 36) & 0x0f); + OSRAMWriteByte(0x80); + OSRAMWriteByte(0x10 | (((ulX + 36) >> 4) & 0x0f)); + OSRAMWriteByte(0x40); + + // + // Loop while there are more characters in the string. + // + while(*pcStr != 0) + { + // + // See if there is enough space on the display for this entire + // character. + // + if(ulX <= 90) + { + // + // Write the contents of this character to the display. + // + OSRAMWriteArray(g_pucFont[*pcStr - ' '], 5); + + // + // See if this is the last character to display (either because the + // right edge has been reached or because there are no more + // characters). + // + if((ulX == 90) || (pcStr[1] == 0)) + { + // + // Write the final column of the display. + // + OSRAMWriteFinal(0x00); + + // + // The string has been displayed. + // + return; + } + + // + // Write the inter-character padding column. + // + OSRAMWriteByte(0x00); + } + else + { + // + // Write the portion of the character that will fit onto the + // display. + // + OSRAMWriteArray(g_pucFont[*pcStr - ' '], 95 - ulX); + OSRAMWriteFinal(g_pucFont[*pcStr - ' '][95 - ulX]); + + // + // The string has been displayed. + // + return; + } + + // + // Advance to the next character. + // + pcStr++; + + // + // Increment the X coordinate by the six columns that were just + // written. + // + ulX += 6; + } +} + +//***************************************************************************** +// +//! Displays an image on the OLED display. +//! +//! \param pucImage is a pointer to the image data. +//! \param ulX is the horizontal position to display this image, specified in +//! columns from the left edge of the display. +//! \param ulY is the vertical position to display this image, specified in +//! eight scan line blocks from the top of the display (i.e. only 0 and 1 are +//! valid). +//! \param ulWidth is the width of the image, specified in columns. +//! \param ulHeight is the height of the image, specified in eight row blocks +//! (i.e. only 1 and 2 are valid). +//! +//! This function will display a bitmap graphic on the display. The image to +//! be displayed must be a multiple of eight scan lines high (i.e. one row) and +//! will be drawn at a vertical position that is a multiple of eight scan lines +//! (i.e. scan line zero or scan line eight, corresponding to row zero or row +//! one). +//! +//! The image data is organized with the first row of image data appearing left +//! to right, followed immediately by the second row of image data. Each byte +//! contains the data for the eight scan lines of the column, with the top scan +//! line being in the least significant bit of the byte and the bottom scan +//! line being in the most significant bit of the byte. +//! +//! For example, an image four columns wide and sixteen scan lines tall would +//! be arranged as follows (showing how the eight bytes of the image would +//! appear on the display): +//! +//! \verbatim +//! +-------+ +-------+ +-------+ +-------+ +//! | | 0 | | | 0 | | | 0 | | | 0 | +//! | B | 1 | | B | 1 | | B | 1 | | B | 1 | +//! | y | 2 | | y | 2 | | y | 2 | | y | 2 | +//! | t | 3 | | t | 3 | | t | 3 | | t | 3 | +//! | e | 4 | | e | 4 | | e | 4 | | e | 4 | +//! | | 5 | | | 5 | | | 5 | | | 5 | +//! | 0 | 6 | | 1 | 6 | | 2 | 6 | | 3 | 6 | +//! | | 7 | | | 7 | | | 7 | | | 7 | +//! +-------+ +-------+ +-------+ +-------+ +//! +//! +-------+ +-------+ +-------+ +-------+ +//! | | 0 | | | 0 | | | 0 | | | 0 | +//! | B | 1 | | B | 1 | | B | 1 | | B | 1 | +//! | y | 2 | | y | 2 | | y | 2 | | y | 2 | +//! | t | 3 | | t | 3 | | t | 3 | | t | 3 | +//! | e | 4 | | e | 4 | | e | 4 | | e | 4 | +//! | | 5 | | | 5 | | | 5 | | | 5 | +//! | 4 | 6 | | 5 | 6 | | 6 | 6 | | 7 | 6 | +//! | | 7 | | | 7 | | | 7 | | | 7 | +//! +-------+ +-------+ +-------+ +-------+ +//! \endverbatim +//! +//! This function is contained in osram96x16.c, with +//! osram96x16.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAMImageDraw(const unsigned char *pucImage, unsigned long ulX, + unsigned long ulY, unsigned long ulWidth, + unsigned long ulHeight) +{ + // + // Check the arguments. + // + ASSERT(ulX < 96); + ASSERT(ulY < 2); + ASSERT((ulX + ulWidth) <= 96); + ASSERT((ulY + ulHeight) <= 2); + + // + // The first 36 columns of the LCD buffer are not displayed, so increment + // the X coorddinate by 36 to account for the non-displayed frame buffer + // memory. + // + ulX += 36; + + // + // Loop while there are more rows to display. + // + while(ulHeight--) + { + // + // Write the starting address within this row. + // + OSRAMWriteFirst(0x80); + OSRAMWriteByte((ulY == 0) ? 0xb0 : 0xb1); + OSRAMWriteByte(0x80); + OSRAMWriteByte(ulX & 0x0f); + OSRAMWriteByte(0x80); + OSRAMWriteByte(0x10 | ((ulX >> 4) & 0x0f)); + OSRAMWriteByte(0x40); + + // + // Write this row of image data. + // + OSRAMWriteArray(pucImage, ulWidth - 1); + OSRAMWriteFinal(pucImage[ulWidth - 1]); + + // + // Advance to the next row of the image. + // + pucImage += ulWidth; + ulY++; + } +} + +//***************************************************************************** +// +//! Initialize the OLED display. +//! +//! \param bFast is a boolean that is \e true if the I2C interface should be +//! run at 400 kbps and \e false if it should be run at 100 kbps. +//! +//! This function initializes the I2C interface to the OLED display and +//! configures the SSD0303 controller on the panel. +//! +//! This function is contained in osram96x16.c, with +//! osram96x16.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAMInit(tBoolean bFast) +{ + unsigned long ulIdx; + + // + // Enable the I2C and GPIO port B blocks as they are needed by this driver. + // + SysCtlPeripheralEnable(SYSCTL_PERIPH_I2C); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB); + + // + // Configure the I2C SCL and SDA pins for I2C operation. + // + GPIOPinTypeI2C(GPIO_PORTB_BASE, GPIO_PIN_2 | GPIO_PIN_3); + + // + // Initialize the I2C master. + // + I2CMasterInitExpClk(I2C_MASTER_BASE, SysCtlClockGet(), bFast); + + // + // Compute the inter-byte delay for the SSD0303 controller. This delay is + // dependent upon the I2C bus clock rate; the slower the clock the longer + // the delay required. + // + // The derivation of this formula is based on a measured delay of + // OSRAMDelay(1700) for a 100 kHz I2C bus with the CPU running at 50 MHz + // (referred to as C). To scale this to the delay for a different CPU + // speed (since this is just a CPU-based delay loop) is: + // + // f(CPU) + // C * ---------- + // 50,000,000 + // + // To then scale this to the actual I2C rate (since it won't always be + // precisely 100 kHz): + // + // f(CPU) 100,000 + // C * ---------- * ------- + // 50,000,000 f(I2C) + // + // This equation will give the inter-byte delay required for any + // configuration of the I2C master. But, as arranged it is impossible to + // directly compute in 32-bit arithmetic (without loosing a lot of + // accuracy). So, the equation is simplified. + // + // Since f(I2C) is generated by dividing down from f(CPU), replace it with + // the equivalent (where TPR is the value programmed into the Master Timer + // Period Register of the I2C master, with the 1 added back): + // + // 100,000 + // f(CPU) ------- + // C * ---------- * f(CPU) + // 50,000,000 ------------ + // 2 * 10 * TPR + // + // Inverting the dividend in the last term: + // + // f(CPU) 100,000 * 2 * 10 * TPR + // C * ---------- * ---------------------- + // 50,000,000 f(CPU) + // + // The f(CPU) now cancels out. + // + // 100,000 * 2 * 10 * TPR + // C * ---------------------- + // 50,000,000 + // + // Since there are no clock frequencies left in the equation, this equation + // also works for 400 kHz bus operation as well, since the 100,000 in the + // numerator becomes 400,000 but C is 1/4, which cancel out each other. + // Reducing the constants gives: + // + // TPR TPR TPR + // C * --- = 1700 * --- = 340 * --- = 68 * TPR + // 25 25 5 + // + // Note that the constant C is actually a bit larger than it needs to be in + // order to provide some safety margin. + // + g_ulDelay = 68 * (HWREG(I2C_MASTER_BASE + I2C_MASTER_O_TPR) + 1); + + // + // Initialize the SSD0303 controller. Loop through the initialization + // sequence doing a single I2C transfer for each command. + // + for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAMInit); + ulIdx += g_pucOSRAMInit[ulIdx] + 1) + { + // + // Send this command. + // + OSRAMWriteFirst(g_pucOSRAMInit[ulIdx + 1]); + OSRAMWriteArray(g_pucOSRAMInit + ulIdx + 2, g_pucOSRAMInit[ulIdx] - 2); + OSRAMWriteFinal(g_pucOSRAMInit[ulIdx + g_pucOSRAMInit[ulIdx]]); + } + + // + // Clear the frame buffer. + // + OSRAMClear(); +} + +//***************************************************************************** +// +//! Turns on the OLED display. +//! +//! This function will turn on the OLED display, causing it to display the +//! contents of its internal frame buffer. +//! +//! This function is contained in osram96x16.c, with +//! osram96x16.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAMDisplayOn(void) +{ + unsigned long ulIdx; + + // + // Re-initialize the SSD0303 controller. Loop through the initialization + // sequence doing a single I2C transfer for each command. + // + for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAMInit); + ulIdx += g_pucOSRAMInit[ulIdx] + 1) + { + // + // Send this command. + // + OSRAMWriteFirst(g_pucOSRAMInit[ulIdx + 1]); + OSRAMWriteArray(g_pucOSRAMInit + ulIdx + 2, g_pucOSRAMInit[ulIdx] - 2); + OSRAMWriteFinal(g_pucOSRAMInit[ulIdx + g_pucOSRAMInit[ulIdx]]); + } +} + +//***************************************************************************** +// +//! Turns off the OLED display. +//! +//! This function will turn off the OLED display. This will stop the scanning +//! of the panel and turn off the on-chip DC-DC converter, preventing damage to +//! the panel due to burn-in (it has similar characters to a CRT in this +//! respect). +//! +//! This function is contained in osram96x16.c, with +//! osram96x16.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAMDisplayOff(void) +{ + // + // Turn off the DC-DC converter and the display. + // + OSRAMWriteFirst(0x80); + OSRAMWriteByte(0xae); + OSRAMWriteByte(0x80); + OSRAMWriteByte(0xad); + OSRAMWriteByte(0x80); + OSRAMWriteFinal(0x8a); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/osram96x16.h b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/osram96x16.h new file mode 100644 index 000000000..0c9cd3692 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/osram96x16.h @@ -0,0 +1,47 @@ +//***************************************************************************** +// +// osram96x16.h - Prototypes for the driver for the OSRAM 96x16 graphical OLED +// display. +// +// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __OSRAM96X16_H__ +#define __OSRAM96X16_H__ + +//***************************************************************************** +// +// Prototypes for the driver APIs. +// +//***************************************************************************** +extern void OSRAMClear(void); +extern void OSRAMStringDraw(const char *pcStr, unsigned long ulX, + unsigned long ulY); +extern void OSRAMImageDraw(const unsigned char *pucImage, unsigned long ulX, + unsigned long ulY, unsigned long ulWidth, + unsigned long ulHeight); +extern void OSRAMInit(tBoolean bFast); +extern void OSRAMDisplayOn(void); +extern void OSRAMDisplayOff(void); + +#endif // __OSRAM96X16_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/pwm.c b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/pwm.c new file mode 100644 index 000000000..6697566ea --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/pwm.c @@ -0,0 +1,1291 @@ +//***************************************************************************** +// +// pwm.c - API for the PWM modules +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup pwm_api +//! @{ +// +//***************************************************************************** + +#include "../hw_ints.h" +#include "../hw_memmap.h" +#include "../hw_pwm.h" +#include "../hw_types.h" +#include "debug.h" +#include "interrupt.h" +#include "pwm.h" + +//***************************************************************************** +// +// Misc macros for manipulating the encoded generator and output defines used +// by the API. +// +//***************************************************************************** +#define PWM_GEN_BADDR(_mod_, _gen_) \ + ((_mod_) + (_gen_)) +#define PWM_OUT_BADDR(_mod_, _out_) \ + ((_mod_) + ((_out_) & 0xFFFFFFC0)) +#define PWM_IS_OUTPUT_ODD(_out_) \ + ((_out_) & 0x00000001) + +//***************************************************************************** +// +//! Configures a PWM generator. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to configure. Must be one of +//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. +//! \param ulConfig is the configuration for the PWM generator. +//! +//! This function is used to set the mode of operation for a PWM generator. +//! The counting mode, synchronization mode, and debug behavior are all +//! configured. After configuration, the generator is left in the disabled +//! state. +//! +//! A PWM generator can count in two different modes: count down mode or count +//! up/down mode. In count down mode, it will count from a value down to zero, +//! and then reset to the preset value. This will produce left-aligned PWM +//! signals (i.e. the rising edge of the two PWM signals produced by the +//! generator will occur at the same time). In count up/down mode, it will +//! count up from zero to the preset value, count back down to zero, and then +//! repeat the process. This will produce center-aligned PWM signals (i.e. the +//! middle of the high/low period of the PWM signals produced by the generator +//! will occur at the same time). +//! +//! When the PWM generator parameters (period and pulse width) are modified, +//! their affect on the output PWM signals can be delayed. In synchronous +//! mode, the parameter updates are not applied until a synchronization event +//! occurs. This allows multiple parameters to be modified and take affect +//! simultaneously, instead of one at a time. Additionally, parameters to +//! multiple PWM generators in synchronous mode can be updated simultaneously, +//! allowing them to be treated as if they were a unified generator. In +//! non-synchronous mode, the parameter updates are not delayed until a +//! synchronization event. In either mode, the parameter updates only occur +//! when the counter is at zero to help prevent oddly formed PWM signals during +//! the update (i.e. a PWM pulse that is too short or too long). +//! +//! The PWM generator can either pause or continue running when the processor +//! is stopped via the debugger. If configured to pause, it will continue to +//! count until it reaches zero, at which point it will pause until the +//! processor is restarted. If configured to continue running, it will keep +//! counting as if nothing had happened. +//! +//! The \b ulConfig parameter contains the desired configuration. It is the +//! logical OR of the following: \b PWM_GEN_MODE_DOWN or +//! \b PWM_GEN_MODE_UP_DOWN to specify the counting mode, \b PWM_GEN_MODE_SYNC +//! or \b PWM_GEN_MODE_NO_SYNC to specify the synchronization mode, and +//! \b PWM_GEN_MODE_DBG_RUN or \b PWM_GEN_MODE_DBG_STOP to specify the debug +//! behavior. +//! +//! \note Changes to the counter mode will affect the period of the PWM signals +//! produced. PWMGenPeriodSet() and PWMPulseWidthSet() should be called after +//! any changes to the counter mode of a generator. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_genconfigure) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMGenConfigure(unsigned long ulBase, unsigned long ulGen, + unsigned long ulConfig) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + + // + // Compute the generator's base address. + // + ulGen = PWM_GEN_BADDR(ulBase, ulGen); + + // + // Change the global configuration of the generator. + // + HWREG(ulGen + PWM_O_X_CTL) = ((HWREG(ulGen + PWM_O_X_CTL) & + ~(PWM_X_CTL_MODE | PWM_X_CTL_DEBUG | + PWM_X_CTL_LOADUPD | PWM_X_CTL_CMPAUPD | + PWM_X_CTL_CMPBUPD)) | ulConfig); + + // + // Set the individual PWM generator controls. + // + if(ulConfig & PWM_X_CTL_MODE) + { + // + // In up/down count mode, set the signal high on up count comparison + // and low on down count comparison (i.e. center align the signals). + // + HWREG(ulGen + PWM_O_X_GENA) = ((PWM_GEN_ACT_ONE << + PWM_GEN_ACT_A_UP_SHIFT) | + (PWM_GEN_ACT_ZERO << + PWM_GEN_ACT_A_DN_SHIFT)); + HWREG(ulGen + PWM_O_X_GENB) = ((PWM_GEN_ACT_ONE << + PWM_GEN_ACT_B_UP_SHIFT) | + (PWM_GEN_ACT_ZERO << + PWM_GEN_ACT_B_DN_SHIFT)); + } + else + { + // + // In down count mode, set the signal high on load and low on count + // comparison (i.e. left align the signals). + // + HWREG(ulGen + PWM_O_X_GENA) = ((PWM_GEN_ACT_ONE << + PWM_GEN_ACT_LOAD_SHIFT) | + (PWM_GEN_ACT_ZERO << + PWM_GEN_ACT_A_DN_SHIFT)); + HWREG(ulGen + PWM_O_X_GENB) = ((PWM_GEN_ACT_ONE << + PWM_GEN_ACT_LOAD_SHIFT) | + (PWM_GEN_ACT_ZERO << + PWM_GEN_ACT_B_DN_SHIFT)); + } +} +#endif + +//***************************************************************************** +// +//! Set the period of a PWM generator. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to be modified. Must be one of +//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. +//! \param ulPeriod specifies the period of PWM generator output, measured +//! in clock ticks. +//! +//! This function sets the period of the specified PWM generator block, where +//! the period of the generator block is defined as the number of \b PWM +//! clock ticks between pulses on the generator block \b zero signal. +//! +//! \note Any subsequent calls made to this function before an update occurs +//! will cause the previous values to be overwritten. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_genperiodset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen, + unsigned long ulPeriod) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + + // + // Compute the generator's base address. + // + ulGen = PWM_GEN_BADDR(ulBase, ulGen); + + // + // Set the reload register based on the mode. + // + if(HWREG(ulGen + PWM_O_X_CTL) & PWM_X_CTL_MODE) + { + // + // In up/down count mode, set the reload register to half the requested + // period. + // + ASSERT((ulPeriod / 2) < 65536); + HWREG(ulGen + PWM_O_X_LOAD) = ulPeriod / 2; + } + else + { + // + // In down count mode, set the reload register to the requested period + // minus one. + // + ASSERT((ulPeriod <= 65536) && (ulPeriod != 0)); + HWREG(ulGen + PWM_O_X_LOAD) = ulPeriod - 1; + } +} +#endif + +//***************************************************************************** +// +//! Gets the period of a PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to query. Must be one of +//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. +//! +//! This function gets the period of the specified PWM generator block. The +//! period of the generator block is defined as the number of \b PWM clock +//! ticks between pulses on the generator block \b zero signal. +//! +//! If the update of the counter for the specified PWM generator has yet +//! to be completed, the value returned may not be the active period. The +//! value returned is the programmed period, measured in \b PWM clock ticks. +//! +//! \return Returns the programmed period of the specified generator block +//! in \b PWM clock ticks. +// +//***************************************************************************** +#if defined(GROUP_genperiodget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +PWMGenPeriodGet(unsigned long ulBase, unsigned long ulGen) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + + // + // Compute the generator's base address. + // + ulGen = PWM_GEN_BADDR(ulBase, ulGen); + + // + // Figure out the counter mode. + // + if(HWREG(ulGen + PWM_O_X_CTL) & PWM_X_CTL_MODE) + { + // + // The period is twice the reload register value. + // + return(HWREG(ulGen + PWM_O_X_LOAD) * 2); + } + else + { + // + // The period is the reload register value plus one. + // + return(HWREG(ulGen + PWM_O_X_LOAD) + 1); + } +} +#endif + +//***************************************************************************** +// +//! Enables the timer/counter for a PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to be enabled. Must be one of +//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. +//! +//! This function allows the \b PWM clock to drive the timer/counter for the +//! specified generator block. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_genenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMGenEnable(unsigned long ulBase, unsigned long ulGen) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + + // + // Enable the PWM generator. + // + HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_CTL) |= PWM_X_CTL_ENABLE; +} +#endif + +//***************************************************************************** +// +//! Disables the timer/counter for a PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to be disabled. Must be one of +//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. +//! +//! This function blocks the \b PWM clock from driving the timer/counter for +//! the specified generator block. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_gendisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMGenDisable(unsigned long ulBase, unsigned long ulGen) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + + // + // Disable the PWM generator. + // + HWREG(PWM_GEN_BADDR(ulBase, + ulGen) + PWM_O_X_CTL) &= ~(PWM_X_CTL_ENABLE); +} +#endif + +//***************************************************************************** +// +//! Sets the pulse width for the specified PWM output. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulPWMOut is the PWM output to modify. Must be one of \b PWM_OUT_0, +//! \b PWM_OUT_1, \b PWM_OUT_2, \b PWM_OUT_3, \b PWM_OUT_4, or \b PWM_OUT_5. +//! \param ulWidth specifies the width of the positive portion of the pulse. +//! +//! This function sets the pulse width for the specified PWM output, where the +//! pulse width is defined as the number of \b PWM clock ticks. +//! +//! \note Any subsequent calls made to this function before an update occurs +//! will cause the previous values to be overwritten. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pulsewidthset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut, + unsigned long ulWidth) +{ + unsigned long ulGenBase, ulReg; + + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulPWMOut == PWM_OUT_0) || (ulPWMOut == PWM_OUT_1) || + (ulPWMOut == PWM_OUT_2) || (ulPWMOut == PWM_OUT_3) || + (ulPWMOut == PWM_OUT_4) || (ulPWMOut == PWM_OUT_5)); + + // + // Compute the generator's base address. + // + ulGenBase = PWM_OUT_BADDR(ulBase, ulPWMOut); + + // + // If the counter is in up/down count mode, divide the width by two. + // + if(HWREG(ulGenBase + PWM_O_X_CTL) & PWM_X_CTL_MODE) + { + ulWidth /= 2; + } + + // + // Get the period. + // + ulReg = HWREG(ulGenBase + PWM_O_X_LOAD); + + // + // Make sure the width is not too large. + // + ASSERT(ulWidth < ulReg); + + // + // Compute the compare value. + // + ulReg = ulReg - ulWidth; + + // + // Write to the appropriate registers. + // + if(PWM_IS_OUTPUT_ODD(ulPWMOut)) + { + HWREG(ulGenBase + PWM_O_X_CMPB) = ulReg; + } + else + { + HWREG(ulGenBase + PWM_O_X_CMPA) = ulReg; + } +} +#endif + +//***************************************************************************** +// +//! Gets the pulse width of a PWM output. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulPWMOut is the PWM output to query. Must be one of \b PWM_OUT_0, +//! \b PWM_OUT_1, \b PWM_OUT_2, \b PWM_OUT_3, \b PWM_OUT_4, or \b PWM_OUT_5. +//! +//! This function gets the currently programmed pulse width for the +//! specified PWM output. If the update of the comparator for the specified +//! output has yet to be completed, the value returned may not be the active +//! pulse width. The value returned is the programmed pulse width, measured +//! in \b PWM clock ticks. +//! +//! \return Returns the width of the pulse in \b PWM clock ticks. +// +//***************************************************************************** +#if defined(GROUP_pulsewidthget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +PWMPulseWidthGet(unsigned long ulBase, unsigned long ulPWMOut) +{ + unsigned long ulGenBase, ulReg, ulLoad; + + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulPWMOut == PWM_OUT_0) || (ulPWMOut == PWM_OUT_1) || + (ulPWMOut == PWM_OUT_2) || (ulPWMOut == PWM_OUT_3) || + (ulPWMOut == PWM_OUT_4) || (ulPWMOut == PWM_OUT_5)); + + // + // Compute the generator's base address. + // + ulGenBase = PWM_OUT_BADDR(ulBase, ulPWMOut); + + // + // Then compute the pulse width. If mode is UpDown, set + // width = (load-compare)*2. Otherwise, set width = load - compare + // + ulLoad = HWREG(ulGenBase + PWM_O_X_LOAD); + if(PWM_IS_OUTPUT_ODD(ulPWMOut)) + { + ulReg = HWREG(ulGenBase + PWM_O_X_CMPB); + } + else + { + ulReg = HWREG(ulGenBase + PWM_O_X_CMPA); + } + ulReg = ulLoad - ulReg; + + // + // If in up/down count mode, double the pulse width. + // + if(HWREG(ulGenBase + PWM_O_X_CTL) & PWM_X_CTL_MODE) + { + ulReg = ulReg * 2; + } + + // + // Return the pulse width. + // + return(ulReg); +} +#endif + +//***************************************************************************** +// +//! Enables the PWM dead band output, and sets the dead band delays. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to modify. Must be one of +//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. +//! \param usRise specifies the width of delay from the rising edge. +//! \param usFall specifies the width of delay from the falling edge. +//! +//! This function sets the dead bands for the specified PWM generator, +//! where the dead bands are defined as the number of \b PWM clock ticks +//! from the rising or falling edge of the generator's \b OutA signal. +//! Note that this function causes the coupling of \b OutB to \b OutA. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_deadbandenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen, + unsigned short usRise, unsigned short usFall) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + ASSERT(usRise < 4096); + ASSERT(usFall < 4096); + + // + // Compute the generator's base address. + // + ulGen = PWM_GEN_BADDR(ulBase, ulGen); + + // + // Write the dead band delay values. + // + HWREG(ulGen + PWM_O_X_DBRISE) = usRise; + HWREG(ulGen + PWM_O_X_DBFALL) = usFall; + + // + // Enable the deadband functionality. + // + HWREG(ulGen + PWM_O_X_DBCTL) |= PWM_DBCTL_ENABLE; +} +#endif + +//***************************************************************************** +// +//! Disables the PWM dead band output. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to modify. Must be one of +//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. +//! +//! This function disables the dead band mode for the specified PWM generator. +//! Doing so decouples the \b OutA and \b OutB signals. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_deadbanddisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + + // + // Disable the deadband functionality. + // + HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_DBCTL) &= ~(PWM_DBCTL_ENABLE); +} +#endif + +//***************************************************************************** +// +//! Synchronizes all pending updates. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGenBits are the PWM generator blocks to be updated. Must be the +//! logical OR of any of \b PWM_GEN_0_BIT, \b PWM_GEN_1_BIT, or +//! \b PWM_GEN_2_BIT. +//! +//! For the selected PWM generators, this function causes all queued updates to +//! the period or pulse width to be applied the next time the corresponding +//! counter becomes zero. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_syncupdate) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT(!(ulGenBits & ~(PWM_GEN_0_BIT | PWM_GEN_1_BIT | PWM_GEN_2_BIT))); + + // + // Update the PWM timing registers. + // + HWREG(ulBase + PWM_O_CTL) = ulGenBits; +} +#endif + +//***************************************************************************** +// +//! Synchronizes the counters in one or multiple PWM generator blocks. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGenBits are the PWM generator blocks to be synchronized. Must be +//! the logical OR of any of \b PWM_GEN_0_BIT, \b PWM_GEN_1_BIT, or +//! \b PWM_GEN_2_BIT. +//! +//! For the selected PWM module, this function synchronizes the time base +//! of the generator blocks by causing the specified generator counters to be +//! reset to zero. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_synctimebase) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT(!(ulGenBits & ~(PWM_GEN_0_BIT | PWM_GEN_1_BIT | PWM_GEN_2_BIT))); + + // + // Synchronize the counters in the specified generators by writing to + // the module's synchronization register. + // + HWREG(ulBase + PWM_O_SYNC) = ulGenBits; +} +#endif + +//***************************************************************************** +// +//! Enables or disables PWM outputs. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the +//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT, +//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, or \b PWM_OUT_5_BIT. +//! \param bEnable determines if the signal is enabled or disabled. +//! +//! This function is used to enable or disable the selected PWM outputs. The +//! outputs are selected using the parameter \e ulPWMOutBits. The parameter +//! \e bEnable determines the state of the selected outputs. If \e bEnable is +//! \b true, then the selected PWM outputs are enabled, or placed in the active +//! state. If \e bEnable is \b false, then the selected outputs are disabled, +//! or placed in the inactive state. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_outputstate) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bEnable) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT | + PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT))); + + // + // Read the module's ENABLE output control register, and set or clear + // the requested bits. + // + if(bEnable == true) + { + HWREG(ulBase + PWM_O_ENABLE) |= ulPWMOutBits; + } + else + { + HWREG(ulBase + PWM_O_ENABLE) &= ~(ulPWMOutBits); + } +} +#endif + +//***************************************************************************** +// +//! Selects the inversion mode for PWM outputs. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the +//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT, +//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, or \b PWM_OUT_5_BIT. +//! \param bInvert determines if the signal is inverted or passed through. +//! +//! This function is used to select the inversion mode for the selected PWM +//! outputs. The outputs are selected using the parameter \e ulPWMOutBits. +//! The parameter \e bInvert determines the inversion mode for the selected +//! outputs. If \e bInvert is \b true, this function will cause the specified +//! PWM output signals to be inverted, or made active low. If \e bInvert is +//! \b false, the specified output will be passed through as is, or be made +//! active high. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_outputinvert) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bInvert) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT | + PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT))); + + // + // Read the module's INVERT output control register, and set or clear + // the requested bits. + // + if(bInvert == true) + { + HWREG(ulBase + PWM_O_INVERT) |= ulPWMOutBits; + } + else + { + HWREG(ulBase + PWM_O_INVERT) &= ~(ulPWMOutBits); + } +} +#endif + +//***************************************************************************** +// +//! Specifies the state of PWM outputs in response to a fault condition. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the +//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT, +//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, or \b PWM_OUT_5_BIT. +//! \param bFaultKill determines if the signal is killed or passed through +//! during an active fault condition. +//! +//! This function sets the fault handling characteristics of the selected PWM +//! outputs. The outputs are selected using the parameter \e ulPWMOutBits. +//! The parameter \e bFaultKill determines the fault handling characteristics +//! for the selected outputs. If \e bFaultKill is \b true, then the selected +//! outputs will be made inactive. If \e bFaultKill is \b false, then the +//! selected outputs are unaffected by the detected fault. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_outputfault) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bFaultKill) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT | + PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT))); + + // + // Read the module's FAULT output control register, and set or clear + // the requested bits. + // + if(bFaultKill == true) + { + HWREG(ulBase + PWM_O_FAULT) |= ulPWMOutBits; + } + else + { + HWREG(ulBase + PWM_O_FAULT) &= ~(ulPWMOutBits); + } +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for the specified PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator in question. +//! \param pfnIntHandler is a pointer to the function to be called when the PWM +//! generator interrupt occurs. +//! +//! This function will ensure that the interrupt handler specified by +//! \e pfnIntHandler is called when an interrupt is detected for the specified +//! PWM generator block. This function will also enable the corresponding +//! PWM generator interrupt in the interrupt controller; individual generator +//! interrupts and interrupt sources must be enabled with PWMIntEnable() and +//! PWMGenIntTrigEnable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_genintregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen, + void (*pfnIntHandler)(void)) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + + // + // Get the interrupt number associated with the specified generator. + // + ulInt = INT_PWM0 + (ulGen >> 6) - 1; + + // + // Register the interrupt handler. + // + IntRegister(ulInt, pfnIntHandler); + + // + // Enable the PWMx interrupt. + // + IntEnable(ulInt); +} +#endif + +//***************************************************************************** +// +//! Removes an interrupt handler for the specified PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator in question. +//! +//! This function will unregister the interrupt handler for the specified +//! PWM generator block. This function will also disable the corresponding +//! PWM generator interrupt in the interrupt controller; individual generator +//! interrupts and interrupt sources must be disabled with PWMIntDisable() and +//! PWMGenIntTrigDisable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_genintunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + + // + // Get the interrupt number associated with the specified generator. + // + ulInt = INT_PWM0 + (ulGen >> 6) - 1; + + // + // Disable the PWMx interrupt. + // + IntDisable(ulInt); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulInt); +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for a fault condition detected in a PWM +//! module. +//! +//! \param ulBase is the base address of the PWM module. +//! \param pfnIntHandler is a pointer to the function to be called when the PWM +//! fault interrupt occurs. +//! +//! This function will ensure that the interrupt handler specified by +//! \e pfnIntHandler is called when a fault interrupt is detected for the +//! selected PWM module. This function will also enable the PWM fault +//! interrupt in the NVIC; the PWM fault interrupt must also be enabled at the +//! module level using PWMIntEnable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_faultintregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMFaultIntRegister(unsigned long ulBase, void (*pfnIntHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + + // + // Register the interrupt handler, returning an error if one occurs. + // + IntRegister(INT_PWM_FAULT, pfnIntHandler); + + // + // Enable the PWM fault interrupt. + // + IntEnable(INT_PWM_FAULT); +} +#endif + +//***************************************************************************** +// +//! Removes the PWM fault condition interrupt handler. +//! +//! \param ulBase is the base address of the PWM module. +//! +//! This function will remove the interrupt handler for a PWM fault interrupt +//! from the selected PWM module. This function will also disable the PWM +//! fault interrupt in the NVIC; the PWM fault interrupt must also be disabled +//! at the module level using PWMIntDisable(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_faultintunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMFaultIntUnregister(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + + // + // Disable the PWM fault interrupt. + // + IntDisable(INT_PWM_FAULT); + + // + // Unregister the interrupt handler, returning an error if one occurs. + // + IntUnregister(INT_PWM_FAULT); +} +#endif + +//***************************************************************************** +// +//! Enables interrupts and triggers for the specified PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to have interrupts and triggers enabled. +//! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. +//! \param ulIntTrig specifies the interrupts and triggers to be enabled. +//! +//! Unmasks the specified interrupt(s) and trigger(s) by setting the +//! specified bits of the interrupt/trigger enable register for the specified +//! PWM generator. The defined values for the bits are as follows: +//! +//! - PWM_INT_CNT_ZERO +//! - PWM_INT_CNT_LOAD +//! - PWM_INT_CMP_AU +//! - PWM_INT_CMP_AD +//! - PWM_INT_CMP_BU +//! - PWM_INT_CMP_BD +//! - PWM_TR_CNT_ZERO +//! - PWM_TR_CNT_LOAD +//! - PWM_TR_CMP_AU +//! - PWM_TR_CMP_AD +//! - PWM_TR_CMP_BU +//! - PWM_TR_CMP_BD +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_geninttrigenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen, + unsigned long ulIntTrig) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + + // + // Enable the specified interrupts/triggers. + // + HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_INTEN) |= ulIntTrig; +} +#endif + +//***************************************************************************** +// +//! Disables interrupts for the specified PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to have interrupts and triggers disabled. +//! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. +//! \param ulIntTrig specifies the interrupts and triggers to be disabled. +//! +//! Masks the specified interrupt(s) and trigger(s) by clearing the +//! specified bits of the interrupt/trigger enable register for the specified +//! PWM generator. The defined values for the bits are as follows: +//! +//! - PWM_INT_CNT_ZERO +//! - PWM_INT_CNT_LOAD +//! - PWM_INT_CMP_AU +//! - PWM_INT_CMP_AD +//! - PWM_INT_CMP_BU +//! - PWM_INT_CMP_BD +//! - PWM_TR_CNT_ZERO +//! - PWM_TR_CNT_LOAD +//! - PWM_TR_CMP_AU +//! - PWM_TR_CMP_AD +//! - PWM_TR_CMP_BU +//! - PWM_TR_CMP_BD +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_geninttrigdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen, + unsigned long ulIntTrig) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + + // + // Disable the specified interrupts/triggers. + // + HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_INTEN) &= ~(ulIntTrig); +} +#endif + +//***************************************************************************** +// +//! Gets interrupt status for the specified PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to query. Must be one of \b PWM_GEN_0, +//! \b PWM_GEN_1, or \b PWM_GEN_2. +//! \param bMasked specifies whether masked or raw interrupt status is +//! returned. +//! +//! If \e bMasked is set as \b true, then the masked interrupt status is +//! returned; otherwise, the raw interrupt status will be returned. +//! +//! \return Returns the contents of the interrupt status register, or the +//! contents of the raw interrupt status register, for the specified +//! PWM generator. +// +//***************************************************************************** +#if defined(GROUP_genintstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + + // + // Compute the generator's base address. + // + ulGen = PWM_GEN_BADDR(ulBase, ulGen); + + // + // Read and return the specified generator's raw or enabled interrupt + // status. + // + if(bMasked == true) + { + return(HWREG(ulGen + PWM_O_X_ISC)); + } + else + { + return(HWREG(ulGen + PWM_O_X_RIS)); + } +} +#endif + +//***************************************************************************** +// +//! Clears the specified interrupt(s) for the specified PWM generator block. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGen is the PWM generator to query. Must be one of \b PWM_GEN_0, +//! \b PWM_GEN_1, or \b PWM_GEN_2. +//! \param ulInts specifies the interrupts to be cleared. +//! +//! Clears the specified interrupt(s) by writing a 1 to the specified bits +//! of the interrupt status register for the specified PWM generator. The +//! defined values for the bits are as follows: +//! +//! - PWM_INT_CNT_ZERO +//! - PWM_INT_CNT_LOAD +//! - PWM_INT_CMP_AU +//! - PWM_INT_CMP_AD +//! - PWM_INT_CMP_BU +//! - PWM_INT_CMP_BD +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_genintclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMGenIntClear(unsigned long ulBase, unsigned long ulGen, unsigned long ulInts) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || + (ulGen == PWM_GEN_2)); + + // + // Clear the requested interrupts by writing ones to the specified bit + // of the module's interrupt enable register. + // + HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_ISC) = ulInts; +} +#endif + +//***************************************************************************** +// +//! Enables generator and fault interrupts for a PWM module. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGenFault contains the interrupts to be enabled. Must be a logical +//! OR of any of \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2, or +//! \b PWM_INT_FAULT. +//! +//! Unmasks the specified interrupt(s) by setting the specified bits of +//! the interrupt enable register for the selected PWM module. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + + // + // Read the module's interrupt enable register, and enable interrupts + // for the specified PWM generators. + // + HWREG(ulBase + PWM_O_INTEN) |= ulGenFault; +} +#endif + +//***************************************************************************** +// +//! Disables generator and fault interrupts for a PWM module. +//! +//! \param ulBase is the base address of the PWM module. +//! \param ulGenFault contains the interrupts to be disabled. Must be a +//! logical OR of any of \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2, +//! or \b PWM_INT_FAULT. +//! +//! Masks the specified interrupt(s) by clearing the specified bits of +//! the interrupt enable register for the selected PWM module. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + + // + // Read the module's interrupt enable register, and disable interrupts + // for the specified PWM generators. + // + HWREG(ulBase + PWM_O_INTEN) &= ~(ulGenFault); +} +#endif + +//***************************************************************************** +// +//! Clears the fault interrupt for a PWM module. +//! +//! \param ulBase is the base address of the PWM module. +//! +//! Clears the fault interrupt by writing to the appropriate bit of the +//! interrupt status register for the selected PWM module. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_faultintclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +PWMFaultIntClear(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + + // + // Write the only writeable bit in the module's interrupt register. + // + HWREG(ulBase + PWM_O_ISC) = PWM_INT_INTFAULT; +} +#endif + +//***************************************************************************** +// +//! Gets the interrupt status for a PWM module. +//! +//! \param ulBase is the base address of the PWM module. +//! \param bMasked specifies whether masked or raw interrupt status is +//! returned. +//! +//! If \e bMasked is set as \b true, then the masked interrupt status is +//! returned; otherwise, the raw interrupt status will be returned. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2, and \b PWM_INT_FAULT. +//! +//***************************************************************************** +#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +PWMIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == PWM_BASE); + + // + // Read and return either the module's raw or enabled interrupt status. + // + if(bMasked == true) + { + return(HWREG(ulBase + PWM_O_ISC)); + } + else + { + return(HWREG(ulBase + PWM_O_RIS)); + } +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/pwm.h b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/pwm.h new file mode 100644 index 000000000..db835bacd --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/pwm.h @@ -0,0 +1,161 @@ +//***************************************************************************** +// +// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __PWM_H__ +#define __PWM_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following defines are passed to PWMGenConfigure() as the ulConfig +// parameter and specify the configuration of the PWM generator. +// +//***************************************************************************** +#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode +#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode +#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates +#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates +#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode +#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode + +//***************************************************************************** +// +// Defines for enabling, disabling, and clearing PWM generator interrupts and +// triggers. +// +//***************************************************************************** +#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0 +#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD +#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U +#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D +#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U +#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D +#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0 +#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD +#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U +#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D +#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U +#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D + +//***************************************************************************** +// +// Defines for enabling, disabling, and clearing PWM interrupts. +// +//***************************************************************************** +#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt +#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt +#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt +#define PWM_INT_FAULT 0x00010000 // Fault interrupt + +//***************************************************************************** +// +// Defines to identify the generators within a module. +// +//***************************************************************************** +#define PWM_GEN_0 0x00000040 // Offset address of Gen0 +#define PWM_GEN_1 0x00000080 // Offset address of Gen1 +#define PWM_GEN_2 0x000000C0 // Offset address of Gen2 + +#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0 +#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1 +#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2 + +//***************************************************************************** +// +// Defines to identify the outputs within a module. +// +//***************************************************************************** +#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0 +#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1 +#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2 +#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3 +#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4 +#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5 + +#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0 +#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1 +#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2 +#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3 +#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4 +#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5 + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen, + unsigned long ulConfig); +extern void PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen, + unsigned long ulPeriod); +extern unsigned long PWMGenPeriodGet(unsigned long ulBase, + unsigned long ulGen); +extern void PWMGenEnable(unsigned long ulBase, unsigned long ulGen); +extern void PWMGenDisable(unsigned long ulBase, unsigned long ulGen); +extern void PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut, + unsigned long ulWidth); +extern unsigned long PWMPulseWidthGet(unsigned long ulBase, + unsigned long ulPWMOut); +extern void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen, + unsigned short usRise, unsigned short usFall); +extern void PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen); +extern void PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits); +extern void PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits); +extern void PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bEnable); +extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bInvert); +extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bFaultKill); +extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen, + void (*pfnIntHandler)(void)); +extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen); +extern void PWMFaultIntRegister(unsigned long ulBase, + void (*pfnIntHandler)(void)); +extern void PWMFaultIntUnregister(unsigned long ulBase); +extern void PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen, + unsigned long ulIntTrig); +extern void PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen, + unsigned long ulIntTrig); +extern unsigned long PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen, + tBoolean bMasked); +extern void PWMGenIntClear(unsigned long ulBase, unsigned long ulGen, + unsigned long ulInts); +extern void PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault); +extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault); +extern void PWMFaultIntClear(unsigned long ulBase); +extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked); + +#ifdef __cplusplus +} +#endif + +#endif // __PWM_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/qei.c b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/qei.c new file mode 100644 index 000000000..eb982de39 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/qei.c @@ -0,0 +1,630 @@ +//***************************************************************************** +// +// qei.c - Driver for the Quadrature Encoder with Index. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup qei_api +//! @{ +// +//***************************************************************************** + +#include "../hw_ints.h" +#include "../hw_memmap.h" +#include "../hw_qei.h" +#include "../hw_types.h" +#include "debug.h" +#include "interrupt.h" +#include "qei.h" + +//***************************************************************************** +// +//! Enables the quadrature encoder. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This will enable operation of the quadrature encoder module. It must be +//! configured before it is enabled. +//! +//! \sa QEIConfigure() +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +QEIEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Enable the QEI module. + // + HWREG(ulBase + QEI_O_CTL) |= QEI_CTL_ENABLE; +} +#endif + +//***************************************************************************** +// +//! Disables the quadrature encoder. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This will disable operation of the quadrature encoder module. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +QEIDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Disable the QEI module. + // + HWREG(ulBase + QEI_O_CTL) &= ~(QEI_CTL_ENABLE); +} +#endif + +//***************************************************************************** +// +//! Configures the quadrature encoder. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! \param ulConfig is the configuration for the quadrature encoder. See below +//! for a description of this parameter. +//! \param ulMaxPosition specifies the maximum position value. +//! +//! This will configure the operation of the quadrature encoder. The +//! \e ulConfig parameter provides the configuration of the encoder and is the +//! logical OR of several values: +//! +//! - \b QEI_CONFIG_CAPTURE_A or \b QEI_CONFIG_CAPTURE_A_B to specify if edges +//! on channel A or on both channels A and B should be counted by the +//! position integrator and velocity accumulator. +//! - \b QEI_CONFIG_NO_RESET or \b QEI_CONFIG_RESET_IDX to specify if the +//! position integrator should be reset when the index pulse is detected. +//! - \b QEI_CONFIG_QUADRATURE or \b QEI_CONFIG_CLOCK_DIR to specify if +//! quadrature signals are being provided on ChA and ChB, or if a direction +//! signal and a clock are being provided instead. +//! - \b QEI_CONFIG_NO_SWAP or \b QEI_CONFIG_SWAP to specify if the signals +//! provided on ChA and ChB should be swapped before being processed. +//! +//! \e ulMaxPosition is the maximum value of the position integrator, and is +//! the value used to reset the position capture when in index reset mode and +//! moving in the reverse (negative) direction. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_configure) || defined(BUILD_ALL) || defined(DOXYGEN) +void +QEIConfigure(unsigned long ulBase, unsigned long ulConfig, + unsigned long ulMaxPosition) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Write the new configuration to the hardware. + // + HWREG(ulBase + QEI_O_CTL) = ((HWREG(ulBase + QEI_O_CTL) & + ~(QEI_CTL_CAPMODE | QEI_CTL_RESMODE | + QEI_CTL_SIGMODE | QEI_CTL_SWAP)) | + ulConfig); + + // + // Set the maximum position. + // + HWREG(ulBase + QEI_O_MAXPOS) = ulMaxPosition; +} +#endif + +//***************************************************************************** +// +//! Gets the current encoder position. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This returns the current position of the encoder. Depending upon the +//! configuration of the encoder, and the incident of an index pulse, this +//! value may or may not contain the expected data (i.e. if in reset on index +//! mode, if an index pulse has not been encountered, the position counter will +//! not be aligned with the index pulse yet). +//! +//! \return The current position of the encoder. +// +//***************************************************************************** +#if defined(GROUP_positionget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +QEIPositionGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Return the current position counter. + // + return(HWREG(ulBase + QEI_O_POS)); +} +#endif + +//***************************************************************************** +// +//! Sets the current encoder position. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! \param ulPosition is the new position for the encoder. +//! +//! This sets the current position of the encoder; the encoder position will +//! then be measured relative to this value. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_positionset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +QEIPositionSet(unsigned long ulBase, unsigned long ulPosition) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Set the position counter. + // + HWREG(ulBase + QEI_O_POS) = ulPosition; +} +#endif + +//***************************************************************************** +// +//! Gets the current direction of rotation. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This returns the current direction of rotation. In this case, current +//! means the most recently detected direction of the encoder; it may not be +//! presently moving but this is the direction it last moved before it stopped. +//! +//! \return 1 if moving in the forward direction or -1 if moving in the reverse +//! direction. +// +//***************************************************************************** +#if defined(GROUP_directionget) || defined(BUILD_ALL) || defined(DOXYGEN) +long +QEIDirectionGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Return the direction of rotation. + // + return((HWREG(ulBase + QEI_O_STAT) & QEI_STAT_DIRECTION) ? -1 : 1); +} +#endif + +//***************************************************************************** +// +//! Gets the encoder error indicator. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This returns the error indicator for the quadrature encoder. It is an +//! error for both of the signals of the quadrature input to change at the same +//! time. +//! +//! \return true if an error has occurred and false otherwise. +// +//***************************************************************************** +#if defined(GROUP_errorget) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +QEIErrorGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Return the error indicator. + // + return((HWREG(ulBase + QEI_O_STAT) & QEI_STAT_ERROR) ? true : false); +} +#endif + +//***************************************************************************** +// +//! Enables the velocity capture. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This will enable operation of the velocity capture in the quadrature +//! encoder module. It must be configured before it is enabled. Velocity +//! capture will not occur if the quadrature encoder is not enabled. +//! +//! \sa QEIVelocityConfigure() and QEIEnable() +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_velocityenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +QEIVelocityEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Enable the velocity capture. + // + HWREG(ulBase + QEI_O_CTL) |= QEI_CTL_VELEN; +} +#endif + +//***************************************************************************** +// +//! Disables the velocity capture. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This will disable operation of the velocity capture in the quadrature +//! encoder module. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_velocitydisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +QEIVelocityDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Disable the velocity capture. + // + HWREG(ulBase + QEI_O_CTL) &= ~(QEI_CTL_VELEN); +} +#endif + +//***************************************************************************** +// +//! Configures the velocity capture. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! \param ulPreDiv specifies the predivider applied to the input quadrature +//! signal before it is counted; can be one of QEI_VELDIV_1, QEI_VELDIV_2, +//! QEI_VELDIV_4, QEI_VELDIV_8, QEI_VELDIV_16, QEI_VELDIV_32, QEI_VELDIV_64, or +//! QEI_VELDIV_128. +//! \param ulPeriod specifies the number of clock ticks over which to measure +//! the velocity; must be non-zero. +//! +//! This will configure the operation of the velocity capture portion of the +//! quadrature encoder. The position increment signal is predivided as +//! specified by \e ulPreDiv before being accumulated by the velocity capture. +//! The divided signal is accumulated over \e ulPeriod system clock before +//! being saved and resetting the accumulator. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_velocityconfigure) || defined(BUILD_ALL) || defined(DOXYGEN) +void +QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv, + unsigned long ulPeriod) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + ASSERT(!(ulPreDiv & ~(QEI_CTL_VELDIV_M))); + ASSERT(ulPeriod != 0); + + // + // Set the velocity predivider. + // + HWREG(ulBase + QEI_O_CTL) = ((HWREG(ulBase + QEI_O_CTL) & + ~(QEI_CTL_VELDIV_M)) | ulPreDiv); + + // + // Set the timer period. + // + HWREG(ulBase + QEI_O_LOAD) = ulPeriod - 1; +} +#endif + +//***************************************************************************** +// +//! Gets the current encoder speed. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This returns the current speed of the encoder. The value returned is the +//! number of pulses detected in the specified time period; this number can be +//! multiplied by the number of time periods per second and divided by the +//! number of pulses per revolution to obtain the number of revolutions per +//! second. +//! +//! \return The number of pulses captured in the given time period. +// +//***************************************************************************** +#if defined(GROUP_velocityget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +QEIVelocityGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Return the speed capture value. + // + return(HWREG(ulBase + QEI_O_SPEED)); +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for the quadrature encoder interrupt. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! \param pfnHandler is a pointer to the function to be called when the +//! quadrature encoder interrupt occurs. +//! +//! This sets the handler to be called when a quadrature encoder interrupt +//! occurs. This will enable the global interrupt in the interrupt controller; +//! specific quadrature encoder interrupts must be enabled via QEIIntEnable(). +//! It is the interrupt handler's responsibility to clear the interrupt source +//! via QEIIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(INT_QEI, pfnHandler); + + // + // Enable the quadrature encoder interrupt. + // + IntEnable(INT_QEI); +} +#endif + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the quadrature encoder interrupt. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! +//! This function will clear the handler to be called when a quadrature encoder +//! interrupt occurs. This will also mask off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +QEIIntUnregister(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Disable the interrupt. + // + IntDisable(INT_QEI); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_QEI); +} +#endif + +//***************************************************************************** +// +//! Enables individual quadrature encoder interrupt sources. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. +//! Can be any of the QEI_INTERROR, QEI_INTDIR, QEI_INTTIMER, or QEI_INTINDEX +//! values. +//! +//! Enables the indicated quadrature encoder interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Enable the specified interrupts. + // + HWREG(ulBase + QEI_O_INTEN) |= ulIntFlags; +} +#endif + +//***************************************************************************** +// +//! Disables individual quadrature encoder interrupt sources. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled. +//! Can be any of the QEI_INTERROR, QEI_INTDIR, QEI_INTTIMER, or QEI_INTINDEX +//! values. +//! +//! Disables the indicated quadrature encoder interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Disable the specified interrupts. + // + HWREG(ulBase + QEI_O_INTEN) &= ~(ulIntFlags); +} +#endif + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! \param bMasked is false if the raw interrupt status is required and true if +//! the masked interrupt status is required. +//! +//! This returns the interrupt status for the quadrature encoder module. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! QEI_INTERROR, QEI_INTDIR, QEI_INTTIMER, and QEI_INTINDEX. +// +//***************************************************************************** +#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +QEIIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ulBase + QEI_O_ISC)); + } + else + { + return(HWREG(ulBase + QEI_O_RIS)); + } +} +#endif + +//***************************************************************************** +// +//! Clears quadrature encoder interrupt sources. +//! +//! \param ulBase is the base address of the quadrature encoder module. +//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. +//! Can be any of the QEI_INTERROR, QEI_INTDIR, QEI_INTTIMER, or QEI_INTINDEX +//! values. +//! +//! The specified quadrature encoder interrupt sources are cleared, so that +//! they no longer assert. This must be done in the interrupt handler to keep +//! it from being called again immediately upon exit. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == QEI_BASE); + + // + // Clear the requested interrupt sources. + // + HWREG(ulBase + QEI_O_ISC) = ulIntFlags; +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/qei.h b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/qei.h new file mode 100644 index 000000000..3eaafaeef --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/qei.h @@ -0,0 +1,104 @@ +//***************************************************************************** +// +// qei.h - Prototypes for the Quadrature Encoder Driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __QEI_H__ +#define __QEI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to QEIConfigure as the ulConfig paramater. +// +//***************************************************************************** +#define QEI_CONFIG_CAPTURE_A 0x00000000 // Count on ChA edges only +#define QEI_CONFIG_CAPTURE_A_B 0x00000008 // Count on ChA and ChB edges +#define QEI_CONFIG_NO_RESET 0x00000000 // Do not reset on index pulse +#define QEI_CONFIG_RESET_IDX 0x00000010 // Reset position on index pulse +#define QEI_CONFIG_QUADRATURE 0x00000000 // ChA and ChB are quadrature +#define QEI_CONFIG_CLOCK_DIR 0x00000004 // ChA and ChB are clock and dir +#define QEI_CONFIG_NO_SWAP 0x00000000 // Do not swap ChA and ChB +#define QEI_CONFIG_SWAP 0x00000002 // Swap ChA and ChB + +//***************************************************************************** +// +// Values that can be passed to QEIVelocityConfigure as the ulPreDiv parameter. +// +//***************************************************************************** +#define QEI_VELDIV_1 0x00000000 // Predivide by 1 +#define QEI_VELDIV_2 0x00000040 // Predivide by 2 +#define QEI_VELDIV_4 0x00000080 // Predivide by 4 +#define QEI_VELDIV_8 0x000000C0 // Predivide by 8 +#define QEI_VELDIV_16 0x00000100 // Predivide by 16 +#define QEI_VELDIV_32 0x00000140 // Predivide by 32 +#define QEI_VELDIV_64 0x00000180 // Predivide by 64 +#define QEI_VELDIV_128 0x000001C0 // Predivide by 128 + +//***************************************************************************** +// +// Values that can be passed to QEIEnableInts, QEIDisableInts, and QEIClearInts +// as the ulIntFlags parameter, and returned by QEIGetIntStatus. +// +//***************************************************************************** +#define QEI_INTERROR 0x00000008 // Phase error detected +#define QEI_INTDIR 0x00000004 // Direction change +#define QEI_INTTIMER 0x00000002 // Velocity timer expired +#define QEI_INTINDEX 0x00000001 // Index pulse detected + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void QEIEnable(unsigned long ulBase); +extern void QEIDisable(unsigned long ulBase); +extern void QEIConfigure(unsigned long ulBase, unsigned long ulConfig, + unsigned long ulMaxPosition); +extern unsigned long QEIPositionGet(unsigned long ulBase); +extern void QEIPositionSet(unsigned long ulBase, unsigned long ulPosition); +extern long QEIDirectionGet(unsigned long ulBase); +extern tBoolean QEIErrorGet(unsigned long ulBase); +extern void QEIVelocityEnable(unsigned long ulBase); +extern void QEIVelocityDisable(unsigned long ulBase); +extern void QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv, + unsigned long ulPeriod); +extern unsigned long QEIVelocityGet(unsigned long ulBase); +extern void QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); +extern void QEIIntUnregister(unsigned long ulBase); +extern void QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long QEIIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags); + +#ifdef __cplusplus +} +#endif + +#endif // __QEI_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/ssi.c b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/ssi.c new file mode 100644 index 000000000..095aaab33 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/ssi.c @@ -0,0 +1,609 @@ +//***************************************************************************** +// +// ssi.c - Driver for Synchronous Serial Interface. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup ssi_api +//! @{ +// +//***************************************************************************** + +#include "../hw_ints.h" +#include "../hw_memmap.h" +#include "../hw_ssi.h" +#include "../hw_types.h" +#include "debug.h" +#include "interrupt.h" +#include "ssi.h" +#include "sysctl.h" + +//***************************************************************************** +// +//! Configures the synchronous serial interface. +//! +//! \param ulBase specifies the SSI module base address. +//! \param ulProtocol specifies the data transfer protocol. +//! \param ulMode specifies the mode of operation. +//! \param ulBitRate specifies the clock rate. +//! \param ulDataWidth specifies number of bits transfered per frame. +//! +//! This function configures the synchronous serial interface. It sets +//! the SSI protocol, mode of operation, bit rate, and data width. +//! +//! The parameter \e ulProtocol defines the data frame format. The parameter +//! \e ulProtocol can be one of the following values: SSI_FRF_MOTO_MODE_0, +//! SSI_FRF_MOTO_MODE_1, SSI_FRF_MOTO_MODE_2, SSI_FRF_MOTO_MODE_3, +//! SSI_FRF_TI, or SSI_FRF_NMW. The Motorola frame formats imply the +//! following polarity and phase configurations: +//! 

+//! Polarity Phase       Mode
+//!   0       0   SSI_FRF_MOTO_MODE_0
+//!   0       1   SSI_FRF_MOTO_MODE_1
+//!   1       0   SSI_FRF_MOTO_MODE_2
+//!   1       1   SSI_FRF_MOTO_MODE_3
+//!
+//! +//! The parameter \e ulMode defines the operating mode of the SSI module. The +//! SSI module can operate as a master or slave; if a slave, the SSI can be +//! configured to disable output on its serial output line. The parameter +//! \e ulMode can be one of the following values: SSI_MODE_MASTER, +//! SSI_MODE_SLAVE, or SSI_MODE_SLAVE_OD. +//! +//! The parameter \e ulBitRate defines the bit rate for the SSI. This bit rate +//! must satisfy the following clock ratio criteria: +//! - FSSI >= 2 * bit rate (master mode) +//! - FSSI >= 12 * bit rate (slave modes) +//! +//! where FSSI is the frequency of the clock supplied to the SSI module. +//! +//! The parameter \e ulDataWidth defines the width of the data transfers. +//! The parameter \e ulDataWidth can be a value between 4 and 16, inclusive. +//! +//! The SSI clocking is dependent upon the system clock rate returned by +//! SysCtlClockGet(); if it does not return the correct system clock rate then +//! the SSI clock rate will be incorrect. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_config) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SSIConfig(unsigned long ulBase, unsigned long ulProtocol, unsigned long ulMode, + unsigned long ulBitRate, unsigned long ulDataWidth) +{ + unsigned long ulMaxBitRate; + unsigned long ulRegVal; + unsigned long ulPreDiv; + unsigned long ulSCR; + unsigned long ulSPH_SPO; + unsigned long ulClock; + + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + ASSERT((ulProtocol == SSI_FRF_MOTO_MODE_0) || + (ulProtocol == SSI_FRF_MOTO_MODE_1) || + (ulProtocol == SSI_FRF_MOTO_MODE_2) || + (ulProtocol == SSI_FRF_MOTO_MODE_3) || + (ulProtocol == SSI_FRF_TI) || + (ulProtocol == SSI_FRF_NMW)); + ASSERT((ulMode == SSI_MODE_MASTER) || + (ulMode == SSI_MODE_SLAVE) || + (ulMode == SSI_MODE_SLAVE_OD)); + ASSERT((ulDataWidth >= 4) && (ulDataWidth <= 16)); + + // + // Get the processor clock rate. + // + ulClock = SysCtlClockGet(); + + // + // Validate the clock speed. + // + ASSERT(((ulMode == SSI_MODE_MASTER) && (ulBitRate <= (ulClock / 2))) || + ((ulMode != SSI_MODE_MASTER) && (ulBitRate <= (ulClock / 12)))); + ASSERT((ulClock / ulBitRate) <= (254 * 256)); + + // + // Set the mode. + // + ulRegVal = (ulMode == SSI_MODE_SLAVE_OD) ? SSI_CR1_SOD : 0; + ulRegVal |= (ulMode == SSI_MODE_MASTER) ? 0 : SSI_CR1_MS; + HWREG(ulBase + SSI_O_CR1) = ulRegVal; + + // + // Set the clock predivider. + // + ulMaxBitRate = ulClock / ulBitRate; + ulPreDiv = 0; + do + { + ulPreDiv += 2; + ulSCR = (ulMaxBitRate / ulPreDiv) - 1; + } + while(ulSCR > 255); + HWREG(ulBase + SSI_O_CPSR) = ulPreDiv; + + // + // Set protocol and clock rate. + // + ulSPH_SPO = ulProtocol << 6; + ulProtocol &= SSI_CR0_FRF_MASK; + ulRegVal = (ulSCR << 8) | ulSPH_SPO | ulProtocol | (ulDataWidth - 1); + HWREG(ulBase + SSI_O_CR0) = ulRegVal; +} +#endif + +//***************************************************************************** +// +//! Enables the synchronous serial interface. +//! +//! \param ulBase specifies the SSI module base address. +//! +//! This will enable operation of the synchronous serial interface. It must be +//! configured before it is enabled. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SSIEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + + // + // Read-modify-write the enable bit. + // + HWREG(ulBase + SSI_O_CR1) |= SSI_CR1_SSE; +} +#endif + +//***************************************************************************** +// +//! Disables the synchronous serial interface. +//! +//! \param ulBase specifies the SSI module base address. +//! +//! This will disable operation of the synchronous serial interface. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SSIDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + + // + // Read-modify-write the enable bit. + // + HWREG(ulBase + SSI_O_CR1) &= ~(SSI_CR1_SSE); +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for the synchronous serial interface. +//! +//! \param ulBase specifies the SSI module base address. +//! \param pfnHandler is a pointer to the function to be called when the +//! synchronous serial interface interrupt occurs. +//! +//! This sets the handler to be called when an SSI interrupt +//! occurs. This will enable the global interrupt in the interrupt controller; +//! specific SSI interrupts must be enabled via SSIIntEnable(). If necessary, +//! it is the interrupt handler's responsibility to clear the interrupt source +//! via SSIIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SSIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(INT_SSI, pfnHandler); + + // + // Enable the synchronous serial interface interrupt. + // + IntEnable(INT_SSI); +} +#endif + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the synchronous serial interface. +//! +//! \param ulBase specifies the SSI module base address. +//! +//! This function will clear the handler to be called when a SSI +//! interrupt occurs. This will also mask off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SSIIntUnregister(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + + // + // Disable the interrupt. + // + IntDisable(INT_SSI); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_SSI); +} +#endif + +//***************************************************************************** +// +//! Enables individual SSI interrupt sources. +//! +//! \param ulBase specifies the SSI module base address. +//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. +//! +//! Enables the indicated SSI interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources +//! have no effect on the processor. The parameter \e ulIntFlags Can be +//! any of the SSI_TXFF, SSI_RXFF, SSI_RXTO, or SSI_RXOR values. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + + // + // Enable the specified interrupts. + // + HWREG(ulBase + SSI_O_IM) |= ulIntFlags; +} +#endif + +//***************************************************************************** +// +//! Disables individual SSI interrupt sources. +//! +//! \param ulBase specifies the SSI module base address. +//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled. +//! +//! Disables the indicated SSI interrupt sources. The parameter +//! \e ulIntFlags Can be any of the SSI_TXFF, SSI_RXFF, SSI_RXTO, +//! or SSI_RXOR values. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + + // + // Disable the specified interrupts. + // + HWREG(ulBase + SSI_O_IM) &= ~(ulIntFlags); +} +#endif + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ulBase specifies the SSI module base address. +//! \param bMasked is false if the raw interrupt status is required and +//! true if the masked interrupt status is required. +//! +//! This returns the interrupt status for the SSI module. +//! Either the raw interrupt status or the status of interrupts that are +//! allowed to reflect to the processor can be returned. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! SSI_TXFF, SSI_RXFF, SSI_RXTO, and SSI_RXOR. +// +//***************************************************************************** +#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +SSIIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ulBase + SSI_O_MIS)); + } + else + { + return(HWREG(ulBase + SSI_O_RIS)); + } +} +#endif + +//***************************************************************************** +// +//! Clears SSI interrupt sources. +//! +//! \param ulBase specifies the SSI module base address. +//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! The specified SSI interrupt sources are cleared, so that +//! they no longer assert. This must be done in the interrupt handler to +//! keep it from being called again immediately upon exit. +//! The parameter \e ulIntFlags can consist of either or both the SSI_RXTO +//! and SSI_RXOR values. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + + // + // Clear the requested interrupt sources. + // + HWREG(ulBase + SSI_O_ICR) = ulIntFlags; +} +#endif + +//***************************************************************************** +// +//! Puts a data element into the SSI transmit FIFO. +//! +//! \param ulBase specifies the SSI module base address. +//! \param ulData data to be transmitted over the SSI interface. +//! +//! This function will place the supplied data into the transmit FIFO of +//! the specified SSI module. +//! +//! \note The upper 32 - N bits of the \e ulData will be discarded by the +//! hardware, where N is the data width as configured by SSIConfig(). For +//! example, if the interface is configured for 8 bit data width, the upper 24 +//! bits of \e ulData will be discarded. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_dataput) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SSIDataPut(unsigned long ulBase, unsigned long ulData) +{ + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + ASSERT((ulData & (0xfffffffe << (HWREG(ulBase + SSI_O_CR0) & + SSI_CR0_DSS))) == 0); + + // + // Wait until there is space. + // + while(!(HWREG(ulBase + SSI_O_SR) & SSI_SR_TNF)) + { + } + + // + // Write the data to the SSI. + // + HWREG(ulBase + SSI_O_DR) = ulData; +} +#endif + +//***************************************************************************** +// +//! Puts a data element into the SSI transmit FIFO. +//! +//! \param ulBase specifies the SSI module base address. +//! \param ulData data to be transmitted over the SSI interface. +//! +//! This function will place the supplied data into the transmit FIFO of +//! the specified SSI module. If there is no space in the FIFO, then this +//! function will return a zero. +//! +//! \note The upper 32 - N bits of the \e ulData will be discarded by the +//! hardware, where N is the data width as configured by SSIConfig(). For +//! example, if the interface is configured for 8 bit data width, the upper 24 +//! bits of \e ulData will be discarded. +//! +//! \return Returns the number of elements written to the SSI transmit FIFO. +// +//***************************************************************************** +#if defined(GROUP_datanonblockingput) || defined(BUILD_ALL) || defined(DOXYGEN) +long +SSIDataNonBlockingPut(unsigned long ulBase, unsigned long ulData) +{ + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + ASSERT((ulData & (0xfffffffe << (HWREG(ulBase + SSI_O_CR0) & + SSI_CR0_DSS))) == 0); + + // + // Check for space to write. + // + if(HWREG(ulBase + SSI_O_SR) & SSI_SR_TNF) + { + HWREG(ulBase + SSI_O_DR) = ulData; + return(1); + } + else + { + return(0); + } +} +#endif + +//***************************************************************************** +// +//! Gets a data element from the SSI receive FIFO. +//! +//! \param ulBase specifies the SSI module base address. +//! \param pulData pointer to a storage location for data that was received +//! over the SSI interface. +//! +//! This function will get received data from the receive FIFO of the specified +//! SSI module, and place that data into the location specified by the +//! \e pulData parameter. +//! +//! \note Only the lower N bits of the value written to \e pulData will contain +//! valid data, where N is the data width as configured by SSIConfig(). For +//! example, if the interface is configured for 8 bit data width, only the +//! lower 8 bits of the value written to \e pulData will contain valid data. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_dataget) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SSIDataGet(unsigned long ulBase, unsigned long *pulData) +{ + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + + // + // Wait until there is data to be read. + // + while(!(HWREG(ulBase + SSI_O_SR) & SSI_SR_RNE)) + { + } + + // + // Read data from SSI. + // + *pulData = HWREG(ulBase + SSI_O_DR); +} +#endif + +//***************************************************************************** +// +//! Gets a data element from the SSI receive FIFO. +//! +//! \param ulBase specifies the SSI module base address. +//! \param pulData pointer to a storage location for data that was received +//! over the SSI interface. +//! +//! This function will get received data from the receive FIFO of +//! the specified SSI module, and place that data into the location specified +//! by the \e ulData parameter. If there is no data in the FIFO, then this +//! function will return a zero. +//! +//! \note Only the lower N bits of the value written to \e pulData will contain +//! valid data, where N is the data width as configured by SSIConfig(). For +//! example, if the interface is configured for 8 bit data width, only the +//! lower 8 bits of the value written to \e pulData will contain valid data. +//! +//! \return Returns the number of elements read from the SSI receive FIFO. +// +//***************************************************************************** +#if defined(GROUP_datanonblockingget) || defined(BUILD_ALL) || defined(DOXYGEN) +long +SSIDataNonBlockingGet(unsigned long ulBase, unsigned long *pulData) +{ + // + // Check the arguments. + // + ASSERT(ulBase == SSI_BASE); + + // + // Check for data to read. + // + if(HWREG(ulBase + SSI_O_SR) & SSI_SR_RNE) + { + *pulData = HWREG(ulBase + SSI_O_DR); + return(1); + } + else + { + return(0); + } +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/ssi.h b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/ssi.h new file mode 100644 index 000000000..045d8cb02 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/ssi.h @@ -0,0 +1,89 @@ +//***************************************************************************** +// +// ssi.h - Prototypes for the Synchronous Serial Interface Driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __SSI_H__ +#define __SSI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear +// as the ulIntFlags parameter, and returned by SSIIntStatus. +// +//***************************************************************************** +#define SSI_TXFF 0x00000008 // TX FIFO half empty or less +#define SSI_RXFF 0x00000004 // RX FIFO half full or less +#define SSI_RXTO 0x00000002 // RX timeout +#define SSI_RXOR 0x00000001 // RX overrun + +//***************************************************************************** +// +// Values that can be passed to SSIConfig. +// +//***************************************************************************** +#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0 +#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1 +#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0 +#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1 +#define SSI_FRF_TI 0x00000010 // TI frame format +#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format + +#define SSI_MODE_MASTER 0x00000000 // SSI master +#define SSI_MODE_SLAVE 0x00000001 // SSI slave +#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void SSIConfig(unsigned long ulBase, unsigned long ulProtocol, + unsigned long ulMode, unsigned long ulBitRate, + unsigned long ulDataWidth); +extern void SSIDataGet(unsigned long ulBase, unsigned long *pulData); +extern long SSIDataNonBlockingGet(unsigned long ulBase, + unsigned long *pulData); +extern void SSIDataPut(unsigned long ulBase, unsigned long ulData); +extern long SSIDataNonBlockingPut(unsigned long ulBase, unsigned long ulData); +extern void SSIDisable(unsigned long ulBase); +extern void SSIEnable(unsigned long ulBase); +extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void SSIIntUnregister(unsigned long ulBase); + +#ifdef __cplusplus +} +#endif + +#endif // __SSI_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/sysctl.c b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/sysctl.c new file mode 100644 index 000000000..539d0f76d --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/sysctl.c @@ -0,0 +1,1889 @@ +//***************************************************************************** +// +// sysctl.c - Driver for the system controller. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. ALl rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup sysctl_api +//! @{ +// +//***************************************************************************** + +#include "../hw_ints.h" +#include "../hw_memmap.h" +#include "../hw_nvic.h" +#include "../hw_sysctl.h" +#include "../hw_types.h" +#include "cpu.h" +#include "debug.h" +#include "interrupt.h" +#include "sysctl.h" + +//***************************************************************************** +// +// An array that maps the "peripheral set" number (which is stored in the upper +// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL DC? register that +// contains the peripheral present bit for that peripheral. +// +//***************************************************************************** +#if defined(GROUP_puldcregs) || defined(BUILD_ALL) +const unsigned long g_pulDCRegs[] = +{ + SYSCTL_DC1, + SYSCTL_DC2, + SYSCTL_DC4, + SYSCTL_DC1 +}; +#else +extern const unsigned long g_pulDCRegs[]; +#endif + +//***************************************************************************** +// +// An array that maps the "peripheral set" number (which is stored in the upper +// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_SRCR? register that +// controls the software reset for that peripheral. +// +//***************************************************************************** +#if defined(GROUP_pulsrcrregs) || defined(BUILD_ALL) +const unsigned long g_pulSRCRRegs[] = +{ + SYSCTL_SRCR0, + SYSCTL_SRCR1, + SYSCTL_SRCR2 +}; +#else +extern const unsigned long g_pulSRCRRegs[]; +#endif + +//***************************************************************************** +// +// An array that maps the "peripheral set" number (which is stored in the upper +// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_RCGC? register that +// controls the run-mode enable for that peripheral. +// +//***************************************************************************** +#if defined(GROUP_pulrcgcregs) || defined(BUILD_ALL) +const unsigned long g_pulRCGCRegs[] = +{ + SYSCTL_RCGC0, + SYSCTL_RCGC1, + SYSCTL_RCGC2 +}; +#else +extern const unsigned long g_pulRCGCRegs[]; +#endif + +//***************************************************************************** +// +// An array that maps the "peripheral set" number (which is stored in the upper +// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_SCGC? register that +// controls the sleep-mode enable for that peripheral. +// +//***************************************************************************** +#if defined(GROUP_pulscgcregs) || defined(BUILD_ALL) +const unsigned long g_pulSCGCRegs[] = +{ + SYSCTL_SCGC0, + SYSCTL_SCGC1, + SYSCTL_SCGC2 +}; +#else +extern const unsigned long g_pulSCGCRegs[]; +#endif + +//***************************************************************************** +// +// An array that maps the "peripheral set" number (which is stored in the upper +// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_DCGC? register that +// controls the deep-sleep-mode enable for that peripheral. +// +//***************************************************************************** +#if defined(GROUP_pulDCGCregs) || defined(BUILD_ALL) +const unsigned long g_pulDCGCRegs[] = +{ + SYSCTL_DCGC0, + SYSCTL_DCGC1, + SYSCTL_DCGC2 +}; +#else +extern const unsigned long g_pulDCGCRegs[]; +#endif + +//***************************************************************************** +// +// An array that maps the crystal number in RCC to a frequency. +// +//***************************************************************************** +#if defined(GROUP_pulxtals) || defined(BUILD_ALL) +const unsigned long g_pulXtals[] = +{ + 3579545, + 3686400, + 4000000, + 4096000, + 4915200, + 5000000, + 5120000, + 6000000, + 6144000, + 7372800, + 8000000, + 8192000 +}; +#else +extern const unsigned long g_pulXtals[]; +#endif + +//***************************************************************************** +// +//! Gets the size of the SRAM. +//! +//! This function determines the size of the SRAM on the Stellaris device. +//! +//! \return The total number of bytes of SRAM. +// +//***************************************************************************** +#if defined(GROUP_sramsizeget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +SysCtlSRAMSizeGet(void) +{ + // + // Compute the size of the SRAM. + // + return(((HWREG(SYSCTL_DC0) & SYSCTL_DC0_SRAMSZ_MASK) >> 8) + 0x100); +} +#endif + +//***************************************************************************** +// +//! Gets the size of the flash. +//! +//! This function determines the size of the flash on the Stellaris device. +//! +//! \return The total number of bytes of flash. +// +//***************************************************************************** +#if defined(GROUP_flashsizeget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +SysCtlFlashSizeGet(void) +{ + // + // Compute the size of the flash. + // + return(((HWREG(SYSCTL_DC0) & SYSCTL_DC0_FLASHSZ_MASK) << 11) + 0x800); +} +#endif + +//***************************************************************************** +// +//! Determines if a pin is present. +//! +//! \param ulPin is the pin in question. +//! +//! Determines if a particular pin is present in the device. The PWM, analog +//! comparators, ADC, and timers have a varying number of pins across members +//! of the Stellaris family; this will determine which are present on this +//! device. +//! +//! The \b ulPin argument must be only one of the following values: +//! \b SYSCTL_PIN_PWM0, \b SYSCTL_PIN_PWM1, \b SYSCTL_PIN_PWM2, +//! \b SYSCTL_PIN_PWM3, \b SYSCTL_PIN_PWM4, \b SYSCTL_PIN_PWM5, +//! \b SYSCTL_PIN_C0MINUS, \b SYSCTL_PIN_C0PLUS, \b SYSCTL_PIN_C0O, +//! \b SYSCTL_PIN_C1MINUS, \b SYSCTL_PIN_C1PLUS, \b SYSCTL_PIN_C1O, +//! \b SYSCTL_PIN_C2MINUS, \b SYSCTL_PIN_C2PLUS, \b SYSCTL_PIN_C2O, +//! \b SYSCTL_PIN_ADC0, \b SYSCTL_PIN_ADC1, \b SYSCTL_PIN_ADC2, +//! \b SYSCTL_PIN_ADC3, \b SYSCTL_PIN_ADC4, \b SYSCTL_PIN_ADC5, +//! \b SYSCTL_PIN_ADC6, \b SYSCTL_PIN_ADC7, \b SYSCTL_PIN_CCP0, +//! \b SYSCTL_PIN_CCP1, \b SYSCTL_PIN_CCP2, \b SYSCTL_PIN_CCP3, +//! \b SYSCTL_PIN_CCP4, \b SYSCTL_PIN_CCP5, or \b SYSCTL_PIN_32KHZ. +//! +//! \return Returns \b true if the specified pin is present and \b false if it +//! is not. +// +//***************************************************************************** +#if defined(GROUP_pinpresent) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +SysCtlPinPresent(unsigned long ulPin) +{ + // + // Check the arguments. + // + ASSERT((ulPin == SYSCTL_PIN_PWM0) || + (ulPin == SYSCTL_PIN_PWM1) || + (ulPin == SYSCTL_PIN_PWM2) || + (ulPin == SYSCTL_PIN_PWM3) || + (ulPin == SYSCTL_PIN_PWM4) || + (ulPin == SYSCTL_PIN_PWM5) || + (ulPin == SYSCTL_PIN_C0MINUS) || + (ulPin == SYSCTL_PIN_C0PLUS) || + (ulPin == SYSCTL_PIN_C0O) || + (ulPin == SYSCTL_PIN_C1MINUS) || + (ulPin == SYSCTL_PIN_C1PLUS) || + (ulPin == SYSCTL_PIN_C1O) || + (ulPin == SYSCTL_PIN_C2MINUS) || + (ulPin == SYSCTL_PIN_C2PLUS) || + (ulPin == SYSCTL_PIN_C2O) || + (ulPin == SYSCTL_PIN_ADC0) || + (ulPin == SYSCTL_PIN_ADC1) || + (ulPin == SYSCTL_PIN_ADC2) || + (ulPin == SYSCTL_PIN_ADC3) || + (ulPin == SYSCTL_PIN_ADC4) || + (ulPin == SYSCTL_PIN_ADC5) || + (ulPin == SYSCTL_PIN_ADC6) || + (ulPin == SYSCTL_PIN_ADC7) || + (ulPin == SYSCTL_PIN_CCP0) || + (ulPin == SYSCTL_PIN_CCP1) || + (ulPin == SYSCTL_PIN_CCP2) || + (ulPin == SYSCTL_PIN_CCP3) || + (ulPin == SYSCTL_PIN_CCP4) || + (ulPin == SYSCTL_PIN_CCP5) || + (ulPin == SYSCTL_PIN_32KHZ)) + + // + // Determine if this pin is present. + // + if(HWREG(SYSCTL_DC3) & ulPin) + { + return(true); + } + else + { + return(false); + } +} +#endif + +//***************************************************************************** +// +//! Determines if a peripheral is present. +//! +//! \param ulPeripheral is the peripheral in question. +//! +//! Determines if a particular peripheral is present in the device. Each +//! member of the Stellaris family has a different peripheral set; this will +//! determine which are present on this device. +//! +//! The \b ulPeripheral argument must be only one of the following values: +//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG, +//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI, +//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0, +//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA, +//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, +//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_MPU, \b SYSCTL_PERIPH_TEMP, or +//! \b SYSCTL_PERIPH_PLL. +//! +//! \return Returns \b true if the specified peripheral is present and \b false +//! if it is not. +// +//***************************************************************************** +#if defined(GROUP_peripheralpresent) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +SysCtlPeripheralPresent(unsigned long ulPeripheral) +{ + // + // Check the arguments. + // + ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) || + (ulPeripheral == SYSCTL_PERIPH_ADC) || + (ulPeripheral == SYSCTL_PERIPH_WDOG) || + (ulPeripheral == SYSCTL_PERIPH_UART0) || + (ulPeripheral == SYSCTL_PERIPH_UART1) || + (ulPeripheral == SYSCTL_PERIPH_SSI) || + (ulPeripheral == SYSCTL_PERIPH_QEI) || + (ulPeripheral == SYSCTL_PERIPH_I2C) || + (ulPeripheral == SYSCTL_PERIPH_TIMER0) || + (ulPeripheral == SYSCTL_PERIPH_TIMER1) || + (ulPeripheral == SYSCTL_PERIPH_TIMER2) || + (ulPeripheral == SYSCTL_PERIPH_COMP0) || + (ulPeripheral == SYSCTL_PERIPH_COMP1) || + (ulPeripheral == SYSCTL_PERIPH_COMP2) || + (ulPeripheral == SYSCTL_PERIPH_GPIOA) || + (ulPeripheral == SYSCTL_PERIPH_GPIOB) || + (ulPeripheral == SYSCTL_PERIPH_GPIOC) || + (ulPeripheral == SYSCTL_PERIPH_GPIOD) || + (ulPeripheral == SYSCTL_PERIPH_GPIOE) || + (ulPeripheral == SYSCTL_PERIPH_MPU) || + (ulPeripheral == SYSCTL_PERIPH_TEMP) || + (ulPeripheral == SYSCTL_PERIPH_PLL)); + + // + // Read the correct DC register and determine if this peripheral exists. + // + if(HWREG(g_pulDCRegs[ulPeripheral >> 28]) & ulPeripheral & 0x0fffffff) + { + return(true); + } + else + { + return(false); + } +} +#endif + +//***************************************************************************** +// +//! Performs a software reset of a peripheral. +//! +//! \param ulPeripheral is the peripheral to reset. +//! +//! This function performs a software reset of the specified peripheral. An +//! individual peripheral reset signal is asserted for a brief period and then +//! deasserted, leaving the peripheral in a operating state but in its reset +//! condition. +//! +//! The \b ulPeripheral argument must be only one of the following values: +//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG, +//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI, +//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0, +//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA, +//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or +//! \b SYSCTL_PERIPH_GPIOE. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_peripheralreset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlPeripheralReset(unsigned long ulPeripheral) +{ + volatile unsigned long ulDelay; + + // + // Check the arguments. + // + ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) || + (ulPeripheral == SYSCTL_PERIPH_ADC) || + (ulPeripheral == SYSCTL_PERIPH_WDOG) || + (ulPeripheral == SYSCTL_PERIPH_UART0) || + (ulPeripheral == SYSCTL_PERIPH_UART1) || + (ulPeripheral == SYSCTL_PERIPH_SSI) || + (ulPeripheral == SYSCTL_PERIPH_QEI) || + (ulPeripheral == SYSCTL_PERIPH_I2C) || + (ulPeripheral == SYSCTL_PERIPH_TIMER0) || + (ulPeripheral == SYSCTL_PERIPH_TIMER1) || + (ulPeripheral == SYSCTL_PERIPH_TIMER2) || + (ulPeripheral == SYSCTL_PERIPH_COMP0) || + (ulPeripheral == SYSCTL_PERIPH_COMP1) || + (ulPeripheral == SYSCTL_PERIPH_COMP2) || + (ulPeripheral == SYSCTL_PERIPH_GPIOA) || + (ulPeripheral == SYSCTL_PERIPH_GPIOB) || + (ulPeripheral == SYSCTL_PERIPH_GPIOC) || + (ulPeripheral == SYSCTL_PERIPH_GPIOD) || + (ulPeripheral == SYSCTL_PERIPH_GPIOE)); + + // + // Put the peripheral into the reset state. + // + HWREG(g_pulSRCRRegs[ulPeripheral >> 28]) |= ulPeripheral & 0x0fffffff; + + // + // Delay for a little bit. + // + for(ulDelay = 0; ulDelay < 16; ulDelay++) + { + } + + // + // Take the peripheral out of the reset state. + // + HWREG(g_pulSRCRRegs[ulPeripheral >> 28]) &= ~(ulPeripheral); +} +#endif + +//***************************************************************************** +// +//! Enables a peripheral. +//! +//! \param ulPeripheral is the peripheral to enable. +//! +//! Peripherals are enabled with this function. At power-up, all peripherals +//! are disabled; they must be enabled in order to operate or respond to +//! register reads/writes. +//! +//! The \b ulPeripheral argument must be only one of the following values: +//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG, +//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI, +//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0, +//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA, +//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or +//! \b SYSCTL_PERIPH_GPIOE. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_peripheralenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlPeripheralEnable(unsigned long ulPeripheral) +{ + // + // Check the arguments. + // + ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) || + (ulPeripheral == SYSCTL_PERIPH_ADC) || + (ulPeripheral == SYSCTL_PERIPH_WDOG) || + (ulPeripheral == SYSCTL_PERIPH_UART0) || + (ulPeripheral == SYSCTL_PERIPH_UART1) || + (ulPeripheral == SYSCTL_PERIPH_SSI) || + (ulPeripheral == SYSCTL_PERIPH_QEI) || + (ulPeripheral == SYSCTL_PERIPH_I2C) || + (ulPeripheral == SYSCTL_PERIPH_TIMER0) || + (ulPeripheral == SYSCTL_PERIPH_TIMER1) || + (ulPeripheral == SYSCTL_PERIPH_TIMER2) || + (ulPeripheral == SYSCTL_PERIPH_COMP0) || + (ulPeripheral == SYSCTL_PERIPH_COMP1) || + (ulPeripheral == SYSCTL_PERIPH_COMP2) || + (ulPeripheral == SYSCTL_PERIPH_GPIOA) || + (ulPeripheral == SYSCTL_PERIPH_GPIOB) || + (ulPeripheral == SYSCTL_PERIPH_GPIOC) || + (ulPeripheral == SYSCTL_PERIPH_GPIOD) || + (ulPeripheral == SYSCTL_PERIPH_GPIOE)); + + // + // Enable this peripheral. + // + HWREG(g_pulRCGCRegs[ulPeripheral >> 28]) |= ulPeripheral & 0x0fffffff; +} +#endif + +//***************************************************************************** +// +//! Disables a peripheral. +//! +//! \param ulPeripheral is the peripheral to disable. +//! +//! Peripherals are disabled with this function. Once disabled, they will not +//! operate or respond to register reads/writes. +//! +//! The \b ulPeripheral argument must be only one of the following values: +//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG, +//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI, +//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0, +//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA, +//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or +//! \b SYSCTL_PERIPH_GPIOE. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_peripheraldisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlPeripheralDisable(unsigned long ulPeripheral) +{ + // + // Check the arguments. + // + ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) || + (ulPeripheral == SYSCTL_PERIPH_ADC) || + (ulPeripheral == SYSCTL_PERIPH_WDOG) || + (ulPeripheral == SYSCTL_PERIPH_UART0) || + (ulPeripheral == SYSCTL_PERIPH_UART1) || + (ulPeripheral == SYSCTL_PERIPH_SSI) || + (ulPeripheral == SYSCTL_PERIPH_QEI) || + (ulPeripheral == SYSCTL_PERIPH_I2C) || + (ulPeripheral == SYSCTL_PERIPH_TIMER0) || + (ulPeripheral == SYSCTL_PERIPH_TIMER1) || + (ulPeripheral == SYSCTL_PERIPH_TIMER2) || + (ulPeripheral == SYSCTL_PERIPH_COMP0) || + (ulPeripheral == SYSCTL_PERIPH_COMP1) || + (ulPeripheral == SYSCTL_PERIPH_COMP2) || + (ulPeripheral == SYSCTL_PERIPH_GPIOA) || + (ulPeripheral == SYSCTL_PERIPH_GPIOB) || + (ulPeripheral == SYSCTL_PERIPH_GPIOC) || + (ulPeripheral == SYSCTL_PERIPH_GPIOD) || + (ulPeripheral == SYSCTL_PERIPH_GPIOE)); + + // + // Disable this peripheral. + // + HWREG(g_pulRCGCRegs[ulPeripheral >> 28]) &= ~(ulPeripheral & 0x0fffffff); +} +#endif + +//***************************************************************************** +// +//! Enables a peripheral in sleep mode. +//! +//! \param ulPeripheral is the peripheral to enable in sleep mode. +//! +//! This function allows a peripheral to continue operating when the processor +//! goes into sleep mode. Since the clocking configuration of the device does +//! not change, any peripheral can safely continue operating while the +//! processor is in sleep mode, and can therefore wake the processor from sleep +//! mode. +//! +//! Sleep mode clocking of peripherals must be enabled via +//! SysCtlPeripheralClockGating(); if disabled, the peripheral sleep mode +//! configuration is maintained but has no effect when sleep mode is entered. +//! +//! The \b ulPeripheral argument must be only one of the following values: +//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG, +//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI, +//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0, +//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA, +//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or +//! \b SYSCTL_PERIPH_GPIOE. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_peripheralsleepenable) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +SysCtlPeripheralSleepEnable(unsigned long ulPeripheral) +{ + // + // Check the arguments. + // + ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) || + (ulPeripheral == SYSCTL_PERIPH_ADC) || + (ulPeripheral == SYSCTL_PERIPH_WDOG) || + (ulPeripheral == SYSCTL_PERIPH_UART0) || + (ulPeripheral == SYSCTL_PERIPH_UART1) || + (ulPeripheral == SYSCTL_PERIPH_SSI) || + (ulPeripheral == SYSCTL_PERIPH_QEI) || + (ulPeripheral == SYSCTL_PERIPH_I2C) || + (ulPeripheral == SYSCTL_PERIPH_TIMER0) || + (ulPeripheral == SYSCTL_PERIPH_TIMER1) || + (ulPeripheral == SYSCTL_PERIPH_TIMER2) || + (ulPeripheral == SYSCTL_PERIPH_COMP0) || + (ulPeripheral == SYSCTL_PERIPH_COMP1) || + (ulPeripheral == SYSCTL_PERIPH_COMP2) || + (ulPeripheral == SYSCTL_PERIPH_GPIOA) || + (ulPeripheral == SYSCTL_PERIPH_GPIOB) || + (ulPeripheral == SYSCTL_PERIPH_GPIOC) || + (ulPeripheral == SYSCTL_PERIPH_GPIOD) || + (ulPeripheral == SYSCTL_PERIPH_GPIOE)); + + // + // Enable this peripheral in sleep mode. + // + HWREG(g_pulSCGCRegs[ulPeripheral >> 28]) |= ulPeripheral & 0x0fffffff; +} +#endif + +//***************************************************************************** +// +//! Disables a peripheral in sleep mode. +//! +//! \param ulPeripheral is the peripheral to disable in sleep mode. +//! +//! This function causes a peripheral to stop operating when the processor goes +//! into sleep mode. Disabling peripherals while in sleep mode helps to lower +//! the current draw of the device. If enabled (via SysCtlPeripheralEnable()), +//! the peripheral will automatically resume operation when the processor +//! leaves sleep mode, maintaining its entire state from before sleep mode was +//! entered. +//! +//! Sleep mode clocking of peripherals must be enabled via +//! SysCtlPeripheralClockGating(); if disabled, the peripheral sleep mode +//! configuration is maintained but has no effect when sleep mode is entered. +//! +//! The \b ulPeripheral argument must be only one of the following values: +//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG, +//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI, +//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0, +//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA, +//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or +//! \b SYSCTL_PERIPH_GPIOE. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_peripheralsleepdisable) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +SysCtlPeripheralSleepDisable(unsigned long ulPeripheral) +{ + // + // Check the arguments. + // + ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) || + (ulPeripheral == SYSCTL_PERIPH_ADC) || + (ulPeripheral == SYSCTL_PERIPH_WDOG) || + (ulPeripheral == SYSCTL_PERIPH_UART0) || + (ulPeripheral == SYSCTL_PERIPH_UART1) || + (ulPeripheral == SYSCTL_PERIPH_SSI) || + (ulPeripheral == SYSCTL_PERIPH_QEI) || + (ulPeripheral == SYSCTL_PERIPH_I2C) || + (ulPeripheral == SYSCTL_PERIPH_TIMER0) || + (ulPeripheral == SYSCTL_PERIPH_TIMER1) || + (ulPeripheral == SYSCTL_PERIPH_TIMER2) || + (ulPeripheral == SYSCTL_PERIPH_COMP0) || + (ulPeripheral == SYSCTL_PERIPH_COMP1) || + (ulPeripheral == SYSCTL_PERIPH_COMP2) || + (ulPeripheral == SYSCTL_PERIPH_GPIOA) || + (ulPeripheral == SYSCTL_PERIPH_GPIOB) || + (ulPeripheral == SYSCTL_PERIPH_GPIOC) || + (ulPeripheral == SYSCTL_PERIPH_GPIOD) || + (ulPeripheral == SYSCTL_PERIPH_GPIOE)); + + // + // Disable this peripheral in sleep mode. + // + HWREG(g_pulSCGCRegs[ulPeripheral >> 28]) &= ~(ulPeripheral & 0x0fffffff); +} +#endif + +//***************************************************************************** +// +//! Enables a peripheral in deep-sleep mode. +//! +//! \param ulPeripheral is the peripheral to enable in deep-sleep mode. +//! +//! This function allows a peripheral to continue operating when the processor +//! goes into deep-sleep mode. Since the clocking configuration of the device +//! may change, not all peripherals can safely continue operating while the +//! processor is in sleep mode. Those that must run at a particular frequency +//! (such as a UART) will not work as expected if the clock changes. It is the +//! responsibility of the caller to make sensible choices. +//! +//! Deep-sleep mode clocking of peripherals must be enabled via +//! SysCtlPeripheralClockGating(); if disabled, the peripheral deep-sleep mode +//! configuration is maintained but has no effect when deep-sleep mode is +//! entered. +//! +//! The \b ulPeripheral argument must be one of the following values: +//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG, +//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI, +//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0, +//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA, +//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or +//! \b SYSCTL_PERIPH_GPIOE. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_peripheraldeepsleepenable) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral) +{ + // + // Check the arguments. + // + ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) || + (ulPeripheral == SYSCTL_PERIPH_ADC) || + (ulPeripheral == SYSCTL_PERIPH_WDOG) || + (ulPeripheral == SYSCTL_PERIPH_UART0) || + (ulPeripheral == SYSCTL_PERIPH_UART1) || + (ulPeripheral == SYSCTL_PERIPH_SSI) || + (ulPeripheral == SYSCTL_PERIPH_QEI) || + (ulPeripheral == SYSCTL_PERIPH_I2C) || + (ulPeripheral == SYSCTL_PERIPH_TIMER0) || + (ulPeripheral == SYSCTL_PERIPH_TIMER1) || + (ulPeripheral == SYSCTL_PERIPH_TIMER2) || + (ulPeripheral == SYSCTL_PERIPH_COMP0) || + (ulPeripheral == SYSCTL_PERIPH_COMP1) || + (ulPeripheral == SYSCTL_PERIPH_COMP2) || + (ulPeripheral == SYSCTL_PERIPH_GPIOA) || + (ulPeripheral == SYSCTL_PERIPH_GPIOB) || + (ulPeripheral == SYSCTL_PERIPH_GPIOC) || + (ulPeripheral == SYSCTL_PERIPH_GPIOD) || + (ulPeripheral == SYSCTL_PERIPH_GPIOE)); + + // + // Enable this peripheral in deep-sleep mode. + // + HWREG(g_pulDCGCRegs[ulPeripheral >> 28]) |= ulPeripheral & 0x0fffffff; +} +#endif + +//***************************************************************************** +// +//! Disables a peripheral in deep-sleep mode. +//! +//! \param ulPeripheral is the peripheral to disable in deep-sleep mode. +//! +//! This function causes a peripheral to stop operating when the processor goes +//! into deep-sleep mode. Disabling peripherals while in deep-sleep mode helps +//! to lower the current draw of the device, and can keep peripherals that +//! require a particular clock frequency from operating when the clock changes +//! as a result of entering deep-sleep mode. If enabled (via +//! SysCtlPeripheralEnable()), the peripheral will automatically resume +//! operation when the processor leaves deep-sleep mode, maintaining its entire +//! state from before deep-sleep mode was entered. +//! +//! Deep-sleep mode clocking of peripherals must be enabled via +//! SysCtlPeripheralClockGating(); if disabled, the peripheral deep-sleep mode +//! configuration is maintained but has no effect when deep-sleep mode is +//! entered. +//! +//! The \b ulPeripheral argument must be one of the following values: +//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG, +//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI, +//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0, +//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0, +//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA, +//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or +//! \b SYSCTL_PERIPH_GPIOE. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_peripheraldeepsleepdisable) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral) +{ + // + // Check the arguments. + // + ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) || + (ulPeripheral == SYSCTL_PERIPH_ADC) || + (ulPeripheral == SYSCTL_PERIPH_WDOG) || + (ulPeripheral == SYSCTL_PERIPH_UART0) || + (ulPeripheral == SYSCTL_PERIPH_UART1) || + (ulPeripheral == SYSCTL_PERIPH_SSI) || + (ulPeripheral == SYSCTL_PERIPH_QEI) || + (ulPeripheral == SYSCTL_PERIPH_I2C) || + (ulPeripheral == SYSCTL_PERIPH_TIMER0) || + (ulPeripheral == SYSCTL_PERIPH_TIMER1) || + (ulPeripheral == SYSCTL_PERIPH_TIMER2) || + (ulPeripheral == SYSCTL_PERIPH_COMP0) || + (ulPeripheral == SYSCTL_PERIPH_COMP1) || + (ulPeripheral == SYSCTL_PERIPH_COMP2) || + (ulPeripheral == SYSCTL_PERIPH_GPIOA) || + (ulPeripheral == SYSCTL_PERIPH_GPIOB) || + (ulPeripheral == SYSCTL_PERIPH_GPIOC) || + (ulPeripheral == SYSCTL_PERIPH_GPIOD) || + (ulPeripheral == SYSCTL_PERIPH_GPIOE)); + + // + // Disable this peripheral in deep-sleep mode. + // + HWREG(g_pulDCGCRegs[ulPeripheral >> 28]) &= ~(ulPeripheral & 0x0fffffff); +} +#endif + +//***************************************************************************** +// +//! Controls peripheral clock gating in sleep and deep-sleep mode. +//! +//! \param bEnable is a boolean that is \b true if the sleep and deep-sleep +//! peripheral configuration should be used and \b false if not. +//! +//! This function controls how peripherals are clocked when the processor goes +//! into sleep or deep-sleep mode. By default, the peripherals are clocked the +//! same as in run mode; if peripheral clock gating is enabled they are clocked +//! according to the configuration set by SysCtlPeripheralSleepEnable(), +//! SysCtlPeripheralSleepDisable(), SysCtlPeripheralDeepSleepEnable(), and +//! SysCtlPeripheralDeepSleepDisable(). +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_peripheralclockgating) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +SysCtlPeripheralClockGating(tBoolean bEnable) +{ + // + // Enable peripheral clock gating as requested. + // + if(bEnable) + { + HWREG(SYSCTL_RCC) |= SYSCTL_RCC_ACG; + } + else + { + HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_ACG); + } +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for the system control interrupt. +//! +//! \param pfnHandler is a pointer to the function to be called when the system +//! control interrupt occurs. +//! +//! This sets the handler to be called when a system control interrupt occurs. +//! This will enable the global interrupt in the interrupt controller; specific +//! system control interrupts must be enabled via SysCtlIntEnable(). It is the +//! interrupt handler's responsibility to clear the interrupt source via +//! SysCtlIntClear(). +//! +//! System control can generate interrupts when the PLL achieves lock, if the +//! internal LDO current limit is exceeded, if the internal oscillator fails, +//! if the main oscillator fails, if the internal LDO output voltage droops too +//! much, if the external voltage droops too much, or if the PLL fails. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlIntRegister(void (*pfnHandler)(void)) +{ + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(INT_SYSCTL, pfnHandler); + + // + // Enable the system control interrupt. + // + IntEnable(INT_SYSCTL); +} +#endif + +//***************************************************************************** +// +//! Unregisters the interrupt handler for the system control interrupt. +//! +//! This function will clear the handler to be called when a system control +//! interrupt occurs. This will also mask off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlIntUnregister(void) +{ + // + // Disable the interrupt. + // + IntDisable(INT_SYSCTL); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_SYSCTL); +} +#endif + +//***************************************************************************** +// +//! Enables individual system control interrupt sources. +//! +//! \param ulInts is a bit mask of the interrupt sources to be enabled. Must +//! be a logical OR of \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT, +//! \b SYSCTL_INT_IOSC_FAIL, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR, +//! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL. +//! +//! Enables the indicated system control interrupt sources. Only the sources +//! that are enabled can be reflected to the processor interrupt; disabled +//! sources have no effect on the processor. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlIntEnable(unsigned long ulInts) +{ + // + // Enable the specified interrupts. + // + HWREG(SYSCTL_IMC) |= ulInts; +} +#endif + +//***************************************************************************** +// +//! Disables individual system control interrupt sources. +//! +//! \param ulInts is a bit mask of the interrupt sources to be disabled. Must +//! be a logical OR of \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT, +//! \b SYSCTL_INT_IOSC_FAIL, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR, +//! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL. +//! +//! Disables the indicated system control interrupt sources. Only the sources +//! that are enabled can be reflected to the processor interrupt; disabled +//! sources have no effect on the processor. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlIntDisable(unsigned long ulInts) +{ + // + // Disable the specified interrupts. + // + HWREG(SYSCTL_IMC) &= ~(ulInts); +} +#endif + +//***************************************************************************** +// +//! Clears system control interrupt sources. +//! +//! \param ulInts is a bit mask of the interrupt sources to be cleared. Must +//! be a logical OR of \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT, +//! \b SYSCTL_INT_IOSC_FAIL, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR, +//! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL. +//! +//! The specified system control interrupt sources are cleared, so that they no +//! longer assert. This must be done in the interrupt handler to keep it from +//! being called again immediately upon exit. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlIntClear(unsigned long ulInts) +{ + // + // Clear the requested interrupt sources. + // + HWREG(SYSCTL_MISC) = ulInts; +} +#endif + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param bMasked is false if the raw interrupt status is required and true if +//! the masked interrupt status is required. +//! +//! This returns the interrupt status for the system controller. Either the +//! raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT, \b SYSCTL_INT_IOSC_FAIL, +//! \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR, \b SYSCTL_INT_BOR, and +//! \b SYSCTL_INT_PLL_FAIL. +// +//***************************************************************************** +#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +SysCtlIntStatus(tBoolean bMasked) +{ + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(SYSCTL_MISC)); + } + else + { + return(HWREG(SYSCTL_RIS)); + } +} +#endif + +//***************************************************************************** +// +//! Sets the output voltage of the LDO. +//! +//! \param ulVoltage is the required output voltage from the LDO. Must be one +//! of \b SYSCTL_LDO_2_25V, \b SYSCTL_LDO_2_30V, \b SYSCTL_LDO_2_35V, +//! \b SYSCTL_LDO_2_40V, \b SYSCTL_LDO_2_45V, \b SYSCTL_LDO_2_50V, +//! \b SYSCTL_LDO_2_55V, \b SYSCTL_LDO_2_60V, \b SYSCTL_LDO_2_65V, +//! \b SYSCTL_LDO_2_70V, or \b SYSCTL_LDO_2_75V. +//! +//! This function sets the output voltage of the LDO. The default voltage is +//! 2.5 V; it can be adjusted +/- 10%. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_ldoset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlLDOSet(unsigned long ulVoltage) +{ + // + // Check the arguments. + // + ASSERT((ulVoltage == SYSCTL_LDO_2_25V) || + (ulVoltage == SYSCTL_LDO_2_30V) || + (ulVoltage == SYSCTL_LDO_2_35V) || + (ulVoltage == SYSCTL_LDO_2_40V) || + (ulVoltage == SYSCTL_LDO_2_45V) || + (ulVoltage == SYSCTL_LDO_2_50V) || + (ulVoltage == SYSCTL_LDO_2_55V) || + (ulVoltage == SYSCTL_LDO_2_60V) || + (ulVoltage == SYSCTL_LDO_2_65V) || + (ulVoltage == SYSCTL_LDO_2_70V) || + (ulVoltage == SYSCTL_LDO_2_75V)); + + // + // Set the LDO voltage to the requested value. + // + HWREG(SYSCTL_LDOPCTL) = ulVoltage; +} +#endif + +//***************************************************************************** +// +//! Gets the output voltage of the LDO. +//! +//! This function determines the output voltage of the LDO, as specified by the +//! control register. +//! +//! \return Returns the current voltage of the LDO; will be one of +//! \b SYSCTL_LDO_2_25V, \b SYSCTL_LDO_2_30V, \b SYSCTL_LDO_2_35V, +//! \b SYSCTL_LDO_2_40V, \b SYSCTL_LDO_2_45V, \b SYSCTL_LDO_2_50V, +//! \b SYSCTL_LDO_2_55V, \b SYSCTL_LDO_2_60V, \b SYSCTL_LDO_2_65V, +//! \b SYSCTL_LDO_2_70V, or \b SYSCTL_LDO_2_75V. +// +//***************************************************************************** +#if defined(GROUP_ldoget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +SysCtlLDOGet(void) +{ + // + // Return the LDO voltage setting. + // + return(HWREG(SYSCTL_LDOPCTL)); +} +#endif + +//***************************************************************************** +// +//! Configures the LDO failure control. +//! +//! \param ulConfig is the required LDO failure control setting; can be either +//! \b SYSCTL_LDOCFG_ARST or \b SYSCTL_LDOCFG_NORST. +//! +//! This function allows the LDO to be configured to cause a processor reset +//! when the output voltage becomes unregulated. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_ldoconfigset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlLDOConfigSet(unsigned long ulConfig) +{ + // + // Check hte arguments. + // + ASSERT((ulConfig == SYSCTL_LDOCFG_ARST) || + (ulConfig == SYSCTL_LDOCFG_NORST)); + + // + // Set the reset control as requested. + // + HWREG(SYSCTL_LDOARST) = ulConfig; +} +#endif + +//***************************************************************************** +// +//! Resets the device. +//! +//! This function will perform a software reset of the entire device. The +//! processor and all peripherals will be reset and all device registers will +//! return to their default values (with the exception of the reset cause +//! register, which will maintain its current value but have the software reset +//! bit set as well). +//! +//! \return This function does not return. +// +//***************************************************************************** +#if defined(GROUP_reset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlReset(void) +{ + // + // Perform a software reset request. This will cause the device to reset, + // no further code will be executed. + // + HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | NVIC_APINT_SYSRESETREQ; + + // + // The device should have reset, so this should never be reached. Just in + // case, loop forever. + // + while(1) + { + } +} +#endif + +//***************************************************************************** +// +//! Puts the processor into sleep mode. +//! +//! This function places the processor into sleep mode; it will not return +//! until the processor returns to run mode. The peripherals that are enabled +//! via SysCtlPeripheralSleepEnable() continue to operate and can wake up the +//! processor (if automatic clock gating is enabled with +//! SysCtlPeripheralClockGating(), otherwise all peripherals continue to +//! operate). +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_sleep) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlSleep(void) +{ + // + // Wait for an interrupt. + // + CPUwfi(); +} +#endif + +//***************************************************************************** +// +//! Puts the processor into deep-sleep mode. +//! +//! This function places the processor into deep-sleep mode; it will not return +//! until the processor returns to run mode. The peripherals that are enabled +//! via SysCtlPeripheralDeepSleepEnable() continue to operate and can wake up +//! the processor (if automatic clock gating is enabled with +//! SysCtlPeripheralClockGating(), otherwise all peripherals continue to +//! operate). +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_deepsleep) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlDeepSleep(void) +{ + // + // Enable deep-sleep. + // + HWREG(NVIC_SYS_CTRL) |= NVIC_SYS_CTRL_SLEEPDEEP; + + // + // Wait for an interrupt. + // + CPUwfi(); + + // + // Disable deep-sleep so that a future sleep will work correctly. + // + HWREG(NVIC_SYS_CTRL) &= ~(NVIC_SYS_CTRL_SLEEPDEEP); +} +#endif + +//***************************************************************************** +// +//! Gets the reason for a reset. +//! +//! This function will return the reason(s) for a reset. Since the reset +//! reasons are sticky until either cleared by software or an external reset, +//! multiple reset reasons may be returned if multiple resets have occurred. +//! The reset reason will be a logical OR of \b SYSCTL_CAUSE_LDO, +//! \b SYSCTL_CAUSE_SW, \b SYSCTL_CAUSE_WDOG, \b SYSCTL_CAUSE_BOR, +//! \b SYSCTL_CAUSE_POR, and/or \b SYSCTL_CAUSE_EXT. +//! +//! \return The reason(s) for a reset. +// +//***************************************************************************** +#if defined(GROUP_resetcauseget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +SysCtlResetCauseGet(void) +{ + // + // Return the reset reasons. + // + return(HWREG(SYSCTL_RESC)); +} +#endif + +//***************************************************************************** +// +//! Clears reset reasons. +//! +//! \param ulCauses are the reset causes to be cleared; must be a logical OR of +//! \b SYSCTL_CAUSE_LDO, \b SYSCTL_CAUSE_SW, \b SYSCTL_CAUSE_WDOG, +//! \b SYSCTL_CAUSE_BOR, \b SYSCTL_CAUSE_POR, and/or \b SYSCTL_CAUSE_EXT. +//! +//! This function clears the specified sticky reset reasons. Once cleared, +//! another reset for the same reason can be detected, and a reset for a +//! different reason can be distinguished (instead of having two reset causes +//! set). If the reset reason is used by an application, all reset causes +//! should be cleared after they are retrieved with SysCtlResetCauseGet(). +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_resetcauseclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlResetCauseClear(unsigned long ulCauses) +{ + // + // Clear the given reset reasons. + // + HWREG(SYSCTL_RESC) &= ~(ulCauses); +} +#endif + +//***************************************************************************** +// +//! Configures the brown-out control. +//! +//! \param ulConfig is the desired configuration of the brown-out control. +//! Must be the logical OR of \b SYSCTL_BOR_RESET and/or +//! \b SYSCTL_BOR_RESAMPLE. +//! \param ulDelay is the number of internal oscillator cycles to wait before +//! resampling an asserted brown-out signal. This value only has meaning when +//! \b SYSCTL_BOR_RESAMPLE is set and must be less than 8192. +//! +//! This function configures how the brown-out control operates. It can detect +//! a brown-out by looking at only the brown-out output, or it can wait for it +//! to be active for two consecutive samples separated by a configurable time. +//! When it detects a brown-out condition, it can either reset the device or +//! generate a processor interrupt. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_brownoutconfigset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlBrownOutConfigSet(unsigned long ulConfig, unsigned long ulDelay) +{ + // + // Check the arguments. + // + ASSERT(!(ulConfig & ~(SYSCTL_BOR_RESET | SYSCTL_BOR_RESAMPLE))); + ASSERT(ulDelay < 8192); + + // + // Configure the brown-out reset control. + // + HWREG(SYSCTL_PBORCTL) = (ulDelay << SYSCTL_PBORCTL_BOR_SH) | ulConfig; +} +#endif + +//***************************************************************************** +// +//! Sets the clocking of the device. +//! +//! \param ulConfig is the required configuration of the device clocking. +//! +//! This function configures the clocking of the device. The input crystal +//! frequency, oscillator to be used, use of the PLL, and the system clock +//! divider are all configured with this function. +//! +//! The \b ulConfig parameter is the logical OR of several different values, +//! many of which are grouped into sets where only one can be chosen. +//! +//! The system clock divider is chosen with one of the following values: +//! \b SYSCTL_SYSDIV_1, \b SYSCTL_SYSDIV_2, \b SYSCTL_SYSDIV_3, +//! \b SYSCTL_SYSDIV_4, \b SYSCTL_SYSDIV_5, \b SYSCTL_SYSDIV_6, +//! \b SYSCTL_SYSDIV_7, \b SYSCTL_SYSDIV_8, \b SYSCTL_SYSDIV_9, +//! \b SYSCTL_SYSDIV_10, \b SYSCTL_SYSDIV_11, \b SYSCTL_SYSDIV_12, +//! \b SYSCTL_SYSDIV_13, \b SYSCTL_SYSDIV_14, \b SYSCTL_SYSDIV_15, or +//! \b SYSCTL_SYSDIV_16. +//! +//! The use of the PLL is chosen with either \b SYSCTL_USE_PLL or +//! \b SYSCTL_USE_OSC. +//! +//! The external crystal frequency is chosen with one of the following values: +//! \b SYSCTL_XTAL_3_57MHZ, \b SYSCTL_XTAL_3_68MHZ, \b SYSCTL_XTAL_4MHZ, +//! \b SYSCTL_XTAL_4_09MHZ, \b SYSCTL_XTAL_4_91MHZ, \b SYSCTL_XTAL_5MHZ, +//! \b SYSCTL_XTAL_5_12MHZ, \b SYSCTL_XTAL_6MHZ, \b SYSCTL_XTAL_6_14MHZ, +//! \b SYSCTL_XTAL_7_37MHZ, \b SYSCTL_XTAL_8MHZ, or \b SYSCTL_XTAL_8_19MHZ. +//! +//! The oscillator source is chosen with one of the following values: +//! \b SYSCTL_OSC_MAIN, \b SYSCTL_OSC_INT, or \b SYSCTL_OSC_INT4. +//! +//! The internal and main oscillators are disabled with the +//! \b SYSCTL_INT_OSC_DIS and \b SYSCTL_MAIN_OSC_DIS flags, respectively. +//! The external oscillator must be enabled in order to use an external clock +//! source. Note that attempts to disable the oscillator used to clock the +//! device will be prevented by the hardware. +//! +//! To clock the system from an external source (such as an external crystal +//! oscillator), use \b SYSCTL_USE_OSC \b | \b SYSCTL_OSC_MAIN. To clock the +//! system from the main oscillator, use \b SYSCTL_USE_OSC \b | +//! \b SYSCTL_OSC_MAIN. To clock the system from the PLL, use +//! \b SYSCTL_USE_PLL \b | \b SYSCTL_OSC_MAIN, and select the appropriate +//! crystal with one of the \b SYSCTL_XTAL_xxx values. +//! +//! \note If selecting the PLL as the system clock source (i.e. via +//! \b SYSCTL_USE_PLL), this function will poll the PLL lock interrupt to +//! determine when the PLL has locked. If an interrupt handler for the +//! system control interrupt is in place, and it responds to and clears the +//! PLL lock interrupt, this function will delay until its timeout has occurred +//! instead of completing as soon as PLL lock is achieved. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_clockset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlClockSet(unsigned long ulConfig) +{ + volatile unsigned long ulDelay; + unsigned long ulRCC; + + // + // Get the current value of the RCC register. + // + ulRCC = HWREG(SYSCTL_RCC); + + // + // Bypass the PLL and system clock dividers for now. + // + ulRCC |= SYSCTL_RCC_BYPASS; + ulRCC &= ~(SYSCTL_RCC_USE_SYSDIV); + + // + // Write the new RCC value. + // + HWREG(SYSCTL_RCC) = ulRCC; + + // + // Make sure that the PLL and system clock dividers are bypassed for now. + // + ulRCC |= SYSCTL_RCC_BYPASS; + ulRCC &= ~(SYSCTL_RCC_USE_SYSDIV); + + // + // Make sure that the required oscillators are enabled. For now, the + // previously enabled oscillators must be enabled along with the newly + // requested oscillators. + // + ulRCC &= (~(SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS) | + (ulConfig & (SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS))); + + // + // Set the new crystal value, oscillator source, and PLL configuration. + // + ulRCC &= ~(SYSCTL_RCC_XTAL_MASK | SYSCTL_RCC_OSCSRC_MASK | + SYSCTL_RCC_PWRDN | SYSCTL_RCC_OE); + ulRCC |= ulConfig & (SYSCTL_RCC_XTAL_MASK | SYSCTL_RCC_OSCSRC_MASK | + SYSCTL_RCC_PWRDN | SYSCTL_RCC_OE); + + // + // Clear the PLL lock interrupt. + // + HWREG(SYSCTL_MISC) = SYSCTL_INT_PLL_LOCK; + + // + // Write the new RCC value. + // + HWREG(SYSCTL_RCC) = ulRCC; + + // + // Wait for a bit so that new crystal value and oscillator source can take + // effect. One of the oscillators may need to be started as well. + // + for(ulDelay = 0; ulDelay < 16; ulDelay++) + { + } + + // + // Disable the appropriate oscillators. + // + ulRCC &= ~(SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS); + ulRCC |= ulConfig & (SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS); + + // + // Write the new RCC value. + // + HWREG(SYSCTL_RCC) = ulRCC; + + // + // Set the requested system divider. This will not get written + // immediately. + // + ulRCC &= ~(SYSCTL_RCC_SYSDIV_MASK | SYSCTL_RCC_USE_SYSDIV); + ulRCC |= ulConfig & (SYSCTL_RCC_SYSDIV_MASK | SYSCTL_RCC_USE_SYSDIV); + + // + // See if the PLL output is being used to clock the system. + // + if(!(ulConfig & SYSCTL_RCC_BYPASS)) + { + // + // Wait until the PLL has locked. + // + for(ulDelay = 32768; ulDelay > 0; ulDelay--) + { + if(HWREG(SYSCTL_RIS) & SYSCTL_INT_PLL_LOCK) + { + break; + } + } + + // + // Enable use of the PLL. + // + ulRCC &= ~(SYSCTL_RCC_BYPASS); + } + + // + // Write the final RCC value. + // + HWREG(SYSCTL_RCC) = ulRCC; + + // + // Delay for a little bit so that the system divider takes effect. + // + for(ulDelay = 0; ulDelay < 16; ulDelay++) + { + } +} +#endif + +//***************************************************************************** +// +//! Gets the processor clock rate. +//! +//! This function determines the clock rate of the processor clock. This is +//! also the clock rate of all the peripheral modules (with the exception of +//! PWM, which has its own clock divider). +//! +//! \note This will not return accurate results if SysCtlClockSet() has not +//! been called to configure the clocking of the device, or if the device is +//! directly clocked from a crystal (or a clock source) that is not one of the +//! supported crystal frequencies. In the later case, this function should be +//! modified to directly return the correct system clock rate. +//! +//! \return The processor clock rate. +// +//***************************************************************************** +#if defined(GROUP_clockget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +SysCtlClockGet(void) +{ + unsigned long ulRCC, ulPLL, ulClk; + + // + // Read RCC. + // + ulRCC = HWREG(SYSCTL_RCC); + + // + // Get the base clock rate. + // + switch(ulRCC & SYSCTL_RCC_OSCSRC_MASK) + { + // + // The main oscillator is the clock source. Determine its rate from + // the crystal setting field. + // + case SYSCTL_RCC_OSCSRC_MAIN: + { + ulClk = g_pulXtals[((ulRCC & SYSCTL_RCC_XTAL_MASK) >> + SYSCTL_RCC_XTAL_SHIFT) - + (SYSCTL_RCC_XTAL_3_57MHZ >> + SYSCTL_RCC_XTAL_SHIFT)]; + break; + } + + // + // The internal oscillator is the source clock. This is not an + // accurate clock (it is +/- 50%); what is used is the nominal. + // + case SYSCTL_RCC_OSCSRC_INT: + { + ulClk = 15000000; + break; + } + + // + // The internal oscillator divided by four is the source clock. This + // is not an accurate clock (it is +/- 50%); what is used is the + // nominal. + // + case SYSCTL_RCC_OSCSRC_INT4: + { + ulClk = 15000000 / 4; + break; + } + + // + // An unknown setting, so return a zero clock (i.e. an unknown clock + // rate). + // + default: + { + return(0); + } + } + + // + // See if the PLL is being used. + // + if(!(ulRCC & SYSCTL_RCC_BYPASS)) + { + // + // Get the PLL configuration. + // + ulPLL = HWREG(SYSCTL_PLLCFG); + + // + // Compute the PLL output frequency based on its input frequency. + // + ulClk = ((ulClk * (((ulPLL & SYSCTL_PLLCFG_F_MASK) >> + SYSCTL_PLLCFG_F_SHIFT) + 2)) / + (((ulPLL & SYSCTL_PLLCFG_R_MASK) >> + SYSCTL_PLLCFG_R_SHIFT) + 2)); + + // + // See if the optional output divide by 2 is being used. + // + if(ulPLL & SYSCTL_PLLCFG_OD_2) + { + ulClk /= 2; + } + + // + // See if the optional output divide by 4 is being used. + // + if(ulPLL & SYSCTL_PLLCFG_OD_4) + { + ulClk /= 4; + } + } + + // + // See if the system divider is being used. + // + if(ulRCC & SYSCTL_RCC_USE_SYSDIV) + { + // + // Adjust the clock rate by the system clock divider. + // + ulClk /= ((ulRCC & SYSCTL_RCC_SYSDIV_MASK) >> + SYSCTL_RCC_SYSDIV_SHIFT) + 1; + } + + // + // Return the computed clock rate. + // + return(ulClk); +} +#endif + +//***************************************************************************** +// +//! Sets the PWM clock configuration. +//! +//! \param ulConfig is the configuration for the PWM clock; it must be one of +//! \b SYSCTL_PWMDIV_1, \b SYSCTL_PWMDIV_2, \b SYSCTL_PWMDIV_4, +//! \b SYSCTL_PWMDIV_8, \b SYSCTL_PWMDIV_16, \b SYSCTL_PWMDIV_32, or +//! \b SYSCTL_PWMDIV_64. +//! +//! This function sets the rate of the clock provided to the PWM module as a +//! ratio of the processor clock. This clock is used by the PWM module to +//! generate PWM signals; its rate forms the basis for all PWM signals. +//! +//! \note The clocking of the PWM is dependent upon the system clock rate as +//! configured by SysCtlClockSet(). +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pwmclockset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlPWMClockSet(unsigned long ulConfig) +{ + // + // Check the arguments. + // + ASSERT((ulConfig == SYSCTL_PWMDIV_1) || + (ulConfig == SYSCTL_PWMDIV_2) || + (ulConfig == SYSCTL_PWMDIV_4) || + (ulConfig == SYSCTL_PWMDIV_8) || + (ulConfig == SYSCTL_PWMDIV_16) || + (ulConfig == SYSCTL_PWMDIV_32) || + (ulConfig == SYSCTL_PWMDIV_64)); + + // + // Check that there is a PWM block on this part. + // + ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_PWM); + + // + // Set the PWM clock configuration into the run-mode clock configuration + // register. + // + HWREG(SYSCTL_RCC) = ((HWREG(SYSCTL_RCC) & + ~(SYSCTL_RCC_USE_PWMDIV | SYSCTL_RCC_PWMDIV_MASK)) | + ulConfig); +} +#endif + +//***************************************************************************** +// +//! Gets the current PWM clock configuration. +//! +//! This function returns the current PWM clock configuration. +//! +//! \return The current PWM clock configuration; will be one of +//! \b SYSCTL_PWMDIV_1, \b SYSCTL_PWMDIV_2, \b SYSCTL_PWMDIV_4, +//! \b SYSCTL_PWMDIV_8, \b SYSCTL_PWMDIV_16, \b SYSCTL_PWMDIV_32, or +//! \b SYSCTL_PWMDIV_64. +// +//***************************************************************************** +#if defined(GROUP_pwmclockget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +SysCtlPWMClockGet(void) +{ + // + // Check that there is a PWM block on this part. + // + ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_PWM); + + // + // Return the current PWM clock configuration. + // + return(HWREG(SYSCTL_RCC) & + (SYSCTL_RCC_USE_PWMDIV | SYSCTL_RCC_PWMDIV_MASK)); +} +#endif + +//***************************************************************************** +// +//! Sets the sample rate of the ADC. +//! +//! \param ulSpeed is the desired sample rate of the ADC; must be one of +//! \b SYSCTL_ADCSPEED_1MSPS, \b SYSCTL_ADCSPEED_500KSPS, +//! \b SYSCTL_ADCSPEED_250KSPS, or \b SYSCTL_ADCSPEED_125KSPS. +//! +//! This function sets the rate at which the ADC samples are captured by the +//! ADC block. The sampling speed may be limited by the hardware, so the +//! sample rate may end up being slower than requested. SysCtlADCSpeedGet() +//! will return the actual speed in use. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_adcspeedset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlADCSpeedSet(unsigned long ulSpeed) +{ + // + // Check the arguments. + // + ASSERT((ulSpeed == SYSCTL_ADCSPEED_1MSPS) || + (ulSpeed == SYSCTL_ADCSPEED_500KSPS) || + (ulSpeed == SYSCTL_ADCSPEED_250KSPS) || + (ulSpeed == SYSCTL_ADCSPEED_125KSPS)); + + // + // Check that there is an ADC block on this part. + // + ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_ADC); + + // + // Set the ADC speed in run, sleep, and deep-sleep mode. + // + HWREG(SYSCTL_RCGC0) = ((HWREG(SYSCTL_RCGC0) & ~(SYSCTL_SET0_ADCSPD_MASK)) | + ulSpeed); + HWREG(SYSCTL_SCGC0) = ((HWREG(SYSCTL_SCGC0) & ~(SYSCTL_SET0_ADCSPD_MASK)) | + ulSpeed); + HWREG(SYSCTL_DCGC0) = ((HWREG(SYSCTL_DCGC0) & ~(SYSCTL_SET0_ADCSPD_MASK)) | + ulSpeed); +} +#endif + +//***************************************************************************** +// +//! Gets the sample rate of the ADC. +//! +//! This function gets the current sample rate of the ADC. +//! +//! \return Returns the current ADC sample rate; will be one of +//! \b SYSCTL_ADCSPEED_1MSPS, \b SYSCTL_ADCSPEED_500KSPS, +//! \b SYSCTL_ADCSPEED_250KSPS, or \b SYSCTL_ADCSPEED_125KSPS. +// +//***************************************************************************** +#if defined(GROUP_adcspeedget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +SysCtlADCSpeedGet(void) +{ + // + // Check that there is an ADC block on this part. + // + ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_ADC); + + // + // Return the current ADC speed. + // + return(HWREG(SYSCTL_RCGC0) & SYSCTL_SET0_ADCSPD_MASK); +} +#endif + +//***************************************************************************** +// +//! Configures the internal oscillator verification timer. +//! +//! \param bEnable is a boolean that is \b true if the internal oscillator +//! verification timer should be enabled. +//! +//! This function allows the internal oscillator verification timer to be +//! enabled or disabled. When enabled, an interrupt will be generated if the +//! internal oscillator ceases to operate. +//! +//! \note Both oscillators (main and internal) must be enabled for this +//! verification timer to operate as the main oscillator will verify the +//! internal oscillator. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_boscverificationset) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +SysCtlIOSCVerificationSet(tBoolean bEnable) +{ + // + // Enable or disable the internal oscillator verification timer as + // requested. + // + if(bEnable) + { + HWREG(SYSCTL_RCC) |= SYSCTL_RCC_IOSCVER; + } + else + { + HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_IOSCVER); + } +} +#endif + +//***************************************************************************** +// +//! Configures the main oscillator verification timer. +//! +//! \param bEnable is a boolean that is \b true if the main oscillator +//! verification timer should be enabled. +//! +//! This function allows the main oscillator verification timer to be enabled +//! or disabled. When enabled, an interrupt will be generated if the main +//! oscillator ceases to operate. +//! +//! \note Both oscillators (main and internal) must be enabled for this +//! verification timer to operate as the internal oscillator will verify the +//! main oscillator. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_moscverificationset) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +SysCtlMOSCVerificationSet(tBoolean bEnable) +{ + // + // Enable or disable the main oscillator verification timer as requested. + // + if(bEnable) + { + HWREG(SYSCTL_RCC) |= SYSCTL_RCC_MOSCVER; + } + else + { + HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_MOSCVER); + } +} +#endif + +//***************************************************************************** +// +//! Configures the PLL verification timer. +//! +//! \param bEnable is a boolean that is \b true if the PLL verification timer +//! should be enabled. +//! +//! This function allows the PLL verification timer to be enabled or disabled. +//! When enabled, an interrupt will be generated if the PLL ceases to operate. +//! +//! \note The main oscillator must be enabled for this verification timer to +//! operate as it is used to check the PLL. Also, the verification timer +//! should be disabled while the PLL is being reconfigured via +//! SysCtlClockSet(). +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_pllverificationset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysCtlPLLVerificationSet(tBoolean bEnable) +{ + // + // Enable or disable the PLL verification timer as requested. + // + if(bEnable) + { + HWREG(SYSCTL_RCC) |= SYSCTL_RCC_PLLVER; + } + else + { + HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_PLLVER); + } +} +#endif + +//***************************************************************************** +// +//! Clears the clock verification status. +//! +//! This function clears the status of the clock verification timers, allowing +//! them to assert another failure if detected. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_clkverificationclear) || defined(BUILD_ALL) || \ + defined(DOXYGEN) +void +SysCtlClkVerificationClear(void) +{ + // + // Clear the clock verification. + // + HWREG(SYSCTL_CLKVCLR) = SYSCTL_CLKVCLR_CLR; + + // + // The bit does not self-reset, so clear it. + // + HWREG(SYSCTL_CLKVCLR) = 0; +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/sysctl.h b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/sysctl.h new file mode 100644 index 000000000..94b147084 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/sysctl.h @@ -0,0 +1,285 @@ +//***************************************************************************** +// +// sysctl.h - Prototypes for the system control driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __SYSCTL_H__ +#define __SYSCTL_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed to the +// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(), +// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the +// ulPeripheral parameter. The peripherals in the fourth group (upper nibble +// is 3) can only be used with the SysCtlPeripheralPresent() API. +// +//***************************************************************************** +#define SYSCTL_PERIPH_PWM 0x00100000 // PWM +#define SYSCTL_PERIPH_ADC 0x00010000 // ADC +#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog +#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0 +#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1 +#define SYSCTL_PERIPH_SSI 0x10000010 // SSI +#define SYSCTL_PERIPH_QEI 0x10000100 // QEI +#define SYSCTL_PERIPH_I2C 0x10001000 // I2C +#define SYSCTL_PERIPH_TIMER0 0x10010000 // Timer 0 +#define SYSCTL_PERIPH_TIMER1 0x10020000 // Timer 1 +#define SYSCTL_PERIPH_TIMER2 0x10040000 // Timer 2 +#define SYSCTL_PERIPH_COMP0 0x11000000 // Analog comparator 0 +#define SYSCTL_PERIPH_COMP1 0x12000000 // Analog comparator 1 +#define SYSCTL_PERIPH_COMP2 0x14000000 // Analog comparator 2 +#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A +#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B +#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C +#define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D +#define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E +#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex M3 MPU +#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor +#define SYSCTL_PERIPH_PLL 0x30000010 // PLL + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlPinPresent() API +// as the ulPin parameter. +// +//***************************************************************************** +#define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin +#define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin +#define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin +#define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin +#define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin +#define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin +#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin +#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin +#define SYSCTL_PIN_C0O 0x00000100 // C0o pin +#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin +#define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin +#define SYSCTL_PIN_C1O 0x00000800 // C1o pin +#define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin +#define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin +#define SYSCTL_PIN_C2O 0x00004000 // C2o pin +#define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin +#define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin +#define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin +#define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin +#define SYSCTL_PIN_ADC4 0x00100000 // ADC4 pin +#define SYSCTL_PIN_ADC5 0x00200000 // ADC5 pin +#define SYSCTL_PIN_ADC6 0x00400000 // ADC6 pin +#define SYSCTL_PIN_ADC7 0x00800000 // ADC7 pin +#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin +#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin +#define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin +#define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin +#define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin +#define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin +#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlLDOSet() API as +// the ulVoltage value, or returned by the SysCtlLDOGet() API. +// +//***************************************************************************** +#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V +#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V +#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V +#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V +#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V +#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V +#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V +#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V +#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V +#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V +#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlLDOConfigSet() API. +// +//***************************************************************************** +#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset +#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlIntEnable(), +// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask +// by the SysCtlIntStatus() API. +// +//***************************************************************************** +#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt +#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt +#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int +#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int +#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt +#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt +#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlResetCauseClear() +// API or returned by the SysCtlResetCauseGet() API. +// +//***************************************************************************** +#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset +#define SYSCTL_CAUSE_SW 0x00000010 // Software reset +#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset +#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset +#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset +#define SYSCTL_CAUSE_EXT 0x00000001 // External reset + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlBrownOutConfigSet() +// API as the ulConfig parameter. +// +//***************************************************************************** +#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting +#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlPWMClockSet() API +// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet() +// API. +// +//***************************************************************************** +#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1 +#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2 +#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4 +#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8 +#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16 +#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32 +#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64 + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlADCSpeedSet() API +// as the ulSpeed parameter, and can be returned by the SyCtlADCSpeedGet() +// API. +// +//***************************************************************************** +#define SYSCTL_ADCSPEED_1MSPS 0x00000300 // 1,000,000 samples per second +#define SYSCTL_ADCSPEED_500KSPS 0x00000200 // 500,000 samples per second +#define SYSCTL_ADCSPEED_250KSPS 0x00000100 // 250,000 samples per second +#define SYSCTL_ADCSPEED_125KSPS 0x00000000 // 125,000 samples per second + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlClockSet() API as +// the ulConfig parameter. +// +//***************************************************************************** +#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1 +#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2 +#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3 +#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4 +#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5 +#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6 +#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7 +#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8 +#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9 +#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10 +#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11 +#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12 +#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13 +#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14 +#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15 +#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16 +#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock +#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock +#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz +#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz +#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz +#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz +#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz +#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz +#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz +#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz +#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz +#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz +#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz +#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz +#define SYSCTL_OSC_MAIN 0x00000000 // Oscillator source is main osc +#define SYSCTL_OSC_INT 0x00000010 // Oscillator source is int. osc +#define SYSCTL_OSC_INT4 0x00000020 // Oscillator source is int. osc /4 +#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator +#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern unsigned long SysCtlSRAMSizeGet(void); +extern unsigned long SysCtlFlashSizeGet(void); +extern tBoolean SysCtlPinPresent(unsigned long ulPin); +extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral); +extern void SysCtlPeripheralReset(unsigned long ulPeripheral); +extern void SysCtlPeripheralEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralClockGating(tBoolean bEnable); +extern void SysCtlIntRegister(void (*pfnHandler)(void)); +extern void SysCtlIntUnregister(void); +extern void SysCtlIntEnable(unsigned long ulInts); +extern void SysCtlIntDisable(unsigned long ulInts); +extern void SysCtlIntClear(unsigned long ulInts); +extern unsigned long SysCtlIntStatus(tBoolean bMasked); +extern void SysCtlLDOSet(unsigned long ulVoltage); +extern unsigned long SysCtlLDOGet(void); +extern void SysCtlLDOConfigSet(unsigned long ulConfig); +extern void SysCtlReset(void); +extern void SysCtlSleep(void); +extern void SysCtlDeepSleep(void); +extern unsigned long SysCtlResetCauseGet(void); +extern void SysCtlResetCauseClear(unsigned long ulCauses); +extern void SysCtlBrownOutConfigSet(unsigned long ulConfig, + unsigned long ulDelay); +extern void SysCtlClockSet(unsigned long ulConfig); +extern unsigned long SysCtlClockGet(void); +extern void SysCtlPWMClockSet(unsigned long ulConfig); +extern unsigned long SysCtlPWMClockGet(void); +extern void SysCtlADCSpeedSet(unsigned long ulSpeed); +extern unsigned long SysCtlADCSpeedGet(void); +extern void SysCtlIOSCVerificationSet(tBoolean bEnable); +extern void SysCtlMOSCVerificationSet(tBoolean bEnable); +extern void SysCtlPLLVerificationSet(tBoolean bEnable); +extern void SysCtlClkVerificationClear(void); + +#ifdef __cplusplus +} +#endif + +#endif // __SYSCTL_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/systick.c b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/systick.c new file mode 100644 index 000000000..382533513 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/systick.c @@ -0,0 +1,262 @@ +//***************************************************************************** +// +// systick.c - Driver for the SysTick timer in NVIC. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup systick_api +//! @{ +// +//***************************************************************************** + +#include "../hw_ints.h" +#include "../hw_nvic.h" +#include "../hw_types.h" +#include "debug.h" +#include "interrupt.h" +#include "systick.h" + +//***************************************************************************** +// +//! Enables the SysTick counter. +//! +//! This will start the SysTick counter. If an interrupt handler has been +//! registered, it will be called when the SysTick counter rolls over. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysTickEnable(void) +{ + // + // Enable SysTick. + // + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_CLK_SRC | NVIC_ST_CTRL_ENABLE; +} +#endif + +//***************************************************************************** +// +//! Disables the SysTick counter. +//! +//! This will stop the SysTick counter. If an interrupt handler has been +//! registered, it will no longer be called until SysTick is restarted. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysTickDisable(void) +{ + // + // Disable SysTick. + // + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_ENABLE); +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for the SysTick interrupt. +//! +//! \param pfnHandler is a pointer to the function to be called when the +//! SysTick interrupt occurs. +//! +//! This sets the handler to be called when a SysTick interrupt occurs. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysTickIntRegister(void (*pfnHandler)(void)) +{ + // + // Register the interrupt handler, returning an error if an error occurs. + // + IntRegister(FAULT_SYSTICK, pfnHandler); + + // + // Enable the SysTick interrupt. + // + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; +} +#endif + +//***************************************************************************** +// +//! Unregisters the interrupt handler for the SysTick interrupt. +//! +//! This function will clear the handler to be called when a SysTick interrupt +//! occurs. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysTickIntUnregister(void) +{ + // + // Disable the SysTick interrupt. + // + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); + + // + // Unregister the interrupt handler. + // + IntUnregister(FAULT_SYSTICK); +} +#endif + +//***************************************************************************** +// +//! Enables the SysTick interrupt. +//! +//! This function will enable the SysTick interrupt, allowing it to be +//! reflected to the processor. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysTickIntEnable(void) +{ + // + // Enable the SysTick interrupt. + // + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; +} +#endif + +//***************************************************************************** +// +//! Disables the SysTick interrupt. +//! +//! This function will disable the SysTick interrupt, preventing it from being +//! reflected to the processor. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysTickIntDisable(void) +{ + // + // Disable the SysTick interrupt. + // + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); +} +#endif + +//***************************************************************************** +// +//! Sets the period of the SysTick counter. +//! +//! \param ulPeriod is the number of clock ticks in each period of the SysTick +//! counter; must be between 1 and 16,777,216, inclusive. +//! +//! This function sets the rate at which the SysTick counter wraps; this +//! equates to the number of processor clocks between interrupts. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_periodset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +SysTickPeriodSet(unsigned long ulPeriod) +{ + // + // Check the arguments. + // + ASSERT((ulPeriod > 0) && (ulPeriod <= 16777216)); + + // + // Set the period of the SysTick counter. + // + HWREG(NVIC_ST_RELOAD) = ulPeriod - 1; +} +#endif + +//***************************************************************************** +// +//! Gets the period of the SysTick counter. +//! +//! This function returns the rate at which the SysTick counter wraps; this +//! equates to the number of processor clocks between interrupts. +//! +//! \return Returns the period of the SysTick counter. +// +//***************************************************************************** +#if defined(GROUP_periodget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +SysTickPeriodGet(void) +{ + // + // Return the period of the SysTick counter. + // + return(HWREG(NVIC_ST_RELOAD) + 1); +} +#endif + +//***************************************************************************** +// +//! Gets the current value of the SysTick counter. +//! +//! This function returns the current value of the SysTick counter; this will +//! be a value between the period - 1 and zero, inclusive. +//! +//! \return Returns the current value of the SysTick counter. +// +//***************************************************************************** +#if defined(GROUP_valueget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +SysTickValueGet(void) +{ + // + // Return the current value of the SysTick counter. + // + return(HWREG(NVIC_ST_CURRENT)); +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/systick.h b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/systick.h new file mode 100644 index 000000000..bfddfb16f --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/systick.h @@ -0,0 +1,55 @@ +//***************************************************************************** +// +// systick.h - Prototypes for the SysTick driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __SYSTICK_H__ +#define __SYSTICK_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void SysTickEnable(void); +extern void SysTickDisable(void); +extern void SysTickIntRegister(void (*pfnHandler)(void)); +extern void SysTickIntUnregister(void); +extern void SysTickIntEnable(void); +extern void SysTickIntDisable(void); +extern void SysTickPeriodSet(unsigned long ulPeriod); +extern unsigned long SysTickPeriodGet(void); +extern unsigned long SysTickValueGet(void); + +#ifdef __cplusplus +} +#endif + +#endif // __SYSTICK_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/timer.c b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/timer.c new file mode 100644 index 000000000..46ce19a30 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/timer.c @@ -0,0 +1,1125 @@ +//***************************************************************************** +// +// timer.c - Driver for the timer module. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup timer_api +//! @{ +// +//***************************************************************************** + +#include "../hw_ints.h" +#include "../hw_memmap.h" +#include "../hw_timer.h" +#include "../hw_types.h" +#include "debug.h" +#include "interrupt.h" +#include "timer.h" + +//***************************************************************************** +// +//! Enables the timer(s). +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to enable; must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! +//! This will enable operation of the timer module. The timer must be +//! configured before it is enabled. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerEnable(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Enable the timer(s) module. + // + HWREG(ulBase + TIMER_O_CTL) |= ulTimer & (TIMER_CTL_TAEN | TIMER_CTL_TBEN); +} +#endif + +//***************************************************************************** +// +//! Disables the timer(s). +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to disable; must be one of +//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. +//! +//! This will disable operation of the timer module. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerDisable(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Disable the timer module. + // + HWREG(ulBase + TIMER_O_CTL) &= ~(ulTimer & + (TIMER_CTL_TAEN | TIMER_CTL_TBEN)); +} +#endif + +//***************************************************************************** +// +//! Configures the timer(s). +//! +//! \param ulBase is the base address of the timer module. +//! \param ulConfig is the configuration for the timer. +//! +//! This function configures the operating mode of the timer(s). The timer +//! module is disabled before being configured, and is left in the disabled +//! state. The configuration is specified in \e ulConfig as one of the +//! following values: +//! +//! - \b TIMER_CFG_32_BIT_OS - 32-bit one shot timer +//! - \b TIMER_CFG_32_BIT_PER - 32-bit periodic timer +//! - \b TIMER_CFG_32_RTC - 32-bit real time clock timer +//! - \b TIMER_CFG_16_BIT_PAIR - Two 16-bit timers +//! +//! When configured for a pair of 16-bit timers, each timer is separately +//! configured. The first timer is configured by setting \e ulConfig to +//! the result of a logical OR operation between one of the following values +//! and \e ulConfig: +//! +//! - \b TIMER_CFG_A_ONE_SHOT - 16-bit one shot timer +//! - \b TIMER_CFG_A_PERIODIC - 16-bit periodic timer +//! - \b TIMER_CFG_A_CAP_COUNT - 16-bit edge count capture +//! - \b TIMER_CFG_A_CAP_TIME - 16-bit edge time capture +//! - \b TIMER_CFG_A_PWM - 16-bit PWM output +//! +//! Similarly, the second timer is configured by setting \e ulConfig to +//! the result of a logical OR operation between one of the corresponding +//! \b TIMER_CFG_B_* values and \e ulConfig. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_configure) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerConfigure(unsigned long ulBase, unsigned long ulConfig) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulConfig == TIMER_CFG_32_BIT_OS) || + (ulConfig == TIMER_CFG_32_BIT_PER) || + (ulConfig == TIMER_CFG_32_RTC) || + ((ulConfig & 0xff000000) == TIMER_CFG_16_BIT_PAIR)); + ASSERT(((ulConfig & 0xff000000) != TIMER_CFG_16_BIT_PAIR) || + ((((ulConfig & 0x000000ff) == TIMER_CFG_A_ONE_SHOT) || + ((ulConfig & 0x000000ff) == TIMER_CFG_A_PERIODIC) || + ((ulConfig & 0x000000ff) == TIMER_CFG_A_CAP_COUNT) || + ((ulConfig & 0x000000ff) == TIMER_CFG_A_CAP_TIME) || + ((ulConfig & 0x000000ff) == TIMER_CFG_A_PWM)) && + (((ulConfig & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT) || + ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PERIODIC) || + ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_COUNT) || + ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_TIME) || + ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PWM)))); + + // + // Disable the timers. + // + HWREG(ulBase + TIMER_O_CTL) &= ~(TIMER_CTL_TAEN | TIMER_CTL_TBEN); + + // + // Set the global timer configuration. + // + HWREG(ulBase + TIMER_O_CFG) = ulConfig >> 24; + + // + // Set the configuration of the A and B timers. Note that the B timer + // configuration is ignored by the hardware in 32-bit modes. + // + HWREG(ulBase + TIMER_O_TAMR) = ulConfig & 255; + HWREG(ulBase + TIMER_O_TBMR) = (ulConfig >> 8) & 255; +} +#endif + +//***************************************************************************** +// +//! Controls the output level. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! \param bInvert specifies the output level. +//! +//! This function sets the PWM output level for the specified timer. If the +//! parameter \e bInvert is \b true, then the timer's output will be made +//! active low; otherwise, it will be made active high. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_controllevel) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, + tBoolean bInvert) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Set the output levels as requested. + // + ulTimer &= TIMER_CTL_TAPWML | TIMER_CTL_TBPWML; + HWREG(ulBase + TIMER_O_CTL) = (bInvert ? + (HWREG(ulBase + TIMER_O_CTL) | ulTimer) : + (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer))); +} +#endif + +//***************************************************************************** +// +//! Enables or disables the trigger output. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer to adjust; must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! \param bEnable specifies the desired trigger state. +//! +//! This function controls the trigger output for the specified timer. If the +//! parameter \e bEnable is \b true, then the timer's output trigger is +//! enabled; otherwise it is disabled. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_controltrigger) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer, + tBoolean bEnable) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Set the trigger output as requested. + // + ulTimer &= TIMER_CTL_TAOTE | TIMER_CTL_TBOTE; + HWREG(ulBase + TIMER_O_CTL) = (bEnable ? + (HWREG(ulBase + TIMER_O_CTL) | ulTimer) : + (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer))); +} +#endif + +//***************************************************************************** +// +//! Controls the event type. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to be adjusted; must be one of +//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. +//! \param ulEvent specifies the type of event; must be one of +//! \b TIMER_EVENT_POS_EDGE, \b TIMER_EVENT_NEG_EDGE, or +//! \b TIMER_EVENT_BOTH_EDGES. +//! +//! This function sets the signal edge(s) that will trigger the timer when in +//! capture mode. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_controlevent) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulEvent) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Set the event type. + // + ulEvent &= ulTimer & (TIMER_CTL_TAEVENT_MSK | TIMER_CTL_TBEVENT_MSK); + HWREG(ulBase + TIMER_O_CTL) = ((HWREG(ulBase + TIMER_O_CTL) & + ~(TIMER_CTL_TAEVENT_MSK | + TIMER_CTL_TBEVENT_MSK)) | ulEvent); +} +#endif + +//***************************************************************************** +// +//! Controls the stall handling. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to be adjusted; must be one of +//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. +//! \param bStall specifies the response to a stall signal. +//! +//! This function controls the stall response for the specified timer. If the +//! parameter \e bStall is \b true, then the timer will stop counting if the +//! processor enters debug mode; otherwise the timer will keep running while in +//! debug mode. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_controlstall) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerControlStall(unsigned long ulBase, unsigned long ulTimer, + tBoolean bStall) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Set the stall mode. + // + ulTimer &= TIMER_CTL_TASTALL | TIMER_CTL_TBSTALL; + HWREG(ulBase + TIMER_O_CTL) = (bStall ? + (HWREG(ulBase + TIMER_O_CTL) | ulTimer) : + (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer))); +} +#endif + +//***************************************************************************** +// +//! Enable RTC counting. +//! +//! \param ulBase is the base address of the timer module. +//! +//! This function causes the timer to start counting when in RTC mode. If not +//! configured for RTC mode, this will do nothing. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_rtcenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerRTCEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + + // + // Enable RTC counting. + // + HWREG(ulBase + TIMER_O_CTL) |= TIMER_CTL_RTCEN; +} +#endif + +//***************************************************************************** +// +//! Disable RTC counting. +//! +//! \param ulBase is the base address of the timer module. +//! +//! This function causes the timer to stop counting when in RTC mode. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_rtcdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerRTCDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + + // + // Disable RTC counting. + // + HWREG(ulBase + TIMER_O_CTL) &= ~(TIMER_CTL_RTCEN); +} +#endif + +//***************************************************************************** +// +//! Set the timer prescale value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! \param ulValue is the timer prescale value; must be between 0 and 255, +//! inclusive. +//! +//! This function sets the value of the input clock prescaler. The prescaler +//! is only operational when in 16-bit mode and is used to extend the range of +//! the 16-bit timer modes. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_prescaleset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + ASSERT(ulValue < 256); + + // + // Set the timer A prescaler if requested. + // + if(ulTimer & TIMER_A) + { + HWREG(ulBase + TIMER_O_TAPR) = ulValue; + } + + // + // Set the timer B prescaler if requested. + // + if(ulTimer & TIMER_B) + { + HWREG(ulBase + TIMER_O_TBPR) = ulValue; + } +} +#endif + +//***************************************************************************** +// +//! Get the timer prescale value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer; must be one of \b TIMER_A or +//! \b TIMER_B. +//! +//! This function gets the value of the input clock prescaler. The prescaler +//! is only operational when in 16-bit mode and is used to extend the range of +//! the 16-bit timer modes. +//! +//! \return The value of the timer prescaler. +// +//***************************************************************************** +#if defined(GROUP_prescaleget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +TimerPrescaleGet(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Return the appropriate prescale value. + // + return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAPR) : + HWREG(ulBase + TIMER_O_TBPR)); +} +#endif + +//***************************************************************************** +// +//! Set the timer prescale match value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! \param ulValue is the timer prescale match value; must be between 0 and +//! 255, inclusive. +//! +//! This function sets the value of the input clock prescaler match value. +//! When in a 16-bit mode that uses the counter match (edge count or PWM), the +//! prescale match effectively extends the range of the counter to 24-bits. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_prescalematchset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + ASSERT(ulValue < 256); + + // + // Set the timer A prescale match if requested. + // + if(ulTimer & TIMER_A) + { + HWREG(ulBase + TIMER_O_TAPMR) = ulValue; + } + + // + // Set the timer B prescale match if requested. + // + if(ulTimer & TIMER_B) + { + HWREG(ulBase + TIMER_O_TBPMR) = ulValue; + } +} +#endif + +//***************************************************************************** +// +//! Get the timer prescale match value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer; must be one of \b TIMER_A or +//! \b TIMER_B. +//! +//! This function gets the value of the input clock prescaler match value. +//! When in a 16-bit mode that uses the counter match (edge count or PWM), the +//! prescale match effectively extends the range of the counter to 24-bits. +//! +//! \return The value of the timer prescale match. +// +//***************************************************************************** +#if defined(GROUP_prescalematchget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +TimerPrescaleMatchGet(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Return the appropriate prescale match value. + // + return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAPMR) : + HWREG(ulBase + TIMER_O_TBPMR)); +} +#endif + +//***************************************************************************** +// +//! Sets the timer load value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. Only \b TIMER_A should be used when the +//! timer is configured for 32-bit operation. +//! \param ulValue is the load value. +//! +//! This function sets the timer load value; if the timer is running then the +//! value will be immediately loaded into the timer. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_loadset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Set the timer A load value if requested. + // + if(ulTimer & TIMER_A) + { + HWREG(ulBase + TIMER_O_TAILR) = ulValue; + } + + // + // Set the timer B load value if requested. + // + if(ulTimer & TIMER_B) + { + HWREG(ulBase + TIMER_O_TBILR) = ulValue; + } +} +#endif + +//***************************************************************************** +// +//! Gets the timer load value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer; must be one of \b TIMER_A or +//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured +//! for 32-bit operation. +//! +//! This function gets the currently programmed interval load value for the +//! specified timer. +//! +//! \return Returns the load value for the timer. +// +//***************************************************************************** +#if defined(GROUP_loadget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +TimerLoadGet(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B)); + + // + // Return the appropriate load value. + // + return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAILR) : + HWREG(ulBase + TIMER_O_TBILR)); +} +#endif + +//***************************************************************************** +// +//! Gets the current timer value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer; must be one of \b TIMER_A or +//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured +//! for 32-bit operation. +//! +//! This function reads the current value of the specified timer. +//! +//! \return Returns the current value of the timer. +// +//***************************************************************************** +#if defined(GROUP_valueget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +TimerValueGet(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B)); + + // + // Return the appropriate timer value. + // + return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAR) : + HWREG(ulBase + TIMER_O_TBR)); +} +#endif + +//***************************************************************************** +// +//! Sets the timer match value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. Only \b TIMER_A should be used when the +//! timer is configured for 32-bit operation. +//! \param ulValue is the match value. +//! +//! This function sets the match value for a timer. This is used in capture +//! count mode to determine when to interrupt the processor and in PWM mode to +//! determine the duty cycle of the output signal. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_matchset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Set the timer A match value if requested. + // + if(ulTimer & TIMER_A) + { + HWREG(ulBase + TIMER_O_TAMATCHR) = ulValue; + } + + // + // Set the timer B match value if requested. + // + if(ulTimer & TIMER_B) + { + HWREG(ulBase + TIMER_O_TBMATCHR) = ulValue; + } +} +#endif + +//***************************************************************************** +// +//! Gets the timer match value. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer; must be one of \b TIMER_A or +//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured +//! for 32-bit operation. +//! +//! This function gets the match value for the specified timer. +//! +//! \return Returns the match value for the timer. +// +//***************************************************************************** +#if defined(GROUP_matchget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +TimerMatchGet(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B)); + + // + // Return the appropriate match value. + // + return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAMATCHR) : + HWREG(ulBase + TIMER_O_TBMATCHR)); +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for the timer interrupt. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s); must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! \param pfnHandler is a pointer to the function to be called when the timer +//! interrupt occurs. +//! +//! This sets the handler to be called when a timer interrupt occurs. This +//! will enable the global interrupt in the interrupt controller; specific +//! timer interrupts must be enabled via TimerIntEnable(). It is the interrupt +//! handler's responsibility to clear the interrupt source via TimerIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, + void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Get the interrupt number for this timer module. + // + ulBase = ((ulBase == TIMER0_BASE) ? INT_TIMER0A : + ((ulBase == TIMER1_BASE) ? INT_TIMER1A : INT_TIMER2A)); + + // + // Register an interrupt handler for timer A if requested. + // + if(ulTimer & TIMER_A) + { + // + // Register the interrupt handler. + // + IntRegister(ulBase, pfnHandler); + + // + // Enable the interrupt. + // + IntEnable(ulBase); + } + + // + // Register an interrupt handler for timer B if requested. + // + if(ulTimer & TIMER_B) + { + // + // Register the interrupt handler. + // + IntRegister(ulBase + 1, pfnHandler); + + // + // Enable the interrupt. + // + IntEnable(ulBase + 1); + } +} +#endif + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the timer interrupt. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulTimer specifies the timer(s); must be one of \b TIMER_A, +//! \b TIMER_B, or \b TIMER_BOTH. +//! +//! This function will clear the handler to be called when a timer interrupt +//! occurs. This will also mask off the interrupt in the interrupt controller +//! so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || + (ulTimer == TIMER_BOTH)); + + // + // Get the interrupt number for this timer module. + // + ulBase = ((ulBase == TIMER0_BASE) ? INT_TIMER0A : + ((ulBase == TIMER1_BASE) ? INT_TIMER1A : INT_TIMER2A)); + + // + // Unregister the interrupt handler for timer A if requested. + // + if(ulTimer & TIMER_A) + { + // + // Disable the interrupt. + // + IntDisable(ulBase); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulBase); + } + + // + // Unregister the interrupt handler for timer B if requested. + // + if(ulTimer & TIMER_B) + { + // + // Disable the interrupt. + // + IntDisable(ulBase + 1); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulBase + 1); + } +} +#endif + +//***************************************************************************** +// +//! Enables individual timer interrupt sources. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! Enables the indicated timer interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! The parameter \e ulIntFlags must be the logical OR of any combination of +//! the following: +//! +//! - TIMER_CAPB_EVENT - Capture B event interrupt +//! - TIMER_CAPB_MATCH - Capture B match interrupt +//! - TIMER_TIMB_TIMEOUT - Timer B timeout interrupt +//! - TIMER_RTC_MATCH - RTC interrupt mask +//! - TIMER_CAPA_EVENT - Capture A event interrupt +//! - TIMER_CAPA_MATCH - Capture A match interrupt +//! - TIMER_TIMA_TIMEOUT - Timer A timeout interrupt +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + + // + // Enable the specified interrupts. + // + HWREG(ulBase + TIMER_O_IMR) |= ulIntFlags; +} +#endif + +//***************************************************************************** +// +//! Disables individual timer interrupt sources. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. +//! +//! Disables the indicated timer interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! The parameter \e ulIntFlags has the same definition as the \e ulIntFlags +//! parameter to TimerIntEnable(). +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + + // + // Disable the specified interrupts. + // + HWREG(ulBase + TIMER_O_IMR) &= ~(ulIntFlags); +} +#endif + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ulBase is the base address of the timer module. +//! \param bMasked is false if the raw interrupt status is required and true if +//! the masked interrupt status is required. +//! +//! This returns the interrupt status for the timer module. Either the raw +//! interrupt status or the status of interrupts that are allowed to reflect to +//! the processor can be returned. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! values described in TimerIntEnable(). +// +//***************************************************************************** +#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +TimerIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + return(bMasked ? HWREG(ulBase + TIMER_O_MIS) : + HWREG(ulBase + TIMER_O_RIS)); +} +#endif + +//***************************************************************************** +// +//! Clears timer interrupt sources. +//! +//! \param ulBase is the base address of the timer module. +//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! The specified timer interrupt sources are cleared, so that they no longer +//! assert. This must be done in the interrupt handler to keep it from being +//! called again immediately upon exit. +//! +//! The parameter \e ulIntFlags has the same definition as the \e ulIntFlags +//! parameter to TimerIntEnable(). +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + + // + // Clear the requested interrupt sources. + // + HWREG(ulBase + TIMER_O_ICR) = ulIntFlags; +} +#endif + +//***************************************************************************** +// +//! Puts the timer into its reset state. +//! +//! \param ulBase is the base address of the timer module. +//! +//! The specified timer is disabled, and all its interrupts are disabled, +//! cleared, and unregistered. Then the timer registers are set to their reset +//! value. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_quiesce) || defined(BUILD_ALL) || defined(DOXYGEN) +void +TimerQuiesce(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || + (ulBase == TIMER2_BASE)); + + // + // Disable the timer. + // + HWREG(ulBase + TIMER_O_CTL) = TIMER_RV_CTL; + + // + // Disable all the timer interrupts. + // + HWREG(ulBase + TIMER_O_IMR) = TIMER_RV_IMR; + + // + // Clear all the timer interrupts. + // + HWREG(ulBase + TIMER_O_ICR) = 0xFFFFFFFF; + + // + // Unregister the interrupt handler. This also disables interrupts to the + // core. + // + TimerIntUnregister(ulBase, TIMER_BOTH); + + // + // Set all the registers to their reset value. + // + HWREG(ulBase + TIMER_O_CFG) = TIMER_RV_CFG; + HWREG(ulBase + TIMER_O_TAMR) = TIMER_RV_TAMR; + HWREG(ulBase + TIMER_O_TBMR) = TIMER_RV_TBMR; + HWREG(ulBase + TIMER_O_RIS) = TIMER_RV_RIS; + HWREG(ulBase + TIMER_O_MIS) = TIMER_RV_MIS; + HWREG(ulBase + TIMER_O_TAILR) = TIMER_RV_TAILR; + HWREG(ulBase + TIMER_O_TBILR) = TIMER_RV_TBILR; + HWREG(ulBase + TIMER_O_TAMATCHR) = TIMER_RV_TAMATCHR; + HWREG(ulBase + TIMER_O_TBMATCHR) = TIMER_RV_TBMATCHR; + HWREG(ulBase + TIMER_O_TAPR) = TIMER_RV_TAPR; + HWREG(ulBase + TIMER_O_TBPR) = TIMER_RV_TBPR; + HWREG(ulBase + TIMER_O_TAPMR) = TIMER_RV_TAPMR; + HWREG(ulBase + TIMER_O_TBPMR) = TIMER_RV_TBPMR; + HWREG(ulBase + TIMER_O_TAR) = TIMER_RV_TAR; + HWREG(ulBase + TIMER_O_TBR) = TIMER_RV_TBR; +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/timer.h b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/timer.h new file mode 100644 index 000000000..660c325f4 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/timer.h @@ -0,0 +1,137 @@ +//***************************************************************************** +// +// timer.h - Prototypes for the timer module +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __TIMER_H__ +#define __TIMER_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to TimerConfigure as the ulConfig parameter. +// +//***************************************************************************** +#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer +#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer +#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer +#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers +#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer +#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer +#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter +#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer +#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output +#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer +#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer +#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter +#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer +#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output + +//***************************************************************************** +// +// Values that can be passed to TimerIntEnable, TimerIntDisable, and +// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus. +// +//***************************************************************************** +#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt +#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt +#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt +#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask +#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt +#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt +#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt + +//***************************************************************************** +// +// Values that can be passed to TimerControlEvent as the ulEvent parameter. +// +//***************************************************************************** +#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges +#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges +#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges + +//***************************************************************************** +// +// Values that can be passed to most of the timer APIs as the ulTimer +// parameter. +// +//***************************************************************************** +#define TIMER_A 0x000000ff // Timer A +#define TIMER_B 0x0000ff00 // Timer B +#define TIMER_BOTH 0x0000ffff // Timer Both + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer); +extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer); +extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig); +extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, + tBoolean bInvert); +extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer, + tBoolean bEnable); +extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulEvent); +extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer, + tBoolean bStall); +extern void TimerRTCEnable(unsigned long ulBase); +extern void TimerRTCDisable(unsigned long ulBase); +extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerPrescaleGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer); +extern unsigned long TimerValueGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerMatchGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, + void (*pfnHandler)(void)); +extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer); +extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void TimerQuiesce(unsigned long ulBase); + +#ifdef __cplusplus +} +#endif + +#endif // __TIMER_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/uart.c b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/uart.c new file mode 100644 index 000000000..cbae1b0ca --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/uart.c @@ -0,0 +1,821 @@ +//***************************************************************************** +// +// uart.c - Driver for the UART. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup uart_api +//! @{ +// +//***************************************************************************** + +#include "../hw_ints.h" +#include "../hw_memmap.h" +#include "../hw_types.h" +#include "../hw_uart.h" +#include "debug.h" +#include "interrupt.h" +#include "sysctl.h" +#include "uart.h" + +//***************************************************************************** +// +//! Sets the type of parity. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulParity specifies the type of parity to use. +//! +//! Sets the type of parity to use for transmitting and expect when receiving. +//! The \e ulParity parameter must be one of \b UART_CONFIG_PAR_NONE, +//! \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE, +//! or \b UART_CONFIG_PAR_ZERO. The last two allow direct control of the +//! parity bit; it will always be either be one or zero based on the mode. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_paritymodeset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +UARTParityModeSet(unsigned long ulBase, unsigned long ulParity) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + ASSERT((ulParity == UART_CONFIG_PAR_NONE) || + (ulParity == UART_CONFIG_PAR_EVEN) || + (ulParity == UART_CONFIG_PAR_ODD) || + (ulParity == UART_CONFIG_PAR_ONE) || + (ulParity == UART_CONFIG_PAR_ZERO)); + + // + // Set the parity mode. + // + HWREG(ulBase + UART_O_LCR_H) = ((HWREG(ulBase + UART_O_LCR_H) & + ~(UART_LCR_H_SPS | UART_LCR_H_EPS | + UART_LCR_H_PEN)) | ulParity); +} +#endif + +//***************************************************************************** +// +//! Gets the type of parity currently being used. +//! +//! \param ulBase is the base address of the UART port. +//! +//! \return The current parity settings, specified as one of +//! \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, +//! \b UART_CONFIG_PAR_ONE, or \b UART_CONFIG_PAR_ZERO. +// +//***************************************************************************** +#if defined(GROUP_paritymodeget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +UARTParityModeGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Return the current parity setting. + // + return(HWREG(ulBase + UART_O_LCR_H) & + (UART_LCR_H_SPS | UART_LCR_H_EPS | UART_LCR_H_PEN)); +} +#endif + +//***************************************************************************** +// +//! Sets the configuration of a UART. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulBaud is the desired baud rate. +//! \param ulConfig is the data format for the port (number of data bits, +//! number of stop bits, and parity). +//! +//! This function will configure the UART for operation in the specified data +//! format. The baud rate is provided in the \e ulBaud parameter and the +//! data format in the \e ulConfig parameter. +//! +//! The \e ulConfig parameter is the logical OR of three values: the number of +//! data bits, the number of stop bits, and the parity. \b UART_CONFIG_WLEN_8, +//! \b UART_CONFIG_WLEN_7, \b UART_CONFIG_WLEN_6, and \b UART_CONFIG_WLEN_5 +//! select from eight to five data bits per byte (respectively). +//! \b UART_CONFIG_STOP_ONE and \b UART_CONFIG_STOP_TWO select one or two stop +//! bits (respectively). \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, +//! \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE, and \b UART_CONFIG_PAR_ZERO +//! select the parity mode (no parity bit, even parity bit, odd parity bit, +//! parity bit always one, and parity bit always zero, respectively). +//! +//! The baud rate is dependent upon the system clock rate returned by +//! SysCtlClockGet(); if it does not return the correct system clock rate then +//! the baud rate will be incorrect. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_configset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +UARTConfigSet(unsigned long ulBase, unsigned long ulBaud, + unsigned long ulConfig) +{ + unsigned long ulUARTClk, ulInt, ulFrac; + + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Stop the UART. + // + UARTDisable(ulBase); + + // + // Determine the UART clock rate. + // + ulUARTClk = SysCtlClockGet(); + + // + // Compute the fractional baud rate divider. + // + ulInt = ulUARTClk / (16 * ulBaud); + ulFrac = ulUARTClk % (16 * ulBaud); + ulFrac = ((((2 * ulFrac * 4) / ulBaud) + 1) / 2); + + // + // Set the baud rate. + // + HWREG(ulBase + UART_O_IBRD) = ulInt; + HWREG(ulBase + UART_O_FBRD) = ulFrac; + + // + // Set parity, data length, and number of stop bits. + // + HWREG(ulBase + UART_O_LCR_H) = ulConfig; + + // + // Clear the flags register. + // + HWREG(ulBase + UART_O_FR) = 0; + + // + // Start the UART. + // + UARTEnable(ulBase); +} +#endif + +//***************************************************************************** +// +//! Gets the current configuration of a UART. +//! +//! \param ulBase is the base address of the UART port. +//! \param pulBaud is a pointer to storage for the baud rate. +//! \param pulConfig is a pointer to storage for the data format. +//! +//! The baud rate and data format for the UART is determined. The returned +//! baud rate is the actual baud rate; it may not be the exact baud rate +//! requested or an ``official'' baud rate. The data format returned in +//! \e pulConfig is enumerated the same as the \e ulConfig parameter of +//! UARTConfigSet(). +//! +//! The baud rate is dependent upon the system clock rate returned by +//! SysCtlClockGet(); if it does not return the correct system clock rate then +//! the baud rate will be computed incorrectly. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_configget) || defined(BUILD_ALL) || defined(DOXYGEN) +void +UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud, + unsigned long *pulConfig) + +{ + unsigned long ulInt, ulFrac; + + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Compute the baud rate. + // + ulInt = HWREG(ulBase + UART_O_IBRD); + ulFrac = HWREG(ulBase + UART_O_FBRD); + *pulBaud = (SysCtlClockGet() * 4) / ((64 * ulInt) + ulFrac); + + // + // Get the parity, data length, and number of stop bits. + // + *pulConfig = (HWREG(ulBase + UART_O_LCR_H) & + (UART_LCR_H_SPS | UART_LCR_H_WLEN | UART_LCR_H_STP2 | + UART_LCR_H_EPS | UART_LCR_H_PEN)); +} +#endif + +//***************************************************************************** +// +//! Enables transmitting and receiving. +//! +//! \param ulBase is the base address of the UART port. +//! +//! Sets the UARTEN, TXE, and RXE bits, and enables the transmit and receive +//! FIFOs. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +UARTEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Enable the FIFO. + // + HWREG(ulBase + UART_O_LCR_H) |= UART_LCR_H_FEN; + + // + // Enable RX, TX, and the UART. + // + HWREG(ulBase + UART_O_CTL) |= (UART_CTL_UARTEN | UART_CTL_TXE | + UART_CTL_RXE); +} +#endif + +//***************************************************************************** +// +//! Disables transmitting and receiving. +//! +//! \param ulBase is the base address of the UART port. +//! +//! Clears the UARTEN, TXE, and RXE bits, then waits for the end of +//! transmission of the current character, and flushes the transmit FIFO. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +UARTDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Wait for end of TX. + // + while(HWREG(ulBase + UART_O_FR) & UART_FR_BUSY) + { + } + + // + // Disable the FIFO. + // + HWREG(ulBase + UART_O_LCR_H) &= ~(UART_LCR_H_FEN); + + // + // Disable the UART. + // + HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_UARTEN | UART_CTL_TXE | + UART_CTL_RXE); +} +#endif + +//***************************************************************************** +// +//! Determines if there are any characters in the receive FIFO. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function returns a flag indicating whether or not there is data +//! available in the receive FIFO. +//! +//! \return Returns \b true if there is data in the receive FIFO, and \b false +//! if there is no data in the receive FIFO. +// +//***************************************************************************** +#if defined(GROUP_charsavail) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +UARTCharsAvail(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Return the availability of characters. + // + return((HWREG(ulBase + UART_O_FR) & UART_FR_RXFE) ? false : true); +} +#endif + +//***************************************************************************** +// +//! Determines if there is any space in the transmit FIFO. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function returns a flag indicating whether or not there is space +//! available in the transmit FIFO. +//! +//! \return Returns \b true if there is space available in the transmit FIFO, +//! and \b false if there is no space available in the transmit FIFO. +// +//***************************************************************************** +#if defined(GROUP_spaceavail) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +UARTSpaceAvail(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Return the availability of space. + // + return((HWREG(ulBase + UART_O_FR) & UART_FR_TXFF) ? false : true); +} +#endif + +//***************************************************************************** +// +//! Receives a character from the specified port. +//! +//! \param ulBase is the base address of the UART port. +//! +//! Gets a character from the receive FIFO for the specified port. +//! +//! \return Returns the character read from the specified port, cast as a +//! \e long. A \b -1 will be returned if there are no characters present in +//! the receive FIFO. The UARTCharsAvail() function should be called before +//! attempting to call this function. +// +//***************************************************************************** +#if defined(GROUP_charnonblockingget) || defined(BUILD_ALL) || defined(DOXYGEN) +long +UARTCharNonBlockingGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // See if there are any characters in the receive FIFO. + // + if(!(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE)) + { + // + // Read and return the next character. + // + return(HWREG(ulBase + UART_O_DR)); + } + else + { + // + // There are no characters, so return a failure. + // + return(-1); + } +} +#endif + +//***************************************************************************** +// +//! Waits for a character from the specified port. +//! +//! \param ulBase is the base address of the UART port. +//! +//! Gets a character from the receive FIFO for the specified port. If there +//! are no characters available, this function will wait until a character is +//! received before returning. +//! +//! \return Returns the character read from the specified port, cast as an +//! \e int. +// +//***************************************************************************** +#if defined(GROUP_charget) || defined(BUILD_ALL) || defined(DOXYGEN) +long +UARTCharGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Wait until a char is available. + // + while(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE) + { + } + + // + // Now get the char. + // + return(HWREG(ulBase + UART_O_DR)); +} +#endif + +//***************************************************************************** +// +//! Sends a character to the specified port. +//! +//! \param ulBase is the base address of the UART port. +//! \param ucData is the character to be transmitted. +//! +//! Writes the character \e ucData to the transmit FIFO for the specified port. +//! This function does not block, so if there is no space available, then a +//! \b false is returned, and the application will have to retry the function +//! later. +//! +//! \return Returns \b true if the character was successfully placed in the +//! transmit FIFO, and \b false if there was no space available in the transmit +//! FIFO. +// +//***************************************************************************** +#if defined(GROUP_charnonblockingput) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +UARTCharNonBlockingPut(unsigned long ulBase, unsigned char ucData) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // See if there is space in the transmit FIFO. + // + if(!(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF)) + { + // + // Write this character to the transmit FIFO. + // + HWREG(ulBase + UART_O_DR) = ucData; + + // + // Success. + // + return(true); + } + else + { + // + // There is no space in the transmit FIFO, so return a failure. + // + return(false); + } +} +#endif + +//***************************************************************************** +// +//! Waits to send a character from the specified port. +//! +//! \param ulBase is the base address of the UART port. +//! \param ucData is the character to be transmitted. +//! +//! Sends the character \e ucData to the transmit FIFO for the specified port. +//! If there is no space available in the transmit FIFO, this function will +//! wait until there is space available before returning. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_charput) || defined(BUILD_ALL) || defined(DOXYGEN) +void +UARTCharPut(unsigned long ulBase, unsigned char ucData) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Wait until space is available. + // + while(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF) + { + } + + // + // Send the char. + // + HWREG(ulBase + UART_O_DR) = ucData; +} +#endif + +//***************************************************************************** +// +//! Causes a BREAK to be sent. +//! +//! \param ulBase is the base address of the UART port. +//! \param bBreakState controls the output level. +//! +//! Calling this function with \e bBreakState set to \b true will assert a +//! break condition on the UART. Calling this function with \e bBreakState set +//! to \b false will remove the break condition. For proper transmission of a +//! break command, the break must be asserted for at least two complete frames. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_breakctl) || defined(BUILD_ALL) || defined(DOXYGEN) +void +UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Set the break condition as requested. + // + HWREG(ulBase + UART_O_LCR_H) = + (bBreakState ? + (HWREG(ulBase + UART_O_LCR_H) | UART_LCR_H_BRK) : + (HWREG(ulBase + UART_O_LCR_H) & ~(UART_LCR_H_BRK))); +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for a UART interrupt. +//! +//! \param ulBase is the base address of the UART port. +//! \param pfnHandler is a pointer to the function to be called when the +//! UART interrupt occurs. +//! +//! This function does the actual registering of the interrupt handler. This +//! will enable the global interrupt in the interrupt controller; specific UART +//! interrupts must be enabled via UARTIntEnable(). It is the interrupt +//! handler's responsibility to clear the interrupt source. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +UARTIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Determine the interrupt number based on the UART port. + // + ulInt = (ulBase == UART0_BASE) ? INT_UART0 : INT_UART1; + + // + // Register the interrupt handler. + // + IntRegister(ulInt, pfnHandler); + + // + // Enable the UART interrupt. + // + IntEnable(ulInt); +} +#endif + +//***************************************************************************** +// +//! Unregisters an interrupt handler for a UART interrupt. +//! +//! \param ulBase is the base address of the UART port. +//! +//! This function does the actual unregistering of the interrupt handler. It +//! will clear the handler to be called when a UART interrupt occurs. This +//! will also mask off the interrupt in the interrupt controller so that the +//! interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +UARTIntUnregister(unsigned long ulBase) +{ + unsigned long ulInt; + + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Determine the interrupt number based on the UART port. + // + ulInt = (ulBase == UART0_BASE) ? INT_UART0 : INT_UART1; + + // + // Disable the interrupt. + // + IntDisable(ulInt); + + // + // Unregister the interrupt handler. + // + IntUnregister(ulInt); +} +#endif + +//***************************************************************************** +// +//! Enables individual UART interrupt sources. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. +//! +//! Enables the indicated UART interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! The parameter \e ulIntFlags is the logical OR of any of the following: +//! +//! - UART_INT_OE - Overrun Error interrupt +//! - UART_INT_BE - Break Error interrupt +//! - UART_INT_PE - Parity Error interrupt +//! - UART_INT_FE - Framing Error interrupt +//! - UART_INT_RT - Receive Timeout interrupt +//! - UART_INT_TX - Transmit interrupt +//! - UART_INT_RX - Receive interrupt +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Enable the specified interrupts. + // + HWREG(ulBase + UART_O_IM) |= ulIntFlags; +} +#endif + +//***************************************************************************** +// +//! Disables individual UART interrupt sources. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. +//! +//! Disables the indicated UART interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! The parameter \e ulIntFlags has the same definition as the same parameter +//! to UARTIntEnable(). +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Disable the specified interrupts. + // + HWREG(ulBase + UART_O_IM) &= ~(ulIntFlags); +} +#endif + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param ulBase is the base address of the UART port. +//! \param bMasked is false if the raw interrupt status is required and true +//! if the masked interrupt status is required. +//! +//! This returns the interrupt status for the specified UART. Either the raw +//! interrupt status or the status of interrupts that are allowed to reflect to +//! the processor can be returned. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! values described in UARTIntEnable(). +// +//***************************************************************************** +#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +UARTIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ulBase + UART_O_MIS)); + } + else + { + return(HWREG(ulBase + UART_O_RIS)); + } +} +#endif + +//***************************************************************************** +// +//! Clears UART interrupt sources. +//! +//! \param ulBase is the base address of the UART port. +//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. +//! +//! The specified UART interrupt sources are cleared, so that they no longer +//! assert. This must be done in the interrupt handler to keep it from being +//! called again immediately upon exit. +//! +//! The parameter \e ulIntFlags has the same definition as the same parameter +//! to UARTIntEnable(). +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags) +{ + // + // Check the arguments. + // + ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); + + // + // Clear the requested interrupt sources. + // + HWREG(ulBase + UART_O_ICR) = ulIntFlags; +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/uart.h b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/uart.h new file mode 100644 index 000000000..ee8930861 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/uart.h @@ -0,0 +1,104 @@ +//***************************************************************************** +// +// uart.h - Defines and Macros for the UART. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __UART_H__ +#define __UART_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear +// as the ulIntFlags parameter, and returned from UARTIntStatus. +// +//***************************************************************************** +#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask +#define UART_INT_BE 0x200 // Break Error Interrupt Mask +#define UART_INT_PE 0x100 // Parity Error Interrupt Mask +#define UART_INT_FE 0x080 // Framing Error Interrupt Mask +#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask +#define UART_INT_TX 0x020 // Transmit Interrupt Mask +#define UART_INT_RX 0x010 // Receive Interrupt Mask + +//***************************************************************************** +// +// Values that can be passed to UARTConfigSet as the ulConfig parameter and +// returned by UARTConfigGet in the pulConfig parameter. Additionally, the +// UART_CONFIG_PAR_* subset can be passed to UARTParityModeSet as the ulParity +// parameter, and are returned by UARTParityModeGet. +// +//***************************************************************************** +#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data +#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data +#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data +#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data +#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit +#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits +#define UART_CONFIG_PAR_NONE 0x00000000 // No parity +#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity +#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity +#define UART_CONFIG_PAR_ONE 0x00000086 // Parity bit is one +#define UART_CONFIG_PAR_ZERO 0x00000082 // Parity bit is zero + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity); +extern unsigned long UARTParityModeGet(unsigned long ulBase); +extern void UARTConfigSet(unsigned long ulBase, unsigned long ulBaud, + unsigned long ulConfig); +extern void UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud, + unsigned long *pulConfig); +extern void UARTEnable(unsigned long ulBase); +extern void UARTDisable(unsigned long ulBase); +extern tBoolean UARTCharsAvail(unsigned long ulBase); +extern tBoolean UARTSpaceAvail(unsigned long ulBase); +extern long UARTCharNonBlockingGet(unsigned long ulBase); +extern long UARTCharGet(unsigned long ulBase); +extern tBoolean UARTCharNonBlockingPut(unsigned long ulBase, + unsigned char ucData); +extern void UARTCharPut(unsigned long ulBase, unsigned char ucData); +extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState); +extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern void UARTIntUnregister(unsigned long ulBase); +extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk, + unsigned long ulBaud, unsigned long ulConfig); + +#ifdef __cplusplus +} +#endif + +#endif // __UART_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/watchdog.c b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/watchdog.c new file mode 100644 index 000000000..53332d051 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/watchdog.c @@ -0,0 +1,592 @@ +//***************************************************************************** +// +// watchdog.c - Driver for the Watchdog Timer Module. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup watchdog_api +//! @{ +// +//***************************************************************************** + +#include "../hw_ints.h" +#include "../hw_memmap.h" +#include "../hw_types.h" +#include "../hw_watchdog.h" +#include "debug.h" +#include "interrupt.h" +#include "watchdog.h" + +//***************************************************************************** +// +//! Determines if the watchdog timer is enabled. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This will check to see if the watchdog timer is enabled. +//! +//! \return Returns \b true if the watchdog timer is enabled, and \b false +//! if it is not. +// +//***************************************************************************** +#if defined(GROUP_running) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +WatchdogRunning(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // See if the watchdog timer module is enabled, and return. + // + return(HWREG(ulBase + WDT_O_CTL) & WDT_CTL_INTEN); +} +#endif + +//***************************************************************************** +// +//! Enables the watchdog timer. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This will enable the watchdog timer counter and interrupt. +//! +//! \note This function will have no effect if the watchdog timer has +//! been locked. +//! +//! \sa WatchdogLock(), WatchdogUnlock() +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +WatchdogEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Enable the watchdog timer module. + // + HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_INTEN; +} +#endif + +//***************************************************************************** +// +//! Enables the watchdog timer reset. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! Enables the capability of the watchdog timer to issue a reset to the +//! processor upon a second timeout condition. +//! +//! \note This function will have no effect if the watchdog timer has +//! been locked. +//! +//! \sa WatchdogLock(), WatchdogUnlock() +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_resetenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +WatchdogResetEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Enable the watchdog reset. + // + HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_RESEN; +} +#endif + +//***************************************************************************** +// +//! Disables the watchdog timer reset. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! Disables the capability of the watchdog timer to issue a reset to the +//! processor upon a second timeout condition. +//! +//! \note This function will have no effect if the watchdog timer has +//! been locked. +//! +//! \sa WatchdogLock(), WatchdogUnlock() +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_resetdisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +WatchdogResetDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Disable the watchdog reset. + // + HWREG(ulBase + WDT_O_CTL) &= ~(WDT_CTL_RESEN); +} +#endif + +//***************************************************************************** +// +//! Enables the watchdog timer lock mechanism. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! Locks out write access to the watchdog timer configuration registers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_lock) || defined(BUILD_ALL) || defined(DOXYGEN) +void +WatchdogLock(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Lock out watchdog register writes. Writing anything to the WDT_O_LOCK + // register causes the lock to go into effect. + // + HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_LOCKED; +} +#endif + +//***************************************************************************** +// +//! Disables the watchdog timer lock mechanism. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! Enables write access to the watchdog timer configuration registers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_unlock) || defined(BUILD_ALL) || defined(DOXYGEN) +void +WatchdogUnlock(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Unlock watchdog register writes. + // + HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_UNLOCK; +} +#endif + +//***************************************************************************** +// +//! Gets the state of the watchdog timer lock mechanism. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! Returns the lock state of the watchdog timer registers. +//! +//! \return Returns \b true if the watchdog timer registers are locked, and +//! \b false if they are not locked. +// +//***************************************************************************** +#if defined(GROUP_lockstate) || defined(BUILD_ALL) || defined(DOXYGEN) +tBoolean +WatchdogLockState(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Get the lock state. + // + return((HWREG(ulBase + WDT_O_LOCK) == WDT_LOCK_LOCKED) ? true : false); +} +#endif + +//***************************************************************************** +// +//! Sets the watchdog timer reload value. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! \param ulLoadVal is the load value for the watchdog timer. +//! +//! This function sets the value to load into the watchdog timer when the count +//! reaches zero for the first time; if the watchdog timer is running when this +//! function is called, then the value will be immediately loaded into the +//! watchdog timer counter. If the parameter \e ulLoadVal is 0, then an +//! interrupt is immediately generated. +//! +//! \note This function will have no effect if the watchdog timer has +//! been locked. +//! +//! \sa WatchdogLock(), WatchdogUnlock(), WatchdogReloadGet() +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_reloadset) || defined(BUILD_ALL) || defined(DOXYGEN) +void +WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Set the load register. + // + HWREG(ulBase + WDT_O_LOAD) = ulLoadVal; +} +#endif + +//***************************************************************************** +// +//! Gets the watchdog timer reload value. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This function gets the value that is loaded into the watchdog timer when +//! the count reaches zero for the first time. +//! +//! \sa WatchdogReloadSet() +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_reloadget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +WatchdogReloadGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Get the load register. + // + return(HWREG(ulBase + WDT_O_LOAD)); +} +#endif + +//***************************************************************************** +// +//! Gets the current watchdog timer value. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This function reads the current value of the watchdog timer. +//! +//! \return Returns the current value of the watchdog timer. +// +//***************************************************************************** +#if defined(GROUP_valueget) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +WatchdogValueGet(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Get the current watchdog timer register value. + // + return(HWREG(ulBase + WDT_O_VALUE)); +} +#endif + +//***************************************************************************** +// +//! Registers an interrupt handler for watchdog timer interrupt. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! \param pfnHandler is a pointer to the function to be called when the +//! watchdog timer interrupt occurs. +//! +//! This function does the actual registering of the interrupt handler. This +//! will enable the global interrupt in the interrupt controller; the watchdog +//! timer interrupt must be enabled via WatchdogEnable(). It is the interrupt +//! handler's responsibility to clear the interrupt source via +//! WatchdogIntClear(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +WatchdogIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Register the interrupt handler. + // + IntRegister(INT_WATCHDOG, pfnHandler); + + // + // Enable the watchdog timer interrupt. + // + IntEnable(INT_WATCHDOG); +} +#endif + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the watchdog timer interrupt. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This function does the actual unregistering of the interrupt handler. This +//! function will clear the handler to be called when a watchdog timer +//! interrupt occurs. This will also mask off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) +void +WatchdogIntUnregister(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Disable the interrupt. + // + IntDisable(INT_WATCHDOG); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_WATCHDOG); +} +#endif + +//***************************************************************************** +// +//! Enables the watchdog timer interrupt. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! Enables the watchdog timer interrupt. +//! +//! \note This function will have no effect if the watchdog timer has +//! been locked. +//! +//! \sa WatchdogLock(), WatchdogUnlock(), WatchdogEnable() +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +WatchdogIntEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Enable the watchdog interrupt. + // + HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_INTEN; +} +#endif + +//***************************************************************************** +// +//! Gets the current watchdog timer interrupt status. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! \param bMasked is \b false if the raw interrupt status is required and +//! \b true if the masked interrupt status is required. +//! +//! This returns the interrupt status for the watchdog timer module. Either +//! the raw interrupt status or the status of interrupt that is allowed to +//! reflect to the processor can be returned. +//! +//! \return The current interrupt status, where a 1 indicates that the watchdog +//! interrupt is active, and a 0 indicates that it is not active. +// +//***************************************************************************** +#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) +unsigned long +WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Return either the interrupt status or the raw interrupt status as + // requested. + // + if(bMasked) + { + return(HWREG(ulBase + WDT_O_MIS)); + } + else + { + return(HWREG(ulBase + WDT_O_RIS)); + } +} +#endif + +//***************************************************************************** +// +//! Clears the watchdog timer interrupt. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! The watchdog timer interrupt source is cleared, so that it no longer +//! asserts. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) +void +WatchdogIntClear(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Clear the interrupt source. + // + HWREG(ulBase + WDT_O_ICR) = WDT_INT_TIMEOUT; +} +#endif + +//***************************************************************************** +// +//! Enables stalling of the watchdog timer during debug events. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This function allows the watchdog timer to stop counting when the processor +//! is stopped by the debugger. By doing so, the watchdog is prevented from +//! expiring (typically almost immediately from a human time perspective) and +//! resetting the system (if reset is enabled). The watchdog will instead +//! expired after the appropriate number of processor cycles have been executed +//! while debugging (or at the appropriate time after the processor has been +//! restarted). +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_stallenable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +WatchdogStallEnable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Enable timer stalling. + // + HWREG(ulBase + WDT_O_TEST) |= WDT_TEST_STALL; +} +#endif + +//***************************************************************************** +// +//! Disables stalling of the watchdog timer during debug events. +//! +//! \param ulBase is the base address of the watchdog timer module. +//! +//! This function disables the debug mode stall of the watchdog timer. By +//! doing so, the watchdog timer continues to count regardless of the processor +//! debug state. +//! +//! \return None. +// +//***************************************************************************** +#if defined(GROUP_stalldisable) || defined(BUILD_ALL) || defined(DOXYGEN) +void +WatchdogStallDisable(unsigned long ulBase) +{ + // + // Check the arguments. + // + ASSERT(ulBase == WATCHDOG_BASE); + + // + // Disable timer stalling. + // + HWREG(ulBase + WDT_O_TEST) &= ~(WDT_TEST_STALL); +} +#endif + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/watchdog.h b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/watchdog.h new file mode 100644 index 000000000..9378504a0 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/LuminaryCode/watchdog.h @@ -0,0 +1,63 @@ +//***************************************************************************** +// +// watchdog.h - Prototypes for the Watchdog Timer API +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __WATCHDOG_H__ +#define __WATCHDOG_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern tBoolean WatchdogRunning(unsigned long ulBase); +extern void WatchdogEnable(unsigned long ulBase); +extern void WatchdogResetEnable(unsigned long ulBase); +extern void WatchdogResetDisable(unsigned long ulBase); +extern void WatchdogLock(unsigned long ulBase); +extern void WatchdogUnlock(unsigned long ulBase); +extern tBoolean WatchdogLockState(unsigned long ulBase); +extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal); +extern unsigned long WatchdogReloadGet(unsigned long ulBase); +extern unsigned long WatchdogValueGet(unsigned long ulBase); +extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern void WatchdogIntUnregister(unsigned long ulBase); +extern void WatchdogIntEnable(unsigned long ulBase); +extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void WatchdogIntClear(unsigned long ulBase); +extern void WatchdogStallDisable(unsigned long ulBase); +extern void WatchdogStallDisable(unsigned long ulBase); + +#ifdef __cplusplus +} +#endif + +#endif // __WATCHDOG_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/RTOSDemo.ewd b/20080212/Demo/CORTEX_LM3S811_IAR/RTOSDemo.ewd new file mode 100644 index 000000000..cfdaf6ecc --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/RTOSDemo.ewd @@ -0,0 +1,616 @@ + + + + 1 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 15 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IARROM_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + JLINK_ID + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 1 + 1 + 1 + + + + + + + + MACRAIGOR_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin + 0 + + + + + + diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/RTOSDemo.ewp b/20080212/Demo/CORTEX_LM3S811_IAR/RTOSDemo.ewp new file mode 100644 index 000000000..b6d9faa4a --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/RTOSDemo.ewp @@ -0,0 +1,819 @@ + + + + 1 + + Debug + + ARM + + 1 + + General + 3 + + 14 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 19 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 7 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 5 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Demo Source + + $PROJ_DIR$\..\Common\Minimal\BlockQ.c + + + $PROJ_DIR$\..\Common\Minimal\integer.c + + + $PROJ_DIR$\main.c + + + $PROJ_DIR$\LuminaryCode\osram96x16.c + + + $PROJ_DIR$\..\Common\Minimal\PollQ.c + + + $PROJ_DIR$\..\Common\Minimal\semtest.c + + + $PROJ_DIR$\startup.c + + + + Scheduler Source + + $PROJ_DIR$\..\..\Source\portable\MemMang\heap_1.c + + + $PROJ_DIR$\..\..\Source\list.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s + + + $PROJ_DIR$\..\..\Source\queue.c + + + $PROJ_DIR$\..\..\Source\tasks.c + + + + + diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/RTOSDemo.eww b/20080212/Demo/CORTEX_LM3S811_IAR/RTOSDemo.eww new file mode 100644 index 000000000..b7687f61f --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/RTOSDemo.eww @@ -0,0 +1,54 @@ + + + + + $WS_DIR$\RTOSDemo.ewp + + + + All Examples + + driverlib + Debug + + + bitband + Debug + + + gpio_jtag + Debug + + + hello + Debug + + + interrupts + Debug + + + pwmgen + Debug + + + qs_ev-lm3s811 + Debug + + + timers + Debug + + + uart_echo + Debug + + + watchdog + Debug + + + + + + diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/main.c b/20080212/Demo/CORTEX_LM3S811_IAR/main.c new file mode 100644 index 000000000..5b890c4e3 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/main.c @@ -0,0 +1,374 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +/* + * This project contains an application demonstrating the use of the + * FreeRTOS.org mini real time scheduler on the Luminary Micro LM3S811 Eval + * board. See http://www.FreeRTOS.org for more information. + * + * main() simply sets up the hardware, creates all the demo application tasks, + * then starts the scheduler. http://www.freertos.org/a00102.html provides + * more information on the standard demo tasks. + * + * In addition to a subset of the standard demo application tasks, main.c also + * defines the following tasks: + * + * + A 'Print' task. The print task is the only task permitted to access the + * LCD - thus ensuring mutual exclusion and consistent access to the resource. + * Other tasks do not access the LCD directly, but instead send the text they + * wish to display to the print task. The print task spends most of its time + * blocked - only waking when a message is queued for display. + * + * + A 'Button handler' task. The eval board contains a user push button that + * is configured to generate interrupts. The interrupt handler uses a + * semaphore to wake the button handler task - demonstrating how the priority + * mechanism can be used to defer interrupt processing to the task level. The + * button handler task sends a message both to the LCD (via the print task) and + * the UART where it can be viewed using a dumb terminal (via the UART to USB + * converter on the eval board). NOTES: The dumb terminal must be closed in + * order to reflash the microcontroller. A very basic interrupt driven UART + * driver is used that does not use the FIFO. 19200 baud is used. + * + * + A 'check' task. The check task only executes every five seconds but has a + * high priority so is guaranteed to get processor time. Its function is to + * check that all the other tasks are still operational and that no errors have + * been detected at any time. If no errors have every been detected 'PASS' is + * written to the display (via the print task) - if an error has ever been + * detected the message is changed to 'FAIL'. The position of the message is + * changed for each write. + */ + + + +/* Environment includes. */ +#include "DriverLib.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "semphr.h" + +/* Demo app includes. */ +#include "integer.h" +#include "PollQ.h" +#include "semtest.h" +#include "BlockQ.h" + +/* Delay between cycles of the 'check' task. */ +#define mainCHECK_DELAY ( ( portTickType ) 5000 / portTICK_RATE_MS ) + +/* UART configuration - note this does not use the FIFO so is not very +efficient. */ +#define mainBAUD_RATE ( 19200 ) +#define mainFIFO_SET ( 0x10 ) + +/* Demo task priorities. */ +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) + +/* Demo board specifics. */ +#define mainPUSH_BUTTON GPIO_PIN_4 + +/* Misc. */ +#define mainQUEUE_SIZE ( 3 ) +#define mainDEBOUNCE_DELAY ( ( portTickType ) 150 / portTICK_RATE_MS ) +#define mainNO_DELAY ( ( portTickType ) 0 ) +/* + * Configure the processor and peripherals for this demo. + */ +static void prvSetupHardware( void ); + +/* + * The 'check' task, as described at the top of this file. + */ +static void vCheckTask( void *pvParameters ); + +/* + * The task that is woken by the ISR that processes GPIO interrupts originating + * from the push button. + */ +static void vButtonHandlerTask( void *pvParameters ); + +/* + * The task that controls access to the LCD. + */ +static void vPrintTask( void *pvParameter ); + +/* String that is transmitted on the UART. */ +static portCHAR *cMessage = "Task woken by button interrupt! --- "; +static volatile portCHAR *pcNextChar; + +/* The semaphore used to wake the button handler task from within the GPIO +interrupt handler. */ +xSemaphoreHandle xButtonSemaphore; + +/* The queue used to send strings to the print task for display on the LCD. */ +xQueueHandle xPrintQueue; + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + /* Configure the clocks, UART and GPIO. */ + prvSetupHardware(); + + /* Create the semaphore used to wake the button handler task from the GPIO + ISR. */ + vSemaphoreCreateBinary( xButtonSemaphore ); + xSemaphoreTake( xButtonSemaphore, 0 ); + + /* Create the queue used to pass message to vPrintTask. */ + xPrintQueue = xQueueCreate( mainQUEUE_SIZE, sizeof( portCHAR * ) ); + + /* Start the standard demo tasks. */ + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + + /* Start the tasks defined within the file. */ + xTaskCreate( vCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + xTaskCreate( vButtonHandlerTask, "Status", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY + 1, NULL ); + xTaskCreate( vPrintTask, "Print", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY - 1, NULL ); + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* Will only get here if there was insufficient heap to start the + scheduler. */ + + return 0; +} +/*-----------------------------------------------------------*/ + +static void vCheckTask( void *pvParameters ) +{ +portBASE_TYPE xErrorOccurred = pdFALSE; +portTickType xLastExecutionTime; +const portCHAR *pcPassMessage = "PASS"; +const portCHAR *pcFailMessage = "FAIL"; + + /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() + works correctly. */ + xLastExecutionTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Perform this check every mainCHECK_DELAY milliseconds. */ + vTaskDelayUntil( &xLastExecutionTime, mainCHECK_DELAY ); + + /* Has an error been found in any task? */ + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + /* Send either a pass or fail message. If an error is found it is + never cleared again. We do not write directly to the LCD, but instead + queue a message for display by the print task. */ + if( xErrorOccurred == pdTRUE ) + { + xQueueSend( xPrintQueue, &pcFailMessage, portMAX_DELAY ); + } + else + { + xQueueSend( xPrintQueue, &pcPassMessage, portMAX_DELAY ); + } + } +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Setup the PLL. */ + SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); + + /* Setup the push button. */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC); + GPIODirModeSet(GPIO_PORTC_BASE, mainPUSH_BUTTON, GPIO_DIR_MODE_IN); + GPIOIntTypeSet( GPIO_PORTC_BASE, mainPUSH_BUTTON,GPIO_FALLING_EDGE ); + IntPrioritySet( INT_GPIOC, configKERNEL_INTERRUPT_PRIORITY ); + GPIOPinIntEnable( GPIO_PORTC_BASE, mainPUSH_BUTTON ); + IntEnable( INT_GPIOC ); + + + + /* Enable the UART. */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + + /* Set GPIO A0 and A1 as peripheral function. They are used to output the + UART signals. */ + GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); + + /* Configure the UART for 8-N-1 operation. */ + UARTConfigSetExpClk( UART0_BASE, SysCtlClockGet(), mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); + + /* We don't want to use the fifo. This is for test purposes to generate + as many interrupts as possible. */ + HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET; + + /* Enable Tx interrupts. */ + HWREG( UART0_BASE + UART_O_IM ) |= UART_INT_TX; + IntPrioritySet( INT_UART0, configKERNEL_INTERRUPT_PRIORITY ); + IntEnable( INT_UART0 ); + + + /* Initialise the LCD> */ + OSRAMInit( false ); + OSRAMStringDraw("www.FreeRTOS.org", 0, 0); + OSRAMStringDraw("LM3S811 demo", 16, 1); +} +/*-----------------------------------------------------------*/ + +static void vButtonHandlerTask( void *pvParameters ) +{ +const portCHAR *pcInterruptMessage = "Int"; + + for( ;; ) + { + /* Wait for a GPIO interrupt to wake this task. */ + while( xSemaphoreTake( xButtonSemaphore, portMAX_DELAY ) != pdPASS ); + + /* Start the Tx of the message on the UART. */ + UARTIntDisable( UART0_BASE, UART_INT_TX ); + { + pcNextChar = cMessage; + + /* Send the first character. */ + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = *pcNextChar; + } + + pcNextChar++; + } + UARTIntEnable(UART0_BASE, UART_INT_TX); + + /* Queue a message for the print task to display on the LCD. */ + xQueueSend( xPrintQueue, &pcInterruptMessage, portMAX_DELAY ); + + /* Make sure we don't process bounces. */ + vTaskDelay( mainDEBOUNCE_DELAY ); + xSemaphoreTake( xButtonSemaphore, mainNO_DELAY ); + } +} + +/*-----------------------------------------------------------*/ + +void vUART_ISR(void) +{ +unsigned portLONG ulStatus; + + /* What caused the interrupt. */ + ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); + + /* Clear the interrupt. */ + UARTIntClear( UART0_BASE, ulStatus ); + + /* Was a Tx interrupt pending? */ + if( ulStatus & UART_INT_TX ) + { + /* Send the next character in the string. We are not using the FIFO. */ + if( *pcNextChar != NULL ) + { + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = *pcNextChar; + } + pcNextChar++; + } + } +} +/*-----------------------------------------------------------*/ + +void vGPIO_ISR( void ) +{ + /* Clear the interrupt. */ + GPIOPinIntClear(GPIO_PORTC_BASE, mainPUSH_BUTTON); + + /* Wake the button handler task. */ + if( xSemaphoreGiveFromISR( xButtonSemaphore, pdFALSE ) ) + { + portEND_SWITCHING_ISR( pdTRUE ); + } +} +/*-----------------------------------------------------------*/ + +static void vPrintTask( void *pvParameters ) +{ +portCHAR *pcMessage; +unsigned portBASE_TYPE uxLine = 0, uxRow = 0; + + for( ;; ) + { + /* Wait for a message to arrive. */ + xQueueReceive( xPrintQueue, &pcMessage, portMAX_DELAY ); + + /* Write the message to the LCD. */ + uxRow++; + uxLine++; + OSRAMClear(); + OSRAMStringDraw( pcMessage, uxLine & 0x3f, uxRow & 0x01); + } +} + diff --git a/20080212/Demo/CORTEX_LM3S811_IAR/startup.c b/20080212/Demo/CORTEX_LM3S811_IAR/startup.c new file mode 100644 index 000000000..d53376fd7 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_IAR/startup.c @@ -0,0 +1,196 @@ +//***************************************************************************** +// +// startup_ewarm.c - Boot code for Stellaris. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 991 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +// Enable the IAR extensions for this source file. +// +//***************************************************************************** +#pragma language=extended + +//***************************************************************************** +// +// Forward declaration of the default fault handlers. +// +//***************************************************************************** +static void NmiSR(void); +static void FaultISR(void); +static void IntDefaultHandler(void); + +//***************************************************************************** +// +// The entry point for the application. +// +//***************************************************************************** +extern void __iar_program_start(void); + +//***************************************************************************** +// +// External declaration for the interrupt handler used by the application. +// +//***************************************************************************** +extern void xPortPendSVHandler(void); +extern void xPortSysTickHandler(void); +extern void vGPIO_ISR(void); +extern void vUART_ISR(void); + +//***************************************************************************** +// +// Reserve space for the system stack. +// +//***************************************************************************** +#ifndef STACK_SIZE +#define STACK_SIZE 64 +#endif +static unsigned long pulStack[STACK_SIZE] @ ".noinit"; + +//***************************************************************************** +// +// A union that describes the entries of the vector table. The union is needed +// since the first entry is the stack pointer and the remainder are function +// pointers. +// +//***************************************************************************** +typedef union +{ + void (*pfnHandler)(void); + unsigned long ulPtr; +} +uVectorEntry; + +//***************************************************************************** +// +// The minimal vector table for a Cortex M3. Note that the proper constructs +// must be placed on this to ensure that it ends up at physical address +// 0x0000.0000. +// +//***************************************************************************** +__root const uVectorEntry __vector_table[] @ ".intvec" = +{ + { .ulPtr = (unsigned long)pulStack + sizeof(pulStack) }, + // The initial stack pointer + __iar_program_start, // The reset handler + NmiSR, // The NMI handler + FaultISR, // The hard fault handler + IntDefaultHandler, // The MPU fault handler + IntDefaultHandler, // The bus fault handler + IntDefaultHandler, // The usage fault handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // SVCall handler + IntDefaultHandler, // Debug monitor handler + 0, // Reserved + xPortPendSVHandler, // The PendSV handler + xPortSysTickHandler, // The SysTick handler + IntDefaultHandler, // GPIO Port A + IntDefaultHandler, // GPIO Port B + vGPIO_ISR, // GPIO Port C + IntDefaultHandler, // GPIO Port D + IntDefaultHandler, // GPIO Port E + vUART_ISR, // UART0 Rx and Tx + IntDefaultHandler, // UART1 Rx and Tx + IntDefaultHandler, // SSI Rx and Tx + IntDefaultHandler, // I2C Master and Slave + IntDefaultHandler, // PWM Fault + IntDefaultHandler, // PWM Generator 0 + IntDefaultHandler, // PWM Generator 1 + IntDefaultHandler, // PWM Generator 2 + IntDefaultHandler, // Quadrature Encoder + IntDefaultHandler, // ADC Sequence 0 + IntDefaultHandler, // ADC Sequence 1 + IntDefaultHandler, // ADC Sequence 2 + IntDefaultHandler, // ADC Sequence 3 + IntDefaultHandler, // Watchdog timer + IntDefaultHandler, // Timer 0 subtimer A + IntDefaultHandler, // Timer 0 subtimer B + IntDefaultHandler, // Timer 1 subtimer A + IntDefaultHandler, // Timer 1 subtimer B + IntDefaultHandler, // Timer 2 subtimer A + IntDefaultHandler, // Timer 2 subtimer B + IntDefaultHandler, // Analog Comparator 0 + IntDefaultHandler, // Analog Comparator 1 + IntDefaultHandler, // Analog Comparator 2 + IntDefaultHandler, // System Control (PLL, OSC, BO) + IntDefaultHandler // FLASH Control +}; + + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a NMI. This +// simply enters an infinite loop, preserving the system state for examination +// by a debugger. +// +//***************************************************************************** +static void +NmiSR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a fault +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +FaultISR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives an unexpected +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +IntDefaultHandler(void) +{ + // + // Go into an infinite loop. + // + while(1) + { + } +} diff --git a/20080212/Demo/CORTEX_LM3S811_KEIL/FreeRTOSConfig.h b/20080212/Demo/CORTEX_LM3S811_KEIL/FreeRTOSConfig.h new file mode 100644 index 000000000..5c2d2d922 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_KEIL/FreeRTOSConfig.h @@ -0,0 +1,86 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 59 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 7000 ) ) +#define configMAX_TASK_NAME_LEN ( 3 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_CO_ROUTINES 0 + +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/DriverLib.h b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/DriverLib.h new file mode 100644 index 000000000..956bf129a --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/DriverLib.h @@ -0,0 +1,39 @@ +#ifndef DRIVER_LIB_H +#define DRIVER_LIB_H + +#include "DriverLib.h" +#include "hw_adc.h" +#include "hw_comp.h" +#include "hw_flash.h" +#include "hw_gpio.h" +#include "hw_i2c.h" +#include "hw_ints.h" +#include "hw_memmap.h" +#include "hw_nvic.h" +#include "hw_pwm.h" +#include "hw_qei.h" +#include "hw_ssi.h" +#include "hw_sysctl.h" +#include "hw_timer.h" +#include "hw_types.h" +#include "hw_uart.h" +#include "hw_watchdog.h" +#include "osram96x16.h" +#include "src\adc.h" +#include "src\comp.h" +#include "src\cpu.h" +#include "src\debug.h" +#include "src\flash.h" +#include "src\gpio.h" +#include "src\i2c.h" +#include "src\interrupt.h" +#include "src\pwm.h" +#include "src\qei.h" +#include "src\ssi.h" +#include "src\sysctl.h" +#include "src\systick.h" +#include "src\timer.h" +#include "src\uart.h" +#include "src\watchdog.h" + +#endif diff --git a/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_adc.h b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_adc.h new file mode 100644 index 000000000..4d981c611 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_adc.h @@ -0,0 +1,329 @@ +//***************************************************************************** +// +// hw_adc.h - Macros used when accessing the ADC hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_ADC_H__ +#define __HW_ADC_H__ + +//***************************************************************************** +// +// The following define the offsets of the ADC registers. +// +//***************************************************************************** +#define ADC_O_ACTSS 0x00000000 // Active sample register +#define ADC_O_RIS 0x00000004 // Raw interrupt status register +#define ADC_O_IM 0x00000008 // Interrupt mask register +#define ADC_O_ISC 0x0000000C // Interrupt status/clear register +#define ADC_O_OSTAT 0x00000010 // Overflow status register +#define ADC_O_EMUX 0x00000014 // Event multiplexer select reg. +#define ADC_O_USTAT 0x00000018 // Underflow status register +#define ADC_O_SSPRI 0x00000020 // Channel priority register +#define ADC_O_PSSI 0x00000028 // Processor sample initiate reg. +#define ADC_O_SSMUX0 0x00000040 // Multiplexer select 0 register +#define ADC_O_SSCTL0 0x00000044 // Sample sequence control 0 reg. +#define ADC_O_SSFIFO0 0x00000048 // Result FIFO 0 register +#define ADC_O_SSFSTAT0 0x0000004C // FIFO 0 status register +#define ADC_O_SSMUX1 0x00000060 // Multiplexer select 1 register +#define ADC_O_SSCTL1 0x00000064 // Sample sequence control 1 reg. +#define ADC_O_SSFIFO1 0x00000068 // Result FIFO 1 register +#define ADC_O_SSFSTAT1 0x0000006C // FIFO 1 status register +#define ADC_O_SSMUX2 0x00000080 // Multiplexer select 2 register +#define ADC_O_SSCTL2 0x00000084 // Sample sequence control 2 reg. +#define ADC_O_SSFIFO2 0x00000088 // Result FIFO 2 register +#define ADC_O_SSFSTAT2 0x0000008C // FIFO 2 status register +#define ADC_O_SSMUX3 0x000000A0 // Multiplexer select 3 register +#define ADC_O_SSCTL3 0x000000A4 // Sample sequence control 3 reg. +#define ADC_O_SSFIFO3 0x000000A8 // Result FIFO 3 register +#define ADC_O_SSFSTAT3 0x000000AC // FIFO 3 status register +#define ADC_O_TMLB 0x00000100 // Test mode loopback register + +//***************************************************************************** +// +// The following define the offsets of the ADC sequence registers. +// +//***************************************************************************** +#define ADC_O_SEQ 0x00000040 // Offset to the first sequence +#define ADC_O_SEQ_STEP 0x00000020 // Increment to the next sequence +#define ADC_O_X_SSMUX 0x00000000 // Multiplexer select register +#define ADC_O_X_SSCTL 0x00000004 // Sample sequence control register +#define ADC_O_X_SSFIFO 0x00000008 // Result FIFO register +#define ADC_O_X_SSFSTAT 0x0000000C // FIFO status register + +//***************************************************************************** +// +// The following define the bit fields in the ADC_ACTSS register. +// +//***************************************************************************** +#define ADC_ACTSS_ASEN3 0x00000008 // Sample sequence 3 enable +#define ADC_ACTSS_ASEN2 0x00000004 // Sample sequence 2 enable +#define ADC_ACTSS_ASEN1 0x00000002 // Sample sequence 1 enable +#define ADC_ACTSS_ASEN0 0x00000001 // Sample sequence 0 enable + +//***************************************************************************** +// +// The following define the bit fields in the ADC_RIS register. +// +//***************************************************************************** +#define ADC_RIS_INR3 0x00000008 // Sample sequence 3 interrupt +#define ADC_RIS_INR2 0x00000004 // Sample sequence 2 interrupt +#define ADC_RIS_INR1 0x00000002 // Sample sequence 1 interrupt +#define ADC_RIS_INR0 0x00000001 // Sample sequence 0 interrupt + +//***************************************************************************** +// +// The following define the bit fields in the ADC_IM register. +// +//***************************************************************************** +#define ADC_IM_MASK3 0x00000008 // Sample sequence 3 mask +#define ADC_IM_MASK2 0x00000004 // Sample sequence 2 mask +#define ADC_IM_MASK1 0x00000002 // Sample sequence 1 mask +#define ADC_IM_MASK0 0x00000001 // Sample sequence 0 mask + +//***************************************************************************** +// +// The following define the bit fields in the ADC_ISC register. +// +//***************************************************************************** +#define ADC_ISC_IN3 0x00000008 // Sample sequence 3 interrupt +#define ADC_ISC_IN2 0x00000004 // Sample sequence 2 interrupt +#define ADC_ISC_IN1 0x00000002 // Sample sequence 1 interrupt +#define ADC_ISC_IN0 0x00000001 // Sample sequence 0 interrupt + +//***************************************************************************** +// +// The following define the bit fields in the ADC_OSTAT register. +// +//***************************************************************************** +#define ADC_OSTAT_OV3 0x00000008 // Sample sequence 3 overflow +#define ADC_OSTAT_OV2 0x00000004 // Sample sequence 2 overflow +#define ADC_OSTAT_OV1 0x00000002 // Sample sequence 1 overflow +#define ADC_OSTAT_OV0 0x00000001 // Sample sequence 0 overflow + +//***************************************************************************** +// +// The following define the bit fields in the ADC_EMUX register. +// +//***************************************************************************** +#define ADC_EMUX_EM3_MASK 0x0000F000 // Event mux 3 mask +#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor event +#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog comparator 0 event +#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog comparator 1 event +#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog comparator 2 event +#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External event +#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer event +#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0 event +#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1 event +#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2 event +#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always event +#define ADC_EMUX_EM2_MASK 0x00000F00 // Event mux 2 mask +#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor event +#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog comparator 0 event +#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog comparator 1 event +#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog comparator 2 event +#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External event +#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer event +#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0 event +#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1 event +#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2 event +#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always event +#define ADC_EMUX_EM1_MASK 0x000000F0 // Event mux 1 mask +#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor event +#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog comparator 0 event +#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog comparator 1 event +#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog comparator 2 event +#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External event +#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer event +#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0 event +#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1 event +#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2 event +#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always event +#define ADC_EMUX_EM0_MASK 0x0000000F // Event mux 0 mask +#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor event +#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog comparator 0 event +#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog comparator 1 event +#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog comparator 2 event +#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External event +#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer event +#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0 event +#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1 event +#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2 event +#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always event +#define ADC_EMUX_EM0_SHIFT 0 // The shift for the first event +#define ADC_EMUX_EM1_SHIFT 4 // The shift for the second event +#define ADC_EMUX_EM2_SHIFT 8 // The shift for the third event +#define ADC_EMUX_EM3_SHIFT 12 // The shift for the fourth event + +//***************************************************************************** +// +// The following define the bit fields in the ADC_USTAT register. +// +//***************************************************************************** +#define ADC_USTAT_UV3 0x00000008 // Sample sequence 3 underflow +#define ADC_USTAT_UV2 0x00000004 // Sample sequence 2 underflow +#define ADC_USTAT_UV1 0x00000002 // Sample sequence 1 underflow +#define ADC_USTAT_UV0 0x00000001 // Sample sequence 0 underflow + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SSPRI register. +// +//***************************************************************************** +#define ADC_SSPRI_SS3_MASK 0x00003000 // Sequencer 3 priority mask +#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority +#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority +#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority +#define ADC_SSPRI_SS2_MASK 0x00000300 // Sequencer 2 priority mask +#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority +#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority +#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority +#define ADC_SSPRI_SS1_MASK 0x00000030 // Sequencer 1 priority mask +#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority +#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority +#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority +#define ADC_SSPRI_SS0_MASK 0x00000003 // Sequencer 0 priority mask +#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority +#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority +#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority + +//***************************************************************************** +// +// The following define the bit fields in the ADC_PSSI register. +// +//***************************************************************************** +#define ADC_PSSI_SS3 0x00000008 // Trigger sample sequencer 3 +#define ADC_PSSI_SS2 0x00000004 // Trigger sample sequencer 2 +#define ADC_PSSI_SS1 0x00000002 // Trigger sample sequencer 1 +#define ADC_PSSI_SS0 0x00000001 // Trigger sample sequencer 0 + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SSMUX0, ADC_SSMUX1, +// ADC_SSMUX2, and ADC_SSMUX3 registers. Not all fields are present in all +// registers. +// +//***************************************************************************** +#define ADC_SSMUX_MUX7_MASK 0x70000000 // 8th mux select mask +#define ADC_SSMUX_MUX6_MASK 0x07000000 // 7th mux select mask +#define ADC_SSMUX_MUX5_MASK 0x00700000 // 6th mux select mask +#define ADC_SSMUX_MUX4_MASK 0x00070000 // 5th mux select mask +#define ADC_SSMUX_MUX3_MASK 0x00007000 // 4th mux select mask +#define ADC_SSMUX_MUX2_MASK 0x00000700 // 3rd mux select mask +#define ADC_SSMUX_MUX1_MASK 0x00000070 // 2nd mux select mask +#define ADC_SSMUX_MUX0_MASK 0x00000007 // 1st mux select mask +#define ADC_SSMUX_MUX7_SHIFT 28 +#define ADC_SSMUX_MUX6_SHIFT 24 +#define ADC_SSMUX_MUX5_SHIFT 20 +#define ADC_SSMUX_MUX4_SHIFT 16 +#define ADC_SSMUX_MUX3_SHIFT 12 +#define ADC_SSMUX_MUX2_SHIFT 8 +#define ADC_SSMUX_MUX1_SHIFT 4 +#define ADC_SSMUX_MUX0_SHIFT 0 + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SSCTL0, ADC_SSCTL1, +// ADC_SSCTL2, and ADC_SSCTL3 registers. Not all fields are present in all +// registers. +// +//***************************************************************************** +#define ADC_SSCTL_TS7 0x80000000 // 8th temperature sensor select +#define ADC_SSCTL_IE7 0x40000000 // 8th interrupt enable +#define ADC_SSCTL_END7 0x20000000 // 8th sequence end select +#define ADC_SSCTL_D7 0x10000000 // 8th differential select +#define ADC_SSCTL_TS6 0x08000000 // 7th temperature sensor select +#define ADC_SSCTL_IE6 0x04000000 // 7th interrupt enable +#define ADC_SSCTL_END6 0x02000000 // 7th sequence end select +#define ADC_SSCTL_D6 0x01000000 // 7th differential select +#define ADC_SSCTL_TS5 0x00800000 // 6th temperature sensor select +#define ADC_SSCTL_IE5 0x00400000 // 6th interrupt enable +#define ADC_SSCTL_END5 0x00200000 // 6th sequence end select +#define ADC_SSCTL_D5 0x00100000 // 6th differential select +#define ADC_SSCTL_TS4 0x00080000 // 5th temperature sensor select +#define ADC_SSCTL_IE4 0x00040000 // 5th interrupt enable +#define ADC_SSCTL_END4 0x00020000 // 5th sequence end select +#define ADC_SSCTL_D4 0x00010000 // 5th differential select +#define ADC_SSCTL_TS3 0x00008000 // 4th temperature sensor select +#define ADC_SSCTL_IE3 0x00004000 // 4th interrupt enable +#define ADC_SSCTL_END3 0x00002000 // 4th sequence end select +#define ADC_SSCTL_D3 0x00001000 // 4th differential select +#define ADC_SSCTL_TS2 0x00000800 // 3rd temperature sensor select +#define ADC_SSCTL_IE2 0x00000400 // 3rd interrupt enable +#define ADC_SSCTL_END2 0x00000200 // 3rd sequence end select +#define ADC_SSCTL_D2 0x00000100 // 3rd differential select +#define ADC_SSCTL_TS1 0x00000080 // 2nd temperature sensor select +#define ADC_SSCTL_IE1 0x00000040 // 2nd interrupt enable +#define ADC_SSCTL_END1 0x00000020 // 2nd sequence end select +#define ADC_SSCTL_D1 0x00000010 // 2nd differential select +#define ADC_SSCTL_TS0 0x00000008 // 1st temperature sensor select +#define ADC_SSCTL_IE0 0x00000004 // 1st interrupt enable +#define ADC_SSCTL_END0 0x00000002 // 1st sequence end select +#define ADC_SSCTL_D0 0x00000001 // 1st differential select + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SSFIFO0, ADC_SSFIFO1, +// ADC_SSFIFO2, and ADC_SSFIFO3 registers. +// +//***************************************************************************** +#define ADC_SSFIFO_DATA_MASK 0x000003FF // Sample data +#define ADC_SSFIFO_DATA_SHIFT 0 + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SSFSTAT0, ADC_SSFSTAT1, +// ADC_SSFSTAT2, and ADC_SSFSTAT3 registers. +// +//***************************************************************************** +#define ADC_SSFSTAT_FULL 0x00001000 // FIFO is full +#define ADC_SSFSTAT_EMPTY 0x00000100 // FIFO is empty +#define ADC_SSFSTAT_HPTR 0x000000F0 // FIFO head pointer +#define ADC_SSFSTAT_TPTR 0x0000000F // FIFO tail pointer + +//***************************************************************************** +// +// The following define the bit fields in the ADC_TMLB register. +// +//***************************************************************************** +#define ADC_TMLB_LB 0x00000001 // Loopback control signals + +//***************************************************************************** +// +// The following define the bit fields in the loopback ADC data. +// +//***************************************************************************** +#define ADC_LB_CNT_MASK 0x000003C0 // Sample counter mask +#define ADC_LB_CONT 0x00000020 // Continuation sample +#define ADC_LB_DIFF 0x00000010 // Differential sample +#define ADC_LB_TS 0x00000008 // Temperature sensor sample +#define ADC_LB_MUX_MASK 0x00000007 // Input channel number mask +#define ADC_LB_CNT_SHIFT 6 // Sample counter shift +#define ADC_LB_MUX_SHIFT 0 // Input channel number shift + +#endif // __HW_ADC_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_comp.h b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_comp.h new file mode 100644 index 000000000..9c5212b00 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_comp.h @@ -0,0 +1,118 @@ +//***************************************************************************** +// +// hw_comp.h - Macros used when accessing the comparator hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_COMP_H__ +#define __HW_COMP_H__ + +//***************************************************************************** +// +// The following define the offsets of the comparator registers. +// +//***************************************************************************** +#define COMP_O_MIS 0x00000000 // Interrupt status register +#define COMP_O_RIS 0x00000004 // Raw interrupt status register +#define COMP_O_INTEN 0x00000008 // Interrupt enable register +#define COMP_O_REFCTL 0x00000010 // Reference voltage control reg. +#define COMP_O_ACSTAT0 0x00000020 // Comp0 status register +#define COMP_O_ACCTL0 0x00000024 // Comp0 control register +#define COMP_O_ACSTAT1 0x00000040 // Comp1 status register +#define COMP_O_ACCTL1 0x00000044 // Comp1 control register +#define COMP_O_ACSTAT2 0x00000060 // Comp2 status register +#define COMP_O_ACCTL2 0x00000064 // Comp2 control register + +//***************************************************************************** +// +// The following define the bit fields in the COMP_MIS, COMP_RIS, and +// COMP_INTEN registers. +// +//***************************************************************************** +#define COMP_INT_2 0x00000004 // Comp2 interrupt +#define COMP_INT_1 0x00000002 // Comp1 interrupt +#define COMP_INT_0 0x00000001 // Comp0 interrupt + +//***************************************************************************** +// +// The following define the bit fields in the COMP_REFCTL register. +// +//***************************************************************************** +#define COMP_REFCTL_EN 0x00000200 // Reference voltage enable +#define COMP_REFCTL_RNG 0x00000100 // Reference voltage range +#define COMP_REFCTL_VREF_MASK 0x0000000F // Reference voltage select mask +#define COMP_REFCTL_VREF_SHIFT 0 + +//***************************************************************************** +// +// The following define the bit fields in the COMP_ACSTAT0, COMP_ACSTAT1, and +// COMP_ACSTAT2 registers. +// +//***************************************************************************** +#define COMP_ACSTAT_OVAL 0x00000002 // Comparator output value + +//***************************************************************************** +// +// The following define the bit fields in the COMP_ACCTL0, COMP_ACCTL1, and +// COMP_ACCTL2 registers. +// +//***************************************************************************** +#define COMP_ACCTL_TMASK 0x00000800 // Trigger enable +#define COMP_ACCTL_ASRCP_MASK 0x00000600 // Vin+ source select mask +#define COMP_ACCTL_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin +#define COMP_ACCTL_ASRCP_PIN0 0x00000200 // Comp0+ pin +#define COMP_ACCTL_ASRCP_REF 0x00000400 // Internal voltage reference +#define COMP_ACCTL_ASRCP_RES 0x00000600 // Reserved +#define COMP_ACCTL_OEN 0x00000100 // Comparator output enable +#define COMP_ACCTL_TSVAL 0x00000080 // Trigger polarity select +#define COMP_ACCTL_TSEN_MASK 0x00000060 // Trigger sense mask +#define COMP_ACCTL_TSEN_LEVEL 0x00000000 // Trigger is level sense +#define COMP_ACCTL_TSEN_FALL 0x00000020 // Trigger is falling edge +#define COMP_ACCTL_TSEN_RISE 0x00000040 // Trigger is rising edge +#define COMP_ACCTL_TSEN_BOTH 0x00000060 // Trigger is both edges +#define COMP_ACCTL_ISLVAL 0x00000010 // Interrupt polarity select +#define COMP_ACCTL_ISEN_MASK 0x0000000C // Interrupt sense mask +#define COMP_ACCTL_ISEN_LEVEL 0x00000000 // Interrupt is level sense +#define COMP_ACCTL_ISEN_FALL 0x00000004 // Interrupt is falling edge +#define COMP_ACCTL_ISEN_RISE 0x00000008 // Interrupt is rising edge +#define COMP_ACCTL_ISEN_BOTH 0x0000000C // Interrupt is both edges +#define COMP_ACCTL_CINV 0x00000002 // Comparator output invert + +//***************************************************************************** +// +// The following define the reset values for the comparator registers. +// +//***************************************************************************** +#define COMP_RV_MIS 0x00000000 // Interrupt status register +#define COMP_RV_RIS 0x00000000 // Raw interrupt status register +#define COMP_RV_INTEN 0x00000000 // Interrupt enable register +#define COMP_RV_REFCTL 0x00000000 // Reference voltage control reg. +#define COMP_RV_ACSTAT0 0x00000000 // Comp0 status register +#define COMP_RV_ACCTL0 0x00000000 // Comp0 control register +#define COMP_RV_ACSTAT1 0x00000000 // Comp1 status register +#define COMP_RV_ACCTL1 0x00000000 // Comp1 control register +#define COMP_RV_ACSTAT2 0x00000000 // Comp2 status register +#define COMP_RV_ACCTL2 0x00000000 // Comp2 control register + +#endif // __HW_COMP_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_flash.h b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_flash.h new file mode 100644 index 000000000..d27ebcfbf --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_flash.h @@ -0,0 +1,139 @@ +//***************************************************************************** +// +// hw_flash.h - Macros used when accessing the flash controller. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_FLASH_H__ +#define __HW_FLASH_H__ + +//***************************************************************************** +// +// The following define the offsets of the FLASH registers. +// +//***************************************************************************** +#define FLASH_FMA 0x400FD000 // Memory address register +#define FLASH_FMD 0x400FD004 // Memory data register +#define FLASH_FMC 0x400FD008 // Memory control register +#define FLASH_FCRIS 0x400FD00c // Raw interrupt status register +#define FLASH_FCIM 0x400FD010 // Interrupt mask register +#define FLASH_FCMISC 0x400FD014 // Interrupt status register +#define FLASH_FMPRE 0x400FE130 // FLASH read protect register +#define FLASH_FMPPE 0x400FE134 // FLASH program protect register +#define FLASH_USECRL 0x400FE140 // uSec reload register + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FMC register. +// +//***************************************************************************** +#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask +#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key +#define FLASH_FMC_COMT 0x00000008 // Commit user register +#define FLASH_FMC_MERASE 0x00000004 // Mass erase FLASH +#define FLASH_FMC_ERASE 0x00000002 // Erase FLASH page +#define FLASH_FMC_WRITE 0x00000001 // Write FLASH word + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FCRIS register. +// +//***************************************************************************** +#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status +#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FCIM register. +// +//***************************************************************************** +#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask +#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FMIS register. +// +//***************************************************************************** +#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status +#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FMPRE and FLASH_FMPPE +// registers. +// +//***************************************************************************** +#define FLASH_FMP_BLOCK_31 0x80000000 // Enable for block 31 +#define FLASH_FMP_BLOCK_30 0x40000000 // Enable for block 30 +#define FLASH_FMP_BLOCK_29 0x20000000 // Enable for block 29 +#define FLASH_FMP_BLOCK_28 0x10000000 // Enable for block 28 +#define FLASH_FMP_BLOCK_27 0x08000000 // Enable for block 27 +#define FLASH_FMP_BLOCK_26 0x04000000 // Enable for block 26 +#define FLASH_FMP_BLOCK_25 0x02000000 // Enable for block 25 +#define FLASH_FMP_BLOCK_24 0x01000000 // Enable for block 24 +#define FLASH_FMP_BLOCK_23 0x00800000 // Enable for block 23 +#define FLASH_FMP_BLOCK_22 0x00400000 // Enable for block 22 +#define FLASH_FMP_BLOCK_21 0x00200000 // Enable for block 21 +#define FLASH_FMP_BLOCK_20 0x00100000 // Enable for block 20 +#define FLASH_FMP_BLOCK_19 0x00080000 // Enable for block 19 +#define FLASH_FMP_BLOCK_18 0x00040000 // Enable for block 18 +#define FLASH_FMP_BLOCK_17 0x00020000 // Enable for block 17 +#define FLASH_FMP_BLOCK_16 0x00010000 // Enable for block 16 +#define FLASH_FMP_BLOCK_15 0x00008000 // Enable for block 15 +#define FLASH_FMP_BLOCK_14 0x00004000 // Enable for block 14 +#define FLASH_FMP_BLOCK_13 0x00002000 // Enable for block 13 +#define FLASH_FMP_BLOCK_12 0x00001000 // Enable for block 12 +#define FLASH_FMP_BLOCK_11 0x00000800 // Enable for block 11 +#define FLASH_FMP_BLOCK_10 0x00000400 // Enable for block 10 +#define FLASH_FMP_BLOCK_9 0x00000200 // Enable for block 9 +#define FLASH_FMP_BLOCK_8 0x00000100 // Enable for block 8 +#define FLASH_FMP_BLOCK_7 0x00000080 // Enable for block 7 +#define FLASH_FMP_BLOCK_6 0x00000040 // Enable for block 6 +#define FLASH_FMP_BLOCK_5 0x00000020 // Enable for block 5 +#define FLASH_FMP_BLOCK_4 0x00000010 // Enable for block 4 +#define FLASH_FMP_BLOCK_3 0x00000008 // Enable for block 3 +#define FLASH_FMP_BLOCK_2 0x00000004 // Enable for block 2 +#define FLASH_FMP_BLOCK_1 0x00000002 // Enable for block 1 +#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0 + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_USECRL register. +// +//***************************************************************************** +#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec +#define FLASH_USECRL_SHIFT 0 + +//***************************************************************************** +// +// The erase size is the size of the FLASH block that is erased by an erase +// operation, and the protect size is the size of the FLASH block that is +// protected by each protection register. +// +//***************************************************************************** +#define FLASH_ERASE_SIZE 0x00000400 +#define FLASH_PROTECT_SIZE 0x00000800 + +#endif // __HW_FLASH_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_gpio.h b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_gpio.h new file mode 100644 index 000000000..10bf23b24 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_gpio.h @@ -0,0 +1,103 @@ +//***************************************************************************** +// +// hw_gpio.h - Defines and Macros for GPIO hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_GPIO_H__ +#define __HW_GPIO_H__ + +//***************************************************************************** +// +// GPIO Register Offsets. +// +//***************************************************************************** +#define GPIO_O_DATA 0x00000000 // Data register. +#define GPIO_O_DIR 0x00000400 // Data direction register. +#define GPIO_O_IS 0x00000404 // Interrupt sense register. +#define GPIO_O_IBE 0x00000408 // Interrupt both edges register. +#define GPIO_O_IEV 0x0000040C // Intterupt event register. +#define GPIO_O_IM 0x00000410 // Interrupt mask register. +#define GPIO_O_RIS 0x00000414 // Raw interrupt status register. +#define GPIO_O_MIS 0x00000418 // Masked interrupt status reg. +#define GPIO_O_ICR 0x0000041C // Interrupt clear register. +#define GPIO_O_AFSEL 0x00000420 // Mode control select register. +#define GPIO_O_DR2R 0x00000500 // 2ma drive select register. +#define GPIO_O_DR4R 0x00000504 // 4ma drive select register. +#define GPIO_O_DR8R 0x00000508 // 8ma drive select register. +#define GPIO_O_ODR 0x0000050C // Open drain select register. +#define GPIO_O_PUR 0x00000510 // Pull up select register. +#define GPIO_O_PDR 0x00000514 // Pull down select register. +#define GPIO_O_SLR 0x00000518 // Slew rate control enable reg. +#define GPIO_O_DEN 0x0000051C // Digital input enable register. +#define GPIO_O_PeriphID4 0x00000FD0 // +#define GPIO_O_PeriphID5 0x00000FD4 // +#define GPIO_O_PeriphID6 0x00000FD8 // +#define GPIO_O_PeriphID7 0x00000FDC // +#define GPIO_O_PeriphID0 0x00000FE0 // +#define GPIO_O_PeriphID1 0x00000FE4 // +#define GPIO_O_PeriphID2 0x00000FE8 // +#define GPIO_O_PeriphID3 0x00000FEC // +#define GPIO_O_PCellID0 0x00000FF0 // +#define GPIO_O_PCellID1 0x00000FF4 // +#define GPIO_O_PCellID2 0x00000FF8 // +#define GPIO_O_PCellID3 0x00000FFC // + +//***************************************************************************** +// +// GPIO Register reset values. +// +//***************************************************************************** +#define GPIO_RV_DATA 0x00000000 // Data register reset value. +#define GPIO_RV_DIR 0x00000000 // Data direction reg RV. +#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV. +#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV. +#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV. +#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV. +#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV. +#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV. +#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV. +#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV. +#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV. +#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV. +#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV. +#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV. +#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV. +#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV. +#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV. +#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV. +#define GPIO_RV_PeriphID4 0x00000000 // +#define GPIO_RV_PeriphID5 0x00000000 // +#define GPIO_RV_PeriphID6 0x00000000 // +#define GPIO_RV_PeriphID7 0x00000000 // +#define GPIO_RV_PeriphID0 0x00000061 // +#define GPIO_RV_PeriphID1 0x00000010 // +#define GPIO_RV_PeriphID2 0x00000004 // +#define GPIO_RV_PeriphID3 0x00000000 // +#define GPIO_RV_PCellID0 0x0000000D // +#define GPIO_RV_PCellID1 0x000000F0 // +#define GPIO_RV_PCellID2 0x00000005 // +#define GPIO_RV_PCellID3 0x000000B1 // + +#endif // __HW_GPIO_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_i2c.h b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_i2c.h new file mode 100644 index 000000000..2a3900c59 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_i2c.h @@ -0,0 +1,197 @@ +//***************************************************************************** +// +// hw_i2c.h - Macros used when accessing the I2C master and slave hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_I2C_H__ +#define __HW_I2C_H__ + +//***************************************************************************** +// +// The following defines the offset between the I2C master and slave registers. +// +//***************************************************************************** +#define I2C_O_SLAVE 0x00000800 // Offset from master to slave + +//***************************************************************************** +// +// The following define the offsets of the I2C master registers. +// +//***************************************************************************** +#define I2C_MASTER_O_SA 0x00000000 // Slave address register +#define I2C_MASTER_O_CS 0x00000004 // Control and Status register +#define I2C_MASTER_O_DR 0x00000008 // Data register +#define I2C_MASTER_O_TPR 0x0000000C // Timer period register +#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register +#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register +#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg +#define I2C_MASTER_O_MICR 0x0000001c // Interrupt clear register +#define I2C_MASTER_O_CR 0x00000020 // Configuration register + +//***************************************************************************** +// +// The following define the offsets of the I2C slave registers. +// +//***************************************************************************** +#define I2C_SLAVE_O_OAR 0x00000000 // Own address register +#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register +#define I2C_SLAVE_O_DR 0x00000008 // Data register +#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register +#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register +#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg +#define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register + +//***************************************************************************** +// +// The followng define the bit fields in the I2C master slave address register. +// +//***************************************************************************** +#define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address +#define I2C_MASTER_SA_RS 0x00000001 // Receive/send +#define I2C_MASTER_SA_SA_SHIFT 1 + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Control and Status +// register. +// +//***************************************************************************** +#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde +#define I2C_MASTER_CS_STOP 0x00000004 // Stop +#define I2C_MASTER_CS_START 0x00000002 // Start +#define I2C_MASTER_CS_RUN 0x00000001 // Run +#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy +#define I2C_MASTER_CS_IDLE 0x00000020 // Idle +#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration +#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged +#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged +#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred +#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data +#define I2C_MASTER_CS_ERR_MASK 0x0000001C + +//***************************************************************************** +// +// The following define values used in determining the contents of the I2C +// Master Timer Period register. +// +//***************************************************************************** +#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period +#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period +#define I2C_MASTER_TPR_SCL (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP) +#define I2C_SCL_STANDARD 100000 // SCL standard frequency +#define I2C_SCL_FAST 400000 // SCL fast frequency + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Interrupt Mask +// register. +// +//***************************************************************************** +#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Raw Interrupt Status +// register. +// +//***************************************************************************** +#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Masked Interrupt +// Status register. +// +//***************************************************************************** +#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Interrupt Clear +// register. +// +//***************************************************************************** +#define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Configuration +// register. +// +//***************************************************************************** +#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable +#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable +#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Own Address register. +// +//***************************************************************************** +#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Control/Status +// register. +// +//***************************************************************************** +#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device +#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received +#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Interrupt Mask +// register. +// +//***************************************************************************** +#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Raw Interrupt Status +// register. +// +//***************************************************************************** +#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Masked Interrupt +// Status register. +// +//***************************************************************************** +#define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Interrupt Clear +// register. +// +//***************************************************************************** +#define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear + +#endif // __HW_I2C_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_ints.h b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_ints.h new file mode 100644 index 000000000..820d5cdff --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_ints.h @@ -0,0 +1,97 @@ +//***************************************************************************** +// +// hw_ints.h - Macros that define the interrupt assignment on Stellaris. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_INTS_H__ +#define __HW_INTS_H__ + +//***************************************************************************** +// +// The following define the fault assignments. +// +//***************************************************************************** +#define FAULT_NMI 2 // NMI fault +#define FAULT_HARD 3 // Hard fault +#define FAULT_MPU 4 // MPU fault +#define FAULT_BUS 5 // Bus fault +#define FAULT_USAGE 6 // Usage fault +#define FAULT_SVCALL 11 // SVCall +#define FAULT_DEBUG 12 // Debug monitor +#define FAULT_PENDSV 14 // PendSV +#define FAULT_SYSTICK 15 // System Tick + +//***************************************************************************** +// +// The following define the interrupt assignments. +// +//***************************************************************************** +#define INT_GPIOA 16 // GPIO Port A +#define INT_GPIOB 17 // GPIO Port B +#define INT_GPIOC 18 // GPIO Port C +#define INT_GPIOD 19 // GPIO Port D +#define INT_GPIOE 20 // GPIO Port E +#define INT_UART0 21 // UART0 Rx and Tx +#define INT_UART1 22 // UART1 Rx and Tx +#define INT_SSI 23 // SSI Rx and Tx +#define INT_I2C 24 // I2C Master and Slave +#define INT_PWM_FAULT 25 // PWM Fault +#define INT_PWM0 26 // PWM Generator 0 +#define INT_PWM1 27 // PWM Generator 1 +#define INT_PWM2 28 // PWM Generator 2 +#define INT_QEI 29 // Quadrature Encoder +#define INT_ADC0 30 // ADC Sequence 0 +#define INT_ADC1 31 // ADC Sequence 1 +#define INT_ADC2 32 // ADC Sequence 2 +#define INT_ADC3 33 // ADC Sequence 3 +#define INT_WATCHDOG 34 // Watchdog timer +#define INT_TIMER0A 35 // Timer 0 subtimer A +#define INT_TIMER0B 36 // Timer 0 subtimer B +#define INT_TIMER1A 37 // Timer 1 subtimer A +#define INT_TIMER1B 38 // Timer 1 subtimer B +#define INT_TIMER2A 39 // Timer 2 subtimer A +#define INT_TIMER2B 40 // Timer 2 subtimer B +#define INT_COMP0 41 // Analog Comparator 0 +#define INT_COMP1 42 // Analog Comparator 1 +#define INT_COMP2 43 // Analog Comparator 2 +#define INT_SYSCTL 44 // System Control (PLL, OSC, BO) +#define INT_FLASH 45 // FLASH Control + +//***************************************************************************** +// +// The total number of interrupts. +// +//***************************************************************************** +#define NUM_INTERRUPTS 46 + +//***************************************************************************** +// +// The total number of priority levels. +// +//***************************************************************************** +#define NUM_PRIORITY 8 +#define NUM_PRIORITY_BITS 3 + +#endif // __HW_INTS_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_memmap.h b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_memmap.h new file mode 100644 index 000000000..4340d63d1 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_memmap.h @@ -0,0 +1,64 @@ +//***************************************************************************** +// +// hw_memmap.h - Macros defining the memory map of Stellaris. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_MEMMAP_H__ +#define __HW_MEMMAP_H__ + +//***************************************************************************** +// +// The following define the base address of the memories and peripherals. +// +//***************************************************************************** +#define FLASH_BASE 0x00000000 // FLASH memory +#define SRAM_BASE 0x20000000 // SRAM memory +#define WATCHDOG_BASE 0x40000000 // Watchdog +#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A +#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B +#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C +#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D +#define SSI_BASE 0x40008000 // SSI +#define UART0_BASE 0x4000C000 // UART0 +#define UART1_BASE 0x4000D000 // UART1 +#define I2C_MASTER_BASE 0x40020000 // I2C Master +#define I2C_SLAVE_BASE 0x40020800 // I2C Slave +#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E +#define PWM_BASE 0x40028000 // PWM +#define QEI_BASE 0x4002C000 // QEI +#define TIMER0_BASE 0x40030000 // Timer0 +#define TIMER1_BASE 0x40031000 // Timer1 +#define TIMER2_BASE 0x40032000 // Timer2 +#define ADC_BASE 0x40038000 // ADC +#define COMP_BASE 0x4003C000 // Analog comparators +#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller +#define SYSCTL_BASE 0x400FE000 // System Control +#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell +#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace +#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint +#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl +#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit + +#endif // __HW_MEMMAP_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_nvic.h b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_nvic.h new file mode 100644 index 000000000..692af25df --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_nvic.h @@ -0,0 +1,830 @@ +//***************************************************************************** +// +// hw_nvic.h - Macros used when accessing the NVIC hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_NVIC_H__ +#define __HW_NVIC_H__ + +//***************************************************************************** +// +// The following define the addresses of the NVIC registers. +// +//***************************************************************************** +#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg. +#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg. +#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register +#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register +#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg. +#define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register +#define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg. +#define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register +#define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg. +#define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register +#define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register +#define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register +#define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register +#define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register +#define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register +#define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register +#define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register +#define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register +#define NVIC_CPUID 0xE000ED00 // CPUID Base Register +#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register +#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register +#define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg. +#define NVIC_SYS_CTRL 0xE000ED10 // System Control Register +#define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register +#define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority +#define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority +#define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority +#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State +#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg. +#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register +#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register +#define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register +#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register +#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register +#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register +#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register +#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register +#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg. +#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg. +#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select +#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data +#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control +#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg. + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_INT_TYPE register. +// +//***************************************************************************** +#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) +#define NVIC_INT_TYPE_LINES_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_CTRL register. +// +//***************************************************************************** +#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag +#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source +#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable +#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_RELOAD register. +// +//***************************************************************************** +#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value +#define NVIC_ST_RELOAD_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_CURRENT register. +// +//***************************************************************************** +#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value +#define NVIC_ST_CURRENT_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_CAL register. +// +//***************************************************************************** +#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock +#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew +#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value +#define NVIC_ST_CAL_ONEMS_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_EN0 register. +// +//***************************************************************************** +#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable +#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable +#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable +#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable +#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable +#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable +#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable +#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable +#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable +#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable +#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable +#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable +#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable +#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable +#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable +#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable +#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable +#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable +#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable +#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable +#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable +#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable +#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable +#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable +#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable +#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable +#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable +#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable +#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable +#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable +#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable +#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DIS0 register. +// +//***************************************************************************** +#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable +#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable +#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable +#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable +#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable +#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable +#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable +#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable +#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable +#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable +#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable +#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable +#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable +#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable +#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable +#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable +#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable +#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable +#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable +#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable +#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable +#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable +#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable +#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable +#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable +#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable +#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable +#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable +#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable +#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable +#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable +#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PEND0 register. +// +//***************************************************************************** +#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend +#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend +#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend +#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend +#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend +#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend +#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend +#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend +#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend +#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend +#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend +#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend +#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend +#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend +#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend +#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend +#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend +#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend +#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend +#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend +#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend +#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend +#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend +#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend +#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend +#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend +#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend +#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend +#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend +#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend +#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend +#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_UNPEND0 register. +// +//***************************************************************************** +#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend +#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend +#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend +#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend +#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend +#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend +#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend +#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend +#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend +#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend +#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend +#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend +#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend +#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend +#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend +#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend +#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend +#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend +#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend +#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend +#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend +#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend +#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend +#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend +#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend +#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend +#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend +#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend +#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend +#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend +#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend +#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ACTIVE0 register. +// +//***************************************************************************** +#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active +#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active +#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active +#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active +#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active +#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active +#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active +#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active +#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active +#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active +#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active +#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active +#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active +#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active +#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active +#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active +#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active +#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active +#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active +#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active +#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active +#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active +#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active +#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active +#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active +#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active +#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active +#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active +#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active +#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active +#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active +#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI0 register. +// +//***************************************************************************** +#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask +#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask +#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask +#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask +#define NVIC_PRI0_INT3_S 24 +#define NVIC_PRI0_INT2_S 16 +#define NVIC_PRI0_INT1_S 8 +#define NVIC_PRI0_INT0_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI1 register. +// +//***************************************************************************** +#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask +#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask +#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask +#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask +#define NVIC_PRI1_INT7_S 24 +#define NVIC_PRI1_INT6_S 16 +#define NVIC_PRI1_INT5_S 8 +#define NVIC_PRI1_INT4_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI2 register. +// +//***************************************************************************** +#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask +#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask +#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask +#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask +#define NVIC_PRI2_INT11_S 24 +#define NVIC_PRI2_INT10_S 16 +#define NVIC_PRI2_INT9_S 8 +#define NVIC_PRI2_INT8_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI3 register. +// +//***************************************************************************** +#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask +#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask +#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask +#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask +#define NVIC_PRI3_INT15_S 24 +#define NVIC_PRI3_INT14_S 16 +#define NVIC_PRI3_INT13_S 8 +#define NVIC_PRI3_INT12_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI4 register. +// +//***************************************************************************** +#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask +#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask +#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask +#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask +#define NVIC_PRI4_INT19_S 24 +#define NVIC_PRI4_INT18_S 16 +#define NVIC_PRI4_INT17_S 8 +#define NVIC_PRI4_INT16_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI5 register. +// +//***************************************************************************** +#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask +#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask +#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask +#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask +#define NVIC_PRI5_INT23_S 24 +#define NVIC_PRI5_INT22_S 16 +#define NVIC_PRI5_INT21_S 8 +#define NVIC_PRI5_INT20_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI6 register. +// +//***************************************************************************** +#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask +#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask +#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask +#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask +#define NVIC_PRI6_INT27_S 24 +#define NVIC_PRI6_INT26_S 16 +#define NVIC_PRI6_INT25_S 8 +#define NVIC_PRI6_INT24_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI7 register. +// +//***************************************************************************** +#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask +#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask +#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask +#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask +#define NVIC_PRI7_INT31_S 24 +#define NVIC_PRI7_INT30_S 16 +#define NVIC_PRI7_INT29_S 8 +#define NVIC_PRI7_INT28_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_CPUID register. +// +//***************************************************************************** +#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer +#define NVIC_CPUID_VAR_M 0x00F00000 // Variant +#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number +#define NVIC_CPUID_REV_M 0x0000000F // Revision + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_INT_CTRL register. +// +//***************************************************************************** +#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI +#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV +#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV +#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling +#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending +#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception +#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base +#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception +#define NVIC_INT_CTRL_VEC_PEN_S 12 +#define NVIC_INT_CTRL_VEC_ACT_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_VTABLE register. +// +//***************************************************************************** +#define NVIC_VTABLE_BASE 0x20000000 // Vector table base +#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset +#define NVIC_VTABLE_OFFSET_S 8 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_APINT register. +// +//***************************************************************************** +#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask +#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key +#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess +#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group +#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split +#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split +#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split +#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split +#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split +#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split +#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split +#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split +#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request +#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info +#define NVIC_APINT_VECT_RESET 0x00000001 // System reset + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend +#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable +#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_CFG_CTRL register. +// +//***************************************************************************** +#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault +#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0 +#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access +#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger +#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger +#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_PRI1 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler +#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler +#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler +#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler +#define NVIC_SYS_PRI1_USAGE_S 16 +#define NVIC_SYS_PRI1_BUS_S 8 +#define NVIC_SYS_PRI1_MEM_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_PRI2 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler +#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers +#define NVIC_SYS_PRI2_SVC_S 24 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_PRI3 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler +#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler +#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler +#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler +#define NVIC_SYS_PRI3_TICK_S 24 +#define NVIC_SYS_PRI3_PENDSV_S 16 +#define NVIC_SYS_PRI3_DEBUG_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_HND_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable +#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable +#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable +#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended +#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended +#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active +#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active +#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active +#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active +#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active +#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active +#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_FAULT_STAT register. +// +//***************************************************************************** +#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault +#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault +#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault +#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault +#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault +#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault +#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid +#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault +#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault +#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error +#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error +#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault +#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid +#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation +#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation +#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation +#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_HFAULT_STAT register. +// +//***************************************************************************** +#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event +#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler +#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DEBUG_STAT register. +// +//***************************************************************************** +#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted +#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch +#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match +#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction +#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MM_ADDR register. +// +//***************************************************************************** +#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address +#define NVIC_MM_ADDR_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_FAULT_ADDR register. +// +//***************************************************************************** +#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address +#define NVIC_FAULT_ADDR_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_EXC_STACK register. +// +//***************************************************************************** +#define NVIC_EXC_STACK_DEEP 0x00000001 // Exception stack + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_EXC_NUM register. +// +//***************************************************************************** +#define NVIC_EXC_NUM_M 0x000003FF // Exception number +#define NVIC_EXC_NUM_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_COPRO register. +// +//***************************************************************************** +#define NVIC_COPRO_15_M 0xC0000000 // Coprocessor 15 access mask +#define NVIC_COPRO_15_DENIED 0x00000000 // Coprocessor 15 access denied +#define NVIC_COPRO_15_PRIV 0x40000000 // Coprocessor 15 privileged addess +#define NVIC_COPRO_15_FULL 0xC0000000 // Coprocessor 15 full access +#define NVIC_COPRO_14_M 0x30000000 // Coprocessor 14 access mask +#define NVIC_COPRO_14_DENIED 0x00000000 // Coprocessor 14 access denied +#define NVIC_COPRO_14_PRIV 0x10000000 // Coprocessor 14 privileged addess +#define NVIC_COPRO_14_FULL 0x30000000 // Coprocessor 14 full access +#define NVIC_COPRO_13_M 0x0C000000 // Coprocessor 13 access mask +#define NVIC_COPRO_13_DENIED 0x00000000 // Coprocessor 13 access denied +#define NVIC_COPRO_13_PRIV 0x04000000 // Coprocessor 13 privileged addess +#define NVIC_COPRO_13_FULL 0x0C000000 // Coprocessor 13 full access +#define NVIC_COPRO_12_M 0x03000000 // Coprocessor 12 access mask +#define NVIC_COPRO_12_DENIED 0x00000000 // Coprocessor 12 access denied +#define NVIC_COPRO_12_PRIV 0x01000000 // Coprocessor 12 privileged addess +#define NVIC_COPRO_12_FULL 0x03000000 // Coprocessor 12 full access +#define NVIC_COPRO_11_M 0x00C00000 // Coprocessor 11 access mask +#define NVIC_COPRO_11_DENIED 0x00000000 // Coprocessor 11 access denied +#define NVIC_COPRO_11_PRIV 0x00400000 // Coprocessor 11 privileged addess +#define NVIC_COPRO_11_FULL 0x00C00000 // Coprocessor 11 full access +#define NVIC_COPRO_10_M 0x00300000 // Coprocessor 10 access mask +#define NVIC_COPRO_10_DENIED 0x00000000 // Coprocessor 10 access denied +#define NVIC_COPRO_10_PRIV 0x00100000 // Coprocessor 10 privileged addess +#define NVIC_COPRO_10_FULL 0x00300000 // Coprocessor 10 full access +#define NVIC_COPRO_9_M 0x000C0000 // Coprocessor 9 access mask +#define NVIC_COPRO_9_DENIED 0x00000000 // Coprocessor 9 access denied +#define NVIC_COPRO_9_PRIV 0x00040000 // Coprocessor 9 privileged addess +#define NVIC_COPRO_9_FULL 0x000C0000 // Coprocessor 9 full access +#define NVIC_COPRO_8_M 0x00030000 // Coprocessor 8 access mask +#define NVIC_COPRO_8_DENIED 0x00000000 // Coprocessor 8 access denied +#define NVIC_COPRO_8_PRIV 0x00010000 // Coprocessor 8 privileged addess +#define NVIC_COPRO_8_FULL 0x00030000 // Coprocessor 8 full access +#define NVIC_COPRO_7_M 0x0000C000 // Coprocessor 7 access mask +#define NVIC_COPRO_7_DENIED 0x00000000 // Coprocessor 7 access denied +#define NVIC_COPRO_7_PRIV 0x00004000 // Coprocessor 7 privileged addess +#define NVIC_COPRO_7_FULL 0x0000C000 // Coprocessor 7 full access +#define NVIC_COPRO_6_M 0x00003000 // Coprocessor 6 access mask +#define NVIC_COPRO_6_DENIED 0x00000000 // Coprocessor 6 access denied +#define NVIC_COPRO_6_PRIV 0x00001000 // Coprocessor 6 privileged addess +#define NVIC_COPRO_6_FULL 0x00003000 // Coprocessor 6 full access +#define NVIC_COPRO_5_M 0x00000C00 // Coprocessor 5 access mask +#define NVIC_COPRO_5_DENIED 0x00000000 // Coprocessor 5 access denied +#define NVIC_COPRO_5_PRIV 0x00000400 // Coprocessor 5 privileged addess +#define NVIC_COPRO_5_FULL 0x00000C00 // Coprocessor 5 full access +#define NVIC_COPRO_4_M 0x00000300 // Coprocessor 4 access mask +#define NVIC_COPRO_4_DENIED 0x00000000 // Coprocessor 4 access denied +#define NVIC_COPRO_4_PRIV 0x00000100 // Coprocessor 4 privileged addess +#define NVIC_COPRO_4_FULL 0x00000300 // Coprocessor 4 full access +#define NVIC_COPRO_3_M 0x000000C0 // Coprocessor 3 access mask +#define NVIC_COPRO_3_DENIED 0x00000000 // Coprocessor 3 access denied +#define NVIC_COPRO_3_PRIV 0x00000040 // Coprocessor 3 privileged addess +#define NVIC_COPRO_3_FULL 0x000000C0 // Coprocessor 3 full access +#define NVIC_COPRO_2_M 0x00000030 // Coprocessor 2 access mask +#define NVIC_COPRO_2_DENIED 0x00000000 // Coprocessor 2 access denied +#define NVIC_COPRO_2_PRIV 0x00000010 // Coprocessor 2 privileged addess +#define NVIC_COPRO_2_FULL 0x00000030 // Coprocessor 2 full access +#define NVIC_COPRO_1_M 0x0000000C // Coprocessor 1 access mask +#define NVIC_COPRO_1_DENIED 0x00000000 // Coprocessor 1 access denied +#define NVIC_COPRO_1_PRIV 0x00000004 // Coprocessor 1 privileged addess +#define NVIC_COPRO_1_FULL 0x0000000C // Coprocessor 1 full access +#define NVIC_COPRO_0_M 0x00000003 // Coprocessor 0 access mask +#define NVIC_COPRO_0_DENIED 0x00000000 // Coprocessor 0 access denied +#define NVIC_COPRO_0_PRIV 0x00000001 // Coprocessor 0 privileged addess +#define NVIC_COPRO_0_FULL 0x00000003 // Coprocessor 0 full access + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_TYPE register. +// +//***************************************************************************** +#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions +#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions +#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU +#define NVIC_MPU_TYPE_IREGION_S 16 +#define NVIC_MPU_TYPE_DREGION_S 8 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_CTRL register. +// +//***************************************************************************** +#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults +#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_NUMBER register. +// +//***************************************************************************** +#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access +#define NVIC_MPU_NUMBER_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_BASE register. +// +//***************************************************************************** +#define NVIC_MPU_BASE_ADDR_M 0xFFFFFF00 // Base address +#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid +#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number +#define NVIC_MPU_BASE_ADDR_S 8 +#define NVIC_MPU_BASE_REGION_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_ATTR register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR_ATTRS 0xFFFF0000 // Attributes +#define NVIC_MPU_ATTR_SRD 0x0000FF00 // Sub-region disable +#define NVIC_MPU_ATTR_SZENABLE 0x000000FF // Region size + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_CTRL register. +// +//***************************************************************************** +#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask +#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key +#define NVIC_DBG_CTRL_MON_PEND 0x00008000 // Pend the monitor +#define NVIC_DBG_CTRL_MON_REQ 0x00004000 // Monitor request +#define NVIC_DBG_CTRL_MON_EN 0x00002000 // Debug monitor enable +#define NVIC_DBG_CTRL_MONSTEP 0x00001000 // Monitor step the core +#define NVIC_DBG_CTRL_S_SLEEP 0x00000400 // Core is sleeping +#define NVIC_DBG_CTRL_S_HALT 0x00000200 // Core status on halt +#define NVIC_DBG_CTRL_S_REGRDY 0x00000100 // Register read/write available +#define NVIC_DBG_CTRL_S_LOCKUP 0x00000080 // Core is locked up +#define NVIC_DBG_CTRL_C_RESET 0x00000010 // Reset the core +#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping +#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core +#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core +#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_XFER register. +// +//***************************************************************************** +#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read +#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register +#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 +#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 +#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 +#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 +#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 +#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 +#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 +#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 +#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 +#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 +#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 +#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 +#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 +#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 +#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 +#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 +#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register +#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP +#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP +#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP +#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_DATA register. +// +//***************************************************************************** +#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache +#define NVIC_DBG_DATA_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_INT register. +// +//***************************************************************************** +#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault +#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors +#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error +#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state +#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check +#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error +#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault +#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status +#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset +#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending +#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SW_TRIG register. +// +//***************************************************************************** +#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger +#define NVIC_SW_TRIG_INTID_S 0 + +#endif // __HW_NVIC_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_pwm.h b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_pwm.h new file mode 100644 index 000000000..a324eaa90 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_pwm.h @@ -0,0 +1,260 @@ +//***************************************************************************** +// +// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_PWM_H__ +#define __HW_PWM_H__ + +//***************************************************************************** +// +// PWM Module Register Offsets. +// +//***************************************************************************** +#define PWM_O_CTL 0x00000000 // PWM Master Control register +#define PWM_O_SYNC 0x00000004 // PWM Time Base Sync register +#define PWM_O_ENABLE 0x00000008 // PWM Output Enable register +#define PWM_O_INVERT 0x0000000C // PWM Output Inversion register +#define PWM_O_FAULT 0x00000010 // PWM Output Fault register +#define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable register +#define PWM_O_RIS 0x00000018 // PWM Interrupt Raw Status reg. +#define PWM_O_ISC 0x0000001C // PWM Interrupt Status register +#define PWM_O_STATUS 0x00000020 // PWM Status register + +//***************************************************************************** +// +// The following define the bit fields in the PWM Master Control register. +// +//***************************************************************************** +#define PWM_CTL_GLOBAL_SYNC2 0x00000004 // Global sync generator 2 +#define PWM_CTL_GLOBAL_SYNC1 0x00000002 // Global sync generator 1 +#define PWM_CTL_GLOBAL_SYNC0 0x00000001 // Global sync generator 0 + +//***************************************************************************** +// +// The following define the bit fields in the PWM Time Base Sync register. +// +//***************************************************************************** +#define PWM_SYNC_SYNC2 0x00000004 // Reset generator 2 counter +#define PWM_SYNC_SYNC1 0x00000002 // Reset generator 1 counter +#define PWM_SYNC_SYNC0 0x00000001 // Reset generator 0 counter + +//***************************************************************************** +// +// The following define the bit fields in the PWM Output Enable register. +// +//***************************************************************************** +#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 pin enable +#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 pin enable +#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 pin enable +#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 pin enable +#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 pin enable +#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 pin enable + +//***************************************************************************** +// +// The following define the bit fields in the PWM Inversion register. +// +//***************************************************************************** +#define PWM_INVERT_PWM5INV 0x00000020 // PWM5 pin invert +#define PWM_INVERT_PWM4INV 0x00000010 // PWM4 pin invert +#define PWM_INVERT_PWM3INV 0x00000008 // PWM3 pin invert +#define PWM_INVERT_PWM2INV 0x00000004 // PWM2 pin invert +#define PWM_INVERT_PWM1INV 0x00000002 // PWM1 pin invert +#define PWM_INVERT_PWM0INV 0x00000001 // PWM0 pin invert + +//***************************************************************************** +// +// The following define the bit fields in the PWM Fault register. +// +//***************************************************************************** +#define PWM_FAULT_FAULT5 0x00000020 // PWM5 pin fault +#define PWM_FAULT_FAULT4 0x00000010 // PWM5 pin fault +#define PWM_FAULT_FAULT3 0x00000008 // PWM5 pin fault +#define PWM_FAULT_FAULT2 0x00000004 // PWM5 pin fault +#define PWM_FAULT_FAULT1 0x00000002 // PWM5 pin fault +#define PWM_FAULT_FAULT0 0x00000001 // PWM5 pin fault + +//***************************************************************************** +// +// PWM Interrupt Register bit definitions. +// +//***************************************************************************** +#define PWM_INT_INTFAULT 0x00010000 // Fault interrupt pending + +//***************************************************************************** +// +// The following define the bit fields in the PWM Status register. +// +//***************************************************************************** +#define PWM_STATUS_FAULT 0x00000001 // Fault status + +//***************************************************************************** +// +// PWM Generator standard offsets. +// +//***************************************************************************** +#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base +#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base +#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base + +#define PWM_O_X_CTL 0x00000000 // Gen Control Reg +#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg +#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg +#define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg +#define PWM_O_X_LOAD 0x00000010 // Gen Load Reg +#define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg +#define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg +#define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg +#define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg +#define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg +#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg +#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg +#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg + +//***************************************************************************** +// +// PWM_X Control Register bit definitions. +// +//***************************************************************************** +#define PWM_X_CTL_ENABLE 0x00000001 // Master enable for gen block +#define PWM_X_CTL_MODE 0x00000002 // Counter mode, down or up/down +#define PWM_X_CTL_DEBUG 0x00000004 // Debug mode +#define PWM_X_CTL_LOADUPD 0x00000008 // Update mode for the load reg +#define PWM_X_CTL_CMPAUPD 0x00000010 // Update mode for comp A reg +#define PWM_X_CTL_CMPBUPD 0x00000020 // Update mode for comp B reg + +//***************************************************************************** +// +// PWM_X Interrupt/Trigger Enable Register bit definitions. +// +//***************************************************************************** +#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Int if COUNT = 0 +#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Int if COUNT = LOAD +#define PWM_X_INTEN_INTCMPAU 0x00000004 // Int if COUNT = CMPA U +#define PWM_X_INTEN_INTCMPAD 0x00000008 // Int if COUNT = CMPA D +#define PWM_X_INTEN_INTCMPBU 0x00000010 // Int if COUNT = CMPA U +#define PWM_X_INTEN_INTCMPBD 0x00000020 // Int if COUNT = CMPA D +#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trig if COUNT = 0 +#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trig if COUNT = LOAD +#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trig if COUNT = CMPA U +#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trig if COUNT = CMPA D +#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trig if COUNT = CMPA U +#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trig if COUNT = CMPA D + +//***************************************************************************** +// +// PWM_X Raw Interrupt Status Register bit definitions. +// +//***************************************************************************** +#define PWM_X_RIS_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 int +#define PWM_X_RIS_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD int +#define PWM_X_RIS_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U int +#define PWM_X_RIS_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D int +#define PWM_X_RIS_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U int +#define PWM_X_RIS_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D int + +//***************************************************************************** +// +// PWM_X Interrupt Status Register bit definitions. +// +//***************************************************************************** +#define PWM_X_INT_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 received +#define PWM_X_INT_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD rcvd +#define PWM_X_INT_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U rcvd +#define PWM_X_INT_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D rcvd +#define PWM_X_INT_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U rcvd +#define PWM_X_INT_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D rcvd + +//***************************************************************************** +// +// PWM_X Generator A/B Control Register bit definitions. +// +//***************************************************************************** +#define PWM_X_GEN_Y_ACTZERO 0x00000003 // Act PWM_X_COUNT = 0 +#define PWM_X_GEN_Y_ACTLOAD 0x0000000C // Act PWM_X_COUNT = PWM_X_LOAD +#define PWM_X_GEN_Y_ACTCMPAU 0x00000030 // Act PWM_X_COUNT = PWM_X_CMPA U +#define PWM_X_GEN_Y_ACTCMPAD 0x000000C0 // Act PWM_X_COUNT = PWM_X_CMPA D +#define PWM_X_GEN_Y_ACTCMPBU 0x00000300 // Act PWM_X_COUNT = PWM_X_CMPB U +#define PWM_X_GEN_Y_ACTCMPBD 0x00000C00 // Act PWM_X_COUNT = PWM_X_CMPB D + +//***************************************************************************** +// +// PWM_X Generator A/B Control Register action definitions. +// +//***************************************************************************** +#define PWM_GEN_ACT_NONE 0x0 // Do nothing +#define PWM_GEN_ACT_INV 0x1 // Invert the output signal +#define PWM_GEN_ACT_ZERO 0x2 // Set the output signal to zero +#define PWM_GEN_ACT_ONE 0x3 // Set the output signal to one +#define PWM_GEN_ACT_ZERO_SHIFT 0 // Shift amount for the zero action +#define PWM_GEN_ACT_LOAD_SHIFT 2 // Shift amount for the load action +#define PWM_GEN_ACT_A_UP_SHIFT 4 // Shift amount for the A up action +#define PWM_GEN_ACT_A_DN_SHIFT 6 // Shift amount for the A dn action +#define PWM_GEN_ACT_B_UP_SHIFT 8 // Shift amount for the B up action +#define PWM_GEN_ACT_B_DN_SHIFT 10 // Shift amount for the B dn action + +//***************************************************************************** +// +// PWM_X Dead Band Control Register bit definitions. +// +//***************************************************************************** +#define PWM_DBCTL_ENABLE 0x00000001 // Enable dead band insertion + +//***************************************************************************** +// +// PWM Register reset values. +// +//***************************************************************************** +#define PWM_RV_CTL 0x00000000 // Master control of the PWM module +#define PWM_RV_SYNC 0x00000000 // Counter synch for PWM generators +#define PWM_RV_ENABLE 0x00000000 // Master enable for the PWM + // output pins +#define PWM_RV_INVERT 0x00000000 // Inversion control for + // PWM output pins +#define PWM_RV_FAULT 0x00000000 // Fault handling for the PWM + // output pins +#define PWM_RV_INTEN 0x00000000 // Interrupt enable +#define PWM_RV_RIS 0x00000000 // Raw interrupt status +#define PWM_RV_ISC 0x00000000 // Interrupt status and clearing +#define PWM_RV_STATUS 0x00000000 // Status +#define PWM_RV_X_CTL 0x00000000 // Master control of the PWM + // generator block +#define PWM_RV_X_INTEN 0x00000000 // Interrupt and trigger enable +#define PWM_RV_X_RIS 0x00000000 // Raw interrupt status +#define PWM_RV_X_ISC 0x00000000 // Interrupt status and clearing +#define PWM_RV_X_LOAD 0x00000000 // The load value for the counter +#define PWM_RV_X_COUNT 0x00000000 // The current counter value +#define PWM_RV_X_CMPA 0x00000000 // The comparator A value +#define PWM_RV_X_CMPB 0x00000000 // The comparator B value +#define PWM_RV_X_GENA 0x00000000 // Controls PWM generator A +#define PWM_RV_X_GENB 0x00000000 // Controls PWM generator B +#define PWM_RV_X_DBCTL 0x00000000 // Control the dead band generator +#define PWM_RV_X_DBRISE 0x00000000 // The dead band rising edge delay + // count +#define PWM_RV_X_DBFALL 0x00000000 // The dead band falling edge delay + // count + +#endif // __HW_PWM_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_qei.h b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_qei.h new file mode 100644 index 000000000..64ebcd18e --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_qei.h @@ -0,0 +1,176 @@ +//***************************************************************************** +// +// hw_qei.h - Macros used when accessing the QEI hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_QEI_H__ +#define __HW_QEI_H__ + +//***************************************************************************** +// +// The following define the offsets of the QEI registers. +// +//***************************************************************************** +#define QEI_O_CTL 0x00000000 // Configuration and control reg. +#define QEI_O_STAT 0x00000004 // Status register +#define QEI_O_POS 0x00000008 // Current position register +#define QEI_O_MAXPOS 0x0000000C // Maximum position register +#define QEI_O_LOAD 0x00000010 // Velocity timer load register +#define QEI_O_TIME 0x00000014 // Velocity timer register +#define QEI_O_COUNT 0x00000018 // Velocity pulse count register +#define QEI_O_SPEED 0x0000001C // Velocity speed register +#define QEI_O_INTEN 0x00000020 // Interrupt enable register +#define QEI_O_RIS 0x00000024 // Raw interrupt status register +#define QEI_O_ISC 0x00000028 // Interrupt status register + +//***************************************************************************** +// +// The following define the bit fields in the QEI_CTL register. +// +//***************************************************************************** +#define QEI_CTL_STALLEN 0x00001000 // Stall enable +#define QEI_CTL_INVI 0x00000800 // Invert Index input +#define QEI_CTL_INVB 0x00000400 // Invert PhB input +#define QEI_CTL_INVA 0x00000200 // Invert PhA input +#define QEI_CTL_VELDIV_M 0x000001C0 // Velocity predivider mask +#define QEI_CTL_VELDIV_1 0x00000000 // Predivide by 1 +#define QEI_CTL_VELDIV_2 0x00000040 // Predivide by 2 +#define QEI_CTL_VELDIV_4 0x00000080 // Predivide by 4 +#define QEI_CTL_VELDIV_8 0x000000C0 // Predivide by 8 +#define QEI_CTL_VELDIV_16 0x00000100 // Predivide by 16 +#define QEI_CTL_VELDIV_32 0x00000140 // Predivide by 32 +#define QEI_CTL_VELDIV_64 0x00000180 // Predivide by 64 +#define QEI_CTL_VELDIV_128 0x000001C0 // Predivide by 128 +#define QEI_CTL_VELEN 0x00000020 // Velocity enable +#define QEI_CTL_RESMODE 0x00000010 // Position counter reset mode +#define QEI_CTL_CAPMODE 0x00000008 // Edge capture mode +#define QEI_CTL_SIGMODE 0x00000004 // Encoder signaling mode +#define QEI_CTL_SWAP 0x00000002 // Swap input signals +#define QEI_CTL_ENABLE 0x00000001 // QEI enable + +//***************************************************************************** +// +// The following define the bit fields in the QEI_STAT register. +// +//***************************************************************************** +#define QEI_STAT_DIRECTION 0x00000002 // Direction of rotation +#define QEI_STAT_ERROR 0x00000001 // Signalling error detected + +//***************************************************************************** +// +// The following define the bit fields in the QEI_POS register. +// +//***************************************************************************** +#define QEI_POS_M 0xFFFFFFFF // Current encoder position +#define QEI_POS_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the QEI_MAXPOS register. +// +//***************************************************************************** +#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum encoder position +#define QEI_MAXPOS_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the QEI_LOAD register. +// +//***************************************************************************** +#define QEI_LOAD_M 0xFFFFFFFF // Velocity timer load value +#define QEI_LOAD_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the QEI_TIME register. +// +//***************************************************************************** +#define QEI_TIME_M 0xFFFFFFFF // Velocity timer current value +#define QEI_TIME_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the QEI_COUNT register. +// +//***************************************************************************** +#define QEI_COUNT_M 0xFFFFFFFF // Encoder running pulse count +#define QEI_COUNT_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the QEI_SPEED register. +// +//***************************************************************************** +#define QEI_SPEED_M 0xFFFFFFFF // Encoder pulse count +#define QEI_SPEED_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the QEI_INTEN register. +// +//***************************************************************************** +#define QEI_INTEN_ERROR 0x00000008 // Phase error detected +#define QEI_INTEN_DIR 0x00000004 // Direction change +#define QEI_INTEN_TIMER 0x00000002 // Velocity timer expired +#define QEI_INTEN_INDEX 0x00000001 // Index pulse detected + +//***************************************************************************** +// +// The following define the bit fields in the QEI_RIS register. +// +//***************************************************************************** +#define QEI_RIS_ERROR 0x00000008 // Phase error detected +#define QEI_RIS_DIR 0x00000004 // Direction change +#define QEI_RIS_TIMER 0x00000002 // Velocity timer expired +#define QEI_RIS_INDEX 0x00000001 // Index pulse detected + +//***************************************************************************** +// +// The following define the bit fields in the QEI_ISC register. +// +//***************************************************************************** +#define QEI_INT_ERROR 0x00000008 // Phase error detected +#define QEI_INT_DIR 0x00000004 // Direction change +#define QEI_INT_TIMER 0x00000002 // Velocity timer expired +#define QEI_INT_INDEX 0x00000001 // Index pulse detected + +//***************************************************************************** +// +// The following define the reset values for the QEI registers. +// +//***************************************************************************** +#define QEI_RV_CTL 0x00000000 // Configuration and control reg. +#define QEI_RV_STAT 0x00000000 // Status register +#define QEI_RV_POS 0x00000000 // Current position register +#define QEI_RV_MAXPOS 0x00000000 // Maximum position register +#define QEI_RV_LOAD 0x00000000 // Velocity timer load register +#define QEI_RV_TIME 0x00000000 // Velocity timer register +#define QEI_RV_COUNT 0x00000000 // Velocity pulse count register +#define QEI_RV_SPEED 0x00000000 // Velocity speed register +#define QEI_RV_INTEN 0x00000000 // Interrupt enable register +#define QEI_RV_RIS 0x00000000 // Raw interrupt status register +#define QEI_RV_ISC 0x00000000 // Interrupt status register + +#endif // __HW_QEI_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_ssi.h b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_ssi.h new file mode 100644 index 000000000..9ebf6279a --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_ssi.h @@ -0,0 +1,120 @@ +//***************************************************************************** +// +// hw_ssi.h - Macros used when accessing the SSI hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_SSI_H__ +#define __HW_SSI_H__ + +//***************************************************************************** +// +// The following define the offsets of the SSI registers. +// +//***************************************************************************** +#define SSI_O_CR0 0x00000000 // Control register 0 +#define SSI_O_CR1 0x00000004 // Control register 1 +#define SSI_O_DR 0x00000008 // Data register +#define SSI_O_SR 0x0000000C // Status register +#define SSI_O_CPSR 0x00000010 // Clock prescale register +#define SSI_O_IM 0x00000014 // Int mask set and clear register +#define SSI_O_RIS 0x00000018 // Raw interrupt register +#define SSI_O_MIS 0x0000001C // Masked interrupt register +#define SSI_O_ICR 0x00000020 // Interrupt clear register + +//***************************************************************************** +// +// The following define the bit fields in the SSI Control register 0. +// +//***************************************************************************** +#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate +#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase +#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity +#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask +#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format +#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format +#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format +#define SSI_CR0_DSS 0x0000000F // Data size select +#define SSI_CR0_DSS_4 0x00000003 // 4 bit data +#define SSI_CR0_DSS_5 0x00000004 // 5 bit data +#define SSI_CR0_DSS_6 0x00000005 // 6 bit data +#define SSI_CR0_DSS_7 0x00000006 // 7 bit data +#define SSI_CR0_DSS_8 0x00000007 // 8 bit data +#define SSI_CR0_DSS_9 0x00000008 // 9 bit data +#define SSI_CR0_DSS_10 0x00000009 // 10 bit data +#define SSI_CR0_DSS_11 0x0000000A // 11 bit data +#define SSI_CR0_DSS_12 0x0000000B // 12 bit data +#define SSI_CR0_DSS_13 0x0000000C // 13 bit data +#define SSI_CR0_DSS_14 0x0000000D // 14 bit data +#define SSI_CR0_DSS_15 0x0000000E // 15 bit data +#define SSI_CR0_DSS_16 0x0000000F // 16 bit data + +//***************************************************************************** +// +// The following define the bit fields in the SSI Control register 1. +// +//***************************************************************************** +#define SSI_CR1_SOD 0x00000008 // Slave mode output disable +#define SSI_CR1_MS 0x00000004 // Master or slave mode select +#define SSI_CR1_SSE 0x00000002 // Sync serial port enable +#define SSI_CR1_LBM 0x00000001 // Loopback mode + +//***************************************************************************** +// +// The following define the bit fields in the SSI Status register. +// +//***************************************************************************** +#define SSI_SR_BSY 0x00000010 // SSI busy +#define SSI_SR_RFF 0x00000008 // RX FIFO full +#define SSI_SR_RNE 0x00000004 // RX FIFO not empty +#define SSI_SR_TNF 0x00000002 // TX FIFO not full +#define SSI_SR_TFE 0x00000001 // TX FIFO empty + +//***************************************************************************** +// +// The following define the bit fields in the SSI clock prescale register. +// +//***************************************************************************** +#define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale + +//***************************************************************************** +// +// The following define information concerning the SSI Data register. +// +//***************************************************************************** +#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO +#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO + +//***************************************************************************** +// +// The following define the bit fields in the interrupt mask set and clear, +// raw interrupt, masked interrupt, and interrupt clear registers. +// +//***************************************************************************** +#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt +#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt +#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt +#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt + +#endif // __HW_SSI_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_sysctl.h b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_sysctl.h new file mode 100644 index 000000000..5ac87f228 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_sysctl.h @@ -0,0 +1,409 @@ +//***************************************************************************** +// +// hw_sysctl.h - Macros used when accessing the system control hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_SYSCTL_H__ +#define __HW_SYSCTL_H__ + +//***************************************************************************** +// +// The following define the offsets of the system control registers. +// +//***************************************************************************** +#define SYSCTL_DID0 0x400fe000 // Device identification register 0 +#define SYSCTL_DID1 0x400fe004 // Device identification register 1 +#define SYSCTL_DC0 0x400fe008 // Device capabilities register 0 +#define SYSCTL_DC1 0x400fe010 // Device capabilities register 1 +#define SYSCTL_DC2 0x400fe014 // Device capabilities register 2 +#define SYSCTL_DC3 0x400fe018 // Device capabilities register 3 +#define SYSCTL_DC4 0x400fe01C // Device capabilities register 4 +#define SYSCTL_PBORCTL 0x400fe030 // POR/BOR reset control register +#define SYSCTL_LDOPCTL 0x400fe034 // LDO power control register +#define SYSCTL_SRCR0 0x400fe040 // Software reset control reg 0 +#define SYSCTL_SRCR1 0x400fe044 // Software reset control reg 1 +#define SYSCTL_SRCR2 0x400fe048 // Software reset control reg 2 +#define SYSCTL_RIS 0x400fe050 // Raw interrupt status register +#define SYSCTL_IMC 0x400fe054 // Interrupt mask/control register +#define SYSCTL_MISC 0x400fe058 // Interrupt status register +#define SYSCTL_RESC 0x400fe05c // Reset cause register +#define SYSCTL_RCC 0x400fe060 // Run-mode clock config register +#define SYSCTL_PLLCFG 0x400fe064 // PLL configuration register +#define SYSCTL_RCGC0 0x400fe100 // Run-mode clock gating register 0 +#define SYSCTL_RCGC1 0x400fe104 // Run-mode clock gating register 1 +#define SYSCTL_RCGC2 0x400fe108 // Run-mode clock gating register 2 +#define SYSCTL_SCGC0 0x400fe110 // Sleep-mode clock gating reg 0 +#define SYSCTL_SCGC1 0x400fe114 // Sleep-mode clock gating reg 1 +#define SYSCTL_SCGC2 0x400fe118 // Sleep-mode clock gating reg 2 +#define SYSCTL_DCGC0 0x400fe120 // Deep Sleep-mode clock gate reg 0 +#define SYSCTL_DCGC1 0x400fe124 // Deep Sleep-mode clock gate reg 1 +#define SYSCTL_DCGC2 0x400fe128 // Deep Sleep-mode clock gate reg 2 +#define SYSCTL_CLKVCLR 0x400fe150 // Clock verifcation clear register +#define SYSCTL_LDOARST 0x400fe160 // LDO reset control register + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DID0 register. +// +//***************************************************************************** +#define SYSCTL_DID0_VER_MASK 0x70000000 // DID0 version mask +#define SYSCTL_DID0_VER_0 0x00000000 // DID0 version 0 +#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask +#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A +#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B +#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask +#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0 +#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DID1 register. +// +//***************************************************************************** +#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask +#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask +#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family +#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask +#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101 +#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102 +#define SYSCTL_DID1_PRTNO_301 0x00110000 // LM3S301 +#define SYSCTL_DID1_PRTNO_310 0x00120000 // LM3S310 +#define SYSCTL_DID1_PRTNO_315 0x00130000 // LM3S315 +#define SYSCTL_DID1_PRTNO_316 0x00140000 // LM3S316 +#define SYSCTL_DID1_PRTNO_328 0x00150000 // LM3S328 +#define SYSCTL_DID1_PRTNO_601 0x00210000 // LM3S601 +#define SYSCTL_DID1_PRTNO_610 0x00220000 // LM3S610 +#define SYSCTL_DID1_PRTNO_611 0x00230000 // LM3S611 +#define SYSCTL_DID1_PRTNO_612 0x00240000 // LM3S612 +#define SYSCTL_DID1_PRTNO_613 0x00250000 // LM3S613 +#define SYSCTL_DID1_PRTNO_615 0x00260000 // LM3S615 +#define SYSCTL_DID1_PRTNO_628 0x00270000 // LM3S628 +#define SYSCTL_DID1_PRTNO_801 0x00310000 // LM3S801 +#define SYSCTL_DID1_PRTNO_811 0x00320000 // LM3S811 +#define SYSCTL_DID1_PRTNO_812 0x00330000 // LM3S812 +#define SYSCTL_DID1_PRTNO_815 0x00340000 // LM3S815 +#define SYSCTL_DID1_PRTNO_828 0x00350000 // LM3S828 +#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask +#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C) +#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C) +#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask +#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC +#define SYSCTL_DID1_PKG_48QFP 0x00000008 // 48-pin QFP +#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant +#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask +#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified) +#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified) +#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified +#define SYSCTL_DID1_PRTNO_SHIFT 16 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC0 register. +// +//***************************************************************************** +#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask +#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2kB of SRAM +#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4kB of SRAM +#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8kB of SRAM +#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask +#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8kB of flash +#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16kB of flash +#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32kB of flash +#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64kB of flash + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC1 register. +// +//***************************************************************************** +#define SYSCTL_DC1_PWM 0x00100000 // PWM module present +#define SYSCTL_DC1_ADC 0x00010000 // ADC module present +#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask +#define SYSCTL_DC1_ADCSPD_MASK 0x00000F00 // ADC speed mask +#define SYSCTL_DC1_ADCSPD_1M 0x00000300 // 1Msps ADC +#define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500Ksps ADC +#define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250Ksps ADC +#define SYSCTL_DC1_ADCSPD_125K 0x00000000 // 125Ksps ADC +#define SYSCTL_DC1_MPU 0x00000080 // Cortex M3 MPU present +#define SYSCTL_DC1_TEMP 0x00000020 // Temperature sensor present +#define SYSCTL_DC1_PLL 0x00000010 // PLL present +#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present +#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present +#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present +#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC2 register. +// +//***************************************************************************** +#define SYSCTL_DC2_COMP2 0x04000000 // Analog comparator 2 present +#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present +#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present +#define SYSCTL_DC2_TIMER2 0x00040000 // Timer 2 present +#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present +#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present +#define SYSCTL_DC2_I2C 0x00001000 // I2C present +#define SYSCTL_DC2_QEI 0x00000100 // QEI present +#define SYSCTL_DC2_SSI 0x00000010 // SSI present +#define SYSCTL_DC2_UART1 0x00000002 // UART 1 present +#define SYSCTL_DC2_UART0 0x00000001 // UART 0 present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC3 register. +// +//***************************************************************************** +#define SYSCTL_DC3_32KHZ 0x80000000 // 32kHz pin present +#define SYSCTL_DC3_CCP5 0x20000000 // CCP5 pin present +#define SYSCTL_DC3_CCP4 0x10000000 // CCP4 pin present +#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 pin present +#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 pin present +#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present +#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present +#define SYSCTL_DC3_ADC7 0x00800000 // ADC7 pin present +#define SYSCTL_DC3_ADC6 0x00400000 // ADC6 pin present +#define SYSCTL_DC3_ADC5 0x00200000 // ADC5 pin present +#define SYSCTL_DC3_ADC4 0x00100000 // ADC4 pin present +#define SYSCTL_DC3_ADC3 0x00080000 // ADC3 pin present +#define SYSCTL_DC3_ADC2 0x00040000 // ADC2 pin present +#define SYSCTL_DC3_ADC1 0x00020000 // ADC1 pin present +#define SYSCTL_DC3_ADC0 0x00010000 // ADC0 pin present +#define SYSCTL_DC3_C2O 0x00004000 // C2o pin present +#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ pin present +#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- pin present +#define SYSCTL_DC3_C1O 0x00000800 // C1o pin present +#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ pin present +#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present +#define SYSCTL_DC3_C0O 0x00000100 // C0o pin present +#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present +#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present +#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 pin present +#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 pin present +#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 pin present +#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 pin present +#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 pin present +#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 pin present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC4 register. +// +//***************************************************************************** +#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO port E present +#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO port D present +#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present +#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present +#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_PBORCTL register. +// +//***************************************************************************** +#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer +#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset +#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise +#define SYSCTL_PBORCTL_BOR_SH 2 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_LDOPCTL register. +// +//***************************************************************************** +#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask +#define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V +#define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V +#define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V +#define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V +#define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V +#define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V +#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V +#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V +#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V +#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V +#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_SRCR0, SYSCTL_RCGC0, +// SYSCTL_SCGC0, and SYSCTL_DCGC0 registers. +// +//***************************************************************************** +#define SYSCTL_SET0_PWM 0x00100000 // PWM module +#define SYSCTL_SET0_ADC 0x00010000 // ADC module +#define SYSCTL_SET0_ADCSPD_MASK 0x00000F00 // ADC speed mask +#define SYSCTL_SET0_ADCSPD_1M 0x00000300 // 1Msps ADC +#define SYSCTL_SET0_ADCSPD_500K 0x00000200 // 500Ksps ADC +#define SYSCTL_SET0_ADCSPD_250K 0x00000100 // 250Ksps ADC +#define SYSCTL_SET0_ADCSPD_125K 0x00000000 // 125Ksps ADC +#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_SRCR1, SYSCTL_RCGC1, +// SYSCTL_SCGC1, and SYSCTL_DCGC1 registers. +// +//***************************************************************************** +#define SYSCTL_SET1_COMP2 0x04000000 // Analog comparator module 2 +#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1 +#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0 +#define SYSCTL_SET1_TIMER2 0x00040000 // Timer module 2 +#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1 +#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0 +#define SYSCTL_SET1_I2C 0x00001000 // I2C module +#define SYSCTL_SET1_QEI 0x00000100 // QEI module +#define SYSCTL_SET1_SSI 0x00000010 // SSI module +#define SYSCTL_SET1_UART1 0x00000002 // UART module 1 +#define SYSCTL_SET1_UART0 0x00000001 // UART module 0 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_SRCR2, SYSCTL_RCGC2, +// SYSCTL_SCGC2, and SYSCTL_DCGC2 registers. +// +//***************************************************************************** +#define SYSCTL_SET2_GPIOE 0x00000010 // GPIO E module +#define SYSCTL_SET2_GPIOD 0x00000008 // GPIO D module +#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module +#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module +#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_RIS, SYSCTL_IMC, and +// SYSCTL_IMS registers. +// +//***************************************************************************** +#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt +#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt +#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int +#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int +#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt +#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt +#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_RESC register. +// +//***************************************************************************** +#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset +#define SYSCTL_RESC_SW 0x00000010 // Software reset +#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset +#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset +#define SYSCTL_RESC_POR 0x00000002 // Power on reset +#define SYSCTL_RESC_EXT 0x00000001 // External reset + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_RCC register. +// +//***************************************************************************** +#define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating +#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider +#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2 +#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3 +#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4 +#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5 +#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6 +#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7 +#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8 +#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9 +#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10 +#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11 +#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12 +#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13 +#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14 +#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15 +#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16 +#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider +#define SYSCTL_RCC_USE_PWMDIV 0x00100000 // Use PWM clock divider +#define SYSCTL_RCC_PWMDIV_MASK 0x000E0000 // PWM clock divider +#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2 +#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4 +#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8 +#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16 +#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32 +#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64 +#define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down +#define SYSCTL_RCC_OE 0x00001000 // PLL output enable +#define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass +#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable +#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc +#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal +#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864MHz crystal +#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4MHz crystal +#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal +#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal +#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal +#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal +#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal +#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal +#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal +#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal +#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal +#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select +#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator +#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // Use the internal oscillator +#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // Use the internal oscillator / 4 +#define SYSCTL_RCC_IOSCVER 0x00000008 // Int. osc. verification timer en +#define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en +#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal oscillator disable +#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable +#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field +#define SYSCTL_RCC_PWMDIV_SHIFT 17 // Shift to the PWMDIV field +#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field +#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_PLLCFG register. +// +//***************************************************************************** +#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider +#define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1 +#define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2 +#define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4 +#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier +#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider +#define SYSCTL_PLLCFG_F_SHIFT 5 +#define SYSCTL_PLLCFG_R_SHIFT 0 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_CLKVCLR register. +// +//***************************************************************************** +#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_LDOARST register. +// +//***************************************************************************** +#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device + +#endif // __HW_SYSCTL_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_timer.h b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_timer.h new file mode 100644 index 000000000..6a09cd826 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_timer.h @@ -0,0 +1,235 @@ +//***************************************************************************** +// +// hw_timer.h - Defines and macros used when accessing the timer. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_TIMER_H__ +#define __HW_TIMER_H__ + +//***************************************************************************** +// +// The following define the offsets of the timer registers. +// +//***************************************************************************** +#define TIMER_O_CFG 0x00000000 // Configuration register +#define TIMER_O_TAMR 0x00000004 // TimerA mode register +#define TIMER_O_TBMR 0x00000008 // TimerB mode register +#define TIMER_O_CTL 0x0000000C // Control register +#define TIMER_O_IMR 0x00000018 // Interrupt mask register +#define TIMER_O_RIS 0x0000001C // Interrupt status register +#define TIMER_O_MIS 0x00000020 // Masked interrupt status reg. +#define TIMER_O_ICR 0x00000024 // Interrupt clear register +#define TIMER_O_TAILR 0x00000028 // TimerA interval load register +#define TIMER_O_TBILR 0x0000002C // TimerB interval load register +#define TIMER_O_TAMATCHR 0x00000030 // TimerA match register +#define TIMER_O_TBMATCHR 0x00000034 // TimerB match register +#define TIMER_O_TAPR 0x00000038 // TimerA prescale register +#define TIMER_O_TBPR 0x0000003C // TimerB prescale register +#define TIMER_O_TAPMR 0x00000040 // TimerA prescale match register +#define TIMER_O_TBPMR 0x00000044 // TimerB prescale match register +#define TIMER_O_TAR 0x00000048 // TimerA register +#define TIMER_O_TBR 0x0000004C // TimerB register + +//***************************************************************************** +// +// The following define the reset values of the timer registers. +// +//***************************************************************************** +#define TIMER_RV_CFG 0x00000000 // Configuration register RV +#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV +#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV +#define TIMER_RV_CTL 0x00000000 // Control register RV +#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV +#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV +#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV +#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV +#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV +#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV +#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV +#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV +#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV +#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV +#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV +#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV +#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV +#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_CFG register. +// +//***************************************************************************** +#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask +#define TIMER_CFG_16_BIT 0x00000004 // Two 16 bit timers +#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32 bit RTC +#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32 bit timer + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_TnMR register. +// +//***************************************************************************** +#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select +#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time +#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask +#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture +#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic +#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_CTL register. +// +//***************************************************************************** +#define TIMER_CTL_TBPWML 0x00004000 // TimerB PWM output level invert +#define TIMER_CTL_TBOTE 0x00002000 // TimerB output trigger enable +#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask +#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // TimerB event mode - both edges +#define TIMER_CTL_TBEVENT_NEG 0x00000400 // TimerB event mode - neg edge +#define TIMER_CTL_TBEVENT_POS 0x00000000 // TimerB event mode - pos edge +#define TIMER_CTL_TBSTALL 0x00000200 // TimerB stall enable +#define TIMER_CTL_TBEN 0x00000100 // TimerB enable +#define TIMER_CTL_TAPWML 0x00000040 // TimerA PWM output level invert +#define TIMER_CTL_TAOTE 0x00000020 // TimerA output trigger enable +#define TIMER_CTL_RTCEN 0x00000010 // RTC counter enable +#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask +#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // TimerA event mode - both edges +#define TIMER_CTL_TAEVENT_NEG 0x00000004 // TimerA event mode - neg edge +#define TIMER_CTL_TAEVENT_POS 0x00000000 // TimerA event mode - pos edge +#define TIMER_CTL_TASTALL 0x00000002 // TimerA stall enable +#define TIMER_CTL_TAEN 0x00000001 // TimerA enable + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_IMR register. +// +//***************************************************************************** +#define TIMER_IMR_CBEIM 0x00000400 // CaptureB event interrupt mask +#define TIMER_IMR_CBMIM 0x00000200 // CaptureB match interrupt mask +#define TIMER_IMR_TBTOIM 0x00000100 // TimerB time out interrupt mask +#define TIMER_IMR_RTCIM 0x00000008 // RTC interrupt mask +#define TIMER_IMR_CAEIM 0x00000004 // CaptureA event interrupt mask +#define TIMER_IMR_CAMIM 0x00000002 // CaptureA match interrupt mask +#define TIMER_IMR_TATOIM 0x00000001 // TimerA time out interrupt mask + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_RIS register. +// +//***************************************************************************** +#define TIMER_RIS_CBERIS 0x00000400 // CaptureB event raw int status +#define TIMER_RIS_CBMRIS 0x00000200 // CaptureB match raw int status +#define TIMER_RIS_TBTORIS 0x00000100 // TimerB time out raw int status +#define TIMER_RIS_RTCRIS 0x00000008 // RTC raw int status +#define TIMER_RIS_CAERIS 0x00000004 // CaptureA event raw int status +#define TIMER_RIS_CAMRIS 0x00000002 // CaptureA match raw int status +#define TIMER_RIS_TATORIS 0x00000001 // TimerA time out raw int status + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_MIS register. +// +//***************************************************************************** +#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status +#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status +#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat +#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status +#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status +#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status +#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_ICR register. +// +//***************************************************************************** +#define TIMER_ICR_CBECINT 0x00000400 // CaptureB event interrupt clear +#define TIMER_ICR_CBMCINT 0x00000200 // CaptureB match interrupt clear +#define TIMER_ICR_TBTOCINT 0x00000100 // TimerB time out interrupt clear +#define TIMER_ICR_RTCCINT 0x00000008 // RTC interrupt clear +#define TIMER_ICR_CAECINT 0x00000004 // CaptureA event interrupt clear +#define TIMER_ICR_CAMCINT 0x00000002 // CaptureA match interrupt clear +#define TIMER_ICR_TATOCINT 0x00000001 // TimerA time out interrupt clear + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_TAILR register. +// +//***************************************************************************** +#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode +#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TBILR register. +// +//***************************************************************************** +#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_TAMATCHR register. +// +//***************************************************************************** +#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode +#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TBMATCHR register. +// +//***************************************************************************** +#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TnPR register. +// +//***************************************************************************** +#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TnPMR register. +// +//***************************************************************************** +#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_TAR register. +// +//***************************************************************************** +#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode +#define TIMER_TAR_TARL 0x0000FFFF // TimerA value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TBR register. +// +//***************************************************************************** +#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value + +#endif // __HW_TIMER_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_types.h b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_types.h new file mode 100644 index 000000000..0a6084ae3 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_types.h @@ -0,0 +1,67 @@ +//***************************************************************************** +// +// hw_types.h - Common types and macros. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_TYPES_H__ +#define __HW_TYPES_H__ + +//***************************************************************************** +// +// Define a boolean type, and values for true and false. +// +//***************************************************************************** +typedef unsigned char tBoolean; + +#ifndef true +#define true 1 +#endif + +#ifndef false +#define false 0 +#endif + +//***************************************************************************** +// +// Macros for hardware access, both direct and via the bit-band region. +// +//***************************************************************************** +#define HWREG(x) \ + (*((volatile unsigned long *)(x))) +#define HWREGH(x) \ + (*((volatile unsigned short *)(x))) +#define HWREGB(x) \ + (*((volatile unsigned char *)(x))) +#define HWREGBITW(x, b) \ + HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITH(x, b) \ + HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITB(x, b) \ + HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) + +#endif // __HW_TYPES_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_uart.h b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_uart.h new file mode 100644 index 000000000..a688a6aed --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_uart.h @@ -0,0 +1,239 @@ +//***************************************************************************** +// +// hw_uart.h - Macros and defines used when accessing the UART hardware +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_UART_H__ +#define __HW_UART_H__ + +//***************************************************************************** +// +// UART Register Offsets. +// +//***************************************************************************** +#define UART_O_DR 0x00000000 // Data Register +#define UART_O_RSR 0x00000004 // Receive Status Register (read) +#define UART_O_ECR 0x00000004 // Error Clear Register (write) +#define UART_O_FR 0x00000018 // Flag Register (read only) +#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg +#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg +#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte +#define UART_O_CTL 0x00000030 // Control Register +#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg +#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg +#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register +#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register +#define UART_O_ICR 0x00000044 // Interrupt Clear Register +#define UART_O_PeriphID4 0x00000FD0 // +#define UART_O_PeriphID5 0x00000FD4 // +#define UART_O_PeriphID6 0x00000FD8 // +#define UART_O_PeriphID7 0x00000FDC // +#define UART_O_PeriphID0 0x00000FE0 // +#define UART_O_PeriphID1 0x00000FE4 // +#define UART_O_PeriphID2 0x00000FE8 // +#define UART_O_PeriphID3 0x00000FEC // +#define UART_O_PCellID0 0x00000FF0 // +#define UART_O_PCellID1 0x00000FF4 // +#define UART_O_PCellID2 0x00000FF8 // +#define UART_O_PCellID3 0x00000FFC // + +//***************************************************************************** +// +// Data Register bits +// +//***************************************************************************** +#define UART_DR_OE 0x00000800 // Overrun Error +#define UART_DR_BE 0x00000400 // Break Error +#define UART_DR_PE 0x00000200 // Parity Error +#define UART_DR_FE 0x00000100 // Framing Error +#define UART_DR_DATA_MASK 0x000000FF // UART data + +//***************************************************************************** +// +// Receive Status Register bits +// +//***************************************************************************** +#define UART_RSR_OE 0x00000008 // Overrun Error +#define UART_RSR_BE 0x00000004 // Break Error +#define UART_RSR_PE 0x00000002 // Parity Error +#define UART_RSR_FE 0x00000001 // Framing Error + +//***************************************************************************** +// +// Flag Register bits +// +//***************************************************************************** +#define UART_FR_TXFE 0x00000080 // TX FIFO Empty +#define UART_FR_RXFF 0x00000040 // RX FIFO Full +#define UART_FR_TXFF 0x00000020 // TX FIFO Full +#define UART_FR_RXFE 0x00000010 // RX FIFO Empty +#define UART_FR_BUSY 0x00000008 // UART Busy + +//***************************************************************************** +// +// Integer baud-rate divisor +// +//***************************************************************************** +#define UART_IBRD_DIVINT_MASK 0x0000FFFF // Integer baud-rate divisor + +//***************************************************************************** +// +// Fractional baud-rate divisor +// +//***************************************************************************** +#define UART_FBRD_DIVFRAC_MASK 0x0000003F // Fractional baud-rate divisor + +//***************************************************************************** +// +// Line Control Register High bits +// +//***************************************************************************** +#define UART_LCR_H_SPS 0x00000080 // Stick Parity Select +#define UART_LCR_H_WLEN 0x00000060 // Word length +#define UART_LCR_H_WLEN_8 0x00000060 // 8 bit data +#define UART_LCR_H_WLEN_7 0x00000040 // 7 bit data +#define UART_LCR_H_WLEN_6 0x00000020 // 6 bit data +#define UART_LCR_H_WLEN_5 0x00000000 // 5 bit data +#define UART_LCR_H_FEN 0x00000010 // Enable FIFO +#define UART_LCR_H_STP2 0x00000008 // Two Stop Bits Select +#define UART_LCR_H_EPS 0x00000004 // Even Parity Select +#define UART_LCR_H_PEN 0x00000002 // Parity Enable +#define UART_LCR_H_BRK 0x00000001 // Send Break + +//***************************************************************************** +// +// Control Register bits +// +//***************************************************************************** +#define UART_CTL_RXE 0x00000200 // Receive Enable +#define UART_CTL_TXE 0x00000100 // Transmit Enable +#define UART_CTL_LBE 0x00000080 // Loopback Enable +#define UART_CTL_UARTEN 0x00000001 // UART Enable + +//***************************************************************************** +// +// Interrupt FIFO Level Select Register bits +// +//***************************************************************************** +#define UART_IFLS_RX1_8 0x00000000 // 1/8 Full +#define UART_IFLS_RX2_8 0x00000010 // 1/4 Full +#define UART_IFLS_RX4_8 0x00000020 // 1/2 Full +#define UART_IFLS_RX6_8 0x00000030 // 3/4 Full +#define UART_IFLS_RX7_8 0x00000040 // 7/8 Full +#define UART_IFLS_TX1_8 0x00000000 // 1/8 Full +#define UART_IFLS_TX2_8 0x00000001 // 1/4 Full +#define UART_IFLS_TX4_8 0x00000002 // 1/2 Full +#define UART_IFLS_TX6_8 0x00000003 // 3/4 Full +#define UART_IFLS_TX7_8 0x00000004 // 7/8 Full + +//***************************************************************************** +// +// Interrupt Mask Set/Clear Register bits +// +//***************************************************************************** +#define UART_IM_OEIM 0x00000400 // Overrun Error Interrupt Mask +#define UART_IM_BEIM 0x00000200 // Break Error Interrupt Mask +#define UART_IM_PEIM 0x00000100 // Parity Error Interrupt Mask +#define UART_IM_FEIM 0x00000080 // Framing Error Interrupt Mask +#define UART_IM_RTIM 0x00000040 // Receive Timeout Interrupt Mask +#define UART_IM_TXIM 0x00000020 // Transmit Interrupt Mask +#define UART_IM_RXIM 0x00000010 // Receive Interrupt Mask + +//***************************************************************************** +// +// Raw Interrupt Status Register +// +//***************************************************************************** +#define UART_RIS_OERIS 0x00000400 // Overrun Error Interrupt Status +#define UART_RIS_BERIS 0x00000200 // Break Error Interrupt Status +#define UART_RIS_PERIS 0x00000100 // Parity Error Interrupt Status +#define UART_RIS_FERIS 0x00000080 // Framing Error Interrupt Status +#define UART_RIS_RTRIS 0x00000040 // Receive Timeout Interrupt Status +#define UART_RIS_TXRIS 0x00000020 // Transmit Interrupt Status +#define UART_RIS_RXRIS 0x00000010 // Receive Interrupt Status + +//***************************************************************************** +// +// Masked Interrupt Status Register +// +//***************************************************************************** +#define UART_MIS_OEMIS 0x00000400 // Overrun Error Interrupt Status +#define UART_MIS_BEMIS 0x00000200 // Break Error Interrupt Status +#define UART_MIS_PEMIS 0x00000100 // Parity Error Interrupt Status +#define UART_MIS_FEMIS 0x00000080 // Framing Error Interrupt Status +#define UART_MIS_RTMIS 0x00000040 // Receive Timeout Interrupt Status +#define UART_MIS_TXMIS 0x00000020 // Transmit Interrupt Status +#define UART_MIS_RXMIS 0x00000010 // Receive Interrupt Status + +//***************************************************************************** +// +// Interrupt Clear Register bits +// +//***************************************************************************** +#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear +#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear +#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear +#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear +#define UART_ICR_RTIC 0x00000040 // Receive Timeout Interrupt Clear +#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear +#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear + +#define UART_RSR_ANY (UART_RSR_OE | \ + UART_RSR_BE | \ + UART_RSR_PE | \ + UART_RSR_FE) + +//***************************************************************************** +// +// Reset Values for UART Registers. +// +//***************************************************************************** +#define UART_RV_DR 0x00000000 +#define UART_RV_RSR 0x00000000 +#define UART_RV_ECR 0x00000000 +#define UART_RV_FR 0x00000090 +#define UART_RV_IBRD 0x00000000 +#define UART_RV_FBRD 0x00000000 +#define UART_RV_LCR_H 0x00000000 +#define UART_RV_CTL 0x00000300 +#define UART_RV_IFLS 0x00000012 +#define UART_RV_IM 0x00000000 +#define UART_RV_RIS 0x00000000 +#define UART_RV_MIS 0x00000000 +#define UART_RV_ICR 0x00000000 +#define UART_RV_PeriphID4 0x00000000 +#define UART_RV_PeriphID5 0x00000000 +#define UART_RV_PeriphID6 0x00000000 +#define UART_RV_PeriphID7 0x00000000 +#define UART_RV_PeriphID0 0x00000011 +#define UART_RV_PeriphID1 0x00000000 +#define UART_RV_PeriphID2 0x00000018 +#define UART_RV_PeriphID3 0x00000001 +#define UART_RV_PCellID0 0x0000000D +#define UART_RV_PCellID1 0x000000F0 +#define UART_RV_PCellID2 0x00000005 +#define UART_RV_PCellID3 0x000000B1 + +#endif // __HW_UART_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_watchdog.h b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_watchdog.h new file mode 100644 index 000000000..e6e3fa50a --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_watchdog.h @@ -0,0 +1,116 @@ +//***************************************************************************** +// +// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __HW_WATCHDOG_H__ +#define __HW_WATCHDOG_H__ + +//***************************************************************************** +// +// The following define the offsets of the Watchdog Timer registers. +// +//***************************************************************************** +#define WDT_O_LOAD 0x00000000 // Load register +#define WDT_O_VALUE 0x00000004 // Current value register +#define WDT_O_CTL 0x00000008 // Control register +#define WDT_O_ICR 0x0000000C // Interrupt clear register +#define WDT_O_RIS 0x00000010 // Raw interrupt status register +#define WDT_O_MIS 0x00000014 // Masked interrupt status register +#define WDT_O_TEST 0x00000418 // Test register +#define WDT_O_LOCK 0x00000C00 // Lock register +#define WDT_O_PeriphID4 0x00000FD0 // +#define WDT_O_PeriphID5 0x00000FD4 // +#define WDT_O_PeriphID6 0x00000FD8 // +#define WDT_O_PeriphID7 0x00000FDC // +#define WDT_O_PeriphID0 0x00000FE0 // +#define WDT_O_PeriphID1 0x00000FE4 // +#define WDT_O_PeriphID2 0x00000FE8 // +#define WDT_O_PeriphID3 0x00000FEC // +#define WDT_O_PCellID0 0x00000FF0 // +#define WDT_O_PCellID1 0x00000FF4 // +#define WDT_O_PCellID2 0x00000FF8 // +#define WDT_O_PCellID3 0x00000FFC // + +//***************************************************************************** +// +// The following define the bit fields in the WDT_CTL register. +// +//***************************************************************************** +#define WDT_CTL_RESEN 0x00000002 // Enable reset output +#define WDT_CTL_INTEN 0x00000001 // Enable the WDT counter and int + +//***************************************************************************** +// +// The following define the bit fields in the WDT_ISR, WDT_RIS, and WDT_MIS +// registers. +// +//***************************************************************************** +#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired + +//***************************************************************************** +// +// The following define the bit fields in the WDT_TEST register. +// +//***************************************************************************** +#define WDT_TEST_STALL 0x00000100 // Watchdog stall enable +#ifndef DEPRECATED +#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable +#endif + +//***************************************************************************** +// +// The following define the bit fields in the WDT_LOCK register. +// +//***************************************************************************** +#define WDT_LOCK_LOCKED 0x00000001 // Watchdog timer is locked +#define WDT_LOCK_UNLOCKED 0x00000000 // Watchdog timer is unlocked +#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer + +//***************************************************************************** +// +// The following define the reset values for the WDT registers. +// +//***************************************************************************** +#define WDT_RV_LOAD 0xFFFFFFFF // Load register +#define WDT_RV_VALUE 0xFFFFFFFF // Current value register +#define WDT_RV_CTL 0x00000000 // Control register +#define WDT_RV_RIS 0x00000000 // Raw interrupt status register +#define WDT_RV_MIS 0x00000000 // Masked interrupt status register +#define WDT_RV_LOCK 0x00000000 // Lock register +#define WDT_RV_PeriphID4 0x00000000 // +#define WDT_RV_PeriphID5 0x00000000 // +#define WDT_RV_PeriphID6 0x00000000 // +#define WDT_RV_PeriphID7 0x00000000 // +#define WDT_RV_PeriphID0 0x00000005 // +#define WDT_RV_PeriphID1 0x00000018 // +#define WDT_RV_PeriphID2 0x00000018 // +#define WDT_RV_PeriphID3 0x00000001 // +#define WDT_RV_PCellID0 0x0000000D // +#define WDT_RV_PCellID1 0x000000F0 // +#define WDT_RV_PCellID2 0x00000005 // +#define WDT_RV_PCellID3 0x000000B1 // + +#endif // __HW_WATCHDOG_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/osram96x16.c b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/osram96x16.c new file mode 100644 index 000000000..7c6ef0184 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/osram96x16.c @@ -0,0 +1,952 @@ +//***************************************************************************** +// +// osram96x16.c - Driver for the OSRAM 96x16 graphical OLED display. +// +// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup ev_lm3s811_api +//! @{ +// +//***************************************************************************** + +#include "hw_i2c.h" +#include "hw_memmap.h" +#include "hw_sysctl.h" +#include "hw_types.h" +#include "src/debug.h" +#include "src/gpio.h" +#include "src/i2c.h" +#include "src/sysctl.h" +#include "osram96x16.h" + +//***************************************************************************** +// +// The I2C slave address of the SSD0303 controller on the OLED display. +// +//***************************************************************************** +#define SSD0303_ADDR 0x3d + +//***************************************************************************** +// +// A 5x7 font (in a 6x8 cell, where the sixth column is omitted from this +// table) for displaying text on the OLED display. The data is organized as +// bytes from the left column to the right column, with each byte containing +// the top row in the LSB and the bottom row in the MSB. +// +//***************************************************************************** +static const unsigned char g_pucFont[95][5] = +{ + { 0x00, 0x00, 0x00, 0x00, 0x00 }, // " " + { 0x00, 0x00, 0x4f, 0x00, 0x00 }, // ! + { 0x00, 0x07, 0x00, 0x07, 0x00 }, // " + { 0x14, 0x7f, 0x14, 0x7f, 0x14 }, // # + { 0x24, 0x2a, 0x7f, 0x2a, 0x12 }, // $ + { 0x23, 0x13, 0x08, 0x64, 0x62 }, // % + { 0x36, 0x49, 0x55, 0x22, 0x50 }, // & + { 0x00, 0x05, 0x03, 0x00, 0x00 }, // ' + { 0x00, 0x1c, 0x22, 0x41, 0x00 }, // ( + { 0x00, 0x41, 0x22, 0x1c, 0x00 }, // ) + { 0x14, 0x08, 0x3e, 0x08, 0x14 }, // * + { 0x08, 0x08, 0x3e, 0x08, 0x08 }, // + + { 0x00, 0x50, 0x30, 0x00, 0x00 }, // , + { 0x08, 0x08, 0x08, 0x08, 0x08 }, // - + { 0x00, 0x60, 0x60, 0x00, 0x00 }, // . + { 0x20, 0x10, 0x08, 0x04, 0x02 }, // / + { 0x3e, 0x51, 0x49, 0x45, 0x3e }, // 0 + { 0x00, 0x42, 0x7f, 0x40, 0x00 }, // 1 + { 0x42, 0x61, 0x51, 0x49, 0x46 }, // 2 + { 0x21, 0x41, 0x45, 0x4b, 0x31 }, // 3 + { 0x18, 0x14, 0x12, 0x7f, 0x10 }, // 4 + { 0x27, 0x45, 0x45, 0x45, 0x39 }, // 5 + { 0x3c, 0x4a, 0x49, 0x49, 0x30 }, // 6 + { 0x01, 0x71, 0x09, 0x05, 0x03 }, // 7 + { 0x36, 0x49, 0x49, 0x49, 0x36 }, // 8 + { 0x06, 0x49, 0x49, 0x29, 0x1e }, // 9 + { 0x00, 0x36, 0x36, 0x00, 0x00 }, // : + { 0x00, 0x56, 0x36, 0x00, 0x00 }, // ; + { 0x08, 0x14, 0x22, 0x41, 0x00 }, // < + { 0x14, 0x14, 0x14, 0x14, 0x14 }, // = + { 0x00, 0x41, 0x22, 0x14, 0x08 }, // > + { 0x02, 0x01, 0x51, 0x09, 0x06 }, // ? + { 0x32, 0x49, 0x79, 0x41, 0x3e }, // @ + { 0x7e, 0x11, 0x11, 0x11, 0x7e }, // A + { 0x7f, 0x49, 0x49, 0x49, 0x36 }, // B + { 0x3e, 0x41, 0x41, 0x41, 0x22 }, // C + { 0x7f, 0x41, 0x41, 0x22, 0x1c }, // D + { 0x7f, 0x49, 0x49, 0x49, 0x41 }, // E + { 0x7f, 0x09, 0x09, 0x09, 0x01 }, // F + { 0x3e, 0x41, 0x49, 0x49, 0x7a }, // G + { 0x7f, 0x08, 0x08, 0x08, 0x7f }, // H + { 0x00, 0x41, 0x7f, 0x41, 0x00 }, // I + { 0x20, 0x40, 0x41, 0x3f, 0x01 }, // J + { 0x7f, 0x08, 0x14, 0x22, 0x41 }, // K + { 0x7f, 0x40, 0x40, 0x40, 0x40 }, // L + { 0x7f, 0x02, 0x0c, 0x02, 0x7f }, // M + { 0x7f, 0x04, 0x08, 0x10, 0x7f }, // N + { 0x3e, 0x41, 0x41, 0x41, 0x3e }, // O + { 0x7f, 0x09, 0x09, 0x09, 0x06 }, // P + { 0x3e, 0x41, 0x51, 0x21, 0x5e }, // Q + { 0x7f, 0x09, 0x19, 0x29, 0x46 }, // R + { 0x46, 0x49, 0x49, 0x49, 0x31 }, // S + { 0x01, 0x01, 0x7f, 0x01, 0x01 }, // T + { 0x3f, 0x40, 0x40, 0x40, 0x3f }, // U + { 0x1f, 0x20, 0x40, 0x20, 0x1f }, // V + { 0x3f, 0x40, 0x38, 0x40, 0x3f }, // W + { 0x63, 0x14, 0x08, 0x14, 0x63 }, // X + { 0x07, 0x08, 0x70, 0x08, 0x07 }, // Y + { 0x61, 0x51, 0x49, 0x45, 0x43 }, // Z + { 0x00, 0x7f, 0x41, 0x41, 0x00 }, // [ + { 0x02, 0x04, 0x08, 0x10, 0x20 }, // "\" + { 0x00, 0x41, 0x41, 0x7f, 0x00 }, // ] + { 0x04, 0x02, 0x01, 0x02, 0x04 }, // ^ + { 0x40, 0x40, 0x40, 0x40, 0x40 }, // _ + { 0x00, 0x01, 0x02, 0x04, 0x00 }, // ` + { 0x20, 0x54, 0x54, 0x54, 0x78 }, // a + { 0x7f, 0x48, 0x44, 0x44, 0x38 }, // b + { 0x38, 0x44, 0x44, 0x44, 0x20 }, // c + { 0x38, 0x44, 0x44, 0x48, 0x7f }, // d + { 0x38, 0x54, 0x54, 0x54, 0x18 }, // e + { 0x08, 0x7e, 0x09, 0x01, 0x02 }, // f + { 0x0c, 0x52, 0x52, 0x52, 0x3e }, // g + { 0x7f, 0x08, 0x04, 0x04, 0x78 }, // h + { 0x00, 0x44, 0x7d, 0x40, 0x00 }, // i + { 0x20, 0x40, 0x44, 0x3d, 0x00 }, // j + { 0x7f, 0x10, 0x28, 0x44, 0x00 }, // k + { 0x00, 0x41, 0x7f, 0x40, 0x00 }, // l + { 0x7c, 0x04, 0x18, 0x04, 0x78 }, // m + { 0x7c, 0x08, 0x04, 0x04, 0x78 }, // n + { 0x38, 0x44, 0x44, 0x44, 0x38 }, // o + { 0x7c, 0x14, 0x14, 0x14, 0x08 }, // p + { 0x08, 0x14, 0x14, 0x18, 0x7c }, // q + { 0x7c, 0x08, 0x04, 0x04, 0x08 }, // r + { 0x48, 0x54, 0x54, 0x54, 0x20 }, // s + { 0x04, 0x3f, 0x44, 0x40, 0x20 }, // t + { 0x3c, 0x40, 0x40, 0x20, 0x7c }, // u + { 0x1c, 0x20, 0x40, 0x20, 0x1c }, // v + { 0x3c, 0x40, 0x30, 0x40, 0x3c }, // w + { 0x44, 0x28, 0x10, 0x28, 0x44 }, // x + { 0x0c, 0x50, 0x50, 0x50, 0x3c }, // y + { 0x44, 0x64, 0x54, 0x4c, 0x44 }, // z + { 0x00, 0x08, 0x36, 0x41, 0x00 }, // { + { 0x00, 0x00, 0x7f, 0x00, 0x00 }, // | + { 0x00, 0x41, 0x36, 0x08, 0x00 }, // } + { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~ +}; + +//***************************************************************************** +// +// The sequence of commands used to initialize the SSD0303 controller. Each +// command is described as follows: there is a byte specifying the number of +// bytes in the I2C transfer, followed by that many bytes of command data. +// +//***************************************************************************** +static const unsigned char g_pucOSRAMInit[] = +{ + // + // Turn off the panel + // + 0x02, 0x80, 0xae, + + // + // Set lower column address + // + 0x02, 0x80, 0x04, + + // + // Set higher column address + // + 0x02, 0x80, 0x12, + + // + // Set contrast control register + // + 0x04, 0x80, 0x81, 0x80, 0x2b, + + // + // Set segment re-map + // + 0x02, 0x80, 0xa1, + + // + // Set display start line + // + 0x02, 0x80, 0x40, + + // + // Set display offset + // + 0x04, 0x80, 0xd3, 0x80, 0x00, + + // + // Set multiplex ratio + // + 0x04, 0x80, 0xa8, 0x80, 0x0f, + + // + // Set the display to normal mode + // + 0x02, 0x80, 0xa4, + + // + // Non-inverted display + // + 0x02, 0x80, 0xa6, + + // + // Set the page address + // + 0x02, 0x80, 0xb0, + + // + // Set COM output scan direction + // + 0x02, 0x80, 0xc8, + + // + // Set display clock divide ratio/oscillator frequency + // + 0x04, 0x80, 0xd5, 0x80, 0x72, + + // + // Enable mono mode + // + 0x04, 0x80, 0xd8, 0x80, 0x00, + + // + // Set pre-charge period + // + 0x04, 0x80, 0xd9, 0x80, 0x22, + + // + // Set COM pins hardware configuration + // + 0x04, 0x80, 0xda, 0x80, 0x12, + + // + // Set VCOM deslect level + // + 0x04, 0x80, 0xdb, 0x80, 0x0f, + + // + // Set DC-DC on + // + 0x04, 0x80, 0xad, 0x80, 0x8b, + + // + // Turn on the panel + // + 0x02, 0x80, 0xaf, +}; + +//***************************************************************************** +// +// The inter-byte delay required by the SSD0303 OLED controller. +// +//***************************************************************************** +static unsigned long g_ulDelay; + +//***************************************************************************** +// +//! \internal +//! +//! Provide a small delay. +//! +//! \param ulCount is the number of delay loop iterations to perform. +//! +//! Since the SSD0303 controller needs a delay between bytes written to it over +//! the I2C bus, this function provides a means of generating that delay. It +//! is written in assembly to keep the delay consistent across tool chains, +//! avoiding the need to tune the delay based on the tool chain in use. +//! +//! \return None. +// +//***************************************************************************** +#if defined(ewarm) +static void +OSRAMDelay(unsigned long ulCount) +{ + __asm(" subs r0, #1\n" + " bne OSRAMDelay\n" + " bx lr"); +} +#endif +#if defined(gcc) +static void __attribute__((naked)) +OSRAMDelay(unsigned long ulCount) +{ + __asm(" subs r0, #1\n" + " bne OSRAMDelay\n" + " bx lr"); +} +#endif +#if defined(rvmdk) || defined(__ARMCC_VERSION) +__asm void +OSRAMDelay(unsigned long ulCount) +{ + subs r0, #1; + bne OSRAMDelay; + bx lr; +} +#endif + +//***************************************************************************** +// +//! \internal +//! +//! Start a transfer to the SSD0303 controller. +//! +//! \param ucChar is the first byte to be written to the controller. +//! +//! This function will start a transfer to the SSD0303 controller via the I2C +//! bus. +//! +//! The data is written in a polled fashion; this function will not return +//! until the byte has been written to the controller. +//! +//! \return None. +// +//***************************************************************************** +static void +OSRAMWriteFirst(unsigned char ucChar) +{ + // + // Set the slave address. + // + I2CMasterSlaveAddrSet(I2C_MASTER_BASE, SSD0303_ADDR, false); + + // + // Write the first byte to the controller. + // + I2CMasterDataPut(I2C_MASTER_BASE, ucChar); + + // + // Start the transfer. + // + I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_START); +} + +//***************************************************************************** +// +//! \internal +//! +//! Write a byte to the SSD0303 controller. +//! +//! \param ucChar is the byte to be transmitted to the controller. +//! +//! This function continues a transfer to the SSD0303 controller by writing +//! another byte over the I2C bus. This must only be called after calling +//! OSRAMWriteFirst(), but before calling OSRAMWriteFinal(). +//! +//! The data is written in a polled faashion; this function will not return +//! until the byte has been written to the controller. +//! +//! \return None. +// +//***************************************************************************** +static void +OSRAMWriteByte(unsigned char ucChar) +{ + // + // Wait until the current byte has been transferred. + // + while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0) + { + } + + // + // Provide the required inter-byte delay. + // + OSRAMDelay(g_ulDelay); + + // + // Write the next byte to the controller. + // + I2CMasterDataPut(I2C_MASTER_BASE, ucChar); + + // + // Continue the transfer. + // + I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_CONT); +} + +//***************************************************************************** +// +//! \internal +//! +//! Write a sequence of bytes to the SSD0303 controller. +//! +//! This function continues a transfer to the SSD0303 controller by writing a +//! sequence of bytes over the I2C bus. This must only be called after calling +//! OSRAMWriteFirst(), but before calling OSRAMWriteFinal(). +//! +//! The data is written in a polled fashion; this function will not return +//! until the entire byte sequence has been written to the controller. +//! +//! \return None. +// +//***************************************************************************** +static void +OSRAMWriteArray(const unsigned char *pucBuffer, unsigned long ulCount) +{ + // + // Loop while there are more bytes left to be transferred. + // + while(ulCount != 0) + { + // + // Wait until the current byte has been transferred. + // + while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0) + { + } + + // + // Provide the required inter-byte delay. + // + OSRAMDelay(g_ulDelay); + + // + // Write the next byte to the controller. + // + I2CMasterDataPut(I2C_MASTER_BASE, *pucBuffer++); + ulCount--; + + // + // Continue the transfer. + // + I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_CONT); + } +} + +//***************************************************************************** +// +//! \internal +//! +//! Finish a transfer to the SSD0303 controller. +//! +//! \param ucChar is the final byte to be written to the controller. +//! +//! This function will finish a transfer to the SSD0303 controller via the I2C +//! bus. This must only be called after calling OSRAMWriteFirst(). +//! +//! The data is written in a polled fashion; this function will not return +//! until the byte has been written to the controller. +//! +//! \return None. +// +//***************************************************************************** +static void +OSRAMWriteFinal(unsigned char ucChar) +{ + // + // Wait until the current byte has been transferred. + // + while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0) + { + } + + // + // Provide the required inter-byte delay. + // + OSRAMDelay(g_ulDelay); + + // + // Write the final byte to the controller. + // + I2CMasterDataPut(I2C_MASTER_BASE, ucChar); + + // + // Finish the transfer. + // + I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_FINISH); + + // + // Wait until the final byte has been transferred. + // + while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0) + { + } + + // + // Provide the required inter-byte delay. + // + OSRAMDelay(g_ulDelay); +} + +//***************************************************************************** +// +//! Clears the OLED display. +//! +//! This function will clear the display. All pixels in the display will be +//! turned off. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAMClear(void) +{ + static const unsigned char pucRow1[] = + { + 0xb0, 0x80, 0x04, 0x80, 0x12, 0x40 + }; + static const unsigned char pucRow2[] = + { + 0xb1, 0x80, 0x04, 0x80, 0x12, 0x40 + }; + unsigned long ulIdx; + + // + // Move the display cursor to the first column of the first row. + // + OSRAMWriteFirst(0x80); + OSRAMWriteArray(pucRow1, sizeof(pucRow1)); + + // + // Fill this row with zeros. + // + for(ulIdx = 0; ulIdx < 95; ulIdx++) + { + OSRAMWriteByte(0x00); + } + OSRAMWriteFinal(0x00); + + // + // Move the display cursor to the first column of the second row. + // + OSRAMWriteFirst(0x80); + OSRAMWriteArray(pucRow2, sizeof(pucRow2)); + + // + // Fill this row with zeros. + // + for(ulIdx = 0; ulIdx < 95; ulIdx++) + { + OSRAMWriteByte(0x00); + } + OSRAMWriteFinal(0x00); +} + +//***************************************************************************** +// +//! Displays a string on the OLED display. +//! +//! \param pcStr is a pointer to the string to display. +//! \param ulX is the horizontal position to display the string, specified in +//! columns from the left edge of the display. +//! \param ulY is the vertical position to display the string, specified in +//! eight scan line blocks from the top of the display (i.e. only 0 and 1 are +//! valid). +//! +//! This function will draw a string on the display. Only the ASCII characters +//! between 32 (space) and 126 (tilde) are supported; other characters will +//! result in random data being draw on the display (based on whatever appears +//! before/after the font in memory). The font is mono-spaced, so characters +//! such as "i" and "l" have more white space around them than characters such +//! as "m" or "w". +//! +//! If the drawing of the string reaches the right edge of the display, no more +//! characters will be drawn. Therefore, special care is not required to avoid +//! supplying a string that is "too long" to display. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAMStringDraw(const char *pcStr, unsigned long ulX, unsigned long ulY) +{ + // + // Check the arguments. + // + ASSERT(ulX < 96); + ASSERT(ulY < 2); + + // + // Move the display cursor to the requested position on the display. + // + OSRAMWriteFirst(0x80); + OSRAMWriteByte((ulY == 0) ? 0xb0 : 0xb1); + OSRAMWriteByte(0x80); + OSRAMWriteByte((ulX + 36) & 0x0f); + OSRAMWriteByte(0x80); + OSRAMWriteByte(0x10 | (((ulX + 36) >> 4) & 0x0f)); + OSRAMWriteByte(0x40); + + // + // Loop while there are more characters in the string. + // + while(*pcStr != 0) + { + // + // See if there is enough space on the display for this entire + // character. + // + if(ulX <= 90) + { + // + // Write the contents of this character to the display. + // + OSRAMWriteArray(g_pucFont[*pcStr - ' '], 5); + + // + // See if this is the last character to display (either because the + // right edge has been reached or because there are no more + // characters). + // + if((ulX == 90) || (pcStr[1] == 0)) + { + // + // Write the final column of the display. + // + OSRAMWriteFinal(0x00); + + // + // The string has been displayed. + // + return; + } + + // + // Write the inter-character padding column. + // + OSRAMWriteByte(0x00); + } + else + { + // + // Write the portion of the character that will fit onto the + // display. + // + OSRAMWriteArray(g_pucFont[*pcStr - ' '], 95 - ulX); + OSRAMWriteFinal(g_pucFont[*pcStr - ' '][95 - ulX]); + + // + // The string has been displayed. + // + return; + } + + // + // Advance to the next character. + // + pcStr++; + + // + // Increment the X coordinate by the six columns that were just + // written. + // + ulX += 6; + } +} + +//***************************************************************************** +// +//! Displays an image on the OLED display. +//! +//! \param pucImage is a pointer to the image data. +//! \param ulX is the horizontal position to display this image, specified in +//! columns from the left edge of the display. +//! \param ulY is the vertical position to display this image, specified in +//! eight scan line blocks from the top of the display (i.e. only 0 and 1 are +//! valid). +//! \param ulWidth is the width of the image, specified in columns. +//! \param ulHeight is the height of the image, specified in eight row blocks +//! (i.e. only 1 and 2 are valid). +//! +//! This function will display a bitmap graphic on the display. The image to +//! be displayed must be a multiple of eight scan lines high (i.e. one row) and +//! will be drawn at a vertical position that is a multiple of eight scan lines +//! (i.e. scan line zero or scan line eight, corresponding to row zero or row +//! one). +//! +//! The image data is organized with the first row of image data appearing left +//! to right, followed immediately by the second row of image data. Each byte +//! contains the data for the eight scan lines of the column, with the top scan +//! line being in the least significant bit of the byte and the bottom scan +//! line being in the most significant bit of the byte. +//! +//! For example, an image four columns wide and sixteen scan lines tall would +//! be arranged as follows (showing how the eight bytes of the image would +//! appear on the display): +//! +//! \verbatim +//! +-------+ +-------+ +-------+ +-------+ +//! | | 0 | | | 0 | | | 0 | | | 0 | +//! | B | 1 | | B | 1 | | B | 1 | | B | 1 | +//! | y | 2 | | y | 2 | | y | 2 | | y | 2 | +//! | t | 3 | | t | 3 | | t | 3 | | t | 3 | +//! | e | 4 | | e | 4 | | e | 4 | | e | 4 | +//! | | 5 | | | 5 | | | 5 | | | 5 | +//! | 0 | 6 | | 1 | 6 | | 2 | 6 | | 3 | 6 | +//! | | 7 | | | 7 | | | 7 | | | 7 | +//! +-------+ +-------+ +-------+ +-------+ +//! +//! +-------+ +-------+ +-------+ +-------+ +//! | | 0 | | | 0 | | | 0 | | | 0 | +//! | B | 1 | | B | 1 | | B | 1 | | B | 1 | +//! | y | 2 | | y | 2 | | y | 2 | | y | 2 | +//! | t | 3 | | t | 3 | | t | 3 | | t | 3 | +//! | e | 4 | | e | 4 | | e | 4 | | e | 4 | +//! | | 5 | | | 5 | | | 5 | | | 5 | +//! | 4 | 6 | | 5 | 6 | | 6 | 6 | | 7 | 6 | +//! | | 7 | | | 7 | | | 7 | | | 7 | +//! +-------+ +-------+ +-------+ +-------+ +//! \endverbatim +//! +//! \return None. +// +//***************************************************************************** +void +OSRAMImageDraw(const unsigned char *pucImage, unsigned long ulX, + unsigned long ulY, unsigned long ulWidth, + unsigned long ulHeight) +{ + // + // Check the arguments. + // + ASSERT(ulX < 96); + ASSERT(ulY < 2); + ASSERT((ulX + ulWidth) <= 96); + ASSERT((ulY + ulHeight) <= 2); + + // + // The first 36 columns of the LCD buffer are not displayed, so increment + // the X coorddinate by 36 to account for the non-displayed frame buffer + // memory. + // + ulX += 36; + + // + // Loop while there are more rows to display. + // + while(ulHeight--) + { + // + // Write the starting address within this row. + // + OSRAMWriteFirst(0x80); + OSRAMWriteByte((ulY == 0) ? 0xb0 : 0xb1); + OSRAMWriteByte(0x80); + OSRAMWriteByte(ulX & 0x0f); + OSRAMWriteByte(0x80); + OSRAMWriteByte(0x10 | ((ulX >> 4) & 0x0f)); + OSRAMWriteByte(0x40); + + // + // Write this row of image data. + // + OSRAMWriteArray(pucImage, ulWidth - 1); + OSRAMWriteFinal(pucImage[ulWidth - 1]); + + // + // Advance to the next row of the image. + // + pucImage += ulWidth; + ulY++; + } +} + +//***************************************************************************** +// +//! Initialize the OLED display. +//! +//! \param bFast is a boolean that is \e true if the I2C interface should be +//! run at 400 kbps and \e false if it should be run at 100 kbps. +//! +//! This function initializes the I2C interface to the OLED display and +//! configures the SSD0303 controller on the panel. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAMInit(tBoolean bFast) +{ + unsigned long ulIdx; + + // + // Enable the I2C and GPIO port B blocks as they are needed by this driver. + // + SysCtlPeripheralEnable(SYSCTL_PERIPH_I2C); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB); + + // + // Configure the I2C SCL and SDA pins for I2C operation. + // + GPIOPinTypeI2C(GPIO_PORTB_BASE, GPIO_PIN_2 | GPIO_PIN_3); + + // + // Initialize the I2C master. + // + I2CMasterInit(I2C_MASTER_BASE, bFast); + + // + // Compute the inter-byte delay for the SSD0303 controller. This delay is + // dependent upon the I2C bus clock rate; the slower the clock the longer + // the delay required. + // + // The derivation of this formula is based on a measured delay of + // OSRAMDelay(1700) for a 100 kHz I2C bus with the CPU running at 50 MHz + // (referred to as C). To scale this to the delay for a different CPU + // speed (since this is just a CPU-based delay loop) is: + // + // f(CPU) + // C * ---------- + // 50,000,000 + // + // To then scale this to the actual I2C rate (since it won't always be + // precisely 100 kHz): + // + // f(CPU) 100,000 + // C * ---------- * ------- + // 50,000,000 f(I2C) + // + // This equation will give the inter-byte delay required for any + // configuration of the I2C master. But, as arranged it is impossible to + // directly compute in 32-bit arithmetic (without loosing a lot of + // accuracy). So, the equation is simplified. + // + // Since f(I2C) is generated by dividing down from f(CPU), replace it with + // the equivalent (where TPR is the value programmed into the Master Timer + // Period Register of the I2C master, with the 1 added back): + // + // 100,000 + // f(CPU) ------- + // C * ---------- * f(CPU) + // 50,000,000 ------------ + // 2 * 10 * TPR + // + // Inverting the dividend in the last term: + // + // f(CPU) 100,000 * 2 * 10 * TPR + // C * ---------- * ---------------------- + // 50,000,000 f(CPU) + // + // The f(CPU) now cancels out. + // + // 100,000 * 2 * 10 * TPR + // C * ---------------------- + // 50,000,000 + // + // Since there are no clock frequencies left in the equation, this equation + // also works for 400 kHz bus operation as well, since the 100,000 in the + // numerator becomes 400,000 but C is 1/4, which cancel out each other. + // Reducing the constants gives: + // + // TPR TPR TPR + // C * --- = 1700 * --- = 340 * --- + // 25 25 5 + // + // Note that the constant C is actually a bit larger than it needs to be in + // order to provide some safety margin. + // + // When the panel is being initialized, the value of C actually needs to be + // a bit longer (3200 instead of 1700). So, set the larger value for now. + // + g_ulDelay = (640 * (HWREG(I2C_MASTER_BASE + I2C_MASTER_O_TPR) + 1)) / 5; + + // + // Initialize the SSD0303 controller. Loop through the initialization + // sequence doing a single I2C transfer for each command. + // + for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAMInit); + ulIdx += g_pucOSRAMInit[ulIdx] + 1) + { + // + // Send this command. + // + OSRAMWriteFirst(g_pucOSRAMInit[ulIdx + 1]); + OSRAMWriteArray(g_pucOSRAMInit + ulIdx + 2, g_pucOSRAMInit[ulIdx] - 2); + OSRAMWriteFinal(g_pucOSRAMInit[ulIdx + g_pucOSRAMInit[ulIdx]]); + } + + // + // Now, switch to the actual value of C. + // + g_ulDelay = (340 * (HWREG(I2C_MASTER_BASE + I2C_MASTER_O_TPR) + 1)) / 5; + + // + // Clear the frame buffer. + // + OSRAMClear(); +} + +//***************************************************************************** +// +//! Turns on the OLED display. +//! +//! This function will turn on the OLED display, causing it to display the +//! contents of its internal frame buffer. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAMDisplayOn(void) +{ + // + // Turn on the DC-DC converter and the display. + // + OSRAMWriteFirst(0x80); + OSRAMWriteByte(0xad); + OSRAMWriteByte(0x80); + OSRAMWriteByte(0x8b); + OSRAMWriteByte(0x80); + OSRAMWriteFinal(0xaf); +} + +//***************************************************************************** +// +//! Turns off the OLED display. +//! +//! This function will turn off the OLED display. This will stop the scanning +//! of the panel and turn off the on-chip DC-DC converter, preventing damage to +//! the panel due to burn-in (it has similar characters to a CRT in this +//! respect). +//! +//! \return None. +// +//***************************************************************************** +void +OSRAMDisplayOff(void) +{ + // + // Turn off the DC-DC converter and the display. + // + OSRAMWriteFirst(0x80); + OSRAMWriteByte(0xad); + OSRAMWriteByte(0x80); + OSRAMWriteByte(0x8a); + OSRAMWriteByte(0x80); + OSRAMWriteFinal(0xae); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/osram96x16.h b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/osram96x16.h new file mode 100644 index 000000000..54cf4215a --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/osram96x16.h @@ -0,0 +1,47 @@ +//***************************************************************************** +// +// osram96x16.h - Prototypes for the driver for the OSRAM 96x16 graphical OLED +// display. +// +// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 852 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __OSRAM96X16_H__ +#define __OSRAM96X16_H__ + +//***************************************************************************** +// +// Prototypes for the driver APIs. +// +//***************************************************************************** +extern void OSRAMClear(void); +extern void OSRAMStringDraw(const char *pcStr, unsigned long ulX, + unsigned long ulY); +extern void OSRAMImageDraw(const unsigned char *pucImage, unsigned long ulX, + unsigned long ulY, unsigned long ulWidth, + unsigned long ulHeight); +extern void OSRAMInit(tBoolean bFast); +extern void OSRAMDisplayOn(void); +extern void OSRAMDisplayOff(void); + +#endif // __OSRAM96X16_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/adc.h b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/adc.h new file mode 100644 index 000000000..ee06b9c29 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/adc.h @@ -0,0 +1,124 @@ +//***************************************************************************** +// +// adc.h - ADC headers for using the ADC driver functions. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __ADC_H__ +#define __ADC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to ADCSequenceConfigure as the ulTrigger +// parameter. +// +//***************************************************************************** +#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event +#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event +#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event +#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event +#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event +#define ADC_TRIGGER_TIMER 0x00000005 // Timer event +#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event +#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event +#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event +#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event + +//***************************************************************************** +// +// Values that can be passed to ADCSequenceStepConfigure as the ulConfig +// parameter. +// +//***************************************************************************** +#define ADC_CTL_TS 0x00000080 // Temperature sensor select +#define ADC_CTL_IE 0x00000040 // Interrupt enable +#define ADC_CTL_END 0x00000020 // Sequence end select +#define ADC_CTL_D 0x00000010 // Differential select +#define ADC_CTL_CH0 0x00000000 // Input channel 0 +#define ADC_CTL_CH1 0x00000001 // Input channel 1 +#define ADC_CTL_CH2 0x00000002 // Input channel 2 +#define ADC_CTL_CH3 0x00000003 // Input channel 3 +#define ADC_CTL_CH4 0x00000004 // Input channel 4 +#define ADC_CTL_CH5 0x00000005 // Input channel 5 +#define ADC_CTL_CH6 0x00000006 // Input channel 6 +#define ADC_CTL_CH7 0x00000007 // Input channel 7 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum, + void (*pfnHandler)(void)); +extern void ADCIntUnregister(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum); +extern void ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum); +extern unsigned long ADCIntStatus(unsigned long ulBase, + unsigned long ulSequenceNum, + tBoolean bMasked); +extern void ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum); +extern void ADCSequenceEnable(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCSequenceDisable(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCSequenceConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulTrigger, + unsigned long ulPriority); +extern void ADCSequenceStepConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulStep, + unsigned long ulConfig); +extern long ADCSequenceOverflow(unsigned long ulBase, + unsigned long ulSequenceNum); +extern long ADCSequenceUnderflow(unsigned long ulBase, + unsigned long ulSequenceNum); +extern long ADCSequenceDataGet(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long *pulBuffer); +extern void ADCProcessorTrigger(unsigned long ulBase, + unsigned long ulSequenceNum); +extern void ADCSoftwareOversampleConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulFactor); +extern void ADCSoftwareOversampleStepConfigure(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long ulStep, + unsigned long ulConfig); +extern void ADCSoftwareOversampleDataGet(unsigned long ulBase, + unsigned long ulSequenceNum, + unsigned long *pulBuffer, + unsigned long ulCount); + +#ifdef __cplusplus +} +#endif + +#endif // __ADC_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/comp.h b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/comp.h new file mode 100644 index 000000000..14751223a --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/comp.h @@ -0,0 +1,120 @@ +//***************************************************************************** +// +// comp.h - Prototypes for the analog comparator driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __COMP_H__ +#define __COMP_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to ComparatorConfigure() as the ulConfig +// parameter. For each group (i.e. COMP_TRIG_xxx, COMP_INT_xxx, etc.), one of +// the values may be selected and ORed together will values from the other +// groups. +// +//***************************************************************************** +#define COMP_TRIG_NONE 0x00000000 // No ADC trigger +#define COMP_TRIG_HIGH 0x00000880 // Trigger when high +#define COMP_TRIG_LOW 0x00000800 // Trigger when low +#define COMP_TRIG_FALL 0x00000820 // Trigger on falling edge +#define COMP_TRIG_RISE 0x00000840 // Trigger on rising edge +#define COMP_TRIG_BOTH 0x00000860 // Trigger on both edges +#define COMP_INT_HIGH 0x00000010 // Interrupt when high +#define COMP_INT_LOW 0x00000000 // Interrupt when low +#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge +#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge +#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges +#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin +#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin +#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference +#define COMP_OUTPUT_NONE 0x00000000 // No comparator output +#define COMP_OUTPUT_NORMAL 0x00000100 // Comparator output normal +#define COMP_OUTPUT_INVERT 0x00000102 // Comparator output inverted + +//***************************************************************************** +// +// Values that can be passed to ComparatorSetRef() as the ulRef parameter. +// +//***************************************************************************** +#define COMP_REF_OFF 0x00000000 // Turn off the internal reference +#define COMP_REF_0V 0x00000300 // Internal reference of 0V +#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V +#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V +#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V +#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V +#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V +#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V +#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V +#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V +#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V +#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V +#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V +#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V +#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V +#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V +#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V +#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V +#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V +#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V +#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V +#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V +#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V +#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V +#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V +#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V +#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V +#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V +#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp, + unsigned long ulConfig); +extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef); +extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp); +extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp, + void (*pfnHandler)(void)); +extern void ComparatorIntUnregister(unsigned long ulBase, + unsigned long ulComp); +extern void ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp); +extern void ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp); +extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp, + tBoolean bMasked); +extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp); + +#ifdef __cplusplus +} +#endif + +#endif // __COMP_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/cpu.h b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/cpu.h new file mode 100644 index 000000000..a71928c99 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/cpu.h @@ -0,0 +1,40 @@ +//***************************************************************************** +// +// cpu.h - Prototypes for the CPU instruction wrapper functions. +// +// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __CPU_H__ +#define __CPU_H__ + +//***************************************************************************** +// +// Prototypes. +// +//***************************************************************************** +extern void CPUcpsid(void); +extern void CPUcpsie(void); +extern void CPUwfi(void); + +#endif // __CPU_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/debug.h b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/debug.h new file mode 100644 index 000000000..0000ed346 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/debug.h @@ -0,0 +1,56 @@ +//***************************************************************************** +// +// debug.h - Macros for assisting debug of the driver library. +// +// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __DEBUG_H__ +#define __DEBUG_H__ + +//***************************************************************************** +// +// Prototype for the function that is called when an invalid argument is passed +// to an API. This is only used when doing a DEBUG build. +// +//***************************************************************************** +extern void __error__(char *pcFilename, unsigned long ulLine); + +//***************************************************************************** +// +// The ASSERT macro, which does the actual assertion checking. Typically, this +// will be for procedure arguments. +// +//***************************************************************************** +#ifdef DEBUG +#define ASSERT(expr) { \ + if(!(expr)) \ + { \ + __error__(__FILE__, __LINE__); \ + } \ + } +#else +#define ASSERT(expr) +#endif + +#endif // __DEBUG_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/flash.h b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/flash.h new file mode 100644 index 000000000..f8ff60a12 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/flash.h @@ -0,0 +1,75 @@ +//***************************************************************************** +// +// flash.h - Prototypes for the flash driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __FLASH_H__ +#define __FLASH_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to FlashProtectSet(), and returned by +// FlashProtectGet(). +// +//***************************************************************************** +typedef enum +{ + FlashReadWrite, // Flash can be read and written + FlashReadOnly, // Flash can only be read + FlashExecuteOnly // Flash can only be executed +} +tFlashProtection; + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern unsigned long FlashUsecGet(void); +extern void FlashUsecSet(unsigned long ulClocks); +extern long FlashErase(unsigned long ulAddress); +extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress, + unsigned long ulCount); +extern tFlashProtection FlashProtectGet(unsigned long ulAddress); +extern long FlashProtectSet(unsigned long ulAddress, + tFlashProtection eProtect); +extern long FlashProtectSave(void); +extern void FlashIntRegister(void (*pfnHandler)(void)); +extern void FlashIntUnregister(void); +extern void FlashIntEnable(unsigned long ulIntFlags); +extern void FlashIntDisable(unsigned long ulIntFlags); +extern unsigned long FlashIntGetStatus(tBoolean bMasked); +extern void FlashIntClear(unsigned long ulIntFlags); + +#ifdef __cplusplus +} +#endif + +#endif // __FLASH_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/gpio.h b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/gpio.h new file mode 100644 index 000000000..ec682b54d --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/gpio.h @@ -0,0 +1,137 @@ +//***************************************************************************** +// +// gpio.h - Defines and Macros for GPIO API. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __GPIO_H__ +#define __GPIO_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following values define the bit field for the ucPins argument to several +// of the APIs. +// +//***************************************************************************** +#define GPIO_PIN_0 0x00000001 // GPIO pin 0 +#define GPIO_PIN_1 0x00000002 // GPIO pin 1 +#define GPIO_PIN_2 0x00000004 // GPIO pin 2 +#define GPIO_PIN_3 0x00000008 // GPIO pin 3 +#define GPIO_PIN_4 0x00000010 // GPIO pin 4 +#define GPIO_PIN_5 0x00000020 // GPIO pin 5 +#define GPIO_PIN_6 0x00000040 // GPIO pin 6 +#define GPIO_PIN_7 0x00000080 // GPIO pin 7 + +//***************************************************************************** +// +// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and +// returned from GPIODirModeGet. +// +//***************************************************************************** +#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input +#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output +#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function + +//***************************************************************************** +// +// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and +// returned from GPIOIntTypeGet. +// +//***************************************************************************** +#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge +#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge +#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges +#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level +#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level + +//***************************************************************************** +// +// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter, +// and returned by GPIOPadConfigGet in the *pulStrength parameter. +// +//***************************************************************************** +#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength +#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength +#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength +#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control + +//***************************************************************************** +// +// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter, +// and returned by GPIOPadConfigGet in the *pulPadType parameter. +// +//***************************************************************************** +#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull +#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up +#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down +#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain +#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up +#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down +#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulPinIO); +extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin); +extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulIntType); +extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin); +extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulStrength, + unsigned long ulPadType); +extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin, + unsigned long *pulStrength, + unsigned long *pulPadType); +extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins); +extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked); +extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPortIntRegister(unsigned long ulPort, + void (*pfIntHandler)(void)); +extern void GPIOPortIntUnregister(unsigned long ulPort); +extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, + unsigned char ucVal); +extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins); + +#ifdef __cplusplus +} +#endif + +#endif // __GPIO_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/i2c.h b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/i2c.h new file mode 100644 index 000000000..88234a862 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/i2c.h @@ -0,0 +1,137 @@ +//***************************************************************************** +// +// i2c.h - Prototypes for the I2C Driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __I2C_H__ +#define __I2C_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Defines for the API. +// +//***************************************************************************** +//***************************************************************************** +// +// Interrupt defines. +// +//***************************************************************************** +#define I2C_INT_MASTER 0x00000001 +#define I2C_INT_SLAVE 0x00000002 + +//***************************************************************************** +// +// I2C Master commands. +// +//***************************************************************************** +#define I2C_MASTER_CMD_SINGLE_SEND \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_SINGLE_RECEIVE \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_SEND_START \ + (I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_SEND_CONT \ + (I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_SEND_FINISH \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \ + (I2C_MASTER_CS_STOP) +#define I2C_MASTER_CMD_BURST_RECEIVE_START \ + (I2C_MASTER_CS_ACK | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \ + (I2C_MASTER_CS_ACK | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) +#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \ + (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) + +//***************************************************************************** +// +// I2C Master error status. +// +//***************************************************************************** +#define I2C_MASTER_ERR_NONE 0 +#define I2C_MASTER_ERR_ADDR_ACK 0x00000004 +#define I2C_MASTER_ERR_DATA_ACK 0x00000008 +#define I2C_MASTER_ERR_ARB_LOST 0x00000010 + +//***************************************************************************** +// +// I2C Slave action requests +// +//***************************************************************************** +#define I2C_SLAVE_ACT_NONE 0 +#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data +#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data + +//***************************************************************************** +// Miscellaneous I2C driver definitions. +//***************************************************************************** +#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void)); +extern void I2CIntUnregister(unsigned long ulBase); +extern tBoolean I2CMasterBusBusy(unsigned long ulBase); +extern tBoolean I2CMasterBusy(unsigned long ulBase); +extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd); +extern unsigned long I2CMasterDataGet(unsigned long ulBase); +extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData); +extern void I2CMasterDisable(unsigned long ulBase); +extern void I2CMasterEnable(unsigned long ulBase); +extern unsigned long I2CMasterErr(unsigned long ulBase); +extern void I2CMasterInit(unsigned long ulBase, tBoolean bFast); +extern void I2CMasterIntClear(unsigned long ulBase); +extern void I2CMasterIntDisable(unsigned long ulBase); +extern void I2CMasterIntEnable(unsigned long ulBase); +extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void I2CMasterSlaveAddrSet(unsigned long ulBase, + unsigned char ucSlaveAddr, + tBoolean bReceive); +extern unsigned long I2CSlaveDataGet(unsigned long ulBase); +extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData); +extern void I2CSlaveDisable(unsigned long ulBase); +extern void I2CSlaveEnable(unsigned long ulBase); +extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr); +extern void I2CSlaveIntClear(unsigned long ulBase); +extern void I2CSlaveIntDisable(unsigned long ulBase); +extern void I2CSlaveIntEnable(unsigned long ulBase); +extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked); +extern unsigned long I2CSlaveStatus(unsigned long ulBase); + +#ifdef __cplusplus +} +#endif + +#endif // __I2C_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/interrupt.h b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/interrupt.h new file mode 100644 index 000000000..edd8a0897 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/interrupt.h @@ -0,0 +1,57 @@ +//***************************************************************************** +// +// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void IntMasterEnable(void); +extern void IntMasterDisable(void); +extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)); +extern void IntUnregister(unsigned long ulInterrupt); +extern void IntPriorityGroupingSet(unsigned long ulBits); +extern unsigned long IntPriorityGroupingGet(void); +extern void IntPrioritySet(unsigned long ulInterrupt, + unsigned char ucPriority); +extern long IntPriorityGet(unsigned long ulInterrupt); +extern void IntEnable(unsigned long ulInterrupt); +extern void IntDisable(unsigned long ulInterrupt); + +#ifdef __cplusplus +} +#endif + +#endif // __INTERRUPT_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/pwm.h b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/pwm.h new file mode 100644 index 000000000..0986833db --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/pwm.h @@ -0,0 +1,161 @@ +//***************************************************************************** +// +// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __PWM_H__ +#define __PWM_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following defines are passed to PWMGenConfigure() as the ulConfig +// parameter and specify the configuration of the PWM generator. +// +//***************************************************************************** +#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode +#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode +#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates +#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates +#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode +#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode + +//***************************************************************************** +// +// Defines for enabling, disabling, and clearing PWM generator interrupts and +// triggers. +// +//***************************************************************************** +#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0 +#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD +#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U +#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D +#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U +#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D +#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0 +#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD +#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U +#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D +#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U +#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D + +//***************************************************************************** +// +// Defines for enabling, disabling, and clearing PWM interrupts. +// +//***************************************************************************** +#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt +#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt +#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt +#define PWM_INT_FAULT 0x00010000 // Fault interrupt + +//***************************************************************************** +// +// Defines to identify the generators within a module. +// +//***************************************************************************** +#define PWM_GEN_0 0x00000040 // Offset address of Gen0 +#define PWM_GEN_1 0x00000080 // Offset address of Gen1 +#define PWM_GEN_2 0x000000C0 // Offset address of Gen2 + +#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0 +#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1 +#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2 + +//***************************************************************************** +// +// Defines to identify the outputs within a module. +// +//***************************************************************************** +#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0 +#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1 +#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2 +#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3 +#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4 +#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5 + +#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0 +#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1 +#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2 +#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3 +#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4 +#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5 + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen, + unsigned long ulConfig); +extern void PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen, + unsigned long ulPeriod); +extern unsigned long PWMGenPeriodGet(unsigned long ulBase, + unsigned long ulGen); +extern void PWMGenEnable(unsigned long ulBase, unsigned long ulGen); +extern void PWMGenDisable(unsigned long ulBase, unsigned long ulGen); +extern void PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut, + unsigned long ulWidth); +extern unsigned long PWMPulseWidthGet(unsigned long ulBase, + unsigned long ulPWMOut); +extern void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen, + unsigned short usRise, unsigned short usFall); +extern void PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen); +extern void PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits); +extern void PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits); +extern void PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bEnable); +extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bInvert); +extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bFaultKill); +extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen, + void (*pfIntHandler)(void)); +extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen); +extern void PWMFaultIntRegister(unsigned long ulBase, + void (*pfIntHandler)(void)); +extern void PWMFaultIntUnregister(unsigned long ulBase); +extern void PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen, + unsigned long ulIntTrig); +extern void PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen, + unsigned long ulIntTrig); +extern unsigned long PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen, + tBoolean bMasked); +extern void PWMGenIntClear(unsigned long ulBase, unsigned long ulGen, + unsigned long ulInts); +extern void PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault); +extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault); +extern void PWMFaultIntClear(unsigned long ulBase); +extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked); + +#ifdef __cplusplus +} +#endif + +#endif // __PWM_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/qei.h b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/qei.h new file mode 100644 index 000000000..9cea48b89 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/qei.h @@ -0,0 +1,104 @@ +//***************************************************************************** +// +// qei.h - Prototypes for the Quadrature Encoder Driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __QEI_H__ +#define __QEI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to QEIConfigure as the ulConfig paramater. +// +//***************************************************************************** +#define QEI_CONFIG_CAPTURE_A 0x00000000 // Count on ChA edges only +#define QEI_CONFIG_CAPTURE_A_B 0x00000008 // Count on ChA and ChB edges +#define QEI_CONFIG_NO_RESET 0x00000000 // Do not reset on index pulse +#define QEI_CONFIG_RESET_IDX 0x00000010 // Reset position on index pulse +#define QEI_CONFIG_QUADRATURE 0x00000000 // ChA and ChB are quadrature +#define QEI_CONFIG_CLOCK_DIR 0x00000004 // ChA and ChB are clock and dir +#define QEI_CONFIG_NO_SWAP 0x00000000 // Do not swap ChA and ChB +#define QEI_CONFIG_SWAP 0x00000002 // Swap ChA and ChB + +//***************************************************************************** +// +// Values that can be passed to QEIVelocityConfigure as the ulPreDiv parameter. +// +//***************************************************************************** +#define QEI_VELDIV_1 0x00000000 // Predivide by 1 +#define QEI_VELDIV_2 0x00000040 // Predivide by 2 +#define QEI_VELDIV_4 0x00000080 // Predivide by 4 +#define QEI_VELDIV_8 0x000000C0 // Predivide by 8 +#define QEI_VELDIV_16 0x00000100 // Predivide by 16 +#define QEI_VELDIV_32 0x00000140 // Predivide by 32 +#define QEI_VELDIV_64 0x00000180 // Predivide by 64 +#define QEI_VELDIV_128 0x000001C0 // Predivide by 128 + +//***************************************************************************** +// +// Values that can be passed to QEIEnableInts, QEIDisableInts, and QEIClearInts +// as the ulIntFlags parameter, and returned by QEIGetIntStatus. +// +//***************************************************************************** +#define QEI_INTERROR 0x00000008 // Phase error detected +#define QEI_INTDIR 0x00000004 // Direction change +#define QEI_INTTIMER 0x00000002 // Velocity timer expired +#define QEI_INTINDEX 0x00000001 // Index pulse detected + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void QEIEnable(unsigned long ulBase); +extern void QEIDisable(unsigned long ulBase); +extern void QEIConfigure(unsigned long ulBase, unsigned long ulConfig, + unsigned long ulMaxPosition); +extern unsigned long QEIPositionGet(unsigned long ulBase); +extern void QEIPositionSet(unsigned long ulBase, unsigned long ulPosition); +extern long QEIDirectionGet(unsigned long ulBase); +extern tBoolean QEIErrorGet(unsigned long ulBase); +extern void QEIVelocityEnable(unsigned long ulBase); +extern void QEIVelocityDisable(unsigned long ulBase); +extern void QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv, + unsigned long ulPeriod); +extern unsigned long QEIVelocityGet(unsigned long ulBase); +extern void QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); +extern void QEIIntUnregister(unsigned long ulBase); +extern void QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long QEIIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags); + +#ifdef __cplusplus +} +#endif + +#endif // __QEI_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/ssi.h b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/ssi.h new file mode 100644 index 000000000..b697a1069 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/ssi.h @@ -0,0 +1,88 @@ +//***************************************************************************** +// +// ssi.h - Prototypes for the Synchronous Serial Interface Driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __SSI_H__ +#define __SSI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear +// as the ulIntFlags parameter, and returned by SSIIntStatus. +// +//***************************************************************************** +#define SSI_TXFF 0x00000008 // TX FIFO half empty or less +#define SSI_RXFF 0x00000004 // RX FIFO half full or less +#define SSI_RXTO 0x00000002 // RX timeout +#define SSI_RXOR 0x00000001 // RX overrun + +//***************************************************************************** +// +// Values that can be passed to SSIConfig. +// +//***************************************************************************** +#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0 +#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1 +#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0 +#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1 +#define SSI_FRF_TI 0x00000010 // TI frame format +#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format + +#define SSI_MODE_MASTER 0x00000000 // SSI master +#define SSI_MODE_SLAVE 0x00000001 // SSI slave +#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void SSIConfig(unsigned long ulBase, unsigned long ulProtocol, + unsigned long ulMode, unsigned long ulBitRate, + unsigned long ulDataWidth); +extern void SSIDataGet(unsigned long ulBase, unsigned long *ulData); +extern long SSIDataNonBlockingGet(unsigned long ulBase, unsigned long *ulData); +extern void SSIDataPut(unsigned long ulBase, unsigned long ulData); +extern long SSIDataNonBlockingPut(unsigned long ulBase, unsigned long ulData); +extern void SSIDisable(unsigned long ulBase); +extern void SSIEnable(unsigned long ulBase); +extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void SSIIntUnregister(unsigned long ulBase); + +#ifdef __cplusplus +} +#endif + +#endif // __SSI_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/sysctl.h b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/sysctl.h new file mode 100644 index 000000000..098013d63 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/sysctl.h @@ -0,0 +1,285 @@ +//***************************************************************************** +// +// sysctl.h - Prototypes for the system control driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __SYSCTL_H__ +#define __SYSCTL_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed to the +// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(), +// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the +// ulPeripheral parameter. The peripherals in the fourth group (upper nibble +// is 3) can only be used with the SysCtlPeripheralPresent() API. +// +//***************************************************************************** +#define SYSCTL_PERIPH_PWM 0x00100000 // PWM +#define SYSCTL_PERIPH_ADC 0x00010000 // ADC +#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog +#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0 +#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1 +#define SYSCTL_PERIPH_SSI 0x10000010 // SSI +#define SYSCTL_PERIPH_QEI 0x10000100 // QEI +#define SYSCTL_PERIPH_I2C 0x10001000 // I2C +#define SYSCTL_PERIPH_TIMER0 0x10010000 // Timer 0 +#define SYSCTL_PERIPH_TIMER1 0x10020000 // Timer 1 +#define SYSCTL_PERIPH_TIMER2 0x10040000 // Timer 2 +#define SYSCTL_PERIPH_COMP0 0x11000000 // Analog comparator 0 +#define SYSCTL_PERIPH_COMP1 0x12000000 // Analog comparator 1 +#define SYSCTL_PERIPH_COMP2 0x14000000 // Analog comparator 2 +#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A +#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B +#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C +#define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D +#define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E +#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex M3 MPU +#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor +#define SYSCTL_PERIPH_PLL 0x30000010 // PLL + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlPinPresent() API +// as the ulPin parameter. +// +//***************************************************************************** +#define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin +#define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin +#define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin +#define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin +#define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin +#define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin +#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin +#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin +#define SYSCTL_PIN_C0O 0x00000100 // C0o pin +#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin +#define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin +#define SYSCTL_PIN_C1O 0x00000800 // C1o pin +#define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin +#define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin +#define SYSCTL_PIN_C2O 0x00004000 // C2o pin +#define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin +#define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin +#define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin +#define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin +#define SYSCTL_PIN_ADC4 0x00100000 // ADC4 pin +#define SYSCTL_PIN_ADC5 0x00200000 // ADC5 pin +#define SYSCTL_PIN_ADC6 0x00400000 // ADC6 pin +#define SYSCTL_PIN_ADC7 0x00800000 // ADC7 pin +#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin +#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin +#define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin +#define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin +#define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin +#define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin +#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlLDOSet() API as +// the ulVoltage value, or returned by the SysCtlLDOGet() API. +// +//***************************************************************************** +#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V +#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V +#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V +#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V +#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V +#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V +#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V +#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V +#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V +#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V +#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlLDOConfigSet() API. +// +//***************************************************************************** +#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset +#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlIntEnable(), +// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask +// by the SysCtlIntStatus() API. +// +//***************************************************************************** +#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt +#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt +#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int +#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int +#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt +#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt +#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlResetCauseClear() +// API or returned by the SysCtlResetCauseGet() API. +// +//***************************************************************************** +#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset +#define SYSCTL_CAUSE_SW 0x00000010 // Software reset +#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset +#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset +#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset +#define SYSCTL_CAUSE_EXT 0x00000001 // External reset + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlBrownOutConfigSet() +// API as the ulConfig parameter. +// +//***************************************************************************** +#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting +#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlPWMClockSet() API +// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet() +// API. +// +//***************************************************************************** +#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1 +#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2 +#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4 +#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8 +#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16 +#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32 +#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64 + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlADCSpeedSet() API +// as the ulSpeed parameter, and can be returned by the SyCtlADCSpeedGet() +// API. +// +//***************************************************************************** +#define SYSCTL_ADCSPEED_1MSPS 0x00000300 // 1,000,000 samples per second +#define SYSCTL_ADCSPEED_500KSPS 0x00000200 // 500,000 samples per second +#define SYSCTL_ADCSPEED_250KSPS 0x00000100 // 250,000 samples per second +#define SYSCTL_ADCSPEED_125KSPS 0x00000000 // 125,000 samples per second + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlClockSet() API as +// the ulConfig parameter. +// +//***************************************************************************** +#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1 +#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2 +#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3 +#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4 +#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5 +#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6 +#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7 +#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8 +#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9 +#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10 +#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11 +#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12 +#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13 +#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14 +#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15 +#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16 +#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock +#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock +#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz +#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz +#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz +#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz +#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz +#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz +#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz +#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz +#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz +#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz +#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz +#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz +#define SYSCTL_OSC_MAIN 0x00000000 // Oscillator source is main osc +#define SYSCTL_OSC_INT 0x00000010 // Oscillator source is int. osc +#define SYSCTL_OSC_INT4 0x00000020 // Oscillator source is int. osc /4 +#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator +#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern unsigned long SysCtlSRAMSizeGet(void); +extern unsigned long SysCtlFlashSizeGet(void); +extern tBoolean SysCtlPinPresent(unsigned long ulPin); +extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral); +extern void SysCtlPeripheralReset(unsigned long ulPeripheral); +extern void SysCtlPeripheralEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralClockGating(tBoolean bEnable); +extern void SysCtlIntRegister(void (*pfnHandler)(void)); +extern void SysCtlIntUnregister(void); +extern void SysCtlIntEnable(unsigned long ulInts); +extern void SysCtlIntDisable(unsigned long ulInts); +extern void SysCtlIntClear(unsigned long ulInts); +extern unsigned long SysCtlIntStatus(tBoolean bMasked); +extern void SysCtlLDOSet(unsigned long ulVoltage); +extern unsigned long SysCtlLDOGet(void); +extern void SysCtlLDOConfigSet(unsigned long ulConfig); +extern void SysCtlReset(void); +extern void SysCtlSleep(void); +extern void SysCtlDeepSleep(void); +extern unsigned long SysCtlResetCauseGet(void); +extern void SysCtlResetCauseClear(unsigned long ulCauses); +extern void SysCtlBrownOutConfigSet(unsigned long ulConfig, + unsigned long ulDelay); +extern void SysCtlClockSet(unsigned long ulConfig); +extern unsigned long SysCtlClockGet(void); +extern void SysCtlPWMClockSet(unsigned long ulConfig); +extern unsigned long SysCtlPWMClockGet(void); +extern void SysCtlADCSpeedSet(unsigned long ulSpeed); +extern unsigned long SysCtlADCSpeedGet(void); +extern void SysCtlIOSCVerificationSet(tBoolean bEnable); +extern void SysCtlMOSCVerificationSet(tBoolean bEnable); +extern void SysCtlPLLVerificationSet(tBoolean bEnable); +extern void SysCtlClkVerificationClear(void); + +#ifdef __cplusplus +} +#endif + +#endif // __SYSCTL_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/systick.h b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/systick.h new file mode 100644 index 000000000..beffd88b7 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/systick.h @@ -0,0 +1,55 @@ +//***************************************************************************** +// +// systick.h - Prototypes for the SysTick driver. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __SYSTICK_H__ +#define __SYSTICK_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void SysTickEnable(void); +extern void SysTickDisable(void); +extern void SysTickIntRegister(void (*pfnHandler)(void)); +extern void SysTickIntUnregister(void); +extern void SysTickIntEnable(void); +extern void SysTickIntDisable(void); +extern void SysTickPeriodSet(unsigned long ulPeriod); +extern unsigned long SysTickPeriodGet(void); +extern unsigned long SysTickValueGet(void); + +#ifdef __cplusplus +} +#endif + +#endif // __SYSTICK_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/timer.h b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/timer.h new file mode 100644 index 000000000..ef98c0d71 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/timer.h @@ -0,0 +1,137 @@ +//***************************************************************************** +// +// timer.h - Prototypes for the timer module +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __TIMER_H__ +#define __TIMER_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to TimerConfigure as the ulConfig parameter. +// +//***************************************************************************** +#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer +#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer +#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer +#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers +#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer +#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer +#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter +#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer +#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output +#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer +#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer +#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter +#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer +#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output + +//***************************************************************************** +// +// Values that can be passed to TimerIntEnable, TimerIntDisable, and +// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus. +// +//***************************************************************************** +#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt +#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt +#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt +#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask +#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt +#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt +#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt + +//***************************************************************************** +// +// Values that can be passed to TimerControlEvent as the ulEvent parameter. +// +//***************************************************************************** +#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges +#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges +#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges + +//***************************************************************************** +// +// Values that can be passed to most of the timer APIs as the ulTimer +// parameter. +// +//***************************************************************************** +#define TIMER_A 0x000000ff // Timer A +#define TIMER_B 0x0000ff00 // Timer B +#define TIMER_BOTH 0x0000ffff // Timer Both + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer); +extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer); +extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig); +extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, + tBoolean bInvert); +extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer, + tBoolean bEnable); +extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulEvent); +extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer, + tBoolean bStall); +extern void TimerRTCEnable(unsigned long ulBase); +extern void TimerRTCDisable(unsigned long ulBase); +extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerPrescaleGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer); +extern unsigned long TimerValueGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerMatchGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, + void (*pfnHandler)(void)); +extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer); +extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void TimerQuiesce(unsigned long ulBase); + +#ifdef __cplusplus +} +#endif + +#endif // __TIMER_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/uart.h b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/uart.h new file mode 100644 index 000000000..43eb8d544 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/uart.h @@ -0,0 +1,102 @@ +//***************************************************************************** +// +// uart.h - Defines and Macros for the UART. +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __UART_H__ +#define __UART_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear +// as the ulIntFlags parameter, and returned from UARTIntStatus. +// +//***************************************************************************** +#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask +#define UART_INT_BE 0x200 // Break Error Interrupt Mask +#define UART_INT_PE 0x100 // Parity Error Interrupt Mask +#define UART_INT_FE 0x080 // Framing Error Interrupt Mask +#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask +#define UART_INT_TX 0x020 // Transmit Interrupt Mask +#define UART_INT_RX 0x010 // Receive Interrupt Mask + +//***************************************************************************** +// +// Values that can be passed to UARTConfigSet as the ulConfig parameter and +// returned by UARTConfigGet in the pulConfig parameter. Additionally, the +// UART_CONFIG_PAR_* subset can be passed to UARTParityModeSet as the ulParity +// parameter, and are returned by UARTParityModeGet. +// +//***************************************************************************** +#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data +#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data +#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data +#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data +#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit +#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits +#define UART_CONFIG_PAR_NONE 0x00000000 // No parity +#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity +#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity +#define UART_CONFIG_PAR_ONE 0x00000086 // Parity bit is one +#define UART_CONFIG_PAR_ZERO 0x00000082 // Parity bit is zero + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity); +extern unsigned long UARTParityModeGet(unsigned long ulBase); +extern void UARTConfigSet(unsigned long ulBase, unsigned long ulBaud, + unsigned long ulConfig); +extern void UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud, + unsigned long *pulConfig); +extern void UARTEnable(unsigned long ulBase); +extern void UARTDisable(unsigned long ulBase); +extern tBoolean UARTCharsAvail(unsigned long ulBase); +extern tBoolean UARTSpaceAvail(unsigned long ulBase); +extern long UARTCharNonBlockingGet(unsigned long ulBase); +extern long UARTCharGet(unsigned long ulBase); +extern tBoolean UARTCharNonBlockingPut(unsigned long ulBase, + unsigned char ucData); +extern void UARTCharPut(unsigned long ulBase, unsigned char ucData); +extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState); +extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern void UARTIntUnregister(unsigned long ulBase); +extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags); + +#ifdef __cplusplus +} +#endif + +#endif // __UART_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/watchdog.h b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/watchdog.h new file mode 100644 index 000000000..ad8bc45ef --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/watchdog.h @@ -0,0 +1,63 @@ +//***************************************************************************** +// +// watchdog.h - Prototypes for the Watchdog Timer API +// +// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's Stellaris Family of microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 816 of the Stellaris Driver Library. +// +//***************************************************************************** + +#ifndef __WATCHDOG_H__ +#define __WATCHDOG_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern tBoolean WatchdogRunning(unsigned long ulBase); +extern void WatchdogEnable(unsigned long ulBase); +extern void WatchdogResetEnable(unsigned long ulBase); +extern void WatchdogResetDisable(unsigned long ulBase); +extern void WatchdogLock(unsigned long ulBase); +extern void WatchdogUnlock(unsigned long ulBase); +extern tBoolean WatchdogLockState(unsigned long ulBase); +extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal); +extern unsigned long WatchdogReloadGet(unsigned long ulBase); +extern unsigned long WatchdogValueGet(unsigned long ulBase); +extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern void WatchdogIntUnregister(unsigned long ulBase); +extern void WatchdogIntEnable(unsigned long ulBase); +extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void WatchdogIntClear(unsigned long ulBase); +extern void WatchdogStallDisable(unsigned long ulBase); +extern void WatchdogStallDisable(unsigned long ulBase); + +#ifdef __cplusplus +} +#endif + +#endif // __WATCHDOG_H__ diff --git a/20080212/Demo/CORTEX_LM3S811_KEIL/RTOSDemo.Opt b/20080212/Demo/CORTEX_LM3S811_KEIL/RTOSDemo.Opt new file mode 100644 index 000000000..a78d564ce --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_KEIL/RTOSDemo.Opt @@ -0,0 +1,54 @@ +### uVision2 Project, (C) Keil Software +### Do not modify ! + + cExt (*.c) + aExt (*.s*; *.src; *.a*) + oExt (*.obj) + lExt (*.lib) + tExt (*.txt; *.h; *.inc) + pExt (*.plm) + CppX (*.cpp) + DaveTm { 0,0,0,0,0,0,0,0 } + +Target (FreeRTOS_Demo), 0x0004 // Tools: 'ARM-ADS' +GRPOPT 1,(Demo_Source),1,0,0 +GRPOPT 2,(Libraries),1,0,0 +GRPOPT 3,(RTOS_Source),1,0,0 +GRPOPT 4,(Documentation),1,0,0 + +OPTFFF 1,1,2,0,0,0,0,0,<.\startup_rvmdk.S> +OPTFFF 1,2,1,167772160,0,0,0,0,<.\LuminaryCode\osram96x16.c> +OPTFFF 1,3,1,0,0,0,0,0,<.\main.c> +OPTFFF 1,4,1,0,0,0,0,0,<..\Common\Minimal\semtest.c> +OPTFFF 1,5,1,989855744,0,0,0,0,<..\Common\Minimal\integer.c> +OPTFFF 1,6,1,939524096,0,0,0,0,<..\Common\Minimal\PollQ.c> +OPTFFF 1,7,1,201326592,0,0,0,0,<..\Common\Minimal\BlockQ.c> +OPTFFF 1,8,1,0,0,0,0,0,<.\heap\heap_1.c> +OPTFFF 2,9,4,0,0,0,0,0, +OPTFFF 3,10,1,0,0,0,0,0,<..\..\Source\tasks.c> +OPTFFF 3,11,1,0,0,0,0,0,<..\..\Source\list.c> +OPTFFF 3,12,1,0,0,0,0,0,<..\..\Source\queue.c> +OPTFFF 3,13,1,0,0,0,0,0,<..\..\Source\portable\RVDS\ARM_CM3\port.c> +OPTFFF 4,14,5,2,0,1,1,0,<.\readme.txt> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,66,0,0,0,99,0,0,0,22,4,0,0,64,2,0,0 } + +ExtF <.\readme.txt> 1,1,0,{ 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,66,0,0,0,99,0,0,0,22,4,0,0,64,2,0,0 } + +TARGOPT 1, (FreeRTOS_Demo) + ADSCLK=50000000 + OPTTT 1,1,1,0 + OPTHX 1,65535,0,0,0 + OPTLX 79,66,8,<.\rvmdk\> + OPTOX 16 + OPTLT 1,1,1,0,1,1,0,1,0,0,0,0 + OPTXL 1,1,1,1,1,1,1,0,0 + OPTFL 1,0,1 + OPTDL (SARMCM3.DLL)()(DLM.DLL)(-pLM3S811)(SARMCM3.DLL)()(TLM.DLL)(-pLM3S811) + OPTDBG 48126,4,()()()()()()()()()() (BIN\lmidk-agdi.dll)()()() + OPTKEY 0,(DLGTARM)() + OPTKEY 0,(ARMDBGFLAGS)(-T5F) + OPTKEY 0,(LMIDK-AGDI)(-B0 -O1792) + OPTDF 0x84 + OPTLE <> + OPTLC <> +EndOpt + diff --git a/20080212/Demo/CORTEX_LM3S811_KEIL/RTOSDemo.Uv2 b/20080212/Demo/CORTEX_LM3S811_KEIL/RTOSDemo.Uv2 new file mode 100644 index 000000000..737a39bf0 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_KEIL/RTOSDemo.Uv2 @@ -0,0 +1,113 @@ +### uVision2 Project, (C) Keil Software +### Do not modify ! + +Target (FreeRTOS_Demo), 0x0004 // Tools: 'ARM-ADS' + +Group (Demo_Source) +Group (Libraries) +Group (RTOS_Source) +Group (Documentation) + +File 1,2,<.\startup_rvmdk.S> 0x45431C95 +File 1,1,<.\LuminaryCode\osram96x16.c> 0x452BAD20 +File 1,1,<.\main.c> 0x452A35C1 +File 1,1,<..\Common\Minimal\semtest.c> 0x452A35D8 +File 1,1,<..\Common\Minimal\integer.c> 0x452A35D8 +File 1,1,<..\Common\Minimal\PollQ.c> 0x452A35D8 +File 1,1,<..\Common\Minimal\BlockQ.c> 0x4538ECC1 +File 1,1,<.\heap\heap_1.c> 0x45431CD6 +File 2,4, 0x44F892D1 +File 3,1,<..\..\Source\tasks.c> 0x452A35A8 +File 3,1,<..\..\Source\list.c> 0x452A35BA +File 3,1,<..\..\Source\queue.c> 0x452A35BA +File 3,1,<..\..\Source\portable\RVDS\ARM_CM3\port.c> 0x452A35FB +File 4,5,<.\readme.txt> 0x44FC00DA + + +Options 1,0,0 // Target 'FreeRTOS_Demo' + Device (LM3S811) + Vendor (Luminary Micro) + Cpu (IRAM(0x20000000-0x20001fff) IROM(0-0xffff) CLOCK(50000000) CPUTYPE("Cortex-M3")) + FlashUt () + StupF ("STARTUP\Luminary\Startup.s" ("Luminary Startup Code")) + FlashDR (LMIDK-AGDI(-U40296420 -O7 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0LM3S_8 -FS00 -FL02000)) + DevID (4079) + Rgf (LM3Sxxx.H) + Mem () + C () + A () + RL () + OH () + DBC_IFX () + DBC_CMS () + DBC_AMS () + DBC_LMS () + UseEnv=0 + EnvBin () + EnvInc () + EnvLib () + EnvReg (ÿLuminary\) + OrgReg (ÿLuminary\) + TgStat=16 + OutDir (.\rvmdk\) + OutName (RTOSDemo) + GenApp=1 + GenLib=0 + GenHex=0 + Debug=1 + Browse=1 + LstDir (.\rvmdk\) + HexSel=1 + MG32K=0 + TGMORE=0 + RunUsr 0 0 <> + RunUsr 1 0 <> + BrunUsr 0 0 <> + BrunUsr 1 0 <> + SVCSID <> + GLFLAGS=1790 + ADSFLGA { 176,3,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ACPUTYP (Cortex-M3) + ADSTFLGA { 0,12,0,0,99,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + OCMADSOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + OCMADSIRAM { 0,0,0,0,32,0,32,0,0 } + OCMADSIROM { 1,0,0,0,0,0,0,1,0 } + OCMADSXRAM { 0,0,0,0,0,0,0,0,0 } + OCR_RVCT { 1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,32,0,0,0,0,0,0,0,0,0,0,0 } + RV_STAVEC () + ADSCCFLG { 9,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ADSCMISC () + ADSCDEFN (RVDS_ARMCM3_LM3S102) + ADSCUDEF () + ADSCINCD (.;./LuminaryCode;..\..\Source\portable\RVDS\ARM_CM3;..\..\Source\include;..\Common\include) + ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ADSAMISC () + ADSADEFN () + ADSAUDEF () + ADSAINCD () + PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + IncBld=1 + AlwaysBuild=0 + GenAsm=0 + AsmAsm=0 + PublicsOnly=0 + StopCode=3 + CustArgs () + LibMods () + ADSLDFG { 17,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ADSLDTA (0x00000000) + ADSLDDA (0x20000000) + ADSLDSC () + ADSLDIB () + ADSLDIC () + ADSLDMC (--entry Reset_Handler --last xHeap) + ADSLDIF () + ADSLDDW () + OPTDL (SARMCM3.DLL)()(DLM.DLL)(-pLM3S811)(SARMCM3.DLL)()(TLM.DLL)(-pLM3S811) + OPTDBG 48126,4,()()()()()()()()()() (BIN\lmidk-agdi.dll)()()() + FLASH1 { 1,0,0,0,1,0,0,0,3,0,0,0,0,0,0,0,0,0,0,0 } + FLASH2 (BIN\LMIDK-AGDI.DLL) + FLASH3 ("" ()) + FLASH4 () +EndOpt + diff --git a/20080212/Demo/CORTEX_LM3S811_KEIL/heap/heap_1.c b/20080212/Demo/CORTEX_LM3S811_KEIL/heap/heap_1.c new file mode 100644 index 000000000..34828f31e --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_KEIL/heap/heap_1.c @@ -0,0 +1,130 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + + +/* + * The simplest possible implementation of pvPortMalloc(). Note that this + * implementation does NOT allow allocated memory to be freed again. + * + * See heap_2.c and heap_3.c for alternative implementations, and the memory + * management pages of http://www.FreeRTOS.org for more information. + */ +#include +#include "FreeRTOS.h" +#include "task.h" + +/* Setup the correct byte alignment mask for the defined byte alignment. */ +#if portBYTE_ALIGNMENT == 4 + #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0003 ) +#endif + +#if portBYTE_ALIGNMENT == 2 + #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0001 ) +#endif + +#if portBYTE_ALIGNMENT == 1 + #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0000 ) +#endif + +#ifndef heapBYTE_ALIGNMENT_MASK + #error "Invalid portBYTE_ALIGNMENT definition" +#endif + +/* Allocate the memory for the heap. The struct is used to force byte +alignment without using any non-portable code. */ +extern struct xRTOS_HEAP +{ + unsigned portLONG ulDummy; + unsigned portCHAR ucHeap[ configTOTAL_HEAP_SIZE ]; +} xHeap; + +static size_t xNextFreeByte = ( size_t ) 0; +/*-----------------------------------------------------------*/ + +void *pvPortMalloc( size_t xWantedSize ) +{ +void *pvReturn = NULL; + + /* Ensure that blocks are always aligned to the required number of bytes. */ + #if portBYTE_ALIGNMENT != 1 + if( xWantedSize & heapBYTE_ALIGNMENT_MASK ) + { + /* Byte alignment required. */ + xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & heapBYTE_ALIGNMENT_MASK ) ); + } + #endif + + vTaskSuspendAll(); + { + /* Check there is enough room left for the allocation. */ + if( ( ( xNextFreeByte + xWantedSize ) < configTOTAL_HEAP_SIZE ) && + ( ( xNextFreeByte + xWantedSize ) > xNextFreeByte ) )/* Check for overflow. */ + { + /* Return the next free byte then increment the index past this + block. */ + pvReturn = &( xHeap.ucHeap[ xNextFreeByte ] ); + xNextFreeByte += xWantedSize; + } + } + xTaskResumeAll(); + + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void *pv ) +{ + /* Memory cannot be freed using this scheme. See heap_2.c and heap_3.c + for alternative implementations, and the memory management pages of + http://www.FreeRTOS.org for more information. */ + ( void ) pv; +} +/*-----------------------------------------------------------*/ + +void vPortInitialiseBlocks( void ) +{ + /* Only required when static memory is not cleared. */ + xNextFreeByte = ( size_t ) 0; +} + + diff --git a/20080212/Demo/CORTEX_LM3S811_KEIL/main.c b/20080212/Demo/CORTEX_LM3S811_KEIL/main.c new file mode 100644 index 000000000..a472c2525 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_KEIL/main.c @@ -0,0 +1,372 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +/* + * This project contains an application demonstrating the use of the + * FreeRTOS.org mini real time scheduler on the Luminary Micro LM3S811 Eval + * board. See http://www.FreeRTOS.org for more information. + * + * main() simply sets up the hardware, creates all the demo application tasks, + * then starts the scheduler. http://www.freertos.org/a00102.html provides + * more information on the standard demo tasks. + * + * In addition to a subset of the standard demo application tasks, main.c also + * defines the following tasks: + * + * + A 'Print' task. The print task is the only task permitted to access the + * LCD - thus ensuring mutual exclusion and consistent access to the resource. + * Other tasks do not access the LCD directly, but instead send the text they + * wish to display to the print task. The print task spends most of its time + * blocked - only waking when a message is queued for display. + * + * + A 'Button handler' task. The eval board contains a user push button that + * is configured to generate interrupts. The interrupt handler uses a + * semaphore to wake the button handler task - demonstrating how the priority + * mechanism can be used to defer interrupt processing to the task level. The + * button handler task sends a message both to the LCD (via the print task) and + * the UART where it can be viewed using a dumb terminal (via the UART to USB + * converter on the eval board). NOTES: The dumb terminal must be closed in + * order to reflash the microcontroller. A very basic interrupt driven UART + * driver is used that does not use the FIFO. 19200 baud is used. + * + * + A 'check' task. The check task only executes every five seconds but has a + * high priority so is guaranteed to get processor time. Its function is to + * check that all the other tasks are still operational and that no errors have + * been detected at any time. If no errors have every been detected 'PASS' is + * written to the display (via the print task) - if an error has ever been + * detected the message is changed to 'FAIL'. The position of the message is + * changed for each write. + */ + + + +/* Environment includes. */ +#include "DriverLib.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "semphr.h" + +/* Demo app includes. */ +#include "integer.h" +#include "PollQ.h" +#include "semtest.h" +#include "BlockQ.h" + +/* Delay between cycles of the 'check' task. */ +#define mainCHECK_DELAY ( ( portTickType ) 5000 / portTICK_RATE_MS ) + +/* UART configuration - note this does not use the FIFO so is not very +efficient. */ +#define mainBAUD_RATE ( 19200 ) +#define mainFIFO_SET ( 0x10 ) + +/* Demo task priorities. */ +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) + +/* Demo board specifics. */ +#define mainPUSH_BUTTON GPIO_PIN_4 + +/* Misc. */ +#define mainQUEUE_SIZE ( 3 ) +#define mainDEBOUNCE_DELAY ( ( portTickType ) 150 / portTICK_RATE_MS ) +#define mainNO_DELAY ( ( portTickType ) 0 ) +/* + * Configure the processor and peripherals for this demo. + */ +static void prvSetupHardware( void ); + +/* + * The 'check' task, as described at the top of this file. + */ +static void vCheckTask( void *pvParameters ); + +/* + * The task that is woken by the ISR that processes GPIO interrupts originating + * from the push button. + */ +static void vButtonHandlerTask( void *pvParameters ); + +/* + * The task that controls access to the LCD. + */ +static void vPrintTask( void *pvParameter ); + +/* String that is transmitted on the UART. */ +static portCHAR *cMessage = "Task woken by button interrupt! --- "; +static volatile portCHAR *pcNextChar; + +/* The semaphore used to wake the button handler task from within the GPIO +interrupt handler. */ +xSemaphoreHandle xButtonSemaphore; + +/* The queue used to send strings to the print task for display on the LCD. */ +xQueueHandle xPrintQueue; + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + /* Configure the clocks, UART and GPIO. */ + prvSetupHardware(); + + /* Create the semaphore used to wake the button handler task from the GPIO + ISR. */ + vSemaphoreCreateBinary( xButtonSemaphore ); + xSemaphoreTake( xButtonSemaphore, 0 ); + + /* Create the queue used to pass message to vPrintTask. */ + xPrintQueue = xQueueCreate( mainQUEUE_SIZE, sizeof( portCHAR * ) ); + + /* Start the standard demo tasks. */ + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + + /* Start the tasks defined within the file. */ + xTaskCreate( vCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + xTaskCreate( vButtonHandlerTask, "Status", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY + 1, NULL ); + xTaskCreate( vPrintTask, "Print", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY - 1, NULL ); + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* Will only get here if there was insufficient heap to start the + scheduler. */ + + return 0; +} +/*-----------------------------------------------------------*/ + +static void vCheckTask( void *pvParameters ) +{ +portBASE_TYPE xErrorOccurred = pdFALSE; +portTickType xLastExecutionTime; +const portCHAR *pcPassMessage = "PASS"; +const portCHAR *pcFailMessage = "FAIL"; + + /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() + works correctly. */ + xLastExecutionTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Perform this check every mainCHECK_DELAY milliseconds. */ + vTaskDelayUntil( &xLastExecutionTime, mainCHECK_DELAY ); + + /* Has an error been found in any task? */ + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + + /* Send either a pass or fail message. If an error is found it is + never cleared again. We do not write directly to the LCD, but instead + queue a message for display by the print task. */ + if( xErrorOccurred == pdTRUE ) + { + xQueueSend( xPrintQueue, &pcFailMessage, portMAX_DELAY ); + } + else + { + xQueueSend( xPrintQueue, &pcPassMessage, portMAX_DELAY ); + } + } +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Setup the PLL. */ + SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); + + /* Setup the push button. */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC); + GPIODirModeSet(GPIO_PORTC_BASE, mainPUSH_BUTTON, GPIO_DIR_MODE_IN); + GPIOIntTypeSet( GPIO_PORTC_BASE, mainPUSH_BUTTON,GPIO_FALLING_EDGE ); + GPIOPinIntEnable( GPIO_PORTC_BASE, mainPUSH_BUTTON ); + IntEnable( INT_GPIOC ); + + + + /* Enable the UART. */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + + /* Set GPIO A0 and A1 as peripheral function. They are used to output the + UART signals. */ + GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); + + /* Configure the UART for 8-N-1 operation. */ + UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); + + /* We don't want to use the fifo. This is for test purposes to generate + as many interrupts as possible. */ + HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET; + + /* Enable Tx interrupts. */ + HWREG( UART0_BASE + UART_O_IM ) |= UART_INT_TX; + IntEnable( INT_UART0 ); + + + /* Initialise the LCD> */ + OSRAMInit( false ); + OSRAMStringDraw("www.FreeRTOS.org", 0, 0); + OSRAMStringDraw("LM3S811 demo", 16, 1); +} +/*-----------------------------------------------------------*/ + +static void vButtonHandlerTask( void *pvParameters ) +{ +const portCHAR *pcInterruptMessage = "Int"; + + for( ;; ) + { + /* Wait for a GPIO interrupt to wake this task. */ + while( xSemaphoreTake( xButtonSemaphore, portMAX_DELAY ) != pdPASS ); + + /* Start the Tx of the message on the UART. */ + UARTIntDisable( UART0_BASE, UART_INT_TX ); + { + pcNextChar = cMessage; + + /* Send the first character. */ + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = *pcNextChar; + } + + pcNextChar++; + } + UARTIntEnable(UART0_BASE, UART_INT_TX); + + /* Queue a message for the print task to display on the LCD. */ + xQueueSend( xPrintQueue, &pcInterruptMessage, portMAX_DELAY ); + + /* Make sure we don't process bounces. */ + vTaskDelay( mainDEBOUNCE_DELAY ); + xSemaphoreTake( xButtonSemaphore, mainNO_DELAY ); + } +} + +/*-----------------------------------------------------------*/ + +void vUART_ISR(void) +{ +unsigned portLONG ulStatus; + + /* What caused the interrupt. */ + ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); + + /* Clear the interrupt. */ + UARTIntClear( UART0_BASE, ulStatus ); + + /* Was a Tx interrupt pending? */ + if( ulStatus & UART_INT_TX ) + { + /* Send the next character in the string. We are not using the FIFO. */ + if( *pcNextChar != NULL ) + { + if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) + { + HWREG( UART0_BASE + UART_O_DR ) = *pcNextChar; + } + pcNextChar++; + } + } +} +/*-----------------------------------------------------------*/ + +void vGPIO_ISR( void ) +{ + /* Clear the interrupt. */ + GPIOPinIntClear(GPIO_PORTC_BASE, mainPUSH_BUTTON); + + /* Wake the button handler task. */ + if( xSemaphoreGiveFromISR( xButtonSemaphore, pdFALSE ) ) + { + portEND_SWITCHING_ISR( pdTRUE ); + } +} +/*-----------------------------------------------------------*/ + +static void vPrintTask( void *pvParameters ) +{ +portCHAR *pcMessage; +unsigned portBASE_TYPE uxLine = 0, uxRow = 0; + + for( ;; ) + { + /* Wait for a message to arrive. */ + xQueueReceive( xPrintQueue, &pcMessage, portMAX_DELAY ); + + /* Write the message to the LCD. */ + uxRow++; + uxLine++; + OSRAMClear(); + OSRAMStringDraw( pcMessage, uxLine & 0x3f, uxRow & 0x01); + } +} + diff --git a/20080212/Demo/CORTEX_LM3S811_KEIL/readme.txt b/20080212/Demo/CORTEX_LM3S811_KEIL/readme.txt new file mode 100644 index 000000000..371a25b70 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_KEIL/readme.txt @@ -0,0 +1,36 @@ +/* + * This project contains an application demonstrating the use of the + * FreeRTOS.org mini real time scheduler on the Luminary Micro LM3S811 Eval + * board. See http://www.FreeRTOS.org for more information. + * + * main() simply sets up the hardware, creates all the demo application tasks, + * then starts the scheduler. http://www.freertos.org/a00102.html provides + * more information on the standard demo tasks. + * + * In addition to a subset of the standard demo application tasks, main.c also + * defines the following tasks: + * + * + A 'Print' task. The print task is the only task permitted to access the + * LCD - thus ensuring mutual exclusion and consistent access to the resource. + * Other tasks do not access the LCD directly, but instead send the text they + * wish to display to the print task. The print task spends most of its time + * blocked - only waking when a message is queued for display. + * + * + A 'Button handler' task. The eval board contains a user push button that + * is configured to generate interrupts. The interrupt handler uses a + * semaphore to wake the button handler task - demonstrating how the priority + * mechanism can be used to defer interrupt processing to the task level. The + * button handler task sends a message both to the LCD (via the print task) and + * the UART where it can be viewed using a dumb terminal (via the UART to USB + * converter on the eval board). NOTES: The dumb terminal must be closed in + * order to reflash the microcontroller. A very basic interrupt driven UART + * driver is used that does not use the FIFO. 19200 baud is used. + * + * + A 'check' task. The check task only executes every five seconds but has a + * high priority so is guaranteed to get processor time. Its function is to + * check that all the other tasks are still operational and that no errors have + * been detected at any time. If no errors have every been detected 'PASS' is + * written to the display (via the print task) - if an error has ever been + * detected the message is changed to 'FAIL'. The position of the message is + * changed for each write. + */ \ No newline at end of file diff --git a/20080212/Demo/CORTEX_LM3S811_KEIL/startup_rvmdk.S b/20080212/Demo/CORTEX_LM3S811_KEIL/startup_rvmdk.S new file mode 100644 index 000000000..e22c13e83 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3S811_KEIL/startup_rvmdk.S @@ -0,0 +1,238 @@ +; <<< Use Configuration Wizard in Context Menu >>> +;****************************************************************************** +; +; startup_rvmdk.S - Startup code for Stellaris. +; +; Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. +; +; Software License Agreement +; +; Luminary Micro, Inc. (LMI) is supplying this software for use solely and +; exclusively on LMI's Stellaris Family of microcontroller products. +; +; The software is owned by LMI and/or its suppliers, and is protected under +; applicable copyright laws. All rights are reserved. Any use in violation of +; the foregoing restrictions may subject the user to criminal sanctions under +; applicable laws, as well as to civil liability for the breach of the terms +; and conditions of this license. +; +; THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; +; This is part of revision 816 of the Stellaris Driver Library. +; +;****************************************************************************** + +;****************************************************************************** +; +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; +; +;****************************************************************************** +Stack EQU 0x00000100 + +;****************************************************************************** +; +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; +; +;****************************************************************************** +Heap EQU 0x00000000 + +;****************************************************************************** +; +; Allocate space for the stack. +; +;****************************************************************************** + AREA STACK, NOINIT, READWRITE, ALIGN=3 +StackMem + SPACE Stack + +;****************************************************************************** +; +; Allocate space for the heap. +; +;****************************************************************************** + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +HeapMem + SPACE Heap + +;****************************************************************************** +; +; Indicate that the code in this file preserves 8-byte alignment of the stack. +; +;****************************************************************************** + PRESERVE8 + +;****************************************************************************** +; +; Place code into the reset code section. +; +;****************************************************************************** + AREA RESET, CODE, READONLY + THUMB + +;****************************************************************************** +; +; The vector table. +; +;****************************************************************************** +Vectors + DCD StackMem + Stack ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NmiSR ; NMI Handler + DCD FaultISR ; Hard Fault Handler + DCD IntDefaultHandler ; MPU Fault Handler + DCD IntDefaultHandler ; Bus Fault Handler + DCD IntDefaultHandler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD IntDefaultHandler ; SVCall Handler + DCD IntDefaultHandler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD xPortPendSVHandler ; PendSV Handler + DCD xPortSysTickHandler ; SysTick Handler + DCD IntDefaultHandler ; GPIO Port A + DCD IntDefaultHandler ; GPIO Port B + DCD vGPIO_ISR ; GPIO Port C + DCD IntDefaultHandler ; GPIO Port D + DCD IntDefaultHandler ; GPIO Port E + DCD vUART_ISR ; UART0 + DCD IntDefaultHandler ; UART1 + DCD IntDefaultHandler ; SSI + DCD IntDefaultHandler ; I2C + DCD IntDefaultHandler ; PWM Fault + DCD IntDefaultHandler ; PWM Generator 0 + DCD IntDefaultHandler ; PWM Generator 1 + DCD IntDefaultHandler ; PWM Generator 2 + DCD IntDefaultHandler ; Quadrature Encoder + DCD IntDefaultHandler ; ADC Sequence 0 + DCD IntDefaultHandler ; ADC Sequence 1 + DCD IntDefaultHandler ; ADC Sequence 2 + DCD IntDefaultHandler ; ADC Sequence 3 + DCD IntDefaultHandler ; Watchdog + DCD IntDefaultHandler ; Timer 0A + DCD IntDefaultHandler ; Timer 0B + DCD IntDefaultHandler ; Timer 1A + DCD IntDefaultHandler ; Timer 1B + DCD IntDefaultHandler ; Timer 2A + DCD IntDefaultHandler ; Timer 2B + DCD IntDefaultHandler ; Comp 0 + DCD IntDefaultHandler ; Comp 1 + DCD IntDefaultHandler ; Comp 2 + DCD IntDefaultHandler ; System Control + DCD IntDefaultHandler ; Flash Control + +;****************************************************************************** +; +; This is the code that gets called when the processor first starts execution +; following a reset event. +; +;****************************************************************************** + EXPORT Reset_Handler +Reset_Handler + ; + ; Call __main() in the C library, which will call the application + ; supplied main(). + ; + IMPORT __main + IMPORT vGPIO_ISR + IMPORT vUART_ISR + IMPORT xPortPendSVHandler + IMPORT xPortSysTickHandler + + LDR R0, =__main + BX R0 + +;****************************************************************************** +; +; This is the code that gets called when the processor receives a NMI. This +; simply enters an infinite loop, preserving the system state for examination +; by a debugger. +; +;****************************************************************************** +NmiSR + B NmiSR + +;****************************************************************************** +; +; This is the code that gets called when the processor receives a fault +; interrupt. This simply enters an infinite loop, preserving the system state +; for examination by a debugger. +; +;****************************************************************************** +FaultISR + B FaultISR + +;****************************************************************************** +; +; This is the code that gets called when the processor receives an unexpected +; interrupt. This simply enters an infinite loop, preserving the system state +; for examination by a debugger. +; +;****************************************************************************** +IntDefaultHandler + B IntDefaultHandler + +;****************************************************************************** +; +; Make sure the end of this section is aligned. +; +;****************************************************************************** + ALIGN + +;****************************************************************************** +; +; Some code in the normal code section for initializing the heap and stack. +; +;****************************************************************************** + AREA |.text|, CODE, READONLY + +;****************************************************************************** +; +; The function expected of the C library startup code for defining the stack +; and heap memory locations. +; +;****************************************************************************** + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + LDR R0, =HeapMem + LDR R1, =(StackMem + Stack) + LDR R2, =(HeapMem + Heap) + LDR R3, =StackMem + BX LR + +;****************************************************************************** +; +; Make sure the end of this section is aligned. +; +;****************************************************************************** + ALIGN + +; Note: +; Using READWRITE places Section .RTOSHeap in Region ER_RW. +; Using NOINIT places Section .RTOSHeap in Region ER_ZI,which means +; "ZEROINITIALIZE" (sic), and which is the last region in memory. Then +; we need to make this section the last section, which is somewhat tricky, +; because we cannot use the sectionname, but need to use a defined symbol: +; Linker option: "--last xHeap" + + EXPORT xHeap + + AREA RTOSHeap, DATA, NOINIT +xHeap + +;****************************************************************************** +; +; Tell the assembler that we're done. +; +;****************************************************************************** + END diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.cdt.core/.log b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.cdt.core/.log new file mode 100644 index 000000000..ad90e761f --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.cdt.core/.log @@ -0,0 +1,19 @@ +*** SESSION Aug 19, 2007 15:19:16.906 ------------------------------------------ +*** SESSION Aug 19, 2007 20:47:55.734 ------------------------------------------ +*** SESSION Aug 19, 2007 20:58:19.953 ------------------------------------------ +*** SESSION Aug 20, 2007 10:30:54.968 ------------------------------------------ +*** SESSION Aug 20, 2007 15:43:10.859 ------------------------------------------ +*** SESSION Aug 21, 2007 13:05:50.828 ------------------------------------------ +*** SESSION Aug 21, 2007 19:01:46.812 ------------------------------------------ +*** SESSION Aug 22, 2007 14:47:56.156 ------------------------------------------ +*** SESSION Aug 23, 2007 11:52:49.406 ------------------------------------------ +*** SESSION Aug 23, 2007 19:24:16.984 ------------------------------------------ +*** SESSION Aug 23, 2007 22:26:06.78 ------------------------------------------- +*** SESSION Aug 24, 2007 12:43:08.578 ------------------------------------------ +*** SESSION Aug 24, 2007 17:08:36.187 ------------------------------------------ +*** SESSION Aug 26, 2007 11:13:57.906 ------------------------------------------ +*** SESSION Aug 26, 2007 14:24:42.656 ------------------------------------------ +*** SESSION Aug 26, 2007 14:34:02.93 ------------------------------------------- +*** SESSION Aug 26, 2007 17:35:44.937 ------------------------------------------ +*** SESSION Aug 27, 2007 10:56:42.953 ------------------------------------------ +*** SESSION Aug 27, 2007 13:13:37.593 ------------------------------------------ diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.cdt.core/shareddefaults.xml b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.cdt.core/shareddefaults.xml new file mode 100644 index 000000000..c4b91cfab --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.cdt.core/shareddefaults.xml @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.cdt.make.core/.log b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.cdt.make.core/.log new file mode 100644 index 000000000..e69de29bb diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.cdt.make.core/RTOSDemo.sc b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.cdt.make.core/RTOSDemo.sc new file mode 100644 index 000000000..44e0a6764 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.cdt.make.core/RTOSDemo.sc @@ -0,0 +1,117 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.cdt.make.core/specs.c b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.cdt.make.core/specs.c new file mode 100644 index 000000000..8b1378917 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.cdt.make.core/specs.c @@ -0,0 +1 @@ + diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.cdt.make.core/specs.cpp b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.cdt.make.core/specs.cpp new file mode 100644 index 000000000..8b1378917 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.cdt.make.core/specs.cpp @@ -0,0 +1 @@ + diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.cdt.make.ui/dialog_settings.xml b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.cdt.make.ui/dialog_settings.xml new file mode 100644 index 000000000..9e62c4bb5 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.cdt.make.ui/dialog_settings.xml @@ -0,0 +1,5 @@ + +
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b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-RTOSDemo.prefs new file mode 100644 index 000000000..bb305ff00 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-RTOSDemo.prefs @@ -0,0 +1,3 @@ +#Sun Aug 19 15:20:24 BST 2007 +eclipse.preferences.version=1 +indexer/preferenceScope=0 diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.core.prefs b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.core.prefs new file mode 100644 index 000000000..1c0fdf149 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.core.prefs @@ -0,0 +1,3 @@ +#Sun Aug 19 15:19:23 BST 2007 +org.eclipse.cdt.debug.core.cDebug.common_source_containers=\r\n\r\n\r\n\r\n +eclipse.preferences.version=1 diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.ui.prefs b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.ui.prefs new file mode 100644 index 000000000..962a2b7ac --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.ui.prefs @@ -0,0 +1,5 @@ +#Sun Aug 19 23:06:50 BST 2007 +pref_state_memento.org.eclipse.cdt.debug.ui.ModulesView=\r\n +eclipse.preferences.version=1 +org.eclipse.debug.ui.DebugView.org.eclipse.cdt.debug.ui.cDebug.show_full_paths=true +org.eclipse.debug.ui.BreakpointView.org.eclipse.cdt.debug.ui.cDebug.show_full_paths=true diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.managedbuilder.core.prefs new file mode 100644 index 000000000..614a480f6 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.managedbuilder.core.prefs @@ -0,0 +1,3 @@ +#Sun Aug 26 14:26:57 BST 2007 +eclipse.preferences.version=1 +properties/RTOSDemo.null.976634949/0.1109417601=\#\r\n\#Sun Aug 26 14\:26\:57 BST 2007\r\n0.1109417601\=\\\#\\r\\n\\\#Sun Aug 26 14\\\:26\\\:57 BST 2007\\r\\nrcState\\\=0\\r\\nrebuildState\\\=false\\r\\n\r\norg.eclipse.cdt.build.core.settings.holder.1502006385\=\\\#\\r\\n\\\#Sun Aug 26 14\\\:26\\\:57 BST 2007\\r\\nrebuildState\\\=false\\r\\n\r\norg.eclipse.cdt.build.core.settings.holder.1021181093\=\\\#\\r\\n\\\#Sun Aug 26 14\\\:26\\\:57 BST 2007\\r\\nrebuildState\\\=false\\r\\n\r\norg.eclipse.cdt.build.core.settings.holder.164584712\=\\\#\\r\\n\\\#Sun Aug 26 14\\\:26\\\:57 BST 2007\\r\\nrebuildState\\\=false\\r\\n\r\norg.eclipse.cdt.build.core.settings.holder.libs.260784574\=\\\#\\r\\n\\\#Sun Aug 26 14\\\:26\\\:57 BST 2007\\r\\nrebuildState\\\=false\\r\\n\r\norg.eclipse.cdt.build.core.prefbase.toolchain.1816209921\=\\\#\\r\\n\\\#Sun Aug 26 14\\\:26\\\:57 BST 2007\\r\\nrebuildState\\\=false\\r\\n\r\n diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prefs b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prefs new file mode 100644 index 000000000..8a970dac4 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prefs @@ -0,0 +1,12 @@ +#Thu Aug 23 20:22:58 BST 2007 +useQuickDiffPrefPage=true +closeBrackets=false +ensureNewlineAtEOF=true +useAnnotationsPrefPage=true +closeAngularBrackets=false +eclipse.preferences.version=1 +org.eclipse.cdt.ui.text.templates.custom= +hoverModifierMasks=org.eclipse.cdt.ui.BestMatchHover;0;org.eclipse.cdt.ui.CSourceHover;131072;org.eclipse.cdt.debug.internal.ui.editors.DebugTextHover;0;org.eclipse.cdt.ui.CDocHover;0;org.eclipse.cdt.ui.AnnotationHover;0; +hoverModifiers=org.eclipse.cdt.ui.BestMatchHover;0;org.eclipse.cdt.ui.CSourceHover;Shift;org.eclipse.cdt.debug.internal.ui.editors.DebugTextHover;\!0;org.eclipse.cdt.ui.CDocHover;\!0;org.eclipse.cdt.ui.AnnotationHover;\!0; +closeBraces=false +closeStrings=false diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.core.resources.prefs b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 000000000..289e27f45 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,5 @@ +#Mon Aug 27 13:15:37 BST 2007 +version=1 +eclipse.preferences.version=1 +pathvariable.FreeRTOS_ROOT=C\:/Dev/FreeRTOS +description.autobuilding=false diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs new file mode 100644 index 000000000..42e9df661 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs @@ -0,0 +1,7 @@ +#Thu Aug 23 22:01:25 BST 2007 +pref_state_memento.org.eclipse.debug.ui.VariableView=\r\n +eclipse.preferences.version=1 +pref_state_memento.org.eclipse.debug.ui.RegisterView=\r\n +org.eclipse.debug.ui.BreakpointView+org.eclipse.debug.ui.ShowSupportedBreakpointsAction=true +preferredDetailPanes=DefaultDetailPane\:DefaultDetailPane| +org.eclipse.debug.ui.PREF_LAUNCH_PERSPECTIVES=\r\n\r\n diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.help.ui.prefs b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.help.ui.prefs new file mode 100644 index 000000000..8d1b31164 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.help.ui.prefs @@ -0,0 +1,7 @@ +#Sun Aug 26 17:32:13 BST 2007 +browser.x=177 +browser.w=1024 +eclipse.preferences.version=1 +browser.h=768 +browser.maximized=false +browser.y=128 diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.search.prefs b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.search.prefs new file mode 100644 index 000000000..2426c2b79 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.search.prefs @@ -0,0 +1,3 @@ +#Sun Aug 19 19:39:29 BST 2007 +org.eclipse.search.defaultPerspective=org.eclipse.search.defaultPerspective.none +eclipse.preferences.version=1 diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.editors.prefs b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.editors.prefs new file mode 100644 index 000000000..1affd268e --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.editors.prefs @@ -0,0 +1,3 @@ +#Sun Aug 19 20:45:57 BST 2007 +eclipse.preferences.version=1 +overviewRuler_migration=migrated_3.1 diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.ide.prefs b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.ide.prefs new file mode 100644 index 000000000..18dcfbff6 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.ide.prefs @@ -0,0 +1,4 @@ +#Sun Aug 19 20:45:58 BST 2007 +eclipse.preferences.version=1 +tipsAndTricks=true +platformState=1187207632220 diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.prefs b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.prefs new file mode 100644 index 000000000..3e5b2b17d --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.prefs @@ -0,0 +1,3 @@ +#Sun Aug 19 20:45:58 BST 2007 +eclipse.preferences.version=1 +showIntro=false diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.workbench.prefs b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.workbench.prefs new file mode 100644 index 000000000..06cd1e9cd --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.workbench.prefs @@ -0,0 +1,3 @@ +#Mon Aug 20 21:59:49 BST 2007 +eclipse.preferences.version=1 +org.eclipse.ui.commands=\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.debug.core/.launches/OpenOCD Programmer.launch b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.debug.core/.launches/OpenOCD Programmer.launch new file mode 100644 index 000000000..ccfe3f5c6 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.debug.core/.launches/OpenOCD Programmer.launch @@ -0,0 +1,7 @@ + + + + + + + diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.debug.core/.launches/OpenOCD Server.launch b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.debug.core/.launches/OpenOCD Server.launch new file mode 100644 index 000000000..cdc0f1770 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.debug.core/.launches/OpenOCD Server.launch @@ -0,0 +1,7 @@ + + + + + + + diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.debug.core/.launches/RTOSDemo.launch b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.debug.core/.launches/RTOSDemo.launch new file mode 100644 index 000000000..1768f4611 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.debug.core/.launches/RTOSDemo.launch @@ -0,0 +1,26 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.debug.ui/dialog_settings.xml b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.debug.ui/dialog_settings.xml new file mode 100644 index 000000000..c2bd2c7c8 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.debug.ui/dialog_settings.xml @@ -0,0 +1,20 @@ + +
+
+ + + + + + + + +
+
+ + + + + +
+
diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.debug.ui/launchConfigurationHistory.xml b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.debug.ui/launchConfigurationHistory.xml new file mode 100644 index 000000000..598b376c8 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.debug.ui/launchConfigurationHistory.xml @@ -0,0 +1,24 @@ + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.help.ui/dialog_settings.xml b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.help.ui/dialog_settings.xml new file mode 100644 index 000000000..1ef2b05b5 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.help.ui/dialog_settings.xml @@ -0,0 +1,3 @@ + +
+
diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.help.ui/scope_sets/Default.pref b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.help.ui/scope_sets/Default.pref new file mode 100644 index 000000000..fc158177d --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.help.ui/scope_sets/Default.pref @@ -0,0 +1,2 @@ +#Sun Aug 26 17:54:18 BST 2007 +__DEFAULT__=true diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.help.ui/scope_sets/relative_path.hist b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.help.ui/scope_sets/relative_path.hist new file mode 100644 index 000000000..713e72168 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.help.ui/scope_sets/relative_path.hist @@ -0,0 +1,4 @@ +#Sun Aug 26 17:36:29 BST 2007 +__DEFAULT__=false +org.eclipse.help.ui.localSearch.master=true +expression=relative path diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.help.ui/scope_sets/working_set.hist b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.help.ui/scope_sets/working_set.hist new file mode 100644 index 000000000..197837b95 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.help.ui/scope_sets/working_set.hist @@ -0,0 +1,4 @@ +#Sun Aug 26 17:29:25 BST 2007 +__DEFAULT__=false +org.eclipse.help.ui.localSearch.master=true +expression=working set diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.help.ui/scope_sets/working_sets.hist b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.help.ui/scope_sets/working_sets.hist new file mode 100644 index 000000000..a88e15eb8 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.help.ui/scope_sets/working_sets.hist @@ -0,0 +1,4 @@ +#Sun Aug 26 17:54:21 BST 2007 +__DEFAULT__=false +org.eclipse.help.ui.localSearch.master=true +expression=working sets diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.ltk.ui.refactoring/dialog_settings.xml b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.ltk.ui.refactoring/dialog_settings.xml new file mode 100644 index 000000000..ac671478c --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.ltk.ui.refactoring/dialog_settings.xml @@ -0,0 +1,6 @@ + +
+
+ +
+
diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.search/dialog_settings.xml b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.search/dialog_settings.xml new file mode 100644 index 000000000..839aca5ed --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.search/dialog_settings.xml @@ -0,0 +1,46 @@ + +
+
+ +
+
+ + + + + +
+
+ + + + + + + + +
+
+ +
+
+ + + + +
+ + + + + + + + + +
+
+
+ +
+
diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.ui.cheatsheets/dialog_settings.xml b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.ui.cheatsheets/dialog_settings.xml new file mode 100644 index 000000000..1df8b48c3 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.ui.cheatsheets/dialog_settings.xml @@ -0,0 +1,10 @@ + +
+
+ + + + + +
+
diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.ui.ide/dialog_settings.xml b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.ui.ide/dialog_settings.xml new file mode 100644 index 000000000..bbc6392ba --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.ui.ide/dialog_settings.xml @@ -0,0 +1,19 @@ + +
+
+ + +
+
+
+
+
+
+ + + + + + +
+
diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.ui.intro/dialog_settings.xml b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.ui.intro/dialog_settings.xml new file mode 100644 index 000000000..d3014f5c1 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.ui.intro/dialog_settings.xml @@ -0,0 +1,4 @@ + +
+ +
diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.ui.workbench.texteditor/dialog_settings.xml b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.ui.workbench.texteditor/dialog_settings.xml new file mode 100644 index 000000000..bffa7155b --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.ui.workbench.texteditor/dialog_settings.xml @@ -0,0 +1,31 @@ + +
+
+ + + + + +
+
+ + + + + + + + + + + + + + + + + + + +
+
diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.ui.workbench/dialog_settings.xml b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.ui.workbench/dialog_settings.xml new file mode 100644 index 000000000..77beade3e --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.ui.workbench/dialog_settings.xml @@ -0,0 +1,19 @@ + +
+
+ + +
+
+ + + + +
+
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+
diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.ui.workbench/workbench.xml b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.ui.workbench/workbench.xml new file mode 100644 index 000000000..b1b44e27a --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.ui.workbench/workbench.xml @@ -0,0 +1,532 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.ui.workbench/workingsets.xml b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.ui.workbench/workingsets.xml new file mode 100644 index 000000000..d14870dc1 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.ui.workbench/workingsets.xml @@ -0,0 +1,68 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.ui/dialog_settings.xml b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.ui/dialog_settings.xml new file mode 100644 index 000000000..64561b65c --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.ui/dialog_settings.xml @@ -0,0 +1,10 @@ + +
+
+ + + + + +
+
diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.update.ui/dialog_settings.xml b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.update.ui/dialog_settings.xml new file mode 100644 index 000000000..86928e08c --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/.plugins/org.eclipse.update.ui/dialog_settings.xml @@ -0,0 +1,5 @@ + +
+
+
+
diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/version.ini b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/version.ini new file mode 100644 index 000000000..c51ff745b --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/.metadata/version.ini @@ -0,0 +1 @@ +org.eclipse.core.runtime=1 \ No newline at end of file diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/.cproject b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/.cproject new file mode 100644 index 000000000..f0306170d --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/.cproject @@ -0,0 +1,228 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/.project b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/.project new file mode 100644 index 000000000..e635b964b --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/.project @@ -0,0 +1,97 @@ + + + RTOSDemo + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.buildCommand + cs-make + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.buildLocation + ${workspace_loc:/RTOSDemo} + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + false + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + ?children? + ?name?=outputEntries\|?children?=?name?=entry\\\\\\\\\\\\\\\|\\\\\\\|\|| + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.core.cnature + + + + Common Demo Files + 2 + FreeRTOS_ROOT/Demo/Common + + + FreeRTOS.org Source + 2 + FreeRTOS_ROOT/Source + + + diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/.settings/org.eclipse.ltk.core.refactoring.prefs b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/.settings/org.eclipse.ltk.core.refactoring.prefs new file mode 100644 index 000000000..a9f7e81cf --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/.settings/org.eclipse.ltk.core.refactoring.prefs @@ -0,0 +1,3 @@ +#Sun Aug 19 20:36:58 BST 2007 +eclipse.preferences.version=1 +org.eclipse.ltk.core.refactoring.enable.project.refactoring.history=false diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/FreeRTOSConfig.h b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/FreeRTOSConfig.h new file mode 100644 index 000000000..51a03b555 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/FreeRTOSConfig.h @@ -0,0 +1,89 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 1 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 50000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 70 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 24000 ) ) +#define configMAX_TASK_NAME_LEN ( 12 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_CO_ROUTINES 0 +#define configUSE_MUTEXES 1 + +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + + +#define configKERNEL_INTERRUPT_PRIORITY 255 + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/Makefile b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/Makefile new file mode 100644 index 000000000..64f622a5c --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/Makefile @@ -0,0 +1,106 @@ +# FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. +# +# This file is part of the FreeRTOS.org distribution. +# +# FreeRTOS.org is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# FreeRTOS.org is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with FreeRTOS.org; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +# +# A special exception to the GPL can be applied should you wish to distribute +# a combined work that includes FreeRTOS.org, without being obliged to provide +# the source code for any proprietary components. See the licensing section +# of http://www.FreeRTOS.org for full details of how and when the exception +# can be applied. +# +# *************************************************************************** +# See http://www.FreeRTOS.org for documentation, latest information, license +# and contact details. Please ensure to read the configuration and relevant +# port sections of the online documentation. +# *************************************************************************** + + +RTOS_SOURCE_DIR=../../../Source +DEMO_COMMON_DIR=../../Common/Minimal +DEMO_INCLUDE_DIR=../../Common/include +UIP_COMMON_DIR=../../Common/ethernet/uIP/uip-1.0/uip +LUMINARY_DRIVER_DIR=../../Common/drivers/LuminaryMicro + +CC=arm-none-eabi-gcc +OBJCOPY=arm-none-eabi-objcopy +LDSCRIPT=standalone.ld + +LINKER_FLAGS=-nostartfiles -Xlinker -oRTOSDemo.axf -Xlinker -M -Xlinker -Map=rtosdemo.map + +DEBUG=-g +OPTIM=-O0 + + +CFLAGS=$(DEBUG) -I . -I $(RTOS_SOURCE_DIR)/include -I $(RTOS_SOURCE_DIR)/portable/GCC/ARM_CM3 \ + -I $(DEMO_INCLUDE_DIR) -D GCC_ARMCM3_LM3S102 -D inline= -mthumb -mcpu=cortex-m3 $(OPTIM) -T$(LDSCRIPT) \ + -D PACK_STRUCT_END=__attribute\(\(packed\)\) -D ALIGN_STRUCT_END=__attribute\(\(aligned\(4\)\)\) -D sprintf=usprintf -D snprintf=usnprintf -D printf=uipprintf \ + -I $(UIP_COMMON_DIR) -I ./webserver -ffunction-sections -fdata-sections -Wl,--no-gc-sections -I $(LUMINARY_DRIVER_DIR) + +SOURCE= main.c \ + timertest.c \ + ./ParTest/ParTest.c \ + rit128x96x4.c \ + osram128x64x4.c \ + $(LUMINARY_DRIVER_DIR)/ustdlib.c \ + $(DEMO_COMMON_DIR)/BlockQ.c \ + $(DEMO_COMMON_DIR)/blocktim.c \ + $(DEMO_COMMON_DIR)/death.c \ + $(DEMO_COMMON_DIR)/integer.c \ + $(DEMO_COMMON_DIR)/PollQ.c \ + $(DEMO_COMMON_DIR)/semtest.c \ + $(DEMO_COMMON_DIR)/GenQTest.c \ + $(DEMO_COMMON_DIR)/QPeek.c \ + ./webserver/uIP_Task.c \ + ./webserver/emac.c \ + ./webserver/httpd.c \ + ./webserver/httpd-cgi.c \ + ./webserver/httpd-fs.c \ + ./webserver/http-strings.c \ + $(UIP_COMMON_DIR)/uip_arp.c \ + $(UIP_COMMON_DIR)/psock.c \ + $(UIP_COMMON_DIR)/timer.c \ + $(UIP_COMMON_DIR)/uip.c \ + $(RTOS_SOURCE_DIR)/list.c \ + $(RTOS_SOURCE_DIR)/queue.c \ + $(RTOS_SOURCE_DIR)/tasks.c \ + $(RTOS_SOURCE_DIR)/Portable/GCC/ARM_CM3/port.c \ + $(RTOS_SOURCE_DIR)/Portable/MemMang/heap_2.c + +LIBS= $(LUMINARY_DRIVER_DIR)/arm-none-eabi-gcc/libdriver.a + +OBJS = $(SOURCE:.c=.o) + +all: RTOSDemo.bin + +RTOSDemo.bin : RTOSDemo.axf + $(OBJCOPY) RTOSDemo.axf -O binary RTOSDemo.bin + +RTOSDemo.axf : $(OBJS) startup.o Makefile + $(CC) $(CFLAGS) $(OBJS) startup.o $(LIBS) $(LINKER_FLAGS) + +$(OBJS) : %.o : %.c Makefile FreeRTOSConfig.h + $(CC) -c $(CFLAGS) $< -o $@ + +startup.o : startup.c Makefile + $(CC) -c $(CFLAGS) -O1 startup.c -o startup.o + +clean : + cs-rm $(OBJS) + + + + diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/ParTest/ParTest.c b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/ParTest/ParTest.c new file mode 100644 index 000000000..d03d019ce --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/ParTest/ParTest.c @@ -0,0 +1,90 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +/* +*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo includes. */ +#include "partest.h" + +/* Library includes. */ +#include "hw_types.h" +#include "gpio.h" +#include "hw_memmap.h" + + +/*-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ + GPIODirModeSet( GPIO_PORTF_BASE, GPIO_PIN_0, GPIO_DIR_MODE_OUT ); + GPIOPadConfigSet( GPIO_PORTF_BASE, GPIO_PIN_0, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD ); + GPIOPinWrite( GPIO_PORTF_BASE, GPIO_PIN_0, 0 ); +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ + /* There is only one LED. */ + ( void ) uxLED; + + GPIOPinWrite( GPIO_PORTF_BASE, GPIO_PIN_0, xValue ); +} +/*-----------------------------------------------------------*/ + +unsigned portBASE_TYPE uxParTestGetLED( unsigned portBASE_TYPE uxLED ) +{ + /* There is only one LED. */ + ( void ) uxLED; + + return GPIOPinRead( GPIO_PORTF_BASE, GPIO_PIN_0 ); +} + + diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/bitmap.h b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/bitmap.h new file mode 100644 index 000000000..02ce0b365 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/bitmap.h @@ -0,0 +1,171 @@ +#ifndef BITMAP_H +#define BITMAP_H + +const unsigned char pucImage[] = +{ +0x00, 0x0a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, +0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, +0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, +0xaa, 0xaa, 0xaa, 0x00, 0x0a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, +0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, +0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +0xff, 0xff, 0xfa, 0xaa, 0xaa, 0xaa, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, +0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, +0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, +0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x0a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, +0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, +0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, +0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0, 0x00, 0xaa, 0xaa, 0xaa, +0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, +0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, +0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, +0x00 }; + +#define bmpBITMAP_HEIGHT 50 +#define bmpBITMAP_WIDTH 128 + +#endif diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/lcd_message.h b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/lcd_message.h new file mode 100644 index 000000000..ced7a1dbc --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/lcd_message.h @@ -0,0 +1,9 @@ +#ifndef LCD_MESSAGE_H +#define LCD_MESSAGE_H + +typedef struct +{ + char *pcMessage; +} xOLEDMessage; + +#endif /* LCD_MESSAGE_H */ diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/main.c b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/main.c new file mode 100644 index 000000000..d19e4470a --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/main.c @@ -0,0 +1,442 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +/* + * Creates all the demo application tasks, then starts the scheduler. The WEB + * documentation provides more details of the standard demo application tasks. + * In addition to the standard demo tasks, the following tasks and tests are + * defined and/or created within this file: + * + * "Fast Interrupt Test" - A high frequency periodic interrupt is generated + * using a free running timer to demonstrate the use of the + * configKERNEL_INTERRUPT_PRIORITY configuration constant. The interrupt + * service routine measures the number of processor clocks that occur between + * each interrupt - and in so doing measures the jitter in the interrupt timing. + * The maximum measured jitter time is latched in the ulMaxJitter variable, and + * displayed on the OLED display by the 'OLED' task as described below. The + * fast interrupt is configured and handled in the timertest.c source file. + * + * "OLED" task - the OLED task is a 'gatekeeper' task. It is the only task that + * is permitted to access the display directly. Other tasks wishing to write a + * message to the OLED send the message on a queue to the OLED task instead of + * accessing the OLED themselves. The OLED task just blocks on the queue waiting + * for messages - waking and displaying the messages as they arrive. + * + * "Check" hook - This only executes every five seconds from the tick hook. + * Its main function is to check that all the standard demo tasks are still + * operational. Should any unexpected behaviour within a demo task be discovered + * the tick hook will write an error to the OLED (via the OLED task). If all the + * demo tasks are executing with their expected behaviour then the check task + * writes PASS to the OLED (again via the OLED task), as described above. + * + * "uIP" task - This is the task that handles the uIP stack. All TCP/IP + * processing is performed in this task. + */ + + + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "Task.h" +#include "queue.h" +#include "semphr.h" + +/* Demo app includes. */ +#include "BlockQ.h" +#include "death.h" +#include "integer.h" +#include "blocktim.h" +#include "flash.h" +#include "partest.h" +#include "semtest.h" +#include "pollq.h" +#include "lcd_message.h" +#include "bitmap.h" +#include "GenQTest.h" +#include "QPeek.h" + +/* Hardware library includes. */ +#include "hw_memmap.h" +#include "hw_types.h" +#include "hw_sysctl.h" +#include "sysctl.h" +#include "gpio.h" +#include "rit128x96x4.h" +#include "osram128x64x4.h" + +/*-----------------------------------------------------------*/ + +/* The time between cycles of the 'check' functionality (defined within the +tick hook. */ +#define mainCHECK_DELAY ( ( portTickType ) 5000 / portTICK_RATE_MS ) + +/* Size of the stack allocated to the uIP task. */ +#define mainBASIC_WEB_STACK_SIZE ( configMINIMAL_STACK_SIZE * 3 ) + +/* The OLED task uses the sprintf function so requires a little more stack too. */ +#define mainOLED_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE + 50 ) + +/* Task priorities. */ +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainINTEGER_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY ) + +/* The maximum number of message that can be waiting for display at any one +time. */ +#define mainOLED_QUEUE_SIZE ( 3 ) + +/* Dimensions the buffer into which the jitter time is written. */ +#define mainMAX_MSG_LEN 25 + +/* The period of the system clock in nano seconds. This is used to calculate +the jitter time in nano seconds. */ +#define mainNS_PER_CLOCK ( ( unsigned portLONG ) ( ( 1.0 / ( double ) configCPU_CLOCK_HZ ) * 1000000000.0 ) ) + +/* Constants used when writing strings to the display. */ +#define mainCHARACTER_HEIGHT ( 9 ) +#define mainMAX_ROWS_96 ( mainCHARACTER_HEIGHT * 10 ) +#define mainMAX_ROWS_64 ( mainCHARACTER_HEIGHT * 7 ) +#define mainFULL_SCALE ( 15 ) +#define ulSSI_FREQUENCY ( 3500000UL ) + +/*-----------------------------------------------------------*/ + +/* + * The task that handles the uIP stack. All TCP/IP processing is performed in + * this task. + */ +extern void vuIP_Task( void *pvParameters ); + +/* + * The display is written two by more than one task so is controlled by a + * 'gatekeeper' task. This is the only task that is actually permitted to + * access the display directly. Other tasks wanting to display a message send + * the message to the gatekeeper. + */ +static void vOLEDTask( void *pvParameters ); + +/* + * Configure the hardware for the demo. + */ +static void prvSetupHardware( void ); + +/* + * Configures the high frequency timers - those used to measure the timing + * jitter while the real time kernel is executing. + */ +extern void vSetupTimer( void ); + +/* + * The idle hook is used to run a test of the scheduler context switch + * mechanism. + */ +void vApplicationIdleHook( void ) __attribute__((naked)); +/*-----------------------------------------------------------*/ + +/* The queue used to send messages to the OLED task. */ +xQueueHandle xOLEDQueue; + +/* The welcome text. */ +const portCHAR * const pcWelcomeMessage = " www.FreeRTOS.org"; + +/* Variables used to detect the test in the idle hook failing. */ +unsigned portLONG ulIdleError = pdFALSE; + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + prvSetupHardware(); + + /* Create the queue used by the OLED task. Messages for display on the OLED + are received via this queue. */ + xOLEDQueue = xQueueCreate( mainOLED_QUEUE_SIZE, sizeof( xOLEDMessage ) ); + + /* Create the uIP task if running on a processor that includes a MAC and + PHY. */ + if( SysCtlPeripheralPresent( SYSCTL_PERIPH_ETH ) ) + { + xTaskCreate( vuIP_Task, ( signed portCHAR * ) "uIP", mainBASIC_WEB_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY - 1, NULL ); + } + + /* Start the standard demo tasks. */ + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vCreateBlockTimeTasks(); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartIntegerMathTasks( mainINTEGER_TASK_PRIORITY ); + vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY ); + vStartQueuePeekTasks(); + + /* Start the tasks defined within this file/specific to this demo. */ + xTaskCreate( vOLEDTask, ( signed portCHAR * ) "OLED", mainOLED_TASK_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + + /* The suicide tasks must be created last as they need to know how many + tasks were running prior to their creation in order to ascertain whether + or not the correct/expected number of tasks are running at any given time. */ + vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); + + /* Configure the high frequency interrupt used to measure the interrupt + jitter time. */ + vSetupTimer(); + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* Will only get here if there was insufficient memory to create the idle + task. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void prvSetupHardware( void ) +{ + /* If running on Rev A2 silicon, turn the LDO voltage up to 2.75V. This is + a workaround to allow the PLL to operate reliably. */ + if( DEVICE_IS_REVA2 ) + { + SysCtlLDOSet( SYSCTL_LDO_2_75V ); + } + + /* Set the clocking to run from the PLL at 50 MHz */ + SysCtlClockSet( SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_8MHZ ); + + /* Enable Port F for Ethernet LEDs + LED0 Bit 3 Output + LED1 Bit 2 Output */ + SysCtlPeripheralEnable( SYSCTL_PERIPH_GPIOF ); + GPIODirModeSet( GPIO_PORTF_BASE, (GPIO_PIN_2 | GPIO_PIN_3), GPIO_DIR_MODE_HW ); + GPIOPadConfigSet( GPIO_PORTF_BASE, (GPIO_PIN_2 | GPIO_PIN_3 ), GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD ); + + vParTestInitialise(); +} +/*-----------------------------------------------------------*/ + +void vApplicationTickHook( void ) +{ +static xOLEDMessage xMessage = { "PASS" }; +static unsigned portLONG ulTicksSinceLastDisplay = 0; + + /* Called from every tick interrupt. Have enough ticks passed to make it + time to perform our health status check again? */ + ulTicksSinceLastDisplay++; + if( ulTicksSinceLastDisplay >= mainCHECK_DELAY ) + { + ulTicksSinceLastDisplay = 0; + + /* Has an error been found in any task? */ + if( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN GEN Q"; + } + else if( xAreQueuePeekTasksStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN PEEK Q"; + } + else if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN BLOCK Q"; + } + else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN BLOCK TIME"; + } + else if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN SEMAPHORE"; + } + else if( xArePollingQueuesStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN POLL Q"; + } + else if( xIsCreateTaskStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN CREATE"; + } + else if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN MATH"; + } + else if( ulIdleError != pdFALSE ) + { + xMessage.pcMessage = "ERROR IN HOOK"; + } + + /* Send the message to the OLED gatekeeper for display. */ + xQueueSendFromISR( xOLEDQueue, &xMessage, pdFALSE ); + } +} +/*-----------------------------------------------------------*/ + +void vOLEDTask( void *pvParameters ) +{ +xOLEDMessage xMessage; +unsigned portLONG ulY, ulMaxY; +static portCHAR cMessage[ mainMAX_MSG_LEN ]; +extern unsigned portLONG ulMaxJitter; + +/* Functions to access the OLED. The one used depends on the dev kit +being used. */ +void ( *vOLEDInit )( unsigned portLONG ); +void ( *vOLEDStringDraw )( const portCHAR *, unsigned portLONG, unsigned portLONG, unsigned portCHAR ); +void ( *vOLEDImageDraw )( const unsigned portCHAR *, unsigned portLONG, unsigned portLONG, unsigned portLONG, unsigned portLONG ); +void ( *vOLEDClear )( void ); + + /* Map the OLED access functions to the driver functions that are appropriate + for the evaluation kit being used. */ + switch( HWREG( SYSCTL_DID1 ) & SYSCTL_DID1_PRTNO_MASK ) + { + case SYSCTL_DID1_PRTNO_6965 : + case SYSCTL_DID1_PRTNO_2965 : vOLEDInit = OSRAM128x64x4Init; + vOLEDStringDraw = OSRAM128x64x4StringDraw; + vOLEDImageDraw = OSRAM128x64x4ImageDraw; + vOLEDClear = OSRAM128x64x4Clear; + ulMaxY = mainMAX_ROWS_64; + break; + + default : vOLEDInit = RIT128x96x4Init; + vOLEDStringDraw = RIT128x96x4StringDraw; + vOLEDImageDraw = RIT128x96x4ImageDraw; + vOLEDClear = RIT128x96x4Clear; + ulMaxY = mainMAX_ROWS_96; + break; + } + + ulY = ulMaxY; + + /* Initialise the OLED and display a startup message. */ + vOLEDInit( ulSSI_FREQUENCY ); + vOLEDStringDraw( " POWERED BY FreeRTOS", 0, 0, mainFULL_SCALE ); + vOLEDImageDraw( pucImage, 0, mainCHARACTER_HEIGHT + 1, bmpBITMAP_WIDTH, bmpBITMAP_HEIGHT ); + + for( ;; ) + { + /* Wait for a message to arrive that requires displaying. */ + xQueueReceive( xOLEDQueue, &xMessage, portMAX_DELAY ); + + /* Write the message on the next available row. */ + ulY += mainCHARACTER_HEIGHT; + if( ulY >= ulMaxY ) + { + ulY = mainCHARACTER_HEIGHT; + vOLEDClear(); + vOLEDStringDraw( pcWelcomeMessage, 0, 0, mainFULL_SCALE ); + } + + /* Display the message along with the maximum jitter time from the + high priority time test. */ + sprintf( cMessage, "%s [%uns]", xMessage.pcMessage, ulMaxJitter * mainNS_PER_CLOCK ); + vOLEDStringDraw( cMessage, 0, ulY, mainFULL_SCALE ); + } +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ + /* This is just a sanity check function to test the port is + functioning correctly. It can be removed from real applications. + + Fill the general purpose registers with known values. */ + __asm volatile( " mov r11, #10 \n" + " add r0, r11, #1 \n" + " add r1, r11, #2 \n" + " add r2, r11, #3 \n" + " add r3, r11, #4 \n" + " add r4, r11, #5 \n" + " add r5, r11, #6 \n" + " add r6, r11, #7 \n" + " add r7, r11, #8 \n" + " add r8, r11, #9 \n" + " add r9, r11, #10 \n" + " add r10, r11, #11 \n" + " add r12, r11, #12" ); + + /* Check the values are as expected. A context switch might + have occurred since setting the register values. */ + __asm volatile( " cmp r11, #10 \n" + " bne set_error_flag \n" + " cmp r0, #11 \n" + " bne set_error_flag \n" + " cmp r1, #12 \n" + " bne set_error_flag \n" + " cmp r2, #13 \n" + " bne set_error_flag \n" + " cmp r3, #14 \n" + " bne set_error_flag \n" + " cmp r4, #15 \n" + " bne set_error_flag \n" + " cmp r5, #16 \n" + " bne set_error_flag \n" + " cmp r6, #17 \n" + " bne set_error_flag \n" + " cmp r7, #18 \n" + " bne set_error_flag \n" + " cmp r8, #19 \n" + " bne set_error_flag \n" + " cmp r9, #20 \n" + " bne set_error_flag \n" + " cmp r10, #21 \n" + " bne set_error_flag \n" + " cmp r12, #22 \n" + " bne set_error_flag \n" + " bx r14 \n" + " \n" /* If an error is detected in the */ + "set_error_flag: \n" /* value of a register then the error */ + " ldr r1, ulIdleErrorConst\n" /* variable will be set to true. This */ + " mov r0, #1 \n" /* will cause an error message to be */ + " str r0, [r1] \n" /* written to the OLED. */ + " bx r14 \n" + " \n" + " .align 2 \n" + "ulIdleErrorConst: .word ulIdleError" ); +} + + + diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/osram128x64x4.c b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/osram128x64x4.c new file mode 100644 index 000000000..3353a82e6 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/osram128x64x4.c @@ -0,0 +1,933 @@ +//***************************************************************************** +// +// osram128x64x4.c - Driver for the OSRAM 128x64x4 graphical OLED display. +// +// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1408 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup ek_lm3sx965_api +//! @{ +// +//***************************************************************************** + +#include "hw_ssi.h" +#include "hw_memmap.h" +#include "hw_sysctl.h" +#include "hw_types.h" +#include "debug.h" +#include "gpio.h" +#include "ssi.h" +#include "sysctl.h" +#include "osram128x64x4.h" + +//***************************************************************************** +// +// Flag to indicate if SSI port is enabled for OSRAM usage. +// +//***************************************************************************** +static volatile tBoolean g_bSSIEnabled = false; + +//***************************************************************************** +// +// Define the OSRAM 128x64x4 Remap Setting(s). This will be used in +// several places in the code to switch between vertical and horizontal +// address incrementing. +// +// The Remap Command (0xA0) takes one 8-bit parameter. The parameter is +// defined as follows. +// +// Bit 7: Reserved +// Bit 6: Disable(0)/Enable(1) COM Split Odd Even +// When enabled, the COM signals are split Odd on one side, even on +// the other. Otherwise, they are split 0-39 on one side, 40-79 on +// the other. +// Bit 5: Reserved +// Bit 4: Disable(0)/Enable(1) COM Remap +// When Enabled, ROW 0-79 map to COM 79-0 (i.e. reverse row order) +// Bit 3: Reserved +// Bit 2: Horizontal(0)/Vertical(1) Address Increment +// When set, data RAM address will increment along the column rather +// than along the row. +// Bit 1: Disable(0)/Enable(1) Nibble Remap +// When enabled, the upper and lower nibbles in the DATA bus for access +// to the data RAM are swapped. +// Bit 0: Disable(0)/Enable(1) Column Address Remap +// When enabled, DATA RAM columns 0-63 are remapped to Segment Columns +// 127-0. +// +//***************************************************************************** +#define OSRAM_INIT_REMAP 0x52 +#define OSRAM_INIT_OFFSET 0x4C +static const unsigned char g_pucOSRAM128x64x4VerticalInc[] = { 0xA0, 0x56 }; +static const unsigned char g_pucOSRAM128x64x4HorizontalInc[] = { 0xA0, 0x52 }; + +//***************************************************************************** +// +// A 5x7 font (in a 6x8 cell, where the sixth column is omitted from this +// table) for displaying text on the OLED display. The data is organized as +// bytes from the left column to the right column, with each byte containing +// the top row in the LSB and the bottom row in the MSB. +// +// Note: This is the same font data that is used in the EK-LM3S811 +// osram96x16x1 driver. The single bit-per-pixel is expaned in the StringDraw +// function to the appropriate four bit-per-pixel gray scale format. +// +//***************************************************************************** +static const unsigned char g_pucFont[96][5] = +{ + { 0x00, 0x00, 0x00, 0x00, 0x00 }, // " " + { 0x00, 0x00, 0x4f, 0x00, 0x00 }, // ! + { 0x00, 0x07, 0x00, 0x07, 0x00 }, // " + { 0x14, 0x7f, 0x14, 0x7f, 0x14 }, // # + { 0x24, 0x2a, 0x7f, 0x2a, 0x12 }, // $ + { 0x23, 0x13, 0x08, 0x64, 0x62 }, // % + { 0x36, 0x49, 0x55, 0x22, 0x50 }, // & + { 0x00, 0x05, 0x03, 0x00, 0x00 }, // ' + { 0x00, 0x1c, 0x22, 0x41, 0x00 }, // ( + { 0x00, 0x41, 0x22, 0x1c, 0x00 }, // ) + { 0x14, 0x08, 0x3e, 0x08, 0x14 }, // * + { 0x08, 0x08, 0x3e, 0x08, 0x08 }, // + + { 0x00, 0x50, 0x30, 0x00, 0x00 }, // , + { 0x08, 0x08, 0x08, 0x08, 0x08 }, // - + { 0x00, 0x60, 0x60, 0x00, 0x00 }, // . + { 0x20, 0x10, 0x08, 0x04, 0x02 }, // / + { 0x3e, 0x51, 0x49, 0x45, 0x3e }, // 0 + { 0x00, 0x42, 0x7f, 0x40, 0x00 }, // 1 + { 0x42, 0x61, 0x51, 0x49, 0x46 }, // 2 + { 0x21, 0x41, 0x45, 0x4b, 0x31 }, // 3 + { 0x18, 0x14, 0x12, 0x7f, 0x10 }, // 4 + { 0x27, 0x45, 0x45, 0x45, 0x39 }, // 5 + { 0x3c, 0x4a, 0x49, 0x49, 0x30 }, // 6 + { 0x01, 0x71, 0x09, 0x05, 0x03 }, // 7 + { 0x36, 0x49, 0x49, 0x49, 0x36 }, // 8 + { 0x06, 0x49, 0x49, 0x29, 0x1e }, // 9 + { 0x00, 0x36, 0x36, 0x00, 0x00 }, // : + { 0x00, 0x56, 0x36, 0x00, 0x00 }, // ; + { 0x08, 0x14, 0x22, 0x41, 0x00 }, // < + { 0x14, 0x14, 0x14, 0x14, 0x14 }, // = + { 0x00, 0x41, 0x22, 0x14, 0x08 }, // > + { 0x02, 0x01, 0x51, 0x09, 0x06 }, // ? + { 0x32, 0x49, 0x79, 0x41, 0x3e }, // @ + { 0x7e, 0x11, 0x11, 0x11, 0x7e }, // A + { 0x7f, 0x49, 0x49, 0x49, 0x36 }, // B + { 0x3e, 0x41, 0x41, 0x41, 0x22 }, // C + { 0x7f, 0x41, 0x41, 0x22, 0x1c }, // D + { 0x7f, 0x49, 0x49, 0x49, 0x41 }, // E + { 0x7f, 0x09, 0x09, 0x09, 0x01 }, // F + { 0x3e, 0x41, 0x49, 0x49, 0x7a }, // G + { 0x7f, 0x08, 0x08, 0x08, 0x7f }, // H + { 0x00, 0x41, 0x7f, 0x41, 0x00 }, // I + { 0x20, 0x40, 0x41, 0x3f, 0x01 }, // J + { 0x7f, 0x08, 0x14, 0x22, 0x41 }, // K + { 0x7f, 0x40, 0x40, 0x40, 0x40 }, // L + { 0x7f, 0x02, 0x0c, 0x02, 0x7f }, // M + { 0x7f, 0x04, 0x08, 0x10, 0x7f }, // N + { 0x3e, 0x41, 0x41, 0x41, 0x3e }, // O + { 0x7f, 0x09, 0x09, 0x09, 0x06 }, // P + { 0x3e, 0x41, 0x51, 0x21, 0x5e }, // Q + { 0x7f, 0x09, 0x19, 0x29, 0x46 }, // R + { 0x46, 0x49, 0x49, 0x49, 0x31 }, // S + { 0x01, 0x01, 0x7f, 0x01, 0x01 }, // T + { 0x3f, 0x40, 0x40, 0x40, 0x3f }, // U + { 0x1f, 0x20, 0x40, 0x20, 0x1f }, // V + { 0x3f, 0x40, 0x38, 0x40, 0x3f }, // W + { 0x63, 0x14, 0x08, 0x14, 0x63 }, // X + { 0x07, 0x08, 0x70, 0x08, 0x07 }, // Y + { 0x61, 0x51, 0x49, 0x45, 0x43 }, // Z + { 0x00, 0x7f, 0x41, 0x41, 0x00 }, // [ + { 0x02, 0x04, 0x08, 0x10, 0x20 }, // "\" + { 0x00, 0x41, 0x41, 0x7f, 0x00 }, // ] + { 0x04, 0x02, 0x01, 0x02, 0x04 }, // ^ + { 0x40, 0x40, 0x40, 0x40, 0x40 }, // _ + { 0x00, 0x01, 0x02, 0x04, 0x00 }, // ` + { 0x20, 0x54, 0x54, 0x54, 0x78 }, // a + { 0x7f, 0x48, 0x44, 0x44, 0x38 }, // b + { 0x38, 0x44, 0x44, 0x44, 0x20 }, // c + { 0x38, 0x44, 0x44, 0x48, 0x7f }, // d + { 0x38, 0x54, 0x54, 0x54, 0x18 }, // e + { 0x08, 0x7e, 0x09, 0x01, 0x02 }, // f + { 0x0c, 0x52, 0x52, 0x52, 0x3e }, // g + { 0x7f, 0x08, 0x04, 0x04, 0x78 }, // h + { 0x00, 0x44, 0x7d, 0x40, 0x00 }, // i + { 0x20, 0x40, 0x44, 0x3d, 0x00 }, // j + { 0x7f, 0x10, 0x28, 0x44, 0x00 }, // k + { 0x00, 0x41, 0x7f, 0x40, 0x00 }, // l + { 0x7c, 0x04, 0x18, 0x04, 0x78 }, // m + { 0x7c, 0x08, 0x04, 0x04, 0x78 }, // n + { 0x38, 0x44, 0x44, 0x44, 0x38 }, // o + { 0x7c, 0x14, 0x14, 0x14, 0x08 }, // p + { 0x08, 0x14, 0x14, 0x18, 0x7c }, // q + { 0x7c, 0x08, 0x04, 0x04, 0x08 }, // r + { 0x48, 0x54, 0x54, 0x54, 0x20 }, // s + { 0x04, 0x3f, 0x44, 0x40, 0x20 }, // t + { 0x3c, 0x40, 0x40, 0x20, 0x7c }, // u + { 0x1c, 0x20, 0x40, 0x20, 0x1c }, // v + { 0x3c, 0x40, 0x30, 0x40, 0x3c }, // w + { 0x44, 0x28, 0x10, 0x28, 0x44 }, // x + { 0x0c, 0x50, 0x50, 0x50, 0x3c }, // y + { 0x44, 0x64, 0x54, 0x4c, 0x44 }, // z + { 0x00, 0x08, 0x36, 0x41, 0x00 }, // { + { 0x00, 0x00, 0x7f, 0x00, 0x00 }, // | + { 0x00, 0x41, 0x36, 0x08, 0x00 }, // } + { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~ + { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~ +}; + +//***************************************************************************** +// +// The sequence of commands used to initialize the SSD0303 controller. Each +// command is described as follows: there is a byte specifying the number of +// bytes in the command sequence, followed by that many bytes of command data. +// Note: This initialization sequence is derived from OSRAM App Note AN018. +// +//***************************************************************************** +static const unsigned char g_pucOSRAM128x64x4Init[] = +{ + // + // Column Address + // + 4, 0x15, 0, 63, 0xe3, + + // + // Row Address + // + 4, 0x75, 0, 63, 0xe3, + + // + // Contrast Control + // + 3, 0x81, 50, 0xe3, + + // + // Half Current Range + // + 2, 0x85, 0xe3, + + // + // Display Re-map + // + 3, 0xA0, OSRAM_INIT_REMAP, 0xe3, + + // + // Display Start Line + // + 3, 0xA1, 0, 0xe3, + + // + // Display Offset + // + 3, 0xA2, OSRAM_INIT_OFFSET, 0xe3, + + // + // Display Mode Normal + // + 2, 0xA4, 0xe3, + + // + // Multiplex Ratio + // + 3, 0xA8, 63, 0xe3, + + // + // Phase Length + // + 3, 0xB1, 0x22, 0xe3, + + // + // Row Period + // + 3, 0xB2, 70, 0xe3, + + // + // Display Clock Divide + // + 3, 0xB3, 0xF1, 0xe3, + + // + // VSL + // + 3, 0xBF, 0x0D, 0xe3, + + // + // VCOMH + // + 3, 0xBE, 0x02, 0xe3, + + // + // VP + // + 3, 0xBC, 0x10, 0xe3, + + // + // Gamma + // + 10, 0xB8, 0x01, 0x11, 0x22, 0x32, 0x43, 0x54, 0x65, 0x76, 0xe3, + + // + // Set DC-DC + 3, 0xAD, 0x03, 0xe3, + + // + // Display ON/OFF + // + 2, 0xAF, 0xe3, +}; + +//***************************************************************************** +// +//! \internal +//! +//! Write a sequence of command bytes to the SSD0323 controller. +//! +//! The data is written in a polled fashion; this function will not return +//! until the entire byte sequence has been written to the controller. +//! +//! \return None. +// +//***************************************************************************** +static void +OSRAMWriteCommand(const unsigned char *pucBuffer, unsigned long ulCount) +{ + unsigned long ulTemp; + + // + // Return iff SSI port is not enabled for OSRAM. + // + if(!g_bSSIEnabled) + { + return; + } + + // + // Clear the command/control bit to enable command mode. + // + GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, 0); + + // + // Loop while there are more bytes left to be transferred. + // + while(ulCount != 0) + { + // + // Write the next byte to the controller. + // + SSIDataPut(SSI0_BASE, *pucBuffer++); + + // + // Dummy read to drain the fifo and time the GPIO signal. + // + SSIDataGet(SSI0_BASE, &ulTemp); + + // + // Decrement the BYTE counter. + // + ulCount--; + } +} + +//***************************************************************************** +// +//! \internal +//! +//! Write a sequence of data bytes to the SSD0323 controller. +//! +//! The data is written in a polled fashion; this function will not return +//! until the entire byte sequence has been written to the controller. +//! +//! \return None. +// +//***************************************************************************** +static void +OSRAMWriteData(const unsigned char *pucBuffer, unsigned long ulCount) +{ + unsigned long ulTemp; + + // + // Return iff SSI port is not enabled for OSRAM. + // + if(!g_bSSIEnabled) + { + return; + } + + // + // Set the command/control bit to enable data mode. + // + GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_PIN_7); + + // + // Loop while there are more bytes left to be transferred. + // + while(ulCount != 0) + { + // + // Write the next byte to the controller. + // + SSIDataPut(SSI0_BASE, *pucBuffer++); + + // + // Dummy read to drain the fifo and time the GPIO signal. + // + SSIDataGet(SSI0_BASE, &ulTemp); + + // + // Decrement the BYTE counter. + // + ulCount--; + } +} + +//***************************************************************************** +// +//! Clears the OLED display. +//! +//! This function will clear the display RAM. All pixels in the display will +//! be turned off. +//! +//! This function is contained in osram128x64x4.c, with +//! osram128x64x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAM128x64x4Clear(void) +{ + static const unsigned char pucCommand1[] = { 0x15, 0, 63 }; + static const unsigned char pucCommand2[] = { 0x75, 0, 79 }; + unsigned long ulRow, ulColumn; + static unsigned char pucZeroBuffer[8] = { 0, 0, 0, 0, 0, 0, 0, 0}; + + // + // Set the window to fill the entire display. + // + OSRAMWriteCommand(pucCommand1, sizeof(pucCommand1)); + OSRAMWriteCommand(pucCommand2, sizeof(pucCommand2)); + OSRAMWriteCommand(g_pucOSRAM128x64x4VerticalInc, + sizeof(g_pucOSRAM128x64x4VerticalInc)); + + // + // In vertical address increment mode, loop through each column, filling + // each row with 0. + // + for(ulColumn = 0; ulColumn < (128/2); ulColumn++) + { + // + // 8 rows (bytes) per row of text. + // + for(ulRow = 0; ulRow < 80; ulRow += 8) + { + OSRAMWriteData(pucZeroBuffer, sizeof(pucZeroBuffer)); + } + } +} + +//***************************************************************************** +// +//! Displays a string on the OLED display. +//! +//! \param pcStr is a pointer to the string to display. +//! \param ulX is the horizontal position to display the string, specified in +//! columns from the left edge of the display. +//! \param ulY is the vertical position to display the string, specified in +//! rows from the top edge of the display. +//! \param ucLevel is the 4-bit grey scale value to be used for displayed text. +//! +//! This function will draw a string on the display. Only the ASCII characters +//! between 32 (space) and 126 (tilde) are supported; other characters will +//! result in random data being draw on the display (based on whatever appears +//! before/after the font in memory). The font is mono-spaced, so characters +//! such as "i" and "l" have more white space around them than characters such +//! as "m" or "w". +//! +//! If the drawing of the string reaches the right edge of the display, no more +//! characters will be drawn. Therefore, special care is not required to avoid +//! supplying a string that is "too long" to display. +//! +//! This function is contained in osram128x64x4.c, with +//! osram128x64x4.h containing the API definition for use by +//! applications. +//! +//! \note Because the OLED display packs 2 pixels of data in a single byte, the +//! parameter \e ulX must be an even column number (e.g. 0, 2, 4, etc). +//! +//! \return None. +// +//***************************************************************************** +void +OSRAM128x64x4StringDraw(const char *pcStr, unsigned long ulX, + unsigned long ulY, unsigned char ucLevel) +{ + static unsigned char pucBuffer[8]; + unsigned long ulIdx1, ulIdx2; + unsigned char ucTemp; + + // + // Check the arguments. + // + ASSERT(ulX < 128); + ASSERT((ulX & 1) == 0); + ASSERT(ulY < 64); + ASSERT(ucLevel < 16); + + // + // Setup a window starting at the specified column and row, ending + // at the right edge of the display and 8 rows down (single character row). + // + pucBuffer[0] = 0x15; + pucBuffer[1] = ulX / 2; + pucBuffer[2] = 63; + OSRAMWriteCommand(pucBuffer, 3); + pucBuffer[0] = 0x75; + pucBuffer[1] = ulY; + pucBuffer[2] = ulY + 7; + OSRAMWriteCommand(pucBuffer, 3); + OSRAMWriteCommand(g_pucOSRAM128x64x4VerticalInc, + sizeof(g_pucOSRAM128x64x4VerticalInc)); + + // + // Loop while there are more characters in the string. + // + while(*pcStr != 0) + { + // + // Get a working copy of the current character and convert to an + // index into the character bit-map array. + // + ucTemp = *pcStr; + ucTemp &= 0x7F; + if(ucTemp < ' ') + { + ucTemp = ' '; + } + else + { + ucTemp -= ' '; + } + + // + // Build and display the character buffer. + // + for(ulIdx1 = 0; ulIdx1 < 3; ulIdx1++) + { + // + // Convert two columns of 1-bit font data into a single data + // byte column of 4-bit font data. + // + for(ulIdx2 = 0; ulIdx2 < 8; ulIdx2++) + { + pucBuffer[ulIdx2] = 0; + if(g_pucFont[ucTemp][ulIdx1*2] & (1 << ulIdx2)) + { + pucBuffer[ulIdx2] = ((ucLevel << 4) & 0xf0); + } + if((ulIdx1 < 2) && + (g_pucFont[ucTemp][ulIdx1*2+1] & (1 << ulIdx2))) + { + pucBuffer[ulIdx2] |= ((ucLevel << 0) & 0x0f); + } + } + + // + // If there is room, dump the single data byte column to the + // display. Otherwise, bail out. + // + if(ulX < 126) + { + OSRAMWriteData(pucBuffer, 8); + ulX += 2; + } + else + { + return; + } + } + + // + // Advance to the next character. + // + pcStr++; + } +} + +//***************************************************************************** +// +//! Displays an image on the OLED display. +//! +//! \param pucImage is a pointer to the image data. +//! \param ulX is the horizontal position to display this image, specified in +//! columns from the left edge of the display. +//! \param ulY is the vertical position to display this image, specified in +//! rows from the top of the display. +//! \param ulWidth is the width of the image, specified in columns. +//! \param ulHeight is the height of the image, specified in rows. +//! +//! This function will display a bitmap graphic on the display. Because of the +//! format of the display RAM, the starting column (/e ulX) and the number of +//! columns (/e ulWidth) must be an integer multiple of two. +//! +//! The image data is organized with the first row of image data appearing left +//! to right, followed immediately by the second row of image data. Each byte +//! contains the data for two columns in the current row, with the leftmost +//! column being contained in bits 7:4 and the rightmost column being contained +//! in bits 3:0. +//! +//! For example, an image six columns wide and seven scan lines tall would +//! be arranged as follows (showing how the twenty one bytes of the image would +//! appear on the display): +//! +//! \verbatim +//! +-------------------+-------------------+-------------------+ +//! | Byte 0 | Byte 1 | Byte 2 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 3 | Byte 4 | Byte 5 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 6 | Byte 7 | Byte 8 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 9 | Byte 10 | Byte 11 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 12 | Byte 13 | Byte 14 | +//! +---------+---------+---------+--3------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 15 | Byte 16 | Byte 17 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 18 | Byte 19 | Byte 20 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! \endverbatim +//! +//! This function is contained in osram128x64x4.c, with +//! osram128x64x4.h containing the API definition for use by` +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAM128x64x4ImageDraw(const unsigned char *pucImage, unsigned long ulX, + unsigned long ulY, unsigned long ulWidth, + unsigned long ulHeight) +{ + static unsigned char pucBuffer[8]; + + // + // Check the arguments. + // + ASSERT(ulX < 128); + ASSERT((ulX & 1) == 0); + ASSERT(ulY < 64); + ASSERT((ulX + ulWidth) <= 128); + ASSERT((ulY + ulHeight) <= 64); + ASSERT((ulWidth & 1) == 0); + + // + // Setup a window starting at the specified column and row, and ending + // at the column + width and row+height. + // + pucBuffer[0] = 0x15; + pucBuffer[1] = ulX / 2; + pucBuffer[2] = (ulX + ulWidth - 2) / 2; + OSRAMWriteCommand(pucBuffer, 3); + pucBuffer[0] = 0x75; + pucBuffer[1] = ulY; + pucBuffer[2] = ulY + ulHeight - 1; + OSRAMWriteCommand(pucBuffer, 3); + OSRAMWriteCommand(g_pucOSRAM128x64x4HorizontalInc, + sizeof(g_pucOSRAM128x64x4HorizontalInc)); + + // + // Loop while there are more rows to display. + // + while(ulHeight--) + { + // + // Write this row of image data. + // + OSRAMWriteData(pucImage, (ulWidth / 2)); + + // + // Advance to the next row of the image. + // + pucImage += (ulWidth / 2); + } +} + +//***************************************************************************** +// +//! Enable the SSI component of the OLED display driver. +//! +//! \param ulFrequency specifies the SSI Clock Frequency to be used. +//! +//! This function initializes the SSI interface to the OLED display. +//! +//! This function is contained in osram128x64x4.c, with +//! osram128x64x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAM128x64x4Enable(unsigned long ulFrequency) +{ + unsigned long ulTemp; + + // + // Disable the SSI port. + // + SSIDisable(SSI0_BASE); + + // + // Configure the SSI0 port for master mode. + // + SSIConfig(SSI0_BASE, SSI_FRF_MOTO_MODE_2, SSI_MODE_MASTER, ulFrequency, 8); + + // + // (Re)Enable SSI control of the FSS pin. + // + GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_3); + GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA, + GPIO_PIN_TYPE_STD_WPU); + + // + // Enable the SSI port. + // + SSIEnable(SSI0_BASE); + + // + // Drain the receive fifo. + // + while(SSIDataNonBlockingGet(SSI0_BASE, &ulTemp) != 0) + { + } + + // + // Indicate that the OSRAM driver can use the SSI Port. + // + g_bSSIEnabled = true; +} + +//***************************************************************************** +// +//! Enable the SSI component of the OLED display driver. +//! +//! \param ulFrequency specifies the SSI Clock Frequency to be used. +//! +//! This function initializes the SSI interface to the OLED display. +//! +//! This function is contained in osram128x64x4.c, with +//! osram128x64x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAM128x64x4Disable(void) +{ + unsigned long ulTemp; + + // + // Indicate that the OSRAM driver can no longer use the SSI Port. + // + g_bSSIEnabled = false; + + // + // Drain the receive fifo. + // + while(SSIDataNonBlockingGet(SSI0_BASE, &ulTemp) != 0) + { + } + + // + // Disable the SSI port. + // + SSIDisable(SSI0_BASE); + + // + // Disable SSI control of the FSS pin. + // + GPIODirModeSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_DIR_MODE_OUT); + GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA, + GPIO_PIN_TYPE_STD_WPU); + GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_PIN_3); + +} + +//***************************************************************************** +// +//! Initialize the OLED display. +//! +//! \param ulFrequency specifies the SSI Clock Frequency to be used. +//! +//! This function initializes the SSI interface to the OLED display and +//! configures the SSD0323 controller on the panel. +//! +//! This function is contained in osram128x64x4.c, with +//! osram128x64x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAM128x64x4Init(unsigned long ulFrequency) +{ + unsigned long ulIdx; + + // + // Enable the SSI0 and GPIO port blocks as they are needed by this driver. + // + SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC); + + // + // Configure the SSI0CLK and SSIOTX pins for SSI operation. + // + GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5); + GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_2, GPIO_STRENGTH_8MA, + GPIO_PIN_TYPE_STD_WPU); + GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA, + GPIO_PIN_TYPE_STD_WPU); + GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_5, GPIO_STRENGTH_8MA, + GPIO_PIN_TYPE_STD_WPU); + + // + // Configure the PC7 pin as a D/Cn signal for OLED device. + // + GPIODirModeSet(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_DIR_MODE_OUT); + GPIOPadConfigSet(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_STRENGTH_8MA, + GPIO_PIN_TYPE_STD); + GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_PIN_7); + + // + // Configure and enable the SSI0 port for master mode. + // + OSRAM128x64x4Enable(ulFrequency); + + // + // Clear the frame buffer. + // + OSRAM128x64x4Clear(); + + // + // Initialize the SSD0323 controller. Loop through the initialization + // sequence array, sending each command "string" to the controller. + // + for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAM128x64x4Init); + ulIdx += g_pucOSRAM128x64x4Init[ulIdx] + 1) + { + // + // Send this command. + // + OSRAMWriteCommand(g_pucOSRAM128x64x4Init + ulIdx + 1, + g_pucOSRAM128x64x4Init[ulIdx] - 1); + } +} + +//***************************************************************************** +// +//! Turns on the OLED display. +//! +//! This function will turn on the OLED display, causing it to display the +//! contents of its internal frame buffer. +//! +//! This function is contained in osram128x64x4.c, with +//! osram128x64x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAM128x64x4DisplayOn(void) +{ + unsigned long ulIdx; + + // + // Initialize the SSD0323 controller. Loop through the initialization + // sequence array, sending each command "string" to the controller. + // + for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAM128x64x4Init); + ulIdx += g_pucOSRAM128x64x4Init[ulIdx] + 1) + { + // + // Send this command. + // + OSRAMWriteCommand(g_pucOSRAM128x64x4Init + ulIdx + 1, + g_pucOSRAM128x64x4Init[ulIdx] - 1); + } +} + +//***************************************************************************** +// +//! Turns off the OLED display. +//! +//! This function will turn off the OLED display. This will stop the scanning +//! of the panel and turn off the on-chip DC-DC converter, preventing damage to +//! the panel due to burn-in (it has similar characters to a CRT in this +//! respect). +//! +//! This function is contained in osram128x64x4.c, with +//! osram128x64x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAM128x64x4DisplayOff(void) +{ + static const unsigned char pucCommand1[] = + { + 0xAE, 0xAD, 0x02 + }; + + // + // Turn off the DC-DC converter and the display. + // + OSRAMWriteCommand(pucCommand1, sizeof(pucCommand1)); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/osram128x64x4.h b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/osram128x64x4.h new file mode 100644 index 000000000..2ba7cb956 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/osram128x64x4.h @@ -0,0 +1,63 @@ +//***************************************************************************** +// +// osram128x64x4.h - Prototypes for the driver for the OSRAM 128x64x4 graphical +// OLED display. +// +// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1408 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __OSRAM128X64X4_H__ +#define __OSRAM128X64X4_H__ + +//***************************************************************************** +// +// Prototypes for the driver APIs. +// +//***************************************************************************** +extern void OSRAM128x64x4Clear(void); +extern void OSRAM128x64x4StringDraw(const char *pcStr, + unsigned long ulX, + unsigned long ulY, + unsigned char ucLevel); +extern void OSRAM128x64x4ImageDraw(const unsigned char *pucImage, + unsigned long ulX, + unsigned long ulY, + unsigned long ulWidth, + unsigned long ulHeight); +extern void OSRAM128x64x4Init(unsigned long ulFrequency); +extern void OSRAM128x64x4Enable(unsigned long ulFrequency); +extern void OSRAM128x64x4Disable(void); +extern void OSRAM128x64x4DisplayOn(void); +extern void OSRAM128x64x4DisplayOff(void); + +//***************************************************************************** +// +// The following macro(s) map old names for the OSRAM functions to the new +// names. In new code, the new names should be used in favor of the old names. +// +//***************************************************************************** +#ifndef DEPRECATED +#define OSRAM128x64x1InitSSI OSRAM128x64x4Enable +#endif + +#endif // __OSRAM128X64X4_H__ diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/rit128x96x4.c b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/rit128x96x4.c new file mode 100644 index 000000000..cff38d557 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/rit128x96x4.c @@ -0,0 +1,981 @@ +//***************************************************************************** +// +// rit128x96x4.c - Driver for the RIT 128x96x4 graphical OLED display. +// +// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1504-conf of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup ek_lm3sLM3S8962_api +//! @{ +// +//***************************************************************************** + +#include "hw_ssi.h" +#include "hw_memmap.h" +#include "hw_sysctl.h" +#include "hw_types.h" +#include "debug.h" +#include "gpio.h" +#include "ssi.h" +#include "sysctl.h" +#include "rit128x96x4.h" + +//***************************************************************************** +// +// Macros that define the peripheral, port, and pin used for the OLEDDC +// panel control signal. +// +//***************************************************************************** + +unsigned long ulGPIOId = 0, ulGPIOBase = 0, ulOLEDDC_PIN = 0, ulOLEDEN_PIN = 0; + +#define LM3S8962_SYSCTL_PERIPH_GPIO_OLEDDC SYSCTL_PERIPH_GPIOA +#define LM3S8962_GPIO_OLEDDC_BASE GPIO_PORTA_BASE +#define LM3S8962_GPIO_OLEDDC_PIN GPIO_PIN_6 +#define LM3S8962_GPIO_OLEDEN_PIN GPIO_PIN_7 + +#define LM3S1968_SYSCTL_PERIPH_GPIO_OLEDDC SYSCTL_PERIPH_GPIOH +#define LM3S1968_GPIO_OLEDDC_BASE GPIO_PORTH_BASE +#define LM3S1968_GPIO_OLEDDC_PIN GPIO_PIN_2 +#define LM3S1968_GPIO_OLEDEN_PIN GPIO_PIN_3 + + +//***************************************************************************** +// +// Flag to indicate if SSI port is enabled for display usage. +// +//***************************************************************************** +static volatile tBoolean g_bSSIEnabled = false; + +//***************************************************************************** +// +// Buffer for storing sequences of command and data for the display. +// +//***************************************************************************** +static unsigned char g_pucBuffer[8]; + +//***************************************************************************** +// +// Define the SSD1329 128x96x4 Remap Setting(s). This will be used in +// several places in the code to switch between vertical and horizontal +// address incrementing. Note that the controller support 128 rows while +// the RIT display only uses 96. +// +// The Remap Command (0xA0) takes one 8-bit parameter. The parameter is +// defined as follows. +// +// Bit 7: Reserved +// Bit 6: Disable(0)/Enable(1) COM Split Odd Even +// When enabled, the COM signals are split Odd on one side, even on +// the other. Otherwise, they are split 0-63 on one side, 64-127 on +// the other. +// Bit 5: Reserved +// Bit 4: Disable(0)/Enable(1) COM Remap +// When Enabled, ROW 0-127 map to COM 127-0 (i.e. reverse row order) +// Bit 3: Reserved +// Bit 2: Horizontal(0)/Vertical(1) Address Increment +// When set, data RAM address will increment along the column rather +// than along the row. +// Bit 1: Disable(0)/Enable(1) Nibble Remap +// When enabled, the upper and lower nibbles in the DATA bus for access +// to the data RAM are swapped. +// Bit 0: Disable(0)/Enable(1) Column Address Remap +// When enabled, DATA RAM columns 0-63 are remapped to Segment Columns +// 127-0. +// +//***************************************************************************** +#define RIT_INIT_REMAP 0x52 // app note says 0x51 +#define RIT_INIT_OFFSET 0x00 +static const unsigned char g_pucRIT128x96x4VerticalInc[] = { 0xA0, 0x56 }; +static const unsigned char g_pucRIT128x96x4HorizontalInc[] = { 0xA0, 0x52 }; + +//***************************************************************************** +// +// A 5x7 font (in a 6x8 cell, where the sixth column is omitted from this +// table) for displaying text on the OLED display. The data is organized as +// bytes from the left column to the right column, with each byte containing +// the top row in the LSB and the bottom row in the MSB. +// +// Note: This is the same font data that is used in the EK-LM3S811 +// osram96x16x1 driver. The single bit-per-pixel is expaned in the StringDraw +// function to the appropriate four bit-per-pixel gray scale format. +// +//***************************************************************************** +static const unsigned char g_pucFont[96][5] = +{ + { 0x00, 0x00, 0x00, 0x00, 0x00 }, // " " + { 0x00, 0x00, 0x4f, 0x00, 0x00 }, // ! + { 0x00, 0x07, 0x00, 0x07, 0x00 }, // " + { 0x14, 0x7f, 0x14, 0x7f, 0x14 }, // # + { 0x24, 0x2a, 0x7f, 0x2a, 0x12 }, // $ + { 0x23, 0x13, 0x08, 0x64, 0x62 }, // % + { 0x36, 0x49, 0x55, 0x22, 0x50 }, // & + { 0x00, 0x05, 0x03, 0x00, 0x00 }, // ' + { 0x00, 0x1c, 0x22, 0x41, 0x00 }, // ( + { 0x00, 0x41, 0x22, 0x1c, 0x00 }, // ) + { 0x14, 0x08, 0x3e, 0x08, 0x14 }, // * + { 0x08, 0x08, 0x3e, 0x08, 0x08 }, // + + { 0x00, 0x50, 0x30, 0x00, 0x00 }, // , + { 0x08, 0x08, 0x08, 0x08, 0x08 }, // - + { 0x00, 0x60, 0x60, 0x00, 0x00 }, // . + { 0x20, 0x10, 0x08, 0x04, 0x02 }, // / + { 0x3e, 0x51, 0x49, 0x45, 0x3e }, // 0 + { 0x00, 0x42, 0x7f, 0x40, 0x00 }, // 1 + { 0x42, 0x61, 0x51, 0x49, 0x46 }, // 2 + { 0x21, 0x41, 0x45, 0x4b, 0x31 }, // 3 + { 0x18, 0x14, 0x12, 0x7f, 0x10 }, // 4 + { 0x27, 0x45, 0x45, 0x45, 0x39 }, // 5 + { 0x3c, 0x4a, 0x49, 0x49, 0x30 }, // 6 + { 0x01, 0x71, 0x09, 0x05, 0x03 }, // 7 + { 0x36, 0x49, 0x49, 0x49, 0x36 }, // 8 + { 0x06, 0x49, 0x49, 0x29, 0x1e }, // 9 + { 0x00, 0x36, 0x36, 0x00, 0x00 }, // : + { 0x00, 0x56, 0x36, 0x00, 0x00 }, // ; + { 0x08, 0x14, 0x22, 0x41, 0x00 }, // < + { 0x14, 0x14, 0x14, 0x14, 0x14 }, // = + { 0x00, 0x41, 0x22, 0x14, 0x08 }, // > + { 0x02, 0x01, 0x51, 0x09, 0x06 }, // ? + { 0x32, 0x49, 0x79, 0x41, 0x3e }, // @ + { 0x7e, 0x11, 0x11, 0x11, 0x7e }, // A + { 0x7f, 0x49, 0x49, 0x49, 0x36 }, // B + { 0x3e, 0x41, 0x41, 0x41, 0x22 }, // C + { 0x7f, 0x41, 0x41, 0x22, 0x1c }, // D + { 0x7f, 0x49, 0x49, 0x49, 0x41 }, // E + { 0x7f, 0x09, 0x09, 0x09, 0x01 }, // F + { 0x3e, 0x41, 0x49, 0x49, 0x7a }, // G + { 0x7f, 0x08, 0x08, 0x08, 0x7f }, // H + { 0x00, 0x41, 0x7f, 0x41, 0x00 }, // I + { 0x20, 0x40, 0x41, 0x3f, 0x01 }, // J + { 0x7f, 0x08, 0x14, 0x22, 0x41 }, // K + { 0x7f, 0x40, 0x40, 0x40, 0x40 }, // L + { 0x7f, 0x02, 0x0c, 0x02, 0x7f }, // M + { 0x7f, 0x04, 0x08, 0x10, 0x7f }, // N + { 0x3e, 0x41, 0x41, 0x41, 0x3e }, // O + { 0x7f, 0x09, 0x09, 0x09, 0x06 }, // P + { 0x3e, 0x41, 0x51, 0x21, 0x5e }, // Q + { 0x7f, 0x09, 0x19, 0x29, 0x46 }, // R + { 0x46, 0x49, 0x49, 0x49, 0x31 }, // S + { 0x01, 0x01, 0x7f, 0x01, 0x01 }, // T + { 0x3f, 0x40, 0x40, 0x40, 0x3f }, // U + { 0x1f, 0x20, 0x40, 0x20, 0x1f }, // V + { 0x3f, 0x40, 0x38, 0x40, 0x3f }, // W + { 0x63, 0x14, 0x08, 0x14, 0x63 }, // X + { 0x07, 0x08, 0x70, 0x08, 0x07 }, // Y + { 0x61, 0x51, 0x49, 0x45, 0x43 }, // Z + { 0x00, 0x7f, 0x41, 0x41, 0x00 }, // [ + { 0x02, 0x04, 0x08, 0x10, 0x20 }, // "\" + { 0x00, 0x41, 0x41, 0x7f, 0x00 }, // ] + { 0x04, 0x02, 0x01, 0x02, 0x04 }, // ^ + { 0x40, 0x40, 0x40, 0x40, 0x40 }, // _ + { 0x00, 0x01, 0x02, 0x04, 0x00 }, // ` + { 0x20, 0x54, 0x54, 0x54, 0x78 }, // a + { 0x7f, 0x48, 0x44, 0x44, 0x38 }, // b + { 0x38, 0x44, 0x44, 0x44, 0x20 }, // c + { 0x38, 0x44, 0x44, 0x48, 0x7f }, // d + { 0x38, 0x54, 0x54, 0x54, 0x18 }, // e + { 0x08, 0x7e, 0x09, 0x01, 0x02 }, // f + { 0x0c, 0x52, 0x52, 0x52, 0x3e }, // g + { 0x7f, 0x08, 0x04, 0x04, 0x78 }, // h + { 0x00, 0x44, 0x7d, 0x40, 0x00 }, // i + { 0x20, 0x40, 0x44, 0x3d, 0x00 }, // j + { 0x7f, 0x10, 0x28, 0x44, 0x00 }, // k + { 0x00, 0x41, 0x7f, 0x40, 0x00 }, // l + { 0x7c, 0x04, 0x18, 0x04, 0x78 }, // m + { 0x7c, 0x08, 0x04, 0x04, 0x78 }, // n + { 0x38, 0x44, 0x44, 0x44, 0x38 }, // o + { 0x7c, 0x14, 0x14, 0x14, 0x08 }, // p + { 0x08, 0x14, 0x14, 0x18, 0x7c }, // q + { 0x7c, 0x08, 0x04, 0x04, 0x08 }, // r + { 0x48, 0x54, 0x54, 0x54, 0x20 }, // s + { 0x04, 0x3f, 0x44, 0x40, 0x20 }, // t + { 0x3c, 0x40, 0x40, 0x20, 0x7c }, // u + { 0x1c, 0x20, 0x40, 0x20, 0x1c }, // v + { 0x3c, 0x40, 0x30, 0x40, 0x3c }, // w + { 0x44, 0x28, 0x10, 0x28, 0x44 }, // x + { 0x0c, 0x50, 0x50, 0x50, 0x3c }, // y + { 0x44, 0x64, 0x54, 0x4c, 0x44 }, // z + { 0x00, 0x08, 0x36, 0x41, 0x00 }, // { + { 0x00, 0x00, 0x7f, 0x00, 0x00 }, // | + { 0x00, 0x41, 0x36, 0x08, 0x00 }, // } + { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~ + { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~ +}; + +//***************************************************************************** +// +// The sequence of commands used to initialize the SSD1329 controller. Each +// command is described as follows: there is a byte specifying the number of +// bytes in the command sequence, followed by that many bytes of command data. +// Note: This initialization sequence is derived from RIT App Note for +// the P14201. Values used are from the RIT app note, except where noted. +// +//***************************************************************************** +static const unsigned char g_pucRIT128x96x4Init[] = +{ + // + // Unlock commands + // + 3, 0xFD, 0x12, 0xe3, + + // + // Display off + // + 2, 0xAE, 0xe3, + + // + // Icon off + // + 3, 0x94, 0, 0xe3, + + // + // Multiplex ratio + // + 3, 0xA8, 95, 0xe3, + + // + // Contrast + // + 3, 0x81, 0xb7, 0xe3, + + // + // Pre-charge current + // + 3, 0x82, 0x3f, 0xe3, + + // + // Display Re-map + // + 3, 0xA0, RIT_INIT_REMAP, 0xe3, + + // + // Display Start Line + // + 3, 0xA1, 0, 0xe3, + + // + // Display Offset + // + 3, 0xA2, RIT_INIT_OFFSET, 0xe3, + + // + // Display Mode Normal + // + 2, 0xA4, 0xe3, + + // + // Phase Length + // + 3, 0xB1, 0x11, 0xe3, + + // + // Frame frequency + // + 3, 0xB2, 0x23, 0xe3, + + // + // Front Clock Divider + // + 3, 0xB3, 0xe2, 0xe3, + + // + // Set gray scale table. App note uses default command: + // 2, 0xB7, 0xe3 + // This gray scale attempts some gamma correction to reduce the + // the brightness of the low levels. + // + 17, 0xB8, 1, 2, 3, 4, 5, 6, 8, 10, 12, 14, 16, 19, 22, 26, 30, 0xe3, + + // + // Second pre-charge period. App note uses value 0x04. + // + 3, 0xBB, 0x01, 0xe3, + + // + // Pre-charge voltage + // + 3, 0xBC, 0x3f, 0xe3, + + // + // Display ON + // + 2, 0xAF, 0xe3, +}; + +//***************************************************************************** +// +//! \internal +//! +//! Write a sequence of command bytes to the SSD1329 controller. +//! +//! The data is written in a polled fashion; this function will not return +//! until the entire byte sequence has been written to the controller. +//! +//! \return None. +// +//***************************************************************************** +static void +RITWriteCommand(const unsigned char *pucBuffer, unsigned long ulCount) +{ + unsigned long ulTemp; + + // + // Return if SSI port is not enabled for RIT display. + // + if(!g_bSSIEnabled) + { + return; + } + + // + // Clear the command/control bit to enable command mode. + // + GPIOPinWrite(ulGPIOBase, ulOLEDDC_PIN, 0); + + // + // Loop while there are more bytes left to be transferred. + // + while(ulCount != 0) + { + // + // Write the next byte to the controller. + // + SSIDataPut(SSI0_BASE, *pucBuffer++); + + // + // Dummy read to drain the fifo and time the GPIO signal. + // + SSIDataGet(SSI0_BASE, &ulTemp); + + // + // Decrement the BYTE counter. + // + ulCount--; + } +} + +//***************************************************************************** +// +//! \internal +//! +//! Write a sequence of data bytes to the SSD1329 controller. +//! +//! The data is written in a polled fashion; this function will not return +//! until the entire byte sequence has been written to the controller. +//! +//! \return None. +// +//***************************************************************************** +static void +RITWriteData(const unsigned char *pucBuffer, unsigned long ulCount) +{ + unsigned long ulTemp; + + // + // Return if SSI port is not enabled for RIT display. + // + if(!g_bSSIEnabled) + { + return; + } + + // + // Set the command/control bit to enable data mode. + // + GPIOPinWrite(ulGPIOBase, ulOLEDDC_PIN, ulOLEDDC_PIN); + + // + // Loop while there are more bytes left to be transferred. + // + while(ulCount != 0) + { + // + // Write the next byte to the controller. + // + SSIDataPut(SSI0_BASE, *pucBuffer++); + + // + // Dummy read to drain the fifo and time the GPIO signal. + // + SSIDataGet(SSI0_BASE, &ulTemp); + + // + // Decrement the BYTE counter. + // + ulCount--; + } +} + +//***************************************************************************** +// +//! Clears the OLED display. +//! +//! This function will clear the display RAM. All pixels in the display will +//! be turned off. +//! +//! This function is contained in rit128x96x4.c, with +//! rit128x96x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +RIT128x96x4Clear(void) +{ + static const unsigned char pucCommand1[] = { 0x15, 0, 63 }; + static const unsigned char pucCommand2[] = { 0x75, 0, 127 }; + unsigned long ulRow, ulColumn; + + // + // Clear out the buffer used for sending bytes to the display. + *(unsigned long *)&g_pucBuffer[0] = 0; + *(unsigned long *)&g_pucBuffer[4] = 0; + + // + // Set the window to fill the entire display. + // + RITWriteCommand(pucCommand1, sizeof(pucCommand1)); + RITWriteCommand(pucCommand2, sizeof(pucCommand2)); + RITWriteCommand(g_pucRIT128x96x4HorizontalInc, + sizeof(g_pucRIT128x96x4HorizontalInc)); + + // + // Loop through the rows + // + for(ulRow = 0; ulRow < 96; ulRow++) + { + // + // Loop through the columns. Each byte is two pixels, + // and the buffer hold 8 bytes, so 16 pixels are cleared + // at a time. + // + for(ulColumn = 0; ulColumn < 128; ulColumn += 8 * 2) + { + // + // Write 8 clearing bytes to the display, which will + // clear 16 pixels across. + // + RITWriteData(g_pucBuffer, sizeof(g_pucBuffer)); + } + } +} + +//***************************************************************************** +// +//! Displays a string on the OLED display. +//! +//! \param pcStr is a pointer to the string to display. +//! \param ulX is the horizontal position to display the string, specified in +//! columns from the left edge of the display. +//! \param ulY is the vertical position to display the string, specified in +//! rows from the top edge of the display. +//! \param ucLevel is the 4-bit grey scale value to be used for displayed text. +//! +//! This function will draw a string on the display. Only the ASCII characters +//! between 32 (space) and 126 (tilde) are supported; other characters will +//! result in random data being draw on the display (based on whatever appears +//! before/after the font in memory). The font is mono-spaced, so characters +//! such as "i" and "l" have more white space around them than characters such +//! as "m" or "w". +//! +//! If the drawing of the string reaches the right edge of the display, no more +//! characters will be drawn. Therefore, special care is not required to avoid +//! supplying a string that is "too long" to display. +//! +//! This function is contained in rit128x96x4.c, with +//! rit128x96x4.h containing the API definition for use by +//! applications. +//! +//! \note Because the OLED display packs 2 pixels of data in a single byte, the +//! parameter \e ulX must be an even column number (e.g. 0, 2, 4, etc). +//! +//! \return None. +// +//***************************************************************************** +void +RIT128x96x4StringDraw(const char *pcStr, unsigned long ulX, + unsigned long ulY, unsigned char ucLevel) +{ + unsigned long ulIdx1, ulIdx2; + unsigned char ucTemp; + + // + // Check the arguments. + // + ASSERT(ulX < 128); + ASSERT((ulX & 1) == 0); + ASSERT(ulY < 96); + ASSERT(ucLevel < 16); + + // + // Setup a window starting at the specified column and row, ending + // at the right edge of the display and 8 rows down (single character row). + // + g_pucBuffer[0] = 0x15; + g_pucBuffer[1] = ulX / 2; + g_pucBuffer[2] = 63; + RITWriteCommand(g_pucBuffer, 3); + g_pucBuffer[0] = 0x75; + g_pucBuffer[1] = ulY; + g_pucBuffer[2] = ulY + 7; + RITWriteCommand(g_pucBuffer, 3); + RITWriteCommand(g_pucRIT128x96x4VerticalInc, + sizeof(g_pucRIT128x96x4VerticalInc)); + + // + // Loop while there are more characters in the string. + // + while(*pcStr != 0) + { + // + // Get a working copy of the current character and convert to an + // index into the character bit-map array. + // + ucTemp = *pcStr; + ucTemp &= 0x7F; + if(ucTemp < ' ') + { + ucTemp = ' '; + } + else + { + ucTemp -= ' '; + } + + // + // Build and display the character buffer. + // + for(ulIdx1 = 0; ulIdx1 < 3; ulIdx1++) + { + // + // Convert two columns of 1-bit font data into a single data + // byte column of 4-bit font data. + // + for(ulIdx2 = 0; ulIdx2 < 8; ulIdx2++) + { + g_pucBuffer[ulIdx2] = 0; + if(g_pucFont[ucTemp][ulIdx1*2] & (1 << ulIdx2)) + { + g_pucBuffer[ulIdx2] = ((ucLevel << 4) & 0xf0); + } + if((ulIdx1 < 2) && + (g_pucFont[ucTemp][ulIdx1*2+1] & (1 << ulIdx2))) + { + g_pucBuffer[ulIdx2] |= ((ucLevel << 0) & 0x0f); + } + } + + // + // If there is room, dump the single data byte column to the + // display. Otherwise, bail out. + // + if(ulX < 126) + { + RITWriteData(g_pucBuffer, 8); + ulX += 2; + } + else + { + return; + } + } + + // + // Advance to the next character. + // + pcStr++; + } +} + +//***************************************************************************** +// +//! Displays an image on the OLED display. +//! +//! \param pucImage is a pointer to the image data. +//! \param ulX is the horizontal position to display this image, specified in +//! columns from the left edge of the display. +//! \param ulY is the vertical position to display this image, specified in +//! rows from the top of the display. +//! \param ulWidth is the width of the image, specified in columns. +//! \param ulHeight is the height of the image, specified in rows. +//! +//! This function will display a bitmap graphic on the display. Because of the +//! format of the display RAM, the starting column (\e ulX) and the number of +//! columns (\e ulWidth) must be an integer multiple of two. +//! +//! The image data is organized with the first row of image data appearing left +//! to right, followed immediately by the second row of image data. Each byte +//! contains the data for two columns in the current row, with the leftmost +//! column being contained in bits 7:4 and the rightmost column being contained +//! in bits 3:0. +//! +//! For example, an image six columns wide and seven scan lines tall would +//! be arranged as follows (showing how the twenty one bytes of the image would +//! appear on the display): +//! +//! \verbatim +//! +-------------------+-------------------+-------------------+ +//! | Byte 0 | Byte 1 | Byte 2 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 3 | Byte 4 | Byte 5 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 6 | Byte 7 | Byte 8 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 9 | Byte 10 | Byte 11 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 12 | Byte 13 | Byte 14 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 15 | Byte 16 | Byte 17 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 18 | Byte 19 | Byte 20 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! \endverbatim +//! +//! This function is contained in rit128x96x4.c, with +//! rit128x96x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +RIT128x96x4ImageDraw(const unsigned char *pucImage, unsigned long ulX, + unsigned long ulY, unsigned long ulWidth, + unsigned long ulHeight) +{ + // + // Check the arguments. + // + ASSERT(ulX < 128); + ASSERT((ulX & 1) == 0); + ASSERT(ulY < 96); + ASSERT((ulX + ulWidth) <= 128); + ASSERT((ulY + ulHeight) <= 96); + ASSERT((ulWidth & 1) == 0); + + // + // Setup a window starting at the specified column and row, and ending + // at the column + width and row+height. + // + g_pucBuffer[0] = 0x15; + g_pucBuffer[1] = ulX / 2; + g_pucBuffer[2] = (ulX + ulWidth - 2) / 2; + RITWriteCommand(g_pucBuffer, 3); + g_pucBuffer[0] = 0x75; + g_pucBuffer[1] = ulY; + g_pucBuffer[2] = ulY + ulHeight - 1; + RITWriteCommand(g_pucBuffer, 3); + RITWriteCommand(g_pucRIT128x96x4HorizontalInc, + sizeof(g_pucRIT128x96x4HorizontalInc)); + + // + // Loop while there are more rows to display. + // + while(ulHeight--) + { + // + // Write this row of image data. + // + RITWriteData(pucImage, (ulWidth / 2)); + + // + // Advance to the next row of the image. + // + pucImage += (ulWidth / 2); + } +} + +//***************************************************************************** +// +//! Enable the SSI component of the OLED display driver. +//! +//! \param ulFrequency specifies the SSI Clock Frequency to be used. +//! +//! This function initializes the SSI interface to the OLED display. +//! +//! This function is contained in rit128x96x4.c, with +//! rit128x96x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +RIT128x96x4Enable(unsigned long ulFrequency) +{ + unsigned long ulTemp; + + // + // Disable the SSI port. + // + SSIDisable(SSI0_BASE); + + // + // Configure the SSI0 port for master mode. + // + SSIConfig(SSI0_BASE, SSI_FRF_MOTO_MODE_2, SSI_MODE_MASTER, ulFrequency, 8); + + // + // (Re)Enable SSI control of the FSS pin. + // + GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_3); + GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA, + GPIO_PIN_TYPE_STD_WPU); + + // + // Enable the SSI port. + // + SSIEnable(SSI0_BASE); + + // + // Drain the receive fifo. + // + while(SSIDataNonBlockingGet(SSI0_BASE, &ulTemp) != 0) + { + } + + // + // Indicate that the RIT driver can use the SSI Port. + // + g_bSSIEnabled = true; +} + +//***************************************************************************** +// +//! Enable the SSI component of the OLED display driver. +//! +//! This function initializes the SSI interface to the OLED display. +//! +//! This function is contained in rit128x96x4.c, with +//! rit128x96x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +RIT128x96x4Disable(void) +{ + unsigned long ulTemp; + + // + // Indicate that the RIT driver can no longer use the SSI Port. + // + g_bSSIEnabled = false; + + // + // Drain the receive fifo. + // + while(SSIDataNonBlockingGet(SSI0_BASE, &ulTemp) != 0) + { + } + + // + // Disable the SSI port. + // + SSIDisable(SSI0_BASE); + + // + // Disable SSI control of the FSS pin. + // + GPIOPinTypeGPIOOutput(GPIO_PORTA_BASE, GPIO_PIN_3); + GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA, + GPIO_PIN_TYPE_STD_WPU); + GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_PIN_3); +} + +//***************************************************************************** +// +//! Initialize the OLED display. +//! +//! \param ulFrequency specifies the SSI Clock Frequency to be used. +//! +//! This function initializes the SSI interface to the OLED display and +//! configures the SSD1329 controller on the panel. +//! +//! This function is contained in rit128x96x4.c, with +//! rit128x96x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +RIT128x96x4Init(unsigned long ulFrequency) +{ + unsigned long ulIdx; + + + /* Determine which board is being used. */ + if( SysCtlPeripheralPresent( SYSCTL_PERIPH_ETH ) ) + { + /* Ethernet is present, we must be using the LM3S8962 EK. */ + ulGPIOId = LM3S8962_SYSCTL_PERIPH_GPIO_OLEDDC; + ulGPIOBase = LM3S8962_GPIO_OLEDDC_BASE; + ulOLEDDC_PIN = GPIO_PIN_6; + ulOLEDEN_PIN = GPIO_PIN_7; + } + else + { + /* Ethernet is not present, we must be using the LM3S1968 EK. */ + ulGPIOId = LM3S1968_SYSCTL_PERIPH_GPIO_OLEDDC; + ulGPIOBase = LM3S1968_GPIO_OLEDDC_BASE; + ulOLEDDC_PIN = GPIO_PIN_2; + ulOLEDEN_PIN = GPIO_PIN_3; + } + + // + // Enable the SSI0 and GPIO port blocks as they are needed by this driver. + // + SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + SysCtlPeripheralEnable(ulGPIOId); + + // + // Configure the SSI0CLK and SSIOTX pins for SSI operation. + // + GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5); + GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5, + GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD_WPU); + + // + // Configure the GPIO port pin used as a D/Cn signal for OLED device, + // and the port pin used to enable power to the OLED panel. + // + GPIOPinTypeGPIOOutput(ulGPIOBase, ulOLEDDC_PIN | ulOLEDEN_PIN); + GPIOPadConfigSet(ulGPIOBase, ulOLEDDC_PIN | ulOLEDEN_PIN, + GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD); + GPIOPinWrite(ulGPIOBase, ulOLEDDC_PIN | ulOLEDEN_PIN, + ulOLEDDC_PIN | ulOLEDEN_PIN); + + // + // Configure and enable the SSI0 port for master mode. + // + RIT128x96x4Enable(ulFrequency); + + // + // Clear the frame buffer. + // + RIT128x96x4Clear(); + + // + // Initialize the SSD1329 controller. Loop through the initialization + // sequence array, sending each command "string" to the controller. + // + for(ulIdx = 0; ulIdx < sizeof(g_pucRIT128x96x4Init); + ulIdx += g_pucRIT128x96x4Init[ulIdx] + 1) + { + // + // Send this command. + // + RITWriteCommand(g_pucRIT128x96x4Init + ulIdx + 1, + g_pucRIT128x96x4Init[ulIdx] - 1); + } +} + +//***************************************************************************** +// +//! Turns on the OLED display. +//! +//! This function will turn on the OLED display, causing it to display the +//! contents of its internal frame buffer. +//! +//! This function is contained in rit128x96x4.c, with +//! rit128x96x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +RIT128x96x4DisplayOn(void) +{ + unsigned long ulIdx; + + // + // Initialize the SSD1329 controller. Loop through the initialization + // sequence array, sending each command "string" to the controller. + // + for(ulIdx = 0; ulIdx < sizeof(g_pucRIT128x96x4Init); + ulIdx += g_pucRIT128x96x4Init[ulIdx] + 1) + { + // + // Send this command. + // + RITWriteCommand(g_pucRIT128x96x4Init + ulIdx + 1, + g_pucRIT128x96x4Init[ulIdx] - 1); + } +} + +//***************************************************************************** +// +//! Turns off the OLED display. +//! +//! This function will turn off the OLED display. This will stop the scanning +//! of the panel and turn off the on-chip DC-DC converter, preventing damage to +//! the panel due to burn-in (it has similar characters to a CRT in this +//! respect). +//! +//! This function is contained in rit128x96x4.c, with +//! rit128x96x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +RIT128x96x4DisplayOff(void) +{ + static const unsigned char pucCommand1[] = + { + 0xAE, 0xe3 + }; + + // + // Put the display to sleep. + // + RITWriteCommand(pucCommand1, sizeof(pucCommand1)); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/standalone.ld b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/standalone.ld new file mode 100644 index 000000000..35111445b --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/standalone.ld @@ -0,0 +1,60 @@ +/****************************************************************************** + * + * standalone.ld - Linker script for applications using startup.c and + * DriverLib. + * + * Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. + * + * Software License Agreement + * + * Luminary Micro, Inc. (LMI) is supplying this software for use solely and + * exclusively on LMI's microcontroller products. + * + * The software is owned by LMI and/or its suppliers, and is protected under + * applicable copyright laws. All rights are reserved. Any use in violation + * of the foregoing restrictions may subject the user to criminal sanctions + * under applicable laws, as well as to civil liability for the breach of the + * terms and conditions of this license. + * + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + * This is part of revision 1392 of the Stellaris Peripheral Driver Library. + * + *****************************************************************************/ + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 256K + SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + *(.rodata*) + _etext = .; + } > FLASH + + .data : AT (ADDR(.text) + SIZEOF(.text)) + { + _data = .; + *(vtable) + *(.data*) + _edata = .; + } > SRAM + + .bss : + { + _bss = .; + *(.bss*) + *(COMMON) + _ebss = .; + } > SRAM +} diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/startup.c b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/startup.c new file mode 100644 index 000000000..4593d3f43 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/startup.c @@ -0,0 +1,248 @@ +//***************************************************************************** +// +// startup.c - Boot code for Stellaris. +// +// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1392 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +// Forward declaration of the default fault handlers. +// +//***************************************************************************** +void ResetISR(void); +static void NmiSR(void); +static void FaultISR(void); +static void IntDefaultHandler(void); + +//***************************************************************************** +// +// The entry point for the application. +// +//***************************************************************************** +extern int main(void); +extern void xPortPendSVHandler(void); +extern void xPortSysTickHandler(void); +extern void Timer0IntHandler( void ); +extern void vEMAC_ISR(void); + +//***************************************************************************** +// +// Reserve space for the system stack. +// +//***************************************************************************** +#ifndef STACK_SIZE +#define STACK_SIZE 64 +#endif +static unsigned long pulStack[STACK_SIZE]; + +//***************************************************************************** +// +// The minimal vector table for a Cortex M3. Note that the proper constructs +// must be placed on this to ensure that it ends up at physical address +// 0x0000.0000. +// +//***************************************************************************** +__attribute__ ((section(".isr_vector"))) +void (* const g_pfnVectors[])(void) = +{ + (void (*)(void))((unsigned long)pulStack + sizeof(pulStack)), + // The initial stack pointer + ResetISR, // The reset handler + NmiSR, // The NMI handler + FaultISR, // The hard fault handler + IntDefaultHandler, // The MPU fault handler + IntDefaultHandler, // The bus fault handler + IntDefaultHandler, // The usage fault handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // SVCall handler + IntDefaultHandler, // Debug monitor handler + 0, // Reserved + xPortPendSVHandler, // The PendSV handler + xPortSysTickHandler, // The SysTick handler + IntDefaultHandler, // GPIO Port A + IntDefaultHandler, // GPIO Port B + IntDefaultHandler, // GPIO Port C + IntDefaultHandler, // GPIO Port D + IntDefaultHandler, // GPIO Port E + IntDefaultHandler, // UART0 Rx and Tx + IntDefaultHandler, // UART1 Rx and Tx + IntDefaultHandler, // SSI Rx and Tx + IntDefaultHandler, // I2C Master and Slave + IntDefaultHandler, // PWM Fault + IntDefaultHandler, // PWM Generator 0 + IntDefaultHandler, // PWM Generator 1 + IntDefaultHandler, // PWM Generator 2 + IntDefaultHandler, // Quadrature Encoder + IntDefaultHandler, // ADC Sequence 0 + IntDefaultHandler, // ADC Sequence 1 + IntDefaultHandler, // ADC Sequence 2 + IntDefaultHandler, // ADC Sequence 3 + IntDefaultHandler, // Watchdog timer + Timer0IntHandler, // Timer 0 subtimer A + IntDefaultHandler, // Timer 0 subtimer B + IntDefaultHandler, // Timer 1 subtimer A + IntDefaultHandler, // Timer 1 subtimer B + IntDefaultHandler, // Timer 2 subtimer A + IntDefaultHandler, // Timer 2 subtimer B + IntDefaultHandler, // Analog Comparator 0 + IntDefaultHandler, // Analog Comparator 1 + IntDefaultHandler, // Analog Comparator 2 + IntDefaultHandler, // System Control (PLL, OSC, BO) + IntDefaultHandler, // FLASH Control + IntDefaultHandler, // GPIO Port F + IntDefaultHandler, // GPIO Port G + IntDefaultHandler, // GPIO Port H + IntDefaultHandler, // UART2 Rx and Tx + IntDefaultHandler, // SSI1 Rx and Tx + IntDefaultHandler, // Timer 3 subtimer A + IntDefaultHandler, // Timer 3 subtimer B + IntDefaultHandler, // I2C1 Master and Slave + IntDefaultHandler, // Quadrature Encoder 1 + IntDefaultHandler, // CAN0 + IntDefaultHandler, // CAN1 + 0, // Reserved + vEMAC_ISR, // Ethernet + IntDefaultHandler // Hibernate +}; + +//***************************************************************************** +// +// The following are constructs created by the linker, indicating where the +// the "data" and "bss" segments reside in memory. The initializers for the +// for the "data" segment resides immediately following the "text" segment. +// +//***************************************************************************** +extern unsigned long _etext; +extern unsigned long _data; +extern unsigned long _edata; +extern unsigned long _bss; +extern unsigned long _ebss; + +//***************************************************************************** +// +// This is the code that gets called when the processor first starts execution +// following a reset event. Only the absolutely necessary set is performed, +// after which the application supplied main() routine is called. Any fancy +// actions (such as making decisions based on the reset cause register, and +// resetting the bits in that register) are left solely in the hands of the +// application. +// +//***************************************************************************** +void +ResetISR(void) +{ + unsigned long *pulSrc, *pulDest; + + // + // Copy the data segment initializers from flash to SRAM. + // + pulSrc = &_etext; + for(pulDest = &_data; pulDest < &_edata; ) + { + *pulDest++ = *pulSrc++; + } + + // + // Zero fill the bss segment. + // + for(pulDest = &_bss; pulDest < &_ebss; ) + { + *pulDest++ = 0; + } + + // + // Call the application's entry point. + // + main(); +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a NMI. This +// simply enters an infinite loop, preserving the system state for examination +// by a debugger. +// +//***************************************************************************** +static void +NmiSR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a fault +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +FaultISR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives an unexpected +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +IntDefaultHandler(void) +{ + // + // Go into an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// A dummy printf function to satisfy the calls to printf from uip. This +// avoids pulling in the run-time library. +// +//***************************************************************************** +int +uipprintf(const char *fmt, ...) +{ + return(0); +} + diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/timertest.c b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/timertest.c new file mode 100644 index 000000000..c060800ed --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/timertest.c @@ -0,0 +1,140 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* High speed timer test as described in main.c. */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* Library includes. */ +#include "hw_ints.h" +#include "hw_memmap.h" +#include "hw_types.h" +#include "interrupt.h" +#include "sysctl.h" +#include "lmi_timer.h" + +/* The set frequency of the interrupt. Deviations from this are measured as +the jitter. */ +#define timerINTERRUPT_FREQUENCY ( 20000UL ) + +/* The expected time between each of the timer interrupts - if the jitter was +zero. */ +#define timerEXPECTED_DIFFERENCE_VALUE ( configCPU_CLOCK_HZ / timerINTERRUPT_FREQUENCY ) + +/* The highest available interrupt priority. */ +#define timerHIGHEST_PRIORITY ( 0 ) + +/* Misc defines. */ +#define timerMAX_32BIT_VALUE ( 0xffffffffUL ) +#define timerTIMER_1_COUNT_VALUE ( * ( ( unsigned long * ) ( TIMER1_BASE + 0x48 ) ) ) + +/*-----------------------------------------------------------*/ + +/* Interrupt handler in which the jitter is measured. */ +void Timer0IntHandler( void ); + +/* Stores the value of the maximum recorded jitter between interrupts. */ +unsigned portLONG ulMaxJitter = 0; + +/*-----------------------------------------------------------*/ + +void vSetupTimer( void ) +{ +unsigned long ulFrequency; + + /* Timer zero is used to generate the interrupts, and timer 1 is used + to measure the jitter. */ + SysCtlPeripheralEnable( SYSCTL_PERIPH_TIMER0 ); + SysCtlPeripheralEnable( SYSCTL_PERIPH_TIMER1 ); + TimerConfigure( TIMER0_BASE, TIMER_CFG_32_BIT_PER ); + TimerConfigure( TIMER1_BASE, TIMER_CFG_32_BIT_PER ); + + /* Set the timer interrupt to be above the kernel - highest. */ + IntPrioritySet( INT_TIMER0A, timerHIGHEST_PRIORITY ); + + /* Just used to measure time. */ + TimerLoadSet(TIMER1_BASE, TIMER_A, timerMAX_32BIT_VALUE ); + + /* The rate at which the timer will interrupt. */ + ulFrequency = configCPU_CLOCK_HZ / timerINTERRUPT_FREQUENCY; + TimerLoadSet( TIMER0_BASE, TIMER_A, ulFrequency ); + IntEnable( INT_TIMER0A ); + TimerIntEnable( TIMER0_BASE, TIMER_TIMA_TIMEOUT ); + + /* Enable both timers. */ + TimerEnable( TIMER0_BASE, TIMER_A ); + TimerEnable( TIMER1_BASE, TIMER_A ); +} +/*-----------------------------------------------------------*/ + +void Timer0IntHandler( void ) +{ +unsigned portLONG ulDifference, ulCurrentCount; +static portLONG ulMaxDifference = 0, ulLastCount = 0; + + /* We use the timer 1 counter value to measure the clock cycles between + the timer 0 interrupts. */ + ulCurrentCount = timerTIMER_1_COUNT_VALUE; + + if( ulCurrentCount < ulLastCount ) + { + /* How many times has timer 1 counted since the last interrupt? */ + ulDifference = ulLastCount - ulCurrentCount; + + /* Is this the largest difference we have measured yet? */ + if( ulDifference > ulMaxDifference ) + { + ulMaxDifference = ulDifference; + ulMaxJitter = ulMaxDifference - timerEXPECTED_DIFFERENCE_VALUE; + } + } + + ulLastCount = ulCurrentCount; + + TimerIntClear( TIMER0_BASE, TIMER_TIMA_TIMEOUT ); +} + + + + + diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/Makefile.webserver b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/Makefile.webserver new file mode 100644 index 000000000..f38c47a72 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/Makefile.webserver @@ -0,0 +1 @@ +APP_SOURCES += httpd.c http-strings.c httpd-fs.c httpd-cgi.c diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/clock-arch.h b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/clock-arch.h new file mode 100644 index 000000000..cde657b62 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/clock-arch.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2006, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: clock-arch.h,v 1.2 2006/06/12 08:00:31 adam Exp $ + */ + +#ifndef __CLOCK_ARCH_H__ +#define __CLOCK_ARCH_H__ + +#include "FreeRTOS.h" + +typedef unsigned long clock_time_t; +#define CLOCK_CONF_SECOND configTICK_RATE_HZ + +#endif /* __CLOCK_ARCH_H__ */ diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/emac.c b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/emac.c new file mode 100644 index 000000000..380928cb1 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/emac.c @@ -0,0 +1,281 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "Semphr.h" +#include "task.h" + +/* Demo includes. */ +#include "EMAC.h" + +/* uIP includes. */ +#include "uip.h" + +/* Hardware library includes. */ +#include "hw_types.h" +#include "hw_memmap.h" +#include "hw_ints.h" +#include "hw_ethernet.h" +#include "ethernet.h" +#include "interrupt.h" + +#define emacNUM_RX_BUFFERS 5 +#define emacFRAM_SIZE_BYTES 2 +#define macNEGOTIATE_DELAY 2000 +#define macWAIT_SEND_TIME ( 10 ) + +/* The task that handles the MAC peripheral. This is created at a high +priority and is effectively a deferred interrupt handler. The peripheral +handling is deferred to a task to prevent the entire FIFO having to be read +from within an ISR. */ +void vMACHandleTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* The semaphore used to wake the uIP task when data arrives. */ +xSemaphoreHandle xEMACSemaphore = NULL; + +/* The semaphore used to wake the interrupt handler task. The peripheral +is processed at the task level to prevent the need to read the entire FIFO from +within the ISR itself. */ +xSemaphoreHandle xMACInterruptSemaphore = NULL; + +/* The buffer used by the uIP stack. In this case the pointer is used to +point to one of the Rx buffers. */ +unsigned portCHAR *uip_buf; + +/* Buffers into which Rx data is placed. */ +static unsigned portCHAR ucRxBuffers[ emacNUM_RX_BUFFERS ][ UIP_BUFSIZE + ( 4 * emacFRAM_SIZE_BYTES ) ]; + +/* The length of the data within each of the Rx buffers. */ +static unsigned portLONG ulRxLength[ emacNUM_RX_BUFFERS ]; + +/* Used to keep a track of the number of bytes to transmit. */ +static unsigned portLONG ulNextTxSpace; + +/*-----------------------------------------------------------*/ + +portBASE_TYPE vInitEMAC( void ) +{ +unsigned long ulTemp; +portBASE_TYPE xReturn; + + /* Ensure all interrupts are disabled. */ + EthernetIntDisable( ETH_BASE, ( ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER | ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER | ETH_INT_RX)); + + /* Clear any interrupts that were already pending. */ + ulTemp = EthernetIntStatus( ETH_BASE, pdFALSE ); + EthernetIntClear( ETH_BASE, ulTemp ); + + /* Initialise the MAC and connect. */ + EthernetInit( ETH_BASE ); + EthernetConfigSet( ETH_BASE, ( ETH_CFG_TX_DPLXEN | ETH_CFG_TX_CRCEN | ETH_CFG_TX_PADEN ) ); + EthernetEnable( ETH_BASE ); + + /* Mark each Rx buffer as empty. */ + for( ulTemp = 0; ulTemp < emacNUM_RX_BUFFERS; ulTemp++ ) + { + ulRxLength[ ulTemp ] = 0; + } + + /* Create the queue and task used to defer the MAC processing to the + task level. */ + vSemaphoreCreateBinary( xMACInterruptSemaphore ); + xSemaphoreTake( xMACInterruptSemaphore, 0 ); + xReturn = xTaskCreate( vMACHandleTask, ( signed portCHAR * ) "MAC", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL ); + vTaskDelay( macNEGOTIATE_DELAY ); + + /* We are only interested in Rx interrupts. */ + IntPrioritySet( INT_ETH, configKERNEL_INTERRUPT_PRIORITY ); + IntEnable( INT_ETH ); + EthernetIntEnable(ETH_BASE, ETH_INT_RX); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +unsigned int uiGetEMACRxData( unsigned char *ucBuffer ) +{ +static unsigned long ulNextRxBuffer = 0; +unsigned int iLen; + + iLen = ulRxLength[ ulNextRxBuffer ]; + + if( iLen != 0 ) + { + /* Leave room for the size at the start of the buffer. */ + uip_buf = &( ucRxBuffers[ ulNextRxBuffer ][ 2 ] ); + + ulRxLength[ ulNextRxBuffer ] = 0; + + ulNextRxBuffer++; + if( ulNextRxBuffer >= emacNUM_RX_BUFFERS ) + { + ulNextRxBuffer = 0; + } + } + + return iLen; +} +/*-----------------------------------------------------------*/ + +void vInitialiseSend( void ) +{ + /* Set the index to the first byte to send - skipping over the size + bytes. */ + ulNextTxSpace = 2; +} +/*-----------------------------------------------------------*/ + +void vIncrementTxLength( unsigned portLONG ulLength ) +{ + ulNextTxSpace += ulLength; +} +/*-----------------------------------------------------------*/ + +void vSendBufferToMAC( void ) +{ +unsigned long *pulSource; +unsigned portSHORT * pus; +unsigned portLONG ulNextWord; + + /* Locate the data to be send. */ + pus = ( unsigned portSHORT * ) uip_buf; + + /* Add in the size of the data. */ + pus--; + *pus = ulNextTxSpace; + + /* Wait for data to be sent if there is no space immediately. */ + while( !EthernetSpaceAvail( ETH_BASE ) ) + { + vTaskDelay( macWAIT_SEND_TIME ); + } + + pulSource = ( unsigned portLONG * ) pus; + + for( ulNextWord = 0; ulNextWord < ulNextTxSpace; ulNextWord += sizeof( unsigned portLONG ) ) + { + HWREG(ETH_BASE + MAC_O_DATA) = *pulSource; + pulSource++; + } + + /* Go. */ + HWREG( ETH_BASE + MAC_O_TR ) = MAC_TR_NEWTX; +} +/*-----------------------------------------------------------*/ + +void vEMAC_ISR( void ) +{ +portBASE_TYPE xSwitchRequired = pdFALSE; +unsigned portLONG ulTemp; + + /* Clear the interrupt. */ + ulTemp = EthernetIntStatus( ETH_BASE, pdFALSE ); + EthernetIntClear( ETH_BASE, ulTemp ); + + /* Was it an Rx interrupt? */ + if( ulTemp & ETH_INT_RX ) + { + xSwitchRequired = pdTRUE; + xSemaphoreGiveFromISR( xMACInterruptSemaphore, pdFALSE ); + EthernetIntDisable( ETH_BASE, ETH_INT_RX ); + } + + /* Switch to the uIP task. */ + portEND_SWITCHING_ISR( xSwitchRequired ); +} +/*-----------------------------------------------------------*/ + +void vMACHandleTask( void *pvParameters ) +{ +unsigned long ulLen = 0, i; +unsigned portLONG ulLength, ulInt; +unsigned long *pulBuffer; +static unsigned portLONG ulNextRxBuffer = 0; +portBASE_TYPE xSwitchRequired = pdFALSE; + + for( ;; ) + { + /* Wait for something to do. */ + xSemaphoreTake( xMACInterruptSemaphore, portMAX_DELAY ); + + while( ( ulInt = ( EthernetIntStatus( ETH_BASE, pdFALSE ) & ETH_INT_RX ) ) != 0 ) + { + ulLength = HWREG( ETH_BASE + MAC_O_DATA ); + + /* Leave room at the start of the buffer for the size. */ + pulBuffer = ( unsigned long * ) &( ucRxBuffers[ ulNextRxBuffer ][ 2 ] ); + *pulBuffer = ( ulLength >> 16 ); + + /* Get the size of the data. */ + pulBuffer = ( unsigned long * ) &( ucRxBuffers[ ulNextRxBuffer ][ 4 ] ); + ulLength &= 0xFFFF; + + if( ulLength > 4 ) + { + ulLength -= 4; + + if( ulLength >= UIP_BUFSIZE ) + { + /* The data won't fit in our buffer. Ensure we don't + try to write into the buffer. */ + ulLength = 0; + } + + /* Read out the data into our buffer. */ + for( i = 0; i < ulLength; i += sizeof( unsigned portLONG ) ) + { + *pulBuffer = HWREG( ETH_BASE + MAC_O_DATA ); + pulBuffer++; + } + + /* Store the length of the data into the separate array. */ + ulRxLength[ ulNextRxBuffer ] = ulLength; + + /* Use the next buffer the next time through. */ + ulNextRxBuffer++; + if( ulNextRxBuffer >= emacNUM_RX_BUFFERS ) + { + ulNextRxBuffer = 0; + } + + /* Ensure the uIP task is not blocked as data has arrived. */ + xSemaphoreGive( xEMACSemaphore ); + } + } + + EthernetIntEnable( ETH_BASE, ETH_INT_RX ); + } +} + diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/emac.h b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/emac.h new file mode 100644 index 000000000..a49b59828 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/emac.h @@ -0,0 +1,322 @@ +/*---------------------------------------------------------------------------- + * LPC2378 Ethernet Definitions + *---------------------------------------------------------------------------- + * Name: EMAC.H + * Purpose: Philips LPC2378 EMAC hardware definitions + *---------------------------------------------------------------------------- + * Copyright (c) 2006 KEIL - An ARM Company. All rights reserved. + *---------------------------------------------------------------------------*/ +#ifndef __EMAC_H +#define __EMAC_H + +/* MAC address definition. The MAC address must be unique on the network. */ +#define emacETHADDR0 0 +#define emacETHADDR1 0xbd +#define emacETHADDR2 0x33 +#define emacETHADDR3 0x02 +#define emacETHADDR4 0x64 +#define emacETHADDR5 0x24 + + +/* EMAC Memory Buffer configuration for 16K Ethernet RAM. */ +#define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */ +#define NUM_TX_FRAG 2 /* Num.of TX Fragments 2*1536= 3.0kB */ +#define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */ + +#define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */ + +/* EMAC variables located in 16K Ethernet SRAM */ +#define RX_DESC_BASE 0x7FE00000 +#define RX_STAT_BASE (RX_DESC_BASE + NUM_RX_FRAG*8) +#define TX_DESC_BASE (RX_STAT_BASE + NUM_RX_FRAG*8) +#define TX_STAT_BASE (TX_DESC_BASE + NUM_TX_FRAG*8) +#define RX_BUF_BASE (TX_STAT_BASE + NUM_TX_FRAG*4) +#define TX_BUF_BASE (RX_BUF_BASE + NUM_RX_FRAG*ETH_FRAG_SIZE) + +/* RX and TX descriptor and status definitions. */ +#define RX_DESC_PACKET(i) (*(unsigned int *)(RX_DESC_BASE + 8*i)) +#define RX_DESC_CTRL(i) (*(unsigned int *)(RX_DESC_BASE+4 + 8*i)) +#define RX_STAT_INFO(i) (*(unsigned int *)(RX_STAT_BASE + 8*i)) +#define RX_STAT_HASHCRC(i) (*(unsigned int *)(RX_STAT_BASE+4 + 8*i)) +#define TX_DESC_PACKET(i) (*(unsigned int *)(TX_DESC_BASE + 8*i)) +#define TX_DESC_CTRL(i) (*(unsigned int *)(TX_DESC_BASE+4 + 8*i)) +#define TX_STAT_INFO(i) (*(unsigned int *)(TX_STAT_BASE + 4*i)) +#define RX_BUF(i) (RX_BUF_BASE + ETH_FRAG_SIZE*i) +#define TX_BUF(i) (TX_BUF_BASE + ETH_FRAG_SIZE*i) + +/* MAC Configuration Register 1 */ +#define MAC1_REC_EN 0x00000001 /* Receive Enable */ +#define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */ +#define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */ +#define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */ +#define MAC1_LOOPB 0x00000010 /* Loop Back Mode */ +#define MAC1_RES_TX 0x00000100 /* Reset TX Logic */ +#define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */ +#define MAC1_RES_RX 0x00000400 /* Reset RX Logic */ +#define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */ +#define MAC1_SIM_RES 0x00004000 /* Simulation Reset */ +#define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */ + +/* MAC Configuration Register 2 */ +#define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */ +#define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */ +#define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */ +#define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */ +#define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */ +#define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */ +#define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */ +#define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */ +#define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */ +#define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */ +#undef MAC2_NO_BACKOFF /* Remove compiler warning. */ +#define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */ +#define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */ +#define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */ + +/* Back-to-Back Inter-Packet-Gap Register */ +#define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */ +#define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */ + +/* Non Back-to-Back Inter-Packet-Gap Register */ +#define IPGR_DEF 0x00000012 /* Recommended value */ + +/* Collision Window/Retry Register */ +#define CLRT_DEF 0x0000370F /* Default value */ + +/* PHY Support Register */ +#undef SUPP_SPEED /* Remove compiler warning. */ +#define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */ +#define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */ + +/* Test Register */ +#define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */ +#define TEST_TST_PAUSE 0x00000002 /* Test Pause */ +#define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */ + +/* MII Management Configuration Register */ +#define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */ +#define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */ +#define MCFG_CLK_SEL 0x0000001C /* Clock Select Mask */ +#define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */ + +/* MII Management Command Register */ +#undef MCMD_READ /* Remove compiler warning. */ +#define MCMD_READ 0x00000001 /* MII Read */ +#undef MCMD_SCAN /* Remove compiler warning. */ +#define MCMD_SCAN 0x00000002 /* MII Scan continuously */ + +#define MII_WR_TOUT 0x00050000 /* MII Write timeout count */ +#define MII_RD_TOUT 0x00050000 /* MII Read timeout count */ + +/* MII Management Address Register */ +#define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */ +#define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */ + +/* MII Management Indicators Register */ +#undef MIND_BUSY /* Remove compiler warning. */ +#define MIND_BUSY 0x00000001 /* MII is Busy */ +#define MIND_SCAN 0x00000002 /* MII Scanning in Progress */ +#define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */ +#define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */ + +/* Command Register */ +#define CR_RX_EN 0x00000001 /* Enable Receive */ +#define CR_TX_EN 0x00000002 /* Enable Transmit */ +#define CR_REG_RES 0x00000008 /* Reset Host Registers */ +#define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */ +#define CR_RX_RES 0x00000020 /* Reset Receive Datapath */ +#define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */ +#define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */ +#define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */ +#define CR_RMII 0x00000200 /* Reduced MII Interface */ +#define CR_FULL_DUP 0x00000400 /* Full Duplex */ + +/* Status Register */ +#define SR_RX_EN 0x00000001 /* Enable Receive */ +#define SR_TX_EN 0x00000002 /* Enable Transmit */ + +/* Transmit Status Vector 0 Register */ +#define TSV0_CRC_ERR 0x00000001 /* CRC error */ +#define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */ +#define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */ +#define TSV0_DONE 0x00000008 /* Tramsmission Completed */ +#define TSV0_MCAST 0x00000010 /* Multicast Destination */ +#define TSV0_BCAST 0x00000020 /* Broadcast Destination */ +#define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */ +#define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */ +#define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */ +#define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */ +#define TSV0_GIANT 0x00000400 /* Giant Frame */ +#define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */ +#define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */ +#define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */ +#define TSV0_PAUSE 0x20000000 /* Pause Frame */ +#define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */ +#define TSV0_VLAN 0x80000000 /* VLAN Frame */ + +/* Transmit Status Vector 1 Register */ +#define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */ +#define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */ + +/* Receive Status Vector Register */ +#define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */ +#define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */ +#define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */ +#define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */ +#define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */ +#define RSV_CRC_ERR 0x00100000 /* CRC Error */ +#define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */ +#define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */ +#define RSV_REC_OK 0x00800000 /* Frame Received OK */ +#define RSV_MCAST 0x01000000 /* Multicast Frame */ +#define RSV_BCAST 0x02000000 /* Broadcast Frame */ +#define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */ +#define RSV_CTRL_FRAME 0x08000000 /* Control Frame */ +#define RSV_PAUSE 0x10000000 /* Pause Frame */ +#define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */ +#define RSV_VLAN 0x40000000 /* VLAN Frame */ + +/* Flow Control Counter Register */ +#define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */ +#define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */ + +/* Flow Control Status Register */ +#define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */ + +/* Receive Filter Control Register */ +#define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */ +#define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */ +#define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */ +#define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */ +#define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/ +#define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */ +#define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */ +#define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */ + +/* Receive Filter WoL Status/Clear Registers */ +#define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */ +#define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */ +#define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */ +#define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */ +#define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */ +#define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */ +#define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */ +#define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */ + +/* Interrupt Status/Enable/Clear/Set Registers */ +#define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */ +#define INT_RX_ERR 0x00000002 /* Receive Error */ +#define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */ +#define INT_RX_DONE 0x00000008 /* Receive Done */ +#define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */ +#define INT_TX_ERR 0x00000020 /* Transmit Error */ +#define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */ +#define INT_TX_DONE 0x00000080 /* Transmit Done */ +#define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */ +#define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */ + +/* Power Down Register */ +#define PD_POWER_DOWN 0x80000000 /* Power Down MAC */ + +/* RX Descriptor Control Word */ +#define RCTRL_SIZE 0x000007FF /* Buffer size mask */ +#define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */ + +/* RX Status Hash CRC Word */ +#define RHASH_SA 0x000001FF /* Hash CRC for Source Address */ +#define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */ + +/* RX Status Information Word */ +#define RINFO_SIZE 0x000007FF /* Data size in bytes */ +#define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */ +#define RINFO_VLAN 0x00080000 /* VLAN Frame */ +#define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */ +#define RINFO_MCAST 0x00200000 /* Multicast Frame */ +#define RINFO_BCAST 0x00400000 /* Broadcast Frame */ +#define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */ +#define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */ +#define RINFO_LEN_ERR 0x02000000 /* Length Error */ +#define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */ +#define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */ +#define RINFO_OVERRUN 0x10000000 /* Receive overrun */ +#define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */ +#define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */ +#define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ + +#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | \ + RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN) + +/* TX Descriptor Control Word */ +#define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */ +#define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */ +#define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */ +#define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */ +#define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */ +#define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */ +#define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */ + +/* TX Status Information Word */ +#define TINFO_COL_CNT 0x01E00000 /* Collision Count */ +#define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */ +#define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */ +#define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */ +#define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */ +#define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */ +#define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */ +#define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ + +/* DP83848C PHY Registers */ +#define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */ +#define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */ +#define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */ +#define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */ +#define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */ +#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */ +#define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */ +#define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */ + +/* PHY Extended Registers */ +#define PHY_REG_STS 0x10 /* Status Register */ +#define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */ +#define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */ +#define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */ +#define PHY_REG_RECR 0x15 /* Receive Error Counter */ +#define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */ +#define PHY_REG_RBR 0x17 /* RMII and Bypass Register */ +#define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */ +#define PHY_REG_PHYCR 0x19 /* PHY Control Register */ +#define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */ +#define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */ +#define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */ + +#define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */ +#define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */ +#define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */ +#define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */ +#define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */ + +#define DP83848C_DEF_ADR 0x0100 /* Default PHY device address */ +#define DP83848C_ID 0x20005C90 /* PHY Identifier */ + +// prototypes +portBASE_TYPE vInitEMAC(void); +unsigned short ReadFrameBE_EMAC(void); +void vIncrementTxLength(unsigned long ulLength); +void CopyFromFrame_EMAC(void *Dest, unsigned short Size); +void DummyReadFrame_EMAC(unsigned short Size); +unsigned short StartReadFrame(void); +void EndReadFrame(void); +unsigned int CheckFrameReceived(void); +void vInitialiseSend(void); +unsigned int Rdy4Tx(void); +void vSendBufferToMAC(void); +void vEMACWaitForInput( void ); +unsigned int uiGetEMACRxData( unsigned char *ucBuffer ); + + +#endif + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/http-strings b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/http-strings new file mode 100644 index 000000000..0d3c30cdd --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/http-strings @@ -0,0 +1,35 @@ +http_http "http://" +http_200 "200 " +http_301 "301 " +http_302 "302 " +http_get "GET " +http_10 "HTTP/1.0" +http_11 "HTTP/1.1" +http_content_type "content-type: " +http_texthtml "text/html" +http_location "location: " +http_host "host: " +http_crnl "\r\n" +http_index_html "/index.html" +http_404_html "/404.html" +http_referer "Referer:" +http_header_200 "HTTP/1.0 200 OK\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" +http_header_404 "HTTP/1.0 404 Not found\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" +http_content_type_plain "Content-type: text/plain\r\n\r\n" +http_content_type_html "Content-type: text/html\r\n\r\n" +http_content_type_css "Content-type: text/css\r\n\r\n" +http_content_type_text "Content-type: text/text\r\n\r\n" +http_content_type_png "Content-type: image/png\r\n\r\n" +http_content_type_gif "Content-type: image/gif\r\n\r\n" +http_content_type_jpg "Content-type: image/jpeg\r\n\r\n" +http_content_type_binary "Content-type: application/octet-stream\r\n\r\n" +http_html ".html" +http_shtml ".shtml" +http_htm ".htm" +http_css ".css" +http_png ".png" +http_gif ".gif" +http_jpg ".jpg" +http_text ".txt" +http_txt ".txt" + diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/http-strings.c b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/http-strings.c new file mode 100644 index 000000000..ef7a41c7d --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/http-strings.c @@ -0,0 +1,102 @@ +const char http_http[8] = +/* "http://" */ +{0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, }; +const char http_200[5] = +/* "200 " */ +{0x32, 0x30, 0x30, 0x20, }; +const char http_301[5] = +/* "301 " */ +{0x33, 0x30, 0x31, 0x20, }; +const char http_302[5] = +/* "302 " */ +{0x33, 0x30, 0x32, 0x20, }; +const char http_get[5] = +/* "GET " */ +{0x47, 0x45, 0x54, 0x20, }; +const char http_10[9] = +/* "HTTP/1.0" */ +{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, }; +const char http_11[9] = +/* "HTTP/1.1" */ +{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x31, }; +const char http_content_type[15] = +/* "content-type: " */ +{0x63, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, }; +const char http_texthtml[10] = +/* "text/html" */ +{0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_location[11] = +/* "location: " */ +{0x6c, 0x6f, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, }; +const char http_host[7] = +/* "host: " */ +{0x68, 0x6f, 0x73, 0x74, 0x3a, 0x20, }; +const char http_crnl[3] = +/* "\r\n" */ +{0xd, 0xa, }; +const char http_index_html[12] = +/* "/index.html" */ +{0x2f, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_404_html[10] = +/* "/404.html" */ +{0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_referer[9] = +/* "Referer:" */ +{0x52, 0x65, 0x66, 0x65, 0x72, 0x65, 0x72, 0x3a, }; +const char http_header_200[84] = +/* "HTTP/1.0 200 OK\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */ +{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x32, 0x30, 0x30, 0x20, 0x4f, 0x4b, 0xd, 0xa, 0x53, 0x65, 0x72, 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x73, 0x69, 0x63, 0x73, 0x2e, 0x73, 0x65, 0x2f, 0x7e, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, 0x70, 0x2f, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0xd, 0xa, }; +const char http_header_404[91] = +/* "HTTP/1.0 404 Not found\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */ +{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x34, 0x30, 0x34, 0x20, 0x4e, 0x6f, 0x74, 0x20, 0x66, 0x6f, 0x75, 0x6e, 0x64, 0xd, 0xa, 0x53, 0x65, 0x72, 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x73, 0x69, 0x63, 0x73, 0x2e, 0x73, 0x65, 0x2f, 0x7e, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, 0x70, 0x2f, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0xd, 0xa, }; +const char http_content_type_plain[29] = +/* "Content-type: text/plain\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x70, 0x6c, 0x61, 0x69, 0x6e, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_html[28] = +/* "Content-type: text/html\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_css [27] = +/* "Content-type: text/css\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x63, 0x73, 0x73, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_text[28] = +/* "Content-type: text/text\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x74, 0x65, 0x78, 0x74, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_png [28] = +/* "Content-type: image/png\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x70, 0x6e, 0x67, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_gif [28] = +/* "Content-type: image/gif\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x67, 0x69, 0x66, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_jpg [29] = +/* "Content-type: image/jpeg\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x6a, 0x70, 0x65, 0x67, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_binary[43] = +/* "Content-type: application/octet-stream\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x61, 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x2f, 0x6f, 0x63, 0x74, 0x65, 0x74, 0x2d, 0x73, 0x74, 0x72, 0x65, 0x61, 0x6d, 0xd, 0xa, 0xd, 0xa, }; +const char http_html[6] = +/* ".html" */ +{0x2e, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_shtml[7] = +/* ".shtml" */ +{0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_htm[5] = +/* ".htm" */ +{0x2e, 0x68, 0x74, 0x6d, }; +const char http_css[5] = +/* ".css" */ +{0x2e, 0x63, 0x73, 0x73, }; +const char http_png[5] = +/* ".png" */ +{0x2e, 0x70, 0x6e, 0x67, }; +const char http_gif[5] = +/* ".gif" */ +{0x2e, 0x67, 0x69, 0x66, }; +const char http_jpg[5] = +/* ".jpg" */ +{0x2e, 0x6a, 0x70, 0x67, }; +const char http_text[5] = +/* ".txt" */ +{0x2e, 0x74, 0x78, 0x74, }; +const char http_txt[5] = +/* ".txt" */ +{0x2e, 0x74, 0x78, 0x74, }; diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/http-strings.h b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/http-strings.h new file mode 100644 index 000000000..acbe7e17f --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/http-strings.h @@ -0,0 +1,34 @@ +extern const char http_http[8]; +extern const char http_200[5]; +extern const char http_301[5]; +extern const char http_302[5]; +extern const char http_get[5]; +extern const char http_10[9]; +extern const char http_11[9]; +extern const char http_content_type[15]; +extern const char http_texthtml[10]; +extern const char http_location[11]; +extern const char http_host[7]; +extern const char http_crnl[3]; +extern const char http_index_html[12]; +extern const char http_404_html[10]; +extern const char http_referer[9]; +extern const char http_header_200[84]; +extern const char http_header_404[91]; +extern const char http_content_type_plain[29]; +extern const char http_content_type_html[28]; +extern const char http_content_type_css [27]; +extern const char http_content_type_text[28]; +extern const char http_content_type_png [28]; +extern const char http_content_type_gif [28]; +extern const char http_content_type_jpg [29]; +extern const char http_content_type_binary[43]; +extern const char http_html[6]; +extern const char http_shtml[7]; +extern const char http_htm[5]; +extern const char http_css[5]; +extern const char http_png[5]; +extern const char http_gif[5]; +extern const char http_jpg[5]; +extern const char http_text[5]; +extern const char http_txt[5]; diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-cgi.c b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-cgi.c new file mode 100644 index 000000000..803b771e6 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-cgi.c @@ -0,0 +1,269 @@ +/** + * \addtogroup httpd + * @{ + */ + +/** + * \file + * Web server script interface + * \author + * Adam Dunkels + * + */ + +/* + * Copyright (c) 2001-2006, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: httpd-cgi.c,v 1.2 2006/06/11 21:46:37 adam Exp $ + * + */ + +#include "uip.h" +#include "psock.h" +#include "httpd.h" +#include "httpd-cgi.h" +#include "httpd-fs.h" + +#include +#include + +HTTPD_CGI_CALL(file, "file-stats", file_stats); +HTTPD_CGI_CALL(tcp, "tcp-connections", tcp_stats); +HTTPD_CGI_CALL(net, "net-stats", net_stats); +HTTPD_CGI_CALL(rtos, "rtos-stats", rtos_stats ); +HTTPD_CGI_CALL(io, "led-io", led_io ); + + +static const struct httpd_cgi_call *calls[] = { &file, &tcp, &net, &rtos, &io, NULL }; + +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(nullfunction(struct httpd_state *s, char *ptr)) +{ + PSOCK_BEGIN(&s->sout); + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +httpd_cgifunction +httpd_cgi(char *name) +{ + const struct httpd_cgi_call **f; + + /* Find the matching name in the table, return the function. */ + for(f = calls; *f != NULL; ++f) { + if(strncmp((*f)->name, name, strlen((*f)->name)) == 0) { + return (*f)->function; + } + } + return nullfunction; +} +/*---------------------------------------------------------------------------*/ +static unsigned short +generate_file_stats(void *arg) +{ + char *f = (char *)arg; + return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, "%5u", httpd_fs_count(f)); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(file_stats(struct httpd_state *s, char *ptr)) +{ + PSOCK_BEGIN(&s->sout); + + PSOCK_GENERATOR_SEND(&s->sout, generate_file_stats, strchr(ptr, ' ') + 1); + + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +static const char closed[] = /* "CLOSED",*/ +{0x43, 0x4c, 0x4f, 0x53, 0x45, 0x44, 0}; +static const char syn_rcvd[] = /* "SYN-RCVD",*/ +{0x53, 0x59, 0x4e, 0x2d, 0x52, 0x43, 0x56, + 0x44, 0}; +static const char syn_sent[] = /* "SYN-SENT",*/ +{0x53, 0x59, 0x4e, 0x2d, 0x53, 0x45, 0x4e, + 0x54, 0}; +static const char established[] = /* "ESTABLISHED",*/ +{0x45, 0x53, 0x54, 0x41, 0x42, 0x4c, 0x49, 0x53, 0x48, + 0x45, 0x44, 0}; +static const char fin_wait_1[] = /* "FIN-WAIT-1",*/ +{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49, + 0x54, 0x2d, 0x31, 0}; +static const char fin_wait_2[] = /* "FIN-WAIT-2",*/ +{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49, + 0x54, 0x2d, 0x32, 0}; +static const char closing[] = /* "CLOSING",*/ +{0x43, 0x4c, 0x4f, 0x53, 0x49, + 0x4e, 0x47, 0}; +static const char time_wait[] = /* "TIME-WAIT,"*/ +{0x54, 0x49, 0x4d, 0x45, 0x2d, 0x57, 0x41, + 0x49, 0x54, 0}; +static const char last_ack[] = /* "LAST-ACK"*/ +{0x4c, 0x41, 0x53, 0x54, 0x2d, 0x41, 0x43, + 0x4b, 0}; + +static const char *states[] = { + closed, + syn_rcvd, + syn_sent, + established, + fin_wait_1, + fin_wait_2, + closing, + time_wait, + last_ack}; + + +static unsigned short +generate_tcp_stats(void *arg) +{ + struct uip_conn *conn; + struct httpd_state *s = (struct httpd_state *)arg; + + conn = &uip_conns[s->count]; + return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, + "
\r\n", + htons(conn->lport), + htons(conn->ripaddr[0]) >> 8, + htons(conn->ripaddr[0]) & 0xff, + htons(conn->ripaddr[1]) >> 8, + htons(conn->ripaddr[1]) & 0xff, + htons(conn->rport), + states[conn->tcpstateflags & UIP_TS_MASK], + conn->nrtx, + conn->timer, + (uip_outstanding(conn))? '*':' ', + (uip_stopped(conn))? '!':' '); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(tcp_stats(struct httpd_state *s, char *ptr)) +{ + + PSOCK_BEGIN(&s->sout); + + for(s->count = 0; s->count < UIP_CONNS; ++s->count) { + if((uip_conns[s->count].tcpstateflags & UIP_TS_MASK) != UIP_CLOSED) { + PSOCK_GENERATOR_SEND(&s->sout, generate_tcp_stats, s); + } + } + + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +static unsigned short +generate_net_stats(void *arg) +{ + struct httpd_state *s = (struct httpd_state *)arg; + return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, + "%5u\n", ((uip_stats_t *)&uip_stat)[s->count]); +} + +static +PT_THREAD(net_stats(struct httpd_state *s, char *ptr)) +{ + PSOCK_BEGIN(&s->sout); + +#if UIP_STATISTICS + + for(s->count = 0; s->count < sizeof(uip_stat) / sizeof(uip_stats_t); + ++s->count) { + PSOCK_GENERATOR_SEND(&s->sout, generate_net_stats, s); + } + +#endif /* UIP_STATISTICS */ + + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ + +extern void vTaskList( signed char *pcWriteBuffer ); +static char cCountBuf[ 32 ]; +long lRefreshCount = 0; +static unsigned short +generate_rtos_stats(void *arg) +{ + lRefreshCount++; + sprintf( cCountBuf, "


Refresh count = %d", lRefreshCount ); + vTaskList( uip_appdata ); + strcat( uip_appdata, cCountBuf ); + + return strlen( uip_appdata ); +} +/*---------------------------------------------------------------------------*/ + + +static +PT_THREAD(rtos_stats(struct httpd_state *s, char *ptr)) +{ + PSOCK_BEGIN(&s->sout); + PSOCK_GENERATOR_SEND(&s->sout, generate_rtos_stats, NULL); + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ + +char *pcStatus; +extern unsigned long uxParTestGetLED( unsigned long uxLED ); + +static unsigned short generate_io_state( void *arg ) +{ + if( uxParTestGetLED( 0 ) ) + { + pcStatus = "checked"; + } + else + { + pcStatus = ""; + } + + sprintf( uip_appdata, + "LED"\ + "

"\ + "", + pcStatus ); + + return strlen( uip_appdata ); +} +/*---------------------------------------------------------------------------*/ + +static PT_THREAD(led_io(struct httpd_state *s, char *ptr)) +{ + PSOCK_BEGIN(&s->sout); + PSOCK_GENERATOR_SEND(&s->sout, generate_io_state, NULL); + PSOCK_END(&s->sout); +} + +/** @} */ + + + + + + diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-cgi.h b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-cgi.h new file mode 100644 index 000000000..7ae928321 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-cgi.h @@ -0,0 +1,84 @@ +/** + * \addtogroup httpd + * @{ + */ + +/** + * \file + * Web server script interface header file + * \author + * Adam Dunkels + * + */ + + + +/* + * Copyright (c) 2001, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: httpd-cgi.h,v 1.2 2006/06/11 21:46:38 adam Exp $ + * + */ + +#ifndef __HTTPD_CGI_H__ +#define __HTTPD_CGI_H__ + +#include "psock.h" +#include "httpd.h" + +typedef PT_THREAD((* httpd_cgifunction)(struct httpd_state *, char *)); + +httpd_cgifunction httpd_cgi(char *name); + +struct httpd_cgi_call { + const char *name; + const httpd_cgifunction function; +}; + +/** + * \brief HTTPD CGI function declaration + * \param name The C variable name of the function + * \param str The string name of the function, used in the script file + * \param function A pointer to the function that implements it + * + * This macro is used for declaring a HTTPD CGI + * function. This function is then added to the list of + * HTTPD CGI functions with the httpd_cgi_add() function. + * + * \hideinitializer + */ +#define HTTPD_CGI_CALL(name, str, function) \ +static PT_THREAD(function(struct httpd_state *, char *)); \ +static const struct httpd_cgi_call name = {str, function} + +void httpd_cgi_init(void); +#endif /* __HTTPD_CGI_H__ */ + +/** @} */ diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs.c b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs.c new file mode 100644 index 000000000..dc4aef011 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs.c @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: httpd-fs.c,v 1.1 2006/06/07 09:13:08 adam Exp $ + */ + +#include "httpd.h" +#include "httpd-fs.h" +#include "httpd-fsdata.h" + +#ifndef NULL +#define NULL 0 +#endif /* NULL */ + +#include "httpd-fsdata.c" + +#if HTTPD_FS_STATISTICS +static u16_t count[HTTPD_FS_NUMFILES]; +#endif /* HTTPD_FS_STATISTICS */ + +/*-----------------------------------------------------------------------------------*/ +static u8_t +httpd_fs_strcmp(const char *str1, const char *str2) +{ + u8_t i; + i = 0; + loop: + + if(str2[i] == 0 || + str1[i] == '\r' || + str1[i] == '\n') { + return 0; + } + + if(str1[i] != str2[i]) { + return 1; + } + + + ++i; + goto loop; +} +/*-----------------------------------------------------------------------------------*/ +int +httpd_fs_open(const char *name, struct httpd_fs_file *file) +{ +#if HTTPD_FS_STATISTICS + u16_t i = 0; +#endif /* HTTPD_FS_STATISTICS */ + struct httpd_fsdata_file_noconst *f; + + for(f = (struct httpd_fsdata_file_noconst *)HTTPD_FS_ROOT; + f != NULL; + f = (struct httpd_fsdata_file_noconst *)f->next) { + + if(httpd_fs_strcmp(name, f->name) == 0) { + file->data = f->data; + file->len = f->len; +#if HTTPD_FS_STATISTICS + ++count[i]; +#endif /* HTTPD_FS_STATISTICS */ + return 1; + } +#if HTTPD_FS_STATISTICS + ++i; +#endif /* HTTPD_FS_STATISTICS */ + + } + return 0; +} +/*-----------------------------------------------------------------------------------*/ +void +httpd_fs_init(void) +{ +#if HTTPD_FS_STATISTICS + u16_t i; + for(i = 0; i < HTTPD_FS_NUMFILES; i++) { + count[i] = 0; + } +#endif /* HTTPD_FS_STATISTICS */ +} +/*-----------------------------------------------------------------------------------*/ +#if HTTPD_FS_STATISTICS +u16_t httpd_fs_count +(char *name) +{ + struct httpd_fsdata_file_noconst *f; + u16_t i; + + i = 0; + for(f = (struct httpd_fsdata_file_noconst *)HTTPD_FS_ROOT; + f != NULL; + f = (struct httpd_fsdata_file_noconst *)f->next) { + + if(httpd_fs_strcmp(name, f->name) == 0) { + return count[i]; + } + ++i; + } + return 0; +} +#endif /* HTTPD_FS_STATISTICS */ +/*-----------------------------------------------------------------------------------*/ diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs.h b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs.h new file mode 100644 index 000000000..b594eea56 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: httpd-fs.h,v 1.1 2006/06/07 09:13:08 adam Exp $ + */ +#ifndef __HTTPD_FS_H__ +#define __HTTPD_FS_H__ + +#define HTTPD_FS_STATISTICS 1 + +struct httpd_fs_file { + char *data; + int len; +}; + +/* file must be allocated by caller and will be filled in + by the function. */ +int httpd_fs_open(const char *name, struct httpd_fs_file *file); + +#ifdef HTTPD_FS_STATISTICS +#if HTTPD_FS_STATISTICS == 1 +u16_t httpd_fs_count(char *name); +#endif /* HTTPD_FS_STATISTICS */ +#endif /* HTTPD_FS_STATISTICS */ + +void httpd_fs_init(void); + +#endif /* __HTTPD_FS_H__ */ diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs/404.html b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs/404.html new file mode 100644 index 000000000..43e7f4cad --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs/404.html @@ -0,0 +1,8 @@ + + +

+

404 - file not found

+

Go here instead.

+
+ + \ No newline at end of file diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs/index.html b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs/index.html new file mode 100644 index 000000000..1d3bbeee1 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs/index.html @@ -0,0 +1,13 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +Loading index.shtml. Click here if not automatically redirected. + + + + + diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs/index.shtml b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs/index.shtml new file mode 100644 index 000000000..1923ea762 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs/index.shtml @@ -0,0 +1,20 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +RTOS Stats | TCP Stats | Connections | FreeRTOS.org Homepage | IO +

+

+

+

Task statistics

+Page will refresh every 2 seconds.

+

Task          State  Priority  Stack	#
************************************************

+%! rtos-stats
+
+ + + + diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs/io.shtml b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs/io.shtml new file mode 100644 index 000000000..07554bb71 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs/io.shtml @@ -0,0 +1,28 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +RTOS Stats | TCP Stats | Connections | FreeRTOS.org Homepage | IO +

+

+LED and LCD IO
+ +

+ +Use the check box to turn on or off the LED, enter text to display on the OLED display, then click "Update IO". + + +

+
+%! led-io +

+ + +

+ + + + diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs/stats.shtml b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs/stats.shtml new file mode 100644 index 000000000..d762f40d8 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs/stats.shtml @@ -0,0 +1,41 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +RTOS Stats | TCP Stats | Connections | FreeRTOS.org Homepage | IO +

+

+

+

Network statistics

+
LocalRemoteStateRetransmissionsTimerFlags
%d%u.%u.%u.%u:%u%s%u%u%c %c
+
+IP           Packets dropped
+             Packets received
+             Packets sent
+IP errors    IP version/header length
+             IP length, high byte
+             IP length, low byte
+             IP fragments
+             Header checksum
+             Wrong protocol
+ICMP	     Packets dropped
+             Packets received
+             Packets sent
+             Type errors
+TCP          Packets dropped
+             Packets received
+             Packets sent
+             Checksum errors
+             Data packets without ACKs
+             Resets
+             Retransmissions
+	     No connection avaliable
+	     Connection attempts to closed ports
+
%! net-stats
+
+ + + diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs/tcp.shtml b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs/tcp.shtml new file mode 100644 index 000000000..654d61f21 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fs/tcp.shtml @@ -0,0 +1,21 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +RTOS Stats | TCP Stats | Connections | FreeRTOS.org Homepage | IO +

+

+
+

Network connections

+

+ + +%! tcp-connections + + + + + diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fsdata.c b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fsdata.c new file mode 100644 index 000000000..a7fcfab5a --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fsdata.c @@ -0,0 +1,470 @@ +static const unsigned char data_404_html[] = { + /* /404.html */ + 0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0, + 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xd, 0xa, 0x20, 0x20, + 0x3c, 0x62, 0x6f, 0x64, 0x79, 0x20, 0x62, 0x67, 0x63, 0x6f, + 0x6c, 0x6f, 0x72, 0x3d, 0x22, 0x77, 0x68, 0x69, 0x74, 0x65, + 0x22, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x3c, 0x63, + 0x65, 0x6e, 0x74, 0x65, 0x72, 0x3e, 0xd, 0xa, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x3c, 0x68, 0x31, 0x3e, 0x34, 0x30, + 0x34, 0x20, 0x2d, 0x20, 0x66, 0x69, 0x6c, 0x65, 0x20, 0x6e, + 0x6f, 0x74, 0x20, 0x66, 0x6f, 0x75, 0x6e, 0x64, 0x3c, 0x2f, + 0x68, 0x31, 0x3e, 0xd, 0xa, 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0x3e, 0x3c, 0x74, + 0x68, 0x3e, 0x46, 0x6c, 0x61, 0x67, 0x73, 0x3c, 0x2f, 0x74, + 0x68, 0x3e, 0x3c, 0x2f, 0x74, 0x72, 0x3e, 0xd, 0xa, 0x25, + 0x21, 0x20, 0x74, 0x63, 0x70, 0x2d, 0x63, 0x6f, 0x6e, 0x6e, + 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x73, 0xd, 0xa, 0x3c, + 0x2f, 0x70, 0x72, 0x65, 0x3e, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, + 0x74, 0x3e, 0xd, 0xa, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, 0x74, + 0x3e, 0xd, 0xa, 0x3c, 0x2f, 0x62, 0x6f, 0x64, 0x79, 0x3e, + 0xd, 0xa, 0x3c, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xd, + 0xa, 0xd, 0xa, 0}; + +const struct httpd_fsdata_file file_404_html[] = {{NULL, data_404_html, data_404_html + 10, sizeof(data_404_html) - 10}}; + +const struct httpd_fsdata_file file_index_html[] = {{file_404_html, data_index_html, data_index_html + 12, sizeof(data_index_html) - 12}}; + +const struct httpd_fsdata_file file_index_shtml[] = {{file_index_html, data_index_shtml, data_index_shtml + 13, sizeof(data_index_shtml) - 13}}; + +const struct httpd_fsdata_file file_io_shtml[] = {{file_index_shtml, data_io_shtml, data_io_shtml + 10, sizeof(data_io_shtml) - 10}}; + +const struct httpd_fsdata_file file_stats_shtml[] = {{file_io_shtml, data_stats_shtml, data_stats_shtml + 13, sizeof(data_stats_shtml) - 13}}; + +const struct httpd_fsdata_file file_tcp_shtml[] = {{file_stats_shtml, data_tcp_shtml, data_tcp_shtml + 11, sizeof(data_tcp_shtml) - 11}}; + +#define HTTPD_FS_ROOT file_tcp_shtml + +#define HTTPD_FS_NUMFILES 6 diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fsdata.h b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fsdata.h new file mode 100644 index 000000000..52d35c265 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd-fsdata.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: httpd-fsdata.h,v 1.1 2006/06/07 09:13:08 adam Exp $ + */ +#ifndef __HTTPD_FSDATA_H__ +#define __HTTPD_FSDATA_H__ + +#include "uip.h" + +struct httpd_fsdata_file { + const struct httpd_fsdata_file *next; + const char *name; + const char *data; + const int len; +#ifdef HTTPD_FS_STATISTICS +#if HTTPD_FS_STATISTICS == 1 + u16_t count; +#endif /* HTTPD_FS_STATISTICS */ +#endif /* HTTPD_FS_STATISTICS */ +}; + +struct httpd_fsdata_file_noconst { + struct httpd_fsdata_file *next; + char *name; + char *data; + int len; +#ifdef HTTPD_FS_STATISTICS +#if HTTPD_FS_STATISTICS == 1 + u16_t count; +#endif /* HTTPD_FS_STATISTICS */ +#endif /* HTTPD_FS_STATISTICS */ +}; + +#endif /* __HTTPD_FSDATA_H__ */ diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd.c b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd.c new file mode 100644 index 000000000..644cf16b7 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd.c @@ -0,0 +1,346 @@ +/** + * \addtogroup apps + * @{ + */ + +/** + * \defgroup httpd Web server + * @{ + * The uIP web server is a very simplistic implementation of an HTTP + * server. It can serve web pages and files from a read-only ROM + * filesystem, and provides a very small scripting language. + + */ + +/** + * \file + * Web server + * \author + * Adam Dunkels + */ + + +/* + * Copyright (c) 2004, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: httpd.c,v 1.2 2006/06/11 21:46:38 adam Exp $ + */ + +#include "uip.h" +#include "httpd.h" +#include "httpd-fs.h" +#include "httpd-cgi.h" +#include "http-strings.h" + +#include + +#define STATE_WAITING 0 +#define STATE_OUTPUT 1 + +#define ISO_nl 0x0a +#define ISO_space 0x20 +#define ISO_bang 0x21 +#define ISO_percent 0x25 +#define ISO_period 0x2e +#define ISO_slash 0x2f +#define ISO_colon 0x3a + + +/*---------------------------------------------------------------------------*/ +static unsigned short +generate_part_of_file(void *state) +{ + struct httpd_state *s = (struct httpd_state *)state; + + if(s->file.len > uip_mss()) { + s->len = uip_mss(); + } else { + s->len = s->file.len; + } + memcpy(uip_appdata, s->file.data, s->len); + + return s->len; +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(send_file(struct httpd_state *s)) +{ + PSOCK_BEGIN(&s->sout); + + do { + PSOCK_GENERATOR_SEND(&s->sout, generate_part_of_file, s); + s->file.len -= s->len; + s->file.data += s->len; + } while(s->file.len > 0); + + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(send_part_of_file(struct httpd_state *s)) +{ + PSOCK_BEGIN(&s->sout); + + PSOCK_SEND(&s->sout, s->file.data, s->len); + + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +static void +next_scriptstate(struct httpd_state *s) +{ + char *p; + p = strchr(s->scriptptr, ISO_nl) + 1; + s->scriptlen -= (unsigned short)(p - s->scriptptr); + s->scriptptr = p; +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(handle_script(struct httpd_state *s)) +{ + char *ptr; + + PT_BEGIN(&s->scriptpt); + + + while(s->file.len > 0) { + + /* Check if we should start executing a script. */ + if(*s->file.data == ISO_percent && + *(s->file.data + 1) == ISO_bang) { + s->scriptptr = s->file.data + 3; + s->scriptlen = s->file.len - 3; + if(*(s->scriptptr - 1) == ISO_colon) { + httpd_fs_open(s->scriptptr + 1, &s->file); + PT_WAIT_THREAD(&s->scriptpt, send_file(s)); + } else { + PT_WAIT_THREAD(&s->scriptpt, + httpd_cgi(s->scriptptr)(s, s->scriptptr)); + } + next_scriptstate(s); + + /* The script is over, so we reset the pointers and continue + sending the rest of the file. */ + s->file.data = s->scriptptr; + s->file.len = s->scriptlen; + } else { + /* See if we find the start of script marker in the block of HTML + to be sent. */ + + if(s->file.len > uip_mss()) { + s->len = uip_mss(); + } else { + s->len = s->file.len; + } + + if(*s->file.data == ISO_percent) { + ptr = strchr(s->file.data + 1, ISO_percent); + } else { + ptr = strchr(s->file.data, ISO_percent); + } + if(ptr != NULL && + ptr != s->file.data) { + s->len = (int)(ptr - s->file.data); + if(s->len >= uip_mss()) { + s->len = uip_mss(); + } + } + PT_WAIT_THREAD(&s->scriptpt, send_part_of_file(s)); + s->file.data += s->len; + s->file.len -= s->len; + + } + } + + PT_END(&s->scriptpt); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(send_headers(struct httpd_state *s, const char *statushdr)) +{ + char *ptr; + + PSOCK_BEGIN(&s->sout); + + PSOCK_SEND_STR(&s->sout, statushdr); + + ptr = strrchr(s->filename, ISO_period); + if(ptr == NULL) { + PSOCK_SEND_STR(&s->sout, http_content_type_binary); + } else if(strncmp(http_html, ptr, 5) == 0 || + strncmp(http_shtml, ptr, 6) == 0) { + PSOCK_SEND_STR(&s->sout, http_content_type_html); + } else if(strncmp(http_css, ptr, 4) == 0) { + PSOCK_SEND_STR(&s->sout, http_content_type_css); + } else if(strncmp(http_png, ptr, 4) == 0) { + PSOCK_SEND_STR(&s->sout, http_content_type_png); + } else if(strncmp(http_gif, ptr, 4) == 0) { + PSOCK_SEND_STR(&s->sout, http_content_type_gif); + } else if(strncmp(http_jpg, ptr, 4) == 0) { + PSOCK_SEND_STR(&s->sout, http_content_type_jpg); + } else { + PSOCK_SEND_STR(&s->sout, http_content_type_plain); + } + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(handle_output(struct httpd_state *s)) +{ + char *ptr; + + PT_BEGIN(&s->outputpt); + + if(!httpd_fs_open(s->filename, &s->file)) { + httpd_fs_open(http_404_html, &s->file); + strcpy(s->filename, http_404_html); + PT_WAIT_THREAD(&s->outputpt, + send_headers(s, + http_header_404)); + PT_WAIT_THREAD(&s->outputpt, + send_file(s)); + } else { + PT_WAIT_THREAD(&s->outputpt, + send_headers(s, + http_header_200)); + ptr = strchr(s->filename, ISO_period); + if(ptr != NULL && strncmp(ptr, http_shtml, 6) == 0) { + PT_INIT(&s->scriptpt); + PT_WAIT_THREAD(&s->outputpt, handle_script(s)); + } else { + PT_WAIT_THREAD(&s->outputpt, + send_file(s)); + } + } + PSOCK_CLOSE(&s->sout); + PT_END(&s->outputpt); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(handle_input(struct httpd_state *s)) +{ + PSOCK_BEGIN(&s->sin); + + PSOCK_READTO(&s->sin, ISO_space); + + + if(strncmp(s->inputbuf, http_get, 4) != 0) { + PSOCK_CLOSE_EXIT(&s->sin); + } + PSOCK_READTO(&s->sin, ISO_space); + + if(s->inputbuf[0] != ISO_slash) { + PSOCK_CLOSE_EXIT(&s->sin); + } + + if(s->inputbuf[1] == ISO_space) { + strncpy(s->filename, http_index_html, sizeof(s->filename)); + } else { + + s->inputbuf[PSOCK_DATALEN(&s->sin) - 1] = 0; + + /* Process any form input being sent to the server. */ + { + extern void vApplicationProcessFormInput( char *pcInputString, long xInputLength ); + vApplicationProcessFormInput( s->inputbuf, PSOCK_DATALEN(&s->sin) ); + } + + strncpy(s->filename, &s->inputbuf[0], sizeof(s->filename)); + } + + /* httpd_log_file(uip_conn->ripaddr, s->filename);*/ + + s->state = STATE_OUTPUT; + + while(1) { + PSOCK_READTO(&s->sin, ISO_nl); + + if(strncmp(s->inputbuf, http_referer, 8) == 0) { + s->inputbuf[PSOCK_DATALEN(&s->sin) - 2] = 0; + /* httpd_log(&s->inputbuf[9]);*/ + } + } + + PSOCK_END(&s->sin); +} +/*---------------------------------------------------------------------------*/ +static void +handle_connection(struct httpd_state *s) +{ + handle_input(s); + if(s->state == STATE_OUTPUT) { + handle_output(s); + } +} +/*---------------------------------------------------------------------------*/ +void +httpd_appcall(void) +{ + struct httpd_state *s = (struct httpd_state *)&(uip_conn->appstate); + + if(uip_closed() || uip_aborted() || uip_timedout()) { + } else if(uip_connected()) { + PSOCK_INIT(&s->sin, s->inputbuf, sizeof(s->inputbuf) - 1); + PSOCK_INIT(&s->sout, s->inputbuf, sizeof(s->inputbuf) - 1); + PT_INIT(&s->outputpt); + s->state = STATE_WAITING; + /* timer_set(&s->timer, CLOCK_SECOND * 100);*/ + s->timer = 0; + handle_connection(s); + } else if(s != NULL) { + if(uip_poll()) { + ++s->timer; + if(s->timer >= 20) { + uip_abort(); + } + } else { + s->timer = 0; + } + handle_connection(s); + } else { + uip_abort(); + } +} +/*---------------------------------------------------------------------------*/ +/** + * \brief Initialize the web server + * + * This function initializes the web server and should be + * called at system boot-up. + */ +void +httpd_init(void) +{ + uip_listen(HTONS(80)); +} +/*---------------------------------------------------------------------------*/ +/** @} */ diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd.h b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd.h new file mode 100644 index 000000000..7f7a6666e --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/httpd.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2001-2005, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: httpd.h,v 1.2 2006/06/11 21:46:38 adam Exp $ + * + */ + +#ifndef __HTTPD_H__ +#define __HTTPD_H__ + +#include "psock.h" +#include "httpd-fs.h" + +struct httpd_state { + unsigned char timer; + struct psock sin, sout; + struct pt outputpt, scriptpt; + char inputbuf[50]; + char filename[20]; + char state; + struct httpd_fs_file file; + int len; + char *scriptptr; + int scriptlen; + + unsigned short count; +}; + +void httpd_init(void); +void httpd_appcall(void); + +void httpd_log(char *msg); +void httpd_log_file(u16_t *requester, char *file); + +#endif /* __HTTPD_H__ */ diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/makefsdata b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/makefsdata new file mode 100644 index 000000000..8d2715a8a --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/makefsdata @@ -0,0 +1,78 @@ +#!/usr/bin/perl + +open(OUTPUT, "> httpd-fsdata.c"); + +chdir("httpd-fs"); + +opendir(DIR, "."); +@files = grep { !/^\./ && !/(CVS|~)/ } readdir(DIR); +closedir(DIR); + +foreach $file (@files) { + + if(-d $file && $file !~ /^\./) { + print "Processing directory $file\n"; + opendir(DIR, $file); + @newfiles = grep { !/^\./ && !/(CVS|~)/ } readdir(DIR); + closedir(DIR); + printf "Adding files @newfiles\n"; + @files = (@files, map { $_ = "$file/$_" } @newfiles); + next; + } +} + +foreach $file (@files) { + if(-f $file) { + + print "Adding file $file\n"; + + open(FILE, $file) || die "Could not open file $file\n"; + + $file =~ s-^-/-; + $fvar = $file; + $fvar =~ s-/-_-g; + $fvar =~ s-\.-_-g; + # for AVR, add PROGMEM here + print(OUTPUT "static const unsigned char data".$fvar."[] = {\n"); + print(OUTPUT "\t/* $file */\n\t"); + for($j = 0; $j < length($file); $j++) { + printf(OUTPUT "%#02x, ", unpack("C", substr($file, $j, 1))); + } + printf(OUTPUT "0,\n"); + + + $i = 0; + while(read(FILE, $data, 1)) { + if($i == 0) { + print(OUTPUT "\t"); + } + printf(OUTPUT "%#02x, ", unpack("C", $data)); + $i++; + if($i == 10) { + print(OUTPUT "\n"); + $i = 0; + } + } + print(OUTPUT "0};\n\n"); + close(FILE); + push(@fvars, $fvar); + push(@pfiles, $file); + } +} + +for($i = 0; $i < @fvars; $i++) { + $file = $pfiles[$i]; + $fvar = $fvars[$i]; + + if($i == 0) { + $prevfile = "NULL"; + } else { + $prevfile = "file" . $fvars[$i - 1]; + } + print(OUTPUT "const struct httpd_fsdata_file file".$fvar."[] = {{$prevfile, data$fvar, "); + print(OUTPUT "data$fvar + ". (length($file) + 1) .", "); + print(OUTPUT "sizeof(data$fvar) - ". (length($file) + 1) ."}};\n\n"); +} + +print(OUTPUT "#define HTTPD_FS_ROOT file$fvars[$i - 1]\n\n"); +print(OUTPUT "#define HTTPD_FS_NUMFILES $i\n"); diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/makestrings b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/makestrings new file mode 100644 index 000000000..8a13c6d29 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/makestrings @@ -0,0 +1,40 @@ +#!/usr/bin/perl + + +sub stringify { + my $name = shift(@_); + open(OUTPUTC, "> $name.c"); + open(OUTPUTH, "> $name.h"); + + open(FILE, "$name"); + + while() { + if(/(.+) "(.+)"/) { + $var = $1; + $data = $2; + + $datan = $data; + $datan =~ s/\\r/\r/g; + $datan =~ s/\\n/\n/g; + $datan =~ s/\\01/\01/g; + $datan =~ s/\\0/\0/g; + + printf(OUTPUTC "const char $var\[%d] = \n", length($datan) + 1); + printf(OUTPUTC "/* \"$data\" */\n"); + printf(OUTPUTC "{"); + for($j = 0; $j < length($datan); $j++) { + printf(OUTPUTC "%#02x, ", unpack("C", substr($datan, $j, 1))); + } + printf(OUTPUTC "};\n"); + + printf(OUTPUTH "extern const char $var\[%d];\n", length($datan) + 1); + + } + } + close(OUTPUTC); + close(OUTPUTH); +} +stringify("http-strings"); + +exit 0; + diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/uIP_Task.c b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/uIP_Task.c new file mode 100644 index 000000000..3844aee4a --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/uIP_Task.c @@ -0,0 +1,305 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +#include "lcd_message.h" + +/* uip includes. */ +#include "hw_types.h" + +#include "uip.h" +#include "uip_arp.h" +#include "httpd.h" +#include "timer.h" +#include "clock-arch.h" +#include "hw_ethernet.h" +#include "ethernet.h" +#include "hw_memmap.h" +#include "lmi_flash.h" +#include "sysctl.h" + +/* Demo includes. */ +#include "emac.h" +#include "partest.h" + +/*-----------------------------------------------------------*/ + +/* IP address configuration. */ +#define uipIP_ADDR0 172 +#define uipIP_ADDR1 25 +#define uipIP_ADDR2 218 +#define uipIP_ADDR3 19 + +/* How long to wait before attempting to connect the MAC again. */ +#define uipINIT_WAIT 100 + +/* Shortcut to the header within the Rx buffer. */ +#define xHeader ((struct uip_eth_hdr *) &uip_buf[ 0 ]) + +/* Standard constant. */ +#define uipTOTAL_FRAME_HEADER_SIZE 54 + +/*-----------------------------------------------------------*/ + +/* + * Send the uIP buffer to the MAC. + */ +static void prvENET_Send(void); + +/* + * Setup the MAC address in the MAC itself, and in the uIP stack. + */ +static void prvSetMACAddress( void ); + +/* + * Port functions required by the uIP stack. + */ +void clock_init( void ); +clock_time_t clock_time( void ); + +/*-----------------------------------------------------------*/ + +/* The semaphore used by the ISR to wake the uIP task. */ +extern xSemaphoreHandle xEMACSemaphore; + +/*-----------------------------------------------------------*/ + +void clock_init(void) +{ + /* This is done when the scheduler starts. */ +} +/*-----------------------------------------------------------*/ + +clock_time_t clock_time( void ) +{ + return xTaskGetTickCount(); +} + + +void vuIP_Task( void *pvParameters ) +{ +portBASE_TYPE i; +uip_ipaddr_t xIPAddr; +struct timer periodic_timer, arp_timer; +extern void ( vEMAC_ISR )( void ); + + /* Enable/Reset the Ethernet Controller */ + SysCtlPeripheralEnable( SYSCTL_PERIPH_ETH ); + SysCtlPeripheralReset( SYSCTL_PERIPH_ETH ); + + /* Create the semaphore used by the ISR to wake this task. */ + vSemaphoreCreateBinary( xEMACSemaphore ); + + /* Initialise the uIP stack. */ + timer_set( &periodic_timer, configTICK_RATE_HZ / 2 ); + timer_set( &arp_timer, configTICK_RATE_HZ * 10 ); + uip_init(); + uip_ipaddr( xIPAddr, uipIP_ADDR0, uipIP_ADDR1, uipIP_ADDR2, uipIP_ADDR3 ); + uip_sethostaddr( xIPAddr ); + httpd_init(); + + while( vInitEMAC() != pdPASS ) + { + vTaskDelay( uipINIT_WAIT ); + } + prvSetMACAddress(); + + + for( ;; ) + { + /* Is there received data ready to be processed? */ + uip_len = uiGetEMACRxData( uip_buf ); + + if( uip_len > 0 ) + { + /* Standard uIP loop taken from the uIP manual. */ + + if( xHeader->type == htons( UIP_ETHTYPE_IP ) ) + { + uip_arp_ipin(); + uip_input(); + + /* If the above function invocation resulted in data that + should be sent out on the network, the global variable + uip_len is set to a value > 0. */ + if( uip_len > 0 ) + { + uip_arp_out(); + prvENET_Send(); + } + } + else if( xHeader->type == htons( UIP_ETHTYPE_ARP ) ) + { + uip_arp_arpin(); + + /* If the above function invocation resulted in data that + should be sent out on the network, the global variable + uip_len is set to a value > 0. */ + if( uip_len > 0 ) + { + prvENET_Send(); + } + } + } + else + { + if( timer_expired( &periodic_timer ) ) + { + timer_reset( &periodic_timer ); + for( i = 0; i < UIP_CONNS; i++ ) + { + uip_periodic( i ); + + /* If the above function invocation resulted in data that + should be sent out on the network, the global variable + uip_len is set to a value > 0. */ + if( uip_len > 0 ) + { + uip_arp_out(); + prvENET_Send(); + } + } + + /* Call the ARP timer function every 10 seconds. */ + if( timer_expired( &arp_timer ) ) + { + timer_reset( &arp_timer ); + uip_arp_timer(); + } + } + else + { + /* We did not receive a packet, and there was no periodic + processing to perform. Block for a fixed period. If a packet + is received during this period we will be woken by the ISR + giving us the Semaphore. */ + xSemaphoreTake( xEMACSemaphore, configTICK_RATE_HZ / 2 ); + } + } + } +} +/*-----------------------------------------------------------*/ + +static void prvENET_Send(void) +{ + vInitialiseSend(); + vIncrementTxLength( uip_len ); + vSendBufferToMAC(); +} +/*-----------------------------------------------------------*/ + +static void prvSetMACAddress( void ) +{ +unsigned portLONG ulUser0, ulUser1; +unsigned char pucMACArray[8]; +struct uip_eth_addr xAddr; + + /* Get the device MAC address from flash */ + FlashUserGet(&ulUser0, &ulUser1); + + /* Convert the MAC address from flash into sequence of bytes. */ + pucMACArray[0] = ((ulUser0 >> 0) & 0xff); + pucMACArray[1] = ((ulUser0 >> 8) & 0xff); + pucMACArray[2] = ((ulUser0 >> 16) & 0xff); + pucMACArray[3] = ((ulUser1 >> 0) & 0xff); + pucMACArray[4] = ((ulUser1 >> 8) & 0xff); + pucMACArray[5] = ((ulUser1 >> 16) & 0xff); + + /* Program the MAC address. */ + EthernetMACAddrSet(ETH_BASE, pucMACArray); + + xAddr.addr[ 0 ] = pucMACArray[0]; + xAddr.addr[ 1 ] = pucMACArray[1]; + xAddr.addr[ 2 ] = pucMACArray[2]; + xAddr.addr[ 3 ] = pucMACArray[3]; + xAddr.addr[ 4 ] = pucMACArray[4]; + xAddr.addr[ 5 ] = pucMACArray[5]; + uip_setethaddr( xAddr ); +} +/*-----------------------------------------------------------*/ + +void vApplicationProcessFormInput( portCHAR *pcInputString, portBASE_TYPE xInputLength ) +{ +char *c, *pcText; +static portCHAR cMessageForDisplay[ 32 ]; +extern xQueueHandle xOLEDQueue; +xOLEDMessage xOLEDMessage; + + /* Process the form input sent by the IO page of the served HTML. */ + + c = strstr( pcInputString, "?" ); + + if( c ) + { + /* Turn LED's on or off in accordance with the check box status. */ + if( strstr( c, "LED0=1" ) != NULL ) + { + vParTestSetLED( 0, 1 ); + } + else + { + vParTestSetLED( 0, 0 ); + } + + /* Find the start of the text to be displayed on the LCD. */ + pcText = strstr( c, "LCD=" ); + pcText += strlen( "LCD=" ); + + /* Terminate the file name for further processing within uIP. */ + *c = 0x00; + + /* Terminate the LCD string. */ + c = strstr( pcText, " " ); + if( c != NULL ) + { + *c = 0x00; + } + + /* Add required spaces. */ + while( ( c = strstr( pcText, "+" ) ) != NULL ) + { + *c = ' '; + } + + /* Write the message to the LCD. */ + strcpy( cMessageForDisplay, pcText ); + xOLEDMessage.pcMessage = cMessageForDisplay; + xQueueSend( xOLEDQueue, &xOLEDMessage, portMAX_DELAY ); + } +} + diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/uip-conf.h b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/uip-conf.h new file mode 100644 index 000000000..664077d89 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/uip-conf.h @@ -0,0 +1,159 @@ +/** + * \addtogroup uipopt + * @{ + */ + +/** + * \name Project-specific configuration options + * @{ + * + * uIP has a number of configuration options that can be overridden + * for each project. These are kept in a project-specific uip-conf.h + * file and all configuration names have the prefix UIP_CONF. + */ + +/* + * Copyright (c) 2006, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: uip-conf.h,v 1.6 2006/06/12 08:00:31 adam Exp $ + */ + +/** + * \file + * An example uIP configuration file + * \author + * Adam Dunkels + */ + +#ifndef __UIP_CONF_H__ +#define __UIP_CONF_H__ + +#include + +/** + * 8 bit datatype + * + * This typedef defines the 8-bit type used throughout uIP. + * + * \hideinitializer + */ +typedef uint8_t u8_t; + +/** + * 16 bit datatype + * + * This typedef defines the 16-bit type used throughout uIP. + * + * \hideinitializer + */ +typedef uint16_t u16_t; + +/** + * Statistics datatype + * + * This typedef defines the dataype used for keeping statistics in + * uIP. + * + * \hideinitializer + */ +typedef unsigned short uip_stats_t; + +/** + * Maximum number of TCP connections. + * + * \hideinitializer + */ +#define UIP_CONF_MAX_CONNECTIONS 40 + +/** + * Maximum number of listening TCP ports. + * + * \hideinitializer + */ +#define UIP_CONF_MAX_LISTENPORTS 40 + +/** + * uIP buffer size. + * + * \hideinitializer + */ +#define UIP_CONF_BUFFER_SIZE 1500 + +/** + * CPU byte order. + * + * \hideinitializer + */ +#define UIP_CONF_BYTE_ORDER LITTLE_ENDIAN + +/** + * Logging on or off + * + * \hideinitializer + */ +#define UIP_CONF_LOGGING 0 + +/** + * UDP support on or off + * + * \hideinitializer + */ +#define UIP_CONF_UDP 0 + +/** + * UDP checksums on or off + * + * \hideinitializer + */ +#define UIP_CONF_UDP_CHECKSUMS 1 + +/** + * uIP statistics on or off + * + * \hideinitializer + */ +#define UIP_CONF_STATISTICS 1 + +/* Here we include the header file for the application(s) we use in + our project. */ +/*#include "smtp.h"*/ +/*#include "hello-world.h"*/ +/*#include "telnetd.h"*/ +#include "webserver.h" +/*#include "dhcpc.h"*/ +/*#include "resolv.h"*/ +/*#include "webclient.h"*/ + +#define UIP_CONF_EXTERNAL_BUFFER + +#endif /* __UIP_CONF_H__ */ + +/** @} */ +/** @} */ diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/webserver.h b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/webserver.h new file mode 100644 index 000000000..1acb290b8 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/RTOSDemo/webserver/webserver.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2002, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: webserver.h,v 1.2 2006/06/11 21:46:38 adam Exp $ + * + */ +#ifndef __WEBSERVER_H__ +#define __WEBSERVER_H__ + +#include "httpd.h" + +typedef struct httpd_state uip_tcp_appstate_t; +/* UIP_APPCALL: the name of the application function. This function + must return void and take no arguments (i.e., C type "void + appfunc(void)"). */ +#ifndef UIP_APPCALL +#define UIP_APPCALL httpd_appcall +#endif + + +#endif /* __WEBSERVER_H__ */ diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/fury_ft2232.cfg b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/fury_ft2232.cfg new file mode 100644 index 000000000..8f2b3ed1e --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/fury_ft2232.cfg @@ -0,0 +1,28 @@ +#daemon configuration +telnet_port 4444 +gdb_port 3333 + +#interface +interface ft2232 +ft2232_device_desc "Stellaris Evaluation Board A" +ft2232_layout evb_lm3s811 +ft2232_vid_pid 0x0403 0xbcd9 +jtag_speed 40 +#LM3S811 Evaluation Board has only srst +reset_config srst_only separate + +#jtag scan chain +#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) +jtag_device 4 0x1 0xf 0xe + +#target configuration +daemon_startup attach +#target +#target arm7tdmi +target cortex_m3 little run_and_halt 0 +# 4k working area at base of ram +working_area 0 0x20000800 0x1200 nobackup +#target_script 0 reset ../doc/scripts/evb_lm3s811_test.script + +#flash configuration +flash bank stellaris 0 0 0 0 0 diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/fury_ft2232_flash.cfg b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/fury_ft2232_flash.cfg new file mode 100644 index 000000000..28ffaea9e --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/fury_ft2232_flash.cfg @@ -0,0 +1,34 @@ +#daemon configuration +telnet_port 4444 +gdb_port 3333 + +#interface +interface ft2232 +ft2232_device_desc "Stellaris Evaluation Board A" +ft2232_layout evb_lm3s811 +ft2232_vid_pid 0x0403 0xbcd9 +jtag_speed 40 +#LM3S811 Evaluation Board has only srst +reset_config srst_only separate + +#jtag scan chain +#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) +jtag_device 4 0x1 0xf 0xe + +#target configuration +daemon_startup reset +#target +#target arm7tdmi +target cortex_m3 little run_and_init 0 +# 4k working area at base of ram +working_area 0 0x20000800 0x1200 nobackup +#target_script 0 reset ../doc/scripts/evb_lm3s811_test.script + +target_script 0 reset program.script + + +#flash configuration +flash bank stellaris 0 0 0 0 0 + + + diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/program.script b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/program.script new file mode 100644 index 000000000..314624b33 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_Eclipse/program.script @@ -0,0 +1,17 @@ +halt +sleep 200 +wait_halt +flash probe 0 +#sleep 500 +flash info 0 +#sleep 500 +#flash protect 0 0 31 off +#sleep 500 +flash erase 0 0 255 +sleep 200 +flash write 0 ./RTOSDemo/RTOSDemo.bin 0 +sleep 200 +reset run +shutdown + + diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/RTOSDemo.pbd b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/RTOSDemo.pbd new file mode 100644 index 000000000..f8e33063b --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/Debug/Obj/RTOSDemo.pbd @@ -0,0 +1,32 @@ +This is an internal working file generated by the Source Browser. +20:38 47s +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\BlockQ.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\GenQTest.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\ParTest.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\PollQ.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\QPeek.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\blocktim.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\death.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\emac.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\flash.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\heap_2.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\http-strings.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\httpd-cgi.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\httpd-fs.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\httpd.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\integer.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\list.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\main.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\osram128x64x4.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\port.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\psock.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\queue.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\rit128x96x4.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\semtest.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\startup_ewarm.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\tasks.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\timer.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\timertest.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\uIP_Task.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\uip.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\CORTEX_LM3Sxxxx_IAR_Keil\Debug\Obj\uip_arp.pbi diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/FreeRTOSConfig.h b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/FreeRTOSConfig.h new file mode 100644 index 000000000..8b16e4433 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/FreeRTOSConfig.h @@ -0,0 +1,88 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 1 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 50000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 70 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 24000 ) ) +#define configMAX_TASK_NAME_LEN ( 12 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_CO_ROUTINES 0 +#define configUSE_MUTEXES 1 + +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + +#define configKERNEL_INTERRUPT_PRIORITY 255 + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/LM3Sxxxx.icf b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/LM3Sxxxx.icf new file mode 100644 index 000000000..575329d1f --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/LM3Sxxxx.icf @@ -0,0 +1,58 @@ +//***************************************************************************** +// +// enet_lwip.icf - Linker configuration file for enet_lwip. +// +// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved. +// Luminary Micro Confidential - For Use Under NDA Only +// +//***************************************************************************** + +// +// Define a memory region that covers the entire 4 GB addressible space of the +// processor. +// +define memory mem with size = 4G; + +// +// Define a region for the on-chip flash. +// +define region FLASH = mem:[from 0x00000000 to 0x0003ffff]; + +// +// Define a region for the on-chip SRAM. +// +define region SRAM = mem:[from 0x20000000 to 0x2000ffff]; + +// +// Define a block for the heap. The size should be set to something other +// than zero if things in the C library that require the heap are used. +// +define block HEAP with alignment = 8, size = 0x00000000 { }; + +// +// Indicate that the read/write values should be initialized by copying from +// flash. +// +initialize by copy { readwrite }; + +// +// Initicate that the noinit values should be left alone. This includes the +// stack, which if initialized will destroy the return address from the +// initialization code, causing the processor to branch to zero and fault. +// +do not initialize { section .noinit }; + +// +// Place the interrupt vectors at the start of flash. +// +place at start of FLASH { readonly section .intvec }; + +// +// Place the remainder of the read-only items into flash. +// +place in FLASH { readonly }; + +// +// Place all read/write items into SRAM. +// +place in SRAM { readwrite, block HEAP }; diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/ParTest/ParTest.c b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/ParTest/ParTest.c new file mode 100644 index 000000000..d03d019ce --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/ParTest/ParTest.c @@ -0,0 +1,90 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +/* +*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo includes. */ +#include "partest.h" + +/* Library includes. */ +#include "hw_types.h" +#include "gpio.h" +#include "hw_memmap.h" + + +/*-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ + GPIODirModeSet( GPIO_PORTF_BASE, GPIO_PIN_0, GPIO_DIR_MODE_OUT ); + GPIOPadConfigSet( GPIO_PORTF_BASE, GPIO_PIN_0, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD ); + GPIOPinWrite( GPIO_PORTF_BASE, GPIO_PIN_0, 0 ); +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ + /* There is only one LED. */ + ( void ) uxLED; + + GPIOPinWrite( GPIO_PORTF_BASE, GPIO_PIN_0, xValue ); +} +/*-----------------------------------------------------------*/ + +unsigned portBASE_TYPE uxParTestGetLED( unsigned portBASE_TYPE uxLED ) +{ + /* There is only one LED. */ + ( void ) uxLED; + + return GPIOPinRead( GPIO_PORTF_BASE, GPIO_PIN_0 ); +} + + diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.Opt b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.Opt new file mode 100644 index 000000000..0302df76b --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.Opt @@ -0,0 +1,73 @@ +### uVision2 Project, (C) Keil Software +### Do not modify ! + + cExt (*.c) + aExt (*.s*; *.src; *.a*) + oExt (*.obj) + lExt (*.lib) + tExt (*.txt; *.h; *.inc) + pExt (*.plm) + CppX (*.cpp) + DaveTm { 0,0,0,0,0,0,0,0 } + +Target (FreeRTOS_Demo), 0x0004 // Tools: 'ARM-ADS' +GRPOPT 1,(Demo_Source),0,0,0 +GRPOPT 2,(Libraries),0,0,0 +GRPOPT 3,(RTOS_Source),0,0,0 +GRPOPT 4,(uIP_Source),0,0,0 + +OPTFFF 1,1,1,0,0,0,0,0,<..\Common\Minimal\BlockQ.c> +OPTFFF 1,2,1,0,0,0,0,0,<..\Common\Minimal\blocktim.c> +OPTFFF 1,3,1,0,0,0,0,0,<..\Common\Minimal\death.c> +OPTFFF 1,4,1,0,0,0,0,0,<..\Common\Minimal\integer.c> +OPTFFF 1,5,1,2,0,1,1,0,<.\main.c> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,110,0,0,0,115,0,0,0,248,3,0,0,22,2,0,0 } +OPTFFF 1,6,1,0,0,0,0,0,<.\ParTest\ParTest.c> +OPTFFF 1,7,1,0,0,0,0,0,<..\Common\Minimal\PollQ.c> +OPTFFF 1,8,1,0,0,0,0,0,<..\Common\Minimal\semtest.c> +OPTFFF 1,9,2,0,0,0,0,0,<.\startup_rvmdk.S> +OPTFFF 1,10,1,0,0,0,0,0,<.\timertest.c> +OPTFFF 1,11,5,0,0,0,0,0,<.\FreeRTOSConfig.h> +OPTFFF 1,12,1,0,0,0,0,0,<..\Common\Minimal\GenQTest.c> +OPTFFF 1,13,1,0,0,0,0,0,<..\Common\Minimal\QPeek.c> +OPTFFF 2,14,1,0,0,0,0,0,<.\rit128x96x4.c> +OPTFFF 2,15,1,0,0,0,0,0,<.\osram128x64x4.c> +OPTFFF 2,16,4,0,0,0,0,0,<..\Common\drivers\LuminaryMicro\Keil\driverlib.lib> +OPTFFF 3,17,1,0,0,0,0,0,<..\..\Source\tasks.c> +OPTFFF 3,18,1,0,0,0,0,0,<..\..\Source\list.c> +OPTFFF 3,19,1,0,0,0,0,0,<..\..\Source\queue.c> +OPTFFF 3,20,1,0,0,0,0,0,<..\..\Source\portable\RVDS\ARM_CM3\port.c> +OPTFFF 3,21,1,0,0,0,0,0,<..\..\Source\portable\MemMang\heap_2.c> +OPTFFF 4,22,1,822083584,0,0,0,0,<.\webserver\uIP_Task.c> +OPTFFF 4,23,1,218103808,0,0,0,0,<.\webserver\emac.c> +OPTFFF 4,24,1,0,0,0,0,0,<.\webserver\httpd.c> +OPTFFF 4,25,1,0,0,0,0,0,<.\webserver\httpd-cgi.c> +OPTFFF 4,26,1,0,0,0,0,0,<.\webserver\httpd-fs.c> +OPTFFF 4,27,1,0,0,0,0,0,<.\webserver\http-strings.c> +OPTFFF 4,28,1,0,0,0,0,0,<..\Common\ethernet\uIP\uip-1.0\uip\uip_arp.c> +OPTFFF 4,29,1,0,0,0,0,0,<..\Common\ethernet\uIP\uip-1.0\uip\psock.c> +OPTFFF 4,30,1,0,0,0,0,0,<..\Common\ethernet\uIP\uip-1.0\uip\timer.c> +OPTFFF 4,31,1,0,0,0,0,0,<..\Common\ethernet\uIP\uip-1.0\uip\uip.c> + + +TARGOPT 1, (FreeRTOS_Demo) + ADSCLK=8000000 + OPTTT 1,1,1,0 + OPTHX 1,65535,0,0,0 + OPTLX 79,66,8,<.\rvmdk\> + OPTOX 16 + OPTLT 1,1,1,0,1,1,0,1,0,0,0,0 + OPTXL 1,1,1,1,1,1,1,0,0 + OPTFL 1,0,1 + OPTAX 255 + OPTBL 0,(Data Sheet) + OPTDL (SARMCM3.DLL)()(DLM.DLL)(-pLM3S6965)(SARMCM3.DLL)()(TLM.DLL)(-pLM3S6965) + OPTDBG 48126,3,()()()()()()()()()() (BIN\lmidk-agdi.dll)()()() + OPTKEY 0,(DLGTARM)((1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(102=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)(1014=-1,-1,-1,-1,0)(1016=-1,-1,-1,-1,0)) + OPTKEY 0,(ARMDBGFLAGS)() + OPTKEY 0,(lmidk-agdi)(-B0 -O1792) + OPTMM 1,2,(0) + OPTDF 0x84 + OPTLE <> + OPTLC <> +EndOpt + diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.Uv2 b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.Uv2 new file mode 100644 index 000000000..6ea95c4a5 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.Uv2 @@ -0,0 +1,132 @@ +### uVision2 Project, (C) Keil Software +### Do not modify ! + +Target (FreeRTOS_Demo), 0x0004 // Tools: 'ARM-ADS' + +Group (Demo_Source) +Group (Libraries) +Group (RTOS_Source) +Group (uIP_Source) + +File 1,1,<..\Common\Minimal\BlockQ.c> 0x46AC3C5D +File 1,1,<..\Common\Minimal\blocktim.c> 0x46AC3C5D +File 1,1,<..\Common\Minimal\death.c> 0x46ADD531 +File 1,1,<..\Common\Minimal\integer.c> 0x46AC3C5A +File 1,1,<.\main.c> 0x46D709ED +File 1,1,<.\ParTest\ParTest.c> 0x46AC3C69 +File 1,1,<..\Common\Minimal\PollQ.c> 0x46AC3C59 +File 1,1,<..\Common\Minimal\semtest.c> 0x46AC3C59 +File 1,2,<.\startup_rvmdk.S> 0x466462F2 +File 1,1,<.\timertest.c> 0x46D705A3 +File 1,5,<.\FreeRTOSConfig.h> 0x46D70622 +File 1,1,<..\Common\Minimal\GenQTest.c> 0x46CB0603 +File 1,1,<..\Common\Minimal\QPeek.c> 0x46CDED45 +File 2,1,<.\rit128x96x4.c> 0x46D28D06 +File 2,1,<.\osram128x64x4.c> 0x46644906 +File 2,4,<..\Common\drivers\LuminaryMicro\Keil\driverlib.lib> 0x46BC6EE4 +File 3,1,<..\..\Source\tasks.c> 0x46CEC127 +File 3,1,<..\..\Source\list.c> 0x46AC3BCE +File 3,1,<..\..\Source\queue.c> 0x46D2EA0D +File 3,1,<..\..\Source\portable\RVDS\ARM_CM3\port.c> 0x46AC3CA9 +File 3,1,<..\..\Source\portable\MemMang\heap_2.c> 0x46AC3C8D +File 4,1,<.\webserver\uIP_Task.c> 0x46D71230 +File 4,1,<.\webserver\emac.c> 0x46D712B5 +File 4,1,<.\webserver\httpd.c> 0x461135EB +File 4,1,<.\webserver\httpd-cgi.c> 0x46515375 +File 4,1,<.\webserver\httpd-fs.c> 0x4560E5F3 +File 4,1,<.\webserver\http-strings.c> 0x4560E5F3 +File 4,1,<..\Common\ethernet\uIP\uip-1.0\uip\uip_arp.c> 0x46516ADA +File 4,1,<..\Common\ethernet\uIP\uip-1.0\uip\psock.c> 0x4560E5E6 +File 4,1,<..\Common\ethernet\uIP\uip-1.0\uip\timer.c> 0x4560E5E6 +File 4,1,<..\Common\ethernet\uIP\uip-1.0\uip\uip.c> 0x46CEF877 + + +Options 1,0,0 // Target 'FreeRTOS_Demo' + Device (LM3S6965) + Vendor (Luminary Micro) + Cpu (IRAM(0x20000000-0x2000FFFF) IROM(0-0x3FFFF) CLOCK(6000000) CPUTYPE("Cortex-M3")) + FlashUt () + StupF ("STARTUP\Luminary\Startup.s" ("Luminary Startup Code")) + FlashDR (UL2CM3(-UU0101L5E -O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0LM3S_256 -FS00 -FL040000)) + DevID (4337) + Rgf (LM3Sxxxx.H) + Mem () + C () + A () + RL () + OH () + DBC_IFX () + DBC_CMS () + DBC_AMS () + DBC_LMS () + UseEnv=0 + EnvBin () + EnvInc () + EnvLib () + EnvReg (ÿLuminary\) + OrgReg (ÿLuminary\) + TgStat=16 + OutDir (.\rvmdk\) + OutName (RTOSDemo) + GenApp=1 + GenLib=0 + GenHex=0 + Debug=1 + Browse=1 + LstDir (.\rvmdk\) + HexSel=1 + MG32K=0 + TGMORE=0 + RunUsr 0 1 + RunUsr 1 0 <> + BrunUsr 0 0 <> + BrunUsr 1 0 <> + CrunUsr 0 0 <> + CrunUsr 1 0 <> + SVCSID <> + GLFLAGS=1790 + ADSFLGA { 16,3,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ACPUTYP ("Cortex-M3") + ADSTFLGA { 0,12,0,2,99,0,0,66,0,0,0,0,0,0,0,0,0,0,0,0 } + OCMADSOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + OCMADSIRAM { 0,0,0,0,32,0,0,1,0 } + OCMADSIROM { 1,0,0,0,0,0,0,4,0 } + OCMADSXRAM { 0,0,0,0,0,0,0,0,0 } + OCR_RVCT { 1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,4,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,1,0,0,0,0,0,0,0,0,0,0 } + RV_STAVEC () + ADSCCFLG { 9,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ADSCMISC (--diag_suppress 191,550,513,167,177,144) + ADSCDEFN (RVDS_ARMCM3_LM3S102, "PACK_STRUCT_END=","ALIGN_STRUCT_END=") + ADSCUDEF () + ADSCINCD (.;.\..\Common\drivers\LuminaryMicro;..\..\Source\portable\RVDS\ARM_CM3;..\..\Source\include;..\Common\include;..\Common\ethernet\uIP\uip-1.0\uip;.\webserver) + ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ADSAMISC () + ADSADEFN () + ADSAUDEF () + ADSAINCD () + PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + IncBld=1 + AlwaysBuild=0 + GenAsm=0 + AsmAsm=0 + PublicsOnly=0 + StopCode=3 + CustArgs () + LibMods () + ADSLDFG { 17,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ADSLDTA (0x00000000) + ADSLDDA (0x20000000) + ADSLDSC () + ADSLDIB () + ADSLDIC () + ADSLDMC (--entry Reset_Handler) + ADSLDIF () + ADSLDDW () + OPTDL (SARMCM3.DLL)()(DLM.DLL)(-pLM3S6965)(SARMCM3.DLL)()(TLM.DLL)(-pLM3S6965) + OPTDBG 48126,3,()()()()()()()()()() (BIN\lmidk-agdi.dll)()()() + FLASH1 { 1,0,0,0,1,0,0,0,3,0,0,0,0,0,0,0,0,0,0,0 } + FLASH2 (BIN\lmidk-agdi.dll) + FLASH3 ("" ()) + FLASH4 () +EndOpt + diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.ewd b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.ewd new file mode 100644 index 000000000..a1f663560 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.ewd @@ -0,0 +1,616 @@ + + + + 1 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 15 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IARROM_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + JLINK_ID + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 1 + 1 + 1 + + + + + + + + MACRAIGOR_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin + 1 + + + + + + diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.ewp b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.ewp new file mode 100644 index 000000000..1f0f615c4 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.ewp @@ -0,0 +1,886 @@ + + + + 1 + + Debug + + ARM + + 1 + + General + 3 + + 14 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 19 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 7 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 5 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Demo files + + $PROJ_DIR$\..\Common\Minimal\BlockQ.c + + + $PROJ_DIR$\..\Common\Minimal\blocktim.c + + + $PROJ_DIR$\..\Common\Minimal\death.c + + + $PROJ_DIR$\..\Common\Minimal\flash.c + + + $PROJ_DIR$\..\Common\Minimal\GenQTest.c + + + $PROJ_DIR$\..\Common\Minimal\integer.c + + + $PROJ_DIR$\main.c + + + $PROJ_DIR$\ParTest\ParTest.c + + + $PROJ_DIR$\..\Common\Minimal\PollQ.c + + + $PROJ_DIR$\..\Common\Minimal\QPeek.c + + + $PROJ_DIR$\..\Common\Minimal\semtest.c + + + $PROJ_DIR$\timertest.c + + + + Library files + + $PROJ_DIR$\..\Common\drivers\LuminaryMicro\IAR\driverlib.r79 + + + $PROJ_DIR$\osram128x64x4.c + + + $PROJ_DIR$\rit128x96x4.c + + + + Scheduler files + + $PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c + + + $PROJ_DIR$\..\..\Source\list.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s + + + $PROJ_DIR$\..\..\Source\queue.c + + + $PROJ_DIR$\..\..\Source\tasks.c + + + + System files + + $PROJ_DIR$\startup_ewarm.c + + + + uIP files + + $PROJ_DIR$\webserver\emac.c + + + $PROJ_DIR$\webserver\http-strings.c + + + $PROJ_DIR$\webserver\httpd-cgi.c + + + $PROJ_DIR$\webserver\httpd-fs.c + + + $PROJ_DIR$\webserver\httpd.c + + + $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\psock.c + + + $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\timer.c + + + $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\uip.c + + + $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\uip_arp.c + + + $PROJ_DIR$\webserver\uIP_Task.c + + + + + diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.eww b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.eww new file mode 100644 index 000000000..239a9381e --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\RTOSDemo.ewp + + + + + diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/bitmap.h b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/bitmap.h new file mode 100644 index 000000000..02ce0b365 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/bitmap.h @@ -0,0 +1,171 @@ +#ifndef BITMAP_H +#define BITMAP_H + +const unsigned char pucImage[] = +{ +0x00, 0x0a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, +0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 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0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, +0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, +0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, +0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x0a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, +0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, +0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, +0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0, 0x00, 0xaa, 0xaa, 0xaa, +0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, +0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, +0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x00, +0x00 }; + +#define bmpBITMAP_HEIGHT 50 +#define bmpBITMAP_WIDTH 128 + +#endif diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/lcd_message.h b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/lcd_message.h new file mode 100644 index 000000000..adfc18b8a --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/lcd_message.h @@ -0,0 +1,9 @@ +#ifndef LCD_MESSAGE_H +#define LCD_MESSAGE_H + +typedef struct +{ + signed char *pcMessage; +} xOLEDMessage; + +#endif /* LCD_MESSAGE_H */ diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/main.c b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/main.c new file mode 100644 index 000000000..bb32c33b8 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/main.c @@ -0,0 +1,371 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +/* + * Creates all the demo application tasks, then starts the scheduler. The WEB + * documentation provides more details of the standard demo application tasks. + * In addition to the standard demo tasks, the following tasks and tests are + * defined and/or created within this file: + * + * "Fast Interrupt Test" - A high frequency periodic interrupt is generated + * using a free running timer to demonstrate the use of the + * configKERNEL_INTERRUPT_PRIORITY configuration constant. The interrupt + * service routine measures the number of processor clocks that occur between + * each interrupt - and in so doing measures the jitter in the interrupt timing. + * The maximum measured jitter time is latched in the ulMaxJitter variable, and + * displayed on the OLED display by the 'OLED' task as described below. The + * fast interrupt is configured and handled in the timertest.c source file. + * + * "OLED" task - the OLED task is a 'gatekeeper' task. It is the only task that + * is permitted to access the display directly. Other tasks wishing to write a + * message to the OLED send the message on a queue to the OLED task instead of + * accessing the OLED themselves. The OLED task just blocks on the queue waiting + * for messages - waking and displaying the messages as they arrive. + * + * "Check" hook - This only executes every five seconds from the tick hook. + * Its main function is to check that all the standard demo tasks are still + * operational. Should any unexpected behaviour within a demo task be discovered + * the tick hook will write an error to the OLED (via the OLED task). If all the + * demo tasks are executing with their expected behaviour then the check task + * writes PASS to the OLED (again via the OLED task), as described above. + * + * "uIP" task - This is the task that handles the uIP stack. All TCP/IP + * processing is performed in this task. + */ + + + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "Task.h" +#include "queue.h" +#include "semphr.h" + +/* Demo app includes. */ +#include "BlockQ.h" +#include "death.h" +#include "integer.h" +#include "blocktim.h" +#include "flash.h" +#include "partest.h" +#include "semtest.h" +#include "pollq.h" +#include "lcd_message.h" +#include "bitmap.h" +#include "GenQTest.h" +#include "QPeek.h" + +/* Hardware library includes. */ +#include "hw_memmap.h" +#include "hw_types.h" +#include "hw_sysctl.h" +#include "sysctl.h" +#include "gpio.h" +#include "rit128x96x4.h" +#include "osram128x64x4.h" + +/*-----------------------------------------------------------*/ + +/* The time between cycles of the 'check' functionality (defined within the +tick hook. */ +#define mainCHECK_DELAY ( ( portTickType ) 5000 / portTICK_RATE_MS ) + +/* Size of the stack allocated to the uIP task. */ +#define mainBASIC_WEB_STACK_SIZE ( configMINIMAL_STACK_SIZE * 3 ) + +/* The OLED task uses the sprintf function so requires a little more stack too. */ +#define mainOLED_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE + 50 ) + +/* Task priorities. */ +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainINTEGER_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY ) + +/* The maximum number of message that can be waiting for display at any one +time. */ +#define mainOLED_QUEUE_SIZE ( 3 ) + +/* Dimensions the buffer into which the jitter time is written. */ +#define mainMAX_MSG_LEN 25 + +/* The period of the system clock in nano seconds. This is used to calculate +the jitter time in nano seconds. */ +#define mainNS_PER_CLOCK ( ( unsigned portLONG ) ( ( 1.0 / ( double ) configCPU_CLOCK_HZ ) * 1000000000.0 ) ) + +/* Constants used when writing strings to the display. */ +#define mainCHARACTER_HEIGHT ( 9 ) +#define mainMAX_ROWS_96 ( mainCHARACTER_HEIGHT * 10 ) +#define mainMAX_ROWS_64 ( mainCHARACTER_HEIGHT * 7 ) +#define mainFULL_SCALE ( 15 ) +#define ulSSI_FREQUENCY ( 3500000UL ) + +/*-----------------------------------------------------------*/ + +/* + * The task that handles the uIP stack. All TCP/IP processing is performed in + * this task. + */ +extern void vuIP_Task( void *pvParameters ); + +/* + * The display is written two by more than one task so is controlled by a + * 'gatekeeper' task. This is the only task that is actually permitted to + * access the display directly. Other tasks wanting to display a message send + * the message to the gatekeeper. + */ +static void vOLEDTask( void *pvParameters ); + +/* + * Configure the hardware for the demo. + */ +static void prvSetupHardware( void ); + +/* + * Configures the high frequency timers - those used to measure the timing + * jitter while the real time kernel is executing. + */ +extern void vSetupTimer( void ); + +/*-----------------------------------------------------------*/ + +/* The queue used to send messages to the OLED task. */ +xQueueHandle xOLEDQueue; + +/* The welcome text. */ +const portCHAR * const pcWelcomeMessage = " www.FreeRTOS.org"; + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + prvSetupHardware(); + + /* Create the queue used by the OLED task. Messages for display on the OLED + are received via this queue. */ + xOLEDQueue = xQueueCreate( mainOLED_QUEUE_SIZE, sizeof( xOLEDMessage ) ); + + /* Create the uIP task if running on a processor that includes a MAC and + PHY. */ + if( SysCtlPeripheralPresent( SYSCTL_PERIPH_ETH ) ) + { + xTaskCreate( vuIP_Task, ( signed portCHAR * ) "uIP", mainBASIC_WEB_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY - 1, NULL ); + } + + /* Start the standard demo tasks. */ + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vCreateBlockTimeTasks(); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartIntegerMathTasks( mainINTEGER_TASK_PRIORITY ); + vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY ); + vStartQueuePeekTasks(); + + /* Start the tasks defined within this file/specific to this demo. */ + xTaskCreate( vOLEDTask, ( signed portCHAR * ) "OLED", mainOLED_TASK_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + + /* The suicide tasks must be created last as they need to know how many + tasks were running prior to their creation in order to ascertain whether + or not the correct/expected number of tasks are running at any given time. */ + vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); + + /* Configure the high frequency interrupt used to measure the interrupt + jitter time. The Keil port does not yet include the + configKERNEL_INTERRUPT_PRIORITY functionality so cannot perform this test. */ + #ifndef RVDS_ARMCM3_LM3S102 + { + vSetupTimer(); + } + #endif + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* Will only get here if there was insufficient memory to create the idle + task. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void prvSetupHardware( void ) +{ + /* If running on Rev A2 silicon, turn the LDO voltage up to 2.75V. This is + a workaround to allow the PLL to operate reliably. */ + if( DEVICE_IS_REVA2 ) + { + SysCtlLDOSet( SYSCTL_LDO_2_75V ); + } + + /* Set the clocking to run from the PLL at 50 MHz */ + SysCtlClockSet( SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_8MHZ ); + + /* Enable Port F for Ethernet LEDs + LED0 Bit 3 Output + LED1 Bit 2 Output */ + SysCtlPeripheralEnable( SYSCTL_PERIPH_GPIOF ); + GPIODirModeSet( GPIO_PORTF_BASE, (GPIO_PIN_2 | GPIO_PIN_3), GPIO_DIR_MODE_HW ); + GPIOPadConfigSet( GPIO_PORTF_BASE, (GPIO_PIN_2 | GPIO_PIN_3 ), GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD ); + + vParTestInitialise(); +} +/*-----------------------------------------------------------*/ + +void vApplicationTickHook( void ) +{ +static xOLEDMessage xMessage = { "PASS" }; +static unsigned portLONG ulTicksSinceLastDisplay = 0; + + /* Called from every tick interrupt. Have enough ticks passed to make it + time to perform our health status check again? */ + ulTicksSinceLastDisplay++; + if( ulTicksSinceLastDisplay >= mainCHECK_DELAY ) + { + ulTicksSinceLastDisplay = 0; + + /* Has an error been found in any task? */ + if( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN GEN Q"; + } + else if( xAreQueuePeekTasksStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN PEEK Q"; + } + else if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN BLOCK Q"; + } + else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN BLOCK TIME"; + } + else if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN SEMAPHORE"; + } + else if( xArePollingQueuesStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN POLL Q"; + } + else if( xIsCreateTaskStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN CREATE"; + } + else if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN MATH"; + } + + /* Send the message to the OLED gatekeeper for display. */ + xQueueSendFromISR( xOLEDQueue, &xMessage, pdFALSE ); + } +} +/*-----------------------------------------------------------*/ + +void vOLEDTask( void *pvParameters ) +{ +xOLEDMessage xMessage; +unsigned portLONG ulY, ulMaxY; +static portCHAR cMessage[ mainMAX_MSG_LEN ]; +extern unsigned portLONG ulMaxJitter; + +/* Functions to access the OLED. The one used depends on the dev kit +being used. */ +void ( *vOLEDInit )( unsigned portLONG ); +void ( *vOLEDStringDraw )( const portCHAR *, unsigned portLONG, unsigned portLONG, unsigned portCHAR ); +void ( *vOLEDImageDraw )( const unsigned portCHAR *, unsigned portLONG, unsigned portLONG, unsigned portLONG, unsigned portLONG ); +void ( *vOLEDClear )( void ); + + /* Map the OLED access functions to the driver functions that are appropriate + for the evaluation kit being used. */ + switch( HWREG( SYSCTL_DID1 ) & SYSCTL_DID1_PRTNO_MASK ) + { + case SYSCTL_DID1_PRTNO_6965 : + case SYSCTL_DID1_PRTNO_2965 : vOLEDInit = OSRAM128x64x4Init; + vOLEDStringDraw = OSRAM128x64x4StringDraw; + vOLEDImageDraw = OSRAM128x64x4ImageDraw; + vOLEDClear = OSRAM128x64x4Clear; + ulMaxY = mainMAX_ROWS_64; + break; + + default : vOLEDInit = RIT128x96x4Init; + vOLEDStringDraw = RIT128x96x4StringDraw; + vOLEDImageDraw = RIT128x96x4ImageDraw; + vOLEDClear = RIT128x96x4Clear; + ulMaxY = mainMAX_ROWS_96; + break; + } + + ulY = ulMaxY; + + /* Initialise the OLED and display a startup message. */ + vOLEDInit( ulSSI_FREQUENCY ); + vOLEDStringDraw( " POWERED BY FreeRTOS", 0, 0, mainFULL_SCALE ); + vOLEDImageDraw( pucImage, 0, mainCHARACTER_HEIGHT + 1, bmpBITMAP_WIDTH, bmpBITMAP_HEIGHT ); + + for( ;; ) + { + /* Wait for a message to arrive that requires displaying. */ + xQueueReceive( xOLEDQueue, &xMessage, portMAX_DELAY ); + + /* Write the message on the next available row. */ + ulY += mainCHARACTER_HEIGHT; + if( ulY >= ulMaxY ) + { + ulY = mainCHARACTER_HEIGHT; + vOLEDClear(); + vOLEDStringDraw( pcWelcomeMessage, 0, 0, mainFULL_SCALE ); + } + + /* Display the message along with the maximum jitter time from the + high priority time test. */ + sprintf( cMessage, "%s [%uns]", xMessage.pcMessage, ulMaxJitter * mainNS_PER_CLOCK ); + vOLEDStringDraw( cMessage, 0, ulY, mainFULL_SCALE ); + } +} diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/osram128x64x4.c b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/osram128x64x4.c new file mode 100644 index 000000000..3353a82e6 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/osram128x64x4.c @@ -0,0 +1,933 @@ +//***************************************************************************** +// +// osram128x64x4.c - Driver for the OSRAM 128x64x4 graphical OLED display. +// +// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1408 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup ek_lm3sx965_api +//! @{ +// +//***************************************************************************** + +#include "hw_ssi.h" +#include "hw_memmap.h" +#include "hw_sysctl.h" +#include "hw_types.h" +#include "debug.h" +#include "gpio.h" +#include "ssi.h" +#include "sysctl.h" +#include "osram128x64x4.h" + +//***************************************************************************** +// +// Flag to indicate if SSI port is enabled for OSRAM usage. +// +//***************************************************************************** +static volatile tBoolean g_bSSIEnabled = false; + +//***************************************************************************** +// +// Define the OSRAM 128x64x4 Remap Setting(s). This will be used in +// several places in the code to switch between vertical and horizontal +// address incrementing. +// +// The Remap Command (0xA0) takes one 8-bit parameter. The parameter is +// defined as follows. +// +// Bit 7: Reserved +// Bit 6: Disable(0)/Enable(1) COM Split Odd Even +// When enabled, the COM signals are split Odd on one side, even on +// the other. Otherwise, they are split 0-39 on one side, 40-79 on +// the other. +// Bit 5: Reserved +// Bit 4: Disable(0)/Enable(1) COM Remap +// When Enabled, ROW 0-79 map to COM 79-0 (i.e. reverse row order) +// Bit 3: Reserved +// Bit 2: Horizontal(0)/Vertical(1) Address Increment +// When set, data RAM address will increment along the column rather +// than along the row. +// Bit 1: Disable(0)/Enable(1) Nibble Remap +// When enabled, the upper and lower nibbles in the DATA bus for access +// to the data RAM are swapped. +// Bit 0: Disable(0)/Enable(1) Column Address Remap +// When enabled, DATA RAM columns 0-63 are remapped to Segment Columns +// 127-0. +// +//***************************************************************************** +#define OSRAM_INIT_REMAP 0x52 +#define OSRAM_INIT_OFFSET 0x4C +static const unsigned char g_pucOSRAM128x64x4VerticalInc[] = { 0xA0, 0x56 }; +static const unsigned char g_pucOSRAM128x64x4HorizontalInc[] = { 0xA0, 0x52 }; + +//***************************************************************************** +// +// A 5x7 font (in a 6x8 cell, where the sixth column is omitted from this +// table) for displaying text on the OLED display. The data is organized as +// bytes from the left column to the right column, with each byte containing +// the top row in the LSB and the bottom row in the MSB. +// +// Note: This is the same font data that is used in the EK-LM3S811 +// osram96x16x1 driver. The single bit-per-pixel is expaned in the StringDraw +// function to the appropriate four bit-per-pixel gray scale format. +// +//***************************************************************************** +static const unsigned char g_pucFont[96][5] = +{ + { 0x00, 0x00, 0x00, 0x00, 0x00 }, // " " + { 0x00, 0x00, 0x4f, 0x00, 0x00 }, // ! + { 0x00, 0x07, 0x00, 0x07, 0x00 }, // " + { 0x14, 0x7f, 0x14, 0x7f, 0x14 }, // # + { 0x24, 0x2a, 0x7f, 0x2a, 0x12 }, // $ + { 0x23, 0x13, 0x08, 0x64, 0x62 }, // % + { 0x36, 0x49, 0x55, 0x22, 0x50 }, // & + { 0x00, 0x05, 0x03, 0x00, 0x00 }, // ' + { 0x00, 0x1c, 0x22, 0x41, 0x00 }, // ( + { 0x00, 0x41, 0x22, 0x1c, 0x00 }, // ) + { 0x14, 0x08, 0x3e, 0x08, 0x14 }, // * + { 0x08, 0x08, 0x3e, 0x08, 0x08 }, // + + { 0x00, 0x50, 0x30, 0x00, 0x00 }, // , + { 0x08, 0x08, 0x08, 0x08, 0x08 }, // - + { 0x00, 0x60, 0x60, 0x00, 0x00 }, // . + { 0x20, 0x10, 0x08, 0x04, 0x02 }, // / + { 0x3e, 0x51, 0x49, 0x45, 0x3e }, // 0 + { 0x00, 0x42, 0x7f, 0x40, 0x00 }, // 1 + { 0x42, 0x61, 0x51, 0x49, 0x46 }, // 2 + { 0x21, 0x41, 0x45, 0x4b, 0x31 }, // 3 + { 0x18, 0x14, 0x12, 0x7f, 0x10 }, // 4 + { 0x27, 0x45, 0x45, 0x45, 0x39 }, // 5 + { 0x3c, 0x4a, 0x49, 0x49, 0x30 }, // 6 + { 0x01, 0x71, 0x09, 0x05, 0x03 }, // 7 + { 0x36, 0x49, 0x49, 0x49, 0x36 }, // 8 + { 0x06, 0x49, 0x49, 0x29, 0x1e }, // 9 + { 0x00, 0x36, 0x36, 0x00, 0x00 }, // : + { 0x00, 0x56, 0x36, 0x00, 0x00 }, // ; + { 0x08, 0x14, 0x22, 0x41, 0x00 }, // < + { 0x14, 0x14, 0x14, 0x14, 0x14 }, // = + { 0x00, 0x41, 0x22, 0x14, 0x08 }, // > + { 0x02, 0x01, 0x51, 0x09, 0x06 }, // ? + { 0x32, 0x49, 0x79, 0x41, 0x3e }, // @ + { 0x7e, 0x11, 0x11, 0x11, 0x7e }, // A + { 0x7f, 0x49, 0x49, 0x49, 0x36 }, // B + { 0x3e, 0x41, 0x41, 0x41, 0x22 }, // C + { 0x7f, 0x41, 0x41, 0x22, 0x1c }, // D + { 0x7f, 0x49, 0x49, 0x49, 0x41 }, // E + { 0x7f, 0x09, 0x09, 0x09, 0x01 }, // F + { 0x3e, 0x41, 0x49, 0x49, 0x7a }, // G + { 0x7f, 0x08, 0x08, 0x08, 0x7f }, // H + { 0x00, 0x41, 0x7f, 0x41, 0x00 }, // I + { 0x20, 0x40, 0x41, 0x3f, 0x01 }, // J + { 0x7f, 0x08, 0x14, 0x22, 0x41 }, // K + { 0x7f, 0x40, 0x40, 0x40, 0x40 }, // L + { 0x7f, 0x02, 0x0c, 0x02, 0x7f }, // M + { 0x7f, 0x04, 0x08, 0x10, 0x7f }, // N + { 0x3e, 0x41, 0x41, 0x41, 0x3e }, // O + { 0x7f, 0x09, 0x09, 0x09, 0x06 }, // P + { 0x3e, 0x41, 0x51, 0x21, 0x5e }, // Q + { 0x7f, 0x09, 0x19, 0x29, 0x46 }, // R + { 0x46, 0x49, 0x49, 0x49, 0x31 }, // S + { 0x01, 0x01, 0x7f, 0x01, 0x01 }, // T + { 0x3f, 0x40, 0x40, 0x40, 0x3f }, // U + { 0x1f, 0x20, 0x40, 0x20, 0x1f }, // V + { 0x3f, 0x40, 0x38, 0x40, 0x3f }, // W + { 0x63, 0x14, 0x08, 0x14, 0x63 }, // X + { 0x07, 0x08, 0x70, 0x08, 0x07 }, // Y + { 0x61, 0x51, 0x49, 0x45, 0x43 }, // Z + { 0x00, 0x7f, 0x41, 0x41, 0x00 }, // [ + { 0x02, 0x04, 0x08, 0x10, 0x20 }, // "\" + { 0x00, 0x41, 0x41, 0x7f, 0x00 }, // ] + { 0x04, 0x02, 0x01, 0x02, 0x04 }, // ^ + { 0x40, 0x40, 0x40, 0x40, 0x40 }, // _ + { 0x00, 0x01, 0x02, 0x04, 0x00 }, // ` + { 0x20, 0x54, 0x54, 0x54, 0x78 }, // a + { 0x7f, 0x48, 0x44, 0x44, 0x38 }, // b + { 0x38, 0x44, 0x44, 0x44, 0x20 }, // c + { 0x38, 0x44, 0x44, 0x48, 0x7f }, // d + { 0x38, 0x54, 0x54, 0x54, 0x18 }, // e + { 0x08, 0x7e, 0x09, 0x01, 0x02 }, // f + { 0x0c, 0x52, 0x52, 0x52, 0x3e }, // g + { 0x7f, 0x08, 0x04, 0x04, 0x78 }, // h + { 0x00, 0x44, 0x7d, 0x40, 0x00 }, // i + { 0x20, 0x40, 0x44, 0x3d, 0x00 }, // j + { 0x7f, 0x10, 0x28, 0x44, 0x00 }, // k + { 0x00, 0x41, 0x7f, 0x40, 0x00 }, // l + { 0x7c, 0x04, 0x18, 0x04, 0x78 }, // m + { 0x7c, 0x08, 0x04, 0x04, 0x78 }, // n + { 0x38, 0x44, 0x44, 0x44, 0x38 }, // o + { 0x7c, 0x14, 0x14, 0x14, 0x08 }, // p + { 0x08, 0x14, 0x14, 0x18, 0x7c }, // q + { 0x7c, 0x08, 0x04, 0x04, 0x08 }, // r + { 0x48, 0x54, 0x54, 0x54, 0x20 }, // s + { 0x04, 0x3f, 0x44, 0x40, 0x20 }, // t + { 0x3c, 0x40, 0x40, 0x20, 0x7c }, // u + { 0x1c, 0x20, 0x40, 0x20, 0x1c }, // v + { 0x3c, 0x40, 0x30, 0x40, 0x3c }, // w + { 0x44, 0x28, 0x10, 0x28, 0x44 }, // x + { 0x0c, 0x50, 0x50, 0x50, 0x3c }, // y + { 0x44, 0x64, 0x54, 0x4c, 0x44 }, // z + { 0x00, 0x08, 0x36, 0x41, 0x00 }, // { + { 0x00, 0x00, 0x7f, 0x00, 0x00 }, // | + { 0x00, 0x41, 0x36, 0x08, 0x00 }, // } + { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~ + { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~ +}; + +//***************************************************************************** +// +// The sequence of commands used to initialize the SSD0303 controller. Each +// command is described as follows: there is a byte specifying the number of +// bytes in the command sequence, followed by that many bytes of command data. +// Note: This initialization sequence is derived from OSRAM App Note AN018. +// +//***************************************************************************** +static const unsigned char g_pucOSRAM128x64x4Init[] = +{ + // + // Column Address + // + 4, 0x15, 0, 63, 0xe3, + + // + // Row Address + // + 4, 0x75, 0, 63, 0xe3, + + // + // Contrast Control + // + 3, 0x81, 50, 0xe3, + + // + // Half Current Range + // + 2, 0x85, 0xe3, + + // + // Display Re-map + // + 3, 0xA0, OSRAM_INIT_REMAP, 0xe3, + + // + // Display Start Line + // + 3, 0xA1, 0, 0xe3, + + // + // Display Offset + // + 3, 0xA2, OSRAM_INIT_OFFSET, 0xe3, + + // + // Display Mode Normal + // + 2, 0xA4, 0xe3, + + // + // Multiplex Ratio + // + 3, 0xA8, 63, 0xe3, + + // + // Phase Length + // + 3, 0xB1, 0x22, 0xe3, + + // + // Row Period + // + 3, 0xB2, 70, 0xe3, + + // + // Display Clock Divide + // + 3, 0xB3, 0xF1, 0xe3, + + // + // VSL + // + 3, 0xBF, 0x0D, 0xe3, + + // + // VCOMH + // + 3, 0xBE, 0x02, 0xe3, + + // + // VP + // + 3, 0xBC, 0x10, 0xe3, + + // + // Gamma + // + 10, 0xB8, 0x01, 0x11, 0x22, 0x32, 0x43, 0x54, 0x65, 0x76, 0xe3, + + // + // Set DC-DC + 3, 0xAD, 0x03, 0xe3, + + // + // Display ON/OFF + // + 2, 0xAF, 0xe3, +}; + +//***************************************************************************** +// +//! \internal +//! +//! Write a sequence of command bytes to the SSD0323 controller. +//! +//! The data is written in a polled fashion; this function will not return +//! until the entire byte sequence has been written to the controller. +//! +//! \return None. +// +//***************************************************************************** +static void +OSRAMWriteCommand(const unsigned char *pucBuffer, unsigned long ulCount) +{ + unsigned long ulTemp; + + // + // Return iff SSI port is not enabled for OSRAM. + // + if(!g_bSSIEnabled) + { + return; + } + + // + // Clear the command/control bit to enable command mode. + // + GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, 0); + + // + // Loop while there are more bytes left to be transferred. + // + while(ulCount != 0) + { + // + // Write the next byte to the controller. + // + SSIDataPut(SSI0_BASE, *pucBuffer++); + + // + // Dummy read to drain the fifo and time the GPIO signal. + // + SSIDataGet(SSI0_BASE, &ulTemp); + + // + // Decrement the BYTE counter. + // + ulCount--; + } +} + +//***************************************************************************** +// +//! \internal +//! +//! Write a sequence of data bytes to the SSD0323 controller. +//! +//! The data is written in a polled fashion; this function will not return +//! until the entire byte sequence has been written to the controller. +//! +//! \return None. +// +//***************************************************************************** +static void +OSRAMWriteData(const unsigned char *pucBuffer, unsigned long ulCount) +{ + unsigned long ulTemp; + + // + // Return iff SSI port is not enabled for OSRAM. + // + if(!g_bSSIEnabled) + { + return; + } + + // + // Set the command/control bit to enable data mode. + // + GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_PIN_7); + + // + // Loop while there are more bytes left to be transferred. + // + while(ulCount != 0) + { + // + // Write the next byte to the controller. + // + SSIDataPut(SSI0_BASE, *pucBuffer++); + + // + // Dummy read to drain the fifo and time the GPIO signal. + // + SSIDataGet(SSI0_BASE, &ulTemp); + + // + // Decrement the BYTE counter. + // + ulCount--; + } +} + +//***************************************************************************** +// +//! Clears the OLED display. +//! +//! This function will clear the display RAM. All pixels in the display will +//! be turned off. +//! +//! This function is contained in osram128x64x4.c, with +//! osram128x64x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAM128x64x4Clear(void) +{ + static const unsigned char pucCommand1[] = { 0x15, 0, 63 }; + static const unsigned char pucCommand2[] = { 0x75, 0, 79 }; + unsigned long ulRow, ulColumn; + static unsigned char pucZeroBuffer[8] = { 0, 0, 0, 0, 0, 0, 0, 0}; + + // + // Set the window to fill the entire display. + // + OSRAMWriteCommand(pucCommand1, sizeof(pucCommand1)); + OSRAMWriteCommand(pucCommand2, sizeof(pucCommand2)); + OSRAMWriteCommand(g_pucOSRAM128x64x4VerticalInc, + sizeof(g_pucOSRAM128x64x4VerticalInc)); + + // + // In vertical address increment mode, loop through each column, filling + // each row with 0. + // + for(ulColumn = 0; ulColumn < (128/2); ulColumn++) + { + // + // 8 rows (bytes) per row of text. + // + for(ulRow = 0; ulRow < 80; ulRow += 8) + { + OSRAMWriteData(pucZeroBuffer, sizeof(pucZeroBuffer)); + } + } +} + +//***************************************************************************** +// +//! Displays a string on the OLED display. +//! +//! \param pcStr is a pointer to the string to display. +//! \param ulX is the horizontal position to display the string, specified in +//! columns from the left edge of the display. +//! \param ulY is the vertical position to display the string, specified in +//! rows from the top edge of the display. +//! \param ucLevel is the 4-bit grey scale value to be used for displayed text. +//! +//! This function will draw a string on the display. Only the ASCII characters +//! between 32 (space) and 126 (tilde) are supported; other characters will +//! result in random data being draw on the display (based on whatever appears +//! before/after the font in memory). The font is mono-spaced, so characters +//! such as "i" and "l" have more white space around them than characters such +//! as "m" or "w". +//! +//! If the drawing of the string reaches the right edge of the display, no more +//! characters will be drawn. Therefore, special care is not required to avoid +//! supplying a string that is "too long" to display. +//! +//! This function is contained in osram128x64x4.c, with +//! osram128x64x4.h containing the API definition for use by +//! applications. +//! +//! \note Because the OLED display packs 2 pixels of data in a single byte, the +//! parameter \e ulX must be an even column number (e.g. 0, 2, 4, etc). +//! +//! \return None. +// +//***************************************************************************** +void +OSRAM128x64x4StringDraw(const char *pcStr, unsigned long ulX, + unsigned long ulY, unsigned char ucLevel) +{ + static unsigned char pucBuffer[8]; + unsigned long ulIdx1, ulIdx2; + unsigned char ucTemp; + + // + // Check the arguments. + // + ASSERT(ulX < 128); + ASSERT((ulX & 1) == 0); + ASSERT(ulY < 64); + ASSERT(ucLevel < 16); + + // + // Setup a window starting at the specified column and row, ending + // at the right edge of the display and 8 rows down (single character row). + // + pucBuffer[0] = 0x15; + pucBuffer[1] = ulX / 2; + pucBuffer[2] = 63; + OSRAMWriteCommand(pucBuffer, 3); + pucBuffer[0] = 0x75; + pucBuffer[1] = ulY; + pucBuffer[2] = ulY + 7; + OSRAMWriteCommand(pucBuffer, 3); + OSRAMWriteCommand(g_pucOSRAM128x64x4VerticalInc, + sizeof(g_pucOSRAM128x64x4VerticalInc)); + + // + // Loop while there are more characters in the string. + // + while(*pcStr != 0) + { + // + // Get a working copy of the current character and convert to an + // index into the character bit-map array. + // + ucTemp = *pcStr; + ucTemp &= 0x7F; + if(ucTemp < ' ') + { + ucTemp = ' '; + } + else + { + ucTemp -= ' '; + } + + // + // Build and display the character buffer. + // + for(ulIdx1 = 0; ulIdx1 < 3; ulIdx1++) + { + // + // Convert two columns of 1-bit font data into a single data + // byte column of 4-bit font data. + // + for(ulIdx2 = 0; ulIdx2 < 8; ulIdx2++) + { + pucBuffer[ulIdx2] = 0; + if(g_pucFont[ucTemp][ulIdx1*2] & (1 << ulIdx2)) + { + pucBuffer[ulIdx2] = ((ucLevel << 4) & 0xf0); + } + if((ulIdx1 < 2) && + (g_pucFont[ucTemp][ulIdx1*2+1] & (1 << ulIdx2))) + { + pucBuffer[ulIdx2] |= ((ucLevel << 0) & 0x0f); + } + } + + // + // If there is room, dump the single data byte column to the + // display. Otherwise, bail out. + // + if(ulX < 126) + { + OSRAMWriteData(pucBuffer, 8); + ulX += 2; + } + else + { + return; + } + } + + // + // Advance to the next character. + // + pcStr++; + } +} + +//***************************************************************************** +// +//! Displays an image on the OLED display. +//! +//! \param pucImage is a pointer to the image data. +//! \param ulX is the horizontal position to display this image, specified in +//! columns from the left edge of the display. +//! \param ulY is the vertical position to display this image, specified in +//! rows from the top of the display. +//! \param ulWidth is the width of the image, specified in columns. +//! \param ulHeight is the height of the image, specified in rows. +//! +//! This function will display a bitmap graphic on the display. Because of the +//! format of the display RAM, the starting column (/e ulX) and the number of +//! columns (/e ulWidth) must be an integer multiple of two. +//! +//! The image data is organized with the first row of image data appearing left +//! to right, followed immediately by the second row of image data. Each byte +//! contains the data for two columns in the current row, with the leftmost +//! column being contained in bits 7:4 and the rightmost column being contained +//! in bits 3:0. +//! +//! For example, an image six columns wide and seven scan lines tall would +//! be arranged as follows (showing how the twenty one bytes of the image would +//! appear on the display): +//! +//! \verbatim +//! +-------------------+-------------------+-------------------+ +//! | Byte 0 | Byte 1 | Byte 2 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 3 | Byte 4 | Byte 5 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 6 | Byte 7 | Byte 8 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 9 | Byte 10 | Byte 11 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 12 | Byte 13 | Byte 14 | +//! +---------+---------+---------+--3------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 15 | Byte 16 | Byte 17 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 18 | Byte 19 | Byte 20 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! \endverbatim +//! +//! This function is contained in osram128x64x4.c, with +//! osram128x64x4.h containing the API definition for use by` +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAM128x64x4ImageDraw(const unsigned char *pucImage, unsigned long ulX, + unsigned long ulY, unsigned long ulWidth, + unsigned long ulHeight) +{ + static unsigned char pucBuffer[8]; + + // + // Check the arguments. + // + ASSERT(ulX < 128); + ASSERT((ulX & 1) == 0); + ASSERT(ulY < 64); + ASSERT((ulX + ulWidth) <= 128); + ASSERT((ulY + ulHeight) <= 64); + ASSERT((ulWidth & 1) == 0); + + // + // Setup a window starting at the specified column and row, and ending + // at the column + width and row+height. + // + pucBuffer[0] = 0x15; + pucBuffer[1] = ulX / 2; + pucBuffer[2] = (ulX + ulWidth - 2) / 2; + OSRAMWriteCommand(pucBuffer, 3); + pucBuffer[0] = 0x75; + pucBuffer[1] = ulY; + pucBuffer[2] = ulY + ulHeight - 1; + OSRAMWriteCommand(pucBuffer, 3); + OSRAMWriteCommand(g_pucOSRAM128x64x4HorizontalInc, + sizeof(g_pucOSRAM128x64x4HorizontalInc)); + + // + // Loop while there are more rows to display. + // + while(ulHeight--) + { + // + // Write this row of image data. + // + OSRAMWriteData(pucImage, (ulWidth / 2)); + + // + // Advance to the next row of the image. + // + pucImage += (ulWidth / 2); + } +} + +//***************************************************************************** +// +//! Enable the SSI component of the OLED display driver. +//! +//! \param ulFrequency specifies the SSI Clock Frequency to be used. +//! +//! This function initializes the SSI interface to the OLED display. +//! +//! This function is contained in osram128x64x4.c, with +//! osram128x64x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAM128x64x4Enable(unsigned long ulFrequency) +{ + unsigned long ulTemp; + + // + // Disable the SSI port. + // + SSIDisable(SSI0_BASE); + + // + // Configure the SSI0 port for master mode. + // + SSIConfig(SSI0_BASE, SSI_FRF_MOTO_MODE_2, SSI_MODE_MASTER, ulFrequency, 8); + + // + // (Re)Enable SSI control of the FSS pin. + // + GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_3); + GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA, + GPIO_PIN_TYPE_STD_WPU); + + // + // Enable the SSI port. + // + SSIEnable(SSI0_BASE); + + // + // Drain the receive fifo. + // + while(SSIDataNonBlockingGet(SSI0_BASE, &ulTemp) != 0) + { + } + + // + // Indicate that the OSRAM driver can use the SSI Port. + // + g_bSSIEnabled = true; +} + +//***************************************************************************** +// +//! Enable the SSI component of the OLED display driver. +//! +//! \param ulFrequency specifies the SSI Clock Frequency to be used. +//! +//! This function initializes the SSI interface to the OLED display. +//! +//! This function is contained in osram128x64x4.c, with +//! osram128x64x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAM128x64x4Disable(void) +{ + unsigned long ulTemp; + + // + // Indicate that the OSRAM driver can no longer use the SSI Port. + // + g_bSSIEnabled = false; + + // + // Drain the receive fifo. + // + while(SSIDataNonBlockingGet(SSI0_BASE, &ulTemp) != 0) + { + } + + // + // Disable the SSI port. + // + SSIDisable(SSI0_BASE); + + // + // Disable SSI control of the FSS pin. + // + GPIODirModeSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_DIR_MODE_OUT); + GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA, + GPIO_PIN_TYPE_STD_WPU); + GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_PIN_3); + +} + +//***************************************************************************** +// +//! Initialize the OLED display. +//! +//! \param ulFrequency specifies the SSI Clock Frequency to be used. +//! +//! This function initializes the SSI interface to the OLED display and +//! configures the SSD0323 controller on the panel. +//! +//! This function is contained in osram128x64x4.c, with +//! osram128x64x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAM128x64x4Init(unsigned long ulFrequency) +{ + unsigned long ulIdx; + + // + // Enable the SSI0 and GPIO port blocks as they are needed by this driver. + // + SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC); + + // + // Configure the SSI0CLK and SSIOTX pins for SSI operation. + // + GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5); + GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_2, GPIO_STRENGTH_8MA, + GPIO_PIN_TYPE_STD_WPU); + GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA, + GPIO_PIN_TYPE_STD_WPU); + GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_5, GPIO_STRENGTH_8MA, + GPIO_PIN_TYPE_STD_WPU); + + // + // Configure the PC7 pin as a D/Cn signal for OLED device. + // + GPIODirModeSet(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_DIR_MODE_OUT); + GPIOPadConfigSet(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_STRENGTH_8MA, + GPIO_PIN_TYPE_STD); + GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, GPIO_PIN_7); + + // + // Configure and enable the SSI0 port for master mode. + // + OSRAM128x64x4Enable(ulFrequency); + + // + // Clear the frame buffer. + // + OSRAM128x64x4Clear(); + + // + // Initialize the SSD0323 controller. Loop through the initialization + // sequence array, sending each command "string" to the controller. + // + for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAM128x64x4Init); + ulIdx += g_pucOSRAM128x64x4Init[ulIdx] + 1) + { + // + // Send this command. + // + OSRAMWriteCommand(g_pucOSRAM128x64x4Init + ulIdx + 1, + g_pucOSRAM128x64x4Init[ulIdx] - 1); + } +} + +//***************************************************************************** +// +//! Turns on the OLED display. +//! +//! This function will turn on the OLED display, causing it to display the +//! contents of its internal frame buffer. +//! +//! This function is contained in osram128x64x4.c, with +//! osram128x64x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAM128x64x4DisplayOn(void) +{ + unsigned long ulIdx; + + // + // Initialize the SSD0323 controller. Loop through the initialization + // sequence array, sending each command "string" to the controller. + // + for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAM128x64x4Init); + ulIdx += g_pucOSRAM128x64x4Init[ulIdx] + 1) + { + // + // Send this command. + // + OSRAMWriteCommand(g_pucOSRAM128x64x4Init + ulIdx + 1, + g_pucOSRAM128x64x4Init[ulIdx] - 1); + } +} + +//***************************************************************************** +// +//! Turns off the OLED display. +//! +//! This function will turn off the OLED display. This will stop the scanning +//! of the panel and turn off the on-chip DC-DC converter, preventing damage to +//! the panel due to burn-in (it has similar characters to a CRT in this +//! respect). +//! +//! This function is contained in osram128x64x4.c, with +//! osram128x64x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +OSRAM128x64x4DisplayOff(void) +{ + static const unsigned char pucCommand1[] = + { + 0xAE, 0xAD, 0x02 + }; + + // + // Turn off the DC-DC converter and the display. + // + OSRAMWriteCommand(pucCommand1, sizeof(pucCommand1)); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/osram128x64x4.h b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/osram128x64x4.h new file mode 100644 index 000000000..2ba7cb956 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/osram128x64x4.h @@ -0,0 +1,63 @@ +//***************************************************************************** +// +// osram128x64x4.h - Prototypes for the driver for the OSRAM 128x64x4 graphical +// OLED display. +// +// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1408 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __OSRAM128X64X4_H__ +#define __OSRAM128X64X4_H__ + +//***************************************************************************** +// +// Prototypes for the driver APIs. +// +//***************************************************************************** +extern void OSRAM128x64x4Clear(void); +extern void OSRAM128x64x4StringDraw(const char *pcStr, + unsigned long ulX, + unsigned long ulY, + unsigned char ucLevel); +extern void OSRAM128x64x4ImageDraw(const unsigned char *pucImage, + unsigned long ulX, + unsigned long ulY, + unsigned long ulWidth, + unsigned long ulHeight); +extern void OSRAM128x64x4Init(unsigned long ulFrequency); +extern void OSRAM128x64x4Enable(unsigned long ulFrequency); +extern void OSRAM128x64x4Disable(void); +extern void OSRAM128x64x4DisplayOn(void); +extern void OSRAM128x64x4DisplayOff(void); + +//***************************************************************************** +// +// The following macro(s) map old names for the OSRAM functions to the new +// names. In new code, the new names should be used in favor of the old names. +// +//***************************************************************************** +#ifndef DEPRECATED +#define OSRAM128x64x1InitSSI OSRAM128x64x4Enable +#endif + +#endif // __OSRAM128X64X4_H__ diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rit128x96x4.c b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rit128x96x4.c new file mode 100644 index 000000000..cff38d557 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/rit128x96x4.c @@ -0,0 +1,981 @@ +//***************************************************************************** +// +// rit128x96x4.c - Driver for the RIT 128x96x4 graphical OLED display. +// +// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1504-conf of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup ek_lm3sLM3S8962_api +//! @{ +// +//***************************************************************************** + +#include "hw_ssi.h" +#include "hw_memmap.h" +#include "hw_sysctl.h" +#include "hw_types.h" +#include "debug.h" +#include "gpio.h" +#include "ssi.h" +#include "sysctl.h" +#include "rit128x96x4.h" + +//***************************************************************************** +// +// Macros that define the peripheral, port, and pin used for the OLEDDC +// panel control signal. +// +//***************************************************************************** + +unsigned long ulGPIOId = 0, ulGPIOBase = 0, ulOLEDDC_PIN = 0, ulOLEDEN_PIN = 0; + +#define LM3S8962_SYSCTL_PERIPH_GPIO_OLEDDC SYSCTL_PERIPH_GPIOA +#define LM3S8962_GPIO_OLEDDC_BASE GPIO_PORTA_BASE +#define LM3S8962_GPIO_OLEDDC_PIN GPIO_PIN_6 +#define LM3S8962_GPIO_OLEDEN_PIN GPIO_PIN_7 + +#define LM3S1968_SYSCTL_PERIPH_GPIO_OLEDDC SYSCTL_PERIPH_GPIOH +#define LM3S1968_GPIO_OLEDDC_BASE GPIO_PORTH_BASE +#define LM3S1968_GPIO_OLEDDC_PIN GPIO_PIN_2 +#define LM3S1968_GPIO_OLEDEN_PIN GPIO_PIN_3 + + +//***************************************************************************** +// +// Flag to indicate if SSI port is enabled for display usage. +// +//***************************************************************************** +static volatile tBoolean g_bSSIEnabled = false; + +//***************************************************************************** +// +// Buffer for storing sequences of command and data for the display. +// +//***************************************************************************** +static unsigned char g_pucBuffer[8]; + +//***************************************************************************** +// +// Define the SSD1329 128x96x4 Remap Setting(s). This will be used in +// several places in the code to switch between vertical and horizontal +// address incrementing. Note that the controller support 128 rows while +// the RIT display only uses 96. +// +// The Remap Command (0xA0) takes one 8-bit parameter. The parameter is +// defined as follows. +// +// Bit 7: Reserved +// Bit 6: Disable(0)/Enable(1) COM Split Odd Even +// When enabled, the COM signals are split Odd on one side, even on +// the other. Otherwise, they are split 0-63 on one side, 64-127 on +// the other. +// Bit 5: Reserved +// Bit 4: Disable(0)/Enable(1) COM Remap +// When Enabled, ROW 0-127 map to COM 127-0 (i.e. reverse row order) +// Bit 3: Reserved +// Bit 2: Horizontal(0)/Vertical(1) Address Increment +// When set, data RAM address will increment along the column rather +// than along the row. +// Bit 1: Disable(0)/Enable(1) Nibble Remap +// When enabled, the upper and lower nibbles in the DATA bus for access +// to the data RAM are swapped. +// Bit 0: Disable(0)/Enable(1) Column Address Remap +// When enabled, DATA RAM columns 0-63 are remapped to Segment Columns +// 127-0. +// +//***************************************************************************** +#define RIT_INIT_REMAP 0x52 // app note says 0x51 +#define RIT_INIT_OFFSET 0x00 +static const unsigned char g_pucRIT128x96x4VerticalInc[] = { 0xA0, 0x56 }; +static const unsigned char g_pucRIT128x96x4HorizontalInc[] = { 0xA0, 0x52 }; + +//***************************************************************************** +// +// A 5x7 font (in a 6x8 cell, where the sixth column is omitted from this +// table) for displaying text on the OLED display. The data is organized as +// bytes from the left column to the right column, with each byte containing +// the top row in the LSB and the bottom row in the MSB. +// +// Note: This is the same font data that is used in the EK-LM3S811 +// osram96x16x1 driver. The single bit-per-pixel is expaned in the StringDraw +// function to the appropriate four bit-per-pixel gray scale format. +// +//***************************************************************************** +static const unsigned char g_pucFont[96][5] = +{ + { 0x00, 0x00, 0x00, 0x00, 0x00 }, // " " + { 0x00, 0x00, 0x4f, 0x00, 0x00 }, // ! + { 0x00, 0x07, 0x00, 0x07, 0x00 }, // " + { 0x14, 0x7f, 0x14, 0x7f, 0x14 }, // # + { 0x24, 0x2a, 0x7f, 0x2a, 0x12 }, // $ + { 0x23, 0x13, 0x08, 0x64, 0x62 }, // % + { 0x36, 0x49, 0x55, 0x22, 0x50 }, // & + { 0x00, 0x05, 0x03, 0x00, 0x00 }, // ' + { 0x00, 0x1c, 0x22, 0x41, 0x00 }, // ( + { 0x00, 0x41, 0x22, 0x1c, 0x00 }, // ) + { 0x14, 0x08, 0x3e, 0x08, 0x14 }, // * + { 0x08, 0x08, 0x3e, 0x08, 0x08 }, // + + { 0x00, 0x50, 0x30, 0x00, 0x00 }, // , + { 0x08, 0x08, 0x08, 0x08, 0x08 }, // - + { 0x00, 0x60, 0x60, 0x00, 0x00 }, // . + { 0x20, 0x10, 0x08, 0x04, 0x02 }, // / + { 0x3e, 0x51, 0x49, 0x45, 0x3e }, // 0 + { 0x00, 0x42, 0x7f, 0x40, 0x00 }, // 1 + { 0x42, 0x61, 0x51, 0x49, 0x46 }, // 2 + { 0x21, 0x41, 0x45, 0x4b, 0x31 }, // 3 + { 0x18, 0x14, 0x12, 0x7f, 0x10 }, // 4 + { 0x27, 0x45, 0x45, 0x45, 0x39 }, // 5 + { 0x3c, 0x4a, 0x49, 0x49, 0x30 }, // 6 + { 0x01, 0x71, 0x09, 0x05, 0x03 }, // 7 + { 0x36, 0x49, 0x49, 0x49, 0x36 }, // 8 + { 0x06, 0x49, 0x49, 0x29, 0x1e }, // 9 + { 0x00, 0x36, 0x36, 0x00, 0x00 }, // : + { 0x00, 0x56, 0x36, 0x00, 0x00 }, // ; + { 0x08, 0x14, 0x22, 0x41, 0x00 }, // < + { 0x14, 0x14, 0x14, 0x14, 0x14 }, // = + { 0x00, 0x41, 0x22, 0x14, 0x08 }, // > + { 0x02, 0x01, 0x51, 0x09, 0x06 }, // ? + { 0x32, 0x49, 0x79, 0x41, 0x3e }, // @ + { 0x7e, 0x11, 0x11, 0x11, 0x7e }, // A + { 0x7f, 0x49, 0x49, 0x49, 0x36 }, // B + { 0x3e, 0x41, 0x41, 0x41, 0x22 }, // C + { 0x7f, 0x41, 0x41, 0x22, 0x1c }, // D + { 0x7f, 0x49, 0x49, 0x49, 0x41 }, // E + { 0x7f, 0x09, 0x09, 0x09, 0x01 }, // F + { 0x3e, 0x41, 0x49, 0x49, 0x7a }, // G + { 0x7f, 0x08, 0x08, 0x08, 0x7f }, // H + { 0x00, 0x41, 0x7f, 0x41, 0x00 }, // I + { 0x20, 0x40, 0x41, 0x3f, 0x01 }, // J + { 0x7f, 0x08, 0x14, 0x22, 0x41 }, // K + { 0x7f, 0x40, 0x40, 0x40, 0x40 }, // L + { 0x7f, 0x02, 0x0c, 0x02, 0x7f }, // M + { 0x7f, 0x04, 0x08, 0x10, 0x7f }, // N + { 0x3e, 0x41, 0x41, 0x41, 0x3e }, // O + { 0x7f, 0x09, 0x09, 0x09, 0x06 }, // P + { 0x3e, 0x41, 0x51, 0x21, 0x5e }, // Q + { 0x7f, 0x09, 0x19, 0x29, 0x46 }, // R + { 0x46, 0x49, 0x49, 0x49, 0x31 }, // S + { 0x01, 0x01, 0x7f, 0x01, 0x01 }, // T + { 0x3f, 0x40, 0x40, 0x40, 0x3f }, // U + { 0x1f, 0x20, 0x40, 0x20, 0x1f }, // V + { 0x3f, 0x40, 0x38, 0x40, 0x3f }, // W + { 0x63, 0x14, 0x08, 0x14, 0x63 }, // X + { 0x07, 0x08, 0x70, 0x08, 0x07 }, // Y + { 0x61, 0x51, 0x49, 0x45, 0x43 }, // Z + { 0x00, 0x7f, 0x41, 0x41, 0x00 }, // [ + { 0x02, 0x04, 0x08, 0x10, 0x20 }, // "\" + { 0x00, 0x41, 0x41, 0x7f, 0x00 }, // ] + { 0x04, 0x02, 0x01, 0x02, 0x04 }, // ^ + { 0x40, 0x40, 0x40, 0x40, 0x40 }, // _ + { 0x00, 0x01, 0x02, 0x04, 0x00 }, // ` + { 0x20, 0x54, 0x54, 0x54, 0x78 }, // a + { 0x7f, 0x48, 0x44, 0x44, 0x38 }, // b + { 0x38, 0x44, 0x44, 0x44, 0x20 }, // c + { 0x38, 0x44, 0x44, 0x48, 0x7f }, // d + { 0x38, 0x54, 0x54, 0x54, 0x18 }, // e + { 0x08, 0x7e, 0x09, 0x01, 0x02 }, // f + { 0x0c, 0x52, 0x52, 0x52, 0x3e }, // g + { 0x7f, 0x08, 0x04, 0x04, 0x78 }, // h + { 0x00, 0x44, 0x7d, 0x40, 0x00 }, // i + { 0x20, 0x40, 0x44, 0x3d, 0x00 }, // j + { 0x7f, 0x10, 0x28, 0x44, 0x00 }, // k + { 0x00, 0x41, 0x7f, 0x40, 0x00 }, // l + { 0x7c, 0x04, 0x18, 0x04, 0x78 }, // m + { 0x7c, 0x08, 0x04, 0x04, 0x78 }, // n + { 0x38, 0x44, 0x44, 0x44, 0x38 }, // o + { 0x7c, 0x14, 0x14, 0x14, 0x08 }, // p + { 0x08, 0x14, 0x14, 0x18, 0x7c }, // q + { 0x7c, 0x08, 0x04, 0x04, 0x08 }, // r + { 0x48, 0x54, 0x54, 0x54, 0x20 }, // s + { 0x04, 0x3f, 0x44, 0x40, 0x20 }, // t + { 0x3c, 0x40, 0x40, 0x20, 0x7c }, // u + { 0x1c, 0x20, 0x40, 0x20, 0x1c }, // v + { 0x3c, 0x40, 0x30, 0x40, 0x3c }, // w + { 0x44, 0x28, 0x10, 0x28, 0x44 }, // x + { 0x0c, 0x50, 0x50, 0x50, 0x3c }, // y + { 0x44, 0x64, 0x54, 0x4c, 0x44 }, // z + { 0x00, 0x08, 0x36, 0x41, 0x00 }, // { + { 0x00, 0x00, 0x7f, 0x00, 0x00 }, // | + { 0x00, 0x41, 0x36, 0x08, 0x00 }, // } + { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~ + { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~ +}; + +//***************************************************************************** +// +// The sequence of commands used to initialize the SSD1329 controller. Each +// command is described as follows: there is a byte specifying the number of +// bytes in the command sequence, followed by that many bytes of command data. +// Note: This initialization sequence is derived from RIT App Note for +// the P14201. Values used are from the RIT app note, except where noted. +// +//***************************************************************************** +static const unsigned char g_pucRIT128x96x4Init[] = +{ + // + // Unlock commands + // + 3, 0xFD, 0x12, 0xe3, + + // + // Display off + // + 2, 0xAE, 0xe3, + + // + // Icon off + // + 3, 0x94, 0, 0xe3, + + // + // Multiplex ratio + // + 3, 0xA8, 95, 0xe3, + + // + // Contrast + // + 3, 0x81, 0xb7, 0xe3, + + // + // Pre-charge current + // + 3, 0x82, 0x3f, 0xe3, + + // + // Display Re-map + // + 3, 0xA0, RIT_INIT_REMAP, 0xe3, + + // + // Display Start Line + // + 3, 0xA1, 0, 0xe3, + + // + // Display Offset + // + 3, 0xA2, RIT_INIT_OFFSET, 0xe3, + + // + // Display Mode Normal + // + 2, 0xA4, 0xe3, + + // + // Phase Length + // + 3, 0xB1, 0x11, 0xe3, + + // + // Frame frequency + // + 3, 0xB2, 0x23, 0xe3, + + // + // Front Clock Divider + // + 3, 0xB3, 0xe2, 0xe3, + + // + // Set gray scale table. App note uses default command: + // 2, 0xB7, 0xe3 + // This gray scale attempts some gamma correction to reduce the + // the brightness of the low levels. + // + 17, 0xB8, 1, 2, 3, 4, 5, 6, 8, 10, 12, 14, 16, 19, 22, 26, 30, 0xe3, + + // + // Second pre-charge period. App note uses value 0x04. + // + 3, 0xBB, 0x01, 0xe3, + + // + // Pre-charge voltage + // + 3, 0xBC, 0x3f, 0xe3, + + // + // Display ON + // + 2, 0xAF, 0xe3, +}; + +//***************************************************************************** +// +//! \internal +//! +//! Write a sequence of command bytes to the SSD1329 controller. +//! +//! The data is written in a polled fashion; this function will not return +//! until the entire byte sequence has been written to the controller. +//! +//! \return None. +// +//***************************************************************************** +static void +RITWriteCommand(const unsigned char *pucBuffer, unsigned long ulCount) +{ + unsigned long ulTemp; + + // + // Return if SSI port is not enabled for RIT display. + // + if(!g_bSSIEnabled) + { + return; + } + + // + // Clear the command/control bit to enable command mode. + // + GPIOPinWrite(ulGPIOBase, ulOLEDDC_PIN, 0); + + // + // Loop while there are more bytes left to be transferred. + // + while(ulCount != 0) + { + // + // Write the next byte to the controller. + // + SSIDataPut(SSI0_BASE, *pucBuffer++); + + // + // Dummy read to drain the fifo and time the GPIO signal. + // + SSIDataGet(SSI0_BASE, &ulTemp); + + // + // Decrement the BYTE counter. + // + ulCount--; + } +} + +//***************************************************************************** +// +//! \internal +//! +//! Write a sequence of data bytes to the SSD1329 controller. +//! +//! The data is written in a polled fashion; this function will not return +//! until the entire byte sequence has been written to the controller. +//! +//! \return None. +// +//***************************************************************************** +static void +RITWriteData(const unsigned char *pucBuffer, unsigned long ulCount) +{ + unsigned long ulTemp; + + // + // Return if SSI port is not enabled for RIT display. + // + if(!g_bSSIEnabled) + { + return; + } + + // + // Set the command/control bit to enable data mode. + // + GPIOPinWrite(ulGPIOBase, ulOLEDDC_PIN, ulOLEDDC_PIN); + + // + // Loop while there are more bytes left to be transferred. + // + while(ulCount != 0) + { + // + // Write the next byte to the controller. + // + SSIDataPut(SSI0_BASE, *pucBuffer++); + + // + // Dummy read to drain the fifo and time the GPIO signal. + // + SSIDataGet(SSI0_BASE, &ulTemp); + + // + // Decrement the BYTE counter. + // + ulCount--; + } +} + +//***************************************************************************** +// +//! Clears the OLED display. +//! +//! This function will clear the display RAM. All pixels in the display will +//! be turned off. +//! +//! This function is contained in rit128x96x4.c, with +//! rit128x96x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +RIT128x96x4Clear(void) +{ + static const unsigned char pucCommand1[] = { 0x15, 0, 63 }; + static const unsigned char pucCommand2[] = { 0x75, 0, 127 }; + unsigned long ulRow, ulColumn; + + // + // Clear out the buffer used for sending bytes to the display. + *(unsigned long *)&g_pucBuffer[0] = 0; + *(unsigned long *)&g_pucBuffer[4] = 0; + + // + // Set the window to fill the entire display. + // + RITWriteCommand(pucCommand1, sizeof(pucCommand1)); + RITWriteCommand(pucCommand2, sizeof(pucCommand2)); + RITWriteCommand(g_pucRIT128x96x4HorizontalInc, + sizeof(g_pucRIT128x96x4HorizontalInc)); + + // + // Loop through the rows + // + for(ulRow = 0; ulRow < 96; ulRow++) + { + // + // Loop through the columns. Each byte is two pixels, + // and the buffer hold 8 bytes, so 16 pixels are cleared + // at a time. + // + for(ulColumn = 0; ulColumn < 128; ulColumn += 8 * 2) + { + // + // Write 8 clearing bytes to the display, which will + // clear 16 pixels across. + // + RITWriteData(g_pucBuffer, sizeof(g_pucBuffer)); + } + } +} + +//***************************************************************************** +// +//! Displays a string on the OLED display. +//! +//! \param pcStr is a pointer to the string to display. +//! \param ulX is the horizontal position to display the string, specified in +//! columns from the left edge of the display. +//! \param ulY is the vertical position to display the string, specified in +//! rows from the top edge of the display. +//! \param ucLevel is the 4-bit grey scale value to be used for displayed text. +//! +//! This function will draw a string on the display. Only the ASCII characters +//! between 32 (space) and 126 (tilde) are supported; other characters will +//! result in random data being draw on the display (based on whatever appears +//! before/after the font in memory). The font is mono-spaced, so characters +//! such as "i" and "l" have more white space around them than characters such +//! as "m" or "w". +//! +//! If the drawing of the string reaches the right edge of the display, no more +//! characters will be drawn. Therefore, special care is not required to avoid +//! supplying a string that is "too long" to display. +//! +//! This function is contained in rit128x96x4.c, with +//! rit128x96x4.h containing the API definition for use by +//! applications. +//! +//! \note Because the OLED display packs 2 pixels of data in a single byte, the +//! parameter \e ulX must be an even column number (e.g. 0, 2, 4, etc). +//! +//! \return None. +// +//***************************************************************************** +void +RIT128x96x4StringDraw(const char *pcStr, unsigned long ulX, + unsigned long ulY, unsigned char ucLevel) +{ + unsigned long ulIdx1, ulIdx2; + unsigned char ucTemp; + + // + // Check the arguments. + // + ASSERT(ulX < 128); + ASSERT((ulX & 1) == 0); + ASSERT(ulY < 96); + ASSERT(ucLevel < 16); + + // + // Setup a window starting at the specified column and row, ending + // at the right edge of the display and 8 rows down (single character row). + // + g_pucBuffer[0] = 0x15; + g_pucBuffer[1] = ulX / 2; + g_pucBuffer[2] = 63; + RITWriteCommand(g_pucBuffer, 3); + g_pucBuffer[0] = 0x75; + g_pucBuffer[1] = ulY; + g_pucBuffer[2] = ulY + 7; + RITWriteCommand(g_pucBuffer, 3); + RITWriteCommand(g_pucRIT128x96x4VerticalInc, + sizeof(g_pucRIT128x96x4VerticalInc)); + + // + // Loop while there are more characters in the string. + // + while(*pcStr != 0) + { + // + // Get a working copy of the current character and convert to an + // index into the character bit-map array. + // + ucTemp = *pcStr; + ucTemp &= 0x7F; + if(ucTemp < ' ') + { + ucTemp = ' '; + } + else + { + ucTemp -= ' '; + } + + // + // Build and display the character buffer. + // + for(ulIdx1 = 0; ulIdx1 < 3; ulIdx1++) + { + // + // Convert two columns of 1-bit font data into a single data + // byte column of 4-bit font data. + // + for(ulIdx2 = 0; ulIdx2 < 8; ulIdx2++) + { + g_pucBuffer[ulIdx2] = 0; + if(g_pucFont[ucTemp][ulIdx1*2] & (1 << ulIdx2)) + { + g_pucBuffer[ulIdx2] = ((ucLevel << 4) & 0xf0); + } + if((ulIdx1 < 2) && + (g_pucFont[ucTemp][ulIdx1*2+1] & (1 << ulIdx2))) + { + g_pucBuffer[ulIdx2] |= ((ucLevel << 0) & 0x0f); + } + } + + // + // If there is room, dump the single data byte column to the + // display. Otherwise, bail out. + // + if(ulX < 126) + { + RITWriteData(g_pucBuffer, 8); + ulX += 2; + } + else + { + return; + } + } + + // + // Advance to the next character. + // + pcStr++; + } +} + +//***************************************************************************** +// +//! Displays an image on the OLED display. +//! +//! \param pucImage is a pointer to the image data. +//! \param ulX is the horizontal position to display this image, specified in +//! columns from the left edge of the display. +//! \param ulY is the vertical position to display this image, specified in +//! rows from the top of the display. +//! \param ulWidth is the width of the image, specified in columns. +//! \param ulHeight is the height of the image, specified in rows. +//! +//! This function will display a bitmap graphic on the display. Because of the +//! format of the display RAM, the starting column (\e ulX) and the number of +//! columns (\e ulWidth) must be an integer multiple of two. +//! +//! The image data is organized with the first row of image data appearing left +//! to right, followed immediately by the second row of image data. Each byte +//! contains the data for two columns in the current row, with the leftmost +//! column being contained in bits 7:4 and the rightmost column being contained +//! in bits 3:0. +//! +//! For example, an image six columns wide and seven scan lines tall would +//! be arranged as follows (showing how the twenty one bytes of the image would +//! appear on the display): +//! +//! \verbatim +//! +-------------------+-------------------+-------------------+ +//! | Byte 0 | Byte 1 | Byte 2 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 3 | Byte 4 | Byte 5 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 6 | Byte 7 | Byte 8 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 9 | Byte 10 | Byte 11 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 12 | Byte 13 | Byte 14 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 15 | Byte 16 | Byte 17 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! | Byte 18 | Byte 19 | Byte 20 | +//! +---------+---------+---------+---------+---------+---------+ +//! | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | 7 6 5 4 | 3 2 1 0 | +//! +---------+---------+---------+---------+---------+---------+ +//! \endverbatim +//! +//! This function is contained in rit128x96x4.c, with +//! rit128x96x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +RIT128x96x4ImageDraw(const unsigned char *pucImage, unsigned long ulX, + unsigned long ulY, unsigned long ulWidth, + unsigned long ulHeight) +{ + // + // Check the arguments. + // + ASSERT(ulX < 128); + ASSERT((ulX & 1) == 0); + ASSERT(ulY < 96); + ASSERT((ulX + ulWidth) <= 128); + ASSERT((ulY + ulHeight) <= 96); + ASSERT((ulWidth & 1) == 0); + + // + // Setup a window starting at the specified column and row, and ending + // at the column + width and row+height. + // + g_pucBuffer[0] = 0x15; + g_pucBuffer[1] = ulX / 2; + g_pucBuffer[2] = (ulX + ulWidth - 2) / 2; + RITWriteCommand(g_pucBuffer, 3); + g_pucBuffer[0] = 0x75; + g_pucBuffer[1] = ulY; + g_pucBuffer[2] = ulY + ulHeight - 1; + RITWriteCommand(g_pucBuffer, 3); + RITWriteCommand(g_pucRIT128x96x4HorizontalInc, + sizeof(g_pucRIT128x96x4HorizontalInc)); + + // + // Loop while there are more rows to display. + // + while(ulHeight--) + { + // + // Write this row of image data. + // + RITWriteData(pucImage, (ulWidth / 2)); + + // + // Advance to the next row of the image. + // + pucImage += (ulWidth / 2); + } +} + +//***************************************************************************** +// +//! Enable the SSI component of the OLED display driver. +//! +//! \param ulFrequency specifies the SSI Clock Frequency to be used. +//! +//! This function initializes the SSI interface to the OLED display. +//! +//! This function is contained in rit128x96x4.c, with +//! rit128x96x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +RIT128x96x4Enable(unsigned long ulFrequency) +{ + unsigned long ulTemp; + + // + // Disable the SSI port. + // + SSIDisable(SSI0_BASE); + + // + // Configure the SSI0 port for master mode. + // + SSIConfig(SSI0_BASE, SSI_FRF_MOTO_MODE_2, SSI_MODE_MASTER, ulFrequency, 8); + + // + // (Re)Enable SSI control of the FSS pin. + // + GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_3); + GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA, + GPIO_PIN_TYPE_STD_WPU); + + // + // Enable the SSI port. + // + SSIEnable(SSI0_BASE); + + // + // Drain the receive fifo. + // + while(SSIDataNonBlockingGet(SSI0_BASE, &ulTemp) != 0) + { + } + + // + // Indicate that the RIT driver can use the SSI Port. + // + g_bSSIEnabled = true; +} + +//***************************************************************************** +// +//! Enable the SSI component of the OLED display driver. +//! +//! This function initializes the SSI interface to the OLED display. +//! +//! This function is contained in rit128x96x4.c, with +//! rit128x96x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +RIT128x96x4Disable(void) +{ + unsigned long ulTemp; + + // + // Indicate that the RIT driver can no longer use the SSI Port. + // + g_bSSIEnabled = false; + + // + // Drain the receive fifo. + // + while(SSIDataNonBlockingGet(SSI0_BASE, &ulTemp) != 0) + { + } + + // + // Disable the SSI port. + // + SSIDisable(SSI0_BASE); + + // + // Disable SSI control of the FSS pin. + // + GPIOPinTypeGPIOOutput(GPIO_PORTA_BASE, GPIO_PIN_3); + GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA, + GPIO_PIN_TYPE_STD_WPU); + GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_PIN_3); +} + +//***************************************************************************** +// +//! Initialize the OLED display. +//! +//! \param ulFrequency specifies the SSI Clock Frequency to be used. +//! +//! This function initializes the SSI interface to the OLED display and +//! configures the SSD1329 controller on the panel. +//! +//! This function is contained in rit128x96x4.c, with +//! rit128x96x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +RIT128x96x4Init(unsigned long ulFrequency) +{ + unsigned long ulIdx; + + + /* Determine which board is being used. */ + if( SysCtlPeripheralPresent( SYSCTL_PERIPH_ETH ) ) + { + /* Ethernet is present, we must be using the LM3S8962 EK. */ + ulGPIOId = LM3S8962_SYSCTL_PERIPH_GPIO_OLEDDC; + ulGPIOBase = LM3S8962_GPIO_OLEDDC_BASE; + ulOLEDDC_PIN = GPIO_PIN_6; + ulOLEDEN_PIN = GPIO_PIN_7; + } + else + { + /* Ethernet is not present, we must be using the LM3S1968 EK. */ + ulGPIOId = LM3S1968_SYSCTL_PERIPH_GPIO_OLEDDC; + ulGPIOBase = LM3S1968_GPIO_OLEDDC_BASE; + ulOLEDDC_PIN = GPIO_PIN_2; + ulOLEDEN_PIN = GPIO_PIN_3; + } + + // + // Enable the SSI0 and GPIO port blocks as they are needed by this driver. + // + SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + SysCtlPeripheralEnable(ulGPIOId); + + // + // Configure the SSI0CLK and SSIOTX pins for SSI operation. + // + GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5); + GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5, + GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD_WPU); + + // + // Configure the GPIO port pin used as a D/Cn signal for OLED device, + // and the port pin used to enable power to the OLED panel. + // + GPIOPinTypeGPIOOutput(ulGPIOBase, ulOLEDDC_PIN | ulOLEDEN_PIN); + GPIOPadConfigSet(ulGPIOBase, ulOLEDDC_PIN | ulOLEDEN_PIN, + GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD); + GPIOPinWrite(ulGPIOBase, ulOLEDDC_PIN | ulOLEDEN_PIN, + ulOLEDDC_PIN | ulOLEDEN_PIN); + + // + // Configure and enable the SSI0 port for master mode. + // + RIT128x96x4Enable(ulFrequency); + + // + // Clear the frame buffer. + // + RIT128x96x4Clear(); + + // + // Initialize the SSD1329 controller. Loop through the initialization + // sequence array, sending each command "string" to the controller. + // + for(ulIdx = 0; ulIdx < sizeof(g_pucRIT128x96x4Init); + ulIdx += g_pucRIT128x96x4Init[ulIdx] + 1) + { + // + // Send this command. + // + RITWriteCommand(g_pucRIT128x96x4Init + ulIdx + 1, + g_pucRIT128x96x4Init[ulIdx] - 1); + } +} + +//***************************************************************************** +// +//! Turns on the OLED display. +//! +//! This function will turn on the OLED display, causing it to display the +//! contents of its internal frame buffer. +//! +//! This function is contained in rit128x96x4.c, with +//! rit128x96x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +RIT128x96x4DisplayOn(void) +{ + unsigned long ulIdx; + + // + // Initialize the SSD1329 controller. Loop through the initialization + // sequence array, sending each command "string" to the controller. + // + for(ulIdx = 0; ulIdx < sizeof(g_pucRIT128x96x4Init); + ulIdx += g_pucRIT128x96x4Init[ulIdx] + 1) + { + // + // Send this command. + // + RITWriteCommand(g_pucRIT128x96x4Init + ulIdx + 1, + g_pucRIT128x96x4Init[ulIdx] - 1); + } +} + +//***************************************************************************** +// +//! Turns off the OLED display. +//! +//! This function will turn off the OLED display. This will stop the scanning +//! of the panel and turn off the on-chip DC-DC converter, preventing damage to +//! the panel due to burn-in (it has similar characters to a CRT in this +//! respect). +//! +//! This function is contained in rit128x96x4.c, with +//! rit128x96x4.h containing the API definition for use by +//! applications. +//! +//! \return None. +// +//***************************************************************************** +void +RIT128x96x4DisplayOff(void) +{ + static const unsigned char pucCommand1[] = + { + 0xAE, 0xe3 + }; + + // + // Put the display to sleep. + // + RITWriteCommand(pucCommand1, sizeof(pucCommand1)); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/settings/RTOSDemo.cspy.bat b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/settings/RTOSDemo.cspy.bat new file mode 100644 index 000000000..ac49556d8 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/settings/RTOSDemo.cspy.bat @@ -0,0 +1,32 @@ +@REM This bat file has been generated by the IAR Embeddded Workbench +@REM C-SPY interactive debugger,as an aid to preparing a command +@REM line for running the cspybat command line utility with the +@REM appropriate settings. +@REM +@REM After making some adjustments to this file, you can launch cspybat +@REM by typing the name of this file followed by the name of the debug +@REM file (usually an ubrof file). Note that this file is generated +@REM every time a new debug session is initialized, so you may want to +@REM move or rename the file before making changes. +@REM +@REM Note: some command line arguments cannot be properly generated +@REM by this process. Specifically, the plugin which is responsible +@REM for the Terminal I/O window (and other C runtime functionality) +@REM comes in a special version for cspybat, and the name of that +@REM plugin dll is not known when generating this file. It resides in +@REM the $TOOLKIT_DIR$\bin folder and is usually called XXXbat.dll or +@REM XXXlibsupportbat.dll, where XXX is the name of the corresponding +@REM tool chain. Replace the '' parameter +@REM below with the appropriate file name. Other plugins loaded by +@REM C-SPY are usually not needed by, or will not work in, cspybat +@REM but they are listed at the end of this file for reference. + + +"C:\Devtools\IAR Systems\Embedded Workbench 5.0\common\bin\cspybat" "C:\Devtools\IAR Systems\Embedded Workbench 5.0\ARM\bin\armproc.dll" "C:\Devtools\IAR Systems\Embedded Workbench 5.0\ARM\bin\armlmiftdi.dll" %1 --plugin "C:\Devtools\IAR Systems\Embedded Workbench 5.0\ARM\bin\" --backend -B "--endian" "little" "--cpu" "Cortex-M3" "--fpu" "None" "--proc_device_desc_file" "C:\Devtools\IAR Systems\Embedded Workbench 5.0\ARM\CONFIG\debugger\Luminary\iolm3sxxxx.ddf" "--drv_verify_download" "all" "--proc_no_semihosting" "--proc_driver" "lmiftdi" "--lmiftdi_speed" "500" + + +@REM Loaded plugins: +@REM armlibsupport.dll +@REM C:\Devtools\IAR Systems\Embedded Workbench 5.0\common\plugins\CodeCoverage\CodeCoverage.dll +@REM C:\Devtools\IAR Systems\Embedded Workbench 5.0\common\plugins\Profiling\Profiling.dll +@REM C:\Devtools\IAR Systems\Embedded Workbench 5.0\common\plugins\stack\stack.dll diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/settings/RTOSDemo.dbgdt b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/settings/RTOSDemo.dbgdt new file mode 100644 index 000000000..e2af7d9ee --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/settings/RTOSDemo.dbgdt @@ -0,0 +1,80 @@ + + + + + + + + 20 + 1006 + 268 + 67 + + + + + + + + 164272727 + + + + 2 + 0 + 0 + + + 1 + 0 + + + + + + + + + TabID-10465-12018 + Debug Log + Debug-Log + + + + TabID-9942-12028 + Build + Build + + + + + 0 + + + TabID-21213-12021 + Workspace + Workspace + + + RTOSDemoRTOSDemo/Demo files + + + + 0 + + + + + + TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\main.c0161695669560TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\webserver\uIP_Task.c03900TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\timertest.c09639933993TextEditorC:\E\Dev\FreeRTOS\Source\tasks.c010913621136211TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\FreeRTOSConfig.h036191519150100000010000001 + + + + + + + iaridepm.enu1debuggergui.enu1-2-2740238-2-2240200142857203666142857755601-2-21981682-2-216842001002381203666142857203666 + + + + diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/settings/RTOSDemo.dni b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/settings/RTOSDemo.dni new file mode 100644 index 000000000..462defc70 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/settings/RTOSDemo.dni @@ -0,0 +1,28 @@ +[CodeCoverage] +Enabled=_ 0 +[DisAssemblyWindow] +NumStates=_ 1 +State 1=_ 1 +[Profiling] +Enabled=0 +[StackPlugin] +Enabled=1 +OverflowWarningsEnabled=1 +WarningThreshold=90 +SpWarningsEnabled=1 +WarnHow=0 +UseTrigger=1 +TriggerName=main +LimitSize=0 +ByteLimit=50 +[Log file] +LoggingEnabled=_ 0 +LogFile=_ "" +Category=_ 0 +[TermIOLog] +LoggingEnabled=_ 0 +LogFile=_ "" +[Disassemble mode] +mode=1 +[Breakpoints] +Count=0 diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/settings/RTOSDemo.wsdt b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/settings/RTOSDemo.wsdt new file mode 100644 index 000000000..7913d1b96 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/settings/RTOSDemo.wsdt @@ -0,0 +1,49 @@ + + + + + + RTOSDemo/Debug + + + + + + + + + 304272727 + + 4826882619100726867 + + + + + + TabID-18883-22024 + Workspace + Workspace + + + RTOSDemo + + + + 0TabID-29040-7360Find in FilesFind-in-FilesTabID-19024-10413BuildBuild1 + + + + + + TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\main.c0161695669560TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\webserver\uIP_Task.c03900TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\timertest.c09639933993TextEditorC:\E\Dev\FreeRTOS\Source\tasks.c010913621136211TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\FreeRTOSConfig.h036191519150100000010000001 + + + + + + + iaridepm.enu1-2-2613378-2-2240200142857203666226190626273-2-23251682-2-216843271002381332994142857203666 + + + + diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/startup_ewarm.c b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/startup_ewarm.c new file mode 100644 index 000000000..3279be441 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/startup_ewarm.c @@ -0,0 +1,212 @@ +//***************************************************************************** +// +// startup_ewarm.c - Boot code for Stellaris. +// +// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 100 of the Stellaris Ethernet +// Applications Library. +// +//***************************************************************************** + +//***************************************************************************** +// +// Enable the IAR extensions for this source file. +// +//***************************************************************************** +#pragma language=extended + +//***************************************************************************** +// +// Forward declaration of the default fault handlers. +// +//***************************************************************************** +static void NmiSR(void); +static void FaultISR(void); +static void IntDefaultHandler(void); + +//***************************************************************************** +// +// External declaration for the interrupt handler used by the application. +// +//***************************************************************************** + + +//***************************************************************************** +// +// The entry point for the application. +// +//***************************************************************************** +extern void __iar_program_start(void); +extern void xPortPendSVHandler(void); +extern void xPortSysTickHandler(void); +extern void vEMAC_ISR( void ); +extern Timer0IntHandler( void ); + +//***************************************************************************** +// +// Reserve space for the system stack. +// +//***************************************************************************** +#ifndef STACK_SIZE +#define STACK_SIZE 64 +#endif +static unsigned long pulStack[STACK_SIZE] @ ".noinit"; + +//***************************************************************************** +// +// A union that describes the entries of the vector table. The union is needed +// since the first entry is the stack pointer and the remainder are function +// pointers. +// +//***************************************************************************** +typedef union +{ + void (*pfnHandler)(void); + unsigned long ulPtr; +} +uVectorEntry; + +//***************************************************************************** +// +// The minimal vector table for a Cortex M3. Note that the proper constructs +// must be placed on this to ensure that it ends up at physical address +// 0x0000.0000. +// +//***************************************************************************** +__root const uVectorEntry __vector_table[] @ ".intvec" = +{ + { .ulPtr = (unsigned long)pulStack + sizeof(pulStack) }, + // The initial stack pointer + __iar_program_start, // The reset handler + NmiSR, // The NMI handler + FaultISR, // The hard fault handler + IntDefaultHandler, // The MPU fault handler + IntDefaultHandler, // The bus fault handler + IntDefaultHandler, // The usage fault handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + IntDefaultHandler, // SVCall handler + IntDefaultHandler, // Debug monitor handler + 0, // Reserved + xPortPendSVHandler, // The PendSV handler + xPortSysTickHandler, // The SysTick handler + IntDefaultHandler, // GPIO Port A + IntDefaultHandler, // GPIO Port B + IntDefaultHandler, // GPIO Port C + IntDefaultHandler, // GPIO Port D + IntDefaultHandler, // GPIO Port E + IntDefaultHandler, // UART0 Rx and Tx + IntDefaultHandler, // UART1 Rx and Tx + IntDefaultHandler, // SSI Rx and Tx + IntDefaultHandler, // I2C Master and Slave + IntDefaultHandler, // PWM Fault + IntDefaultHandler, // PWM Generator 0 + IntDefaultHandler, // PWM Generator 1 + IntDefaultHandler, // PWM Generator 2 + IntDefaultHandler, // Quadrature Encoder + IntDefaultHandler, // ADC Sequence 0 + IntDefaultHandler, // ADC Sequence 1 + IntDefaultHandler, // ADC Sequence 2 + IntDefaultHandler, // ADC Sequence 3 + IntDefaultHandler, // Watchdog timer + Timer0IntHandler, // Timer 0 subtimer A + IntDefaultHandler, // Timer 0 subtimer B + IntDefaultHandler, // Timer 1 subtimer A + IntDefaultHandler, // Timer 1 subtimer B + IntDefaultHandler, // Timer 2 subtimer A + IntDefaultHandler, // Timer 2 subtimer B + IntDefaultHandler, // Analog Comparator 0 + IntDefaultHandler, // Analog Comparator 1 + IntDefaultHandler, // Analog Comparator 2 + IntDefaultHandler, // System Control (PLL, OSC, BO) + IntDefaultHandler, // FLASH Control + IntDefaultHandler, // GPIO Port F + IntDefaultHandler, // GPIO Port G + IntDefaultHandler, // GPIO Port H + IntDefaultHandler, // UART2 Rx and Tx + IntDefaultHandler, // SSI1 Rx and Tx + IntDefaultHandler, // Timer 3 subtimer A + IntDefaultHandler, // Timer 3 subtimer B + IntDefaultHandler, // I2C1 Master and Slave + IntDefaultHandler, // Quadrature Encoder 1 + IntDefaultHandler, // CAN0 + IntDefaultHandler, // CAN1 + IntDefaultHandler, // CAN2 + vEMAC_ISR, // Ethernet + IntDefaultHandler // Power Island +}; + + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a NMI. This +// simply enters an infinite loop, preserving the system state for examination +// by a debugger. +// +//***************************************************************************** +static void +NmiSR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a fault +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +FaultISR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives an unexpected +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +static void +IntDefaultHandler(void) +{ + // + // Go into an infinite loop. + // + while(1) + { + } +} diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/startup_rvmdk.S b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/startup_rvmdk.S new file mode 100644 index 000000000..ddedd9af5 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/startup_rvmdk.S @@ -0,0 +1,248 @@ +; <<< Use Configuration Wizard in Context Menu >>> +;****************************************************************************** +; +; startup_rvmdk.S - Startup code for use with Keil's uVision. +; +; Copyright (c) 2007 Luminary Micro, Inc. All rights reserved. +; +; Software License Agreement +; +; Luminary Micro, Inc. (LMI) is supplying this software for use solely and +; exclusively on LMI's microcontroller products. +; +; The software is owned by LMI and/or its suppliers, and is protected under +; applicable copyright laws. All rights are reserved. Any use in violation +; of the foregoing restrictions may subject the user to criminal sanctions +; under applicable laws, as well as to civil liability for the breach of the +; terms and conditions of this license. +; +; THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; +; This is part of revision 1408 of the Stellaris Peripheral Driver Library. +; +;****************************************************************************** + +;****************************************************************************** +; +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; +;****************************************************************************** +Stack EQU 0x00000800 + +;****************************************************************************** +; +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; +;****************************************************************************** +Heap EQU 0x00000000 + +;****************************************************************************** +; +; Allocate space for the stack. +; +;****************************************************************************** + AREA STACK, NOINIT, READWRITE, ALIGN=3 +StackMem + SPACE Stack +__initial_sp + +;****************************************************************************** +; +; Allocate space for the heap. +; +;****************************************************************************** + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +HeapMem + SPACE Heap +__heap_limit + +;****************************************************************************** +; +; Indicate that the code in this file preserves 8-byte alignment of the stack. +; +;****************************************************************************** + PRESERVE8 + +;****************************************************************************** +; +; Place code into the reset code section. +; +;****************************************************************************** + AREA RESET, CODE, READONLY + THUMB + +;****************************************************************************** +; +; The vector table. +; +;****************************************************************************** + EXPORT __Vectors +__Vectors + DCD StackMem + Stack ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NmiSR ; NMI Handler + DCD FaultISR ; Hard Fault Handler + DCD IntDefaultHandler ; MPU Fault Handler + DCD IntDefaultHandler ; Bus Fault Handler + DCD IntDefaultHandler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD IntDefaultHandler ; SVCall Handler + DCD IntDefaultHandler ; Debug Monitor Handler + DCD 0 ; Reserved + EXTERN xPortPendSVHandler + DCD xPortPendSVHandler ; PendSV Handler + EXTERN xPortSysTickHandler + DCD xPortSysTickHandler ; SysTick Handler + DCD IntDefaultHandler ; GPIO Port A + DCD IntDefaultHandler ; GPIO Port B + DCD IntDefaultHandler ; GPIO Port C + DCD IntDefaultHandler ; GPIO Port D + DCD IntDefaultHandler ; GPIO Port E + DCD IntDefaultHandler ; UART0 + DCD IntDefaultHandler ; UART1 + DCD IntDefaultHandler ; SSI + DCD IntDefaultHandler ; I2C + DCD IntDefaultHandler ; PWM Fault + DCD IntDefaultHandler ; PWM Generator 0 + DCD IntDefaultHandler ; PWM Generator 1 + DCD IntDefaultHandler ; PWM Generator 2 + DCD IntDefaultHandler ; Quadrature Encoder + DCD IntDefaultHandler ; ADC Sequence 0 + DCD IntDefaultHandler ; ADC Sequence 1 + DCD IntDefaultHandler ; ADC Sequence 2 + DCD IntDefaultHandler ; ADC Sequence 3 + DCD IntDefaultHandler ; Watchdog + EXTERN Timer0IntHandler + DCD Timer0IntHandler ; Timer 0A + DCD IntDefaultHandler ; Timer 0B + DCD IntDefaultHandler ; Timer 1A + DCD IntDefaultHandler ; Timer 1B + DCD IntDefaultHandler ; Timer 2A + DCD IntDefaultHandler ; Timer 2B + DCD IntDefaultHandler ; Comp 0 + DCD IntDefaultHandler ; Comp 1 + DCD IntDefaultHandler ; Comp 2 + DCD IntDefaultHandler ; System Control + DCD IntDefaultHandler ; Flash Control + DCD IntDefaultHandler ; GPIO Port F + DCD IntDefaultHandler ; GPIO Port G + DCD IntDefaultHandler ; GPIO Port H + DCD IntDefaultHandler ; UART2 Rx and Tx + DCD IntDefaultHandler ; SSI1 Rx and Tx + DCD IntDefaultHandler ; Timer 3 subtimer A + DCD IntDefaultHandler ; Timer 3 subtimer B + DCD IntDefaultHandler ; I2C1 Master and Slave + DCD IntDefaultHandler ; Quadrature Encoder 1 + DCD IntDefaultHandler ; CAN0 + DCD IntDefaultHandler ; CAN1 + DCD 0 ; Reserved + EXTERN vEMAC_ISR + DCD vEMAC_ISR ; Ethernet + DCD IntDefaultHandler ; Hibernate + +;****************************************************************************** +; +; This is the code that gets called when the processor first starts execution +; following a reset event. +; +;****************************************************************************** + EXPORT Reset_Handler +Reset_Handler + ; + ; Call the C library enty point that handles startup. This will copy + ; the .data section initializers from flash to SRAM and zero fill the + ; .bss section. It will then call __rt_entry, which will be either the + ; C library version or the one supplied here depending on the + ; configured startup type. + ; + IMPORT __main + B __main + +;****************************************************************************** +; +; This is the code that gets called when the processor receives a NMI. This +; simply enters an infinite loop, preserving the system state for examination +; by a debugger. +; +;****************************************************************************** +NmiSR + B NmiSR + +;****************************************************************************** +; +; This is the code that gets called when the processor receives a fault +; interrupt. This simply enters an infinite loop, preserving the system state +; for examination by a debugger. +; +;****************************************************************************** +FaultISR + B FaultISR + +;****************************************************************************** +; +; This is the code that gets called when the processor receives an unexpected +; interrupt. This simply enters an infinite loop, preserving the system state +; for examination by a debugger. +; +;****************************************************************************** +IntDefaultHandler + B IntDefaultHandler + +;****************************************************************************** +; +; Make sure the end of this section is aligned. +; +;****************************************************************************** + ALIGN + +;****************************************************************************** +; +; Some code in the normal code section for initializing the heap and stack. +; +;****************************************************************************** + AREA |.text|, CODE, READONLY + +;****************************************************************************** +; +; The function expected of the C library startup code for defining the stack +; and heap memory locations. For the C library version of the startup code, +; provide this function so that the C library initialization code can find out +; the location of the stack and heap. +; +;****************************************************************************** + IF :DEF: __MICROLIB + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + ELSE + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + LDR R0, =HeapMem + LDR R1, =(StackMem + Stack) + LDR R2, =(HeapMem + Heap) + LDR R3, =StackMem + BX LR + ENDIF + +;****************************************************************************** +; +; Make sure the end of this section is aligned. +; +;****************************************************************************** + ALIGN + +;****************************************************************************** +; +; Tell the assembler that we're done. +; +;****************************************************************************** + END diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/timertest.c b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/timertest.c new file mode 100644 index 000000000..143ab9a16 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/timertest.c @@ -0,0 +1,144 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* High speed timer test as described in main.c. */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* Library includes. */ +#include "hw_ints.h" +#include "hw_memmap.h" +#include "hw_types.h" +#include "interrupt.h" +#include "sysctl.h" +#include "lmi_timer.h" + +/* The set frequency of the interrupt. Deviations from this are measured as +the jitter. */ +#define timerINTERRUPT_FREQUENCY ( 20000UL ) + +/* The expected time between each of the timer interrupts - if the jitter was +zero. */ +#define timerEXPECTED_DIFFERENCE_VALUE ( configCPU_CLOCK_HZ / timerINTERRUPT_FREQUENCY ) + +/* The highest available interrupt priority. */ +#define timerHIGHEST_PRIORITY ( 0 ) + +/* Misc defines. */ +#define timerMAX_32BIT_VALUE ( 0xffffffffUL ) +#define timerTIMER_1_COUNT_VALUE ( * ( ( unsigned long * ) ( TIMER1_BASE + 0x48 ) ) ) + +/*-----------------------------------------------------------*/ + +/* Interrupt handler in which the jitter is measured. */ +void Timer0IntHandler( void ); + +/* Stores the value of the maximum recorded jitter between interrupts. */ +volatile unsigned portLONG ulMaxJitter = 0; + +/*-----------------------------------------------------------*/ + +void vSetupTimer( void ) +{ +unsigned long ulFrequency; + + /* Timer zero is used to generate the interrupts, and timer 1 is used + to measure the jitter. */ + SysCtlPeripheralEnable( SYSCTL_PERIPH_TIMER0 ); + SysCtlPeripheralEnable( SYSCTL_PERIPH_TIMER1 ); + TimerConfigure( TIMER0_BASE, TIMER_CFG_32_BIT_PER ); + TimerConfigure( TIMER1_BASE, TIMER_CFG_32_BIT_PER ); + + /* Set the timer interrupt to be above the kernel - highest. */ + IntPrioritySet( INT_TIMER0A, timerHIGHEST_PRIORITY ); + + /* Just used to measure time. */ + TimerLoadSet(TIMER1_BASE, TIMER_A, timerMAX_32BIT_VALUE ); + + /* Ensure interrupts do not start until the scheduler is running. */ + portDISABLE_INTERRUPTS(); + + /* The rate at which the timer will interrupt. */ + ulFrequency = configCPU_CLOCK_HZ / timerINTERRUPT_FREQUENCY; + TimerLoadSet( TIMER0_BASE, TIMER_A, ulFrequency ); + IntEnable( INT_TIMER0A ); + TimerIntEnable( TIMER0_BASE, TIMER_TIMA_TIMEOUT ); + + /* Enable both timers. */ + TimerEnable( TIMER0_BASE, TIMER_A ); + TimerEnable( TIMER1_BASE, TIMER_A ); +} +/*-----------------------------------------------------------*/ + +void Timer0IntHandler( void ) +{ +unsigned portLONG ulDifference; +volatile unsigned portLONG ulCurrentCount; +static portLONG ulMaxDifference = 0, ulLastCount = 0; + + /* We use the timer 1 counter value to measure the clock cycles between + the timer 0 interrupts. */ + ulCurrentCount = timerTIMER_1_COUNT_VALUE; + + if( ulCurrentCount < ulLastCount ) + { + /* How many times has timer 1 counted since the last interrupt? */ + ulDifference = ulLastCount - ulCurrentCount; + + /* Is this the largest difference we have measured yet? */ + if( ulDifference > ulMaxDifference ) + { + ulMaxDifference = ulDifference; + ulMaxJitter = ulMaxDifference - timerEXPECTED_DIFFERENCE_VALUE; + } + } + + ulLastCount = ulCurrentCount; + + TimerIntClear( TIMER0_BASE, TIMER_TIMA_TIMEOUT ); +} + + + + + diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/Makefile.webserver b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/Makefile.webserver new file mode 100644 index 000000000..f38c47a72 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/Makefile.webserver @@ -0,0 +1 @@ +APP_SOURCES += httpd.c http-strings.c httpd-fs.c httpd-cgi.c diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/clock-arch.h b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/clock-arch.h new file mode 100644 index 000000000..cde657b62 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/clock-arch.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2006, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: clock-arch.h,v 1.2 2006/06/12 08:00:31 adam Exp $ + */ + +#ifndef __CLOCK_ARCH_H__ +#define __CLOCK_ARCH_H__ + +#include "FreeRTOS.h" + +typedef unsigned long clock_time_t; +#define CLOCK_CONF_SECOND configTICK_RATE_HZ + +#endif /* __CLOCK_ARCH_H__ */ diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/emac.c b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/emac.c new file mode 100644 index 000000000..380928cb1 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/emac.c @@ -0,0 +1,281 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "Semphr.h" +#include "task.h" + +/* Demo includes. */ +#include "EMAC.h" + +/* uIP includes. */ +#include "uip.h" + +/* Hardware library includes. */ +#include "hw_types.h" +#include "hw_memmap.h" +#include "hw_ints.h" +#include "hw_ethernet.h" +#include "ethernet.h" +#include "interrupt.h" + +#define emacNUM_RX_BUFFERS 5 +#define emacFRAM_SIZE_BYTES 2 +#define macNEGOTIATE_DELAY 2000 +#define macWAIT_SEND_TIME ( 10 ) + +/* The task that handles the MAC peripheral. This is created at a high +priority and is effectively a deferred interrupt handler. The peripheral +handling is deferred to a task to prevent the entire FIFO having to be read +from within an ISR. */ +void vMACHandleTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* The semaphore used to wake the uIP task when data arrives. */ +xSemaphoreHandle xEMACSemaphore = NULL; + +/* The semaphore used to wake the interrupt handler task. The peripheral +is processed at the task level to prevent the need to read the entire FIFO from +within the ISR itself. */ +xSemaphoreHandle xMACInterruptSemaphore = NULL; + +/* The buffer used by the uIP stack. In this case the pointer is used to +point to one of the Rx buffers. */ +unsigned portCHAR *uip_buf; + +/* Buffers into which Rx data is placed. */ +static unsigned portCHAR ucRxBuffers[ emacNUM_RX_BUFFERS ][ UIP_BUFSIZE + ( 4 * emacFRAM_SIZE_BYTES ) ]; + +/* The length of the data within each of the Rx buffers. */ +static unsigned portLONG ulRxLength[ emacNUM_RX_BUFFERS ]; + +/* Used to keep a track of the number of bytes to transmit. */ +static unsigned portLONG ulNextTxSpace; + +/*-----------------------------------------------------------*/ + +portBASE_TYPE vInitEMAC( void ) +{ +unsigned long ulTemp; +portBASE_TYPE xReturn; + + /* Ensure all interrupts are disabled. */ + EthernetIntDisable( ETH_BASE, ( ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER | ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER | ETH_INT_RX)); + + /* Clear any interrupts that were already pending. */ + ulTemp = EthernetIntStatus( ETH_BASE, pdFALSE ); + EthernetIntClear( ETH_BASE, ulTemp ); + + /* Initialise the MAC and connect. */ + EthernetInit( ETH_BASE ); + EthernetConfigSet( ETH_BASE, ( ETH_CFG_TX_DPLXEN | ETH_CFG_TX_CRCEN | ETH_CFG_TX_PADEN ) ); + EthernetEnable( ETH_BASE ); + + /* Mark each Rx buffer as empty. */ + for( ulTemp = 0; ulTemp < emacNUM_RX_BUFFERS; ulTemp++ ) + { + ulRxLength[ ulTemp ] = 0; + } + + /* Create the queue and task used to defer the MAC processing to the + task level. */ + vSemaphoreCreateBinary( xMACInterruptSemaphore ); + xSemaphoreTake( xMACInterruptSemaphore, 0 ); + xReturn = xTaskCreate( vMACHandleTask, ( signed portCHAR * ) "MAC", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL ); + vTaskDelay( macNEGOTIATE_DELAY ); + + /* We are only interested in Rx interrupts. */ + IntPrioritySet( INT_ETH, configKERNEL_INTERRUPT_PRIORITY ); + IntEnable( INT_ETH ); + EthernetIntEnable(ETH_BASE, ETH_INT_RX); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +unsigned int uiGetEMACRxData( unsigned char *ucBuffer ) +{ +static unsigned long ulNextRxBuffer = 0; +unsigned int iLen; + + iLen = ulRxLength[ ulNextRxBuffer ]; + + if( iLen != 0 ) + { + /* Leave room for the size at the start of the buffer. */ + uip_buf = &( ucRxBuffers[ ulNextRxBuffer ][ 2 ] ); + + ulRxLength[ ulNextRxBuffer ] = 0; + + ulNextRxBuffer++; + if( ulNextRxBuffer >= emacNUM_RX_BUFFERS ) + { + ulNextRxBuffer = 0; + } + } + + return iLen; +} +/*-----------------------------------------------------------*/ + +void vInitialiseSend( void ) +{ + /* Set the index to the first byte to send - skipping over the size + bytes. */ + ulNextTxSpace = 2; +} +/*-----------------------------------------------------------*/ + +void vIncrementTxLength( unsigned portLONG ulLength ) +{ + ulNextTxSpace += ulLength; +} +/*-----------------------------------------------------------*/ + +void vSendBufferToMAC( void ) +{ +unsigned long *pulSource; +unsigned portSHORT * pus; +unsigned portLONG ulNextWord; + + /* Locate the data to be send. */ + pus = ( unsigned portSHORT * ) uip_buf; + + /* Add in the size of the data. */ + pus--; + *pus = ulNextTxSpace; + + /* Wait for data to be sent if there is no space immediately. */ + while( !EthernetSpaceAvail( ETH_BASE ) ) + { + vTaskDelay( macWAIT_SEND_TIME ); + } + + pulSource = ( unsigned portLONG * ) pus; + + for( ulNextWord = 0; ulNextWord < ulNextTxSpace; ulNextWord += sizeof( unsigned portLONG ) ) + { + HWREG(ETH_BASE + MAC_O_DATA) = *pulSource; + pulSource++; + } + + /* Go. */ + HWREG( ETH_BASE + MAC_O_TR ) = MAC_TR_NEWTX; +} +/*-----------------------------------------------------------*/ + +void vEMAC_ISR( void ) +{ +portBASE_TYPE xSwitchRequired = pdFALSE; +unsigned portLONG ulTemp; + + /* Clear the interrupt. */ + ulTemp = EthernetIntStatus( ETH_BASE, pdFALSE ); + EthernetIntClear( ETH_BASE, ulTemp ); + + /* Was it an Rx interrupt? */ + if( ulTemp & ETH_INT_RX ) + { + xSwitchRequired = pdTRUE; + xSemaphoreGiveFromISR( xMACInterruptSemaphore, pdFALSE ); + EthernetIntDisable( ETH_BASE, ETH_INT_RX ); + } + + /* Switch to the uIP task. */ + portEND_SWITCHING_ISR( xSwitchRequired ); +} +/*-----------------------------------------------------------*/ + +void vMACHandleTask( void *pvParameters ) +{ +unsigned long ulLen = 0, i; +unsigned portLONG ulLength, ulInt; +unsigned long *pulBuffer; +static unsigned portLONG ulNextRxBuffer = 0; +portBASE_TYPE xSwitchRequired = pdFALSE; + + for( ;; ) + { + /* Wait for something to do. */ + xSemaphoreTake( xMACInterruptSemaphore, portMAX_DELAY ); + + while( ( ulInt = ( EthernetIntStatus( ETH_BASE, pdFALSE ) & ETH_INT_RX ) ) != 0 ) + { + ulLength = HWREG( ETH_BASE + MAC_O_DATA ); + + /* Leave room at the start of the buffer for the size. */ + pulBuffer = ( unsigned long * ) &( ucRxBuffers[ ulNextRxBuffer ][ 2 ] ); + *pulBuffer = ( ulLength >> 16 ); + + /* Get the size of the data. */ + pulBuffer = ( unsigned long * ) &( ucRxBuffers[ ulNextRxBuffer ][ 4 ] ); + ulLength &= 0xFFFF; + + if( ulLength > 4 ) + { + ulLength -= 4; + + if( ulLength >= UIP_BUFSIZE ) + { + /* The data won't fit in our buffer. Ensure we don't + try to write into the buffer. */ + ulLength = 0; + } + + /* Read out the data into our buffer. */ + for( i = 0; i < ulLength; i += sizeof( unsigned portLONG ) ) + { + *pulBuffer = HWREG( ETH_BASE + MAC_O_DATA ); + pulBuffer++; + } + + /* Store the length of the data into the separate array. */ + ulRxLength[ ulNextRxBuffer ] = ulLength; + + /* Use the next buffer the next time through. */ + ulNextRxBuffer++; + if( ulNextRxBuffer >= emacNUM_RX_BUFFERS ) + { + ulNextRxBuffer = 0; + } + + /* Ensure the uIP task is not blocked as data has arrived. */ + xSemaphoreGive( xEMACSemaphore ); + } + } + + EthernetIntEnable( ETH_BASE, ETH_INT_RX ); + } +} + diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/emac.h b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/emac.h new file mode 100644 index 000000000..a49b59828 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/emac.h @@ -0,0 +1,322 @@ +/*---------------------------------------------------------------------------- + * LPC2378 Ethernet Definitions + *---------------------------------------------------------------------------- + * Name: EMAC.H + * Purpose: Philips LPC2378 EMAC hardware definitions + *---------------------------------------------------------------------------- + * Copyright (c) 2006 KEIL - An ARM Company. All rights reserved. + *---------------------------------------------------------------------------*/ +#ifndef __EMAC_H +#define __EMAC_H + +/* MAC address definition. The MAC address must be unique on the network. */ +#define emacETHADDR0 0 +#define emacETHADDR1 0xbd +#define emacETHADDR2 0x33 +#define emacETHADDR3 0x02 +#define emacETHADDR4 0x64 +#define emacETHADDR5 0x24 + + +/* EMAC Memory Buffer configuration for 16K Ethernet RAM. */ +#define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */ +#define NUM_TX_FRAG 2 /* Num.of TX Fragments 2*1536= 3.0kB */ +#define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */ + +#define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */ + +/* EMAC variables located in 16K Ethernet SRAM */ +#define RX_DESC_BASE 0x7FE00000 +#define RX_STAT_BASE (RX_DESC_BASE + NUM_RX_FRAG*8) +#define TX_DESC_BASE (RX_STAT_BASE + NUM_RX_FRAG*8) +#define TX_STAT_BASE (TX_DESC_BASE + NUM_TX_FRAG*8) +#define RX_BUF_BASE (TX_STAT_BASE + NUM_TX_FRAG*4) +#define TX_BUF_BASE (RX_BUF_BASE + NUM_RX_FRAG*ETH_FRAG_SIZE) + +/* RX and TX descriptor and status definitions. */ +#define RX_DESC_PACKET(i) (*(unsigned int *)(RX_DESC_BASE + 8*i)) +#define RX_DESC_CTRL(i) (*(unsigned int *)(RX_DESC_BASE+4 + 8*i)) +#define RX_STAT_INFO(i) (*(unsigned int *)(RX_STAT_BASE + 8*i)) +#define RX_STAT_HASHCRC(i) (*(unsigned int *)(RX_STAT_BASE+4 + 8*i)) +#define TX_DESC_PACKET(i) (*(unsigned int *)(TX_DESC_BASE + 8*i)) +#define TX_DESC_CTRL(i) (*(unsigned int *)(TX_DESC_BASE+4 + 8*i)) +#define TX_STAT_INFO(i) (*(unsigned int *)(TX_STAT_BASE + 4*i)) +#define RX_BUF(i) (RX_BUF_BASE + ETH_FRAG_SIZE*i) +#define TX_BUF(i) (TX_BUF_BASE + ETH_FRAG_SIZE*i) + +/* MAC Configuration Register 1 */ +#define MAC1_REC_EN 0x00000001 /* Receive Enable */ +#define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */ +#define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */ +#define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */ +#define MAC1_LOOPB 0x00000010 /* Loop Back Mode */ +#define MAC1_RES_TX 0x00000100 /* Reset TX Logic */ +#define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */ +#define MAC1_RES_RX 0x00000400 /* Reset RX Logic */ +#define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */ +#define MAC1_SIM_RES 0x00004000 /* Simulation Reset */ +#define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */ + +/* MAC Configuration Register 2 */ +#define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */ +#define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */ +#define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */ +#define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */ +#define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */ +#define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */ +#define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */ +#define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */ +#define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */ +#define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */ +#undef MAC2_NO_BACKOFF /* Remove compiler warning. */ +#define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */ +#define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */ +#define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */ + +/* Back-to-Back Inter-Packet-Gap Register */ +#define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */ +#define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */ + +/* Non Back-to-Back Inter-Packet-Gap Register */ +#define IPGR_DEF 0x00000012 /* Recommended value */ + +/* Collision Window/Retry Register */ +#define CLRT_DEF 0x0000370F /* Default value */ + +/* PHY Support Register */ +#undef SUPP_SPEED /* Remove compiler warning. */ +#define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */ +#define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */ + +/* Test Register */ +#define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */ +#define TEST_TST_PAUSE 0x00000002 /* Test Pause */ +#define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */ + +/* MII Management Configuration Register */ +#define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */ +#define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */ +#define MCFG_CLK_SEL 0x0000001C /* Clock Select Mask */ +#define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */ + +/* MII Management Command Register */ +#undef MCMD_READ /* Remove compiler warning. */ +#define MCMD_READ 0x00000001 /* MII Read */ +#undef MCMD_SCAN /* Remove compiler warning. */ +#define MCMD_SCAN 0x00000002 /* MII Scan continuously */ + +#define MII_WR_TOUT 0x00050000 /* MII Write timeout count */ +#define MII_RD_TOUT 0x00050000 /* MII Read timeout count */ + +/* MII Management Address Register */ +#define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */ +#define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */ + +/* MII Management Indicators Register */ +#undef MIND_BUSY /* Remove compiler warning. */ +#define MIND_BUSY 0x00000001 /* MII is Busy */ +#define MIND_SCAN 0x00000002 /* MII Scanning in Progress */ +#define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */ +#define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */ + +/* Command Register */ +#define CR_RX_EN 0x00000001 /* Enable Receive */ +#define CR_TX_EN 0x00000002 /* Enable Transmit */ +#define CR_REG_RES 0x00000008 /* Reset Host Registers */ +#define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */ +#define CR_RX_RES 0x00000020 /* Reset Receive Datapath */ +#define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */ +#define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */ +#define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */ +#define CR_RMII 0x00000200 /* Reduced MII Interface */ +#define CR_FULL_DUP 0x00000400 /* Full Duplex */ + +/* Status Register */ +#define SR_RX_EN 0x00000001 /* Enable Receive */ +#define SR_TX_EN 0x00000002 /* Enable Transmit */ + +/* Transmit Status Vector 0 Register */ +#define TSV0_CRC_ERR 0x00000001 /* CRC error */ +#define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */ +#define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */ +#define TSV0_DONE 0x00000008 /* Tramsmission Completed */ +#define TSV0_MCAST 0x00000010 /* Multicast Destination */ +#define TSV0_BCAST 0x00000020 /* Broadcast Destination */ +#define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */ +#define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */ +#define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */ +#define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */ +#define TSV0_GIANT 0x00000400 /* Giant Frame */ +#define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */ +#define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */ +#define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */ +#define TSV0_PAUSE 0x20000000 /* Pause Frame */ +#define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */ +#define TSV0_VLAN 0x80000000 /* VLAN Frame */ + +/* Transmit Status Vector 1 Register */ +#define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */ +#define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */ + +/* Receive Status Vector Register */ +#define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */ +#define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */ +#define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */ +#define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */ +#define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */ +#define RSV_CRC_ERR 0x00100000 /* CRC Error */ +#define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */ +#define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */ +#define RSV_REC_OK 0x00800000 /* Frame Received OK */ +#define RSV_MCAST 0x01000000 /* Multicast Frame */ +#define RSV_BCAST 0x02000000 /* Broadcast Frame */ +#define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */ +#define RSV_CTRL_FRAME 0x08000000 /* Control Frame */ +#define RSV_PAUSE 0x10000000 /* Pause Frame */ +#define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */ +#define RSV_VLAN 0x40000000 /* VLAN Frame */ + +/* Flow Control Counter Register */ +#define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */ +#define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */ + +/* Flow Control Status Register */ +#define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */ + +/* Receive Filter Control Register */ +#define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */ +#define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */ +#define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */ +#define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */ +#define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/ +#define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */ +#define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */ +#define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */ + +/* Receive Filter WoL Status/Clear Registers */ +#define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */ +#define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */ +#define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */ +#define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */ +#define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */ +#define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */ +#define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */ +#define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */ + +/* Interrupt Status/Enable/Clear/Set Registers */ +#define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */ +#define INT_RX_ERR 0x00000002 /* Receive Error */ +#define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */ +#define INT_RX_DONE 0x00000008 /* Receive Done */ +#define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */ +#define INT_TX_ERR 0x00000020 /* Transmit Error */ +#define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */ +#define INT_TX_DONE 0x00000080 /* Transmit Done */ +#define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */ +#define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */ + +/* Power Down Register */ +#define PD_POWER_DOWN 0x80000000 /* Power Down MAC */ + +/* RX Descriptor Control Word */ +#define RCTRL_SIZE 0x000007FF /* Buffer size mask */ +#define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */ + +/* RX Status Hash CRC Word */ +#define RHASH_SA 0x000001FF /* Hash CRC for Source Address */ +#define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */ + +/* RX Status Information Word */ +#define RINFO_SIZE 0x000007FF /* Data size in bytes */ +#define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */ +#define RINFO_VLAN 0x00080000 /* VLAN Frame */ +#define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */ +#define RINFO_MCAST 0x00200000 /* Multicast Frame */ +#define RINFO_BCAST 0x00400000 /* Broadcast Frame */ +#define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */ +#define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */ +#define RINFO_LEN_ERR 0x02000000 /* Length Error */ +#define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */ +#define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */ +#define RINFO_OVERRUN 0x10000000 /* Receive overrun */ +#define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */ +#define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */ +#define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ + +#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | \ + RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN) + +/* TX Descriptor Control Word */ +#define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */ +#define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */ +#define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */ +#define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */ +#define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */ +#define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */ +#define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */ + +/* TX Status Information Word */ +#define TINFO_COL_CNT 0x01E00000 /* Collision Count */ +#define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */ +#define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */ +#define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */ +#define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */ +#define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */ +#define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */ +#define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ + +/* DP83848C PHY Registers */ +#define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */ +#define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */ +#define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */ +#define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */ +#define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */ +#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */ +#define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */ +#define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */ + +/* PHY Extended Registers */ +#define PHY_REG_STS 0x10 /* Status Register */ +#define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */ +#define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */ +#define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */ +#define PHY_REG_RECR 0x15 /* Receive Error Counter */ +#define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */ +#define PHY_REG_RBR 0x17 /* RMII and Bypass Register */ +#define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */ +#define PHY_REG_PHYCR 0x19 /* PHY Control Register */ +#define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */ +#define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */ +#define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */ + +#define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */ +#define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */ +#define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */ +#define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */ +#define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */ + +#define DP83848C_DEF_ADR 0x0100 /* Default PHY device address */ +#define DP83848C_ID 0x20005C90 /* PHY Identifier */ + +// prototypes +portBASE_TYPE vInitEMAC(void); +unsigned short ReadFrameBE_EMAC(void); +void vIncrementTxLength(unsigned long ulLength); +void CopyFromFrame_EMAC(void *Dest, unsigned short Size); +void DummyReadFrame_EMAC(unsigned short Size); +unsigned short StartReadFrame(void); +void EndReadFrame(void); +unsigned int CheckFrameReceived(void); +void vInitialiseSend(void); +unsigned int Rdy4Tx(void); +void vSendBufferToMAC(void); +void vEMACWaitForInput( void ); +unsigned int uiGetEMACRxData( unsigned char *ucBuffer ); + + +#endif + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/http-strings b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/http-strings new file mode 100644 index 000000000..0d3c30cdd --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/http-strings @@ -0,0 +1,35 @@ +http_http "http://" +http_200 "200 " +http_301 "301 " +http_302 "302 " +http_get "GET " +http_10 "HTTP/1.0" +http_11 "HTTP/1.1" +http_content_type "content-type: " +http_texthtml "text/html" +http_location "location: " +http_host "host: " +http_crnl "\r\n" +http_index_html "/index.html" +http_404_html "/404.html" +http_referer "Referer:" +http_header_200 "HTTP/1.0 200 OK\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" +http_header_404 "HTTP/1.0 404 Not found\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" +http_content_type_plain "Content-type: text/plain\r\n\r\n" +http_content_type_html "Content-type: text/html\r\n\r\n" +http_content_type_css "Content-type: text/css\r\n\r\n" +http_content_type_text "Content-type: text/text\r\n\r\n" +http_content_type_png "Content-type: image/png\r\n\r\n" +http_content_type_gif "Content-type: image/gif\r\n\r\n" +http_content_type_jpg "Content-type: image/jpeg\r\n\r\n" +http_content_type_binary "Content-type: application/octet-stream\r\n\r\n" +http_html ".html" +http_shtml ".shtml" +http_htm ".htm" +http_css ".css" +http_png ".png" +http_gif ".gif" +http_jpg ".jpg" +http_text ".txt" +http_txt ".txt" + diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/http-strings.c b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/http-strings.c new file mode 100644 index 000000000..ef7a41c7d --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/http-strings.c @@ -0,0 +1,102 @@ +const char http_http[8] = +/* "http://" */ +{0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, }; +const char http_200[5] = +/* "200 " */ +{0x32, 0x30, 0x30, 0x20, }; +const char http_301[5] = +/* "301 " */ +{0x33, 0x30, 0x31, 0x20, }; +const char http_302[5] = +/* "302 " */ +{0x33, 0x30, 0x32, 0x20, }; +const char http_get[5] = +/* "GET " */ +{0x47, 0x45, 0x54, 0x20, }; +const char http_10[9] = +/* "HTTP/1.0" */ +{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, }; +const char http_11[9] = +/* "HTTP/1.1" */ +{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x31, }; +const char http_content_type[15] = +/* "content-type: " */ +{0x63, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, }; +const char http_texthtml[10] = +/* "text/html" */ +{0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_location[11] = +/* "location: " */ +{0x6c, 0x6f, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, }; +const char http_host[7] = +/* "host: " */ +{0x68, 0x6f, 0x73, 0x74, 0x3a, 0x20, }; +const char http_crnl[3] = +/* "\r\n" */ +{0xd, 0xa, }; +const char http_index_html[12] = +/* "/index.html" */ +{0x2f, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_404_html[10] = +/* "/404.html" */ +{0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_referer[9] = +/* "Referer:" */ +{0x52, 0x65, 0x66, 0x65, 0x72, 0x65, 0x72, 0x3a, }; +const char http_header_200[84] = +/* "HTTP/1.0 200 OK\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */ +{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x32, 0x30, 0x30, 0x20, 0x4f, 0x4b, 0xd, 0xa, 0x53, 0x65, 0x72, 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x73, 0x69, 0x63, 0x73, 0x2e, 0x73, 0x65, 0x2f, 0x7e, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, 0x70, 0x2f, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0xd, 0xa, }; +const char http_header_404[91] = +/* "HTTP/1.0 404 Not found\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */ +{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x34, 0x30, 0x34, 0x20, 0x4e, 0x6f, 0x74, 0x20, 0x66, 0x6f, 0x75, 0x6e, 0x64, 0xd, 0xa, 0x53, 0x65, 0x72, 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x73, 0x69, 0x63, 0x73, 0x2e, 0x73, 0x65, 0x2f, 0x7e, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, 0x70, 0x2f, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0xd, 0xa, }; +const char http_content_type_plain[29] = +/* "Content-type: text/plain\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x70, 0x6c, 0x61, 0x69, 0x6e, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_html[28] = +/* "Content-type: text/html\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_css [27] = +/* "Content-type: text/css\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x63, 0x73, 0x73, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_text[28] = +/* "Content-type: text/text\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x74, 0x65, 0x78, 0x74, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_png [28] = +/* "Content-type: image/png\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x70, 0x6e, 0x67, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_gif [28] = +/* "Content-type: image/gif\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x67, 0x69, 0x66, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_jpg [29] = +/* "Content-type: image/jpeg\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x6a, 0x70, 0x65, 0x67, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_binary[43] = +/* "Content-type: application/octet-stream\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x61, 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x2f, 0x6f, 0x63, 0x74, 0x65, 0x74, 0x2d, 0x73, 0x74, 0x72, 0x65, 0x61, 0x6d, 0xd, 0xa, 0xd, 0xa, }; +const char http_html[6] = +/* ".html" */ +{0x2e, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_shtml[7] = +/* ".shtml" */ +{0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_htm[5] = +/* ".htm" */ +{0x2e, 0x68, 0x74, 0x6d, }; +const char http_css[5] = +/* ".css" */ +{0x2e, 0x63, 0x73, 0x73, }; +const char http_png[5] = +/* ".png" */ +{0x2e, 0x70, 0x6e, 0x67, }; +const char http_gif[5] = +/* ".gif" */ +{0x2e, 0x67, 0x69, 0x66, }; +const char http_jpg[5] = +/* ".jpg" */ +{0x2e, 0x6a, 0x70, 0x67, }; +const char http_text[5] = +/* ".txt" */ +{0x2e, 0x74, 0x78, 0x74, }; +const char http_txt[5] = +/* ".txt" */ +{0x2e, 0x74, 0x78, 0x74, }; diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/http-strings.h b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/http-strings.h new file mode 100644 index 000000000..acbe7e17f --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/http-strings.h @@ -0,0 +1,34 @@ +extern const char http_http[8]; +extern const char http_200[5]; +extern const char http_301[5]; +extern const char http_302[5]; +extern const char http_get[5]; +extern const char http_10[9]; +extern const char http_11[9]; +extern const char http_content_type[15]; +extern const char http_texthtml[10]; +extern const char http_location[11]; +extern const char http_host[7]; +extern const char http_crnl[3]; +extern const char http_index_html[12]; +extern const char http_404_html[10]; +extern const char http_referer[9]; +extern const char http_header_200[84]; +extern const char http_header_404[91]; +extern const char http_content_type_plain[29]; +extern const char http_content_type_html[28]; +extern const char http_content_type_css [27]; +extern const char http_content_type_text[28]; +extern const char http_content_type_png [28]; +extern const char http_content_type_gif [28]; +extern const char http_content_type_jpg [29]; +extern const char http_content_type_binary[43]; +extern const char http_html[6]; +extern const char http_shtml[7]; +extern const char http_htm[5]; +extern const char http_css[5]; +extern const char http_png[5]; +extern const char http_gif[5]; +extern const char http_jpg[5]; +extern const char http_text[5]; +extern const char http_txt[5]; diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-cgi.c b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-cgi.c new file mode 100644 index 000000000..803b771e6 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-cgi.c @@ -0,0 +1,269 @@ +/** + * \addtogroup httpd + * @{ + */ + +/** + * \file + * Web server script interface + * \author + * Adam Dunkels + * + */ + +/* + * Copyright (c) 2001-2006, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: httpd-cgi.c,v 1.2 2006/06/11 21:46:37 adam Exp $ + * + */ + +#include "uip.h" +#include "psock.h" +#include "httpd.h" +#include "httpd-cgi.h" +#include "httpd-fs.h" + +#include +#include + +HTTPD_CGI_CALL(file, "file-stats", file_stats); +HTTPD_CGI_CALL(tcp, "tcp-connections", tcp_stats); +HTTPD_CGI_CALL(net, "net-stats", net_stats); +HTTPD_CGI_CALL(rtos, "rtos-stats", rtos_stats ); +HTTPD_CGI_CALL(io, "led-io", led_io ); + + +static const struct httpd_cgi_call *calls[] = { &file, &tcp, &net, &rtos, &io, NULL }; + +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(nullfunction(struct httpd_state *s, char *ptr)) +{ + PSOCK_BEGIN(&s->sout); + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +httpd_cgifunction +httpd_cgi(char *name) +{ + const struct httpd_cgi_call **f; + + /* Find the matching name in the table, return the function. */ + for(f = calls; *f != NULL; ++f) { + if(strncmp((*f)->name, name, strlen((*f)->name)) == 0) { + return (*f)->function; + } + } + return nullfunction; +} +/*---------------------------------------------------------------------------*/ +static unsigned short +generate_file_stats(void *arg) +{ + char *f = (char *)arg; + return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, "%5u", httpd_fs_count(f)); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(file_stats(struct httpd_state *s, char *ptr)) +{ + PSOCK_BEGIN(&s->sout); + + PSOCK_GENERATOR_SEND(&s->sout, generate_file_stats, strchr(ptr, ' ') + 1); + + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +static const char closed[] = /* "CLOSED",*/ +{0x43, 0x4c, 0x4f, 0x53, 0x45, 0x44, 0}; +static const char syn_rcvd[] = /* "SYN-RCVD",*/ +{0x53, 0x59, 0x4e, 0x2d, 0x52, 0x43, 0x56, + 0x44, 0}; +static const char syn_sent[] = /* "SYN-SENT",*/ +{0x53, 0x59, 0x4e, 0x2d, 0x53, 0x45, 0x4e, + 0x54, 0}; +static const char established[] = /* "ESTABLISHED",*/ +{0x45, 0x53, 0x54, 0x41, 0x42, 0x4c, 0x49, 0x53, 0x48, + 0x45, 0x44, 0}; +static const char fin_wait_1[] = /* "FIN-WAIT-1",*/ +{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49, + 0x54, 0x2d, 0x31, 0}; +static const char fin_wait_2[] = /* "FIN-WAIT-2",*/ +{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49, + 0x54, 0x2d, 0x32, 0}; +static const char closing[] = /* "CLOSING",*/ +{0x43, 0x4c, 0x4f, 0x53, 0x49, + 0x4e, 0x47, 0}; +static const char time_wait[] = /* "TIME-WAIT,"*/ +{0x54, 0x49, 0x4d, 0x45, 0x2d, 0x57, 0x41, + 0x49, 0x54, 0}; +static const char last_ack[] = /* "LAST-ACK"*/ +{0x4c, 0x41, 0x53, 0x54, 0x2d, 0x41, 0x43, + 0x4b, 0}; + +static const char *states[] = { + closed, + syn_rcvd, + syn_sent, + established, + fin_wait_1, + fin_wait_2, + closing, + time_wait, + last_ack}; + + +static unsigned short +generate_tcp_stats(void *arg) +{ + struct uip_conn *conn; + struct httpd_state *s = (struct httpd_state *)arg; + + conn = &uip_conns[s->count]; + return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, + "\r\n", + htons(conn->lport), + htons(conn->ripaddr[0]) >> 8, + htons(conn->ripaddr[0]) & 0xff, + htons(conn->ripaddr[1]) >> 8, + htons(conn->ripaddr[1]) & 0xff, + htons(conn->rport), + states[conn->tcpstateflags & UIP_TS_MASK], + conn->nrtx, + conn->timer, + (uip_outstanding(conn))? '*':' ', + (uip_stopped(conn))? '!':' '); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(tcp_stats(struct httpd_state *s, char *ptr)) +{ + + PSOCK_BEGIN(&s->sout); + + for(s->count = 0; s->count < UIP_CONNS; ++s->count) { + if((uip_conns[s->count].tcpstateflags & UIP_TS_MASK) != UIP_CLOSED) { + PSOCK_GENERATOR_SEND(&s->sout, generate_tcp_stats, s); + } + } + + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +static unsigned short +generate_net_stats(void *arg) +{ + struct httpd_state *s = (struct httpd_state *)arg; + return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, + "%5u\n", ((uip_stats_t *)&uip_stat)[s->count]); +} + +static +PT_THREAD(net_stats(struct httpd_state *s, char *ptr)) +{ + PSOCK_BEGIN(&s->sout); + +#if UIP_STATISTICS + + for(s->count = 0; s->count < sizeof(uip_stat) / sizeof(uip_stats_t); + ++s->count) { + PSOCK_GENERATOR_SEND(&s->sout, generate_net_stats, s); + } + +#endif /* UIP_STATISTICS */ + + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ + +extern void vTaskList( signed char *pcWriteBuffer ); +static char cCountBuf[ 32 ]; +long lRefreshCount = 0; +static unsigned short +generate_rtos_stats(void *arg) +{ + lRefreshCount++; + sprintf( cCountBuf, "


Refresh count = %d", lRefreshCount ); + vTaskList( uip_appdata ); + strcat( uip_appdata, cCountBuf ); + + return strlen( uip_appdata ); +} +/*---------------------------------------------------------------------------*/ + + +static +PT_THREAD(rtos_stats(struct httpd_state *s, char *ptr)) +{ + PSOCK_BEGIN(&s->sout); + PSOCK_GENERATOR_SEND(&s->sout, generate_rtos_stats, NULL); + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ + +char *pcStatus; +extern unsigned long uxParTestGetLED( unsigned long uxLED ); + +static unsigned short generate_io_state( void *arg ) +{ + if( uxParTestGetLED( 0 ) ) + { + pcStatus = "checked"; + } + else + { + pcStatus = ""; + } + + sprintf( uip_appdata, + "LED"\ + "

"\ + "", + pcStatus ); + + return strlen( uip_appdata ); +} +/*---------------------------------------------------------------------------*/ + +static PT_THREAD(led_io(struct httpd_state *s, char *ptr)) +{ + PSOCK_BEGIN(&s->sout); + PSOCK_GENERATOR_SEND(&s->sout, generate_io_state, NULL); + PSOCK_END(&s->sout); +} + +/** @} */ + + + + + + diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-cgi.h b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-cgi.h new file mode 100644 index 000000000..7ae928321 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-cgi.h @@ -0,0 +1,84 @@ +/** + * \addtogroup httpd + * @{ + */ + +/** + * \file + * Web server script interface header file + * \author + * Adam Dunkels + * + */ + + + +/* + * Copyright (c) 2001, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: httpd-cgi.h,v 1.2 2006/06/11 21:46:38 adam Exp $ + * + */ + +#ifndef __HTTPD_CGI_H__ +#define __HTTPD_CGI_H__ + +#include "psock.h" +#include "httpd.h" + +typedef PT_THREAD((* httpd_cgifunction)(struct httpd_state *, char *)); + +httpd_cgifunction httpd_cgi(char *name); + +struct httpd_cgi_call { + const char *name; + const httpd_cgifunction function; +}; + +/** + * \brief HTTPD CGI function declaration + * \param name The C variable name of the function + * \param str The string name of the function, used in the script file + * \param function A pointer to the function that implements it + * + * This macro is used for declaring a HTTPD CGI + * function. This function is then added to the list of + * HTTPD CGI functions with the httpd_cgi_add() function. + * + * \hideinitializer + */ +#define HTTPD_CGI_CALL(name, str, function) \ +static PT_THREAD(function(struct httpd_state *, char *)); \ +static const struct httpd_cgi_call name = {str, function} + +void httpd_cgi_init(void); +#endif /* __HTTPD_CGI_H__ */ + +/** @} */ diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs.c b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs.c new file mode 100644 index 000000000..dc4aef011 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs.c @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: httpd-fs.c,v 1.1 2006/06/07 09:13:08 adam Exp $ + */ + +#include "httpd.h" +#include "httpd-fs.h" +#include "httpd-fsdata.h" + +#ifndef NULL +#define NULL 0 +#endif /* NULL */ + +#include "httpd-fsdata.c" + +#if HTTPD_FS_STATISTICS +static u16_t count[HTTPD_FS_NUMFILES]; +#endif /* HTTPD_FS_STATISTICS */ + +/*-----------------------------------------------------------------------------------*/ +static u8_t +httpd_fs_strcmp(const char *str1, const char *str2) +{ + u8_t i; + i = 0; + loop: + + if(str2[i] == 0 || + str1[i] == '\r' || + str1[i] == '\n') { + return 0; + } + + if(str1[i] != str2[i]) { + return 1; + } + + + ++i; + goto loop; +} +/*-----------------------------------------------------------------------------------*/ +int +httpd_fs_open(const char *name, struct httpd_fs_file *file) +{ +#if HTTPD_FS_STATISTICS + u16_t i = 0; +#endif /* HTTPD_FS_STATISTICS */ + struct httpd_fsdata_file_noconst *f; + + for(f = (struct httpd_fsdata_file_noconst *)HTTPD_FS_ROOT; + f != NULL; + f = (struct httpd_fsdata_file_noconst *)f->next) { + + if(httpd_fs_strcmp(name, f->name) == 0) { + file->data = f->data; + file->len = f->len; +#if HTTPD_FS_STATISTICS + ++count[i]; +#endif /* HTTPD_FS_STATISTICS */ + return 1; + } +#if HTTPD_FS_STATISTICS + ++i; +#endif /* HTTPD_FS_STATISTICS */ + + } + return 0; +} +/*-----------------------------------------------------------------------------------*/ +void +httpd_fs_init(void) +{ +#if HTTPD_FS_STATISTICS + u16_t i; + for(i = 0; i < HTTPD_FS_NUMFILES; i++) { + count[i] = 0; + } +#endif /* HTTPD_FS_STATISTICS */ +} +/*-----------------------------------------------------------------------------------*/ +#if HTTPD_FS_STATISTICS +u16_t httpd_fs_count +(char *name) +{ + struct httpd_fsdata_file_noconst *f; + u16_t i; + + i = 0; + for(f = (struct httpd_fsdata_file_noconst *)HTTPD_FS_ROOT; + f != NULL; + f = (struct httpd_fsdata_file_noconst *)f->next) { + + if(httpd_fs_strcmp(name, f->name) == 0) { + return count[i]; + } + ++i; + } + return 0; +} +#endif /* HTTPD_FS_STATISTICS */ +/*-----------------------------------------------------------------------------------*/ diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs.h b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs.h new file mode 100644 index 000000000..b594eea56 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: httpd-fs.h,v 1.1 2006/06/07 09:13:08 adam Exp $ + */ +#ifndef __HTTPD_FS_H__ +#define __HTTPD_FS_H__ + +#define HTTPD_FS_STATISTICS 1 + +struct httpd_fs_file { + char *data; + int len; +}; + +/* file must be allocated by caller and will be filled in + by the function. */ +int httpd_fs_open(const char *name, struct httpd_fs_file *file); + +#ifdef HTTPD_FS_STATISTICS +#if HTTPD_FS_STATISTICS == 1 +u16_t httpd_fs_count(char *name); +#endif /* HTTPD_FS_STATISTICS */ +#endif /* HTTPD_FS_STATISTICS */ + +void httpd_fs_init(void); + +#endif /* __HTTPD_FS_H__ */ diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs/404.html b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs/404.html new file mode 100644 index 000000000..43e7f4cad --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs/404.html @@ -0,0 +1,8 @@ + + +

+

404 - file not found

+

Go here instead.

+
+ + \ No newline at end of file diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs/index.html b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs/index.html new file mode 100644 index 000000000..1d3bbeee1 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs/index.html @@ -0,0 +1,13 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +Loading index.shtml. Click here if not automatically redirected. + + + + + diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs/index.shtml b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs/index.shtml new file mode 100644 index 000000000..1923ea762 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs/index.shtml @@ -0,0 +1,20 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +RTOS Stats | TCP Stats | Connections | FreeRTOS.org Homepage | IO +

+

+

+

Task statistics

+Page will refresh every 2 seconds.

+

Task          State  Priority  Stack	#
************************************************

+%! rtos-stats
+
+ + + + diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs/io.shtml b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs/io.shtml new file mode 100644 index 000000000..07554bb71 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs/io.shtml @@ -0,0 +1,28 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +RTOS Stats | TCP Stats | Connections | FreeRTOS.org Homepage | IO +

+

+LED and LCD IO
+ +

+ +Use the check box to turn on or off the LED, enter text to display on the OLED display, then click "Update IO". + + +

+
+%! led-io +

+ + +

+ + + + diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs/stats.shtml b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs/stats.shtml new file mode 100644 index 000000000..d762f40d8 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs/stats.shtml @@ -0,0 +1,41 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +RTOS Stats | TCP Stats | Connections | FreeRTOS.org Homepage | IO +

+

+

+

Network statistics

+
LocalRemoteStateRetransmissionsTimerFlags
%d%u.%u.%u.%u:%u%s%u%u%c %c
+
+IP           Packets dropped
+             Packets received
+             Packets sent
+IP errors    IP version/header length
+             IP length, high byte
+             IP length, low byte
+             IP fragments
+             Header checksum
+             Wrong protocol
+ICMP	     Packets dropped
+             Packets received
+             Packets sent
+             Type errors
+TCP          Packets dropped
+             Packets received
+             Packets sent
+             Checksum errors
+             Data packets without ACKs
+             Resets
+             Retransmissions
+	     No connection avaliable
+	     Connection attempts to closed ports
+
%! net-stats
+
+ + + diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs/tcp.shtml b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs/tcp.shtml new file mode 100644 index 000000000..654d61f21 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fs/tcp.shtml @@ -0,0 +1,21 @@ + + + + FreeRTOS.org uIP WEB server demo + + + +RTOS Stats | TCP Stats | Connections | FreeRTOS.org Homepage | IO +

+

+
+

Network connections

+

+ + +%! tcp-connections + + + + + diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fsdata.c b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fsdata.c new file mode 100644 index 000000000..a7fcfab5a --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fsdata.c @@ -0,0 +1,470 @@ +static const unsigned char data_404_html[] = { + /* /404.html */ + 0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0, + 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xd, 0xa, 0x20, 0x20, + 0x3c, 0x62, 0x6f, 0x64, 0x79, 0x20, 0x62, 0x67, 0x63, 0x6f, + 0x6c, 0x6f, 0x72, 0x3d, 0x22, 0x77, 0x68, 0x69, 0x74, 0x65, + 0x22, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x3c, 0x63, + 0x65, 0x6e, 0x74, 0x65, 0x72, 0x3e, 0xd, 0xa, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x3c, 0x68, 0x31, 0x3e, 0x34, 0x30, + 0x34, 0x20, 0x2d, 0x20, 0x66, 0x69, 0x6c, 0x65, 0x20, 0x6e, + 0x6f, 0x74, 0x20, 0x66, 0x6f, 0x75, 0x6e, 0x64, 0x3c, 0x2f, + 0x68, 0x31, 0x3e, 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 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0x3e, + 0xd, 0xa, 0}; + +static const unsigned char data_tcp_shtml[] = { + /* /tcp.shtml */ + 0x2f, 0x74, 0x63, 0x70, 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0, + 0x3c, 0x21, 0x44, 0x4f, 0x43, 0x54, 0x59, 0x50, 0x45, 0x20, + 0x48, 0x54, 0x4d, 0x4c, 0x20, 0x50, 0x55, 0x42, 0x4c, 0x49, + 0x43, 0x20, 0x22, 0x2d, 0x2f, 0x2f, 0x57, 0x33, 0x43, 0x2f, + 0x2f, 0x44, 0x54, 0x44, 0x20, 0x48, 0x54, 0x4d, 0x4c, 0x20, + 0x34, 0x2e, 0x30, 0x31, 0x20, 0x54, 0x72, 0x61, 0x6e, 0x73, + 0x69, 0x74, 0x69, 0x6f, 0x6e, 0x61, 0x6c, 0x2f, 0x2f, 0x45, + 0x4e, 0x22, 0x20, 0x22, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, + 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x77, 0x33, 0x2e, 0x6f, 0x72, + 0x67, 0x2f, 0x54, 0x52, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x34, + 0x2f, 0x6c, 0x6f, 0x6f, 0x73, 0x65, 0x2e, 0x64, 0x74, 0x64, + 0x22, 0x3e, 0xd, 0xa, 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, + 0xd, 0xa, 0x20, 0x20, 0x3c, 0x68, 0x65, 0x61, 0x64, 0x3e, + 0xd, 0xa, 0x20, 0x20, 0x20, 0x20, 0x3c, 0x74, 0x69, 0x74, + 0x6c, 0x65, 0x3e, 0x46, 0x72, 0x65, 0x65, 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0x6c, 0x61, 0x67, 0x73, 0x3c, 0x2f, 0x74, + 0x68, 0x3e, 0x3c, 0x2f, 0x74, 0x72, 0x3e, 0xd, 0xa, 0x25, + 0x21, 0x20, 0x74, 0x63, 0x70, 0x2d, 0x63, 0x6f, 0x6e, 0x6e, + 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x73, 0xd, 0xa, 0x3c, + 0x2f, 0x70, 0x72, 0x65, 0x3e, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, + 0x74, 0x3e, 0xd, 0xa, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, 0x74, + 0x3e, 0xd, 0xa, 0x3c, 0x2f, 0x62, 0x6f, 0x64, 0x79, 0x3e, + 0xd, 0xa, 0x3c, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xd, + 0xa, 0xd, 0xa, 0}; + +const struct httpd_fsdata_file file_404_html[] = {{NULL, data_404_html, data_404_html + 10, sizeof(data_404_html) - 10}}; + +const struct httpd_fsdata_file file_index_html[] = {{file_404_html, data_index_html, data_index_html + 12, sizeof(data_index_html) - 12}}; + +const struct httpd_fsdata_file file_index_shtml[] = {{file_index_html, data_index_shtml, data_index_shtml + 13, sizeof(data_index_shtml) - 13}}; + +const struct httpd_fsdata_file file_io_shtml[] = {{file_index_shtml, data_io_shtml, data_io_shtml + 10, sizeof(data_io_shtml) - 10}}; + +const struct httpd_fsdata_file file_stats_shtml[] = {{file_io_shtml, data_stats_shtml, data_stats_shtml + 13, sizeof(data_stats_shtml) - 13}}; + +const struct httpd_fsdata_file file_tcp_shtml[] = {{file_stats_shtml, data_tcp_shtml, data_tcp_shtml + 11, sizeof(data_tcp_shtml) - 11}}; + +#define HTTPD_FS_ROOT file_tcp_shtml + +#define HTTPD_FS_NUMFILES 6 diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fsdata.h b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fsdata.h new file mode 100644 index 000000000..52d35c265 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd-fsdata.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: httpd-fsdata.h,v 1.1 2006/06/07 09:13:08 adam Exp $ + */ +#ifndef __HTTPD_FSDATA_H__ +#define __HTTPD_FSDATA_H__ + +#include "uip.h" + +struct httpd_fsdata_file { + const struct httpd_fsdata_file *next; + const char *name; + const char *data; + const int len; +#ifdef HTTPD_FS_STATISTICS +#if HTTPD_FS_STATISTICS == 1 + u16_t count; +#endif /* HTTPD_FS_STATISTICS */ +#endif /* HTTPD_FS_STATISTICS */ +}; + +struct httpd_fsdata_file_noconst { + struct httpd_fsdata_file *next; + char *name; + char *data; + int len; +#ifdef HTTPD_FS_STATISTICS +#if HTTPD_FS_STATISTICS == 1 + u16_t count; +#endif /* HTTPD_FS_STATISTICS */ +#endif /* HTTPD_FS_STATISTICS */ +}; + +#endif /* __HTTPD_FSDATA_H__ */ diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd.c b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd.c new file mode 100644 index 000000000..644cf16b7 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd.c @@ -0,0 +1,346 @@ +/** + * \addtogroup apps + * @{ + */ + +/** + * \defgroup httpd Web server + * @{ + * The uIP web server is a very simplistic implementation of an HTTP + * server. It can serve web pages and files from a read-only ROM + * filesystem, and provides a very small scripting language. + + */ + +/** + * \file + * Web server + * \author + * Adam Dunkels + */ + + +/* + * Copyright (c) 2004, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: httpd.c,v 1.2 2006/06/11 21:46:38 adam Exp $ + */ + +#include "uip.h" +#include "httpd.h" +#include "httpd-fs.h" +#include "httpd-cgi.h" +#include "http-strings.h" + +#include + +#define STATE_WAITING 0 +#define STATE_OUTPUT 1 + +#define ISO_nl 0x0a +#define ISO_space 0x20 +#define ISO_bang 0x21 +#define ISO_percent 0x25 +#define ISO_period 0x2e +#define ISO_slash 0x2f +#define ISO_colon 0x3a + + +/*---------------------------------------------------------------------------*/ +static unsigned short +generate_part_of_file(void *state) +{ + struct httpd_state *s = (struct httpd_state *)state; + + if(s->file.len > uip_mss()) { + s->len = uip_mss(); + } else { + s->len = s->file.len; + } + memcpy(uip_appdata, s->file.data, s->len); + + return s->len; +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(send_file(struct httpd_state *s)) +{ + PSOCK_BEGIN(&s->sout); + + do { + PSOCK_GENERATOR_SEND(&s->sout, generate_part_of_file, s); + s->file.len -= s->len; + s->file.data += s->len; + } while(s->file.len > 0); + + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(send_part_of_file(struct httpd_state *s)) +{ + PSOCK_BEGIN(&s->sout); + + PSOCK_SEND(&s->sout, s->file.data, s->len); + + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +static void +next_scriptstate(struct httpd_state *s) +{ + char *p; + p = strchr(s->scriptptr, ISO_nl) + 1; + s->scriptlen -= (unsigned short)(p - s->scriptptr); + s->scriptptr = p; +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(handle_script(struct httpd_state *s)) +{ + char *ptr; + + PT_BEGIN(&s->scriptpt); + + + while(s->file.len > 0) { + + /* Check if we should start executing a script. */ + if(*s->file.data == ISO_percent && + *(s->file.data + 1) == ISO_bang) { + s->scriptptr = s->file.data + 3; + s->scriptlen = s->file.len - 3; + if(*(s->scriptptr - 1) == ISO_colon) { + httpd_fs_open(s->scriptptr + 1, &s->file); + PT_WAIT_THREAD(&s->scriptpt, send_file(s)); + } else { + PT_WAIT_THREAD(&s->scriptpt, + httpd_cgi(s->scriptptr)(s, s->scriptptr)); + } + next_scriptstate(s); + + /* The script is over, so we reset the pointers and continue + sending the rest of the file. */ + s->file.data = s->scriptptr; + s->file.len = s->scriptlen; + } else { + /* See if we find the start of script marker in the block of HTML + to be sent. */ + + if(s->file.len > uip_mss()) { + s->len = uip_mss(); + } else { + s->len = s->file.len; + } + + if(*s->file.data == ISO_percent) { + ptr = strchr(s->file.data + 1, ISO_percent); + } else { + ptr = strchr(s->file.data, ISO_percent); + } + if(ptr != NULL && + ptr != s->file.data) { + s->len = (int)(ptr - s->file.data); + if(s->len >= uip_mss()) { + s->len = uip_mss(); + } + } + PT_WAIT_THREAD(&s->scriptpt, send_part_of_file(s)); + s->file.data += s->len; + s->file.len -= s->len; + + } + } + + PT_END(&s->scriptpt); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(send_headers(struct httpd_state *s, const char *statushdr)) +{ + char *ptr; + + PSOCK_BEGIN(&s->sout); + + PSOCK_SEND_STR(&s->sout, statushdr); + + ptr = strrchr(s->filename, ISO_period); + if(ptr == NULL) { + PSOCK_SEND_STR(&s->sout, http_content_type_binary); + } else if(strncmp(http_html, ptr, 5) == 0 || + strncmp(http_shtml, ptr, 6) == 0) { + PSOCK_SEND_STR(&s->sout, http_content_type_html); + } else if(strncmp(http_css, ptr, 4) == 0) { + PSOCK_SEND_STR(&s->sout, http_content_type_css); + } else if(strncmp(http_png, ptr, 4) == 0) { + PSOCK_SEND_STR(&s->sout, http_content_type_png); + } else if(strncmp(http_gif, ptr, 4) == 0) { + PSOCK_SEND_STR(&s->sout, http_content_type_gif); + } else if(strncmp(http_jpg, ptr, 4) == 0) { + PSOCK_SEND_STR(&s->sout, http_content_type_jpg); + } else { + PSOCK_SEND_STR(&s->sout, http_content_type_plain); + } + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(handle_output(struct httpd_state *s)) +{ + char *ptr; + + PT_BEGIN(&s->outputpt); + + if(!httpd_fs_open(s->filename, &s->file)) { + httpd_fs_open(http_404_html, &s->file); + strcpy(s->filename, http_404_html); + PT_WAIT_THREAD(&s->outputpt, + send_headers(s, + http_header_404)); + PT_WAIT_THREAD(&s->outputpt, + send_file(s)); + } else { + PT_WAIT_THREAD(&s->outputpt, + send_headers(s, + http_header_200)); + ptr = strchr(s->filename, ISO_period); + if(ptr != NULL && strncmp(ptr, http_shtml, 6) == 0) { + PT_INIT(&s->scriptpt); + PT_WAIT_THREAD(&s->outputpt, handle_script(s)); + } else { + PT_WAIT_THREAD(&s->outputpt, + send_file(s)); + } + } + PSOCK_CLOSE(&s->sout); + PT_END(&s->outputpt); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(handle_input(struct httpd_state *s)) +{ + PSOCK_BEGIN(&s->sin); + + PSOCK_READTO(&s->sin, ISO_space); + + + if(strncmp(s->inputbuf, http_get, 4) != 0) { + PSOCK_CLOSE_EXIT(&s->sin); + } + PSOCK_READTO(&s->sin, ISO_space); + + if(s->inputbuf[0] != ISO_slash) { + PSOCK_CLOSE_EXIT(&s->sin); + } + + if(s->inputbuf[1] == ISO_space) { + strncpy(s->filename, http_index_html, sizeof(s->filename)); + } else { + + s->inputbuf[PSOCK_DATALEN(&s->sin) - 1] = 0; + + /* Process any form input being sent to the server. */ + { + extern void vApplicationProcessFormInput( char *pcInputString, long xInputLength ); + vApplicationProcessFormInput( s->inputbuf, PSOCK_DATALEN(&s->sin) ); + } + + strncpy(s->filename, &s->inputbuf[0], sizeof(s->filename)); + } + + /* httpd_log_file(uip_conn->ripaddr, s->filename);*/ + + s->state = STATE_OUTPUT; + + while(1) { + PSOCK_READTO(&s->sin, ISO_nl); + + if(strncmp(s->inputbuf, http_referer, 8) == 0) { + s->inputbuf[PSOCK_DATALEN(&s->sin) - 2] = 0; + /* httpd_log(&s->inputbuf[9]);*/ + } + } + + PSOCK_END(&s->sin); +} +/*---------------------------------------------------------------------------*/ +static void +handle_connection(struct httpd_state *s) +{ + handle_input(s); + if(s->state == STATE_OUTPUT) { + handle_output(s); + } +} +/*---------------------------------------------------------------------------*/ +void +httpd_appcall(void) +{ + struct httpd_state *s = (struct httpd_state *)&(uip_conn->appstate); + + if(uip_closed() || uip_aborted() || uip_timedout()) { + } else if(uip_connected()) { + PSOCK_INIT(&s->sin, s->inputbuf, sizeof(s->inputbuf) - 1); + PSOCK_INIT(&s->sout, s->inputbuf, sizeof(s->inputbuf) - 1); + PT_INIT(&s->outputpt); + s->state = STATE_WAITING; + /* timer_set(&s->timer, CLOCK_SECOND * 100);*/ + s->timer = 0; + handle_connection(s); + } else if(s != NULL) { + if(uip_poll()) { + ++s->timer; + if(s->timer >= 20) { + uip_abort(); + } + } else { + s->timer = 0; + } + handle_connection(s); + } else { + uip_abort(); + } +} +/*---------------------------------------------------------------------------*/ +/** + * \brief Initialize the web server + * + * This function initializes the web server and should be + * called at system boot-up. + */ +void +httpd_init(void) +{ + uip_listen(HTONS(80)); +} +/*---------------------------------------------------------------------------*/ +/** @} */ diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd.h b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd.h new file mode 100644 index 000000000..7f7a6666e --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/httpd.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2001-2005, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: httpd.h,v 1.2 2006/06/11 21:46:38 adam Exp $ + * + */ + +#ifndef __HTTPD_H__ +#define __HTTPD_H__ + +#include "psock.h" +#include "httpd-fs.h" + +struct httpd_state { + unsigned char timer; + struct psock sin, sout; + struct pt outputpt, scriptpt; + char inputbuf[50]; + char filename[20]; + char state; + struct httpd_fs_file file; + int len; + char *scriptptr; + int scriptlen; + + unsigned short count; +}; + +void httpd_init(void); +void httpd_appcall(void); + +void httpd_log(char *msg); +void httpd_log_file(u16_t *requester, char *file); + +#endif /* __HTTPD_H__ */ diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/makefsdata b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/makefsdata new file mode 100644 index 000000000..8d2715a8a --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/makefsdata @@ -0,0 +1,78 @@ +#!/usr/bin/perl + +open(OUTPUT, "> httpd-fsdata.c"); + +chdir("httpd-fs"); + +opendir(DIR, "."); +@files = grep { !/^\./ && !/(CVS|~)/ } readdir(DIR); +closedir(DIR); + +foreach $file (@files) { + + if(-d $file && $file !~ /^\./) { + print "Processing directory $file\n"; + opendir(DIR, $file); + @newfiles = grep { !/^\./ && !/(CVS|~)/ } readdir(DIR); + closedir(DIR); + printf "Adding files @newfiles\n"; + @files = (@files, map { $_ = "$file/$_" } @newfiles); + next; + } +} + +foreach $file (@files) { + if(-f $file) { + + print "Adding file $file\n"; + + open(FILE, $file) || die "Could not open file $file\n"; + + $file =~ s-^-/-; + $fvar = $file; + $fvar =~ s-/-_-g; + $fvar =~ s-\.-_-g; + # for AVR, add PROGMEM here + print(OUTPUT "static const unsigned char data".$fvar."[] = {\n"); + print(OUTPUT "\t/* $file */\n\t"); + for($j = 0; $j < length($file); $j++) { + printf(OUTPUT "%#02x, ", unpack("C", substr($file, $j, 1))); + } + printf(OUTPUT "0,\n"); + + + $i = 0; + while(read(FILE, $data, 1)) { + if($i == 0) { + print(OUTPUT "\t"); + } + printf(OUTPUT "%#02x, ", unpack("C", $data)); + $i++; + if($i == 10) { + print(OUTPUT "\n"); + $i = 0; + } + } + print(OUTPUT "0};\n\n"); + close(FILE); + push(@fvars, $fvar); + push(@pfiles, $file); + } +} + +for($i = 0; $i < @fvars; $i++) { + $file = $pfiles[$i]; + $fvar = $fvars[$i]; + + if($i == 0) { + $prevfile = "NULL"; + } else { + $prevfile = "file" . $fvars[$i - 1]; + } + print(OUTPUT "const struct httpd_fsdata_file file".$fvar."[] = {{$prevfile, data$fvar, "); + print(OUTPUT "data$fvar + ". (length($file) + 1) .", "); + print(OUTPUT "sizeof(data$fvar) - ". (length($file) + 1) ."}};\n\n"); +} + +print(OUTPUT "#define HTTPD_FS_ROOT file$fvars[$i - 1]\n\n"); +print(OUTPUT "#define HTTPD_FS_NUMFILES $i\n"); diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/makestrings b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/makestrings new file mode 100644 index 000000000..8a13c6d29 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/makestrings @@ -0,0 +1,40 @@ +#!/usr/bin/perl + + +sub stringify { + my $name = shift(@_); + open(OUTPUTC, "> $name.c"); + open(OUTPUTH, "> $name.h"); + + open(FILE, "$name"); + + while() { + if(/(.+) "(.+)"/) { + $var = $1; + $data = $2; + + $datan = $data; + $datan =~ s/\\r/\r/g; + $datan =~ s/\\n/\n/g; + $datan =~ s/\\01/\01/g; + $datan =~ s/\\0/\0/g; + + printf(OUTPUTC "const char $var\[%d] = \n", length($datan) + 1); + printf(OUTPUTC "/* \"$data\" */\n"); + printf(OUTPUTC "{"); + for($j = 0; $j < length($datan); $j++) { + printf(OUTPUTC "%#02x, ", unpack("C", substr($datan, $j, 1))); + } + printf(OUTPUTC "};\n"); + + printf(OUTPUTH "extern const char $var\[%d];\n", length($datan) + 1); + + } + } + close(OUTPUTC); + close(OUTPUTH); +} +stringify("http-strings"); + +exit 0; + diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/uIP_Task.c b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/uIP_Task.c new file mode 100644 index 000000000..1a697b84a --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/uIP_Task.c @@ -0,0 +1,316 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* uip includes. */ +#include "hw_types.h" +#include "uip.h" +#include "uip_arp.h" +#include "httpd.h" +#include "timer.h" +#include "clock-arch.h" +#include "hw_ethernet.h" +#include "ethernet.h" +#include "hw_memmap.h" +#include "lmi_flash.h" +#include "sysctl.h" + +/* Demo includes. */ +#include "emac.h" +#include "partest.h" +#include "lcd_message.h" + +struct timer { + clock_time_t start; + clock_time_t interval; +}; + + +/*-----------------------------------------------------------*/ + +/* IP address configuration. */ +#define uipIP_ADDR0 172 +#define uipIP_ADDR1 25 +#define uipIP_ADDR2 218 +#define uipIP_ADDR3 19 + +/* How long to wait before attempting to connect the MAC again. */ +#define uipINIT_WAIT 100 + +/* Shortcut to the header within the Rx buffer. */ +#define xHeader ((struct uip_eth_hdr *) &uip_buf[ 0 ]) + +/* Standard constant. */ +#define uipTOTAL_FRAME_HEADER_SIZE 54 + +/*-----------------------------------------------------------*/ + +/* + * Send the uIP buffer to the MAC. + */ +static void prvENET_Send(void); + +/* + * Setup the MAC address in the MAC itself, and in the uIP stack. + */ +static void prvSetMACAddress( void ); + +/* + * Port functions required by the uIP stack. + */ +void clock_init( void ); +clock_time_t clock_time( void ); + +/*-----------------------------------------------------------*/ + +/* The semaphore used by the ISR to wake the uIP task. */ +extern xSemaphoreHandle xEMACSemaphore; + +/*-----------------------------------------------------------*/ + +void clock_init(void) +{ + /* This is done when the scheduler starts. */ +} +/*-----------------------------------------------------------*/ + +/* Define clock functions here to avoid header file name clash between uIP +and the Luminary Micro driver library. */ +clock_time_t clock_time( void ) +{ + return xTaskGetTickCount(); +} +extern void timer_set(struct timer *t, clock_time_t interval); +extern int timer_expired(struct timer *t); +extern void timer_reset(struct timer *t); + + + + +void vuIP_Task( void *pvParameters ) +{ +portBASE_TYPE i; +uip_ipaddr_t xIPAddr; +struct timer periodic_timer, arp_timer; +extern void ( vEMAC_ISR )( void ); + + /* Enable/Reset the Ethernet Controller */ + SysCtlPeripheralEnable( SYSCTL_PERIPH_ETH ); + SysCtlPeripheralReset( SYSCTL_PERIPH_ETH ); + + /* Create the semaphore used by the ISR to wake this task. */ + vSemaphoreCreateBinary( xEMACSemaphore ); + + /* Initialise the uIP stack. */ + timer_set( &periodic_timer, configTICK_RATE_HZ / 2 ); + timer_set( &arp_timer, configTICK_RATE_HZ * 10 ); + uip_init(); + uip_ipaddr( xIPAddr, uipIP_ADDR0, uipIP_ADDR1, uipIP_ADDR2, uipIP_ADDR3 ); + uip_sethostaddr( xIPAddr ); + httpd_init(); + + while( vInitEMAC() != pdPASS ) + { + vTaskDelay( uipINIT_WAIT ); + } + prvSetMACAddress(); + + + for( ;; ) + { + /* Is there received data ready to be processed? */ + uip_len = uiGetEMACRxData( uip_buf ); + + if( uip_len > 0 ) + { + /* Standard uIP loop taken from the uIP manual. */ + + if( xHeader->type == htons( UIP_ETHTYPE_IP ) ) + { + uip_arp_ipin(); + uip_input(); + + /* If the above function invocation resulted in data that + should be sent out on the network, the global variable + uip_len is set to a value > 0. */ + if( uip_len > 0 ) + { + uip_arp_out(); + prvENET_Send(); + } + } + else if( xHeader->type == htons( UIP_ETHTYPE_ARP ) ) + { + uip_arp_arpin(); + + /* If the above function invocation resulted in data that + should be sent out on the network, the global variable + uip_len is set to a value > 0. */ + if( uip_len > 0 ) + { + prvENET_Send(); + } + } + } + else + { + if( timer_expired( &periodic_timer ) ) + { + timer_reset( &periodic_timer ); + for( i = 0; i < UIP_CONNS; i++ ) + { + uip_periodic( i ); + + /* If the above function invocation resulted in data that + should be sent out on the network, the global variable + uip_len is set to a value > 0. */ + if( uip_len > 0 ) + { + uip_arp_out(); + prvENET_Send(); + } + } + + /* Call the ARP timer function every 10 seconds. */ + if( timer_expired( &arp_timer ) ) + { + timer_reset( &arp_timer ); + uip_arp_timer(); + } + } + else + { + /* We did not receive a packet, and there was no periodic + processing to perform. Block for a fixed period. If a packet + is received during this period we will be woken by the ISR + giving us the Semaphore. */ + xSemaphoreTake( xEMACSemaphore, configTICK_RATE_HZ / 2 ); + } + } + } +} +/*-----------------------------------------------------------*/ + +static void prvENET_Send(void) +{ + vInitialiseSend(); + vIncrementTxLength( uip_len ); + vSendBufferToMAC(); +} +/*-----------------------------------------------------------*/ + +static void prvSetMACAddress( void ) +{ +unsigned portLONG ulUser0, ulUser1; +unsigned char pucMACArray[8]; +struct uip_eth_addr xAddr; + + /* Get the device MAC address from flash */ + FlashUserGet(&ulUser0, &ulUser1); + + /* Convert the MAC address from flash into sequence of bytes. */ + pucMACArray[0] = ((ulUser0 >> 0) & 0xff); + pucMACArray[1] = ((ulUser0 >> 8) & 0xff); + pucMACArray[2] = ((ulUser0 >> 16) & 0xff); + pucMACArray[3] = ((ulUser1 >> 0) & 0xff); + pucMACArray[4] = ((ulUser1 >> 8) & 0xff); + pucMACArray[5] = ((ulUser1 >> 16) & 0xff); + + /* Program the MAC address. */ + EthernetMACAddrSet(ETH_BASE, pucMACArray); + + xAddr.addr[ 0 ] = pucMACArray[0]; + xAddr.addr[ 1 ] = pucMACArray[1]; + xAddr.addr[ 2 ] = pucMACArray[2]; + xAddr.addr[ 3 ] = pucMACArray[3]; + xAddr.addr[ 4 ] = pucMACArray[4]; + xAddr.addr[ 5 ] = pucMACArray[5]; + uip_setethaddr( xAddr ); +} +/*-----------------------------------------------------------*/ + +void vApplicationProcessFormInput( portCHAR *pcInputString, portBASE_TYPE xInputLength ) +{ +char *c, *pcText; +static portCHAR cMessageForDisplay[ 32 ]; +extern xQueueHandle xOLEDQueue; +xOLEDMessage xOLEDMessage; + + /* Process the form input sent by the IO page of the served HTML. */ + + c = strstr( pcInputString, "?" ); + + if( c ) + { + /* Turn LED's on or off in accordance with the check box status. */ + if( strstr( c, "LED0=1" ) != NULL ) + { + vParTestSetLED( 0, 1 ); + } + else + { + vParTestSetLED( 0, 0 ); + } + + /* Find the start of the text to be displayed on the LCD. */ + pcText = strstr( c, "LCD=" ); + pcText += strlen( "LCD=" ); + + /* Terminate the file name for further processing within uIP. */ + *c = 0x00; + + /* Terminate the LCD string. */ + c = strstr( pcText, " " ); + if( c != NULL ) + { + *c = 0x00; + } + + /* Add required spaces. */ + while( ( c = strstr( pcText, "+" ) ) != NULL ) + { + *c = ' '; + } + + /* Write the message to the LCD. */ + strcpy( cMessageForDisplay, pcText ); + xOLEDMessage.pcMessage = cMessageForDisplay; + xQueueSend( xOLEDQueue, &xOLEDMessage, portMAX_DELAY ); + } +} + diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/uip-conf.h b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/uip-conf.h new file mode 100644 index 000000000..455540da1 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/uip-conf.h @@ -0,0 +1,159 @@ +/** + * \addtogroup uipopt + * @{ + */ + +/** + * \name Project-specific configuration options + * @{ + * + * uIP has a number of configuration options that can be overridden + * for each project. These are kept in a project-specific uip-conf.h + * file and all configuration names have the prefix UIP_CONF. + */ + +/* + * Copyright (c) 2006, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: uip-conf.h,v 1.6 2006/06/12 08:00:31 adam Exp $ + */ + +/** + * \file + * An example uIP configuration file + * \author + * Adam Dunkels + */ + +#ifndef __UIP_CONF_H__ +#define __UIP_CONF_H__ + +#include + +/** + * 8 bit datatype + * + * This typedef defines the 8-bit type used throughout uIP. + * + * \hideinitializer + */ +typedef uint8_t u8_t; + +/** + * 16 bit datatype + * + * This typedef defines the 16-bit type used throughout uIP. + * + * \hideinitializer + */ +typedef uint16_t u16_t; + +/** + * Statistics datatype + * + * This typedef defines the dataype used for keeping statistics in + * uIP. + * + * \hideinitializer + */ +typedef unsigned short uip_stats_t; + +/** + * Maximum number of TCP connections. + * + * \hideinitializer + */ +#define UIP_CONF_MAX_CONNECTIONS 40 + +/** + * Maximum number of listening TCP ports. + * + * \hideinitializer + */ +#define UIP_CONF_MAX_LISTENPORTS 40 + +/** + * uIP buffer size. + * + * \hideinitializer + */ +#define UIP_CONF_BUFFER_SIZE 1480 + +/** + * CPU byte order. + * + * \hideinitializer + */ +#define UIP_CONF_BYTE_ORDER LITTLE_ENDIAN + +/** + * Logging on or off + * + * \hideinitializer + */ +#define UIP_CONF_LOGGING 0 + +/** + * UDP support on or off + * + * \hideinitializer + */ +#define UIP_CONF_UDP 0 + +/** + * UDP checksums on or off + * + * \hideinitializer + */ +#define UIP_CONF_UDP_CHECKSUMS 1 + +/** + * uIP statistics on or off + * + * \hideinitializer + */ +#define UIP_CONF_STATISTICS 1 + +/* Here we include the header file for the application(s) we use in + our project. */ +/*#include "smtp.h"*/ +/*#include "hello-world.h"*/ +/*#include "telnetd.h"*/ +#include "webserver.h" +/*#include "dhcpc.h"*/ +/*#include "resolv.h"*/ +/*#include "webclient.h"*/ + +#define UIP_CONF_EXTERNAL_BUFFER + +#endif /* __UIP_CONF_H__ */ + +/** @} */ +/** @} */ diff --git a/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/webserver.h b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/webserver.h new file mode 100644 index 000000000..1acb290b8 --- /dev/null +++ b/20080212/Demo/CORTEX_LM3Sxxxx_IAR_Keil/webserver/webserver.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2002, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: webserver.h,v 1.2 2006/06/11 21:46:38 adam Exp $ + * + */ +#ifndef __WEBSERVER_H__ +#define __WEBSERVER_H__ + +#include "httpd.h" + +typedef struct httpd_state uip_tcp_appstate_t; +/* UIP_APPCALL: the name of the application function. This function + must return void and take no arguments (i.e., C type "void + appfunc(void)"). */ +#ifndef UIP_APPCALL +#define UIP_APPCALL httpd_appcall +#endif + + +#endif /* __WEBSERVER_H__ */ diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/FreeRTOSConfig.h b/20080212/Demo/CORTEX_STM32F103_IAR/FreeRTOSConfig.h new file mode 100644 index 000000000..08494333c --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/FreeRTOSConfig.h @@ -0,0 +1,95 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 72000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 128 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 17 * 1024 ) ) +#define configMAX_TASK_NAME_LEN ( 16 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + +/* This is the raw value as per the Cortex-M3 NVIC. Values can be 255 +(lowest) to 0 (1?) (highest). */ +#define configKERNEL_INTERRUPT_PRIORITY 255 + +/* This is the value being used as per the ST library which permits 16 +priority values, 0 to 15. This must correspond to the +configKERNEL_INTERRUPT_PRIORITY setting. Here 15 corresponds to the lowest +NVIC value of 255. */ +#define configLIBRARY_KERNEL_INTERRUPT_PRIORITY 15 + +#endif /* FREERTOS_CONFIG_H */ + diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/LCD_Message.h b/20080212/Demo/CORTEX_STM32F103_IAR/LCD_Message.h new file mode 100644 index 000000000..2323c015f --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/LCD_Message.h @@ -0,0 +1,502 @@ +#ifndef LCD_MESSAGE_H +#define LCD_MESSAGE_H + +/* The structure passed to the LCD when there is text to display. */ +typedef struct +{ + long xColumn; + signed char *pcMessage; +} xLCDMessage; + +/* The bitmap displayed on the LCD when the LCD task starts. */ +const unsigned portCHAR pcBitmap[] = +{ +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 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+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x25, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0xf0, +0x00, 0x00, 0x01, 0x40, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x3e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x25, 0xbe, +0x4d, 0x42, 0x00 +}; + + +#endif + diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/ParTest/ParTest.c b/20080212/Demo/CORTEX_STM32F103_IAR/ParTest/ParTest.c new file mode 100644 index 000000000..149f12689 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/ParTest/ParTest.c @@ -0,0 +1,126 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +/* FreeRTOS.org includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "partest.h" + +/* Library includes. */ +#include "stm32f10x_lib.h" + +#define partstMAX_OUTPUT_LED ( 4 ) +#define partstFIRST_LED GPIO_Pin_6 + +static unsigned portSHORT usOutputValue = 0; + +/*-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ +GPIO_InitTypeDef GPIO_InitStructure; + + /* Configure PC.06, PC.07, PC.08 and PC.09 as output push-pull */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init( GPIOC, &GPIO_InitStructure ); +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ +unsigned portSHORT usBit; + + vTaskSuspendAll(); + { + if( uxLED < partstMAX_OUTPUT_LED ) + { + usBit = partstFIRST_LED << uxLED; + + if( xValue == pdFALSE ) + { + usBit ^= ( unsigned portSHORT ) 0xffff; + usOutputValue &= usBit; + } + else + { + usOutputValue |= usBit; + } + + GPIO_Write( GPIOC, usOutputValue ); + } + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned portSHORT usBit; + + vTaskSuspendAll(); + { + if( uxLED < partstMAX_OUTPUT_LED ) + { + usBit = partstFIRST_LED << uxLED; + + if( usOutputValue & usBit ) + { + usOutputValue &= ~usBit; + } + else + { + usOutputValue |= usBit; + } + + GPIO_Write( GPIOC, usOutputValue ); + } + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/RTOSDemo.ewd b/20080212/Demo/CORTEX_STM32F103_IAR/RTOSDemo.ewd new file mode 100644 index 000000000..5b6128974 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/RTOSDemo.ewd @@ -0,0 +1,616 @@ + + + + 1 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 15 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IARROM_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + JLINK_ID + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 1 + 1 + 1 + + + + + + + + MACRAIGOR_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin + 0 + + + + + + diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/RTOSDemo.ewp b/20080212/Demo/CORTEX_STM32F103_IAR/RTOSDemo.ewp new file mode 100644 index 000000000..d9127ed12 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/RTOSDemo.ewp @@ -0,0 +1,878 @@ + + + + 1 + + Debug + + ARM + + 1 + + General + 3 + + 14 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 19 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 7 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 5 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Demo files + + $PROJ_DIR$\..\Common\Minimal\BlockQ.c + + + $PROJ_DIR$\..\Common\Minimal\blocktim.c + + + $PROJ_DIR$\..\Common\Minimal\comtest.c + + + $PROJ_DIR$\..\Common\Minimal\death.c + + + $PROJ_DIR$\..\Common\Minimal\flash.c + + + $PROJ_DIR$\..\Common\Minimal\integer.c + + + $PROJ_DIR$\main.c + + + $PROJ_DIR$\ParTest\ParTest.c + + + $PROJ_DIR$\..\Common\Minimal\PollQ.c + + + $PROJ_DIR$\..\Common\Minimal\semtest.c + + + $PROJ_DIR$\serial\serial.c + + + $PROJ_DIR$\spi_flash.c + + + $PROJ_DIR$\stm32f10x_it.c + + + $PROJ_DIR$\timertest.c + + + + FreeRTOS files + + $PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c + + + $PROJ_DIR$\..\..\Source\list.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s + + + $PROJ_DIR$\..\..\Source\queue.c + + + $PROJ_DIR$\..\..\Source\tasks.c + + + + ST Library + + $PROJ_DIR$\STM32F10xFWLib\src\cortexm3_macro.s + + + $PROJ_DIR$\STM32F10xFWLib\src\lcd.c + + + $PROJ_DIR$\STM32F10xFWLib\src\stm32f10x_gpio.c + + + $PROJ_DIR$\STM32F10xFWLib\src\stm32f10x_lib.c + + + $PROJ_DIR$\STM32F10xFWLib\src\stm32f10x_nvic.c + + + $PROJ_DIR$\STM32F10xFWLib\src\stm32f10x_rcc.c + + + $PROJ_DIR$\STM32F10xFWLib\src\stm32f10x_spi.c + + + $PROJ_DIR$\STM32F10xFWLib\src\stm32f10x_systick.c + + + $PROJ_DIR$\STM32F10xFWLib\src\stm32f10x_tim.c + + + $PROJ_DIR$\STM32F10xFWLib\src\stm32f10x_usart.c + + + + System files + + $PROJ_DIR$\stm32f10x_vector.c + + + + + diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/RTOSDemo.eww b/20080212/Demo/CORTEX_STM32F103_IAR/RTOSDemo.eww new file mode 100644 index 000000000..239a9381e --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/RTOSDemo.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\RTOSDemo.ewp + + + + + diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/cortexm3_macro.h b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/cortexm3_macro.h new file mode 100644 index 000000000..c67240eee --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/cortexm3_macro.h @@ -0,0 +1,51 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : cortexm3_macro.h +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : Header file for cortexm3_macro.s. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CORTEXM3_MACRO_H +#define __CORTEXM3_MACRO_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_type.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void __WFI(void); +void __WFE(void); +void __SEV(void); +void __ISB(void); +void __DSB(void); +void __DMB(void); +void __SVC(void); +u32 __MRS_CONTROL(void); +void __MSR_CONTROL(u32 Control); +void __SETPRIMASK(void); +void __RESETPRIMASK(void); +void __SETFAULTMASK(void); +void __RESETFAULTMASK(void); +void __BASEPRICONFIG(u32 NewPriority); +u32 __GetBASEPRI(void); +u16 __REV_HalfWord(u16 Data); +u32 __REV_Word(u32 Data); + +#endif /* __CORTEXM3_MACRO_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/lcd.h b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/lcd.h new file mode 100644 index 000000000..73f44b974 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/lcd.h @@ -0,0 +1,179 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : lcd.h +* Author : MCD Application Team +* Date First Issued : mm/dd/yyyy +* Description : This file contains all the functions prototypes for the +* lcd software driver. +******************************************************************************** +* History: +* mm/dd/yyyy +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __LCD_H +#define __LCD_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_lib.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* LCD Registers */ +#define R0 0x00 +#define R1 0x01 +#define R2 0x02 +#define R3 0x03 +#define R5 0x05 +#define R6 0x06 +#define R13 0x0D +#define R14 0x0E +#define R15 0x0F +#define R16 0x10 +#define R17 0x11 +#define R18 0x12 +#define R19 0x13 +#define R20 0x14 +#define R21 0x15 +#define R22 0x16 +#define R23 0x17 +#define R24 0x18 +#define R25 0x19 +#define R26 0x1A +#define R27 0x1B +#define R28 0x1C +#define R29 0x1D +#define R30 0x1E +#define R31 0x1F +#define R32 0x20 +#define R36 0x24 +#define R37 0x25 +#define R40 0x28 +#define R43 0x2B +#define R45 0x2D +#define R49 0x31 +#define R50 0x32 +#define R51 0x33 +#define R52 0x34 +#define R53 0x35 +#define R55 0x37 +#define R59 0x3B +#define R60 0x3C +#define R61 0x3D +#define R62 0x3E +#define R63 0x3F +#define R64 0x40 +#define R65 0x41 +#define R66 0x42 +#define R67 0x43 +#define R68 0x44 +#define R69 0x45 +#define R70 0x46 +#define R71 0x47 +#define R72 0x48 +#define R73 0x49 +#define R74 0x4A +#define R75 0x4B +#define R76 0x4C +#define R77 0x4D +#define R78 0x4E +#define R79 0x4F +#define R80 0x50 +#define R118 0x76 +#define R134 0x86 +#define R135 0x87 +#define R136 0x88 +#define R137 0x89 +#define R139 0x8B +#define R140 0x8C +#define R141 0x8D +#define R143 0x8F +#define R144 0x90 +#define R145 0x91 +#define R146 0x92 +#define R147 0x93 +#define R148 0x94 +#define R149 0x95 +#define R150 0x96 +#define R151 0x97 +#define R152 0x98 +#define R153 0x99 +#define R154 0x9A +#define R157 0x9D +#define R192 0xC0 +#define R193 0xC1 + +/* LCD Control pins */ +#define CtrlPin_NCS GPIO_Pin_2 /* PB.02 */ +#define CtrlPin_RS GPIO_Pin_7 /* PD.07 */ +#define CtrlPin_NWR GPIO_Pin_15 /* PD.15 */ + +/* LCD color */ +#define White 0xFFFF +#define Black 0x0000 +#define Blue 0x001F +#define Orange 0x051F +#define Red 0xF800 +#define Magenta 0xF81F +#define Green 0x07E0 +#define Cyan 0x7FFF +#define Yellow 0xFFE0 + +#define Line0 0 +#define Line1 24 +#define Line2 48 +#define Line3 72 +#define Line4 96 +#define Line5 120 +#define Line6 144 +#define Line7 168 +#define Line8 192 +#define Line9 216 + +#define Horizontal 0x00 +#define Vertical 0x01 + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +/*----- High layer function -----*/ +void LCD_Init(void); +void LCD_SetTextColor(vu16 Color); +void LCD_SetBackColor(vu16 Color); +void LCD_ClearLine(u8 Line); +void LCD_Clear(void); +void LCD_SetCursor(u8 Xpos, u16 Ypos); +void LCD_DrawChar(u8 Xpos, u16 Ypos, uc16 *c); +void LCD_DisplayChar(u8 Line, u16 Column, u8 Ascii); +void LCD_DisplayStringLine(u8 Line, u8 *ptr); +void LCD_DisplayString(u8 Line, u8 *ptr); +void LCD_ScrollText(u8 Line, u8 *ptr); +void LCD_SetDisplayWindow(u8 Xpos, u16 Ypos, u8 Height, u16 Width); +void LCD_DrawLine(u8 Xpos, u16 Ypos, u16 Length, u8 Direction); +void LCD_DrawRect(u8 Xpos, u16 Ypos, u8 Height, u16 Width); +void LCD_DrawCircle(u8 Xpos, u16 Ypos, u16 Radius); +void LCD_DrawMonoPict(uc32 *Pict); +void LCD_DrawBMP(u32 BmpAddress); + +/*----- Medium layer function -----*/ +void LCD_WriteReg(u8 LCD_Reg, u8 LCD_RegValue); +u8 LCD_ReadReg(u8 LCD_Reg); +void LCD_WriteRAM(u16 RGB_Code); +u16 LCD_ReadRAM(void); +void LCD_PowerOn(void); +void LCD_DisplayOn(void); +void LCD_DisplayOff(void); + +/*----- Low layer function -----*/ +void LCD_CtrlLinesConfig(void); +void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, u16 CtrlPins, BitAction BitVal); +void LCD_SPIConfig(void); + +#endif /* __LCD_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/spi_flash.h b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/spi_flash.h new file mode 100644 index 000000000..5bd8a96ba --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/spi_flash.h @@ -0,0 +1,53 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : spi_flash.h +* Author : MCD Application Team +* Date First Issued : 02/05/2007 +* Description : Header for spi_flash.c file. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __SPI_FLASH_H +#define __SPI_FLASH_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_lib.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +#define Low 0x00 /* Chip Select line low */ +#define High 0x01 /* Chip Select line high */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +/*----- High layer function -----*/ +void SPI_FLASH_Init(void); +void SPI_FLASH_SectorErase(u32 SectorAddr); +void SPI_FLASH_BulkErase(void); +void SPI_FLASH_PageWrite(u8* pBuffer, u32 WriteAddr, u16 NumByteToWrite); +void SPI_FLASH_BufferWrite(u8* pBuffer, u32 WriteAddr, u16 NumByteToWrite); +void SPI_FLASH_BufferRead(u8* pBuffer, u32 ReadAddr, u16 NumByteToRead); +u32 SPI_FLASH_ReadID(void); +void SPI_FLASH_StartReadSequence(u32 ReadAddr); + +/*----- Low layer function -----*/ +u8 SPI_FLASH_ReadByte(void); +void SPI_FLASH_ChipSelect(u8 State); +u8 SPI_FLASH_SendByte(u8 byte); +u16 SPI_FLASH_SendHalfWord(u16 HalfWord); +void SPI_FLASH_WriteEnable(void); +void SPI_FLASH_WaitForWriteEnd(void); + +#endif /* __SPI_FLASH_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_adc.h b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_adc.h new file mode 100644 index 000000000..8e90539f3 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_adc.h @@ -0,0 +1,269 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_adc.h +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file contains all the functions prototypes for the +* ADC firmware library. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_ADC_H +#define __STM32F10x_ADC_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* ADC Init structure definition */ +typedef struct +{ + u32 ADC_Mode; + FunctionalState ADC_ScanConvMode; + FunctionalState ADC_ContinuousConvMode; + u32 ADC_ExternalTrigConv; + u32 ADC_DataAlign; + u8 ADC_NbrOfChannel; +}ADC_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* ADC dual mode -------------------------------------------------------------*/ +#define ADC_Mode_Independent ((u32)0x00000000) +#define ADC_Mode_RegInjecSimult ((u32)0x00010000) +#define ADC_Mode_RegSimult_AlterTrig ((u32)0x00020000) +#define ADC_Mode_InjecSimult_FastInterl ((u32)0x00030000) +#define ADC_Mode_InjecSimult_SlowInterl ((u32)0x00040000) +#define ADC_Mode_InjecSimult ((u32)0x00050000) +#define ADC_Mode_RegSimult ((u32)0x00060000) +#define ADC_Mode_FastInterl ((u32)0x00070000) +#define ADC_Mode_SlowInterl ((u32)0x00080000) +#define ADC_Mode_AlterTrig ((u32)0x00090000) + +#define IS_ADC_MODE(MODE) ((MODE == ADC_Mode_Independent) || \ + (MODE == ADC_Mode_RegInjecSimult) || \ + (MODE == ADC_Mode_RegSimult_AlterTrig) || \ + (MODE == ADC_Mode_InjecSimult_FastInterl) || \ + (MODE == ADC_Mode_InjecSimult_SlowInterl) || \ + (MODE == ADC_Mode_InjecSimult) || \ + (MODE == ADC_Mode_RegSimult) || \ + (MODE == ADC_Mode_FastInterl) || \ + (MODE == ADC_Mode_SlowInterl) || \ + (MODE == ADC_Mode_AlterTrig)) + +/* ADC extrenal trigger sources for regular channels conversion --------------*/ +#define ADC_ExternalTrigConv_T1_CC1 ((u32)0x00000000) +#define ADC_ExternalTrigConv_T1_CC2 ((u32)0x00020000) +#define ADC_ExternalTrigConv_T1_CC3 ((u32)0x00040000) +#define ADC_ExternalTrigConv_T2_CC2 ((u32)0x00060000) +#define ADC_ExternalTrigConv_T3_TRGO ((u32)0x00080000) +#define ADC_ExternalTrigConv_T4_CC4 ((u32)0x000A0000) +#define ADC_ExternalTrigConv_Ext_IT11 ((u32)0x000C0000) +#define ADC_ExternalTrigConv_None ((u32)0x000E0000) + +#define IS_ADC_EXT_TRIG(TRIG1) ((TRIG1 == ADC_ExternalTrigConv_T1_CC1) || \ + (TRIG1 == ADC_ExternalTrigConv_T1_CC2) || \ + (TRIG1 == ADC_ExternalTrigConv_T1_CC3) || \ + (TRIG1 == ADC_ExternalTrigConv_T2_CC2) || \ + (TRIG1 == ADC_ExternalTrigConv_T3_TRGO) || \ + (TRIG1 == ADC_ExternalTrigConv_T4_CC4) || \ + (TRIG1 == ADC_ExternalTrigConv_Ext_IT11) || \ + (TRIG1 == ADC_ExternalTrigConv_None)) + +/* ADC data align ------------------------------------------------------------*/ +#define ADC_DataAlign_Right ((u32)0x00000000) +#define ADC_DataAlign_Left ((u32)0x00000800) + +#define IS_ADC_DATA_ALIGN(ALIGN) ((ALIGN == ADC_DataAlign_Right) || \ + (ALIGN == ADC_DataAlign_Left)) + +/* ADC channels --------------------------------------------------------------*/ +#define ADC_Channel_0 ((u8)0x00) +#define ADC_Channel_1 ((u8)0x01) +#define ADC_Channel_2 ((u8)0x02) +#define ADC_Channel_3 ((u8)0x03) +#define ADC_Channel_4 ((u8)0x04) +#define ADC_Channel_5 ((u8)0x05) +#define ADC_Channel_6 ((u8)0x06) +#define ADC_Channel_7 ((u8)0x07) +#define ADC_Channel_8 ((u8)0x08) +#define ADC_Channel_9 ((u8)0x09) +#define ADC_Channel_10 ((u8)0x0A) +#define ADC_Channel_11 ((u8)0x0B) +#define ADC_Channel_12 ((u8)0x0C) +#define ADC_Channel_13 ((u8)0x0D) +#define ADC_Channel_14 ((u8)0x0E) +#define ADC_Channel_15 ((u8)0x0F) +#define ADC_Channel_16 ((u8)0x10) +#define ADC_Channel_17 ((u8)0x11) + +#define IS_ADC_CHANNEL(CHANNEL) ((CHANNEL == ADC_Channel_0) || (CHANNEL == ADC_Channel_1) || \ + (CHANNEL == ADC_Channel_2) || (CHANNEL == ADC_Channel_3) || \ + (CHANNEL == ADC_Channel_4) || (CHANNEL == ADC_Channel_5) || \ + (CHANNEL == ADC_Channel_6) || (CHANNEL == ADC_Channel_7) || \ + (CHANNEL == ADC_Channel_8) || (CHANNEL == ADC_Channel_9) || \ + (CHANNEL == ADC_Channel_10) || (CHANNEL == ADC_Channel_11) || \ + (CHANNEL == ADC_Channel_12) || (CHANNEL == ADC_Channel_13) || \ + (CHANNEL == ADC_Channel_14) || (CHANNEL == ADC_Channel_15) || \ + (CHANNEL == ADC_Channel_16) || (CHANNEL == ADC_Channel_17)) + +/* ADC sampling times --------------------------------------------------------*/ +#define ADC_SampleTime_1Cycles5 ((u8)0x00) +#define ADC_SampleTime_7Cycles5 ((u8)0x01) +#define ADC_SampleTime_13Cycles5 ((u8)0x02) +#define ADC_SampleTime_28Cycles5 ((u8)0x03) +#define ADC_SampleTime_41Cycles5 ((u8)0x04) +#define ADC_SampleTime_55Cycles5 ((u8)0x05) +#define ADC_SampleTime_71Cycles5 ((u8)0x06) +#define ADC_SampleTime_239Cycles5 ((u8)0x07) + +#define IS_ADC_SAMPLE_TIME(TIME) ((TIME == ADC_SampleTime_1Cycles5) || \ + (TIME == ADC_SampleTime_7Cycles5) || \ + (TIME == ADC_SampleTime_13Cycles5) || \ + (TIME == ADC_SampleTime_28Cycles5) || \ + (TIME == ADC_SampleTime_41Cycles5) || \ + (TIME == ADC_SampleTime_55Cycles5) || \ + (TIME == ADC_SampleTime_71Cycles5) || \ + (TIME == ADC_SampleTime_239Cycles5)) + +/* ADC extrenal trigger sources for injected channels conversion -------------*/ +#define ADC_ExternalTrigInjecConv_T1_TRGO ((u32)0x00000000) +#define ADC_ExternalTrigInjecConv_T1_CC4 ((u32)0x00001000) +#define ADC_ExternalTrigInjecConv_T2_TRGO ((u32)0x00002000) +#define ADC_ExternalTrigInjecConv_T2_CC1 ((u32)0x00003000) +#define ADC_ExternalTrigInjecConv_T3_CC4 ((u32)0x00004000) +#define ADC_ExternalTrigInjecConv_T4_TRGO ((u32)0x00005000) +#define ADC_ExternalTrigInjecConv_Ext_IT15 ((u32)0x00006000) +#define ADC_ExternalTrigInjecConv_None ((u32)0x00007000) + +#define IS_ADC_EXT_INJEC_TRIG(TRIG) ((TRIG == ADC_ExternalTrigInjecConv_T1_TRGO) || \ + (TRIG == ADC_ExternalTrigInjecConv_T1_CC4) || \ + (TRIG == ADC_ExternalTrigInjecConv_T2_TRGO) || \ + (TRIG == ADC_ExternalTrigInjecConv_T2_CC1) || \ + (TRIG == ADC_ExternalTrigInjecConv_T3_CC4) || \ + (TRIG == ADC_ExternalTrigInjecConv_T4_TRGO) || \ + (TRIG == ADC_ExternalTrigInjecConv_Ext_IT15) || \ + (TRIG == ADC_ExternalTrigInjecConv_None)) + +/* ADC injected channel selection --------------------------------------------*/ +#define ADC_InjectedChannel_1 ((u8)0x14) +#define ADC_InjectedChannel_2 ((u8)0x18) +#define ADC_InjectedChannel_3 ((u8)0x1C) +#define ADC_InjectedChannel_4 ((u8)0x20) + +#define IS_ADC_INJECTED_CHANNEL(CHANNEL) ((CHANNEL == ADC_InjectedChannel_1) || \ + (CHANNEL == ADC_InjectedChannel_2) || \ + (CHANNEL == ADC_InjectedChannel_3) || \ + (CHANNEL == ADC_InjectedChannel_4)) + +/* ADC analog watchdog selection ---------------------------------------------*/ +#define ADC_AnalogWatchdog_SingleRegEnable ((u32)0x00800200) +#define ADC_AnalogWatchdog_SingleInjecEnable ((u32)0x00400200) +#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((u32)0x00C00200) +#define ADC_AnalogWatchdog_AllRegEnable ((u32)0x00800000) +#define ADC_AnalogWatchdog_AllInjecEnable ((u32)0x00400000) +#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((u32)0x00C00000) +#define ADC_AnalogWatchdog_None ((u32)0x00000000) + +#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) ((WATCHDOG == ADC_AnalogWatchdog_SingleRegEnable) || \ + (WATCHDOG == ADC_AnalogWatchdog_SingleInjecEnable) || \ + (WATCHDOG == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \ + (WATCHDOG == ADC_AnalogWatchdog_AllRegEnable) || \ + (WATCHDOG == ADC_AnalogWatchdog_AllInjecEnable) || \ + (WATCHDOG == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \ + (WATCHDOG == ADC_AnalogWatchdog_None)) + +/* ADC interrupts definition -------------------------------------------------*/ +#define ADC_IT_EOC ((u16)0x0220) +#define ADC_IT_AWD ((u16)0x0140) +#define ADC_IT_JEOC ((u16)0x0480) + +#define IS_ADC_IT(IT) (((IT & (u16)0xF81F) == 0x00) && (IT != 0x00)) +#define IS_ADC_GET_IT(IT) ((IT == ADC_IT_EOC) || (IT == ADC_IT_AWD) || \ + (IT == ADC_IT_JEOC)) + +/* ADC flags definition ------------------------------------------------------*/ +#define ADC_FLAG_AWD ((u8)0x01) +#define ADC_FLAG_EOC ((u8)0x02) +#define ADC_FLAG_JEOC ((u8)0x04) +#define ADC_FLAG_JSTRT ((u8)0x08) +#define ADC_FLAG_STRT ((u8)0x10) + +#define IS_ADC_CLEAR_FLAG(FLAG) (((FLAG & (u8)0xE0) == 0x00) && (FLAG != 0x00)) +#define IS_ADC_GET_FLAG(FLAG) ((FLAG == ADC_FLAG_AWD) || (FLAG == ADC_FLAG_EOC) || \ + (FLAG == ADC_FLAG_JEOC) || (FLAG == ADC_FLAG_JSTRT) || \ + (FLAG == ADC_FLAG_STRT)) + +/* ADC thresholds ------------------------------------------------------------*/ +#define IS_ADC_THRESHOLD(THRESHOLD) (THRESHOLD <= 0xFFF) + +/* ADC injected offset -------------------------------------------------------*/ +#define IS_ADC_OFFSET(OFFSET) (OFFSET <= 0xFFF) + +/* ADC injected length -------------------------------------------------------*/ +#define IS_ADC_INJECTED_LENGTH(LENGTH) ((LENGTH >= 0x1) && (LENGTH <= 0x4)) + +/* ADC injected rank ---------------------------------------------------------*/ +#define IS_ADC_INJECTED_RANK(RANK) ((RANK >= 0x1) && (RANK <= 0x4)) + +/* ADC regular length --------------------------------------------------------*/ +#define IS_ADC_REGULAR_LENGTH(LENGTH) ((LENGTH >= 0x1) && (LENGTH <= 0x10)) + +/* ADC regular rank ----------------------------------------------------------*/ +#define IS_ADC_REGULAR_RANK(RANK) ((RANK >= 0x1) && (RANK <= 0x10)) + +/* ADC regular discontinuous mode number -------------------------------------*/ +#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) ((NUMBER >= 0x1) && (NUMBER <= 0x8)) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void ADC_DeInit(ADC_TypeDef* ADCx); +void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); +void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_ITConfig(ADC_TypeDef* ADCx, u16 ADC_IT, FunctionalState NewState); +void ADC_ResetCalibration(ADC_TypeDef* ADCx); +FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx); +void ADC_StartCalibration(ADC_TypeDef* ADCx); +FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx); +void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx); +void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, u8 Number); +void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime); +void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +u16 ADC_GetConversionValue(ADC_TypeDef* ADCx); +u32 ADC_GetDualModeConversionValue(void); +void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, u32 ADC_ExternalTrigInjecConv); +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx); +void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime); +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, u8 Length); +void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel, u16 Offset); +u16 ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel); +void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, u32 ADC_AnalogWatchdog); +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, u16 HighThreshold, u16 LowThreshold); +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel); +void ADC_TempSensorCmd(FunctionalState NewState); +FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, u8 ADC_FLAG); +void ADC_ClearFlag(ADC_TypeDef* ADCx, u8 ADC_FLAG); +ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, u16 ADC_IT); +void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, u16 ADC_IT); + +#endif /*__STM32F10x_ADC_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_bkp.h b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_bkp.h new file mode 100644 index 000000000..82224d172 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_bkp.h @@ -0,0 +1,73 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_bkp.h +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file contains all the functions prototypes for the +* BKP firmware library. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_BKP_H +#define __STM32F10x_BKP_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Tamper Pin active level*/ +#define BKP_TamperPinLevel_High ((u16)0x0000) +#define BKP_TamperPinLevel_Low ((u16)0x0001) + +#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) ((LEVEL == BKP_TamperPinLevel_High) || \ + (LEVEL == BKP_TamperPinLevel_Low)) + +/* Data Backup Register */ +#define BKP_DR1 ((u16)0x0004) +#define BKP_DR2 ((u16)0x0008) +#define BKP_DR3 ((u16)0x000C) +#define BKP_DR4 ((u16)0x0010) +#define BKP_DR5 ((u16)0x0014) +#define BKP_DR6 ((u16)0x0018) +#define BKP_DR7 ((u16)0x001C) +#define BKP_DR8 ((u16)0x0020) +#define BKP_DR9 ((u16)0x0024) +#define BKP_DR10 ((u16)0x0028) + +#define IS_BKP_DR(DR) ((DR == BKP_DR1) || (DR == BKP_DR2) || (DR == BKP_DR3) || \ + (DR == BKP_DR4) || (DR == BKP_DR5) || (DR == BKP_DR6) || \ + (DR == BKP_DR7) || (DR == BKP_DR8) || (DR == BKP_DR9) || \ + (DR == BKP_DR10)) + +#define IS_BKP_CALIBRATION_VALUE(VALUE) (VALUE <= 0x7F) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void BKP_DeInit(void); +void BKP_TamperPinLevelConfig(u16 BKP_TamperPinLevel); +void BKP_TamperPinCmd(FunctionalState NewState); +void BKP_ITConfig(FunctionalState NewState); +void BKP_RTCCalibrationClockOutputCmd(FunctionalState NewState); +void BKP_SetRTCCalibrationValue(u8 CalibrationValue); +void BKP_WriteBackupRegister(u16 BKP_DR, u16 Data); +u16 BKP_ReadBackupRegister(u16 BKP_DR); +FlagStatus BKP_GetFlagStatus(void); +void BKP_ClearFlag(void); +ITStatus BKP_GetITStatus(void); +void BKP_ClearITPendingBit(void); + +#endif /* __STM32F10x_BKP_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_can.h b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_can.h new file mode 100644 index 000000000..bd7f53827 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_can.h @@ -0,0 +1,269 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_can.h +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file contains all the functions prototypes for the +* CAN firmware library. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_CAN_H +#define __STM32F10x_CAN_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* CAN init structure definition */ +typedef struct +{ + FunctionalState CAN_TTCM; + FunctionalState CAN_ABOM; + FunctionalState CAN_AWUM; + FunctionalState CAN_NART; + FunctionalState CAN_RFLM; + FunctionalState CAN_TXFP; + u8 CAN_Mode; + u8 CAN_SJW; + u8 CAN_BS1; + u8 CAN_BS2; + u8 CAN_Clock; + u16 CAN_Prescaler; +} CAN_InitTypeDef; + +/* CAN filter init structure definition */ +typedef struct +{ + u8 CAN_FilterNumber; + u8 CAN_FilterMode; + u8 CAN_FilterScale; + u16 CAN_FilterIdHigh; + u16 CAN_FilterIdLow; + u16 CAN_FilterMaskIdHigh; + u16 CAN_FilterMaskIdLow; + u16 CAN_FilterFIFOAssignment; + FunctionalState CAN_FilterActivation; +} CAN_FilterInitTypeDef; + +/* CAN Tx message structure definition */ +typedef struct +{ + u32 StdId; + u32 ExtId; + u8 IDE; + u8 RTR; + u8 DLC; + u8 Data[8]; +} CanTxMsg; + +/* CAN Rx message structure definition */ +typedef struct +{ + u32 StdId; + u32 ExtId; + u8 IDE; + u8 RTR; + u8 DLC; + u8 Data[8]; + u8 FMI; +} CanRxMsg; + +/* Exported constants --------------------------------------------------------*/ + +/* CAN sleep constants */ +#define CANINITFAILED ((u8)0x00) /* CAN initialization failed */ +#define CANINITOK ((u8)0x01) /* CAN initialization failed */ + +/* CAN operating mode */ +#define CAN_Mode_Normal ((u8)0x00) /* normal mode */ +#define CAN_Mode_LoopBack ((u8)0x01) /* loopback mode */ +#define CAN_Mode_Silent ((u8)0x02) /* silent mode */ +#define CAN_Mode_Silent_LoopBack ((u8)0x03) /* loopback combined with silent mode */ + +#define IS_CAN_MODE(MODE) ((MODE == CAN_Mode_Normal) || (MODE == CAN_Mode_LoopBack)|| \ + (MODE == CAN_Mode_Silent) || (MODE == CAN_Mode_Silent_LoopBack)) + +/* CAN synchronisation jump width */ +#define CAN_SJW_0tq ((u8)0x00) /* 0 time quantum */ +#define CAN_SJW_1tq ((u8)0x01) /* 1 time quantum */ +#define CAN_SJW_2tq ((u8)0x02) /* 2 time quantum */ +#define CAN_SJW_3tq ((u8)0x03) /* 3 time quantum */ + +#define IS_CAN_SJW(SJW) ((SJW == CAN_SJW_0tq) || (SJW == CAN_SJW_1tq)|| \ + (SJW == CAN_SJW_2tq) || (SJW == CAN_SJW_3tq)) + +/* time quantum in bit segment 1 */ +#define CAN_BS1_1tq ((u8)0x00) /* 1 time quantum */ +#define CAN_BS1_2tq ((u8)0x01) /* 2 time quantum */ +#define CAN_BS1_3tq ((u8)0x02) /* 3 time quantum */ +#define CAN_BS1_4tq ((u8)0x03) /* 4 time quantum */ +#define CAN_BS1_5tq ((u8)0x04) /* 5 time quantum */ +#define CAN_BS1_6tq ((u8)0x05) /* 6 time quantum */ +#define CAN_BS1_7tq ((u8)0x06) /* 7 time quantum */ +#define CAN_BS1_8tq ((u8)0x07) /* 8 time quantum */ +#define CAN_BS1_9tq ((u8)0x08) /* 9 time quantum */ +#define CAN_BS1_10tq ((u8)0x09) /* 10 time quantum */ +#define CAN_BS1_11tq ((u8)0x0A) /* 11 time quantum */ +#define CAN_BS1_12tq ((u8)0x0B) /* 12 time quantum */ +#define CAN_BS1_13tq ((u8)0x0C) /* 13 time quantum */ +#define CAN_BS1_14tq ((u8)0x0D) /* 14 time quantum */ +#define CAN_BS1_15tq ((u8)0x0E) /* 15 time quantum */ +#define CAN_BS1_16tq ((u8)0x0F) /* 16 time quantum */ + +#define IS_CAN_BS1(BS1) (BS1 <= CAN_BS1_16tq) + +/* time quantum in bit segment 2 */ +#define CAN_BS2_1tq ((u8)0x00) /* 1 time quantum */ +#define CAN_BS2_2tq ((u8)0x01) /* 2 time quantum */ +#define CAN_BS2_3tq ((u8)0x02) /* 3 time quantum */ +#define CAN_BS2_4tq ((u8)0x03) /* 4 time quantum */ +#define CAN_BS2_5tq ((u8)0x04) /* 5 time quantum */ +#define CAN_BS2_6tq ((u8)0x05) /* 6 time quantum */ +#define CAN_BS2_7tq ((u8)0x06) /* 7 time quantum */ +#define CAN_BS2_8tq ((u8)0x07) /* 8 time quantum */ + +#define IS_CAN_BS2(BS2) (BS2 <= CAN_BS2_8tq) + +/* CAN clock selected */ +#define CAN_Clock_8MHz ((u8)0x00) /* 8MHz XTAL clock selected */ +#define CAN_Clock_APB ((u8)0x01) /* APB clock selected */ + +#define IS_CAN_CLOCK(CLOCK) ((CLOCK == CAN_Clock_8MHz) || (CLOCK == CAN_Clock_APB)) + +/* CAN clock prescaler */ +#define IS_CAN_PRESCALER(PRESCALER) ((PRESCALER >= 1) && (PRESCALER <= 1024)) + +/* CAN filter number */ +#define IS_CAN_FILTER_NUMBER(NUMBER) (NUMBER <= 13) + +/* CAN filter mode */ +#define CAN_FilterMode_IdMask ((u8)0x00) /* id/mask mode */ +#define CAN_FilterMode_IdList ((u8)0x01) /* identifier list mode */ + +#define IS_CAN_FILTER_MODE(MODE) ((MODE == CAN_FilterMode_IdMask) || \ + (MODE == CAN_FilterMode_IdList)) + +/* CAN filter scale */ +#define CAN_FilterScale_16bit ((u8)0x00) /* 16-bit filter scale */ +#define CAN_FilterScale_32bit ((u8)0x01) /* 2-bit filter scale */ + +#define IS_CAN_FILTER_SCALE(SCALE) ((SCALE == CAN_FilterScale_16bit) || \ + (SCALE == CAN_FilterScale_32bit)) + +/* CAN filter FIFO assignation */ +#define CAN_FilterFIFO0 ((u8)0x00) /* Filter FIFO 0 assignment for filter x */ +#define CAN_FilterFIFO1 ((u8)0x01) /* Filter FIFO 1 assignment for filter x */ + +#define IS_CAN_FILTER_FIFO(FIFO) ((FIFO == CAN_FilterFIFO0) || \ + (FIFO == CAN_FilterFIFO1)) + +/* CAN Tx */ +#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) (TRANSMITMAILBOX <= ((u8)0x02)) +#define IS_CAN_STDID(STDID) (STDID <= ((u32)0x7FF)) +#define IS_CAN_EXTID(EXTID) (EXTID <= ((u32)0x3FFFF)) +#define IS_CAN_DLC(DLC) (DLC <= ((u8)0x08)) + +/* CAN identifier type */ +#define CAN_ID_STD ((u32)0x00000000) /* Standard Id */ +#define CAN_ID_EXT ((u32)0x00000004) /* Extended Id */ + +#define IS_CAN_IDTYPE(IDTYPE) ((IDTYPE == CAN_ID_STD) || (IDTYPE == CAN_ID_EXT)) + +/* CAN remote transmission request */ +#define CAN_RTR_DATA ((u32)0x00000000) /* Data frame */ +#define CAN_RTR_REMOTE ((u32)0x00000002) /* Remote frame */ + +#define IS_CAN_RTR(RTR) ((RTR == CAN_RTR_DATA) || (RTR == CAN_RTR_REMOTE)) + +/* CAN transmit constants */ +#define CANTXFAILED ((u8)0x00) /* CAN transmission failed */ +#define CANTXOK ((u8)0x01) /* CAN transmission succeeded */ +#define CANTXPENDING ((u8)0x02) /* CAN transmission pending */ +#define CAN_NO_MB ((u8)0x04) /* CAN cell did not provide an empty mailbox */ + +/* CAN receive FIFO number constants */ +#define CAN_FIFO0 ((u8)0x00) /* CAN FIFO0 used to receive */ +#define CAN_FIFO1 ((u8)0x01) /* CAN FIFO1 used to receive */ + +#define IS_CAN_FIFO(FIFO) ((FIFO == CAN_FIFO0) || (FIFO == CAN_FIFO1)) + +/* CAN sleep constants */ +#define CANSLEEPFAILED ((u8)0x00) /* CAN did not enter the sleep mode */ +#define CANSLEEPOK ((u8)0x01) /* CAN entered the sleep mode */ + +/* CAN wake up constants */ +#define CANWAKEUPFAILED ((u8)0x00) /* CAN did not leave the sleep mode */ +#define CANWAKEUPOK ((u8)0x01) /* CAN leaved the sleep mode */ + +/* CAN flags */ +#define CAN_FLAG_EWG ((u32)0x00000001) /* Error Warning Flag */ +#define CAN_FLAG_EPV ((u32)0x00000002) /* Error Passive Flag */ +#define CAN_FLAG_BOF ((u32)0x00000004) /* Bus-Off Flag */ + +#define IS_CAN_FLAG(FLAG) ((FLAG == CAN_FLAG_EWG) || (FLAG == CAN_FLAG_EPV) ||\ + (FLAG == CAN_FLAG_BOF)) + +/* CAN interrupts */ +#define CAN_IT_RQCP0 ((u8)0x05) /* Request completed mailbox 0 */ +#define CAN_IT_RQCP1 ((u8)0x06) /* Request completed mailbox 1 */ +#define CAN_IT_RQCP2 ((u8)0x07) /* Request completed mailbox 2 */ +#define CAN_IT_TME ((u32)0x00000001) /* Transmit mailbox empty */ +#define CAN_IT_FMP0 ((u32)0x00000002) /* FIFO 0 message pending */ +#define CAN_IT_FF0 ((u32)0x00000004) /* FIFO 0 full */ +#define CAN_IT_FOV0 ((u32)0x00000008) /* FIFO 0 overrun */ +#define CAN_IT_FMP1 ((u32)0x00000010) /* FIFO 1 message pending */ +#define CAN_IT_FF1 ((u32)0x00000020) /* FIFO 1 full */ +#define CAN_IT_FOV1 ((u32)0x00000040) /* FIFO 1 overrun */ +#define CAN_IT_EWG ((u32)0x00000100) /* Error warning */ +#define CAN_IT_EPV ((u32)0x00000200) /* Error passive */ +#define CAN_IT_BOF ((u32)0x00000400) /* Bus-off */ +#define CAN_IT_LEC ((u32)0x00000800) /* Last error code */ +#define CAN_IT_ERR ((u32)0x00008000) /* Error */ +#define CAN_IT_WKU ((u32)0x00010000) /* Wake-up */ +#define CAN_IT_SLK ((u32)0x00020000) /* Sleep */ + +#define IS_CAN_IT(IT) ((IT == CAN_IT_RQCP0) || (IT == CAN_IT_RQCP1) ||\ + (IT == CAN_IT_RQCP2) || (IT == CAN_IT_TME) ||\ + (IT == CAN_IT_FMP0) || (IT == CAN_IT_FF0) ||\ + (IT == CAN_IT_FOV0) || (IT == CAN_IT_FMP1) ||\ + (IT == CAN_IT_FF1) || (IT == CAN_IT_FOV1) ||\ + (IT == CAN_IT_EWG) || (IT == CAN_IT_EPV) ||\ + (IT == CAN_IT_BOF) || (IT == CAN_IT_LEC) ||\ + (IT == CAN_IT_ERR) || (IT == CAN_IT_WKU) ||\ + (IT == CAN_IT_SLK)) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported function protypes ----------------------------------------------- */ +void CAN_DeInit(void); +u8 CAN_Init(CAN_InitTypeDef* CAN_InitStruct); +void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct); +void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct); +void CAN_ITConfig(u32 CAN_IT, FunctionalState NewState); +u8 CAN_Transmit(CanTxMsg* TxMessage); +u32 CAN_TransmitStatus(u8 TransmitMailbox); +void CAN_CancelTransmit(u8 Mailbox); +void CAN_FIFORelease(u8 FIFONumber); +u8 CAN_MessagePending(u8 FIFONumber); +void CAN_Receive(u8 FIFONumber, CanRxMsg* RxMessage); +u8 CAN_Sleep(void); +u8 CAN_WakeUp(void); +FlagStatus CAN_GetFlagStatus(u32 CAN_FLAG); +void CAN_ClearFlag(u32 CAN_FLAG); +ITStatus CAN_GetITStatus(u32 CAN_IT); +void CAN_ClearITPendingBit(u32 CAN_IT); + +#endif /* __STM32F10x_CAN_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_dma.h b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_dma.h new file mode 100644 index 000000000..95274ad07 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_dma.h @@ -0,0 +1,224 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_dma.h +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file contains all the functions prototypes for the +* DMA firmware library. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_DMA_H +#define __STM32F10x_DMA_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* DMA Init structure definition */ +typedef struct +{ + u32 DMA_PeripheralBaseAddr; + u32 DMA_MemoryBaseAddr; + u32 DMA_DIR; + u32 DMA_BufferSize; + u32 DMA_PeripheralInc; + u32 DMA_MemoryInc; + u32 DMA_PeripheralDataSize; + u32 DMA_MemoryDataSize; + u32 DMA_Mode; + u32 DMA_Priority; + u32 DMA_M2M; +}DMA_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* DMA data transfer direction -----------------------------------------------*/ +#define DMA_DIR_PeripheralDST ((u32)0x00000010) +#define DMA_DIR_PeripheralSRC ((u32)0x00000000) + +#define IS_DMA_DIR(DIR) ((DIR == DMA_DIR_PeripheralDST) || \ + (DIR == DMA_DIR_PeripheralSRC)) + +/* DMA peripheral incremented mode -------------------------------------------*/ +#define DMA_PeripheralInc_Enable ((u32)0x00000040) +#define DMA_PeripheralInc_Disable ((u32)0x00000000) + +#define IS_DMA_PERIPHERAL_INC_STATE(STATE) ((STATE == DMA_PeripheralInc_Enable) || \ + (STATE == DMA_PeripheralInc_Disable)) + +/* DMA memory incremented mode -----------------------------------------------*/ +#define DMA_MemoryInc_Enable ((u32)0x00000080) +#define DMA_MemoryInc_Disable ((u32)0x00000000) + +#define IS_DMA_MEMORY_INC_STATE(STATE) ((STATE == DMA_MemoryInc_Enable) || \ + (STATE == DMA_MemoryInc_Disable)) + +/* DMA peripheral data size --------------------------------------------------*/ +#define DMA_PeripheralDataSize_Byte ((u32)0x00000000) +#define DMA_PeripheralDataSize_HalfWord ((u32)0x00000100) +#define DMA_PeripheralDataSize_Word ((u32)0x00000200) + +#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) ((SIZE == DMA_PeripheralDataSize_Byte) || \ + (SIZE == DMA_PeripheralDataSize_HalfWord) || \ + (SIZE == DMA_PeripheralDataSize_Word)) + +/* DMA memory data size ------------------------------------------------------*/ +#define DMA_MemoryDataSize_Byte ((u32)0x00000000) +#define DMA_MemoryDataSize_HalfWord ((u32)0x00000400) +#define DMA_MemoryDataSize_Word ((u32)0x00000800) + +#define IS_DMA_MEMORY_DATA_SIZE(SIZE) ((SIZE == DMA_MemoryDataSize_Byte) || \ + (SIZE == DMA_MemoryDataSize_HalfWord) || \ + (SIZE == DMA_MemoryDataSize_Word)) + +/* DMA circular/normal mode --------------------------------------------------*/ +#define DMA_Mode_Circular ((u32)0x00000020) +#define DMA_Mode_Normal ((u32)0x00000000) + +#define IS_DMA_MODE(MODE) ((MODE == DMA_Mode_Circular) || (MODE == DMA_Mode_Normal)) + +/* DMA priority level --------------------------------------------------------*/ +#define DMA_Priority_VeryHigh ((u32)0x00003000) +#define DMA_Priority_High ((u32)0x00002000) +#define DMA_Priority_Medium ((u32)0x00001000) +#define DMA_Priority_Low ((u32)0x00000000) + +#define IS_DMA_PRIORITY(PRIORITY) ((PRIORITY == DMA_Priority_VeryHigh) || \ + (PRIORITY == DMA_Priority_High) || \ + (PRIORITY == DMA_Priority_Medium) || \ + (PRIORITY == DMA_Priority_Low)) + +/* DMA memory to memory ------------------------------------------------------*/ +#define DMA_M2M_Enable ((u32)0x00004000) +#define DMA_M2M_Disable ((u32)0x00000000) + +#define IS_DMA_M2M_STATE(STATE) ((STATE == DMA_M2M_Enable) || (STATE == DMA_M2M_Disable)) + +/* DMA interrupts definition -------------------------------------------------*/ +#define DMA_IT_TC ((u32)0x00000002) +#define DMA_IT_HT ((u32)0x00000004) +#define DMA_IT_TE ((u32)0x00000008) + +#define IS_DMA_CONFIG_IT(IT) (((IT & 0xFFFFFFF1) == 0x00) && (IT != 0x00)) + +#define DMA_IT_GL1 ((u32)0x00000001) +#define DMA_IT_TC1 ((u32)0x00000002) +#define DMA_IT_HT1 ((u32)0x00000004) +#define DMA_IT_TE1 ((u32)0x00000008) +#define DMA_IT_GL2 ((u32)0x00000010) +#define DMA_IT_TC2 ((u32)0x00000020) +#define DMA_IT_HT2 ((u32)0x00000040) +#define DMA_IT_TE2 ((u32)0x00000080) +#define DMA_IT_GL3 ((u32)0x00000100) +#define DMA_IT_TC3 ((u32)0x00000200) +#define DMA_IT_HT3 ((u32)0x00000400) +#define DMA_IT_TE3 ((u32)0x00000800) +#define DMA_IT_GL4 ((u32)0x00001000) +#define DMA_IT_TC4 ((u32)0x00002000) +#define DMA_IT_HT4 ((u32)0x00004000) +#define DMA_IT_TE4 ((u32)0x00008000) +#define DMA_IT_GL5 ((u32)0x00010000) +#define DMA_IT_TC5 ((u32)0x00020000) +#define DMA_IT_HT5 ((u32)0x00040000) +#define DMA_IT_TE5 ((u32)0x00080000) +#define DMA_IT_GL6 ((u32)0x00100000) +#define DMA_IT_TC6 ((u32)0x00200000) +#define DMA_IT_HT6 ((u32)0x00400000) +#define DMA_IT_TE6 ((u32)0x00800000) +#define DMA_IT_GL7 ((u32)0x01000000) +#define DMA_IT_TC7 ((u32)0x02000000) +#define DMA_IT_HT7 ((u32)0x04000000) +#define DMA_IT_TE7 ((u32)0x08000000) + +#define IS_DMA_CLEAR_IT(IT) (((IT & 0xF0000000) == 0x00) && (IT != 0x00)) +#define IS_DMA_GET_IT(IT) ((IT == DMA_IT_GL1) || (IT == DMA_IT_TC1) || \ + (IT == DMA_IT_HT1) || (IT == DMA_IT_TE1) || \ + (IT == DMA_IT_GL2) || (IT == DMA_IT_TC2) || \ + (IT == DMA_IT_HT2) || (IT == DMA_IT_TE2) || \ + (IT == DMA_IT_GL3) || (IT == DMA_IT_TC3) || \ + (IT == DMA_IT_HT3) || (IT == DMA_IT_TE3) || \ + (IT == DMA_IT_GL4) || (IT == DMA_IT_TC4) || \ + (IT == DMA_IT_HT4) || (IT == DMA_IT_TE4) || \ + (IT == DMA_IT_GL5) || (IT == DMA_IT_TC5) || \ + (IT == DMA_IT_HT5) || (IT == DMA_IT_TE5) || \ + (IT == DMA_IT_GL6) || (IT == DMA_IT_TC6) || \ + (IT == DMA_IT_HT6) || (IT == DMA_IT_TE6) || \ + (IT == DMA_IT_GL7) || (IT == DMA_IT_TC7) || \ + (IT == DMA_IT_HT7) || (IT == DMA_IT_TE7)) + +/* DMA flags definition ------------------------------------------------------*/ +#define DMA_FLAG_GL1 ((u32)0x00000001) +#define DMA_FLAG_TC1 ((u32)0x00000002) +#define DMA_FLAG_HT1 ((u32)0x00000004) +#define DMA_FLAG_TE1 ((u32)0x00000008) +#define DMA_FLAG_GL2 ((u32)0x00000010) +#define DMA_FLAG_TC2 ((u32)0x00000020) +#define DMA_FLAG_HT2 ((u32)0x00000040) +#define DMA_FLAG_TE2 ((u32)0x00000080) +#define DMA_FLAG_GL3 ((u32)0x00000100) +#define DMA_FLAG_TC3 ((u32)0x00000200) +#define DMA_FLAG_HT3 ((u32)0x00000400) +#define DMA_FLAG_TE3 ((u32)0x00000800) +#define DMA_FLAG_GL4 ((u32)0x00001000) +#define DMA_FLAG_TC4 ((u32)0x00002000) +#define DMA_FLAG_HT4 ((u32)0x00004000) +#define DMA_FLAG_TE4 ((u32)0x00008000) +#define DMA_FLAG_GL5 ((u32)0x00010000) +#define DMA_FLAG_TC5 ((u32)0x00020000) +#define DMA_FLAG_HT5 ((u32)0x00040000) +#define DMA_FLAG_TE5 ((u32)0x00080000) +#define DMA_FLAG_GL6 ((u32)0x00100000) +#define DMA_FLAG_TC6 ((u32)0x00200000) +#define DMA_FLAG_HT6 ((u32)0x00400000) +#define DMA_FLAG_TE6 ((u32)0x00800000) +#define DMA_FLAG_GL7 ((u32)0x01000000) +#define DMA_FLAG_TC7 ((u32)0x02000000) +#define DMA_FLAG_HT7 ((u32)0x04000000) +#define DMA_FLAG_TE7 ((u32)0x08000000) + +#define IS_DMA_CLEAR_FLAG(FLAG) (((FLAG & 0xF0000000) == 0x00) && (FLAG != 0x00)) +#define IS_DMA_GET_FLAG(FLAG) ((FLAG == DMA_FLAG_GL1) || (FLAG == DMA_FLAG_TC1) || \ + (FLAG == DMA_FLAG_HT1) || (FLAG == DMA_FLAG_TE1) || \ + (FLAG == DMA_FLAG_GL2) || (FLAG == DMA_FLAG_TC2) || \ + (FLAG == DMA_FLAG_HT2) || (FLAG == DMA_FLAG_TE2) || \ + (FLAG == DMA_FLAG_GL3) || (FLAG == DMA_FLAG_TC3) || \ + (FLAG == DMA_FLAG_HT3) || (FLAG == DMA_FLAG_TE3) || \ + (FLAG == DMA_FLAG_GL4) || (FLAG == DMA_FLAG_TC4) || \ + (FLAG == DMA_FLAG_HT4) || (FLAG == DMA_FLAG_TE4) || \ + (FLAG == DMA_FLAG_GL5) || (FLAG == DMA_FLAG_TC5) || \ + (FLAG == DMA_FLAG_HT5) || (FLAG == DMA_FLAG_TE5) || \ + (FLAG == DMA_FLAG_GL6) || (FLAG == DMA_FLAG_TC6) || \ + (FLAG == DMA_FLAG_HT6) || (FLAG == DMA_FLAG_TE6) || \ + (FLAG == DMA_FLAG_GL7) || (FLAG == DMA_FLAG_TC7) || \ + (FLAG == DMA_FLAG_HT7) || (FLAG == DMA_FLAG_TE7)) + +/* DMA Buffer Size -----------------------------------------------------------*/ +#define IS_DMA_BUFFER_SIZE(SIZE) ((SIZE >= 0x1) && (SIZE < 0x10000)) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void DMA_DeInit(DMA_Channel_TypeDef* DMA_Channelx); +void DMA_Init(DMA_Channel_TypeDef* DMA_Channelx, DMA_InitTypeDef* DMA_InitStruct); +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); +void DMA_Cmd(DMA_Channel_TypeDef* DMA_Channelx, FunctionalState NewState); +void DMA_ITConfig(DMA_Channel_TypeDef* DMA_Channelx, u32 DMA_IT, FunctionalState NewState); +u16 DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMA_Channelx); +FlagStatus DMA_GetFlagStatus(u32 DMA_FLAG); +void DMA_ClearFlag(u32 DMA_FLAG); +ITStatus DMA_GetITStatus(u32 DMA_IT); +void DMA_ClearITPendingBit(u32 DMA_IT); + +#endif /*__STM32F10x_DMA_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_exti.h b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_exti.h new file mode 100644 index 000000000..2c6d4b646 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_exti.h @@ -0,0 +1,111 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_exti.h +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file contains all the functions prototypes for the +* EXTI firmware library. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_EXTI_H +#define __STM32F10x_EXTI_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* EXTI mode enumeration -----------------------------------------------------*/ +typedef enum +{ + EXTI_Mode_Interrupt = 0x00, + EXTI_Mode_Event = 0x04 +}EXTIMode_TypeDef; + +#define IS_EXTI_MODE(MODE) ((MODE == EXTI_Mode_Interrupt) || (MODE == EXTI_Mode_Event)) + +/* EXTI Trigger enumeration --------------------------------------------------*/ +typedef enum +{ + EXTI_Trigger_Rising = 0x08, + EXTI_Trigger_Falling = 0x0C, + EXTI_Trigger_Rising_Falling = 0x10 +}EXTITrigger_TypeDef; + +#define IS_EXTI_TRIGGER(TRIGGER) ((TRIGGER == EXTI_Trigger_Rising) || \ + (TRIGGER == EXTI_Trigger_Falling) || \ + (TRIGGER == EXTI_Trigger_Rising_Falling)) + +/* EXTI Init Structure definition --------------------------------------------*/ +typedef struct +{ + u32 EXTI_Line; + EXTIMode_TypeDef EXTI_Mode; + EXTITrigger_TypeDef EXTI_Trigger; + FunctionalState EXTI_LineCmd; +}EXTI_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* EXTI Lines ----------------------------------------------------------------*/ +#define EXTI_Line0 ((u32)0x00001) /* External interrupt line 0 */ +#define EXTI_Line1 ((u32)0x00002) /* External interrupt line 1 */ +#define EXTI_Line2 ((u32)0x00004) /* External interrupt line 2 */ +#define EXTI_Line3 ((u32)0x00008) /* External interrupt line 3 */ +#define EXTI_Line4 ((u32)0x00010) /* External interrupt line 4 */ +#define EXTI_Line5 ((u32)0x00020) /* External interrupt line 5 */ +#define EXTI_Line6 ((u32)0x00040) /* External interrupt line 6 */ +#define EXTI_Line7 ((u32)0x00080) /* External interrupt line 7 */ +#define EXTI_Line8 ((u32)0x00100) /* External interrupt line 8 */ +#define EXTI_Line9 ((u32)0x00200) /* External interrupt line 9 */ +#define EXTI_Line10 ((u32)0x00400) /* External interrupt line 10 */ +#define EXTI_Line11 ((u32)0x00800) /* External interrupt line 11 */ +#define EXTI_Line12 ((u32)0x01000) /* External interrupt line 12 */ +#define EXTI_Line13 ((u32)0x02000) /* External interrupt line 13 */ +#define EXTI_Line14 ((u32)0x04000) /* External interrupt line 14 */ +#define EXTI_Line15 ((u32)0x08000) /* External interrupt line 15 */ +#define EXTI_Line16 ((u32)0x10000) /* External interrupt line 16 + Connected to the PVD Output */ +#define EXTI_Line17 ((u32)0x20000) /* External interrupt line 17 + Connected to the RTC Alarm event */ +#define EXTI_Line18 ((u32)0x40000) /* External interrupt line 18 + Connected to the USB Wakeup from + suspend event */ + +#define IS_EXTI_LINE(LINE) (((LINE & (u32)0xFFF80000) == 0x00) && (LINE != (u16)0x00)) + +#define IS_GET_EXTI_LINE(LINE) ((LINE == EXTI_Line0) || (LINE == EXTI_Line1) || \ + (LINE == EXTI_Line2) || (LINE == EXTI_Line3) || \ + (LINE == EXTI_Line4) || (LINE == EXTI_Line5) || \ + (LINE == EXTI_Line6) || (LINE == EXTI_Line7) || \ + (LINE == EXTI_Line8) || (LINE == EXTI_Line9) || \ + (LINE == EXTI_Line10) || (LINE == EXTI_Line11) || \ + (LINE == EXTI_Line12) || (LINE == EXTI_Line13) || \ + (LINE == EXTI_Line14) || (LINE == EXTI_Line15) || \ + (LINE == EXTI_Line16) || (LINE == EXTI_Line17) || \ + (LINE == EXTI_Line18)) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void EXTI_DeInit(void); +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_GenerateSWInterrupt(u32 EXTI_Line); +FlagStatus EXTI_GetFlagStatus(u32 EXTI_Line); +void EXTI_ClearFlag(u32 EXTI_Line); +ITStatus EXTI_GetITStatus(u32 EXTI_Line); +void EXTI_ClearITPendingBit(u32 EXTI_Line); + +#endif /* __STM32F10x_EXTI_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_gpio.h b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_gpio.h new file mode 100644 index 000000000..bbe59f544 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_gpio.h @@ -0,0 +1,195 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_gpio.h +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file contains all the functions prototypes for the +* GPIO firmware library. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_GPIO_H +#define __STM32F10x_GPIO_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* Output Maximum frequency selection ----------------------------------------*/ +typedef enum +{ + GPIO_Speed_10MHz = 1, + GPIO_Speed_2MHz, + GPIO_Speed_50MHz +}GPIOSpeed_TypeDef; + +#define IS_GPIO_SPEED(SPEED) ((SPEED == GPIO_Speed_10MHz) || (SPEED == GPIO_Speed_2MHz) || \ + (SPEED == GPIO_Speed_50MHz)) + +/* Configuration Mode enumeration --------------------------------------------*/ +typedef enum +{ GPIO_Mode_AIN = 0x0, + GPIO_Mode_IN_FLOATING = 0x04, + GPIO_Mode_IPD = 0x28, + GPIO_Mode_IPU = 0x48, + GPIO_Mode_Out_OD = 0x14, + GPIO_Mode_Out_PP = 0x10, + GPIO_Mode_AF_OD = 0x1C, + GPIO_Mode_AF_PP = 0x18 +}GPIOMode_TypeDef; + +#define IS_GPIO_MODE(MODE) ((MODE == GPIO_Mode_AIN) || (MODE == GPIO_Mode_IN_FLOATING) || \ + (MODE == GPIO_Mode_IPD) || (MODE == GPIO_Mode_IPU) || \ + (MODE == GPIO_Mode_Out_OD) || (MODE == GPIO_Mode_Out_PP) || \ + (MODE == GPIO_Mode_AF_OD) || (MODE == GPIO_Mode_AF_PP)) + +/* GPIO Init structure definition */ +typedef struct +{ + u16 GPIO_Pin; + GPIOSpeed_TypeDef GPIO_Speed; + GPIOMode_TypeDef GPIO_Mode; +}GPIO_InitTypeDef; + +/* Bit_SET and Bit_RESET enumeration -----------------------------------------*/ +typedef enum +{ Bit_RESET = 0, + Bit_SET +}BitAction; +#define IS_GPIO_BIT_ACTION(ACTION) ((ACTION == Bit_RESET) || (ACTION == Bit_SET)) + +/* Exported constants --------------------------------------------------------*/ +/* GPIO pins define ----------------------------------------------------------*/ +#define GPIO_Pin_0 ((u16)0x0001) /* Pin 0 selected */ +#define GPIO_Pin_1 ((u16)0x0002) /* Pin 1 selected */ +#define GPIO_Pin_2 ((u16)0x0004) /* Pin 2 selected */ +#define GPIO_Pin_3 ((u16)0x0008) /* Pin 3 selected */ +#define GPIO_Pin_4 ((u16)0x0010) /* Pin 4 selected */ +#define GPIO_Pin_5 ((u16)0x0020) /* Pin 5 selected */ +#define GPIO_Pin_6 ((u16)0x0040) /* Pin 6 selected */ +#define GPIO_Pin_7 ((u16)0x0080) /* Pin 7 selected */ +#define GPIO_Pin_8 ((u16)0x0100) /* Pin 8 selected */ +#define GPIO_Pin_9 ((u16)0x0200) /* Pin 9 selected */ +#define GPIO_Pin_10 ((u16)0x0400) /* Pin 10 selected */ +#define GPIO_Pin_11 ((u16)0x0800) /* Pin 11 selected */ +#define GPIO_Pin_12 ((u16)0x1000) /* Pin 12 selected */ +#define GPIO_Pin_13 ((u16)0x2000) /* Pin 13 selected */ +#define GPIO_Pin_14 ((u16)0x4000) /* Pin 14 selected */ +#define GPIO_Pin_15 ((u16)0x8000) /* Pin 15 selected */ +#define GPIO_Pin_All ((u16)0xFFFF) /* All pins selected */ + +#define IS_GPIO_PIN(PIN) (((PIN & (u16)0x00) == 0x00) && (PIN != (u16)0x00)) + +/* GPIO Remap define ---------------------------------------------------------*/ +#define GPIO_Remap_SPI1 ((u32)0x00000001) /* SPI1 Alternate Function mapping */ +#define GPIO_Remap_I2C1 ((u32)0x00000002) /* I2C1 Alternate Function mapping */ +#define GPIO_Remap_USART1 ((u32)0x00000004) /* USART1 Alternate Function mapping */ +#define GPIO_Remap_USART2 ((u32)0x00000008) /* USART2 Alternate Function mapping */ +#define GPIO_PartialRemap_USART3 ((u32)0x00140010) /* USART3 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART3 ((u32)0x00140030) /* USART3 Full Alternate Function mapping */ +#define GPIO_PartialRemap_TIM1 ((u32)0x00160040) /* TIM1 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM1 ((u32)0x001600C0) /* TIM1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_TIM2 ((u32)0x00180100) /* TIM2 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM2 ((u32)0x00180200) /* TIM2 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_TIM2 ((u32)0x00180300) /* TIM2 Full Alternate Function mapping */ +#define GPIO_PartialRemap_TIM3 ((u32)0x001A0800) /* TIM3 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM3 ((u32)0x001A0C00) /* TIM3 Full Alternate Function mapping */ +#define GPIO_Remap_TIM4 ((u32)0x00001000) /* TIM4 Alternate Function mapping */ +#define GPIO_Remap1_CAN ((u32)0x001D2000) /* CAN Alternate Function mapping */ +#define GPIO_Remap2_CAN ((u32)0x001D6000) /* CAN Alternate Function mapping */ +#define GPIO_Remap_PD01 ((u32)0x00008000) /* PD01 Alternate Function mapping */ +#define GPIO_Remap_SWJ_NoJTRST ((u32)0x00300100) /* Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */ +#define GPIO_Remap_SWJ_JTAGDisable ((u32)0x00300200) /* JTAG-DP Disabled and SW-DP Enabled */ +#define GPIO_Remap_SWJ_Disable ((u32)0x00300400) /* Full SWJ Disabled (JTAG-DP + SW-DP) */ + +#define IS_GPIO_REMAP(REMAP) ((REMAP == GPIO_Remap_SPI1) || (REMAP == GPIO_Remap_I2C1) || \ + (REMAP == GPIO_Remap_USART1) || (REMAP == GPIO_Remap_USART2) || \ + (REMAP == GPIO_PartialRemap_USART3) || (REMAP == GPIO_FullRemap_USART3) || \ + (REMAP == GPIO_PartialRemap_TIM1) || (REMAP == GPIO_FullRemap_TIM1) || \ + (REMAP == GPIO_PartialRemap1_TIM2) || (REMAP == GPIO_PartialRemap2_TIM2) || \ + (REMAP == GPIO_FullRemap_TIM2) || (REMAP == GPIO_PartialRemap_TIM3) || \ + (REMAP == GPIO_FullRemap_TIM3) || (REMAP == GPIO_Remap_TIM4) || \ + (REMAP == GPIO_Remap1_CAN) || (REMAP == GPIO_Remap2_CAN) || \ + (REMAP == GPIO_Remap_PD01) || (REMAP == GPIO_Remap_SWJ_NoJTRST) || \ + (REMAP == GPIO_Remap_SWJ_JTAGDisable) || (REMAP == GPIO_Remap_SWJ_Disable)) + +/* GPIO Port Sources ---------------------------------------------------------*/ +#define GPIO_PortSourceGPIOA ((u8)0x00) +#define GPIO_PortSourceGPIOB ((u8)0x01) +#define GPIO_PortSourceGPIOC ((u8)0x02) +#define GPIO_PortSourceGPIOD ((u8)0x03) +#define GPIO_PortSourceGPIOE ((u8)0x04) + +#define IS_GPIO_PORT_SOURCE(PORTSOURCE) ((PORTSOURCE == GPIO_PortSourceGPIOA) || \ + (PORTSOURCE == GPIO_PortSourceGPIOB) || \ + (PORTSOURCE == GPIO_PortSourceGPIOC) || \ + (PORTSOURCE == GPIO_PortSourceGPIOD) || \ + (PORTSOURCE == GPIO_PortSourceGPIOE)) + +/* GPIO Pin sources ----------------------------------------------------------*/ +#define GPIO_PinSource0 ((u8)0x00) +#define GPIO_PinSource1 ((u8)0x01) +#define GPIO_PinSource2 ((u8)0x02) +#define GPIO_PinSource3 ((u8)0x03) +#define GPIO_PinSource4 ((u8)0x04) +#define GPIO_PinSource5 ((u8)0x05) +#define GPIO_PinSource6 ((u8)0x06) +#define GPIO_PinSource7 ((u8)0x07) +#define GPIO_PinSource8 ((u8)0x08) +#define GPIO_PinSource9 ((u8)0x09) +#define GPIO_PinSource10 ((u8)0x0A) +#define GPIO_PinSource11 ((u8)0x0B) +#define GPIO_PinSource12 ((u8)0x0C) +#define GPIO_PinSource13 ((u8)0x0D) +#define GPIO_PinSource14 ((u8)0x0E) +#define GPIO_PinSource15 ((u8)0x0F) + +#define IS_GPIO_PIN_SOURCE(PINSOURCE) ((PINSOURCE == GPIO_PinSource0) || \ + (PINSOURCE == GPIO_PinSource1) || \ + (PINSOURCE == GPIO_PinSource2) || \ + (PINSOURCE == GPIO_PinSource3) || \ + (PINSOURCE == GPIO_PinSource4) || \ + (PINSOURCE == GPIO_PinSource5) || \ + (PINSOURCE == GPIO_PinSource6) || \ + (PINSOURCE == GPIO_PinSource7) || \ + (PINSOURCE == GPIO_PinSource8) || \ + (PINSOURCE == GPIO_PinSource9) || \ + (PINSOURCE == GPIO_PinSource10) || \ + (PINSOURCE == GPIO_PinSource11) || \ + (PINSOURCE == GPIO_PinSource12) || \ + (PINSOURCE == GPIO_PinSource13) || \ + (PINSOURCE == GPIO_PinSource14) || \ + (PINSOURCE == GPIO_PinSource15)) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void GPIO_DeInit(GPIO_TypeDef* GPIOx); +void GPIO_AFIODeInit(void); +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); +u8 GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin); +u16 GPIO_ReadInputData(GPIO_TypeDef* GPIOx); +u8 GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin); +u16 GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin, BitAction BitVal); +void GPIO_Write(GPIO_TypeDef* GPIOx, u16 PortVal); +void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, u16 GPIO_Pin); +void GPIO_EventOutputConfig(u8 GPIO_PortSource, u8 GPIO_PinSource); +void GPIO_EventOutputCmd(FunctionalState NewState); +void GPIO_PinRemapConfig(u32 GPIO_Remap, FunctionalState NewState); +void GPIO_EXTILineConfig(u8 GPIO_PortSource, u8 GPIO_PinSource); + +#endif /* __STM32F10x_GPIO_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_i2c.h b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_i2c.h new file mode 100644 index 000000000..d0d000cba --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_i2c.h @@ -0,0 +1,286 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_i2c.h +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file contains all the functions prototypes for the +* I2C firmware library. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_I2C_H +#define __STM32F10x_I2C_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* I2C Init structure definition */ +typedef struct +{ + u16 I2C_Mode; + u16 I2C_DutyCycle; + u16 I2C_OwnAddress1; + u16 I2C_Ack; + u16 I2C_AcknowledgedAddress; + u32 I2C_ClockSpeed; +}I2C_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* I2C modes */ +#define I2C_Mode_I2C ((u16)0x0000) +#define I2C_Mode_SMBusDevice ((u16)0x0002) +#define I2C_Mode_SMBusHost ((u16)0x000A) + +#define IS_I2C_MODE(MODE) ((MODE == I2C_Mode_I2C) || \ + (MODE == I2C_Mode_SMBusDevice) || \ + (MODE == I2C_Mode_SMBusHost)) +/* I2C duty cycle in fast mode */ +#define I2C_DutyCycle_16_9 ((u16)0x4000) +#define I2C_DutyCycle_2 ((u16)0xBFFF) + +#define IS_I2C_DUTY_CYCLE(CYCLE) ((CYCLE == I2C_DutyCycle_16_9) || \ + (CYCLE == I2C_DutyCycle_2)) + +/* I2C cknowledgementy */ +#define I2C_Ack_Enable ((u16)0x0400) +#define I2C_Ack_Disable ((u16)0x0000) + +#define IS_I2C_ACK_STATE(STATE) ((STATE == I2C_Ack_Enable) || \ + (STATE == I2C_Ack_Disable)) + +/* I2C transfer direction */ +#define I2C_Direction_Transmitter ((u8)0x00) +#define I2C_Direction_Receiver ((u8)0x01) + +#define IS_I2C_DIRECTION(DIRECTION) ((DIRECTION == I2C_Direction_Transmitter) || \ + (DIRECTION == I2C_Direction_Receiver)) + +/* I2C acknowledged address defines */ +#define I2C_AcknowledgedAddress_7bit ((u16)0x4000) +#define I2C_AcknowledgedAddress_10bit ((u16)0xC000) + +#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) ((ADDRESS == I2C_AcknowledgedAddress_7bit) || \ + (ADDRESS == I2C_AcknowledgedAddress_10bit)) + +/* I2C registers */ +#define I2C_Register_CR1 ((u8)0x00) +#define I2C_Register_CR2 ((u8)0x04) +#define I2C_Register_OAR1 ((u8)0x08) +#define I2C_Register_OAR2 ((u8)0x0C) +#define I2C_Register_DR ((u8)0x10) +#define I2C_Register_SR1 ((u8)0x14) +#define I2C_Register_SR2 ((u8)0x18) +#define I2C_Register_CCR ((u8)0x1C) +#define I2C_Register_TRISE ((u8)0x20) + +#define IS_I2C_REGISTER(REGISTER) ((REGISTER == I2C_Register_CR1) || \ + (REGISTER == I2C_Register_CR2) || \ + (REGISTER == I2C_Register_OAR1) || \ + (REGISTER == I2C_Register_OAR2) || \ + (REGISTER == I2C_Register_DR) || \ + (REGISTER == I2C_Register_SR1) || \ + (REGISTER == I2C_Register_SR2) || \ + (REGISTER == I2C_Register_CCR) || \ + (REGISTER == I2C_Register_TRISE)) + +/* I2C SMBus alert pin level */ +#define I2C_SMBusAlert_Low ((u16)0x2000) +#define I2C_SMBusAlert_High ((u16)0xCFFF) + +#define IS_I2C_SMBUS_ALERT(ALERT) ((ALERT == I2C_SMBusAlert_Low) || \ + (ALERT == I2C_SMBusAlert_High)) + +/* I2C PEC position */ +#define I2C_PECPosition_Next ((u16)0x0800) +#define I2C_PECPosition_Current ((u16)0xF7FF) + +#define IS_I2C_PEC_POSITION(POSITION) ((POSITION == I2C_PECPosition_Next) || \ + (POSITION == I2C_PECPosition_Current)) + +/* I2C interrupts definition */ +#define I2C_IT_BUF ((u16)0x0400) +#define I2C_IT_EVT ((u16)0x0200) +#define I2C_IT_ERR ((u16)0x0100) + +#define IS_I2C_CONFIG_IT(IT) (((IT & (u16)0xF8FF) == 0x00) && (IT != 0x00)) + +/* I2C interrupts definition */ +#define I2C_IT_SMBALERT ((u32)0x10008000) +#define I2C_IT_TIMEOUT ((u32)0x10004000) +#define I2C_IT_PECERR ((u32)0x10001000) +#define I2C_IT_OVR ((u32)0x10000800) +#define I2C_IT_AF ((u32)0x10000400) +#define I2C_IT_ARLO ((u32)0x10000200) +#define I2C_IT_BERR ((u32)0x10000100) +#define I2C_IT_TXE ((u32)0x00000080) +#define I2C_IT_RXNE ((u32)0x00000040) +#define I2C_IT_STOPF ((u32)0x60000010) +#define I2C_IT_ADD10 ((u32)0x20000008) +#define I2C_IT_BTF ((u32)0x60000004) +#define I2C_IT_ADDR ((u32)0xA0000002) +#define I2C_IT_SB ((u32)0x20000001) + +#define IS_I2C_CLEAR_IT(IT) ((IT == I2C_IT_SMBALERT) || (IT == I2C_IT_TIMEOUT) || \ + (IT == I2C_IT_PECERR) || (IT == I2C_IT_OVR) || \ + (IT == I2C_IT_AF) || (IT == I2C_IT_ARLO) || \ + (IT == I2C_IT_BERR) || (IT == I2C_IT_STOPF) || \ + (IT == I2C_IT_ADD10) || (IT == I2C_IT_BTF) || \ + (IT == I2C_IT_ADDR) || (IT == I2C_IT_SB)) + +#define IS_I2C_GET_IT(IT) ((IT == I2C_IT_SMBALERT) || (IT == I2C_IT_TIMEOUT) || \ + (IT == I2C_IT_PECERR) || (IT == I2C_IT_OVR) || \ + (IT == I2C_IT_AF) || (IT == I2C_IT_ARLO) || \ + (IT == I2C_IT_BERR) || (IT == I2C_IT_TXE) || \ + (IT == I2C_IT_RXNE) || (IT == I2C_IT_STOPF) || \ + (IT == I2C_IT_ADD10) || (IT == I2C_IT_BTF) || \ + (IT == I2C_IT_ADDR) || (IT == I2C_IT_SB)) + +/* I2C flags definition */ +#define I2C_FLAG_DUALF ((u32)0x00800000) +#define I2C_FLAG_SMBHOST ((u32)0x00400000) +#define I2C_FLAG_SMBDEFAULT ((u32)0x00200000) +#define I2C_FLAG_GENCALL ((u32)0x00100000) +#define I2C_FLAG_TRA ((u32)0x00040000) +#define I2C_FLAG_BUSY ((u32)0x00020000) +#define I2C_FLAG_MSL ((u32)0x00010000) +#define I2C_FLAG_SMBALERT ((u32)0x10008000) +#define I2C_FLAG_TIMEOUT ((u32)0x10004000) +#define I2C_FLAG_PECERR ((u32)0x10001000) +#define I2C_FLAG_OVR ((u32)0x10000800) +#define I2C_FLAG_AF ((u32)0x10000400) +#define I2C_FLAG_ARLO ((u32)0x10000200) +#define I2C_FLAG_BERR ((u32)0x10000100) +#define I2C_FLAG_TXE ((u32)0x00000080) +#define I2C_FLAG_RXNE ((u32)0x00000040) +#define I2C_FLAG_STOPF ((u32)0x60000010) +#define I2C_FLAG_ADD10 ((u32)0x20000008) +#define I2C_FLAG_BTF ((u32)0x60000004) +#define I2C_FLAG_ADDR ((u32)0xA0000002) +#define I2C_FLAG_SB ((u32)0x20000001) + +#define IS_I2C_CLEAR_FLAG(FLAG) ((FLAG == I2C_FLAG_SMBALERT) || (FLAG == I2C_FLAG_TIMEOUT) || \ + (FLAG == I2C_FLAG_PECERR) || (FLAG == I2C_FLAG_OVR) || \ + (FLAG == I2C_FLAG_AF) || (FLAG == I2C_FLAG_ARLO) || \ + (FLAG == I2C_FLAG_BERR) || (FLAG == I2C_FLAG_STOPF) || \ + (FLAG == I2C_FLAG_ADD10) || (FLAG == I2C_FLAG_BTF) || \ + (FLAG == I2C_FLAG_ADDR) || (FLAG == I2C_FLAG_SB)) + +#define IS_I2C_GET_FLAG(FLAG) ((FLAG == I2C_FLAG_DUALF) || (FLAG == I2C_FLAG_SMBHOST) || \ + (FLAG == I2C_FLAG_SMBDEFAULT) || (FLAG == I2C_FLAG_GENCALL) || \ + (FLAG == I2C_FLAG_TRA) || (FLAG == I2C_FLAG_BUSY) || \ + (FLAG == I2C_FLAG_MSL) || (FLAG == I2C_FLAG_SMBALERT) || \ + (FLAG == I2C_FLAG_TIMEOUT) || (FLAG == I2C_FLAG_PECERR) || \ + (FLAG == I2C_FLAG_OVR) || (FLAG == I2C_FLAG_AF) || \ + (FLAG == I2C_FLAG_ARLO) || (FLAG == I2C_FLAG_BERR) || \ + (FLAG == I2C_FLAG_TXE) || (FLAG == I2C_FLAG_RXNE) || \ + (FLAG == I2C_FLAG_STOPF) || (FLAG == I2C_FLAG_ADD10) || \ + (FLAG == I2C_FLAG_BTF) || (FLAG == I2C_FLAG_ADDR) || \ + (FLAG == I2C_FLAG_SB)) + +/* I2C Events */ +/* EV1 */ +#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((u32)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ +#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((u32)0x00020002) /* BUSY and ADDR flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((u32)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ +#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((u32)0x00820000) /* DUALF and BUSY flags */ +#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((u32)0x00120000) /* GENCALL and BUSY flags */ + +/* EV2 */ +#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((u32)0x00020040) /* BUSY and RXNE flags */ + +/* EV3 */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((u32)0x00060084) /* TRA, BUSY, TXE and BTF flags */ + +/* EV4 */ +#define I2C_EVENT_SLAVE_STOP_DETECTED ((u32)0x00000010) /* STOPF flag */ + +/* EV5 */ +#define I2C_EVENT_MASTER_MODE_SELECT ((u32)0x00030001) /* BUSY, MSL and SB flag */ + +/* EV6 */ +#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((u32)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ +#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((u32)0x00030002) /* BUSY, MSL and ADDR flags */ + +/* EV7 */ +#define I2C_EVENT_MASTER_BYTE_RECEIVED ((u32)0x00030040) /* BUSY, MSL and RXNE flags */ + +/* EV8 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((u32)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ + +/* EV9 */ +#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((u32)0x00030008) /* BUSY, MSL and ADD10 flags */ + +/* EV3_1 */ +#define I2C_EVENT_SLAVE_ACK_FAILURE ((u32)0x00000400) /* AF flag */ + +#define IS_I2C_EVENT(EVENT) ((EVENT == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \ + (EVENT == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \ + (EVENT == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \ + (EVENT == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \ + (EVENT == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \ + (EVENT == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \ + (EVENT == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \ + (EVENT == I2C_EVENT_SLAVE_STOP_DETECTED) || \ + (EVENT == I2C_EVENT_MASTER_MODE_SELECT) || \ + (EVENT == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \ + (EVENT == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \ + (EVENT == I2C_EVENT_MASTER_BYTE_RECEIVED) || \ + (EVENT == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \ + (EVENT == I2C_EVENT_MASTER_MODE_ADDRESS10) || \ + (EVENT == I2C_EVENT_SLAVE_ACK_FAILURE)) + +/* I2C own address1 -----------------------------------------------------------*/ +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (ADDRESS1 <= 0x3FF) +/* I2C clock speed ------------------------------------------------------------*/ +#define IS_I2C_CLOCK_SPEED(SPEED) ((SPEED >= 0x1) && (SPEED <= 400000)) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void I2C_DeInit(I2C_TypeDef* I2Cx); +void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); +void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, u8 Address); +void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_ITConfig(I2C_TypeDef* I2Cx, u16 I2C_IT, FunctionalState NewState); +void I2C_SendData(I2C_TypeDef* I2Cx, u8 Data); +u8 I2C_ReceiveData(I2C_TypeDef* I2Cx); +void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, u8 Address, u8 I2C_Direction); +u16 I2C_ReadRegister(I2C_TypeDef* I2Cx, u8 I2C_Register); +void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, u16 I2C_SMBusAlert); +void I2C_TransmitPEC(I2C_TypeDef* I2Cx); +void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, u16 I2C_PECPosition); +void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState); +u8 I2C_GetPEC(I2C_TypeDef* I2Cx); +void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, u16 I2C_DutyCycle); +u32 I2C_GetLastEvent(I2C_TypeDef* I2Cx); +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, u32 I2C_EVENT); +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, u32 I2C_FLAG); +void I2C_ClearFlag(I2C_TypeDef* I2Cx, u32 I2C_FLAG); +ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, u32 I2C_IT); +void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, u32 I2C_IT); + +#endif /*__STM32F10x_I2C_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_it.h b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_it.h new file mode 100644 index 000000000..90ed398d4 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_it.h @@ -0,0 +1,86 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_it.h +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file contains the headers of the interrupt handlers. +******************************************************************************** +* History: +* mm/dd/yyyy: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_IT_H +#define __STM32F10x_IT_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_lib.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMIException(void); +void HardFaultException(void); +void MemManageException(void); +void BusFaultException(void); +void UsageFaultException(void); +void DebugMonitor(void); +void SVCHandler(void); +void PendSVC(void); +void SysTickHandler(void); +void WWDG_IRQHandler(void); +void PVD_IRQHandler(void); +void TAMPER_IRQHandler(void); +void RTC_IRQHandler(void); +void FLASH_IRQHandler(void); +void RCC_IRQHandler(void); +void EXTI0_IRQHandler(void); +void EXTI1_IRQHandler(void); +void EXTI2_IRQHandler(void); +void EXTI3_IRQHandler(void); +void EXTI4_IRQHandler(void); +void DMAChannel1_IRQHandler(void); +void DMAChannel2_IRQHandler(void); +void DMAChannel3_IRQHandler(void); +void DMAChannel4_IRQHandler(void); +void DMAChannel5_IRQHandler(void); +void DMAChannel6_IRQHandler(void); +void DMAChannel7_IRQHandler(void); +void ADC_IRQHandler(void); +void USB_HP_CAN_TX_IRQHandler(void); +void USB_LP_CAN_RX0_IRQHandler(void); +void CAN_RX1_IRQHandler(void); +void CAN_SCE_IRQHandler(void); +void EXTI9_5_IRQHandler(void); +void TIM1_BRK_IRQHandler(void); +void TIM1_UP_IRQHandler(void); +void TIM1_TRG_COM_IRQHandler(void); +void TIM1_CC_IRQHandler(void); +void TIM2_IRQHandler(void); +void TIM3_IRQHandler(void); +void TIM4_IRQHandler(void); +void I2C1_EV_IRQHandler(void); +void I2C1_ER_IRQHandler(void); +void I2C2_EV_IRQHandler(void); +void I2C2_ER_IRQHandler(void); +void SPI1_IRQHandler(void); +void SPI2_IRQHandler(void); +void USART1_IRQHandler(void); +void USART2_IRQHandler(void); +void USART3_IRQHandler(void); +void EXTI15_10_IRQHandler(void); +void RTCAlarm_IRQHandler(void); +void USBWakeUp_IRQHandler(void); + +#endif /* __STM32F10x_IT_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_iwdg.h b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_iwdg.h new file mode 100644 index 000000000..7cfc6ed4f --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_iwdg.h @@ -0,0 +1,73 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_iwdg.h +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file contains all the functions prototypes for the +* IWDG firmware library. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_IWDG_H +#define __STM32F10x_IWDG_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Write access to IWDG_PR and IWDG_RLR registers */ +#define IWDG_WriteAccess_Enable ((u16)0x5555) +#define IWDG_WriteAccess_Disable ((u16)0x0000) + +#define IS_IWDG_WRITE_ACCESS(ACCESS) ((ACCESS == IWDG_WriteAccess_Enable) || \ + (ACCESS == IWDG_WriteAccess_Disable)) + +/* IWDG prescaler */ +#define IWDG_Prescaler_4 ((u8)0x00) +#define IWDG_Prescaler_8 ((u8)0x01) +#define IWDG_Prescaler_16 ((u8)0x02) +#define IWDG_Prescaler_32 ((u8)0x03) +#define IWDG_Prescaler_64 ((u8)0x04) +#define IWDG_Prescaler_128 ((u8)0x05) +#define IWDG_Prescaler_256 ((u8)0x06) + +#define IS_IWDG_PRESCALER(PRESCALER) ((PRESCALER == IWDG_Prescaler_4) || \ + (PRESCALER == IWDG_Prescaler_8) || \ + (PRESCALER == IWDG_Prescaler_16) || \ + (PRESCALER == IWDG_Prescaler_32) || \ + (PRESCALER == IWDG_Prescaler_64) || \ + (PRESCALER == IWDG_Prescaler_128)|| \ + (PRESCALER == IWDG_Prescaler_256)) + +/* IWDG Flag */ +#define IWDG_FLAG_PVU ((u16)0x0001) +#define IWDG_FLAG_RVU ((u16)0x0002) + +#define IS_IWDG_FLAG(FLAG) ((FLAG == IWDG_FLAG_PVU) || (FLAG == IWDG_FLAG_RVU)) + +#define IS_IWDG_RELOAD(RELOAD) (RELOAD <= 0xFFF) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void IWDG_WriteAccessCmd(u16 IWDG_WriteAccess); +void IWDG_SetPrescaler(u8 IWDG_Prescaler); +void IWDG_SetReload(u16 Reload); +void IWDG_ReloadCounter(void); +void IWDG_Enable(void); +FlagStatus IWDG_GetFlagStatus(u16 IWDG_FLAG); + +#endif /* __STM32F10x_IWDG_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_lib.h b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_lib.h new file mode 100644 index 000000000..26d4e41e8 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_lib.h @@ -0,0 +1,112 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_lib.h +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file includes the peripherals header files in the +* user application. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_LIB_H +#define __STM32F10x_LIB_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +#ifdef _ADC + #include "stm32f10x_adc.h" +#endif /*_ADC */ + +#ifdef _BKP + #include "stm32f10x_bkp.h" +#endif /*_BKP */ + +#ifdef _CAN + #include "stm32f10x_can.h" +#endif /*_CAN */ + +#ifdef _DMA + #include "stm32f10x_dma.h" +#endif /*_DMA */ + +#ifdef _EXTI + #include "stm32f10x_exti.h" +#endif /*_EXTI */ + +#ifdef _FLASH + #include "stm32f10x_flash.h" +#endif /*_FLASH */ + +#ifdef _GPIO + #include "stm32f10x_gpio.h" +#endif /*_GPIO */ + +#ifdef _I2C + #include "stm32f10x_i2c.h" +#endif /*_I2C */ + +#ifdef _IWDG + #include "stm32f10x_iwdg.h" +#endif /*_IWDG */ + +#ifdef _NVIC + #include "stm32f10x_nvic.h" +#endif /*_NVIC */ + +#ifdef _PWR + #include "stm32f10x_pwr.h" +#endif /*_PWR */ + +#ifdef _RCC + #include "stm32f10x_rcc.h" +#endif /*_RCC */ + +#ifdef _RTC + #include "stm32f10x_rtc.h" +#endif /*_RTC */ + +#ifdef _SPI + #include "stm32f10x_spi.h" +#endif /*_SPI */ + +#ifdef _SysTick + #include "stm32f10x_systick.h" +#endif /*_SysTick */ + +#ifdef _TIM1 + #include "stm32f10x_tim1.h" +#endif /*_TIM1 */ + +#ifdef _TIM + #include "stm32f10x_tim.h" +#endif /*_TIM */ + +#ifdef _USART + #include "stm32f10x_usart.h" +#endif /*_USART */ + +#ifdef _WWDG + #include "stm32f10x_wwdg.h" +#endif /*_WWDG */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void debug(void); + +#endif /* __STM32F10x_LIB_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_map.h b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_map.h new file mode 100644 index 000000000..1c83a4fa4 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_map.h @@ -0,0 +1,865 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_map.h +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file contains all the peripheral register's definitions +* and memory mapping. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_MAP_H +#define __STM32F10x_MAP_H + +#ifndef EXT + #define EXT extern +#endif /* EXT */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_conf.h" +#include "stm32f10x_type.h" +#include "cortexm3_macro.h" + +/* Exported types ------------------------------------------------------------*/ +/******************************************************************************/ +/* IP registers structures */ +/******************************************************************************/ + +/*------------------------ Analog to Digital Converter -----------------------*/ +typedef struct +{ + vu32 SR; + vu32 CR1; + vu32 CR2; + vu32 SMPR1; + vu32 SMPR2; + vu32 JOFR1; + vu32 JOFR2; + vu32 JOFR3; + vu32 JOFR4; + vu32 HTR; + vu32 LTR; + vu32 SQR1; + vu32 SQR2; + vu32 SQR3; + vu32 JSQR; + vu32 JDR1; + vu32 JDR2; + vu32 JDR3; + vu32 JDR4; + vu32 DR; +} ADC_TypeDef; + +/*------------------------ Backup Registers ----------------------------------*/ +typedef struct +{ + u32 RESERVED0; + vu16 DR1; + u16 RESERVED1; + vu16 DR2; + u16 RESERVED2; + vu16 DR3; + u16 RESERVED3; + vu16 DR4; + u16 RESERVED4; + vu16 DR5; + u16 RESERVED5; + vu16 DR6; + u16 RESERVED6; + vu16 DR7; + u16 RESERVED7; + vu16 DR8; + u16 RESERVED8; + vu16 DR9; + u16 RESERVED9; + vu16 DR10; + u16 RESERVED10; + vu16 RTCCR; + u16 RESERVED11; + vu16 CR; + u16 RESERVED12; + vu16 CSR; + u16 RESERVED13; +} BKP_TypeDef; + +/*------------------------ Controller Area Network ---------------------------*/ +typedef struct +{ + vu32 TIR; + vu32 TDTR; + vu32 TDLR; + vu32 TDHR; +} CAN_TxMailBox_TypeDef; + +typedef struct +{ + vu32 RIR; + vu32 RDTR; + vu32 RDLR; + vu32 RDHR; +} CAN_FIFOMailBox_TypeDef; + +typedef struct +{ + vu32 FR0; + vu32 FR1; +} CAN_FilterRegister_TypeDef; + +typedef struct +{ + vu32 MCR; + vu32 MSR; + vu32 TSR; + vu32 RF0R; + vu32 RF1R; + vu32 IER; + vu32 ESR; + vu32 BTR; + u32 RESERVED0[88]; + CAN_TxMailBox_TypeDef sTxMailBox[3]; + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; + u32 RESERVED1[12]; + vu32 FMR; + vu32 FM0R; + u32 RESERVED2[1]; + vu32 FS0R; + u32 RESERVED3[1]; + vu32 FFA0R; + u32 RESERVED4[1]; + vu32 FA0R; + u32 RESERVED5[8]; + CAN_FilterRegister_TypeDef sFilterRegister[14]; +} CAN_TypeDef; + +/*------------------------ DMA Controller ------------------------------------*/ +typedef struct +{ + vu32 CCR; + vu32 CNDTR; + vu32 CPAR; + vu32 CMAR; +} DMA_Channel_TypeDef; + +typedef struct +{ + vu32 ISR; + vu32 IFCR; +} DMA_TypeDef; + +/*------------------------ External Interrupt/Event Controller ---------------*/ +typedef struct +{ + vu32 IMR; + vu32 EMR; + vu32 RTSR; + vu32 FTSR; + vu32 SWIER; + vu32 PR; +} EXTI_TypeDef; + +/*------------------------ FLASH and Option Bytes Registers ------------------*/ +typedef struct +{ + vu32 ACR; + vu32 KEYR; + vu32 OPTKEYR; + vu32 SR; + vu32 CR; + vu32 AR; + vu32 RESERVED; + vu32 OBR; + vu32 WRPR; +} FLASH_TypeDef; + +typedef struct +{ + vu16 RDP; + vu16 USER; + vu16 Data0; + vu16 Data1; + vu16 WRP0; + vu16 WRP1; + vu16 WRP2; + vu16 WRP3; +} OB_TypeDef; + +/*------------------------ General Purpose and Alternate Function IO ---------*/ +typedef struct +{ + vu32 CRL; + vu32 CRH; + vu32 IDR; + vu32 ODR; + vu32 BSRR; + vu32 BRR; + vu32 LCKR; +} GPIO_TypeDef; + +typedef struct +{ + vu32 EVCR; + vu32 MAPR; + vu32 EXTICR[4]; +} AFIO_TypeDef; + +/*------------------------ Inter-integrated Circuit Interface ----------------*/ +typedef struct +{ + vu16 CR1; + u16 RESERVED0; + vu16 CR2; + u16 RESERVED1; + vu16 OAR1; + u16 RESERVED2; + vu16 OAR2; + u16 RESERVED3; + vu16 DR; + u16 RESERVED4; + vu16 SR1; + u16 RESERVED5; + vu16 SR2; + u16 RESERVED6; + vu16 CCR; + u16 RESERVED7; + vu16 TRISE; + u16 RESERVED8; +} I2C_TypeDef; + +/*------------------------ Independent WATCHDOG ------------------------------*/ +typedef struct +{ + vu32 KR; + vu32 PR; + vu32 RLR; + vu32 SR; +} IWDG_TypeDef; + +/*------------------------ Nested Vectored Interrupt Controller --------------*/ +typedef struct +{ + vu32 Enable[2]; + u32 RESERVED0[30]; + vu32 Disable[2]; + u32 RSERVED1[30]; + vu32 Set[2]; + u32 RESERVED2[30]; + vu32 Clear[2]; + u32 RESERVED3[30]; + vu32 Active[2]; + u32 RESERVED4[62]; + vu32 Priority[11]; +} NVIC_TypeDef; + +typedef struct +{ + vu32 CPUID; + vu32 IRQControlState; + vu32 ExceptionTableOffset; + vu32 AIRC; + vu32 SysCtrl; + vu32 ConfigCtrl; + vu32 SystemPriority[3]; + vu32 SysHandlerCtrl; + vu32 ConfigFaultStatus; + vu32 HardFaultStatus; + vu32 DebugFaultStatus; + vu32 MemoryManageFaultAddr; + vu32 BusFaultAddr; +} SCB_TypeDef; + +/*------------------------ Power Controller ----------------------------------*/ +typedef struct +{ + vu32 CR; + vu32 CSR; +} PWR_TypeDef; + +/*------------------------ Reset and Clock Controller ------------------------*/ +typedef struct +{ + vu32 CR; + vu32 CFGR; + vu32 CIR; + vu32 APB2RSTR; + vu32 APB1RSTR; + vu32 AHBENR; + vu32 APB2ENR; + vu32 APB1ENR; + vu32 BDCR; + vu32 CSR; +} RCC_TypeDef; + +/*------------------------ Real-Time Clock -----------------------------------*/ +typedef struct +{ + vu16 CRH; + u16 RESERVED0; + vu16 CRL; + u16 RESERVED1; + vu16 PRLH; + u16 RESERVED2; + vu16 PRLL; + u16 RESERVED3; + vu16 DIVH; + u16 RESERVED4; + vu16 DIVL; + u16 RESERVED5; + vu16 CNTH; + u16 RESERVED6; + vu16 CNTL; + u16 RESERVED7; + vu16 ALRH; + u16 RESERVED8; + vu16 ALRL; + u16 RESERVED9; +} RTC_TypeDef; + +/*------------------------ Serial Peripheral Interface -----------------------*/ +typedef struct +{ + vu16 CR1; + u16 RESERVED0; + vu16 CR2; + u16 RESERVED1; + vu16 SR; + u16 RESERVED2; + vu16 DR; + u16 RESERVED3; + vu16 CRCPR; + u16 RESERVED4; + vu16 RXCRCR; + u16 RESERVED5; + vu16 TXCRCR; + u16 RESERVED6; +} SPI_TypeDef; + +/*------------------------ SystemTick ----------------------------------------*/ +typedef struct +{ + vu32 CTRL; + vu32 LOAD; + vu32 VAL; + vuc32 CALIB; +} SysTick_TypeDef; + +/*------------------------ Advanced Control Timer ----------------------------*/ +typedef struct +{ + vu16 CR1; + u16 RESERVED0; + vu16 CR2; + u16 RESERVED1; + vu16 SMCR; + u16 RESERVED2; + vu16 DIER; + u16 RESERVED3; + vu16 SR; + u16 RESERVED4; + vu16 EGR; + u16 RESERVED5; + vu16 CCMR1; + u16 RESERVED6; + vu16 CCMR2; + u16 RESERVED7; + vu16 CCER; + u16 RESERVED8; + vu16 CNT; + u16 RESERVED9; + vu16 PSC; + u16 RESERVED10; + vu16 ARR; + u16 RESERVED11; + vu16 RCR; + u16 RESERVED12; + vu16 CCR1; + u16 RESERVED13; + vu16 CCR2; + u16 RESERVED14; + vu16 CCR3; + u16 RESERVED15; + vu16 CCR4; + u16 RESERVED16; + vu16 BDTR; + u16 RESERVED17; + vu16 DCR; + u16 RESERVED18; + vu16 DMAR; + u16 RESERVED19; +} TIM1_TypeDef; + +/*------------------------ General Purpose Timer -----------------------------*/ +typedef struct +{ + vu16 CR1; + u16 RESERVED0; + vu16 CR2; + u16 RESERVED1; + vu16 SMCR; + u16 RESERVED2; + vu16 DIER; + u16 RESERVED3; + vu16 SR; + u16 RESERVED4; + vu16 EGR; + u16 RESERVED5; + vu16 CCMR1; + u16 RESERVED6; + vu16 CCMR2; + u16 RESERVED7; + vu16 CCER; + u16 RESERVED8; + vu16 CNT; + u16 RESERVED9; + vu16 PSC; + u16 RESERVED10; + vu16 ARR; + u16 RESERVED11[3]; + vu16 CCR1; + u16 RESERVED12; + vu16 CCR2; + u16 RESERVED13; + vu16 CCR3; + u16 RESERVED14; + vu16 CCR4; + u16 RESERVED15[3]; + vu16 DCR; + u16 RESERVED16; + vu16 DMAR; + u16 RESERVED17; +} TIM_TypeDef; + +/*----------------- Universal Synchronous Asynchronous Receiver Transmitter --*/ +typedef struct +{ + vu16 SR; + u16 RESERVED0; + vu16 DR; + u16 RESERVED1; + vu16 BRR; + u16 RESERVED2; + vu16 CR1; + u16 RESERVED3; + vu16 CR2; + u16 RESERVED4; + vu16 CR3; + u16 RESERVED5; + vu16 GTPR; + u16 RESERVED6; +} USART_TypeDef; + +/*------------------------ Window WATCHDOG -----------------------------------*/ +typedef struct +{ + vu32 CR; + vu32 CFR; + vu32 SR; +} WWDG_TypeDef; + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +/* Peripheral and SRAM base address in the alias region */ +#define PERIPH_BB_BASE ((u32)0x42000000) +#define SRAM_BB_BASE ((u32)0x22000000) + +/* Peripheral and SRAM base address in the bit-band region */ +#define SRAM_BASE ((u32)0x20000000) +#define PERIPH_BASE ((u32)0x40000000) + +/* Flash refisters base address */ +#define FLASH_BASE ((u32)0x40022000) +/* Flash Option Bytes base address */ +#define OB_BASE ((u32)0x1FFFF800) + +/* Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) + +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define CAN_BASE (APB1PERIPH_BASE + 0x6400) +#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) + +#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) +#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) +#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) +#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800) + +#define DMA_BASE (AHBPERIPH_BASE + 0x0000) +#define DMA_Channel1_BASE (AHBPERIPH_BASE + 0x0008) +#define DMA_Channel2_BASE (AHBPERIPH_BASE + 0x001C) +#define DMA_Channel3_BASE (AHBPERIPH_BASE + 0x0030) +#define DMA_Channel4_BASE (AHBPERIPH_BASE + 0x0044) +#define DMA_Channel5_BASE (AHBPERIPH_BASE + 0x0058) +#define DMA_Channel6_BASE (AHBPERIPH_BASE + 0x006C) +#define DMA_Channel7_BASE (AHBPERIPH_BASE + 0x0080) +#define RCC_BASE (AHBPERIPH_BASE + 0x1000) + +/* System Control Space memory map */ +#define SCS_BASE ((u32)0xE000E000) + +#define SysTick_BASE (SCS_BASE + 0x0010) +#define NVIC_BASE (SCS_BASE + 0x0100) +#define SCB_BASE (SCS_BASE + 0x0D00) + + +/******************************************************************************/ +/* IPs' declaration */ +/******************************************************************************/ + +/*------------------- Non Debug Mode -----------------------------------------*/ +#ifndef DEBUG +#ifdef _TIM2 + #define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#endif /*_TIM2 */ + +#ifdef _TIM3 + #define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#endif /*_TIM3 */ + +#ifdef _TIM4 + #define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#endif /*_TIM4 */ + +#ifdef _RTC + #define RTC ((RTC_TypeDef *) RTC_BASE) +#endif /*_RTC */ + +#ifdef _WWDG + #define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#endif /*_WWDG */ + +#ifdef _IWDG + #define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#endif /*_IWDG */ + +#ifdef _SPI2 + #define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#endif /*_SPI2 */ + +#ifdef _USART2 + #define USART2 ((USART_TypeDef *) USART2_BASE) +#endif /*_USART2 */ + +#ifdef _USART3 + #define USART3 ((USART_TypeDef *) USART3_BASE) +#endif /*_USART3 */ + +#ifdef _I2C1 + #define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#endif /*_I2C1 */ + +#ifdef _I2C2 + #define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#endif /*_I2C2 */ + +#ifdef _CAN + #define CAN ((CAN_TypeDef *) CAN_BASE) +#endif /*_CAN */ + +#ifdef _BKP + #define BKP ((BKP_TypeDef *) BKP_BASE) +#endif /*_BKP */ + +#ifdef _PWR + #define PWR ((PWR_TypeDef *) PWR_BASE) +#endif /*_PWR */ + +#ifdef _AFIO + #define AFIO ((AFIO_TypeDef *) AFIO_BASE) +#endif /*_AFIO */ + +#ifdef _EXTI + #define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#endif /*_EXTI */ + +#ifdef _GPIOA + #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#endif /*_GPIOA */ + +#ifdef _GPIOB + #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#endif /*_GPIOB */ + +#ifdef _GPIOC + #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#endif /*_GPIOC */ + +#ifdef _GPIOD + #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#endif /*_GPIOD */ + +#ifdef _GPIOE + #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#endif /*_GPIOE */ + +#ifdef _ADC1 + #define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#endif /*_ADC1 */ + +#ifdef _ADC2 + #define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#endif /*_ADC2 */ + +#ifdef _TIM1 + #define TIM1 ((TIM1_TypeDef *) TIM1_BASE) +#endif /*_TIM1 */ + +#ifdef _SPI1 + #define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#endif /*_SPI1 */ + +#ifdef _USART1 + #define USART1 ((USART_TypeDef *) USART1_BASE) +#endif /*_USART1 */ + +#ifdef _DMA + #define DMA ((DMA_TypeDef *) DMA_BASE) +#endif /*_DMA */ + +#ifdef _DMA_Channel1 + #define DMA_Channel1 ((DMA_Channel_TypeDef *) DMA_Channel1_BASE) +#endif /*_DMA_Channel1 */ + +#ifdef _DMA_Channel2 + #define DMA_Channel2 ((DMA_Channel_TypeDef *) DMA_Channel2_BASE) +#endif /*_DMA_Channel2 */ + +#ifdef _DMA_Channel3 + #define DMA_Channel3 ((DMA_Channel_TypeDef *) DMA_Channel3_BASE) +#endif /*_DMA_Channel3 */ + +#ifdef _DMA_Channel4 + #define DMA_Channel4 ((DMA_Channel_TypeDef *) DMA_Channel4_BASE) +#endif /*_DMA_Channel4 */ + +#ifdef _DMA_Channel5 + #define DMA_Channel5 ((DMA_Channel_TypeDef *) DMA_Channel5_BASE) +#endif /*_DMA_Channel5 */ + +#ifdef _DMA_Channel6 + #define DMA_Channel6 ((DMA_Channel_TypeDef *) DMA_Channel6_BASE) +#endif /*_DMA_Channel6 */ + +#ifdef _DMA_Channel7 + #define DMA_Channel7 ((DMA_Channel_TypeDef *) DMA_Channel7_BASE) +#endif /*_DMA_Channel7 */ + +#ifdef _FLASH + #define FLASH ((FLASH_TypeDef *) FLASH_BASE) + #define OB ((OB_TypeDef *) OB_BASE) +#endif /*_FLASH */ + +#ifdef _RCC + #define RCC ((RCC_TypeDef *) RCC_BASE) +#endif /*_RCC */ + +#ifdef _SysTick + #define SysTick ((SysTick_TypeDef *) SysTick_BASE) +#endif /*_SysTick */ + +#ifdef _NVIC + #define NVIC ((NVIC_TypeDef *) NVIC_BASE) +#endif /*_NVIC */ + +#ifdef _SCB + #define SCB ((SCB_TypeDef *) SCB_BASE) +#endif /*_SCB */ +/*---------------------- Debug Mode -----------------------------------------*/ +#else /* DEBUG */ +#ifdef _TIM2 + EXT TIM_TypeDef *TIM2; +#endif /*_TIM2 */ + +#ifdef _TIM3 + EXT TIM_TypeDef *TIM3; +#endif /*_TIM3 */ + +#ifdef _TIM4 + EXT TIM_TypeDef *TIM4; +#endif /*_TIM4 */ + +#ifdef _RTC + EXT RTC_TypeDef *RTC; +#endif /*_RTC */ + +#ifdef _WWDG + EXT WWDG_TypeDef *WWDG; +#endif /*_WWDG */ + +#ifdef _IWDG + EXT IWDG_TypeDef *IWDG; +#endif /*_IWDG */ + +#ifdef _SPI2 + EXT SPI_TypeDef *SPI2; +#endif /*_SPI2 */ + +#ifdef _USART2 + EXT USART_TypeDef *USART2; +#endif /*_USART2 */ + +#ifdef _USART3 + EXT USART_TypeDef *USART3; +#endif /*_USART3 */ + +#ifdef _I2C1 + EXT I2C_TypeDef *I2C1; +#endif /*_I2C1 */ + +#ifdef _I2C2 + EXT I2C_TypeDef *I2C2; +#endif /*_I2C2 */ + +#ifdef _CAN + EXT CAN_TypeDef *CAN; +#endif /*_CAN */ + +#ifdef _BKP + EXT BKP_TypeDef *BKP; +#endif /*_BKP */ + +#ifdef _PWR + EXT PWR_TypeDef *PWR; +#endif /*_PWR */ + +#ifdef _AFIO + EXT AFIO_TypeDef *AFIO; +#endif /*_AFIO */ + +#ifdef _EXTI + EXT EXTI_TypeDef *EXTI; +#endif /*_EXTI */ + +#ifdef _GPIOA + EXT GPIO_TypeDef *GPIOA; +#endif /*_GPIOA */ + +#ifdef _GPIOB + EXT GPIO_TypeDef *GPIOB; +#endif /*_GPIOB */ + +#ifdef _GPIOC + EXT GPIO_TypeDef *GPIOC; +#endif /*_GPIOC */ + +#ifdef _GPIOD + EXT GPIO_TypeDef *GPIOD; +#endif /*_GPIOD */ + +#ifdef _GPIOE + EXT GPIO_TypeDef *GPIOE; +#endif /*_GPIOE */ + +#ifdef _ADC1 + EXT ADC_TypeDef *ADC1; +#endif /*_ADC1 */ + +#ifdef _ADC2 + EXT ADC_TypeDef *ADC2; +#endif /*_ADC2 */ + +#ifdef _TIM1 + EXT TIM1_TypeDef *TIM1; +#endif /*_TIM1 */ + +#ifdef _SPI1 + EXT SPI_TypeDef *SPI1; +#endif /*_SPI1 */ + +#ifdef _USART1 + EXT USART_TypeDef *USART1; +#endif /*_USART1 */ + +#ifdef _DMA + EXT DMA_TypeDef *DMA; +#endif /*_DMA */ + +#ifdef _DMA_Channel1 + EXT DMA_Channel_TypeDef *DMA_Channel1; +#endif /*_DMA_Channel1 */ + +#ifdef _DMA_Channel2 + EXT DMA_Channel_TypeDef *DMA_Channel2; +#endif /*_DMA_Channel2 */ + +#ifdef _DMA_Channel3 + EXT DMA_Channel_TypeDef *DMA_Channel3; +#endif /*_DMA_Channel3 */ + +#ifdef _DMA_Channel4 + EXT DMA_Channel_TypeDef *DMA_Channel4; +#endif /*_DMA_Channel4 */ + +#ifdef _DMA_Channel5 + EXT DMA_Channel_TypeDef *DMA_Channel5; +#endif /*_DMA_Channel5 */ + +#ifdef _DMA_Channel6 + EXT DMA_Channel_TypeDef *DMA_Channel6; +#endif /*_DMA_Channel6 */ + +#ifdef _DMA_Channel7 + EXT DMA_Channel_TypeDef *DMA_Channel7; +#endif /*_DMA_Channel7 */ + +#ifdef _FLASH + EXT FLASH_TypeDef *FLASH; + EXT OB_TypeDef *OB; +#endif /*_FLASH */ + +#ifdef _RCC + EXT RCC_TypeDef *RCC; +#endif /*_RCC */ + +#ifdef _SysTick + EXT SysTick_TypeDef *SysTick; +#endif /*_SysTick */ + +#ifdef _NVIC + EXT NVIC_TypeDef *NVIC; +#endif /*_NVIC */ + +#ifdef _SCB + EXT SCB_TypeDef *SCB; +#endif /*_SCB */ + +#endif /* DEBUG */ + +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +#endif /* __STM32F10x_MAP_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_nvic.h b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_nvic.h new file mode 100644 index 000000000..5cfacf893 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_nvic.h @@ -0,0 +1,255 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_nvic.h +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file contains all the functions prototypes for the +* NVIC firmware library. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_NVIC_H +#define __STM32F10x_NVIC_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* NVIC Init Structure definition */ +typedef struct +{ + u8 NVIC_IRQChannel; + u8 NVIC_IRQChannelPreemptionPriority; + u8 NVIC_IRQChannelSubPriority; + FunctionalState NVIC_IRQChannelCmd; +} NVIC_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* IRQ Channels --------------------------------------------------------------*/ +#define WWDG_IRQChannel ((u8)0x00) /* Window WatchDog Interrupt */ +#define PVD_IRQChannel ((u8)0x01) /* PVD through EXTI Line detection Interrupt */ +#define TAMPER_IRQChannel ((u8)0x02) /* Tamper Interrupt */ +#define RTC_IRQChannel ((u8)0x03) /* RTC global Interrupt */ +#define FLASH_IRQChannel ((u8)0x04) /* FLASH global Interrupt */ +#define RCC_IRQChannel ((u8)0x05) /* RCC global Interrupt */ +#define EXTI0_IRQChannel ((u8)0x06) /* EXTI Line0 Interrupt */ +#define EXTI1_IRQChannel ((u8)0x07) /* EXTI Line1 Interrupt */ +#define EXTI2_IRQChannel ((u8)0x08) /* EXTI Line2 Interrupt */ +#define EXTI3_IRQChannel ((u8)0x09) /* EXTI Line3 Interrupt */ +#define EXTI4_IRQChannel ((u8)0x0A) /* EXTI Line4 Interrupt */ +#define DMAChannel1_IRQChannel ((u8)0x0B) /* DMA Channel 1 global Interrupt */ +#define DMAChannel2_IRQChannel ((u8)0x0C) /* DMA Channel 2 global Interrupt */ +#define DMAChannel3_IRQChannel ((u8)0x0D) /* DMA Channel 3 global Interrupt */ +#define DMAChannel4_IRQChannel ((u8)0x0E) /* DMA Channel 4 global Interrupt */ +#define DMAChannel5_IRQChannel ((u8)0x0F) /* DMA Channel 5 global Interrupt */ +#define DMAChannel6_IRQChannel ((u8)0x10) /* DMA Channel 6 global Interrupt */ +#define DMAChannel7_IRQChannel ((u8)0x11) /* DMA Channel 7 global Interrupt */ +#define ADC_IRQChannel ((u8)0x12) /* ADC global Interrupt */ +#define USB_HP_CAN_TX_IRQChannel ((u8)0x13) /* USB High Priority or CAN TX Interrupts */ +#define USB_LP_CAN_RX0_IRQChannel ((u8)0x14) /* USB Low Priority or CAN RX0 Interrupts */ +#define CAN_RX1_IRQChannel ((u8)0x15) /* CAN RX1 Interrupt */ +#define CAN_SCE_IRQChannel ((u8)0x16) /* CAN SCE Interrupt */ +#define EXTI9_5_IRQChannel ((u8)0x17) /* External Line[9:5] Interrupts */ +#define TIM1_BRK_IRQChannel ((u8)0x18) /* TIM1 Break Interrupt */ +#define TIM1_UP_IRQChannel ((u8)0x19) /* TIM1 Update Interrupt */ +#define TIM1_TRG_COM_IRQChannel ((u8)0x1A) /* TIM1 Trigger and Commutation Interrupt */ +#define TIM1_CC_IRQChannel ((u8)0x1B) /* TIM1 Capture Compare Interrupt */ +#define TIM2_IRQChannel ((u8)0x1C) /* TIM2 global Interrupt */ +#define TIM3_IRQChannel ((u8)0x1D) /* TIM3 global Interrupt */ +#define TIM4_IRQChannel ((u8)0x1E) /* TIM4 global Interrupt */ +#define I2C1_EV_IRQChannel ((u8)0x1F) /* I2C1 Event Interrupt */ +#define I2C1_ER_IRQChannel ((u8)0x20) /* I2C1 Error Interrupt */ +#define I2C2_EV_IRQChannel ((u8)0x21) /* I2C2 Event Interrupt */ +#define I2C2_ER_IRQChannel ((u8)0x22) /* I2C2 Error Interrupt */ +#define SPI1_IRQChannel ((u8)0x23) /* SPI1 global Interrupt */ +#define SPI2_IRQChannel ((u8)0x24) /* SPI2 global Interrupt */ +#define USART1_IRQChannel ((u8)0x25) /* USART1 global Interrupt */ +#define USART2_IRQChannel ((u8)0x26) /* USART2 global Interrupt */ +#define USART3_IRQChannel ((u8)0x27) /* USART3 global Interrupt */ +#define EXTI15_10_IRQChannel ((u8)0x28) /* External Line[15:10] Interrupts */ +#define RTCAlarm_IRQChannel ((u8)0x29) /* RTC Alarm through EXTI Line Interrupt */ +#define USBWakeUp_IRQChannel ((u8)0x2A) /* USB WakeUp from suspend through EXTI Line Interrupt */ + +#define IS_NVIC_IRQ_CHANNEL(CHANNEL) ((CHANNEL == WWDG_IRQChannel) || \ + (CHANNEL == PVD_IRQChannel) || \ + (CHANNEL == TAMPER_IRQChannel) || \ + (CHANNEL == RTC_IRQChannel) || \ + (CHANNEL == FLASH_IRQChannel) || \ + (CHANNEL == RCC_IRQChannel) || \ + (CHANNEL == EXTI0_IRQChannel) || \ + (CHANNEL == EXTI1_IRQChannel) || \ + (CHANNEL == EXTI2_IRQChannel) || \ + (CHANNEL == EXTI3_IRQChannel) || \ + (CHANNEL == EXTI4_IRQChannel) || \ + (CHANNEL == DMAChannel1_IRQChannel) || \ + (CHANNEL == DMAChannel2_IRQChannel) || \ + (CHANNEL == DMAChannel3_IRQChannel) || \ + (CHANNEL == DMAChannel4_IRQChannel) || \ + (CHANNEL == DMAChannel5_IRQChannel) || \ + (CHANNEL == DMAChannel6_IRQChannel) || \ + (CHANNEL == DMAChannel7_IRQChannel) || \ + (CHANNEL == ADC_IRQChannel) || \ + (CHANNEL == USB_HP_CAN_TX_IRQChannel) || \ + (CHANNEL == USB_LP_CAN_RX0_IRQChannel) || \ + (CHANNEL == CAN_RX1_IRQChannel) || \ + (CHANNEL == CAN_SCE_IRQChannel) || \ + (CHANNEL == EXTI9_5_IRQChannel) || \ + (CHANNEL == TIM1_BRK_IRQChannel) || \ + (CHANNEL == TIM1_UP_IRQChannel) || \ + (CHANNEL == TIM1_TRG_COM_IRQChannel) || \ + (CHANNEL == TIM1_CC_IRQChannel) || \ + (CHANNEL == TIM2_IRQChannel) || \ + (CHANNEL == TIM3_IRQChannel) || \ + (CHANNEL == TIM4_IRQChannel) || \ + (CHANNEL == I2C1_EV_IRQChannel) || \ + (CHANNEL == I2C1_ER_IRQChannel) || \ + (CHANNEL == I2C2_EV_IRQChannel) || \ + (CHANNEL == I2C2_ER_IRQChannel) || \ + (CHANNEL == SPI1_IRQChannel) || \ + (CHANNEL == SPI2_IRQChannel) || \ + (CHANNEL == USART1_IRQChannel) || \ + (CHANNEL == USART2_IRQChannel) || \ + (CHANNEL == USART3_IRQChannel) || \ + (CHANNEL == EXTI15_10_IRQChannel) || \ + (CHANNEL == RTCAlarm_IRQChannel) || \ + (CHANNEL == USBWakeUp_IRQChannel)) + +/* System Handlers -----------------------------------------------------------*/ +#define SystemHandler_NMI ((u32)0x00001F) /* NMI Handler */ +#define SystemHandler_HardFault ((u32)0x000000) /* Hard Fault Handler */ +#define SystemHandler_MemoryManage ((u32)0x043430) /* Memory Manage Handler */ +#define SystemHandler_BusFault ((u32)0x547931) /* Bus Fault Handler */ +#define SystemHandler_UsageFault ((u32)0x24C232) /* Usage Fault Handler */ +#define SystemHandler_SVCall ((u32)0x01FF40) /* SVCall Handler */ +#define SystemHandler_DebugMonitor ((u32)0x0A0080) /* Debug Monitor Handler */ +#define SystemHandler_PSV ((u32)0x02829C) /* PSV Handler */ +#define SystemHandler_SysTick ((u32)0x02C39A) /* SysTick Handler */ + +#define IS_CONFIG_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \ + (HANDLER == SystemHandler_BusFault) || \ + (HANDLER == SystemHandler_UsageFault)) + +#define IS_PRIORITY_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \ + (HANDLER == SystemHandler_BusFault) || \ + (HANDLER == SystemHandler_UsageFault) || \ + (HANDLER == SystemHandler_SVCall) || \ + (HANDLER == SystemHandler_DebugMonitor) || \ + (HANDLER == SystemHandler_PSV) || \ + (HANDLER == SystemHandler_SysTick)) + +#define IS_GET_PENDING_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \ + (HANDLER == SystemHandler_BusFault) || \ + (HANDLER == SystemHandler_SVCall)) + +#define IS_SET_PENDING_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_NMI) || \ + (HANDLER == SystemHandler_PSV) || \ + (HANDLER == SystemHandler_SysTick)) + +#define IS_CLEAR_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_PSV) || \ + (HANDLER == SystemHandler_SysTick)) + +#define IS_GET_ACTIVE_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \ + (HANDLER == SystemHandler_BusFault) || \ + (HANDLER == SystemHandler_UsageFault) || \ + (HANDLER == SystemHandler_SVCall) || \ + (HANDLER == SystemHandler_DebugMonitor) || \ + (HANDLER == SystemHandler_PSV) || \ + (HANDLER == SystemHandler_SysTick)) + +#define IS_FAULT_SOURCE_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_HardFault) || \ + (HANDLER == SystemHandler_MemoryManage) || \ + (HANDLER == SystemHandler_BusFault) || \ + (HANDLER == SystemHandler_UsageFault) || \ + (HANDLER == SystemHandler_DebugMonitor)) + +#define IS_FAULT_ADDRESS_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \ + (HANDLER == SystemHandler_BusFault)) + + +/* Vector Table Base ---------------------------------------------------------*/ +#define NVIC_VectTab_RAM ((u32)0x20000000) +#define NVIC_VectTab_FLASH ((u32)0x00000000) + +#define IS_NVIC_VECTTAB(VECTTAB) ((VECTTAB == NVIC_VectTab_RAM) || \ + (VECTTAB == NVIC_VectTab_FLASH)) + +/* System Low Power ----------------------------------------------------------*/ +#define NVIC_LP_SEVONPEND ((u8)0x10) +#define NVIC_LP_SLEEPDEEP ((u8)0x04) +#define NVIC_LP_SLEEPONEXIT ((u8)0x02) + +#define IS_NVIC_LP(LP) ((LP == NVIC_LP_SEVONPEND) || \ + (LP == NVIC_LP_SLEEPDEEP) || \ + (LP == NVIC_LP_SLEEPONEXIT)) + +/* Preemption Priority Group -------------------------------------------------*/ +#define NVIC_PriorityGroup_0 ((u32)0x700) /* 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PriorityGroup_1 ((u32)0x600) /* 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PriorityGroup_2 ((u32)0x500) /* 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PriorityGroup_3 ((u32)0x400) /* 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PriorityGroup_4 ((u32)0x300) /* 4 bits for pre-emption priority + 0 bits for subpriority */ + +#define IS_NVIC_PRIORITY_GROUP(GROUP) ((GROUP == NVIC_PriorityGroup_0) || \ + (GROUP == NVIC_PriorityGroup_1) || \ + (GROUP == NVIC_PriorityGroup_2) || \ + (GROUP == NVIC_PriorityGroup_3) || \ + (GROUP == NVIC_PriorityGroup_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) (PRIORITY < 0x10) +#define IS_NVIC_SUB_PRIORITY(PRIORITY) (PRIORITY < 0x10) +#define IS_NVIC_OFFSET(OFFSET) (OFFSET < 0x3FFFFF) +#define IS_NVIC_BASE_PRI(PRI) ((PRI > 0x00) && (PRI < 0x10)) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NVIC_DeInit(void); +void NVIC_SCBDeInit(void); +void NVIC_PriorityGroupConfig(u32 NVIC_PriorityGroup); +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); +void NVIC_StructInit(NVIC_InitTypeDef* NVIC_InitStruct); +void NVIC_SETPRIMASK(void); +void NVIC_RESETPRIMASK(void); +void NVIC_SETFAULTMASK(void); +void NVIC_RESETFAULTMASK(void); +void NVIC_BASEPRICONFIG(u32 NewPriority); +u32 NVIC_GetBASEPRI(void); +u16 NVIC_GetCurrentPendingIRQChannel(void); +ITStatus NVIC_GetIRQChannelPendingBitStatus(u8 NVIC_IRQChannel); +void NVIC_SetIRQChannelPendingBit(u8 NVIC_IRQChannel); +void NVIC_ClearIRQChannelPendingBit(u8 NVIC_IRQChannel); +u16 NVIC_GetCurrentActiveHandler(void); +ITStatus NVIC_GetIRQChannelActiveBitStatus(u8 NVIC_IRQChannel); +u32 NVIC_GetCPUID(void); +void NVIC_SetVectorTable(u32 NVIC_VectTab, u32 Offset); +void NVIC_GenerateSystemReset(void); +void NVIC_GenerateCoreReset(void); +void NVIC_SystemLPConfig(u8 LowPowerMode, FunctionalState NewState); +void NVIC_SystemHandlerConfig(u32 SystemHandler, FunctionalState NewState); +void NVIC_SystemHandlerPriorityConfig(u32 SystemHandler, u8 SystemHandlerPreemptionPriority, + u8 SystemHandlerSubPriority); +ITStatus NVIC_GetSystemHandlerPendingBitStatus(u32 SystemHandler); +void NVIC_SetSystemHandlerPendingBit(u32 SystemHandler); +void NVIC_ClearSystemHandlerPendingBit(u32 SystemHandler); +ITStatus NVIC_GetSystemHandlerActiveBitStatus(u32 SystemHandler); +u32 NVIC_GetFaultHandlerSources(u32 SystemHandler); +u32 NVIC_GetFaultAddress(u32 SystemHandler); + +#endif /* __STM32F10x_NVIC_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_pwr.h b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_pwr.h new file mode 100644 index 000000000..4bbc29164 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_pwr.h @@ -0,0 +1,81 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_pwr.h +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file contains all the functions prototypes for the +* PWR firmware library. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_PWR_H +#define __STM32F10x_PWR_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* PVD detection level */ +#define PWR_PVDLevel_2V2 ((u32)0x00000000) +#define PWR_PVDLevel_2V3 ((u32)0x00000020) +#define PWR_PVDLevel_2V4 ((u32)0x00000040) +#define PWR_PVDLevel_2V5 ((u32)0x00000060) +#define PWR_PVDLevel_2V6 ((u32)0x00000080) +#define PWR_PVDLevel_2V7 ((u32)0x000000A0) +#define PWR_PVDLevel_2V8 ((u32)0x000000C0) +#define PWR_PVDLevel_2V9 ((u32)0x000000E0) + +#define IS_PWR_PVD_LEVEL(LEVEL) ((LEVEL == PWR_PVDLevel_2V2) || (LEVEL == PWR_PVDLevel_2V3)|| \ + (LEVEL == PWR_PVDLevel_2V4) || (LEVEL == PWR_PVDLevel_2V5)|| \ + (LEVEL == PWR_PVDLevel_2V6) || (LEVEL == PWR_PVDLevel_2V7)|| \ + (LEVEL == PWR_PVDLevel_2V8) || (LEVEL == PWR_PVDLevel_2V9)) + +/* Regulator state is STOP mode */ +#define PWR_Regulator_ON ((u32)0x00000000) +#define PWR_Regulator_LowPower ((u32)0x00000001) + +#define IS_PWR_REGULATOR(REGULATOR) ((REGULATOR == PWR_Regulator_ON) || \ + (REGULATOR == PWR_Regulator_LowPower)) + +/* STOP mode entry */ +#define PWR_STOPEntry_WFI ((u8)0x01) +#define PWR_STOPEntry_WFE ((u8)0x02) + +#define IS_PWR_STOP_ENTRY(ENTRY) ((ENTRY == PWR_STOPEntry_WFI) || (ENTRY == PWR_STOPEntry_WFE)) + +/* PWR Flag */ +#define PWR_FLAG_WU ((u32)0x00000001) +#define PWR_FLAG_SB ((u32)0x00000002) +#define PWR_FLAG_PVDO ((u32)0x00000004) + +#define IS_PWR_GET_FLAG(FLAG) ((FLAG == PWR_FLAG_WU) || (FLAG == PWR_FLAG_SB) || \ + (FLAG == PWR_FLAG_PVDO)) +#define IS_PWR_CLEAR_FLAG(FLAG) ((FLAG == PWR_FLAG_WU) || (FLAG == PWR_FLAG_SB)) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void PWR_DeInit(void); +void PWR_BackupAccessCmd(FunctionalState NewState); +void PWR_PVDCmd(FunctionalState NewState); +void PWR_PVDLevelConfig(u32 PWR_PVDLevel); +void PWR_WakeUpPinCmd(FunctionalState NewState); +void PWR_EnterSTOPMode(u32 PWR_Regulator, u8 PWR_STOPEntry); +void PWR_EnterSTANDBYMode(void); +FlagStatus PWR_GetFlagStatus(u32 PWR_FLAG); +void PWR_ClearFlag(u32 PWR_FLAG); + +#endif /* __STM32F10x_PWR_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_rcc.h b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_rcc.h new file mode 100644 index 000000000..b7d0aa317 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_rcc.h @@ -0,0 +1,276 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_rcc.h +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file contains all the functions prototypes for the +* RCC firmware library. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_RCC_H +#define __STM32F10x_RCC_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +typedef struct +{ + u32 SYSCLK_Frequency; + u32 HCLK_Frequency; + u32 PCLK1_Frequency; + u32 PCLK2_Frequency; + u32 ADCCLK_Frequency; +}RCC_ClocksTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* HSE configuration */ +#define RCC_HSE_OFF ((u32)0x00000000) +#define RCC_HSE_ON ((u32)0x00010000) +#define RCC_HSE_Bypass ((u32)0x00040000) + +#define IS_RCC_HSE(HSE) ((HSE == RCC_HSE_OFF) || (HSE == RCC_HSE_ON) || \ + (HSE == RCC_HSE_Bypass)) + +/* PLL entry clock source */ +#define RCC_PLLSource_HSI_Div2 ((u32)0x00000000) +#define RCC_PLLSource_HSE_Div1 ((u32)0x00010000) +#define RCC_PLLSource_HSE_Div2 ((u32)0x00030000) + +#define IS_RCC_PLL_SOURCE(SOURCE) ((SOURCE == RCC_PLLSource_HSI_Div2) || \ + (SOURCE == RCC_PLLSource_HSE_Div1) || \ + (SOURCE == RCC_PLLSource_HSE_Div2)) + +/* PLL multiplication factor */ +#define RCC_PLLMul_2 ((u32)0x00000000) +#define RCC_PLLMul_3 ((u32)0x00040000) +#define RCC_PLLMul_4 ((u32)0x00080000) +#define RCC_PLLMul_5 ((u32)0x000C0000) +#define RCC_PLLMul_6 ((u32)0x00100000) +#define RCC_PLLMul_7 ((u32)0x00140000) +#define RCC_PLLMul_8 ((u32)0x00180000) +#define RCC_PLLMul_9 ((u32)0x001C0000) +#define RCC_PLLMul_10 ((u32)0x00200000) +#define RCC_PLLMul_11 ((u32)0x00240000) +#define RCC_PLLMul_12 ((u32)0x00280000) +#define RCC_PLLMul_13 ((u32)0x002C0000) +#define RCC_PLLMul_14 ((u32)0x00300000) +#define RCC_PLLMul_15 ((u32)0x00340000) +#define RCC_PLLMul_16 ((u32)0x00380000) + +#define IS_RCC_PLL_MUL(MUL) ((MUL == RCC_PLLMul_2) || (MUL == RCC_PLLMul_3) ||\ + (MUL == RCC_PLLMul_4) || (MUL == RCC_PLLMul_5) ||\ + (MUL == RCC_PLLMul_6) || (MUL == RCC_PLLMul_7) ||\ + (MUL == RCC_PLLMul_8) || (MUL == RCC_PLLMul_9) ||\ + (MUL == RCC_PLLMul_10) || (MUL == RCC_PLLMul_11) ||\ + (MUL == RCC_PLLMul_12) || (MUL == RCC_PLLMul_13) ||\ + (MUL == RCC_PLLMul_14) || (MUL == RCC_PLLMul_15) ||\ + (MUL == RCC_PLLMul_16)) + +/* System clock source */ +#define RCC_SYSCLKSource_HSI ((u32)0x00000000) +#define RCC_SYSCLKSource_HSE ((u32)0x00000001) +#define RCC_SYSCLKSource_PLLCLK ((u32)0x00000002) + +#define IS_RCC_SYSCLK_SOURCE(SOURCE) ((SOURCE == RCC_SYSCLKSource_HSI) || \ + (SOURCE == RCC_SYSCLKSource_HSE) || \ + (SOURCE == RCC_SYSCLKSource_PLLCLK)) + +/* AHB clock source */ +#define RCC_SYSCLK_Div1 ((u32)0x00000000) +#define RCC_SYSCLK_Div2 ((u32)0x00000080) +#define RCC_SYSCLK_Div4 ((u32)0x00000090) +#define RCC_SYSCLK_Div8 ((u32)0x000000A0) +#define RCC_SYSCLK_Div16 ((u32)0x000000B0) +#define RCC_SYSCLK_Div64 ((u32)0x000000C0) +#define RCC_SYSCLK_Div128 ((u32)0x000000D0) +#define RCC_SYSCLK_Div256 ((u32)0x000000E0) +#define RCC_SYSCLK_Div512 ((u32)0x000000F0) + +#define IS_RCC_HCLK(HCLK) ((HCLK == RCC_SYSCLK_Div1) || (HCLK == RCC_SYSCLK_Div2) || \ + (HCLK == RCC_SYSCLK_Div4) || (HCLK == RCC_SYSCLK_Div8) || \ + (HCLK == RCC_SYSCLK_Div16) || (HCLK == RCC_SYSCLK_Div64) || \ + (HCLK == RCC_SYSCLK_Div128) || (HCLK == RCC_SYSCLK_Div256) || \ + (HCLK == RCC_SYSCLK_Div512)) + +/* APB1/APB2 clock source */ +#define RCC_HCLK_Div1 ((u32)0x00000000) +#define RCC_HCLK_Div2 ((u32)0x00000400) +#define RCC_HCLK_Div4 ((u32)0x00000500) +#define RCC_HCLK_Div8 ((u32)0x00000600) +#define RCC_HCLK_Div16 ((u32)0x00000700) + +#define IS_RCC_PCLK(PCLK) ((PCLK == RCC_HCLK_Div1) || (PCLK == RCC_HCLK_Div2) || \ + (PCLK == RCC_HCLK_Div4) || (PCLK == RCC_HCLK_Div8) || \ + (PCLK == RCC_HCLK_Div16)) + +/* RCC Interrupt source */ +#define RCC_IT_LSIRDY ((u8)0x01) +#define RCC_IT_LSERDY ((u8)0x02) +#define RCC_IT_HSIRDY ((u8)0x04) +#define RCC_IT_HSERDY ((u8)0x08) +#define RCC_IT_PLLRDY ((u8)0x10) +#define RCC_IT_CSS ((u8)0x80) + +#define IS_RCC_IT(IT) (((IT & (u8)0xE0) == 0x00) && (IT != 0x00)) +#define IS_RCC_GET_IT(IT) ((IT == RCC_IT_LSIRDY) || (IT == RCC_IT_LSERDY) || \ + (IT == RCC_IT_HSIRDY) || (IT == RCC_IT_HSERDY) || \ + (IT == RCC_IT_PLLRDY) || (IT == RCC_IT_CSS)) +#define IS_RCC_CLEAR_IT(IT) (((IT & (u8)0x60) == 0x00) && (IT != 0x00)) + +/* USB clock source */ +#define RCC_USBCLKSource_PLLCLK_1Div5 ((u8)0x00) +#define RCC_USBCLKSource_PLLCLK_Div1 ((u8)0x01) + +#define IS_RCC_USBCLK_SOURCE(SOURCE) ((SOURCE == RCC_USBCLKSource_PLLCLK_1Div5) || \ + (SOURCE == RCC_USBCLKSource_PLLCLK_Div1)) + +/* ADC clock source */ +#define RCC_PCLK2_Div2 ((u32)0x00000000) +#define RCC_PCLK2_Div4 ((u32)0x00004000) +#define RCC_PCLK2_Div6 ((u32)0x00008000) +#define RCC_PCLK2_Div8 ((u32)0x0000C000) + +#define IS_RCC_ADCCLK(ADCCLK) ((ADCCLK == RCC_PCLK2_Div2) || (ADCCLK == RCC_PCLK2_Div4) || \ + (ADCCLK == RCC_PCLK2_Div6) || (ADCCLK == RCC_PCLK2_Div8)) + +/* LSE configuration */ +#define RCC_LSE_OFF ((u8)0x00) +#define RCC_LSE_ON ((u8)0x01) +#define RCC_LSE_Bypass ((u8)0x04) + +#define IS_RCC_LSE(LSE) ((LSE == RCC_LSE_OFF) || (LSE == RCC_LSE_ON) || \ + (LSE == RCC_LSE_Bypass)) + +/* RTC clock source */ +#define RCC_RTCCLKSource_LSE ((u32)0x00000100) +#define RCC_RTCCLKSource_LSI ((u32)0x00000200) +#define RCC_RTCCLKSource_HSE_Div128 ((u32)0x00000300) + +#define IS_RCC_RTCCLK_SOURCE(SOURCE) ((SOURCE == RCC_RTCCLKSource_LSE) || \ + (SOURCE == RCC_RTCCLKSource_LSI) || \ + (SOURCE == RCC_RTCCLKSource_HSE_Div128)) + +/* AHB peripheral */ +#define RCC_AHBPeriph_DMA ((u32)0x00000001) +#define RCC_AHBPeriph_SRAM ((u32)0x00000004) +#define RCC_AHBPeriph_FLITF ((u32)0x00000010) + +#define IS_RCC_AHB_PERIPH(PERIPH) (((PERIPH & 0xFFFFFFEA) == 0x00) && (PERIPH != 0x00)) + +/* APB2 peripheral */ +#define RCC_APB2Periph_AFIO ((u32)0x00000001) +#define RCC_APB2Periph_GPIOA ((u32)0x00000004) +#define RCC_APB2Periph_GPIOB ((u32)0x00000008) +#define RCC_APB2Periph_GPIOC ((u32)0x00000010) +#define RCC_APB2Periph_GPIOD ((u32)0x00000020) +#define RCC_APB2Periph_GPIOE ((u32)0x00000040) +#define RCC_APB2Periph_ADC1 ((u32)0x00000200) +#define RCC_APB2Periph_ADC2 ((u32)0x00000400) +#define RCC_APB2Periph_TIM1 ((u32)0x00000800) +#define RCC_APB2Periph_SPI1 ((u32)0x00001000) +#define RCC_APB2Periph_USART1 ((u32)0x00004000) +#define RCC_APB2Periph_ALL ((u32)0x00005E7D) + +#define IS_RCC_APB2_PERIPH(PERIPH) (((PERIPH & 0xFFFFA182) == 0x00) && (PERIPH != 0x00)) + +/* APB1 peripheral */ +#define RCC_APB1Periph_TIM2 ((u32)0x00000001) +#define RCC_APB1Periph_TIM3 ((u32)0x00000002) +#define RCC_APB1Periph_TIM4 ((u32)0x00000004) +#define RCC_APB1Periph_WWDG ((u32)0x00000800) +#define RCC_APB1Periph_SPI2 ((u32)0x00004000) +#define RCC_APB1Periph_USART2 ((u32)0x00020000) +#define RCC_APB1Periph_USART3 ((u32)0x00040000) +#define RCC_APB1Periph_I2C1 ((u32)0x00200000) +#define RCC_APB1Periph_I2C2 ((u32)0x00400000) +#define RCC_APB1Periph_USB ((u32)0x00800000) +#define RCC_APB1Periph_CAN ((u32)0x02000000) +#define RCC_APB1Periph_BKP ((u32)0x08000000) +#define RCC_APB1Periph_PWR ((u32)0x10000000) +#define RCC_APB1Periph_ALL ((u32)0x1AE64807) + +#define IS_RCC_APB1_PERIPH(PERIPH) (((PERIPH & 0xE519B7F8) == 0x00) && (PERIPH != 0x00)) + +/* Clock source to output on MCO pin */ +#define RCC_MCO_NoClock ((u8)0x00) +#define RCC_MCO_SYSCLK ((u8)0x04) +#define RCC_MCO_HSI ((u8)0x05) +#define RCC_MCO_HSE ((u8)0x06) +#define RCC_MCO_PLLCLK_Div2 ((u8)0x07) + +#define IS_RCC_MCO(MCO) ((MCO == RCC_MCO_NoClock) || (MCO == RCC_MCO_HSI) || \ + (MCO == RCC_MCO_SYSCLK) || (MCO == RCC_MCO_HSE) || \ + (MCO == RCC_MCO_PLLCLK_Div2)) + +/* RCC Flag */ +#define RCC_FLAG_HSIRDY ((u8)0x20) +#define RCC_FLAG_HSERDY ((u8)0x31) +#define RCC_FLAG_PLLRDY ((u8)0x39) +#define RCC_FLAG_LSERDY ((u8)0x41) +#define RCC_FLAG_LSIRDY ((u8)0x61) +#define RCC_FLAG_PINRST ((u8)0x7A) +#define RCC_FLAG_PORRST ((u8)0x7B) +#define RCC_FLAG_SFTRST ((u8)0x7C) +#define RCC_FLAG_IWDGRST ((u8)0x7D) +#define RCC_FLAG_WWDGRST ((u8)0x7E) +#define RCC_FLAG_LPWRRST ((u8)0x7F) + +#define IS_RCC_FLAG(FLAG) ((FLAG == RCC_FLAG_HSIRDY) || (FLAG == RCC_FLAG_HSERDY) || \ + (FLAG == RCC_FLAG_PLLRDY) || (FLAG == RCC_FLAG_LSERDY) || \ + (FLAG == RCC_FLAG_LSIRDY) || (FLAG == RCC_FLAG_PINRST) || \ + (FLAG == RCC_FLAG_PORRST) || (FLAG == RCC_FLAG_SFTRST) || \ + (FLAG == RCC_FLAG_IWDGRST)|| (FLAG == RCC_FLAG_WWDGRST)|| \ + (FLAG == RCC_FLAG_LPWRRST)) + +#define IS_RCC_CALIBRATION_VALUE(VALUE) (VALUE <= 0x1F) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void RCC_DeInit(void); +void RCC_HSEConfig(u32 RCC_HSE); +void RCC_AdjustHSICalibrationValue(u8 HSICalibrationValue); +void RCC_HSICmd(FunctionalState NewState); +void RCC_PLLConfig(u32 RCC_PLLSource, u32 RCC_PLLMul); +void RCC_PLLCmd(FunctionalState NewState); +void RCC_SYSCLKConfig(u32 RCC_SYSCLKSource); +u8 RCC_GetSYSCLKSource(void); +void RCC_HCLKConfig(u32 RCC_HCLK); +void RCC_PCLK1Config(u32 RCC_PCLK1); +void RCC_PCLK2Config(u32 RCC_PCLK2); +void RCC_ITConfig(u8 RCC_IT, FunctionalState NewState); +void RCC_USBCLKConfig(u32 RCC_USBCLKSource); +void RCC_ADCCLKConfig(u32 RCC_ADCCLK); +void RCC_LSEConfig(u32 RCC_LSE); +void RCC_LSICmd(FunctionalState NewState); +void RCC_RTCCLKConfig(u32 RCC_RTCCLKSource); +void RCC_RTCCLKCmd(FunctionalState NewState); +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); +void RCC_AHBPeriphClockCmd(u32 RCC_AHBPeriph, FunctionalState NewState); +void RCC_APB2PeriphClockCmd(u32 RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphClockCmd(u32 RCC_APB1Periph, FunctionalState NewState); +void RCC_APB2PeriphResetCmd(u32 RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphResetCmd(u32 RCC_APB1Periph, FunctionalState NewState); +void RCC_BackupResetCmd(FunctionalState NewState); +void RCC_ClockSecuritySystemCmd(FunctionalState NewState); +void RCC_MCOConfig(u8 RCC_MCO); +FlagStatus RCC_GetFlagStatus(u8 RCC_FLAG); +void RCC_ClearFlag(void); +ITStatus RCC_GetITStatus(u8 RCC_IT); +void RCC_ClearITPendingBit(u8 RCC_IT); + +#endif /* __STM32F10x_RCC_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_rtc.h b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_rtc.h new file mode 100644 index 000000000..6f8c4e0db --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_rtc.h @@ -0,0 +1,75 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_rtc.h +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file contains all the functions prototypes for the +* RTC firmware library. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_RTC_H +#define __STM32F10x_RTC_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* RTC interrupts define -----------------------------------------------------*/ +#define RTC_IT_OW ((u16)0x0004) /* Overflow interrupt */ +#define RTC_IT_ALR ((u16)0x0002) /* Alarm interrupt */ +#define RTC_IT_SEC ((u16)0x0001) /* Second interrupt */ + +#define IS_RTC_IT(IT) (((IT & (u16)0xFFF8) == 0x00) && (IT != 0x00)) + +#define IS_RTC_GET_IT(IT) ((IT == RTC_IT_OW) || (IT == RTC_IT_ALR) || \ + (IT == RTC_IT_SEC)) + +/* RTC interrupts flags ------------------------------------------------------*/ +#define RTC_FLAG_RTOFF ((u16)0x0020) /* RTC Operation OFF flag */ +#define RTC_FLAG_RSF ((u16)0x0008) /* Registers Synchronized flag */ +#define RTC_FLAG_OW ((u16)0x0004) /* Overflow flag */ +#define RTC_FLAG_ALR ((u16)0x0002) /* Alarm flag */ +#define RTC_FLAG_SEC ((u16)0x0001) /* Second flag */ + +#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG & (u16)0xFFF0) == 0x00) && (FLAG != 0x00)) + +#define IS_RTC_GET_FLAG(FLAG) ((FLAG == RTC_FLAG_RTOFF) || (FLAG == RTC_FLAG_RSF) || \ + (FLAG == RTC_FLAG_OW) || (FLAG == RTC_FLAG_ALR) || \ + (FLAG == RTC_FLAG_SEC)) + +#define IS_RTC_PRESCALER(PRESCALER) (PRESCALER <= 0xFFFFF) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void RTC_ITConfig(u16 RTC_IT, FunctionalState NewState); +void RTC_EnterConfigMode(void); +void RTC_ExitConfigMode(void); +u32 RTC_GetCounter(void); +void RTC_SetCounter(u32 CounterValue); +u32 RTC_GetPrescaler(void); +void RTC_SetPrescaler(u32 PrescalerValue); +void RTC_SetAlarm(u32 AlarmValue); +u32 RTC_GetDivider(void); +void RTC_WaitForLastTask(void); +void RTC_WaitForSynchro(void); +FlagStatus RTC_GetFlagStatus(u16 RTC_FLAG); +void RTC_ClearFlag(u16 RTC_FLAG); +ITStatus RTC_GetITStatus(u16 RTC_IT); +void RTC_ClearITPendingBit(u16 RTC_IT); + +#endif /* __STM32F10x_RTC_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_spi.h b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_spi.h new file mode 100644 index 000000000..3ca55e4c7 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_spi.h @@ -0,0 +1,202 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_spi.h +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file contains all the functions prototypes for the +* SPI firmware library. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_SPI_H +#define __STM32F10x_SPI_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* SPI Init structure definition */ +typedef struct +{ + u16 SPI_Direction; + u16 SPI_Mode; + u16 SPI_DataSize; + u16 SPI_CPOL; + u16 SPI_CPHA; + u16 SPI_NSS; + u16 SPI_BaudRatePrescaler; + u16 SPI_FirstBit; + u16 SPI_CRCPolynomial; +}SPI_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* SPI data direction mode */ +#define SPI_Direction_2Lines_FullDuplex ((u16)0x0000) +#define SPI_Direction_2Lines_RxOnly ((u16)0x0400) +#define SPI_Direction_1Line_Rx ((u16)0x8000) +#define SPI_Direction_1Line_Tx ((u16)0xC000) + +#define IS_SPI_DIRECTION_MODE(MODE) ((MODE == SPI_Direction_2Lines_FullDuplex) || \ + (MODE == SPI_Direction_2Lines_RxOnly) || \ + (MODE == SPI_Direction_1Line_Rx) || \ + (MODE == SPI_Direction_1Line_Tx)) + +/* SPI master/slave mode */ +#define SPI_Mode_Master ((u16)0x0104) +#define SPI_Mode_Slave ((u16)0x0000) + +#define IS_SPI_MODE(MODE) ((MODE == SPI_Mode_Master) || \ + (MODE == SPI_Mode_Slave)) + +/* SPI data size */ +#define SPI_DataSize_16b ((u16)0x0800) +#define SPI_DataSize_8b ((u16)0x0000) + +#define IS_SPI_DATASIZE(DATASIZE) ((DATASIZE == SPI_DataSize_16b) || \ + (DATASIZE == SPI_DataSize_8b)) + +/* SPI Clock Polarity */ +#define SPI_CPOL_Low ((u16)0x0000) +#define SPI_CPOL_High ((u16)0x0002) + +#define IS_SPI_CPOL(CPOL) ((CPOL == SPI_CPOL_Low) || \ + (CPOL == SPI_CPOL_High)) + +/* SPI Clock Phase */ +#define SPI_CPHA_1Edge ((u16)0x0000) +#define SPI_CPHA_2Edge ((u16)0x0001) + +#define IS_SPI_CPHA(CPHA) ((CPHA == SPI_CPHA_1Edge) || \ + (CPHA == SPI_CPHA_2Edge)) + +/* SPI Slave Select management */ +#define SPI_NSS_Soft ((u16)0x0200) +#define SPI_NSS_Hard ((u16)0x0000) + +#define IS_SPI_NSS(NSS) ((NSS == SPI_NSS_Soft) || \ + (NSS == SPI_NSS_Hard)) + +/* SPI BaudRate Prescaler */ +#define SPI_BaudRatePrescaler_2 ((u16)0x0000) +#define SPI_BaudRatePrescaler_4 ((u16)0x0008) +#define SPI_BaudRatePrescaler_8 ((u16)0x0010) +#define SPI_BaudRatePrescaler_16 ((u16)0x0018) +#define SPI_BaudRatePrescaler_32 ((u16)0x0020) +#define SPI_BaudRatePrescaler_64 ((u16)0x0028) +#define SPI_BaudRatePrescaler_128 ((u16)0x0030) +#define SPI_BaudRatePrescaler_256 ((u16)0x0038) + +#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) ((PRESCALER == SPI_BaudRatePrescaler_2) || \ + (PRESCALER == SPI_BaudRatePrescaler_4) || \ + (PRESCALER == SPI_BaudRatePrescaler_8) || \ + (PRESCALER == SPI_BaudRatePrescaler_16) || \ + (PRESCALER == SPI_BaudRatePrescaler_32) || \ + (PRESCALER == SPI_BaudRatePrescaler_64) || \ + (PRESCALER == SPI_BaudRatePrescaler_128) || \ + (PRESCALER == SPI_BaudRatePrescaler_256)) + +/* SPI MSB/LSB transmission */ +#define SPI_FirstBit_MSB ((u16)0x0000) +#define SPI_FirstBit_LSB ((u16)0x0080) + +#define IS_SPI_FIRST_BIT(BIT) ((BIT == SPI_FirstBit_MSB) || \ + (BIT == SPI_FirstBit_LSB)) + +/* SPI DMA transfer requests */ +#define SPI_DMAReq_Tx ((u16)0x0002) +#define SPI_DMAReq_Rx ((u16)0x0001) + +#define IS_SPI_DMA_REQ(REQ) (((REQ & (u16)0xFFFC) == 0x00) && (REQ != 0x00)) + +/* SPI NSS internal software mangement */ +#define SPI_NSSInternalSoft_Set ((u16)0x0100) +#define SPI_NSSInternalSoft_Reset ((u16)0xFEFF) + +#define IS_SPI_NSS_INTERNAL(INTERNAL) ((INTERNAL == SPI_NSSInternalSoft_Set) || \ + (INTERNAL == SPI_NSSInternalSoft_Reset)) + +/* SPI CRC Transmit/Receive */ +#define SPI_CRC_Tx ((u8)0x00) +#define SPI_CRC_Rx ((u8)0x01) + +#define IS_SPI_CRC(CRC) ((CRC == SPI_CRC_Tx) || (CRC == SPI_CRC_Rx)) + +/* SPI direction transmit/receive */ +#define SPI_Direction_Rx ((u16)0xBFFF) +#define SPI_Direction_Tx ((u16)0x4000) + +#define IS_SPI_DIRECTION(DIRECTION) ((DIRECTION == SPI_Direction_Rx) || \ + (DIRECTION == SPI_Direction_Tx)) + +/* SPI interrupts definition */ +#define SPI_IT_TXE ((u8)0x71) +#define SPI_IT_RXNE ((u8)0x60) +#define SPI_IT_ERR ((u8)0x50) + +#define IS_SPI_CONFIG_IT(IT) ((IT == SPI_IT_TXE) || (IT == SPI_IT_RXNE) || \ + (IT == SPI_IT_ERR)) + +#define SPI_IT_OVR ((u8)0x56) +#define SPI_IT_MODF ((u8)0x55) +#define SPI_IT_CRCERR ((u8)0x54) + +#define IS_SPI_CLEAR_IT(IT) ((IT == SPI_IT_OVR) || (IT == SPI_IT_MODF) || \ + (IT == SPI_IT_CRCERR)) + +#define IS_SPI_GET_IT(IT) ((IT == SPI_IT_TXE) || (IT == SPI_IT_RXNE) || \ + (IT == SPI_IT_OVR) || (IT == SPI_IT_MODF) || \ + (IT == SPI_IT_CRCERR)) + +/* SPI flags definition */ +#define SPI_FLAG_RXNE ((u16)0x0001) +#define SPI_FLAG_TXE ((u16)0x0002) +#define SPI_FLAG_CRCERR ((u16)0x0010) +#define SPI_FLAG_MODF ((u16)0x0020) +#define SPI_FLAG_OVR ((u16)0x0040) +#define SPI_FLAG_BSY ((u16)0x0080) + +#define IS_SPI_CLEAR_FLAG(FLAG) (((FLAG & (u16)0xFF8F) == 0x00) && (FLAG != 0x00)) +#define IS_SPI_GET_FLAG(FLAG) ((FLAG == SPI_FLAG_BSY) || (FLAG == SPI_FLAG_OVR) || \ + (FLAG == SPI_FLAG_MODF) || (FLAG == SPI_FLAG_CRCERR) || \ + (FLAG == SPI_FLAG_TXE) || (FLAG == SPI_FLAG_RXNE)) + +/* SPI CRC polynomial --------------------------------------------------------*/ +#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (POLYNOMIAL >= 0x1) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void SPI_DeInit(SPI_TypeDef* SPIx); +void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); +void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_ITConfig(SPI_TypeDef* SPIx, u8 SPI_IT, FunctionalState NewState); +void SPI_DMACmd(SPI_TypeDef* SPIx, u16 SPI_DMAReq, FunctionalState NewState); +void SPI_SendData(SPI_TypeDef* SPIx, u16 Data); +u16 SPI_ReceiveData(SPI_TypeDef* SPIx); +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, u16 SPI_NSSInternalSoft); +void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_DataSizeConfig(SPI_TypeDef* SPIx, u16 SPI_DataSize); +void SPI_TransmitCRC(SPI_TypeDef* SPIx); +void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); +u16 SPI_GetCRC(SPI_TypeDef* SPIx, u8 SPI_CRC); +u16 SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); +void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, u16 SPI_Direction); +FlagStatus SPI_GetFlagStatus(SPI_TypeDef* SPIx, u16 SPI_FLAG); +void SPI_ClearFlag(SPI_TypeDef* SPIx, u16 SPI_FLAG); +ITStatus SPI_GetITStatus(SPI_TypeDef* SPIx, u8 SPI_IT); +void SPI_ClearITPendingBit(SPI_TypeDef* SPIx, u8 SPI_IT); + +#endif /*__STM32F10x_SPI_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_systick.h b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_systick.h new file mode 100644 index 000000000..706080577 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_systick.h @@ -0,0 +1,68 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_systick.h +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file contains all the functions prototypes for the +* SysTick firmware library. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_SYSTICK_H +#define __STM32F10x_SYSTICK_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* SysTick clock source */ +#define SysTick_CLKSource_HCLK_Div8 ((u32)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((u32)0x00000004) + +#define IS_SYSTICK_CLK_SOURCE(SOURCE) ((SOURCE == SysTick_CLKSource_HCLK) || \ + (SOURCE == SysTick_CLKSource_HCLK_Div8)) + +/* SysTick counter state */ +#define SysTick_Counter_Disable ((u32)0xFFFFFFFE) +#define SysTick_Counter_Enable ((u32)0x00000001) +#define SysTick_Counter_Clear ((u32)0x00000000) + +#define IS_SYSTICK_COUNTER(COUNTER) ((COUNTER == SysTick_Counter_Disable) || \ + (COUNTER == SysTick_Counter_Enable) || \ + (COUNTER == SysTick_Counter_Clear)) + +/* SysTick Flag */ +#define SysTick_FLAG_COUNT ((u8)0x30) +#define SysTick_FLAG_SKEW ((u8)0x5E) +#define SysTick_FLAG_NOREF ((u8)0x5F) + +#define IS_SYSTICK_FLAG(FLAG) ((FLAG == SysTick_FLAG_COUNT) || \ + (FLAG == SysTick_FLAG_SKEW) || \ + (FLAG == SysTick_FLAG_NOREF)) + +#define IS_SYSTICK_RELOAD(RELOAD) ((RELOAD > 0) || (RELOAD <= 0xFFFFFF)) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void SysTick_CLKSourceConfig(u32 SysTick_CLKSource); +void SysTick_SetReload(u32 Reload); +void SysTick_CounterCmd(u32 SysTick_Counter); +void SysTick_ITConfig(FunctionalState NewState); +u32 SysTick_GetCounter(void); +FlagStatus SysTick_GetFlagStatus(u8 SysTick_FLAG); + +#endif /* __STM32F10x_SYSTICK_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_tim.h b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_tim.h new file mode 100644 index 000000000..12f837841 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_tim.h @@ -0,0 +1,513 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_tim.h +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file contains all the functions prototypes for the +* TIM firmware library. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_TIM_H +#define __STM32F10x_TIM_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ + +/* TIM Base Init structure definition */ +typedef struct +{ + u16 TIM_Period; /* Period value */ + u16 TIM_Prescaler; /* Prescaler value */ + u16 TIM_ClockDivision; /* Timer clock division */ + u16 TIM_CounterMode; /* Timer Counter mode */ +} TIM_TimeBaseInitTypeDef; + +/* TIM Output Compare Init structure definition */ +typedef struct +{ + u16 TIM_OCMode; /* Timer Output Compare Mode */ + u16 TIM_Channel; /* Timer Channel */ + u16 TIM_Pulse; /* PWM or OC Channel pulse length */ + u16 TIM_OCPolarity; /* PWM, OCM or OPM Channel polarity */ +} TIM_OCInitTypeDef; + +/* TIM Input Capture Init structure definition */ +typedef struct +{ + u16 TIM_ICMode; /* Timer Input Capture Mode */ + u16 TIM_Channel; /* Timer Channel */ + u16 TIM_ICPolarity; /* Input Capture polarity */ + u16 TIM_ICSelection; /* Input Capture selection */ + u16 TIM_ICPrescaler; /* Input Capture prescaler */ + u8 TIM_ICFilter; /* Input Capture filter */ +} TIM_ICInitTypeDef; + +/* Exported constants -------------------------------------------------------*/ +/* TIM Ouput Compare modes --------------------------------------------------*/ +#define TIM_OCMode_Timing ((u16)0x0000) +#define TIM_OCMode_Active ((u16)0x0010) +#define TIM_OCMode_Inactive ((u16)0x0020) +#define TIM_OCMode_Toggle ((u16)0x0030) +#define TIM_OCMode_PWM1 ((u16)0x0060) +#define TIM_OCMode_PWM2 ((u16)0x0070) + +#define IS_TIM_OC_MODE(MODE) ((MODE == TIM_OCMode_Timing) || \ + (MODE == TIM_OCMode_Active) || \ + (MODE == TIM_OCMode_Inactive) || \ + (MODE == TIM_OCMode_Toggle)|| \ + (MODE == TIM_OCMode_PWM1) || \ + (MODE == TIM_OCMode_PWM2)) + +/* TIM Input Capture modes --------------------------------------------------*/ +#define TIM_ICMode_ICAP ((u16)0x0007) +#define TIM_ICMode_PWMI ((u16)0x0006) + +#define IS_TIM_IC_MODE(MODE) ((MODE == TIM_ICMode_ICAP) || \ + (MODE == TIM_ICMode_PWMI)) + +/* TIM One Pulse Mode -------------------------------------------------------*/ +#define TIM_OPMode_Single ((u16)0x0008) +#define TIM_OPMode_Repetitive ((u16)0x0000) + +#define IS_TIM_OPM_MODE(MODE) ((MODE == TIM_OPMode_Single) || \ + (MODE == TIM_OPMode_Repetitive)) + +/* TIM Channel --------------------------------------------------------------*/ +#define TIM_Channel_1 ((u16)0x0000) +#define TIM_Channel_2 ((u16)0x0001) +#define TIM_Channel_3 ((u16)0x0002) +#define TIM_Channel_4 ((u16)0x0003) + +#define IS_TIM_CHANNEL(CHANNEL) ((CHANNEL == TIM_Channel_1) || \ + (CHANNEL == TIM_Channel_2) || \ + (CHANNEL == TIM_Channel_3) || \ + (CHANNEL == TIM_Channel_4)) + +/* TIM Clock Division CKD ---------------------------------------------------*/ +#define TIM_CKD_DIV1 ((u16)0x0000) +#define TIM_CKD_DIV2 ((u16)0x0100) +#define TIM_CKD_DIV4 ((u16)0x0200) + +#define IS_TIM_CKD_DIV(DIV) ((DIV == TIM_CKD_DIV1) || \ + (DIV == TIM_CKD_DIV2) || \ + (DIV == TIM_CKD_DIV4)) + +/* TIM Counter Mode ---------------------------------------------------------*/ +#define TIM_CounterMode_Up ((u16)0x0000) +#define TIM_CounterMode_Down ((u16)0x0010) +#define TIM_CounterMode_CenterAligned1 ((u16)0x0020) +#define TIM_CounterMode_CenterAligned2 ((u16)0x0040) +#define TIM_CounterMode_CenterAligned3 ((u16)0x0060) + +#define IS_TIM_COUNTER_MODE(MODE) ((MODE == TIM_CounterMode_Up) || \ + (MODE == TIM_CounterMode_Down) || \ + (MODE == TIM_CounterMode_CenterAligned1) || \ + (MODE == TIM_CounterMode_CenterAligned2) || \ + (MODE == TIM_CounterMode_CenterAligned3)) + +/* TIM Output Compare Polarity ----------------------------------------------*/ +#define TIM_OCPolarity_High ((u16)0x0000) +#define TIM_OCPolarity_Low ((u16)0x0002) + +#define IS_TIM_OC_POLARITY(POLARITY) ((POLARITY == TIM_OCPolarity_High) || \ + (POLARITY == TIM_OCPolarity_Low)) + +/* TIM Input Capture Polarity -----------------------------------------------*/ +#define TIM_ICPolarity_Rising ((u16)0x0000) +#define TIM_ICPolarity_Falling ((u16)0x0002) + +#define IS_TIM_IC_POLARITY(POLARITY) ((POLARITY == TIM_ICPolarity_Rising) || \ + (POLARITY == TIM_ICPolarity_Falling)) + +/* TIM Input Capture Channel Selection -------------------------------------*/ +#define TIM_ICSelection_DirectTI ((u16)0x0001) +#define TIM_ICSelection_IndirectTI ((u16)0x0002) +#define TIM_ICSelection_TRGI ((u16)0x0003) + +#define IS_TIM_IC_SELECTION(SELECTION) ((SELECTION == TIM_ICSelection_DirectTI) || \ + (SELECTION == TIM_ICSelection_IndirectTI) || \ + (SELECTION == TIM_ICSelection_TRGI)) + +/* TIM Input Capture Prescaler ----------------------------------------------*/ +#define TIM_ICPSC_DIV1 ((u16)0x0000) +#define TIM_ICPSC_DIV2 ((u16)0x0004) +#define TIM_ICPSC_DIV4 ((u16)0x0008) +#define TIM_ICPSC_DIV8 ((u16)0x000C) + +#define IS_TIM_IC_PRESCALER(PRESCALER) ((PRESCALER == TIM_ICPSC_DIV1) || \ + (PRESCALER == TIM_ICPSC_DIV2) || \ + (PRESCALER == TIM_ICPSC_DIV4) || \ + (PRESCALER == TIM_ICPSC_DIV8)) + +/* TIM Input Capture Filer Value ---------------------------------------------*/ +#define IS_TIM_IC_FILTER(ICFILTER) (ICFILTER <= 0xF) + +/* TIM interrupt sources ----------------------------------------------------*/ +#define TIM_IT_Update ((u16)0x0001) +#define TIM_IT_CC1 ((u16)0x0002) +#define TIM_IT_CC2 ((u16)0x0004) +#define TIM_IT_CC3 ((u16)0x0008) +#define TIM_IT_CC4 ((u16)0x0010) +#define TIM_IT_Trigger ((u16)0x0040) + +#define IS_TIM_IT(IT) (((IT & (u16)0xFFA0) == 0x0000) && (IT != 0x0000)) + +#define IS_TIM_GET_IT(IT) ((IT == TIM_IT_Update) || \ + (IT == TIM_IT_CC1) || \ + (IT == TIM_IT_CC2) || \ + (IT == TIM_IT_CC3) || \ + (IT == TIM_IT_CC4) || \ + (IT == TIM_IT_Trigger)) + +/* TIM DMA Base address -----------------------------------------------------*/ +#define TIM_DMABase_CR1 ((u16)0x0000) +#define TIM_DMABase_CR2 ((u16)0x0001) +#define TIM_DMABase_SMCR ((u16)0x0002) +#define TIM_DMABase_DIER ((u16)0x0003) +#define TIM_DMABase_SR ((u16)0x0004) +#define TIM_DMABase_EGR ((u16)0x0005) +#define TIM_DMABase_CCMR1 ((u16)0x0006) +#define TIM_DMABase_CCMR2 ((u16)0x0007) +#define TIM_DMABase_CCER ((u16)0x0008) +#define TIM_DMABase_CNT ((u16)0x0009) +#define TIM_DMABase_PSC ((u16)0x000A) +#define TIM_DMABase_ARR ((u16)0x000B) +#define TIM_DMABase_CCR1 ((u16)0x000D) +#define TIM_DMABase_CCR2 ((u16)0x000E) +#define TIM_DMABase_CCR3 ((u16)0x000F) +#define TIM_DMABase_CCR4 ((u16)0x0010) +#define TIM_DMABase_DCR ((u16)0x0012) + +#define IS_TIM_DMA_BASE(BASE) ((BASE == TIM_DMABase_CR1) || \ + (BASE == TIM_DMABase_CR2) || \ + (BASE == TIM_DMABase_SMCR) || \ + (BASE == TIM_DMABase_DIER) || \ + (BASE == TIM_DMABase_SR) || \ + (BASE == TIM_DMABase_EGR) || \ + (BASE == TIM_DMABase_CCMR1) || \ + (BASE == TIM_DMABase_CCMR2) || \ + (BASE == TIM_DMABase_CCER) || \ + (BASE == TIM_DMABase_CNT) || \ + (BASE == TIM_DMABase_PSC) || \ + (BASE == TIM_DMABase_ARR) || \ + (BASE == TIM_DMABase_CCR1) || \ + (BASE == TIM_DMABase_CCR2) || \ + (BASE == TIM_DMABase_CCR3) || \ + (BASE == TIM_DMABase_CCR4) || \ + (BASE == TIM_DMABase_DCR)) + +/* TIM DMA Burst Length -----------------------------------------------------*/ +#define TIM_DMABurstLength_1Byte ((u16)0x0000) +#define TIM_DMABurstLength_2Bytes ((u16)0x0100) +#define TIM_DMABurstLength_3Bytes ((u16)0x0200) +#define TIM_DMABurstLength_4Bytes ((u16)0x0300) +#define TIM_DMABurstLength_5Bytes ((u16)0x0400) +#define TIM_DMABurstLength_6Bytes ((u16)0x0500) +#define TIM_DMABurstLength_7Bytes ((u16)0x0600) +#define TIM_DMABurstLength_8Bytes ((u16)0x0700) +#define TIM_DMABurstLength_9Bytes ((u16)0x0800) +#define TIM_DMABurstLength_10Bytes ((u16)0x0900) +#define TIM_DMABurstLength_11Bytes ((u16)0x0A00) +#define TIM_DMABurstLength_12Bytes ((u16)0x0B00) +#define TIM_DMABurstLength_13Bytes ((u16)0x0C00) +#define TIM_DMABurstLength_14Bytes ((u16)0x0D00) +#define TIM_DMABurstLength_15Bytes ((u16)0x0E00) +#define TIM_DMABurstLength_16Bytes ((u16)0x0F00) +#define TIM_DMABurstLength_17Bytes ((u16)0x1000) +#define TIM_DMABurstLength_18Bytes ((u16)0x1100) + +#define IS_TIM_DMA_LENGTH(LENGTH) ((LENGTH == TIM_DMABurstLength_1Byte) || \ + (LENGTH == TIM_DMABurstLength_2Bytes) || \ + (LENGTH == TIM_DMABurstLength_3Bytes) || \ + (LENGTH == TIM_DMABurstLength_4Bytes) || \ + (LENGTH == TIM_DMABurstLength_5Bytes) || \ + (LENGTH == TIM_DMABurstLength_6Bytes) || \ + (LENGTH == TIM_DMABurstLength_7Bytes) || \ + (LENGTH == TIM_DMABurstLength_8Bytes) || \ + (LENGTH == TIM_DMABurstLength_9Bytes) || \ + (LENGTH == TIM_DMABurstLength_10Bytes) || \ + (LENGTH == TIM_DMABurstLength_11Bytes) || \ + (LENGTH == TIM_DMABurstLength_12Bytes) || \ + (LENGTH == TIM_DMABurstLength_13Bytes) || \ + (LENGTH == TIM_DMABurstLength_14Bytes) || \ + (LENGTH == TIM_DMABurstLength_15Bytes) || \ + (LENGTH == TIM_DMABurstLength_16Bytes) || \ + (LENGTH == TIM_DMABurstLength_17Bytes) || \ + (LENGTH == TIM_DMABurstLength_18Bytes)) + +/* TIM DMA sources ----------------------------------------------------------*/ +#define TIM_DMA_Update ((u16)0x0100) +#define TIM_DMA_CC1 ((u16)0x0200) +#define TIM_DMA_CC2 ((u16)0x0400) +#define TIM_DMA_CC3 ((u16)0x0800) +#define TIM_DMA_CC4 ((u16)0x1000) +#define TIM_DMA_Trigger ((u16)0x4000) + +#define IS_TIM_DMA_SOURCE(SOURCE) (((SOURCE & (u16)0xA0FF) == 0x0000) && (SOURCE != 0x0000)) + +/* TIM External Trigger Prescaler -------------------------------------------*/ +#define TIM_ExtTRGPSC_OFF ((u16)0x0000) +#define TIM_ExtTRGPSC_DIV2 ((u16)0x1000) +#define TIM_ExtTRGPSC_DIV4 ((u16)0x2000) +#define TIM_ExtTRGPSC_DIV8 ((u16)0x3000) + +#define IS_TIM_EXT_PRESCALER(PRESCALER) ((PRESCALER == TIM_ExtTRGPSC_OFF) || \ + (PRESCALER == TIM_ExtTRGPSC_DIV2) || \ + (PRESCALER == TIM_ExtTRGPSC_DIV4) || \ + (PRESCALER == TIM_ExtTRGPSC_DIV8)) + +/* TIM Input Trigger Selection ---------------------------------------------*/ +#define TIM_TS_ITR0 ((u16)0x0000) +#define TIM_TS_ITR1 ((u16)0x0010) +#define TIM_TS_ITR2 ((u16)0x0020) +#define TIM_TS_ITR3 ((u16)0x0030) +#define TIM_TS_TI1F_ED ((u16)0x0040) +#define TIM_TS_TI1FP1 ((u16)0x0050) +#define TIM_TS_TI2FP2 ((u16)0x0060) +#define TIM_TS_ETRF ((u16)0x0070) + +#define IS_TIM_TRIGGER_SELECTION(SELECTION) ((SELECTION == TIM_TS_ITR0) || \ + (SELECTION == TIM_TS_ITR1) || \ + (SELECTION == TIM_TS_ITR2) || \ + (SELECTION == TIM_TS_ITR3) || \ + (SELECTION == TIM_TS_TI1F_ED) || \ + (SELECTION == TIM_TS_TI1FP1) || \ + (SELECTION == TIM_TS_TI2FP2) || \ + (SELECTION == TIM_TS_ETRF)) + +#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) ((SELECTION == TIM_TS_ITR0) || \ + (SELECTION == TIM_TS_ITR1) || \ + (SELECTION == TIM_TS_ITR2) || \ + (SELECTION == TIM_TS_ITR3)) + +#define IS_TIM_TIX_TRIGGER_SELECTION(SELECTION) ((SELECTION == TIM_TS_TI1F_ED) || \ + (SELECTION == TIM_TS_TI1FP1) || \ + (SELECTION == TIM_TS_TI2FP2)) + +/* TIM External Trigger Polarity --------------------------------------------*/ +#define TIM_ExtTRGPolarity_Inverted ((u16)0x8000) +#define TIM_ExtTRGPolarity_NonInverted ((u16)0x0000) + +#define IS_TIM_EXT_POLARITY(POLARITY) ((POLARITY == TIM_ExtTRGPolarity_Inverted) || \ + (POLARITY == TIM_ExtTRGPolarity_NonInverted)) + +/* TIM Prescaler Reload Mode ------------------------------------------------*/ +#define TIM_PSCReloadMode_Update ((u16)0x0000) +#define TIM_PSCReloadMode_Immediate ((u16)0x0001) + +#define IS_TIM_PRESCALER_RELOAD(RELOAD) ((RELOAD == TIM_PSCReloadMode_Update) || \ + (RELOAD == TIM_PSCReloadMode_Immediate)) + +/* TIM Forced Action --------------------------------------------------------*/ +#define TIM_ForcedAction_Active ((u16)0x0050) +#define TIM_ForcedAction_InActive ((u16)0x0040) + +#define IS_TIM_FORCED_ACTION(ACTION) ((ACTION == TIM_ForcedAction_Active) || \ + (ACTION == TIM_ForcedAction_InActive)) + +/* TIM Encoder Mode ---------------------------------------------------------*/ +#define TIM_EncoderMode_TI1 ((u16)0x0001) +#define TIM_EncoderMode_TI2 ((u16)0x0002) +#define TIM_EncoderMode_TI12 ((u16)0x0003) + +#define IS_TIM_ENCODER_MODE(MODE) ((MODE == TIM_EncoderMode_TI1) || \ + (MODE == TIM_EncoderMode_TI2) || \ + (MODE == TIM_EncoderMode_TI12)) + +/* TIM Event Source ---------------------------------------------------------*/ +#define TIM_EventSource_Update ((u16)0x0001) +#define TIM_EventSource_CC1 ((u16)0x0002) +#define TIM_EventSource_CC2 ((u16)0x0004) +#define TIM_EventSource_CC3 ((u16)0x0008) +#define TIM_EventSource_CC4 ((u16)0x0010) +#define TIM_EventSource_Trigger ((u16)0x0040) + +#define IS_TIM_EVENT_SOURCE(SOURCE) (((SOURCE & (u16)0xFFA0) == 0x0000) && (SOURCE != 0x0000)) + + +/* TIM Update Source --------------------------------------------------------*/ +#define TIM_UpdateSource_Global ((u16)0x0000) +#define TIM_UpdateSource_Regular ((u16)0x0001) + +#define IS_TIM_UPDATE_SOURCE(SOURCE) ((SOURCE == TIM_UpdateSource_Global) || \ + (SOURCE == TIM_UpdateSource_Regular)) + +/* TIM Ouput Compare Preload State ------------------------------------------*/ +#define TIM_OCPreload_Enable ((u16)0x0008) +#define TIM_OCPreload_Disable ((u16)0x0000) + +#define IS_TIM_OCPRELOAD_STATE(STATE) ((STATE == TIM_OCPreload_Enable) || \ + (STATE == TIM_OCPreload_Disable)) + +/* TIM Ouput Compare Fast State ---------------------------------------------*/ +#define TIM_OCFast_Enable ((u16)0x0004) +#define TIM_OCFast_Disable ((u16)0x0000) + +#define IS_TIM_OCFAST_STATE(STATE) ((STATE == TIM_OCFast_Enable) || \ + (STATE == TIM_OCFast_Disable)) + +/* TIM Trigger Output Source ------------------------------------------------*/ +#define TIM_TRGOSource_Reset ((u16)0x0000) +#define TIM_TRGOSource_Enable ((u16)0x0010) +#define TIM_TRGOSource_Update ((u16)0x0020) +#define TIM_TRGOSource_OC1 ((u16)0x0030) +#define TIM_TRGOSource_OC1Ref ((u16)0x0040) +#define TIM_TRGOSource_OC2Ref ((u16)0x0050) +#define TIM_TRGOSource_OC3Ref ((u16)0x0060) +#define TIM_TRGOSource_OC4Ref ((u16)0x0070) + +#define IS_TIM_TRGO_SOURCE(SOURCE) ((SOURCE == TIM_TRGOSource_Reset) || \ + (SOURCE == TIM_TRGOSource_Enable) || \ + (SOURCE == TIM_TRGOSource_Update) || \ + (SOURCE == TIM_TRGOSource_OC1) || \ + (SOURCE == TIM_TRGOSource_OC1Ref) || \ + (SOURCE == TIM_TRGOSource_OC2Ref) || \ + (SOURCE == TIM_TRGOSource_OC3Ref) || \ + (SOURCE == TIM_TRGOSource_OC4Ref)) + +/* TIM Slave Mode -----------------------------------------------------------*/ +#define TIM_SlaveMode_Reset ((u16)0x0004) +#define TIM_SlaveMode_Gated ((u16)0x0005) +#define TIM_SlaveMode_Trigger ((u16)0x0006) +#define TIM_SlaveMode_External1 ((u16)0x0007) + + +#define IS_TIM_SLAVE_MODE(MODE) ((MODE == TIM_SlaveMode_Reset) || \ + (MODE == TIM_SlaveMode_Gated) || \ + (MODE == TIM_SlaveMode_Trigger) || \ + (MODE == TIM_SlaveMode_External1)) + +/* TIM TIx External Clock Source --------------------------------------------*/ +#define TIM_TIxExternalCLK1Source_TI1 ((u16)0x0050) +#define TIM_TIxExternalCLK1Source_TI2 ((u16)0x0060) +#define TIM_TIxExternalCLK1Source_TI1ED ((u16)0x0040) + +#define IS_TIM_TIXCLK_SOURCE(SOURCE) ((SOURCE == TIM_TIxExternalCLK1Source_TI1) || \ + (SOURCE == TIM_TIxExternalCLK1Source_TI2) || \ + (SOURCE == TIM_TIxExternalCLK1Source_TI1ED)) + + +/* TIM Master Slave Mode ----------------------------------------------------*/ +#define TIM_MasterSlaveMode_Enable ((u16)0x0080) +#define TIM_MasterSlaveMode_Disable ((u16)0x0000) + +#define IS_TIM_MSM_STATE(STATE) ((STATE == TIM_MasterSlaveMode_Enable) || \ + (STATE == TIM_MasterSlaveMode_Disable)) + +/* TIM Flags ----------------------------------------------------------------*/ +#define TIM_FLAG_Update ((u16)0x0001) +#define TIM_FLAG_CC1 ((u16)0x0002) +#define TIM_FLAG_CC2 ((u16)0x0004) +#define TIM_FLAG_CC3 ((u16)0x0008) +#define TIM_FLAG_CC4 ((u16)0x0010) +#define TIM_FLAG_Trigger ((u16)0x0040) +#define TIM_FLAG_CC1OF ((u16)0x0200) +#define TIM_FLAG_CC2OF ((u16)0x0400) +#define TIM_FLAG_CC3OF ((u16)0x0800) +#define TIM_FLAG_CC4OF ((u16)0x1000) + +#define IS_TIM_GET_FLAG(FLAG) ((FLAG == TIM_FLAG_Update) || \ + (FLAG == TIM_FLAG_CC1) || \ + (FLAG == TIM_FLAG_CC2) || \ + (FLAG == TIM_FLAG_CC3) || \ + (FLAG == TIM_FLAG_CC4) || \ + (FLAG == TIM_FLAG_Trigger) || \ + (FLAG == TIM_FLAG_CC1OF) || \ + (FLAG == TIM_FLAG_CC2OF) || \ + (FLAG == TIM_FLAG_CC3OF) || \ + (FLAG == TIM_FLAG_CC4OF)) + +#define IS_TIM_CLEAR_FLAG(FLAG) (((FLAG & (u16)0xE1A0) == 0x0000) && (FLAG != 0x0000)) + + + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +void TIM_DeInit(TIM_TypeDef* TIMx); +void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); +void TIM_OCInit(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); +void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_ITConfig(TIM_TypeDef* TIMx, u16 TIM_IT, FunctionalState NewState); +void TIM_DMAConfig(TIM_TypeDef* TIMx, u16 TIM_DMABase, u16 TIM_DMABurstLength); +void TIM_DMACmd(TIM_TypeDef* TIMx, u16 TIM_DMASource, FunctionalState Newstate); +void TIM_InternalClockConfig(TIM_TypeDef* TIMx); +void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, u16 TIM_InputTriggerSource); +void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, u16 TIM_TIxExternalCLKSource, + u16 TIM_ICPolarity, u8 ICFilter); +void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, u16 TIM_ExtTRGPolarity, + u8 ExtTRGFilter); +void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, u16 TIM_ExtTRGPolarity, + u8 ExtTRGFilter); +void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, u16 TIM_InputTriggerSource); +void TIM_PrescalerConfig(TIM_TypeDef* TIMx, u16 Prescaler, u16 TIM_PSCReloadMode); +void TIM_CounterModeConfig(TIM_TypeDef* TIMx, u16 TIM_CounterMode); +void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction); +void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction); +void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction); +void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction); +void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState Newstate); +void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState Newstate); +void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload); +void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload); +void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload); +void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload); +void TIM_OC1FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast); +void TIM_OC2FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast); +void TIM_OC3FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast); +void TIM_OC4FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast); +void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState Newstate); +void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, u16 TIM_EncoderMode, + u16 TIM_IC1Polarity, u16 TIM_IC2Polarity); +void TIM_GenerateEvent(TIM_TypeDef* TIMx, u16 TIM_EventSource); +void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity); +void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity); +void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity); +void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity); +void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, u16 TIM_UpdateSource); +void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState Newstate); +void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, u16 TIM_OPMode); +void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, u16 TIM_TRGOSource); +void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, u16 TIM_SlaveMode); +void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, u16 TIM_MasterSlaveMode); +void TIM_SetAutoreload(TIM_TypeDef* TIMx, u16 Autoreload); +void TIM_SetCompare1(TIM_TypeDef* TIMx, u16 Compare1); +void TIM_SetCompare2(TIM_TypeDef* TIMx, u16 Compare2); +void TIM_SetCompare3(TIM_TypeDef* TIMx, u16 Compare3); +void TIM_SetCompare4(TIM_TypeDef* TIMx, u16 Compare4); +void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC1Prescaler); +void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC2Prescaler); +void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC3Prescaler); +void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC4Prescaler); +void TIM_SetClockDivision(TIM_TypeDef* TIMx, u16 TIM_CKD); +u16 TIM_GetCapture1(TIM_TypeDef* TIMx); +u16 TIM_GetCapture2(TIM_TypeDef* TIMx); +u16 TIM_GetCapture3(TIM_TypeDef* TIMx); +u16 TIM_GetCapture4(TIM_TypeDef* TIMx); +u16 TIM_GetCounter(TIM_TypeDef* TIMx); +u16 TIM_GetPrescaler(TIM_TypeDef* TIMx); +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, u16 TIM_FLAG); +void TIM_ClearFlag(TIM_TypeDef* TIMx, u16 TIM_FLAG); +ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, u16 TIM_IT); +void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, u16 TIM_IT); + +#endif /*__STM32F10x_TIM_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_tim1.h b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_tim1.h new file mode 100644 index 000000000..b83761d96 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_tim1.h @@ -0,0 +1,644 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_tim1.h +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file contains all the functions prototypes for the +* TIM1 firmware library. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* mm/dd/yyyy: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_TIM1_H +#define __STM32F10x_TIM1_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ + +/* TIM1 Time Base Init structure definition */ +typedef struct +{ + u16 TIM1_Prescaler; + u16 TIM1_CounterMode; + u16 TIM1_Period; + u16 TIM1_ClockDivision; + u8 TIM1_RepetitionCounter; +} TIM1_TimeBaseInitTypeDef; + +/* TIM1 Output Compare Init structure definition */ +typedef struct +{ + u16 TIM1_OCMode; + u16 TIM1_OutputState; + u16 TIM1_OutputNState; + u16 TIM1_Pulse; + u16 TIM1_OCPolarity; + u16 TIM1_OCNPolarity; + u16 TIM1_OCIdleState; + u16 TIM1_OCNIdleState; +} TIM1_OCInitTypeDef; + +/* TIM1 Input Capture Init structure definition */ +typedef struct +{ + u16 TIM1_Channel; + u16 TIM1_ICPolarity; + u16 TIM1_ICSelection; + u16 TIM1_ICPrescaler; + u8 TIM1_ICFilter; +} TIM1_ICInitTypeDef; + +/* BDTR structure definition */ +typedef struct +{ + u16 TIM1_OSSRState; + u16 TIM1_OSSIState; + u16 TIM1_LOCKLevel; + u16 TIM1_DeadTime; + u16 TIM1_Break; + u16 TIM1_BreakPolarity; + u16 TIM1_AutomaticOutput; +} TIM1_BDTRInitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* TIM1 Output Compare and PWM modes ----------------------------------------*/ +#define TIM1_OCMode_Timing ((u16)0x0000) +#define TIM1_OCMode_Active ((u16)0x0010) +#define TIM1_OCMode_Inactive ((u16)0x0020) +#define TIM1_OCMode_Toggle ((u16)0x0030) +#define TIM1_OCMode_PWM1 ((u16)0x0060) +#define TIM1_OCMode_PWM2 ((u16)0x0070) + +#define IS_TIM1_OC_MODE(MODE) ((MODE == TIM1_OCMode_Timing) || \ + (MODE == TIM1_OCMode_Active) || \ + (MODE == TIM1_OCMode_Inactive) || \ + (MODE == TIM1_OCMode_Toggle)|| \ + (MODE == TIM1_OCMode_PWM1) || \ + (MODE == TIM1_OCMode_PWM2)) + +#define IS_TIM1_OCM(MODE)((MODE == TIM1_OCMode_Timing) || \ + (MODE == TIM1_OCMode_Active) || \ + (MODE == TIM1_OCMode_Inactive) || \ + (MODE == TIM1_OCMode_Toggle)|| \ + (MODE == TIM1_OCMode_PWM1) || \ + (MODE == TIM1_OCMode_PWM2) || \ + (MODE == TIM1_ForcedAction_Active) || \ + (MODE == TIM1_ForcedAction_InActive)) +/* TIM1 One Pulse Mode ------------------------------------------------------*/ +#define TIM1_OPMode_Single ((u16)0x0001) +#define TIM1_OPMode_Repetitive ((u16)0x0000) + +#define IS_TIM1_OPM_MODE(MODE) ((MODE == TIM1_OPMode_Single) || \ + (MODE == TIM1_OPMode_Repetitive)) + +/* TIM1 Channel -------------------------------------------------------------*/ +#define TIM1_Channel_1 ((u16)0x0000) +#define TIM1_Channel_2 ((u16)0x0001) +#define TIM1_Channel_3 ((u16)0x0002) +#define TIM1_Channel_4 ((u16)0x0003) + +#define IS_TIM1_CHANNEL(CHANNEL) ((CHANNEL == TIM1_Channel_1) || \ + (CHANNEL == TIM1_Channel_2) || \ + (CHANNEL == TIM1_Channel_3) || \ + (CHANNEL == TIM1_Channel_4)) + +#define IS_TIM1_PWMI_CHANNEL(CHANNEL) ((CHANNEL == TIM1_Channel_1) || \ + (CHANNEL == TIM1_Channel_2)) + +#define IS_TIM1_COMPLEMENTARY_CHANNEL(CHANNEL) ((CHANNEL == TIM1_Channel_1) || \ + (CHANNEL == TIM1_Channel_2) || \ + (CHANNEL == TIM1_Channel_3)) +/* TIM1 Clock Division CKD --------------------------------------------------*/ +#define TIM1_CKD_DIV1 ((u16)0x0000) +#define TIM1_CKD_DIV2 ((u16)0x0100) +#define TIM1_CKD_DIV4 ((u16)0x0200) + +#define IS_TIM1_CKD_DIV(DIV) ((DIV == TIM1_CKD_DIV1) || \ + (DIV == TIM1_CKD_DIV2) || \ + (DIV == TIM1_CKD_DIV4)) + +/* TIM1 Counter Mode --------------------------------------------------------*/ +#define TIM1_CounterMode_Up ((u16)0x0000) +#define TIM1_CounterMode_Down ((u16)0x0010) +#define TIM1_CounterMode_CenterAligned1 ((u16)0x0020) +#define TIM1_CounterMode_CenterAligned2 ((u16)0x0040) +#define TIM1_CounterMode_CenterAligned3 ((u16)0x0060) + +#define IS_TIM1_COUNTER_MODE(MODE) ((MODE == TIM1_CounterMode_Up) || \ + (MODE == TIM1_CounterMode_Down) || \ + (MODE == TIM1_CounterMode_CenterAligned1) || \ + (MODE == TIM1_CounterMode_CenterAligned2) || \ + (MODE == TIM1_CounterMode_CenterAligned3)) + +/* TIM1 Output Compare Polarity ---------------------------------------------*/ +#define TIM1_OCPolarity_High ((u16)0x0000) +#define TIM1_OCPolarity_Low ((u16)0x0001) + +#define IS_TIM1_OC_POLARITY(POLARITY) ((POLARITY == TIM1_OCPolarity_High) || \ + (POLARITY == TIM1_OCPolarity_Low)) + +/* TIM1 Output Compare N Polarity -------------------------------------------*/ +#define TIM1_OCNPolarity_High ((u16)0x0000) +#define TIM1_OCNPolarity_Low ((u16)0x0001) + +#define IS_TIM1_OCN_POLARITY(POLARITY) ((POLARITY == TIM1_OCNPolarity_High) || \ + (POLARITY == TIM1_OCNPolarity_Low)) + +/* TIM1 Output Compare states -----------------------------------------------*/ +#define TIM1_OutputState_Disable ((u16)0x0000) +#define TIM1_OutputState_Enable ((u16)0x0001) + +#define IS_TIM1_OUTPUT_STATE(STATE) ((STATE == TIM1_OutputState_Disable) || \ + (STATE == TIM1_OutputState_Enable)) + +/* TIM1 Output Compare N States ---------------------------------------------*/ +#define TIM1_OutputNState_Disable ((u16)0x0000) +#define TIM1_OutputNState_Enable ((u16)0x0001) + +#define IS_TIM1_OUTPUTN_STATE(STATE) ((STATE == TIM1_OutputNState_Disable) || \ + (STATE == TIM1_OutputNState_Enable)) + +/* Break Input enable/disable -----------------------------------------------*/ +#define TIM1_Break_Enable ((u16)0x1000) +#define TIM1_Break_Disable ((u16)0x0000) + +#define IS_TIM1_BREAK_STATE(STATE) ((STATE == TIM1_Break_Enable) || \ + (STATE == TIM1_Break_Disable)) + +/* Break Polarity -----------------------------------------------------------*/ +#define TIM1_BreakPolarity_Low ((u16)0x0000) +#define TIM1_BreakPolarity_High ((u16)0x2000) + +#define IS_TIM1_BREAK_POLARITY(POLARITY) ((POLARITY == TIM1_BreakPolarity_Low) || \ + (POLARITY == TIM1_BreakPolarity_High)) + +/* TIM1 AOE Bit Set/Reset ---------------------------------------------------*/ +#define TIM1_AutomaticOutput_Enable ((u16)0x4000) +#define TIM1_AutomaticOutput_Disable ((u16)0x0000) + +#define IS_TIM1_AUTOMATIC_OUTPUT_STATE(STATE) ((STATE == TIM1_AutomaticOutput_Enable) || \ + (STATE == TIM1_AutomaticOutput_Disable)) +/* Lock levels --------------------------------------------------------------*/ +#define TIM1_LOCKLevel_OFF ((u16)0x0000) +#define TIM1_LOCKLevel_1 ((u16)0x0100) +#define TIM1_LOCKLevel_2 ((u16)0x0200) +#define TIM1_LOCKLevel_3 ((u16)0x0300) + +#define IS_TIM1_LOCK_LEVEL(LEVEL) ((LEVEL == TIM1_LOCKLevel_OFF) || \ + (LEVEL == TIM1_LOCKLevel_1) || \ + (LEVEL == TIM1_LOCKLevel_2) || \ + (LEVEL == TIM1_LOCKLevel_3)) + +/* OSSI: Off-State Selection for Idle mode states ---------------------------*/ +#define TIM1_OSSIState_Enable ((u16)0x0400) +#define TIM1_OSSIState_Disable ((u16)0x0000) + +#define IS_TIM1_OSSI_STATE(STATE) ((STATE == TIM1_OSSIState_Enable) || \ + (STATE == TIM1_OSSIState_Disable)) + +/* OSSR: Off-State Selection for Run mode states ----------------------------*/ +#define TIM1_OSSRState_Enable ((u16)0x0800) +#define TIM1_OSSRState_Disable ((u16)0x0000) + +#define IS_TIM1_OSSR_STATE(STATE) ((STATE == TIM1_OSSRState_Enable) || \ + (STATE == TIM1_OSSRState_Disable)) + +/* TIM1 Output Compare Idle State -------------------------------------------*/ +#define TIM1_OCIdleState_Set ((u16)0x0001) +#define TIM1_OCIdleState_Reset ((u16)0x0000) + +#define IS_TIM1_OCIDLE_STATE(STATE) ((STATE == TIM1_OCIdleState_Set) || \ + (STATE == TIM1_OCIdleState_Reset)) + +/* TIM1 Output Compare N Idle State -----------------------------------------*/ +#define TIM1_OCNIdleState_Set ((u16)0x0001) +#define TIM1_OCNIdleState_Reset ((u16)0x0000) + +#define IS_TIM1_OCNIDLE_STATE(STATE) ((STATE == TIM1_OCNIdleState_Set) || \ + (STATE == TIM1_OCNIdleState_Reset)) + +/* TIM1 Input Capture Polarity ----------------------------------------------*/ +#define TIM1_ICPolarity_Rising ((u16)0x0000) +#define TIM1_ICPolarity_Falling ((u16)0x0001) + +#define IS_TIM1_IC_POLARITY(POLARITY) ((POLARITY == TIM1_ICPolarity_Rising) || \ + (POLARITY == TIM1_ICPolarity_Falling)) + +/* TIM1 Input Capture Selection ---------------------------------------------*/ +#define TIM1_ICSelection_DirectTI ((u16)0x0001) +#define TIM1_ICSelection_IndirectTI ((u16)0x0002) +#define TIM1_ICSelection_TRGI ((u16)0x0003) + +#define IS_TIM1_IC_SELECTION(SELECTION) ((SELECTION == TIM1_ICSelection_DirectTI) || \ + (SELECTION == TIM1_ICSelection_IndirectTI) || \ + (SELECTION == TIM1_ICSelection_TRGI)) + +/* TIM1 Input Capture Prescaler ---------------------------------------------*/ +#define TIM1_ICPSC_DIV1 ((u16)0x0000) +#define TIM1_ICPSC_DIV2 ((u16)0x0004) +#define TIM1_ICPSC_DIV4 ((u16)0x0008) +#define TIM1_ICPSC_DIV8 ((u16)0x000C) + +#define IS_TIM1_IC_PRESCALER(PRESCALER) ((PRESCALER == TIM1_ICPSC_DIV1) || \ + (PRESCALER == TIM1_ICPSC_DIV2) || \ + (PRESCALER == TIM1_ICPSC_DIV4) || \ + (PRESCALER == TIM1_ICPSC_DIV8)) + +/* TIM1 Input Capture Filer Value ---------------------------------------------*/ +#define IS_TIM1_IC_FILTER(ICFILTER) (ICFILTER <= 0xF) + +/* TIM1 interrupt sources ---------------------------------------------------*/ +#define TIM1_IT_Update ((u16)0x0001) +#define TIM1_IT_CC1 ((u16)0x0002) +#define TIM1_IT_CC2 ((u16)0x0004) +#define TIM1_IT_CC3 ((u16)0x0008) +#define TIM1_IT_CC4 ((u16)0x0010) +#define TIM1_IT_COM ((u16)0x0020) +#define TIM1_IT_Trigger ((u16)0x0040) +#define TIM1_IT_Break ((u16)0x0080) + +#define IS_TIM1_IT(IT) (((IT & (u16)0xFF00) == 0x0000) && (IT != 0x0000)) + +#define IS_TIM1_GET_IT(IT) ((IT == TIM1_IT_Update) || \ + (IT == TIM1_IT_CC1) || \ + (IT == TIM1_IT_CC2) || \ + (IT == TIM1_IT_CC3) || \ + (IT == TIM1_IT_CC4) || \ + (IT == TIM1_IT_COM) || \ + (IT == TIM1_IT_Trigger) || \ + (IT == TIM1_IT_Break)) + +/* TIM1 DMA Base address ----------------------------------------------------*/ +#define TIM1_DMABase_CR1 ((u16)0x0000) +#define TIM1_DMABase_CR2 ((u16)0x0001) +#define TIM1_DMABase_SMCR ((u16)0x0002) +#define TIM1_DMABase_DIER ((u16)0x0003) +#define TIM1_DMABase_SR ((u16)0x0004) +#define TIM1_DMABase_EGR ((u16)0x0005) +#define TIM1_DMABase_CCMR1 ((u16)0x0006) +#define TIM1_DMABase_CCMR2 ((u16)0x0007) +#define TIM1_DMABase_CCER ((u16)0x0008) +#define TIM1_DMABase_CNT ((u16)0x0009) +#define TIM1_DMABase_PSC ((u16)0x000A) +#define TIM1_DMABase_ARR ((u16)0x000B) +#define TIM1_DMABase_RCR ((u16)0x000C) +#define TIM1_DMABase_CCR1 ((u16)0x000D) +#define TIM1_DMABase_CCR2 ((u16)0x000E) +#define TIM1_DMABase_CCR3 ((u16)0x000F) +#define TIM1_DMABase_CCR4 ((u16)0x0010) +#define TIM1_DMABase_BDTR ((u16)0x0011) +#define TIM1_DMABase_DCR ((u16)0x0012) + +#define IS_TIM1_DMA_BASE(BASE) ((BASE == TIM1_DMABase_CR1) || \ + (BASE == TIM1_DMABase_CR2) || \ + (BASE == TIM1_DMABase_SMCR) || \ + (BASE == TIM1_DMABase_DIER) || \ + (BASE == TIM1_DMABase_SR) || \ + (BASE == TIM1_DMABase_EGR) || \ + (BASE == TIM1_DMABase_CCMR1) || \ + (BASE == TIM1_DMABase_CCMR2) || \ + (BASE == TIM1_DMABase_CCER) || \ + (BASE == TIM1_DMABase_CNT) || \ + (BASE == TIM1_DMABase_PSC) || \ + (BASE == TIM1_DMABase_ARR) || \ + (BASE == TIM1_DMABase_RCR) || \ + (BASE == TIM1_DMABase_CCR1) || \ + (BASE == TIM1_DMABase_CCR2) || \ + (BASE == TIM1_DMABase_CCR3) || \ + (BASE == TIM1_DMABase_CCR4) || \ + (BASE == TIM1_DMABase_BDTR) || \ + (BASE == TIM1_DMABase_DCR)) + +/* TIM1 DMA Burst Length ----------------------------------------------------*/ +#define TIM1_DMABurstLength_1Byte ((u16)0x0000) +#define TIM1_DMABurstLength_2Bytes ((u16)0x0100) +#define TIM1_DMABurstLength_3Bytes ((u16)0x0200) +#define TIM1_DMABurstLength_4Bytes ((u16)0x0300) +#define TIM1_DMABurstLength_5Bytes ((u16)0x0400) +#define TIM1_DMABurstLength_6Bytes ((u16)0x0500) +#define TIM1_DMABurstLength_7Bytes ((u16)0x0600) +#define TIM1_DMABurstLength_8Bytes ((u16)0x0700) +#define TIM1_DMABurstLength_9Bytes ((u16)0x0800) +#define TIM1_DMABurstLength_10Bytes ((u16)0x0900) +#define TIM1_DMABurstLength_11Bytes ((u16)0x0A00) +#define TIM1_DMABurstLength_12Bytes ((u16)0x0B00) +#define TIM1_DMABurstLength_13Bytes ((u16)0x0C00) +#define TIM1_DMABurstLength_14Bytes ((u16)0x0D00) +#define TIM1_DMABurstLength_15Bytes ((u16)0x0E00) +#define TIM1_DMABurstLength_16Bytes ((u16)0x0F00) +#define TIM1_DMABurstLength_17Bytes ((u16)0x1000) +#define TIM1_DMABurstLength_18Bytes ((u16)0x1100) + +#define IS_TIM1_DMA_LENGTH(LENGTH) ((LENGTH == TIM1_DMABurstLength_1Byte) || \ + (LENGTH == TIM1_DMABurstLength_2Bytes) || \ + (LENGTH == TIM1_DMABurstLength_3Bytes) || \ + (LENGTH == TIM1_DMABurstLength_4Bytes) || \ + (LENGTH == TIM1_DMABurstLength_5Bytes) || \ + (LENGTH == TIM1_DMABurstLength_6Bytes) || \ + (LENGTH == TIM1_DMABurstLength_7Bytes) || \ + (LENGTH == TIM1_DMABurstLength_8Bytes) || \ + (LENGTH == TIM1_DMABurstLength_9Bytes) || \ + (LENGTH == TIM1_DMABurstLength_10Bytes) || \ + (LENGTH == TIM1_DMABurstLength_11Bytes) || \ + (LENGTH == TIM1_DMABurstLength_12Bytes) || \ + (LENGTH == TIM1_DMABurstLength_13Bytes) || \ + (LENGTH == TIM1_DMABurstLength_14Bytes) || \ + (LENGTH == TIM1_DMABurstLength_15Bytes) || \ + (LENGTH == TIM1_DMABurstLength_16Bytes) || \ + (LENGTH == TIM1_DMABurstLength_17Bytes) || \ + (LENGTH == TIM1_DMABurstLength_18Bytes)) + +/* TIM1 DMA sources ---------------------------------------------------------*/ +#define TIM1_DMA_Update ((u16)0x0100) +#define TIM1_DMA_CC1 ((u16)0x0200) +#define TIM1_DMA_CC2 ((u16)0x0400) +#define TIM1_DMA_CC3 ((u16)0x0800) +#define TIM1_DMA_CC4 ((u16)0x1000) +#define TIM1_DMA_COM ((u16)0x2000) +#define TIM1_DMA_Trigger ((u16)0x4000) + +#define IS_TIM1_DMA_SOURCE(SOURCE) (((SOURCE & (u16)0x80FF) == 0x0000) && (SOURCE != 0x0000)) + +/* TIM1 External Trigger Prescaler ------------------------------------------*/ +#define TIM1_ExtTRGPSC_OFF ((u16)0x0000) +#define TIM1_ExtTRGPSC_DIV2 ((u16)0x1000) +#define TIM1_ExtTRGPSC_DIV4 ((u16)0x2000) +#define TIM1_ExtTRGPSC_DIV8 ((u16)0x3000) + +#define IS_TIM1_EXT_PRESCALER(PRESCALER) ((PRESCALER == TIM1_ExtTRGPSC_OFF) || \ + (PRESCALER == TIM1_ExtTRGPSC_DIV2) || \ + (PRESCALER == TIM1_ExtTRGPSC_DIV4) || \ + (PRESCALER == TIM1_ExtTRGPSC_DIV8)) + +/* TIM1 Internal Trigger Selection ------------------------------------------*/ +#define TIM1_TS_ITR0 ((u16)0x0000) +#define TIM1_TS_ITR1 ((u16)0x0010) +#define TIM1_TS_ITR2 ((u16)0x0020) +#define TIM1_TS_ITR3 ((u16)0x0030) +#define TIM1_TS_TI1F_ED ((u16)0x0040) +#define TIM1_TS_TI1FP1 ((u16)0x0050) +#define TIM1_TS_TI2FP2 ((u16)0x0060) +#define TIM1_TS_ETRF ((u16)0x0070) + +#define IS_TIM1_TRIGGER_SELECTION(SELECTION) ((SELECTION == TIM1_TS_ITR0) || \ + (SELECTION == TIM1_TS_ITR1) || \ + (SELECTION == TIM1_TS_ITR2) || \ + (SELECTION == TIM1_TS_ITR3) || \ + (SELECTION == TIM1_TS_TI1F_ED) || \ + (SELECTION == TIM1_TS_TI1FP1) || \ + (SELECTION == TIM1_TS_TI2FP2) || \ + (SELECTION == TIM1_TS_ETRF)) + +#define IS_TIM1_INTERNAL_TRIGGER_SELECTION(SELECTION) ((SELECTION == TIM1_TS_ITR0) || \ + (SELECTION == TIM1_TS_ITR1) || \ + (SELECTION == TIM1_TS_ITR2) || \ + (SELECTION == TIM1_TS_ITR3)) + +#define IS_TIM1_TIX_TRIGGER_SELECTION(SELECTION) ((SELECTION == TIM1_TS_TI1F_ED) || \ + (SELECTION == TIM1_TS_TI1FP1) || \ + (SELECTION == TIM1_TS_TI2FP2)) + +/* TIM1 External Trigger Polarity -------------------------------------------*/ +#define TIM1_ExtTRGPolarity_Inverted ((u16)0x8000) +#define TIM1_ExtTRGPolarity_NonInverted ((u16)0x0000) + +#define IS_TIM1_EXT_POLARITY(POLARITY) ((POLARITY == TIM1_ExtTRGPolarity_Inverted) || \ + (POLARITY == TIM1_ExtTRGPolarity_NonInverted)) + +/* TIM1 Prescaler Reload Mode -----------------------------------------------*/ +#define TIM1_PSCReloadMode_Update ((u16)0x0000) +#define TIM1_PSCReloadMode_Immediate ((u16)0x0001) + +#define IS_TIM1_PRESCALER_RELOAD(RELOAD) ((RELOAD == TIM1_PSCReloadMode_Update) || \ + (RELOAD == TIM1_PSCReloadMode_Immediate)) + +/* TIM1 Forced Action -------------------------------------------------------*/ +#define TIM1_ForcedAction_Active ((u16)0x0050) +#define TIM1_ForcedAction_InActive ((u16)0x0040) + +#define IS_TIM1_FORCED_ACTION(ACTION) ((ACTION == TIM1_ForcedAction_Active) || \ + (ACTION == TIM1_ForcedAction_InActive)) + +/* TIM1 Encoder Mode --------------------------------------------------------*/ +#define TIM1_EncoderMode_TI1 ((u16)0x0001) +#define TIM1_EncoderMode_TI2 ((u16)0x0002) +#define TIM1_EncoderMode_TI12 ((u16)0x0003) + +#define IS_TIM1_ENCODER_MODE(MODE) ((MODE == TIM1_EncoderMode_TI1) || \ + (MODE == TIM1_EncoderMode_TI2) || \ + (MODE == TIM1_EncoderMode_TI12)) + +/* TIM1 Event Source --------------------------------------------------------*/ +#define TIM1_EventSource_Update ((u16)0x0001) +#define TIM1_EventSource_CC1 ((u16)0x0002) +#define TIM1_EventSource_CC2 ((u16)0x0004) +#define TIM1_EventSource_CC3 ((u16)0x0008) +#define TIM1_EventSource_CC4 ((u16)0x0010) +#define TIM1_EventSource_COM ((u16)0x0020) +#define TIM1_EventSource_Trigger ((u16)0x0040) +#define TIM1_EventSource_Break ((u16)0x0080) + +#define IS_TIM1_EVENT_SOURCE(SOURCE) (((SOURCE & (u16)0xFF00) == 0x0000) && (SOURCE != 0x0000)) + + +/* TIM1 Update Source -------------------------------------------------------*/ +#define TIM1_UpdateSource_Global ((u16)0x0000) +#define TIM1_UpdateSource_Regular ((u16)0x0001) + +#define IS_TIM1_UPDATE_SOURCE(SOURCE) ((SOURCE == TIM1_UpdateSource_Global) || \ + (SOURCE == TIM1_UpdateSource_Regular)) + +/* TIM1 Ouput Compare Preload State ------------------------------------------*/ +#define TIM1_OCPreload_Enable ((u16)0x0001) +#define TIM1_OCPreload_Disable ((u16)0x0000) + +#define IS_TIM1_OCPRELOAD_STATE(STATE) ((STATE == TIM1_OCPreload_Enable) || \ + (STATE == TIM1_OCPreload_Disable)) + +/* TIM1 Ouput Compare Fast State ---------------------------------------------*/ +#define TIM1_OCFast_Enable ((u16)0x0001) +#define TIM1_OCFast_Disable ((u16)0x0000) + +#define IS_TIM1_OCFAST_STATE(STATE) ((STATE == TIM1_OCFast_Enable) || \ + (STATE == TIM1_OCFast_Disable)) + +/* TIM1 Trigger Output Source -----------------------------------------------*/ +#define TIM1_TRGOSource_Reset ((u16)0x0000) +#define TIM1_TRGOSource_Enable ((u16)0x0010) +#define TIM1_TRGOSource_Update ((u16)0x0020) +#define TIM1_TRGOSource_OC1 ((u16)0x0030) +#define TIM1_TRGOSource_OC1Ref ((u16)0x0040) +#define TIM1_TRGOSource_OC2Ref ((u16)0x0050) +#define TIM1_TRGOSource_OC3Ref ((u16)0x0060) +#define TIM1_TRGOSource_OC4Ref ((u16)0x0070) + +#define IS_TIM1_TRGO_SOURCE(SOURCE) ((SOURCE == TIM1_TRGOSource_Reset) || \ + (SOURCE == TIM1_TRGOSource_Enable) || \ + (SOURCE == TIM1_TRGOSource_Update) || \ + (SOURCE == TIM1_TRGOSource_OC1) || \ + (SOURCE == TIM1_TRGOSource_OC1Ref) || \ + (SOURCE == TIM1_TRGOSource_OC2Ref) || \ + (SOURCE == TIM1_TRGOSource_OC3Ref) || \ + (SOURCE == TIM1_TRGOSource_OC4Ref)) + +/* TIM1 Slave Mode ----------------------------------------------------------*/ +#define TIM1_SlaveMode_Reset ((u16)0x0004) +#define TIM1_SlaveMode_Gated ((u16)0x0005) +#define TIM1_SlaveMode_Trigger ((u16)0x0006) +#define TIM1_SlaveMode_External1 ((u16)0x0007) + +#define IS_TIM1_SLAVE_MODE(MODE) ((MODE == TIM1_SlaveMode_Reset) || \ + (MODE == TIM1_SlaveMode_Gated) || \ + (MODE == TIM1_SlaveMode_Trigger) || \ + (MODE == TIM1_SlaveMode_External1)) + +/* TIM1 TIx External Clock Source -------------------------------------------*/ +#define TIM1_TIxExternalCLK1Source_TI1 ((u16)0x0050) +#define TIM1_TIxExternalCLK1Source_TI2 ((u16)0x0060) +#define TIM1_TIxExternalCLK1Source_TI1ED ((u16)0x0040) + +#define IS_TIM1_TIXCLK_SOURCE(SOURCE) ((SOURCE == TIM1_TIxExternalCLK1Source_TI1) || \ + (SOURCE == TIM1_TIxExternalCLK1Source_TI2) || \ + (SOURCE == TIM1_TIxExternalCLK1Source_TI1ED)) + +/* TIM1 Master Slave Mode ---------------------------------------------------*/ +#define TIM1_MasterSlaveMode_Enable ((u16)0x0001) +#define TIM1_MasterSlaveMode_Disable ((u16)0x0000) + +#define IS_TIM1_MSM_STATE(STATE) ((STATE == TIM1_MasterSlaveMode_Enable) || \ + (STATE == TIM1_MasterSlaveMode_Disable)) + +/* TIM1 Flags ---------------------------------------------------------------*/ +#define TIM1_FLAG_Update ((u16)0x0001) +#define TIM1_FLAG_CC1 ((u16)0x0002) +#define TIM1_FLAG_CC2 ((u16)0x0004) +#define TIM1_FLAG_CC3 ((u16)0x0008) +#define TIM1_FLAG_CC4 ((u16)0x0010) +#define TIM1_FLAG_COM ((u16)0x0020) +#define TIM1_FLAG_Trigger ((u16)0x0040) +#define TIM1_FLAG_Break ((u16)0x0080) +#define TIM1_FLAG_CC1OF ((u16)0x0200) +#define TIM1_FLAG_CC2OF ((u16)0x0400) +#define TIM1_FLAG_CC3OF ((u16)0x0800) +#define TIM1_FLAG_CC4OF ((u16)0x1000) + +#define IS_TIM1_GET_FLAG(FLAG) ((FLAG == TIM1_FLAG_Update) || \ + (FLAG == TIM1_FLAG_CC1) || \ + (FLAG == TIM1_FLAG_CC2) || \ + (FLAG == TIM1_FLAG_CC3) || \ + (FLAG == TIM1_FLAG_CC4) || \ + (FLAG == TIM1_FLAG_COM) || \ + (FLAG == TIM1_FLAG_Trigger) || \ + (FLAG == TIM1_FLAG_Break) || \ + (FLAG == TIM1_FLAG_CC1OF) || \ + (FLAG == TIM1_FLAG_CC2OF) || \ + (FLAG == TIM1_FLAG_CC3OF) || \ + (FLAG == TIM1_FLAG_CC4OF)) + +#define IS_TIM1_CLEAR_FLAG(FLAG) (((FLAG & (u16)0xE100) == 0x0000) && (FLAG != 0x0000)) + + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +void TIM1_DeInit(void); +void TIM1_TimeBaseInit(TIM1_TimeBaseInitTypeDef* TIM1_TimeBaseInitStruct); +void TIM1_OC1Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct); +void TIM1_OC2Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct); +void TIM1_OC3Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct); +void TIM1_OC4Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct); +void TIM1_BDTRConfig(TIM1_BDTRInitTypeDef *TIM1_BDTRInitStruct); +void TIM1_ICInit(TIM1_ICInitTypeDef* TIM1_ICInitStruct); +void TIM1_PWMIConfig(TIM1_ICInitTypeDef* TIM1_ICInitStruct); +void TIM1_TimeBaseStructInit(TIM1_TimeBaseInitTypeDef* TIM1_TimeBaseInitStruct); +void TIM1_OCStructInit(TIM1_OCInitTypeDef* TIM1_OCInitStruct); +void TIM1_ICStructInit(TIM1_ICInitTypeDef* TIM1_ICInitStruct); +void TIM1_BDTRStructInit(TIM1_BDTRInitTypeDef* TIM1_BDTRInitStruct); +void TIM1_Cmd(FunctionalState NewState); +void TIM1_CtrlPWMOutputs(FunctionalState Newstate); +void TIM1_ITConfig(u16 TIM1_IT, FunctionalState NewState); +void TIM1_DMAConfig(u16 TIM1_DMABase, u16 TIM1_DMABurstLength); +void TIM1_DMACmd(u16 TIM1_DMASource, FunctionalState Newstate); +void TIM1_InternalClockConfig(void); +void TIM1_ETRClockMode1Config(u16 TIM1_ExtTRGPrescaler, u16 TIM1_ExtTRGPolarity, + u16 ExtTRGFilter); +void TIM1_ETRClockMode2Config(u16 TIM1_ExtTRGPrescaler, u16 TIM1_ExtTRGPolarity, + u16 ExtTRGFilter); +void TIM1_ITRxExternalClockConfig(u16 TIM1_InputTriggerSource); +void TIM1_TIxExternalClockConfig(u16 TIM1_TIxExternalCLKSource, u16 TIM1_ICPolarity, + u8 ICFilter); +void TIM1_SelectInputTrigger(u16 TIM1_InputTriggerSource); +void TIM1_UpdateDisableConfig(FunctionalState Newstate); +void TIM1_UpdateRequestConfig(u8 TIM1_UpdateSource); +void TIM1_SelectHallSensor(FunctionalState Newstate); +void TIM1_SelectOnePulseMode(u16 TIM1_OPMode); +void TIM1_SelectOutputTrigger(u16 TIM1_TRGOSource); +void TIM1_SelectSlaveMode(u16 TIM1_SlaveMode); +void TIM1_SelectMasterSlaveMode(u16 TIM1_MasterSlaveMode); +void TIM1_EncoderInterfaceConfig(u16 TIM1_EncoderMode, u16 TIM1_IC1Polarity, + u16 TIM1_IC2Polarity); +void TIM1_PrescalerConfig(u16 Prescaler, u16 TIM1_PSCReloadMode); +void TIM1_CounterModeConfig(u16 TIM1_CounterMode); +void TIM1_ForcedOC1Config(u16 TIM1_ForcedAction); +void TIM1_ForcedOC2Config(u16 TIM1_ForcedAction); +void TIM1_ForcedOC3Config(u16 TIM1_ForcedAction); +void TIM1_ForcedOC4Config(u16 TIM1_ForcedAction); +void TIM1_ARRPreloadConfig(FunctionalState Newstate); +void TIM1_SelectCOM(FunctionalState Newstate); +void TIM1_SelectCCDMA(FunctionalState Newstate); +void TIM1_CCPreloadControl(FunctionalState Newstate); +void TIM1_OC1PreloadConfig(u16 TIM1_OCPreload); +void TIM1_OC2PreloadConfig(u16 TIM1_OCPreload); +void TIM1_OC3PreloadConfig(u16 TIM1_OCPreload); +void TIM1_OC4PreloadConfig(u16 TIM1_OCPreload); +void TIM1_OC1FastConfig(u16 TIM1_OCFast); +void TIM1_OC2FastConfig(u16 TIM1_OCFast); +void TIM1_OC3FastConfig(u16 TIM1_OCFast); +void TIM1_OC4FastConfig(u16 TIM1_OCFast); +void TIM1_GenerateEvent(u16 TIM1_EventSource); +void TIM1_OC1PolarityConfig(u16 TIM1_OCPolarity); +void TIM1_OC1NPolarityConfig(u16 TIM1_OCPolarity); +void TIM1_OC2PolarityConfig(u16 TIM1_OCPolarity); +void TIM1_OC2NPolarityConfig(u16 TIM1_OCPolarity); +void TIM1_OC3PolarityConfig(u16 TIM1_OCPolarity); +void TIM1_OC3NPolarityConfig(u16 TIM1_OCPolarity); +void TIM1_OC4PolarityConfig(u16 TIM1_OCPolarity); +void TIM1_CCxCmd(u16 TIM1_Channel, FunctionalState Newstate); +void TIM1_CCxNCmd(u16 TIM1_Channel, FunctionalState Newstate); +void TIM1_SelectOCxM(u16 TIM1_Channel, u16 TIM1_OCMode); +void TIM1_SetAutoreload(u16 Autoreload); +void TIM1_SetCompare1(u16 Compare1); +void TIM1_SetCompare2(u16 Compare2); +void TIM1_SetCompare3(u16 Compare3); +void TIM1_SetCompare4(u16 Compare4); +void TIM1_SetIC1Prescaler(u16 TIM1_IC1Prescaler); +void TIM1_SetIC2Prescaler(u16 TIM1_IC2Prescaler); +void TIM1_SetIC3Prescaler(u16 TIM1_IC3Prescaler); +void TIM1_SetIC4Prescaler(u16 TIM1_IC4Prescaler); +void TIM1_SetClockDivision(u16 TIM1_CKD); +u16 TIM1_GetCapture1(void); +u16 TIM1_GetCapture2(void); +u16 TIM1_GetCapture3(void); +u16 TIM1_GetCapture4(void); +u16 TIM1_GetCounter(void); +u16 TIM1_GetPrescaler(void); +FlagStatus TIM1_GetFlagStatus(u16 TIM1_FLAG); +void TIM1_ClearFlag(u16 TIM1_Flag); +ITStatus TIM1_GetITStatus(u16 TIM1_IT); +void TIM1_ClearITPendingBit(u16 TIM1_IT); + +#endif /*__STM32F10x_TIM1_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_type.h b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_type.h new file mode 100644 index 000000000..d6e83a937 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_type.h @@ -0,0 +1,76 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_type.h +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file contains all the common data types used for the +* STM32F10x firmware library. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_TYPE_H +#define __STM32F10x_TYPE_H + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +typedef signed long s32; +typedef signed short s16; +typedef signed char s8; + +typedef volatile signed long vs32; +typedef volatile signed short vs16; +typedef volatile signed char vs8; + +typedef unsigned long u32; +typedef unsigned short u16; +typedef unsigned char u8; + +typedef unsigned long const uc32; /* Read Only */ +typedef unsigned short const uc16; /* Read Only */ +typedef unsigned char const uc8; /* Read Only */ + +typedef volatile unsigned long vu32; +typedef volatile unsigned short vu16; +typedef volatile unsigned char vu8; + +typedef volatile unsigned long const vuc32; /* Read Only */ +typedef volatile unsigned short const vuc16; /* Read Only */ +typedef volatile unsigned char const vuc8; /* Read Only */ + +typedef enum {FALSE = 0, TRUE = !FALSE} bool; + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) ((STATE == DISABLE) || (STATE == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +#define U8_MAX ((u8)255) +#define S8_MAX ((s8)127) +#define S8_MIN ((s8)-128) +#define U16_MAX ((u16)65535u) +#define S16_MAX ((s16)32767) +#define S16_MIN ((s16)-32768) +#define U32_MAX ((u32)4294967295uL) +#define S32_MAX ((s32)2147483647) +#define S32_MIN ((s32)2147483648uL) + +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +#endif /* __STM32F10x_TYPE_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_usart.h b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_usart.h new file mode 100644 index 000000000..e8c44aaab --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_usart.h @@ -0,0 +1,219 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_usart.h +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file contains all the functions prototypes for the +* USART firmware library. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_USART_H +#define __STM32F10x_USART_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* UART Init Structure definition */ +typedef struct +{ + u32 USART_BaudRate; + u16 USART_WordLength; + u16 USART_StopBits; + u16 USART_Parity; + u16 USART_HardwareFlowControl; + u16 USART_Mode; + u16 USART_Clock; + u16 USART_CPOL; + u16 USART_CPHA; + u16 USART_LastBit; +} USART_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* USART Word Length ---------------------------------------------------------*/ +#define USART_WordLength_8b ((u16)0x0000) +#define USART_WordLength_9b ((u16)0x1000) + +#define IS_USART_WORD_LENGTH(LENGTH) ((LENGTH == USART_WordLength_8b) || \ + (LENGTH == USART_WordLength_9b)) + +/* USART Stop Bits -----------------------------------------------------------*/ +#define USART_StopBits_1 ((u16)0x0000) +#define USART_StopBits_0_5 ((u16)0x1000) +#define USART_StopBits_2 ((u16)0x2000) +#define USART_StopBits_1_5 ((u16)0x3000) + +#define IS_USART_STOPBITS(STOPBITS) ((STOPBITS == USART_StopBits_1) || \ + (STOPBITS == USART_StopBits_0_5) || \ + (STOPBITS == USART_StopBits_2) || \ + (STOPBITS == USART_StopBits_1_5)) +/* USART Parity --------------------------------------------------------------*/ +#define USART_Parity_No ((u16)0x0000) +#define USART_Parity_Even ((u16)0x0400) +#define USART_Parity_Odd ((u16)0x0600) + +#define IS_USART_PARITY(PARITY) ((PARITY == USART_Parity_No) || \ + (PARITY == USART_Parity_Even) || \ + (PARITY == USART_Parity_Odd)) + +/* USART Hardware Flow Control -----------------------------------------------*/ +#define USART_HardwareFlowControl_None ((u16)0x0000) +#define USART_HardwareFlowControl_RTS ((u16)0x0100) +#define USART_HardwareFlowControl_CTS ((u16)0x0200) +#define USART_HardwareFlowControl_RTS_CTS ((u16)0x0300) + +#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\ + ((CONTROL == USART_HardwareFlowControl_None) || \ + (CONTROL == USART_HardwareFlowControl_RTS) || \ + (CONTROL == USART_HardwareFlowControl_CTS) || \ + (CONTROL == USART_HardwareFlowControl_RTS_CTS)) + +/* USART Mode ----------------------------------------------------------------*/ +#define USART_Mode_Rx ((u16)0x0004) +#define USART_Mode_Tx ((u16)0x0008) + +#define IS_USART_MODE(MODE) (((MODE & (u16)0xFFF3) == 0x00) && (MODE != (u16)0x00)) + +/* USART Clock ---------------------------------------------------------------*/ +#define USART_Clock_Disable ((u16)0x0000) +#define USART_Clock_Enable ((u16)0x0800) + +#define IS_USART_CLOCK(CLOCK) ((CLOCK == USART_Clock_Disable) || \ + (CLOCK == USART_Clock_Enable)) + +/* USART Clock Polarity ------------------------------------------------------*/ +#define USART_CPOL_Low ((u16)0x0000) +#define USART_CPOL_High ((u16)0x0400) + +#define IS_USART_CPOL(CPOL) ((CPOL == USART_CPOL_Low) || (CPOL == USART_CPOL_High)) + +/* USART Clock Phase ---------------------------------------------------------*/ +#define USART_CPHA_1Edge ((u16)0x0000) +#define USART_CPHA_2Edge ((u16)0x0200) +#define IS_USART_CPHA(CPHA) ((CPHA == USART_CPHA_1Edge) || (CPHA == USART_CPHA_2Edge)) + +/* USART Last Bit ------------------------------------------------------------*/ +#define USART_LastBit_Disable ((u16)0x0000) +#define USART_LastBit_Enable ((u16)0x0100) + +#define IS_USART_LASTBIT(LASTBIT) ((LASTBIT == USART_LastBit_Disable) || \ + (LASTBIT == USART_LastBit_Enable)) + +/* USART Interrupt definition ------------------------------------------------*/ +#define USART_IT_PE ((u16)0x0028) +#define USART_IT_TXE ((u16)0x0727) +#define USART_IT_TC ((u16)0x0626) +#define USART_IT_RXNE ((u16)0x0525) +#define USART_IT_IDLE ((u16)0x0424) +#define USART_IT_LBD ((u16)0x0846) +#define USART_IT_CTS ((u16)0x096A) +#define USART_IT_ERR ((u16)0x0060) +#define USART_IT_ORE ((u16)0x0360) +#define USART_IT_NE ((u16)0x0260) +#define USART_IT_FE ((u16)0x0160) + +#define IS_USART_CONFIG_IT(IT) ((IT == USART_IT_PE) || (IT == USART_IT_TXE) || \ + (IT == USART_IT_TC) || (IT == USART_IT_RXNE) || \ + (IT == USART_IT_IDLE) || (IT == USART_IT_LBD) || \ + (IT == USART_IT_CTS) || (IT == USART_IT_ERR)) + +#define IS_USART_IT(IT) ((IT == USART_IT_PE) || (IT == USART_IT_TXE) || \ + (IT == USART_IT_TC) || (IT == USART_IT_RXNE) || \ + (IT == USART_IT_IDLE) || (IT == USART_IT_LBD) || \ + (IT == USART_IT_CTS) || (IT == USART_IT_ORE) || \ + (IT == USART_IT_NE) || (IT == USART_IT_FE)) + +/* USART DMA Requests --------------------------------------------------------*/ +#define USART_DMAReq_Tx ((u16)0x0080) +#define USART_DMAReq_Rx ((u16)0x0040) + +#define IS_USART_DMAREQ(DMAREQ) (((DMAREQ & (u16)0xFF3F) == 0x00) && (DMAREQ != (u16)0x00)) + +/* USART WakeUp methods ------------------------------------------------------*/ +#define USART_WakeUp_IdleLine ((u16)0x0000) +#define USART_WakeUp_AddressMark ((u16)0x0800) + +#define IS_USART_WAKEUP(WAKEUP) ((WAKEUP == USART_WakeUp_IdleLine) || \ + (WAKEUP == USART_WakeUp_AddressMark)) + +/* USART LIN Break Detection Length ------------------------------------------*/ +#define USART_LINBreakDetectLength_10b ((u16)0x0000) +#define USART_LINBreakDetectLength_11b ((u16)0x0020) + +#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \ + ((LENGTH == USART_LINBreakDetectLength_10b) || \ + (LENGTH == USART_LINBreakDetectLength_11b)) + +/* USART IrDA Low Power ------------------------------------------------------*/ +#define USART_IrDAMode_LowPower ((u16)0x0004) +#define USART_IrDAMode_Normal ((u16)0x0000) + +#define IS_USART_IRDA_MODE(MODE) ((MODE == USART_IrDAMode_LowPower) || \ + (MODE == USART_IrDAMode_Normal)) + +/* USART Flags ---------------------------------------------------------------*/ +#define USART_FLAG_CTS ((u16)0x0200) +#define USART_FLAG_LBD ((u16)0x0100) +#define USART_FLAG_TXE ((u16)0x0080) +#define USART_FLAG_TC ((u16)0x0040) +#define USART_FLAG_RXNE ((u16)0x0020) +#define USART_FLAG_IDLE ((u16)0x0010) +#define USART_FLAG_ORE ((u16)0x0008) +#define USART_FLAG_NE ((u16)0x0004) +#define USART_FLAG_FE ((u16)0x0002) +#define USART_FLAG_PE ((u16)0x0001) + +#define IS_USART_FLAG(FLAG) ((FLAG == USART_FLAG_PE) || (FLAG == USART_FLAG_TXE) || \ + (FLAG == USART_FLAG_TC) || (FLAG == USART_FLAG_RXNE) || \ + (FLAG == USART_FLAG_IDLE) || (FLAG == USART_FLAG_LBD) || \ + (FLAG == USART_FLAG_CTS) || (FLAG == USART_FLAG_ORE) || \ + (FLAG == USART_FLAG_NE) || (FLAG == USART_FLAG_FE)) + +#define IS_USART_CLEAR_FLAG(FLAG) (((FLAG & (u16)0xFC00) == 0x00) && (FLAG != (u16)0x00)) + +#define IS_USART_ADDRESS(ADDRESS) (ADDRESS <= 0xF) +#define IS_USART_DATA(DATA) (DATA <= 0x1FF) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void USART_DeInit(USART_TypeDef* USARTx); +void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct); +void USART_StructInit(USART_InitTypeDef* USART_InitStruct); +void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_ITConfig(USART_TypeDef* USARTx, u16 USART_IT, FunctionalState NewState); +void USART_DMACmd(USART_TypeDef* USARTx, u16 USART_DMAReq, FunctionalState NewState); +void USART_SetAddress(USART_TypeDef* USARTx, u8 USART_Address); +void USART_WakeUpConfig(USART_TypeDef* USARTx, u16 USART_WakeUp); +void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, u16 USART_LINBreakDetectLength); +void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SendData(USART_TypeDef* USARTx, u16 Data); +u16 USART_ReceiveData(USART_TypeDef* USARTx); +void USART_SendBreak(USART_TypeDef* USARTx); +void USART_SetGuardTime(USART_TypeDef* USARTx, u8 USART_GuardTime); +void USART_SetPrescaler(USART_TypeDef* USARTx, u8 USART_Prescaler); +void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_IrDAConfig(USART_TypeDef* USARTx, u16 USART_IrDAMode); +void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); +FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, u16 USART_FLAG); +void USART_ClearFlag(USART_TypeDef* USARTx, u16 USART_FLAG); +ITStatus USART_GetITStatus(USART_TypeDef* USARTx, u16 USART_IT); +void USART_ClearITPendingBit(USART_TypeDef* USARTx, u16 USART_IT); + +#endif /* __STM32F10x_USART_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_wwdg.h b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_wwdg.h new file mode 100644 index 000000000..2230b5823 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/inc/stm32f10x_wwdg.h @@ -0,0 +1,58 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_wwdg.h +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file contains all the functions prototypes for the +* WWDG firmware library. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_WWDG_H +#define __STM32F10x_WWDG_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* WWDG Prescaler */ +#define WWDG_Prescaler_1 ((u32)0x00000000) +#define WWDG_Prescaler_2 ((u32)0x00000080) +#define WWDG_Prescaler_4 ((u32)0x00000100) +#define WWDG_Prescaler_8 ((u32)0x00000180) + +#define IS_WWDG_PRESCALER(PRESCALER) ((PRESCALER == WWDG_Prescaler_1) || \ + (PRESCALER == WWDG_Prescaler_2) || \ + (PRESCALER == WWDG_Prescaler_4) || \ + (PRESCALER == WWDG_Prescaler_8)) + +#define IS_WWDG_WINDOW_VALUE(VALUE) (VALUE <= 0x7F) + +#define IS_WWDG_COUNTER(COUNTER) ((COUNTER >= 0x40) && (COUNTER <= 0x7F)) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void WWDG_DeInit(void); +void WWDG_SetPrescaler(u32 WWDG_Prescaler); +void WWDG_SetWindowValue(u8 WindowValue); +void WWDG_EnableIT(void); +void WWDG_SetCounter(u8 Counter); +void WWDG_Enable(u8 Counter); +FlagStatus WWDG_GetFlagStatus(void); +void WWDG_ClearFlag(void); + +#endif /* __STM32F10x_WWDG_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/cortexm3_macro.s b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/cortexm3_macro.s new file mode 100644 index 000000000..cb20961e9 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/cortexm3_macro.s @@ -0,0 +1,278 @@ +;******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +;* File Name : cortexm3_macro.s +;* Author : MCD Application Team +;* Date First Issued : 02/19/2007 +;* Description : Instruction wrappers for special Cortex-M3 instructions. +;******************************************************************************* +; History: +; 04/02/2007: V0.2 +; 02/19/2007: V0.1 +;******************************************************************************* +; THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +; CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************* + + SECTION .text:CODE(2) + + ; Exported functions + EXPORT __WFI + EXPORT __WFE + EXPORT __SEV + EXPORT __ISB + EXPORT __DSB + EXPORT __DMB + EXPORT __SVC + EXPORT __MRS_CONTROL + EXPORT __MSR_CONTROL + EXPORT __MRS_PSP + EXPORT __MSR_PSP + EXPORT __MRS_MSP + EXPORT __MSR_MSP + EXPORT __SETPRIMASK + EXPORT __RESETPRIMASK + EXPORT __SETFAULTMASK + EXPORT __RESETFAULTMASK + EXPORT __BASEPRICONFIG + EXPORT __GetBASEPRI + EXPORT __REV_HalfWord + EXPORT __REV_Word + +;******************************************************************************* +; Function Name : __WFI +; Description : Assembler function for the WFI instruction. +; Input : None +; Return : None +;******************************************************************************* +__WFI + + WFI + BX r14 + +;******************************************************************************* +; Function Name : __WFE +; Description : Assembler function for the WFE instruction. +; Input : None +; Return : None +;******************************************************************************* +__WFE + + WFE + BX r14 + +;******************************************************************************* +; Function Name : __SEV +; Description : Assembler function for the SEV instruction. +; Input : None +; Return : None +;******************************************************************************* +__SEV + + SEV + BX r14 + +;******************************************************************************* +; Function Name : __ISB +; Description : Assembler function for the ISB instruction. +; Input : None +; Return : None +;******************************************************************************* +__ISB + + ISB + BX r14 + +;******************************************************************************* +; Function Name : __DSB +; Description : Assembler function for the DSB instruction. +; Input : None +; Return : None +;******************************************************************************* +__DSB + + DSB + BX r14 + +;******************************************************************************* +; Function Name : __DMB +; Description : Assembler function for the DMB instruction. +; Input : None +; Return : None +;******************************************************************************* +__DMB + + DMB + BX r14 + +;******************************************************************************* +; Function Name : __SVC +; Description : Assembler function for the SVC instruction. +; Input : None +; Return : None +;******************************************************************************* +__SVC + + SVC 0x01 + BX r14 + +;******************************************************************************* +; Function Name : __MRS_CONTROL +; Description : Assembler function for the MRS instruction. +; Input : None +; Return : - r0 : Cortex-M3 CONTROL register value. +;******************************************************************************* +__MRS_CONTROL + + MRS r0, CONTROL + BX r14 + +;******************************************************************************* +; Function Name : __MSR_CONTROL +; Description : Assembler function for the MSR instruction. +; Input : - r0 : Cortex-M3 CONTROL register new value. +; Return : None +;******************************************************************************* +__MSR_CONTROL + + MSR CONTROL, r0 + ISB + BX r14 + +;******************************************************************************* +; Function Name : __MRS_PSP +; Description : Assembler function for the MRS instruction. +; Input : None +; Return : - r0 : Process Stack value. +;******************************************************************************* +__MRS_PSP + + MRS r0, PSP + BX r14 + +;******************************************************************************* +; Function Name : __MSR_PSP +; Description : Assembler function for the MSR instruction. +; Input : - r0 : Process Stack new value. +; Return : None +;******************************************************************************* +__MSR_PSP + + MSR PSP, r0 ; set Process Stack value + BX r14 + +;******************************************************************************* +; Function Name : __MRS_MSP +; Description : Assembler function for the MRS instruction. +; Input : None +; Return : - r0 : Main Stack value. +;******************************************************************************* +__MRS_MSP + + MRS r0, MSP + BX r14 + +;******************************************************************************* +; Function Name : __MSR_MSP +; Description : Assembler function for the MSR instruction. +; Input : - r0 : Main Stack new value. +; Return : None +;******************************************************************************* +__MSR_MSP + + MSR MSP, r0 ; set Main Stack value + BX r14 + +;******************************************************************************* +; Function Name : __SETPRIMASK +; Description : Assembler function to set the PRIMASK. +; Input : None +; Return : None +;******************************************************************************* +__SETPRIMASK + + CPSID i + BX r14 + +;******************************************************************************* +; Function Name : __RESETPRIMASK +; Description : Assembler function to reset the PRIMASK. +; Input : None +; Return : None +;******************************************************************************* +__RESETPRIMASK + + CPSIE i + BX r14 + +;******************************************************************************* +; Function Name : __SETFAULTMASK +; Description : Assembler function to set the FAULTMASK. +; Input : None +; Return : None +;******************************************************************************* +__SETFAULTMASK + + CPSID f + BX r14 + +;******************************************************************************* +; Function Name : __RESETFAULTMASK +; Description : Assembler function to reset the FAULTMASK. +; Input : None +; Return : None +;******************************************************************************* +__RESETFAULTMASK + + CPSIE f + BX r14 + +;******************************************************************************* +; Function Name : __BASEPRICONFIG +; Description : Assembler function to set the Base Priority. +; Input : - r0 : Base Priority new value +; Return : None +;******************************************************************************* +__BASEPRICONFIG + + MSR BASEPRI, r0 + BX r14 + +;******************************************************************************* +; Function Name : __GetBASEPRI +; Description : Assembler function to get the Base Priority value. +; Input : None +; Return : - r0 : Base Priority value +;******************************************************************************* +__GetBASEPRI + + MRS r0, BASEPRI_MAX + BX r14 + +;******************************************************************************* +; Function Name : __REV_HalfWord +; Description : Reverses the byte order in HalfWord(16-bit) input variable. +; Input : - r0 : specifies the input variable +; Return : - r0 : holds tve variable value after byte reversing. +;******************************************************************************* +__REV_HalfWord + + REV16 r0, r0 + BX r14 + +;******************************************************************************* +; Function Name : __REV_Word +; Description : Reverses the byte order in Word(32-bit) input variable. +; Input : - r0 : specifies the input variable +; Return : - r0 : holds tve variable value after byte reversing. +;******************************************************************************* +__REV_Word + + REV r0, r0 + BX r14 + + END + +;******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE***** diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/lcd.c b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/lcd.c new file mode 100644 index 000000000..4319782c7 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/lcd.c @@ -0,0 +1,1305 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : lcd.c +* Author : MCD Application Team +* Date First Issued : mm/dd/yyyy +* Description : This file includes the LCD driver for AM-240320LTNQW00H +* liquid Crystal Display Module of STM32F10x-EVAL. +******************************************************************************** +* History: +* mm/dd/yyyy +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_type.h" +#include "lcd.h" +#include "spi_flash.h" + +#include "FreeRTOS.h" +#include "Task.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + /* ASCII Table: each character is 16 column (16dots large) + and 24 raw (24 dots high) */ + const uc16 ASCII_Table[] = + { + /* Space ' ' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* '!' */ + 0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0000, 0x0000, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* '"' */ + 0x0000, 0x0000, 0x00CC, 0x00CC, 0x00CC, 0x00CC, 0x00CC, 0x00CC, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* '#' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0C60, 0x0C60, + 0x0C60, 0x0630, 0x0630, 0x1FFE, 0x1FFE, 0x0630, 0x0738, 0x0318, + 0x1FFE, 0x1FFE, 0x0318, 0x0318, 0x018C, 0x018C, 0x018C, 0x0000, + /* '$' */ + 0x0000, 0x0080, 0x03E0, 0x0FF8, 0x0E9C, 0x1C8C, 0x188C, 0x008C, + 0x0098, 0x01F8, 0x07E0, 0x0E80, 0x1C80, 0x188C, 0x188C, 0x189C, + 0x0CB8, 0x0FF0, 0x03E0, 0x0080, 0x0080, 0x0000, 0x0000, 0x0000, + /* '%' */ + 0x0000, 0x0000, 0x0000, 0x180E, 0x0C1B, 0x0C11, 0x0611, 0x0611, + 0x0311, 0x0311, 0x019B, 0x018E, 0x38C0, 0x6CC0, 0x4460, 0x4460, + 0x4430, 0x4430, 0x4418, 0x6C18, 0x380C, 0x0000, 0x0000, 0x0000, + /* '&' */ + 0x0000, 0x01E0, 0x03F0, 0x0738, 0x0618, 0x0618, 0x0330, 0x01F0, + 0x00F0, 0x00F8, 0x319C, 0x330E, 0x1E06, 0x1C06, 0x1C06, 0x3F06, + 0x73FC, 0x21F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* ''' */ + 0x0000, 0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* '(' */ + 0x0000, 0x0200, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x0060, 0x0060, + 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, + 0x0060, 0x0060, 0x00C0, 0x00C0, 0x0180, 0x0300, 0x0200, 0x0000, + /* ')' */ + 0x0000, 0x0020, 0x0060, 0x00C0, 0x0180, 0x0180, 0x0300, 0x0300, + 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, + 0x0300, 0x0300, 0x0180, 0x0180, 0x00C0, 0x0060, 0x0020, 0x0000, + /* '*' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0, + 0x06D8, 0x07F8, 0x01E0, 0x0330, 0x0738, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* '+' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x3FFC, 0x3FFC, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* ',' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0180, 0x0180, 0x0100, 0x0100, 0x0080, 0x0000, 0x0000, + /* '-' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x07E0, 0x07E0, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* '.' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* '/' */ + 0x0000, 0x0C00, 0x0C00, 0x0600, 0x0600, 0x0600, 0x0300, 0x0300, + 0x0300, 0x0380, 0x0180, 0x0180, 0x0180, 0x00C0, 0x00C0, 0x00C0, + 0x0060, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* '0' */ + 0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C18, 0x180C, 0x180C, 0x180C, + 0x180C, 0x180C, 0x180C, 0x180C, 0x180C, 0x180C, 0x0C18, 0x0E38, + 0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* '1' */ + 0x0000, 0x0100, 0x0180, 0x01C0, 0x01F0, 0x0198, 0x0188, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* '2' */ + 0x0000, 0x03E0, 0x0FF8, 0x0C18, 0x180C, 0x180C, 0x1800, 0x1800, + 0x0C00, 0x0600, 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018, + 0x1FFC, 0x1FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* '3' */ + 0x0000, 0x01E0, 0x07F8, 0x0E18, 0x0C0C, 0x0C0C, 0x0C00, 0x0600, + 0x03C0, 0x07C0, 0x0C00, 0x1800, 0x1800, 0x180C, 0x180C, 0x0C18, + 0x07F8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* '4' */ + 0x0000, 0x0C00, 0x0E00, 0x0F00, 0x0F00, 0x0D80, 0x0CC0, 0x0C60, + 0x0C60, 0x0C30, 0x0C18, 0x0C0C, 0x3FFC, 0x3FFC, 0x0C00, 0x0C00, + 0x0C00, 0x0C00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* '5' */ + 0x0000, 0x0FF8, 0x0FF8, 0x0018, 0x0018, 0x000C, 0x03EC, 0x07FC, + 0x0E1C, 0x1C00, 0x1800, 0x1800, 0x1800, 0x180C, 0x0C1C, 0x0E18, + 0x07F8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* '6' */ + 0x0000, 0x07C0, 0x0FF0, 0x1C38, 0x1818, 0x0018, 0x000C, 0x03CC, + 0x0FEC, 0x0E3C, 0x1C1C, 0x180C, 0x180C, 0x180C, 0x1C18, 0x0E38, + 0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* '7' */ + 0x0000, 0x1FFC, 0x1FFC, 0x0C00, 0x0600, 0x0600, 0x0300, 0x0380, + 0x0180, 0x01C0, 0x00C0, 0x00E0, 0x0060, 0x0060, 0x0070, 0x0030, + 0x0030, 0x0030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* '8' */ + 0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C18, 0x0C18, 0x0C18, 0x0638, + 0x07F0, 0x07F0, 0x0C18, 0x180C, 0x180C, 0x180C, 0x180C, 0x0C38, + 0x0FF8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* '9' */ + 0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C1C, 0x180C, 0x180C, 0x180C, + 0x1C1C, 0x1E38, 0x1BF8, 0x19E0, 0x1800, 0x0C00, 0x0C00, 0x0E1C, + 0x07F8, 0x01F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* ':' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* ';' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0180, 0x0180, 0x0100, 0x0100, 0x0080, 0x0000, 0x0000, 0x0000, + /* '<' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x1000, 0x1C00, 0x0F80, 0x03E0, 0x00F8, 0x0018, 0x00F8, 0x03E0, + 0x0F80, 0x1C00, 0x1000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* '=' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x1FF8, 0x0000, 0x0000, 0x0000, 0x1FF8, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* '>' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0008, 0x0038, 0x01F0, 0x07C0, 0x1F00, 0x1800, 0x1F00, 0x07C0, + 0x01F0, 0x0038, 0x0008, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* '?' */ + 0x0000, 0x03E0, 0x0FF8, 0x0C18, 0x180C, 0x180C, 0x1800, 0x0C00, + 0x0600, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x00C0, 0x0000, 0x0000, + 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* '@' */ + 0x0000, 0x0000, 0x07E0, 0x1818, 0x2004, 0x29C2, 0x4A22, 0x4411, + 0x4409, 0x4409, 0x4409, 0x2209, 0x1311, 0x0CE2, 0x4002, 0x2004, + 0x1818, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'A' */ + 0x0000, 0x0380, 0x0380, 0x06C0, 0x06C0, 0x06C0, 0x0C60, 0x0C60, + 0x1830, 0x1830, 0x1830, 0x3FF8, 0x3FF8, 0x701C, 0x600C, 0x600C, + 0xC006, 0xC006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'B' */ + 0x0000, 0x03FC, 0x0FFC, 0x0C0C, 0x180C, 0x180C, 0x180C, 0x0C0C, + 0x07FC, 0x0FFC, 0x180C, 0x300C, 0x300C, 0x300C, 0x300C, 0x180C, + 0x1FFC, 0x07FC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'C' */ + 0x0000, 0x07C0, 0x1FF0, 0x3838, 0x301C, 0x700C, 0x6006, 0x0006, + 0x0006, 0x0006, 0x0006, 0x0006, 0x0006, 0x6006, 0x700C, 0x301C, + 0x1FF0, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'D' */ + 0x0000, 0x03FE, 0x0FFE, 0x0E06, 0x1806, 0x1806, 0x3006, 0x3006, + 0x3006, 0x3006, 0x3006, 0x3006, 0x3006, 0x1806, 0x1806, 0x0E06, + 0x0FFE, 0x03FE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'E' */ + 0x0000, 0x3FFC, 0x3FFC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, + 0x1FFC, 0x1FFC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, + 0x3FFC, 0x3FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'F' */ + 0x0000, 0x3FF8, 0x3FF8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, + 0x1FF8, 0x1FF8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, + 0x0018, 0x0018, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'G' */ + 0x0000, 0x0FE0, 0x3FF8, 0x783C, 0x600E, 0xE006, 0xC007, 0x0003, + 0x0003, 0xFE03, 0xFE03, 0xC003, 0xC007, 0xC006, 0xC00E, 0xF03C, + 0x3FF8, 0x0FE0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'H' */ + 0x0000, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, + 0x3FFC, 0x3FFC, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, + 0x300C, 0x300C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'I' */ + 0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'J' */ + 0x0000, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, + 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0618, 0x0618, 0x0738, + 0x03F0, 0x01E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'K' */ + 0x0000, 0x3006, 0x1806, 0x0C06, 0x0606, 0x0306, 0x0186, 0x00C6, + 0x0066, 0x0076, 0x00DE, 0x018E, 0x0306, 0x0606, 0x0C06, 0x1806, + 0x3006, 0x6006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'L' */ + 0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, + 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, + 0x1FF8, 0x1FF8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'M' */ + 0x0000, 0xE00E, 0xF01E, 0xF01E, 0xF01E, 0xD836, 0xD836, 0xD836, + 0xD836, 0xCC66, 0xCC66, 0xCC66, 0xC6C6, 0xC6C6, 0xC6C6, 0xC6C6, + 0xC386, 0xC386, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'N' */ + 0x0000, 0x300C, 0x301C, 0x303C, 0x303C, 0x306C, 0x306C, 0x30CC, + 0x30CC, 0x318C, 0x330C, 0x330C, 0x360C, 0x360C, 0x3C0C, 0x3C0C, + 0x380C, 0x300C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'O' */ + 0x0000, 0x07E0, 0x1FF8, 0x381C, 0x700E, 0x6006, 0xC003, 0xC003, + 0xC003, 0xC003, 0xC003, 0xC003, 0xC003, 0x6006, 0x700E, 0x381C, + 0x1FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'P' */ + 0x0000, 0x0FFC, 0x1FFC, 0x380C, 0x300C, 0x300C, 0x300C, 0x300C, + 0x180C, 0x1FFC, 0x07FC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, + 0x000C, 0x000C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'Q' */ + 0x0000, 0x07E0, 0x1FF8, 0x381C, 0x700E, 0x6006, 0xE003, 0xC003, + 0xC003, 0xC003, 0xC003, 0xC003, 0xE007, 0x6306, 0x3F0E, 0x3C1C, + 0x3FF8, 0xF7E0, 0xC000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'R' */ + 0x0000, 0x0FFE, 0x1FFE, 0x3806, 0x3006, 0x3006, 0x3006, 0x3806, + 0x1FFE, 0x07FE, 0x0306, 0x0606, 0x0C06, 0x1806, 0x1806, 0x3006, + 0x3006, 0x6006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'S' */ + 0x0000, 0x03E0, 0x0FF8, 0x0C1C, 0x180C, 0x180C, 0x000C, 0x001C, + 0x03F8, 0x0FE0, 0x1E00, 0x3800, 0x3006, 0x3006, 0x300E, 0x1C1C, + 0x0FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'T' */ + 0x0000, 0x7FFE, 0x7FFE, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'U' */ + 0x0000, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, + 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x1818, + 0x1FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'V' */ + 0x0000, 0x6003, 0x3006, 0x3006, 0x3006, 0x180C, 0x180C, 0x180C, + 0x0C18, 0x0C18, 0x0E38, 0x0630, 0x0630, 0x0770, 0x0360, 0x0360, + 0x01C0, 0x01C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'W' */ + 0x0000, 0x6003, 0x61C3, 0x61C3, 0x61C3, 0x3366, 0x3366, 0x3366, + 0x3366, 0x3366, 0x3366, 0x1B6C, 0x1B6C, 0x1B6C, 0x1A2C, 0x1E3C, + 0x0E38, 0x0E38, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'X' */ + 0x0000, 0xE00F, 0x700C, 0x3018, 0x1830, 0x0C70, 0x0E60, 0x07C0, + 0x0380, 0x0380, 0x03C0, 0x06E0, 0x0C70, 0x1C30, 0x1818, 0x300C, + 0x600E, 0xE007, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'Y' */ + 0x0000, 0xC003, 0x6006, 0x300C, 0x381C, 0x1838, 0x0C30, 0x0660, + 0x07E0, 0x03C0, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'Z' */ + 0x0000, 0x7FFC, 0x7FFC, 0x6000, 0x3000, 0x1800, 0x0C00, 0x0600, + 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018, 0x000C, 0x0006, + 0x7FFE, 0x7FFE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* '[' */ + 0x0000, 0x03E0, 0x03E0, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, + 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, + 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x03E0, 0x03E0, 0x0000, + /* '\' */ + 0x0000, 0x0030, 0x0030, 0x0060, 0x0060, 0x0060, 0x00C0, 0x00C0, + 0x00C0, 0x01C0, 0x0180, 0x0180, 0x0180, 0x0300, 0x0300, 0x0300, + 0x0600, 0x0600, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* ']' */ + 0x0000, 0x03E0, 0x03E0, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, + 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, + 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x03E0, 0x03E0, 0x0000, + /* '^' */ + 0x0000, 0x0000, 0x01C0, 0x01C0, 0x0360, 0x0360, 0x0360, 0x0630, + 0x0630, 0x0C18, 0x0C18, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* '_' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* ''' */ + 0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'a' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03F0, 0x07F8, + 0x0C1C, 0x0C0C, 0x0F00, 0x0FF0, 0x0CF8, 0x0C0C, 0x0C0C, 0x0F1C, + 0x0FF8, 0x18F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'b' */ + 0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x03D8, 0x0FF8, + 0x0C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C38, + 0x0FF8, 0x03D8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'c' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x07F0, + 0x0E30, 0x0C18, 0x0018, 0x0018, 0x0018, 0x0018, 0x0C18, 0x0E30, + 0x07F0, 0x03C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'd' */ + 0x0000, 0x1800, 0x1800, 0x1800, 0x1800, 0x1800, 0x1BC0, 0x1FF0, + 0x1C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C30, + 0x1FF0, 0x1BC0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'e' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x0FF0, + 0x0C30, 0x1818, 0x1FF8, 0x1FF8, 0x0018, 0x0018, 0x1838, 0x1C30, + 0x0FF0, 0x07C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'f' */ + 0x0000, 0x0F80, 0x0FC0, 0x00C0, 0x00C0, 0x00C0, 0x07F0, 0x07F0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'g' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0DE0, 0x0FF8, + 0x0E18, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0E18, + 0x0FF8, 0x0DE0, 0x0C00, 0x0C0C, 0x061C, 0x07F8, 0x01F0, 0x0000, + /* 'h' */ + 0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x07D8, 0x0FF8, + 0x1C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, + 0x1818, 0x1818, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'i' */ + 0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'j' */ + 0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00F8, 0x0078, 0x0000, + /* 'k' */ + 0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x0C0C, 0x060C, + 0x030C, 0x018C, 0x00CC, 0x006C, 0x00FC, 0x019C, 0x038C, 0x030C, + 0x060C, 0x0C0C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'l' */ + 0x0000, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'm' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3C7C, 0x7EFF, + 0xE3C7, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, + 0xC183, 0xC183, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'n' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0798, 0x0FF8, + 0x1C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, + 0x1818, 0x1818, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'o' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x0FF0, + 0x0C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C30, + 0x0FF0, 0x03C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'p' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03D8, 0x0FF8, + 0x0C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C38, + 0x0FF8, 0x03D8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0000, + /* 'q' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1BC0, 0x1FF0, + 0x1C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C30, + 0x1FF0, 0x1BC0, 0x1800, 0x1800, 0x1800, 0x1800, 0x1800, 0x0000, + /* 'r' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x07B0, 0x03F0, + 0x0070, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, + 0x0030, 0x0030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 's' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03E0, 0x03F0, + 0x0E38, 0x0C18, 0x0038, 0x03F0, 0x07C0, 0x0C00, 0x0C18, 0x0E38, + 0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 't' */ + 0x0000, 0x0000, 0x0080, 0x00C0, 0x00C0, 0x00C0, 0x07F0, 0x07F0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x07C0, 0x0780, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'u' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1818, 0x1818, + 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C38, + 0x1FF0, 0x19E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'v' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x180C, 0x0C18, + 0x0C18, 0x0C18, 0x0630, 0x0630, 0x0630, 0x0360, 0x0360, 0x0360, + 0x01C0, 0x01C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'w' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x41C1, 0x41C1, + 0x61C3, 0x6363, 0x6363, 0x6363, 0x3636, 0x3636, 0x3636, 0x1C1C, + 0x1C1C, 0x1C1C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'x' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x381C, 0x1C38, + 0x0C30, 0x0660, 0x0360, 0x0360, 0x0360, 0x0360, 0x0660, 0x0C30, + 0x1C38, 0x381C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* 'y' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3018, 0x1830, + 0x1830, 0x1870, 0x0C60, 0x0C60, 0x0CE0, 0x06C0, 0x06C0, 0x0380, + 0x0380, 0x0380, 0x0180, 0x0180, 0x01C0, 0x00F0, 0x0070, 0x0000, + /* 'z' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1FFC, 0x1FFC, + 0x0C00, 0x0600, 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018, + 0x1FFC, 0x1FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + /* '{' */ + 0x0000, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, + 0x00C0, 0x0060, 0x0060, 0x0030, 0x0060, 0x0040, 0x00C0, 0x00C0, + 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x0180, 0x0300, 0x0000, 0x0000, + /* '|' */ + 0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0000, + /* '}' */ + 0x0000, 0x0060, 0x00C0, 0x01C0, 0x0180, 0x0180, 0x0180, 0x0180, + 0x0180, 0x0300, 0x0300, 0x0600, 0x0300, 0x0100, 0x0180, 0x0180, + 0x0180, 0x0180, 0x0180, 0x0180, 0x00C0, 0x0060, 0x0000, 0x0000, + /* '~' */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x10F0, 0x1FF8, 0x0F08, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + }; +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + /* Global variables to set the written text color */ +static vu16 TextColor = 0x0000, BackColor = 0xFFFF; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +static u32 StrLength(u8 *Str); + +/******************************************************************************* +* Function Name : LCD_Init +* Description : Initializes LCD. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void LCD_Init(void) +{ +/* Configure the LCD Control pins --------------------------------------------*/ + LCD_CtrlLinesConfig(); + +/* Configure the SPI2 interface ----------------------------------------------*/ + LCD_SPIConfig(); + +/* Enable the LCD Oscillator -------------------------------------------------*/ + LCD_WriteReg(R1, 0x10); + LCD_WriteReg(R0, 0xA0); + LCD_WriteReg(R3, 0x01); + vTaskDelay( 10 / portTICK_RATE_MS ); /* Delay 10 ms */ + LCD_WriteReg(R3, 0x00); + LCD_WriteReg(R43, 0x04); + + LCD_WriteReg(R40, 0x18); + LCD_WriteReg(R26, 0x05); + LCD_WriteReg(R37, 0x05); + LCD_WriteReg(R25, 0x00); + +/* LCD Power On --------------------------------------------------------------*/ + LCD_WriteReg(R28, 0x73); + LCD_WriteReg(R36, 0x74); + LCD_WriteReg(R30, 0x01); + LCD_WriteReg(R24, 0xC1); + vTaskDelay( 10 / portTICK_RATE_MS ); /* Delay 10 ms */ + LCD_WriteReg(R24, 0xE1); + LCD_WriteReg(R24, 0xF1); + vTaskDelay( 60 / portTICK_RATE_MS ); /* Delay 60 ms */ + LCD_WriteReg(R24, 0xF5); + vTaskDelay( 60 / portTICK_RATE_MS ); /* Delay 60 ms */ + LCD_WriteReg(R27, 0x09); + vTaskDelay( 10 / portTICK_RATE_MS ); /* Delay 10 ms */ + LCD_WriteReg(R31, 0x11); + LCD_WriteReg(R32, 0x0E); + LCD_WriteReg(R30, 0x81); + vTaskDelay( 10 / portTICK_RATE_MS ); /* Delay 10 ms */ + +/* Chip Set ------------------------------------------------------------------*/ + LCD_WriteReg(R157, 0x00); + LCD_WriteReg(R192, 0x00); + + LCD_WriteReg(R14, 0x00); + LCD_WriteReg(R15, 0x00); + LCD_WriteReg(R16, 0x00); + LCD_WriteReg(R17, 0x00); + LCD_WriteReg(R18, 0x00); + LCD_WriteReg(R19, 0x00); + LCD_WriteReg(R20, 0x00); + LCD_WriteReg(R21, 0x00); + LCD_WriteReg(R22, 0x00); + LCD_WriteReg(R23, 0x00); + + LCD_WriteReg(R52, 0x01); + LCD_WriteReg(R53, 0x00); + + LCD_WriteReg(R75, 0x00); + LCD_WriteReg(R76, 0x00); + LCD_WriteReg(R78, 0x00); + LCD_WriteReg(R79, 0x00); + LCD_WriteReg(R80, 0x00); + + LCD_WriteReg(R60, 0x00); + LCD_WriteReg(R61, 0x00); + LCD_WriteReg(R62, 0x01); + LCD_WriteReg(R63, 0x3F); + LCD_WriteReg(R64, 0x02); + LCD_WriteReg(R65, 0x02); + LCD_WriteReg(R66, 0x00); + LCD_WriteReg(R67, 0x00); + LCD_WriteReg(R68, 0x00); + LCD_WriteReg(R69, 0x00); + LCD_WriteReg(R70, 0xEF); + LCD_WriteReg(R71, 0x00); + LCD_WriteReg(R72, 0x00); + LCD_WriteReg(R73, 0x01); + LCD_WriteReg(R74, 0x3F); + + LCD_WriteReg(R29, 0x08); /* R29:Gate scan direction setting */ + + LCD_WriteReg(R134, 0x00); + LCD_WriteReg(R135, 0x30); + LCD_WriteReg(R136, 0x02); + LCD_WriteReg(R137, 0x05); + + LCD_WriteReg(R141, 0x01); /* R141:Register set-up mode for one line clock */ + LCD_WriteReg(R139, 0x20); /* R139:One line SYSCLK number in one-line */ + LCD_WriteReg(R51, 0x01); /* R51:N line inversion setting */ + LCD_WriteReg(R55, 0x01); /* R55:Scanning method setting */ + LCD_WriteReg(R118, 0x00); + +/* Gamma Set -----------------------------------------------------------------*/ + LCD_WriteReg(R143, 0x10); + LCD_WriteReg(R144, 0x67); + LCD_WriteReg(R145, 0x07); + LCD_WriteReg(R146, 0x65); + LCD_WriteReg(R147, 0x07); + LCD_WriteReg(R148, 0x01); + LCD_WriteReg(R149, 0x76); + LCD_WriteReg(R150, 0x56); + LCD_WriteReg(R151, 0x00); + LCD_WriteReg(R152, 0x06); + LCD_WriteReg(R153, 0x03); + LCD_WriteReg(R154, 0x00); + +/* Display On ----------------------------------------------------------------*/ + LCD_WriteReg(R1, 0x50); + LCD_WriteReg(R5, 0x04); + + LCD_WriteReg(R0, 0x80); + LCD_WriteReg(R59, 0x01); + vTaskDelay( 40 / portTICK_RATE_MS ); /* Delay 40 ms */ + LCD_WriteReg(R0, 0x20); +} + +/******************************************************************************* +* Function Name : LCD_SetTextColor +* Description : Sets the Text color. +* Input : - Color: specifies the Text color code RGB(5-6-5). +* Output : - TextColor: Text color global variable used by LCD_DrawChar +* and LCD_DrawPicture functions. +* Return : None +*******************************************************************************/ +void LCD_SetTextColor(vu16 Color) +{ + TextColor = Color; +} + +/******************************************************************************* +* Function Name : LCD_SetBackColor +* Description : Sets the Background color. +* Input : - Color: specifies the Background color code RGB(5-6-5). +* Output : - BackColor: Background color global variable used by +* LCD_DrawChar and LCD_DrawPicture functions. +* Return : None +*******************************************************************************/ +void LCD_SetBackColor(vu16 Color) +{ + BackColor = Color; +} + +/******************************************************************************* +* Function Name : LCD_ClearLine +* Description : Clears the selected line. +* Input : - Line: the Line to be cleared. +* This parameter can be one of the following values: +* - Linex: where x can be 0..9 +* Output : None +* Return : None +*******************************************************************************/ +void LCD_ClearLine(u8 Line) +{ + LCD_DisplayStringLine(Line, " "); +} + +/******************************************************************************* +* Function Name : LCD_Clear +* Description : Clears the hole LCD. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void LCD_Clear(void) +{ + u32 index = 0; + + LCD_SetCursor(0x00, 0x013F); + + for(index = 0; index < 0x12C00; index++) + { + LCD_WriteRAM(White); + } +} + +/******************************************************************************* +* Function Name : LCD_SetCursor +* Description : Sets the cursor position. +* Input : - Xpos: specifies the X position. +* - Ypos: specifies the Y position. +* Output : None +* Return : None +*******************************************************************************/ +void LCD_SetCursor(u8 Xpos, u16 Ypos) +{ + LCD_WriteReg(R66, Xpos); + LCD_WriteReg(R67, ((Ypos & 0x100)>> 8)); + LCD_WriteReg(R68, (Ypos & 0xFF)); +} + +/******************************************************************************* +* Function Name : LCD_DrawChar +* Description : Draws a character on LCD. +* Input : - Xpos: the Line where to display the character shape. +* This parameter can be one of the following values: +* - Linex: where x can be 0..9 +* - Ypos: start column address. +* - c: pointer to the character data. +* Output : None +* Return : None +*******************************************************************************/ +void LCD_DrawChar(u8 Xpos, u16 Ypos, uc16 *c) +{ + u32 index = 0, i = 0; + u8 Xaddress = 0; + + Xaddress = Xpos; + + LCD_SetCursor(Xaddress, Ypos); + + for(index = 0; index < 24; index++) + { + for(i = 0; i < 16; i++) + { + if((c[index] & (1 << i)) == 0x00) + { + LCD_WriteRAM(BackColor); + } + else + { + LCD_WriteRAM(TextColor); + } + } + Xaddress++; + LCD_SetCursor(Xaddress, Ypos); + } +} + +/******************************************************************************* +* Function Name : LCD_DisplayChar +* Description : Displays one character (16dots width, 24dots height). +* Input : - Line: the Line where to display the character shape . +* This parameter can be one of the following values: +* - Linex: where x can be 0..9 +* - Column: start column address. +* - Ascii: character ascii code, must be between 0x20 and 0x7E. +* Output : None +* Return : None +*******************************************************************************/ +void LCD_DisplayChar(u8 Line, u16 Column, u8 Ascii) +{ + Ascii -= 32; + LCD_DrawChar(Line, Column, &ASCII_Table[Ascii * 24]); +} + +/******************************************************************************* +* Function Name : LCD_DisplayStringLine +* Description : Displays a maximum of 20 char on the LCD. +* Input : - Line: the Line where to display the character shape . +* This parameter can be one of the following values: +* - Linex: where x can be 0..9 +* - *ptr: pointer to string to display on LCD. +* Output : None +* Return : None +*******************************************************************************/ +void LCD_DisplayStringLine(u8 Line, u8 *ptr) +{ + u32 i = 0; + u16 refcolumn = 319; + + /* Send the string character by character on lCD */ + while ((*ptr != 0) & (i < 20)) + { + /* Display one character on LCD */ + LCD_DisplayChar(Line, refcolumn, *ptr); + /* Decrement the column position by 16 */ + refcolumn -= 16; + /* Point on the next character */ + ptr++; + /* Increment the character counter */ + i++; + } +} + +/******************************************************************************* +* Function Name : LCD_DisplayString +* Description : Displays a maximum of 200 char on the LCD. +* Input : - Line: the starting Line where to display the character shape. +* This parameter can be one of the following values: +* - Linex: where x can be 0..9 +* - *ptr: pointer to string to display on LCD. +* Output : None +* Return : None +*******************************************************************************/ +void LCD_DisplayString(u8 Line, u8 *ptr) +{ + u32 i = 0, column = 0, index = 0, spaceindex = 0; + u16 refcolumn = 319; + u32 length = 0; + + /* Get the string length */ + length = StrLength(ptr); + if(length > 200) + { + /* Set the Cursor position */ + LCD_SetCursor(Line, 0x013F); + /* Clear the Selected Line */ + LCD_ClearLine(Line); + LCD_DisplayStringLine(Line, " String too long "); + } + else + { + /* Set the Cursor position */ + LCD_SetCursor(Line, 0x013F); + /* Clear the Selected Line */ + LCD_ClearLine(Line); + + while(length--) + { + if(index == 20) + { + if(*ptr == 0x20) + { + ptr++; + } + else + { + for(i = 0; i < spaceindex; i++) + { + LCD_DisplayChar(Line, column, ' '); + column -= 16; + } + ptr -= (spaceindex - 1); + length += (spaceindex - 1); + } + Line += 24; + /* Clear the Selected Line */ + LCD_ClearLine(Line); + refcolumn = 319; + index = 0; + } + /* Display one character on LCD */ + LCD_DisplayChar(Line, refcolumn, *ptr); + + /* Increment character number in one line */ + index++; + + /* Decrement the column position by 16 */ + refcolumn -= 16; + /* Point on the next character */ + ptr++; + /* Increment the number of character after the last space */ + spaceindex++; + if(*ptr == 0x20) + { + spaceindex = 0; + column = refcolumn - 16; + } + } + } +} + +/******************************************************************************* +* Function Name : LCD_ScrollText +* Description : +* Input : +* Output : None +* Return : None +*******************************************************************************/ +void LCD_ScrollText(u8 Line, u8 *ptr) +{ + u32 i = 0, length = 0, x = 0; + u16 refcolumn = 319; + + /* Get the string length */ + length = StrLength(ptr); + + while(1) + { + /* Send the string character by character on lCD */ + while ((*ptr != 0) & (i < 20)) + { + /* Display one character on LCD */ + LCD_DisplayChar(Line, refcolumn, *ptr); + /* Decrement the column position by 16 */ + refcolumn -= 16; + /* Point on the next character */ + ptr++; + /* Increment the character counter */ + i++; + } + vTaskDelay( 100 / portTICK_RATE_MS ); + i = 0; + //LCD_ClearLine(Line); + ptr -= length; + x++; + if(refcolumn < 16) + { + x = 0; + } + refcolumn = 319 - (x * 16); + } +} + +/******************************************************************************* +* Function Name : LCD_SetDisplayWindow +* Description : Sets a display window +* Input : - Xpos: specifies the X position. +* - Ypos: specifies the Y position. +* - Height: display window height. +* - Width: display window width. +* Output : None +* Return : None +*******************************************************************************/ +void LCD_SetDisplayWindow(u8 Xpos, u16 Ypos, u8 Height, u16 Width) +{ + LCD_WriteReg(R1, 0xD0); + LCD_WriteReg(R5, 0x14); + + LCD_WriteReg(R69, Xpos); + LCD_WriteReg(R70, (Xpos + Height + 1)); + + LCD_WriteReg(R71, ((Ypos & 0x100)>> 8)); + LCD_WriteReg(R72, (Ypos & 0xFF)); + + LCD_WriteReg(R73, (((Ypos + Width + 1) & 0x100)>> 8)); + LCD_WriteReg(R74, ((Ypos + Width + 1) & 0xFF)); + + LCD_SetCursor(Xpos, Ypos); +} + +/******************************************************************************* +* Function Name : LCD_DrawLine +* Description : Displays a line. +* Input : - Xpos: specifies the X position. +* - Ypos: specifies the Y position. +* - Length: line length. +* - Direction: line direction. +* This parameter can be one of the following values: Vertical +* or Horizontal. +* Output : None +* Return : None +*******************************************************************************/ +void LCD_DrawLine(u8 Xpos, u16 Ypos, u16 Length, u8 Direction) +{ + u32 i = 0; + + LCD_SetCursor(Xpos, Ypos); + + if(Direction == Horizontal) + { + for(i = 0; i < Length; i++) + { + LCD_WriteRAM(TextColor); + } + } + else + { + for(i = 0; i < Length; i++) + { + + LCD_WriteRAM(TextColor); + Xpos++; + LCD_SetCursor(Xpos, Ypos); + } + } +} + +/******************************************************************************* +* Function Name : LCD_DrawRect +* Description : Displays a rectangle. +* Input : - Xpos: specifies the X position. +* - Ypos: specifies the Y position. +* - Height: display rectangle height. +* - Width: display rectangle width. +* Output : None +* Return : None +*******************************************************************************/ +void LCD_DrawRect(u8 Xpos, u16 Ypos, u8 Height, u16 Width) +{ + LCD_DrawLine(Xpos, Ypos, Width, Horizontal); + LCD_DrawLine((Xpos + Height), Ypos, Width, Horizontal); + + LCD_DrawLine(Xpos, Ypos, Height, Vertical); + LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, Vertical); +} + +/******************************************************************************* +* Function Name : LCD_DrawCircle +* Description : Displays a circle. +* Input : - Xpos: specifies the X position. +* - Ypos: specifies the Y position. +* - Height: display rectangle height. +* - Width: display rectangle width. +* Output : None +* Return : None +*******************************************************************************/ +void LCD_DrawCircle(u8 Xpos, u16 Ypos, u16 Radius) +{ + s32 D; /* Decision Variable */ + u32 CurX; /* Current X Value */ + u32 CurY; /* Current Y Value */ + + D = 3 - (Radius << 1); + CurX = 0; + CurY = Radius; + + while (CurX <= CurY) + { + LCD_SetCursor(Xpos + CurX, Ypos + CurY); + LCD_WriteRAM(TextColor); + LCD_SetCursor(Xpos + CurX, Ypos - CurY); + LCD_WriteRAM(TextColor); + LCD_SetCursor(Xpos - CurX, Ypos + CurY); + LCD_WriteRAM(TextColor); + LCD_SetCursor(Xpos - CurX, Ypos - CurY); + LCD_WriteRAM(TextColor); + LCD_SetCursor(Xpos + CurY, Ypos + CurX); + LCD_WriteRAM(TextColor); + LCD_SetCursor(Xpos + CurY, Ypos - CurX); + LCD_WriteRAM(TextColor); + LCD_SetCursor(Xpos - CurY, Ypos + CurX); + LCD_WriteRAM(TextColor); + LCD_SetCursor(Xpos - CurY, Ypos - CurX); + LCD_WriteRAM(TextColor); + + if (D < 0) + { + D += (CurX << 2) + 6; + } + else + { + D += ((CurX - CurY) << 2) + 10; + CurY--; + } + CurX++; + } +} + +/******************************************************************************* +* Function Name : LCD_DrawMonoPict +* Description : Displays a monocolor picture. +* Input : - Pict: pointer to the picture array. +* Output : None +* Return : None +*******************************************************************************/ +void LCD_DrawMonoPict(uc32 *Pict) +{ + u32 index = 0, i = 0; + + LCD_SetCursor(0, 319); + + for(index = 0; index < 2400; index++) + { + for(i = 0; i < 32; i++) + { + if((Pict[index] & (1 << i)) == 0x00) + { + LCD_WriteRAM(BackColor); + } + else + { + LCD_WriteRAM(TextColor); + } + } + } +} + +/******************************************************************************* +* Function Name : LCD_DrawBMP +* Description : Displays a bitmap picture loaded in the SPI Flash. +* Input : - BmpAddress: Bmp picture address in the SPI Flash. +* Output : None +* Return : None +*******************************************************************************/ +void LCD_DrawBMP(u32 BmpAddress) +{ + u32 i = 0; + + LCD_WriteReg(R1, 0xD0); + LCD_WriteReg(R5, 0x04); + + LCD_SetCursor(239, 0x013F); + + SPI_FLASH_StartReadSequence(BmpAddress); + + /* Disable SPI1 */ + SPI_Cmd(SPI1, DISABLE); + /* SPI in 16-bit mode */ + SPI_DataSizeConfig(SPI1, SPI_DataSize_16b); + /* Enable SPI1 */ + SPI_Cmd(SPI1, ENABLE); + + for(i = 0; i < 76800; i++) + { + LCD_WriteRAM(__REV_HalfWord(SPI_FLASH_SendHalfWord(0xA5A5))); + } + + /* Deselect the FLASH: Chip Select high */ + SPI_FLASH_ChipSelect(1); + + /* Disable SPI1 */ + SPI_Cmd(SPI1, DISABLE); + /* SPI in 8-bit mode */ + SPI_DataSizeConfig(SPI1, SPI_DataSize_8b); + /* Enable SPI1 */ + SPI_Cmd(SPI1, ENABLE); +} + +/******************************************************************************* +* Function Name : LCD_WriteReg +* Description : Writes to the selected LCD register. +* Input : - LCD_Reg: address of the selected register. +* - LCD_RegValue: value to write to the selected register. +* Output : None +* Return : None +*******************************************************************************/ +void LCD_WriteReg(u8 LCD_Reg, u8 LCD_RegValue) +{ + u16 tmp = 0; + + LCD_CtrlLinesWrite(GPIOD, CtrlPin_NWR, Bit_RESET); + LCD_CtrlLinesWrite(GPIOD, CtrlPin_RS, Bit_RESET); + LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_RESET); + + tmp = LCD_Reg << 8; + tmp |= LCD_RegValue; + + SPI_SendData(SPI2, tmp); + while(SPI_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET) + { + } + + LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_SET); +} + +/******************************************************************************* +* Function Name : LCD_ReadReg +* Description : Reads the selected LCD Register. +* Input : None +* Output : None +* Return : LCD Register Value. +*******************************************************************************/ +u8 LCD_ReadReg(u8 LCD_Reg) +{ + u16 tmp = 0; + + LCD_CtrlLinesWrite(GPIOD, CtrlPin_NWR, Bit_RESET); + LCD_CtrlLinesWrite(GPIOD, CtrlPin_RS, Bit_RESET); + LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_RESET); + + while(SPI_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET) + { + } + SPI_SendData(SPI2, LCD_Reg); + + LCD_CtrlLinesWrite(GPIOD, CtrlPin_NWR, Bit_SET); + + while(SPI_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET) + { + } + SPI_SendData(SPI2, 0xFF); + + while(SPI_GetFlagStatus(SPI2, SPI_FLAG_RXNE)== RESET) + { + } + tmp = SPI_ReceiveData(SPI2); + + LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_SET); + return tmp; +} + +/******************************************************************************* +* Function Name : LCD_WriteRAM +* Description : Writes to the LCD RAM. +* Input : - RGB_Code: the pixel color in RGB mode (5-6-5). +* Output : None +* Return : None +*******************************************************************************/ +void LCD_WriteRAM(u16 RGB_Code) +{ + LCD_CtrlLinesWrite(GPIOD, CtrlPin_NWR, Bit_RESET); + LCD_CtrlLinesWrite(GPIOD, CtrlPin_RS, Bit_SET); + LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_RESET); + + SPI_SendData(SPI2, RGB_Code); + while(SPI_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET) + { + } + + LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_SET); +} + +/******************************************************************************* +* Function Name : LCD_ReadRAM +* Description : Reads the LCD RAM. +* Input : None +* Output : None +* Return : LCD RAM Value. +*******************************************************************************/ +u16 LCD_ReadRAM(void) +{ + u16 tmp = 0; + + LCD_CtrlLinesWrite(GPIOD, CtrlPin_NWR, Bit_SET); + LCD_CtrlLinesWrite(GPIOD, CtrlPin_RS, Bit_SET); + LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_RESET); + + while(SPI_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET) + { + } + SPI_SendData(SPI2, 0xFF); + while(SPI_GetFlagStatus(SPI2, SPI_FLAG_RXNE)==RESET) + { + } + tmp = SPI_ReceiveData(SPI2); + + LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_SET); + + return tmp; +} + +/******************************************************************************* +* Function Name : LCD_PowerOn +* Description : +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void LCD_PowerOn(void) +{ + /* Power On Set */ + LCD_WriteReg(R28, 0x73); + LCD_WriteReg(R36, 0x74); + LCD_WriteReg(R30, 0x01); + LCD_WriteReg(R24, 0xC1); + vTaskDelay( 10 / portTICK_RATE_MS ); /* Delay 10 ms */ + LCD_WriteReg(R24, 0xE1); + LCD_WriteReg(R24, 0xF1); + vTaskDelay( 60 / portTICK_RATE_MS ); /* Delay 60 ms */ + LCD_WriteReg(R24, 0xF5); + vTaskDelay( 60 / portTICK_RATE_MS ); /* Delay 60 ms */ + LCD_WriteReg(R27, 0x09); + vTaskDelay( 10 / portTICK_RATE_MS ); /* Delay 10 ms */ + LCD_WriteReg(R31, 0x11); + LCD_WriteReg(R32, 0x0E); + LCD_WriteReg(R30, 0x81); + vTaskDelay( 10 / portTICK_RATE_MS ); /* Delay 10 ms */ +} + +/******************************************************************************* +* Function Name : LCD_DisplayOn +* Description : Enables the Display. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void LCD_DisplayOn(void) +{ + LCD_WriteReg(R1, 0x50); + LCD_WriteReg(R5, 0x04); + + /* Display On */ + LCD_WriteReg(R0, 0x80); + LCD_WriteReg(R59, 0x01); + vTaskDelay( 40 / portTICK_RATE_MS ); /* Delay 40 ms */ + LCD_WriteReg(R0, 0x20); +} + +/******************************************************************************* +* Function Name : LCD_DisplayOff +* Description : Disables the Display. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void LCD_DisplayOff(void) +{ + /* Display Off */ + LCD_WriteReg(R0, 0xA0); + vTaskDelay( 40 / portTICK_RATE_MS ); /* Delay 40 ms */ + LCD_WriteReg(R59, 0x00); +} + +/******************************************************************************* +* Function Name : LCD_CtrlLinesConfig +* Description : Configures LCD control lines in Output Push-Pull mode. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void LCD_CtrlLinesConfig(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /* Configure NCS (PB.02) in Output Push-Pull mode */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_Init(GPIOB, &GPIO_InitStructure); + + /* Configure NWR(RNW), RS (PD.15, PD.07) in Output Push-Pull mode */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_15; + GPIO_Init(GPIOD, &GPIO_InitStructure); +} + +/******************************************************************************* +* Function Name : LCD_CtrlLinesWrite +* Description : Sets or reset LCD control lines. +* Input : - GPIOx: where x can be B or D to select the GPIO peripheral. +* - CtrlPins: the Control line. This parameter can be: +* - CtrlPin_NCS: Chip Select pin (PB.02) +* - CtrlPin_NWR: Read/Write Selection pin (PD.15) +* - CtrlPin_RS: Register/RAM Selection pin (PD.07) +* - BitVal: specifies the value to be written to the selected bit. +* This parameter can be: +* - Bit_RESET: to clear the port pin +* - Bit_SET: to set the port pin +* Output : None +* Return : None +*******************************************************************************/ +void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, u16 CtrlPins, BitAction BitVal) +{ + /* Set or Reset the control line */ + GPIO_WriteBit(GPIOx, CtrlPins, BitVal); +} + +/******************************************************************************* +* Function Name : LCD_SPIConfig +* Description : Configures the SPI2 interface. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void LCD_SPIConfig(void) +{ + SPI_InitTypeDef SPI_InitStructure; + GPIO_InitTypeDef GPIO_InitStructure; + + /* Enable GPIOA clock */ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE); + + /* Enable SPI2 clock */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE); + + /* Configure SPI2 pins: NSS, SCK, MISO and MOSI */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOB, &GPIO_InitStructure); + + /* SPI2 Config */ + SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; + SPI_InitStructure.SPI_Mode = SPI_Mode_Master; + SPI_InitStructure.SPI_DataSize = SPI_DataSize_16b; + SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low; + SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge; + SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; + SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; + SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; + SPI_Init(SPI2, &SPI_InitStructure); + + /* SPI2 enable */ + SPI_Cmd(SPI2, ENABLE); +} + +/******************************************************************************* +* Function Name : StrLength +* Description : Returns length of string. +* Input : - Str: Character Pointer. +* Output : None +* Return : String length. +*******************************************************************************/ +static u32 StrLength(u8 *Str) +{ + u32 Index = 0; + + /* Increment the Index unless the end of string */ + for(Index = 0; *Str != '\0'; Str++, Index++) + { + } + + return Index; +} + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_adc.c b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_adc.c new file mode 100644 index 000000000..caf94a24c --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_adc.c @@ -0,0 +1,1321 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_adc.c +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file provides all the ADC firmware functions. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_adc.h" +#include "stm32f10x_rcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* ADC ADON mask */ +#define CR2_ADON_Set ((u32)0x00000001) +#define CR2_ADON_Reset ((u32)0xFFFFFFFE) + +/* ADC DMA mask */ +#define CR2_DMA_Set ((u16)0x0100) +#define CR2_DMA_Reset ((u16)0xFEFF) + +/* ADC RSTCAL mask */ +#define CR2_RSTCAL_Set ((u16)0x0008) + +/* ADC CAL mask */ +#define CR2_CAL_Set ((u16)0x0004) + +/* ADC SWSTRT mask */ +#define CR2_SWSTRT_Set ((u32)0x00400000) + +/* ADC DISCNUM mask */ +#define CR1_DISCNUM_Reset ((u32)0xFFFF1FFF) + +/* ADC DISCEN mask */ +#define CR1_DISCEN_Set ((u32)0x00000800) +#define CR1_DISCEN_Reset ((u32)0xFFFFF7FF) + +/* ADC EXTTRIG mask */ +#define CR2_EXTTRIG_Set ((u32)0x00100000) +#define CR2_EXTTRIG_Reset ((u32)0xFFEFFFFF) + +/* ADC Software start mask */ +#define CR2_EXTTRIG_SWSTRT_Set ((u32)0x00500000) +#define CR2_EXTTRIG_SWSTRT_Reset ((u32)0xFFAFFFFF) + +/* ADC JAUTO mask */ +#define CR1_JAUTO_Set ((u32)0x00000400) +#define CR1_JAUTO_Reset ((u32)0xFFFFFBFF) + +/* ADC JDISCEN mask */ +#define CR1_JDISCEN_Set ((u32)0x00001000) +#define CR1_JDISCEN_Reset ((u32)0xFFFFEFFF) + +/* ADC JEXTSEL mask */ +#define CR2_JEXTSEL_Reset ((u32)0xFFFF8FFF) + +/* ADC JEXTTRIG mask */ +#define CR2_JEXTTRIG_Set ((u32)0x00008000) +#define CR2_JEXTTRIG_Reset ((u32)0xFFFF7FFF) + +/* ADC JSWSTRT mask */ +#define CR2_JSWSTRT_Set ((u32)0x00200000) + +/* ADC injected software start mask */ +#define CR2_JEXTTRIG_JSWSTRT_Set ((u32)0x00208000) +#define CR2_JEXTTRIG_JSWSTRT_Reset ((u32)0xFFDF7FFF) + +/* ADC AWDCH mask */ +#define CR1_AWDCH_Reset ((u32)0xFFFFFFE0) + +/* ADC SQx mask */ +#define SQR3_SQ_Set ((u8)0x1F) +#define SQR2_SQ_Set ((u8)0x1F) +#define SQR1_SQ_Set ((u8)0x1F) + +/* ADC JSQx mask */ +#define JSQR_JSQ_Set ((u8)0x1F) + +/* ADC JL mask */ +#define JSQR_JL_Reset ((u32)0xFFCFFFFF) + +/* ADC SMPx mask */ +#define SMPR1_SMP_Set ((u8)0x07) +#define SMPR2_SMP_Set ((u8)0x07) + +/* ADC Analog watchdog enable mode mask */ +#define CR1_AWDMode_Reset ((u32)0xFF3FFDFF) + +/* ADC TSPD mask */ +#define CR2_TSPD_Set ((u32)0x00800000) +#define CR2_TSPD_Reset ((u32)0xFF7FFFFF) + +/* ADC JDRx registers= offset */ +#define JDR_Offset ((u8)0x28) + +/* ADC registers Masks */ +#define CR1_CLEAR_Mask ((u32)0xFFF0FEFF) +#define CR2_CLEAR_Mask ((u32)0xFFF1F7FD) +#define SQR1_CLEAR_Mask ((u32)0xFF0FFFFF) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : ADC_DeInit +* Description : Deinitializes the ADCx peripheral registers to their default +* reset values. +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_DeInit(ADC_TypeDef* ADCx) +{ + switch (*(u32*)&ADCx) + { + case ADC1_BASE: + /* Enable ADC1 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE); + /* Release ADC1 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE); + break; + + case ADC2_BASE: + /* Enable ADC2 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE); + /* Release ADC2 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : ADC_Init +* Description : Initializes the ADCx according to the specified parameters +* in the ADC_InitStruct. +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* - ADC_InitStruct: pointer to a ADC_InitTypeDef structure that +* contains the configuration information for the specified +* ADC peripheral. +* Output : None +* Return : None +******************************************************************************/ +void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct) +{ + u32 tmpreg1 = 0; + u8 tmpreg2 = 0; + + /* Check the parameters */ + assert(IS_ADC_MODE(ADC_InitStruct->ADC_Mode)); + assert(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode)); + assert(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode)); + assert(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv)); + assert(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); + assert(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfChannel)); + + /*---------------------------- ADCx CR1 Configuration -----------------*/ + /* Get the ADCx CR1 value */ + tmpreg1 = ADCx->CR1; + /* Clear DUALMODE and SCAN bits */ + tmpreg1 &= CR1_CLEAR_Mask; + /* Configure ADCx: Dual mode and scan conversion mode */ + /* Set DUALMODE bits according to ADC_Mode value */ + /* Set SCAN bit according to ADC_ScanConvMode value */ + tmpreg1 |= (u32)(ADC_InitStruct->ADC_Mode | ((u32)ADC_InitStruct->ADC_ScanConvMode << 8)); + /* Write to ADCx CR1 */ + ADCx->CR1 = tmpreg1; + + /*---------------------------- ADCx CR2 Configuration -----------------*/ + /* Get the ADCx CR2 value */ + tmpreg1 = ADCx->CR2; + /* Clear CONT, ALIGN and EXTTRIG bits */ + tmpreg1 &= CR2_CLEAR_Mask; + /* Configure ADCx: external trigger event and continuous conversion mode */ + /* Set ALIGN bit according to ADC_DataAlign value */ + /* Set EXTTRIG bits according to ADC_ExternalTrigConv value */ + /* Set CONT bit according to ADC_ContinuousConvMode value */ + tmpreg1 |= (u32)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | + ((u32)ADC_InitStruct->ADC_ContinuousConvMode << 1)); + /* Write to ADCx CR2 */ + ADCx->CR2 = tmpreg1; + + /*---------------------------- ADCx SQR1 Configuration -----------------*/ + /* Get the ADCx SQR1 value */ + tmpreg1 = ADCx->SQR1; + /* Clear L bits */ + tmpreg1 &= SQR1_CLEAR_Mask; + /* Configure ADCx: regular channel sequence length */ + /* Set L bits according to ADC_NbrOfChannel value */ + tmpreg2 |= (ADC_InitStruct->ADC_NbrOfChannel - 1); + tmpreg1 |= ((u32)tmpreg2 << 20); + /* Write to ADCx SQR1 */ + ADCx->SQR1 = tmpreg1; +} + +/******************************************************************************* +* Function Name : ADC_StructInit +* Description : Fills each ADC_InitStruct member with its default value. +* Input : ADC_InitStruct : pointer to a ADC_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) +{ + /* Reset ADC init structure parameters values */ + /* Initialize the ADC_Mode member */ + ADC_InitStruct->ADC_Mode = ADC_Mode_Independent; + + /* initialize the ADC_ScanConvMode member */ + ADC_InitStruct->ADC_ScanConvMode = DISABLE; + + /* Initialize the ADC_ContinuousConvMode member */ + ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; + + /* Initialize the ADC_ExternalTrigConv member */ + ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; + + /* Initialize the ADC_DataAlign member */ + ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; + + /* Initialize the ADC_NbrOfChannel member */ + ADC_InitStruct->ADC_NbrOfChannel = 1; +} + +/******************************************************************************* +* Function Name : ADC_Cmd +* Description : Enables or disables the specified ADC peripheral. +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* - NewState: new state of the ADCx peripheral. This parameter +* can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the ADON bit to wake up the ADC from power down mode */ + ADCx->CR2 |= CR2_ADON_Set; + } + else + { + /* Disable the selected ADC peripheral */ + ADCx->CR2 &= CR2_ADON_Reset; + } +} + +/******************************************************************************* +* Function Name : ADC_DMACmd +* Description : Enables or disables the specified ADC DMA request. +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* - NewState: new state of the selected ADC DMA transfer. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ADC DMA request */ + ADCx->CR2 |= CR2_DMA_Set; + } + else + { + /* Disable the selected ADC DMA request */ + ADCx->CR2 &= CR2_DMA_Reset; + } +} + +/******************************************************************************* +* Function Name : ADC_ITConfig +* Description : Enables or disables the specified ADC interrupts. +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* - ADC_IT: specifies the ADC interrupts sources to be enabled +* or disabled. +* This parameter can be any combination of the following values: +* - ADC_IT_EOC: End of conversion interrupt mask +* - ADC_IT_AWD: Analog watchdog interrupt mask +* - ADC_IT_JEOC: End of injected conversion interrupt mask +* - NewState: new state of the specified ADC interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_ITConfig(ADC_TypeDef* ADCx, u16 ADC_IT, FunctionalState NewState) +{ + u8 itmask = 0; + + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + assert(IS_ADC_IT(ADC_IT)); + + /* Get the ADC IT index */ + itmask = (u8)ADC_IT; + + if (NewState != DISABLE) + { + /* Enable the selected ADC interrupts */ + ADCx->CR1 |= itmask; + } + else + { + /* Disable the selected ADC interrupts */ + ADCx->CR1 &= (~(u32)itmask); + } +} + +/******************************************************************************* +* Function Name : ADC_ResetCalibration +* Description : Resets the ADC calibration registers. +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_ResetCalibration(ADC_TypeDef* ADCx) +{ + /* Resets the selected ADC calibartion registers */ + ADCx->CR2 |= CR2_RSTCAL_Set; +} + +/******************************************************************************* +* Function Name : ADC_GetResetCalibrationStatus +* Description : Gets the ADC reset calibration registers status. +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* Output : None +* Return : The new state of ADC Reset Calibration registers (SET or RESET). +*******************************************************************************/ +FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx) +{ + FlagStatus bitstatus = RESET; + + /* Check the status of RSTCAL bit */ + if ((ADCx->CR2 & CR2_RSTCAL_Set) != (u16)RESET) + { + /* RSTCAL bit is set */ + bitstatus = SET; + } + else + { + /* RSTCAL bit is reset */ + bitstatus = RESET; + } + /* Return the RSTCAL bit status */ + return bitstatus; +} + +/******************************************************************************* +* Function Name : ADC_StartCalibration +* Description : Starts the calibration process. +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_StartCalibration(ADC_TypeDef* ADCx) +{ + /* Enable the selected ADC calibration process */ + ADCx->CR2 |= CR2_CAL_Set; +} + +/******************************************************************************* +* Function Name : ADC_GetCalibrationStatus +* Description : Gets the ADC calibration status. +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* Output : None +* Return : The new state of ADC calibration (SET or RESET). +*******************************************************************************/ +FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx) +{ + FlagStatus bitstatus = RESET; + + /* Check the status of CAL bit */ + if ((ADCx->CR2 & CR2_CAL_Set) != (u16)RESET) + { + /* CAL bit is set: calibration on going */ + bitstatus = SET; + } + else + { + /* CAL bit is reset: end of calibration */ + bitstatus = RESET; + } + /* Return the CAL bit status */ + return bitstatus; +} + +/******************************************************************************* +* Function Name : ADC_SoftwareStartConvCmd +* Description : Enables or disables the ADC software start conversion . +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* - NewState: new state of the selected ADC software start conversion. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ADC conversion on external event */ + /* Starts the selected ADC conversion */ + ADCx->CR2 |= CR2_EXTTRIG_SWSTRT_Set; + } + else + { + /* Stops the selected ADC conversion */ + /* Disable the selected ADC conversion on external event */ + ADCx->CR2 &= CR2_EXTTRIG_SWSTRT_Reset; + } +} + +/******************************************************************************* +* Function Name : ADC_GetSoftwareStartConvStatus +* Description : Gets the ADC Software start conversion Status. +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* Output : None +* Return : The new state of ADC software start conversion (SET or RESET). +*******************************************************************************/ +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx) +{ + FlagStatus bitstatus = RESET; + + /* Check the status of SWSTRT bit */ + if ((ADCx->CR2 & CR2_SWSTRT_Set) != (u32)RESET) + { + /* SWSTRT bit is set */ + bitstatus = SET; + } + else + { + /* SWSTRT bit is reset */ + bitstatus = RESET; + } + /* Return the SWSTRT bit status */ + return bitstatus; +} + +/******************************************************************************* +* Function Name : ADC_DiscModeChannelCountConfig +* Description : Configures the discontinuous mode for the selected ADC regular +* group channel. +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* - Number: specifies the discontinuous mode regular channel +* count value. This mumber must be between 1 and 8. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, u8 Number) +{ + u32 tmpreg1 = 0; + u8 tmpreg2 = 0; + + /* Check the parameters */ + assert(IS_ADC_REGULAR_DISC_NUMBER(Number)); + + /* Get the old register value */ + tmpreg1 = ADCx->CR1; + /* Clear the old discontinuous mode channel count */ + tmpreg1 &= CR1_DISCNUM_Reset; + /* Set the discontinuous mode channel count */ + tmpreg2 = Number - 1; + tmpreg1 |= ((u32)tmpreg2 << 13); + /* Store the new register value */ + ADCx->CR1 = tmpreg1; +} + +/******************************************************************************* +* Function Name : ADC_DiscModeCmd +* Description : Enables or disables the discontinuous mode on regular group +* channel for the specified ADC +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* - NewState: new state of the selected ADC discontinuous mode +* on regular group channel. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ADC regular discontinuous mode */ + ADCx->CR1 |= CR1_DISCEN_Set; + } + else + { + /* Disable the selected ADC regular discontinuous mode */ + ADCx->CR1 &= CR1_DISCEN_Reset; + } +} + +/******************************************************************************* +* Function Name : ADC_RegularChannelConfig +* Description : Configures for the selected ADC regular channel its corresponding +* rank in the sequencer and its sample time. +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* - ADC_Channel: the ADC channel to configure. +* This parameter can be one of the following values: +* - ADC_Channel_0: ADC Channel0 selected +* - ADC_Channel_1: ADC Channel1 selected +* - ADC_Channel_2: ADC Channel2 selected +* - ADC_Channel_3: ADC Channel3 selected +* - ADC_Channel_4: ADC Channel4 selected +* - ADC_Channel_5: ADC Channel5 selected +* - ADC_Channel_6: ADC Channel6 selected +* - ADC_Channel_7: ADC Channel7 selected +* - ADC_Channel_8: ADC Channel8 selected +* - ADC_Channel_9: ADC Channel9 selected +* - ADC_Channel_10: ADC Channel10 selected +* - ADC_Channel_11: ADC Channel11 selected +* - ADC_Channel_12: ADC Channel12 selected +* - ADC_Channel_13: ADC Channel13 selected +* - ADC_Channel_14: ADC Channel14 selected +* - ADC_Channel_15: ADC Channel15 selected +* - ADC_Channel_16: ADC Channel16 selected +* - ADC_Channel_17: ADC Channel17 selected +* - Rank: The rank in the regular group sequencer. This parameter +* must be between 1 to 16. +* - ADC_SampleTime: The sample time value to be set for the +* selected channel. +* This parameter can be one of the following values: +* - ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles +* - ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles +* - ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles +* - ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles +* - ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles +* - ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles +* - ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles +* - ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles +* Output : None +* Return : None +*******************************************************************************/ +void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime) +{ + u32 tmpreg1 = 0, tmpreg2 = 0; + + /* Check the parameters */ + assert(IS_ADC_CHANNEL(ADC_Channel)); + assert(IS_ADC_REGULAR_RANK(Rank)); + assert(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); + + /* if ADC_Channel_10 ... ADC_Channel_17 is selected */ + if (ADC_Channel > ADC_Channel_9) + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR1; + /* Calculate the mask to clear */ + tmpreg2 = (u32)SMPR1_SMP_Set << (3 * (ADC_Channel - 10)); + /* Clear the old discontinuous mode channel count */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (u32)ADC_SampleTime << (3 * (ADC_Channel - 10)); + /* Set the discontinuous mode channel count */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SMPR1 = tmpreg1; + } + else /* ADC_Channel include in ADC_Channel_[0..9] */ + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR2; + /* Calculate the mask to clear */ + tmpreg2 = (u32)SMPR2_SMP_Set << (3 * ADC_Channel); + /* Clear the old discontinuous mode channel count */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (u32)ADC_SampleTime << (3 * ADC_Channel); + /* Set the discontinuous mode channel count */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SMPR2 = tmpreg1; + } + /* For Rank 1 to 6 */ + if (Rank < 7) + { + /* Get the old register value */ + tmpreg1 = ADCx->SQR3; + /* Calculate the mask to clear */ + tmpreg2 = (u32)SQR3_SQ_Set << (5 * (Rank - 1)); + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (u32)ADC_Channel << (5 * (Rank - 1)); + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SQR3 = tmpreg1; + } + /* For Rank 7 to 12 */ + else if (Rank < 13) + { + /* Get the old register value */ + tmpreg1 = ADCx->SQR2; + /* Calculate the mask to clear */ + tmpreg2 = (u32)SQR2_SQ_Set << (5 * (Rank - 7)); + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (u32)ADC_Channel << (5 * (Rank - 7)); + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SQR2 = tmpreg1; + } + /* For Rank 13 to 16 */ + else + { + /* Get the old register value */ + tmpreg1 = ADCx->SQR1; + /* Calculate the mask to clear */ + tmpreg2 = (u32)SQR1_SQ_Set << (5 * (Rank - 13)); + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (u32)ADC_Channel << (5 * (Rank - 13)); + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SQR1 = tmpreg1; + } +} + +/******************************************************************************* +* Function Name : ADC_ExternalTrigConvCmd +* Description : Enables or disables the ADCx conversion through external trigger. +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* - NewState: new state of the selected ADC external trigger +* start of conversion. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ADC conversion on external event */ + ADCx->CR2 |= CR2_EXTTRIG_Set; + } + else + { + /* Disable the selected ADC conversion on external event */ + ADCx->CR2 &= CR2_EXTTRIG_Reset; + } +} + +/******************************************************************************* +* Function Name : ADC_GetConversionValue +* Description : Returns the last ADC conversion result data for regular channel. +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* Output : None +* Return : The Data conversion value. +*******************************************************************************/ +u16 ADC_GetConversionValue(ADC_TypeDef* ADCx) +{ + /* Return the selected ADC conversion value */ + return (u16) ADCx->DR; +} + +/******************************************************************************* +* Function Name : ADC_GetDualModeConversionValue +* Description : Returns the last ADCs conversion result data in dual mode. +* Output : None +* Return : The Data conversion value. +*******************************************************************************/ +u32 ADC_GetDualModeConversionValue(void) +{ + /* Return the dual mode conversion value */ + return ADC1->DR; +} + +/******************************************************************************* +* Function Name : ADC_AutoInjectedConvCmd +* Description : Enables or disables the automatic injected group conversion +* after regular one. +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* - NewState: new state of the selected ADC auto injected +* conversion +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ADC automatic injected group conversion */ + ADCx->CR1 |= CR1_JAUTO_Set; + } + else + { + /* Disable the selected ADC automatic injected group conversion */ + ADCx->CR1 &= CR1_JAUTO_Reset; + } +} + +/******************************************************************************* +* Function Name : ADC_InjectedDiscModeCmd +* Description : Enables or disables the discontinuous mode for injected group +* channel for the specified ADC +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* - NewState: new state of the selected ADC discontinuous mode +* on injected group channel. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ADC injected discontinuous mode */ + ADCx->CR1 |= CR1_JDISCEN_Set; + } + else + { + /* Disable the selected ADC injected discontinuous mode */ + ADCx->CR1 &= CR1_JDISCEN_Reset; + } +} + +/******************************************************************************* +* Function Name : ADC_ExternalTrigInjectedConvConfig +* Description : Configures the external trigger for injected channels conversion. +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* - ADC_ExternalTrigInjecConv: specifies the ADC trigger to +* start injected conversion. +* This parameter can be one of the following values: +* - ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event +* selected +* - ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture +* compare4 selected +* - ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event +* selected +* - ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture +* compare1 selected +* - ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture +* compare4 selected +* - ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event +* selected +* - ADC_ExternalTrigInjecConv_Ext_Interrupt15: External +* interrupt 15 event selected +* - ADC_ExternalTrigInjecConv_None: Injected conversion +* started by software and not by external trigger +* Output : None +* Return : None +*******************************************************************************/ +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, u32 ADC_ExternalTrigInjecConv) +{ + u32 tmpreg = 0; + + /* Check the parameters */ + assert(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv)); + + /* Get the old register value */ + tmpreg = ADCx->CR2; + /* Clear the old external event selection for injected group */ + tmpreg &= CR2_JEXTSEL_Reset; + /* Set the external event selection for injected group */ + tmpreg |= ADC_ExternalTrigInjecConv; + /* Store the new register value */ + ADCx->CR2 = tmpreg; +} + +/******************************************************************************* +* Function Name : ADC_ExternalTrigInjectedConvCmd +* Description : Enables or disables the ADCx injected channels conversion +* through external trigger +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* - NewState: new state of the selected ADC external trigger +* start of injected conversion. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ADC external event selection for injected group */ + ADCx->CR2 |= CR2_JEXTTRIG_Set; + } + else + { + /* Disable the selected ADC external event selection for injected group */ + ADCx->CR2 &= CR2_JEXTTRIG_Reset; + } +} + +/******************************************************************************* +* Function Name : ADC_SoftwareStartInjectedConvCmd +* Description : Enables or disables the start of the injected channels conversion. +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* - NewState: new state of the selected ADC software start +* injected conversion. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ADC external event selection for injected group */ + /* Starts the selected ADC injected conversion */ + ADCx->CR2 |= CR2_JEXTTRIG_JSWSTRT_Set; + } + else + { + /* Stops the selected ADC injected conversion */ + /* Disable the selected ADC external event selection for injected group */ + ADCx->CR2 &= CR2_JEXTTRIG_JSWSTRT_Reset; + } +} + +/******************************************************************************* +* Function Name : ADC_GetSoftwareStartInjectedConvCmdStatus +* Description : Gets the ADC Software start injected conversion Status. +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* Output : None +* Return : The new state of ADC software start injected conversion (SET or RESET). +*******************************************************************************/ +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx) +{ + FlagStatus bitstatus = RESET; + + /* Check the status of JSWSTRT bit */ + if ((ADCx->CR2 & CR2_JSWSTRT_Set) != (u32)RESET) + { + /* JSWSTRT bit is set */ + bitstatus = SET; + } + else + { + /* JSWSTRT bit is reset */ + bitstatus = RESET; + } + /* Return the JSWSTRT bit status */ + return bitstatus; +} + +/******************************************************************************* +* Function Name : ADC_InjectedChannelConfig +* Description : Configures for the selected ADC injected channel its corresponding +* rank in the sequencer and its sample time. +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* - ADC_Channel: the ADC channel to configure. +* This parameter can be one of the following values: +* - ADC_Channel_0: ADC Channel0 selected +* - ADC_Channel_1: ADC Channel1 selected +* - ADC_Channel_2: ADC Channel2 selected +* - ADC_Channel_3: ADC Channel3 selected +* - ADC_Channel_4: ADC Channel4 selected +* - ADC_Channel_5: ADC Channel5 selected +* - ADC_Channel_6: ADC Channel6 selected +* - ADC_Channel_7: ADC Channel7 selected +* - ADC_Channel_8: ADC Channel8 selected +* - ADC_Channel_9: ADC Channel9 selected +* - ADC_Channel_10: ADC Channel10 selected +* - ADC_Channel_11: ADC Channel11 selected +* - ADC_Channel_12: ADC Channel12 selected +* - ADC_Channel_13: ADC Channel13 selected +* - ADC_Channel_14: ADC Channel14 selected +* - ADC_Channel_15: ADC Channel15 selected +* - ADC_Channel_16: ADC Channel16 selected +* - ADC_Channel_17: ADC Channel17 selected +* - Rank: The rank in the injected group sequencer. This parameter +* must be between 1 to 4. +* - ADC_SampleTime: The sample time value to be set for the +* selected channel. +* This parameter can be one of the following values: +* - ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles +* - ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles +* - ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles +* - ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles +* - ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles +* - ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles +* - ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles +* - ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles +* Output : None +* Return : None +*******************************************************************************/ +void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime) +{ + u32 tmpreg1 = 0, tmpreg2 = 0; + u8 tmpreg3 = 0; + + /* Check the parameters */ + assert(IS_ADC_CHANNEL(ADC_Channel)); + assert(IS_ADC_INJECTED_RANK(Rank)); + assert(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); + + /* if ADC_Channel_10 ... ADC_Channel_17 is selected */ + if (ADC_Channel > ADC_Channel_9) + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR1; + /* Calculate the mask to clear */ + tmpreg2 = (u32)SMPR1_SMP_Set << (3*(ADC_Channel - 10)); + /* Clear the old discontinuous mode channel count */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (u32)ADC_SampleTime << (3*(ADC_Channel - 10)); + /* Set the discontinuous mode channel count */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SMPR1 = tmpreg1; + } + else /* ADC_Channel include in ADC_Channel_[0..9] */ + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR2; + /* Calculate the mask to clear */ + tmpreg2 = (u32)SMPR2_SMP_Set << (3 * ADC_Channel); + /* Clear the old discontinuous mode channel count */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (u32)ADC_SampleTime << (3 * ADC_Channel); + /* Set the discontinuous mode channel count */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SMPR2 = tmpreg1; + } + + /* Rank configuration */ + /* Get the old register value */ + tmpreg1 = ADCx->JSQR; + /* Get JL value: Number = JL+1 */ + tmpreg3 = (u8)((tmpreg1 & (u32)~JSQR_JL_Reset)>> 20); + /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */ + tmpreg2 = (u32)JSQR_JSQ_Set << (5 * ((Rank + 3) - (tmpreg3 + 1))); + /* Clear the old JSQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */ + tmpreg2 = (u32)ADC_Channel << (5 * ((Rank + 3) - (tmpreg3 + 1))); + /* Set the JSQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->JSQR = tmpreg1; +} + +/******************************************************************************* +* Function Name : ADC_InjectedSequencerLengthConfig +* Description : Configures the sequencer for injected channels +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* - Length: The sequencer length. +* This parameter must be a number between 1 to 4. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, u8 Length) +{ + u32 tmpreg1 = 0; + u8 tmpreg2 = 0; + + /* Check the parameters */ + assert(IS_ADC_INJECTED_LENGTH(Length)); + + /* Get the old register value */ + tmpreg1 = ADCx->JSQR; + /* Clear the old injected sequnence lenght JL bits */ + tmpreg1 &= JSQR_JL_Reset; + /* Set the injected sequnence lenght JL bits */ + tmpreg2 = Length - 1; + tmpreg1 |= (u32)tmpreg2 << 20; + /* Store the new register value */ + ADCx->JSQR = tmpreg1; +} + +/******************************************************************************* +* Function Name : ADC_SetInjectedOffset +* Description : Set the injected channels conversion value offset +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* - ADC_InjectedChannel: the ADC injected channel to set its +* offset. +* This parameter can be one of the following values: +* - ADC_InjectedChannel_1: Injected Channel1 selected +* - ADC_InjectedChannel_2: Injected Channel2 selected +* - ADC_InjectedChannel_3: Injected Channel3 selected +* - ADC_InjectedChannel_4: Injected Channel4 selected +* Output : None +* Return : None +*******************************************************************************/ +void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel, u16 Offset) +{ + /* Check the parameters */ + assert(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); + assert(IS_ADC_OFFSET(Offset)); + + /* Set the selected injected channel data offset */ + *((u32 *)((*(u32*)&ADCx) + ADC_InjectedChannel)) = (u32)Offset; +} + +/******************************************************************************* +* Function Name : ADC_GetInjectedConversionValue +* Description : Returns the ADC conversion result data for the selected +* injected channel +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* - ADC_InjectedChannel: the converted ADC injected channel. +* This parameter can be one of the following values: +* - ADC_InjectedChannel_1: Injected Channel1 selected +* - ADC_InjectedChannel_2: Injected Channel2 selected +* - ADC_InjectedChannel_3: Injected Channel3 selected +* - ADC_InjectedChannel_4: Injected Channel4 selected +* Output : None +* Return : The Data conversion value. +*******************************************************************************/ +u16 ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel) +{ + /* Check the parameters */ + assert(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); + + /* Returns the selected injected channel conversion data value */ + return (u16) (*(u32*) (((*(u32*)&ADCx) + ADC_InjectedChannel + JDR_Offset))); +} + +/******************************************************************************* +* Function Name : ADC_AnalogWatchdogCmd +* Description : Enables or disables the analog watchdog on single/all regular +* or injected channels +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* - ADC_AnalogWatchdog: the ADC analog watchdog configuration. +* This parameter can be one of the following values: +* - ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on +* a single regular channel +* - ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on +* a single injected channel +* - ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog +* watchdog on a single regular or injected channel +* - ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on +* all regular channel +* - ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on +* all injected channel +* - ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog +* on all regular and injected channels +* - ADC_AnalogWatchdog_None: No channel guarded by the +* analog watchdog +* Output : None +* Return : None +*******************************************************************************/ +void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, u32 ADC_AnalogWatchdog) +{ + u32 tmpreg = 0; + + /* Check the parameters */ + assert(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog)); + + /* Get the old register value */ + tmpreg = ADCx->CR1; + /* Clear AWDEN, AWDENJ and AWDSGL bits */ + tmpreg &= CR1_AWDMode_Reset; + /* Set the analog watchdog enable mode */ + tmpreg |= ADC_AnalogWatchdog; + /* Store the new register value */ + ADCx->CR1 = tmpreg; +} + +/******************************************************************************* +* Function Name : ADC_AnalogWatchdogThresholdsConfig +* Description : Configures the High and low thresholds of the analog watchdog. +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* - HighThreshold: the ADC analog watchdog High threshold value. +* This parameter must be a 12bit value. +* - LowThreshold: the ADC analog watchdog Low threshold value. +* This parameter must be a 12bit value. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, u16 HighThreshold, + u16 LowThreshold) +{ + /* Check the parameters */ + assert(IS_ADC_THRESHOLD(HighThreshold)); + assert(IS_ADC_THRESHOLD(LowThreshold)); + + /* Set the ADCx high threshold */ + ADCx->HTR = HighThreshold; + /* Set the ADCx low threshold */ + ADCx->LTR = LowThreshold; +} + +/******************************************************************************* +* Function Name : ADC_AnalogWatchdogSingleChannelConfig +* Description : Configures the analog watchdog guarded single channel +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* - ADC_Channel: the ADC channel to configure for the analog +* watchdog. +* This parameter can be one of the following values: +* - ADC_Channel_0: ADC Channel0 selected +* - ADC_Channel_1: ADC Channel1 selected +* - ADC_Channel_2: ADC Channel2 selected +* - ADC_Channel_3: ADC Channel3 selected +* - ADC_Channel_4: ADC Channel4 selected +* - ADC_Channel_5: ADC Channel5 selected +* - ADC_Channel_6: ADC Channel6 selected +* - ADC_Channel_7: ADC Channel7 selected +* - ADC_Channel_8: ADC Channel8 selected +* - ADC_Channel_9: ADC Channel9 selected +* - ADC_Channel_10: ADC Channel10 selected +* - ADC_Channel_11: ADC Channel11 selected +* - ADC_Channel_12: ADC Channel12 selected +* - ADC_Channel_13: ADC Channel13 selected +* - ADC_Channel_14: ADC Channel14 selected +* - ADC_Channel_15: ADC Channel15 selected +* - ADC_Channel_16: ADC Channel16 selected +* - ADC_Channel_17: ADC Channel17 selected +* Output : None +* Return : None +*******************************************************************************/ +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel) +{ + u32 tmpreg = 0; + + /* Check the parameters */ + assert(IS_ADC_CHANNEL(ADC_Channel)); + + /* Get the old register value */ + tmpreg = ADCx->CR1; + /* Clear the Analog watchdog channel select bits */ + tmpreg &= CR1_AWDCH_Reset; + /* Set the Analog watchdog channel */ + tmpreg |= ADC_Channel; + /* Store the new register value */ + ADCx->CR1 = tmpreg; +} + +/******************************************************************************* +* Function Name : ADC_TempSensorCmd +* Description : Enables or disables the temperature sensor. +* Input : - NewState: new state of the temperature sensor. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_TempSensorCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the temperature sensor */ + ADC1->CR2 |= CR2_TSPD_Set; + } + else + { + /* Disable the temperature sensor */ + ADC1->CR2 &= CR2_TSPD_Reset; + } +} + +/******************************************************************************* +* Function Name : ADC_GetFlagStatus +* Description : Checks whether the specified ADC flag is set or not. +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* - ADC_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - ADC_FLAG_AWD: Analog watchdog flag +* - ADC_FLAG_EOC: End of conversion flag +* - ADC_FLAG_JEOC: End of injected group conversion flag +* - ADC_FLAG_JSTRT: Start of injected group conversion flag +* - ADC_FLAG_STRT: Start of regular group conversion flag +* Output : None +* Return : The new state of ADC_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, u8 ADC_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert(IS_ADC_GET_FLAG(ADC_FLAG)); + + /* Check the status of the specified ADC flag */ + if ((ADCx->SR & ADC_FLAG) != (u8)RESET) + { + /* ADC_FLAG is set */ + bitstatus = SET; + } + else + { + /* ADC_FLAG is reset */ + bitstatus = RESET; + } + /* Return the ADC_FLAG status */ + return bitstatus; +} + +/******************************************************************************* +* Function Name : ADC_ClearFlag +* Description : Clears the ADCx's pending flags. +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* - ADC_FLAG: specifies the flag to clear. +* This parameter can be any combination of the following values: +* - ADC_FLAG_AWD: Analog watchdog flag +* - ADC_FLAG_EOC: End of conversion flag +* - ADC_FLAG_JEOC: End of injected group conversion flag +* - ADC_FLAG_JSTRT: Start of injected group conversion flag +* - ADC_FLAG_STRT: Start of regular group conversion flag +* Output : None +* Return : None +*******************************************************************************/ +void ADC_ClearFlag(ADC_TypeDef* ADCx, u8 ADC_FLAG) +{ + /* Check the parameters */ + assert(IS_ADC_CLEAR_FLAG(ADC_FLAG)); + + /* Clear the selected ADC flags */ + ADCx->SR &= ~(u32)ADC_FLAG; +} + +/******************************************************************************* +* Function Name : ADC_GetITStatus +* Description : Checks whether the specified ADC interrupt has occurred or not. +* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral. +* - ADC_IT: specifies the ADC interrupt source to check. +* This parameter can be one of the following values: +* - ADC_IT_EOC: End of conversion interrupt mask +* - ADC_IT_AWD: Analog watchdog interrupt mask +* - ADC_IT_JEOC: End of injected conversion interrupt mask +* Output : None +* Return : The new state of ADC_IT (SET or RESET). +*******************************************************************************/ +ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, u16 ADC_IT) +{ + ITStatus bitstatus = RESET; + u8 itmask = 0, enablestatus; + + /* Check the parameters */ + assert(IS_ADC_GET_IT(ADC_IT)); + + /* Get the ADC IT index */ + itmask = (u8)(ADC_IT >> 8); + + /* Get the ADC_IT enable bit status */ + enablestatus = (ADCx->CR1 & (u8)ADC_IT) ; + + /* Check the status of the specified ADC interrupt */ + if (((ADCx->SR & itmask) != (u8)RESET) && enablestatus) + { + /* ADC_IT is set */ + bitstatus = SET; + } + else + { + /* ADC_IT is reset */ + bitstatus = RESET; + } + /* Return the ADC_IT status */ + return bitstatus; +} + +/******************************************************************************* +* Function Name : ADC_ClearITPendingBit +* Description : Clears the ADC’s interrupt pending bits. +* Input : - ADC_IT: specifies the ADC interrupt pending bit to clear. +* This parameter can be any combination of the following values: +* - ADC_IT_EOC: End of conversion interrupt mask +* - ADC_IT_AWD: Analog watchdog interrupt mask +* - ADC_IT_JEOC: End of injected conversion interrupt mask +* Output : None +* Return : None +*******************************************************************************/ +void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, u16 ADC_IT) +{ + u8 itmask = 0; + + /* Check the parameters */ + assert(IS_ADC_IT(ADC_IT)); + + /* Get the ADC IT index */ + itmask = (u8)(ADC_IT >> 8); + + /* Clear the selected ADC interrupt pending bits */ + ADCx->SR &= ~(u32)itmask; +} + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_bkp.c b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_bkp.c new file mode 100644 index 000000000..a8616e0f1 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_bkp.c @@ -0,0 +1,263 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_bkp.c +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file provides all the BKP firmware functions. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_bkp.h" +#include "stm32f10x_rcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* ------------ BKP registers bit address in the alias region ----------- */ +#define BKP_OFFSET (BKP_BASE - PERIPH_BASE) + +/* --- RTCCR Register ---*/ +/* Alias word address of CCO bit */ +#define RTCCR_OFFSET (BKP_OFFSET + 0x2C) +#define CCO_BitNumber 0x07 +#define RTCCR_CCO_BB (PERIPH_BB_BASE + (RTCCR_OFFSET * 32) + (CCO_BitNumber * 4)) + +/* --- CR Register ---*/ +/* Alias word address of TPAL bit */ +#define CR_OFFSET (BKP_OFFSET + 0x30) +#define TPAL_BitNumber 0x01 +#define CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4)) + +/* Alias word address of TPE bit */ +#define TPE_BitNumber 0x00 +#define CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4)) + +/* --- CSR Register ---*/ +/* Alias word address of TPIE bit */ +#define CSR_OFFSET (BKP_OFFSET + 0x34) +#define TPIE_BitNumber 0x02 +#define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4)) + +/* Alias word address of TIF bit */ +#define TIF_BitNumber 0x09 +#define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4)) + +/* Alias word address of TEF bit */ +#define TEF_BitNumber 0x08 +#define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4)) + + +/* ---------------------- BKP registers bit mask ------------------------ */ +/* RTCCR register bit mask */ +#define RTCCR_CAL_Mask ((u16)0xFF80) + +/* CSR register bit mask */ +#define CSR_CTE_Set ((u16)0x0001) +#define CSR_CTI_Set ((u16)0x0002) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : BKP_DeInit +* Description : Deinitializes the BKP peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void BKP_DeInit(void) +{ + RCC_BackupResetCmd(ENABLE); + RCC_BackupResetCmd(DISABLE); +} + +/******************************************************************************* +* Function Name : BKP_TamperPinLevelConfig +* Description : Configures the Tamper Pin active level. +* Input : - BKP_TamperPinLevel: specifies the Tamper Pin active level. +* This parameter can be one of the following values: +* - BKP_TamperPinLevel_High: Tamper pin active on high level +* - BKP_TamperPinLevel_Low: Tamper pin active on low level +* Output : None +* Return : None +*******************************************************************************/ +void BKP_TamperPinLevelConfig(u16 BKP_TamperPinLevel) +{ + /* Check the parameters */ + assert(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel)); + + *(vu32 *) CR_TPAL_BB = BKP_TamperPinLevel; +} + +/******************************************************************************* +* Function Name : BKP_TamperPinCmd +* Description : Enables or disables the Tamper Pin activation. +* Input : - NewState: new state of the Tamper Pin activation. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void BKP_TamperPinCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + *(vu32 *) CR_TPE_BB = (u32)NewState; +} + +/******************************************************************************* +* Function Name : BKP_ITConfig +* Description : Enables or disables the Tamper Pin Interrupt. +* Input : - NewState: new state of the Tamper Pin Interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void BKP_ITConfig(FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + *(vu32 *) CSR_TPIE_BB = (u32)NewState; +} + +/******************************************************************************* +* Function Name : BKP_RTCCalibrationClockOutputCmd +* Description : Enables or disables the output of the Calibration Clock. +* Input : - NewState: new state of the Calibration Clock output. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void BKP_RTCCalibrationClockOutputCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + *(vu32 *) RTCCR_CCO_BB = (u32)NewState; +} + +/******************************************************************************* +* Function Name : BKP_SetRTCCalibrationValue +* Description : Sets RTC Clock Calibration value. +* Input : - CalibrationValue: specifies the RTC Clock Calibration value. +* This parameter must be a number between 0 and 0x7F. +* Output : None +* Return : None +*******************************************************************************/ +void BKP_SetRTCCalibrationValue(u8 CalibrationValue) +{ + u16 tmpreg = 0; + + /* Check the parameters */ + assert(IS_BKP_CALIBRATION_VALUE(CalibrationValue)); + + tmpreg = BKP->RTCCR; + + /* Clear CAL[6:0] bits */ + tmpreg &= RTCCR_CAL_Mask; + + /* Set CAL[6:0] bits according to CalibrationValue value */ + tmpreg |= CalibrationValue; + + /* Store the new value */ + BKP->RTCCR = tmpreg; +} + +/******************************************************************************* +* Function Name : BKP_WriteBackupRegister +* Description : Writes user data to the specified Data Backup Register. +* Input : - BKP_DR: specifies the Data Backup Register. +* This parameter can be BKP_DRx where x:[1, 10] +* - Data: data to write +* Output : None +* Return : None +*******************************************************************************/ +void BKP_WriteBackupRegister(u16 BKP_DR, u16 Data) +{ + /* Check the parameters */ + assert(IS_BKP_DR(BKP_DR)); + + *(vu16 *) (BKP_BASE + BKP_DR) = Data; +} + +/******************************************************************************* +* Function Name : BKP_ReadBackupRegister +* Description : Reads data from the specified Data Backup Register. +* Input : - BKP_DR: specifies the Data Backup Register. +* This parameter can be BKP_DRx where x:[1, 10] +* Output : None +* Return : The content of the specified Data Backup Register +*******************************************************************************/ +u16 BKP_ReadBackupRegister(u16 BKP_DR) +{ + /* Check the parameters */ + assert(IS_BKP_DR(BKP_DR)); + + return (*(vu16 *) (BKP_BASE + BKP_DR)); +} + +/******************************************************************************* +* Function Name : BKP_GetFlagStatus +* Description : Checks whether the Tamper Pin Event flag is set or not. +* Input : None +* Output : None +* Return : The new state of the Tamper Pin Event flag (SET or RESET). +*******************************************************************************/ +FlagStatus BKP_GetFlagStatus(void) +{ + return (FlagStatus)(*(vu32 *) CSR_TEF_BB); +} + +/******************************************************************************* +* Function Name : BKP_ClearFlag +* Description : Clears Tamper Pin Event pending flag. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void BKP_ClearFlag(void) +{ + /* Set CTE bit to clear Tamper Pin Event flag */ + BKP->CSR |= CSR_CTE_Set; +} + +/******************************************************************************* +* Function Name : BKP_GetITStatus +* Description : Checks whether the Tamper Pin Interrupt has occurred or not. +* Input : None +* Output : None +* Return : The new state of the Tamper Pin Interrupt (SET or RESET). +*******************************************************************************/ +ITStatus BKP_GetITStatus(void) +{ + return (ITStatus)(*(vu32 *) CSR_TIF_BB); +} + +/******************************************************************************* +* Function Name : BKP_ClearITPendingBit +* Description : Clears Tamper Pin Interrupt pending bit. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void BKP_ClearITPendingBit(void) +{ + /* Set CTI bit to clear Tamper Pin Interrupt pending bit */ + BKP->CSR |= CSR_CTI_Set; +} + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_can.c b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_can.c new file mode 100644 index 000000000..3457f0de4 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_can.c @@ -0,0 +1,873 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_can.c +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file provides all the CAN firmware functions. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_can.h" +#include "stm32f10x_rcc.h" + +/* Private typedef -----------------------------------------------------------*/ + +/* Private define ------------------------------------------------------------*/ +/* CAN Master Control Register bits */ +#define CAN_MCR_INRQ ((u32)0x00000001) /* Initialization request */ +#define CAN_MCR_SLEEP ((u32)0x00000002) /* Sleep mode request */ +#define CAN_MCR_TXFP ((u32)0x00000004) /* Transmit FIFO priority */ +#define CAN_MCR_RFLM ((u32)0x00000008) /* Receive FIFO locked mode */ +#define CAN_MCR_NART ((u32)0x00000010) /* No automatic retransmission */ +#define CAN_MCR_AWUM ((u32)0x00000020) /* Automatic wake up mode */ +#define CAN_MCR_ABOM ((u32)0x00000040) /* Automatic bus-off management */ +#define CAN_MCR_TTCM ((u32)0x00000080) /* time triggered communication */ + +/* CAN Master Status Register bits */ +#define CAN_MSR_INAK ((u32)0x00000001) /* Initialization acknowledge */ +#define CAN_MSR_WKUI ((u32)0x00000008) /* Wake-up interrupt */ +#define CAN_MSR_SLAKI ((u32)0x00000010) /* Sleep acknowledge interrupt */ + +/* CAN Transmit Status Register bits */ +#define CAN_TSR_RQCP0 ((u32)0x00000001) /* Request completed mailbox0 */ +#define CAN_TSR_TXOK0 ((u32)0x00000002) /* Transmission OK of mailbox0 */ +#define CAN_TSR_ABRQ0 ((u32)0x00000080) /* Abort request for mailbox0 */ +#define CAN_TSR_RQCP1 ((u32)0x00000100) /* Request completed mailbox1 */ +#define CAN_TSR_TXOK1 ((u32)0x00000200) /* Transmission OK of mailbox1 */ +#define CAN_TSR_ABRQ1 ((u32)0x00008000) /* Abort request for mailbox1 */ +#define CAN_TSR_RQCP2 ((u32)0x00010000) /* Request completed mailbox2 */ +#define CAN_TSR_TXOK2 ((u32)0x00020000) /* Transmission OK of mailbox2 */ +#define CAN_TSR_ABRQ2 ((u32)0x00800000) /* Abort request for mailbox2 */ +#define CAN_TSR_TME0 ((u32)0x04000000) /* Transmit mailbox 0 empty */ +#define CAN_TSR_TME1 ((u32)0x08000000) /* Transmit mailbox 1 empty */ +#define CAN_TSR_TME2 ((u32)0x10000000) /* Transmit mailbox 2 empty */ + +/* CAN Receive FIFO 0 Register bits */ +#define CAN_RF0R_FULL0 ((u32)0x00000008) /* FIFO 0 full */ +#define CAN_RF0R_FOVR0 ((u32)0x00000010) /* FIFO 0 overrun */ +#define CAN_RF0R_RFOM0 ((u32)0x00000020) /* Release FIFO 0 output mailbox */ + +/* CAN Receive FIFO 1 Register bits */ +#define CAN_RF1R_FULL1 ((u32)0x00000008) /* FIFO 1 full */ +#define CAN_RF1R_FOVR1 ((u32)0x00000010) /* FIFO 1 overrun */ +#define CAN_RF1R_RFOM1 ((u32)0x00000020) /* Release FIFO 1 output mailbox */ + +/* CAN Error Status Register bits */ +#define CAN_ESR_EWGF ((u32)0x00000001) /* Error warning flag */ +#define CAN_ESR_EPVF ((u32)0x00000002) /* Error passive flag */ +#define CAN_ESR_BOFF ((u32)0x00000004) /* Bus-off flag */ + +/* CAN Mailbox Transmit Request */ +#define CAN_TMIDxR_TXRQ ((u32)0x00000001) /* Transmit mailbox request */ + +/* CAN Filter Master Register bits */ +#define CAN_FMR_FINIT ((u32)0x00000001) /* Filter init mode */ + + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static ITStatus CheckITStatus(u32 CAN_Reg, u32 It_Bit); + +/* Private functions ---------------------------------------------------------*/ +/******************************************************************************* +* Function Name : CAN_DeInit +* Description : Deinitializes the CAN peripheral registers to their default +* reset values. +* Input : None. +* Output : None. +* Return : None. +*******************************************************************************/ +void CAN_DeInit(void) +{ + /* Enable CAN reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN, ENABLE); + /* Release CAN from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN, DISABLE); +} + +/******************************************************************************* +* Function Name : CAN_Init +* Description : Initializes the CAN peripheral according to the specified +* parameters in the CAN_InitStruct. +* Input : CAN_InitStruct: pointer to a CAN_InitTypeDef structure that + contains the configuration information for the CAN peripheral. +* Output : None. +* Return : Constant indicates initialization succeed which will be +* CANINITFAILED or CANINITOK. +*******************************************************************************/ +u8 CAN_Init(CAN_InitTypeDef* CAN_InitStruct) +{ + u8 InitStatus = 0; + + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM)); + assert(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM)); + assert(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM)); + assert(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART)); + assert(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM)); + assert(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP)); + assert(IS_CAN_MODE(CAN_InitStruct->CAN_Mode)); + assert(IS_CAN_SJW(CAN_InitStruct->CAN_SJW)); + assert(IS_CAN_BS1(CAN_InitStruct->CAN_BS1)); + assert(IS_CAN_BS2(CAN_InitStruct->CAN_BS2)); + assert(IS_CAN_CLOCK(CAN_InitStruct->CAN_Clock)); + assert(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler)); + + /* Request initialisation */ + CAN->MCR = CAN_MCR_INRQ; + + /* ...and check acknowledged */ + if ((CAN->MSR & CAN_MSR_INAK) == 0) + { + InitStatus = CANINITFAILED; + } + else + { + /* Set the time triggered communication mode */ + if (CAN_InitStruct->CAN_TTCM == ENABLE) + { + CAN->MCR |= CAN_MCR_TTCM; + } + else + { + CAN->MCR &= ~CAN_MCR_TTCM; + } + + /* Set the automatic bus-off management */ + if (CAN_InitStruct->CAN_ABOM == ENABLE) + { + CAN->MCR |= CAN_MCR_ABOM; + } + else + { + CAN->MCR &= ~CAN_MCR_ABOM; + } + + /* Set the automatic wake-up mode */ + if (CAN_InitStruct->CAN_AWUM == ENABLE) + { + CAN->MCR |= CAN_MCR_AWUM; + } + else + { + CAN->MCR &= ~CAN_MCR_AWUM; + } + + /* Set the no automatic retransmission */ + if (CAN_InitStruct->CAN_NART == ENABLE) + { + CAN->MCR |= CAN_MCR_NART; + } + else + { + CAN->MCR &= ~CAN_MCR_NART; + } + + /* Set the receive FIFO locked mode */ + if (CAN_InitStruct->CAN_RFLM == ENABLE) + { + CAN->MCR |= CAN_MCR_RFLM; + } + else + { + CAN->MCR &= ~CAN_MCR_RFLM; + } + + /* Set the transmit FIFO priority */ + if (CAN_InitStruct->CAN_TXFP == ENABLE) + { + CAN->MCR |= CAN_MCR_TXFP; + } + else + { + CAN->MCR &= ~CAN_MCR_TXFP; + } + + /* Set the bit timing register */ + CAN->BTR = (u32)((u32)CAN_InitStruct->CAN_Mode << 30) | ((u32)CAN_InitStruct->CAN_SJW << 24) | + ((u32)CAN_InitStruct->CAN_BS1 << 16) | ((u32)CAN_InitStruct->CAN_BS2 << 20) | + ((u32)CAN_InitStruct->CAN_Clock << 15) | ((u32)CAN_InitStruct->CAN_Prescaler - 1); + + InitStatus = CANINITOK; + + /* Request leave initialisation */ + CAN->MCR &= ~CAN_MCR_INRQ; + + /* ...and check acknowledged */ + if ((CAN->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) + { + InitStatus = CANINITFAILED; + } + } + + /* At this step, return the status of initialization */ + return InitStatus; +} + +/******************************************************************************* +* Function Name : CAN_FilterInit +* Description : Initializes the CAN peripheral according to the specified +* parameters in the CAN_FilterInitStruct. +* Input : CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef +* structure that contains the configuration information. +* Output : None. +* Return : None. +*******************************************************************************/ +void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct) +{ + u16 FilterNumber_BitPos = 0; + + /* Check the parameters */ + assert(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber)); + assert(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode)); + assert(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale)); + assert(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment)); + assert(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation)); + + FilterNumber_BitPos = (u16)((u16)0x0001 << ((u16)CAN_FilterInitStruct->CAN_FilterNumber)); + + /* Initialisation mode for the filter */ + CAN->FMR |= CAN_FMR_FINIT; + + /* Filter Deactivation */ + CAN->FA0R &= ~(u32)FilterNumber_BitPos; + + /* Filter Scale */ + if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit) + { + /* 16-bit scale for the filter */ + CAN->FS0R &= ~(u32)FilterNumber_BitPos; + + /* First 16-bit identifier and First 16-bit mask */ + /* Or First 16-bit identifier and Second 16-bit identifier */ + CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR0 = ((u32)((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) | + ((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterIdLow); + + /* Second 16-bit identifier and Second 16-bit mask */ + /* Or Third 16-bit identifier and Fourth 16-bit identifier */ + CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = ((u32)((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | + ((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterIdHigh); + } + if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit) + { + /* 32-bit scale for the filter */ + CAN->FS0R |= FilterNumber_BitPos; + + /* 32-bit identifier or First 32-bit identifier */ + CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR0 = ((u32)((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) | + ((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterIdLow); + + /* 32-bit mask or Second 32-bit identifier */ + CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = ((u32)((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | + ((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterMaskIdLow); + + } + + /* Filter Mode */ + if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask) + { + /*Id/Mask mode for the filter*/ + CAN->FM0R &= ~(u32)FilterNumber_BitPos; + } + else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ + { + /*Identifier list mode for the filter*/ + CAN->FM0R |= (u32)FilterNumber_BitPos; + } + + /* Filter FIFO assignment */ + if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO0) + { + /* FIFO 0 assignation for the filter */ + CAN->FFA0R &= ~(u32)FilterNumber_BitPos; + } + if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO1) + { + /* FIFO 1 assignation for the filter */ + CAN->FFA0R |= (u32)FilterNumber_BitPos; + } + + /* Filter activation */ + if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE) + { + CAN->FA0R |= FilterNumber_BitPos; + } + + /* Leave the initialisation mode for the filter */ + CAN->FMR &= ~CAN_FMR_FINIT; +} + +/******************************************************************************* +* Function Name : CAN_StructInit +* Description : Fills each CAN_InitStruct member with its default value. +* Input : CAN_InitStruct: pointer to a CAN_InitTypeDef structure which +* will be initialized. +* Output : None. +* Return : None. +*******************************************************************************/ +void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct) +{ + /* Reset CAN init structure parameters values */ + + /* Initialize the time triggered communication mode */ + CAN_InitStruct->CAN_TTCM = DISABLE; + + /* Initialize the automatic bus-off management */ + CAN_InitStruct->CAN_ABOM = DISABLE; + + /* Initialize the automatic wake-up mode */ + CAN_InitStruct->CAN_AWUM = DISABLE; + + /* Initialize the no automatic retransmission */ + CAN_InitStruct->CAN_NART = DISABLE; + + /* Initialize the receive FIFO locked mode */ + CAN_InitStruct->CAN_RFLM = DISABLE; + + /* Initialize the transmit FIFO priority */ + CAN_InitStruct->CAN_TXFP = DISABLE; + + /* Initialize the CAN_Mode member */ + CAN_InitStruct->CAN_Mode = CAN_Mode_Normal; + + /* Initialize the CAN_SJW member */ + CAN_InitStruct->CAN_SJW = CAN_SJW_0tq; + + /* Initialize the CAN_BS1 member */ + CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq; + + /* Initialize the CAN_BS2 member */ + CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq; + + /* Initialize the CAN_Clock member */ + CAN_InitStruct->CAN_Clock = CAN_Clock_APB; + + /* Initialize the CAN_Prescaler member */ + CAN_InitStruct->CAN_Prescaler = 1; +} + +/******************************************************************************* +* Function Name : CAN_ITConfig +* Description : Enables or disables the CAN interrupts. +* Input : - CAN_IT: specifies the CAN interrupt sources to be enabled or +* disabled. +* - NewState: new state of the CAN interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None. +* Return : None. +*******************************************************************************/ +void CAN_ITConfig(u32 CAN_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_CAN_IT(CAN_IT)); + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected CAN interrupt */ + CAN->IER |= CAN_IT; + } + else + { + /* Disable the selected CAN interrupt */ + CAN->IER &= ~CAN_IT; + } +} + +/******************************************************************************* +* Function Name : CAN_Transmit +* Description : Initiates the transmission of a message. +* Input : TxMessage: pointer to a structure which contains CAN Id, CAN +* DLC and CAN datas. +* Output : None. +* Return : The number of the mailbox that is used for transmission +* or CAN_NO_MB if there is no empty mailbox. +*******************************************************************************/ +u8 CAN_Transmit(CanTxMsg* TxMessage) +{ + u8 TransmitMailbox = 0; + + /* Check the parameters */ + assert(IS_CAN_STDID(TxMessage->StdId)); + assert(IS_CAN_EXTID(TxMessage->StdId)); + assert(IS_CAN_IDTYPE(TxMessage->IDE)); + assert(IS_CAN_RTR(TxMessage->RTR)); + assert(IS_CAN_DLC(TxMessage->DLC)); + + /* Select one empty transmit mailbox */ + if ((CAN->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) + { + TransmitMailbox = 0; + } + else if ((CAN->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) + { + TransmitMailbox = 1; + } + else if ((CAN->TSR&CAN_TSR_TME2) == CAN_TSR_TME2) + { + TransmitMailbox = 2; + } + else + { + TransmitMailbox = CAN_NO_MB; + } + + if (TransmitMailbox != CAN_NO_MB) + { + /* Set up the Id */ + TxMessage->StdId &= (u32)0x000007FF; + TxMessage->StdId = TxMessage->StdId << 21; + TxMessage->ExtId &= (u32)0x0003FFFF; + TxMessage->ExtId <<= 3; + + CAN->sTxMailBox[TransmitMailbox].TIR &= CAN_TMIDxR_TXRQ; + CAN->sTxMailBox[TransmitMailbox].TIR |= (TxMessage->StdId | TxMessage->ExtId | + TxMessage->IDE | TxMessage->RTR); + + /* Set up the DLC */ + TxMessage->DLC &= (u8)0x0000000F; + CAN->sTxMailBox[TransmitMailbox].TDTR &= (u32)0xFFFFFFF0; + CAN->sTxMailBox[TransmitMailbox].TDTR |= TxMessage->DLC; + + /* Set up the data field */ + CAN->sTxMailBox[TransmitMailbox].TDLR = (((u32)TxMessage->Data[3] << 24) | ((u32)TxMessage->Data[2] << 16) | + ((u32)TxMessage->Data[1] << 8) | ((u32)TxMessage->Data[0])); + CAN->sTxMailBox[TransmitMailbox].TDHR = (((u32)TxMessage->Data[7] << 24) | ((u32)TxMessage->Data[6] << 16) | + ((u32)TxMessage->Data[5] << 8) | ((u32)TxMessage->Data[4])); + + /* Request transmission */ + CAN->sTxMailBox[TransmitMailbox].TIR |= CAN_TMIDxR_TXRQ; + } + + return TransmitMailbox; +} + +/******************************************************************************* +* Function Name : CAN_TransmitStatus +* Description : Check the transmission of a message. +* Input : TransmitMailbox: the number of the mailbox that is used for +* transmission. +* Output : None. +* Return : CANTXOK if the CAN driver transmits the message, CANTXFAILED +* in an other case. +*******************************************************************************/ +u32 CAN_TransmitStatus(u8 TransmitMailbox) +{ + /* RQCP, TXOK and TME bits */ + u32 State = 0; + + /* Check the parameters */ + assert(IS_CAN_TRANSMITMAILBOX(TransmitMailbox)); + + switch (TransmitMailbox) + { + case (0): State |= ((CAN->TSR & CAN_TSR_RQCP0) << 2); + State |= ((CAN->TSR & CAN_TSR_TXOK0) >> 0); + State |= ((CAN->TSR & CAN_TSR_TME0) >> 26); + break; + case (1): State |= ((CAN->TSR & CAN_TSR_RQCP1) >> 6); + State |= ((CAN->TSR & CAN_TSR_TXOK1) >> 8); + State |= ((CAN->TSR & CAN_TSR_TME1) >> 27); + break; + case (2): State |= ((CAN->TSR & CAN_TSR_RQCP2) >> 14); + State |= ((CAN->TSR & CAN_TSR_TXOK2) >> 16); + State |= ((CAN->TSR & CAN_TSR_TME2) >> 28); + break; + default: + State = CANTXFAILED; + break; + } + + switch (State) + { + /* transmit pending */ + case (0x0): State = CANTXPENDING; + break; + /* transmit failed */ + case (0x5): State = CANTXFAILED; + break; + /* transmit succedeed */ + case (0x7): State = CANTXOK; + break; + default: + State = CANTXFAILED; + break; + } + + return State; +} + +/******************************************************************************* +* Function Name : CAN_CancelTransmit +* Description : Cancels a transmit request. +* Input : Mailbox number. +* Output : None. +* Return : None. +*******************************************************************************/ +void CAN_CancelTransmit(u8 Mailbox) +{ + /* Check the parameters */ + assert(IS_CAN_TRANSMITMAILBOX(Mailbox)); + + /* abort transmission */ + switch (Mailbox) + { + case (0): CAN->TSR |= CAN_TSR_ABRQ0; + break; + case (1): CAN->TSR |= CAN_TSR_ABRQ1; + break; + case (2): CAN->TSR |= CAN_TSR_ABRQ2; + break; + default: + break; + } +} + +/******************************************************************************* +* Function Name : CAN_FIFORelease +* Description : Release a FIFO. +* Input : FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1. +* Output : None. +* Return : None. +*******************************************************************************/ +void CAN_FIFORelease(u8 FIFONumber) +{ + /* Check the parameters */ + assert(IS_CAN_FIFO(FIFONumber)); + + /* Release FIFO0 */ + if (FIFONumber == CAN_FIFO0) + { + CAN->RF0R = CAN_RF0R_RFOM0; + } + /* Release FIFO1 */ + else /* FIFONumber == CAN_FIFO1 */ + { + CAN->RF1R = CAN_RF1R_RFOM1; + } +} + +/******************************************************************************* +* Function Name : CAN_MessagePending +* Description : Return the number of pending messages. +* Input : FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. +* Output : None. +* Return : NbMessage which is the number of pending message. +*******************************************************************************/ +u8 CAN_MessagePending(u8 FIFONumber) +{ + u8 MessagePending=0; + + /* Check the parameters */ + assert(IS_CAN_FIFO(FIFONumber)); + + if (FIFONumber == CAN_FIFO0) + { + MessagePending = (u8)(CAN->RF0R&(u32)0x03); + } + else if (FIFONumber == CAN_FIFO1) + { + MessagePending = (u8)(CAN->RF1R&(u32)0x03); + } + else + { + MessagePending = 0; + } + return MessagePending; +} + +/******************************************************************************* +* Function Name : CAN_Receive +* Description : Receives a message. +* Input : FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. +* Output : RxMessage: pointer to a structure which contains CAN Id, +* CAN DLC, CAN datas and FMI number. +* Return : None. +*******************************************************************************/ +void CAN_Receive(u8 FIFONumber, CanRxMsg* RxMessage) +{ + /* Check the parameters */ + assert(IS_CAN_FIFO(FIFONumber)); + + /* Get the Id */ + RxMessage->StdId = (u32)0x000007FF & (CAN->sFIFOMailBox[FIFONumber].RIR >> 21); + RxMessage->ExtId = (u32)0x0003FFFF & (CAN->sFIFOMailBox[FIFONumber].RIR >> 3); + + RxMessage->IDE = (u32)0x00000004 & CAN->sFIFOMailBox[FIFONumber].RIR; + RxMessage->RTR = (u32)0x00000002 & CAN->sFIFOMailBox[FIFONumber].RIR; + + /* Get the DLC */ + RxMessage->DLC = (u32)0x0000000F & CAN->sFIFOMailBox[FIFONumber].RDTR; + + /* Get the FMI */ + RxMessage->FMI = (u32)0x000000FF & (CAN->sFIFOMailBox[FIFONumber].RDTR >> 8); + + /* Get the data field */ + RxMessage->Data[0] = (u32)0x000000FF & CAN->sFIFOMailBox[FIFONumber].RDLR; + RxMessage->Data[1] = (u32)0x000000FF & (CAN->sFIFOMailBox[FIFONumber].RDLR >> 8); + RxMessage->Data[2] = (u32)0x000000FF & (CAN->sFIFOMailBox[FIFONumber].RDLR >> 16); + RxMessage->Data[3] = (u32)0x000000FF & (CAN->sFIFOMailBox[FIFONumber].RDLR >> 24); + + RxMessage->Data[4] = (u32)0x000000FF & CAN->sFIFOMailBox[FIFONumber].RDHR; + RxMessage->Data[5] = (u32)0x000000FF & (CAN->sFIFOMailBox[FIFONumber].RDHR >> 8); + RxMessage->Data[6] = (u32)0x000000FF & (CAN->sFIFOMailBox[FIFONumber].RDHR >> 16); + RxMessage->Data[7] = (u32)0x000000FF & (CAN->sFIFOMailBox[FIFONumber].RDHR >> 24); + + /* Release the FIFO */ + CAN_FIFORelease(FIFONumber); +} + +/******************************************************************************* +* Function Name : CAN_Sleep +* Description : Enters the low power mode. +* Input : None. +* Output : None. +* Return : CANSLEEPOK if sleep entered, CANSLEEPFAILED in an other case. +*******************************************************************************/ +u8 CAN_Sleep(void) +{ + u8 SleepStatus = 0; + + /* Sleep mode entering request */ + CAN->MCR |= CAN_MCR_SLEEP; + SleepStatus = CANSLEEPOK; + + /* Sleep mode status */ + if ((CAN->MCR&CAN_MCR_SLEEP) == 0) + { + /* Sleep mode not entered */ + SleepStatus = CANSLEEPFAILED; + } + + /* At this step, sleep mode status */ + return SleepStatus; +} + +/******************************************************************************* +* Function Name : CAN_WakeUp +* Description : Wakes the CAN up. +* Input : None. +* Output : None. +* Return : CANWAKEUPOK if sleep mode left, CANWAKEUPFAILED in an other +* case. +*******************************************************************************/ +u8 CAN_WakeUp(void) +{ + u8 WakeUpStatus = 0; + + /* Wake up request */ + CAN->MCR &= ~CAN_MCR_SLEEP; + WakeUpStatus = CANWAKEUPFAILED; + + /* Sleep mode status */ + if ((CAN->MCR&CAN_MCR_SLEEP) == 0) + { + /* Sleep mode exited */ + WakeUpStatus = CANWAKEUPOK; + } + + /* At this step, sleep mode status */ + return WakeUpStatus; +} + +/******************************************************************************* +* Function Name : CAN_GetFlagStatus +* Description : Checks whether the CAN flag is set or not. +* Input : CAN_FLAG: specifies the flag to check. +* Output : None. +* Return : The new state of CAN_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus CAN_GetFlagStatus(u32 CAN_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert(IS_CAN_FLAG(CAN_FLAG)); + + /* Check the status of the specified CAN flag */ + if ((CAN->ESR & CAN_FLAG) != (u32)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + /* Return the CAN_FLAG status */ + return bitstatus; +} + +/******************************************************************************* +* Function Name : CAN_ClearFlag +* Description : Clears the CAN's pending flags. +* Input : CAN_FLAG: specifies the flag to clear. +* Output : None. +* Return : None. +*******************************************************************************/ +void CAN_ClearFlag(u32 CAN_FLAG) +{ + /* Check the parameters */ + assert(IS_CAN_FLAG(CAN_FLAG)); + + /* Clear the selected CAN flags */ + CAN->ESR &= ~CAN_FLAG; +} + +/******************************************************************************* +* Function Name : CAN_GetITStatus +* Description : Checks whether the CAN interrupt has occurred or not. +* Input : CAN_IT: specifies the CAN interrupt source to check. +* Output : None. +* Return : The new state of CAN_IT (SET or RESET). +*******************************************************************************/ +ITStatus CAN_GetITStatus(u32 CAN_IT) +{ + ITStatus pendingbitstatus = RESET; + + /* Check the parameters */ + assert(IS_CAN_IT(CAN_IT)); + + switch (CAN_IT) + { + case CAN_IT_RQCP0: + pendingbitstatus = CheckITStatus(CAN->TSR, CAN_TSR_RQCP0); + break; + case CAN_IT_RQCP1: + pendingbitstatus = CheckITStatus(CAN->TSR, CAN_TSR_RQCP1); + break; + case CAN_IT_RQCP2: + pendingbitstatus = CheckITStatus(CAN->TSR, CAN_TSR_RQCP2); + break; + case CAN_IT_FF0: + pendingbitstatus = CheckITStatus(CAN->RF0R, CAN_RF0R_FULL0); + break; + case CAN_IT_FOV0: + pendingbitstatus = CheckITStatus(CAN->RF0R, CAN_RF0R_FOVR0); + break; + case CAN_IT_FF1: + pendingbitstatus = CheckITStatus(CAN->RF1R, CAN_RF1R_FULL1); + break; + case CAN_IT_FOV1: + pendingbitstatus = CheckITStatus(CAN->RF1R, CAN_RF1R_FOVR1); + break; + case CAN_IT_EWG: + pendingbitstatus = CheckITStatus(CAN->ESR, CAN_ESR_EWGF); + break; + case CAN_IT_EPV: + pendingbitstatus = CheckITStatus(CAN->ESR, CAN_ESR_EPVF); + break; + case CAN_IT_BOF: + pendingbitstatus = CheckITStatus(CAN->ESR, CAN_ESR_BOFF); + break; + case CAN_IT_SLK: + pendingbitstatus = CheckITStatus(CAN->MSR, CAN_MSR_SLAKI); + break; + case CAN_IT_WKU: + pendingbitstatus = CheckITStatus(CAN->MSR, CAN_MSR_WKUI); + break; + + default : + pendingbitstatus = RESET; + break; + } + + /* Return the CAN_IT status */ + return pendingbitstatus; +} + +/******************************************************************************* +* Function Name : CAN_ClearITPendingBit +* Description : Clears the CAN’s interrupt pending bits. +* Input : CAN_IT: specifies the interrupt pending bit to clear. +* Output : None. +* Return : None. +*******************************************************************************/ +void CAN_ClearITPendingBit(u32 CAN_IT) +{ + /* Check the parameters */ + assert(IS_CAN_IT(CAN_IT)); + + switch (CAN_IT) + { + case CAN_IT_RQCP0: + CAN->TSR = CAN_TSR_RQCP0; /* rc_w1*/ + break; + case CAN_IT_RQCP1: + CAN->TSR = CAN_TSR_RQCP1; /* rc_w1*/ + break; + case CAN_IT_RQCP2: + CAN->TSR = CAN_TSR_RQCP2; /* rc_w1*/ + break; + case CAN_IT_FF0: + CAN->RF0R = CAN_RF0R_FULL0; /* rc_w1*/ + break; + case CAN_IT_FOV0: + CAN->RF0R = CAN_RF0R_FOVR0; /* rc_w1*/ + break; + case CAN_IT_FF1: + CAN->RF1R = CAN_RF1R_FULL1; /* rc_w1*/ + break; + case CAN_IT_FOV1: + CAN->RF1R = CAN_RF1R_FOVR1; /* rc_w1*/ + break; + case CAN_IT_EWG: + CAN->ESR &= ~ CAN_ESR_EWGF; /* rw */ + break; + case CAN_IT_EPV: + CAN->ESR &= ~ CAN_ESR_EPVF; /* rw */ + break; + case CAN_IT_BOF: + CAN->ESR &= ~ CAN_ESR_BOFF; /* rw */ + break; + case CAN_IT_WKU: + CAN->MSR = CAN_MSR_WKUI; /* rc_w1*/ + break; + case CAN_IT_SLK: + CAN->MSR = CAN_MSR_SLAKI; /* rc_w1*/ + break; + default : + break; + } +} + +/******************************************************************************* +* Function Name : CheckITStatus +* Description : Checks whether the CAN interrupt has occurred or not. +* Input : CAN_Reg: specifies the CAN interrupt register to check. +* It_Bit: specifies the interrupt source bit to check. +* Output : None. +* Return : The new state of the CAN Interrupt (SET or RESET). +*******************************************************************************/ +static ITStatus CheckITStatus(u32 CAN_Reg, u32 It_Bit) +{ + ITStatus pendingbitstatus = RESET; + + if ((CAN_Reg & It_Bit) != (u32)RESET) + { + /* CAN_IT is set */ + pendingbitstatus = SET; + } + else + { + /* CAN_IT is reset */ + pendingbitstatus = RESET; + } + + return pendingbitstatus; +} + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_dma.c b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_dma.c new file mode 100644 index 000000000..30239b7dc --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_dma.c @@ -0,0 +1,503 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_dma.c +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file provides all the DMA firmware functions. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_dma.h" +#include "stm32f10x_rcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* DMA ENABLE mask */ +#define CCR_ENABLE_Set ((u32)0x00000001) +#define CCR_ENABLE_Reset ((u32)0xFFFFFFFE) + +/* DMA Channelx interrupt pending bit masks */ +#define DMA_Channel1_IT_Mask ((u32)0x0000000F) +#define DMA_Channel2_IT_Mask ((u32)0x000000F0) +#define DMA_Channel3_IT_Mask ((u32)0x00000F00) +#define DMA_Channel4_IT_Mask ((u32)0x0000F000) +#define DMA_Channel5_IT_Mask ((u32)0x000F0000) +#define DMA_Channel6_IT_Mask ((u32)0x00F00000) +#define DMA_Channel7_IT_Mask ((u32)0x0F000000) + +/* DMA registers Masks */ +#define CCR_CLEAR_Mask ((u32)0xFFFF800F) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : DMA_DeInit +* Description : Deinitializes the DMA Channelx registers to their default reset +* values. +* Input : - DMA_Channelx: where x can be 1, 2 to 7 to select the DMA +* Channel. +* Output : None +* Return : None +*******************************************************************************/ +void DMA_DeInit(DMA_Channel_TypeDef* DMA_Channelx) +{ + /* DMA Channelx disable */ + DMA_Cmd(DMA_Channelx, DISABLE); + + /* Reset Channelx control register */ + DMA_Channelx->CCR = 0; + + /* Reset Channelx remaining bytes register */ + DMA_Channelx->CNDTR = 0; + + /* Reset Channelx peripheral address register */ + DMA_Channelx->CPAR = 0; + + /* Reset Channelx memory address register */ + DMA_Channelx->CMAR = 0; + + switch (*(u32*)&DMA_Channelx) + { + case DMA_Channel1_BASE: + /* Reset interrupt pending bits for Channel1 */ + DMA->IFCR |= DMA_Channel1_IT_Mask; + break; + + case DMA_Channel2_BASE: + /* Reset interrupt pending bits for Channel2 */ + DMA->IFCR |= DMA_Channel2_IT_Mask; + break; + + case DMA_Channel3_BASE: + /* Reset interrupt pending bits for Channel3 */ + DMA->IFCR |= DMA_Channel3_IT_Mask; + break; + + case DMA_Channel4_BASE: + /* Reset interrupt pending bits for Channel4 */ + DMA->IFCR |= DMA_Channel4_IT_Mask; + break; + + case DMA_Channel5_BASE: + /* Reset interrupt pending bits for Channel5 */ + DMA->IFCR |= DMA_Channel5_IT_Mask; + break; + + case DMA_Channel6_BASE: + /* Reset interrupt pending bits for Channel6 */ + DMA->IFCR |= DMA_Channel6_IT_Mask; + break; + + case DMA_Channel7_BASE: + /* Reset interrupt pending bits for Channel7 */ + DMA->IFCR |= DMA_Channel7_IT_Mask; + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : DMA_Init +* Description : Initializes the DMA Channelx according to the specified +* parameters in the DMA_InitStruct. +* Input : - DMA_Channelx: where x can be 1, 2 to 7 to select the DMA +* Channel. +* - DMA_InitStruct: pointer to a DMA_InitTypeDef structure that +* contains the configuration information for the specified +* DMA Channel. +* Output : None +* Return : None +******************************************************************************/ +void DMA_Init(DMA_Channel_TypeDef* DMA_Channelx, DMA_InitTypeDef* DMA_InitStruct) +{ + u32 tmpreg = 0; + + /* Check the parameters */ + assert(IS_DMA_DIR(DMA_InitStruct->DMA_DIR)); + assert(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize)); + assert(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc)); + assert(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); + assert(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize)); + assert(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize)); + assert(IS_DMA_MODE(DMA_InitStruct->DMA_Mode)); + assert(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority)); + assert(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M)); + +/*--------------------------- DMA Channelx CCR Configuration -----------------*/ + /* Get the DMA_Channelx CCR value */ + tmpreg = DMA_Channelx->CCR; + /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRCULAR and DIR bits */ + tmpreg &= CCR_CLEAR_Mask; + /* Configure DMA Channelx: data transfer, data size, priority level and mode */ + /* Set DIR bit according to DMA_DIR value */ + /* Set CIRCULAR bit according to DMA_Mode value */ + /* Set PINC bit according to DMA_PeripheralInc value */ + /* Set MINC bit according to DMA_MemoryInc value */ + /* Set PSIZE bits according to DMA_PeripheralDataSize value */ + /* Set MSIZE bits according to DMA_MemoryDataSize value */ + /* Set PL bits according to DMA_Priority value */ + /* Set the MEM2MEM bit according to DMA_M2M value */ + tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | + DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | + DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | + DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; + /* Write to DMA Channelx CCR */ + DMA_Channelx->CCR = tmpreg; + +/*--------------------------- DMA Channelx CNBTR Configuration ---------------*/ + /* Write to DMA Channelx CNBTR */ + DMA_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize; + +/*--------------------------- DMA Channelx CPAR Configuration ----------------*/ + /* Write to DMA Channelx CPAR */ + DMA_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr; + +/*--------------------------- DMA Channelx CMAR Configuration ----------------*/ + /* Write to DMA Channelx CMAR */ + DMA_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr; +} + +/******************************************************************************* +* Function Name : DMA_StructInit +* Description : Fills each DMA_InitStruct member with its default value. +* Input : - DMA_InitStruct : pointer to a DMA_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) +{ +/*-------------- Reset DMA init structure parameters values ------------------*/ + /* Initialize the DMA_PeripheralBaseAddr member */ + DMA_InitStruct->DMA_PeripheralBaseAddr = 0; + + /* Initialize the DMA_MemoryBaseAddr member */ + DMA_InitStruct->DMA_MemoryBaseAddr = 0; + + /* Initialize the DMA_DIR member */ + DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; + + /* Initialize the DMA_BufferSize member */ + DMA_InitStruct->DMA_BufferSize = 0; + + /* Initialize the DMA_PeripheralInc member */ + DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; + + /* Initialize the DMA_MemoryInc member */ + DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; + + /* Initialize the DMA_PeripheralDataSize member */ + DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + + /* Initialize the DMA_MemoryDataSize member */ + DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + + /* Initialize the DMA_Mode member */ + DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; + + /* Initialize the DMA_Priority member */ + DMA_InitStruct->DMA_Priority = DMA_Priority_Low; + + /* Initialize the DMA_M2M member */ + DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; +} + +/******************************************************************************* +* Function Name : DMA_Cmd +* Description : Enables or disables the specified DMA Channel. +* Input : - DMA_Channelx: where x can be 1, 2 to 7 to select the DMA +* Channel. +* - NewState: new state of the DMAx Channel. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void DMA_Cmd(DMA_Channel_TypeDef* DMA_Channelx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA Channelx */ + DMA_Channelx->CCR |= CCR_ENABLE_Set; + } + else + { + /* Disable the selected DMA Channelx */ + DMA_Channelx->CCR &= CCR_ENABLE_Reset; + } +} + +/******************************************************************************* +* Function Name : DMA_ITConfig +* Description : Enables or disables the specified DMA interrupts. +* Input : - DMA_IT: specifies the DMA interrupts sources to be enabled +* or disabled. +* This parameter can be any combination of the following values: +* - DMA_IT_TC: Transfer complete interrupt mask +* - DMA_IT_HT: Half transfer interrupt mask +* - DMA_IT_TE: Transfer error interrupt mask +* - NewState: new state of the specified DMA interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void DMA_ITConfig(DMA_Channel_TypeDef* DMA_Channelx, u32 DMA_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_DMA_CONFIG_IT(DMA_IT)); + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA interrupts */ + DMA_Channelx->CCR |= DMA_IT; + } + else + { + /* Disable the selected DMA interrupts */ + DMA_Channelx->CCR &= ~DMA_IT; + } +} + +/******************************************************************************* +* Function Name : DMA_GetCurrDataCounter +* Description : Returns the number of remaining data units in the current +* DMA Channel transfer. +* Input : - DMA_Channelx: where x can be 1, 2 to 7 to select the DMA +* Channel. +* Output : None +* Return : The number of remaining data units in the current DMA Channel +* transfer.. +*******************************************************************************/ +u16 DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMA_Channelx) +{ + /* Return the current memory address value for Channelx */ + return ((u16)(DMA_Channelx->CNDTR)); +} + +/******************************************************************************* +* Function Name : DMA_GetFlagStatus +* Description : Checks whether the specified DMA flag is set or not. +* Input : - DMA_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - DMA_FLAG_GL1: Channel1 global flag. +* - DMA_FLAG_TC1: Channel1 transfer complete flag. +* - DMA_FLAG_HT1: Channel1 half transfer flag. +* - DMA_FLAG_TE1: Channel1 transfer error flag. +* - DMA_FLAG_GL2: Channel2 global flag. +* - DMA_FLAG_TC2: Channel2 transfer complete flag. +* - DMA_FLAG_HT2: Channel2 half transfer flag. +* - DMA_FLAG_TE2: Channel2 transfer error flag. +* - DMA_FLAG_GL3: Channel3 global flag. +* - DMA_FLAG_TC3: Channel3 transfer complete flag. +* - DMA_FLAG_HT3: Channel3 half transfer flag. +* - DMA_FLAG_TE3: Channel3 transfer error flag. +* - DMA_FLAG_GL4: Channel4 global flag. +* - DMA_FLAG_TC4: Channel4 transfer complete flag. +* - DMA_FLAG_HT4: Channel4 half transfer flag. +* - DMA_FLAG_TE4: Channel4 transfer error flag. +* - DMA_FLAG_GL5: Channel5 global flag. +* - DMA_FLAG_TC5: Channel5 transfer complete flag. +* - DMA_FLAG_HT5: Channel5 half transfer flag. +* - DMA_FLAG_TE5: Channel5 transfer error flag. +* - DMA_FLAG_GL6: Channel6 global flag. +* - DMA_FLAG_TC6: Channel6 transfer complete flag. +* - DMA_FLAG_HT6: Channel6 half transfer flag. +* - DMA_FLAG_TE6: Channel6 transfer error flag. +* - DMA_FLAG_GL7: Channel7 global flag. +* - DMA_FLAG_TC7: Channel7 transfer complete flag. +* - DMA_FLAG_HT7: Channel7 half transfer flag. +* - DMA_FLAG_TE7: Channel7 transfer error flag. +* Output : None +* Return : The new state of DMA_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus DMA_GetFlagStatus(u32 DMA_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert(IS_DMA_GET_FLAG(DMA_FLAG)); + + /* Check the status of the specified DMA flag */ + if ((DMA->ISR & DMA_FLAG) != (u32)RESET) + { + /* DMA_FLAG is set */ + bitstatus = SET; + } + else + { + /* DMA_FLAG is reset */ + bitstatus = RESET; + } + /* Return the DMA_FLAG status */ + return bitstatus; +} + +/******************************************************************************* +* Function Name : DMA_ClearFlag +* Description : Clears the DMA's pending flags. +* Input : - DMA_FLAG: specifies the flag to clear. +* This parameter can be any combination of the following values: +* - DMA_FLAG_GL1: Channel1 global flag. +* - DMA_FLAG_TC1: Channel1 transfer complete flag. +* - DMA_FLAG_HT1: Channel1 half transfer flag. +* - DMA_FLAG_TE1: Channel1 transfer error flag. +* - DMA_FLAG_GL2: Channel2 global flag. +* - DMA_FLAG_TC2: Channel2 transfer complete flag. +* - DMA_FLAG_HT2: Channel2 half transfer flag. +* - DMA_FLAG_TE2: Channel2 transfer error flag. +* - DMA_FLAG_GL3: Channel3 global flag. +* - DMA_FLAG_TC3: Channel3 transfer complete flag. +* - DMA_FLAG_HT3: Channel3 half transfer flag. +* - DMA_FLAG_TE3: Channel3 transfer error flag. +* - DMA_FLAG_GL4: Channel4 global flag. +* - DMA_FLAG_TC4: Channel4 transfer complete flag. +* - DMA_FLAG_HT4: Channel4 half transfer flag. +* - DMA_FLAG_TE4: Channel4 transfer error flag. +* - DMA_FLAG_GL5: Channel5 global flag. +* - DMA_FLAG_TC5: Channel5 transfer complete flag. +* - DMA_FLAG_HT5: Channel5 half transfer flag. +* - DMA_FLAG_TE5: Channel5 transfer error flag. +* - DMA_FLAG_GL6: Channel6 global flag. +* - DMA_FLAG_TC6: Channel6 transfer complete flag. +* - DMA_FLAG_HT6: Channel6 half transfer flag. +* - DMA_FLAG_TE6: Channel6 transfer error flag. +* - DMA_FLAG_GL7: Channel7 global flag. +* - DMA_FLAG_TC7: Channel7 transfer complete flag. +* - DMA_FLAG_HT7: Channel7 half transfer flag. +* - DMA_FLAG_TE7: Channel7 transfer error flag. +* Output : None +* Return : None +*******************************************************************************/ +void DMA_ClearFlag(u32 DMA_FLAG) +{ + /* Check the parameters */ + assert(IS_DMA_CLEAR_FLAG(DMA_FLAG)); + + /* Clear the selected DMA flags */ + DMA->IFCR = DMA_FLAG; +} + +/******************************************************************************* +* Function Name : DMA_GetITStatus +* Description : Checks whether the specified DMA interrupt has occurred or not. +* Input : - DMA_IT: specifies the DMA interrupt source to check. +* This parameter can be one of the following values: +* - DMA_IT_GL1: Channel1 global interrupt. +* - DMA_IT_TC1: Channel1 transfer complete interrupt. +* - DMA_IT_HT1: Channel1 half transfer interrupt. +* - DMA_IT_TE1: Channel1 transfer error interrupt. +* - DMA_IT_GL2: Channel2 global interrupt. +* - DMA_IT_TC2: Channel2 transfer complete interrupt. +* - DMA_IT_HT2: Channel2 half transfer interrupt. +* - DMA_IT_TE2: Channel2 transfer error interrupt. +* - DMA_IT_GL3: Channel3 global interrupt. +* - DMA_IT_TC3: Channel3 transfer complete interrupt. +* - DMA_IT_HT3: Channel3 half transfer interrupt. +* - DMA_IT_TE3: Channel3 transfer error interrupt. +* - DMA_IT_GL4: Channel4 global interrupt. +* - DMA_IT_TC4: Channel4 transfer complete interrupt. +* - DMA_IT_HT4: Channel4 half transfer interrupt. +* - DMA_IT_TE4: Channel4 transfer error interrupt. +* - DMA_IT_GL5: Channel5 global interrupt. +* - DMA_IT_TC5: Channel5 transfer complete interrupt. +* - DMA_IT_HT5: Channel5 half transfer interrupt. +* - DMA_IT_TE5: Channel5 transfer error interrupt. +* - DMA_IT_GL6: Channel6 global interrupt. +* - DMA_IT_TC6: Channel6 transfer complete interrupt. +* - DMA_IT_HT6: Channel6 half transfer interrupt. +* - DMA_IT_TE6: Channel6 transfer error interrupt. +* - DMA_IT_GL7: Channel7 global interrupt. +* - DMA_IT_TC7: Channel7 transfer complete interrupt. +* - DMA_IT_HT7: Channel7 half transfer interrupt. +* - DMA_IT_TE7: Channel7 transfer error interrupt. +* Output : None +* Return : The new state of DMA_IT (SET or RESET). +*******************************************************************************/ +ITStatus DMA_GetITStatus(u32 DMA_IT) +{ + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert(IS_DMA_GET_IT(DMA_IT)); + + /* Check the status of the specified DMA interrupt */ + if ((DMA->ISR & DMA_IT) != (u32)RESET) + { + /* DMA_IT is set */ + bitstatus = SET; + } + else + { + /* DMA_IT is reset */ + bitstatus = RESET; + } + /* Return the DMA_IT status */ + return bitstatus; +} + +/******************************************************************************* +* Function Name : DMA_ClearITPendingBit +* Description : Clears the DMA’s interrupt pending bits. +* Input : - DMA_IT: specifies the DMA interrupt pending bit to clear. +* This parameter can be any combination of the following values: +* - DMA_IT_GL1: Channel1 global interrupt. +* - DMA_IT_TC1: Channel1 transfer complete interrupt. +* - DMA_IT_HT1: Channel1 half transfer interrupt. +* - DMA_IT_TE1: Channel1 transfer error interrupt. +* - DMA_IT_GL2: Channel2 global interrupt. +* - DMA_IT_TC2: Channel2 transfer complete interrupt. +* - DMA_IT_HT2: Channel2 half transfer interrupt. +* - DMA_IT_TE2: Channel2 transfer error interrupt. +* - DMA_IT_GL3: Channel3 global interrupt. +* - DMA_IT_TC3: Channel3 transfer complete interrupt. +* - DMA_IT_HT3: Channel3 half transfer interrupt. +* - DMA_IT_TE3: Channel3 transfer error interrupt. +* - DMA_IT_GL4: Channel4 global interrupt. +* - DMA_IT_TC4: Channel4 transfer complete interrupt. +* - DMA_IT_HT4: Channel4 half transfer interrupt. +* - DMA_IT_TE4: Channel4 transfer error interrupt. +* - DMA_IT_GL5: Channel5 global interrupt. +* - DMA_IT_TC5: Channel5 transfer complete interrupt. +* - DMA_IT_HT5: Channel5 half transfer interrupt. +* - DMA_IT_TE5: Channel5 transfer error interrupt. +* - DMA_IT_GL6: Channel6 global interrupt. +* - DMA_IT_TC6: Channel6 transfer complete interrupt. +* - DMA_IT_HT6: Channel6 half transfer interrupt. +* - DMA_IT_TE6: Channel6 transfer error interrupt. +* - DMA_IT_GL7: Channel7 global interrupt. +* - DMA_IT_TC7: Channel7 transfer complete interrupt. +* - DMA_IT_HT7: Channel7 half transfer interrupt. +* - DMA_IT_TE7: Channel7 transfer error interrupt. +* Output : None +* Return : None +*******************************************************************************/ +void DMA_ClearITPendingBit(u32 DMA_IT) +{ + /* Check the parameters */ + assert(IS_DMA_CLEAR_IT(DMA_IT)); + + /* Clear the selected DMA interrupt pending bits */ + DMA->IFCR = DMA_IT; +} + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ + diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_exti.c b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_exti.c new file mode 100644 index 000000000..811d94bdd --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_exti.c @@ -0,0 +1,219 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_exti.c +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file provides all the EXTI firmware functions. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_exti.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define EXTI_LineNone ((u32)0x00000) /* No interrupt selected */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : EXTI_DeInit +* Description : Deinitializes the EXTI peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void EXTI_DeInit(void) +{ + EXTI->IMR = 0x00000000; + EXTI->EMR = 0x00000000; + EXTI->RTSR = 0x00000000; + EXTI->FTSR = 0x00000000; + EXTI->PR = 0x0007FFFF; +} + +/******************************************************************************* +* Function Name : EXTI_Init +* Description : Initializes the EXTI peripheral according to the specified +* parameters in the EXTI_InitStruct. +* Input : - EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure +* that contains the configuration information for the EXTI +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) +{ + /* Check the parameters */ + assert(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode)); + assert(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger)); + assert(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); + assert(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); + + if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) + { + *(u32 *)(EXTI_BASE + (u32)EXTI_InitStruct->EXTI_Mode)|= EXTI_InitStruct->EXTI_Line; + + /* Clear Rising Falling edge configuration */ + EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line; + + /* Select the trigger for the selected external interrupts */ + if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) + { + /* Rising Falling edge */ + EXTI->RTSR |= EXTI_InitStruct->EXTI_Line; + EXTI->FTSR |= EXTI_InitStruct->EXTI_Line; + } + else + { + *(u32 *)(EXTI_BASE + (u32)EXTI_InitStruct->EXTI_Trigger)|= EXTI_InitStruct->EXTI_Line; + } + } + else + { + /* Disable the selected external lines */ + *(u32 *)(EXTI_BASE + (u32)EXTI_InitStruct->EXTI_Mode)&= ~EXTI_InitStruct->EXTI_Line; + } +} + +/******************************************************************************* +* Function Name : EXTI_StructInit +* Description : Fills each EXTI_InitStruct member with its reset value. +* Input : - EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct) +{ + EXTI_InitStruct->EXTI_Line = EXTI_LineNone; + EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; + EXTI_InitStruct->EXTI_LineCmd = DISABLE; +} + +/******************************************************************************* +* Function Name : EXTI_GenerateSWInterrupt +* Description : Generates a Software interrupt. +* Input : - EXTI_Line: specifies the EXTI lines to be enabled or +* disabled. +* This parameter can be: +* - EXTI_Linex: External interrupt line x where x(0..18) +* Output : None +* Return : None +*******************************************************************************/ +void EXTI_GenerateSWInterrupt(u32 EXTI_Line) +{ + /* Check the parameters */ + assert(IS_EXTI_LINE(EXTI_Line)); + + EXTI->SWIER |= EXTI_Line; +} + +/******************************************************************************* +* Function Name : EXTI_GetFlagStatus +* Description : Checks whether the specified EXTI line flag is set or not. +* Input : - EXTI_Line: specifies the EXTI lines flag to check. +* This parameter can be: +* - EXTI_Linex: External interrupt line x where x(0..18) +* Output : None +* Return : The new state of EXTI_Line (SET or RESET). +*******************************************************************************/ +FlagStatus EXTI_GetFlagStatus(u32 EXTI_Line) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert(IS_GET_EXTI_LINE(EXTI_Line)); + + if ((EXTI->PR & EXTI_Line) != (u32)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : EXTI_ClearFlag +* Description : Clears the EXTI’s line pending flags. +* Input : - EXTI_Line: specifies the EXTI lines flags to clear. +* This parameter can be: +* - EXTI_Linex: External interrupt line x where x(0..18) +* Output : None +* Return : None +*******************************************************************************/ +void EXTI_ClearFlag(u32 EXTI_Line) +{ + /* Check the parameters */ + assert(IS_EXTI_LINE(EXTI_Line)); + + EXTI->PR = EXTI_Line; +} + +/******************************************************************************* +* Function Name : EXTI_GetITStatus +* Description : Checks whether the specified EXTI line is asserted or not. +* Input : - EXTI_Line: specifies the EXTI lines to check. +* This parameter can be: +* - EXTI_Linex: External interrupt line x where x(0..18) +* Output : None +* Return : The new state of EXTI_Line (SET or RESET). +*******************************************************************************/ +ITStatus EXTI_GetITStatus(u32 EXTI_Line) +{ + ITStatus bitstatus = RESET; + u32 enablestatus = 0; + + /* Check the parameters */ + assert(IS_GET_EXTI_LINE(EXTI_Line)); + + enablestatus = EXTI->IMR & EXTI_Line; + + if (((EXTI->PR & EXTI_Line) != (u32)RESET) && enablestatus) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : EXTI_ClearITPendingBit +* Description : Clears the EXTI’s line pending bits. +* Input : - EXTI_Line: specifies the EXTI lines to clear. +* This parameter can be: +* - EXTI_Linex: External interrupt line x where x(0..18) +* Output : None +* Return : None +*******************************************************************************/ +void EXTI_ClearITPendingBit(u32 EXTI_Line) +{ + /* Check the parameters */ + assert(IS_EXTI_LINE(EXTI_Line)); + + EXTI->PR = EXTI_Line; +} + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_gpio.c b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_gpio.c new file mode 100644 index 000000000..571a00d69 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_gpio.c @@ -0,0 +1,515 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_gpio.c +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file provides all the GPIO firmware functions. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_gpio.h" +#include "stm32f10x_rcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* ------------ RCC registers bit address in the alias region ----------- */ +#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE) + +/* --- EVENTCR Register ---*/ +/* Alias word address of EVOE bit */ +#define EVCR_OFFSET (AFIO_OFFSET + 0x00) +#define EVOE_BitNumber ((u8)0x07) +#define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4)) + +#define EVCR_PORTPINCONFIG_MASK ((u16)0xFF80) +#define LSB_MASK ((u16)0xFFFF) +#define DBGAFR_POSITION_MASK ((u32)0x000F0000) +#define DBGAFR_SWJCFG_MASK ((u32)0xF8FFFFFF) +#define DBGAFR_LOCATION_MASK ((u32)0x00200000) +#define DBGAFR_NUMBITS_MASK ((u32)0x00100000) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : GPIO_DeInit +* Description : Deinitializes the GPIOx peripheral registers to their default +* reset values. +* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_DeInit(GPIO_TypeDef* GPIOx) +{ + switch (*(u32*)&GPIOx) + { + case GPIOA_BASE: + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE); + break; + + case GPIOB_BASE: + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE); + break; + + case GPIOC_BASE: + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE); + break; + + case GPIOD_BASE: + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE); + break; + + case GPIOE_BASE: + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : GPIO_AFIODeInit +* Description : Deinitializes the Alternate Functions (remap, event control +* and EXTI configuration) registers to their default reset +* values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_AFIODeInit(void) +{ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE); +} + +/******************************************************************************* +* Function Name : GPIO_Init +* Description : Initializes the GPIOx peripheral according to the specified +* parameters in the GPIO_InitStruct. +* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral. +* - GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that +* contains the configuration information for the specified GPIO +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) +{ + u32 currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; + u32 tmpreg = 0x00, pinmask = 0x00; + + /* Check the parameters */ + assert(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); + assert(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); + +/*---------------------------- GPIO Mode Configuration -----------------------*/ + currentmode = ((u32)GPIO_InitStruct->GPIO_Mode) & ((u32)0x0F); + + if ((((u32)GPIO_InitStruct->GPIO_Mode) & ((u32)0x10)) != 0x00) + { + /* Check the parameters */ + assert(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); + /* Output mode */ + currentmode |= (u32)GPIO_InitStruct->GPIO_Speed; + } + +/*---------------------------- GPIO CRL Configuration ------------------------*/ + /* Configure the eight low port pins */ + if (((u32)GPIO_InitStruct->GPIO_Pin & ((u32)0x00FF)) != 0x00) + { + tmpreg = GPIOx->CRL; + + for (pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = ((u32)0x01) << pinpos; + /* Get the port pins position */ + currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; + + if (currentpin == pos) + { + pos = pinpos << 2; + /* Clear the corresponding low control register bits */ + pinmask = ((u32)0x0F) << pos; + tmpreg &= ~pinmask; + + /* Write the mode configuration in the corresponding bits */ + tmpreg |= (currentmode << pos); + + /* Reset the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BRR = (((u32)0x01) << pinpos); + } + /* Set the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSRR = (((u32)0x01) << pinpos); + } + } + } + GPIOx->CRL = tmpreg; + tmpreg = 0; + } + +/*---------------------------- GPIO CRH Configuration ------------------------*/ + /* Configure the eight high port pins */ + if (GPIO_InitStruct->GPIO_Pin > 0x00FF) + { + tmpreg = GPIOx->CRH; + for (pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = (((u32)0x01) << (pinpos + 0x08)); + /* Get the port pins position */ + currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); + if (currentpin == pos) + { + pos = pinpos << 2; + /* Clear the corresponding high control register bits */ + pinmask = ((u32)0x0F) << pos; + tmpreg &= ~pinmask; + + /* Write the mode configuration in the corresponding bits */ + tmpreg |= (currentmode << pos); + + /* Reset the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BRR = (((u32)0x01) << (pinpos + 0x08)); + } + /* Set the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSRR = (((u32)0x01) << (pinpos + 0x08)); + } + } + } + GPIOx->CRH = tmpreg; + } +} + +/******************************************************************************* +* Function Name : GPIO_StructInit +* Description : Fills each GPIO_InitStruct member with its default value. +* Input : - GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) +{ + /* Reset GPIO init structure parameters values */ + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; + GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; +} + +/******************************************************************************* +* Function Name : GPIO_ReadInputDataBit +* Description : Reads the specified input port pin. +* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral. +* : - GPIO_Pin: specifies the port bit to read. +* This parameter can be GPIO_Pin_x where x can be (0..15). +* Output : None +* Return : The input port pin value. +*******************************************************************************/ +u8 GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin) +{ + u8 bitstatus = 0x00; + + /* Check the parameters */ + assert(IS_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->IDR & GPIO_Pin) != (u32)Bit_RESET) + { + bitstatus = (u8)Bit_SET; + } + else + { + bitstatus = (u8)Bit_RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : GPIO_ReadInputData +* Description : Reads the specified GPIO input data port. +* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral. +* Output : None +* Return : GPIO input data port value. +*******************************************************************************/ +u16 GPIO_ReadInputData(GPIO_TypeDef* GPIOx) +{ + return ((u16)GPIOx->IDR); +} + +/******************************************************************************* +* Function Name : GPIO_ReadOutputDataBit +* Description : Reads the specified output data port bit. +* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral. +* : - GPIO_Pin: specifies the port bit to read. +* This parameter can be GPIO_Pin_x where x can be (0..15). +* Output : None +* Return : The output port pin value. +*******************************************************************************/ +u8 GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin) +{ + u8 bitstatus = 0x00; + + /* Check the parameters */ + assert(IS_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->ODR & GPIO_Pin) != (u32)Bit_RESET) + { + bitstatus = (u8)Bit_SET; + } + else + { + bitstatus = (u8)Bit_RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : GPIO_ReadOutputData +* Description : Reads the specified GPIO output data port. +* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral. +* Output : None +* Return : GPIO output data port value. +*******************************************************************************/ +u16 GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) +{ + return ((u16)GPIOx->ODR); +} + +/******************************************************************************* +* Function Name : GPIO_WriteBit +* Description : Sets or clears the selected data port bit. +* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral. +* - GPIO_Pin: specifies the port bit to be written. +* This parameter can be GPIO_Pin_x where x can be (0..15). +* - BitVal: specifies the value to be written to the selected bit. +* This parameter can be one of the BitAction enum values: +* - Bit_RESET: to clear the port pin +* - Bit_SET: to set the port pin +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin, BitAction BitVal) +{ + /* Check the parameters */ + assert(IS_GPIO_PIN(GPIO_Pin)); + assert(IS_GPIO_BIT_ACTION(BitVal)); + + if (BitVal != Bit_RESET) + { + GPIOx->BSRR = GPIO_Pin; + } + else + { + GPIOx->BRR = GPIO_Pin; + } +} + +/******************************************************************************* +* Function Name : GPIO_Write +* Description : Writes data to the specified GPIO data port. +* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral. +* - PortVal: specifies the value to be written to the port output +* data register. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_Write(GPIO_TypeDef* GPIOx, u16 PortVal) +{ + GPIOx->ODR = PortVal; +} + +/******************************************************************************* +* Function Name : GPIO_PinLockConfig +* Description : Locks GPIO Pins configuration registers. +* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral. +* - GPIO_Pin: specifies the port bit to be written. +* This parameter can be GPIO_Pin_x where x can be (0..15). +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, u16 GPIO_Pin) +{ + u32 tmp = 0x00010000; + + /* Check the parameters */ + assert(IS_GPIO_PIN(GPIO_Pin)); + + tmp |= GPIO_Pin; + /* Set LCKK bit */ + GPIOx->LCKR = tmp; + /* Reset LCKK bit */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKK bit */ + GPIOx->LCKR = tmp; + /* Read LCKK bit*/ + tmp = GPIOx->LCKR; + /* Read LCKK bit*/ + tmp = GPIOx->LCKR; +} + +/******************************************************************************* +* Function Name : GPIO_EventOutputConfig +* Description : Selects the GPIO pin used as Event output. +* Input : - GPIO_PortSource: selects the GPIO port to be used as source +* for Event output. +* This parameter can be GPIO_PortSourceGPIOx where x can be +* (A..E). +* - GPIO_PinSource: specifies the pin for the Event output. +* This parameter can be GPIO_PinSourcex where x can be (0..15). +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_EventOutputConfig(u8 GPIO_PortSource, u8 GPIO_PinSource) +{ + u32 tmpreg = 0x00; + + /* Check the parameters */ + assert(IS_GPIO_PORT_SOURCE(GPIO_PortSource)); + assert(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); + + tmpreg = AFIO->EVCR; + /* Clear the PORT[6:4] and PIN[3:0] bits */ + tmpreg &= EVCR_PORTPINCONFIG_MASK; + tmpreg |= (u32)GPIO_PortSource << 0x04; + tmpreg |= GPIO_PinSource; + + AFIO->EVCR = tmpreg; +} + +/******************************************************************************* +* Function Name : GPIO_EventOutputCmd +* Description : Enables or disables the Event Output. +* Input : - NewState: new state of the Event output. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_EventOutputCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + *(vu32 *) EVCR_EVOE_BB = (u32)NewState; +} + +/******************************************************************************* +* Function Name : GPIO_PinRemapConfig +* Description : Changes the mapping of the specified pin. +* Input : - GPIO_Remap: selects the pin to remap. +* This parameter can be one of the following values: +* - GPIO_Remap_SPI1 +* - GPIO_Remap_I2C1 +* - GPIO_Remap_USART1 +* - GPIO_Remap_USART2 +* - GPIO_PartialRemap_USART3 +* - GPIO_FullRemap_USART3 +* - GPIO_PartialRemap_TIM1 +* - GPIO_FullRemap_TIM1 +* - GPIO_PartialRemap1_TIM2 +* - GPIO_PartialRemap2_TIM2 +* - GPIO_FullRemap_TIM2 +* - GPIO_PartialRemap_TIM3 +* - GPIO_FullRemap_TIM3 +* - GPIO_Remap_TIM4 +* - GPIO_Remap1_CAN +* - GPIO_Remap2_CAN +* - GPIO_Remap_PD01 +* - GPIO_Remap_SWJ_NoJTRST +* - GPIO_Remap_SWJ_JTAGDisable +* - GPIO_Remap_SWJ_Disable +* - NewState: new state of the port pin remapping. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_PinRemapConfig(u32 GPIO_Remap, FunctionalState NewState) +{ + u32 tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00; + + /* Check the parameters */ + assert(IS_GPIO_REMAP(GPIO_Remap)); + assert(IS_FUNCTIONAL_STATE(NewState)); + + tmpreg = AFIO->MAPR; + + tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10; + tmp = GPIO_Remap & LSB_MASK; + + if ((GPIO_Remap & DBGAFR_LOCATION_MASK) == DBGAFR_LOCATION_MASK) + { + tmpreg &= DBGAFR_SWJCFG_MASK; + } + else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) + { + tmp1 = ((u32)0x03) << tmpmask; + tmpreg &= ~tmp1; + } + else + { + tmpreg &= ~tmp; + } + + if (NewState != DISABLE) + { + if ((GPIO_Remap & DBGAFR_LOCATION_MASK) == DBGAFR_LOCATION_MASK) + { + tmpreg |= (tmp << 0x10); + } + else + { + tmpreg |= tmp; + } + } + AFIO->MAPR = tmpreg; +} + +/******************************************************************************* +* Function Name : GPIO_EXTILineConfig +* Description : Selects the GPIO pin used as EXTI Line. +* Input : - GPIO_PortSource: selects the GPIO port to be used as +* source for EXTI lines. +* - GPIO_PinSource: specifies the EXTI line to be configured. +* This parameter can be GPIO_PinSourcex where x can be (0..15). +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_EXTILineConfig(u8 GPIO_PortSource, u8 GPIO_PinSource) +{ + u32 tmp = 0x00; + + /* Check the parameters */ + assert(IS_GPIO_PORT_SOURCE(GPIO_PortSource)); + assert(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); + + tmp = ((u32)0x0F) << (0x04 * (GPIO_PinSource & (u8)0x03)); + + AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp; + AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((u32)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (u8)0x03))); +} + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_i2c.c b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_i2c.c new file mode 100644 index 000000000..2809b83c9 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_i2c.c @@ -0,0 +1,1186 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_i2c.c +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file provides all the I2C firmware functions. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_i2c.h" +#include "stm32f10x_rcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* I2C SPE mask */ +#define CR1_PE_Set ((u16)0x0001) +#define CR1_PE_Reset ((u16)0xFFFE) + +/* I2C DMAEN mask */ +#define CR2_DMAEN_Set ((u16)0x0800) +#define CR2_DMAEN_Reset ((u16)0xF7FF) + +/* I2C LAST mask */ +#define CR2_LAST_Set ((u16)0x1000) +#define CR2_LAST_Reset ((u16)0xEFFF) + +/* I2C START mask */ +#define CR1_START_Set ((u16)0x0100) +#define CR1_START_Reset ((u16)0xFEFF) + +/* I2C STOP mask */ +#define CR1_STOP_Set ((u16)0x0200) +#define CR1_STOP_Reset ((u16)0xFDFF) + +/* I2C ACK mask */ +#define CR1_ACK_Set ((u16)0x0400) +#define CR1_ACK_Reset ((u16)0xFBFF) + +/* I2C ENGC mask */ +#define CR1_ENGC_Set ((u16)0x0040) +#define CR1_ENGC_Reset ((u16)0xFFBF) + +/* I2C ADD0 mask */ +#define OAR1_ADD0_Set ((u16)0x0001) +#define OAR1_ADD0_Reset ((u16)0xFFFE) + +/* I2C SWRST mask */ +#define CR1_SWRST_Set ((u16)0x8000) +#define CR1_SWRST_Reset ((u16)0x7FFF) + +/* I2C PEC mask */ +#define CR1_PEC_Set ((u16)0x1000) + +/* I2C ENPEC mask */ +#define CR1_ENPEC_Set ((u16)0x0020) +#define CR1_ENPEC_Reset ((u16)0xFFDF) + +/* I2C ENARP mask */ +#define CR1_ENARP_Set ((u16)0x0010) +#define CR1_ENARP_Reset ((u16)0xFFEF) + +/* I2C NOSTRETCH mask */ +#define CR1_NOSTRETCH_Set ((u16)0x0080) +#define CR1_NOSTRETCH_Reset ((u16)0xFF7F) + +/* I2C ENDUAL mask */ +#define OAR2_ENDUAL_Set ((u16)0x0001) +#define OAR2_ENDUAL_Reset ((u16)0xFFFE) + +/* I2C F/S mask */ +#define CCR_FS_Set ((u16)0x8000) + +/* I2C ADD2 mask */ +#define OAR2_ADD2_Reset ((u16)0xFF01) + +/* I2C FREQ mask */ +#define CR2_FREQ_Reset ((u16)0xFFC0) + +/* I2C CCR mask */ +#define CCR_CCR_Set ((u16)0x0FFF) + +/* I2C FLAG mask */ +#define I2C_FLAG_Mask ((u32)0x00FFFFFF) + +/* I2C registers Masks */ +#define CR1_CLEAR_Mask ((u16)0xFBF5) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : I2C_DeInit +* Description : Deinitializes the I2Cx peripheral registers to their default +* reset values. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void I2C_DeInit(I2C_TypeDef* I2Cx) +{ + switch (*(u32*)&I2Cx) + { + case I2C1_BASE: + /* Enable I2C1 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE); + /* Release I2C1 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE); + break; + + case I2C2_BASE: + /* Enable I2C2 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE); + /* Release I2C2 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : I2C_Init +* Description : Initializes the I2Cx according to the specified parameters +* in the I2C_InitStruct. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - I2C_InitStruct: pointer to a I2C_InitTypeDef structure that +* contains the configuration information for the specified +* I2C peripheral. +* Output : None +* Return : None +******************************************************************************/ +void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct) +{ + u16 tmpreg = 0, freqrange = 0; + u16 result = 0x04; + u32 pclk1clock = 12000000; + RCC_ClocksTypeDef RCC_Clocks; + + /* Check the parameters */ + assert(IS_I2C_MODE(I2C_InitStruct->I2C_Mode)); + assert(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle)); + assert(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1)); + assert(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack)); + assert(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress)); + assert(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed)); + +/*---------------------------- I2Cx CR2 Configuration ------------------------*/ + /* Get the I2Cx CR2 value */ + tmpreg = I2Cx->CR2; + /* Clear frequency FREQ[5:0] bits */ + tmpreg &= CR2_FREQ_Reset; + /* Get PCLK1Clock frequency value */ + RCC_GetClocksFreq(&RCC_Clocks); + pclk1clock = RCC_Clocks.PCLK1_Frequency; + /* Set frequency bits depending on PCLK1Clock value */ + freqrange = (u16)(pclk1clock / 1000000); + tmpreg |= freqrange; + /* Write to I2Cx CR2 */ + I2Cx->CR2 = tmpreg; + +/*---------------------------- I2Cx CCR Configuration ------------------------*/ + /* Disable I2Cx to configure TRISE */ + I2C_Cmd(I2Cx, DISABLE); + + /* Reset tmpreg value */ + /* Clear F/S, DUTY and CCR[11:0] bits */ + tmpreg = 0; + + /* Configure speed in standard mode */ + if (I2C_InitStruct->I2C_ClockSpeed <= 100000) + { + /* Standard mode speed calculate */ + result = (u16)(pclk1clock / (I2C_InitStruct->I2C_ClockSpeed << 1)); + /* Test if CCR value is under 0x4*/ + if (result < 0x04) + { + /* Set minimum allowed value */ + result = 0x04; + } + /* Set speed value for standard mode */ + tmpreg |= result; + /* Set Maximum Rise Time: ((1000/(1000000000/pclk1clock))+1 */ + I2Cx->TRISE = freqrange + 1; + } + /* Configure speed in fast mode */ + else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/ + { + if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2) + { + /* Fast mode speed calculate: Tlow/Thigh = 2 */ + result = (u16)(pclk1clock / (I2C_InitStruct->I2C_ClockSpeed * 3)); + } + else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/ + { + /* Fast mode speed calculate: Tlow/Thigh = 16/9 */ + result = (u16)(pclk1clock / (I2C_InitStruct->I2C_ClockSpeed * 25)); + /* Set DUTY bit */ + result |= I2C_DutyCycle_16_9; + } + /* Test if CCR value is under 0x1*/ + if ((result & CCR_CCR_Set) == 0) + { + /* Set minimum allowed value */ + result |= (u16)0x0001; + } + /* Set speed value and set F/S bit for fast mode */ + tmpreg |= result | CCR_FS_Set; + /* Set Maximum Rise Time: ((300/(1000000000/pclk1clock))+1 */ + I2Cx->TRISE = (u16)(((freqrange * 300) / 1000) + 1); + } + /* Write to I2Cx CCR */ + I2Cx->CCR = tmpreg; + + /* Enable I2Cx */ + I2C_Cmd(I2Cx, ENABLE); + +/*---------------------------- I2Cx CR1 Configuration ------------------------*/ + /* Get the I2Cx CR1 value */ + tmpreg = I2Cx->CR1; + /* Clear ACK, SMBTYPE and SMBUS bits */ + tmpreg &= CR1_CLEAR_Mask; + /* Configure I2Cx: mode and acknowledgement */ + /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */ + /* Set ACK bit according to I2C_Ack value */ + tmpreg |= (u16)((u32)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); + /* Write to I2Cx CR1 */ + I2Cx->CR1 = tmpreg; + +/*---------------------------- I2Cx OAR1 Configuration -----------------------*/ + /* Set I2Cx Own Address1 and acknowledged address */ + I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); +} + +/******************************************************************************* +* Function Name : I2C_StructInit +* Description : Fills each I2C_InitStruct member with its default value. +* Input : - I2C_InitStruct: pointer to a I2C_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct) +{ +/*---------------- Reset I2C init structure parameters values ----------------*/ + /* Initialize the I2C_Mode member */ + I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; + + /* Initialize the I2C_DutyCycle member */ + I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; + + /* Initialize the I2C_OwnAddress1 member */ + I2C_InitStruct->I2C_OwnAddress1 = 0; + + /* Initialize the I2C_Ack member */ + I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; + + /* Initialize the I2C_AcknowledgedAddress member */ + I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; + + /* initialize the I2C_ClockSpeed member */ + I2C_InitStruct->I2C_ClockSpeed = 5000; +} + +/******************************************************************************* +* Function Name : I2C_Cmd +* Description : Enables or disables the specified I2C peripheral. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - NewState: new state of the I2Cx peripheral. This parameter +* can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected I2C peripheral */ + I2Cx->CR1 |= CR1_PE_Set; + } + else + { + /* Disable the selected I2C peripheral */ + I2Cx->CR1 &= CR1_PE_Reset; + } +} + +/******************************************************************************* +* Function Name : I2C_DMACmd +* Description : Enables or disables the specified I2C DMA requests. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - NewState: new state of the I2C DMA transfer. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected I2C DMA requests */ + I2Cx->CR2 |= CR2_DMAEN_Set; + } + else + { + /* Disable the selected I2C DMA requests */ + I2Cx->CR2 &= CR2_DMAEN_Reset; + } +} + +/******************************************************************************* +* Function Name : I2C_DMALastTransferCmd +* Description : Specifies that the next DMA transfer is the last one. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - NewState: new state of the I2C DMA last transfer. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Next DMA end of transfer is the last transfer */ + I2Cx->CR2 |= CR2_LAST_Set; + } + else + { + /* Next DMA end of transfer is not the last transfer */ + I2Cx->CR2 &= CR2_LAST_Reset; + } +} + +/******************************************************************************* +* Function Name : I2C_GenerateSTART +* Description : Generates I2Cx communication START condition. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - NewState: new state of the I2C START condition generation. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Generate a START condition */ + I2Cx->CR1 |= CR1_START_Set; + } + else + { + /* Disable the START condition generation */ + I2Cx->CR1 &= CR1_START_Reset; + } +} + +/******************************************************************************* +* Function Name : I2C_GenerateSTOP +* Description : Generates I2Cx communication STOP condition. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - NewState: new state of the I2C STOP condition generation. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Generate a STOP condition */ + I2Cx->CR1 |= CR1_STOP_Set; + } + else + { + /* Disable the STOP condition generation */ + I2Cx->CR1 &= CR1_STOP_Reset; + } +} + +/******************************************************************************* +* Function Name : I2C_AcknowledgeConfig +* Description : Enables or disables the specified I2C acknowledge feature. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - NewState: new state of the I2C Acknowledgement. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the acknowledgement */ + I2Cx->CR1 |= CR1_ACK_Set; + } + else + { + /* Disable the acknowledgement */ + I2Cx->CR1 &= CR1_ACK_Reset; + } +} + +/******************************************************************************* +* Function Name : I2C_OwnAddress2Config +* Description : Configures the specified I2C own address2. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - Address: specifies the 7bit I2C own address2. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, u8 Address) +{ + u16 tmpreg = 0; + + /* Get the old register value */ + tmpreg = I2Cx->OAR2; + /* Reset I2Cx Own address2 bit [7:1] */ + tmpreg &= OAR2_ADD2_Reset; + /* Set I2Cx Own address2 */ + tmpreg |= (u16)(Address & (u16)0x00FE); + /* Store the new register value */ + I2Cx->OAR2 = tmpreg; +} + +/******************************************************************************* +* Function Name : I2C_DualAddressCmd +* Description : Enables or disables the specified I2C dual addressing mode. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - NewState: new state of the I2C dual addressing mode. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable dual addressing mode */ + I2Cx->OAR2 |= OAR2_ENDUAL_Set; + } + else + { + /* Disable dual addressing mode */ + I2Cx->OAR2 &= OAR2_ENDUAL_Reset; + } +} + +/******************************************************************************* +* Function Name : I2C_GeneralCallCmd +* Description : Enables or disables the specified I2C general call feature. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - NewState: new state of the I2C General call. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable generall call */ + I2Cx->CR1 |= CR1_ENGC_Set; + } + else + { + /* Disable generall call */ + I2Cx->CR1 &= CR1_ENGC_Reset; + } +} + +/******************************************************************************* +* Function Name : I2C_ITConfig +* Description : Enables or disables the specified I2C interrupts. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - I2C_IT: specifies the I2C interrupts sources to be enabled +* or disabled. +* This parameter can be any combination of the following values: +* - I2C_IT_BUF: Buffer interrupt mask +* - I2C_IT_EVT: Event interrupt mask +* - I2C_IT_ERR: Error interrupt mask +* - NewState: new state of the specified I2C interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void I2C_ITConfig(I2C_TypeDef* I2Cx, u16 I2C_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + assert(IS_I2C_CONFIG_IT(I2C_IT)); + + if (NewState != DISABLE) + { + /* Enable the selected I2C interrupts */ + I2Cx->CR2 |= I2C_IT; + } + else + { + /* Disable the selected I2C interrupts */ + I2Cx->CR2 &= (u16)~I2C_IT; + } +} + +/******************************************************************************* +* Function Name : I2C_SendData +* Description : Sends a data byte through the I2Cx peripheral. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - Data: Byte to be transmitted.. +* Output : None +* Return : None +*******************************************************************************/ +void I2C_SendData(I2C_TypeDef* I2Cx, u8 Data) +{ + /* Write in the DR register the data to be sent */ + I2Cx->DR = Data; +} + +/******************************************************************************* +* Function Name : I2C_ReceiveData +* Description : Returns the most recent received data by the I2Cx peripheral. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* Output : None +* Return : The value of the received data. +*******************************************************************************/ +u8 I2C_ReceiveData(I2C_TypeDef* I2Cx) +{ + /* Return the data in the DR register */ + return (u8)I2Cx->DR; +} + +/******************************************************************************* +* Function Name : I2C_Send7bitAddress +* Description : Transmits the address byte to select the slave device. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - Address: specifies the slave address which will be transmitted +* - Direction: specifies whether the I2C device will be a +* Transmitter or a Receiver. +* This parameter can be one of the following values +* - I2C_Direction_Transmitter: Transmitter mode +* - I2C_Direction_Receiver: Receiver mode +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, u8 Address, u8 I2C_Direction) +{ + /* Check the parameters */ + assert(IS_I2C_DIRECTION(I2C_Direction)); + + /* Test on the direction to set/reset the read/write bit */ + if (I2C_Direction != I2C_Direction_Transmitter) + { + /* Set the address ADD0 bit0 for read */ + Address |= OAR1_ADD0_Set; + } + else + { + /* Reset the address bit0 for write */ + Address &= OAR1_ADD0_Reset; + } + /* Send the address */ + I2Cx->DR = Address; +} + +/******************************************************************************* +* Function Name : I2C_ReadRegister +* Description : Reads the specified I2C register and returns its value. +* Input1 : - I2C_Register: specifies the register to read. +* This parameter can be one of the following values: +* - I2C_Register_CR1: CR1 register. +* - I2C_Register_CR2: CR2 register. +* - I2C_Register_OAR1: OAR1 register. +* - I2C_Register_OAR2: OAR2 register. +* - I2C_Register_DR: DR register. +* - I2C_Register_SR1: SR1 register. +* - I2C_Register_SR2: SR2 register. +* - I2C_Register_CCR: CCR register. +* - I2C_Register_TRISE: TRISE register. +* Output : None +* Return : The value of the read register. +*******************************************************************************/ +u16 I2C_ReadRegister(I2C_TypeDef* I2Cx, u8 I2C_Register) +{ + /* Check the parameters */ + assert(IS_I2C_REGISTER(I2C_Register)); + + /* Return the selected register value */ + return (*(u16 *)(*((u32 *)&I2Cx) + I2C_Register)); +} + +/******************************************************************************* +* Function Name : I2C_SoftwareResetCmd +* Description : Enables or disables the specified I2C software reset. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - NewState: new state of the I2C software reset. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Peripheral under reset */ + I2Cx->CR1 |= CR1_SWRST_Set; + } + else + { + /* Peripheral not under reset */ + I2Cx->CR1 &= CR1_SWRST_Reset; + } +} + +/******************************************************************************* +* Function Name : I2C_SMBusAlertConfig +* Description : Drives the SMBusAlert pin high or low for the specified I2C. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - I2C_SMBusAlert: specifies SMBAlert pin level. +* This parameter can be one of the following values: +* - I2C_SMBusAlert_Low: SMBAlert pin driven low +* - I2C_SMBusAlert_High: SMBAlert pin driven high +* Output : None +* Return : None +*******************************************************************************/ +void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, u16 I2C_SMBusAlert) +{ + /* Check the parameters */ + assert(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert)); + + if (I2C_SMBusAlert == I2C_SMBusAlert_Low) + { + /* Drive the SMBusAlert pin Low */ + I2Cx->CR1 |= I2C_SMBusAlert_Low; + } + else + { + /* Drive the SMBusAlert pin High */ + I2Cx->CR1 &= I2C_SMBusAlert_High; + } +} + +/******************************************************************************* +* Function Name : I2C_TransmitPEC +* Description : Enables the specified I2C PEC transfer. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void I2C_TransmitPEC(I2C_TypeDef* I2Cx) +{ + /* Enable the selected I2C PEC transmission */ + I2Cx->CR1 |= CR1_PEC_Set; +} + +/******************************************************************************* +* Function Name : I2C_PECPositionConfig +* Description : Selects the specified I2C PEC position. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - I2C_PECPosition: specifies the PEC position. +* This parameter can be one of the following values: +* - I2C_PECPosition_Next: PEC bit indicates that current +* byte is PEC +* - I2C_PECPosition_Current: PEC bit indicates that the +* next byte is PEC +* Output : None +* Return : None +*******************************************************************************/ +void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, u16 I2C_PECPosition) +{ + /* Check the parameters */ + assert(IS_I2C_PEC_POSITION(I2C_PECPosition)); + + if (I2C_PECPosition == I2C_PECPosition_Next) + { + /* PEC indicates that the next byte in shift register is PEC */ + I2Cx->CR1 |= I2C_PECPosition_Next; + } + else + { + /* PEC indicates that the current byte in shift register is PEC */ + I2Cx->CR1 &= I2C_PECPosition_Current; + } +} + +/******************************************************************************* +* Function Name : I2C_CalculatePEC +* Description : Enables or disables the PEC value calculation of the +* transfered bytes. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - NewState: new state of the I2Cx PEC value calculation. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected I2C PEC calculation */ + I2Cx->CR1 |= CR1_ENPEC_Set; + } + else + { + /* Disable the selected I2C PEC calculation */ + I2Cx->CR1 &= CR1_ENPEC_Reset; + } +} + +/******************************************************************************* +* Function Name : I2C_GetPEC +* Description : Returns the PEC value for the specified I2C. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* Output : None +* Return : The PEC value. +*******************************************************************************/ +u8 I2C_GetPEC(I2C_TypeDef* I2Cx) +{ + u8 pec; + + /* Get the PEC value */ + pec = (I2Cx->SR2) >> 8; + /* Return the selected I2C PEC register value */ + return pec; +} + +/******************************************************************************* +* Function Name : I2C_ARPCmd +* Description : Enables or disables the specified I2C ARP. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - NewState: new state of the I2Cx ARP. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected I2C ARP */ + I2Cx->CR1 |= CR1_ENARP_Set; + } + else + { + /* Disable the selected I2C ARP */ + I2Cx->CR1 &= CR1_ENARP_Reset; + } +} + +/******************************************************************************* +* Function Name : I2C_StretchClockCmd +* Description : Enables or disables the specified I2C Clock stretching. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - NewState: new state of the I2Cx Clock stretching. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == DISABLE) + { + /* Enable the selected I2C Clock stretching */ + I2Cx->CR1 |= CR1_NOSTRETCH_Set; + } + else + { + /* Disable the selected I2C Clock stretching */ + I2Cx->CR1 &= CR1_NOSTRETCH_Reset; + } +} + +/******************************************************************************* +* Function Name : I2C_FastModeDutyCycleConfig +* Description : Selects the specified I2C fast mode duty cycle. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - I2C_DutyCycle: specifies the fast mode duty cycle. +* This parameter can be one of the following values: +* - I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2 +* - I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9 +* Output : None +* Return : None +*******************************************************************************/ +void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, u16 I2C_DutyCycle) +{ + /* Check the parameters */ + assert(IS_I2C_DUTY_CYCLE(I2C_DutyCycle)); + + if (I2C_DutyCycle != I2C_DutyCycle_16_9) + { + /* I2C fast mode Tlow/Thigh=2 */ + I2Cx->CCR &= I2C_DutyCycle_2; + } + else + { + /* I2C fast mode Tlow/Thigh=16/9 */ + I2Cx->CCR |= I2C_DutyCycle_16_9; + } +} + +/******************************************************************************* +* Function Name : I2C_GetLastEvent +* Description : Returns the Last I2C Event. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* Output : None +* Return : The last event +*******************************************************************************/ +u32 I2C_GetLastEvent(I2C_TypeDef* I2Cx) +{ + u32 LastEvent = 0; + u32 Flag1 = 0, Flag2 = 0; + + Flag1 = I2Cx->SR1; + Flag2 = I2Cx->SR2; + Flag2 = Flag2 << 16; + + /* Get the last event value from I2C status register */ + LastEvent = (Flag1 | Flag2) & I2C_FLAG_Mask; + + /* Return status */ + return LastEvent; +} + +/******************************************************************************* +* Function Name : I2C_CheckEvent +* Description : Checks whether the Last I2C Event is equal to the one passed +* as parameter. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - I2C_EVENT: specifies the event to be checked. +* This parameter can be one of the following values: +* - I2C_EVENT_SLAVE_ADDRESS_MATCHED : EV1 +* - I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2 +* - I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3 +* - I2C_EVENT_SLAVE_ACK_FAILURE : EV3-1 +* - I2C_EVENT_MASTER_MODE_SELECT : EV5 +* - I2C_EVENT_MASTER_MODE_SELECTED : EV6 +* - I2C_EVENT_MASTER_BYTE_RECEIVED : EV7 +* - I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8 +* - I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9 +* - I2C_EVENT_SLAVE_STOP_DETECTED : EV4 +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Last event is equal to the I2C_Event +* - ERROR: Last event is different from the I2C_Event +*******************************************************************************/ +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, u32 I2C_EVENT) +{ + u32 LastEvent = 0; + u32 Flag1 = 0, Flag2 = 0; + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert(IS_I2C_EVENT(I2C_EVENT)); + + Flag1 = I2Cx->SR1; + Flag2 = I2Cx->SR2; + Flag2 = Flag2 << 16; + + /* Get the last event value from I2C status register */ + LastEvent = (Flag1 | Flag2) & I2C_FLAG_Mask; + + /* Check whether the last event is equal to I2C_EVENT */ + if (LastEvent == I2C_EVENT ) + { + /* SUCCESS: last event is equal to I2C_EVENT */ + status = SUCCESS; + } + else + { + /* ERROR: last event is different from I2C_EVENT */ + status = ERROR; + } + + /* Return status */ + return status; +} + +/******************************************************************************* +* Function Name : I2C_GetFlagStatus +* Description : Checks whether the specified I2C flag is set or not. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - I2C_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - I2C_FLAG_DUALF: Dual flag (Slave mode) +* - I2C_FLAG_SMBHOST: SMBus host header (Slave mode) +* - I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode) +* - I2C_FLAG_GENCALL: General call header flag (Slave mode) +* - I2C_FLAG_TRA: Transmitter/Receiver flag +* - I2C_FLAG_BUSY: Bus busy flag +* - I2C_FLAG_MSL: Master/Slave flag +* - I2C_FLAG_SMBALERT: SMBus Alert flag +* - I2C_FLAG_TIMEOUT: Timeout or Tlow error flag +* - I2C_FLAG_PECERR: PEC error in reception flag +* - I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) +* - I2C_FLAG_AF: Acknowledge failure flag +* - I2C_FLAG_ARLO: Arbitration lost flag (Master mode) +* - I2C_FLAG_BERR: Bus error flag +* - I2C_FLAG_TXE: Data register empty flag (Transmitter) +* - I2C_FLAG_RXNE: Data register not empty (Receiver) flag +* - I2C_FLAG_STOPF: Stop detection flag (Slave mode) +* - I2C_FLAG_ADD10: 10-bit header sent flag (Master mode) +* - I2C_FLAG_BTF: Byte transfer finished flag +* - I2C_FLAG_ADDR: Address sent flag (Master mode) “ADSL” +* Address matched flag (Slave mode)”ENDAD” +* - I2C_FLAG_SB: Start bit flag (Master mode) +* Output : None +* Return : The new state of I2C_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, u32 I2C_FLAG) +{ + FlagStatus bitstatus = RESET; + u32 i2cstatus = 0; + u32 Flag1 = 0, Flag2 = 0; + + /* Check the parameters */ + assert(IS_I2C_GET_FLAG(I2C_FLAG)); + + /* Read the I2Cx status register */ + Flag1 = I2Cx->SR1; + Flag2 = I2Cx->SR2; + Flag2 = (Flag2 & I2C_FLAG_Mask) << 16; + + /* Get the I2C status value */ + i2cstatus = Flag1 | Flag2; + + /* Get bit[27:0] of the flag */ + I2C_FLAG &= I2C_FLAG_Mask; + + /* Check the status of the specified I2C flag */ + if ((i2cstatus & I2C_FLAG) != (u32)RESET) + { + /* I2C_FLAG is set */ + bitstatus = SET; + } + else + { + /* I2C_FLAG is reset */ + bitstatus = RESET; + } + /* Return the I2C_FLAG status */ + return bitstatus; +} + +/******************************************************************************* +* Function Name : I2C_ClearFlag +* Description : Clears the I2Cx's pending flags. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - I2C_FLAG: specifies the flag to clear. +* This parameter can be one of the following values: +* - I2C_FLAG_SMBALERT: SMBus Alert flag +* - I2C_FLAG_TIMEOUT: Timeout or Tlow error flag +* - I2C_FLAG_PECERR: PEC error in reception flag +* - I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) +* - I2C_FLAG_AF: Acknowledge failure flag +* - I2C_FLAG_ARLO: Arbitration lost flag (Master mode) +* - I2C_FLAG_BERR: Bus error flag +* - I2C_FLAG_STOPF: Stop detection flag (Slave mode) +* - I2C_FLAG_ADD10: 10-bit header sent flag (Master mode) +* - I2C_FLAG_BTF: Byte transfer finished flag +* - I2C_FLAG_ADDR: Address sent flag (Master mode) “ADSL” +* Address matched flag (Slave mode)”ENDAD” +* - I2C_FLAG_SB: Start bit flag (Master mode) +* Output : None +* Return : None +*******************************************************************************/ +void I2C_ClearFlag(I2C_TypeDef* I2Cx, u32 I2C_FLAG) +{ + u32 flagpos = 0; + u8 flagindex = 0; + + /* Check the parameters */ + assert(IS_I2C_CLEAR_FLAG(I2C_FLAG)); + + /* Get the I2C flag position */ + flagpos = I2C_FLAG & I2C_FLAG_Mask; + + /* Get the I2C flag index */ + flagindex = I2C_FLAG >> 28; + + /* Clear the flag by writing 0 */ + if (flagindex == 1) + { + /* Clear the selected I2C flag */ + I2Cx->SR1 &= ~flagpos; + } + /* Flags that need a read of the SR1 register to be cleared */ + else if (flagindex == 2) + { + /* Read the SR1 register */ + (void)I2Cx->SR1; + } + /* Flags that need a read of SR1 and a write on CR2 registers to be cleared */ + else if (flagindex == 6) + { + /* Read the SR1 register */ + (void)I2Cx->SR1; + + /* Write on the CR1 register */ + I2Cx->CR1 |= CR1_PE_Set; + } + /* Flags that need a read of SR1 and a write on CR2 registers to be cleared */ + else /*flagindex == 0xA*/ + { + /* Read the SR1 register */ + (void)I2Cx->SR1; + + /* Read the SR2 register */ + (void)I2Cx->SR2; + } +} + +/******************************************************************************* +* Function Name : I2C_GetITStatus +* Description : Checks whether the specified I2C interrupt has occurred or not. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - I2C_IT: specifies the interrupt source to check. +* This parameter can be one of the following values: +* - I2C_IT_SMBALERT: SMBus Alert flag +* - I2C_IT_TIMEOUT: Timeout or Tlow error flag +* - I2C_IT_PECERR: PEC error in reception flag +* - I2C_IT_OVR: Overrun/Underrun flag (Slave mode) +* - I2C_IT_AF: Acknowledge failure flag +* - I2C_IT_ARLO: Arbitration lost flag (Master mode) +* - I2C_IT_BERR: Bus error flag +* - I2C_IT_TXE: Data register empty flag (Transmitter) +* - I2C_IT_RXNE: Data register not empty (Receiver) flag +* - I2C_IT_STOPF: Stop detection flag (Slave mode) +* - I2C_IT_ADD10: 10-bit header sent flag (Master mode) +* - I2C_IT_BTF: Byte transfer finished flag +* - I2C_IT_ADDR: Address sent flag (Master mode) “ADSL” +* Address matched flag (Slave mode)”ENDAD” +* - I2C_IT_SB: Start bit flag (Master mode) +* Output : None +* Return : The new state of I2C_IT (SET or RESET). +*******************************************************************************/ +ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, u32 I2C_IT) +{ + ITStatus bitstatus = RESET; + u32 i2cstatus = 0; + u32 Flag1 = 0, Flag2 = 0; + + /* Check the parameters */ + assert(IS_I2C_GET_IT(I2C_IT)); + + /* Read the I2Cx status register */ + Flag1 = I2Cx->SR1; + Flag2 = I2Cx->SR2; + Flag2 = (Flag2 & I2C_FLAG_Mask) << 16; + + /* Get the I2C status value */ + i2cstatus = Flag1 | Flag2; + + /* Get bit[27:0] of the flag */ + I2C_IT &= I2C_FLAG_Mask; + + /* Check the status of the specified I2C flag */ + if ((i2cstatus & I2C_IT) != (u32)RESET) + { + /* I2C_IT is set */ + bitstatus = SET; + } + else + { + /* I2C_IT is reset */ + bitstatus = RESET; + } + /* Return the I2C_IT status */ + return bitstatus; +} + +/******************************************************************************* +* Function Name : I2C_ClearITPendingBit +* Description : Clears the I2Cx’s interrupt pending bits. +* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* - I2C_IT: specifies the interrupt pending to clear. +* This parameter can be one of the following values: +* - I2C_IT_SMBALERT: SMBus Alert flag +* - I2C_IT_TIMEOUT: Timeout or Tlow error flag +* - I2C_IT_PECERR: PEC error in reception flag +* - I2C_IT_OVR: Overrun/Underrun flag (Slave mode) +* - I2C_IT_AF: Acknowledge failure flag +* - I2C_IT_ARLO: Arbitration lost flag (Master mode) +* - I2C_IT_BERR: Bus error flag +* - I2C_IT_STOPF: Stop detection flag (Slave mode) +* - I2C_IT_ADD10: 10-bit header sent flag (Master mode) +* - I2C_IT_BTF: Byte transfer finished flag +* - I2C_IT_ADDR: Address sent flag (Master mode) “ADSL” +* Address matched flag (Slave mode)”ENDAD” +* - I2C_IT_SB: Start bit flag (Master mode) +* Output : None +* Return : None +*******************************************************************************/ +void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, u32 I2C_IT) +{ + u32 flagpos = 0; + u8 flagindex = 0; + + /* Check the parameters */ + assert(IS_I2C_CLEAR_IT(I2C_IT)); + + /* Get the I2C flag position */ + flagpos = I2C_IT & I2C_FLAG_Mask; + + /* Get the I2C flag index */ + flagindex = I2C_IT >> 28; + + /* Clear the flag by writing 0 */ + if (flagindex == 1) + { + /* Clear the selected I2C flag */ + I2Cx->SR1 &= ~flagpos; + } + /* Flags that need a read of the SR1 register to be cleared */ + else if (flagindex == 2) + { + /* Read the SR1 register */ + (void)I2Cx->SR1; + } + /* Flags that need a read of SR1 and a write on CR2 registers to be cleared */ + else if (flagindex == 6) + { + /* Read the SR1 register */ + (void)I2Cx->SR1; + + /* Write on the CR1 register */ + I2Cx->CR1 |= CR1_PE_Set; + } + /* Flags that need a read of SR1 and a write on CR2 registers to be cleared */ + else /*flagindex == 0xA*/ + { + /* Read the SR1 register */ + (void)I2Cx->SR1; + + /* Read the SR2 register */ + (void)I2Cx->SR2; + } +} + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_iwdg.c b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_iwdg.c new file mode 100644 index 000000000..496e68d3c --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_iwdg.c @@ -0,0 +1,152 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_iwdg.c +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file provides all the IWDG firmware functions. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_iwdg.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* ---------------------- IWDG registers bit mask ------------------------ */ +/* KR register bit mask */ +#define KR_Reload ((u16)0xAAAA) +#define KR_Enable ((u16)0xCCCC) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : IWDG_WriteAccessCmd +* Description : Enables or disables write access to IWDG_PR and IWDG_RLR +* registers. +* Input : - IWDG_WriteAccess: new state of write access to IWDG_PR and +* IWDG_RLR registers. +* This parameter can be one of the following values: +* - IWDG_WriteAccess_Enable: Enable write access to +* IWDG_PR and IWDG_RLR registers +* - IWDG_WriteAccess_Disable: Disable write access to +* IWDG_PR and IWDG_RLR registers +* Output : None +* Return : None +*******************************************************************************/ +void IWDG_WriteAccessCmd(u16 IWDG_WriteAccess) +{ + /* Check the parameters */ + assert(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess)); + + IWDG->KR = IWDG_WriteAccess; +} + +/******************************************************************************* +* Function Name : IWDG_SetPrescaler +* Description : Sets IWDG Prescaler value. +* Input : - IWDG_Prescaler: specifies the IWDG Prescaler value. +* This parameter can be one of the following values: +* - IWDG_Prescaler_4: IWDG prescaler set to 4 +* - IWDG_Prescaler_8: IWDG prescaler set to 8 +* - IWDG_Prescaler_16: IWDG prescaler set to 16 +* - IWDG_Prescaler_32: IWDG prescaler set to 32 +* - IWDG_Prescaler_64: IWDG prescaler set to 64 +* - IWDG_Prescaler_128: IWDG prescaler set to 128 +* - IWDG_Prescaler_256: IWDG prescaler set to 256 +* Output : None +* Return : None +*******************************************************************************/ +void IWDG_SetPrescaler(u8 IWDG_Prescaler) +{ + /* Check the parameters */ + assert(IS_IWDG_PRESCALER(IWDG_Prescaler)); + + IWDG->PR = IWDG_Prescaler; +} + +/******************************************************************************* +* Function Name : IWDG_SetReload +* Description : Sets IWDG Reload value. +* Input : - Reload: specifies the IWDG Reload value. +* This parameter must be a number between 0 and 0x0FFF. +* Output : None +* Return : None +*******************************************************************************/ +void IWDG_SetReload(u16 Reload) +{ + /* Check the parameters */ + assert(IS_IWDG_RELOAD(Reload)); + + IWDG->RLR = Reload; +} + +/******************************************************************************* +* Function Name : IWDG_ReloadCounter +* Description : Reloads IWDG counter with value defined in the reload register +* (write access to IWDG_PR and IWDG_RLR registers disabled). +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void IWDG_ReloadCounter(void) +{ + IWDG->KR = KR_Reload; +} + +/******************************************************************************* +* Function Name : IWDG_Enable +* Description : Enables IWDG (write access to IWDG_PR and IWDG_RLR registers +* disabled). +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void IWDG_Enable(void) +{ + IWDG->KR = KR_Enable; +} + +/******************************************************************************* +* Function Name : IWDG_GetFlagStatus +* Description : Checks whether the specified IWDG flag is set or not. +* Input : - IWDG_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - IWDG_FLAG_PVU: Prescaler Value Update on going +* - IWDG_FLAG_RVU: Reload Value Update on going +* Output : None +* Return : The new state of IWDG_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus IWDG_GetFlagStatus(u16 IWDG_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert(IS_IWDG_FLAG(IWDG_FLAG)); + + if ((IWDG->SR & IWDG_FLAG) != (u32)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + /* Return the flag status */ + return bitstatus; +} + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_lib.c b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_lib.c new file mode 100644 index 000000000..7df2cb812 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_lib.c @@ -0,0 +1,221 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_lib.c +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file provides all peripherals pointers initialization. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +#define EXT + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_lib.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +#ifdef DEBUG +/******************************************************************************* +* Function Name : debug +* Description : This function initialize peripherals pointers. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void debug(void) +{ + +/************************************* ADC ************************************/ +#ifdef _ADC1 + ADC1 = (ADC_TypeDef *) ADC1_BASE; +#endif /*_ADC1 */ + +#ifdef _ADC2 + ADC2 = (ADC_TypeDef *) ADC2_BASE; +#endif /*_ADC2 */ + +/************************************* BKP ************************************/ +#ifdef _BKP + BKP = (BKP_TypeDef *) BKP_BASE; +#endif /*_BKP */ + +/************************************* CAN ************************************/ +#ifdef _CAN + CAN = (CAN_TypeDef *) CAN_BASE; +#endif /*_CAN */ + +/************************************* DMA ************************************/ +#ifdef _DMA + DMA = (DMA_TypeDef *) DMA_BASE; +#endif /*_DMA */ + +#ifdef _DMA_Channel1 + DMA_Channel1 = (DMA_Channel_TypeDef *) DMA_Channel1_BASE; +#endif /*_DMA_Channel1 */ + +#ifdef _DMA_Channel2 + DMA_Channel2 = (DMA_Channel_TypeDef *) DMA_Channel2_BASE; +#endif /*_DMA_Channel2 */ + +#ifdef _DMA_Channel3 + DMA_Channel3 = (DMA_Channel_TypeDef *) DMA_Channel3_BASE; +#endif /*_DMA_Channel3 */ + +#ifdef _DMA_Channel4 + DMA_Channel4 = (DMA_Channel_TypeDef *) DMA_Channel4_BASE; +#endif /*_DMA_Channel4 */ + +#ifdef _DMA_Channel5 + DMA_Channel5 = (DMA_Channel_TypeDef *) DMA_Channel5_BASE; +#endif /*_DMA_Channel5 */ + +#ifdef _DMA_Channel6 + DMA_Channel6 = (DMA_Channel_TypeDef *) DMA_Channel6_BASE; +#endif /*_DMA_Channel6 */ + +#ifdef _DMA_Channel7 + DMA_Channel7 = (DMA_Channel_TypeDef *) DMA_Channel7_BASE; +#endif /*_DMA_Channel7 */ + +/************************************* EXTI ***********************************/ +#ifdef _EXTI + EXTI = (EXTI_TypeDef *) EXTI_BASE; +#endif /*_EXTI */ + +/************************************* FLASH and Option Bytes *****************/ +#ifdef _FLASH + FLASH = (FLASH_TypeDef *) FLASH_BASE; + OB = (OB_TypeDef *) OB_BASE; +#endif /*_FLASH */ + +/************************************* GPIO ***********************************/ +#ifdef _GPIOA + GPIOA = (GPIO_TypeDef *) GPIOA_BASE; +#endif /*_GPIOA */ + +#ifdef _GPIOB + GPIOB = (GPIO_TypeDef *) GPIOB_BASE; +#endif /*_GPIOB */ + +#ifdef _GPIOC + GPIOC = (GPIO_TypeDef *) GPIOC_BASE; +#endif /*_GPIOC */ + +#ifdef _GPIOD + GPIOD = (GPIO_TypeDef *) GPIOD_BASE; +#endif /*_GPIOD */ + +#ifdef _GPIOE + GPIOE = (GPIO_TypeDef *) GPIOE_BASE; +#endif /*_GPIOE */ + +#ifdef _AFIO + AFIO = (AFIO_TypeDef *) AFIO_BASE; +#endif /*_AFIO */ + +/************************************* I2C ************************************/ +#ifdef _I2C1 + I2C1 = (I2C_TypeDef *) I2C1_BASE; +#endif /*_I2C1 */ + +#ifdef _I2C2 + I2C2 = (I2C_TypeDef *) I2C2_BASE; +#endif /*_I2C2 */ + +/************************************* IWDG ***********************************/ +#ifdef _IWDG + IWDG = (IWDG_TypeDef *) IWDG_BASE; +#endif /*_IWDG */ + +/************************************* NVIC ***********************************/ +#ifdef _NVIC + NVIC = (NVIC_TypeDef *) NVIC_BASE; +#endif /*_NVIC */ + +#ifdef _SCB + SCB = (SCB_TypeDef *) SCB_BASE; +#endif /*_SCB */ + +/************************************* PWR ************************************/ +#ifdef _PWR + PWR = (PWR_TypeDef *) PWR_BASE; +#endif /*_PWR */ + +/************************************* RCC ************************************/ +#ifdef _RCC + RCC = (RCC_TypeDef *) RCC_BASE; +#endif /*_RCC */ + +/************************************* RTC ************************************/ +#ifdef _RTC + RTC = (RTC_TypeDef *) RTC_BASE; +#endif /*_RTC */ + +/************************************* SPI ************************************/ +#ifdef _SPI1 + SPI1 = (SPI_TypeDef *) SPI1_BASE; +#endif /*_SPI1 */ + +#ifdef _SPI2 + SPI2 = (SPI_TypeDef *) SPI2_BASE; +#endif /*_SPI2 */ + +/************************************* SysTick ********************************/ +#ifdef _SysTick + SysTick = (SysTick_TypeDef *) SysTick_BASE; +#endif /*_SysTick */ + +/************************************* TIM1 ***********************************/ +#ifdef _TIM1 + TIM1 = (TIM1_TypeDef *) TIM1_BASE; +#endif /*_TIM1 */ + +/************************************* TIM ************************************/ +#ifdef _TIM2 + TIM2 = (TIM_TypeDef *) TIM2_BASE; +#endif /*_TIM2 */ + +#ifdef _TIM3 + TIM3 = (TIM_TypeDef *) TIM3_BASE; +#endif /*_TIM3 */ + +#ifdef _TIM4 + TIM4 = (TIM_TypeDef *) TIM4_BASE; +#endif /*_TIM4 */ + +/************************************* USART **********************************/ +#ifdef _USART1 + USART1 = (USART_TypeDef *) USART1_BASE; +#endif /*_USART1 */ + +#ifdef _USART2 + USART2 = (USART_TypeDef *) USART2_BASE; +#endif /*_USART2 */ + +#ifdef _USART3 + USART3 = (USART_TypeDef *) USART3_BASE; +#endif /*_USART3 */ + +/************************************* WWDG ***********************************/ +#ifdef _WWDG + WWDG = (WWDG_TypeDef *) WWDG_BASE; +#endif /*_WWDG */ +} +#endif + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_nvic.c b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_nvic.c new file mode 100644 index 000000000..79bb86743 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_nvic.c @@ -0,0 +1,755 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_nvic.c +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file provides all the NVIC firmware functions. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_nvic.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define AIRC_VECTKEY_MASK ((u32)0x05FA0000) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : NVIC_DeInit +* Description : Deinitializes the NVIC peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_DeInit(void) +{ + u32 index = 0; + + NVIC->Disable[0] = 0xFFFFFFFF; + NVIC->Disable[1] = 0x000007FF; + NVIC->Clear[0] = 0xFFFFFFFF; + NVIC->Clear[1] = 0x000007FF; + + for(index = 0; index < 0x0B; index++) + { + NVIC->Priority[index] = 0x00000000; + } +} + +/******************************************************************************* +* Function Name : NVIC_SCBDeInit +* Description : Deinitializes the SCB peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_SCBDeInit(void) +{ + u32 index = 0x00; + + SCB->IRQControlState = 0x0A000000; + SCB->ExceptionTableOffset = 0x00000000; + SCB->AIRC = AIRC_VECTKEY_MASK; + SCB->SysCtrl = 0x00000000; + SCB->ConfigCtrl = 0x00000000; + for(index = 0; index < 0x03; index++) + { + SCB->SystemPriority[index] = 0; + } + SCB->SysHandlerCtrl = 0x00000000; + SCB->ConfigFaultStatus = 0xFFFFFFFF; + SCB->HardFaultStatus = 0xFFFFFFFF; + SCB->DebugFaultStatus = 0xFFFFFFFF; +} + +/******************************************************************************* +* Function Name : NVIC_PriorityGroupConfig +* Description : Configures the priority grouping: pre-emption priority +* and subpriority. +* Input : - NVIC_PriorityGroup: specifies the priority grouping bits +* length. This parameter can be one of the following values: +* - NVIC_PriorityGroup_0: 0 bits for pre-emption priority +* 4 bits for subpriority +* - NVIC_PriorityGroup_1: 1 bits for pre-emption priority +* 3 bits for subpriority +* - NVIC_PriorityGroup_2: 2 bits for pre-emption priority +* 2 bits for subpriority +* - NVIC_PriorityGroup_3: 3 bits for pre-emption priority +* 1 bits for subpriority +* - NVIC_PriorityGroup_4: 4 bits for pre-emption priority +* 0 bits for subpriority +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_PriorityGroupConfig(u32 NVIC_PriorityGroup) +{ + /* Check the parameters */ + assert(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ + SCB->AIRC = AIRC_VECTKEY_MASK | NVIC_PriorityGroup; +} + +/******************************************************************************* +* Function Name : NVIC_Init +* Description : Initializes the NVIC peripheral according to the specified +* parameters in the NVIC_InitStruct. +* Input : - NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure +* that contains the configuration information for the +* specified NVIC peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) +{ + u32 tmppriority = 0x00, tmpreg = 0x00, tmpmask = 0x00; + u32 tmppre = 0, tmpsub = 0x0F; + + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); + assert(IS_NVIC_IRQ_CHANNEL(NVIC_InitStruct->NVIC_IRQChannel)); + assert(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); + assert(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); + + if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) + { + /* Compute the Corresponding IRQ Priority --------------------------------*/ + tmppriority = (0x700 - (SCB->AIRC & (u32)0x700))>> 0x08; + tmppre = (0x4 - tmppriority); + tmpsub = tmpsub >> tmppriority; + + tmppriority = (u32)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; + tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub; + + tmppriority = tmppriority << 0x04; + tmppriority = ((u32)tmppriority) << ((NVIC_InitStruct->NVIC_IRQChannel & (u8)0x03) * 0x08); + + tmpreg = NVIC->Priority[(NVIC_InitStruct->NVIC_IRQChannel >> 0x02)]; + tmpmask = (u32)0xFF << ((NVIC_InitStruct->NVIC_IRQChannel & (u8)0x03) * 0x08); + tmpreg &= ~tmpmask; + tmppriority &= tmpmask; + tmpreg |= tmppriority; + + NVIC->Priority[(NVIC_InitStruct->NVIC_IRQChannel >> 0x02)] = tmpreg; + + /* Enable the Selected IRQ Channels --------------------------------------*/ + NVIC->Enable[(NVIC_InitStruct->NVIC_IRQChannel >> 0x05)] = + (u32)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (u8)0x1F); + } + else + { + /* Disable the Selected IRQ Channels -------------------------------------*/ + NVIC->Disable[(NVIC_InitStruct->NVIC_IRQChannel >> 0x05)] = + (u32)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (u8)0x1F); + } +} + +/******************************************************************************* +* Function Name : NVIC_StructInit +* Description : Fills each NVIC_InitStruct member with its default value. +* Input : - NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure which +* will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_StructInit(NVIC_InitTypeDef* NVIC_InitStruct) +{ + /* NVIC_InitStruct members default value */ + NVIC_InitStruct->NVIC_IRQChannel = 0x00; + NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority = 0x00; + NVIC_InitStruct->NVIC_IRQChannelSubPriority = 0x00; + NVIC_InitStruct->NVIC_IRQChannelCmd = DISABLE; +} + +/******************************************************************************* +* Function Name : NVIC_SETPRIMASK +* Description : Enables the PRIMASK priority: Raises the execution priority to 0. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_SETPRIMASK(void) +{ + __SETPRIMASK(); +} + +/******************************************************************************* +* Function Name : NVIC_RESETPRIMASK +* Description : Disables the PRIMASK priority. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_RESETPRIMASK(void) +{ + __RESETPRIMASK(); +} + +/******************************************************************************* +* Function Name : NVIC_SETFAULTMASK +* Description : Enables the FAULTMASK priority: Raises the execution priority to -1. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_SETFAULTMASK(void) +{ + __SETFAULTMASK(); +} + +/******************************************************************************* +* Function Name : NVIC_RESETFAULTMASK +* Description : Disables the FAULTMASK priority. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_RESETFAULTMASK(void) +{ + __RESETFAULTMASK(); +} + +/******************************************************************************* +* Function Name : NVIC_BASEPRICONFIG +* Description : The execution priority can be changed from 15 (lowest + configurable priority) to 1. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_BASEPRICONFIG(u32 NewPriority) +{ + /* Check the parameters */ + assert(IS_NVIC_BASE_PRI(NewPriority)); + + __BASEPRICONFIG(NewPriority << 0x04); +} + +/******************************************************************************* +* Function Name : NVIC_GetBASEPRI +* Description : Returns the BASEPRI mask value. +* Input : None +* Output : None +* Return : BASEPRI register value +*******************************************************************************/ +u32 NVIC_GetBASEPRI(void) +{ + return (__GetBASEPRI()); +} + +/******************************************************************************* +* Function Name : NVIC_GetCurrentPendingIRQChannel +* Description : Returns the current pending IRQ channel identifier. +* Input : None +* Output : None +* Return : Pending IRQ Channel Identifier. +*******************************************************************************/ +u16 NVIC_GetCurrentPendingIRQChannel(void) +{ + return ((u16)((SCB->IRQControlState & (u32)0x003FF000) >> 0x0C)); +} + +/******************************************************************************* +* Function Name : NVIC_GetIRQChannelPendingBitStatus +* Description : Checks whether the specified IRQ Channel pending bit is set +* or not. +* Input : - NVIC_IRQChannel: specifies the interrupt pending bit to check. +* Output : None +* Return : The new state of IRQ Channel pending bit(SET or RESET). +*******************************************************************************/ +ITStatus NVIC_GetIRQChannelPendingBitStatus(u8 NVIC_IRQChannel) +{ + ITStatus pendingirqstatus = RESET; + u32 tmp = 0x00; + + /* Check the parameters */ + assert(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel)); + + tmp = ((u32)0x01 << (NVIC_IRQChannel & (u32)0x1F)); + + if (((NVIC->Set[(NVIC_IRQChannel >> 0x05)]) & tmp) == tmp) + { + pendingirqstatus = SET; + } + else + { + pendingirqstatus = RESET; + } + return pendingirqstatus; +} + +/******************************************************************************* +* Function Name : NVIC_SetIRQChannelPendingBit +* Description : Sets the NVIC’s interrupt pending bit. +* Input : - NVIC_IRQChannel: specifies the interrupt pending bit to Set. +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_SetIRQChannelPendingBit(u8 NVIC_IRQChannel) +{ + /* Check the parameters */ + assert(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel)); + + *(u32*)0xE000EF00 = (u32)NVIC_IRQChannel; +} + +/******************************************************************************* +* Function Name : NVIC_ClearIRQChannelPendingBit +* Description : Clears the NVIC’s interrupt pending bit. +* Input : - NVIC_IRQChannel: specifies the interrupt pending bit to clear. +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_ClearIRQChannelPendingBit(u8 NVIC_IRQChannel) +{ + /* Check the parameters */ + assert(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel)); + + NVIC->Clear[(NVIC_IRQChannel >> 0x05)] = (u32)0x01 << (NVIC_IRQChannel & (u32)0x1F); +} + +/******************************************************************************* +* Function Name : NVIC_GetCurrentActiveHandler +* Description : Returns the current active Handler (IRQ Channel and +* SystemHandler) identifier. +* Input : None +* Output : None +* Return : Active Handler Identifier. +*******************************************************************************/ +u16 NVIC_GetCurrentActiveHandler(void) +{ + return ((u16)(SCB->IRQControlState & (u32)0x3FF)); +} + +/******************************************************************************* +* Function Name : NVIC_GetIRQChannelActiveBitStatus +* Description : Checks whether the specified IRQ Channel active bit is set +* or not. +* Input : - NVIC_IRQChannel: specifies the interrupt active bit to check. +* Output : None +* Return : The new state of IRQ Channel active bit(SET or RESET). +*******************************************************************************/ +ITStatus NVIC_GetIRQChannelActiveBitStatus(u8 NVIC_IRQChannel) +{ + ITStatus activeirqstatus = RESET; + u32 tmp = 0x00; + + /* Check the parameters */ + assert(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel)); + + tmp = ((u32)0x01 << (NVIC_IRQChannel & (u32)0x1F)); + + if (((NVIC->Active[(NVIC_IRQChannel >> 0x05)]) & tmp) == tmp ) + { + activeirqstatus = SET; + } + else + { + activeirqstatus = RESET; + } + return activeirqstatus; +} + +/******************************************************************************* +* Function Name : NVIC_GetCPUID +* Description : Returns the ID number, the version number and the implementation +* details of the Cortex-M3 core. +* Input : None +* Output : None +* Return : CPU ID. +*******************************************************************************/ +u32 NVIC_GetCPUID(void) +{ + return (SCB->CPUID); +} + +/******************************************************************************* +* Function Name : NVIC_SetVectorTable +* Description : Sets the vector table location and Offset. +* Input : - NVIC_VectTab: specifies if the vector table is in RAM or +* code memory. +* This parameter can be one of the following values: +* - NVIC_VectTab_RAM +* - NVIC_VectTab_FLASH +* - Offset: Vector Table base offset field. +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_SetVectorTable(u32 NVIC_VectTab, u32 Offset) +{ + /* Check the parameters */ + assert(IS_NVIC_VECTTAB(NVIC_VectTab)); + assert(IS_NVIC_OFFSET(Offset)); + + SCB->ExceptionTableOffset = (((u32)Offset << 0x07) & (u32)0x1FFFFF80); + + SCB->ExceptionTableOffset |= NVIC_VectTab; +} + +/******************************************************************************* +* Function Name : NVIC_GenerateSystemReset +* Description : Generates a system reset. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_GenerateSystemReset(void) +{ + SCB->AIRC = AIRC_VECTKEY_MASK | (u32)0x04; +} + +/******************************************************************************* +* Function Name : NVIC_GenerateCoreReset +* Description : Generates a Core (Core + NVIC) reset. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_GenerateCoreReset(void) +{ + SCB->AIRC = AIRC_VECTKEY_MASK | (u32)0x01; +} + +/******************************************************************************* +* Function Name : NVIC_SystemLPConfig +* Description : Selects the condition for the system to enter low power mode. +* Input : - LowPowerMode: Specifies the new mode for the system to enter +* low power mode. +* This parameter can be one of the following values: +* - NVIC_LP_SEVONPEND +* - NVIC_LP_SLEEPDEEP +* - NVIC_LP_SLEEPONEXIT +* - NewState: new state of LP condition. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_SystemLPConfig(u8 LowPowerMode, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_NVIC_LP(LowPowerMode)); + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + SCB->SysCtrl |= LowPowerMode; + } + else + { + SCB->SysCtrl &= (u32)(~(u32)LowPowerMode); + } +} + +/******************************************************************************* +* Function Name : NVIC_SystemHandlerConfig +* Description : Enables or disables the specified System Handlers. +* Input : - SystemHandler: specifies the system handler to be enabled +* or disabled. +* This parameter can be one of the following values: +* - SystemHandler_MemoryManage +* - SystemHandler_BusFault +* - SystemHandler_UsageFault +* - NewState: new state of specified System Handlers. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_SystemHandlerConfig(u32 SystemHandler, FunctionalState NewState) +{ + u32 tmpreg = 0x00; + + /* Check the parameters */ + assert(IS_CONFIG_SYSTEM_HANDLER(SystemHandler)); + assert(IS_FUNCTIONAL_STATE(NewState)); + + tmpreg = (u32)0x01 << (SystemHandler & (u32)0x1F); + + if (NewState != DISABLE) + { + SCB->SysHandlerCtrl |= tmpreg; + } + else + { + SCB->SysHandlerCtrl &= ~tmpreg; + } +} + +/******************************************************************************* +* Function Name : NVIC_SystemHandlerPriorityConfig +* Description : Configures the specified System Handlers priority. +* Input : - SystemHandler: specifies the system handler to be +* enabled or disabled. +* This parameter can be one of the following values: +* - SystemHandler_MemoryManage +* - SystemHandler_BusFault +* - SystemHandler_UsageFault +* - SystemHandler_SVCall +* - SystemHandler_DebugMonitor +* - SystemHandler_PSV +* - SystemHandler_SysTick +* - SystemHandlerPreemptionPriority: new priority group of the +* specified system handlers. +* - SystemHandlerSubPriority: new sub priority of the specified +* system handlers. +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_SystemHandlerPriorityConfig(u32 SystemHandler, u8 SystemHandlerPreemptionPriority, + u8 SystemHandlerSubPriority) +{ + u32 tmp1 = 0x00, tmp2 = 0xFF, handlermask = 0x00; + u32 tmppriority = 0x00; + + /* Check the parameters */ + assert(IS_PRIORITY_SYSTEM_HANDLER(SystemHandler)); + assert(IS_NVIC_PREEMPTION_PRIORITY(SystemHandlerPreemptionPriority)); + assert(IS_NVIC_SUB_PRIORITY(SystemHandlerSubPriority)); + + tmppriority = (0x700 - (SCB->AIRC & (u32)0x700))>> 0x08; + tmp1 = (0x4 - tmppriority); + tmp2 = tmp2 >> tmppriority; + + tmppriority = (u32)SystemHandlerPreemptionPriority << tmp1; + tmppriority |= SystemHandlerSubPriority & tmp2; + + tmppriority = tmppriority << 0x04; + tmp1 = SystemHandler & (u32)0xC0; + tmp1 = tmp1 >> 0x06; + tmp2 = (SystemHandler >> 0x08) & (u32)0x03; + tmppriority = tmppriority << (tmp2 * 0x08); + handlermask = (u32)0xFF << (tmp2 * 0x08); + + SCB->SystemPriority[tmp1] &= ~handlermask; + SCB->SystemPriority[tmp1] |= tmppriority; +} + +/******************************************************************************* +* Function Name : NVIC_GetSystemHandlerPendingBitStatus +* Description : Checks whether the specified System handlers pending bit is +* set or not. +* Input : - SystemHandler: specifies the system handler pending bit to +* check. +* This parameter can be one of the following values: +* - SystemHandler_MemoryManage +* - SystemHandler_BusFault +* - SystemHandler_SVCall +* Output : None +* Return : The new state of System Handler pending bit(SET or RESET). +*******************************************************************************/ +ITStatus NVIC_GetSystemHandlerPendingBitStatus(u32 SystemHandler) +{ + ITStatus bitstatus = RESET; + u32 tmp = 0x00, tmppos = 0x00; + + /* Check the parameters */ + assert(IS_GET_PENDING_SYSTEM_HANDLER(SystemHandler)); + + tmppos = (SystemHandler >> 0x0A); + tmppos &= (u32)0x0F; + + tmppos = (u32)0x01 << tmppos; + + tmp = SCB->SysHandlerCtrl & tmppos; + + if (tmp == tmppos) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : NVIC_SetSystemHandlerPendingBit +* Description : Sets System Handler pending bit. +* Input : - SystemHandler: specifies the system handler pending bit +* to be set. +* This parameter can be one of the following values: +* - SystemHandler_NMI +* - SystemHandler_PSV +* - SystemHandler_SysTick +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_SetSystemHandlerPendingBit(u32 SystemHandler) +{ + u32 tmp = 0x00; + + /* Check the parameters */ + assert(IS_SET_PENDING_SYSTEM_HANDLER(SystemHandler)); + + /* Get the System Handler pending bit position */ + tmp = SystemHandler & (u32)0x1F; + /* Set the corresponding System Handler pending bit */ + SCB->IRQControlState |= ((u32)0x01 << tmp); +} + +/******************************************************************************* +* Function Name : NVIC_ClearSystemHandlerPendingBit +* Description : Clears System Handler pending bit. +* Input : - SystemHandler: specifies the system handler pending bit to +* be clear. +* This parameter can be one of the following values: +* - SystemHandler_PSV +* - SystemHandler_SysTick +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_ClearSystemHandlerPendingBit(u32 SystemHandler) +{ + u32 tmp = 0x00; + + /* Check the parameters */ + assert(IS_CLEAR_SYSTEM_HANDLER(SystemHandler)); + + /* Get the System Handler pending bit position */ + tmp = SystemHandler & (u32)0x1F; + /* Clear the corresponding System Handler pending bit */ + SCB->IRQControlState |= ((u32)0x01 << (tmp - 0x01)); +} + +/******************************************************************************* +* Function Name : NVIC_GetSystemHandlerActiveBitStatus +* Description : Checks whether the specified System handlers active bit is +* set or not. +* Input : - SystemHandler: specifies the system handler active bit to +* check. +* This parameter can be one of the following values: +* - SystemHandler_MemoryManage +* - SystemHandler_BusFault +* - SystemHandler_UsageFault +* - SystemHandler_SVCall +* - SystemHandler_DebugMonitor +* - SystemHandler_PSV +* - SystemHandler_SysTick +* Output : None +* Return : The new state of System Handler active bit(SET or RESET). +*******************************************************************************/ +ITStatus NVIC_GetSystemHandlerActiveBitStatus(u32 SystemHandler) +{ + ITStatus bitstatus = RESET; + + u32 tmp = 0x00, tmppos = 0x00; + + /* Check the parameters */ + assert(IS_GET_ACTIVE_SYSTEM_HANDLER(SystemHandler)); + + tmppos = (SystemHandler >> 0x0E) & (u32)0x0F; + + tmppos = (u32)0x01 << tmppos; + + tmp = SCB->SysHandlerCtrl & tmppos; + + if (tmp == tmppos) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : NVIC_GetFaultHandlerSources +* Description : Returns the system fault handlers sources. +* Input : - SystemHandler: specifies the system handler to get its fault +* sources. +* This parameter can be one of the following values: +* - SystemHandler_HardFault +* - SystemHandler_MemoryManage +* - SystemHandler_BusFault +* - SystemHandler_UsageFault +* - SystemHandler_DebugMonitor +* Output : None +* Return : Source of the fault handler. +*******************************************************************************/ +u32 NVIC_GetFaultHandlerSources(u32 SystemHandler) +{ + u32 faultsources = 0x00; + u32 tmpreg = 0x00, tmppos = 0x00; + + /* Check the parameters */ + assert(IS_FAULT_SOURCE_SYSTEM_HANDLER(SystemHandler)); + + tmpreg = (SystemHandler >> 0x12) & (u32)0x03; + tmppos = (SystemHandler >> 0x14) & (u32)0x03; + + if (tmpreg == 0x00) + { + faultsources = SCB->HardFaultStatus; + } + else if (tmpreg == 0x01) + { + faultsources = SCB->ConfigFaultStatus >> (tmppos * 0x08); + if (tmppos != 0x02) + { + faultsources &= (u32)0x0F; + } + else + { + faultsources &= (u32)0xFF; + } + } + else + { + faultsources = SCB->DebugFaultStatus; + } + return faultsources; +} + +/******************************************************************************* +* Function Name : NVIC_GetFaultAddress +* Description : Returns the address of the location that generated a fault +* handler. +* Input : - SystemHandler: specifies the system handler to get its +* fault address. +* This parameter can be one of the following values: +* - SystemHandler_MemoryManage +* - SystemHandler_BusFault +* Output : None +* Return : Fault address. +*******************************************************************************/ +u32 NVIC_GetFaultAddress(u32 SystemHandler) +{ + u32 faultaddress = 0x00; + u32 tmp = 0x00; + + /* Check the parameters */ + assert(IS_FAULT_ADDRESS_SYSTEM_HANDLER(SystemHandler)); + + tmp = (SystemHandler >> 0x16) & (u32)0x01; + + if (tmp == 0x00) + { + faultaddress = SCB->MemoryManageFaultAddr; + } + else + { + faultaddress = SCB->BusFaultAddr; + } + return faultaddress; +} + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_pwr.c b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_pwr.c new file mode 100644 index 000000000..26b6dcc2f --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_pwr.c @@ -0,0 +1,283 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_pwr.c +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file provides all the PWR firmware functions. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_pwr.h" +#include "stm32f10x_rcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* --------- PWR registers bit address in the alias region ---------- */ +#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) + +/* --- CR Register ---*/ +/* Alias word address of DBP bit */ +#define CR_OFFSET (PWR_OFFSET + 0x00) +#define DBP_BitNumber 0x08 +#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) + +/* Alias word address of PVDE bit */ +#define PVDE_BitNumber 0x04 +#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4)) + +/* --- CSR Register ---*/ +/* Alias word address of EWUP bit */ +#define CSR_OFFSET (PWR_OFFSET + 0x04) +#define EWUP_BitNumber 0x08 +#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4)) + +/* ------------------ PWR registers bit mask ------------------------ */ +/* CR register bit mask */ +#define CR_PDDS_Set ((u32)0x00000002) +#define CR_DS_Mask ((u32)0xFFFFFFFC) +#define CR_CWUF_Set ((u32)0x00000004) +#define CR_PLS_Mask ((u32)0xFFFFFF1F) + +/* --------- Cortex System Control register bit mask ---------------- */ +/* Cortex System Control register address */ +#define SCB_SysCtrl ((u32)0xE000ED10) +/* SLEEPDEEP bit mask */ +#define SysCtrl_SLEEPDEEP_Set ((u32)0x00000004) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : PWR_DeInit +* Description : Deinitializes the PWR peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void PWR_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); +} + +/******************************************************************************* +* Function Name : PWR_BackupAccessCmd +* Description : Enables or disables access to the RTC and backup registers. +* Input : - NewState: new state of the access to the RTC and backup +* registers. This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void PWR_BackupAccessCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + *(vu32 *) CR_DBP_BB = (u32)NewState; +} + +/******************************************************************************* +* Function Name : PWR_PVDCmd +* Description : Enables or disables the Power Voltage Detector(PVD). +* Input : - NewState: new state of the PVD. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void PWR_PVDCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + *(vu32 *) CR_PVDE_BB = (u32)NewState; +} + +/******************************************************************************* +* Function Name : PWR_PVDLevelConfig +* Description : Configures the value detected by the Power Voltage Detector(PVD). +* Input : - PWR_PVDLevel: specifies the PVD detection level +* This parameter can be one of the following values: +* - PWR_PVDLevel_2V2: PVD detection level set to 2.2V +* - PWR_PVDLevel_2V3: PVD detection level set to 2.3V +* - PWR_PVDLevel_2V4: PVD detection level set to 2.4V +* - PWR_PVDLevel_2V5: PVD detection level set to 2.5V +* - PWR_PVDLevel_2V6: PVD detection level set to 2.6V +* - PWR_PVDLevel_2V7: PVD detection level set to 2.7V +* - PWR_PVDLevel_2V8: PVD detection level set to 2.8V +* - PWR_PVDLevel_2V9: PVD detection level set to 2.9V +* Output : None +* Return : None +*******************************************************************************/ +void PWR_PVDLevelConfig(u32 PWR_PVDLevel) +{ + u32 tmpreg = 0; + + /* Check the parameters */ + assert(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); + + tmpreg = PWR->CR; + + /* Clear PLS[7:5] bits */ + tmpreg &= CR_PLS_Mask; + + /* Set PLS[7:5] bits according to PWR_PVDLevel value */ + tmpreg |= PWR_PVDLevel; + + /* Store the new value */ + PWR->CR = tmpreg; +} + +/******************************************************************************* +* Function Name : PWR_WakeUpPinCmd +* Description : Enables or disables the WakeUp Pin functionality. +* Input : - NewState: new state of the WakeUp Pin functionality. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void PWR_WakeUpPinCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + *(vu32 *) CSR_EWUP_BB = (u32)NewState; +} + +/******************************************************************************* +* Function Name : PWR_EnterSTOPMode +* Description : Enters STOP mode. +* Input : - PWR_Regulator: specifies the regulator state in STOP mode. +* This parameter can be one of the following values: +* - PWR_Regulator_ON: STOP mode with regulator ON +* - PWR_Regulator_LowPower: STOP mode with +* regulator in low power mode +* - PWR_STOPEntry: specifies if STOP mode in entered with WFI or +* WFE instruction. +* This parameter can be one of the following values: +* - PWR_STOPEntry_WFI: enter STOP mode with WFI instruction +* - PWR_STOPEntry_WFE: enter STOP mode with WFE instruction +* Output : None +* Return : None +*******************************************************************************/ +void PWR_EnterSTOPMode(u32 PWR_Regulator, u8 PWR_STOPEntry) +{ + u32 tmpreg = 0; + + /* Check the parameters */ + assert(IS_PWR_REGULATOR(PWR_Regulator)); + assert(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); + + /* Select the regulator state in STOP mode ---------------------------------*/ + tmpreg = PWR->CR; + + /* Clear PDDS and LPDS bits */ + tmpreg &= CR_DS_Mask; + + /* Set LPDS bit according to PWR_Regulator value */ + tmpreg |= PWR_Regulator; + + /* Store the new value */ + PWR->CR = tmpreg; + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + *(vu32 *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set; + + /* Select STOP mode entry --------------------------------------------------*/ + if(PWR_STOPEntry == PWR_STOPEntry_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __WFE(); + } +} + +/******************************************************************************* +* Function Name : PWR_EnterSTANDBYMode +* Description : Enters STANDBY mode. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void PWR_EnterSTANDBYMode(void) +{ + /* Clear Wake-up flag */ + PWR->CR |= CR_CWUF_Set; + + /* Select STANDBY mode */ + PWR->CR |= CR_PDDS_Set; + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + *(vu32 *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set; + + /* Request Wait For Interrupt */ + __WFI(); +} + +/******************************************************************************* +* Function Name : PWR_GetFlagStatus +* Description : Checks whether the specified PWR flag is set or not. +* Input : - PWR_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - PWR_FLAG_WU: Wake Up flag +* - PWR_FLAG_SB: StandBy flag +* - PWR_FLAG_PVDO: PVD Output +* Output : None +* Return : The new state of PWR_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus PWR_GetFlagStatus(u32 PWR_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert(IS_PWR_GET_FLAG(PWR_FLAG)); + + if ((PWR->CSR & PWR_FLAG) != (u32)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + /* Return the flag status */ + return bitstatus; +} + +/******************************************************************************* +* Function Name : PWR_ClearFlag +* Description : Clears the PWR's pending flags. +* Input : - PWR_FLAG: specifies the flag to clear. +* This parameter can be one of the following values: +* - PWR_FLAG_WU: Wake Up flag +* - PWR_FLAG_SB: StandBy flag +* Output : None +* Return : None +*******************************************************************************/ +void PWR_ClearFlag(u32 PWR_FLAG) +{ + /* Check the parameters */ + assert(IS_PWR_CLEAR_FLAG(PWR_FLAG)); + + PWR->CR |= PWR_FLAG << 2; +} + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_rcc.c b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_rcc.c new file mode 100644 index 000000000..1cd00bdf7 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_rcc.c @@ -0,0 +1,1069 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_rcc.c +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file provides all the RCC firmware functions. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_rcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* ------------ RCC registers bit address in the alias region ----------- */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) + +/* --- CR Register ---*/ +/* Alias word address of HSION bit */ +#define CR_OFFSET (RCC_OFFSET + 0x00) +#define HSION_BitNumber 0x00 +#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) + +/* Alias word address of PLLON bit */ +#define PLLON_BitNumber 0x18 +#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) + +/* Alias word address of CSSON bit */ +#define CSSON_BitNumber 0x13 +#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) + +/* --- CFGR Register ---*/ +/* Alias word address of USBPRE bit */ +#define CFGR_OFFSET (RCC_OFFSET + 0x04) +#define USBPRE_BitNumber 0x16 +#define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4)) + +/* --- BDCR Register ---*/ +/* Alias word address of RTCEN bit */ +#define BDCR_OFFSET (RCC_OFFSET + 0x20) +#define RTCEN_BitNumber 0x0F +#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) + +/* Alias word address of BDRST bit */ +#define BDRST_BitNumber 0x10 +#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) + +/* --- CSR Register ---*/ +/* Alias word address of LSION bit */ +#define CSR_OFFSET (RCC_OFFSET + 0x24) +#define LSION_BitNumber 0x00 +#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) + +/* ---------------------- RCC registers bit mask ------------------------ */ +/* CR register bit mask */ +#define CR_HSEBYP_Reset ((u32)0xFFFBFFFF) +#define CR_HSEBYP_Set ((u32)0x00040000) +#define CR_HSEON_Reset ((u32)0xFFFEFFFF) +#define CR_HSEON_Set ((u32)0x00010000) +#define CR_HSITRIM_Mask ((u32)0xFFFFFF07) + +/* CFGR register bit mask */ +#define CFGR_PLL_Mask ((u32)0xFFC0FFFF) +#define CFGR_PLLMull_Mask ((u32)0x003C0000) +#define CFGR_PLLSRC_Mask ((u32)0x00010000) +#define CFGR_PLLXTPRE_Mask ((u32)0x00020000) +#define CFGR_SWS_Mask ((u32)0x0000000C) +#define CFGR_SW_Mask ((u32)0xFFFFFFFC) +#define CFGR_HPRE_Reset_Mask ((u32)0xFFFFFF0F) +#define CFGR_HPRE_Set_Mask ((u32)0x000000F0) +#define CFGR_PPRE1_Reset_Mask ((u32)0xFFFFF8FF) +#define CFGR_PPRE1_Set_Mask ((u32)0x00000700) +#define CFGR_PPRE2_Reset_Mask ((u32)0xFFFFC7FF) +#define CFGR_PPRE2_Set_Mask ((u32)0x00003800) +#define CFGR_ADCPRE_Reset_Mask ((u32)0xFFFF3FFF) +#define CFGR_ADCPRE_Set_Mask ((u32)0x0000C000) + +/* CSR register bit mask */ +#define CSR_RVMF_Set ((u32)0x01000000) + +/* RCC Flag Mask */ +#define FLAG_Mask ((u8)0x1F) + +/* Typical Value of the HSI in Hz */ +#define HSI_Value ((u32)8000000) + +/* BDCR register base address */ +#define BDCR_BASE (PERIPH_BASE + BDCR_OFFSET) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +static uc8 APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; +static uc8 ADCPrescTable[4] = {2, 4, 6, 8}; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : RCC_DeInit +* Description : Deinitializes the RCC peripheral registers to their default +* reset values. +* - The HSITRIM[4:0] bits in RCC_CR register are not modified +* by this function. +* - The RCC_BDCR and RCC_CSR registers are not reset by this +* function. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RCC_DeInit(void) +{ + /* Disable APB2 Peripheral Reset */ + RCC->APB2RSTR = 0x00000000; + + /* Disable APB1 Peripheral Reset */ + RCC->APB1RSTR = 0x00000000; + + /* FLITF and SRAM Clock ON */ + RCC->AHBENR = 0x00000014; + + /* Disable APB2 Peripheral Clock */ + RCC->APB2ENR = 0x00000000; + + /* Disable APB1 Peripheral Clock */ + RCC->APB1ENR = 0x00000000; + + /* Set HSION bit */ + RCC->CR |= (u32)0x00000001; + + /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], ADCPRE[1:0] and MCO[2:0] bits*/ + RCC->CFGR &= 0xF8FF0000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= 0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= 0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL[3:0] and USBPRE bits */ + RCC->CFGR &= 0xFF80FFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; +} + +/******************************************************************************* +* Function Name : RCC_HSEConfig +* Description : Configures the External High Speed oscillator (HSE). +* Input : - RCC_HSE: specifies the new state of the HSE. +* This parameter can be one of the following values: +* - RCC_HSE_OFF: HSE oscillator OFF +* - RCC_HSE_ON: HSE oscillator ON +* - RCC_HSE_Bypass: HSE oscillator bypassed with external +* clock +* Output : None +* Return : None +*******************************************************************************/ +void RCC_HSEConfig(u32 RCC_HSE) +{ + /* Check the parameters */ + assert(IS_RCC_HSE(RCC_HSE)); + + /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ + /* Reset HSEON bit */ + RCC->CR &= CR_HSEON_Reset; + + /* Reset HSEBYP bit */ + RCC->CR &= CR_HSEBYP_Reset; + + /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */ + switch(RCC_HSE) + { + case RCC_HSE_ON: + /* Set HSEON bit */ + RCC->CR |= CR_HSEON_Set; + break; + + case RCC_HSE_Bypass: + /* Set HSEBYP and HSEON bits */ + RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set; + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : RCC_AdjustHSICalibrationValue +* Description : Adjusts the Internal High Speed oscillator (HSI) calibration +* value. +* Input : - HSICalibrationValue: specifies the calibration trimming value. +* This parameter must be a number between 0 and 0x1F. +* Output : None +* Return : None +*******************************************************************************/ +void RCC_AdjustHSICalibrationValue(u8 HSICalibrationValue) +{ + u32 tmpreg = 0; + + /* Check the parameters */ + assert(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue)); + + tmpreg = RCC->CR; + + /* Clear HSITRIM[7:3] bits */ + tmpreg &= CR_HSITRIM_Mask; + + /* Set the HSITRIM[7:3] bits according to HSICalibrationValue value */ + tmpreg |= (u32)HSICalibrationValue << 3; + + /* Store the new value */ + RCC->CR = tmpreg; +} + +/******************************************************************************* +* Function Name : RCC_HSICmd +* Description : Enables or disables the Internal High Speed oscillator (HSI). +* HSI can not be stopped if it is used directly or through the +* PLL as system clock, or if a Flash programmation is on going. +* Input : - NewState: new state of the HSI. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void RCC_HSICmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + *(vu32 *) CR_HSION_BB = (u32)NewState; +} + +/******************************************************************************* +* Function Name : RCC_PLLConfig +* Description : Configures the PLL clock source and multiplication factor. +* This function must be used only when the PLL is disabled. +* Input : - RCC_PLLSource: specifies the PLL entry clock source. +* This parameter can be one of the following values: +* - RCC_PLLSource_HSI_Div2: HSI oscillator clock divided +* by 2 selected as PLL clock entry +* - RCC_PLLSource_HSE_Div1: HSE oscillator clock selected +* as PLL clock entry +* - RCC_PLLSource_HSE_Div2: HSE oscillator clock divided +* by 2 selected as PLL clock entry +* - RCC_PLLMul: specifies the PLL multiplication factor. +* This parameter can be RCC_PLLMul_x where x:[2,16] +* Output : None +* Return : None +*******************************************************************************/ +void RCC_PLLConfig(u32 RCC_PLLSource, u32 RCC_PLLMul) +{ + u32 tmpreg = 0; + + /* Check the parameters */ + assert(IS_RCC_PLL_SOURCE(RCC_PLLSource)); + assert(IS_RCC_PLL_MUL(RCC_PLLMul)); + + tmpreg = RCC->CFGR; + + /* Clear PLLSRC, PLLXTPRE and PLLMUL[21:18] bits */ + tmpreg &= CFGR_PLL_Mask; + + /* Set the PLL configuration bits */ + tmpreg |= RCC_PLLSource | RCC_PLLMul; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/******************************************************************************* +* Function Name : RCC_PLLCmd +* Description : Enables or disables the PLL. +* The PLL can not be disabled if it is used as system clock. +* Input : - NewState: new state of the PLL. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void RCC_PLLCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + *(vu32 *) CR_PLLON_BB = (u32)NewState; +} + +/******************************************************************************* +* Function Name : RCC_SYSCLKConfig +* Description : Configures the system clock (SYSCLK). +* Input : - RCC_SYSCLKSource: specifies the clock source used as system +* clock. This parameter can be one of the following values: +* - RCC_SYSCLKSource_HSI: HSI selected as system clock +* - RCC_SYSCLKSource_HSE: HSE selected as system clock +* - RCC_SYSCLKSource_PLLCLK: PLL selected as system clock +* Output : None +* Return : None +*******************************************************************************/ +void RCC_SYSCLKConfig(u32 RCC_SYSCLKSource) +{ + u32 tmpreg = 0; + + /* Check the parameters */ + assert(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource)); + + tmpreg = RCC->CFGR; + + /* Clear SW[1:0] bits */ + tmpreg &= CFGR_SW_Mask; + + /* Set SW[1:0] bits according to RCC_SYSCLKSource value */ + tmpreg |= RCC_SYSCLKSource; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/******************************************************************************* +* Function Name : RCC_GetSYSCLKSource +* Description : Returns the clock source used as system clock. +* Input : None +* Output : None +* Return : The clock source used as system clock. The returned value can +* be one of the following: +* - 0x00: HSI used as system clock +* - 0x04: HSE used as system clock +* - 0x08: PLL used as system clock +*******************************************************************************/ +u8 RCC_GetSYSCLKSource(void) +{ + return ((u8)(RCC->CFGR & CFGR_SWS_Mask)); +} + +/******************************************************************************* +* Function Name : RCC_HCLKConfig +* Description : Configures the AHB clock (HCLK). +* Input : - RCC_HCLK: defines the AHB clock. This clock is derived +* from the system clock (SYSCLK). +* This parameter can be one of the following values: +* - RCC_SYSCLK_Div1: AHB clock = SYSCLK +* - RCC_SYSCLK_Div2: AHB clock = SYSCLK/2 +* - RCC_SYSCLK_Div4: AHB clock = SYSCLK/4 +* - RCC_SYSCLK_Div8: AHB clock = SYSCLK/8 +* - RCC_SYSCLK_Div16: AHB clock = SYSCLK/16 +* - RCC_SYSCLK_Div64: AHB clock = SYSCLK/64 +* - RCC_SYSCLK_Div128: AHB clock = SYSCLK/128 +* - RCC_SYSCLK_Div256: AHB clock = SYSCLK/256 +* - RCC_SYSCLK_Div512: AHB clock = SYSCLK/512 +* Output : None +* Return : None +*******************************************************************************/ +void RCC_HCLKConfig(u32 RCC_HCLK) +{ + u32 tmpreg = 0; + + /* Check the parameters */ + assert(IS_RCC_HCLK(RCC_HCLK)); + + tmpreg = RCC->CFGR; + + /* Clear HPRE[7:4] bits */ + tmpreg &= CFGR_HPRE_Reset_Mask; + + /* Set HPRE[7:4] bits according to RCC_HCLK value */ + tmpreg |= RCC_HCLK; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/******************************************************************************* +* Function Name : RCC_PCLK1Config +* Description : Configures the Low Speed APB clock (PCLK1). +* Input : - RCC_PCLK1: defines the APB1 clock. This clock is derived +* from the AHB clock (HCLK). +* This parameter can be one of the following values: +* - RCC_HCLK_Div1: APB1 clock = HCLK +* - RCC_HCLK_Div2: APB1 clock = HCLK/2 +* - RCC_HCLK_Div4: APB1 clock = HCLK/4 +* - RCC_HCLK_Div8: APB1 clock = HCLK/8 +* - RCC_HCLK_Div16: APB1 clock = HCLK/16 +* Output : None +* Return : None +*******************************************************************************/ +void RCC_PCLK1Config(u32 RCC_PCLK1) +{ + u32 tmpreg = 0; + + /* Check the parameters */ + assert(IS_RCC_PCLK(RCC_PCLK1)); + + tmpreg = RCC->CFGR; + + /* Clear PPRE1[10:8] bits */ + tmpreg &= CFGR_PPRE1_Reset_Mask; + + /* Set PPRE1[10:8] bits according to RCC_PCLK1 value */ + tmpreg |= RCC_PCLK1; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/******************************************************************************* +* Function Name : RCC_PCLK2Config +* Description : Configures the High Speed APB clock (PCLK2). +* Input : - RCC_PCLK2: defines the APB2 clock. This clock is derived +* from the AHB clock (HCLK). +* This parameter can be one of the following values: +* - RCC_HCLK_Div1: APB2 clock = HCLK +* - RCC_HCLK_Div2: APB2 clock = HCLK/2 +* - RCC_HCLK_Div4: APB2 clock = HCLK/4 +* - RCC_HCLK_Div8: APB2 clock = HCLK/8 +* - RCC_HCLK_Div16: APB2 clock = HCLK/16 +* Output : None +* Return : None +*******************************************************************************/ +void RCC_PCLK2Config(u32 RCC_PCLK2) +{ + u32 tmpreg = 0; + + /* Check the parameters */ + assert(IS_RCC_PCLK(RCC_PCLK2)); + + tmpreg = RCC->CFGR; + + /* Clear PPRE2[13:11] bits */ + tmpreg &= CFGR_PPRE2_Reset_Mask; + + /* Set PPRE2[13:11] bits according to RCC_PCLK2 value */ + tmpreg |= RCC_PCLK2 << 3; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/******************************************************************************* +* Function Name : RCC_ITConfig +* Description : Enables or disables the specified RCC interrupts. +* Input : - RCC_IT: specifies the RCC interrupt sources to be enabled +* or disabled. +* This parameter can be any combination of the following values: +* - RCC_IT_LSIRDY: LSI ready interrupt +* - RCC_IT_LSERDY: LSE ready interrupt +* - RCC_IT_HSIRDY: HSI ready interrupt +* - RCC_IT_HSERDY: HSE ready interrupt +* - RCC_IT_PLLRDY: PLL ready interrupt +* - NewState: new state of the specified RCC interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void RCC_ITConfig(u8 RCC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_RCC_IT(RCC_IT)); + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Perform Byte access to RCC_CIR[12:8] bits to enable the selected interrupts */ + *(vu8 *) 0x40021009 |= RCC_IT; + } + else + { + /* Perform Byte access to RCC_CIR[12:8] bits to disable the selected interrupts */ + *(vu8 *) 0x40021009 &= ~(u32)RCC_IT; + } +} + +/******************************************************************************* +* Function Name : RCC_USBCLKConfig +* Description : Configures the USB clock (USBCLK). +* Input : - RCC_USBCLKSource: specifies the USB clock source. This clock +* is derived from the PLL output. +* This parameter can be one of the following values: +* - RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 +* selected as USB clock source +* - RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB +* clock source +* Output : None +* Return : None +*******************************************************************************/ +void RCC_USBCLKConfig(u32 RCC_USBCLKSource) +{ + /* Check the parameters */ + assert(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource)); + + *(vu32 *) CFGR_USBPRE_BB = RCC_USBCLKSource; +} + +/******************************************************************************* +* Function Name : RCC_ADCCLKConfig +* Description : Configures the ADC clock (ADCCLK). +* Input : - RCC_ADCCLK: defines the ADC clock. This clock is derived +* from the APB2 clock (PCLK2). +* This parameter can be one of the following values: +* - RCC_PCLK2_Div2: ADC clock = PCLK2/2 +* - RCC_PCLK2_Div4: ADC clock = PCLK2/4 +* - RCC_PCLK2_Div6: ADC clock = PCLK2/6 +* - RCC_PCLK2_Div8: ADC clock = PCLK2/8 +* Output : None +* Return : None +*******************************************************************************/ +void RCC_ADCCLKConfig(u32 RCC_ADCCLK) +{ + u32 tmpreg = 0; + + /* Check the parameters */ + assert(IS_RCC_ADCCLK(RCC_ADCCLK)); + + tmpreg = RCC->CFGR; + + /* Clear ADCPRE[15:14] bits */ + tmpreg &= CFGR_ADCPRE_Reset_Mask; + + /* Set ADCPRE[15:14] bits according to RCC_ADCCLK value */ + tmpreg |= RCC_ADCCLK; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/******************************************************************************* +* Function Name : RCC_LSEConfig +* Description : Configures the External Low Speed oscillator (LSE). +* Input : - RCC_LSE: specifies the new state of the LSE. +* This parameter can be one of the following values: +* - RCC_LSE_OFF: LSE oscillator OFF +* - RCC_LSE_ON: LSE oscillator ON +* - RCC_LSE_Bypass: LSE oscillator bypassed with external +* clock +* Output : None +* Return : None +*******************************************************************************/ +void RCC_LSEConfig(u32 RCC_LSE) +{ + /* Check the parameters */ + assert(IS_RCC_LSE(RCC_LSE)); + + /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/ + /* Reset LSEON bit */ + *(vu8 *) BDCR_BASE = RCC_LSE_OFF; + + /* Reset LSEBYP bit */ + *(vu8 *) BDCR_BASE = RCC_LSE_OFF; + + /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */ + switch(RCC_LSE) + { + case RCC_LSE_ON: + /* Set LSEON bit */ + *(vu8 *) BDCR_BASE = RCC_LSE_ON; + break; + + case RCC_LSE_Bypass: + /* Set LSEBYP and LSEON bits */ + *(vu8 *) BDCR_BASE = RCC_LSE_Bypass | RCC_LSE_ON; + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : RCC_LSICmd +* Description : Enables or disables the Internal Low Speed oscillator (LSI). +* LSI can not be disabled if the IWDG is running. +* Input : - NewState: new state of the LSI. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void RCC_LSICmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + *(vu32 *) CSR_LSION_BB = (u32)NewState; +} + +/******************************************************************************* +* Function Name : RCC_RTCCLKConfig +* Description : Configures the RTC clock (RTCCLK). +* Once the RTC clock is selected it can’t be changed unless the +* Backup domain is reset. +* Input : - RCC_RTCCLKSource: specifies the RTC clock source. +* This parameter can be one of the following values: +* - RCC_RTCCLKSource_LSE: LSE oscillator clock used as RTC +* clock +* - RCC_RTCCLKSource_LSI: LSI oscillator clock used as RTC +* clock +* - RCC_RTCCLKSource_HSE_Div128: HSE oscillator clock divided +* by 128 used as RTC clock +* Output : None +* Return : None +*******************************************************************************/ +void RCC_RTCCLKConfig(u32 RCC_RTCCLKSource) +{ + /* Check the parameters */ + assert(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource)); + + /* Select the RTC clock source */ + RCC->BDCR |= RCC_RTCCLKSource; +} + +/******************************************************************************* +* Function Name : RCC_RTCCLKCmd +* Description : Enables or disables the RTC clock. +* This function must be used only after the RTC clock was +* selected using the RCC_RTCCLKConfig function. +* Input : - NewState: new state of the RTC clock. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void RCC_RTCCLKCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + *(vu32 *) BDCR_RTCEN_BB = (u32)NewState; +} + +/******************************************************************************* +* Function Name : RCC_GetClocksFreq +* Description : Returns the frequencies of different on chip clocks. +* Input : - RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which +* will hold the clocks frequencies. +* Output : None +* Return : None +*******************************************************************************/ +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) +{ + u32 tmp = 0, pllmull = 0, pllsource = 0, presc = 0; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & CFGR_SWS_Mask; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + RCC_Clocks->SYSCLK_Frequency = HSI_Value; + break; + + case 0x04: /* HSE used as system clock */ + RCC_Clocks->SYSCLK_Frequency = HSE_Value; + break; + + case 0x08: /* PLL used as system clock */ + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & CFGR_PLLMull_Mask; + pllmull = ( pllmull >> 18) + 2; + + pllsource = RCC->CFGR & CFGR_PLLSRC_Mask; + + if (pllsource == 0x00) + {/* HSI oscillator clock divided by 2 selected as PLL clock entry */ + RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull; + } + else + {/* HSE selected as PLL clock entry */ + + if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (u32)RESET) + {/* HSE oscillator clock divided by 2 */ + + RCC_Clocks->SYSCLK_Frequency = (HSE_Value >> 1) * pllmull; + } + else + { + RCC_Clocks->SYSCLK_Frequency = HSE_Value * pllmull; + } + } + break; + + default: + RCC_Clocks->SYSCLK_Frequency = HSI_Value; + break; + } + + /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/ + /* Get HCLK prescaler */ + tmp = RCC->CFGR & CFGR_HPRE_Set_Mask; + tmp = tmp >> 4; + presc = APBAHBPrescTable[tmp]; + + /* HCLK clock frequency */ + RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; + + /* Get PCLK1 prescaler */ + tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask; + tmp = tmp >> 8; + presc = APBAHBPrescTable[tmp]; + + /* PCLK1 clock frequency */ + RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + + /* Get PCLK2 prescaler */ + tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask; + tmp = tmp >> 11; + presc = APBAHBPrescTable[tmp]; + + /* PCLK2 clock frequency */ + RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + + /* Get ADCCLK prescaler */ + tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask; + tmp = tmp >> 14; + presc = ADCPrescTable[tmp]; + + /* ADCCLK clock frequency */ + RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc; +} + +/******************************************************************************* +* Function Name : RCC_AHBPeriphClockCmd +* Description : Enables or disables the AHB peripheral clock. +* Input : - RCC_AHBPeriph: specifies the AHB peripheral to gates its clock. +* This parameter can be any combination of the following values: +* - RCC_AHBPeriph_DMA +* - RCC_AHBPeriph_SRAM +* - RCC_AHBPeriph_FLITF +* SRAM and FLITF clock can be disabled only during sleep mode. +* - NewState: new state of the specified peripheral clock. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void RCC_AHBPeriphClockCmd(u32 RCC_AHBPeriph, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_RCC_AHB_PERIPH(RCC_AHBPeriph)); + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHBENR |= RCC_AHBPeriph; + } + else + { + RCC->AHBENR &= ~RCC_AHBPeriph; + } +} + +/******************************************************************************* +* Function Name : RCC_APB2PeriphClockCmd +* Description : Enables or disables the High Speed APB (APB2) peripheral clock. +* Input : - RCC_APB2Periph: specifies the APB2 peripheral to gates its +* clock. +* This parameter can be any combination of the following values: +* - RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB +* RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE +* RCC_APB2Periph_ADC1, RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1 +* RCC_APB2Periph_SPI1, RCC_APB2Periph_USART1, RCC_APB2Periph_ALL +* - NewState: new state of the specified peripheral clock. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void RCC_APB2PeriphClockCmd(u32 RCC_APB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->APB2ENR |= RCC_APB2Periph; + } + else + { + RCC->APB2ENR &= ~RCC_APB2Periph; + } +} + +/******************************************************************************* +* Function Name : RCC_APB1PeriphClockCmd +* Description : Enables or disables the Low Speed APB (APB1) peripheral clock. +* Input : - RCC_APB1Periph: specifies the APB1 peripheral to gates its +* clock. +* This parameter can be any combination of the following values: +* - RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4 +* RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_USART2 +* RCC_APB1Periph_USART3, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2 +* RCC_APB1Periph_USB, RCC_APB1Periph_CAN, RCC_APB1Periph_BKP +* RCC_APB1Periph_PWR, RCC_APB1Periph_ALL +* - NewState: new state of the specified peripheral clock. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void RCC_APB1PeriphClockCmd(u32 RCC_APB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->APB1ENR |= RCC_APB1Periph; + } + else + { + RCC->APB1ENR &= ~RCC_APB1Periph; + } +} + +/******************************************************************************* +* Function Name : RCC_APB2PeriphResetCmd +* Description : Forces or releases High Speed APB (APB2) peripheral reset. +* Input : - RCC_APB2Periph: specifies the APB2 peripheral to reset. +* This parameter can be any combination of the following values: +* - RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB +* RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE +* RCC_APB2Periph_ADC1, RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1 +* RCC_APB2Periph_SPI1, RCC_APB2Periph_USART1, RCC_APB2Periph_ALL +* - NewState: new state of the specified peripheral reset. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void RCC_APB2PeriphResetCmd(u32 RCC_APB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->APB2RSTR |= RCC_APB2Periph; + } + else + { + RCC->APB2RSTR &= ~RCC_APB2Periph; + } +} + +/******************************************************************************* +* Function Name : RCC_APB1PeriphResetCmd +* Description : Forces or releases Low Speed APB (APB1) peripheral reset. +* Input : - RCC_APB1Periph: specifies the APB1 peripheral to reset. +* This parameter can be any combination of the following values: +* - RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4 +* RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_USART2 +* RCC_APB1Periph_USART3, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2 +* RCC_APB1Periph_USB, RCC_APB1Periph_CAN, RCC_APB1Periph_BKP +* RCC_APB1Periph_PWR, RCC_APB1Periph_ALL +* - NewState: new state of the specified peripheral clock. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void RCC_APB1PeriphResetCmd(u32 RCC_APB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->APB1RSTR |= RCC_APB1Periph; + } + else + { + RCC->APB1RSTR &= ~RCC_APB1Periph; + } +} + +/******************************************************************************* +* Function Name : RCC_BackupResetCmd +* Description : Forces or releases the Backup domain reset. +* Input : - NewState: new state of the Backup domain reset. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void RCC_BackupResetCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + *(vu32 *) BDCR_BDRST_BB = (u32)NewState; +} + +/******************************************************************************* +* Function Name : RCC_ClockSecuritySystemCmd +* Description : Enables or disables the Clock Security System. +* Input : - NewState: new state of the Clock Security System.. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void RCC_ClockSecuritySystemCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + *(vu32 *) CR_CSSON_BB = (u32)NewState; +} + +/******************************************************************************* +* Function Name : RCC_MCOConfig +* Description : Selects the clock source to output on MCO pin. +* Input : - RCC_MCO: specifies the clock source to output. +* This parameter can be one of the following values: +* - RCC_MCO_NoClock: No clock selected +* - RCC_MCO_SYSCLK: System clock selected +* - RCC_MCO_HSI: HSI oscillator clock selected +* - RCC_MCO_HSE: HSE oscillator clock selected +* - RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected +* Output : None +* Return : None +*******************************************************************************/ +void RCC_MCOConfig(u8 RCC_MCO) +{ + /* Check the parameters */ + assert(IS_RCC_MCO(RCC_MCO)); + + /* Perform Byte access to MCO[26:24] bits to select the MCO source */ + *(vu8 *) 0x40021007 = RCC_MCO; +} + +/******************************************************************************* +* Function Name : RCC_GetFlagStatus +* Description : Checks whether the specified RCC flag is set or not. +* Input : - RCC_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - RCC_FLAG_HSIRDY: HSI oscillator clock ready +* - RCC_FLAG_HSERDY: HSE oscillator clock ready +* - RCC_FLAG_PLLRDY: PLL clock ready +* - RCC_FLAG_LSERDY: LSE oscillator clock ready +* - RCC_FLAG_LSIRDY: LSI oscillator clock ready +* - RCC_FLAG_PINRST: Pin reset +* - RCC_FLAG_PORRST: POR/PDR reset +* - RCC_FLAG_SFTRST: Software reset +* - RCC_FLAG_IWDGRST: Independent Watchdog reset +* - RCC_FLAG_WWDGRST: Window Watchdog reset +* - RCC_FLAG_LPWRRST: Low Power reset +* Output : None +* Return : The new state of RCC_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus RCC_GetFlagStatus(u8 RCC_FLAG) +{ + u32 tmp = 0; + u32 statusreg = 0; + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert(IS_RCC_FLAG(RCC_FLAG)); + + /* Get the RCC register index */ + tmp = RCC_FLAG >> 5; + + if (tmp == 1) /* The flag to check is in CR register */ + { + statusreg = RCC->CR; + } + else if (tmp == 2) /* The flag to check is in BDCR register */ + { + statusreg = RCC->BDCR; + } + else /* The flag to check is in CSR register */ + { + statusreg = RCC->CSR; + } + + /* Get the flag position */ + tmp = RCC_FLAG & FLAG_Mask; + + if ((statusreg & ((u32)1 << tmp)) != (u32)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + /* Return the flag status */ + return bitstatus; +} + +/******************************************************************************* +* Function Name : RCC_ClearFlag +* Description : Clears the RCC reset flags. +* The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, +* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, +* RCC_FLAG_LPWRRST +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RCC_ClearFlag(void) +{ + /* Set RVMF bit to clear the reset flags */ + RCC->CSR |= CSR_RVMF_Set; +} + +/******************************************************************************* +* Function Name : RCC_GetITStatus +* Description : Checks whether the specified RCC interrupt has occurred or not. +* Input : - RCC_IT: specifies the RCC interrupt source to check. +* This parameter can be one of the following values: +* - RCC_IT_LSIRDY: LSI ready interrupt +* - RCC_IT_LSERDY: LSE ready interrupt +* - RCC_IT_HSIRDY: HSI ready interrupt +* - RCC_IT_HSERDY: HSE ready interrupt +* - RCC_IT_PLLRDY: PLL ready interrupt +* - RCC_IT_CSS: Clock Security System interrupt +* Output : None +* Return : The new state of RCC_IT (SET or RESET). +*******************************************************************************/ +ITStatus RCC_GetITStatus(u8 RCC_IT) +{ + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert(IS_RCC_GET_IT(RCC_IT)); + + /* Check the status of the specified RCC interrupt */ + if ((RCC->CIR & RCC_IT) != (u32)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + /* Return the RCC_IT status */ + return bitstatus; +} + +/******************************************************************************* +* Function Name : RCC_ClearITPendingBit +* Description : Clears the RCC’s interrupt pending bits. +* Input : - RCC_IT: specifies the interrupt pending bit to clear. +* This parameter can be any combination of the following values: +* - RCC_IT_LSIRDY: LSI ready interrupt +* - RCC_IT_LSERDY: LSE ready interrupt +* - RCC_IT_HSIRDY: HSI ready interrupt +* - RCC_IT_HSERDY: HSE ready interrupt +* - RCC_IT_PLLRDY: PLL ready interrupt +* - RCC_IT_CSS: Clock Security System interrupt +* Output : None +* Return : None +*******************************************************************************/ +void RCC_ClearITPendingBit(u8 RCC_IT) +{ + /* Check the parameters */ + assert(IS_RCC_CLEAR_IT(RCC_IT)); + + /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt + pending bits */ + *(vu8 *) 0x4002100A = RCC_IT; +} + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_rtc.c b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_rtc.c new file mode 100644 index 000000000..21637910c --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_rtc.c @@ -0,0 +1,342 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_rtc.c +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file provides all the RTC firmware functions. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_rtc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define CRL_CNF_Set ((u16)0x0010) /* Configuration Flag Enable Mask */ +#define CRL_CNF_Reset ((u16)0xFFEF) /* Configuration Flag Disable Mask */ +#define RTC_LSB_Mask ((u32)0x0000FFFF) /* RTC LSB Mask */ +#define RTC_MSB_Mask ((u32)0xFFFF0000) /* RTC MSB Mask */ +#define PRLH_MSB_Mask ((u32)0x000F0000) /* RTC Prescaler MSB Mask */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : RTC_ITConfig +* Description : Enables or disables the specified RTC interrupts. +* Input : - RTC_IT: specifies the RTC interrupts sources to be enabled +* or disabled. +* This parameter can be any combination of the following values: +* - RTC_IT_OW: Overflow interrupt +* - RTC_IT_ALR: Alarm interrupt +* - RTC_IT_SEC: Second interrupt +* - NewState: new state of the specified RTC interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void RTC_ITConfig(u16 RTC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_RTC_IT(RTC_IT)); + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RTC->CRH |= RTC_IT; + } + else + { + RTC->CRH &= (u16)~RTC_IT; + } +} + +/******************************************************************************* +* Function Name : RTC_EnterConfigMode +* Description : Enters the RTC configuration mode. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RTC_EnterConfigMode(void) +{ + /* Set the CNF flag to enter in the Configuration Mode */ + RTC->CRL |= CRL_CNF_Set; +} + +/******************************************************************************* +* Function Name : RTC_ExitConfigMode +* Description : Exits from the RTC configuration mode. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RTC_ExitConfigMode(void) +{ + /* Reset the CNF flag to exit from the Configuration Mode */ + RTC->CRL &= CRL_CNF_Reset; +} + +/******************************************************************************* +* Function Name : RTC_GetCounter +* Description : Gets the RTC counter value. +* Input : None +* Output : None +* Return : RTC counter value. +*******************************************************************************/ +u32 RTC_GetCounter(void) +{ + u16 tmp = 0; + tmp = RTC->CNTL; + + return (((u32)RTC->CNTH << 16 ) | tmp) ; +} + +/******************************************************************************* +* Function Name : RTC_SetCounter +* Description : Sets the RTC counter value. +* Input : - CounterValue: RTC counter new value. +* Output : None +* Return : None +*******************************************************************************/ +void RTC_SetCounter(u32 CounterValue) +{ + RTC_EnterConfigMode(); + + /* Set RTC COUNTER MSB word */ + RTC->CNTH = (CounterValue & RTC_MSB_Mask) >> 16; + /* Set RTC COUNTER LSB word */ + RTC->CNTL = (CounterValue & RTC_LSB_Mask); + + RTC_ExitConfigMode(); +} + +/******************************************************************************* +* Function Name : RTC_GetPrescaler +* Description : Gets the RTC prescaler value. +* Input : None +* Output : None +* Return : RTC prescaler value. +*******************************************************************************/ +u32 RTC_GetPrescaler(void) +{ + u32 tmp = 0x00; + + tmp = ((u32)RTC->PRLH & (u32)0x000F) << 0x10; + tmp |= RTC->PRLL; + + return tmp; +} + +/******************************************************************************* +* Function Name : RTC_SetPrescaler +* Description : Sets the RTC prescaler value. +* Input : - PrescalerValue: RTC prescaler new value. +* Output : None +* Return : None +*******************************************************************************/ +void RTC_SetPrescaler(u32 PrescalerValue) +{ + /* Check the parameters */ + assert(IS_RTC_PRESCALER(PrescalerValue)); + + RTC_EnterConfigMode(); + + /* Set RTC PRESCALER MSB word */ + RTC->PRLH = (PrescalerValue & PRLH_MSB_Mask) >> 0x10; + /* Set RTC PRESCALER LSB word */ + RTC->PRLL = (PrescalerValue & RTC_LSB_Mask); + + RTC_ExitConfigMode(); +} + +/******************************************************************************* +* Function Name : RTC_SetAlarm +* Description : Sets the RTC alarm value. +* Input : - AlarmValue: RTC alarm new value. +* Output : None +* Return : None +*******************************************************************************/ +void RTC_SetAlarm(u32 AlarmValue) +{ + RTC_EnterConfigMode(); + + /* Set the ALARM MSB word */ + RTC->ALRH = (AlarmValue & RTC_MSB_Mask) >> 16; + /* Set the ALARM LSB word */ + RTC->ALRL = (AlarmValue & RTC_LSB_Mask); + + RTC_ExitConfigMode(); +} + +/******************************************************************************* +* Function Name : RTC_GetDivider +* Description : Gets the RTC divider value. +* Input : None +* Output : None +* Return : RTC Divider value. +*******************************************************************************/ +u32 RTC_GetDivider(void) +{ + u32 tmp = 0x00; + + tmp = ((u32)RTC->DIVH & (u32)0x000F) << 0x10; + tmp |= RTC->DIVL; + + return tmp; +} + +/******************************************************************************* +* Function Name : RTC_WaitForLastTask +* Description : Waits until last write operation on RTC registers has finished. +* This function must be called before any write to RTC registers. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RTC_WaitForLastTask(void) +{ + /* Loop until RTOFF flag is set */ + while ((RTC->CRL & RTC_FLAG_RTOFF) == (u16)RESET) + { + } +} + +/******************************************************************************* +* Function Name : RTC_WaitForSynchro +* Description : Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL) +* are synchronized with RTC APB clock. +* This function must be called before any read operation after +* an APB reset or an APB clock stop. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RTC_WaitForSynchro(void) +{ + /* Clear RSF flag */ + RTC->CRL &= (u16)~RTC_FLAG_RSF; + + /* Loop until RSF flag is set */ + while ((RTC->CRL & RTC_FLAG_RSF) == (u16)RESET) + { + } +} + +/******************************************************************************* +* Function Name : RTC_GetFlagStatus +* Description : Checks whether the specified RTC flag is set or not. +* Input : - RTC_FLAG: specifies the flag to check. +* This parameter can be one the following values: +* - RTC_FLAG_RTOFF: RTC Operation OFF flag +* - RTC_FLAG_RSF: Registers Synchronized flag +* - RTC_FLAG_OW: Overflow flag +* - RTC_FLAG_ALR: Alarm flag +* - RTC_FLAG_SEC: Second flag +* Output : None +* Return : The new state of RTC_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus RTC_GetFlagStatus(u16 RTC_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert(IS_RTC_GET_FLAG(RTC_FLAG)); + + if ((RTC->CRL & RTC_FLAG) != (u16)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : RTC_ClearFlag +* Description : Clears the RTC’s pending flags. +* Input : - RTC_FLAG: specifies the flag to clear. +* This parameter can be any combination of the following values: +* - RTC_FLAG_RSF: Registers Synchronized flag. This flag +* is cleared only after an APB reset or an APB Clock stop. +* - RTC_FLAG_OW: Overflow flag +* - RTC_FLAG_ALR: Alarm flag +* - RTC_FLAG_SEC: Second flag +* Output : None +* Return : None +*******************************************************************************/ +void RTC_ClearFlag(u16 RTC_FLAG) +{ + /* Check the parameters */ + assert(IS_RTC_CLEAR_FLAG(RTC_FLAG)); + + /* Clear the coressponding RTC flag */ + RTC->CRL &= (u16)~RTC_FLAG; +} + +/******************************************************************************* +* Function Name : RTC_GetITStatus +* Description : Checks whether the specified RTC interrupt has occured or not. +* Input : - RTC_IT: specifies the RTC interrupts sources to check. +* This parameter can be one of the following values: +* - RTC_IT_OW: Overflow interrupt +* - RTC_IT_ALR: Alarm interrupt +* - RTC_IT_SEC: Second interrupt +* Output : None +* Return : The new state of the RTC_IT (SET or RESET). +*******************************************************************************/ +ITStatus RTC_GetITStatus(u16 RTC_IT) +{ + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert(IS_RTC_GET_IT(RTC_IT)); + + bitstatus = (ITStatus)((RTC->CRL & RTC_IT) != (u16)RESET); + + if (((RTC->CRH & RTC_IT) != (u16)RESET) && bitstatus) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : RTC_ClearITPendingBit +* Description : Clears the RTC’s interrupt pending bits. +* Input : - RTC_IT: specifies the interrupt pending bit to clear. +* This parameter can be any combination of the following values: +* - RTC_IT_OW: Overflow interrupt +* - RTC_IT_ALR: Alarm interrupt +* - RTC_IT_SEC: Second interrupt +* Output : None +* Return : None +*******************************************************************************/ +void RTC_ClearITPendingBit(u16 RTC_IT) +{ + /* Check the parameters */ + assert(IS_RTC_IT(RTC_IT)); + + /* Clear the coressponding RTC pending bit */ + RTC->CRL &= (u16)~RTC_IT; +} + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_spi.c b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_spi.c new file mode 100644 index 000000000..ae507dccd --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_spi.c @@ -0,0 +1,658 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_spi.c +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file provides all the SPI firmware functions. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_spi.h" +#include "stm32f10x_rcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* SPI SPE mask */ +#define CR1_SPE_Set ((u16)0x0040) +#define CR1_SPE_Reset ((u16)0xFFBF) + +/* SPI CRCNext mask */ +#define CR1_CRCNext_Set ((u16)0x1000) + +/* SPI CRCEN mask */ +#define CR1_CRCEN_Set ((u16)0x2000) +#define CR1_CRCEN_Reset ((u16)0xDFFF) + +/* SPI SSOE mask */ +#define CR2_SSOE_Set ((u16)0x0004) +#define CR2_SSOE_Reset ((u16)0xFFFB) + +/* SPI registers Masks */ +#define CR1_CLEAR_Mask ((u16)0x3040) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : SPI_DeInit +* Description : Deinitializes the SPIx peripheral registers to their default +* reset values. +* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void SPI_DeInit(SPI_TypeDef* SPIx) +{ + switch (*(u32*)&SPIx) + { + case SPI1_BASE: + /* Enable SPI1 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); + /* Release SPI1 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); + break; + + case SPI2_BASE: + /* Enable SPI2 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); + /* Release SPI2 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : SPI_Init +* Description : Initializes the SPIx according to the specified parameters +* in the SPI_InitStruct. +* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral. +* - SPI_InitStruct: pointer to a SPI_InitTypeDef structure that +* contains the configuration information for the specified +* SPI peripheral. +* Output : None +* Return : None +******************************************************************************/ +void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) +{ + u16 tmpreg = 0; + + /* Check the parameters */ + assert(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction)); + assert(IS_SPI_MODE(SPI_InitStruct->SPI_Mode)); + assert(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize)); + assert(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL)); + assert(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA)); + assert(IS_SPI_NSS(SPI_InitStruct->SPI_NSS)); + assert(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler)); + assert(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit)); + assert(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial)); + +/*---------------------------- SPIx CR1 Configuration ------------------------*/ + /* Get the SPIx CR1 value */ + tmpreg = SPIx->CR1; + /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */ + tmpreg &= CR1_CLEAR_Mask; + /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler + master/salve mode, CPOL and CPHA */ + /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */ + /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */ + /* Set LSBFirst bit according to SPI_FirstBit value */ + /* Set BR bits according to SPI_BaudRatePrescaler value */ + /* Set CPOL bit according to SPI_CPOL value */ + /* Set CPHA bit according to SPI_CPHA value */ + tmpreg |= (u16)((u32)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | + SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | + SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | + SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); + /* Write to SPIx CR1 */ + SPIx->CR1 = tmpreg; + +/*---------------------------- SPIx CRCPOLY Configuration --------------------*/ + /* Write to SPIx CRCPOLY */ + SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial; +} + +/******************************************************************************* +* Function Name : SPI_StructInit +* Description : Fills each SPI_InitStruct member with its default value. +* Input : - SPI_InitStruct : pointer to a SPI_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct) +{ +/*--------------- Reset SPI init structure parameters values -----------------*/ + /* Initialize the SPI_Direction member */ + SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; + + /* initialize the SPI_Mode member */ + SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; + + /* initialize the SPI_DataSize member */ + SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; + + /* Initialize the SPI_CPOL member */ + SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; + + /* Initialize the SPI_CPHA member */ + SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; + + /* Initialize the SPI_NSS member */ + SPI_InitStruct->SPI_NSS = SPI_NSS_Hard; + + /* Initialize the SPI_BaudRatePrescaler member */ + SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; + + /* Initialize the SPI_FirstBit member */ + SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; + + /* Initialize the SPI_CRCPolynomial member */ + SPI_InitStruct->SPI_CRCPolynomial = 7; +} + +/******************************************************************************* +* Function Name : SPI_Cmd +* Description : Enables or disables the specified SPI peripheral. +* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral. +* - NewState: new state of the SPIx peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected SPI peripheral */ + SPIx->CR1 |= CR1_SPE_Set; + } + else + { + /* Disable the selected SPI peripheral */ + SPIx->CR1 &= CR1_SPE_Reset; + } +} + +/******************************************************************************* +* Function Name : SPI_ITConfig +* Description : Enables or disables the specified SPI interrupts. +* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral. +* - SPI_IT: specifies the SPI interrupts sources to be enabled +* or disabled. +* This parameter can be one of the following values: +* - SPI_IT_TXE: Tx buffer empty interrupt mask +* - SPI_IT_RXNE: Rx buffer not empty interrupt mask +* - SPI_IT_ERR: Error interrupt mask +* - NewState: new state of the specified SPI interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SPI_ITConfig(SPI_TypeDef* SPIx, u8 SPI_IT, FunctionalState NewState) +{ + u16 itpos = 0, itmask = 0 ; + + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + assert(IS_SPI_CONFIG_IT(SPI_IT)); + + /* Get the SPI IT index */ + itpos = SPI_IT >> 4; + /* Set the IT mask */ + itmask = (u16)((u16)1 << itpos); + + if (NewState != DISABLE) + { + /* Enable the selected SPI interrupt */ + SPIx->CR2 |= itmask; + } + else + { + /* Disable the selected SPI interrupt */ + SPIx->CR2 &= (u16)~itmask; + } +} + +/******************************************************************************* +* Function Name : SPI_DMACmd +* Description : Enables or disables the SPIx’s DMA interface. +* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral. +* - SPI_DMAReq: specifies the SPI DMA transfer request to be +* enabled or disabled. +* This parameter can be any combination of the following values: +* - SPI_DMAReq_Tx: Tx buffer DMA transfer request +* - SPI_DMAReq_Rx: Rx buffer DMA transfer request +* - NewState: new state of the selected SPI DMA transfer request. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SPI_DMACmd(SPI_TypeDef* SPIx, u16 SPI_DMAReq, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + assert(IS_SPI_DMA_REQ(SPI_DMAReq)); + + if (NewState != DISABLE) + { + /* Enable the selected SPI DMA requests */ + SPIx->CR2 |= SPI_DMAReq; + } + else + { + /* Disable the selected SPI DMA requests */ + SPIx->CR2 &= (u16)~SPI_DMAReq; + } +} + +/******************************************************************************* +* Function Name : SPI_SendData +* Description : Transmits a Data through the SPIx peripheral. +* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral. +* - Data : Data to be transmitted.. +* Output : None +* Return : None +*******************************************************************************/ +void SPI_SendData(SPI_TypeDef* SPIx, u16 Data) +{ + /* Write in the DR register the data to be sent */ + SPIx->DR = Data; +} + +/******************************************************************************* +* Function Name : SPI_ReceiveData +* Description : Returns the most recent received data by the SPIx peripheral. +* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral. +* Output : None +* Return : The value of the received data. +*******************************************************************************/ +u16 SPI_ReceiveData(SPI_TypeDef* SPIx) +{ + /* Return the data in the DR register */ + return SPIx->DR; +} + +/******************************************************************************* +* Function Name : SPI_NSSInternalSoftwareConfig +* Description : Configures internally by software the NSS pin for the selected +* SPI. +* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral. +* - SPI_NSSInternalSoft: specifies the SPI NSS internal state. +* This parameter can be one of the following values: +* - SPI_NSSInternalSoft_Set: Set NSS pin internally +* - SPI_NSSInternalSoft_Reset: Reset NSS pin internally +* Output : None +* Return : None +*******************************************************************************/ +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, u16 SPI_NSSInternalSoft) +{ + /* Check the parameters */ + assert(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft)); + + if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) + { + /* Set NSS pin internally by software */ + SPIx->CR1 |= SPI_NSSInternalSoft_Set; + } + else + { + /* Reset NSS pin internally by software */ + SPIx->CR1 &= SPI_NSSInternalSoft_Reset; + } +} + +/******************************************************************************* +* Function Name : SPI_SSOutputCmd +* Description : Enables or disables the SS output for the selected SPI. +* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral. +* - NewState: new state of the SPIx SS output. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected SPI SS output */ + SPIx->CR2 |= CR2_SSOE_Set; + } + else + { + /* Disable the selected SPI SS output */ + SPIx->CR2 &= CR2_SSOE_Reset; + } +} + +/******************************************************************************* +* Function Name : SPI_DataSizeConfig +* Description : Configures the data size for the selected SPI. +* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral. +* - SPI_DataSize: specifies the SPI data size. +* This parameter can be one of the following values: +* - SPI_DataSize_16b: Set data frame format to 16bit +* - SPI_DataSize_8b: Set data frame format to 8bit +* Output : None +* Return : None +*******************************************************************************/ +void SPI_DataSizeConfig(SPI_TypeDef* SPIx, u16 SPI_DataSize) +{ + /* Check the parameters */ + assert(IS_SPI_DATASIZE(SPI_DataSize)); + + if (SPI_DataSize != SPI_DataSize_8b) + { + /* Set data frame format to 16bit */ + SPIx->CR1 |= SPI_DataSize_16b; + } + else + { + /* Set data frame format to 8bit */ + SPIx->CR1 &= SPI_DataSize_8b; + } +} + +/******************************************************************************* +* Function Name : SPI_TransmitCRC +* Description : Transmit the SPIx CRC value. +* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void SPI_TransmitCRC(SPI_TypeDef* SPIx) +{ + /* Enable the selected SPI CRC transmission */ + SPIx->CR1 |= CR1_CRCNext_Set; +} + +/******************************************************************************* +* Function Name : SPI_CalculateCRC +* Description : Enables or disables the CRC value calculation of the +* transfered bytes. +* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral. +* - NewState: new state of the SPIx CRC value calculation. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected SPI CRC calculation */ + SPIx->CR1 |= CR1_CRCEN_Set; + } + else + { + /* Disable the selected SPI CRC calculation */ + SPIx->CR1 &= CR1_CRCEN_Reset; + } +} + +/******************************************************************************* +* Function Name : SPI_GetCRC +* Description : Returns the transmit or the receive CRC register value for +* the specified SPI. +* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral. +* - SPI_CRC: specifies the CRC register to be read. +* This parameter can be one of the following values: +* - SPI_CRC_Tx: Selects Tx CRC register +* - SPI_CRC_Rx: Selects Rx CRC register +* Output : None +* Return : The selected CRC register value.. +*******************************************************************************/ +u16 SPI_GetCRC(SPI_TypeDef* SPIx, u8 SPI_CRC) +{ + u16 crcreg = 0; + + /* Check the parameters */ + assert(IS_SPI_CRC(SPI_CRC)); + + if (SPI_CRC != SPI_CRC_Rx) + { + /* Get the Tx CRC register */ + crcreg = SPIx->TXCRCR; + } + else + { + /* Get the Rx CRC register */ + crcreg = SPIx->RXCRCR; + } + + /* Return the selected CRC register */ + return crcreg; +} + +/******************************************************************************* +* Function Name : SPI_GetCRCPolynomial +* Description : Returns the CRC Polynomial register value for the specified SPI. +* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral. +* Output : None +* Return : The CRC Polynomial register value. +*******************************************************************************/ +u16 SPI_GetCRCPolynomial(SPI_TypeDef* SPIx) +{ + /* Return the CRC polynomial register */ + return SPIx->CRCPR; +} + +/******************************************************************************* +* Function Name : SPI_BiDirectionalLineConfig +* Description : Selects the data transfer direction in bi-directional mode +* for the specified SPI. +* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral. +* - SPI_Direction: specifies the data transfer direction in +* bi-directional mode. +* This parameter can be one of the following values: +* - SPI_Direction_Tx: Selects Tx transmission direction +* - SPI_Direction_Rx: Selects Rx receive direction +* Output : None +* Return : None +*******************************************************************************/ +void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, u16 SPI_Direction) +{ + /* Check the parameters */ + assert(IS_SPI_DIRECTION(SPI_Direction)); + + if (SPI_Direction == SPI_Direction_Tx) + { + /* Set the Tx only mode */ + SPIx->CR1 |= SPI_Direction_Tx; + } + else + { + /* Set the Rx only mode */ + SPIx->CR1 &= SPI_Direction_Rx; + } +} + +/******************************************************************************* +* Function Name : SPI_GetFlagStatus +* Description : Checks whether the specified SPI flag is set or not. +* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral. +* - SPI_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - SPI_FLAG_BSY: Busy flag. +* - SPI_FLAG_OVR: Overrun flag. +* - SPI_FLAG_MODF: Mode Fault flag. +* - SPI_FLAG_CRCERR: CRC Error flag. +* - SPI_FLAG_TXE: Transmit buffer empty flag. +* - SPI_FLAG_RXNE: Receive buffer not empty flag. +* Output : None +* Return : The new state of SPI_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus SPI_GetFlagStatus(SPI_TypeDef* SPIx, u16 SPI_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert(IS_SPI_GET_FLAG(SPI_FLAG)); + + /* Check the status of the specified SPI flag */ + if ((SPIx->SR & SPI_FLAG) != (u16)RESET) + { + /* SPI_FLAG is set */ + bitstatus = SET; + } + else + { + /* SPI_FLAG is reset */ + bitstatus = RESET; + } + /* Return the SPI_FLAG status */ + return bitstatus; +} + +/******************************************************************************* +* Function Name : SPI_ClearFlag +* Description : Clears the SPIx's pending flags. +* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral. +* - SPI_FLAG: specifies the flag to clear. +* This parameter can be any combination of the following values: +* - SPI_FLAG_OVR: Overrun flag. +* - SPI_FLAG_MODF: Mode Fault flag. +* - SPI_FLAG_CRCERR: CRC Error flag. +* Output : None +* Return : None +*******************************************************************************/ +void SPI_ClearFlag(SPI_TypeDef* SPIx, u16 SPI_FLAG) +{ + /* Check the parameters */ + assert(IS_SPI_CLEAR_FLAG(SPI_FLAG)); + + /* SPI_FLAG_MODF flag clear */ + if(SPI_FLAG == SPI_FLAG_MODF) + { + /* Read SR register */ + (void)SPIx->SR; + /* Write on CR1 register */ + SPIx->CR1 |= CR1_SPE_Set; + } + /* SPI_FLAG_OVR flag clear */ + else if(SPI_FLAG == SPI_FLAG_OVR) + { + /* Read SR register */ + (void)SPIx->SR; + } + else /* SPI_FLAG_CRCERR flag clear */ + { + /* Clear the selected SPI flag */ + SPIx->SR &= (u16)~SPI_FLAG; + } +} + +/******************************************************************************* +* Function Name : SPI_GetITStatus +* Description : Checks whether the specified SPI interrupt has occurred or not. +* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral. +* - SPI_IT: specifies the SPI interrupt source to check. +* This parameter can be one of the following values: +* - SPI_IT_OVR: Overrun interrupt. +* - SPI_IT_MODF: Mode Fault interrupt. +* - SPI_IT_CRCERR: CRC Error interrupt. +* - SPI_IT_TXE: Transmit buffer empty interrupt. +* - SPI_IT_RXNE: Receive buffer not empty interrupt. +* Output : None +* Return : The new state of SPI_IT (SET or RESET). +*******************************************************************************/ +ITStatus SPI_GetITStatus(SPI_TypeDef* SPIx, u8 SPI_IT) +{ + ITStatus bitstatus = RESET; + u16 itpos = 0, itmask = 0, enablestatus = 0; + + /* Check the parameters */ + assert(IS_SPI_GET_IT(SPI_IT)); + + /* Get the SPI IT index */ + itpos = (u16)((u16)0x01 << (SPI_IT & (u8)0x0F)); + + /* Get the SPI IT index */ + itmask = SPI_IT >> 4; + /* Set the IT mask */ + itmask = (u16)((u16)0x01 << itmask); + /* Get the SPI_IT enable bit status */ + enablestatus = (SPIx->CR2 & itmask) ; + + /* Check the status of the specified SPI interrupt */ + if (((SPIx->SR & itpos) != (u16)RESET) && enablestatus) + { + /* SPI_IT is set */ + bitstatus = SET; + } + else + { + /* SPI_IT is reset */ + bitstatus = RESET; + } + /* Return the SPI_IT status */ + return bitstatus; +} + +/******************************************************************************* +* Function Name : SPI_ClearITPendingBit +* Description : Clears the SPI’s interrupt pending bits. +* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral. +* - SPI_IT: specifies the SPI interrupt pending bit to clear. +* This parameter can be one of the following values: +* - SPI_IT_OVR: Overrun interrupt. +* - SPI_IT_MODF: Mode Fault interrupt. +* - SPI_IT_CRCERR: CRC Error interrupt. +* Output : None +* Return : None +*******************************************************************************/ +void SPI_ClearITPendingBit(SPI_TypeDef* SPIx, u8 SPI_IT) +{ + u16 itpos = 0; + + /* Check the parameters */ + assert(IS_SPI_CLEAR_IT(SPI_IT)); + + /* SPI_IT_MODF pending bit clear */ + if(SPI_IT == SPI_IT_MODF) + { + /* Read SR register */ + (void)SPIx->SR; + /* Write on CR1 register */ + SPIx->CR1 |= CR1_SPE_Set; + } + else if(SPI_IT == SPI_IT_OVR) /* SPI_IT_OVR pending bit clear */ + { + /* Read SR register */ + (void)(SPIx->SR); + } + else /* SPI_IT_CRCERR pending bit clear */ + { + /* Get the SPI IT index */ + itpos = (u16)((u16)0x01 << (SPI_IT & (u8)0x0F)); + /* Clear the selected SPI interrupt pending bits */ + SPIx->SR &= (u16)~itpos; + } +} + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_systick.c b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_systick.c new file mode 100644 index 000000000..6f7a27eda --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_systick.c @@ -0,0 +1,195 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_systick.c +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file provides all the SysTick firmware functions. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_systick.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* ---------------------- SysTick registers bit mask -------------------- */ +/* CTRL TICKINT Mask */ +#define CTRL_TICKINT_Set ((u32)0x00000002) +#define CTRL_TICKINT_Reset ((u32)0xFFFFFFFD) + +/* SysTick Flag Mask */ +#define FLAG_Mask ((u8)0x1F) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : SysTick_CLKSourceConfig +* Description : Configures the SysTick clock source. +* Input : - SysTick_CLKSource: specifies the SysTick clock source. +* This parameter can be one of the following values: +* - SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 +* selected as SysTick clock source. +* - SysTick_CLKSource_HCLK: AHB clock selected as +* SysTick clock source. +* Output : None +* Return : None +*******************************************************************************/ +void SysTick_CLKSourceConfig(u32 SysTick_CLKSource) +{ + /* Check the parameters */ + assert(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); + + if (SysTick_CLKSource == SysTick_CLKSource_HCLK) + { + SysTick->CTRL |= SysTick_CLKSource_HCLK; + } + else + { + SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; + } +} + +/******************************************************************************* +* Function Name : SysTick_SetReload +* Description : Sets SysTick Reload value. +* Input : - Reload: SysTick Reload new value. +* This parameter must be a number between 1 and 0xFFFFFF. +* Output : None +* Return : None +*******************************************************************************/ +void SysTick_SetReload(u32 Reload) +{ + /* Check the parameters */ + assert(IS_SYSTICK_RELOAD(Reload)); + + SysTick->LOAD = Reload; +} + +/******************************************************************************* +* Function Name : SysTick_CounterCmd +* Description : Enables or disables the SysTick counter. +* Input : - SysTick_Counter: new state of the SysTick counter. +* This parameter can be one of the following values: +* - SysTick_Counter_Disable: Disable counter +* - SysTick_Counter_Enable: Enable counter +* - SysTick_Counter_Clear: Clear counter value to 0 +* Output : None +* Return : None +*******************************************************************************/ +void SysTick_CounterCmd(u32 SysTick_Counter) +{ + /* Check the parameters */ + assert(IS_SYSTICK_COUNTER(SysTick_Counter)); + + if (SysTick_Counter == SysTick_Counter_Clear) + { + SysTick->VAL = SysTick_Counter_Clear; + } + else + { + if (SysTick_Counter == SysTick_Counter_Enable) + { + SysTick->CTRL |= SysTick_Counter_Enable; + } + else + { + SysTick->CTRL &= SysTick_Counter_Disable; + } + } +} + +/******************************************************************************* +* Function Name : SysTick_ITConfig +* Description : Enables or disables the SysTick Interrupt. +* Input : - NewState: new state of the SysTick Interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SysTick_ITConfig(FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + SysTick->CTRL |= CTRL_TICKINT_Set; + } + else + { + SysTick->CTRL &= CTRL_TICKINT_Reset; + } +} + +/******************************************************************************* +* Function Name : SysTick_GetCounter +* Description : Gets SysTick counter value. +* Input : None +* Output : None +* Return : SysTick current value +*******************************************************************************/ +u32 SysTick_GetCounter(void) +{ + return(SysTick->VAL); +} + +/******************************************************************************* +* Function Name : SysTick_GetFlagStatus +* Description : Checks whether the specified SysTick flag is set or not. +* Input : - SysTick_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - SysTick_FLAG_COUNT +* - SysTick_FLAG_SKEW +* - SysTick_FLAG_NOREF +* Output : None +* Return : None +*******************************************************************************/ +FlagStatus SysTick_GetFlagStatus(u8 SysTick_FLAG) +{ + u32 tmp = 0; + u32 statusreg = 0; + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert(IS_SYSTICK_FLAG(SysTick_FLAG)); + + /* Get the SysTick register index */ + tmp = SysTick_FLAG >> 5; + + if (tmp == 1) /* The flag to check is in CTRL register */ + { + statusreg = SysTick->CTRL; + } + else /* The flag to check is in CALIB register */ + { + statusreg = SysTick->CALIB; + } + + /* Get the flag position */ + tmp = SysTick_FLAG & FLAG_Mask; + + if ((statusreg & ((u32)1 << tmp)) != (u32)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_tim.c b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_tim.c new file mode 100644 index 000000000..5fd374eb9 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_tim.c @@ -0,0 +1,2348 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_tim.c +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file provides all the TIM firmware functions. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_tim.h" +#include "stm32f10x_rcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* ---------------------- TIM registers bit mask ------------------------ */ +#define CR1_CEN_Set ((u16)0x0001) +#define CR1_CEN_Reset ((u16)0x03FE) +#define CR1_UDIS_Set ((u16)0x0002) +#define CR1_UDIS_Reset ((u16)0x03FD) +#define CR1_URS_Set ((u16)0x0004) +#define CR1_URS_Reset ((u16)0x03FB) +#define CR1_OPM_Mask ((u16)0x03F7) +#define CR1_CounterMode_Mask ((u16)0x039F) +#define CR1_ARPE_Set ((u16)0x0080) +#define CR1_ARPE_Reset ((u16)0x037F) +#define CR1_CKD_Mask ((u16)0x00FF) + +#define CR2_CCDS_Set ((u16)0x0008) +#define CR2_CCDS_Reset ((u16)0x0007) +#define CR2_MMS_Mask ((u16)0x0080) +#define CR2_TI1S_Set ((u16)0x0080) +#define CR2_TI1S_Reset ((u16)0xFF70) + +#define SMCR_SMS_Mask ((u16)0xFFF0) +#define SMCR_ETR_Mask ((u16)0x00F7) +#define SMCR_TS_Mask ((u16)0xFF87) +#define SMCR_MSM_Mask ((u16)0xFF77) +#define SMCR_ECE_Set ((u16)0x4000) + +#define CCMR_CC13S_Mask ((u16)0x7F7C) +#define CCMR_CC24S_Mask ((u16)0x7C7F) +#define CCMR_TI13Direct_Set ((u16)0x0001) +#define CCMR_TI24Direct_Set ((u16)0x0100) +#define CCMR_OC13FE_Mask ((u16)0x7F7B) +#define CCMR_OC24FE_Mask ((u16)0x7B7F) +#define CCMR_OC13PE_Mask ((u16)0x7F77) +#define CCMR_OC24PE_Mask ((u16)0x777F) +#define CCMR_OCM13_Mask ((u16)0x7F0F) +#define CCMR_OCM24_Mask ((u16)0x0F7F) +#define CCMR_IC13PSC_Mask ((u16)0xFFF3) +#define CCMR_IC24PSC_Mask ((u16)0xF3FF) +#define CCMR_IC13F_Mask ((u16)0xFF0F) +#define CCMR_IC24F_Mask ((u16)0x0FFF) +#define CCER_CC1P_Mask ((u16)0xFFFD) + +#define CCER_CC2P_Mask ((u16)0xFFDF) +#define CCER_CC3P_Mask ((u16)0xFDFF) +#define CCER_CC4P_Mask ((u16)0xDFFF) + +#define CCRE_CC1E_Set ((u16)0x0001) +#define CCRE_CC1E_Reset ((u16)0xFFFE) +#define CCRE_CC1E_Mask ((u16)0xFFFE) + +#define CCRE_CC2E_Set ((u16)0x0010) +#define CCRE_CC2E_Reset ((u16)0xFFEF) +#define CCRE_CC2E_Mask ((u16)0xFFEF) + +#define CCRE_CC3E_Set ((u16)0x0100) +#define CCRE_CC3E_Reset ((u16)0xFEFF) + +#define CCRE_CC4E_Set ((u16)0x1000) +#define CCRE_CC4E_Reset ((u16)0xEFFF) +#define CCRE_CC4E_Mask ((u16)0xEFFF) + +#define DCR_DMA_Mask ((u16)0x0000) + +/* TIM private Masks */ +#define TIM_Period_Reset_Mask ((u16)0x0000) +#define TIM_Prescaler_Reset_Mask ((u16)0x0000) +#define TIM_Pulse_Reset_Mask ((u16)0x0000) +#define TIM_ICFilter_Mask ((u8)0x00) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +static uc16 Tab_OCModeMask[4] = {0xFF00, 0x00FF, 0xFF00, 0x00FF}; +static uc16 Tab_PolarityMask[4] = {CCER_CC1P_Mask, CCER_CC2P_Mask, CCER_CC3P_Mask, CCER_CC4P_Mask}; + +/* Private function prototypes -----------------------------------------------*/ +static void PWMI_Config(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); +static void TI1_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection, + u8 TIM_ICFilter); +static void TI2_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection, + u8 TIM_ICFilter); +static void TI3_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection, + u8 TIM_ICFilter); +static void TI4_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection, + u8 TIM_ICFilter); +static void ETR_Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, + u16 TIM_ExtTRGPolarity, u8 ExtTRGFilter); +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : TIM_DeInit +* Description : Deinitializes the TIMx peripheral registers to their default +* reset values. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_DeInit(TIM_TypeDef* TIMx) +{ + switch (*(u32*)&TIMx) + { + case TIM2_BASE: + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); + break; + + case TIM3_BASE: + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); + break; + + case TIM4_BASE: + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : TIM_TimeBaseInit +* Description : Initializes the TIMx Time Base Unit peripheral according to +* the specified parameters in the TIM_TimeBaseInitStruct. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef +* structure that contains the configuration information for +* the specified TIM peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) +{ + /* Check the parameters */ + assert(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode)); + assert(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision)); + + /* Set the Autoreload value */ + TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ; + + /* Set the Prescaler value */ + TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; + + /* Select the Counter Mode and set the clock division */ + TIMx->CR1 &= CR1_CKD_Mask & CR1_CounterMode_Mask; + TIMx->CR1 |= (u32)TIM_TimeBaseInitStruct->TIM_ClockDivision | + TIM_TimeBaseInitStruct->TIM_CounterMode; +} +/******************************************************************************* +* Function Name : TIM_OCInit +* Description : Initializes the TIMx peripheral according to the specified +* parameters in the TIM_OCInitStruct. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure +* that contains the configuration information for the specified +* TIM peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OCInit(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + u32 tmpccmrx = 0, tmpccer = 0; + + /* Check the parameters */ + assert(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert(IS_TIM_CHANNEL(TIM_OCInitStruct->TIM_Channel)); + assert(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + + if ((TIM_OCInitStruct->TIM_Channel == (u16)TIM_Channel_1) || + (TIM_OCInitStruct->TIM_Channel == (u16)TIM_Channel_2)) + { + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare Bits */ + tmpccmrx &= Tab_OCModeMask[TIM_OCInitStruct->TIM_Channel]; + + /* Set the Output Polarity level */ + tmpccer &= Tab_PolarityMask[TIM_OCInitStruct->TIM_Channel]; + + if (TIM_OCInitStruct->TIM_Channel == TIM_Channel_1) + { + /* Disable the Channel 1: Reset the CCE Bit */ + TIMx->CCER &= CCRE_CC1E_Reset; + + /* Select the Output Compare Mode */ + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; + + /* Set the Capture Compare Enable Bit */ + tmpccer |= CCRE_CC1E_Set; + + /* Set the Capture Compare Polarity */ + tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; + } + else /* TIM_Channel_2 */ + { + /* Disable the Channel 2: Reset the CCE Bit */ + TIMx->CCER &= CCRE_CC2E_Reset; + + /* Select the Output Compare Mode */ + tmpccmrx |= (u32)TIM_OCInitStruct->TIM_OCMode << 8; + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse; + + /* Set the Capture Compare Enable Bit */ + tmpccer |= CCRE_CC2E_Set; + + /* Set the Capture Compare Polarity */ + tmpccer |= (u32)TIM_OCInitStruct->TIM_OCPolarity << 4; + } + + TIMx->CCMR1 = (u16)tmpccmrx; + } + else + { + if ((TIM_OCInitStruct->TIM_Channel == TIM_Channel_3) || + (TIM_OCInitStruct->TIM_Channel == TIM_Channel_4)) + { + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare Bits */ + tmpccmrx &= Tab_OCModeMask[TIM_OCInitStruct->TIM_Channel]; + + /* Set the Output Polarity level */ + tmpccer &= Tab_PolarityMask[TIM_OCInitStruct->TIM_Channel]; + + if (TIM_OCInitStruct->TIM_Channel == TIM_Channel_3) + { + /* Disable the Channel 3: Reset the CCE Bit */ + TIMx->CCER &= CCRE_CC3E_Reset; + + /* Select the Output Compare Mode */ + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse; + + /* Set the Capture Compare Enable Bit */ + tmpccer |= CCRE_CC3E_Set; + + /* Set the Capture Compare Polarity */ + tmpccer |= (u32)TIM_OCInitStruct->TIM_OCPolarity << 8; + } + else /* TIM_Channel_4 */ + { + /* Disable the Channel 4: Reset the CCE Bit */ + TIMx->CCER &= CCRE_CC4E_Reset; + + /* Select the Output Compare Mode */ + tmpccmrx |= (u32)TIM_OCInitStruct->TIM_OCMode << 8; + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse; + + /* Set the Capture Compare Enable Bit */ + tmpccer |= CCRE_CC4E_Set; + + /* Set the Capture Compare Polarity */ + tmpccer |= (u32)TIM_OCInitStruct->TIM_OCPolarity << 12; + } + + TIMx->CCMR2 = (u16)tmpccmrx; + } + } + + TIMx->CCER = (u16)tmpccer; +} + +/******************************************************************************* +* Function Name : TIM_ICInit +* Description : Initializes the TIMx peripheral according to the specified +* parameters in the TIM_ICInitStruct. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure +* that contains the configuration information for the specified +* TIM peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + /* Check the parameters */ + assert(IS_TIM_IC_MODE(TIM_ICInitStruct->TIM_ICMode)); + assert(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel)); + assert(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity)); + assert(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection)); + assert(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler)); + assert(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter)); + + if (TIM_ICInitStruct->TIM_ICMode == TIM_ICMode_ICAP) + { + if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + /* TI1 Configuration */ + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) + { + /* TI2 Configuration */ + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) + { + /* TI3 Configuration */ + TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else /* TIM_Channel_4 */ + { + /* TI4 Configuration */ + TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + } + else + { + PWMI_Config(TIMx, TIM_ICInitStruct); + } +} + +/******************************************************************************* +* Function Name : TIM_TimeBaseStructInit +* Description : Fills each TIM_TimeBaseInitStruct member with its default value. +* Input : - TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef +* structure which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) +{ + /* Set the default configuration */ + TIM_TimeBaseInitStruct->TIM_Period = TIM_Period_Reset_Mask; + TIM_TimeBaseInitStruct->TIM_Prescaler = TIM_Prescaler_Reset_Mask; + TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; + TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; +} + +/******************************************************************************* +* Function Name : TIM_OCStructInit +* Description : Fills each TIM_OCInitStruct member with its default value. +* Input : - TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + /* Set the default configuration */ + TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; + TIM_OCInitStruct->TIM_Channel = TIM_Channel_1; + TIM_OCInitStruct->TIM_Pulse = TIM_Pulse_Reset_Mask; + TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; +} + +/******************************************************************************* +* Function Name : TIM_ICStructInit +* Description : Fills each TIM_InitStruct member with its default value. +* Input : - TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + /* Set the default configuration */ + TIM_ICInitStruct->TIM_ICMode = TIM_ICMode_ICAP; + TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; + TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; + TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; + TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; + TIM_ICInitStruct->TIM_ICFilter = TIM_ICFilter_Mask; +} + +/******************************************************************************* +* Function Name : TIM_Cmd +* Description : Enables or disables the specified TIM peripheral. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIMx peripheral. +* - Newstate: new state of the TIMx peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the TIM Counter */ + TIMx->CR1 |= CR1_CEN_Set; + } + else + { + /* Disable the TIM Counter */ + TIMx->CR1 &= CR1_CEN_Reset; + } +} + +/******************************************************************************* +* Function Name : TIM_ITConfig +* Description : Enables or disables the TIMx interrupts. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_IT: specifies the TIM interrupts sources to be enabled +* or disabled. +* This parameter can be any combination of the following values: +* - TIM_IT_Update: Timer update Interrupt +* - TIM_IT_CC1: Capture Compare 1 Interrupt +* - TIM_IT_CC2: Capture Compare 2 Interrupt +* - TIM_IT_CC3: Capture Compare 3 Interrupt +* - TIM_IT_CC4: Capture Compare 4 Interrupt +* - TIM_IT_Trigger: Trigger Interrupt +* - Newstate: new state of the specified TIMx interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ITConfig(TIM_TypeDef* TIMx, u16 TIM_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_TIM_IT(TIM_IT)); + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Interrupt sources */ + TIMx->DIER |= TIM_IT; + } + else + { + /* Disable the Interrupt sources */ + TIMx->DIER &= (u16)(~TIM_IT); + } +} + +/******************************************************************************* +* Function Name : TIM_DMAConfig +* Description : Configures the TIMx’s DMA interface. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_DMABase: DMA Base address. +* This parameter can be one of the following values: +* - TIM_DMABase_CR1, TIM_DMABase_CR2, TIM_DMABase_SMCR, +* TIM_DMABase_DIER, TIM_DMABase_SR, TIM_DMABase_EGR, +* TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER, +* TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR, +* TIM_DMABase_CCR1, TIM_DMABase_CCR2, TIM_DMABase_CCR3, +* TIM_DMABase_CCR4, TIM_DMABase_DCR. +* - TIM_DMABurstLength: DMA Burst length. +* This parameter can be one value between: +* TIM_DMABurstLength_1Byte and TIM_DMABurstLength_18Bytes. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_DMAConfig(TIM_TypeDef* TIMx, u16 TIM_DMABase, u16 TIM_DMABurstLength) +{ + u32 tmpdcr = 0; + + /* Check the parameters */ + assert(IS_TIM_DMA_BASE(TIM_DMABase)); + assert(IS_TIM_DMA_LENGTH(TIM_DMABurstLength)); + + tmpdcr = TIMx->DCR; + + /* Reset the DBA and the DBL Bits */ + tmpdcr &= DCR_DMA_Mask; + + /* Set the DMA Base and the DMA Burst Length */ + tmpdcr |= TIM_DMABase | TIM_DMABurstLength; + + TIMx->DCR = (u16)tmpdcr; +} + +/******************************************************************************* +* Function Name : TIM_DMACmd +* Description : Enables or disables the TIMx’s DMA Requests. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_DMASources: specifies the DMA Request sources. +* This parameter can be any combination of the following values: +* - TIM_DMA_CC1: Capture Compare 1 DMA source +* - TIM_DMA_CC2: Capture Compare 2 DMA source +* - TIM_DMA_CC3: Capture Compare 3 DMA source +* - TIM_DMA_CC4: Capture Compare 4 DMA source +* - TIM_DMA_Trigger: Trigger DMA source +* - Newstate: new state of the DMA Request sources. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_DMACmd(TIM_TypeDef* TIMx, u16 TIM_DMASource, FunctionalState Newstate) +{ + u32 tmpdier = 0; + + /* Check the parameters */ + assert(IS_TIM_DMA_SOURCE(TIM_DMASource)); + assert(IS_FUNCTIONAL_STATE(Newstate)); + + tmpdier = TIMx->DIER; + + if (Newstate != DISABLE) + { + /* Enable the DMA sources */ + tmpdier |= TIM_DMASource; + } + else + { + /* Disable the DMA sources */ + tmpdier &= (u16)(~TIM_DMASource); + } + TIMx->DIER = (u16)tmpdier; +} + +/******************************************************************************* +* Function Name : TIM_InternalClockConfig +* Description : Configures the TIMx interrnal Clock +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_InternalClockConfig(TIM_TypeDef* TIMx) +{ + /* Disable slave mode to clock the prescaler directly with the internal clock */ + TIMx->SMCR &= SMCR_SMS_Mask; +} +/******************************************************************************* +* Function Name : TIM_ITRxExternalClockConfig +* Description : Configures the TIMx Internal Trigger as External Clock +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_ITRSource: Trigger source. +* This parameter can be one of the following values: +* - TIM_TS_ITR0: Internal Trigger 0 +* - TIM_TS_ITR1: Internal Trigger 1 +* - TIM_TS_ITR2: Internal Trigger 2 +* - TIM_TS_ITR3: Internal Trigger 3 +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, u16 TIM_InputTriggerSource) +{ + /* Check the parameters */ + assert(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource)); + + /* Select the Internal Trigger */ + TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); + + /* Select the External clock mode1 */ + TIMx->SMCR |= TIM_SlaveMode_External1; +} +/******************************************************************************* +* Function Name : TIM_TIxExternalClockConfig +* Description : Configures the TIMx Trigger as External Clock +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_TIxExternalCLKSource: Trigger source. +* This parameter can be one of the following values: +* - TIM_TS_TI1F_ED: TI1 Edge Detector +* - TIM_TS_TI1FP1: Filtered Timer Input 1 +* - TIM_TS_TI2FP2: Filtered Timer Input 2 +* - TIM_ICPolarity: specifies the TIx Polarity. +* This parameter can be: +* - TIM_ICPolarity_Rising +* - TIM_ICPolarity_Falling +* - ICFilter : specifies the filter value. +* This parameter must be a value between 0x0 and 0xF. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, u16 TIM_TIxExternalCLKSource, + u16 TIM_ICPolarity, u8 ICFilter) +{ + /* Check the parameters */ + assert(IS_TIM_TIX_TRIGGER_SELECTION(TIM_TIxExternalCLKSource)); + assert(IS_TIM_IC_POLARITY(TIM_ICPolarity)); + assert(IS_TIM_IC_FILTER(ICFilter)); + + /* Configure the Timer Input Clock Source */ + if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) + { + TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + else + { + TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + + /* Select the Trigger source */ + TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); + + /* Select the External clock mode1 */ + TIMx->SMCR |= TIM_SlaveMode_External1; +} + +/******************************************************************************* +* Function Name : TIM_ETRClockMode1Config +* Description : Configures the External clock Mode1 +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_ExtTRGPrescaler: The external Trigger Prescaler. +* It can be one of the following values: +* - TIM_ExtTRGPSC_OFF +* - TIM_ExtTRGPSC_DIV2 +* - TIM_ExtTRGPSC_DIV4 +* - TIM_ExtTRGPSC_DIV8. +* - TIM_ExtTRGPolarity: The external Trigger Polarity. +* It can be one of the following values: +* - TIM_ExtTRGPolarity_Inverted +* - TIM_ExtTRGPolarity_NonInverted +* - ExtTRGFilter: External Trigger Filter. +* This parameter must be a value between 0x00 and 0x0F +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, u16 TIM_ExtTRGPolarity, + u8 ExtTRGFilter) +{ + /* Check the parameters */ + assert(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + + /* Configure the ETR Clock source */ + ETR_Config(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + + /* Select the External clock mode1 */ + TIMx->SMCR &= SMCR_SMS_Mask; + TIMx->SMCR |= TIM_SlaveMode_External1; + + /* Select the Trigger selection : ETRF */ + TIMx->SMCR &= SMCR_TS_Mask; + TIMx->SMCR |= TIM_TS_ETRF; +} + +/******************************************************************************* +* Function Name : TIM_ETRClockMode2Config +* Description : Configures the External clock Mode2 +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_ExtTRGPrescaler: The external Trigger Prescaler. +* It can be one of the following values: +* - TIM_ExtTRGPSC_OFF +* - TIM_ExtTRGPSC_DIV2 +* - TIM_ExtTRGPSC_DIV4 +* - TIM_ExtTRGPSC_DIV8 +* - TIM_ExtTRGPolarity: The external Trigger Polarity. +* It can be one of the following values: +* - TIM_ExtTRGPolarity_Inverted +* - TIM_ExtTRGPolarity_NonInverted +* - ExtTRGFilter: External Trigger Filter. +* This parameter must be a value between 0x00 and 0x0F +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, + u16 TIM_ExtTRGPolarity, u8 ExtTRGFilter) +{ + /* Check the parameters */ + assert(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + + /* Configure the ETR Clock source */ + ETR_Config(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + + /* Enable the External clock mode2 */ + TIMx->SMCR |= SMCR_ECE_Set; +} +/******************************************************************************* +* Function Name : TIM_SelectInputTrigger +* Description : Selects the Input Trigger source +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_InputTriggerSource: The Input Trigger source. +* This parameter can be one of the following values: +* - TIM_TS_ITR0: Internal Trigger 0 +* - TIM_TS_ITR1: Internal Trigger 1 +* - TIM_TS_ITR2: Internal Trigger 2 +* - TIM_TS_ITR3: Internal Trigger 3 +* - TIM_TS_TI1F_ED: TI1 Edge Detector +* - TIM_TS_TI1FP1: Filtered Timer Input 1 +* - TIM_TS_TI2FP2: Filtered Timer Input 2 +* - TIM_TS_ETRF: External Trigger input +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, u16 TIM_InputTriggerSource) +{ + u32 tmpsmcr = 0; + + /* Check the parameters */ + assert(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource)); + + tmpsmcr = TIMx->SMCR; + + /* Select the Tgigger Source */ + tmpsmcr &= SMCR_TS_Mask; + tmpsmcr |= TIM_InputTriggerSource; + + TIMx->SMCR = (u16)tmpsmcr; +} + +/******************************************************************************* +* Function Name : TIM_PrescalerConfig +* Description : Configures the TIMx Prescaler. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - Prescaler: specifies the Prescaler Register value +* - TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode +* This parameter can be one of the following values: +* - TIM_PSCReloadMode_Update: The Prescaler is loaded at +* the update event. +* - TIM_PSCReloadMode_Immediate: The Prescaler is loaded +* immediatly. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_PrescalerConfig(TIM_TypeDef* TIMx, u16 Prescaler, u16 TIM_PSCReloadMode) +{ + /* Check the parameters */ + assert(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode)); + + /* Set the Prescaler value */ + TIMx->PSC = Prescaler; + + /* Set or reset the UG Bit */ + if (TIM_PSCReloadMode == TIM_PSCReloadMode_Immediate) + { + TIMx->EGR |= TIM_EventSource_Update; + } + else + { + TIMx->EGR &= TIM_EventSource_Update; + } +} + +/******************************************************************************* +* Function Name : TIM_CounterModeConfig +* Description : Specifies the TIMx Counter Mode to be used. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_CounterMode: specifies the Counter Mode to be used +* This parameter can be one of the following values: +* - TIM_CounterMode_Up: TIM Up Counting Mode +* - TIM_CounterMode_Down: TIM Down Counting Mode +* - TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1 +* - TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 +* - TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 +* Output : None +* Return : None +*******************************************************************************/ +void TIM_CounterModeConfig(TIM_TypeDef* TIMx, u16 TIM_CounterMode) +{ + u32 tmpcr1 = 0; + + /* Check the parameters */ + assert(IS_TIM_COUNTER_MODE(TIM_CounterMode)); + + tmpcr1 = TIMx->CR1; + + /* Reset the CMS and DIR Bits */ + tmpcr1 &= CR1_CounterMode_Mask; + + /* Set the Counter Mode */ + tmpcr1 |= TIM_CounterMode; + + TIMx->CR1 = (u16)tmpcr1; +} + +/******************************************************************************* +* Function Name : TIM_ForcedOC1Config +* Description : Forces the TIMx output 1 waveform to active or inactive level. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_ForcedAction: specifies the forced Action to be set to +* the output waveform. +* This parameter can be one of the following values: +* - TIM_ForcedAction_Active: Force active level on OC1REF +* - TIM_ForcedAction_InActive: Force inactive level on +* OC1REF. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction) +{ + u32 tmpccmr1 = 0; + + /* Check the parameters */ + assert(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OCM Bits */ + tmpccmr1 &= CCMR_OCM13_Mask; + + /* Configure The Forced output Mode */ + tmpccmr1 |= TIM_ForcedAction; + + TIMx->CCMR1 = (u16)tmpccmr1; +} + +/******************************************************************************* +* Function Name : TIM_ForcedOC2Config +* Description : Forces the TIMx output 2 waveform to active or inactive level. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_ForcedAction: specifies the forced Action to be set to +* the output waveform. +* This parameter can be one of the following values: +* - TIM_ForcedAction_Active: Force active level on OC2REF +* - TIM_ForcedAction_InActive: Force inactive level on +* OC2REF. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction) +{ + u32 tmpccmr1 = 0; + + /* Check the parameters */ + assert(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OCM Bits */ + tmpccmr1 &= CCMR_OCM24_Mask; + + /* Configure The Forced output Mode */ + tmpccmr1 |= (u16)(TIM_ForcedAction << 8); + + TIMx->CCMR1 = (u16)tmpccmr1; +} + +/******************************************************************************* +* Function Name : TIM_ForcedOC3Config +* Description : Forces the TIMx output 3 waveform to active or inactive level. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_ForcedAction: specifies the forced Action to be set to +* the output waveform. +* This parameter can be one of the following values: +* - TIM_ForcedAction_Active: Force active level on OC3REF +* - TIM_ForcedAction_InActive: Force inactive level on +* OC3REF. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction) +{ + u32 tmpccmr2 = 0; + + /* Check the parameters */ + assert(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OCM Bits */ + tmpccmr2 &= CCMR_OCM13_Mask; + + /* Configure The Forced output Mode */ + tmpccmr2 |= TIM_ForcedAction; + + TIMx->CCMR2 = (u16)tmpccmr2; +} + +/******************************************************************************* +* Function Name : TIM_ForcedOC4Config +* Description : Forces the TIMx output 4 waveform to active or inactive level. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_ForcedAction: specifies the forced Action to be set to +* the output waveform. +* This parameter can be one of the following values: +* - TIM_ForcedAction_Active: Force active level on OC4REF +* - TIM_ForcedAction_InActive: Force inactive level on +* OC4REF. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction) +{ + u32 tmpccmr2 = 0; + + /* Check the parameters */ + assert(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OCM Bits */ + tmpccmr2 &= CCMR_OCM24_Mask; + + /* Configure The Forced output Mode */ + tmpccmr2 |= (u16)(TIM_ForcedAction << 8); + + TIMx->CCMR2 = (u16)tmpccmr2; +} + +/******************************************************************************* +* Function Name : TIM_ARRPreloadConfig +* Description : Enables or disables TIMx peripheral Preload register on ARR. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - Newstate: new state of the TIMx peripheral Preload register +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState Newstate) +{ + u32 tmpcr1 = 0; + + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(Newstate)); + + tmpcr1 = TIMx->CR1; + + if (Newstate != DISABLE) + { + /* Set the ARR Preload Bit */ + tmpcr1 |= CR1_ARPE_Set; + } + else + { + /* Reset the ARR Preload Bit */ + tmpcr1 &= CR1_ARPE_Reset; + } + + TIMx->CR1 = (u16)tmpcr1; +} + +/******************************************************************************* +* Function Name : TIM_SelectCCDMA +* Description : Selects the TIMx peripheral Capture Compare DMA source. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - Newstate: new state of the Capture Compare DMA source +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState Newstate) +{ + u32 tmpcr2 = 0; + + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(Newstate)); + + tmpcr2 = TIMx->CR2; + + if (Newstate != DISABLE) + { + /* Set the CCDS Bit */ + tmpcr2 |= CR2_CCDS_Set; + } + else + { + /* Reset the CCDS Bit */ + tmpcr2 &= CR2_CCDS_Reset; + } + + TIMx->CR2 = (u16)tmpcr2; +} + +/******************************************************************************* +* Function Name : TIM_OC1PreloadConfig +* Description : Enables or disables the TIMx peripheral Preload register on CCR1. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_OCPreload: new state of the TIMx peripheral Preload +* register +* This parameter can be one of the following values: +* - TIM_OCPreload_Enable +* - TIM_OCPreload_Disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload) +{ + u32 tmpccmr1 = 0; + + /* Check the parameters */ + assert(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OCPE Bit */ + tmpccmr1 &= CCMR_OC13PE_Mask; + + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr1 |= TIM_OCPreload; + + TIMx->CCMR1 = (u16)tmpccmr1; +} + +/******************************************************************************* +* Function Name : TIM_OC2PreloadConfig +* Description : Enables or disables the TIMx peripheral Preload register on CCR2. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_OCPreload: new state of the TIMx peripheral Preload +* register +* This parameter can be one of the following values: +* - TIM_OCPreload_Enable +* - TIM_OCPreload_Disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload) +{ + u32 tmpccmr1 = 0; + + /* Check the parameters */ + assert(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OCPE Bit */ + tmpccmr1 &= CCMR_OC24PE_Mask; + + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr1 |= (u16)(TIM_OCPreload << 8); + + TIMx->CCMR1 = (u16)tmpccmr1; +} + +/******************************************************************************* +* Function Name : TIM_OC3PreloadConfig +* Description : Enables or disables the TIMx peripheral Preload register on CCR3. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_OCPreload: new state of the TIMx peripheral Preload +* register +* This parameter can be one of the following values: +* - TIM_OCPreload_Enable +* - TIM_OCPreload_Disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload) +{ + u32 tmpccmr2 = 0; + + /* Check the parameters */ + assert(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OCPE Bit */ + tmpccmr2 &= CCMR_OC13PE_Mask; + + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr2 |= TIM_OCPreload; + + TIMx->CCMR2 = (u16)tmpccmr2; +} + +/******************************************************************************* +* Function Name : TIM_OC4PreloadConfig +* Description : Enables or disables the TIMx peripheral Preload register on CCR4. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_OCPreload: new state of the TIMx peripheral Preload +* register +* This parameter can be one of the following values: +* - TIM_OCPreload_Enable +* - TIM_OCPreload_Disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload) +{ + u32 tmpccmr2 = 0; + + /* Check the parameters */ + assert(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OCPE Bit */ + tmpccmr2 &= CCMR_OC24PE_Mask; + + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr2 |= (u16)(TIM_OCPreload << 8); + + TIMx->CCMR2 = (u16)tmpccmr2; +} + +/******************************************************************************* +* Function Name : TIM_OC1FastConfig +* Description : Configures the TIMx Output Compare 1 Fast feature. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_OCFast: new state of the Output Compare Fast Enable Bit. +* This parameter can be one of the following values: +* - TIM_OCFast_Enable +* - TIM_OCFast_Disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC1FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast) +{ + u32 tmpccmr1 = 0; + + /* Check the parameters */ + assert(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OCFE Bit */ + tmpccmr1 &= CCMR_OC13FE_Mask; + + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr1 |= TIM_OCFast; + + TIMx->CCMR1 = (u16)tmpccmr1; +} + +/******************************************************************************* +* Function Name : TIM_OC2FastConfig +* Description : Configures the TIMx Output Compare 2 Fast feature. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_OCFast: new state of the Output Compare Fast Enable Bit. +* This parameter can be one of the following values: +* - TIM_OCFast_Enable +* - TIM_OCFast_Disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC2FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast) +{ + u32 tmpccmr1 = 0; + + /* Check the parameters */ + assert(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OCFE Bit */ + tmpccmr1 &= CCMR_OC24FE_Mask; + + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr1 |= (u16)(TIM_OCFast << 8); + + TIMx->CCMR1 = (u16)tmpccmr1; +} + +/******************************************************************************* +* Function Name : TIM_OC3FastConfig +* Description : Configures the TIMx Output Compare 3 Fast feature. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_OCFast: new state of the Output Compare Fast Enable Bit. +* This parameter can be one of the following values: +* - TIM_OCFast_Enable +* - TIM_OCFast_Disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC3FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast) +{ + u32 tmpccmr2 = 0; + + /* Check the parameters */ + assert(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OCFE Bit */ + tmpccmr2 &= CCMR_OC13FE_Mask; + + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr2 |= TIM_OCFast; + + TIMx->CCMR2 = (u16)tmpccmr2; +} + +/******************************************************************************* +* Function Name : TIM_OC4FastConfig +* Description : Configures the TIMx Output Compare 4 Fast feature. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_OCFast: new state of the Output Compare Fast Enable Bit. +* This parameter can be one of the following values: +* - TIM_OCFast_Enable +* - TIM_OCFast_Disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC4FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast) +{ + u32 tmpccmr2 = 0; + + /* Check the parameters */ + assert(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OCFE Bit */ + tmpccmr2 &= CCMR_OC24FE_Mask; + + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr2 |= (u16)(TIM_OCFast << 8); + + TIMx->CCMR2 = (u16)tmpccmr2; +} + +/******************************************************************************* +* Function Name : TIM_UpdateDisableConfig +* Description : Enables or Disables the TIMx Update event. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - Newstate: new state of the TIMx peripheral Preload register +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState Newstate) +{ + u32 tmpcr1 = 0; + + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(Newstate)); + + tmpcr1 = TIMx->CR1; + + if (Newstate != DISABLE) + { + /* Set the Update Disable Bit */ + tmpcr1 |= CR1_UDIS_Set; + } + else + { + /* Reset the Update Disable Bit */ + tmpcr1 &= CR1_UDIS_Reset; + } + + TIMx->CR1 = (u16)tmpcr1; +} + +/******************************************************************************* +* Function Name : TIM_EncoderInterfaceConfig +* Description : Configures the TIMx Encoder Interface. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_EncoderMode: specifies the TIMx Encoder Mode. +* This parameter can be one of the following values: +* - TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge +* depending on TI2FP2 level. +* - TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge +* depending on TI1FP1 level. +* - TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and +* TI2FP2 edges depending on the level of the other input. +* - TIM_IC1Polarity: specifies the IC1 Polarity +* This parmeter can be one of the following values: +* - TIM_ICPolarity_Falling +* - TIM_ICPolarity_Rising +* - TIM_IC2Polarity: specifies the IC2 Polarity +* This parmeter can be one of the following values: +* - TIM_ICPolarity_Falling +* - TIM_ICPolarity_Rising +* Output : None +* Return : None +*******************************************************************************/ +void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, u16 TIM_EncoderMode, + u16 TIM_IC1Polarity, u16 TIM_IC2Polarity) +{ + u32 tmpsmcr = 0; + u32 tmpccmr1 = 0; + u32 tmpccer = 0; + + /* Check the parameters */ + assert(IS_TIM_ENCODER_MODE(TIM_EncoderMode)); + assert(IS_TIM_IC_POLARITY(TIM_IC1Polarity)); + assert(IS_TIM_IC_POLARITY(TIM_IC2Polarity)); + + tmpsmcr = TIMx->SMCR; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Set the encoder Mode */ + tmpsmcr &= SMCR_SMS_Mask; + tmpsmcr |= TIM_EncoderMode; + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= CCMR_CC13S_Mask & CCMR_CC24S_Mask; + tmpccmr1 |= CCMR_TI13Direct_Set | CCMR_TI24Direct_Set; + + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= CCER_CC1P_Mask & CCER_CC2P_Mask; + tmpccer |= (TIM_IC1Polarity | (u16)((u16)TIM_IC2Polarity << 4)); + + TIMx->SMCR = (u16)tmpsmcr; + + TIMx->CCMR1 = (u16)tmpccmr1; + + TIMx->CCER = (u16)tmpccer; +} + +/******************************************************************************* +* Function Name : TIM_GenerateEvent +* Description : Configures the TIMx event to be generate by software. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_EventSource: specifies the event source. +* This parameter can be one or more of the following values: +* - TIM_EventSource_Update: Timer update Event source +* - TIM_EventSource_CC1: Timer Capture Compare 1 Event source +* - TIM_EventSource_CC2: Timer Capture Compare 2 Event source +* - TIM_EventSource_CC3: Timer Capture Compare 3 Event source +* - TIM_EventSource_CC4: Timer Capture Compare 4 Event source +* - TIM_EventSource_Trigger: Timer Trigger Event source +* Output : None +* Return : None +*******************************************************************************/ +void TIM_GenerateEvent(TIM_TypeDef* TIMx, u16 TIM_EventSource) +{ + /* Check the parameters */ + assert(IS_TIM_EVENT_SOURCE(TIM_EventSource)); + + /* Set the event sources */ + TIMx->EGR |= TIM_EventSource; +} + +/******************************************************************************* +* Function Name : TIM_OC1PolarityConfig +* Description : Configures the TIMx channel 1 polarity. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_OCPolarity: specifies the OC1 Polarity +* This parmeter can be one of the following values: +* - TIM_OCPolarity_High: Output Compare active high +* - TIM_OCPolarity_Low: Output Compare active low +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity) +{ + u32 tmpccer = 0; + + /* Check the parameters */ + assert(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC1P Bit */ + tmpccer &= CCER_CC1P_Mask; + tmpccer |= TIM_OCPolarity; + + TIMx->CCER = (u16)tmpccer; +} + +/******************************************************************************* +* Function Name : TIM_OC2PolarityConfig +* Description : Configures the TIMx channel 2 polarity. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_OCPolarity: specifies the OC2 Polarity +* This parmeter can be one of the following values: +* - TIM_OCPolarity_High: Output Compare active high +* - TIM_OCPolarity_Low: Output Compare active low +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity) +{ + u32 tmpccer = 0; + + /* Check the parameters */ + assert(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC2P Bit */ + tmpccer &= CCER_CC2P_Mask; + tmpccer |= (u16)((u16)TIM_OCPolarity << 4); + + TIMx->CCER = (u16)tmpccer; +} + +/******************************************************************************* +* Function Name : TIM_OC3PolarityConfig +* Description : Configures the TIMx channel 3 polarity. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_OCPolarity: specifies the OC3 Polarity +* This parmeter can be one of the following values: +* - TIM_OCPolarity_High: Output Compare active high +* - TIM_OCPolarity_Low: Output Compare active low +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity) +{ + u32 tmpccer = 0; + + /* Check the parameters */ + assert(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC3P Bit */ + tmpccer &= CCER_CC3P_Mask; + tmpccer |= (u16)((u16)TIM_OCPolarity << 8); + + TIMx->CCER = (u16)tmpccer; +} + +/******************************************************************************* +* Function Name : TIM_OC4PolarityConfig +* Description : Configures the TIMx channel 4 polarity. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_OCPolarity: specifies the OC4 Polarity +* This parmeter can be one of the following values: +* - TIM_OCPolarity_High: Output Compare active high +* - TIM_OCPolarity_Low: Output Compare active low +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity) +{ + u32 tmpccer = 0; + + /* Check the parameters */ + assert(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC4P Bit */ + tmpccer &= CCER_CC4P_Mask; + tmpccer |= (u16)((u16)TIM_OCPolarity << 12); + + TIMx->CCER = (u16)tmpccer; +} + +/******************************************************************************* +* Function Name : TIM_UpdateRequestConfig +* Description : Configures the TIMx Update Request Interrupt source. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_UpdateSource: specifies the Update source. +* This parameter can be one of the following values: +* - TIM_UpdateSource_Regular +* - TIM_UpdateSource_Global +* Output : None +* Return : None +*******************************************************************************/ +void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, u16 TIM_UpdateSource) +{ + u32 tmpcr1 = 0; + + /* Check the parameters */ + assert(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource)); + + tmpcr1 = TIMx->CR1; + + if (TIM_UpdateSource == TIM_UpdateSource_Regular) + { + /* Set the URS Bit */ + tmpcr1 |= CR1_URS_Set; + } + else + { + /* Reset the URS Bit */ + tmpcr1 &= CR1_URS_Reset; + } + TIMx->CR1 = (u16)tmpcr1; +} + +/******************************************************************************* +* Function Name : TIM_SelectHallSensor +* Description : Enables or disables the TIMx’s Hall sensor interface. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - Newstate: new state of the TIMx Hall sensor interface. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState Newstate) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(Newstate)); + + if (Newstate != DISABLE) + { + /* Set the TI1S Bit */ + TIMx->CR2 |= CR2_TI1S_Set; + } + else + { + /* Reset the TI1S Bit */ + TIMx->CR2 &= CR2_TI1S_Reset; + } +} + +/******************************************************************************* +* Function Name : TIM_SelectOnePulseMode +* Description : Selects the TIMx’s One Pulse Mode. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_OPMode: specifies the OPM Mode to be used. +* This parameter can be one of the following values: +* - TIM_OPMode_Single +* - TIM_OPMode_Repetitive +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, u16 TIM_OPMode) +{ + u32 tmpcr1 = 0; + + /* Check the parameters */ + assert(IS_TIM_OPM_MODE(TIM_OPMode)); + + tmpcr1 = TIMx->CR1; + + /* Reset the OPM Bit */ + tmpcr1 &= CR1_OPM_Mask; + + /* Configure the OPM Mode */ + tmpcr1 |= TIM_OPMode; + + TIMx->CR1 = (u16)tmpcr1; +} + +/******************************************************************************* +* Function Name : TIM_SelectOutputTrigger +* Description : Selects the TIMx Trigger Output Mode. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_TRGOSource: specifies the Trigger Output source. +* This paramter can be one of the following values: +* - TIM_TRGOSource_Reset +* - TIM_TRGOSource_Enable +* - TIM_TRGOSource_Update +* - TIM_TRGOSource_OC1 +* - TIM_TRGOSource_OC1Ref +* - TIM_TRGOSource_OC2Ref +* - TIM_TRGOSource_OC3Ref +* - TIM_TRGOSource_OC4Ref +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, u16 TIM_TRGOSource) +{ + u32 tmpcr2 = 0; + + /* Check the parameters */ + assert(IS_TIM_TRGO_SOURCE(TIM_TRGOSource)); + + tmpcr2 = TIMx->CR2; + /* Reset the MMS Bits */ + tmpcr2 &= CR2_MMS_Mask; + + /* Select the TRGO source */ + tmpcr2 |= TIM_TRGOSource; + + TIMx->CR2 = (u16)tmpcr2; +} + +/******************************************************************************* +* Function Name : TIM_SelectSlaveMode +* Description : Selects the TIMx Slave Mode. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_SlaveMode: specifies the Timer Slave Mode. +* This paramter can be one of the following values: +* - TIM_SlaveMode_Reset +* - TIM_SlaveMode_Gated +* - TIM_SlaveMode_Trigger +* - TIM_SlaveMode_External1 +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, u16 TIM_SlaveMode) +{ + u32 tmpsmcr = 0; + + /* Check the parameters */ + assert(IS_TIM_SLAVE_MODE(TIM_SlaveMode)); + + tmpsmcr = TIMx->SMCR; + + /* Reset the SMS Bits */ + tmpsmcr &= SMCR_SMS_Mask; + + /* Select the Slave Mode */ + tmpsmcr |= TIM_SlaveMode; + + TIMx->SMCR = (u16)tmpsmcr; +} + +/******************************************************************************* +* Function Name : TIM_SelectMasterSlaveMode +* Description : Sets or Resets the TIMx Master/Slave Mode. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_MasterSlaveMode: specifies the Timer Master Slave Mode. +* This paramter can be one of the following values: +* - TIM_MasterSlaveMode_Enable: synchronization between the +* current timer and its slaves (through TRGO). +* - TIM_MasterSlaveMode_Disable: No action +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, u16 TIM_MasterSlaveMode) +{ + u32 tmpsmcr = 0; + + /* Check the parameters */ + assert(IS_TIM_MSM_STATE(TIM_MasterSlaveMode)); + + tmpsmcr = TIMx->SMCR; + + /* Set or Reset the MSM Bit */ + tmpsmcr &= SMCR_MSM_Mask; + tmpsmcr |= TIM_MasterSlaveMode; + + TIMx->SMCR = (u16)tmpsmcr; +} + +/******************************************************************************* +* Function Name : TIM_SetAutoreload +* Description : Sets the TIMx Autoreload Register value +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - Autoreload: specifies the Autoreload register new value. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetAutoreload(TIM_TypeDef* TIMx, u16 Autoreload) +{ + /* Set the Autoreload Register value */ + TIMx->ARR = Autoreload; +} + +/******************************************************************************* +* Function Name : TIM_SetCompare1 +* Description : Sets the TIMx Capture Compare1 Register value +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - Compare1: specifies the Capture Compare1 register new value. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetCompare1(TIM_TypeDef* TIMx, u16 Compare1) +{ + /* Set the Capture Compare1 Register value */ + TIMx->CCR1 = Compare1; +} + +/******************************************************************************* +* Function Name : TIM_SetCompare2 +* Description : Sets the TIMx Capture Compare2 Register value +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - Compare2: specifies the Capture Compare2 register new value. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetCompare2(TIM_TypeDef* TIMx, u16 Compare2) +{ + /* Set the Capture Compare2 Register value */ + TIMx->CCR2 = Compare2; +} + +/******************************************************************************* +* Function Name : TIM_SetCompare3 +* Description : Sets the TIMx Capture Compare3 Register value +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - Compare3: specifies the Capture Compare3 register new value. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetCompare3(TIM_TypeDef* TIMx, u16 Compare3) +{ + /* Set the Capture Compare3 Register value */ + TIMx->CCR3 = Compare3; +} + +/******************************************************************************* +* Function Name : TIM_SetCompare4 +* Description : Sets the TIMx Capture Compare4 Register value +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - Compare4: specifies the Capture Compare4 register new value. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetCompare4(TIM_TypeDef* TIMx, u16 Compare4) +{ + /* Set the Capture Compare4 Register value */ + TIMx->CCR4 = Compare4; +} + +/******************************************************************************* +* Function Name : TIM_SetIC1Prescaler +* Description : Sets the TIMx Input Capture 1 prescaler. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_IC1Prescaler: specifies the Input Capture1 prescaler +* new value. +* This parameter can be one of the following values: +* - TIM_ICPSC_DIV1: no prescaler +* - TIM_ICPSC_DIV2: capture is done once every 2 events +* - TIM_ICPSC_DIV4: capture is done once every 4 events +* - TIM_ICPSC_DIV8: capture is done once every 8 events +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC1Prescaler) +{ + u32 tmpccmr1 = 0; + + /* Check the parameters */ + assert(IS_TIM_IC_PRESCALER(TIM_IC1Prescaler)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the IC1PSC Bits */ + tmpccmr1 &= CCMR_IC13PSC_Mask; + + /* Set the IC1PSC value */ + tmpccmr1 |= TIM_IC1Prescaler; + + TIMx->CCMR1 = (u16)tmpccmr1; +} + +/******************************************************************************* +* Function Name : TIM_SetIC2Prescaler +* Description : Sets the TIMx Input Capture 2 prescaler. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_IC2Prescaler: specifies the Input Capture2 prescaler +* new value. +* This parameter can be one of the following values: +* - TIM_ICPSC_DIV1: no prescaler +* - TIM_ICPSC_DIV2: capture is done once every 2 events +* - TIM_ICPSC_DIV4: capture is done once every 4 events +* - TIM_ICPSC_DIV8: capture is done once every 8 events +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC2Prescaler) +{ + u32 tmpccmr1 = 0; + + /* Check the parameters */ + assert(IS_TIM_IC_PRESCALER(TIM_IC2Prescaler)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the IC2PSC Bits */ + tmpccmr1 &= CCMR_IC24PSC_Mask; + + /* Set the IC2PSC value */ + tmpccmr1 |= (u16)((u16)TIM_IC2Prescaler << 8); + + TIMx->CCMR1 = (u16)tmpccmr1; +} + +/******************************************************************************* +* Function Name : TIM_SetIC3Prescaler +* Description : Sets the TIMx Input Capture 3 prescaler. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_IC3Prescaler: specifies the Input Capture3 prescaler +* new value. +* This parameter can be one of the following values: +* - TIM_ICPSC_DIV1: no prescaler +* - TIM_ICPSC_DIV2: capture is done once every 2 events +* - TIM_ICPSC_DIV4: capture is done once every 4 events +* - TIM_ICPSC_DIV8: capture is done once every 8 events +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC3Prescaler) +{ + u32 tmpccmr2 = 0; + + /* Check the parameters */ + assert(IS_TIM_IC_PRESCALER(TIM_IC3Prescaler)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the IC3PSC Bits */ + tmpccmr2 &= CCMR_IC13PSC_Mask; + + /* Set the IC3PSC value */ + tmpccmr2 |= TIM_IC3Prescaler; + + TIMx->CCMR2 = (u16)tmpccmr2; +} + +/******************************************************************************* +* Function Name : TIM_SetIC4Prescaler +* Description : Sets the TIMx Input Capture 4 prescaler. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_IC4Prescaler: specifies the Input Capture4 prescaler +* new value. +* This parameter can be one of the following values: +* - TIM_ICPSC_DIV1: no prescaler +* - TIM_ICPSC_DIV2: capture is done once every 2 events +* - TIM_ICPSC_DIV4: capture is done once every 4 events +* - TIM_ICPSC_DIV8: capture is done once every 8 events +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC4Prescaler) +{ + u32 tmpccmr2 = 0; + + /* Check the parameters */ + assert(IS_TIM_IC_PRESCALER(TIM_IC4Prescaler)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the IC4PSC Bits */ + tmpccmr2 &= CCMR_IC24PSC_Mask; + + /* Set the IC4PSC value */ + tmpccmr2 |= (u16)((u16)TIM_IC4Prescaler << 8); + + TIMx->CCMR2 = (u16)tmpccmr2; +} + +/******************************************************************************* +* Function Name : TIM_SetClockDivision +* Description : Sets the TIMx Clock Division value. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_CKD: specifies the clock division value. +* This parameter can be one of the following value: +* - TIM_CKD_DIV1: TDTS = Tck_tim +* - TIM_CKD_DIV2: TDTS = 2*Tck_tim +* - TIM_CKD_DIV4: TDTS = 4*Tck_tim +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetClockDivision(TIM_TypeDef* TIMx, u16 TIM_CKD) +{ + u32 tmpcr1 = 0; + + /* Check the parameters */ + assert(IS_TIM_CKD_DIV(TIM_CKD)); + + tmpcr1 = TIMx->CR1; + + /* Reset the CKD Bits */ + tmpcr1 &= CR1_CKD_Mask; + + /* Set the CKD value */ + tmpcr1 |= TIM_CKD; + + TIMx->CR1 = (u16)tmpcr1; +} + +/******************************************************************************* +* Function Name : TIM_GetCapture1 +* Description : Gets the TIMx Input Capture 1 value. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* Output : None +* Return : Capture Compare 1 Register value. +*******************************************************************************/ +u16 TIM_GetCapture1(TIM_TypeDef* TIMx) +{ + /* Get the Capture 1 Register value */ + return TIMx->CCR1; +} + +/******************************************************************************* +* Function Name : TIM_GetCapture2 +* Description : Gets the TIMx Input Capture 2 value. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* Output : None +* Return : Capture Compare 2 Register value. +*******************************************************************************/ +u16 TIM_GetCapture2(TIM_TypeDef* TIMx) +{ + /* Get the Capture 2 Register value */ + return TIMx->CCR2; +} + +/******************************************************************************* +* Function Name : TIM_GetCapture3 +* Description : Gets the TIMx Input Capture 3 value. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* Output : None +* Return : Capture Compare 3 Register value. +*******************************************************************************/ +u16 TIM_GetCapture3(TIM_TypeDef* TIMx) +{ + /* Get the Capture 3 Register value */ + return TIMx->CCR3; +} + +/******************************************************************************* +* Function Name : TIM_GetCapture4 +* Description : Gets the TIMx Input Capture 4 value. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* Output : None +* Return : Capture Compare 4 Register value. +*******************************************************************************/ +u16 TIM_GetCapture4(TIM_TypeDef* TIMx) +{ + /* Get the Capture 4 Register value */ + return TIMx->CCR4; +} + +/******************************************************************************* +* Function Name : TIM_GetCounter +* Description : Gets the TIMx Counter value. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* Output : None +* Return : Counter Register value. +*******************************************************************************/ +u16 TIM_GetCounter(TIM_TypeDef* TIMx) +{ + /* Get the Counter Register value */ + return TIMx->CNT; +} + +/******************************************************************************* +* Function Name : TIM_GetPrescaler +* Description : Gets the TIMx Prescaler value. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* Output : None +* Return : Prescaler Register value. +*******************************************************************************/ +u16 TIM_GetPrescaler(TIM_TypeDef* TIMx) +{ + /* Get the Prescaler Register value */ + return TIMx->PSC; +} + +/******************************************************************************* +* Function Name : TIM_GetFlagStatus +* Description : Checks whether the specified TIMx flag is set or not. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - TIM_FLAG_Update: Timer update Flag +* - TIM_FLAG_CC1: Timer Capture Compare 1 Flag +* - TIM_FLAG_CC2: Timer Capture Compare 2 Flag +* - TIM_FLAG_CC3: Timer Capture Compare 3 Flag +* - TIM_FLAG_CC4: Timer Capture Compare 4 Flag +* - TIM_FLAG_Trigger: Timer Trigger Flag +* - TIM_FLAG_CC1OF: Timer Capture Compare 1 overcapture Flag +* - TIM_FLAG_CC2OF: Timer Capture Compare 2 overcapture Flag +* - TIM_FLAG_CC3OF: Timer Capture Compare 3 overcapture Flag +* - TIM_FLAG_CC4OF: Timer Capture Compare 4 overcapture Flag +* Output : None +* Return : The new state of TIM_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, u16 TIM_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert(IS_TIM_GET_FLAG(TIM_FLAG)); + + if ((TIMx->SR & TIM_FLAG) != (u16)RESET ) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : TIM_ClearFlag +* Description : Clears the TIMx's pending flags. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_FLAG: specifies the flag bit to clear. +* This parameter can be any combination of the following values: +* - TIM_FLAG_Update: Timer update Flag +* - TIM_FLAG_CC1: Timer Capture Compare 1 Flag +* - TIM_FLAG_CC2: Timer Capture Compare 2 Flag +* - TIM_FLAG_CC3: Timer Capture Compare 3 Flag +* - TIM_FLAG_CC4: Timer Capture Compare 4 Flag +* - TIM_FLAG_Trigger: Timer Trigger Flag +* - TIM_FLAG_CC1OF: Timer Capture Compare 1 overcapture Flag +* - TIM_FLAG_CC2OF: Timer Capture Compare 2 overcapture Flag +* - TIM_FLAG_CC3OF: Timer Capture Compare 3 overcapture Flag +* - TIM_FLAG_CC4OF: Timer Capture Compare 4 overcapture Flag +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ClearFlag(TIM_TypeDef* TIMx, u16 TIM_FLAG) +{ + /* Check the parameters */ + assert(IS_TIM_CLEAR_FLAG(TIM_FLAG)); + + /* Clear the flags */ + TIMx->SR &= (u16)~TIM_FLAG; +} + +/******************************************************************************* +* Function Name : TIM_GetITStatus +* Description : Checks whether the TIMx interrupt has occurred or not. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_IT: specifies the TIM interrupt source to check. +* This parameter can be one of the following values: +* - TIM_IT_Update: Timer update Interrupt source +* - TIM_IT_CC1: Timer Capture Compare 1 Interrupt source +* - TIM_IT_CC2: Timer Capture Compare 2 Interrupt source +* - TIM_IT_CC3: Timer Capture Compare 3 Interrupt source +* - TIM_IT_CC4: Timer Capture Compare 4 Interrupt source +* - TIM_IT_Trigger: Timer Trigger Interrupt source +* Output : None +* Return : The new state of the TIM_IT(SET or RESET). +*******************************************************************************/ +ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, u16 TIM_IT) +{ + ITStatus bitstatus = RESET; + + u16 itstatus = 0x0, itenable = 0x0; + + /* Check the parameters */ + assert(IS_TIM_GET_IT(TIM_IT)); + + itstatus = TIMx->SR & TIM_IT; + + itenable = TIMx->DIER & TIM_IT; + + if ((itstatus != (u16)RESET) && (itenable != (u16)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : TIM_ClearITPendingBit +* Description : Clears the TIMx's interrupt pending bits. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_IT: specifies the pending bit to clear. +* This parameter can be any combination of the following values: +* - TIM_IT_Update: Timer update Interrupt source +* - TIM_IT_CC1: Timer Capture Compare 1 Interrupt source +* - TIM_IT_CC2: Timer Capture Compare 2 Interrupt source +* - TIM_IT_CC3: Timer Capture Compare 3 Interrupt source +* - TIM_IT_CC4: Timer Capture Compare 4 Interrupt source +* - TIM_IT_Trigger: Timer Trigger Interrupt source +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, u16 TIM_IT) +{ + /* Check the parameters */ + assert(IS_TIM_IT(TIM_IT)); + + /* Clear the IT pending Bit */ + TIMx->SR &= (u16)~TIM_IT; +} + +/******************************************************************************* +* Function Name : PWMInput_Config +* Description : Configures the TIM peripheral according to the specified +* parameters in the TIM_ICInitStruct to measure an external PWM +* signal. +* Input : - TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure +* that contains the configuration information for the specified +* TIM peripheral. +* Output : None +* Return : None +*******************************************************************************/ +static void PWMI_Config(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + u8 ICPolarity = TIM_ICPolarity_Rising; + u8 ICSelection = TIM_ICSelection_DirectTI; + + /* Select the Opposite Input Polarity */ + if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) + { + ICPolarity = TIM_ICPolarity_Falling; + } + else + { + ICPolarity = TIM_ICPolarity_Rising; + } + + /* Select the Opposite Input */ + if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) + { + ICSelection = TIM_ICSelection_IndirectTI; + } + else + { + ICSelection = TIM_ICSelection_DirectTI; + } + + if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + /* TI1 Configuration */ + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + + /* TI2 Configuration */ + TI2_Config(TIMx, ICPolarity, ICSelection, TIM_ICInitStruct->TIM_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + /* TI1 Configuration */ + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + + /* TI2 Configuration */ + TI1_Config(TIMx, ICPolarity, ICSelection, TIM_ICInitStruct->TIM_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/******************************************************************************* +* Function Name : TI1_Config +* Description : Configure the TI1 as Input. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_ICPolarity : The Input Polarity. +* This parameter can be one of the following values: +* - TIM_ICPolarity_Rising +* - TIM_ICPolarity_Falling +* - TIM_ICSelection: specifies the input to be used. +* This parameter can be one of the following values: +* - TIM_ICSelection_DirectTI: TIM Input 1 is selected to +* be connected to IC1. +* - TIM_ICSelection_IndirectTI: TIM Input 1 is selected to +* be connected to IC2. +* - TIM_ICSelection_TRGI: TIM Input 1 is selected to be +* connected to TRGI. +* - TIM_ICFilter: Specifies the Input Capture Filter. +* This parameter must be a value between 0x00 and 0x0F. +* Output : None +* Return : None +*******************************************************************************/ +static void TI1_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection, + u8 TIM_ICFilter) +{ + u32 tmpccmr1 = 0, tmpccer = 0; + + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Disable the Channel 1: Reset the CCE Bit */ + TIMx->CCER &= CCRE_CC1E_Reset; + + /* Select the Input and set the filter */ + tmpccmr1 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask; + tmpccmr1 |= TIM_ICSelection | (u16)((u16)TIM_ICFilter << 4); + + /* Select the Polarity and set the CCE Bit */ + tmpccer &= CCER_CC1P_Mask & CCRE_CC1E_Mask; + tmpccer |= TIM_ICPolarity | CCRE_CC1E_Set; + + TIMx->CCMR1 = 0x0000; + TIMx->CCMR1 = (u16)tmpccmr1; + TIMx->CCER = (u16)tmpccer; +} + +/******************************************************************************* +* Function Name : TI2_Config +* Description : Configure the TI2 as Input. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_ICPolarity : The Input Polarity. +* This parameter can be one of the following values: +* - TIM_ICPolarity_Rising +* - TIM_ICPolarity_Falling +* - TIM_ICSelection: specifies the input to be used. +* This parameter can be one of the following values: +* - TIM_ICSelection_DirectTI: TIM Input 2 is selected to +* be connected to IC2. +* - TIM_ICSelection_IndirectTI: TIM Input 2 is selected to +* be connected to IC1. +* - TIM_ICSelection_TRGI: TIM Input 2 is selected to be +* connected to TRGI. +* - TIM_ICFilter: Specifies the Input Capture Filter. +* This parameter must be a value between 0x00 and 0x0F. +* Output : None +* Return : None +*******************************************************************************/ +static void TI2_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection, + u8 TIM_ICFilter) +{ + u32 tmpccmr1 = 0, tmpccer = 0, tmp = 0; + + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + tmp = (u16)((u16)TIM_ICPolarity << 4); + + /* Disable the Channel 2: Reset the CCE Bit */ + TIMx->CCER &= CCRE_CC2E_Reset; + + /* Select the Input and set the filter */ + tmpccmr1 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask; + tmpccmr1 |= (u16)((u16)TIM_ICFilter << 12); + tmpccmr1 |= (u16)((u16)TIM_ICSelection << 8); + + /* Select the Polarity and set the CCE Bit */ + tmpccer &= CCER_CC2P_Mask & CCRE_CC2E_Mask; + tmpccer |= tmp | CCRE_CC2E_Set; + + TIMx->CCMR1 = (u16)tmpccmr1 ; + TIMx->CCER = (u16)tmpccer; +} + +/******************************************************************************* +* Function Name : TI3_Config +* Description : Configure the TI3 as Input. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_ICPolarity : The Input Polarity. +* This parameter can be one of the following values: +* - TIM_ICPolarity_Rising +* - TIM_ICPolarity_Falling +* - TIM_ICSelection: specifies the input to be used. +* This parameter can be one of the following values: +* - TIM_ICSelection_DirectTI: TIM Input 3 is selected to +* be connected to IC3. +* - TIM_ICSelection_IndirectTI: TIM Input 3 is selected to +* be connected to IC4. +* - TIM_ICSelection_TRGI: TIM Input 3 is selected to be +* connected to TRGI. +* - TIM_ICFilter: Specifies the Input Capture Filter. +* This parameter must be a value between 0x00 and 0x0F. +* Output : None +* Return : None +*******************************************************************************/ +static void TI3_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection, + u8 TIM_ICFilter) +{ + u32 tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + tmp = (u16)((u16)TIM_ICPolarity << 8); + + /* Disable the Channel 3: Reset the CCE Bit */ + TIMx->CCER &= CCRE_CC3E_Reset; + + /* Select the Input and set the filter */ + tmpccmr2 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask; + tmpccmr2 |= TIM_ICSelection | (u16)((u16)TIM_ICFilter << 4); + + /* Select the Polarity and set the CCE Bit */ + tmpccer &= CCER_CC1P_Mask & CCRE_CC1E_Mask; + tmpccer |= tmp | CCRE_CC3E_Set; + + TIMx->CCMR2 = (u16)tmpccmr2; + TIMx->CCER = (u16)tmpccer; +} + +/******************************************************************************* +* Function Name : TI4_Config +* Description : Configure the TI1 as Input. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_ICPolarity : The Input Polarity. +* This parameter can be one of the following values: +* - TIM_ICPolarity_Rising +* - TIM_ICPolarity_Falling +* - TIM_ICSelection: specifies the input to be used. +* This parameter can be one of the following values: +* - TIM_ICSelection_DirectTI: TIM Input 4 is selected to +* be connected to IC4. +* - TIM_ICSelection_IndirectTI: TIM Input 4 is selected to +* be connected to IC3. +* - TIM_ICSelection_TRGI: TIM Input 4 is selected to be +* connected to TRGI. +* - TIM_ICFilter: Specifies the Input Capture Filter. +* This parameter must be a value between 0x00 and 0x0F. +* Output : None +* Return : None +*******************************************************************************/ +static void TI4_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection, + u8 TIM_ICFilter) +{ + u32 tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + tmp = (u16)((u16)TIM_ICPolarity << 12); + + /* Disable the Channel 4: Reset the CCE Bit */ + TIMx->CCER &= CCRE_CC4E_Reset; + + /* Select the Input and set the filter */ + tmpccmr2 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask; + tmpccmr2 |= (u16)((u16)TIM_ICSelection << 8) | (u16)((u16)TIM_ICFilter << 12); + + /* Select the Polarity and set the CCE Bit */ + tmpccer &= CCER_CC4P_Mask & CCRE_CC4E_Mask; + tmpccer |= tmp | CCRE_CC4E_Set; + + TIMx->CCMR2 = (u16)tmpccmr2; + TIMx->CCER = (u16)tmpccer ; +} + +/******************************************************************************* +* Function Name : ETR_Config +* Description : Configure the External Trigger +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_ExtTRGPrescaler: The external Trigger Prescaler. +* This parameter can be one of the following values: +* - TIM_ExtTRGPSC_OFF +* - TIM_ExtTRGPSC_DIV2 +* - TIM_ExtTRGPSC_DIV4 +* - TIM_ExtTRGPSC_DIV8 +* - TIM_ExtTRGPolarity: The external Trigger Polarity. +* This parameter can be one of the following values: +* - TIM_ExtTRGPolarity_Inverted +* - TIM_ExtTRGPolarity_NonInverted +* - ExtTRGFilter: External Trigger Filter. +* This parameter must be a value between 0x00 and 0x0F. +* Output : None +* Return : None +*******************************************************************************/ +static void ETR_Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, u16 TIM_ExtTRGPolarity, + u8 ExtTRGFilter) +{ + u32 tmpsmcr = 0; + + tmpsmcr = TIMx->SMCR; + + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr &= SMCR_ETR_Mask; + tmpsmcr |= TIM_ExtTRGPrescaler | TIM_ExtTRGPolarity | (u16)((u16)ExtTRGFilter << 8); + + TIMx->SMCR = (u16)tmpsmcr; +} +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_tim1.c b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_tim1.c new file mode 100644 index 000000000..deac420a2 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_tim1.c @@ -0,0 +1,2664 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_tim1.c +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file provides all the TIM1 software functions. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* mm/dd/yyyy: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_tim1.h" +#include "stm32f10x_rcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* ------------ TIM1 registers bit address in the alias region ----------- */ +#define TIM1_OFFSET (TIM1_BASE - PERIPH_BASE) + +/* --- TIM1 CR1 Register ---*/ +/* Alias word address of CEN bit */ +#define CR1_OFFSET (TIM1_OFFSET + 0x00) +#define CEN_BitNumber 0x00 +#define CR1_CEN_BB (PERIPH_BB_BASE + (CR1_OFFSET * 32) + (CEN_BitNumber * 4)) + +/* Alias word address of UDIS bit */ +#define UDIS_BitNumber 0x01 +#define CR1_UDIS_BB (PERIPH_BB_BASE + (CR1_OFFSET * 32) + (UDIS_BitNumber * 4)) + +/* Alias word address of URS bit */ +#define URS_BitNumber 0x02 +#define CR1_URS_BB (PERIPH_BB_BASE + (CR1_OFFSET * 32) + (URS_BitNumber * 4)) + +/* Alias word address of OPM bit */ +#define OPM_BitNumber 0x03 +#define CR1_OPM_BB (PERIPH_BB_BASE + (CR1_OFFSET * 32) + (OPM_BitNumber * 4)) + +/* Alias word address of ARPE bit */ +#define ARPE_BitNumber 0x07 +#define CR1_ARPE_BB (PERIPH_BB_BASE + (CR1_OFFSET * 32) + (ARPE_BitNumber * 4)) + +/* --- TIM1 CR2 Register --- */ +/* Alias word address of CCPC bit */ +#define CR2_OFFSET (TIM1_OFFSET + 0x04) +#define CCPC_BitNumber 0x00 +#define CR2_CCPC_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (CCPC_BitNumber * 4)) + +/* Alias word address of CCUS bit */ +#define CCUS_BitNumber 0x02 +#define CR2_CCUS_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (CCUS_BitNumber * 4)) + +/* Alias word address of CCDS bit */ +#define CCDS_BitNumber 0x03 +#define CR2_CCDS_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (CCDS_BitNumber * 4)) + +/* Alias word address of TI1S bit */ +#define TI1S_BitNumber 0x07 +#define CR2_TI1S_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (TI1S_BitNumber * 4)) + +/* Alias word address of OIS1 bit */ +#define OIS1_BitNumber 0x08 +#define CR2_OIS1_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS1_BitNumber * 4)) + +/* Alias word address of OIS1N bit */ +#define OIS1N_BitNumber 0x09 +#define CR2_OIS1N_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS1N_BitNumber * 4)) + +/* Alias word address of OIS2 bit */ +#define OIS2_BitNumber 0x0A +#define CR2_OIS2_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS2_BitNumber * 4)) + +/* Alias word address of OIS2N bit */ +#define OIS2N_BitNumber 0x0B +#define CR2_OIS2N_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS2N_BitNumber * 4)) + +/* Alias word address of OIS3 bit */ +#define OIS3_BitNumber 0x0C +#define CR2_OIS3_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS3_BitNumber * 4)) + +/* Alias word address of OIS3N bit */ +#define OIS3N_BitNumber 0x0D +#define CR2_OIS3N_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS3N_BitNumber * 4)) + +/* Alias word address of OIS4 bit */ +#define OIS4_BitNumber 0x0E +#define CR2_OIS4_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS4_BitNumber * 4)) + +/* --- TIM1 SMCR Register --- */ +/* Alias word address of MSM bit */ +#define SMCR_OFFSET (TIM1_OFFSET + 0x08) +#define MSM_BitNumber 0x07 +#define SMCR_MSM_BB (PERIPH_BB_BASE + (SMCR_OFFSET * 32) + (MSM_BitNumber * 4)) + +/* Alias word address of ECE bit */ +#define ECE_BitNumber 0x0E +#define SMCR_ECE_BB (PERIPH_BB_BASE + (SMCR_OFFSET * 32) + (ECE_BitNumber * 4)) + +/* --- TIM1 EGR Register --- */ +/* Alias word address of UG bit */ +#define EGR_OFFSET (TIM1_OFFSET + 0x14) +#define UG_BitNumber 0x00 +#define EGR_UG_BB (PERIPH_BB_BASE + (EGR_OFFSET * 32) + (UG_BitNumber * 4)) + +/* --- TIM1 CCER Register --- */ +/* Alias word address of CC1E bit */ +#define CCER_OFFSET (TIM1_OFFSET + 0x20) +#define CC1E_BitNumber 0x00 +#define CCER_CC1E_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC1E_BitNumber * 4)) + +/* Alias word address of CC1P bit */ +#define CC1P_BitNumber 0x01 +#define CCER_CC1P_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC1P_BitNumber * 4)) + +/* Alias word address of CC1NE bit */ +#define CC1NE_BitNumber 0x02 +#define CCER_CC1NE_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC1NE_BitNumber * 4)) + +/* Alias word address of CC1NP bit */ +#define CC1NP_BitNumber 0x03 +#define CCER_CC1NP_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC1NP_BitNumber * 4)) + +/* Alias word address of CC2E bit */ +#define CC2E_BitNumber 0x04 +#define CCER_CC2E_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC2E_BitNumber * 4)) + +/* Alias word address of CC2P bit */ +#define CC2P_BitNumber 0x05 +#define CCER_CC2P_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC2P_BitNumber * 4)) + +/* Alias word address of CC2NE bit */ +#define CC2NE_BitNumber 0x06 +#define CCER_CC2NE_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC2NE_BitNumber * 4)) + +/* Alias word address of CC2NP bit */ +#define CC2NP_BitNumber 0x07 +#define CCER_CC2NP_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC2NP_BitNumber * 4)) + +/* Alias word address of CC3E bit */ +#define CC3E_BitNumber 0x08 +#define CCER_CC3E_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC3E_BitNumber * 4)) + +/* Alias word address of CC3P bit */ +#define CC3P_BitNumber 0x09 +#define CCER_CC3P_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC3P_BitNumber * 4)) + +/* Alias word address of CC3NE bit */ +#define CC3NE_BitNumber 0x0A +#define CCER_CC3NE_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC3NE_BitNumber * 4)) + +/* Alias word address of CC3NP bit */ +#define CC3NP_BitNumber 0x0B +#define CCER_CC3NP_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC3NP_BitNumber * 4)) + +/* Alias word address of CC4E bit */ +#define CC4E_BitNumber 0x0C +#define CCER_CC4E_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC4E_BitNumber * 4)) + +/* Alias word address of CC4P bit */ +#define CC4P_BitNumber 0x0D +#define CCER_CC4P_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC4P_BitNumber * 4)) + +/* --- TIM1 BDTR Register --- */ +/* Alias word address of MOE bit */ +#define BDTR_OFFSET (TIM1_OFFSET + 0x44) +#define MOE_BitNumber 0x0F +#define BDTR_MOE_BB (PERIPH_BB_BASE + (BDTR_OFFSET * 32) + (MOE_BitNumber * 4)) + +/* --- TIM1 CCMR1 Register --- */ +/* Alias word address of OC1FE bit */ +#define CCMR1_OFFSET (TIM1_OFFSET + 0x18) +#define OC1FE_BitNumber 0x02 +#define CCMR1_OC1FE_BB (PERIPH_BB_BASE + (CCMR1_OFFSET * 32) + (OC1FE_BitNumber * 4)) + +/* Alias word address of OC1PE bit */ +#define OC1PE_BitNumber 0x03 +#define CCMR1_OC1PE_BB (PERIPH_BB_BASE + (CCMR1_OFFSET * 32) + (OC1PE_BitNumber * 4)) + +/* Alias word address of OC2FE bit */ +#define OC2FE_BitNumber 0x0A +#define CCMR1_OC2FE_BB (PERIPH_BB_BASE + (CCMR1_OFFSET * 32) + (OC2FE_BitNumber * 4)) + +/* Alias word address of OC2PE bit */ +#define OC2PE_BitNumber 0x0B +#define CCMR1_OC2PE_BB (PERIPH_BB_BASE + (CCMR1_OFFSET * 32) + (OC2PE_BitNumber * 4)) + +/* --- TIM1 CCMR2 Register ---- */ +/* Alias word address of OC3FE bit */ +#define CCMR2_OFFSET (TIM1_OFFSET + 0x1C) +#define OC3FE_BitNumber 0x02 +#define CCMR2_OC3FE_BB (PERIPH_BB_BASE + (CCMR2_OFFSET * 32) + (OC3FE_BitNumber * 4)) + +/* Alias word address of OC3PE bit */ +#define OC3PE_BitNumber 0x03 +#define CCMR2_OC3PE_BB (PERIPH_BB_BASE + (CCMR2_OFFSET * 32) + (OC3PE_BitNumber * 4)) + +/* Alias word address of OC4FE bit */ +#define OC4FE_BitNumber 0x0A +#define CCMR2_OC4FE_BB (PERIPH_BB_BASE + (CCMR2_OFFSET * 32) + (OC4FE_BitNumber * 4)) + +/* Alias word address of OC4PE bit */ +#define OC4PE_BitNumber 0x0B +#define CCMR2_OC4PE_BB (PERIPH_BB_BASE + (CCMR2_OFFSET * 32) + (OC4PE_BitNumber * 4)) + +/* --------------------- TIM1 registers bit mask ------------------------- */ +/* TIM1 CR1 Mask */ +#define CR1_CounterMode_Mask ((u16)0x039F) +#define CR1_CKD_Mask ((u16)0x00FF) + +/* TIM1 CR2 Mask */ +#define CR2_MMS_Mask ((u16)0x0080) + +/* TIM1 SMCR Mask */ +#define SMCR_SMS_Mask ((u16)0xFFF0) +#define SMCR_ETR_Mask ((u16)0x40F7) +#define SMCR_TS_Mask ((u16)0xFF87) +#define SMCR_ECE_Set ((u16)0x0001) + +/* TIM1 CCMRx Mask */ +#define CCMR_CC13S_Mask ((u16)0xFFFC) +#define CCMR_CC24S_Mask ((u16)0xFCFF) +#define CCMR_TI13Direct_Set ((u16)0x0001) +#define CCMR_TI24Direct_Set ((u16)0x0100) +#define CCMR_OCM13_Mask ((u16)0x7F0F) +#define CCMR_OCM24_Mask ((u16)0x0F7F) +#define CCMR_IC13PSC_Mask ((u16)0xFFF3) +#define CCMR_IC24PSC_Mask ((u16)0xF3FF) +#define CCMR_IC13F_Mask ((u16)0xFF0F) +#define CCMR_IC24F_Mask ((u16)0x0FFF) +#define OC13Mode_Mask ((u16)0xFF00) +#define OC24Mode_Mask ((u16)0x00FF) + +/* TIM1 CCER Set/Reset Bit */ +#define CCER_CCE_Set ((u16)0x0001) +#define CCER_CCE_Reset ((u16)0x0000) + +/* TIM1 DMA Mask */ +#define DCR_DMA_Mask ((u16)0x0000) + +/* TIM1 private Masks */ +#define TIM1_Period_Reset_Mask ((u16)0xFFFF) +#define TIM1_Prescaler_Reset_Mask ((u16)0x0000) +#define TIM1_RepetitionCounter_Reset_Mask ((u16)0x0000) +#define TIM1_Pulse_Reset_Mask ((u16)0x0000) +#define TIM1_ICFilter_Mask ((u8)0x00) +#define TIM1_DeadTime_Reset_Mask ((u16)0x0000) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void ETR_Config(u16 TIM1_ExtTRGPrescaler, u16 TIM1_ExtTRGPolarity, + u16 ExtTRGFilter); +static void TI1_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection, + u8 TIM1_ICFilter); +static void TI2_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection, + u8 TIM1_ICFilter); +static void TI3_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection, + u8 TIM1_ICFilter); +static void TI4_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection, + u8 TIM1_ICFilter); + +/******************************************************************************* +* Function Name : TIM1_DeInit +* Description : Deinitializes the TIM1 peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_DeInit(void) +{ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); +} + +/******************************************************************************* +* Function Name : TIM1_TimeBaseInit +* Description : Initializes the TIM1 Time Base Unit according to the specified +* parameters in the TIM1_TimeBaseInitStruct. +* Input : - TIM1_TimeBaseInitStruct: pointer to a TIM1_TimeBaseInitTypeDef +* structure that contains the configuration information for +* the specified TIM1 peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_TimeBaseInit(TIM1_TimeBaseInitTypeDef* TIM1_TimeBaseInitStruct) +{ + /* Check the parameters */ + assert(IS_TIM1_COUNTER_MODE(TIM1_TimeBaseInitStruct->TIM1_CounterMode)); + assert(IS_TIM1_CKD_DIV(TIM1_TimeBaseInitStruct->TIM1_ClockDivision)); + + /* Set the Autoreload value */ + TIM1->ARR = TIM1_TimeBaseInitStruct->TIM1_Period ; + + /* Set the Prescaler value */ + TIM1->PSC = TIM1_TimeBaseInitStruct->TIM1_Prescaler; + + /* Select the Counter Mode and set the clock division */ + TIM1->CR1 &= CR1_CKD_Mask & CR1_CounterMode_Mask; + TIM1->CR1 |= (u32)TIM1_TimeBaseInitStruct->TIM1_ClockDivision | + TIM1_TimeBaseInitStruct->TIM1_CounterMode; + + /* Set the Repetition Counter value */ + TIM1->RCR = TIM1_TimeBaseInitStruct->TIM1_RepetitionCounter; +} + +/******************************************************************************* +* Function Name : TIM1_OC1Init +* Description : Initializes the TIM1 Channel1 according to the specified +* parameters in the TIM1_OCInitStruct. +* Input : - TIM1_OCInitStruct: pointer to a TIM1_OCInitTypeDef structure that +* contains the configuration information for the TIM1 peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_OC1Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct) +{ + u16 tmpccmr = 0; + + /* Check the parameters */ + assert(IS_TIM1_OC_MODE(TIM1_OCInitStruct->TIM1_OCMode)); + assert(IS_TIM1_OUTPUT_STATE(TIM1_OCInitStruct->TIM1_OutputState)); + assert(IS_TIM1_OUTPUTN_STATE(TIM1_OCInitStruct->TIM1_OutputNState)); + assert(IS_TIM1_OC_POLARITY(TIM1_OCInitStruct->TIM1_OCPolarity)); + assert(IS_TIM1_OCN_POLARITY(TIM1_OCInitStruct->TIM1_OCNPolarity)); + assert(IS_TIM1_OCIDLE_STATE(TIM1_OCInitStruct->TIM1_OCIdleState)); + assert(IS_TIM1_OCNIDLE_STATE(TIM1_OCInitStruct->TIM1_OCNIdleState)); + + tmpccmr = TIM1->CCMR1; + + /* Disable the Channel 1: Reset the CCE Bit */ + *(vu32 *) CCER_CC1E_BB = CCER_CCE_Reset; + + /* Reset the Output Compare Bits */ + tmpccmr &= OC13Mode_Mask; + + /* Set the Ouput Compare Mode */ + tmpccmr |= TIM1_OCInitStruct->TIM1_OCMode; + + TIM1->CCMR1 = tmpccmr; + + /* Set the Output State */ + *(vu32 *) CCER_CC1E_BB = TIM1_OCInitStruct->TIM1_OutputState; + + /* Set the Output N State */ + *(vu32 *) CCER_CC1NE_BB = TIM1_OCInitStruct->TIM1_OutputNState; + + /* Set the Output Polarity */ + *(vu32 *) CCER_CC1P_BB = TIM1_OCInitStruct->TIM1_OCPolarity; + + /* Set the Output N Polarity */ + *(vu32 *) CCER_CC1NP_BB = TIM1_OCInitStruct->TIM1_OCNPolarity; + + /* Set the Output Idle state */ + *(vu32 *) CR2_OIS1_BB = TIM1_OCInitStruct->TIM1_OCIdleState; + + /* Set the Output N Idle state */ + *(vu32 *) CR2_OIS1N_BB = TIM1_OCInitStruct->TIM1_OCNIdleState; + + /* Set the Pulse value */ + TIM1->CCR1 = TIM1_OCInitStruct->TIM1_Pulse; +} + +/******************************************************************************* +* Function Name : TIM1_OC2Init +* Description : Initializes the TIM1 Channel2 according to the specified +* parameters in the TIM1_OCInitStruct. +* Input : - TIM1_OCInitStruct: pointer to a TIM1_OCInitTypeDef structure that +* contains the configuration information for the TIM1 peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_OC2Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct) +{ + u32 tmpccmr = 0; + + /* Check the parameters */ + assert(IS_TIM1_OC_MODE(TIM1_OCInitStruct->TIM1_OCMode)); + assert(IS_TIM1_OUTPUT_STATE(TIM1_OCInitStruct->TIM1_OutputState)); + assert(IS_TIM1_OUTPUTN_STATE(TIM1_OCInitStruct->TIM1_OutputNState)); + assert(IS_TIM1_OC_POLARITY(TIM1_OCInitStruct->TIM1_OCPolarity)); + assert(IS_TIM1_OCN_POLARITY(TIM1_OCInitStruct->TIM1_OCNPolarity)); + assert(IS_TIM1_OCIDLE_STATE(TIM1_OCInitStruct->TIM1_OCIdleState)); + assert(IS_TIM1_OCNIDLE_STATE(TIM1_OCInitStruct->TIM1_OCNIdleState)); + + tmpccmr = TIM1->CCMR1; + + /* Disable the Channel 2: Reset the CCE Bit */ + *(vu32 *) CCER_CC2E_BB = CCER_CCE_Reset; + + /* Reset the Output Compare Bits */ + tmpccmr &= OC24Mode_Mask; + + /* Set the Ouput Compare Mode */ + tmpccmr |= (u32)TIM1_OCInitStruct->TIM1_OCMode << 8; + + TIM1->CCMR1 = (u16)tmpccmr; + + /* Set the Output State */ + *(vu32 *) CCER_CC2E_BB = TIM1_OCInitStruct->TIM1_OutputState; + + /* Set the Output N State */ + *(vu32 *) CCER_CC2NE_BB = TIM1_OCInitStruct->TIM1_OutputNState; + + /* Set the Output Polarity */ + *(vu32 *) CCER_CC2P_BB = TIM1_OCInitStruct->TIM1_OCPolarity; + + /* Set the Output N Polarity */ + *(vu32 *) CCER_CC2NP_BB = TIM1_OCInitStruct->TIM1_OCNPolarity; + + /* Set the Output Idle state */ + *(vu32 *) CR2_OIS2_BB = TIM1_OCInitStruct->TIM1_OCIdleState; + + /* Set the Output N Idle state */ + *(vu32 *) CR2_OIS2N_BB = TIM1_OCInitStruct->TIM1_OCNIdleState; + + /* Set the Pulse value */ + TIM1->CCR2 = TIM1_OCInitStruct->TIM1_Pulse; +} + +/******************************************************************************* +* Function Name : TIM1_OC3Init +* Description : Initializes the TIM1 Channel3 according to the specified +* parameters in the TIM1_OCInitStruct. +* Input : - TIM1_OCInitStruct: pointer to a TIM1_OCInitTypeDef structure that +* contains the configuration information for the TIM1 peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_OC3Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct) +{ + u16 tmpccmr = 0; + + /* Check the parameters */ + assert(IS_TIM1_OC_MODE(TIM1_OCInitStruct->TIM1_OCMode)); + assert(IS_TIM1_OUTPUT_STATE(TIM1_OCInitStruct->TIM1_OutputState)); + assert(IS_TIM1_OUTPUTN_STATE(TIM1_OCInitStruct->TIM1_OutputNState)); + assert(IS_TIM1_OC_POLARITY(TIM1_OCInitStruct->TIM1_OCPolarity)); + assert(IS_TIM1_OCN_POLARITY(TIM1_OCInitStruct->TIM1_OCNPolarity)); + assert(IS_TIM1_OCIDLE_STATE(TIM1_OCInitStruct->TIM1_OCIdleState)); + assert(IS_TIM1_OCNIDLE_STATE(TIM1_OCInitStruct->TIM1_OCNIdleState)); + + tmpccmr = TIM1->CCMR2; + + /* Disable the Channel 3: Reset the CCE Bit */ + *(vu32 *) CCER_CC3E_BB = CCER_CCE_Reset; + + /* Reset the Output Compare Bits */ + tmpccmr &= OC13Mode_Mask; + + /* Set the Ouput Compare Mode */ + tmpccmr |= TIM1_OCInitStruct->TIM1_OCMode; + + TIM1->CCMR2 = tmpccmr; + + /* Set the Output State */ + *(vu32 *) CCER_CC3E_BB = TIM1_OCInitStruct->TIM1_OutputState; + + /* Set the Output N State */ + *(vu32 *) CCER_CC3NE_BB = TIM1_OCInitStruct->TIM1_OutputNState; + + /* Set the Output Polarity */ + *(vu32 *) CCER_CC3P_BB = TIM1_OCInitStruct->TIM1_OCPolarity; + + /* Set the Output N Polarity */ + *(vu32 *) CCER_CC3NP_BB = TIM1_OCInitStruct->TIM1_OCNPolarity; + + /* Set the Output Idle state */ + *(vu32 *) CR2_OIS3_BB = TIM1_OCInitStruct->TIM1_OCIdleState; + + /* Set the Output N Idle state */ + *(vu32 *) CR2_OIS3N_BB = TIM1_OCInitStruct->TIM1_OCNIdleState; + + /* Set the Pulse value */ + TIM1->CCR3 = TIM1_OCInitStruct->TIM1_Pulse; +} + +/******************************************************************************* +* Function Name : TIM1_OC4Init +* Description : Initializes the TIM1 Channel4 according to the specified +* parameters in the TIM1_OCInitStruct. +* Input : - TIM1_OCInitStruct: pointer to a TIM1_OCInitTypeDef structure that +* contains the configuration information for the TIM1 peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_OC4Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct) +{ + u32 tmpccmr = 0; + + /* Check the parameters */ + assert(IS_TIM1_OC_MODE(TIM1_OCInitStruct->TIM1_OCMode)); + assert(IS_TIM1_OUTPUT_STATE(TIM1_OCInitStruct->TIM1_OutputState)); + assert(IS_TIM1_OC_POLARITY(TIM1_OCInitStruct->TIM1_OCPolarity)); + assert(IS_TIM1_OCIDLE_STATE(TIM1_OCInitStruct->TIM1_OCIdleState)); + + tmpccmr = TIM1->CCMR2; + + /* Disable the Channel 4: Reset the CCE Bit */ + *(vu32 *) CCER_CC4E_BB = CCER_CCE_Reset; + + /* Reset the Output Compare Bits */ + tmpccmr &= OC24Mode_Mask; + + /* Set the Ouput Compare Mode */ + tmpccmr |= (u32)TIM1_OCInitStruct->TIM1_OCMode << 8; + + TIM1->CCMR2 = (u16)tmpccmr; + + /* Set the Output State */ + *(vu32 *) CCER_CC4E_BB = TIM1_OCInitStruct->TIM1_OutputState; + + /* Set the Output Polarity */ + *(vu32 *) CCER_CC4P_BB = TIM1_OCInitStruct->TIM1_OCPolarity; + + /* Set the Output Idle state */ + *(vu32 *) CR2_OIS4_BB = TIM1_OCInitStruct->TIM1_OCIdleState; + + /* Set the Pulse value */ + TIM1->CCR4 = TIM1_OCInitStruct->TIM1_Pulse; +} + +/******************************************************************************* +* Function Name : TIM1_BDTRConfig +* Description : Configures the: Break feature, dead time, Lock level, the OSSI, +* the OSSR State and the AOE(automatic output enable). +* Input : - TIM1_BDTRInitStruct: pointer to a TIM1_BDTRInitTypeDef +* structure that contains the BDTR Register configuration +* information for the TIM1 peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_BDTRConfig(TIM1_BDTRInitTypeDef *TIM1_BDTRInitStruct) +{ + u16 tmpbdtr = 0; + + /* Check the parameters */ + assert(IS_TIM1_OSSR_STATE(TIM1_BDTRInitStruct->TIM1_OSSRState)); + assert(IS_TIM1_OSSI_STATE(TIM1_BDTRInitStruct->TIM1_OSSIState)); + assert(IS_TIM1_LOCK_LEVEL(TIM1_BDTRInitStruct->TIM1_LOCKLevel)); + assert(IS_TIM1_BREAK_STATE(TIM1_BDTRInitStruct->TIM1_Break)); + assert(IS_TIM1_BREAK_POLARITY(TIM1_BDTRInitStruct->TIM1_BreakPolarity)); + assert(IS_TIM1_AUTOMATIC_OUTPUT_STATE(TIM1_BDTRInitStruct->TIM1_AutomaticOutput)); + + tmpbdtr = TIM1->BDTR; + + /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + + tmpbdtr = (u32)TIM1_BDTRInitStruct->TIM1_OSSRState | TIM1_BDTRInitStruct->TIM1_OSSIState | + TIM1_BDTRInitStruct->TIM1_LOCKLevel | TIM1_BDTRInitStruct->TIM1_DeadTime | + TIM1_BDTRInitStruct->TIM1_Break | TIM1_BDTRInitStruct->TIM1_BreakPolarity | + TIM1_BDTRInitStruct->TIM1_AutomaticOutput; + + TIM1->BDTR = tmpbdtr; +} + +/******************************************************************************* +* Function Name : TIM1_ICInit +* Description : Initializes the TIM1 peripheral according to the specified +* parameters in the TIM1_ICInitStruct. +* Input : - TIM1_ICInitStruct: pointer to a TIM1_ICInitTypeDef structure +* that contains the configuration information for the specified +* TIM1 peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_ICInit(TIM1_ICInitTypeDef* TIM1_ICInitStruct) +{ + /* Check the parameters */ + assert(IS_TIM1_CHANNEL(TIM1_ICInitStruct->TIM1_Channel)); + assert(IS_TIM1_IC_POLARITY(TIM1_ICInitStruct->TIM1_ICPolarity)); + assert(IS_TIM1_IC_SELECTION(TIM1_ICInitStruct->TIM1_ICSelection)); + assert(IS_TIM1_IC_PRESCALER(TIM1_ICInitStruct->TIM1_ICPrescaler)); + assert(IS_TIM1_IC_FILTER(TIM1_ICInitStruct->TIM1_ICFilter)); + + if (TIM1_ICInitStruct->TIM1_Channel == TIM1_Channel_1) + { + /* TI1 Configuration */ + TI1_Config(TIM1_ICInitStruct->TIM1_ICPolarity, + TIM1_ICInitStruct->TIM1_ICSelection, + TIM1_ICInitStruct->TIM1_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM1_SetIC1Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler); + } + else if (TIM1_ICInitStruct->TIM1_Channel == TIM1_Channel_2) + { + /* TI2 Configuration */ + TI2_Config(TIM1_ICInitStruct->TIM1_ICPolarity, + TIM1_ICInitStruct->TIM1_ICSelection, + TIM1_ICInitStruct->TIM1_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM1_SetIC2Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler); + } + else if (TIM1_ICInitStruct->TIM1_Channel == TIM1_Channel_3) + { + /* TI3 Configuration */ + TI3_Config(TIM1_ICInitStruct->TIM1_ICPolarity, + TIM1_ICInitStruct->TIM1_ICSelection, + TIM1_ICInitStruct->TIM1_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM1_SetIC3Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler); + } + else + { + /* TI4 Configuration */ + TI4_Config(TIM1_ICInitStruct->TIM1_ICPolarity, + TIM1_ICInitStruct->TIM1_ICSelection, + TIM1_ICInitStruct->TIM1_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM1_SetIC4Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler); + } +} + +/******************************************************************************* +* Function Name : TIM1_PWMIConfig +* Description : Configures the TIM1 peripheral in PWM Input Mode according +* to the specified parameters in the TIM1_ICInitStruct. +* Input : - TIM1_ICInitStruct: pointer to a TIM1_ICInitTypeDef structure +* that contains the configuration information for the specified +* TIM1 peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_PWMIConfig(TIM1_ICInitTypeDef* TIM1_ICInitStruct) +{ + u8 ICPolarity = TIM1_ICPolarity_Rising; + u8 ICSelection = TIM1_ICSelection_DirectTI; + + /* Check the parameters */ + assert(IS_TIM1_PWMI_CHANNEL(TIM1_ICInitStruct->TIM1_Channel)); + assert(IS_TIM1_IC_POLARITY(TIM1_ICInitStruct->TIM1_ICPolarity)); + assert(IS_TIM1_IC_SELECTION(TIM1_ICInitStruct->TIM1_ICSelection)); + assert(IS_TIM1_IC_PRESCALER(TIM1_ICInitStruct->TIM1_ICPrescaler)); + + /* Select the Opposite Input Polarity */ + if (TIM1_ICInitStruct->TIM1_ICPolarity == TIM1_ICPolarity_Rising) + { + ICPolarity = TIM1_ICPolarity_Falling; + } + else + { + ICPolarity = TIM1_ICPolarity_Rising; + } + + /* Select the Opposite Input */ + if (TIM1_ICInitStruct->TIM1_ICSelection == TIM1_ICSelection_DirectTI) + { + ICSelection = TIM1_ICSelection_IndirectTI; + } + else + { + ICSelection = TIM1_ICSelection_DirectTI; + } + + if (TIM1_ICInitStruct->TIM1_Channel == TIM1_Channel_1) + { + /* TI1 Configuration */ + TI1_Config(TIM1_ICInitStruct->TIM1_ICPolarity, TIM1_ICInitStruct->TIM1_ICSelection, + TIM1_ICInitStruct->TIM1_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM1_SetIC1Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler); + + /* TI2 Configuration */ + TI2_Config(ICPolarity, ICSelection, TIM1_ICInitStruct->TIM1_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM1_SetIC2Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler); + } + else + { + /* TI2 Configuration */ + TI2_Config(TIM1_ICInitStruct->TIM1_ICPolarity, TIM1_ICInitStruct->TIM1_ICSelection, + TIM1_ICInitStruct->TIM1_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM1_SetIC2Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler); + + /* TI1 Configuration */ + TI1_Config(ICPolarity, ICSelection, TIM1_ICInitStruct->TIM1_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM1_SetIC1Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler); + } +} +/******************************************************************************* +* Function Name : TIM1_OCStructInit +* Description : Fills each TIM1_OCInitStruct member with its default value. +* Input : - TIM1_OCInitStruct : pointer to a TIM1_OCInitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_OCStructInit(TIM1_OCInitTypeDef* TIM1_OCInitStruct) +{ + /* Set the default configuration */ + TIM1_OCInitStruct->TIM1_OCMode = TIM1_OCMode_Timing; + TIM1_OCInitStruct->TIM1_OutputState = TIM1_OutputState_Disable; + TIM1_OCInitStruct->TIM1_OutputNState = TIM1_OutputNState_Disable; + TIM1_OCInitStruct->TIM1_Pulse = TIM1_Pulse_Reset_Mask; + TIM1_OCInitStruct->TIM1_OCPolarity = TIM1_OCPolarity_High; + TIM1_OCInitStruct->TIM1_OCNPolarity = TIM1_OCPolarity_High; + TIM1_OCInitStruct->TIM1_OCIdleState = TIM1_OCIdleState_Reset; + TIM1_OCInitStruct->TIM1_OCNIdleState = TIM1_OCNIdleState_Reset; +} + +/******************************************************************************* +* Function Name : TIM1_ICStructInit +* Description : Fills each TIM1_ICInitStruct member with its default value. +* Input : - TIM1_ICInitStruct : pointer to a TIM1_ICInitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_ICStructInit(TIM1_ICInitTypeDef* TIM1_ICInitStruct) +{ + /* Set the default configuration */ + TIM1_ICInitStruct->TIM1_Channel = TIM1_Channel_1; + TIM1_ICInitStruct->TIM1_ICSelection = TIM1_ICSelection_DirectTI; + TIM1_ICInitStruct->TIM1_ICPolarity = TIM1_ICPolarity_Rising; + TIM1_ICInitStruct->TIM1_ICPrescaler = TIM1_ICPSC_DIV1; + TIM1_ICInitStruct->TIM1_ICFilter = TIM1_ICFilter_Mask; +} + +/******************************************************************************* +* Function Name : TIM1_TimeBaseStructInit +* Description : Fills each TIM1_TimeBaseInitStruct member with its default value. +* Input : - TIM1_TimeBaseInitStruct : pointer to a TIM1_TimeBaseInitTypeDef +* structure which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_TimeBaseStructInit(TIM1_TimeBaseInitTypeDef* TIM1_TimeBaseInitStruct) +{ + /* Set the default configuration */ + TIM1_TimeBaseInitStruct->TIM1_Period = TIM1_Period_Reset_Mask; + TIM1_TimeBaseInitStruct->TIM1_Prescaler = TIM1_Prescaler_Reset_Mask; + TIM1_TimeBaseInitStruct->TIM1_ClockDivision = TIM1_CKD_DIV1; + TIM1_TimeBaseInitStruct->TIM1_CounterMode = TIM1_CounterMode_Up; + TIM1_TimeBaseInitStruct->TIM1_RepetitionCounter = TIM1_RepetitionCounter_Reset_Mask; +} + +/******************************************************************************* +* Function Name : TIM1_BDTRStructInit +* Description : Fills each TIM1_BDTRInitStruct member with its default value. +* Input : - TIM1_BDTRInitStruct : pointer to a TIM1_BDTRInitTypeDef +* structure which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_BDTRStructInit(TIM1_BDTRInitTypeDef* TIM1_BDTRInitStruct) +{ + /* Set the default configuration */ + TIM1_BDTRInitStruct->TIM1_OSSRState = TIM1_OSSRState_Disable; + TIM1_BDTRInitStruct->TIM1_OSSIState = TIM1_OSSIState_Disable; + TIM1_BDTRInitStruct->TIM1_LOCKLevel = TIM1_LOCKLevel_OFF; + TIM1_BDTRInitStruct->TIM1_DeadTime = TIM1_DeadTime_Reset_Mask; + TIM1_BDTRInitStruct->TIM1_Break = TIM1_Break_Disable; + TIM1_BDTRInitStruct->TIM1_BreakPolarity = TIM1_BreakPolarity_Low; + TIM1_BDTRInitStruct->TIM1_AutomaticOutput = TIM1_AutomaticOutput_Disable; +} + +/******************************************************************************* +* Function Name : TIM1_Cmd +* Description : Enables or disables the TIM1 peripheral. +* Input : - Newstate: new state of the TIM1 peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_Cmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + /* set or Reset the CEN Bit */ + *(vu32 *) CR1_CEN_BB = (u16)NewState; +} + +/******************************************************************************* +* Function Name : TIM1_CtrlPWMOutputs +* Description : Enables or disables the TIM1 peripheral Main Outputs. +* Input : - Newstate: new state of the TIM1 peripheral Main Outputs. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_CtrlPWMOutputs(FunctionalState Newstate) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(Newstate)); + + /* Set or Reset the MOE Bit */ + *(vu32 *) BDTR_MOE_BB = (u16)Newstate; +} + +/******************************************************************************* +* Function Name : TIM1_ITConfig +* Description : Enables or disables the specified TIM1 interrupts. +* Input : - TIM1_IT: specifies the TIM1 interrupts sources to be enabled +* or disabled. +* This parameter can be any combination of the following values: +* - TIM1_IT_Update: TIM1 update Interrupt source +* - TIM1_IT_CC1: TIM1 Capture Compare 1 Interrupt source +* - TIM1_IT_CC2: TIM1 Capture Compare 2 Interrupt source +* - TIM1_IT_CC3: TIM1 Capture Compare 3 Interrupt source +* - TIM1_IT_CC4: TIM1 Capture Compare 4 Interrupt source +* - TIM1_IT_CCUpdate: TIM1 Capture Compare Update Interrupt +* source +* - TIM1_IT_Trigger: TIM1 Trigger Interrupt source +* - TIM1_IT_Break: TIM1 Break Interrupt source +* - Newstate: new state of the TIM1 interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_ITConfig(u16 TIM1_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_TIM1_IT(TIM1_IT)); + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + { + /* Enable the Interrupt sources */ + TIM1->DIER |= TIM1_IT; + } + else + { + /* Disable the Interrupt sources */ + TIM1->DIER &= (u16)~TIM1_IT; + } +} + +/******************************************************************************* +* Function Name : TIM1_DMAConfig +* Description : Configures the TIM1’s DMA interface. +* Input : - TIM1_DMABase: DMA Base address. +* This parameter can be one of the following values: +* - TIM1_DMABase_CR1, TIM1_DMABase_CR2, TIM1_DMABase_SMCR, +* TIM1_DMABase_DIER, TIM1_DMABase_SR, TIM1_DMABase_EGR, +* TIM1_DMABase_CCMR1, TIM1_DMABase_CCMR2, TIM1_DMABase_CCER, +* TIM1_DMABase_CNT, TIM1_DMABase_PSC, TIM1_DMABase_ARR, +* TIM1_DMABase_RCR, TIM1_DMABase_CCR1, TIM1_DMABase_CCR2, +* TIM1_DMABase_CCR3, TIM1_DMABase_CCR4, TIM1_DMABase_BDTR, +* TIM1_DMABase_DCR. +* - TIM1_DMABurstLength: DMA Burst length. +* This parameter can be one value between: +* TIM1_DMABurstLength_1Byte and TIM1_DMABurstLength_18Bytes. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_DMAConfig(u16 TIM1_DMABase, u16 TIM1_DMABurstLength) +{ + u32 tmpdcr = 0; + + /* Check the parameters */ + assert(IS_TIM1_DMA_BASE(TIM1_DMABase)); + assert(IS_TIM1_DMA_LENGTH(TIM1_DMABurstLength)); + + tmpdcr = TIM1->DCR; + + /* Reset the DBA and the DBL Bits */ + tmpdcr &= DCR_DMA_Mask; + + /* Set the DMA Base and the DMA Burst Length */ + tmpdcr |= TIM1_DMABase | TIM1_DMABurstLength; + + TIM1->DCR = (u16)tmpdcr; +} + +/******************************************************************************* +* Function Name : TIM1_DMACmd +* Description : Enables or disables the TIM1’s DMA Requests. +* Input : - TIM1_DMASources: specifies the DMA Request sources. +* This parameter can be any combination of the following values: +* - TIM1_DMA_Update: TIM1 update Interrupt source +* - TIM1_DMA_CC1: TIM1 Capture Compare 1 DMA source +* - TIM1_DMA_CC2: TIM1 Capture Compare 2 DMA source +* - TIM1_DMA_CC3: TIM1 Capture Compare 3 DMA source +* - TIM1_DMA_CC4: TIM1 Capture Compare 4 DMA source +* - TIM1_DMA_COM: TIM1 Capture Compare Update DMA +* source +* - TIM1_DMA_Trigger: TIM1 Trigger DMA source +* - Newstate: new state of the DMA Request sources. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_DMACmd(u16 TIM1_DMASource, FunctionalState Newstate) +{ + u32 tmpdier = 0; + + /* Check the parameters */ + assert(IS_TIM1_DMA_SOURCE(TIM1_DMASource)); + assert(IS_FUNCTIONAL_STATE(Newstate)); + + tmpdier = TIM1->DIER; + + if (Newstate == ENABLE) + { + /* Enable the DMA sources */ + tmpdier |= TIM1_DMASource; + } + else + { + /* Disable the DMA sources */ + tmpdier &= (u16)~TIM1_DMASource; + } + TIM1->DIER = (u16)tmpdier; +} + +/******************************************************************************* +* Function Name : TIM1_InternalClockConfig +* Description : Configures the TIM1 interrnal Clock +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_InternalClockConfig(void) +{ + /* Disable slave mode to clock the prescaler directly with the internal clock */ + TIM1->SMCR &= SMCR_SMS_Mask; +} +/******************************************************************************* +* Function Name : TIM1_ETRClockMode1Config +* Description : Configures the TIM1 External clock Mode1 +* Input : - TIM1_ExtTRGPrescaler: The external Trigger Prescaler. +* It can be one of the following values: +* - TIM1_ExtTRGPSC_OFF +* - TIM1_ExtTRGPSC_DIV2 +* - TIM1_ExtTRGPSC_DIV4 +* - TIM1_ExtTRGPSC_DIV8. +* - TIM1_ExtTRGPolarity: The external Trigger Polarity. +* It can be one of the following values: +* - TIM1_ExtTRGPolarity_Inverted +* - TIM1_ExtTRGPolarity_NonInverted +* - ExtTRGFilter: External Trigger Filter. +* This parameter must be a value between 0x00 and 0x0F +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_ETRClockMode1Config(u16 TIM1_ExtTRGPrescaler, u16 TIM1_ExtTRGPolarity, + u16 ExtTRGFilter) +{ + /* Check the parameters */ + assert(IS_TIM1_EXT_PRESCALER(TIM1_ExtTRGPrescaler)); + assert(IS_TIM1_EXT_POLARITY(TIM1_ExtTRGPolarity)); + + /* Configure the ETR Clock source */ + ETR_Config(TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity, ExtTRGFilter); + + /* Select the External clock mode1 */ + TIM1->SMCR &= SMCR_SMS_Mask; + TIM1->SMCR |= TIM1_SlaveMode_External1; + + /* Select the Trigger selection : ETRF */ + TIM1->SMCR &= SMCR_TS_Mask; + TIM1->SMCR |= TIM1_TS_ETRF; +} + +/******************************************************************************* +* Function Name : TIM1_ETRClockMode2Config +* Description : Configures the TIM1 External clock Mode2 +* Input : - TIM1_ExtTRGPrescaler: The external Trigger Prescaler. +* It can be one of the following values: +* - TIM1_ExtTRGPSC_OFF +* - TIM1_ExtTRGPSC_DIV2 +* - TIM1_ExtTRGPSC_DIV4 +* - TIM1_ExtTRGPSC_DIV8 +* - TIM1_ExtTRGPolarity: The external Trigger Polarity. +* It can be one of the following values: +* - TIM1_ExtTRGPolarity_Inverted +* - TIM1_ExtTRGPolarity_NonInverted +* - ExtTRGFilter: External Trigger Filter. +* This parameter must be a value between 0x00 and 0x0F +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_ETRClockMode2Config(u16 TIM1_ExtTRGPrescaler, u16 TIM1_ExtTRGPolarity, + u16 ExtTRGFilter) +{ + /* Check the parameters */ + assert(IS_TIM1_EXT_PRESCALER(TIM1_ExtTRGPrescaler)); + assert(IS_TIM1_EXT_POLARITY(TIM1_ExtTRGPolarity)); + + /* Configure the ETR Clock source */ + ETR_Config(TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity, ExtTRGFilter); + + /* Enable the External clock mode2 */ + *(vu32 *) SMCR_ECE_BB = SMCR_ECE_Set; +} + +/******************************************************************************* +* Function Name : TIM1_ITRxExternalClockConfig +* Description : Configures the TIM1 Internal Trigger as External Clock +* Input : - TIM1_ITRSource: Internal Trigger source. +* This parameter can be one of the following values: +* - TIM1_TS_ITR0: Internal Trigger 0 +* - TIM1_TS_ITR1: Internal Trigger 1 +* - TIM1_TS_ITR2: Internal Trigger 2 +* - TIM1_TS_ITR3: Internal Trigger 3 +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_ITRxExternalClockConfig(u16 TIM1_InputTriggerSource) +{ + /* Check the parameters */ + assert(IS_TIM1_INTERNAL_TRIGGER_SELECTION(TIM1_InputTriggerSource)); + + /* Select the Internal Trigger */ + TIM1_SelectInputTrigger(TIM1_InputTriggerSource); + + /* Select the External clock mode1 */ + TIM1->SMCR |= TIM1_SlaveMode_External1; +} + +/******************************************************************************* +* Function Name : TIM1_TIxExternalClockConfig +* Description : Configures the TIM1 Trigger as External Clock +* Input : - TIM1_TIxExternalCLKSource: Trigger source. +* This parameter can be one of the following values: +* - TIM1_TS_TI1F_ED: TI1 Edge Detector +* - TIM1_TS_TI1FP1: Filtered TIM1 Input 1 +* - TIM1_TS_TI2FP2: Filtered TIM1 Input 2 +* - TIM1_ICPolarity: specifies the TIx Polarity. +* This parameter can be: +* - TIM1_ICPolarity_Rising +* - TIM1_ICPolarity_Falling +* - ICFilter : specifies the filter value. +* This parameter must be a value between 0x0 and 0xF. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_TIxExternalClockConfig(u16 TIM1_TIxExternalCLKSource, + u16 TIM1_ICPolarity, u8 ICFilter) +{ + /* Check the parameters */ + assert(IS_TIM1_TIX_TRIGGER_SELECTION(TIM1_TIxExternalCLKSource)); + assert(IS_TIM1_IC_POLARITY(TIM1_ICPolarity)); + assert(IS_TIM1_IC_FILTER(ICFilter)); + + /* Configure the TIM1 Input Clock Source */ + if (TIM1_TIxExternalCLKSource == TIM1_TIxExternalCLK1Source_TI2) + { + TI2_Config(TIM1_ICPolarity, TIM1_ICSelection_DirectTI, ICFilter); + } + else + { + TI1_Config(TIM1_ICPolarity, TIM1_ICSelection_DirectTI, ICFilter); + } + + /* Select the Trigger source */ + TIM1_SelectInputTrigger(TIM1_TIxExternalCLKSource); + + /* Select the External clock mode1 */ + TIM1->SMCR |= TIM1_SlaveMode_External1; +} +/******************************************************************************* +* Function Name : TIM1_SelectInputTrigger +* Description : Selects the TIM1 Input Trigger source +* Input : - TIM1_InputTriggerSource: The Trigger source. +* This parameter can be one of the following values: +* - TIM1_TS_ITR0: Internal Trigger 0 +* - TIM1_TS_ITR1: Internal Trigger 1 +* - TIM1_TS_ITR2: Internal Trigger 2 +* - TIM1_TS_ITR3: Internal Trigger 3 +* - TIM1_TS_TI1F_ED: TI1 Edge Detector +* - TIM1_TS_TI1FP1: Filtered Timer Input 1 +* - TIM1_TS_TI2FP2: Filtered Timer Input 2 +* - TIM1_TS_ETRF: External Trigger input +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_SelectInputTrigger(u16 TIM1_InputTriggerSource) +{ + u32 tmpsmcr = 0; + + /* Check the parameters */ + assert(IS_TIM1_TRIGGER_SELECTION(TIM1_InputTriggerSource)); + + tmpsmcr = TIM1->SMCR; + + /* Select the Tgigger Source */ + tmpsmcr &= SMCR_TS_Mask; + tmpsmcr |= TIM1_InputTriggerSource; + + TIM1->SMCR = (u16)tmpsmcr; +} + +/******************************************************************************* +* Function Name : TIM1_UpdateDisableConfig +* Description : Enables or Disables the TIM1 Update event. +* Input : - Newstate: new state of the TIM1 peripheral Preload register +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_UpdateDisableConfig(FunctionalState Newstate) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(Newstate)); + + /* Set or Reset the UDIS Bit */ + *(vu32 *) CR1_UDIS_BB = (u16)Newstate; +} + +/******************************************************************************* +* Function Name : TIM1_UpdateRequestConfig +* Description : Selects the TIM1 Update Request Interrupt source. +* Input : - TIM1_UpdateSource: specifies the Update source. +* This parameter can be one of the following values: +* - TIM1_UpdateSource_Regular +* - TIM1_UpdateSource_Global +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_UpdateRequestConfig(u8 TIM1_UpdateSource) +{ + /* Check the parameters */ + assert(IS_TIM1_UPDATE_SOURCE(TIM1_UpdateSource)); + + /* Set or Reset the URS Bit */ + *(vu32 *) CR1_URS_BB = TIM1_UpdateSource; +} + +/******************************************************************************* +* Function Name : TIM1_SelectHallSensor +* Description : Enables or disables the TIM1’s Hall sensor interface. +* Input : - Newstate: new state of the TIM1 Hall sensor interface +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_SelectHallSensor(FunctionalState Newstate) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(Newstate)); + + /* Set or Reset the TI1S Bit */ + *(vu32 *) CR2_TI1S_BB = (u16)Newstate; +} + +/******************************************************************************* +* Function Name : TIM1_SelectOPM +* Description : Enables or disables the TIM1’s One Pulse Mode. +* Input : - TIM1_OPMode: specifies the OPM Mode to be used. +* This parameter can be one of the following values: +* - TIM1_OPMode_Single +* - TIM1_OPMode_Repetitive +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_SelectOnePulseMode(u16 TIM1_OPMode) +{ + /* Check the parameters */ + assert(IS_TIM1_OPM_MODE(TIM1_OPMode)); + + /* Set or Reset the OPM Bit */ + *(vu32 *) CR1_OPM_BB = TIM1_OPMode; +} + +/******************************************************************************* +* Function Name : TIM1_SelectOutputTrigger +* Description : Selects the TIM1 Trigger Output Mode. +* Input : - TIM1_TRGOSource: specifies the Trigger Output source. +* This paramter can be one of the following values: +* - TIM1_TRGOSource_Reset +* - TIM1_TRGOSource_Enable +* - TIM1_TRGOSource_Update +* - TIM1_TRGOSource_OC1 +* - TIM1_TRGOSource_OC1Ref +* - TIM1_TRGOSource_OC2Ref +* - TIM1_TRGOSource_OC3Ref +* - TIM1_TRGOSource_OC4Ref +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_SelectOutputTrigger(u16 TIM1_TRGOSource) +{ + u32 tmpcr2 = 0; + + /* Check the parameters */ + assert(IS_TIM1_TRGO_SOURCE(TIM1_TRGOSource)); + + tmpcr2 = TIM1->CR2; + + /* Reset the MMS Bits */ + tmpcr2 &= CR2_MMS_Mask; + + /* Select the TRGO source */ + tmpcr2 |= TIM1_TRGOSource; + + TIM1->CR2 = (u16)tmpcr2; +} + +/******************************************************************************* +* Function Name : TIM1_SelectSlaveMode +* Description : Selects the TIM1 Slave Mode. +* Input : - TIM1_SlaveMode: specifies the TIM1 Slave Mode. +* This paramter can be one of the following values: +* - TIM1_SlaveMode_Reset +* - TIM1_SlaveMode_Gated +* - TIM1_SlaveMode_Trigger +* - TIM1_SlaveMode_External1 +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_SelectSlaveMode(u16 TIM1_SlaveMode) +{ + u32 tmpsmcr = 0; + + /* Check the parameters */ + assert(IS_TIM1_SLAVE_MODE(TIM1_SlaveMode)); + + tmpsmcr = TIM1->SMCR; + + /* Reset the SMS Bits */ + tmpsmcr &= SMCR_SMS_Mask; + + /* Select the Slave Mode */ + tmpsmcr |= TIM1_SlaveMode; + + TIM1->SMCR = (u16)tmpsmcr; +} + +/******************************************************************************* +* Function Name : TIM1_SelectMasterSlaveMode +* Description : Sets or Resets the TIM1 Master/Slave Mode. +* Input : - TIM1_MasterSlaveMode: specifies the TIM1 Master Slave Mode. +* This paramter can be one of the following values: +* - TIM1_MasterSlaveMode_Enable: synchronization between +* the current timer and its slaves (through TRGO). +* - TIM1_MasterSlaveMode_Disable: No action +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_SelectMasterSlaveMode(u16 TIM1_MasterSlaveMode) +{ + /* Check the parameters */ + assert(IS_TIM1_MSM_STATE(TIM1_MasterSlaveMode)); + + /* Set or Reset the MSM Bit */ + *(vu32 *) SMCR_MSM_BB = TIM1_MasterSlaveMode; +} + +/******************************************************************************* +* Function Name : TIM1_EncoderInterfaceConfig +* Description : Configures the TIM1 Encoder Interface. +* Input : - TIM1_EncoderMode: specifies the TIM1 Encoder Mode. +* This parameter can be one of the following values: +* - TIM1_EncoderMode_TI1: Counter counts on TI1FP1 edge +* depending on TI2FP2 level. +* - TIM1_EncoderMode_TI2: Counter counts on TI2FP2 edge +* depending on TI1FP1 level. +* - TIM1_EncoderMode_TI12: Counter counts on both TI1FP1 and +* TI2FP2 edges depending on the level of the other input. +* - TIM1_IC1Polarity: specifies the IC1 Polarity +* This parmeter can be one of the following values: +* - TIM1_ICPolarity_Falling +* - TIM1_ICPolarity_Rising +* - TIM1_IC2Polarity: specifies the IC2 Polarity +* This parmeter can be one of the following values: +* - TIM1_ICPolarity_Falling +* - TIM1_ICPolarity_Rising +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_EncoderInterfaceConfig(u16 TIM1_EncoderMode, u16 TIM1_IC1Polarity, + u16 TIM1_IC2Polarity) +{ + u32 tmpsmcr = 0; + u32 tmpccmr1 = 0; + + /* Check the parameters */ + assert(IS_TIM1_ENCODER_MODE(TIM1_EncoderMode)); + assert(IS_TIM1_IC_POLARITY(TIM1_IC1Polarity)); + assert(IS_TIM1_IC_POLARITY(TIM1_IC2Polarity)); + + tmpsmcr = TIM1->SMCR; + tmpccmr1 = TIM1->CCMR1; + + /* Set the encoder Mode */ + tmpsmcr &= SMCR_SMS_Mask; + tmpsmcr |= TIM1_EncoderMode; + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= CCMR_CC13S_Mask & CCMR_CC24S_Mask; + tmpccmr1 |= CCMR_TI13Direct_Set | CCMR_TI24Direct_Set; + + /* Set the TI1 and the TI2 Polarities */ + *(vu32 *) CCER_CC1P_BB = TIM1_IC1Polarity; + *(vu32 *) CCER_CC2P_BB = TIM1_IC2Polarity; + + TIM1->SMCR = (u16)tmpsmcr; + + TIM1->CCMR1 = (u16)tmpccmr1; +} + +/******************************************************************************* +* Function Name : TIM1_PrescalerConfig +* Description : Configures the TIM1 Prescaler. +* Input : - Prescaler: specifies the Prescaler Register value +* - TIM1_PSCReloadMode: specifies the TIM1 Prescaler Reload mode. +* This parmeter can be one of the following values: +* - TIM1_PSCReloadMode_Update: The Prescaler is loaded at +* the update event. +* - TIM1_PSCReloadMode_Immediate: The Prescaler is loaded +* immediatly. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_PrescalerConfig(u16 Prescaler, u16 TIM1_PSCReloadMode) +{ + /* Check the parameters */ + assert(IS_TIM1_PRESCALER_RELOAD(TIM1_PSCReloadMode)); + + /* Set the Prescaler value */ + TIM1->PSC = Prescaler; + + /* Set or reset the UG Bit */ + *(vu32 *) EGR_UG_BB = TIM1_PSCReloadMode; +} +/******************************************************************************* +* Function Name : TIM1_CounterModeConfig +* Description : Specifies the TIM1 Counter Mode to be used. +* Input : - TIM1_CounterMode: specifies the Counter Mode to be used +* This parameter can be one of the following values: +* - TIM1_CounterMode_Up: TIM1 Up Counting Mode +* - TIM1_CounterMode_Down: TIM1 Down Counting Mode +* - TIM1_CounterMode_CenterAligned1: TIM1 Center Aligned Mode1 +* - TIM1_CounterMode_CenterAligned2: TIM1 Center Aligned Mode2 +* - TIM1_CounterMode_CenterAligned3: TIM1 Center Aligned Mode3 +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_CounterModeConfig(u16 TIM1_CounterMode) +{ + u32 tmpcr1 = 0; + + /* Check the parameters */ + assert(IS_TIM1_COUNTER_MODE(TIM1_CounterMode)); + + tmpcr1 = TIM1->CR1; + + /* Reset the CMS and DIR Bits */ + tmpcr1 &= CR1_CounterMode_Mask; + + /* Set the Counter Mode */ + tmpcr1 |= TIM1_CounterMode; + + TIM1->CR1 = (u16)tmpcr1; +} + +/******************************************************************************* +* Function Name : TIM1_ForcedOC1Config +* Description : Forces the TIM1 Channel1 output waveform to active or inactive +* level. +* Input : - TIM1_ForcedAction: specifies the forced Action to be set to +* the output waveform. +* This parameter can be one of the following values: +* - TIM1_ForcedAction_Active: Force active level on OC1REF +* - TIM1_ForcedAction_InActive: Force inactive level on +* OC1REF. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_ForcedOC1Config(u16 TIM1_ForcedAction) +{ + u32 tmpccmr1 = 0; + + /* Check the parameters */ + assert(IS_TIM1_FORCED_ACTION(TIM1_ForcedAction)); + + tmpccmr1 = TIM1->CCMR1; + + /* Reset the OCM Bits */ + tmpccmr1 &= CCMR_OCM13_Mask; + + /* Configure The Forced output Mode */ + tmpccmr1 |= TIM1_ForcedAction; + + TIM1->CCMR1 = (u16)tmpccmr1; +} + +/******************************************************************************* +* Function Name : TIM1_ForcedOC2Config +* Description : Forces the TIM1 Channel2 output waveform to active or inactive +* level. +* Input : - TIM1_ForcedAction: specifies the forced Action to be set to +* the output waveform. +* This parameter can be one of the following values: +* - TIM1_ForcedAction_Active: Force active level on OC2REF +* - TIM1_ForcedAction_InActive: Force inactive level on +* OC2REF. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_ForcedOC2Config(u16 TIM1_ForcedAction) +{ + u32 tmpccmr1 = 0; + + /* Check the parameters */ + assert(IS_TIM1_FORCED_ACTION(TIM1_ForcedAction)); + + tmpccmr1 = TIM1->CCMR1; + + /* Reset the OCM Bits */ + tmpccmr1 &= CCMR_OCM24_Mask; + + /* Configure The Forced output Mode */ + tmpccmr1 |= (u32)TIM1_ForcedAction << 8; + + TIM1->CCMR1 = (u16)tmpccmr1; +} + +/******************************************************************************* +* Function Name : TIM1_ForcedOC3Config +* Description : Forces the TIM1 Channel3 output waveform to active or inactive +* level. +* Input : - TIM1_ForcedAction: specifies the forced Action to be set to +* the output waveform. +* This parameter can be one of the following values: +* - TIM1_ForcedAction_Active: Force active level on OC3REF +* - TIM1_ForcedAction_InActive: Force inactive level on +* OC3REF. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_ForcedOC3Config(u16 TIM1_ForcedAction) +{ + u32 tmpccmr2 = 0; + + /* Check the parameters */ + assert(IS_TIM1_FORCED_ACTION(TIM1_ForcedAction)); + + tmpccmr2 = TIM1->CCMR2; + + /* Reset the OCM Bits */ + tmpccmr2 &= CCMR_OCM13_Mask; + + /* Configure The Forced output Mode */ + tmpccmr2 |= TIM1_ForcedAction; + + TIM1->CCMR2 = (u16)tmpccmr2; +} + +/******************************************************************************* +* Function Name : TIM1_ForcedOC4Config +* Description : Forces the TIM1 Channel4 output waveform to active or inactive +* level. +* Input : - TIM1_ForcedAction: specifies the forced Action to be set to +* the output waveform. +* This parameter can be one of the following values: +* - TIM1_ForcedAction_Active: Force active level on OC4REF +* - TIM1_ForcedAction_InActive: Force inactive level on +* OC4REF. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_ForcedOC4Config(u16 TIM1_ForcedAction) +{ + u32 tmpccmr2 = 0; + + /* Check the parameters */ + assert(IS_TIM1_FORCED_ACTION(TIM1_ForcedAction)); + + tmpccmr2 = TIM1->CCMR1; + + /* Reset the OCM Bits */ + tmpccmr2 &= CCMR_OCM24_Mask; + + /* Configure The Forced output Mode */ + tmpccmr2 |= (u16)((u16)TIM1_ForcedAction << 8); + + TIM1->CCMR2 = (u16)tmpccmr2; +} + +/******************************************************************************* +* Function Name : TIM1_ARRPreloadConfig +* Description : Enables or disables TIM1 peripheral Preload register on ARR. +* Input : - Newstate: new state of the TIM1 peripheral Preload register +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_ARRPreloadConfig(FunctionalState Newstate) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(Newstate)); + + /* Set or Reset the ARPE Bit */ + *(vu32 *) CR1_ARPE_BB = (u16)Newstate; +} + +/******************************************************************************* +* Function Name : TIM1_SelectCOM +* Description : Selects the TIM1 peripheral Commutation event. +* Input : - Newstate: new state of the Commutation event. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_SelectCOM(FunctionalState Newstate) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(Newstate)); + + /* Set or Reset the CCUS Bit */ + *(vu32 *) CR2_CCUS_BB = (u16)Newstate; +} + +/******************************************************************************* +* Function Name : TIM1_SelectCCDMA +* Description : Selects the TIM1 peripheral Capture Compare DMA source. +* Input : - Newstate: new state of the Capture Compare DMA source +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_SelectCCDMA(FunctionalState Newstate) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(Newstate)); + + /* Set or Reset the CCDS Bit */ + *(vu32 *) CR2_CCDS_BB = (u16)Newstate; +} + +/******************************************************************************* +* Function Name : TIM1_CCPreloadControl +* Description : Sets or Resets the TIM1 peripheral Capture Compare Preload +* Control bit. +* Input : - Newstate: new state of the Capture Compare Preload Control bit +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_CCPreloadControl(FunctionalState Newstate) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(Newstate)); + + /* Set or Reset the CCPC Bit */ + *(vu32 *) CR2_CCPC_BB = (u16)Newstate; +} + +/******************************************************************************* +* Function Name : TIM1_OC1PreloadConfig +* Description : Enables or disables the TIM1 peripheral Preload Register on CCR1. +* Input : - TIM1_OCPreload: new state of the Capture Compare Preload +* register. +* This parameter can be one of the following values: +* - TIM1_OCPreload_Enable +* - TIM1_OCPreload_Disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_OC1PreloadConfig(u16 TIM1_OCPreload) +{ + /* Check the parameters */ + assert(IS_TIM1_OCPRELOAD_STATE(TIM1_OCPreload)); + + /* Set or Reset the OC1PE Bit */ + *(vu32 *) CCMR1_OC1PE_BB = (u16)TIM1_OCPreload; +} + +/******************************************************************************* +* Function Name : TIM1_OC2PreloadConfig +* Description : Enables or disables the TIM1 peripheral Preload Register on CCR2. +* Input : - TIM1_OCPreload: new state of the Capture Compare Preload +* register. +* This parameter can be one of the following values: +* - TIM1_OCPreload_Enable +* - TIM1_OCPreload_Disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_OC2PreloadConfig(u16 TIM1_OCPreload) +{ + /* Check the parameters */ + assert(IS_TIM1_OCPRELOAD_STATE(TIM1_OCPreload)); + + /* Set or Reset the OC2PE Bit */ + *(vu32 *) CCMR1_OC2PE_BB = (u16)TIM1_OCPreload; +} + +/******************************************************************************* +* Function Name : TIM1_OC3PreloadConfig +* Description : Enables or disables the TIM1 peripheral Preload Register on CCR3. +* Input : - TIM1_OCPreload: new state of the Capture Compare Preload +* register. +* This parameter can be one of the following values: +* - TIM1_OCPreload_Enable +* - TIM1_OCPreload_Disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_OC3PreloadConfig(u16 TIM1_OCPreload) +{ + /* Check the parameters */ + assert(IS_TIM1_OCPRELOAD_STATE(TIM1_OCPreload)); + + /* Set or Reset the OC3PE Bit */ + *(vu32 *) CCMR2_OC3PE_BB = (u16)TIM1_OCPreload; +} + +/******************************************************************************* +* Function Name : TIM1_OC4PreloadConfig +* Description : Enables or disables the TIM1 peripheral Preload Register on CCR4. +* Input : - TIM1_OCPreload: new state of the Capture Compare Preload +* register. +* This parameter can be one of the following values: +* - TIM1_OCPreload_Enable +* - TIM1_OCPreload_Disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_OC4PreloadConfig(u16 TIM1_OCPreload) +{ + /* Check the parameters */ + assert(IS_TIM1_OCPRELOAD_STATE(TIM1_OCPreload)); + + /* Set or Reset the OC4PE Bit */ + *(vu32 *) CCMR2_OC4PE_BB = (u16)TIM1_OCPreload; +} + +/******************************************************************************* +* Function Name : TIM1_OC1FastConfig +* Description : Configures the TIM1 Capture Compare 1 Fast feature. +* Input : - TIM1_OCFast: new state of the Output Compare Fast Enable bit. +* This parameter can be one of the following values: +* - TIM1_OCFast_Enable +* - TIM1_OCFast_Disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_OC1FastConfig(u16 TIM1_OCFast) +{ + /* Check the parameters */ + assert(IS_TIM1_OCFAST_STATE(TIM1_OCFast)); + + /* Set or Reset the OC1FE Bit */ + *(vu32 *) CCMR1_OC1FE_BB = (u16)TIM1_OCFast; +} + +/******************************************************************************* +* Function Name : TIM1_OC2FastConfig +* Description : Configures the TIM1 Capture Compare Fast feature. +* Input : - TIM1_OCFast: new state of the Output Compare Fast Enable bit. +* This parameter can be one of the following values: +* - TIM1_OCFast_Enable +* - TIM1_OCFast_Disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_OC2FastConfig(u16 TIM1_OCFast) +{ + /* Check the parameters */ + assert(IS_TIM1_OCFAST_STATE(TIM1_OCFast)); + + /* Set or Reset the OC2FE Bit */ + *(vu32 *) CCMR1_OC2FE_BB = (u16)TIM1_OCFast; +} + +/******************************************************************************* +* Function Name : TIM1_OC3FastConfig +* Description : Configures the TIM1 Capture Compare Fast feature. +* Input : - TIM1_OCFast: new state of the Output Compare Fast Enable bit. +* This parameter can be one of the following values: +* - TIM1_OCFast_Enable +* - TIM1_OCFast_Disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_OC3FastConfig(u16 TIM1_OCFast) +{ + /* Check the parameters */ + assert(IS_TIM1_OCFAST_STATE(TIM1_OCFast)); + + /* Set or Reset the OC3FE Bit */ + *(vu32 *) CCMR2_OC3FE_BB = (u16)TIM1_OCFast; +} + +/******************************************************************************* +* Function Name : TIM1_OC4FastConfig +* Description : Configures the TIM1 Capture Compare Fast feature. +* Input : - TIM1_OCFast: new state of the Output Compare Fast Enable bit. +* This parameter can be one of the following values: +* - TIM1_OCFast_Enable +* - TIM1_OCFast_Disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_OC4FastConfig(u16 TIM1_OCFast) +{ + /* Check the parameters */ + assert(IS_TIM1_OCFAST_STATE(TIM1_OCFast)); + + /* Set or Reset the OC4FE Bit */ + *(vu32 *) CCMR2_OC4FE_BB = (u16)TIM1_OCFast; +} + +/******************************************************************************* +* Function Name : TIM1_GenerateEvent +* Description : Configures the TIM1 event to be generate by software. +* Input : - TIM1_EventSource: specifies the event source. +* This parameter can be one or more of the following values: +* - TIM1_EventSource_Update: TIM1 update Event source +* - TIM1_EventSource_CC1: TIM1 Capture Compare 1 Event source +* - TIM1_EventSource_CC2: TIM1 Capture Compare 2 Event source +* - TIM1_EventSource_CC3: TIM1 Capture Compare 3 Event source +* - TIM1_EventSource_CC4: TIM1 Capture Compare 4 Event source +* - TIM1_EventSource_COM: TIM1 COM Event source +* - TIM1_EventSource_Trigger: TIM1 Trigger Event source +* - TIM1_EventSourceBreak: TIM1 Break Event source +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_GenerateEvent(u16 TIM1_EventSource) +{ + /* Check the parameters */ + assert(IS_TIM1_EVENT_SOURCE(TIM1_EventSource)); + + /* Set the event sources */ + TIM1->EGR |= TIM1_EventSource; +} + +/******************************************************************************* +* Function Name : TIM1_OC1PolarityConfig +* Description : Configures the TIM1 Channel 1 polarity. +* Input : - TIM1_OCPolarity: specifies the OC1 Polarity +* This parmeter can be one of the following values: +* - TIM1_OCPolarity_High: Output Compare active high +* - TIM1_OCPolarity_Low: Output Compare active low +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_OC1PolarityConfig(u16 TIM1_OCPolarity) +{ + /* Check the parameters */ + assert(IS_TIM1_OC_POLARITY(TIM1_OCPolarity)); + + /* Set or Reset the CC1P Bit */ + *(vu32 *) CCER_CC1P_BB = (u16)TIM1_OCPolarity; +} + +/******************************************************************************* +* Function Name : TIM1_OC1NPolarityConfig +* Description : Configures the TIM1 Channel 1N polarity. +* Input : - TIM1_OCPolarity: specifies the OC1N Polarity +* This parmeter can be one of the following values: +* - TIM1_OCPolarity_High: Output Compare active high +* - TIM1_OCPolarity_Low: Output Compare active low +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_OC1NPolarityConfig(u16 TIM1_OCPolarity) +{ + /* Check the parameters */ + assert(IS_TIM1_OC_POLARITY(TIM1_OCPolarity)); + + /* Set or Reset the CC3P Bit */ + *(vu32 *) CCER_CC1NP_BB = (u16)TIM1_OCPolarity; +} + +/******************************************************************************* +* Function Name : TIM1_OC2PolarityConfig +* Description : Configures the TIM1 Channel 2 polarity. +* Input : - TIM1_OCPolarity: specifies the OC2 Polarity +* This parmeter can be one of the following values: +* - TIM1_OCPolarity_High: Output Compare active high +* - TIM1_OCPolarity_Low: Output Compare active low +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_OC2PolarityConfig(u16 TIM1_OCPolarity) +{ + /* Check the parameters */ + assert(IS_TIM1_OC_POLARITY(TIM1_OCPolarity)); + + /* Set or Reset the CC2P Bit */ + *(vu32 *) CCER_CC2P_BB = (u16)TIM1_OCPolarity; +} + +/******************************************************************************* +* Function Name : TIM1_OC2NPolarityConfig +* Description : Configures the TIM1 Channel 2N polarity. +* Input : - TIM1_OCPolarity: specifies the OC2N Polarity +* This parmeter can be one of the following values: +* - TIM1_OCPolarity_High: Output Compare active high +* - TIM1_OCPolarity_Low: Output Compare active low +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_OC2NPolarityConfig(u16 TIM1_OCPolarity) +{ + /* Check the parameters */ + assert(IS_TIM1_OC_POLARITY(TIM1_OCPolarity)); + + /* Set or Reset the CC3P Bit */ + *(vu32 *) CCER_CC2NP_BB = (u16)TIM1_OCPolarity; +} + +/******************************************************************************* +* Function Name : TIM1_OC3PolarityConfig +* Description : Configures the TIM1 Channel 3 polarity. +* Input : - TIM1_OCPolarity: specifies the OC3 Polarity +* This parmeter can be one of the following values: +* - TIM1_OCPolarity_High: Output Compare active high +* - TIM1_OCPolarity_Low: Output Compare active low +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_OC3PolarityConfig(u16 TIM1_OCPolarity) +{ + /* Check the parameters */ + assert(IS_TIM1_OC_POLARITY(TIM1_OCPolarity)); + + /* Set or Reset the CC3P Bit */ + *(vu32 *) CCER_CC3P_BB = (u16)TIM1_OCPolarity; +} + +/******************************************************************************* +* Function Name : TIM1_OC3NPolarityConfig +* Description : Configures the TIM1 Channel 3N polarity. +* Input : - TIM1_OCPolarity: specifies the OC3N Polarity +* This parmeter can be one of the following values: +* - TIM1_OCPolarity_High: Output Compare active high +* - TIM1_OCPolarity_Low: Output Compare active low +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_OC3NPolarityConfig(u16 TIM1_OCPolarity) +{ + /* Check the parameters */ + assert(IS_TIM1_OC_POLARITY(TIM1_OCPolarity)); + + /* Set or Reset the CC3P Bit */ + *(vu32 *) CCER_CC3NP_BB = (u16)TIM1_OCPolarity; +} + +/******************************************************************************* +* Function Name : TIM1_OC4PolarityConfig +* Description : Configures the TIM1 Channel 4 polarity. +* Input : - TIM1_OCPolarity: specifies the OC4 Polarity +* This parmeter can be one of the following values: +* - TIM1_OCPolarity_High: Output Compare active high +* - TIM1_OCPolarity_Low: Output Compare active low +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_OC4PolarityConfig(u16 TIM1_OCPolarity) +{ + /* Check the parameters */ + assert(IS_TIM1_OC_POLARITY(TIM1_OCPolarity)); + + /* Set or Reset the CC4P Bit */ + *(vu32 *) CCER_CC4P_BB = (u16)TIM1_OCPolarity; +} + +/******************************************************************************* +* Function Name : TIM1_CCxCmd +* Description : Enables or disables the TIM1 Capture Compare Channel x. +* Input : - TIM1_Channel: specifies the TIM1 Channel +* This parmeter can be one of the following values: +* - TIM1_Channel1: TIM1 Channel1 +* - TIM1_Channel2: TIM1 Channel2 +* - TIM1_Channel3: TIM1 Channel3 +* - TIM1_Channel4: TIM1 Channel4 +* - Newstate: specifies the TIM1 Channel CCxE bit new state. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_CCxCmd(u16 TIM1_Channel, FunctionalState Newstate) +{ + /* Check the parameters */ + assert(IS_TIM1_CHANNEL(TIM1_Channel)); + assert(IS_FUNCTIONAL_STATE(Newstate)); + + if(TIM1_Channel == TIM1_Channel_1) + { + /* Set or Reset the CC1E Bit */ + *(vu32 *) CCER_CC1E_BB = (u16)Newstate; + } + else if(TIM1_Channel == TIM1_Channel_2) + { + /* Set or Reset the CC2E Bit */ + *(vu32 *) CCER_CC2E_BB = (u16)Newstate; + } + else if(TIM1_Channel == TIM1_Channel_3) + { + /* Set or Reset the CC3E Bit */ + *(vu32 *) CCER_CC3E_BB = (u16)Newstate; + } + else + { + /* Set or Reset the CC4E Bit */ + *(vu32 *) CCER_CC4E_BB = (u16)Newstate; + } +} + +/******************************************************************************* +* Function Name : TIM1_CCxNCmd +* Description : Enables or disables the TIM1 Capture Compare Channel xN. +* Input : - TIM1_Channel: specifies the TIM1 Channel +* This parmeter can be one of the following values: +* - TIM1_Channel1: TIM1 Channel1 +* - TIM1_Channel2: TIM1 Channel2 +* - TIM1_Channel3: TIM1 Channel3 +* - Newstate: specifies the TIM1 Channel CCxNE bit new state. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_CCxNCmd(u16 TIM1_Channel, FunctionalState Newstate) +{ + /* Check the parameters */ + assert(IS_TIM1_COMPLEMENTARY_CHANNEL(TIM1_Channel)); + assert(IS_FUNCTIONAL_STATE(Newstate)); + + if(TIM1_Channel == TIM1_Channel_1) + { + /* Set or Reset the CC1NE Bit */ + *(vu32 *) CCER_CC1NE_BB = (u16)Newstate; + } + else if(TIM1_Channel == TIM1_Channel_2) + { + /* Set or Reset the CC2NE Bit */ + *(vu32 *) CCER_CC2NE_BB = (u16)Newstate; + } + else + { + /* Set or Reset the CC3NE Bit */ + *(vu32 *) CCER_CC3NE_BB = (u16)Newstate; + } +} + +/******************************************************************************* +* Function Name : TIM1_SelectOCxM +* Description : Selects the TIM1 Ouput Compare Mode. +* This function disables the selected channel before changing +* the Ouput Compare Mode. User has to enable this channel using +* TIM1_CCxCmd and TIM1_CCxNCmd functions. +* Input : - TIM1_Channel: specifies the TIM1 Channel +* This parmeter can be one of the following values: +* - TIM1_Channel1: TIM1 Channel1 +* - TIM1_Channel2: TIM1 Channel2 +* - TIM1_Channel3: TIM1 Channel3 +* - TIM1_Channel4: TIM1 Channel4 +* - TIM1_OCMode: specifies the TIM1 Output Compare Mode. +* This paramter can be one of the following values: +* - TIM1_OCMode_Timing +* - TIM1_OCMode_Active +* - TIM1_OCMode_Toggle +* - TIM1_OCMode_PWM1 +* - TIM1_OCMode_PWM2 +* - TIM1_ForcedAction_Active +* - TIM1_ForcedAction_InActive +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_SelectOCxM(u16 TIM1_Channel, u16 TIM1_OCMode) +{ + /* Check the parameters */ + assert(IS_TIM1_CHANNEL(TIM1_Channel)); + assert(IS_TIM1_OCM(TIM1_OCMode)); + + if(TIM1_Channel == TIM1_Channel_1) + { + /* Disable the Channel 1: Reset the CCE Bit */ + *(vu32 *) CCER_CC1E_BB = CCER_CCE_Reset; + + /* Reset the Output Compare Bits */ + TIM1->CCMR1 &= OC13Mode_Mask; + + /* Set the Ouput Compare Mode */ + TIM1->CCMR1 |= TIM1_OCMode; + } + else if(TIM1_Channel == TIM1_Channel_2) + { + /* Disable the Channel 2: Reset the CCE Bit */ + *(vu32 *) CCER_CC2E_BB = CCER_CCE_Reset; + + /* Reset the Output Compare Bits */ + TIM1->CCMR1 &= OC24Mode_Mask; + + /* Set the Ouput Compare Mode */ + TIM1->CCMR1 |= (u16)((u16)TIM1_OCMode << 8); + } + else if(TIM1_Channel == TIM1_Channel_3) + { + /* Disable the Channel 3: Reset the CCE Bit */ + *(vu32 *) CCER_CC3E_BB = CCER_CCE_Reset; + + /* Reset the Output Compare Bits */ + TIM1->CCMR2 &= OC13Mode_Mask; + + /* Set the Ouput Compare Mode */ + TIM1->CCMR2 |= TIM1_OCMode; + } + else + { + /* Disable the Channel 4: Reset the CCE Bit */ + *(vu32 *) CCER_CC4E_BB = CCER_CCE_Reset; + + /* Reset the Output Compare Bits */ + TIM1->CCMR2 &= OC24Mode_Mask; + + /* Set the Ouput Compare Mode */ + TIM1->CCMR2 |= (u16)((u16)TIM1_OCMode << 8); + } +} + +/******************************************************************************* +* Function Name : TIM1_SetAutoreload +* Description : Sets the TIM1 Autoreload Register value. +* Input : - Autoreload: specifies the Autoreload register new value. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_SetAutoreload(u16 Autoreload) +{ + /* Set the Autoreload Register value */ + TIM1->ARR = Autoreload; +} + +/******************************************************************************* +* Function Name : TIM1_SetCompare1 +* Description : Sets the TIM1 Capture Compare1 Register value. +* Input : - Compare1: specifies the Capture Compare1 register new value. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_SetCompare1(u16 Compare1) +{ + /* Set the Capture Compare1 Register value */ + TIM1->CCR1 = Compare1; +} + +/******************************************************************************* +* Function Name : TIM1_SetCompare2 +* Description : Sets the TIM1 Capture Compare2 Register value. +* Input : - Compare2: specifies the Capture Compare2 register new value. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_SetCompare2(u16 Compare2) +{ + /* Set the Capture Compare2 Register value */ + TIM1->CCR2 = Compare2; +} + +/******************************************************************************* +* Function Name : TIM1_SetCompare3 +* Description : Sets the TIM1 Capture Compare3 Register value. +* Input : - Compare3: specifies the Capture Compare3 register new value. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_SetCompare3(u16 Compare3) +{ + /* Set the Capture Compare3 Register value */ + TIM1->CCR3 = Compare3; +} + +/******************************************************************************* +* Function Name : TIM1_SetCompare4 +* Description : Sets the TIM1 Capture Compare4 Register value. +* Input : - Compare4: specifies the Capture Compare4 register new value. +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_SetCompare4(u16 Compare4) +{ + /* Set the Capture Compare4 Register value */ + TIM1->CCR4 = Compare4; +} + +/******************************************************************************* +* Function Name : TIM1_SetIC1Prescaler +* Description : Sets the TIM1 Input Capture 1 prescaler. +* Input : - TIM1_IC1Prescaler: specifies the Input Capture prescaler +* new value. +* This parameter can be one of the following values: +* - TIM1_ICPSC_DIV1: no prescaler +* - TIM1_ICPSC_DIV2: capture is done once every 2 events +* - TIM1_ICPSC_DIV4: capture is done once every 4 events +* - TIM1_ICPSC_DIV8: capture is done once every 8 events +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_SetIC1Prescaler(u16 TIM1_IC1Prescaler) +{ + u32 tmpccmr1 = 0; + + /* Check the parameters */ + assert(IS_TIM1_IC_PRESCALER(TIM1_IC1Prescaler)); + + tmpccmr1 = TIM1->CCMR1; + + /* Reset the IC1PSC Bits */ + tmpccmr1 &= CCMR_IC13PSC_Mask; + + /* Set the IC1PSC value */ + tmpccmr1 |= TIM1_IC1Prescaler; + + TIM1->CCMR1 = (u16)tmpccmr1; +} + +/******************************************************************************* +* Function Name : TIM1_SetIC2Prescaler +* Description : Sets the TIM1 Input Capture 2 prescaler. +* Input : - TIM1_IC2Prescaler: specifies the Input Capture prescaler +* new value. +* This parameter can be one of the following values: +* - TIM1_ICPSC_DIV1: no prescaler +* - TIM1_ICPSC_DIV2: capture is done once every 2 events +* - TIM1_ICPSC_DIV4: capture is done once every 4 events +* - TIM1_ICPSC_DIV8: capture is done once every 8 events +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_SetIC2Prescaler(u16 TIM1_IC2Prescaler) +{ + u32 tmpccmr1 = 0; + + /* Check the parameters */ + assert(IS_TIM1_IC_PRESCALER(TIM1_IC2Prescaler)); + + tmpccmr1 = TIM1->CCMR1; + + /* Reset the IC2PSC Bits */ + tmpccmr1 &= CCMR_IC24PSC_Mask; + + /* Set the IC2PSC value */ + tmpccmr1 |= (u16)((u16)TIM1_IC2Prescaler << 8); + + TIM1->CCMR1 = (u16)tmpccmr1; +} + +/******************************************************************************* +* Function Name : TIM1_SetIC3Prescaler +* Description : Sets the TIM1 Input Capture 3 prescaler. +* Input : - TIM1_IC3Prescaler: specifies the Input Capture prescaler +* new value. +* This parameter can be one of the following values: +* - TIM1_ICPSC_DIV1: no prescaler +* - TIM1_ICPSC_DIV2: capture is done once every 2 events +* - TIM1_ICPSC_DIV4: capture is done once every 4 events +* - TIM1_ICPSC_DIV8: capture is done once every 8 events +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_SetIC3Prescaler(u16 TIM1_IC3Prescaler) +{ + u32 tmpccmr2 = 0; + + /* Check the parameters */ + assert(IS_TIM1_IC_PRESCALER(TIM1_IC3Prescaler)); + + tmpccmr2 = TIM1->CCMR2; + + /* Reset the IC3PSC Bits */ + tmpccmr2 &= CCMR_IC13PSC_Mask; + + /* Set the IC3PSC value */ + tmpccmr2 |= TIM1_IC3Prescaler; + + TIM1->CCMR2 = (u16)tmpccmr2; +} + +/******************************************************************************* +* Function Name : TIM1_SetIC4Prescaler +* Description : Sets the TIM1 Input Capture 4 prescaler. +* Input : - TIM1_IC4Prescaler: specifies the Input Capture prescaler +* new value. +* This parameter can be one of the following values: +* - TIM1_ICPSC_DIV1: no prescaler +* - TIM1_ICPSC_DIV2: capture is done once every 2 events +* - TIM1_ICPSC_DIV4: capture is done once every 4 events +* - TIM1_ICPSC_DIV8: capture is done once every 8 events +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_SetIC4Prescaler(u16 TIM1_IC4Prescaler) +{ + u32 tmpccmr2 = 0; + + /* Check the parameters */ + assert(IS_TIM1_IC_PRESCALER(TIM1_IC4Prescaler)); + + tmpccmr2 = TIM1->CCMR2; + + /* Reset the IC4PSC Bits */ + tmpccmr2 &= CCMR_IC24PSC_Mask; + + /* Set the IC4PSC value */ + tmpccmr2 |= (u16)((u16)TIM1_IC4Prescaler << 8); + + TIM1->CCMR2 = (u16)tmpccmr2; +} + +/******************************************************************************* +* Function Name : TIM1_SetClockDivision +* Description : Sets the TIM1 Clock Division value. +* Input : - TIM1_CKD: specifies the clock division value. +* This parameter can be one of the following value: +* - TIM1_CKD_DIV1: TDTS = Tck_tim +* - TIM1_CKD_DIV2: TDTS = 2*Tck_tim +* - TIM1_CKD_DIV4: TDTS = 4*Tck_tim +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_SetClockDivision(u16 TIM1_CKD) +{ + u32 tmpcr1 = 0; + + /* Check the parameters */ + assert(IS_TIM1_CKD_DIV(TIM1_CKD)); + + tmpcr1 = TIM1->CR1; + + /* Reset the CKD Bits */ + tmpcr1 &= CR1_CKD_Mask; + + /* Set the CKD value */ + tmpcr1 |= TIM1_CKD; + + TIM1->CR1 = (u16)tmpcr1; +} + +/******************************************************************************* +* Function Name : TIM1_GetCapture1 +* Description : Gets the TIM1 Input Capture 1 value. +* Input : None +* Output : None +* Return : Capture Compare 1 Register value. +*******************************************************************************/ +u16 TIM1_GetCapture1(void) +{ + /* Get the Capture 1 Register value */ + return TIM1->CCR1; +} + +/******************************************************************************* +* Function Name : TIM1_GetCapture2 +* Description : Gets the TIM1 Input Capture 2 value. +* Input : None +* Output : None +* Return : Capture Compare 2 Register value. +*******************************************************************************/ +u16 TIM1_GetCapture2(void) +{ + /* Get the Capture 2 Register value */ + return TIM1->CCR2; +} + +/******************************************************************************* +* Function Name : TIM1_GetCapture3 +* Description : Gets the TIM1 Input Capture 3 value. +* Input : None +* Output : None +* Return : Capture Compare 3 Register value. +*******************************************************************************/ +u16 TIM1_GetCapture3(void) +{ + /* Get the Capture 3 Register value */ + return TIM1->CCR3; +} + +/******************************************************************************* +* Function Name : TIM1_GetCapture4 +* Description : Gets the TIM1 Input Capture 4 value. +* Input : None +* Output : None +* Return : Capture Compare 4 Register value. +*******************************************************************************/ +u16 TIM1_GetCapture4(void) +{ + /* Get the Capture 4 Register value */ + return TIM1->CCR4; +} + +/******************************************************************************* +* Function Name : TIM1_GetCounter +* Description : Gets the TIM1 Counter value. +* Input : None +* Output : None +* Return : Counter Register value. +*******************************************************************************/ +u16 TIM1_GetCounter(void) +{ + /* Get the Counter Register value */ + return TIM1->CNT; +} + +/******************************************************************************* +* Function Name : TIM1_GetPrescaler +* Description : Gets the TIM1 Prescaler value. +* Input : None +* Output : None +* Return : Prescaler Register value. +*******************************************************************************/ +u16 TIM1_GetPrescaler(void) +{ + /* Get the Prescaler Register value */ + return TIM1->PSC; +} + +/******************************************************************************* +* Function Name : TIM1_GetFlagStatus +* Description : Checks whether the specified TIM1 flag is set or not. +* Input : - TIM1_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - TIM1_FLAG_Update: TIM1 update Flag +* - TIM1_FLAG_CC1: TIM1 Capture Compare 1 Flag +* - TIM1_FLAG_CC2: TIM1 Capture Compare 2 Flag +* - TIM1_FLAG_CC3: TIM1 Capture Compare 3 Flag +* - TIM1_FLAG_CC4: TIM1 Capture Compare 4 Flag +* - TIM1_FLAG_COM: TIM1 Commutation Flag +* - TIM1_FLAG_Trigger: TIM1 Trigger Flag +* - TIM1_FLAG_Break: TIM1 Break Flag +* - TIM1_FLAG_CC1OF: TIM1 Capture Compare 1 overcapture Flag +* - TIM1_FLAG_CC2OF: TIM1 Capture Compare 2 overcapture Flag +* - TIM1_FLAG_CC3OF: TIM1 Capture Compare 3 overcapture Flag +* - TIM1_FLAG_CC4OF: TIM1 Capture Compare 4 overcapture Flag +* Output : None +* Return : The new state of TIM1_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus TIM1_GetFlagStatus(u16 TIM1_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert(IS_TIM1_GET_FLAG(TIM1_FLAG)); + + if ((TIM1->SR & TIM1_FLAG) != (u16)RESET ) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : TIM1_ClearFlag +* Description : Clears the TIM1’s pending flags. +* Input : - TIM1_FLAG: specifies the flag to clear. +* This parameter can be any combination of the following values: +* - TIM1_FLAG_Update: TIM1 update Flag +* - TIM1_FLAG_CC1: TIM1 Capture Compare 1 Flag +* - TIM1_FLAG_CC2: TIM1 Capture Compare 2 Flag +* - TIM1_FLAG_CC3: TIM1 Capture Compare 3 Flag +* - TIM1_FLAG_CC4: TIM1 Capture Compare 4 Flag +* - TIM1_FLAG_COM: TIM1 Commutation Flag +* - TIM1_FLAG_Trigger: TIM1 Trigger Flag +* - TIM1_FLAG_Break: TIM1 Break Flag +* - TIM1_FLAG_CC1OF: TIM1 Capture Compare 1 overcapture Flag +* - TIM1_FLAG_CC2OF: TIM1 Capture Compare 2 overcapture Flag +* - TIM1_FLAG_CC3OF: TIM1 Capture Compare 3 overcapture Flag +* - TIM1_FLAG_CC4OF: TIM1 Capture Compare 4 overcapture Flag +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_ClearFlag(u16 TIM1_FLAG) +{ + /* Check the parameters */ + assert(IS_TIM1_CLEAR_FLAG(TIM1_FLAG)); + + /* Clear the flags */ + TIM1->SR &= (u16)~TIM1_FLAG; +} + +/******************************************************************************* +* Function Name : TIM1_GetITStatus +* Description : Checks whether the TIM1 interrupt has occurred or not. +* Input : - TIM1_IT: specifies the TIM1 interrupt source to check. +* This parameter can be one of the following values: +* - TIM1_IT_Update: TIM1 update Interrupt source +* - TIM1_IT_CC1: TIM1 Capture Compare 1 Interrupt source +* - TIM1_IT_CC2: TIM1 Capture Compare 2 Interrupt source +* - TIM1_IT_CC3: TIM1 Capture Compare 3 Interrupt source +* - TIM1_IT_CC4: TIM1 Capture Compare 4 Interrupt source +* - TIM1_IT_COM: TIM1 Commutation Interrupt +* source +* - TIM1_IT_Trigger: TIM1 Trigger Interrupt source +* - TIM1_IT_Break: TIM1 Break Interrupt source +* Output : None +* Return : The new state of the TIM1_IT(SET or RESET). +*******************************************************************************/ +ITStatus TIM1_GetITStatus(u16 TIM1_IT) +{ + ITStatus bitstatus = RESET; + + u16 TIM1_itStatus = 0x0, TIM1_itEnable = 0x0; + + /* Check the parameters */ + assert(IS_TIM1_GET_IT(TIM1_IT)); + + TIM1_itStatus = TIM1->SR & TIM1_IT; + + TIM1_itEnable = TIM1->DIER & TIM1_IT; + + if ((TIM1_itStatus != (u16)RESET ) && (TIM1_itEnable != (u16)RESET )) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : TIM1_ClearITPendingBit +* Description : Clears the TIM1's interrupt pending bits. +* Input : - TIM1_IT: specifies the pending bit to clear. +* This parameter can be any combination of the following values: +* - TIM1_IT_Update: TIM1 update Interrupt source +* - TIM1_IT_CC1: TIM1 Capture Compare 1 Interrupt source +* - TIM1_IT_CC2: TIM1 Capture Compare 2 Interrupt source +* - TIM1_IT_CC3: TIM1 Capture Compare 3 Interrupt source +* - TIM1_IT_CC4: TIM1 Capture Compare 4 Interrupt source +* - TIM1_IT_COM: TIM1 Commutation Interrupt +* source +* - TIM1_IT_Trigger: TIM1 Trigger Interrupt source +* - TIM1_IT_Break: TIM1 Break Interrupt source +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_ClearITPendingBit(u16 TIM1_IT) +{ + /* Check the parameters */ + assert(IS_TIM1_IT(TIM1_IT)); + + /* Clear the IT pending Bit */ + TIM1->SR &= (u16)~TIM1_IT; +} + +/******************************************************************************* +* Function Name : TI1_Config +* Description : Configure the TI1 as Input. +* Input : - TIM1_ICPolarity : The Input Polarity. +* This parameter can be one of the following values: +* - TIM1_ICPolarity_Rising +* - TIM1_ICPolarity_Falling +* - TIM1_ICSelection: specifies the input to be used. +* This parameter can be one of the following values: +* - TIM1_ICSelection_DirectTI: TIM1 Input 1 is selected to +* be connected to IC1. +* - TIM1_ICSelection_IndirectTI: TIM1 Input 1 is selected to +* be connected to IC2. +* - TIM1_ICSelection_TRGI:TIM1 Input 1 is selected to be +* connected to TRGI. +* - TIM1_ICFilter: Specifies the Input Capture Filter. +* This parameter must be a value between 0x00 and 0x0F. +* Output : None +* Return : None +*******************************************************************************/ +static void TI1_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection, + u8 TIM1_ICFilter) +{ + u32 tmpccmr1 = 0; + + tmpccmr1 = TIM1->CCMR1; + + /* Disable the Channel 1: Reset the CCE Bit */ + *(vu32 *) CCER_CC1E_BB = CCER_CCE_Reset; + + /* Select the Input and set the filter */ + tmpccmr1 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask; + tmpccmr1 |= (u16)TIM1_ICSelection | (u16)((u16)TIM1_ICFilter << 4); + + TIM1->CCMR1 = (u16)tmpccmr1; + + /* Select the Polarity */ + *(vu32 *) CCER_CC1P_BB = TIM1_ICPolarity; + + /* Set the CCE Bit */ + *(vu32 *) CCER_CC1E_BB = CCER_CCE_Set; +} + +/******************************************************************************* +* Function Name : TI2_Config +* Description : Configure the TI2 as Input. +* Input : - TIM1_ICPolarity : The Input Polarity. +* This parameter can be one of the following values: +* - TIM1_ICPolarity_Rising +* - TIM1_ICPolarity_Falling +* - TIM1_ICSelection: specifies the input to be used. +* This parameter can be one of the following values: +* - TIM1_ICSelection_DirectTI: TIM1 Input 2 is selected to +* be connected to IC2. +* - TIM1_ICSelection_IndirectTI: TIM1 Input 2 is selected to +* be connected to IC1. +* - TIM1_ICSelection_TRGI: TIM1 Input 2 is selected to be +* connected to TRGI. +* - TIM1_ICFilter: Specifies the Input Capture Filter. +* This parameter must be a value between 0x00 and 0x0F. +* Output : None +* Return : None +*******************************************************************************/ +static void TI2_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection, + u8 TIM1_ICFilter) +{ + u32 tmpccmr1 = 0; + + tmpccmr1 = TIM1->CCMR1; + + /* Disable the Channel 2: Reset the CCE Bit */ + *(vu32 *) CCER_CC2E_BB = CCER_CCE_Reset; + + /* Select the Input and set the filter */ + tmpccmr1 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask; + tmpccmr1 |= (u16)((u16)TIM1_ICSelection << 8) | (u16)((u16)TIM1_ICFilter <<12); + + TIM1->CCMR1 = (u16)tmpccmr1; + + /* Select the Polarity */ + *(vu32 *) CCER_CC2P_BB = TIM1_ICPolarity; + + /* Set the CCE Bit */ + *(vu32 *) CCER_CC2E_BB = CCER_CCE_Set; + +} + +/******************************************************************************* +* Function Name : TI3_Config +* Description : Configure the TI3 as Input. +* Input : - TIM1_ICPolarity : The Input Polarity. +* This parameter can be one of the following values: +* - TIM1_ICPolarity_Rising +* - TIM1_ICPolarity_Falling +* - TIM1_ICSelection: specifies the input to be used. +* This parameter can be one of the following values: +* - TIM1_ICSelection_DirectTI: TIM1 Input 3 is selected to +* be connected to IC3. +* - TIM1_ICSelection_IndirectTI: TIM1 Input 3 is selected to +* be connected to IC4. +* - TIM1_ICSelection_TRGI: TIM1 Input 3 is selected to be +* connected to TRGI. +* - TIM1_ICFilter: Specifies the Input Capture Filter. +* This parameter must be a value between 0x00 and 0x0F. +* Output : None +* Return : None +*******************************************************************************/ +static void TI3_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection, + u8 TIM1_ICFilter) +{ + u32 tmpccmr2 = 0; + + tmpccmr2 = TIM1->CCMR2; + + /* Disable the Channel 3: Reset the CCE Bit */ + *(vu32 *) CCER_CC3E_BB = CCER_CCE_Reset; + + /* Select the Input and set the filter */ + tmpccmr2 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask; + tmpccmr2 |= (u16)TIM1_ICSelection | (u16)((u16)TIM1_ICFilter << 4); + + TIM1->CCMR2 = (u16)tmpccmr2; + + /* Select the Polarity */ + *(vu32 *) CCER_CC3P_BB = TIM1_ICPolarity; + + /* Set the CCE Bit */ + *(vu32 *) CCER_CC3E_BB = CCER_CCE_Set; +} + +/******************************************************************************* +* Function Name : TI4_Config +* Description : Configure the TI4 as Input. +* Input : - TIM1_ICPolarity : The Input Polarity. +* This parameter can be one of the following values: +* - TIM1_ICPolarity_Rising +* - TIM1_ICPolarity_Falling +* - TIM1_ICSelection: specifies the input to be used. +* This parameter can be one of the following values: +* - TIM1_ICSelection_DirectTI: TIM1 Input 4 is selected to +* be connected to IC4. +* - TIM1_ICSelection_IndirectTI: TIM1 Input 4 is selected to +* be connected to IC3. +* - TIM1_ICSelection_TRGI: TIM1 Input 4 is selected to be +* connected to TRGI. +* - TIM1_ICFilter: Specifies the Input Capture Filter. +* This parameter must be a value between 0x00 and 0x0F. +* Output : None +* Return : None +*******************************************************************************/ +static void TI4_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection, + u8 TIM1_ICFilter) +{ + u32 tmpccmr2 = 0; + + tmpccmr2 = TIM1->CCMR2; + + /* Disable the Channel 4: Reset the CCE Bit */ + *(vu32 *) CCER_CC4E_BB = CCER_CCE_Reset; + + /* Select the Input and set the filter */ + tmpccmr2 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask; + tmpccmr2 |= (u16)((u16)TIM1_ICSelection << 8) | (u16)((u16)TIM1_ICFilter << 12); + + TIM1->CCMR2 = (u16)tmpccmr2; + + /* Select the Polarity */ + *(vu32 *) CCER_CC4P_BB = TIM1_ICPolarity; + + /* Set the CCE Bit */ + *(vu32 *) CCER_CC4E_BB = CCER_CCE_Set; +} + +/******************************************************************************* +* Function Name : ETR_Config +* Description : Configure the External Trigger +* Input : - TIM1_ExtTRGPrescaler: The external Trigger Prescaler. +* This parameter can be one of the following values: +* - TIM1_ExtTRGPSC_OFF +* - TIM1_ExtTRGPSC_DIV2 +* - TIM1_ExtTRGPSC_DIV4 +* - TIM1_ExtTRGPSC_DIV8 +* - TIM1_ExtTRGPolarity: The external Trigger Polarity. +* This parameter can be one of the following values: +* - TIM1_ExtTRGPolarity_Inverted +* - TIM1_ExtTRGPolarity_NonInverted +* - ExtTRGFilter: External Trigger Filter. +* This parameter must be a value between 0x00 and 0x0F. +* Output : None +* Return : None +*******************************************************************************/ +static void ETR_Config(u16 TIM1_ExtTRGPrescaler, u16 TIM1_ExtTRGPolarity, + u16 ExtTRGFilter) +{ + u32 tmpsmcr = 0; + + tmpsmcr = TIM1->SMCR; + + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr &= SMCR_ETR_Mask; + tmpsmcr |= TIM1_ExtTRGPrescaler | TIM1_ExtTRGPolarity | (u16)((u16)ExtTRGFilter << 8); + + TIM1->SMCR = (u16)tmpsmcr; +} + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_usart.c b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_usart.c new file mode 100644 index 000000000..7bc288acb --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_usart.c @@ -0,0 +1,852 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_usart.c +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file provides all the USART firmware functions. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_usart.h" +#include "stm32f10x_rcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* USART RUN Mask */ +#define CR1_RUN_Set ((u16)0x2000) /* USART Enable Mask */ +#define CR1_RUN_Reset ((u16)0xDFFF) /* USART Disable Mask */ + +#define CR2_Address_Mask ((u16)0xFFF0) /* USART address Mask */ + +/* USART RWU Mask */ +#define CR1_RWU_Set ((u16)0x0002) /* USART mute mode Enable Mask */ +#define CR1_RWU_Reset ((u16)0xFFFD) /* USART mute mode Enable Mask */ + +#define USART_IT_Mask ((u16)0x001F) /* USART Interrupt Mask */ + +/* USART LIN Mask */ +#define CR2_LINE_Set ((u16)0x4000) /* USART LIN Enable Mask */ +#define CR2_LINE_Reset ((u16)0xBFFF) /* USART LIN Disable Mask */ + +#define CR1_SBK_Set ((u16)0x0001) /* USART Break Character send Mask */ + +/* USART SC Mask */ +#define CR3_SCEN_Set ((u16)0x0020) /* USART SC Enable Mask */ +#define CR3_SCEN_Reset ((u16)0xFFDF) /* USART SC Disable Mask */ + +/* USART SC NACK Mask */ +#define CR3_NACK_Set ((u16)0x0010) /* USART SC NACK Enable Mask */ +#define CR3_NACK_Reset ((u16)0xFFEF) /* USART SC NACK Disable Mask */ + +/* USART Half-Duplex Mask */ +#define CR3_HDSEL_Set ((u16)0x0008) /* USART Half-Duplex Enable Mask */ +#define CR3_HDSEL_Reset ((u16)0xFFF7) /* USART Half-Duplex Disable Mask */ + +/* USART IrDA Mask */ +#define CR3_IRLP_Mask ((u16)0xFFFB) /* USART IrDA LowPower mode Mask */ + +/* USART LIN Break detection */ +#define CR3_LBDL_Mask ((u16)0xFFDF) /* USART LIN Break detection Mask */ + +/* USART WakeUp Method */ +#define CR3_WAKE_Mask ((u16)0xF7FF) /* USART WakeUp Method Mask */ + +/* USART IrDA Mask */ +#define CR3_IREN_Set ((u16)0x0002) /* USART IrDA Enable Mask */ +#define CR3_IREN_Reset ((u16)0xFFFD) /* USART IrDA Disable Mask */ + +#define GTPR_LSB_Mask ((u16)0x00FF) /* Guard Time Register LSB Mask */ +#define GTPR_MSB_Mask ((u16)0xFF00) /* Guard Time Register MSB Mask */ + +#define CR1_CLEAR_Mask ((u16)0xE9F3) /* USART CR1 Mask */ +#define CR2_CLEAR_Mask ((u16)0xC0FF) /* USART CR2 Mask */ +#define CR3_CLEAR_Mask ((u16)0xFCFF) /* USART CR3 Mask */ + + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : USART_DeInit +* Description : Deinitializes the USARTx peripheral registers to their +* default reset values. +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void USART_DeInit(USART_TypeDef* USARTx) +{ + switch (*(u32*)&USARTx) + { + case USART1_BASE: + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); + break; + + case USART2_BASE: + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); + break; + + case USART3_BASE: + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : USART_Init +* Description : Initializes the USARTx peripheral according to the specified +* parameters in the USART_InitStruct . +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART peripheral. +* - USART_InitStruct: pointer to a USART_InitTypeDef structure +* that contains the configuration information for the +* specified USART peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct) +{ + u32 tmpreg = 0x00, apbclock = 0x00; + u32 integerdivider = 0x00; + u32 fractionaldivider = 0x00; + RCC_ClocksTypeDef RCC_ClocksStatus; + + /* Check the parameters */ + assert(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength)); + assert(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits)); + assert(IS_USART_PARITY(USART_InitStruct->USART_Parity)); + assert(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl)); + assert(IS_USART_MODE(USART_InitStruct->USART_Mode)); + assert(IS_USART_CLOCK(USART_InitStruct->USART_Clock)); + assert(IS_USART_CPOL(USART_InitStruct->USART_CPOL)); + assert(IS_USART_CPHA(USART_InitStruct->USART_CPHA)); + assert(IS_USART_LASTBIT(USART_InitStruct->USART_LastBit)); + +/*---------------------------- USART CR2 Configuration -----------------------*/ + tmpreg = USARTx->CR2; + /* Clear STOP[13:12], CLKEN, CPOL, CPHA and LBCL bits */ + tmpreg &= CR2_CLEAR_Mask; + + /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/ + /* Set STOP[13:12] bits according to USART_Mode value */ + /* Set CPOL bit according to USART_CPOL value */ + /* Set CPHA bit according to USART_CPHA value */ + /* Set LBCL bit according to USART_LastBit value */ + tmpreg |= (u32)USART_InitStruct->USART_StopBits | USART_InitStruct->USART_Clock | + USART_InitStruct->USART_CPOL | USART_InitStruct->USART_CPHA | + USART_InitStruct->USART_LastBit; + + /* Write to USART CR2 */ + USARTx->CR2 = (u16)tmpreg; + +/*---------------------------- USART CR1 Configuration -----------------------*/ + tmpreg = 0x00; + tmpreg = USARTx->CR1; + /* Clear M, PCE, PS, TE and RE bits */ + tmpreg &= CR1_CLEAR_Mask; + + /* Configure the USART Word Length, Parity and mode ----------------------- */ + /* Set the M bits according to USART_WordLength value */ + /* Set PCE and PS bits according to USART_Parity value */ + /* Set TE and RE bits according to USART_Mode value */ + tmpreg |= (u32)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | + USART_InitStruct->USART_Mode; + + /* Write to USART CR1 */ + USARTx->CR1 = (u16)tmpreg; + +/*---------------------------- USART CR3 Configuration -----------------------*/ + tmpreg = 0x00; + tmpreg = USARTx->CR3; + /* Clear CTSE and RTSE bits */ + tmpreg &= CR3_CLEAR_Mask; + + /* Configure the USART HFC -------------------------------------------------*/ + /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */ + tmpreg |= USART_InitStruct->USART_HardwareFlowControl; + + /* Write to USART CR3 */ + USARTx->CR3 = (u16)tmpreg; + +/*---------------------------- USART BRR Configuration -----------------------*/ + tmpreg = 0x00; + + /* Configure the USART Baud Rate -------------------------------------------*/ + RCC_GetClocksFreq(&RCC_ClocksStatus); + if ((*(u32*)&USARTx) == USART1_BASE) + { + apbclock = RCC_ClocksStatus.PCLK2_Frequency; + } + else + { + apbclock = RCC_ClocksStatus.PCLK1_Frequency; + } + + /* Determine the integer part */ + integerdivider = ((0x19 * apbclock) / (0x04 * (USART_InitStruct->USART_BaudRate))); + tmpreg = (integerdivider / 0x64) << 0x04; + + /* Determine the fractional part */ + fractionaldivider = integerdivider - (0x64 * (tmpreg >> 0x04)); + tmpreg |= ((((fractionaldivider * 0x10) + 0x32) / 0x64)) & ((u8)0x0F); + + /* Write to USART BRR */ + USARTx->BRR = (u16)tmpreg; +} + +/******************************************************************************* +* Function Name : USART_StructInit +* Description : Fills each USART_InitStruct member with its default value. +* Input : - USART_InitStruct: pointer to a USART_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void USART_StructInit(USART_InitTypeDef* USART_InitStruct) +{ + /* USART_InitStruct members default value */ + USART_InitStruct->USART_BaudRate = 0x2580; /* 9600 Baud */ + USART_InitStruct->USART_WordLength = USART_WordLength_8b; + USART_InitStruct->USART_StopBits = USART_StopBits_1; + USART_InitStruct->USART_Parity = USART_Parity_No ; + USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_InitStruct->USART_Clock = USART_Clock_Disable; + USART_InitStruct->USART_CPOL = USART_CPOL_Low; + USART_InitStruct->USART_CPHA = USART_CPHA_1Edge; + USART_InitStruct->USART_LastBit = USART_LastBit_Disable; +} + +/******************************************************************************* +* Function Name : USART_Cmd +* Description : Enables or disables the specified USART peripheral. +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART +* peripheral. +* : - NewState: new state of the USARTx peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected USART by setting the RUN bit in the CR1 register */ + USARTx->CR1 |= CR1_RUN_Set; + } + else + { + /* Disable the selected USART by clearing the RUN bit in the CR1 register */ + USARTx->CR1 &= CR1_RUN_Reset; + } +} + +/******************************************************************************* +* Function Name : USART_ITConfig +* Description : Enables or disables the specified USART interrupts. +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART +* peripheral. +* - USART_IT: specifies the USART interrupt sources to be +* enabled or disabled. +* This parameter can be one of the following values: +* - USART_IT_PE +* - USART_IT_TXE +* - USART_IT_TC +* - USART_IT_RXNE +* - USART_IT_IDLE +* - USART_IT_LBD +* - USART_IT_CTS +* - USART_IT_ERR +* - NewState: new state of the specified USARTx interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void USART_ITConfig(USART_TypeDef* USARTx, u16 USART_IT, FunctionalState NewState) +{ + u32 usartreg = 0x00, itpos = 0x00, itmask = 0x00; + u32 address = 0x00; + + /* Check the parameters */ + assert(IS_USART_CONFIG_IT(USART_IT)); + assert(IS_FUNCTIONAL_STATE(NewState)); + + /* Get the USART register index */ + usartreg = (((u8)USART_IT) >> 0x05); + + /* Get the interrupt position */ + itpos = USART_IT & USART_IT_Mask; + + itmask = (((u32)0x01) << itpos); + address = *(u32*)&(USARTx); + + if (usartreg == 0x01) /* The IT is in CR1 register */ + { + address += 0x0C; + } + else if (usartreg == 0x02) /* The IT is in CR2 register */ + { + address += 0x10; + } + else /* The IT is in CR3 register */ + { + address += 0x14; + } + if (NewState != DISABLE) + { + *(u32*)address |= itmask; + } + else + { + *(u32*)address &= ~itmask; + } +} + +/******************************************************************************* +* Function Name : USART_DMACmd +* Description : Enables or disables the USART’s DMA interface. +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART +* peripheral. +* - USART_DMAReq: specifies the DMA request. +* This parameter can be any combination of the following values: +* - USART_DMAReq_Tx +* - USART_DMAReq_Rx +* - NewState: new state of the DMA Request sources. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void USART_DMACmd(USART_TypeDef* USARTx, u16 USART_DMAReq, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_USART_DMAREQ(USART_DMAReq)); + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA transfer for selected requests by setting the DMAT and/or + DMAR bits in the USART CR3 register */ + USARTx->CR3 |= USART_DMAReq; + } + else + { + /* Disable the DMA transfer for selected requests by clearing the DMAT and/or + DMAR bits in the USART CR3 register */ + USARTx->CR3 &= (u16)~USART_DMAReq; + } +} + +/******************************************************************************* +* Function Name : USART_SetAddress +* Description : Sets the address of the USART node. +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART +* peripheral. +* - USART_Address: Indicates the address of the USART node. +* Output : None +* Return : None +*******************************************************************************/ +void USART_SetAddress(USART_TypeDef* USARTx, u8 USART_Address) +{ + /* Check the parameters */ + assert(IS_USART_ADDRESS(USART_Address)); + + /* Clear the USART address */ + USARTx->CR2 &= CR2_Address_Mask; + /* Set the USART address node */ + USARTx->CR2 |= USART_Address; +} + +/******************************************************************************* +* Function Name : USART_WakeUpConfig +* Description : Selects the USART WakeUp method. +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART +* peripheral. +* - USART_WakeUp: specifies the USART wakeup method. +* This parameter can be one of the following values: +* - USART_WakeUp_IdleLine +* - USART_WakeUp_AddressMark +* Output : None +* Return : None +*******************************************************************************/ +void USART_WakeUpConfig(USART_TypeDef* USARTx, u16 USART_WakeUp) +{ + /* Check the parameters */ + assert(IS_USART_WAKEUP(USART_WakeUp)); + + USARTx->CR1 &= CR3_WAKE_Mask; + USARTx->CR1 |= USART_WakeUp; +} + +/******************************************************************************* +* Function Name : USART_ReceiverWakeUpCmd +* Description : Determines if the USART is in mute mode or not. +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART +* peripheral. +* - NewState: new state of the USART mode. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the mute mode USART by setting the RWU bit in the CR1 register */ + USARTx->CR1 |= CR1_RWU_Set; + } + else + { + /* Disable the mute mode USART by clearing the RWU bit in the CR1 register */ + USARTx->CR1 &= CR1_RWU_Reset; + } +} + +/******************************************************************************* +* Function Name : USART_LINBreakDetectLengthConfig +* Description : Sets the USART LIN Break detection length. +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART +* peripheral. +* - USART_LINBreakDetectLength: specifies the LIN break +* detection length. +* This parameter can be one of the following values: +* - USART_LINBreakDetectLength_10b +* - USART_LINBreakDetectLength_11b +* Output : None +* Return : None +*******************************************************************************/ +void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, u16 USART_LINBreakDetectLength) +{ + /* Check the parameters */ + assert(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength)); + + USARTx->CR2 &= CR3_LBDL_Mask; + USARTx->CR2 |= USART_LINBreakDetectLength; +} + +/******************************************************************************* +* Function Name : USART_LINCmd +* Description : Enables or disables the USART’s LIN mode. +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART +* peripheral. +* - NewState: new state of the USART LIN mode. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the LIN mode by setting the LINE bit in the CR2 register */ + USARTx->CR2 |= CR2_LINE_Set; + } + else + { + /* Disable the LIN mode by clearing the LINE bit in the CR2 register */ + USARTx->CR2 &= CR2_LINE_Reset; + } +} + +/******************************************************************************* +* Function Name : USART_SendData +* Description : Transmits signle data through the USARTx peripheral. +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART +* peripheral. +* - Data: the data to transmit. +* Output : None +* Return : None +*******************************************************************************/ +void USART_SendData(USART_TypeDef* USARTx, u16 Data) +{ + /* Check the parameters */ + assert(IS_USART_DATA(Data)); + + /* Transmit Data */ + USARTx->DR = (Data & (u16)0x01FF); +} + +/******************************************************************************* +* Function Name : USART_ReceiveData +* Description : Returns the most recent received data by the USARTx peripheral. +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART +* peripheral. +* Output : None +* Return : The received data. +*******************************************************************************/ +u16 USART_ReceiveData(USART_TypeDef* USARTx) +{ + /* Receive Data */ + return (u16)(USARTx->DR & (u16)0x01FF); +} + +/******************************************************************************* +* Function Name : USART_SendBreak +* Description : Transmits break characters. +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void USART_SendBreak(USART_TypeDef* USARTx) +{ + /* Send break characters */ + USARTx->CR1 |= CR1_SBK_Set; +} + +/******************************************************************************* +* Function Name : USART_SetGuardTime +* Description : Sets the specified USART guard time. +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART +* peripheral. +* - USART_GuardTime: specifies the guard time. +* Output : None +* Return : None +*******************************************************************************/ +void USART_SetGuardTime(USART_TypeDef* USARTx, u8 USART_GuardTime) +{ + /* Clear the USART Guard time */ + USARTx->GTPR &= GTPR_LSB_Mask; + /* Set the USART guard time */ + USARTx->GTPR |= (u16)((u16)USART_GuardTime << 0x08); +} + +/******************************************************************************* +* Function Name : USART_SetPrescaler +* Description : Sets the system clock prescaler. +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART +* peripheral. +* - USART_Prescaler: specifies the prescaler clock. +* Output : None +* Return : None +*******************************************************************************/ +void USART_SetPrescaler(USART_TypeDef* USARTx, u8 USART_Prescaler) +{ + /* Clear the USART prescaler */ + USARTx->GTPR &= GTPR_MSB_Mask; + /* Set the USART prescaler */ + USARTx->GTPR |= USART_Prescaler; +} + +/******************************************************************************* +* Function Name : USART_SmartCardCmd +* Description : Enables or disables the USART’s Smart Card mode. +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART +* peripheral. +* - NewState: new state of the Smart Card mode. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the SC mode by setting the SCEN bit in the CR3 register */ + USARTx->CR3 |= CR3_SCEN_Set; + } + else + { + /* Disable the SC mode by clearing the SCEN bit in the CR3 register */ + USARTx->CR3 &= CR3_SCEN_Reset; + } +} + +/******************************************************************************* +* Function Name : USART_SmartCardNACKCmd +* Description : Enables or disables NACK transmission. +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART +* peripheral. +* - NewState: new state of the NACK transmission. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the NACK transmission by setting the NACK bit in the CR3 register */ + USARTx->CR3 |= CR3_NACK_Set; + } + else + { + /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */ + USARTx->CR3 &= CR3_NACK_Reset; + } + +} + +/******************************************************************************* +* Function Name : USART_HalfDuplexCmd +* Description : Enables or disables the USART’s Half Duplex communication. +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART +* peripheral. +* - NewState: new state of the USART Communication. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ + USARTx->CR3 |= CR3_HDSEL_Set; + } + else + { + /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */ + USARTx->CR3 &= CR3_HDSEL_Reset; + } +} + +/******************************************************************************* +* Function Name : USART_IrDAConfig +* Description : Configures the USART’s IrDA interface. +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART +* peripheral. +* - USART_IrDAMode: specifies the IrDA mode. +* This parameter can be one of the following values: +* - USART_IrDAMode_LowPower +* - USART_IrDAMode_Normal +* Output : None +* Return : None +*******************************************************************************/ +void USART_IrDAConfig(USART_TypeDef* USARTx, u16 USART_IrDAMode) +{ + /* Check the parameters */ + assert(IS_USART_IRDA_MODE(USART_IrDAMode)); + + USARTx->CR3 &= CR3_IRLP_Mask; + USARTx->CR3 |= USART_IrDAMode; +} + +/******************************************************************************* +* Function Name : USART_IrDACmd +* Description : Enables or disables the USART’s IrDA interface. +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART +* peripheral. +* - NewState: new state of the IrDA mode. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the IrDA mode by setting the IREN bit in the CR3 register */ + USARTx->CR3 |= CR3_IREN_Set; + } + else + { + /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */ + USARTx->CR3 &= CR3_IREN_Reset; + } +} + +/******************************************************************************* +* Function Name : USART_GetFlagStatus +* Description : Checks whether the specified USART flag is set or not. +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART +* peripheral. +* - USART_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - USART_FLAG_CTS +* - USART_FLAG_LBD +* - USART_FLAG_TXE +* - USART_FLAG_TC +* - USART_FLAG_RXNE +* - USART_FLAG_IDLE +* - USART_FLAG_ORE +* - USART_FLAG_NE +* - USART_FLAG_FE +* - USART_FLAG_PE +* Output : None +* Return : The new state of USART_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, u16 USART_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert(IS_USART_FLAG(USART_FLAG)); + + if ((USARTx->SR & USART_FLAG) != (u16)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : USART_ClearFlag +* Description : Clears the USARTx's pending flags. +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART +* peripheral. +* - USART_FLAG: specifies the flag to clear. +* This parameter can be any combination of the following values: +* - USART_FLAG_CTS +* - USART_FLAG_LBD +* - USART_FLAG_TXE +* - USART_FLAG_TC +* - USART_FLAG_RXNE +* - USART_FLAG_IDLE +* - USART_FLAG_ORE +* - USART_FLAG_NE +* - USART_FLAG_FE +* - USART_FLAG_PE +* Output : None +* Return : None +*******************************************************************************/ +void USART_ClearFlag(USART_TypeDef* USARTx, u16 USART_FLAG) +{ + /* Check the parameters */ + assert(IS_USART_CLEAR_FLAG(USART_FLAG)); + + USARTx->SR &= (u16)~USART_FLAG; +} + +/******************************************************************************* +* Function Name : USART_GetITStatus +* Description : Checks whether the specified USART interrupt has occurred or not. +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART +* peripheral. +* - USART_IT: specifies the USART interrupt source to check. +* This parameter can be one of the following values: +* - USART_IT_PE +* - USART_IT_TXE +* - USART_IT_TC +* - USART_IT_RXNE +* - USART_IT_IDLE +* - USART_IT_LBD +* - USART_IT_CTS +* - USART_IT_ORE +* - USART_IT_NE +* - USART_IT_FE +* Output : None +* Return : The new state of USART_IT (SET or RESET). +*******************************************************************************/ +ITStatus USART_GetITStatus(USART_TypeDef* USARTx, u16 USART_IT) +{ + u32 bitpos = 0x00, itmask = 0x00, usartreg = 0; + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert(IS_USART_IT(USART_IT)); + + /* Get the USART register index */ + usartreg = (((u8)USART_IT) >> 0x05); + + /* Get the interrupt position */ + itmask = USART_IT & USART_IT_Mask; + + itmask = (u32)0x01 << itmask; + + if (usartreg == 0x01) /* The IT is in CR1 register */ + { + itmask &= USARTx->CR1; + } + else if (usartreg == 0x02) /* The IT is in CR2 register */ + { + itmask &= USARTx->CR2; + } + else /* The IT is in CR3 register */ + { + itmask &= USARTx->CR3; + } + + bitpos = USART_IT >> 0x08; + + bitpos = (u32)0x01 << bitpos; + bitpos &= USARTx->SR; + + if ((itmask != (u16)RESET)&&(bitpos != (u16)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : USART_ClearITPendingBit +* Description : Clears the USARTx’s interrupt pending bits. +* Input : - USARTx: where x can be 1, 2 or 3 to select the USART +* peripheral. +* - USART_IT: specifies the interrupt pending bit to clear. +* This parameter can be one of the following values: +* - USART_IT_PE +* - USART_IT_TXE +* - USART_IT_TC +* - USART_IT_RXNE +* - USART_IT_IDLE +* - USART_IT_LBD +* - USART_IT_CTS +* - USART_IT_ORE +* - USART_IT_NE +* - USART_IT_FE +* Output : None +* Return : None +*******************************************************************************/ +void USART_ClearITPendingBit(USART_TypeDef* USARTx, u16 USART_IT) +{ + u32 bitpos = 0x00, itmask = 0x00; + + /* Check the parameters */ + assert(IS_USART_IT(USART_IT)); + + bitpos = USART_IT >> 0x08; + + itmask = (u32)0x01 << bitpos; + USARTx->SR &= ~itmask; +} + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_wwdg.c b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_wwdg.c new file mode 100644 index 000000000..e1cb58d5b --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/stm32f10x_wwdg.c @@ -0,0 +1,194 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_wwdg.c +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file provides all the WWDG firmware functions. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_wwdg.h" +#include "stm32f10x_rcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* ----------- WWDG registers bit address in the alias region ----------- */ +#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE) + +/* Alias word address of EWI bit */ +#define CFR_OFFSET (WWDG_OFFSET + 0x04) +#define EWI_BitNumber 0x09 +#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4)) + +/* Alias word address of EWIF bit */ +#define SR_OFFSET (WWDG_OFFSET + 0x08) +#define EWIF_BitNumber 0x00 +#define SR_EWIF_BB (PERIPH_BB_BASE + (SR_OFFSET * 32) + (EWIF_BitNumber * 4)) + +/* --------------------- WWDG registers bit mask ------------------------ */ +/* CR register bit mask */ +#define CR_WDGA_Set ((u32)0x00000080) + +/* CFR register bit mask */ +#define CFR_WDGTB_Mask ((u32)0xFFFFFE7F) +#define CFR_W_Mask ((u32)0xFFFFFF80) + +#define BIT_Mask ((u8)0x7F) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : WWDG_DeInit +* Description : Deinitializes the WWDG peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void WWDG_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); +} + +/******************************************************************************* +* Function Name : WWDG_SetPrescaler +* Description : Sets the WWDG Prescaler. +* Input : - WWDG_Prescaler: specifies the WWDG Prescaler. +* This parameter can be one of the following values: +* - WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1 +* - WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2 +* - WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4 +* - WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8 +* Output : None +* Return : None +*******************************************************************************/ +void WWDG_SetPrescaler(u32 WWDG_Prescaler) +{ + u32 tmpreg = 0; + + /* Check the parameters */ + assert(IS_WWDG_PRESCALER(WWDG_Prescaler)); + + /* Clear WDGTB[8:7] bits */ + tmpreg = WWDG->CFR & CFR_WDGTB_Mask; + + /* Set WDGTB[8:7] bits according to WWDG_Prescaler value */ + tmpreg |= WWDG_Prescaler; + + /* Store the new value */ + WWDG->CFR = tmpreg; +} + +/******************************************************************************* +* Function Name : WWDG_SetWindowValue +* Description : Sets the WWDG window value. +* Input : - WindowValue: specifies the window value to be compared to +* the downcounter. +* This parameter value must be lower than 0x80. +* Output : None +* Return : None +*******************************************************************************/ +void WWDG_SetWindowValue(u8 WindowValue) +{ + u32 tmpreg = 0; + + /* Check the parameters */ + assert(IS_WWDG_WINDOW_VALUE(WindowValue)); + + /* Clear W[6:0] bits */ + tmpreg = WWDG->CFR & CFR_W_Mask; + + /* Set W[6:0] bits according to WindowValue value */ + tmpreg |= WindowValue & BIT_Mask; + + /* Store the new value */ + WWDG->CFR = tmpreg; +} + +/******************************************************************************* +* Function Name : WWDG_EnableIT +* Description : Enables the WWDG Early Wakeup interrupt(EWI). +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void WWDG_EnableIT(void) +{ + *(vu32 *) CFR_EWI_BB = (u32)ENABLE; +} + +/******************************************************************************* +* Function Name : WWDG_SetCounter +* Description : Sets the WWDG counter value. +* Input : - Counter: specifies the watchdog counter value. +* This parameter must be a number between 0x40 and 0x7F. +* Output : None +* Return : None +*******************************************************************************/ +void WWDG_SetCounter(u8 Counter) +{ + /* Check the parameters */ + assert(IS_WWDG_COUNTER(Counter)); + + /* Write to T[6:0] bits to configure the counter value, no need to do + a read-modify-write; writing a 0 to WDGA bit does nothing */ + WWDG->CR = Counter & BIT_Mask; +} + +/******************************************************************************* +* Function Name : WWDG_Enable +* Description : Enables WWDG and load the counter value. +* - Counter: specifies the watchdog counter value. +* This parameter must be a number between 0x40 and 0x7F. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void WWDG_Enable(u8 Counter) +{ + /* Check the parameters */ + assert(IS_WWDG_COUNTER(Counter)); + + WWDG->CR = CR_WDGA_Set | Counter; +} + +/******************************************************************************* +* Function Name : WWDG_GetFlagStatus +* Description : Checks whether the Early Wakeup interrupt flag is set or not. +* Input : None +* Output : None +* Return : The new state of the Early Wakeup interrupt flag (SET or RESET) +*******************************************************************************/ +FlagStatus WWDG_GetFlagStatus(void) +{ + return (FlagStatus)(*(vu32 *) SR_EWIF_BB); +} + +/******************************************************************************* +* Function Name : WWDG_ClearFlag +* Description : Clears Early Wakeup interrupt flag. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void WWDG_ClearFlag(void) +{ + WWDG->SR = (u32)RESET; +} + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/version.txt b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/version.txt new file mode 100644 index 000000000..72d300199 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/version.txt @@ -0,0 +1,22 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : version.txt +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : Version file for STM32F10x Firmware Library. +******************************************************************************** + +* 04/02/2007: V0.2 +=================== + Updated version + +* 02/05/2007 : V0.1 +=================== + Updated version + +* 09/29/2006 : V0.01 +=================== + Created. + +******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****** + + diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10x_FLASH.icf b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10x_FLASH.icf new file mode 100644 index 000000000..2f38805ab --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/STM32F10x_FLASH.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x080000EC; +define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20004FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x4; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/main.c b/20080212/Demo/CORTEX_STM32F103_IAR/main.c new file mode 100644 index 000000000..4a7358f12 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/main.c @@ -0,0 +1,449 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + * Creates all the demo application tasks, then starts the scheduler. The WEB + * documentation provides more details of the standard demo application tasks. + * In addition to the standard demo tasks, the following tasks and tests are + * defined and/or created within this file: + * + * "Fast Interrupt Test" - A high frequency periodic interrupt is generated + * using a free running timer to demonstrate the use of the + * configKERNEL_INTERRUPT_PRIORITY configuration constant. The interrupt + * service routine measures the number of processor clocks that occur between + * each interrupt - and in so doing measures the jitter in the interrupt timing. + * The maximum measured jitter time is latched in the ulMaxJitter variable, and + * displayed on the LCD by the 'Check' task as described below. The + * fast interrupt is configured and handled in the timertest.c source file. + * + * "LCD" task - the LCD task is a 'gatekeeper' task. It is the only task that + * is permitted to access the display directly. Other tasks wishing to write a + * message to the LCD send the message on a queue to the LCD task instead of + * accessing the LCD themselves. The LCD task just blocks on the queue waiting + * for messages - waking and displaying the messages as they arrive. + * + * "Check" task - This only executes every five seconds but has the highest + * priority so is guaranteed to get processor time. Its main function is to + * check that all the standard demo tasks are still operational. Should any + * unexpected behaviour within a demo task be discovered the 'check' task will + * write an error to the LCD (via the LCD task). If all the demo tasks are + * executing with their expected behaviour then the check task writes PASS + * along with the max jitter time to the LCD (again via the LCD task), as + * described above. + * + */ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "Task.h" +#include "Queue.h" + +/* Library includes. */ +#include "stm32f10x_it.h" + +/* Demo app includes. */ +#include "lcd.h" +#include "LCD_Message.h" +#include "BlockQ.h" +#include "death.h" +#include "integer.h" +#include "blocktim.h" +#include "partest.h" +#include "semtest.h" +#include "pollq.h" +#include "flash.h" +#include "comtest2.h" + +/* Task priorities. */ +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainFLASH_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainINTEGER_TASK_PRIORITY ( tskIDLE_PRIORITY ) + +/* Constants related to the LCD. */ +#define mainMAX_LINE ( 240 ) +#define mainROW_INCREMENT ( 24 ) +#define mainMAX_COLUMN ( 20 ) +#define mainCOLUMN_START ( 319 ) +#define mainCOLUMN_INCREMENT ( 16 ) + +/* The maximum number of message that can be waiting for display at any one +time. */ +#define mainLCD_QUEUE_SIZE ( 3 ) + +/* The check task uses the sprintf function so requires a little more stack. */ +#define mainCHECK_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE + 50 ) + +/* Dimensions the buffer into which the jitter time is written. */ +#define mainMAX_MSG_LEN 25 + +/* The time between cycles of the 'check' task. */ +#define mainCHECK_DELAY ( ( portTickType ) 5000 / portTICK_RATE_MS ) + +/* The number of nano seconds between each processor clock. */ +#define mainNS_PER_CLOCK ( ( unsigned portLONG ) ( ( 1.0 / ( double ) configCPU_CLOCK_HZ ) * 1000000000.0 ) ) + +/* Baud rate used by the comtest tasks. */ +#define mainCOM_TEST_BAUD_RATE ( 115200 ) + +/* The LED used by the comtest tasks. See the comtest.c file for more +information. */ +#define mainCOM_TEST_LED ( 3 ) + +/*-----------------------------------------------------------*/ + +/* + * Configure the clocks, GPIO and other peripherals as required by the demo. + */ +static void prvSetupHardware( void ); + +/* + * Configure the LCD as required by the demo. + */ +static void prvConfigureLCD( void ); + +/* + * The LCD is written two by more than one task so is controlled by a + * 'gatekeeper' task. This is the only task that is actually permitted to + * access the LCD directly. Other tasks wanting to display a message send + * the message to the gatekeeper. + */ +static void vLCDTask( void *pvParameters ); + +/* + * Retargets the C library printf function to the USART. + */ +int fputc( int ch, FILE *f ); + +/* + * Checks the status of all the demo tasks then prints a message to the + * display. The message will be either PASS - and include in brackets the + * maximum measured jitter time (as described at the to of the file), or a + * message that describes which of the standard demo tasks an error has been + * discovered in. + * + * Messages are not written directly to the terminal, but passed to vLCDTask + * via a queue. + */ +static void vCheckTask( void *pvParameters ); + +/* + * Configures the timers and interrupts for the fast interrupt test as + * described at the top of this file. + */ +extern void vSetupTimerTest( void ); + +/*-----------------------------------------------------------*/ + +/* The queue used to send messages to the LCD task. */ +xQueueHandle xLCDQueue; + +/*-----------------------------------------------------------*/ + +int main( void ) +{ +#ifdef DEBUG + debug(); +#endif + + prvSetupHardware(); + + /* Create the queue used by the LCD task. Messages for display on the LCD + are received via this queue. */ + xLCDQueue = xQueueCreate( mainLCD_QUEUE_SIZE, sizeof( xLCDMessage ) ); + + /* Start the standard demo tasks. */ + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vCreateBlockTimeTasks(); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartIntegerMathTasks( mainINTEGER_TASK_PRIORITY ); + vStartLEDFlashTasks( mainFLASH_TASK_PRIORITY ); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); + + /* Start the tasks defined within this file/specific to this demo. */ + xTaskCreate( vCheckTask, ( signed portCHAR * ) "Check", mainCHECK_TASK_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + xTaskCreate( vLCDTask, ( signed portCHAR * ) "LCD", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + + /* The suicide tasks must be created last as they need to know how many + tasks were running prior to their creation in order to ascertain whether + or not the correct/expected number of tasks are running at any given time. */ + vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); + + /* Configure the timers used by the fast interrupt timer test. */ + vSetupTimerTest(); + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* Will only get here if there was not enough heap space to create the + idle task. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vLCDTask( void *pvParameters ) +{ +xLCDMessage xMessage; + + /* Initialise the LCD and display a startup message. */ + prvConfigureLCD(); + LCD_DrawMonoPict( ( unsigned portLONG * ) pcBitmap ); + + for( ;; ) + { + /* Wait for a message to arrive that requires displaying. */ + while( xQueueReceive( xLCDQueue, &xMessage, portMAX_DELAY ) != pdPASS ); + + /* Display the message. Print each message to a different position. */ + printf( ( portCHAR const * ) xMessage.pcMessage ); + } +} +/*-----------------------------------------------------------*/ + +static void vCheckTask( void *pvParameters ) +{ +portTickType xLastExecutionTime; +xLCDMessage xMessage; +static signed portCHAR cPassMessage[ mainMAX_MSG_LEN ]; +extern unsigned portSHORT usMaxJitter; + + xLastExecutionTime = xTaskGetTickCount(); + xMessage.pcMessage = cPassMessage; + + for( ;; ) + { + /* Perform this check every mainCHECK_DELAY milliseconds. */ + vTaskDelayUntil( &xLastExecutionTime, mainCHECK_DELAY ); + + /* Has an error been found in any task? */ + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN BLOCK Q\n"; + } + else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN BLOCK TIME\n"; + } + else if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN SEMAPHORE\n"; + } + else if( xArePollingQueuesStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN POLL Q\n"; + } + else if( xIsCreateTaskStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN CREATE\n"; + } + else if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN MATH\n"; + } + else if( xAreComTestTasksStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN COM TEST\n"; + } + else + { + sprintf( ( portCHAR * ) cPassMessage, "PASS [%uns]\n", ( ( unsigned portLONG ) usMaxJitter ) * mainNS_PER_CLOCK ); + } + + /* Send the message to the LCD gatekeeper for display. */ + xQueueSend( xLCDQueue, &xMessage, portMAX_DELAY ); + } +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Start with the clocks in their expected state. */ + RCC_DeInit(); + + /* Enable HSE (high speed external clock). */ + RCC_HSEConfig( RCC_HSE_ON ); + + /* Wait till HSE is ready. */ + while( RCC_GetFlagStatus( RCC_FLAG_HSERDY ) == RESET ) + { + } + + /* 2 wait states required on the flash. */ + *( ( unsigned portLONG * ) 0x40022000 ) = 0x02; + + /* HCLK = SYSCLK */ + RCC_HCLKConfig( RCC_SYSCLK_Div1 ); + + /* PCLK2 = HCLK */ + RCC_PCLK2Config( RCC_HCLK_Div1 ); + + /* PCLK1 = HCLK/2 */ + RCC_PCLK1Config( RCC_HCLK_Div2 ); + + /* PLLCLK = 8MHz * 9 = 72 MHz. */ + RCC_PLLConfig( RCC_PLLSource_HSE_Div1, RCC_PLLMul_9 ); + + /* Enable PLL. */ + RCC_PLLCmd( ENABLE ); + + /* Wait till PLL is ready. */ + while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) + { + } + + /* Select PLL as system clock source. */ + RCC_SYSCLKConfig( RCC_SYSCLKSource_PLLCLK ); + + /* Wait till PLL is used as system clock source. */ + while( RCC_GetSYSCLKSource() != 0x08 ) + { + } + + /* Enable GPIOA, GPIOB, GPIOC, GPIOD, GPIOE and AFIO clocks */ + RCC_APB2PeriphClockCmd( RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB |RCC_APB2Periph_GPIOC + | RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE | RCC_APB2Periph_AFIO, ENABLE ); + + /* SPI2 Periph clock enable */ + RCC_APB1PeriphClockCmd( RCC_APB1Periph_SPI2, ENABLE ); + + + /* Set the Vector Table base address at 0x08000000 */ + NVIC_SetVectorTable( NVIC_VectTab_FLASH, 0x0 ); + + NVIC_PriorityGroupConfig( NVIC_PriorityGroup_4 ); + + /* Configure HCLK clock as SysTick clock source. */ + SysTick_CLKSourceConfig( SysTick_CLKSource_HCLK ); + + vParTestInitialise(); +} +/*-----------------------------------------------------------*/ + +static void prvConfigureLCD( void ) +{ +GPIO_InitTypeDef GPIO_InitStructure; + + /* Configure LCD Back Light (PA8) as output push-pull */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_Init( GPIOA, &GPIO_InitStructure ); + + /* Set the Backlight Pin */ + GPIO_WriteBit(GPIOA, GPIO_Pin_8, Bit_SET); + + /* Initialize the LCD */ + LCD_Init(); + + /* Set the Back Color */ + LCD_SetBackColor( White ); + + /* Set the Text Color */ + LCD_SetTextColor( 0x051F ); + + LCD_Clear(); +} +/*-----------------------------------------------------------*/ + +int fputc( int ch, FILE *f ) +{ +static unsigned portSHORT usColumn = 0, usRefColumn = mainCOLUMN_START; +static unsigned portCHAR ucLine = 0; + + if( ( usColumn == 0 ) && ( ucLine == 0 ) ) + { + LCD_Clear(); + } + + if( ch != '\n' ) + { + /* Display one character on LCD */ + LCD_DisplayChar( ucLine, usRefColumn, (u8) ch ); + + /* Decrement the column position by 16 */ + usRefColumn -= mainCOLUMN_INCREMENT; + + /* Increment the character counter */ + usColumn++; + if( usColumn == mainMAX_COLUMN ) + { + ucLine += mainROW_INCREMENT; + usRefColumn = mainCOLUMN_START; + usColumn = 0; + } + } + else + { + /* Move back to the first column of the next line. */ + ucLine += mainROW_INCREMENT; + usRefColumn = mainCOLUMN_START; + usColumn = 0; + } + + /* Wrap back to the top of the display. */ + if( ucLine >= mainMAX_LINE ) + { + ucLine = 0; + } + + return ch; +} +/*-----------------------------------------------------------*/ + +#ifdef DEBUG +/* Keep the linker happy. */ +void assert_failed( unsigned portCHAR* pcFile, unsigned portLONG ulLine ) +{ + for( ;; ) + { + } +} +#endif diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/serial/serial.c b/20080212/Demo/CORTEX_STM32F103_IAR/serial/serial.c new file mode 100644 index 000000000..c03bd274c --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/serial/serial.c @@ -0,0 +1,243 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0. +*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "queue.h" +#include "semphr.h" + +/* Library includes. */ +#include "stm32f10x_lib.h" + +/* Demo application includes. */ +#include "serial.h" +/*-----------------------------------------------------------*/ + +/* Misc defines. */ +#define serINVALID_QUEUE ( ( xQueueHandle ) 0 ) +#define serNO_BLOCK ( ( portTickType ) 0 ) +#define serTX_BLOCK_TIME ( 40 / portTICK_RATE_MS ) + +/*-----------------------------------------------------------*/ + +/* The queue used to hold received characters. */ +static xQueueHandle xRxedChars; +static xQueueHandle xCharsForTx; + +/*-----------------------------------------------------------*/ + +/* UART interrupt handler. */ +void vUARTInterruptHandler( void ); + +/*-----------------------------------------------------------*/ + +/* + * See the serial2.h header file. + */ +xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) +{ +xComPortHandle xReturn; +USART_InitTypeDef USART_InitStructure; +NVIC_InitTypeDef NVIC_InitStructure; +GPIO_InitTypeDef GPIO_InitStructure; + + /* Create the queues used to hold Rx/Tx characters. */ + xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + + /* If the queue/semaphore was created correctly then setup the serial port + hardware. */ + if( ( xRxedChars != serINVALID_QUEUE ) && ( xCharsForTx != serINVALID_QUEUE ) ) + { + /* Enable USART1 clock */ + RCC_APB2PeriphClockCmd( RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOA, ENABLE ); + + /* Configure USART1 Rx (PA10) as input floating */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; + GPIO_Init( GPIOA, &GPIO_InitStructure ); + + /* Configure USART1 Tx (PA9) as alternate function push-pull */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init( GPIOA, &GPIO_InitStructure ); + + USART_InitStructure.USART_BaudRate = ulWantedBaud; + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No ; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_InitStructure.USART_Clock = USART_Clock_Disable; + USART_InitStructure.USART_CPOL = USART_CPOL_Low; + USART_InitStructure.USART_CPHA = USART_CPHA_2Edge; + USART_InitStructure.USART_LastBit = USART_LastBit_Disable; + + USART_Init( USART1, &USART_InitStructure ); + + USART_ITConfig( USART1, USART_IT_RXNE, ENABLE ); + + NVIC_InitStructure.NVIC_IRQChannel = USART1_IRQChannel; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = configLIBRARY_KERNEL_INTERRUPT_PRIORITY; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init( &NVIC_InitStructure ); + + USART_Cmd( USART1, ENABLE ); + } + else + { + xReturn = ( xComPortHandle ) 0; + } + + /* This demo file only supports a single port but we have to return + something to comply with the standard demo header file. */ + return xReturn; +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) +{ + /* The port handle is not required as this driver only supports one port. */ + ( void ) pxPort; + + /* Get the next character from the buffer. Return false if no characters + are available, or arrive before xBlockTime expires. */ + if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) + { + return pdTRUE; + } + else + { + return pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength ) +{ +signed portCHAR *pxNext; + + /* A couple of parameters that this port does not use. */ + ( void ) usStringLength; + ( void ) pxPort; + + /* NOTE: This implementation does not handle the queue being full as no + block time is used! */ + + /* The port handle is not required as this driver only supports UART1. */ + ( void ) pxPort; + + /* Send each character in the string, one at a time. */ + pxNext = ( signed portCHAR * ) pcString; + while( *pxNext ) + { + xSerialPutChar( pxPort, *pxNext, serNO_BLOCK ); + pxNext++; + } +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) +{ +signed portBASE_TYPE xReturn; + + if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) == pdPASS ) + { + xReturn = pdPASS; + USART_ITConfig( USART1, USART_IT_TXE, ENABLE ); + } + else + { + xReturn = pdFAIL; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +void vSerialClose( xComPortHandle xPort ) +{ + /* Not supported as not required by the demo application. */ +} +/*-----------------------------------------------------------*/ + +void vUARTInterruptHandler( void ) +{ +portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByPost = pdFALSE; +portCHAR cChar; + + if( USART_GetITStatus( USART1, USART_IT_TXE ) == SET ) + { + /* The interrupt was caused by the THR becoming empty. Are there any + more characters to transmit? */ + if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE ) + { + /* A character was retrieved from the queue so can be sent to the + THR now. */ + USART_SendData( USART1, cChar ); + } + else + { + USART_ITConfig( USART1, USART_IT_TXE, DISABLE ); + } + } + + if( USART_GetITStatus( USART1, USART_IT_RXNE ) == SET ) + { + cChar = USART_ReceiveData( USART1 ); + xTaskWokenByPost = xQueueSendFromISR( xRxedChars, &cChar, xTaskWokenByPost ); + } + + portEND_SWITCHING_ISR( xTaskWokenByPost || xTaskWokenByTx ); +} + + + + + + diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/spi_flash.c b/20080212/Demo/CORTEX_STM32F103_IAR/spi_flash.c new file mode 100644 index 000000000..b96cbff6e --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/spi_flash.c @@ -0,0 +1,498 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : spi_flash.c +* Author : MCD Application Team +* Date First Issued : 02/05/2007 +* Description : This file provides a set of functions needed to manage the +* communication between SPI peripheral and SPI M25P64 FLASH. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "spi_flash.h" + +/* Private typedef -----------------------------------------------------------*/ +#define SPI_FLASH_PageSize 256 + +#define WRITE 0x02 /* Write to Memory instruction */ +#define WRSR 0x01 /* Write Status Register instruction */ +#define WREN 0x06 /* Write enable instruction */ + +#define READ 0x03 /* Read from Memory instruction */ +#define RDSR 0x05 /* Read Status Register instruction */ +#define RDID 0x9F /* Read identification */ +#define SE 0xD8 /* Sector Erase instruction */ +#define BE 0xC7 /* Bulk Erase instruction */ + +#define WIP_Flag 0x01 /* Write In Progress (WIP) flag */ + +#define Dummy_Byte 0xA5 + +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : SPI_FLASH_Init +* Description : Initializes the peripherals used by the SPI FLASH driver. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SPI_FLASH_Init(void) +{ + SPI_InitTypeDef SPI_InitStructure; + GPIO_InitTypeDef GPIO_InitStructure; + + /* Enable SPI1 and GPIOA clocks */ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1 | RCC_APB2Periph_GPIOA, ENABLE); + + /* Configure SPI1 pins: NSS, SCK, MISO and MOSI */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + /* Configure PA.4 as Output push-pull, used as Flash Chip select */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + /* Deselect the FLASH: Chip Select high */ + SPI_FLASH_ChipSelect(High); + + /* SPI1 configuration */ + SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; + SPI_InitStructure.SPI_Mode = SPI_Mode_Master; + SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; + SPI_InitStructure.SPI_CPOL = SPI_CPOL_High; + SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge; + SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; + SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4; + SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; + SPI_InitStructure.SPI_CRCPolynomial = 7; + SPI_Init(SPI1, &SPI_InitStructure); + + /* Enable SPI1 */ + SPI_Cmd(SPI1, ENABLE); +} + +/******************************************************************************* +* Function Name : SPI_FLASH_SectorErase +* Description : Erases the specified FLASH sector. +* Input : SectorAddr: address of the sector to erase. +* Output : None +* Return : None +*******************************************************************************/ +void SPI_FLASH_SectorErase(u32 SectorAddr) +{ + /* Send write enable instruction */ + SPI_FLASH_WriteEnable(); + + /* Sector Erase */ + /* Select the FLASH: Chip Select low */ + SPI_FLASH_ChipSelect(Low); + /* Send Sector Erase instruction */ + SPI_FLASH_SendByte(SE); + /* Send SectorAddr high nibble address byte */ + SPI_FLASH_SendByte((SectorAddr & 0xFF0000) >> 16); + /* Send SectorAddr medium nibble address byte */ + SPI_FLASH_SendByte((SectorAddr & 0xFF00) >> 8); + /* Send SectorAddr low nibble address byte */ + SPI_FLASH_SendByte(SectorAddr & 0xFF); + /* Deselect the FLASH: Chip Select high */ + SPI_FLASH_ChipSelect(High); + + /* Wait the end of Flash writing */ + SPI_FLASH_WaitForWriteEnd(); +} + +/******************************************************************************* +* Function Name : SPI_FLASH_BulkErase +* Description : Erases the entire FLASH. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SPI_FLASH_BulkErase(void) +{ + /* Send write enable instruction */ + SPI_FLASH_WriteEnable(); + + /* Bulk Erase */ + /* Select the FLASH: Chip Select low */ + SPI_FLASH_ChipSelect(Low); + /* Send Bulk Erase instruction */ + SPI_FLASH_SendByte(BE); + /* Deselect the FLASH: Chip Select high */ + SPI_FLASH_ChipSelect(High); + + /* Wait the end of Flash writing */ + SPI_FLASH_WaitForWriteEnd(); +} + +/******************************************************************************* +* Function Name : SPI_FLASH_PageWrite +* Description : Writes more than one byte to the FLASH with a single WRITE +* cycle(Page WRITE sequence). The number of byte can't exceed +* the FLASH page size. +* Input : - pBuffer : pointer to the buffer containing the data to be +* written to the FLASH. +* - WriteAddr : FLASH's internal address to write to. +* - NumByteToWrite : number of bytes to write to the FLASH, +* must be equal or less than "SPI_FLASH_PageSize" value. +* Output : None +* Return : None +*******************************************************************************/ +void SPI_FLASH_PageWrite(u8* pBuffer, u32 WriteAddr, u16 NumByteToWrite) +{ + /* Enable the write access to the FLASH */ + SPI_FLASH_WriteEnable(); + + /* Select the FLASH: Chip Select low */ + SPI_FLASH_ChipSelect(Low); + /* Send "Write to Memory " instruction */ + SPI_FLASH_SendByte(WRITE); + /* Send WriteAddr high nibble address byte to write to */ + SPI_FLASH_SendByte((WriteAddr & 0xFF0000) >> 16); + /* Send WriteAddr medium nibble address byte to write to */ + SPI_FLASH_SendByte((WriteAddr & 0xFF00) >> 8); + /* Send WriteAddr low nibble address byte to write to */ + SPI_FLASH_SendByte(WriteAddr & 0xFF); + + /* while there is data to be written on the FLASH */ + while(NumByteToWrite--) + { + /* Send the current byte */ + SPI_FLASH_SendByte(*pBuffer); + /* Point on the next byte to be written */ + pBuffer++; + } + + /* Deselect the FLASH: Chip Select high */ + SPI_FLASH_ChipSelect(High); + + /* Wait the end of Flash writing */ + SPI_FLASH_WaitForWriteEnd(); +} + +/******************************************************************************* +* Function Name : SPI_FLASH_BufferWrite +* Description : Writes block of data to the FLASH. In this function, the +* number of WRITE cycles are reduced, using Page WRITE sequence. +* Input : - pBuffer : pointer to the buffer containing the data to be +* written to the FLASH. +* - WriteAddr : FLASH's internal address to write to. +* - NumByteToWrite : number of bytes to write to the FLASH. +* Output : None +* Return : None +*******************************************************************************/ +void SPI_FLASH_BufferWrite(u8* pBuffer, u32 WriteAddr, u16 NumByteToWrite) +{ + u8 NumOfPage = 0, NumOfSingle = 0, Addr = 0, count = 0, temp = 0; + + Addr = WriteAddr % SPI_FLASH_PageSize; + count = SPI_FLASH_PageSize - Addr; + NumOfPage = NumByteToWrite / SPI_FLASH_PageSize; + NumOfSingle = NumByteToWrite % SPI_FLASH_PageSize; + + if(Addr == 0) /* WriteAddr is SPI_FLASH_PageSize aligned */ + { + if(NumOfPage == 0) /* NumByteToWrite < SPI_FLASH_PageSize */ + { + SPI_FLASH_PageWrite(pBuffer, WriteAddr, NumByteToWrite); + } + else /* NumByteToWrite > SPI_FLASH_PageSize */ + { + while(NumOfPage--) + { + SPI_FLASH_PageWrite(pBuffer, WriteAddr, SPI_FLASH_PageSize); + WriteAddr += SPI_FLASH_PageSize; + pBuffer += SPI_FLASH_PageSize; + } + + SPI_FLASH_PageWrite(pBuffer, WriteAddr, NumOfSingle); + } + } + else /* WriteAddr is not SPI_FLASH_PageSize aligned */ + { + if(NumOfPage== 0) /* NumByteToWrite < SPI_FLASH_PageSize */ + { + if(NumOfSingle > count) /* (NumByteToWrite + WriteAddr) > SPI_FLASH_PageSize */ + { + temp = NumOfSingle - count; + + SPI_FLASH_PageWrite(pBuffer, WriteAddr, count); + WriteAddr += count; + pBuffer += count; + + SPI_FLASH_PageWrite(pBuffer, WriteAddr, temp); + } + else + { + SPI_FLASH_PageWrite(pBuffer, WriteAddr, NumByteToWrite); + } + } + else /* NumByteToWrite > SPI_FLASH_PageSize */ + { + NumByteToWrite -= count; + NumOfPage = NumByteToWrite / SPI_FLASH_PageSize; + NumOfSingle = NumByteToWrite % SPI_FLASH_PageSize; + + SPI_FLASH_PageWrite(pBuffer, WriteAddr, count); + WriteAddr += count; + pBuffer += count; + + while(NumOfPage--) + { + SPI_FLASH_PageWrite(pBuffer, WriteAddr, SPI_FLASH_PageSize); + WriteAddr += SPI_FLASH_PageSize; + pBuffer += SPI_FLASH_PageSize; + } + + if(NumOfSingle != 0) + { + SPI_FLASH_PageWrite(pBuffer, WriteAddr, NumOfSingle); + } + } + } +} + +/******************************************************************************* +* Function Name : SPI_FLASH_BufferRead +* Description : Reads a block of data from the FLASH. +* Input : - pBuffer : pointer to the buffer that receives the data read +* from the FLASH. +* - ReadAddr : FLASH's internal address to read from. +* - NumByteToRead : number of bytes to read from the FLASH. +* Output : None +* Return : None +*******************************************************************************/ +void SPI_FLASH_BufferRead(u8* pBuffer, u32 ReadAddr, u16 NumByteToRead) +{ + /* Select the FLASH: Chip Select low */ + SPI_FLASH_ChipSelect(Low); + + /* Send "Read from Memory " instruction */ + SPI_FLASH_SendByte(READ); + + /* Send ReadAddr high nibble address byte to read from */ + SPI_FLASH_SendByte((ReadAddr & 0xFF0000) >> 16); + /* Send ReadAddr medium nibble address byte to read from */ + SPI_FLASH_SendByte((ReadAddr& 0xFF00) >> 8); + /* Send ReadAddr low nibble address byte to read from */ + SPI_FLASH_SendByte(ReadAddr & 0xFF); + + while(NumByteToRead--) /* while there is data to be read */ + { + /* Read a byte from the FLASH */ + *pBuffer = SPI_FLASH_SendByte(Dummy_Byte); + /* Point to the next location where the byte read will be saved */ + pBuffer++; + } + + /* Deselect the FLASH: Chip Select high */ + SPI_FLASH_ChipSelect(High); +} + +/******************************************************************************* +* Function Name : SPI_FLASH_ReadID +* Description : Reads FLASH identification. +* Input : None +* Output : None +* Return : FLASH identification +*******************************************************************************/ +u32 SPI_FLASH_ReadID(void) +{ + u32 Temp = 0, Temp0 = 0, Temp1 = 0, Temp2 = 0; + + /* Select the FLASH: Chip Select low */ + SPI_FLASH_ChipSelect(Low); + + /* Send "RDID " instruction */ + SPI_FLASH_SendByte(0x9F); + + /* Read a byte from the FLASH */ + Temp0 = SPI_FLASH_SendByte(Dummy_Byte); + + /* Read a byte from the FLASH */ + Temp1 = SPI_FLASH_SendByte(Dummy_Byte); + + /* Read a byte from the FLASH */ + Temp2 = SPI_FLASH_SendByte(Dummy_Byte); + + /* Deselect the FLASH: Chip Select high */ + SPI_FLASH_ChipSelect(High); + + Temp = (Temp0 << 16) | (Temp1 << 8) | Temp2; + + return Temp; +} + +/******************************************************************************* +* Function Name : SPI_FLASH_StartReadSequence +* Description : Initiates a read data byte (READ) sequence from the Flash. +* This is done by driving the /CS line low to select the device, +* then the READ instruction is transmitted followed by 3 bytes +* address. This function exit and keep the /CS line low, so the +* Flash still being selected. With this technique the whole +* content of the Flash is read with a single READ instruction. +* Input : - ReadAddr : FLASH's internal address to read from. +* Output : None +* Return : None +*******************************************************************************/ +void SPI_FLASH_StartReadSequence(u32 ReadAddr) +{ + /* Select the FLASH: Chip Select low */ + SPI_FLASH_ChipSelect(Low); + + /* Send "Read from Memory " instruction */ + SPI_FLASH_SendByte(READ); + +/* Send the 24-bit address of the address to read from -----------------------*/ + /* Send ReadAddr high nibble address byte */ + SPI_FLASH_SendByte((ReadAddr & 0xFF0000) >> 16); + /* Send ReadAddr medium nibble address byte */ + SPI_FLASH_SendByte((ReadAddr& 0xFF00) >> 8); + /* Send ReadAddr low nibble address byte */ + SPI_FLASH_SendByte(ReadAddr & 0xFF); +} + +/******************************************************************************* +* Function Name : SPI_FLASH_ReadByte +* Description : Reads a byte from the SPI Flash. +* This function must be used only if the Start_Read_Sequence +* function has been previously called. +* Input : None +* Output : None +* Return : Byte Read from the SPI Flash. +*******************************************************************************/ +u8 SPI_FLASH_ReadByte(void) +{ + return (SPI_FLASH_SendByte(Dummy_Byte)); +} + +/******************************************************************************* +* Function Name : SPI_FLASH_ChipSelect +* Description : Selects or deselects the FLASH. +* Input : State : level to be applied on the FLASH's ChipSelect pin. +* Output : None +* Return : None +*******************************************************************************/ +void SPI_FLASH_ChipSelect(u8 State) +{ + /* Set High or low the chip select line on PA.4 pin */ + GPIO_WriteBit(GPIOA, GPIO_Pin_4, (BitAction)State); +} + +/******************************************************************************* +* Function Name : SPI_FLASH_SendByte +* Description : Sends a byte through the SPI interface and return the byte +* received from the SPI bus. +* Input : byte : byte to send. +* Output : None +* Return : The value of the received byte. +*******************************************************************************/ +u8 SPI_FLASH_SendByte(u8 byte) +{ + /* Loop while DR register in not emplty */ + while(SPI_GetFlagStatus(SPI1, SPI_FLAG_TXE) == RESET); + + /* Send byte through the SPI1 peripheral */ + SPI_SendData(SPI1, byte); + + /* Wait to receive a byte */ + while(SPI_GetFlagStatus(SPI1, SPI_FLAG_RXNE) == RESET); + + /* Return the byte read from the SPI bus */ + return SPI_ReceiveData(SPI1); +} + +/******************************************************************************* +* Function Name : SPI_FLASH_SendHalfWord +* Description : Sends a Half Word through the SPI interface and return the +* Half Word received from the SPI bus. +* Input : Half Word : Half Word to send. +* Output : None +* Return : The value of the received Half Word. +*******************************************************************************/ +u16 SPI_FLASH_SendHalfWord(u16 HalfWord) +{ + /* Loop while DR register in not emplty */ + while(SPI_GetFlagStatus(SPI1, SPI_FLAG_TXE) == RESET); + + /* Send Half Word through the SPI1 peripheral */ + SPI_SendData(SPI1, HalfWord); + + /* Wait to receive a Half Word */ + while(SPI_GetFlagStatus(SPI1, SPI_FLAG_RXNE) == RESET); + + /* Return the Half Word read from the SPI bus */ + return SPI_ReceiveData(SPI1); +} + +/******************************************************************************* +* Function Name : SPI_FLASH_WriteEnable +* Description : Enables the write access to the FLASH. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SPI_FLASH_WriteEnable(void) +{ + /* Select the FLASH: Chip Select low */ + SPI_FLASH_ChipSelect(Low); + + /* Send "Write Enable" instruction */ + SPI_FLASH_SendByte(WREN); + + /* Deselect the FLASH: Chip Select high */ + SPI_FLASH_ChipSelect(High); +} + +/******************************************************************************* +* Function Name : SPI_FLASH_WaitForWriteEnd +* Description : Polls the status of the Write In Progress (WIP) flag in the +* FLASH's status register and loop until write opertaion +* has completed. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SPI_FLASH_WaitForWriteEnd(void) +{ + u8 FLASH_Status = 0; + + /* Select the FLASH: Chip Select low */ + SPI_FLASH_ChipSelect(Low); + + /* Send "Read Status Register" instruction */ + SPI_FLASH_SendByte(RDSR); + + /* Loop as long as the memory is busy with a write cycle */ + do + { + + /* Send a dummy byte to generate the clock needed by the FLASH + and put the value of the status register in FLASH_Status variable */ + FLASH_Status = SPI_FLASH_SendByte(Dummy_Byte); + + } while((FLASH_Status & WIP_Flag) == SET); /* Write in progress */ + + /* Deselect the FLASH: Chip Select high */ + SPI_FLASH_ChipSelect(High); +} + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/stm32f10x_conf.h b/20080212/Demo/CORTEX_STM32F103_IAR/stm32f10x_conf.h new file mode 100644 index 000000000..c4ca772ee --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/stm32f10x_conf.h @@ -0,0 +1,137 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_conf.h +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : Library configuration file. +******************************************************************************** +* History: +* mm/dd/yyyy: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_CONF_H +#define __STM32F10x_CONF_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_type.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Comment the line below to compile the library in release mode */ +#define DEBUG + +/* Comment the line below to disable the specific peripheral inclusion */ +/************************************* ADC ************************************/ +//#define _ADC +//#define _ADC1 +//#define _ADC2 + +/************************************* CAN ************************************/ +//#define _CAN + +/************************************* DMA ************************************/ +//#define _DMA +//#define _DMA_Channel1 +//#define _DMA_Channel2 +//#define _DMA_Channel3 +//#define _DMA_Channel4 +//#define _DMA_Channel5 +//#define _DMA_Channel6 +//#define _DMA_Channel7 + +/************************************* EXTI ***********************************/ +#define _EXTI + +/************************************* GPIO ***********************************/ +#define _GPIO +#define _GPIOA +#define _GPIOB +#define _GPIOC +#define _GPIOD +#define _GPIOE +#define _AFIO + +/************************************* I2C ************************************/ +//#define _I2C +//#define _I2C1 +//#define _I2C2 + +/************************************* IWDG ***********************************/ +//#define _IWDG + +/************************************* NVIC ***********************************/ +#define _NVIC +#define _SCB + +/************************************* BKP ************************************/ +//#define _BKP + +/************************************* PWR ************************************/ +//#define _PWR + +/************************************* RCC ************************************/ +#define _RCC + +/************************************* RTC ************************************/ +//#define _RTC + +/************************************* SPI ************************************/ +#define _SPI +#define _SPI1 +#define _SPI2 + +/************************************* SysTick ********************************/ +#define _SysTick + +/************************************* TIM ************************************/ +//#define _TIM +#define _TIM2 +#define _TIM3 +//#define _TIM4 + +/************************************* USART **********************************/ +#define _USART +#define _USART1 +//#define _USART2 +//#define _USART3 + +/************************************* WWDG ***********************************/ +//#define _WWDG + +/* In the following line adjust the value of External High Speed oscillator (HSE) + used in your application */ +#define HSE_Value ((u32)8000000) /* Value of the External oscillator in Hz*/ + +/* Exported macro ------------------------------------------------------------*/ +#undef assert +#ifdef DEBUG +/******************************************************************************* +* Macro Name : assert +* Description : The assert macro is used for function's parameters check. +* It is used only if the library is compiled in DEBUG mode. +* Input : - expr: If expr is false, it calls assert_failed function +* which reports the name of the source file and the source +* line number of the call that failed. +* If expr is true, it returns no value. +* Return : None +*******************************************************************************/ + #define assert(expr) ((expr) ? (void)0 : assert_failed(__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(u8* file, u32 line); +#else + #define assert(expr) ((void)0) +#endif /* DEBUG */ + +/* Exported functions ------------------------------------------------------- */ + +#endif /* __STM32F10x_CONF_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/stm32f10x_it.c b/20080212/Demo/CORTEX_STM32F103_IAR/stm32f10x_it.c new file mode 100644 index 000000000..e6dc5c531 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/stm32f10x_it.c @@ -0,0 +1,617 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_it.c +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : Main Interrupt Service Routines. +* This file can be used to describe all the exceptions +* subroutines that may occur within user application. +* When an interrupt happens, the software will branch +* automatically to the corresponding routine. +* The following routines are all empty, user can write code +* for exceptions handlers and peripherals IRQ interrupts. +******************************************************************************** +* History: +* mm/dd/yyyy: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_it.h" + +extern void TimingDelay_Decrement(void); + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : NMIException +* Description : This function handles NMI exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void NMIException(void) +{ +} + +/******************************************************************************* +* Function Name : HardFaultException +* Description : This function handles Hard Fault exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void HardFaultException(void) +{ +} + +/******************************************************************************* +* Function Name : MemManageException +* Description : This function handles Memory Manage exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void MemManageException(void) +{ +} + +/******************************************************************************* +* Function Name : BusFaultException +* Description : This function handles Bus Fault exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void BusFaultException(void) +{ +} + +/******************************************************************************* +* Function Name : UsageFaultException +* Description : This function handles Usage Fault exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void UsageFaultException(void) +{ +} + +/******************************************************************************* +* Function Name : DebugMonitor +* Description : This function handles Debug Monitor exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void DebugMonitor(void) +{ +} + +/******************************************************************************* +* Function Name : SVCHandler +* Description : This function handles SVCall exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SVCHandler(void) +{ +} + +/******************************************************************************* +* Function Name : PendSVC +* Description : This function handles PendSVC exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void PendSVC(void) +{ +} + +/******************************************************************************* +* Function Name : SysTickHandler +* Description : This function handles SysTick Handler. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SysTickHandler(void) +{ + /* Decrement the TimingDelay variable */ + TimingDelay_Decrement(); +} + +/******************************************************************************* +* Function Name : WWDG_IRQHandler +* Description : This function handles WWDG interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void WWDG_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : PVD_IRQHandler +* Description : This function handles PVD interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void PVD_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : TAMPER_IRQHandler +* Description : This function handles Tamper interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TAMPER_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : RTC_IRQHandler +* Description : This function handles RTC global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RTC_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : FLASH_IRQHandler +* Description : This function handles Flash interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void FLASH_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : RCC_IRQHandler +* Description : This function handles RCC interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RCC_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : EXTI0_IRQHandler +* Description : This function handles External interrupt Line 0 request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void EXTI0_IRQHandler(void) +{ + +} + +/******************************************************************************* +* Function Name : EXTI1_IRQHandler +* Description : This function handles External interrupt Line 1 request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void EXTI1_IRQHandler(void) +{ + +} + +/******************************************************************************* +* Function Name : EXTI2_IRQHandler +* Description : This function handles External interrupt Line 2 request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void EXTI2_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : EXTI3_IRQHandler +* Description : This function handles External interrupt Line 3 request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void EXTI3_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : EXTI4_IRQHandler +* Description : This function handles External interrupt Line 4 request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void EXTI4_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : DMAChannel1_IRQHandler +* Description : This function handles DMA Stream 1 interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void DMAChannel1_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : DMAChannel2_IRQHandler +* Description : This function handles DMA Stream 2 interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void DMAChannel2_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : DMAChannel3_IRQHandler +* Description : This function handles DMA Stream 3 interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void DMAChannel3_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : DMAChannel4_IRQHandler +* Description : This function handles DMA Stream 4 interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void DMAChannel4_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : DMAChannel5_IRQHandler +* Description : This function handles DMA Stream 5 interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void DMAChannel5_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : DMAChannel6_IRQHandler +* Description : This function handles DMA Stream 6 interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void DMAChannel6_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : DMAChannel7_IRQHandler +* Description : This function handles DMA Stream 7 interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void DMAChannel7_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : ADC_IRQHandler +* Description : This function handles ADC global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void ADC_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : USB_HP_CAN_TX_IRQHandler +* Description : This function handles USB High Priority or CAN TX interrupts +* requests. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void USB_HP_CAN_TX_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : USB_LP_CAN_RX0_IRQHandler +* Description : This function handles USB Low Priority or CAN RX0 interrupts +* requests. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void USB_LP_CAN_RX0_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : CAN_RX1_IRQHandler +* Description : This function handles CAN RX1 interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void CAN_RX1_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : CAN_SCE_IRQHandler +* Description : This function handles CAN SCE interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void CAN_SCE_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : EXTI9_5_IRQHandler +* Description : This function handles External lines 9 to 5 interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void EXTI9_5_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : TIM1_BRK_IRQHandler +* Description : This function handles TIM1 Break interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_BRK_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : TIM1_UP_IRQHandler +* Description : This function handles TIM1 overflow and update interrupt +* request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_UP_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : TIM1_TRG_COM_IRQHandler +* Description : This function handles TIM1 Trigger and Commutation interrupts +* requests. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_TRG_COM_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : TIM1_CC_IRQHandler +* Description : This function handles TIM1 capture compare interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_CC_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : TIM2_IRQHandler +* Description : This function handles TIM2 global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM2_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : TIM3_IRQHandler +* Description : This function handles TIM3 global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM3_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : TIM4_IRQHandler +* Description : This function handles TIM4 global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM4_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : I2C1_EV_IRQHandler +* Description : This function handles I2C1 Event interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void I2C1_EV_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : I2C1_ER_IRQHandler +* Description : This function handles I2C1 Error interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void I2C1_ER_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : I2C2_EV_IRQHandler +* Description : This function handles I2C2 Event interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void I2C2_EV_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : I2C2_ER_IRQHandler +* Description : This function handles I2C2 Error interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void I2C2_ER_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : SPI1_IRQHandler +* Description : This function handles SPI1 global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SPI1_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : SPI2_IRQHandler +* Description : This function handles SPI2 global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SPI2_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : USART1_IRQHandler +* Description : This function handles USART1 global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void USART1_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : USART2_IRQHandler +* Description : This function handles USART2 global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void USART2_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : USART3_IRQHandler +* Description : This function handles USART3 global interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void USART3_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : EXTI15_10_IRQHandler +* Description : This function handles External lines 15 to 10 interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void EXTI15_10_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : RTCAlarm_IRQHandler +* Description : This function handles RTC Alarm interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RTCAlarm_IRQHandler(void) +{ +} + +/******************************************************************************* +* Function Name : USBWakeUp_IRQHandler +* Description : This function handles USB WakeUp interrupt request. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void USBWakeUp_IRQHandler(void) +{ +} + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/stm32f10x_vector.c b/20080212/Demo/CORTEX_STM32F103_IAR/stm32f10x_vector.c new file mode 100644 index 000000000..a30b73e81 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/stm32f10x_vector.c @@ -0,0 +1,109 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_vector.c +* Author : MCD Application Team +* Date First Issued : 02/19/2007 +* Description : This file contains the vector table for STM32F10x. +* After Reset the Cortex-M3 processor is in Thread mode, +* priority is Privileged, and the Stack is set to Main. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/19/2007: V0.1 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_lib.h" +#include "stm32f10x_it.h" + +extern void xPortPendSVHandler( void ); +extern void xPortSysTickHandler( void ); +extern void vTimer2IntHandler( void ); +extern void vUARTInterruptHandler( void ); + +/* Private typedef -----------------------------------------------------------*/ +typedef void( *intfunc )( void ); +typedef union { intfunc __fun; void * __ptr; } intvec_elem; + +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + + +#pragma language=extended +#pragma segment="CSTACK" + +void __iar_program_start( void ); + +#pragma location = ".intvec" +/* STM32F10x Vector Table entries */ +const intvec_elem __vector_table[] = +{ + { .__ptr = __sfe( "CSTACK" ) }, + &__iar_program_start, + NMIException, + HardFaultException, + MemManageException, + BusFaultException, + UsageFaultException, + 0, 0, 0, 0, /* Reserved */ + SVCHandler, + DebugMonitor, + 0, /* Reserved */ + xPortPendSVHandler, + xPortSysTickHandler, + WWDG_IRQHandler, + PVD_IRQHandler, + TAMPER_IRQHandler, + RTC_IRQHandler, + FLASH_IRQHandler, + RCC_IRQHandler, + EXTI0_IRQHandler, + EXTI1_IRQHandler, + EXTI2_IRQHandler, + EXTI3_IRQHandler, + EXTI4_IRQHandler, + DMAChannel1_IRQHandler, + DMAChannel2_IRQHandler, + DMAChannel3_IRQHandler, + DMAChannel4_IRQHandler, + DMAChannel5_IRQHandler, + DMAChannel6_IRQHandler, + DMAChannel7_IRQHandler, + ADC_IRQHandler, + USB_HP_CAN_TX_IRQHandler, + USB_LP_CAN_RX0_IRQHandler, + CAN_RX1_IRQHandler, + CAN_SCE_IRQHandler, + EXTI9_5_IRQHandler, + TIM1_BRK_IRQHandler, + TIM1_UP_IRQHandler, + TIM1_TRG_COM_IRQHandler, + TIM1_CC_IRQHandler, + vTimer2IntHandler, + TIM3_IRQHandler, + TIM4_IRQHandler, + I2C1_EV_IRQHandler, + I2C1_ER_IRQHandler, + I2C2_EV_IRQHandler, + I2C2_ER_IRQHandler, + SPI1_IRQHandler, + SPI2_IRQHandler, + vUARTInterruptHandler, + USART2_IRQHandler, + USART3_IRQHandler, + EXTI15_10_IRQHandler, + RTCAlarm_IRQHandler, + USBWakeUp_IRQHandler, +}; + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ + diff --git a/20080212/Demo/CORTEX_STM32F103_IAR/timertest.c b/20080212/Demo/CORTEX_STM32F103_IAR/timertest.c new file mode 100644 index 000000000..798db39db --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_IAR/timertest.c @@ -0,0 +1,176 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* High speed timer test as described in main.c. */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* Library includes. */ +#include "stm32f10x_lib.h" +#include "stm32f10x_tim.h" +#include "stm32f10x_map.h" + +/* The set frequency of the interrupt. Deviations from this are measured as +the jitter. */ +#define timerINTERRUPT_FREQUENCY ( ( unsigned portSHORT ) 20000 ) + +/* The expected time between each of the timer interrupts - if the jitter was +zero. */ +#define timerEXPECTED_DIFFERENCE_VALUE ( configCPU_CLOCK_HZ / timerINTERRUPT_FREQUENCY ) + +/* The highest available interrupt priority. */ +#define timerHIGHEST_PRIORITY ( 0 ) + +/* Misc defines. */ +#define timerMAX_32BIT_VALUE ( 0xffffffffUL ) +#define timerTIMER_1_COUNT_VALUE ( * ( ( unsigned long * ) ( TIMER1_BASE + 0x48 ) ) ) + +/* The number of interrupts to pass before we start looking at the jitter. */ +#define timerSETTLE_TIME 5 + +/*-----------------------------------------------------------*/ + +/* + * Configures the two timers used to perform the test. + */ +void vSetupTimerTest( void ); + +/* Interrupt handler in which the jitter is measured. */ +void vTimer2IntHandler( void ); + +/* Stores the value of the maximum recorded jitter between interrupts. */ +volatile unsigned portSHORT usMaxJitter = 0; + +/*-----------------------------------------------------------*/ + +void vSetupTimerTest( void ) +{ +unsigned long ulFrequency; +TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; +NVIC_InitTypeDef NVIC_InitStructure; + + + /* Enable timer clocks */ + RCC_APB1PeriphClockCmd( RCC_APB1Periph_TIM2, ENABLE ); + RCC_APB1PeriphClockCmd( RCC_APB1Periph_TIM3, ENABLE ); + + /* Initialise data. */ + TIM_DeInit( TIM2 ); + TIM_DeInit( TIM3 ); + TIM_TimeBaseStructInit( &TIM_TimeBaseStructure ); + + /* Time base configuration for timer 2 - which generates the interrupts. */ + ulFrequency = configCPU_CLOCK_HZ / timerINTERRUPT_FREQUENCY; + TIM_TimeBaseStructure.TIM_Period = ( unsigned portSHORT ) ( ulFrequency & 0xffffUL ); + TIM_TimeBaseStructure.TIM_Prescaler = 0x0; + TIM_TimeBaseStructure.TIM_ClockDivision = 0x0; + TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseInit( TIM2, &TIM_TimeBaseStructure ); + TIM_ARRPreloadConfig( TIM2, ENABLE ); + + + /* Configuration for timer 3 which is used as a high resolution time + measurement. */ + TIM_TimeBaseStructure.TIM_Period = ( unsigned portSHORT ) 0xffff; + TIM_TimeBaseInit( TIM3, &TIM_TimeBaseStructure ); + TIM_ARRPreloadConfig( TIM3, ENABLE ); + + /* Enable TIM2 IT. TIM3 does not generate an interrupt. */ + NVIC_InitStructure.NVIC_IRQChannel = TIM2_IRQChannel; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = timerHIGHEST_PRIORITY; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init( &NVIC_InitStructure ); + TIM_ITConfig( TIM2, TIM_IT_Update, ENABLE ); + + /* Finally, enable both timers. */ + TIM_Cmd( TIM2, ENABLE ); + TIM_Cmd( TIM3, ENABLE ); +} +/*-----------------------------------------------------------*/ + +void vTimer2IntHandler( void ) +{ +static unsigned portSHORT usLastCount = 0, usSettleCount = 0, usMaxDifference = 0; +unsigned portSHORT usThisCount, usDifference; + + /* Capture the free running timer 3 value as we enter the interrupt. */ + usThisCount = TIM3->CNT; + + if( usSettleCount >= timerSETTLE_TIME ) + { + /* What is the difference between the timer value in this interrupt + and the value from the last interrupt. */ + usDifference = usThisCount - usLastCount; + + /* Store the difference in the timer values if it is larger than the + currently stored largest value. The difference over and above the + expected difference will give the 'jitter' in the processing of these + interrupts. */ + if( usDifference > usMaxDifference ) + { + usMaxDifference = usDifference; + usMaxJitter = usMaxDifference - timerEXPECTED_DIFFERENCE_VALUE; + } + } + else + { + /* Don't bother storing any values for the first couple of + interrupts. */ + usSettleCount++; + } + + /* Remember what the timer value was this time through, so we can calculate + the difference the next time through. */ + usLastCount = usThisCount; + + TIM_ClearITPendingBit( TIM2, TIM_IT_Update ); +} + + + + + + + + diff --git a/20080212/Demo/CORTEX_STM32F103_Primer_GCC/FreeRTOSConfig.h b/20080212/Demo/CORTEX_STM32F103_Primer_GCC/FreeRTOSConfig.h new file mode 100644 index 000000000..5d67ef276 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_Primer_GCC/FreeRTOSConfig.h @@ -0,0 +1,99 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/* Library includes. */ +#include "stm32f10x_lib.h" + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 1 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 72000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 128 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 17 * 1024 ) ) +#define configMAX_TASK_NAME_LEN ( 16 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + +/* This is the raw value as per the Cortex-M3 NVIC. Values can be 255 +(lowest) to 0 (1?) (highest). */ +#define configKERNEL_INTERRUPT_PRIORITY 255 + +/* This is the value being used as per the ST library which permits 16 +priority values, 0 to 15. This must correspond to the +configKERNEL_INTERRUPT_PRIORITY setting. Here 15 corresponds to the lowest +NVIC value of 255. */ +#define configLIBRARY_KERNEL_INTERRUPT_PRIORITY 15 + +#endif /* FREERTOS_CONFIG_H */ + diff --git a/20080212/Demo/CORTEX_STM32F103_Primer_GCC/ParTest/ParTest.c b/20080212/Demo/CORTEX_STM32F103_Primer_GCC/ParTest/ParTest.c new file mode 100644 index 000000000..e7fdf691f --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_Primer_GCC/ParTest/ParTest.c @@ -0,0 +1,127 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +/* FreeRTOS.org includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "partest.h" + +#define partstMAX_OUTPUT_LED ( 2 ) +#define partstFIRST_LED GPIO_Pin_8 + +static unsigned portSHORT usOutputValue = 0; + +/*-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ +GPIO_InitTypeDef GPIO_InitStructure; + + /* Enable LED GPIO clock. */ + RCC_APB2PeriphClockCmd( RCC_APB2Periph_GPIOB, ENABLE ); + + /* Configure LED pins as output push-pull. */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 ; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + + GPIO_Init( GPIOB, &GPIO_InitStructure ); +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ +unsigned portSHORT usBit; + + vTaskSuspendAll(); + { + if( uxLED < partstMAX_OUTPUT_LED ) + { + usBit = partstFIRST_LED << uxLED; + + if( xValue == pdFALSE ) + { + usBit ^= ( unsigned portSHORT ) 0xffff; + usOutputValue &= usBit; + } + else + { + usOutputValue |= usBit; + } + + GPIO_Write( GPIOB, usOutputValue ); + } + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned portSHORT usBit; + + vTaskSuspendAll(); + { + if( uxLED < partstMAX_OUTPUT_LED ) + { + usBit = partstFIRST_LED << uxLED; + + if( usOutputValue & usBit ) + { + usOutputValue &= ~usBit; + } + else + { + usOutputValue |= usBit; + } + + GPIO_Write( GPIOB, usOutputValue ); + } + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + diff --git a/20080212/Demo/CORTEX_STM32F103_Primer_GCC/RTOSDemo-globals.Standard.xml b/20080212/Demo/CORTEX_STM32F103_Primer_GCC/RTOSDemo-globals.Standard.xml new file mode 100644 index 000000000..1156f6f04 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_Primer_GCC/RTOSDemo-globals.Standard.xml @@ -0,0 +1,577 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/20080212/Demo/CORTEX_STM32F103_Primer_GCC/RTOSDemo.Standard.xml b/20080212/Demo/CORTEX_STM32F103_Primer_GCC/RTOSDemo.Standard.xml new file mode 100644 index 000000000..e4bb7e670 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_Primer_GCC/RTOSDemo.Standard.xml @@ -0,0 +1,2278 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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b/20080212/Demo/CORTEX_STM32F103_Primer_GCC/RTOSDemo.rapp new file mode 100644 index 000000000..1d85f43d5 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_Primer_GCC/RTOSDemo.rapp @@ -0,0 +1,108 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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+ + + + + \ No newline at end of file diff --git a/20080212/Demo/CORTEX_STM32F103_Primer_GCC/RTOSDemo.rprj b/20080212/Demo/CORTEX_STM32F103_Primer_GCC/RTOSDemo.rprj new file mode 100644 index 000000000..3eb5276de --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_Primer_GCC/RTOSDemo.rprj @@ -0,0 +1,4 @@ + + + + \ No newline at end of file diff --git a/20080212/Demo/CORTEX_STM32F103_Primer_GCC/ST_Code/Util.c b/20080212/Demo/CORTEX_STM32F103_Primer_GCC/ST_Code/Util.c new file mode 100644 index 000000000..b331df730 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_Primer_GCC/ST_Code/Util.c @@ -0,0 +1,528 @@ +/********************* (C) COPYRIGHT 2007 RAISONANCE S.A.S. *******************/ +/** +* +* @file Util.c +* @brief Various utilities for STM32 CircleOS. +* @author RT +* @date 07/2007 +* +**/ +/******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ + +#include "circle.h" +#include "adc.h" + +/// @cond Internal + +/* Private defines -----------------------------------------------------------*/ +#define GPIO_USB_PIN GPIO_Pin_1 +#define GPIOx_USB GPIOA +#define OsVersion "V 1.7" /*!< CircleOS version string. */ + +/* Private typedef -----------------------------------------------------------*/ +enum eSpeed CurrentSpeed; + +/* Private variables ---------------------------------------------------------*/ +RCC_ClocksTypeDef RCC_ClockFreq; +int dummycounter = 0; +u8 fTemperatureInFahrenheit = 0; /*!< 1 : Fahrenheit, 0 : Celcius (default). */ + +/* Private function prototypes -----------------------------------------------*/ +static void _int2str( char* ptr, s32 X, u16 digit, int flagunsigned, int fillwithzero ); + +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* +* _int2str +* +*******************************************************************************/ +/** +* +* Translate a 32 bit word into a string. +* +* @param[in,out] ptr A pointer to a string large enough to contain +* the translated 32 bit word. +* @param[in] X The 32 bit word to translate. +* @param[in] digit The amount of digits wanted in the result string. +* @param[in] flagunsigned Is the input word unsigned? +* @param[in] fillwithzero Fill with zeros or spaces. +* +**/ +/******************************************************************************/ +static void _int2str( char* ptr, s32 X, u16 digit, int flagunsigned, int fillwithzero ) + { + u8 c; + u8 fFirst = 0; + u8 fNeg = 0; + u32 DIG = 1; + int i; + + for( i = 1; i < digit; i++ ) + { + DIG *= 10; + } + + if( !flagunsigned && ( X < 0 ) ) + { + fNeg = 1; + X = -X; + } + + u32 r = X; + + for( i = 0; i < digit; i++, DIG /= 10 ) + { + c = (r/DIG); + r -= (c*DIG); + + if( fillwithzero || fFirst || c || ( i == ( digit - 1 ) ) ) + { + if( ( fFirst == 0 ) && !flagunsigned ) + { + *ptr++ = fNeg ? '-' : ' '; + } + + *ptr++ = c + 0x30; + fFirst = 1; + } + else + { + *ptr++ = ' '; + } + } + + *ptr++ = 0; + } + +/* Public functions for CircleOS ---------------------------------------------*/ + +/******************************************************************************* +* +* delay_unit +* +*******************************************************************************/ +/** +* +* Called by starting_delay(). +* +* @note Not in main.c to avoid inlining. +* +**/ +/******************************************************************************/ +void delay_unit( void ) + { + dummycounter++; + } + +/// @endcond + +/* Public functions ----------------------------------------------------------*/ + +/******************************************************************************* +* +* UTIL_GetBat +* +*******************************************************************************/ +/** +* +* Return the batterie tension in mV. +* +* @return Batterie tension in mV. +* +**/ +/******************************************************************************/ +u16 UTIL_GetBat( void ) + { +#ifdef _ADC + u16 vbat; + + // Measure VBAT + vbat = ADC_ConvertedValue[0]; //*( (u16*)ADC1_DR_Address ); // <=== note changed + vbat = vbat & 0xFFF; + vbat = ( vbat * VDD_VOLTAGE_MV ) / 0x1000; + + return vbat; +#else + return 0; +#endif + } + +/******************************************************************************* +* +* UTIL_GetTemp +* +*******************************************************************************/ +/** +* +* Return the Temperature: degrees / 10, Celcius or Fahrenheit. +* +* @return The temperature (C or F) (averaging of several channels). +* +**/ +/******************************************************************************/ +u16 UTIL_GetTemp( void ) + { + s32 temp; + s16 *p=&ADC_ConvertedValue[1]; //intent; point to first of 8 results from same source - use a short name for it! + + // Measure temp + //temp = ADC_ConvertedValue[1];//*( (u16*)ADC1_DR_Address ); + temp = (p[0]+p[1]+p[2]+p[3]+p[4]+p[5]+p[6]+p[7])/8; //take avg of burst of 8 temp reads. may only help reject hi freq noise a bit + //will not help reduce mains ripple because conversions are SO FAST!! + temp = temp & 0xFFF; + temp = ( temp * VDD_VOLTAGE_MV ) / 0x1000; //finds mV + temp = (((1400-temp)*100000)/448)+25000; //gives approx temp x 1000 degrees C + + //Fahrenheit = 32 + 9 / 5 * Celsius + if ( fTemperatureInFahrenheit ) + { + temp = 32000 + (9 * temp) / 5 ; + } + + return temp / 100; + } + +/******************************************************************************* +* +* UTIL_SetTempMode +* +*******************************************************************************/ +/** +* +* Set the temperature mode (F/C) +* +* @param[in] mode 0: Celcius, 1: Fahrenheit +* +**/ +/******************************************************************************/ +void UTIL_SetTempMode ( int mode ) + { + fTemperatureInFahrenheit = mode; + + return; + } + + +/******************************************************************************* +* +* UTIL_GetUsb +* +*******************************************************************************/ +/** +* +* Return the USB connexion state. +* +* @return The USB connexion state. +* +**/ +/******************************************************************************/ +u8 UTIL_GetUsb( void ) + { + GPIO_InitStructure.GPIO_Pin = GPIO_USB_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + + GPIO_Init( GPIOx_USB, &GPIO_InitStructure ); + + return ( GPIO_ReadInputDataBit( GPIOx_USB, GPIO_USB_PIN ) == Bit_SET ); + } + +/******************************************************************************* +* +* UTIL_uint2str +* +*******************************************************************************/ +/** +* +* Convert an unsigned integer into a string. +* +* @param [out] ptr The output string. +* @param [in] X The unsigned value to convert. +* @param [in] digit The number of digits in the output string. +* @param [in] fillwithzero \li 0 fill with blanks. +* \li 1 fill with zeros. +* +**/ +/********************************************************************************/ +void UTIL_uint2str( char* ptr, u32 X, u16 digit, int fillwithzero ) + { + _int2str( ptr, X, digit, 1, fillwithzero); + } + +/******************************************************************************* +* +* UTIL_int2str +* +*******************************************************************************/ +/** +* +* Convert a signed integer into a string. +* +* @param [out] ptr The output string. +* @param [in] X The unsigned value to convert. +* @param [in] digit The number of digits in the output string. +* @param [in] fillwithzero \li 0 fill with blanks. +* \li 1 fill with zeros. +* +**/ +/******************************************************************************/ +void UTIL_int2str( char* ptr, s32 X, u16 digit, int fillwithzero ) + { + _int2str( ptr, X, digit, 0, fillwithzero); + } + +/******************************************************************************* +* +* UTIL_SetPll +* +*******************************************************************************/ +/** +* +* Set clock frequency (lower to save energy) +* +* @param [in] speed New clock speed from very low to very fast. +* +**/ +/******************************************************************************/ +void UTIL_SetPll( enum eSpeed speed ) + { + /* Select PLL as system clock source */ + RCC_SYSCLKConfig( RCC_SYSCLKSource_HSI ); + + /* Enable PLL */ + RCC_PLLCmd( DISABLE ); + + if( ( speed < SPEED_VERY_LOW ) || ( speed > SPEED_VERY_HIGH ) ) + { + speed = SPEED_MEDIUM; + } + + CurrentSpeed = speed; + + switch( speed ) + { + // 18 MHz + case SPEED_VERY_LOW : + /* PLLCLK = 6MHz * 3 = 18 MHz */ + RCC_PLLConfig( RCC_PLLSource_HSE_Div2, RCC_PLLMul_3 ); + break; + + // 24MHz + case SPEED_LOW : + /* PLLCLK = 12MHz * 2 = 24 MHz */ + RCC_PLLConfig( RCC_PLLSource_HSE_Div1, RCC_PLLMul_2 ); + break; + + // 36MHz + case SPEED_MEDIUM : + default : + /* PLLCLK = 12MHz * 3 = 36 MHz */ + RCC_PLLConfig( RCC_PLLSource_HSE_Div1, RCC_PLLMul_3 ); + break; + + // 48MHz + case SPEED_HIGH : + /* PLLCLK = 12MHz * 4 = 48 MHz */ + RCC_PLLConfig( RCC_PLLSource_HSE_Div1, RCC_PLLMul_4 ); + break; + + // 72MHz + case SPEED_VERY_HIGH : + /* PLLCLK = 12MHz * 6 = 72 MHz */ + RCC_PLLConfig( RCC_PLLSource_HSE_Div1, RCC_PLLMul_6 ); + break; + } + + /* Enable PLL */ + RCC_PLLCmd( ENABLE ); + + /* Wait till PLL is ready */ + while( RCC_GetFlagStatus( RCC_FLAG_PLLRDY ) == RESET ) + { ; } + + /* Select PLL as system clock source */ + RCC_SYSCLKConfig( RCC_SYSCLKSource_PLLCLK ); + + /* Wait till PLL is used as system clock source */ + while( RCC_GetSYSCLKSource() != 0x08 ) + { ; } + + /* This function fills a RCC_ClocksTypeDef structure with the current frequencies + of different on chip clocks (for debug purpose) */ + RCC_GetClocksFreq( &RCC_ClockFreq ); + } + +/******************************************************************************* +* +* UTIL_GetPll +* +*******************************************************************************/ +/** +* +* Get clock frequency +* +* @return Current clock speed from very low to very fast. +* +**/ +/******************************************************************************/ +enum eSpeed UTIL_GetPll( void ) + { + return CurrentSpeed; + } + +/******************************************************************************* +* +* UTIL_GetVersion +* +*******************************************************************************/ +/** +* +* Get CircleOS version. +* +* @return A pointer to a string containing the CircleOS version. +* +**/ +/******************************************************************************/ +const char* UTIL_GetVersion( void ) + { + return OsVersion; + } + +/******************************************************************************* +* +* UTIL_ReadBackupRegister +* +*******************************************************************************/ +/** +* +* Reads data from the specified Data Backup Register. +* +* @param[in] BKP_DR Specifies the Data Backup Register. This parameter can be BKP_DRx where x:[1, 10] +* +* @return The content of the specified Data Backup Register. +* +**/ +/******************************************************************************/ +u16 UTIL_ReadBackupRegister( u16 BKP_DR ) + { + return (*(vu16 *)( BKP_BASE + 4 * BKP_DR ) ); + } + +/******************************************************************************* +* +* UTIL_WriteBackupRegister +* +*******************************************************************************/ +/** +* +* Writes data to the specified Data Backup Register. +* +* @param[in] BKP_DR Specifies the Data Backup Register. This parameter can be BKP_DRx where x:[1, 10] +* @param[in] Data The data to write. +* +**/ +/********************************************************************************/ +void UTIL_WriteBackupRegister( u16 BKP_DR, u16 Data ) + { + *(vu16 *)( BKP_BASE + 4 * BKP_DR ) = Data; + } + + +/******************************************************************************* +* +* UTIL_SetIrqHandler +* +*******************************************************************************/ +/** +* +* Redirect an IRQ handler. +* +* @param[in] Offs Address in the NVIC table +* @param[in] pHDL Pointer to the handler. +* +**/ +/********************************************************************************/ +void UTIL_SetIrqHandler( int Offs, tHandler pHDL ) + { + if ( (Offs >= 8) && (Offs<0x100) ) + *(tHandler *)( CIRCLEOS_RAM_BASE + Offs ) = pHDL; + } + +/******************************************************************************* +* +* UTIL_GetIrqHandler +* +*******************************************************************************/ +/** +* +* Get the current IRQ handler. +* Since (V1.6) the vector table is relocated in RAM, the vectors can be easily modified +* by the applications. +* +* @param[in] Offs Address in the NVIC table +* @return A pointer to the current handler. +* +**/ +/********************************************************************************/ +tHandler UTIL_GetIrqHandler( int Offs ) + { + if ( (Offs >= 8) && (Offs<0x100) ) + return *(tHandler *)( CIRCLEOS_RAM_BASE + Offs ); + } + + + +/******************************************************************************* +* +* UTIL_SetSchHandler +* +*******************************************************************************/ +/** +* +* Redirect a SCHEDULER handler. +* Set the current SCHEDULER handler. With UTIL_GetSchHandler(), these functions +* allow to take the control of the different handler. You can: +* - replace them (get-Set)by your own handler +* - disable a handler: UTIL_SetSchHandler(Ix,0); +* - create a new handler (using the unused handlers). +* See scheduler.c to understand further... +* +* @param[in] Ix ID if the SCH Handler +* @param[in] pHDL Pointer to the handler. +* +**/ +/********************************************************************************/ +void UTIL_SetSchHandler( enum eSchHandler Ix, tHandler pHDL ) + { + if (Ix '0') && (*CurrentMelody < '9') ) + { + duration = *CurrentMelody++ - '0'; + + if ( (*CurrentMelody > '0') && (*CurrentMelody < '9') ) + { + duration *= 10; + duration += (*CurrentMelody++ - '0'); + } + } + + Buzzer_Counter = ( (32/duration) * 256L * 32L) / DefaultBeats; + Buzzer_Counter*= (RCC_ClockFreq.SYSCLK_Frequency / 12000000L); //Adapt to HCLK1 + + //read the note + c = *CurrentMelody++; + + if ( (c >= 'a') && (c <= 'z') ) + { + c+=('A'-'a'); + } + + if ( c == 'P' ) + { + note = NOTE_PAUSE; + } + else if ( (c >= 'A') && (c <= 'G') ) + { + note = (c - 'A') + NOTE_LA; + + if ( *CurrentMelody == '#' ) + { + note|=0x8; + CurrentMelody++; + } + } + + octave = DefaultOctave; + c = *CurrentMelody; + + if ( (c>= '5') && (c<= '8') ) + { + octave = OCT_440 + (c-'5'); + CurrentMelody++; + } + + BUZZER_SetFrequency ( (Note_Freq [ note ] * (1<NOT be called by the user. +* +**/ +/******************************************************************************/ +void BUZZER_Init( void ) + { + GPIO_InitTypeDef GPIO_InitStructure; + + /* Enable GPIOB clock */ + RCC_APB2PeriphClockCmd( RCC_APB2Periph_GPIOB, ENABLE ); + + /* GPIOB Configuration: TIM3 3in Output */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + + GPIO_Init( GPIOB, &GPIO_InitStructure ); + + /* TIM3 Configuration ------------------------------------------------------*/ + /* TIM3CLK = 18 MHz, Prescaler = 0x0, TIM3 counter clock = 18 MHz */ + /* CC update rate = TIM3 counter clock / (2* CCR_Val) ~= 750 Hz */ + + /* Enable TIM3 clock */ + RCC_APB1PeriphClockCmd( RCC_APB1Periph_TIM3, ENABLE ); + TIM_DeInit( TIM3 ); + TIM_TimeBaseStructInit( &TIM_TimeBaseStructure ); + TIM_OCStructInit( &TIM_OCInitStructure ); + + /* Time base configuration */ + TIM_TimeBaseStructure.TIM_Period = 0xFFFF; + TIM_TimeBaseStructure.TIM_Prescaler = 0x0; + TIM_TimeBaseStructure.TIM_ClockDivision = 0x0; + TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; + + TIM_TimeBaseInit( TIM3, &TIM_TimeBaseStructure ); + + /* Output Compare Toggle Mode configuration: Channel3 */ + TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_Toggle; + TIM_OCInitStructure.TIM_Channel = TIM_Channel_3; + TIM_OCInitStructure.TIM_Pulse = CCR_Val; + + TIM_OCInit( TIM3, &TIM_OCInitStructure ); + TIM_OC3PreloadConfig( TIM3, TIM_OCPreload_Disable ); + BUZZER_SetFrequency( 440 ); + + /* Enable TIM3 IT */ + TIM_ITConfig( TIM3, TIM_IT_CC3, ENABLE ); + + Buzzer_Mode = BUZZER_OFF; + } + +/******************************************************************************* +* +* BUZZER_Handler +* +*******************************************************************************/ +/** +* +* Called by the CircleOS scheduler to manage Buzzer tasks. +* +* @attention This function must NOT be called by the user. +* +**/ +/******************************************************************************/ +void BUZZER_Handler( void ) + { + int fSetOFF = 0; + + if ( Buzzer_Mode == BUZZER_PLAYMUSIC ) + { + if ( Buzzer_Counter == 0 ) + { + PlayMusic(); + } + else + { + Buzzer_Counter--; + } + + return; + } + else if ( Buzzer_Mode == BUZZER_SHORTBEEP ) + { + if ( Buzzer_Counter++ == (BUZZER_SHORTBEEP_DURATION) ) + { + Buzzer_Mode = BUZZER_OFF; + + return; + } + if ( Buzzer_Counter == (BUZZER_SHORTBEEP_DURATION/2) ) + { + fSetOFF = 1; + } + } + else if ( Buzzer_Mode == BUZZER_LONGBEEP ) + { + if ( Buzzer_Counter++ == (BUZZER_LONGBEEP_DURATION) ) + { + Buzzer_Mode = BUZZER_OFF; + + return; + } + if ( Buzzer_Counter > (BUZZER_LONGBEEP_DURATION/2) ) + { + fSetOFF = 1; + } + } + + if ( fSetOFF == 1 ) + { + TIM_Cmd(TIM3, DISABLE); + } + } + +/// @endcond + +/* Public functions ----------------------------------------------------------*/ + +/******************************************************************************* +* +* BUZZER_GetMode +* +*******************************************************************************/ +/** +* +* Get the current buzzer mode. +* +* @return Current buzzer mode. +* +**/ +/******************************************************************************/ +enum BUZZER_mode BUZZER_GetMode( void ) + { + return Buzzer_Mode; + } + +/******************************************************************************* +* +* BUZZER_SetMode +* +*******************************************************************************/ +/** +* +* Set new buzzer mode +* +* @param[in] mode New buzzer mode. +* +**/ +/******************************************************************************/ +void BUZZER_SetMode( enum BUZZER_mode mode ) + { + Buzzer_Mode = mode; + Buzzer_Counter = 0; + + switch ( mode ) + { + case BUZZER_PLAYMUSIC : + PlayMusic(); //start melody + /* no break */ + + case BUZZER_LONGBEEP : + case BUZZER_SHORTBEEP : + case BUZZER_ON : + TIM_Cmd( TIM3, ENABLE ); + break; + + case BUZZER_OFF : + TIM_Cmd( TIM3, DISABLE ); + break; + } + } + +/******************************************************************************* +* +* BUZZER_PlayMusic +* +*******************************************************************************/ +/** +* +* Plays the provided melody that follows the RTTTL Format. +* +* Official Specification +* @verbatim + := + [] + + := + ; maximum name length 10 characters + := ":" + := + | + | + + := "d=" + := "o=" + := "b=" + := 25,28,...,900 ; decimal value +; If not specified, defaults are + ; + ; 4 = duration + ; 6 = scale + ; 63 = beats-per-minute + := + [] [] [] + := + "1" | ; Full 1/1 note + "2" | ; 1/2 note + "4" | ; 1/4 note + "8" | ; 1/8 note + "16" | ; 1/16 note + "32" | ; 1/32 note + := + "P" | ; pause + "C" | + "C#" | + "D" | + "D#" | + "E" | + "F" | + "F#" | + "G" | + "G#" | + "A" | + "A#" | + "B" + := + "5" | ; Note A is 440Hz + "6" | ; Note A is 880Hz + "7" | ; Note A is 1.76 kHz + "8" ; Note A is 3.52 kHz + := + "." ; Dotted note + := "," +@endverbatim +* +* @param[in] melody New melody to play on buzzer. +* +**/ +/******************************************************************************/ +void BUZZER_PlayMusic (const u8 *melody ) + { + u8 c; + u8 default_id = 0; + u16 default_val = 0; + + DefaultOctave = OCT_880; // Default for the default Octave. + DefaultDuration = 4; // Default for the default Duration. + DefaultBeats = 63; + CurrentMelody = melody; + CurrentMelodySTART = melody; + + while( *CurrentMelody != RTTTL_SEP ) + { + if( *CurrentMelody == 0 ) + { + return; + } + + // Discard the melody name. + CurrentMelody++; + } + + // Now read the defaults if any. + for( ++CurrentMelody; *CurrentMelody != RTTTL_SEP; CurrentMelody++ ) + { + if( *CurrentMelody == 0 ) + { + return; + } + + // Discard any blank. + while ( *CurrentMelody == ' ' ) + { + CurrentMelody++; + } + + c = *CurrentMelody; + + if ( c == RTTTL_SEP ) + { + break; + } + + if ( (c >= 'a') && (c <= 'z') ) + { + c+=('A'-'a'); + } + + if ( (c >= 'A') && (c <= 'Z') ) + { + default_id = c; + continue; + } + + if ( (c >= '0') && (c <= '9') ) + { + default_val *= 10; + default_val += (c-'0'); + c = * (CurrentMelody + 1 ); + + if ( (c >= '0') && (c <= '9') ) + { + continue; + } + + if ( default_id == 'D' ) + { + DefaultDuration = default_val; + } + else if ( default_id == 'O' ) + { + DefaultOctave = default_val - 5; + + if ( DefaultOctave > OCT_7040 ) + DefaultOctave = OCT_440; + } + else if ( default_id == 'B' ) + { + DefaultBeats = default_val; + + if ( ( DefaultBeats == 0 ) || ( DefaultBeats > 500 ) ) + DefaultBeats = 63; + } + + default_val = 0; + default_id = 0; + } + } + + BUZZER_SetMode( BUZZER_PLAYMUSIC ); + } diff --git a/20080212/Demo/CORTEX_STM32F103_Primer_GCC/ST_Code/circle.h b/20080212/Demo/CORTEX_STM32F103_Primer_GCC/ST_Code/circle.h new file mode 100644 index 000000000..0a7c02177 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_Primer_GCC/ST_Code/circle.h @@ -0,0 +1,431 @@ +/********************* (C) COPYRIGHT 2007 RAISONANCE S.A.S. *******************/ +/** +* +* @file circle.h +* @brief General header for the CircleOS project. +* @author FL +* @date 07/2007 +* @version 1.5 +* +* It contains the list of the utilities functions organized by sections +* (MEMS, LCD, POINTER, ...) +* +* @date 10/2007 +* @version 1.5 types of OutX_F64 and OutX_F256 changed to u32 (same for Y and Z) +**/ +/******************************************************************************/ + +#include "scheduler.h" + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CIRCLE_H +#define __CIRCLE_H + +//-------------------------------- General ------------------------------------- +/* Defines ------------------------------------------------------------------*/ +#define VDD_VOLTAGE_MV 3300 //Voltage (mV) of the STM32 +#define FA_TABLE 0x8006000 +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define CIRCLEOS_RAM_BASE 0x20004000 + +/* Variables ----------------------------------------------------------------*/ +extern GPIO_InitTypeDef GPIO_InitStructure; + +/* Utilities -----------------------------------------------------------------*/ +void UTIL_uint2str( char *ptr , u32 X, u16 digit, int fillwithzero ); +void UTIL_int2str( char *ptr , s32 X, u16 digit, int fillwithzero ); +u16 UTIL_ReadBackupRegister( u16 BKP_DR ); +void UTIL_WriteBackupRegister( u16 BKP_DR, u16 Data ); +u16 UTIL_GetBat( void ); +u8 UTIL_GetUsb( void ); +u16 UTIL_GetTemp ( void ) ; +void UTIL_SetTempMode ( int mode ); +//typedef void (*tHandler) ( void ); +void UTIL_SetIrqHandler ( int , tHandler ); +tHandler UTIL_GetIrqHandler ( int ); +extern u16 ADC_ConvertedValue[17]; + + +extern enum eSpeed + { + SPEED_VERY_LOW = 1, + SPEED_LOW = 2, + SPEED_MEDIUM = 3, + SPEED_HIGH = 4, + SPEED_VERY_HIGH = 5 + } CurrentSpeed; + +enum eSchHandler + { + LED_SCHHDL_ID = 0, + BUTTON_SCHHDL_ID = 1, + BUZZER_SCHHDL_ID = 2, + MENU_SCHHDL_ID = 3, + POINTER_SCHHDL_ID = 4, + LCD_SCHHDL_ID = 5, + DRAW_SCHHDL_ID = 6, + RTC_SCHHDL_ID = 7, + + UNUSED0_SCHHDL_ID = 8, + UNUSED1_SCHHDL_ID = 9, + UNUSED2_SCHHDL_ID = 10, + UNUSED3_SCHHDL_ID = 11, + UNUSED4_SCHHDL_ID = 12, + UNUSED5_SCHHDL_ID = 13, + UNUSED6_SCHHDL_ID = 14, + UNUSED7_SCHHDL_ID = 15 + } dummy_var ; //for doxygen + +void UTIL_SetSchHandler ( enum eSchHandler , tHandler ); +tHandler UTIL_GetSchHandler ( enum eSchHandler ); +#define NULL_SCHHDL (0) +#define LAST_SCHHDL ((tHandler)(-1)) + + +void UTIL_SetPll( enum eSpeed speed ); +const char* UTIL_GetVersion( void ); +enum eSpeed UTIL_GetPll( void ); +extern RCC_ClocksTypeDef RCC_ClockFreq; +extern u8 fTemperatureInFahrenheit; /*!< 1 : Fahrenheit, 0 : Celcius (default). */ + + +//--------------------------------- MEMS ------------------------------------ + +/* Exported types ------------------------------------------------------------*/ +typedef enum + { + V12=0, + V3=1, + V6=2, + V9=3 +} Rotate_H12_V_Match_TypeDef; + +typedef struct + { + s16 OutX ; + s16 OutX_F4 ; + s16 OutX_F16 ; + s32 OutX_F64 ; + s32 OutX_F256 ; + s16 OutY ; + s16 OutY_F4 ; + s16 OutY_F16 ; + s32 OutY_F64 ; + s32 OutY_F256 ; + s16 OutZ ; + s16 OutZ_F4 ; + s16 OutZ_F16 ; + s32 OutZ_F64 ; + s32 OutZ_F256 ; + s16 Shocked ; + s16 RELATIVE_X ; + s16 RELATIVE_Y ; + s16 DoubleClick ; + } tMEMS_Info; + +extern tMEMS_Info MEMS_Info; + +/* Exported functions --------------------------------------------------------*/ +void MEMS_Init(void); +void MEMS_Handler(void); +void MEMS_GetPosition(s16 * pX, s16* pY); +void MEMS_SetNeutral( void ); +void MEMS_GetRotation(Rotate_H12_V_Match_TypeDef * H12); +tMEMS_Info* MEMS_GetInfo (void); +u8 MEMS_ReadID(void); + +//---------------------------------- LED ------------------------------------- + +/* Exported types ------------------------------------------------------------*/ +enum LED_mode { LED_UNDEF = -1, LED_OFF = 0, LED_ON = 1, LED_BLINKING_LF = 2, LED_BLINKING_HF = 3 }; +enum LED_id { LED_GREEN = 0, LED_RED = 1}; + +/* Exported functions --------------------------------------------------------*/ +void LED_Init (void); +void LED_Handler_hw ( enum LED_id id ); +void LED_Handler ( void ); +void LED_Set ( enum LED_id id, enum LED_mode mode ); + +//-------------------------------- ADC -------------------------------------- + +/* Exported functions --------------------------------------------------------*/ +void ADConverter_Init (void); + + +//============================================================================== +//-------------------------------- SHUTDOWN --------------------------------- +/* Exported functions --------------------------------------------------------*/ +void SHUTDOWN_Action (void); + +//-------------------------------- BUTTON ----------------------------------- +/* Exported types ------------------------------------------------------------*/ +enum BUTTON_mode { BUTTON_DISABLED = -1, BUTTON_ONOFF = 0, + BUTTON_ONOFF_FORMAIN = 1, BUTTON_WITHCLICK = 2 }; +enum BUTTON_state { BUTTON_UNDEF = -1, BUTTON_RELEASED = 0, BUTTON_PUSHED = 1, + BUTTON_PUSHED_FORMAIN = 2 , BUTTON_CLICK = 3, BUTTON_DBLCLICK = 4 }; + +/* Exported functions -------------------------------------------------------*/ +void BUTTON_Init (void); +void BUTTON_Handler(void); +enum BUTTON_state BUTTON_GetState(); +void BUTTON_SetMode( enum BUTTON_mode mode); +enum BUTTON_mode BUTTON_GetMode ( void ) ; +void BUTTON_WaitForRelease(); + +//-------------------------------- POINTER ---------------------------------- + +/* Exported types ------------------------------------------------------------*/ +enum POINTER_mode { POINTER_UNDEF = -1, POINTER_OFF = 0, POINTER_ON = 1, POINTER_MENU = 2, POINTER_APPLICATION = 3, POINTER_RESTORE_LESS = 4 }; +enum POINTER_state { POINTER_S_UNDEF = -1, POINTER_S_DISABLED = 0, POINTER_S_ENABLED = 1 }; + +/* Exported defines ----------------------------------------------------------*/ +#define POINTER_WIDTH 7 + +typedef struct + { + s16 xPos ; + s16 yPos ; + s16 shift_PosX ; + s16 shift_PosY ; + s16 X_PosMin ; + s16 Y_PosMin ; + s16 X_PosMax ; + s16 Y_PosMax ; + } tPointer_Info; + +extern tPointer_Info POINTER_Info ; + +/* Exported vars -------------------------------------------------------------*/ +extern unsigned char *BallPointerBmpSize; +extern unsigned char BallPointerBmp [POINTER_WIDTH], *CurrentPointerBmp,*CurrentPointerSize; +extern u16 CurrentPointerColor; +extern u16 BallColor; +extern s16 POINTER_X_PosMin; +extern s16 POINTER_Y_PosMin; +extern s16 POINTER_X_PosMax; +extern s16 POINTER_Y_PosMax; +extern unsigned char PointerAreaStore [2*POINTER_WIDTH*POINTER_WIDTH]; + +/* Exported functions --------------------------------------------------------*/ +extern void POINTER_Init ( void ) ; +void POINTER_Handler(void); +u16 POINTER_GetCurrentAngleStart ( void ); +void POINTER_SetCurrentAngleStart ( u16 ); +u16 POINTER_GetCurrentSpeedOnAngle ( void ); +void POINTER_SetCurrentSpeedOnAngle ( u16 newspeed ); +void POINTER_SetMode( enum POINTER_mode mode); +void POINTER_SetCurrentPointer( unsigned char width, unsigned char height, unsigned char *bmp); +enum POINTER_state POINTER_GetState(void); +void POINTER_Draw (u8 Line, u8 Column, u8 Width, u8 Height, u8 *Bmp); +void POINTER_SetRect ( s16 x, s16 y, s16 width, s16 height ); //Restrict the move of the pointer to a rectangle +void POINTER_SetRectScreen ( void ); //Remove any space restriction for the pointer moves. +void POINTER_Save (u8 Line, u8 Column, u8 Width, u8 Height); +void POINTER_Restore (u8 Line, u8 Column, u8 Width, u8 Height); +u16 POINTER_GetPos(void); //Return the poistion of the cursor (x=lower byte, y = upperbyte) +void POINTER_SetPos ( u16 x, u16 y ); +typedef void (*tAppPtrMgr) ( int , int ); +void POINTER_SetApplication_Pointer_Mgr( tAppPtrMgr mgr ); +tPointer_Info* POINTER_GetInfo ( void ); +u16 POINTER_GetColor ( void ) ; +void POINTER_SetColor ( u16 color ); +enum POINTER_mode POINTER_GetMode( void ); +void POINTER_SetCurrentAreaStore ( u8 *ptr ); +void LCD_SetRotateScreen ( u8 RotateScreen); +u8 LCD_GetRotateScreen (); +void LCD_SetScreenOrientation (Rotate_H12_V_Match_TypeDef ScreenOrientation); +Rotate_H12_V_Match_TypeDef LCD_GetScreenOrientation (); + +//---------------------------------- LCD ----------------------------------- + +/* Exported defines ----------------------------------------------------------*/ +//RGB is 16-bit coded as G2G1G0B4 B3B2B1B0 R4R3R2R1 R0G5G4G3 +#define RGB_MAKE(xR,xG,xB) ( ( (xG&0x07)<<13 ) + ( (xG)>>5 ) + \ + ( ((xB)>>3) << 8 ) + \ + ( ((xR)>>3) << 3 ) ) +#define RGB_RED 0x00F8 +#define RGB_BLACK 0x0000 +#define RGB_WHITE 0xffff +#define RGB_BLUE 0x1F00 +#define RGB_GREEN 0xE007 +#define RGB_YELLOW (RGB_GREEN|RGB_RED) +#define RGB_MAGENTA (RGB_BLUE|RGB_RED) +#define RGB_LIGHTBLUE (RGB_BLUE|RGB_GREEN) +#define RGB_ORANGE (RGB_RED | 0xE001) //green/2 + red +#define RGB_PINK (RGB_MAGENTA | 0xE001) //green/2 + magenta + +// SCREEN Infos +#define SCREEN_WIDTH 128 +#define SCREEN_HEIGHT 128 +#define CHIP_SCREEN_WIDTH 132 +#define CHIP_SCREEN_HEIGHT 132 + +// Characters Infos +#define CHAR_WIDTH 7 +#define CHAR_HEIGHT 14 + +// PWM rates. +#define BACKLIGHTMIN 0x1000 /*!< Minimal PWM rate. */ +#define DEFAULT_CCR_BACKLIGHTSTART 0x8000 /*!< Default PWM rate. */ + +/* Exported vars -------------------------------------------------------------*/ +extern Rotate_H12_V_Match_TypeDef Screen_Orientation; +extern int rotate_screen; + +/* Exported functions --------------------------------------------------------*/ +void LCD_Init(void); +void LCD_Handler(void); +void LCD_SetRect_For_Cmd( s16 x, s16 y, s16 width, s16 height ); +u16 LCD_GetPixel( u8 x, u8 y ); +void LCD_DrawPixel( u8 x, u8 y, u16 Pixel ); +void LCD_SendLCDCmd( u8 Cmd ); +void LCD_SendLCDData( u8 Data ); +u32 LCD_ReadLCDData( void ); +void LCD_FillRect( u16 x, u16 y, u16 width, u16 height, u16 color ); +void LCD_DrawRect( u16 x, u16 y, u16 width, u16 height, u16 color ); +void LCD_DisplayChar( u8 x, u8 y, u8 Ascii, u16 TextColor, u16 BGndColor, u16 CharMagniCoeff ); +void LCD_RectRead( u16 x, u16 y, u16 width, u16 height, u8* bmp ); +void LCD_SetBackLight (u32 newBacklightStart); +u32 LCD_GetBackLight ( void ); +void LCD_SetBackLightOff( void ); +void LCD_SetBackLightOn( void ); + +#include "lcd.h" + +//---------------------------------- DRAW ---------------------------------- + +/* Exported functions --------------------------------------------------------*/ +void DRAW_Init(void); +void DRAW_Clear(void); +void DRAW_Handler(void); +void DRAW_SetDefaultColor (void); +void DRAW_SetImage(const u16 *imageptr, u8 x, u8 y, u8 width, u8 height); +void DRAW_SetImageBW(const u8 *imageptr, u8 x, u8 y, u8 width, u8 height); +void DRAW_SetLogoBW(void); +void DRAW_DisplayVbat(u8 x, u8 y); +void DRAW_DisplayTime(u8 x, u8 y); +void DRAW_DisplayTemp(u8 x, u8 y); +void DRAW_DisplayString( u8 x, u8 y, const u8 *ptr, u8 len ); +void DRAW_DisplayStringInverted( u8 x, u8 y, const u8 *ptr, u8 len ); +u16 DRAW_GetCharMagniCoeff(void); +void DRAW_SetCharMagniCoeff(u16 Coeff); +u16 DRAW_GetTextColor(void); +void DRAW_SetTextColor(u16 Color); +u16 DRAW_GetBGndColor(void); +void DRAW_SetBGndColor(u16 Color); +void DRAW_Batt( void ); +void DRAW_Line (s16 x1, s16 y1, s16 x2, s16 y2, u16 color ); + +/* Exported vars -------------------------------------------------------------*/ +extern int fDisplayTime; + + +//-------------------------------- BUZZER ----------------------------------- + +/* Exported defines ----------------------------------------------------------*/ +#define BUZZER_BEEP BUZZER_SHORTBEEP + +/* Exported type def ---------------------------------------------------------*/ +enum BUZZER_mode { BUZZER_UNDEF = -1, BUZZER_OFF = 0, BUZZER_ON = 1, + BUZZER_SHORTBEEP = 2, BUZZER_LONGBEEP = 3, BUZZER_PLAYMUSIC = 4 }; + +/* Exported type functions ---------------------------------------------------*/ +void BUZZER_Init(void); +void BUZZER_Handler(void); +void BUZZER_SetMode( enum BUZZER_mode mode); +enum BUZZER_mode BUZZER_GetMode( void ); +void BUZZER_PlayMusic (const u8 *melody ); + +//--------------------------------- MENU ----------------------------------- + +/* Exported defines ----------------------------------------------------------*/ +#define MENU_MAXITEM 6 +#define APP_VOID ((tMenuItem *)(-1)) +#define MAX_APP_MENU_SIZE 10 +#define MAXAPP 64 +#define MAX_MENUAPP_SIZE 3 +#define REMOVE_MENU 0x01 +#define APP_MENU 0x02 + +enum MENU_code { MENU_LEAVE = 0, MENU_CONTINUE = 1, MENU_REFRESH = 2, + MENU_CHANGE = 3, MENU_CONTINUE_COMMAND = 4}; + +/* Exported type def ---------------------------------------------------------*/ +typedef struct + { + const char *Text; + enum MENU_code (*Fct_Init) ( void ); + enum MENU_code (*Fct_Manage)( void ); + int fMenuFlag; + } tMenuItem; + +typedef struct + { + unsigned fdispTitle : 1; + const char *Title; + int NbItems; + int LgMax; + int XPos, YPos; + int XSize, YSize; + unsigned int SelectedItem; + tMenuItem Items[MENU_MAXITEM]; + } tMenu; + +/* Exported vars -------------------------------------------------------------*/ +extern tMenu MainMenu, *CurrentMenu; +extern tMenuItem *CurrentCommand; +extern int BGndColor_Menu; +extern int TextColor_Menu; + +/* Exported type functions ---------------------------------------------------*/ +enum MENU_code fColor ( void ) ; +void MENU_Set ( tMenu *mptr ); +void MENU_Handler ( void ) ; +extern enum MENU_code MENU_Quit ( void ); +void MENU_Remove ( void ) ; +void MENU_Question ( char *str, int *answer ); +void MENU_Print ( char *str ); +enum MENU_code MENU_SetLevel_Ini( void ); +enum MENU_code MENU_SetLevel_Mgr( u32 *value, u32 value_range [] ) ; +void MENU_ClearCurrentCommand( void ); +void MENU_SetLevelTitle(u8* title); +void MENU_SetTextColor ( int TextColor ); +int MENU_GetTextColor ( void ); +void MENU_SetBGndColor ( int BGndColor ); +int MENU_GetBGndColor ( void ); +extern enum MENU_code fQuit ( void ) ; +void MENU_ClearCurrentMenu(void); + +//-------------------------------- BACKLIGHT -------------------------------- + +/* Exported type functions ---------------------------------------------------*/ +void BackLight_Configuration (void); +void ManageBackLight (void); +void BackLight_Change (void); + +//-------------------------------- RTC -------------------------------------- + +/* Exported type functions ---------------------------------------------------*/ +void RTC_Init(void); +void RTC_SetTime (u32 THH, u32 TMM, u32 TSS); +void RTC_GetTime (u32 * THH, u32 * TMM, u32 * TSS); +void RTC_DisplayTime ( void ); + +//Backup registers +#define BKP_SYS1 1 +#define BKP_SYS2 2 +#define BKP_SYS3 3 +#define BKP_SYS4 4 +#define BKP_SYS5 5 +#define BKP_SYS6 6 +#define BKP_USER1 7 +#define BKP_USER2 8 +#define BKP_USER3 9 +#define BKP_USER4 10 + +#define BKP_PLL (BKP_SYS2) +#define BKP_BKLIGHT (BKP_SYS3) + +//--------------------------------- Application -------------------------------- +void (*Application_Pointer_Mgr) ( int sposX, int sposY); + +#endif /*__CIRCLE_H */ diff --git a/20080212/Demo/CORTEX_STM32F103_Primer_GCC/ST_Code/circle_api.h b/20080212/Demo/CORTEX_STM32F103_Primer_GCC/ST_Code/circle_api.h new file mode 100644 index 000000000..f3cdb8f77 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_Primer_GCC/ST_Code/circle_api.h @@ -0,0 +1,679 @@ +/********************* (C) COPYRIGHT 2007 RAISONANCE S.A.S. *******************/ +/** +* +* @file circle_api.h +* @brief General header for the STM32-circle projects. +* @author FL +* @date 07/2007 +* @version 1.2 +* @date 10/2007 +* @version 1.5 types of OutX_F64 and OutX_F256 changed to u32 (same for Y and Z) +* @date 10/2007 +* @version 1.6 Add the IRQ handler replacement +* +* It contains the list of the utilities functions organized by sections +* (MEMS, LCD, POINTER, ...) +* +**/ +/******************************************************************************* +* +* Use this header with version 1.5 or later of the OS. +* +* For a complete documentation on the CircleOS, please go to: +* http://www.stm32circle.com +* +*******************************************************************************/ + +#include "stm32f10x_lib.h" + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CIRCLE_API_H +#define __CIRCLE_API_H + +//-------------------------------- General ------------------------------------- + +/** +* @enum eSpeed +* @brief Clock speeds. +* +* Available clock speeds. +**/ +extern enum eSpeed + { + SPEED_VERY_LOW = 1, + SPEED_LOW = 2, + SPEED_MEDIUM = 3, + SPEED_HIGH = 4, + SPEED_VERY_HIGH = 5 + } CurrentSpeed; +enum eSchHandler + { + LED_SCHHDL_ID = 0, + BUTTON_SCHHDL_ID = 1, + BUZZER_SCHHDL_ID = 2, + MENU_SCHHDL_ID = 3, + POINTER_SCHHDL_ID = 4, + LCD_SCHHDL_ID = 5, + DRAW_SCHHDL_ID = 6, + RTC_SCHHDL_ID = 7, + + UNUSED0_SCHHDL_ID = 8, + UNUSED1_SCHHDL_ID = 9, + UNUSED2_SCHHDL_ID = 10, + UNUSED3_SCHHDL_ID = 11, + UNUSED4_SCHHDL_ID = 12, + UNUSED5_SCHHDL_ID = 13, + UNUSED6_SCHHDL_ID = 14, + UNUSED7_SCHHDL_ID = 15 + }; + + +/// @cond Internal + +extern RCC_ClocksTypeDef RCC_ClockFreq; + +/* Typedefs ------------------------------------------------------------------*/ +typedef u32 (*tCircleFunc0 ) (void); +typedef u32 (*tCircleFunc1 ) (u32 param1); +typedef u32 (*tCircleFunc2 ) (u32 param1, u32 param2); +typedef u32 (*tCircleFunc3 ) (u32 param1, u32 param2, u32 param3); +typedef u32 (*tCircleFunc4 ) (u32 param1, u32 param2, u32 param3, u32 param4); +typedef u32 (*tCircleFunc5 ) (u32 param1, u32 param2, u32 param3, u32 param4, u32 param5); +typedef u32 (*tCircleFunc6 ) (u32 param1, u32 param2, u32 param3, u32 param4, u32 param5, u32 param6); + +extern tCircleFunc0 (*ptrCircle_API) []; + +/* Defines -------------------------------------------------------------------*/ +#define Circle_API (*ptrCircle_API) + +#define POINTER_ID 0x00 +#define DRAW_ID 0x20 +#define LCD_ID 0x40 +#define LED_ID 0x60 +#define MEMS_ID 0x70 +#define BUTTON_ID 0x80 +#define BUZZER_ID 0x90 +#define MENU_ID 0xA0 +#define UTIL_ID 0xB0 +#define RTC_ID 0xC0 + +// UTIL functions definition. +#define UTIL_SET_PLL_ID (UTIL_ID + 0) // Set clock frequency. +#define UTIL_GET_PLL_ID (UTIL_ID + 1) // Get clock frequency. +#define UTIL_UINT2STR_ID (UTIL_ID + 2) // Convert an unsigned integer into a string. +#define UTIL_INT2STR_ID (UTIL_ID + 3) // Convert a signed integer into a string. +#define UTIL_GET_VERSION_ID (UTIL_ID + 4) // Get CircleOS version. +#define UTIL_READ_BACKUPREGISTER_ID (UTIL_ID + 5) // Reads data from the specified Data Backup Register. +#define UTIL_WRITE_BACKUPREGISTER_ID (UTIL_ID + 6) // Writes data to the specified Data Backup Register. +#define UTIL_GET_BAT_ID (UTIL_ID + 7) // Return the batterie tension in mV. +#define UTIL_GET_USB_ID (UTIL_ID + 8) // Return the USB connexion state. +#define UTIL_SET_IRQ_HANDLER_ID (UTIL_ID + 9) // Replace an irq handler +#define UTIL_GET_IRQ_HANDLER_ID (UTIL_ID + 10) // Get the current irq handler +#define UTIL_SET_SCH_HANDLER_ID (UTIL_ID + 11) // Replace an irq handler +#define UTIL_GET_SCH_HANDLER_ID (UTIL_ID + 12) // Get the current irq handler +#define UTIL_GET_TEMP_ID (UTIL_ID + 13) // Return the temperature (1/100 C) +#define UTIL_SET_TEMPMODE_ID (UTIL_ID + 14) // Set the temperature mode (0: mCelcius, 1: mFahrenheit +typedef void (*tHandler) (void); + +// Prototypes. +#define UTIL_SetPll(a) ((tCircleFunc1)(Circle_API [UTIL_SET_PLL_ID])) ((u32)(a)) // void UTIL_SetPll( enum eSpeed speed ); +#define UTIL_GetPll() (u32) (((tCircleFunc0)(Circle_API [UTIL_GET_PLL_ID])) ()) // enum eSpeed UTIL_GetPll( void ); +#define UTIL_uint2str(a,b,c,d) ((tCircleFunc4)(Circle_API [UTIL_UINT2STR_ID])) ((u32)(a),(u32)(b),(u32)(c),(u32)(d)) // void uint2str( char* ptr , u32 X, u16 digit, int fillwithzero ); +#define UTIL_int2str(a,b,c,d) ((tCircleFunc4)(Circle_API [UTIL_INT2STR_ID])) ((u32)(a),(u32)(b),(u32)(c),(u32)(d)) // void int2str( char* ptr , s32 X, u16 digit, int fillwithzero ); +#define UTIL_GetVersion() (u32) (((tCircleFunc0)(Circle_API [UTIL_GET_VERSION_ID])) ()) // char* UTIL_GetVersion( void ); +#define UTIL_ReadBackupRegister(a) (u32) (((tCircleFunc1)(Circle_API [UTIL_READ_BACKUPREGISTER_ID])) ((u32)(a))) // u16 UTIL_ReadBackupRegister( u16 BKP_DR ); +#define UTIL_WriteBackupRegister(a,b) ((tCircleFunc2)(Circle_API [UTIL_WRITE_BACKUPREGISTER_ID])) ((u32)(a),(u32)(b)) // void UTIL_WriteBackupRegister( u16 BKP_DR, u16 Data ); +#define UTIL_GetBat() (u32) (((tCircleFunc0)(Circle_API [UTIL_GET_BAT_ID])) ()) // u16 UTIL_GetBat( void ); +#define UTIL_GetUsb() (u32) (((tCircleFunc0)(Circle_API [UTIL_GET_USB_ID])) ()) // u8 UTIL_GetUsb( void ); +#define UTIL_SetIrqHandler(a,b) (((tCircleFunc2)(Circle_API [UTIL_SET_IRQ_HANDLER_ID])) ((int)a,(tHandler)b)) // void UTIL_SetIrqHandler ( int , tHandler ); +#define UTIL_GetIrqHandler(a) (u32) (((tCircleFunc1)(Circle_API [UTIL_GET_IRQ_HANDLER_ID])) ((int)a)) // tHandler* UTIL_GetIrqHandler ( int ); +#define UTIL_SetSchHandler(a,b) (((tCircleFunc2)(Circle_API [UTIL_SET_SCH_HANDLER_ID])) ((int)a,(tHandler)b)) // void UTIL_SetSchHandler ( int , tHandler ); +#define UTIL_GetSchHandler(a) (u32) (((tCircleFunc1)(Circle_API [UTIL_GET_SCH_HANDLER_ID])) ((int)a)) // tHandler* UTIL_GetSchHandler ( int ); +#define UTIL_GetTemp() (u32) (((tCircleFunc0)(Circle_API [UTIL_GET_TEMP_ID])) ()) // u16 UTIL_GetTemp( void ); +#define UTIL_SetTempMode(a) (((tCircleFunc1)(Circle_API [UTIL_SET_TEMPMODE_ID])) ((int)a)) // void UTIL_SetTempMode( int mode ); + +/// @endcond + +//--------------------------------- MEMS ------------------------------------ + +/* Exported types ------------------------------------------------------------*/ + +/** +* @enum Rotate_H12_V_Match_TypeDef +* @brief The 4 possible rotations. +* +* The 4 possible MEM rotations. +**/ +typedef enum + { + V12 = 0, /*!< No rotation. */ + V3 = 1, /*!< Rotation to the right.*/ + V6 = 2, /*!< Rotation to the left. */ + V9 = 3 /*!< Half a rotation. */ + } Rotate_H12_V_Match_TypeDef; + +/** +* @struct tMEMS_Info +* @brief MEMS state description. +**/ +typedef struct + { + s16 OutX; /*!< MEMS X position. */ + s16 OutX_F4; /*!< MEMS X position filtered on 4 values. */ + s16 OutX_F16; /*!< MEMS X position filtered on 16 values. */ + s32 OutX_F64; /*!< MEMS X position filtered on 64 values. */ + s32 OutX_F256; /*!< MEMS X position filtered on 256 values. */ + s16 OutY; /*!< MEMS Y position. */ + s16 OutY_F4; /*!< MEMS Y position filtered on 4 values. */ + s16 OutY_F16; /*!< MEMS Y position filtered on 16 values. */ + s32 OutY_F64; /*!< MEMS Y position filtered on 64 values. */ + s32 OutY_F256; /*!< MEMS Y position filtered on 256 values. */ + s16 OutZ; /*!< MEMS Z position. */ + s16 OutZ_F4; /*!< MEMS Z position filtered on 4 values. */ + s16 OutZ_F16; /*!< MEMS Z position filtered on 16 values. */ + s32 OutZ_F64; /*!< MEMS Z position filtered on 64 values. */ + s32 OutZ_F256; /*!< MEMS Z position filtered on 256 values. */ + s16 Shocked; /*!< MEMS shock counter (incremented...) */ + s16 RELATIVE_X; /*!< MEMS relative X position. */ + s16 RELATIVE_Y; /*!< MEMS relative Y position. */ + s16 DoubleClick; /*!< MEMS DoubleClick counter(incremented...)*/ + } tMEMS_Info; + +/// @cond Internal + +/* Exported defines ----------------------------------------------------------*/ + +// MEMS functions definition +#define MEMS_GET_POSITION_ID (MEMS_ID + 0) // Return the current (relative) Mems information +#define MEMS_GET_ROTATION_ID (MEMS_ID + 1) // Return the current screen orientation of the circle +#define MEMS_SET_NEUTRAL_ID (MEMS_ID + 2) // Set the current position as "neutral position" +#define MEMS_GET_INFO_ID (MEMS_ID + 3) // Return Mems informations + +// Prototypes +#define MEMS_GetPosition(a,b) ((tCircleFunc2)(Circle_API [MEMS_GET_POSITION_ID])) ((u32)(a),(u32)(b)) // void MEMS_GetPosition(s16 * pX, s16* pY); +#define MEMS_GetRotation(a) ((tCircleFunc1)(Circle_API [MEMS_GET_ROTATION_ID])) ((u32)(a)) // void MEMS_GetRotation(Rotate_H12_V_Match_TypeDef * H12); +#define MEMS_SetNeutral() ((tCircleFunc0)(Circle_API [MEMS_GET_ROTATION_ID])) () // void MEMS_SetNeutral( void ); +#define MEMS_GetInfo() ( (tMEMS_Info*) (((tCircleFunc0)(Circle_API [MEMS_GET_INFO_ID])) ())) // tMEMS_Info* MEMS_GetInfo (void) + +/// @endcond + +//-------------------------------- POINTER ---------------------------------- + +/* Exported types ------------------------------------------------------------*/ + +/** +* @enum POINTER_mode +* @brief Available pointer modes. +* +* Description of all the available pointer modes in CircleOS. +**/ +enum POINTER_mode + { + POINTER_UNDEF = -1, /*!< Pointer's mode is unknown! */ + POINTER_OFF = 0, /*!< Pointer isn't managed and displayed. */ + POINTER_ON = 1, /*!< Pointer mode used in main screen. */ + POINTER_MENU = 2, /*!< Pointer management is used to select item menu (but pointer isn't displayed). */ + POINTER_APPLICATION = 3, /*!< The managment of pointer depend of extern application. */ + POINTER_RESTORE_LESS = 4 /*!< The background isn't restored (to go faster). */ + }; + +/** +* @enum POINTER_state +* @brief The different pointer modes. +* +* Despite beeing in a undefined state, the pointer can be disabled or enable. +**/ +enum POINTER_state + { + POINTER_S_UNDEF = -1, /*!< Pointer state is unknown! */ + POINTER_S_DISABLED = 0, /*!< Pointer is disabled. */ + POINTER_S_ENABLED = 1 /*!< Pointer is enabled. */ + }; + +/** +* @struct tPointer_Info +* @brief Pointer position description. +**/ +typedef struct + { + s16 xPos; /*!< X position of pointer. */ + s16 yPos; /*!< Y position of pointer. */ + s16 shift_PosX; /*!< Pointer speed on X axis. */ + s16 shift_PosY; /*!< Pointer speed on Y axis */ + s16 X_PosMin; /*!< Minimum position on X axis. */ + s16 Y_PosMin; /*!< Minimum position on Y axis. */ + s16 X_PosMax; /*!< Maximum position on X axis. */ + s16 Y_PosMax; /*!< Maximum position on Y axis. */ + } tPointer_Info; + +/// @cond Internal + +/* Exported defines ---------------------------------------------------------*/ +#define POINTER_WIDTH 7 + +// POINTER functions definition +#define POINTER_SET_RECT_ID (POINTER_ID + 0) // Set new limits for the move of the pointer +#define POINTER_SETRECTSCREEN_ID (POINTER_ID + 1) // Remove any space restriction for the pointer moves. +#define POINTER_GETCURRENTANGLESTART_ID (POINTER_ID + 2) // Return the current minimum angle to move pointer +#define POINTER_SETCURRENTANGLESTART_ID (POINTER_ID + 3) // Set the current minimum angle to move pointer +#define POINTER_GETCURRENTSPEEDONANGLE_ID (POINTER_ID + 4) // Return the ratio speed / angle +#define POINTER_SETCURRENTSPEEDONANGLE_ID (POINTER_ID + 5) // Set the ratio speed / angle +#define POINTER_SETMODE_ID (POINTER_ID + 6) // Change the current mode of the pointer management +#define POINTER_GETMODE_ID (POINTER_ID + 7) // Return the current mode of the pointer management +#define POINTER_SETCURRENTPOINTER_ID (POINTER_ID + 8) // Set the dimention and bitmap of pointer +#define POINTER_GETSTATE_ID (POINTER_ID + 9) // Return the current state +#define POINTER_DRAW_ID (POINTER_ID + 10) // Draw a pointer +#define POINTER_SAVE_ID (POINTER_ID + 11) // Save the background of the pointer +#define POINTER_RESTORE_ID (POINTER_ID + 12) // Restore the background of the pointer +#define POINTER_GETPOSITION_ID (POINTER_ID + 13) // Return the poistion of the cursor (x=lower byte, y = upperbyte) +#define POINTER_SETPOSITION_ID (POINTER_ID + 14) // Force the position of the pointer in the screen +#define POINTER_SETAPPLICATION_POINTER_MGR_ID (POINTER_ID + 15) // Set the application pointer manager +#define POINTER_SETCOLOR_ID (POINTER_ID + 16) // Set pointer color +#define POINTER_GETCOLOR_ID (POINTER_ID + 17) // Return pointer color +#define POINTER_GETINFO_ID (POINTER_ID + 18) // Return pointer informations +#define POINTER_SET_CURRENT_AREASTORE_ID (POINTER_ID + 19) // Change the current storage area + +// Prototypes +#define POINTER_SetRect(a,b,c,d) ((tCircleFunc4)(Circle_API [POINTER_SET_RECT_ID])) ((u32)(a),(u32)(b),(u32)(c),(u32)(d)) //void POINTER_SetRect ( s16 x, s16 y, s16 width, s16 height ); //Restrict the move of the pointer to a rectangle +#define POINTER_SetRectScreen() ((tCircleFunc0)(Circle_API [POINTER_SETRECTSCREEN_ID])) () //void POINTER_SetRectScreen ( void ); +#define POINTER_GetCurrentAngleStart() (u16) (((tCircleFunc0)(Circle_API [POINTER_GETCURRENTANGLESTART_ID])) ()) //u16 POINTER_GetCurrentAngleStart ( void ); +#define POINTER_SetCurrentAngleStart(a) ((tCircleFunc1)(Circle_API [POINTER_SETCURRENTANGLESTART_ID])) ((u32)(a)) //void POINTER_SetCurrentAngleStart ( u16 ); +#define POINTER_GetCurrentSpeedOnAngle() (u16) (((tCircleFunc0)(Circle_API [POINTER_GETCURRENTSPEEDONANGLE_ID])) ()) //u16 POINTER_GetCurrentSpeedOnAngle ( void ); +#define POINTER_SetCurrentSpeedOnAngle(a) ((tCircleFunc1)(Circle_API [POINTER_SETCURRENTSPEEDONANGLE_ID])) ((u32)(a)) //void POINTER_SetCurrentSpeedOnAngle ( u16 newspeed ); +#define POINTER_SetMode(a) ((tCircleFunc1)(Circle_API [POINTER_SETMODE_ID])) ((u32)(a)) //void POINTER_SetMode( enum POINTER_mode mode); +#define POINTER_GetMode() (enum POINTER_mode) (((tCircleFunc0)(Circle_API [POINTER_GETMODE_ID])) ()) //enum POINTER_mode POINTER_GetMode( void ); +#define POINTER_SetCurrentPointer(a,b,c) ((tCircleFunc3)(Circle_API [POINTER_SETCURRENTPOINTER_ID])) ((u32)(a),(u32)(b),(u32)(c)) //void POINTER_SetCurrentPointer( unsigned char width, unsigned char height, unsigned char *bmp); +#define POINTER_GetState() (enum POINTER_state) (((tCircleFunc0)(Circle_API [POINTER_GETSTATE_ID])) ()) //enum POINTER_state POINTER_GetState(void); +#define POINTER_Draw(a,b,c,d,e) ((tCircleFunc5)(Circle_API [POINTER_DRAW_ID])) ((u32)(a),(u32)(b),(u32)(c),(u32)(d),(u32)(e)) //void POINTER_Draw (u8 Line, u8 Column, u8 Width, u8 Height, u8 *Bmp); +#define POINTER_Save(a,b,c,d) ((tCircleFunc4)(Circle_API [POINTER_SAVE_ID])) ((u32)(a),(u32)(b),(u32)(c),(u32)(d)) //void POINTER_Save (u8 Line, u8 Column, u8 Width, u8 Height); +#define POINTER_Restore(a,b,c,d) ((tCircleFunc4)(Circle_API [POINTER_RESTORE_ID])) ((u32)(a),(u32)(b),(u32)(c),(u32)(d)) //void POINTER_Restore (u8 Line, u8 Column, u8 Width, u8 Height); +#define POINTER_GetPos() (u16) (((tCircleFunc0)(Circle_API [POINTER_GETPOSITION_ID])) ()) //u16 POINTER_GetPos(void); +#define POINTER_SetPos(a,b) ((tCircleFunc2)(Circle_API [POINTER_SETPOSITION_ID])) ((u32)(a),(u32)(b)) //void POINTER_SetPos ( u16 x, u16 y ); +#define POINTER_SetApplication_Pointer_Mgr(a) ((tCircleFunc1)(Circle_API [POINTER_SETAPPLICATION_POINTER_MGR_ID])) ((u32)(a)) //void POINTER_SetApplication_Pointer_Mgr( tAppPtrMgr mgr ); +#define POINTER_SetColor(a) ((tCircleFunc1)(Circle_API [POINTER_SETCOLOR_ID])) ((u32)(a)) //void POINTER_SetColor ( u16 color ) +#define POINTER_GetColor() (u16) (((tCircleFunc0)(Circle_API [POINTER_GETCOLOR_ID])) ()) //u16 POINTER_GetColor ( void ) +#define POINTER_GetInfo() (tPointer_Info*) (((tCircleFunc0)(Circle_API [POINTER_GETINFO_ID])) ()) //tPointer_Info* POINTER_GetInfo ( void ) +#define POINTER_SetCurrentAreaStore(a) ((tCircleFunc1)(Circle_API [POINTER_SET_CURRENT_AREASTORE_ID])) ((u32)(a)) //void POINTER_SetCurrentAreaStore ( u8 *ptr ) + +/// @endcond + +//-------------------------------- BUTTON ----------------------------------- + +/* Exported types ------------------------------------------------------------*/ + +/** +* @enum BUTTON_mode +* @brief Available button modes. +* +* List of all the available button mode in the CircleOS. +**/ +enum BUTTON_mode + { + BUTTON_DISABLED = -1, /*!< No action on the button is detected. */ + BUTTON_ONOFF = 0, /*!< Detect ON/OFF pression type. */ + BUTTON_ONOFF_FORMAIN = 1, /*!< Special mode for main screen. */ + BUTTON_WITHCLICK = 2 /*!< Currently unused. */ + }; + +/** +* @enum BUTTON_state +* @brief CircleOS button states. +* +* Description of the button states provided by CircleOS. +**/ +enum BUTTON_state + { + BUTTON_UNDEF = -1, /*!< Undefined state. */ + BUTTON_RELEASED = 0, /*!< Button is released. */ + BUTTON_PUSHED = 1, /*!< Button was just pushed. */ + BUTTON_PUSHED_FORMAIN = 2, /*!< Same as BUTTON_PUSHED when button mode is BUTTON_ONOFF_FORMAIN. */ + BUTTON_CLICK = 3, /*!< Currently unused. */ + BUTTON_DBLCLICK = 4 /*!< Currently unused. */ + }; + +/// @cond Internal + +/* Exported defines ----------------------------------------------------------*/ + +// BUTTON functions definition +#define BUTTON_GETSTATE_ID (BUTTON_ID + 0) // Return state of button +#define BUTTON_SETMODE_ID (BUTTON_ID + 1) // Set button mode +#define BUTTON_GETMODE_ID (BUTTON_ID + 2) // Return button mode +#define BUTTON_WAITFORRELEASE_ID (BUTTON_ID + 3) // Disable temporarily any new button event + +// Prototypes +#define BUTTON_GetState() (enum BUTTON_state) (((tCircleFunc0)(Circle_API [BUTTON_GETSTATE_ID])) ()) // enum BUTTON_state BUTTON_GetState(void); +#define BUTTON_SetMode(a); ((tCircleFunc1)(Circle_API [BUTTON_SETMODE_ID])) ((u32)(a)) // void BUTTON_SetMode( enum BUTTON_mode mode); +#define BUTTON_GetMode(); (enum BUTTON_mode) (((tCircleFunc0)(Circle_API [BUTTON_GETMODE_ID])) ()) // enum BUTTON_mode BUTTON_GetMode ( void ) ; +#define BUTTON_WaitForRelease() ((tCircleFunc0)(Circle_API [BUTTON_WAITFORRELEASE_ID])) () // void BUTTON_WaitForRelease(void); + +/// @endcond + +//---------------------------------- LCD ----------------------------------- + +/* Exported defines ----------------------------------------------------------*/ + +// RGB is 16-bit coded as G2G1G0B4 B3B2B1B0 R4R3R2R1 R0G5G4G3 +#define RGB_MAKE(xR,xG,xB) ( ( (xG&0x07)<<13 ) + ( (xG)>>5 ) + \ + ( ((xB)>>3) << 8 ) + \ + ( ((xR)>>3) << 3 ) ) /*!< Macro to make a LCD compatible color format from RGB. */ + +#define RGB_RED 0x00F8 /*!< Predefined color. */ +#define RGB_BLACK 0x0000 /*!< Predefined color. */ +#define RGB_WHITE 0xffff /*!< Predefined color. */ +#define RGB_BLUE 0x1F00 /*!< Predefined color. */ +#define RGB_GREEN 0xE007 /*!< Predefined color. */ +#define RGB_YELLOW (RGB_GREEN|RGB_RED) /*!< Predefined color. */ +#define RGB_MAGENTA (RGB_BLUE|RGB_RED) /*!< Predefined color. */ +#define RGB_LIGHTBLUE (RGB_BLUE|RGB_GREEN) /*!< Predefined color. */ +#define RGB_ORANGE (RGB_RED | 0xE001) /*!< Predefined color ( Green/2 + red ). */ +#define RGB_PINK (RGB_MAGENTA | 0xE001) /*!< Predefined color ( Green/2 + magenta ). */ + +// PWM rates. +#define BACKLIGHTMIN 0x1000 /*!< Minimal PWM rate. */ +#define DEFAULT_CCR_BACKLIGHTSTART 0x8000 /*!< Default PWM rate. */ + +// SCREEN Infos +#define SCREEN_WIDTH 128 /*!< Width of visible screen in pixels. */ +#define SCREEN_HEIGHT 128 /*!< Height of visible screen in pixels. */ +#define CHIP_SCREEN_WIDTH 132 /*!< Width of screen driven by LCD controller in pixels. */ +#define CHIP_SCREEN_HEIGHT 132 /*!< Height of screen driven by LCD controller in pixels. */ + +// Characters Infos +#define CHAR_WIDTH 7 /*!< Width of a character. */ +#define CHAR_HEIGHT 14 /*!< Height of a character. */ + +/// @cond Internal + +// LCD functions definition +#define LCD_SETRECTFORCMD_ID (LCD_ID + 0) // Define the rectangle (for the next command to be applied) +#define LCD_GETPIXEL_ID (LCD_ID + 1) // Read the value of one pixel +#define LCD_DRAWPIXEL_ID (LCD_ID + 2) // Draw a Graphic image on slave LCD. +#define LCD_SENDLCDCMD_ID (LCD_ID + 3) // Send one byte command to LCD LCD. +#define LCD_SENDLCDDATA_ID (LCD_ID + 4) // Display one byte data to LCD LCD. +#define LCD_READLCDDATA_ID (LCD_ID + 5) // Read LCD byte data displayed on LCD LCD. +#define LCD_FILLRECT_ID (LCD_ID + 6) // Fill a rectangle with one color +#define LCD_DRAWRECT_ID (LCD_ID + 7) // Draw a rectangle with one color +#define LCD_DISPLAYCHAR_ID (LCD_ID + 8) // Display one character +#define LCD_RECTREAD_ID (LCD_ID + 9) // Save a rectangle of the monitor RAM +#define LCD_SETBACKLIGHT_ID (LCD_ID + 10) // Modify the PWM rate +#define LCD_GETBACKLIGHT_ID (LCD_ID + 11) // Return the PWM rate +#define LCD_SETROTATESCREEN_ID (LCD_ID + 12) // Enable/Disable screen rotation +#define LCD_GETROTATESCREEN_ID (LCD_ID + 13) // Return screen rotation mode +#define LCD_SETSCREENORIENTATION_ID (LCD_ID + 14) // Set screen orientation +#define LCD_GETSCREENORIENTATION_ID (LCD_ID + 15) // Return screen orientation +#define LCD_SETBACKLIGHT_OFF_ID (LCD_ID + 16) // Switch the LCD back light off. +#define LCD_SETBACKLIGHT_ON_ID (LCD_ID + 17) // Switch the LCD back light on. + +// Prototypes +#define LCD_SetRect_For_Cmd(a,b,c,d) ((tCircleFunc4)(Circle_API [LCD_SETRECTFORCMD_ID])) ((u32)(a),(u32)(b),(u32)(c),(u32)(d)) //void LCD_SetRect_For_Cmd ( s16 x, s16 y, s16 width, s16 height) +#define LCD_GetPixel(a,b) (u16) (((tCircleFunc2)(Circle_API [LCD_GETPIXEL_ID])) ((u32)(a),(u32)(b))) //u16 LCD_GetPixel (u8 x, u8 y) +#define LCD_DrawPixel(a,b,c) ((tCircleFunc3)(Circle_API [LCD_DRAWPIXEL_ID])) ((u32)(a),(u32)(b),(u32)(c)) //void LCD_SetPixel (u8 x, u8 y, u16 Pixel) ; +#define LCD_SendLCDCmd(a) ((tCircleFunc1)(Circle_API [LCD_SENDLCDCMD_ID])) ((u32)(a)) //void LCD_SendLCDCmd(u8 Cmd); +#define LCD_SendLCDData(a) ((tCircleFunc1)(Circle_API [LCD_SENDLCDDATA_ID])) ((u32)(a)) //void LCD_SendLCDData(u8 Data); +#define LCD_ReadLCDData() (u32) (((tCircleFunc0)(Circle_API [LCD_READLCDDATA_ID])) ()) //u32 LCD_ReadLCDData(void); +#define LCD_FillRect(a,b,c,d,e) ((tCircleFunc5)(Circle_API [LCD_FILLRECT_ID])) ((u32)(a),(u32)(b),(u32)(c),(u32)(d),(u32)(e)) //void LCD_FillRect ( u16 x, u16 y, u16 width, u16 height, u16 color ); +#define LCD_DrawRect(a,b,c,d,e) ((tCircleFunc5)(Circle_API [LCD_DRAWRECT_ID])) ((u32)(a),(u32)(b),(u32)(c),(u32)(d),(u32)(e)) //void LCD_DrawRect ( u16 x, u16 y, u16 width, u16 height, u16 color ); +#define LCD_DisplayChar(a,b,c,d,e,f) ((tCircleFunc6)(Circle_API [LCD_DISPLAYCHAR_ID])) ((u32)(a),(u32)(b),(u32)(c),(u32)(d),(u32)(e),(u32)(f)) //void LCD_DisplayChar(u8 x, u8 y, u8 Ascii, u16 TextColor, u16 BGndColor, u16 CharMagniCoeff); +#define LCD_RectRead(a,b,c,d,e) ((tCircleFunc5)(Circle_API [LCD_RECTREAD_ID])) ((u32)(a),(u32)(b),(u32)(c),(u32)(d),(u32)(e)) //void LCD_RectRead ( u16 x, u16 y, u16 width, u16 height, u8* bmp ); +#define LCD_SetBackLight(a) ((tCircleFunc1)(Circle_API [LCD_SETBACKLIGHT_ID])) ((u32)(a)) //void LCD_SetBackLight(u32 newBaclightStart); +#define LCD_GetBackLight() (u32) (((tCircleFunc0)(Circle_API [LCD_GETBACKLIGHT_ID])) ()) //u32 LCD_GetBackLight(void); +#define LCD_SetRotateScreen(a) ((tCircleFunc1)(Circle_API [LCD_SETROTATESCREEN_ID])) ((u32)(a)) //void LCD_SetRotateScreen ( u8 RotateScreen) +#define LCD_GetRotateScreen() (u32) (((tCircleFunc0)(Circle_API [LCD_GETROTATESCREEN_ID])) ()) //u8 LCD_GetRotateScreen (void) +#define LCD_SetScreenOrientation(a) ((tCircleFunc1)(Circle_API [LCD_SETSCREENORIENTATION_ID])) ((u32)(a)) //void LCD_SetScreenOrientation (Rotate_H12_V_Match_TypeDef ScreenOrientation) +#define LCD_GetScreenOrientation() (u32) (((tCircleFunc0)(Circle_API [LCD_GETSCREENORIENTATION_ID])) ()) //Rotate_H12_V_Match_TypeDef LCD_GetScreenOrientation (void) +#define LCD_SetBackLightOff() ((tCircleFunc0)(Circle_API [LCD_SETBACKLIGHT_OFF_ID])) () +#define LCD_SetBackLightOn() ((tCircleFunc0)(Circle_API [LCD_SETBACKLIGHT_ON_ID])) () + +/// @endcond + +//---------------------------------- DRAW ---------------------------------- + +/// @cond Internal + +/* Exported defines ----------------------------------------------------------*/ + +// DRAW functions definition +#define DRAW_SETDEFAULTCOLOR_ID (DRAW_ID + 0) // Reset colors (bgnd + text) +#define DRAW_CLEAR_ID (DRAW_ID + 1) // Clear the LCD display +#define DRAW_SETIMAGE_ID (DRAW_ID + 2) // Draw a colored image +#define DRAW_SETIMAGEBW_ID (DRAW_ID + 3) // Draw a black and white image +#define DRAW_SETLOGOBW_ID (DRAW_ID + 4) // Draw logo +#define DRAW_DISPLAYVBAT_ID (DRAW_ID + 5) // Display the voltage of battery in ascii +#define DRAW_DISPLAYTIME_ID (DRAW_ID + 6) // Display time in ascii +#define DRAW_DISPLAYSTRING_ID (DRAW_ID + 7) // Display a 17char max string of characters +#define DRAW_DISPLAYSTRINGINVERTED_ID (DRAW_ID + 8) // Display a 17char max string of characters with inverted colors +#define DRAW_GETCHARMAGNICOEFF_ID (DRAW_ID + 9) // Return the magnifying value for the characters +#define DRAW_SETCHARMAGNICOEFF_ID (DRAW_ID + 10) // Set the magnifying value for the characters +#define DRAW_GETTEXTCOLOR_ID (DRAW_ID + 11) // Return the current text color +#define DRAW_SETTEXTCOLOR_ID (DRAW_ID + 12) // Set the current text color +#define DRAW_GETBGNDCOLOR_ID (DRAW_ID + 13) // Return the current background color +#define DRAW_SETBGNDCOLOR_ID (DRAW_ID + 14) // Set the current background color +#define DRAW_LINE_ID (DRAW_ID + 15) // Draw a Line between (using Bresenham algorithm) + +//Prototypes +#define DRAW_SetDefaultColor() ((tCircleFunc0)(Circle_API [DRAW_SETDEFAULTCOLOR_ID])) () //void DRAW_SetDefaultColor (void); +#define DRAW_Clear() ((tCircleFunc0)(Circle_API [DRAW_CLEAR_ID])) () //void DRAW_Clear(void); +#define DRAW_SetImage(a,b,c,d,e) ((tCircleFunc5)(Circle_API [DRAW_SETIMAGE_ID])) ((u32)(a),(u32)(b),(u32)(c),(u32)(d),(u32)(e)) //void DRAW_SetImage(const u16 *imageptr, u8 x, u8 y, u8 width, u8 height); +#define DRAW_SetImageBW(a,b,c,d,e) ((tCircleFunc5)(Circle_API [DRAW_SETIMAGEBW_ID])) ((u32)(a),(u32)(b),(u32)(c),(u32)(d),(u32)(e)) //void DRAW_SetImageBW(const u8 *imageptr, u8 x, u8 y, u8 width, u8 height); +#define DRAW_SetLogoBW() ((tCircleFunc0)(Circle_API [DRAW_SETLOGOBW_ID])) () //void DRAW_SetLogoBW(void); +#define DRAW_DisplayVbat(a,b) ((tCircleFunc2)(Circle_API [DRAW_DISPLAYVBAT_ID])) ((u32)(a),(u32)(b)) //void DRAW_DisplayVbat(u8 x, u8 y); +#define DRAW_DisplayTime(a,b) ((tCircleFunc2)(Circle_API [DRAW_DISPLAYTIME_ID])) ((u32)(a),(u32)(b)) //void DRAW_DisplayTime(u8 x, u8 y); +#define DRAW_DisplayString(a,b,c,d) ((tCircleFunc4)(Circle_API [DRAW_DISPLAYSTRING_ID])) ((u32)(a),(u32)(b),(u32)(c),(u32)(d)) //void DRAW_DisplayString( u8 x, u8 y, u8 *ptr, u8 len ); +#define DRAW_DisplayStringInverted(a,b,c,d) ((tCircleFunc4)(Circle_API [DRAW_DISPLAYSTRINGINVERTED_ID])) ((u32)(a),(u32)(b),(u32)(c),(u32)(d)) //void DRAW_DisplayStringInverted( u8 x, u8 y, u8 *ptr, u8 len ); +#define DRAW_GetCharMagniCoeff() (u16) (((tCircleFunc0)(Circle_API [DRAW_GETCHARMAGNICOEFF_ID])) ()) //u16 DRAW_GetCharMagniCoeff(void); +#define DRAW_SetCharMagniCoeff(a) ((tCircleFunc1)(Circle_API [DRAW_SETCHARMAGNICOEFF_ID])) ((u32)(a)) //void DRAW_SetCharMagniCoeff(u16 Coeff); +#define DRAW_GetTextColor() (u16) (((tCircleFunc0)(Circle_API [DRAW_GETTEXTCOLOR_ID])) ()) //u16 DRAW_GetTextColor(void); +#define DRAW_SetTextColor(a) ((tCircleFunc1)(Circle_API [DRAW_SETTEXTCOLOR_ID])) ((u32)(a)) //void DRAW_SetTextColor(u16 Color); +#define DRAW_GetBGndColor() (u16) (((tCircleFunc0)(Circle_API [DRAW_GETBGNDCOLOR_ID])) ()) //u16 DRAW_GetBGndColor(void); +#define DRAW_SetBGndColor(a) ((tCircleFunc1)(Circle_API [DRAW_SETBGNDCOLOR_ID])) ((u32)(a)) //void DRAW_SetBGndColor(u16 Color); +#define DRAW_Line(a,b,c,d,e) ((tCircleFunc5)(Circle_API [DRAW_LINE_ID])) ((u32)(a),(u32)(b),(u32)(c),(u32)(d),(u32)(e)) //void DRAW_Line(s16 x1, s16 y1, s16 x2, s16 y2, u16 color ); +/// @endcond + +//-------------------------------- BUZZER ----------------------------------- + +/* Exported type def ---------------------------------------------------------*/ + +/** +* @enum BUZZER_mode +* @brief CircleOS buzzer modes. +* +* Without the undefined mode, the CircleOS provides 5 modes for its buzzer. +**/ +enum BUZZER_mode + { + BUZZER_UNDEF = -1, /*!< undefined mode for buzzer */ + BUZZER_OFF = 0, /*!< The buzzer is put off. */ + BUZZER_ON = 1, /*!< The buzzer is put on. */ + BUZZER_SHORTBEEP = 2, /*!< Make buzzer to bip for a short time */ + BUZZER_LONGBEEP = 3, /*!< Make buzzer to bip for a long time */ + BUZZER_PLAYMUSIC = 4 /*!< Make buzzer to play a music */ + }; + +/// @cond Internal + +/* Exported defines ----------------------------------------------------------*/ +#define BUZZER_BEEP BUZZER_SHORTBEEP + +// BUZZER functions definition +#define BUZZER_SETMODE_ID (BUZZER_ID + 0) // Set new buzzer mode +#define BUZZER_GETMODE_ID (BUZZER_ID + 1) // Get the current buzzer mode. +#define BUZZER_PLAY_MUSIC_ID (BUZZER_ID + 2) // Plays the provided melody that follows the RTTTL Format. + +// Prototypes +#define BUZZER_SetMode(a) ((tCircleFunc1)(Circle_API [BUZZER_SETMODE_ID])) ((u32)(a)) //void BUZZER_SetMode( enum BUZZER_mode mode); +#define BUZZER_GetMode() (enum BUZZER_mode) (((tCircleFunc0)(Circle_API [BUZZER_GETMODE_ID])) ()) //enum BUZZER_mode BUZZER_GetMode( void ); +#define BUZZER_PlayMusic(a) ((tCircleFunc1)(Circle_API [BUZZER_PLAY_MUSIC_ID])) ((u32)(a)) //void BUZZER_PlayMusic (const u8 *melody ); + +/// @endcond + +//--------------------------------- MENU ----------------------------------- + +/* Exported defines ----------------------------------------------------------*/ +#define REMOVE_MENU 0x01 /*!< Menu flag: remove menu when item selected. */ +#define APP_MENU 0x02 /*!< Menu flag: item is an application. */ +#define MENU_MAXITEM 8 /*!< Maximum number of item in a menu. */ + +/* Exported type def ---------------------------------------------------------*/ + +/** +* @struct tMenuItem +* @brief Menu item description. +**/ +typedef struct + { + const char* Text; /*!< Name of Item displayed in menu */ + enum MENU_code (*Fct_Init) ( void ); /*!< First function launched if item is selected. */ + enum MENU_code (*Fct_Manage)( void ); /*!< Second function launched after a "return MENU_CONTINU_COMMAND" in the first function */ + int fRemoveMenu; /*!< Flag to know if remove menu at end */ + } tMenuItem; + +/** +* @struct tMenu +* @brief Menu description. +**/ +typedef struct + { + unsigned fdispTitle: 1; /*!< Display title is set. */ + const char* Title; /*!< Menu title. */ + int NbItems; /*!< Number of items in the menu ( must be <= MENU_MAXITEM ) */ + int LgMax; /*!< Unused. */ + int XPos; /*!< X position of menu bottom-left corner. */ + int YPos; /*!< Y position of menu bottom-left corner. */ + int XSize; /*!< Unused. */ + int YSize; /*!< Unused. */ + unsigned int SelectedItem; /*!< ID of selected item (0 for first item, 1 for second item, ...) */ + tMenuItem Items[MENU_MAXITEM]; /*!< Items of menu. */ + } tMenu; + +/** +* @enum MENU_code +* @brief Application return values. +* +* List of all the codes available for CircleOS application return values. +**/ +enum MENU_code + { + MENU_LEAVE = 0, /*!< Leave application. */ + MENU_CONTINUE = 1, /*!< Continue application. */ + MENU_REFRESH = 2, /*!< Refresh current menu. */ + MENU_CHANGE = 3, /*!< Change current menu. */ + MENU_CONTINUE_COMMAND = 4 /*!< Sent by Ini functions.*/ + }; + +/// @cond Internal + +/* Exported defines ----------------------------------------------------------*/ + +// MENU functions definition +#define MENU_SET_ID (MENU_ID + 0) // Display a menu +#define MENU_REMOVE_ID (MENU_ID + 1) // Remove the current menu, DRAW_Clear and set pointer mode to "POINTER_ON". +#define MENU_QUESTION_ID (MENU_ID + 2) // Dedicated menu for ask question and yes/no responses +#define MENU_PRINT_ID (MENU_ID + 3) // Display a popup menu with a string. +#define MENU_CLEAR_CURRENT_COMMAND_ID (MENU_ID + 4) // Set CurrentCommand to 0 +#define MENU_SET_LEVELTITLE_ID (MENU_ID + 5) // Set the title of level menu managed by MENU_SetLevel_Mgr. +#define MENU_SET_TEXTCOLOR_ID (MENU_ID + 6) // Set the color used for text menu. +#define MENU_GET_TEXTCOLOR_ID (MENU_ID + 7) // Return the color used for text menu. +#define MENU_SET_BGNDCOLOR_ID (MENU_ID + 8) // Set the background color used for menu. +#define MENU_GET_BGNDCOLOR_ID (MENU_ID + 9) // Return the background color used for menu. +#define MENU_QUIT_ID (MENU_ID + 10) // Leave the current menu (stand for "cancel" and do a DRAW_Clear) +#define MENU_SET_LEVELINI_ID (MENU_ID + 11) // Initialise a generic function to set a avalue in the range of [0,4] +#define MENU_CLEAR_CURRENT_MENU_ID (MENU_ID + 12) // Set CurrentMenu to 0 +#define MENU_SET_LEVEL_MGR_ID (MENU_ID + 13) // Generic function to set a avalue in the range of [0,4] (handling of the control) + +// Prototypes +#define MENU_Set(a) ((tCircleFunc1)(Circle_API [MENU_SET_ID])) ((u32)(a)) //void MENU_Set ( tMenu *mptr ); +#define MENU_Remove() ((tCircleFunc0)(Circle_API [MENU_REMOVE_ID])) () //void MENU_Remove ( void ) ; +#define MENU_Question(a,b) ((tCircleFunc2)(Circle_API [MENU_QUESTION_ID])) ((u32)(a),(u32)(b)) //void MENU_Question ( char *str, int *answer ); +#define MENU_Print(a) ((tCircleFunc1)(Circle_API [MENU_PRINT_ID])) ((u32)(a)) //void MENU_Print ( char *str ); +#define MENU_ClearCurrentCommand() ((tCircleFunc0)(Circle_API [MENU_CLEAR_CURRENT_COMMAND_ID])) () //void MENU_ClearCurrentCommand(void) +#define MENU_SetLevelTitle(a) ((tCircleFunc1)(Circle_API [MENU_SET_LEVELTITLE_ID])) ((u32)(a)) //void MENU_SetLevelTitle(u8* title) +#define MENU_SetTextColor(a) ((tCircleFunc1)(Circle_API [MENU_SET_TEXTCOLOR_ID])) ((u32)(a)) //void MENU_SetTextColor ( int TextColor ) +#define MENU_GetTextColor() (u32) (((tCircleFunc0)(Circle_API [MENU_GET_TEXTCOLOR_ID])) ()) //int MENU_GetTextColor ( void ) +#define MENU_SetBGndColor(a) ((tCircleFunc1)(Circle_API [MENU_SET_BGNDCOLOR_ID])) ((u32)(a)) //void MENU_SetBGndColor ( int BGndColor ) +#define MENU_GetBGndColor() (u32) (((tCircleFunc0)(Circle_API [MENU_GET_BGNDCOLOR_ID])) ()) //int MENU_GetBGndColor ( void ) +#define MENU_Quit() (enum MENU_code) (((tCircleFunc0)(Circle_API [MENU_QUIT_ID])) ()) //enum MENU_code MENU_Quit ( void ) +#define MENU_SetLevel_Ini() (enum MENU_code) (((tCircleFunc0)(Circle_API [MENU_SET_LEVELINI_ID])) ()) //enum MENU_code MENU_SetLevel_Ini ( void ) +#define MENU_ClearCurrentMenu() ((tCircleFunc0)(Circle_API [MENU_CLEAR_CURRENT_MENU_ID])) () //void MENU_ClearCurrentMenu(void) +#define MENU_SetLevel_Mgr(a,b) (enum MENU_code) ((tCircleFunc2)(Circle_API [MENU_SET_LEVEL_MGR_ID])) ((u32)(a),(u32)(b)) //enum MENU_code MENU_SetLevel_Mgr ( u32 *value, u32 value_range [] ) + +/// @endcond + +//---------------------------------- LED ------------------------------------- + +/* Exported types ------------------------------------------------------------*/ + +/** +* @enum LED_mode +* @brief LED modes. +* +* LEDs may be on, off or blinking slowly or fastly! +**/ +enum LED_mode + { + LED_UNDEF = -1, /*!< Undefined led mode. */ + LED_OFF = 0, /*!< Put off the led. */ + LED_ON = 1, /*!< Put on the led. */ + LED_BLINKING_LF = 2, /*!< Slow blinking led mode. */ + LED_BLINKING_HF = 3 /*!< Fast blinking led mode. */ + }; + +/** +* @enum LED_id +* @brief Available LEDs. +* +* List of all the available LEDs. +**/ +enum LED_id + { + LED_GREEN = 0, /*!< Green led id. */ + LED_RED = 1 /*!< Red led id. */ + }; + +/// @cond Internal + +/* Exported defines ----------------------------------------------------------*/ + +// LED functions definition +#define LED_SET_ID (LED_ID + 0) // Set a specified LED in a specified mode. + +// Prototypes +#define LED_Set(a,b) ((tCircleFunc2)(Circle_API [LED_SET_ID])) ((u32)(a),(u32)(b)) //void LED_Set ( enum LED_id id, enum LED_mode mode ) //void LED_Set ( enum LED_id id, enum LED_mode mode ); + +/// @endcond + +//-------------------------------- RTC -------------------------------------- + +/* Exported defines ----------------------------------------------------------*/ + +// Backup registers +#define BKP_SYS1 1 /*!< Backup register reserved for OS */ +#define BKP_SYS2 2 /*!< Backup register reserved for OS */ +#define BKP_SYS3 3 /*!< Backup register reserved for OS */ +#define BKP_SYS4 4 /*!< Backup register reserved for OS */ +#define BKP_SYS5 5 /*!< Backup register reserved for OS */ +#define BKP_SYS6 6 /*!< Backup register reserved for OS */ + +#define BKP_USER1 7 /*!< Backup available for users application */ +#define BKP_USER2 8 /*!< Backup available for users application */ +#define BKP_USER3 9 /*!< Backup available for users application */ +#define BKP_USER4 10 /*!< Backup available for users application */ + +/// @cond Internal + +//RTC functions definition +#define RTC_SET_TIME_ID (RTC_ID + 0) // Set current time. +#define RTC_GET_TIME_ID (RTC_ID + 1) // Return current time. +#define RTC_DISPLAY_TIME_ID (RTC_ID + 2) // Display current time on the 6th line at column 0. + +// Prototypes +#define RTC_SetTime(a,b,c) ((tCircleFunc3)(Circle_API [RTC_SET_TIME_ID])) ((u32)(a),(u32)(b),(u32)(c)) //void RTC_SetTime (u32 THH, u32 TMM, u32 TSS); +#define RTC_GetTime(a,b,c) ((tCircleFunc3)(Circle_API [RTC_GET_TIME_ID])) ((u32)(a),(u32)(b),(u32)(c)) //void RTC_GetTime (u32 * THH, u32 * TMM, u32 * TSS); +#define RTC_DisplayTime() ((tCircleFunc0)(Circle_API [RTC_DISPLAY_TIME_ID])) () //void RTC_DisplayTime ( void ); + +/// @endcond + +//--------------------------------- Application ------------------------------- +typedef void (*tAppPtrMgr) ( int , int ); + +#endif /*__CIRCLE_API_H */ diff --git a/20080212/Demo/CORTEX_STM32F103_Primer_GCC/ST_Code/crt0_STM32x.c b/20080212/Demo/CORTEX_STM32F103_Primer_GCC/ST_Code/crt0_STM32x.c new file mode 100644 index 000000000..6dfbb2de1 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_Primer_GCC/ST_Code/crt0_STM32x.c @@ -0,0 +1,217 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_vector.c +* Author : MCD Tools Team +* Date First Issued : 05/14/2007 +* Description : This file contains the vector table for STM32F10x. +* After Reset the Cortex-M3 processor is in Thread mode, +* priority is Privileged, and the Stack is set to Main. +******************************************************************************** +* History: +* 05/14/2007: V0.2 +* +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ----------------------------------------------------------------------*/ + +void NMIException(void); +void HardFaultException(void); +void MemManageException(void); +void BusFaultException(void); +void UsageFaultException(void); +void DebugMonitor(void); +void SVCHandler(void); +void PendSVC(void); +void SysTickHandler(void); +void WWDG_IRQHandler(void); +void PVD_IRQHandler(void); +void TAMPER_IRQHandler(void); +void RTC_IRQHandler(void); +void FLASH_IRQHandler(void); +void RCC_IRQHandler(void); +void EXTI0_IRQHandler(void); +void EXTI1_IRQHandler(void); +void EXTI2_IRQHandler(void); +void EXTI3_IRQHandler(void); +void EXTI4_IRQHandler(void); +void DMAChannel1_IRQHandler(void); +void DMAChannel2_IRQHandler(void); +void DMAChannel3_IRQHandler(void); +void DMAChannel4_IRQHandler(void); +void DMAChannel5_IRQHandler(void); +void DMAChannel6_IRQHandler(void); +void DMAChannel7_IRQHandler(void); +void ADC_IRQHandler(void); +void USB_HP_CAN_TX_IRQHandler(void); +void USB_LP_CAN_RX0_IRQHandler(void); +void CAN_RX1_IRQHandler(void); +void CAN_SCE_IRQHandler(void); +void EXTI9_5_IRQHandler(void); +void TIM1_BRK_IRQHandler(void); +void TIM1_UP_IRQHandler(void); +void TIM1_TRG_COM_IRQHandler(void); +void TIM1_CC_IRQHandler(void); +void TIM2_IRQHandler(void); +void TIM3_IRQHandler(void); +void TIM4_IRQHandler(void); +void I2C1_EV_IRQHandler(void); +void I2C1_ER_IRQHandler(void); +void I2C2_EV_IRQHandler(void); +void I2C2_ER_IRQHandler(void); +void SPI1_IRQHandler(void); +void SPI2_IRQHandler(void); +void USART1_IRQHandler(void); +void USART2_IRQHandler(void); +void USART3_IRQHandler(void); +void EXTI15_10_IRQHandler(void); +void RTCAlarm_IRQHandler(void); +void USBWakeUp_IRQHandler(void); + + +/* Exported types --------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +extern unsigned long _etext; +extern unsigned long _sidata; /* start address for the initialization values of the .data section. defined in linker script */ +extern unsigned long _sdata; /* start address for the .data section. defined in linker script */ +extern unsigned long _edata; /* end address for the .data section. defined in linker script */ + +extern unsigned long _sbss; /* start address for the .bss section. defined in linker script */ +extern unsigned long _ebss; /* end address for the .bss section. defined in linker script */ + +extern void _estack; /* init value for the stack pointer. defined in linker script */ + + + +/* Private typedef -----------------------------------------------------------*/ +/* function prototypes ------------------------------------------------------*/ +void Reset_Handler(void) __attribute__((__interrupt__)); +extern int main(void); +extern void xPortPendSVHandler(void); +extern void xPortSysTickHandler(void); +extern void vTimer2IntHandler( void ); + + +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + + +__attribute__ ((section(".isr_vector"))) +void (* const g_pfnVectors[])(void) = +{ + &_estack, // The initial stack pointer + Reset_Handler, // The reset handler + NMIException, + HardFaultException, + MemManageException, + BusFaultException, + UsageFaultException, + 0, 0, 0, 0, /* Reserved */ + SVCHandler, + DebugMonitor, + 0, /* Reserved */ + xPortPendSVHandler, + xPortSysTickHandler, + WWDG_IRQHandler, + PVD_IRQHandler, + TAMPER_IRQHandler, + RTC_IRQHandler, + FLASH_IRQHandler, + RCC_IRQHandler, + EXTI0_IRQHandler, + EXTI1_IRQHandler, + EXTI2_IRQHandler, + EXTI3_IRQHandler, + EXTI4_IRQHandler, + DMAChannel1_IRQHandler, + DMAChannel2_IRQHandler, + DMAChannel3_IRQHandler, + DMAChannel4_IRQHandler, + DMAChannel5_IRQHandler, + DMAChannel6_IRQHandler, + DMAChannel7_IRQHandler, + ADC_IRQHandler, + USB_HP_CAN_TX_IRQHandler, + USB_LP_CAN_RX0_IRQHandler, + CAN_RX1_IRQHandler, + CAN_SCE_IRQHandler, + EXTI9_5_IRQHandler, + TIM1_BRK_IRQHandler, + TIM1_UP_IRQHandler, + TIM1_TRG_COM_IRQHandler, + TIM1_CC_IRQHandler, + vTimer2IntHandler, + TIM3_IRQHandler, + TIM4_IRQHandler, + I2C1_EV_IRQHandler, + I2C1_ER_IRQHandler, + I2C2_EV_IRQHandler, + I2C2_ER_IRQHandler, + SPI1_IRQHandler, + SPI2_IRQHandler, + USART1_IRQHandler, + USART2_IRQHandler, + USART3_IRQHandler, + EXTI15_10_IRQHandler, + RTCAlarm_IRQHandler, + USBWakeUp_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + (unsigned long)0xF108F85F //this is a workaround for boot in RAM mode. +}; + +/******************************************************************************* +* Function Name : Reset_Handler +* Description : This is the code that gets called when the processor first starts execution +* following a reset event. Only the absolutely necessary set is performed, +* after which the application supplied main() routine is called. +* Input : +* Output : +* Return : +*******************************************************************************/ +void Reset_Handler(void) +{ + unsigned long *pulSrc, *pulDest; + + // + // Copy the data segment initializers from flash to SRAM. + // + pulSrc = &_sidata; + for(pulDest = &_sdata; pulDest < &_edata; ) + { + *(pulDest++) = *(pulSrc++); + } + + // + // Zero fill the bss segment. + // + for(pulDest = &_sbss; pulDest < &_ebss; ) + { + *(pulDest++) = 0; + } + + // + // Call the application's entry point. + // + main(); +} + + +/********************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ + + diff --git a/20080212/Demo/CORTEX_STM32F103_Primer_GCC/ST_Code/draw.c b/20080212/Demo/CORTEX_STM32F103_Primer_GCC/ST_Code/draw.c new file mode 100644 index 000000000..17b5f51aa --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_Primer_GCC/ST_Code/draw.c @@ -0,0 +1,545 @@ +/********************* (C) COPYRIGHT 2007 RAISONANCE S.A.S. *******************/ +/** +* +* @file draw.c +* @brief Various utilities for drawings (characters, ..) +* @author FL +* @author IB +* @date 07/2007 +* +**/ +/******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "circle.h" + +/// @cond Internal + +/* Private define ------------------------------------------------------------*/ +#define V9_MADCTRVAL 0x90 +#define V12_MADCTRVAL 0x30 +#define V3_MADCTRVAL 0x50 +#define V6_MADCTRVAL 0xF0 + +#define ROTATE_DIVISER 500 + +/* Private variables ---------------------------------------------------------*/ + +static u16 CharMagniCoeff = 1; /*!< Current character magnify coefficient. */ +static u16 BGndColor; /*!< Current background color. */ +static u16 TextColor; /*!< Current text color. */ + +int fDisplayTime = 0; +u16 BatState; +u16 OldBatState; +u32 OldTHH; +u32 OldTMM; +u32 OldTSS; +u32 OldTemp; //FL071107 +u16 xBat; +u16 yBat; +u16 widthBat; +u16 heightBat; +u8 UsbState,OldUsbState; +static int divider_coord = 0; + +// Screen orientation management +int rotate_counter = 0; +Rotate_H12_V_Match_TypeDef previous_H12 = V9; +Rotate_H12_V_Match_TypeDef previous_previous_H12 = V9; +Rotate_H12_V_Match_TypeDef H12; +Rotate_H12_V_Match_TypeDef CurrentScreenOrientation; +int CurrentRotateScreen = 1; + +extern s16 XInit; +extern s16 YInit; + +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* +* vbattoa +* +*******************************************************************************/ +/** +* +* This function convert an u16 in ascii radix 10 +* +* @param[out] ptr A pointer to a string where the converted value will be put. +* @param[in] X The value to convert. +* +* @see DRAW_DisplayVbat +* +**/ +/******************************************************************************/ +static void vbattoa( char* ptr, u16 X ) + { + u8 c; + u16 r = 0; + + // 1 000 digit + c = ((X-r)/1000); + r = r + (c*1000); + *ptr++ = c + 0x30; + + // dot + *ptr++ = '.'; + + // 100 digit + c = ((X-r)/100); + r = r + (c*100); + *ptr++ = c + 0x30; + + // 10 digit + c = ((X-r)/10); + r = r + (c*10); + *ptr++ = c + 0x30; + + // Volt + *ptr++ = 'V'; + *ptr++ = 0; + } + +/******************************************************************************* +* +* DRAW_DisplayStringWithMode +* +*******************************************************************************/ +/** +* +* This function is used to display a 17char max string of +* characters on the LCD display on the selected line. +* Note: +* this function is the user interface to use the LCD driver. +* +* @param[in] x The horizontal screen coordinate where to draw the string. +* @param[in] y The vertical screen coordinate where to draw the string. +* @param[in] ptr Pointer to string to display. +* @param[in] len String size. +* @param[in] mode Display mode: 0 normal, 1 inverted colors. +* +* @warning The (0x0) point in on the low left corner. +* +* @see DRAW_DisplayString +* @see DRAW_DisplayStringInverted +* +**/ +/******************************************************************************/ +static void DRAW_DisplayStringWithMode( u8 x, u8 y, const u8* ptr, u8 len, int mode ) + { + u8 ref_x = x, i = 0; + + /* Send the string character by character on LCD */ + while ((*ptr!=0)&&(i<18)) + { + /* Display one character on LCD */ + LCD_DisplayChar( ref_x, y, *ptr, mode ? BGndColor : TextColor, mode ? TextColor : BGndColor, CharMagniCoeff ); + + /* Increment the column position by 7 */ + ref_x+= (7*CharMagniCoeff); + + /* Point on the next character */ + ptr++; + + /* Increment the character counter */ + i++; + /* If we reach the maximum Line character */ + } + + while ( i < len ) + { + /* Display one character on LCD */ + LCD_DisplayChar( ref_x, y, ' ', mode ? BGndColor : TextColor, mode ? TextColor : BGndColor, CharMagniCoeff ); + + /* Increment the column position by 7 */ + ref_x += ( 7 * CharMagniCoeff ); + + /* Increment the character counter */ + i++; + } + } + +/* Public functions for CircleOS ---------------------------------------------*/ + +/******************************************************************************* +* +* DRAW_Init +* +*******************************************************************************/ +/** +* +* Initialize GUI drawing. Called at CircleOS startup. +* +* @attention This function must NOT be called by the user. +* +**/ +/******************************************************************************/ +void DRAW_Init( void ) + { + LCD_Init(); +#ifdef _MEMS + MEMS_GetRotation( &CurrentScreenOrientation ); +#endif + LCD_SetScreenOrientation( CurrentScreenOrientation ); + + xBat = 98; + yBat = 3; + OldBatState = 10; + OldTSS = 100; + OldTMM = 100; + OldTHH = 100; + OldTemp = -1; + + // Clear LCD and draw black and white logo + DRAW_SetDefaultColor(); + LCD_FillRect( 0, 0, CHIP_SCREEN_WIDTH, CHIP_SCREEN_HEIGHT, BGndColor ); +// POINTER_Init(); + } + + + + +/* Public functions ----------------------------------------------------------*/ + +/******************************************************************************* +* +* DRAW_SetCharMagniCoeff +* +*******************************************************************************/ +/** +* +* Set the magnifying value for the characters (should be 1 or 2) +* +* @param[in] Coeff The new magnifying coefficent. +* +**/ +/******************************************************************************/ +void DRAW_SetCharMagniCoeff( u16 Coeff ) + { + CharMagniCoeff = Coeff; + } + + /****************************************************************************** +* +* DRAW_GetCharMagniCoeff +* +*******************************************************************************/ +/** +* +* Return the current magnifying value for the characters +* +* @return Current magnifying value. +* +**/ +/******************************************************************************/ +u16 DRAW_GetCharMagniCoeff( void ) + { + return CharMagniCoeff; + } + + /****************************************************************************** +* +* DRAW_GetTextColor +* +*******************************************************************************/ +/** +* +* Return current text color. +* +* @return The current RGB color used to draw text. +* +**/ +/******************************************************************************/ +u16 DRAW_GetTextColor( void ) + { + return TextColor; + } + +/******************************************************************************* +* +* DRAW_SetTextColor +* +*******************************************************************************/ +/** +* +* Set current text color. +* +* @param[in] Color The new RGB color used when drawing text. +* +**/ +/******************************************************************************/ +void DRAW_SetTextColor( u16 Color ) + { + TextColor = Color ; + } + +/******************************************************************************* +* +* DRAW_GetBGndColor +* +*******************************************************************************/ +/** +* +* Return current background color. +* +* @return The current RGB color used for the background. +* +**/ +/******************************************************************************/ +u16 DRAW_GetBGndColor( void ) + { + return BGndColor; + } + +/******************************************************************************* +* +* DRAW_SetBGndColor +* +*******************************************************************************/ +/** +* +* Set current background color +* +* @param[in] Color The new RGB color for background. +* +**/ +/******************************************************************************/ +void DRAW_SetBGndColor(u16 Color) + { + BGndColor = Color; + } + + +/******************************************************************************* +* +* DRAW_SetImage +* +*******************************************************************************/ +/** +* +* The provided bitmap is made width * height 2 byte words. Each 2 byte word contains +* the RGB color of a pixel. +* +* @brief Draw a color bitmap at the provided coordinates. +* @param[in] imageptr A pointer to an array of width * height 2 byte words. +* @param[in] x The horizontal coordinate of the low left corner of the bitmap. +* @param[in] y The vertical coordinate of the low left corner of the bitmap. +* @param[in] width The bitmap width. +* @param[in] height The bitmap height. +* +* @warning The (0x0) point in on the low left corner. +* +**/ +/******************************************************************************/ +void DRAW_SetImage( const u16* imageptr, u8 x, u8 y, u8 width, u8 height ) + { + int i; + + // Select screen area to access. + LCD_SetRect_For_Cmd( x, y, width, height ); + + // Send command to write data on the LCD screen. + LCD_SendLCDCmd(ST7637_RAMWR); + + for( i = 0; i < ( width * height ); i++ ) + { + LCD_SendLCDData( imageptr[ i ] & 0xff ); + LCD_SendLCDData( ( imageptr[ i ] >> 8 ) & 0xff ); + } + } + + + +/******************************************************************************* +* +* DRAW_DisplayString +* +*******************************************************************************/ +/** +* +* This function is used to display a 17 character max string of +* characters on the LCD display at the provided coordinates. +* +* @param[in] x The horizontal coordinate of the displayed string. +* @param[in] y The vertical coordinate of the display string. +* @param[in] *ptr Pointer to the string to display on LCD. +* @param[in] len String length. +* +* @warning The (0x0) point in on the low left corner. +* +**/ +/******************************************************************************/ +void DRAW_DisplayString( u8 x, u8 y, const u8* ptr, u8 len ) + { + DRAW_DisplayStringWithMode( x, y, ptr, len, 0 ); + } + +/******************************************************************************* +* +* DRAW_DisplayStringInverted +* +*******************************************************************************/ +/** +* +* This function is used to display a 17 character max string of +* characters on the LCD display at the provided coordinates with inverted colors. +* +* @param[in] x The horizontal coordinate of the displayed string. +* @param[in] y The vertical coordinate of the display string. +* @param[in] *ptr Pointer to the string to display on LCD. +* @param[in] len String length. +* +* @warning The (0x0) point in on the low left corner. +* +**/ +/******************************************************************************/ +void DRAW_DisplayStringInverted( u8 x, u8 y, const u8* ptr, u8 len ) + { + //BackGround and Text Colors are inverted + DRAW_DisplayStringWithMode( x, y, ptr, len, 1 ); + } + +/******************************************************************************* +* +* DRAW_SetDefaultColor +* +*******************************************************************************/ +/** +* +* Reset text and background colors to their default values. +* +**/ +/******************************************************************************/ +void DRAW_SetDefaultColor (void) + { + BGndColor = RGB_WHITE; + TextColor = RGB_BLACK; + } + +/******************************************************************************* +* +* DRAW_DisplayTemp +* +*******************************************************************************/ +/** +* +* This function is used to display the current temperature in ascii. +* The choice between Celcius and Fahrenheit is fixed by UTIL_SetModeTemp() +* +* @param[in] x The horizontal coordinate of the displayed string. +* @param[in] y The vertical coordinate of the display string. +* +* @warning The (0x0) point in on the low left corner. +* +**/ +/******************************************************************************/ +void DRAW_DisplayTemp( u8 x, u8 y ) + { + u32 Temp = 0; + u8 TextBuffer[5] = { 0,0,0,0,0}; + + // Get Time + Temp = UTIL_GetTemp() ; + + if( Temp != OldTemp ) + { + // Display C (if modified). + UTIL_uint2str( TextBuffer, Temp/10, 2, 1 ); + TextBuffer[ 2 ] = '.'; + DRAW_DisplayString( x + ( 0 * CharMagniCoeff * 7 ), y, TextBuffer, 3 ); + + // Display C/10 (if modified). + UTIL_uint2str( TextBuffer, Temp%10, 1, 1 ); + TextBuffer[ 1 ] = fTemperatureInFahrenheit ? 'F' : 'C'; TextBuffer[ 2 ] = 0; + DRAW_DisplayString( x + ( 3 * CharMagniCoeff * 7 ), y, TextBuffer, 2 ); + } + OldTemp = Temp; + } + +/******************************************************************************* +* +* DRAW_Line +* +*******************************************************************************/ +/** +* Draw a line on the LCD screen. Optimized for horizontal/vertical lines, +* and use the Bresenham algorithm for other cases. +* +* @param[in] x1 The x-coordinate of the first line endpoint. +* @param[in] x2 The x-coordinate of the second line endpoint. +* @param[in] y1 The y-coordinate of the first line endpoint. +* @param[in] y2 The y-coordinate of the second line endpoint. +* @param[in] color The line color. +* +**/ +void DRAW_Line (s16 x1, s16 y1, s16 x2, s16 y2, u16 color ) + { + int i,dx,dy,sdx,sdy,dxabs,dyabs,x,y,px,py; + + #define abs(X) ( ( (X) < 0 ) ? -(X) : (X) ) + #define sgn(X) ( ( (X) < 0 ) ? -1 : 1 ) + + if ( x1==x2 ) //Vertical Line + { + if ( y1 > y2 ) //We assume y2>y1 and invert if not + { + i = y2; + y2 = y1; + y1 = i; + } + LCD_FillRect( x1, y1, 1, y2-y1+1, color ); + return; + } + else if ( y1==y2 ) //Horizontal Line + { + if ( x1 > x2 ) //We assume x2>x1 and we swap them if not + { + i = x2; + x2 = x1; + x1 = i; + } + LCD_FillRect( x1, y1, x2-x1+1, 1, color ); + return; + } + + dx=x2-x1; /* the horizontal distance of the line */ + dy=y2-y1; /* the vertical distance of the line */ + dxabs=abs(dx); + dyabs=abs(dy); + sdx=sgn(dx); + sdy=sgn(dy); + x=dyabs>>1; + y=dxabs>>1; + px=x1; + py=y1; + + if (dxabs>=dyabs) /* the line is more horizontal than vertical */ + { + for(i=0;i=dxabs) + { + y-=dxabs; + py+=sdy; + } + px+=sdx; + LCD_DrawPixel(px,py,color); + } + } + else /* the line is more vertical than horizontal */ + { + for(i=0;i=dyabs) + { + x-=dyabs; + px+=sdx; + } + py+=sdy; + LCD_DrawPixel(px,py,color); + } + } + } + diff --git a/20080212/Demo/CORTEX_STM32F103_Primer_GCC/ST_Code/lcd.c b/20080212/Demo/CORTEX_STM32F103_Primer_GCC/ST_Code/lcd.c new file mode 100644 index 000000000..0f39b47cf --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_Primer_GCC/ST_Code/lcd.c @@ -0,0 +1,1189 @@ +/********************* (C) COPYRIGHT 2007 RAISONANCE S.A.S. *******************/ +/** +* +* @file lcd.c +* @brief The LCD driver for the ST7637. +* @author FL +* @date 07/2007 +* +**/ +/******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "lcd.h" +#include "circle.h" + +/// @cond Internal + +/* Private define ------------------------------------------------------------*/ +#define V9_MADCTRVAL 0x90 /*!< Left orientation value. */ +#define V12_MADCTRVAL 0x30 /*!< Up orientation value. */ +#define V3_MADCTRVAL 0x50 /*!< Right orientation value. */ +#define V6_MADCTRVAL 0xF0 /*!< Bottom orientation value. */ +#define BACKLIGHT_DIVIDER 500 /*!< LCD handler step. */ + +/* Private variables ---------------------------------------------------------*/ + +// vars for timer dedicated for lcd backlight +static TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; +static TIM_OCInitTypeDef TIM_OCInitStructure; +static int HandlerDivider = 0; + +int Current_CCR_BackLightStart = DEFAULT_CCR_BACKLIGHTSTART; + +/* External variable ---------------------------------------------------------*/ +extern GPIO_InitTypeDef GPIO_InitStructure; +extern u16 CCR_BackLight_Tab[5]; +extern int CurrentRotateScreen; +extern Rotate_H12_V_Match_TypeDef CurrentScreenOrientation; + +/*! ASCII Table. Each character is 7 column (7dots large) on two pages (16dots high) + 7 column character: Two 8 bit data to display one column*/ +static const u8 AsciiDotsTable[95 * 14 ] = { + /* ASCII 32 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + /* ASCII 33 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x13,0xe0,0x00,0x00,0x00,0x00,0x00,0x00, + /* ASCII 34 */ 0x00,0x00,0x00,0xe0,0x00,0x20,0x00,0x00,0x00,0xe0,0x00,0x20,0x00,0x00, + /* ASCII 35 */ 0x00,0x00,0x35,0x00,0x0f,0x80,0x35,0x60,0x0f,0x80,0x05,0x60,0x00,0x00, + /* ASCII 36 */ 0x00,0x00,0x0d,0x80,0x0a,0x40,0x3a,0x60,0x06,0x40,0x00,0x00,0x00,0x00, + /* ASCII 37 */ 0x00,0x00,0x02,0x40,0x02,0xa0,0x0a,0x40,0x15,0x00,0x09,0x00,0x00,0x00, + /* ASCII 38 */ 0x00,0x00,0x0c,0x00,0x13,0x00,0x14,0x80,0x08,0x80,0x14,0x00,0x00,0x00, + /* ASCII 39 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xe0,0x00,0x00,0x00,0x00,0x00,0x00, + /* ASCII 40 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x1f,0x80,0x60,0x60,0x00,0x00,0x00,0x00, + /* ASCII 41 */ 0x00,0x00,0x00,0x00,0x60,0x60,0x1f,0x80,0x00,0x00,0x00,0x00,0x00,0x00, + /* ASCII 42 */ 0x00,0x00,0x00,0x40,0x03,0x40,0x00,0xe0,0x03,0x40,0x00,0x40,0x00,0x00, + /* ASCII 43 */ 0x02,0x00,0x02,0x00,0x02,0x00,0x1f,0xc0,0x02,0x00,0x02,0x00,0x02,0x00, + /* ASCII 44 */ 0x00,0x00,0x00,0x00,0x60,0x00,0x38,0x00,0x08,0x00,0x00,0x00,0x00,0x00, + /* ASCII 45 */ 0x00,0x00,0x02,0x00,0x02,0x00,0x02,0x00,0x02,0x00,0x02,0x00,0x00,0x00, + /* ASCII 46 */ 0x00,0x00,0x00,0x00,0x18,0x00,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + /* ASCII 47 */ 0x00,0x00,0x20,0x00,0x18,0x00,0x06,0x00,0x01,0x80,0x00,0x60,0x00,0x00, + /* ASCII 48 */ 0x00,0x00,0x0f,0xc0,0x10,0x20,0x10,0x20,0x10,0x20,0x0f,0xc0,0x00,0x00, + /* ASCII 49 */ 0x00,0x00,0x10,0x00,0x10,0x20,0x1f,0xe0,0x10,0x00,0x10,0x00,0x00,0x00, + /* ASCII 50 */ 0x00,0x00,0x18,0x40,0x14,0x20,0x12,0x20,0x11,0x20,0x18,0xc0,0x00,0x00, + /* ASCII 51 */ 0x00,0x00,0x08,0x40,0x10,0x20,0x11,0x20,0x11,0x20,0x0e,0xc0,0x00,0x00, + /* ASCII 52 */ 0x00,0x00,0x06,0x00,0x05,0x00,0x04,0xc0,0x14,0x20,0x1f,0xe0,0x14,0x00, + /* ASCII 53 */ 0x00,0x00,0x08,0x00,0x11,0xe0,0x11,0x20,0x11,0x20,0x0e,0x20,0x00,0x00, + /* ASCII 54 */ 0x00,0x00,0x0f,0x80,0x11,0x40,0x11,0x20,0x11,0x20,0x0e,0x20,0x00,0x00, + /* ASCII 55 */ 0x00,0x00,0x00,0x60,0x00,0x20,0x18,0x20,0x07,0x20,0x00,0xe0,0x00,0x00, + /* ASCII 56 */ 0x00,0x00,0x0e,0xc0,0x11,0x20,0x11,0x20,0x11,0x20,0x0e,0xc0,0x00,0x00, + /* ASCII 57 */ 0x00,0x00,0x11,0xc0,0x12,0x20,0x12,0x20,0x0a,0x20,0x07,0xc0,0x00,0x00, + /* ASCII 58 */ 0x00,0x00,0x00,0x00,0x19,0x80,0x19,0x80,0x00,0x00,0x00,0x00,0x00,0x00, + /* ASCII 59 */ 0x00,0x00,0x00,0x00,0x30,0x00,0x19,0x80,0x09,0x80,0x00,0x00,0x00,0x00, + /* ASCII 60 */ 0x02,0x00,0x05,0x00,0x05,0x00,0x08,0x80,0x10,0x40,0x10,0x40,0x00,0x00, + /* ASCII 61 */ 0x00,0x00,0x05,0x00,0x05,0x00,0x05,0x00,0x05,0x00,0x05,0x00,0x00,0x00, + /* ASCII 62 */ 0x10,0x40,0x10,0x40,0x08,0x80,0x05,0x00,0x05,0x00,0x02,0x00,0x00,0x00, + /* ASCII 63 */ 0x00,0x00,0x00,0x00,0x10,0x80,0x14,0x40,0x02,0x40,0x01,0x80,0x00,0x00, + /* ASCII 64 */ 0x00,0x00,0x1f,0xe0,0x20,0x10,0x23,0x10,0x24,0x90,0x17,0xe0,0x00,0x00, + /* ASCII 65 */ 0x10,0x00,0x1c,0x00,0x17,0xa0,0x04,0x60,0x17,0x80,0x1c,0x00,0x10,0x00, + /* ASCII 66 */ 0x10,0x20,0x1f,0xe0,0x11,0x20,0x11,0x20,0x11,0x20,0x0e,0xc0,0x00,0x00, + /* ASCII 67 */ 0x00,0x00,0x0f,0xc0,0x10,0x20,0x10,0x20,0x10,0x20,0x08,0x60,0x00,0x00, + /* ASCII 68 */ 0x10,0x20,0x1f,0xe0,0x10,0x20,0x10,0x20,0x08,0x40,0x07,0x80,0x00,0x00, + /* ASCII 69 */ 0x10,0x20,0x1f,0xe0,0x11,0x20,0x13,0xa0,0x10,0x20,0x18,0x60,0x00,0x00, + /* ASCII 70 */ 0x00,0x00,0x10,0x20,0x1f,0xe0,0x11,0x20,0x03,0xa0,0x00,0x20,0x00,0x60, + /* ASCII 71 */ 0x00,0x00,0x0f,0xc0,0x10,0x20,0x10,0x20,0x12,0x20,0x0e,0x60,0x02,0x00, + /* ASCII 72 */ 0x10,0x20,0x1f,0xe0,0x11,0x20,0x01,0x00,0x11,0x20,0x1f,0xe0,0x10,0x20, + /* ASCII 73 */ 0x00,0x00,0x10,0x20,0x10,0x20,0x1f,0xe0,0x10,0x20,0x10,0x20,0x00,0x00, + /* ASCII 74 */ 0x00,0x00,0x0e,0x00,0x10,0x20,0x10,0x20,0x0f,0xe0,0x00,0x20,0x00,0x00, + /* ASCII 75 */ 0x10,0x20,0x1f,0xe0,0x12,0x20,0x03,0x00,0x04,0xa0,0x18,0x60,0x10,0x20, + /* ASCII 76 */ 0x00,0x00,0x10,0x20,0x1f,0xe0,0x10,0x20,0x10,0x00,0x1c,0x00,0x00,0x00, + /* ASCII 77 */ 0x10,0x20,0x1f,0xe0,0x10,0xe0,0x03,0x00,0x10,0xe0,0x1f,0xe0,0x10,0x20, + /* ASCII 78 */ 0x10,0x20,0x1f,0xe0,0x10,0xe0,0x07,0x00,0x18,0x20,0x1f,0xe0,0x00,0x20, + /* ASCII 79 */ 0x00,0x00,0x0f,0xc0,0x10,0x20,0x10,0x20,0x10,0x20,0x0f,0xc0,0x00,0x00, + /* ASCII 80 */ 0x00,0x00,0x10,0x20,0x1f,0xe0,0x12,0x20,0x02,0x20,0x01,0xc0,0x00,0x00, + /* ASCII 81 */ 0x00,0x00,0x0f,0xc0,0x10,0x20,0x30,0x20,0x30,0x20,0x2f,0xc0,0x00,0x00, + /* ASCII 82 */ 0x10,0x20,0x1f,0xe0,0x12,0x20,0x02,0x20,0x06,0x20,0x09,0xc0,0x10,0x00, + /* ASCII 83 */ 0x00,0x00,0x18,0xc0,0x09,0x20,0x11,0x20,0x11,0x40,0x0e,0x60,0x00,0x00, + /* ASCII 84 */ 0x00,0x60,0x00,0x20,0x10,0x20,0x1f,0xe0,0x10,0x20,0x00,0x20,0x00,0x60, + /* ASCII 85 */ 0x00,0x20,0x0f,0xe0,0x10,0x20,0x10,0x00,0x10,0x20,0x0f,0xe0,0x00,0x20, + /* ASCII 86 */ 0x00,0x20,0x00,0xe0,0x07,0x20,0x18,0x00,0x07,0x20,0x00,0xe0,0x00,0x20, + /* ASCII 87 */ 0x00,0x20,0x0f,0xe0,0x10,0x20,0x0f,0x00,0x10,0x20,0x0f,0xe0,0x00,0x20, + /* ASCII 88 */ 0x10,0x20,0x18,0x60,0x04,0x80,0x03,0x00,0x04,0x80,0x18,0x60,0x10,0x20, + /* ASCII 89 */ 0x00,0x20,0x00,0x60,0x11,0xa0,0x1e,0x00,0x11,0xa0,0x00,0x60,0x00,0x20, + /* ASCII 90 */ 0x00,0x00,0x18,0x60,0x14,0x20,0x13,0x20,0x10,0xa0,0x18,0x60,0x00,0x00, + /* ASCII 91 */ 0x00,0x00,0x00,0x00,0x7f,0xe0,0x40,0x20,0x40,0x20,0x00,0x00,0x00,0x00, + /* ASCII 92 */ 0x00,0x00,0x00,0x20,0x01,0xc0,0x06,0x00,0x38,0x00,0x00,0x00,0x00,0x00, + /* ASCII 93 */ 0x00,0x00,0x00,0x00,0x40,0x20,0x40,0x20,0x7f,0xe0,0x00,0x00,0x00,0x00, + /* ASCII 94 */ 0x00,0x00,0x01,0x00,0x00,0x80,0x00,0x60,0x00,0x80,0x01,0x00,0x00,0x00, + /* ASCII 95 */ 0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00, + /* ASCII 96 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x40,0x00,0x00,0x00,0x00, + /* ASCII 97 */ 0x00,0x00,0x0d,0x00,0x12,0x80,0x12,0x80,0x12,0x80,0x1f,0x00,0x10,0x00, + /* ASCII 98 */ 0x10,0x20,0x1f,0xe0,0x11,0x00,0x10,0x80,0x10,0x80,0x0f,0x00,0x00,0x00, + /* ASCII 99 */ 0x00,0x00,0x0f,0x00,0x10,0x80,0x10,0x80,0x10,0x80,0x09,0x80,0x00,0x00, + /* ASCII 100 */ 0x00,0x00,0x0f,0x00,0x10,0x80,0x10,0x80,0x11,0x20,0x1f,0xe0,0x10,0x00, + /* ASCII 101 */ 0x00,0x00,0x0f,0x00,0x12,0x80,0x12,0x80,0x12,0x80,0x13,0x00,0x00,0x00, + /* ASCII 102 */ 0x00,0x00,0x10,0x80,0x1f,0xc0,0x10,0xa0,0x10,0xa0,0x10,0xa0,0x00,0x00, + /* ASCII 103 */ 0x00,0x00,0x0f,0x00,0x50,0x80,0x50,0x80,0x51,0x00,0x3f,0x80,0x00,0x80, + /* ASCII 104 */ 0x10,0x20,0x1f,0xe0,0x11,0x00,0x00,0x80,0x10,0x80,0x1f,0x00,0x10,0x00, + /* ASCII 105 */ 0x00,0x00,0x10,0x80,0x10,0x80,0x1f,0xa0,0x10,0x00,0x10,0x00,0x00,0x00, + /* ASCII 106 */ 0x00,0x00,0x40,0x80,0x40,0x80,0x40,0xa0,0x3f,0x80,0x00,0x00,0x00,0x00, + /* ASCII 107 */ 0x10,0x20,0x1f,0xe0,0x02,0x00,0x16,0x80,0x19,0x80,0x10,0x80,0x00,0x00, + /* ASCII 108 */ 0x00,0x00,0x10,0x00,0x10,0x20,0x1f,0xe0,0x10,0x00,0x10,0x00,0x00,0x00, + /* ASCII 109 */ 0x10,0x80,0x1f,0x80,0x10,0x80,0x1f,0x00,0x10,0x80,0x1f,0x00,0x10,0x00, + /* ASCII 110 */ 0x10,0x80,0x1f,0x80,0x11,0x00,0x00,0x80,0x10,0x80,0x1f,0x00,0x10,0x00, + /* ASCII 111 */ 0x00,0x00,0x0f,0x00,0x10,0x80,0x10,0x80,0x10,0x80,0x0f,0x00,0x00,0x00, + /* ASCII 112 */ 0x40,0x80,0x7f,0x80,0x51,0x00,0x10,0x80,0x10,0x80,0x0f,0x00,0x00,0x00, + /* ASCII 113 */ 0x00,0x00,0x0f,0x00,0x10,0x80,0x10,0x80,0x51,0x00,0x7f,0x80,0x40,0x80, + /* ASCII 114 */ 0x00,0x00,0x10,0x80,0x1f,0x80,0x11,0x00,0x10,0x80,0x10,0x80,0x00,0x00, + /* ASCII 115 */ 0x00,0x00,0x19,0x00,0x12,0x80,0x12,0x80,0x12,0x80,0x0d,0x80,0x00,0x00, + /* ASCII 116 */ 0x00,0x00,0x00,0x80,0x0f,0xc0,0x10,0x80,0x10,0x80,0x10,0x80,0x08,0x00, + /* ASCII 117 */ 0x00,0x80,0x0f,0x80,0x10,0x00,0x10,0x00,0x08,0x80,0x1f,0x80,0x10,0x00, + /* ASCII 118 */ 0x00,0x80,0x03,0x80,0x0c,0x80,0x10,0x00,0x0c,0x80,0x03,0x80,0x00,0x80, + /* ASCII 119 */ 0x00,0x80,0x0f,0x80,0x10,0x80,0x0e,0x00,0x10,0x80,0x0f,0x80,0x00,0x80, + /* ASCII 120 */ 0x10,0x80,0x19,0x80,0x06,0x00,0x06,0x00,0x19,0x80,0x10,0x80,0x00,0x00, + /* ASCII 121 */ 0x00,0x80,0x41,0x80,0x46,0x80,0x78,0x00,0x4c,0x80,0x03,0x80,0x00,0x80, + /* ASCII 122 */ 0x00,0x00,0x19,0x80,0x14,0x80,0x12,0x80,0x11,0x80,0x18,0x80,0x00,0x00, + /* ASCII 123 */ 0x00,0x00,0x00,0x00,0x04,0x00,0x3b,0xc0,0x40,0x20,0x00,0x00,0x00,0x00, + /* ASCII 124 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x3f,0xe0,0x00,0x00,0x00,0x00,0x00,0x00, + /* ASCII 125 */ 0x00,0x00,0x00,0x00,0x40,0x20,0x3b,0xc0,0x04,0x00,0x00,0x00,0x00,0x00, + /* ASCII 126 */ 0x00,0x00,0x04,0x00,0x02,0x00,0x04,0x00,0x04,0x00,0x02,0x00,0x00,0x00}; + +int OrientationOffsetX [] = { 0 /* V12*/,0 /* V3*/,+4 /* V6*/,+4 /* V9*/ }; +int OrientationOffsetY [] = { +4 /* V12*/,0 /* V3*/,0 /* V6*/,+4 /* V9*/ }; + +/* Private function prototypes -----------------------------------------------*/ +static void LCD_7637_Controller( void ); +static void LCD_DrawChar( u8 x, u8 y, u8 width, const u8 *bmp, u16 textColor, u16 bGndColor, u16 charMagniCoeff ); +static void LCD_BackLightChange( void ); +static void LCD_BackLightConfig( void ); +static void LCD_CtrlLinesWrite( GPIO_TypeDef* GPIOx, u32 CtrlPins, BitAction BitVal ); + +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* +* LCD_DataLinesConfig +* +*******************************************************************************/ +/** +* Configure data lines D0~D7 in Input Floating mode for read from LCD or in +* Output Push-Pull mode for write on LCD +* +* @param[in] Mode Specifies the configuration mode for data lines D0~D7. +* @n @c Input: configure in Input Floating mode +* @n @c Output: configure in Output Push-Pul mode +* +**/ +/******************************************************************************/ +static void LCD_DataLinesConfig( DataConfigMode_TypeDef Mode ) + { + GPIO_InitTypeDef GPIO_InitStructure; + + GPIO_InitStructure.GPIO_Pin = LCD_DATA_PINS; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + + if( Mode == Input ) + { + /* Configure D0~D7 lines as Input */ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; + } + else + { + /* Configure D0~D7 lines in Output Push-Pull mode */ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + } + + GPIO_Init( GPIOx_D_LCD, &GPIO_InitStructure ); + } + +/******************************************************************************* +* +* LCD_DataLinesWrite +* +*******************************************************************************/ +/** +* Write a value on D0~D7 +* +* @param[in] GPIOx GPIO port to write on. +* @param[in] PortVal The value to write. Only the lowest 8 bits are taken into +* account. +* +**/ +/******************************************************************************/ +static void LCD_DataLinesWrite( GPIO_TypeDef* GPIOx, u32 PortVal ) + { + // Write only the lowest 8 bits! + GPIOx->ODR = ( (GPIOx->ODR) & 0xFF00 ) | (u8)PortVal; + } + +/******************************************************************************* +* +* LCD_CtrlLinesConfig +* +*******************************************************************************/ +/** +* Configure control lines in Output Push-Pull mode. +* +**/ +/******************************************************************************/ +static void LCD_CtrlLinesConfig( void ) + { + GPIO_InitTypeDef GPIO_InitStructure; + + GPIO_InitStructure.GPIO_Pin = LCD_CTRL_PINS; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + + GPIO_Init( GPIOx_CTRL_LCD, &GPIO_InitStructure ); + + GPIO_InitStructure.GPIO_Pin = CtrlPin_CS; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + + GPIO_Init( GPIOx_CS_LCD, &GPIO_InitStructure ); + + LCD_CtrlLinesWrite( GPIOx_CTRL_LCD, CtrlPin_RS, Bit_SET ); /* RS = 1 */ + LCD_CtrlLinesWrite( GPIOx_CTRL_LCD, CtrlPin_RD, Bit_SET ); /* RD = 1 */ + LCD_CtrlLinesWrite( GPIOx_CS_LCD, CtrlPin_CS, Bit_SET ); /* CS = 1 */ + LCD_CtrlLinesWrite( GPIOx_CTRL_LCD, CtrlPin_WR, Bit_SET ); /* WR = 1 */ + LCD_CtrlLinesWrite( GPIOx_CTRL_LCD, CtrlPin_RST, Bit_RESET ); /* RST = 0 */ + } + +/******************************************************************************* +* +* LCD_CtrlLinesWrite +* +*******************************************************************************/ +/** +* Set or reset control lines. +* +* @param[in] GPIOx Where x can be 0, 1 or 2 to select the GPIO peripheral. +* @param[in] CtrlPins The Control line. +* @param[in] BitVal +* +**/ +/******************************************************************************/ +static void LCD_CtrlLinesWrite( GPIO_TypeDef* GPIOx, u32 CtrlPins, BitAction BitVal ) + { + /* Set or Reset the control line */ + GPIO_WriteBit( GPIOx, CtrlPins, BitVal ); + } + +/******************************************************************************* +* +* LCD_CheckLCDStatus +* +*******************************************************************************/ +/** +* Check whether LCD LCD is busy or not. +* +**/ +/******************************************************************************/ +static void LCD_CheckLCDStatus( void ) + { + unsigned char ID1; + unsigned char ID2; + unsigned char ID3; + + LCD_SendLCDCmd( ST7637_RDDID ); + + /* Configure Data lines as Input */ + LCD_DataLinesConfig (Input ); + + /* Start the LCD send data sequence */ + LCD_CtrlLinesWrite( GPIOx_CTRL_LCD, CtrlPin_RS, Bit_RESET ); /* RS = 0 */ + LCD_CtrlLinesWrite( GPIOx_CTRL_LCD, CtrlPin_RD, Bit_RESET ); /* RD = 0 */ + LCD_CtrlLinesWrite( GPIOx_CS_LCD, CtrlPin_CS, Bit_RESET ); /* CS = 0 */ + LCD_CtrlLinesWrite( GPIOx_CTRL_LCD, CtrlPin_WR, Bit_SET ); /* WR = 1 */ + + /* Read data to the LCD */ + GPIO_ReadInputData( GPIOx_D_LCD ); + LCD_CtrlLinesWrite( GPIOx_CTRL_LCD, CtrlPin_RD, Bit_SET ); /* RD = 1 */ + LCD_CtrlLinesWrite( GPIOx_CTRL_LCD, CtrlPin_RD, Bit_RESET ); /* RD = 0 */ + + ID1 = GPIO_ReadInputData( GPIOx_D_LCD ); + + LCD_CtrlLinesWrite( GPIOx_CTRL_LCD, CtrlPin_RD, Bit_SET ); /* RD = 1 */ + LCD_CtrlLinesWrite( GPIOx_CTRL_LCD, CtrlPin_RD, Bit_RESET ); /* RD = 0 */ + + ID2 = GPIO_ReadInputData( GPIOx_D_LCD ); + + LCD_CtrlLinesWrite( GPIOx_CTRL_LCD, CtrlPin_RD, Bit_SET ); /* RD = 1 */ + LCD_CtrlLinesWrite( GPIOx_CTRL_LCD, CtrlPin_RD, Bit_RESET ); /* RD = 0 */ + + ID3 = GPIO_ReadInputData( GPIOx_D_LCD ); + + LCD_DataLinesConfig( Output ); + } + +/******************************************************************************* +* +* LCD_DrawChar +* +*******************************************************************************/ +/** +* Draw a character on the LCD screen. +* +* @param[in] x The line where to display the character shape. +* @param[in] y The column start address. +* @param[in] width The number of columns (dots) in a character width. +* @param[in] bmp The character (monochrome) bitmap. A pointer of the dot matrix data. +* @param[in] textColor The character color. +* @param[in] bGndColor The character background color. +* @param[in] charMagniCoeff The character magnifying coefficient. +* +* @warning The (0x0) point in on the low left corner. +* +**/ +/******************************************************************************/ +static void LCD_DrawChar( u8 x, u8 y, u8 width, const u8* bmp, u16 textColor, u16 bGndColor, u16 charMagniCoeff ) + { + int i; + int j; + int k1; + int k2; + + // Select the area for LCD output. + LCD_SetRect_For_Cmd( x, y, 7 * charMagniCoeff, 14 * charMagniCoeff ); + + // Select LCD output mode. + LCD_SendLCDCmd( ST7637_RAMWR ); + + for( i = 0; i < 7; i++ ) + { + for( k1 = 0; k1 < charMagniCoeff; k1++ ) + { + for( j = 0x80; j; j >>= 1 ) // 8 + { + for( k2 = 0; k2 < charMagniCoeff; k2++ ) + { + LCD_SendLCDData( ( bmp[2*i] & j ) ? ( textColor & 255 ) : ( bGndColor & 255 ) ); + LCD_SendLCDData( ( bmp[2*i] & j ) ? ( textColor >> 8 ) : ( bGndColor >> 8 ) ); + } + } + + for( j = 0x80; j > 2; j >>= 1 ) // 8 + { + for( k2 = 0; k2 < charMagniCoeff; k2++ ) + { + LCD_SendLCDData( ( bmp[2*i+1] & j ) ? ( textColor & 255 ) : ( bGndColor & 255 ) ); + LCD_SendLCDData( ( bmp[2*i+1] & j ) ? ( textColor >> 8 ) : ( bGndColor >> 8 ) ); + } + } + } + } + } + +/******************************************************************************* +* +* LCD_DisplayRotate +* +*******************************************************************************/ +/** +* Configure the LCD controller for a given orientation. +* +* @param[in] H12 The new screen orientation. +* +**/ +/******************************************************************************/ +static void LCD_DisplayRotate( Rotate_H12_V_Match_TypeDef H12 ) + { + // Memory Access Control 0x36 + LCD_SendLCDCmd( ST7637_MADCTR ); + + switch( H12 ) + { + case V3 : + LCD_SendLCDData( V3_MADCTRVAL ); + break; + + case V6 : + LCD_SendLCDData( V6_MADCTRVAL ); + break; + + case V9 : + LCD_SendLCDData( V9_MADCTRVAL ); + break; + + case V12 : + default : + LCD_SendLCDData( V12_MADCTRVAL ); + break; + } + } + +/******************************************************************************* +* +* LCD_7637_Controller +* +*******************************************************************************/ +/** +* Initialization of the controller registers. +* +* @note See ST7637.PDF for more information. +* +**/ +/******************************************************************************/ +static void LCD_7637_Controller( void ) + { + extern void starting_delay ( long unsigned ); + + /** Apply hardware reset **/ + LCD_CtrlLinesWrite( GPIOx_CTRL_LCD, CtrlPin_RST, Bit_SET ); /* RST = 1 */ + LCD_CtrlLinesWrite( GPIOx_CTRL_LCD, CtrlPin_RST, Bit_RESET ); /* RST = 0 */ + starting_delay( 0x500 ); + + LCD_CtrlLinesWrite( GPIOx_CTRL_LCD, CtrlPin_RST, Bit_SET ); /* RST = 1 */ + starting_delay( 0x500 ); + + //default mode is output + LCD_DataLinesConfig( Output ); + + LCD_CheckLCDStatus(); + + LCD_SendLCDCmd( ST7637_SWRESET ); + + //-----------disable autoread + Manual read once ---------------------------- + LCD_SendLCDCmd( ST7637_AUTOLOADSET ); // Auto Load Set 0xD7 + LCD_SendLCDData( 0xBF ); // Auto Load Disable + + LCD_SendLCDCmd( ST7637_EPCTIN ); // EE Read/write mode 0xE0 + LCD_SendLCDData( 0x00 ); // Set read mode + + LCD_SendLCDCmd( ST7637_EPMRD ); // Read active 0xE3 + LCD_SendLCDCmd( ST7637_EPCTOUT ); // Cancel control 0xE1 + + //---------------------------------- Sleep OUT ------------------------------ + LCD_SendLCDCmd( ST7637_DISPOFF ); // display off 0x28 + LCD_SendLCDCmd( ST7637_SLPOUT ); // Sleep Out 0x11 + + //--------------------------------Vop setting-------------------------------- + LCD_SendLCDCmd( ST7637_VOPSET ); // Set Vop by initial Module 0xC0 + LCD_SendLCDData( 0xFB ); // Vop = 13.64 + LCD_SendLCDData( 0x00 ); // base on Module + + //----------------------------Set Register----------------------------------- + LCD_SendLCDCmd( ST7637_BIASSEL ); // Bias select 0xC3 + LCD_SendLCDData( 0x00 ); // 1/12 Bias, base on Module + + LCD_SendLCDCmd( ST7637_BSTBMPXSEL ); // Setting Booster times 0xC4 + LCD_SendLCDData( 0x05 ); // Booster X 8 + + LCD_SendLCDCmd( ST7637_BSTEFFSEL ); // Booster eff 0xC5 + LCD_SendLCDData( 0x11 ); // BE = 0x01 (Level 2) + + LCD_SendLCDCmd( ST7637_VGSORCSEL ); // Vg with booster x2 control 0xcb + LCD_SendLCDData( 0x01 ); // Vg from Vdd2 + + LCD_SendLCDCmd( ST7637_ID1SET ); // ID1 = 00 0xcc + LCD_SendLCDData( 0x00 ); // + + LCD_SendLCDCmd( ST7637_ID3SET ); // ID3 = 00 0xce + LCD_SendLCDData( 0x00 ); // + + LCD_SendLCDCmd( 0xB7 ); // Glass direction + LCD_SendLCDData( 0xC0 ); // + + LCD_SendLCDCmd( ST7637_ANASET ); // Analog circuit setting 0xd0 + LCD_SendLCDData( 0x1D ); // + + LCD_SendLCDCmd( 0xB4 ); // PTL mode set + LCD_SendLCDData( 0x18 ); // power normal mode + LCD_SendLCDCmd( ST7637_INVOFF ); // Display Inversion OFF 0x20 + + LCD_SendLCDCmd( 0x2A ); // column range + LCD_SendLCDData( 0x04 ); // + LCD_SendLCDData( 0x83 ); // + + LCD_SendLCDCmd( 0x2B ); // raw range + LCD_SendLCDData( 0x04 ); // + LCD_SendLCDData( 0x83 ); // + + + LCD_SendLCDCmd( ST7637_COLMOD ); // Color mode = 65k 0x3A + LCD_SendLCDData( 0x05 ); // + + LCD_SendLCDCmd( ST7637_MADCTR ); // Memory Access Control 0x36 + LCD_SendLCDData( V9_MADCTRVAL ); + + LCD_SendLCDCmd( ST7637_DUTYSET ); // Duty = 132 duty 0xb0 + LCD_SendLCDData( 0x7F ); + + LCD_SendLCDCmd( 0x29 ); // Display ON + LCD_SendLCDCmd( 0xF9 ); // Gamma + LCD_SendLCDData( 0x00 ); // + LCD_SendLCDData( 0x03 ); // + LCD_SendLCDData( 0x05 ); // + LCD_SendLCDData( 0x07 ); // + LCD_SendLCDData( 0x09 ); // + LCD_SendLCDData( 0x0B ); // + LCD_SendLCDData( 0x0D ); // + LCD_SendLCDData( 0x0F ); // + LCD_SendLCDData( 0x11 ); // + LCD_SendLCDData( 0x13 ); // + LCD_SendLCDData( 0x15 ); // + LCD_SendLCDData( 0x17 ); // + LCD_SendLCDData( 0x19 ); // + LCD_SendLCDData( 0x1B ); // + LCD_SendLCDData( 0x1D ); // + LCD_SendLCDData( 0x1F ); // + } + +/******************************************************************************* +* +* LCD_BackLightConfig +* +*******************************************************************************/ +/** +* Setting of the PWM that drives the backlight intensity. +* +**/ +/******************************************************************************/ +static void LCD_BackLightConfig( void ) + { + GPIO_InitTypeDef GPIO_InitStructure; + + /* Enable GPIOB clock */ + RCC_APB2PeriphClockCmd( RCC_APB2Periph_GPIOB, ENABLE ); + + /* GPIOB Configuration:TIM4 2 in Output */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + + GPIO_Init( GPIOB, &GPIO_InitStructure ); + + /* TIM4 Configuration -----------------------------------------------------*/ + /* TIM4CLK = 12 MHz, Prescaler = 0x0 */ + + /* Enable TIM4 clock */ + RCC_APB1PeriphClockCmd( RCC_APB1Periph_TIM4, ENABLE ); + + TIM_DeInit( TIM4 ); + TIM_TimeBaseStructInit( &TIM_TimeBaseStructure ); + TIM_OCStructInit( &TIM_OCInitStructure ); + + /* Time base configuration */ + TIM_TimeBaseStructure.TIM_Period = 0xFFFF; + TIM_TimeBaseStructure.TIM_Prescaler = 0x0; + TIM_TimeBaseStructure.TIM_ClockDivision = 0x0; + TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; + + TIM_TimeBaseInit( TIM4, &TIM_TimeBaseStructure ); + + /* Output Compare Toggle Mode configuration: Channel2 */ + TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1; + TIM_OCInitStructure.TIM_Channel = TIM_Channel_2; + TIM_OCInitStructure.TIM_Pulse = Current_CCR_BackLightStart; + + TIM_OCInit( TIM4, &TIM_OCInitStructure ); + TIM_OC4PreloadConfig( TIM4, TIM_OCPreload_Disable ); + + TIM_ARRPreloadConfig( TIM4, ENABLE ); + + /* Enable TIM4 IT */ + TIM_ITConfig( TIM4, TIM_IT_CC2, ENABLE ); + + // Go !!! + TIM_Cmd( TIM4, ENABLE ); + } + +/******************************************************************************* +* +* LCD_BackLightChange +* +*******************************************************************************/ +/** +* Modify the PWM rate. +* +**/ +/******************************************************************************/ +static void LCD_BackLightChange( void ) + { + /* Output Compare Toggle Mode configuration: Channel2 */ + TIM_OCInitStructure.TIM_Pulse = Current_CCR_BackLightStart; + + TIM_OCInit( TIM4, &TIM_OCInitStructure ); + } + +/* Public functions for CircleOS ---------------------------------------------*/ + +/******************************************************************************* +* +* LCD_Init +* +*******************************************************************************/ +/** +* +* Initialize LCD. Called at CircleOS startup. +* +* @attention This function must NOT be called by the user. +* +**/ +/******************************************************************************/ +void LCD_Init( void ) + { + LCD_SetBackLight( UTIL_ReadBackupRegister( BKP_BKLIGHT ) ); + + /* Do some gpio configs*/ + GPIO_InitTypeDef GPIO_InitStructure; + + /* Enable GPIO clock for LCD */ + RCC_APB2PeriphClockCmd( GPIO_LCD_CTRL_PERIPH, ENABLE ); + RCC_APB2PeriphClockCmd( GPIO_LCD_D_PERIPH, ENABLE ); + RCC_APB2PeriphClockCmd( GPIO_LCD_CS_PERIPH, ENABLE ); + + /* Enable GPIOC clock */ + RCC_APB2PeriphClockCmd( RCC_APB2Periph_GPIOC, ENABLE ); + + /* Init BackLight*/ + LCD_BackLightConfig(); + + /* Configure control lines signals as output mode */ + LCD_CtrlLinesConfig(); + + /* LCD LCD Init */ + LCD_7637_Controller(); + } + +/******************************************************************************* +* +* LCD_Handler +* +*******************************************************************************/ +/** +* +* Called by the CircleOS scheduler to manage LCD tasks. +* +* @attention This function must NOT be called by the user. +* +**/ +/******************************************************************************/ +void LCD_Handler( void ) + { + if( ++HandlerDivider % BACKLIGHT_DIVIDER ) + { + return; + } + + LCD_BackLightChange(); + } + + +/// @endcond + +/* Public functions ----------------------------------------------------------*/ + +/******************************************************************************* +* +* LCD_SendLCDCmd +* +*******************************************************************************/ +/** +* +* Send on command byte to the LCD. +* +* @param[in] Cmd An unsigned char containing the user command to send to the LCD. +* +**/ +/******************************************************************************/ +void LCD_SendLCDCmd( u8 Cmd ) + { + /* Start the LCD send data sequence */ + LCD_CtrlLinesWrite( GPIOx_CTRL_LCD, CtrlPin_RS, Bit_RESET ); /* RS = 0 */ + LCD_CtrlLinesWrite( GPIOx_CTRL_LCD, CtrlPin_RD, Bit_SET ); /* RD = 1 */ + LCD_CtrlLinesWrite( GPIOx_CS_LCD, CtrlPin_CS, Bit_RESET ); /* CS = 0 */ + LCD_CtrlLinesWrite( GPIOx_CTRL_LCD, CtrlPin_WR, Bit_RESET ); /* WR = 0 */ + + /* Write data to the LCD */ + LCD_DataLinesWrite( GPIOx_D_LCD, (u32)Cmd ); + LCD_CtrlLinesWrite( GPIOx_CTRL_LCD, CtrlPin_WR, Bit_SET ); /* WR = 1 */ + } + +/******************************************************************************* +* +* LCD_SendLCDData +* +*******************************************************************************/ +/** +* +* Send one data byte to the LCD. +* +* @param[in] Data An unsigned character containing the data to send to the LCD. +* @pre An LCD_SendLCDCmd was done with a command waiting for data. +* +* +**/ +/******************************************************************************/ +void LCD_SendLCDData( u8 Data ) + { + /* Configure Data lines as Output */ + LCD_CtrlLinesWrite( GPIOx_CTRL_LCD, CtrlPin_RS, Bit_SET ); + LCD_CtrlLinesWrite( GPIOx_CTRL_LCD, CtrlPin_RD, Bit_SET ); + LCD_CtrlLinesWrite( GPIOx_CS_LCD, CtrlPin_CS, Bit_RESET ); + LCD_CtrlLinesWrite( GPIOx_CTRL_LCD, CtrlPin_WR, Bit_RESET ); + + /* Write data to the LCD */ + LCD_DataLinesWrite( GPIOx_D_LCD,(u32)Data ); + LCD_CtrlLinesWrite( GPIOx_CTRL_LCD, CtrlPin_WR, Bit_SET ); + } + +/*********************************************************************************** +* +* LCD_ReadLCDData +* +************************************************************************************/ +/** +* +* Read one data byte from the LCD. +* +* @return An unsigned 32 bit word containing the data returned by a LCD command. +* @pre An LCD_SendLCDCmd was done with a command returning data. +* +**/ +/********************************************************************************/ +u32 LCD_ReadLCDData( void ) + { + u32 LCDData = 0; + + /* Configure Data lines as Input */ + LCD_DataLinesConfig(Input); + + /* Start the LCD send data sequence */ + LCD_CtrlLinesWrite( GPIOx_D_LCD, CtrlPin_RS, Bit_SET ); /* RS = 1 */ + LCD_CtrlLinesWrite( GPIOx_D_LCD, CtrlPin_WR, Bit_SET ); /* WR = 1 */ + LCD_CtrlLinesWrite( GPIOx_CS_LCD, CtrlPin_CS, Bit_RESET ); /* CS = 0 */ + LCD_CtrlLinesWrite( GPIOx_D_LCD, CtrlPin_RD, Bit_RESET ); /* RD = 0 */ + + /* Read data from the LCD */ + LCDData = (GPIO_ReadInputData( GPIOx_D_LCD ) & LCD_DATA_PINS ); + + LCD_CtrlLinesWrite( GPIOx_D_LCD, CtrlPin_RD, Bit_SET ); /* RD = 1 */ + + /* Read the LCD returned data */ + LCD_DataLinesConfig( Output ); + + return LCDData; + } + +/******************************************************************************* +* +* LCD_FillRect +* +*******************************************************************************/ +/** +* +* Fill a rectangle with a provided color. +* +* @param[in] x The horizontal coordinate of the rectangle low left corner. +* @param[in] y The vertical coordinate of the rectangle low left corner. +* @param[in] width The rectangle width in pixels. +* @param[in] height The rectangle height in pixels. +* @param[in] color The RGB color to fill the rectangle with. +* +* @warning The (0x0) point in on the low left corner. +* +**/ +/******************************************************************************/ +void LCD_FillRect( u16 x, u16 y, u16 width, u16 height, u16 color ) + { + u8 Line; + u8 Column; + + /* Select LCD screen area. */ + LCD_SetRect_For_Cmd( x, y, width, height ); + + /* Send LCD RAM write command. */ + LCD_SendLCDCmd( ST7637_RAMWR ); + + /* Fill selected LCD screen area with provided color. */ + for( Line = 0; Line < width; Line++ ) + { + for( Column = 0; Column < height; Column++ ) + { + LCD_SendLCDData( color & 0xff ); + LCD_SendLCDData( ( color >> 8 ) & 0xff ); + } + } + + #ifdef TESTLCD + /* Configure Data lines as Input */ + LCD_DataLinesConfig( Input ); + + LCD_CtrlLinesWrite( GPIOx_CTRL_LCD, CtrlPin_RST, Bit_SET ); /* RST = 1 */ + LCD_CtrlLinesWrite( GPIOx_CTRL_LCD, CtrlPin_RST, Bit_RESET ); /* RST = 0 */ + LCD_CtrlLinesWrite( GPIOx_CTRL_LCD, CtrlPin_RST, Bit_SET ); /* RST = 1 */ + + /* Start the LCD send data sequence */ + LCD_CtrlLinesWrite( GPIOx_D_LCD, CtrlPin_RS, Bit_SET ); /* RS = 1 */ + LCD_CtrlLinesWrite( GPIOx_D_LCD, CtrlPin_RS, Bit_RESET ); /* RS = 0 */ + LCD_CtrlLinesWrite( GPIOx_D_LCD, CtrlPin_RS, Bit_SET ); /* RS = 1 */ + + LCD_CtrlLinesWrite( GPIOx_D_LCD, CtrlPin_RS, Bit_SET ); /* RS = 1 */ + LCD_CtrlLinesWrite( GPIOx_D_LCD, CtrlPin_RS, Bit_RESET ); /* RS = 0 */ + LCD_CtrlLinesWrite( GPIOx_D_LCD, CtrlPin_RS, Bit_SET ); /* RS = 1 */ + + LCD_CtrlLinesWrite( GPIOx_D_LCD, CtrlPin_WR, Bit_SET ); /* WR = 1 */ + LCD_CtrlLinesWrite( GPIOx_D_LCD, CtrlPin_WR, Bit_RESET ); /* WR = 1 */ + LCD_CtrlLinesWrite( GPIOx_D_LCD, CtrlPin_WR, Bit_SET ); /* WR = 1 */ + + LCD_CtrlLinesWrite( GPIOx_D_LCD, CtrlPin_RD, Bit_SET ); /* RD = 1 */ + LCD_CtrlLinesWrite( GPIOx_D_LCD, CtrlPin_RD, Bit_RESET ); /* RD = 0 */ + LCD_CtrlLinesWrite( GPIOx_D_LCD, CtrlPin_RD, Bit_SET ); /* RD = 1 */ + + LCD_CtrlLinesWrite( GPIOx_D_LCD, CtrlPin_RD, Bit_SET ); /* RD = 1 */ + LCD_CtrlLinesWrite( GPIOx_D_LCD, CtrlPin_RD, Bit_RESET ); /* RD = 0 */ + LCD_CtrlLinesWrite( GPIOx_D_LCD, CtrlPin_RD, Bit_SET ); /* RD = 1 */ + + /* Configure Data lines as Input */ + LCD_DataLinesConfig( Output ); + + LCD_DataLinesWrite( GPIOx_D_LCD, ~0 ); + LCD_DataLinesWrite( GPIOx_D_LCD, 0 ); + LCD_DataLinesWrite( GPIOx_D_LCD, ~1 ); + LCD_DataLinesWrite( GPIOx_D_LCD, 1 ); + LCD_DataLinesWrite( GPIOx_D_LCD, ~2 ); + LCD_DataLinesWrite( GPIOx_D_LCD, 2 ); + LCD_DataLinesWrite( GPIOx_D_LCD, ~4 ); + LCD_DataLinesWrite( GPIOx_D_LCD, 4 ); + LCD_DataLinesWrite( GPIOx_D_LCD, ~8 ); + LCD_DataLinesWrite( GPIOx_D_LCD, 8 ); + LCD_DataLinesWrite( GPIOx_D_LCD, ~0x10 ); + LCD_DataLinesWrite( GPIOx_D_LCD, 0x10 ); + LCD_DataLinesWrite( GPIOx_D_LCD, ~0x20 ); + LCD_DataLinesWrite( GPIOx_D_LCD, 0x20 ); + LCD_DataLinesWrite( GPIOx_D_LCD, ~0x40 ); + LCD_DataLinesWrite( GPIOx_D_LCD, 0x40 ); + LCD_DataLinesWrite( GPIOx_D_LCD, ~0x80 ); + LCD_DataLinesWrite( GPIOx_D_LCD, 0x80 ); + + LCD_DataLinesConfig( Input ); + + #endif + } + +/******************************************************************************* +* +* LCD_DrawRect +* +*******************************************************************************/ +/** +* +* Draw a rectangle with a provided color. +* +* @param[in] x The horizontal coordinate of the rectangle low left corner. +* @param[in] y The vertical coordinate of the rectangle low left corner. +* @param[in] width The rectangle width in pixels. +* @param[in] height The rectangle height in pixels. +* @param[in] color The RGB color to draw the rectangle with. +* +* @warning The (0x0) point in on the low left corner. +* +**/ +/******************************************************************************/ +void LCD_DrawRect( u16 x, u16 y, u16 width, u16 height, u16 color ) + { + // Draw horizontal sides. + LCD_FillRect( x, y, width, 1, color ); + LCD_FillRect( x, y + height - 1, width, 1, color ); + + // Draw vertical sides. + LCD_FillRect( x, y, 1, height, color ); + LCD_FillRect( x + width - 1, y, 1, height, color ); + } + +/******************************************************************************* +* +* LCD_DrawPixel +* +*******************************************************************************/ +/** +* +* Draw a pixel on the LCD with the provided color. +* +* @param[in] XPos The horizontal coordinate of the pixel. +* @param[in] YPos The vertical coordinate of the pixel. +* @param[in] Color The RGB color to draw the pixel with. +* +* @warning The (0x0) point in on the low left corner. +* +**/ +/******************************************************************************/ +void LCD_DrawPixel( u8 XPos, u8 YPos, u16 Color ) + { + /* Select LCD screen area. */ + LCD_SetRect_For_Cmd( XPos, YPos, 1, 1 ); + + /* Send LCD RAM write command. */ + LCD_SendLCDCmd( ST7637_RAMWR ); + + // Draw pixel. + LCD_SendLCDData( Color ); + LCD_SendLCDData( Color >> 8 ); + } + +/******************************************************************************* +* +* LCD_RectRead +* +*******************************************************************************/ +/** +* +* Save the pixels of a rectangle part of the LCD into a RAM variable. +* +* @param[in] x The horizontal coordinate of the rectangle low left corner. +* @param[in] y The vertical coordinate of the rectangle low left corner. +* @param[in] width The rectangle width in pixels. +* @param[in] height The rectangle height in pixels. +* @param[out] bmp The variable to store the read data into. +* +* @warning One pixel weights 2 bytes. +* @warning The (0x0) point in on the low left corner. +* +**/ +/******************************************************************************/ +void LCD_RectRead( u16 x, u16 y, u16 width, u16 height, u8* bmp ) + { + int i; + int bytesize = (width * height) *2; // 2 bytes per pixel. + + /* Select LCD screen area. */ + LCD_SetRect_For_Cmd( x, y, width, height ); + + /* Send LCD RAM write command. */ + LCD_SendLCDCmd(ST7637_RAMRD); + + // First read byte is dummy! + LCD_ReadLCDData(); + + // Read pixels from LCD screen. + for( i = 0; i < bytesize; i++ ) + { + *bmp++ = LCD_ReadLCDData(); + } + } + +/******************************************************************************* +* +* LCD_GetPixel +* +*******************************************************************************/ +/** +* +* Read the RGB color of the pixel the coordinate are provided in parameter. +* +* @param[in] x The horizontal coordinate of the pixel. +* @param[in] y The vertical coordinate of the pixel. +* @return An unsigned 16 bit word containing the RGB color of the pixel. +* +* @warning The (0x0) point in on the low left corner. +* @see LCD_RectRead +* +**/ +/******************************************************************************/ +u16 LCD_GetPixel( u8 x, u8 y ) + { + u16 val; + + LCD_RectRead( x, y, 1, 1, (u8*)&val ); + + return val; + } + +/******************************************************************************* +* +* LCD_DisplayChar +* +*******************************************************************************/ +/** +* +* Display at provided coordinates the provided ASCII character with the provided +* text and background colors and with the provided magnify coefficient. +* +* @param[in] x The horizontal coordinate of the character. +* @param[in] y The vertical coordinate of the character. +* @param[in] Ascii The ASCII code of the character to display. +* @n Ascii must be higher than 31 and lower than 127. +* @param[in] TextColor The color used to draw the character. +* @param[in] BGndColor The background color of the drawn character. +* @param[in] CharMagniCoeff The magnify coefficient used to draw the character. +* +* @warning The (0x0) point in on the low left corner. +* +**/ +/******************************************************************************/ +void LCD_DisplayChar( u8 x, u8 y, u8 Ascii, u16 TextColor, u16 BGndColor, u16 CharMagniCoeff) + { + // Display the selected bitmap according to the provided ASCII character. + LCD_DrawChar( x, y, 7, (u8*)&AsciiDotsTable[ (Ascii-32) * 14 ], TextColor, BGndColor, CharMagniCoeff ); + } + +/******************************************************************************* +* +* LCD_SetRect_For_Cmd +* +*******************************************************************************/ +/** +* +* Define the rectangle for the next command to be applied. +* +* @param[in] x The horizontal coordinate of the rectangle low left corner. +* @param[in] y The vertical coordinate of the rectangle low left corner. +* @param[in] width The rectangle width in pixels. +* @param[in] height The rectangle height in pixels. +* +* @warning The (0x0) point in on the low left corner. +* +**/ +/******************************************************************************/ +void LCD_SetRect_For_Cmd( s16 x, s16 y, s16 width, s16 height ) + { + LCD_SendLCDCmd( ST7637_CASET ); + LCD_SendLCDData( y + OrientationOffsetX[ CurrentScreenOrientation ] ); + LCD_SendLCDData( y + OrientationOffsetX[ CurrentScreenOrientation ] + height - 1 ); + + LCD_SendLCDCmd( ST7637_RASET ); + LCD_SendLCDData( x + OrientationOffsetY[ CurrentScreenOrientation ] ); + LCD_SendLCDData( x + OrientationOffsetY[ CurrentScreenOrientation ] + width - 1 ); + } + +/******************************************************************************* +* +* LCD_SetBackLight +* +*******************************************************************************/ +/** +* +* Modify the PWM rate. Any value below BACKLIGHTMIN reset the value to the +* default value (DEFAULT_CCR_BACKLIGHTSTART). +* +* @param[in] newBacklightStart The new PWM rate. +* +**/ +/******************************************************************************/ +void LCD_SetBackLight( u32 newBacklightStart ) + { + if( newBacklightStart >= BACKLIGHTMIN ) + { + Current_CCR_BackLightStart = newBacklightStart; + } + else + { + Current_CCR_BackLightStart = DEFAULT_CCR_BACKLIGHTSTART; + } + } + +/******************************************************************************* +* +* LCD_SetBackLightOff +* +*******************************************************************************/ +/** +* +* Switch the LCD back light off. +* +**/ +/******************************************************************************/ +void LCD_SetBackLightOff( void ) + { + Current_CCR_BackLightStart = 0; + } + +/******************************************************************************* +* +* LCD_SetBackLightOn +* +*******************************************************************************/ +/** +* +* Switch the LCD back light on. +* +**/ +/******************************************************************************/ +void LCD_SetBackLightOn( void ) + { + Current_CCR_BackLightStart = DEFAULT_CCR_BACKLIGHTSTART; + } + +/******************************************************************************* +* +* LCD_GetBackLight +* +*******************************************************************************/ +/** +* +* Returns le LCD PWM rate. +* +* @return The current LCD PWM rate. +* +**/ +/******************************************************************************/ +u32 LCD_GetBackLight( void ) + { + return Current_CCR_BackLightStart; + } + +/******************************************************************************* +* +* LCD_SetRotateScreen +* +*******************************************************************************/ +/** +* +* Enable or disable the ability of the screen display to rotate according to +* the MEMs information. +* +* @param[in] RotateScreen 0 to disable screen rotation and 1 to enable. +* +**/ +/******************************************************************************/ +void LCD_SetRotateScreen( u8 RotateScreen) + { + CurrentRotateScreen = RotateScreen; + } + +/******************************************************************************* +* +* LCD_GetRotateScreen +* +*******************************************************************************/ +/** +* +* Return the screen rotation mode. +* +* @retval 0 screen rotation is disabled. +* @retval 1 screen rotation is enabled. +* +**/ +/******************************************************************************/ +u8 LCD_GetRotateScreen( void ) + { + return CurrentRotateScreen; + } + +/******************************************************************************* +* +* LCD_SetScreenOrientation +* +*******************************************************************************/ +/** +* +* Set the screen orientation. +* +* @param[in] ScreenOrientation The new screen orientation. +* +**/ +/******************************************************************************/ +void LCD_SetScreenOrientation( Rotate_H12_V_Match_TypeDef ScreenOrientation ) + { + CurrentScreenOrientation = ScreenOrientation; + + LCD_DisplayRotate( CurrentScreenOrientation ); + } + +/******************************************************************************* +* +* LCD_GetScreenOrientation +* +*******************************************************************************/ +/** +* +* Return current screen orientation. +* +* @return A Rotate_H12_V_Match_TypeDef telling the current screen orientation. +* +**/ +/******************************************************************************/ +Rotate_H12_V_Match_TypeDef LCD_GetScreenOrientation( void ) + { + return CurrentScreenOrientation; + } + diff --git a/20080212/Demo/CORTEX_STM32F103_Primer_GCC/ST_Code/lcd.h b/20080212/Demo/CORTEX_STM32F103_Primer_GCC/ST_Code/lcd.h new file mode 100644 index 000000000..478f43824 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_Primer_GCC/ST_Code/lcd.h @@ -0,0 +1,154 @@ +/********************* (C) COPYRIGHT 2007 RAISONANCE S.A.S. *******************/ +/** +* +* @file lcd.h +* @brief The header file for ST7637 driver. +* @author IB +* @date 07/2007 +* +**/ +/******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __LCD_H +#define __LCD_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_lib.h" + +/* Type def -----------------------------------------------------------------*/ + +/* Data lines configuration mode */ +typedef enum + { + Input, + Output + } DataConfigMode_TypeDef; + +/* Constants -----------------------------------------------------------------*/ + +/* LCD Control pins */ +#define CtrlPin_RS GPIO_Pin_8 +#define CtrlPin_RD GPIO_Pin_9 +#define CtrlPin_WR GPIO_Pin_10 +#define CtrlPin_RST GPIO_Pin_12 +#define LCD_CTRL_PINS (CtrlPin_RS|CtrlPin_RD|CtrlPin_WR|CtrlPin_RST) +#define GPIOx_CTRL_LCD GPIOC +#define GPIO_LCD_CTRL_PERIPH RCC_APB2Periph_GPIOC + +#define CtrlPin_CS GPIO_Pin_2 +#define GPIOx_CS_LCD GPIOD +#define GPIO_LCD_CS_PERIPH RCC_APB2Periph_GPIOD + +#define LCD_D0 GPIO_Pin_0 +#define LCD_D1 GPIO_Pin_1 +#define LCD_D2 GPIO_Pin_2 +#define LCD_D3 GPIO_Pin_3 +#define LCD_D4 GPIO_Pin_4 +#define LCD_D5 GPIO_Pin_5 +#define LCD_D6 GPIO_Pin_6 +#define LCD_D7 GPIO_Pin_7 +#define LCD_DATA_PINS (LCD_D0|LCD_D1|LCD_D2|LCD_D3|LCD_D4|LCD_D5|LCD_D6|LCD_D7) +#define GPIOx_D_LCD GPIOC +#define GPIO_LCD_D_PERIPH RCC_APB2Periph_GPIOC + +/* LCD Commands */ +#define DISPLAY_ON 0xAF +#define DISPLAY_OFF 0xAE +#define START_LINE 0xC0 +#define START_COLUMN 0x00 +#define CLOCKWISE_OUTPUT 0xA0 +#define DYNAMIC_DRIVE 0xA4 +#define DUTY_CYCLE 0xA9 +#define READ_MODIFY_WRITE_OFF 0xEE +#define SOFTWARE_RESET 0xE2 + +#define ST7637_NOP 0x00 +#define ST7637_SWRESET 0x01 +#define ST7637_RDDID 0x04 +#define ST7637_RDDST 0x09 +#define ST7637_RDDPM 0x0A +#define ST7637_RDDMADCTR 0x0B +#define ST7637_RDDCOLMOD 0x0C +#define ST7637_RDDIM 0x0D +#define ST7637_RDDSM 0x0E +#define ST7637_RDDSDR 0x0F + +#define ST7637_SLPIN 0x10 +#define ST7637_SLPOUT 0x11 +#define ST7637_PTLON 0x12 +#define ST7637_NORON 0x13 + +#define ST7637_INVOFF 0x20 +#define ST7637_INVON 0x21 +#define ST7637_APOFF 0x22 +#define ST7637_APON 0x23 +#define ST7637_WRCNTR 0x25 +#define ST7637_DISPOFF 0x28 +#define ST7637_DISPON 0x29 +#define ST7637_CASET 0x2A +#define ST7637_RASET 0x2B +#define ST7637_RAMWR 0x2C +#define ST7637_RGBSET 0x2D +#define ST7637_RAMRD 0x2E + +#define ST7637_PTLAR 0x30 +#define ST7637_SCRLAR 0x33 +#define ST7637_TEOFF 0x34 +#define ST7637_TEON 0x35 +#define ST7637_MADCTR 0x36 +#define ST7637_VSCSAD 0x37 +#define ST7637_IDMOFF 0x38 +#define ST7637_IDMON 0x39 +#define ST7637_COLMOD 0x3A + +#define ST7637_RDID1 0xDA +#define ST7637_RDID2 0xDB +#define ST7637_RDID3 0xDC + +#define ST7637_DUTYSET 0xB0 +#define ST7637_FIRSTCOM 0xB1 +#define ST7637_OSCDIV 0xB3 +#define ST7637_PTLMOD 0xB4 +#define ST7637_NLINVSET 0xB5 +#define ST7637_COMSCANDIR 0xB7 +#define ST7637_RMWIN 0xB8 +#define ST7637_RMWOUT 0xB9 + +#define ST7637_VOPSET 0xC0 +#define ST7637_VOPOFSETINC 0xC1 +#define ST7637_VOPOFSETDEC 0xC2 +#define ST7637_BIASSEL 0xC3 +#define ST7637_BSTBMPXSEL 0xC4 +#define ST7637_BSTEFFSEL 0xC5 +#define ST7637_VOPOFFSET 0xC7 +#define ST7637_VGSORCSEL 0xCB + +#define ST7637_ID1SET 0xCC +#define ST7637_ID2SET 0xCD +#define ST7637_ID3SET 0xCE + +#define ST7637_ANASET 0xD0 +#define ST7637_AUTOLOADSET 0xD7 +#define ST7637_RDTSTSTATUS 0xDE + +#define ST7637_EPCTIN 0xE0 +#define ST7637_EPCTOUT 0xE1 +#define ST7637_EPMWR 0xE2 +#define ST7637_EPMRD 0xE3 +#define ST7637_MTPSEL 0xE4 +#define ST7637_ROMSET 0xE5 +#define ST7637_HPMSET 0xEB + +#define ST7637_FRMSEL 0xF0 +#define ST7637_FRM8SEL 0xF1 +#define ST7637_TMPRNG 0xF2 +#define ST7637_TMPHYS 0xF3 +#define ST7637_TEMPSEL 0xF4 +#define ST7637_THYS 0xF7 +#define ST7637_FRAMESET 0xF9 + +#define ST7637_MAXCOL 0x83 +#define ST7637_MAXPAG 0x83 + +#endif /*__LCD_H */ diff --git a/20080212/Demo/CORTEX_STM32F103_Primer_GCC/ST_Code/led.c b/20080212/Demo/CORTEX_STM32F103_Primer_GCC/ST_Code/led.c new file mode 100644 index 000000000..107ac66c4 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_Primer_GCC/ST_Code/led.c @@ -0,0 +1,210 @@ +/********************* (C) COPYRIGHT 2007 RAISONANCE S.A.S. *******************/ +/** +* +* @file led.c +* @brief LED management. +* @author IB +* @date 07/2007 +* +**/ +/******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "circle.h" + +/// @cond Internal + +/* Private variables ---------------------------------------------------------*/ + +int GreenLED_Counter = 0; +int RedLED_Counter = 0; +enum LED_mode GreenLED_mode = LED_UNDEF; +enum LED_mode RedLED_mode = LED_UNDEF; +enum LED_mode GreenLED_newmode = LED_OFF; +enum LED_mode RedLED_newmode = LED_OFF; +const int HalfPeriod_LF = 200; +const int HalfPeriod_HF = 50; +const int Period_LF = 200 * 2; +const int Period_HF = 50 * 2; + +/* Public functions for CircleOS ---------------------------------------------*/ + +/******************************************************************************* +* +* LED_Init +* +*******************************************************************************/ +/** +* +* Initialization of the GPIOs for the LEDs +* +* @note Is called by CircleOS startup. +* +**/ +/******************************************************************************/ +void LED_Init( void ) + { + GPIO_InitTypeDef GPIO_InitStructure; + + /* Enable LED GPIO clock */ + RCC_APB2PeriphClockCmd( RCC_APB2Periph_GPIOB, ENABLE ); + + /* Configure LED pins as output push-pull */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 ; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + + GPIO_Init( GPIOB, &GPIO_InitStructure ); + } + +/******************************************************************************* +* +* LED_Handler +* +*******************************************************************************/ +/** +* +* Called by the CircleOS scheduler to manage the states of the LEDs. +* LEDs may be on, off or blinking according to their state. +* +**/ +/******************************************************************************/ +void LED_Handler( void ) + { + LED_Handler_hw(LED_GREEN); + LED_Handler_hw(LED_RED); + } + +/******************************************************************************* +* +* LED_Handler +* +*******************************************************************************/ +/** +* +* Called by the CircleOS scheduler to manage the states of the LEDs. +* LEDs may be on, off or blinking according to their state. +* +* @param[in] id A LED_id indicating the LED to take care of. +* +**/ +/******************************************************************************/ +void LED_Handler_hw( enum LED_id id ) + { + int counter; + enum LED_mode mode; + + // Choose the right LED parameters. + if( id == LED_GREEN ) + { + counter = GreenLED_Counter; + mode = GreenLED_newmode; + } + else + { + counter = RedLED_Counter; + mode = RedLED_newmode; + } + + switch( mode ) + { + case LED_OFF : + case LED_ON : + if( ( ( id == LED_GREEN ) && ( GreenLED_mode == mode ) ) || + ( ( id == LED_RED ) && ( RedLED_mode == mode ) ) ) + { + return; + } + + if( id == LED_GREEN ) + { + GPIO_WriteBit( GPIOB, GPIO_Pin_8, ( mode == LED_OFF ) ? Bit_RESET : Bit_SET ); + + GreenLED_mode = mode; + } + else if( id == LED_RED ) + { + GPIO_WriteBit( GPIOB, GPIO_Pin_9, ( mode == LED_OFF ) ? Bit_RESET : Bit_SET ); + + RedLED_mode = mode; + } + + counter = -1; + break; + + case LED_BLINKING_HF : + counter++; + + if( counter == HalfPeriod_HF ) + { + GPIO_WriteBit( GPIOB, ( id == LED_RED ) ? GPIO_Pin_9 : GPIO_Pin_8, Bit_SET ); + } + else if( ( counter < 0 ) || ( counter >= Period_HF ) ) + { + GPIO_WriteBit( GPIOB, ( id == LED_RED ) ? GPIO_Pin_9 : GPIO_Pin_8, Bit_RESET ); + + counter = 0; + } + break; + + case LED_BLINKING_LF : + counter++; + + if( counter == HalfPeriod_LF ) + { + GPIO_WriteBit( GPIOB, ( id == LED_RED ) ? GPIO_Pin_9 : GPIO_Pin_8, Bit_SET ); + } + + else if( ( counter < 0 ) || ( counter >= Period_LF ) ) + { + GPIO_WriteBit( GPIOB, ( id == LED_RED ) ? GPIO_Pin_9 : GPIO_Pin_8, Bit_RESET ); + + counter = 0; + } + break; + + default : + break; + } + + if( id == LED_GREEN ) + { + GreenLED_Counter = counter; + GreenLED_mode = mode; + } + else + { + RedLED_Counter = counter; + RedLED_mode = mode; + } + } + +/// @endcond + +/* Public functions ----------------------------------------------------------*/ + +/******************************************************************************* +* +* LED_Set +* +*******************************************************************************/ +/** +* +* Set a specified LED in a specified mode. +* +* @param[in] id A LED_id specifying the LED to change the mode. +* @param[in] mode A LED_mode describing the new LED mode. +* +**/ +/******************************************************************************/ +void LED_Set( enum LED_id id, enum LED_mode mode ) + { + if( id == LED_GREEN ) + { + GreenLED_newmode = mode; + } + else if( id == LED_RED ) + { + RedLED_newmode = mode; + } + } diff --git a/20080212/Demo/CORTEX_STM32F103_Primer_GCC/ST_Code/mems.c b/20080212/Demo/CORTEX_STM32F103_Primer_GCC/ST_Code/mems.c new file mode 100644 index 000000000..e226cd9fa --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_Primer_GCC/ST_Code/mems.c @@ -0,0 +1,605 @@ +/********************* (C) COPYRIGHT 2007 RAISONANCE S.A.S. *******************/ +/** +* +* @file mems.c +* @brief Mems Initialization and management +* @author FL +* @date 07/2007 +* @version 1.1 +* @date 10/2007 +* @version 1.5 various corrections reported by Ron Miller +* +**/ +/******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "circle.h" + +/// @cond Internal + +/* Private define ------------------------------------------------------------*/ +#define RDOUTXL 0xE8 /*!< Multiple Read from OUTXL */ +#define WRCTRL_REG1 0x20 /*!< Single Write CTRL_REG */ +#define RDCTRL_REG1 0xA0 /*!< Single Read CTRL_REG */ +#define RDID 0x8F /*!< Single Read WHO_AM_I */ +#define LOW 0x00 /*!< ChipSelect line low */ +#define HIGH 0x01 /*!< ChipSelect line high */ +#define DUMMY_BYTE 0xA5 +#define MEMS_DIVIDER 1 +#define MEMS_TESTING_DIVIDER 101 +#define MARGIN 500 +#define DELAY_REACT 20 +#define MIN_REACT 15 +#define DIV_REACT 10 +#define GRAD_SHOCK 200000 + +/* Private variables ---------------------------------------------------------*/ +tMEMS_Info MEMS_Info = {0}; // structure definition in circle.h +int TestingActive = 0; +int StartingFromResetOrShockCounter = 1000; +int TimeCounterForDoubleClick = 0; +int TimeLastShock = 0; +static int divider = 0; +static Rotate_H12_V_Match_TypeDef previous_Screen_Orientation; +u32 Gradient2; + +//Filtering +unsigned N_filtering = 0; + +//Gradient +s16 GradX = 0; +s16 GradY = 0; +s16 GradZ = 0; + +// Pointer move: +// each coordinate (X, Y and Z) is described by 3 variables where suffix means: +// f = flag to indicate that a move has been done. Cleared by the Ptr Manager when acknowledged. +// i = amplitude of the move (Grad / 10) +// t = delay to accept the counter reaction +int fMovePtrX; +int iMovePtrX; +int tMovePtrX; +int fMovePtrY; +int iMovePtrY; +int tMovePtrY; +int fMovePtrZ; +int iMovePtrZ; +int tMovePtrZ; + +s16 XInit = 0; +s16 YInit = 0; +s16 ZInit = 0; + +/* Private function prototypes -----------------------------------------------*/ +static void MEMS_ChipSelect( u8 State ); +static u8 MEMS_SendByte( u8 byte ); +static void MEMS_WriteEnable( void ); +static u32 MEMS_ReadOutXY( void ); +static void MEMS_WakeUp( void ); + +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* +* MEMS_WakeUp +* +*******************************************************************************/ +/** +* Wake Up Mems. +* +**/ +/******************************************************************************/ +static void MEMS_WakeUp( void ) + { + u8 reg_val; + + /* read RDCTRL_REG1 */ + + /* Chip Select low */ + MEMS_ChipSelect( LOW ); + + /* Send "RDCTRL_REG1" instruction */ + MEMS_SendByte( RDCTRL_REG1 ); + + reg_val = MEMS_SendByte( DUMMY_BYTE ); + + /* Chip Select high */ + MEMS_ChipSelect( HIGH ); + + /* SET P0:P1 to '11' */ + /* 0xC0 to wake up and 0x30 for full speed frequency (640 Hz). */ + reg_val = reg_val | 0xC0 | 0x30; + + /* Chip Select low */ + MEMS_ChipSelect( LOW ); + + /* Send "WRCTRL_REG1" instruction */ + MEMS_SendByte( WRCTRL_REG1 ); + MEMS_SendByte( reg_val ); + + /* Chip Select high */ + MEMS_ChipSelect( HIGH ); + } + +/******************************************************************************* +* +* MEMS_ReadOutXY +* +*******************************************************************************/ +/** +* Reads X and Y Out. +* +* @return An unsigned 32 bit word with the highest 16 bits containing the Y +* and the lowest 16 bits the X. +* +**/ +/******************************************************************************/ +static u32 MEMS_ReadOutXY( void ) + { + u8 OutXL; + u8 OutXH; + u8 OutYL; + u8 OutYH; + u8 OutZL; + u8 OutZH; + + /* Chip Select low */ + MEMS_ChipSelect( LOW ); + + /* Send "RDOUTXL" instruction */ + MEMS_SendByte( RDOUTXL ); + + /* Read a byte */ + OutXL = MEMS_SendByte( DUMMY_BYTE ); + + /* Read a byte */ + OutXH = MEMS_SendByte( DUMMY_BYTE ); + + /* Read a byte */ + OutYL = MEMS_SendByte( DUMMY_BYTE ); + + /* Read a byte */ + OutYH = MEMS_SendByte( DUMMY_BYTE ); + + /* Read a byte */ + OutZL = MEMS_SendByte( DUMMY_BYTE ); + + /* Read a byte */ + OutZH = MEMS_SendByte( DUMMY_BYTE ); + + MEMS_Info.OutX = OutXL + ( OutXH << 8 ); + MEMS_Info.OutY = OutYL + ( OutYH << 8 ); + MEMS_Info.OutZ = OutZL + ( OutZH << 8 ); + + /* Chip Select high */ + MEMS_ChipSelect( HIGH ); + + MEMS_Info.OutX_F4 += ( MEMS_Info.OutX - ( MEMS_Info.OutX_F4 >> 2 ) ); // Filter on 4 values. + MEMS_Info.OutY_F4 += ( MEMS_Info.OutY - ( MEMS_Info.OutY_F4 >> 2 ) ); // Filter on 4 values. + MEMS_Info.OutZ_F4 += ( MEMS_Info.OutZ - ( MEMS_Info.OutZ_F4 >> 2 ) ); // Filter on 4 values. + + MEMS_Info.OutX_F16 += ( MEMS_Info.OutX - ( MEMS_Info.OutX_F16 >> 4 ) ); // Filter on 16 values. + MEMS_Info.OutY_F16 += ( MEMS_Info.OutY - ( MEMS_Info.OutY_F16 >> 4 ) ); // Filter on 16 values. + MEMS_Info.OutZ_F16 += ( MEMS_Info.OutZ - ( MEMS_Info.OutZ_F16 >> 4 ) ); // Filter on 16 values. + + MEMS_Info.OutX_F64 += ( MEMS_Info.OutX - ( MEMS_Info.OutX_F64 >> 6 ) ); // Filter on 64 values. + MEMS_Info.OutY_F64 += ( MEMS_Info.OutY - ( MEMS_Info.OutY_F64 >> 6 ) ); // Filter on 64 values. + MEMS_Info.OutZ_F64 += ( MEMS_Info.OutZ - ( MEMS_Info.OutZ_F64 >> 6 ) ); // Filter on 64 values. + + MEMS_Info.OutX_F256 += ( MEMS_Info.OutX - ( MEMS_Info.OutX_F256 >> 8) ); // Filter on 256 values. + MEMS_Info.OutY_F256 += ( MEMS_Info.OutY - ( MEMS_Info.OutY_F256 >> 8) ); // Filter on 256 values. + MEMS_Info.OutZ_F256 += ( MEMS_Info.OutZ - ( MEMS_Info.OutZ_F256 >> 8) ); // Filter on 256 values. + + if( N_filtering < 256 ) + { + // Just to validate the calculated average values. + N_filtering++; + } + + return ( MEMS_Info.OutX + ( MEMS_Info.OutY << 16 ) ); + } + +/******************************************************************************* +* +* MEMS_ChipSelect +* +*******************************************************************************/ +/** +* Selects or deselects the MEMS device. +* +* @param[in] State Level to be applied on ChipSelect pin. +* +**/ +/******************************************************************************/ +static void MEMS_ChipSelect( u8 State ) + { + /* Set High or low the chip select line on PA.4 pin */ + GPIO_WriteBit( GPIOD, GPIO_Pin_2, (BitAction)State ); + } + +/******************************************************************************* +* +* MEMS_SendByte +* +*******************************************************************************/ +/** +* Sends a byte through the SPI interface and return the byte received from +* the SPI bus. +* +* @param[in] byte The byte to send to the SPI interface. +* +* @return The byte returned by the SPI bus. +* +**/ +/******************************************************************************/ +static u8 MEMS_SendByte( u8 byte ) + { + /* Loop while DR register in not emplty */ + while( SPI_GetFlagStatus( SPI2, SPI_FLAG_TXE ) == RESET ); + + /* Send byte through the SPI2 peripheral */ + SPI_SendData( SPI2, byte ); + + /* Wait to receive a byte */ + while( SPI_GetFlagStatus( SPI2, SPI_FLAG_RXNE ) == RESET ); + + /* Return the byte read from the SPI bus */ + return SPI_ReceiveData( SPI2 ); + } + +/* Public functions for CircleOS ---------------------------------------------*/ + +/******************************************************************************* +* +* MEMS_Init +* +*******************************************************************************/ +/** +* +* Initializes the peripherals used by the SPI MEMS driver. +* +* @attention This function must NOT be called by the user. +* +**/ +/******************************************************************************/ +void MEMS_Init(void) +{ + SPI_InitTypeDef SPI_InitStructure; + GPIO_InitTypeDef GPIO_InitStructure; + + /* Configure PC6 and PC7 as Output push-pull For MEMS*/ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_7; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + + GPIO_Init( GPIOC, &GPIO_InitStructure ); + + /* Enable SPI2 and GPIOA clocks */ + RCC_APB1PeriphClockCmd( RCC_APB1Periph_SPI2, ENABLE ); + RCC_APB2PeriphClockCmd( RCC_APB2Periph_GPIOB, ENABLE ); + RCC_APB2PeriphClockCmd( RCC_APB2Periph_GPIOD, ENABLE ); + + /* Configure SPI2 pins: SCK, MISO and MOSI */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + + GPIO_Init( GPIOB, &GPIO_InitStructure ); + + /* Configure PD2 as Output push-pull, used as MEMS Chip select */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + + GPIO_Init( GPIOD, &GPIO_InitStructure ); + + /* SPI2 configuration */ + SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; + SPI_InitStructure.SPI_Mode = SPI_Mode_Master; + SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; + SPI_InitStructure.SPI_CPOL = SPI_CPOL_High; + SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge; + SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; + SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_256; + SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; + SPI_InitStructure.SPI_CRCPolynomial = 7; + + SPI_Init( SPI2, &SPI_InitStructure ); + + /* Enable SPI2 */ + SPI_Cmd( SPI2, ENABLE ); + + if( MEMS_ReadID() != 0x3A ) + { + int i; + + // Try to resynchronize + for( i = 0 ; i < 17 ; i++ ) + { + /* Configure SPI2 pins: SCK, MISO and MOSI */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13 | GPIO_Pin_15; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + + GPIO_Init( GPIOB, &GPIO_InitStructure ); + GPIO_WriteBit( GPIOB, GPIO_Pin_15, HIGH ); + MEMS_ChipSelect( LOW ); + + GPIO_WriteBit( GPIOB, GPIO_Pin_13, LOW ); + GPIO_WriteBit( GPIOB, GPIO_Pin_13, HIGH ); + MEMS_ChipSelect( HIGH ); + + /* Configure again PB. SCK as SPI2 pin */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13 | GPIO_Pin_15; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + + GPIO_Init( GPIOB, &GPIO_InitStructure ); + if ( MEMS_ReadID() == 0x3A ) + { + break; + } + } + + if( i == 17 ) + { + DRAW_DisplayString( 1, 50, "Test MEM ID Failed", 17 ); + } + } + + /* Read for the first time */ + N_filtering = 0; + + MEMS_ReadOutXY(); + + MEMS_Info.OutX_F4 = MEMS_Info.OutX_F16 = MEMS_Info.OutX_F64 = MEMS_Info.OutX_F256 = MEMS_Info.OutX; + MEMS_Info.OutY_F4 = MEMS_Info.OutY_F16 = MEMS_Info.OutY_F64 = MEMS_Info.OutY_F256 = MEMS_Info.OutY; + MEMS_Info.OutZ_F4 = MEMS_Info.OutZ_F16 = MEMS_Info.OutZ_F64 = MEMS_Info.OutZ_F256 = MEMS_Info.OutZ; + + /* Init X and Y*/ + MEMS_GetPosition( &XInit, &YInit ); + + /* Wake Up Mems*/ + MEMS_WakeUp(); +} + +/******************************************************************************* +* +* MEMS_Handler +* +*******************************************************************************/ +/** +* +* Called by the CircleOS scheduler to manage the MEMS. The Circle beeps if the +* MEMS is shocked. +* +* @attention This function must NOT be called by the user. +* +**/ +/******************************************************************************/ +void MEMS_Handler( void ) + { + char buffer [20]; + int i; + int ofs_disp = 0; + + if( StartingFromResetOrShockCounter ) + { + StartingFromResetOrShockCounter--; + } + TimeCounterForDoubleClick++; + + MEMS_ReadOutXY(); + + // Evaluate gradients + GradX = ( MEMS_Info.OutX_F4 >> 2 ) - MEMS_Info.OutX; + GradY = ( MEMS_Info.OutY_F4 >> 2 ) - MEMS_Info.OutY; + GradZ = ( MEMS_Info.OutZ_F4 >> 2 ) - MEMS_Info.OutZ; + + // Decide whether a direction is selected + if( tMovePtrX == 0 ) + { + if( ( GradX > MIN_REACT ) || ( GradX < -MIN_REACT ) ) + { + iMovePtrX = GradX / DIV_REACT; + tMovePtrX = DELAY_REACT; + fMovePtrX = 1; + } + } + else + { + tMovePtrX--; + } + + if( tMovePtrY == 0 ) + { + if( ( GradY > MIN_REACT ) || ( GradY < -MIN_REACT ) ) + { + iMovePtrY = GradY / DIV_REACT; //FL071012 rrm fix + tMovePtrY = DELAY_REACT; + fMovePtrY = 1; + } + } + else + { + tMovePtrY--; + } + + if( tMovePtrZ==0 ) + { + if( ( GradZ > MIN_REACT ) || ( GradY < -MIN_REACT ) ) + { + iMovePtrZ = GradZ / DIV_REACT; + tMovePtrZ = DELAY_REACT; + fMovePtrZ = 1; + } + } + else + { + tMovePtrZ--; + } + + Gradient2 = (s32)GradX * (s32)GradX + (s32)GradY * (s32)GradY + (s32)GradZ * (s32)GradZ; + + // MEMS is shocked, let's beep! + if( ( Gradient2 > GRAD_SHOCK ) && ( BUZZER_GetMode() == BUZZER_OFF ) && ( StartingFromResetOrShockCounter == 0 ) ) + { + MEMS_Info.Shocked++; +/*FL071007 = 1; + Suggested by Bob Seabrook: a further posiblity is to increment Shocked rather than just setting it + So it can still be tested for non zero as before but one can get more + info from the int without extra cost. */ + +#define DELAY_BETWEEN_TWO_SHOCK 20 +#define MAX_DELAY_FOR_DOUBLECLICK 150 + StartingFromResetOrShockCounter = DELAY_BETWEEN_TWO_SHOCK; //< filter: short delay before detecting the next shock + if ( (TimeCounterForDoubleClick - TimeLastShock) < MAX_DELAY_FOR_DOUBLECLICK ) + { + MEMS_Info.DoubleClick++; + TimeLastShock = 0; + } + else + { + TimeLastShock = TimeCounterForDoubleClick; + } + BUZZER_SetMode( BUZZER_SHORTBEEP ); + } + } + +/******************************************************************************* +* +* MEMS_ReadID +* +*******************************************************************************/ +/** +* Reads SPI chip identification. +* +* @return The SPI chip identification. +* +**/ +/******************************************************************************/ +u8 MEMS_ReadID( void ) + { + u8 Temp = 0; + + /* Chip Select low */ + MEMS_ChipSelect( LOW ); + + /* Send "RDID" instruction */ + MEMS_SendByte( RDID ); + + /* Read a byte from the MEMS */ + Temp = MEMS_SendByte( DUMMY_BYTE ); + + /* Chip Select low */ + MEMS_ChipSelect( HIGH ); + + return Temp; + } + +/// @endcond + +/* Public functions ----------------------------------------------------------*/ + +/******************************************************************************* +* +* MEMS_GetPosition +* +*******************************************************************************/ +/** +* +* Returns the current (relative) position of the Primer. +* Only X-Y axis are considered here. +* +* @param[out] pX Current horizontal coordinate. +* @param[out] pY Current vertical coordinate. +* +* @warning The (0x0) point in on the low left corner. +* @note For absolute position information use MEMS_GetInfo() +* +**/ +/******************************************************************************/ +void MEMS_GetPosition( s16* pX, s16* pY ) + { + *pX = MEMS_Info.OutX - XInit; + *pY = MEMS_Info.OutY - YInit; + } + +/******************************************************************************* +* +* MEMS_GetRotation +* +*******************************************************************************/ +/** +* +* Returns current screen orientation. +* +* @param[out] pH12 Current screen orientation. +* +**/ +/******************************************************************************/ +void MEMS_GetRotation( Rotate_H12_V_Match_TypeDef* pH12 ) + { + s16 sX = MEMS_Info.OutX; + s16 sY = MEMS_Info.OutY; + + if( ( ( sX <= -MARGIN ) && ( sY <= 0 ) && (sX<=sY ) ) || + ( ( sX <=- MARGIN ) && ( sY > 0) && (sX <= (-sY ) ) ) ) + { + // 1st case: x<0, |x|>y => H12 = V9 + *pH12 = V9; + } + else if( ( ( sY <= -MARGIN ) && ( sX <= 0 ) && ( sY <= sX ) ) || + ( ( sY <= -MARGIN ) && ( sX > 0 ) && ( sY <= (-sX ) ) ) ) + { + // 2nd case: y<0, |y|>x => H12 = V12 + *pH12 = V12; + } + else if( ( ( sX >= MARGIN ) && ( sY <= 0 ) && ( sX >= (-sY) ) ) || + ( ( sX >= MARGIN ) && ( sY > 0 ) && ( sX >= sY ) ) ) + { + // 3rd case: x>0, |x|>y => H12=V3 + *pH12 = V3; + } + else if( ( ( sY >= MARGIN ) && ( sX <= 0 ) && ( sY >= (-sX ) ) ) || + ( ( sY >= MARGIN ) && ( sX > 0 ) && ( sY >= sX ) ) ) + { + // 4th case: y>0, |y|>x => H12=V6 + *pH12 = V6; + } + } + +/******************************************************************************* +* +* MEMS_SetNeutral +* +*******************************************************************************/ +/** +* +* Set current position as "neutral position". +* +**/ +/******************************************************************************/ +void MEMS_SetNeutral( void ) + { + // Set Neutral position. + MEMS_GetPosition( &XInit, &YInit ); + } + +/******************************************************************************* +* +* MEMS_GetInfo +* +*******************************************************************************/ +/** +* +* Return the current MEMS information (state, absolute position...). +* +* @return a pointer to tMEMS_Info +* +**/ +/******************************************************************************/ +tMEMS_Info* MEMS_GetInfo( void ) + { + return &MEMS_Info; + } diff --git a/20080212/Demo/CORTEX_STM32F103_Primer_GCC/ST_Code/pointer.c b/20080212/Demo/CORTEX_STM32F103_Primer_GCC/ST_Code/pointer.c new file mode 100644 index 000000000..02fe9834b --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_Primer_GCC/ST_Code/pointer.c @@ -0,0 +1,901 @@ +/********************* (C) COPYRIGHT 2007 RAISONANCE S.A.S. *******************/ +/** +* +* @file pointer.c +* @brief Various utilities for the pointer management for STM32-primer. +* @author FL +* @date 07/2007 +* @version 1.1 +* @date 10/2007 +* @version 1.5 various corrections reported by Ron Miller to suppress jittery +* +* +**/ +/******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "circle.h" + +/// @cond Internal + +/* Private define ------------------------------------------------------------*/ +#define POS_MIN 0 +#define POS_MAX (SCREEN_WIDTH - POINTER_WIDTH - 1) +#define POINTER_DIVIDER 50 +#define POINTER_DEFAULT_COLOR RGB_BLUE + +// defines for pointer move +#define ANGLEPAUSE 500 +#define DEFAULT_ANGLESTART 25 +#define MIN_ANGLE_FOR_SHIFT_UP (ANGLEPAUSE+CurrentAngleStart) +#define MIN_ANGLE_FOR_SHIFT_DOWN (ANGLEPAUSE-CurrentAngleStart) +#define MIN_ANGLE_FOR_SHIFT_RIGHT (signed)(0+CurrentAngleStart) +#define MIN_ANGLE_FOR_SHIFT_LEFT (signed)(0-CurrentAngleStart) +#define DEFAULT_SPEED_ON_ANGLE 60 + +/* Private variables ---------------------------------------------------------*/ +static int divider = 0; + +unsigned char BallPointerBmp[ POINTER_WIDTH ] = { 0x38, 0x7C, 0xFF, 0xFF, 0xFF, 0x7C, 0x38 } ; +unsigned char locbuf[ POINTER_WIDTH ]; +unsigned char DefaultAreaStore[ 2 * POINTER_WIDTH * POINTER_WIDTH ]; + +// Variables for pointer. +u8* CurrentPointerBmp = 0; +u8 CurrentPointerWidth = 0; +u8 CurrentPointerHeight = 0; +u16 CurrentSpeedOnAngle = DEFAULT_SPEED_ON_ANGLE; +u32 CurrentAngleStart = DEFAULT_ANGLESTART ; +unsigned char* ptrAreaStore = DefaultAreaStore; +u16 CurrentPointerColor = POINTER_DEFAULT_COLOR; +enum POINTER_mode Pointer_Mode = POINTER_UNDEF; +enum POINTER_state Pointer_State = POINTER_S_UNDEF; + +s16 OUT_X; +s16 OUT_Y; + +// Init pointer Info Structure (structure definition in circle.h) +tPointer_Info POINTER_Info = { + SCREEN_WIDTH - POINTER_WIDTH / 2, + SCREEN_WIDTH - POINTER_WIDTH / 2, + 0, + 0} ; + +/* Private function prototypes -----------------------------------------------*/ +static int POINTER_Move ( void ); + +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* +* Pointer_Move +* +*******************************************************************************/ +/** +* Moves LCD pointer according to Mems indications. +* +* @retval 0 The pointer resides in the screen +* @retval -1 The pointer touche the screen edges. +* +**/ +/******************************************************************************/ +static int POINTER_Move( void ) + { + int res = 0; + s16 oldPointer_xPos = POINTER_Info.xPos; + s16 oldPointer_yPos = POINTER_Info.yPos; + s16 unmodied_shift_PosX; + s16 unmodied_shift_PosY; + signed outx = MEMS_Info.OutX_F16 >> 4; + signed outy = MEMS_Info.OutY_F16 >> 4; + + POINTER_Info.shift_PosX = POINTER_Info.shift_PosY = 0; + + // The move depends on the screen orientation + switch( LCD_GetScreenOrientation() ) + { + // north + case V12 : + MEMS_Info.RELATIVE_X = outx; + MEMS_Info.RELATIVE_Y = outy; + + if( outx > MIN_ANGLE_FOR_SHIFT_RIGHT ) + { + POINTER_Info.shift_PosX = ( outx - MIN_ANGLE_FOR_SHIFT_RIGHT ); + } + else if( outx < MIN_ANGLE_FOR_SHIFT_LEFT ) + { + POINTER_Info.shift_PosX = ( outx - MIN_ANGLE_FOR_SHIFT_LEFT ); + } + + if( outy < -MIN_ANGLE_FOR_SHIFT_UP ) + { + POINTER_Info.shift_PosY = ( outy + MIN_ANGLE_FOR_SHIFT_UP ); + } + else if( outy > -MIN_ANGLE_FOR_SHIFT_DOWN ) + { + POINTER_Info.shift_PosY = ( outy + MIN_ANGLE_FOR_SHIFT_DOWN ); + } + break; + + // West + case V9 : + MEMS_Info.RELATIVE_X = -( outy ); + MEMS_Info.RELATIVE_Y = outx; + + if( outy > MIN_ANGLE_FOR_SHIFT_RIGHT ) + { + POINTER_Info.shift_PosX = -( outy - MIN_ANGLE_FOR_SHIFT_RIGHT ); + } + else if( outy < MIN_ANGLE_FOR_SHIFT_LEFT ) + { + POINTER_Info.shift_PosX = -( outy - MIN_ANGLE_FOR_SHIFT_LEFT ); + } + + if( outx < -MIN_ANGLE_FOR_SHIFT_UP ) + { + POINTER_Info.shift_PosY = ( outx + MIN_ANGLE_FOR_SHIFT_UP ); + } + else if( outx > -MIN_ANGLE_FOR_SHIFT_DOWN ) + { + POINTER_Info.shift_PosY = ( outx + MIN_ANGLE_FOR_SHIFT_DOWN ); + } + break; + + // South + case V6 : + MEMS_Info.RELATIVE_X = -( outx ); + MEMS_Info.RELATIVE_Y = -( outy ); + + if( outx > MIN_ANGLE_FOR_SHIFT_RIGHT ) + { + POINTER_Info.shift_PosX = ( MIN_ANGLE_FOR_SHIFT_RIGHT - outx ); + } + else if( outx < MIN_ANGLE_FOR_SHIFT_LEFT ) + { + POINTER_Info.shift_PosX = ( MIN_ANGLE_FOR_SHIFT_LEFT - outx ); + } + + if( outy > MIN_ANGLE_FOR_SHIFT_UP ) + { + POINTER_Info.shift_PosY = -( outy - MIN_ANGLE_FOR_SHIFT_UP ); + } + else if( outy < MIN_ANGLE_FOR_SHIFT_DOWN ) + { + POINTER_Info.shift_PosY = +( MIN_ANGLE_FOR_SHIFT_DOWN - outy ); + } + break; + + // East + case V3 : + MEMS_Info.RELATIVE_X = outy; + MEMS_Info.RELATIVE_Y = -( outx ); + + if( outy > MIN_ANGLE_FOR_SHIFT_RIGHT ) + { + POINTER_Info.shift_PosX = ( outy - MIN_ANGLE_FOR_SHIFT_RIGHT ); + } + else if( outy < MIN_ANGLE_FOR_SHIFT_LEFT ) + { + POINTER_Info.shift_PosX = ( outy - MIN_ANGLE_FOR_SHIFT_LEFT ); + } + + if( outx > MIN_ANGLE_FOR_SHIFT_UP ) + { + POINTER_Info.shift_PosY = ( MIN_ANGLE_FOR_SHIFT_UP - outx); + } + else if( outx < MIN_ANGLE_FOR_SHIFT_DOWN ) + { + POINTER_Info.shift_PosY = ( MIN_ANGLE_FOR_SHIFT_DOWN - outx ); + } + + default : + break; + } + + unmodied_shift_PosX = POINTER_Info.shift_PosX; + unmodied_shift_PosY = POINTER_Info.shift_PosY; + + POINTER_Info.shift_PosX /= CurrentSpeedOnAngle; + POINTER_Info.shift_PosY /= CurrentSpeedOnAngle; + + if( Pointer_Mode == POINTER_APPLICATION ) + { + if ( Application_Pointer_Mgr ) + { + Application_Pointer_Mgr( POINTER_Info.shift_PosX, POINTER_Info.shift_PosY ); + } + + return 0; + } + + POINTER_Info.xPos += POINTER_Info.shift_PosX; + POINTER_Info.yPos += POINTER_Info.shift_PosY; + + if( POINTER_Info.xPos < POINTER_Info.X_PosMin ) + { + POINTER_Info.xPos = POINTER_Info.X_PosMin; + } + + if( POINTER_Info.xPos > POINTER_Info.X_PosMax ) + { + POINTER_Info.xPos = POINTER_Info.X_PosMax; + } + + if( POINTER_Info.yPos < POINTER_Info.Y_PosMin ) + { + POINTER_Info.yPos = POINTER_Info.Y_PosMin; + } + + if( POINTER_Info.yPos > POINTER_Info.Y_PosMax ) + { + POINTER_Info.yPos = POINTER_Info.Y_PosMax; + } + + if( ( Pointer_Mode != POINTER_MENU ) && ( Pointer_Mode != POINTER_RESTORE_LESS ) && + ( ( oldPointer_xPos != POINTER_Info.xPos ) || ( oldPointer_yPos != POINTER_Info.yPos ) ) ) + { + // Use default area. + POINTER_SetCurrentAreaStore( 0 ); + + // Restore previously drawn area. + POINTER_Restore( oldPointer_xPos, oldPointer_yPos, POINTER_WIDTH, POINTER_WIDTH ); + + // Save new area and draw pointer + POINTER_Save( POINTER_Info.xPos, POINTER_Info.yPos, POINTER_WIDTH, POINTER_WIDTH ); + POINTER_Draw( POINTER_Info.xPos, POINTER_Info.yPos, POINTER_WIDTH, POINTER_WIDTH, CurrentPointerBmp ); + } + + if( ( Pointer_Mode == POINTER_RESTORE_LESS ) && + ( ( oldPointer_xPos != POINTER_Info.xPos ) || ( oldPointer_yPos != POINTER_Info.yPos ) ) ) + { + // Use default area. + POINTER_SetCurrentAreaStore( 0 ); + + // Restore previously drawn area. + POINTER_Restore( oldPointer_xPos, oldPointer_yPos, CurrentPointerWidth, CurrentPointerHeight ); + + // Save new area and draw pointer + POINTER_Save( POINTER_Info.xPos, POINTER_Info.yPos, CurrentPointerWidth, CurrentPointerHeight ); + POINTER_Draw( POINTER_Info.xPos, POINTER_Info.yPos, CurrentPointerWidth, CurrentPointerHeight, CurrentPointerBmp ); + } + + // Is the pointer touching one edge of the screen ? + if( ( POINTER_Info.xPos == POS_MIN ) || ( POINTER_Info.yPos == POS_MIN ) || + ( POINTER_Info.xPos == POS_MAX ) || ( POINTER_Info.yPos == POS_MAX ) ) + { + res = -1; + } + + return res; + } + +/* Public functions for CircleOS ---------------------------------------------*/ + +/******************************************************************************* +* +* POINTER_Init +* +*******************************************************************************/ +/** +* Initialize pointer. Called at CircleOS startup. Set default pointer at the +* middle of the screen and allows it to move into the whole screen. +* +* @attention This function must NOT be called by the user. +* +**/ +/******************************************************************************/ +void POINTER_Init( void ) + { + // Increase pointer sensibility. + POINTER_SetCurrentSpeedOnAngle( DEFAULT_SPEED_ON_ANGLE ); + POINTER_SetCurrentAngleStart( DEFAULT_ANGLESTART ); + POINTER_SetCurrentPointer( POINTER_WIDTH, POINTER_WIDTH, BallPointerBmp ); + POINTER_SetMode( POINTER_ON ); + POINTER_SetPos( 56, 56 ); + POINTER_SetRectScreen(); + + CurrentPointerColor = POINTER_DEFAULT_COLOR; + } + +/******************************************************************************* +* +* POINTER_Handler +* +*******************************************************************************/ +/** +* +* Called by the CircleOS scheduler to manage the pointer. +* +* @attention This function must NOT be called by the user. +* +**/ +/******************************************************************************/ +void POINTER_Handler( void ) + { + switch( Pointer_Mode ) + { + // Nothing to do! + case POINTER_OFF : + case POINTER_UNDEF: + return; + } + + // Where is the MEMS ? + MEMS_GetPosition( &OUT_X, &OUT_Y ); + + POINTER_Move(); + } + +/// @endcond + +/* Public functions ----------------------------------------------------------*/ + +/******************************************************************************* +* +* POINTER_SetCurrentPointer +* +*******************************************************************************/ +/** +* +* Set the dimension and the bitmap of the pointer. +* @note The bitmap is a monochrome one! +* +* @param[in] width width of the pointer (u8) +* @param[in] height height of the pointer (u8) +* @param[in] bmp pointer to an array of width * height bits. +* +**/ +/********************************************************************************/ +void POINTER_SetCurrentPointer( u8 width, u8 height, u8* bmp ) + { + if( !bmp ) + { + bmp = BallPointerBmp; + } + + CurrentPointerWidth = width; + CurrentPointerHeight = height; + CurrentPointerBmp = bmp; + } + +/******************************************************************************* +* +* POINTER_GetCurrentAngleStart +* +*******************************************************************************/ +/** +* +* Get the current minimal angle to move pointer +* +* @return current minimal angle. +* +**/ +/******************************************************************************/ +u16 POINTER_GetCurrentAngleStart( void ) + { + return CurrentAngleStart; + } + +/******************************************************************************* +* +* POINTER_SetCurrentAngleStart +* +*******************************************************************************/ +/** +* +* Set the current minimal angle to move pointer +* +* @param[in] newangle The new minimal angle to move pointer. +* +**/ +/******************************************************************************/ +void POINTER_SetCurrentAngleStart( u16 newangle ) + { + CurrentAngleStart = newangle; + } + +/******************************************************************************* +* +* POINTER_GetCurrentSpeedOnAngle +* +*******************************************************************************/ +/** +* +* Return the current speed/angle ratio. +* +* @return current ratio. +* +**/ +/******************************************************************************/ +u16 POINTER_GetCurrentSpeedOnAngle( void ) + { + return CurrentSpeedOnAngle; + } + +/******************************************************************************* +* +* POINTER_SetCurrentSpeedOnAngle +* +*******************************************************************************/ +/** +* +* Set the current speed/angle ratio. +* +* @param[in] newspeed New speed/angle ratio. +* +**/ +/******************************************************************************/ +void POINTER_SetCurrentSpeedOnAngle( u16 newspeed ) + { + CurrentSpeedOnAngle = newspeed; + } + +/******************************************************************************* +* +* POINTER_SetCurrentAreaStore +* +*******************************************************************************/ +/** +* +* Change the current storage area. If the provided value is NULL, the default +* storage area will be used. +* +* @param[in] ptr New storage area (may be null). +* +* @warning Memory space pointed by the provided pointer must be large enough +* to store a color bitmap corresponding to the pointer area. +* In other words, space must be width * height * 2 large. +* +**/ +/******************************************************************************/ +void POINTER_SetCurrentAreaStore( u8* ptr ) + { + ptrAreaStore = ( ptr == 0 ) ? DefaultAreaStore : ptr; + } + +/******************************************************************************* +* +* POINTER_SetMode +* +*******************************************************************************/ +/** +* +* Change the current mode of the pointer management. +* +* @note Must be called only ONCE!! +* +* @param[in] mode New pointer management mode. +* +**/ +/******************************************************************************/ +void POINTER_SetMode( enum POINTER_mode mode ) + { + u16* ptr; + u16 i; + u16 color; + + switch( mode ) + { + case POINTER_APPLICATION: + ptr = (u16*)DefaultAreaStore; + color = DRAW_GetBGndColor(); + + for ( i = 0; i < (CurrentPointerWidth*CurrentPointerHeight) ; i++ ) + { + *ptr++ = color; + } + + POINTER_Draw( POINTER_Info.xPos, POINTER_Info.yPos, CurrentPointerWidth, CurrentPointerHeight, CurrentPointerBmp ); + break; + + case POINTER_RESTORE_LESS: + POINTER_Draw( POINTER_Info.xPos, POINTER_Info.yPos, CurrentPointerWidth, CurrentPointerHeight, CurrentPointerBmp ); + break; + + case POINTER_ON: + POINTER_SetCurrentAreaStore( 0 ); + POINTER_Save( POINTER_Info.xPos, POINTER_Info.yPos, POINTER_WIDTH, POINTER_WIDTH ); + POINTER_Draw( POINTER_Info.xPos, POINTER_Info.yPos, CurrentPointerWidth, CurrentPointerHeight,CurrentPointerBmp ); + break; + + case POINTER_OFF: + POINTER_Info.xPos = ( SCREEN_WIDTH - POINTER_WIDTH ) / 2; + POINTER_Info.yPos = ( SCREEN_WIDTH - POINTER_WIDTH ) / 2; + + case POINTER_MENU: + if( Pointer_Mode == POINTER_ON ) + { + POINTER_SetCurrentAreaStore( 0 ); + POINTER_Restore( POINTER_Info.xPos, POINTER_Info.yPos, POINTER_WIDTH, POINTER_WIDTH ); + } + break; + } + + Pointer_Mode = mode; + } + +/******************************************************************************* +* +* POINTER_GetMode +* +*******************************************************************************/ +/** +* +* Return the current mode of the pointer management +* +* @return Current pointer management mode. +* +**/ +/******************************************************************************/ +enum POINTER_mode POINTER_GetMode( void ) + { + return Pointer_Mode; + } + +/******************************************************************************* +* +* POINTER_GetState +* +*******************************************************************************/ +/** +* +* Return current pointer state. +* +* @return Current pointer state. +* +**/ +/******************************************************************************/ +enum POINTER_state POINTER_GetState( void ) + { + return Pointer_State; + } + +/******************************************************************************* +* +* POINTER_SetRect +* +*******************************************************************************/ +/** +* +* Set new limits for the move of the pointer +* +* @param[in] x Horizontal coordinate of the bottom left corner of the new area. +* @param[in] y Vertical coordinate of the bottom left corner of the new are. +* @param[in] width New area width. +* @param[in] height New area height. +* +* @warning The (0x0) point in on the low left corner. +* +**/ +/******************************************************************************/ +void POINTER_SetRect( s16 x, s16 y, s16 width, s16 height ) + { + POINTER_Info.X_PosMin = x; + + if( POINTER_Info.xPos < POINTER_Info.X_PosMin ) + { + POINTER_Info.xPos = POINTER_Info.X_PosMin; + } + + POINTER_Info.X_PosMax = x + width - 1; + + if( POINTER_Info.xPos > POINTER_Info.X_PosMax ) + { + POINTER_Info.xPos = POINTER_Info.X_PosMax; + } + + POINTER_Info.Y_PosMin = y; + + if( POINTER_Info.yPos < POINTER_Info.Y_PosMin ) + { + POINTER_Info.yPos = POINTER_Info.Y_PosMin; + } + + POINTER_Info.Y_PosMax = y + height - 1; + + if( POINTER_Info.yPos > POINTER_Info.Y_PosMax ) + { + POINTER_Info.yPos = POINTER_Info.Y_PosMax; + } + } + +/******************************************************************************* +* +* POINTER_SetRectScreen +* +*******************************************************************************/ +/** +* +* Allow the pointer to move on the whole screen. +* +**/ +/******************************************************************************/ +void POINTER_SetRectScreen( void ) + { + POINTER_SetRect( 0, 0, POS_MAX, POS_MAX ); + } + +/******************************************************************************* +* +* POINTER_GetPos +* +*******************************************************************************/ +/** +* +* Return the current position of the pointer (on the screen). +* +* @return The current pointer screen position with X in the LSB and Y in the MSB. +* +* @warning The (0x0) point in on the low left corner. +**/ +/******************************************************************************/ +u16 POINTER_GetPos( void ) + { + return ( POINTER_Info.xPos | ( POINTER_Info.yPos << 8 ) ); + } + +/******************************************************************************* +* +* POINTER_SetPos +* +*******************************************************************************/ +/** +* +* Force the screen position of the pointer. +* +* @param[in] x New horizontal coordinate. +* @param[in] y New vertical coordinate. +* +* @warning The (0x0) point in on the low left corner. +* +**/ +/******************************************************************************/ +void POINTER_SetPos( u16 x, u16 y ) + { + POINTER_Info.xPos = x; + POINTER_Info.yPos = y; + } + +/******************************************************************************* +* +* POINTER_Draw +* +*******************************************************************************/ +/** +* +* Draw pointer. +* +* @param[in] x Horizontal coordinate of the bottom left corner of the pointer. +* @param[in] y Vertical coordinate of the bottom left corner of the pointer. +* @param[in] width Pointer bitmap width. +* @param[in] height Pointer bitmap height. +* @param[in] bmp Pointer to width * height bit array. If null used default +* pointer bitmap. +* +* @note The provided bitmap is a monochrome one. +* @warning The (0x0) point in on the low left corner. +* +**/ +/******************************************************************************/ +void POINTER_Draw( u8 x, u8 y, u8 width, u8 height, u8* bmp ) + { + int i = 0; + int l = 0; + int n = 0; + char* ptr = ptrAreaStore; + char c; + u16 val; + + // No bitmap provided, use the default one! + if( bmp == 0 ) + { + bmp = BallPointerBmp; + } + + // Select the screen area were going to take care about! + LCD_SetRect_For_Cmd( x, y, width, height ); + + // Let draw to the LCD screen. + LCD_SendLCDCmd( ST7637_RAMWR ); + + while( n < ( width * height ) ) + { + if( Pointer_Mode != POINTER_RESTORE_LESS ) + { + // Draw pixel using current storage area data for background pixels. + c = *ptr++; + LCD_SendLCDData( ( bmp[ l + ( i / 8 ) ] & ( 1 << ( 7 - ( i % 8 ) ) ) ) ? ( POINTER_GetColor() & 255 ) : c ); + + c = *ptr++; + LCD_SendLCDData( ( bmp[ l + ( i / 8 ) ] & ( 1 << ( 7 - ( i % 8 ) ) ) ) ? ( POINTER_GetColor() >> 8 ) : c ); + } + else + { + // POINTER_RESTORE_LESS: use current background color for background color. + c = DRAW_GetBGndColor(); + val = ( bmp[ l + ( i / 8 ) ] & ( 1 << ( 7 - ( i % 8 ) ) ) ) ? POINTER_GetColor() : c; + + LCD_SendLCDData( val & 255 ); + LCD_SendLCDData( val >> 8 ); + } + + n++; + + i++; + + // End of line ? + if( i == width ) + { + // Next line! + l++; + i=0; + } + } + } + +/******************************************************************************* +* +* POINTER_Save +* +*******************************************************************************/ +/** +* +* Save the background of the pointer. +* +* @param[in] x Horizontal coordinate of the bottom left corner of the area to save. +* @param[in] y Vertical coordinate of the bottom left corner of the area to save. +* @param[in] width Width of the area to save. +* @param[in] height Height of the area to save. +* +* @note The store area must be large enough to store all the pixels (16 bits). +* @warning The (0x0) point in on the low left corner. +* @see POINTER_Restore +* @see POINTER_SetCurrentAreaStore +* +**/ +/******************************************************************************/ +void POINTER_Save( u8 x, u8 y, u8 width, u8 height ) + { + int i; + char* ptr = ptrAreaStore; + int bytesize = ( width * height ) * 2; // 2 bytes per pixel. + + // Is this pointer management mode, don't save pointer background! + if( Pointer_Mode == POINTER_RESTORE_LESS ) + { + return; + } + + // Select the LCD screen area to read. + LCD_SetRect_For_Cmd ( x, y, width, height ); + + // Send the memory read command to the LCD controller. + LCD_SendLCDCmd( ST7637_RAMRD ); + + // First returned byte is a dummy! + LCD_ReadLCDData(); + + for( i = 0; i < bytesize; i++ ) + { + *ptr++ = LCD_ReadLCDData(); + } + } + +/******************************************************************************* +* +* POINTER_Restore +* +*******************************************************************************/ +/** +* +* Restore the background of the pointer with data saved in the current store area. +* +* @param[in] x Horizontal coordinate of the bottom left corner of the area to restore. +* @param[in] y Vertical coordinate of the bottom left corner of the area to restore. +* @param[in] width Width of the area to restore. +* @param[in] height Height of the area to restore. +* +* @warning The (0x0) point in on the low left corner. +* @see POINTER_Save +* @see POINTER_SetCurrentAreaStore +* +**/ +/******************************************************************************/ +void POINTER_Restore( u8 x, u8 y, u8 width, u8 height ) + { + int i; + char* ptr = ptrAreaStore; + int bytesize = ( width * height ) * 2; // 2 bytes per pixel. + + // Select the screen area to write. + LCD_SetRect_For_Cmd( x, y, width, height ); + + // Send the memory write command to the LCD controller. + LCD_SendLCDCmd( ST7637_RAMWR ); + + for( i = 0; i < bytesize; i++ ) + { + // In this mode, use background color (no data was previously saved). + if ( Pointer_Mode == POINTER_RESTORE_LESS ) + { + LCD_SendLCDData( DRAW_GetBGndColor() ); + } + else + { + LCD_SendLCDData( *ptr++ ); + } + } + } + +/******************************************************************************* +* +* POINTER_SetApplication_Pointer_Mgr +* +*******************************************************************************/ +/** +* +* Provides an user defined pointer manager. +* +* @param[in] mgr Pointer to the user defined pointer manager. +* +**/ +/******************************************************************************/ +void POINTER_SetApplication_Pointer_Mgr( tAppPtrMgr mgr ) + { + Application_Pointer_Mgr = mgr; + } + +/******************************************************************************* +* +* POINTER_SetColor +* +*******************************************************************************/ +/** +* +* Set the pointer color. +* +* @param[in] color The new pointer color. +* +**/ +/******************************************************************************/ +void POINTER_SetColor( u16 color ) + { + CurrentPointerColor = color; + } + +/******************************************************************************* +* +* POINTER_GetColor +* +*******************************************************************************/ +/** +* +* Return the current pointer color. +* +* @return Current pointer color. +* +**/ +/******************************************************************************/ +u16 POINTER_GetColor( void ) + { + return CurrentPointerColor; + } + +/******************************************************************************* +* +* POINTER_GetInfo +* +*******************************************************************************/ +/** +* +* Get pointer informations. +* +* @return A pointer to a pointer information structure. +* +**/ +/******************************************************************************/ +tPointer_Info* POINTER_GetInfo( void ) + { + return &POINTER_Info; + } diff --git a/20080212/Demo/CORTEX_STM32F103_Primer_GCC/ST_Code/scheduler.h b/20080212/Demo/CORTEX_STM32F103_Primer_GCC/ST_Code/scheduler.h new file mode 100644 index 000000000..11c7e67fa --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_Primer_GCC/ST_Code/scheduler.h @@ -0,0 +1,81 @@ +/********************* (C) COPYRIGHT 2007 RAISONANCE S.A.S. *******************/ +/** +* +* @file scheduler.h +* @brief Header file for the SysTick interrupt handler of the CircleOS project. +* @author FL +* @author IB +* @date 07/2007 +* +**/ +/******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_IT_H +#define __STM32F10x_IT_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_lib.h" + +void NMIException( void ); +void HardFaultException( void ); +void MemManageException( void ); +void BusFaultException( void ); +void UsageFaultException( void ); +void DebugMonitor( void ); +void SVCHandler( void ); +void PendSVC( void ); +void SysTickHandler( void ); +void WWDG_IRQHandler( void ); +void PVD_IRQHandler( void ); +void TAMPER_IRQHandler( void ); +void RTC_IRQHandler( void ); +void FLASH_IRQHandler( void ); +void RCC_IRQHandler( void ); +void EXTI0_IRQHandler( void ); +void EXTI1_IRQHandler( void ); +void EXTI2_IRQHandler( void ); +void EXTI3_IRQHandler( void ); +void EXTI4_IRQHandler( void ); +void DMAChannel1_IRQHandler( void ); +void DMAChannel2_IRQHandler( void ); +void DMAChannel3_IRQHandler( void ); +void DMAChannel4_IRQHandler( void ); +void DMAChannel5_IRQHandler( void ); +void DMAChannel6_IRQHandler( void ); +void DMAChannel7_IRQHandler( void ); +void ADC_IRQHandler( void ); +void USB_HP_CAN_TX_IRQHandler( void ); +void USB_LP_CAN_RX0_IRQHandler( void ); +void CAN_RX1_IRQHandler( void ); +void CAN_SCE_IRQHandler( void ); +void EXTI9_5_IRQHandler( void ); +void TIM1_BRK_IRQHandler( void ); +void TIM1_UP_IRQHandler( void ); +void TIM1_TRG_CCUP_IRQHandler( void ); +void TIM1_CC_IRQHandler( void ); +void TIM2_IRQHandler( void ); +void TIM3_IRQHandler( void ); +void TIM4_IRQHandler( void ); +void I2C1_EV_IRQHandler( void ); +void I2C1_ER_IRQHandler( void ); +void I2C2_EV_IRQHandler( void ); +void I2C2_ER_IRQHandler( void ); +void SPI1_IRQHandler( void ); +void SPI2_IRQHandler( void ); +void USART1_IRQHandler( void ); +void USART2_IRQHandler( void ); +void USART3_IRQHandler( void ); +void EXTI15_10_IRQHandler( void ); +void RTCAlarm_IRQHandler( void ); +void USBWakeUp_IRQHandler( void ); + +//FL071107 Make the scheduler configurable. The handler are inserted into a list that could +//be modified by the applications. +typedef void (*tHandler) ( void ); +extern tHandler SchHandler [16+1]; +#define SCH_HDL_MAX ( sizeof SchHandler / sizeof (tHandler) ) + + + +#endif /* __STM32F10x_IT_H */ diff --git a/20080212/Demo/CORTEX_STM32F103_Primer_GCC/ST_Code/stm32f10x_circle_it.c b/20080212/Demo/CORTEX_STM32F103_Primer_GCC/ST_Code/stm32f10x_circle_it.c new file mode 100644 index 000000000..a656d685f --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_Primer_GCC/ST_Code/stm32f10x_circle_it.c @@ -0,0 +1,217 @@ +/********************* (C) COPYRIGHT 2007 RAISONANCE S.A.S. *******************/ +/** +* +* @file stm32f10x_circle_it.c +* @brief Interrupt handler for the CircleOS project. +* @author FL +* @author IB +* @date 07/2007 +* +**/ +/******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "circle.h" + +/* External variables --------------------------------------------------------*/ +extern u16 CCR_Val; +extern u16 Current_CCR_BackLightStart; + +/******************************************************************************* +* +* NMIException +* +*******************************************************************************/ +/** +* +* Handles the NMI exception. +* +**/ +/******************************************************************************/ +void NMIException( void ) {} + +/******************************************************************************* +* +* HardFaultException +* +*******************************************************************************/ +/** +* +* Handles the Hard Fault exception. +* +**/ +/******************************************************************************/ +void HardFaultException( void ) + { + #ifdef TIMING_ANALYSIS //to debug with a scope + GPIO_WriteBit( GPIOA, GPIO_Pin_5, Bit_RESET ); + GPIO_WriteBit( GPIOA, GPIO_Pin_5, Bit_SET ); + #endif + } + +/******************************************************************************* +* +* MemManageException +* +*******************************************************************************/ +/** +* +* Handles the Memory Manage exception. +* +**/ +/******************************************************************************/ +void MemManageException( void ) {} + +/******************************************************************************* +* +* BusFaultException +* +*******************************************************************************/ +/** +* +* Handles the Bus Fault exception. +* +**/ +/******************************************************************************/ +void BusFaultException( void ) {} + +/******************************************************************************* +* +* UsageFaultException +* +*******************************************************************************/ +/** +* +* Handles the Usage Fault exception. +* +**/ +/******************************************************************************/ +void UsageFaultException( void ) {} + +/******************************************************************************* +* +* DebugMonitor +* +*******************************************************************************/ +/** +* +* Handles the Debug Monitor exception. +* +**/ +/******************************************************************************/ +void DebugMonitor( void ) {} + +/******************************************************************************* +* +* SVCHandler +* +*******************************************************************************/ +/** +* +* Handles the SVCall exception. +* +**/ +/******************************************************************************/ +void SVCHandler( void ) {} + +/******************************************************************************* +* +* PendSVC +* +*******************************************************************************/ +/** +* +* Handles the PendSVC exception. +* +**/ +/******************************************************************************/ +void PendSVC( void ) {} + +/******************************************************************************* +* +* DummyHandler +* +*******************************************************************************/ +/** +* +* Default handling for the IRQ-Exception +* +**/ +/******************************************************************************/ +void DummyHandler ( void ) {} + +/******************************************************************************* +* +* TIM2_IRQHandler +* +*******************************************************************************/ +/** +* +* Handles the TIM2 global interrupt request. +* +**/ +/******************************************************************************/ +void TIM2_IRQHandler( void ) + { + #ifdef TIMING_ANALYSIS //to debug with a scope + GPIO_WriteBit( GPIOA, GPIO_Pin_7, Bit_RESET ); + #endif + + /* Clear TIM2 update interrupt */ + TIM_ClearITPendingBit( TIM2, TIM_IT_Update ); + + MEMS_Handler(); + + #ifdef TIMING_ANALYSIS //to debug with a scope + GPIO_WriteBit( GPIOA, GPIO_Pin_7, Bit_SET ); + #endif + } + +/******************************************************************************* +* +* TIM3_IRQHandler +* +*******************************************************************************/ +/** +* +* Handles the TIM3 global interrupt request. +* +**/ +/******************************************************************************/ +void TIM3_IRQHandler( void ) +{ + u16 capture = 0; + + if( TIM_GetITStatus( TIM3, TIM_IT_CC3 ) != RESET ) + { + capture = TIM_GetCapture3( TIM3 ); + + TIM_SetCompare3( TIM3, capture + CCR_Val + 1 ); + TIM_ClearITPendingBit( TIM3, TIM_IT_CC3 ); + } +} + +/******************************************************************************* +* +* TIM4_IRQHandler +* +*******************************************************************************/ +/** +* +* Handles the TIM4 global interrupt request. +* +**/ +/******************************************************************************/ +void TIM4_IRQHandler( void ) +{ + u16 BackLight_capture = 0; + + if( TIM_GetITStatus( TIM4, TIM_IT_CC2 ) != RESET ) + { + BackLight_capture = TIM_GetCapture2( TIM4 ); + + TIM_SetCompare2( TIM4, BackLight_capture + Current_CCR_BackLightStart + 1 ); + TIM_ClearITPendingBit( TIM4, TIM_IT_CC2 ); + } +} + diff --git a/20080212/Demo/CORTEX_STM32F103_Primer_GCC/ST_Code/stm32f10x_conf.h b/20080212/Demo/CORTEX_STM32F103_Primer_GCC/ST_Code/stm32f10x_conf.h new file mode 100644 index 000000000..27234fc73 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_Primer_GCC/ST_Code/stm32f10x_conf.h @@ -0,0 +1,119 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_conf.h +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : Library configuration file. +******************************************************************************** +* History: +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_CONF_H +#define __STM32F10x_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Comment the line below to compile the library in release mode */ +//#define DEBUG 0 + +/* Comment the line below to disable the specific peripheral inclusion */ +/************************************* ADC ************************************/ +//#define _ADC +#define _ADC1 +#define _ADC2 + +/************************************* CAN ************************************/ +//#define _CAN + +/************************************* DMA ************************************/ +//#define _DMA +#define _DMA_Channel1 +#define _DMA_Channel2 +#define _DMA_Channel3 +#define _DMA_Channel4 +#define _DMA_Channel5 +#define _DMA_Channel6 +#define _DMA_Channel7 + +/************************************* EXTI ***********************************/ +//#define _EXTI + +/************************************* GPIO ***********************************/ +#define _GPIO +#define _GPIOA +#define _GPIOB +#define _GPIOC +#define _GPIOD +//#define _GPIOE +#define _AFIO + +/************************************* I2C ************************************/ +//#define _I2C +//#define _I2C1 +//#define _I2C2 + +/************************************* IWDG ***********************************/ +//#define _IWDG + +/************************************* NVIC ***********************************/ +#define _NVIC +#define _SCB + +/************************************* BKP ************************************/ +//#define _BKP + +/************************************* PWR ************************************/ +//#define _PWR + +/************************************* RCC ************************************/ +#define _RCC + +/************************************* RTC ************************************/ +//#define _RTC + +/************************************* SPI ************************************/ +#define _SPI +//#define _SPI1 +#define _SPI2 + +/************************************* SysTick ********************************/ +#define _SysTick + +/************************************* TIM1 ***********************************/ +//#define _TIM1 + +/************************************* TIM ************************************/ +#define _TIM +#define _TIM2 +#define _TIM3 +#define _TIM4 + +/************************************* USART **********************************/ +//#define _USART +//#define _USART1 +//#define _USART2 +//#define _USART3 + +/************************************* WWDG ***********************************/ +//#define _WWDG + +/* In the following line adjust the value of External High Speed oscillator (HSE) + used in your application */ +#define HSE_Value ((u32)12000000) /* Value of the External oscillator in Hz*/ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +#endif /* __STM32F10x_CONF_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/CORTEX_STM32F103_Primer_GCC/ST_Code/stm32f10x_it.h b/20080212/Demo/CORTEX_STM32F103_Primer_GCC/ST_Code/stm32f10x_it.h new file mode 100644 index 000000000..9fa5322b4 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_Primer_GCC/ST_Code/stm32f10x_it.h @@ -0,0 +1,70 @@ +/********************* (C) COPYRIGHT 2007 RAISONANCE S.A.S. ******************** +* File Name : stm32f10x_it.c +* Author : IB/FL +* Date First Issued : 07/2007 +* Description : Interrupt handler for the CircleOS project. +* Revision : +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_IT_H +#define __STM32F10x_IT_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_lib.h" + +/* Exported functions ------------------------------------------------------- */ +void NMIException( void ); +void HardFaultException( void ); +void MemManageException( void ); +void BusFaultException( void ); +void UsageFaultException( void ); +void DebugMonitor( void ); +void SVCHandler( void ); +void PendSVC( void ); +void SysTickHandler( void ); +void WWDG_IRQHandler( void ); +void PVD_IRQHandler( void ); +void TAMPER_IRQHandler( void ); +void RTC_IRQHandler( void ); +void FLASH_IRQHandler( void ); +void RCC_IRQHandler( void ); +void EXTI0_IRQHandler( void ); +void EXTI1_IRQHandler( void ); +void EXTI2_IRQHandler( void ); +void EXTI3_IRQHandler( void ); +void EXTI4_IRQHandler( void ); +void DMAChannel1_IRQHandler( void ); +void DMAChannel2_IRQHandler( void ); +void DMAChannel3_IRQHandler( void ); +void DMAChannel4_IRQHandler( void ); +void DMAChannel5_IRQHandler( void ); +void DMAChannel6_IRQHandler( void ); +void DMAChannel7_IRQHandler( void ); +void ADC_IRQHandler( void ); +void USB_HP_CAN_TX_IRQHandler( void ); +void USB_LP_CAN_RX0_IRQHandler( void ); +void CAN_RX1_IRQHandler( void ); +void CAN_SCE_IRQHandler( void ); +void EXTI9_5_IRQHandler( void ); +void TIM1_BRK_IRQHandler( void ); +void TIM1_UP_IRQHandler( void ); +void TIM1_TRG_COM_IRQHandler( void ); +void TIM1_CC_IRQHandler( void ); +void TIM2_IRQHandler( void ); +void TIM3_IRQHandler( void ); +void TIM4_IRQHandler( void ); +void I2C1_EV_IRQHandler( void ); +void I2C1_ER_IRQHandler( void ); +void I2C2_EV_IRQHandler( void ); +void I2C2_ER_IRQHandler( void ); +void SPI1_IRQHandler( void ); +void SPI2_IRQHandler( void ); +void USART1_IRQHandler( void ); +void USART2_IRQHandler( void ); +void USART3_IRQHandler( void ); +void EXTI15_10_IRQHandler( void ); +void RTCAlarm_IRQHandler( void ); +void USBWakeUp_IRQHandler( void ); + +#endif /* __STM32F10x_IT_H */ diff --git a/20080212/Demo/CORTEX_STM32F103_Primer_GCC/ST_Code/stm32f10x_tim.c b/20080212/Demo/CORTEX_STM32F103_Primer_GCC/ST_Code/stm32f10x_tim.c new file mode 100644 index 000000000..5fd374eb9 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_Primer_GCC/ST_Code/stm32f10x_tim.c @@ -0,0 +1,2348 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_tim.c +* Author : MCD Application Team +* Date First Issued : 09/29/2006 +* Description : This file provides all the TIM firmware functions. +******************************************************************************** +* History: +* 04/02/2007: V0.2 +* 02/05/2007: V0.1 +* 09/29/2006: V0.01 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_tim.h" +#include "stm32f10x_rcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* ---------------------- TIM registers bit mask ------------------------ */ +#define CR1_CEN_Set ((u16)0x0001) +#define CR1_CEN_Reset ((u16)0x03FE) +#define CR1_UDIS_Set ((u16)0x0002) +#define CR1_UDIS_Reset ((u16)0x03FD) +#define CR1_URS_Set ((u16)0x0004) +#define CR1_URS_Reset ((u16)0x03FB) +#define CR1_OPM_Mask ((u16)0x03F7) +#define CR1_CounterMode_Mask ((u16)0x039F) +#define CR1_ARPE_Set ((u16)0x0080) +#define CR1_ARPE_Reset ((u16)0x037F) +#define CR1_CKD_Mask ((u16)0x00FF) + +#define CR2_CCDS_Set ((u16)0x0008) +#define CR2_CCDS_Reset ((u16)0x0007) +#define CR2_MMS_Mask ((u16)0x0080) +#define CR2_TI1S_Set ((u16)0x0080) +#define CR2_TI1S_Reset ((u16)0xFF70) + +#define SMCR_SMS_Mask ((u16)0xFFF0) +#define SMCR_ETR_Mask ((u16)0x00F7) +#define SMCR_TS_Mask ((u16)0xFF87) +#define SMCR_MSM_Mask ((u16)0xFF77) +#define SMCR_ECE_Set ((u16)0x4000) + +#define CCMR_CC13S_Mask ((u16)0x7F7C) +#define CCMR_CC24S_Mask ((u16)0x7C7F) +#define CCMR_TI13Direct_Set ((u16)0x0001) +#define CCMR_TI24Direct_Set ((u16)0x0100) +#define CCMR_OC13FE_Mask ((u16)0x7F7B) +#define CCMR_OC24FE_Mask ((u16)0x7B7F) +#define CCMR_OC13PE_Mask ((u16)0x7F77) +#define CCMR_OC24PE_Mask ((u16)0x777F) +#define CCMR_OCM13_Mask ((u16)0x7F0F) +#define CCMR_OCM24_Mask ((u16)0x0F7F) +#define CCMR_IC13PSC_Mask ((u16)0xFFF3) +#define CCMR_IC24PSC_Mask ((u16)0xF3FF) +#define CCMR_IC13F_Mask ((u16)0xFF0F) +#define CCMR_IC24F_Mask ((u16)0x0FFF) +#define CCER_CC1P_Mask ((u16)0xFFFD) + +#define CCER_CC2P_Mask ((u16)0xFFDF) +#define CCER_CC3P_Mask ((u16)0xFDFF) +#define CCER_CC4P_Mask ((u16)0xDFFF) + +#define CCRE_CC1E_Set ((u16)0x0001) +#define CCRE_CC1E_Reset ((u16)0xFFFE) +#define CCRE_CC1E_Mask ((u16)0xFFFE) + +#define CCRE_CC2E_Set ((u16)0x0010) +#define CCRE_CC2E_Reset ((u16)0xFFEF) +#define CCRE_CC2E_Mask ((u16)0xFFEF) + +#define CCRE_CC3E_Set ((u16)0x0100) +#define CCRE_CC3E_Reset ((u16)0xFEFF) + +#define CCRE_CC4E_Set ((u16)0x1000) +#define CCRE_CC4E_Reset ((u16)0xEFFF) +#define CCRE_CC4E_Mask ((u16)0xEFFF) + +#define DCR_DMA_Mask ((u16)0x0000) + +/* TIM private Masks */ +#define TIM_Period_Reset_Mask ((u16)0x0000) +#define TIM_Prescaler_Reset_Mask ((u16)0x0000) +#define TIM_Pulse_Reset_Mask ((u16)0x0000) +#define TIM_ICFilter_Mask ((u8)0x00) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +static uc16 Tab_OCModeMask[4] = {0xFF00, 0x00FF, 0xFF00, 0x00FF}; +static uc16 Tab_PolarityMask[4] = {CCER_CC1P_Mask, CCER_CC2P_Mask, CCER_CC3P_Mask, CCER_CC4P_Mask}; + +/* Private function prototypes -----------------------------------------------*/ +static void PWMI_Config(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); +static void TI1_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection, + u8 TIM_ICFilter); +static void TI2_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection, + u8 TIM_ICFilter); +static void TI3_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection, + u8 TIM_ICFilter); +static void TI4_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection, + u8 TIM_ICFilter); +static void ETR_Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, + u16 TIM_ExtTRGPolarity, u8 ExtTRGFilter); +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : TIM_DeInit +* Description : Deinitializes the TIMx peripheral registers to their default +* reset values. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_DeInit(TIM_TypeDef* TIMx) +{ + switch (*(u32*)&TIMx) + { + case TIM2_BASE: + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); + break; + + case TIM3_BASE: + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); + break; + + case TIM4_BASE: + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : TIM_TimeBaseInit +* Description : Initializes the TIMx Time Base Unit peripheral according to +* the specified parameters in the TIM_TimeBaseInitStruct. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef +* structure that contains the configuration information for +* the specified TIM peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) +{ + /* Check the parameters */ + assert(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode)); + assert(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision)); + + /* Set the Autoreload value */ + TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ; + + /* Set the Prescaler value */ + TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; + + /* Select the Counter Mode and set the clock division */ + TIMx->CR1 &= CR1_CKD_Mask & CR1_CounterMode_Mask; + TIMx->CR1 |= (u32)TIM_TimeBaseInitStruct->TIM_ClockDivision | + TIM_TimeBaseInitStruct->TIM_CounterMode; +} +/******************************************************************************* +* Function Name : TIM_OCInit +* Description : Initializes the TIMx peripheral according to the specified +* parameters in the TIM_OCInitStruct. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure +* that contains the configuration information for the specified +* TIM peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OCInit(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + u32 tmpccmrx = 0, tmpccer = 0; + + /* Check the parameters */ + assert(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert(IS_TIM_CHANNEL(TIM_OCInitStruct->TIM_Channel)); + assert(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + + if ((TIM_OCInitStruct->TIM_Channel == (u16)TIM_Channel_1) || + (TIM_OCInitStruct->TIM_Channel == (u16)TIM_Channel_2)) + { + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare Bits */ + tmpccmrx &= Tab_OCModeMask[TIM_OCInitStruct->TIM_Channel]; + + /* Set the Output Polarity level */ + tmpccer &= Tab_PolarityMask[TIM_OCInitStruct->TIM_Channel]; + + if (TIM_OCInitStruct->TIM_Channel == TIM_Channel_1) + { + /* Disable the Channel 1: Reset the CCE Bit */ + TIMx->CCER &= CCRE_CC1E_Reset; + + /* Select the Output Compare Mode */ + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; + + /* Set the Capture Compare Enable Bit */ + tmpccer |= CCRE_CC1E_Set; + + /* Set the Capture Compare Polarity */ + tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; + } + else /* TIM_Channel_2 */ + { + /* Disable the Channel 2: Reset the CCE Bit */ + TIMx->CCER &= CCRE_CC2E_Reset; + + /* Select the Output Compare Mode */ + tmpccmrx |= (u32)TIM_OCInitStruct->TIM_OCMode << 8; + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse; + + /* Set the Capture Compare Enable Bit */ + tmpccer |= CCRE_CC2E_Set; + + /* Set the Capture Compare Polarity */ + tmpccer |= (u32)TIM_OCInitStruct->TIM_OCPolarity << 4; + } + + TIMx->CCMR1 = (u16)tmpccmrx; + } + else + { + if ((TIM_OCInitStruct->TIM_Channel == TIM_Channel_3) || + (TIM_OCInitStruct->TIM_Channel == TIM_Channel_4)) + { + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare Bits */ + tmpccmrx &= Tab_OCModeMask[TIM_OCInitStruct->TIM_Channel]; + + /* Set the Output Polarity level */ + tmpccer &= Tab_PolarityMask[TIM_OCInitStruct->TIM_Channel]; + + if (TIM_OCInitStruct->TIM_Channel == TIM_Channel_3) + { + /* Disable the Channel 3: Reset the CCE Bit */ + TIMx->CCER &= CCRE_CC3E_Reset; + + /* Select the Output Compare Mode */ + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse; + + /* Set the Capture Compare Enable Bit */ + tmpccer |= CCRE_CC3E_Set; + + /* Set the Capture Compare Polarity */ + tmpccer |= (u32)TIM_OCInitStruct->TIM_OCPolarity << 8; + } + else /* TIM_Channel_4 */ + { + /* Disable the Channel 4: Reset the CCE Bit */ + TIMx->CCER &= CCRE_CC4E_Reset; + + /* Select the Output Compare Mode */ + tmpccmrx |= (u32)TIM_OCInitStruct->TIM_OCMode << 8; + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse; + + /* Set the Capture Compare Enable Bit */ + tmpccer |= CCRE_CC4E_Set; + + /* Set the Capture Compare Polarity */ + tmpccer |= (u32)TIM_OCInitStruct->TIM_OCPolarity << 12; + } + + TIMx->CCMR2 = (u16)tmpccmrx; + } + } + + TIMx->CCER = (u16)tmpccer; +} + +/******************************************************************************* +* Function Name : TIM_ICInit +* Description : Initializes the TIMx peripheral according to the specified +* parameters in the TIM_ICInitStruct. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure +* that contains the configuration information for the specified +* TIM peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + /* Check the parameters */ + assert(IS_TIM_IC_MODE(TIM_ICInitStruct->TIM_ICMode)); + assert(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel)); + assert(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity)); + assert(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection)); + assert(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler)); + assert(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter)); + + if (TIM_ICInitStruct->TIM_ICMode == TIM_ICMode_ICAP) + { + if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + /* TI1 Configuration */ + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) + { + /* TI2 Configuration */ + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) + { + /* TI3 Configuration */ + TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else /* TIM_Channel_4 */ + { + /* TI4 Configuration */ + TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + } + else + { + PWMI_Config(TIMx, TIM_ICInitStruct); + } +} + +/******************************************************************************* +* Function Name : TIM_TimeBaseStructInit +* Description : Fills each TIM_TimeBaseInitStruct member with its default value. +* Input : - TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef +* structure which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) +{ + /* Set the default configuration */ + TIM_TimeBaseInitStruct->TIM_Period = TIM_Period_Reset_Mask; + TIM_TimeBaseInitStruct->TIM_Prescaler = TIM_Prescaler_Reset_Mask; + TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; + TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; +} + +/******************************************************************************* +* Function Name : TIM_OCStructInit +* Description : Fills each TIM_OCInitStruct member with its default value. +* Input : - TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + /* Set the default configuration */ + TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; + TIM_OCInitStruct->TIM_Channel = TIM_Channel_1; + TIM_OCInitStruct->TIM_Pulse = TIM_Pulse_Reset_Mask; + TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; +} + +/******************************************************************************* +* Function Name : TIM_ICStructInit +* Description : Fills each TIM_InitStruct member with its default value. +* Input : - TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + /* Set the default configuration */ + TIM_ICInitStruct->TIM_ICMode = TIM_ICMode_ICAP; + TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; + TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; + TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; + TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; + TIM_ICInitStruct->TIM_ICFilter = TIM_ICFilter_Mask; +} + +/******************************************************************************* +* Function Name : TIM_Cmd +* Description : Enables or disables the specified TIM peripheral. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIMx peripheral. +* - Newstate: new state of the TIMx peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the TIM Counter */ + TIMx->CR1 |= CR1_CEN_Set; + } + else + { + /* Disable the TIM Counter */ + TIMx->CR1 &= CR1_CEN_Reset; + } +} + +/******************************************************************************* +* Function Name : TIM_ITConfig +* Description : Enables or disables the TIMx interrupts. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_IT: specifies the TIM interrupts sources to be enabled +* or disabled. +* This parameter can be any combination of the following values: +* - TIM_IT_Update: Timer update Interrupt +* - TIM_IT_CC1: Capture Compare 1 Interrupt +* - TIM_IT_CC2: Capture Compare 2 Interrupt +* - TIM_IT_CC3: Capture Compare 3 Interrupt +* - TIM_IT_CC4: Capture Compare 4 Interrupt +* - TIM_IT_Trigger: Trigger Interrupt +* - Newstate: new state of the specified TIMx interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ITConfig(TIM_TypeDef* TIMx, u16 TIM_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert(IS_TIM_IT(TIM_IT)); + assert(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Interrupt sources */ + TIMx->DIER |= TIM_IT; + } + else + { + /* Disable the Interrupt sources */ + TIMx->DIER &= (u16)(~TIM_IT); + } +} + +/******************************************************************************* +* Function Name : TIM_DMAConfig +* Description : Configures the TIMx’s DMA interface. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_DMABase: DMA Base address. +* This parameter can be one of the following values: +* - TIM_DMABase_CR1, TIM_DMABase_CR2, TIM_DMABase_SMCR, +* TIM_DMABase_DIER, TIM_DMABase_SR, TIM_DMABase_EGR, +* TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER, +* TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR, +* TIM_DMABase_CCR1, TIM_DMABase_CCR2, TIM_DMABase_CCR3, +* TIM_DMABase_CCR4, TIM_DMABase_DCR. +* - TIM_DMABurstLength: DMA Burst length. +* This parameter can be one value between: +* TIM_DMABurstLength_1Byte and TIM_DMABurstLength_18Bytes. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_DMAConfig(TIM_TypeDef* TIMx, u16 TIM_DMABase, u16 TIM_DMABurstLength) +{ + u32 tmpdcr = 0; + + /* Check the parameters */ + assert(IS_TIM_DMA_BASE(TIM_DMABase)); + assert(IS_TIM_DMA_LENGTH(TIM_DMABurstLength)); + + tmpdcr = TIMx->DCR; + + /* Reset the DBA and the DBL Bits */ + tmpdcr &= DCR_DMA_Mask; + + /* Set the DMA Base and the DMA Burst Length */ + tmpdcr |= TIM_DMABase | TIM_DMABurstLength; + + TIMx->DCR = (u16)tmpdcr; +} + +/******************************************************************************* +* Function Name : TIM_DMACmd +* Description : Enables or disables the TIMx’s DMA Requests. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_DMASources: specifies the DMA Request sources. +* This parameter can be any combination of the following values: +* - TIM_DMA_CC1: Capture Compare 1 DMA source +* - TIM_DMA_CC2: Capture Compare 2 DMA source +* - TIM_DMA_CC3: Capture Compare 3 DMA source +* - TIM_DMA_CC4: Capture Compare 4 DMA source +* - TIM_DMA_Trigger: Trigger DMA source +* - Newstate: new state of the DMA Request sources. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_DMACmd(TIM_TypeDef* TIMx, u16 TIM_DMASource, FunctionalState Newstate) +{ + u32 tmpdier = 0; + + /* Check the parameters */ + assert(IS_TIM_DMA_SOURCE(TIM_DMASource)); + assert(IS_FUNCTIONAL_STATE(Newstate)); + + tmpdier = TIMx->DIER; + + if (Newstate != DISABLE) + { + /* Enable the DMA sources */ + tmpdier |= TIM_DMASource; + } + else + { + /* Disable the DMA sources */ + tmpdier &= (u16)(~TIM_DMASource); + } + TIMx->DIER = (u16)tmpdier; +} + +/******************************************************************************* +* Function Name : TIM_InternalClockConfig +* Description : Configures the TIMx interrnal Clock +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_InternalClockConfig(TIM_TypeDef* TIMx) +{ + /* Disable slave mode to clock the prescaler directly with the internal clock */ + TIMx->SMCR &= SMCR_SMS_Mask; +} +/******************************************************************************* +* Function Name : TIM_ITRxExternalClockConfig +* Description : Configures the TIMx Internal Trigger as External Clock +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_ITRSource: Trigger source. +* This parameter can be one of the following values: +* - TIM_TS_ITR0: Internal Trigger 0 +* - TIM_TS_ITR1: Internal Trigger 1 +* - TIM_TS_ITR2: Internal Trigger 2 +* - TIM_TS_ITR3: Internal Trigger 3 +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, u16 TIM_InputTriggerSource) +{ + /* Check the parameters */ + assert(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource)); + + /* Select the Internal Trigger */ + TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); + + /* Select the External clock mode1 */ + TIMx->SMCR |= TIM_SlaveMode_External1; +} +/******************************************************************************* +* Function Name : TIM_TIxExternalClockConfig +* Description : Configures the TIMx Trigger as External Clock +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_TIxExternalCLKSource: Trigger source. +* This parameter can be one of the following values: +* - TIM_TS_TI1F_ED: TI1 Edge Detector +* - TIM_TS_TI1FP1: Filtered Timer Input 1 +* - TIM_TS_TI2FP2: Filtered Timer Input 2 +* - TIM_ICPolarity: specifies the TIx Polarity. +* This parameter can be: +* - TIM_ICPolarity_Rising +* - TIM_ICPolarity_Falling +* - ICFilter : specifies the filter value. +* This parameter must be a value between 0x0 and 0xF. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, u16 TIM_TIxExternalCLKSource, + u16 TIM_ICPolarity, u8 ICFilter) +{ + /* Check the parameters */ + assert(IS_TIM_TIX_TRIGGER_SELECTION(TIM_TIxExternalCLKSource)); + assert(IS_TIM_IC_POLARITY(TIM_ICPolarity)); + assert(IS_TIM_IC_FILTER(ICFilter)); + + /* Configure the Timer Input Clock Source */ + if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) + { + TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + else + { + TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + + /* Select the Trigger source */ + TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); + + /* Select the External clock mode1 */ + TIMx->SMCR |= TIM_SlaveMode_External1; +} + +/******************************************************************************* +* Function Name : TIM_ETRClockMode1Config +* Description : Configures the External clock Mode1 +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_ExtTRGPrescaler: The external Trigger Prescaler. +* It can be one of the following values: +* - TIM_ExtTRGPSC_OFF +* - TIM_ExtTRGPSC_DIV2 +* - TIM_ExtTRGPSC_DIV4 +* - TIM_ExtTRGPSC_DIV8. +* - TIM_ExtTRGPolarity: The external Trigger Polarity. +* It can be one of the following values: +* - TIM_ExtTRGPolarity_Inverted +* - TIM_ExtTRGPolarity_NonInverted +* - ExtTRGFilter: External Trigger Filter. +* This parameter must be a value between 0x00 and 0x0F +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, u16 TIM_ExtTRGPolarity, + u8 ExtTRGFilter) +{ + /* Check the parameters */ + assert(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + + /* Configure the ETR Clock source */ + ETR_Config(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + + /* Select the External clock mode1 */ + TIMx->SMCR &= SMCR_SMS_Mask; + TIMx->SMCR |= TIM_SlaveMode_External1; + + /* Select the Trigger selection : ETRF */ + TIMx->SMCR &= SMCR_TS_Mask; + TIMx->SMCR |= TIM_TS_ETRF; +} + +/******************************************************************************* +* Function Name : TIM_ETRClockMode2Config +* Description : Configures the External clock Mode2 +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_ExtTRGPrescaler: The external Trigger Prescaler. +* It can be one of the following values: +* - TIM_ExtTRGPSC_OFF +* - TIM_ExtTRGPSC_DIV2 +* - TIM_ExtTRGPSC_DIV4 +* - TIM_ExtTRGPSC_DIV8 +* - TIM_ExtTRGPolarity: The external Trigger Polarity. +* It can be one of the following values: +* - TIM_ExtTRGPolarity_Inverted +* - TIM_ExtTRGPolarity_NonInverted +* - ExtTRGFilter: External Trigger Filter. +* This parameter must be a value between 0x00 and 0x0F +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, + u16 TIM_ExtTRGPolarity, u8 ExtTRGFilter) +{ + /* Check the parameters */ + assert(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + + /* Configure the ETR Clock source */ + ETR_Config(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + + /* Enable the External clock mode2 */ + TIMx->SMCR |= SMCR_ECE_Set; +} +/******************************************************************************* +* Function Name : TIM_SelectInputTrigger +* Description : Selects the Input Trigger source +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_InputTriggerSource: The Input Trigger source. +* This parameter can be one of the following values: +* - TIM_TS_ITR0: Internal Trigger 0 +* - TIM_TS_ITR1: Internal Trigger 1 +* - TIM_TS_ITR2: Internal Trigger 2 +* - TIM_TS_ITR3: Internal Trigger 3 +* - TIM_TS_TI1F_ED: TI1 Edge Detector +* - TIM_TS_TI1FP1: Filtered Timer Input 1 +* - TIM_TS_TI2FP2: Filtered Timer Input 2 +* - TIM_TS_ETRF: External Trigger input +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, u16 TIM_InputTriggerSource) +{ + u32 tmpsmcr = 0; + + /* Check the parameters */ + assert(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource)); + + tmpsmcr = TIMx->SMCR; + + /* Select the Tgigger Source */ + tmpsmcr &= SMCR_TS_Mask; + tmpsmcr |= TIM_InputTriggerSource; + + TIMx->SMCR = (u16)tmpsmcr; +} + +/******************************************************************************* +* Function Name : TIM_PrescalerConfig +* Description : Configures the TIMx Prescaler. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - Prescaler: specifies the Prescaler Register value +* - TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode +* This parameter can be one of the following values: +* - TIM_PSCReloadMode_Update: The Prescaler is loaded at +* the update event. +* - TIM_PSCReloadMode_Immediate: The Prescaler is loaded +* immediatly. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_PrescalerConfig(TIM_TypeDef* TIMx, u16 Prescaler, u16 TIM_PSCReloadMode) +{ + /* Check the parameters */ + assert(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode)); + + /* Set the Prescaler value */ + TIMx->PSC = Prescaler; + + /* Set or reset the UG Bit */ + if (TIM_PSCReloadMode == TIM_PSCReloadMode_Immediate) + { + TIMx->EGR |= TIM_EventSource_Update; + } + else + { + TIMx->EGR &= TIM_EventSource_Update; + } +} + +/******************************************************************************* +* Function Name : TIM_CounterModeConfig +* Description : Specifies the TIMx Counter Mode to be used. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_CounterMode: specifies the Counter Mode to be used +* This parameter can be one of the following values: +* - TIM_CounterMode_Up: TIM Up Counting Mode +* - TIM_CounterMode_Down: TIM Down Counting Mode +* - TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1 +* - TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 +* - TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 +* Output : None +* Return : None +*******************************************************************************/ +void TIM_CounterModeConfig(TIM_TypeDef* TIMx, u16 TIM_CounterMode) +{ + u32 tmpcr1 = 0; + + /* Check the parameters */ + assert(IS_TIM_COUNTER_MODE(TIM_CounterMode)); + + tmpcr1 = TIMx->CR1; + + /* Reset the CMS and DIR Bits */ + tmpcr1 &= CR1_CounterMode_Mask; + + /* Set the Counter Mode */ + tmpcr1 |= TIM_CounterMode; + + TIMx->CR1 = (u16)tmpcr1; +} + +/******************************************************************************* +* Function Name : TIM_ForcedOC1Config +* Description : Forces the TIMx output 1 waveform to active or inactive level. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_ForcedAction: specifies the forced Action to be set to +* the output waveform. +* This parameter can be one of the following values: +* - TIM_ForcedAction_Active: Force active level on OC1REF +* - TIM_ForcedAction_InActive: Force inactive level on +* OC1REF. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction) +{ + u32 tmpccmr1 = 0; + + /* Check the parameters */ + assert(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OCM Bits */ + tmpccmr1 &= CCMR_OCM13_Mask; + + /* Configure The Forced output Mode */ + tmpccmr1 |= TIM_ForcedAction; + + TIMx->CCMR1 = (u16)tmpccmr1; +} + +/******************************************************************************* +* Function Name : TIM_ForcedOC2Config +* Description : Forces the TIMx output 2 waveform to active or inactive level. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_ForcedAction: specifies the forced Action to be set to +* the output waveform. +* This parameter can be one of the following values: +* - TIM_ForcedAction_Active: Force active level on OC2REF +* - TIM_ForcedAction_InActive: Force inactive level on +* OC2REF. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction) +{ + u32 tmpccmr1 = 0; + + /* Check the parameters */ + assert(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OCM Bits */ + tmpccmr1 &= CCMR_OCM24_Mask; + + /* Configure The Forced output Mode */ + tmpccmr1 |= (u16)(TIM_ForcedAction << 8); + + TIMx->CCMR1 = (u16)tmpccmr1; +} + +/******************************************************************************* +* Function Name : TIM_ForcedOC3Config +* Description : Forces the TIMx output 3 waveform to active or inactive level. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_ForcedAction: specifies the forced Action to be set to +* the output waveform. +* This parameter can be one of the following values: +* - TIM_ForcedAction_Active: Force active level on OC3REF +* - TIM_ForcedAction_InActive: Force inactive level on +* OC3REF. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction) +{ + u32 tmpccmr2 = 0; + + /* Check the parameters */ + assert(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OCM Bits */ + tmpccmr2 &= CCMR_OCM13_Mask; + + /* Configure The Forced output Mode */ + tmpccmr2 |= TIM_ForcedAction; + + TIMx->CCMR2 = (u16)tmpccmr2; +} + +/******************************************************************************* +* Function Name : TIM_ForcedOC4Config +* Description : Forces the TIMx output 4 waveform to active or inactive level. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_ForcedAction: specifies the forced Action to be set to +* the output waveform. +* This parameter can be one of the following values: +* - TIM_ForcedAction_Active: Force active level on OC4REF +* - TIM_ForcedAction_InActive: Force inactive level on +* OC4REF. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction) +{ + u32 tmpccmr2 = 0; + + /* Check the parameters */ + assert(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OCM Bits */ + tmpccmr2 &= CCMR_OCM24_Mask; + + /* Configure The Forced output Mode */ + tmpccmr2 |= (u16)(TIM_ForcedAction << 8); + + TIMx->CCMR2 = (u16)tmpccmr2; +} + +/******************************************************************************* +* Function Name : TIM_ARRPreloadConfig +* Description : Enables or disables TIMx peripheral Preload register on ARR. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - Newstate: new state of the TIMx peripheral Preload register +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState Newstate) +{ + u32 tmpcr1 = 0; + + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(Newstate)); + + tmpcr1 = TIMx->CR1; + + if (Newstate != DISABLE) + { + /* Set the ARR Preload Bit */ + tmpcr1 |= CR1_ARPE_Set; + } + else + { + /* Reset the ARR Preload Bit */ + tmpcr1 &= CR1_ARPE_Reset; + } + + TIMx->CR1 = (u16)tmpcr1; +} + +/******************************************************************************* +* Function Name : TIM_SelectCCDMA +* Description : Selects the TIMx peripheral Capture Compare DMA source. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - Newstate: new state of the Capture Compare DMA source +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState Newstate) +{ + u32 tmpcr2 = 0; + + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(Newstate)); + + tmpcr2 = TIMx->CR2; + + if (Newstate != DISABLE) + { + /* Set the CCDS Bit */ + tmpcr2 |= CR2_CCDS_Set; + } + else + { + /* Reset the CCDS Bit */ + tmpcr2 &= CR2_CCDS_Reset; + } + + TIMx->CR2 = (u16)tmpcr2; +} + +/******************************************************************************* +* Function Name : TIM_OC1PreloadConfig +* Description : Enables or disables the TIMx peripheral Preload register on CCR1. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_OCPreload: new state of the TIMx peripheral Preload +* register +* This parameter can be one of the following values: +* - TIM_OCPreload_Enable +* - TIM_OCPreload_Disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload) +{ + u32 tmpccmr1 = 0; + + /* Check the parameters */ + assert(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OCPE Bit */ + tmpccmr1 &= CCMR_OC13PE_Mask; + + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr1 |= TIM_OCPreload; + + TIMx->CCMR1 = (u16)tmpccmr1; +} + +/******************************************************************************* +* Function Name : TIM_OC2PreloadConfig +* Description : Enables or disables the TIMx peripheral Preload register on CCR2. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_OCPreload: new state of the TIMx peripheral Preload +* register +* This parameter can be one of the following values: +* - TIM_OCPreload_Enable +* - TIM_OCPreload_Disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload) +{ + u32 tmpccmr1 = 0; + + /* Check the parameters */ + assert(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OCPE Bit */ + tmpccmr1 &= CCMR_OC24PE_Mask; + + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr1 |= (u16)(TIM_OCPreload << 8); + + TIMx->CCMR1 = (u16)tmpccmr1; +} + +/******************************************************************************* +* Function Name : TIM_OC3PreloadConfig +* Description : Enables or disables the TIMx peripheral Preload register on CCR3. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_OCPreload: new state of the TIMx peripheral Preload +* register +* This parameter can be one of the following values: +* - TIM_OCPreload_Enable +* - TIM_OCPreload_Disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload) +{ + u32 tmpccmr2 = 0; + + /* Check the parameters */ + assert(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OCPE Bit */ + tmpccmr2 &= CCMR_OC13PE_Mask; + + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr2 |= TIM_OCPreload; + + TIMx->CCMR2 = (u16)tmpccmr2; +} + +/******************************************************************************* +* Function Name : TIM_OC4PreloadConfig +* Description : Enables or disables the TIMx peripheral Preload register on CCR4. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_OCPreload: new state of the TIMx peripheral Preload +* register +* This parameter can be one of the following values: +* - TIM_OCPreload_Enable +* - TIM_OCPreload_Disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload) +{ + u32 tmpccmr2 = 0; + + /* Check the parameters */ + assert(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OCPE Bit */ + tmpccmr2 &= CCMR_OC24PE_Mask; + + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr2 |= (u16)(TIM_OCPreload << 8); + + TIMx->CCMR2 = (u16)tmpccmr2; +} + +/******************************************************************************* +* Function Name : TIM_OC1FastConfig +* Description : Configures the TIMx Output Compare 1 Fast feature. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_OCFast: new state of the Output Compare Fast Enable Bit. +* This parameter can be one of the following values: +* - TIM_OCFast_Enable +* - TIM_OCFast_Disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC1FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast) +{ + u32 tmpccmr1 = 0; + + /* Check the parameters */ + assert(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OCFE Bit */ + tmpccmr1 &= CCMR_OC13FE_Mask; + + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr1 |= TIM_OCFast; + + TIMx->CCMR1 = (u16)tmpccmr1; +} + +/******************************************************************************* +* Function Name : TIM_OC2FastConfig +* Description : Configures the TIMx Output Compare 2 Fast feature. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_OCFast: new state of the Output Compare Fast Enable Bit. +* This parameter can be one of the following values: +* - TIM_OCFast_Enable +* - TIM_OCFast_Disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC2FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast) +{ + u32 tmpccmr1 = 0; + + /* Check the parameters */ + assert(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OCFE Bit */ + tmpccmr1 &= CCMR_OC24FE_Mask; + + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr1 |= (u16)(TIM_OCFast << 8); + + TIMx->CCMR1 = (u16)tmpccmr1; +} + +/******************************************************************************* +* Function Name : TIM_OC3FastConfig +* Description : Configures the TIMx Output Compare 3 Fast feature. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_OCFast: new state of the Output Compare Fast Enable Bit. +* This parameter can be one of the following values: +* - TIM_OCFast_Enable +* - TIM_OCFast_Disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC3FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast) +{ + u32 tmpccmr2 = 0; + + /* Check the parameters */ + assert(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OCFE Bit */ + tmpccmr2 &= CCMR_OC13FE_Mask; + + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr2 |= TIM_OCFast; + + TIMx->CCMR2 = (u16)tmpccmr2; +} + +/******************************************************************************* +* Function Name : TIM_OC4FastConfig +* Description : Configures the TIMx Output Compare 4 Fast feature. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_OCFast: new state of the Output Compare Fast Enable Bit. +* This parameter can be one of the following values: +* - TIM_OCFast_Enable +* - TIM_OCFast_Disable +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC4FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast) +{ + u32 tmpccmr2 = 0; + + /* Check the parameters */ + assert(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OCFE Bit */ + tmpccmr2 &= CCMR_OC24FE_Mask; + + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr2 |= (u16)(TIM_OCFast << 8); + + TIMx->CCMR2 = (u16)tmpccmr2; +} + +/******************************************************************************* +* Function Name : TIM_UpdateDisableConfig +* Description : Enables or Disables the TIMx Update event. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - Newstate: new state of the TIMx peripheral Preload register +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState Newstate) +{ + u32 tmpcr1 = 0; + + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(Newstate)); + + tmpcr1 = TIMx->CR1; + + if (Newstate != DISABLE) + { + /* Set the Update Disable Bit */ + tmpcr1 |= CR1_UDIS_Set; + } + else + { + /* Reset the Update Disable Bit */ + tmpcr1 &= CR1_UDIS_Reset; + } + + TIMx->CR1 = (u16)tmpcr1; +} + +/******************************************************************************* +* Function Name : TIM_EncoderInterfaceConfig +* Description : Configures the TIMx Encoder Interface. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_EncoderMode: specifies the TIMx Encoder Mode. +* This parameter can be one of the following values: +* - TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge +* depending on TI2FP2 level. +* - TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge +* depending on TI1FP1 level. +* - TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and +* TI2FP2 edges depending on the level of the other input. +* - TIM_IC1Polarity: specifies the IC1 Polarity +* This parmeter can be one of the following values: +* - TIM_ICPolarity_Falling +* - TIM_ICPolarity_Rising +* - TIM_IC2Polarity: specifies the IC2 Polarity +* This parmeter can be one of the following values: +* - TIM_ICPolarity_Falling +* - TIM_ICPolarity_Rising +* Output : None +* Return : None +*******************************************************************************/ +void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, u16 TIM_EncoderMode, + u16 TIM_IC1Polarity, u16 TIM_IC2Polarity) +{ + u32 tmpsmcr = 0; + u32 tmpccmr1 = 0; + u32 tmpccer = 0; + + /* Check the parameters */ + assert(IS_TIM_ENCODER_MODE(TIM_EncoderMode)); + assert(IS_TIM_IC_POLARITY(TIM_IC1Polarity)); + assert(IS_TIM_IC_POLARITY(TIM_IC2Polarity)); + + tmpsmcr = TIMx->SMCR; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Set the encoder Mode */ + tmpsmcr &= SMCR_SMS_Mask; + tmpsmcr |= TIM_EncoderMode; + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= CCMR_CC13S_Mask & CCMR_CC24S_Mask; + tmpccmr1 |= CCMR_TI13Direct_Set | CCMR_TI24Direct_Set; + + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= CCER_CC1P_Mask & CCER_CC2P_Mask; + tmpccer |= (TIM_IC1Polarity | (u16)((u16)TIM_IC2Polarity << 4)); + + TIMx->SMCR = (u16)tmpsmcr; + + TIMx->CCMR1 = (u16)tmpccmr1; + + TIMx->CCER = (u16)tmpccer; +} + +/******************************************************************************* +* Function Name : TIM_GenerateEvent +* Description : Configures the TIMx event to be generate by software. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_EventSource: specifies the event source. +* This parameter can be one or more of the following values: +* - TIM_EventSource_Update: Timer update Event source +* - TIM_EventSource_CC1: Timer Capture Compare 1 Event source +* - TIM_EventSource_CC2: Timer Capture Compare 2 Event source +* - TIM_EventSource_CC3: Timer Capture Compare 3 Event source +* - TIM_EventSource_CC4: Timer Capture Compare 4 Event source +* - TIM_EventSource_Trigger: Timer Trigger Event source +* Output : None +* Return : None +*******************************************************************************/ +void TIM_GenerateEvent(TIM_TypeDef* TIMx, u16 TIM_EventSource) +{ + /* Check the parameters */ + assert(IS_TIM_EVENT_SOURCE(TIM_EventSource)); + + /* Set the event sources */ + TIMx->EGR |= TIM_EventSource; +} + +/******************************************************************************* +* Function Name : TIM_OC1PolarityConfig +* Description : Configures the TIMx channel 1 polarity. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_OCPolarity: specifies the OC1 Polarity +* This parmeter can be one of the following values: +* - TIM_OCPolarity_High: Output Compare active high +* - TIM_OCPolarity_Low: Output Compare active low +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity) +{ + u32 tmpccer = 0; + + /* Check the parameters */ + assert(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC1P Bit */ + tmpccer &= CCER_CC1P_Mask; + tmpccer |= TIM_OCPolarity; + + TIMx->CCER = (u16)tmpccer; +} + +/******************************************************************************* +* Function Name : TIM_OC2PolarityConfig +* Description : Configures the TIMx channel 2 polarity. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_OCPolarity: specifies the OC2 Polarity +* This parmeter can be one of the following values: +* - TIM_OCPolarity_High: Output Compare active high +* - TIM_OCPolarity_Low: Output Compare active low +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity) +{ + u32 tmpccer = 0; + + /* Check the parameters */ + assert(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC2P Bit */ + tmpccer &= CCER_CC2P_Mask; + tmpccer |= (u16)((u16)TIM_OCPolarity << 4); + + TIMx->CCER = (u16)tmpccer; +} + +/******************************************************************************* +* Function Name : TIM_OC3PolarityConfig +* Description : Configures the TIMx channel 3 polarity. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_OCPolarity: specifies the OC3 Polarity +* This parmeter can be one of the following values: +* - TIM_OCPolarity_High: Output Compare active high +* - TIM_OCPolarity_Low: Output Compare active low +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity) +{ + u32 tmpccer = 0; + + /* Check the parameters */ + assert(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC3P Bit */ + tmpccer &= CCER_CC3P_Mask; + tmpccer |= (u16)((u16)TIM_OCPolarity << 8); + + TIMx->CCER = (u16)tmpccer; +} + +/******************************************************************************* +* Function Name : TIM_OC4PolarityConfig +* Description : Configures the TIMx channel 4 polarity. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_OCPolarity: specifies the OC4 Polarity +* This parmeter can be one of the following values: +* - TIM_OCPolarity_High: Output Compare active high +* - TIM_OCPolarity_Low: Output Compare active low +* Output : None +* Return : None +*******************************************************************************/ +void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity) +{ + u32 tmpccer = 0; + + /* Check the parameters */ + assert(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC4P Bit */ + tmpccer &= CCER_CC4P_Mask; + tmpccer |= (u16)((u16)TIM_OCPolarity << 12); + + TIMx->CCER = (u16)tmpccer; +} + +/******************************************************************************* +* Function Name : TIM_UpdateRequestConfig +* Description : Configures the TIMx Update Request Interrupt source. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_UpdateSource: specifies the Update source. +* This parameter can be one of the following values: +* - TIM_UpdateSource_Regular +* - TIM_UpdateSource_Global +* Output : None +* Return : None +*******************************************************************************/ +void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, u16 TIM_UpdateSource) +{ + u32 tmpcr1 = 0; + + /* Check the parameters */ + assert(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource)); + + tmpcr1 = TIMx->CR1; + + if (TIM_UpdateSource == TIM_UpdateSource_Regular) + { + /* Set the URS Bit */ + tmpcr1 |= CR1_URS_Set; + } + else + { + /* Reset the URS Bit */ + tmpcr1 &= CR1_URS_Reset; + } + TIMx->CR1 = (u16)tmpcr1; +} + +/******************************************************************************* +* Function Name : TIM_SelectHallSensor +* Description : Enables or disables the TIMx’s Hall sensor interface. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - Newstate: new state of the TIMx Hall sensor interface. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState Newstate) +{ + /* Check the parameters */ + assert(IS_FUNCTIONAL_STATE(Newstate)); + + if (Newstate != DISABLE) + { + /* Set the TI1S Bit */ + TIMx->CR2 |= CR2_TI1S_Set; + } + else + { + /* Reset the TI1S Bit */ + TIMx->CR2 &= CR2_TI1S_Reset; + } +} + +/******************************************************************************* +* Function Name : TIM_SelectOnePulseMode +* Description : Selects the TIMx’s One Pulse Mode. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_OPMode: specifies the OPM Mode to be used. +* This parameter can be one of the following values: +* - TIM_OPMode_Single +* - TIM_OPMode_Repetitive +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, u16 TIM_OPMode) +{ + u32 tmpcr1 = 0; + + /* Check the parameters */ + assert(IS_TIM_OPM_MODE(TIM_OPMode)); + + tmpcr1 = TIMx->CR1; + + /* Reset the OPM Bit */ + tmpcr1 &= CR1_OPM_Mask; + + /* Configure the OPM Mode */ + tmpcr1 |= TIM_OPMode; + + TIMx->CR1 = (u16)tmpcr1; +} + +/******************************************************************************* +* Function Name : TIM_SelectOutputTrigger +* Description : Selects the TIMx Trigger Output Mode. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_TRGOSource: specifies the Trigger Output source. +* This paramter can be one of the following values: +* - TIM_TRGOSource_Reset +* - TIM_TRGOSource_Enable +* - TIM_TRGOSource_Update +* - TIM_TRGOSource_OC1 +* - TIM_TRGOSource_OC1Ref +* - TIM_TRGOSource_OC2Ref +* - TIM_TRGOSource_OC3Ref +* - TIM_TRGOSource_OC4Ref +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, u16 TIM_TRGOSource) +{ + u32 tmpcr2 = 0; + + /* Check the parameters */ + assert(IS_TIM_TRGO_SOURCE(TIM_TRGOSource)); + + tmpcr2 = TIMx->CR2; + /* Reset the MMS Bits */ + tmpcr2 &= CR2_MMS_Mask; + + /* Select the TRGO source */ + tmpcr2 |= TIM_TRGOSource; + + TIMx->CR2 = (u16)tmpcr2; +} + +/******************************************************************************* +* Function Name : TIM_SelectSlaveMode +* Description : Selects the TIMx Slave Mode. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_SlaveMode: specifies the Timer Slave Mode. +* This paramter can be one of the following values: +* - TIM_SlaveMode_Reset +* - TIM_SlaveMode_Gated +* - TIM_SlaveMode_Trigger +* - TIM_SlaveMode_External1 +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, u16 TIM_SlaveMode) +{ + u32 tmpsmcr = 0; + + /* Check the parameters */ + assert(IS_TIM_SLAVE_MODE(TIM_SlaveMode)); + + tmpsmcr = TIMx->SMCR; + + /* Reset the SMS Bits */ + tmpsmcr &= SMCR_SMS_Mask; + + /* Select the Slave Mode */ + tmpsmcr |= TIM_SlaveMode; + + TIMx->SMCR = (u16)tmpsmcr; +} + +/******************************************************************************* +* Function Name : TIM_SelectMasterSlaveMode +* Description : Sets or Resets the TIMx Master/Slave Mode. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_MasterSlaveMode: specifies the Timer Master Slave Mode. +* This paramter can be one of the following values: +* - TIM_MasterSlaveMode_Enable: synchronization between the +* current timer and its slaves (through TRGO). +* - TIM_MasterSlaveMode_Disable: No action +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, u16 TIM_MasterSlaveMode) +{ + u32 tmpsmcr = 0; + + /* Check the parameters */ + assert(IS_TIM_MSM_STATE(TIM_MasterSlaveMode)); + + tmpsmcr = TIMx->SMCR; + + /* Set or Reset the MSM Bit */ + tmpsmcr &= SMCR_MSM_Mask; + tmpsmcr |= TIM_MasterSlaveMode; + + TIMx->SMCR = (u16)tmpsmcr; +} + +/******************************************************************************* +* Function Name : TIM_SetAutoreload +* Description : Sets the TIMx Autoreload Register value +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - Autoreload: specifies the Autoreload register new value. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetAutoreload(TIM_TypeDef* TIMx, u16 Autoreload) +{ + /* Set the Autoreload Register value */ + TIMx->ARR = Autoreload; +} + +/******************************************************************************* +* Function Name : TIM_SetCompare1 +* Description : Sets the TIMx Capture Compare1 Register value +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - Compare1: specifies the Capture Compare1 register new value. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetCompare1(TIM_TypeDef* TIMx, u16 Compare1) +{ + /* Set the Capture Compare1 Register value */ + TIMx->CCR1 = Compare1; +} + +/******************************************************************************* +* Function Name : TIM_SetCompare2 +* Description : Sets the TIMx Capture Compare2 Register value +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - Compare2: specifies the Capture Compare2 register new value. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetCompare2(TIM_TypeDef* TIMx, u16 Compare2) +{ + /* Set the Capture Compare2 Register value */ + TIMx->CCR2 = Compare2; +} + +/******************************************************************************* +* Function Name : TIM_SetCompare3 +* Description : Sets the TIMx Capture Compare3 Register value +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - Compare3: specifies the Capture Compare3 register new value. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetCompare3(TIM_TypeDef* TIMx, u16 Compare3) +{ + /* Set the Capture Compare3 Register value */ + TIMx->CCR3 = Compare3; +} + +/******************************************************************************* +* Function Name : TIM_SetCompare4 +* Description : Sets the TIMx Capture Compare4 Register value +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - Compare4: specifies the Capture Compare4 register new value. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetCompare4(TIM_TypeDef* TIMx, u16 Compare4) +{ + /* Set the Capture Compare4 Register value */ + TIMx->CCR4 = Compare4; +} + +/******************************************************************************* +* Function Name : TIM_SetIC1Prescaler +* Description : Sets the TIMx Input Capture 1 prescaler. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_IC1Prescaler: specifies the Input Capture1 prescaler +* new value. +* This parameter can be one of the following values: +* - TIM_ICPSC_DIV1: no prescaler +* - TIM_ICPSC_DIV2: capture is done once every 2 events +* - TIM_ICPSC_DIV4: capture is done once every 4 events +* - TIM_ICPSC_DIV8: capture is done once every 8 events +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC1Prescaler) +{ + u32 tmpccmr1 = 0; + + /* Check the parameters */ + assert(IS_TIM_IC_PRESCALER(TIM_IC1Prescaler)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the IC1PSC Bits */ + tmpccmr1 &= CCMR_IC13PSC_Mask; + + /* Set the IC1PSC value */ + tmpccmr1 |= TIM_IC1Prescaler; + + TIMx->CCMR1 = (u16)tmpccmr1; +} + +/******************************************************************************* +* Function Name : TIM_SetIC2Prescaler +* Description : Sets the TIMx Input Capture 2 prescaler. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_IC2Prescaler: specifies the Input Capture2 prescaler +* new value. +* This parameter can be one of the following values: +* - TIM_ICPSC_DIV1: no prescaler +* - TIM_ICPSC_DIV2: capture is done once every 2 events +* - TIM_ICPSC_DIV4: capture is done once every 4 events +* - TIM_ICPSC_DIV8: capture is done once every 8 events +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC2Prescaler) +{ + u32 tmpccmr1 = 0; + + /* Check the parameters */ + assert(IS_TIM_IC_PRESCALER(TIM_IC2Prescaler)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the IC2PSC Bits */ + tmpccmr1 &= CCMR_IC24PSC_Mask; + + /* Set the IC2PSC value */ + tmpccmr1 |= (u16)((u16)TIM_IC2Prescaler << 8); + + TIMx->CCMR1 = (u16)tmpccmr1; +} + +/******************************************************************************* +* Function Name : TIM_SetIC3Prescaler +* Description : Sets the TIMx Input Capture 3 prescaler. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_IC3Prescaler: specifies the Input Capture3 prescaler +* new value. +* This parameter can be one of the following values: +* - TIM_ICPSC_DIV1: no prescaler +* - TIM_ICPSC_DIV2: capture is done once every 2 events +* - TIM_ICPSC_DIV4: capture is done once every 4 events +* - TIM_ICPSC_DIV8: capture is done once every 8 events +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC3Prescaler) +{ + u32 tmpccmr2 = 0; + + /* Check the parameters */ + assert(IS_TIM_IC_PRESCALER(TIM_IC3Prescaler)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the IC3PSC Bits */ + tmpccmr2 &= CCMR_IC13PSC_Mask; + + /* Set the IC3PSC value */ + tmpccmr2 |= TIM_IC3Prescaler; + + TIMx->CCMR2 = (u16)tmpccmr2; +} + +/******************************************************************************* +* Function Name : TIM_SetIC4Prescaler +* Description : Sets the TIMx Input Capture 4 prescaler. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_IC4Prescaler: specifies the Input Capture4 prescaler +* new value. +* This parameter can be one of the following values: +* - TIM_ICPSC_DIV1: no prescaler +* - TIM_ICPSC_DIV2: capture is done once every 2 events +* - TIM_ICPSC_DIV4: capture is done once every 4 events +* - TIM_ICPSC_DIV8: capture is done once every 8 events +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC4Prescaler) +{ + u32 tmpccmr2 = 0; + + /* Check the parameters */ + assert(IS_TIM_IC_PRESCALER(TIM_IC4Prescaler)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the IC4PSC Bits */ + tmpccmr2 &= CCMR_IC24PSC_Mask; + + /* Set the IC4PSC value */ + tmpccmr2 |= (u16)((u16)TIM_IC4Prescaler << 8); + + TIMx->CCMR2 = (u16)tmpccmr2; +} + +/******************************************************************************* +* Function Name : TIM_SetClockDivision +* Description : Sets the TIMx Clock Division value. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_CKD: specifies the clock division value. +* This parameter can be one of the following value: +* - TIM_CKD_DIV1: TDTS = Tck_tim +* - TIM_CKD_DIV2: TDTS = 2*Tck_tim +* - TIM_CKD_DIV4: TDTS = 4*Tck_tim +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetClockDivision(TIM_TypeDef* TIMx, u16 TIM_CKD) +{ + u32 tmpcr1 = 0; + + /* Check the parameters */ + assert(IS_TIM_CKD_DIV(TIM_CKD)); + + tmpcr1 = TIMx->CR1; + + /* Reset the CKD Bits */ + tmpcr1 &= CR1_CKD_Mask; + + /* Set the CKD value */ + tmpcr1 |= TIM_CKD; + + TIMx->CR1 = (u16)tmpcr1; +} + +/******************************************************************************* +* Function Name : TIM_GetCapture1 +* Description : Gets the TIMx Input Capture 1 value. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* Output : None +* Return : Capture Compare 1 Register value. +*******************************************************************************/ +u16 TIM_GetCapture1(TIM_TypeDef* TIMx) +{ + /* Get the Capture 1 Register value */ + return TIMx->CCR1; +} + +/******************************************************************************* +* Function Name : TIM_GetCapture2 +* Description : Gets the TIMx Input Capture 2 value. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* Output : None +* Return : Capture Compare 2 Register value. +*******************************************************************************/ +u16 TIM_GetCapture2(TIM_TypeDef* TIMx) +{ + /* Get the Capture 2 Register value */ + return TIMx->CCR2; +} + +/******************************************************************************* +* Function Name : TIM_GetCapture3 +* Description : Gets the TIMx Input Capture 3 value. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* Output : None +* Return : Capture Compare 3 Register value. +*******************************************************************************/ +u16 TIM_GetCapture3(TIM_TypeDef* TIMx) +{ + /* Get the Capture 3 Register value */ + return TIMx->CCR3; +} + +/******************************************************************************* +* Function Name : TIM_GetCapture4 +* Description : Gets the TIMx Input Capture 4 value. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* Output : None +* Return : Capture Compare 4 Register value. +*******************************************************************************/ +u16 TIM_GetCapture4(TIM_TypeDef* TIMx) +{ + /* Get the Capture 4 Register value */ + return TIMx->CCR4; +} + +/******************************************************************************* +* Function Name : TIM_GetCounter +* Description : Gets the TIMx Counter value. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* Output : None +* Return : Counter Register value. +*******************************************************************************/ +u16 TIM_GetCounter(TIM_TypeDef* TIMx) +{ + /* Get the Counter Register value */ + return TIMx->CNT; +} + +/******************************************************************************* +* Function Name : TIM_GetPrescaler +* Description : Gets the TIMx Prescaler value. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* Output : None +* Return : Prescaler Register value. +*******************************************************************************/ +u16 TIM_GetPrescaler(TIM_TypeDef* TIMx) +{ + /* Get the Prescaler Register value */ + return TIMx->PSC; +} + +/******************************************************************************* +* Function Name : TIM_GetFlagStatus +* Description : Checks whether the specified TIMx flag is set or not. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - TIM_FLAG_Update: Timer update Flag +* - TIM_FLAG_CC1: Timer Capture Compare 1 Flag +* - TIM_FLAG_CC2: Timer Capture Compare 2 Flag +* - TIM_FLAG_CC3: Timer Capture Compare 3 Flag +* - TIM_FLAG_CC4: Timer Capture Compare 4 Flag +* - TIM_FLAG_Trigger: Timer Trigger Flag +* - TIM_FLAG_CC1OF: Timer Capture Compare 1 overcapture Flag +* - TIM_FLAG_CC2OF: Timer Capture Compare 2 overcapture Flag +* - TIM_FLAG_CC3OF: Timer Capture Compare 3 overcapture Flag +* - TIM_FLAG_CC4OF: Timer Capture Compare 4 overcapture Flag +* Output : None +* Return : The new state of TIM_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, u16 TIM_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert(IS_TIM_GET_FLAG(TIM_FLAG)); + + if ((TIMx->SR & TIM_FLAG) != (u16)RESET ) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : TIM_ClearFlag +* Description : Clears the TIMx's pending flags. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_FLAG: specifies the flag bit to clear. +* This parameter can be any combination of the following values: +* - TIM_FLAG_Update: Timer update Flag +* - TIM_FLAG_CC1: Timer Capture Compare 1 Flag +* - TIM_FLAG_CC2: Timer Capture Compare 2 Flag +* - TIM_FLAG_CC3: Timer Capture Compare 3 Flag +* - TIM_FLAG_CC4: Timer Capture Compare 4 Flag +* - TIM_FLAG_Trigger: Timer Trigger Flag +* - TIM_FLAG_CC1OF: Timer Capture Compare 1 overcapture Flag +* - TIM_FLAG_CC2OF: Timer Capture Compare 2 overcapture Flag +* - TIM_FLAG_CC3OF: Timer Capture Compare 3 overcapture Flag +* - TIM_FLAG_CC4OF: Timer Capture Compare 4 overcapture Flag +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ClearFlag(TIM_TypeDef* TIMx, u16 TIM_FLAG) +{ + /* Check the parameters */ + assert(IS_TIM_CLEAR_FLAG(TIM_FLAG)); + + /* Clear the flags */ + TIMx->SR &= (u16)~TIM_FLAG; +} + +/******************************************************************************* +* Function Name : TIM_GetITStatus +* Description : Checks whether the TIMx interrupt has occurred or not. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_IT: specifies the TIM interrupt source to check. +* This parameter can be one of the following values: +* - TIM_IT_Update: Timer update Interrupt source +* - TIM_IT_CC1: Timer Capture Compare 1 Interrupt source +* - TIM_IT_CC2: Timer Capture Compare 2 Interrupt source +* - TIM_IT_CC3: Timer Capture Compare 3 Interrupt source +* - TIM_IT_CC4: Timer Capture Compare 4 Interrupt source +* - TIM_IT_Trigger: Timer Trigger Interrupt source +* Output : None +* Return : The new state of the TIM_IT(SET or RESET). +*******************************************************************************/ +ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, u16 TIM_IT) +{ + ITStatus bitstatus = RESET; + + u16 itstatus = 0x0, itenable = 0x0; + + /* Check the parameters */ + assert(IS_TIM_GET_IT(TIM_IT)); + + itstatus = TIMx->SR & TIM_IT; + + itenable = TIMx->DIER & TIM_IT; + + if ((itstatus != (u16)RESET) && (itenable != (u16)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/******************************************************************************* +* Function Name : TIM_ClearITPendingBit +* Description : Clears the TIMx's interrupt pending bits. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_IT: specifies the pending bit to clear. +* This parameter can be any combination of the following values: +* - TIM_IT_Update: Timer update Interrupt source +* - TIM_IT_CC1: Timer Capture Compare 1 Interrupt source +* - TIM_IT_CC2: Timer Capture Compare 2 Interrupt source +* - TIM_IT_CC3: Timer Capture Compare 3 Interrupt source +* - TIM_IT_CC4: Timer Capture Compare 4 Interrupt source +* - TIM_IT_Trigger: Timer Trigger Interrupt source +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, u16 TIM_IT) +{ + /* Check the parameters */ + assert(IS_TIM_IT(TIM_IT)); + + /* Clear the IT pending Bit */ + TIMx->SR &= (u16)~TIM_IT; +} + +/******************************************************************************* +* Function Name : PWMInput_Config +* Description : Configures the TIM peripheral according to the specified +* parameters in the TIM_ICInitStruct to measure an external PWM +* signal. +* Input : - TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure +* that contains the configuration information for the specified +* TIM peripheral. +* Output : None +* Return : None +*******************************************************************************/ +static void PWMI_Config(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + u8 ICPolarity = TIM_ICPolarity_Rising; + u8 ICSelection = TIM_ICSelection_DirectTI; + + /* Select the Opposite Input Polarity */ + if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) + { + ICPolarity = TIM_ICPolarity_Falling; + } + else + { + ICPolarity = TIM_ICPolarity_Rising; + } + + /* Select the Opposite Input */ + if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) + { + ICSelection = TIM_ICSelection_IndirectTI; + } + else + { + ICSelection = TIM_ICSelection_DirectTI; + } + + if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + /* TI1 Configuration */ + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + + /* TI2 Configuration */ + TI2_Config(TIMx, ICPolarity, ICSelection, TIM_ICInitStruct->TIM_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + /* TI1 Configuration */ + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + + /* TI2 Configuration */ + TI1_Config(TIMx, ICPolarity, ICSelection, TIM_ICInitStruct->TIM_ICFilter); + + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/******************************************************************************* +* Function Name : TI1_Config +* Description : Configure the TI1 as Input. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_ICPolarity : The Input Polarity. +* This parameter can be one of the following values: +* - TIM_ICPolarity_Rising +* - TIM_ICPolarity_Falling +* - TIM_ICSelection: specifies the input to be used. +* This parameter can be one of the following values: +* - TIM_ICSelection_DirectTI: TIM Input 1 is selected to +* be connected to IC1. +* - TIM_ICSelection_IndirectTI: TIM Input 1 is selected to +* be connected to IC2. +* - TIM_ICSelection_TRGI: TIM Input 1 is selected to be +* connected to TRGI. +* - TIM_ICFilter: Specifies the Input Capture Filter. +* This parameter must be a value between 0x00 and 0x0F. +* Output : None +* Return : None +*******************************************************************************/ +static void TI1_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection, + u8 TIM_ICFilter) +{ + u32 tmpccmr1 = 0, tmpccer = 0; + + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Disable the Channel 1: Reset the CCE Bit */ + TIMx->CCER &= CCRE_CC1E_Reset; + + /* Select the Input and set the filter */ + tmpccmr1 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask; + tmpccmr1 |= TIM_ICSelection | (u16)((u16)TIM_ICFilter << 4); + + /* Select the Polarity and set the CCE Bit */ + tmpccer &= CCER_CC1P_Mask & CCRE_CC1E_Mask; + tmpccer |= TIM_ICPolarity | CCRE_CC1E_Set; + + TIMx->CCMR1 = 0x0000; + TIMx->CCMR1 = (u16)tmpccmr1; + TIMx->CCER = (u16)tmpccer; +} + +/******************************************************************************* +* Function Name : TI2_Config +* Description : Configure the TI2 as Input. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_ICPolarity : The Input Polarity. +* This parameter can be one of the following values: +* - TIM_ICPolarity_Rising +* - TIM_ICPolarity_Falling +* - TIM_ICSelection: specifies the input to be used. +* This parameter can be one of the following values: +* - TIM_ICSelection_DirectTI: TIM Input 2 is selected to +* be connected to IC2. +* - TIM_ICSelection_IndirectTI: TIM Input 2 is selected to +* be connected to IC1. +* - TIM_ICSelection_TRGI: TIM Input 2 is selected to be +* connected to TRGI. +* - TIM_ICFilter: Specifies the Input Capture Filter. +* This parameter must be a value between 0x00 and 0x0F. +* Output : None +* Return : None +*******************************************************************************/ +static void TI2_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection, + u8 TIM_ICFilter) +{ + u32 tmpccmr1 = 0, tmpccer = 0, tmp = 0; + + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + tmp = (u16)((u16)TIM_ICPolarity << 4); + + /* Disable the Channel 2: Reset the CCE Bit */ + TIMx->CCER &= CCRE_CC2E_Reset; + + /* Select the Input and set the filter */ + tmpccmr1 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask; + tmpccmr1 |= (u16)((u16)TIM_ICFilter << 12); + tmpccmr1 |= (u16)((u16)TIM_ICSelection << 8); + + /* Select the Polarity and set the CCE Bit */ + tmpccer &= CCER_CC2P_Mask & CCRE_CC2E_Mask; + tmpccer |= tmp | CCRE_CC2E_Set; + + TIMx->CCMR1 = (u16)tmpccmr1 ; + TIMx->CCER = (u16)tmpccer; +} + +/******************************************************************************* +* Function Name : TI3_Config +* Description : Configure the TI3 as Input. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_ICPolarity : The Input Polarity. +* This parameter can be one of the following values: +* - TIM_ICPolarity_Rising +* - TIM_ICPolarity_Falling +* - TIM_ICSelection: specifies the input to be used. +* This parameter can be one of the following values: +* - TIM_ICSelection_DirectTI: TIM Input 3 is selected to +* be connected to IC3. +* - TIM_ICSelection_IndirectTI: TIM Input 3 is selected to +* be connected to IC4. +* - TIM_ICSelection_TRGI: TIM Input 3 is selected to be +* connected to TRGI. +* - TIM_ICFilter: Specifies the Input Capture Filter. +* This parameter must be a value between 0x00 and 0x0F. +* Output : None +* Return : None +*******************************************************************************/ +static void TI3_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection, + u8 TIM_ICFilter) +{ + u32 tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + tmp = (u16)((u16)TIM_ICPolarity << 8); + + /* Disable the Channel 3: Reset the CCE Bit */ + TIMx->CCER &= CCRE_CC3E_Reset; + + /* Select the Input and set the filter */ + tmpccmr2 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask; + tmpccmr2 |= TIM_ICSelection | (u16)((u16)TIM_ICFilter << 4); + + /* Select the Polarity and set the CCE Bit */ + tmpccer &= CCER_CC1P_Mask & CCRE_CC1E_Mask; + tmpccer |= tmp | CCRE_CC3E_Set; + + TIMx->CCMR2 = (u16)tmpccmr2; + TIMx->CCER = (u16)tmpccer; +} + +/******************************************************************************* +* Function Name : TI4_Config +* Description : Configure the TI1 as Input. +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_ICPolarity : The Input Polarity. +* This parameter can be one of the following values: +* - TIM_ICPolarity_Rising +* - TIM_ICPolarity_Falling +* - TIM_ICSelection: specifies the input to be used. +* This parameter can be one of the following values: +* - TIM_ICSelection_DirectTI: TIM Input 4 is selected to +* be connected to IC4. +* - TIM_ICSelection_IndirectTI: TIM Input 4 is selected to +* be connected to IC3. +* - TIM_ICSelection_TRGI: TIM Input 4 is selected to be +* connected to TRGI. +* - TIM_ICFilter: Specifies the Input Capture Filter. +* This parameter must be a value between 0x00 and 0x0F. +* Output : None +* Return : None +*******************************************************************************/ +static void TI4_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection, + u8 TIM_ICFilter) +{ + u32 tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + tmp = (u16)((u16)TIM_ICPolarity << 12); + + /* Disable the Channel 4: Reset the CCE Bit */ + TIMx->CCER &= CCRE_CC4E_Reset; + + /* Select the Input and set the filter */ + tmpccmr2 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask; + tmpccmr2 |= (u16)((u16)TIM_ICSelection << 8) | (u16)((u16)TIM_ICFilter << 12); + + /* Select the Polarity and set the CCE Bit */ + tmpccer &= CCER_CC4P_Mask & CCRE_CC4E_Mask; + tmpccer |= tmp | CCRE_CC4E_Set; + + TIMx->CCMR2 = (u16)tmpccmr2; + TIMx->CCER = (u16)tmpccer ; +} + +/******************************************************************************* +* Function Name : ETR_Config +* Description : Configure the External Trigger +* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. +* - TIM_ExtTRGPrescaler: The external Trigger Prescaler. +* This parameter can be one of the following values: +* - TIM_ExtTRGPSC_OFF +* - TIM_ExtTRGPSC_DIV2 +* - TIM_ExtTRGPSC_DIV4 +* - TIM_ExtTRGPSC_DIV8 +* - TIM_ExtTRGPolarity: The external Trigger Polarity. +* This parameter can be one of the following values: +* - TIM_ExtTRGPolarity_Inverted +* - TIM_ExtTRGPolarity_NonInverted +* - ExtTRGFilter: External Trigger Filter. +* This parameter must be a value between 0x00 and 0x0F. +* Output : None +* Return : None +*******************************************************************************/ +static void ETR_Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, u16 TIM_ExtTRGPolarity, + u8 ExtTRGFilter) +{ + u32 tmpsmcr = 0; + + tmpsmcr = TIMx->SMCR; + + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr &= SMCR_ETR_Mask; + tmpsmcr |= TIM_ExtTRGPrescaler | TIM_ExtTRGPolarity | (u16)((u16)ExtTRGFilter << 8); + + TIMx->SMCR = (u16)tmpsmcr; +} +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/20080212/Demo/CORTEX_STM32F103_Primer_GCC/bitmap.h b/20080212/Demo/CORTEX_STM32F103_Primer_GCC/bitmap.h new file mode 100644 index 000000000..b4dd85214 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_Primer_GCC/bitmap.h @@ -0,0 +1,3367 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* FreeRTOS.org Logo as a 16bit bitmap. */ + +#ifndef BITMAP_H +#define BITMAP_H + +const unsigned short pucImage[] = +{ +0xffff, +0xffff, +0xe006, +0xe006, +0xe006, +0xe006, +0xe006, +0xe006, +0xe006, +0xe006, +0xe006, +0xe006, +0xe006, +0xe006, +0xe006, +0xe006, +0xe006, +0xe006, +0xe006, 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FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + * Creates all the demo application tasks, then starts the scheduler. The WEB + * documentation provides more details of the standard demo application tasks. + * In addition to the standard demo tasks, the following tasks and tests are + * defined and/or created within this file: + * + * "Fast Interrupt Test" - A high frequency periodic interrupt is generated + * using a free running timer to demonstrate the use of the + * configKERNEL_INTERRUPT_PRIORITY configuration constant. The interrupt + * service routine measures the number of processor clocks that occur between + * each interrupt - and in so doing measures the jitter in the interrupt timing. + * The maximum measured jitter time is latched in the ulMaxJitter variable, and + * displayed on the LCD by the 'Check' task as described below. The + * fast interrupt is configured and handled in the timertest.c source file. + * + * "LCD" task - the LCD task is a 'gatekeeper' task. It is the only task that + * is permitted to access the display directly. Other tasks wishing to write a + * message to the LCD send the message on a queue to the LCD task instead of + * accessing the LCD themselves. The LCD task just blocks on the queue waiting + * for messages - waking and displaying the messages as they arrive. Messages + * can either be a text string to display, or an instruction to update MEMS + * input. The MEMS input is used to display a ball that can be moved around + * LCD by tilting the STM32 Primer. 45% is taken as the neutral position. + * + * "Check" task - This only executes every five seconds but has the highest + * priority so is guaranteed to get processor time. Its main function is to + * check that all the standard demo tasks are still operational. Should any + * unexpected behaviour within a demo task be discovered the 'check' task will + * write an error to the LCD (via the LCD task). If all the demo tasks are + * executing with their expected behaviour then the check task writes PASS + * along with the max jitter time to the LCD (again via the LCD task), as + * described above. + * + * Tick Hook - A tick hook is provided just for demonstration purposes. In + * this case it is used to periodically send an instruction to updated the + * MEMS input to the LCD task. + * + */ + +/* CircleOS includes. Some of the CircleOS peripheral functionality is +utilised, although CircleOS itself is not used. */ +#include "circle.h" + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "Task.h" +#include "Queue.h" + +/* Demo app includes. */ +#include "BlockQ.h" +#include "blocktim.h" +#include "GenQTest.h" +#include "partest.h" +#include "QPeek.h" + +/* The bitmap used to display the FreeRTOS.org logo is stored in 16bit format +and therefore takes up a large proportion of the Flash space. Setting this +parameter to 0 excludes the bitmap from the build, freeing up Flash space for +extra code. */ +#define mainINCLUDE_BITMAP 1 + +#if mainINCLUDE_BITMAP == 1 + #include "bitmap.h" +#endif + +/* Task priorities. */ +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainGEN_Q_PRIORITY ( tskIDLE_PRIORITY + 0 ) +#define mainFLASH_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) + +/* Splash screen related constants. */ +#define mainBITMAP_Y ( 38 ) +#define mainBITMAP_X ( 18 ) +#define mainURL_Y ( 8 ) +#define mainURL_X ( 78 ) +#define mainSPLASH_SCREEN_DELAY ( 2000 / portTICK_RATE_MS ) + +/* Text drawing related constants. */ +#define mainLCD_CHAR_HEIGHT ( 13 ) +#define mainLCD_MAX_Y ( 110 ) + +/* The maximum number of message that can be waiting for display at any one +time. */ +#define mainLCD_QUEUE_SIZE ( 3 ) + +/* The check task uses the sprintf function so requires a little more stack. */ +#define mainCHECK_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE + 50 ) + +/* The LCD task calls some of the CircleOS functions (for MEMS and LCD access), +these can require a larger stack. */ +#define configLCD_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE + 50 ) + +/* Dimensions the buffer into which the jitter time is written. */ +#define mainMAX_MSG_LEN 25 + +/* The time between cycles of the 'check' task. */ +#define mainCHECK_DELAY ( ( portTickType ) 5000 / portTICK_RATE_MS ) + +/* The period at which the MEMS input should be updated. */ +#define mainMEMS_DELAY ( ( portTickType ) 100 / portTICK_RATE_MS ) + +/* The rate at which the flash task toggles the LED. */ +#define mainFLASH_DELAY ( ( portTickType ) 1000 / portTICK_RATE_MS ) + +/* The number of nano seconds between each processor clock. */ +#define mainNS_PER_CLOCK ( ( unsigned portLONG ) ( ( 1.0 / ( double ) configCPU_CLOCK_HZ ) * 1000000000.0 ) ) + +/* The two types of message that can be sent to the LCD task. */ +#define mainUPDATE_BALL_MESSAGE ( 0 ) +#define mainWRITE_STRING_MESSAGE ( 1 ) + +/* Type of the message sent to the LCD task. */ +typedef struct +{ + portBASE_TYPE xMessageType; + signed char *pcMessage; +} xLCDMessage; + +/*-----------------------------------------------------------*/ + +/* + * Configure the clocks, GPIO and other peripherals as required by the demo. + */ +static void prvSetupHardware( void ); + +/* + * The LCD is written two by more than one task so is controlled by a + * 'gatekeeper' task. This is the only task that is actually permitted to + * access the LCD directly. Other tasks wanting to display a message send + * the message to the gatekeeper. + */ +static void prvLCDTask( void *pvParameters ); + +/* + * Checks the status of all the demo tasks then prints a message to the + * display. The message will be either PASS - and include in brackets the + * maximum measured jitter time (as described at the to of the file), or a + * message that describes which of the standard demo tasks an error has been + * discovered in. + * + * Messages are not written directly to the terminal, but passed to prvLCDTask + * via a queue. + * + * The check task also receives instructions to update the MEMS input, which + * in turn can also lead to the LCD being updated. + */ +static void prvCheckTask( void *pvParameters ); + +/* + * Configures the timers and interrupts for the fast interrupt test as + * described at the top of this file. + */ +extern void vSetupTimerTest( void ); + +/* + * A cut down version of sprintf() used to percent the HUGE GCC library + * equivalent from being included in the binary image. + */ +extern int sprintf(char *out, const char *format, ...); + +/* + * Simple toggle the LED periodically for timing verification. + */ +static void prvFlashTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* The queue used to send messages to the LCD task. */ +xQueueHandle xLCDQueue; + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + #ifdef DEBUG + debug(); + #endif + + prvSetupHardware(); + + /* Create the queue used by the LCD task. Messages for display on the LCD + are received via this queue. */ + xLCDQueue = xQueueCreate( mainLCD_QUEUE_SIZE, sizeof( xLCDMessage ) ); + + /* Start the standard demo tasks. */ + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vCreateBlockTimeTasks(); + vStartGenericQueueTasks( mainGEN_Q_PRIORITY ); + vStartQueuePeekTasks(); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + + /* Start the tasks defined within this file/specific to this demo. */ + xTaskCreate( prvCheckTask, ( signed portCHAR * ) "Check", mainCHECK_TASK_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + xTaskCreate( prvLCDTask, ( signed portCHAR * ) "LCD", configLCD_TASK_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + xTaskCreate( prvFlashTask, ( signed portCHAR * ) "Flash", configMINIMAL_STACK_SIZE, NULL, mainFLASH_TASK_PRIORITY, NULL ); + + /* Configure the timers used by the fast interrupt timer test. */ + vSetupTimerTest(); + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* Will only get here if there was not enough heap space to create the + idle task. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void prvLCDTask( void *pvParameters ) +{ +xLCDMessage xMessage; +portCHAR cY = mainLCD_CHAR_HEIGHT; +const portCHAR * const pcString = "www.FreeRTOS.org"; +const portCHAR * const pcBlankLine = " "; + + DRAW_Init(); + + #if mainINCLUDE_BITMAP == 1 + DRAW_SetImage( pucImage, mainBITMAP_Y, mainBITMAP_X, bmpBITMAP_HEIGHT, bmpBITMAP_WIDTH ); + #endif + + LCD_SetScreenOrientation( V9 ); + DRAW_DisplayString( mainURL_Y, mainURL_X, pcString, strlen( pcString ) ); + vTaskDelay( mainSPLASH_SCREEN_DELAY ); + LCD_FillRect( 0, 0, CHIP_SCREEN_WIDTH, CHIP_SCREEN_HEIGHT, RGB_WHITE ); + + for( ;; ) + { + /* Wait for a message to arrive that requires displaying. */ + while( xQueueReceive( xLCDQueue, &xMessage, portMAX_DELAY ) != pdPASS ); + + /* Check the message type. */ + if( xMessage.xMessageType == mainUPDATE_BALL_MESSAGE ) + { + /* Read the MEMS and update the ball display on the LCD if required. */ + MEMS_Handler(); + POINTER_Handler(); + } + else + { + /* A text string was sent. First blank off the old text string, then + draw the new text on the next line down. */ + DRAW_DisplayString( 0, cY, pcBlankLine, strlen( pcBlankLine ) ); + + cY -= mainLCD_CHAR_HEIGHT; + if( cY <= ( mainLCD_CHAR_HEIGHT - 1 ) ) + { + /* Wrap the line onto which we are going to write the text. */ + cY = mainLCD_MAX_Y; + } + + /* Display the message. */ + DRAW_DisplayString( 0, cY, xMessage.pcMessage, strlen( xMessage.pcMessage ) ); + } + } +} +/*-----------------------------------------------------------*/ + +static void prvCheckTask( void *pvParameters ) +{ +portTickType xLastExecutionTime; +xLCDMessage xMessage; +static signed portCHAR cPassMessage[ mainMAX_MSG_LEN ]; +extern unsigned portSHORT usMaxJitter; + + /* Initialise the xLastExecutionTime variable on task entry. */ + xLastExecutionTime = xTaskGetTickCount(); + + /* Setup the message we are going to send to the LCD task. */ + xMessage.xMessageType = mainWRITE_STRING_MESSAGE; + xMessage.pcMessage = cPassMessage; + + for( ;; ) + { + /* Perform this check every mainCHECK_DELAY milliseconds. */ + vTaskDelayUntil( &xLastExecutionTime, mainCHECK_DELAY ); + + /* Has an error been found in any task? If so then point the text + we are going to send to the LCD task to an error message instead of + the PASS message. */ + if( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN GEN Q"; + } + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN BLOCK Q"; + } + else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN BLOCK TIME"; + } + else if( xArePollingQueuesStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN POLL Q"; + } + else if( xAreQueuePeekTasksStillRunning() != pdTRUE ) + { + xMessage.pcMessage = "ERROR IN PEEK Q"; + } + else + { + /* No errors were found in any task, so send a pass message + with the max measured jitter time also included (as per the + fast interrupt test described at the top of this file and on + the online documentation page for this demo application). */ + sprintf( ( portCHAR * ) cPassMessage, "PASS [%uns]", ( ( unsigned portLONG ) usMaxJitter ) * mainNS_PER_CLOCK ); + } + + /* Send the message to the LCD gatekeeper for display. */ + xQueueSend( xLCDQueue, &xMessage, portMAX_DELAY ); + } +} +/*-----------------------------------------------------------*/ + +void vApplicationTickHook( void ) +{ +static unsigned portLONG ulCallCount; +static const xLCDMessage xMemsMessage = { mainUPDATE_BALL_MESSAGE, NULL }; + + /* Periodically send a message to the LCD task telling it to update + the MEMS input, and then if necessary the LCD. */ + ulCallCount++; + if( ulCallCount >= mainMEMS_DELAY ) + { + ulCallCount = 0; + xQueueSendFromISR( xLCDQueue, &xMemsMessage, pdFALSE ); + } +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Start with the clocks in their expected state. */ + RCC_DeInit(); + + /* Enable HSE (high speed external clock). */ + RCC_HSEConfig( RCC_HSE_ON ); + + /* Wait till HSE is ready. */ + while( RCC_GetFlagStatus( RCC_FLAG_HSERDY ) == RESET ) + { + } + + /* 2 wait states required on the flash. */ + *( ( unsigned portLONG * ) 0x40022000 ) = 0x02; + + /* HCLK = SYSCLK */ + RCC_HCLKConfig( RCC_SYSCLK_Div1 ); + + /* PCLK2 = HCLK */ + RCC_PCLK2Config( RCC_HCLK_Div1 ); + + /* PCLK1 = HCLK/2 */ + RCC_PCLK1Config( RCC_HCLK_Div2 ); + + /* PLLCLK = 12MHz * 6 = 72 MHz. */ + RCC_PLLConfig( RCC_PLLSource_HSE_Div1, RCC_PLLMul_6 ); + + /* Enable PLL. */ + RCC_PLLCmd( ENABLE ); + + /* Wait till PLL is ready. */ + while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) + { + } + + /* Select PLL as system clock source. */ + RCC_SYSCLKConfig( RCC_SYSCLKSource_PLLCLK ); + + /* Wait till PLL is used as system clock source. */ + while( RCC_GetSYSCLKSource() != 0x08 ) + { + } + + /* Enable GPIOA, GPIOB, GPIOC, GPIOD, GPIOE and AFIO clocks */ + RCC_APB2PeriphClockCmd( RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB |RCC_APB2Periph_GPIOC + | RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE | RCC_APB2Periph_AFIO, ENABLE ); + + /* SPI2 Periph clock enable */ + RCC_APB1PeriphClockCmd( RCC_APB1Periph_SPI2, ENABLE ); + + + /* Set the Vector Table base address at 0x08000000 */ + NVIC_SetVectorTable( NVIC_VectTab_FLASH, 0x0 ); + + NVIC_PriorityGroupConfig( NVIC_PriorityGroup_4 ); + + /* Configure HCLK clock as SysTick clock source. */ + SysTick_CLKSourceConfig( SysTick_CLKSource_HCLK ); + + /* Misc initialisation, including some of the CircleOS features. Note + that CircleOS itself is not used. */ + vParTestInitialise(); + MEMS_Init(); + POINTER_Init(); + POINTER_SetMode( POINTER_RESTORE_LESS ); +} +/*-----------------------------------------------------------*/ + +static void prvFlashTask( void *pvParameters ) +{ +portTickType xLastExecutionTime; + + /* Initialise the xLastExecutionTime variable on task entry. */ + xLastExecutionTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Simple toggle the LED periodically. This just provides some timing + verification. */ + vTaskDelayUntil( &xLastExecutionTime, mainFLASH_DELAY ); + vParTestToggleLED( 0 ); + } +} +/*-----------------------------------------------------------*/ + +void starting_delay( unsigned long ul ) +{ + vTaskDelay( ( portTickType ) ul ); +} + + + diff --git a/20080212/Demo/CORTEX_STM32F103_Primer_GCC/printf-stdarg.c b/20080212/Demo/CORTEX_STM32F103_Primer_GCC/printf-stdarg.c new file mode 100644 index 000000000..45a824384 --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_Primer_GCC/printf-stdarg.c @@ -0,0 +1,280 @@ +/* + Copyright 2001, 2002 Georges Menie (www.menie.org) + stdarg version contributed by Christian Ettinger + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU Lesser General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +*/ + +/* + putchar is the only external dependency for this file, + if you have a working putchar, leave it commented out. + If not, uncomment the define below and + replace outbyte(c) by your own function call. + +#define putchar(c) outbyte(c) +*/ + +#include + +static void printchar(char **str, int c) +{ + extern int putchar(int c); + + if (str) { + **str = c; + ++(*str); + } + else (void)putchar(c); +} + +#define PAD_RIGHT 1 +#define PAD_ZERO 2 + +static int prints(char **out, const char *string, int width, int pad) +{ + register int pc = 0, padchar = ' '; + + if (width > 0) { + register int len = 0; + register const char *ptr; + for (ptr = string; *ptr; ++ptr) ++len; + if (len >= width) width = 0; + else width -= len; + if (pad & PAD_ZERO) padchar = '0'; + } + if (!(pad & PAD_RIGHT)) { + for ( ; width > 0; --width) { + printchar (out, padchar); + ++pc; + } + } + for ( ; *string ; ++string) { + printchar (out, *string); + ++pc; + } + for ( ; width > 0; --width) { + printchar (out, padchar); + ++pc; + } + + return pc; +} + +/* the following should be enough for 32 bit int */ +#define PRINT_BUF_LEN 12 + +static int printi(char **out, int i, int b, int sg, int width, int pad, int letbase) +{ + char print_buf[PRINT_BUF_LEN]; + register char *s; + register int t, neg = 0, pc = 0; + register unsigned int u = i; + + if (i == 0) { + print_buf[0] = '0'; + print_buf[1] = '\0'; + return prints (out, print_buf, width, pad); + } + + if (sg && b == 10 && i < 0) { + neg = 1; + u = -i; + } + + s = print_buf + PRINT_BUF_LEN-1; + *s = '\0'; + + while (u) { + t = u % b; + if( t >= 10 ) + t += letbase - '0' - 10; + *--s = t + '0'; + u /= b; + } + + if (neg) { + if( width && (pad & PAD_ZERO) ) { + printchar (out, '-'); + ++pc; + --width; + } + else { + *--s = '-'; + } + } + + return pc + prints (out, s, width, pad); +} + +static int print( char **out, const char *format, va_list args ) +{ + register int width, pad; + register int pc = 0; + char scr[2]; + + for (; *format != 0; ++format) { + if (*format == '%') { + ++format; + width = pad = 0; + if (*format == '\0') break; + if (*format == '%') goto out; + if (*format == '-') { + ++format; + pad = PAD_RIGHT; + } + while (*format == '0') { + ++format; + pad |= PAD_ZERO; + } + for ( ; *format >= '0' && *format <= '9'; ++format) { + width *= 10; + width += *format - '0'; + } + if( *format == 's' ) { + register char *s = (char *)va_arg( args, int ); + pc += prints (out, s?s:"(null)", width, pad); + continue; + } + if( *format == 'd' ) { + pc += printi (out, va_arg( args, int ), 10, 1, width, pad, 'a'); + continue; + } + if( *format == 'x' ) { + pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'a'); + continue; + } + if( *format == 'X' ) { + pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'A'); + continue; + } + if( *format == 'u' ) { + pc += printi (out, va_arg( args, int ), 10, 0, width, pad, 'a'); + continue; + } + if( *format == 'c' ) { + /* char are converted to int then pushed on the stack */ + scr[0] = (char)va_arg( args, int ); + scr[1] = '\0'; + pc += prints (out, scr, width, pad); + continue; + } + } + else { + out: + printchar (out, *format); + ++pc; + } + } + if (out) **out = '\0'; + va_end( args ); + return pc; +} + +int printf(const char *format, ...) +{ + va_list args; + + va_start( args, format ); + return print( 0, format, args ); +} + +int sprintf(char *out, const char *format, ...) +{ + va_list args; + + va_start( args, format ); + return print( &out, format, args ); +} + + +int snprintf( char *buf, unsigned int count, const char *format, ... ) +{ + va_list args; + + ( void ) count; + + va_start( args, format ); + return print( &buf, format, args ); +} + + +#ifdef TEST_PRINTF +int main(void) +{ + char *ptr = "Hello world!"; + char *np = 0; + int i = 5; + unsigned int bs = sizeof(int)*8; + int mi; + char buf[80]; + + mi = (1 << (bs-1)) + 1; + printf("%s\n", ptr); + printf("printf test\n"); + printf("%s is null pointer\n", np); + printf("%d = 5\n", i); + printf("%d = - max int\n", mi); + printf("char %c = 'a'\n", 'a'); + printf("hex %x = ff\n", 0xff); + printf("hex %02x = 00\n", 0); + printf("signed %d = unsigned %u = hex %x\n", -3, -3, -3); + printf("%d %s(s)%", 0, "message"); + printf("\n"); + printf("%d %s(s) with %%\n", 0, "message"); + sprintf(buf, "justif: \"%-10s\"\n", "left"); printf("%s", buf); + sprintf(buf, "justif: \"%10s\"\n", "right"); printf("%s", buf); + sprintf(buf, " 3: %04d zero padded\n", 3); printf("%s", buf); + sprintf(buf, " 3: %-4d left justif.\n", 3); printf("%s", buf); + sprintf(buf, " 3: %4d right justif.\n", 3); printf("%s", buf); + sprintf(buf, "-3: %04d zero padded\n", -3); printf("%s", buf); + sprintf(buf, "-3: %-4d left justif.\n", -3); printf("%s", buf); + sprintf(buf, "-3: %4d right justif.\n", -3); printf("%s", buf); + + return 0; +} + +/* + * if you compile this file with + * gcc -Wall $(YOUR_C_OPTIONS) -DTEST_PRINTF -c printf.c + * you will get a normal warning: + * printf.c:214: warning: spurious trailing `%' in format + * this line is testing an invalid % at the end of the format string. + * + * this should display (on 32bit int machine) : + * + * Hello world! + * printf test + * (null) is null pointer + * 5 = 5 + * -2147483647 = - max int + * char a = 'a' + * hex ff = ff + * hex 00 = 00 + * signed -3 = unsigned 4294967293 = hex fffffffd + * 0 message(s) + * 0 message(s) with % + * justif: "left " + * justif: " right" + * 3: 0003 zero padded + * 3: 3 left justif. + * 3: 3 right justif. + * -3: -003 zero padded + * -3: -3 left justif. + * -3: -3 right justif. + */ + +#endif + + diff --git a/20080212/Demo/CORTEX_STM32F103_Primer_GCC/timertest.c b/20080212/Demo/CORTEX_STM32F103_Primer_GCC/timertest.c new file mode 100644 index 000000000..798db39db --- /dev/null +++ b/20080212/Demo/CORTEX_STM32F103_Primer_GCC/timertest.c @@ -0,0 +1,176 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* High speed timer test as described in main.c. */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* Library includes. */ +#include "stm32f10x_lib.h" +#include "stm32f10x_tim.h" +#include "stm32f10x_map.h" + +/* The set frequency of the interrupt. Deviations from this are measured as +the jitter. */ +#define timerINTERRUPT_FREQUENCY ( ( unsigned portSHORT ) 20000 ) + +/* The expected time between each of the timer interrupts - if the jitter was +zero. */ +#define timerEXPECTED_DIFFERENCE_VALUE ( configCPU_CLOCK_HZ / timerINTERRUPT_FREQUENCY ) + +/* The highest available interrupt priority. */ +#define timerHIGHEST_PRIORITY ( 0 ) + +/* Misc defines. */ +#define timerMAX_32BIT_VALUE ( 0xffffffffUL ) +#define timerTIMER_1_COUNT_VALUE ( * ( ( unsigned long * ) ( TIMER1_BASE + 0x48 ) ) ) + +/* The number of interrupts to pass before we start looking at the jitter. */ +#define timerSETTLE_TIME 5 + +/*-----------------------------------------------------------*/ + +/* + * Configures the two timers used to perform the test. + */ +void vSetupTimerTest( void ); + +/* Interrupt handler in which the jitter is measured. */ +void vTimer2IntHandler( void ); + +/* Stores the value of the maximum recorded jitter between interrupts. */ +volatile unsigned portSHORT usMaxJitter = 0; + +/*-----------------------------------------------------------*/ + +void vSetupTimerTest( void ) +{ +unsigned long ulFrequency; +TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; +NVIC_InitTypeDef NVIC_InitStructure; + + + /* Enable timer clocks */ + RCC_APB1PeriphClockCmd( RCC_APB1Periph_TIM2, ENABLE ); + RCC_APB1PeriphClockCmd( RCC_APB1Periph_TIM3, ENABLE ); + + /* Initialise data. */ + TIM_DeInit( TIM2 ); + TIM_DeInit( TIM3 ); + TIM_TimeBaseStructInit( &TIM_TimeBaseStructure ); + + /* Time base configuration for timer 2 - which generates the interrupts. */ + ulFrequency = configCPU_CLOCK_HZ / timerINTERRUPT_FREQUENCY; + TIM_TimeBaseStructure.TIM_Period = ( unsigned portSHORT ) ( ulFrequency & 0xffffUL ); + TIM_TimeBaseStructure.TIM_Prescaler = 0x0; + TIM_TimeBaseStructure.TIM_ClockDivision = 0x0; + TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseInit( TIM2, &TIM_TimeBaseStructure ); + TIM_ARRPreloadConfig( TIM2, ENABLE ); + + + /* Configuration for timer 3 which is used as a high resolution time + measurement. */ + TIM_TimeBaseStructure.TIM_Period = ( unsigned portSHORT ) 0xffff; + TIM_TimeBaseInit( TIM3, &TIM_TimeBaseStructure ); + TIM_ARRPreloadConfig( TIM3, ENABLE ); + + /* Enable TIM2 IT. TIM3 does not generate an interrupt. */ + NVIC_InitStructure.NVIC_IRQChannel = TIM2_IRQChannel; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = timerHIGHEST_PRIORITY; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init( &NVIC_InitStructure ); + TIM_ITConfig( TIM2, TIM_IT_Update, ENABLE ); + + /* Finally, enable both timers. */ + TIM_Cmd( TIM2, ENABLE ); + TIM_Cmd( TIM3, ENABLE ); +} +/*-----------------------------------------------------------*/ + +void vTimer2IntHandler( void ) +{ +static unsigned portSHORT usLastCount = 0, usSettleCount = 0, usMaxDifference = 0; +unsigned portSHORT usThisCount, usDifference; + + /* Capture the free running timer 3 value as we enter the interrupt. */ + usThisCount = TIM3->CNT; + + if( usSettleCount >= timerSETTLE_TIME ) + { + /* What is the difference between the timer value in this interrupt + and the value from the last interrupt. */ + usDifference = usThisCount - usLastCount; + + /* Store the difference in the timer values if it is larger than the + currently stored largest value. The difference over and above the + expected difference will give the 'jitter' in the processing of these + interrupts. */ + if( usDifference > usMaxDifference ) + { + usMaxDifference = usDifference; + usMaxJitter = usMaxDifference - timerEXPECTED_DIFFERENCE_VALUE; + } + } + else + { + /* Don't bother storing any values for the first couple of + interrupts. */ + usSettleCount++; + } + + /* Remember what the timer value was this time through, so we can calculate + the difference the next time through. */ + usLastCount = usThisCount; + + TIM_ClearITPendingBit( TIM2, TIM_IT_Update ); +} + + + + + + + + diff --git a/20080212/Demo/Common/Full/BlockQ.c b/20080212/Demo/Common/Full/BlockQ.c new file mode 100644 index 000000000..939371794 --- /dev/null +++ b/20080212/Demo/Common/Full/BlockQ.c @@ -0,0 +1,323 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/** + * Creates six tasks that operate on three queues as follows: + * + * The first two tasks send and receive an incrementing number to/from a queue. + * One task acts as a producer and the other as the consumer. The consumer is a + * higher priority than the producer and is set to block on queue reads. The queue + * only has space for one item - as soon as the producer posts a message on the + * queue the consumer will unblock, pre-empt the producer, and remove the item. + * + * The second two tasks work the other way around. Again the queue used only has + * enough space for one item. This time the consumer has a lower priority than the + * producer. The producer will try to post on the queue blocking when the queue is + * full. When the consumer wakes it will remove the item from the queue, causing + * the producer to unblock, pre-empt the consumer, and immediately re-fill the + * queue. + * + * The last two tasks use the same queue producer and consumer functions. This time the queue has + * enough space for lots of items and the tasks operate at the same priority. The + * producer will execute, placing items into the queue. The consumer will start + * executing when either the queue becomes full (causing the producer to block) or + * a context switch occurs (tasks of the same priority will time slice). + * + * \page BlockQC blockQ.c + * \ingroup DemoFiles + *
+ */ + +/* +Changes from V1.00: + + + Reversed the priority and block times of the second two demo tasks so + they operate as per the description above. + +Changes from V2.0.0 + + + Delay periods are now specified using variables and constants of + portTickType rather than unsigned portLONG. + +Changes from V4.0.2 + + + The second set of tasks were created the wrong way around. This has been + corrected. +*/ + + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* Demo program include files. */ +#include "BlockQ.h" +#include "print.h" + +#define blckqSTACK_SIZE ( ( unsigned portSHORT ) configMINIMAL_STACK_SIZE ) +#define blckqNUM_TASK_SETS ( 3 ) + +/* Structure used to pass parameters to the blocking queue tasks. */ +typedef struct BLOCKING_QUEUE_PARAMETERS +{ + xQueueHandle xQueue; /*< The queue to be used by the task. */ + portTickType xBlockTime; /*< The block time to use on queue reads/writes. */ + volatile portSHORT *psCheckVariable; /*< Incremented on each successful cycle to check the task is still running. */ +} xBlockingQueueParameters; + +/* Task function that creates an incrementing number and posts it on a queue. */ +static void vBlockingQueueProducer( void *pvParameters ); + +/* Task function that removes the incrementing number from a queue and checks that +it is the expected number. */ +static void vBlockingQueueConsumer( void *pvParameters ); + +/* Variables which are incremented each time an item is removed from a queue, and +found to be the expected value. +These are used to check that the tasks are still running. */ +static volatile portSHORT sBlockingConsumerCount[ blckqNUM_TASK_SETS ] = { ( portSHORT ) 0, ( portSHORT ) 0, ( portSHORT ) 0 }; + +/* Variable which are incremented each time an item is posted on a queue. These +are used to check that the tasks are still running. */ +static volatile portSHORT sBlockingProducerCount[ blckqNUM_TASK_SETS ] = { ( portSHORT ) 0, ( portSHORT ) 0, ( portSHORT ) 0 }; + +/*-----------------------------------------------------------*/ + +void vStartBlockingQueueTasks( unsigned portBASE_TYPE uxPriority ) +{ +xBlockingQueueParameters *pxQueueParameters1, *pxQueueParameters2; +xBlockingQueueParameters *pxQueueParameters3, *pxQueueParameters4; +xBlockingQueueParameters *pxQueueParameters5, *pxQueueParameters6; +const unsigned portBASE_TYPE uxQueueSize1 = 1, uxQueueSize5 = 5; +const portTickType xBlockTime = ( portTickType ) 1000 / portTICK_RATE_MS; +const portTickType xDontBlock = ( portTickType ) 0; + + /* Create the first two tasks as described at the top of the file. */ + + /* First create the structure used to pass parameters to the consumer tasks. */ + pxQueueParameters1 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + + /* Create the queue used by the first two tasks to pass the incrementing number. + Pass a pointer to the queue in the parameter structure. */ + pxQueueParameters1->xQueue = xQueueCreate( uxQueueSize1, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) ); + + /* The consumer is created first so gets a block time as described above. */ + pxQueueParameters1->xBlockTime = xBlockTime; + + /* Pass in the variable that this task is going to increment so we can check it + is still running. */ + pxQueueParameters1->psCheckVariable = &( sBlockingConsumerCount[ 0 ] ); + + /* Create the structure used to pass parameters to the producer task. */ + pxQueueParameters2 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + + /* Pass the queue to this task also, using the parameter structure. */ + pxQueueParameters2->xQueue = pxQueueParameters1->xQueue; + + /* The producer is not going to block - as soon as it posts the consumer will + wake and remove the item so the producer should always have room to post. */ + pxQueueParameters2->xBlockTime = xDontBlock; + + /* Pass in the variable that this task is going to increment so we can check + it is still running. */ + pxQueueParameters2->psCheckVariable = &( sBlockingProducerCount[ 0 ] ); + + + /* Note the producer has a lower priority than the consumer when the tasks are + spawned. */ + xTaskCreate( vBlockingQueueConsumer, "QConsB1", blckqSTACK_SIZE, ( void * ) pxQueueParameters1, uxPriority, NULL ); + xTaskCreate( vBlockingQueueProducer, "QProdB2", blckqSTACK_SIZE, ( void * ) pxQueueParameters2, tskIDLE_PRIORITY, NULL ); + + + + /* Create the second two tasks as described at the top of the file. This uses + the same mechanism but reverses the task priorities. */ + + pxQueueParameters3 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + pxQueueParameters3->xQueue = xQueueCreate( uxQueueSize1, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) ); + pxQueueParameters3->xBlockTime = xDontBlock; + pxQueueParameters3->psCheckVariable = &( sBlockingProducerCount[ 1 ] ); + + pxQueueParameters4 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + pxQueueParameters4->xQueue = pxQueueParameters3->xQueue; + pxQueueParameters4->xBlockTime = xBlockTime; + pxQueueParameters4->psCheckVariable = &( sBlockingConsumerCount[ 1 ] ); + + xTaskCreate( vBlockingQueueProducer, "QProdB3", blckqSTACK_SIZE, ( void * ) pxQueueParameters3, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vBlockingQueueConsumer, "QConsB4", blckqSTACK_SIZE, ( void * ) pxQueueParameters4, uxPriority, NULL ); + + + + /* Create the last two tasks as described above. The mechanism is again just + the same. This time both parameter structures are given a block time. */ + pxQueueParameters5 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + pxQueueParameters5->xQueue = xQueueCreate( uxQueueSize5, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) ); + pxQueueParameters5->xBlockTime = xBlockTime; + pxQueueParameters5->psCheckVariable = &( sBlockingProducerCount[ 2 ] ); + + pxQueueParameters6 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + pxQueueParameters6->xQueue = pxQueueParameters5->xQueue; + pxQueueParameters6->xBlockTime = xBlockTime; + pxQueueParameters6->psCheckVariable = &( sBlockingConsumerCount[ 2 ] ); + + xTaskCreate( vBlockingQueueProducer, "QProdB5", blckqSTACK_SIZE, ( void * ) pxQueueParameters5, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vBlockingQueueConsumer, "QConsB6", blckqSTACK_SIZE, ( void * ) pxQueueParameters6, tskIDLE_PRIORITY, NULL ); +} +/*-----------------------------------------------------------*/ + +static void vBlockingQueueProducer( void *pvParameters ) +{ +unsigned portSHORT usValue = 0; +xBlockingQueueParameters *pxQueueParameters; +const portCHAR * const pcTaskStartMsg = "Blocking queue producer started.\r\n"; +const portCHAR * const pcTaskErrorMsg = "Could not post on blocking queue\r\n"; +portSHORT sErrorEverOccurred = pdFALSE; + + pxQueueParameters = ( xBlockingQueueParameters * ) pvParameters; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + for( ;; ) + { + if( xQueueSendToBack( pxQueueParameters->xQueue, ( void * ) &usValue, pxQueueParameters->xBlockTime ) != pdPASS ) + { + vPrintDisplayMessage( &pcTaskErrorMsg ); + sErrorEverOccurred = pdTRUE; + } + else + { + /* We have successfully posted a message, so increment the variable + used to check we are still running. */ + if( sErrorEverOccurred == pdFALSE ) + { + ( *pxQueueParameters->psCheckVariable )++; + } + + /* Increment the variable we are going to post next time round. The + consumer will expect the numbers to follow in numerical order. */ + ++usValue; + } + } +} +/*-----------------------------------------------------------*/ + +static void vBlockingQueueConsumer( void *pvParameters ) +{ +unsigned portSHORT usData, usExpectedValue = 0; +xBlockingQueueParameters *pxQueueParameters; +const portCHAR * const pcTaskStartMsg = "Blocking queue consumer started.\r\n"; +const portCHAR * const pcTaskErrorMsg = "Incorrect value received on blocking queue.\r\n"; +portSHORT sErrorEverOccurred = pdFALSE; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + pxQueueParameters = ( xBlockingQueueParameters * ) pvParameters; + + for( ;; ) + { + if( xQueueReceive( pxQueueParameters->xQueue, &usData, pxQueueParameters->xBlockTime ) == pdPASS ) + { + if( usData != usExpectedValue ) + { + vPrintDisplayMessage( &pcTaskErrorMsg ); + + /* Catch-up. */ + usExpectedValue = usData; + + sErrorEverOccurred = pdTRUE; + } + else + { + /* We have successfully received a message, so increment the + variable used to check we are still running. */ + if( sErrorEverOccurred == pdFALSE ) + { + ( *pxQueueParameters->psCheckVariable )++; + } + + /* Increment the value we expect to remove from the queue next time + round. */ + ++usExpectedValue; + } + } + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +portBASE_TYPE xAreBlockingQueuesStillRunning( void ) +{ +static portSHORT sLastBlockingConsumerCount[ blckqNUM_TASK_SETS ] = { ( portSHORT ) 0, ( portSHORT ) 0, ( portSHORT ) 0 }; +static portSHORT sLastBlockingProducerCount[ blckqNUM_TASK_SETS ] = { ( portSHORT ) 0, ( portSHORT ) 0, ( portSHORT ) 0 }; +portBASE_TYPE xReturn = pdPASS, xTasks; + + /* Not too worried about mutual exclusion on these variables as they are 16 + bits and we are only reading them. We also only care to see if they have + changed or not. + + Loop through each check variable and return pdFALSE if any are found not + to have changed since the last call. */ + + for( xTasks = 0; xTasks < blckqNUM_TASK_SETS; xTasks++ ) + { + if( sBlockingConsumerCount[ xTasks ] == sLastBlockingConsumerCount[ xTasks ] ) + { + xReturn = pdFALSE; + } + sLastBlockingConsumerCount[ xTasks ] = sBlockingConsumerCount[ xTasks ]; + + + if( sBlockingProducerCount[ xTasks ] == sLastBlockingProducerCount[ xTasks ] ) + { + xReturn = pdFALSE; + } + sLastBlockingProducerCount[ xTasks ] = sBlockingProducerCount[ xTasks ]; + } + + return xReturn; +} + diff --git a/20080212/Demo/Common/Full/PollQ.c b/20080212/Demo/Common/Full/PollQ.c new file mode 100644 index 000000000..98e042e9b --- /dev/null +++ b/20080212/Demo/Common/Full/PollQ.c @@ -0,0 +1,235 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +/** + * This is a very simple queue test. See the BlockQ. c documentation for a more + * comprehensive version. + * + * Creates two tasks that communicate over a single queue. One task acts as a + * producer, the other a consumer. + * + * The producer loops for three iteration, posting an incrementing number onto the + * queue each cycle. It then delays for a fixed period before doing exactly the + * same again. + * + * The consumer loops emptying the queue. Each item removed from the queue is + * checked to ensure it contains the expected value. When the queue is empty it + * blocks for a fixed period, then does the same again. + * + * All queue access is performed without blocking. The consumer completely empties + * the queue each time it runs so the producer should never find the queue full. + * + * An error is flagged if the consumer obtains an unexpected value or the producer + * find the queue is full. + * + * \page PollQC pollQ.c + * \ingroup DemoFiles + *
+ */ + +/* +Changes from V2.0.0 + + + Delay periods are now specified using variables and constants of + portTickType rather than unsigned portLONG. +*/ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "print.h" + +/* Demo program include files. */ +#include "PollQ.h" + +#define pollqSTACK_SIZE ( ( unsigned portSHORT ) configMINIMAL_STACK_SIZE ) + +/* The task that posts the incrementing number onto the queue. */ +static void vPolledQueueProducer( void *pvParameters ); + +/* The task that empties the queue. */ +static void vPolledQueueConsumer( void *pvParameters ); + +/* Variables that are used to check that the tasks are still running with no errors. */ +static volatile portSHORT sPollingConsumerCount = 0, sPollingProducerCount = 0; +/*-----------------------------------------------------------*/ + +void vStartPolledQueueTasks( unsigned portBASE_TYPE uxPriority ) +{ +static xQueueHandle xPolledQueue; +const unsigned portBASE_TYPE uxQueueSize = 10; + + /* Create the queue used by the producer and consumer. */ + xPolledQueue = xQueueCreate( uxQueueSize, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) ); + + /* Spawn the producer and consumer. */ + xTaskCreate( vPolledQueueConsumer, "QConsNB", pollqSTACK_SIZE, ( void * ) &xPolledQueue, uxPriority, NULL ); + xTaskCreate( vPolledQueueProducer, "QProdNB", pollqSTACK_SIZE, ( void * ) &xPolledQueue, uxPriority, NULL ); +} +/*-----------------------------------------------------------*/ + +static void vPolledQueueProducer( void *pvParameters ) +{ +unsigned portSHORT usValue = 0, usLoop; +xQueueHandle *pxQueue; +const portTickType xDelay = ( portTickType ) 200 / portTICK_RATE_MS; +const unsigned portSHORT usNumToProduce = 3; +const portCHAR * const pcTaskStartMsg = "Polled queue producer started.\r\n"; +const portCHAR * const pcTaskErrorMsg = "Could not post on polled queue.\r\n"; +portSHORT sError = pdFALSE; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + /* The queue being used is passed in as the parameter. */ + pxQueue = ( xQueueHandle * ) pvParameters; + + for( ;; ) + { + for( usLoop = 0; usLoop < usNumToProduce; ++usLoop ) + { + /* Send an incrementing number on the queue without blocking. */ + if( xQueueSendToBack( *pxQueue, ( void * ) &usValue, ( portTickType ) 0 ) != pdPASS ) + { + /* We should never find the queue full - this is an error. */ + vPrintDisplayMessage( &pcTaskErrorMsg ); + sError = pdTRUE; + } + else + { + if( sError == pdFALSE ) + { + /* If an error has ever been recorded we stop incrementing the + check variable. */ + ++sPollingProducerCount; + } + + /* Update the value we are going to post next time around. */ + ++usValue; + } + } + + /* Wait before we start posting again to ensure the consumer runs and + empties the queue. */ + vTaskDelay( xDelay ); + } +} +/*-----------------------------------------------------------*/ + +static void vPolledQueueConsumer( void *pvParameters ) +{ +unsigned portSHORT usData, usExpectedValue = 0; +xQueueHandle *pxQueue; +const portTickType xDelay = ( portTickType ) 200 / portTICK_RATE_MS; +const portCHAR * const pcTaskStartMsg = "Polled queue consumer started.\r\n"; +const portCHAR * const pcTaskErrorMsg = "Incorrect value received on polled queue.\r\n"; +portSHORT sError = pdFALSE; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + /* The queue being used is passed in as the parameter. */ + pxQueue = ( xQueueHandle * ) pvParameters; + + for( ;; ) + { + /* Loop until the queue is empty. */ + while( uxQueueMessagesWaiting( *pxQueue ) ) + { + if( xQueueReceive( *pxQueue, &usData, ( portTickType ) 0 ) == pdPASS ) + { + if( usData != usExpectedValue ) + { + /* This is not what we expected to receive so an error has + occurred. */ + vPrintDisplayMessage( &pcTaskErrorMsg ); + sError = pdTRUE; + /* Catch-up to the value we received so our next expected value + should again be correct. */ + usExpectedValue = usData; + } + else + { + if( sError == pdFALSE ) + { + /* Only increment the check variable if no errors have + occurred. */ + ++sPollingConsumerCount; + } + } + ++usExpectedValue; + } + } + + /* Now the queue is empty we block, allowing the producer to place more + items in the queue. */ + vTaskDelay( xDelay ); + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running with no errors. */ +portBASE_TYPE xArePollingQueuesStillRunning( void ) +{ +static portSHORT sLastPollingConsumerCount = 0, sLastPollingProducerCount = 0; +portBASE_TYPE xReturn; + + if( ( sLastPollingConsumerCount == sPollingConsumerCount ) || + ( sLastPollingProducerCount == sPollingProducerCount ) + ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + sLastPollingConsumerCount = sPollingConsumerCount; + sLastPollingProducerCount = sPollingProducerCount; + + return xReturn; +} diff --git a/20080212/Demo/Common/Full/comtest.c b/20080212/Demo/Common/Full/comtest.c new file mode 100644 index 000000000..7795daab9 --- /dev/null +++ b/20080212/Demo/Common/Full/comtest.c @@ -0,0 +1,361 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/** + * Creates two tasks that operate on an interrupt driven serial port. A loopback + * connector should be used so that everything that is transmitted is also received. + * The serial port does not use any flow control. On a standard 9way 'D' connector + * pins two and three should be connected together. + * + * The first task repeatedly sends a string to a queue, character at a time. The + * serial port interrupt will empty the queue and transmit the characters. The + * task blocks for a pseudo random period before resending the string. + * + * The second task blocks on a queue waiting for a character to be received. + * Characters received by the serial port interrupt routine are posted onto the + * queue - unblocking the task making it ready to execute. If this is then the + * highest priority task ready to run it will run immediately - with a context + * switch occurring at the end of the interrupt service routine. The task + * receiving characters is spawned with a higher priority than the task + * transmitting the characters. + * + * With the loop back connector in place, one task will transmit a string and the + * other will immediately receive it. The receiving task knows the string it + * expects to receive so can detect an error. + * + * This also creates a third task. This is used to test semaphore usage from an + * ISR and does nothing interesting. + * + * \page ComTestC comtest.c + * \ingroup DemoFiles + *
+ */ + +/* +Changes from V1.00: + + + The priority of the Rx task has been lowered. Received characters are + now processed (read from the queue) at the idle priority, allowing low + priority tasks to run evenly at times of a high communications overhead. + +Changes from V1.01: + + + The Tx task now waits a pseudo random time between transissions. + Previously a fixed period was used but this was not such a good test as + interrupts fired at regular intervals. + +Changes From V1.2.0: + + + Use vSerialPutString() instead of single character puts. + + Only stop the check variable incrementing after two consecutive errors. + +Changed from V1.2.5 + + + Made the Rx task 2 priorities higher than the Tx task. Previously it was + only 1. This is done to tie in better with the other demo application + tasks. + +Changes from V2.0.0 + + + Delay periods are now specified using variables and constants of + portTickType rather than unsigned portLONG. + + Slight modification to task priorities. + +*/ + + +/* Scheduler include files. */ +#include +#include +#include "FreeRTOS.h" +#include "task.h" + +/* Demo program include files. */ +#include "serial.h" +#include "comtest.h" +#include "print.h" + +/* The Tx task will transmit the sequence of characters at a pseudo random +interval. This is the maximum and minimum block time between sends. */ +#define comTX_MAX_BLOCK_TIME ( ( portTickType ) 0x15e ) +#define comTX_MIN_BLOCK_TIME ( ( portTickType ) 0xc8 ) + +#define comMAX_CONSECUTIVE_ERRORS ( 2 ) + +#define comSTACK_SIZE ( ( unsigned portSHORT ) 256 ) + +#define comRX_RELATIVE_PRIORITY ( 1 ) + +/* Handle to the com port used by both tasks. */ +static xComPortHandle xPort; + +/* The transmit function as described at the top of the file. */ +static void vComTxTask( void *pvParameters ); + +/* The receive function as described at the top of the file. */ +static void vComRxTask( void *pvParameters ); + +/* The semaphore test function as described at the top of the file. */ +static void vSemTestTask( void * pvParameters ); + +/* The string that is repeatedly transmitted. */ +const portCHAR * const pcMessageToExchange = "Send this message over and over again to check communications interrupts. " + "0123456789abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ\r\n"; + +/* Variables that are incremented on each cycle of each task. These are used to +check that both tasks are still executing. */ +volatile portSHORT sTxCount = 0, sRxCount = 0, sSemCount = 0; + +/* The handle to the semaphore test task. */ +static xTaskHandle xSemTestTaskHandle = NULL; + +/*-----------------------------------------------------------*/ + +void vStartComTestTasks( unsigned portBASE_TYPE uxPriority, eCOMPort ePort, eBaud eBaudRate ) +{ +const unsigned portBASE_TYPE uxBufferLength = 255; + + /* Initialise the com port then spawn both tasks. */ + xPort = xSerialPortInit( ePort, eBaudRate, serNO_PARITY, serBITS_8, serSTOP_1, uxBufferLength ); + xTaskCreate( vComTxTask, "COMTx", comSTACK_SIZE, NULL, uxPriority, NULL ); + xTaskCreate( vComRxTask, "COMRx", comSTACK_SIZE, NULL, uxPriority + comRX_RELATIVE_PRIORITY, NULL ); + xTaskCreate( vSemTestTask, "ISRSem", comSTACK_SIZE, NULL, tskIDLE_PRIORITY, &xSemTestTaskHandle ); +} +/*-----------------------------------------------------------*/ + +static void vComTxTask( void *pvParameters ) +{ +const portCHAR * const pcTaskStartMsg = "COM Tx task started.\r\n"; +portTickType xTimeToWait; + + /* Stop warnings. */ + ( void ) pvParameters; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + for( ;; ) + { + /* Send the string to the serial port. */ + vSerialPutString( xPort, pcMessageToExchange, strlen( pcMessageToExchange ) ); + + /* We have posted all the characters in the string - increment the variable + used to check that this task is still running, then wait before re-sending + the string. */ + sTxCount++; + + xTimeToWait = xTaskGetTickCount(); + + /* Make sure we don't wait too long... */ + xTimeToWait %= comTX_MAX_BLOCK_TIME; + + /* ...but we do want to wait. */ + if( xTimeToWait < comTX_MIN_BLOCK_TIME ) + { + xTimeToWait = comTX_MIN_BLOCK_TIME; + } + + vTaskDelay( xTimeToWait ); + } +} /*lint !e715 !e818 pvParameters is required for a task function even if it is not referenced. */ +/*-----------------------------------------------------------*/ + +static void vComRxTask( void *pvParameters ) +{ +const portCHAR * const pcTaskStartMsg = "COM Rx task started.\r\n"; +const portCHAR * const pcTaskErrorMsg = "COM read error\r\n"; +const portCHAR * const pcTaskRestartMsg = "COM resynced\r\n"; +const portCHAR * const pcTaskTimeoutMsg = "COM Rx timed out\r\n"; +const portTickType xBlockTime = ( portTickType ) 0xffff / portTICK_RATE_MS; +const portCHAR *pcExpectedChar; +portBASE_TYPE xGotChar; +portCHAR cRxedChar; +portSHORT sResyncRequired, sConsecutiveErrors, sLatchedError; + + /* Stop warnings. */ + ( void ) pvParameters; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + /* The first expected character is the first character in the string. */ + pcExpectedChar = pcMessageToExchange; + sResyncRequired = pdFALSE; + sConsecutiveErrors = 0; + sLatchedError = pdFALSE; + + for( ;; ) + { + /* Receive a message from the com port interrupt routine. If a message is + not yet available the call will block the task. */ + xGotChar = xSerialGetChar( xPort, &cRxedChar, xBlockTime ); + if( xGotChar == pdTRUE ) + { + if( sResyncRequired == pdTRUE ) + { + /* We got out of sequence and are waiting for the start of the next + transmission of the string. */ + if( cRxedChar == '\n' ) + { + /* This is the end of the message so we can start again - with + the first character in the string being the next thing we expect + to receive. */ + pcExpectedChar = pcMessageToExchange; + sResyncRequired = pdFALSE; + + /* Queue a message for printing to say that we are going to try + again. */ + vPrintDisplayMessage( &pcTaskRestartMsg ); + + /* Stop incrementing the check variable, if consecutive errors occur. */ + sConsecutiveErrors++; + if( sConsecutiveErrors >= comMAX_CONSECUTIVE_ERRORS ) + { + sLatchedError = pdTRUE; + } + } + } + else + { + /* We have received a character, but is it the expected character? */ + if( cRxedChar != *pcExpectedChar ) + { + /* This was not the expected character so post a message for + printing to say that an error has occurred. We will then wait + to resynchronise. */ + vPrintDisplayMessage( &pcTaskErrorMsg ); + sResyncRequired = pdTRUE; + } + else + { + /* This was the expected character so next time we will expect + the next character in the string. Wrap back to the beginning + of the string when the null terminator has been reached. */ + pcExpectedChar++; + if( *pcExpectedChar == '\0' ) + { + pcExpectedChar = pcMessageToExchange; + + /* We have got through the entire string without error. */ + sConsecutiveErrors = 0; + } + } + } + + /* Increment the count that is used to check that this task is still + running. This is only done if an error has never occurred. */ + if( sLatchedError == pdFALSE ) + { + sRxCount++; + } + } + else + { + vPrintDisplayMessage( &pcTaskTimeoutMsg ); + } + } +} /*lint !e715 !e818 pvParameters is required for a task function even if it is not referenced. */ +/*-----------------------------------------------------------*/ + +static void vSemTestTask( void * pvParameters ) +{ +const portCHAR * const pcTaskStartMsg = "ISR Semaphore test started.\r\n"; +portBASE_TYPE xError = pdFALSE; + + /* Stop warnings. */ + ( void ) pvParameters; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + for( ;; ) + { + if( xSerialWaitForSemaphore( xPort ) ) + { + if( xError == pdFALSE ) + { + sSemCount++; + } + } + else + { + xError = pdTRUE; + } + } +} /*lint !e715 !e830 !e818 pvParameters not used but function prototype must be standard for task function. */ +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +portBASE_TYPE xAreComTestTasksStillRunning( void ) +{ +static portSHORT sLastTxCount = 0, sLastRxCount = 0, sLastSemCount = 0; +portBASE_TYPE xReturn; + + /* Not too worried about mutual exclusion on these variables as they are 16 + bits and we are only reading them. We also only care to see if they have + changed or not. */ + + if( ( sTxCount == sLastTxCount ) || ( sRxCount == sLastRxCount ) || ( sSemCount == sLastSemCount ) ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + sLastTxCount = sTxCount; + sLastRxCount = sRxCount; + sLastSemCount = sSemCount; + + return xReturn; +} +/*-----------------------------------------------------------*/ + +void vComTestUnsuspendTask( void ) +{ + /* The task that is suspended on the semaphore will be referenced from the + Suspended list as it is blocking indefinitely. This call just checks that + the kernel correctly detects this and does not attempt to unsuspend the + task. */ + xTaskResumeFromISR( xSemTestTaskHandle ); +} diff --git a/20080212/Demo/Common/Full/death.c b/20080212/Demo/Common/Full/death.c new file mode 100644 index 000000000..c65bc48b3 --- /dev/null +++ b/20080212/Demo/Common/Full/death.c @@ -0,0 +1,218 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/** + * Create a single persistent task which periodically dynamically creates another + * four tasks. The original task is called the creator task, the four tasks it + * creates are called suicidal tasks. + * + * Two of the created suicidal tasks kill one other suicidal task before killing + * themselves - leaving just the original task remaining. + * + * The creator task must be spawned after all of the other demo application tasks + * as it keeps a check on the number of tasks under the scheduler control. The + * number of tasks it expects to see running should never be greater than the + * number of tasks that were in existence when the creator task was spawned, plus + * one set of four suicidal tasks. If this number is exceeded an error is flagged. + * + * \page DeathC death.c + * \ingroup DemoFiles + *
+ */ + +/* +Changes from V2.0.0 + + + Delay periods are now specified using variables and constants of + portTickType rather than unsigned portLONG. +*/ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo program include files. */ +#include "death.h" +#include "print.h" + +#define deathSTACK_SIZE ( ( unsigned portSHORT ) 512 ) + +/* The task originally created which is responsible for periodically dynamically +creating another four tasks. */ +static void vCreateTasks( void *pvParameters ); + +/* The task function of the dynamically created tasks. */ +static void vSuicidalTask( void *pvParameters ); + +/* A variable which is incremented every time the dynamic tasks are created. This +is used to check that the task is still running. */ +static volatile portSHORT sCreationCount = 0; + +/* Used to store the number of tasks that were originally running so the creator +task can tell if any of the suicidal tasks have failed to die. */ +static volatile unsigned portBASE_TYPE uxTasksRunningAtStart = 0; +static const unsigned portBASE_TYPE uxMaxNumberOfExtraTasksRunning = 5; + +/* Used to store a handle to the tasks that should be killed by a suicidal task, +before it kills itself. */ +xTaskHandle xCreatedTask1, xCreatedTask2; + +/*-----------------------------------------------------------*/ + +void vCreateSuicidalTasks( unsigned portBASE_TYPE uxPriority ) +{ +unsigned portBASE_TYPE *puxPriority; + + /* Create the Creator tasks - passing in as a parameter the priority at which + the suicidal tasks should be created. */ + puxPriority = ( unsigned portBASE_TYPE * ) pvPortMalloc( sizeof( unsigned portBASE_TYPE ) ); + *puxPriority = uxPriority; + + xTaskCreate( vCreateTasks, "CREATOR", deathSTACK_SIZE, ( void * ) puxPriority, uxPriority, NULL ); + + /* Record the number of tasks that are running now so we know if any of the + suicidal tasks have failed to be killed. */ + uxTasksRunningAtStart = uxTaskGetNumberOfTasks(); +} +/*-----------------------------------------------------------*/ + +static void vSuicidalTask( void *pvParameters ) +{ +portDOUBLE d1, d2; +xTaskHandle xTaskToKill; +const portTickType xDelay = ( portTickType ) 500 / portTICK_RATE_MS; + + if( pvParameters != NULL ) + { + /* This task is periodically created four times. Tow created tasks are + passed a handle to the other task so it can kill it before killing itself. + The other task is passed in null. */ + xTaskToKill = *( xTaskHandle* )pvParameters; + } + else + { + xTaskToKill = NULL; + } + + for( ;; ) + { + /* Do something random just to use some stack and registers. */ + d1 = 2.4; + d2 = 89.2; + d2 *= d1; + vTaskDelay( xDelay ); + + if( xTaskToKill != NULL ) + { + /* Make sure the other task has a go before we delete it. */ + vTaskDelay( ( portTickType ) 0 ); + /* Kill the other task that was created by vCreateTasks(). */ + vTaskDelete( xTaskToKill ); + /* Kill ourselves. */ + vTaskDelete( NULL ); + } + } +}/*lint !e818 !e550 Function prototype must be as per standard for task functions. */ +/*-----------------------------------------------------------*/ + +static void vCreateTasks( void *pvParameters ) +{ +const portTickType xDelay = ( portTickType ) 1000 / portTICK_RATE_MS; +unsigned portBASE_TYPE uxPriority; +const portCHAR * const pcTaskStartMsg = "Create task started.\r\n"; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + uxPriority = *( unsigned portBASE_TYPE * ) pvParameters; + vPortFree( pvParameters ); + + for( ;; ) + { + /* Just loop round, delaying then creating the four suicidal tasks. */ + vTaskDelay( xDelay ); + + xTaskCreate( vSuicidalTask, "SUICIDE1", deathSTACK_SIZE, NULL, uxPriority, &xCreatedTask1 ); + xTaskCreate( vSuicidalTask, "SUICIDE2", deathSTACK_SIZE, &xCreatedTask1, uxPriority, NULL ); + + xTaskCreate( vSuicidalTask, "SUICIDE1", deathSTACK_SIZE, NULL, uxPriority, &xCreatedTask2 ); + xTaskCreate( vSuicidalTask, "SUICIDE2", deathSTACK_SIZE, &xCreatedTask2, uxPriority, NULL ); + + ++sCreationCount; + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that the creator task is still running and that there +are not any more than four extra tasks. */ +portBASE_TYPE xIsCreateTaskStillRunning( void ) +{ +static portSHORT sLastCreationCount = 0; +portSHORT sReturn = pdTRUE; +unsigned portBASE_TYPE uxTasksRunningNow; + + if( sLastCreationCount == sCreationCount ) + { + sReturn = pdFALSE; + } + + uxTasksRunningNow = uxTaskGetNumberOfTasks(); + + if( uxTasksRunningNow < uxTasksRunningAtStart ) + { + sReturn = pdFALSE; + } + else if( ( uxTasksRunningNow - uxTasksRunningAtStart ) > uxMaxNumberOfExtraTasksRunning ) + { + sReturn = pdFALSE; + } + else + { + /* Everything is okay. */ + } + + return sReturn; +} + + diff --git a/20080212/Demo/Common/Full/dynamic.c b/20080212/Demo/Common/Full/dynamic.c new file mode 100644 index 000000000..6aa2cf26a --- /dev/null +++ b/20080212/Demo/Common/Full/dynamic.c @@ -0,0 +1,593 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/** + * The first test creates three tasks - two counter tasks (one continuous count + * and one limited count) and one controller. A "count" variable is shared + * between all three tasks. The two counter tasks should never be in a "ready" + * state at the same time. The controller task runs at the same priority as + * the continuous count task, and at a lower priority than the limited count + * task. + * + * One counter task loops indefinitely, incrementing the shared count variable + * on each iteration. To ensure it has exclusive access to the variable it + * raises it's priority above that of the controller task before each + * increment, lowering it again to it's original priority before starting the + * next iteration. + * + * The other counter task increments the shared count variable on each + * iteration of it's loop until the count has reached a limit of 0xff - at + * which point it suspends itself. It will not start a new loop until the + * controller task has made it "ready" again by calling vTaskResume (). + * This second counter task operates at a higher priority than controller + * task so does not need to worry about mutual exclusion of the counter + * variable. + * + * The controller task is in two sections. The first section controls and + * monitors the continuous count task. When this section is operational the + * limited count task is suspended. Likewise, the second section controls + * and monitors the limited count task. When this section is operational the + * continuous count task is suspended. + * + * In the first section the controller task first takes a copy of the shared + * count variable. To ensure mutual exclusion on the count variable it + * suspends the continuous count task, resuming it again when the copy has been + * taken. The controller task then sleeps for a fixed period - during which + * the continuous count task will execute and increment the shared variable. + * When the controller task wakes it checks that the continuous count task + * has executed by comparing the copy of the shared variable with its current + * value. This time, to ensure mutual exclusion, the scheduler itself is + * suspended with a call to vTaskSuspendAll (). This is for demonstration + * purposes only and is not a recommended technique due to its inefficiency. + * + * After a fixed number of iterations the controller task suspends the + * continuous count task, and moves on to its second section. + * + * At the start of the second section the shared variable is cleared to zero. + * The limited count task is then woken from it's suspension by a call to + * vTaskResume (). As this counter task operates at a higher priority than + * the controller task the controller task should not run again until the + * shared variable has been counted up to the limited value causing the counter + * task to suspend itself. The next line after vTaskResume () is therefore + * a check on the shared variable to ensure everything is as expected. + * + * + * The second test consists of a couple of very simple tasks that post onto a + * queue while the scheduler is suspended. This test was added to test parts + * of the scheduler not exercised by the first test. + * + * + * The final set of two tasks implements a third test. This simply raises the + * priority of a task while the scheduler is suspended. Again this test was + * added to exercise parts of the code not covered by the first test. + * + * \page Priorities dynamic.c + * \ingroup DemoFiles + *
+ */ + +/* +Changes from V2.0.0 + + + Delay periods are now specified using variables and constants of + portTickType rather than unsigned portLONG. + + Added a second, simple test that uses the functions + vQueueReceiveWhenSuspendedTask() and vQueueSendWhenSuspendedTask(). + +Changes from V3.1.1 + + + Added a third simple test that uses the vTaskPrioritySet() function + while the scheduler is suspended. + + Modified the controller task slightly to test the calling of + vTaskResumeAll() while the scheduler is suspended. +*/ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Demo app include files. */ +#include "dynamic.h" +#include "print.h" + +/* Function that implements the "limited count" task as described above. */ +static void vLimitedIncrementTask( void * pvParameters ); + +/* Function that implements the "continuous count" task as described above. */ +static void vContinuousIncrementTask( void * pvParameters ); + +/* Function that implements the controller task as described above. */ +static void vCounterControlTask( void * pvParameters ); + +/* The simple test functions that check sending and receiving while the +scheduler is suspended. */ +static void vQueueReceiveWhenSuspendedTask( void *pvParameters ); +static void vQueueSendWhenSuspendedTask( void *pvParameters ); + +/* The simple test functions that check raising and lowering of task priorities +while the scheduler is suspended. */ +static void prvChangePriorityWhenSuspendedTask( void *pvParameters ); +static void prvChangePriorityHelperTask( void *pvParameters ); + + +/* Demo task specific constants. */ +#define priSTACK_SIZE ( ( unsigned portSHORT ) configMINIMAL_STACK_SIZE ) +#define priSLEEP_TIME ( ( portTickType ) 50 ) +#define priLOOPS ( 5 ) +#define priMAX_COUNT ( ( unsigned portLONG ) 0xff ) +#define priNO_BLOCK ( ( portTickType ) 0 ) +#define priSUSPENDED_QUEUE_LENGTH ( 1 ) + +/*-----------------------------------------------------------*/ + +/* Handles to the two counter tasks. These could be passed in as parameters +to the controller task to prevent them having to be file scope. */ +static xTaskHandle xContinuousIncrementHandle, xLimitedIncrementHandle, xChangePriorityWhenSuspendedHandle; + +/* The shared counter variable. This is passed in as a parameter to the two +counter variables for demonstration purposes. */ +static unsigned portLONG ulCounter; + +/* Variable used in a similar way by the test that checks the raising and +lowering of task priorities while the scheduler is suspended. */ +static unsigned portLONG ulPrioritySetCounter; + +/* Variables used to check that the tasks are still operating without error. +Each complete iteration of the controller task increments this variable +provided no errors have been found. The variable maintaining the same value +is therefore indication of an error. */ +static unsigned portSHORT usCheckVariable = ( unsigned portSHORT ) 0; +static portBASE_TYPE xSuspendedQueueSendError = pdFALSE; +static portBASE_TYPE xSuspendedQueueReceiveError = pdFALSE; +static portBASE_TYPE xPriorityRaiseWhenSuspendedError = pdFALSE; + +/* Queue used by the second test. */ +xQueueHandle xSuspendedTestQueue; + +/*-----------------------------------------------------------*/ +/* + * Start the seven tasks as described at the top of the file. + * Note that the limited count task is given a higher priority. + */ +void vStartDynamicPriorityTasks( void ) +{ + xSuspendedTestQueue = xQueueCreate( priSUSPENDED_QUEUE_LENGTH, sizeof( unsigned portLONG ) ); + xTaskCreate( vContinuousIncrementTask, "CONT_INC", priSTACK_SIZE, ( void * ) &ulCounter, tskIDLE_PRIORITY, &xContinuousIncrementHandle ); + xTaskCreate( vLimitedIncrementTask, "LIM_INC", priSTACK_SIZE, ( void * ) &ulCounter, tskIDLE_PRIORITY + 1, &xLimitedIncrementHandle ); + xTaskCreate( vCounterControlTask, "C_CTRL", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vQueueSendWhenSuspendedTask, "SUSP_SEND", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vQueueReceiveWhenSuspendedTask, "SUSP_RECV", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + xTaskCreate( prvChangePriorityWhenSuspendedTask, "1st_P_CHANGE", priSTACK_SIZE, NULL, tskIDLE_PRIORITY + 1, NULL ); + xTaskCreate( prvChangePriorityHelperTask, "2nd_P_CHANGE", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, &xChangePriorityWhenSuspendedHandle ); +} +/*-----------------------------------------------------------*/ + +/* + * Just loops around incrementing the shared variable until the limit has been + * reached. Once the limit has been reached it suspends itself. + */ +static void vLimitedIncrementTask( void * pvParameters ) +{ +unsigned portLONG *pulCounter; + + /* Take a pointer to the shared variable from the parameters passed into + the task. */ + pulCounter = ( unsigned portLONG * ) pvParameters; + + /* This will run before the control task, so the first thing it does is + suspend - the control task will resume it when ready. */ + vTaskSuspend( NULL ); + + for( ;; ) + { + /* Just count up to a value then suspend. */ + ( *pulCounter )++; + + if( *pulCounter >= priMAX_COUNT ) + { + vTaskSuspend( NULL ); + } + } +} +/*-----------------------------------------------------------*/ + +/* + * Just keep counting the shared variable up. The control task will suspend + * this task when it wants. + */ +static void vContinuousIncrementTask( void * pvParameters ) +{ +unsigned portLONG *pulCounter; +unsigned portBASE_TYPE uxOurPriority; + + /* Take a pointer to the shared variable from the parameters passed into + the task. */ + pulCounter = ( unsigned portLONG * ) pvParameters; + + /* Query our priority so we can raise it when exclusive access to the + shared variable is required. */ + uxOurPriority = uxTaskPriorityGet( NULL ); + + for( ;; ) + { + /* Raise our priority above the controller task to ensure a context + switch does not occur while we are accessing this variable. */ + vTaskPrioritySet( NULL, uxOurPriority + 1 ); + ( *pulCounter )++; + vTaskPrioritySet( NULL, uxOurPriority ); + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + } +} +/*-----------------------------------------------------------*/ + +/* + * Controller task as described above. + */ +static void vCounterControlTask( void * pvParameters ) +{ +unsigned portLONG ulLastCounter; +portSHORT sLoops; +portSHORT sError = pdFALSE; +const portCHAR * const pcTaskStartMsg = "Priority manipulation tasks started.\r\n"; +const portCHAR * const pcTaskFailMsg = "Priority manipulation Task Failed\r\n"; + + /* Just to stop warning messages. */ + ( void ) pvParameters; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + for( ;; ) + { + /* Start with the counter at zero. */ + ulCounter = ( unsigned portLONG ) 0; + + /* First section : */ + + /* Check the continuous count task is running. */ + for( sLoops = 0; sLoops < priLOOPS; sLoops++ ) + { + /* Suspend the continuous count task so we can take a mirror of the + shared variable without risk of corruption. */ + vTaskSuspend( xContinuousIncrementHandle ); + ulLastCounter = ulCounter; + vTaskResume( xContinuousIncrementHandle ); + + /* Now delay to ensure the other task has processor time. */ + vTaskDelay( priSLEEP_TIME ); + + /* Check the shared variable again. This time to ensure mutual + exclusion the whole scheduler will be locked. This is just for + demo purposes! */ + vTaskSuspendAll(); + { + if( ulLastCounter == ulCounter ) + { + /* The shared variable has not changed. There is a problem + with the continuous count task so flag an error. */ + sError = pdTRUE; + xTaskResumeAll(); + vPrintDisplayMessage( &pcTaskFailMsg ); + vTaskSuspendAll(); + } + } + xTaskResumeAll(); + } + + + /* Second section: */ + + /* Suspend the continuous counter task so it stops accessing the shared variable. */ + vTaskSuspend( xContinuousIncrementHandle ); + + /* Reset the variable. */ + ulCounter = ( unsigned portLONG ) 0; + + /* Resume the limited count task which has a higher priority than us. + We should therefore not return from this call until the limited count + task has suspended itself with a known value in the counter variable. + The scheduler suspension is not necessary but is included for test + purposes. */ + vTaskSuspendAll(); + vTaskResume( xLimitedIncrementHandle ); + xTaskResumeAll(); + + /* Does the counter variable have the expected value? */ + if( ulCounter != priMAX_COUNT ) + { + sError = pdTRUE; + vPrintDisplayMessage( &pcTaskFailMsg ); + } + + if( sError == pdFALSE ) + { + /* If no errors have occurred then increment the check variable. */ + portENTER_CRITICAL(); + usCheckVariable++; + portEXIT_CRITICAL(); + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* Resume the continuous count task and do it all again. */ + vTaskResume( xContinuousIncrementHandle ); + } +} +/*-----------------------------------------------------------*/ + +static void vQueueSendWhenSuspendedTask( void *pvParameters ) +{ +static unsigned portLONG ulValueToSend = ( unsigned portLONG ) 0; +const portCHAR * const pcTaskStartMsg = "Queue send while suspended task started.\r\n"; +const portCHAR * const pcTaskFailMsg = "Queue send while suspended failed.\r\n"; + + /* Just to stop warning messages. */ + ( void ) pvParameters; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + for( ;; ) + { + vTaskSuspendAll(); + { + /* We must not block while the scheduler is suspended! */ + if( xQueueSend( xSuspendedTestQueue, ( void * ) &ulValueToSend, priNO_BLOCK ) != pdTRUE ) + { + if( xSuspendedQueueSendError == pdFALSE ) + { + xTaskResumeAll(); + vPrintDisplayMessage( &pcTaskFailMsg ); + vTaskSuspendAll(); + } + + xSuspendedQueueSendError = pdTRUE; + } + } + xTaskResumeAll(); + + vTaskDelay( priSLEEP_TIME ); + + ++ulValueToSend; + } +} +/*-----------------------------------------------------------*/ + +static void vQueueReceiveWhenSuspendedTask( void *pvParameters ) +{ +static unsigned portLONG ulExpectedValue = ( unsigned portLONG ) 0, ulReceivedValue; +const portCHAR * const pcTaskStartMsg = "Queue receive while suspended task started.\r\n"; +const portCHAR * const pcTaskFailMsg = "Queue receive while suspended failed.\r\n"; +portBASE_TYPE xGotValue; + + /* Just to stop warning messages. */ + ( void ) pvParameters; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + for( ;; ) + { + do + { + /* Suspending the scheduler here is fairly pointless and + undesirable for a normal application. It is done here purely + to test the scheduler. The inner xTaskResumeAll() should + never return pdTRUE as the scheduler is still locked by the + outer call. */ + vTaskSuspendAll(); + { + vTaskSuspendAll(); + { + xGotValue = xQueueReceive( xSuspendedTestQueue, ( void * ) &ulReceivedValue, priNO_BLOCK ); + } + if( xTaskResumeAll() ) + { + xSuspendedQueueReceiveError = pdTRUE; + } + } + xTaskResumeAll(); + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + } while( xGotValue == pdFALSE ); + + if( ulReceivedValue != ulExpectedValue ) + { + if( xSuspendedQueueReceiveError == pdFALSE ) + { + vPrintDisplayMessage( &pcTaskFailMsg ); + } + xSuspendedQueueReceiveError = pdTRUE; + } + + ++ulExpectedValue; + } +} +/*-----------------------------------------------------------*/ + +static void prvChangePriorityWhenSuspendedTask( void *pvParameters ) +{ +const portCHAR * const pcTaskStartMsg = "Priority change when suspended task started.\r\n"; +const portCHAR * const pcTaskFailMsg = "Priority change when suspended task failed.\r\n"; + + /* Just to stop warning messages. */ + ( void ) pvParameters; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + for( ;; ) + { + /* Start with the counter at 0 so we know what the counter should be + when we check it next. */ + ulPrioritySetCounter = ( unsigned portLONG ) 0; + + /* Resume the helper task. At this time it has a priority lower than + ours so no context switch should occur. */ + vTaskResume( xChangePriorityWhenSuspendedHandle ); + + /* Check to ensure the task just resumed has not executed. */ + portENTER_CRITICAL(); + { + if( ulPrioritySetCounter != ( unsigned portLONG ) 0 ) + { + xPriorityRaiseWhenSuspendedError = pdTRUE; + vPrintDisplayMessage( &pcTaskFailMsg ); + } + } + portEXIT_CRITICAL(); + + /* Now try raising the priority while the scheduler is suspended. */ + vTaskSuspendAll(); + { + vTaskPrioritySet( xChangePriorityWhenSuspendedHandle, ( configMAX_PRIORITIES - 1 ) ); + + /* Again, even though the helper task has a priority greater than + ours, it should not have executed yet because the scheduler is + suspended. */ + portENTER_CRITICAL(); + { + if( ulPrioritySetCounter != ( unsigned portLONG ) 0 ) + { + xPriorityRaiseWhenSuspendedError = pdTRUE; + vPrintDisplayMessage( &pcTaskFailMsg ); + } + } + portEXIT_CRITICAL(); + } + xTaskResumeAll(); + + /* Now the scheduler has been resumed the helper task should + immediately preempt us and execute. When it executes it will increment + the ulPrioritySetCounter exactly once before suspending itself. + + We should now always find the counter set to 1. */ + portENTER_CRITICAL(); + { + if( ulPrioritySetCounter != ( unsigned portLONG ) 1 ) + { + xPriorityRaiseWhenSuspendedError = pdTRUE; + vPrintDisplayMessage( &pcTaskFailMsg ); + } + } + portEXIT_CRITICAL(); + + /* Delay until we try this again. */ + vTaskDelay( priSLEEP_TIME * 2 ); + + /* Set the priority of the helper task back ready for the next + execution of this task. */ + vTaskSuspendAll(); + vTaskPrioritySet( xChangePriorityWhenSuspendedHandle, tskIDLE_PRIORITY ); + xTaskResumeAll(); + } +} +/*-----------------------------------------------------------*/ + +static void prvChangePriorityHelperTask( void *pvParameters ) +{ + /* Just to stop warning messages. */ + ( void ) pvParameters; + + for( ;; ) + { + /* This is the helper task for prvChangePriorityWhenSuspendedTask(). + It has it's priority raised and lowered. When it runs it simply + increments the counter then suspends itself again. This allows + prvChangePriorityWhenSuspendedTask() to know how many times it has + executed. */ + ulPrioritySetCounter++; + vTaskSuspend( NULL ); + } +} +/*-----------------------------------------------------------*/ + +/* Called to check that all the created tasks are still running without error. */ +portBASE_TYPE xAreDynamicPriorityTasksStillRunning( void ) +{ +/* Keep a history of the check variables so we know if it has been incremented +since the last call. */ +static unsigned portSHORT usLastTaskCheck = ( unsigned portSHORT ) 0; +portBASE_TYPE xReturn = pdTRUE; + + /* Check the tasks are still running by ensuring the check variable + is still incrementing. */ + + if( usCheckVariable == usLastTaskCheck ) + { + /* The check has not incremented so an error exists. */ + xReturn = pdFALSE; + } + + if( xSuspendedQueueSendError == pdTRUE ) + { + xReturn = pdFALSE; + } + + if( xSuspendedQueueReceiveError == pdTRUE ) + { + xReturn = pdFALSE; + } + + if( xPriorityRaiseWhenSuspendedError == pdTRUE ) + { + xReturn = pdFALSE; + } + + usLastTaskCheck = usCheckVariable; + return xReturn; +} + + + + diff --git a/20080212/Demo/Common/Full/events.c b/20080212/Demo/Common/Full/events.c new file mode 100644 index 000000000..f56cda08f --- /dev/null +++ b/20080212/Demo/Common/Full/events.c @@ -0,0 +1,383 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/** + * This file exercises the event mechanism whereby more than one task is + * blocked waiting for the same event. + * + * The demo creates five tasks - four 'event' tasks, and a controlling task. + * The event tasks have various different priorities and all block on reading + * the same queue. The controlling task writes data to the queue, then checks + * to see which of the event tasks read the data from the queue. The + * controlling task has the lowest priority of all the tasks so is guaranteed + * to always get preempted immediately upon writing to the queue. + * + * By selectively suspending and resuming the event tasks the controlling task + * can check that the highest priority task that is blocked on the queue is the + * task that reads the posted data from the queue. + * + * Two of the event tasks share the same priority. When neither of these tasks + * are suspended they should alternate - one reading one message from the queue, + * the other the next message, etc. + */ + +/* Standard includes. */ +#include +#include +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* Demo program include files. */ +#include "mevents.h" +#include "print.h" + +/* Demo specific constants. */ +#define evtSTACK_SIZE ( ( unsigned portBASE_TYPE ) configMINIMAL_STACK_SIZE ) +#define evtNUM_TASKS ( 4 ) +#define evtQUEUE_LENGTH ( ( unsigned portBASE_TYPE ) 3 ) +#define evtNO_DELAY 0 + +/* Just indexes used to uniquely identify the tasks. Note that two tasks are +'highest' priority. */ +#define evtHIGHEST_PRIORITY_INDEX_2 3 +#define evtHIGHEST_PRIORITY_INDEX_1 2 +#define evtMEDIUM_PRIORITY_INDEX 1 +#define evtLOWEST_PRIORITY_INDEX 0 + +/* Each event task increments one of these counters each time it reads data +from the queue. */ +static volatile portBASE_TYPE xTaskCounters[ evtNUM_TASKS ] = { 0, 0, 0, 0 }; + +/* Each time the controlling task posts onto the queue it increments the +expected count of the task that it expected to read the data from the queue +(i.e. the task with the highest priority that should be blocked on the queue). + +xExpectedTaskCounters are incremented from the controlling task, and +xTaskCounters are incremented from the individual event tasks - therefore +comparing xTaskCounters to xExpectedTaskCounters shows whether or not the +correct task was unblocked by the post. */ +static portBASE_TYPE xExpectedTaskCounters[ evtNUM_TASKS ] = { 0, 0, 0, 0 }; + +/* Handles to the four event tasks. These are required to suspend and resume +the tasks. */ +static xTaskHandle xCreatedTasks[ evtNUM_TASKS ]; + +/* The single queue onto which the controlling task posts, and the four event +tasks block. */ +static xQueueHandle xQueue; + +/* Flag used to indicate whether or not an error has occurred at any time. +An error is either the queue being full when not expected, or an unexpected +task reading data from the queue. */ +static portBASE_TYPE xHealthStatus = pdPASS; + +/*-----------------------------------------------------------*/ + +/* Function that implements the event task. This is created four times. */ +static void prvMultiEventTask( void *pvParameters ); + +/* Function that implements the controlling task. */ +static void prvEventControllerTask( void *pvParameters ); + +/* This is a utility function that posts data to the queue, then compares +xExpectedTaskCounters with xTaskCounters to ensure everything worked as +expected. + +The event tasks all have higher priorities the controlling task. Therefore +the controlling task will always get preempted between writhing to the queue +and checking the task counters. + +@param xExpectedTask The index to the task that the controlling task thinks + should be the highest priority task waiting for data, and + therefore the task that will unblock. + +@param xIncrement The number of items that should be written to the queue. +*/ +static void prvCheckTaskCounters( portBASE_TYPE xExpectedTask, portBASE_TYPE xIncrement ); + +/* This is just incremented each cycle of the controlling tasks function so +the main application can ensure the test is still running. */ +static portBASE_TYPE xCheckVariable = 0; + +/*-----------------------------------------------------------*/ + +void vStartMultiEventTasks( void ) +{ + /* Create the queue to be used for all the communications. */ + xQueue = xQueueCreate( evtQUEUE_LENGTH, ( unsigned portBASE_TYPE ) sizeof( unsigned portBASE_TYPE ) ); + + /* Start the controlling task. This has the idle priority to ensure it is + always preempted by the event tasks. */ + xTaskCreate( prvEventControllerTask, "EvntCTRL", evtSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + + /* Start the four event tasks. Note that two have priority 3, one + priority 2 and the other priority 1. */ + xTaskCreate( prvMultiEventTask, "Event0", evtSTACK_SIZE, ( void * ) &( xTaskCounters[ 0 ] ), 1, &( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] ) ); + xTaskCreate( prvMultiEventTask, "Event1", evtSTACK_SIZE, ( void * ) &( xTaskCounters[ 1 ] ), 2, &( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] ) ); + xTaskCreate( prvMultiEventTask, "Event2", evtSTACK_SIZE, ( void * ) &( xTaskCounters[ 2 ] ), 3, &( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ) ); + xTaskCreate( prvMultiEventTask, "Event3", evtSTACK_SIZE, ( void * ) &( xTaskCounters[ 3 ] ), 3, &( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_2 ] ) ); +} +/*-----------------------------------------------------------*/ + +static void prvMultiEventTask( void *pvParameters ) +{ +portBASE_TYPE *pxCounter; +unsigned portBASE_TYPE uxDummy; +const portCHAR * const pcTaskStartMsg = "Multi event task started.\r\n"; + + /* The variable this task will increment is passed in as a parameter. */ + pxCounter = ( portBASE_TYPE * ) pvParameters; + + vPrintDisplayMessage( &pcTaskStartMsg ); + + for( ;; ) + { + /* Block on the queue. */ + if( xQueueReceive( xQueue, &uxDummy, portMAX_DELAY ) ) + { + /* We unblocked by reading the queue - so simply increment + the counter specific to this task instance. */ + ( *pxCounter )++; + } + else + { + xHealthStatus = pdFAIL; + } + } +} +/*-----------------------------------------------------------*/ + +static void prvEventControllerTask( void *pvParameters ) +{ +const portCHAR * const pcTaskStartMsg = "Multi event controller task started.\r\n"; +portBASE_TYPE xDummy = 0; + + /* Just to stop warnings. */ + ( void ) pvParameters; + + vPrintDisplayMessage( &pcTaskStartMsg ); + + for( ;; ) + { + /* All tasks are blocked on the queue. When a message is posted one of + the two tasks that share the highest priority should unblock to read + the queue. The next message written should unblock the other task with + the same high priority, and so on in order. No other task should + unblock to read data as they have lower priorities. */ + + prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 ); + prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_2, 1 ); + prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 ); + prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_2, 1 ); + prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 ); + + /* For the rest of these tests we don't need the second 'highest' + priority task - so it is suspended. */ + vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_2 ] ); + + + + /* Now suspend the other highest priority task. The medium priority + task will then be the task with the highest priority that remains + blocked on the queue. */ + vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ); + + /* This time, when we post onto the queue we will expect the medium + priority task to unblock and preempt us. */ + prvCheckTaskCounters( evtMEDIUM_PRIORITY_INDEX, 1 ); + + /* Now try resuming the highest priority task while the scheduler is + suspended. The task should start executing as soon as the scheduler + is resumed - therefore when we post to the queue again, the highest + priority task should again preempt us. */ + vTaskSuspendAll(); + vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ); + xTaskResumeAll(); + prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 ); + + /* Now we are going to suspend the high and medium priority tasks. The + low priority task should then preempt us. Again the task suspension is + done with the whole scheduler suspended just for test purposes. */ + vTaskSuspendAll(); + vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ); + vTaskSuspend( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] ); + xTaskResumeAll(); + prvCheckTaskCounters( evtLOWEST_PRIORITY_INDEX, 1 ); + + /* Do the same basic test another few times - selectively suspending + and resuming tasks and each time calling prvCheckTaskCounters() passing + to the function the number of the task we expected to be unblocked by + the post. */ + + vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ); + prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 ); + + vTaskSuspendAll(); /* Just for test. */ + vTaskSuspendAll(); /* Just for test. */ + vTaskSuspendAll(); /* Just for even more test. */ + vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ); + xTaskResumeAll(); + xTaskResumeAll(); + xTaskResumeAll(); + prvCheckTaskCounters( evtLOWEST_PRIORITY_INDEX, 1 ); + + vTaskResume( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] ); + prvCheckTaskCounters( evtMEDIUM_PRIORITY_INDEX, 1 ); + + vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ); + prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 ); + + /* Now a slight change, first suspend all tasks. */ + vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ); + vTaskSuspend( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] ); + vTaskSuspend( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] ); + + /* Now when we resume the low priority task and write to the queue 3 + times. We expect the low priority task to service the queue three + times. */ + vTaskResume( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] ); + prvCheckTaskCounters( evtLOWEST_PRIORITY_INDEX, evtQUEUE_LENGTH ); + + /* Again suspend all tasks (only the low priority task is not suspended + already). */ + vTaskSuspend( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] ); + + /* This time we are going to suspend the scheduler, resume the low + priority task, then resume the high priority task. In this state we + will write to the queue three times. When the scheduler is resumed + we expect the high priority task to service all three messages. */ + vTaskSuspendAll(); + { + vTaskResume( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] ); + vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ); + + for( xDummy = 0; xDummy < evtQUEUE_LENGTH; xDummy++ ) + { + if( xQueueSend( xQueue, &xDummy, evtNO_DELAY ) != pdTRUE ) + { + xHealthStatus = pdFAIL; + } + } + + /* The queue should not have been serviced yet!. The scheduler + is still suspended. */ + if( memcmp( ( void * ) xExpectedTaskCounters, ( void * ) xTaskCounters, sizeof( xExpectedTaskCounters ) ) ) + { + xHealthStatus = pdFAIL; + } + } + xTaskResumeAll(); + + /* We should have been preempted by resuming the scheduler - so by the + time we are running again we expect the high priority task to have + removed three items from the queue. */ + xExpectedTaskCounters[ evtHIGHEST_PRIORITY_INDEX_1 ] += evtQUEUE_LENGTH; + if( memcmp( ( void * ) xExpectedTaskCounters, ( void * ) xTaskCounters, sizeof( xExpectedTaskCounters ) ) ) + { + xHealthStatus = pdFAIL; + } + + /* The medium priority and second high priority tasks are still + suspended. Make sure to resume them before starting again. */ + vTaskResume( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] ); + vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_2 ] ); + + /* Just keep incrementing to show the task is still executing. */ + xCheckVariable++; + } +} +/*-----------------------------------------------------------*/ + +static void prvCheckTaskCounters( portBASE_TYPE xExpectedTask, portBASE_TYPE xIncrement ) +{ +portBASE_TYPE xDummy = 0; + + /* Write to the queue the requested number of times. The data written is + not important. */ + for( xDummy = 0; xDummy < xIncrement; xDummy++ ) + { + if( xQueueSend( xQueue, &xDummy, evtNO_DELAY ) != pdTRUE ) + { + /* Did not expect to ever find the queue full. */ + xHealthStatus = pdFAIL; + } + } + + /* All the tasks blocked on the queue have a priority higher than the + controlling task. Writing to the queue will therefore have caused this + task to be preempted. By the time this line executes the event task will + have executed and incremented its counter. Increment the expected counter + to the same value. */ + ( xExpectedTaskCounters[ xExpectedTask ] ) += xIncrement; + + /* Check the actual counts and expected counts really are the same. */ + if( memcmp( ( void * ) xExpectedTaskCounters, ( void * ) xTaskCounters, sizeof( xExpectedTaskCounters ) ) ) + { + /* The counters were not the same. This means a task we did not expect + to unblock actually did unblock. */ + xHealthStatus = pdFAIL; + } +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xAreMultiEventTasksStillRunning( void ) +{ +static portBASE_TYPE xPreviousCheckVariable = 0; + + /* Called externally to periodically check that this test is still + operational. */ + + if( xPreviousCheckVariable == xCheckVariable ) + { + xHealthStatus = pdFAIL; + } + + xPreviousCheckVariable = xCheckVariable; + + return xHealthStatus; +} + + diff --git a/20080212/Demo/Common/Full/flash.c b/20080212/Demo/Common/Full/flash.c new file mode 100644 index 000000000..c3fe23c07 --- /dev/null +++ b/20080212/Demo/Common/Full/flash.c @@ -0,0 +1,143 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +/** + * Creates eight tasks, each of which flash an LED at a different rate. The first + * LED flashes every 125ms, the second every 250ms, the third every 375ms, etc. + * + * The LED flash tasks provide instant visual feedback. They show that the scheduler + * is still operational. + * + * The PC port uses the standard parallel port for outputs, the Flashlite 186 port + * uses IO port F. + * + * \page flashC flash.c + * \ingroup DemoFiles + *
+ */ + +/* +Changes from V2.0.0 + + + Delay periods are now specified using variables and constants of + portTickType rather than unsigned portLONG. + +Changes from V2.1.1 + + + The stack size now uses configMINIMAL_STACK_SIZE. + + String constants made file scope to decrease stack depth on 8051 port. +*/ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo program include files. */ +#include "partest.h" +#include "flash.h" +#include "print.h" + +#define ledSTACK_SIZE configMINIMAL_STACK_SIZE + +/* Structure used to pass parameters to the LED tasks. */ +typedef struct LED_PARAMETERS +{ + unsigned portBASE_TYPE uxLED; /*< The output the task should use. */ + portTickType xFlashRate; /*< The rate at which the LED should flash. */ +} xLEDParameters; + +/* The task that is created eight times - each time with a different xLEDParaemtes +structure passed in as the parameter. */ +static void vLEDFlashTask( void *pvParameters ); + +/* String to print if USE_STDIO is defined. */ +const portCHAR * const pcTaskStartMsg = "LED flash task started.\r\n"; + +/*-----------------------------------------------------------*/ + +void vStartLEDFlashTasks( unsigned portBASE_TYPE uxPriority ) +{ +unsigned portBASE_TYPE uxLEDTask; +xLEDParameters *pxLEDParameters; +const unsigned portBASE_TYPE uxNumOfLEDs = 8; +const portTickType xFlashRate = 125; + + /* Create the eight tasks. */ + for( uxLEDTask = 0; uxLEDTask < uxNumOfLEDs; ++uxLEDTask ) + { + /* Create and complete the structure used to pass parameters to the next + created task. */ + pxLEDParameters = ( xLEDParameters * ) pvPortMalloc( sizeof( xLEDParameters ) ); + pxLEDParameters->uxLED = uxLEDTask; + pxLEDParameters->xFlashRate = ( xFlashRate + ( xFlashRate * ( portTickType ) uxLEDTask ) ); + pxLEDParameters->xFlashRate /= portTICK_RATE_MS; + + /* Spawn the task. */ + xTaskCreate( vLEDFlashTask, "LEDx", ledSTACK_SIZE, ( void * ) pxLEDParameters, uxPriority, ( xTaskHandle * ) NULL ); + } +} +/*-----------------------------------------------------------*/ + +static void vLEDFlashTask( void *pvParameters ) +{ +xLEDParameters *pxParameters; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + pxParameters = ( xLEDParameters * ) pvParameters; + + for(;;) + { + /* Delay for half the flash period then turn the LED on. */ + vTaskDelay( pxParameters->xFlashRate / ( portTickType ) 2 ); + vParTestToggleLED( pxParameters->uxLED ); + + /* Delay for half the flash period then turn the LED off. */ + vTaskDelay( pxParameters->xFlashRate / ( portTickType ) 2 ); + vParTestToggleLED( pxParameters->uxLED ); + } +} + diff --git a/20080212/Demo/Common/Full/flop.c b/20080212/Demo/Common/Full/flop.c new file mode 100644 index 000000000..91d124087 --- /dev/null +++ b/20080212/Demo/Common/Full/flop.c @@ -0,0 +1,346 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V1.2.3 + + + The created tasks now include calls to tskYIELD(), allowing them to be used + with the cooperative scheduler. +*/ + +/** + * Creates eight tasks, each of which loops continuously performing an (emulated) + * floating point calculation. + * + * All the tasks run at the idle priority and never block or yield. This causes + * all eight tasks to time slice with the idle task. Running at the idle priority + * means that these tasks will get pre-empted any time another task is ready to run + * or a time slice occurs. More often than not the pre-emption will occur mid + * calculation, creating a good test of the schedulers context switch mechanism - a + * calculation producing an unexpected result could be a symptom of a corruption in + * the context of a task. + * + * \page FlopC flop.c + * \ingroup DemoFiles + *
+ */ + +#include +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "print.h" + +/* Demo program include files. */ +#include "flop.h" + +#define mathSTACK_SIZE ( ( unsigned portSHORT ) 512 ) +#define mathNUMBER_OF_TASKS ( 8 ) + +/* Four tasks, each of which performs a different floating point calculation. +Each of the four is created twice. */ +static void vCompetingMathTask1( void *pvParameters ); +static void vCompetingMathTask2( void *pvParameters ); +static void vCompetingMathTask3( void *pvParameters ); +static void vCompetingMathTask4( void *pvParameters ); + +/* These variables are used to check that all the tasks are still running. If a +task gets a calculation wrong it will +stop incrementing its check variable. */ +static volatile unsigned portSHORT usTaskCheck[ mathNUMBER_OF_TASKS ] = { ( unsigned portSHORT ) 0 }; + +/*-----------------------------------------------------------*/ + +void vStartMathTasks( unsigned portBASE_TYPE uxPriority ) +{ + xTaskCreate( vCompetingMathTask1, "Math1", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 0 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask2, "Math2", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 1 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask3, "Math3", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 2 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask4, "Math4", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 3 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask1, "Math5", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 4 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask2, "Math6", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 5 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask3, "Math7", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 6 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask4, "Math8", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 7 ] ), uxPriority, NULL ); +} +/*-----------------------------------------------------------*/ + +static void vCompetingMathTask1( void *pvParameters ) +{ +portDOUBLE d1, d2, d3, d4; +volatile unsigned portSHORT *pusTaskCheckVariable; +const portDOUBLE dAnswer = ( 123.4567 + 2345.6789 ) * -918.222; +const portCHAR * const pcTaskStartMsg = "Math task 1 started.\r\n"; +const portCHAR * const pcTaskFailMsg = "Math task 1 failed.\r\n"; +portSHORT sError = pdFALSE; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + /* The variable this task increments to show it is still running is passed in + as the parameter. */ + pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters; + + /* Keep performing a calculation and checking the result against a constant. */ + for(;;) + { + d1 = 123.4567; + d2 = 2345.6789; + d3 = -918.222; + + d4 = ( d1 + d2 ) * d3; + + taskYIELD(); + + /* If the calculation does not match the expected constant, stop the + increment of the check variable. */ + if( fabs( d4 - dAnswer ) > 0.001 ) + { + vPrintDisplayMessage( &pcTaskFailMsg ); + sError = pdTRUE; + } + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + variable so we know this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + + taskYIELD(); + } +} +/*-----------------------------------------------------------*/ + +static void vCompetingMathTask2( void *pvParameters ) +{ +portDOUBLE d1, d2, d3, d4; +volatile unsigned portSHORT *pusTaskCheckVariable; +const portDOUBLE dAnswer = ( -389.38 / 32498.2 ) * -2.0001; +const portCHAR * const pcTaskStartMsg = "Math task 2 started.\r\n"; +const portCHAR * const pcTaskFailMsg = "Math task 2 failed.\r\n"; +portSHORT sError = pdFALSE; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + /* The variable this task increments to show it is still running is passed in + as the parameter. */ + pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters; + + /* Keep performing a calculation and checking the result against a constant. */ + for( ;; ) + { + d1 = -389.38; + d2 = 32498.2; + d3 = -2.0001; + + d4 = ( d1 / d2 ) * d3; + + taskYIELD(); + + /* If the calculation does not match the expected constant, stop the + increment of the check variable. */ + if( fabs( d4 - dAnswer ) > 0.001 ) + { + vPrintDisplayMessage( &pcTaskFailMsg ); + sError = pdTRUE; + } + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + variable so we know + this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + + taskYIELD(); + } +} +/*-----------------------------------------------------------*/ + +static void vCompetingMathTask3( void *pvParameters ) +{ +portDOUBLE *pdArray, dTotal1, dTotal2, dDifference; +volatile unsigned portSHORT *pusTaskCheckVariable; +const unsigned portSHORT usArraySize = 250; +unsigned portSHORT usPosition; +const portCHAR * const pcTaskStartMsg = "Math task 3 started.\r\n"; +const portCHAR * const pcTaskFailMsg = "Math task 3 failed.\r\n"; +portSHORT sError = pdFALSE; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + /* The variable this task increments to show it is still running is passed in + as the parameter. */ + pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters; + + pdArray = ( portDOUBLE * ) pvPortMalloc( ( size_t ) 250 * sizeof( portDOUBLE ) ); + + /* Keep filling an array, keeping a running total of the values placed in the + array. Then run through the array adding up all the values. If the two totals + do not match, stop the check variable from incrementing. */ + for( ;; ) + { + dTotal1 = 0.0; + dTotal2 = 0.0; + + for( usPosition = 0; usPosition < usArraySize; usPosition++ ) + { + pdArray[ usPosition ] = ( portDOUBLE ) usPosition + 5.5; + dTotal1 += ( portDOUBLE ) usPosition + 5.5; + } + + taskYIELD(); + + for( usPosition = 0; usPosition < usArraySize; usPosition++ ) + { + dTotal2 += pdArray[ usPosition ]; + } + + dDifference = dTotal1 - dTotal2; + if( fabs( dDifference ) > 0.001 ) + { + vPrintDisplayMessage( &pcTaskFailMsg ); + sError = pdTRUE; + } + + taskYIELD(); + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + variable so we know this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + } +} +/*-----------------------------------------------------------*/ + +static void vCompetingMathTask4( void *pvParameters ) +{ +portDOUBLE *pdArray, dTotal1, dTotal2, dDifference; +volatile unsigned portSHORT *pusTaskCheckVariable; +const unsigned portSHORT usArraySize = 250; +unsigned portSHORT usPosition; +const portCHAR * const pcTaskStartMsg = "Math task 4 started.\r\n"; +const portCHAR * const pcTaskFailMsg = "Math task 4 failed.\r\n"; +portSHORT sError = pdFALSE; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + /* The variable this task increments to show it is still running is passed in + as the parameter. */ + pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters; + + pdArray = ( portDOUBLE * ) pvPortMalloc( ( size_t ) 250 * sizeof( portDOUBLE ) ); + + /* Keep filling an array, keeping a running total of the values placed in the + array. Then run through the array adding up all the values. If the two totals + do not match, stop the check variable from incrementing. */ + for( ;; ) + { + dTotal1 = 0.0; + dTotal2 = 0.0; + + for( usPosition = 0; usPosition < usArraySize; usPosition++ ) + { + pdArray[ usPosition ] = ( portDOUBLE ) usPosition * 12.123; + dTotal1 += ( portDOUBLE ) usPosition * 12.123; + } + + taskYIELD(); + + for( usPosition = 0; usPosition < usArraySize; usPosition++ ) + { + dTotal2 += pdArray[ usPosition ]; + } + + dDifference = dTotal1 - dTotal2; + if( fabs( dDifference ) > 0.001 ) + { + vPrintDisplayMessage( &pcTaskFailMsg ); + sError = pdTRUE; + } + + taskYIELD(); + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + variable so we know this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +portBASE_TYPE xAreMathsTaskStillRunning( void ) +{ +/* Keep a history of the check variables so we know if they have been incremented +since the last call. */ +static unsigned portSHORT usLastTaskCheck[ mathNUMBER_OF_TASKS ] = { ( unsigned portSHORT ) 0 }; +portBASE_TYPE xReturn = pdTRUE, xTask; + + /* Check the maths tasks are still running by ensuring their check variables + are still incrementing. */ + for( xTask = 0; xTask < mathNUMBER_OF_TASKS; xTask++ ) + { + if( usTaskCheck[ xTask ] == usLastTaskCheck[ xTask ] ) + { + /* The check has not incremented so an error exists. */ + xReturn = pdFALSE; + } + + usLastTaskCheck[ xTask ] = usTaskCheck[ xTask ]; + } + + return xReturn; +} + + + diff --git a/20080212/Demo/Common/Full/integer.c b/20080212/Demo/Common/Full/integer.c new file mode 100644 index 000000000..17581172a --- /dev/null +++ b/20080212/Demo/Common/Full/integer.c @@ -0,0 +1,342 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V1.2.3 + + + The created tasks now include calls to tskYIELD(), allowing them to be used + with the cooperative scheduler. +*/ + +/** + * This does the same as flop. c, but uses variables of type long instead of + * type double. + * + * As with flop. c, the tasks created in this file are a good test of the + * scheduler context switch mechanism. The processor has to access 32bit + * variables in two or four chunks (depending on the processor). The low + * priority of these tasks means there is a high probability that a context + * switch will occur mid calculation. See the flop. c documentation for + * more information. + * + * \page IntegerC integer.c + * \ingroup DemoFiles + *
+ */ + +/* +Changes from V1.2.1 + + + The constants used in the calculations are larger to ensure the + optimiser does not truncate them to 16 bits. +*/ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "print.h" + +/* Demo program include files. */ +#include "integer.h" + +#define intgSTACK_SIZE ( ( unsigned portSHORT ) 256 ) +#define intgNUMBER_OF_TASKS ( 8 ) + +/* Four tasks, each of which performs a different calculation on four byte +variables. Each of the four is created twice. */ +static void vCompeteingIntMathTask1( void *pvParameters ); +static void vCompeteingIntMathTask2( void *pvParameters ); +static void vCompeteingIntMathTask3( void *pvParameters ); +static void vCompeteingIntMathTask4( void *pvParameters ); + +/* These variables are used to check that all the tasks are still running. If a +task gets a calculation wrong it will stop incrementing its check variable. */ +static volatile unsigned portSHORT usTaskCheck[ intgNUMBER_OF_TASKS ] = { ( unsigned portSHORT ) 0 }; +/*-----------------------------------------------------------*/ + +void vStartIntegerMathTasks( unsigned portBASE_TYPE uxPriority ) +{ + xTaskCreate( vCompeteingIntMathTask1, "IntMath1", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 0 ] ), uxPriority, NULL ); + xTaskCreate( vCompeteingIntMathTask2, "IntMath2", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 1 ] ), uxPriority, NULL ); + xTaskCreate( vCompeteingIntMathTask3, "IntMath3", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 2 ] ), uxPriority, NULL ); + xTaskCreate( vCompeteingIntMathTask4, "IntMath4", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 3 ] ), uxPriority, NULL ); + xTaskCreate( vCompeteingIntMathTask1, "IntMath5", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 4 ] ), uxPriority, NULL ); + xTaskCreate( vCompeteingIntMathTask2, "IntMath6", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 5 ] ), uxPriority, NULL ); + xTaskCreate( vCompeteingIntMathTask3, "IntMath7", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 6 ] ), uxPriority, NULL ); + xTaskCreate( vCompeteingIntMathTask4, "IntMath8", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 7 ] ), uxPriority, NULL ); +} +/*-----------------------------------------------------------*/ + +static void vCompeteingIntMathTask1( void *pvParameters ) +{ +portLONG l1, l2, l3, l4; +portSHORT sError = pdFALSE; +volatile unsigned portSHORT *pusTaskCheckVariable; +const portLONG lAnswer = ( ( portLONG ) 74565L + ( portLONG ) 1234567L ) * ( portLONG ) -918L; +const portCHAR * const pcTaskStartMsg = "Integer math task 1 started.\r\n"; +const portCHAR * const pcTaskFailMsg = "Integer math task 1 failed.\r\n"; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + /* The variable this task increments to show it is still running is passed in + as the parameter. */ + pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters; + + /* Keep performing a calculation and checking the result against a constant. */ + for(;;) + { + l1 = ( portLONG ) 74565L; + l2 = ( portLONG ) 1234567L; + l3 = ( portLONG ) -918L; + + l4 = ( l1 + l2 ) * l3; + + taskYIELD(); + + /* If the calculation does not match the expected constant, stop the + increment of the check variable. */ + if( l4 != lAnswer ) + { + vPrintDisplayMessage( &pcTaskFailMsg ); + sError = pdTRUE; + } + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + variable so we know this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + } +} +/*-----------------------------------------------------------*/ + +static void vCompeteingIntMathTask2( void *pvParameters ) +{ +portLONG l1, l2, l3, l4; +portSHORT sError = pdFALSE; +volatile unsigned portSHORT *pusTaskCheckVariable; +const portLONG lAnswer = ( ( portLONG ) -389000L / ( portLONG ) 329999L ) * ( portLONG ) -89L; +const portCHAR * const pcTaskStartMsg = "Integer math task 2 started.\r\n"; +const portCHAR * const pcTaskFailMsg = "Integer math task 2 failed.\r\n"; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + /* The variable this task increments to show it is still running is passed in + as the parameter. */ + pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters; + + /* Keep performing a calculation and checking the result against a constant. */ + for( ;; ) + { + l1 = -389000L; + l2 = 329999L; + l3 = -89L; + + l4 = ( l1 / l2 ) * l3; + + taskYIELD(); + + /* If the calculation does not match the expected constant, stop the + increment of the check variable. */ + if( l4 != lAnswer ) + { + vPrintDisplayMessage( &pcTaskFailMsg ); + sError = pdTRUE; + } + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + variable so we know this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + } +} +/*-----------------------------------------------------------*/ + +static void vCompeteingIntMathTask3( void *pvParameters ) +{ +portLONG *plArray, lTotal1, lTotal2; +portSHORT sError = pdFALSE; +volatile unsigned portSHORT *pusTaskCheckVariable; +const unsigned portSHORT usArraySize = ( unsigned portSHORT ) 250; +unsigned portSHORT usPosition; +const portCHAR * const pcTaskStartMsg = "Integer math task 3 started.\r\n"; +const portCHAR * const pcTaskFailMsg = "Integer math task 3 failed.\r\n"; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + /* The variable this task increments to show it is still running is passed in + as the parameter. */ + pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters; + + /* Create the array we are going to use for our check calculation. */ + plArray = ( portLONG * ) pvPortMalloc( ( size_t ) 250 * sizeof( portLONG ) ); + + /* Keep filling the array, keeping a running total of the values placed in the + array. Then run through the array adding up all the values. If the two totals + do not match, stop the check variable from incrementing. */ + for( ;; ) + { + lTotal1 = ( portLONG ) 0; + lTotal2 = ( portLONG ) 0; + + for( usPosition = 0; usPosition < usArraySize; usPosition++ ) + { + plArray[ usPosition ] = ( portLONG ) usPosition + ( portLONG ) 5; + lTotal1 += ( portLONG ) usPosition + ( portLONG ) 5; + } + + taskYIELD(); + + for( usPosition = 0; usPosition < usArraySize; usPosition++ ) + { + lTotal2 += plArray[ usPosition ]; + } + + if( lTotal1 != lTotal2 ) + { + vPrintDisplayMessage( &pcTaskFailMsg ); + sError = pdTRUE; + } + + taskYIELD(); + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + variable so we know this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + } +} +/*-----------------------------------------------------------*/ + +static void vCompeteingIntMathTask4( void *pvParameters ) +{ +portLONG *plArray, lTotal1, lTotal2; +portSHORT sError = pdFALSE; +volatile unsigned portSHORT *pusTaskCheckVariable; +const unsigned portSHORT usArraySize = 250; +unsigned portSHORT usPosition; +const portCHAR * const pcTaskStartMsg = "Integer math task 4 started.\r\n"; +const portCHAR * const pcTaskFailMsg = "Integer math task 4 failed.\r\n"; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + + /* The variable this task increments to show it is still running is passed in + as the parameter. */ + pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters; + + /* Create the array we are going to use for our check calculation. */ + plArray = ( portLONG * ) pvPortMalloc( ( size_t ) 250 * sizeof( portLONG ) ); + + /* Keep filling the array, keeping a running total of the values placed in the + array. Then run through the array adding up all the values. If the two totals + do not match, stop the check variable from incrementing. */ + for( ;; ) + { + lTotal1 = ( portLONG ) 0; + lTotal2 = ( portLONG ) 0; + + for( usPosition = 0; usPosition < usArraySize; usPosition++ ) + { + plArray[ usPosition ] = ( portLONG ) usPosition * ( portLONG ) 12; + lTotal1 += ( portLONG ) usPosition * ( portLONG ) 12; + } + + taskYIELD(); + + for( usPosition = 0; usPosition < usArraySize; usPosition++ ) + { + lTotal2 += plArray[ usPosition ]; + } + + + if( lTotal1 != lTotal2 ) + { + vPrintDisplayMessage( &pcTaskFailMsg ); + sError = pdTRUE; + } + + taskYIELD(); + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + variable so we know this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +portBASE_TYPE xAreIntegerMathsTaskStillRunning( void ) +{ +/* Keep a history of the check variables so we know if they have been incremented +since the last call. */ +static unsigned portSHORT usLastTaskCheck[ intgNUMBER_OF_TASKS ] = { ( unsigned portSHORT ) 0 }; +portBASE_TYPE xReturn = pdTRUE, xTask; + + /* Check the maths tasks are still running by ensuring their check variables + are still incrementing. */ + for( xTask = 0; xTask < intgNUMBER_OF_TASKS; xTask++ ) + { + if( usTaskCheck[ xTask ] == usLastTaskCheck[ xTask ] ) + { + /* The check has not incremented so an error exists. */ + xReturn = pdFALSE; + } + + usLastTaskCheck[ xTask ] = usTaskCheck[ xTask ]; + } + + return xReturn; +} diff --git a/20080212/Demo/Common/Full/print.c b/20080212/Demo/Common/Full/print.c new file mode 100644 index 000000000..64ca2bcc6 --- /dev/null +++ b/20080212/Demo/Common/Full/print.c @@ -0,0 +1,121 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/** + * Manages a queue of strings that are waiting to be displayed. This is used to + * ensure mutual exclusion of console output. + * + * A task wishing to display a message will call vPrintDisplayMessage (), with a + * pointer to the string as the parameter. The pointer is posted onto the + * xPrintQueue queue. + * + * The task spawned in main. c blocks on xPrintQueue. When a message becomes + * available it calls pcPrintGetNextMessage () to obtain a pointer to the next + * string, then uses the functions defined in the portable layer FileIO. c to + * display the message. + * + * NOTE: + * Using console IO can disrupt real time performance - depending on the port. + * Standard C IO routines are not designed for real time applications. While + * standard IO is useful for demonstration and debugging an alternative method + * should be used if you actually require console IO as part of your application. + * + * \page PrintC print.c + * \ingroup DemoFiles + *
+ */ + +/* +Changes from V2.0.0 + + + Delay periods are now specified using variables and constants of + portTickType rather than unsigned portLONG. +*/ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "queue.h" + +/* Demo program include files. */ +#include "print.h" + +static xQueueHandle xPrintQueue; + +/*-----------------------------------------------------------*/ + +void vPrintInitialise( void ) +{ +const unsigned portBASE_TYPE uxQueueSize = 20; + + /* Create the queue on which errors will be reported. */ + xPrintQueue = xQueueCreate( uxQueueSize, ( unsigned portBASE_TYPE ) sizeof( portCHAR * ) ); +} +/*-----------------------------------------------------------*/ + +void vPrintDisplayMessage( const portCHAR * const * ppcMessageToSend ) +{ + #ifdef USE_STDIO + xQueueSend( xPrintQueue, ( void * ) ppcMessageToSend, ( portTickType ) 0 ); + #else + /* Stop warnings. */ + ( void ) ppcMessageToSend; + #endif +} +/*-----------------------------------------------------------*/ + +const portCHAR *pcPrintGetNextMessage( portTickType xPrintRate ) +{ +portCHAR *pcMessage; + + if( xQueueReceive( xPrintQueue, &pcMessage, xPrintRate ) == pdPASS ) + { + return pcMessage; + } + else + { + return NULL; + } +} + + diff --git a/20080212/Demo/Common/Full/semtest.c b/20080212/Demo/Common/Full/semtest.c new file mode 100644 index 000000000..ebe792283 --- /dev/null +++ b/20080212/Demo/Common/Full/semtest.c @@ -0,0 +1,300 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/** + * Creates two sets of two tasks. The tasks within a set share a variable, access + * to which is guarded by a semaphore. + * + * Each task starts by attempting to obtain the semaphore. On obtaining a + * semaphore a task checks to ensure that the guarded variable has an expected + * value. It then clears the variable to zero before counting it back up to the + * expected value in increments of 1. After each increment the variable is checked + * to ensure it contains the value to which it was just set. When the starting + * value is again reached the task releases the semaphore giving the other task in + * the set a chance to do exactly the same thing. The starting value is high + * enough to ensure that a tick is likely to occur during the incrementing loop. + * + * An error is flagged if at any time during the process a shared variable is + * found to have a value other than that expected. Such an occurrence would + * suggest an error in the mutual exclusion mechanism by which access to the + * variable is restricted. + * + * The first set of two tasks poll their semaphore. The second set use blocking + * calls. + * + * \page SemTestC semtest.c + * \ingroup DemoFiles + *
+ */ + +/* +Changes from V1.2.0: + + + The tasks that operate at the idle priority now use a lower expected + count than those running at a higher priority. This prevents the low + priority tasks from signaling an error because they have not been + scheduled enough time for each of them to count the shared variable to + the high value. + +Changes from V2.0.0 + + + Delay periods are now specified using variables and constants of + portTickType rather than unsigned portLONG. + +Changes from V2.1.1 + + + The stack size now uses configMINIMAL_STACK_SIZE. + + String constants made file scope to decrease stack depth on 8051 port. +*/ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Demo app include files. */ +#include "semtest.h" +#include "print.h" + +/* The value to which the shared variables are counted. */ +#define semtstBLOCKING_EXPECTED_VALUE ( ( unsigned portLONG ) 0xfff ) +#define semtstNON_BLOCKING_EXPECTED_VALUE ( ( unsigned portLONG ) 0xff ) + +#define semtstSTACK_SIZE configMINIMAL_STACK_SIZE + +#define semtstNUM_TASKS ( 4 ) + +#define semtstDELAY_FACTOR ( ( portTickType ) 10 ) + +/* The task function as described at the top of the file. */ +static void prvSemaphoreTest( void *pvParameters ); + +/* Structure used to pass parameters to each task. */ +typedef struct SEMAPHORE_PARAMETERS +{ + xSemaphoreHandle xSemaphore; + volatile unsigned portLONG *pulSharedVariable; + portTickType xBlockTime; +} xSemaphoreParameters; + +/* Variables used to check that all the tasks are still running without errors. */ +static volatile portSHORT sCheckVariables[ semtstNUM_TASKS ] = { 0 }; +static volatile portSHORT sNextCheckVariable = 0; + +/* Strings to print if USE_STDIO is defined. */ +const portCHAR * const pcPollingSemaphoreTaskError = "Guarded shared variable in unexpected state.\r\n"; +const portCHAR * const pcSemaphoreTaskStart = "Guarded shared variable task started.\r\n"; + +/*-----------------------------------------------------------*/ + +void vStartSemaphoreTasks( unsigned portBASE_TYPE uxPriority ) +{ +xSemaphoreParameters *pxFirstSemaphoreParameters, *pxSecondSemaphoreParameters; +const portTickType xBlockTime = ( portTickType ) 100; + + /* Create the structure used to pass parameters to the first two tasks. */ + pxFirstSemaphoreParameters = ( xSemaphoreParameters * ) pvPortMalloc( sizeof( xSemaphoreParameters ) ); + + if( pxFirstSemaphoreParameters != NULL ) + { + /* Create the semaphore used by the first two tasks. */ + vSemaphoreCreateBinary( pxFirstSemaphoreParameters->xSemaphore ); + + if( pxFirstSemaphoreParameters->xSemaphore != NULL ) + { + /* Create the variable which is to be shared by the first two tasks. */ + pxFirstSemaphoreParameters->pulSharedVariable = ( unsigned portLONG * ) pvPortMalloc( sizeof( unsigned portLONG ) ); + + /* Initialise the share variable to the value the tasks expect. */ + *( pxFirstSemaphoreParameters->pulSharedVariable ) = semtstNON_BLOCKING_EXPECTED_VALUE; + + /* The first two tasks do not block on semaphore calls. */ + pxFirstSemaphoreParameters->xBlockTime = ( portTickType ) 0; + + /* Spawn the first two tasks. As they poll they operate at the idle priority. */ + xTaskCreate( prvSemaphoreTest, "PolSEM1", semtstSTACK_SIZE, ( void * ) pxFirstSemaphoreParameters, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL ); + xTaskCreate( prvSemaphoreTest, "PolSEM2", semtstSTACK_SIZE, ( void * ) pxFirstSemaphoreParameters, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL ); + } + } + + /* Do exactly the same to create the second set of tasks, only this time + provide a block time for the semaphore calls. */ + pxSecondSemaphoreParameters = ( xSemaphoreParameters * ) pvPortMalloc( sizeof( xSemaphoreParameters ) ); + if( pxSecondSemaphoreParameters != NULL ) + { + vSemaphoreCreateBinary( pxSecondSemaphoreParameters->xSemaphore ); + + if( pxSecondSemaphoreParameters->xSemaphore != NULL ) + { + pxSecondSemaphoreParameters->pulSharedVariable = ( unsigned portLONG * ) pvPortMalloc( sizeof( unsigned portLONG ) ); + *( pxSecondSemaphoreParameters->pulSharedVariable ) = semtstBLOCKING_EXPECTED_VALUE; + pxSecondSemaphoreParameters->xBlockTime = xBlockTime / portTICK_RATE_MS; + + xTaskCreate( prvSemaphoreTest, "BlkSEM1", semtstSTACK_SIZE, ( void * ) pxSecondSemaphoreParameters, uxPriority, ( xTaskHandle * ) NULL ); + xTaskCreate( prvSemaphoreTest, "BlkSEM2", semtstSTACK_SIZE, ( void * ) pxSecondSemaphoreParameters, uxPriority, ( xTaskHandle * ) NULL ); + } + } +} +/*-----------------------------------------------------------*/ + +static void prvSemaphoreTest( void *pvParameters ) +{ +xSemaphoreParameters *pxParameters; +volatile unsigned portLONG *pulSharedVariable, ulExpectedValue; +unsigned portLONG ulCounter; +portSHORT sError = pdFALSE, sCheckVariableToUse; + + /* See which check variable to use. sNextCheckVariable is not semaphore + protected! */ + portENTER_CRITICAL(); + sCheckVariableToUse = sNextCheckVariable; + sNextCheckVariable++; + portEXIT_CRITICAL(); + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcSemaphoreTaskStart ); + + /* A structure is passed in as the parameter. This contains the shared + variable being guarded. */ + pxParameters = ( xSemaphoreParameters * ) pvParameters; + pulSharedVariable = pxParameters->pulSharedVariable; + + /* If we are blocking we use a much higher count to ensure loads of context + switches occur during the count. */ + if( pxParameters->xBlockTime > ( portTickType ) 0 ) + { + ulExpectedValue = semtstBLOCKING_EXPECTED_VALUE; + } + else + { + ulExpectedValue = semtstNON_BLOCKING_EXPECTED_VALUE; + } + + for( ;; ) + { + /* Try to obtain the semaphore. */ + if( xSemaphoreTake( pxParameters->xSemaphore, pxParameters->xBlockTime ) == pdPASS ) + { + /* We have the semaphore and so expect any other tasks using the + shared variable to have left it in the state we expect to find + it. */ + if( *pulSharedVariable != ulExpectedValue ) + { + vPrintDisplayMessage( &pcPollingSemaphoreTaskError ); + sError = pdTRUE; + } + + /* Clear the variable, then count it back up to the expected value + before releasing the semaphore. Would expect a context switch or + two during this time. */ + for( ulCounter = ( unsigned portLONG ) 0; ulCounter <= ulExpectedValue; ulCounter++ ) + { + *pulSharedVariable = ulCounter; + if( *pulSharedVariable != ulCounter ) + { + if( sError == pdFALSE ) + { + vPrintDisplayMessage( &pcPollingSemaphoreTaskError ); + } + sError = pdTRUE; + } + } + + /* Release the semaphore, and if no errors have occurred increment the check + variable. */ + if( xSemaphoreGive( pxParameters->xSemaphore ) == pdFALSE ) + { + vPrintDisplayMessage( &pcPollingSemaphoreTaskError ); + sError = pdTRUE; + } + + if( sError == pdFALSE ) + { + if( sCheckVariableToUse < semtstNUM_TASKS ) + { + ( sCheckVariables[ sCheckVariableToUse ] )++; + } + } + + /* If we have a block time then we are running at a priority higher + than the idle priority. This task takes a long time to complete + a cycle (deliberately so to test the guarding) so will be starving + out lower priority tasks. Block for some time to allow give lower + priority tasks some processor time. */ + vTaskDelay( pxParameters->xBlockTime * semtstDELAY_FACTOR ); + } + else + { + if( pxParameters->xBlockTime == ( portTickType ) 0 ) + { + /* We have not got the semaphore yet, so no point using the + processor. We are not blocking when attempting to obtain the + semaphore. */ + taskYIELD(); + } + } + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +portBASE_TYPE xAreSemaphoreTasksStillRunning( void ) +{ +static portSHORT sLastCheckVariables[ semtstNUM_TASKS ] = { 0 }; +portBASE_TYPE xTask, xReturn = pdTRUE; + + for( xTask = 0; xTask < semtstNUM_TASKS; xTask++ ) + { + if( sLastCheckVariables[ xTask ] == sCheckVariables[ xTask ] ) + { + xReturn = pdFALSE; + } + + sLastCheckVariables[ xTask ] = sCheckVariables[ xTask ]; + } + + return xReturn; +} + + diff --git a/20080212/Demo/Common/Minimal/AltBlckQ.c b/20080212/Demo/Common/Minimal/AltBlckQ.c new file mode 100644 index 000000000..a9ff76281 --- /dev/null +++ b/20080212/Demo/Common/Minimal/AltBlckQ.c @@ -0,0 +1,309 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + * This is a version of BlockQ.c that uses the alternative (Alt) API. + * + * Creates six tasks that operate on three queues as follows: + * + * The first two tasks send and receive an incrementing number to/from a queue. + * One task acts as a producer and the other as the consumer. The consumer is a + * higher priority than the producer and is set to block on queue reads. The queue + * only has space for one item - as soon as the producer posts a message on the + * queue the consumer will unblock, pre-empt the producer, and remove the item. + * + * The second two tasks work the other way around. Again the queue used only has + * enough space for one item. This time the consumer has a lower priority than the + * producer. The producer will try to post on the queue blocking when the queue is + * full. When the consumer wakes it will remove the item from the queue, causing + * the producer to unblock, pre-empt the consumer, and immediately re-fill the + * queue. + * + * The last two tasks use the same queue producer and consumer functions. This time the queue has + * enough space for lots of items and the tasks operate at the same priority. The + * producer will execute, placing items into the queue. The consumer will start + * executing when either the queue becomes full (causing the producer to block) or + * a context switch occurs (tasks of the same priority will time slice). + * + */ + + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* Demo program include files. */ +#include "AltBlckQ.h" + +#define blckqSTACK_SIZE configMINIMAL_STACK_SIZE +#define blckqNUM_TASK_SETS ( 3 ) + +/* Structure used to pass parameters to the blocking queue tasks. */ +typedef struct BLOCKING_QUEUE_PARAMETERS +{ + xQueueHandle xQueue; /*< The queue to be used by the task. */ + portTickType xBlockTime; /*< The block time to use on queue reads/writes. */ + volatile portSHORT *psCheckVariable; /*< Incremented on each successful cycle to check the task is still running. */ +} xBlockingQueueParameters; + +/* Task function that creates an incrementing number and posts it on a queue. */ +static portTASK_FUNCTION_PROTO( vBlockingQueueProducer, pvParameters ); + +/* Task function that removes the incrementing number from a queue and checks that +it is the expected number. */ +static portTASK_FUNCTION_PROTO( vBlockingQueueConsumer, pvParameters ); + +/* Variables which are incremented each time an item is removed from a queue, and +found to be the expected value. +These are used to check that the tasks are still running. */ +static volatile portSHORT sBlockingConsumerCount[ blckqNUM_TASK_SETS ] = { ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0 }; + +/* Variable which are incremented each time an item is posted on a queue. These +are used to check that the tasks are still running. */ +static volatile portSHORT sBlockingProducerCount[ blckqNUM_TASK_SETS ] = { ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0 }; + +/*-----------------------------------------------------------*/ + +void vStartAltBlockingQueueTasks( unsigned portBASE_TYPE uxPriority ) +{ +xBlockingQueueParameters *pxQueueParameters1, *pxQueueParameters2; +xBlockingQueueParameters *pxQueueParameters3, *pxQueueParameters4; +xBlockingQueueParameters *pxQueueParameters5, *pxQueueParameters6; +const unsigned portBASE_TYPE uxQueueSize1 = 1, uxQueueSize5 = 5; +const portTickType xBlockTime = ( portTickType ) 1000 / portTICK_RATE_MS; +const portTickType xDontBlock = ( portTickType ) 0; + + /* Create the first two tasks as described at the top of the file. */ + + /* First create the structure used to pass parameters to the consumer tasks. */ + pxQueueParameters1 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + + /* Create the queue used by the first two tasks to pass the incrementing number. + Pass a pointer to the queue in the parameter structure. */ + pxQueueParameters1->xQueue = xQueueCreate( uxQueueSize1, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) ); + + /* The consumer is created first so gets a block time as described above. */ + pxQueueParameters1->xBlockTime = xBlockTime; + + /* Pass in the variable that this task is going to increment so we can check it + is still running. */ + pxQueueParameters1->psCheckVariable = &( sBlockingConsumerCount[ 0 ] ); + + /* Create the structure used to pass parameters to the producer task. */ + pxQueueParameters2 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + + /* Pass the queue to this task also, using the parameter structure. */ + pxQueueParameters2->xQueue = pxQueueParameters1->xQueue; + + /* The producer is not going to block - as soon as it posts the consumer will + wake and remove the item so the producer should always have room to post. */ + pxQueueParameters2->xBlockTime = xDontBlock; + + /* Pass in the variable that this task is going to increment so we can check + it is still running. */ + pxQueueParameters2->psCheckVariable = &( sBlockingProducerCount[ 0 ] ); + + + /* Note the producer has a lower priority than the consumer when the tasks are + spawned. */ + xTaskCreate( vBlockingQueueConsumer, ( signed portCHAR * ) "QConsB1", blckqSTACK_SIZE, ( void * ) pxQueueParameters1, uxPriority, NULL ); + xTaskCreate( vBlockingQueueProducer, ( signed portCHAR * ) "QProdB2", blckqSTACK_SIZE, ( void * ) pxQueueParameters2, tskIDLE_PRIORITY, NULL ); + + + + /* Create the second two tasks as described at the top of the file. This uses + the same mechanism but reverses the task priorities. */ + + pxQueueParameters3 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + pxQueueParameters3->xQueue = xQueueCreate( uxQueueSize1, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) ); + pxQueueParameters3->xBlockTime = xDontBlock; + pxQueueParameters3->psCheckVariable = &( sBlockingProducerCount[ 1 ] ); + + pxQueueParameters4 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + pxQueueParameters4->xQueue = pxQueueParameters3->xQueue; + pxQueueParameters4->xBlockTime = xBlockTime; + pxQueueParameters4->psCheckVariable = &( sBlockingConsumerCount[ 1 ] ); + + xTaskCreate( vBlockingQueueConsumer, ( signed portCHAR * ) "QProdB3", blckqSTACK_SIZE, ( void * ) pxQueueParameters3, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vBlockingQueueProducer, ( signed portCHAR * ) "QConsB4", blckqSTACK_SIZE, ( void * ) pxQueueParameters4, uxPriority, NULL ); + + + + /* Create the last two tasks as described above. The mechanism is again just + the same. This time both parameter structures are given a block time. */ + pxQueueParameters5 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + pxQueueParameters5->xQueue = xQueueCreate( uxQueueSize5, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) ); + pxQueueParameters5->xBlockTime = xBlockTime; + pxQueueParameters5->psCheckVariable = &( sBlockingProducerCount[ 2 ] ); + + pxQueueParameters6 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + pxQueueParameters6->xQueue = pxQueueParameters5->xQueue; + pxQueueParameters6->xBlockTime = xBlockTime; + pxQueueParameters6->psCheckVariable = &( sBlockingConsumerCount[ 2 ] ); + + xTaskCreate( vBlockingQueueProducer, ( signed portCHAR * ) "QProdB5", blckqSTACK_SIZE, ( void * ) pxQueueParameters5, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vBlockingQueueConsumer, ( signed portCHAR * ) "QConsB6", blckqSTACK_SIZE, ( void * ) pxQueueParameters6, tskIDLE_PRIORITY, NULL ); +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vBlockingQueueProducer, pvParameters ) +{ +unsigned portSHORT usValue = 0; +xBlockingQueueParameters *pxQueueParameters; +portSHORT sErrorEverOccurred = pdFALSE; + + #ifdef USE_STDIO + void vPrintDisplayMessage( const portCHAR * const * ppcMessageToSend ); + + const portCHAR * const pcTaskStartMsg = "Alt blocking queue producer task started.\r\n"; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + #endif + + pxQueueParameters = ( xBlockingQueueParameters * ) pvParameters; + + for( ;; ) + { + if( xQueueAltSendToBack( pxQueueParameters->xQueue, ( void * ) &usValue, pxQueueParameters->xBlockTime ) != pdPASS ) + { + sErrorEverOccurred = pdTRUE; + } + else + { + /* We have successfully posted a message, so increment the variable + used to check we are still running. */ + if( sErrorEverOccurred == pdFALSE ) + { + ( *pxQueueParameters->psCheckVariable )++; + } + + /* Increment the variable we are going to post next time round. The + consumer will expect the numbers to follow in numerical order. */ + ++usValue; + } + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vBlockingQueueConsumer, pvParameters ) +{ +unsigned portSHORT usData, usExpectedValue = 0; +xBlockingQueueParameters *pxQueueParameters; +portSHORT sErrorEverOccurred = pdFALSE; + + #ifdef USE_STDIO + void vPrintDisplayMessage( const portCHAR * const * ppcMessageToSend ); + + const portCHAR * const pcTaskStartMsg = "Alt blocking queue consumer task started.\r\n"; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + #endif + + pxQueueParameters = ( xBlockingQueueParameters * ) pvParameters; + + for( ;; ) + { + if( xQueueAltReceive( pxQueueParameters->xQueue, &usData, pxQueueParameters->xBlockTime ) == pdPASS ) + { + if( usData != usExpectedValue ) + { + /* Catch-up. */ + usExpectedValue = usData; + + sErrorEverOccurred = pdTRUE; + } + else + { + /* We have successfully received a message, so increment the + variable used to check we are still running. */ + if( sErrorEverOccurred == pdFALSE ) + { + ( *pxQueueParameters->psCheckVariable )++; + } + + /* Increment the value we expect to remove from the queue next time + round. */ + ++usExpectedValue; + } + } + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +portBASE_TYPE xAreAltBlockingQueuesStillRunning( void ) +{ +static portSHORT sLastBlockingConsumerCount[ blckqNUM_TASK_SETS ] = { ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0 }; +static portSHORT sLastBlockingProducerCount[ blckqNUM_TASK_SETS ] = { ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0 }; +portBASE_TYPE xReturn = pdPASS, xTasks; + + /* Not too worried about mutual exclusion on these variables as they are 16 + bits and we are only reading them. We also only care to see if they have + changed or not. + + Loop through each check variable to and return pdFALSE if any are found not + to have changed since the last call. */ + + for( xTasks = 0; xTasks < blckqNUM_TASK_SETS; xTasks++ ) + { + if( sBlockingConsumerCount[ xTasks ] == sLastBlockingConsumerCount[ xTasks ] ) + { + xReturn = pdFALSE; + } + sLastBlockingConsumerCount[ xTasks ] = sBlockingConsumerCount[ xTasks ]; + + + if( sBlockingProducerCount[ xTasks ] == sLastBlockingProducerCount[ xTasks ] ) + { + xReturn = pdFALSE; + } + sLastBlockingProducerCount[ xTasks ] = sBlockingProducerCount[ xTasks ]; + } + + return xReturn; +} + diff --git a/20080212/Demo/Common/Minimal/AltBlock.c b/20080212/Demo/Common/Minimal/AltBlock.c new file mode 100644 index 000000000..56a0b5d89 --- /dev/null +++ b/20080212/Demo/Common/Minimal/AltBlock.c @@ -0,0 +1,517 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + * This is a version of BlockTim.c that uses the light weight API. + * + * This file contains some test scenarios that ensure tasks do not exit queue + * send or receive functions prematurely. A description of the tests is + * included within the code. + */ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* Demo includes. */ +#include "AltBlock.h" + +/* Task priorities. */ +#define bktPRIMARY_PRIORITY ( 3 ) +#define bktSECONDARY_PRIORITY ( 2 ) + +/* Task behaviour. */ +#define bktQUEUE_LENGTH ( 5 ) +#define bktSHORT_WAIT ( ( ( portTickType ) 20 ) / portTICK_RATE_MS ) +#define bktPRIMARY_BLOCK_TIME ( 10 ) +#define bktALLOWABLE_MARGIN ( 12 ) +#define bktTIME_TO_BLOCK ( 175 ) +#define bktDONT_BLOCK ( ( portTickType ) 0 ) +#define bktRUN_INDICATOR ( ( unsigned portBASE_TYPE ) 0x55 ) + +/* The queue on which the tasks block. */ +static xQueueHandle xTestQueue; + +/* Handle to the secondary task is required by the primary task for calls +to vTaskSuspend/Resume(). */ +static xTaskHandle xSecondary; + +/* Used to ensure that tasks are still executing without error. */ +static portBASE_TYPE xPrimaryCycles = 0, xSecondaryCycles = 0; +static portBASE_TYPE xErrorOccurred = pdFALSE; + +/* Provides a simple mechanism for the primary task to know when the +secondary task has executed. */ +static volatile unsigned portBASE_TYPE xRunIndicator; + +/* The two test tasks. Their behaviour is commented within the files. */ +static void vPrimaryBlockTimeTestTask( void *pvParameters ); +static void vSecondaryBlockTimeTestTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +void vCreateAltBlockTimeTasks( void ) +{ + /* Create the queue on which the two tasks block. */ + xTestQueue = xQueueCreate( bktQUEUE_LENGTH, sizeof( portBASE_TYPE ) ); + + /* Create the two test tasks. */ + xTaskCreate( vPrimaryBlockTimeTestTask, ( signed portCHAR * )"FBTest1", configMINIMAL_STACK_SIZE, NULL, bktPRIMARY_PRIORITY, NULL ); + xTaskCreate( vSecondaryBlockTimeTestTask, ( signed portCHAR * )"FBTest2", configMINIMAL_STACK_SIZE, NULL, bktSECONDARY_PRIORITY, &xSecondary ); +} +/*-----------------------------------------------------------*/ + +static void vPrimaryBlockTimeTestTask( void *pvParameters ) +{ +portBASE_TYPE xItem, xData; +portTickType xTimeWhenBlocking; +portTickType xTimeToBlock, xBlockedTime; + + #ifdef USE_STDIO + void vPrintDisplayMessage( const portCHAR * const * ppcMessageToSend ); + + const portCHAR * const pcTaskStartMsg = "Alt primary block time test started.\r\n"; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + #endif + + ( void ) pvParameters; + + for( ;; ) + { + /********************************************************************* + Test 1 + + Simple block time wakeup test on queue receives. */ + for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ ) + { + /* The queue is empty. Attempt to read from the queue using a block + time. When we wake, ensure the delta in time is as expected. */ + xTimeToBlock = bktPRIMARY_BLOCK_TIME << xItem; + + /* A critical section is used to minimise the jitter in the time + measurements. */ + portENTER_CRITICAL(); + { + xTimeWhenBlocking = xTaskGetTickCount(); + + /* We should unblock after xTimeToBlock having not received + anything on the queue. */ + if( xQueueAltReceive( xTestQueue, &xData, xTimeToBlock ) != errQUEUE_EMPTY ) + { + xErrorOccurred = pdTRUE; + } + + /* How long were we blocked for? */ + xBlockedTime = xTaskGetTickCount() - xTimeWhenBlocking; + } + portEXIT_CRITICAL(); + + if( xBlockedTime < xTimeToBlock ) + { + /* Should not have blocked for less than we requested. */ + xErrorOccurred = pdTRUE; + } + + if( xBlockedTime > ( xTimeToBlock + bktALLOWABLE_MARGIN ) ) + { + /* Should not have blocked for longer than we requested, + although we would not necessarily run as soon as we were + unblocked so a margin is allowed. */ + xErrorOccurred = pdTRUE; + } + } + + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + + /********************************************************************* + Test 2 + + Simple block time wakeup test on queue sends. + + First fill the queue. It should be empty so all sends should pass. */ + for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ ) + { + if( xQueueAltSendToBack( xTestQueue, &xItem, bktDONT_BLOCK ) != pdPASS ) + { + xErrorOccurred = pdTRUE; + } + } + + for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ ) + { + /* The queue is full. Attempt to write to the queue using a block + time. When we wake, ensure the delta in time is as expected. */ + xTimeToBlock = bktPRIMARY_BLOCK_TIME << xItem; + + portENTER_CRITICAL(); + { + xTimeWhenBlocking = xTaskGetTickCount(); + + /* We should unblock after xTimeToBlock having not received + anything on the queue. */ + if( xQueueAltSendToBack( xTestQueue, &xItem, xTimeToBlock ) != errQUEUE_FULL ) + { + xErrorOccurred = pdTRUE; + } + + /* How long were we blocked for? */ + xBlockedTime = xTaskGetTickCount() - xTimeWhenBlocking; + } + portEXIT_CRITICAL(); + + if( xBlockedTime < xTimeToBlock ) + { + /* Should not have blocked for less than we requested. */ + xErrorOccurred = pdTRUE; + } + + if( xBlockedTime > ( xTimeToBlock + bktALLOWABLE_MARGIN ) ) + { + /* Should not have blocked for longer than we requested, + although we would not necessarily run as soon as we were + unblocked so a margin is allowed. */ + xErrorOccurred = pdTRUE; + } + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + + /********************************************************************* + Test 3 + + Wake the other task, it will block attempting to post to the queue. + When we read from the queue the other task will wake, but before it + can run we will post to the queue again. When the other task runs it + will find the queue still full, even though it was woken. It should + recognise that its block time has not expired and return to block for + the remains of its block time. + + Wake the other task so it blocks attempting to post to the already + full queue. */ + xRunIndicator = 0; + vTaskResume( xSecondary ); + + /* We need to wait a little to ensure the other task executes. */ + while( xRunIndicator != bktRUN_INDICATOR ) + { + /* The other task has not yet executed. */ + vTaskDelay( bktSHORT_WAIT ); + } + /* Make sure the other task is blocked on the queue. */ + vTaskDelay( bktSHORT_WAIT ); + xRunIndicator = 0; + + for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ ) + { + /* Now when we make space on the queue the other task should wake + but not execute as this task has higher priority. */ + if( xQueueAltReceive( xTestQueue, &xData, bktDONT_BLOCK ) != pdPASS ) + { + xErrorOccurred = pdTRUE; + } + + /* Now fill the queue again before the other task gets a chance to + execute. If the other task had executed we would find the queue + full ourselves, and the other task have set xRunIndicator. */ + if( xQueueAltSendToBack( xTestQueue, &xItem, bktDONT_BLOCK ) != pdPASS ) + { + xErrorOccurred = pdTRUE; + } + + if( xRunIndicator == bktRUN_INDICATOR ) + { + /* The other task should not have executed. */ + xErrorOccurred = pdTRUE; + } + + /* Raise the priority of the other task so it executes and blocks + on the queue again. */ + vTaskPrioritySet( xSecondary, bktPRIMARY_PRIORITY + 2 ); + + /* The other task should now have re-blocked without exiting the + queue function. */ + if( xRunIndicator == bktRUN_INDICATOR ) + { + /* The other task should not have executed outside of the + queue function. */ + xErrorOccurred = pdTRUE; + } + + /* Set the priority back down. */ + vTaskPrioritySet( xSecondary, bktSECONDARY_PRIORITY ); + } + + /* Let the other task timeout. When it unblockes it will check that it + unblocked at the correct time, then suspend itself. */ + while( xRunIndicator != bktRUN_INDICATOR ) + { + vTaskDelay( bktSHORT_WAIT ); + } + vTaskDelay( bktSHORT_WAIT ); + xRunIndicator = 0; + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /********************************************************************* + Test 4 + + As per test 3 - but with the send and receive the other way around. + The other task blocks attempting to read from the queue. + + Empty the queue. We should find that it is full. */ + for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ ) + { + if( xQueueAltReceive( xTestQueue, &xData, bktDONT_BLOCK ) != pdPASS ) + { + xErrorOccurred = pdTRUE; + } + } + + /* Wake the other task so it blocks attempting to read from the + already empty queue. */ + vTaskResume( xSecondary ); + + /* We need to wait a little to ensure the other task executes. */ + while( xRunIndicator != bktRUN_INDICATOR ) + { + vTaskDelay( bktSHORT_WAIT ); + } + vTaskDelay( bktSHORT_WAIT ); + xRunIndicator = 0; + + for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ ) + { + /* Now when we place an item on the queue the other task should + wake but not execute as this task has higher priority. */ + if( xQueueAltSendToBack( xTestQueue, &xItem, bktDONT_BLOCK ) != pdPASS ) + { + xErrorOccurred = pdTRUE; + } + + /* Now empty the queue again before the other task gets a chance to + execute. If the other task had executed we would find the queue + empty ourselves, and the other task would be suspended. */ + if( xQueueAltReceive( xTestQueue, &xData, bktDONT_BLOCK ) != pdPASS ) + { + xErrorOccurred = pdTRUE; + } + + if( xRunIndicator == bktRUN_INDICATOR ) + { + /* The other task should not have executed. */ + xErrorOccurred = pdTRUE; + } + + /* Raise the priority of the other task so it executes and blocks + on the queue again. */ + vTaskPrioritySet( xSecondary, bktPRIMARY_PRIORITY + 2 ); + + /* The other task should now have re-blocked without exiting the + queue function. */ + if( xRunIndicator == bktRUN_INDICATOR ) + { + /* The other task should not have executed outside of the + queue function. */ + xErrorOccurred = pdTRUE; + } + vTaskPrioritySet( xSecondary, bktSECONDARY_PRIORITY ); + } + + /* Let the other task timeout. When it unblockes it will check that it + unblocked at the correct time, then suspend itself. */ + while( xRunIndicator != bktRUN_INDICATOR ) + { + vTaskDelay( bktSHORT_WAIT ); + } + vTaskDelay( bktSHORT_WAIT ); + + xPrimaryCycles++; + } +} +/*-----------------------------------------------------------*/ + +static void vSecondaryBlockTimeTestTask( void *pvParameters ) +{ +portTickType xTimeWhenBlocking, xBlockedTime; +portBASE_TYPE xData; + + #ifdef USE_STDIO + void vPrintDisplayMessage( const portCHAR * const * ppcMessageToSend ); + + const portCHAR * const pcTaskStartMsg = "Alt secondary block time test started.\r\n"; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + #endif + + ( void ) pvParameters; + + for( ;; ) + { + /********************************************************************* + Test 1 and 2 + + This task does does not participate in these tests. */ + vTaskSuspend( NULL ); + + /********************************************************************* + Test 3 + + The first thing we do is attempt to read from the queue. It should be + full so we block. Note the time before we block so we can check the + wake time is as per that expected. */ + portENTER_CRITICAL(); + { + xTimeWhenBlocking = xTaskGetTickCount(); + + /* We should unblock after bktTIME_TO_BLOCK having not received + anything on the queue. */ + xData = 0; + xRunIndicator = bktRUN_INDICATOR; + if( xQueueAltSendToBack( xTestQueue, &xData, bktTIME_TO_BLOCK ) != errQUEUE_FULL ) + { + xErrorOccurred = pdTRUE; + } + + /* How long were we inside the send function? */ + xBlockedTime = xTaskGetTickCount() - xTimeWhenBlocking; + } + portEXIT_CRITICAL(); + + /* We should not have blocked for less time than bktTIME_TO_BLOCK. */ + if( xBlockedTime < bktTIME_TO_BLOCK ) + { + xErrorOccurred = pdTRUE; + } + + /* We should of not blocked for much longer than bktALLOWABLE_MARGIN + either. A margin is permitted as we would not necessarily run as + soon as we unblocked. */ + if( xBlockedTime > ( bktTIME_TO_BLOCK + bktALLOWABLE_MARGIN ) ) + { + xErrorOccurred = pdTRUE; + } + + /* Suspend ready for test 3. */ + xRunIndicator = bktRUN_INDICATOR; + vTaskSuspend( NULL ); + + /********************************************************************* + Test 4 + + As per test three, but with the send and receive reversed. */ + portENTER_CRITICAL(); + { + xTimeWhenBlocking = xTaskGetTickCount(); + + /* We should unblock after bktTIME_TO_BLOCK having not received + anything on the queue. */ + xRunIndicator = bktRUN_INDICATOR; + if( xQueueAltReceive( xTestQueue, &xData, bktTIME_TO_BLOCK ) != errQUEUE_EMPTY ) + { + xErrorOccurred = pdTRUE; + } + + xBlockedTime = xTaskGetTickCount() - xTimeWhenBlocking; + } + portEXIT_CRITICAL(); + + /* We should not have blocked for less time than bktTIME_TO_BLOCK. */ + if( xBlockedTime < bktTIME_TO_BLOCK ) + { + xErrorOccurred = pdTRUE; + } + + /* We should of not blocked for much longer than bktALLOWABLE_MARGIN + either. A margin is permitted as we would not necessarily run as soon + as we unblocked. */ + if( xBlockedTime > ( bktTIME_TO_BLOCK + bktALLOWABLE_MARGIN ) ) + { + xErrorOccurred = pdTRUE; + } + + xRunIndicator = bktRUN_INDICATOR; + + xSecondaryCycles++; + } +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xAreAltBlockTimeTestTasksStillRunning( void ) +{ +static portBASE_TYPE xLastPrimaryCycleCount = 0, xLastSecondaryCycleCount = 0; +portBASE_TYPE xReturn = pdPASS; + + /* Have both tasks performed at least one cycle since this function was + last called? */ + if( xPrimaryCycles == xLastPrimaryCycleCount ) + { + xReturn = pdFAIL; + } + + if( xSecondaryCycles == xLastSecondaryCycleCount ) + { + xReturn = pdFAIL; + } + + if( xErrorOccurred == pdTRUE ) + { + xReturn = pdFAIL; + } + + xLastSecondaryCycleCount = xSecondaryCycles; + xLastPrimaryCycleCount = xPrimaryCycles; + + return xReturn; +} diff --git a/20080212/Demo/Common/Minimal/AltPollQ.c b/20080212/Demo/Common/Minimal/AltPollQ.c new file mode 100644 index 000000000..f6cda8fc2 --- /dev/null +++ b/20080212/Demo/Common/Minimal/AltPollQ.c @@ -0,0 +1,243 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + * This is a version of PollQ.c that uses the alternative (Alt) API. + * + * Creates two tasks that communicate over a single queue. One task acts as a + * producer, the other a consumer. + * + * The producer loops for three iteration, posting an incrementing number onto the + * queue each cycle. It then delays for a fixed period before doing exactly the + * same again. + * + * The consumer loops emptying the queue. Each item removed from the queue is + * checked to ensure it contains the expected value. When the queue is empty it + * blocks for a fixed period, then does the same again. + * + * All queue access is performed without blocking. The consumer completely empties + * the queue each time it runs so the producer should never find the queue full. + * + * An error is flagged if the consumer obtains an unexpected value or the producer + * find the queue is full. + */ + +/* +Changes from V2.0.0 + + + Delay periods are now specified using variables and constants of + portTickType rather than unsigned portLONG. +*/ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* Demo program include files. */ +#include "AltPollQ.h" + +#define pollqSTACK_SIZE configMINIMAL_STACK_SIZE +#define pollqQUEUE_SIZE ( 10 ) +#define pollqPRODUCER_DELAY ( ( portTickType ) 200 / portTICK_RATE_MS ) +#define pollqCONSUMER_DELAY ( pollqPRODUCER_DELAY - ( portTickType ) ( 20 / portTICK_RATE_MS ) ) +#define pollqNO_DELAY ( ( portTickType ) 0 ) +#define pollqVALUES_TO_PRODUCE ( ( signed portBASE_TYPE ) 3 ) +#define pollqINITIAL_VALUE ( ( signed portBASE_TYPE ) 0 ) + +/* The task that posts the incrementing number onto the queue. */ +static portTASK_FUNCTION_PROTO( vPolledQueueProducer, pvParameters ); + +/* The task that empties the queue. */ +static portTASK_FUNCTION_PROTO( vPolledQueueConsumer, pvParameters ); + +/* Variables that are used to check that the tasks are still running with no +errors. */ +static volatile signed portBASE_TYPE xPollingConsumerCount = pollqINITIAL_VALUE, xPollingProducerCount = pollqINITIAL_VALUE; + +/*-----------------------------------------------------------*/ + +void vStartAltPolledQueueTasks( unsigned portBASE_TYPE uxPriority ) +{ +static xQueueHandle xPolledQueue; + + /* Create the queue used by the producer and consumer. */ + xPolledQueue = xQueueCreate( pollqQUEUE_SIZE, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) ); + + /* Spawn the producer and consumer. */ + xTaskCreate( vPolledQueueConsumer, ( signed portCHAR * ) "QConsNB", pollqSTACK_SIZE, ( void * ) &xPolledQueue, uxPriority, ( xTaskHandle * ) NULL ); + xTaskCreate( vPolledQueueProducer, ( signed portCHAR * ) "QProdNB", pollqSTACK_SIZE, ( void * ) &xPolledQueue, uxPriority, ( xTaskHandle * ) NULL ); +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vPolledQueueProducer, pvParameters ) +{ +unsigned portSHORT usValue = ( unsigned portSHORT ) 0; +signed portBASE_TYPE xError = pdFALSE, xLoop; + + #ifdef USE_STDIO + void vPrintDisplayMessage( const portCHAR * const * ppcMessageToSend ); + + const portCHAR * const pcTaskStartMsg = "Alt polling queue producer task started.\r\n"; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + #endif + + for( ;; ) + { + for( xLoop = 0; xLoop < pollqVALUES_TO_PRODUCE; xLoop++ ) + { + /* Send an incrementing number on the queue without blocking. */ + if( xQueueAltSendToBack( *( ( xQueueHandle * ) pvParameters ), ( void * ) &usValue, pollqNO_DELAY ) != pdPASS ) + { + /* We should never find the queue full so if we get here there + has been an error. */ + xError = pdTRUE; + } + else + { + if( xError == pdFALSE ) + { + /* If an error has ever been recorded we stop incrementing the + check variable. */ + portENTER_CRITICAL(); + xPollingProducerCount++; + portEXIT_CRITICAL(); + } + + /* Update the value we are going to post next time around. */ + usValue++; + } + } + + /* Wait before we start posting again to ensure the consumer runs and + empties the queue. */ + vTaskDelay( pollqPRODUCER_DELAY ); + } +} /*lint !e818 Function prototype must conform to API. */ +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vPolledQueueConsumer, pvParameters ) +{ +unsigned portSHORT usData, usExpectedValue = ( unsigned portSHORT ) 0; +signed portBASE_TYPE xError = pdFALSE; + + #ifdef USE_STDIO + void vPrintDisplayMessage( const portCHAR * const * ppcMessageToSend ); + + const portCHAR * const pcTaskStartMsg = "Alt blocking queue consumer task started.\r\n"; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + #endif + + for( ;; ) + { + /* Loop until the queue is empty. */ + while( uxQueueMessagesWaiting( *( ( xQueueHandle * ) pvParameters ) ) ) + { + if( xQueueAltReceive( *( ( xQueueHandle * ) pvParameters ), &usData, pollqNO_DELAY ) == pdPASS ) + { + if( usData != usExpectedValue ) + { + /* This is not what we expected to receive so an error has + occurred. */ + xError = pdTRUE; + + /* Catch-up to the value we received so our next expected + value should again be correct. */ + usExpectedValue = usData; + } + else + { + if( xError == pdFALSE ) + { + /* Only increment the check variable if no errors have + occurred. */ + portENTER_CRITICAL(); + xPollingConsumerCount++; + portEXIT_CRITICAL(); + } + } + + /* Next time round we would expect the number to be one higher. */ + usExpectedValue++; + } + } + + /* Now the queue is empty we block, allowing the producer to place more + items in the queue. */ + vTaskDelay( pollqCONSUMER_DELAY ); + } +} /*lint !e818 Function prototype must conform to API. */ +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running with no errors. */ +portBASE_TYPE xAreAltPollingQueuesStillRunning( void ) +{ +portBASE_TYPE xReturn; + + /* Check both the consumer and producer poll count to check they have both + been changed since out last trip round. We do not need a critical section + around the check variables as this is called from a higher priority than + the other tasks that access the same variables. */ + if( ( xPollingConsumerCount == pollqINITIAL_VALUE ) || + ( xPollingProducerCount == pollqINITIAL_VALUE ) + ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + /* Set the check variables back down so we know if they have been + incremented the next time around. */ + xPollingConsumerCount = pollqINITIAL_VALUE; + xPollingProducerCount = pollqINITIAL_VALUE; + + return xReturn; +} diff --git a/20080212/Demo/Common/Minimal/AltQTest.c b/20080212/Demo/Common/Minimal/AltQTest.c new file mode 100644 index 000000000..fd6771c1f --- /dev/null +++ b/20080212/Demo/Common/Minimal/AltQTest.c @@ -0,0 +1,548 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +/* + * This file implements the same demo and test as GenQTest.c, but uses the + * light weight API in place of the fully featured API. + * + * See the comments at the top of GenQTest.c for a description. + */ + + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "semphr.h" + +/* Demo program include files. */ +#include "AltQTest.h" + +#define genqQUEUE_LENGTH ( 5 ) +#define genqNO_BLOCK ( 0 ) + +#define genqMUTEX_LOW_PRIORITY ( tskIDLE_PRIORITY ) +#define genqMUTEX_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define genqMUTEX_MEDIUM_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define genqMUTEX_HIGH_PRIORITY ( tskIDLE_PRIORITY + 3 ) + +/*-----------------------------------------------------------*/ + +/* + * Tests the behaviour of the xQueueAltSendToFront() and xQueueAltSendToBack() + * macros by using both to fill a queue, then reading from the queue to + * check the resultant queue order is as expected. Queue data is also + * peeked. + */ +static void prvSendFrontAndBackTest( void *pvParameters ); + +/* + * The following three tasks are used to demonstrate the mutex behaviour. + * Each task is given a different priority to demonstrate the priority + * inheritance mechanism. + * + * The low priority task obtains a mutex. After this a high priority task + * attempts to obtain the same mutex, causing its priority to be inherited + * by the low priority task. The task with the inherited high priority then + * resumes a medium priority task to ensure it is not blocked by the medium + * priority task while it holds the inherited high priority. Once the mutex + * is returned the task with the inherited priority returns to its original + * low priority, and is therefore immediately preempted by first the high + * priority task and then the medium prioroity task before it can continue. + */ +static void prvLowPriorityMutexTask( void *pvParameters ); +static void prvMediumPriorityMutexTask( void *pvParameters ); +static void prvHighPriorityMutexTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* Flag that will be latched to pdTRUE should any unexpected behaviour be +detected in any of the tasks. */ +static portBASE_TYPE xErrorDetected = pdFALSE; + +/* Counters that are incremented on each cycle of a test. This is used to +detect a stalled task - a test that is no longer running. */ +static volatile unsigned portLONG ulLoopCounter = 0; +static volatile unsigned portLONG ulLoopCounter2 = 0; + +/* The variable that is guarded by the mutex in the mutex demo tasks. */ +static volatile unsigned portLONG ulGuardedVariable = 0; + +/* Handles used in the mutext test to suspend and resume the high and medium +priority mutex test tasks. */ +static xTaskHandle xHighPriorityMutexTask, xMediumPriorityMutexTask; + +/*-----------------------------------------------------------*/ + +void vStartAltGenericQueueTasks( unsigned portBASE_TYPE uxPriority ) +{ +xQueueHandle xQueue; +xSemaphoreHandle xMutex; + + /* Create the queue that we are going to use for the + prvSendFrontAndBackTest demo. */ + xQueue = xQueueCreate( genqQUEUE_LENGTH, sizeof( unsigned portLONG ) ); + + /* Create the demo task and pass it the queue just created. We are + passing the queue handle by value so it does not matter that it is + declared on the stack here. */ + xTaskCreate( prvSendFrontAndBackTest, ( signed portCHAR * ) "FGenQ", configMINIMAL_STACK_SIZE, ( void * ) xQueue, uxPriority, NULL ); + + /* Create the mutex used by the prvMutexTest task. */ + xMutex = xSemaphoreCreateMutex(); + + /* Create the mutex demo tasks and pass it the mutex just created. We are + passing the mutex handle by value so it does not matter that it is declared + on the stack here. */ + xTaskCreate( prvLowPriorityMutexTask, ( signed portCHAR * ) "FMuLow", configMINIMAL_STACK_SIZE, ( void * ) xMutex, genqMUTEX_LOW_PRIORITY, NULL ); + xTaskCreate( prvMediumPriorityMutexTask, ( signed portCHAR * ) "FMuMed", configMINIMAL_STACK_SIZE, NULL, genqMUTEX_MEDIUM_PRIORITY, &xMediumPriorityMutexTask ); + xTaskCreate( prvHighPriorityMutexTask, ( signed portCHAR * ) "FMuHigh", configMINIMAL_STACK_SIZE, ( void * ) xMutex, genqMUTEX_HIGH_PRIORITY, &xHighPriorityMutexTask ); +} +/*-----------------------------------------------------------*/ + +static void prvSendFrontAndBackTest( void *pvParameters ) +{ +unsigned portLONG ulData, ulData2; +xQueueHandle xQueue; + + #ifdef USE_STDIO + void vPrintDisplayMessage( const portCHAR * const * ppcMessageToSend ); + + const portCHAR * const pcTaskStartMsg = "Alt queue SendToFront/SendToBack/Peek test started.\r\n"; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + #endif + + xQueue = ( xQueueHandle ) pvParameters; + + for( ;; ) + { + /* The queue is empty, so sending an item to the back of the queue + should have the same efect as sending it to the front of the queue. + + First send to the front and check everything is as expected. */ + xQueueAltSendToFront( xQueue, ( void * ) &ulLoopCounter, genqNO_BLOCK ); + + if( uxQueueMessagesWaiting( xQueue ) != 1 ) + { + xErrorDetected = pdTRUE; + } + + if( xQueueAltReceive( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + /* The data we sent to the queue should equal the data we just received + from the queue. */ + if( ulLoopCounter != ulData ) + { + xErrorDetected = pdTRUE; + } + + /* Then do the same, sending the data to the back, checking everything + is as expected. */ + if( uxQueueMessagesWaiting( xQueue ) != 0 ) + { + xErrorDetected = pdTRUE; + } + + xQueueAltSendToBack( xQueue, ( void * ) &ulLoopCounter, genqNO_BLOCK ); + + if( uxQueueMessagesWaiting( xQueue ) != 1 ) + { + xErrorDetected = pdTRUE; + } + + if( xQueueAltReceive( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + if( uxQueueMessagesWaiting( xQueue ) != 0 ) + { + xErrorDetected = pdTRUE; + } + + /* The data we sent to the queue should equal the data we just received + from the queue. */ + if( ulLoopCounter != ulData ) + { + xErrorDetected = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + + + /* Place 2, 3, 4 into the queue, adding items to the back of the queue. */ + for( ulData = 2; ulData < 5; ulData++ ) + { + xQueueAltSendToBack( xQueue, ( void * ) &ulData, genqNO_BLOCK ); + } + + /* Now the order in the queue should be 2, 3, 4, with 2 being the first + thing to be read out. Now add 1 then 0 to the front of the queue. */ + if( uxQueueMessagesWaiting( xQueue ) != 3 ) + { + xErrorDetected = pdTRUE; + } + ulData = 1; + xQueueAltSendToFront( xQueue, ( void * ) &ulData, genqNO_BLOCK ); + ulData = 0; + xQueueAltSendToFront( xQueue, ( void * ) &ulData, genqNO_BLOCK ); + + /* Now the queue should be full, and when we read the data out we + should receive 0, 1, 2, 3, 4. */ + if( uxQueueMessagesWaiting( xQueue ) != 5 ) + { + xErrorDetected = pdTRUE; + } + + if( xQueueAltSendToFront( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != errQUEUE_FULL ) + { + xErrorDetected = pdTRUE; + } + + if( xQueueAltSendToBack( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != errQUEUE_FULL ) + { + xErrorDetected = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* Check the data we read out is in the expected order. */ + for( ulData = 0; ulData < genqQUEUE_LENGTH; ulData++ ) + { + /* Try peeking the data first. */ + if( xQueueAltPeek( xQueue, &ulData2, genqNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + if( ulData != ulData2 ) + { + xErrorDetected = pdTRUE; + } + + + /* Now try receiving the data for real. The value should be the + same. Clobber the value first so we know we really received it. */ + ulData2 = ~ulData2; + if( xQueueAltReceive( xQueue, &ulData2, genqNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + if( ulData != ulData2 ) + { + xErrorDetected = pdTRUE; + } + } + + /* The queue should now be empty again. */ + if( uxQueueMessagesWaiting( xQueue ) != 0 ) + { + xErrorDetected = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + + /* Our queue is empty once more, add 10, 11 to the back. */ + ulData = 10; + if( xQueueAltSendToBack( xQueue, &ulData, genqNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + ulData = 11; + if( xQueueAltSendToBack( xQueue, &ulData, genqNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + if( uxQueueMessagesWaiting( xQueue ) != 2 ) + { + xErrorDetected = pdTRUE; + } + + /* Now we should have 10, 11 in the queue. Add 7, 8, 9 to the + front. */ + for( ulData = 9; ulData >= 7; ulData-- ) + { + if( xQueueAltSendToFront( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + } + + /* Now check that the queue is full, and that receiving data provides + the expected sequence of 7, 8, 9, 10, 11. */ + if( uxQueueMessagesWaiting( xQueue ) != 5 ) + { + xErrorDetected = pdTRUE; + } + + if( xQueueAltSendToFront( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != errQUEUE_FULL ) + { + xErrorDetected = pdTRUE; + } + + if( xQueueAltSendToBack( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != errQUEUE_FULL ) + { + xErrorDetected = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* Check the data we read out is in the expected order. */ + for( ulData = 7; ulData < ( 7 + genqQUEUE_LENGTH ); ulData++ ) + { + if( xQueueAltReceive( xQueue, &ulData2, genqNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + if( ulData != ulData2 ) + { + xErrorDetected = pdTRUE; + } + } + + if( uxQueueMessagesWaiting( xQueue ) != 0 ) + { + xErrorDetected = pdTRUE; + } + + ulLoopCounter++; + } +} +/*-----------------------------------------------------------*/ + +static void prvLowPriorityMutexTask( void *pvParameters ) +{ +xSemaphoreHandle xMutex = ( xSemaphoreHandle ) pvParameters; + + #ifdef USE_STDIO + void vPrintDisplayMessage( const portCHAR * const * ppcMessageToSend ); + + const portCHAR * const pcTaskStartMsg = "Fast mutex with priority inheritance test started.\r\n"; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + #endif + + ( void ) pvParameters; + + + for( ;; ) + { + /* Take the mutex. It should be available now. */ + if( xSemaphoreAltTake( xMutex, genqNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + /* Set our guarded variable to a known start value. */ + ulGuardedVariable = 0; + + /* Our priority should be as per that assigned when the task was + created. */ + if( uxTaskPriorityGet( NULL ) != genqMUTEX_LOW_PRIORITY ) + { + xErrorDetected = pdTRUE; + } + + /* Now unsuspend the high priority task. This will attempt to take the + mutex, and block when it finds it cannot obtain it. */ + vTaskResume( xHighPriorityMutexTask ); + + /* We should now have inherited the prioritoy of the high priority task, + as by now it will have attempted to get the mutex. */ + if( uxTaskPriorityGet( NULL ) != genqMUTEX_HIGH_PRIORITY ) + { + xErrorDetected = pdTRUE; + } + + /* We can attempt to set our priority to the test priority - between the + idle priority and the medium/high test priorities, but our actual + prioroity should remain at the high priority. */ + vTaskPrioritySet( NULL, genqMUTEX_TEST_PRIORITY ); + if( uxTaskPriorityGet( NULL ) != genqMUTEX_HIGH_PRIORITY ) + { + xErrorDetected = pdTRUE; + } + + /* Now unsuspend the medium priority task. This should not run as our + inherited priority is above that of the medium priority task. */ + vTaskResume( xMediumPriorityMutexTask ); + + /* If the did run then it will have incremented our guarded variable. */ + if( ulGuardedVariable != 0 ) + { + xErrorDetected = pdTRUE; + } + + /* When we give back the semaphore our priority should be disinherited + back to the priority to which we attempted to set ourselves. This means + that when the high priority task next blocks, the medium priority task + should execute and increment the guarded variable. When we next run + both the high and medium priority tasks will have been suspended again. */ + if( xSemaphoreAltGive( xMutex ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + /* Check that the guarded variable did indeed increment... */ + if( ulGuardedVariable != 1 ) + { + xErrorDetected = pdTRUE; + } + + /* ... and that our priority has been disinherited to + genqMUTEX_TEST_PRIORITY. */ + if( uxTaskPriorityGet( NULL ) != genqMUTEX_TEST_PRIORITY ) + { + xErrorDetected = pdTRUE; + } + + /* Set our priority back to our original priority ready for the next + loop around this test. */ + vTaskPrioritySet( NULL, genqMUTEX_LOW_PRIORITY ); + + /* Just to show we are still running. */ + ulLoopCounter2++; + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + } +} +/*-----------------------------------------------------------*/ + +static void prvMediumPriorityMutexTask( void *pvParameters ) +{ + ( void ) pvParameters; + + for( ;; ) + { + /* The medium priority task starts by suspending itself. The low + priority task will unsuspend this task when required. */ + vTaskSuspend( NULL ); + + /* When this task unsuspends all it does is increment the guarded + variable, this is so the low priority task knows that it has + executed. */ + ulGuardedVariable++; + } +} +/*-----------------------------------------------------------*/ + +static void prvHighPriorityMutexTask( void *pvParameters ) +{ +xSemaphoreHandle xMutex = ( xSemaphoreHandle ) pvParameters; + + ( void ) pvParameters; + + for( ;; ) + { + /* The high priority task starts by suspending itself. The low + priority task will unsuspend this task when required. */ + vTaskSuspend( NULL ); + + /* When this task unsuspends all it does is attempt to obtain + the mutex. It should find the mutex is not available so a + block time is specified. */ + if( xSemaphoreAltTake( xMutex, portMAX_DELAY ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + /* When we eventually obtain the mutex we just give it back then + return to suspend ready for the next test. */ + if( xSemaphoreAltGive( xMutex ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +portBASE_TYPE xAreAltGenericQueueTasksStillRunning( void ) +{ +static unsigned portLONG ulLastLoopCounter = 0, ulLastLoopCounter2 = 0; + + /* If the demo task is still running then we expect the loopcounters to + have incremented since this function was last called. */ + if( ulLastLoopCounter == ulLoopCounter ) + { + xErrorDetected = pdTRUE; + } + + if( ulLastLoopCounter2 == ulLoopCounter2 ) + { + xErrorDetected = pdTRUE; + } + + ulLastLoopCounter = ulLoopCounter; + ulLastLoopCounter2 = ulLoopCounter2; + + /* Errors detected in the task itself will have latched xErrorDetected + to true. */ + + return !xErrorDetected; +} + + diff --git a/20080212/Demo/Common/Minimal/BlockQ.c b/20080212/Demo/Common/Minimal/BlockQ.c new file mode 100644 index 000000000..bd6872f56 --- /dev/null +++ b/20080212/Demo/Common/Minimal/BlockQ.c @@ -0,0 +1,297 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + * Creates six tasks that operate on three queues as follows: + * + * The first two tasks send and receive an incrementing number to/from a queue. + * One task acts as a producer and the other as the consumer. The consumer is a + * higher priority than the producer and is set to block on queue reads. The queue + * only has space for one item - as soon as the producer posts a message on the + * queue the consumer will unblock, pre-empt the producer, and remove the item. + * + * The second two tasks work the other way around. Again the queue used only has + * enough space for one item. This time the consumer has a lower priority than the + * producer. The producer will try to post on the queue blocking when the queue is + * full. When the consumer wakes it will remove the item from the queue, causing + * the producer to unblock, pre-empt the consumer, and immediately re-fill the + * queue. + * + * The last two tasks use the same queue producer and consumer functions. This time the queue has + * enough space for lots of items and the tasks operate at the same priority. The + * producer will execute, placing items into the queue. The consumer will start + * executing when either the queue becomes full (causing the producer to block) or + * a context switch occurs (tasks of the same priority will time slice). + * + */ + +/* + +Changes from V4.1.1 + + + The second set of tasks were created the wrong way around. This has been + corrected. +*/ + + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* Demo program include files. */ +#include "BlockQ.h" + +#define blckqSTACK_SIZE configMINIMAL_STACK_SIZE +#define blckqNUM_TASK_SETS ( 3 ) + +/* Structure used to pass parameters to the blocking queue tasks. */ +typedef struct BLOCKING_QUEUE_PARAMETERS +{ + xQueueHandle xQueue; /*< The queue to be used by the task. */ + portTickType xBlockTime; /*< The block time to use on queue reads/writes. */ + volatile portSHORT *psCheckVariable; /*< Incremented on each successful cycle to check the task is still running. */ +} xBlockingQueueParameters; + +/* Task function that creates an incrementing number and posts it on a queue. */ +static portTASK_FUNCTION_PROTO( vBlockingQueueProducer, pvParameters ); + +/* Task function that removes the incrementing number from a queue and checks that +it is the expected number. */ +static portTASK_FUNCTION_PROTO( vBlockingQueueConsumer, pvParameters ); + +/* Variables which are incremented each time an item is removed from a queue, and +found to be the expected value. +These are used to check that the tasks are still running. */ +static volatile portSHORT sBlockingConsumerCount[ blckqNUM_TASK_SETS ] = { ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0 }; + +/* Variable which are incremented each time an item is posted on a queue. These +are used to check that the tasks are still running. */ +static volatile portSHORT sBlockingProducerCount[ blckqNUM_TASK_SETS ] = { ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0 }; + +/*-----------------------------------------------------------*/ + +void vStartBlockingQueueTasks( unsigned portBASE_TYPE uxPriority ) +{ +xBlockingQueueParameters *pxQueueParameters1, *pxQueueParameters2; +xBlockingQueueParameters *pxQueueParameters3, *pxQueueParameters4; +xBlockingQueueParameters *pxQueueParameters5, *pxQueueParameters6; +const unsigned portBASE_TYPE uxQueueSize1 = 1, uxQueueSize5 = 5; +const portTickType xBlockTime = ( portTickType ) 1000 / portTICK_RATE_MS; +const portTickType xDontBlock = ( portTickType ) 0; + + /* Create the first two tasks as described at the top of the file. */ + + /* First create the structure used to pass parameters to the consumer tasks. */ + pxQueueParameters1 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + + /* Create the queue used by the first two tasks to pass the incrementing number. + Pass a pointer to the queue in the parameter structure. */ + pxQueueParameters1->xQueue = xQueueCreate( uxQueueSize1, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) ); + + /* The consumer is created first so gets a block time as described above. */ + pxQueueParameters1->xBlockTime = xBlockTime; + + /* Pass in the variable that this task is going to increment so we can check it + is still running. */ + pxQueueParameters1->psCheckVariable = &( sBlockingConsumerCount[ 0 ] ); + + /* Create the structure used to pass parameters to the producer task. */ + pxQueueParameters2 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + + /* Pass the queue to this task also, using the parameter structure. */ + pxQueueParameters2->xQueue = pxQueueParameters1->xQueue; + + /* The producer is not going to block - as soon as it posts the consumer will + wake and remove the item so the producer should always have room to post. */ + pxQueueParameters2->xBlockTime = xDontBlock; + + /* Pass in the variable that this task is going to increment so we can check + it is still running. */ + pxQueueParameters2->psCheckVariable = &( sBlockingProducerCount[ 0 ] ); + + + /* Note the producer has a lower priority than the consumer when the tasks are + spawned. */ + xTaskCreate( vBlockingQueueConsumer, ( signed portCHAR * ) "QConsB1", blckqSTACK_SIZE, ( void * ) pxQueueParameters1, uxPriority, NULL ); + xTaskCreate( vBlockingQueueProducer, ( signed portCHAR * ) "QProdB2", blckqSTACK_SIZE, ( void * ) pxQueueParameters2, tskIDLE_PRIORITY, NULL ); + + + + /* Create the second two tasks as described at the top of the file. This uses + the same mechanism but reverses the task priorities. */ + + pxQueueParameters3 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + pxQueueParameters3->xQueue = xQueueCreate( uxQueueSize1, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) ); + pxQueueParameters3->xBlockTime = xDontBlock; + pxQueueParameters3->psCheckVariable = &( sBlockingProducerCount[ 1 ] ); + + pxQueueParameters4 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + pxQueueParameters4->xQueue = pxQueueParameters3->xQueue; + pxQueueParameters4->xBlockTime = xBlockTime; + pxQueueParameters4->psCheckVariable = &( sBlockingConsumerCount[ 1 ] ); + + xTaskCreate( vBlockingQueueConsumer, ( signed portCHAR * ) "QProdB3", blckqSTACK_SIZE, ( void * ) pxQueueParameters3, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vBlockingQueueProducer, ( signed portCHAR * ) "QConsB4", blckqSTACK_SIZE, ( void * ) pxQueueParameters4, uxPriority, NULL ); + + + + /* Create the last two tasks as described above. The mechanism is again just + the same. This time both parameter structures are given a block time. */ + pxQueueParameters5 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + pxQueueParameters5->xQueue = xQueueCreate( uxQueueSize5, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) ); + pxQueueParameters5->xBlockTime = xBlockTime; + pxQueueParameters5->psCheckVariable = &( sBlockingProducerCount[ 2 ] ); + + pxQueueParameters6 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); + pxQueueParameters6->xQueue = pxQueueParameters5->xQueue; + pxQueueParameters6->xBlockTime = xBlockTime; + pxQueueParameters6->psCheckVariable = &( sBlockingConsumerCount[ 2 ] ); + + xTaskCreate( vBlockingQueueProducer, ( signed portCHAR * ) "QProdB5", blckqSTACK_SIZE, ( void * ) pxQueueParameters5, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vBlockingQueueConsumer, ( signed portCHAR * ) "QConsB6", blckqSTACK_SIZE, ( void * ) pxQueueParameters6, tskIDLE_PRIORITY, NULL ); +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vBlockingQueueProducer, pvParameters ) +{ +unsigned portSHORT usValue = 0; +xBlockingQueueParameters *pxQueueParameters; +portSHORT sErrorEverOccurred = pdFALSE; + + pxQueueParameters = ( xBlockingQueueParameters * ) pvParameters; + + for( ;; ) + { + if( xQueueSend( pxQueueParameters->xQueue, ( void * ) &usValue, pxQueueParameters->xBlockTime ) != pdPASS ) + { + sErrorEverOccurred = pdTRUE; + } + else + { + /* We have successfully posted a message, so increment the variable + used to check we are still running. */ + if( sErrorEverOccurred == pdFALSE ) + { + ( *pxQueueParameters->psCheckVariable )++; + } + + /* Increment the variable we are going to post next time round. The + consumer will expect the numbers to follow in numerical order. */ + ++usValue; + } + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vBlockingQueueConsumer, pvParameters ) +{ +unsigned portSHORT usData, usExpectedValue = 0; +xBlockingQueueParameters *pxQueueParameters; +portSHORT sErrorEverOccurred = pdFALSE; + + pxQueueParameters = ( xBlockingQueueParameters * ) pvParameters; + + for( ;; ) + { + if( xQueueReceive( pxQueueParameters->xQueue, &usData, pxQueueParameters->xBlockTime ) == pdPASS ) + { + if( usData != usExpectedValue ) + { + /* Catch-up. */ + usExpectedValue = usData; + + sErrorEverOccurred = pdTRUE; + } + else + { + /* We have successfully received a message, so increment the + variable used to check we are still running. */ + if( sErrorEverOccurred == pdFALSE ) + { + ( *pxQueueParameters->psCheckVariable )++; + } + + /* Increment the value we expect to remove from the queue next time + round. */ + ++usExpectedValue; + } + } + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +portBASE_TYPE xAreBlockingQueuesStillRunning( void ) +{ +static portSHORT sLastBlockingConsumerCount[ blckqNUM_TASK_SETS ] = { ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0 }; +static portSHORT sLastBlockingProducerCount[ blckqNUM_TASK_SETS ] = { ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0 }; +portBASE_TYPE xReturn = pdPASS, xTasks; + + /* Not too worried about mutual exclusion on these variables as they are 16 + bits and we are only reading them. We also only care to see if they have + changed or not. + + Loop through each check variable to and return pdFALSE if any are found not + to have changed since the last call. */ + + for( xTasks = 0; xTasks < blckqNUM_TASK_SETS; xTasks++ ) + { + if( sBlockingConsumerCount[ xTasks ] == sLastBlockingConsumerCount[ xTasks ] ) + { + xReturn = pdFALSE; + } + sLastBlockingConsumerCount[ xTasks ] = sBlockingConsumerCount[ xTasks ]; + + + if( sBlockingProducerCount[ xTasks ] == sLastBlockingProducerCount[ xTasks ] ) + { + xReturn = pdFALSE; + } + sLastBlockingProducerCount[ xTasks ] = sBlockingProducerCount[ xTasks ]; + } + + return xReturn; +} + diff --git a/20080212/Demo/Common/Minimal/GenQTest.c b/20080212/Demo/Common/Minimal/GenQTest.c new file mode 100644 index 000000000..53dca367c --- /dev/null +++ b/20080212/Demo/Common/Minimal/GenQTest.c @@ -0,0 +1,545 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +/* + * Tests the extra queue functionality introduced in FreeRTOS.org V4.5.0 - + * including xQueueSendToFront(), xQueueSendToBack(), xQueuePeek() and + * mutex behaviour. + * + * See the comments above the prvSendFrontAndBackTest() and + * prvLowPriorityMutexTask() prototypes below for more information. + */ + + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "semphr.h" + +/* Demo program include files. */ +#include "GenQTest.h" + +#define genqQUEUE_LENGTH ( 5 ) +#define genqNO_BLOCK ( 0 ) + +#define genqMUTEX_LOW_PRIORITY ( tskIDLE_PRIORITY ) +#define genqMUTEX_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define genqMUTEX_MEDIUM_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define genqMUTEX_HIGH_PRIORITY ( tskIDLE_PRIORITY + 3 ) + +/*-----------------------------------------------------------*/ + +/* + * Tests the behaviour of the xQueueSendToFront() and xQueueSendToBack() + * macros by using both to fill a queue, then reading from the queue to + * check the resultant queue order is as expected. Queue data is also + * peeked. + */ +static void prvSendFrontAndBackTest( void *pvParameters ); + +/* + * The following three tasks are used to demonstrate the mutex behaviour. + * Each task is given a different priority to demonstrate the priority + * inheritance mechanism. + * + * The low priority task obtains a mutex. After this a high priority task + * attempts to obtain the same mutex, causing its priority to be inherited + * by the low priority task. The task with the inherited high priority then + * resumes a medium priority task to ensure it is not blocked by the medium + * priority task while it holds the inherited high priority. Once the mutex + * is returned the task with the inherited priority returns to its original + * low priority, and is therefore immediately preempted by first the high + * priority task and then the medium prioroity task before it can continue. + */ +static void prvLowPriorityMutexTask( void *pvParameters ); +static void prvMediumPriorityMutexTask( void *pvParameters ); +static void prvHighPriorityMutexTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* Flag that will be latched to pdTRUE should any unexpected behaviour be +detected in any of the tasks. */ +static portBASE_TYPE xErrorDetected = pdFALSE; + +/* Counters that are incremented on each cycle of a test. This is used to +detect a stalled task - a test that is no longer running. */ +static volatile unsigned portLONG ulLoopCounter = 0; +static volatile unsigned portLONG ulLoopCounter2 = 0; + +/* The variable that is guarded by the mutex in the mutex demo tasks. */ +static volatile unsigned portLONG ulGuardedVariable = 0; + +/* Handles used in the mutext test to suspend and resume the high and medium +priority mutex test tasks. */ +static xTaskHandle xHighPriorityMutexTask, xMediumPriorityMutexTask; + +/*-----------------------------------------------------------*/ + +void vStartGenericQueueTasks( unsigned portBASE_TYPE uxPriority ) +{ +xQueueHandle xQueue; +xSemaphoreHandle xMutex; + + /* Create the queue that we are going to use for the + prvSendFrontAndBackTest demo. */ + xQueue = xQueueCreate( genqQUEUE_LENGTH, sizeof( unsigned portLONG ) ); + + /* Create the demo task and pass it the queue just created. We are + passing the queue handle by value so it does not matter that it is + declared on the stack here. */ + xTaskCreate( prvSendFrontAndBackTest, ( signed portCHAR * )"GenQ", configMINIMAL_STACK_SIZE, ( void * ) xQueue, uxPriority, NULL ); + + /* Create the mutex used by the prvMutexTest task. */ + xMutex = xSemaphoreCreateMutex(); + + /* Create the mutex demo tasks and pass it the mutex just created. We are + passing the mutex handle by value so it does not matter that it is declared + on the stack here. */ + xTaskCreate( prvLowPriorityMutexTask, ( signed portCHAR * )"MuLow", configMINIMAL_STACK_SIZE, ( void * ) xMutex, genqMUTEX_LOW_PRIORITY, NULL ); + xTaskCreate( prvMediumPriorityMutexTask, ( signed portCHAR * )"MuMed", configMINIMAL_STACK_SIZE, NULL, genqMUTEX_MEDIUM_PRIORITY, &xMediumPriorityMutexTask ); + xTaskCreate( prvHighPriorityMutexTask, ( signed portCHAR * )"MuHigh", configMINIMAL_STACK_SIZE, ( void * ) xMutex, genqMUTEX_HIGH_PRIORITY, &xHighPriorityMutexTask ); +} +/*-----------------------------------------------------------*/ + +static void prvSendFrontAndBackTest( void *pvParameters ) +{ +unsigned portLONG ulData, ulData2; +xQueueHandle xQueue; + + #ifdef USE_STDIO + void vPrintDisplayMessage( const portCHAR * const * ppcMessageToSend ); + + const portCHAR * const pcTaskStartMsg = "Queue SendToFront/SendToBack/Peek test started.\r\n"; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + #endif + + xQueue = ( xQueueHandle ) pvParameters; + + for( ;; ) + { + /* The queue is empty, so sending an item to the back of the queue + should have the same efect as sending it to the front of the queue. + + First send to the front and check everything is as expected. */ + xQueueSendToFront( xQueue, ( void * ) &ulLoopCounter, genqNO_BLOCK ); + + if( uxQueueMessagesWaiting( xQueue ) != 1 ) + { + xErrorDetected = pdTRUE; + } + + if( xQueueReceive( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + /* The data we sent to the queue should equal the data we just received + from the queue. */ + if( ulLoopCounter != ulData ) + { + xErrorDetected = pdTRUE; + } + + /* Then do the same, sending the data to the back, checking everything + is as expected. */ + if( uxQueueMessagesWaiting( xQueue ) != 0 ) + { + xErrorDetected = pdTRUE; + } + + xQueueSendToBack( xQueue, ( void * ) &ulLoopCounter, genqNO_BLOCK ); + + if( uxQueueMessagesWaiting( xQueue ) != 1 ) + { + xErrorDetected = pdTRUE; + } + + if( xQueueReceive( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + if( uxQueueMessagesWaiting( xQueue ) != 0 ) + { + xErrorDetected = pdTRUE; + } + + /* The data we sent to the queue should equal the data we just received + from the queue. */ + if( ulLoopCounter != ulData ) + { + xErrorDetected = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + + + /* Place 2, 3, 4 into the queue, adding items to the back of the queue. */ + for( ulData = 2; ulData < 5; ulData++ ) + { + xQueueSendToBack( xQueue, ( void * ) &ulData, genqNO_BLOCK ); + } + + /* Now the order in the queue should be 2, 3, 4, with 2 being the first + thing to be read out. Now add 1 then 0 to the front of the queue. */ + if( uxQueueMessagesWaiting( xQueue ) != 3 ) + { + xErrorDetected = pdTRUE; + } + ulData = 1; + xQueueSendToFront( xQueue, ( void * ) &ulData, genqNO_BLOCK ); + ulData = 0; + xQueueSendToFront( xQueue, ( void * ) &ulData, genqNO_BLOCK ); + + /* Now the queue should be full, and when we read the data out we + should receive 0, 1, 2, 3, 4. */ + if( uxQueueMessagesWaiting( xQueue ) != 5 ) + { + xErrorDetected = pdTRUE; + } + + if( xQueueSendToFront( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != errQUEUE_FULL ) + { + xErrorDetected = pdTRUE; + } + + if( xQueueSendToBack( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != errQUEUE_FULL ) + { + xErrorDetected = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* Check the data we read out is in the expected order. */ + for( ulData = 0; ulData < genqQUEUE_LENGTH; ulData++ ) + { + /* Try peeking the data first. */ + if( xQueuePeek( xQueue, &ulData2, genqNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + if( ulData != ulData2 ) + { + xErrorDetected = pdTRUE; + } + + + /* Now try receiving the data for real. The value should be the + same. Clobber the value first so we know we really received it. */ + ulData2 = ~ulData2; + if( xQueueReceive( xQueue, &ulData2, genqNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + if( ulData != ulData2 ) + { + xErrorDetected = pdTRUE; + } + } + + /* The queue should now be empty again. */ + if( uxQueueMessagesWaiting( xQueue ) != 0 ) + { + xErrorDetected = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + + /* Our queue is empty once more, add 10, 11 to the back. */ + ulData = 10; + if( xQueueSend( xQueue, &ulData, genqNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + ulData = 11; + if( xQueueSend( xQueue, &ulData, genqNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + if( uxQueueMessagesWaiting( xQueue ) != 2 ) + { + xErrorDetected = pdTRUE; + } + + /* Now we should have 10, 11 in the queue. Add 7, 8, 9 to the + front. */ + for( ulData = 9; ulData >= 7; ulData-- ) + { + if( xQueueSendToFront( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + } + + /* Now check that the queue is full, and that receiving data provides + the expected sequence of 7, 8, 9, 10, 11. */ + if( uxQueueMessagesWaiting( xQueue ) != 5 ) + { + xErrorDetected = pdTRUE; + } + + if( xQueueSendToFront( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != errQUEUE_FULL ) + { + xErrorDetected = pdTRUE; + } + + if( xQueueSendToBack( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != errQUEUE_FULL ) + { + xErrorDetected = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* Check the data we read out is in the expected order. */ + for( ulData = 7; ulData < ( 7 + genqQUEUE_LENGTH ); ulData++ ) + { + if( xQueueReceive( xQueue, &ulData2, genqNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + if( ulData != ulData2 ) + { + xErrorDetected = pdTRUE; + } + } + + if( uxQueueMessagesWaiting( xQueue ) != 0 ) + { + xErrorDetected = pdTRUE; + } + + ulLoopCounter++; + } +} +/*-----------------------------------------------------------*/ + +static void prvLowPriorityMutexTask( void *pvParameters ) +{ +xSemaphoreHandle xMutex = ( xSemaphoreHandle ) pvParameters; + + #ifdef USE_STDIO + void vPrintDisplayMessage( const portCHAR * const * ppcMessageToSend ); + + const portCHAR * const pcTaskStartMsg = "Mutex with priority inheritance test started.\r\n"; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + #endif + + for( ;; ) + { + /* Take the mutex. It should be available now. */ + if( xSemaphoreTake( xMutex, genqNO_BLOCK ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + /* Set our guarded variable to a known start value. */ + ulGuardedVariable = 0; + + /* Our priority should be as per that assigned when the task was + created. */ + if( uxTaskPriorityGet( NULL ) != genqMUTEX_LOW_PRIORITY ) + { + xErrorDetected = pdTRUE; + } + + /* Now unsuspend the high priority task. This will attempt to take the + mutex, and block when it finds it cannot obtain it. */ + vTaskResume( xHighPriorityMutexTask ); + + /* We should now have inherited the prioritoy of the high priority task, + as by now it will have attempted to get the mutex. */ + if( uxTaskPriorityGet( NULL ) != genqMUTEX_HIGH_PRIORITY ) + { + xErrorDetected = pdTRUE; + } + + /* We can attempt to set our priority to the test priority - between the + idle priority and the medium/high test priorities, but our actual + prioroity should remain at the high priority. */ + vTaskPrioritySet( NULL, genqMUTEX_TEST_PRIORITY ); + if( uxTaskPriorityGet( NULL ) != genqMUTEX_HIGH_PRIORITY ) + { + xErrorDetected = pdTRUE; + } + + /* Now unsuspend the medium priority task. This should not run as our + inherited priority is above that of the medium priority task. */ + vTaskResume( xMediumPriorityMutexTask ); + + /* If the did run then it will have incremented our guarded variable. */ + if( ulGuardedVariable != 0 ) + { + xErrorDetected = pdTRUE; + } + + /* When we give back the semaphore our priority should be disinherited + back to the priority to which we attempted to set ourselves. This means + that when the high priority task next blocks, the medium priority task + should execute and increment the guarded variable. When we next run + both the high and medium priority tasks will have been suspended again. */ + if( xSemaphoreGive( xMutex ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + /* Check that the guarded variable did indeed increment... */ + if( ulGuardedVariable != 1 ) + { + xErrorDetected = pdTRUE; + } + + /* ... and that our priority has been disinherited to + genqMUTEX_TEST_PRIORITY. */ + if( uxTaskPriorityGet( NULL ) != genqMUTEX_TEST_PRIORITY ) + { + xErrorDetected = pdTRUE; + } + + /* Set our priority back to our original priority ready for the next + loop around this test. */ + vTaskPrioritySet( NULL, genqMUTEX_LOW_PRIORITY ); + + /* Just to show we are still running. */ + ulLoopCounter2++; + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + } +} +/*-----------------------------------------------------------*/ + +static void prvMediumPriorityMutexTask( void *pvParameters ) +{ + ( void ) pvParameters; + + for( ;; ) + { + /* The medium priority task starts by suspending itself. The low + priority task will unsuspend this task when required. */ + vTaskSuspend( NULL ); + + /* When this task unsuspends all it does is increment the guarded + variable, this is so the low priority task knows that it has + executed. */ + ulGuardedVariable++; + } +} +/*-----------------------------------------------------------*/ + +static void prvHighPriorityMutexTask( void *pvParameters ) +{ +xSemaphoreHandle xMutex = ( xSemaphoreHandle ) pvParameters; + + for( ;; ) + { + /* The high priority task starts by suspending itself. The low + priority task will unsuspend this task when required. */ + vTaskSuspend( NULL ); + + /* When this task unsuspends all it does is attempt to obtain + the mutex. It should find the mutex is not available so a + block time is specified. */ + if( xSemaphoreTake( xMutex, portMAX_DELAY ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + /* When we eventually obtain the mutex we just give it back then + return to suspend ready for the next test. */ + if( xSemaphoreGive( xMutex ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +portBASE_TYPE xAreGenericQueueTasksStillRunning( void ) +{ +static unsigned portLONG ulLastLoopCounter = 0, ulLastLoopCounter2 = 0; + + /* If the demo task is still running then we expect the loopcounters to + have incremented since this function was last called. */ + if( ulLastLoopCounter == ulLoopCounter ) + { + xErrorDetected = pdTRUE; + } + + if( ulLastLoopCounter2 == ulLoopCounter2 ) + { + xErrorDetected = pdTRUE; + } + + ulLastLoopCounter = ulLoopCounter; + ulLastLoopCounter2 = ulLoopCounter2; + + /* Errors detected in the task itself will have latched xErrorDetected + to true. */ + + return !xErrorDetected; +} + + diff --git a/20080212/Demo/Common/Minimal/PollQ.c b/20080212/Demo/Common/Minimal/PollQ.c new file mode 100644 index 000000000..f04c7f5a0 --- /dev/null +++ b/20080212/Demo/Common/Minimal/PollQ.c @@ -0,0 +1,227 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + * This version of PollQ. c is for use on systems that have limited stack + * space and no display facilities. The complete version can be found in + * the Demo/Common/Full directory. + * + * Creates two tasks that communicate over a single queue. One task acts as a + * producer, the other a consumer. + * + * The producer loops for three iteration, posting an incrementing number onto the + * queue each cycle. It then delays for a fixed period before doing exactly the + * same again. + * + * The consumer loops emptying the queue. Each item removed from the queue is + * checked to ensure it contains the expected value. When the queue is empty it + * blocks for a fixed period, then does the same again. + * + * All queue access is performed without blocking. The consumer completely empties + * the queue each time it runs so the producer should never find the queue full. + * + * An error is flagged if the consumer obtains an unexpected value or the producer + * find the queue is full. + */ + +/* +Changes from V2.0.0 + + + Delay periods are now specified using variables and constants of + portTickType rather than unsigned portLONG. +*/ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* Demo program include files. */ +#include "PollQ.h" + +#define pollqSTACK_SIZE configMINIMAL_STACK_SIZE +#define pollqQUEUE_SIZE ( 10 ) +#define pollqPRODUCER_DELAY ( ( portTickType ) 200 / portTICK_RATE_MS ) +#define pollqCONSUMER_DELAY ( pollqPRODUCER_DELAY - ( portTickType ) ( 20 / portTICK_RATE_MS ) ) +#define pollqNO_DELAY ( ( portTickType ) 0 ) +#define pollqVALUES_TO_PRODUCE ( ( signed portBASE_TYPE ) 3 ) +#define pollqINITIAL_VALUE ( ( signed portBASE_TYPE ) 0 ) + +/* The task that posts the incrementing number onto the queue. */ +static portTASK_FUNCTION_PROTO( vPolledQueueProducer, pvParameters ); + +/* The task that empties the queue. */ +static portTASK_FUNCTION_PROTO( vPolledQueueConsumer, pvParameters ); + +/* Variables that are used to check that the tasks are still running with no +errors. */ +static volatile signed portBASE_TYPE xPollingConsumerCount = pollqINITIAL_VALUE, xPollingProducerCount = pollqINITIAL_VALUE; + +/*-----------------------------------------------------------*/ + +void vStartPolledQueueTasks( unsigned portBASE_TYPE uxPriority ) +{ +static xQueueHandle xPolledQueue; + + /* Create the queue used by the producer and consumer. */ + xPolledQueue = xQueueCreate( pollqQUEUE_SIZE, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) ); + + /* Spawn the producer and consumer. */ + xTaskCreate( vPolledQueueConsumer, ( signed portCHAR * ) "QConsNB", pollqSTACK_SIZE, ( void * ) &xPolledQueue, uxPriority, ( xTaskHandle * ) NULL ); + xTaskCreate( vPolledQueueProducer, ( signed portCHAR * ) "QProdNB", pollqSTACK_SIZE, ( void * ) &xPolledQueue, uxPriority, ( xTaskHandle * ) NULL ); +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vPolledQueueProducer, pvParameters ) +{ +unsigned portSHORT usValue = ( unsigned portSHORT ) 0; +signed portBASE_TYPE xError = pdFALSE, xLoop; + + for( ;; ) + { + for( xLoop = 0; xLoop < pollqVALUES_TO_PRODUCE; xLoop++ ) + { + /* Send an incrementing number on the queue without blocking. */ + if( xQueueSend( *( ( xQueueHandle * ) pvParameters ), ( void * ) &usValue, pollqNO_DELAY ) != pdPASS ) + { + /* We should never find the queue full so if we get here there + has been an error. */ + xError = pdTRUE; + } + else + { + if( xError == pdFALSE ) + { + /* If an error has ever been recorded we stop incrementing the + check variable. */ + portENTER_CRITICAL(); + xPollingProducerCount++; + portEXIT_CRITICAL(); + } + + /* Update the value we are going to post next time around. */ + usValue++; + } + } + + /* Wait before we start posting again to ensure the consumer runs and + empties the queue. */ + vTaskDelay( pollqPRODUCER_DELAY ); + } +} /*lint !e818 Function prototype must conform to API. */ +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vPolledQueueConsumer, pvParameters ) +{ +unsigned portSHORT usData, usExpectedValue = ( unsigned portSHORT ) 0; +signed portBASE_TYPE xError = pdFALSE; + + for( ;; ) + { + /* Loop until the queue is empty. */ + while( uxQueueMessagesWaiting( *( ( xQueueHandle * ) pvParameters ) ) ) + { + if( xQueueReceive( *( ( xQueueHandle * ) pvParameters ), &usData, pollqNO_DELAY ) == pdPASS ) + { + if( usData != usExpectedValue ) + { + /* This is not what we expected to receive so an error has + occurred. */ + xError = pdTRUE; + + /* Catch-up to the value we received so our next expected + value should again be correct. */ + usExpectedValue = usData; + } + else + { + if( xError == pdFALSE ) + { + /* Only increment the check variable if no errors have + occurred. */ + portENTER_CRITICAL(); + xPollingConsumerCount++; + portEXIT_CRITICAL(); + } + } + + /* Next time round we would expect the number to be one higher. */ + usExpectedValue++; + } + } + + /* Now the queue is empty we block, allowing the producer to place more + items in the queue. */ + vTaskDelay( pollqCONSUMER_DELAY ); + } +} /*lint !e818 Function prototype must conform to API. */ +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running with no errors. */ +portBASE_TYPE xArePollingQueuesStillRunning( void ) +{ +portBASE_TYPE xReturn; + + /* Check both the consumer and producer poll count to check they have both + been changed since out last trip round. We do not need a critical section + around the check variables as this is called from a higher priority than + the other tasks that access the same variables. */ + if( ( xPollingConsumerCount == pollqINITIAL_VALUE ) || + ( xPollingProducerCount == pollqINITIAL_VALUE ) + ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + /* Set the check variables back down so we know if they have been + incremented the next time around. */ + xPollingConsumerCount = pollqINITIAL_VALUE; + xPollingProducerCount = pollqINITIAL_VALUE; + + return xReturn; +} diff --git a/20080212/Demo/Common/Minimal/QPeek.c b/20080212/Demo/Common/Minimal/QPeek.c new file mode 100644 index 000000000..400278754 --- /dev/null +++ b/20080212/Demo/Common/Minimal/QPeek.c @@ -0,0 +1,427 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +/* + * Tests the behaviour when data is peeked from a queue when there are + * multiple tasks blocked on the queue. + */ + + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "semphr.h" + +/* Demo program include files. */ +#include "QPeek.h" + +#define qpeekQUEUE_LENGTH ( 5 ) +#define qpeekNO_BLOCK ( 0 ) +#define qpeekSHORT_DELAY ( 10 ) + +#define qpeekLOW_PRIORITY ( tskIDLE_PRIORITY + 0 ) +#define qpeekMEDIUM_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define qpeekHIGH_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define qpeekHIGHEST_PRIORITY ( tskIDLE_PRIORITY + 3 ) + +/*-----------------------------------------------------------*/ + +/* + * The following three tasks are used to demonstrate the peeking behaviour. + * Each task is given a different priority to demonstrate the order in which + * tasks are woken as data is peeked from a queue. + */ +static void prvLowPriorityPeekTask( void *pvParameters ); +static void prvMediumPriorityPeekTask( void *pvParameters ); +static void prvHighPriorityPeekTask( void *pvParameters ); +static void prvHighestPriorityPeekTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* Flag that will be latched to pdTRUE should any unexpected behaviour be +detected in any of the tasks. */ +static portBASE_TYPE xErrorDetected = pdFALSE; + +/* Counter that is incremented on each cycle of a test. This is used to +detect a stalled task - a test that is no longer running. */ +static volatile unsigned portLONG ulLoopCounter = 0; + +/* Handles to the test tasks. */ +xTaskHandle xMediumPriorityTask, xHighPriorityTask, xHighestPriorityTask; +/*-----------------------------------------------------------*/ + +void vStartQueuePeekTasks( void ) +{ +xQueueHandle xQueue; + + /* Create the queue that we are going to use for the test/demo. */ + xQueue = xQueueCreate( qpeekQUEUE_LENGTH, sizeof( unsigned portLONG ) ); + + /* Create the demo tasks and pass it the queue just created. We are + passing the queue handle by value so it does not matter that it is declared + on the stack here. */ + xTaskCreate( prvLowPriorityPeekTask, ( signed portCHAR * )"PeekL", configMINIMAL_STACK_SIZE, ( void * ) xQueue, qpeekLOW_PRIORITY, NULL ); + xTaskCreate( prvMediumPriorityPeekTask, ( signed portCHAR * )"PeekM", configMINIMAL_STACK_SIZE, ( void * ) xQueue, qpeekMEDIUM_PRIORITY, &xMediumPriorityTask ); + xTaskCreate( prvHighPriorityPeekTask, ( signed portCHAR * )"PeekH1", configMINIMAL_STACK_SIZE, ( void * ) xQueue, qpeekHIGH_PRIORITY, &xHighPriorityTask ); + xTaskCreate( prvHighestPriorityPeekTask, ( signed portCHAR * )"PeekH2", configMINIMAL_STACK_SIZE, ( void * ) xQueue, qpeekHIGHEST_PRIORITY, &xHighestPriorityTask ); +} +/*-----------------------------------------------------------*/ + +static void prvHighestPriorityPeekTask( void *pvParameters ) +{ +xQueueHandle xQueue = ( xQueueHandle ) pvParameters; +unsigned portLONG ulValue; + + #ifdef USE_STDIO + { + void vPrintDisplayMessage( const portCHAR * const * ppcMessageToSend ); + + const portCHAR * const pcTaskStartMsg = "Queue peek test started.\r\n"; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + } + #endif + + for( ;; ) + { + /* Try peeking from the queue. The queue should be empty so we will + block, allowing the high priority task to execute. */ + if( xQueuePeek( xQueue, &ulValue, portMAX_DELAY ) != pdPASS ) + { + /* We expected to have received something by the time we unblock. */ + xErrorDetected = pdTRUE; + } + + /* When we reach here the high and medium priority tasks should still + be blocked on the queue. We unblocked because the low priority task + wrote a value to the queue, which we should have peeked. Peeking the + data (rather than receiving it) will leave the data on the queue, so + the high priority task should then have also been unblocked, but not + yet executed. */ + if( ulValue != 0x11223344 ) + { + /* We did not receive the expected value. */ + xErrorDetected = pdTRUE; + } + + if( uxQueueMessagesWaiting( xQueue ) != 1 ) + { + /* The message should have been left on the queue. */ + xErrorDetected = pdTRUE; + } + + /* Now we are going to actually receive the data, so when the high + priority task runs it will find the queue empty and return to the + blocked state. */ + ulValue = 0; + if( xQueueReceive( xQueue, &ulValue, qpeekNO_BLOCK ) != pdPASS ) + { + /* We expected to receive the value. */ + xErrorDetected = pdTRUE; + } + + if( ulValue != 0x11223344 ) + { + /* We did not receive the expected value - which should have been + the same value as was peeked. */ + xErrorDetected = pdTRUE; + } + + /* Now we will block again as the queue is once more empty. The low + priority task can then execute again. */ + if( xQueuePeek( xQueue, &ulValue, portMAX_DELAY ) != pdPASS ) + { + /* We expected to have received something by the time we unblock. */ + xErrorDetected = pdTRUE; + } + + /* When we get here the low priority task should have again written to the + queue. */ + if( ulValue != 0x01234567 ) + { + /* We did not receive the expected value. */ + xErrorDetected = pdTRUE; + } + + if( uxQueueMessagesWaiting( xQueue ) != 1 ) + { + /* The message should have been left on the queue. */ + xErrorDetected = pdTRUE; + } + + /* We only peeked the data, so suspending ourselves now should enable + the high priority task to also peek the data. The high priority task + will have been unblocked when we peeked the data as we left the data + in the queue. */ + vTaskSuspend( NULL ); + + + + /* This time we are going to do the same as the above test, but the + high priority task is going to receive the data, rather than peek it. + This means that the medium priority task should never peek the value. */ + if( xQueuePeek( xQueue, &ulValue, portMAX_DELAY ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + if( ulValue != 0xaabbaabb ) + { + xErrorDetected = pdTRUE; + } + + vTaskSuspend( NULL ); + } +} +/*-----------------------------------------------------------*/ + +static void prvHighPriorityPeekTask( void *pvParameters ) +{ +xQueueHandle xQueue = ( xQueueHandle ) pvParameters; +unsigned portLONG ulValue; + + for( ;; ) + { + /* Try peeking from the queue. The queue should be empty so we will + block, allowing the medium priority task to execute. Both the high + and highest priority tasks will then be blocked on the queue. */ + if( xQueuePeek( xQueue, &ulValue, portMAX_DELAY ) != pdPASS ) + { + /* We expected to have received something by the time we unblock. */ + xErrorDetected = pdTRUE; + } + + /* When we get here the highest priority task should have peeked the data + (unblocking this task) then suspended (allowing this task to also peek + the data). */ + if( ulValue != 0x01234567 ) + { + /* We did not receive the expected value. */ + xErrorDetected = pdTRUE; + } + + if( uxQueueMessagesWaiting( xQueue ) != 1 ) + { + /* The message should have been left on the queue. */ + xErrorDetected = pdTRUE; + } + + /* We only peeked the data, so suspending ourselves now should enable + the medium priority task to also peek the data. The medium priority task + will have been unblocked when we peeked the data as we left the data + in the queue. */ + vTaskSuspend( NULL ); + + + /* This time we are going actually receive the value, so the medium + priority task will never peek the data - we removed it from the queue. */ + if( xQueueReceive( xQueue, &ulValue, portMAX_DELAY ) != pdPASS ) + { + xErrorDetected = pdTRUE; + } + + if( ulValue != 0xaabbaabb ) + { + xErrorDetected = pdTRUE; + } + + vTaskSuspend( NULL ); + } +} +/*-----------------------------------------------------------*/ + +static void prvMediumPriorityPeekTask( void *pvParameters ) +{ +xQueueHandle xQueue = ( xQueueHandle ) pvParameters; +unsigned portLONG ulValue; + + for( ;; ) + { + /* Try peeking from the queue. The queue should be empty so we will + block, allowing the low priority task to execute. The highest, high + and medium priority tasks will then all be blocked on the queue. */ + if( xQueuePeek( xQueue, &ulValue, portMAX_DELAY ) != pdPASS ) + { + /* We expected to have received something by the time we unblock. */ + xErrorDetected = pdTRUE; + } + + /* When we get here the high priority task should have peeked the data + (unblocking this task) then suspended (allowing this task to also peek + the data). */ + if( ulValue != 0x01234567 ) + { + /* We did not receive the expected value. */ + xErrorDetected = pdTRUE; + } + + if( uxQueueMessagesWaiting( xQueue ) != 1 ) + { + /* The message should have been left on the queue. */ + xErrorDetected = pdTRUE; + } + + /* Just so we know the test is still running. */ + ulLoopCounter++; + + /* Now we can suspend ourselves so the low priority task can execute + again. */ + vTaskSuspend( NULL ); + } +} +/*-----------------------------------------------------------*/ + +static void prvLowPriorityPeekTask( void *pvParameters ) +{ +xQueueHandle xQueue = ( xQueueHandle ) pvParameters; +unsigned portLONG ulValue; + + for( ;; ) + { + /* Write some data to the queue. This should unblock the highest + priority task that is waiting to peek data from the queue. */ + ulValue = 0x11223344; + if( xQueueSendToBack( xQueue, &ulValue, qpeekNO_BLOCK ) != pdPASS ) + { + /* We were expecting the queue to be empty so we should not of + had a problem writing to the queue. */ + xErrorDetected = pdTRUE; + } + + /* By the time we get here the data should have been removed from + the queue. */ + if( uxQueueMessagesWaiting( xQueue ) != 0 ) + { + xErrorDetected = pdTRUE; + } + + /* Write another value to the queue, again waking the highest priority + task that is blocked on the queue. */ + ulValue = 0x01234567; + if( xQueueSendToBack( xQueue, &ulValue, qpeekNO_BLOCK ) != pdPASS ) + { + /* We were expecting the queue to be empty so we should not of + had a problem writing to the queue. */ + xErrorDetected = pdTRUE; + } + + /* All the other tasks should now have successfully peeked the data. + The data is still in the queue so we should be able to receive it. */ + ulValue = 0; + if( xQueueReceive( xQueue, &ulValue, qpeekNO_BLOCK ) != pdPASS ) + { + /* We expected to receive the data. */ + xErrorDetected = pdTRUE; + } + + if( ulValue != 0x01234567 ) + { + /* We did not receive the expected value. */ + } + + /* Lets just delay a while as this is an intensive test as we don't + want to starve other tests of processing time. */ + vTaskDelay( qpeekSHORT_DELAY ); + + /* Unsuspend the other tasks so we can repeat the test - this time + however not all the other tasks will peek the data as the high + priority task is actually going to remove it from the queue. Send + to front is used just to be different. As the queue is empty it + makes no difference to the result. */ + vTaskResume( xMediumPriorityTask ); + vTaskResume( xHighPriorityTask ); + vTaskResume( xHighestPriorityTask ); + + ulValue = 0xaabbaabb; + if( xQueueSendToFront( xQueue, &ulValue, qpeekNO_BLOCK ) != pdPASS ) + { + /* We were expecting the queue to be empty so we should not of + had a problem writing to the queue. */ + xErrorDetected = pdTRUE; + } + + /* This time we should find that the queue is empty. The high priority + task actually removed the data rather than just peeking it. */ + if( xQueuePeek( xQueue, &ulValue, qpeekNO_BLOCK ) != errQUEUE_EMPTY ) + { + /* We expected to receive the data. */ + xErrorDetected = pdTRUE; + } + + /* Unsuspend the highest and high priority tasks so we can go back + and repeat the whole thing. The medium priority task should not be + suspended as it was not able to peek the data in this last case. */ + vTaskResume( xHighPriorityTask ); + vTaskResume( xHighestPriorityTask ); + + /* Lets just delay a while as this is an intensive test as we don't + want to starve other tests of processing time. */ + vTaskDelay( qpeekSHORT_DELAY ); + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +portBASE_TYPE xAreQueuePeekTasksStillRunning( void ) +{ +static unsigned portLONG ulLastLoopCounter = 0; + + /* If the demo task is still running then we expect the loopcounter to + have incremented since this function was last called. */ + if( ulLastLoopCounter == ulLoopCounter ) + { + xErrorDetected = pdTRUE; + } + + ulLastLoopCounter = ulLoopCounter; + + /* Errors detected in the task itself will have latched xErrorDetected + to true. */ + + return !xErrorDetected; +} + diff --git a/20080212/Demo/Common/Minimal/blocktim.c b/20080212/Demo/Common/Minimal/blocktim.c new file mode 100644 index 000000000..645dada65 --- /dev/null +++ b/20080212/Demo/Common/Minimal/blocktim.c @@ -0,0 +1,487 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + * This file contains some test scenarios that ensure tasks do not exit queue + * send or receive functions prematurely. A description of the tests is + * included within the code. + */ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* Demo includes. */ +#include "blocktim.h" + +/* Task priorities. */ +#define bktPRIMARY_PRIORITY ( 3 ) +#define bktSECONDARY_PRIORITY ( 2 ) + +/* Task behaviour. */ +#define bktQUEUE_LENGTH ( 5 ) +#define bktSHORT_WAIT ( ( ( portTickType ) 20 ) / portTICK_RATE_MS ) +#define bktPRIMARY_BLOCK_TIME ( 10 ) +#define bktALLOWABLE_MARGIN ( 12 ) +#define bktTIME_TO_BLOCK ( 175 ) +#define bktDONT_BLOCK ( ( portTickType ) 0 ) +#define bktRUN_INDICATOR ( ( unsigned portBASE_TYPE ) 0x55 ) + +/* The queue on which the tasks block. */ +static xQueueHandle xTestQueue; + +/* Handle to the secondary task is required by the primary task for calls +to vTaskSuspend/Resume(). */ +static xTaskHandle xSecondary; + +/* Used to ensure that tasks are still executing without error. */ +static portBASE_TYPE xPrimaryCycles = 0, xSecondaryCycles = 0; +static portBASE_TYPE xErrorOccurred = pdFALSE; + +/* Provides a simple mechanism for the primary task to know when the +secondary task has executed. */ +static volatile unsigned portBASE_TYPE xRunIndicator; + +/* The two test tasks. Their behaviour is commented within the files. */ +static void vPrimaryBlockTimeTestTask( void *pvParameters ); +static void vSecondaryBlockTimeTestTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +void vCreateBlockTimeTasks( void ) +{ + /* Create the queue on which the two tasks block. */ + xTestQueue = xQueueCreate( bktQUEUE_LENGTH, sizeof( portBASE_TYPE ) ); + + /* Create the two test tasks. */ + xTaskCreate( vPrimaryBlockTimeTestTask, ( signed portCHAR * )"BTest1", configMINIMAL_STACK_SIZE, NULL, bktPRIMARY_PRIORITY, NULL ); + xTaskCreate( vSecondaryBlockTimeTestTask, ( signed portCHAR * )"BTest2", configMINIMAL_STACK_SIZE, NULL, bktSECONDARY_PRIORITY, &xSecondary ); +} +/*-----------------------------------------------------------*/ + +static void vPrimaryBlockTimeTestTask( void *pvParameters ) +{ +portBASE_TYPE xItem, xData; +portTickType xTimeWhenBlocking; +portTickType xTimeToBlock, xBlockedTime; + + ( void ) pvParameters; + + for( ;; ) + { + /********************************************************************* + Test 1 + + Simple block time wakeup test on queue receives. */ + for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ ) + { + /* The queue is empty. Attempt to read from the queue using a block + time. When we wake, ensure the delta in time is as expected. */ + xTimeToBlock = bktPRIMARY_BLOCK_TIME << xItem; + + /* A critical section is used to minimise the jitter in the time + measurements. */ + portENTER_CRITICAL(); + { + xTimeWhenBlocking = xTaskGetTickCount(); + + /* We should unblock after xTimeToBlock having not received + anything on the queue. */ + if( xQueueReceive( xTestQueue, &xData, xTimeToBlock ) != errQUEUE_EMPTY ) + { + xErrorOccurred = pdTRUE; + } + + /* How long were we blocked for? */ + xBlockedTime = xTaskGetTickCount() - xTimeWhenBlocking; + } + portEXIT_CRITICAL(); + + if( xBlockedTime < xTimeToBlock ) + { + /* Should not have blocked for less than we requested. */ + xErrorOccurred = pdTRUE; + } + + if( xBlockedTime > ( xTimeToBlock + bktALLOWABLE_MARGIN ) ) + { + /* Should not have blocked for longer than we requested, + although we would not necessarily run as soon as we were + unblocked so a margin is allowed. */ + xErrorOccurred = pdTRUE; + } + } + + /********************************************************************* + Test 2 + + Simple block time wakeup test on queue sends. + + First fill the queue. It should be empty so all sends should pass. */ + for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ ) + { + if( xQueueSend( xTestQueue, &xItem, bktDONT_BLOCK ) != pdPASS ) + { + xErrorOccurred = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + } + + for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ ) + { + /* The queue is full. Attempt to write to the queue using a block + time. When we wake, ensure the delta in time is as expected. */ + xTimeToBlock = bktPRIMARY_BLOCK_TIME << xItem; + + portENTER_CRITICAL(); + { + xTimeWhenBlocking = xTaskGetTickCount(); + + /* We should unblock after xTimeToBlock having not received + anything on the queue. */ + if( xQueueSend( xTestQueue, &xItem, xTimeToBlock ) != errQUEUE_FULL ) + { + xErrorOccurred = pdTRUE; + } + + /* How long were we blocked for? */ + xBlockedTime = xTaskGetTickCount() - xTimeWhenBlocking; + } + portEXIT_CRITICAL(); + + if( xBlockedTime < xTimeToBlock ) + { + /* Should not have blocked for less than we requested. */ + xErrorOccurred = pdTRUE; + } + + if( xBlockedTime > ( xTimeToBlock + bktALLOWABLE_MARGIN ) ) + { + /* Should not have blocked for longer than we requested, + although we would not necessarily run as soon as we were + unblocked so a margin is allowed. */ + xErrorOccurred = pdTRUE; + } + } + + /********************************************************************* + Test 3 + + Wake the other task, it will block attempting to post to the queue. + When we read from the queue the other task will wake, but before it + can run we will post to the queue again. When the other task runs it + will find the queue still full, even though it was woken. It should + recognise that its block time has not expired and return to block for + the remains of its block time. + + Wake the other task so it blocks attempting to post to the already + full queue. */ + xRunIndicator = 0; + vTaskResume( xSecondary ); + + /* We need to wait a little to ensure the other task executes. */ + while( xRunIndicator != bktRUN_INDICATOR ) + { + /* The other task has not yet executed. */ + vTaskDelay( bktSHORT_WAIT ); + } + /* Make sure the other task is blocked on the queue. */ + vTaskDelay( bktSHORT_WAIT ); + xRunIndicator = 0; + + for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ ) + { + /* Now when we make space on the queue the other task should wake + but not execute as this task has higher priority. */ + if( xQueueReceive( xTestQueue, &xData, bktDONT_BLOCK ) != pdPASS ) + { + xErrorOccurred = pdTRUE; + } + + /* Now fill the queue again before the other task gets a chance to + execute. If the other task had executed we would find the queue + full ourselves, and the other task have set xRunIndicator. */ + if( xQueueSend( xTestQueue, &xItem, bktDONT_BLOCK ) != pdPASS ) + { + xErrorOccurred = pdTRUE; + } + + if( xRunIndicator == bktRUN_INDICATOR ) + { + /* The other task should not have executed. */ + xErrorOccurred = pdTRUE; + } + + /* Raise the priority of the other task so it executes and blocks + on the queue again. */ + vTaskPrioritySet( xSecondary, bktPRIMARY_PRIORITY + 2 ); + + /* The other task should now have re-blocked without exiting the + queue function. */ + if( xRunIndicator == bktRUN_INDICATOR ) + { + /* The other task should not have executed outside of the + queue function. */ + xErrorOccurred = pdTRUE; + } + + /* Set the priority back down. */ + vTaskPrioritySet( xSecondary, bktSECONDARY_PRIORITY ); + } + + /* Let the other task timeout. When it unblockes it will check that it + unblocked at the correct time, then suspend itself. */ + while( xRunIndicator != bktRUN_INDICATOR ) + { + vTaskDelay( bktSHORT_WAIT ); + } + vTaskDelay( bktSHORT_WAIT ); + xRunIndicator = 0; + + + /********************************************************************* + Test 4 + + As per test 3 - but with the send and receive the other way around. + The other task blocks attempting to read from the queue. + + Empty the queue. We should find that it is full. */ + for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ ) + { + if( xQueueReceive( xTestQueue, &xData, bktDONT_BLOCK ) != pdPASS ) + { + xErrorOccurred = pdTRUE; + } + } + + /* Wake the other task so it blocks attempting to read from the + already empty queue. */ + vTaskResume( xSecondary ); + + /* We need to wait a little to ensure the other task executes. */ + while( xRunIndicator != bktRUN_INDICATOR ) + { + vTaskDelay( bktSHORT_WAIT ); + } + vTaskDelay( bktSHORT_WAIT ); + xRunIndicator = 0; + + for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ ) + { + /* Now when we place an item on the queue the other task should + wake but not execute as this task has higher priority. */ + if( xQueueSend( xTestQueue, &xItem, bktDONT_BLOCK ) != pdPASS ) + { + xErrorOccurred = pdTRUE; + } + + /* Now empty the queue again before the other task gets a chance to + execute. If the other task had executed we would find the queue + empty ourselves, and the other task would be suspended. */ + if( xQueueReceive( xTestQueue, &xData, bktDONT_BLOCK ) != pdPASS ) + { + xErrorOccurred = pdTRUE; + } + + if( xRunIndicator == bktRUN_INDICATOR ) + { + /* The other task should not have executed. */ + xErrorOccurred = pdTRUE; + } + + /* Raise the priority of the other task so it executes and blocks + on the queue again. */ + vTaskPrioritySet( xSecondary, bktPRIMARY_PRIORITY + 2 ); + + /* The other task should now have re-blocked without exiting the + queue function. */ + if( xRunIndicator == bktRUN_INDICATOR ) + { + /* The other task should not have executed outside of the + queue function. */ + xErrorOccurred = pdTRUE; + } + vTaskPrioritySet( xSecondary, bktSECONDARY_PRIORITY ); + } + + /* Let the other task timeout. When it unblockes it will check that it + unblocked at the correct time, then suspend itself. */ + while( xRunIndicator != bktRUN_INDICATOR ) + { + vTaskDelay( bktSHORT_WAIT ); + } + vTaskDelay( bktSHORT_WAIT ); + + xPrimaryCycles++; + } +} +/*-----------------------------------------------------------*/ + +static void vSecondaryBlockTimeTestTask( void *pvParameters ) +{ +portTickType xTimeWhenBlocking, xBlockedTime; +portBASE_TYPE xData; + + ( void ) pvParameters; + + for( ;; ) + { + /********************************************************************* + Test 1 and 2 + + This task does does not participate in these tests. */ + vTaskSuspend( NULL ); + + /********************************************************************* + Test 3 + + The first thing we do is attempt to read from the queue. It should be + full so we block. Note the time before we block so we can check the + wake time is as per that expected. */ + portENTER_CRITICAL(); + { + xTimeWhenBlocking = xTaskGetTickCount(); + + /* We should unblock after bktTIME_TO_BLOCK having not received + anything on the queue. */ + xData = 0; + xRunIndicator = bktRUN_INDICATOR; + if( xQueueSend( xTestQueue, &xData, bktTIME_TO_BLOCK ) != errQUEUE_FULL ) + { + xErrorOccurred = pdTRUE; + } + + /* How long were we inside the send function? */ + xBlockedTime = xTaskGetTickCount() - xTimeWhenBlocking; + } + portEXIT_CRITICAL(); + + /* We should not have blocked for less time than bktTIME_TO_BLOCK. */ + if( xBlockedTime < bktTIME_TO_BLOCK ) + { + xErrorOccurred = pdTRUE; + } + + /* We should of not blocked for much longer than bktALLOWABLE_MARGIN + either. A margin is permitted as we would not necessarily run as + soon as we unblocked. */ + if( xBlockedTime > ( bktTIME_TO_BLOCK + bktALLOWABLE_MARGIN ) ) + { + xErrorOccurred = pdTRUE; + } + + /* Suspend ready for test 3. */ + xRunIndicator = bktRUN_INDICATOR; + vTaskSuspend( NULL ); + + /********************************************************************* + Test 4 + + As per test three, but with the send and receive reversed. */ + portENTER_CRITICAL(); + { + xTimeWhenBlocking = xTaskGetTickCount(); + + /* We should unblock after bktTIME_TO_BLOCK having not received + anything on the queue. */ + xRunIndicator = bktRUN_INDICATOR; + if( xQueueReceive( xTestQueue, &xData, bktTIME_TO_BLOCK ) != errQUEUE_EMPTY ) + { + xErrorOccurred = pdTRUE; + } + + xBlockedTime = xTaskGetTickCount() - xTimeWhenBlocking; + } + portEXIT_CRITICAL(); + + /* We should not have blocked for less time than bktTIME_TO_BLOCK. */ + if( xBlockedTime < bktTIME_TO_BLOCK ) + { + xErrorOccurred = pdTRUE; + } + + /* We should of not blocked for much longer than bktALLOWABLE_MARGIN + either. A margin is permitted as we would not necessarily run as soon + as we unblocked. */ + if( xBlockedTime > ( bktTIME_TO_BLOCK + bktALLOWABLE_MARGIN ) ) + { + xErrorOccurred = pdTRUE; + } + + xRunIndicator = bktRUN_INDICATOR; + + xSecondaryCycles++; + } +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xAreBlockTimeTestTasksStillRunning( void ) +{ +static portBASE_TYPE xLastPrimaryCycleCount = 0, xLastSecondaryCycleCount = 0; +portBASE_TYPE xReturn = pdPASS; + + /* Have both tasks performed at least one cycle since this function was + last called? */ + if( xPrimaryCycles == xLastPrimaryCycleCount ) + { + xReturn = pdFAIL; + } + + if( xSecondaryCycles == xLastSecondaryCycleCount ) + { + xReturn = pdFAIL; + } + + if( xErrorOccurred == pdTRUE ) + { + xReturn = pdFAIL; + } + + xLastSecondaryCycleCount = xSecondaryCycles; + xLastPrimaryCycleCount = xPrimaryCycles; + + return xReturn; +} diff --git a/20080212/Demo/Common/Minimal/comtest.c b/20080212/Demo/Common/Minimal/comtest.c new file mode 100644 index 000000000..d7bc1cf8f --- /dev/null +++ b/20080212/Demo/Common/Minimal/comtest.c @@ -0,0 +1,297 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +/* + * This version of comtest. c is for use on systems that have limited stack + * space and no display facilities. The complete version can be found in + * the Demo/Common/Full directory. + * + * Creates two tasks that operate on an interrupt driven serial port. A + * loopback connector should be used so that everything that is transmitted is + * also received. The serial port does not use any flow control. On a + * standard 9way 'D' connector pins two and three should be connected together. + * + * The first task posts a sequence of characters to the Tx queue, toggling an + * LED on each successful post. At the end of the sequence it sleeps for a + * pseudo-random period before resending the same sequence. + * + * The UART Tx end interrupt is enabled whenever data is available in the Tx + * queue. The Tx end ISR removes a single character from the Tx queue and + * passes it to the UART for transmission. + * + * The second task blocks on the Rx queue waiting for a character to become + * available. When the UART Rx end interrupt receives a character it places + * it in the Rx queue, waking the second task. The second task checks that the + * characters removed from the Rx queue form the same sequence as those posted + * to the Tx queue, and toggles an LED for each correct character. + * + * The receiving task is spawned with a higher priority than the transmitting + * task. The receiver will therefore wake every time a character is + * transmitted so neither the Tx or Rx queue should ever hold more than a few + * characters. + * + */ + +/* +Changes from V1.2.0: + + + Reduced the maximum time between successive transmissions. This provides + for a more rigorous test. + +Changes from V2.0.0 + + + Delay periods are now specified using variables and constants of + portTickType rather than unsigned portLONG. + +Changes from V2.5.1 + + + The constant comOFFSET_TIME added to the delay period to ensure a more + random delay period is used. +*/ + +/* Scheduler include files. */ +#include +#include "FreeRTOS.h" +#include "task.h" + +/* Demo program include files. */ +#include "serial.h" +#include "comtest.h" +#include "partest.h" + +#define comSTACK_SIZE configMINIMAL_STACK_SIZE +#define comTX_LED_OFFSET ( 0 ) +#define comRX_LED_OFFSET ( 1 ) +#define comTOTAL_PERMISSIBLE_ERRORS ( 2 ) + +/* The Tx task will transmit the sequence of characters at a pseudo random +interval. This is the maximum and minimum block time between sends. */ +#define comTX_MAX_BLOCK_TIME ( ( portTickType ) 0x96 ) +#define comTX_MIN_BLOCK_TIME ( ( portTickType ) 0x32 ) +#define comOFFSET_TIME ( ( portTickType ) 3 ) + +/* We should find that each character can be queued for Tx immediately and we +don't have to block to send. */ +#define comNO_BLOCK ( ( portTickType ) 0 ) + +/* The Rx task will block on the Rx queue for a long period. */ +#define comRX_BLOCK_TIME ( ( portTickType ) 0xffff ) + +/* The sequence transmitted is from comFIRST_BYTE to and including comLAST_BYTE. */ +#define comFIRST_BYTE ( 'A' ) +#define comLAST_BYTE ( 'X' ) + +#define comBUFFER_LEN ( ( unsigned portBASE_TYPE ) ( comLAST_BYTE - comFIRST_BYTE ) + ( unsigned portBASE_TYPE ) 1 ) +#define comINITIAL_RX_COUNT_VALUE ( 0 ) + +/* Handle to the com port used by both tasks. */ +static xComPortHandle xPort = NULL; + +/* The transmit task as described at the top of the file. */ +static portTASK_FUNCTION_PROTO( vComTxTask, pvParameters ); + +/* The receive task as described at the top of the file. */ +static portTASK_FUNCTION_PROTO( vComRxTask, pvParameters ); + +/* The LED that should be toggled by the Rx and Tx tasks. The Rx task will +toggle LED ( uxBaseLED + comRX_LED_OFFSET). The Tx task will toggle LED +( uxBaseLED + comTX_LED_OFFSET ). */ +static unsigned portBASE_TYPE uxBaseLED = 0; + +/* Check variable used to ensure no error have occurred. The Rx task will +increment this variable after every successfully received sequence. If at any +time the sequence is incorrect the the variable will stop being incremented. */ +static volatile unsigned portBASE_TYPE uxRxLoops = comINITIAL_RX_COUNT_VALUE; + +/*-----------------------------------------------------------*/ + +void vAltStartComTestTasks( unsigned portBASE_TYPE uxPriority, unsigned portLONG ulBaudRate, unsigned portBASE_TYPE uxLED ) +{ + /* Initialise the com port then spawn the Rx and Tx tasks. */ + uxBaseLED = uxLED; + xSerialPortInitMinimal( ulBaudRate, comBUFFER_LEN ); + + /* The Tx task is spawned with a lower priority than the Rx task. */ + xTaskCreate( vComTxTask, ( signed portCHAR * ) "COMTx", comSTACK_SIZE, NULL, uxPriority - 1, ( xTaskHandle * ) NULL ); + xTaskCreate( vComRxTask, ( signed portCHAR * ) "COMRx", comSTACK_SIZE, NULL, uxPriority, ( xTaskHandle * ) NULL ); +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vComTxTask, pvParameters ) +{ +signed portCHAR cByteToSend; +portTickType xTimeToWait; + + /* Just to stop compiler warnings. */ + ( void ) pvParameters; + + for( ;; ) + { + /* Simply transmit a sequence of characters from comFIRST_BYTE to + comLAST_BYTE. */ + for( cByteToSend = comFIRST_BYTE; cByteToSend <= comLAST_BYTE; cByteToSend++ ) + { + if( xSerialPutChar( xPort, cByteToSend, comNO_BLOCK ) == pdPASS ) + { + vParTestToggleLED( uxBaseLED + comTX_LED_OFFSET ); + } + } + + /* Turn the LED off while we are not doing anything. */ + vParTestSetLED( uxBaseLED + comTX_LED_OFFSET, pdFALSE ); + + /* We have posted all the characters in the string - wait before + re-sending. Wait a pseudo-random time as this will provide a better + test. */ + xTimeToWait = xTaskGetTickCount() + comOFFSET_TIME; + + /* Make sure we don't wait too long... */ + xTimeToWait %= comTX_MAX_BLOCK_TIME; + + /* ...but we do want to wait. */ + if( xTimeToWait < comTX_MIN_BLOCK_TIME ) + { + xTimeToWait = comTX_MIN_BLOCK_TIME; + } + + vTaskDelay( xTimeToWait ); + } +} /*lint !e715 !e818 pvParameters is required for a task function even if it is not referenced. */ +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vComRxTask, pvParameters ) +{ +signed portCHAR cExpectedByte, cByteRxed; +portBASE_TYPE xResyncRequired = pdFALSE, xErrorOccurred = pdFALSE; + + /* Just to stop compiler warnings. */ + ( void ) pvParameters; + + for( ;; ) + { + /* We expect to receive the characters from comFIRST_BYTE to + comLAST_BYTE in an incrementing order. Loop to receive each byte. */ + for( cExpectedByte = comFIRST_BYTE; cExpectedByte <= comLAST_BYTE; cExpectedByte++ ) + { + /* Block on the queue that contains received bytes until a byte is + available. */ + if( xSerialGetChar( xPort, &cByteRxed, comRX_BLOCK_TIME ) ) + { + /* Was this the byte we were expecting? If so, toggle the LED, + otherwise we are out on sync and should break out of the loop + until the expected character sequence is about to restart. */ + if( cByteRxed == cExpectedByte ) + { + vParTestToggleLED( uxBaseLED + comRX_LED_OFFSET ); + } + else + { + xResyncRequired = pdTRUE; + break; /*lint !e960 Non-switch break allowed. */ + } + } + } + + /* Turn the LED off while we are not doing anything. */ + vParTestSetLED( uxBaseLED + comRX_LED_OFFSET, pdFALSE ); + + /* Did we break out of the loop because the characters were received in + an unexpected order? If so wait here until the character sequence is + about to restart. */ + if( xResyncRequired == pdTRUE ) + { + while( cByteRxed != comLAST_BYTE ) + { + /* Block until the next char is available. */ + xSerialGetChar( xPort, &cByteRxed, comRX_BLOCK_TIME ); + } + + /* Note that an error occurred which caused us to have to resync. + We use this to stop incrementing the loop counter so + sAreComTestTasksStillRunning() will return false - indicating an + error. */ + xErrorOccurred++; + + /* We have now resynced with the Tx task and can continue. */ + xResyncRequired = pdFALSE; + } + else + { + if( xErrorOccurred < comTOTAL_PERMISSIBLE_ERRORS ) + { + /* Increment the count of successful loops. As error + occurring (i.e. an unexpected character being received) will + prevent this counter being incremented for the rest of the + execution. Don't worry about mutual exclusion on this + variable - it doesn't really matter as we just want it + to change. */ + uxRxLoops++; + } + } + } +} /*lint !e715 !e818 pvParameters is required for a task function even if it is not referenced. */ +/*-----------------------------------------------------------*/ + +portBASE_TYPE xAreComTestTasksStillRunning( void ) +{ +portBASE_TYPE xReturn; + + /* If the count of successful reception loops has not changed than at + some time an error occurred (i.e. a character was received out of sequence) + and we will return false. */ + if( uxRxLoops == comINITIAL_RX_COUNT_VALUE ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + /* Reset the count of successful Rx loops. When this function is called + again we expect this to have been incremented. */ + uxRxLoops = comINITIAL_RX_COUNT_VALUE; + + return xReturn; +} + diff --git a/20080212/Demo/Common/Minimal/countsem.c b/20080212/Demo/Common/Minimal/countsem.c new file mode 100644 index 000000000..36d84045d --- /dev/null +++ b/20080212/Demo/Common/Minimal/countsem.c @@ -0,0 +1,289 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +/* + * Simple demonstration of the usage of counting semaphore. + */ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Demo program include files. */ +#include "countsem.h" + +/* The maximum count value that the semaphore used for the demo can hold. */ +#define countMAX_COUNT_VALUE ( 200 ) + +/* Constants used to indicate whether or not the semaphore should have been +created with its maximum count value, or its minimum count value. These +numbers are used to ensure that the pointers passed in as the task parameters +are valid. */ +#define countSTART_AT_MAX_COUNT ( 0xaa ) +#define countSTART_AT_ZERO ( 0x55 ) + +/* Two tasks are created for the test. One uses a semaphore created with its +count value set to the maximum, and one with the count value set to zero. */ +#define countNUM_TEST_TASKS ( 2 ) +#define countDONT_BLOCK ( 0 ) + +/*-----------------------------------------------------------*/ + +/* Flag that will be latched to pdTRUE should any unexpected behaviour be +detected in any of the tasks. */ +static portBASE_TYPE xErrorDetected = pdFALSE; + +/*-----------------------------------------------------------*/ + +/* + * The demo task. This simply counts the semaphore up to its maximum value, + * the counts it back down again. The result of each semaphore 'give' and + * 'take' is inspected, with an error being flagged if it is found not to be + * the expected result. + */ +static void prvCountingSemaphoreTask( void *pvParameters ); + +/* + * Utility function to increment the semaphore count value up from zero to + * countMAX_COUNT_VALUE. + */ +static void prvIncrementSemaphoreCount( xSemaphoreHandle xSemaphore, unsigned portBASE_TYPE *puxLoopCounter ); + +/* + * Utility function to decrement the semaphore count value up from + * countMAX_COUNT_VALUE to zero. + */ +static void prvDecrementSemaphoreCount( xSemaphoreHandle xSemaphore, unsigned portBASE_TYPE *puxLoopCounter ); + +/*-----------------------------------------------------------*/ + +/* The structure that is passed into the task as the task parameter. */ +typedef struct COUNT_SEM_STRUCT +{ + /* The semaphore to be used for the demo. */ + xSemaphoreHandle xSemaphore; + + /* Set to countSTART_AT_MAX_COUNT if the semaphore should be created with + its count value set to its max count value, or countSTART_AT_ZERO if it + should have been created with its count value set to 0. */ + unsigned portBASE_TYPE uxExpectedStartCount; + + /* Incremented on each cycle of the demo task. Used to detect a stalled + task. */ + unsigned portBASE_TYPE uxLoopCounter; +} xCountSemStruct; + +/* Two structures are defined, one is passed to each test task. */ +static xCountSemStruct xParameters[ countNUM_TEST_TASKS ]; + +/*-----------------------------------------------------------*/ + +void vStartCountingSemaphoreTasks( void ) +{ + /* Create the semaphores that we are going to use for the test/demo. The + first should be created such that it starts at its maximum count value, + the second should be created such that it starts with a count value of zero. */ + xParameters[ 0 ].xSemaphore = xSemaphoreCreateCounting( countMAX_COUNT_VALUE, countMAX_COUNT_VALUE ); + xParameters[ 0 ].uxExpectedStartCount = countSTART_AT_MAX_COUNT; + xParameters[ 0 ].uxLoopCounter = 0; + + xParameters[ 1 ].xSemaphore = xSemaphoreCreateCounting( countMAX_COUNT_VALUE, 0 ); + xParameters[ 1 ].uxExpectedStartCount = 0; + xParameters[ 1 ].uxLoopCounter = 0; + + /* Were the semaphores created? */ + if( ( xParameters[ 0 ].xSemaphore != NULL ) || ( xParameters[ 1 ].xSemaphore != NULL ) ) + { + /* Create the demo tasks, passing in the semaphore to use as the parameter. */ + xTaskCreate( prvCountingSemaphoreTask, ( signed portCHAR * ) "CNT1", configMINIMAL_STACK_SIZE, ( void * ) &( xParameters[ 0 ] ), tskIDLE_PRIORITY, NULL ); + xTaskCreate( prvCountingSemaphoreTask, ( signed portCHAR * ) "CNT2", configMINIMAL_STACK_SIZE, ( void * ) &( xParameters[ 1 ] ), tskIDLE_PRIORITY, NULL ); + } +} +/*-----------------------------------------------------------*/ + +static void prvDecrementSemaphoreCount( xSemaphoreHandle xSemaphore, unsigned portBASE_TYPE *puxLoopCounter ) +{ +unsigned portBASE_TYPE ux; + + /* If the semaphore count is at its maximum then we should not be able to + 'give' the semaphore. */ + if( xSemaphoreGive( xSemaphore ) == pdPASS ) + { + xErrorDetected = pdTRUE; + } + + /* We should be able to 'take' the semaphore countMAX_COUNT_VALUE times. */ + for( ux = 0; ux < countMAX_COUNT_VALUE; ux++ ) + { + if( xSemaphoreTake( xSemaphore, countDONT_BLOCK ) != pdPASS ) + { + /* We expected to be able to take the semaphore. */ + xErrorDetected = pdTRUE; + } + + ( *puxLoopCounter )++; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* If the semaphore count is zero then we should not be able to 'take' + the semaphore. */ + if( xSemaphoreTake( xSemaphore, countDONT_BLOCK ) == pdPASS ) + { + xErrorDetected = pdTRUE; + } +} +/*-----------------------------------------------------------*/ + +static void prvIncrementSemaphoreCount( xSemaphoreHandle xSemaphore, unsigned portBASE_TYPE *puxLoopCounter ) +{ +unsigned portBASE_TYPE ux; + + /* If the semaphore count is zero then we should not be able to 'take' + the semaphore. */ + if( xSemaphoreTake( xSemaphore, countDONT_BLOCK ) == pdPASS ) + { + xErrorDetected = pdTRUE; + } + + /* We should be able to 'give' the semaphore countMAX_COUNT_VALUE times. */ + for( ux = 0; ux < countMAX_COUNT_VALUE; ux++ ) + { + if( xSemaphoreGive( xSemaphore ) != pdPASS ) + { + /* We expected to be able to take the semaphore. */ + xErrorDetected = pdTRUE; + } + + ( *puxLoopCounter )++; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* If the semaphore count is at its maximum then we should not be able to + 'give' the semaphore. */ + if( xSemaphoreGive( xSemaphore ) == pdPASS ) + { + xErrorDetected = pdTRUE; + } +} +/*-----------------------------------------------------------*/ + +static void prvCountingSemaphoreTask( void *pvParameters ) +{ +xCountSemStruct *pxParameter; + + #ifdef USE_STDIO + void vPrintDisplayMessage( const portCHAR * const * ppcMessageToSend ); + + const portCHAR * const pcTaskStartMsg = "Counting semaphore demo started.\r\n"; + + /* Queue a message for printing to say the task has started. */ + vPrintDisplayMessage( &pcTaskStartMsg ); + #endif + + /* The semaphore to be used was passed as the parameter. */ + pxParameter = ( xCountSemStruct * ) pvParameters; + + /* Did we expect to find the semaphore already at its max count value, or + at zero? */ + if( pxParameter->uxExpectedStartCount == countSTART_AT_MAX_COUNT ) + { + prvDecrementSemaphoreCount( pxParameter->xSemaphore, &( pxParameter->uxLoopCounter ) ); + } + + /* Now we expect the semaphore count to be 0, so this time there is an + error if we can take the semaphore. */ + if( xSemaphoreTake( pxParameter->xSemaphore, 0 ) == pdPASS ) + { + xErrorDetected = pdTRUE; + } + + for( ;; ) + { + prvIncrementSemaphoreCount( pxParameter->xSemaphore, &( pxParameter->uxLoopCounter ) ); + prvDecrementSemaphoreCount( pxParameter->xSemaphore, &( pxParameter->uxLoopCounter ) ); + } +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xAreCountingSemaphoreTasksStillRunning( void ) +{ +static unsigned portBASE_TYPE uxLastCount0 = 0, uxLastCount1 = 0; +portBASE_TYPE xReturn = pdPASS; + + /* Return fail if any 'give' or 'take' did not result in the expected + behaviour. */ + if( xErrorDetected != pdFALSE ) + { + xReturn = pdFAIL; + } + + /* Return fail if either task is not still incrementing its loop counter. */ + if( uxLastCount0 == xParameters[ 0 ].uxLoopCounter ) + { + xReturn = pdFAIL; + } + else + { + uxLastCount0 = xParameters[ 0 ].uxLoopCounter; + } + + if( uxLastCount1 == xParameters[ 1 ].uxLoopCounter ) + { + xReturn = pdFAIL; + } + else + { + uxLastCount1 = xParameters[ 1 ].uxLoopCounter; + } + + return xReturn; +} + + diff --git a/20080212/Demo/Common/Minimal/crflash.c b/20080212/Demo/Common/Minimal/crflash.c new file mode 100644 index 000000000..dd3892648 --- /dev/null +++ b/20080212/Demo/Common/Minimal/crflash.c @@ -0,0 +1,223 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + * This demo application file demonstrates the use of queues to pass data + * between co-routines. + * + * N represents the number of 'fixed delay' co-routines that are created and + * is set during initialisation. + * + * N 'fixed delay' co-routines are created that just block for a fixed + * period then post the number of an LED onto a queue. Each such co-routine + * uses a different block period. A single 'flash' co-routine is also created + * that blocks on the same queue, waiting for the number of the next LED it + * should flash. Upon receiving a number it simply toggle the instructed LED + * then blocks on the queue once more. In this manner each LED from LED 0 to + * LED N-1 is caused to flash at a different rate. + * + * The 'fixed delay' co-routines are created with co-routine priority 0. The + * flash co-routine is created with co-routine priority 1. This means that + * the queue should never contain more than a single item. This is because + * posting to the queue will unblock the 'flash' co-routine, and as this has + * a priority greater than the tasks posting to the queue it is guaranteed to + * have emptied the queue and blocked once again before the queue can contain + * any more date. An error is indicated if an attempt to post data to the + * queue fails - indicating that the queue is already full. + * + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "croutine.h" +#include "queue.h" + +/* Demo application includes. */ +#include "partest.h" +#include "crflash.h" + +/* The queue should only need to be of length 1. See the description at the +top of the file. */ +#define crfQUEUE_LENGTH 1 + +#define crfFIXED_DELAY_PRIORITY 0 +#define crfFLASH_PRIORITY 1 + +/* Only one flash co-routine is created so the index is not significant. */ +#define crfFLASH_INDEX 0 + +/* Don't allow more than crfMAX_FLASH_TASKS 'fixed delay' co-routines to be +created. */ +#define crfMAX_FLASH_TASKS 8 + +/* We don't want to block when posting to the queue. */ +#define crfPOSTING_BLOCK_TIME 0 + +/* + * The 'fixed delay' co-routine as described at the top of the file. + */ +static void prvFixedDelayCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + +/* + * The 'flash' co-routine as described at the top of the file. + */ +static void prvFlashCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + +/* The queue used to pass data between the 'fixed delay' co-routines and the +'flash' co-routine. */ +static xQueueHandle xFlashQueue; + +/* This will be set to pdFALSE if we detect an error. */ +static unsigned portBASE_TYPE uxCoRoutineFlashStatus = pdPASS; + +/*-----------------------------------------------------------*/ + +/* + * See the header file for details. + */ +void vStartFlashCoRoutines( unsigned portBASE_TYPE uxNumberToCreate ) +{ +unsigned portBASE_TYPE uxIndex; + + if( uxNumberToCreate > crfMAX_FLASH_TASKS ) + { + uxNumberToCreate = crfMAX_FLASH_TASKS; + } + + /* Create the queue used to pass data between the co-routines. */ + xFlashQueue = xQueueCreate( crfQUEUE_LENGTH, sizeof( unsigned portBASE_TYPE ) ); + + if( xFlashQueue ) + { + /* Create uxNumberToCreate 'fixed delay' co-routines. */ + for( uxIndex = 0; uxIndex < uxNumberToCreate; uxIndex++ ) + { + xCoRoutineCreate( prvFixedDelayCoRoutine, crfFIXED_DELAY_PRIORITY, uxIndex ); + } + + /* Create the 'flash' co-routine. */ + xCoRoutineCreate( prvFlashCoRoutine, crfFLASH_PRIORITY, crfFLASH_INDEX ); + } +} +/*-----------------------------------------------------------*/ + +static void prvFixedDelayCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +/* Even though this is a co-routine the xResult variable does not need to be +static as we do not need it to maintain its state between blocks. */ +signed portBASE_TYPE xResult; +/* The uxIndex parameter of the co-routine function is used as an index into +the xFlashRates array to obtain the delay period to use. */ +static const portTickType xFlashRates[ crfMAX_FLASH_TASKS ] = { 150 / portTICK_RATE_MS, + 200 / portTICK_RATE_MS, + 250 / portTICK_RATE_MS, + 300 / portTICK_RATE_MS, + 350 / portTICK_RATE_MS, + 400 / portTICK_RATE_MS, + 450 / portTICK_RATE_MS, + 500 / portTICK_RATE_MS }; + + /* Co-routines MUST start with a call to crSTART. */ + crSTART( xHandle ); + + for( ;; ) + { + /* Post our uxIndex value onto the queue. This is used as the LED to + flash. */ + crQUEUE_SEND( xHandle, xFlashQueue, ( void * ) &uxIndex, crfPOSTING_BLOCK_TIME, &xResult ); + + if( xResult != pdPASS ) + { + /* For the reasons stated at the top of the file we should always + find that we can post to the queue. If we could not then an error + has occurred. */ + uxCoRoutineFlashStatus = pdFAIL; + } + + crDELAY( xHandle, xFlashRates[ uxIndex ] ); + } + + /* Co-routines MUST end with a call to crEND. */ + crEND(); +} +/*-----------------------------------------------------------*/ + +static void prvFlashCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +/* Even though this is a co-routine the variable do not need to be +static as we do not need it to maintain their state between blocks. */ +signed portBASE_TYPE xResult; +unsigned portBASE_TYPE uxLEDToFlash; + + /* Co-routines MUST start with a call to crSTART. */ + crSTART( xHandle ); + ( void ) uxIndex; + + for( ;; ) + { + /* Block to wait for the number of the LED to flash. */ + crQUEUE_RECEIVE( xHandle, xFlashQueue, &uxLEDToFlash, portMAX_DELAY, &xResult ); + + if( xResult != pdPASS ) + { + /* We would not expect to wake unless we received something. */ + uxCoRoutineFlashStatus = pdFAIL; + } + else + { + /* We received the number of an LED to flash - flash it! */ + vParTestToggleLED( uxLEDToFlash ); + } + } + + /* Co-routines MUST end with a call to crEND. */ + crEND(); +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xAreFlashCoRoutinesStillRunning( void ) +{ + /* Return pdPASS or pdFAIL depending on whether an error has been detected + or not. */ + return uxCoRoutineFlashStatus; +} + diff --git a/20080212/Demo/Common/Minimal/crhook.c b/20080212/Demo/Common/Minimal/crhook.c new file mode 100644 index 000000000..614ea819c --- /dev/null +++ b/20080212/Demo/Common/Minimal/crhook.c @@ -0,0 +1,247 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + * This demo file demonstrates how to send data between an ISR and a + * co-routine. A tick hook function is used to periodically pass data between + * the RTOS tick and a set of 'hook' co-routines. + * + * hookNUM_HOOK_CO_ROUTINES co-routines are created. Each co-routine blocks + * to wait for a character to be received on a queue from the tick ISR, checks + * to ensure the character received was that expected, then sends the number + * back to the tick ISR on a different queue. + * + * The tick ISR checks the numbers received back from the 'hook' co-routines + * matches the number previously sent. + * + * If at any time a queue function returns unexpectedly, or an incorrect value + * is received either by the tick hook or a co-routine then an error is + * latched. + * + * This demo relies on each 'hook' co-routine to execute between each + * hookTICK_CALLS_BEFORE_POST tick interrupts. This and the heavy use of + * queues from within an interrupt may result in an error being detected on + * slower targets simply due to timing. + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "croutine.h" +#include "queue.h" + +/* Demo application includes. */ +#include "crhook.h" + +/* The number of 'hook' co-routines that are to be created. */ +#define hookNUM_HOOK_CO_ROUTINES ( 4 ) + +/* The number of times the tick hook should be called before a character is +posted to the 'hook' co-routines. */ +#define hookTICK_CALLS_BEFORE_POST ( 500 ) + +/* There should never be more than one item in any queue at any time. */ +#define hookHOOK_QUEUE_LENGTH ( 1 ) + +/* Don't block when initially posting to the queue. */ +#define hookNO_BLOCK_TIME ( 0 ) + +/* The priority relative to other co-routines (rather than tasks) that the +'hook' co-routines should take. */ +#define mainHOOK_CR_PRIORITY ( 1 ) +/*-----------------------------------------------------------*/ + +/* + * The co-routine function itself. + */ +static void prvHookCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + + +/* + * The tick hook function. This receives a number from each 'hook' co-routine + * then sends a number to each co-routine. An error is flagged if a send or + * receive fails, or an unexpected number is received. + */ +void vApplicationTickHook( void ); + +/*-----------------------------------------------------------*/ + +/* Queues used to send data FROM a co-routine TO the tick hook function. +The hook functions received (Rx's) on these queues. One queue per +'hook' co-routine. */ +static xQueueHandle xHookRxQueues[ hookNUM_HOOK_CO_ROUTINES ]; + +/* Queues used to send data FROM the tick hook TO a co-routine function. +The hood function transmits (Tx's) on these queues. One queue per +'hook' co-routine. */ +static xQueueHandle xHookTxQueues[ hookNUM_HOOK_CO_ROUTINES ]; + +/* Set to true if an error is detected at any time. */ +static portBASE_TYPE xCoRoutineErrorDetected = pdFALSE; + +/*-----------------------------------------------------------*/ + +void vStartHookCoRoutines( void ) +{ +unsigned portBASE_TYPE uxIndex, uxValueToPost = 0; + + for( uxIndex = 0; uxIndex < hookNUM_HOOK_CO_ROUTINES; uxIndex++ ) + { + /* Create a queue to transmit to and receive from each 'hook' + co-routine. */ + xHookRxQueues[ uxIndex ] = xQueueCreate( hookHOOK_QUEUE_LENGTH, sizeof( unsigned portBASE_TYPE ) ); + xHookTxQueues[ uxIndex ] = xQueueCreate( hookHOOK_QUEUE_LENGTH, sizeof( unsigned portBASE_TYPE ) ); + + /* To start things off the tick hook function expects the queue it + uses to receive data to contain a value. */ + xQueueSend( xHookRxQueues[ uxIndex ], &uxValueToPost, hookNO_BLOCK_TIME ); + + /* Create the 'hook' co-routine itself. */ + xCoRoutineCreate( prvHookCoRoutine, mainHOOK_CR_PRIORITY, uxIndex ); + } +} +/*-----------------------------------------------------------*/ + +static unsigned portBASE_TYPE uxCallCounter = 0, uxNumberToPost = 0; +void vApplicationTickHook( void ) +{ +unsigned portBASE_TYPE uxReceivedNumber; +signed portBASE_TYPE xIndex, xCoRoutineWoken; + + /* Is it time to talk to the 'hook' co-routines again? */ + uxCallCounter++; + if( uxCallCounter >= hookTICK_CALLS_BEFORE_POST ) + { + uxCallCounter = 0; + + for( xIndex = 0; xIndex < hookNUM_HOOK_CO_ROUTINES; xIndex++ ) + { + xCoRoutineWoken = pdFALSE; + if( crQUEUE_RECEIVE_FROM_ISR( xHookRxQueues[ xIndex ], &uxReceivedNumber, &xCoRoutineWoken ) != pdPASS ) + { + /* There is no reason why we would not expect the queue to + contain a value. */ + xCoRoutineErrorDetected = pdTRUE; + } + else + { + /* Each queue used to receive data from the 'hook' co-routines + should contain the number we last posted to the same co-routine. */ + if( uxReceivedNumber != uxNumberToPost ) + { + xCoRoutineErrorDetected = pdTRUE; + } + + /* Nothing should be blocked waiting to post to the queue. */ + if( xCoRoutineWoken != pdFALSE ) + { + xCoRoutineErrorDetected = pdTRUE; + } + } + } + + /* Start the next cycle by posting the next number onto each Tx queue. */ + uxNumberToPost++; + + for( xIndex = 0; xIndex < hookNUM_HOOK_CO_ROUTINES; xIndex++ ) + { + if( crQUEUE_SEND_FROM_ISR( xHookTxQueues[ xIndex ], &uxNumberToPost, pdFALSE ) != pdTRUE ) + { + /* Posting to the queue should have woken the co-routine that + was blocked on the queue. */ + xCoRoutineErrorDetected = pdTRUE; + } + } + } +} +/*-----------------------------------------------------------*/ + +static void prvHookCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +static unsigned portBASE_TYPE uxReceivedValue[ hookNUM_HOOK_CO_ROUTINES ]; +portBASE_TYPE xResult; + + /* Each co-routine MUST start with a call to crSTART(); */ + crSTART( xHandle ); + + for( ;; ) + { + /* Wait to receive a value from the tick hook. */ + xResult = pdFAIL; + crQUEUE_RECEIVE( xHandle, xHookTxQueues[ uxIndex ], &( uxReceivedValue[ uxIndex ] ), portMAX_DELAY, &xResult ); + + /* There is no reason why we should not have received something on + the queue. */ + if( xResult != pdPASS ) + { + xCoRoutineErrorDetected = pdTRUE; + } + + /* Send the same number back to the idle hook so it can verify it. */ + xResult = pdFAIL; + crQUEUE_SEND( xHandle, xHookRxQueues[ uxIndex ], &( uxReceivedValue[ uxIndex ] ), hookNO_BLOCK_TIME, &xResult ); + if( xResult != pdPASS ) + { + /* There is no reason why we should not have been able to post to + the queue. */ + xCoRoutineErrorDetected = pdTRUE; + } + } + + /* Each co-routine MUST end with a call to crEND(). */ + crEND(); +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xAreHookCoRoutinesStillRunning( void ) +{ + if( xCoRoutineErrorDetected ) + { + return pdFALSE; + } + else + { + return pdTRUE; + } +} + + + diff --git a/20080212/Demo/Common/Minimal/death.c b/20080212/Demo/Common/Minimal/death.c new file mode 100644 index 000000000..cd8d421fa --- /dev/null +++ b/20080212/Demo/Common/Minimal/death.c @@ -0,0 +1,237 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/** + * Create a single persistent task which periodically dynamically creates another + * two tasks. The original task is called the creator task, the two tasks it + * creates are called suicidal tasks. + * + * One of the created suicidal tasks kill one other suicidal task before killing + * itself - leaving just the original task remaining. + * + * The creator task must be spawned after all of the other demo application tasks + * as it keeps a check on the number of tasks under the scheduler control. The + * number of tasks it expects to see running should never be greater than the + * number of tasks that were in existence when the creator task was spawned, plus + * one set of four suicidal tasks. If this number is exceeded an error is flagged. + * + * \page DeathC death.c + * \ingroup DemoFiles + *
+ */ + +/* +Changes from V3.0.0 + + CreationCount sizes changed from unsigned portBASE_TYPE to + unsigned portSHORT to minimize the risk of overflowing. + + + Reset of usLastCreationCount added + +Changes from V3.1.0 + + Changed the dummy calculation to use variables of type long, rather than + float. This allows the file to be used with ports that do not support + floating point. + +*/ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo program include files. */ +#include "death.h" + +#define deathSTACK_SIZE ( configMINIMAL_STACK_SIZE + 60 ) + +/* The task originally created which is responsible for periodically dynamically +creating another four tasks. */ +static portTASK_FUNCTION_PROTO( vCreateTasks, pvParameters ); + +/* The task function of the dynamically created tasks. */ +static portTASK_FUNCTION_PROTO( vSuicidalTask, pvParameters ); + +/* A variable which is incremented every time the dynamic tasks are created. This +is used to check that the task is still running. */ +static volatile unsigned portSHORT usCreationCount = 0; + +/* Used to store the number of tasks that were originally running so the creator +task can tell if any of the suicidal tasks have failed to die. +*/ +static volatile unsigned portBASE_TYPE uxTasksRunningAtStart = 0; + +/* Tasks are deleted by the idle task. Under heavy load the idle task might +not get much processing time, so it would be legitimate for several tasks to +remain undeleted for a short period. */ +static const unsigned portBASE_TYPE uxMaxNumberOfExtraTasksRunning = 2; + +/* Used to store a handle to the task that should be killed by a suicidal task, +before it kills itself. */ +xTaskHandle xCreatedTask; + +/*-----------------------------------------------------------*/ + +void vCreateSuicidalTasks( unsigned portBASE_TYPE uxPriority ) +{ +unsigned portBASE_TYPE *puxPriority; + + /* Create the Creator tasks - passing in as a parameter the priority at which + the suicidal tasks should be created. */ + puxPriority = ( unsigned portBASE_TYPE * ) pvPortMalloc( sizeof( unsigned portBASE_TYPE ) ); + *puxPriority = uxPriority; + + xTaskCreate( vCreateTasks, ( signed portCHAR * ) "CREATOR", deathSTACK_SIZE, ( void * ) puxPriority, uxPriority, NULL ); + + /* Record the number of tasks that are running now so we know if any of the + suicidal tasks have failed to be killed. */ + uxTasksRunningAtStart = ( unsigned portBASE_TYPE ) uxTaskGetNumberOfTasks(); + + /* FreeRTOS.org versions before V3.0 started the idle-task as the very + first task. The idle task was then already included in uxTasksRunningAtStart. + From FreeRTOS V3.0 on, the idle task is started when the scheduler is + started. Therefore the idle task is not yet accounted for. We correct + this by increasing uxTasksRunningAtStart by 1. */ + uxTasksRunningAtStart++; +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vSuicidalTask, pvParameters ) +{ +volatile portLONG l1, l2; +xTaskHandle xTaskToKill; +const portTickType xDelay = ( portTickType ) 200 / portTICK_RATE_MS; + + if( pvParameters != NULL ) + { + /* This task is periodically created four times. Two created tasks are + passed a handle to the other task so it can kill it before killing itself. + The other task is passed in null. */ + xTaskToKill = *( xTaskHandle* )pvParameters; + } + else + { + xTaskToKill = NULL; + } + + for( ;; ) + { + /* Do something random just to use some stack and registers. */ + l1 = 2; + l2 = 89; + l2 *= l1; + vTaskDelay( xDelay ); + + if( xTaskToKill != NULL ) + { + /* Make sure the other task has a go before we delete it. */ + vTaskDelay( ( portTickType ) 0 ); + + /* Kill the other task that was created by vCreateTasks(). */ + vTaskDelete( xTaskToKill ); + + /* Kill ourselves. */ + vTaskDelete( NULL ); + } + } +}/*lint !e818 !e550 Function prototype must be as per standard for task functions. */ +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vCreateTasks, pvParameters ) +{ +const portTickType xDelay = ( portTickType ) 1000 / portTICK_RATE_MS; +unsigned portBASE_TYPE uxPriority; + + uxPriority = *( unsigned portBASE_TYPE * ) pvParameters; + vPortFree( pvParameters ); + + for( ;; ) + { + /* Just loop round, delaying then creating the four suicidal tasks. */ + vTaskDelay( xDelay ); + + xCreatedTask = NULL; + + xTaskCreate( vSuicidalTask, ( signed portCHAR * ) "SUICID1", configMINIMAL_STACK_SIZE, NULL, uxPriority, &xCreatedTask ); + xTaskCreate( vSuicidalTask, ( signed portCHAR * ) "SUICID2", configMINIMAL_STACK_SIZE, &xCreatedTask, uxPriority, NULL ); + + ++usCreationCount; + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that the creator task is still running and that there +are not any more than four extra tasks. */ +portBASE_TYPE xIsCreateTaskStillRunning( void ) +{ +static portSHORT usLastCreationCount = -1; +portBASE_TYPE xReturn = pdTRUE; +static unsigned portBASE_TYPE uxTasksRunningNow; + + if( usLastCreationCount == usCreationCount ) + { + xReturn = pdFALSE; + } + else + { + usLastCreationCount = usCreationCount; + } + + uxTasksRunningNow = ( unsigned portBASE_TYPE ) uxTaskGetNumberOfTasks(); + + if( uxTasksRunningNow < uxTasksRunningAtStart ) + { + xReturn = pdFALSE; + } + else if( ( uxTasksRunningNow - uxTasksRunningAtStart ) > uxMaxNumberOfExtraTasksRunning ) + { + xReturn = pdFALSE; + } + else + { + /* Everything is okay. */ + } + + return xReturn; +} + + diff --git a/20080212/Demo/Common/Minimal/dynamic.c b/20080212/Demo/Common/Minimal/dynamic.c new file mode 100644 index 000000000..604613c46 --- /dev/null +++ b/20080212/Demo/Common/Minimal/dynamic.c @@ -0,0 +1,407 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + * The first test creates three tasks - two counter tasks (one continuous count + * and one limited count) and one controller. A "count" variable is shared + * between all three tasks. The two counter tasks should never be in a "ready" + * state at the same time. The controller task runs at the same priority as + * the continuous count task, and at a lower priority than the limited count + * task. + * + * One counter task loops indefinitely, incrementing the shared count variable + * on each iteration. To ensure it has exclusive access to the variable it + * raises it's priority above that of the controller task before each + * increment, lowering it again to it's original priority before starting the + * next iteration. + * + * The other counter task increments the shared count variable on each + * iteration of it's loop until the count has reached a limit of 0xff - at + * which point it suspends itself. It will not start a new loop until the + * controller task has made it "ready" again by calling vTaskResume (). + * This second counter task operates at a higher priority than controller + * task so does not need to worry about mutual exclusion of the counter + * variable. + * + * The controller task is in two sections. The first section controls and + * monitors the continuous count task. When this section is operational the + * limited count task is suspended. Likewise, the second section controls + * and monitors the limited count task. When this section is operational the + * continuous count task is suspended. + * + * In the first section the controller task first takes a copy of the shared + * count variable. To ensure mutual exclusion on the count variable it + * suspends the continuous count task, resuming it again when the copy has been + * taken. The controller task then sleeps for a fixed period - during which + * the continuous count task will execute and increment the shared variable. + * When the controller task wakes it checks that the continuous count task + * has executed by comparing the copy of the shared variable with its current + * value. This time, to ensure mutual exclusion, the scheduler itself is + * suspended with a call to vTaskSuspendAll (). This is for demonstration + * purposes only and is not a recommended technique due to its inefficiency. + * + * After a fixed number of iterations the controller task suspends the + * continuous count task, and moves on to its second section. + * + * At the start of the second section the shared variable is cleared to zero. + * The limited count task is then woken from it's suspension by a call to + * vTaskResume (). As this counter task operates at a higher priority than + * the controller task the controller task should not run again until the + * shared variable has been counted up to the limited value causing the counter + * task to suspend itself. The next line after vTaskResume () is therefore + * a check on the shared variable to ensure everything is as expected. + * + * + * The second test consists of a couple of very simple tasks that post onto a + * queue while the scheduler is suspended. This test was added to test parts + * of the scheduler not exercised by the first test. + * + */ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Demo app include files. */ +#include "dynamic.h" + +/* Function that implements the "limited count" task as described above. */ +static portTASK_FUNCTION_PROTO( vLimitedIncrementTask, pvParameters ); + +/* Function that implements the "continuous count" task as described above. */ +static portTASK_FUNCTION_PROTO( vContinuousIncrementTask, pvParameters ); + +/* Function that implements the controller task as described above. */ +static portTASK_FUNCTION_PROTO( vCounterControlTask, pvParameters ); + +static portTASK_FUNCTION_PROTO( vQueueReceiveWhenSuspendedTask, pvParameters ); +static portTASK_FUNCTION_PROTO( vQueueSendWhenSuspendedTask, pvParameters ); + +/* Demo task specific constants. */ +#define priSTACK_SIZE ( configMINIMAL_STACK_SIZE ) +#define priSLEEP_TIME ( ( portTickType ) 128 / portTICK_RATE_MS ) +#define priLOOPS ( 5 ) +#define priMAX_COUNT ( ( unsigned portLONG ) 0xff ) +#define priNO_BLOCK ( ( portTickType ) 0 ) +#define priSUSPENDED_QUEUE_LENGTH ( 1 ) + +/*-----------------------------------------------------------*/ + +/* Handles to the two counter tasks. These could be passed in as parameters +to the controller task to prevent them having to be file scope. */ +static xTaskHandle xContinousIncrementHandle, xLimitedIncrementHandle; + +/* The shared counter variable. This is passed in as a parameter to the two +counter variables for demonstration purposes. */ +static unsigned portLONG ulCounter; + +/* Variables used to check that the tasks are still operating without error. +Each complete iteration of the controller task increments this variable +provided no errors have been found. The variable maintaining the same value +is therefore indication of an error. */ +static unsigned portSHORT usCheckVariable = ( unsigned portSHORT ) 0; +static portBASE_TYPE xSuspendedQueueSendError = pdFALSE; +static portBASE_TYPE xSuspendedQueueReceiveError = pdFALSE; + +/* Queue used by the second test. */ +xQueueHandle xSuspendedTestQueue; + +/*-----------------------------------------------------------*/ +/* + * Start the three tasks as described at the top of the file. + * Note that the limited count task is given a higher priority. + */ +void vStartDynamicPriorityTasks( void ) +{ + xSuspendedTestQueue = xQueueCreate( priSUSPENDED_QUEUE_LENGTH, sizeof( unsigned portLONG ) ); + xTaskCreate( vContinuousIncrementTask, ( signed portCHAR * ) "CNT_INC", priSTACK_SIZE, ( void * ) &ulCounter, tskIDLE_PRIORITY, &xContinousIncrementHandle ); + xTaskCreate( vLimitedIncrementTask, ( signed portCHAR * ) "LIM_INC", priSTACK_SIZE, ( void * ) &ulCounter, tskIDLE_PRIORITY + 1, &xLimitedIncrementHandle ); + xTaskCreate( vCounterControlTask, ( signed portCHAR * ) "C_CTRL", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vQueueSendWhenSuspendedTask, ( signed portCHAR * ) "SUSP_TX", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vQueueReceiveWhenSuspendedTask, ( signed portCHAR * ) "SUSP_RX", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); +} +/*-----------------------------------------------------------*/ + +/* + * Just loops around incrementing the shared variable until the limit has been + * reached. Once the limit has been reached it suspends itself. + */ +static portTASK_FUNCTION( vLimitedIncrementTask, pvParameters ) +{ +unsigned portLONG *pulCounter; + + /* Take a pointer to the shared variable from the parameters passed into + the task. */ + pulCounter = ( unsigned portLONG * ) pvParameters; + + /* This will run before the control task, so the first thing it does is + suspend - the control task will resume it when ready. */ + vTaskSuspend( NULL ); + + for( ;; ) + { + /* Just count up to a value then suspend. */ + ( *pulCounter )++; + + if( *pulCounter >= priMAX_COUNT ) + { + vTaskSuspend( NULL ); + } + } +} +/*-----------------------------------------------------------*/ + +/* + * Just keep counting the shared variable up. The control task will suspend + * this task when it wants. + */ +static portTASK_FUNCTION( vContinuousIncrementTask, pvParameters ) +{ +unsigned portLONG *pulCounter; +unsigned portBASE_TYPE uxOurPriority; + + /* Take a pointer to the shared variable from the parameters passed into + the task. */ + pulCounter = ( unsigned portLONG * ) pvParameters; + + /* Query our priority so we can raise it when exclusive access to the + shared variable is required. */ + uxOurPriority = uxTaskPriorityGet( NULL ); + + for( ;; ) + { + /* Raise our priority above the controller task to ensure a context + switch does not occur while we are accessing this variable. */ + vTaskPrioritySet( NULL, uxOurPriority + 1 ); + ( *pulCounter )++; + vTaskPrioritySet( NULL, uxOurPriority ); + } +} +/*-----------------------------------------------------------*/ + +/* + * Controller task as described above. + */ +static portTASK_FUNCTION( vCounterControlTask, pvParameters ) +{ +unsigned portLONG ulLastCounter; +portSHORT sLoops; +portSHORT sError = pdFALSE; + + /* Just to stop warning messages. */ + ( void ) pvParameters; + + for( ;; ) + { + /* Start with the counter at zero. */ + ulCounter = ( unsigned portLONG ) 0; + + /* First section : */ + + /* Check the continuous count task is running. */ + for( sLoops = 0; sLoops < priLOOPS; sLoops++ ) + { + /* Suspend the continuous count task so we can take a mirror of the + shared variable without risk of corruption. */ + vTaskSuspend( xContinousIncrementHandle ); + ulLastCounter = ulCounter; + vTaskResume( xContinousIncrementHandle ); + + /* Now delay to ensure the other task has processor time. */ + vTaskDelay( priSLEEP_TIME ); + + /* Check the shared variable again. This time to ensure mutual + exclusion the whole scheduler will be locked. This is just for + demo purposes! */ + vTaskSuspendAll(); + { + if( ulLastCounter == ulCounter ) + { + /* The shared variable has not changed. There is a problem + with the continuous count task so flag an error. */ + sError = pdTRUE; + } + } + xTaskResumeAll(); + } + + + /* Second section: */ + + /* Suspend the continuous counter task so it stops accessing the shared variable. */ + vTaskSuspend( xContinousIncrementHandle ); + + /* Reset the variable. */ + ulCounter = ( unsigned portLONG ) 0; + + /* Resume the limited count task which has a higher priority than us. + We should therefore not return from this call until the limited count + task has suspended itself with a known value in the counter variable. */ + vTaskResume( xLimitedIncrementHandle ); + + /* Does the counter variable have the expected value? */ + if( ulCounter != priMAX_COUNT ) + { + sError = pdTRUE; + } + + if( sError == pdFALSE ) + { + /* If no errors have occurred then increment the check variable. */ + portENTER_CRITICAL(); + usCheckVariable++; + portEXIT_CRITICAL(); + } + + /* Resume the continuous count task and do it all again. */ + vTaskResume( xContinousIncrementHandle ); + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vQueueSendWhenSuspendedTask, pvParameters ) +{ +static unsigned portLONG ulValueToSend = ( unsigned portLONG ) 0; + + /* Just to stop warning messages. */ + ( void ) pvParameters; + + for( ;; ) + { + vTaskSuspendAll(); + { + /* We must not block while the scheduler is suspended! */ + if( xQueueSend( xSuspendedTestQueue, ( void * ) &ulValueToSend, priNO_BLOCK ) != pdTRUE ) + { + xSuspendedQueueSendError = pdTRUE; + } + } + xTaskResumeAll(); + + vTaskDelay( priSLEEP_TIME ); + + ++ulValueToSend; + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vQueueReceiveWhenSuspendedTask, pvParameters ) +{ +static unsigned portLONG ulExpectedValue = ( unsigned portLONG ) 0, ulReceivedValue; +portBASE_TYPE xGotValue; + + /* Just to stop warning messages. */ + ( void ) pvParameters; + + for( ;; ) + { + do + { + /* Suspending the scheduler here is fairly pointless and + undesirable for a normal application. It is done here purely + to test the scheduler. The inner xTaskResumeAll() should + never return pdTRUE as the scheduler is still locked by the + outer call. */ + vTaskSuspendAll(); + { + vTaskSuspendAll(); + { + xGotValue = xQueueReceive( xSuspendedTestQueue, ( void * ) &ulReceivedValue, priNO_BLOCK ); + } + if( xTaskResumeAll() ) + { + xSuspendedQueueReceiveError = pdTRUE; + } + } + xTaskResumeAll(); + + #if configUSE_PREEMPTION == 0 + { + taskYIELD(); + } + #endif + + } while( xGotValue == pdFALSE ); + + if( ulReceivedValue != ulExpectedValue ) + { + xSuspendedQueueReceiveError = pdTRUE; + } + + ++ulExpectedValue; + } +} +/*-----------------------------------------------------------*/ + +/* Called to check that all the created tasks are still running without error. */ +portBASE_TYPE xAreDynamicPriorityTasksStillRunning( void ) +{ +/* Keep a history of the check variables so we know if it has been incremented +since the last call. */ +static unsigned portSHORT usLastTaskCheck = ( unsigned portSHORT ) 0; +portBASE_TYPE xReturn = pdTRUE; + + /* Check the tasks are still running by ensuring the check variable + is still incrementing. */ + + if( usCheckVariable == usLastTaskCheck ) + { + /* The check has not incremented so an error exists. */ + xReturn = pdFALSE; + } + + if( xSuspendedQueueSendError == pdTRUE ) + { + xReturn = pdFALSE; + } + + if( xSuspendedQueueReceiveError == pdTRUE ) + { + xReturn = pdFALSE; + } + + usLastTaskCheck = usCheckVariable; + return xReturn; +} diff --git a/20080212/Demo/Common/Minimal/flash.c b/20080212/Demo/Common/Minimal/flash.c new file mode 100644 index 000000000..d9d2969a9 --- /dev/null +++ b/20080212/Demo/Common/Minimal/flash.c @@ -0,0 +1,148 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/** + * This version of flash .c is for use on systems that have limited stack space + * and no display facilities. The complete version can be found in the + * Demo/Common/Full directory. + * + * Three tasks are created, each of which flash an LED at a different rate. The first + * LED flashes every 200ms, the second every 400ms, the third every 600ms. + * + * The LED flash tasks provide instant visual feedback. They show that the scheduler + * is still operational. + * + * The PC port uses the standard parallel port for outputs, the Flashlite 186 port + * uses IO port F and the AVR port port B. + * + */ + +/* +Changes from V2.0.0 + + + Delay periods are now specified using variables and constants of + portTickType rather than unsigned portLONG. + +Changes from V2.5.5 + + + Calls to vTaskDelay() have been replaced with vTaskDelayUntil(). + +*/ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo program include files. */ +#include "partest.h" +#include "flash.h" + +#define ledSTACK_SIZE configMINIMAL_STACK_SIZE +#define ledNUMBER_OF_LEDS ( 3 ) +#define ledFLASH_RATE_BASE ( ( portTickType ) 333 ) + +/* Variable used by the created tasks to calculate the LED number to use, and +the rate at which they should flash the LED. */ +static volatile unsigned portBASE_TYPE uxFlashTaskNumber = 0; + +/* The task that is created three times. */ +static portTASK_FUNCTION_PROTO( vLEDFlashTask, pvParameters ); + +/*-----------------------------------------------------------*/ + +void vStartLEDFlashTasks( unsigned portBASE_TYPE uxPriority ) +{ +signed portBASE_TYPE xLEDTask; + + /* Create the three tasks. */ + for( xLEDTask = 0; xLEDTask < ledNUMBER_OF_LEDS; ++xLEDTask ) + { + /* Spawn the task. */ + xTaskCreate( vLEDFlashTask, ( signed portCHAR * ) "LEDx", ledSTACK_SIZE, NULL, uxPriority, ( xTaskHandle * ) NULL ); + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vLEDFlashTask, pvParameters ) +{ +portTickType xFlashRate, xLastFlashTime; +unsigned portBASE_TYPE uxLED; + + /* The parameters are not used. */ + ( void ) pvParameters; + + /* Calculate the LED and flash rate. */ + portENTER_CRITICAL(); + { + /* See which of the eight LED's we should use. */ + uxLED = uxFlashTaskNumber; + + /* Update so the next task uses the next LED. */ + uxFlashTaskNumber++; + } + portEXIT_CRITICAL(); + + xFlashRate = ledFLASH_RATE_BASE + ( ledFLASH_RATE_BASE * ( portTickType ) uxLED ); + xFlashRate /= portTICK_RATE_MS; + + /* We will turn the LED on and off again in the delay period, so each + delay is only half the total period. */ + xFlashRate /= ( portTickType ) 2; + + /* We need to initialise xLastFlashTime prior to the first call to + vTaskDelayUntil(). */ + xLastFlashTime = xTaskGetTickCount(); + + for(;;) + { + /* Delay for half the flash period then turn the LED on. */ + vTaskDelayUntil( &xLastFlashTime, xFlashRate ); + vParTestToggleLED( uxLED ); + + /* Delay for half the flash period then turn the LED off. */ + vTaskDelayUntil( &xLastFlashTime, xFlashRate ); + vParTestToggleLED( uxLED ); + } +} /*lint !e715 !e818 !e830 Function definition must be standard for task creation. */ + diff --git a/20080212/Demo/Common/Minimal/flop.c b/20080212/Demo/Common/Minimal/flop.c new file mode 100644 index 000000000..14f0832a9 --- /dev/null +++ b/20080212/Demo/Common/Minimal/flop.c @@ -0,0 +1,340 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + * Creates eight tasks, each of which loops continuously performing an (emulated) + * floating point calculation. + * + * All the tasks run at the idle priority and never block or yield. This causes + * all eight tasks to time slice with the idle task. Running at the idle priority + * means that these tasks will get pre-empted any time another task is ready to run + * or a time slice occurs. More often than not the pre-emption will occur mid + * calculation, creating a good test of the schedulers context switch mechanism - a + * calculation producing an unexpected result could be a symptom of a corruption in + * the context of a task. + */ + +#include +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo program include files. */ +#include "flop.h" + +#define mathSTACK_SIZE configMINIMAL_STACK_SIZE +#define mathNUMBER_OF_TASKS ( 8 ) + +/* Four tasks, each of which performs a different floating point calculation. +Each of the four is created twice. */ +static portTASK_FUNCTION_PROTO( vCompetingMathTask1, pvParameters ); +static portTASK_FUNCTION_PROTO( vCompetingMathTask2, pvParameters ); +static portTASK_FUNCTION_PROTO( vCompetingMathTask3, pvParameters ); +static portTASK_FUNCTION_PROTO( vCompetingMathTask4, pvParameters ); + +/* These variables are used to check that all the tasks are still running. If a +task gets a calculation wrong it will +stop incrementing its check variable. */ +static volatile unsigned portSHORT usTaskCheck[ mathNUMBER_OF_TASKS ] = { ( unsigned portSHORT ) 0 }; + +/*-----------------------------------------------------------*/ + +void vStartMathTasks( unsigned portBASE_TYPE uxPriority ) +{ + xTaskCreate( vCompetingMathTask1, ( signed portCHAR * ) "Math1", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 0 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask2, ( signed portCHAR * ) "Math2", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 1 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask3, ( signed portCHAR * ) "Math3", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 2 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask4, ( signed portCHAR * ) "Math4", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 3 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask1, ( signed portCHAR * ) "Math5", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 4 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask2, ( signed portCHAR * ) "Math6", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 5 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask3, ( signed portCHAR * ) "Math7", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 6 ] ), uxPriority, NULL ); + xTaskCreate( vCompetingMathTask4, ( signed portCHAR * ) "Math8", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 7 ] ), uxPriority, NULL ); +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vCompetingMathTask1, pvParameters ) +{ +volatile portDOUBLE d1, d2, d3, d4; +volatile unsigned portSHORT *pusTaskCheckVariable; +volatile portDOUBLE dAnswer; +portSHORT sError = pdFALSE; + + d1 = 123.4567; + d2 = 2345.6789; + d3 = -918.222; + + dAnswer = ( d1 + d2 ) * d3; + + /* The variable this task increments to show it is still running is passed in + as the parameter. */ + pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters; + + /* Keep performing a calculation and checking the result against a constant. */ + for(;;) + { + d1 = 123.4567; + d2 = 2345.6789; + d3 = -918.222; + + d4 = ( d1 + d2 ) * d3; + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* If the calculation does not match the expected constant, stop the + increment of the check variable. */ + if( fabs( d4 - dAnswer ) > 0.001 ) + { + sError = pdTRUE; + } + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + variable so we know this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vCompetingMathTask2, pvParameters ) +{ +volatile portDOUBLE d1, d2, d3, d4; +volatile unsigned portSHORT *pusTaskCheckVariable; +volatile portDOUBLE dAnswer; +portSHORT sError = pdFALSE; + + d1 = -389.38; + d2 = 32498.2; + d3 = -2.0001; + + dAnswer = ( d1 / d2 ) * d3; + + + /* The variable this task increments to show it is still running is passed in + as the parameter. */ + pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters; + + /* Keep performing a calculation and checking the result against a constant. */ + for( ;; ) + { + d1 = -389.38; + d2 = 32498.2; + d3 = -2.0001; + + d4 = ( d1 / d2 ) * d3; + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* If the calculation does not match the expected constant, stop the + increment of the check variable. */ + if( fabs( d4 - dAnswer ) > 0.001 ) + { + sError = pdTRUE; + } + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + variable so we know + this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vCompetingMathTask3, pvParameters ) +{ +volatile portDOUBLE *pdArray, dTotal1, dTotal2, dDifference; +volatile unsigned portSHORT *pusTaskCheckVariable; +const size_t xArraySize = 10; +size_t xPosition; +portSHORT sError = pdFALSE; + + /* The variable this task increments to show it is still running is passed in + as the parameter. */ + pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters; + + pdArray = ( portDOUBLE * ) pvPortMalloc( xArraySize * sizeof( portDOUBLE ) ); + + /* Keep filling an array, keeping a running total of the values placed in the + array. Then run through the array adding up all the values. If the two totals + do not match, stop the check variable from incrementing. */ + for( ;; ) + { + dTotal1 = 0.0; + dTotal2 = 0.0; + + for( xPosition = 0; xPosition < xArraySize; xPosition++ ) + { + pdArray[ xPosition ] = ( portDOUBLE ) xPosition + 5.5; + dTotal1 += ( portDOUBLE ) xPosition + 5.5; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + for( xPosition = 0; xPosition < xArraySize; xPosition++ ) + { + dTotal2 += pdArray[ xPosition ]; + } + + dDifference = dTotal1 - dTotal2; + if( fabs( dDifference ) > 0.001 ) + { + sError = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + variable so we know this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vCompetingMathTask4, pvParameters ) +{ +volatile portDOUBLE *pdArray, dTotal1, dTotal2, dDifference; +volatile unsigned portSHORT *pusTaskCheckVariable; +const size_t xArraySize = 10; +size_t xPosition; +portSHORT sError = pdFALSE; + + /* The variable this task increments to show it is still running is passed in + as the parameter. */ + pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters; + + pdArray = ( portDOUBLE * ) pvPortMalloc( xArraySize * sizeof( portDOUBLE ) ); + + /* Keep filling an array, keeping a running total of the values placed in the + array. Then run through the array adding up all the values. If the two totals + do not match, stop the check variable from incrementing. */ + for( ;; ) + { + dTotal1 = 0.0; + dTotal2 = 0.0; + + for( xPosition = 0; xPosition < xArraySize; xPosition++ ) + { + pdArray[ xPosition ] = ( portDOUBLE ) xPosition * 12.123; + dTotal1 += ( portDOUBLE ) xPosition * 12.123; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + for( xPosition = 0; xPosition < xArraySize; xPosition++ ) + { + dTotal2 += pdArray[ xPosition ]; + } + + dDifference = dTotal1 - dTotal2; + if( fabs( dDifference ) > 0.001 ) + { + sError = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + variable so we know this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +portBASE_TYPE xAreMathsTaskStillRunning( void ) +{ +/* Keep a history of the check variables so we know if they have been incremented +since the last call. */ +static unsigned portSHORT usLastTaskCheck[ mathNUMBER_OF_TASKS ] = { ( unsigned portSHORT ) 0 }; +portBASE_TYPE xReturn = pdTRUE, xTask; + + /* Check the maths tasks are still running by ensuring their check variables + are still incrementing. */ + for( xTask = 0; xTask < mathNUMBER_OF_TASKS; xTask++ ) + { + if( usTaskCheck[ xTask ] == usLastTaskCheck[ xTask ] ) + { + /* The check has not incremented so an error exists. */ + xReturn = pdFALSE; + } + + usLastTaskCheck[ xTask ] = usTaskCheck[ xTask ]; + } + + return xReturn; +} + + + diff --git a/20080212/Demo/Common/Minimal/integer.c b/20080212/Demo/Common/Minimal/integer.c new file mode 100644 index 000000000..f2d264cca --- /dev/null +++ b/20080212/Demo/Common/Minimal/integer.c @@ -0,0 +1,201 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + * This version of integer. c is for use on systems that have limited stack + * space and no display facilities. The complete version can be found in + * the Demo/Common/Full directory. + * + * As with the full version, the tasks created in this file are a good test + * of the scheduler context switch mechanism. The processor has to access + * 32bit variables in two or four chunks (depending on the processor). The low + * priority of these tasks means there is a high probability that a context + * switch will occur mid calculation. See flop. c documentation for + * more information. + * + */ + +/* +Changes from V1.2.1 + + + The constants used in the calculations are larger to ensure the + optimiser does not truncate them to 16 bits. + +Changes from V1.2.3 + + + uxTaskCheck is now just used as a boolean. Instead of incrementing + the variable each cycle of the task, the variable is simply set to + true. sAreIntegerMathsTaskStillRunning() sets it back to false and + expects it to have been set back to true by the time it is called + again. + + A division has been included in the calculation. +*/ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo program include files. */ +#include "integer.h" + +/* The constants used in the calculation. */ +#define intgCONST1 ( ( portLONG ) 123 ) +#define intgCONST2 ( ( portLONG ) 234567 ) +#define intgCONST3 ( ( portLONG ) -3 ) +#define intgCONST4 ( ( portLONG ) 7 ) +#define intgEXPECTED_ANSWER ( ( ( intgCONST1 + intgCONST2 ) * intgCONST3 ) / intgCONST4 ) + +#define intgSTACK_SIZE configMINIMAL_STACK_SIZE + +/* As this is the minimal version, we will only create one task. */ +#define intgNUMBER_OF_TASKS ( 1 ) + +/* The task function. Repeatedly performs a 32 bit calculation, checking the +result against the expected result. If the result is incorrect then the +context switch must have caused some corruption. */ +static portTASK_FUNCTION_PROTO( vCompeteingIntMathTask, pvParameters ); + +/* Variables that are set to true within the calculation task to indicate +that the task is still executing. The check task sets the variable back to +false, flagging an error if the variable is still false the next time it +is called. */ +static volatile signed portBASE_TYPE xTaskCheck[ intgNUMBER_OF_TASKS ] = { ( signed portBASE_TYPE ) pdFALSE }; + +/*-----------------------------------------------------------*/ + +void vStartIntegerMathTasks( unsigned portBASE_TYPE uxPriority ) +{ +portSHORT sTask; + + for( sTask = 0; sTask < intgNUMBER_OF_TASKS; sTask++ ) + { + xTaskCreate( vCompeteingIntMathTask, ( signed portCHAR * ) "IntMath", intgSTACK_SIZE, ( void * ) &( xTaskCheck[ sTask ] ), uxPriority, ( xTaskHandle * ) NULL ); + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vCompeteingIntMathTask, pvParameters ) +{ +/* These variables are all effectively set to constants so they are volatile to +ensure the compiler does not just get rid of them. */ +volatile portLONG lValue; +portSHORT sError = pdFALSE; +volatile signed portBASE_TYPE *pxTaskHasExecuted; + + /* Set a pointer to the variable we are going to set to true each + iteration. This is also a good test of the parameter passing mechanism + within each port. */ + pxTaskHasExecuted = ( volatile signed portBASE_TYPE * ) pvParameters; + + /* Keep performing a calculation and checking the result against a constant. */ + for( ;; ) + { + /* Perform the calculation. This will store partial value in + registers, resulting in a good test of the context switch mechanism. */ + lValue = intgCONST1; + lValue += intgCONST2; + + /* Yield in case cooperative scheduling is being used. */ + #if configUSE_PREEMPTION == 0 + { + taskYIELD(); + } + #endif + + /* Finish off the calculation. */ + lValue *= intgCONST3; + lValue /= intgCONST4; + + /* If the calculation is found to be incorrect we stop setting the + TaskHasExecuted variable so the check task can see an error has + occurred. */ + if( lValue != intgEXPECTED_ANSWER ) /*lint !e774 volatile used to prevent this being optimised out. */ + { + sError = pdTRUE; + } + + if( sError == pdFALSE ) + { + /* We have not encountered any errors, so set the flag that show + we are still executing. This will be periodically cleared by + the check task. */ + portENTER_CRITICAL(); + *pxTaskHasExecuted = pdTRUE; + portEXIT_CRITICAL(); + } + + /* Yield in case cooperative scheduling is being used. */ + #if configUSE_PREEMPTION == 0 + { + taskYIELD(); + } + #endif + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +portBASE_TYPE xAreIntegerMathsTaskStillRunning( void ) +{ +portBASE_TYPE xReturn = pdTRUE; +portSHORT sTask; + + /* Check the maths tasks are still running by ensuring their check variables + are still being set to true. */ + for( sTask = 0; sTask < intgNUMBER_OF_TASKS; sTask++ ) + { + if( xTaskCheck[ sTask ] == pdFALSE ) + { + /* The check has not incremented so an error exists. */ + xReturn = pdFALSE; + } + + /* Reset the check variable so we can tell if it has been set by + the next time around. */ + xTaskCheck[ sTask ] = pdFALSE; + } + + return xReturn; +} + diff --git a/20080212/Demo/Common/Minimal/recmutex.c b/20080212/Demo/Common/Minimal/recmutex.c new file mode 100644 index 000000000..755505cd9 --- /dev/null +++ b/20080212/Demo/Common/Minimal/recmutex.c @@ -0,0 +1,340 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + The tasks defined on this page demonstrate the use of recursive mutexes. + + For recursive mutex functionality the created mutex should be created using + xSemaphoreCreateRecursiveMutex(), then be manipulated + using the xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() API + functions. + + This demo creates three tasks all of which access the same recursive mutex: + + prvRecursiveMutexControllingTask() has the highest priority so executes + first and grabs the mutex. It then performs some recursive accesses - + between each of which it sleeps for a short period to let the lower + priority tasks execute. When it has completed its demo functionality + it gives the mutex back before suspending itself. + + prvRecursiveMutexBlockingTask() attempts to access the mutex by performing + a blocking 'take'. The blocking task has a lower priority than the + controlling task so by the time it executes the mutex has already been + taken by the controlling task, causing the blocking task to block. It + does not unblock until the controlling task has given the mutex back, + and it does not actually run until the controlling task has suspended + itself (due to the relative priorities). When it eventually does obtain + the mutex all it does is give the mutex back prior to also suspending + itself. At this point both the controlling task and the blocking task are + suspended. + + prvRecursiveMutexPollingTask() runs at the idle priority. It spins round + a tight loop attempting to obtain the mutex with a non-blocking call. As + the lowest priority task it will not successfully obtain the mutex until + both the controlling and blocking tasks are suspended. Once it eventually + does obtain the mutex it first unsuspends both the controlling task and + blocking task prior to giving the mutex back - resulting in the polling + task temporarily inheriting the controlling tasks priority. +*/ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Demo app include files. */ +#include "recmutex.h" + +/* Priorities assigned to the three tasks. */ +#define recmuCONTROLLING_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define recmuBLOCKING_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define recmuPOLLING_TASK_PRIORITY ( tskIDLE_PRIORITY + 0 ) + +/* The recursive call depth. */ +#define recmuMAX_COUNT ( 10 ) + +/* Misc. */ +#define recmuSHORT_DELAY ( 20 / portTICK_RATE_MS ) +#define recmuNO_DELAY ( ( portTickType ) 0 ) +#define recmuONE_TICK_DELAY ( ( portTickType ) 1 ) + +/* The three tasks as described at the top of this file. */ +static void prvRecursiveMutexControllingTask( void *pvParameters ); +static void prvRecursiveMutexBlockingTask( void *pvParameters ); +static void prvRecursiveMutexPollingTask( void *pvParameters ); + +/* The mutex used by the demo. */ +static xSemaphoreHandle xMutex; + +/* Variables used to detect and latch errors. */ +static portBASE_TYPE xErrorOccurred = pdFALSE, xControllingIsSuspended = pdFALSE, xBlockingIsSuspended = pdFALSE; +static unsigned portBASE_TYPE uxControllingCycles = 0, uxBlockingCycles, uxPollingCycles = 0; + +/* Handles of the two higher priority tasks, required so they can be resumed +(unsuspended). */ +static xTaskHandle xControllingTaskHandle, xBlockingTaskHandle; + +/*-----------------------------------------------------------*/ + +void vStartRecursiveMutexTasks( void ) +{ + /* Just creates the mutex and the three tasks. */ + + xMutex = xSemaphoreCreateRecursiveMutex(); + + if( xMutex != NULL ) + { + xTaskCreate( prvRecursiveMutexControllingTask, "Rec1", configMINIMAL_STACK_SIZE, NULL, recmuCONTROLLING_TASK_PRIORITY, &xControllingTaskHandle ); + xTaskCreate( prvRecursiveMutexBlockingTask, "Rec2", configMINIMAL_STACK_SIZE, NULL, recmuBLOCKING_TASK_PRIORITY, &xBlockingTaskHandle ); + xTaskCreate( prvRecursiveMutexPollingTask, "Rec3", configMINIMAL_STACK_SIZE, NULL, recmuPOLLING_TASK_PRIORITY, NULL ); + } +} +/*-----------------------------------------------------------*/ + +static void prvRecursiveMutexControllingTask( void *pvParameters ) +{ +unsigned portBASE_TYPE ux; + + for( ;; ) + { + /* Should not be able to 'give' the mutex, as we have not yet 'taken' + it. */ + if( xSemaphoreGiveRecursive( xMutex ) == pdPASS ) + { + xErrorOccurred = pdTRUE; + } + + for( ux = 0; ux < recmuMAX_COUNT; ux++ ) + { + /* We should now be able to take the mutex as many times as + we like. A one tick delay is used so the polling task will + inherit our priority on all but the first cycle of this task. + If we did not block attempting to receive the mutex then no + priority inheritance would occur. */ + if( xSemaphoreTakeRecursive( xMutex, recmuONE_TICK_DELAY ) != pdPASS ) + { + xErrorOccurred = pdTRUE; + } + + /* Ensure the other task attempting to access the mutex (and the + other demo tasks) are able to execute. */ + vTaskDelay( recmuSHORT_DELAY ); + } + + /* For each time we took the mutex, give it back. */ + for( ux = 0; ux < recmuMAX_COUNT; ux++ ) + { + /* Ensure the other task attempting to access the mutex (and the + other demo tasks) are able to execute. */ + vTaskDelay( recmuSHORT_DELAY ); + + /* We should now be able to give the mutex as many times as we + took it. */ + if( xSemaphoreGiveRecursive( xMutex ) != pdPASS ) + { + xErrorOccurred = pdTRUE; + } + } + + /* Having given it back the same number of times as it was taken, we + should no longer be the mutex owner, so the next give should fail. */ + if( xSemaphoreGiveRecursive( xMutex ) == pdPASS ) + { + xErrorOccurred = pdTRUE; + } + + /* Keep count of the number of cycles this task has performed so a + stall can be detected. */ + uxControllingCycles++; + + /* Suspend ourselves to the blocking task can execute. */ + xControllingIsSuspended = pdTRUE; + vTaskSuspend( NULL ); + xControllingIsSuspended = pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +static void prvRecursiveMutexBlockingTask( void *pvParameters ) +{ + for( ;; ) + { + /* Attempt to obtain the mutex. We should block until the + controlling task has given up the mutex, and not actually execute + past this call until the controlling task is suspended. */ + if( xSemaphoreTakeRecursive( xMutex, portMAX_DELAY ) == pdPASS ) + { + if( xControllingIsSuspended != pdTRUE ) + { + /* Did not expect to execute until the controlling task was + suspended. */ + xErrorOccurred = pdTRUE; + } + else + { + /* Give the mutex back before suspending ourselves to allow + the polling task to obtain the mutex. */ + if( xSemaphoreGiveRecursive( xMutex ) != pdPASS ) + { + xErrorOccurred = pdTRUE; + } + + xBlockingIsSuspended = pdTRUE; + vTaskSuspend( NULL ); + xBlockingIsSuspended = pdFALSE; + } + } + else + { + /* We should not leave the xSemaphoreTakeRecursive() function + until the mutex was obtained. */ + xErrorOccurred = pdTRUE; + } + + /* The controlling and blocking tasks should be in lock step. */ + if( uxControllingCycles != ( uxBlockingCycles + 1 ) ) + { + xErrorOccurred = pdTRUE; + } + + /* Keep count of the number of cycles this task has performed so a + stall can be detected. */ + uxBlockingCycles++; + } +} +/*-----------------------------------------------------------*/ + +static void prvRecursiveMutexPollingTask( void *pvParameters ) +{ + for( ;; ) + { + /* Keep attempting to obtain the mutex. We should only obtain it when + the blocking task has suspended itself. */ + if( xSemaphoreTakeRecursive( xMutex, recmuNO_DELAY ) == pdPASS ) + { + /* Is the blocking task suspended? */ + if( xBlockingIsSuspended != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + else + { + /* Keep count of the number of cycles this task has performed so + a stall can be detected. */ + uxPollingCycles++; + + /* We can resume the other tasks here even though they have a + higher priority than the polling task. When they execute they + will attempt to obtain the mutex but fail because the polling + task is still the mutex holder. The polling task (this task) + will then inherit the higher priority. */ + vTaskResume( xBlockingTaskHandle ); + vTaskResume( xControllingTaskHandle ); + + /* Release the mutex, disinheriting the higher priority again. */ + if( xSemaphoreGiveRecursive( xMutex ) != pdPASS ) + { + xErrorOccurred = pdTRUE; + } + } + } + + #if configUSE_PREEMPTION == 0 + { + taskYIELD(); + } + #endif + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +portBASE_TYPE xAreRecursiveMutexTasksStillRunning( void ) +{ +portBASE_TYPE xReturn; +static unsigned portBASE_TYPE uxLastControllingCycles = 0, uxLastBlockingCycles = 0, uxLastPollingCycles = 0; + + /* Is the controlling task still cycling? */ + if( uxLastControllingCycles == uxControllingCycles ) + { + xErrorOccurred = pdTRUE; + } + else + { + uxLastControllingCycles = uxControllingCycles; + } + + /* Is the blocking task still cycling? */ + if( uxLastBlockingCycles == uxBlockingCycles ) + { + xErrorOccurred = pdTRUE; + } + else + { + uxLastBlockingCycles = uxBlockingCycles; + } + + /* Is the polling task still cycling? */ + if( uxLastPollingCycles == uxPollingCycles ) + { + xErrorOccurred = pdTRUE; + } + else + { + uxLastPollingCycles = uxPollingCycles; + } + + if( xErrorOccurred == pdTRUE ) + { + xReturn = pdFAIL; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} + + + + diff --git a/20080212/Demo/Common/Minimal/semtest.c b/20080212/Demo/Common/Minimal/semtest.c new file mode 100644 index 000000000..323589c06 --- /dev/null +++ b/20080212/Demo/Common/Minimal/semtest.c @@ -0,0 +1,264 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + * Creates two sets of two tasks. The tasks within a set share a variable, access + * to which is guarded by a semaphore. + * + * Each task starts by attempting to obtain the semaphore. On obtaining a + * semaphore a task checks to ensure that the guarded variable has an expected + * value. It then clears the variable to zero before counting it back up to the + * expected value in increments of 1. After each increment the variable is checked + * to ensure it contains the value to which it was just set. When the starting + * value is again reached the task releases the semaphore giving the other task in + * the set a chance to do exactly the same thing. The starting value is high + * enough to ensure that a tick is likely to occur during the incrementing loop. + * + * An error is flagged if at any time during the process a shared variable is + * found to have a value other than that expected. Such an occurrence would + * suggest an error in the mutual exclusion mechanism by which access to the + * variable is restricted. + * + * The first set of two tasks poll their semaphore. The second set use blocking + * calls. + * + */ + + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Demo app include files. */ +#include "semtest.h" + +/* The value to which the shared variables are counted. */ +#define semtstBLOCKING_EXPECTED_VALUE ( ( unsigned portLONG ) 0xfff ) +#define semtstNON_BLOCKING_EXPECTED_VALUE ( ( unsigned portLONG ) 0xff ) + +#define semtstSTACK_SIZE configMINIMAL_STACK_SIZE + +#define semtstNUM_TASKS ( 4 ) + +#define semtstDELAY_FACTOR ( ( portTickType ) 10 ) + +/* The task function as described at the top of the file. */ +static portTASK_FUNCTION_PROTO( prvSemaphoreTest, pvParameters ); + +/* Structure used to pass parameters to each task. */ +typedef struct SEMAPHORE_PARAMETERS +{ + xSemaphoreHandle xSemaphore; + volatile unsigned portLONG *pulSharedVariable; + portTickType xBlockTime; +} xSemaphoreParameters; + +/* Variables used to check that all the tasks are still running without errors. */ +static volatile portSHORT sCheckVariables[ semtstNUM_TASKS ] = { 0 }; +static volatile portSHORT sNextCheckVariable = 0; + +/*-----------------------------------------------------------*/ + +void vStartSemaphoreTasks( unsigned portBASE_TYPE uxPriority ) +{ +xSemaphoreParameters *pxFirstSemaphoreParameters, *pxSecondSemaphoreParameters; +const portTickType xBlockTime = ( portTickType ) 100; + + /* Create the structure used to pass parameters to the first two tasks. */ + pxFirstSemaphoreParameters = ( xSemaphoreParameters * ) pvPortMalloc( sizeof( xSemaphoreParameters ) ); + + if( pxFirstSemaphoreParameters != NULL ) + { + /* Create the semaphore used by the first two tasks. */ + vSemaphoreCreateBinary( pxFirstSemaphoreParameters->xSemaphore ); + + if( pxFirstSemaphoreParameters->xSemaphore != NULL ) + { + /* Create the variable which is to be shared by the first two tasks. */ + pxFirstSemaphoreParameters->pulSharedVariable = ( unsigned portLONG * ) pvPortMalloc( sizeof( unsigned portLONG ) ); + + /* Initialise the share variable to the value the tasks expect. */ + *( pxFirstSemaphoreParameters->pulSharedVariable ) = semtstNON_BLOCKING_EXPECTED_VALUE; + + /* The first two tasks do not block on semaphore calls. */ + pxFirstSemaphoreParameters->xBlockTime = ( portTickType ) 0; + + /* Spawn the first two tasks. As they poll they operate at the idle priority. */ + xTaskCreate( prvSemaphoreTest, ( signed portCHAR * ) "PolSEM1", semtstSTACK_SIZE, ( void * ) pxFirstSemaphoreParameters, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL ); + xTaskCreate( prvSemaphoreTest, ( signed portCHAR * ) "PolSEM2", semtstSTACK_SIZE, ( void * ) pxFirstSemaphoreParameters, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL ); + } + } + + /* Do exactly the same to create the second set of tasks, only this time + provide a block time for the semaphore calls. */ + pxSecondSemaphoreParameters = ( xSemaphoreParameters * ) pvPortMalloc( sizeof( xSemaphoreParameters ) ); + if( pxSecondSemaphoreParameters != NULL ) + { + vSemaphoreCreateBinary( pxSecondSemaphoreParameters->xSemaphore ); + + if( pxSecondSemaphoreParameters->xSemaphore != NULL ) + { + pxSecondSemaphoreParameters->pulSharedVariable = ( unsigned portLONG * ) pvPortMalloc( sizeof( unsigned portLONG ) ); + *( pxSecondSemaphoreParameters->pulSharedVariable ) = semtstBLOCKING_EXPECTED_VALUE; + pxSecondSemaphoreParameters->xBlockTime = xBlockTime / portTICK_RATE_MS; + + xTaskCreate( prvSemaphoreTest, ( signed portCHAR * ) "BlkSEM1", semtstSTACK_SIZE, ( void * ) pxSecondSemaphoreParameters, uxPriority, ( xTaskHandle * ) NULL ); + xTaskCreate( prvSemaphoreTest, ( signed portCHAR * ) "BlkSEM2", semtstSTACK_SIZE, ( void * ) pxSecondSemaphoreParameters, uxPriority, ( xTaskHandle * ) NULL ); + } + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( prvSemaphoreTest, pvParameters ) +{ +xSemaphoreParameters *pxParameters; +volatile unsigned portLONG *pulSharedVariable, ulExpectedValue; +unsigned portLONG ulCounter; +portSHORT sError = pdFALSE, sCheckVariableToUse; + + /* See which check variable to use. sNextCheckVariable is not semaphore + protected! */ + portENTER_CRITICAL(); + sCheckVariableToUse = sNextCheckVariable; + sNextCheckVariable++; + portEXIT_CRITICAL(); + + /* A structure is passed in as the parameter. This contains the shared + variable being guarded. */ + pxParameters = ( xSemaphoreParameters * ) pvParameters; + pulSharedVariable = pxParameters->pulSharedVariable; + + /* If we are blocking we use a much higher count to ensure loads of context + switches occur during the count. */ + if( pxParameters->xBlockTime > ( portTickType ) 0 ) + { + ulExpectedValue = semtstBLOCKING_EXPECTED_VALUE; + } + else + { + ulExpectedValue = semtstNON_BLOCKING_EXPECTED_VALUE; + } + + for( ;; ) + { + /* Try to obtain the semaphore. */ + if( xSemaphoreTake( pxParameters->xSemaphore, pxParameters->xBlockTime ) == pdPASS ) + { + /* We have the semaphore and so expect any other tasks using the + shared variable to have left it in the state we expect to find + it. */ + if( *pulSharedVariable != ulExpectedValue ) + { + sError = pdTRUE; + } + + /* Clear the variable, then count it back up to the expected value + before releasing the semaphore. Would expect a context switch or + two during this time. */ + for( ulCounter = ( unsigned portLONG ) 0; ulCounter <= ulExpectedValue; ulCounter++ ) + { + *pulSharedVariable = ulCounter; + if( *pulSharedVariable != ulCounter ) + { + sError = pdTRUE; + } + } + + /* Release the semaphore, and if no errors have occurred increment the check + variable. */ + if( xSemaphoreGive( pxParameters->xSemaphore ) == pdFALSE ) + { + sError = pdTRUE; + } + + if( sError == pdFALSE ) + { + if( sCheckVariableToUse < semtstNUM_TASKS ) + { + ( sCheckVariables[ sCheckVariableToUse ] )++; + } + } + + /* If we have a block time then we are running at a priority higher + than the idle priority. This task takes a long time to complete + a cycle (deliberately so to test the guarding) so will be starving + out lower priority tasks. Block for some time to allow give lower + priority tasks some processor time. */ + vTaskDelay( pxParameters->xBlockTime * semtstDELAY_FACTOR ); + } + else + { + if( pxParameters->xBlockTime == ( portTickType ) 0 ) + { + /* We have not got the semaphore yet, so no point using the + processor. We are not blocking when attempting to obtain the + semaphore. */ + taskYIELD(); + } + } + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +portBASE_TYPE xAreSemaphoreTasksStillRunning( void ) +{ +static portSHORT sLastCheckVariables[ semtstNUM_TASKS ] = { 0 }; +portBASE_TYPE xTask, xReturn = pdTRUE; + + for( xTask = 0; xTask < semtstNUM_TASKS; xTask++ ) + { + if( sLastCheckVariables[ xTask ] == sCheckVariables[ xTask ] ) + { + xReturn = pdFALSE; + } + + sLastCheckVariables[ xTask ] = sCheckVariables[ xTask ]; + } + + return xReturn; +} + + diff --git a/20080212/Demo/Common/drivers/LuminaryMicro/EULA.txt b/20080212/Demo/Common/drivers/LuminaryMicro/EULA.txt new file mode 100644 index 000000000..e28207634 --- /dev/null +++ b/20080212/Demo/Common/drivers/LuminaryMicro/EULA.txt @@ -0,0 +1,131 @@ +IMPORTANT. Read the following LMI Software License Agreement ("Agreement") +completely. + +In summary, this license agreement allows you to use this software only on +Luminary Micro microcontrollers, on an as-is basis, with no warranties. + +LUMINARY MICRO SOFTWARE LICENSE AGREEMENT + +This is a legal agreement between you (either as an individual or as an +authorized representative of your employer) and Luminary Micro, Inc. ("LMI"). +It concerns your rights to use this file and any accompanying written materials +(the "Software"). In consideration for LMI allowing you to access the Software, +you are agreeing to be bound by the terms of this Agreement. If you do not +agree to all of the terms of this Agreement, do not download the Software. If +you change your mind later, stop using the Software and delete all copies of +the Software in your possession or control. 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zr~%)(-^nZ(VJC6dTt$f_Jp`$jEjvP=>c`$YSMszc{|8e!(q{`|t*uVFlK&@G<8rV# zc8k>*<0xZ#7#r_Dcf#?W!F_bO+)onkNlfdoY1|snjTE>fIJx(VJ`7d4xYxkf`nJ!5 zdoRNEfzGSnrx9)tbYA_wjBsy&<~>r9v||zsUB4rsMMkXTuSU3|N~Ur2y|q5JOLS=5 zQh+q>7=(H4h}UlaWFB1XW1j{t@A&PC$~^;I-f@Z7Y?_z{N1s@?V+y!s*d$5Y-v>y0 z2=y@6SuUUU(efpZ^^JXJ9``(bvG3fb^l4vQd}pXh(k%Ydo|MG8Gx1xa=tEXMIL-r+Bw7ASU#9GM9sZ$_w31iYY|?%n6Y0Cin&WVTcuEO+&ei60(0?v_B7yPn>@r?ys+89l|v?bD? z^(}pCSf4id6ZR_PIiat|KF4d;`a%nmzUAp!vmubznO%;y``4R&j%GdS>m715k0gD) zqmJg4%4g~y2Xv$PJfIixH9b|I`^3XN>s=z!^Go literal 0 HcmV?d00001 diff --git a/20080212/Demo/Common/drivers/LuminaryMicro/can.h b/20080212/Demo/Common/drivers/LuminaryMicro/can.h new file mode 100644 index 000000000..0df5c4587 --- /dev/null +++ b/20080212/Demo/Common/drivers/LuminaryMicro/can.h @@ -0,0 +1,441 @@ +//***************************************************************************** +// +// can.h - Defines and Macros for the CAN controller. +// +// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1582 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __CAN_H__ +#define __CAN_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup can_api +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Miscellaneous defines for Message ID Types +// +//***************************************************************************** + +//***************************************************************************** +// +//! These are the flags used by the tCANMsgObject variable when calling the +//! the CANMessageSet() and CANMessageGet() APIs. +// +//***************************************************************************** +typedef enum +{ + // + //! This indicates that transmit interrupts should be enabled, or are + //! enabled. + // + MSG_OBJ_TX_INT_ENABLE = 0x00000001, + + // + //! This indicates that receive interrupts should be enabled or are + //! enabled. + // + MSG_OBJ_RX_INT_ENABLE = 0x00000002, + + // + //! This indicates that a message object will use or is using an extended + //! identifier. + // + MSG_OBJ_EXTENDED_ID = 0x00000004, + + // + //! This indicates that a message object will use or is using filtering + //! based on the object's message Identifier. + // + MSG_OBJ_USE_ID_FILTER = 0x00000008, + + // + //! This indicates that new data was available in the message object. + // + MSG_OBJ_NEW_DATA = 0x00000080, + + // + //! This indicates that data was lost since this message object was last + //! read. + // + MSG_OBJ_DATA_LOST = 0x00000100, + + // + //! This indicates that a message object will use or is using filtering + //! based on the direction of the transfer. If the direction filtering is + //! used then ID filtering must also be enabled. + // + MSG_OBJ_USE_DIR_FILTER = (0x00000010 | MSG_OBJ_USE_ID_FILTER), + + // + //! This indicates that a message object will use or is using message + //! identifier filtering based of the the extended identifier. + //! If the extended identifier filtering is used then ID filtering must + //! also be enabled. + // + MSG_OBJ_USE_EXT_FILTER = (0x00000020 | MSG_OBJ_USE_ID_FILTER), + + // + //! This indicates that a message object is a remote frame. + // + MSG_OBJ_REMOTE_FRAME = 0x00000040, + + // + //! This indicates that a message object has no flags set. + // + MSG_OBJ_NO_FLAGS = 0x00000000 +} +tCANObjFlags; + +//***************************************************************************** +// +//! This define is used with the #tCANObjFlags enumerated values to allow +//! checking only status flags and not configuration flags. +// +//***************************************************************************** +#define MSG_OBJ_STATUS_MASK (MSG_OBJ_NEW_DATA | MSG_OBJ_DATA_LOST) + +//***************************************************************************** +// +//! This structure used for encapsulating all the items associated with a CAN +//! message object in the CAN controller. +// +//***************************************************************************** +typedef struct +{ + // + //! The CAN message identifier used for 11 or 29 bit identifiers. + // + unsigned long ulMsgID; + + // + //! The message identifier mask used when identifier filtering is enabled. + // + unsigned long ulMsgIDMask; + + // + //! This value holds various status flags and settings specified by + //! tCANObjFlags. + // + unsigned long ulFlags; + + // + //! This value is the number of bytes of data in the message object. + // + unsigned long ulMsgLen; + + // + //! This is a pointer to the message object's data. + // + unsigned char *pucMsgData; +} +tCANMsgObject; + +//***************************************************************************** +// +//! This structure is used for encapsulating the values associated with setting +//! up the bit timing for a CAN controller. The structure is used when calling +//! the CANGetBitTiming and CANSetBitTiming functions. +// +//***************************************************************************** +typedef struct +{ + // + //! This value holds the sum of the Synchronization, Propagation, and Phase + //! Buffer 1 segments, measured in time quanta. The valid values for this + //! setting range from 2 to 16. + // + unsigned int uSyncPropPhase1Seg; + + // + //! This value holds the Phase Buffer 2 segment in time quanta. The valid + //! values for this setting range from 1 to 8. + // + unsigned int uPhase2Seg; + + // + //! This value holds the Resynchronization Jump Width in time quanta. The + //! valid values for this setting range from 1 to 4. + // + unsigned int uSJW; + + // + //! This value holds the CAN_CLK divider used to determine time quanta. + //! The valid values for this setting range from 1 to 1023. + // + unsigned int uQuantumPrescaler; + +} +tCANBitClkParms; + +//***************************************************************************** +// +//! This data type is used to identify the interrupt status register. This is +//! used when calling the a CANIntStatus() function. +// +//***************************************************************************** +typedef enum +{ + // + //! Read the CAN interrupt status information. + // + CAN_INT_STS_CAUSE, + + // + //! Read a message object's interrupt status. + // + CAN_INT_STS_OBJECT +} +tCANIntStsReg; + +//***************************************************************************** +// +//! This data type is used to identify which of the several status registers +//! to read when calling the CANStatusGet() function. +// +//***************************************************************************** +typedef enum +{ + // + //! Read the full CAN controller status. + // + CAN_STS_CONTROL, + + // + //! Read the full 32 bit mask of message objects with a transmit request + //! set. + // + CAN_STS_TXREQUEST, + + // + //! Read the full 32 bit mask of message objects with a new data available. + // + CAN_STS_NEWDAT, + + // + //! Read the full 32 bit mask of message objects that are enabled. + // + CAN_STS_MSGVAL +} +tCANStsReg; + +//***************************************************************************** +// +//! These definitions are used to specify interrupt sources to CANIntEnable() +//! and CANIntDisable(). +// +//***************************************************************************** +typedef enum +{ + // + //! This flag is used to allow a CAN controller to generate error + //! interrupts. + // + CAN_INT_ERROR = 0x00000008, + + // + //! This flag is used to allow a CAN controller to generate status + //! interrupts. + // + CAN_INT_STATUS = 0x00000004, + + // + //! This flag is used to allow a CAN controller to generate any CAN + //! interrupts. If this is not set then no interrupts will be generated by + //! the CAN controller. + // + CAN_INT_MASTER = 0x00000002 +} +tCANIntFlags; + +//***************************************************************************** +// +//! This definition is used to determine the type of message object that will +//! be set up via a call to the CANMessageSet() API. +// +//***************************************************************************** +typedef enum +{ + // + //! Transmit message object. + // + MSG_OBJ_TYPE_TX, + + // + //! Transmit remote request message object + // + MSG_OBJ_TYPE_TX_REMOTE, + + // + //! Receive message object. + // + MSG_OBJ_TYPE_RX, + + // + //! Receive remote request message object. + // + MSG_OBJ_TYPE_RX_REMOTE, + + // + //! Remote frame receive remote, with auto-transmit message object. + // + MSG_OBJ_TYPE_RXTX_REMOTE +} +tMsgObjType; + +//***************************************************************************** +// +//! The following enumeration contains all error or status indicators that +//! can be returned when calling the CANStatusGet() API. +// +//***************************************************************************** +typedef enum +{ + // + //! CAN controller has entered a Bus Off state. + // + CAN_STATUS_BUS_OFF = 0x00000080, + + // + //! CAN controller error level has reached warning level. + // + CAN_STATUS_EWARN = 0x00000040, + + // + //! CAN controller error level has reached error passive level. + // + CAN_STATUS_EPASS = 0x00000020, + + // + //! A message was received successfully since the last read of this status. + // + CAN_STATUS_RXOK = 0x00000010, + + // + //! A message was transmitted successfully since the last read of this + //! status. + // + CAN_STATUS_TXOK = 0x00000008, + + // + //! This is the mask for the last error code field. + // + CAN_STATUS_LEC_MSK = 0x00000007, + + // + //! There was no error. + // + CAN_STATUS_LEC_NONE = 0x00000000, + + // + //! A bit stuffing error has occurred. + // + CAN_STATUS_LEC_STUFF = 0x00000001, + + // + //! A formatting error has occurred. + // + CAN_STATUS_LEC_FORM = 0x00000002, + + // + //! An acknowledge error has occurred. + // + CAN_STATUS_LEC_ACK = 0x00000003, + + // + //! The bus remained a bit level of 1 for longer than is allowed. + // + CAN_STATUS_LEC_BIT1 = 0x00000004, + + // + //! The bus remained a bit level of 0 for longer than is allowed. + // + CAN_STATUS_LEC_BIT0 = 0x00000005, + + // + //! A CRC error has occurred. + // + CAN_STATUS_LEC_CRC = 0x00000006, + + // + //! This is the mask for the CAN Last Error Code (LEC). + // + CAN_STATUS_LEC_MASK = 0x00000007 +} +tCANStatusCtrl; + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void CANInit(unsigned long ulBase); +extern void CANEnable(unsigned long ulBase); +extern void CANDisable(unsigned long ulBase); +extern void CANSetBitTiming(unsigned long ulBase, tCANBitClkParms *pClkParms); +extern void CANGetBitTiming(unsigned long ulBase, tCANBitClkParms *pClkParms); +extern unsigned long CANReadReg(unsigned long ulRegAddress); +extern void CANWriteReg(unsigned long ulRegAddress, unsigned long ulRegValue); +extern void CANMessageSet(unsigned long ulBase, unsigned long ulObjID, + tCANMsgObject *pMsgObject, tMsgObjType eMsgType); +extern void CANMessageGet(unsigned long ulBase, unsigned long ulObjID, + tCANMsgObject *pMsgObject, tBoolean bClrPendingInt); +extern unsigned long CANStatusGet(unsigned long ulBase, tCANStsReg eStatusReg); +extern void CANMessageClear(unsigned long ulBase, unsigned long ulObjID); +extern void CANIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); +extern void CANIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void CANIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern void CANIntClear(unsigned long ulBase, unsigned long ulIntClr); +extern unsigned long CANIntStatus(unsigned long ulBase, + tCANIntStsReg eIntStsReg); +extern tBoolean CANRetryGet(unsigned long ulBase); +extern void CANRetrySet(unsigned long ulBase, tBoolean bAutoRetry); +extern tBoolean CANErrCntrGet(unsigned long ulBase, unsigned long *pulRxCount, + unsigned long *pulTxCount); +extern long CANGetIntNumber(unsigned long ulBase); +extern void CANReadDataReg(unsigned char *pucData, unsigned long *pulRegister, + int iSize); +extern void CANWriteDataReg(unsigned char *pucData, unsigned long *pulRegister, + int iSize); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +#ifdef __cplusplus +} +#endif + +#endif // __CAN_H__ diff --git a/20080212/Demo/Common/drivers/LuminaryMicro/comp.h b/20080212/Demo/Common/drivers/LuminaryMicro/comp.h new file mode 100644 index 000000000..be88edba1 --- /dev/null +++ b/20080212/Demo/Common/drivers/LuminaryMicro/comp.h @@ -0,0 +1,122 @@ +//***************************************************************************** +// +// comp.h - Prototypes for the analog comparator driver. +// +// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1582 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __COMP_H__ +#define __COMP_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to ComparatorConfigure() as the ulConfig +// parameter. For each group (i.e. COMP_TRIG_xxx, COMP_INT_xxx, etc.), one of +// the values may be selected and ORed together will values from the other +// groups. +// +//***************************************************************************** +#define COMP_TRIG_NONE 0x00000000 // No ADC trigger +#define COMP_TRIG_HIGH 0x00000880 // Trigger when high +#define COMP_TRIG_LOW 0x00000800 // Trigger when low +#define COMP_TRIG_FALL 0x00000820 // Trigger on falling edge +#define COMP_TRIG_RISE 0x00000840 // Trigger on rising edge +#define COMP_TRIG_BOTH 0x00000860 // Trigger on both edges +#define COMP_INT_HIGH 0x00000010 // Interrupt when high +#define COMP_INT_LOW 0x00000000 // Interrupt when low +#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge +#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge +#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges +#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin +#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin +#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference +#ifndef DEPRECATED +#define COMP_OUTPUT_NONE 0x00000000 // No comparator output +#endif +#define COMP_OUTPUT_NORMAL 0x00000000 // Comparator output normal +#define COMP_OUTPUT_INVERT 0x00000002 // Comparator output inverted + +//***************************************************************************** +// +// Values that can be passed to ComparatorSetRef() as the ulRef parameter. +// +//***************************************************************************** +#define COMP_REF_OFF 0x00000000 // Turn off the internal reference +#define COMP_REF_0V 0x00000300 // Internal reference of 0V +#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V +#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V +#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V +#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V +#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V +#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V +#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V +#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V +#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V +#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V +#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V +#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V +#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V +#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V +#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V +#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V +#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V +#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V +#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V +#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V +#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V +#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V +#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V +#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V +#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V +#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V +#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp, + unsigned long ulConfig); +extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef); +extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp); +extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp, + void (*pfnHandler)(void)); +extern void ComparatorIntUnregister(unsigned long ulBase, + unsigned long ulComp); +extern void ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp); +extern void ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp); +extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp, + tBoolean bMasked); +extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp); + +#ifdef __cplusplus +} +#endif + +#endif // __COMP_H__ diff --git a/20080212/Demo/Common/drivers/LuminaryMicro/cpu.h b/20080212/Demo/Common/drivers/LuminaryMicro/cpu.h new file mode 100644 index 000000000..6cabc3393 --- /dev/null +++ b/20080212/Demo/Common/drivers/LuminaryMicro/cpu.h @@ -0,0 +1,40 @@ +//***************************************************************************** +// +// cpu.h - Prototypes for the CPU instruction wrapper functions. +// +// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1582 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __CPU_H__ +#define __CPU_H__ + +//***************************************************************************** +// +// Prototypes. +// +//***************************************************************************** +extern void CPUcpsid(void); +extern void CPUcpsie(void); +extern void CPUwfi(void); + +#endif // __CPU_H__ diff --git a/20080212/Demo/Common/drivers/LuminaryMicro/debug.h b/20080212/Demo/Common/drivers/LuminaryMicro/debug.h new file mode 100644 index 000000000..0843731af --- /dev/null +++ b/20080212/Demo/Common/drivers/LuminaryMicro/debug.h @@ -0,0 +1,56 @@ +//***************************************************************************** +// +// debug.h - Macros for assisting debug of the driver library. +// +// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1582 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DEBUG_H__ +#define __DEBUG_H__ + +//***************************************************************************** +// +// Prototype for the function that is called when an invalid argument is passed +// to an API. This is only used when doing a DEBUG build. +// +//***************************************************************************** +extern void __error__(char *pcFilename, unsigned long ulLine); + +//***************************************************************************** +// +// The ASSERT macro, which does the actual assertion checking. Typically, this +// will be for procedure arguments. +// +//***************************************************************************** +#ifdef DEBUG +#define ASSERT(expr) { \ + if(!(expr)) \ + { \ + __error__(__FILE__, __LINE__); \ + } \ + } +#else +#define ASSERT(expr) +#endif + +#endif // __DEBUG_H__ diff --git a/20080212/Demo/Common/drivers/LuminaryMicro/ethernet.h b/20080212/Demo/Common/drivers/LuminaryMicro/ethernet.h new file mode 100644 index 000000000..268a5e708 --- /dev/null +++ b/20080212/Demo/Common/drivers/LuminaryMicro/ethernet.h @@ -0,0 +1,271 @@ +//***************************************************************************** +// +// ethernet.h - Defines and Macros for the ethernet module. +// +// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1582 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __ETHERNET_H__ +#define __ETHERNET_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to EthernetConfigSet as the ulConfig value, and +// returned from EthernetConfigGet. +// +//***************************************************************************** +#define ETH_CFG_TS_TSEN 0x010000 // Enable Timestamp (CCP) +#define ETH_CFG_RX_BADCRCDIS 0x000800 // Disable RX BAD CRC Packets +#define ETH_CFG_RX_PRMSEN 0x000400 // Enable RX Promiscuous +#define ETH_CFG_RX_AMULEN 0x000200 // Enable RX Multicast +#define ETH_CFG_TX_DPLXEN 0x000010 // Enable TX Duplex Mode +#define ETH_CFG_TX_CRCEN 0x000004 // Enable TX CRC Generation +#define ETH_CFG_TX_PADEN 0x000002 // Enable TX Padding + +//***************************************************************************** +// +// Values that can be passed to EthernetIntEnable, EthernetIntDisable, and +// EthernetIntClear as the ulIntFlags parameter, and returned from +// EthernetIntStatus. +// +//***************************************************************************** +#define ETH_INT_PHY 0x040 // PHY Event/Interrupt +#define ETH_INT_MDIO 0x020 // Management Transaction +#define ETH_INT_RXER 0x010 // RX Error +#define ETH_INT_RXOF 0x008 // RX FIFO Overrun +#define ETH_INT_TX 0x004 // TX Complete +#define ETH_INT_TXER 0x002 // TX Error +#define ETH_INT_RX 0x001 // RX Complete + +//***************************************************************************** +// +// The following define values that can be passed as register addresses to +// EthernetPHYRead and EthernetPHYWrite. +// +//***************************************************************************** +#define PHY_MR0 0 // Control +#define PHY_MR1 1 // Status +#define PHY_MR2 2 // PHY Identifier 1 +#define PHY_MR3 3 // PHY Identifier 2 +#define PHY_MR4 4 // Auto-Neg. Advertisement +#define PHY_MR5 5 // Auto-Neg. Link Partner Ability +#define PHY_MR6 6 // Auto-Neg. Expansion + // 7-15 Reserved/Not Implemented +#define PHY_MR16 16 // Vendor Specific +#define PHY_MR17 17 // Interrupt Control/Status +#define PHY_MR18 18 // Diagnostic Register +#define PHY_MR19 19 // Transceiver Control + // 20-22 Reserved +#define PHY_MR23 23 // LED Configuration Register +#define PHY_MR24 24 // MDI/MDIX Control Register + // 25-31 Reserved/Not Implemented + +//***************************************************************************** +// +// The following define bit fields in the ETH_MR0 register +// +//***************************************************************************** +#define PHY_MR0_RESET 0x8000 // Reset the PHY +#define PHY_MR0_LOOPBK 0x4000 // TXD to RXD Loopback +#define PHY_MR0_SPEEDSL 0x2000 // Speed Selection +#define PHY_MR0_SPEEDSL_10 0x0000 // Speed Selection 10BASE-T +#define PHY_MR0_SPEEDSL_100 0x2000 // Speed Selection 100BASE-T +#define PHY_MR0_ANEGEN 0x1000 // Auto-Negotiation Enable +#define PHY_MR0_PWRDN 0x0800 // Power Down +#define PHY_MR0_RANEG 0x0200 // Restart Auto-Negotiation +#define PHY_MR0_DUPLEX 0x0100 // Enable full duplex +#define PHY_MR0_DUPLEX_HALF 0x0000 // Enable half duplex mode +#define PHY_MR0_DUPLEX_FULL 0x0100 // Enable full duplex mode + +//***************************************************************************** +// +// The following define bit fields in the ETH_MR1 register +// +//***************************************************************************** +#define PHY_MR1_ANEGC 0x0020 // Auto-Negotiate Complete +#define PHY_MR1_RFAULT 0x0010 // Remove Fault Detected +#define PHY_MR1_LINK 0x0004 // Link Established +#define PHY_MR1_JAB 0x0002 // Jabber Condition Detected + +//***************************************************************************** +// +// The following define bit fields in the ETH_MR17 register +// +//***************************************************************************** +#define PHY_MR17_RXER_IE 0x4000 // Enable Receive Error Interrupt +#define PHY_MR17_LSCHG_IE 0x0400 // Enable Link Status Change Int. +#define PHY_MR17_ANEGCOMP_IE 0x0100 // Enable Auto-Negotiate Cmpl. Int. +#define PHY_MR17_RXER_INT 0x0040 // Receive Error Interrupt +#define PHY_MR17_LSCHG_INT 0x0004 // Link Status Change Interrupt +#define PHY_MR17_ANEGCOMP_INT 0x0001 // Auto-Negotiate Complete Int. + +//***************************************************************************** +// +// The following define bit fields in the ETH_MR18 register +// +//***************************************************************************** +#define PHY_MR18_ANEGF 0x1000 // Auto-Negotiate Failed +#define PHY_MR18_DPLX 0x0800 // Duplex Mode Negotiated +#define PHY_MR18_DPLX_HALF 0x0000 // Half Duplex Mode Negotiated +#define PHY_MR18_DPLX_FULL 0x0800 // Full Duplex Mode Negotiated +#define PHY_MR18_RATE 0x0400 // Rate Negotiated +#define PHY_MR18_RATE_10 0x0000 // Rate Negotiated is 10BASE-T +#define PHY_MR18_RATE_100 0x0400 // Rate Negotiated is 100BASE-TX + +//***************************************************************************** +// +// The following define bit fields in the ETH_MR23 register +// +//***************************************************************************** +#define PHY_MR23_LED1 0x00f0 // LED1 Configuration +#define PHY_MR23_LED1_LINK 0x0000 // LED1 is Link Status +#define PHY_MR23_LED1_RXTX 0x0010 // LED1 is RX or TX Activity +#define PHY_MR23_LED1_TX 0x0020 // LED1 is TX Activity +#define PHY_MR23_LED1_RX 0x0030 // LED1 is RX Activity +#define PHY_MR23_LED1_COL 0x0040 // LED1 is RX Activity +#define PHY_MR23_LED1_100 0x0050 // LED1 is RX Activity +#define PHY_MR23_LED1_10 0x0060 // LED1 is RX Activity +#define PHY_MR23_LED1_DUPLEX 0x0070 // LED1 is RX Activity +#define PHY_MR23_LED1_LINKACT 0x0080 // LED1 is Link Status + Activity +#define PHY_MR23_LED0 0x000f // LED0 Configuration +#define PHY_MR23_LED0_LINK 0x0000 // LED0 is Link Status +#define PHY_MR23_LED0_RXTX 0x0001 // LED0 is RX or TX Activity +#define PHY_MR23_LED0_TX 0x0002 // LED0 is TX Activity +#define PHY_MR23_LED0_RX 0x0003 // LED0 is RX Activity +#define PHY_MR23_LED0_COL 0x0004 // LED0 is RX Activity +#define PHY_MR23_LED0_100 0x0005 // LED0 is RX Activity +#define PHY_MR23_LED0_10 0x0006 // LED0 is RX Activity +#define PHY_MR23_LED0_DUPLEX 0x0007 // LED0 is RX Activity +#define PHY_MR23_LED0_LINKACT 0x0008 // LED0 is Link Status + Activity + +//***************************************************************************** +// +// The following define bit fields in the ETH_MR24 register +// +//***************************************************************************** +#define PHY_MR24_MDIX 0x0020 // Auto-Switching Configuration +#define PHY_MR24_MDIX_NORMAL 0x0000 // Auto-Switching in passthrough +#define PHY_MR23_MDIX_CROSSOVER 0x0020 // Auto-Switching in crossover + +//***************************************************************************** +// +// Helper Macros for Ethernet Processing +// +//***************************************************************************** +// +// htonl/ntohl - big endian/little endian byte swapping macros for +// 32-bit (long) values +// +//***************************************************************************** +#ifndef htonl + #define htonl(a) \ + ((((a) >> 24) & 0x000000ff) | \ + (((a) >> 8) & 0x0000ff00) | \ + (((a) << 8) & 0x00ff0000) | \ + (((a) << 24) & 0xff000000)) +#endif + +#ifndef ntohl + #define ntohl(a) htonl((a)) +#endif + +//***************************************************************************** +// +// htons/ntohs - big endian/little endian byte swapping macros for +// 16-bit (short) values +// +//***************************************************************************** +#ifndef htons + #define htons(a) \ + ((((a) >> 8) & 0x00ff) | \ + (((a) << 8) & 0xff00)) +#endif + +#ifndef ntohs + #define ntohs(a) htons((a)) +#endif + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void EthernetInitExpClk(unsigned long ulBase, unsigned long ulEthClk); +extern void EthernetConfigSet(unsigned long ulBase, unsigned long ulConfig); +extern unsigned long EthernetConfigGet(unsigned long ulBase); +extern void EthernetMACAddrSet(unsigned long ulBase, + unsigned char *pucMACAddr); +extern void EthernetMACAddrGet(unsigned long ulBase, + unsigned char *pucMACAddr); +extern void EthernetEnable(unsigned long ulBase); +extern void EthernetDisable(unsigned long ulBase); +extern tBoolean EthernetPacketAvail(unsigned long ulBase); +extern tBoolean EthernetSpaceAvail(unsigned long ulBase); +extern long EthernetPacketGetNonBlocking(unsigned long ulBase, + unsigned char *pucBuf, + long lBufLen); +extern long EthernetPacketGet(unsigned long ulBase, unsigned char *pucBuf, + long lBufLen); +extern long EthernetPacketPutNonBlocking(unsigned long ulBase, + unsigned char *pucBuf, + long lBufLen); +extern long EthernetPacketPut(unsigned long ulBase, unsigned char *pucBuf, + long lBufLen); +extern void EthernetIntRegister(unsigned long ulBase, + void (*pfnHandler)(void)); +extern void EthernetIntUnregister(unsigned long ulBase); +extern void EthernetIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void EthernetIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long EthernetIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void EthernetIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void EthernetPHYWrite(unsigned long ulBase, unsigned char ucRegAddr, + unsigned long ulData); +extern unsigned long EthernetPHYRead(unsigned long ulBase, + unsigned char ucRegAddr); + +//***************************************************************************** +// +// Several Ethernet APIs have been renamed, with the original function name +// being deprecated. These defines provide backward compatibility. +// +//***************************************************************************** +#ifndef DEPRECATED +#include "sysctl.h" +#define EthernetInit(a) \ + EthernetInitExpClk(a, SysCtlClockGet()) +#define EthernetPacketNonBlockingGet(a, b, c) \ + EthernetPacketGetNonBlocking(a, b, c) +#define EthernetPacketNonBlockingPut(a, b, c) \ + EthernetPacketPutNonBlocking(a, b, c) +#endif + +#ifdef __cplusplus +} +#endif + +#endif // __ETHERNET_H__ diff --git a/20080212/Demo/Common/drivers/LuminaryMicro/gpio.h b/20080212/Demo/Common/drivers/LuminaryMicro/gpio.h new file mode 100644 index 000000000..67cd90bc0 --- /dev/null +++ b/20080212/Demo/Common/drivers/LuminaryMicro/gpio.h @@ -0,0 +1,140 @@ +//***************************************************************************** +// +// gpio.h - Defines and Macros for GPIO API. +// +// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1582 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __GPIO_H__ +#define __GPIO_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following values define the bit field for the ucPins argument to several +// of the APIs. +// +//***************************************************************************** +#define GPIO_PIN_0 0x00000001 // GPIO pin 0 +#define GPIO_PIN_1 0x00000002 // GPIO pin 1 +#define GPIO_PIN_2 0x00000004 // GPIO pin 2 +#define GPIO_PIN_3 0x00000008 // GPIO pin 3 +#define GPIO_PIN_4 0x00000010 // GPIO pin 4 +#define GPIO_PIN_5 0x00000020 // GPIO pin 5 +#define GPIO_PIN_6 0x00000040 // GPIO pin 6 +#define GPIO_PIN_7 0x00000080 // GPIO pin 7 + +//***************************************************************************** +// +// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and +// returned from GPIODirModeGet. +// +//***************************************************************************** +#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input +#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output +#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function + +//***************************************************************************** +// +// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and +// returned from GPIOIntTypeGet. +// +//***************************************************************************** +#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge +#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge +#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges +#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level +#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level + +//***************************************************************************** +// +// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter, +// and returned by GPIOPadConfigGet in the *pulStrength parameter. +// +//***************************************************************************** +#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength +#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength +#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength +#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control + +//***************************************************************************** +// +// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter, +// and returned by GPIOPadConfigGet in the *pulPadType parameter. +// +//***************************************************************************** +#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull +#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up +#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down +#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain +#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up +#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down +#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulPinIO); +extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin); +extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulIntType); +extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin); +extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins, + unsigned long ulStrength, + unsigned long ulPadType); +extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin, + unsigned long *pulStrength, + unsigned long *pulPadType); +extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins); +extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked); +extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPortIntRegister(unsigned long ulPort, + void (*pfIntHandler)(void)); +extern void GPIOPortIntUnregister(unsigned long ulPort); +extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, + unsigned char ucVal); +extern void GPIOPinTypeCAN(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeGPIOInput(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeGPIOOutput(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins); +extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins); + +#ifdef __cplusplus +} +#endif + +#endif // __GPIO_H__ diff --git a/20080212/Demo/Common/drivers/LuminaryMicro/hibernate.h b/20080212/Demo/Common/drivers/LuminaryMicro/hibernate.h new file mode 100644 index 000000000..ed9387352 --- /dev/null +++ b/20080212/Demo/Common/drivers/LuminaryMicro/hibernate.h @@ -0,0 +1,119 @@ +//***************************************************************************** +// +// hibernate.h - API definition for the Hibernation module. +// +// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1582 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __HIBERNATE_H__ +#define __HIBERNATE_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Macros needed for selecting the clock source for HibernateClockSelect() +// +//***************************************************************************** +#define HIBERNATE_CLOCK_SEL_RAW 0x04 +#define HIBERNATE_CLOCK_SEL_DIV128 0x00 + +//***************************************************************************** +// +// Macros need to configure wake events for HibernateWakeSet() +// +//***************************************************************************** +#define HIBERNATE_WAKE_PIN 0x10 +#define HIBERNATE_WAKE_RTC 0x08 + +//***************************************************************************** +// +// Macros needed to configure low battery detect for HibernateLowBatSet() +// +//***************************************************************************** +#define HIBERNATE_LOW_BAT_DETECT 0x20 +#define HIBERNATE_LOW_BAT_ABORT 0xA0 + +//***************************************************************************** +// +// Macros defining interrupt source bits for the interrupt functions. +// +//***************************************************************************** +#define HIBERNATE_INT_PIN_WAKE 0x08 +#define HIBERNATE_INT_LOW_BAT 0x04 +#define HIBERNATE_INT_RTC_MATCH_0 0x01 +#define HIBERNATE_INT_RTC_MATCH_1 0x02 + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void HibernateEnableExpClk(unsigned long ulHibClk); +extern void HibernateDisable(void); +extern void HibernateClockSelect(unsigned long ulClockInput); +extern void HibernateRTCEnable(void); +extern void HibernateRTCDisable(void); +extern void HibernateWakeSet(unsigned long ulWakeFlags); +extern unsigned long HibernateWakeGet(void); +extern void HibernateLowBatSet(unsigned long ulLowBatFlags); +extern unsigned long HibernateLowBatGet(void); +extern void HibernateRTCSet(unsigned long ulRTCValue); +extern unsigned long HibernateRTCGet(void); +extern void HibernateRTCMatch0Set(unsigned long ulMatch); +extern unsigned long HibernateRTCMatch0Get(void); +extern void HibernateRTCMatch1Set(unsigned long ulMatch); +extern unsigned long HibernateRTCMatch1Get(void); +extern void HibernateRTCTrimSet(unsigned long ulTrim); +extern unsigned long HibernateRTCTrimGet(void); +extern void HibernateDataSet(unsigned long *pulData, unsigned long ulCount); +extern void HibernateDataGet(unsigned long *pulData, unsigned long ulCount); +extern void HibernateRequest(void); +extern void HibernateIntEnable(unsigned long ulIntFlags); +extern void HibernateIntDisable(unsigned long ulIntFlags); +extern void HibernateIntRegister(void (*pfnHandler)(void)); +extern void HibernateIntUnregister(void); +extern unsigned long HibernateIntStatus(tBoolean bMasked); +extern void HibernateIntClear(unsigned long ulIntFlags); +extern unsigned int HibernateIsActive(void); + +//***************************************************************************** +// +// Several Hibernate module APIs have been renamed, with the original function +// name being deprecated. These defines provide backward compatibility. +// +//***************************************************************************** +#ifndef DEPRECATED +#include "sysctl.h" +#define HibernateEnable(a) \ + HibernateEnableExpClk(a, SysCtlClockGet()) +#endif + +#ifdef __cplusplus +} +#endif + +#endif // __HIBERNATE_H__ diff --git a/20080212/Demo/Common/drivers/LuminaryMicro/hw_adc.h b/20080212/Demo/Common/drivers/LuminaryMicro/hw_adc.h new file mode 100644 index 000000000..6ee79f46e --- /dev/null +++ b/20080212/Demo/Common/drivers/LuminaryMicro/hw_adc.h @@ -0,0 +1,343 @@ +//***************************************************************************** +// +// hw_adc.h - Macros used when accessing the ADC hardware. +// +// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1582 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __HW_ADC_H__ +#define __HW_ADC_H__ + +//***************************************************************************** +// +// The following define the offsets of the ADC registers. +// +//***************************************************************************** +#define ADC_O_ACTSS 0x00000000 // Active sample register +#define ADC_O_RIS 0x00000004 // Raw interrupt status register +#define ADC_O_IM 0x00000008 // Interrupt mask register +#define ADC_O_ISC 0x0000000C // Interrupt status/clear register +#define ADC_O_OSTAT 0x00000010 // Overflow status register +#define ADC_O_EMUX 0x00000014 // Event multiplexer select reg. +#define ADC_O_USTAT 0x00000018 // Underflow status register +#define ADC_O_SSPRI 0x00000020 // Channel priority register +#define ADC_O_PSSI 0x00000028 // Processor sample initiate reg. +#define ADC_O_SAC 0x00000030 // Sample Averaging Control reg. +#define ADC_O_SSMUX0 0x00000040 // Multiplexer select 0 register +#define ADC_O_SSCTL0 0x00000044 // Sample sequence control 0 reg. +#define ADC_O_SSFIFO0 0x00000048 // Result FIFO 0 register +#define ADC_O_SSFSTAT0 0x0000004C // FIFO 0 status register +#define ADC_O_SSMUX1 0x00000060 // Multiplexer select 1 register +#define ADC_O_SSCTL1 0x00000064 // Sample sequence control 1 reg. +#define ADC_O_SSFIFO1 0x00000068 // Result FIFO 1 register +#define ADC_O_SSFSTAT1 0x0000006C // FIFO 1 status register +#define ADC_O_SSMUX2 0x00000080 // Multiplexer select 2 register +#define ADC_O_SSCTL2 0x00000084 // Sample sequence control 2 reg. +#define ADC_O_SSFIFO2 0x00000088 // Result FIFO 2 register +#define ADC_O_SSFSTAT2 0x0000008C // FIFO 2 status register +#define ADC_O_SSMUX3 0x000000A0 // Multiplexer select 3 register +#define ADC_O_SSCTL3 0x000000A4 // Sample sequence control 3 reg. +#define ADC_O_SSFIFO3 0x000000A8 // Result FIFO 3 register +#define ADC_O_SSFSTAT3 0x000000AC // FIFO 3 status register +#define ADC_O_TMLB 0x00000100 // Test mode loopback register + +//***************************************************************************** +// +// The following define the offsets of the ADC sequence registers. +// +//***************************************************************************** +#define ADC_O_SEQ 0x00000040 // Offset to the first sequence +#define ADC_O_SEQ_STEP 0x00000020 // Increment to the next sequence +#define ADC_O_X_SSMUX 0x00000000 // Multiplexer select register +#define ADC_O_X_SSCTL 0x00000004 // Sample sequence control register +#define ADC_O_X_SSFIFO 0x00000008 // Result FIFO register +#define ADC_O_X_SSFSTAT 0x0000000C // FIFO status register + +//***************************************************************************** +// +// The following define the bit fields in the ADC_ACTSS register. +// +//***************************************************************************** +#define ADC_ACTSS_ASEN3 0x00000008 // Sample sequence 3 enable +#define ADC_ACTSS_ASEN2 0x00000004 // Sample sequence 2 enable +#define ADC_ACTSS_ASEN1 0x00000002 // Sample sequence 1 enable +#define ADC_ACTSS_ASEN0 0x00000001 // Sample sequence 0 enable + +//***************************************************************************** +// +// The following define the bit fields in the ADC_RIS register. +// +//***************************************************************************** +#define ADC_RIS_INR3 0x00000008 // Sample sequence 3 interrupt +#define ADC_RIS_INR2 0x00000004 // Sample sequence 2 interrupt +#define ADC_RIS_INR1 0x00000002 // Sample sequence 1 interrupt +#define ADC_RIS_INR0 0x00000001 // Sample sequence 0 interrupt + +//***************************************************************************** +// +// The following define the bit fields in the ADC_IM register. +// +//***************************************************************************** +#define ADC_IM_MASK3 0x00000008 // Sample sequence 3 mask +#define ADC_IM_MASK2 0x00000004 // Sample sequence 2 mask +#define ADC_IM_MASK1 0x00000002 // Sample sequence 1 mask +#define ADC_IM_MASK0 0x00000001 // Sample sequence 0 mask + +//***************************************************************************** +// +// The following define the bit fields in the ADC_ISC register. +// +//***************************************************************************** +#define ADC_ISC_IN3 0x00000008 // Sample sequence 3 interrupt +#define ADC_ISC_IN2 0x00000004 // Sample sequence 2 interrupt +#define ADC_ISC_IN1 0x00000002 // Sample sequence 1 interrupt +#define ADC_ISC_IN0 0x00000001 // Sample sequence 0 interrupt + +//***************************************************************************** +// +// The following define the bit fields in the ADC_OSTAT register. +// +//***************************************************************************** +#define ADC_OSTAT_OV3 0x00000008 // Sample sequence 3 overflow +#define ADC_OSTAT_OV2 0x00000004 // Sample sequence 2 overflow +#define ADC_OSTAT_OV1 0x00000002 // Sample sequence 1 overflow +#define ADC_OSTAT_OV0 0x00000001 // Sample sequence 0 overflow + +//***************************************************************************** +// +// The following define the bit fields in the ADC_EMUX register. +// +//***************************************************************************** +#define ADC_EMUX_EM3_MASK 0x0000F000 // Event mux 3 mask +#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor event +#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog comparator 0 event +#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog comparator 1 event +#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog comparator 2 event +#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External event +#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer event +#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0 event +#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1 event +#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2 event +#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always event +#define ADC_EMUX_EM2_MASK 0x00000F00 // Event mux 2 mask +#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor event +#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog comparator 0 event +#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog comparator 1 event +#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog comparator 2 event +#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External event +#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer event +#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0 event +#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1 event +#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2 event +#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always event +#define ADC_EMUX_EM1_MASK 0x000000F0 // Event mux 1 mask +#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor event +#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog comparator 0 event +#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog comparator 1 event +#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog comparator 2 event +#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External event +#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer event +#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0 event +#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1 event +#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2 event +#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always event +#define ADC_EMUX_EM0_MASK 0x0000000F // Event mux 0 mask +#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor event +#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog comparator 0 event +#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog comparator 1 event +#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog comparator 2 event +#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External event +#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer event +#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0 event +#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1 event +#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2 event +#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always event +#define ADC_EMUX_EM0_SHIFT 0 // The shift for the first event +#define ADC_EMUX_EM1_SHIFT 4 // The shift for the second event +#define ADC_EMUX_EM2_SHIFT 8 // The shift for the third event +#define ADC_EMUX_EM3_SHIFT 12 // The shift for the fourth event + +//***************************************************************************** +// +// The following define the bit fields in the ADC_USTAT register. +// +//***************************************************************************** +#define ADC_USTAT_UV3 0x00000008 // Sample sequence 3 underflow +#define ADC_USTAT_UV2 0x00000004 // Sample sequence 2 underflow +#define ADC_USTAT_UV1 0x00000002 // Sample sequence 1 underflow +#define ADC_USTAT_UV0 0x00000001 // Sample sequence 0 underflow + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SSPRI register. +// +//***************************************************************************** +#define ADC_SSPRI_SS3_MASK 0x00003000 // Sequencer 3 priority mask +#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority +#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority +#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority +#define ADC_SSPRI_SS2_MASK 0x00000300 // Sequencer 2 priority mask +#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority +#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority +#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority +#define ADC_SSPRI_SS1_MASK 0x00000030 // Sequencer 1 priority mask +#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority +#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority +#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority +#define ADC_SSPRI_SS0_MASK 0x00000003 // Sequencer 0 priority mask +#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority +#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority +#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority +#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority + +//***************************************************************************** +// +// The following define the bit fields in the ADC_PSSI register. +// +//***************************************************************************** +#define ADC_PSSI_SS3 0x00000008 // Trigger sample sequencer 3 +#define ADC_PSSI_SS2 0x00000004 // Trigger sample sequencer 2 +#define ADC_PSSI_SS1 0x00000002 // Trigger sample sequencer 1 +#define ADC_PSSI_SS0 0x00000001 // Trigger sample sequencer 0 + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SAC register. +// +//***************************************************************************** +#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling +#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling +#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling +#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling +#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling +#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling +#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SSMUX0, ADC_SSMUX1, +// ADC_SSMUX2, and ADC_SSMUX3 registers. Not all fields are present in all +// registers. +// +//***************************************************************************** +#define ADC_SSMUX_MUX7_MASK 0x70000000 // 8th mux select mask +#define ADC_SSMUX_MUX6_MASK 0x07000000 // 7th mux select mask +#define ADC_SSMUX_MUX5_MASK 0x00700000 // 6th mux select mask +#define ADC_SSMUX_MUX4_MASK 0x00070000 // 5th mux select mask +#define ADC_SSMUX_MUX3_MASK 0x00007000 // 4th mux select mask +#define ADC_SSMUX_MUX2_MASK 0x00000700 // 3rd mux select mask +#define ADC_SSMUX_MUX1_MASK 0x00000070 // 2nd mux select mask +#define ADC_SSMUX_MUX0_MASK 0x00000007 // 1st mux select mask +#define ADC_SSMUX_MUX7_SHIFT 28 +#define ADC_SSMUX_MUX6_SHIFT 24 +#define ADC_SSMUX_MUX5_SHIFT 20 +#define ADC_SSMUX_MUX4_SHIFT 16 +#define ADC_SSMUX_MUX3_SHIFT 12 +#define ADC_SSMUX_MUX2_SHIFT 8 +#define ADC_SSMUX_MUX1_SHIFT 4 +#define ADC_SSMUX_MUX0_SHIFT 0 + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SSCTL0, ADC_SSCTL1, +// ADC_SSCTL2, and ADC_SSCTL3 registers. Not all fields are present in all +// registers. +// +//***************************************************************************** +#define ADC_SSCTL_TS7 0x80000000 // 8th temperature sensor select +#define ADC_SSCTL_IE7 0x40000000 // 8th interrupt enable +#define ADC_SSCTL_END7 0x20000000 // 8th sequence end select +#define ADC_SSCTL_D7 0x10000000 // 8th differential select +#define ADC_SSCTL_TS6 0x08000000 // 7th temperature sensor select +#define ADC_SSCTL_IE6 0x04000000 // 7th interrupt enable +#define ADC_SSCTL_END6 0x02000000 // 7th sequence end select +#define ADC_SSCTL_D6 0x01000000 // 7th differential select +#define ADC_SSCTL_TS5 0x00800000 // 6th temperature sensor select +#define ADC_SSCTL_IE5 0x00400000 // 6th interrupt enable +#define ADC_SSCTL_END5 0x00200000 // 6th sequence end select +#define ADC_SSCTL_D5 0x00100000 // 6th differential select +#define ADC_SSCTL_TS4 0x00080000 // 5th temperature sensor select +#define ADC_SSCTL_IE4 0x00040000 // 5th interrupt enable +#define ADC_SSCTL_END4 0x00020000 // 5th sequence end select +#define ADC_SSCTL_D4 0x00010000 // 5th differential select +#define ADC_SSCTL_TS3 0x00008000 // 4th temperature sensor select +#define ADC_SSCTL_IE3 0x00004000 // 4th interrupt enable +#define ADC_SSCTL_END3 0x00002000 // 4th sequence end select +#define ADC_SSCTL_D3 0x00001000 // 4th differential select +#define ADC_SSCTL_TS2 0x00000800 // 3rd temperature sensor select +#define ADC_SSCTL_IE2 0x00000400 // 3rd interrupt enable +#define ADC_SSCTL_END2 0x00000200 // 3rd sequence end select +#define ADC_SSCTL_D2 0x00000100 // 3rd differential select +#define ADC_SSCTL_TS1 0x00000080 // 2nd temperature sensor select +#define ADC_SSCTL_IE1 0x00000040 // 2nd interrupt enable +#define ADC_SSCTL_END1 0x00000020 // 2nd sequence end select +#define ADC_SSCTL_D1 0x00000010 // 2nd differential select +#define ADC_SSCTL_TS0 0x00000008 // 1st temperature sensor select +#define ADC_SSCTL_IE0 0x00000004 // 1st interrupt enable +#define ADC_SSCTL_END0 0x00000002 // 1st sequence end select +#define ADC_SSCTL_D0 0x00000001 // 1st differential select + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SSFIFO0, ADC_SSFIFO1, +// ADC_SSFIFO2, and ADC_SSFIFO3 registers. +// +//***************************************************************************** +#define ADC_SSFIFO_DATA_MASK 0x000003FF // Sample data +#define ADC_SSFIFO_DATA_SHIFT 0 + +//***************************************************************************** +// +// The following define the bit fields in the ADC_SSFSTAT0, ADC_SSFSTAT1, +// ADC_SSFSTAT2, and ADC_SSFSTAT3 registers. +// +//***************************************************************************** +#define ADC_SSFSTAT_FULL 0x00001000 // FIFO is full +#define ADC_SSFSTAT_EMPTY 0x00000100 // FIFO is empty +#define ADC_SSFSTAT_HPTR 0x000000F0 // FIFO head pointer +#define ADC_SSFSTAT_TPTR 0x0000000F // FIFO tail pointer + +//***************************************************************************** +// +// The following define the bit fields in the ADC_TMLB register. +// +//***************************************************************************** +#define ADC_TMLB_LB 0x00000001 // Loopback control signals + +//***************************************************************************** +// +// The following define the bit fields in the loopback ADC data. +// +//***************************************************************************** +#define ADC_LB_CNT_MASK 0x000003C0 // Sample counter mask +#define ADC_LB_CONT 0x00000020 // Continuation sample +#define ADC_LB_DIFF 0x00000010 // Differential sample +#define ADC_LB_TS 0x00000008 // Temperature sensor sample +#define ADC_LB_MUX_MASK 0x00000007 // Input channel number mask +#define ADC_LB_CNT_SHIFT 6 // Sample counter shift +#define ADC_LB_MUX_SHIFT 0 // Input channel number shift + +#endif // __HW_ADC_H__ diff --git a/20080212/Demo/Common/drivers/LuminaryMicro/hw_can.h b/20080212/Demo/Common/drivers/LuminaryMicro/hw_can.h new file mode 100644 index 000000000..9fe03a66e --- /dev/null +++ b/20080212/Demo/Common/drivers/LuminaryMicro/hw_can.h @@ -0,0 +1,379 @@ +//***************************************************************************** +// +// hw_can.h - Defines and macros used when accessing the can. +// +// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1582 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __HW_CAN_H__ +#define __HW_CAN_H__ + +//***************************************************************************** +// +// The following define the offsets of the can registers. +// +//***************************************************************************** +#define CAN_O_CTL 0x00000000 // Control register +#define CAN_O_STS 0x00000004 // Status register +#define CAN_O_ERR 0x00000008 // Error register +#define CAN_O_BIT 0x0000000C // Bit Timing register +#define CAN_O_INT 0x00000010 // Interrupt register +#define CAN_O_TST 0x00000014 // Test register +#define CAN_O_BRPE 0x00000018 // Baud Rate Prescaler register +#define CAN_O_IF1CRQ 0x00000020 // Interface 1 Command Request reg. +#define CAN_O_IF1CMSK 0x00000024 // Interface 1 Command Mask reg. +#define CAN_O_IF1MSK1 0x00000028 // Interface 1 Mask 1 register +#define CAN_O_IF1MSK2 0x0000002C // Interface 1 Mask 2 register +#define CAN_O_IF1ARB1 0x00000030 // Interface 1 Arbitration 1 reg. +#define CAN_O_IF1ARB2 0x00000034 // Interface 1 Arbitration 2 reg. +#define CAN_O_IF1MCTL 0x00000038 // Interface 1 Message Control reg. +#define CAN_O_IF1DA1 0x0000003C // Interface 1 DataA 1 register +#define CAN_O_IF1DA2 0x00000040 // Interface 1 DataA 2 register +#define CAN_O_IF1DB1 0x00000044 // Interface 1 DataB 1 register +#define CAN_O_IF1DB2 0x00000048 // Interface 1 DataB 2 register +#define CAN_O_IF2CRQ 0x00000080 // Interface 2 Command Request reg. +#define CAN_O_IF2CMSK 0x00000084 // Interface 2 Command Mask reg. +#define CAN_O_IF2MSK1 0x00000088 // Interface 2 Mask 1 register +#define CAN_O_IF2MSK2 0x0000008C // Interface 2 Mask 2 register +#define CAN_O_IF2ARB1 0x00000090 // Interface 2 Arbitration 1 reg. +#define CAN_O_IF2ARB2 0x00000094 // Interface 2 Arbitration 2 reg. +#define CAN_O_IF2MCTL 0x00000098 // Interface 2 Message Control reg. +#define CAN_O_IF2DA1 0x0000009C // Interface 2 DataA 1 register +#define CAN_O_IF2DA2 0x000000A0 // Interface 2 DataA 2 register +#define CAN_O_IF2DB1 0x000000A4 // Interface 2 DataB 1 register +#define CAN_O_IF2DB2 0x000000A8 // Interface 2 DataB 2 register +#define CAN_O_TXRQ1 0x00000100 // Transmission Request 1 register +#define CAN_O_TXRQ2 0x00000104 // Transmission Request 2 register +#define CAN_O_NWDA1 0x00000120 // New Data 1 register +#define CAN_O_NWDA2 0x00000124 // New Data 2 register +#define CAN_O_MSGINT1 0x00000140 // Intr. Pending in Msg Obj 1 reg. +#define CAN_O_MSGINT2 0x00000144 // Intr. Pending in Msg Obj 2 reg. +#define CAN_O_MSGVAL1 0x00000160 // Message Valid in Msg Obj 1 reg. +#define CAN_O_MSGVAL2 0x00000164 // Message Valid in Msg Obj 2 reg. + +//***************************************************************************** +// +// The following define the reset values of the can registers. +// +//***************************************************************************** +#define CAN_RV_CTL 0x00000001 +#define CAN_RV_STS 0x00000000 +#define CAN_RV_ERR 0x00000000 +#define CAN_RV_BIT 0x00002301 +#define CAN_RV_INT 0x00000000 +#define CAN_RV_TST 0x00000000 +#define CAN_RV_BRPE 0x00000000 +#define CAN_RV_IF1CRQ 0x00000001 +#define CAN_RV_IF1CMSK 0x00000000 +#define CAN_RV_IF1MSK1 0x0000FFFF +#define CAN_RV_IF1MSK2 0x0000FFFF +#define CAN_RV_IF1ARB1 0x00000000 +#define CAN_RV_IF1ARB2 0x00000000 +#define CAN_RV_IF1MCTL 0x00000000 +#define CAN_RV_IF1DA1 0x00000000 +#define CAN_RV_IF1DA2 0x00000000 +#define CAN_RV_IF1DB1 0x00000000 +#define CAN_RV_IF1DB2 0x00000000 +#define CAN_RV_IF2CRQ 0x00000001 +#define CAN_RV_IF2CMSK 0x00000000 +#define CAN_RV_IF2MSK1 0x0000FFFF +#define CAN_RV_IF2MSK2 0x0000FFFF +#define CAN_RV_IF2ARB1 0x00000000 +#define CAN_RV_IF2ARB2 0x00000000 +#define CAN_RV_IF2MCTL 0x00000000 +#define CAN_RV_IF2DA1 0x00000000 +#define CAN_RV_IF2DA2 0x00000000 +#define CAN_RV_IF2DB1 0x00000000 +#define CAN_RV_IF2DB2 0x00000000 +#define CAN_RV_TXRQ1 0x00000000 +#define CAN_RV_TXRQ2 0x00000000 +#define CAN_RV_NWDA1 0x00000000 +#define CAN_RV_NWDA2 0x00000000 +#define CAN_RV_MSGINT1 0x00000000 +#define CAN_RV_MSGINT2 0x00000000 +#define CAN_RV_MSGVAL1 0x00000000 +#define CAN_RV_MSGVAL2 0x00000000 + +//***************************************************************************** +// +// The following define the bit fields in the CAN_CTL register. +// +//***************************************************************************** +#define CAN_CTL_TEST 0x00000080 // Test mode enable +#define CAN_CTL_CCE 0x00000040 // Configuration change enable +#define CAN_CTL_DAR 0x00000020 // Disable automatic retransmission +#define CAN_CTL_EIE 0x00000008 // Error interrupt enable +#define CAN_CTL_SIE 0x00000004 // Status change interrupt enable +#define CAN_CTL_IE 0x00000002 // Module interrupt enable +#define CAN_CTL_INIT 0x00000001 // Initialization + +//***************************************************************************** +// +// The following define the bit fields in the CAN_STS register. +// +//***************************************************************************** +#define CAN_STS_BOFF 0x00000080 // Bus Off status +#define CAN_STS_EWARN 0x00000040 // Error Warning status +#define CAN_STS_EPASS 0x00000020 // Error Passive status +#define CAN_STS_RXOK 0x00000010 // Received Message Successful +#define CAN_STS_TXOK 0x00000008 // Transmitted Message Successful +#define CAN_STS_LEC_MSK 0x00000007 // Last Error Code +#define CAN_STS_LEC_NONE 0x00000000 // No error +#define CAN_STS_LEC_STUFF 0x00000001 // Stuff error +#define CAN_STS_LEC_FORM 0x00000002 // Form(at) error +#define CAN_STS_LEC_ACK 0x00000003 // Ack error +#define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 error +#define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 error +#define CAN_STS_LEC_CRC 0x00000006 // CRC error + +//***************************************************************************** +// +// The following define the bit fields in the CAN_ERR register. +// +//***************************************************************************** +#define CAN_ERR_RP 0x00008000 // Receive error passive status +#define CAN_ERR_REC_MASK 0x00007F00 // Receive error counter status +#define CAN_ERR_REC_SHIFT 8 // Receive error counter bit pos +#define CAN_ERR_TEC_MASK 0x000000FF // Transmit error counter status +#define CAN_ERR_TEC_SHIFT 0 // Transmit error counter bit pos + +//***************************************************************************** +// +// The following define the bit fields in the CAN_BIT register. +// +//***************************************************************************** +#define CAN_BIT_TSEG2 0x00007000 // Time segment after sample point +#define CAN_BIT_TSEG1 0x00000F00 // Time segment before sample point +#define CAN_BIT_SJW 0x000000C0 // (Re)Synchronization jump width +#define CAN_BIT_BRP 0x0000003F // Baud rate prescaler + +//***************************************************************************** +// +// The following define the bit fields in the CAN_INT register. +// +//***************************************************************************** +#define CAN_INT_INTID_MSK 0x0000FFFF // Interrupt Identifier +#define CAN_INT_INTID_NONE 0x00000000 // No Interrupt Pending +#define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt + +//***************************************************************************** +// +// The following define the bit fields in the CAN_TST register. +// +//***************************************************************************** +#define CAN_TST_RX 0x00000080 // CAN_RX pin status +#define CAN_TST_TX_MSK 0x00000060 // Overide control of CAN_TX pin +#define CAN_TST_TX_CANCTL 0x00000000 // CAN core controls CAN_TX +#define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point on CAN_TX +#define CAN_TST_TX_DOMINANT 0x00000040 // Dominant value on CAN_TX +#define CAN_TST_TX_RECESSIVE 0x00000060 // Recessive value on CAN_TX +#define CAN_TST_LBACK 0x00000010 // Loop back mode +#define CAN_TST_SILENT 0x00000008 // Silent mode +#define CAN_TST_BASIC 0x00000004 // Basic mode + +//***************************************************************************** +// +// The following define the bit fields in the CAN_BRPE register. +// +//***************************************************************************** +#define CAN_BRPE_BRPE 0x0000000F // Baud rate prescaler extension + +//***************************************************************************** +// +// The following define the bit fields in the CAN_IF1CRQ and CAN_IF1CRQ +// registers. +// Note: All bits may not be available in all registers +// +//***************************************************************************** +#define CAN_IFCRQ_BUSY 0x00008000 // Busy flag status +#define CAN_IFCRQ_MNUM_MSK 0x0000003F // Message Number + +//***************************************************************************** +// +// The following define the bit fields in the CAN_IF1CMSK and CAN_IF2CMSK +// registers. +// Note: All bits may not be available in all registers +// +//***************************************************************************** +#define CAN_IFCMSK_WRNRD 0x00000080 // Write, not Read +#define CAN_IFCMSK_MASK 0x00000040 // Access Mask Bits +#define CAN_IFCMSK_ARB 0x00000020 // Access Arbitration Bits +#define CAN_IFCMSK_CONTROL 0x00000010 // Access Control Bits +#define CAN_IFCMSK_CLRINTPND 0x00000008 // Clear interrupt pending Bit +#define CAN_IFCMSK_TXRQST 0x00000004 // Access Tx request bit (WRNRD=1) +#define CAN_IFCMSK_NEWDAT 0x00000004 // Access New Data bit (WRNRD=0) +#define CAN_IFCMSK_DATAA 0x00000002 // DataA access - bytes 0 to 3 +#define CAN_IFCMSK_DATAB 0x00000001 // DataB access - bytes 4 to 7 + +//***************************************************************************** +// +// The following define the bit fields in the CAN_IF1MSK1 and CAN_IF2MSK1 +// registers. +// Note: All bits may not be available in all registers +// +//***************************************************************************** +#define CAN_IFMSK1_MSK 0x0000FFFF // Identifier Mask + +//***************************************************************************** +// +// The following define the bit fields in the CAN_IF1MSK2 and CAN_IF2MSK2 +// registers. +// Note: All bits may not be available in all registers +// +//***************************************************************************** +#define CAN_IFMSK2_MXTD 0x00008000 // Mask extended identifier +#define CAN_IFMSK2_MDIR 0x00004000 // Mask message direction +#define CAN_IFMSK2_MSK 0x00001FFF // Mask identifier + +//***************************************************************************** +// +// The following define the bit fields in the CAN_IF1ARB1 and CAN_IF2ARB1 +// registers. +// Note: All bits may not be available in all registers +// +//***************************************************************************** +#define CAN_IFARB1_ID 0x0000FFFF // Identifier + +//***************************************************************************** +// +// The following define the bit fields in the CAN_IF1ARB2 and CAN_IF2ARB2 +// registers. +// Note: All bits may not be available in all registers +// +//***************************************************************************** +#define CAN_IFARB2_MSGVAL 0x00008000 // Message valid +#define CAN_IFARB2_XTD 0x00004000 // Extended identifier +#define CAN_IFARB2_DIR 0x00002000 // Message direction +#define CAN_IFARB2_ID 0x00001FFF // Message identifier + +//***************************************************************************** +// +// The following define the bit fields in the CAN_IF1MCTL and CAN_IF2MCTL +// registers. +// Note: All bits may not be available in all registers +// +//***************************************************************************** +#define CAN_IFMCTL_NEWDAT 0x00008000 // New Data +#define CAN_IFMCTL_MSGLST 0x00004000 // Message lost +#define CAN_IFMCTL_INTPND 0x00002000 // Interrupt pending +#define CAN_IFMCTL_UMASK 0x00001000 // Use acceptance mask +#define CAN_IFMCTL_TXIE 0x00000800 // Transmit interrupt enable +#define CAN_IFMCTL_RXIE 0x00000400 // Receive interrupt enable +#define CAN_IFMCTL_RMTEN 0x00000200 // Remote enable +#define CAN_IFMCTL_TXRQST 0x00000100 // Transmit request +#define CAN_IFMCTL_EOB 0x00000080 // End of buffer +#define CAN_IFMCTL_DLC 0x0000000F // Data length code + +//***************************************************************************** +// +// The following define the bit fields in the CAN_IF1DA1 and CAN_IF2DA1 +// registers. +// Note: All bits may not be available in all registers +// +//***************************************************************************** +#define CAN_IFDA1_DATA 0x0000FFFF // Data - bytes 1 and 0 + +//***************************************************************************** +// +// The following define the bit fields in the CAN_IF1DA2 and CAN_IF2DA2 +// registers. +// Note: All bits may not be available in all registers +// +//***************************************************************************** +#define CAN_IFDA2_DATA 0x0000FFFF // Data - bytes 3 and 2 + +//***************************************************************************** +// +// The following define the bit fields in the CAN_IF1DB1 and CAN_IF2DB1 +// registers. +// Note: All bits may not be available in all registers +// +//***************************************************************************** +#define CAN_IFDB1_DATA 0x0000FFFF // Data - bytes 5 and 4 + +//***************************************************************************** +// +// The following define the bit fields in the CAN_IF1DB2 and CAN_IF2DB2 +// registers. +// Note: All bits may not be available in all registers +// +//***************************************************************************** +#define CAN_IFDB2_DATA 0x0000FFFF // Data - bytes 7 and 6 + +//***************************************************************************** +// +// The following define the bit fields in the CAN_TXRQ1 register. +// +//***************************************************************************** +#define CAN_TXRQ1_TXRQST 0x0000FFFF // Transmission Request Bits + +//***************************************************************************** +// +// The following define the bit fields in the CAN_TXRQ2 register. +// +//***************************************************************************** +#define CAN_TXRQ2_TXRQST 0x0000FFFF // Transmission Request Bits + +//***************************************************************************** +// +// The following define the bit fields in the CAN_NWDA1 register. +// +//***************************************************************************** +#define CAN_NWDA1_NEWDATA 0x0000FFFF // New Data Bits + +//***************************************************************************** +// +// The following define the bit fields in the CAN_NWDA2 register. +// +//***************************************************************************** +#define CAN_NWDA2_NEWDATA 0x0000FFFF // New Data Bits + +//***************************************************************************** +// +// The following define the bit fields in the CAN_MSGINT1 register. +// +//***************************************************************************** +#define CAN_MSGINT1_INTPND 0x0000FFFF // Interrupt Pending Bits + +//***************************************************************************** +// +// The following define the bit fields in the CAN_MSGINT2 register. +// +//***************************************************************************** +#define CAN_MSGINT2_INTPND 0x0000FFFF // Interrupt Pending Bits + +//***************************************************************************** +// +// The following define the bit fields in the CAN_MSGVAL1 register. +// +//***************************************************************************** +#define CAN_MSGVAL1_MSGVAL 0x0000FFFF // Message Valid Bits + +//***************************************************************************** +// +// The following define the bit fields in the CAN_MSGVAL2 register. +// +//***************************************************************************** +#define CAN_MSGVAL2_MSGVAL 0x0000FFFF // Message Valid Bits + +#endif // __HW_CAN_H__ diff --git a/20080212/Demo/Common/drivers/LuminaryMicro/hw_comp.h b/20080212/Demo/Common/drivers/LuminaryMicro/hw_comp.h new file mode 100644 index 000000000..2299016f4 --- /dev/null +++ b/20080212/Demo/Common/drivers/LuminaryMicro/hw_comp.h @@ -0,0 +1,118 @@ +//***************************************************************************** +// +// hw_comp.h - Macros used when accessing the comparator hardware. +// +// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1582 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __HW_COMP_H__ +#define __HW_COMP_H__ + +//***************************************************************************** +// +// The following define the offsets of the comparator registers. +// +//***************************************************************************** +#define COMP_O_MIS 0x00000000 // Interrupt status register +#define COMP_O_RIS 0x00000004 // Raw interrupt status register +#define COMP_O_INTEN 0x00000008 // Interrupt enable register +#define COMP_O_REFCTL 0x00000010 // Reference voltage control reg. +#define COMP_O_ACSTAT0 0x00000020 // Comp0 status register +#define COMP_O_ACCTL0 0x00000024 // Comp0 control register +#define COMP_O_ACSTAT1 0x00000040 // Comp1 status register +#define COMP_O_ACCTL1 0x00000044 // Comp1 control register +#define COMP_O_ACSTAT2 0x00000060 // Comp2 status register +#define COMP_O_ACCTL2 0x00000064 // Comp2 control register + +//***************************************************************************** +// +// The following define the bit fields in the COMP_MIS, COMP_RIS, and +// COMP_INTEN registers. +// +//***************************************************************************** +#define COMP_INT_2 0x00000004 // Comp2 interrupt +#define COMP_INT_1 0x00000002 // Comp1 interrupt +#define COMP_INT_0 0x00000001 // Comp0 interrupt + +//***************************************************************************** +// +// The following define the bit fields in the COMP_REFCTL register. +// +//***************************************************************************** +#define COMP_REFCTL_EN 0x00000200 // Reference voltage enable +#define COMP_REFCTL_RNG 0x00000100 // Reference voltage range +#define COMP_REFCTL_VREF_MASK 0x0000000F // Reference voltage select mask +#define COMP_REFCTL_VREF_SHIFT 0 + +//***************************************************************************** +// +// The following define the bit fields in the COMP_ACSTAT0, COMP_ACSTAT1, and +// COMP_ACSTAT2 registers. +// +//***************************************************************************** +#define COMP_ACSTAT_OVAL 0x00000002 // Comparator output value + +//***************************************************************************** +// +// The following define the bit fields in the COMP_ACCTL0, COMP_ACCTL1, and +// COMP_ACCTL2 registers. +// +//***************************************************************************** +#define COMP_ACCTL_TMASK 0x00000800 // Trigger enable +#define COMP_ACCTL_ASRCP_MASK 0x00000600 // Vin+ source select mask +#define COMP_ACCTL_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin +#define COMP_ACCTL_ASRCP_PIN0 0x00000200 // Comp0+ pin +#define COMP_ACCTL_ASRCP_REF 0x00000400 // Internal voltage reference +#define COMP_ACCTL_ASRCP_RES 0x00000600 // Reserved +#define COMP_ACCTL_OEN 0x00000100 // Comparator output enable +#define COMP_ACCTL_TSVAL 0x00000080 // Trigger polarity select +#define COMP_ACCTL_TSEN_MASK 0x00000060 // Trigger sense mask +#define COMP_ACCTL_TSEN_LEVEL 0x00000000 // Trigger is level sense +#define COMP_ACCTL_TSEN_FALL 0x00000020 // Trigger is falling edge +#define COMP_ACCTL_TSEN_RISE 0x00000040 // Trigger is rising edge +#define COMP_ACCTL_TSEN_BOTH 0x00000060 // Trigger is both edges +#define COMP_ACCTL_ISLVAL 0x00000010 // Interrupt polarity select +#define COMP_ACCTL_ISEN_MASK 0x0000000C // Interrupt sense mask +#define COMP_ACCTL_ISEN_LEVEL 0x00000000 // Interrupt is level sense +#define COMP_ACCTL_ISEN_FALL 0x00000004 // Interrupt is falling edge +#define COMP_ACCTL_ISEN_RISE 0x00000008 // Interrupt is rising edge +#define COMP_ACCTL_ISEN_BOTH 0x0000000C // Interrupt is both edges +#define COMP_ACCTL_CINV 0x00000002 // Comparator output invert + +//***************************************************************************** +// +// The following define the reset values for the comparator registers. +// +//***************************************************************************** +#define COMP_RV_MIS 0x00000000 // Interrupt status register +#define COMP_RV_RIS 0x00000000 // Raw interrupt status register +#define COMP_RV_INTEN 0x00000000 // Interrupt enable register +#define COMP_RV_REFCTL 0x00000000 // Reference voltage control reg. +#define COMP_RV_ACSTAT0 0x00000000 // Comp0 status register +#define COMP_RV_ACCTL0 0x00000000 // Comp0 control register +#define COMP_RV_ACSTAT1 0x00000000 // Comp1 status register +#define COMP_RV_ACCTL1 0x00000000 // Comp1 control register +#define COMP_RV_ACSTAT2 0x00000000 // Comp2 status register +#define COMP_RV_ACCTL2 0x00000000 // Comp2 control register + +#endif // __HW_COMP_H__ diff --git a/20080212/Demo/Common/drivers/LuminaryMicro/hw_ethernet.h b/20080212/Demo/Common/drivers/LuminaryMicro/hw_ethernet.h new file mode 100644 index 000000000..d25c415f0 --- /dev/null +++ b/20080212/Demo/Common/drivers/LuminaryMicro/hw_ethernet.h @@ -0,0 +1,213 @@ +//***************************************************************************** +// +// hw_ethernet.h - Macros used when accessing the ethernet hardware. +// +// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1582 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __HW_ETHERNET_H__ +#define __HW_ETHERNET_H__ + +//***************************************************************************** +// +// The following define the offsets of the MAC registers in the Ethernet +// Controller. +// +//***************************************************************************** +#define MAC_O_IS 0x00000000 // Interrupt Status Register +#define MAC_O_IACK 0x00000000 // Interrupt Acknowledge Register +#define MAC_O_IM 0x00000004 // Interrupt Mask Register +#define MAC_O_RCTL 0x00000008 // Receive Control Register +#define MAC_O_TCTL 0x0000000C // Transmit Control Register +#define MAC_O_DATA 0x00000010 // Data Register +#define MAC_O_IA0 0x00000014 // Individual Address Register 0 +#define MAC_O_IA1 0x00000018 // Individual Address Register 1 +#define MAC_O_THR 0x0000001C // Threshold Register +#define MAC_O_MCTL 0x00000020 // Management Control Register +#define MAC_O_MDV 0x00000024 // Management Divider Register +#define MAC_O_MADD 0x00000028 // Management Address Register +#define MAC_O_MTXD 0x0000002C // Management Transmit Data Reg +#define MAC_O_MRXD 0x00000030 // Management Receive Data Reg +#define MAC_O_NP 0x00000034 // Number of Packets Register +#define MAC_O_TR 0x00000038 // Transmission Request Register +#define MAC_O_TS 0x0000003C // Timer Support Register + +//***************************************************************************** +// +// The following define the reset values of the MAC registers. +// +//***************************************************************************** +#define MAC_RV_IS 0x00000000 +#define MAC_RV_IACK 0x00000000 +#define MAC_RV_IM 0x0000007F +#define MAC_RV_RCTL 0x00000008 +#define MAC_RV_TCTL 0x00000000 +#define MAC_RV_DATA 0x00000000 +#define MAC_RV_IA0 0x00000000 +#define MAC_RV_IA1 0x00000000 +#define MAC_RV_THR 0x0000003F +#define MAC_RV_MCTL 0x00000000 +#define MAC_RV_MDV 0x00000080 +#define MAC_RV_MADD 0x00000000 +#define MAC_RV_MTXD 0x00000000 +#define MAC_RV_MRXD 0x00000000 +#define MAC_RV_NP 0x00000000 +#define MAC_RV_TR 0x00000000 + +//***************************************************************************** +// +// The following define the bit fields in the MAC_IS register. +// +//***************************************************************************** +#define MAC_IS_PHYINT 0x00000040 // PHY Interrupt +#define MAC_IS_MDINT 0x00000020 // MDI Transaction Complete +#define MAC_IS_RXER 0x00000010 // RX Error +#define MAC_IS_FOV 0x00000008 // RX FIFO Overrun +#define MAC_IS_TXEMP 0x00000004 // TX FIFO Empy +#define MAC_IS_TXER 0x00000002 // TX Error +#define MAC_IS_RXINT 0x00000001 // RX Packet Available + +//***************************************************************************** +// +// The following define the bit fields in the MAC_IACK register. +// +//***************************************************************************** +#define MAC_IACK_PHYINT 0x00000040 // Clear PHY Interrupt +#define MAC_IACK_MDINT 0x00000020 // Clear MDI Transaction Complete +#define MAC_IACK_RXER 0x00000010 // Clear RX Error +#define MAC_IACK_FOV 0x00000008 // Clear RX FIFO Overrun +#define MAC_IACK_TXEMP 0x00000004 // Clear TX FIFO Empy +#define MAC_IACK_TXER 0x00000002 // Clear TX Error +#define MAC_IACK_RXINT 0x00000001 // Clear RX Packet Available + +//***************************************************************************** +// +// The following define the bit fields in the MAC_IM register. +// +//***************************************************************************** +#define MAC_IM_PHYINTM 0x00000040 // Mask PHY Interrupt +#define MAC_IM_MDINTM 0x00000020 // Mask MDI Transaction Complete +#define MAC_IM_RXERM 0x00000010 // Mask RX Error +#define MAC_IM_FOVM 0x00000008 // Mask RX FIFO Overrun +#define MAC_IM_TXEMPM 0x00000004 // Mask TX FIFO Empy +#define MAC_IM_TXERM 0x00000002 // Mask TX Error +#define MAC_IM_RXINTM 0x00000001 // Mask RX Packet Available + +//***************************************************************************** +// +// The following define the bit fields in the MAC_RCTL register. +// +//***************************************************************************** +#define MAC_RCTL_RSTFIFO 0x00000010 // Clear the Receive FIFO +#define MAC_RCTL_BADCRC 0x00000008 // Reject Packets With Bad CRC +#define MAC_RCTL_PRMS 0x00000004 // Enable Promiscuous Mode +#define MAC_RCTL_AMUL 0x00000002 // Enable Multicast Packets +#define MAC_RCTL_RXEN 0x00000001 // Enable Ethernet Receiver + +//***************************************************************************** +// +// The following define the bit fields in the MAC_TCTL register. +// +//***************************************************************************** +#define MAC_TCTL_DUPLEX 0x00000010 // Enable Duplex mode +#define MAC_TCTL_CRC 0x00000004 // Enable CRC Generation +#define MAC_TCTL_PADEN 0x00000002 // Enable Automatic Padding +#define MAC_TCTL_TXEN 0x00000001 // Enable Ethernet Transmitter + +//***************************************************************************** +// +// The following define the bit fields in the MAC_IA0 register. +// +//***************************************************************************** +#define MAC_IA0_MACOCT4 0xFF000000 // 4th Octet of MAC address +#define MAC_IA0_MACOCT3 0x00FF0000 // 3rd Octet of MAC address +#define MAC_IA0_MACOCT2 0x0000FF00 // 2nd Octet of MAC address +#define MAC_IA0_MACOCT1 0x000000FF // 1st Octet of MAC address + +//***************************************************************************** +// +// The following define the bit fields in the MAC_IA1 register. +// +//***************************************************************************** +#define MAC_IA1_MACOCT6 0x0000FF00 // 6th Octet of MAC address +#define MAC_IA1_MACOCT5 0x000000FF // 5th Octet of MAC address + +//***************************************************************************** +// +// The following define the bit fields in the MAC_TXTH register. +// +//***************************************************************************** +#define MAC_THR_THRESH 0x0000003F // Transmit Threshold Value + +//***************************************************************************** +// +// The following define the bit fields in the MAC_MCTL register. +// +//***************************************************************************** +#define MAC_MCTL_REGADR 0x000000F8 // Address for Next MII Transaction +#define MAC_MCTL_WRITE 0x00000002 // Next MII Transaction is Write +#define MAC_MCTL_START 0x00000001 // Start MII Transaction + +//***************************************************************************** +// +// The following define the bit fields in the MAC_MDV register. +// +//***************************************************************************** +#define MAC_MDV_DIV 0x000000FF // Clock Divider for MDC for TX + +//***************************************************************************** +// +// The following define the bit fields in the MAC_MTXD register. +// +//***************************************************************************** +#define MAC_MTXD_MDTX 0x0000FFFF // Data for Next MII Transaction + +//***************************************************************************** +// +// The following define the bit fields in the MAC_MRXD register. +// +//***************************************************************************** +#define MAC_MRXD_MDRX 0x0000FFFF // Data Read from Last MII Trans. + +//***************************************************************************** +// +// The following define the bit fields in the MAC_NP register. +// +//***************************************************************************** +#define MAC_NP_NPR 0x0000003F // Number of RX Frames in FIFO + +//***************************************************************************** +// +// The following define the bit fields in the MAC_TXRQ register. +// +//***************************************************************************** +#define MAC_TR_NEWTX 0x00000001 // Start an Ethernet Transmission + +//***************************************************************************** +// +// The following define the bit fields in the MAC_TS register. +// +//***************************************************************************** +#define MAC_TS_TSEN 0x00000001 // Enable Timestamp Logic + +#endif // __HW_ETHERNET_H__ diff --git a/20080212/Demo/Common/drivers/LuminaryMicro/hw_flash.h b/20080212/Demo/Common/drivers/LuminaryMicro/hw_flash.h new file mode 100644 index 000000000..e4f147bce --- /dev/null +++ b/20080212/Demo/Common/drivers/LuminaryMicro/hw_flash.h @@ -0,0 +1,147 @@ +//***************************************************************************** +// +// hw_flash.h - Macros used when accessing the flash controller. +// +// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1582 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __HW_FLASH_H__ +#define __HW_FLASH_H__ + +//***************************************************************************** +// +// The following define the offsets of the FLASH registers. +// +//***************************************************************************** +#define FLASH_FMA 0x400FD000 // Memory address register +#define FLASH_FMD 0x400FD004 // Memory data register +#define FLASH_FMC 0x400FD008 // Memory control register +#define FLASH_FCRIS 0x400FD00c // Raw interrupt status register +#define FLASH_FCIM 0x400FD010 // Interrupt mask register +#define FLASH_FCMISC 0x400FD014 // Interrupt status register +#define FLASH_FMPRE 0x400FE130 // FLASH read protect register +#define FLASH_FMPPE 0x400FE134 // FLASH program protect register +#define FLASH_USECRL 0x400FE140 // uSec reload register +#define FLASH_FMPRE0 0x400FE200 // FLASH read protect register 0 +#define FLASH_FMPRE1 0x400FE204 // FLASH read protect register 1 +#define FLASH_FMPRE2 0x400FE208 // FLASH read protect register 2 +#define FLASH_FMPRE3 0x400FE20C // FLASH read protect register 3 +#define FLASH_FMPPE0 0x400FE400 // FLASH program protect register 0 +#define FLASH_FMPPE1 0x400FE404 // FLASH program protect register 1 +#define FLASH_FMPPE2 0x400FE408 // FLASH program protect register 2 +#define FLASH_FMPPE3 0x400FE40C // FLASH program protect register 3 + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FMC register. +// +//***************************************************************************** +#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask +#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key +#define FLASH_FMC_COMT 0x00000008 // Commit user register +#define FLASH_FMC_MERASE 0x00000004 // Mass erase FLASH +#define FLASH_FMC_ERASE 0x00000002 // Erase FLASH page +#define FLASH_FMC_WRITE 0x00000001 // Write FLASH word + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FCRIS register. +// +//***************************************************************************** +#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status +#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FCIM register. +// +//***************************************************************************** +#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask +#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FMIS register. +// +//***************************************************************************** +#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status +#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_FMPRE and FLASH_FMPPE +// registers. +// +//***************************************************************************** +#define FLASH_FMP_BLOCK_31 0x80000000 // Enable for block 31 +#define FLASH_FMP_BLOCK_30 0x40000000 // Enable for block 30 +#define FLASH_FMP_BLOCK_29 0x20000000 // Enable for block 29 +#define FLASH_FMP_BLOCK_28 0x10000000 // Enable for block 28 +#define FLASH_FMP_BLOCK_27 0x08000000 // Enable for block 27 +#define FLASH_FMP_BLOCK_26 0x04000000 // Enable for block 26 +#define FLASH_FMP_BLOCK_25 0x02000000 // Enable for block 25 +#define FLASH_FMP_BLOCK_24 0x01000000 // Enable for block 24 +#define FLASH_FMP_BLOCK_23 0x00800000 // Enable for block 23 +#define FLASH_FMP_BLOCK_22 0x00400000 // Enable for block 22 +#define FLASH_FMP_BLOCK_21 0x00200000 // Enable for block 21 +#define FLASH_FMP_BLOCK_20 0x00100000 // Enable for block 20 +#define FLASH_FMP_BLOCK_19 0x00080000 // Enable for block 19 +#define FLASH_FMP_BLOCK_18 0x00040000 // Enable for block 18 +#define FLASH_FMP_BLOCK_17 0x00020000 // Enable for block 17 +#define FLASH_FMP_BLOCK_16 0x00010000 // Enable for block 16 +#define FLASH_FMP_BLOCK_15 0x00008000 // Enable for block 15 +#define FLASH_FMP_BLOCK_14 0x00004000 // Enable for block 14 +#define FLASH_FMP_BLOCK_13 0x00002000 // Enable for block 13 +#define FLASH_FMP_BLOCK_12 0x00001000 // Enable for block 12 +#define FLASH_FMP_BLOCK_11 0x00000800 // Enable for block 11 +#define FLASH_FMP_BLOCK_10 0x00000400 // Enable for block 10 +#define FLASH_FMP_BLOCK_9 0x00000200 // Enable for block 9 +#define FLASH_FMP_BLOCK_8 0x00000100 // Enable for block 8 +#define FLASH_FMP_BLOCK_7 0x00000080 // Enable for block 7 +#define FLASH_FMP_BLOCK_6 0x00000040 // Enable for block 6 +#define FLASH_FMP_BLOCK_5 0x00000020 // Enable for block 5 +#define FLASH_FMP_BLOCK_4 0x00000010 // Enable for block 4 +#define FLASH_FMP_BLOCK_3 0x00000008 // Enable for block 3 +#define FLASH_FMP_BLOCK_2 0x00000004 // Enable for block 2 +#define FLASH_FMP_BLOCK_1 0x00000002 // Enable for block 1 +#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0 + +//***************************************************************************** +// +// The following define the bit fields in the FLASH_USECRL register. +// +//***************************************************************************** +#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec +#define FLASH_USECRL_SHIFT 0 + +//***************************************************************************** +// +// The erase size is the size of the FLASH block that is erased by an erase +// operation, and the protect size is the size of the FLASH block that is +// protected by each protection register. +// +//***************************************************************************** +#define FLASH_ERASE_SIZE 0x00000400 +#define FLASH_PROTECT_SIZE 0x00000800 + +#endif // __HW_FLASH_H__ diff --git a/20080212/Demo/Common/drivers/LuminaryMicro/hw_gpio.h b/20080212/Demo/Common/drivers/LuminaryMicro/hw_gpio.h new file mode 100644 index 000000000..1b6c15a88 --- /dev/null +++ b/20080212/Demo/Common/drivers/LuminaryMicro/hw_gpio.h @@ -0,0 +1,115 @@ +//***************************************************************************** +// +// hw_gpio.h - Defines and Macros for GPIO hardware. +// +// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1582 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __HW_GPIO_H__ +#define __HW_GPIO_H__ + +//***************************************************************************** +// +// GPIO Register Offsets. +// +//***************************************************************************** +#define GPIO_O_DATA 0x00000000 // Data register. +#define GPIO_O_DIR 0x00000400 // Data direction register. +#define GPIO_O_IS 0x00000404 // Interrupt sense register. +#define GPIO_O_IBE 0x00000408 // Interrupt both edges register. +#define GPIO_O_IEV 0x0000040C // Interrupt event register. +#define GPIO_O_IM 0x00000410 // Interrupt mask register. +#define GPIO_O_RIS 0x00000414 // Raw interrupt status register. +#define GPIO_O_MIS 0x00000418 // Masked interrupt status reg. +#define GPIO_O_ICR 0x0000041C // Interrupt clear register. +#define GPIO_O_AFSEL 0x00000420 // Mode control select register. +#define GPIO_O_DR2R 0x00000500 // 2ma drive select register. +#define GPIO_O_DR4R 0x00000504 // 4ma drive select register. +#define GPIO_O_DR8R 0x00000508 // 8ma drive select register. +#define GPIO_O_ODR 0x0000050C // Open drain select register. +#define GPIO_O_PUR 0x00000510 // Pull up select register. +#define GPIO_O_PDR 0x00000514 // Pull down select register. +#define GPIO_O_SLR 0x00000518 // Slew rate control enable reg. +#define GPIO_O_DEN 0x0000051C // Digital input enable register. +#define GPIO_O_LOCK 0x00000520 // Lock register. +#define GPIO_O_CR 0x00000524 // Commit register. +#define GPIO_O_PeriphID4 0x00000FD0 // +#define GPIO_O_PeriphID5 0x00000FD4 // +#define GPIO_O_PeriphID6 0x00000FD8 // +#define GPIO_O_PeriphID7 0x00000FDC // +#define GPIO_O_PeriphID0 0x00000FE0 // +#define GPIO_O_PeriphID1 0x00000FE4 // +#define GPIO_O_PeriphID2 0x00000FE8 // +#define GPIO_O_PeriphID3 0x00000FEC // +#define GPIO_O_PCellID0 0x00000FF0 // +#define GPIO_O_PCellID1 0x00000FF4 // +#define GPIO_O_PCellID2 0x00000FF8 // +#define GPIO_O_PCellID3 0x00000FFC // + +//***************************************************************************** +// +// The following define the bit fields in the GPIO_LOCK register. +// +//***************************************************************************** +#define GPIO_LOCK_LOCKED 0x00000001 // GPIO_CR register is locked +#define GPIO_LOCK_UNLOCKED 0x00000000 // GPIO_CR register is unlocked +#define GPIO_LOCK_KEY 0x1ACCE551 // Unlocks the GPIO_CR register + +//***************************************************************************** +// +// GPIO Register reset values. +// +//***************************************************************************** +#define GPIO_RV_DATA 0x00000000 // Data register reset value. +#define GPIO_RV_DIR 0x00000000 // Data direction reg RV. +#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV. +#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV. +#define GPIO_RV_IEV 0x00000000 // Interrupt event reg RV. +#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV. +#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV. +#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV. +#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV. +#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV. +#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV. +#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV. +#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV. +#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV. +#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV. +#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV. +#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV. +#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV. +#define GPIO_RV_LOCK 0x00000001 // Lock register RV. +#define GPIO_RV_PeriphID4 0x00000000 // +#define GPIO_RV_PeriphID5 0x00000000 // +#define GPIO_RV_PeriphID6 0x00000000 // +#define GPIO_RV_PeriphID7 0x00000000 // +#define GPIO_RV_PeriphID0 0x00000061 // +#define GPIO_RV_PeriphID1 0x00000010 // +#define GPIO_RV_PeriphID2 0x00000004 // +#define GPIO_RV_PeriphID3 0x00000000 // +#define GPIO_RV_PCellID0 0x0000000D // +#define GPIO_RV_PCellID1 0x000000F0 // +#define GPIO_RV_PCellID2 0x00000005 // +#define GPIO_RV_PCellID3 0x000000B1 // + +#endif // __HW_GPIO_H__ diff --git a/20080212/Demo/Common/drivers/LuminaryMicro/hw_hibernate.h b/20080212/Demo/Common/drivers/LuminaryMicro/hw_hibernate.h new file mode 100644 index 000000000..a363cceff --- /dev/null +++ b/20080212/Demo/Common/drivers/LuminaryMicro/hw_hibernate.h @@ -0,0 +1,145 @@ +//***************************************************************************** +// +// hw_hibernate.h - Defines and Macros for the Hibernation module. +// +// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1582 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __HW_HIBERNATE_H__ +#define __HW_HIBERNATE_H__ + +//***************************************************************************** +// +// The following define the addresses of the hibernation module registers. +// +//***************************************************************************** +#define HIB_RTCC 0x400fc000 // Hibernate RTC counter +#define HIB_RTCM0 0x400fc004 // Hibernate RTC match 0 +#define HIB_RTCM1 0x400fc008 // Hibernate RTC match 1 +#define HIB_RTCLD 0x400fc00C // Hibernate RTC load +#define HIB_CTL 0x400fc010 // Hibernate RTC control +#define HIB_IM 0x400fc014 // Hibernate interrupt mask +#define HIB_RIS 0x400fc018 // Hibernate raw interrupt status +#define HIB_MIS 0x400fc01C // Hibernate masked interrupt stat +#define HIB_IC 0x400fc020 // Hibernate interrupt clear +#define HIB_RTCT 0x400fc024 // Hibernate RTC trim +#define HIB_DATA 0x400fc030 // Hibernate data area +#define HIB_DATA_END 0x400fc130 // end of data area, exclusive + +//***************************************************************************** +// +// The following define the bit fields in the Hibernate RTC counter register. +// +//***************************************************************************** +#define HIB_RTCC_MASK 0xffffffff // RTC counter mask + +//***************************************************************************** +// +// The following define the bit fields in the Hibernate RTC match 0 register. +// +//***************************************************************************** +#define HIB_RTCM0_MASK 0xffffffff // RTC match 0 mask + +//***************************************************************************** +// +// The following define the bit fields in the Hibernate RTC match 1 register. +// +//***************************************************************************** +#define HIB_RTCM1_MASK 0xffffffff // RTC match 1 mask + +//***************************************************************************** +// +// The following define the bit fields in the Hibernate RTC load register. +// +//***************************************************************************** +#define HIB_RTCLD_MASK 0xffffffff // RTC load mask + +//***************************************************************************** +// +// The following define the bit fields in the Hibernate control register +// +//***************************************************************************** +#define HIB_CTL_VABORT 0x00000080 // low bat abort +#define HIB_CTL_CLK32EN 0x00000040 // enable clock/oscillator +#define HIB_CTL_LOWBATEN 0x00000020 // enable low battery detect +#define HIB_CTL_PINWEN 0x00000010 // enable wake on WAKE pin +#define HIB_CTL_RTCWEN 0x00000008 // enable wake on RTC match +#define HIB_CTL_CLKSEL 0x00000004 // clock input selection +#define HIB_CTL_HIBREQ 0x00000002 // request hibernation +#define HIB_CTL_RTCEN 0x00000001 // RTC enable + +//***************************************************************************** +// +// The following define the bit fields in the Hibernate interrupt mask reg. +// +//***************************************************************************** +#define HIB_IM_EXTW 0x00000008 // wake from external pin interrupt +#define HIB_IM_LOWBAT 0x00000004 // low battery interrupt +#define HIB_IM_RTCALT1 0x00000002 // RTC match 1 interrupt +#define HIB_IM_RTCALT0 0x00000001 // RTC match 0 interrupt + +//***************************************************************************** +// +// The following define the bit fields in the Hibernate raw interrupt status. +// +//***************************************************************************** +#define HIB_RIS_EXTW 0x00000008 // wake from external pin interrupt +#define HIB_RIS_LOWBAT 0x00000004 // low battery interrupt +#define HIB_RIS_RTCALT1 0x00000002 // RTC match 1 interrupt +#define HIB_RID_RTCALT0 0x00000001 // RTC match 0 interrupt + +//***************************************************************************** +// +// The following define the bit fields in the Hibernate masked int status. +// +//***************************************************************************** +#define HIB_MIS_EXTW 0x00000008 // wake from external pin interrupt +#define HIB_MIS_LOWBAT 0x00000004 // low battery interrupt +#define HIB_MIS_RTCALT1 0x00000002 // RTC match 1 interrupt +#define HIB_MID_RTCALT0 0x00000001 // RTC match 0 interrupt + +//***************************************************************************** +// +// The following define the bit fields in the Hibernate interrupt clear reg. +// +//***************************************************************************** +#define HIB_IC_EXTW 0x00000008 // wake from external pin interrupt +#define HIB_IC_LOWBAT 0x00000004 // low battery interrupt +#define HIB_IC_RTCALT1 0x00000002 // RTC match 1 interrupt +#define HIB_IC_RTCALT0 0x00000001 // RTC match 0 interrupt + +//***************************************************************************** +// +// The following define the bit fields in the Hibernate RTC trim register. +// +//***************************************************************************** +#define HIB_RTCT_MASK 0x0000ffff // RTC trim mask + +//***************************************************************************** +// +// The following define the bit fields in the Hibernate data register. +// +//***************************************************************************** +#define HIB_DATA_MASK 0xffffffff // NV memory data mask + +#endif // __HW_HIBERNATE_H__ diff --git a/20080212/Demo/Common/drivers/LuminaryMicro/hw_i2c.h b/20080212/Demo/Common/drivers/LuminaryMicro/hw_i2c.h new file mode 100644 index 000000000..0c0d54f26 --- /dev/null +++ b/20080212/Demo/Common/drivers/LuminaryMicro/hw_i2c.h @@ -0,0 +1,197 @@ +//***************************************************************************** +// +// hw_i2c.h - Macros used when accessing the I2C master and slave hardware. +// +// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1582 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __HW_I2C_H__ +#define __HW_I2C_H__ + +//***************************************************************************** +// +// The following defines the offset between the I2C master and slave registers. +// +//***************************************************************************** +#define I2C_O_SLAVE 0x00000800 // Offset from master to slave + +//***************************************************************************** +// +// The following define the offsets of the I2C master registers. +// +//***************************************************************************** +#define I2C_MASTER_O_SA 0x00000000 // Slave address register +#define I2C_MASTER_O_CS 0x00000004 // Control and Status register +#define I2C_MASTER_O_DR 0x00000008 // Data register +#define I2C_MASTER_O_TPR 0x0000000C // Timer period register +#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register +#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register +#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg +#define I2C_MASTER_O_MICR 0x0000001c // Interrupt clear register +#define I2C_MASTER_O_CR 0x00000020 // Configuration register + +//***************************************************************************** +// +// The following define the offsets of the I2C slave registers. +// +//***************************************************************************** +#define I2C_SLAVE_O_OAR 0x00000000 // Own address register +#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register +#define I2C_SLAVE_O_DR 0x00000008 // Data register +#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register +#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register +#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg +#define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register + +//***************************************************************************** +// +// The followng define the bit fields in the I2C master slave address register. +// +//***************************************************************************** +#define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address +#define I2C_MASTER_SA_RS 0x00000001 // Receive/send +#define I2C_MASTER_SA_SA_SHIFT 1 + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Control and Status +// register. +// +//***************************************************************************** +#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde +#define I2C_MASTER_CS_STOP 0x00000004 // Stop +#define I2C_MASTER_CS_START 0x00000002 // Start +#define I2C_MASTER_CS_RUN 0x00000001 // Run +#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy +#define I2C_MASTER_CS_IDLE 0x00000020 // Idle +#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration +#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged +#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged +#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred +#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data +#define I2C_MASTER_CS_ERR_MASK 0x0000001C + +//***************************************************************************** +// +// The following define values used in determining the contents of the I2C +// Master Timer Period register. +// +//***************************************************************************** +#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period +#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period +#define I2C_MASTER_TPR_SCL (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP) +#define I2C_SCL_STANDARD 100000 // SCL standard frequency +#define I2C_SCL_FAST 400000 // SCL fast frequency + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Interrupt Mask +// register. +// +//***************************************************************************** +#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Raw Interrupt Status +// register. +// +//***************************************************************************** +#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Masked Interrupt +// Status register. +// +//***************************************************************************** +#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Interrupt Clear +// register. +// +//***************************************************************************** +#define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear + +//***************************************************************************** +// +// The following define the bit fields in the I2C Master Configuration +// register. +// +//***************************************************************************** +#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable +#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable +#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Own Address register. +// +//***************************************************************************** +#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Control/Status +// register. +// +//***************************************************************************** +#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device +#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received +#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Interrupt Mask +// register. +// +//***************************************************************************** +#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Raw Interrupt Status +// register. +// +//***************************************************************************** +#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Masked Interrupt +// Status register. +// +//***************************************************************************** +#define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status + +//***************************************************************************** +// +// The following define the bit fields in the I2C Slave Interrupt Clear +// register. +// +//***************************************************************************** +#define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear + +#endif // __HW_I2C_H__ diff --git a/20080212/Demo/Common/drivers/LuminaryMicro/hw_ints.h b/20080212/Demo/Common/drivers/LuminaryMicro/hw_ints.h new file mode 100644 index 000000000..8e97c6550 --- /dev/null +++ b/20080212/Demo/Common/drivers/LuminaryMicro/hw_ints.h @@ -0,0 +1,114 @@ +//***************************************************************************** +// +// hw_ints.h - Macros that define the interrupt assignment on Stellaris. +// +// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1582 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __HW_INTS_H__ +#define __HW_INTS_H__ + +//***************************************************************************** +// +// The following define the fault assignments. +// +//***************************************************************************** +#define FAULT_NMI 2 // NMI fault +#define FAULT_HARD 3 // Hard fault +#define FAULT_MPU 4 // MPU fault +#define FAULT_BUS 5 // Bus fault +#define FAULT_USAGE 6 // Usage fault +#define FAULT_SVCALL 11 // SVCall +#define FAULT_DEBUG 12 // Debug monitor +#define FAULT_PENDSV 14 // PendSV +#define FAULT_SYSTICK 15 // System Tick + +//***************************************************************************** +// +// The following define the interrupt assignments. +// +//***************************************************************************** +#define INT_GPIOA 16 // GPIO Port A +#define INT_GPIOB 17 // GPIO Port B +#define INT_GPIOC 18 // GPIO Port C +#define INT_GPIOD 19 // GPIO Port D +#define INT_GPIOE 20 // GPIO Port E +#define INT_UART0 21 // UART0 Rx and Tx +#define INT_UART1 22 // UART1 Rx and Tx +#define INT_SSI 23 // SSI Rx and Tx +#define INT_SSI0 23 // SSI0 Rx and Tx +#define INT_I2C 24 // I2C Master and Slave +#define INT_I2C0 24 // I2C0 Master and Slave +#define INT_PWM_FAULT 25 // PWM Fault +#define INT_PWM0 26 // PWM Generator 0 +#define INT_PWM1 27 // PWM Generator 1 +#define INT_PWM2 28 // PWM Generator 2 +#define INT_QEI 29 // Quadrature Encoder +#define INT_QEI0 29 // Quadrature Encoder 0 +#define INT_ADC0 30 // ADC Sequence 0 +#define INT_ADC1 31 // ADC Sequence 1 +#define INT_ADC2 32 // ADC Sequence 2 +#define INT_ADC3 33 // ADC Sequence 3 +#define INT_WATCHDOG 34 // Watchdog timer +#define INT_TIMER0A 35 // Timer 0 subtimer A +#define INT_TIMER0B 36 // Timer 0 subtimer B +#define INT_TIMER1A 37 // Timer 1 subtimer A +#define INT_TIMER1B 38 // Timer 1 subtimer B +#define INT_TIMER2A 39 // Timer 2 subtimer A +#define INT_TIMER2B 40 // Timer 2 subtimer B +#define INT_COMP0 41 // Analog Comparator 0 +#define INT_COMP1 42 // Analog Comparator 1 +#define INT_COMP2 43 // Analog Comparator 2 +#define INT_SYSCTL 44 // System Control (PLL, OSC, BO) +#define INT_FLASH 45 // FLASH Control +#define INT_GPIOF 46 // GPIO Port F +#define INT_GPIOG 47 // GPIO Port G +#define INT_GPIOH 48 // GPIO Port H +#define INT_UART2 49 // UART2 Rx and Tx +#define INT_SSI1 50 // SSI1 Rx and Tx +#define INT_TIMER3A 51 // Timer 3 subtimer A +#define INT_TIMER3B 52 // Timer 3 subtimer B +#define INT_I2C1 53 // I2C1 Master and Slave +#define INT_QEI1 54 // Quadrature Encoder 1 +#define INT_CAN0 55 // CAN0 +#define INT_CAN1 56 // CAN1 +#define INT_CAN2 57 // CAN2 +#define INT_ETH 58 // Ethernet +#define INT_HIBERNATE 59 // Hibernation module + +//***************************************************************************** +// +// The total number of interrupts. +// +//***************************************************************************** +#define NUM_INTERRUPTS 60 + +//***************************************************************************** +// +// The total number of priority levels. +// +//***************************************************************************** +#define NUM_PRIORITY 8 +#define NUM_PRIORITY_BITS 3 + +#endif // __HW_INTS_H__ diff --git a/20080212/Demo/Common/drivers/LuminaryMicro/hw_memmap.h b/20080212/Demo/Common/drivers/LuminaryMicro/hw_memmap.h new file mode 100644 index 000000000..ac1bf2d86 --- /dev/null +++ b/20080212/Demo/Common/drivers/LuminaryMicro/hw_memmap.h @@ -0,0 +1,81 @@ +//***************************************************************************** +// +// hw_memmap.h - Macros defining the memory map of Stellaris. +// +// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1582 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __HW_MEMMAP_H__ +#define __HW_MEMMAP_H__ + +//***************************************************************************** +// +// The following define the base address of the memories and peripherals. +// +//***************************************************************************** +#define FLASH_BASE 0x00000000 // FLASH memory +#define SRAM_BASE 0x20000000 // SRAM memory +#define WATCHDOG_BASE 0x40000000 // Watchdog +#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A +#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B +#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C +#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D +#define SSI_BASE 0x40008000 // SSI +#define SSI0_BASE 0x40008000 // SSI0 +#define SSI1_BASE 0x40009000 // SSI1 +#define UART0_BASE 0x4000C000 // UART0 +#define UART1_BASE 0x4000D000 // UART1 +#define UART2_BASE 0x4000E000 // UART2 +#define I2C_MASTER_BASE 0x40020000 // I2C Master +#define I2C_SLAVE_BASE 0x40020800 // I2C Slave +#define I2C0_MASTER_BASE 0x40020000 // I2C0 Master +#define I2C0_SLAVE_BASE 0x40020800 // I2C0 Slave +#define I2C1_MASTER_BASE 0x40021000 // I2C1 Master +#define I2C1_SLAVE_BASE 0x40021800 // I2C1 Slave +#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E +#define GPIO_PORTF_BASE 0x40025000 // GPIO Port F +#define GPIO_PORTG_BASE 0x40026000 // GPIO Port G +#define GPIO_PORTH_BASE 0x40027000 // GPIO Port H +#define PWM_BASE 0x40028000 // PWM +#define QEI_BASE 0x4002C000 // QEI +#define QEI0_BASE 0x4002C000 // QEI0 +#define QEI1_BASE 0x4002D000 // QEI1 +#define TIMER0_BASE 0x40030000 // Timer0 +#define TIMER1_BASE 0x40031000 // Timer1 +#define TIMER2_BASE 0x40032000 // Timer2 +#define TIMER3_BASE 0x40033000 // Timer3 +#define ADC_BASE 0x40038000 // ADC +#define COMP_BASE 0x4003C000 // Analog comparators +#define CAN0_BASE 0x40040000 // CAN0 +#define CAN1_BASE 0x40041000 // CAN1 +#define CAN2_BASE 0x40042000 // CAN2 +#define ETH_BASE 0x40048000 // Ethernet +#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller +#define SYSCTL_BASE 0x400FE000 // System Control +#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell +#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace +#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint +#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl +#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit + +#endif // __HW_MEMMAP_H__ diff --git a/20080212/Demo/Common/drivers/LuminaryMicro/hw_nvic.h b/20080212/Demo/Common/drivers/LuminaryMicro/hw_nvic.h new file mode 100644 index 000000000..862f40cc0 --- /dev/null +++ b/20080212/Demo/Common/drivers/LuminaryMicro/hw_nvic.h @@ -0,0 +1,1050 @@ +//***************************************************************************** +// +// hw_nvic.h - Macros used when accessing the NVIC hardware. +// +// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1582 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __HW_NVIC_H__ +#define __HW_NVIC_H__ + +//***************************************************************************** +// +// The following define the addresses of the NVIC registers. +// +//***************************************************************************** +#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg. +#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg. +#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register +#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register +#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg. +#define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register +#define NVIC_EN1 0xE000E104 // IRQ 32 to 63 Set Enable Register +#define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg. +#define NVIC_DIS1 0xE000E184 // IRQ 32 to 63 Clear Enable Reg. +#define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register +#define NVIC_PEND1 0xE000E204 // IRQ 32 to 63 Set Pending Reg. +#define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg. +#define NVIC_UNPEND1 0xE000E284 // IRQ 32 to 63 Clear Pending Reg. +#define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register +#define NVIC_ACTIVE1 0xE000E304 // IRQ 32 to 63 Active Register +#define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register +#define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register +#define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register +#define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register +#define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register +#define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register +#define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register +#define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register +#define NVIC_PRI8 0xE000E420 // IRQ 32 to 35 Priority Register +#define NVIC_PRI9 0xE000E424 // IRQ 36 to 39 Priority Register +#define NVIC_PRI10 0xE000E428 // IRQ 40 to 43 Priority Register +#define NVIC_CPUID 0xE000ED00 // CPUID Base Register +#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register +#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register +#define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg. +#define NVIC_SYS_CTRL 0xE000ED10 // System Control Register +#define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register +#define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority +#define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority +#define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority +#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State +#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg. +#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register +#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register +#define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register +#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register +#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register +#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register +#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register +#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register +#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg. +#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg. +#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select +#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data +#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control +#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg. + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_INT_TYPE register. +// +//***************************************************************************** +#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) +#define NVIC_INT_TYPE_LINES_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_CTRL register. +// +//***************************************************************************** +#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag +#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source +#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable +#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_RELOAD register. +// +//***************************************************************************** +#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value +#define NVIC_ST_RELOAD_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_CURRENT register. +// +//***************************************************************************** +#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value +#define NVIC_ST_CURRENT_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ST_CAL register. +// +//***************************************************************************** +#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock +#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew +#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value +#define NVIC_ST_CAL_ONEMS_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_EN0 register. +// +//***************************************************************************** +#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable +#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable +#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable +#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable +#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable +#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable +#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable +#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable +#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable +#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable +#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable +#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable +#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable +#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable +#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable +#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable +#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable +#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable +#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable +#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable +#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable +#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable +#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable +#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable +#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable +#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable +#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable +#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable +#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable +#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable +#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable +#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_EN1 register. +// +//***************************************************************************** +#define NVIC_EN1_INT59 0x08000000 // Interrupt 59 enable +#define NVIC_EN1_INT58 0x04000000 // Interrupt 58 enable +#define NVIC_EN1_INT57 0x02000000 // Interrupt 57 enable +#define NVIC_EN1_INT56 0x01000000 // Interrupt 56 enable +#define NVIC_EN1_INT55 0x00800000 // Interrupt 55 enable +#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable +#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable +#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable +#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable +#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable +#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable +#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable +#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable +#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable +#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable +#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable +#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable +#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable +#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable +#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable +#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable +#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable +#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable +#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable +#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable +#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable +#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable +#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DIS0 register. +// +//***************************************************************************** +#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable +#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable +#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable +#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable +#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable +#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable +#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable +#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable +#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable +#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable +#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable +#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable +#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable +#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable +#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable +#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable +#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable +#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable +#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable +#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable +#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable +#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable +#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable +#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable +#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable +#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable +#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable +#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable +#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable +#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable +#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable +#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DIS1 register. +// +//***************************************************************************** +#define NVIC_DIS1_INT59 0x08000000 // Interrupt 59 disable +#define NVIC_DIS1_INT58 0x04000000 // Interrupt 58 disable +#define NVIC_DIS1_INT57 0x02000000 // Interrupt 57 disable +#define NVIC_DIS1_INT56 0x01000000 // Interrupt 56 disable +#define NVIC_DIS1_INT55 0x00800000 // Interrupt 55 disable +#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable +#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable +#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable +#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable +#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable +#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable +#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable +#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable +#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable +#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable +#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable +#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable +#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable +#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable +#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable +#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable +#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable +#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable +#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable +#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable +#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable +#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable +#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PEND0 register. +// +//***************************************************************************** +#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend +#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend +#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend +#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend +#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend +#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend +#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend +#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend +#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend +#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend +#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend +#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend +#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend +#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend +#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend +#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend +#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend +#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend +#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend +#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend +#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend +#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend +#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend +#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend +#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend +#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend +#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend +#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend +#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend +#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend +#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend +#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PEND1 register. +// +//***************************************************************************** +#define NVIC_PEND1_INT59 0x08000000 // Interrupt 59 pend +#define NVIC_PEND1_INT58 0x04000000 // Interrupt 58 pend +#define NVIC_PEND1_INT57 0x02000000 // Interrupt 57 pend +#define NVIC_PEND1_INT56 0x01000000 // Interrupt 56 pend +#define NVIC_PEND1_INT55 0x00800000 // Interrupt 55 pend +#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend +#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend +#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend +#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend +#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend +#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend +#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend +#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend +#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend +#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend +#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend +#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend +#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend +#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend +#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend +#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend +#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend +#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend +#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend +#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend +#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend +#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend +#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_UNPEND0 register. +// +//***************************************************************************** +#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend +#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend +#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend +#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend +#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend +#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend +#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend +#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend +#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend +#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend +#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend +#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend +#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend +#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend +#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend +#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend +#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend +#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend +#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend +#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend +#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend +#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend +#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend +#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend +#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend +#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend +#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend +#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend +#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend +#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend +#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend +#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_UNPEND1 register. +// +//***************************************************************************** +#define NVIC_UNPEND1_INT59 0x08000000 // Interrupt 59 unpend +#define NVIC_UNPEND1_INT58 0x04000000 // Interrupt 58 unpend +#define NVIC_UNPEND1_INT57 0x02000000 // Interrupt 57 unpend +#define NVIC_UNPEND1_INT56 0x01000000 // Interrupt 56 unpend +#define NVIC_UNPEND1_INT55 0x00800000 // Interrupt 55 unpend +#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend +#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend +#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend +#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend +#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend +#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend +#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend +#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend +#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend +#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend +#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend +#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend +#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend +#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend +#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend +#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend +#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend +#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend +#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend +#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend +#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend +#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend +#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ACTIVE0 register. +// +//***************************************************************************** +#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active +#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active +#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active +#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active +#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active +#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active +#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active +#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active +#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active +#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active +#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active +#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active +#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active +#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active +#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active +#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active +#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active +#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active +#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active +#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active +#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active +#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active +#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active +#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active +#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active +#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active +#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active +#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active +#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active +#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active +#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active +#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_ACTIVE1 register. +// +//***************************************************************************** +#define NVIC_ACTIVE1_INT59 0x08000000 // Interrupt 59 active +#define NVIC_ACTIVE1_INT58 0x04000000 // Interrupt 58 active +#define NVIC_ACTIVE1_INT57 0x02000000 // Interrupt 57 active +#define NVIC_ACTIVE1_INT56 0x01000000 // Interrupt 56 active +#define NVIC_ACTIVE1_INT55 0x00800000 // Interrupt 55 active +#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active +#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active +#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active +#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active +#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active +#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active +#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active +#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active +#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active +#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active +#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active +#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active +#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active +#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active +#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active +#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active +#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active +#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active +#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active +#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active +#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active +#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active +#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI0 register. +// +//***************************************************************************** +#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask +#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask +#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask +#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask +#define NVIC_PRI0_INT3_S 24 +#define NVIC_PRI0_INT2_S 16 +#define NVIC_PRI0_INT1_S 8 +#define NVIC_PRI0_INT0_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI1 register. +// +//***************************************************************************** +#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask +#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask +#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask +#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask +#define NVIC_PRI1_INT7_S 24 +#define NVIC_PRI1_INT6_S 16 +#define NVIC_PRI1_INT5_S 8 +#define NVIC_PRI1_INT4_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI2 register. +// +//***************************************************************************** +#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask +#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask +#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask +#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask +#define NVIC_PRI2_INT11_S 24 +#define NVIC_PRI2_INT10_S 16 +#define NVIC_PRI2_INT9_S 8 +#define NVIC_PRI2_INT8_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI3 register. +// +//***************************************************************************** +#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask +#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask +#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask +#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask +#define NVIC_PRI3_INT15_S 24 +#define NVIC_PRI3_INT14_S 16 +#define NVIC_PRI3_INT13_S 8 +#define NVIC_PRI3_INT12_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI4 register. +// +//***************************************************************************** +#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask +#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask +#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask +#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask +#define NVIC_PRI4_INT19_S 24 +#define NVIC_PRI4_INT18_S 16 +#define NVIC_PRI4_INT17_S 8 +#define NVIC_PRI4_INT16_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI5 register. +// +//***************************************************************************** +#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask +#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask +#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask +#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask +#define NVIC_PRI5_INT23_S 24 +#define NVIC_PRI5_INT22_S 16 +#define NVIC_PRI5_INT21_S 8 +#define NVIC_PRI5_INT20_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI6 register. +// +//***************************************************************************** +#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask +#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask +#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask +#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask +#define NVIC_PRI6_INT27_S 24 +#define NVIC_PRI6_INT26_S 16 +#define NVIC_PRI6_INT25_S 8 +#define NVIC_PRI6_INT24_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI7 register. +// +//***************************************************************************** +#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask +#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask +#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask +#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask +#define NVIC_PRI7_INT31_S 24 +#define NVIC_PRI7_INT30_S 16 +#define NVIC_PRI7_INT29_S 8 +#define NVIC_PRI7_INT28_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI8 register. +// +//***************************************************************************** +#define NVIC_PRI8_INT35_M 0xFF000000 // Interrupt 35 priority mask +#define NVIC_PRI8_INT34_M 0x00FF0000 // Interrupt 34 priority mask +#define NVIC_PRI8_INT33_M 0x0000FF00 // Interrupt 33 priority mask +#define NVIC_PRI8_INT32_M 0x000000FF // Interrupt 32 priority mask +#define NVIC_PRI8_INT35_S 24 +#define NVIC_PRI8_INT34_S 16 +#define NVIC_PRI8_INT33_S 8 +#define NVIC_PRI8_INT32_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI9 register. +// +//***************************************************************************** +#define NVIC_PRI9_INT39_M 0xFF000000 // Interrupt 39 priority mask +#define NVIC_PRI9_INT38_M 0x00FF0000 // Interrupt 38 priority mask +#define NVIC_PRI9_INT37_M 0x0000FF00 // Interrupt 37 priority mask +#define NVIC_PRI9_INT36_M 0x000000FF // Interrupt 36 priority mask +#define NVIC_PRI9_INT39_S 24 +#define NVIC_PRI9_INT38_S 16 +#define NVIC_PRI9_INT37_S 8 +#define NVIC_PRI9_INT36_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_PRI10 register. +// +//***************************************************************************** +#define NVIC_PRI10_INT43_M 0xFF000000 // Interrupt 43 priority mask +#define NVIC_PRI10_INT42_M 0x00FF0000 // Interrupt 42 priority mask +#define NVIC_PRI10_INT41_M 0x0000FF00 // Interrupt 41 priority mask +#define NVIC_PRI10_INT40_M 0x000000FF // Interrupt 40 priority mask +#define NVIC_PRI10_INT43_S 24 +#define NVIC_PRI10_INT42_S 16 +#define NVIC_PRI10_INT41_S 8 +#define NVIC_PRI10_INT40_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_CPUID register. +// +//***************************************************************************** +#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer +#define NVIC_CPUID_VAR_M 0x00F00000 // Variant +#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number +#define NVIC_CPUID_REV_M 0x0000000F // Revision + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_INT_CTRL register. +// +//***************************************************************************** +#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI +#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV +#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV +#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling +#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending +#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception +#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base +#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception +#define NVIC_INT_CTRL_VEC_PEN_S 12 +#define NVIC_INT_CTRL_VEC_ACT_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_VTABLE register. +// +//***************************************************************************** +#define NVIC_VTABLE_BASE 0x20000000 // Vector table base +#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset +#define NVIC_VTABLE_OFFSET_S 8 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_APINT register. +// +//***************************************************************************** +#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask +#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key +#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess +#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group +#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split +#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split +#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split +#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split +#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split +#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split +#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split +#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split +#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request +#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info +#define NVIC_APINT_VECT_RESET 0x00000001 // System reset + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend +#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable +#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_CFG_CTRL register. +// +//***************************************************************************** +#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault +#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0 +#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access +#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger +#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger +#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_PRI1 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler +#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler +#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler +#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler +#define NVIC_SYS_PRI1_USAGE_S 16 +#define NVIC_SYS_PRI1_BUS_S 8 +#define NVIC_SYS_PRI1_MEM_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_PRI2 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler +#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers +#define NVIC_SYS_PRI2_SVC_S 24 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_PRI3 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler +#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler +#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler +#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler +#define NVIC_SYS_PRI3_TICK_S 24 +#define NVIC_SYS_PRI3_PENDSV_S 16 +#define NVIC_SYS_PRI3_DEBUG_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SYS_HND_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable +#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable +#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable +#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended +#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended +#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active +#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active +#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active +#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active +#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active +#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active +#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_FAULT_STAT register. +// +//***************************************************************************** +#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault +#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault +#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault +#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault +#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault +#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault +#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid +#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault +#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault +#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error +#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error +#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault +#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid +#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation +#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation +#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation +#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_HFAULT_STAT register. +// +//***************************************************************************** +#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event +#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler +#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DEBUG_STAT register. +// +//***************************************************************************** +#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted +#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch +#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match +#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction +#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MM_ADDR register. +// +//***************************************************************************** +#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address +#define NVIC_MM_ADDR_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_FAULT_ADDR register. +// +//***************************************************************************** +#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address +#define NVIC_FAULT_ADDR_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_EXC_STACK register. +// +//***************************************************************************** +#define NVIC_EXC_STACK_DEEP 0x00000001 // Exception stack + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_EXC_NUM register. +// +//***************************************************************************** +#define NVIC_EXC_NUM_M 0x000003FF // Exception number +#define NVIC_EXC_NUM_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_COPRO register. +// +//***************************************************************************** +#define NVIC_COPRO_15_M 0xC0000000 // Coprocessor 15 access mask +#define NVIC_COPRO_15_DENIED 0x00000000 // Coprocessor 15 access denied +#define NVIC_COPRO_15_PRIV 0x40000000 // Coprocessor 15 privileged addess +#define NVIC_COPRO_15_FULL 0xC0000000 // Coprocessor 15 full access +#define NVIC_COPRO_14_M 0x30000000 // Coprocessor 14 access mask +#define NVIC_COPRO_14_DENIED 0x00000000 // Coprocessor 14 access denied +#define NVIC_COPRO_14_PRIV 0x10000000 // Coprocessor 14 privileged addess +#define NVIC_COPRO_14_FULL 0x30000000 // Coprocessor 14 full access +#define NVIC_COPRO_13_M 0x0C000000 // Coprocessor 13 access mask +#define NVIC_COPRO_13_DENIED 0x00000000 // Coprocessor 13 access denied +#define NVIC_COPRO_13_PRIV 0x04000000 // Coprocessor 13 privileged addess +#define NVIC_COPRO_13_FULL 0x0C000000 // Coprocessor 13 full access +#define NVIC_COPRO_12_M 0x03000000 // Coprocessor 12 access mask +#define NVIC_COPRO_12_DENIED 0x00000000 // Coprocessor 12 access denied +#define NVIC_COPRO_12_PRIV 0x01000000 // Coprocessor 12 privileged addess +#define NVIC_COPRO_12_FULL 0x03000000 // Coprocessor 12 full access +#define NVIC_COPRO_11_M 0x00C00000 // Coprocessor 11 access mask +#define NVIC_COPRO_11_DENIED 0x00000000 // Coprocessor 11 access denied +#define NVIC_COPRO_11_PRIV 0x00400000 // Coprocessor 11 privileged addess +#define NVIC_COPRO_11_FULL 0x00C00000 // Coprocessor 11 full access +#define NVIC_COPRO_10_M 0x00300000 // Coprocessor 10 access mask +#define NVIC_COPRO_10_DENIED 0x00000000 // Coprocessor 10 access denied +#define NVIC_COPRO_10_PRIV 0x00100000 // Coprocessor 10 privileged addess +#define NVIC_COPRO_10_FULL 0x00300000 // Coprocessor 10 full access +#define NVIC_COPRO_9_M 0x000C0000 // Coprocessor 9 access mask +#define NVIC_COPRO_9_DENIED 0x00000000 // Coprocessor 9 access denied +#define NVIC_COPRO_9_PRIV 0x00040000 // Coprocessor 9 privileged addess +#define NVIC_COPRO_9_FULL 0x000C0000 // Coprocessor 9 full access +#define NVIC_COPRO_8_M 0x00030000 // Coprocessor 8 access mask +#define NVIC_COPRO_8_DENIED 0x00000000 // Coprocessor 8 access denied +#define NVIC_COPRO_8_PRIV 0x00010000 // Coprocessor 8 privileged addess +#define NVIC_COPRO_8_FULL 0x00030000 // Coprocessor 8 full access +#define NVIC_COPRO_7_M 0x0000C000 // Coprocessor 7 access mask +#define NVIC_COPRO_7_DENIED 0x00000000 // Coprocessor 7 access denied +#define NVIC_COPRO_7_PRIV 0x00004000 // Coprocessor 7 privileged addess +#define NVIC_COPRO_7_FULL 0x0000C000 // Coprocessor 7 full access +#define NVIC_COPRO_6_M 0x00003000 // Coprocessor 6 access mask +#define NVIC_COPRO_6_DENIED 0x00000000 // Coprocessor 6 access denied +#define NVIC_COPRO_6_PRIV 0x00001000 // Coprocessor 6 privileged addess +#define NVIC_COPRO_6_FULL 0x00003000 // Coprocessor 6 full access +#define NVIC_COPRO_5_M 0x00000C00 // Coprocessor 5 access mask +#define NVIC_COPRO_5_DENIED 0x00000000 // Coprocessor 5 access denied +#define NVIC_COPRO_5_PRIV 0x00000400 // Coprocessor 5 privileged addess +#define NVIC_COPRO_5_FULL 0x00000C00 // Coprocessor 5 full access +#define NVIC_COPRO_4_M 0x00000300 // Coprocessor 4 access mask +#define NVIC_COPRO_4_DENIED 0x00000000 // Coprocessor 4 access denied +#define NVIC_COPRO_4_PRIV 0x00000100 // Coprocessor 4 privileged addess +#define NVIC_COPRO_4_FULL 0x00000300 // Coprocessor 4 full access +#define NVIC_COPRO_3_M 0x000000C0 // Coprocessor 3 access mask +#define NVIC_COPRO_3_DENIED 0x00000000 // Coprocessor 3 access denied +#define NVIC_COPRO_3_PRIV 0x00000040 // Coprocessor 3 privileged addess +#define NVIC_COPRO_3_FULL 0x000000C0 // Coprocessor 3 full access +#define NVIC_COPRO_2_M 0x00000030 // Coprocessor 2 access mask +#define NVIC_COPRO_2_DENIED 0x00000000 // Coprocessor 2 access denied +#define NVIC_COPRO_2_PRIV 0x00000010 // Coprocessor 2 privileged addess +#define NVIC_COPRO_2_FULL 0x00000030 // Coprocessor 2 full access +#define NVIC_COPRO_1_M 0x0000000C // Coprocessor 1 access mask +#define NVIC_COPRO_1_DENIED 0x00000000 // Coprocessor 1 access denied +#define NVIC_COPRO_1_PRIV 0x00000004 // Coprocessor 1 privileged addess +#define NVIC_COPRO_1_FULL 0x0000000C // Coprocessor 1 full access +#define NVIC_COPRO_0_M 0x00000003 // Coprocessor 0 access mask +#define NVIC_COPRO_0_DENIED 0x00000000 // Coprocessor 0 access denied +#define NVIC_COPRO_0_PRIV 0x00000001 // Coprocessor 0 privileged addess +#define NVIC_COPRO_0_FULL 0x00000003 // Coprocessor 0 full access + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_TYPE register. +// +//***************************************************************************** +#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions +#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions +#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU +#define NVIC_MPU_TYPE_IREGION_S 16 +#define NVIC_MPU_TYPE_DREGION_S 8 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_CTRL register. +// +//***************************************************************************** +#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults +#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_NUMBER register. +// +//***************************************************************************** +#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access +#define NVIC_MPU_NUMBER_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_BASE register. +// +//***************************************************************************** +#define NVIC_MPU_BASE_ADDR_M 0xFFFFFF00 // Base address +#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid +#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number +#define NVIC_MPU_BASE_ADDR_S 8 +#define NVIC_MPU_BASE_REGION_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_MPU_ATTR register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR_ATTRS 0xFFFF0000 // Attributes +#define NVIC_MPU_ATTR_SRD 0x0000FF00 // Sub-region disable +#define NVIC_MPU_ATTR_SZENABLE 0x000000FF // Region size + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_CTRL register. +// +//***************************************************************************** +#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask +#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key +#define NVIC_DBG_CTRL_MON_PEND 0x00008000 // Pend the monitor +#define NVIC_DBG_CTRL_MON_REQ 0x00004000 // Monitor request +#define NVIC_DBG_CTRL_MON_EN 0x00002000 // Debug monitor enable +#define NVIC_DBG_CTRL_MONSTEP 0x00001000 // Monitor step the core +#define NVIC_DBG_CTRL_S_SLEEP 0x00000400 // Core is sleeping +#define NVIC_DBG_CTRL_S_HALT 0x00000200 // Core status on halt +#define NVIC_DBG_CTRL_S_REGRDY 0x00000100 // Register read/write available +#define NVIC_DBG_CTRL_S_LOCKUP 0x00000080 // Core is locked up +#define NVIC_DBG_CTRL_C_RESET 0x00000010 // Reset the core +#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping +#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core +#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core +#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_XFER register. +// +//***************************************************************************** +#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read +#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register +#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 +#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 +#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 +#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 +#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 +#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 +#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 +#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 +#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 +#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 +#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 +#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 +#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 +#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 +#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 +#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 +#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register +#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP +#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP +#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP +#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_DATA register. +// +//***************************************************************************** +#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache +#define NVIC_DBG_DATA_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_DBG_INT register. +// +//***************************************************************************** +#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault +#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors +#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error +#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state +#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check +#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error +#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault +#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status +#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset +#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending +#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch + +//***************************************************************************** +// +// The following define the bit fields in the NVIC_SW_TRIG register. +// +//***************************************************************************** +#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger +#define NVIC_SW_TRIG_INTID_S 0 + +#endif // __HW_NVIC_H__ diff --git a/20080212/Demo/Common/drivers/LuminaryMicro/hw_pwm.h b/20080212/Demo/Common/drivers/LuminaryMicro/hw_pwm.h new file mode 100644 index 000000000..6f670c108 --- /dev/null +++ b/20080212/Demo/Common/drivers/LuminaryMicro/hw_pwm.h @@ -0,0 +1,260 @@ +//***************************************************************************** +// +// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports +// +// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1582 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __HW_PWM_H__ +#define __HW_PWM_H__ + +//***************************************************************************** +// +// PWM Module Register Offsets. +// +//***************************************************************************** +#define PWM_O_CTL 0x00000000 // PWM Master Control register +#define PWM_O_SYNC 0x00000004 // PWM Time Base Sync register +#define PWM_O_ENABLE 0x00000008 // PWM Output Enable register +#define PWM_O_INVERT 0x0000000C // PWM Output Inversion register +#define PWM_O_FAULT 0x00000010 // PWM Output Fault register +#define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable register +#define PWM_O_RIS 0x00000018 // PWM Interrupt Raw Status reg. +#define PWM_O_ISC 0x0000001C // PWM Interrupt Status register +#define PWM_O_STATUS 0x00000020 // PWM Status register + +//***************************************************************************** +// +// The following define the bit fields in the PWM Master Control register. +// +//***************************************************************************** +#define PWM_CTL_GLOBAL_SYNC2 0x00000004 // Global sync generator 2 +#define PWM_CTL_GLOBAL_SYNC1 0x00000002 // Global sync generator 1 +#define PWM_CTL_GLOBAL_SYNC0 0x00000001 // Global sync generator 0 + +//***************************************************************************** +// +// The following define the bit fields in the PWM Time Base Sync register. +// +//***************************************************************************** +#define PWM_SYNC_SYNC2 0x00000004 // Reset generator 2 counter +#define PWM_SYNC_SYNC1 0x00000002 // Reset generator 1 counter +#define PWM_SYNC_SYNC0 0x00000001 // Reset generator 0 counter + +//***************************************************************************** +// +// The following define the bit fields in the PWM Output Enable register. +// +//***************************************************************************** +#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 pin enable +#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 pin enable +#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 pin enable +#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 pin enable +#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 pin enable +#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 pin enable + +//***************************************************************************** +// +// The following define the bit fields in the PWM Inversion register. +// +//***************************************************************************** +#define PWM_INVERT_PWM5INV 0x00000020 // PWM5 pin invert +#define PWM_INVERT_PWM4INV 0x00000010 // PWM4 pin invert +#define PWM_INVERT_PWM3INV 0x00000008 // PWM3 pin invert +#define PWM_INVERT_PWM2INV 0x00000004 // PWM2 pin invert +#define PWM_INVERT_PWM1INV 0x00000002 // PWM1 pin invert +#define PWM_INVERT_PWM0INV 0x00000001 // PWM0 pin invert + +//***************************************************************************** +// +// The following define the bit fields in the PWM Fault register. +// +//***************************************************************************** +#define PWM_FAULT_FAULT5 0x00000020 // PWM5 pin fault +#define PWM_FAULT_FAULT4 0x00000010 // PWM5 pin fault +#define PWM_FAULT_FAULT3 0x00000008 // PWM5 pin fault +#define PWM_FAULT_FAULT2 0x00000004 // PWM5 pin fault +#define PWM_FAULT_FAULT1 0x00000002 // PWM5 pin fault +#define PWM_FAULT_FAULT0 0x00000001 // PWM5 pin fault + +//***************************************************************************** +// +// PWM Interrupt Register bit definitions. +// +//***************************************************************************** +#define PWM_INT_INTFAULT 0x00010000 // Fault interrupt pending + +//***************************************************************************** +// +// The following define the bit fields in the PWM Status register. +// +//***************************************************************************** +#define PWM_STATUS_FAULT 0x00000001 // Fault status + +//***************************************************************************** +// +// PWM Generator standard offsets. +// +//***************************************************************************** +#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base +#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base +#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base + +#define PWM_O_X_CTL 0x00000000 // Gen Control Reg +#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg +#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg +#define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg +#define PWM_O_X_LOAD 0x00000010 // Gen Load Reg +#define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg +#define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg +#define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg +#define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg +#define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg +#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg +#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg +#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg + +//***************************************************************************** +// +// PWM_X Control Register bit definitions. +// +//***************************************************************************** +#define PWM_X_CTL_ENABLE 0x00000001 // Master enable for gen block +#define PWM_X_CTL_MODE 0x00000002 // Counter mode, down or up/down +#define PWM_X_CTL_DEBUG 0x00000004 // Debug mode +#define PWM_X_CTL_LOADUPD 0x00000008 // Update mode for the load reg +#define PWM_X_CTL_CMPAUPD 0x00000010 // Update mode for comp A reg +#define PWM_X_CTL_CMPBUPD 0x00000020 // Update mode for comp B reg + +//***************************************************************************** +// +// PWM_X Interrupt/Trigger Enable Register bit definitions. +// +//***************************************************************************** +#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Int if COUNT = 0 +#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Int if COUNT = LOAD +#define PWM_X_INTEN_INTCMPAU 0x00000004 // Int if COUNT = CMPA U +#define PWM_X_INTEN_INTCMPAD 0x00000008 // Int if COUNT = CMPA D +#define PWM_X_INTEN_INTCMPBU 0x00000010 // Int if COUNT = CMPA U +#define PWM_X_INTEN_INTCMPBD 0x00000020 // Int if COUNT = CMPA D +#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trig if COUNT = 0 +#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trig if COUNT = LOAD +#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trig if COUNT = CMPA U +#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trig if COUNT = CMPA D +#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trig if COUNT = CMPA U +#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trig if COUNT = CMPA D + +//***************************************************************************** +// +// PWM_X Raw Interrupt Status Register bit definitions. +// +//***************************************************************************** +#define PWM_X_RIS_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 int +#define PWM_X_RIS_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD int +#define PWM_X_RIS_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U int +#define PWM_X_RIS_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D int +#define PWM_X_RIS_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U int +#define PWM_X_RIS_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D int + +//***************************************************************************** +// +// PWM_X Interrupt Status Register bit definitions. +// +//***************************************************************************** +#define PWM_X_INT_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 received +#define PWM_X_INT_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD rcvd +#define PWM_X_INT_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U rcvd +#define PWM_X_INT_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D rcvd +#define PWM_X_INT_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U rcvd +#define PWM_X_INT_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D rcvd + +//***************************************************************************** +// +// PWM_X Generator A/B Control Register bit definitions. +// +//***************************************************************************** +#define PWM_X_GEN_Y_ACTZERO 0x00000003 // Act PWM_X_COUNT = 0 +#define PWM_X_GEN_Y_ACTLOAD 0x0000000C // Act PWM_X_COUNT = PWM_X_LOAD +#define PWM_X_GEN_Y_ACTCMPAU 0x00000030 // Act PWM_X_COUNT = PWM_X_CMPA U +#define PWM_X_GEN_Y_ACTCMPAD 0x000000C0 // Act PWM_X_COUNT = PWM_X_CMPA D +#define PWM_X_GEN_Y_ACTCMPBU 0x00000300 // Act PWM_X_COUNT = PWM_X_CMPB U +#define PWM_X_GEN_Y_ACTCMPBD 0x00000C00 // Act PWM_X_COUNT = PWM_X_CMPB D + +//***************************************************************************** +// +// PWM_X Generator A/B Control Register action definitions. +// +//***************************************************************************** +#define PWM_GEN_ACT_NONE 0x0 // Do nothing +#define PWM_GEN_ACT_INV 0x1 // Invert the output signal +#define PWM_GEN_ACT_ZERO 0x2 // Set the output signal to zero +#define PWM_GEN_ACT_ONE 0x3 // Set the output signal to one +#define PWM_GEN_ACT_ZERO_SHIFT 0 // Shift amount for the zero action +#define PWM_GEN_ACT_LOAD_SHIFT 2 // Shift amount for the load action +#define PWM_GEN_ACT_A_UP_SHIFT 4 // Shift amount for the A up action +#define PWM_GEN_ACT_A_DN_SHIFT 6 // Shift amount for the A dn action +#define PWM_GEN_ACT_B_UP_SHIFT 8 // Shift amount for the B up action +#define PWM_GEN_ACT_B_DN_SHIFT 10 // Shift amount for the B dn action + +//***************************************************************************** +// +// PWM_X Dead Band Control Register bit definitions. +// +//***************************************************************************** +#define PWM_DBCTL_ENABLE 0x00000001 // Enable dead band insertion + +//***************************************************************************** +// +// PWM Register reset values. +// +//***************************************************************************** +#define PWM_RV_CTL 0x00000000 // Master control of the PWM module +#define PWM_RV_SYNC 0x00000000 // Counter synch for PWM generators +#define PWM_RV_ENABLE 0x00000000 // Master enable for the PWM + // output pins +#define PWM_RV_INVERT 0x00000000 // Inversion control for + // PWM output pins +#define PWM_RV_FAULT 0x00000000 // Fault handling for the PWM + // output pins +#define PWM_RV_INTEN 0x00000000 // Interrupt enable +#define PWM_RV_RIS 0x00000000 // Raw interrupt status +#define PWM_RV_ISC 0x00000000 // Interrupt status and clearing +#define PWM_RV_STATUS 0x00000000 // Status +#define PWM_RV_X_CTL 0x00000000 // Master control of the PWM + // generator block +#define PWM_RV_X_INTEN 0x00000000 // Interrupt and trigger enable +#define PWM_RV_X_RIS 0x00000000 // Raw interrupt status +#define PWM_RV_X_ISC 0x00000000 // Interrupt status and clearing +#define PWM_RV_X_LOAD 0x00000000 // The load value for the counter +#define PWM_RV_X_COUNT 0x00000000 // The current counter value +#define PWM_RV_X_CMPA 0x00000000 // The comparator A value +#define PWM_RV_X_CMPB 0x00000000 // The comparator B value +#define PWM_RV_X_GENA 0x00000000 // Controls PWM generator A +#define PWM_RV_X_GENB 0x00000000 // Controls PWM generator B +#define PWM_RV_X_DBCTL 0x00000000 // Control the dead band generator +#define PWM_RV_X_DBRISE 0x00000000 // The dead band rising edge delay + // count +#define PWM_RV_X_DBFALL 0x00000000 // The dead band falling edge delay + // count + +#endif // __HW_PWM_H__ diff --git a/20080212/Demo/Common/drivers/LuminaryMicro/hw_qei.h b/20080212/Demo/Common/drivers/LuminaryMicro/hw_qei.h new file mode 100644 index 000000000..c06fe0e4d --- /dev/null +++ b/20080212/Demo/Common/drivers/LuminaryMicro/hw_qei.h @@ -0,0 +1,176 @@ +//***************************************************************************** +// +// hw_qei.h - Macros used when accessing the QEI hardware. +// +// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1582 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __HW_QEI_H__ +#define __HW_QEI_H__ + +//***************************************************************************** +// +// The following define the offsets of the QEI registers. +// +//***************************************************************************** +#define QEI_O_CTL 0x00000000 // Configuration and control reg. +#define QEI_O_STAT 0x00000004 // Status register +#define QEI_O_POS 0x00000008 // Current position register +#define QEI_O_MAXPOS 0x0000000C // Maximum position register +#define QEI_O_LOAD 0x00000010 // Velocity timer load register +#define QEI_O_TIME 0x00000014 // Velocity timer register +#define QEI_O_COUNT 0x00000018 // Velocity pulse count register +#define QEI_O_SPEED 0x0000001C // Velocity speed register +#define QEI_O_INTEN 0x00000020 // Interrupt enable register +#define QEI_O_RIS 0x00000024 // Raw interrupt status register +#define QEI_O_ISC 0x00000028 // Interrupt status register + +//***************************************************************************** +// +// The following define the bit fields in the QEI_CTL register. +// +//***************************************************************************** +#define QEI_CTL_STALLEN 0x00001000 // Stall enable +#define QEI_CTL_INVI 0x00000800 // Invert Index input +#define QEI_CTL_INVB 0x00000400 // Invert PhB input +#define QEI_CTL_INVA 0x00000200 // Invert PhA input +#define QEI_CTL_VELDIV_M 0x000001C0 // Velocity predivider mask +#define QEI_CTL_VELDIV_1 0x00000000 // Predivide by 1 +#define QEI_CTL_VELDIV_2 0x00000040 // Predivide by 2 +#define QEI_CTL_VELDIV_4 0x00000080 // Predivide by 4 +#define QEI_CTL_VELDIV_8 0x000000C0 // Predivide by 8 +#define QEI_CTL_VELDIV_16 0x00000100 // Predivide by 16 +#define QEI_CTL_VELDIV_32 0x00000140 // Predivide by 32 +#define QEI_CTL_VELDIV_64 0x00000180 // Predivide by 64 +#define QEI_CTL_VELDIV_128 0x000001C0 // Predivide by 128 +#define QEI_CTL_VELEN 0x00000020 // Velocity enable +#define QEI_CTL_RESMODE 0x00000010 // Position counter reset mode +#define QEI_CTL_CAPMODE 0x00000008 // Edge capture mode +#define QEI_CTL_SIGMODE 0x00000004 // Encoder signaling mode +#define QEI_CTL_SWAP 0x00000002 // Swap input signals +#define QEI_CTL_ENABLE 0x00000001 // QEI enable + +//***************************************************************************** +// +// The following define the bit fields in the QEI_STAT register. +// +//***************************************************************************** +#define QEI_STAT_DIRECTION 0x00000002 // Direction of rotation +#define QEI_STAT_ERROR 0x00000001 // Signalling error detected + +//***************************************************************************** +// +// The following define the bit fields in the QEI_POS register. +// +//***************************************************************************** +#define QEI_POS_M 0xFFFFFFFF // Current encoder position +#define QEI_POS_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the QEI_MAXPOS register. +// +//***************************************************************************** +#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum encoder position +#define QEI_MAXPOS_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the QEI_LOAD register. +// +//***************************************************************************** +#define QEI_LOAD_M 0xFFFFFFFF // Velocity timer load value +#define QEI_LOAD_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the QEI_TIME register. +// +//***************************************************************************** +#define QEI_TIME_M 0xFFFFFFFF // Velocity timer current value +#define QEI_TIME_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the QEI_COUNT register. +// +//***************************************************************************** +#define QEI_COUNT_M 0xFFFFFFFF // Encoder running pulse count +#define QEI_COUNT_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the QEI_SPEED register. +// +//***************************************************************************** +#define QEI_SPEED_M 0xFFFFFFFF // Encoder pulse count +#define QEI_SPEED_S 0 + +//***************************************************************************** +// +// The following define the bit fields in the QEI_INTEN register. +// +//***************************************************************************** +#define QEI_INTEN_ERROR 0x00000008 // Phase error detected +#define QEI_INTEN_DIR 0x00000004 // Direction change +#define QEI_INTEN_TIMER 0x00000002 // Velocity timer expired +#define QEI_INTEN_INDEX 0x00000001 // Index pulse detected + +//***************************************************************************** +// +// The following define the bit fields in the QEI_RIS register. +// +//***************************************************************************** +#define QEI_RIS_ERROR 0x00000008 // Phase error detected +#define QEI_RIS_DIR 0x00000004 // Direction change +#define QEI_RIS_TIMER 0x00000002 // Velocity timer expired +#define QEI_RIS_INDEX 0x00000001 // Index pulse detected + +//***************************************************************************** +// +// The following define the bit fields in the QEI_ISC register. +// +//***************************************************************************** +#define QEI_INT_ERROR 0x00000008 // Phase error detected +#define QEI_INT_DIR 0x00000004 // Direction change +#define QEI_INT_TIMER 0x00000002 // Velocity timer expired +#define QEI_INT_INDEX 0x00000001 // Index pulse detected + +//***************************************************************************** +// +// The following define the reset values for the QEI registers. +// +//***************************************************************************** +#define QEI_RV_CTL 0x00000000 // Configuration and control reg. +#define QEI_RV_STAT 0x00000000 // Status register +#define QEI_RV_POS 0x00000000 // Current position register +#define QEI_RV_MAXPOS 0x00000000 // Maximum position register +#define QEI_RV_LOAD 0x00000000 // Velocity timer load register +#define QEI_RV_TIME 0x00000000 // Velocity timer register +#define QEI_RV_COUNT 0x00000000 // Velocity pulse count register +#define QEI_RV_SPEED 0x00000000 // Velocity speed register +#define QEI_RV_INTEN 0x00000000 // Interrupt enable register +#define QEI_RV_RIS 0x00000000 // Raw interrupt status register +#define QEI_RV_ISC 0x00000000 // Interrupt status register + +#endif // __HW_QEI_H__ diff --git a/20080212/Demo/Common/drivers/LuminaryMicro/hw_ssi.h b/20080212/Demo/Common/drivers/LuminaryMicro/hw_ssi.h new file mode 100644 index 000000000..b12c2c4f4 --- /dev/null +++ b/20080212/Demo/Common/drivers/LuminaryMicro/hw_ssi.h @@ -0,0 +1,120 @@ +//***************************************************************************** +// +// hw_ssi.h - Macros used when accessing the SSI hardware. +// +// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1582 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __HW_SSI_H__ +#define __HW_SSI_H__ + +//***************************************************************************** +// +// The following define the offsets of the SSI registers. +// +//***************************************************************************** +#define SSI_O_CR0 0x00000000 // Control register 0 +#define SSI_O_CR1 0x00000004 // Control register 1 +#define SSI_O_DR 0x00000008 // Data register +#define SSI_O_SR 0x0000000C // Status register +#define SSI_O_CPSR 0x00000010 // Clock prescale register +#define SSI_O_IM 0x00000014 // Int mask set and clear register +#define SSI_O_RIS 0x00000018 // Raw interrupt register +#define SSI_O_MIS 0x0000001C // Masked interrupt register +#define SSI_O_ICR 0x00000020 // Interrupt clear register + +//***************************************************************************** +// +// The following define the bit fields in the SSI Control register 0. +// +//***************************************************************************** +#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate +#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase +#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity +#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask +#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format +#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format +#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format +#define SSI_CR0_DSS 0x0000000F // Data size select +#define SSI_CR0_DSS_4 0x00000003 // 4 bit data +#define SSI_CR0_DSS_5 0x00000004 // 5 bit data +#define SSI_CR0_DSS_6 0x00000005 // 6 bit data +#define SSI_CR0_DSS_7 0x00000006 // 7 bit data +#define SSI_CR0_DSS_8 0x00000007 // 8 bit data +#define SSI_CR0_DSS_9 0x00000008 // 9 bit data +#define SSI_CR0_DSS_10 0x00000009 // 10 bit data +#define SSI_CR0_DSS_11 0x0000000A // 11 bit data +#define SSI_CR0_DSS_12 0x0000000B // 12 bit data +#define SSI_CR0_DSS_13 0x0000000C // 13 bit data +#define SSI_CR0_DSS_14 0x0000000D // 14 bit data +#define SSI_CR0_DSS_15 0x0000000E // 15 bit data +#define SSI_CR0_DSS_16 0x0000000F // 16 bit data + +//***************************************************************************** +// +// The following define the bit fields in the SSI Control register 1. +// +//***************************************************************************** +#define SSI_CR1_SOD 0x00000008 // Slave mode output disable +#define SSI_CR1_MS 0x00000004 // Master or slave mode select +#define SSI_CR1_SSE 0x00000002 // Sync serial port enable +#define SSI_CR1_LBM 0x00000001 // Loopback mode + +//***************************************************************************** +// +// The following define the bit fields in the SSI Status register. +// +//***************************************************************************** +#define SSI_SR_BSY 0x00000010 // SSI busy +#define SSI_SR_RFF 0x00000008 // RX FIFO full +#define SSI_SR_RNE 0x00000004 // RX FIFO not empty +#define SSI_SR_TNF 0x00000002 // TX FIFO not full +#define SSI_SR_TFE 0x00000001 // TX FIFO empty + +//***************************************************************************** +// +// The following define the bit fields in the SSI clock prescale register. +// +//***************************************************************************** +#define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale + +//***************************************************************************** +// +// The following define information concerning the SSI Data register. +// +//***************************************************************************** +#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO +#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO + +//***************************************************************************** +// +// The following define the bit fields in the interrupt mask set and clear, +// raw interrupt, masked interrupt, and interrupt clear registers. +// +//***************************************************************************** +#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt +#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt +#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt +#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt + +#endif // __HW_SSI_H__ diff --git a/20080212/Demo/Common/drivers/LuminaryMicro/hw_sysctl.h b/20080212/Demo/Common/drivers/LuminaryMicro/hw_sysctl.h new file mode 100644 index 000000000..f540e63a4 --- /dev/null +++ b/20080212/Demo/Common/drivers/LuminaryMicro/hw_sysctl.h @@ -0,0 +1,703 @@ +//***************************************************************************** +// +// hw_sysctl.h - Macros used when accessing the system control hardware. +// +// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1582 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __HW_SYSCTL_H__ +#define __HW_SYSCTL_H__ + +//***************************************************************************** +// +// The following define the addresses of the system control registers. +// +//***************************************************************************** +#define SYSCTL_DID0 0x400fe000 // Device identification register 0 +#define SYSCTL_DID1 0x400fe004 // Device identification register 1 +#define SYSCTL_DC0 0x400fe008 // Device capabilities register 0 +#define SYSCTL_DC1 0x400fe010 // Device capabilities register 1 +#define SYSCTL_DC2 0x400fe014 // Device capabilities register 2 +#define SYSCTL_DC3 0x400fe018 // Device capabilities register 3 +#define SYSCTL_DC4 0x400fe01C // Device capabilities register 4 +#define SYSCTL_PBORCTL 0x400fe030 // POR/BOR reset control register +#define SYSCTL_LDOPCTL 0x400fe034 // LDO power control register +#define SYSCTL_SRCR0 0x400fe040 // Software reset control reg 0 +#define SYSCTL_SRCR1 0x400fe044 // Software reset control reg 1 +#define SYSCTL_SRCR2 0x400fe048 // Software reset control reg 2 +#define SYSCTL_RIS 0x400fe050 // Raw interrupt status register +#define SYSCTL_IMC 0x400fe054 // Interrupt mask/control register +#define SYSCTL_MISC 0x400fe058 // Interrupt status register +#define SYSCTL_RESC 0x400fe05c // Reset cause register +#define SYSCTL_RCC 0x400fe060 // Run-mode clock config register +#define SYSCTL_PLLCFG 0x400fe064 // PLL configuration register +#define SYSCTL_RCC2 0x400fe070 // Run-mode clock config register 2 +#define SYSCTL_RCGC0 0x400fe100 // Run-mode clock gating register 0 +#define SYSCTL_RCGC1 0x400fe104 // Run-mode clock gating register 1 +#define SYSCTL_RCGC2 0x400fe108 // Run-mode clock gating register 2 +#define SYSCTL_SCGC0 0x400fe110 // Sleep-mode clock gating reg 0 +#define SYSCTL_SCGC1 0x400fe114 // Sleep-mode clock gating reg 1 +#define SYSCTL_SCGC2 0x400fe118 // Sleep-mode clock gating reg 2 +#define SYSCTL_DCGC0 0x400fe120 // Deep Sleep-mode clock gate reg 0 +#define SYSCTL_DCGC1 0x400fe124 // Deep Sleep-mode clock gate reg 1 +#define SYSCTL_DCGC2 0x400fe128 // Deep Sleep-mode clock gate reg 2 +#define SYSCTL_DSLPCLKCFG 0x400fe144 // Deep Sleep-mode clock config reg +#define SYSCTL_CLKVCLR 0x400fe150 // Clock verifcation clear register +#define SYSCTL_LDOARST 0x400fe160 // LDO reset control register +#define SYSCTL_USER0 0x400fe1e0 // NV User Register 0 +#define SYSCTL_USER1 0x400fe1e4 // NV User Register 1 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DID0 register. +// +//***************************************************************************** +#define SYSCTL_DID0_VER_MASK 0x70000000 // DID0 version mask +#define SYSCTL_DID0_VER_0 0x00000000 // DID0 version 0 +#define SYSCTL_DID0_VER_1 0x10000000 // DID0 version 1 +#define SYSCTL_DID0_CLASS_MASK 0x00FF0000 // Device Class +#define SYSCTL_DID0_CLASS_SANDSTORM 0x00000000 // Sandstorm-class Device +#define SYSCTL_DID0_CLASS_FURY 0x00010000 // Fury-class Device +#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask +#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A +#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B +#define SYSCTL_DID0_MAJ_C 0x00000200 // Major revision C +#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask +#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0 +#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1 +#define SYSCTL_DID0_MIN_2 0x00000002 // Minor revision 2 +#define SYSCTL_DID0_MIN_3 0x00000003 // Minor revision 3 +#define SYSCTL_DID0_MIN_4 0x00000004 // Minor revision 4 +#define SYSCTL_DID0_MIN_5 0x00000005 // Minor revision 5 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DID1 register. +// +//***************************************************************************** +#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask +#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask +#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family +#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask +#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101 +#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102 +#define SYSCTL_DID1_PRTNO_301 0x00110000 // LM3S301 +#define SYSCTL_DID1_PRTNO_310 0x00120000 // LM3S310 +#define SYSCTL_DID1_PRTNO_315 0x00130000 // LM3S315 +#define SYSCTL_DID1_PRTNO_316 0x00140000 // LM3S316 +#define SYSCTL_DID1_PRTNO_317 0x00170000 // LM3S317 +#define SYSCTL_DID1_PRTNO_328 0x00150000 // LM3S328 +#define SYSCTL_DID1_PRTNO_601 0x00210000 // LM3S601 +#define SYSCTL_DID1_PRTNO_610 0x00220000 // LM3S610 +#define SYSCTL_DID1_PRTNO_611 0x00230000 // LM3S611 +#define SYSCTL_DID1_PRTNO_612 0x00240000 // LM3S612 +#define SYSCTL_DID1_PRTNO_613 0x00250000 // LM3S613 +#define SYSCTL_DID1_PRTNO_615 0x00260000 // LM3S615 +#define SYSCTL_DID1_PRTNO_617 0x00280000 // LM3S617 +#define SYSCTL_DID1_PRTNO_618 0x00290000 // LM3S618 +#define SYSCTL_DID1_PRTNO_628 0x00270000 // LM3S628 +#define SYSCTL_DID1_PRTNO_801 0x00310000 // LM3S801 +#define SYSCTL_DID1_PRTNO_811 0x00320000 // LM3S811 +#define SYSCTL_DID1_PRTNO_812 0x00330000 // LM3S812 +#define SYSCTL_DID1_PRTNO_815 0x00340000 // LM3S815 +#define SYSCTL_DID1_PRTNO_817 0x00360000 // LM3S817 +#define SYSCTL_DID1_PRTNO_818 0x00370000 // LM3S818 +#define SYSCTL_DID1_PRTNO_828 0x00350000 // LM3S828 +#define SYSCTL_DID1_PRTNO_1110 0x00BF0000 // LM3S1110 +#define SYSCTL_DID1_PRTNO_1133 0x00C30000 // LM3S1133 +#define SYSCTL_DID1_PRTNO_1138 0x00C50000 // LM3S1138 +#define SYSCTL_DID1_PRTNO_1150 0x00C10000 // LM3S1150 +#define SYSCTL_DID1_PRTNO_1162 0x00C40000 // LM3S1162 +#define SYSCTL_DID1_PRTNO_1165 0x00C20000 // LM3S1165 +#define SYSCTL_DID1_PRTNO_1332 0x00C60000 // LM3S1332 +#define SYSCTL_DID1_PRTNO_1435 0x00BC0000 // LM3S1435 +#define SYSCTL_DID1_PRTNO_1439 0x00BA0000 // LM3S1439 +#define SYSCTL_DID1_PRTNO_1512 0x00BB0000 // LM3S1512 +#define SYSCTL_DID1_PRTNO_1538 0x00C70000 // LM3S1538 +#define SYSCTL_DID1_PRTNO_1620 0x00C00000 // LM3S1620 +#define SYSCTL_DID1_PRTNO_1635 0x00B30000 // LM3S1635 +#define SYSCTL_DID1_PRTNO_1637 0x00BD0000 // LM3S1637 +#define SYSCTL_DID1_PRTNO_1751 0x00B90000 // LM3S1751 +#define SYSCTL_DID1_PRTNO_1850 0x00B40000 // LM3S1850 +#define SYSCTL_DID1_PRTNO_1937 0x00B70000 // LM3S1937 +#define SYSCTL_DID1_PRTNO_1958 0x00BE0000 // LM3S1958 +#define SYSCTL_DID1_PRTNO_1960 0x00B50000 // LM3S1960 +#define SYSCTL_DID1_PRTNO_1968 0x00B80000 // LM3S1968 +#define SYSCTL_DID1_PRTNO_2110 0x00510000 // LM3S2110 +#define SYSCTL_DID1_PRTNO_2139 0x00840000 // LM3S2139 +#define SYSCTL_DID1_PRTNO_2410 0x00A20000 // LM3S2410 +#define SYSCTL_DID1_PRTNO_2412 0x00590000 // LM3S2412 +#define SYSCTL_DID1_PRTNO_2432 0x00560000 // LM3S2432 +#define SYSCTL_DID1_PRTNO_2533 0x005A0000 // LM3S2533 +#define SYSCTL_DID1_PRTNO_2620 0x00570000 // LM3S2620 +#define SYSCTL_DID1_PRTNO_2637 0x00850000 // LM3S2637 +#define SYSCTL_DID1_PRTNO_2651 0x00530000 // LM3S2651 +#define SYSCTL_DID1_PRTNO_2730 0x00A40000 // LM3S2730 +#define SYSCTL_DID1_PRTNO_2739 0x00520000 // LM3S2739 +#define SYSCTL_DID1_PRTNO_2939 0x00540000 // LM3S2939 +#define SYSCTL_DID1_PRTNO_2948 0x008F0000 // LM3S2948 +#define SYSCTL_DID1_PRTNO_2950 0x00580000 // LM3S2950 +#define SYSCTL_DID1_PRTNO_2965 0x00550000 // LM3S2965 +#define SYSCTL_DID1_PRTNO_6100 0x00A10000 // LM3S6100 +#define SYSCTL_DID1_PRTNO_6110 0x00740000 // LM3S6110 +#define SYSCTL_DID1_PRTNO_6420 0x00A50000 // LM3S6420 +#define SYSCTL_DID1_PRTNO_6422 0x00820000 // LM3S6422 +#define SYSCTL_DID1_PRTNO_6432 0x00750000 // LM3S6432 +#define SYSCTL_DID1_PRTNO_6537 0x00760000 // LM3S6537 +#define SYSCTL_DID1_PRTNO_6610 0x00710000 // LM3S6610 +#define SYSCTL_DID1_PRTNO_6633 0x00830000 // LM3S6633 +#define SYSCTL_DID1_PRTNO_6637 0x008B0000 // LM3S6637 +#define SYSCTL_DID1_PRTNO_6730 0x00A30000 // LM3S6730 +#define SYSCTL_DID1_PRTNO_6753 0x00770000 // LM3S6753 +#define SYSCTL_DID1_PRTNO_6938 0x00890000 // LM3S6938 +#define SYSCTL_DID1_PRTNO_6950 0x00720000 // LM3S6950 +#define SYSCTL_DID1_PRTNO_6952 0x00780000 // LM3S6952 +#define SYSCTL_DID1_PRTNO_6965 0x00730000 // LM3S6965 +#define SYSCTL_DID1_PRTNO_8530 0x00640000 // LM3S8530 +#define SYSCTL_DID1_PRTNO_8538 0x008E0000 // LM3S8538 +#define SYSCTL_DID1_PRTNO_8630 0x00610000 // LM3S8630 +#define SYSCTL_DID1_PRTNO_8730 0x00630000 // LM3S8730 +#define SYSCTL_DID1_PRTNO_8733 0x008D0000 // LM3S8733 +#define SYSCTL_DID1_PRTNO_8738 0x00860000 // LM3S8738 +#define SYSCTL_DID1_PRTNO_8930 0x00650000 // LM3S8930 +#define SYSCTL_DID1_PRTNO_8933 0x008C0000 // LM3S8933 +#define SYSCTL_DID1_PRTNO_8938 0x00880000 // LM3S8938 +#define SYSCTL_DID1_PRTNO_8962 0x00A60000 // LM3S8962 +#define SYSCTL_DID1_PRTNO_8970 0x00620000 // LM3S8970 +#define SYSCTL_DID1_PINCNT_MASK 0x0000E000 // Pin count +#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100 pin package +#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask +#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C) +#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C) +#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask +#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC +#define SYSCTL_DID1_PKG_48QFP 0x00000008 // 48-pin QFP +#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant +#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask +#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified) +#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified) +#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified +#define SYSCTL_DID1_PRTNO_SHIFT 16 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC0 register. +// +//***************************************************************************** +#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask +#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_16KB 0x003F0000 // 16 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 // 32 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_64KB 0x00FF0000 // 64 KB of SRAM +#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask +#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8 KB of flash +#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16 KB of flash +#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32 KB of flash +#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64 KB of flash +#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F // 96 KB of flash +#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F // 128 KB of flash +#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of flash + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC1 register. +// +//***************************************************************************** +#define SYSCTL_DC1_CAN2 0x04000000 // CAN2 module present +#define SYSCTL_DC1_CAN1 0x02000000 // CAN1 module present +#define SYSCTL_DC1_CAN0 0x01000000 // CAN0 module present +#define SYSCTL_DC1_PWM 0x00100000 // PWM module present +#define SYSCTL_DC1_ADC 0x00010000 // ADC module present +#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask +#define SYSCTL_DC1_ADCSPD_MASK 0x00000F00 // ADC speed mask +#define SYSCTL_DC1_ADCSPD_1M 0x00000300 // 1Msps ADC +#define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500Ksps ADC +#define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250Ksps ADC +#define SYSCTL_DC1_ADCSPD_125K 0x00000000 // 125Ksps ADC +#define SYSCTL_DC1_MPU 0x00000080 // Cortex M3 MPU present +#define SYSCTL_DC1_HIB 0x00000040 // Hibernation module present +#define SYSCTL_DC1_TEMP 0x00000020 // Temperature sensor present +#define SYSCTL_DC1_PLL 0x00000010 // PLL present +#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present +#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present +#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present +#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC2 register. +// +//***************************************************************************** +#define SYSCTL_DC2_COMP2 0x04000000 // Analog comparator 2 present +#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present +#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present +#define SYSCTL_DC2_TIMER3 0x00080000 // Timer 3 present +#define SYSCTL_DC2_TIMER2 0x00040000 // Timer 2 present +#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present +#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present +#define SYSCTL_DC2_I2C1 0x00004000 // I2C 1 present +#define SYSCTL_DC2_I2C0 0x00001000 // I2C 0 present +#ifndef DEPRECATED +#define SYSCTL_DC2_I2C 0x00001000 // I2C present +#endif +#define SYSCTL_DC2_QEI1 0x00000200 // QEI 1 present +#define SYSCTL_DC2_QEI0 0x00000100 // QEI 0 present +#ifndef DEPRECATED +#define SYSCTL_DC2_QEI 0x00000100 // QEI present +#endif +#define SYSCTL_DC2_SSI1 0x00000020 // SSI 1 present +#define SYSCTL_DC2_SSI0 0x00000010 // SSI 0 present +#ifndef DEPRECATED +#define SYSCTL_DC2_SSI 0x00000010 // SSI present +#endif +#define SYSCTL_DC2_UART2 0x00000004 // UART 2 present +#define SYSCTL_DC2_UART1 0x00000002 // UART 1 present +#define SYSCTL_DC2_UART0 0x00000001 // UART 0 present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC3 register. +// +//***************************************************************************** +#define SYSCTL_DC3_32KHZ 0x80000000 // 32kHz pin present +#define SYSCTL_DC3_CCP5 0x20000000 // CCP5 pin present +#define SYSCTL_DC3_CCP4 0x10000000 // CCP4 pin present +#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 pin present +#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 pin present +#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present +#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present +#define SYSCTL_DC3_ADC7 0x00800000 // ADC7 pin present +#define SYSCTL_DC3_ADC6 0x00400000 // ADC6 pin present +#define SYSCTL_DC3_ADC5 0x00200000 // ADC5 pin present +#define SYSCTL_DC3_ADC4 0x00100000 // ADC4 pin present +#define SYSCTL_DC3_ADC3 0x00080000 // ADC3 pin present +#define SYSCTL_DC3_ADC2 0x00040000 // ADC2 pin present +#define SYSCTL_DC3_ADC1 0x00020000 // ADC1 pin present +#define SYSCTL_DC3_ADC0 0x00010000 // ADC0 pin present +#define SYSCTL_DC3_MC_FAULT0 0x00008000 // MC0 fault pin present +#define SYSCTL_DC3_C2O 0x00004000 // C2o pin present +#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ pin present +#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- pin present +#define SYSCTL_DC3_C1O 0x00000800 // C1o pin present +#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ pin present +#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present +#define SYSCTL_DC3_C0O 0x00000100 // C0o pin present +#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present +#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present +#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 pin present +#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 pin present +#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 pin present +#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 pin present +#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 pin present +#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 pin present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DC4 register. +// +//***************************************************************************** +#define SYSCTL_DC4_ETH 0x50000000 // Ethernet present +#define SYSCTL_DC4_GPIOH 0x00000080 // GPIO port H present +#define SYSCTL_DC4_GPIOG 0x00000040 // GPIO port G present +#define SYSCTL_DC4_GPIOF 0x00000020 // GPIO port F present +#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO port E present +#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO port D present +#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present +#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present +#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_PBORCTL register. +// +//***************************************************************************** +#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer +#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset +#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise +#define SYSCTL_PBORCTL_BOR_SH 2 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_LDOPCTL register. +// +//***************************************************************************** +#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask +#define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V +#define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V +#define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V +#define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V +#define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V +#define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V +#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V +#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V +#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V +#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V +#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_SRCR0, SYSCTL_RCGC0, +// SYSCTL_SCGC0, and SYSCTL_DCGC0 registers. +// +//***************************************************************************** +#define SYSCTL_SET0_CAN2 0x04000000 // CAN2 module +#define SYSCTL_SET0_CAN1 0x02000000 // CAN1 module +#define SYSCTL_SET0_CAN0 0x01000000 // CAN0 module +#define SYSCTL_SET0_PWM 0x00100000 // PWM module +#define SYSCTL_SET0_ADC 0x00010000 // ADC module +#define SYSCTL_SET0_ADCSPD_MASK 0x00000F00 // ADC speed mask +#define SYSCTL_SET0_ADCSPD_1M 0x00000300 // 1Msps ADC +#define SYSCTL_SET0_ADCSPD_500K 0x00000200 // 500Ksps ADC +#define SYSCTL_SET0_ADCSPD_250K 0x00000100 // 250Ksps ADC +#define SYSCTL_SET0_ADCSPD_125K 0x00000000 // 125Ksps ADC +#define SYSCTL_SET0_HIB 0x00000040 // Hibernation module +#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_SRCR1, SYSCTL_RCGC1, +// SYSCTL_SCGC1, and SYSCTL_DCGC1 registers. +// +//***************************************************************************** +#define SYSCTL_SET1_COMP2 0x04000000 // Analog comparator module 2 +#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1 +#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0 +#define SYSCTL_SET1_TIMER3 0x00080000 // Timer module 3 +#define SYSCTL_SET1_TIMER2 0x00040000 // Timer module 2 +#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1 +#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0 +#define SYSCTL_SET1_I2C1 0x00004000 // I2C module 1 +#define SYSCTL_SET1_I2C0 0x00001000 // I2C module 0 +#ifndef DEPRECATED +#define SYSCTL_SET1_I2C 0x00001000 // I2C module +#endif +#define SYSCTL_SET1_QEI1 0x00000200 // QEI module 1 +#define SYSCTL_SET1_QEI0 0x00000100 // QEI module 0 +#ifndef DEPRECATED +#define SYSCTL_SET1_QEI 0x00000100 // QEI module +#endif +#define SYSCTL_SET1_SSI1 0x00000020 // SSI module 1 +#define SYSCTL_SET1_SSI0 0x00000010 // SSI module 0 +#ifndef DEPRECATED +#define SYSCTL_SET1_SSI 0x00000010 // SSI module +#endif +#define SYSCTL_SET1_UART2 0x00000004 // UART module 2 +#define SYSCTL_SET1_UART1 0x00000002 // UART module 1 +#define SYSCTL_SET1_UART0 0x00000001 // UART module 0 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_SRCR2, SYSCTL_RCGC2, +// SYSCTL_SCGC2, and SYSCTL_DCGC2 registers. +// +//***************************************************************************** +#define SYSCTL_SET2_ETH 0x50000000 // ETH module +#define SYSCTL_SET2_GPIOH 0x00000080 // GPIO H module +#define SYSCTL_SET2_GPIOG 0x00000040 // GPIO G module +#define SYSCTL_SET2_GPIOF 0x00000020 // GPIO F module +#define SYSCTL_SET2_GPIOE 0x00000010 // GPIO E module +#define SYSCTL_SET2_GPIOD 0x00000008 // GPIO D module +#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module +#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module +#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_RIS, SYSCTL_IMC, and +// SYSCTL_IMS registers. +// +//***************************************************************************** +#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt +#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt +#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int +#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int +#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt +#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt +#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_RESC register. +// +//***************************************************************************** +#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset +#define SYSCTL_RESC_SW 0x00000010 // Software reset +#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset +#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset +#define SYSCTL_RESC_POR 0x00000002 // Power on reset +#define SYSCTL_RESC_EXT 0x00000001 // External reset + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_RCC register. +// +//***************************************************************************** +#define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating +#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider +#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2 +#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3 +#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4 +#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5 +#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6 +#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7 +#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8 +#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9 +#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10 +#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11 +#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12 +#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13 +#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14 +#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15 +#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16 +#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider +#define SYSCTL_RCC_USE_PWMDIV 0x00100000 // Use PWM clock divider +#define SYSCTL_RCC_PWMDIV_MASK 0x000E0000 // PWM clock divider +#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2 +#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4 +#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8 +#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16 +#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32 +#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64 +#define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down +#define SYSCTL_RCC_OE 0x00001000 // PLL output enable +#define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass +#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable +#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc +#define SYSCTL_RCC_XTAL_1MHZ 0x00000000 // Using a 1MHz crystal +#define SYSCTL_RCC_XTAL_1_84MHZ 0x00000040 // Using a 1.8432MHz crystal +#define SYSCTL_RCC_XTAL_2MHZ 0x00000080 // Using a 2MHz crystal +#define SYSCTL_RCC_XTAL_2_45MHZ 0x000000C0 // Using a 2.4576MHz crystal +#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal +#define SYSCTL_RCC_XTAL_3_68MHZ 0x00000140 // Using a 3.6864MHz crystal +#define SYSCTL_RCC_XTAL_4MHZ 0x00000180 // Using a 4MHz crystal +#ifdef DEPRECATED +#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864MHz crystal +#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4MHz crystal +#endif +#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal +#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal +#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal +#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal +#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal +#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal +#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal +#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal +#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal +#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select +#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator +#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // Use the internal oscillator +#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // Use the internal oscillator / 4 +#define SYSCTL_RCC_IOSCVER 0x00000008 // Int. osc. verification timer en +#define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en +#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal oscillator disable +#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable +#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field +#define SYSCTL_RCC_PWMDIV_SHIFT 17 // Shift to the PWMDIV field +#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field +#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_PLLCFG register. +// +//***************************************************************************** +#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider +#define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1 +#define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2 +#define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4 +#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier +#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider +#define SYSCTL_PLLCFG_F_SHIFT 5 +#define SYSCTL_PLLCFG_R_SHIFT 0 + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_RCC2 register. +// +//***************************************************************************** +#define SYSCTL_RCC2_USERCC2 0x80000000 // Use RCC2 +#define SYSCTL_RCC2_SYSDIV2_MSK 0x1F800000 // System clock divider +#define SYSCTL_RCC2_SYSDIV2_2 0x00800000 // System clock /2 +#define SYSCTL_RCC2_SYSDIV2_3 0x01000000 // System clock /3 +#define SYSCTL_RCC2_SYSDIV2_4 0x01800000 // System clock /4 +#define SYSCTL_RCC2_SYSDIV2_5 0x02000000 // System clock /5 +#define SYSCTL_RCC2_SYSDIV2_6 0x02800000 // System clock /6 +#define SYSCTL_RCC2_SYSDIV2_7 0x03000000 // System clock /7 +#define SYSCTL_RCC2_SYSDIV2_8 0x03800000 // System clock /8 +#define SYSCTL_RCC2_SYSDIV2_9 0x04000000 // System clock /9 +#define SYSCTL_RCC2_SYSDIV2_10 0x04800000 // System clock /10 +#define SYSCTL_RCC2_SYSDIV2_11 0x05000000 // System clock /11 +#define SYSCTL_RCC2_SYSDIV2_12 0x05800000 // System clock /12 +#define SYSCTL_RCC2_SYSDIV2_13 0x06000000 // System clock /13 +#define SYSCTL_RCC2_SYSDIV2_14 0x06800000 // System clock /14 +#define SYSCTL_RCC2_SYSDIV2_15 0x07000000 // System clock /15 +#define SYSCTL_RCC2_SYSDIV2_16 0x07800000 // System clock /16 +#define SYSCTL_RCC2_SYSDIV2_17 0x08000000 // System clock /17 +#define SYSCTL_RCC2_SYSDIV2_18 0x08800000 // System clock /18 +#define SYSCTL_RCC2_SYSDIV2_19 0x09000000 // System clock /19 +#define SYSCTL_RCC2_SYSDIV2_20 0x09800000 // System clock /20 +#define SYSCTL_RCC2_SYSDIV2_21 0x0A000000 // System clock /21 +#define SYSCTL_RCC2_SYSDIV2_22 0x0A800000 // System clock /22 +#define SYSCTL_RCC2_SYSDIV2_23 0x0B000000 // System clock /23 +#define SYSCTL_RCC2_SYSDIV2_24 0x0B800000 // System clock /24 +#define SYSCTL_RCC2_SYSDIV2_25 0x0C000000 // System clock /25 +#define SYSCTL_RCC2_SYSDIV2_26 0x0C800000 // System clock /26 +#define SYSCTL_RCC2_SYSDIV2_27 0x0D000000 // System clock /27 +#define SYSCTL_RCC2_SYSDIV2_28 0x0D800000 // System clock /28 +#define SYSCTL_RCC2_SYSDIV2_29 0x0E000000 // System clock /29 +#define SYSCTL_RCC2_SYSDIV2_30 0x0E800000 // System clock /30 +#define SYSCTL_RCC2_SYSDIV2_31 0x0F000000 // System clock /31 +#define SYSCTL_RCC2_SYSDIV2_32 0x0F800000 // System clock /32 +#define SYSCTL_RCC2_SYSDIV2_33 0x10000000 // System clock /33 +#define SYSCTL_RCC2_SYSDIV2_34 0x10800000 // System clock /34 +#define SYSCTL_RCC2_SYSDIV2_35 0x11000000 // System clock /35 +#define SYSCTL_RCC2_SYSDIV2_36 0x11800000 // System clock /36 +#define SYSCTL_RCC2_SYSDIV2_37 0x12000000 // System clock /37 +#define SYSCTL_RCC2_SYSDIV2_38 0x12800000 // System clock /38 +#define SYSCTL_RCC2_SYSDIV2_39 0x13000000 // System clock /39 +#define SYSCTL_RCC2_SYSDIV2_40 0x13800000 // System clock /40 +#define SYSCTL_RCC2_SYSDIV2_41 0x14000000 // System clock /41 +#define SYSCTL_RCC2_SYSDIV2_42 0x14800000 // System clock /42 +#define SYSCTL_RCC2_SYSDIV2_43 0x15000000 // System clock /43 +#define SYSCTL_RCC2_SYSDIV2_44 0x15800000 // System clock /44 +#define SYSCTL_RCC2_SYSDIV2_45 0x16000000 // System clock /45 +#define SYSCTL_RCC2_SYSDIV2_46 0x16800000 // System clock /46 +#define SYSCTL_RCC2_SYSDIV2_47 0x17000000 // System clock /47 +#define SYSCTL_RCC2_SYSDIV2_48 0x17800000 // System clock /48 +#define SYSCTL_RCC2_SYSDIV2_49 0x18000000 // System clock /49 +#define SYSCTL_RCC2_SYSDIV2_50 0x18800000 // System clock /50 +#define SYSCTL_RCC2_SYSDIV2_51 0x19000000 // System clock /51 +#define SYSCTL_RCC2_SYSDIV2_52 0x19800000 // System clock /52 +#define SYSCTL_RCC2_SYSDIV2_53 0x1A000000 // System clock /53 +#define SYSCTL_RCC2_SYSDIV2_54 0x1A800000 // System clock /54 +#define SYSCTL_RCC2_SYSDIV2_55 0x1B000000 // System clock /55 +#define SYSCTL_RCC2_SYSDIV2_56 0x1B800000 // System clock /56 +#define SYSCTL_RCC2_SYSDIV2_57 0x1C000000 // System clock /57 +#define SYSCTL_RCC2_SYSDIV2_58 0x1C800000 // System clock /58 +#define SYSCTL_RCC2_SYSDIV2_59 0x1D000000 // System clock /59 +#define SYSCTL_RCC2_SYSDIV2_60 0x1D800000 // System clock /60 +#define SYSCTL_RCC2_SYSDIV2_61 0x1E000000 // System clock /61 +#define SYSCTL_RCC2_SYSDIV2_62 0x1E800000 // System clock /62 +#define SYSCTL_RCC2_SYSDIV2_63 0x1F000000 // System clock /63 +#define SYSCTL_RCC2_SYSDIV2_64 0x1F800000 // System clock /64 +#define SYSCTL_RCC2_PWRDN2 0x00002000 // PLL power down +#define SYSCTL_RCC2_BYPASS2 0x00000800 // PLL bypass +#define SYSCTL_RCC2_OSCSRC2_MSK 0x00000070 // Oscillator input select +#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 // Use the main oscillator +#define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 // Use the internal oscillator +#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 // Use the internal oscillator / 4 +#define SYSCTL_RCC2_OSCSRC2_30 0x00000030 // Use the 30 KHz internal osc. +#define SYSCTL_RCC2_OSCSRC2_32 0x00000070 // Use the 32 KHz external osc. + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_DSLPCLKCFG register. +// +//***************************************************************************** +#define SYSCTL_DSLPCLKCFG_D_MSK 0x1f800000 // Deep sleep system clock override +#define SYSCTL_DSLPCLKCFG_D_2 0x00800000 // System clock /2 +#define SYSCTL_DSLPCLKCFG_D_3 0x01000000 // System clock /3 +#define SYSCTL_DSLPCLKCFG_D_4 0x01800000 // System clock /4 +#define SYSCTL_DSLPCLKCFG_D_5 0x02000000 // System clock /5 +#define SYSCTL_DSLPCLKCFG_D_6 0x02800000 // System clock /6 +#define SYSCTL_DSLPCLKCFG_D_7 0x03000000 // System clock /7 +#define SYSCTL_DSLPCLKCFG_D_8 0x03800000 // System clock /8 +#define SYSCTL_DSLPCLKCFG_D_9 0x04000000 // System clock /9 +#define SYSCTL_DSLPCLKCFG_D_10 0x04800000 // System clock /10 +#define SYSCTL_DSLPCLKCFG_D_11 0x05000000 // System clock /11 +#define SYSCTL_DSLPCLKCFG_D_12 0x05800000 // System clock /12 +#define SYSCTL_DSLPCLKCFG_D_13 0x06000000 // System clock /13 +#define SYSCTL_DSLPCLKCFG_D_14 0x06800000 // System clock /14 +#define SYSCTL_DSLPCLKCFG_D_15 0x07000000 // System clock /15 +#define SYSCTL_DSLPCLKCFG_D_16 0x07800000 // System clock /16 +#define SYSCTL_DSLPCLKCFG_D_17 0x08000000 // System clock /17 +#define SYSCTL_DSLPCLKCFG_D_18 0x08800000 // System clock /18 +#define SYSCTL_DSLPCLKCFG_D_19 0x09000000 // System clock /19 +#define SYSCTL_DSLPCLKCFG_D_20 0x09800000 // System clock /20 +#define SYSCTL_DSLPCLKCFG_D_21 0x0A000000 // System clock /21 +#define SYSCTL_DSLPCLKCFG_D_22 0x0A800000 // System clock /22 +#define SYSCTL_DSLPCLKCFG_D_23 0x0B000000 // System clock /23 +#define SYSCTL_DSLPCLKCFG_D_24 0x0B800000 // System clock /24 +#define SYSCTL_DSLPCLKCFG_D_25 0x0C000000 // System clock /25 +#define SYSCTL_DSLPCLKCFG_D_26 0x0C800000 // System clock /26 +#define SYSCTL_DSLPCLKCFG_D_27 0x0D000000 // System clock /27 +#define SYSCTL_DSLPCLKCFG_D_28 0x0D800000 // System clock /28 +#define SYSCTL_DSLPCLKCFG_D_29 0x0E000000 // System clock /29 +#define SYSCTL_DSLPCLKCFG_D_30 0x0E800000 // System clock /30 +#define SYSCTL_DSLPCLKCFG_D_31 0x0F000000 // System clock /31 +#define SYSCTL_DSLPCLKCFG_D_32 0x0F800000 // System clock /32 +#define SYSCTL_DSLPCLKCFG_D_33 0x10000000 // System clock /33 +#define SYSCTL_DSLPCLKCFG_D_34 0x10800000 // System clock /34 +#define SYSCTL_DSLPCLKCFG_D_35 0x11000000 // System clock /35 +#define SYSCTL_DSLPCLKCFG_D_36 0x11800000 // System clock /36 +#define SYSCTL_DSLPCLKCFG_D_37 0x12000000 // System clock /37 +#define SYSCTL_DSLPCLKCFG_D_38 0x12800000 // System clock /38 +#define SYSCTL_DSLPCLKCFG_D_39 0x13000000 // System clock /39 +#define SYSCTL_DSLPCLKCFG_D_40 0x13800000 // System clock /40 +#define SYSCTL_DSLPCLKCFG_D_41 0x14000000 // System clock /41 +#define SYSCTL_DSLPCLKCFG_D_42 0x14800000 // System clock /42 +#define SYSCTL_DSLPCLKCFG_D_43 0x15000000 // System clock /43 +#define SYSCTL_DSLPCLKCFG_D_44 0x15800000 // System clock /44 +#define SYSCTL_DSLPCLKCFG_D_45 0x16000000 // System clock /45 +#define SYSCTL_DSLPCLKCFG_D_46 0x16800000 // System clock /46 +#define SYSCTL_DSLPCLKCFG_D_47 0x17000000 // System clock /47 +#define SYSCTL_DSLPCLKCFG_D_48 0x17800000 // System clock /48 +#define SYSCTL_DSLPCLKCFG_D_49 0x18000000 // System clock /49 +#define SYSCTL_DSLPCLKCFG_D_50 0x18800000 // System clock /50 +#define SYSCTL_DSLPCLKCFG_D_51 0x19000000 // System clock /51 +#define SYSCTL_DSLPCLKCFG_D_52 0x19800000 // System clock /52 +#define SYSCTL_DSLPCLKCFG_D_53 0x1A000000 // System clock /53 +#define SYSCTL_DSLPCLKCFG_D_54 0x1A800000 // System clock /54 +#define SYSCTL_DSLPCLKCFG_D_55 0x1B000000 // System clock /55 +#define SYSCTL_DSLPCLKCFG_D_56 0x1B800000 // System clock /56 +#define SYSCTL_DSLPCLKCFG_D_57 0x1C000000 // System clock /57 +#define SYSCTL_DSLPCLKCFG_D_58 0x1C800000 // System clock /58 +#define SYSCTL_DSLPCLKCFG_D_59 0x1D000000 // System clock /59 +#define SYSCTL_DSLPCLKCFG_D_60 0x1D800000 // System clock /60 +#define SYSCTL_DSLPCLKCFG_D_61 0x1E000000 // System clock /61 +#define SYSCTL_DSLPCLKCFG_D_62 0x1E800000 // System clock /62 +#define SYSCTL_DSLPCLKCFG_D_63 0x1F000000 // System clock /63 +#define SYSCTL_DSLPCLKCFG_D_64 0x1F800000 // System clock /64 +#define SYSCTL_DSLPCLKCFG_O_MSK 0x00000070 // Deep sleep oscillator override +#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 // Do not override +#define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 // Use the internal oscillator +#define SYSCTL_DSLPCLKCFG_O_30 0x00000030 // Use the 30 KHz internal osc. +#define SYSCTL_DSLPCLKCFG_O_32 0x00000070 // Use the 32 KHz external osc. + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_CLKVCLR register. +// +//***************************************************************************** +#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault + +//***************************************************************************** +// +// The following define the bit fields in the SYSCTL_LDOARST register. +// +//***************************************************************************** +#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device + +#endif // __HW_SYSCTL_H__ diff --git a/20080212/Demo/Common/drivers/LuminaryMicro/hw_timer.h b/20080212/Demo/Common/drivers/LuminaryMicro/hw_timer.h new file mode 100644 index 000000000..6bf0d5305 --- /dev/null +++ b/20080212/Demo/Common/drivers/LuminaryMicro/hw_timer.h @@ -0,0 +1,235 @@ +//***************************************************************************** +// +// hw_timer.h - Defines and macros used when accessing the timer. +// +// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1582 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __HW_TIMER_H__ +#define __HW_TIMER_H__ + +//***************************************************************************** +// +// The following define the offsets of the timer registers. +// +//***************************************************************************** +#define TIMER_O_CFG 0x00000000 // Configuration register +#define TIMER_O_TAMR 0x00000004 // TimerA mode register +#define TIMER_O_TBMR 0x00000008 // TimerB mode register +#define TIMER_O_CTL 0x0000000C // Control register +#define TIMER_O_IMR 0x00000018 // Interrupt mask register +#define TIMER_O_RIS 0x0000001C // Interrupt status register +#define TIMER_O_MIS 0x00000020 // Masked interrupt status reg. +#define TIMER_O_ICR 0x00000024 // Interrupt clear register +#define TIMER_O_TAILR 0x00000028 // TimerA interval load register +#define TIMER_O_TBILR 0x0000002C // TimerB interval load register +#define TIMER_O_TAMATCHR 0x00000030 // TimerA match register +#define TIMER_O_TBMATCHR 0x00000034 // TimerB match register +#define TIMER_O_TAPR 0x00000038 // TimerA prescale register +#define TIMER_O_TBPR 0x0000003C // TimerB prescale register +#define TIMER_O_TAPMR 0x00000040 // TimerA prescale match register +#define TIMER_O_TBPMR 0x00000044 // TimerB prescale match register +#define TIMER_O_TAR 0x00000048 // TimerA register +#define TIMER_O_TBR 0x0000004C // TimerB register + +//***************************************************************************** +// +// The following define the reset values of the timer registers. +// +//***************************************************************************** +#define TIMER_RV_CFG 0x00000000 // Configuration register RV +#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV +#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV +#define TIMER_RV_CTL 0x00000000 // Control register RV +#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV +#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV +#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV +#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV +#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV +#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV +#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV +#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV +#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV +#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV +#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV +#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV +#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV +#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_CFG register. +// +//***************************************************************************** +#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask +#define TIMER_CFG_16_BIT 0x00000004 // Two 16 bit timers +#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32 bit RTC +#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32 bit timer + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_TnMR register. +// +//***************************************************************************** +#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select +#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time +#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask +#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture +#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic +#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_CTL register. +// +//***************************************************************************** +#define TIMER_CTL_TBPWML 0x00004000 // TimerB PWM output level invert +#define TIMER_CTL_TBOTE 0x00002000 // TimerB output trigger enable +#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask +#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // TimerB event mode - both edges +#define TIMER_CTL_TBEVENT_NEG 0x00000400 // TimerB event mode - neg edge +#define TIMER_CTL_TBEVENT_POS 0x00000000 // TimerB event mode - pos edge +#define TIMER_CTL_TBSTALL 0x00000200 // TimerB stall enable +#define TIMER_CTL_TBEN 0x00000100 // TimerB enable +#define TIMER_CTL_TAPWML 0x00000040 // TimerA PWM output level invert +#define TIMER_CTL_TAOTE 0x00000020 // TimerA output trigger enable +#define TIMER_CTL_RTCEN 0x00000010 // RTC counter enable +#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask +#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // TimerA event mode - both edges +#define TIMER_CTL_TAEVENT_NEG 0x00000004 // TimerA event mode - neg edge +#define TIMER_CTL_TAEVENT_POS 0x00000000 // TimerA event mode - pos edge +#define TIMER_CTL_TASTALL 0x00000002 // TimerA stall enable +#define TIMER_CTL_TAEN 0x00000001 // TimerA enable + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_IMR register. +// +//***************************************************************************** +#define TIMER_IMR_CBEIM 0x00000400 // CaptureB event interrupt mask +#define TIMER_IMR_CBMIM 0x00000200 // CaptureB match interrupt mask +#define TIMER_IMR_TBTOIM 0x00000100 // TimerB time out interrupt mask +#define TIMER_IMR_RTCIM 0x00000008 // RTC interrupt mask +#define TIMER_IMR_CAEIM 0x00000004 // CaptureA event interrupt mask +#define TIMER_IMR_CAMIM 0x00000002 // CaptureA match interrupt mask +#define TIMER_IMR_TATOIM 0x00000001 // TimerA time out interrupt mask + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_RIS register. +// +//***************************************************************************** +#define TIMER_RIS_CBERIS 0x00000400 // CaptureB event raw int status +#define TIMER_RIS_CBMRIS 0x00000200 // CaptureB match raw int status +#define TIMER_RIS_TBTORIS 0x00000100 // TimerB time out raw int status +#define TIMER_RIS_RTCRIS 0x00000008 // RTC raw int status +#define TIMER_RIS_CAERIS 0x00000004 // CaptureA event raw int status +#define TIMER_RIS_CAMRIS 0x00000002 // CaptureA match raw int status +#define TIMER_RIS_TATORIS 0x00000001 // TimerA time out raw int status + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_MIS register. +// +//***************************************************************************** +#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status +#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status +#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat +#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status +#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status +#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status +#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_ICR register. +// +//***************************************************************************** +#define TIMER_ICR_CBECINT 0x00000400 // CaptureB event interrupt clear +#define TIMER_ICR_CBMCINT 0x00000200 // CaptureB match interrupt clear +#define TIMER_ICR_TBTOCINT 0x00000100 // TimerB time out interrupt clear +#define TIMER_ICR_RTCCINT 0x00000008 // RTC interrupt clear +#define TIMER_ICR_CAECINT 0x00000004 // CaptureA event interrupt clear +#define TIMER_ICR_CAMCINT 0x00000002 // CaptureA match interrupt clear +#define TIMER_ICR_TATOCINT 0x00000001 // TimerA time out interrupt clear + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_TAILR register. +// +//***************************************************************************** +#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode +#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TBILR register. +// +//***************************************************************************** +#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_TAMATCHR register. +// +//***************************************************************************** +#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode +#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TBMATCHR register. +// +//***************************************************************************** +#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TnPR register. +// +//***************************************************************************** +#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TnPMR register. +// +//***************************************************************************** +#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value + +//***************************************************************************** +// +// The following define the bit fields in the TIMER_TAR register. +// +//***************************************************************************** +#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode +#define TIMER_TAR_TARL 0x0000FFFF // TimerA value + +//***************************************************************************** +// +// The following defines the bit fields in the TIMER_TBR register. +// +//***************************************************************************** +#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value + +#endif // __HW_TIMER_H__ diff --git a/20080212/Demo/Common/drivers/LuminaryMicro/hw_types.h b/20080212/Demo/Common/drivers/LuminaryMicro/hw_types.h new file mode 100644 index 000000000..c31e2c94b --- /dev/null +++ b/20080212/Demo/Common/drivers/LuminaryMicro/hw_types.h @@ -0,0 +1,129 @@ +//***************************************************************************** +// +// hw_types.h - Common types and macros. +// +// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1582 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __HW_TYPES_H__ +#define __HW_TYPES_H__ + +//***************************************************************************** +// +// Define a boolean type, and values for true and false. +// +//***************************************************************************** +typedef unsigned char tBoolean; + +#ifndef true +#define true 1 +#endif + +#ifndef false +#define false 0 +#endif + +//***************************************************************************** +// +// Macros for hardware access, both direct and via the bit-band region. +// +//***************************************************************************** +#define HWREG(x) \ + (*((volatile unsigned long *)(x))) +#define HWREGH(x) \ + (*((volatile unsigned short *)(x))) +#define HWREGB(x) \ + (*((volatile unsigned char *)(x))) +#define HWREGBITW(x, b) \ + HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITH(x, b) \ + HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITB(x, b) \ + HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) + +//***************************************************************************** +// +// Helper Macros for determining silicon revisions, etc. +// +// These macros will be used by Driverlib at "run-time" to create necessary +// conditional code blocks that will allow a single version of the Driverlib +// "binary" code to support multiple(all) Stellaris silicon revisions. +// +// It is expected that these macros will be used inside of a standard 'C' +// conditional block of code, e.g. +// +// if(DEVICE_IS_SANDSTORM()) +// { +// do some Sandstorm specific code here. +// } +// +// By default, these macros will be defined as run-time checks of the +// appropriate register(s) to allow creation of run-time conditional code +// blocks for a common DriverLib across the entire Stellaris family. +// +// However, if code-space optimization is required, these macros can be "hard- +// coded" for a specific version of Stellaris silicon. Many compilers will +// then detect the "hard-coded" conditionals, and appropriately optimize the +// code blocks, eliminating any "unreachable" code. This would result in +// a smaller Driverlib, thus producing a smaller final application size, but +// at the cost of limiting the Driverlib binary to a specific Stellaris +// silicon revision. +// +//***************************************************************************** +#ifndef DEVICE_IS_SANDSTORM +#define DEVICE_IS_SANDSTORM \ + (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_MASK) == SYSCTL_DID0_VER_0) || \ + (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_MASK) == SYSCTL_DID0_VER_1) && \ + ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_CLASS_MASK) == \ + SYSCTL_DID0_CLASS_SANDSTORM))) +#endif + +#ifndef DEVICE_IS_FURY +#define DEVICE_IS_FURY \ + (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_MASK) == SYSCTL_DID0_VER_1) && \ + ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_CLASS_MASK) == \ + SYSCTL_DID0_CLASS_FURY)) +#endif + +#ifndef DEVICE_IS_REVA2 +#define DEVICE_IS_REVA2 \ + (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MAJ_MASK) == SYSCTL_DID0_MAJ_A) && \ + ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MIN_MASK) == SYSCTL_DID0_MIN_2)) +#endif + +#ifndef DEVICE_IS_REVC1 +#define DEVICE_IS_REVC1 \ + (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MAJ_MASK) == SYSCTL_DID0_MAJ_C) && \ + ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MIN_MASK) == SYSCTL_DID0_MIN_1)) +#endif + +#ifndef DEVICE_IS_REVC2 +#define DEVICE_IS_REVC2 \ + (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MAJ_MASK) == SYSCTL_DID0_MAJ_C) && \ + ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MIN_MASK) == SYSCTL_DID0_MIN_2)) +#endif + +#endif // __HW_TYPES_H__ diff --git a/20080212/Demo/Common/drivers/LuminaryMicro/hw_uart.h b/20080212/Demo/Common/drivers/LuminaryMicro/hw_uart.h new file mode 100644 index 000000000..de1127b73 --- /dev/null +++ b/20080212/Demo/Common/drivers/LuminaryMicro/hw_uart.h @@ -0,0 +1,243 @@ +//***************************************************************************** +// +// hw_uart.h - Macros and defines used when accessing the UART hardware +// +// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1582 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __HW_UART_H__ +#define __HW_UART_H__ + +//***************************************************************************** +// +// UART Register Offsets. +// +//***************************************************************************** +#define UART_O_DR 0x00000000 // Data Register +#define UART_O_RSR 0x00000004 // Receive Status Register (read) +#define UART_O_ECR 0x00000004 // Error Clear Register (write) +#define UART_O_FR 0x00000018 // Flag Register (read only) +#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg +#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg +#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte +#define UART_O_CTL 0x00000030 // Control Register +#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg +#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg +#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register +#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register +#define UART_O_ICR 0x00000044 // Interrupt Clear Register +#define UART_O_PeriphID4 0x00000FD0 // +#define UART_O_PeriphID5 0x00000FD4 // +#define UART_O_PeriphID6 0x00000FD8 // +#define UART_O_PeriphID7 0x00000FDC // +#define UART_O_PeriphID0 0x00000FE0 // +#define UART_O_PeriphID1 0x00000FE4 // +#define UART_O_PeriphID2 0x00000FE8 // +#define UART_O_PeriphID3 0x00000FEC // +#define UART_O_PCellID0 0x00000FF0 // +#define UART_O_PCellID1 0x00000FF4 // +#define UART_O_PCellID2 0x00000FF8 // +#define UART_O_PCellID3 0x00000FFC // + +//***************************************************************************** +// +// Data Register bits +// +//***************************************************************************** +#define UART_DR_OE 0x00000800 // Overrun Error +#define UART_DR_BE 0x00000400 // Break Error +#define UART_DR_PE 0x00000200 // Parity Error +#define UART_DR_FE 0x00000100 // Framing Error +#define UART_DR_DATA_MASK 0x000000FF // UART data + +//***************************************************************************** +// +// Receive Status Register bits +// +//***************************************************************************** +#define UART_RSR_OE 0x00000008 // Overrun Error +#define UART_RSR_BE 0x00000004 // Break Error +#define UART_RSR_PE 0x00000002 // Parity Error +#define UART_RSR_FE 0x00000001 // Framing Error + +//***************************************************************************** +// +// Flag Register bits +// +//***************************************************************************** +#define UART_FR_TXFE 0x00000080 // TX FIFO Empty +#define UART_FR_RXFF 0x00000040 // RX FIFO Full +#define UART_FR_TXFF 0x00000020 // TX FIFO Full +#define UART_FR_RXFE 0x00000010 // RX FIFO Empty +#define UART_FR_BUSY 0x00000008 // UART Busy + +//***************************************************************************** +// +// Integer baud-rate divisor +// +//***************************************************************************** +#define UART_IBRD_DIVINT_MASK 0x0000FFFF // Integer baud-rate divisor + +//***************************************************************************** +// +// Fractional baud-rate divisor +// +//***************************************************************************** +#define UART_FBRD_DIVFRAC_MASK 0x0000003F // Fractional baud-rate divisor + +//***************************************************************************** +// +// Line Control Register High bits +// +//***************************************************************************** +#define UART_LCR_H_SPS 0x00000080 // Stick Parity Select +#define UART_LCR_H_WLEN 0x00000060 // Word length +#define UART_LCR_H_WLEN_8 0x00000060 // 8 bit data +#define UART_LCR_H_WLEN_7 0x00000040 // 7 bit data +#define UART_LCR_H_WLEN_6 0x00000020 // 6 bit data +#define UART_LCR_H_WLEN_5 0x00000000 // 5 bit data +#define UART_LCR_H_FEN 0x00000010 // Enable FIFO +#define UART_LCR_H_STP2 0x00000008 // Two Stop Bits Select +#define UART_LCR_H_EPS 0x00000004 // Even Parity Select +#define UART_LCR_H_PEN 0x00000002 // Parity Enable +#define UART_LCR_H_BRK 0x00000001 // Send Break + +//***************************************************************************** +// +// Control Register bits +// +//***************************************************************************** +#define UART_CTL_RXE 0x00000200 // Receive Enable +#define UART_CTL_TXE 0x00000100 // Transmit Enable +#define UART_CTL_LBE 0x00000080 // Loopback Enable +#define UART_CTL_SIRLP 0x00000004 // SIR (IrDA) Low Power Enable +#define UART_CTL_SIREN 0x00000002 // SIR (IrDA) Enable +#define UART_CTL_UARTEN 0x00000001 // UART Enable + +//***************************************************************************** +// +// Interrupt FIFO Level Select Register bits +// +//***************************************************************************** +#define UART_IFLS_RX_MASK 0x00000038 // RX FIFO level mask +#define UART_IFLS_RX1_8 0x00000000 // 1/8 Full +#define UART_IFLS_RX2_8 0x00000008 // 1/4 Full +#define UART_IFLS_RX4_8 0x00000010 // 1/2 Full +#define UART_IFLS_RX6_8 0x00000018 // 3/4 Full +#define UART_IFLS_RX7_8 0x00000020 // 7/8 Full +#define UART_IFLS_TX_MASK 0x00000007 // TX FIFO level mask +#define UART_IFLS_TX1_8 0x00000000 // 1/8 Full +#define UART_IFLS_TX2_8 0x00000001 // 1/4 Full +#define UART_IFLS_TX4_8 0x00000002 // 1/2 Full +#define UART_IFLS_TX6_8 0x00000003 // 3/4 Full +#define UART_IFLS_TX7_8 0x00000004 // 7/8 Full + +//***************************************************************************** +// +// Interrupt Mask Set/Clear Register bits +// +//***************************************************************************** +#define UART_IM_OEIM 0x00000400 // Overrun Error Interrupt Mask +#define UART_IM_BEIM 0x00000200 // Break Error Interrupt Mask +#define UART_IM_PEIM 0x00000100 // Parity Error Interrupt Mask +#define UART_IM_FEIM 0x00000080 // Framing Error Interrupt Mask +#define UART_IM_RTIM 0x00000040 // Receive Timeout Interrupt Mask +#define UART_IM_TXIM 0x00000020 // Transmit Interrupt Mask +#define UART_IM_RXIM 0x00000010 // Receive Interrupt Mask + +//***************************************************************************** +// +// Raw Interrupt Status Register +// +//***************************************************************************** +#define UART_RIS_OERIS 0x00000400 // Overrun Error Interrupt Status +#define UART_RIS_BERIS 0x00000200 // Break Error Interrupt Status +#define UART_RIS_PERIS 0x00000100 // Parity Error Interrupt Status +#define UART_RIS_FERIS 0x00000080 // Framing Error Interrupt Status +#define UART_RIS_RTRIS 0x00000040 // Receive Timeout Interrupt Status +#define UART_RIS_TXRIS 0x00000020 // Transmit Interrupt Status +#define UART_RIS_RXRIS 0x00000010 // Receive Interrupt Status + +//***************************************************************************** +// +// Masked Interrupt Status Register +// +//***************************************************************************** +#define UART_MIS_OEMIS 0x00000400 // Overrun Error Interrupt Status +#define UART_MIS_BEMIS 0x00000200 // Break Error Interrupt Status +#define UART_MIS_PEMIS 0x00000100 // Parity Error Interrupt Status +#define UART_MIS_FEMIS 0x00000080 // Framing Error Interrupt Status +#define UART_MIS_RTMIS 0x00000040 // Receive Timeout Interrupt Status +#define UART_MIS_TXMIS 0x00000020 // Transmit Interrupt Status +#define UART_MIS_RXMIS 0x00000010 // Receive Interrupt Status + +//***************************************************************************** +// +// Interrupt Clear Register bits +// +//***************************************************************************** +#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear +#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear +#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear +#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear +#define UART_ICR_RTIC 0x00000040 // Receive Timeout Interrupt Clear +#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear +#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear + +#define UART_RSR_ANY (UART_RSR_OE | \ + UART_RSR_BE | \ + UART_RSR_PE | \ + UART_RSR_FE) + +//***************************************************************************** +// +// Reset Values for UART Registers. +// +//***************************************************************************** +#define UART_RV_DR 0x00000000 +#define UART_RV_RSR 0x00000000 +#define UART_RV_ECR 0x00000000 +#define UART_RV_FR 0x00000090 +#define UART_RV_IBRD 0x00000000 +#define UART_RV_FBRD 0x00000000 +#define UART_RV_LCR_H 0x00000000 +#define UART_RV_CTL 0x00000300 +#define UART_RV_IFLS 0x00000012 +#define UART_RV_IM 0x00000000 +#define UART_RV_RIS 0x00000000 +#define UART_RV_MIS 0x00000000 +#define UART_RV_ICR 0x00000000 +#define UART_RV_PeriphID4 0x00000000 +#define UART_RV_PeriphID5 0x00000000 +#define UART_RV_PeriphID6 0x00000000 +#define UART_RV_PeriphID7 0x00000000 +#define UART_RV_PeriphID0 0x00000011 +#define UART_RV_PeriphID1 0x00000000 +#define UART_RV_PeriphID2 0x00000018 +#define UART_RV_PeriphID3 0x00000001 +#define UART_RV_PCellID0 0x0000000D +#define UART_RV_PCellID1 0x000000F0 +#define UART_RV_PCellID2 0x00000005 +#define UART_RV_PCellID3 0x000000B1 + +#endif // __HW_UART_H__ diff --git a/20080212/Demo/Common/drivers/LuminaryMicro/hw_watchdog.h b/20080212/Demo/Common/drivers/LuminaryMicro/hw_watchdog.h new file mode 100644 index 000000000..48843ed8c --- /dev/null +++ b/20080212/Demo/Common/drivers/LuminaryMicro/hw_watchdog.h @@ -0,0 +1,116 @@ +//***************************************************************************** +// +// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware. +// +// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1582 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __HW_WATCHDOG_H__ +#define __HW_WATCHDOG_H__ + +//***************************************************************************** +// +// The following define the offsets of the Watchdog Timer registers. +// +//***************************************************************************** +#define WDT_O_LOAD 0x00000000 // Load register +#define WDT_O_VALUE 0x00000004 // Current value register +#define WDT_O_CTL 0x00000008 // Control register +#define WDT_O_ICR 0x0000000C // Interrupt clear register +#define WDT_O_RIS 0x00000010 // Raw interrupt status register +#define WDT_O_MIS 0x00000014 // Masked interrupt status register +#define WDT_O_TEST 0x00000418 // Test register +#define WDT_O_LOCK 0x00000C00 // Lock register +#define WDT_O_PeriphID4 0x00000FD0 // +#define WDT_O_PeriphID5 0x00000FD4 // +#define WDT_O_PeriphID6 0x00000FD8 // +#define WDT_O_PeriphID7 0x00000FDC // +#define WDT_O_PeriphID0 0x00000FE0 // +#define WDT_O_PeriphID1 0x00000FE4 // +#define WDT_O_PeriphID2 0x00000FE8 // +#define WDT_O_PeriphID3 0x00000FEC // +#define WDT_O_PCellID0 0x00000FF0 // +#define WDT_O_PCellID1 0x00000FF4 // +#define WDT_O_PCellID2 0x00000FF8 // +#define WDT_O_PCellID3 0x00000FFC // + +//***************************************************************************** +// +// The following define the bit fields in the WDT_CTL register. +// +//***************************************************************************** +#define WDT_CTL_RESEN 0x00000002 // Enable reset output +#define WDT_CTL_INTEN 0x00000001 // Enable the WDT counter and int + +//***************************************************************************** +// +// The following define the bit fields in the WDT_ISR, WDT_RIS, and WDT_MIS +// registers. +// +//***************************************************************************** +#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired + +//***************************************************************************** +// +// The following define the bit fields in the WDT_TEST register. +// +//***************************************************************************** +#define WDT_TEST_STALL 0x00000100 // Watchdog stall enable +#ifndef DEPRECATED +#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable +#endif + +//***************************************************************************** +// +// The following define the bit fields in the WDT_LOCK register. +// +//***************************************************************************** +#define WDT_LOCK_LOCKED 0x00000001 // Watchdog timer is locked +#define WDT_LOCK_UNLOCKED 0x00000000 // Watchdog timer is unlocked +#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer + +//***************************************************************************** +// +// The following define the reset values for the WDT registers. +// +//***************************************************************************** +#define WDT_RV_LOAD 0xFFFFFFFF // Load register +#define WDT_RV_VALUE 0xFFFFFFFF // Current value register +#define WDT_RV_CTL 0x00000000 // Control register +#define WDT_RV_RIS 0x00000000 // Raw interrupt status register +#define WDT_RV_MIS 0x00000000 // Masked interrupt status register +#define WDT_RV_LOCK 0x00000000 // Lock register +#define WDT_RV_PeriphID4 0x00000000 // +#define WDT_RV_PeriphID5 0x00000000 // +#define WDT_RV_PeriphID6 0x00000000 // +#define WDT_RV_PeriphID7 0x00000000 // +#define WDT_RV_PeriphID0 0x00000005 // +#define WDT_RV_PeriphID1 0x00000018 // +#define WDT_RV_PeriphID2 0x00000018 // +#define WDT_RV_PeriphID3 0x00000001 // +#define WDT_RV_PCellID0 0x0000000D // +#define WDT_RV_PCellID1 0x000000F0 // +#define WDT_RV_PCellID2 0x00000005 // +#define WDT_RV_PCellID3 0x000000B1 // + +#endif // __HW_WATCHDOG_H__ diff --git a/20080212/Demo/Common/drivers/LuminaryMicro/i2c.h b/20080212/Demo/Common/drivers/LuminaryMicro/i2c.h new file mode 100644 index 000000000..0268bd828 --- /dev/null +++ b/20080212/Demo/Common/drivers/LuminaryMicro/i2c.h @@ -0,0 +1,143 @@ +//***************************************************************************** +// +// i2c.h - Prototypes for the I2C Driver. +// +// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1582 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __I2C_H__ +#define __I2C_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Defines for the API. +// +//***************************************************************************** + +//***************************************************************************** +// +// Interrupt defines. +// +//***************************************************************************** +#define I2C_INT_MASTER 0x00000001 +#define I2C_INT_SLAVE 0x00000002 + +//***************************************************************************** +// +// I2C Master commands. +// +//***************************************************************************** +#define I2C_MASTER_CMD_SINGLE_SEND 0x00000007 +#define I2C_MASTER_CMD_SINGLE_RECEIVE 0x00000007 +#define I2C_MASTER_CMD_BURST_SEND_START 0x00000003 +#define I2C_MASTER_CMD_BURST_SEND_CONT 0x00000001 +#define I2C_MASTER_CMD_BURST_SEND_FINISH 0x00000005 +#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP 0x00000004 +#define I2C_MASTER_CMD_BURST_RECEIVE_START 0x0000000b +#define I2C_MASTER_CMD_BURST_RECEIVE_CONT 0x00000009 +#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH 0x00000005 +#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP 0x00000005 + +//***************************************************************************** +// +// I2C Master error status. +// +//***************************************************************************** +#define I2C_MASTER_ERR_NONE 0 +#define I2C_MASTER_ERR_ADDR_ACK 0x00000004 +#define I2C_MASTER_ERR_DATA_ACK 0x00000008 +#define I2C_MASTER_ERR_ARB_LOST 0x00000010 + +//***************************************************************************** +// +// I2C Slave action requests +// +//***************************************************************************** +#define I2C_SLAVE_ACT_NONE 0 +#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data +#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data + +//***************************************************************************** +// +// Miscellaneous I2C driver definitions. +// +//***************************************************************************** +#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void)); +extern void I2CIntUnregister(unsigned long ulBase); +extern tBoolean I2CMasterBusBusy(unsigned long ulBase); +extern tBoolean I2CMasterBusy(unsigned long ulBase); +extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd); +extern unsigned long I2CMasterDataGet(unsigned long ulBase); +extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData); +extern void I2CMasterDisable(unsigned long ulBase); +extern void I2CMasterEnable(unsigned long ulBase); +extern unsigned long I2CMasterErr(unsigned long ulBase); +extern void I2CMasterInitExpClk(unsigned long ulBase, unsigned long ulI2CClk, + tBoolean bFast); +extern void I2CMasterIntClear(unsigned long ulBase); +extern void I2CMasterIntDisable(unsigned long ulBase); +extern void I2CMasterIntEnable(unsigned long ulBase); +extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void I2CMasterSlaveAddrSet(unsigned long ulBase, + unsigned char ucSlaveAddr, + tBoolean bReceive); +extern unsigned long I2CSlaveDataGet(unsigned long ulBase); +extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData); +extern void I2CSlaveDisable(unsigned long ulBase); +extern void I2CSlaveEnable(unsigned long ulBase); +extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr); +extern void I2CSlaveIntClear(unsigned long ulBase); +extern void I2CSlaveIntDisable(unsigned long ulBase); +extern void I2CSlaveIntEnable(unsigned long ulBase); +extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked); +extern unsigned long I2CSlaveStatus(unsigned long ulBase); + +//***************************************************************************** +// +// Several I2C APIs have been renamed, with the original function name being +// deprecated. These defines provide backward compatibility. +// +//***************************************************************************** +#ifndef DEPRECATED +#include "sysctl.h" +#define I2CMasterInit(a, b) \ + I2CMasterInitExpClk(a, SysCtlClockGet(), b) +#endif + +#ifdef __cplusplus +} +#endif + +#endif // __I2C_H__ diff --git a/20080212/Demo/Common/drivers/LuminaryMicro/interrupt.h b/20080212/Demo/Common/drivers/LuminaryMicro/interrupt.h new file mode 100644 index 000000000..fb0ca6e87 --- /dev/null +++ b/20080212/Demo/Common/drivers/LuminaryMicro/interrupt.h @@ -0,0 +1,57 @@ +//***************************************************************************** +// +// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver. +// +// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1582 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void IntMasterEnable(void); +extern void IntMasterDisable(void); +extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)); +extern void IntUnregister(unsigned long ulInterrupt); +extern void IntPriorityGroupingSet(unsigned long ulBits); +extern unsigned long IntPriorityGroupingGet(void); +extern void IntPrioritySet(unsigned long ulInterrupt, + unsigned char ucPriority); +extern long IntPriorityGet(unsigned long ulInterrupt); +extern void IntEnable(unsigned long ulInterrupt); +extern void IntDisable(unsigned long ulInterrupt); + +#ifdef __cplusplus +} +#endif + +#endif // __INTERRUPT_H__ diff --git a/20080212/Demo/Common/drivers/LuminaryMicro/lmi_flash.h b/20080212/Demo/Common/drivers/LuminaryMicro/lmi_flash.h new file mode 100644 index 000000000..e53883fe9 --- /dev/null +++ b/20080212/Demo/Common/drivers/LuminaryMicro/lmi_flash.h @@ -0,0 +1,78 @@ +//***************************************************************************** +// +// flash.h - Prototypes for the flash driver. +// +// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1582 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __FLASH_H__ +#define __FLASH_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to FlashProtectSet(), and returned by +// FlashProtectGet(). +// +//***************************************************************************** +typedef enum +{ + FlashReadWrite, // Flash can be read and written + FlashReadOnly, // Flash can only be read + FlashExecuteOnly // Flash can only be executed +} +tFlashProtection; + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern unsigned long FlashUsecGet(void); +extern void FlashUsecSet(unsigned long ulClocks); +extern long FlashErase(unsigned long ulAddress); +extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress, + unsigned long ulCount); +extern tFlashProtection FlashProtectGet(unsigned long ulAddress); +extern long FlashProtectSet(unsigned long ulAddress, + tFlashProtection eProtect); +extern long FlashProtectSave(void); +extern long FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1); +extern long FlashUserSet(unsigned long ulUser0, unsigned long ulUser1); +extern long FlashUserSave(void); +extern void FlashIntRegister(void (*pfnHandler)(void)); +extern void FlashIntUnregister(void); +extern void FlashIntEnable(unsigned long ulIntFlags); +extern void FlashIntDisable(unsigned long ulIntFlags); +extern unsigned long FlashIntGetStatus(tBoolean bMasked); +extern void FlashIntClear(unsigned long ulIntFlags); + +#ifdef __cplusplus +} +#endif + +#endif // __FLASH_H__ diff --git a/20080212/Demo/Common/drivers/LuminaryMicro/lmi_timer.h b/20080212/Demo/Common/drivers/LuminaryMicro/lmi_timer.h new file mode 100644 index 000000000..0a0d54512 --- /dev/null +++ b/20080212/Demo/Common/drivers/LuminaryMicro/lmi_timer.h @@ -0,0 +1,137 @@ +//***************************************************************************** +// +// timer.h - Prototypes for the timer module +// +// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1582 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __TIMER_H__ +#define __TIMER_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to TimerConfigure as the ulConfig parameter. +// +//***************************************************************************** +#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer +#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer +#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer +#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers +#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer +#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer +#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter +#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer +#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output +#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer +#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer +#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter +#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer +#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output + +//***************************************************************************** +// +// Values that can be passed to TimerIntEnable, TimerIntDisable, and +// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus. +// +//***************************************************************************** +#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt +#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt +#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt +#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask +#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt +#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt +#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt + +//***************************************************************************** +// +// Values that can be passed to TimerControlEvent as the ulEvent parameter. +// +//***************************************************************************** +#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges +#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges +#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges + +//***************************************************************************** +// +// Values that can be passed to most of the timer APIs as the ulTimer +// parameter. +// +//***************************************************************************** +#define TIMER_A 0x000000ff // Timer A +#define TIMER_B 0x0000ff00 // Timer B +#define TIMER_BOTH 0x0000ffff // Timer Both + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer); +extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer); +extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig); +extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, + tBoolean bInvert); +extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer, + tBoolean bEnable); +extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulEvent); +extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer, + tBoolean bStall); +extern void TimerRTCEnable(unsigned long ulBase); +extern void TimerRTCDisable(unsigned long ulBase); +extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerPrescaleGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer); +extern unsigned long TimerValueGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerMatchGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, + void (*pfnHandler)(void)); +extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer); +extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void TimerQuiesce(unsigned long ulBase); + +#ifdef __cplusplus +} +#endif + +#endif // __TIMER_H__ diff --git a/20080212/Demo/Common/drivers/LuminaryMicro/pwm.h b/20080212/Demo/Common/drivers/LuminaryMicro/pwm.h new file mode 100644 index 000000000..d3138d3dd --- /dev/null +++ b/20080212/Demo/Common/drivers/LuminaryMicro/pwm.h @@ -0,0 +1,161 @@ +//***************************************************************************** +// +// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports +// +// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1582 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __PWM_H__ +#define __PWM_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following defines are passed to PWMGenConfigure() as the ulConfig +// parameter and specify the configuration of the PWM generator. +// +//***************************************************************************** +#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode +#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode +#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates +#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates +#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode +#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode + +//***************************************************************************** +// +// Defines for enabling, disabling, and clearing PWM generator interrupts and +// triggers. +// +//***************************************************************************** +#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0 +#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD +#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U +#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D +#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U +#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D +#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0 +#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD +#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U +#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D +#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U +#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D + +//***************************************************************************** +// +// Defines for enabling, disabling, and clearing PWM interrupts. +// +//***************************************************************************** +#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt +#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt +#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt +#define PWM_INT_FAULT 0x00010000 // Fault interrupt + +//***************************************************************************** +// +// Defines to identify the generators within a module. +// +//***************************************************************************** +#define PWM_GEN_0 0x00000040 // Offset address of Gen0 +#define PWM_GEN_1 0x00000080 // Offset address of Gen1 +#define PWM_GEN_2 0x000000C0 // Offset address of Gen2 + +#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0 +#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1 +#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2 + +//***************************************************************************** +// +// Defines to identify the outputs within a module. +// +//***************************************************************************** +#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0 +#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1 +#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2 +#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3 +#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4 +#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5 + +#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0 +#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1 +#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2 +#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3 +#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4 +#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5 + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen, + unsigned long ulConfig); +extern void PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen, + unsigned long ulPeriod); +extern unsigned long PWMGenPeriodGet(unsigned long ulBase, + unsigned long ulGen); +extern void PWMGenEnable(unsigned long ulBase, unsigned long ulGen); +extern void PWMGenDisable(unsigned long ulBase, unsigned long ulGen); +extern void PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut, + unsigned long ulWidth); +extern unsigned long PWMPulseWidthGet(unsigned long ulBase, + unsigned long ulPWMOut); +extern void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen, + unsigned short usRise, unsigned short usFall); +extern void PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen); +extern void PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits); +extern void PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits); +extern void PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bEnable); +extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bInvert); +extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits, + tBoolean bFaultKill); +extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen, + void (*pfnIntHandler)(void)); +extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen); +extern void PWMFaultIntRegister(unsigned long ulBase, + void (*pfnIntHandler)(void)); +extern void PWMFaultIntUnregister(unsigned long ulBase); +extern void PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen, + unsigned long ulIntTrig); +extern void PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen, + unsigned long ulIntTrig); +extern unsigned long PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen, + tBoolean bMasked); +extern void PWMGenIntClear(unsigned long ulBase, unsigned long ulGen, + unsigned long ulInts); +extern void PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault); +extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault); +extern void PWMFaultIntClear(unsigned long ulBase); +extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked); + +#ifdef __cplusplus +} +#endif + +#endif // __PWM_H__ diff --git a/20080212/Demo/Common/drivers/LuminaryMicro/qei.h b/20080212/Demo/Common/drivers/LuminaryMicro/qei.h new file mode 100644 index 000000000..587719aec --- /dev/null +++ b/20080212/Demo/Common/drivers/LuminaryMicro/qei.h @@ -0,0 +1,104 @@ +//***************************************************************************** +// +// qei.h - Prototypes for the Quadrature Encoder Driver. +// +// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1582 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __QEI_H__ +#define __QEI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to QEIConfigure as the ulConfig paramater. +// +//***************************************************************************** +#define QEI_CONFIG_CAPTURE_A 0x00000000 // Count on ChA edges only +#define QEI_CONFIG_CAPTURE_A_B 0x00000008 // Count on ChA and ChB edges +#define QEI_CONFIG_NO_RESET 0x00000000 // Do not reset on index pulse +#define QEI_CONFIG_RESET_IDX 0x00000010 // Reset position on index pulse +#define QEI_CONFIG_QUADRATURE 0x00000000 // ChA and ChB are quadrature +#define QEI_CONFIG_CLOCK_DIR 0x00000004 // ChA and ChB are clock and dir +#define QEI_CONFIG_NO_SWAP 0x00000000 // Do not swap ChA and ChB +#define QEI_CONFIG_SWAP 0x00000002 // Swap ChA and ChB + +//***************************************************************************** +// +// Values that can be passed to QEIVelocityConfigure as the ulPreDiv parameter. +// +//***************************************************************************** +#define QEI_VELDIV_1 0x00000000 // Predivide by 1 +#define QEI_VELDIV_2 0x00000040 // Predivide by 2 +#define QEI_VELDIV_4 0x00000080 // Predivide by 4 +#define QEI_VELDIV_8 0x000000C0 // Predivide by 8 +#define QEI_VELDIV_16 0x00000100 // Predivide by 16 +#define QEI_VELDIV_32 0x00000140 // Predivide by 32 +#define QEI_VELDIV_64 0x00000180 // Predivide by 64 +#define QEI_VELDIV_128 0x000001C0 // Predivide by 128 + +//***************************************************************************** +// +// Values that can be passed to QEIEnableInts, QEIDisableInts, and QEIClearInts +// as the ulIntFlags parameter, and returned by QEIGetIntStatus. +// +//***************************************************************************** +#define QEI_INTERROR 0x00000008 // Phase error detected +#define QEI_INTDIR 0x00000004 // Direction change +#define QEI_INTTIMER 0x00000002 // Velocity timer expired +#define QEI_INTINDEX 0x00000001 // Index pulse detected + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void QEIEnable(unsigned long ulBase); +extern void QEIDisable(unsigned long ulBase); +extern void QEIConfigure(unsigned long ulBase, unsigned long ulConfig, + unsigned long ulMaxPosition); +extern unsigned long QEIPositionGet(unsigned long ulBase); +extern void QEIPositionSet(unsigned long ulBase, unsigned long ulPosition); +extern long QEIDirectionGet(unsigned long ulBase); +extern tBoolean QEIErrorGet(unsigned long ulBase); +extern void QEIVelocityEnable(unsigned long ulBase); +extern void QEIVelocityDisable(unsigned long ulBase); +extern void QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv, + unsigned long ulPeriod); +extern unsigned long QEIVelocityGet(unsigned long ulBase); +extern void QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); +extern void QEIIntUnregister(unsigned long ulBase); +extern void QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long QEIIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags); + +#ifdef __cplusplus +} +#endif + +#endif // __QEI_H__ diff --git a/20080212/Demo/Common/drivers/LuminaryMicro/rit128x96x4.h b/20080212/Demo/Common/drivers/LuminaryMicro/rit128x96x4.h new file mode 100644 index 000000000..eeec8e629 --- /dev/null +++ b/20080212/Demo/Common/drivers/LuminaryMicro/rit128x96x4.h @@ -0,0 +1,53 @@ +//***************************************************************************** +// +// rit128x96x4.h - Prototypes for the driver for the RITEK 128x96x4 graphical +// OLED display. +// +// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1582 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __RIT128X96X4_H__ +#define __RIT128X96X4_H__ + +//***************************************************************************** +// +// Prototypes for the driver APIs. +// +//***************************************************************************** +extern void RIT128x96x4Clear(void); +extern void RIT128x96x4StringDraw(const char *pcStr, + unsigned long ulX, + unsigned long ulY, + unsigned char ucLevel); +extern void RIT128x96x4ImageDraw(const unsigned char *pucImage, + unsigned long ulX, + unsigned long ulY, + unsigned long ulWidth, + unsigned long ulHeight); +extern void RIT128x96x4Init(unsigned long ulFrequency); +extern void RIT128x96x4Enable(unsigned long ulFrequency); +extern void RIT128x96x4Disable(void); +extern void RIT128x96x4DisplayOn(void); +extern void RIT128x96x4DisplayOff(void); + +#endif // __RIT128X96X4_H__ diff --git a/20080212/Demo/Common/drivers/LuminaryMicro/ssi.h b/20080212/Demo/Common/drivers/LuminaryMicro/ssi.h new file mode 100644 index 000000000..088a8bd43 --- /dev/null +++ b/20080212/Demo/Common/drivers/LuminaryMicro/ssi.h @@ -0,0 +1,106 @@ +//***************************************************************************** +// +// ssi.h - Prototypes for the Synchronous Serial Interface Driver. +// +// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1582 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __SSI_H__ +#define __SSI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear +// as the ulIntFlags parameter, and returned by SSIIntStatus. +// +//***************************************************************************** +#define SSI_TXFF 0x00000008 // TX FIFO half empty or less +#define SSI_RXFF 0x00000004 // RX FIFO half full or less +#define SSI_RXTO 0x00000002 // RX timeout +#define SSI_RXOR 0x00000001 // RX overrun + +//***************************************************************************** +// +// Values that can be passed to SSIConfigSetExpClk. +// +//***************************************************************************** +#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0 +#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1 +#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0 +#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1 +#define SSI_FRF_TI 0x00000010 // TI frame format +#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format + +#define SSI_MODE_MASTER 0x00000000 // SSI master +#define SSI_MODE_SLAVE 0x00000001 // SSI slave +#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void SSIConfigSetExpClk(unsigned long ulBase, unsigned long ulSSIClk, + unsigned long ulProtocol, unsigned long ulMode, + unsigned long ulBitRate, + unsigned long ulDataWidth); +extern void SSIDataGet(unsigned long ulBase, unsigned long *pulData); +extern long SSIDataGetNonBlocking(unsigned long ulBase, + unsigned long *pulData); +extern void SSIDataPut(unsigned long ulBase, unsigned long ulData); +extern long SSIDataPutNonBlocking(unsigned long ulBase, unsigned long ulData); +extern void SSIDisable(unsigned long ulBase); +extern void SSIEnable(unsigned long ulBase); +extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void SSIIntUnregister(unsigned long ulBase); + +//***************************************************************************** +// +// Several SSI APIs have been renamed, with the original function name being +// deprecated. These defines provide backward compatibility. +// +//***************************************************************************** +#ifndef DEPRECATED +#include "sysctl.h" +#define SSIConfig(a, b, c, d, e) \ + SSIConfigSetExpClk(a, SysCtlClockGet(), b, c, d, e) +#define SSIDataNonBlockingGet(a, b) \ + SSIDataGetNonBlocking(a, b) +#define SSIDataNonBlockingPut(a, b) \ + SSIDataPutNonBlocking(a, b) +#endif + +#ifdef __cplusplus +} +#endif + +#endif // __SSI_H__ diff --git a/20080212/Demo/Common/drivers/LuminaryMicro/sysctl.h b/20080212/Demo/Common/drivers/LuminaryMicro/sysctl.h new file mode 100644 index 000000000..1ca8bcc6d --- /dev/null +++ b/20080212/Demo/Common/drivers/LuminaryMicro/sysctl.h @@ -0,0 +1,306 @@ +//***************************************************************************** +// +// sysctl.h - Prototypes for the system control driver. +// +// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1582 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __SYSCTL_H__ +#define __SYSCTL_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed to the +// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(), +// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the +// ulPeripheral parameter. The peripherals in the fourth group (upper nibble +// is 3) can only be used with the SysCtlPeripheralPresent() API. +// +//***************************************************************************** +#define SYSCTL_PERIPH_PWM 0x00100010 // PWM +#define SYSCTL_PERIPH_ADC 0x00100001 // ADC +#define SYSCTL_PERIPH_HIBERNATE 0x00000040 // Hibernation module +#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog +#define SYSCTL_PERIPH_CAN0 0x00100100 // CAN 0 +#define SYSCTL_PERIPH_CAN1 0x00100200 // CAN 1 +#define SYSCTL_PERIPH_CAN2 0x00100400 // CAN 2 +#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0 +#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1 +#define SYSCTL_PERIPH_UART2 0x10000004 // UART 2 +#define SYSCTL_PERIPH_SSI 0x10000010 // SSI +#define SYSCTL_PERIPH_SSI0 0x10000010 // SSI 0 +#define SYSCTL_PERIPH_SSI1 0x10000020 // SSI 1 +#define SYSCTL_PERIPH_QEI 0x10000100 // QEI +#define SYSCTL_PERIPH_QEI0 0x10000100 // QEI 0 +#define SYSCTL_PERIPH_QEI1 0x10000200 // QEI 1 +#define SYSCTL_PERIPH_I2C 0x10001000 // I2C +#define SYSCTL_PERIPH_I2C0 0x10001000 // I2C 0 +#define SYSCTL_PERIPH_I2C1 0x10004000 // I2C 1 +#define SYSCTL_PERIPH_TIMER0 0x10100001 // Timer 0 +#define SYSCTL_PERIPH_TIMER1 0x10100002 // Timer 1 +#define SYSCTL_PERIPH_TIMER2 0x10100004 // Timer 2 +#define SYSCTL_PERIPH_TIMER3 0x10100008 // Timer 3 +#define SYSCTL_PERIPH_COMP0 0x10100100 // Analog comparator 0 +#define SYSCTL_PERIPH_COMP1 0x10100200 // Analog comparator 1 +#define SYSCTL_PERIPH_COMP2 0x10100400 // Analog comparator 2 +#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A +#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B +#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C +#define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D +#define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E +#define SYSCTL_PERIPH_GPIOF 0x20000020 // GPIO F +#define SYSCTL_PERIPH_GPIOG 0x20000040 // GPIO G +#define SYSCTL_PERIPH_GPIOH 0x20000080 // GPIO H +#define SYSCTL_PERIPH_ETH 0x20105000 // ETH +#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex M3 MPU +#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor +#define SYSCTL_PERIPH_PLL 0x30000010 // PLL + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlPinPresent() API +// as the ulPin parameter. +// +//***************************************************************************** +#define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin +#define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin +#define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin +#define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin +#define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin +#define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin +#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin +#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin +#define SYSCTL_PIN_C0O 0x00000100 // C0o pin +#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin +#define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin +#define SYSCTL_PIN_C1O 0x00000800 // C1o pin +#define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin +#define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin +#define SYSCTL_PIN_C2O 0x00004000 // C2o pin +#define SYSCTL_PIN_MC_FAULT0 0x00008000 // MC0 Fault pin +#define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin +#define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin +#define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin +#define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin +#define SYSCTL_PIN_ADC4 0x00100000 // ADC4 pin +#define SYSCTL_PIN_ADC5 0x00200000 // ADC5 pin +#define SYSCTL_PIN_ADC6 0x00400000 // ADC6 pin +#define SYSCTL_PIN_ADC7 0x00800000 // ADC7 pin +#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin +#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin +#define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin +#define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin +#define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin +#define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin +#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlLDOSet() API as +// the ulVoltage value, or returned by the SysCtlLDOGet() API. +// +//***************************************************************************** +#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V +#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V +#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V +#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V +#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V +#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V +#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V +#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V +#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V +#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V +#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlLDOConfigSet() API. +// +//***************************************************************************** +#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset +#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlIntEnable(), +// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask +// by the SysCtlIntStatus() API. +// +//***************************************************************************** +#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt +#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt +#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int +#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int +#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt +#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt +#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlResetCauseClear() +// API or returned by the SysCtlResetCauseGet() API. +// +//***************************************************************************** +#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset +#define SYSCTL_CAUSE_SW 0x00000010 // Software reset +#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset +#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset +#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset +#define SYSCTL_CAUSE_EXT 0x00000001 // External reset + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlBrownOutConfigSet() +// API as the ulConfig parameter. +// +//***************************************************************************** +#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting +#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlPWMClockSet() API +// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet() +// API. +// +//***************************************************************************** +#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1 +#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2 +#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4 +#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8 +#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16 +#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32 +#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64 + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlADCSpeedSet() API +// as the ulSpeed parameter, and can be returned by the SyCtlADCSpeedGet() +// API. +// +//***************************************************************************** +#define SYSCTL_ADCSPEED_1MSPS 0x00000300 // 1,000,000 samples per second +#define SYSCTL_ADCSPEED_500KSPS 0x00000200 // 500,000 samples per second +#define SYSCTL_ADCSPEED_250KSPS 0x00000100 // 250,000 samples per second +#define SYSCTL_ADCSPEED_125KSPS 0x00000000 // 125,000 samples per second + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlClockSet() API as +// the ulConfig parameter. +// +//***************************************************************************** +#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1 +#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2 +#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3 +#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4 +#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5 +#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6 +#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7 +#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8 +#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9 +#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10 +#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11 +#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12 +#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13 +#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14 +#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15 +#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16 +#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock +#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock +#define SYSCTL_XTAL_1MHZ 0x00000000 // External crystal is 1MHz +#define SYSCTL_XTAL_1_84MHZ 0x00000040 // External crystal is 1.8432MHz +#define SYSCTL_XTAL_2MHZ 0x00000080 // External crystal is 2MHz +#define SYSCTL_XTAL_2_45MHZ 0x000000C0 // External crystal is 2.4576MHz +#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz +#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz +#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz +#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz +#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz +#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz +#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz +#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz +#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz +#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz +#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz +#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz +#define SYSCTL_OSC_MAIN 0x00000000 // Oscillator source is main osc +#define SYSCTL_OSC_INT 0x00000010 // Oscillator source is int. osc +#define SYSCTL_OSC_INT4 0x00000020 // Oscillator source is int. osc /4 +#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator +#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern unsigned long SysCtlSRAMSizeGet(void); +extern unsigned long SysCtlFlashSizeGet(void); +extern tBoolean SysCtlPinPresent(unsigned long ulPin); +extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral); +extern void SysCtlPeripheralReset(unsigned long ulPeripheral); +extern void SysCtlPeripheralEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralClockGating(tBoolean bEnable); +extern void SysCtlIntRegister(void (*pfnHandler)(void)); +extern void SysCtlIntUnregister(void); +extern void SysCtlIntEnable(unsigned long ulInts); +extern void SysCtlIntDisable(unsigned long ulInts); +extern void SysCtlIntClear(unsigned long ulInts); +extern unsigned long SysCtlIntStatus(tBoolean bMasked); +extern void SysCtlLDOSet(unsigned long ulVoltage); +extern unsigned long SysCtlLDOGet(void); +extern void SysCtlLDOConfigSet(unsigned long ulConfig); +extern void SysCtlReset(void); +extern void SysCtlSleep(void); +extern void SysCtlDeepSleep(void); +extern unsigned long SysCtlResetCauseGet(void); +extern void SysCtlResetCauseClear(unsigned long ulCauses); +extern void SysCtlBrownOutConfigSet(unsigned long ulConfig, + unsigned long ulDelay); +extern void SysCtlClockSet(unsigned long ulConfig); +extern unsigned long SysCtlClockGet(void); +extern void SysCtlPWMClockSet(unsigned long ulConfig); +extern unsigned long SysCtlPWMClockGet(void); +extern void SysCtlADCSpeedSet(unsigned long ulSpeed); +extern unsigned long SysCtlADCSpeedGet(void); +extern void SysCtlIOSCVerificationSet(tBoolean bEnable); +extern void SysCtlMOSCVerificationSet(tBoolean bEnable); +extern void SysCtlPLLVerificationSet(tBoolean bEnable); +extern void SysCtlClkVerificationClear(void); + +#ifdef __cplusplus +} +#endif + +#endif // __SYSCTL_H__ diff --git a/20080212/Demo/Common/drivers/LuminaryMicro/systick.h b/20080212/Demo/Common/drivers/LuminaryMicro/systick.h new file mode 100644 index 000000000..c94c70b89 --- /dev/null +++ b/20080212/Demo/Common/drivers/LuminaryMicro/systick.h @@ -0,0 +1,55 @@ +//***************************************************************************** +// +// systick.h - Prototypes for the SysTick driver. +// +// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1582 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __SYSTICK_H__ +#define __SYSTICK_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void SysTickEnable(void); +extern void SysTickDisable(void); +extern void SysTickIntRegister(void (*pfnHandler)(void)); +extern void SysTickIntUnregister(void); +extern void SysTickIntEnable(void); +extern void SysTickIntDisable(void); +extern void SysTickPeriodSet(unsigned long ulPeriod); +extern unsigned long SysTickPeriodGet(void); +extern unsigned long SysTickValueGet(void); + +#ifdef __cplusplus +} +#endif + +#endif // __SYSTICK_H__ diff --git a/20080212/Demo/Common/drivers/LuminaryMicro/timer.h b/20080212/Demo/Common/drivers/LuminaryMicro/timer.h new file mode 100644 index 000000000..0a0d54512 --- /dev/null +++ b/20080212/Demo/Common/drivers/LuminaryMicro/timer.h @@ -0,0 +1,137 @@ +//***************************************************************************** +// +// timer.h - Prototypes for the timer module +// +// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1582 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __TIMER_H__ +#define __TIMER_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to TimerConfigure as the ulConfig parameter. +// +//***************************************************************************** +#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer +#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer +#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer +#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers +#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer +#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer +#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter +#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer +#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output +#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer +#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer +#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter +#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer +#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output + +//***************************************************************************** +// +// Values that can be passed to TimerIntEnable, TimerIntDisable, and +// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus. +// +//***************************************************************************** +#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt +#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt +#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt +#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask +#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt +#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt +#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt + +//***************************************************************************** +// +// Values that can be passed to TimerControlEvent as the ulEvent parameter. +// +//***************************************************************************** +#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges +#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges +#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges + +//***************************************************************************** +// +// Values that can be passed to most of the timer APIs as the ulTimer +// parameter. +// +//***************************************************************************** +#define TIMER_A 0x000000ff // Timer A +#define TIMER_B 0x0000ff00 // Timer B +#define TIMER_BOTH 0x0000ffff // Timer Both + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer); +extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer); +extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig); +extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, + tBoolean bInvert); +extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer, + tBoolean bEnable); +extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulEvent); +extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer, + tBoolean bStall); +extern void TimerRTCEnable(unsigned long ulBase); +extern void TimerRTCDisable(unsigned long ulBase); +extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerPrescaleGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer); +extern unsigned long TimerValueGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, + unsigned long ulValue); +extern unsigned long TimerMatchGet(unsigned long ulBase, + unsigned long ulTimer); +extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, + void (*pfnHandler)(void)); +extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer); +extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void TimerQuiesce(unsigned long ulBase); + +#ifdef __cplusplus +} +#endif + +#endif // __TIMER_H__ diff --git a/20080212/Demo/Common/drivers/LuminaryMicro/uart.h b/20080212/Demo/Common/drivers/LuminaryMicro/uart.h new file mode 100644 index 000000000..b8d2fea25 --- /dev/null +++ b/20080212/Demo/Common/drivers/LuminaryMicro/uart.h @@ -0,0 +1,152 @@ +//***************************************************************************** +// +// uart.h - Defines and Macros for the UART. +// +// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1582 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __UART_H__ +#define __UART_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear +// as the ulIntFlags parameter, and returned from UARTIntStatus. +// +//***************************************************************************** +#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask +#define UART_INT_BE 0x200 // Break Error Interrupt Mask +#define UART_INT_PE 0x100 // Parity Error Interrupt Mask +#define UART_INT_FE 0x080 // Framing Error Interrupt Mask +#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask +#define UART_INT_TX 0x020 // Transmit Interrupt Mask +#define UART_INT_RX 0x010 // Receive Interrupt Mask + +//***************************************************************************** +// +// Values that can be passed to UARTConfigSetExpClk as the ulConfig parameter +// and returned by UARTConfigGetExpClk in the pulConfig parameter. +// Additionally, the UART_CONFIG_PAR_* subset can be passed to +// UARTParityModeSet as the ulParity parameter, and are returned by +// UARTParityModeGet. +// +//***************************************************************************** +#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data +#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data +#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data +#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data +#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit +#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits +#define UART_CONFIG_PAR_NONE 0x00000000 // No parity +#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity +#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity +#define UART_CONFIG_PAR_ONE 0x00000086 // Parity bit is one +#define UART_CONFIG_PAR_ZERO 0x00000082 // Parity bit is zero + +//***************************************************************************** +// +// Values that can be passed to UARTFIFOLevelSet as the ulTxLevel parameter and +// returned by UARTFIFOLevelGet in the pulTxLevel. +// +//***************************************************************************** +#define UART_FIFO_TX1_8 0x00000000 // Transmit interrupt at 1/8 Full +#define UART_FIFO_TX2_8 0x00000001 // Transmit interrupt at 1/4 Full +#define UART_FIFO_TX4_8 0x00000002 // Transmit interrupt at 1/2 Full +#define UART_FIFO_TX6_8 0x00000003 // Transmit interrupt at 3/4 Full +#define UART_FIFO_TX7_8 0x00000004 // Transmit interrupt at 7/8 Full + +//***************************************************************************** +// +// Values that can be passed to UARTFIFOLevelSet as the ulRxLevel parameter and +// returned by UARTFIFOLevelGet in the pulRxLevel. +// +//***************************************************************************** +#define UART_FIFO_RX1_8 0x00000000 // Receive interrupt at 1/8 Full +#define UART_FIFO_RX2_8 0x00000008 // Receive interrupt at 1/4 Full +#define UART_FIFO_RX4_8 0x00000010 // Receive interrupt at 1/2 Full +#define UART_FIFO_RX6_8 0x00000018 // Receive interrupt at 3/4 Full +#define UART_FIFO_RX7_8 0x00000020 // Receive interrupt at 7/8 Full + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity); +extern unsigned long UARTParityModeGet(unsigned long ulBase); +extern void UARTFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel, + unsigned long ulRxLevel); +extern void UARTFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel, + unsigned long *pulRxLevel); +extern void UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk, + unsigned long ulBaud, unsigned long ulConfig); +extern void UARTConfigGetExpClk(unsigned long ulBase, unsigned long ulUARTClk, + unsigned long *pulBaud, + unsigned long *pulConfig); +extern void UARTEnable(unsigned long ulBase); +extern void UARTDisable(unsigned long ulBase); +extern void UARTEnableSIR(unsigned long ulBase, tBoolean bLowPower); +extern void UARTDisableSIR(unsigned long ulBase); +extern tBoolean UARTCharsAvail(unsigned long ulBase); +extern tBoolean UARTSpaceAvail(unsigned long ulBase); +extern long UARTCharGetNonBlocking(unsigned long ulBase); +extern long UARTCharGet(unsigned long ulBase); +extern tBoolean UARTCharPutNonBlocking(unsigned long ulBase, + unsigned char ucData); +extern void UARTCharPut(unsigned long ulBase, unsigned char ucData); +extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState); +extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern void UARTIntUnregister(unsigned long ulBase); +extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags); + +//***************************************************************************** +// +// Several UART APIs have been renamed, with the original function name being +// deprecated. These defines provide backward compatibility. +// +//***************************************************************************** +#ifndef DEPRECATED +#include "sysctl.h" +#define UARTConfigSet(a, b, c) \ + UARTConfigSetExpClk(a, SysCtlClockGet(), b, c) +#define UARTConfigGet(a, b, c) \ + UARTConfigGetExpClk(a, SysCtlClockGet(), b, c) +#define UARTCharNonBlockingGet(a) \ + UARTCharGetNonBlocking(a) +#define UARTCharNonBlockingPut(a, b) \ + UARTCharPutNonBlocking(a, b) +#endif + +#ifdef __cplusplus +} +#endif + +#endif // __UART_H__ diff --git a/20080212/Demo/Common/drivers/LuminaryMicro/ustdlib.c b/20080212/Demo/Common/drivers/LuminaryMicro/ustdlib.c new file mode 100644 index 000000000..e68b143fa --- /dev/null +++ b/20080212/Demo/Common/drivers/LuminaryMicro/ustdlib.c @@ -0,0 +1,670 @@ +//***************************************************************************** +// +// ustdlib.c - Simple standard library functions. +// +// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +//***************************************************************************** + +#include +#include +#include "debug.h" + +//***************************************************************************** +// +//! \addtogroup utilities_api +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// A mapping from an integer between 0 and 15 to its ASCII character +// equivalent. +// +//***************************************************************************** +static const char * const g_pcHex = "0123456789abcdef"; + +//***************************************************************************** +// +//! A simple vsnprintf function supporting \%c, \%d, \%s, \%u, \%x, and \%X. +//! +//! \param pcBuf points to the buffer where the converted string is stored. +//! \param ulSize is the size of the buffer. +//! \param pcString is the format string. +//! \param vaArgP is the list of optional arguments, which depend on the +//! contents of the format string. +//! +//! This function is very similar to the C library vsnprintf() +//! function. Only the following formatting characters are supported: +//! +//! - \%c to print a character +//! - \%d to print a decimal value +//! - \%s to print a string +//! - \%u to print an unsigned decimal value +//! - \%x to print a hexadecimal value using lower case letters +//! - \%X to print a hexadecimal value using lower case letters (not upper case +//! letters as would typically be used) +//! - \%\% to print out a \% character +//! +//! For \%d, \%u, \%x, and \%X, an optional number may reside between the \% +//! and the format character, which specifies the minimum number of characters +//! to use for that value; if preceeded by a 0 then the extra characters will +//! be filled with zeros instead of spaces. For example, ``\%8d'' will use +//! eight characters to print the decimal value with spaces added to reach +//! eight; ``\%08d'' will use eight characters as well but will add zeros +//! instead of spaces. +//! +//! The type of the arguments after \b pcString must match the requirements of +//! the format string. For example, if an integer was passed where a string +//! was expected, an error of some kind will most likely occur. +//! +//! The \b ulSize parameter limits the number of characters that will be +//! stored in the buffer pointed to by \b pcBuf to prevent the possibility +//! of a buffer overflow. The buffer size should be large enough to hold +//! the expected converted output string, including the null termination +//! character. +//! +//! The function will return the number of characters that would be +//! converted as if there were no limit on the buffer size. Therefore +//! it is possible for the function to return a count that is greater than +//! the specified buffer size. If this happens, it means that the output +//! was truncated. +//! +//! \return the number of characters that were to be stored, not including +//! the NULL termination character, regardless of space in the buffer. +// +//***************************************************************************** +int +uvsnprintf(char *pcBuf, unsigned long ulSize, const char *pcString, + va_list vaArgP) +{ + unsigned long ulIdx, ulValue, ulCount, ulBase; + char *pcStr, cFill; + int iConvertCount = 0; + + // + // Check the arguments. + // + ASSERT(pcString != 0); + ASSERT(pcBuf != 0); + ASSERT(ulSize != 0); + + // + // Adjust buffer size limit to allow one space for null termination. + // + if(ulSize) + { + ulSize--; + } + + // + // Initialize the count of characters converted. + // + iConvertCount = 0; + + // + // Loop while there are more characters in the format string. + // + while(*pcString) + { + // + // Find the first non-% character, or the end of the string. + // + for(ulIdx = 0; (pcString[ulIdx] != '%') && (pcString[ulIdx] != '\0'); + ulIdx++) + { + } + + // + // Write this portion of the string to the output buffer. If + // there are more characters to write than there is space in the + // buffer, then only write as much as will fit in the buffer. + // + if(ulIdx > ulSize) + { + strncpy(pcBuf, pcString, ulSize); + pcBuf += ulSize; + ulSize = 0; + } + else + { + strncpy(pcBuf, pcString, ulIdx); + pcBuf += ulIdx; + ulSize -= ulIdx; + } + + // + // Update the conversion count. This will be the number of + // characters that should have been written, even if there was + // not room in the buffer. + // + iConvertCount += ulIdx; + + // + // Skip the portion of the format string that was written. + // + pcString += ulIdx; + + // + // See if the next character is a %. + // + if(*pcString == '%') + { + // + // Skip the %. + // + pcString++; + + // + // Set the digit count to zero, and the fill character to space + // (i.e. to the defaults). + // + ulCount = 0; + cFill = ' '; + + // + // It may be necessary to get back here to process more characters. + // Goto's aren't pretty, but effective. I feel extremely dirty for + // using not one but two of the beasts. + // +again: + + // + // Determine how to handle the next character. + // + switch(*pcString++) + { + // + // Handle the digit characters. + // + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + { + // + // If this is a zero, and it is the first digit, then the + // fill character is a zero instead of a space. + // + if((pcString[-1] == '0') && (ulCount == 0)) + { + cFill = '0'; + } + + // + // Update the digit count. + // + ulCount *= 10; + ulCount += pcString[-1] - '0'; + + // + // Get the next character. + // + goto again; + } + + // + // Handle the %c command. + // + case 'c': + { + // + // Get the value from the varargs. + // + ulValue = va_arg(vaArgP, unsigned long); + + // + // Copy the character to the output buffer, if + // there is room. Update the buffer size remaining. + // + if(ulSize != 0) + { + *pcBuf++ = (char)ulValue; + ulSize--; + } + + // + // Update the conversion count. + // + iConvertCount++; + + // + // This command has been handled. + // + break; + } + + // + // Handle the %d command. + // + case 'd': + { + // + // Get the value from the varargs. + // + ulValue = va_arg(vaArgP, unsigned long); + + // + // If the value is negative, make it positive and stick a + // minus sign in the beginning of the buffer. + // + if((long)ulValue < 0) + { + ulValue = -(long)ulValue; + + if(ulSize != 0) + { + *pcBuf++ = '-'; + ulSize--; + } + + // + // Update the conversion count. + // + iConvertCount++; + } + + // + // Set the base to 10. + // + ulBase = 10; + + // + // Convert the value to ASCII. + // + goto convert; + } + + // + // Handle the %s command. + // + case 's': + { + // + // Get the string pointer from the varargs. + // + pcStr = va_arg(vaArgP, char *); + + // + // Determine the length of the string. + // + for(ulIdx = 0; pcStr[ulIdx] != '\0'; ulIdx++) + { + } + + // + // Copy the string to the output buffer. Only copy + // as much as will fit in the buffer. Update the + // output buffer pointer and the space remaining. + // + if(ulIdx > ulSize) + { + strncpy(pcBuf, pcStr, ulSize); + pcBuf += ulSize; + ulSize = 0; + } + else + { + strncpy(pcBuf, pcStr, ulIdx); + pcBuf += ulIdx; + ulSize -= ulIdx; + } + + // + // Update the conversion count. This will be the number of + // characters that should have been written, even if there + // was not room in the buffer. + // + iConvertCount += ulIdx; + + // + // + // This command has been handled. + // + break; + } + + // + // Handle the %u command. + // + case 'u': + { + // + // Get the value from the varargs. + // + ulValue = va_arg(vaArgP, unsigned long); + + // + // Set the base to 10. + // + ulBase = 10; + + // + // Convert the value to ASCII. + // + goto convert; + } + + // + // Handle the %x and %X commands. Note that they are treated + // identically; i.e. %X will use lower case letters for a-f + // instead of the upper case letters is should use. + // + case 'x': + case 'X': + { + // + // Get the value from the varargs. + // + ulValue = va_arg(vaArgP, unsigned long); + + // + // Set the base to 16. + // + ulBase = 16; + + // + // Determine the number of digits in the string version of + // the value. + // +convert: + for(ulIdx = 1; + (((ulIdx * ulBase) <= ulValue) && + (((ulIdx * ulBase) / ulBase) == ulIdx)); + ulIdx *= ulBase, ulCount--) + { + } + + // + // Provide additional padding at the beginning of the + // string conversion if needed. + // + if((ulCount > 1) && (ulCount < 16)) + { + for(ulCount--; ulCount; ulCount--) + { + // + // Copy the character to the output buffer if + // there is room. + // + if(ulSize != 0) + { + *pcBuf++ = cFill; + ulSize--; + } + + // + // Update the conversion count. + // + iConvertCount++; + } + } + + // + // Convert the value into a string. + // + for(; ulIdx; ulIdx /= ulBase) + { + // + // Copy the character to the output buffer if + // there is room. + // + if(ulSize != 0) + { + *pcBuf++ = g_pcHex[(ulValue / ulIdx) % ulBase]; + ulSize--; + } + + // + // Update the conversion count. + // + iConvertCount++; + } + + // + // This command has been handled. + // + break; + } + + // + // Handle the %% command. + // + case '%': + { + // + // Simply write a single %. + // + if(ulSize != 0) + { + *pcBuf++ = pcString[-1]; + ulSize--; + } + + // + // Update the conversion count. + // + iConvertCount++; + + // + // This command has been handled. + // + break; + } + + // + // Handle all other commands. + // + default: + { + // + // Indicate an error. + // + if(ulSize >= 5) + { + strncpy(pcBuf, "ERROR", 5); + pcBuf += 5; + ulSize -= 5; + } + else + { + strncpy(pcBuf, "ERROR", ulSize); + pcBuf += ulSize; + ulSize = 0; + } + + // + // Update the conversion count. + // + iConvertCount += 5; + + // + // This command has been handled. + // + break; + } + } + } + } + + // + // Null terminate the string in the buffer. + // + *pcBuf = 0; + return(iConvertCount); +} + +//***************************************************************************** +// +//! A simple sprintf function supporting \%c, \%d, \%s, \%u, \%x, and \%X. +//! +//! \param pcBuf is the buffer where the converted string is stored. +//! \param pcString is the format string. +//! \param ... are the optional arguments, which depend on the contents of the +//! format string. +//! +//! This function is very similar to the C library sprintf() function. +//! Only the following formatting characters are supported: +//! +//! - \%c to print a character +//! - \%d to print a decimal value +//! - \%s to print a string +//! - \%u to print an unsigned decimal value +//! - \%x to print a hexadecimal value using lower case letters +//! - \%X to print a hexadecimal value using lower case letters (not upper case +//! letters as would typically be used) +//! - \%\% to print out a \% character +//! +//! For \%d, \%u, \%x, and \%X, an optional number may reside between the \% +//! and the format character, which specifies the minimum number of characters +//! to use for that value; if preceeded by a 0 then the extra characters will +//! be filled with zeros instead of spaces. For example, ``\%8d'' will use +//! eight characters to print the decimal value with spaces added to reach +//! eight; ``\%08d'' will use eight characters as well but will add zeros +//! instead of spaces. +//! +//! The type of the arguments after \b pcString must match the requirements of +//! the format string. For example, if an integer was passed where a string +//! was expected, an error of some kind will most likely occur. +//! +//! The caller must ensure that the buffer pcBuf is large enough to hold the +//! entire converted string, including the null termination character. +//! +//! \return The count of characters that were written to the output buffer, +//! not including the NULL termination character. +// +//***************************************************************************** +int +usprintf(char *pcBuf, const char *pcString, ...) +{ + va_list vaArgP; + int iRet; + + // + // Start the varargs processing. + // + va_start(vaArgP, pcString); + + // + // Call vsnprintf to perform the conversion. Use a + // large number for the buffer size. + // + iRet = uvsnprintf(pcBuf, 0xffff, pcString, vaArgP); + + // + // End the varargs processing. + // + va_end(vaArgP); + + // + // Return the conversion count. + // + return(iRet); +} + +//***************************************************************************** +// +//! A simple snprintf function supporting \%c, \%d, \%s, \%u, \%x, and \%X. +//! +//! \param pcBuf is the buffer where the converted string is stored. +//! \param ulSize is the size of the buffer. +//! \param pcString is the format string. +//! \param ... are the optional arguments, which depend on the contents of the +//! format string. +//! +//! This function is very similar to the C library sprintf() function. +//! Only the following formatting characters are supported: +//! +//! - \%c to print a character +//! - \%d to print a decimal value +//! - \%s to print a string +//! - \%u to print an unsigned decimal value +//! - \%x to print a hexadecimal value using lower case letters +//! - \%X to print a hexadecimal value using lower case letters (not upper case +//! letters as would typically be used) +//! - \%\% to print out a \% character +//! +//! For \%d, \%u, \%x, and \%X, an optional number may reside between the \% +//! and the format character, which specifies the minimum number of characters +//! to use for that value; if preceeded by a 0 then the extra characters will +//! be filled with zeros instead of spaces. For example, ``\%8d'' will use +//! eight characters to print the decimal value with spaces added to reach +//! eight; ``\%08d'' will use eight characters as well but will add zeros +//! instead of spaces. +//! +//! The type of the arguments after \b pcString must match the requirements of +//! the format string. For example, if an integer was passed where a string +//! was expected, an error of some kind will most likely occur. +//! +//! The function will copy at most \b ulSize - 1 characters into the +//! buffer \b pcBuf. One space is reserved in the buffer for the null +//! termination character. +//! +//! The function will return the number of characters that would be +//! converted as if there were no limit on the buffer size. Therefore +//! it is possible for the function to return a count that is greater than +//! the specified buffer size. If this happens, it means that the output +//! was truncated. +//! +//! \return the number of characters that were to be stored, not including +//! the NULL termination character, regardless of space in the buffer. +// +//***************************************************************************** +int +usnprintf(char *pcBuf, unsigned long ulSize, const char *pcString, ...) +{ +int iRet; + + va_list vaArgP; + + // + // Start the varargs processing. + // + va_start(vaArgP, pcString); + + // + // Call vsnprintf to perform the conversion. + // + iRet = uvsnprintf(pcBuf, ulSize, pcString, vaArgP); + + // + // End the varargs processing. + // + va_end(vaArgP); + + // + // Return the conversion count. + // + return(iRet); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/20080212/Demo/Common/drivers/LuminaryMicro/watchdog.h b/20080212/Demo/Common/drivers/LuminaryMicro/watchdog.h new file mode 100644 index 000000000..f5e227285 --- /dev/null +++ b/20080212/Demo/Common/drivers/LuminaryMicro/watchdog.h @@ -0,0 +1,63 @@ +//***************************************************************************** +// +// watchdog.h - Prototypes for the Watchdog Timer API +// +// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. +// +// Software License Agreement +// +// Luminary Micro, Inc. (LMI) is supplying this software for use solely and +// exclusively on LMI's microcontroller products. +// +// The software is owned by LMI and/or its suppliers, and is protected under +// applicable copyright laws. All rights are reserved. Any use in violation +// of the foregoing restrictions may subject the user to criminal sanctions +// under applicable laws, as well as to civil liability for the breach of the +// terms and conditions of this license. +// +// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +// +// This is part of revision 1582 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __WATCHDOG_H__ +#define __WATCHDOG_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern tBoolean WatchdogRunning(unsigned long ulBase); +extern void WatchdogEnable(unsigned long ulBase); +extern void WatchdogResetEnable(unsigned long ulBase); +extern void WatchdogResetDisable(unsigned long ulBase); +extern void WatchdogLock(unsigned long ulBase); +extern void WatchdogUnlock(unsigned long ulBase); +extern tBoolean WatchdogLockState(unsigned long ulBase); +extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal); +extern unsigned long WatchdogReloadGet(unsigned long ulBase); +extern unsigned long WatchdogValueGet(unsigned long ulBase); +extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); +extern void WatchdogIntUnregister(unsigned long ulBase); +extern void WatchdogIntEnable(unsigned long ulBase); +extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void WatchdogIntClear(unsigned long ulBase); +extern void WatchdogStallEnable(unsigned long ulBase); +extern void WatchdogStallDisable(unsigned long ulBase); + +#ifdef __cplusplus +} +#endif + +#endif // __WATCHDOG_H__ diff --git a/20080212/Demo/Common/drivers/OpenOCD/license.txt b/20080212/Demo/Common/drivers/OpenOCD/license.txt new file mode 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z0~*sx@#P>JBV9Jm#6DL~$9ToId0!{gEmoo&mGKjm2#OTW*4>u0-5U+6X*J7T=Ky(H zC87H-+r4$Hrn-t1Fk^ptp+B>5ub>;SFWe@x{^6W*BekZtDk$3C>m; z=4vpVNZtu}=u^_Jo)*YG;n7+V+zO#`)>t#qipgc7Go8XgW=GoH|L(?X{Jp)o{Jy$h zuWm^%;K&4tg%9aFg{Xf`N<7x{Hy6k6rh~onJqBr#+kIvjSYF#0u%~6U#DLS38$0l1 zI9l$v=02{(N%LiebFZ+{6du-O)WmuUK*nx?rV0W|g>&CLhjFO%9Z~ETYdu9U+@oR1 zAR@w9ecd|2pqtY_Xs?l;m9J&Ow^Ha@@TB{mi1hQMA7`C4t(qx@C5*w3YjmkB4g*nw zPV0}0(+9T1+EOuzvJf3ftc{zo + * + */ + +/* This is the part of the API that is linked with + the application */ + +#include "lwip/opt.h" +#include "lwip/api.h" +#include "lwip/api_msg.h" +#include "lwip/memp.h" + + +struct +netbuf *netbuf_new(void) +{ + struct netbuf *buf; + + buf = memp_malloc(MEMP_NETBUF); + if (buf != NULL) { + buf->p = NULL; + buf->ptr = NULL; + return buf; + } else { + return NULL; + } +} + +void +netbuf_delete(struct netbuf *buf) +{ + if (buf != NULL) { + if (buf->p != NULL) { + pbuf_free(buf->p); + buf->p = buf->ptr = NULL; + } + memp_free(MEMP_NETBUF, buf); + } +} + +void * +netbuf_alloc(struct netbuf *buf, u16_t size) +{ + /* Deallocate any previously allocated memory. */ + if (buf->p != NULL) { + pbuf_free(buf->p); + } + buf->p = pbuf_alloc(PBUF_TRANSPORT, size, PBUF_RAM); + if (buf->p == NULL) { + return NULL; + } + buf->ptr = buf->p; + return buf->p->payload; +} + +void +netbuf_free(struct netbuf *buf) +{ + if (buf->p != NULL) { + pbuf_free(buf->p); + } + buf->p = buf->ptr = NULL; +} + +void +netbuf_ref(struct netbuf *buf, void *dataptr, u16_t size) +{ + if (buf->p != NULL) { + pbuf_free(buf->p); + } + buf->p = pbuf_alloc(PBUF_TRANSPORT, 0, PBUF_REF); + buf->p->payload = dataptr; + buf->p->len = buf->p->tot_len = size; + buf->ptr = buf->p; +} + +void +netbuf_chain(struct netbuf *head, struct netbuf *tail) +{ + pbuf_chain(head->p, tail->p); + head->ptr = head->p; + memp_free(MEMP_NETBUF, tail); +} + +u16_t +netbuf_len(struct netbuf *buf) +{ + return buf->p->tot_len; +} + +err_t +netbuf_data(struct netbuf *buf, void **dataptr, u16_t *len) +{ + if (buf->ptr == NULL) { + return ERR_BUF; + } + *dataptr = buf->ptr->payload; + *len = buf->ptr->len; + return ERR_OK; +} + +s8_t +netbuf_next(struct netbuf *buf) +{ + if (buf->ptr->next == NULL) { + return -1; + } + buf->ptr = buf->ptr->next; + if (buf->ptr->next == NULL) { + return 1; + } + return 0; +} + +void +netbuf_first(struct netbuf *buf) +{ + buf->ptr = buf->p; +} + +void +netbuf_copy_partial(struct netbuf *buf, void *dataptr, u16_t len, u16_t offset) +{ + struct pbuf *p; + u16_t i, left; + + left = 0; + + if(buf == NULL || dataptr == NULL) { + return; + } + + /* This implementation is bad. It should use bcopy + instead. */ + for(p = buf->p; left < len && p != NULL; p = p->next) { + if (offset != 0 && offset >= p->len) { + offset -= p->len; + } else { + for(i = offset; i < p->len; ++i) { + ((u8_t *)dataptr)[left] = ((u8_t *)p->payload)[i]; + if (++left >= len) { + return; + } + } + offset = 0; + } + } +} + +void +netbuf_copy(struct netbuf *buf, void *dataptr, u16_t len) +{ + netbuf_copy_partial(buf, dataptr, len, 0); +} + +struct ip_addr * +netbuf_fromaddr(struct netbuf *buf) +{ + return buf->fromaddr; +} + +u16_t +netbuf_fromport(struct netbuf *buf) +{ + return buf->fromport; +} + +struct +netconn *netconn_new_with_proto_and_callback(enum netconn_type t, u16_t proto, + void (*callback)(struct netconn *, enum netconn_evt, u16_t len)) +{ + struct netconn *conn; + struct api_msg *msg; + + conn = memp_malloc(MEMP_NETCONN); + if (conn == NULL) { + return NULL; + } + + conn->err = ERR_OK; + conn->type = t; + conn->pcb.tcp = NULL; + + if ((conn->mbox = sys_mbox_new()) == SYS_MBOX_NULL) { + memp_free(MEMP_NETCONN, conn); + return NULL; + } + conn->recvmbox = SYS_MBOX_NULL; + conn->acceptmbox = SYS_MBOX_NULL; + conn->sem = sys_sem_new(0); + if (conn->sem == SYS_SEM_NULL) { + memp_free(MEMP_NETCONN, conn); + return NULL; + } + conn->state = NETCONN_NONE; + conn->socket = 0; + conn->callback = callback; + conn->recv_avail = 0; + + if((msg = memp_malloc(MEMP_API_MSG)) == NULL) { + memp_free(MEMP_NETCONN, conn); + return NULL; + } + + msg->type = API_MSG_NEWCONN; + msg->msg.msg.bc.port = proto; /* misusing the port field */ + msg->msg.conn = conn; + api_msg_post(msg); + sys_mbox_fetch(conn->mbox, NULL); + memp_free(MEMP_API_MSG, msg); + + if ( conn->err != ERR_OK ) { + memp_free(MEMP_NETCONN, conn); + return NULL; + } + + return conn; +} + + +struct +netconn *netconn_new(enum netconn_type t) +{ + return netconn_new_with_proto_and_callback(t,0,NULL); +} + +struct +netconn *netconn_new_with_callback(enum netconn_type t, + void (*callback)(struct netconn *, enum netconn_evt, u16_t len)) +{ + return netconn_new_with_proto_and_callback(t,0,callback); +} + + +err_t +netconn_delete(struct netconn *conn) +{ + struct api_msg *msg; + void *mem; + + if (conn == NULL) { + return ERR_OK; + } + + if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) { + return ERR_MEM; + } + + msg->type = API_MSG_DELCONN; + msg->msg.conn = conn; + api_msg_post(msg); + sys_mbox_fetch(conn->mbox, NULL); + memp_free(MEMP_API_MSG, msg); + + /* Drain the recvmbox. */ + if (conn->recvmbox != SYS_MBOX_NULL) { + while (sys_arch_mbox_fetch(conn->recvmbox, &mem, 1) != SYS_ARCH_TIMEOUT) { + if (conn->type == NETCONN_TCP) { + if(mem != NULL) + pbuf_free((struct pbuf *)mem); + } else { + netbuf_delete((struct netbuf *)mem); + } + } + sys_mbox_free(conn->recvmbox); + conn->recvmbox = SYS_MBOX_NULL; + } + + + /* Drain the acceptmbox. */ + if (conn->acceptmbox != SYS_MBOX_NULL) { + while (sys_arch_mbox_fetch(conn->acceptmbox, &mem, 1) != SYS_ARCH_TIMEOUT) { + netconn_delete((struct netconn *)mem); + } + + sys_mbox_free(conn->acceptmbox); + conn->acceptmbox = SYS_MBOX_NULL; + } + + sys_mbox_free(conn->mbox); + conn->mbox = SYS_MBOX_NULL; + if (conn->sem != SYS_SEM_NULL) { + sys_sem_free(conn->sem); + } + /* conn->sem = SYS_SEM_NULL;*/ + memp_free(MEMP_NETCONN, conn); + return ERR_OK; +} + +enum netconn_type +netconn_type(struct netconn *conn) +{ + return conn->type; +} + +err_t +netconn_peer(struct netconn *conn, struct ip_addr *addr, + u16_t *port) +{ + switch (conn->type) { + case NETCONN_RAW: + /* return an error as connecting is only a helper for upper layers */ + return ERR_CONN; + case NETCONN_UDPLITE: + case NETCONN_UDPNOCHKSUM: + case NETCONN_UDP: + if (conn->pcb.udp == NULL || + ((conn->pcb.udp->flags & UDP_FLAGS_CONNECTED) == 0)) + return ERR_CONN; + *addr = (conn->pcb.udp->remote_ip); + *port = conn->pcb.udp->remote_port; + break; + case NETCONN_TCP: + if (conn->pcb.tcp == NULL) + return ERR_CONN; + *addr = (conn->pcb.tcp->remote_ip); + *port = conn->pcb.tcp->remote_port; + break; + } + return (conn->err = ERR_OK); +} + +err_t +netconn_addr(struct netconn *conn, struct ip_addr **addr, + u16_t *port) +{ + switch (conn->type) { + case NETCONN_RAW: + *addr = &(conn->pcb.raw->local_ip); + *port = conn->pcb.raw->protocol; + break; + case NETCONN_UDPLITE: + case NETCONN_UDPNOCHKSUM: + case NETCONN_UDP: + *addr = &(conn->pcb.udp->local_ip); + *port = conn->pcb.udp->local_port; + break; + case NETCONN_TCP: + *addr = &(conn->pcb.tcp->local_ip); + *port = conn->pcb.tcp->local_port; + break; + } + return (conn->err = ERR_OK); +} + +err_t +netconn_bind(struct netconn *conn, struct ip_addr *addr, + u16_t port) +{ + struct api_msg *msg; + + if (conn == NULL) { + return ERR_VAL; + } + + if (conn->type != NETCONN_TCP && + conn->recvmbox == SYS_MBOX_NULL) { + if ((conn->recvmbox = sys_mbox_new()) == SYS_MBOX_NULL) { + return ERR_MEM; + } + } + + if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) { + return (conn->err = ERR_MEM); + } + msg->type = API_MSG_BIND; + msg->msg.conn = conn; + msg->msg.msg.bc.ipaddr = addr; + msg->msg.msg.bc.port = port; + api_msg_post(msg); + sys_mbox_fetch(conn->mbox, NULL); + memp_free(MEMP_API_MSG, msg); + return conn->err; +} + + +err_t +netconn_connect(struct netconn *conn, struct ip_addr *addr, + u16_t port) +{ + struct api_msg *msg; + + if (conn == NULL) { + return ERR_VAL; + } + + + if (conn->recvmbox == SYS_MBOX_NULL) { + if ((conn->recvmbox = sys_mbox_new()) == SYS_MBOX_NULL) { + return ERR_MEM; + } + } + + if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) { + return ERR_MEM; + } + msg->type = API_MSG_CONNECT; + msg->msg.conn = conn; + msg->msg.msg.bc.ipaddr = addr; + msg->msg.msg.bc.port = port; + api_msg_post(msg); + sys_mbox_fetch(conn->mbox, NULL); + memp_free(MEMP_API_MSG, msg); + return conn->err; +} + +err_t +netconn_disconnect(struct netconn *conn) +{ + struct api_msg *msg; + + if (conn == NULL) { + return ERR_VAL; + } + + if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) { + return ERR_MEM; + } + msg->type = API_MSG_DISCONNECT; + msg->msg.conn = conn; + api_msg_post(msg); + sys_mbox_fetch(conn->mbox, NULL); + memp_free(MEMP_API_MSG, msg); + return conn->err; + +} + +err_t +netconn_listen(struct netconn *conn) +{ + struct api_msg *msg; + + if (conn == NULL) { + return ERR_VAL; + } + + if (conn->acceptmbox == SYS_MBOX_NULL) { + conn->acceptmbox = sys_mbox_new(); + if (conn->acceptmbox == SYS_MBOX_NULL) { + return ERR_MEM; + } + } + + if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) { + return (conn->err = ERR_MEM); + } + msg->type = API_MSG_LISTEN; + msg->msg.conn = conn; + api_msg_post(msg); + sys_mbox_fetch(conn->mbox, NULL); + memp_free(MEMP_API_MSG, msg); + return conn->err; +} + +struct netconn * +netconn_accept(struct netconn *conn) +{ + struct netconn *newconn; + + if (conn == NULL) { + return NULL; + } + + sys_mbox_fetch(conn->acceptmbox, (void *)&newconn); + /* Register event with callback */ + if (conn->callback) + (*conn->callback)(conn, NETCONN_EVT_RCVMINUS, 0); + + return newconn; +} + +struct netbuf * +netconn_recv(struct netconn *conn) +{ + struct api_msg *msg; + struct netbuf *buf; + struct pbuf *p; + u16_t len; + + if (conn == NULL) { + return NULL; + } + + if (conn->recvmbox == SYS_MBOX_NULL) { + conn->err = ERR_CONN; + return NULL; + } + + if (conn->err != ERR_OK) { + return NULL; + } + + if (conn->type == NETCONN_TCP) { + if (conn->pcb.tcp->state == LISTEN) { + conn->err = ERR_CONN; + return NULL; + } + + + buf = memp_malloc(MEMP_NETBUF); + + if (buf == NULL) { + conn->err = ERR_MEM; + return NULL; + } + + sys_mbox_fetch(conn->recvmbox, (void *)&p); + + if (p != NULL) + { + len = p->tot_len; + conn->recv_avail -= len; + } + else + len = 0; + + /* Register event with callback */ + if (conn->callback) + (*conn->callback)(conn, NETCONN_EVT_RCVMINUS, len); + + /* If we are closed, we indicate that we no longer wish to receive + data by setting conn->recvmbox to SYS_MBOX_NULL. */ + if (p == NULL) { + memp_free(MEMP_NETBUF, buf); + sys_mbox_free(conn->recvmbox); + conn->recvmbox = SYS_MBOX_NULL; + return NULL; + } + + buf->p = p; + buf->ptr = p; + buf->fromport = 0; + buf->fromaddr = NULL; + + /* Let the stack know that we have taken the data. */ + if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) { + conn->err = ERR_MEM; + return buf; + } + msg->type = API_MSG_RECV; + msg->msg.conn = conn; + if (buf != NULL) { + msg->msg.msg.len = buf->p->tot_len; + } else { + msg->msg.msg.len = 1; + } + api_msg_post(msg); + + sys_mbox_fetch(conn->mbox, NULL); + memp_free(MEMP_API_MSG, msg); + } else { + sys_mbox_fetch(conn->recvmbox, (void *)&buf); + conn->recv_avail -= buf->p->tot_len; + /* Register event with callback */ + if (conn->callback) + (*conn->callback)(conn, NETCONN_EVT_RCVMINUS, buf->p->tot_len); + } + + + + + LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_recv: received %p (err %d)\n", (void *)buf, conn->err)); + + + return buf; +} + +err_t +netconn_send(struct netconn *conn, struct netbuf *buf) +{ + struct api_msg *msg; + + if (conn == NULL) { + return ERR_VAL; + } + + if (conn->err != ERR_OK) { + return conn->err; + } + + if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) { + return (conn->err = ERR_MEM); + } + + LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_send: sending %d bytes\n", buf->p->tot_len)); + msg->type = API_MSG_SEND; + msg->msg.conn = conn; + msg->msg.msg.p = buf->p; + api_msg_post(msg); + + sys_mbox_fetch(conn->mbox, NULL); + memp_free(MEMP_API_MSG, msg); + return conn->err; +} + +err_t +netconn_write(struct netconn *conn, void *dataptr, u16_t size, u8_t copy) +{ + struct api_msg *msg; + u16_t len; + + if (conn == NULL) { + return ERR_VAL; + } + + if (conn->err != ERR_OK) { + return conn->err; + } + + if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) { + return (conn->err = ERR_MEM); + } + msg->type = API_MSG_WRITE; + msg->msg.conn = conn; + + + conn->state = NETCONN_WRITE; + while (conn->err == ERR_OK && size > 0) { + msg->msg.msg.w.dataptr = dataptr; + msg->msg.msg.w.copy = copy; + + if (conn->type == NETCONN_TCP) { + if (tcp_sndbuf(conn->pcb.tcp) == 0) { + sys_sem_wait(conn->sem); + if (conn->err != ERR_OK) { + goto ret; + } + } + if (size > tcp_sndbuf(conn->pcb.tcp)) { + /* We cannot send more than one send buffer's worth of data at a + time. */ + len = tcp_sndbuf(conn->pcb.tcp); + } else { + len = size; + } + } else { + len = size; + } + + LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_write: writing %d bytes (%d)\n", len, copy)); + msg->msg.msg.w.len = len; + api_msg_post(msg); + sys_mbox_fetch(conn->mbox, NULL); + if (conn->err == ERR_OK) { + dataptr = (void *)((u8_t *)dataptr + len); + size -= len; + } else if (conn->err == ERR_MEM) { + conn->err = ERR_OK; + sys_sem_wait(conn->sem); + } else { + goto ret; + } + } + ret: + memp_free(MEMP_API_MSG, msg); + conn->state = NETCONN_NONE; + + return conn->err; +} + +err_t +netconn_close(struct netconn *conn) +{ + struct api_msg *msg; + + if (conn == NULL) { + return ERR_VAL; + } + if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) { + return (conn->err = ERR_MEM); + } + + conn->state = NETCONN_CLOSE; + again: + msg->type = API_MSG_CLOSE; + msg->msg.conn = conn; + api_msg_post(msg); + sys_mbox_fetch(conn->mbox, NULL); + if (conn->err == ERR_MEM && + conn->sem != SYS_SEM_NULL) { + sys_sem_wait(conn->sem); + goto again; + } + conn->state = NETCONN_NONE; + memp_free(MEMP_API_MSG, msg); + return conn->err; +} + +err_t +netconn_err(struct netconn *conn) +{ + return conn->err; +} + diff --git a/20080212/Demo/Common/ethernet/lwIP/api/api_msg.c b/20080212/Demo/Common/ethernet/lwIP/api/api_msg.c new file mode 100644 index 000000000..36a7fc1d8 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/api/api_msg.c @@ -0,0 +1,807 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" +#include "lwip/arch.h" +#include "lwip/api_msg.h" +#include "lwip/memp.h" +#include "lwip/sys.h" +#include "lwip/tcpip.h" + +#if LWIP_RAW +static u8_t +recv_raw(void *arg, struct raw_pcb *pcb, struct pbuf *p, + struct ip_addr *addr) +{ + struct netbuf *buf; + struct netconn *conn; + + conn = arg; + if (!conn) return 0; + + if (conn->recvmbox != SYS_MBOX_NULL) { + if (!(buf = memp_malloc(MEMP_NETBUF))) { + return 0; + } + pbuf_ref(p); + buf->p = p; + buf->ptr = p; + buf->fromaddr = addr; + buf->fromport = pcb->protocol; + + conn->recv_avail += p->tot_len; + /* Register event with callback */ + if (conn->callback) + (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, p->tot_len); + sys_mbox_post(conn->recvmbox, buf); + } + + return 0; /* do not eat the packet */ +} +#endif +#if LWIP_UDP +static void +recv_udp(void *arg, struct udp_pcb *pcb, struct pbuf *p, + struct ip_addr *addr, u16_t port) +{ + struct netbuf *buf; + struct netconn *conn; + + conn = arg; + + if (conn == NULL) { + pbuf_free(p); + return; + } + if (conn->recvmbox != SYS_MBOX_NULL) { + buf = memp_malloc(MEMP_NETBUF); + if (buf == NULL) { + pbuf_free(p); + return; + } else { + buf->p = p; + buf->ptr = p; + buf->fromaddr = addr; + buf->fromport = port; + } + + conn->recv_avail += p->tot_len; + /* Register event with callback */ + if (conn->callback) + (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, p->tot_len); + sys_mbox_post(conn->recvmbox, buf); + } +} +#endif /* LWIP_UDP */ +#if LWIP_TCP + +static err_t +recv_tcp(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err) +{ + struct netconn *conn; + u16_t len; + + conn = arg; + + if (conn == NULL) { + pbuf_free(p); + return ERR_VAL; + } + + if (conn->recvmbox != SYS_MBOX_NULL) { + + conn->err = err; + if (p != NULL) { + len = p->tot_len; + conn->recv_avail += len; + } + else + len = 0; + /* Register event with callback */ + if (conn->callback) + (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, len); + sys_mbox_post(conn->recvmbox, p); + } + return ERR_OK; +} + + +static err_t +poll_tcp(void *arg, struct tcp_pcb *pcb) +{ + struct netconn *conn; + + conn = arg; + if (conn != NULL && + (conn->state == NETCONN_WRITE || conn->state == NETCONN_CLOSE) && + conn->sem != SYS_SEM_NULL) { + sys_sem_signal(conn->sem); + } + return ERR_OK; +} + +static err_t +sent_tcp(void *arg, struct tcp_pcb *pcb, u16_t len) +{ + struct netconn *conn; + + conn = arg; + if (conn != NULL && conn->sem != SYS_SEM_NULL) { + sys_sem_signal(conn->sem); + } + + if (conn && conn->callback) + if (tcp_sndbuf(conn->pcb.tcp) > TCP_SNDLOWAT) + (*conn->callback)(conn, NETCONN_EVT_SENDPLUS, len); + + return ERR_OK; +} + +static void +err_tcp(void *arg, err_t err) +{ + struct netconn *conn; + + conn = arg; + + conn->pcb.tcp = NULL; + + + conn->err = err; + if (conn->recvmbox != SYS_MBOX_NULL) { + /* Register event with callback */ + if (conn->callback) + (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, 0); + sys_mbox_post(conn->recvmbox, NULL); + } + if (conn->mbox != SYS_MBOX_NULL) { + sys_mbox_post(conn->mbox, NULL); + } + if (conn->acceptmbox != SYS_MBOX_NULL) { + /* Register event with callback */ + if (conn->callback) + (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, 0); + sys_mbox_post(conn->acceptmbox, NULL); + } + if (conn->sem != SYS_SEM_NULL) { + sys_sem_signal(conn->sem); + } +} + +static void +setup_tcp(struct netconn *conn) +{ + struct tcp_pcb *pcb; + + pcb = conn->pcb.tcp; + tcp_arg(pcb, conn); + tcp_recv(pcb, recv_tcp); + tcp_sent(pcb, sent_tcp); + tcp_poll(pcb, poll_tcp, 4); + tcp_err(pcb, err_tcp); +} + +static err_t +accept_function(void *arg, struct tcp_pcb *newpcb, err_t err) +{ + sys_mbox_t mbox; + struct netconn *newconn; + struct netconn *conn; + +#if API_MSG_DEBUG +#if TCP_DEBUG + tcp_debug_print_state(newpcb->state); +#endif /* TCP_DEBUG */ +#endif /* API_MSG_DEBUG */ + conn = (struct netconn *)arg; + mbox = conn->acceptmbox; + newconn = memp_malloc(MEMP_NETCONN); + if (newconn == NULL) { + return ERR_MEM; + } + newconn->recvmbox = sys_mbox_new(); + if (newconn->recvmbox == SYS_MBOX_NULL) { + memp_free(MEMP_NETCONN, newconn); + return ERR_MEM; + } + newconn->mbox = sys_mbox_new(); + if (newconn->mbox == SYS_MBOX_NULL) { + sys_mbox_free(newconn->recvmbox); + memp_free(MEMP_NETCONN, newconn); + return ERR_MEM; + } + newconn->sem = sys_sem_new(0); + if (newconn->sem == SYS_SEM_NULL) { + sys_mbox_free(newconn->recvmbox); + sys_mbox_free(newconn->mbox); + memp_free(MEMP_NETCONN, newconn); + return ERR_MEM; + } + /* Allocations were OK, setup the PCB etc */ + newconn->type = NETCONN_TCP; + newconn->pcb.tcp = newpcb; + setup_tcp(newconn); + newconn->acceptmbox = SYS_MBOX_NULL; + newconn->err = err; + /* Register event with callback */ + if (conn->callback) + { + (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, 0); + } + /* We have to set the callback here even though + * the new socket is unknown. Mark the socket as -1. */ + newconn->callback = conn->callback; + newconn->socket = -1; + newconn->recv_avail = 0; + + sys_mbox_post(mbox, newconn); + return ERR_OK; +} +#endif /* LWIP_TCP */ + +static void +do_newconn(struct api_msg_msg *msg) +{ + if(msg->conn->pcb.tcp != NULL) { + /* This "new" connection already has a PCB allocated. */ + /* Is this an error condition? Should it be deleted? + We currently just are happy and return. */ + sys_mbox_post(msg->conn->mbox, NULL); + return; + } + + msg->conn->err = ERR_OK; + + /* Allocate a PCB for this connection */ + switch(msg->conn->type) { +#if LWIP_RAW + case NETCONN_RAW: + msg->conn->pcb.raw = raw_new(msg->msg.bc.port); /* misusing the port field */ + raw_recv(msg->conn->pcb.raw, recv_raw, msg->conn); + break; +#endif +#if LWIP_UDP + case NETCONN_UDPLITE: + msg->conn->pcb.udp = udp_new(); + if(msg->conn->pcb.udp == NULL) { + msg->conn->err = ERR_MEM; + break; + } + udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_UDPLITE); + udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn); + break; + case NETCONN_UDPNOCHKSUM: + msg->conn->pcb.udp = udp_new(); + if(msg->conn->pcb.udp == NULL) { + msg->conn->err = ERR_MEM; + break; + } + udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_NOCHKSUM); + udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn); + break; + case NETCONN_UDP: + msg->conn->pcb.udp = udp_new(); + if(msg->conn->pcb.udp == NULL) { + msg->conn->err = ERR_MEM; + break; + } + udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn); + break; +#endif /* LWIP_UDP */ +#if LWIP_TCP + case NETCONN_TCP: + msg->conn->pcb.tcp = tcp_new(); + if(msg->conn->pcb.tcp == NULL) { + msg->conn->err = ERR_MEM; + break; + } + setup_tcp(msg->conn); + break; +#endif + } + + + sys_mbox_post(msg->conn->mbox, NULL); +} + + +static void +do_delconn(struct api_msg_msg *msg) +{ + if (msg->conn->pcb.tcp != NULL) { + switch (msg->conn->type) { +#if LWIP_RAW + case NETCONN_RAW: + raw_remove(msg->conn->pcb.raw); + break; +#endif +#if LWIP_UDP + case NETCONN_UDPLITE: + /* FALLTHROUGH */ + case NETCONN_UDPNOCHKSUM: + /* FALLTHROUGH */ + case NETCONN_UDP: + msg->conn->pcb.udp->recv_arg = NULL; + udp_remove(msg->conn->pcb.udp); + break; +#endif /* LWIP_UDP */ +#if LWIP_TCP + case NETCONN_TCP: + if (msg->conn->pcb.tcp->state == LISTEN) { + tcp_arg(msg->conn->pcb.tcp, NULL); + tcp_accept(msg->conn->pcb.tcp, NULL); + tcp_close(msg->conn->pcb.tcp); + } else { + tcp_arg(msg->conn->pcb.tcp, NULL); + tcp_sent(msg->conn->pcb.tcp, NULL); + tcp_recv(msg->conn->pcb.tcp, NULL); + tcp_poll(msg->conn->pcb.tcp, NULL, 0); + tcp_err(msg->conn->pcb.tcp, NULL); + if (tcp_close(msg->conn->pcb.tcp) != ERR_OK) { + tcp_abort(msg->conn->pcb.tcp); + } + } +#endif + default: + break; + } + } + /* Trigger select() in socket layer */ + if (msg->conn->callback) + { + (*msg->conn->callback)(msg->conn, NETCONN_EVT_RCVPLUS, 0); + (*msg->conn->callback)(msg->conn, NETCONN_EVT_SENDPLUS, 0); + } + + if (msg->conn->mbox != SYS_MBOX_NULL) { + sys_mbox_post(msg->conn->mbox, NULL); + } +} + +static void +do_bind(struct api_msg_msg *msg) +{ + if (msg->conn->pcb.tcp == NULL) { + switch (msg->conn->type) { +#if LWIP_RAW + case NETCONN_RAW: + msg->conn->pcb.raw = raw_new(msg->msg.bc.port); /* misusing the port field as protocol */ + raw_recv(msg->conn->pcb.raw, recv_raw, msg->conn); + break; +#endif +#if LWIP_UDP + case NETCONN_UDPLITE: + msg->conn->pcb.udp = udp_new(); + udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_UDPLITE); + udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn); + break; + case NETCONN_UDPNOCHKSUM: + msg->conn->pcb.udp = udp_new(); + udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_NOCHKSUM); + udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn); + break; + case NETCONN_UDP: + msg->conn->pcb.udp = udp_new(); + udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn); + break; +#endif /* LWIP_UDP */ +#if LWIP_TCP + case NETCONN_TCP: + msg->conn->pcb.tcp = tcp_new(); + setup_tcp(msg->conn); +#endif /* LWIP_TCP */ + default: + break; + } + } + switch (msg->conn->type) { +#if LWIP_RAW + case NETCONN_RAW: + msg->conn->err = raw_bind(msg->conn->pcb.raw,msg->msg.bc.ipaddr); + break; +#endif +#if LWIP_UDP + case NETCONN_UDPLITE: + /* FALLTHROUGH */ + case NETCONN_UDPNOCHKSUM: + /* FALLTHROUGH */ + case NETCONN_UDP: + msg->conn->err = udp_bind(msg->conn->pcb.udp, msg->msg.bc.ipaddr, msg->msg.bc.port); + break; +#endif /* LWIP_UDP */ +#if LWIP_TCP + case NETCONN_TCP: + msg->conn->err = tcp_bind(msg->conn->pcb.tcp, + msg->msg.bc.ipaddr, msg->msg.bc.port); +#endif /* LWIP_TCP */ + default: + break; + } + sys_mbox_post(msg->conn->mbox, NULL); +} +#if LWIP_TCP + +static err_t +do_connected(void *arg, struct tcp_pcb *pcb, err_t err) +{ + struct netconn *conn; + + conn = arg; + + if (conn == NULL) { + return ERR_VAL; + } + + conn->err = err; + if (conn->type == NETCONN_TCP && err == ERR_OK) { + setup_tcp(conn); + } + sys_mbox_post(conn->mbox, NULL); + return ERR_OK; +} +#endif + +static void +do_connect(struct api_msg_msg *msg) +{ + if (msg->conn->pcb.tcp == NULL) { + switch (msg->conn->type) { +#if LWIP_RAW + case NETCONN_RAW: + msg->conn->pcb.raw = raw_new(msg->msg.bc.port); /* misusing the port field as protocol */ + raw_recv(msg->conn->pcb.raw, recv_raw, msg->conn); + break; +#endif +#if LWIP_UDP + case NETCONN_UDPLITE: + msg->conn->pcb.udp = udp_new(); + if (msg->conn->pcb.udp == NULL) { + msg->conn->err = ERR_MEM; + sys_mbox_post(msg->conn->mbox, NULL); + return; + } + udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_UDPLITE); + udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn); + break; + case NETCONN_UDPNOCHKSUM: + msg->conn->pcb.udp = udp_new(); + if (msg->conn->pcb.udp == NULL) { + msg->conn->err = ERR_MEM; + sys_mbox_post(msg->conn->mbox, NULL); + return; + } + udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_NOCHKSUM); + udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn); + break; + case NETCONN_UDP: + msg->conn->pcb.udp = udp_new(); + if (msg->conn->pcb.udp == NULL) { + msg->conn->err = ERR_MEM; + sys_mbox_post(msg->conn->mbox, NULL); + return; + } + udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn); + break; +#endif /* LWIP_UDP */ +#if LWIP_TCP + case NETCONN_TCP: + msg->conn->pcb.tcp = tcp_new(); + if (msg->conn->pcb.tcp == NULL) { + msg->conn->err = ERR_MEM; + sys_mbox_post(msg->conn->mbox, NULL); + return; + } +#endif + default: + break; + } + } + switch (msg->conn->type) { +#if LWIP_RAW + case NETCONN_RAW: + raw_connect(msg->conn->pcb.raw, msg->msg.bc.ipaddr); + sys_mbox_post(msg->conn->mbox, NULL); + break; +#endif +#if LWIP_UDP + case NETCONN_UDPLITE: + /* FALLTHROUGH */ + case NETCONN_UDPNOCHKSUM: + /* FALLTHROUGH */ + case NETCONN_UDP: + udp_connect(msg->conn->pcb.udp, msg->msg.bc.ipaddr, msg->msg.bc.port); + sys_mbox_post(msg->conn->mbox, NULL); + break; +#endif +#if LWIP_TCP + case NETCONN_TCP: + /* tcp_arg(msg->conn->pcb.tcp, msg->conn);*/ + setup_tcp(msg->conn); + tcp_connect(msg->conn->pcb.tcp, msg->msg.bc.ipaddr, msg->msg.bc.port, + do_connected); + /*tcp_output(msg->conn->pcb.tcp);*/ +#endif + + default: + break; + } +} + +static void +do_disconnect(struct api_msg_msg *msg) +{ + + switch (msg->conn->type) { +#if LWIP_RAW + case NETCONN_RAW: + /* Do nothing as connecting is only a helper for upper lwip layers */ + break; +#endif +#if LWIP_UDP + case NETCONN_UDPLITE: + /* FALLTHROUGH */ + case NETCONN_UDPNOCHKSUM: + /* FALLTHROUGH */ + case NETCONN_UDP: + udp_disconnect(msg->conn->pcb.udp); + break; +#endif + case NETCONN_TCP: + break; + } + sys_mbox_post(msg->conn->mbox, NULL); +} + + +static void +do_listen(struct api_msg_msg *msg) +{ + if (msg->conn->pcb.tcp != NULL) { + switch (msg->conn->type) { +#if LWIP_RAW + case NETCONN_RAW: + LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: listen RAW: cannot listen for RAW.\n")); + break; +#endif +#if LWIP_UDP + case NETCONN_UDPLITE: + /* FALLTHROUGH */ + case NETCONN_UDPNOCHKSUM: + /* FALLTHROUGH */ + case NETCONN_UDP: + LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: listen UDP: cannot listen for UDP.\n")); + break; +#endif /* LWIP_UDP */ +#if LWIP_TCP + case NETCONN_TCP: + msg->conn->pcb.tcp = tcp_listen(msg->conn->pcb.tcp); + if (msg->conn->pcb.tcp == NULL) { + msg->conn->err = ERR_MEM; + } else { + if (msg->conn->acceptmbox == SYS_MBOX_NULL) { + msg->conn->acceptmbox = sys_mbox_new(); + if (msg->conn->acceptmbox == SYS_MBOX_NULL) { + msg->conn->err = ERR_MEM; + break; + } + } + tcp_arg(msg->conn->pcb.tcp, msg->conn); + tcp_accept(msg->conn->pcb.tcp, accept_function); + } +#endif + default: + break; + } + } + sys_mbox_post(msg->conn->mbox, NULL); +} + +static void +do_accept(struct api_msg_msg *msg) +{ + if (msg->conn->pcb.tcp != NULL) { + switch (msg->conn->type) { +#if LWIP_RAW + case NETCONN_RAW: + LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: accept RAW: cannot accept for RAW.\n")); + break; +#endif +#if LWIP_UDP + case NETCONN_UDPLITE: + /* FALLTHROUGH */ + case NETCONN_UDPNOCHKSUM: + /* FALLTHROUGH */ + case NETCONN_UDP: + LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: accept UDP: cannot accept for UDP.\n")); + break; +#endif /* LWIP_UDP */ + case NETCONN_TCP: + break; + } + } +} + +static void +do_send(struct api_msg_msg *msg) +{ + if (msg->conn->pcb.tcp != NULL) { + switch (msg->conn->type) { +#if LWIP_RAW + case NETCONN_RAW: + raw_send(msg->conn->pcb.raw, msg->msg.p); + break; +#endif +#if LWIP_UDP + case NETCONN_UDPLITE: + /* FALLTHROUGH */ + case NETCONN_UDPNOCHKSUM: + /* FALLTHROUGH */ + case NETCONN_UDP: + udp_send(msg->conn->pcb.udp, msg->msg.p); + break; +#endif /* LWIP_UDP */ + case NETCONN_TCP: + break; + } + } + sys_mbox_post(msg->conn->mbox, NULL); +} + +static void +do_recv(struct api_msg_msg *msg) +{ +#if LWIP_TCP + if (msg->conn->pcb.tcp != NULL) { + if (msg->conn->type == NETCONN_TCP) { + tcp_recved(msg->conn->pcb.tcp, msg->msg.len); + } + } +#endif + sys_mbox_post(msg->conn->mbox, NULL); +} + +static void +do_write(struct api_msg_msg *msg) +{ +#if LWIP_TCP + err_t err; +#endif + if (msg->conn->pcb.tcp != NULL) { + switch (msg->conn->type) { +#if LWIP_RAW + case NETCONN_RAW: + msg->conn->err = ERR_VAL; + break; +#endif +#if LWIP_UDP + case NETCONN_UDPLITE: + /* FALLTHROUGH */ + case NETCONN_UDPNOCHKSUM: + /* FALLTHROUGH */ + case NETCONN_UDP: + msg->conn->err = ERR_VAL; + break; +#endif /* LWIP_UDP */ +#if LWIP_TCP + case NETCONN_TCP: + err = tcp_write(msg->conn->pcb.tcp, msg->msg.w.dataptr, + msg->msg.w.len, msg->msg.w.copy); + /* This is the Nagle algorithm: inhibit the sending of new TCP + segments when new outgoing data arrives from the user if any + previously transmitted data on the connection remains + unacknowledged. */ + if(err == ERR_OK && (msg->conn->pcb.tcp->unacked == NULL || + (msg->conn->pcb.tcp->flags & TF_NODELAY) || + (msg->conn->pcb.tcp->snd_queuelen) > 1)) { + tcp_output(msg->conn->pcb.tcp); + } + msg->conn->err = err; + if (msg->conn->callback) + if (err == ERR_OK) + { + if (tcp_sndbuf(msg->conn->pcb.tcp) <= TCP_SNDLOWAT) + (*msg->conn->callback)(msg->conn, NETCONN_EVT_SENDMINUS, msg->msg.w.len); + } +#endif + default: + break; + } + } + sys_mbox_post(msg->conn->mbox, NULL); +} + +static void +do_close(struct api_msg_msg *msg) +{ + err_t err; + + err = ERR_OK; + + if (msg->conn->pcb.tcp != NULL) { + switch (msg->conn->type) { +#if LWIP_RAW + case NETCONN_RAW: + break; +#endif +#if LWIP_UDP + case NETCONN_UDPLITE: + /* FALLTHROUGH */ + case NETCONN_UDPNOCHKSUM: + /* FALLTHROUGH */ + case NETCONN_UDP: + break; +#endif /* LWIP_UDP */ +#if LWIP_TCP + case NETCONN_TCP: + if (msg->conn->pcb.tcp->state == LISTEN) { + err = tcp_close(msg->conn->pcb.tcp); + } + else if (msg->conn->pcb.tcp->state == CLOSE_WAIT) { + err = tcp_output(msg->conn->pcb.tcp); + } + msg->conn->err = err; +#endif + default: + break; + } + } + sys_mbox_post(msg->conn->mbox, NULL); +} + +typedef void (* api_msg_decode)(struct api_msg_msg *msg); +static api_msg_decode decode[API_MSG_MAX] = { + do_newconn, + do_delconn, + do_bind, + do_connect, + do_disconnect, + do_listen, + do_accept, + do_send, + do_recv, + do_write, + do_close + }; +void +api_msg_input(struct api_msg *msg) +{ + decode[msg->type](&(msg->msg)); +} + +void +api_msg_post(struct api_msg *msg) +{ + tcpip_apimsg(msg); +} + + + diff --git a/20080212/Demo/Common/ethernet/lwIP/api/err.c b/20080212/Demo/Common/ethernet/lwIP/api/err.c new file mode 100644 index 000000000..cc6367814 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/api/err.c @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/err.h" + +#ifdef LWIP_DEBUG + +static char *err_strerr[] = {"Ok.", + "Out of memory error.", + "Buffer error.", + "Connection aborted.", + "Connection reset.", + "Connection closed.", + "Not connected.", + "Illegal value.", + "Illegal argument.", + "Routing problem.", + "Address in use." +}; + + +char * +lwip_strerr(err_t err) +{ + return err_strerr[-err]; + +} + + +#endif /* LWIP_DEBUG */ diff --git a/20080212/Demo/Common/ethernet/lwIP/api/sockets.c b/20080212/Demo/Common/ethernet/lwIP/api/sockets.c new file mode 100644 index 000000000..26e6d8630 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/api/sockets.c @@ -0,0 +1,1362 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * Improved by Marc Boucher and David Haas + * + */ + +#include +#include + +#include "lwip/opt.h" +#include "lwip/api.h" +#include "lwip/arch.h" +#include "lwip/sys.h" + +#include "lwip/sockets.h" + +#define NUM_SOCKETS MEMP_NUM_NETCONN + +struct lwip_socket { + struct netconn *conn; + struct netbuf *lastdata; + u16_t lastoffset; + u16_t rcvevent; + u16_t sendevent; + u16_t flags; + int err; +}; + +struct lwip_select_cb +{ + struct lwip_select_cb *next; + fd_set *readset; + fd_set *writeset; + fd_set *exceptset; + int sem_signalled; + sys_sem_t sem; +}; + +static struct lwip_socket sockets[NUM_SOCKETS]; +static struct lwip_select_cb *select_cb_list = 0; + +static sys_sem_t socksem = 0; +static sys_sem_t selectsem = 0; + +static void +event_callback(struct netconn *conn, enum netconn_evt evt, u16_t len); + +static int err_to_errno_table[11] = { + 0, /* ERR_OK 0 No error, everything OK. */ + ENOMEM, /* ERR_MEM -1 Out of memory error. */ + ENOBUFS, /* ERR_BUF -2 Buffer error. */ + ECONNABORTED, /* ERR_ABRT -3 Connection aborted. */ + ECONNRESET, /* ERR_RST -4 Connection reset. */ + ESHUTDOWN, /* ERR_CLSD -5 Connection closed. */ + ENOTCONN, /* ERR_CONN -6 Not connected. */ + EINVAL, /* ERR_VAL -7 Illegal value. */ + EIO, /* ERR_ARG -8 Illegal argument. */ + EHOSTUNREACH, /* ERR_RTE -9 Routing problem. */ + EADDRINUSE /* ERR_USE -10 Address in use. */ +}; + +#define ERR_TO_ERRNO_TABLE_SIZE \ + (sizeof(err_to_errno_table)/sizeof(err_to_errno_table[0])) + +#define err_to_errno(err) \ + (-(err) >= 0 && -(err) < ERR_TO_ERRNO_TABLE_SIZE ? \ + err_to_errno_table[-(err)] : EIO) + +#ifdef ERRNO +#define set_errno(err) errno = (err) +#else +#define set_errno(err) +#endif + +#define sock_set_errno(sk, e) do { \ + sk->err = (e); \ + set_errno(sk->err); \ +} while (0) + + +static struct lwip_socket * +get_socket(int s) +{ + struct lwip_socket *sock; + + if ((s < 0) || (s > NUM_SOCKETS)) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("get_socket(%d): invalid\n", s)); + set_errno(EBADF); + return NULL; + } + + sock = &sockets[s]; + + if (!sock->conn) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("get_socket(%d): not active\n", s)); + set_errno(EBADF); + return NULL; + } + + return sock; +} + +static int +alloc_socket(struct netconn *newconn) +{ + int i; + + if (!socksem) + socksem = sys_sem_new(1); + + /* Protect socket array */ + sys_sem_wait(socksem); + + /* allocate a new socket identifier */ + for(i = 0; i < NUM_SOCKETS; ++i) { + if (!sockets[i].conn) { + sockets[i].conn = newconn; + sockets[i].lastdata = NULL; + sockets[i].lastoffset = 0; + sockets[i].rcvevent = 0; + sockets[i].sendevent = 1; /* TCP send buf is empty */ + sockets[i].flags = 0; + sockets[i].err = 0; + sys_sem_signal(socksem); + return i; + } + } + sys_sem_signal(socksem); + return -1; +} + +int +lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen) +{ + struct lwip_socket *sock; + struct netconn *newconn; + struct ip_addr naddr; + u16_t port; + int newsock; + struct sockaddr_in sin; + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d)...\n", s)); + sock = get_socket(s); + if (!sock) { + set_errno(EBADF); + return -1; + } + + newconn = netconn_accept(sock->conn); + + /* get the IP address and port of the remote host */ + netconn_peer(newconn, &naddr, &port); + + memset(&sin, 0, sizeof(sin)); + sin.sin_len = sizeof(sin); + sin.sin_family = AF_INET; + sin.sin_port = htons(port); + sin.sin_addr.s_addr = naddr.addr; + + if (*addrlen > sizeof(sin)) + *addrlen = sizeof(sin); + + memcpy(addr, &sin, *addrlen); + + newsock = alloc_socket(newconn); + if (newsock == -1) { + netconn_delete(newconn); + sock_set_errno(sock, ENOBUFS); + return -1; + } + newconn->callback = event_callback; + sock = get_socket(newsock); + + sys_sem_wait(socksem); + sock->rcvevent += -1 - newconn->socket; + newconn->socket = newsock; + sys_sem_signal(socksem); + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d) returning new sock=%d addr=", s, newsock)); + ip_addr_debug_print(SOCKETS_DEBUG, &naddr); + LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u\n", port)); + + sock_set_errno(sock, 0); + return newsock; +} + +int +lwip_bind(int s, struct sockaddr *name, socklen_t namelen) +{ + struct lwip_socket *sock; + struct ip_addr local_addr; + u16_t local_port; + err_t err; + + sock = get_socket(s); + if (!sock) { + set_errno(EBADF); + return -1; + } + + local_addr.addr = ((struct sockaddr_in *)name)->sin_addr.s_addr; + local_port = ((struct sockaddr_in *)name)->sin_port; + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d, addr=", s)); + ip_addr_debug_print(SOCKETS_DEBUG, &local_addr); + LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u)\n", ntohs(local_port))); + + err = netconn_bind(sock->conn, &local_addr, ntohs(local_port)); + + if (err != ERR_OK) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d) failed, err=%d\n", s, err)); + sock_set_errno(sock, err_to_errno(err)); + return -1; + } + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d) succeeded\n", s)); + sock_set_errno(sock, 0); + return 0; +} + +int +lwip_close(int s) +{ + struct lwip_socket *sock; + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_close(%d)\n", s)); + if (!socksem) + socksem = sys_sem_new(1); + + /* We cannot allow multiple closes of the same socket. */ + sys_sem_wait(socksem); + + sock = get_socket(s); + if (!sock) { + sys_sem_signal(socksem); + set_errno(EBADF); + return -1; + } + + netconn_delete(sock->conn); + if (sock->lastdata) { + netbuf_delete(sock->lastdata); + } + sock->lastdata = NULL; + sock->lastoffset = 0; + sock->conn = NULL; + sys_sem_signal(socksem); + sock_set_errno(sock, 0); + return 0; +} + +int +lwip_connect(int s, struct sockaddr *name, socklen_t namelen) +{ + struct lwip_socket *sock; + err_t err; + + sock = get_socket(s); + if (!sock) { + set_errno(EBADF); + return -1; + } + + if (((struct sockaddr_in *)name)->sin_family == AF_UNSPEC) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d, AF_UNSPEC)\n", s)); + err = netconn_disconnect(sock->conn); + } else { + struct ip_addr remote_addr; + u16_t remote_port; + + remote_addr.addr = ((struct sockaddr_in *)name)->sin_addr.s_addr; + remote_port = ((struct sockaddr_in *)name)->sin_port; + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d, addr=", s)); + ip_addr_debug_print(SOCKETS_DEBUG, &remote_addr); + LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u)\n", ntohs(remote_port))); + + err = netconn_connect(sock->conn, &remote_addr, ntohs(remote_port)); + } + + if (err != ERR_OK) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d) failed, err=%d\n", s, err)); + sock_set_errno(sock, err_to_errno(err)); + return -1; + } + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d) succeeded\n", s)); + sock_set_errno(sock, 0); + return 0; +} + +int +lwip_listen(int s, int backlog) +{ + struct lwip_socket *sock; + err_t err; + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_listen(%d, backlog=%d)\n", s, backlog)); + sock = get_socket(s); + if (!sock) { + set_errno(EBADF); + return -1; + } + + err = netconn_listen(sock->conn); + + if (err != ERR_OK) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_listen(%d) failed, err=%d\n", s, err)); + sock_set_errno(sock, err_to_errno(err)); + return -1; + } + + sock_set_errno(sock, 0); + return 0; +} + +int +lwip_recvfrom(int s, void *mem, int len, unsigned int flags, + struct sockaddr *from, socklen_t *fromlen) +{ + struct lwip_socket *sock; + struct netbuf *buf; + u16_t buflen, copylen; + struct ip_addr *addr; + u16_t port; + + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d, %p, %d, 0x%x, ..)\n", s, mem, len, flags)); + sock = get_socket(s); + if (!sock) { + set_errno(EBADF); + return -1; + } + + /* Check if there is data left from the last recv operation. */ + if (sock->lastdata) { + buf = sock->lastdata; + } else { + /* If this is non-blocking call, then check first */ + if (((flags & MSG_DONTWAIT) || (sock->flags & O_NONBLOCK)) + && !sock->rcvevent) + { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): returning EWOULDBLOCK\n", s)); + sock_set_errno(sock, EWOULDBLOCK); + return -1; + } + + /* No data was left from the previous operation, so we try to get + some from the network. */ + buf = netconn_recv(sock->conn); + + if (!buf) { + /* We should really do some error checking here. */ + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): buf == NULL!\n", s)); + sock_set_errno(sock, 0); + return 0; + } + } + + buflen = netbuf_len(buf); + + buflen -= sock->lastoffset; + + if (len > buflen) { + copylen = buflen; + } else { + copylen = len; + } + + /* copy the contents of the received buffer into + the supplied memory pointer mem */ + netbuf_copy_partial(buf, mem, copylen, sock->lastoffset); + + /* Check to see from where the data was. */ + if (from && fromlen) { + struct sockaddr_in sin; + + addr = netbuf_fromaddr(buf); + port = netbuf_fromport(buf); + + memset(&sin, 0, sizeof(sin)); + sin.sin_len = sizeof(sin); + sin.sin_family = AF_INET; + sin.sin_port = htons(port); + sin.sin_addr.s_addr = addr->addr; + + if (*fromlen > sizeof(sin)) + *fromlen = sizeof(sin); + + memcpy(from, &sin, *fromlen); + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): addr=", s)); + ip_addr_debug_print(SOCKETS_DEBUG, addr); + LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u len=%u\n", port, copylen)); + } else { +#if SOCKETS_DEBUG + addr = netbuf_fromaddr(buf); + port = netbuf_fromport(buf); + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): addr=", s)); + ip_addr_debug_print(SOCKETS_DEBUG, addr); + LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u len=%u\n", port, copylen)); +#endif + + } + + /* If this is a TCP socket, check if there is data left in the + buffer. If so, it should be saved in the sock structure for next + time around. */ + if (netconn_type(sock->conn) == NETCONN_TCP && buflen - copylen > 0) { + sock->lastdata = buf; + sock->lastoffset += copylen; + } else { + sock->lastdata = NULL; + sock->lastoffset = 0; + netbuf_delete(buf); + } + + + sock_set_errno(sock, 0); + return copylen; +} + +int +lwip_read(int s, void *mem, int len) +{ + return lwip_recvfrom(s, mem, len, 0, NULL, NULL); +} + +int +lwip_recv(int s, void *mem, int len, unsigned int flags) +{ + return lwip_recvfrom(s, mem, len, flags, NULL, NULL); +} + +int +lwip_send(int s, void *data, int size, unsigned int flags) +{ + struct lwip_socket *sock; + struct netbuf *buf; + err_t err; + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d, data=%p, size=%d, flags=0x%x)\n", s, data, size, flags)); + + sock = get_socket(s); + if (!sock) { + set_errno(EBADF); + return -1; + } + + switch (netconn_type(sock->conn)) { + case NETCONN_RAW: + case NETCONN_UDP: + case NETCONN_UDPLITE: + case NETCONN_UDPNOCHKSUM: + /* create a buffer */ + buf = netbuf_new(); + + if (!buf) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d) ENOBUFS\n", s)); + sock_set_errno(sock, ENOBUFS); + return -1; + } + + /* make the buffer point to the data that should + be sent */ + netbuf_ref(buf, data, size); + + /* send the data */ + err = netconn_send(sock->conn, buf); + + /* deallocated the buffer */ + netbuf_delete(buf); + break; + case NETCONN_TCP: + err = netconn_write(sock->conn, data, size, NETCONN_COPY); + break; + default: + err = ERR_ARG; + break; + } + if (err != ERR_OK) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d) err=%d\n", s, err)); + sock_set_errno(sock, err_to_errno(err)); + return -1; + } + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d) ok size=%d\n", s, size)); + sock_set_errno(sock, 0); + return size; +} + +int +lwip_sendto(int s, void *data, int size, unsigned int flags, + struct sockaddr *to, socklen_t tolen) +{ + struct lwip_socket *sock; + struct ip_addr remote_addr, addr; + u16_t remote_port, port; + int ret,connected; + + sock = get_socket(s); + if (!sock) { + set_errno(EBADF); + return -1; + } + + /* get the peer if currently connected */ + connected = (netconn_peer(sock->conn, &addr, &port) == ERR_OK); + + remote_addr.addr = ((struct sockaddr_in *)to)->sin_addr.s_addr; + remote_port = ((struct sockaddr_in *)to)->sin_port; + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_sendto(%d, data=%p, size=%d, flags=0x%x to=", s, data, size, flags)); + ip_addr_debug_print(SOCKETS_DEBUG, &remote_addr); + LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u\n", ntohs(remote_port))); + + netconn_connect(sock->conn, &remote_addr, ntohs(remote_port)); + + ret = lwip_send(s, data, size, flags); + + /* reset the remote address and port number + of the connection */ + if (connected) + netconn_connect(sock->conn, &addr, port); + else + netconn_disconnect(sock->conn); + return ret; +} + +int +lwip_socket(int domain, int type, int protocol) +{ + struct netconn *conn; + int i; + + /* create a netconn */ + switch (type) { + case SOCK_RAW: + conn = netconn_new_with_proto_and_callback(NETCONN_RAW, protocol, event_callback); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_RAW, %d) = ", domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol)); + break; + case SOCK_DGRAM: + conn = netconn_new_with_callback(NETCONN_UDP, event_callback); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_DGRAM, %d) = ", domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol)); + break; + case SOCK_STREAM: + conn = netconn_new_with_callback(NETCONN_TCP, event_callback); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_STREAM, %d) = ", domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol)); + break; + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%d, %d/UNKNOWN, %d) = -1\n", domain, type, protocol)); + set_errno(EINVAL); + return -1; + } + + if (!conn) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("-1 / ENOBUFS (could not create netconn)\n")); + set_errno(ENOBUFS); + return -1; + } + + i = alloc_socket(conn); + + if (i == -1) { + netconn_delete(conn); + set_errno(ENOBUFS); + return -1; + } + conn->socket = i; + LWIP_DEBUGF(SOCKETS_DEBUG, ("%d\n", i)); + set_errno(0); + return i; +} + +int +lwip_write(int s, void *data, int size) +{ + return lwip_send(s, data, size, 0); +} + + +static int +lwip_selscan(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset) +{ + int i, nready = 0; + fd_set lreadset, lwriteset, lexceptset; + struct lwip_socket *p_sock; + + FD_ZERO(&lreadset); + FD_ZERO(&lwriteset); + FD_ZERO(&lexceptset); + + /* Go through each socket in each list to count number of sockets which + currently match */ + for(i = 0; i < maxfdp1; i++) + { + if (FD_ISSET(i, readset)) + { + /* See if netconn of this socket is ready for read */ + p_sock = get_socket(i); + if (p_sock && (p_sock->lastdata || p_sock->rcvevent)) + { + FD_SET(i, &lreadset); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_selscan: fd=%d ready for reading\n", i)); + nready++; + } + } + if (FD_ISSET(i, writeset)) + { + /* See if netconn of this socket is ready for write */ + p_sock = get_socket(i); + if (p_sock && p_sock->sendevent) + { + FD_SET(i, &lwriteset); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_selscan: fd=%d ready for writing\n", i)); + nready++; + } + } + } + *readset = lreadset; + *writeset = lwriteset; + FD_ZERO(exceptset); + + return nready; +} + + + +int +lwip_select(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset, + struct timeval *timeout) +{ + int i; + int nready; + fd_set lreadset, lwriteset, lexceptset; + u32_t msectimeout; + struct lwip_select_cb select_cb; + struct lwip_select_cb *p_selcb; + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select(%d, %p, %p, %p, tvsec=%ld tvusec=%ld)\n", maxfdp1, (void *)readset, (void *) writeset, (void *) exceptset, timeout ? timeout->tv_sec : -1L, timeout ? timeout->tv_usec : -1L)); + + select_cb.next = 0; + select_cb.readset = readset; + select_cb.writeset = writeset; + select_cb.exceptset = exceptset; + select_cb.sem_signalled = 0; + + /* Protect ourselves searching through the list */ + if (!selectsem) + selectsem = sys_sem_new(1); + sys_sem_wait(selectsem); + + if (readset) + lreadset = *readset; + else + FD_ZERO(&lreadset); + if (writeset) + lwriteset = *writeset; + else + FD_ZERO(&lwriteset); + if (exceptset) + lexceptset = *exceptset; + else + FD_ZERO(&lexceptset); + + /* Go through each socket in each list to count number of sockets which + currently match */ + nready = lwip_selscan(maxfdp1, &lreadset, &lwriteset, &lexceptset); + + /* If we don't have any current events, then suspend if we are supposed to */ + if (!nready) + { + if (timeout && timeout->tv_sec == 0 && timeout->tv_usec == 0) + { + sys_sem_signal(selectsem); + if (readset) + FD_ZERO(readset); + if (writeset) + FD_ZERO(writeset); + if (exceptset) + FD_ZERO(exceptset); + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: no timeout, returning 0\n")); + set_errno(0); + + return 0; + } + + /* add our semaphore to list */ + /* We don't actually need any dynamic memory. Our entry on the + * list is only valid while we are in this function, so it's ok + * to use local variables */ + + select_cb.sem = sys_sem_new(0); + /* Note that we are still protected */ + /* Put this select_cb on top of list */ + select_cb.next = select_cb_list; + select_cb_list = &select_cb; + + /* Now we can safely unprotect */ + sys_sem_signal(selectsem); + + /* Now just wait to be woken */ + if (timeout == 0) + /* Wait forever */ + msectimeout = 0; + else + msectimeout = ((timeout->tv_sec * 1000) + ((timeout->tv_usec + 500)/1000)); + + i = sys_sem_wait_timeout(select_cb.sem, msectimeout); + + /* Take us off the list */ + sys_sem_wait(selectsem); + if (select_cb_list == &select_cb) + select_cb_list = select_cb.next; + else + for (p_selcb = select_cb_list; p_selcb; p_selcb = p_selcb->next) + if (p_selcb->next == &select_cb) + { + p_selcb->next = select_cb.next; + break; + } + + sys_sem_signal(selectsem); + + sys_sem_free(select_cb.sem); + if (i == 0) /* Timeout */ + { + if (readset) + FD_ZERO(readset); + if (writeset) + FD_ZERO(writeset); + if (exceptset) + FD_ZERO(exceptset); + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: timeout expired\n")); + set_errno(0); + + return 0; + } + + if (readset) + lreadset = *readset; + else + FD_ZERO(&lreadset); + if (writeset) + lwriteset = *writeset; + else + FD_ZERO(&lwriteset); + if (exceptset) + lexceptset = *exceptset; + else + FD_ZERO(&lexceptset); + + /* See what's set */ + nready = lwip_selscan(maxfdp1, &lreadset, &lwriteset, &lexceptset); + } + else + sys_sem_signal(selectsem); + + if (readset) + *readset = lreadset; + if (writeset) + *writeset = lwriteset; + if (exceptset) + *exceptset = lexceptset; + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: nready=%d\n", nready)); + set_errno(0); + + return nready; +} + + +static void +event_callback(struct netconn *conn, enum netconn_evt evt, u16_t len) +{ + int s; + struct lwip_socket *sock; + struct lwip_select_cb *scb; + + /* Get socket */ + if (conn) + { + s = conn->socket; + if (s < 0) + { + /* Data comes in right away after an accept, even though + * the server task might not have created a new socket yet. + * Just count down (or up) if that's the case and we + * will use the data later. Note that only receive events + * can happen before the new socket is set up. */ + if (evt == NETCONN_EVT_RCVPLUS) + conn->socket--; + return; + } + + sock = get_socket(s); + if (!sock) + return; + } + else + return; + + if (!selectsem) + selectsem = sys_sem_new(1); + + sys_sem_wait(selectsem); + /* Set event as required */ + switch (evt) + { + case NETCONN_EVT_RCVPLUS: + sock->rcvevent++; + break; + case NETCONN_EVT_RCVMINUS: + sock->rcvevent--; + break; + case NETCONN_EVT_SENDPLUS: + sock->sendevent = 1; + break; + case NETCONN_EVT_SENDMINUS: + sock->sendevent = 0; + break; + } + sys_sem_signal(selectsem); + + /* Now decide if anyone is waiting for this socket */ + /* NOTE: This code is written this way to protect the select link list + but to avoid a deadlock situation by releasing socksem before + signalling for the select. This means we need to go through the list + multiple times ONLY IF a select was actually waiting. We go through + the list the number of waiting select calls + 1. This list is + expected to be small. */ + while (1) + { + sys_sem_wait(selectsem); + for (scb = select_cb_list; scb; scb = scb->next) + { + if (scb->sem_signalled == 0) + { + /* Test this select call for our socket */ + if (scb->readset && FD_ISSET(s, scb->readset)) + if (sock->rcvevent) + break; + if (scb->writeset && FD_ISSET(s, scb->writeset)) + if (sock->sendevent) + break; + } + } + if (scb) + { + scb->sem_signalled = 1; + sys_sem_signal(selectsem); + sys_sem_signal(scb->sem); + } else { + sys_sem_signal(selectsem); + break; + } + } + +} + + + + +int lwip_shutdown(int s, int how) +{ + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_shutdown(%d, how=%d)\n", s, how)); + return lwip_close(s); /* XXX temporary hack until proper implementation */ +} + +int lwip_getpeername (int s, struct sockaddr *name, socklen_t *namelen) +{ + struct lwip_socket *sock; + struct sockaddr_in sin; + struct ip_addr naddr; + + sock = get_socket(s); + if (!sock) { + set_errno(EBADF); + return -1; + } + + memset(&sin, 0, sizeof(sin)); + sin.sin_len = sizeof(sin); + sin.sin_family = AF_INET; + + /* get the IP address and port of the remote host */ + netconn_peer(sock->conn, &naddr, &sin.sin_port); + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getpeername(%d, addr=", s)); + ip_addr_debug_print(SOCKETS_DEBUG, &naddr); + LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%d)\n", sin.sin_port)); + + sin.sin_port = htons(sin.sin_port); + sin.sin_addr.s_addr = naddr.addr; + + if (*namelen > sizeof(sin)) + *namelen = sizeof(sin); + + memcpy(name, &sin, *namelen); + sock_set_errno(sock, 0); + return 0; +} + +int lwip_getsockname (int s, struct sockaddr *name, socklen_t *namelen) +{ + struct lwip_socket *sock; + struct sockaddr_in sin; + struct ip_addr *naddr; + + sock = get_socket(s); + if (!sock) { + set_errno(EBADF); + return -1; + } + + memset(&sin, 0, sizeof(sin)); + sin.sin_len = sizeof(sin); + sin.sin_family = AF_INET; + + /* get the IP address and port of the remote host */ + netconn_addr(sock->conn, &naddr, &sin.sin_port); + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockname(%d, addr=", s)); + ip_addr_debug_print(SOCKETS_DEBUG, naddr); + LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%d)\n", sin.sin_port)); + + sin.sin_port = htons(sin.sin_port); + sin.sin_addr.s_addr = naddr->addr; + + if (*namelen > sizeof(sin)) + *namelen = sizeof(sin); + + memcpy(name, &sin, *namelen); + sock_set_errno(sock, 0); + return 0; +} + +int lwip_getsockopt (int s, int level, int optname, void *optval, socklen_t *optlen) +{ + int err = 0; + struct lwip_socket *sock = get_socket(s); + + if(!sock) { + set_errno(EBADF); + return -1; + } + + if( NULL == optval || NULL == optlen ) { + sock_set_errno( sock, EFAULT ); + return -1; + } + + /* Do length and type checks for the various options first, to keep it readable. */ + switch( level ) { + +/* Level: SOL_SOCKET */ + case SOL_SOCKET: + switch(optname) { + + case SO_ACCEPTCONN: + case SO_BROADCAST: + /* UNIMPL case SO_DEBUG: */ + /* UNIMPL case SO_DONTROUTE: */ + case SO_ERROR: + case SO_KEEPALIVE: + /* UNIMPL case SO_OOBINLINE: */ + /* UNIMPL case SO_RCVBUF: */ + /* UNIMPL case SO_SNDBUF: */ + /* UNIMPL case SO_RCVLOWAT: */ + /* UNIMPL case SO_SNDLOWAT: */ +#if SO_REUSE + case SO_REUSEADDR: + case SO_REUSEPORT: +#endif /* SO_REUSE */ + case SO_TYPE: + /* UNIMPL case SO_USELOOPBACK: */ + if( *optlen < sizeof(int) ) { + err = EINVAL; + } + break; + + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, UNIMPL: optname=0x%x, ..)\n", s, optname)); + err = ENOPROTOOPT; + } /* switch */ + break; + +/* Level: IPPROTO_IP */ + case IPPROTO_IP: + switch(optname) { + /* UNIMPL case IP_HDRINCL: */ + /* UNIMPL case IP_RCVDSTADDR: */ + /* UNIMPL case IP_RCVIF: */ + case IP_TTL: + case IP_TOS: + if( *optlen < sizeof(int) ) { + err = EINVAL; + } + break; + + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, UNIMPL: optname=0x%x, ..)\n", s, optname)); + err = ENOPROTOOPT; + } /* switch */ + break; + +/* Level: IPPROTO_TCP */ + case IPPROTO_TCP: + if( *optlen < sizeof(int) ) { + err = EINVAL; + break; + } + + /* If this is no TCP socket, ignore any options. */ + if ( sock->conn->type != NETCONN_TCP ) return 0; + + switch( optname ) { + case TCP_NODELAY: + case TCP_KEEPALIVE: + break; + + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, UNIMPL: optname=0x%x, ..)\n", s, optname)); + err = ENOPROTOOPT; + } /* switch */ + break; + +/* UNDEFINED LEVEL */ + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, level=0x%x, UNIMPL: optname=0x%x, ..)\n", s, level, optname)); + err = ENOPROTOOPT; + } /* switch */ + + + if( 0 != err ) { + sock_set_errno(sock, err); + return -1; + } + + + + /* Now do the actual option processing */ + + switch(level) { + +/* Level: SOL_SOCKET */ + case SOL_SOCKET: + switch( optname ) { + + /* The option flags */ + case SO_ACCEPTCONN: + case SO_BROADCAST: + /* UNIMPL case SO_DEBUG: */ + /* UNIMPL case SO_DONTROUTE: */ + case SO_KEEPALIVE: + /* UNIMPL case SO_OOBINCLUDE: */ +#if SO_REUSE + case SO_REUSEADDR: + case SO_REUSEPORT: +#endif /* SO_REUSE */ + /*case SO_USELOOPBACK: UNIMPL */ + *(int*)optval = sock->conn->pcb.tcp->so_options & optname; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, optname=0x%x, ..) = %s\n", s, optname, (*(int*)optval?"on":"off"))); + break; + + case SO_TYPE: + switch (sock->conn->type) { + case NETCONN_RAW: + *(int*)optval = SOCK_RAW; + break; + case NETCONN_TCP: + *(int*)optval = SOCK_STREAM; + break; + case NETCONN_UDP: + case NETCONN_UDPLITE: + case NETCONN_UDPNOCHKSUM: + *(int*)optval = SOCK_DGRAM; + break; + default: /* unrecognized socket type */ + *(int*)optval = sock->conn->type; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_TYPE): unrecognized socket type %d\n", s, *(int *)optval)); + } /* switch */ + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_TYPE) = %d\n", s, *(int *)optval)); + break; + + case SO_ERROR: + *(int *)optval = sock->err; + sock->err = 0; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_ERROR) = %d\n", s, *(int *)optval)); + break; + } /* switch */ + break; + +/* Level: IPPROTO_IP */ + case IPPROTO_IP: + switch( optname ) { + case IP_TTL: + *(int*)optval = sock->conn->pcb.tcp->ttl; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_TTL) = %d\n", s, *(int *)optval)); + break; + case IP_TOS: + *(int*)optval = sock->conn->pcb.tcp->tos; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_TOS) = %d\n", s, *(int *)optval)); + break; + } /* switch */ + break; + +/* Level: IPPROTO_TCP */ + case IPPROTO_TCP: + switch( optname ) { + case TCP_NODELAY: + *(int*)optval = (sock->conn->pcb.tcp->flags & TF_NODELAY); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, TCP_NODELAY) = %s\n", s, (*(int*)optval)?"on":"off") ); + break; + case TCP_KEEPALIVE: + *(int*)optval = (int)sock->conn->pcb.tcp->keepalive; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, TCP_KEEPALIVE) = %d\n", s, *(int *)optval)); + break; + } /* switch */ + break; + } + + + sock_set_errno(sock, err); + return err ? -1 : 0; +} + +int lwip_setsockopt (int s, int level, int optname, const void *optval, socklen_t optlen) +{ + struct lwip_socket *sock = get_socket(s); + int err = 0; + + if(!sock) { + set_errno(EBADF); + return -1; + } + + if( NULL == optval ) { + sock_set_errno( sock, EFAULT ); + return -1; + } + + + /* Do length and type checks for the various options first, to keep it readable. */ + switch( level ) { + +/* Level: SOL_SOCKET */ + case SOL_SOCKET: + switch(optname) { + + case SO_BROADCAST: + /* UNIMPL case SO_DEBUG: */ + /* UNIMPL case SO_DONTROUTE: */ + case SO_KEEPALIVE: + /* UNIMPL case SO_OOBINLINE: */ + /* UNIMPL case SO_RCVBUF: */ + /* UNIMPL case SO_SNDBUF: */ + /* UNIMPL case SO_RCVLOWAT: */ + /* UNIMPL case SO_SNDLOWAT: */ +#if SO_REUSE + case SO_REUSEADDR: + case SO_REUSEPORT: +#endif /* SO_REUSE */ + /* UNIMPL case SO_USELOOPBACK: */ + if( optlen < sizeof(int) ) { + err = EINVAL; + } + break; + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, SOL_SOCKET, UNIMPL: optname=0x%x, ..)\n", s, optname)); + err = ENOPROTOOPT; + } /* switch */ + break; + +/* Level: IPPROTO_IP */ + case IPPROTO_IP: + switch(optname) { + /* UNIMPL case IP_HDRINCL: */ + /* UNIMPL case IP_RCVDSTADDR: */ + /* UNIMPL case IP_RCVIF: */ + case IP_TTL: + case IP_TOS: + if( optlen < sizeof(int) ) { + err = EINVAL; + } + break; + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, UNIMPL: optname=0x%x, ..)\n", s, optname)); + err = ENOPROTOOPT; + } /* switch */ + break; + +/* Level: IPPROTO_TCP */ + case IPPROTO_TCP: + if( optlen < sizeof(int) ) { + err = EINVAL; + break; + } + + /* If this is no TCP socket, ignore any options. */ + if ( sock->conn->type != NETCONN_TCP ) return 0; + + switch( optname ) { + case TCP_NODELAY: + case TCP_KEEPALIVE: + break; + + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, UNIMPL: optname=0x%x, ..)\n", s, optname)); + err = ENOPROTOOPT; + } /* switch */ + break; + +/* UNDEFINED LEVEL */ + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, level=0x%x, UNIMPL: optname=0x%x, ..)\n", s, level, optname)); + err = ENOPROTOOPT; + } /* switch */ + + + if( 0 != err ) { + sock_set_errno(sock, err); + return -1; + } + + + + /* Now do the actual option processing */ + + switch(level) { + +/* Level: SOL_SOCKET */ + case SOL_SOCKET: + switch(optname) { + + /* The option flags */ + case SO_BROADCAST: + /* UNIMPL case SO_DEBUG: */ + /* UNIMPL case SO_DONTROUTE: */ + case SO_KEEPALIVE: + /* UNIMPL case SO_OOBINCLUDE: */ +#if SO_REUSE + case SO_REUSEADDR: + case SO_REUSEPORT: +#endif /* SO_REUSE */ + /* UNIMPL case SO_USELOOPBACK: */ + if ( *(int*)optval ) { + sock->conn->pcb.tcp->so_options |= optname; + } else { + sock->conn->pcb.tcp->so_options &= ~optname; + } + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, SOL_SOCKET, optname=0x%x, ..) -> %s\n", s, optname, (*(int*)optval?"on":"off"))); + break; + } /* switch */ + break; + +/* Level: IPPROTO_IP */ + case IPPROTO_IP: + switch( optname ) { + case IP_TTL: + sock->conn->pcb.tcp->ttl = (u8_t)(*(int*)optval); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, IP_TTL, ..) -> %u\n", s, sock->conn->pcb.tcp->ttl)); + break; + case IP_TOS: + sock->conn->pcb.tcp->tos = (u8_t)(*(int*)optval); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, IP_TOS, ..)-> %u\n", s, sock->conn->pcb.tcp->tos)); + break; + } /* switch */ + break; + +/* Level: IPPROTO_TCP */ + case IPPROTO_TCP: + switch( optname ) { + case TCP_NODELAY: + if ( *(int*)optval ) { + sock->conn->pcb.tcp->flags |= TF_NODELAY; + } else { + sock->conn->pcb.tcp->flags &= ~TF_NODELAY; + } + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_NODELAY) -> %s\n", s, (*(int *)optval)?"on":"off") ); + break; + case TCP_KEEPALIVE: + sock->conn->pcb.tcp->keepalive = (u32_t)(*(int*)optval); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPALIVE) -> %lu\n", s, sock->conn->pcb.tcp->keepalive)); + break; + } /* switch */ + break; + } /* switch */ + + sock_set_errno(sock, err); + return err ? -1 : 0; +} + +int lwip_ioctl(int s, long cmd, void *argp) +{ + struct lwip_socket *sock = get_socket(s); + + if(!sock) { + set_errno(EBADF); + return -1; + } + + switch (cmd) { + case FIONREAD: + if (!argp) { + sock_set_errno(sock, EINVAL); + return -1; + } + + *((u16_t*)argp) = sock->conn->recv_avail; + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, FIONREAD, %p) = %u\n", s, argp, *((u16_t*)argp))); + sock_set_errno(sock, 0); + return 0; + + case FIONBIO: + if (argp && *(u32_t*)argp) + sock->flags |= O_NONBLOCK; + else + sock->flags &= ~O_NONBLOCK; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, FIONBIO, %d)\n", s, !!(sock->flags & O_NONBLOCK))); + sock_set_errno(sock, 0); + return 0; + + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, UNIMPL: 0x%lx, %p)\n", s, cmd, argp)); + sock_set_errno(sock, ENOSYS); /* not yet implemented */ + return -1; + } +} + diff --git a/20080212/Demo/Common/ethernet/lwIP/api/tcpip.c b/20080212/Demo/Common/ethernet/lwIP/api/tcpip.c new file mode 100644 index 000000000..db86cf4ca --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/api/tcpip.c @@ -0,0 +1,198 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" + +#include "lwip/sys.h" + +#include "lwip/memp.h" +#include "lwip/pbuf.h" + +#include "lwip/ip.h" +#include "lwip/ip_frag.h" +#include "lwip/udp.h" +#include "lwip/tcp.h" + +#include "lwip/tcpip.h" + +static void (* tcpip_init_done)(void *arg) = NULL; +static void *tcpip_init_done_arg; +static sys_mbox_t mbox; + +#if LWIP_TCP +static int tcpip_tcp_timer_active = 0; + +static void +tcpip_tcp_timer(void *arg) +{ + (void)arg; + + /* call TCP timer handler */ + tcp_tmr(); + /* timer still needed? */ + if (tcp_active_pcbs || tcp_tw_pcbs) { + /* restart timer */ + sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL); + } else { + /* disable timer */ + tcpip_tcp_timer_active = 0; + } +} + +#if !NO_SYS +void +tcp_timer_needed(void) +{ + /* timer is off but needed again? */ + if (!tcpip_tcp_timer_active && (tcp_active_pcbs || tcp_tw_pcbs)) { + /* enable and start timer */ + tcpip_tcp_timer_active = 1; + sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL); + } +} +#endif /* !NO_SYS */ +#endif /* LWIP_TCP */ + +#if IP_REASSEMBLY +static void +ip_timer(void *data) +{ + LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip: ip_reass_tmr()\n")); + ip_reass_tmr(); + sys_timeout(1000, ip_timer, NULL); +} +#endif + +static void +tcpip_thread(void *arg) +{ + struct tcpip_msg *msg; + + (void)arg; + + ip_init(); +#if LWIP_UDP + udp_init(); +#endif +#if LWIP_TCP + tcp_init(); +#endif +#if IP_REASSEMBLY + sys_timeout(1000, ip_timer, NULL); +#endif + if (tcpip_init_done != NULL) { + tcpip_init_done(tcpip_init_done_arg); + } + + while (1) { /* MAIN Loop */ + sys_mbox_fetch(mbox, (void *)&msg); + switch (msg->type) { + case TCPIP_MSG_API: + LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: API message %p\n", (void *)msg)); + api_msg_input(msg->msg.apimsg); + break; + case TCPIP_MSG_INPUT: + LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: IP packet %p\n", (void *)msg)); + ip_input(msg->msg.inp.p, msg->msg.inp.netif); + break; + case TCPIP_MSG_CALLBACK: + LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: CALLBACK %p\n", (void *)msg)); + msg->msg.cb.f(msg->msg.cb.ctx); + break; + default: + break; + } + memp_free(MEMP_TCPIP_MSG, msg); + } +} + +err_t +tcpip_input(struct pbuf *p, struct netif *inp) +{ + struct tcpip_msg *msg; + + msg = memp_malloc(MEMP_TCPIP_MSG); + if (msg == NULL) { + pbuf_free(p); + return ERR_MEM; + } + + msg->type = TCPIP_MSG_INPUT; + msg->msg.inp.p = p; + msg->msg.inp.netif = inp; + sys_mbox_post(mbox, msg); + return ERR_OK; +} + +err_t +tcpip_callback(void (*f)(void *ctx), void *ctx) +{ + struct tcpip_msg *msg; + + msg = memp_malloc(MEMP_TCPIP_MSG); + if (msg == NULL) { + return ERR_MEM; + } + + msg->type = TCPIP_MSG_CALLBACK; + msg->msg.cb.f = f; + msg->msg.cb.ctx = ctx; + sys_mbox_post(mbox, msg); + return ERR_OK; +} + +void +tcpip_apimsg(struct api_msg *apimsg) +{ + struct tcpip_msg *msg; + msg = memp_malloc(MEMP_TCPIP_MSG); + if (msg == NULL) { + memp_free(MEMP_API_MSG, apimsg); + return; + } + msg->type = TCPIP_MSG_API; + msg->msg.apimsg = apimsg; + sys_mbox_post(mbox, msg); +} + +void +tcpip_init(void (* initfunc)(void *), void *arg) +{ + tcpip_init_done = initfunc; + tcpip_init_done_arg = arg; + mbox = sys_mbox_new(); + sys_thread_new(tcpip_thread, NULL, TCPIP_THREAD_PRIO); +} + + + + diff --git a/20080212/Demo/Common/ethernet/lwIP/core/dhcp.c b/20080212/Demo/Common/ethernet/lwIP/core/dhcp.c new file mode 100644 index 000000000..47f65c2e2 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/core/dhcp.c @@ -0,0 +1,1464 @@ +/** + * @file + * + * Dynamic Host Configuration Protocol client + */ + +/* + * + * Copyright (c) 2001-2004 Leon Woestenberg + * Copyright (c) 2001-2004 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is a contribution to the lwIP TCP/IP stack. + * The Swedish Institute of Computer Science and Adam Dunkels + * are specifically granted permission to redistribute this + * source code. + * + * Author: Leon Woestenberg + * + * This is a DHCP client for the lwIP TCP/IP stack. It aims to conform + * with RFC 2131 and RFC 2132. + * + * TODO: + * - Proper parsing of DHCP messages exploiting file/sname field overloading. + * - Add JavaDoc style documentation (API, internals). + * - Support for interfaces other than Ethernet (SLIP, PPP, ...) + * + * Please coordinate changes and requests with Leon Woestenberg + * + * + * Integration with your code: + * + * In lwip/dhcp.h + * #define DHCP_COARSE_TIMER_SECS (recommended 60 which is a minute) + * #define DHCP_FINE_TIMER_MSECS (recommended 500 which equals TCP coarse timer) + * + * Then have your application call dhcp_coarse_tmr() and + * dhcp_fine_tmr() on the defined intervals. + * + * dhcp_start(struct netif *netif); + * starts a DHCP client instance which configures the interface by + * obtaining an IP address lease and maintaining it. + * + * Use dhcp_release(netif) to end the lease and use dhcp_stop(netif) + * to remove the DHCP client. + * + */ + +#include + +#include "lwip/stats.h" +#include "lwip/mem.h" +#include "lwip/udp.h" +#include "lwip/ip_addr.h" +#include "lwip/netif.h" +#include "lwip/inet.h" +#include "netif/etharp.h" + +#include "lwip/sys.h" +#include "lwip/opt.h" +#include "lwip/dhcp.h" + +#if LWIP_DHCP /* don't build if not configured for use in lwipopt.h */ + +/** global transaction identifier, must be + * unique for each DHCP request. We simply increment, starting + * with this value (easy to match with a packet analyzer) */ +static u32_t xid = 0xABCD0000; + +/** DHCP client state machine functions */ +static void dhcp_handle_ack(struct netif *netif); +static void dhcp_handle_nak(struct netif *netif); +static void dhcp_handle_offer(struct netif *netif); + +static err_t dhcp_discover(struct netif *netif); +static err_t dhcp_select(struct netif *netif); +static void dhcp_check(struct netif *netif); +static void dhcp_bind(struct netif *netif); +static err_t dhcp_decline(struct netif *netif); +static err_t dhcp_rebind(struct netif *netif); +static void dhcp_set_state(struct dhcp *dhcp, u8_t new_state); + +/** receive, unfold, parse and free incoming messages */ +static void dhcp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *addr, u16_t port); +static err_t dhcp_unfold_reply(struct dhcp *dhcp); +static u8_t *dhcp_get_option_ptr(struct dhcp *dhcp, u8_t option_type); +static u8_t dhcp_get_option_byte(u8_t *ptr); +#if 0 +static u16_t dhcp_get_option_short(u8_t *ptr); +#endif +static u32_t dhcp_get_option_long(u8_t *ptr); +static void dhcp_free_reply(struct dhcp *dhcp); + +/** set the DHCP timers */ +static void dhcp_timeout(struct netif *netif); +static void dhcp_t1_timeout(struct netif *netif); +static void dhcp_t2_timeout(struct netif *netif); + +/** build outgoing messages */ +/** create a DHCP request, fill in common headers */ +static err_t dhcp_create_request(struct netif *netif); +/** free a DHCP request */ +static void dhcp_delete_request(struct netif *netif); +/** add a DHCP option (type, then length in bytes) */ +static void dhcp_option(struct dhcp *dhcp, u8_t option_type, u8_t option_len); +/** add option values */ +static void dhcp_option_byte(struct dhcp *dhcp, u8_t value); +static void dhcp_option_short(struct dhcp *dhcp, u16_t value); +static void dhcp_option_long(struct dhcp *dhcp, u32_t value); +/** always add the DHCP options trailer to end and pad */ +static void dhcp_option_trailer(struct dhcp *dhcp); + +/** + * Back-off the DHCP client (because of a received NAK response). + * + * Back-off the DHCP client because of a received NAK. Receiving a + * NAK means the client asked for something non-sensible, for + * example when it tries to renew a lease obtained on another network. + * + * We back-off and will end up restarting a fresh DHCP negotiation later. + * + * @param state pointer to DHCP state structure + */ +static void dhcp_handle_nak(struct netif *netif) { + struct dhcp *dhcp = netif->dhcp; + u16_t msecs = 10 * 1000; + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_handle_nak(netif=%p) %c%c%"U16_F"\n", + (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); + dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_handle_nak(): set request timeout %"U16_F" msecs\n", msecs)); + dhcp_set_state(dhcp, DHCP_BACKING_OFF); +} + +/** + * Checks if the offered IP address is already in use. + * + * It does so by sending an ARP request for the offered address and + * entering CHECKING state. If no ARP reply is received within a small + * interval, the address is assumed to be free for use by us. + */ +static void dhcp_check(struct netif *netif) +{ + struct dhcp *dhcp = netif->dhcp; + err_t result; + u16_t msecs; + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_check(netif=%p) %c%c\n", (void *)netif, (s16_t)netif->name[0], + (s16_t)netif->name[1])); + /* create an ARP query for the offered IP address, expecting that no host + responds, as the IP address should not be in use. */ + result = etharp_query(netif, &dhcp->offered_ip_addr, NULL); + if (result != ERR_OK) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_check: could not perform ARP query\n")); + } + dhcp->tries++; + msecs = 500; + dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_check(): set request timeout %"U16_F" msecs\n", msecs)); + dhcp_set_state(dhcp, DHCP_CHECKING); +} + +/** + * Remember the configuration offered by a DHCP server. + * + * @param state pointer to DHCP state structure + */ +static void dhcp_handle_offer(struct netif *netif) +{ + struct dhcp *dhcp = netif->dhcp; + /* obtain the server address */ + u8_t *option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_SERVER_ID); + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_handle_offer(netif=%p) %c%c%"U16_F"\n", + (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); + if (option_ptr != NULL) + { + dhcp->server_ip_addr.addr = htonl(dhcp_get_option_long(&option_ptr[2])); + LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_handle_offer(): server 0x%08"X32_F"\n", dhcp->server_ip_addr.addr)); + /* remember offered address */ + ip_addr_set(&dhcp->offered_ip_addr, (struct ip_addr *)&dhcp->msg_in->yiaddr); + LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_handle_offer(): offer for 0x%08"X32_F"\n", dhcp->offered_ip_addr.addr)); + + dhcp_select(netif); + } +} + +/** + * Select a DHCP server offer out of all offers. + * + * Simply select the first offer received. + * + * @param netif the netif under DHCP control + * @return lwIP specific error (see error.h) + */ +static err_t dhcp_select(struct netif *netif) +{ + struct dhcp *dhcp = netif->dhcp; + err_t result; + u32_t msecs; + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_select(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); + + /* create and initialize the DHCP message header */ + result = dhcp_create_request(netif); + if (result == ERR_OK) + { + dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN); + dhcp_option_byte(dhcp, DHCP_REQUEST); + + dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); + dhcp_option_short(dhcp, 576); + + /* MUST request the offered IP address */ + dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4); + dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr)); + + dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4); + dhcp_option_long(dhcp, ntohl(dhcp->server_ip_addr.addr)); + + dhcp_option(dhcp, DHCP_OPTION_PARAMETER_REQUEST_LIST, 4/*num options*/); + dhcp_option_byte(dhcp, DHCP_OPTION_SUBNET_MASK); + dhcp_option_byte(dhcp, DHCP_OPTION_ROUTER); + dhcp_option_byte(dhcp, DHCP_OPTION_BROADCAST); + dhcp_option_byte(dhcp, DHCP_OPTION_DNS_SERVER); + + dhcp_option_trailer(dhcp); + /* shrink the pbuf to the actual content length */ + pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); + + /* TODO: we really should bind to a specific local interface here + but we cannot specify an unconfigured netif as it is addressless */ + udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT); + /* send broadcast to any DHCP server */ + udp_connect(dhcp->pcb, IP_ADDR_BROADCAST, DHCP_SERVER_PORT); + udp_send(dhcp->pcb, dhcp->p_out); + /* reconnect to any (or to server here?!) */ + udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT); + dhcp_delete_request(netif); + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_select: REQUESTING\n")); + dhcp_set_state(dhcp, DHCP_REQUESTING); + } else { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_select: could not allocate DHCP request\n")); + } + dhcp->tries++; + msecs = dhcp->tries < 4 ? dhcp->tries * 1000 : 4 * 1000; + dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; + LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_select(): set request timeout %"U32_F" msecs\n", msecs)); + return result; +} + +/** + * The DHCP timer that checks for lease renewal/rebind timeouts. + * + */ +void dhcp_coarse_tmr() +{ + struct netif *netif = netif_list; + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_coarse_tmr()\n")); + /* iterate through all network interfaces */ + while (netif != NULL) { + /* only act on DHCP configured interfaces */ + if (netif->dhcp != NULL) { + /* timer is active (non zero), and triggers (zeroes) now? */ + if (netif->dhcp->t2_timeout-- == 1) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_coarse_tmr(): t2 timeout\n")); + /* this clients' rebind timeout triggered */ + dhcp_t2_timeout(netif); + /* timer is active (non zero), and triggers (zeroes) now */ + } else if (netif->dhcp->t1_timeout-- == 1) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_coarse_tmr(): t1 timeout\n")); + /* this clients' renewal timeout triggered */ + dhcp_t1_timeout(netif); + } + } + /* proceed to next netif */ + netif = netif->next; + } +} + +/** + * DHCP transaction timeout handling + * + * A DHCP server is expected to respond within a short period of time. + * This timer checks whether an outstanding DHCP request is timed out. + * + */ +void dhcp_fine_tmr() +{ + struct netif *netif = netif_list; + /* loop through netif's */ + while (netif != NULL) { + /* only act on DHCP configured interfaces */ + if (netif->dhcp != NULL) { + /* timer is active (non zero), and is about to trigger now */ + if (netif->dhcp->request_timeout > 1) { + netif->dhcp->request_timeout--; + } + else if (netif->dhcp->request_timeout == 1) { + netif->dhcp->request_timeout--; + /* { netif->dhcp->request_timeout == 0 } */ + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_fine_tmr(): request timeout\n")); + /* this clients' request timeout triggered */ + dhcp_timeout(netif); + } + } + /* proceed to next network interface */ + netif = netif->next; + } +} + +/** + * A DHCP negotiation transaction, or ARP request, has timed out. + * + * The timer that was started with the DHCP or ARP request has + * timed out, indicating no response was received in time. + * + * @param netif the netif under DHCP control + * + */ +static void dhcp_timeout(struct netif *netif) +{ + struct dhcp *dhcp = netif->dhcp; + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_timeout()\n")); + /* back-off period has passed, or server selection timed out */ + if ((dhcp->state == DHCP_BACKING_OFF) || (dhcp->state == DHCP_SELECTING)) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_timeout(): restarting discovery\n")); + dhcp_discover(netif); + /* receiving the requested lease timed out */ + } else if (dhcp->state == DHCP_REQUESTING) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): REQUESTING, DHCP request timed out\n")); + if (dhcp->tries <= 5) { + dhcp_select(netif); + } else { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): REQUESTING, releasing, restarting\n")); + dhcp_release(netif); + dhcp_discover(netif); + } + /* received no ARP reply for the offered address (which is good) */ + } else if (dhcp->state == DHCP_CHECKING) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): CHECKING, ARP request timed out\n")); + if (dhcp->tries <= 1) { + dhcp_check(netif); + /* no ARP replies on the offered address, + looks like the IP address is indeed free */ + } else { + /* bind the interface to the offered address */ + dhcp_bind(netif); + } + } + /* did not get response to renew request? */ + else if (dhcp->state == DHCP_RENEWING) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): RENEWING, DHCP request timed out\n")); + /* just retry renewal */ + /* note that the rebind timer will eventually time-out if renew does not work */ + dhcp_renew(netif); + /* did not get response to rebind request? */ + } else if (dhcp->state == DHCP_REBINDING) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): REBINDING, DHCP request timed out\n")); + if (dhcp->tries <= 8) { + dhcp_rebind(netif); + } else { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): RELEASING, DISCOVERING\n")); + dhcp_release(netif); + dhcp_discover(netif); + } + } +} + +/** + * The renewal period has timed out. + * + * @param netif the netif under DHCP control + */ +static void dhcp_t1_timeout(struct netif *netif) +{ + struct dhcp *dhcp = netif->dhcp; + LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_t1_timeout()\n")); + if ((dhcp->state == DHCP_REQUESTING) || (dhcp->state == DHCP_BOUND) || (dhcp->state == DHCP_RENEWING)) { + /* just retry to renew - note that the rebind timer (t2) will + * eventually time-out if renew tries fail. */ + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_t1_timeout(): must renew\n")); + dhcp_renew(netif); + } +} + +/** + * The rebind period has timed out. + * + */ +static void dhcp_t2_timeout(struct netif *netif) +{ + struct dhcp *dhcp = netif->dhcp; + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_t2_timeout()\n")); + if ((dhcp->state == DHCP_REQUESTING) || (dhcp->state == DHCP_BOUND) || (dhcp->state == DHCP_RENEWING)) { + /* just retry to rebind */ + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_t2_timeout(): must rebind\n")); + dhcp_rebind(netif); + } +} + +/** + * + * @param netif the netif under DHCP control + */ +static void dhcp_handle_ack(struct netif *netif) +{ + struct dhcp *dhcp = netif->dhcp; + u8_t *option_ptr; + /* clear options we might not get from the ACK */ + dhcp->offered_sn_mask.addr = 0; + dhcp->offered_gw_addr.addr = 0; + dhcp->offered_bc_addr.addr = 0; + + /* lease time given? */ + option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_LEASE_TIME); + if (option_ptr != NULL) { + /* remember offered lease time */ + dhcp->offered_t0_lease = dhcp_get_option_long(option_ptr + 2); + } + /* renewal period given? */ + option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_T1); + if (option_ptr != NULL) { + /* remember given renewal period */ + dhcp->offered_t1_renew = dhcp_get_option_long(option_ptr + 2); + } else { + /* calculate safe periods for renewal */ + dhcp->offered_t1_renew = dhcp->offered_t0_lease / 2; + } + + /* renewal period given? */ + option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_T2); + if (option_ptr != NULL) { + /* remember given rebind period */ + dhcp->offered_t2_rebind = dhcp_get_option_long(option_ptr + 2); + } else { + /* calculate safe periods for rebinding */ + dhcp->offered_t2_rebind = dhcp->offered_t0_lease; + } + + /* (y)our internet address */ + ip_addr_set(&dhcp->offered_ip_addr, &dhcp->msg_in->yiaddr); + +/** + * Patch #1308 + * TODO: we must check if the file field is not overloaded by DHCP options! + */ +#if 0 + /* boot server address */ + ip_addr_set(&dhcp->offered_si_addr, &dhcp->msg_in->siaddr); + /* boot file name */ + if (dhcp->msg_in->file[0]) { + dhcp->boot_file_name = mem_malloc(strlen(dhcp->msg_in->file) + 1); + strcpy(dhcp->boot_file_name, dhcp->msg_in->file); + } +#endif + + /* subnet mask */ + option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_SUBNET_MASK); + /* subnet mask given? */ + if (option_ptr != NULL) { + dhcp->offered_sn_mask.addr = htonl(dhcp_get_option_long(&option_ptr[2])); + } + + /* gateway router */ + option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_ROUTER); + if (option_ptr != NULL) { + dhcp->offered_gw_addr.addr = htonl(dhcp_get_option_long(&option_ptr[2])); + } + + /* broadcast address */ + option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_BROADCAST); + if (option_ptr != NULL) { + dhcp->offered_bc_addr.addr = htonl(dhcp_get_option_long(&option_ptr[2])); + } + + /* DNS servers */ + option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_DNS_SERVER); + if (option_ptr != NULL) { + u8_t n; + dhcp->dns_count = dhcp_get_option_byte(&option_ptr[1]) / (u32_t)sizeof(struct ip_addr); + /* limit to at most DHCP_MAX_DNS DNS servers */ + if (dhcp->dns_count > DHCP_MAX_DNS) + dhcp->dns_count = DHCP_MAX_DNS; + for (n = 0; n < dhcp->dns_count; n++) { + dhcp->offered_dns_addr[n].addr = htonl(dhcp_get_option_long(&option_ptr[2 + n * 4])); + } + } +} + +/** + * Start DHCP negotiation for a network interface. + * + * If no DHCP client instance was attached to this interface, + * a new client is created first. If a DHCP client instance + * was already present, it restarts negotiation. + * + * @param netif The lwIP network interface + * @return lwIP error code + * - ERR_OK - No error + * - ERR_MEM - Out of memory + * + */ +err_t dhcp_start(struct netif *netif) +{ + struct dhcp *dhcp = netif->dhcp; + err_t result = ERR_OK; + + LWIP_ASSERT("netif != NULL", netif != NULL); + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_start(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); + netif->flags &= ~NETIF_FLAG_DHCP; + + /* no DHCP client attached yet? */ + if (dhcp == NULL) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): starting new DHCP client\n")); + dhcp = mem_malloc(sizeof(struct dhcp)); + if (dhcp == NULL) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): could not allocate dhcp\n")); + return ERR_MEM; + } + /* store this dhcp client in the netif */ + netif->dhcp = dhcp; + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): allocated dhcp")); + /* already has DHCP client attached */ + } else { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE | 3, ("dhcp_start(): restarting DHCP configuration\n")); + } + + /* clear data structure */ + memset(dhcp, 0, sizeof(struct dhcp)); + /* allocate UDP PCB */ + dhcp->pcb = udp_new(); + if (dhcp->pcb == NULL) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): could not obtain pcb\n")); + mem_free((void *)dhcp); + netif->dhcp = dhcp = NULL; + return ERR_MEM; + } + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): starting DHCP configuration\n")); + /* (re)start the DHCP negotiation */ + result = dhcp_discover(netif); + if (result != ERR_OK) { + /* free resources allocated above */ + dhcp_stop(netif); + return ERR_MEM; + } + netif->flags |= NETIF_FLAG_DHCP; + return result; +} + +/** + * Inform a DHCP server of our manual configuration. + * + * This informs DHCP servers of our fixed IP address configuration + * by sending an INFORM message. It does not involve DHCP address + * configuration, it is just here to be nice to the network. + * + * @param netif The lwIP network interface + * + */ +void dhcp_inform(struct netif *netif) +{ + struct dhcp *dhcp; + err_t result = ERR_OK; + dhcp = mem_malloc(sizeof(struct dhcp)); + if (dhcp == NULL) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_inform(): could not allocate dhcp\n")); + return; + } + netif->dhcp = dhcp; + memset(dhcp, 0, sizeof(struct dhcp)); + + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_inform(): allocated dhcp\n")); + dhcp->pcb = udp_new(); + if (dhcp->pcb == NULL) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_inform(): could not obtain pcb")); + mem_free((void *)dhcp); + return; + } + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_inform(): created new udp pcb\n")); + /* create and initialize the DHCP message header */ + result = dhcp_create_request(netif); + if (result == ERR_OK) { + + dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN); + dhcp_option_byte(dhcp, DHCP_INFORM); + + dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); + /* TODO: use netif->mtu ?! */ + dhcp_option_short(dhcp, 576); + + dhcp_option_trailer(dhcp); + + pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); + + udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT); + udp_connect(dhcp->pcb, IP_ADDR_BROADCAST, DHCP_SERVER_PORT); + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_inform: INFORMING\n")); + udp_send(dhcp->pcb, dhcp->p_out); + udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT); + dhcp_delete_request(netif); + } else { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_inform: could not allocate DHCP request\n")); + } + + if (dhcp != NULL) + { + if (dhcp->pcb != NULL) udp_remove(dhcp->pcb); + dhcp->pcb = NULL; + mem_free((void *)dhcp); + netif->dhcp = NULL; + } +} + +#if DHCP_DOES_ARP_CHECK +/** + * Match an ARP reply with the offered IP address. + * + * @param addr The IP address we received a reply from + * + */ +void dhcp_arp_reply(struct netif *netif, struct ip_addr *addr) +{ + LWIP_ASSERT("netif != NULL", netif != NULL); + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_arp_reply()\n")); + /* is a DHCP client doing an ARP check? */ + if ((netif->dhcp != NULL) && (netif->dhcp->state == DHCP_CHECKING)) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_arp_reply(): CHECKING, arp reply for 0x%08"X32_F"\n", addr->addr)); + /* did a host respond with the address we + were offered by the DHCP server? */ + if (ip_addr_cmp(addr, &netif->dhcp->offered_ip_addr)) { + /* we will not accept the offered address */ + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE | 1, ("dhcp_arp_reply(): arp reply matched with offered address, declining\n")); + dhcp_decline(netif); + } + } +} + +/** + * Decline an offered lease. + * + * Tell the DHCP server we do not accept the offered address. + * One reason to decline the lease is when we find out the address + * is already in use by another host (through ARP). + */ +static err_t dhcp_decline(struct netif *netif) +{ + struct dhcp *dhcp = netif->dhcp; + err_t result = ERR_OK; + u16_t msecs; + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_decline()\n")); + dhcp_set_state(dhcp, DHCP_BACKING_OFF); + /* create and initialize the DHCP message header */ + result = dhcp_create_request(netif); + if (result == ERR_OK) + { + dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN); + dhcp_option_byte(dhcp, DHCP_DECLINE); + + dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); + dhcp_option_short(dhcp, 576); + + dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4); + dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr)); + + dhcp_option_trailer(dhcp); + /* resize pbuf to reflect true size of options */ + pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); + + udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT); + /* @todo: should we really connect here? we are performing sendto() */ + udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT); + /* per section 4.4.4, broadcast DECLINE messages */ + udp_sendto(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT); + dhcp_delete_request(netif); + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_decline: BACKING OFF\n")); + } else { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_decline: could not allocate DHCP request\n")); + } + dhcp->tries++; + msecs = 10*1000; + dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_decline(): set request timeout %"U16_F" msecs\n", msecs)); + return result; +} +#endif + + +/** + * Start the DHCP process, discover a DHCP server. + * + */ +static err_t dhcp_discover(struct netif *netif) +{ + struct dhcp *dhcp = netif->dhcp; + err_t result = ERR_OK; + u16_t msecs; + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_discover()\n")); + ip_addr_set(&dhcp->offered_ip_addr, IP_ADDR_ANY); + /* create and initialize the DHCP message header */ + result = dhcp_create_request(netif); + if (result == ERR_OK) + { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_discover: making request\n")); + dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN); + dhcp_option_byte(dhcp, DHCP_DISCOVER); + + dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); + dhcp_option_short(dhcp, 576); + + dhcp_option(dhcp, DHCP_OPTION_PARAMETER_REQUEST_LIST, 4/*num options*/); + dhcp_option_byte(dhcp, DHCP_OPTION_SUBNET_MASK); + dhcp_option_byte(dhcp, DHCP_OPTION_ROUTER); + dhcp_option_byte(dhcp, DHCP_OPTION_BROADCAST); + dhcp_option_byte(dhcp, DHCP_OPTION_DNS_SERVER); + + dhcp_option_trailer(dhcp); + + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_discover: realloc()ing\n")); + pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); + + /* set receive callback function with netif as user data */ + udp_recv(dhcp->pcb, dhcp_recv, netif); + udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT); + udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT); + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_discover: sendto(DISCOVER, IP_ADDR_BROADCAST, DHCP_SERVER_PORT)\n")); + udp_sendto(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT); + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_discover: deleting()ing\n")); + dhcp_delete_request(netif); + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_discover: SELECTING\n")); + dhcp_set_state(dhcp, DHCP_SELECTING); + } else { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_discover: could not allocate DHCP request\n")); + } + dhcp->tries++; + msecs = dhcp->tries < 4 ? (dhcp->tries + 1) * 1000 : 10 * 1000; + dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_discover(): set request timeout %"U16_F" msecs\n", msecs)); + return result; +} + + +/** + * Bind the interface to the offered IP address. + * + * @param netif network interface to bind to the offered address + */ +static void dhcp_bind(struct netif *netif) +{ + struct dhcp *dhcp = netif->dhcp; + struct ip_addr sn_mask, gw_addr; + LWIP_ASSERT("dhcp_bind: netif != NULL", netif != NULL); + LWIP_ASSERT("dhcp_bind: dhcp != NULL", dhcp != NULL); + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_bind(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); + + /* temporary DHCP lease? */ + if (dhcp->offered_t1_renew != 0xffffffffUL) { + /* set renewal period timer */ + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_bind(): t1 renewal timer %"U32_F" secs\n", dhcp->offered_t1_renew)); + dhcp->t1_timeout = (dhcp->offered_t1_renew + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS; + if (dhcp->t1_timeout == 0) dhcp->t1_timeout = 1; + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t1_renew*1000)); + } + /* set renewal period timer */ + if (dhcp->offered_t2_rebind != 0xffffffffUL) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_bind(): t2 rebind timer %"U32_F" secs\n", dhcp->offered_t2_rebind)); + dhcp->t2_timeout = (dhcp->offered_t2_rebind + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS; + if (dhcp->t2_timeout == 0) dhcp->t2_timeout = 1; + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t2_rebind*1000)); + } + /* copy offered network mask */ + ip_addr_set(&sn_mask, &dhcp->offered_sn_mask); + + /* subnet mask not given? */ + /* TODO: this is not a valid check. what if the network mask is 0? */ + if (sn_mask.addr == 0) { + /* choose a safe subnet mask given the network class */ + u8_t first_octet = ip4_addr1(&sn_mask); + if (first_octet <= 127) sn_mask.addr = htonl(0xff000000); + else if (first_octet >= 192) sn_mask.addr = htonl(0xffffff00); + else sn_mask.addr = htonl(0xffff0000); + } + + ip_addr_set(&gw_addr, &dhcp->offered_gw_addr); + /* gateway address not given? */ + if (gw_addr.addr == 0) { + /* copy network address */ + gw_addr.addr = (dhcp->offered_ip_addr.addr & sn_mask.addr); + /* use first host address on network as gateway */ + gw_addr.addr |= htonl(0x00000001); + } + + LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_bind(): IP: 0x%08"X32_F"\n", dhcp->offered_ip_addr.addr)); + netif_set_ipaddr(netif, &dhcp->offered_ip_addr); + LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_bind(): SN: 0x%08"X32_F"\n", sn_mask.addr)); + netif_set_netmask(netif, &sn_mask); + LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_bind(): GW: 0x%08"X32_F"\n", gw_addr.addr)); + netif_set_gw(netif, &gw_addr); + /* bring the interface up */ + netif_set_up(netif); + /* netif is now bound to DHCP leased address */ + dhcp_set_state(dhcp, DHCP_BOUND); +} + +/** + * Renew an existing DHCP lease at the involved DHCP server. + * + * @param netif network interface which must renew its lease + */ +err_t dhcp_renew(struct netif *netif) +{ + struct dhcp *dhcp = netif->dhcp; + err_t result; + u16_t msecs; + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_renew()\n")); + dhcp_set_state(dhcp, DHCP_RENEWING); + + /* create and initialize the DHCP message header */ + result = dhcp_create_request(netif); + if (result == ERR_OK) { + + dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN); + dhcp_option_byte(dhcp, DHCP_REQUEST); + + dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); + /* TODO: use netif->mtu in some way */ + dhcp_option_short(dhcp, 576); + +#if 0 + dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4); + dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr)); +#endif + +#if 0 + dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4); + dhcp_option_long(dhcp, ntohl(dhcp->server_ip_addr.addr)); +#endif + /* append DHCP message trailer */ + dhcp_option_trailer(dhcp); + + pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); + + udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT); + udp_connect(dhcp->pcb, &dhcp->server_ip_addr, DHCP_SERVER_PORT); + udp_send(dhcp->pcb, dhcp->p_out); + dhcp_delete_request(netif); + + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_renew: RENEWING\n")); + } else { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_renew: could not allocate DHCP request\n")); + } + dhcp->tries++; + /* back-off on retries, but to a maximum of 20 seconds */ + msecs = dhcp->tries < 10 ? dhcp->tries * 2000 : 20 * 1000; + dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_renew(): set request timeout %"U16_F" msecs\n", msecs)); + return result; +} + +/** + * Rebind with a DHCP server for an existing DHCP lease. + * + * @param netif network interface which must rebind with a DHCP server + */ +static err_t dhcp_rebind(struct netif *netif) +{ + struct dhcp *dhcp = netif->dhcp; + err_t result; + u16_t msecs; + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_rebind()\n")); + dhcp_set_state(dhcp, DHCP_REBINDING); + + /* create and initialize the DHCP message header */ + result = dhcp_create_request(netif); + if (result == ERR_OK) + { + + dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN); + dhcp_option_byte(dhcp, DHCP_REQUEST); + + dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); + dhcp_option_short(dhcp, 576); + +#if 0 + dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4); + dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr)); + + dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4); + dhcp_option_long(dhcp, ntohl(dhcp->server_ip_addr.addr)); +#endif + + dhcp_option_trailer(dhcp); + + pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); + + /* set remote IP association to any DHCP server */ + udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT); + udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT); + /* broadcast to server */ + udp_sendto(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT); + dhcp_delete_request(netif); + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_rebind: REBINDING\n")); + } else { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_rebind: could not allocate DHCP request\n")); + } + dhcp->tries++; + msecs = dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000; + dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_rebind(): set request timeout %"U16_F" msecs\n", msecs)); + return result; +} + +/** + * Release a DHCP lease. + * + * @param netif network interface which must release its lease + */ +err_t dhcp_release(struct netif *netif) +{ + struct dhcp *dhcp = netif->dhcp; + err_t result; + u16_t msecs; + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_release()\n")); + + /* idle DHCP client */ + dhcp_set_state(dhcp, DHCP_OFF); + /* clean old DHCP offer */ + dhcp->server_ip_addr.addr = 0; + dhcp->offered_ip_addr.addr = dhcp->offered_sn_mask.addr = 0; + dhcp->offered_gw_addr.addr = dhcp->offered_bc_addr.addr = 0; + dhcp->offered_t0_lease = dhcp->offered_t1_renew = dhcp->offered_t2_rebind = 0; + dhcp->dns_count = 0; + + /* create and initialize the DHCP message header */ + result = dhcp_create_request(netif); + if (result == ERR_OK) { + dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN); + dhcp_option_byte(dhcp, DHCP_RELEASE); + + dhcp_option_trailer(dhcp); + + pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); + + udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT); + udp_connect(dhcp->pcb, &dhcp->server_ip_addr, DHCP_SERVER_PORT); + udp_send(dhcp->pcb, dhcp->p_out); + dhcp_delete_request(netif); + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_release: RELEASED, DHCP_OFF\n")); + } else { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_release: could not allocate DHCP request\n")); + } + dhcp->tries++; + msecs = dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000; + dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_release(): set request timeout %"U16_F" msecs\n", msecs)); + /* bring the interface down */ + netif_set_down(netif); + /* remove IP address from interface */ + netif_set_ipaddr(netif, IP_ADDR_ANY); + netif_set_gw(netif, IP_ADDR_ANY); + netif_set_netmask(netif, IP_ADDR_ANY); + + /* TODO: netif_down(netif); */ + return result; +} +/** + * Remove the DHCP client from the interface. + * + * @param netif The network interface to stop DHCP on + */ +void dhcp_stop(struct netif *netif) +{ + struct dhcp *dhcp = netif->dhcp; + LWIP_ASSERT("dhcp_stop: netif != NULL", netif != NULL); + + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_stop()\n")); + /* netif is DHCP configured? */ + if (dhcp != NULL) + { + if (dhcp->pcb != NULL) + { + udp_remove(dhcp->pcb); + dhcp->pcb = NULL; + } + if (dhcp->p != NULL) + { + pbuf_free(dhcp->p); + dhcp->p = NULL; + } + /* free unfolded reply */ + dhcp_free_reply(dhcp); + mem_free((void *)dhcp); + netif->dhcp = NULL; + } +} + +/* + * Set the DHCP state of a DHCP client. + * + * If the state changed, reset the number of tries. + * + * TODO: we might also want to reset the timeout here? + */ +static void dhcp_set_state(struct dhcp *dhcp, u8_t new_state) +{ + if (new_state != dhcp->state) + { + dhcp->state = new_state; + dhcp->tries = 0; + } +} + +/* + * Concatenate an option type and length field to the outgoing + * DHCP message. + * + */ +static void dhcp_option(struct dhcp *dhcp, u8_t option_type, u8_t option_len) +{ + LWIP_ASSERT("dhcp_option_short: dhcp->options_out_len + 2 + option_len <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 2 + option_len <= DHCP_OPTIONS_LEN); + dhcp->msg_out->options[dhcp->options_out_len++] = option_type; + dhcp->msg_out->options[dhcp->options_out_len++] = option_len; +} +/* + * Concatenate a single byte to the outgoing DHCP message. + * + */ +static void dhcp_option_byte(struct dhcp *dhcp, u8_t value) +{ + LWIP_ASSERT("dhcp_option_short: dhcp->options_out_len < DHCP_OPTIONS_LEN", dhcp->options_out_len < DHCP_OPTIONS_LEN); + dhcp->msg_out->options[dhcp->options_out_len++] = value; +} +static void dhcp_option_short(struct dhcp *dhcp, u16_t value) +{ + LWIP_ASSERT("dhcp_option_short: dhcp->options_out_len + 2 <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 2 <= DHCP_OPTIONS_LEN); + dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0xff00U) >> 8; + dhcp->msg_out->options[dhcp->options_out_len++] = value & 0x00ffU; +} +static void dhcp_option_long(struct dhcp *dhcp, u32_t value) +{ + LWIP_ASSERT("dhcp_option_long: dhcp->options_out_len + 4 <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 4 <= DHCP_OPTIONS_LEN); + dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0xff000000UL) >> 24; + dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0x00ff0000UL) >> 16; + dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0x0000ff00UL) >> 8; + dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0x000000ffUL); +} + +/** + * Extract the DHCP message and the DHCP options. + * + * Extract the DHCP message and the DHCP options, each into a contiguous + * piece of memory. As a DHCP message is variable sized by its options, + * and also allows overriding some fields for options, the easy approach + * is to first unfold the options into a conitguous piece of memory, and + * use that further on. + * + */ +static err_t dhcp_unfold_reply(struct dhcp *dhcp) +{ + struct pbuf *p = dhcp->p; + u8_t *ptr; + u16_t i; + u16_t j = 0; + LWIP_ASSERT("dhcp->p != NULL", dhcp->p != NULL); + /* free any left-overs from previous unfolds */ + dhcp_free_reply(dhcp); + /* options present? */ + if (dhcp->p->tot_len > (sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN)) + { + dhcp->options_in_len = dhcp->p->tot_len - (sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN); + dhcp->options_in = mem_malloc(dhcp->options_in_len); + if (dhcp->options_in == NULL) + { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_unfold_reply(): could not allocate dhcp->options\n")); + return ERR_MEM; + } + } + dhcp->msg_in = mem_malloc(sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN); + if (dhcp->msg_in == NULL) + { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_unfold_reply(): could not allocate dhcp->msg_in\n")); + mem_free((void *)dhcp->options_in); + dhcp->options_in = NULL; + return ERR_MEM; + } + + ptr = (u8_t *)dhcp->msg_in; + /* proceed through struct dhcp_msg */ + for (i = 0; i < sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN; i++) + { + *ptr++ = ((u8_t *)p->payload)[j++]; + /* reached end of pbuf? */ + if (j == p->len) + { + /* proceed to next pbuf in chain */ + p = p->next; + j = 0; + } + } + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_unfold_reply(): copied %"U16_F" bytes into dhcp->msg_in[]\n", i)); + if (dhcp->options_in != NULL) { + ptr = (u8_t *)dhcp->options_in; + /* proceed through options */ + for (i = 0; i < dhcp->options_in_len; i++) { + *ptr++ = ((u8_t *)p->payload)[j++]; + /* reached end of pbuf? */ + if (j == p->len) { + /* proceed to next pbuf in chain */ + p = p->next; + j = 0; + } + } + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_unfold_reply(): copied %"U16_F" bytes to dhcp->options_in[]\n", i)); + } + return ERR_OK; +} + +/** + * Free the incoming DHCP message including contiguous copy of + * its DHCP options. + * + */ +static void dhcp_free_reply(struct dhcp *dhcp) +{ + if (dhcp->msg_in != NULL) { + mem_free((void *)dhcp->msg_in); + dhcp->msg_in = NULL; + } + if (dhcp->options_in) { + mem_free((void *)dhcp->options_in); + dhcp->options_in = NULL; + dhcp->options_in_len = 0; + } + LWIP_DEBUGF(DHCP_DEBUG, ("dhcp_free_reply(): free'd\n")); +} + + +/** + * If an incoming DHCP message is in response to us, then trigger the state machine + */ +static void dhcp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *addr, u16_t port) +{ + struct netif *netif = (struct netif *)arg; + struct dhcp *dhcp = netif->dhcp; + struct dhcp_msg *reply_msg = (struct dhcp_msg *)p->payload; + u8_t *options_ptr; + u8_t msg_type; + u8_t i; + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_recv(pbuf = %p) from DHCP server %"U16_F".%"U16_F".%"U16_F".%"U16_F" port %"U16_F"\n", (void*)p, + (u16_t)(ntohl(addr->addr) >> 24 & 0xff), (u16_t)(ntohl(addr->addr) >> 16 & 0xff), + (u16_t)(ntohl(addr->addr) >> 8 & 0xff), (u16_t)(ntohl(addr->addr) & 0xff), port)); + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("pbuf->len = %"U16_F"\n", p->len)); + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("pbuf->tot_len = %"U16_F"\n", p->tot_len)); + /* prevent warnings about unused arguments */ + (void)pcb; (void)addr; (void)port; + dhcp->p = p; + /* TODO: check packet length before reading them */ + if (reply_msg->op != DHCP_BOOTREPLY) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("not a DHCP reply message, but type %"U16_F"\n", (u16_t)reply_msg->op)); + pbuf_free(p); + dhcp->p = NULL; + return; + } + /* iterate through hardware address and match against DHCP message */ + for (i = 0; i < netif->hwaddr_len; i++) { + if (netif->hwaddr[i] != reply_msg->chaddr[i]) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("netif->hwaddr[%"U16_F"]==%02"X16_F" != reply_msg->chaddr[%"U16_F"]==%02"X16_F"\n", + (u16_t)i, (u16_t)netif->hwaddr[i], (u16_t)i, (u16_t)reply_msg->chaddr[i])); + pbuf_free(p); + dhcp->p = NULL; + return; + } + } + /* match transaction ID against what we expected */ + if (ntohl(reply_msg->xid) != dhcp->xid) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("transaction id mismatch reply_msg->xid(%"X32_F")!=dhcp->xid(%"X32_F")\n",ntohl(reply_msg->xid),dhcp->xid)); + pbuf_free(p); + dhcp->p = NULL; + return; + } + /* option fields could be unfold? */ + if (dhcp_unfold_reply(dhcp) != ERR_OK) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("problem unfolding DHCP message - too short on memory?\n")); + pbuf_free(p); + dhcp->p = NULL; + return; + } + + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("searching DHCP_OPTION_MESSAGE_TYPE\n")); + /* obtain pointer to DHCP message type */ + options_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_MESSAGE_TYPE); + if (options_ptr == NULL) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("DHCP_OPTION_MESSAGE_TYPE option not found\n")); + pbuf_free(p); + dhcp->p = NULL; + return; + } + + /* read DHCP message type */ + msg_type = dhcp_get_option_byte(options_ptr + 2); + /* message type is DHCP ACK? */ + if (msg_type == DHCP_ACK) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("DHCP_ACK received\n")); + /* in requesting state? */ + if (dhcp->state == DHCP_REQUESTING) { + dhcp_handle_ack(netif); + dhcp->request_timeout = 0; +#if DHCP_DOES_ARP_CHECK + /* check if the acknowledged lease address is already in use */ + dhcp_check(netif); +#else + /* bind interface to the acknowledged lease address */ + dhcp_bind(netif); +#endif + } + /* already bound to the given lease address? */ + else if ((dhcp->state == DHCP_REBOOTING) || (dhcp->state == DHCP_REBINDING) || (dhcp->state == DHCP_RENEWING)) { + dhcp->request_timeout = 0; + dhcp_bind(netif); + } + } + /* received a DHCP_NAK in appropriate state? */ + else if ((msg_type == DHCP_NAK) && + ((dhcp->state == DHCP_REBOOTING) || (dhcp->state == DHCP_REQUESTING) || + (dhcp->state == DHCP_REBINDING) || (dhcp->state == DHCP_RENEWING ))) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("DHCP_NAK received\n")); + dhcp->request_timeout = 0; + dhcp_handle_nak(netif); + } + /* received a DHCP_OFFER in DHCP_SELECTING state? */ + else if ((msg_type == DHCP_OFFER) && (dhcp->state == DHCP_SELECTING)) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("DHCP_OFFER received in DHCP_SELECTING state\n")); + dhcp->request_timeout = 0; + /* remember offered lease */ + dhcp_handle_offer(netif); + } + pbuf_free(p); + dhcp->p = NULL; +} + + +static err_t dhcp_create_request(struct netif *netif) +{ + struct dhcp *dhcp = netif->dhcp; + u16_t i; + LWIP_ASSERT("dhcp_create_request: dhcp->p_out == NULL", dhcp->p_out == NULL); + LWIP_ASSERT("dhcp_create_request: dhcp->msg_out == NULL", dhcp->msg_out == NULL); + dhcp->p_out = pbuf_alloc(PBUF_TRANSPORT, sizeof(struct dhcp_msg), PBUF_RAM); + if (dhcp->p_out == NULL) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_create_request(): could not allocate pbuf\n")); + return ERR_MEM; + } + /* give unique transaction identifier to this request */ + dhcp->xid = xid++; + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("transaction id xid++(%"X32_F") dhcp->xid(%"U32_F")\n",xid,dhcp->xid)); + + dhcp->msg_out = (struct dhcp_msg *)dhcp->p_out->payload; + + dhcp->msg_out->op = DHCP_BOOTREQUEST; + /* TODO: make link layer independent */ + dhcp->msg_out->htype = DHCP_HTYPE_ETH; + /* TODO: make link layer independent */ + dhcp->msg_out->hlen = DHCP_HLEN_ETH; + dhcp->msg_out->hops = 0; + dhcp->msg_out->xid = htonl(dhcp->xid); + dhcp->msg_out->secs = 0; + dhcp->msg_out->flags = 0; + dhcp->msg_out->ciaddr.addr = netif->ip_addr.addr; + dhcp->msg_out->yiaddr.addr = 0; + dhcp->msg_out->siaddr.addr = 0; + dhcp->msg_out->giaddr.addr = 0; + for (i = 0; i < DHCP_CHADDR_LEN; i++) { + /* copy netif hardware address, pad with zeroes */ + dhcp->msg_out->chaddr[i] = (i < netif->hwaddr_len) ? netif->hwaddr[i] : 0/* pad byte*/; + } + for (i = 0; i < DHCP_SNAME_LEN; i++) dhcp->msg_out->sname[i] = 0; + for (i = 0; i < DHCP_FILE_LEN; i++) dhcp->msg_out->file[i] = 0; + dhcp->msg_out->cookie = htonl(0x63825363UL); + dhcp->options_out_len = 0; + /* fill options field with an incrementing array (for debugging purposes) */ + for (i = 0; i < DHCP_OPTIONS_LEN; i++) dhcp->msg_out->options[i] = i; + return ERR_OK; +} + +static void dhcp_delete_request(struct netif *netif) +{ + struct dhcp *dhcp = netif->dhcp; + LWIP_ASSERT("dhcp_free_msg: dhcp->p_out != NULL", dhcp->p_out != NULL); + LWIP_ASSERT("dhcp_free_msg: dhcp->msg_out != NULL", dhcp->msg_out != NULL); + pbuf_free(dhcp->p_out); + dhcp->p_out = NULL; + dhcp->msg_out = NULL; +} + +/** + * Add a DHCP message trailer + * + * Adds the END option to the DHCP message, and if + * necessary, up to three padding bytes. + */ + +static void dhcp_option_trailer(struct dhcp *dhcp) +{ + LWIP_ASSERT("dhcp_option_trailer: dhcp->msg_out != NULL\n", dhcp->msg_out != NULL); + LWIP_ASSERT("dhcp_option_trailer: dhcp->options_out_len < DHCP_OPTIONS_LEN\n", dhcp->options_out_len < DHCP_OPTIONS_LEN); + dhcp->msg_out->options[dhcp->options_out_len++] = DHCP_OPTION_END; + /* packet is too small, or not 4 byte aligned? */ + while ((dhcp->options_out_len < DHCP_MIN_OPTIONS_LEN) || (dhcp->options_out_len & 3)) { + /* LWIP_DEBUGF(DHCP_DEBUG,("dhcp_option_trailer:dhcp->options_out_len=%"U16_F", DHCP_OPTIONS_LEN=%"U16_F, dhcp->options_out_len, DHCP_OPTIONS_LEN)); */ + LWIP_ASSERT("dhcp_option_trailer: dhcp->options_out_len < DHCP_OPTIONS_LEN\n", dhcp->options_out_len < DHCP_OPTIONS_LEN); + /* add a fill/padding byte */ + dhcp->msg_out->options[dhcp->options_out_len++] = 0; + } +} + +/** + * Find the offset of a DHCP option inside the DHCP message. + * + * @param client DHCP client + * @param option_type + * + * @return a byte offset into the UDP message where the option was found, or + * zero if the given option was not found. + */ +static u8_t *dhcp_get_option_ptr(struct dhcp *dhcp, u8_t option_type) +{ + u8_t overload = DHCP_OVERLOAD_NONE; + + /* options available? */ + if ((dhcp->options_in != NULL) && (dhcp->options_in_len > 0)) { + /* start with options field */ + u8_t *options = (u8_t *)dhcp->options_in; + u16_t offset = 0; + /* at least 1 byte to read and no end marker, then at least 3 bytes to read? */ + while ((offset < dhcp->options_in_len) && (options[offset] != DHCP_OPTION_END)) { + /* LWIP_DEBUGF(DHCP_DEBUG, ("msg_offset=%"U16_F", q->len=%"U16_F, msg_offset, q->len)); */ + /* are the sname and/or file field overloaded with options? */ + if (options[offset] == DHCP_OPTION_OVERLOAD) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("overloaded message detected\n")); + /* skip option type and length */ + offset += 2; + overload = options[offset++]; + } + /* requested option found */ + else if (options[offset] == option_type) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("option found at offset %"U16_F" in options\n", offset)); + return &options[offset]; + /* skip option */ + } else { + LWIP_DEBUGF(DHCP_DEBUG, ("skipping option %"U16_F" in options\n", options[offset])); + /* skip option type */ + offset++; + /* skip option length, and then length bytes */ + offset += 1 + options[offset]; + } + } + /* is this an overloaded message? */ + if (overload != DHCP_OVERLOAD_NONE) { + u16_t field_len; + if (overload == DHCP_OVERLOAD_FILE) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("overloaded file field\n")); + options = (u8_t *)&dhcp->msg_in->file; + field_len = DHCP_FILE_LEN; + } else if (overload == DHCP_OVERLOAD_SNAME) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("overloaded sname field\n")); + options = (u8_t *)&dhcp->msg_in->sname; + field_len = DHCP_SNAME_LEN; + /* TODO: check if else if () is necessary */ + } else { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("overloaded sname and file field\n")); + options = (u8_t *)&dhcp->msg_in->sname; + field_len = DHCP_FILE_LEN + DHCP_SNAME_LEN; + } + offset = 0; + + /* at least 1 byte to read and no end marker */ + while ((offset < field_len) && (options[offset] != DHCP_OPTION_END)) { + if (options[offset] == option_type) { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("option found at offset=%"U16_F"\n", offset)); + return &options[offset]; + /* skip option */ + } else { + LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("skipping option %"U16_F"\n", options[offset])); + /* skip option type */ + offset++; + offset += 1 + options[offset]; + } + } + } + } + return NULL; +} + +/** + * Return the byte of DHCP option data. + * + * @param client DHCP client. + * @param ptr pointer obtained by dhcp_get_option_ptr(). + * + * @return byte value at the given address. + */ +static u8_t dhcp_get_option_byte(u8_t *ptr) +{ + LWIP_DEBUGF(DHCP_DEBUG, ("option byte value=%"U16_F"\n", (u16_t)(*ptr))); + return *ptr; +} + +#if 0 +/** + * Return the 16-bit value of DHCP option data. + * + * @param client DHCP client. + * @param ptr pointer obtained by dhcp_get_option_ptr(). + * + * @return byte value at the given address. + */ +static u16_t dhcp_get_option_short(u8_t *ptr) +{ + u16_t value; + value = *ptr++ << 8; + value |= *ptr; + LWIP_DEBUGF(DHCP_DEBUG, ("option short value=%"U16_F"\n", value)); + return value; +} +#endif + +/** + * Return the 32-bit value of DHCP option data. + * + * @param client DHCP client. + * @param ptr pointer obtained by dhcp_get_option_ptr(). + * + * @return byte value at the given address. + */ +static u32_t dhcp_get_option_long(u8_t *ptr) +{ + u32_t value; + value = (u32_t)(*ptr++) << 24; + value |= (u32_t)(*ptr++) << 16; + value |= (u32_t)(*ptr++) << 8; + value |= (u32_t)(*ptr++); + LWIP_DEBUGF(DHCP_DEBUG, ("option long value=%"U32_F"\n", value)); + return value; +} + +#endif /* LWIP_DHCP */ diff --git a/20080212/Demo/Common/ethernet/lwIP/core/inet.c b/20080212/Demo/Common/ethernet/lwIP/core/inet.c new file mode 100644 index 000000000..d9d52c543 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/core/inet.c @@ -0,0 +1,537 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + + +/* inet.c + * + * Functions common to all TCP/IP modules, such as the Internet checksum and the + * byte order functions. + * + */ + + +#include "lwip/opt.h" + +#include "lwip/arch.h" + +#include "lwip/def.h" +#include "lwip/inet.h" + +#include "lwip/sys.h" + +/* These are some reference implementations of the checksum algorithm, with the + * aim of being simple, correct and fully portable. Checksumming is the + * first thing you would want to optimize for your platform. If you create + * your own version, link it in and in your sys_arch.h put: + * + * #define LWIP_CHKSUM +*/ +#ifndef LWIP_CHKSUM +#define LWIP_CHKSUM lwip_standard_chksum + +#if 1 /* Version A */ +/** + * lwip checksum + * + * @param dataptr points to start of data to be summed at any boundary + * @param len length of data to be summed + * @return host order (!) lwip checksum (non-inverted Internet sum) + * + * @note accumulator size limits summable length to 64k + * @note host endianess is irrelevant (p3 RFC1071) + */ +static u16_t +lwip_standard_chksum(void *dataptr, u16_t len) +{ + u32_t acc; + u16_t src; + u8_t *octetptr; + + acc = 0; + /* dataptr may be at odd or even addresses */ + octetptr = (u8_t*)dataptr; + while (len > 1) + { + /* declare first octet as most significant + thus assume network order, ignoring host order */ + src = (*octetptr) << 8; + octetptr++; + /* declare second octet as least significant */ + src |= (*octetptr); + octetptr++; + acc += src; + len -= 2; + } + if (len > 0) + { + /* accumulate remaining octet */ + src = (*octetptr) << 8; + acc += src; + } + /* add deferred carry bits */ + acc = (acc >> 16) + (acc & 0x0000ffffUL); + if ((acc & 0xffff0000) != 0) { + acc = (acc >> 16) + (acc & 0x0000ffffUL); + } + /* This maybe a little confusing: reorder sum using htons() + instead of ntohs() since it has a little less call overhead. + The caller must invert bits for Internet sum ! */ + return htons((u16_t)acc); +} +#endif + +#if 0 /* Version B */ +/* + * Curt McDowell + * Broadcom Corp. + * csm@broadcom.com + * + * IP checksum two bytes at a time with support for + * unaligned buffer. + * Works for len up to and including 0x20000. + * by Curt McDowell, Broadcom Corp. 12/08/2005 + */ + +static u16_t +lwip_standard_chksum(void *dataptr, int len) +{ + u8_t *pb = dataptr; + u16_t *ps, t = 0; + u32_t sum = 0; + int odd = ((u32_t)pb & 1); + + /* Get aligned to u16_t */ + if (odd && len > 0) { + ((u8_t *)&t)[1] = *pb++; + len--; + } + + /* Add the bulk of the data */ + ps = (u16_t *)pb; + while (len > 1) { + sum += *ps++; + len -= 2; + } + + /* Consume left-over byte, if any */ + if (len > 0) + ((u8_t *)&t)[0] = *(u8_t *)ps;; + + /* Add end bytes */ + sum += t; + + /* Fold 32-bit sum to 16 bits */ + while (sum >> 16) + sum = (sum & 0xffff) + (sum >> 16); + + /* Swap if alignment was odd */ + if (odd) + sum = ((sum & 0xff) << 8) | ((sum & 0xff00) >> 8); + + return sum; +} +#endif + +#if 0 /* Version C */ +/** + * An optimized checksum routine. Basically, it uses loop-unrolling on + * the checksum loop, treating the head and tail bytes specially, whereas + * the inner loop acts on 8 bytes at a time. + * + * @arg start of buffer to be checksummed. May be an odd byte address. + * @len number of bytes in the buffer to be checksummed. + * + * by Curt McDowell, Broadcom Corp. December 8th, 2005 + */ + +static u16_t +lwip_standard_chksum(void *dataptr, int len) +{ + u8_t *pb = dataptr; + u16_t *ps, t = 0; + u32_t *pl; + u32_t sum = 0, tmp; + /* starts at odd byte address? */ + int odd = ((u32_t)pb & 1); + + if (odd && len > 0) { + ((u8_t *)&t)[1] = *pb++; + len--; + } + + ps = (u16_t *)pb; + + if (((u32_t)ps & 3) && len > 1) { + sum += *ps++; + len -= 2; + } + + pl = (u32_t *)ps; + + while (len > 7) { + tmp = sum + *pl++; /* ping */ + if (tmp < sum) + tmp++; /* add back carry */ + + sum = tmp + *pl++; /* pong */ + if (sum < tmp) + sum++; /* add back carry */ + + len -= 8; + } + + /* make room in upper bits */ + sum = (sum >> 16) + (sum & 0xffff); + + ps = (u16_t *)pl; + + /* 16-bit aligned word remaining? */ + while (len > 1) { + sum += *ps++; + len -= 2; + } + + /* dangling tail byte remaining? */ + if (len > 0) /* include odd byte */ + ((u8_t *)&t)[0] = *(u8_t *)ps; + + sum += t; /* add end bytes */ + + while (sum >> 16) /* combine halves */ + sum = (sum >> 16) + (sum & 0xffff); + + if (odd) + sum = ((sum & 0xff) << 8) | ((sum & 0xff00) >> 8); + + return sum; +} +#endif + +#endif /* LWIP_CHKSUM */ + +/* inet_chksum_pseudo: + * + * Calculates the pseudo Internet checksum used by TCP and UDP for a pbuf chain. + */ + +u16_t +inet_chksum_pseudo(struct pbuf *p, + struct ip_addr *src, struct ip_addr *dest, + u8_t proto, u16_t proto_len) +{ + u32_t acc; + struct pbuf *q; + u8_t swapped; + + acc = 0; + swapped = 0; + /* iterate through all pbuf in chain */ + for(q = p; q != NULL; q = q->next) { + LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): checksumming pbuf %p (has next %p) \n", + (void *)q, (void *)q->next)); + acc += LWIP_CHKSUM(q->payload, q->len); + /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): unwrapped lwip_chksum()=%"X32_F" \n", acc));*/ + while (acc >> 16) { + acc = (acc & 0xffffUL) + (acc >> 16); + } + if (q->len % 2 != 0) { + swapped = 1 - swapped; + acc = ((acc & 0xff) << 8) | ((acc & 0xff00UL) >> 8); + } + /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): wrapped lwip_chksum()=%"X32_F" \n", acc));*/ + } + + if (swapped) { + acc = ((acc & 0xff) << 8) | ((acc & 0xff00UL) >> 8); + } + acc += (src->addr & 0xffffUL); + acc += ((src->addr >> 16) & 0xffffUL); + acc += (dest->addr & 0xffffUL); + acc += ((dest->addr >> 16) & 0xffffUL); + acc += (u32_t)htons((u16_t)proto); + acc += (u32_t)htons(proto_len); + + while (acc >> 16) { + acc = (acc & 0xffffUL) + (acc >> 16); + } + LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): pbuf chain lwip_chksum()=%"X32_F"\n", acc)); + return (u16_t)~(acc & 0xffffUL); +} + +/* inet_chksum: + * + * Calculates the Internet checksum over a portion of memory. Used primarily for IP + * and ICMP. + */ + +u16_t +inet_chksum(void *dataptr, u16_t len) +{ + u32_t acc; + + acc = LWIP_CHKSUM(dataptr, len); + while (acc >> 16) { + acc = (acc & 0xffff) + (acc >> 16); + } + return (u16_t)~(acc & 0xffff); +} + +u16_t +inet_chksum_pbuf(struct pbuf *p) +{ + u32_t acc; + struct pbuf *q; + u8_t swapped; + + acc = 0; + swapped = 0; + for(q = p; q != NULL; q = q->next) { + acc += LWIP_CHKSUM(q->payload, q->len); + while (acc >> 16) { + acc = (acc & 0xffffUL) + (acc >> 16); + } + if (q->len % 2 != 0) { + swapped = 1 - swapped; + acc = (acc & 0x00ffUL << 8) | (acc & 0xff00UL >> 8); + } + } + + if (swapped) { + acc = ((acc & 0x00ffUL) << 8) | ((acc & 0xff00UL) >> 8); + } + return (u16_t)~(acc & 0xffffUL); +} + +/* Here for now until needed in other places in lwIP */ +#ifndef isprint +#define in_range(c, lo, up) ((u8_t)c >= lo && (u8_t)c <= up) +#define isprint(c) in_range(c, 0x20, 0x7f) +#define isdigit(c) in_range(c, '0', '9') +#define isxdigit(c) (isdigit(c) || in_range(c, 'a', 'f') || in_range(c, 'A', 'F')) +#define islower(c) in_range(c, 'a', 'z') +#define isspace(c) (c == ' ' || c == '\f' || c == '\n' || c == '\r' || c == '\t' || c == '\v') +#endif + +/* + * Ascii internet address interpretation routine. + * The value returned is in network order. + */ + +u32_t +inet_addr(const char *cp) +{ + struct in_addr val; + + if (inet_aton(cp, &val)) { + return (val.s_addr); + } + return (INADDR_NONE); +} + +/* + * Check whether "cp" is a valid ascii representation + * of an Internet address and convert to a binary address. + * Returns 1 if the address is valid, 0 if not. + * This replaces inet_addr, the return value from which + * cannot distinguish between failure and a local broadcast address. + */ +int +inet_aton(const char *cp, struct in_addr *addr) +{ + u32_t val; + int base, n, c; + u32_t parts[4]; + u32_t *pp = parts; + + c = *cp; + for (;;) { + /* + * Collect number up to ``.''. + * Values are specified as for C: + * 0x=hex, 0=octal, 1-9=decimal. + */ + if (!isdigit(c)) + return (0); + val = 0; + base = 10; + if (c == '0') { + c = *++cp; + if (c == 'x' || c == 'X') { + base = 16; + c = *++cp; + } else + base = 8; + } + for (;;) { + if (isdigit(c)) { + val = (val * base) + (int)(c - '0'); + c = *++cp; + } else if (base == 16 && isxdigit(c)) { + val = (val << 4) | (int)(c + 10 - (islower(c) ? 'a' : 'A')); + c = *++cp; + } else + break; + } + if (c == '.') { + /* + * Internet format: + * a.b.c.d + * a.b.c (with c treated as 16 bits) + * a.b (with b treated as 24 bits) + */ + if (pp >= parts + 3) + return (0); + *pp++ = val; + c = *++cp; + } else + break; + } + /* + * Check for trailing characters. + */ + if (c != '\0' && (!isprint(c) || !isspace(c))) + return (0); + /* + * Concoct the address according to + * the number of parts specified. + */ + n = pp - parts + 1; + switch (n) { + + case 0: + return (0); /* initial nondigit */ + + case 1: /* a -- 32 bits */ + break; + + case 2: /* a.b -- 8.24 bits */ + if (val > 0xffffff) + return (0); + val |= parts[0] << 24; + break; + + case 3: /* a.b.c -- 8.8.16 bits */ + if (val > 0xffff) + return (0); + val |= (parts[0] << 24) | (parts[1] << 16); + break; + + case 4: /* a.b.c.d -- 8.8.8.8 bits */ + if (val > 0xff) + return (0); + val |= (parts[0] << 24) | (parts[1] << 16) | (parts[2] << 8); + break; + } + if (addr) + addr->s_addr = htonl(val); + return (1); +} + +/* Convert numeric IP address into decimal dotted ASCII representation. + * returns ptr to static buffer; not reentrant! + */ +char * +inet_ntoa(struct in_addr addr) +{ + static char str[16]; + u32_t s_addr = addr.s_addr; + char inv[3]; + char *rp; + u8_t *ap; + u8_t rem; + u8_t n; + u8_t i; + + rp = str; + ap = (u8_t *)&s_addr; + for(n = 0; n < 4; n++) { + i = 0; + do { + rem = *ap % (u8_t)10; + *ap /= (u8_t)10; + inv[i++] = '0' + rem; + } while(*ap); + while(i--) + *rp++ = inv[i]; + *rp++ = '.'; + ap++; + } + *--rp = 0; + return str; +} + +/* + * These are reference implementations of the byte swapping functions. + * Again with the aim of being simple, correct and fully portable. + * Byte swapping is the second thing you would want to optimize. You will + * need to port it to your architecture and in your cc.h: + * + * #define LWIP_PLATFORM_BYTESWAP 1 + * #define LWIP_PLATFORM_HTONS(x) + * #define LWIP_PLATFORM_HTONL(x) + * + * Note ntohs() and ntohl() are merely references to the htonx counterparts. + */ + +#ifndef BYTE_ORDER +#error BYTE_ORDER is not defined +#endif +#if (LWIP_PLATFORM_BYTESWAP == 0) && (BYTE_ORDER == LITTLE_ENDIAN) + +u16_t +htons(u16_t n) +{ + return ((n & 0xff) << 8) | ((n & 0xff00) >> 8); +} + +u16_t +ntohs(u16_t n) +{ + return htons(n); +} + +u32_t +htonl(u32_t n) +{ + return ((n & 0xff) << 24) | + ((n & 0xff00) << 8) | + ((n & 0xff0000) >> 8) | + ((n & 0xff000000) >> 24); +} + +u32_t +ntohl(u32_t n) +{ + return htonl(n); +} + +#endif /* (LWIP_PLATFORM_BYTESWAP == 0) && (BYTE_ORDER == LITTLE_ENDIAN) */ diff --git a/20080212/Demo/Common/ethernet/lwIP/core/inet6.c b/20080212/Demo/Common/ethernet/lwIP/core/inet6.c new file mode 100644 index 000000000..aebc6f381 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/core/inet6.c @@ -0,0 +1,168 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + + +/* inet6.c + * + * Functions common to all TCP/IP modules, such as the Internet checksum and the + * byte order functions. + * + */ + + +#include "lwip/opt.h" + +#include "lwip/def.h" +#include "lwip/inet.h" + + + +/* chksum: + * + * Sums up all 16 bit words in a memory portion. Also includes any odd byte. + * This function is used by the other checksum functions. + * + * For now, this is not optimized. Must be optimized for the particular processor + * arcitecture on which it is to run. Preferebly coded in assembler. + */ + +static u32_t +chksum(void *dataptr, u16_t len) +{ + u16_t *sdataptr = dataptr; + u32_t acc; + + + for(acc = 0; len > 1; len -= 2) { + acc += *sdataptr++; + } + + /* add up any odd byte */ + if (len == 1) { + acc += htons((u16_t)(*(u8_t *)dataptr) << 8); + } + + return acc; + +} + +/* inet_chksum_pseudo: + * + * Calculates the pseudo Internet checksum used by TCP and UDP for a pbuf chain. + */ + +u16_t +inet_chksum_pseudo(struct pbuf *p, + struct ip_addr *src, struct ip_addr *dest, + u8_t proto, u32_t proto_len) +{ + u32_t acc; + struct pbuf *q; + u8_t swapped, i; + + acc = 0; + swapped = 0; + for(q = p; q != NULL; q = q->next) { + acc += chksum(q->payload, q->len); + while (acc >> 16) { + acc = (acc & 0xffff) + (acc >> 16); + } + if (q->len % 2 != 0) { + swapped = 1 - swapped; + acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8); + } + } + + if (swapped) { + acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8); + } + + for(i = 0; i < 8; i++) { + acc += ((u16_t *)src->addr)[i] & 0xffff; + acc += ((u16_t *)dest->addr)[i] & 0xffff; + while (acc >> 16) { + acc = (acc & 0xffff) + (acc >> 16); + } + } + acc += (u16_t)htons((u16_t)proto); + acc += ((u16_t *)&proto_len)[0] & 0xffff; + acc += ((u16_t *)&proto_len)[1] & 0xffff; + + while (acc >> 16) { + acc = (acc & 0xffff) + (acc >> 16); + } + return ~(acc & 0xffff); +} + +/* inet_chksum: + * + * Calculates the Internet checksum over a portion of memory. Used primarely for IP + * and ICMP. + */ + +u16_t +inet_chksum(void *dataptr, u16_t len) +{ + u32_t acc, sum; + + acc = chksum(dataptr, len); + sum = (acc & 0xffff) + (acc >> 16); + sum += (sum >> 16); + return ~(sum & 0xffff); +} + +u16_t +inet_chksum_pbuf(struct pbuf *p) +{ + u32_t acc; + struct pbuf *q; + u8_t swapped; + + acc = 0; + swapped = 0; + for(q = p; q != NULL; q = q->next) { + acc += chksum(q->payload, q->len); + while (acc >> 16) { + acc = (acc & 0xffff) + (acc >> 16); + } + if (q->len % 2 != 0) { + swapped = 1 - swapped; + acc = (acc & 0xff << 8) | (acc & 0xff00 >> 8); + } + } + + if (swapped) { + acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8); + } + return ~(acc & 0xffff); +} + diff --git a/20080212/Demo/Common/ethernet/lwIP/core/ipv4/icmp.c b/20080212/Demo/Common/ethernet/lwIP/core/ipv4/icmp.c new file mode 100644 index 000000000..e4028b18f --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/core/ipv4/icmp.c @@ -0,0 +1,202 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +/* Some ICMP messages should be passed to the transport protocols. This + is not implemented. */ + +#include + +#include "lwip/opt.h" +#include "lwip/icmp.h" +#include "lwip/inet.h" +#include "lwip/ip.h" +#include "lwip/def.h" +#include "lwip/stats.h" +#include "lwip/snmp.h" + +void +icmp_input(struct pbuf *p, struct netif *inp) +{ + u8_t type; + u8_t code; + struct icmp_echo_hdr *iecho; + struct ip_hdr *iphdr; + struct ip_addr tmpaddr; + u16_t hlen; + + ICMP_STATS_INC(icmp.recv); + snmp_inc_icmpinmsgs(); + + + iphdr = p->payload; + hlen = IPH_HL(iphdr) * 4; + if (pbuf_header(p, -((s16_t)hlen)) || (p->tot_len < sizeof(u16_t)*2)) { + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: short ICMP (%"U16_F" bytes) received\n", p->tot_len)); + pbuf_free(p); + ICMP_STATS_INC(icmp.lenerr); + snmp_inc_icmpinerrors(); + return; + } + + type = *((u8_t *)p->payload); + code = *(((u8_t *)p->payload)+1); + switch (type) { + case ICMP_ECHO: + /* broadcast or multicast destination address? */ + if (ip_addr_isbroadcast(&iphdr->dest, inp) || ip_addr_ismulticast(&iphdr->dest)) { + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: Not echoing to multicast or broadcast pings\n")); + ICMP_STATS_INC(icmp.err); + pbuf_free(p); + return; + } + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ping\n")); + if (p->tot_len < sizeof(struct icmp_echo_hdr)) { + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: bad ICMP echo received\n")); + pbuf_free(p); + ICMP_STATS_INC(icmp.lenerr); + snmp_inc_icmpinerrors(); + + return; + } + iecho = p->payload; + if (inet_chksum_pbuf(p) != 0) { + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo\n")); + pbuf_free(p); + ICMP_STATS_INC(icmp.chkerr); + snmp_inc_icmpinerrors(); + return; + } + tmpaddr.addr = iphdr->src.addr; + iphdr->src.addr = iphdr->dest.addr; + iphdr->dest.addr = tmpaddr.addr; + ICMPH_TYPE_SET(iecho, ICMP_ER); + /* adjust the checksum */ + if (iecho->chksum >= htons(0xffff - (ICMP_ECHO << 8))) { + iecho->chksum += htons(ICMP_ECHO << 8) + 1; + } else { + iecho->chksum += htons(ICMP_ECHO << 8); + } + ICMP_STATS_INC(icmp.xmit); + /* increase number of messages attempted to send */ + snmp_inc_icmpoutmsgs(); + /* increase number of echo replies attempted to send */ + snmp_inc_icmpoutechoreps(); + + pbuf_header(p, hlen); + ip_output_if(p, &(iphdr->src), IP_HDRINCL, + IPH_TTL(iphdr), 0, IP_PROTO_ICMP, inp); + break; + default: + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ICMP type %"S16_F" code %"S16_F" not supported.\n", (s16_t)type, (s16_t)code)); + ICMP_STATS_INC(icmp.proterr); + ICMP_STATS_INC(icmp.drop); + } + pbuf_free(p); +} + +void +icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t) +{ + struct pbuf *q; + struct ip_hdr *iphdr; + struct icmp_dur_hdr *idur; + + q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM); + /* ICMP header + IP header + 8 bytes of data */ + + iphdr = p->payload; + + idur = q->payload; + ICMPH_TYPE_SET(idur, ICMP_DUR); + ICMPH_CODE_SET(idur, t); + + memcpy((u8_t *)q->payload + 8, p->payload, IP_HLEN + 8); + + /* calculate checksum */ + idur->chksum = 0; + idur->chksum = inet_chksum(idur, q->len); + ICMP_STATS_INC(icmp.xmit); + /* increase number of messages attempted to send */ + snmp_inc_icmpoutmsgs(); + /* increase number of destination unreachable messages attempted to send */ + snmp_inc_icmpoutdestunreachs(); + + ip_output(q, NULL, &(iphdr->src), + ICMP_TTL, 0, IP_PROTO_ICMP); + pbuf_free(q); +} + +#if IP_FORWARD +void +icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t) +{ + struct pbuf *q; + struct ip_hdr *iphdr; + struct icmp_te_hdr *tehdr; + + q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM); + + iphdr = p->payload; + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded from ")); + ip_addr_debug_print(ICMP_DEBUG, &(iphdr->src)); + LWIP_DEBUGF(ICMP_DEBUG, (" to ")); + ip_addr_debug_print(ICMP_DEBUG, &(iphdr->dest)); + LWIP_DEBUGF(ICMP_DEBUG, ("\n")); + + tehdr = q->payload; + ICMPH_TYPE_SET(tehdr, ICMP_TE); + ICMPH_CODE_SET(tehdr, t); + + /* copy fields from original packet */ + memcpy((u8_t *)q->payload + 8, (u8_t *)p->payload, IP_HLEN + 8); + + /* calculate checksum */ + tehdr->chksum = 0; + tehdr->chksum = inet_chksum(tehdr, q->len); + ICMP_STATS_INC(icmp.xmit); + /* increase number of messages attempted to send */ + snmp_inc_icmpoutmsgs(); + /* increase number of destination unreachable messages attempted to send */ + snmp_inc_icmpouttimeexcds(); + ip_output(q, NULL, &(iphdr->src), + ICMP_TTL, 0, IP_PROTO_ICMP); + pbuf_free(q); +} + +#endif /* IP_FORWARD */ + + + + + + + diff --git a/20080212/Demo/Common/ethernet/lwIP/core/ipv4/ip.c b/20080212/Demo/Common/ethernet/lwIP/core/ipv4/ip.c new file mode 100644 index 000000000..31d29a98c --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/core/ipv4/ip.c @@ -0,0 +1,515 @@ +/* @file + * + * This is the IP layer implementation for incoming and outgoing IP traffic. + * + * @see ip_frag.c + * + */ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" + +#include "lwip/def.h" +#include "lwip/mem.h" +#include "lwip/ip.h" +#include "lwip/ip_frag.h" +#include "lwip/inet.h" +#include "lwip/netif.h" +#include "lwip/icmp.h" +#include "lwip/raw.h" +#include "lwip/udp.h" +#include "lwip/tcp.h" + +#include "lwip/stats.h" + +#include "arch/perf.h" + +#include "lwip/snmp.h" +#if LWIP_DHCP +# include "lwip/dhcp.h" +#endif /* LWIP_DHCP */ + +/** + * Initializes the IP layer. + */ + +void +ip_init(void) +{ +#if IP_FRAG + ip_frag_init(); +#endif +} + +/** + * Finds the appropriate network interface for a given IP address. It + * searches the list of network interfaces linearly. A match is found + * if the masked IP address of the network interface equals the masked + * IP address given to the function. + */ + +struct netif * +ip_route(struct ip_addr *dest) +{ + struct netif *netif; + + /* iterate through netifs */ + for(netif = netif_list; netif != NULL; netif = netif->next) { + /* network mask matches? */ + if (ip_addr_netcmp(dest, &(netif->ip_addr), &(netif->netmask))) { + /* return netif on which to forward IP packet */ + return netif; + } + } + /* no matching netif found, use default netif */ + return netif_default; +} +#if IP_FORWARD + +/** + * Forwards an IP packet. It finds an appropriate route for the + * packet, decrements the TTL value of the packet, adjusts the + * checksum and outputs the packet on the appropriate interface. + */ + +static struct netif * +ip_forward(struct pbuf *p, struct ip_hdr *iphdr, struct netif *inp) +{ + struct netif *netif; + + PERF_START; + /* Find network interface where to forward this IP packet to. */ + netif = ip_route((struct ip_addr *)&(iphdr->dest)); + if (netif == NULL) { + LWIP_DEBUGF(IP_DEBUG, ("ip_forward: no forwarding route for 0x%"X32_F" found\n", + iphdr->dest.addr)); + snmp_inc_ipoutnoroutes(); + return (struct netif *)NULL; + } + /* Do not forward packets onto the same network interface on which + * they arrived. */ + if (netif == inp) { + LWIP_DEBUGF(IP_DEBUG, ("ip_forward: not bouncing packets back on incoming interface.\n")); + snmp_inc_ipoutnoroutes(); + return (struct netif *)NULL; + } + + /* decrement TTL */ + IPH_TTL_SET(iphdr, IPH_TTL(iphdr) - 1); + /* send ICMP if TTL == 0 */ + if (IPH_TTL(iphdr) == 0) { + snmp_inc_ipinhdrerrors(); + /* Don't send ICMP messages in response to ICMP messages */ + if (IPH_PROTO(iphdr) != IP_PROTO_ICMP) { + icmp_time_exceeded(p, ICMP_TE_TTL); + } + return (struct netif *)NULL; + } + + /* Incrementally update the IP checksum. */ + if (IPH_CHKSUM(iphdr) >= htons(0xffff - 0x100)) { + IPH_CHKSUM_SET(iphdr, IPH_CHKSUM(iphdr) + htons(0x100) + 1); + } else { + IPH_CHKSUM_SET(iphdr, IPH_CHKSUM(iphdr) + htons(0x100)); + } + + LWIP_DEBUGF(IP_DEBUG, ("ip_forward: forwarding packet to 0x%"X32_F"\n", + iphdr->dest.addr)); + + IP_STATS_INC(ip.fw); + IP_STATS_INC(ip.xmit); + snmp_inc_ipforwdatagrams(); + + PERF_STOP("ip_forward"); + /* transmit pbuf on chosen interface */ + netif->output(netif, p, (struct ip_addr *)&(iphdr->dest)); + return netif; +} +#endif /* IP_FORWARD */ + +/** + * This function is called by the network interface device driver when + * an IP packet is received. The function does the basic checks of the + * IP header such as packet size being at least larger than the header + * size etc. If the packet was not destined for us, the packet is + * forwarded (using ip_forward). The IP checksum is always checked. + * + * Finally, the packet is sent to the upper layer protocol input function. + * + * + * + */ + +err_t +ip_input(struct pbuf *p, struct netif *inp) { + struct ip_hdr *iphdr; + struct netif *netif; + u16_t iphdrlen; + + IP_STATS_INC(ip.recv); + snmp_inc_ipinreceives(); + + /* identify the IP header */ + iphdr = p->payload; + if (IPH_V(iphdr) != 4) { + LWIP_DEBUGF(IP_DEBUG | 1, ("IP packet dropped due to bad version number %"U16_F"\n", IPH_V(iphdr))); + ip_debug_print(p); + pbuf_free(p); + IP_STATS_INC(ip.err); + IP_STATS_INC(ip.drop); + snmp_inc_ipinhdrerrors(); + return ERR_OK; + } + /* obtain IP header length in number of 32-bit words */ + iphdrlen = IPH_HL(iphdr); + /* calculate IP header length in bytes */ + iphdrlen *= 4; + + /* header length exceeds first pbuf length? */ + if (iphdrlen > p->len) { + LWIP_DEBUGF(IP_DEBUG | 2, ("IP header (len %"U16_F") does not fit in first pbuf (len %"U16_F"), IP packet droppped.\n", + iphdrlen, p->len)); + /* free (drop) packet pbufs */ + pbuf_free(p); + IP_STATS_INC(ip.lenerr); + IP_STATS_INC(ip.drop); + snmp_inc_ipindiscards(); + return ERR_OK; + } + + /* verify checksum */ +#if CHECKSUM_CHECK_IP + if (inet_chksum(iphdr, iphdrlen) != 0) { + + LWIP_DEBUGF(IP_DEBUG | 2, ("Checksum (0x%"X16_F") failed, IP packet dropped.\n", inet_chksum(iphdr, iphdrlen))); + ip_debug_print(p); + pbuf_free(p); + IP_STATS_INC(ip.chkerr); + IP_STATS_INC(ip.drop); + snmp_inc_ipinhdrerrors(); + return ERR_OK; + } +#endif + + /* Trim pbuf. This should have been done at the netif layer, + * but we'll do it anyway just to be sure that its done. */ + pbuf_realloc(p, ntohs(IPH_LEN(iphdr))); + + /* match packet against an interface, i.e. is this packet for us? */ + for (netif = netif_list; netif != NULL; netif = netif->next) { + + LWIP_DEBUGF(IP_DEBUG, ("ip_input: iphdr->dest 0x%"X32_F" netif->ip_addr 0x%"X32_F" (0x%"X32_F", 0x%"X32_F", 0x%"X32_F")\n", + iphdr->dest.addr, netif->ip_addr.addr, + iphdr->dest.addr & netif->netmask.addr, + netif->ip_addr.addr & netif->netmask.addr, + iphdr->dest.addr & ~(netif->netmask.addr))); + + /* interface is up and configured? */ + if ((netif_is_up(netif)) && (!ip_addr_isany(&(netif->ip_addr)))) + { + /* unicast to this interface address? */ + if (ip_addr_cmp(&(iphdr->dest), &(netif->ip_addr)) || + /* or broadcast on this interface network address? */ + ip_addr_isbroadcast(&(iphdr->dest), netif)) { + LWIP_DEBUGF(IP_DEBUG, ("ip_input: packet accepted on interface %c%c\n", + netif->name[0], netif->name[1])); + /* break out of for loop */ + break; + } + } + } +#if LWIP_DHCP + /* Pass DHCP messages regardless of destination address. DHCP traffic is addressed + * using link layer addressing (such as Ethernet MAC) so we must not filter on IP. + * According to RFC 1542 section 3.1.1, referred by RFC 2131). + */ + if (netif == NULL) { + /* remote port is DHCP server? */ + if (IPH_PROTO(iphdr) == IP_PROTO_UDP) { + LWIP_DEBUGF(IP_DEBUG | DBG_TRACE | 1, ("ip_input: UDP packet to DHCP client port %"U16_F"\n", + ntohs(((struct udp_hdr *)((u8_t *)iphdr + iphdrlen))->dest))); + if (ntohs(((struct udp_hdr *)((u8_t *)iphdr + iphdrlen))->dest) == DHCP_CLIENT_PORT) { + LWIP_DEBUGF(IP_DEBUG | DBG_TRACE | 1, ("ip_input: DHCP packet accepted.\n")); + netif = inp; + } + } + } +#endif /* LWIP_DHCP */ + /* packet not for us? */ + if (netif == NULL) { + /* packet not for us, route or discard */ + LWIP_DEBUGF(IP_DEBUG | DBG_TRACE | 1, ("ip_input: packet not for us.\n")); +#if IP_FORWARD + /* non-broadcast packet? */ + if (!ip_addr_isbroadcast(&(iphdr->dest), inp)) { + /* try to forward IP packet on (other) interfaces */ + ip_forward(p, iphdr, inp); + } + else +#endif /* IP_FORWARD */ + { + snmp_inc_ipinaddrerrors(); + snmp_inc_ipindiscards(); + } + pbuf_free(p); + return ERR_OK; + } + /* packet consists of multiple fragments? */ + if ((IPH_OFFSET(iphdr) & htons(IP_OFFMASK | IP_MF)) != 0) { +#if IP_REASSEMBLY /* packet fragment reassembly code present? */ + LWIP_DEBUGF(IP_DEBUG, ("IP packet is a fragment (id=0x%04"X16_F" tot_len=%"U16_F" len=%"U16_F" MF=%"U16_F" offset=%"U16_F"), calling ip_reass()\n", + ntohs(IPH_ID(iphdr)), p->tot_len, ntohs(IPH_LEN(iphdr)), !!(IPH_OFFSET(iphdr) & htons(IP_MF)), (ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK)*8)); + /* reassemble the packet*/ + p = ip_reass(p); + /* packet not fully reassembled yet? */ + if (p == NULL) { + return ERR_OK; + } + iphdr = p->payload; +#else /* IP_REASSEMBLY == 0, no packet fragment reassembly code present */ + pbuf_free(p); + LWIP_DEBUGF(IP_DEBUG | 2, ("IP packet dropped since it was fragmented (0x%"X16_F") (while IP_REASSEMBLY == 0).\n", + ntohs(IPH_OFFSET(iphdr)))); + IP_STATS_INC(ip.opterr); + IP_STATS_INC(ip.drop); + /* unsupported protocol feature */ + snmp_inc_ipinunknownprotos(); + return ERR_OK; +#endif /* IP_REASSEMBLY */ + } + +#if IP_OPTIONS == 0 /* no support for IP options in the IP header? */ + if (iphdrlen > IP_HLEN) { + LWIP_DEBUGF(IP_DEBUG | 2, ("IP packet dropped since there were IP options (while IP_OPTIONS == 0).\n")); + pbuf_free(p); + IP_STATS_INC(ip.opterr); + IP_STATS_INC(ip.drop); + /* unsupported protocol feature */ + snmp_inc_ipinunknownprotos(); + return ERR_OK; + } +#endif /* IP_OPTIONS == 0 */ + + /* send to upper layers */ + LWIP_DEBUGF(IP_DEBUG, ("ip_input: \n")); + ip_debug_print(p); + LWIP_DEBUGF(IP_DEBUG, ("ip_input: p->len %"U16_F" p->tot_len %"U16_F"\n", p->len, p->tot_len)); + +#if LWIP_RAW + /* raw input did not eat the packet? */ + if (raw_input(p, inp) == 0) { +#endif /* LWIP_RAW */ + + switch (IPH_PROTO(iphdr)) { +#if LWIP_UDP + case IP_PROTO_UDP: + case IP_PROTO_UDPLITE: + snmp_inc_ipindelivers(); + udp_input(p, inp); + break; +#endif /* LWIP_UDP */ +#if LWIP_TCP + case IP_PROTO_TCP: + snmp_inc_ipindelivers(); + tcp_input(p, inp); + break; +#endif /* LWIP_TCP */ + case IP_PROTO_ICMP: + snmp_inc_ipindelivers(); + icmp_input(p, inp); + break; + default: + /* send ICMP destination protocol unreachable unless is was a broadcast */ + if (!ip_addr_isbroadcast(&(iphdr->dest), inp) && + !ip_addr_ismulticast(&(iphdr->dest))) { + p->payload = iphdr; + icmp_dest_unreach(p, ICMP_DUR_PROTO); + } + pbuf_free(p); + + LWIP_DEBUGF(IP_DEBUG | 2, ("Unsupported transport protocol %"U16_F"\n", IPH_PROTO(iphdr))); + + IP_STATS_INC(ip.proterr); + IP_STATS_INC(ip.drop); + snmp_inc_ipinunknownprotos(); + } +#if LWIP_RAW + } /* LWIP_RAW */ +#endif + return ERR_OK; +} + +/** + * Sends an IP packet on a network interface. This function constructs + * the IP header and calculates the IP header checksum. If the source + * IP address is NULL, the IP address of the outgoing network + * interface is filled in as source address. + * + * @note ip_id: RFC791 "some host may be able to simply use + * unique identifiers independent of destination" + */ + +err_t +ip_output_if(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, + u8_t ttl, u8_t tos, + u8_t proto, struct netif *netif) +{ + struct ip_hdr *iphdr; + static u16_t ip_id = 0; + + snmp_inc_ipoutrequests(); + + if (dest != IP_HDRINCL) { + if (pbuf_header(p, IP_HLEN)) { + LWIP_DEBUGF(IP_DEBUG | 2, ("ip_output: not enough room for IP header in pbuf\n")); + + IP_STATS_INC(ip.err); + snmp_inc_ipoutdiscards(); + return ERR_BUF; + } + + iphdr = p->payload; + + IPH_TTL_SET(iphdr, ttl); + IPH_PROTO_SET(iphdr, proto); + + ip_addr_set(&(iphdr->dest), dest); + + IPH_VHLTOS_SET(iphdr, 4, IP_HLEN / 4, tos); + IPH_LEN_SET(iphdr, htons(p->tot_len)); + IPH_OFFSET_SET(iphdr, htons(IP_DF)); + IPH_ID_SET(iphdr, htons(ip_id)); + ++ip_id; + + if (ip_addr_isany(src)) { + ip_addr_set(&(iphdr->src), &(netif->ip_addr)); + } else { + ip_addr_set(&(iphdr->src), src); + } + + IPH_CHKSUM_SET(iphdr, 0); +#if CHECKSUM_GEN_IP + IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN)); +#endif + } else { + iphdr = p->payload; + dest = &(iphdr->dest); + } + +#if IP_FRAG + /* don't fragment if interface has mtu set to 0 [loopif] */ + if (netif->mtu && (p->tot_len > netif->mtu)) + return ip_frag(p,netif,dest); +#endif + + IP_STATS_INC(ip.xmit); + + LWIP_DEBUGF(IP_DEBUG, ("ip_output_if: %c%c%"U16_F"\n", netif->name[0], netif->name[1], netif->num)); + ip_debug_print(p); + + LWIP_DEBUGF(IP_DEBUG, ("netif->output()")); + + return netif->output(netif, p, dest); +} + +/** + * Simple interface to ip_output_if. It finds the outgoing network + * interface and calls upon ip_output_if to do the actual work. + */ + +err_t +ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, + u8_t ttl, u8_t tos, u8_t proto) +{ + struct netif *netif; + + if ((netif = ip_route(dest)) == NULL) { + LWIP_DEBUGF(IP_DEBUG | 2, ("ip_output: No route to 0x%"X32_F"\n", dest->addr)); + + IP_STATS_INC(ip.rterr); + snmp_inc_ipoutnoroutes(); + return ERR_RTE; + } + + return ip_output_if(p, src, dest, ttl, tos, proto, netif); +} + +#if IP_DEBUG +void +ip_debug_print(struct pbuf *p) +{ + struct ip_hdr *iphdr = p->payload; + u8_t *payload; + + payload = (u8_t *)iphdr + IP_HLEN; + + LWIP_DEBUGF(IP_DEBUG, ("IP header:\n")); + LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(IP_DEBUG, ("|%2"S16_F" |%2"S16_F" | 0x%02"X16_F" | %5"U16_F" | (v, hl, tos, len)\n", + IPH_V(iphdr), + IPH_HL(iphdr), + IPH_TOS(iphdr), + ntohs(IPH_LEN(iphdr)))); + LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(IP_DEBUG, ("| %5"U16_F" |%"U16_F"%"U16_F"%"U16_F"| %4"U16_F" | (id, flags, offset)\n", + ntohs(IPH_ID(iphdr)), + ntohs(IPH_OFFSET(iphdr)) >> 15 & 1, + ntohs(IPH_OFFSET(iphdr)) >> 14 & 1, + ntohs(IPH_OFFSET(iphdr)) >> 13 & 1, + ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK)); + LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(IP_DEBUG, ("| %3"U16_F" | %3"U16_F" | 0x%04"X16_F" | (ttl, proto, chksum)\n", + IPH_TTL(iphdr), + IPH_PROTO(iphdr), + ntohs(IPH_CHKSUM(iphdr)))); + LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(IP_DEBUG, ("| %3"U16_F" | %3"U16_F" | %3"U16_F" | %3"U16_F" | (src)\n", + ip4_addr1(&iphdr->src), + ip4_addr2(&iphdr->src), + ip4_addr3(&iphdr->src), + ip4_addr4(&iphdr->src))); + LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(IP_DEBUG, ("| %3"U16_F" | %3"U16_F" | %3"U16_F" | %3"U16_F" | (dest)\n", + ip4_addr1(&iphdr->dest), + ip4_addr2(&iphdr->dest), + ip4_addr3(&iphdr->dest), + ip4_addr4(&iphdr->dest))); + LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); +} +#endif /* IP_DEBUG */ + + + + + + diff --git a/20080212/Demo/Common/ethernet/lwIP/core/ipv4/ip_addr.c b/20080212/Demo/Common/ethernet/lwIP/core/ipv4/ip_addr.c new file mode 100644 index 000000000..56b1cd7c4 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/core/ipv4/ip_addr.c @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/ip_addr.h" +#include "lwip/inet.h" +#include "lwip/netif.h" + +#define IP_ADDR_ANY_VALUE 0x00000000UL +#define IP_ADDR_BROADCAST_VALUE 0xffffffffUL + +/* used by IP_ADDR_ANY and IP_ADDR_BROADCAST in ip_addr.h */ +const struct ip_addr ip_addr_any = { IP_ADDR_ANY_VALUE }; +const struct ip_addr ip_addr_broadcast = { IP_ADDR_BROADCAST_VALUE }; + +/* Determine if an address is a broadcast address on a network interface + * + * @param addr address to be checked + * @param netif the network interface against which the address is checked + * @return returns non-zero if the address is a broadcast address + * + */ + +u8_t ip_addr_isbroadcast(struct ip_addr *addr, struct netif *netif) +{ + u32_t addr2test; + + addr2test = addr->addr; + /* all ones (broadcast) or all zeroes (old skool broadcast) */ + if ((~addr2test == IP_ADDR_ANY_VALUE) || + (addr2test == IP_ADDR_ANY_VALUE)) + return 1; + /* no broadcast support on this network interface? */ + else if ((netif->flags & NETIF_FLAG_BROADCAST) == 0) + /* the given address cannot be a broadcast address + * nor can we check against any broadcast addresses */ + return 0; + /* address matches network interface address exactly? => no broadcast */ + else if (addr2test == netif->ip_addr.addr) + return 0; + /* on the same (sub) network... */ + else if (ip_addr_netcmp(addr, &(netif->ip_addr), &(netif->netmask)) + /* ...and host identifier bits are all ones? =>... */ + && ((addr2test & ~netif->netmask.addr) == + (IP_ADDR_BROADCAST_VALUE & ~netif->netmask.addr))) + /* => network broadcast address */ + return 1; + else + return 0; +} diff --git a/20080212/Demo/Common/ethernet/lwIP/core/ipv4/ip_frag.c b/20080212/Demo/Common/ethernet/lwIP/core/ipv4/ip_frag.c new file mode 100644 index 000000000..0256a5020 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/core/ipv4/ip_frag.c @@ -0,0 +1,388 @@ +/* @file + * + * This is the IP packet segmentation and reassembly implementation. + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Jani Monoses + * original reassembly code by Adam Dunkels + * + */ + +#include + +#include "lwip/opt.h" +#include "lwip/ip.h" +#include "lwip/ip_frag.h" +#include "lwip/netif.h" +#include "lwip/snmp.h" +#include "lwip/stats.h" + +static u8_t ip_reassbuf[IP_HLEN + IP_REASS_BUFSIZE]; +static u8_t ip_reassbitmap[IP_REASS_BUFSIZE / (8 * 8) + 1]; +static const u8_t bitmap_bits[8] = { 0xff, 0x7f, 0x3f, 0x1f, + 0x0f, 0x07, 0x03, 0x01 +}; +static u16_t ip_reasslen; +static u8_t ip_reassflags; +#define IP_REASS_FLAG_LASTFRAG 0x01 + +static u8_t ip_reasstmr; + +/* + * Copy len bytes from offset in pbuf to buffer + * + * helper used by both ip_reass and ip_frag + */ +static struct pbuf * +copy_from_pbuf(struct pbuf *p, u16_t * offset, + u8_t * buffer, u16_t len) +{ + u16_t l; + + p->payload = (u8_t *)p->payload + *offset; + p->len -= *offset; + while (len) { + l = len < p->len ? len : p->len; + memcpy(buffer, p->payload, l); + buffer += l; + len -= l; + if (len) + p = p->next; + else + *offset = l; + } + return p; +} + + +/** + * Initializes IP reassembly and fragmentation states. + */ +void +ip_frag_init(void) +{ + ip_reasstmr = 0; + ip_reassflags = 0; + ip_reasslen = 0; + memset(ip_reassbitmap, 0, sizeof(ip_reassbitmap)); +} + +/** + * Reassembly timer base function + * for both NO_SYS == 0 and 1 (!). + * + * Should be called every 1000 msec. + */ +void +ip_reass_tmr(void) +{ + if (ip_reasstmr > 0) { + ip_reasstmr--; + LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass_tmr: timer dec %"U16_F"\n",(u16_t)ip_reasstmr)); + if (ip_reasstmr == 0) { + /* reassembly timed out */ + snmp_inc_ipreasmfails(); + } + } +} + +/** + * Reassembles incoming IP fragments into an IP datagram. + * + * @param p points to a pbuf chain of the fragment + * @return NULL if reassembly is incomplete, ? otherwise + */ +struct pbuf * +ip_reass(struct pbuf *p) +{ + struct pbuf *q; + struct ip_hdr *fraghdr, *iphdr; + u16_t offset, len; + u16_t i; + + IPFRAG_STATS_INC(ip_frag.recv); + snmp_inc_ipreasmreqds(); + + iphdr = (struct ip_hdr *) ip_reassbuf; + fraghdr = (struct ip_hdr *) p->payload; + /* If ip_reasstmr is zero, no packet is present in the buffer, so we + write the IP header of the fragment into the reassembly + buffer. The timer is updated with the maximum age. */ + if (ip_reasstmr == 0) { + LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass: new packet\n")); + memcpy(iphdr, fraghdr, IP_HLEN); + ip_reasstmr = IP_REASS_MAXAGE; + ip_reassflags = 0; + /* Clear the bitmap. */ + memset(ip_reassbitmap, 0, sizeof(ip_reassbitmap)); + } + + /* Check if the incoming fragment matches the one currently present + in the reasembly buffer. If so, we proceed with copying the + fragment into the buffer. */ + if (ip_addr_cmp(&iphdr->src, &fraghdr->src) && + ip_addr_cmp(&iphdr->dest, &fraghdr->dest) && + IPH_ID(iphdr) == IPH_ID(fraghdr)) { + LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass: matching previous fragment ID=%"X16_F"\n", + ntohs(IPH_ID(fraghdr)))); + IPFRAG_STATS_INC(ip_frag.cachehit); + /* Find out the offset in the reassembly buffer where we should + copy the fragment. */ + len = ntohs(IPH_LEN(fraghdr)) - IPH_HL(fraghdr) * 4; + offset = (ntohs(IPH_OFFSET(fraghdr)) & IP_OFFMASK) * 8; + + /* If the offset or the offset + fragment length overflows the + reassembly buffer, we discard the entire packet. */ + if ((offset > IP_REASS_BUFSIZE) || ((offset + len) > IP_REASS_BUFSIZE)) { + LWIP_DEBUGF(IP_REASS_DEBUG, + ("ip_reass: fragment outside of buffer (%"S16_F":%"S16_F"/%"S16_F").\n", offset, + offset + len, IP_REASS_BUFSIZE)); + ip_reasstmr = 0; + snmp_inc_ipreasmfails(); + goto nullreturn; + } + + /* Copy the fragment into the reassembly buffer, at the right + offset. */ + LWIP_DEBUGF(IP_REASS_DEBUG, + ("ip_reass: copying with offset %"S16_F" into %"S16_F":%"S16_F"\n", offset, + IP_HLEN + offset, IP_HLEN + offset + len)); + i = IPH_HL(fraghdr) * 4; + copy_from_pbuf(p, &i, &ip_reassbuf[IP_HLEN + offset], len); + + /* Update the bitmap. */ + if (offset / (8 * 8) == (offset + len) / (8 * 8)) { + LWIP_DEBUGF(IP_REASS_DEBUG, + ("ip_reass: updating single byte in bitmap.\n")); + /* If the two endpoints are in the same byte, we only update that byte. */ + LWIP_ASSERT("offset / (8 * 8) < sizeof(ip_reassbitmap)", + offset / (8 * 8) < sizeof(ip_reassbitmap)); + ip_reassbitmap[offset / (8 * 8)] |= + bitmap_bits[(offset / 8) & 7] & + ~bitmap_bits[((offset + len) / 8) & 7]; + } else { + /* If the two endpoints are in different bytes, we update the + bytes in the endpoints and fill the stuff inbetween with + 0xff. */ + LWIP_ASSERT("offset / (8 * 8) < sizeof(ip_reassbitmap)", + offset / (8 * 8) < sizeof(ip_reassbitmap)); + ip_reassbitmap[offset / (8 * 8)] |= bitmap_bits[(offset / 8) & 7]; + LWIP_DEBUGF(IP_REASS_DEBUG, + ("ip_reass: updating many bytes in bitmap (%"S16_F":%"S16_F").\n", + 1 + offset / (8 * 8), (offset + len) / (8 * 8))); + for (i = 1 + offset / (8 * 8); i < (offset + len) / (8 * 8); ++i) { + ip_reassbitmap[i] = 0xff; + } + LWIP_ASSERT("(offset + len) / (8 * 8) < sizeof(ip_reassbitmap)", + (offset + len) / (8 * 8) < sizeof(ip_reassbitmap)); + ip_reassbitmap[(offset + len) / (8 * 8)] |= + ~bitmap_bits[((offset + len) / 8) & 7]; + } + + /* If this fragment has the More Fragments flag set to zero, we + know that this is the last fragment, so we can calculate the + size of the entire packet. We also set the + IP_REASS_FLAG_LASTFRAG flag to indicate that we have received + the final fragment. */ + + if ((ntohs(IPH_OFFSET(fraghdr)) & IP_MF) == 0) { + ip_reassflags |= IP_REASS_FLAG_LASTFRAG; + ip_reasslen = offset + len; + LWIP_DEBUGF(IP_REASS_DEBUG, + ("ip_reass: last fragment seen, total len %"S16_F"\n", + ip_reasslen)); + } + + /* Finally, we check if we have a full packet in the buffer. We do + this by checking if we have the last fragment and if all bits + in the bitmap are set. */ + if (ip_reassflags & IP_REASS_FLAG_LASTFRAG) { + /* Check all bytes up to and including all but the last byte in + the bitmap. */ + LWIP_ASSERT("ip_reasslen / (8 * 8) - 1 < sizeof(ip_reassbitmap)", + ip_reasslen / (8 * 8) - 1 < ((u16_t) sizeof(ip_reassbitmap))); + for (i = 0; i < ip_reasslen / (8 * 8) - 1; ++i) { + if (ip_reassbitmap[i] != 0xff) { + LWIP_DEBUGF(IP_REASS_DEBUG, + ("ip_reass: last fragment seen, bitmap %"S16_F"/%"S16_F" failed (%"X16_F")\n", + i, ip_reasslen / (8 * 8) - 1, ip_reassbitmap[i])); + goto nullreturn; + } + } + /* Check the last byte in the bitmap. It should contain just the + right amount of bits. */ + LWIP_ASSERT("ip_reasslen / (8 * 8) < sizeof(ip_reassbitmap)", + ip_reasslen / (8 * 8) < sizeof(ip_reassbitmap)); + if (ip_reassbitmap[ip_reasslen / (8 * 8)] != + (u8_t) ~ bitmap_bits[ip_reasslen / 8 & 7]) { + LWIP_DEBUGF(IP_REASS_DEBUG, + ("ip_reass: last fragment seen, bitmap %"S16_F" didn't contain %"X16_F" (%"X16_F")\n", + ip_reasslen / (8 * 8), ~bitmap_bits[ip_reasslen / 8 & 7], + ip_reassbitmap[ip_reasslen / (8 * 8)])); + goto nullreturn; + } + + /* Pretend to be a "normal" (i.e., not fragmented) IP packet + from now on. */ + ip_reasslen += IP_HLEN; + + IPH_LEN_SET(iphdr, htons(ip_reasslen)); + IPH_OFFSET_SET(iphdr, 0); + IPH_CHKSUM_SET(iphdr, 0); + IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN)); + + /* If we have come this far, we have a full packet in the + buffer, so we allocate a pbuf and copy the packet into it. We + also reset the timer. */ + ip_reasstmr = 0; + pbuf_free(p); + p = pbuf_alloc(PBUF_LINK, ip_reasslen, PBUF_POOL); + if (p != NULL) { + i = 0; + for (q = p; q != NULL; q = q->next) { + /* Copy enough bytes to fill this pbuf in the chain. The + available data in the pbuf is given by the q->len variable. */ + LWIP_DEBUGF(IP_REASS_DEBUG, + ("ip_reass: memcpy from %p (%"S16_F") to %p, %"S16_F" bytes\n", + (void *)&ip_reassbuf[i], i, q->payload, + q->len > ip_reasslen - i ? ip_reasslen - i : q->len)); + memcpy(q->payload, &ip_reassbuf[i], + q->len > ip_reasslen - i ? ip_reasslen - i : q->len); + i += q->len; + } + IPFRAG_STATS_INC(ip_frag.fw); + snmp_inc_ipreasmoks(); + } else { + LWIP_DEBUGF(IP_REASS_DEBUG, + ("ip_reass: pbuf_alloc(PBUF_LINK, ip_reasslen=%"U16_F", PBUF_POOL) failed\n", ip_reasslen)); + IPFRAG_STATS_INC(ip_frag.memerr); + snmp_inc_ipreasmfails(); + } + LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass: p %p\n", (void*)p)); + return p; + } + } + +nullreturn: + IPFRAG_STATS_INC(ip_frag.drop); + pbuf_free(p); + return NULL; +} + +static u8_t buf[MEM_ALIGN_SIZE(IP_FRAG_MAX_MTU)]; + +/** + * Fragment an IP datagram if too large for the netif. + * + * Chop the datagram in MTU sized chunks and send them in order + * by using a fixed size static memory buffer (PBUF_ROM) + */ +err_t +ip_frag(struct pbuf *p, struct netif *netif, struct ip_addr *dest) +{ + struct pbuf *rambuf; + struct pbuf *header; + struct ip_hdr *iphdr; + u16_t nfb = 0; + u16_t left, cop; + u16_t mtu = netif->mtu; + u16_t ofo, omf; + u16_t last; + u16_t poff = IP_HLEN; + u16_t tmp; + + /* Get a RAM based MTU sized pbuf */ + rambuf = pbuf_alloc(PBUF_LINK, 0, PBUF_REF); + if (rambuf == NULL) { + LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_frag: pbuf_alloc(PBUF_LINK, 0, PBUF_REF) failed\n")); + return ERR_MEM; + } + rambuf->tot_len = rambuf->len = mtu; + rambuf->payload = MEM_ALIGN((void *)buf); + + /* Copy the IP header in it */ + iphdr = rambuf->payload; + memcpy(iphdr, p->payload, IP_HLEN); + + /* Save original offset */ + tmp = ntohs(IPH_OFFSET(iphdr)); + ofo = tmp & IP_OFFMASK; + omf = tmp & IP_MF; + + left = p->tot_len - IP_HLEN; + + while (left) { + last = (left <= mtu - IP_HLEN); + + /* Set new offset and MF flag */ + ofo += nfb; + tmp = omf | (IP_OFFMASK & (ofo)); + if (!last) + tmp = tmp | IP_MF; + IPH_OFFSET_SET(iphdr, htons(tmp)); + + /* Fill this fragment */ + nfb = (mtu - IP_HLEN) / 8; + cop = last ? left : nfb * 8; + + p = copy_from_pbuf(p, &poff, (u8_t *) iphdr + IP_HLEN, cop); + + /* Correct header */ + IPH_LEN_SET(iphdr, htons(cop + IP_HLEN)); + IPH_CHKSUM_SET(iphdr, 0); + IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN)); + + if (last) + pbuf_realloc(rambuf, left + IP_HLEN); + /* This part is ugly: we alloc a RAM based pbuf for + * the link level header for each chunk and then + * free it.A PBUF_ROM style pbuf for which pbuf_header + * worked would make things simpler. + */ + header = pbuf_alloc(PBUF_LINK, 0, PBUF_RAM); + if (header != NULL) { + pbuf_chain(header, rambuf); + netif->output(netif, header, dest); + IPFRAG_STATS_INC(ip_frag.xmit); + snmp_inc_ipfragcreates(); + pbuf_free(header); + } else { + LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_frag: pbuf_alloc() for header failed\n")); + pbuf_free(rambuf); + return ERR_MEM; + } + left -= cop; + } + pbuf_free(rambuf); + snmp_inc_ipfragoks(); + return ERR_OK; +} diff --git a/20080212/Demo/Common/ethernet/lwIP/core/mem.c b/20080212/Demo/Common/ethernet/lwIP/core/mem.c new file mode 100644 index 000000000..4d4cb1d6a --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/core/mem.c @@ -0,0 +1,414 @@ +/** @file + * + * Dynamic memory manager + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include + +#include "lwip/arch.h" +#include "lwip/opt.h" +#include "lwip/def.h" +#include "lwip/mem.h" + +#include "lwip/sys.h" + +#include "lwip/stats.h" + +#if (MEM_LIBC_MALLOC == 0) +/* lwIP replacement for your libc malloc() */ + +struct mem { + mem_size_t next, prev; +#if MEM_ALIGNMENT == 1 + u8_t used; +#elif MEM_ALIGNMENT == 2 + u16_t used; +#elif MEM_ALIGNMENT == 4 + u32_t used; +#elif MEM_ALIGNMENT == 8 + u64_t used; +#else +#error "unhandled MEM_ALIGNMENT size" +#endif /* MEM_ALIGNMENT */ +}; + +static struct mem *ram_end; +#if 1 +/* Adam original */ +static u8_t ram[MEM_SIZE + sizeof(struct mem) + MEM_ALIGNMENT]; +#else +/* Christiaan alignment fix */ +static u8_t *ram; +static struct mem ram_heap[1 + ( (MEM_SIZE + sizeof(struct mem) - 1) / sizeof(struct mem))]; +#endif + +#define MIN_SIZE 12 +#if 0 /* this one does not align correctly for some, resulting in crashes */ +#define SIZEOF_STRUCT_MEM (unsigned int)MEM_ALIGN_SIZE(sizeof(struct mem)) +#else +#define SIZEOF_STRUCT_MEM (sizeof(struct mem) + \ + (((sizeof(struct mem) % MEM_ALIGNMENT) == 0)? 0 : \ + (4 - (sizeof(struct mem) % MEM_ALIGNMENT)))) +#endif + +static struct mem *lfree; /* pointer to the lowest free block */ + +static sys_sem_t mem_sem; + +static void +plug_holes(struct mem *mem) +{ + struct mem *nmem; + struct mem *pmem; + + LWIP_ASSERT("plug_holes: mem >= ram", (u8_t *)mem >= ram); + LWIP_ASSERT("plug_holes: mem < ram_end", (u8_t *)mem < (u8_t *)ram_end); + LWIP_ASSERT("plug_holes: mem->used == 0", mem->used == 0); + + /* plug hole forward */ + LWIP_ASSERT("plug_holes: mem->next <= MEM_SIZE", mem->next <= MEM_SIZE); + + nmem = (struct mem *)&ram[mem->next]; + if (mem != nmem && nmem->used == 0 && (u8_t *)nmem != (u8_t *)ram_end) { + if (lfree == nmem) { + lfree = mem; + } + mem->next = nmem->next; + ((struct mem *)&ram[nmem->next])->prev = (u8_t *)mem - ram; + } + + /* plug hole backward */ + pmem = (struct mem *)&ram[mem->prev]; + if (pmem != mem && pmem->used == 0) { + if (lfree == mem) { + lfree = pmem; + } + pmem->next = mem->next; + ((struct mem *)&ram[mem->next])->prev = (u8_t *)pmem - ram; + } +} + +void +mem_init(void) +{ + struct mem *mem; + +#if 1 + /* Adam original */ +#else + /* Christiaan alignment fix */ + ram = (u8_t*)ram_heap; +#endif + memset(ram, 0, MEM_SIZE); + mem = (struct mem *)ram; + mem->next = MEM_SIZE; + mem->prev = 0; + mem->used = 0; + ram_end = (struct mem *)&ram[MEM_SIZE]; + ram_end->used = 1; + ram_end->next = MEM_SIZE; + ram_end->prev = MEM_SIZE; + + mem_sem = sys_sem_new(1); + + lfree = (struct mem *)ram; + +#if MEM_STATS + lwip_stats.mem.avail = MEM_SIZE; +#endif /* MEM_STATS */ +} + +void +mem_free(void *rmem) +{ + struct mem *mem; + + if (rmem == NULL) { + LWIP_DEBUGF(MEM_DEBUG | DBG_TRACE | 2, ("mem_free(p == NULL) was called.\n")); + return; + } + + sys_sem_wait(mem_sem); + + LWIP_ASSERT("mem_free: legal memory", (u8_t *)rmem >= (u8_t *)ram && + (u8_t *)rmem < (u8_t *)ram_end); + + if ((u8_t *)rmem < (u8_t *)ram || (u8_t *)rmem >= (u8_t *)ram_end) { + LWIP_DEBUGF(MEM_DEBUG | 3, ("mem_free: illegal memory\n")); +#if MEM_STATS + ++lwip_stats.mem.err; +#endif /* MEM_STATS */ + sys_sem_signal(mem_sem); + return; + } + mem = (struct mem *)((u8_t *)rmem - SIZEOF_STRUCT_MEM); + + LWIP_ASSERT("mem_free: mem->used", mem->used); + + mem->used = 0; + + if (mem < lfree) { + lfree = mem; + } + +#if MEM_STATS + lwip_stats.mem.used -= mem->next - ((u8_t *)mem - ram); + +#endif /* MEM_STATS */ + plug_holes(mem); + sys_sem_signal(mem_sem); +} + +void * +mem_realloc(void *rmem, mem_size_t newsize) +{ + mem_size_t size; + mem_size_t ptr, ptr2; + struct mem *mem, *mem2; + + /* Expand the size of the allocated memory region so that we can + adjust for alignment. */ + if ((newsize % MEM_ALIGNMENT) != 0) { + newsize += MEM_ALIGNMENT - ((newsize + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT); + } + + if (newsize > MEM_SIZE) { + return NULL; + } + + sys_sem_wait(mem_sem); + + LWIP_ASSERT("mem_realloc: legal memory", (u8_t *)rmem >= (u8_t *)ram && + (u8_t *)rmem < (u8_t *)ram_end); + + if ((u8_t *)rmem < (u8_t *)ram || (u8_t *)rmem >= (u8_t *)ram_end) { + LWIP_DEBUGF(MEM_DEBUG | 3, ("mem_realloc: illegal memory\n")); + return rmem; + } + mem = (struct mem *)((u8_t *)rmem - SIZEOF_STRUCT_MEM); + + ptr = (u8_t *)mem - ram; + + size = mem->next - ptr - SIZEOF_STRUCT_MEM; +#if MEM_STATS + lwip_stats.mem.used -= (size - newsize); +#endif /* MEM_STATS */ + + if (newsize + SIZEOF_STRUCT_MEM + MIN_SIZE < size) { + ptr2 = ptr + SIZEOF_STRUCT_MEM + newsize; + mem2 = (struct mem *)&ram[ptr2]; + mem2->used = 0; + mem2->next = mem->next; + mem2->prev = ptr; + mem->next = ptr2; + if (mem2->next != MEM_SIZE) { + ((struct mem *)&ram[mem2->next])->prev = ptr2; + } + + plug_holes(mem2); + } + sys_sem_signal(mem_sem); + return rmem; +} + +#if 1 +/** + * Adam's mem_malloc(), suffers from bug #17922 + * Set if to 0 for alternative mem_malloc(). + */ +void * +mem_malloc(mem_size_t size) +{ + mem_size_t ptr, ptr2; + struct mem *mem, *mem2; + + if (size == 0) { + return NULL; + } + + /* Expand the size of the allocated memory region so that we can + adjust for alignment. */ + if ((size % MEM_ALIGNMENT) != 0) { + size += MEM_ALIGNMENT - ((size + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT); + } + + if (size > MEM_SIZE) { + return NULL; + } + + sys_sem_wait(mem_sem); + + for (ptr = (u8_t *)lfree - ram; ptr < MEM_SIZE; ptr = ((struct mem *)&ram[ptr])->next) { + mem = (struct mem *)&ram[ptr]; + if (!mem->used && + mem->next - (ptr + SIZEOF_STRUCT_MEM) >= size + SIZEOF_STRUCT_MEM) { + ptr2 = ptr + SIZEOF_STRUCT_MEM + size; + mem2 = (struct mem *)&ram[ptr2]; + + mem2->prev = ptr; + mem2->next = mem->next; + mem->next = ptr2; + if (mem2->next != MEM_SIZE) { + ((struct mem *)&ram[mem2->next])->prev = ptr2; + } + + mem2->used = 0; + mem->used = 1; +#if MEM_STATS + lwip_stats.mem.used += (size + SIZEOF_STRUCT_MEM); + /* if (lwip_stats.mem.max < lwip_stats.mem.used) { + lwip_stats.mem.max = lwip_stats.mem.used; + } */ + if (lwip_stats.mem.max < ptr2) { + lwip_stats.mem.max = ptr2; + } +#endif /* MEM_STATS */ + + if (mem == lfree) { + /* Find next free block after mem */ + while (lfree->used && lfree != ram_end) { + lfree = (struct mem *)&ram[lfree->next]; + } + LWIP_ASSERT("mem_malloc: !lfree->used", !lfree->used); + } + sys_sem_signal(mem_sem); + LWIP_ASSERT("mem_malloc: allocated memory not above ram_end.", + (mem_ptr_t)mem + SIZEOF_STRUCT_MEM + size <= (mem_ptr_t)ram_end); + LWIP_ASSERT("mem_malloc: allocated memory properly aligned.", + (unsigned long)((u8_t *)mem + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT == 0); + return (u8_t *)mem + SIZEOF_STRUCT_MEM; + } + } + LWIP_DEBUGF(MEM_DEBUG | 2, ("mem_malloc: could not allocate %"S16_F" bytes\n", (s16_t)size)); +#if MEM_STATS + ++lwip_stats.mem.err; +#endif /* MEM_STATS */ + sys_sem_signal(mem_sem); + return NULL; +} +#else +/** + * Adam's mem_malloc() plus solution for bug #17922 + */ +void * +mem_malloc(mem_size_t size) +{ + mem_size_t ptr, ptr2; + struct mem *mem, *mem2; + + if (size == 0) { + return NULL; + } + + /* Expand the size of the allocated memory region so that we can + adjust for alignment. */ + if ((size % MEM_ALIGNMENT) != 0) { + size += MEM_ALIGNMENT - ((size + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT); + } + + if (size > MEM_SIZE) { + return NULL; + } + + sys_sem_wait(mem_sem); + + for (ptr = (u8_t *)lfree - ram; ptr < MEM_SIZE - size; ptr = ((struct mem *)&ram[ptr])->next) { + mem = (struct mem *)&ram[ptr]; + + if (!mem->used) { + + ptr2 = ptr + SIZEOF_STRUCT_MEM + size; + + if (mem->next - (ptr + (2*SIZEOF_STRUCT_MEM)) >= size) { + /* split large block, create empty remainder */ + mem->next = ptr2; + mem->used = 1; + /* create mem2 struct */ + mem2 = (struct mem *)&ram[ptr2]; + mem2->used = 0; + mem2->next = mem->next; + mem2->prev = ptr; + + if (mem2->next != MEM_SIZE) { + ((struct mem *)&ram[mem2->next])->prev = ptr2; + } + } + else if (mem->next - (ptr + SIZEOF_STRUCT_MEM) > size) { + /* near fit, no split, no mem2 creation, + round up to mem->next */ + ptr2 = mem->next; + mem->used = 1; + } + else if (mem->next - (ptr + SIZEOF_STRUCT_MEM) == size) { + /* exact fit, do not split, no mem2 creation */ + mem->next = ptr2; + mem->used = 1; + } + + if (mem->used) { +#if MEM_STATS + lwip_stats.mem.used += (size + SIZEOF_STRUCT_MEM); + if (lwip_stats.mem.max < ptr2) { + lwip_stats.mem.max = ptr2; + } +#endif /* MEM_STATS */ + if (mem == lfree) { + /* Find next free block after mem */ + while (lfree->used && lfree != ram_end) { + lfree = (struct mem *)&ram[lfree->next]; + } + LWIP_ASSERT("mem_malloc: !lfree->used", !lfree->used); + } + sys_sem_signal(mem_sem); + LWIP_ASSERT("mem_malloc: allocated memory not above ram_end.", + (mem_ptr_t)mem + SIZEOF_STRUCT_MEM + size <= (mem_ptr_t)ram_end); + LWIP_ASSERT("mem_malloc: allocated memory properly aligned.", + (unsigned long)((u8_t *)mem + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT == 0); + return (u8_t *)mem + SIZEOF_STRUCT_MEM; + } + } + } + LWIP_DEBUGF(MEM_DEBUG | 2, ("mem_malloc: could not allocate %"S16_F" bytes\n", (s16_t)size)); +#if MEM_STATS + ++lwip_stats.mem.err; +#endif /* MEM_STATS */ + sys_sem_signal(mem_sem); + return NULL; +} +#endif + +#endif /* MEM_LIBC_MALLOC == 0 */ + diff --git a/20080212/Demo/Common/ethernet/lwIP/core/memp.c b/20080212/Demo/Common/ethernet/lwIP/core/memp.c new file mode 100644 index 000000000..391200957 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/core/memp.c @@ -0,0 +1,238 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" + +#include "lwip/memp.h" + +#include "lwip/pbuf.h" +#include "lwip/udp.h" +#include "lwip/raw.h" +#include "lwip/tcp.h" +#include "lwip/api.h" +#include "lwip/api_msg.h" +#include "lwip/tcpip.h" + +#include "lwip/sys.h" +#include "lwip/stats.h" + +struct memp { + struct memp *next; +}; + +#define MEMP_SIZE MEM_ALIGN_SIZE(sizeof(struct memp)) + +static struct memp *memp_tab[MEMP_MAX]; + +static const u16_t memp_sizes[MEMP_MAX] = { + MEM_ALIGN_SIZE(sizeof(struct pbuf)), + MEM_ALIGN_SIZE(sizeof(struct raw_pcb)), + MEM_ALIGN_SIZE(sizeof(struct udp_pcb)), + MEM_ALIGN_SIZE(sizeof(struct tcp_pcb)), + MEM_ALIGN_SIZE(sizeof(struct tcp_pcb_listen)), + MEM_ALIGN_SIZE(sizeof(struct tcp_seg)), + MEM_ALIGN_SIZE(sizeof(struct netbuf)), + MEM_ALIGN_SIZE(sizeof(struct netconn)), + MEM_ALIGN_SIZE(sizeof(struct api_msg)), + MEM_ALIGN_SIZE(sizeof(struct tcpip_msg)), + MEM_ALIGN_SIZE(sizeof(struct sys_timeo)) +}; + +static const u16_t memp_num[MEMP_MAX] = { + MEMP_NUM_PBUF, + MEMP_NUM_RAW_PCB, + MEMP_NUM_UDP_PCB, + MEMP_NUM_TCP_PCB, + MEMP_NUM_TCP_PCB_LISTEN, + MEMP_NUM_TCP_SEG, + MEMP_NUM_NETBUF, + MEMP_NUM_NETCONN, + MEMP_NUM_API_MSG, + MEMP_NUM_TCPIP_MSG, + MEMP_NUM_SYS_TIMEOUT +}; + +#define MEMP_TYPE_SIZE(qty, type) \ + ((qty) * (MEMP_SIZE + MEM_ALIGN_SIZE(sizeof(type)))) + +static u8_t memp_memory[MEM_ALIGNMENT - 1 + + MEMP_TYPE_SIZE(MEMP_NUM_PBUF, struct pbuf) + + MEMP_TYPE_SIZE(MEMP_NUM_RAW_PCB, struct raw_pcb) + + MEMP_TYPE_SIZE(MEMP_NUM_UDP_PCB, struct udp_pcb) + + MEMP_TYPE_SIZE(MEMP_NUM_TCP_PCB, struct tcp_pcb) + + MEMP_TYPE_SIZE(MEMP_NUM_TCP_PCB_LISTEN, struct tcp_pcb_listen) + + MEMP_TYPE_SIZE(MEMP_NUM_TCP_SEG, struct tcp_seg) + + MEMP_TYPE_SIZE(MEMP_NUM_NETBUF, struct netbuf) + + MEMP_TYPE_SIZE(MEMP_NUM_NETCONN, struct netconn) + + MEMP_TYPE_SIZE(MEMP_NUM_API_MSG, struct api_msg) + + MEMP_TYPE_SIZE(MEMP_NUM_TCPIP_MSG, struct tcpip_msg) + + MEMP_TYPE_SIZE(MEMP_NUM_SYS_TIMEOUT, struct sys_timeo)]; + +#if !SYS_LIGHTWEIGHT_PROT +static sys_sem_t mutex; +#endif + +#if MEMP_SANITY_CHECK +static int +memp_sanity(void) +{ + s16_t i, c; + struct memp *m, *n; + + for (i = 0; i < MEMP_MAX; i++) { + for (m = memp_tab[i]; m != NULL; m = m->next) { + c = 1; + for (n = memp_tab[i]; n != NULL; n = n->next) { + if (n == m && --c < 0) { + return 0; /* LW was: abort(); */ + } + } + } + } + return 1; +} +#endif /* MEMP_SANITY_CHECK*/ + +void +memp_init(void) +{ + struct memp *memp; + u16_t i, j; + +#if MEMP_STATS + for (i = 0; i < MEMP_MAX; ++i) { + lwip_stats.memp[i].used = lwip_stats.memp[i].max = + lwip_stats.memp[i].err = 0; + lwip_stats.memp[i].avail = memp_num[i]; + } +#endif /* MEMP_STATS */ + + memp = MEM_ALIGN(memp_memory); + for (i = 0; i < MEMP_MAX; ++i) { + memp_tab[i] = NULL; + for (j = 0; j < memp_num[i]; ++j) { + memp->next = memp_tab[i]; + memp_tab[i] = memp; + memp = (struct memp *)((u8_t *)memp + MEMP_SIZE + memp_sizes[i]); + } + } + +#if !SYS_LIGHTWEIGHT_PROT + mutex = sys_sem_new(1); +#endif +} + +void * +memp_malloc(memp_t type) +{ + struct memp *memp; + void *mem; +#if SYS_LIGHTWEIGHT_PROT + SYS_ARCH_DECL_PROTECT(old_level); +#endif + + LWIP_ASSERT("memp_malloc: type < MEMP_MAX", type < MEMP_MAX); + +#if SYS_LIGHTWEIGHT_PROT + SYS_ARCH_PROTECT(old_level); +#else /* SYS_LIGHTWEIGHT_PROT */ + sys_sem_wait(mutex); +#endif /* SYS_LIGHTWEIGHT_PROT */ + + memp = memp_tab[type]; + + if (memp != NULL) { + memp_tab[type] = memp->next; + memp->next = NULL; +#if MEMP_STATS + ++lwip_stats.memp[type].used; + if (lwip_stats.memp[type].used > lwip_stats.memp[type].max) { + lwip_stats.memp[type].max = lwip_stats.memp[type].used; + } +#endif /* MEMP_STATS */ + mem = (u8_t *)memp + MEMP_SIZE; + LWIP_ASSERT("memp_malloc: memp properly aligned", + ((mem_ptr_t)memp % MEM_ALIGNMENT) == 0); + } else { + LWIP_DEBUGF(MEMP_DEBUG | 2, ("memp_malloc: out of memory in pool %"S16_F"\n", type)); +#if MEMP_STATS + ++lwip_stats.memp[type].err; +#endif /* MEMP_STATS */ + mem = NULL; + } + +#if SYS_LIGHTWEIGHT_PROT + SYS_ARCH_UNPROTECT(old_level); +#else /* SYS_LIGHTWEIGHT_PROT */ + sys_sem_signal(mutex); +#endif /* SYS_LIGHTWEIGHT_PROT */ + + return mem; +} + +void +memp_free(memp_t type, void *mem) +{ + struct memp *memp; +#if SYS_LIGHTWEIGHT_PROT + SYS_ARCH_DECL_PROTECT(old_level); +#endif /* SYS_LIGHTWEIGHT_PROT */ + + if (mem == NULL) { + return; + } + + memp = (struct memp *)((u8_t *)mem - MEMP_SIZE); + +#if SYS_LIGHTWEIGHT_PROT + SYS_ARCH_PROTECT(old_level); +#else /* SYS_LIGHTWEIGHT_PROT */ + sys_sem_wait(mutex); +#endif /* SYS_LIGHTWEIGHT_PROT */ + +#if MEMP_STATS + lwip_stats.memp[type].used--; +#endif /* MEMP_STATS */ + + memp->next = memp_tab[type]; + memp_tab[type] = memp; + +#if MEMP_SANITY_CHECK + LWIP_ASSERT("memp sanity", memp_sanity()); +#endif + +#if SYS_LIGHTWEIGHT_PROT + SYS_ARCH_UNPROTECT(old_level); +#else /* SYS_LIGHTWEIGHT_PROT */ + sys_sem_signal(mutex); +#endif /* SYS_LIGHTWEIGHT_PROT */ +} diff --git a/20080212/Demo/Common/ethernet/lwIP/core/netif.c b/20080212/Demo/Common/ethernet/lwIP/core/netif.c new file mode 100644 index 000000000..0a7866167 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/core/netif.c @@ -0,0 +1,325 @@ +/** + * @file + * + * lwIP network interface abstraction + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" + +#include "lwip/def.h" +#include "lwip/ip_addr.h" +#include "lwip/netif.h" +#include "lwip/tcp.h" +#include "lwip/snmp.h" + +struct netif *netif_list = NULL; +struct netif *netif_default = NULL; + +/** + * Add a network interface to the list of lwIP netifs. + * + * @param netif a pre-allocated netif structure + * @param ipaddr IP address for the new netif + * @param netmask network mask for the new netif + * @param gw default gateway IP address for the new netif + * @param state opaque data passed to the new netif + * @param init callback function that initializes the interface + * @param input callback function that is called to pass + * ingress packets up in the protocol layer stack. + * + * @return netif, or NULL if failed. + */ +struct netif * +netif_add(struct netif *netif, struct ip_addr *ipaddr, struct ip_addr *netmask, + struct ip_addr *gw, + void *state, + err_t (* init)(struct netif *netif), + err_t (* input)(struct pbuf *p, struct netif *netif)) +{ + static s16_t netifnum = 0; + + /* reset new interface configuration state */ + netif->ip_addr.addr = 0; + netif->netmask.addr = 0; + netif->gw.addr = 0; + netif->flags = 0; +#if LWIP_DHCP + /* netif not under DHCP control by default */ + netif->dhcp = NULL; +#endif + /* remember netif specific state information data */ + netif->state = state; + netif->num = netifnum++; + netif->input = input; + + netif_set_addr(netif, ipaddr, netmask, gw); + + /* call user specified initialization function for netif */ + if (init(netif) != ERR_OK) { + return NULL; + } + + /* add this netif to the list */ + netif->next = netif_list; + netif_list = netif; + snmp_inc_iflist(); + + LWIP_DEBUGF(NETIF_DEBUG, ("netif: added interface %c%c IP addr ", + netif->name[0], netif->name[1])); + ip_addr_debug_print(NETIF_DEBUG, ipaddr); + LWIP_DEBUGF(NETIF_DEBUG, (" netmask ")); + ip_addr_debug_print(NETIF_DEBUG, netmask); + LWIP_DEBUGF(NETIF_DEBUG, (" gw ")); + ip_addr_debug_print(NETIF_DEBUG, gw); + LWIP_DEBUGF(NETIF_DEBUG, ("\n")); + return netif; +} + +void +netif_set_addr(struct netif *netif,struct ip_addr *ipaddr, struct ip_addr *netmask, + struct ip_addr *gw) +{ + netif_set_ipaddr(netif, ipaddr); + netif_set_netmask(netif, netmask); + netif_set_gw(netif, gw); +} + +void netif_remove(struct netif * netif) +{ + if ( netif == NULL ) return; + + snmp_delete_ipaddridx_tree(netif); + + /* is it the first netif? */ + if (netif_list == netif) { + netif_list = netif->next; + snmp_dec_iflist(); + } + else { + /* look for netif further down the list */ + struct netif * tmpNetif; + for (tmpNetif = netif_list; tmpNetif != NULL; tmpNetif = tmpNetif->next) { + if (tmpNetif->next == netif) { + tmpNetif->next = netif->next; + snmp_dec_iflist(); + break; + } + } + if (tmpNetif == NULL) + return; /* we didn't find any netif today */ + } + /* this netif is default? */ + if (netif_default == netif) + /* reset default netif */ + netif_default = NULL; + LWIP_DEBUGF( NETIF_DEBUG, ("netif_remove: removed netif\n") ); +} + +struct netif * +netif_find(char *name) +{ + struct netif *netif; + u8_t num; + + if (name == NULL) { + return NULL; + } + + num = name[2] - '0'; + + for(netif = netif_list; netif != NULL; netif = netif->next) { + if (num == netif->num && + name[0] == netif->name[0] && + name[1] == netif->name[1]) { + LWIP_DEBUGF(NETIF_DEBUG, ("netif_find: found %c%c\n", name[0], name[1])); + return netif; + } + } + LWIP_DEBUGF(NETIF_DEBUG, ("netif_find: didn't find %c%c\n", name[0], name[1])); + return NULL; +} + +void +netif_set_ipaddr(struct netif *netif, struct ip_addr *ipaddr) +{ + /* TODO: Handling of obsolete pcbs */ + /* See: http://mail.gnu.org/archive/html/lwip-users/2003-03/msg00118.html */ +#if LWIP_TCP + struct tcp_pcb *pcb; + struct tcp_pcb_listen *lpcb; + + /* address is actually being changed? */ + if ((ip_addr_cmp(ipaddr, &(netif->ip_addr))) == 0) + { + /* extern struct tcp_pcb *tcp_active_pcbs; defined by tcp.h */ + LWIP_DEBUGF(NETIF_DEBUG | 1, ("netif_set_ipaddr: netif address being changed\n")); + pcb = tcp_active_pcbs; + while (pcb != NULL) { + /* PCB bound to current local interface address? */ + if (ip_addr_cmp(&(pcb->local_ip), &(netif->ip_addr))) { + /* this connection must be aborted */ + struct tcp_pcb *next = pcb->next; + LWIP_DEBUGF(NETIF_DEBUG | 1, ("netif_set_ipaddr: aborting TCP pcb %p\n", (void *)pcb)); + tcp_abort(pcb); + pcb = next; + } else { + pcb = pcb->next; + } + } + for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) { + /* PCB bound to current local interface address? */ + if (ip_addr_cmp(&(lpcb->local_ip), &(netif->ip_addr))) { + /* The PCB is listening to the old ipaddr and + * is set to listen to the new one instead */ + ip_addr_set(&(lpcb->local_ip), ipaddr); + } + } + } +#endif + snmp_delete_ipaddridx_tree(netif); + snmp_delete_iprteidx_tree(0,netif); + /* set new IP address to netif */ + ip_addr_set(&(netif->ip_addr), ipaddr); + snmp_insert_ipaddridx_tree(netif); + snmp_insert_iprteidx_tree(0,netif); + +#if 0 /* only allowed for Ethernet interfaces TODO: how can we check? */ + /** For Ethernet network interfaces, we would like to send a + * "gratuitous ARP"; this is an ARP packet sent by a node in order + * to spontaneously cause other nodes to update an entry in their + * ARP cache. From RFC 3220 "IP Mobility Support for IPv4" section 4.6. + */ + etharp_query(netif, ipaddr, NULL); +#endif + LWIP_DEBUGF(NETIF_DEBUG | DBG_TRACE | DBG_STATE | 3, ("netif: IP address of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", + netif->name[0], netif->name[1], + ip4_addr1(&netif->ip_addr), + ip4_addr2(&netif->ip_addr), + ip4_addr3(&netif->ip_addr), + ip4_addr4(&netif->ip_addr))); +} + +void +netif_set_gw(struct netif *netif, struct ip_addr *gw) +{ + ip_addr_set(&(netif->gw), gw); + LWIP_DEBUGF(NETIF_DEBUG | DBG_TRACE | DBG_STATE | 3, ("netif: GW address of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", + netif->name[0], netif->name[1], + ip4_addr1(&netif->gw), + ip4_addr2(&netif->gw), + ip4_addr3(&netif->gw), + ip4_addr4(&netif->gw))); +} + +void +netif_set_netmask(struct netif *netif, struct ip_addr *netmask) +{ + snmp_delete_iprteidx_tree(0, netif); + /* set new netmask to netif */ + ip_addr_set(&(netif->netmask), netmask); + snmp_insert_iprteidx_tree(0, netif); + LWIP_DEBUGF(NETIF_DEBUG | DBG_TRACE | DBG_STATE | 3, ("netif: netmask of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", + netif->name[0], netif->name[1], + ip4_addr1(&netif->netmask), + ip4_addr2(&netif->netmask), + ip4_addr3(&netif->netmask), + ip4_addr4(&netif->netmask))); +} + +void +netif_set_default(struct netif *netif) +{ + if (netif == NULL) + { + /* remove default route */ + snmp_delete_iprteidx_tree(1, netif); + } + else + { + /* install default route */ + snmp_insert_iprteidx_tree(1, netif); + } + netif_default = netif; + LWIP_DEBUGF(NETIF_DEBUG, ("netif: setting default interface %c%c\n", + netif ? netif->name[0] : '\'', netif ? netif->name[1] : '\'')); +} + +/** + * Bring an interface up, available for processing + * traffic. + * + * @note: Enabling DHCP on a down interface will make it come + * up once configured. + * + * @see dhcp_start() + */ +void netif_set_up(struct netif *netif) +{ + netif->flags |= NETIF_FLAG_UP; +#if LWIP_SNMP + snmp_get_sysuptime(&netif->ts); +#endif +} + +/** + * Ask if an interface is up + */ +u8_t netif_is_up(struct netif *netif) +{ + return (netif->flags & NETIF_FLAG_UP)?1:0; +} + +/** + * Bring an interface down, disabling any traffic processing. + * + * @note: Enabling DHCP on a down interface will make it come + * up once configured. + * + * @see dhcp_start() + */ +void netif_set_down(struct netif *netif) +{ + netif->flags &= ~NETIF_FLAG_UP; +#if LWIP_SNMP + snmp_get_sysuptime(&netif->ts); +#endif +} + +void +netif_init(void) +{ + netif_list = netif_default = NULL; +} + diff --git a/20080212/Demo/Common/ethernet/lwIP/core/pbuf.c b/20080212/Demo/Common/ethernet/lwIP/core/pbuf.c new file mode 100644 index 000000000..1f6516d98 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/core/pbuf.c @@ -0,0 +1,964 @@ +/** + * @file + * Packet buffer management + * + * Packets are built from the pbuf data structure. It supports dynamic + * memory allocation for packet contents or can reference externally + * managed packet contents both in RAM and ROM. Quick allocation for + * incoming packets is provided through pools with fixed sized pbufs. + * + * A packet may span over multiple pbufs, chained as a singly linked + * list. This is called a "pbuf chain". + * + * Multiple packets may be queued, also using this singly linked list. + * This is called a "packet queue". + * + * So, a packet queue consists of one or more pbuf chains, each of + * which consist of one or more pbufs. Currently, queues are only + * supported in a limited section of lwIP, this is the etharp queueing + * code. Outside of this section no packet queues are supported yet. + * + * The differences between a pbuf chain and a packet queue are very + * precise but subtle. + * + * The last pbuf of a packet has a ->tot_len field that equals the + * ->len field. It can be found by traversing the list. If the last + * pbuf of a packet has a ->next field other than NULL, more packets + * are on the queue. + * + * Therefore, looping through a pbuf of a single packet, has an + * loop end condition (tot_len == p->len), NOT (next == NULL). + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include + +#include "lwip/opt.h" +#include "lwip/stats.h" +#include "lwip/def.h" +#include "lwip/mem.h" +#include "lwip/memp.h" +#include "lwip/pbuf.h" +#include "lwip/sys.h" +#include "arch/perf.h" + +static u8_t pbuf_pool_memory[MEM_ALIGNMENT - 1 + PBUF_POOL_SIZE * MEM_ALIGN_SIZE(PBUF_POOL_BUFSIZE + sizeof(struct pbuf))]; + +#if !SYS_LIGHTWEIGHT_PROT +static volatile u8_t pbuf_pool_free_lock, pbuf_pool_alloc_lock; +static sys_sem_t pbuf_pool_free_sem; +#endif + +static struct pbuf *pbuf_pool = NULL; + +/** + * Initializes the pbuf module. + * + * A large part of memory is allocated for holding the pool of pbufs. + * The size of the individual pbufs in the pool is given by the size + * parameter, and the number of pbufs in the pool by the num parameter. + * + * After the memory has been allocated, the pbufs are set up. The + * ->next pointer in each pbuf is set up to point to the next pbuf in + * the pool. + * + */ +void +pbuf_init(void) +{ + struct pbuf *p, *q = NULL; + u16_t i; + + pbuf_pool = (struct pbuf *)MEM_ALIGN(pbuf_pool_memory); + +#if PBUF_STATS + lwip_stats.pbuf.avail = PBUF_POOL_SIZE; +#endif /* PBUF_STATS */ + + /* Set up ->next pointers to link the pbufs of the pool together */ + p = pbuf_pool; + + for(i = 0; i < PBUF_POOL_SIZE; ++i) { + p->next = (struct pbuf *)((u8_t *)p + PBUF_POOL_BUFSIZE + sizeof(struct pbuf)); + p->len = p->tot_len = PBUF_POOL_BUFSIZE; + p->payload = MEM_ALIGN((void *)((u8_t *)p + sizeof(struct pbuf))); + p->flags = PBUF_FLAG_POOL; + q = p; + p = p->next; + } + + /* The ->next pointer of last pbuf is NULL to indicate that there + are no more pbufs in the pool */ + q->next = NULL; + +#if !SYS_LIGHTWEIGHT_PROT + pbuf_pool_alloc_lock = 0; + pbuf_pool_free_lock = 0; + pbuf_pool_free_sem = sys_sem_new(1); +#endif +} + +/** + * @internal only called from pbuf_alloc() + */ +static struct pbuf * +pbuf_pool_alloc(void) +{ + struct pbuf *p = NULL; + + SYS_ARCH_DECL_PROTECT(old_level); + SYS_ARCH_PROTECT(old_level); + +#if !SYS_LIGHTWEIGHT_PROT + /* Next, check the actual pbuf pool, but if the pool is locked, we + pretend to be out of buffers and return NULL. */ + if (pbuf_pool_free_lock) { +#if PBUF_STATS + ++lwip_stats.pbuf.alloc_locked; +#endif /* PBUF_STATS */ + return NULL; + } + pbuf_pool_alloc_lock = 1; + if (!pbuf_pool_free_lock) { +#endif /* SYS_LIGHTWEIGHT_PROT */ + p = pbuf_pool; + if (p) { + pbuf_pool = p->next; + } +#if !SYS_LIGHTWEIGHT_PROT +#if PBUF_STATS + } else { + ++lwip_stats.pbuf.alloc_locked; +#endif /* PBUF_STATS */ + } + pbuf_pool_alloc_lock = 0; +#endif /* SYS_LIGHTWEIGHT_PROT */ + +#if PBUF_STATS + if (p != NULL) { + ++lwip_stats.pbuf.used; + if (lwip_stats.pbuf.used > lwip_stats.pbuf.max) { + lwip_stats.pbuf.max = lwip_stats.pbuf.used; + } + } +#endif /* PBUF_STATS */ + + SYS_ARCH_UNPROTECT(old_level); + return p; +} + + +/** + * Allocates a pbuf of the given type (possibly a chain for PBUF_POOL type). + * + * The actual memory allocated for the pbuf is determined by the + * layer at which the pbuf is allocated and the requested size + * (from the size parameter). + * + * @param flag this parameter decides how and where the pbuf + * should be allocated as follows: + * + * - PBUF_RAM: buffer memory for pbuf is allocated as one large + * chunk. This includes protocol headers as well. + * - PBUF_ROM: no buffer memory is allocated for the pbuf, even for + * protocol headers. Additional headers must be prepended + * by allocating another pbuf and chain in to the front of + * the ROM pbuf. It is assumed that the memory used is really + * similar to ROM in that it is immutable and will not be + * changed. Memory which is dynamic should generally not + * be attached to PBUF_ROM pbufs. Use PBUF_REF instead. + * - PBUF_REF: no buffer memory is allocated for the pbuf, even for + * protocol headers. It is assumed that the pbuf is only + * being used in a single thread. If the pbuf gets queued, + * then pbuf_take should be called to copy the buffer. + * - PBUF_POOL: the pbuf is allocated as a pbuf chain, with pbufs from + * the pbuf pool that is allocated during pbuf_init(). + * + * @return the allocated pbuf. If multiple pbufs where allocated, this + * is the first pbuf of a pbuf chain. + */ +struct pbuf * +pbuf_alloc(pbuf_layer l, u16_t length, pbuf_flag flag) +{ + struct pbuf *p, *q, *r; + u16_t offset; + s32_t rem_len; /* remaining length */ + LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_alloc(length=%"U16_F")\n", length)); + + /* determine header offset */ + offset = 0; + switch (l) { + case PBUF_TRANSPORT: + /* add room for transport (often TCP) layer header */ + offset += PBUF_TRANSPORT_HLEN; + /* FALLTHROUGH */ + case PBUF_IP: + /* add room for IP layer header */ + offset += PBUF_IP_HLEN; + /* FALLTHROUGH */ + case PBUF_LINK: + /* add room for link layer header */ + offset += PBUF_LINK_HLEN; + break; + case PBUF_RAW: + break; + default: + LWIP_ASSERT("pbuf_alloc: bad pbuf layer", 0); + return NULL; + } + + switch (flag) { + case PBUF_POOL: + /* allocate head of pbuf chain into p */ + p = pbuf_pool_alloc(); + LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_alloc: allocated pbuf %p\n", (void *)p)); + if (p == NULL) { +#if PBUF_STATS + ++lwip_stats.pbuf.err; +#endif /* PBUF_STATS */ + return NULL; + } + p->next = NULL; + + /* make the payload pointer point 'offset' bytes into pbuf data memory */ + p->payload = MEM_ALIGN((void *)((u8_t *)p + (sizeof(struct pbuf) + offset))); + LWIP_ASSERT("pbuf_alloc: pbuf p->payload properly aligned", + ((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0); + /* the total length of the pbuf chain is the requested size */ + p->tot_len = length; + /* set the length of the first pbuf in the chain */ + p->len = length > PBUF_POOL_BUFSIZE - offset? PBUF_POOL_BUFSIZE - offset: length; + /* set reference count (needed here in case we fail) */ + p->ref = 1; + + /* now allocate the tail of the pbuf chain */ + + /* remember first pbuf for linkage in next iteration */ + r = p; + /* remaining length to be allocated */ + rem_len = length - p->len; + /* any remaining pbufs to be allocated? */ + while (rem_len > 0) { + q = pbuf_pool_alloc(); + if (q == NULL) { + LWIP_DEBUGF(PBUF_DEBUG | 2, ("pbuf_alloc: Out of pbufs in pool.\n")); +#if PBUF_STATS + ++lwip_stats.pbuf.err; +#endif /* PBUF_STATS */ + /* free chain so far allocated */ + pbuf_free(p); + /* bail out unsuccesfully */ + return NULL; + } + q->next = NULL; + /* make previous pbuf point to this pbuf */ + r->next = q; + /* set total length of this pbuf and next in chain */ + q->tot_len = rem_len; + /* this pbuf length is pool size, unless smaller sized tail */ + q->len = rem_len > PBUF_POOL_BUFSIZE? PBUF_POOL_BUFSIZE: rem_len; + q->payload = (void *)((u8_t *)q + sizeof(struct pbuf)); + LWIP_ASSERT("pbuf_alloc: pbuf q->payload properly aligned", + ((mem_ptr_t)q->payload % MEM_ALIGNMENT) == 0); + q->ref = 1; + /* calculate remaining length to be allocated */ + rem_len -= q->len; + /* remember this pbuf for linkage in next iteration */ + r = q; + } + /* end of chain */ + /*r->next = NULL;*/ + + break; + case PBUF_RAM: + /* If pbuf is to be allocated in RAM, allocate memory for it. */ + p = mem_malloc(MEM_ALIGN_SIZE(sizeof(struct pbuf) + offset) + MEM_ALIGN_SIZE(length)); + if (p == NULL) { + return NULL; + } + /* Set up internal structure of the pbuf. */ + p->payload = MEM_ALIGN((void *)((u8_t *)p + sizeof(struct pbuf) + offset)); + p->len = p->tot_len = length; + p->next = NULL; + p->flags = PBUF_FLAG_RAM; + + LWIP_ASSERT("pbuf_alloc: pbuf->payload properly aligned", + ((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0); + break; + /* pbuf references existing (non-volatile static constant) ROM payload? */ + case PBUF_ROM: + /* pbuf references existing (externally allocated) RAM payload? */ + case PBUF_REF: + /* only allocate memory for the pbuf structure */ + p = memp_malloc(MEMP_PBUF); + if (p == NULL) { + LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_alloc: Could not allocate MEMP_PBUF for PBUF_%s.\n", flag == PBUF_ROM?"ROM":"REF")); + + return NULL; + } + /* caller must set this field properly, afterwards */ + p->payload = NULL; + p->len = p->tot_len = length; + p->next = NULL; + p->flags = (flag == PBUF_ROM? PBUF_FLAG_ROM: PBUF_FLAG_REF); + break; + default: + LWIP_ASSERT("pbuf_alloc: erroneous flag", 0); + return NULL; + } + /* set reference count */ + p->ref = 1; + LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_alloc(length=%"U16_F") == %p\n", length, (void *)p)); + return p; +} + + +#if PBUF_STATS +#define DEC_PBUF_STATS do { --lwip_stats.pbuf.used; } while (0) +#else /* PBUF_STATS */ +#define DEC_PBUF_STATS +#endif /* PBUF_STATS */ + +#define PBUF_POOL_FAST_FREE(p) do { \ + p->next = pbuf_pool; \ + pbuf_pool = p; \ + DEC_PBUF_STATS; \ + } while (0) + +#if SYS_LIGHTWEIGHT_PROT +#define PBUF_POOL_FREE(p) do { \ + SYS_ARCH_DECL_PROTECT(old_level); \ + SYS_ARCH_PROTECT(old_level); \ + PBUF_POOL_FAST_FREE(p); \ + SYS_ARCH_UNPROTECT(old_level); \ + } while (0) +#else /* SYS_LIGHTWEIGHT_PROT */ +#define PBUF_POOL_FREE(p) do { \ + sys_sem_wait(pbuf_pool_free_sem); \ + PBUF_POOL_FAST_FREE(p); \ + sys_sem_signal(pbuf_pool_free_sem); \ + } while (0) +#endif /* SYS_LIGHTWEIGHT_PROT */ + +/** + * Shrink a pbuf chain to a desired length. + * + * @param p pbuf to shrink. + * @param new_len desired new length of pbuf chain + * + * Depending on the desired length, the first few pbufs in a chain might + * be skipped and left unchanged. The new last pbuf in the chain will be + * resized, and any remaining pbufs will be freed. + * + * @note If the pbuf is ROM/REF, only the ->tot_len and ->len fields are adjusted. + * @note May not be called on a packet queue. + * + * @bug Cannot grow the size of a pbuf (chain) (yet). + */ +void +pbuf_realloc(struct pbuf *p, u16_t new_len) +{ + struct pbuf *q; + u16_t rem_len; /* remaining length */ + s16_t grow; + + LWIP_ASSERT("pbuf_realloc: sane p->flags", p->flags == PBUF_FLAG_POOL || + p->flags == PBUF_FLAG_ROM || + p->flags == PBUF_FLAG_RAM || + p->flags == PBUF_FLAG_REF); + + /* desired length larger than current length? */ + if (new_len >= p->tot_len) { + /* enlarging not yet supported */ + return; + } + + /* the pbuf chain grows by (new_len - p->tot_len) bytes + * (which may be negative in case of shrinking) */ + grow = new_len - p->tot_len; + + /* first, step over any pbufs that should remain in the chain */ + rem_len = new_len; + q = p; + /* should this pbuf be kept? */ + while (rem_len > q->len) { + /* decrease remaining length by pbuf length */ + rem_len -= q->len; + /* decrease total length indicator */ + q->tot_len += grow; + /* proceed to next pbuf in chain */ + q = q->next; + } + /* we have now reached the new last pbuf (in q) */ + /* rem_len == desired length for pbuf q */ + + /* shrink allocated memory for PBUF_RAM */ + /* (other types merely adjust their length fields */ + if ((q->flags == PBUF_FLAG_RAM) && (rem_len != q->len)) { + /* reallocate and adjust the length of the pbuf that will be split */ + mem_realloc(q, (u8_t *)q->payload - (u8_t *)q + rem_len); + } + /* adjust length fields for new last pbuf */ + q->len = rem_len; + q->tot_len = q->len; + + /* any remaining pbufs in chain? */ + if (q->next != NULL) { + /* free remaining pbufs in chain */ + pbuf_free(q->next); + } + /* q is last packet in chain */ + q->next = NULL; + +} + +/** + * Adjusts the payload pointer to hide or reveal headers in the payload. + * + * Adjusts the ->payload pointer so that space for a header + * (dis)appears in the pbuf payload. + * + * The ->payload, ->tot_len and ->len fields are adjusted. + * + * @param hdr_size_inc Number of bytes to increment header size which + * increases the size of the pbuf. New space is on the front. + * (Using a negative value decreases the header size.) + * If hdr_size_inc is 0, this function does nothing and returns succesful. + * + * PBUF_ROM and PBUF_REF type buffers cannot have their sizes increased, so + * the call will fail. A check is made that the increase in header size does + * not move the payload pointer in front of the start of the buffer. + * @return non-zero on failure, zero on success. + * + */ +u8_t +pbuf_header(struct pbuf *p, s16_t header_size_increment) +{ + u16_t flags; + void *payload; + + LWIP_ASSERT("p != NULL", p != NULL); + if ((header_size_increment == 0) || (p == NULL)) return 0; + + flags = p->flags; + /* remember current payload pointer */ + payload = p->payload; + + /* pbuf types containing payloads? */ + if (flags == PBUF_FLAG_RAM || flags == PBUF_FLAG_POOL) { + /* set new payload pointer */ + p->payload = (u8_t *)p->payload - header_size_increment; + /* boundary check fails? */ + if ((u8_t *)p->payload < (u8_t *)p + sizeof(struct pbuf)) { + LWIP_DEBUGF( PBUF_DEBUG | 2, ("pbuf_header: failed as %p < %p (not enough space for new header size)\n", + (void *)p->payload, + (void *)(p + 1)));\ + /* restore old payload pointer */ + p->payload = payload; + /* bail out unsuccesfully */ + return 1; + } + /* pbuf types refering to external payloads? */ + } else if (flags == PBUF_FLAG_REF || flags == PBUF_FLAG_ROM) { + /* hide a header in the payload? */ + if ((header_size_increment < 0) && (header_size_increment - p->len <= 0)) { + /* increase payload pointer */ + p->payload = (u8_t *)p->payload - header_size_increment; + } else { + /* cannot expand payload to front (yet!) + * bail out unsuccesfully */ + return 1; + } + } + /* modify pbuf length fields */ + p->len += header_size_increment; + p->tot_len += header_size_increment; + + LWIP_DEBUGF( PBUF_DEBUG, ("pbuf_header: old %p new %p (%"S16_F")\n", + (void *)payload, (void *)p->payload, header_size_increment)); + + return 0; +} + +/** + * Dereference a pbuf chain or queue and deallocate any no-longer-used + * pbufs at the head of this chain or queue. + * + * Decrements the pbuf reference count. If it reaches zero, the pbuf is + * deallocated. + * + * For a pbuf chain, this is repeated for each pbuf in the chain, + * up to the first pbuf which has a non-zero reference count after + * decrementing. So, when all reference counts are one, the whole + * chain is free'd. + * + * @param pbuf The pbuf (chain) to be dereferenced. + * + * @return the number of pbufs that were de-allocated + * from the head of the chain. + * + * @note MUST NOT be called on a packet queue (Not verified to work yet). + * @note the reference counter of a pbuf equals the number of pointers + * that refer to the pbuf (or into the pbuf). + * + * @internal examples: + * + * Assuming existing chains a->b->c with the following reference + * counts, calling pbuf_free(a) results in: + * + * 1->2->3 becomes ...1->3 + * 3->3->3 becomes 2->3->3 + * 1->1->2 becomes ......1 + * 2->1->1 becomes 1->1->1 + * 1->1->1 becomes ....... + * + */ +u8_t +pbuf_free(struct pbuf *p) +{ + u16_t flags; + struct pbuf *q; + u8_t count; + SYS_ARCH_DECL_PROTECT(old_level); + + LWIP_ASSERT("p != NULL", p != NULL); + + /* if assertions are disabled, proceed with debug output */ + if (p == NULL) { + LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_free(p == NULL) was called.\n")); + return 0; + } + LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_free(%p)\n", (void *)p)); + + PERF_START; + + LWIP_ASSERT("pbuf_free: sane flags", + p->flags == PBUF_FLAG_RAM || p->flags == PBUF_FLAG_ROM || + p->flags == PBUF_FLAG_REF || p->flags == PBUF_FLAG_POOL); + + count = 0; + /* Since decrementing ref cannot be guaranteed to be a single machine operation + * we must protect it. Also, the later test of ref must be protected. + */ + SYS_ARCH_PROTECT(old_level); + /* de-allocate all consecutive pbufs from the head of the chain that + * obtain a zero reference count after decrementing*/ + while (p != NULL) { + /* all pbufs in a chain are referenced at least once */ + LWIP_ASSERT("pbuf_free: p->ref > 0", p->ref > 0); + /* decrease reference count (number of pointers to pbuf) */ + p->ref--; + /* this pbuf is no longer referenced to? */ + if (p->ref == 0) { + /* remember next pbuf in chain for next iteration */ + q = p->next; + LWIP_DEBUGF( PBUF_DEBUG | 2, ("pbuf_free: deallocating %p\n", (void *)p)); + flags = p->flags; + /* is this a pbuf from the pool? */ + if (flags == PBUF_FLAG_POOL) { + p->len = p->tot_len = PBUF_POOL_BUFSIZE; + p->payload = (void *)((u8_t *)p + sizeof(struct pbuf)); + PBUF_POOL_FREE(p); + /* is this a ROM or RAM referencing pbuf? */ + } else if (flags == PBUF_FLAG_ROM || flags == PBUF_FLAG_REF) { + memp_free(MEMP_PBUF, p); + /* flags == PBUF_FLAG_RAM */ + } else { + mem_free(p); + } + count++; + /* proceed to next pbuf */ + p = q; + /* p->ref > 0, this pbuf is still referenced to */ + /* (and so the remaining pbufs in chain as well) */ + } else { + LWIP_DEBUGF( PBUF_DEBUG | 2, ("pbuf_free: %p has ref %"U16_F", ending here.\n", (void *)p, (u16_t)p->ref)); + /* stop walking through the chain */ + p = NULL; + } + } + SYS_ARCH_UNPROTECT(old_level); + PERF_STOP("pbuf_free"); + /* return number of de-allocated pbufs */ + + return count; +} + +/** + * Count number of pbufs in a chain + * + * @param p first pbuf of chain + * @return the number of pbufs in a chain + */ + +u8_t +pbuf_clen(struct pbuf *p) +{ + u8_t len; + + len = 0; + while (p != NULL) { + ++len; + p = p->next; + } + return len; +} + +/** + * Increment the reference count of the pbuf. + * + * @param p pbuf to increase reference counter of + * + */ +void +pbuf_ref(struct pbuf *p) +{ + SYS_ARCH_DECL_PROTECT(old_level); + /* pbuf given? */ + if (p != NULL) { + SYS_ARCH_PROTECT(old_level); + ++(p->ref); + SYS_ARCH_UNPROTECT(old_level); + } +} + +/** + * Concatenate two pbufs (each may be a pbuf chain) and take over + * the caller's reference of the tail pbuf. + * + * @note The caller MAY NOT reference the tail pbuf afterwards. + * Use pbuf_chain() for that purpose. + * + * @see pbuf_chain() + */ + +void +pbuf_cat(struct pbuf *h, struct pbuf *t) +{ + struct pbuf *p; + + LWIP_ASSERT("h != NULL (programmer violates API)", h != NULL); + LWIP_ASSERT("t != NULL (programmer violates API)", t != NULL); + if ((h == NULL) || (t == NULL)) return; + + /* proceed to last pbuf of chain */ + for (p = h; p->next != NULL; p = p->next) { + /* add total length of second chain to all totals of first chain */ + p->tot_len += t->tot_len; + } + /* { p is last pbuf of first h chain, p->next == NULL } */ + LWIP_ASSERT("p->tot_len == p->len (of last pbuf in chain)", p->tot_len == p->len); + LWIP_ASSERT("p->next == NULL", p->next == NULL); + /* add total length of second chain to last pbuf total of first chain */ + p->tot_len += t->tot_len; + /* chain last pbuf of head (p) with first of tail (t) */ + p->next = t; + /* p->next now references t, but the caller will drop its reference to t, + * so netto there is no change to the reference count of t. + */ +} + +/** + * Chain two pbufs (or pbuf chains) together. + * + * The caller MUST call pbuf_free(t) once it has stopped + * using it. Use pbuf_cat() instead if you no longer use t. + * + * @param h head pbuf (chain) + * @param t tail pbuf (chain) + * @note The pbufs MUST belong to the same packet. + * @note MAY NOT be called on a packet queue. + * + * The ->tot_len fields of all pbufs of the head chain are adjusted. + * The ->next field of the last pbuf of the head chain is adjusted. + * The ->ref field of the first pbuf of the tail chain is adjusted. + * + */ +void +pbuf_chain(struct pbuf *h, struct pbuf *t) +{ + pbuf_cat(h, t); + /* t is now referenced by h */ + pbuf_ref(t); + LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2, ("pbuf_chain: %p references %p\n", (void *)h, (void *)t)); +} + +/* For packet queueing. Note that queued packets MUST be dequeued first + * using pbuf_dequeue() before calling other pbuf_() functions. */ +#if ARP_QUEUEING +/** + * Add a packet to the end of a queue. + * + * @param q pointer to first packet on the queue + * @param n packet to be queued + * + * Both packets MUST be given, and must be different. + */ +void +pbuf_queue(struct pbuf *p, struct pbuf *n) +{ +#if PBUF_DEBUG /* remember head of queue */ + struct pbuf *q = p; +#endif + /* programmer stupidity checks */ + LWIP_ASSERT("p == NULL in pbuf_queue: this indicates a programmer error\n", p != NULL); + LWIP_ASSERT("n == NULL in pbuf_queue: this indicates a programmer error\n", n != NULL); + LWIP_ASSERT("p == n in pbuf_queue: this indicates a programmer error\n", p != n); + if ((p == NULL) || (n == NULL) || (p == n)){ + LWIP_DEBUGF(PBUF_DEBUG | DBG_HALT | 3, ("pbuf_queue: programmer argument error\n")); + return; + } + + /* iterate through all packets on queue */ + while (p->next != NULL) { +/* be very picky about pbuf chain correctness */ +#if PBUF_DEBUG + /* iterate through all pbufs in packet */ + while (p->tot_len != p->len) { + /* make sure invariant condition holds */ + LWIP_ASSERT("p->len < p->tot_len", p->len < p->tot_len); + /* make sure each packet is complete */ + LWIP_ASSERT("p->next != NULL", p->next != NULL); + p = p->next; + /* { p->tot_len == p->len => p is last pbuf of a packet } */ + } + /* { p is last pbuf of a packet } */ + /* proceed to next packet on queue */ +#endif + /* proceed to next pbuf */ + if (p->next != NULL) p = p->next; + } + /* { p->tot_len == p->len and p->next == NULL } ==> + * { p is last pbuf of last packet on queue } */ + /* chain last pbuf of queue with n */ + p->next = n; + /* n is now referenced to by the (packet p in the) queue */ + pbuf_ref(n); +#if PBUF_DEBUG + LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2, + ("pbuf_queue: newly queued packet %p sits after packet %p in queue %p\n", + (void *)n, (void *)p, (void *)q)); +#endif +} + +/** + * Remove a packet from the head of a queue. + * + * The caller MUST reference the remainder of the queue (as returned). The + * caller MUST NOT call pbuf_ref() as it implicitly takes over the reference + * from p. + * + * @param p pointer to first packet on the queue which will be dequeued. + * @return first packet on the remaining queue (NULL if no further packets). + * + */ +struct pbuf * +pbuf_dequeue(struct pbuf *p) +{ + struct pbuf *q; + LWIP_ASSERT("p != NULL", p != NULL); + + /* iterate through all pbufs in packet p */ + while (p->tot_len != p->len) { + /* make sure invariant condition holds */ + LWIP_ASSERT("p->len < p->tot_len", p->len < p->tot_len); + /* make sure each packet is complete */ + LWIP_ASSERT("p->next != NULL", p->next != NULL); + p = p->next; + } + /* { p->tot_len == p->len } => p is the last pbuf of the first packet */ + /* remember next packet on queue in q */ + q = p->next; + /* dequeue packet p from queue */ + p->next = NULL; + /* any next packet on queue? */ + if (q != NULL) { + /* although q is no longer referenced by p, it MUST be referenced by + * the caller, who is maintaining this packet queue. So, we do not call + * pbuf_free(q) here, resulting in an implicit pbuf_ref(q) for the caller. */ + LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2, ("pbuf_dequeue: first remaining packet on queue is %p\n", (void *)q)); + } else { + LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2, ("pbuf_dequeue: no further packets on queue\n")); + } + return q; +} +#endif + +/** + * + * Create PBUF_POOL (or PBUF_RAM) copies of PBUF_REF pbufs. + * + * Used to queue packets on behalf of the lwIP stack, such as + * ARP based queueing. + * + * Go through a pbuf chain and replace any PBUF_REF buffers + * with PBUF_POOL (or PBUF_RAM) pbufs, each taking a copy of + * the referenced data. + * + * @note You MUST explicitly use p = pbuf_take(p); + * The pbuf you give as argument, may have been replaced + * by a (differently located) copy through pbuf_take()! + * + * @note Any replaced pbufs will be freed through pbuf_free(). + * This may deallocate them if they become no longer referenced. + * + * @param p Head of pbuf chain to process + * + * @return Pointer to head of pbuf chain + */ +struct pbuf * +pbuf_take(struct pbuf *p) +{ + struct pbuf *q , *prev, *head; + LWIP_ASSERT("pbuf_take: p != NULL\n", p != NULL); + LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_take(%p)\n", (void*)p)); + + prev = NULL; + head = p; + /* iterate through pbuf chain */ + do + { + /* pbuf is of type PBUF_REF? */ + if (p->flags == PBUF_FLAG_REF) { + LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE, ("pbuf_take: encountered PBUF_REF %p\n", (void *)p)); + /* allocate a pbuf (w/ payload) fully in RAM */ + /* PBUF_POOL buffers are faster if we can use them */ + if (p->len <= PBUF_POOL_BUFSIZE) { + q = pbuf_alloc(PBUF_RAW, p->len, PBUF_POOL); + if (q == NULL) { + LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_take: Could not allocate PBUF_POOL\n")); + } + } else { + /* no replacement pbuf yet */ + q = NULL; + LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_take: PBUF_POOL too small to replace PBUF_REF\n")); + } + /* no (large enough) PBUF_POOL was available? retry with PBUF_RAM */ + if (q == NULL) { + q = pbuf_alloc(PBUF_RAW, p->len, PBUF_RAM); + if (q == NULL) { + LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_take: Could not allocate PBUF_RAM\n")); + } + } + /* replacement pbuf could be allocated? */ + if (q != NULL) + { + /* copy p to q */ + /* copy successor */ + q->next = p->next; + /* remove linkage from original pbuf */ + p->next = NULL; + /* remove linkage to original pbuf */ + if (prev != NULL) { + /* prev->next == p at this point */ + LWIP_ASSERT("prev->next == p", prev->next == p); + /* break chain and insert new pbuf instead */ + prev->next = q; + /* prev == NULL, so we replaced the head pbuf of the chain */ + } else { + head = q; + } + /* copy pbuf payload */ + memcpy(q->payload, p->payload, p->len); + q->tot_len = p->tot_len; + q->len = p->len; + /* in case p was the first pbuf, it is no longer refered to by + * our caller, as the caller MUST do p = pbuf_take(p); + * in case p was not the first pbuf, it is no longer refered to + * by prev. we can safely free the pbuf here. + * (note that we have set p->next to NULL already so that + * we will not free the rest of the chain by accident.) + */ + pbuf_free(p); + /* do not copy ref, since someone else might be using the old buffer */ + LWIP_DEBUGF(PBUF_DEBUG, ("pbuf_take: replaced PBUF_REF %p with %p\n", (void *)p, (void *)q)); + p = q; + } else { + /* deallocate chain */ + pbuf_free(head); + LWIP_DEBUGF(PBUF_DEBUG | 2, ("pbuf_take: failed to allocate replacement pbuf for %p\n", (void *)p)); + return NULL; + } + /* p->flags != PBUF_FLAG_REF */ + } else { + LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 1, ("pbuf_take: skipping pbuf not of type PBUF_REF\n")); + } + /* remember this pbuf */ + prev = p; + /* proceed to next pbuf in original chain */ + p = p->next; + } while (p); + LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 1, ("pbuf_take: end of chain reached.\n")); + + return head; +} + +/** + * Dechains the first pbuf from its succeeding pbufs in the chain. + * + * Makes p->tot_len field equal to p->len. + * @param p pbuf to dechain + * @return remainder of the pbuf chain, or NULL if it was de-allocated. + * @note May not be called on a packet queue. + */ +struct pbuf * +pbuf_dechain(struct pbuf *p) +{ + struct pbuf *q; + u8_t tail_gone = 1; + /* tail */ + q = p->next; + /* pbuf has successor in chain? */ + if (q != NULL) { + /* assert tot_len invariant: (p->tot_len == p->len + (p->next? p->next->tot_len: 0) */ + LWIP_ASSERT("p->tot_len == p->len + q->tot_len", q->tot_len == p->tot_len - p->len); + /* enforce invariant if assertion is disabled */ + q->tot_len = p->tot_len - p->len; + /* decouple pbuf from remainder */ + p->next = NULL; + /* total length of pbuf p is its own length only */ + p->tot_len = p->len; + /* q is no longer referenced by p, free it */ + LWIP_DEBUGF(PBUF_DEBUG | DBG_STATE, ("pbuf_dechain: unreferencing %p\n", (void *)q)); + tail_gone = pbuf_free(q); + if (tail_gone > 0) { + LWIP_DEBUGF(PBUF_DEBUG | DBG_STATE, + ("pbuf_dechain: deallocated %p (as it is no longer referenced)\n", (void *)q)); + } + /* return remaining tail or NULL if deallocated */ + } + /* assert tot_len invariant: (p->tot_len == p->len + (p->next? p->next->tot_len: 0) */ + LWIP_ASSERT("p->tot_len == p->len", p->tot_len == p->len); + return (tail_gone > 0? NULL: q); +} diff --git a/20080212/Demo/Common/ethernet/lwIP/core/raw.c b/20080212/Demo/Common/ethernet/lwIP/core/raw.c new file mode 100644 index 000000000..b0e18b015 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/core/raw.c @@ -0,0 +1,326 @@ +/** + * @file + * + * Implementation of raw protocol PCBs for low-level handling of + * different types of protocols besides (or overriding) those + * already available in lwIP. + * + */ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include + +#include "lwip/opt.h" + +#include "lwip/def.h" +#include "lwip/memp.h" +#include "lwip/inet.h" +#include "lwip/ip_addr.h" +#include "lwip/netif.h" +#include "lwip/raw.h" + +#include "lwip/stats.h" + +#include "arch/perf.h" +#include "lwip/snmp.h" + +#if LWIP_RAW + +/** The list of RAW PCBs */ +static struct raw_pcb *raw_pcbs = NULL; + +void +raw_init(void) +{ + raw_pcbs = NULL; +} + +/** + * Determine if in incoming IP packet is covered by a RAW PCB + * and if so, pass it to a user-provided receive callback function. + * + * Given an incoming IP datagram (as a chain of pbufs) this function + * finds a corresponding RAW PCB and calls the corresponding receive + * callback function. + * + * @param pbuf pbuf to be demultiplexed to a RAW PCB. + * @param netif network interface on which the datagram was received. + * @Return - 1 if the packet has been eaten by a RAW PCB receive + * callback function. The caller MAY NOT not reference the + * packet any longer, and MAY NOT call pbuf_free(). + * @return - 0 if packet is not eaten (pbuf is still referenced by the + * caller). + * + */ +u8_t +raw_input(struct pbuf *p, struct netif *inp) +{ + struct raw_pcb *pcb; + struct ip_hdr *iphdr; + s16_t proto; + u8_t eaten = 0; + + iphdr = p->payload; + proto = IPH_PROTO(iphdr); + + pcb = raw_pcbs; + /* loop through all raw pcbs until the packet is eaten by one */ + /* this allows multiple pcbs to match against the packet by design */ + while ((eaten == 0) && (pcb != NULL)) { + if (pcb->protocol == proto) { + /* receive callback function available? */ + if (pcb->recv != NULL) { + /* the receive callback function did not eat the packet? */ + if (pcb->recv(pcb->recv_arg, pcb, p, &(iphdr->src)) != 0) + { + /* receive function ate the packet */ + p = NULL; + eaten = 1; + } + } + /* no receive callback function was set for this raw PCB */ + /* drop the packet */ + } + pcb = pcb->next; + } + return eaten; +} + +/** + * Bind a RAW PCB. + * + * @param pcb RAW PCB to be bound with a local address ipaddr. + * @param ipaddr local IP address to bind with. Use IP_ADDR_ANY to + * bind to all local interfaces. + * + * @return lwIP error code. + * - ERR_OK. Successful. No error occured. + * - ERR_USE. The specified IP address is already bound to by + * another RAW PCB. + * + * @see raw_disconnect() + */ +err_t +raw_bind(struct raw_pcb *pcb, struct ip_addr *ipaddr) +{ + ip_addr_set(&pcb->local_ip, ipaddr); + return ERR_OK; +} + +/** + * Connect an RAW PCB. This function is required by upper layers + * of lwip. Using the raw api you could use raw_sendto() instead + * + * This will associate the RAW PCB with the remote address. + * + * @param pcb RAW PCB to be connected with remote address ipaddr and port. + * @param ipaddr remote IP address to connect with. + * + * @return lwIP error code + * + * @see raw_disconnect() and raw_sendto() + */ +err_t +raw_connect(struct raw_pcb *pcb, struct ip_addr *ipaddr) +{ + ip_addr_set(&pcb->remote_ip, ipaddr); + return ERR_OK; +} + + +/** + * Set the callback function for received packets that match the + * raw PCB's protocol and binding. + * + * The callback function MUST either + * - eat the packet by calling pbuf_free() and returning non-zero. The + * packet will not be passed to other raw PCBs or other protocol layers. + * - not free the packet, and return zero. The packet will be matched + * against further PCBs and/or forwarded to another protocol layers. + * + * @return non-zero if the packet was free()d, zero if the packet remains + * available for others. + */ +void +raw_recv(struct raw_pcb *pcb, + u8_t (* recv)(void *arg, struct raw_pcb *upcb, struct pbuf *p, + struct ip_addr *addr), + void *recv_arg) +{ + /* remember recv() callback and user data */ + pcb->recv = recv; + pcb->recv_arg = recv_arg; +} + +/** + * Send the raw IP packet to the given address. Note that actually you cannot + * modify the IP headers (this is inconsistent with the receive callback where + * you actually get the IP headers), you can only specify the IP payload here. + * It requires some more changes in lwIP. (there will be a raw_send() function + * then.) + * + * @param pcb the raw pcb which to send + * @param p the IP payload to send + * @param ipaddr the destination address of the IP packet + * + */ +err_t +raw_sendto(struct raw_pcb *pcb, struct pbuf *p, struct ip_addr *ipaddr) +{ + err_t err; + struct netif *netif; + struct ip_addr *src_ip; + struct pbuf *q; /* q will be sent down the stack */ + + LWIP_DEBUGF(RAW_DEBUG | DBG_TRACE | 3, ("raw_sendto\n")); + + /* not enough space to add an IP header to first pbuf in given p chain? */ + if (pbuf_header(p, IP_HLEN)) { + /* allocate header in new pbuf */ + q = pbuf_alloc(PBUF_IP, 0, PBUF_RAM); + /* new header pbuf could not be allocated? */ + if (q == NULL) { + LWIP_DEBUGF(RAW_DEBUG | DBG_TRACE | 2, ("raw_sendto: could not allocate header\n")); + return ERR_MEM; + } + /* chain header q in front of given pbuf p */ + pbuf_chain(q, p); + /* { first pbuf q points to header pbuf } */ + LWIP_DEBUGF(RAW_DEBUG, ("raw_sendto: added header pbuf %p before given pbuf %p\n", (void *)q, (void *)p)); + } else { + /* first pbuf q equals given pbuf */ + q = p; + pbuf_header(q, -IP_HLEN); + } + + if ((netif = ip_route(ipaddr)) == NULL) { + LWIP_DEBUGF(RAW_DEBUG | 1, ("raw_sendto: No route to 0x%"X32_F"\n", ipaddr->addr)); +#if RAW_STATS + /* ++lwip_stats.raw.rterr;*/ +#endif /* RAW_STATS */ + /* free any temporary header pbuf allocated by pbuf_header() */ + if (q != p) { + pbuf_free(q); + } + return ERR_RTE; + } + + if (ip_addr_isany(&pcb->local_ip)) { + /* use outgoing network interface IP address as source address */ + src_ip = &(netif->ip_addr); + } else { + /* use RAW PCB local IP address as source address */ + src_ip = &(pcb->local_ip); + } + + err = ip_output_if (q, src_ip, ipaddr, pcb->ttl, pcb->tos, pcb->protocol, netif); + + /* did we chain a header earlier? */ + if (q != p) { + /* free the header */ + pbuf_free(q); + } + return err; +} + +/** + * Send the raw IP packet to the address given by raw_connect() + * + * @param pcb the raw pcb which to send + * @param p the IP payload to send + * @param ipaddr the destination address of the IP packet + * + */ +err_t +raw_send(struct raw_pcb *pcb, struct pbuf *p) +{ + return raw_sendto(pcb, p, &pcb->remote_ip); +} + +/** + * Remove an RAW PCB. + * + * @param pcb RAW PCB to be removed. The PCB is removed from the list of + * RAW PCB's and the data structure is freed from memory. + * + * @see raw_new() + */ +void +raw_remove(struct raw_pcb *pcb) +{ + struct raw_pcb *pcb2; + /* pcb to be removed is first in list? */ + if (raw_pcbs == pcb) { + /* make list start at 2nd pcb */ + raw_pcbs = raw_pcbs->next; + /* pcb not 1st in list */ + } else for(pcb2 = raw_pcbs; pcb2 != NULL; pcb2 = pcb2->next) { + /* find pcb in raw_pcbs list */ + if (pcb2->next != NULL && pcb2->next == pcb) { + /* remove pcb from list */ + pcb2->next = pcb->next; + } + } + memp_free(MEMP_RAW_PCB, pcb); +} + +/** + * Create a RAW PCB. + * + * @return The RAW PCB which was created. NULL if the PCB data structure + * could not be allocated. + * + * @param proto the protocol number of the IPs payload (e.g. IP_PROTO_ICMP) + * + * @see raw_remove() + */ +struct raw_pcb * +raw_new(u16_t proto) { + struct raw_pcb *pcb; + + LWIP_DEBUGF(RAW_DEBUG | DBG_TRACE | 3, ("raw_new\n")); + + pcb = memp_malloc(MEMP_RAW_PCB); + /* could allocate RAW PCB? */ + if (pcb != NULL) { + /* initialize PCB to all zeroes */ + memset(pcb, 0, sizeof(struct raw_pcb)); + pcb->protocol = proto; + pcb->ttl = RAW_TTL; + pcb->next = raw_pcbs; + raw_pcbs = pcb; + } + return pcb; +} + +#endif /* LWIP_RAW */ diff --git a/20080212/Demo/Common/ethernet/lwIP/core/snmp/asn1_dec.c b/20080212/Demo/Common/ethernet/lwIP/core/snmp/asn1_dec.c new file mode 100644 index 000000000..a556eddd0 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/core/snmp/asn1_dec.c @@ -0,0 +1,652 @@ +/** + * @file + * Abstract Syntax Notation One (ISO 8824, 8825) decoding + * + * @todo not optimised (yet), favor correctness over speed, favor speed over size + */ + +/* + * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Christiaan Simons + */ + +#include "lwip/opt.h" + +#if LWIP_SNMP +#include "lwip/snmp_asn1.h" + +/** + * Retrieves type field from incoming pbuf chain. + * + * @param p points to a pbuf holding an ASN1 coded type field + * @param ofs points to the offset within the pbuf chain of the ASN1 coded type field + * @param type return ASN1 type + * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode + */ +err_t +snmp_asn1_dec_type(struct pbuf *p, u16_t ofs, u8_t *type) +{ + u16_t plen, base; + u8_t *msg_ptr; + + plen = 0; + while (p != NULL) + { + base = plen; + plen += p->len; + if (ofs < plen) + { + msg_ptr = p->payload; + msg_ptr += ofs - base; + *type = *msg_ptr; + return ERR_OK; + } + p = p->next; + } + /* p == NULL, ofs >= plen */ + return ERR_ARG; +} + +/** + * Decodes length field from incoming pbuf chain into host length. + * + * @param p points to a pbuf holding an ASN1 coded length + * @param ofs points to the offset within the pbuf chain of the ASN1 coded length + * @param octets_used returns number of octets used by the length code + * @param length return host order length, upto 64k + * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode + */ +err_t +snmp_asn1_dec_length(struct pbuf *p, u16_t ofs, u8_t *octets_used, u16_t *length) +{ + u16_t plen, base; + u8_t *msg_ptr; + + plen = 0; + while (p != NULL) + { + base = plen; + plen += p->len; + if (ofs < plen) + { + msg_ptr = p->payload; + msg_ptr += ofs - base; + + if (*msg_ptr < 0x80) + { + /* primitive definite length format */ + *octets_used = 1; + *length = *msg_ptr; + return ERR_OK; + } + else if (*msg_ptr == 0x80) + { + /* constructed indefinite length format, termination with two zero octets */ + u8_t zeros; + u8_t i; + + *length = 0; + zeros = 0; + while (zeros != 2) + { + i = 2; + while (i > 0) + { + i--; + (*length) += 1; + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + if (*msg_ptr == 0) + { + zeros++; + if (zeros == 2) + { + /* stop while (i > 0) */ + i = 0; + } + } + else + { + zeros = 0; + } + } + } + *octets_used = 1; + return ERR_OK; + } + else if (*msg_ptr == 0x81) + { + /* constructed definite length format, one octet */ + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = p->payload; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + *length = *msg_ptr; + *octets_used = 2; + return ERR_OK; + } + else if (*msg_ptr == 0x82) + { + u8_t i; + + /* constructed definite length format, two octets */ + i = 2; + while (i > 0) + { + i--; + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + if (i == 0) + { + /* least significant length octet */ + *length |= *msg_ptr; + } + else + { + /* most significant length octet */ + *length = (*msg_ptr) << 8; + } + } + *octets_used = 3; + return ERR_OK; + } + else + { + /* constructed definite length format 3..127 octets, this is too big (>64k) */ + /** @todo: do we need to accept inefficient codings with many leading zero's? */ + *octets_used = 1 + ((*msg_ptr) & 0x7f); + return ERR_ARG; + } + } + p = p->next; + } + + /* p == NULL, ofs >= plen */ + return ERR_ARG; +} + +/** + * Decodes positive integer (counter, gauge, timeticks) into u32_t. + * + * @param p points to a pbuf holding an ASN1 coded integer + * @param ofs points to the offset within the pbuf chain of the ASN1 coded integer + * @param len length of the coded integer field + * @param value return host order integer + * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode + * + * @note ASN coded integers are _always_ signed. E.g. +0xFFFF is coded + * as 0x00,0xFF,0xFF. Note the leading sign octet. A positive value + * of 0xFFFFFFFF is preceded with 0x00 and the length is 5 octets!! + */ +err_t +snmp_asn1_dec_u32t(struct pbuf *p, u16_t ofs, u16_t len, u32_t *value) +{ + u16_t plen, base; + u8_t *msg_ptr; + + plen = 0; + while (p != NULL) + { + base = plen; + plen += p->len; + if (ofs < plen) + { + msg_ptr = p->payload; + msg_ptr += ofs - base; + if ((len > 0) && (len < 6)) + { + /* start from zero */ + *value = 0; + if (*msg_ptr & 0x80) + { + /* negative, expecting zero sign bit! */ + return ERR_ARG; + } + else + { + /* positive */ + if ((len > 1) && (*msg_ptr == 0)) + { + /* skip leading "sign byte" octet 0x00 */ + len--; + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + } + } + /* OR octets with value */ + while (len > 1) + { + len--; + *value |= *msg_ptr; + *value <<= 8; + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + } + *value |= *msg_ptr; + return ERR_OK; + } + else + { + return ERR_ARG; + } + } + p = p->next; + } + /* p == NULL, ofs >= plen */ + return ERR_ARG; +} + +/** + * Decodes integer into s32_t. + * + * @param p points to a pbuf holding an ASN1 coded integer + * @param ofs points to the offset within the pbuf chain of the ASN1 coded integer + * @param len length of the coded integer field + * @param value return host order integer + * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode + * + * @note ASN coded integers are _always_ signed! + */ +err_t +snmp_asn1_dec_s32t(struct pbuf *p, u16_t ofs, u16_t len, s32_t *value) +{ + u16_t plen, base; + u8_t *msg_ptr; + u8_t *lsb_ptr = (u8_t*)value; + u8_t sign; + + plen = 0; + while (p != NULL) + { + base = plen; + plen += p->len; + if (ofs < plen) + { + msg_ptr = p->payload; + msg_ptr += ofs - base; + if ((len > 0) && (len < 5)) + { + if (*msg_ptr & 0x80) + { + /* negative, start from -1 */ + *value = -1; + sign = 1; + } + else + { + /* positive, start from 0 */ + *value = 0; + sign = 0; + } + /* OR/AND octets with value */ + while (len > 1) + { + len--; + if (sign) + { + *lsb_ptr &= *msg_ptr; + *value <<= 8; + *lsb_ptr |= 255; + } + else + { + *lsb_ptr |= *msg_ptr; + *value <<= 8; + } + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + } + if (sign) + { + *lsb_ptr &= *msg_ptr; + } + else + { + *lsb_ptr |= *msg_ptr; + } + return ERR_OK; + } + else + { + return ERR_ARG; + } + } + p = p->next; + } + /* p == NULL, ofs >= plen */ + return ERR_ARG; +} + +/** + * Decodes object identifier from incoming message into array of s32_t. + * + * @param p points to a pbuf holding an ASN1 coded object identifier + * @param ofs points to the offset within the pbuf chain of the ASN1 coded object identifier + * @param len length of the coded object identifier + * @param oid return object identifier struct + * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode + */ +err_t +snmp_asn1_dec_oid(struct pbuf *p, u16_t ofs, u16_t len, struct snmp_obj_id *oid) +{ + u16_t plen, base; + u8_t *msg_ptr; + s32_t *oid_ptr; + + plen = 0; + while (p != NULL) + { + base = plen; + plen += p->len; + if (ofs < plen) + { + msg_ptr = p->payload; + msg_ptr += ofs - base; + + oid->len = 0; + oid_ptr = &oid->id[0]; + if (len > 0) + { + /* first compressed octet */ + if (*msg_ptr == 0x2B) + { + /* (most) common case 1.3 (iso.org) */ + *oid_ptr = 1; + oid_ptr++; + *oid_ptr = 3; + oid_ptr++; + } + else if (*msg_ptr < 40) + { + *oid_ptr = 0; + oid_ptr++; + *oid_ptr = *msg_ptr; + oid_ptr++; + } + else if (*msg_ptr < 80) + { + *oid_ptr = 1; + oid_ptr++; + *oid_ptr = (*msg_ptr) - 40; + oid_ptr++; + } + else + { + *oid_ptr = 2; + oid_ptr++; + *oid_ptr = (*msg_ptr) - 80; + oid_ptr++; + } + oid->len = 2; + } + else + { + /* accepting zero length identifiers e.g. for + getnext operation. uncommon but valid */ + return ERR_OK; + } + len--; + if (len > 0) + { + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + } + while ((len > 0) && (oid->len < LWIP_SNMP_OBJ_ID_LEN)) + { + /* sub-identifier uses multiple octets */ + if (*msg_ptr & 0x80) + { + s32_t sub_id = 0; + + while ((*msg_ptr & 0x80) && (len > 1)) + { + len--; + sub_id = (sub_id << 7) + (*msg_ptr & ~0x80); + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + } + if (!(*msg_ptr & 0x80) && (len > 0)) + { + /* last octet sub-identifier */ + len--; + sub_id = (sub_id << 7) + *msg_ptr; + *oid_ptr = sub_id; + } + } + else + { + /* !(*msg_ptr & 0x80) sub-identifier uses single octet */ + len--; + *oid_ptr = *msg_ptr; + } + if (len > 0) + { + /* remaining oid bytes available ... */ + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + } + oid_ptr++; + oid->len++; + } + if (len == 0) + { + /* len == 0, end of oid */ + return ERR_OK; + } + else + { + /* len > 0, oid->len == LWIP_SNMP_OBJ_ID_LEN or malformed encoding */ + return ERR_ARG; + } + + } + p = p->next; + } + /* p == NULL, ofs >= plen */ + return ERR_ARG; +} + +/** + * Decodes (copies) raw data (ip-addresses, octet strings, opaque encoding) + * from incoming message into array. + * + * @param p points to a pbuf holding an ASN1 coded raw data + * @param ofs points to the offset within the pbuf chain of the ASN1 coded raw data + * @param len length of the coded raw data (zero is valid, e.g. empty string!) + * @param raw_len length of the raw return value + * @param raw return raw bytes + * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) decode + */ +err_t +snmp_asn1_dec_raw(struct pbuf *p, u16_t ofs, u16_t len, u16_t raw_len, u8_t *raw) +{ + u16_t plen, base; + u8_t *msg_ptr; + + if (len > 0) + { + plen = 0; + while (p != NULL) + { + base = plen; + plen += p->len; + if (ofs < plen) + { + msg_ptr = p->payload; + msg_ptr += ofs - base; + if (raw_len >= len) + { + while (len > 1) + { + /* copy len - 1 octets */ + len--; + *raw = *msg_ptr; + raw++; + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + } + /* copy last octet */ + *raw = *msg_ptr; + return ERR_OK; + } + else + { + /* raw_len < len, not enough dst space */ + return ERR_ARG; + } + } + p = p->next; + } + /* p == NULL, ofs >= plen */ + return ERR_ARG; + } + else + { + /* len == 0, empty string */ + return ERR_OK; + } +} + +#endif /* LWIP_SNMP */ + diff --git a/20080212/Demo/Common/ethernet/lwIP/core/snmp/asn1_enc.c b/20080212/Demo/Common/ethernet/lwIP/core/snmp/asn1_enc.c new file mode 100644 index 000000000..80f8d3768 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/core/snmp/asn1_enc.c @@ -0,0 +1,610 @@ +/** + * @file + * Abstract Syntax Notation One (ISO 8824, 8825) encoding + * + * @todo not optimised (yet), favor correctness over speed, favor speed over size + */ + +/* + * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Christiaan Simons + */ + +#include "lwip/opt.h" + +#if LWIP_SNMP +#include "lwip/snmp_asn1.h" + +/** + * Returns octet count for length. + * + * @param length + * @param octets_needed points to the return value + */ +void +snmp_asn1_enc_length_cnt(u16_t length, u8_t *octets_needed) +{ + if (length < 0x80U) + { + *octets_needed = 1; + } + else if (length < 0x100U) + { + *octets_needed = 2; + } + else + { + *octets_needed = 3; + } +} + +/** + * Returns octet count for an u32_t. + * + * @param value + * @param octets_needed points to the return value + * + * @note ASN coded integers are _always_ signed. E.g. +0xFFFF is coded + * as 0x00,0xFF,0xFF. Note the leading sign octet. A positive value + * of 0xFFFFFFFF is preceded with 0x00 and the length is 5 octets!! + */ +void +snmp_asn1_enc_u32t_cnt(u32_t value, u16_t *octets_needed) +{ + if (value < 0x80UL) + { + *octets_needed = 1; + } + else if (value < 0x8000UL) + { + *octets_needed = 2; + } + else if (value < 0x800000UL) + { + *octets_needed = 3; + } + else if (value < 0x80000000UL) + { + *octets_needed = 4; + } + else + { + *octets_needed = 5; + } +} + +/** + * Returns octet count for an s32_t. + * + * @param value + * @param octets_needed points to the return value + * + * @note ASN coded integers are _always_ signed. + */ +void +snmp_asn1_enc_s32t_cnt(s32_t value, u16_t *octets_needed) +{ + if (value < 0) + { + value = ~value; + } + if (value < 0x80L) + { + *octets_needed = 1; + } + else if (value < 0x8000L) + { + *octets_needed = 2; + } + else if (value < 0x800000L) + { + *octets_needed = 3; + } + else + { + *octets_needed = 4; + } +} + +/** + * Returns octet count for an object identifier. + * + * @param ident_len object identifier array length + * @param ident points to object identifier array + * @param octets_needed points to the return value + */ +void +snmp_asn1_enc_oid_cnt(u8_t ident_len, s32_t *ident, u16_t *octets_needed) +{ + s32_t sub_id; + u8_t cnt; + + cnt = 0; + if (ident_len > 1) + { + /* compressed prefix in one octet */ + cnt++; + ident_len -= 2; + ident += 2; + } + while(ident_len > 0) + { + ident_len--; + sub_id = *ident; + + sub_id >>= 7; + cnt++; + while(sub_id > 0) + { + sub_id >>= 7; + cnt++; + } + ident++; + } + *octets_needed = cnt; +} + +/** + * Encodes ASN type field into a pbuf chained ASN1 msg. + * + * @param p points to output pbuf to encode value into + * @param ofs points to the offset within the pbuf chain + * @param type input ASN1 type + * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) encode + */ +err_t +snmp_asn1_enc_type(struct pbuf *p, u16_t ofs, u8_t type) +{ + u16_t plen, base; + u8_t *msg_ptr; + + plen = 0; + while (p != NULL) + { + base = plen; + plen += p->len; + if (ofs < plen) + { + msg_ptr = p->payload; + msg_ptr += ofs - base; + *msg_ptr = type; + return ERR_OK; + } + p = p->next; + } + /* p == NULL, ofs >= plen */ + return ERR_ARG; +} + +/** + * Encodes host order length field into a pbuf chained ASN1 msg. + * + * @param p points to output pbuf to encode length into + * @param ofs points to the offset within the pbuf chain + * @param length is the host order length to be encoded + * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) encode + */ +err_t +snmp_asn1_enc_length(struct pbuf *p, u16_t ofs, u16_t length) +{ + u16_t plen, base; + u8_t *msg_ptr; + + plen = 0; + while (p != NULL) + { + base = plen; + plen += p->len; + if (ofs < plen) + { + msg_ptr = p->payload; + msg_ptr += ofs - base; + + if (length < 0x80) + { + *msg_ptr = length; + return ERR_OK; + } + else if (length < 0x100) + { + *msg_ptr = 0x81; + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = p->payload; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + *msg_ptr = length; + return ERR_OK; + } + else + { + u8_t i; + + /* length >= 0x100 && length <= 0xFFFF */ + *msg_ptr = 0x82; + i = 2; + while (i > 0) + { + i--; + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + if (i == 0) + { + /* least significant length octet */ + *msg_ptr = length; + } + else + { + /* most significant length octet */ + *msg_ptr = length >> 8; + } + } + return ERR_OK; + } + } + p = p->next; + } + /* p == NULL, ofs >= plen */ + return ERR_ARG; +} + +/** + * Encodes u32_t (counter, gauge, timeticks) into a pbuf chained ASN1 msg. + * + * @param p points to output pbuf to encode value into + * @param ofs points to the offset within the pbuf chain + * @param octets_needed encoding length (from snmp_asn1_enc_u32t_cnt()) + * @param value is the host order u32_t value to be encoded + * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) encode + * + * @see snmp_asn1_enc_u32t_cnt() + */ +err_t +snmp_asn1_enc_u32t(struct pbuf *p, u16_t ofs, u8_t octets_needed, u32_t value) +{ + u16_t plen, base; + u8_t *msg_ptr; + + plen = 0; + while (p != NULL) + { + base = plen; + plen += p->len; + if (ofs < plen) + { + msg_ptr = p->payload; + msg_ptr += ofs - base; + + if (octets_needed == 5) + { + /* not enough bits in 'value' add leading 0x00 */ + octets_needed--; + *msg_ptr = 0x00; + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + } + while (octets_needed > 1) + { + octets_needed--; + *msg_ptr = value >> (octets_needed << 3); + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + } + /* (only) one least significant octet */ + *msg_ptr = value; + return ERR_OK; + } + p = p->next; + } + /* p == NULL, ofs >= plen */ + return ERR_ARG; +} + +/** + * Encodes s32_t integer into a pbuf chained ASN1 msg. + * + * @param p points to output pbuf to encode value into + * @param ofs points to the offset within the pbuf chain + * @param octets_needed encoding length (from snmp_asn1_enc_s32t_cnt()) + * @param value is the host order s32_t value to be encoded + * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) encode + * + * @see snmp_asn1_enc_s32t_cnt() + */ +err_t +snmp_asn1_enc_s32t(struct pbuf *p, u16_t ofs, u8_t octets_needed, s32_t value) +{ + u16_t plen, base; + u8_t *msg_ptr; + + plen = 0; + while (p != NULL) + { + base = plen; + plen += p->len; + if (ofs < plen) + { + msg_ptr = p->payload; + msg_ptr += ofs - base; + + while (octets_needed > 1) + { + octets_needed--; + *msg_ptr = value >> (octets_needed << 3); + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + } + /* (only) one least significant octet */ + *msg_ptr = value; + return ERR_OK; + } + p = p->next; + } + /* p == NULL, ofs >= plen */ + return ERR_ARG; +} + +/** + * Encodes object identifier into a pbuf chained ASN1 msg. + * + * @param p points to output pbuf to encode oid into + * @param ofs points to the offset within the pbuf chain + * @param ident_len object identifier array length + * @param ident points to object identifier array + * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) encode + */ +err_t +snmp_asn1_enc_oid(struct pbuf *p, u16_t ofs, u8_t ident_len, s32_t *ident) +{ + u16_t plen, base; + u8_t *msg_ptr; + + plen = 0; + while (p != NULL) + { + base = plen; + plen += p->len; + if (ofs < plen) + { + msg_ptr = p->payload; + msg_ptr += ofs - base; + + if (ident_len > 1) + { + if ((ident[0] == 1) && (ident[1] == 3)) + { + /* compressed (most common) prefix .iso.org */ + *msg_ptr = 0x2b; + } + else + { + /* calculate prefix */ + *msg_ptr = (ident[0] * 40) + ident[1]; + } + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + ident_len -= 2; + ident += 2; + } + else + { +/* @bug: allow empty varbinds for symmetry (we must decode them for getnext), allow partial compression?? */ + /* ident_len <= 1, at least we need zeroDotZero (0.0) (ident_len == 2) */ + return ERR_ARG; + } + while (ident_len > 0) + { + s32_t sub_id; + u8_t shift, tail; + + ident_len--; + sub_id = *ident; + tail = 0; + shift = 28; + while(shift > 0) + { + u8_t code; + + code = sub_id >> shift; + if ((code != 0) || (tail != 0)) + { + tail = 1; + *msg_ptr = code | 0x80; + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + } + shift -= 7; + } + *msg_ptr = (u8_t)sub_id & 0x7F; + if (ident_len > 0) + { + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + } + /* proceed to next sub-identifier */ + ident++; + } + return ERR_OK; + } + p = p->next; + } + /* p == NULL, ofs >= plen */ + return ERR_ARG; +} + +/** + * Encodes raw data (octet string, opaque) into a pbuf chained ASN1 msg. + * + * @param p points to output pbuf to encode raw data into + * @param ofs points to the offset within the pbuf chain + * @param raw_len raw data length + * @param raw points raw data + * @return ERR_OK if successfull, ERR_ARG if we can't (or won't) encode + */ +err_t +snmp_asn1_enc_raw(struct pbuf *p, u16_t ofs, u8_t raw_len, u8_t *raw) +{ + u16_t plen, base; + u8_t *msg_ptr; + + plen = 0; + while (p != NULL) + { + base = plen; + plen += p->len; + if (ofs < plen) + { + msg_ptr = p->payload; + msg_ptr += ofs - base; + + while (raw_len > 1) + { + /* copy raw_len - 1 octets */ + raw_len--; + *msg_ptr = *raw; + raw++; + ofs += 1; + if (ofs >= plen) + { + /* next octet in next pbuf */ + p = p->next; + if (p == NULL) { return ERR_ARG; } + msg_ptr = p->payload; + plen += p->len; + } + else + { + /* next octet in same pbuf */ + msg_ptr++; + } + } + if (raw_len > 0) + { + /* copy last or single octet */ + *msg_ptr = *raw; + } + return ERR_OK; + } + p = p->next; + } + /* p == NULL, ofs >= plen */ + return ERR_ARG; +} + +#endif /* LWIP_SNMP */ diff --git a/20080212/Demo/Common/ethernet/lwIP/core/snmp/mib2.c b/20080212/Demo/Common/ethernet/lwIP/core/snmp/mib2.c new file mode 100644 index 000000000..035c8b1b4 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/core/snmp/mib2.c @@ -0,0 +1,4021 @@ +/** + * @file + * Management Information Base II (RFC1213) objects and functions. + * + * @note the object identifiers for this MIB-2 and private MIB tree + * must be kept in sorted ascending order. This to ensure correct getnext operation. + */ + +/* + * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Christiaan Simons + */ + +#include "arch/cc.h" +#include "lwip/opt.h" + +#if LWIP_SNMP +#include "lwip/snmp.h" +#include "lwip/netif.h" +#include "netif/etharp.h" +#include "lwip/ip.h" +#include "lwip/ip_frag.h" +#include "lwip/tcp.h" +#include "lwip/udp.h" +#include "lwip/snmp_asn1.h" +#include "lwip/snmp_structs.h" + +/** + * IANA assigned enterprise ID for lwIP is 26381 + * @see http://www.iana.org/assignments/enterprise-numbers + * + * @note this enterprise ID is assigned to the lwIP project, + * all object identifiers living under this ID are assigned + * by the lwIP maintainers (contact Christiaan Simons)! + * @note don't change this define, use snmp_set_sysobjid() + * + * If you need to create your own private MIB you'll need + * to apply for your own enterprise ID with IANA: + * http://www.iana.org/numbers.html + */ +#define SNMP_ENTERPRISE_ID 26381 +#define SNMP_SYSOBJID_LEN 7 +#define SNMP_SYSOBJID {1, 3, 6, 1, 4, 1, SNMP_ENTERPRISE_ID} + +#ifndef SNMP_SYSSERVICES +#define SNMP_SYSSERVICES ((1 << 6) | (1 << 3) | ((IP_FORWARD) << 2)) +#endif + +static void system_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); +static void system_get_value(struct obj_def *od, u16_t len, void *value); +static u8_t system_set_test(struct obj_def *od, u16_t len, void *value); +static void system_set_value(struct obj_def *od, u16_t len, void *value); +static void interfaces_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); +static void interfaces_get_value(struct obj_def *od, u16_t len, void *value); +static void ifentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); +static void ifentry_get_value(struct obj_def *od, u16_t len, void *value); +static void atentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); +static void atentry_get_value(struct obj_def *od, u16_t len, void *value); +static void ip_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); +static void ip_get_value(struct obj_def *od, u16_t len, void *value); +static u8_t ip_set_test(struct obj_def *od, u16_t len, void *value); +static void ip_addrentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); +static void ip_addrentry_get_value(struct obj_def *od, u16_t len, void *value); +static void ip_rteentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); +static void ip_rteentry_get_value(struct obj_def *od, u16_t len, void *value); +static void ip_ntomentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); +static void ip_ntomentry_get_value(struct obj_def *od, u16_t len, void *value); +static void icmp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); +static void icmp_get_value(struct obj_def *od, u16_t len, void *value); +#if LWIP_TCP +static void tcp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); +static void tcp_get_value(struct obj_def *od, u16_t len, void *value); +static void tcpconnentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); +static void tcpconnentry_get_value(struct obj_def *od, u16_t len, void *value); +#endif +static void udp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); +static void udp_get_value(struct obj_def *od, u16_t len, void *value); +static void udpentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); +static void udpentry_get_value(struct obj_def *od, u16_t len, void *value); +static void snmp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); +static void snmp_get_value(struct obj_def *od, u16_t len, void *value); +static u8_t snmp_set_test(struct obj_def *od, u16_t len, void *value); +static void snmp_set_value(struct obj_def *od, u16_t len, void *value); + + +/* snmp .1.3.6.1.2.1.11 */ +const mib_scalar_node snmp_scalar = { + &snmp_get_object_def, + &snmp_get_value, + &snmp_set_test, + &snmp_set_value, + MIB_NODE_SC, + 0 +}; +const s32_t snmp_ids[28] = { + 1, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, + 17, 18, 19, 20, 21, 22, 24, 25, 26, 27, 28, 29, 30 +}; +struct mib_node* const snmp_nodes[28] = { + (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar, + (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar, + (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar, + (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar, + (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar, + (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar, + (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar, + (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar, + (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar, + (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar, + (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar, + (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar, + (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar, + (struct mib_node* const)&snmp_scalar, (struct mib_node* const)&snmp_scalar +}; +const struct mib_array_node snmp = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 28, + snmp_ids, + snmp_nodes +}; + +/* dot3 and EtherLike MIB not planned. (transmission .1.3.6.1.2.1.10) */ +/* historical (some say hysterical). (cmot .1.3.6.1.2.1.9) */ +/* lwIP has no EGP, thus may not implement it. (egp .1.3.6.1.2.1.8) */ + +/* udp .1.3.6.1.2.1.7 */ +/** index root node for udpTable */ +struct mib_list_rootnode udp_root = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_LR, + 0, + NULL, + NULL, + 0 +}; +const s32_t udpentry_ids[2] = { 1, 2 }; +struct mib_node* const udpentry_nodes[2] = { + (struct mib_node* const)&udp_root, (struct mib_node* const)&udp_root, +}; +const struct mib_array_node udpentry = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 2, + udpentry_ids, + udpentry_nodes +}; + +s32_t udptable_id = 1; +struct mib_node* udptable_node = (struct mib_node* const)&udpentry; +struct mib_ram_array_node udptable = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_RA, + 0, + &udptable_id, + &udptable_node +}; + +const mib_scalar_node udp_scalar = { + &udp_get_object_def, + &udp_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_SC, + 0 +}; +const s32_t udp_ids[5] = { 1, 2, 3, 4, 5 }; +struct mib_node* const udp_nodes[5] = { + (struct mib_node* const)&udp_scalar, (struct mib_node* const)&udp_scalar, + (struct mib_node* const)&udp_scalar, (struct mib_node* const)&udp_scalar, + (struct mib_node* const)&udptable +}; +const struct mib_array_node udp = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 5, + udp_ids, + udp_nodes +}; + +/* tcp .1.3.6.1.2.1.6 */ +#if LWIP_TCP +/* only if the TCP protocol is available may implement this group */ +/** index root node for tcpConnTable */ +struct mib_list_rootnode tcpconntree_root = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_LR, + 0, + NULL, + NULL, + 0 +}; +const s32_t tcpconnentry_ids[5] = { 1, 2, 3, 4, 5 }; +struct mib_node* const tcpconnentry_nodes[5] = { + (struct mib_node* const)&tcpconntree_root, (struct mib_node* const)&tcpconntree_root, + (struct mib_node* const)&tcpconntree_root, (struct mib_node* const)&tcpconntree_root, + (struct mib_node* const)&tcpconntree_root +}; +const struct mib_array_node tcpconnentry = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 5, + tcpconnentry_ids, + tcpconnentry_nodes +}; + +s32_t tcpconntable_id = 1; +struct mib_node* tcpconntable_node = (struct mib_node* const)&tcpconnentry; +struct mib_ram_array_node tcpconntable = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_RA, +/** @todo update maxlength when inserting / deleting from table + 0 when table is empty, 1 when more than one entry */ + 0, + &tcpconntable_id, + &tcpconntable_node +}; + +const mib_scalar_node tcp_scalar = { + &tcp_get_object_def, + &tcp_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_SC, + 0 +}; +const s32_t tcp_ids[15] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }; +struct mib_node* const tcp_nodes[15] = { + (struct mib_node* const)&tcp_scalar, (struct mib_node* const)&tcp_scalar, + (struct mib_node* const)&tcp_scalar, (struct mib_node* const)&tcp_scalar, + (struct mib_node* const)&tcp_scalar, (struct mib_node* const)&tcp_scalar, + (struct mib_node* const)&tcp_scalar, (struct mib_node* const)&tcp_scalar, + (struct mib_node* const)&tcp_scalar, (struct mib_node* const)&tcp_scalar, + (struct mib_node* const)&tcp_scalar, (struct mib_node* const)&tcp_scalar, + (struct mib_node* const)&tcpconntable, (struct mib_node* const)&tcp_scalar, + (struct mib_node* const)&tcp_scalar +}; +const struct mib_array_node tcp = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 15, + tcp_ids, + tcp_nodes +}; +#endif + +/* icmp .1.3.6.1.2.1.5 */ +const mib_scalar_node icmp_scalar = { + &icmp_get_object_def, + &icmp_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_SC, + 0 +}; +const s32_t icmp_ids[26] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26 }; +struct mib_node* const icmp_nodes[26] = { + (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar, + (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar, + (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar, + (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar, + (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar, + (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar, + (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar, + (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar, + (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar, + (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar, + (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar, + (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar, + (struct mib_node* const)&icmp_scalar, (struct mib_node* const)&icmp_scalar +}; +const struct mib_array_node icmp = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 26, + icmp_ids, + icmp_nodes +}; + +/** index root node for ipNetToMediaTable */ +struct mib_list_rootnode ipntomtree_root = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_LR, + 0, + NULL, + NULL, + 0 +}; +const s32_t ipntomentry_ids[4] = { 1, 2, 3, 4 }; +struct mib_node* const ipntomentry_nodes[4] = { + (struct mib_node* const)&ipntomtree_root, (struct mib_node* const)&ipntomtree_root, + (struct mib_node* const)&ipntomtree_root, (struct mib_node* const)&ipntomtree_root +}; +const struct mib_array_node ipntomentry = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 4, + ipntomentry_ids, + ipntomentry_nodes +}; + +s32_t ipntomtable_id = 1; +struct mib_node* ipntomtable_node = (struct mib_node* const)&ipntomentry; +struct mib_ram_array_node ipntomtable = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_RA, + 0, + &ipntomtable_id, + &ipntomtable_node +}; + +/** index root node for ipRouteTable */ +struct mib_list_rootnode iprtetree_root = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_LR, + 0, + NULL, + NULL, + 0 +}; +const s32_t iprteentry_ids[13] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 }; +struct mib_node* const iprteentry_nodes[13] = { + (struct mib_node* const)&iprtetree_root, (struct mib_node* const)&iprtetree_root, + (struct mib_node* const)&iprtetree_root, (struct mib_node* const)&iprtetree_root, + (struct mib_node* const)&iprtetree_root, (struct mib_node* const)&iprtetree_root, + (struct mib_node* const)&iprtetree_root, (struct mib_node* const)&iprtetree_root, + (struct mib_node* const)&iprtetree_root, (struct mib_node* const)&iprtetree_root, + (struct mib_node* const)&iprtetree_root, (struct mib_node* const)&iprtetree_root, + (struct mib_node* const)&iprtetree_root +}; +const struct mib_array_node iprteentry = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 13, + iprteentry_ids, + iprteentry_nodes +}; + +s32_t iprtetable_id = 1; +struct mib_node* iprtetable_node = (struct mib_node* const)&iprteentry; +struct mib_ram_array_node iprtetable = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_RA, + 0, + &iprtetable_id, + &iprtetable_node +}; + +/** index root node for ipAddrTable */ +struct mib_list_rootnode ipaddrtree_root = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_LR, + 0, + NULL, + NULL, + 0 +}; +const s32_t ipaddrentry_ids[5] = { 1, 2, 3, 4, 5 }; +struct mib_node* const ipaddrentry_nodes[5] = { + (struct mib_node* const)&ipaddrtree_root, + (struct mib_node* const)&ipaddrtree_root, + (struct mib_node* const)&ipaddrtree_root, + (struct mib_node* const)&ipaddrtree_root, + (struct mib_node* const)&ipaddrtree_root +}; +const struct mib_array_node ipaddrentry = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 5, + ipaddrentry_ids, + ipaddrentry_nodes +}; + +s32_t ipaddrtable_id = 1; +struct mib_node* ipaddrtable_node = (struct mib_node* const)&ipaddrentry; +struct mib_ram_array_node ipaddrtable = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_RA, + 0, + &ipaddrtable_id, + &ipaddrtable_node +}; + +/* ip .1.3.6.1.2.1.4 */ +const mib_scalar_node ip_scalar = { + &ip_get_object_def, + &ip_get_value, + &ip_set_test, + &noleafs_set_value, + MIB_NODE_SC, + 0 +}; +const s32_t ip_ids[23] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 }; +struct mib_node* const ip_nodes[23] = { + (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ip_scalar, + (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ip_scalar, + (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ip_scalar, + (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ip_scalar, + (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ip_scalar, + (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ip_scalar, + (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ip_scalar, + (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ip_scalar, + (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ip_scalar, + (struct mib_node* const)&ip_scalar, (struct mib_node* const)&ipaddrtable, + (struct mib_node* const)&iprtetable, (struct mib_node* const)&ipntomtable, + (struct mib_node* const)&ip_scalar +}; +const struct mib_array_node ip = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 23, + ip_ids, + ip_nodes +}; + +/** index root node for atTable */ +struct mib_list_rootnode arptree_root = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_LR, + 0, + NULL, + NULL, + 0 +}; +const s32_t atentry_ids[3] = { 1, 2, 3 }; +struct mib_node* const atentry_nodes[3] = { + (struct mib_node* const)&arptree_root, + (struct mib_node* const)&arptree_root, + (struct mib_node* const)&arptree_root +}; +const struct mib_array_node atentry = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 3, + atentry_ids, + atentry_nodes +}; + +const s32_t attable_id = 1; +struct mib_node* const attable_node = (struct mib_node* const)&atentry; +const struct mib_array_node attable = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 1, + &attable_id, + &attable_node +}; + +/* at .1.3.6.1.2.1.3 */ +s32_t at_id = 1; +struct mib_node* at_node = (struct mib_node* const)&attable; +struct mib_ram_array_node at = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_RA, + 0, + &at_id, + &at_node +}; + +/** index root node for ifTable */ +struct mib_list_rootnode iflist_root = { + &ifentry_get_object_def, + &ifentry_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_LR, + 0, + NULL, + NULL, + 0 +}; +const s32_t ifentry_ids[22] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22 }; +struct mib_node* const ifentry_nodes[22] = { + (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root, + (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root, + (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root, + (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root, + (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root, + (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root, + (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root, + (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root, + (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root, + (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root, + (struct mib_node* const)&iflist_root, (struct mib_node* const)&iflist_root +}; +const struct mib_array_node ifentry = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 22, + ifentry_ids, + ifentry_nodes +}; + +s32_t iftable_id = 1; +struct mib_node* iftable_node = (struct mib_node* const)&ifentry; +struct mib_ram_array_node iftable = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_RA, + 0, + &iftable_id, + &iftable_node +}; + +/* interfaces .1.3.6.1.2.1.2 */ +const mib_scalar_node interfaces_scalar = { + &interfaces_get_object_def, + &interfaces_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_SC, + 0 +}; +const s32_t interfaces_ids[2] = { 1, 2 }; +struct mib_node* const interfaces_nodes[2] = { + (struct mib_node* const)&interfaces_scalar, (struct mib_node* const)&iftable +}; +const struct mib_array_node interfaces = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 2, + interfaces_ids, + interfaces_nodes +}; + + +/* 0 1 2 3 4 5 6 */ +/* system .1.3.6.1.2.1.1 */ +const mib_scalar_node sys_tem_scalar = { + &system_get_object_def, + &system_get_value, + &system_set_test, + &system_set_value, + MIB_NODE_SC, + 0 +}; +const s32_t sys_tem_ids[7] = { 1, 2, 3, 4, 5, 6, 7 }; +struct mib_node* const sys_tem_nodes[7] = { + (struct mib_node* const)&sys_tem_scalar, (struct mib_node* const)&sys_tem_scalar, + (struct mib_node* const)&sys_tem_scalar, (struct mib_node* const)&sys_tem_scalar, + (struct mib_node* const)&sys_tem_scalar, (struct mib_node* const)&sys_tem_scalar, + (struct mib_node* const)&sys_tem_scalar +}; +/* work around name issue with 'sys_tem', some compiler(s?) seem to reserve 'system' */ +const struct mib_array_node sys_tem = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 7, + sys_tem_ids, + sys_tem_nodes +}; + +/* mib-2 .1.3.6.1.2.1 */ +#if LWIP_TCP +#define MIB2_GROUPS 8 +#else +#define MIB2_GROUPS 7 +#endif +const s32_t mib2_ids[MIB2_GROUPS] = +{ + 1, + 2, + 3, + 4, + 5, +#if LWIP_TCP + 6, +#endif + 7, + 11 +}; +struct mib_node* const mib2_nodes[MIB2_GROUPS] = { + (struct mib_node* const)&sys_tem, + (struct mib_node* const)&interfaces, + (struct mib_node* const)&at, + (struct mib_node* const)&ip, + (struct mib_node* const)&icmp, +#if LWIP_TCP + (struct mib_node* const)&tcp, +#endif + (struct mib_node* const)&udp, + (struct mib_node* const)&snmp +}; + +const struct mib_array_node mib2 = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + MIB2_GROUPS, + mib2_ids, + mib2_nodes +}; + +/* mgmt .1.3.6.1.2 */ +const s32_t mgmt_ids[1] = { 1 }; +struct mib_node* const mgmt_nodes[1] = { (struct mib_node* const)&mib2 }; +const struct mib_array_node mgmt = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 1, + mgmt_ids, + mgmt_nodes +}; + +/* internet .1.3.6.1 */ +#if SNMP_PRIVATE_MIB +s32_t internet_ids[2] = { 2, 4 }; +struct mib_node* const internet_nodes[2] = { (struct mib_node* const)&mgmt, (struct mib_node* const)&private }; +const struct mib_array_node internet = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 2, + internet_ids, + internet_nodes +}; +#else +const s32_t internet_ids[1] = { 2 }; +struct mib_node* const internet_nodes[1] = { (struct mib_node* const)&mgmt }; +const struct mib_array_node internet = { + &noleafs_get_object_def, + &noleafs_get_value, + &noleafs_set_test, + &noleafs_set_value, + MIB_NODE_AR, + 1, + internet_ids, + internet_nodes +}; +#endif + +/** mib-2.system.sysObjectID */ +static struct snmp_obj_id sysobjid = {SNMP_SYSOBJID_LEN, SNMP_SYSOBJID}; +/** enterprise ID for generic TRAPs, .iso.org.dod.internet.mgmt.mib-2.snmp */ +static struct snmp_obj_id snmpgrp_id = {7,{1,3,6,1,2,1,11}}; +/** mib-2.system.sysServices */ +static const s32_t sysservices = SNMP_SYSSERVICES; + +/** mib-2.system.sysDescr */ +static const u8_t sysdescr_len_default = 4; +static const u8_t sysdescr_default[] = "lwIP"; +static u8_t* sysdescr_len_ptr = (u8_t*)&sysdescr_len_default; +static u8_t* sysdescr_ptr = (u8_t*)&sysdescr_default[0]; +/** mib-2.system.sysContact */ +static const u8_t syscontact_len_default = 0; +static const u8_t syscontact_default[] = ""; +static u8_t* syscontact_len_ptr = (u8_t*)&syscontact_len_default; +static u8_t* syscontact_ptr = (u8_t*)&syscontact_default[0]; +/** mib-2.system.sysName */ +static const u8_t sysname_len_default = 8; +static const u8_t sysname_default[] = "FQDN-unk"; +static u8_t* sysname_len_ptr = (u8_t*)&sysname_len_default; +static u8_t* sysname_ptr = (u8_t*)&sysname_default[0]; +/** mib-2.system.sysLocation */ +static const u8_t syslocation_len_default = 0; +static const u8_t syslocation_default[] = ""; +static u8_t* syslocation_len_ptr = (u8_t*)&syslocation_len_default; +static u8_t* syslocation_ptr = (u8_t*)&syslocation_default[0]; +/** mib-2.snmp.snmpEnableAuthenTraps */ +static const u8_t snmpenableauthentraps_default = 2; /* disabled */ +static u8_t* snmpenableauthentraps_ptr = (u8_t*)&snmpenableauthentraps_default; + +/** mib-2.interfaces.ifTable.ifEntry.ifSpecific (zeroDotZero) */ +static const struct snmp_obj_id ifspecific = {2, {0, 0}}; +/** mib-2.ip.ipRouteTable.ipRouteEntry.ipRouteInfo (zeroDotZero) */ +static const struct snmp_obj_id iprouteinfo = {2, {0, 0}}; + + + +/* mib-2.system counter(s) */ +static u32_t sysuptime = 0; + +/* mib-2.ip counter(s) */ +static u32_t ipinreceives = 0, + ipinhdrerrors = 0, + ipinaddrerrors = 0, + ipforwdatagrams = 0, + ipinunknownprotos = 0, + ipindiscards = 0, + ipindelivers = 0, + ipoutrequests = 0, + ipoutdiscards = 0, + ipoutnoroutes = 0, + ipreasmreqds = 0, + ipreasmoks = 0, + ipreasmfails = 0, + ipfragoks = 0, + ipfragfails = 0, + ipfragcreates = 0, + iproutingdiscards = 0; +/* mib-2.icmp counter(s) */ +static u32_t icmpinmsgs = 0, + icmpinerrors = 0, + icmpindestunreachs = 0, + icmpintimeexcds = 0, + icmpinparmprobs = 0, + icmpinsrcquenchs = 0, + icmpinredirects = 0, + icmpinechos = 0, + icmpinechoreps = 0, + icmpintimestamps = 0, + icmpintimestampreps = 0, + icmpinaddrmasks = 0, + icmpinaddrmaskreps = 0, + icmpoutmsgs = 0, + icmpouterrors = 0, + icmpoutdestunreachs = 0, + icmpouttimeexcds = 0, + icmpoutparmprobs = 0, + icmpoutsrcquenchs = 0, + icmpoutredirects = 0, + icmpoutechos = 0, + icmpoutechoreps = 0, + icmpouttimestamps = 0, + icmpouttimestampreps = 0, + icmpoutaddrmasks = 0, + icmpoutaddrmaskreps = 0; +/* mib-2.tcp counter(s) */ +static u32_t tcpactiveopens = 0, + tcppassiveopens = 0, + tcpattemptfails = 0, + tcpestabresets = 0, + tcpinsegs = 0, + tcpoutsegs = 0, + tcpretranssegs = 0, + tcpinerrs = 0, + tcpoutrsts = 0; +/* mib-2.udp counter(s) */ +static u32_t udpindatagrams = 0, + udpnoports = 0, + udpinerrors = 0, + udpoutdatagrams = 0; +/* mib-2.snmp counter(s) */ +static u32_t snmpinpkts = 0, + snmpoutpkts = 0, + snmpinbadversions = 0, + snmpinbadcommunitynames = 0, + snmpinbadcommunityuses = 0, + snmpinasnparseerrs = 0, + snmpintoobigs = 0, + snmpinnosuchnames = 0, + snmpinbadvalues = 0, + snmpinreadonlys = 0, + snmpingenerrs = 0, + snmpintotalreqvars = 0, + snmpintotalsetvars = 0, + snmpingetrequests = 0, + snmpingetnexts = 0, + snmpinsetrequests = 0, + snmpingetresponses = 0, + snmpintraps = 0, + snmpouttoobigs = 0, + snmpoutnosuchnames = 0, + snmpoutbadvalues = 0, + snmpoutgenerrs = 0, + snmpoutgetrequests = 0, + snmpoutgetnexts = 0, + snmpoutsetrequests = 0, + snmpoutgetresponses = 0, + snmpouttraps = 0; + + + +/* prototypes of the following functions are in lwip/src/include/lwip/snmp.h */ +/** + * Copy octet string. + * + * @param dst points to destination + * @param src points to source + * @param n number of octets to copy. + */ +void ocstrncpy(u8_t *dst, u8_t *src, u8_t n) +{ + while (n > 0) + { + n--; + *dst++ = *src++; + } +} + +/** + * Copy object identifier (s32_t) array. + * + * @param dst points to destination + * @param src points to source + * @param n number of sub identifiers to copy. + */ +void objectidncpy(s32_t *dst, s32_t *src, u8_t n) +{ + while(n > 0) + { + n--; + *dst++ = *src++; + } +} + +/** + * Initializes sysDescr pointers. + * + * @param str if non-NULL then copy str pointer + * @param strlen points to string length, excluding zero terminator + */ +void snmp_set_sysdesr(u8_t *str, u8_t *strlen) +{ + if (str != NULL) + { + sysdescr_ptr = str; + sysdescr_len_ptr = strlen; + } +} + +void snmp_get_sysobjid_ptr(struct snmp_obj_id **oid) +{ + *oid = &sysobjid; +} + +/** + * Initializes sysObjectID value. + * + * @param oid points to stuct snmp_obj_id to copy + */ +void snmp_set_sysobjid(struct snmp_obj_id *oid) +{ + sysobjid = *oid; +} + +/** + * Must be called at regular 10 msec interval from a timer interrupt + * or signal handler depending on your runtime environment. + */ +void snmp_inc_sysuptime(void) +{ + sysuptime++; +} + +void snmp_get_sysuptime(u32_t *value) +{ + *value = sysuptime; +} + +/** + * Initializes sysContact pointers, + * e.g. ptrs to non-volatile memory external to lwIP. + * + * @param str if non-NULL then copy str pointer + * @param strlen points to string length, excluding zero terminator + */ +void snmp_set_syscontact(u8_t *ocstr, u8_t *ocstrlen) +{ + if (ocstr != NULL) + { + syscontact_ptr = ocstr; + syscontact_len_ptr = ocstrlen; + } +} + +/** + * Initializes sysName pointers, + * e.g. ptrs to non-volatile memory external to lwIP. + * + * @param str if non-NULL then copy str pointer + * @param strlen points to string length, excluding zero terminator + */ +void snmp_set_sysname(u8_t *ocstr, u8_t *ocstrlen) +{ + if (ocstr != NULL) + { + sysname_ptr = ocstr; + sysname_len_ptr = ocstrlen; + } +} + +/** + * Initializes sysLocation pointers, + * e.g. ptrs to non-volatile memory external to lwIP. + * + * @param str if non-NULL then copy str pointer + * @param strlen points to string length, excluding zero terminator + */ +void snmp_set_syslocation(u8_t *ocstr, u8_t *ocstrlen) +{ + if (ocstr != NULL) + { + syslocation_ptr = ocstr; + syslocation_len_ptr = ocstrlen; + } +} + + +void snmp_add_ifinoctets(struct netif *ni, u32_t value) +{ + ni->ifinoctets += value; +} + +void snmp_inc_ifinucastpkts(struct netif *ni) +{ + (ni->ifinucastpkts)++; +} + +void snmp_inc_ifinnucastpkts(struct netif *ni) +{ + (ni->ifinnucastpkts)++; +} + +void snmp_inc_ifindiscards(struct netif *ni) +{ + (ni->ifindiscards)++; +} + +void snmp_add_ifoutoctets(struct netif *ni, u32_t value) +{ + ni->ifoutoctets += value; +} + +void snmp_inc_ifoutucastpkts(struct netif *ni) +{ + (ni->ifoutucastpkts)++; +} + +void snmp_inc_ifoutnucastpkts(struct netif *ni) +{ + (ni->ifoutnucastpkts)++; +} + +void snmp_inc_ifoutdiscards(struct netif *ni) +{ + (ni->ifoutdiscards)++; +} + +void snmp_inc_iflist(void) +{ + struct mib_list_node *if_node = NULL; + + snmp_mib_node_insert(&iflist_root, iflist_root.count + 1, &if_node); + /* enable getnext traversal on filled table */ + iftable.maxlength = 1; +} + +void snmp_dec_iflist(void) +{ + snmp_mib_node_delete(&iflist_root, iflist_root.tail); + /* disable getnext traversal on empty table */ + if(iflist_root.count == 0) iftable.maxlength = 0; +} + +/** + * Inserts ARP table indexes (.xIfIndex.xNetAddress) + * into arp table index trees (both atTable and ipNetToMediaTable). + */ +void snmp_insert_arpidx_tree(struct netif *ni, struct ip_addr *ip) +{ + struct mib_list_rootnode *at_rn; + struct mib_list_node *at_node; + struct ip_addr hip; + s32_t arpidx[5]; + u8_t level, tree; + + LWIP_ASSERT("ni != NULL", ni != NULL); + snmp_netiftoifindex(ni, &arpidx[0]); + hip.addr = ntohl(ip->addr); + snmp_iptooid(&hip, &arpidx[1]); + + for (tree = 0; tree < 2; tree++) + { + if (tree == 0) + { + at_rn = &arptree_root; + } + else + { + at_rn = &ipntomtree_root; + } + for (level = 0; level < 5; level++) + { + at_node = NULL; + snmp_mib_node_insert(at_rn, arpidx[level], &at_node); + if ((level != 4) && (at_node != NULL)) + { + if (at_node->nptr == NULL) + { + at_rn = snmp_mib_lrn_alloc(); + at_node->nptr = (struct mib_node*)at_rn; + if (at_rn != NULL) + { + if (level == 3) + { + if (tree == 0) + { + at_rn->get_object_def = atentry_get_object_def; + at_rn->get_value = atentry_get_value; + } + else + { + at_rn->get_object_def = ip_ntomentry_get_object_def; + at_rn->get_value = ip_ntomentry_get_value; + } + at_rn->set_test = noleafs_set_test; + at_rn->set_value = noleafs_set_value; + } + } + else + { + /* at_rn == NULL, malloc failure */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("snmp_insert_arpidx_tree() insert failed, mem full")); + break; + } + } + else + { + at_rn = (struct mib_list_rootnode*)at_node->nptr; + } + } + } + } + /* enable getnext traversal on filled tables */ + at.maxlength = 1; + ipntomtable.maxlength = 1; +} + +/** + * Removes ARP table indexes (.xIfIndex.xNetAddress) + * from arp table index trees. + */ +void snmp_delete_arpidx_tree(struct netif *ni, struct ip_addr *ip) +{ + struct mib_list_rootnode *at_rn, *next, *del_rn[5]; + struct mib_list_node *at_n, *del_n[5]; + struct ip_addr hip; + s32_t arpidx[5]; + u8_t fc, tree, level, del_cnt; + + snmp_netiftoifindex(ni, &arpidx[0]); + hip.addr = ntohl(ip->addr); + snmp_iptooid(&hip, &arpidx[1]); + + for (tree = 0; tree < 2; tree++) + { + /* mark nodes for deletion */ + if (tree == 0) + { + at_rn = &arptree_root; + } + else + { + at_rn = &ipntomtree_root; + } + level = 0; + del_cnt = 0; + while ((level < 5) && (at_rn != NULL)) + { + fc = snmp_mib_node_find(at_rn, arpidx[level], &at_n); + if (fc == 0) + { + /* arpidx[level] does not exist */ + del_cnt = 0; + at_rn = NULL; + } + else if (fc == 1) + { + del_rn[del_cnt] = at_rn; + del_n[del_cnt] = at_n; + del_cnt++; + at_rn = (struct mib_list_rootnode*)(at_n->nptr); + } + else if (fc == 2) + { + /* reset delete (2 or more childs) */ + del_cnt = 0; + at_rn = (struct mib_list_rootnode*)(at_n->nptr); + } + level++; + } + /* delete marked index nodes */ + while (del_cnt > 0) + { + del_cnt--; + + at_rn = del_rn[del_cnt]; + at_n = del_n[del_cnt]; + + next = snmp_mib_node_delete(at_rn, at_n); + if (next != NULL) + { + LWIP_ASSERT("next_count == 0",next->count == 0); + snmp_mib_lrn_free(next); + } + } + } + /* disable getnext traversal on empty tables */ + if(arptree_root.count == 0) at.maxlength = 0; + if(ipntomtree_root.count == 0) ipntomtable.maxlength = 0; +} + +void snmp_inc_ipinreceives(void) +{ + ipinreceives++; +} + +void snmp_inc_ipinhdrerrors(void) +{ + ipinhdrerrors++; +} + +void snmp_inc_ipinaddrerrors(void) +{ + ipinaddrerrors++; +} + +void snmp_inc_ipforwdatagrams(void) +{ + ipforwdatagrams++; +} + +void snmp_inc_ipinunknownprotos(void) +{ + ipinunknownprotos++; +} + +void snmp_inc_ipindiscards(void) +{ + ipindiscards++; +} + +void snmp_inc_ipindelivers(void) +{ + ipindelivers++; +} + +void snmp_inc_ipoutrequests(void) +{ + ipoutrequests++; +} + +void snmp_inc_ipoutdiscards(void) +{ + ipoutdiscards++; +} + +void snmp_inc_ipoutnoroutes(void) +{ + ipoutnoroutes++; +} + +void snmp_inc_ipreasmreqds(void) +{ + ipreasmreqds++; +} + +void snmp_inc_ipreasmoks(void) +{ + ipreasmoks++; +} + +void snmp_inc_ipreasmfails(void) +{ + ipreasmfails++; +} + +void snmp_inc_ipfragoks(void) +{ + ipfragoks++; +} + +void snmp_inc_ipfragfails(void) +{ + ipfragfails++; +} + +void snmp_inc_ipfragcreates(void) +{ + ipfragcreates++; +} + +void snmp_inc_iproutingdiscards(void) +{ + iproutingdiscards++; +} + +/** + * Inserts ipAddrTable indexes (.ipAdEntAddr) + * into index tree. + */ +void snmp_insert_ipaddridx_tree(struct netif *ni) +{ + struct mib_list_rootnode *ipa_rn; + struct mib_list_node *ipa_node; + struct ip_addr ip; + s32_t ipaddridx[4]; + u8_t level; + + LWIP_ASSERT("ni != NULL", ni != NULL); + ip.addr = ntohl(ni->ip_addr.addr); + snmp_iptooid(&ip, &ipaddridx[0]); + + level = 0; + ipa_rn = &ipaddrtree_root; + while (level < 4) + { + ipa_node = NULL; + snmp_mib_node_insert(ipa_rn, ipaddridx[level], &ipa_node); + if ((level != 3) && (ipa_node != NULL)) + { + if (ipa_node->nptr == NULL) + { + ipa_rn = snmp_mib_lrn_alloc(); + ipa_node->nptr = (struct mib_node*)ipa_rn; + if (ipa_rn != NULL) + { + if (level == 2) + { + ipa_rn->get_object_def = ip_addrentry_get_object_def; + ipa_rn->get_value = ip_addrentry_get_value; + ipa_rn->set_test = noleafs_set_test; + ipa_rn->set_value = noleafs_set_value; + } + } + else + { + /* ipa_rn == NULL, malloc failure */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("snmp_insert_ipaddridx_tree() insert failed, mem full")); + break; + } + } + else + { + ipa_rn = (struct mib_list_rootnode*)ipa_node->nptr; + } + } + level++; + } + /* enable getnext traversal on filled table */ + ipaddrtable.maxlength = 1; +} + +/** + * Removes ipAddrTable indexes (.ipAdEntAddr) + * from index tree. + */ +void snmp_delete_ipaddridx_tree(struct netif *ni) +{ + struct mib_list_rootnode *ipa_rn, *next, *del_rn[4]; + struct mib_list_node *ipa_n, *del_n[4]; + struct ip_addr ip; + s32_t ipaddridx[4]; + u8_t fc, level, del_cnt; + + LWIP_ASSERT("ni != NULL", ni != NULL); + ip.addr = ntohl(ni->ip_addr.addr); + snmp_iptooid(&ip, &ipaddridx[0]); + + /* mark nodes for deletion */ + level = 0; + del_cnt = 0; + ipa_rn = &ipaddrtree_root; + while ((level < 4) && (ipa_rn != NULL)) + { + fc = snmp_mib_node_find(ipa_rn, ipaddridx[level], &ipa_n); + if (fc == 0) + { + /* ipaddridx[level] does not exist */ + del_cnt = 0; + ipa_rn = NULL; + } + else if (fc == 1) + { + del_rn[del_cnt] = ipa_rn; + del_n[del_cnt] = ipa_n; + del_cnt++; + ipa_rn = (struct mib_list_rootnode*)(ipa_n->nptr); + } + else if (fc == 2) + { + /* reset delete (2 or more childs) */ + del_cnt = 0; + ipa_rn = (struct mib_list_rootnode*)(ipa_n->nptr); + } + level++; + } + /* delete marked index nodes */ + while (del_cnt > 0) + { + del_cnt--; + + ipa_rn = del_rn[del_cnt]; + ipa_n = del_n[del_cnt]; + + next = snmp_mib_node_delete(ipa_rn, ipa_n); + if (next != NULL) + { + LWIP_ASSERT("next_count == 0",next->count == 0); + snmp_mib_lrn_free(next); + } + } + /* disable getnext traversal on empty table */ + if (ipaddrtree_root.count == 0) ipaddrtable.maxlength = 0; +} + +/** + * Inserts ipRouteTable indexes (.ipRouteDest) + * into index tree. + * + * @param dflt non-zero for the default rte, zero for network rte + * @param netif points to network interface for this rte + * + * @todo record sysuptime for _this_ route when it is installed + * (needed for ipRouteAge) in the netif. + */ +void snmp_insert_iprteidx_tree(u8_t dflt, struct netif *ni) +{ + u8_t insert = 0; + struct ip_addr dst; + + if (dflt != 0) + { + /* the default route 0.0.0.0 */ + dst.addr = 0; + insert = 1; + } + else + { + /* route to the network address */ + dst.addr = ntohl(ni->ip_addr.addr & ni->netmask.addr); + /* exclude 0.0.0.0 network (reserved for default rte) */ + if (dst.addr != 0) insert = 1; + } + if (insert) + { + struct mib_list_rootnode *iprte_rn; + struct mib_list_node *iprte_node; + s32_t iprteidx[4]; + u8_t level; + + snmp_iptooid(&dst, &iprteidx[0]); + level = 0; + iprte_rn = &iprtetree_root; + while (level < 4) + { + iprte_node = NULL; + snmp_mib_node_insert(iprte_rn, iprteidx[level], &iprte_node); + if ((level != 3) && (iprte_node != NULL)) + { + if (iprte_node->nptr == NULL) + { + iprte_rn = snmp_mib_lrn_alloc(); + iprte_node->nptr = (struct mib_node*)iprte_rn; + if (iprte_rn != NULL) + { + if (level == 2) + { + iprte_rn->get_object_def = ip_rteentry_get_object_def; + iprte_rn->get_value = ip_rteentry_get_value; + iprte_rn->set_test = noleafs_set_test; + iprte_rn->set_value = noleafs_set_value; + } + } + else + { + /* iprte_rn == NULL, malloc failure */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("snmp_insert_iprteidx_tree() insert failed, mem full")); + break; + } + } + else + { + iprte_rn = (struct mib_list_rootnode*)iprte_node->nptr; + } + } + level++; + } + } + /* enable getnext traversal on filled table */ + iprtetable.maxlength = 1; +} + +/** + * Removes ipRouteTable indexes (.ipRouteDest) + * from index tree. + * + * @param dflt non-zero for the default rte, zero for network rte + * @param netif points to network interface for this rte or NULL + * for default route to be removed. + */ +void snmp_delete_iprteidx_tree(u8_t dflt, struct netif *ni) +{ + u8_t delete = 0; + struct ip_addr dst; + + if (dflt != 0) + { + /* the default route 0.0.0.0 */ + dst.addr = 0; + delete = 1; + } + else + { + /* route to the network address */ + dst.addr = ntohl(ni->ip_addr.addr & ni->netmask.addr); + /* exclude 0.0.0.0 network (reserved for default rte) */ + if (dst.addr != 0) delete = 1; + } + if (delete) + { + struct mib_list_rootnode *iprte_rn, *next, *del_rn[4]; + struct mib_list_node *iprte_n, *del_n[4]; + s32_t iprteidx[4]; + u8_t fc, level, del_cnt; + + snmp_iptooid(&dst, &iprteidx[0]); + /* mark nodes for deletion */ + level = 0; + del_cnt = 0; + iprte_rn = &iprtetree_root; + while ((level < 4) && (iprte_rn != NULL)) + { + fc = snmp_mib_node_find(iprte_rn, iprteidx[level], &iprte_n); + if (fc == 0) + { + /* iprteidx[level] does not exist */ + del_cnt = 0; + iprte_rn = NULL; + } + else if (fc == 1) + { + del_rn[del_cnt] = iprte_rn; + del_n[del_cnt] = iprte_n; + del_cnt++; + iprte_rn = (struct mib_list_rootnode*)(iprte_n->nptr); + } + else if (fc == 2) + { + /* reset delete (2 or more childs) */ + del_cnt = 0; + iprte_rn = (struct mib_list_rootnode*)(iprte_n->nptr); + } + level++; + } + /* delete marked index nodes */ + while (del_cnt > 0) + { + del_cnt--; + + iprte_rn = del_rn[del_cnt]; + iprte_n = del_n[del_cnt]; + + next = snmp_mib_node_delete(iprte_rn, iprte_n); + if (next != NULL) + { + LWIP_ASSERT("next_count == 0",next->count == 0); + snmp_mib_lrn_free(next); + } + } + } + /* disable getnext traversal on empty table */ + if (iprtetree_root.count == 0) iprtetable.maxlength = 0; +} + + +void snmp_inc_icmpinmsgs(void) +{ + icmpinmsgs++; +} + +void snmp_inc_icmpinerrors(void) +{ + icmpinerrors++; +} + +void snmp_inc_icmpindestunreachs(void) +{ + icmpindestunreachs++; +} + +void snmp_inc_icmpintimeexcds(void) +{ + icmpintimeexcds++; +} + +void snmp_inc_icmpinparmprobs(void) +{ + icmpinparmprobs++; +} + +void snmp_inc_icmpinsrcquenchs(void) +{ + icmpinsrcquenchs++; +} + +void snmp_inc_icmpinredirects(void) +{ + icmpinredirects++; +} + +void snmp_inc_icmpinechos(void) +{ + icmpinechos++; +} + +void snmp_inc_icmpinechoreps(void) +{ + icmpinechoreps++; +} + +void snmp_inc_icmpintimestamps(void) +{ + icmpintimestamps++; +} + +void snmp_inc_icmpintimestampreps(void) +{ + icmpintimestampreps++; +} + +void snmp_inc_icmpinaddrmasks(void) +{ + icmpinaddrmasks++; +} + +void snmp_inc_icmpinaddrmaskreps(void) +{ + icmpinaddrmaskreps++; +} + +void snmp_inc_icmpoutmsgs(void) +{ + icmpoutmsgs++; +} + +void snmp_inc_icmpouterrors(void) +{ + icmpouterrors++; +} + +void snmp_inc_icmpoutdestunreachs(void) +{ + icmpoutdestunreachs++; +} + +void snmp_inc_icmpouttimeexcds(void) +{ + icmpouttimeexcds++; +} + +void snmp_inc_icmpoutparmprobs(void) +{ + icmpoutparmprobs++; +} + +void snmp_inc_icmpoutsrcquenchs(void) +{ + icmpoutsrcquenchs++; +} + +void snmp_inc_icmpoutredirects(void) +{ + icmpoutredirects++; +} + +void snmp_inc_icmpoutechos(void) +{ + icmpoutechos++; +} + +void snmp_inc_icmpoutechoreps(void) +{ + icmpoutechoreps++; +} + +void snmp_inc_icmpouttimestamps(void) +{ + icmpouttimestamps++; +} + +void snmp_inc_icmpouttimestampreps(void) +{ + icmpouttimestampreps++; +} + +void snmp_inc_icmpoutaddrmasks(void) +{ + icmpoutaddrmasks++; +} + +void snmp_inc_icmpoutaddrmaskreps(void) +{ + icmpoutaddrmaskreps++; +} + +void snmp_inc_tcpactiveopens(void) +{ + tcpactiveopens++; +} + +void snmp_inc_tcppassiveopens(void) +{ + tcppassiveopens++; +} + +void snmp_inc_tcpattemptfails(void) +{ + tcpattemptfails++; +} + +void snmp_inc_tcpestabresets(void) +{ + tcpestabresets++; +} + +void snmp_inc_tcpinsegs(void) +{ + tcpinsegs++; +} + +void snmp_inc_tcpoutsegs(void) +{ + tcpoutsegs++; +} + +void snmp_inc_tcpretranssegs(void) +{ + tcpretranssegs++; +} + +void snmp_inc_tcpinerrs(void) +{ + tcpinerrs++; +} + +void snmp_inc_tcpoutrsts(void) +{ + tcpoutrsts++; +} + +void snmp_inc_udpindatagrams(void) +{ + udpindatagrams++; +} + +void snmp_inc_udpnoports(void) +{ + udpnoports++; +} + +void snmp_inc_udpinerrors(void) +{ + udpinerrors++; +} + +void snmp_inc_udpoutdatagrams(void) +{ + udpoutdatagrams++; +} + +/** + * Inserts udpTable indexes (.udpLocalAddress.udpLocalPort) + * into index tree. + */ +void snmp_insert_udpidx_tree(struct udp_pcb *pcb) +{ + struct mib_list_rootnode *udp_rn; + struct mib_list_node *udp_node; + struct ip_addr ip; + s32_t udpidx[5]; + u8_t level; + + LWIP_ASSERT("pcb != NULL", pcb != NULL); + ip.addr = ntohl(pcb->local_ip.addr); + snmp_iptooid(&ip, &udpidx[0]); + udpidx[4] = pcb->local_port; + + udp_rn = &udp_root; + for (level = 0; level < 5; level++) + { + udp_node = NULL; + snmp_mib_node_insert(udp_rn, udpidx[level], &udp_node); + if ((level != 4) && (udp_node != NULL)) + { + if (udp_node->nptr == NULL) + { + udp_rn = snmp_mib_lrn_alloc(); + udp_node->nptr = (struct mib_node*)udp_rn; + if (udp_rn != NULL) + { + if (level == 3) + { + udp_rn->get_object_def = udpentry_get_object_def; + udp_rn->get_value = udpentry_get_value; + udp_rn->set_test = noleafs_set_test; + udp_rn->set_value = noleafs_set_value; + } + } + else + { + /* udp_rn == NULL, malloc failure */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("snmp_insert_udpidx_tree() insert failed, mem full")); + break; + } + } + else + { + udp_rn = (struct mib_list_rootnode*)udp_node->nptr; + } + } + } + udptable.maxlength = 1; +} + +/** + * Removes udpTable indexes (.udpLocalAddress.udpLocalPort) + * from index tree. + */ +void snmp_delete_udpidx_tree(struct udp_pcb *pcb) +{ + struct mib_list_rootnode *udp_rn, *next, *del_rn[5]; + struct mib_list_node *udp_n, *del_n[5]; + struct ip_addr ip; + s32_t udpidx[5]; + u8_t bindings, fc, level, del_cnt; + + LWIP_ASSERT("pcb != NULL", pcb != NULL); + ip.addr = ntohl(pcb->local_ip.addr); + snmp_iptooid(&ip, &udpidx[0]); + udpidx[4] = pcb->local_port; + + /* count PCBs for a given binding + (e.g. when reusing ports or for temp output PCBs) */ + bindings = 0; + pcb = udp_pcbs; + while ((pcb != NULL)) + { + if ((pcb->local_ip.addr == ip.addr) && + (pcb->local_port == udpidx[4])) + { + bindings++; + } + pcb = pcb->next; + } + if (bindings == 1) + { + /* selectively remove */ + /* mark nodes for deletion */ + level = 0; + del_cnt = 0; + udp_rn = &udp_root; + while ((level < 5) && (udp_rn != NULL)) + { + fc = snmp_mib_node_find(udp_rn, udpidx[level], &udp_n); + if (fc == 0) + { + /* udpidx[level] does not exist */ + del_cnt = 0; + udp_rn = NULL; + } + else if (fc == 1) + { + del_rn[del_cnt] = udp_rn; + del_n[del_cnt] = udp_n; + del_cnt++; + udp_rn = (struct mib_list_rootnode*)(udp_n->nptr); + } + else if (fc == 2) + { + /* reset delete (2 or more childs) */ + del_cnt = 0; + udp_rn = (struct mib_list_rootnode*)(udp_n->nptr); + } + level++; + } + /* delete marked index nodes */ + while (del_cnt > 0) + { + del_cnt--; + + udp_rn = del_rn[del_cnt]; + udp_n = del_n[del_cnt]; + + next = snmp_mib_node_delete(udp_rn, udp_n); + if (next != NULL) + { + LWIP_ASSERT("next_count == 0",next->count == 0); + snmp_mib_lrn_free(next); + } + } + } + /* disable getnext traversal on empty table */ + if (udp_root.count == 0) udptable.maxlength = 0; +} + + +void snmp_inc_snmpinpkts(void) +{ + snmpinpkts++; +} + +void snmp_inc_snmpoutpkts(void) +{ + snmpoutpkts++; +} + +void snmp_inc_snmpinbadversions(void) +{ + snmpinbadversions++; +} + +void snmp_inc_snmpinbadcommunitynames(void) +{ + snmpinbadcommunitynames++; +} + +void snmp_inc_snmpinbadcommunityuses(void) +{ + snmpinbadcommunityuses++; +} + +void snmp_inc_snmpinasnparseerrs(void) +{ + snmpinasnparseerrs++; +} + +void snmp_inc_snmpintoobigs(void) +{ + snmpintoobigs++; +} + +void snmp_inc_snmpinnosuchnames(void) +{ + snmpinnosuchnames++; +} + +void snmp_inc_snmpinbadvalues(void) +{ + snmpinbadvalues++; +} + +void snmp_inc_snmpinreadonlys(void) +{ + snmpinreadonlys++; +} + +void snmp_inc_snmpingenerrs(void) +{ + snmpingenerrs++; +} + +void snmp_add_snmpintotalreqvars(u8_t value) +{ + snmpintotalreqvars += value; +} + +void snmp_add_snmpintotalsetvars(u8_t value) +{ + snmpintotalsetvars += value; +} + +void snmp_inc_snmpingetrequests(void) +{ + snmpingetrequests++; +} + +void snmp_inc_snmpingetnexts(void) +{ + snmpingetnexts++; +} + +void snmp_inc_snmpinsetrequests(void) +{ + snmpinsetrequests++; +} + +void snmp_inc_snmpingetresponses(void) +{ + snmpingetresponses++; +} + +void snmp_inc_snmpintraps(void) +{ + snmpintraps++; +} + +void snmp_inc_snmpouttoobigs(void) +{ + snmpouttoobigs++; +} + +void snmp_inc_snmpoutnosuchnames(void) +{ + snmpoutnosuchnames++; +} + +void snmp_inc_snmpoutbadvalues(void) +{ + snmpoutbadvalues++; +} + +void snmp_inc_snmpoutgenerrs(void) +{ + snmpoutgenerrs++; +} + +void snmp_inc_snmpoutgetrequests(void) +{ + snmpoutgetrequests++; +} + +void snmp_inc_snmpoutgetnexts(void) +{ + snmpoutgetnexts++; +} + +void snmp_inc_snmpoutsetrequests(void) +{ + snmpoutsetrequests++; +} + +void snmp_inc_snmpoutgetresponses(void) +{ + snmpoutgetresponses++; +} + +void snmp_inc_snmpouttraps(void) +{ + snmpouttraps++; +} + +void snmp_get_snmpgrpid_ptr(struct snmp_obj_id **oid) +{ + *oid = &snmpgrp_id; +} + +void snmp_set_snmpenableauthentraps(u8_t *value) +{ + if (value != NULL) + { + snmpenableauthentraps_ptr = value; + } +} + +void snmp_get_snmpenableauthentraps(u8_t *value) +{ + *value = *snmpenableauthentraps_ptr; +} + +void +noleafs_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) +{ + if (ident_len){} + if (ident){} + od->instance = MIB_OBJECT_NONE; +} + +void +noleafs_get_value(struct obj_def *od, u16_t len, void *value) +{ + if (od){} + if (len){} + if (value){} +} + +u8_t +noleafs_set_test(struct obj_def *od, u16_t len, void *value) +{ + if (od){} + if (len){} + if (value){} + /* can't set */ + return 0; +} + +void +noleafs_set_value(struct obj_def *od, u16_t len, void *value) +{ + if (od){} + if (len){} + if (value){} +} + + +/** + * Returns systems object definitions. + * + * @param ident_len the address length (2) + * @param ident points to objectname.0 (object id trailer) + * @param od points to object definition. + */ +static void +system_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) +{ + u8_t id; + + /* return to object name, adding index depth (1) */ + ident_len += 1; + ident -= 1; + if (ident_len == 2) + { + od->id_inst_len = ident_len; + od->id_inst_ptr = ident; + + id = ident[0]; + LWIP_DEBUGF(SNMP_MIB_DEBUG,("get_object_def system.%"U16_F".0\n",(u16_t)id)); + switch (id) + { + case 1: /* sysDescr */ + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR); + od->v_len = *sysdescr_len_ptr; + break; + case 2: /* sysObjectID */ + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID); + od->v_len = sysobjid.len * sizeof(s32_t); + break; + case 3: /* sysUpTime */ + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_TIMETICKS); + od->v_len = sizeof(u32_t); + break; + case 4: /* sysContact */ + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_WRITE; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR); + od->v_len = *syscontact_len_ptr; + break; + case 5: /* sysName */ + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_WRITE; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR); + od->v_len = *sysname_len_ptr; + break; + case 6: /* sysLocation */ + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_WRITE; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR); + od->v_len = *syslocation_len_ptr; + break; + case 7: /* sysServices */ + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); + od->v_len = sizeof(s32_t); + break; + default: + LWIP_DEBUGF(SNMP_MIB_DEBUG,("system_get_object_def: no such object\n")); + od->instance = MIB_OBJECT_NONE; + break; + }; + } + else + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("system_get_object_def: no scalar\n")); + od->instance = MIB_OBJECT_NONE; + } +} + +/** + * Returns system object value. + * + * @param ident_len the address length (2) + * @param ident points to objectname.0 (object id trailer) + * @param len return value space (in bytes) + * @param value points to (varbind) space to copy value into. + */ +static void +system_get_value(struct obj_def *od, u16_t len, void *value) +{ + u8_t id; + + id = od->id_inst_ptr[0]; + switch (id) + { + case 1: /* sysDescr */ + ocstrncpy(value,sysdescr_ptr,len); + break; + case 2: /* sysObjectID */ + objectidncpy((s32_t*)value,(s32_t*)sysobjid.id,len / sizeof(s32_t)); + break; + case 3: /* sysUpTime */ + { + u32_t *uint_ptr = value; + *uint_ptr = sysuptime; + } + break; + case 4: /* sysContact */ + ocstrncpy(value,syscontact_ptr,len); + break; + case 5: /* sysName */ + ocstrncpy(value,sysname_ptr,len); + break; + case 6: /* sysLocation */ + ocstrncpy(value,syslocation_ptr,len); + break; + case 7: /* sysServices */ + { + s32_t *sint_ptr = value; + *sint_ptr = sysservices; + } + break; + }; +} + +static u8_t +system_set_test(struct obj_def *od, u16_t len, void *value) +{ + u8_t id, set_ok; + + if (value) {} + set_ok = 0; + id = od->id_inst_ptr[0]; + switch (id) + { + case 4: /* sysContact */ + if ((syscontact_ptr != syscontact_default) && + (len <= 255)) + { + set_ok = 1; + } + break; + case 5: /* sysName */ + if ((sysname_ptr != sysname_default) && + (len <= 255)) + { + set_ok = 1; + } + break; + case 6: /* sysLocation */ + if ((syslocation_ptr != syslocation_default) && + (len <= 255)) + { + set_ok = 1; + } + break; + }; + return set_ok; +} + +static void +system_set_value(struct obj_def *od, u16_t len, void *value) +{ + u8_t id; + + id = od->id_inst_ptr[0]; + switch (id) + { + case 4: /* sysContact */ + ocstrncpy(syscontact_ptr,value,len); + *syscontact_len_ptr = len; + break; + case 5: /* sysName */ + ocstrncpy(sysname_ptr,value,len); + *sysname_len_ptr = len; + break; + case 6: /* sysLocation */ + ocstrncpy(syslocation_ptr,value,len); + *syslocation_len_ptr = len; + break; + }; +} + +/** + * Returns interfaces.ifnumber object definition. + * + * @param ident_len the address length (2) + * @param ident points to objectname.index + * @param od points to object definition. + */ +static void +interfaces_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) +{ + /* return to object name, adding index depth (1) */ + ident_len += 1; + ident -= 1; + if (ident_len == 2) + { + od->id_inst_len = ident_len; + od->id_inst_ptr = ident; + + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); + od->v_len = sizeof(s32_t); + } + else + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("interfaces_get_object_def: no scalar\n")); + od->instance = MIB_OBJECT_NONE; + } +} + +/** + * Returns interfaces.ifnumber object value. + * + * @param ident_len the address length (2) + * @param ident points to objectname.0 (object id trailer) + * @param len return value space (in bytes) + * @param value points to (varbind) space to copy value into. + */ +static void +interfaces_get_value(struct obj_def *od, u16_t len, void *value) +{ + if (len){} + if (od->id_inst_ptr[0] == 1) + { + s32_t *sint_ptr = value; + *sint_ptr = iflist_root.count; + } +} + +/** + * Returns ifentry object definitions. + * + * @param ident_len the address length (2) + * @param ident points to objectname.index + * @param od points to object definition. + */ +static void +ifentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) +{ + u8_t id; + + /* return to object name, adding index depth (1) */ + ident_len += 1; + ident -= 1; + if (ident_len == 2) + { + od->id_inst_len = ident_len; + od->id_inst_ptr = ident; + + id = ident[0]; + LWIP_DEBUGF(SNMP_MIB_DEBUG,("get_object_def ifentry.%"U16_F"\n",(u16_t)id)); + switch (id) + { + case 1: /* ifIndex */ + case 3: /* ifType */ + case 4: /* ifMtu */ + case 8: /* ifOperStatus */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); + od->v_len = sizeof(s32_t); + break; + case 2: /* ifDescr */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR); + /** @todo this should be some sort of sizeof(struct netif.name) */ + od->v_len = 2; + break; + case 5: /* ifSpeed */ + case 21: /* ifOutQLen */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_GAUGE); + od->v_len = sizeof(u32_t); + break; + case 6: /* ifPhysAddress */ + { + struct netif *netif; + + snmp_ifindextonetif(ident[1], &netif); + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR); + od->v_len = netif->hwaddr_len; + } + break; + case 7: /* ifAdminStatus */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_WRITE; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); + od->v_len = sizeof(s32_t); + break; + case 9: /* ifLastChange */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_TIMETICKS); + od->v_len = sizeof(u32_t); + break; + case 10: /* ifInOctets */ + case 11: /* ifInUcastPkts */ + case 12: /* ifInNUcastPkts */ + case 13: /* ifInDiscarts */ + case 14: /* ifInErrors */ + case 15: /* ifInUnkownProtos */ + case 16: /* ifOutOctets */ + case 17: /* ifOutUcastPkts */ + case 18: /* ifOutNUcastPkts */ + case 19: /* ifOutDiscarts */ + case 20: /* ifOutErrors */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER); + od->v_len = sizeof(u32_t); + break; + case 22: /* ifSpecific */ + /** @note returning zeroDotZero (0.0) no media specific MIB support */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID); + od->v_len = ifspecific.len * sizeof(s32_t); + break; + default: + LWIP_DEBUGF(SNMP_MIB_DEBUG,("ifentry_get_object_def: no such object\n")); + od->instance = MIB_OBJECT_NONE; + break; + }; + } + else + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("ifentry_get_object_def: no scalar\n")); + od->instance = MIB_OBJECT_NONE; + } +} + +/** + * Returns ifentry object value. + * + * @param ident_len the address length (2) + * @param ident points to objectname.0 (object id trailer) + * @param len return value space (in bytes) + * @param value points to (varbind) space to copy value into. + */ +static void +ifentry_get_value(struct obj_def *od, u16_t len, void *value) +{ + struct netif *netif; + u8_t id; + + snmp_ifindextonetif(od->id_inst_ptr[1], &netif); + id = od->id_inst_ptr[0]; + switch (id) + { + case 1: /* ifIndex */ + { + s32_t *sint_ptr = value; + *sint_ptr = od->id_inst_ptr[1]; + } + break; + case 2: /* ifDescr */ + ocstrncpy(value,(u8_t*)netif->name,len); + break; + case 3: /* ifType */ + { + s32_t *sint_ptr = value; + *sint_ptr = netif->link_type; + } + break; + case 4: /* ifMtu */ + { + s32_t *sint_ptr = value; + *sint_ptr = netif->mtu; + } + break; + case 5: /* ifSpeed */ + { + u32_t *uint_ptr = value; + *uint_ptr = netif->link_speed; + } + break; + case 6: /* ifPhysAddress */ + ocstrncpy(value,netif->hwaddr,len); + break; + case 7: /* ifAdminStatus */ + case 8: /* ifOperStatus */ + { + s32_t *sint_ptr = value; + if (netif_is_up(netif)) + { + *sint_ptr = 1; + } + else + { + *sint_ptr = 2; + } + } + break; + case 9: /* ifLastChange */ + { + u32_t *uint_ptr = value; + *uint_ptr = netif->ts; + } + break; + case 10: /* ifInOctets */ + { + u32_t *uint_ptr = value; + *uint_ptr = netif->ifinoctets; + } + break; + case 11: /* ifInUcastPkts */ + { + u32_t *uint_ptr = value; + *uint_ptr = netif->ifinucastpkts; + } + break; + case 12: /* ifInNUcastPkts */ + { + u32_t *uint_ptr = value; + *uint_ptr = netif->ifinnucastpkts; + } + break; + case 13: /* ifInDiscarts */ + { + u32_t *uint_ptr = value; + *uint_ptr = netif->ifindiscards; + } + break; + case 14: /* ifInErrors */ + case 15: /* ifInUnkownProtos */ + /** @todo add these counters! */ + { + u32_t *uint_ptr = value; + *uint_ptr = 0; + } + break; + case 16: /* ifOutOctets */ + { + u32_t *uint_ptr = value; + *uint_ptr = netif->ifoutoctets; + } + break; + case 17: /* ifOutUcastPkts */ + { + u32_t *uint_ptr = value; + *uint_ptr = netif->ifoutucastpkts; + } + break; + case 18: /* ifOutNUcastPkts */ + { + u32_t *uint_ptr = value; + *uint_ptr = netif->ifoutnucastpkts; + } + break; + case 19: /* ifOutDiscarts */ + { + u32_t *uint_ptr = value; + *uint_ptr = netif->ifoutdiscards; + } + break; + case 20: /* ifOutErrors */ + /** @todo add this counter! */ + { + u32_t *uint_ptr = value; + *uint_ptr = 0; + } + break; + case 21: /* ifOutQLen */ + /** @todo figure out if this must be 0 (no queue) or 1? */ + { + u32_t *uint_ptr = value; + *uint_ptr = 0; + } + break; + case 22: /* ifSpecific */ + objectidncpy((s32_t*)value,(s32_t*)ifspecific.id,len / sizeof(s32_t)); + break; + }; +} + +/** + * Returns atentry object definitions. + * + * @param ident_len the address length (6) + * @param ident points to objectname.atifindex.atnetaddress + * @param od points to object definition. + */ +static void +atentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) +{ + /* return to object name, adding index depth (5) */ + ident_len += 5; + ident -= 5; + + if (ident_len == 6) + { + od->id_inst_len = ident_len; + od->id_inst_ptr = ident; + + switch (ident[0]) + { + case 1: /* atIfIndex */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_WRITE; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); + od->v_len = sizeof(s32_t); + break; + case 2: /* atPhysAddress */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_WRITE; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR); + od->v_len = sizeof(struct eth_addr); + break; + case 3: /* atNetAddress */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_WRITE; + od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR); + od->v_len = 4; + break; + default: + LWIP_DEBUGF(SNMP_MIB_DEBUG,("atentry_get_object_def: no such object\n")); + od->instance = MIB_OBJECT_NONE; + break; + } + } + else + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("atentry_get_object_def: no scalar\n")); + od->instance = MIB_OBJECT_NONE; + } +} + +static void +atentry_get_value(struct obj_def *od, u16_t len, void *value) +{ + u8_t id; + struct eth_addr* ethaddr_ret; + struct ip_addr* ipaddr_ret; + struct ip_addr ip; + struct netif *netif; + + if (len) {} + + snmp_ifindextonetif(od->id_inst_ptr[1], &netif); + snmp_oidtoip(&od->id_inst_ptr[2], &ip); + ip.addr = htonl(ip.addr); + + if (etharp_find_addr(netif, &ip, ðaddr_ret, &ipaddr_ret) > -1) + { + id = od->id_inst_ptr[0]; + switch (id) + { + case 1: /* atIfIndex */ + { + s32_t *sint_ptr = value; + *sint_ptr = od->id_inst_ptr[1]; + } + break; + case 2: /* atPhysAddress */ + { + struct eth_addr *dst = value; + + *dst = *ethaddr_ret; + } + break; + case 3: /* atNetAddress */ + { + struct ip_addr *dst = value; + + *dst = *ipaddr_ret; + } + break; + } + } +} + +static void +ip_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) +{ + u8_t id; + + /* return to object name, adding index depth (1) */ + ident_len += 1; + ident -= 1; + if (ident_len == 2) + { + od->id_inst_len = ident_len; + od->id_inst_ptr = ident; + + id = ident[0]; + LWIP_DEBUGF(SNMP_MIB_DEBUG,("get_object_def ip.%"U16_F".0\n",(u16_t)id)); + switch (id) + { + case 1: /* ipForwarding */ + case 2: /* ipDefaultTTL */ + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_WRITE; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); + od->v_len = sizeof(s32_t); + break; + case 3: /* ipInReceives */ + case 4: /* ipInHdrErrors */ + case 5: /* ipInAddrErrors */ + case 6: /* ipForwDatagrams */ + case 7: /* ipInUnknownProtos */ + case 8: /* ipInDiscards */ + case 9: /* ipInDelivers */ + case 10: /* ipOutRequests */ + case 11: /* ipOutDiscards */ + case 12: /* ipOutNoRoutes */ + case 14: /* ipReasmReqds */ + case 15: /* ipReasmOKs */ + case 16: /* ipReasmFails */ + case 17: /* ipFragOKs */ + case 18: /* ipFragFails */ + case 19: /* ipFragCreates */ + case 23: /* ipRoutingDiscards */ + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER); + od->v_len = sizeof(u32_t); + break; + case 13: /* ipReasmTimeout */ + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); + od->v_len = sizeof(s32_t); + break; + default: + LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_get_object_def: no such object\n")); + od->instance = MIB_OBJECT_NONE; + break; + }; + } + else + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_get_object_def: no scalar\n")); + od->instance = MIB_OBJECT_NONE; + } +} + +static void +ip_get_value(struct obj_def *od, u16_t len, void *value) +{ + u8_t id; + + if (len) {} + id = od->id_inst_ptr[0]; + switch (id) + { + case 1: /* ipForwarding */ + { + s32_t *sint_ptr = value; +#if IP_FORWARD + /* forwarding */ + *sint_ptr = 1; +#else + /* not-forwarding */ + *sint_ptr = 2; +#endif + } + break; + case 2: /* ipDefaultTTL */ + { + s32_t *sint_ptr = value; + *sint_ptr = IP_DEFAULT_TTL; + } + break; + case 3: /* ipInReceives */ + { + u32_t *uint_ptr = value; + *uint_ptr = ipinreceives; + } + break; + case 4: /* ipInHdrErrors */ + { + u32_t *uint_ptr = value; + *uint_ptr = ipinhdrerrors; + } + break; + case 5: /* ipInAddrErrors */ + { + u32_t *uint_ptr = value; + *uint_ptr = ipinaddrerrors; + } + break; + case 6: /* ipForwDatagrams */ + { + u32_t *uint_ptr = value; + *uint_ptr = ipforwdatagrams; + } + break; + case 7: /* ipInUnknownProtos */ + { + u32_t *uint_ptr = value; + *uint_ptr = ipinunknownprotos; + } + break; + case 8: /* ipInDiscards */ + { + u32_t *uint_ptr = value; + *uint_ptr = ipindiscards; + } + break; + case 9: /* ipInDelivers */ + { + u32_t *uint_ptr = value; + *uint_ptr = ipindelivers; + } + break; + case 10: /* ipOutRequests */ + { + u32_t *uint_ptr = value; + *uint_ptr = ipoutrequests; + } + break; + case 11: /* ipOutDiscards */ + { + u32_t *uint_ptr = value; + *uint_ptr = ipoutdiscards; + } + break; + case 12: /* ipOutNoRoutes */ + { + u32_t *uint_ptr = value; + *uint_ptr = ipoutnoroutes; + } + break; + case 13: /* ipReasmTimeout */ + { + s32_t *sint_ptr = value; +#if IP_REASSEMBLY + *sint_ptr = IP_REASS_MAXAGE; +#else + *sint_ptr = 0; +#endif + } + break; + case 14: /* ipReasmReqds */ + { + u32_t *uint_ptr = value; + *uint_ptr = ipreasmreqds; + } + break; + case 15: /* ipReasmOKs */ + { + u32_t *uint_ptr = value; + *uint_ptr = ipreasmoks; + } + break; + case 16: /* ipReasmFails */ + { + u32_t *uint_ptr = value; + *uint_ptr = ipreasmfails; + } + break; + case 17: /* ipFragOKs */ + { + u32_t *uint_ptr = value; + *uint_ptr = ipfragoks; + } + break; + case 18: /* ipFragFails */ + { + u32_t *uint_ptr = value; + *uint_ptr = ipfragfails; + } + break; + case 19: /* ipFragCreates */ + { + u32_t *uint_ptr = value; + *uint_ptr = ipfragcreates; + } + break; + case 23: /* ipRoutingDiscards */ + /** @todo can lwIP discard routes at all?? hardwire this to 0?? */ + { + u32_t *uint_ptr = value; + *uint_ptr = iproutingdiscards; + } + break; + }; +} + +/** + * Test ip object value before setting. + * + * @param od is the object definition + * @param len return value space (in bytes) + * @param value points to (varbind) space to copy value from. + * + * @note we allow set if the value matches the hardwired value, + * otherwise return badvalue. + */ +static u8_t +ip_set_test(struct obj_def *od, u16_t len, void *value) +{ + u8_t id, set_ok; + s32_t *sint_ptr = value; + + if (len) {} + set_ok = 0; + id = od->id_inst_ptr[0]; + switch (id) + { + case 1: /* ipForwarding */ +#if IP_FORWARD + /* forwarding */ + if (*sint_ptr == 1) +#else + /* not-forwarding */ + if (*sint_ptr == 2) +#endif + { + set_ok = 1; + } + break; + case 2: /* ipDefaultTTL */ + if (*sint_ptr == IP_DEFAULT_TTL) + { + set_ok = 1; + } + break; + }; + return set_ok; +} + +static void +ip_addrentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) +{ + /* return to object name, adding index depth (4) */ + ident_len += 4; + ident -= 4; + + if (ident_len == 5) + { + u8_t id; + + od->id_inst_len = ident_len; + od->id_inst_ptr = ident; + + id = ident[0]; + switch (id) + { + case 1: /* ipAdEntAddr */ + case 3: /* ipAdEntNetMask */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR); + od->v_len = 4; + break; + case 2: /* ipAdEntIfIndex */ + case 4: /* ipAdEntBcastAddr */ + case 5: /* ipAdEntReasmMaxSize */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); + od->v_len = sizeof(s32_t); + break; + default: + LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_addrentry_get_object_def: no such object\n")); + od->instance = MIB_OBJECT_NONE; + break; + } + } + else + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_addrentry_get_object_def: no scalar\n")); + od->instance = MIB_OBJECT_NONE; + } +} + +static void +ip_addrentry_get_value(struct obj_def *od, u16_t len, void *value) +{ + u8_t id; + u16_t ifidx; + struct ip_addr ip; + struct netif *netif = netif_list; + + if (len) {} + snmp_oidtoip(&od->id_inst_ptr[1], &ip); + ip.addr = htonl(ip.addr); + ifidx = 0; + while ((netif != NULL) && !ip_addr_cmp(&ip, &netif->ip_addr)) + { + netif = netif->next; + ifidx++; + } + + if (netif != NULL) + { + id = od->id_inst_ptr[0]; + switch (id) + { + case 1: /* ipAdEntAddr */ + { + struct ip_addr *dst = value; + *dst = netif->ip_addr; + } + break; + case 2: /* ipAdEntIfIndex */ + { + s32_t *sint_ptr = value; + *sint_ptr = ifidx + 1; + } + break; + case 3: /* ipAdEntNetMask */ + { + struct ip_addr *dst = value; + *dst = netif->netmask; + } + break; + case 4: /* ipAdEntBcastAddr */ + { + s32_t *sint_ptr = value; + + /* lwIP oddity, there's no broadcast + address in the netif we can rely on */ + *sint_ptr = ip_addr_broadcast.addr & 1; + } + break; + case 5: /* ipAdEntReasmMaxSize */ + { + s32_t *sint_ptr = value; +#if IP_REASSEMBLY + *sint_ptr = (IP_HLEN + IP_REASS_BUFSIZE); +#else + /** @todo returning MTU would be a bad thing and + returning a wild guess like '576' isn't good either */ + *sint_ptr = 0; +#endif + } + break; + } + } +} + +/** + * @note + * lwIP IP routing is currently using the network addresses in netif_list. + * if no suitable network IP is found in netif_list, the default_netif is used. + */ +static void +ip_rteentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) +{ + u8_t id; + + /* return to object name, adding index depth (4) */ + ident_len += 4; + ident -= 4; + + if (ident_len == 5) + { + od->id_inst_len = ident_len; + od->id_inst_ptr = ident; + + id = ident[0]; + switch (id) + { + case 1: /* ipRouteDest */ + case 7: /* ipRouteNextHop */ + case 11: /* ipRouteMask */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_WRITE; + od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR); + od->v_len = 4; + break; + case 2: /* ipRouteIfIndex */ + case 3: /* ipRouteMetric1 */ + case 4: /* ipRouteMetric2 */ + case 5: /* ipRouteMetric3 */ + case 6: /* ipRouteMetric4 */ + case 8: /* ipRouteType */ + case 10: /* ipRouteAge */ + case 12: /* ipRouteMetric5 */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_WRITE; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); + od->v_len = sizeof(s32_t); + break; + case 9: /* ipRouteProto */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); + od->v_len = sizeof(s32_t); + break; + case 13: /* ipRouteInfo */ + /** @note returning zeroDotZero (0.0) no routing protocol specific MIB */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID); + od->v_len = iprouteinfo.len * sizeof(s32_t); + break; + default: + LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_rteentry_get_object_def: no such object\n")); + od->instance = MIB_OBJECT_NONE; + break; + } + } + else + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_rteentry_get_object_def: no scalar\n")); + od->instance = MIB_OBJECT_NONE; + } +} + +static void +ip_rteentry_get_value(struct obj_def *od, u16_t len, void *value) +{ + struct netif *netif; + struct ip_addr dest; + s32_t *ident; + u8_t id; + + ident = od->id_inst_ptr; + snmp_oidtoip(&ident[1], &dest); + dest.addr = htonl(dest.addr); + + if (dest.addr == 0) + { + /* ip_route() uses default netif for default route */ + netif = netif_default; + } + else + { + /* not using ip_route(), need exact match! */ + netif = netif_list; + while ((netif != NULL) && + !ip_addr_netcmp(&dest, &(netif->ip_addr), &(netif->netmask)) ) + { + netif = netif->next; + } + } + if (netif != NULL) + { + id = ident[0]; + switch (id) + { + case 1: /* ipRouteDest */ + { + struct ip_addr *dst = value; + + if (dest.addr == 0) + { + /* default rte has 0.0.0.0 dest */ + dst->addr = 0; + } + else + { + /* netifs have netaddress dest */ + dst->addr = netif->ip_addr.addr & netif->netmask.addr; + } + } + break; + case 2: /* ipRouteIfIndex */ + { + s32_t *sint_ptr = value; + + snmp_netiftoifindex(netif, sint_ptr); + } + break; + case 3: /* ipRouteMetric1 */ + { + s32_t *sint_ptr = value; + + if (dest.addr == 0) + { + /* default rte has metric 1 */ + *sint_ptr = 1; + } + else + { + /* other rtes have metric 0 */ + *sint_ptr = 0; + } + } + break; + case 4: /* ipRouteMetric2 */ + case 5: /* ipRouteMetric3 */ + case 6: /* ipRouteMetric4 */ + case 12: /* ipRouteMetric5 */ + { + s32_t *sint_ptr = value; + /* not used */ + *sint_ptr = -1; + } + break; + case 7: /* ipRouteNextHop */ + { + struct ip_addr *dst = value; + + if (dest.addr == 0) + { + /* default rte: gateway */ + *dst = netif->gw; + } + else + { + /* other rtes: netif ip_addr */ + *dst = netif->ip_addr; + } + } + break; + case 8: /* ipRouteType */ + { + s32_t *sint_ptr = value; + + if (dest.addr == 0) + { + /* default rte is indirect */ + *sint_ptr = 4; + } + else + { + /* other rtes are direct */ + *sint_ptr = 3; + } + } + break; + case 9: /* ipRouteProto */ + { + s32_t *sint_ptr = value; + /* locally defined routes */ + *sint_ptr = 2; + } + break; + case 10: /* ipRouteAge */ + { + s32_t *sint_ptr = value; + /** @todo (sysuptime - timestamp last change) / 100 + @see snmp_insert_iprteidx_tree() */ + *sint_ptr = 0; + } + break; + case 11: /* ipRouteMask */ + { + struct ip_addr *dst = value; + + if (dest.addr == 0) + { + /* default rte use 0.0.0.0 mask */ + dst->addr = 0; + } + else + { + /* other rtes use netmask */ + *dst = netif->netmask; + } + } + break; + case 13: /* ipRouteInfo */ + objectidncpy((s32_t*)value,(s32_t*)iprouteinfo.id,len / sizeof(s32_t)); + break; + } + } +} + +static void +ip_ntomentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) +{ + /* return to object name, adding index depth (5) */ + ident_len += 5; + ident -= 5; + + if (ident_len == 6) + { + u8_t id; + + od->id_inst_len = ident_len; + od->id_inst_ptr = ident; + + id = ident[0]; + switch (id) + { + case 1: /* ipNetToMediaIfIndex */ + case 4: /* ipNetToMediaType */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_WRITE; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); + od->v_len = sizeof(s32_t); + break; + case 2: /* ipNetToMediaPhysAddress */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_WRITE; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR); + od->v_len = sizeof(struct eth_addr); + break; + case 3: /* ipNetToMediaNetAddress */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_WRITE; + od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR); + od->v_len = 4; + break; + default: + LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_ntomentry_get_object_def: no such object\n")); + od->instance = MIB_OBJECT_NONE; + break; + } + } + else + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("ip_ntomentry_get_object_def: no scalar\n")); + od->instance = MIB_OBJECT_NONE; + } +} + +static void +ip_ntomentry_get_value(struct obj_def *od, u16_t len, void *value) +{ + u8_t id; + struct eth_addr* ethaddr_ret; + struct ip_addr* ipaddr_ret; + struct ip_addr ip; + struct netif *netif; + + if (len) {} + + snmp_ifindextonetif(od->id_inst_ptr[1], &netif); + snmp_oidtoip(&od->id_inst_ptr[2], &ip); + ip.addr = htonl(ip.addr); + + if (etharp_find_addr(netif, &ip, ðaddr_ret, &ipaddr_ret) > -1) + { + id = od->id_inst_ptr[0]; + switch (id) + { + case 1: /* ipNetToMediaIfIndex */ + { + s32_t *sint_ptr = value; + *sint_ptr = od->id_inst_ptr[1]; + } + break; + case 2: /* ipNetToMediaPhysAddress */ + { + struct eth_addr *dst = value; + + *dst = *ethaddr_ret; + } + break; + case 3: /* ipNetToMediaNetAddress */ + { + struct ip_addr *dst = value; + + *dst = *ipaddr_ret; + } + break; + case 4: /* ipNetToMediaType */ + { + s32_t *sint_ptr = value; + /* dynamic (?) */ + *sint_ptr = 3; + } + break; + } + } +} + +static void +icmp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) +{ + /* return to object name, adding index depth (1) */ + ident_len += 1; + ident -= 1; + if ((ident_len == 2) && + (ident[0] > 0) && (ident[0] < 27)) + { + od->id_inst_len = ident_len; + od->id_inst_ptr = ident; + + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER); + od->v_len = sizeof(u32_t); + } + else + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("icmp_get_object_def: no scalar\n")); + od->instance = MIB_OBJECT_NONE; + } +} + +static void +icmp_get_value(struct obj_def *od, u16_t len, void *value) +{ + u32_t *uint_ptr = value; + u8_t id; + + if (len){} + id = od->id_inst_ptr[0]; + switch (id) + { + case 1: /* icmpInMsgs */ + *uint_ptr = icmpinmsgs; + break; + case 2: /* icmpInErrors */ + *uint_ptr = icmpinerrors; + break; + case 3: /* icmpInDestUnreachs */ + *uint_ptr = icmpindestunreachs; + break; + case 4: /* icmpInTimeExcds */ + *uint_ptr = icmpintimeexcds; + break; + case 5: /* icmpInParmProbs */ + *uint_ptr = icmpinparmprobs; + break; + case 6: /* icmpInSrcQuenchs */ + *uint_ptr = icmpinsrcquenchs; + break; + case 7: /* icmpInRedirects */ + *uint_ptr = icmpinredirects; + break; + case 8: /* icmpInEchos */ + *uint_ptr = icmpinechos; + break; + case 9: /* icmpInEchoReps */ + *uint_ptr = icmpinechoreps; + break; + case 10: /* icmpInTimestamps */ + *uint_ptr = icmpintimestamps; + break; + case 11: /* icmpInTimestampReps */ + *uint_ptr = icmpintimestampreps; + break; + case 12: /* icmpInAddrMasks */ + *uint_ptr = icmpinaddrmasks; + break; + case 13: /* icmpInAddrMaskReps */ + *uint_ptr = icmpinaddrmaskreps; + break; + case 14: /* icmpOutMsgs */ + *uint_ptr = icmpoutmsgs; + break; + case 15: /* icmpOutErrors */ + *uint_ptr = icmpouterrors; + break; + case 16: /* icmpOutDestUnreachs */ + *uint_ptr = icmpoutdestunreachs; + break; + case 17: /* icmpOutTimeExcds */ + *uint_ptr = icmpouttimeexcds; + break; + case 18: /* icmpOutParmProbs */ + *uint_ptr = icmpoutparmprobs; + break; + case 19: /* icmpOutSrcQuenchs */ + *uint_ptr = icmpoutsrcquenchs; + break; + case 20: /* icmpOutRedirects */ + *uint_ptr = icmpoutredirects; + break; + case 21: /* icmpOutEchos */ + *uint_ptr = icmpoutechos; + break; + case 22: /* icmpOutEchoReps */ + *uint_ptr = icmpoutechoreps; + break; + case 23: /* icmpOutTimestamps */ + *uint_ptr = icmpouttimestamps; + break; + case 24: /* icmpOutTimestampReps */ + *uint_ptr = icmpouttimestampreps; + break; + case 25: /* icmpOutAddrMasks */ + *uint_ptr = icmpoutaddrmasks; + break; + case 26: /* icmpOutAddrMaskReps */ + *uint_ptr = icmpoutaddrmaskreps; + break; + } +} + +#if LWIP_TCP +/** @todo tcp grp */ +static void +tcp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) +{ + u8_t id; + + /* return to object name, adding index depth (1) */ + ident_len += 1; + ident -= 1; + if (ident_len == 2) + { + od->id_inst_len = ident_len; + od->id_inst_ptr = ident; + + id = ident[0]; + LWIP_DEBUGF(SNMP_MIB_DEBUG,("get_object_def tcp.%"U16_F".0\n",(u16_t)id)); + + switch (id) + { + case 1: /* tcpRtoAlgorithm */ + case 2: /* tcpRtoMin */ + case 3: /* tcpRtoMax */ + case 4: /* tcpMaxConn */ + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); + od->v_len = sizeof(s32_t); + break; + case 5: /* tcpActiveOpens */ + case 6: /* tcpPassiveOpens */ + case 7: /* tcpAttemptFails */ + case 8: /* tcpEstabResets */ + case 10: /* tcpInSegs */ + case 11: /* tcpOutSegs */ + case 12: /* tcpRetransSegs */ + case 14: /* tcpInErrs */ + case 15: /* tcpOutRsts */ + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER); + od->v_len = sizeof(u32_t); + break; + case 9: /* tcpCurrEstab */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_GAUGE); + od->v_len = sizeof(u32_t); + break; + default: + LWIP_DEBUGF(SNMP_MIB_DEBUG,("tcp_get_object_def: no such object\n")); + od->instance = MIB_OBJECT_NONE; + break; + }; + } + else + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("tcp_get_object_def: no scalar\n")); + od->instance = MIB_OBJECT_NONE; + } +} + +static void +tcp_get_value(struct obj_def *od, u16_t len, void *value) +{ + u32_t *uint_ptr = value; + s32_t *sint_ptr = value; + u8_t id; + + if (len){} + id = od->id_inst_ptr[0]; + switch (id) + { + case 1: /* tcpRtoAlgorithm, vanj(4) */ + *sint_ptr = 4; + break; + case 2: /* tcpRtoMin */ + /* @todo not the actual value, a guess, + needs to be calculated */ + *sint_ptr = 1000; + break; + case 3: /* tcpRtoMax */ + /* @todo not the actual value, a guess, + needs to be calculated */ + *sint_ptr = 60000; + break; + case 4: /* tcpMaxConn */ + *sint_ptr = MEMP_NUM_TCP_PCB; + break; + case 5: /* tcpActiveOpens */ + *uint_ptr = tcpactiveopens; + break; + case 6: /* tcpPassiveOpens */ + *uint_ptr = tcppassiveopens; + break; + case 7: /* tcpAttemptFails */ + *uint_ptr = tcpattemptfails; + break; + case 8: /* tcpEstabResets */ + *uint_ptr = tcpestabresets; + break; + case 9: /* tcpCurrEstab */ + { + u16_t tcpcurrestab = 0; + struct tcp_pcb *pcb = tcp_active_pcbs; + while (pcb != NULL) + { + if ((pcb->state == ESTABLISHED) || + (pcb->state == CLOSE_WAIT)) + { + tcpcurrestab++; + } + pcb = pcb->next; + } + *uint_ptr = tcpcurrestab; + } + break; + case 10: /* tcpInSegs */ + *uint_ptr = tcpinsegs; + break; + case 11: /* tcpOutSegs */ + *uint_ptr = tcpoutsegs; + break; + case 12: /* tcpRetransSegs */ + *uint_ptr = tcpretranssegs; + break; + case 14: /* tcpInErrs */ + *uint_ptr = tcpinerrs; + break; + case 15: /* tcpOutRsts */ + *uint_ptr = tcpoutrsts; + break; + } +} + +static void +tcpconnentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) +{ + /* return to object name, adding index depth (10) */ + ident_len += 10; + ident -= 10; + + if (ident_len == 11) + { + u8_t id; + + od->id_inst_len = ident_len; + od->id_inst_ptr = ident; + + id = ident[0]; + LWIP_DEBUGF(SNMP_MIB_DEBUG,("get_object_def tcp.%"U16_F".0\n",(u16_t)id)); + + switch (id) + { + case 1: /* tcpConnState */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_WRITE; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); + od->v_len = sizeof(s32_t); + break; + case 2: /* tcpConnLocalAddress */ + case 4: /* tcpConnRemAddress */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR); + od->v_len = 4; + break; + case 3: /* tcpConnLocalPort */ + case 5: /* tcpConnRemPort */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); + od->v_len = sizeof(s32_t); + break; + default: + LWIP_DEBUGF(SNMP_MIB_DEBUG,("tcpconnentry_get_object_def: no such object\n")); + od->instance = MIB_OBJECT_NONE; + break; + }; + } + else + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("tcpconnentry_get_object_def: no such object\n")); + od->instance = MIB_OBJECT_NONE; + } +} + +static void +tcpconnentry_get_value(struct obj_def *od, u16_t len, void *value) +{ + struct ip_addr lip, rip; + u16_t lport, rport; + s32_t *ident; + + ident = od->id_inst_ptr; + snmp_oidtoip(&ident[1], &lip); + lip.addr = htonl(lip.addr); + lport = ident[5]; + snmp_oidtoip(&ident[6], &rip); + rip.addr = htonl(rip.addr); + rport = ident[10]; + + /** @todo find matching PCB */ +} +#endif + +static void +udp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) +{ + /* return to object name, adding index depth (1) */ + ident_len += 1; + ident -= 1; + if ((ident_len == 2) && + (ident[0] > 0) && (ident[0] < 6)) + { + od->id_inst_len = ident_len; + od->id_inst_ptr = ident; + + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER); + od->v_len = sizeof(u32_t); + } + else + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("udp_get_object_def: no scalar\n")); + od->instance = MIB_OBJECT_NONE; + } +} + +static void +udp_get_value(struct obj_def *od, u16_t len, void *value) +{ + u32_t *uint_ptr = value; + u8_t id; + + if (len){} + id = od->id_inst_ptr[0]; + switch (id) + { + case 1: /* udpInDatagrams */ + *uint_ptr = udpindatagrams; + break; + case 2: /* udpNoPorts */ + *uint_ptr = udpnoports; + break; + case 3: /* udpInErrors */ + *uint_ptr = udpinerrors; + break; + case 4: /* udpOutDatagrams */ + *uint_ptr = udpoutdatagrams; + break; + } +} + +static void +udpentry_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) +{ + /* return to object name, adding index depth (5) */ + ident_len += 5; + ident -= 5; + + if (ident_len == 6) + { + od->id_inst_len = ident_len; + od->id_inst_ptr = ident; + + switch (ident[0]) + { + case 1: /* udpLocalAddress */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR); + od->v_len = 4; + break; + case 2: /* udpLocalPort */ + od->instance = MIB_OBJECT_TAB; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); + od->v_len = sizeof(s32_t); + break; + default: + LWIP_DEBUGF(SNMP_MIB_DEBUG,("udpentry_get_object_def: no such object\n")); + od->instance = MIB_OBJECT_NONE; + break; + } + } + else + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("udpentry_get_object_def: no scalar\n")); + od->instance = MIB_OBJECT_NONE; + } +} + +static void +udpentry_get_value(struct obj_def *od, u16_t len, void *value) +{ + u8_t id; + struct udp_pcb *pcb; + struct ip_addr ip; + u16_t port; + + if (len){} + snmp_oidtoip(&od->id_inst_ptr[1], &ip); + ip.addr = htonl(ip.addr); + port = od->id_inst_ptr[5]; + + pcb = udp_pcbs; + while ((pcb != NULL) && + !((pcb->local_ip.addr == ip.addr) && + (pcb->local_port == port))) + { + pcb = pcb->next; + } + + if (pcb != NULL) + { + id = od->id_inst_ptr[0]; + switch (id) + { + case 1: /* udpLocalAddress */ + { + struct ip_addr *dst = value; + *dst = pcb->local_ip; + } + break; + case 2: /* udpLocalPort */ + { + s32_t *sint_ptr = value; + *sint_ptr = pcb->local_port; + } + break; + } + } +} + +static void +snmp_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od) +{ + /* return to object name, adding index depth (1) */ + ident_len += 1; + ident -= 1; + if (ident_len == 2) + { + u8_t id; + + od->id_inst_len = ident_len; + od->id_inst_ptr = ident; + + id = ident[0]; + switch (id) + { + case 1: /* snmpInPkts */ + case 2: /* snmpOutPkts */ + case 3: /* snmpInBadVersions */ + case 4: /* snmpInBadCommunityNames */ + case 5: /* snmpInBadCommunityUses */ + case 6: /* snmpInASNParseErrs */ + case 8: /* snmpInTooBigs */ + case 9: /* snmpInNoSuchNames */ + case 10: /* snmpInBadValues */ + case 11: /* snmpInReadOnlys */ + case 12: /* snmpInGenErrs */ + case 13: /* snmpInTotalReqVars */ + case 14: /* snmpInTotalSetVars */ + case 15: /* snmpInGetRequests */ + case 16: /* snmpInGetNexts */ + case 17: /* snmpInSetRequests */ + case 18: /* snmpInGetResponses */ + case 19: /* snmpInTraps */ + case 20: /* snmpOutTooBigs */ + case 21: /* snmpOutNoSuchNames */ + case 22: /* snmpOutBadValues */ + case 24: /* snmpOutGenErrs */ + case 25: /* snmpOutGetRequests */ + case 26: /* snmpOutGetNexts */ + case 27: /* snmpOutSetRequests */ + case 28: /* snmpOutGetResponses */ + case 29: /* snmpOutTraps */ + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_ONLY; + od->asn_type = (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER); + od->v_len = sizeof(u32_t); + break; + case 30: /* snmpEnableAuthenTraps */ + od->instance = MIB_OBJECT_SCALAR; + od->access = MIB_OBJECT_READ_WRITE; + od->asn_type = (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG); + od->v_len = sizeof(s32_t); + break; + default: + LWIP_DEBUGF(SNMP_MIB_DEBUG,("snmp_get_object_def: no such object\n")); + od->instance = MIB_OBJECT_NONE; + break; + }; + } + else + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("snmp_get_object_def: no scalar\n")); + od->instance = MIB_OBJECT_NONE; + } +} + +static void +snmp_get_value(struct obj_def *od, u16_t len, void *value) +{ + u32_t *uint_ptr = value; + u8_t id; + + if (len){} + id = od->id_inst_ptr[0]; + switch (id) + { + case 1: /* snmpInPkts */ + *uint_ptr = snmpinpkts; + break; + case 2: /* snmpOutPkts */ + *uint_ptr = snmpoutpkts; + break; + case 3: /* snmpInBadVersions */ + *uint_ptr = snmpinbadversions; + break; + case 4: /* snmpInBadCommunityNames */ + *uint_ptr = snmpinbadcommunitynames; + break; + case 5: /* snmpInBadCommunityUses */ + *uint_ptr = snmpinbadcommunityuses; + break; + case 6: /* snmpInASNParseErrs */ + *uint_ptr = snmpinasnparseerrs; + break; + case 8: /* snmpInTooBigs */ + *uint_ptr = snmpintoobigs; + break; + case 9: /* snmpInNoSuchNames */ + *uint_ptr = snmpinnosuchnames; + break; + case 10: /* snmpInBadValues */ + *uint_ptr = snmpinbadvalues; + break; + case 11: /* snmpInReadOnlys */ + *uint_ptr = snmpinreadonlys; + break; + case 12: /* snmpInGenErrs */ + *uint_ptr = snmpingenerrs; + break; + case 13: /* snmpInTotalReqVars */ + *uint_ptr = snmpintotalreqvars; + break; + case 14: /* snmpInTotalSetVars */ + *uint_ptr = snmpintotalsetvars; + break; + case 15: /* snmpInGetRequests */ + *uint_ptr = snmpingetrequests; + break; + case 16: /* snmpInGetNexts */ + *uint_ptr = snmpingetnexts; + break; + case 17: /* snmpInSetRequests */ + *uint_ptr = snmpinsetrequests; + break; + case 18: /* snmpInGetResponses */ + *uint_ptr = snmpingetresponses; + break; + case 19: /* snmpInTraps */ + *uint_ptr = snmpintraps; + break; + case 20: /* snmpOutTooBigs */ + *uint_ptr = snmpouttoobigs; + break; + case 21: /* snmpOutNoSuchNames */ + *uint_ptr = snmpoutnosuchnames; + break; + case 22: /* snmpOutBadValues */ + *uint_ptr = snmpoutbadvalues; + break; + case 24: /* snmpOutGenErrs */ + *uint_ptr = snmpoutgenerrs; + break; + case 25: /* snmpOutGetRequests */ + *uint_ptr = snmpoutgetrequests; + break; + case 26: /* snmpOutGetNexts */ + *uint_ptr = snmpoutgetnexts; + break; + case 27: /* snmpOutSetRequests */ + *uint_ptr = snmpoutsetrequests; + break; + case 28: /* snmpOutGetResponses */ + *uint_ptr = snmpoutgetresponses; + break; + case 29: /* snmpOutTraps */ + *uint_ptr = snmpouttraps; + break; + case 30: /* snmpEnableAuthenTraps */ + *uint_ptr = *snmpenableauthentraps_ptr; + break; + }; +} + +/** + * Test snmp object value before setting. + * + * @param od is the object definition + * @param len return value space (in bytes) + * @param value points to (varbind) space to copy value from. + */ +static u8_t +snmp_set_test(struct obj_def *od, u16_t len, void *value) +{ + u8_t id, set_ok; + + if (len) {} + set_ok = 0; + id = od->id_inst_ptr[0]; + if (id == 30) + { + /* snmpEnableAuthenTraps */ + s32_t *sint_ptr = value; + + if (snmpenableauthentraps_ptr != &snmpenableauthentraps_default) + { + /* we should have writable non-volatile mem here */ + if ((*sint_ptr == 1) || (*sint_ptr == 2)) + { + set_ok = 1; + } + } + else + { + /* const or hardwired value */ + if (*sint_ptr == snmpenableauthentraps_default) + { + set_ok = 1; + } + } + } + return set_ok; +} + +static void +snmp_set_value(struct obj_def *od, u16_t len, void *value) +{ + u8_t id; + + if (len) {} + id = od->id_inst_ptr[0]; + if (id == 30) + { + /* snmpEnableAuthenTraps */ + s32_t *sint_ptr = value; + *snmpenableauthentraps_ptr = *sint_ptr; + } +} + +#endif /* LWIP_SNMP */ diff --git a/20080212/Demo/Common/ethernet/lwIP/core/snmp/mib_structs.c b/20080212/Demo/Common/ethernet/lwIP/core/snmp/mib_structs.c new file mode 100644 index 000000000..1fad58865 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/core/snmp/mib_structs.c @@ -0,0 +1,1185 @@ +/** + * @file + * MIB tree access/construction functions. + */ + +/* + * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Christiaan Simons + */ + +#include "lwip/opt.h" + +#if LWIP_SNMP +#include "lwip/snmp_structs.h" +#include "lwip/mem.h" + + + +/** .iso.org.dod.internet address prefix, @see snmp_iso_*() */ +const s32_t prefix[4] = {1, 3, 6, 1}; + +#define NODE_STACK_SIZE (LWIP_SNMP_OBJ_ID_LEN) +/** node stack entry (old news?) */ +struct nse +{ + /** right child */ + struct mib_node* r_ptr; + /** right child identifier */ + s32_t r_id; + /** right child next level */ + u8_t r_nl; +}; +static u8_t node_stack_cnt = 0; +static struct nse node_stack[NODE_STACK_SIZE]; + +/** + * Pushes nse struct onto stack. + */ +static void +push_node(struct nse* node) +{ + LWIP_ASSERT("node_stack_cnt < NODE_STACK_SIZE",node_stack_cnt < NODE_STACK_SIZE); + LWIP_DEBUGF(SNMP_MIB_DEBUG,("push_node() node=%p id=%"S32_F"\n",(void*)(node->r_ptr),node->r_id)); + if (node_stack_cnt < NODE_STACK_SIZE) + { + node_stack[node_stack_cnt] = *node; + node_stack_cnt++; + } +} + +/** + * Pops nse struct from stack. + */ +static void +pop_node(struct nse* node) +{ + if (node_stack_cnt > 0) + { + node_stack_cnt--; + *node = node_stack[node_stack_cnt]; + } + LWIP_DEBUGF(SNMP_MIB_DEBUG,("pop_node() node=%p id=%"S32_F"\n",(void *)(node->r_ptr),node->r_id)); +} + +/** + * Conversion from ifIndex to lwIP netif + * @param ifindex is a s32_t object sub-identifier + * @param netif points to returned netif struct pointer + */ +void +snmp_ifindextonetif(s32_t ifindex, struct netif **netif) +{ + struct netif *nif = netif_list; + u16_t i, ifidx; + + ifidx = ifindex - 1; + i = 0; + while ((nif != NULL) && (i < ifidx)) + { + nif = nif->next; + i++; + } + *netif = nif; +} + +/** + * Conversion from lwIP netif to ifIndex + * @param netif points to a netif struct + * @param ifindex points to s32_t object sub-identifier + */ +void +snmp_netiftoifindex(struct netif *netif, s32_t *ifidx) +{ + struct netif *nif = netif_list; + u16_t i; + + i = 0; + while (nif != netif) + { + nif = nif->next; + i++; + } + *ifidx = i+1; +} + +/** + * Conversion from oid to lwIP ip_addr + * @param ident points to s32_t ident[4] input + * @param ip points to output struct + */ +void +snmp_oidtoip(s32_t *ident, struct ip_addr *ip) +{ + u32_t ipa; + + ipa = ident[0]; + ipa <<= 8; + ipa |= ident[1]; + ipa <<= 8; + ipa |= ident[2]; + ipa <<= 8; + ipa |= ident[3]; + ip->addr = ipa; +} + +/** + * Conversion from lwIP ip_addr to oid + * @param ip points to input struct + * @param ident points to s32_t ident[4] output + */ +void +snmp_iptooid(struct ip_addr *ip, s32_t *ident) +{ + u32_t ipa; + + ipa = ip->addr; + ident[0] = (ipa >> 24) & 0xff; + ident[1] = (ipa >> 16) & 0xff; + ident[2] = (ipa >> 8) & 0xff; + ident[3] = ipa & 0xff; +} + +struct mib_list_node * +snmp_mib_ln_alloc(s32_t id) +{ + struct mib_list_node *ln; + + ln = (struct mib_list_node *)mem_malloc(sizeof(struct mib_list_node)); + if (ln != NULL) + { + ln->prev = NULL; + ln->next = NULL; + ln->objid = id; + ln->nptr = NULL; + } + return ln; +} + +void +snmp_mib_ln_free(struct mib_list_node *ln) +{ + mem_free(ln); +} + +struct mib_list_rootnode * +snmp_mib_lrn_alloc(void) +{ + struct mib_list_rootnode *lrn; + + lrn = (struct mib_list_rootnode*)mem_malloc(sizeof(struct mib_list_rootnode)); + if (lrn != NULL) + { + lrn->get_object_def = noleafs_get_object_def; + lrn->get_value = noleafs_get_value; + lrn->set_test = noleafs_set_test; + lrn->set_value = noleafs_set_value; + lrn->node_type = MIB_NODE_LR; + lrn->maxlength = 0; + lrn->head = NULL; + lrn->tail = NULL; + lrn->count = 0; + } + return lrn; +} + +void +snmp_mib_lrn_free(struct mib_list_rootnode *lrn) +{ + mem_free(lrn); +} + +/** + * Inserts node in idx list in a sorted + * (ascending order) fashion and + * allocates the node if needed. + * + * @param rn points to the root node + * @param objid is the object sub identifier + * @param insn points to a pointer to the inserted node + * used for constructing the tree. + * @return -1 if failed, 1 if inserted, 2 if present. + */ +s8_t +snmp_mib_node_insert(struct mib_list_rootnode *rn, s32_t objid, struct mib_list_node **insn) +{ + struct mib_list_node *nn; + s8_t insert; + + LWIP_ASSERT("rn != NULL",rn != NULL); + + /* -1 = malloc failure, 0 = not inserted, 1 = inserted, 2 = was present */ + insert = 0; + if (rn->head == NULL) + { + /* empty list, add first node */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("alloc empty list objid==%"S32_F"\n",objid)); + nn = snmp_mib_ln_alloc(objid); + if (nn != NULL) + { + rn->head = nn; + rn->tail = nn; + *insn = nn; + insert = 1; + } + else + { + insert = -1; + } + } + else + { + struct mib_list_node *n; + /* at least one node is present */ + n = rn->head; + while ((n != NULL) && (insert == 0)) + { + if (n->objid == objid) + { + /* node is already there */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("node already there objid==%"S32_F"\n",objid)); + *insn = n; + insert = 2; + } + else if (n->objid < objid) + { + if (n->next == NULL) + { + /* alloc and insert at the tail */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("alloc ins tail objid==%"S32_F"\n",objid)); + nn = snmp_mib_ln_alloc(objid); + if (nn != NULL) + { + nn->next = NULL; + nn->prev = n; + n->next = nn; + rn->tail = nn; + *insn = nn; + insert = 1; + } + else + { + /* insertion failure */ + insert = -1; + } + } + else + { + /* there's more to explore: traverse list */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("traverse list\n")); + n = n->next; + } + } + else + { + /* n->objid > objid */ + /* alloc and insert between n->prev and n */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("alloc ins n->prev, objid==%"S32_F", n\n",objid)); + nn = snmp_mib_ln_alloc(objid); + if (nn != NULL) + { + if (n->prev == NULL) + { + /* insert at the head */ + nn->next = n; + nn->prev = NULL; + rn->head = nn; + n->prev = nn; + } + else + { + /* insert in the middle */ + nn->next = n; + nn->prev = n->prev; + n->prev->next = nn; + n->prev = nn; + } + *insn = nn; + insert = 1; + } + else + { + /* insertion failure */ + insert = -1; + } + } + } + } + if (insert == 1) + { + rn->count += 1; + } + LWIP_ASSERT("insert != 0",insert != 0); + return insert; +} + +/** + * Finds node in idx list and returns deletion mark. + * + * @param rn points to the root node + * @param objid is the object sub identifier + * @param fn returns pointer to found node + * @return 0 if not found, 1 if deletable, + * 2 can't delete (2 or more children), 3 not a list_node + */ +s8_t +snmp_mib_node_find(struct mib_list_rootnode *rn, s32_t objid, struct mib_list_node **fn) +{ + s8_t fc; + struct mib_list_node *n; + + LWIP_ASSERT("rn != NULL",rn != NULL); + n = rn->head; + while ((n != NULL) && (n->objid != objid)) + { + n = n->next; + } + if (n == NULL) + { + fc = 0; + } + else if (n->nptr == NULL) + { + /* leaf, can delete node */ + fc = 1; + } + else + { + struct mib_list_rootnode *rn; + + if (n->nptr->node_type == MIB_NODE_LR) + { + rn = (struct mib_list_rootnode *)n->nptr; + if (rn->count > 1) + { + /* can't delete node */ + fc = 2; + } + else + { + /* count <= 1, can delete node */ + fc = 1; + } + } + else + { + /* other node type */ + fc = 3; + } + } + *fn = n; + return fc; +} + +/** + * Removes node from idx list + * if it has a single child left. + * + * @param rn points to the root node + * @param n points to the node to delete + * @return the nptr to be freed by caller + */ +struct mib_list_rootnode * +snmp_mib_node_delete(struct mib_list_rootnode *rn, struct mib_list_node *n) +{ + struct mib_list_rootnode *next; + + LWIP_ASSERT("rn != NULL",rn != NULL); + LWIP_ASSERT("n != NULL",n != NULL); + + /* caller must remove this sub-tree */ + next = (struct mib_list_rootnode*)(n->nptr); + rn->count -= 1; + + if (n == rn->head) + { + rn->head = n->next; + if (n->next != NULL) + { + /* not last node, new list begin */ + n->next->prev = NULL; + } + } + else if (n == rn->tail) + { + rn->tail = n->prev; + if (n->prev != NULL) + { + /* not last node, new list end */ + n->prev->next = NULL; + } + } + else + { + /* node must be in the middle */ + n->prev->next = n->next; + n->next->prev = n->prev; + } + LWIP_DEBUGF(SNMP_MIB_DEBUG,("free list objid==%"S32_F"\n",n->objid)); + snmp_mib_ln_free(n); + if (rn->count == 0) + { + rn->head = NULL; + rn->tail = NULL; + } + return next; +} + + + +/** + * Searches tree for the supplied (scalar?) object identifier. + * + * @param node points to the root of the tree ('.internet') + * @param ident_len the length of the supplied object identifier + * @param ident points to the array of sub identifiers + * @param np points to the found object instance (rerurn) + * @return pointer to the requested parent (!) node if success, NULL otherwise + */ +struct mib_node * +snmp_search_tree(struct mib_node *node, u8_t ident_len, s32_t *ident, struct snmp_name_ptr *np) +{ + u8_t node_type, ext_level; + + ext_level = 0; + LWIP_DEBUGF(SNMP_MIB_DEBUG,("node==%p *ident==%"S32_F"\n",(void*)node,*ident)); + while (node != NULL) + { + node_type = node->node_type; + if ((node_type == MIB_NODE_AR) || (node_type == MIB_NODE_RA)) + { + struct mib_array_node *an; + u16_t i; + + if (ident_len > 0) + { + /* array node (internal ROM or RAM, fixed length) */ + an = (struct mib_array_node *)node; + i = 0; + while ((i < an->maxlength) && (an->objid[i] != *ident)) + { + i++; + } + if (i < an->maxlength) + { + /* found it, if available proceed to child, otherwise inspect leaf */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("an->objid[%"U16_F"]==%"S32_F" *ident==%"S32_F"\n",i,an->objid[i],*ident)); + if (an->nptr[i] == NULL) + { + /* a scalar leaf OR table, + inspect remaining instance number / table index */ + np->ident_len = ident_len; + np->ident = ident; + return (struct mib_node*)an; + } + else + { + /* follow next child pointer */ + ident++; + ident_len--; + node = an->nptr[i]; + } + } + else + { + /* search failed, identifier mismatch (nosuchname) */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("an search failed *ident==%"S32_F"\n",*ident)); + return NULL; + } + } + else + { + /* search failed, short object identifier (nosuchname) */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("an search failed, short object identifier\n")); + return NULL; + } + } + else if(node_type == MIB_NODE_LR) + { + struct mib_list_rootnode *lrn; + struct mib_list_node *ln; + + if (ident_len > 0) + { + /* list root node (internal 'RAM', variable length) */ + lrn = (struct mib_list_rootnode *)node; + ln = lrn->head; + /* iterate over list, head to tail */ + while ((ln != NULL) && (ln->objid != *ident)) + { + ln = ln->next; + } + if (ln != NULL) + { + /* found it, proceed to child */; + LWIP_DEBUGF(SNMP_MIB_DEBUG,("ln->objid==%"S32_F" *ident==%"S32_F"\n",ln->objid,*ident)); + if (ln->nptr == NULL) + { + np->ident_len = ident_len; + np->ident = ident; + return (struct mib_node*)lrn; + } + else + { + /* follow next child pointer */ + ident_len--; + ident++; + node = ln->nptr; + } + } + else + { + /* search failed */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("ln search failed *ident==%"S32_F"\n",*ident)); + return NULL; + } + } + else + { + /* search failed, short object identifier (nosuchname) */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("ln search failed, short object identifier\n")); + return NULL; + } + } + else if(node_type == MIB_NODE_EX) + { + struct mib_external_node *en; + u16_t i, len; + + if (ident_len > 0) + { + /* external node (addressing and access via functions) */ + en = (struct mib_external_node *)node; + + i = 0; + len = en->level_length(en->addr_inf,ext_level); + while ((i < len) && (en->ident_cmp(en->addr_inf,ext_level,i,*ident) != 0)) + { + i++; + } + if (i < len) + { + s32_t debug_id; + + en->get_objid(en->addr_inf,ext_level,i,&debug_id); + LWIP_DEBUGF(SNMP_MIB_DEBUG,("en->objid==%"S32_F" *ident==%"S32_F"\n",debug_id,*ident)); + if ((ext_level + 1) == en->tree_levels) + { + np->ident_len = ident_len; + np->ident = ident; + return (struct mib_node*)en; + } + else + { + /* found it, proceed to child */ + ident_len--; + ident++; + ext_level++; + } + } + else + { + /* search failed */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("en search failed *ident==%"S32_F"\n",*ident)); + return NULL; + } + } + else + { + /* search failed, short object identifier (nosuchname) */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("en search failed, short object identifier\n")); + return NULL; + } + } + else if (node_type == MIB_NODE_SC) + { + mib_scalar_node *sn; + + sn = (mib_scalar_node *)node; + if ((ident_len == 1) && (*ident == 0)) + { + np->ident_len = ident_len; + np->ident = ident; + return (struct mib_node*)sn; + } + else + { + /* search failed, short object identifier (nosuchname) */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("search failed, invalid object identifier length\n")); + return NULL; + } + } + else + { + /* unknown node_type */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("search failed node_type %"U16_F" unkown\n",(u16_t)node_type)); + return NULL; + } + } + /* done, found nothing */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("search failed node==%p\n",(void*)node)); + return NULL; +} + +/** + * Test table for presence of at least one table entry. + */ +static u8_t +empty_table(struct mib_node *node) +{ + u8_t node_type; + u8_t empty = 0; + + if (node != NULL) + { + node_type = node->node_type; + if (node_type == MIB_NODE_LR) + { + struct mib_list_rootnode *lrn; + lrn = (struct mib_list_rootnode *)node; + if ((lrn->count == 0) || (lrn->head == NULL)) + { + empty = 1; + } + } + else if ((node_type == MIB_NODE_AR) || (node_type == MIB_NODE_RA)) + { + struct mib_array_node *an; + an = (struct mib_array_node *)node; + if ((an->maxlength == 0) || (an->nptr == NULL)) + { + empty = 1; + } + } + else if (node_type == MIB_NODE_EX) + { + struct mib_external_node *en; + en = (struct mib_external_node *)node; + if (en->tree_levels == 0) + { + empty = 1; + } + } + } + return empty; +} + +/** + * Tree expansion. + */ +struct mib_node * +snmp_expand_tree(struct mib_node *node, u8_t ident_len, s32_t *ident, struct snmp_obj_id *oidret) +{ + u8_t node_type, ext_level, climb_tree; + + ext_level = 0; + /* reset node stack */ + node_stack_cnt = 0; + while (node != NULL) + { + climb_tree = 0; + node_type = node->node_type; + if ((node_type == MIB_NODE_AR) || (node_type == MIB_NODE_RA)) + { + struct mib_array_node *an; + u16_t i; + + /* array node (internal ROM or RAM, fixed length) */ + an = (struct mib_array_node *)node; + if (ident_len > 0) + { + i = 0; + while ((i < an->maxlength) && (an->objid[i] < *ident)) + { + i++; + } + if (i < an->maxlength) + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("an->objid[%"U16_F"]==%"S32_F" *ident==%"S32_F"\n",i,an->objid[i],*ident)); + /* add identifier to oidret */ + oidret->id[oidret->len] = an->objid[i]; + (oidret->len)++; + + if (an->nptr[i] == NULL) + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("leaf node\n")); + /* leaf node (e.g. in a fixed size table) */ + if (an->objid[i] > *ident) + { + return (struct mib_node*)an; + } + else if ((i + 1) < an->maxlength) + { + /* an->objid[i] == *ident */ + (oidret->len)--; + oidret->id[oidret->len] = an->objid[i + 1]; + (oidret->len)++; + return (struct mib_node*)an; + } + else + { + /* (i + 1) == an->maxlength */ + (oidret->len)--; + climb_tree = 1; + } + } + else + { + u8_t j; + struct nse cur_node; + + LWIP_DEBUGF(SNMP_MIB_DEBUG,("non-leaf node\n")); + /* non-leaf, store right child ptr and id */ + j = i + 1; + while ((j < an->maxlength) && (empty_table(an->nptr[j]))) + { + j++; + } + if (j < an->maxlength) + { + cur_node.r_ptr = an->nptr[j]; + cur_node.r_id = an->objid[j]; + cur_node.r_nl = 0; + } + else + { + cur_node.r_ptr = NULL; + } + push_node(&cur_node); + if (an->objid[i] == *ident) + { + ident_len--; + ident++; + } + else + { + /* an->objid[i] < *ident */ + ident_len = 0; + } + /* follow next child pointer */ + node = an->nptr[i]; + } + } + else + { + /* i == an->maxlength */ + climb_tree = 1; + } + } + else + { + u8_t j; + /* ident_len == 0, complete with leftmost '.thing' */ + j = 0; + while ((j < an->maxlength) && empty_table(an->nptr[j])) + { + j++; + } + if (j < an->maxlength) + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("left an->objid[j]==%"S32_F"\n",an->objid[j])); + oidret->id[oidret->len] = an->objid[j]; + (oidret->len)++; + if (an->nptr[j] == NULL) + { + /* leaf node */ + return (struct mib_node*)an; + } + else + { + /* no leaf, continue */ + node = an->nptr[j]; + } + } + else + { + /* j == an->maxlength */ + climb_tree = 1; + } + } + } + else if(node_type == MIB_NODE_LR) + { + struct mib_list_rootnode *lrn; + struct mib_list_node *ln; + + /* list root node (internal 'RAM', variable length) */ + lrn = (struct mib_list_rootnode *)node; + if (ident_len > 0) + { + ln = lrn->head; + /* iterate over list, head to tail */ + while ((ln != NULL) && (ln->objid < *ident)) + { + ln = ln->next; + } + if (ln != NULL) + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("ln->objid==%"S32_F" *ident==%"S32_F"\n",ln->objid,*ident)); + oidret->id[oidret->len] = ln->objid; + (oidret->len)++; + if (ln->nptr == NULL) + { + /* leaf node */ + if (ln->objid > *ident) + { + return (struct mib_node*)lrn; + } + else if (ln->next != NULL) + { + /* ln->objid == *ident */ + (oidret->len)--; + oidret->id[oidret->len] = ln->next->objid; + (oidret->len)++; + return (struct mib_node*)lrn; + } + else + { + /* ln->next == NULL */ + (oidret->len)--; + climb_tree = 1; + } + } + else + { + struct mib_list_node *jn; + struct nse cur_node; + + /* non-leaf, store right child ptr and id */ + jn = ln->next; + while ((jn != NULL) && empty_table(jn->nptr)) + { + jn = jn->next; + } + if (jn != NULL) + { + cur_node.r_ptr = jn->nptr; + cur_node.r_id = jn->objid; + cur_node.r_nl = 0; + } + else + { + cur_node.r_ptr = NULL; + } + push_node(&cur_node); + if (ln->objid == *ident) + { + ident_len--; + ident++; + } + else + { + /* ln->objid < *ident */ + ident_len = 0; + } + /* follow next child pointer */ + node = ln->nptr; + } + + } + else + { + /* ln == NULL */ + climb_tree = 1; + } + } + else + { + struct mib_list_node *jn; + /* ident_len == 0, complete with leftmost '.thing' */ + jn = lrn->head; + while ((jn != NULL) && empty_table(jn->nptr)) + { + jn = jn->next; + } + if (jn != NULL) + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("left jn->objid==%"S32_F"\n",jn->objid)); + oidret->id[oidret->len] = jn->objid; + (oidret->len)++; + if (jn->nptr == NULL) + { + /* leaf node */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("jn->nptr == NULL\n")); + return (struct mib_node*)lrn; + } + else + { + /* no leaf, continue */ + node = jn->nptr; + } + } + else + { + /* jn == NULL */ + climb_tree = 1; + } + } + } + else if(node_type == MIB_NODE_EX) + { + struct mib_external_node *en; + s32_t ex_id; + + /* external node (addressing and access via functions) */ + en = (struct mib_external_node *)node; + if (ident_len > 0) + { + u16_t i, len; + + i = 0; + len = en->level_length(en->addr_inf,ext_level); + while ((i < len) && (en->ident_cmp(en->addr_inf,ext_level,i,*ident) < 0)) + { + i++; + } + if (i < len) + { + /* add identifier to oidret */ + en->get_objid(en->addr_inf,ext_level,i,&ex_id); + LWIP_DEBUGF(SNMP_MIB_DEBUG,("en->objid[%"U16_F"]==%"S32_F" *ident==%"S32_F"\n",i,ex_id,*ident)); + oidret->id[oidret->len] = ex_id; + (oidret->len)++; + + if ((ext_level + 1) == en->tree_levels) + { + LWIP_DEBUGF(SNMP_MIB_DEBUG,("leaf node\n")); + /* leaf node */ + if (ex_id > *ident) + { + return (struct mib_node*)en; + } + else if ((i + 1) < len) + { + /* ex_id == *ident */ + en->get_objid(en->addr_inf,ext_level,i + 1,&ex_id); + (oidret->len)--; + oidret->id[oidret->len] = ex_id; + (oidret->len)++; + return (struct mib_node*)en; + } + else + { + /* (i + 1) == len */ + (oidret->len)--; + climb_tree = 1; + } + } + else + { + u8_t j; + struct nse cur_node; + + LWIP_DEBUGF(SNMP_MIB_DEBUG,("non-leaf node\n")); + /* non-leaf, store right child ptr and id */ + j = i + 1; + if (j < len) + { + /* right node is the current external node */ + cur_node.r_ptr = node; + en->get_objid(en->addr_inf,ext_level,j,&cur_node.r_id); + cur_node.r_nl = ext_level + 1; + } + else + { + cur_node.r_ptr = NULL; + } + push_node(&cur_node); + if (en->ident_cmp(en->addr_inf,ext_level,i,*ident) == 0) + { + ident_len--; + ident++; + } + else + { + /* external id < *ident */ + ident_len = 0; + } + /* proceed to child */ + ext_level++; + } + } + else + { + /* i == len (en->level_len()) */ + climb_tree = 1; + } + } + else + { + /* ident_len == 0, complete with leftmost '.thing' */ + en->get_objid(en->addr_inf,ext_level,0,&ex_id); + LWIP_DEBUGF(SNMP_MIB_DEBUG,("left en->objid==%"S32_F"\n",ex_id)); + oidret->id[oidret->len] = ex_id; + (oidret->len)++; + if ((ext_level + 1) == en->tree_levels) + { + /* leaf node */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("(ext_level + 1) == en->tree_levels\n")); + return (struct mib_node*)en; + } + else + { + /* no leaf, proceed to child */ + ext_level++; + } + } + } + else if(node_type == MIB_NODE_SC) + { + mib_scalar_node *sn; + + /* scalar node */ + sn = (mib_scalar_node *)node; + if (ident_len > 0) + { + /* at .0 */ + climb_tree = 1; + } + else + { + /* ident_len == 0, complete object identifier */ + oidret->id[oidret->len] = 0; + (oidret->len)++; + /* leaf node */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("completed scalar leaf\n")); + return (struct mib_node*)sn; + } + } + else + { + /* unknown/unhandled node_type */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("expand failed node_type %"U16_F" unkown\n",(u16_t)node_type)); + return NULL; + } + + if (climb_tree) + { + struct nse child; + + /* find right child ptr */ + child.r_ptr = NULL; + child.r_id = 0; + child.r_nl = 0; + while ((node_stack_cnt > 0) && (child.r_ptr == NULL)) + { + pop_node(&child); + /* trim returned oid */ + (oidret->len)--; + } + if (child.r_ptr != NULL) + { + /* incoming ident is useless beyond this point */ + ident_len = 0; + oidret->id[oidret->len] = child.r_id; + oidret->len++; + node = child.r_ptr; + ext_level = child.r_nl; + } + else + { + /* tree ends here ... */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("expand failed, tree ends here\n")); + return NULL; + } + } + } + /* done, found nothing */ + LWIP_DEBUGF(SNMP_MIB_DEBUG,("expand failed node==%p\n",(void*)node)); + return NULL; +} + +/** + * Test object identifier for the iso.org.dod.internet prefix. + * + * @param ident_len the length of the supplied object identifier + * @param ident points to the array of sub identifiers + * @return 1 if it matches, 0 otherwise + */ +u8_t +snmp_iso_prefix_tst(u8_t ident_len, s32_t *ident) +{ + if ((ident_len > 3) && + (ident[0] == 1) && (ident[1] == 3) && + (ident[2] == 6) && (ident[3] == 1)) + { + return 1; + } + else + { + return 0; + } +} + +/** + * Expands object identifier to the iso.org.dod.internet + * prefix for use in getnext operation. + * + * @param ident_len the length of the supplied object identifier + * @param ident points to the array of sub identifiers + * @param oidret points to returned expanded object identifier + * @return 1 if it matches, 0 otherwise + * + * @note ident_len 0 is allowed, expanding to the first known object id!! + */ +u8_t +snmp_iso_prefix_expand(u8_t ident_len, s32_t *ident, struct snmp_obj_id *oidret) +{ + const s32_t *prefix_ptr; + s32_t *ret_ptr; + u8_t i; + + i = 0; + prefix_ptr = &prefix[0]; + ret_ptr = &oidret->id[0]; + ident_len = ((ident_len < 4)?ident_len:4); + while ((i < ident_len) && ((*ident) <= (*prefix_ptr))) + { + *ret_ptr++ = *prefix_ptr++; + ident++; + i++; + } + if (i == ident_len) + { + /* match, complete missing bits */ + while (i < 4) + { + *ret_ptr++ = *prefix_ptr++; + i++; + } + oidret->len = i; + return 1; + } + else + { + /* i != ident_len */ + return 0; + } +} + +#endif /* LWIP_SNMP */ + diff --git a/20080212/Demo/Common/ethernet/lwIP/core/snmp/msg_in.c b/20080212/Demo/Common/ethernet/lwIP/core/snmp/msg_in.c new file mode 100644 index 000000000..1999d13da --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/core/snmp/msg_in.c @@ -0,0 +1,1458 @@ +/** + * @file + * SNMP input message processing (RFC1157). + */ + +/* + * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Christiaan Simons + */ + +#include "lwip/opt.h" + +#if LWIP_SNMP +#include +#include "arch/cc.h" +#include "lwip/ip_addr.h" +#include "lwip/mem.h" +#include "lwip/udp.h" +#include "lwip/stats.h" + +#include "lwip/snmp.h" +#include "lwip/snmp_asn1.h" +#include "lwip/snmp_msg.h" +#include "lwip/snmp_structs.h" + + +/* public (non-static) constants */ +/** SNMP v1 == 0 */ +const s32_t snmp_version = 0; +/** default SNMP community string */ +const char snmp_publiccommunity[7] = "public"; + +/* statically allocated buffers for SNMP_CONCURRENT_REQUESTS */ +#if (SNMP_CONCURRENT_REQUESTS == 0) +#error "need at least one snmp_msg_pstat" +#endif +struct snmp_msg_pstat msg_input_list[SNMP_CONCURRENT_REQUESTS]; +/* UDP Protocol Control Block */ +struct udp_pcb *snmp1_pcb = NULL; + +static void snmp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *addr, u16_t port); +static err_t snmp_pdu_header_check(struct pbuf *p, u16_t ofs, u16_t pdu_len, u16_t *ofs_ret, struct snmp_msg_pstat *m_stat); +static err_t snmp_pdu_dec_varbindlist(struct pbuf *p, u16_t ofs, u16_t *ofs_ret, struct snmp_msg_pstat *m_stat); + + +/** + * Starts SNMP Agent. + * Allocates UDP pcb and binds it to IP_ADDR_ANY port 161. + */ +void +snmp_init(void) +{ + struct snmp_msg_pstat *msg_ps; + u8_t i; + + snmp1_pcb = udp_new(); + if (snmp1_pcb != NULL) + { + udp_recv(snmp1_pcb, snmp_recv, (void *)SNMP_IN_PORT); + udp_bind(snmp1_pcb, IP_ADDR_ANY, SNMP_IN_PORT); + } + msg_ps = &msg_input_list[0]; + for (i=0; istate = SNMP_MSG_EMPTY; + msg_ps->error_index = 0; + msg_ps->error_status = SNMP_ES_NOERROR; + msg_ps++; + } + trap_msg.pcb = snmp1_pcb; + /* The coldstart trap will only be output + if our outgoing interface is up & configured */ + snmp_coldstart_trap(); +} + +static void +snmp_error_response(struct snmp_msg_pstat *msg_ps, u8_t error) +{ + snmp_varbind_list_free(&msg_ps->outvb); + msg_ps->outvb = msg_ps->invb; + msg_ps->invb.head = NULL; + msg_ps->invb.tail = NULL; + msg_ps->invb.count = 0; + msg_ps->error_status = error; + msg_ps->error_index = 1 + msg_ps->vb_idx; + snmp_send_response(msg_ps); + snmp_varbind_list_free(&msg_ps->outvb); + msg_ps->state = SNMP_MSG_EMPTY; +} + +static void +snmp_ok_response(struct snmp_msg_pstat *msg_ps) +{ + err_t err_ret; + + err_ret = snmp_send_response(msg_ps); + if (err_ret == ERR_MEM) + { + /* serious memory problem, can't return tooBig */ +#if LWIP_STATS + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_event pbufs.used = %"U16_F"\n",lwip_stats.pbuf.used)); +#endif + } + else + { + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_event = %"S32_F"\n",msg_ps->error_status)); + } + /* free varbinds (if available) */ + snmp_varbind_list_free(&msg_ps->invb); + snmp_varbind_list_free(&msg_ps->outvb); + msg_ps->state = SNMP_MSG_EMPTY; +} + +/** + * Service an internal or external event for SNMP GET. + * + * @param request_id identifies requests from 0 to (SNMP_CONCURRENT_REQUESTS-1) + * @param msg_ps points to the assosicated message process state + */ +static void +snmp_msg_get_event(u8_t request_id, struct snmp_msg_pstat *msg_ps) +{ + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_get_event: msg_ps->state==%"U16_F"\n",(u16_t)msg_ps->state)); + + if (msg_ps->state == SNMP_MSG_EXTERNAL_GET_OBJDEF) + { + struct mib_external_node *en; + struct snmp_name_ptr np; + + /* get_object_def() answer*/ + en = msg_ps->ext_mib_node; + np = msg_ps->ext_name_ptr; + + /* translate answer into a known lifeform */ + en->get_object_def_a(request_id, np.ident_len, np.ident, &msg_ps->ext_object_def); + if (msg_ps->ext_object_def.instance != MIB_OBJECT_NONE) + { + msg_ps->state = SNMP_MSG_EXTERNAL_GET_VALUE; + en->get_value_q(request_id, &msg_ps->ext_object_def); + } + else + { + en->get_object_def_pc(request_id, np.ident_len, np.ident); + /* search failed, object id points to unknown object (nosuchname) */ + snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME); + } + } + else if (msg_ps->state == SNMP_MSG_EXTERNAL_GET_VALUE) + { + struct mib_external_node *en; + struct snmp_varbind *vb; + + /* get_value() answer */ + en = msg_ps->ext_mib_node; + + /* allocate output varbind */ + vb = (struct snmp_varbind *)mem_malloc(sizeof(struct snmp_varbind)); + LWIP_ASSERT("vb != NULL",vb != NULL); + if (vb != NULL) + { + vb->next = NULL; + vb->prev = NULL; + + /* move name from invb to outvb */ + vb->ident = msg_ps->vb_ptr->ident; + vb->ident_len = msg_ps->vb_ptr->ident_len; + /* ensure this memory is refereced once only */ + msg_ps->vb_ptr->ident = NULL; + msg_ps->vb_ptr->ident_len = 0; + + vb->value_type = msg_ps->ext_object_def.asn_type; + vb->value_len = msg_ps->ext_object_def.v_len; + if (vb->value_len > 0) + { + vb->value = mem_malloc(vb->value_len); + LWIP_ASSERT("vb->value != NULL",vb->value != NULL); + if (vb->value != NULL) + { + en->get_value_a(request_id, &msg_ps->ext_object_def, vb->value_len, vb->value); + snmp_varbind_tail_add(&msg_ps->outvb, vb); + /* search again (if vb_idx < msg_ps->invb.count) */ + msg_ps->state = SNMP_MSG_SEARCH_OBJ; + msg_ps->vb_idx += 1; + } + else + { + en->get_value_pc(request_id, &msg_ps->ext_object_def); + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_event: no variable space\n")); + msg_ps->vb_ptr->ident = vb->ident; + msg_ps->vb_ptr->ident_len = vb->ident_len; + mem_free(vb); + snmp_error_response(msg_ps,SNMP_ES_TOOBIG); + } + } + else + { + /* vb->value_len == 0, empty value (e.g. empty string) */ + en->get_value_a(request_id, &msg_ps->ext_object_def, 0, NULL); + vb->value = NULL; + snmp_varbind_tail_add(&msg_ps->outvb, vb); + /* search again (if vb_idx < msg_ps->invb.count) */ + msg_ps->state = SNMP_MSG_SEARCH_OBJ; + msg_ps->vb_idx += 1; + } + } + else + { + en->get_value_pc(request_id, &msg_ps->ext_object_def); + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_event: no outvb space\n")); + snmp_error_response(msg_ps,SNMP_ES_TOOBIG); + } + } + + while ((msg_ps->state == SNMP_MSG_SEARCH_OBJ) && + (msg_ps->vb_idx < msg_ps->invb.count)) + { + struct mib_node *mn; + struct snmp_name_ptr np; + + if (msg_ps->vb_idx == 0) + { + msg_ps->vb_ptr = msg_ps->invb.head; + } + else + { + msg_ps->vb_ptr = msg_ps->vb_ptr->next; + } + /** test object identifier for .iso.org.dod.internet prefix */ + if (snmp_iso_prefix_tst(msg_ps->vb_ptr->ident_len, msg_ps->vb_ptr->ident)) + { + mn = snmp_search_tree((struct mib_node*)&internet, msg_ps->vb_ptr->ident_len - 4, + msg_ps->vb_ptr->ident + 4, &np); + } + else + { + mn = NULL; + } + if (mn != NULL) + { + if (mn->node_type == MIB_NODE_EX) + { + /* external object */ + struct mib_external_node *en = (struct mib_external_node*)mn; + + msg_ps->state = SNMP_MSG_EXTERNAL_GET_OBJDEF; + /* save en && args in msg_ps!! */ + msg_ps->ext_mib_node = en; + msg_ps->ext_name_ptr = np; + + en->get_object_def_q(en->addr_inf, request_id, np.ident_len, np.ident); + } + else + { + /* internal object */ + struct obj_def object_def; + + msg_ps->state = SNMP_MSG_INTERNAL_GET_OBJDEF; + mn->get_object_def(np.ident_len, np.ident, &object_def); + if (object_def.instance != MIB_OBJECT_NONE) + { + mn = mn; + } + else + { + /* search failed, object id points to unknown object (nosuchname) */ + mn = NULL; + } + if (mn != NULL) + { + struct snmp_varbind *vb; + + msg_ps->state = SNMP_MSG_INTERNAL_GET_VALUE; + /* allocate output varbind */ + vb = (struct snmp_varbind *)mem_malloc(sizeof(struct snmp_varbind)); + LWIP_ASSERT("vb != NULL",vb != NULL); + if (vb != NULL) + { + vb->next = NULL; + vb->prev = NULL; + + /* move name from invb to outvb */ + vb->ident = msg_ps->vb_ptr->ident; + vb->ident_len = msg_ps->vb_ptr->ident_len; + /* ensure this memory is refereced once only */ + msg_ps->vb_ptr->ident = NULL; + msg_ps->vb_ptr->ident_len = 0; + + vb->value_type = object_def.asn_type; + vb->value_len = object_def.v_len; + if (vb->value_len > 0) + { + vb->value = mem_malloc(vb->value_len); + LWIP_ASSERT("vb->value != NULL",vb->value != NULL); + if (vb->value != NULL) + { + mn->get_value(&object_def, vb->value_len, vb->value); + snmp_varbind_tail_add(&msg_ps->outvb, vb); + msg_ps->state = SNMP_MSG_SEARCH_OBJ; + msg_ps->vb_idx += 1; + } + else + { + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_event: couldn't allocate variable space\n")); + msg_ps->vb_ptr->ident = vb->ident; + msg_ps->vb_ptr->ident_len = vb->ident_len; + mem_free(vb); + snmp_error_response(msg_ps,SNMP_ES_TOOBIG); + } + } + else + { + /* vb->value_len == 0, empty value (e.g. empty string) */ + vb->value = NULL; + snmp_varbind_tail_add(&msg_ps->outvb, vb); + msg_ps->state = SNMP_MSG_SEARCH_OBJ; + msg_ps->vb_idx += 1; + } + } + else + { + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_event: couldn't allocate outvb space\n")); + snmp_error_response(msg_ps,SNMP_ES_TOOBIG); + } + } + } + } + if (mn == NULL) + { + /* mn == NULL, noSuchName */ + snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME); + } + } + if ((msg_ps->state == SNMP_MSG_SEARCH_OBJ) && + (msg_ps->vb_idx == msg_ps->invb.count)) + { + snmp_ok_response(msg_ps); + } +} + +/** + * Service an internal or external event for SNMP GETNEXT. + * + * @param request_id identifies requests from 0 to (SNMP_CONCURRENT_REQUESTS-1) + * @param msg_ps points to the assosicated message process state + */ +static void +snmp_msg_getnext_event(u8_t request_id, struct snmp_msg_pstat *msg_ps) +{ + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_getnext_event: msg_ps->state==%"U16_F"\n",(u16_t)msg_ps->state)); + + if (msg_ps->state == SNMP_MSG_EXTERNAL_GET_OBJDEF) + { + struct mib_external_node *en; + + /* get_object_def() answer*/ + en = msg_ps->ext_mib_node; + + /* translate answer into a known lifeform */ + en->get_object_def_a(request_id, 1, &msg_ps->ext_oid.id[msg_ps->ext_oid.len - 1], &msg_ps->ext_object_def); + if (msg_ps->ext_object_def.instance != MIB_OBJECT_NONE) + { + msg_ps->state = SNMP_MSG_EXTERNAL_GET_VALUE; + en->get_value_q(request_id, &msg_ps->ext_object_def); + } + else + { + en->get_object_def_pc(request_id, 1, &msg_ps->ext_oid.id[msg_ps->ext_oid.len - 1]); + /* search failed, object id points to unknown object (nosuchname) */ + snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME); + } + } + else if (msg_ps->state == SNMP_MSG_EXTERNAL_GET_VALUE) + { + struct mib_external_node *en; + struct snmp_varbind *vb; + + /* get_value() answer */ + en = msg_ps->ext_mib_node; + + vb = snmp_varbind_alloc(&msg_ps->ext_oid, + msg_ps->ext_object_def.asn_type, + msg_ps->ext_object_def.v_len); + if (vb != NULL) + { + en->get_value_a(request_id, &msg_ps->ext_object_def, vb->value_len, vb->value); + snmp_varbind_tail_add(&msg_ps->outvb, vb); + msg_ps->state = SNMP_MSG_SEARCH_OBJ; + msg_ps->vb_idx += 1; + } + else + { + en->get_value_pc(request_id, &msg_ps->ext_object_def); + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_getnext_event: couldn't allocate outvb space\n")); + snmp_error_response(msg_ps,SNMP_ES_TOOBIG); + } + } + + while ((msg_ps->state == SNMP_MSG_SEARCH_OBJ) && + (msg_ps->vb_idx < msg_ps->invb.count)) + { + struct mib_node *mn; + struct snmp_obj_id oid; + + if (msg_ps->vb_idx == 0) + { + msg_ps->vb_ptr = msg_ps->invb.head; + } + else + { + msg_ps->vb_ptr = msg_ps->vb_ptr->next; + } + if (snmp_iso_prefix_expand(msg_ps->vb_ptr->ident_len, msg_ps->vb_ptr->ident, &oid)) + { + if (msg_ps->vb_ptr->ident_len > 3) + { + /* can offset ident_len and ident */ + mn = snmp_expand_tree((struct mib_node*)&internet, + msg_ps->vb_ptr->ident_len - 4, + msg_ps->vb_ptr->ident + 4, &oid); + } + else + { + /* can't offset ident_len -4, ident + 4 */ + mn = snmp_expand_tree((struct mib_node*)&internet, 0, NULL, &oid); + } + } + else + { + mn = NULL; + } + if (mn != NULL) + { + if (mn->node_type == MIB_NODE_EX) + { + /* external object */ + struct mib_external_node *en = (struct mib_external_node*)mn; + + msg_ps->state = SNMP_MSG_EXTERNAL_GET_OBJDEF; + /* save en && args in msg_ps!! */ + msg_ps->ext_mib_node = en; + msg_ps->ext_oid = oid; + + en->get_object_def_q(en->addr_inf, request_id, 1, &oid.id[oid.len - 1]); + } + else + { + /* internal object */ + struct obj_def object_def; + struct snmp_varbind *vb; + + msg_ps->state = SNMP_MSG_INTERNAL_GET_OBJDEF; + mn->get_object_def(1, &oid.id[oid.len - 1], &object_def); + + vb = snmp_varbind_alloc(&oid, object_def.asn_type, object_def.v_len); + if (vb != NULL) + { + msg_ps->state = SNMP_MSG_INTERNAL_GET_VALUE; + mn->get_value(&object_def, object_def.v_len, vb->value); + snmp_varbind_tail_add(&msg_ps->outvb, vb); + msg_ps->state = SNMP_MSG_SEARCH_OBJ; + msg_ps->vb_idx += 1; + } + else + { + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_recv couldn't allocate outvb space\n")); + snmp_error_response(msg_ps,SNMP_ES_TOOBIG); + } + } + } + if (mn == NULL) + { + /* mn == NULL, noSuchName */ + snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME); + } + } + if ((msg_ps->state == SNMP_MSG_SEARCH_OBJ) && + (msg_ps->vb_idx == msg_ps->invb.count)) + { + snmp_ok_response(msg_ps); + } +} + +/** + * Service an internal or external event for SNMP SET. + * + * @param request_id identifies requests from 0 to (SNMP_CONCURRENT_REQUESTS-1) + * @param msg_ps points to the assosicated message process state + */ +static void +snmp_msg_set_event(u8_t request_id, struct snmp_msg_pstat *msg_ps) +{ + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_msg_set_event: msg_ps->state==%"U16_F"\n",(u16_t)msg_ps->state)); + + if (msg_ps->state == SNMP_MSG_EXTERNAL_GET_OBJDEF) + { + struct mib_external_node *en; + struct snmp_name_ptr np; + + /* get_object_def() answer*/ + en = msg_ps->ext_mib_node; + np = msg_ps->ext_name_ptr; + + /* translate answer into a known lifeform */ + en->get_object_def_a(request_id, np.ident_len, np.ident, &msg_ps->ext_object_def); + if (msg_ps->ext_object_def.instance != MIB_OBJECT_NONE) + { + msg_ps->state = SNMP_MSG_EXTERNAL_SET_TEST; + en->set_test_q(request_id, &msg_ps->ext_object_def); + } + else + { + en->get_object_def_pc(request_id, np.ident_len, np.ident); + /* search failed, object id points to unknown object (nosuchname) */ + snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME); + } + } + else if (msg_ps->state == SNMP_MSG_EXTERNAL_SET_TEST) + { + struct mib_external_node *en; + struct snmp_name_ptr np; + + /* set_test() answer*/ + en = msg_ps->ext_mib_node; + np = msg_ps->ext_name_ptr; + + if (msg_ps->ext_object_def.access == MIB_OBJECT_READ_WRITE) + { + if ((msg_ps->ext_object_def.asn_type == msg_ps->vb_ptr->value_type) && + (en->set_test_a(request_id,&msg_ps->ext_object_def, + msg_ps->vb_ptr->value_len,msg_ps->vb_ptr->value) != 0)) + { + msg_ps->state = SNMP_MSG_SEARCH_OBJ; + msg_ps->vb_idx += 1; + } + else + { + en->set_test_pc(request_id,&msg_ps->ext_object_def); + /* bad value */ + snmp_error_response(msg_ps,SNMP_ES_BADVALUE); + } + } + else + { + en->set_test_pc(request_id,&msg_ps->ext_object_def); + /* object not available for set */ + snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME); + } + } + else if (msg_ps->state == SNMP_MSG_EXTERNAL_GET_OBJDEF_S) + { + struct mib_external_node *en; + struct snmp_name_ptr np; + + /* get_object_def() answer*/ + en = msg_ps->ext_mib_node; + np = msg_ps->ext_name_ptr; + + /* translate answer into a known lifeform */ + en->get_object_def_a(request_id, np.ident_len, np.ident, &msg_ps->ext_object_def); + if (msg_ps->ext_object_def.instance != MIB_OBJECT_NONE) + { + msg_ps->state = SNMP_MSG_EXTERNAL_SET_VALUE; + en->set_value_q(request_id, &msg_ps->ext_object_def, + msg_ps->vb_ptr->value_len,msg_ps->vb_ptr->value); + } + else + { + en->get_object_def_pc(request_id, np.ident_len, np.ident); + /* set_value failed, object has disappeared for some odd reason?? */ + snmp_error_response(msg_ps,SNMP_ES_GENERROR); + } + } + else if (msg_ps->state == SNMP_MSG_EXTERNAL_SET_VALUE) + { + struct mib_external_node *en; + + /** set_value_a() @todo: use reply value?? */ + en = msg_ps->ext_mib_node; + en->set_value_a(request_id, &msg_ps->ext_object_def, 0, NULL); + + /** @todo use set_value_pc() if toobig */ + msg_ps->state = SNMP_MSG_INTERNAL_SET_VALUE; + msg_ps->vb_idx += 1; + } + + /* test all values before setting */ + while ((msg_ps->state == SNMP_MSG_SEARCH_OBJ) && + (msg_ps->vb_idx < msg_ps->invb.count)) + { + struct mib_node *mn; + struct snmp_name_ptr np; + + if (msg_ps->vb_idx == 0) + { + msg_ps->vb_ptr = msg_ps->invb.head; + } + else + { + msg_ps->vb_ptr = msg_ps->vb_ptr->next; + } + /** test object identifier for .iso.org.dod.internet prefix */ + if (snmp_iso_prefix_tst(msg_ps->vb_ptr->ident_len, msg_ps->vb_ptr->ident)) + { + mn = snmp_search_tree((struct mib_node*)&internet, msg_ps->vb_ptr->ident_len - 4, + msg_ps->vb_ptr->ident + 4, &np); + } + else + { + mn = NULL; + } + if (mn != NULL) + { + if (mn->node_type == MIB_NODE_EX) + { + /* external object */ + struct mib_external_node *en = (struct mib_external_node*)mn; + + msg_ps->state = SNMP_MSG_EXTERNAL_GET_OBJDEF; + /* save en && args in msg_ps!! */ + msg_ps->ext_mib_node = en; + msg_ps->ext_name_ptr = np; + + en->get_object_def_q(en->addr_inf, request_id, np.ident_len, np.ident); + } + else + { + /* internal object */ + struct obj_def object_def; + + msg_ps->state = SNMP_MSG_INTERNAL_GET_OBJDEF; + mn->get_object_def(np.ident_len, np.ident, &object_def); + if (object_def.instance != MIB_OBJECT_NONE) + { + mn = mn; + } + else + { + /* search failed, object id points to unknown object (nosuchname) */ + mn = NULL; + } + if (mn != NULL) + { + msg_ps->state = SNMP_MSG_INTERNAL_SET_TEST; + + if (object_def.access == MIB_OBJECT_READ_WRITE) + { + if ((object_def.asn_type == msg_ps->vb_ptr->value_type) && + (mn->set_test(&object_def,msg_ps->vb_ptr->value_len,msg_ps->vb_ptr->value) != 0)) + { + msg_ps->state = SNMP_MSG_SEARCH_OBJ; + msg_ps->vb_idx += 1; + } + else + { + /* bad value */ + snmp_error_response(msg_ps,SNMP_ES_BADVALUE); + } + } + else + { + /* object not available for set */ + snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME); + } + } + } + } + if (mn == NULL) + { + /* mn == NULL, noSuchName */ + snmp_error_response(msg_ps,SNMP_ES_NOSUCHNAME); + } + } + + if ((msg_ps->state == SNMP_MSG_SEARCH_OBJ) && + (msg_ps->vb_idx == msg_ps->invb.count)) + { + msg_ps->vb_idx = 0; + msg_ps->state = SNMP_MSG_INTERNAL_SET_VALUE; + } + + /* set all values "atomically" (be as "atomic" as possible) */ + while ((msg_ps->state == SNMP_MSG_INTERNAL_SET_VALUE) && + (msg_ps->vb_idx < msg_ps->invb.count)) + { + struct mib_node *mn; + struct snmp_name_ptr np; + + if (msg_ps->vb_idx == 0) + { + msg_ps->vb_ptr = msg_ps->invb.head; + } + else + { + msg_ps->vb_ptr = msg_ps->vb_ptr->next; + } + /* skip iso prefix test, was done previously while settesting() */ + mn = snmp_search_tree((struct mib_node*)&internet, msg_ps->vb_ptr->ident_len - 4, + msg_ps->vb_ptr->ident + 4, &np); + /* check if object is still available + (e.g. external hot-plug thingy present?) */ + if (mn != NULL) + { + if (mn->node_type == MIB_NODE_EX) + { + /* external object */ + struct mib_external_node *en = (struct mib_external_node*)mn; + + msg_ps->state = SNMP_MSG_EXTERNAL_GET_OBJDEF_S; + /* save en && args in msg_ps!! */ + msg_ps->ext_mib_node = en; + msg_ps->ext_name_ptr = np; + + en->get_object_def_q(en->addr_inf, request_id, np.ident_len, np.ident); + } + else + { + /* internal object */ + struct obj_def object_def; + + msg_ps->state = SNMP_MSG_INTERNAL_GET_OBJDEF_S; + mn->get_object_def(np.ident_len, np.ident, &object_def); + msg_ps->state = SNMP_MSG_INTERNAL_SET_VALUE; + mn->set_value(&object_def,msg_ps->vb_ptr->value_len,msg_ps->vb_ptr->value); + msg_ps->vb_idx += 1; + } + } + } + if ((msg_ps->state == SNMP_MSG_INTERNAL_SET_VALUE) && + (msg_ps->vb_idx == msg_ps->invb.count)) + { + /* simply echo the input if we can set it + @todo do we need to return the actual value? + e.g. if value is silently modified or behaves sticky? */ + msg_ps->outvb = msg_ps->invb; + msg_ps->invb.head = NULL; + msg_ps->invb.tail = NULL; + msg_ps->invb.count = 0; + snmp_ok_response(msg_ps); + } +} + + +/** + * Handle one internal or external event. + * Called for one async event. (recv external/private answer) + * + * @param request_id identifies requests from 0 to (SNMP_CONCURRENT_REQUESTS-1) + */ +void +snmp_msg_event(u8_t request_id) +{ + struct snmp_msg_pstat *msg_ps; + + if (request_id < SNMP_CONCURRENT_REQUESTS) + { + msg_ps = &msg_input_list[request_id]; + if (msg_ps->rt == SNMP_ASN1_PDU_GET_NEXT_REQ) + { + snmp_msg_getnext_event(request_id, msg_ps); + } + else if (msg_ps->rt == SNMP_ASN1_PDU_GET_REQ) + { + snmp_msg_get_event(request_id, msg_ps); + } + else if(msg_ps->rt == SNMP_ASN1_PDU_SET_REQ) + { + snmp_msg_set_event(request_id, msg_ps); + } + } +} + + +/* lwIP UDP receive callback function */ +static void +snmp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *addr, u16_t port) +{ + struct udp_hdr *udphdr; + + /* suppress unused argument warning */ + if (arg); + /* peek in the UDP header (goto IP payload) */ + pbuf_header(p, UDP_HLEN); + udphdr = p->payload; + + /* check if datagram is really directed at us (including broadcast requests) */ + if ((pcb == snmp1_pcb) && (ntohs(udphdr->dest) == 161)) + { + struct snmp_msg_pstat *msg_ps; + u8_t req_idx; + + /* traverse input message process list, look for SNMP_MSG_EMPTY */ + msg_ps = &msg_input_list[0]; + req_idx = 0; + while ((req_idxstate != SNMP_MSG_EMPTY)) + { + req_idx++; + msg_ps++; + } + if (req_idx != SNMP_CONCURRENT_REQUESTS) + { + err_t err_ret; + u16_t payload_len; + u16_t payload_ofs; + u16_t varbind_ofs = 0; + + /* accepting request */ + snmp_inc_snmpinpkts(); + /* record used 'protocol control block' */ + msg_ps->pcb = pcb; + /* source address (network order) */ + msg_ps->sip = *addr; + /* source port (host order (lwIP oddity)) */ + msg_ps->sp = port; + /* read UDP payload length from UDP header */ + payload_len = ntohs(udphdr->len) - UDP_HLEN; + + /* adjust to UDP payload */ + payload_ofs = UDP_HLEN; + + /* check total length, version, community, pdu type */ + err_ret = snmp_pdu_header_check(p, payload_ofs, payload_len, &varbind_ofs, msg_ps); + if (((msg_ps->rt == SNMP_ASN1_PDU_GET_REQ) || + (msg_ps->rt == SNMP_ASN1_PDU_GET_NEXT_REQ) || + (msg_ps->rt == SNMP_ASN1_PDU_SET_REQ)) && + ((msg_ps->error_status == SNMP_ES_NOERROR) && + (msg_ps->error_index == 0)) ) + { + /* Only accept requests and requests without error (be robust) */ + err_ret = err_ret; + } + else + { + /* Reject response and trap headers or error requests as input! */ + err_ret = ERR_ARG; + } + if (err_ret == ERR_OK) + { + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_recv ok, community %s\n", msg_ps->community)); + + /* Builds a list of variable bindings. Copy the varbinds from the pbuf + chain to glue them when these are divided over two or more pbuf's. */ + err_ret = snmp_pdu_dec_varbindlist(p, varbind_ofs, &varbind_ofs, msg_ps); + if ((err_ret == ERR_OK) && (msg_ps->invb.count > 0)) + { + /* we've decoded the incoming message, release input msg now */ + pbuf_free(p); + + msg_ps->error_status = SNMP_ES_NOERROR; + msg_ps->error_index = 0; + /* find object for each variable binding */ + msg_ps->state = SNMP_MSG_SEARCH_OBJ; + /* first variable binding from list to inspect */ + msg_ps->vb_idx = 0; + + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_recv varbind cnt=%"U16_F"\n",(u16_t)msg_ps->invb.count)); + + /* handle input event and as much objects as possible in one go */ + snmp_msg_event(req_idx); + } + else + { + /* varbind-list decode failed, or varbind list empty. + drop request silently, do not return error! + (errors are only returned for a specific varbind failure) */ + pbuf_free(p); + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_pdu_dec_varbindlist() failed\n")); + } + } + else + { + /* header check failed + drop request silently, do not return error! */ + pbuf_free(p); + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_pdu_header_check() failed\n")); + } + } + else + { + /* exceeding number of concurrent requests */ + pbuf_free(p); + } + } + else + { + /* datagram not for us */ + pbuf_free(p); + } +} + +/** + * Checks and decodes incoming SNMP message header, logs header errors. + * + * @param p points to pbuf chain of SNMP message (UDP payload) + * @param ofs points to first octet of SNMP message + * @param pdu_len the length of the UDP payload + * @param ofs_ret returns the ofset of the variable bindings + * @param m_stat points to the current message request state return + * @return + * - ERR_OK SNMP header is sane and accepted + * - ERR_ARG SNMP header is either malformed or rejected + */ +static err_t +snmp_pdu_header_check(struct pbuf *p, u16_t ofs, u16_t pdu_len, u16_t *ofs_ret, struct snmp_msg_pstat *m_stat) +{ + err_t derr; + u16_t len, ofs_base; + u8_t len_octets; + u8_t type; + s32_t version; + + ofs_base = ofs; + snmp_asn1_dec_type(p, ofs, &type); + derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len); + if ((derr != ERR_OK) || + (pdu_len != (1 + len_octets + len)) || + (type != (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ))) + { + snmp_inc_snmpinasnparseerrs(); + return ERR_ARG; + } + ofs += (1 + len_octets); + snmp_asn1_dec_type(p, ofs, &type); + derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len); + if ((derr != ERR_OK) || (type != (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG))) + { + /* can't decode or no integer (version) */ + snmp_inc_snmpinasnparseerrs(); + return ERR_ARG; + } + derr = snmp_asn1_dec_s32t(p, ofs + 1 + len_octets, len, &version); + if (derr != ERR_OK) + { + /* can't decode */ + snmp_inc_snmpinasnparseerrs(); + return ERR_ARG; + } + if (version != 0) + { + /* not version 1 */ + snmp_inc_snmpinbadversions(); + return ERR_ARG; + } + ofs += (1 + len_octets + len); + snmp_asn1_dec_type(p, ofs, &type); + derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len); + if ((derr != ERR_OK) || (type != (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR))) + { + /* can't decode or no octet string (community) */ + snmp_inc_snmpinasnparseerrs(); + return ERR_ARG; + } + derr = snmp_asn1_dec_raw(p, ofs + 1 + len_octets, len, SNMP_COMMUNITY_STR_LEN, m_stat->community); + if (derr != ERR_OK) + { + snmp_inc_snmpinasnparseerrs(); + return ERR_ARG; + } + /* add zero terminator */ + len = ((len < (SNMP_COMMUNITY_STR_LEN))?(len):(SNMP_COMMUNITY_STR_LEN)); + m_stat->community[len] = 0; + m_stat->com_strlen = len; + if (strncmp(snmp_publiccommunity, (const char*)m_stat->community, SNMP_COMMUNITY_STR_LEN) != 0) + { + /** @todo: move this if we need to check more names */ + snmp_inc_snmpinbadcommunitynames(); + snmp_authfail_trap(); + return ERR_ARG; + } + ofs += (1 + len_octets + len); + snmp_asn1_dec_type(p, ofs, &type); + derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len); + if (derr != ERR_OK) + { + snmp_inc_snmpinasnparseerrs(); + return ERR_ARG; + } + switch(type) + { + case (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_GET_REQ): + /* GetRequest PDU */ + snmp_inc_snmpingetrequests(); + derr = ERR_OK; + break; + case (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_GET_NEXT_REQ): + /* GetNextRequest PDU */ + snmp_inc_snmpingetnexts(); + derr = ERR_OK; + break; + case (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_GET_RESP): + /* GetResponse PDU */ + snmp_inc_snmpingetresponses(); + derr = ERR_ARG; + break; + case (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_SET_REQ): + /* SetRequest PDU */ + snmp_inc_snmpinsetrequests(); + derr = ERR_OK; + break; + case (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_TRAP): + /* Trap PDU */ + snmp_inc_snmpintraps(); + derr = ERR_ARG; + break; + default: + snmp_inc_snmpinasnparseerrs(); + derr = ERR_ARG; + break; + } + if (derr != ERR_OK) + { + /* unsupported input PDU for this agent (no parse error) */ + return ERR_ARG; + } + m_stat->rt = type & 0x1F; + ofs += (1 + len_octets); + if (len != (pdu_len - (ofs - ofs_base))) + { + /* decoded PDU length does not equal actual payload length */ + snmp_inc_snmpinasnparseerrs(); + return ERR_ARG; + } + snmp_asn1_dec_type(p, ofs, &type); + derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len); + if ((derr != ERR_OK) || (type != (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG))) + { + /* can't decode or no integer (request ID) */ + snmp_inc_snmpinasnparseerrs(); + return ERR_ARG; + } + derr = snmp_asn1_dec_s32t(p, ofs + 1 + len_octets, len, &m_stat->rid); + if (derr != ERR_OK) + { + /* can't decode */ + snmp_inc_snmpinasnparseerrs(); + return ERR_ARG; + } + ofs += (1 + len_octets + len); + snmp_asn1_dec_type(p, ofs, &type); + derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len); + if ((derr != ERR_OK) || (type != (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG))) + { + /* can't decode or no integer (error-status) */ + snmp_inc_snmpinasnparseerrs(); + return ERR_ARG; + } + /* must be noError (0) for incoming requests. + log errors for mib-2 completeness and for debug purposes */ + derr = snmp_asn1_dec_s32t(p, ofs + 1 + len_octets, len, &m_stat->error_status); + if (derr != ERR_OK) + { + /* can't decode */ + snmp_inc_snmpinasnparseerrs(); + return ERR_ARG; + } + switch (m_stat->error_status) + { + case SNMP_ES_TOOBIG: + snmp_inc_snmpintoobigs(); + break; + case SNMP_ES_NOSUCHNAME: + snmp_inc_snmpinnosuchnames(); + break; + case SNMP_ES_BADVALUE: + snmp_inc_snmpinbadvalues(); + break; + case SNMP_ES_READONLY: + snmp_inc_snmpinreadonlys(); + break; + case SNMP_ES_GENERROR: + snmp_inc_snmpingenerrs(); + break; + } + ofs += (1 + len_octets + len); + snmp_asn1_dec_type(p, ofs, &type); + derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len); + if ((derr != ERR_OK) || (type != (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG))) + { + /* can't decode or no integer (error-index) */ + snmp_inc_snmpinasnparseerrs(); + return ERR_ARG; + } + /* must be 0 for incoming requests. + decode anyway to catch bad integers (and dirty tricks) */ + derr = snmp_asn1_dec_s32t(p, ofs + 1 + len_octets, len, &m_stat->error_index); + if (derr != ERR_OK) + { + /* can't decode */ + snmp_inc_snmpinasnparseerrs(); + return ERR_ARG; + } + ofs += (1 + len_octets + len); + *ofs_ret = ofs; + return ERR_OK; +} + +static err_t +snmp_pdu_dec_varbindlist(struct pbuf *p, u16_t ofs, u16_t *ofs_ret, struct snmp_msg_pstat *m_stat) +{ + err_t derr; + u16_t len, vb_len; + u8_t len_octets; + u8_t type; + + /* variable binding list */ + snmp_asn1_dec_type(p, ofs, &type); + derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &vb_len); + if ((derr != ERR_OK) || + (type != (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ))) + { + snmp_inc_snmpinasnparseerrs(); + return ERR_ARG; + } + ofs += (1 + len_octets); + + /* start with empty list */ + m_stat->invb.count = 0; + m_stat->invb.head = NULL; + m_stat->invb.tail = NULL; + + while (vb_len > 0) + { + struct snmp_obj_id oid, oid_value; + struct snmp_varbind *vb; + + snmp_asn1_dec_type(p, ofs, &type); + derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len); + if ((derr != ERR_OK) || + (type != (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ)) || + (len <= 0) || (len > vb_len)) + { + snmp_inc_snmpinasnparseerrs(); + /* free varbinds (if available) */ + snmp_varbind_list_free(&m_stat->invb); + return ERR_ARG; + } + ofs += (1 + len_octets); + vb_len -= (1 + len_octets); + + snmp_asn1_dec_type(p, ofs, &type); + derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len); + if ((derr != ERR_OK) || (type != (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID))) + { + /* can't decode object name length */ + snmp_inc_snmpinasnparseerrs(); + /* free varbinds (if available) */ + snmp_varbind_list_free(&m_stat->invb); + return ERR_ARG; + } + derr = snmp_asn1_dec_oid(p, ofs + 1 + len_octets, len, &oid); + if (derr != ERR_OK) + { + /* can't decode object name */ + snmp_inc_snmpinasnparseerrs(); + /* free varbinds (if available) */ + snmp_varbind_list_free(&m_stat->invb); + return ERR_ARG; + } + ofs += (1 + len_octets + len); + vb_len -= (1 + len_octets + len); + + snmp_asn1_dec_type(p, ofs, &type); + derr = snmp_asn1_dec_length(p, ofs+1, &len_octets, &len); + if (derr != ERR_OK) + { + /* can't decode object value length */ + snmp_inc_snmpinasnparseerrs(); + /* free varbinds (if available) */ + snmp_varbind_list_free(&m_stat->invb); + return ERR_ARG; + } + + switch (type) + { + case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG): + vb = snmp_varbind_alloc(&oid, type, sizeof(s32_t)); + if (vb != NULL) + { + s32_t *vptr = vb->value; + + derr = snmp_asn1_dec_s32t(p, ofs + 1 + len_octets, len, vptr); + snmp_varbind_tail_add(&m_stat->invb, vb); + } + else + { + derr = ERR_ARG; + } + break; + case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER): + case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_GAUGE): + case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_TIMETICKS): + vb = snmp_varbind_alloc(&oid, type, sizeof(u32_t)); + if (vb != NULL) + { + u32_t *vptr = vb->value; + + derr = snmp_asn1_dec_u32t(p, ofs + 1 + len_octets, len, vptr); + snmp_varbind_tail_add(&m_stat->invb, vb); + } + else + { + derr = ERR_ARG; + } + break; + case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR): + case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_OPAQUE): + vb = snmp_varbind_alloc(&oid, type, len); + if (vb != NULL) + { + derr = snmp_asn1_dec_raw(p, ofs + 1 + len_octets, len, vb->value_len, vb->value); + snmp_varbind_tail_add(&m_stat->invb, vb); + } + else + { + derr = ERR_ARG; + } + break; + case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_NUL): + vb = snmp_varbind_alloc(&oid, type, 0); + if (vb != NULL) + { + snmp_varbind_tail_add(&m_stat->invb, vb); + derr = ERR_OK; + } + else + { + derr = ERR_ARG; + } + break; + case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID): + derr = snmp_asn1_dec_oid(p, ofs + 1 + len_octets, len, &oid_value); + if (derr == ERR_OK) + { + vb = snmp_varbind_alloc(&oid, type, oid_value.len * sizeof(s32_t)); + if (vb != NULL) + { + u8_t i = oid_value.len; + s32_t *vptr = vb->value; + + while(i > 0) + { + i--; + vptr[i] = oid_value.id[i]; + } + snmp_varbind_tail_add(&m_stat->invb, vb); + derr = ERR_OK; + } + else + { + derr = ERR_ARG; + } + } + break; + case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR): + if (len == 4) + { + /* must be exactly 4 octets! */ + vb = snmp_varbind_alloc(&oid, type, 4); + if (vb != NULL) + { + derr = snmp_asn1_dec_raw(p, ofs + 1 + len_octets, len, vb->value_len, vb->value); + snmp_varbind_tail_add(&m_stat->invb, vb); + } + else + { + derr = ERR_ARG; + } + } + else + { + derr = ERR_ARG; + } + break; + default: + derr = ERR_ARG; + break; + } + if (derr != ERR_OK) + { + snmp_inc_snmpinasnparseerrs(); + /* free varbinds (if available) */ + snmp_varbind_list_free(&m_stat->invb); + return ERR_ARG; + } + ofs += (1 + len_octets + len); + vb_len -= (1 + len_octets + len); + } + + if (m_stat->rt == SNMP_ASN1_PDU_SET_REQ) + { + snmp_add_snmpintotalsetvars(m_stat->invb.count); + } + else + { + snmp_add_snmpintotalreqvars(m_stat->invb.count); + } + + *ofs_ret = ofs; + return ERR_OK; +} + +struct snmp_varbind* +snmp_varbind_alloc(struct snmp_obj_id *oid, u8_t type, u8_t len) +{ + struct snmp_varbind *vb; + + vb = (struct snmp_varbind *)mem_malloc(sizeof(struct snmp_varbind)); + LWIP_ASSERT("vb != NULL",vb != NULL); + if (vb != NULL) + { + u8_t i; + + vb->next = NULL; + vb->prev = NULL; + i = oid->len; + vb->ident_len = i; + if (i > 0) + { + /* allocate array of s32_t for our object identifier */ + vb->ident = (s32_t*)mem_malloc(sizeof(s32_t) * i); + LWIP_ASSERT("vb->ident != NULL",vb->ident != NULL); + if (vb->ident == NULL) + { + mem_free(vb); + return NULL; + } + while(i > 0) + { + i--; + vb->ident[i] = oid->id[i]; + } + } + else + { + /* i == 0, pass zero length object identifier */ + vb->ident = NULL; + } + vb->value_type = type; + vb->value_len = len; + if (len > 0) + { + /* allocate raw bytes for our object value */ + vb->value = mem_malloc(len); + LWIP_ASSERT("vb->value != NULL",vb->value != NULL); + if (vb->value == NULL) + { + if (vb->ident != NULL) + { + mem_free(vb->ident); + } + mem_free(vb); + return NULL; + } + } + else + { + /* ASN1_NUL type, or zero length ASN1_OC_STR */ + vb->value = NULL; + } + } + return vb; +} + +void +snmp_varbind_free(struct snmp_varbind *vb) +{ + if (vb->value != NULL ) + { + mem_free(vb->value); + } + if (vb->ident != NULL ) + { + mem_free(vb->ident); + } + mem_free(vb); +} + +void +snmp_varbind_list_free(struct snmp_varbind_root *root) +{ + struct snmp_varbind *vb, *prev; + + vb = root->tail; + while ( vb != NULL ) + { + prev = vb->prev; + snmp_varbind_free(vb); + vb = prev; + } + root->count = 0; + root->head = NULL; + root->tail = NULL; +} + +void +snmp_varbind_tail_add(struct snmp_varbind_root *root, struct snmp_varbind *vb) +{ + if (root->count == 0) + { + /* add first varbind to list */ + root->head = vb; + root->tail = vb; + } + else + { + /* add nth varbind to list tail */ + root->tail->next = vb; + vb->prev = root->tail; + root->tail = vb; + } + root->count += 1; +} + +struct snmp_varbind* +snmp_varbind_tail_remove(struct snmp_varbind_root *root) +{ + struct snmp_varbind* vb; + + if (root->count > 0) + { + /* remove tail varbind */ + vb = root->tail; + root->tail = vb->prev; + vb->prev->next = NULL; + root->count -= 1; + } + else + { + /* nothing to remove */ + vb = NULL; + } + return vb; +} + +#endif /* LWIP_SNMP */ diff --git a/20080212/Demo/Common/ethernet/lwIP/core/snmp/msg_out.c b/20080212/Demo/Common/ethernet/lwIP/core/snmp/msg_out.c new file mode 100644 index 000000000..0da70de4a --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/core/snmp/msg_out.c @@ -0,0 +1,687 @@ +/** + * @file + * SNMP output message processing (RFC1157). + * + * Output responses and traps are build in two passes: + * + * Pass 0: iterate over the output message backwards to determine encoding lengths + * Pass 1: the actual forward encoding of internal form into ASN1 + * + * The single-pass encoding method described by Comer & Stevens + * requires extra buffer space and copying for reversal of the packet. + * The buffer requirement can be prohibitively large for big payloads + * (>= 484) therefore we use the two encoding passes. + */ + +/* + * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Christiaan Simons + */ + +#include "lwip/opt.h" + +#if LWIP_SNMP +#include "arch/cc.h" +#include "lwip/udp.h" +#include "lwip/netif.h" + +#include "lwip/snmp.h" +#include "lwip/snmp_asn1.h" +#include "lwip/snmp_msg.h" + +struct snmp_trap_dst +{ + /* destination IP address in network order */ + struct ip_addr dip; + /* set to 0 when disabled, >0 when enabled */ + u8_t enable; +}; +#if (SNMP_TRAP_DESTINATIONS == 0) +#error "need at least one trap destination" +#endif +struct snmp_trap_dst trap_dst[SNMP_TRAP_DESTINATIONS]; + +/** TRAP message structure */ +struct snmp_msg_trap trap_msg; + +static u16_t snmp_resp_header_sum(struct snmp_msg_pstat *m_stat, u16_t vb_len); +static u16_t snmp_trap_header_sum(struct snmp_msg_trap *m_trap, u16_t vb_len); +static u16_t snmp_varbind_list_sum(struct snmp_varbind_root *root); + +static u16_t snmp_resp_header_enc(struct snmp_msg_pstat *m_stat, struct pbuf *p); +static u16_t snmp_trap_header_enc(struct snmp_msg_trap *m_trap, struct pbuf *p); +static u16_t snmp_varbind_list_enc(struct snmp_varbind_root *root, struct pbuf *p, u16_t ofs); + +/** + * Sets enable switch for this trap destination. + * @param dst_idx index in 0 .. SNMP_TRAP_DESTINATIONS-1 + * @param enable switch if 0 destination is disabled >0 enabled. + */ +void +snmp_trap_dst_enable(u8_t dst_idx, u8_t enable) +{ + if (dst_idx < SNMP_TRAP_DESTINATIONS) + { + trap_dst[dst_idx].enable = enable; + } +} + +/** + * Sets IPv4 address for this trap destination. + * @param dst_idx index in 0 .. SNMP_TRAP_DESTINATIONS-1 + * @param dst IPv4 address in host order. + */ +void +snmp_trap_dst_ip_set(u8_t dst_idx, struct ip_addr *dst) +{ + if (dst_idx < SNMP_TRAP_DESTINATIONS) + { + trap_dst[dst_idx].dip.addr = htonl(dst->addr); + } +} + +/** + * Sends a 'getresponse' message to the request originator. + * + * @param m_stat points to the current message request state source + * @return ERR_OK when success, ERR_MEM if we're out of memory + * + * @note the caller is responsible for filling in outvb in the m_stat + * and provide error-status and index (except for tooBig errors) ... + */ +err_t +snmp_send_response(struct snmp_msg_pstat *m_stat) +{ + struct snmp_varbind_root emptyvb = {NULL, NULL, 0, 0, 0}; + struct pbuf *p; + u16_t tot_len; + err_t err; + + /* pass 0, calculate length fields */ + tot_len = snmp_varbind_list_sum(&m_stat->outvb); + tot_len = snmp_resp_header_sum(m_stat, tot_len); + + /* try allocating pbuf(s) for complete response */ + p = pbuf_alloc(PBUF_TRANSPORT, tot_len, PBUF_POOL); + if (p == NULL) + { + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_snd_response() tooBig\n")); + + /* can't construct reply, return error-status tooBig */ + m_stat->error_status = SNMP_ES_TOOBIG; + m_stat->error_index = 0; + /* pass 0, recalculate lengths, for empty varbind-list */ + tot_len = snmp_varbind_list_sum(&emptyvb); + tot_len = snmp_resp_header_sum(m_stat, tot_len); + /* retry allocation once for header and empty varbind-list */ + p = pbuf_alloc(PBUF_TRANSPORT, tot_len, PBUF_POOL); + } + if (p != NULL) + { + /* first pbuf alloc try or retry alloc success */ + u16_t ofs; + + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_snd_response() p != NULL\n")); + + /* pass 1, size error, encode packet ino the pbuf(s) */ + ofs = snmp_resp_header_enc(m_stat, p); + if (m_stat->error_status == SNMP_ES_TOOBIG) + { + snmp_varbind_list_enc(&emptyvb, p, ofs); + } + else + { + snmp_varbind_list_enc(&m_stat->outvb, p, ofs); + } + + switch (m_stat->error_status) + { + case SNMP_ES_TOOBIG: + snmp_inc_snmpouttoobigs(); + break; + case SNMP_ES_NOSUCHNAME: + snmp_inc_snmpoutnosuchnames(); + break; + case SNMP_ES_BADVALUE: + snmp_inc_snmpoutbadvalues(); + break; + case SNMP_ES_GENERROR: + snmp_inc_snmpoutgenerrs(); + break; + } + snmp_inc_snmpoutgetresponses(); + snmp_inc_snmpoutpkts(); + + /** @todo do we need separate rx and tx pcbs for threaded case? */ + /** connect to the originating source */ + udp_connect(m_stat->pcb, &m_stat->sip, m_stat->sp); + err = udp_send(m_stat->pcb, p); + if (err == ERR_MEM) + { + /** @todo release some memory, retry and return tooBig? tooMuchHassle? */ + err = ERR_MEM; + } + else + { + err = ERR_OK; + } + /** disassociate remote address and port with this pcb */ + udp_disconnect(m_stat->pcb); + + pbuf_free(p); + LWIP_DEBUGF(SNMP_MSG_DEBUG, ("snmp_snd_response() done\n")); + return err; + } + else + { + /* first pbuf alloc try or retry alloc failed + very low on memory, couldn't return tooBig */ + return ERR_MEM; + } +} + + +/** + * Sends an generic or enterprise specific trap message. + * + * @param generic_trap is the trap code + * @param eoid points to enterprise object identifier + * @param specific_trap used for enterprise traps when generic_trap == 6 + * @return ERR_OK when success, ERR_MEM if we're out of memory + * + * @note the caller is responsible for filling in outvb in the trap_msg + * @note the use of the enterpise identifier field + * is per RFC1215. + * Use .iso.org.dod.internet.mgmt.mib-2.snmp for generic traps + * and .iso.org.dod.internet.private.enterprises.yourenterprise + * (sysObjectID) for specific traps. + */ +err_t +snmp_send_trap(s8_t generic_trap, struct snmp_obj_id *eoid, s32_t specific_trap) +{ + struct snmp_trap_dst *td; + struct netif *dst_if; + struct ip_addr dst_ip; + struct pbuf *p; + u16_t i,tot_len; + + for (i=0, td = &trap_dst[0]; ienable != 0) && (td->dip.addr != 0)) + { + /* network order trap destination */ + trap_msg.dip.addr = td->dip.addr; + /* lookup current source address for this dst */ + dst_if = ip_route(&td->dip); + dst_ip.addr = ntohl(dst_if->ip_addr.addr); + trap_msg.sip_raw[0] = dst_ip.addr >> 24; + trap_msg.sip_raw[1] = dst_ip.addr >> 16; + trap_msg.sip_raw[2] = dst_ip.addr >> 8; + trap_msg.sip_raw[3] = dst_ip.addr; + trap_msg.gen_trap = generic_trap; + trap_msg.spc_trap = specific_trap; + if (generic_trap == SNMP_GENTRAP_ENTERPRISESPC) + { + /* enterprise-Specific trap */ + trap_msg.enterprise = eoid; + } + else + { + /* generic (MIB-II) trap */ + snmp_get_snmpgrpid_ptr(&trap_msg.enterprise); + } + snmp_get_sysuptime(&trap_msg.ts); + + /* pass 0, calculate length fields */ + tot_len = snmp_varbind_list_sum(&trap_msg.outvb); + tot_len = snmp_trap_header_sum(&trap_msg, tot_len); + + /* allocate pbuf(s) */ + p = pbuf_alloc(PBUF_TRANSPORT, tot_len, PBUF_POOL); + if (p != NULL) + { + u16_t ofs; + + /* pass 1, encode packet ino the pbuf(s) */ + ofs = snmp_trap_header_enc(&trap_msg, p); + snmp_varbind_list_enc(&trap_msg.outvb, p, ofs); + + snmp_inc_snmpouttraps(); + snmp_inc_snmpoutpkts(); + + /** connect to the TRAP destination */ + udp_connect(trap_msg.pcb, &trap_msg.dip, SNMP_TRAP_PORT); + udp_send(trap_msg.pcb, p); + /** disassociate remote address and port with this pcb */ + udp_disconnect(trap_msg.pcb); + + pbuf_free(p); + } + else + { + return ERR_MEM; + } + } + } + return ERR_OK; +} + +void +snmp_coldstart_trap(void) +{ + trap_msg.outvb.head = NULL; + trap_msg.outvb.tail = NULL; + trap_msg.outvb.count = 0; + snmp_send_trap(SNMP_GENTRAP_COLDSTART, NULL, 0); +} + +void +snmp_authfail_trap(void) +{ + u8_t enable; + snmp_get_snmpenableauthentraps(&enable); + if (enable == 1) + { + trap_msg.outvb.head = NULL; + trap_msg.outvb.tail = NULL; + trap_msg.outvb.count = 0; + snmp_send_trap(SNMP_GENTRAP_AUTHFAIL, NULL, 0); + } +} + +/** + * Sums response header field lengths from tail to head and + * returns resp_header_lengths for second encoding pass. + * + * @param vb_len varbind-list length + * @param rhl points to returned header lengths + * @return the required lenght for encoding the response header + */ +static u16_t +snmp_resp_header_sum(struct snmp_msg_pstat *m_stat, u16_t vb_len) +{ + u16_t tot_len; + struct snmp_resp_header_lengths *rhl; + + rhl = &m_stat->rhl; + tot_len = vb_len; + snmp_asn1_enc_s32t_cnt(m_stat->error_index, &rhl->erridxlen); + snmp_asn1_enc_length_cnt(rhl->erridxlen, &rhl->erridxlenlen); + tot_len += 1 + rhl->erridxlenlen + rhl->erridxlen; + + snmp_asn1_enc_s32t_cnt(m_stat->error_status, &rhl->errstatlen); + snmp_asn1_enc_length_cnt(rhl->errstatlen, &rhl->errstatlenlen); + tot_len += 1 + rhl->errstatlenlen + rhl->errstatlen; + + snmp_asn1_enc_s32t_cnt(m_stat->rid, &rhl->ridlen); + snmp_asn1_enc_length_cnt(rhl->ridlen, &rhl->ridlenlen); + tot_len += 1 + rhl->ridlenlen + rhl->ridlen; + + rhl->pdulen = tot_len; + snmp_asn1_enc_length_cnt(rhl->pdulen, &rhl->pdulenlen); + tot_len += 1 + rhl->pdulenlen; + + rhl->comlen = m_stat->com_strlen; + snmp_asn1_enc_length_cnt(rhl->comlen, &rhl->comlenlen); + tot_len += 1 + rhl->comlenlen + rhl->comlen; + + snmp_asn1_enc_s32t_cnt(snmp_version, &rhl->verlen); + snmp_asn1_enc_length_cnt(rhl->verlen, &rhl->verlenlen); + tot_len += 1 + rhl->verlen + rhl->verlenlen; + + rhl->seqlen = tot_len; + snmp_asn1_enc_length_cnt(rhl->seqlen, &rhl->seqlenlen); + tot_len += 1 + rhl->seqlenlen; + + return tot_len; +} + +/** + * Sums trap header field lengths from tail to head and + * returns trap_header_lengths for second encoding pass. + * + * @param vb_len varbind-list length + * @param thl points to returned header lengths + * @return the required lenght for encoding the trap header + */ +static u16_t +snmp_trap_header_sum(struct snmp_msg_trap *m_trap, u16_t vb_len) +{ + u16_t tot_len; + struct snmp_trap_header_lengths *thl; + + thl = &m_trap->thl; + tot_len = vb_len; + + snmp_asn1_enc_u32t_cnt(m_trap->ts, &thl->tslen); + snmp_asn1_enc_length_cnt(thl->tslen, &thl->tslenlen); + tot_len += 1 + thl->tslen + thl->tslenlen; + + snmp_asn1_enc_s32t_cnt(m_trap->spc_trap, &thl->strplen); + snmp_asn1_enc_length_cnt(thl->strplen, &thl->strplenlen); + tot_len += 1 + thl->strplen + thl->strplenlen; + + snmp_asn1_enc_s32t_cnt(m_trap->gen_trap, &thl->gtrplen); + snmp_asn1_enc_length_cnt(thl->gtrplen, &thl->gtrplenlen); + tot_len += 1 + thl->gtrplen + thl->gtrplenlen; + + thl->aaddrlen = 4; + snmp_asn1_enc_length_cnt(thl->aaddrlen, &thl->aaddrlenlen); + tot_len += 1 + thl->aaddrlen + thl->aaddrlenlen; + + snmp_asn1_enc_oid_cnt(m_trap->enterprise->len, &m_trap->enterprise->id[0], &thl->eidlen); + snmp_asn1_enc_length_cnt(thl->eidlen, &thl->eidlenlen); + tot_len += 1 + thl->eidlen + thl->eidlenlen; + + thl->pdulen = tot_len; + snmp_asn1_enc_length_cnt(thl->pdulen, &thl->pdulenlen); + tot_len += 1 + thl->pdulenlen; + + thl->comlen = sizeof(snmp_publiccommunity) - 1; + snmp_asn1_enc_length_cnt(thl->comlen, &thl->comlenlen); + tot_len += 1 + thl->comlenlen + thl->comlen; + + snmp_asn1_enc_s32t_cnt(snmp_version, &thl->verlen); + snmp_asn1_enc_length_cnt(thl->verlen, &thl->verlenlen); + tot_len += 1 + thl->verlen + thl->verlenlen; + + thl->seqlen = tot_len; + snmp_asn1_enc_length_cnt(thl->seqlen, &thl->seqlenlen); + tot_len += 1 + thl->seqlenlen; + + return tot_len; +} + +/** + * Sums varbind lengths from tail to head and + * annotates lengths in varbind for second encoding pass. + * + * @param root points to the root of the variable binding list + * @return the required lenght for encoding the variable bindings + */ +static u16_t +snmp_varbind_list_sum(struct snmp_varbind_root *root) +{ + struct snmp_varbind *vb; + u32_t *uint_ptr; + s32_t *sint_ptr; + u16_t tot_len; + + tot_len = 0; + vb = root->tail; + while ( vb != NULL ) + { + /* encoded value lenght depends on type */ + switch (vb->value_type) + { + case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG): + sint_ptr = vb->value; + snmp_asn1_enc_s32t_cnt(*sint_ptr, &vb->vlen); + break; + case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER): + case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_GAUGE): + case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_TIMETICKS): + uint_ptr = vb->value; + snmp_asn1_enc_u32t_cnt(*uint_ptr, &vb->vlen); + break; + case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR): + case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_NUL): + case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR): + case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_OPAQUE): + vb->vlen = vb->value_len; + break; + case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID): + sint_ptr = vb->value; + snmp_asn1_enc_oid_cnt(vb->value_len / sizeof(s32_t), sint_ptr, &vb->vlen); + break; + default: + /* unsupported type */ + vb->vlen = 0; + break; + }; + /* encoding length of value length field */ + snmp_asn1_enc_length_cnt(vb->vlen, &vb->vlenlen); + snmp_asn1_enc_oid_cnt(vb->ident_len, vb->ident, &vb->olen); + snmp_asn1_enc_length_cnt(vb->olen, &vb->olenlen); + + vb->seqlen = 1 + vb->vlenlen + vb->vlen; + vb->seqlen += 1 + vb->olenlen + vb->olen; + snmp_asn1_enc_length_cnt(vb->seqlen, &vb->seqlenlen); + + /* varbind seq */ + tot_len += 1 + vb->seqlenlen + vb->seqlen; + + vb = vb->prev; + } + + /* varbind-list seq */ + root->seqlen = tot_len; + snmp_asn1_enc_length_cnt(root->seqlen, &root->seqlenlen); + tot_len += 1 + root->seqlenlen; + + return tot_len; +} + +/** + * Encodes response header from head to tail. + */ +static u16_t +snmp_resp_header_enc(struct snmp_msg_pstat *m_stat, struct pbuf *p) +{ + u16_t ofs; + + ofs = 0; + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, m_stat->rhl.seqlen); + ofs += m_stat->rhl.seqlenlen; + + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, m_stat->rhl.verlen); + ofs += m_stat->rhl.verlenlen; + snmp_asn1_enc_s32t(p, ofs, m_stat->rhl.verlen, snmp_version); + ofs += m_stat->rhl.verlen; + + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, m_stat->rhl.comlen); + ofs += m_stat->rhl.comlenlen; + snmp_asn1_enc_raw(p, ofs, m_stat->rhl.comlen, m_stat->community); + ofs += m_stat->rhl.comlen; + + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_GET_RESP)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, m_stat->rhl.pdulen); + ofs += m_stat->rhl.pdulenlen; + + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, m_stat->rhl.ridlen); + ofs += m_stat->rhl.ridlenlen; + snmp_asn1_enc_s32t(p, ofs, m_stat->rhl.ridlen, m_stat->rid); + ofs += m_stat->rhl.ridlen; + + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, m_stat->rhl.errstatlen); + ofs += m_stat->rhl.errstatlenlen; + snmp_asn1_enc_s32t(p, ofs, m_stat->rhl.errstatlen, m_stat->error_status); + ofs += m_stat->rhl.errstatlen; + + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, m_stat->rhl.erridxlen); + ofs += m_stat->rhl.erridxlenlen; + snmp_asn1_enc_s32t(p, ofs, m_stat->rhl.erridxlen, m_stat->error_index); + ofs += m_stat->rhl.erridxlen; + + return ofs; +} + +/** + * Encodes trap header from head to tail. + */ +static u16_t +snmp_trap_header_enc(struct snmp_msg_trap *m_trap, struct pbuf *p) +{ + u16_t ofs; + + ofs = 0; + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, m_trap->thl.seqlen); + ofs += m_trap->thl.seqlenlen; + + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, m_trap->thl.verlen); + ofs += m_trap->thl.verlenlen; + snmp_asn1_enc_s32t(p, ofs, m_trap->thl.verlen, snmp_version); + ofs += m_trap->thl.verlen; + + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, m_trap->thl.comlen); + ofs += m_trap->thl.comlenlen; + snmp_asn1_enc_raw(p, ofs, m_trap->thl.comlen, (u8_t *)&snmp_publiccommunity[0]); + ofs += m_trap->thl.comlen; + + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_CONTXT | SNMP_ASN1_CONSTR | SNMP_ASN1_PDU_TRAP)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, m_trap->thl.pdulen); + ofs += m_trap->thl.pdulenlen; + + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, m_trap->thl.eidlen); + ofs += m_trap->thl.eidlenlen; + snmp_asn1_enc_oid(p, ofs, m_trap->enterprise->len, &m_trap->enterprise->id[0]); + ofs += m_trap->thl.eidlen; + + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, m_trap->thl.aaddrlen); + ofs += m_trap->thl.aaddrlenlen; + snmp_asn1_enc_raw(p, ofs, m_trap->thl.aaddrlen, &m_trap->sip_raw[0]); + ofs += m_trap->thl.aaddrlen; + + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, m_trap->thl.gtrplen); + ofs += m_trap->thl.gtrplenlen; + snmp_asn1_enc_u32t(p, ofs, m_trap->thl.gtrplen, m_trap->gen_trap); + ofs += m_trap->thl.gtrplen; + + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, m_trap->thl.strplen); + ofs += m_trap->thl.strplenlen; + snmp_asn1_enc_u32t(p, ofs, m_trap->thl.strplen, m_trap->spc_trap); + ofs += m_trap->thl.strplen; + + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_TIMETICKS)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, m_trap->thl.tslen); + ofs += m_trap->thl.tslenlen; + snmp_asn1_enc_u32t(p, ofs, m_trap->thl.tslen, m_trap->ts); + ofs += m_trap->thl.tslen; + + return ofs; +} + +/** + * Encodes varbind list from head to tail. + */ +static u16_t +snmp_varbind_list_enc(struct snmp_varbind_root *root, struct pbuf *p, u16_t ofs) +{ + struct snmp_varbind *vb; + s32_t *sint_ptr; + u32_t *uint_ptr; + u8_t *raw_ptr; + + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, root->seqlen); + ofs += root->seqlenlen; + + vb = root->head; + while ( vb != NULL ) + { + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_CONSTR | SNMP_ASN1_SEQ)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, vb->seqlen); + ofs += vb->seqlenlen; + + snmp_asn1_enc_type(p, ofs, (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID)); + ofs += 1; + snmp_asn1_enc_length(p, ofs, vb->olen); + ofs += vb->olenlen; + snmp_asn1_enc_oid(p, ofs, vb->ident_len, &vb->ident[0]); + ofs += vb->olen; + + snmp_asn1_enc_type(p, ofs, vb->value_type); + ofs += 1; + snmp_asn1_enc_length(p, ofs, vb->vlen); + ofs += vb->vlenlen; + + switch (vb->value_type) + { + case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_INTEG): + sint_ptr = vb->value; + snmp_asn1_enc_s32t(p, ofs, vb->vlen, *sint_ptr); + break; + case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_COUNTER): + case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_GAUGE): + case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_TIMETICKS): + uint_ptr = vb->value; + snmp_asn1_enc_u32t(p, ofs, vb->vlen, *uint_ptr); + break; + case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OC_STR): + case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_IPADDR): + case (SNMP_ASN1_APPLIC | SNMP_ASN1_PRIMIT | SNMP_ASN1_OPAQUE): + raw_ptr = vb->value; + snmp_asn1_enc_raw(p, ofs, vb->vlen, raw_ptr); + break; + case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_NUL): + break; + case (SNMP_ASN1_UNIV | SNMP_ASN1_PRIMIT | SNMP_ASN1_OBJ_ID): + sint_ptr = vb->value; + snmp_asn1_enc_oid(p, ofs, vb->value_len / sizeof(s32_t), sint_ptr); + break; + default: + /* unsupported type */ + break; + }; + ofs += vb->vlen; + vb = vb->next; + } + return ofs; +} + +#endif /* LWIP_SNMP */ diff --git a/20080212/Demo/Common/ethernet/lwIP/core/stats.c b/20080212/Demo/Common/ethernet/lwIP/core/stats.c new file mode 100644 index 000000000..e3cf4a3b5 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/core/stats.c @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include + +#include "lwip/opt.h" + +#include "lwip/def.h" + +#include "lwip/stats.h" +#include "lwip/mem.h" + + +#if LWIP_STATS +struct stats_ lwip_stats; + +void +stats_init(void) +{ + memset(&lwip_stats, 0, sizeof(struct stats_)); +} +#if LWIP_STATS_DISPLAY +void +stats_display_proto(struct stats_proto *proto, char *name) +{ + LWIP_PLATFORM_DIAG(("\n%s\n\t", name)); + LWIP_PLATFORM_DIAG(("xmit: %"S16_F"\n\t", proto->xmit)); + LWIP_PLATFORM_DIAG(("rexmit: %"S16_F"\n\t", proto->rexmit)); + LWIP_PLATFORM_DIAG(("recv: %"S16_F"\n\t", proto->recv)); + LWIP_PLATFORM_DIAG(("fw: %"S16_F"\n\t", proto->fw)); + LWIP_PLATFORM_DIAG(("drop: %"S16_F"\n\t", proto->drop)); + LWIP_PLATFORM_DIAG(("chkerr: %"S16_F"\n\t", proto->chkerr)); + LWIP_PLATFORM_DIAG(("lenerr: %"S16_F"\n\t", proto->lenerr)); + LWIP_PLATFORM_DIAG(("memerr: %"S16_F"\n\t", proto->memerr)); + LWIP_PLATFORM_DIAG(("rterr: %"S16_F"\n\t", proto->rterr)); + LWIP_PLATFORM_DIAG(("proterr: %"S16_F"\n\t", proto->proterr)); + LWIP_PLATFORM_DIAG(("opterr: %"S16_F"\n\t", proto->opterr)); + LWIP_PLATFORM_DIAG(("err: %"S16_F"\n\t", proto->err)); + LWIP_PLATFORM_DIAG(("cachehit: %"S16_F"\n", proto->cachehit)); +} + +void +stats_display_pbuf(struct stats_pbuf *pbuf) +{ + LWIP_PLATFORM_DIAG(("\nPBUF\n\t")); + LWIP_PLATFORM_DIAG(("avail: %"S16_F"\n\t", pbuf->avail)); + LWIP_PLATFORM_DIAG(("used: %"S16_F"\n\t", pbuf->used)); + LWIP_PLATFORM_DIAG(("max: %"S16_F"\n\t", pbuf->max)); + LWIP_PLATFORM_DIAG(("err: %"S16_F"\n\t", pbuf->err)); + LWIP_PLATFORM_DIAG(("alloc_locked: %"S16_F"\n\t", pbuf->alloc_locked)); + LWIP_PLATFORM_DIAG(("refresh_locked: %"S16_F"\n", pbuf->refresh_locked)); +} + +void +stats_display_mem(struct stats_mem *mem, char *name) +{ + LWIP_PLATFORM_DIAG(("\n MEM %s\n\t", name)); + LWIP_PLATFORM_DIAG(("avail: %"MEM_SIZE_F"\n\t", mem->avail)); + LWIP_PLATFORM_DIAG(("used: %"MEM_SIZE_F"\n\t", mem->used)); + LWIP_PLATFORM_DIAG(("max: %"MEM_SIZE_F"\n\t", mem->max)); + LWIP_PLATFORM_DIAG(("err: %"MEM_SIZE_F"\n", mem->err)); + +} + +void +stats_display(void) +{ + s16_t i; + char * memp_names[] = {"PBUF", "RAW_PCB", "UDP_PCB", "TCP_PCB", "TCP_PCB_LISTEN", + "TCP_SEG", "NETBUF", "NETCONN", "API_MSG", "TCP_MSG", "TIMEOUT"}; + stats_display_proto(&lwip_stats.link, "LINK"); + stats_display_proto(&lwip_stats.ip_frag, "IP_FRAG"); + stats_display_proto(&lwip_stats.ip, "IP"); + stats_display_proto(&lwip_stats.icmp, "ICMP"); + stats_display_proto(&lwip_stats.udp, "UDP"); + stats_display_proto(&lwip_stats.tcp, "TCP"); + stats_display_pbuf(&lwip_stats.pbuf); + stats_display_mem(&lwip_stats.mem, "HEAP"); + for (i = 0; i < MEMP_MAX; i++) { + stats_display_mem(&lwip_stats.memp[i], memp_names[i]); + } + +} +#endif /* LWIP_STATS_DISPLAY */ +#endif /* LWIP_STATS */ + diff --git a/20080212/Demo/Common/ethernet/lwIP/core/sys.c b/20080212/Demo/Common/ethernet/lwIP/core/sys.c new file mode 100644 index 000000000..2ecb880a1 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/core/sys.c @@ -0,0 +1,294 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/sys.h" +#include "lwip/opt.h" +#include "lwip/def.h" +#include "lwip/memp.h" + +#if (NO_SYS == 0) + +struct sswt_cb +{ + s16_t timeflag; + sys_sem_t *psem; +}; + + + +void +sys_mbox_fetch(sys_mbox_t mbox, void **msg) +{ + u32_t time; + struct sys_timeouts *timeouts; + struct sys_timeo *tmptimeout; + sys_timeout_handler h; + void *arg; + + + again: + timeouts = sys_arch_timeouts(); + + if (!timeouts || !timeouts->next) { + sys_arch_mbox_fetch(mbox, msg, 0); + } else { + if (timeouts->next->time > 0) { + time = sys_arch_mbox_fetch(mbox, msg, timeouts->next->time); + } else { + time = SYS_ARCH_TIMEOUT; + } + + if (time == SYS_ARCH_TIMEOUT) { + /* If time == SYS_ARCH_TIMEOUT, a timeout occured before a message + could be fetched. We should now call the timeout handler and + deallocate the memory allocated for the timeout. */ + tmptimeout = timeouts->next; + timeouts->next = tmptimeout->next; + h = tmptimeout->h; + arg = tmptimeout->arg; + memp_free(MEMP_SYS_TIMEOUT, tmptimeout); + if (h != NULL) { + LWIP_DEBUGF(SYS_DEBUG, ("smf calling h=%p(%p)\n", (void *)h, (void *)arg)); + h(arg); + } + + /* We try again to fetch a message from the mbox. */ + goto again; + } else { + /* If time != SYS_ARCH_TIMEOUT, a message was received before the timeout + occured. The time variable is set to the number of + milliseconds we waited for the message. */ + if (time <= timeouts->next->time) { + timeouts->next->time -= time; + } else { + timeouts->next->time = 0; + } + } + + } +} + +void +sys_sem_wait(sys_sem_t sem) +{ + u32_t time; + struct sys_timeouts *timeouts; + struct sys_timeo *tmptimeout; + sys_timeout_handler h; + void *arg; + + /* while (sys_arch_sem_wait(sem, 1000) == 0); + return;*/ + + again: + + timeouts = sys_arch_timeouts(); + + if (!timeouts || !timeouts->next) { + sys_arch_sem_wait(sem, 0); + } else { + if (timeouts->next->time > 0) { + time = sys_arch_sem_wait(sem, timeouts->next->time); + } else { + time = SYS_ARCH_TIMEOUT; + } + + if (time == SYS_ARCH_TIMEOUT) { + /* If time == SYS_ARCH_TIMEOUT, a timeout occured before a message + could be fetched. We should now call the timeout handler and + deallocate the memory allocated for the timeout. */ + tmptimeout = timeouts->next; + timeouts->next = tmptimeout->next; + h = tmptimeout->h; + arg = tmptimeout->arg; + memp_free(MEMP_SYS_TIMEOUT, tmptimeout); + if (h != NULL) { + LWIP_DEBUGF(SYS_DEBUG, ("ssw h=%p(%p)\n", (void *)h, (void *)arg)); + h(arg); + } + + + /* We try again to fetch a message from the mbox. */ + goto again; + } else { + /* If time != SYS_ARCH_TIMEOUT, a message was received before the timeout + occured. The time variable is set to the number of + milliseconds we waited for the message. */ + if (time <= timeouts->next->time) { + timeouts->next->time -= time; + } else { + timeouts->next->time = 0; + } + } + + } +} + +void +sys_timeout(u32_t msecs, sys_timeout_handler h, void *arg) +{ + struct sys_timeouts *timeouts; + struct sys_timeo *timeout, *t; + + timeout = memp_malloc(MEMP_SYS_TIMEOUT); + if (timeout == NULL) { + return; + } + timeout->next = NULL; + timeout->h = h; + timeout->arg = arg; + timeout->time = msecs; + + timeouts = sys_arch_timeouts(); + + LWIP_DEBUGF(SYS_DEBUG, ("sys_timeout: %p msecs=%"U32_F" h=%p arg=%p\n", + (void *)timeout, msecs, (void *)h, (void *)arg)); + + LWIP_ASSERT("sys_timeout: timeouts != NULL", timeouts != NULL); + + if (timeouts->next == NULL) { + timeouts->next = timeout; + return; + } + + if (timeouts->next->time > msecs) { + timeouts->next->time -= msecs; + timeout->next = timeouts->next; + timeouts->next = timeout; + } else { + for(t = timeouts->next; t != NULL; t = t->next) { + timeout->time -= t->time; + if (t->next == NULL || t->next->time > timeout->time) { + if (t->next != NULL) { + t->next->time -= timeout->time; + } + timeout->next = t->next; + t->next = timeout; + break; + } + } + } + +} + +/* Go through timeout list (for this task only) and remove the first matching entry, + even though the timeout has not triggered yet. +*/ + +void +sys_untimeout(sys_timeout_handler h, void *arg) +{ + struct sys_timeouts *timeouts; + struct sys_timeo *prev_t, *t; + + timeouts = sys_arch_timeouts(); + + if (timeouts->next == NULL) + return; + + for (t = timeouts->next, prev_t = NULL; t != NULL; prev_t = t, t = t->next) + { + if ((t->h == h) && (t->arg == arg)) + { + /* We have a match */ + /* Unlink from previous in list */ + if (prev_t == NULL) + timeouts->next = t->next; + else + prev_t->next = t->next; + /* If not the last one, add time of this one back to next */ + if (t->next != NULL) + t->next->time += t->time; + memp_free(MEMP_SYS_TIMEOUT, t); + return; + } + } + return; +} + + + + + +static void +sswt_handler(void *arg) +{ + struct sswt_cb *sswt_cb = (struct sswt_cb *) arg; + + /* Timeout. Set flag to TRUE and signal semaphore */ + sswt_cb->timeflag = 1; + sys_sem_signal(*(sswt_cb->psem)); +} + +/* Wait for a semaphore with timeout (specified in ms) */ +/* timeout = 0: wait forever */ +/* Returns 0 on timeout. 1 otherwise */ + +int +sys_sem_wait_timeout(sys_sem_t sem, u32_t timeout) +{ + struct sswt_cb sswt_cb; + + sswt_cb.psem = &sem; + sswt_cb.timeflag = 0; + + /* If timeout is zero, then just wait forever */ + if (timeout > 0) + /* Create a timer and pass it the address of our flag */ + sys_timeout(timeout, sswt_handler, &sswt_cb); + sys_sem_wait(sem); + /* Was it a timeout? */ + if (sswt_cb.timeflag) + { + /* timeout */ + return 0; + } else { + /* Not a timeout. Remove timeout entry */ + sys_untimeout(sswt_handler, &sswt_cb); + return 1; + } + +} + + +void +sys_msleep(u32_t ms) +{ + sys_sem_t delaysem = sys_sem_new(0); + + sys_sem_wait_timeout(delaysem, ms); + + sys_sem_free(delaysem); +} + + +#endif /* NO_SYS */ diff --git a/20080212/Demo/Common/ethernet/lwIP/core/tcp.c b/20080212/Demo/Common/ethernet/lwIP/core/tcp.c new file mode 100644 index 000000000..5b69ee7cf --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/core/tcp.c @@ -0,0 +1,1182 @@ +/** + * @file + * + * Transmission Control Protocol for IP + * + * This file contains common functions for the TCP implementation, such as functinos + * for manipulating the data structures and the TCP timer functions. TCP functions + * related to input and output is found in tcp_in.c and tcp_out.c respectively. + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include + +#include "lwip/opt.h" +#include "lwip/def.h" +#include "lwip/mem.h" +#include "lwip/memp.h" +#include "lwip/snmp.h" + +#include "lwip/tcp.h" +#if LWIP_TCP + +/* Incremented every coarse grained timer shot (typically every 500 ms). */ +u32_t tcp_ticks; +const u8_t tcp_backoff[13] = + { 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7}; + +/* The TCP PCB lists. */ + +/** List of all TCP PCBs in LISTEN state */ +union tcp_listen_pcbs_t tcp_listen_pcbs; +/** List of all TCP PCBs that are in a state in which + * they accept or send data. */ +struct tcp_pcb *tcp_active_pcbs; +/** List of all TCP PCBs in TIME-WAIT state */ +struct tcp_pcb *tcp_tw_pcbs; + +struct tcp_pcb *tcp_tmp_pcb; + +static u8_t tcp_timer; +static u16_t tcp_new_port(void); + +/** + * Initializes the TCP layer. + */ +void +tcp_init(void) +{ + /* Clear globals. */ + tcp_listen_pcbs.listen_pcbs = NULL; + tcp_active_pcbs = NULL; + tcp_tw_pcbs = NULL; + tcp_tmp_pcb = NULL; + + /* initialize timer */ + tcp_ticks = 0; + tcp_timer = 0; + +} + +/** + * Called periodically to dispatch TCP timers. + * + */ +void +tcp_tmr(void) +{ + /* Call tcp_fasttmr() every 250 ms */ + tcp_fasttmr(); + + if (++tcp_timer & 1) { + /* Call tcp_tmr() every 500 ms, i.e., every other timer + tcp_tmr() is called. */ + tcp_slowtmr(); + } +} + +/** + * Closes the connection held by the PCB. + * + */ +err_t +tcp_close(struct tcp_pcb *pcb) +{ + err_t err; + +#if TCP_DEBUG + LWIP_DEBUGF(TCP_DEBUG, ("tcp_close: closing in ")); + tcp_debug_print_state(pcb->state); +#endif /* TCP_DEBUG */ + + switch (pcb->state) { + case CLOSED: + /* Closing a pcb in the CLOSED state might seem erroneous, + * however, it is in this state once allocated and as yet unused + * and the user needs some way to free it should the need arise. + * Calling tcp_close() with a pcb that has already been closed, (i.e. twice) + * or for a pcb that has been used and then entered the CLOSED state + * is erroneous, but this should never happen as the pcb has in those cases + * been freed, and so any remaining handles are bogus. */ + err = ERR_OK; + memp_free(MEMP_TCP_PCB, pcb); + pcb = NULL; + break; + case LISTEN: + err = ERR_OK; + tcp_pcb_remove((struct tcp_pcb **)&tcp_listen_pcbs.pcbs, pcb); + memp_free(MEMP_TCP_PCB_LISTEN, pcb); + pcb = NULL; + break; + case SYN_SENT: + err = ERR_OK; + tcp_pcb_remove(&tcp_active_pcbs, pcb); + memp_free(MEMP_TCP_PCB, pcb); + pcb = NULL; + snmp_inc_tcpattemptfails(); + break; + case SYN_RCVD: + err = tcp_send_ctrl(pcb, TCP_FIN); + if (err == ERR_OK) { + snmp_inc_tcpattemptfails(); + pcb->state = FIN_WAIT_1; + } + break; + case ESTABLISHED: + err = tcp_send_ctrl(pcb, TCP_FIN); + if (err == ERR_OK) { + snmp_inc_tcpestabresets(); + pcb->state = FIN_WAIT_1; + } + break; + case CLOSE_WAIT: + err = tcp_send_ctrl(pcb, TCP_FIN); + if (err == ERR_OK) { + snmp_inc_tcpestabresets(); + pcb->state = LAST_ACK; + } + break; + default: + /* Has already been closed, do nothing. */ + err = ERR_OK; + pcb = NULL; + break; + } + + if (pcb != NULL && err == ERR_OK) { + err = tcp_output(pcb); + } + return err; +} + +/** + * Aborts a connection by sending a RST to the remote host and deletes + * the local protocol control block. This is done when a connection is + * killed because of shortage of memory. + * + */ +void +tcp_abort(struct tcp_pcb *pcb) +{ + u32_t seqno, ackno; + u16_t remote_port, local_port; + struct ip_addr remote_ip, local_ip; +#if LWIP_CALLBACK_API + void (* errf)(void *arg, err_t err); +#endif /* LWIP_CALLBACK_API */ + void *errf_arg; + + + /* Figure out on which TCP PCB list we are, and remove us. If we + are in an active state, call the receive function associated with + the PCB with a NULL argument, and send an RST to the remote end. */ + if (pcb->state == TIME_WAIT) { + tcp_pcb_remove(&tcp_tw_pcbs, pcb); + memp_free(MEMP_TCP_PCB, pcb); + } else { + seqno = pcb->snd_nxt; + ackno = pcb->rcv_nxt; + ip_addr_set(&local_ip, &(pcb->local_ip)); + ip_addr_set(&remote_ip, &(pcb->remote_ip)); + local_port = pcb->local_port; + remote_port = pcb->remote_port; +#if LWIP_CALLBACK_API + errf = pcb->errf; +#endif /* LWIP_CALLBACK_API */ + errf_arg = pcb->callback_arg; + tcp_pcb_remove(&tcp_active_pcbs, pcb); + if (pcb->unacked != NULL) { + tcp_segs_free(pcb->unacked); + } + if (pcb->unsent != NULL) { + tcp_segs_free(pcb->unsent); + } +#if TCP_QUEUE_OOSEQ + if (pcb->ooseq != NULL) { + tcp_segs_free(pcb->ooseq); + } +#endif /* TCP_QUEUE_OOSEQ */ + memp_free(MEMP_TCP_PCB, pcb); + TCP_EVENT_ERR(errf, errf_arg, ERR_ABRT); + LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_abort: sending RST\n")); + tcp_rst(seqno, ackno, &local_ip, &remote_ip, local_port, remote_port); + } +} + +/** + * Binds the connection to a local portnumber and IP address. If the + * IP address is not given (i.e., ipaddr == NULL), the IP address of + * the outgoing network interface is used instead. + * + */ + +err_t +tcp_bind(struct tcp_pcb *pcb, struct ip_addr *ipaddr, u16_t port) +{ + struct tcp_pcb *cpcb; + + if (port == 0) { + port = tcp_new_port(); + } + /* Check if the address already is in use. */ + for(cpcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs; + cpcb != NULL; cpcb = cpcb->next) { + if (cpcb->local_port == port) { + if (ip_addr_isany(&(cpcb->local_ip)) || + ip_addr_isany(ipaddr) || + ip_addr_cmp(&(cpcb->local_ip), ipaddr)) { + return ERR_USE; + } + } + } + for(cpcb = tcp_active_pcbs; + cpcb != NULL; cpcb = cpcb->next) { + if (cpcb->local_port == port) { + if (ip_addr_isany(&(cpcb->local_ip)) || + ip_addr_isany(ipaddr) || + ip_addr_cmp(&(cpcb->local_ip), ipaddr)) { + return ERR_USE; + } + } + } + + if (!ip_addr_isany(ipaddr)) { + pcb->local_ip = *ipaddr; + } + pcb->local_port = port; + LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: bind to port %"U16_F"\n", port)); + return ERR_OK; +} +#if LWIP_CALLBACK_API +static err_t +tcp_accept_null(void *arg, struct tcp_pcb *pcb, err_t err) +{ + (void)arg; + (void)pcb; + (void)err; + + return ERR_ABRT; +} +#endif /* LWIP_CALLBACK_API */ + +/** + * Set the state of the connection to be LISTEN, which means that it + * is able to accept incoming connections. The protocol control block + * is reallocated in order to consume less memory. Setting the + * connection to LISTEN is an irreversible process. + * + */ +struct tcp_pcb * +tcp_listen(struct tcp_pcb *pcb) +{ + struct tcp_pcb_listen *lpcb; + + /* already listening? */ + if (pcb->state == LISTEN) { + return pcb; + } + lpcb = memp_malloc(MEMP_TCP_PCB_LISTEN); + if (lpcb == NULL) { + return NULL; + } + lpcb->callback_arg = pcb->callback_arg; + lpcb->local_port = pcb->local_port; + lpcb->state = LISTEN; + lpcb->so_options = pcb->so_options; + lpcb->so_options |= SOF_ACCEPTCONN; + lpcb->ttl = pcb->ttl; + lpcb->tos = pcb->tos; + ip_addr_set(&lpcb->local_ip, &pcb->local_ip); + memp_free(MEMP_TCP_PCB, pcb); +#if LWIP_CALLBACK_API + lpcb->accept = tcp_accept_null; +#endif /* LWIP_CALLBACK_API */ + TCP_REG(&tcp_listen_pcbs.listen_pcbs, lpcb); + return (struct tcp_pcb *)lpcb; +} + +/** + * This function should be called by the application when it has + * processed the data. The purpose is to advertise a larger window + * when the data has been processed. + * + */ +void +tcp_recved(struct tcp_pcb *pcb, u16_t len) +{ + if ((u32_t)pcb->rcv_wnd + len > TCP_WND) { + pcb->rcv_wnd = TCP_WND; + } else { + pcb->rcv_wnd += len; + } + if (!(pcb->flags & TF_ACK_DELAY) && + !(pcb->flags & TF_ACK_NOW)) { + /* + * We send an ACK here (if one is not already pending, hence + * the above tests) as tcp_recved() implies that the application + * has processed some data, and so we can open the receiver's + * window to allow more to be transmitted. This could result in + * two ACKs being sent for each received packet in some limited cases + * (where the application is only receiving data, and is slow to + * process it) but it is necessary to guarantee that the sender can + * continue to transmit. + */ + tcp_ack(pcb); + } + else if (pcb->flags & TF_ACK_DELAY && pcb->rcv_wnd >= TCP_WND/2) { + /* If we can send a window update such that there is a full + * segment available in the window, do so now. This is sort of + * nagle-like in its goals, and tries to hit a compromise between + * sending acks each time the window is updated, and only sending + * window updates when a timer expires. The "threshold" used + * above (currently TCP_WND/2) can be tuned to be more or less + * aggressive */ + tcp_ack_now(pcb); + } + + LWIP_DEBUGF(TCP_DEBUG, ("tcp_recved: recveived %"U16_F" bytes, wnd %"U16_F" (%"U16_F").\n", + len, pcb->rcv_wnd, TCP_WND - pcb->rcv_wnd)); +} + +/** + * A nastly hack featuring 'goto' statements that allocates a + * new TCP local port. + */ +static u16_t +tcp_new_port(void) +{ + struct tcp_pcb *pcb; +#ifndef TCP_LOCAL_PORT_RANGE_START +#define TCP_LOCAL_PORT_RANGE_START 4096 +#define TCP_LOCAL_PORT_RANGE_END 0x7fff +#endif + static u16_t port = TCP_LOCAL_PORT_RANGE_START; + + again: + if (++port > TCP_LOCAL_PORT_RANGE_END) { + port = TCP_LOCAL_PORT_RANGE_START; + } + + for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { + if (pcb->local_port == port) { + goto again; + } + } + for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { + if (pcb->local_port == port) { + goto again; + } + } + for(pcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs; pcb != NULL; pcb = pcb->next) { + if (pcb->local_port == port) { + goto again; + } + } + return port; +} + +/** + * Connects to another host. The function given as the "connected" + * argument will be called when the connection has been established. + * + */ +err_t +tcp_connect(struct tcp_pcb *pcb, struct ip_addr *ipaddr, u16_t port, + err_t (* connected)(void *arg, struct tcp_pcb *tpcb, err_t err)) +{ + u32_t optdata; + err_t ret; + u32_t iss; + + LWIP_DEBUGF(TCP_DEBUG, ("tcp_connect to port %"U16_F"\n", port)); + if (ipaddr != NULL) { + pcb->remote_ip = *ipaddr; + } else { + return ERR_VAL; + } + pcb->remote_port = port; + if (pcb->local_port == 0) { + pcb->local_port = tcp_new_port(); + } + iss = tcp_next_iss(); + pcb->rcv_nxt = 0; + pcb->snd_nxt = iss; + pcb->lastack = iss - 1; + pcb->snd_lbb = iss - 1; + pcb->rcv_wnd = TCP_WND; + pcb->snd_wnd = TCP_WND; + pcb->mss = TCP_MSS; + pcb->cwnd = 1; + pcb->ssthresh = pcb->mss * 10; + pcb->state = SYN_SENT; +#if LWIP_CALLBACK_API + pcb->connected = connected; +#endif /* LWIP_CALLBACK_API */ + TCP_REG(&tcp_active_pcbs, pcb); + + snmp_inc_tcpactiveopens(); + + /* Build an MSS option */ + optdata = htonl(((u32_t)2 << 24) | + ((u32_t)4 << 16) | + (((u32_t)pcb->mss / 256) << 8) | + (pcb->mss & 255)); + + ret = tcp_enqueue(pcb, NULL, 0, TCP_SYN, 0, (u8_t *)&optdata, 4); + if (ret == ERR_OK) { + tcp_output(pcb); + } + return ret; +} + +/** + * Called every 500 ms and implements the retransmission timer and the timer that + * removes PCBs that have been in TIME-WAIT for enough time. It also increments + * various timers such as the inactivity timer in each PCB. + */ +void +tcp_slowtmr(void) +{ + struct tcp_pcb *pcb, *pcb2, *prev; + u32_t eff_wnd; + u8_t pcb_remove; /* flag if a PCB should be removed */ + err_t err; + + err = ERR_OK; + + ++tcp_ticks; + + /* Steps through all of the active PCBs. */ + prev = NULL; + pcb = tcp_active_pcbs; + if (pcb == NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: no active pcbs\n")); + } + while (pcb != NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: processing active pcb\n")); + LWIP_ASSERT("tcp_slowtmr: active pcb->state != CLOSED\n", pcb->state != CLOSED); + LWIP_ASSERT("tcp_slowtmr: active pcb->state != LISTEN\n", pcb->state != LISTEN); + LWIP_ASSERT("tcp_slowtmr: active pcb->state != TIME-WAIT\n", pcb->state != TIME_WAIT); + + pcb_remove = 0; + + if (pcb->state == SYN_SENT && pcb->nrtx == TCP_SYNMAXRTX) { + ++pcb_remove; + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max SYN retries reached\n")); + } + else if (pcb->nrtx == TCP_MAXRTX) { + ++pcb_remove; + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max DATA retries reached\n")); + } else { + ++pcb->rtime; + if (pcb->unacked != NULL && pcb->rtime >= pcb->rto) { + + /* Time for a retransmission. */ + LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_slowtmr: rtime %"U16_F" pcb->rto %"U16_F"\n", + pcb->rtime, pcb->rto)); + + /* Double retransmission time-out unless we are trying to + * connect to somebody (i.e., we are in SYN_SENT). */ + if (pcb->state != SYN_SENT) { + pcb->rto = ((pcb->sa >> 3) + pcb->sv) << tcp_backoff[pcb->nrtx]; + } + /* Reduce congestion window and ssthresh. */ + eff_wnd = LWIP_MIN(pcb->cwnd, pcb->snd_wnd); + pcb->ssthresh = eff_wnd >> 1; + if (pcb->ssthresh < pcb->mss) { + pcb->ssthresh = pcb->mss * 2; + } + pcb->cwnd = pcb->mss; + LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: cwnd %"U16_F" ssthresh %"U16_F"\n", + pcb->cwnd, pcb->ssthresh)); + + /* The following needs to be called AFTER cwnd is set to one mss - STJ */ + tcp_rexmit_rto(pcb); + } + } + /* Check if this PCB has stayed too long in FIN-WAIT-2 */ + if (pcb->state == FIN_WAIT_2) { + if ((u32_t)(tcp_ticks - pcb->tmr) > + TCP_FIN_WAIT_TIMEOUT / TCP_SLOW_INTERVAL) { + ++pcb_remove; + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in FIN-WAIT-2\n")); + } + } + + /* Check if KEEPALIVE should be sent */ + if((pcb->so_options & SOF_KEEPALIVE) && ((pcb->state == ESTABLISHED) || (pcb->state == CLOSE_WAIT))) { + if((u32_t)(tcp_ticks - pcb->tmr) > (pcb->keepalive + TCP_MAXIDLE) / TCP_SLOW_INTERVAL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: KEEPALIVE timeout. Aborting connection to %"U16_F".%"U16_F".%"U16_F".%"U16_F".\n", + ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip), + ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip))); + + tcp_abort(pcb); + } + else if((u32_t)(tcp_ticks - pcb->tmr) > (pcb->keepalive + pcb->keep_cnt * TCP_KEEPINTVL) / TCP_SLOW_INTERVAL) { + tcp_keepalive(pcb); + pcb->keep_cnt++; + } + } + + /* If this PCB has queued out of sequence data, but has been + inactive for too long, will drop the data (it will eventually + be retransmitted). */ +#if TCP_QUEUE_OOSEQ + if (pcb->ooseq != NULL && + (u32_t)tcp_ticks - pcb->tmr >= + pcb->rto * TCP_OOSEQ_TIMEOUT) { + tcp_segs_free(pcb->ooseq); + pcb->ooseq = NULL; + LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: dropping OOSEQ queued data\n")); + } +#endif /* TCP_QUEUE_OOSEQ */ + + /* Check if this PCB has stayed too long in SYN-RCVD */ + if (pcb->state == SYN_RCVD) { + if ((u32_t)(tcp_ticks - pcb->tmr) > + TCP_SYN_RCVD_TIMEOUT / TCP_SLOW_INTERVAL) { + ++pcb_remove; + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in SYN-RCVD\n")); + } + } + + /* Check if this PCB has stayed too long in LAST-ACK */ + if (pcb->state == LAST_ACK) { + if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) { + ++pcb_remove; + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in LAST-ACK\n")); + } + } + + /* If the PCB should be removed, do it. */ + if (pcb_remove) { + tcp_pcb_purge(pcb); + /* Remove PCB from tcp_active_pcbs list. */ + if (prev != NULL) { + LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_active_pcbs", pcb != tcp_active_pcbs); + prev->next = pcb->next; + } else { + /* This PCB was the first. */ + LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_active_pcbs", tcp_active_pcbs == pcb); + tcp_active_pcbs = pcb->next; + } + + TCP_EVENT_ERR(pcb->errf, pcb->callback_arg, ERR_ABRT); + + pcb2 = pcb->next; + memp_free(MEMP_TCP_PCB, pcb); + pcb = pcb2; + } else { + + /* We check if we should poll the connection. */ + ++pcb->polltmr; + if (pcb->polltmr >= pcb->pollinterval) { + pcb->polltmr = 0; + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: polling application\n")); + TCP_EVENT_POLL(pcb, err); + if (err == ERR_OK) { + tcp_output(pcb); + } + } + + prev = pcb; + pcb = pcb->next; + } + } + + + /* Steps through all of the TIME-WAIT PCBs. */ + prev = NULL; + pcb = tcp_tw_pcbs; + while (pcb != NULL) { + LWIP_ASSERT("tcp_slowtmr: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT); + pcb_remove = 0; + + /* Check if this PCB has stayed long enough in TIME-WAIT */ + if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) { + ++pcb_remove; + } + + + + /* If the PCB should be removed, do it. */ + if (pcb_remove) { + tcp_pcb_purge(pcb); + /* Remove PCB from tcp_tw_pcbs list. */ + if (prev != NULL) { + LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_tw_pcbs", pcb != tcp_tw_pcbs); + prev->next = pcb->next; + } else { + /* This PCB was the first. */ + LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_tw_pcbs", tcp_tw_pcbs == pcb); + tcp_tw_pcbs = pcb->next; + } + pcb2 = pcb->next; + memp_free(MEMP_TCP_PCB, pcb); + pcb = pcb2; + } else { + prev = pcb; + pcb = pcb->next; + } + } +} + +/** + * Is called every TCP_FAST_INTERVAL (250 ms) and sends delayed ACKs. + */ +void +tcp_fasttmr(void) +{ + struct tcp_pcb *pcb; + + /* send delayed ACKs */ + for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { + if (pcb->flags & TF_ACK_DELAY) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_fasttmr: delayed ACK\n")); + tcp_ack_now(pcb); + pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW); + } + } +} + +/** + * Deallocates a list of TCP segments (tcp_seg structures). + * + */ +u8_t +tcp_segs_free(struct tcp_seg *seg) +{ + u8_t count = 0; + struct tcp_seg *next; + while (seg != NULL) { + next = seg->next; + count += tcp_seg_free(seg); + seg = next; + } + return count; +} + +/** + * Frees a TCP segment. + * + */ +u8_t +tcp_seg_free(struct tcp_seg *seg) +{ + u8_t count = 0; + + if (seg != NULL) { + if (seg->p != NULL) { + count = pbuf_free(seg->p); +#if TCP_DEBUG + seg->p = NULL; +#endif /* TCP_DEBUG */ + } + memp_free(MEMP_TCP_SEG, seg); + } + return count; +} + +/** + * Sets the priority of a connection. + * + */ +void +tcp_setprio(struct tcp_pcb *pcb, u8_t prio) +{ + pcb->prio = prio; +} +#if TCP_QUEUE_OOSEQ + +/** + * Returns a copy of the given TCP segment. + * + */ +struct tcp_seg * +tcp_seg_copy(struct tcp_seg *seg) +{ + struct tcp_seg *cseg; + + cseg = memp_malloc(MEMP_TCP_SEG); + if (cseg == NULL) { + return NULL; + } + memcpy((u8_t *)cseg, (const u8_t *)seg, sizeof(struct tcp_seg)); + pbuf_ref(cseg->p); + return cseg; +} +#endif + +#if LWIP_CALLBACK_API +static err_t +tcp_recv_null(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err) +{ + arg = arg; + if (p != NULL) { + pbuf_free(p); + } else if (err == ERR_OK) { + return tcp_close(pcb); + } + return ERR_OK; +} +#endif /* LWIP_CALLBACK_API */ + +static void +tcp_kill_prio(u8_t prio) +{ + struct tcp_pcb *pcb, *inactive; + u32_t inactivity; + u8_t mprio; + + + mprio = TCP_PRIO_MAX; + + /* We kill the oldest active connection that has lower priority than + prio. */ + inactivity = 0; + inactive = NULL; + for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { + if (pcb->prio <= prio && + pcb->prio <= mprio && + (u32_t)(tcp_ticks - pcb->tmr) >= inactivity) { + inactivity = tcp_ticks - pcb->tmr; + inactive = pcb; + mprio = pcb->prio; + } + } + if (inactive != NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_prio: killing oldest PCB %p (%"S32_F")\n", + (void *)inactive, inactivity)); + tcp_abort(inactive); + } +} + + +static void +tcp_kill_timewait(void) +{ + struct tcp_pcb *pcb, *inactive; + u32_t inactivity; + + inactivity = 0; + inactive = NULL; + for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { + if ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity) { + inactivity = tcp_ticks - pcb->tmr; + inactive = pcb; + } + } + if (inactive != NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_timewait: killing oldest TIME-WAIT PCB %p (%"S32_F")\n", + (void *)inactive, inactivity)); + tcp_abort(inactive); + } +} + + + +struct tcp_pcb * +tcp_alloc(u8_t prio) +{ + struct tcp_pcb *pcb; + u32_t iss; + + pcb = memp_malloc(MEMP_TCP_PCB); + if (pcb == NULL) { + /* Try killing oldest connection in TIME-WAIT. */ + LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest TIME-WAIT connection\n")); + tcp_kill_timewait(); + pcb = memp_malloc(MEMP_TCP_PCB); + if (pcb == NULL) { + tcp_kill_prio(prio); + pcb = memp_malloc(MEMP_TCP_PCB); + } + } + if (pcb != NULL) { + memset(pcb, 0, sizeof(struct tcp_pcb)); + pcb->prio = TCP_PRIO_NORMAL; + pcb->snd_buf = TCP_SND_BUF; + pcb->snd_queuelen = 0; + pcb->rcv_wnd = TCP_WND; + pcb->tos = 0; + pcb->ttl = TCP_TTL; + pcb->mss = TCP_MSS; + pcb->rto = 3000 / TCP_SLOW_INTERVAL; + pcb->sa = 0; + pcb->sv = 3000 / TCP_SLOW_INTERVAL; + pcb->rtime = 0; + pcb->cwnd = 1; + iss = tcp_next_iss(); + pcb->snd_wl2 = iss; + pcb->snd_nxt = iss; + pcb->snd_max = iss; + pcb->lastack = iss; + pcb->snd_lbb = iss; + pcb->tmr = tcp_ticks; + + pcb->polltmr = 0; + +#if LWIP_CALLBACK_API + pcb->recv = tcp_recv_null; +#endif /* LWIP_CALLBACK_API */ + + /* Init KEEPALIVE timer */ + pcb->keepalive = TCP_KEEPDEFAULT; + pcb->keep_cnt = 0; + } + return pcb; +} + +/** + * Creates a new TCP protocol control block but doesn't place it on + * any of the TCP PCB lists. + * + * @internal: Maybe there should be a idle TCP PCB list where these + * PCBs are put on. We can then implement port reservation using + * tcp_bind(). Currently, we lack this (BSD socket type of) feature. + */ + +struct tcp_pcb * +tcp_new(void) +{ + return tcp_alloc(TCP_PRIO_NORMAL); +} + +/* + * tcp_arg(): + * + * Used to specify the argument that should be passed callback + * functions. + * + */ + +void +tcp_arg(struct tcp_pcb *pcb, void *arg) +{ + pcb->callback_arg = arg; +} +#if LWIP_CALLBACK_API + +/** + * Used to specify the function that should be called when a TCP + * connection receives data. + * + */ +void +tcp_recv(struct tcp_pcb *pcb, + err_t (* recv)(void *arg, struct tcp_pcb *tpcb, struct pbuf *p, err_t err)) +{ + pcb->recv = recv; +} + +/** + * Used to specify the function that should be called when TCP data + * has been successfully delivered to the remote host. + * + */ + +void +tcp_sent(struct tcp_pcb *pcb, + err_t (* sent)(void *arg, struct tcp_pcb *tpcb, u16_t len)) +{ + pcb->sent = sent; +} + +/** + * Used to specify the function that should be called when a fatal error + * has occured on the connection. + * + */ +void +tcp_err(struct tcp_pcb *pcb, + void (* errf)(void *arg, err_t err)) +{ + pcb->errf = errf; +} + +/** + * Used for specifying the function that should be called when a + * LISTENing connection has been connected to another host. + * + */ +void +tcp_accept(struct tcp_pcb *pcb, + err_t (* accept)(void *arg, struct tcp_pcb *newpcb, err_t err)) +{ + ((struct tcp_pcb_listen *)pcb)->accept = accept; +} +#endif /* LWIP_CALLBACK_API */ + + +/** + * Used to specify the function that should be called periodically + * from TCP. The interval is specified in terms of the TCP coarse + * timer interval, which is called twice a second. + * + */ +void +tcp_poll(struct tcp_pcb *pcb, + err_t (* poll)(void *arg, struct tcp_pcb *tpcb), u8_t interval) +{ +#if LWIP_CALLBACK_API + pcb->poll = poll; +#endif /* LWIP_CALLBACK_API */ + pcb->pollinterval = interval; +} + +/** + * Purges a TCP PCB. Removes any buffered data and frees the buffer memory. + * + */ +void +tcp_pcb_purge(struct tcp_pcb *pcb) +{ + if (pcb->state != CLOSED && + pcb->state != TIME_WAIT && + pcb->state != LISTEN) { + + LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge\n")); + + if (pcb->unsent != NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: not all data sent\n")); + } + if (pcb->unacked != NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->unacked\n")); + } +#if TCP_QUEUE_OOSEQ /* LW */ + if (pcb->ooseq != NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->ooseq\n")); + } + + tcp_segs_free(pcb->ooseq); + pcb->ooseq = NULL; +#endif /* TCP_QUEUE_OOSEQ */ + tcp_segs_free(pcb->unsent); + tcp_segs_free(pcb->unacked); + pcb->unacked = pcb->unsent = NULL; + } +} + +/** + * Purges the PCB and removes it from a PCB list. Any delayed ACKs are sent first. + * + */ +void +tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb) +{ + TCP_RMV(pcblist, pcb); + + tcp_pcb_purge(pcb); + + /* if there is an outstanding delayed ACKs, send it */ + if (pcb->state != TIME_WAIT && + pcb->state != LISTEN && + pcb->flags & TF_ACK_DELAY) { + pcb->flags |= TF_ACK_NOW; + tcp_output(pcb); + } + pcb->state = CLOSED; + + LWIP_ASSERT("tcp_pcb_remove: tcp_pcbs_sane()", tcp_pcbs_sane()); +} + +/** + * Calculates a new initial sequence number for new connections. + * + */ +u32_t +tcp_next_iss(void) +{ + static u32_t iss = 6510; + + iss += tcp_ticks; /* XXX */ + return iss; +} + +#if TCP_DEBUG || TCP_INPUT_DEBUG || TCP_OUTPUT_DEBUG +void +tcp_debug_print(struct tcp_hdr *tcphdr) +{ + LWIP_DEBUGF(TCP_DEBUG, ("TCP header:\n")); + LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(TCP_DEBUG, ("| %5"U16_F" | %5"U16_F" | (src port, dest port)\n", + ntohs(tcphdr->src), ntohs(tcphdr->dest))); + LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(TCP_DEBUG, ("| %010"U32_F" | (seq no)\n", + ntohl(tcphdr->seqno))); + LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(TCP_DEBUG, ("| %010"U32_F" | (ack no)\n", + ntohl(tcphdr->ackno))); + LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(TCP_DEBUG, ("| %2"U16_F" | |%"U16_F"%"U16_F"%"U16_F"%"U16_F"%"U16_F"%"U16_F"| %5"U16_F" | (hdrlen, flags (", + TCPH_HDRLEN(tcphdr), + TCPH_FLAGS(tcphdr) >> 5 & 1, + TCPH_FLAGS(tcphdr) >> 4 & 1, + TCPH_FLAGS(tcphdr) >> 3 & 1, + TCPH_FLAGS(tcphdr) >> 2 & 1, + TCPH_FLAGS(tcphdr) >> 1 & 1, + TCPH_FLAGS(tcphdr) & 1, + ntohs(tcphdr->wnd))); + tcp_debug_print_flags(TCPH_FLAGS(tcphdr)); + LWIP_DEBUGF(TCP_DEBUG, ("), win)\n")); + LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(TCP_DEBUG, ("| 0x%04"X16_F" | %5"U16_F" | (chksum, urgp)\n", + ntohs(tcphdr->chksum), ntohs(tcphdr->urgp))); + LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); +} + +void +tcp_debug_print_state(enum tcp_state s) +{ + LWIP_DEBUGF(TCP_DEBUG, ("State: ")); + switch (s) { + case CLOSED: + LWIP_DEBUGF(TCP_DEBUG, ("CLOSED\n")); + break; + case LISTEN: + LWIP_DEBUGF(TCP_DEBUG, ("LISTEN\n")); + break; + case SYN_SENT: + LWIP_DEBUGF(TCP_DEBUG, ("SYN_SENT\n")); + break; + case SYN_RCVD: + LWIP_DEBUGF(TCP_DEBUG, ("SYN_RCVD\n")); + break; + case ESTABLISHED: + LWIP_DEBUGF(TCP_DEBUG, ("ESTABLISHED\n")); + break; + case FIN_WAIT_1: + LWIP_DEBUGF(TCP_DEBUG, ("FIN_WAIT_1\n")); + break; + case FIN_WAIT_2: + LWIP_DEBUGF(TCP_DEBUG, ("FIN_WAIT_2\n")); + break; + case CLOSE_WAIT: + LWIP_DEBUGF(TCP_DEBUG, ("CLOSE_WAIT\n")); + break; + case CLOSING: + LWIP_DEBUGF(TCP_DEBUG, ("CLOSING\n")); + break; + case LAST_ACK: + LWIP_DEBUGF(TCP_DEBUG, ("LAST_ACK\n")); + break; + case TIME_WAIT: + LWIP_DEBUGF(TCP_DEBUG, ("TIME_WAIT\n")); + break; + } +} + +void +tcp_debug_print_flags(u8_t flags) +{ + if (flags & TCP_FIN) { + LWIP_DEBUGF(TCP_DEBUG, ("FIN ")); + } + if (flags & TCP_SYN) { + LWIP_DEBUGF(TCP_DEBUG, ("SYN ")); + } + if (flags & TCP_RST) { + LWIP_DEBUGF(TCP_DEBUG, ("RST ")); + } + if (flags & TCP_PSH) { + LWIP_DEBUGF(TCP_DEBUG, ("PSH ")); + } + if (flags & TCP_ACK) { + LWIP_DEBUGF(TCP_DEBUG, ("ACK ")); + } + if (flags & TCP_URG) { + LWIP_DEBUGF(TCP_DEBUG, ("URG ")); + } + if (flags & TCP_ECE) { + LWIP_DEBUGF(TCP_DEBUG, ("ECE ")); + } + if (flags & TCP_CWR) { + LWIP_DEBUGF(TCP_DEBUG, ("CWR ")); + } +} + +void +tcp_debug_print_pcbs(void) +{ + struct tcp_pcb *pcb; + LWIP_DEBUGF(TCP_DEBUG, ("Active PCB states:\n")); + for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { + LWIP_DEBUGF(TCP_DEBUG, ("Local port %"U16_F", foreign port %"U16_F" snd_nxt %"U32_F" rcv_nxt %"U32_F" ", + pcb->local_port, pcb->remote_port, + pcb->snd_nxt, pcb->rcv_nxt)); + tcp_debug_print_state(pcb->state); + } + LWIP_DEBUGF(TCP_DEBUG, ("Listen PCB states:\n")); + for(pcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs; pcb != NULL; pcb = pcb->next) { + LWIP_DEBUGF(TCP_DEBUG, ("Local port %"U16_F", foreign port %"U16_F" snd_nxt %"U32_F" rcv_nxt %"U32_F" ", + pcb->local_port, pcb->remote_port, + pcb->snd_nxt, pcb->rcv_nxt)); + tcp_debug_print_state(pcb->state); + } + LWIP_DEBUGF(TCP_DEBUG, ("TIME-WAIT PCB states:\n")); + for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { + LWIP_DEBUGF(TCP_DEBUG, ("Local port %"U16_F", foreign port %"U16_F" snd_nxt %"U32_F" rcv_nxt %"U32_F" ", + pcb->local_port, pcb->remote_port, + pcb->snd_nxt, pcb->rcv_nxt)); + tcp_debug_print_state(pcb->state); + } +} + +s16_t +tcp_pcbs_sane(void) +{ + struct tcp_pcb *pcb; + for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { + LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != CLOSED", pcb->state != CLOSED); + LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != LISTEN", pcb->state != LISTEN); + LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT); + } + for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { + LWIP_ASSERT("tcp_pcbs_sane: tw pcb->state == TIME-WAIT", pcb->state == TIME_WAIT); + } + return 1; +} +#endif /* TCP_DEBUG */ +#endif /* LWIP_TCP */ + + + + + + + + + + diff --git a/20080212/Demo/Common/ethernet/lwIP/core/tcp_in.c b/20080212/Demo/Common/ethernet/lwIP/core/tcp_in.c new file mode 100644 index 000000000..f711266dc --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/core/tcp_in.c @@ -0,0 +1,1211 @@ +/** + * @file + * + * Transmission Control Protocol, incoming traffic + * + * The input processing functions of the TCP layer. + * + * These functions are generally called in the order (ip_input() ->) + * tcp_input() -> * tcp_process() -> tcp_receive() (-> application). + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/def.h" +#include "lwip/opt.h" + +#include "lwip/ip_addr.h" +#include "lwip/netif.h" +#include "lwip/mem.h" +#include "lwip/memp.h" + +#include "lwip/inet.h" +#include "lwip/tcp.h" + +#include "lwip/stats.h" +#include "arch/perf.h" +#include "lwip/snmp.h" + +#if LWIP_TCP +/* These variables are global to all functions involved in the input + processing of TCP segments. They are set by the tcp_input() + function. */ +static struct tcp_seg inseg; +static struct tcp_hdr *tcphdr; +static struct ip_hdr *iphdr; +static u32_t seqno, ackno; +static u8_t flags; +static u16_t tcplen; + +static u8_t recv_flags; +static struct pbuf *recv_data; + +struct tcp_pcb *tcp_input_pcb; + +/* Forward declarations. */ +static err_t tcp_process(struct tcp_pcb *pcb); +static u8_t tcp_receive(struct tcp_pcb *pcb); +static void tcp_parseopt(struct tcp_pcb *pcb); + +static err_t tcp_listen_input(struct tcp_pcb_listen *pcb); +static err_t tcp_timewait_input(struct tcp_pcb *pcb); + +/* tcp_input: + * + * The initial input processing of TCP. It verifies the TCP header, demultiplexes + * the segment between the PCBs and passes it on to tcp_process(), which implements + * the TCP finite state machine. This function is called by the IP layer (in + * ip_input()). + */ + +void +tcp_input(struct pbuf *p, struct netif *inp) +{ + struct tcp_pcb *pcb, *prev; + struct tcp_pcb_listen *lpcb; + u8_t hdrlen; + err_t err; + + PERF_START; + + TCP_STATS_INC(tcp.recv); + snmp_inc_tcpinsegs(); + + iphdr = p->payload; + tcphdr = (struct tcp_hdr *)((u8_t *)p->payload + IPH_HL(iphdr) * 4); + +#if TCP_INPUT_DEBUG + tcp_debug_print(tcphdr); +#endif + + /* remove header from payload */ + if (pbuf_header(p, -((s16_t)(IPH_HL(iphdr) * 4))) || (p->tot_len < sizeof(struct tcp_hdr))) { + /* drop short packets */ + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: short packet (%"U16_F" bytes) discarded\n", p->tot_len)); + TCP_STATS_INC(tcp.lenerr); + TCP_STATS_INC(tcp.drop); + pbuf_free(p); + return; + } + + /* Don't even process incoming broadcasts/multicasts. */ + if (ip_addr_isbroadcast(&(iphdr->dest), inp) || + ip_addr_ismulticast(&(iphdr->dest))) { + snmp_inc_tcpinerrs(); + pbuf_free(p); + return; + } + +#if CHECKSUM_CHECK_TCP + /* Verify TCP checksum. */ + if (inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src), + (struct ip_addr *)&(iphdr->dest), + IP_PROTO_TCP, p->tot_len) != 0) { + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packet discarded due to failing checksum 0x%04"X16_F"\n", + inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src), (struct ip_addr *)&(iphdr->dest), + IP_PROTO_TCP, p->tot_len))); +#if TCP_DEBUG + tcp_debug_print(tcphdr); +#endif /* TCP_DEBUG */ + TCP_STATS_INC(tcp.chkerr); + TCP_STATS_INC(tcp.drop); + snmp_inc_tcpinerrs(); + pbuf_free(p); + return; + } +#endif + + /* Move the payload pointer in the pbuf so that it points to the + TCP data instead of the TCP header. */ + hdrlen = TCPH_HDRLEN(tcphdr); + pbuf_header(p, -(hdrlen * 4)); + + /* Convert fields in TCP header to host byte order. */ + tcphdr->src = ntohs(tcphdr->src); + tcphdr->dest = ntohs(tcphdr->dest); + seqno = tcphdr->seqno = ntohl(tcphdr->seqno); + ackno = tcphdr->ackno = ntohl(tcphdr->ackno); + tcphdr->wnd = ntohs(tcphdr->wnd); + + flags = TCPH_FLAGS(tcphdr) & TCP_FLAGS; + tcplen = p->tot_len + ((flags & TCP_FIN || flags & TCP_SYN)? 1: 0); + + /* Demultiplex an incoming segment. First, we check if it is destined + for an active connection. */ + prev = NULL; + + + for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { + LWIP_ASSERT("tcp_input: active pcb->state != CLOSED", pcb->state != CLOSED); + LWIP_ASSERT("tcp_input: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT); + LWIP_ASSERT("tcp_input: active pcb->state != LISTEN", pcb->state != LISTEN); + if (pcb->remote_port == tcphdr->src && + pcb->local_port == tcphdr->dest && + ip_addr_cmp(&(pcb->remote_ip), &(iphdr->src)) && + ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest))) { + + /* Move this PCB to the front of the list so that subsequent + lookups will be faster (we exploit locality in TCP segment + arrivals). */ + LWIP_ASSERT("tcp_input: pcb->next != pcb (before cache)", pcb->next != pcb); + if (prev != NULL) { + prev->next = pcb->next; + pcb->next = tcp_active_pcbs; + tcp_active_pcbs = pcb; + } + LWIP_ASSERT("tcp_input: pcb->next != pcb (after cache)", pcb->next != pcb); + break; + } + prev = pcb; + } + + if (pcb == NULL) { + /* If it did not go to an active connection, we check the connections + in the TIME-WAIT state. */ + for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { + LWIP_ASSERT("tcp_input: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT); + if (pcb->remote_port == tcphdr->src && + pcb->local_port == tcphdr->dest && + ip_addr_cmp(&(pcb->remote_ip), &(iphdr->src)) && + ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest))) { + /* We don't really care enough to move this PCB to the front + of the list since we are not very likely to receive that + many segments for connections in TIME-WAIT. */ + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packed for TIME_WAITing connection.\n")); + tcp_timewait_input(pcb); + pbuf_free(p); + return; + } + } + + /* Finally, if we still did not get a match, we check all PCBs that + are LISTENing for incoming connections. */ + prev = NULL; + for(lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) { + if ((ip_addr_isany(&(lpcb->local_ip)) || + ip_addr_cmp(&(lpcb->local_ip), &(iphdr->dest))) && + lpcb->local_port == tcphdr->dest) { + /* Move this PCB to the front of the list so that subsequent + lookups will be faster (we exploit locality in TCP segment + arrivals). */ + if (prev != NULL) { + ((struct tcp_pcb_listen *)prev)->next = lpcb->next; + /* our successor is the remainder of the listening list */ + lpcb->next = tcp_listen_pcbs.listen_pcbs; + /* put this listening pcb at the head of the listening list */ + tcp_listen_pcbs.listen_pcbs = lpcb; + } + + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packed for LISTENing connection.\n")); + tcp_listen_input(lpcb); + pbuf_free(p); + return; + } + prev = (struct tcp_pcb *)lpcb; + } + } + +#if TCP_INPUT_DEBUG + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("+-+-+-+-+-+-+-+-+-+-+-+-+-+- tcp_input: flags ")); + tcp_debug_print_flags(TCPH_FLAGS(tcphdr)); + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("-+-+-+-+-+-+-+-+-+-+-+-+-+-+\n")); +#endif /* TCP_INPUT_DEBUG */ + + + if (pcb != NULL) { + /* The incoming segment belongs to a connection. */ +#if TCP_INPUT_DEBUG +#if TCP_DEBUG + tcp_debug_print_state(pcb->state); +#endif /* TCP_DEBUG */ +#endif /* TCP_INPUT_DEBUG */ + + /* Set up a tcp_seg structure. */ + inseg.next = NULL; + inseg.len = p->tot_len; + inseg.dataptr = p->payload; + inseg.p = p; + inseg.tcphdr = tcphdr; + + recv_data = NULL; + recv_flags = 0; + + tcp_input_pcb = pcb; + err = tcp_process(pcb); + tcp_input_pcb = NULL; + /* A return value of ERR_ABRT means that tcp_abort() was called + and that the pcb has been freed. If so, we don't do anything. */ + if (err != ERR_ABRT) { + if (recv_flags & TF_RESET) { + /* TF_RESET means that the connection was reset by the other + end. We then call the error callback to inform the + application that the connection is dead before we + deallocate the PCB. */ + TCP_EVENT_ERR(pcb->errf, pcb->callback_arg, ERR_RST); + tcp_pcb_remove(&tcp_active_pcbs, pcb); + memp_free(MEMP_TCP_PCB, pcb); + } else if (recv_flags & TF_CLOSED) { + /* The connection has been closed and we will deallocate the + PCB. */ + tcp_pcb_remove(&tcp_active_pcbs, pcb); + memp_free(MEMP_TCP_PCB, pcb); + } else { + err = ERR_OK; + /* If the application has registered a "sent" function to be + called when new send buffer space is available, we call it + now. */ + if (pcb->acked > 0) { + TCP_EVENT_SENT(pcb, pcb->acked, err); + } + + if (recv_data != NULL) { + /* Notify application that data has been received. */ + TCP_EVENT_RECV(pcb, recv_data, ERR_OK, err); + } + + /* If a FIN segment was received, we call the callback + function with a NULL buffer to indicate EOF. */ + if (recv_flags & TF_GOT_FIN) { + TCP_EVENT_RECV(pcb, NULL, ERR_OK, err); + } + /* If there were no errors, we try to send something out. */ + if (err == ERR_OK) { + tcp_output(pcb); + } + } + } + + + /* give up our reference to inseg.p */ + if (inseg.p != NULL) + { + pbuf_free(inseg.p); + inseg.p = NULL; + } +#if TCP_INPUT_DEBUG +#if TCP_DEBUG + tcp_debug_print_state(pcb->state); +#endif /* TCP_DEBUG */ +#endif /* TCP_INPUT_DEBUG */ + + } else { + + /* If no matching PCB was found, send a TCP RST (reset) to the + sender. */ + LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_input: no PCB match found, resetting.\n")); + if (!(TCPH_FLAGS(tcphdr) & TCP_RST)) { + TCP_STATS_INC(tcp.proterr); + TCP_STATS_INC(tcp.drop); + tcp_rst(ackno, seqno + tcplen, + &(iphdr->dest), &(iphdr->src), + tcphdr->dest, tcphdr->src); + } + pbuf_free(p); + } + + LWIP_ASSERT("tcp_input: tcp_pcbs_sane()", tcp_pcbs_sane()); + PERF_STOP("tcp_input"); +} + +/* tcp_listen_input(): + * + * Called by tcp_input() when a segment arrives for a listening + * connection. + */ + +static err_t +tcp_listen_input(struct tcp_pcb_listen *pcb) +{ + struct tcp_pcb *npcb; + u32_t optdata; + + /* In the LISTEN state, we check for incoming SYN segments, + creates a new PCB, and responds with a SYN|ACK. */ + if (flags & TCP_ACK) { + /* For incoming segments with the ACK flag set, respond with a + RST. */ + LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_listen_input: ACK in LISTEN, sending reset\n")); + tcp_rst(ackno + 1, seqno + tcplen, + &(iphdr->dest), &(iphdr->src), + tcphdr->dest, tcphdr->src); + } else if (flags & TCP_SYN) { + LWIP_DEBUGF(TCP_DEBUG, ("TCP connection request %"U16_F" -> %"U16_F".\n", tcphdr->src, tcphdr->dest)); + npcb = tcp_alloc(pcb->prio); + /* If a new PCB could not be created (probably due to lack of memory), + we don't do anything, but rely on the sender will retransmit the + SYN at a time when we have more memory available. */ + if (npcb == NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_listen_input: could not allocate PCB\n")); + TCP_STATS_INC(tcp.memerr); + return ERR_MEM; + } + /* Set up the new PCB. */ + ip_addr_set(&(npcb->local_ip), &(iphdr->dest)); + npcb->local_port = pcb->local_port; + ip_addr_set(&(npcb->remote_ip), &(iphdr->src)); + npcb->remote_port = tcphdr->src; + npcb->state = SYN_RCVD; + npcb->rcv_nxt = seqno + 1; + npcb->snd_wnd = tcphdr->wnd; + npcb->ssthresh = npcb->snd_wnd; + npcb->snd_wl1 = seqno - 1;/* initialise to seqno-1 to force window update */ + npcb->callback_arg = pcb->callback_arg; +#if LWIP_CALLBACK_API + npcb->accept = pcb->accept; +#endif /* LWIP_CALLBACK_API */ + /* inherit socket options */ + npcb->so_options = pcb->so_options & (SOF_DEBUG|SOF_DONTROUTE|SOF_KEEPALIVE|SOF_OOBINLINE|SOF_LINGER); + /* Register the new PCB so that we can begin receiving segments + for it. */ + TCP_REG(&tcp_active_pcbs, npcb); + + /* Parse any options in the SYN. */ + tcp_parseopt(npcb); + + snmp_inc_tcppassiveopens(); + + /* Build an MSS option. */ + optdata = htonl(((u32_t)2 << 24) | + ((u32_t)4 << 16) | + (((u32_t)npcb->mss / 256) << 8) | + (npcb->mss & 255)); + /* Send a SYN|ACK together with the MSS option. */ + tcp_enqueue(npcb, NULL, 0, TCP_SYN | TCP_ACK, 0, (u8_t *)&optdata, 4); + return tcp_output(npcb); + } + return ERR_OK; +} + +/* tcp_timewait_input(): + * + * Called by tcp_input() when a segment arrives for a connection in + * TIME_WAIT. + */ + +static err_t +tcp_timewait_input(struct tcp_pcb *pcb) +{ + if (TCP_SEQ_GT(seqno + tcplen, pcb->rcv_nxt)) { + pcb->rcv_nxt = seqno + tcplen; + } + if (tcplen > 0) { + tcp_ack_now(pcb); + } + return tcp_output(pcb); +} + +/* tcp_process + * + * Implements the TCP state machine. Called by tcp_input. In some + * states tcp_receive() is called to receive data. The tcp_seg + * argument will be freed by the caller (tcp_input()) unless the + * recv_data pointer in the pcb is set. + */ + +static err_t +tcp_process(struct tcp_pcb *pcb) +{ + struct tcp_seg *rseg; + u8_t acceptable = 0; + err_t err; + u8_t accepted_inseq; + + err = ERR_OK; + + /* Process incoming RST segments. */ + if (flags & TCP_RST) { + /* First, determine if the reset is acceptable. */ + if (pcb->state == SYN_SENT) { + if (ackno == pcb->snd_nxt) { + acceptable = 1; + } + } else { + /*if (TCP_SEQ_GEQ(seqno, pcb->rcv_nxt) && + TCP_SEQ_LEQ(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) { + */ + if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt+pcb->rcv_wnd)) { + acceptable = 1; + } + } + + if (acceptable) { + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: Connection RESET\n")); + LWIP_ASSERT("tcp_input: pcb->state != CLOSED", pcb->state != CLOSED); + recv_flags = TF_RESET; + pcb->flags &= ~TF_ACK_DELAY; + return ERR_RST; + } else { + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n", + seqno, pcb->rcv_nxt)); + LWIP_DEBUGF(TCP_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n", + seqno, pcb->rcv_nxt)); + return ERR_OK; + } + } + + /* Update the PCB (in)activity timer. */ + pcb->tmr = tcp_ticks; + pcb->keep_cnt = 0; + + /* Do different things depending on the TCP state. */ + switch (pcb->state) { + case SYN_SENT: + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("SYN-SENT: ackno %"U32_F" pcb->snd_nxt %"U32_F" unacked %"U32_F"\n", ackno, + pcb->snd_nxt, ntohl(pcb->unacked->tcphdr->seqno))); + /* received SYN ACK with expected sequence number? */ + if ((flags & TCP_ACK) && (flags & TCP_SYN) + && ackno == ntohl(pcb->unacked->tcphdr->seqno) + 1) { + pcb->snd_buf++; + pcb->rcv_nxt = seqno + 1; + pcb->lastack = ackno; + pcb->snd_wnd = tcphdr->wnd; + pcb->snd_wl1 = seqno - 1; /* initialise to seqno - 1 to force window update */ + pcb->state = ESTABLISHED; + pcb->cwnd = ((pcb->cwnd == 1) ? (pcb->mss * 2) : pcb->mss); + --pcb->snd_queuelen; + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_process: SYN-SENT --queuelen %"U16_F"\n", (u16_t)pcb->snd_queuelen)); + rseg = pcb->unacked; + pcb->unacked = rseg->next; + tcp_seg_free(rseg); + + /* Parse any options in the SYNACK. */ + tcp_parseopt(pcb); + + /* Call the user specified function to call when sucessfully + * connected. */ + TCP_EVENT_CONNECTED(pcb, ERR_OK, err); + tcp_ack(pcb); + } + /* received ACK? possibly a half-open connection */ + else if (flags & TCP_ACK) { + /* send a RST to bring the other side in a non-synchronized state. */ + tcp_rst(ackno, seqno + tcplen, &(iphdr->dest), &(iphdr->src), + tcphdr->dest, tcphdr->src); + } + break; + case SYN_RCVD: + if (flags & TCP_ACK && + !(flags & TCP_RST)) { + /* expected ACK number? */ + if (TCP_SEQ_BETWEEN(ackno, pcb->lastack+1, pcb->snd_nxt)) { + u16_t old_cwnd; + pcb->state = ESTABLISHED; + LWIP_DEBUGF(TCP_DEBUG, ("TCP connection established %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); +#if LWIP_CALLBACK_API + LWIP_ASSERT("pcb->accept != NULL", pcb->accept != NULL); +#endif + /* Call the accept function. */ + TCP_EVENT_ACCEPT(pcb, ERR_OK, err); + if (err != ERR_OK) { + /* If the accept function returns with an error, we abort + * the connection. */ + tcp_abort(pcb); + return ERR_ABRT; + } + old_cwnd = pcb->cwnd; + /* If there was any data contained within this ACK, + * we'd better pass it on to the application as well. */ + tcp_receive(pcb); + pcb->cwnd = ((old_cwnd == 1) ? (pcb->mss * 2) : pcb->mss); + } + /* incorrect ACK number */ + else { + /* send RST */ + tcp_rst(ackno, seqno + tcplen, &(iphdr->dest), &(iphdr->src), + tcphdr->dest, tcphdr->src); + } + } + break; + case CLOSE_WAIT: + /* FALLTHROUGH */ + case ESTABLISHED: + accepted_inseq = tcp_receive(pcb); + if ((flags & TCP_FIN) && accepted_inseq) { /* passive close */ + tcp_ack_now(pcb); + pcb->state = CLOSE_WAIT; + } + break; + case FIN_WAIT_1: + tcp_receive(pcb); + if (flags & TCP_FIN) { + if (flags & TCP_ACK && ackno == pcb->snd_nxt) { + LWIP_DEBUGF(TCP_DEBUG, + ("TCP connection closed %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); + tcp_ack_now(pcb); + tcp_pcb_purge(pcb); + TCP_RMV(&tcp_active_pcbs, pcb); + pcb->state = TIME_WAIT; + TCP_REG(&tcp_tw_pcbs, pcb); + } else { + tcp_ack_now(pcb); + pcb->state = CLOSING; + } + } else if (flags & TCP_ACK && ackno == pcb->snd_nxt) { + pcb->state = FIN_WAIT_2; + } + break; + case FIN_WAIT_2: + tcp_receive(pcb); + if (flags & TCP_FIN) { + LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); + tcp_ack_now(pcb); + tcp_pcb_purge(pcb); + TCP_RMV(&tcp_active_pcbs, pcb); + pcb->state = TIME_WAIT; + TCP_REG(&tcp_tw_pcbs, pcb); + } + break; + case CLOSING: + tcp_receive(pcb); + if (flags & TCP_ACK && ackno == pcb->snd_nxt) { + LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); + tcp_ack_now(pcb); + tcp_pcb_purge(pcb); + TCP_RMV(&tcp_active_pcbs, pcb); + pcb->state = TIME_WAIT; + TCP_REG(&tcp_tw_pcbs, pcb); + } + break; + case LAST_ACK: + tcp_receive(pcb); + if (flags & TCP_ACK && ackno == pcb->snd_nxt) { + LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); + pcb->state = CLOSED; + recv_flags = TF_CLOSED; + } + break; + default: + break; + } + return ERR_OK; +} + +/* tcp_receive: + * + * Called by tcp_process. Checks if the given segment is an ACK for outstanding + * data, and if so frees the memory of the buffered data. Next, is places the + * segment on any of the receive queues (pcb->recved or pcb->ooseq). If the segment + * is buffered, the pbuf is referenced by pbuf_ref so that it will not be freed until + * i it has been removed from the buffer. + * + * If the incoming segment constitutes an ACK for a segment that was used for RTT + * estimation, the RTT is estimated here as well. + * + * @return 1 if + */ + +static u8_t +tcp_receive(struct tcp_pcb *pcb) +{ + struct tcp_seg *next; +#if TCP_QUEUE_OOSEQ + struct tcp_seg *prev, *cseg; +#endif + struct pbuf *p; + s32_t off; + s16_t m; + u32_t right_wnd_edge; + u16_t new_tot_len; + u8_t accepted_inseq = 0; + + if (flags & TCP_ACK) { + right_wnd_edge = pcb->snd_wnd + pcb->snd_wl1; + + /* Update window. */ + if (TCP_SEQ_LT(pcb->snd_wl1, seqno) || + (pcb->snd_wl1 == seqno && TCP_SEQ_LT(pcb->snd_wl2, ackno)) || + (pcb->snd_wl2 == ackno && tcphdr->wnd > pcb->snd_wnd)) { + pcb->snd_wnd = tcphdr->wnd; + pcb->snd_wl1 = seqno; + pcb->snd_wl2 = ackno; + LWIP_DEBUGF(TCP_WND_DEBUG, ("tcp_receive: window update %"U32_F"\n", pcb->snd_wnd)); +#if TCP_WND_DEBUG + } else { + if (pcb->snd_wnd != tcphdr->wnd) { + LWIP_DEBUGF(TCP_WND_DEBUG, ("tcp_receive: no window update lastack %"U32_F" snd_max %"U32_F" ackno %"U32_F" wl1 %"U32_F" seqno %"U32_F" wl2 %"U32_F"\n", + pcb->lastack, pcb->snd_max, ackno, pcb->snd_wl1, seqno, pcb->snd_wl2)); + } +#endif /* TCP_WND_DEBUG */ + } + + if (pcb->lastack == ackno) { + pcb->acked = 0; + + if (pcb->snd_wl1 + pcb->snd_wnd == right_wnd_edge){ + ++pcb->dupacks; + if (pcb->dupacks >= 3 && pcb->unacked != NULL) { + if (!(pcb->flags & TF_INFR)) { + /* This is fast retransmit. Retransmit the first unacked segment. */ + LWIP_DEBUGF(TCP_FR_DEBUG, ("tcp_receive: dupacks %"U16_F" (%"U32_F"), fast retransmit %"U32_F"\n", + (u16_t)pcb->dupacks, pcb->lastack, + ntohl(pcb->unacked->tcphdr->seqno))); + tcp_rexmit(pcb); + /* Set ssthresh to max (FlightSize / 2, 2*SMSS) */ + /*pcb->ssthresh = LWIP_MAX((pcb->snd_max - + pcb->lastack) / 2, + 2 * pcb->mss);*/ + /* Set ssthresh to half of the minimum of the currenct cwnd and the advertised window */ + if (pcb->cwnd > pcb->snd_wnd) + pcb->ssthresh = pcb->snd_wnd / 2; + else + pcb->ssthresh = pcb->cwnd / 2; + + pcb->cwnd = pcb->ssthresh + 3 * pcb->mss; + pcb->flags |= TF_INFR; + } else { + /* Inflate the congestion window, but not if it means that + the value overflows. */ + if ((u16_t)(pcb->cwnd + pcb->mss) > pcb->cwnd) { + pcb->cwnd += pcb->mss; + } + } + } + } else { + LWIP_DEBUGF(TCP_FR_DEBUG, ("tcp_receive: dupack averted %"U32_F" %"U32_F"\n", + pcb->snd_wl1 + pcb->snd_wnd, right_wnd_edge)); + } + } else + /*if (TCP_SEQ_LT(pcb->lastack, ackno) && + TCP_SEQ_LEQ(ackno, pcb->snd_max)) { */ + if (TCP_SEQ_BETWEEN(ackno, pcb->lastack+1, pcb->snd_max)){ + /* We come here when the ACK acknowledges new data. */ + + /* Reset the "IN Fast Retransmit" flag, since we are no longer + in fast retransmit. Also reset the congestion window to the + slow start threshold. */ + if (pcb->flags & TF_INFR) { + pcb->flags &= ~TF_INFR; + pcb->cwnd = pcb->ssthresh; + } + + /* Reset the number of retransmissions. */ + pcb->nrtx = 0; + + /* Reset the retransmission time-out. */ + pcb->rto = (pcb->sa >> 3) + pcb->sv; + + /* Update the send buffer space. */ + pcb->acked = ackno - pcb->lastack; + + pcb->snd_buf += pcb->acked; + + /* Reset the fast retransmit variables. */ + pcb->dupacks = 0; + pcb->lastack = ackno; + + /* Update the congestion control variables (cwnd and + ssthresh). */ + if (pcb->state >= ESTABLISHED) { + if (pcb->cwnd < pcb->ssthresh) { + if ((u16_t)(pcb->cwnd + pcb->mss) > pcb->cwnd) { + pcb->cwnd += pcb->mss; + } + LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: slow start cwnd %"U16_F"\n", pcb->cwnd)); + } else { + u16_t new_cwnd = (pcb->cwnd + pcb->mss * pcb->mss / pcb->cwnd); + if (new_cwnd > pcb->cwnd) { + pcb->cwnd = new_cwnd; + } + LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: congestion avoidance cwnd %"U16_F"\n", pcb->cwnd)); + } + } + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: ACK for %"U32_F", unacked->seqno %"U32_F":%"U32_F"\n", + ackno, + pcb->unacked != NULL? + ntohl(pcb->unacked->tcphdr->seqno): 0, + pcb->unacked != NULL? + ntohl(pcb->unacked->tcphdr->seqno) + TCP_TCPLEN(pcb->unacked): 0)); + + /* Remove segment from the unacknowledged list if the incoming + ACK acknowlegdes them. */ + while (pcb->unacked != NULL && + TCP_SEQ_LEQ(ntohl(pcb->unacked->tcphdr->seqno) + + TCP_TCPLEN(pcb->unacked), ackno)) { + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %"U32_F":%"U32_F" from pcb->unacked\n", + ntohl(pcb->unacked->tcphdr->seqno), + ntohl(pcb->unacked->tcphdr->seqno) + + TCP_TCPLEN(pcb->unacked))); + + next = pcb->unacked; + pcb->unacked = pcb->unacked->next; + + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %"U16_F" ... ", (u16_t)pcb->snd_queuelen)); + pcb->snd_queuelen -= pbuf_clen(next->p); + tcp_seg_free(next); + + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%"U16_F" (after freeing unacked)\n", (u16_t)pcb->snd_queuelen)); + if (pcb->snd_queuelen != 0) { + LWIP_ASSERT("tcp_receive: valid queue length", pcb->unacked != NULL || + pcb->unsent != NULL); + } + } + pcb->polltmr = 0; + } + + /* We go through the ->unsent list to see if any of the segments + on the list are acknowledged by the ACK. This may seem + strange since an "unsent" segment shouldn't be acked. The + rationale is that lwIP puts all outstanding segments on the + ->unsent list after a retransmission, so these segments may + in fact have been sent once. */ + while (pcb->unsent != NULL && + /*TCP_SEQ_LEQ(ntohl(pcb->unsent->tcphdr->seqno) + TCP_TCPLEN(pcb->unsent), ackno) && + TCP_SEQ_LEQ(ackno, pcb->snd_max)*/ + TCP_SEQ_BETWEEN(ackno, ntohl(pcb->unsent->tcphdr->seqno) + TCP_TCPLEN(pcb->unsent), pcb->snd_max) + ) { + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %"U32_F":%"U32_F" from pcb->unsent\n", + ntohl(pcb->unsent->tcphdr->seqno), ntohl(pcb->unsent->tcphdr->seqno) + + TCP_TCPLEN(pcb->unsent))); + + next = pcb->unsent; + pcb->unsent = pcb->unsent->next; + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %"U16_F" ... ", (u16_t)pcb->snd_queuelen)); + pcb->snd_queuelen -= pbuf_clen(next->p); + tcp_seg_free(next); + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%"U16_F" (after freeing unsent)\n", (u16_t)pcb->snd_queuelen)); + if (pcb->snd_queuelen != 0) { + LWIP_ASSERT("tcp_receive: valid queue length", + pcb->unacked != NULL || pcb->unsent != NULL); + } + + if (pcb->unsent != NULL) { + pcb->snd_nxt = htonl(pcb->unsent->tcphdr->seqno); + } + } + /* End of ACK for new data processing. */ + + LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: pcb->rttest %"U32_F" rtseq %"U32_F" ackno %"U32_F"\n", + pcb->rttest, pcb->rtseq, ackno)); + + /* RTT estimation calculations. This is done by checking if the + incoming segment acknowledges the segment we use to take a + round-trip time measurement. */ + if (pcb->rttest && TCP_SEQ_LT(pcb->rtseq, ackno)) { + m = tcp_ticks - pcb->rttest; + + LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: experienced rtt %"U16_F" ticks (%"U16_F" msec).\n", + m, m * TCP_SLOW_INTERVAL)); + + /* This is taken directly from VJs original code in his paper */ + m = m - (pcb->sa >> 3); + pcb->sa += m; + if (m < 0) { + m = -m; + } + m = m - (pcb->sv >> 2); + pcb->sv += m; + pcb->rto = (pcb->sa >> 3) + pcb->sv; + + LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: RTO %"U16_F" (%"U16_F" miliseconds)\n", + pcb->rto, pcb->rto * TCP_SLOW_INTERVAL)); + + pcb->rttest = 0; + } + } + + /* If the incoming segment contains data, we must process it + further. */ + if (tcplen > 0) { + /* This code basically does three things: + + +) If the incoming segment contains data that is the next + in-sequence data, this data is passed to the application. This + might involve trimming the first edge of the data. The rcv_nxt + variable and the advertised window are adjusted. + + +) If the incoming segment has data that is above the next + sequence number expected (->rcv_nxt), the segment is placed on + the ->ooseq queue. This is done by finding the appropriate + place in the ->ooseq queue (which is ordered by sequence + number) and trim the segment in both ends if needed. An + immediate ACK is sent to indicate that we received an + out-of-sequence segment. + + +) Finally, we check if the first segment on the ->ooseq queue + now is in sequence (i.e., if rcv_nxt >= ooseq->seqno). If + rcv_nxt > ooseq->seqno, we must trim the first edge of the + segment on ->ooseq before we adjust rcv_nxt. The data in the + segments that are now on sequence are chained onto the + incoming segment so that we only need to call the application + once. + */ + + /* First, we check if we must trim the first edge. We have to do + this if the sequence number of the incoming segment is less + than rcv_nxt, and the sequence number plus the length of the + segment is larger than rcv_nxt. */ + /* if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)){ + if (TCP_SEQ_LT(pcb->rcv_nxt, seqno + tcplen)) {*/ + if (TCP_SEQ_BETWEEN(pcb->rcv_nxt, seqno + 1, seqno + tcplen - 1)){ + /* Trimming the first edge is done by pushing the payload + pointer in the pbuf downwards. This is somewhat tricky since + we do not want to discard the full contents of the pbuf up to + the new starting point of the data since we have to keep the + TCP header which is present in the first pbuf in the chain. + + What is done is really quite a nasty hack: the first pbuf in + the pbuf chain is pointed to by inseg.p. Since we need to be + able to deallocate the whole pbuf, we cannot change this + inseg.p pointer to point to any of the later pbufs in the + chain. Instead, we point the ->payload pointer in the first + pbuf to data in one of the later pbufs. We also set the + inseg.data pointer to point to the right place. This way, the + ->p pointer will still point to the first pbuf, but the + ->p->payload pointer will point to data in another pbuf. + + After we are done with adjusting the pbuf pointers we must + adjust the ->data pointer in the seg and the segment + length.*/ + + off = pcb->rcv_nxt - seqno; + p = inseg.p; + LWIP_ASSERT("inseg.p != NULL", inseg.p); + if (inseg.p->len < off) { + new_tot_len = inseg.p->tot_len - off; + while (p->len < off) { + off -= p->len; + /* KJM following line changed (with addition of new_tot_len var) + to fix bug #9076 + inseg.p->tot_len -= p->len; */ + p->tot_len = new_tot_len; + p->len = 0; + p = p->next; + } + pbuf_header(p, -off); + } else { + pbuf_header(inseg.p, -off); + } + /* KJM following line changed to use p->payload rather than inseg->p->payload + to fix bug #9076 */ + inseg.dataptr = p->payload; + inseg.len -= pcb->rcv_nxt - seqno; + inseg.tcphdr->seqno = seqno = pcb->rcv_nxt; + } + else { + if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)){ + /* the whole segment is < rcv_nxt */ + /* must be a duplicate of a packet that has already been correctly handled */ + + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: duplicate seqno %"U32_F"\n", seqno)); + tcp_ack_now(pcb); + } + } + + /* The sequence number must be within the window (above rcv_nxt + and below rcv_nxt + rcv_wnd) in order to be further + processed. */ + /*if (TCP_SEQ_GEQ(seqno, pcb->rcv_nxt) && + TCP_SEQ_LT(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) {*/ + if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd - 1)){ + if (pcb->rcv_nxt == seqno) { + accepted_inseq = 1; + /* The incoming segment is the next in sequence. We check if + we have to trim the end of the segment and update rcv_nxt + and pass the data to the application. */ +#if TCP_QUEUE_OOSEQ + if (pcb->ooseq != NULL && + TCP_SEQ_LEQ(pcb->ooseq->tcphdr->seqno, seqno + inseg.len)) { + /* We have to trim the second edge of the incoming + segment. */ + inseg.len = pcb->ooseq->tcphdr->seqno - seqno; + pbuf_realloc(inseg.p, inseg.len); + } +#endif /* TCP_QUEUE_OOSEQ */ + + tcplen = TCP_TCPLEN(&inseg); + + /* First received FIN will be ACKed +1, on any successive (duplicate) + * FINs we are already in CLOSE_WAIT and have already done +1. + */ + if (pcb->state != CLOSE_WAIT) { + pcb->rcv_nxt += tcplen; + } + + /* Update the receiver's (our) window. */ + if (pcb->rcv_wnd < tcplen) { + pcb->rcv_wnd = 0; + } else { + pcb->rcv_wnd -= tcplen; + } + + /* If there is data in the segment, we make preparations to + pass this up to the application. The ->recv_data variable + is used for holding the pbuf that goes to the + application. The code for reassembling out-of-sequence data + chains its data on this pbuf as well. + + If the segment was a FIN, we set the TF_GOT_FIN flag that will + be used to indicate to the application that the remote side has + closed its end of the connection. */ + if (inseg.p->tot_len > 0) { + recv_data = inseg.p; + /* Since this pbuf now is the responsibility of the + application, we delete our reference to it so that we won't + (mistakingly) deallocate it. */ + inseg.p = NULL; + } + if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) { + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: received FIN.\n")); + recv_flags = TF_GOT_FIN; + } + +#if TCP_QUEUE_OOSEQ + /* We now check if we have segments on the ->ooseq queue that + is now in sequence. */ + while (pcb->ooseq != NULL && + pcb->ooseq->tcphdr->seqno == pcb->rcv_nxt) { + + cseg = pcb->ooseq; + seqno = pcb->ooseq->tcphdr->seqno; + + pcb->rcv_nxt += TCP_TCPLEN(cseg); + if (pcb->rcv_wnd < TCP_TCPLEN(cseg)) { + pcb->rcv_wnd = 0; + } else { + pcb->rcv_wnd -= TCP_TCPLEN(cseg); + } + if (cseg->p->tot_len > 0) { + /* Chain this pbuf onto the pbuf that we will pass to + the application. */ + if (recv_data) { + pbuf_cat(recv_data, cseg->p); + } else { + recv_data = cseg->p; + } + cseg->p = NULL; + } + if (TCPH_FLAGS(cseg->tcphdr) & TCP_FIN) { + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: dequeued FIN.\n")); + recv_flags = TF_GOT_FIN; + if (pcb->state == ESTABLISHED) { /* force passive close or we can move to active close */ + pcb->state = CLOSE_WAIT; + } + } + + + pcb->ooseq = cseg->next; + tcp_seg_free(cseg); + } +#endif /* TCP_QUEUE_OOSEQ */ + + + /* Acknowledge the segment(s). */ + tcp_ack(pcb); + + } else { + /* We get here if the incoming segment is out-of-sequence. */ + tcp_ack_now(pcb); +#if TCP_QUEUE_OOSEQ + /* We queue the segment on the ->ooseq queue. */ + if (pcb->ooseq == NULL) { + pcb->ooseq = tcp_seg_copy(&inseg); + } else { + /* If the queue is not empty, we walk through the queue and + try to find a place where the sequence number of the + incoming segment is between the sequence numbers of the + previous and the next segment on the ->ooseq queue. That is + the place where we put the incoming segment. If needed, we + trim the second edges of the previous and the incoming + segment so that it will fit into the sequence. + + If the incoming segment has the same sequence number as a + segment on the ->ooseq queue, we discard the segment that + contains less data. */ + + prev = NULL; + for(next = pcb->ooseq; next != NULL; next = next->next) { + if (seqno == next->tcphdr->seqno) { + /* The sequence number of the incoming segment is the + same as the sequence number of the segment on + ->ooseq. We check the lengths to see which one to + discard. */ + if (inseg.len > next->len) { + /* The incoming segment is larger than the old + segment. We replace the old segment with the new + one. */ + cseg = tcp_seg_copy(&inseg); + if (cseg != NULL) { + cseg->next = next->next; + if (prev != NULL) { + prev->next = cseg; + } else { + pcb->ooseq = cseg; + } + } + break; + } else { + /* Either the lenghts are the same or the incoming + segment was smaller than the old one; in either + case, we ditch the incoming segment. */ + break; + } + } else { + if (prev == NULL) { + if (TCP_SEQ_LT(seqno, next->tcphdr->seqno)) { + /* The sequence number of the incoming segment is lower + than the sequence number of the first segment on the + queue. We put the incoming segment first on the + queue. */ + + if (TCP_SEQ_GT(seqno + inseg.len, next->tcphdr->seqno)) { + /* We need to trim the incoming segment. */ + inseg.len = next->tcphdr->seqno - seqno; + pbuf_realloc(inseg.p, inseg.len); + } + cseg = tcp_seg_copy(&inseg); + if (cseg != NULL) { + cseg->next = next; + pcb->ooseq = cseg; + } + break; + } + } else + /*if (TCP_SEQ_LT(prev->tcphdr->seqno, seqno) && + TCP_SEQ_LT(seqno, next->tcphdr->seqno)) {*/ + if(TCP_SEQ_BETWEEN(seqno, prev->tcphdr->seqno+1, next->tcphdr->seqno-1)){ + /* The sequence number of the incoming segment is in + between the sequence numbers of the previous and + the next segment on ->ooseq. We trim and insert the + incoming segment and trim the previous segment, if + needed. */ + if (TCP_SEQ_GT(seqno + inseg.len, next->tcphdr->seqno)) { + /* We need to trim the incoming segment. */ + inseg.len = next->tcphdr->seqno - seqno; + pbuf_realloc(inseg.p, inseg.len); + } + + cseg = tcp_seg_copy(&inseg); + if (cseg != NULL) { + cseg->next = next; + prev->next = cseg; + if (TCP_SEQ_GT(prev->tcphdr->seqno + prev->len, seqno)) { + /* We need to trim the prev segment. */ + prev->len = seqno - prev->tcphdr->seqno; + pbuf_realloc(prev->p, prev->len); + } + } + break; + } + /* If the "next" segment is the last segment on the + ooseq queue, we add the incoming segment to the end + of the list. */ + if (next->next == NULL && + TCP_SEQ_GT(seqno, next->tcphdr->seqno)) { + next->next = tcp_seg_copy(&inseg); + if (next->next != NULL) { + if (TCP_SEQ_GT(next->tcphdr->seqno + next->len, seqno)) { + /* We need to trim the last segment. */ + next->len = seqno - next->tcphdr->seqno; + pbuf_realloc(next->p, next->len); + } + } + break; + } + } + prev = next; + } + } +#endif /* TCP_QUEUE_OOSEQ */ + + } + } else { + /*if (TCP_SEQ_GT(pcb->rcv_nxt, seqno) || + TCP_SEQ_GEQ(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) {*/ + if(!TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd-1)){ + tcp_ack_now(pcb); + } + } + } else { + /* Segments with length 0 is taken care of here. Segments that + fall out of the window are ACKed. */ + /*if (TCP_SEQ_GT(pcb->rcv_nxt, seqno) || + TCP_SEQ_GEQ(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) {*/ + if(!TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd-1)){ + tcp_ack_now(pcb); + } + } + return accepted_inseq; +} + +/* + * tcp_parseopt: + * + * Parses the options contained in the incoming segment. (Code taken + * from uIP with only small changes.) + * + */ + +static void +tcp_parseopt(struct tcp_pcb *pcb) +{ + u8_t c; + u8_t *opts, opt; + u16_t mss; + + opts = (u8_t *)tcphdr + TCP_HLEN; + + /* Parse the TCP MSS option, if present. */ + if(TCPH_HDRLEN(tcphdr) > 0x5) { + for(c = 0; c < (TCPH_HDRLEN(tcphdr) - 5) << 2 ;) { + opt = opts[c]; + if (opt == 0x00) { + /* End of options. */ + break; + } else if (opt == 0x01) { + ++c; + /* NOP option. */ + } else if (opt == 0x02 && + opts[c + 1] == 0x04) { + /* An MSS option with the right option length. */ + mss = (opts[c + 2] << 8) | opts[c + 3]; + pcb->mss = mss > TCP_MSS? TCP_MSS: mss; + + /* And we are done processing options. */ + break; + } else { + if (opts[c + 1] == 0) { + /* If the length field is zero, the options are malformed + and we don't process them further. */ + break; + } + /* All other options have a length field, so that we easily + can skip past them. */ + c += opts[c + 1]; + } + } + } +} +#endif /* LWIP_TCP */ + + diff --git a/20080212/Demo/Common/ethernet/lwIP/core/tcp_out.c b/20080212/Demo/Common/ethernet/lwIP/core/tcp_out.c new file mode 100644 index 000000000..8802fea0e --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/core/tcp_out.c @@ -0,0 +1,727 @@ +/** + * @file + * + * Transmission Control Protocol, outgoing traffic + * + * The output functions of TCP. + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include + +#include "lwip/def.h" +#include "lwip/opt.h" +#include "lwip/mem.h" +#include "lwip/memp.h" +#include "lwip/sys.h" +#include "lwip/ip_addr.h" +#include "lwip/netif.h" +#include "lwip/inet.h" +#include "lwip/tcp.h" +#include "lwip/stats.h" +#include "lwip/snmp.h" + +#if LWIP_TCP + +/* Forward declarations.*/ +static void tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb); + +err_t +tcp_send_ctrl(struct tcp_pcb *pcb, u8_t flags) +{ + /* no data, no length, flags, copy=1, no optdata, no optdatalen */ + return tcp_enqueue(pcb, NULL, 0, flags, 1, NULL, 0); +} + +/** + * Write data for sending (but does not send it immediately). + * + * It waits in the expectation of more data being sent soon (as + * it can send them more efficiently by combining them together). + * To prompt the system to send data now, call tcp_output() after + * calling tcp_write(). + * + * @arg pcb Protocol control block of the TCP connection to enqueue data for. + * + * @see tcp_write() + */ + +err_t +tcp_write(struct tcp_pcb *pcb, const void *arg, u16_t len, u8_t copy) +{ + LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_write(pcb=%p, arg=%p, len=%"U16_F", copy=%"U16_F")\n", (void *)pcb, + arg, len, (u16_t)copy)); + /* connection is in valid state for data transmission? */ + if (pcb->state == ESTABLISHED || + pcb->state == CLOSE_WAIT || + pcb->state == SYN_SENT || + pcb->state == SYN_RCVD) { + if (len > 0) { + return tcp_enqueue(pcb, (void *)arg, len, 0, copy, NULL, 0); + } + return ERR_OK; + } else { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | DBG_STATE | 3, ("tcp_write() called in invalid state\n")); + return ERR_CONN; + } +} + +/** + * Enqueue either data or TCP options (but not both) for tranmission + * + * + * + * @arg pcb Protocol control block for the TCP connection to enqueue data for. + * @arg arg Pointer to the data to be enqueued for sending. + * @arg len Data length in bytes + * @arg flags + * @arg copy 1 if data must be copied, 0 if data is non-volatile and can be + * referenced. + * @arg optdata + * @arg optlen + */ +err_t +tcp_enqueue(struct tcp_pcb *pcb, void *arg, u16_t len, + u8_t flags, u8_t copy, + u8_t *optdata, u8_t optlen) +{ + struct pbuf *p; + struct tcp_seg *seg, *useg, *queue; + u32_t left, seqno; + u16_t seglen; + void *ptr; + u8_t queuelen; + + LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_enqueue(pcb=%p, arg=%p, len=%"U16_F", flags=%"X16_F", copy=%"U16_F")\n", + (void *)pcb, arg, len, (u16_t)flags, (u16_t)copy)); + LWIP_ASSERT("tcp_enqueue: len == 0 || optlen == 0 (programmer violates API)", + len == 0 || optlen == 0); + LWIP_ASSERT("tcp_enqueue: arg == NULL || optdata == NULL (programmer violates API)", + arg == NULL || optdata == NULL); + /* fail on too much data */ + if (len > pcb->snd_buf) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 3, ("tcp_enqueue: too much data (len=%"U16_F" > snd_buf=%"U16_F")\n", len, pcb->snd_buf)); + return ERR_MEM; + } + left = len; + ptr = arg; + + /* seqno will be the sequence number of the first segment enqueued + * by the call to this function. */ + seqno = pcb->snd_lbb; + + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue: queuelen: %"U16_F"\n", (u16_t)pcb->snd_queuelen)); + + /* If total number of pbufs on the unsent/unacked queues exceeds the + * configured maximum, return an error */ + queuelen = pcb->snd_queuelen; + if (queuelen >= TCP_SND_QUEUELEN) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 3, ("tcp_enqueue: too long queue %"U16_F" (max %"U16_F")\n", queuelen, TCP_SND_QUEUELEN)); + TCP_STATS_INC(tcp.memerr); + return ERR_MEM; + } + if (queuelen != 0) { + LWIP_ASSERT("tcp_enqueue: pbufs on queue => at least one queue non-empty", + pcb->unacked != NULL || pcb->unsent != NULL); + } else { + LWIP_ASSERT("tcp_enqueue: no pbufs on queue => both queues empty", + pcb->unacked == NULL && pcb->unsent == NULL); + } + + /* First, break up the data into segments and tuck them together in + * the local "queue" variable. */ + useg = queue = seg = NULL; + seglen = 0; + while (queue == NULL || left > 0) { + + /* The segment length should be the MSS if the data to be enqueued + * is larger than the MSS. */ + seglen = left > pcb->mss? pcb->mss: left; + + /* Allocate memory for tcp_seg, and fill in fields. */ + seg = memp_malloc(MEMP_TCP_SEG); + if (seg == NULL) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: could not allocate memory for tcp_seg\n")); + goto memerr; + } + seg->next = NULL; + seg->p = NULL; + + /* first segment of to-be-queued data? */ + if (queue == NULL) { + queue = seg; + } + /* subsequent segments of to-be-queued data */ + else { + /* Attach the segment to the end of the queued segments */ + LWIP_ASSERT("useg != NULL", useg != NULL); + useg->next = seg; + } + /* remember last segment of to-be-queued data for next iteration */ + useg = seg; + + /* If copy is set, memory should be allocated + * and data copied into pbuf, otherwise data comes from + * ROM or other static memory, and need not be copied. If + * optdata is != NULL, we have options instead of data. */ + + /* options? */ + if (optdata != NULL) { + if ((seg->p = pbuf_alloc(PBUF_TRANSPORT, optlen, PBUF_RAM)) == NULL) { + goto memerr; + } + ++queuelen; + seg->dataptr = seg->p->payload; + } + /* copy from volatile memory? */ + else if (copy) { + if ((seg->p = pbuf_alloc(PBUF_TRANSPORT, seglen, PBUF_RAM)) == NULL) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue : could not allocate memory for pbuf copy size %"U16_F"\n", seglen)); + goto memerr; + } + ++queuelen; + if (arg != NULL) { + memcpy(seg->p->payload, ptr, seglen); + } + seg->dataptr = seg->p->payload; + } + /* do not copy data */ + else { + /* First, allocate a pbuf for holding the data. + * since the referenced data is available at least until it is sent out on the + * link (as it has to be ACKed by the remote party) we can safely use PBUF_ROM + * instead of PBUF_REF here. + */ + if ((p = pbuf_alloc(PBUF_TRANSPORT, seglen, PBUF_ROM)) == NULL) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: could not allocate memory for zero-copy pbuf\n")); + goto memerr; + } + ++queuelen; + /* reference the non-volatile payload data */ + p->payload = ptr; + seg->dataptr = ptr; + + /* Second, allocate a pbuf for the headers. */ + if ((seg->p = pbuf_alloc(PBUF_TRANSPORT, 0, PBUF_RAM)) == NULL) { + /* If allocation fails, we have to deallocate the data pbuf as + * well. */ + pbuf_free(p); + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: could not allocate memory for header pbuf\n")); + goto memerr; + } + ++queuelen; + + /* Concatenate the headers and data pbufs together. */ + pbuf_cat(seg->p/*header*/, p/*data*/); + p = NULL; + } + + /* Now that there are more segments queued, we check again if the + length of the queue exceeds the configured maximum. */ + if (queuelen > TCP_SND_QUEUELEN) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: queue too long %"U16_F" (%"U16_F")\n", queuelen, TCP_SND_QUEUELEN)); + goto memerr; + } + + seg->len = seglen; + + /* build TCP header */ + if (pbuf_header(seg->p, TCP_HLEN)) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: no room for TCP header in pbuf.\n")); + TCP_STATS_INC(tcp.err); + goto memerr; + } + seg->tcphdr = seg->p->payload; + seg->tcphdr->src = htons(pcb->local_port); + seg->tcphdr->dest = htons(pcb->remote_port); + seg->tcphdr->seqno = htonl(seqno); + seg->tcphdr->urgp = 0; + TCPH_FLAGS_SET(seg->tcphdr, flags); + /* don't fill in tcphdr->ackno and tcphdr->wnd until later */ + + /* Copy the options into the header, if they are present. */ + if (optdata == NULL) { + TCPH_HDRLEN_SET(seg->tcphdr, 5); + } + else { + TCPH_HDRLEN_SET(seg->tcphdr, (5 + optlen / 4)); + /* Copy options into data portion of segment. + Options can thus only be sent in non data carrying + segments such as SYN|ACK. */ + memcpy(seg->dataptr, optdata, optlen); + } + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | DBG_TRACE, ("tcp_enqueue: queueing %"U32_F":%"U32_F" (0x%"X16_F")\n", + ntohl(seg->tcphdr->seqno), + ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg), + (u16_t)flags)); + + left -= seglen; + seqno += seglen; + ptr = (void *)((u8_t *)ptr + seglen); + } + + /* Now that the data to be enqueued has been broken up into TCP + segments in the queue variable, we add them to the end of the + pcb->unsent queue. */ + if (pcb->unsent == NULL) { + useg = NULL; + } + else { + for (useg = pcb->unsent; useg->next != NULL; useg = useg->next); + } + /* { useg is last segment on the unsent queue, NULL if list is empty } */ + + /* If there is room in the last pbuf on the unsent queue, + chain the first pbuf on the queue together with that. */ + if (useg != NULL && + TCP_TCPLEN(useg) != 0 && + !(TCPH_FLAGS(useg->tcphdr) & (TCP_SYN | TCP_FIN)) && + !(flags & (TCP_SYN | TCP_FIN)) && + /* fit within max seg size */ + useg->len + queue->len <= pcb->mss) { + /* Remove TCP header from first segment of our to-be-queued list */ + pbuf_header(queue->p, -TCP_HLEN); + pbuf_cat(useg->p, queue->p); + useg->len += queue->len; + useg->next = queue->next; + + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | DBG_TRACE | DBG_STATE, ("tcp_enqueue: chaining segments, new len %"U16_F"\n", useg->len)); + if (seg == queue) { + seg = NULL; + } + memp_free(MEMP_TCP_SEG, queue); + } + else { + /* empty list */ + if (useg == NULL) { + /* initialize list with this segment */ + pcb->unsent = queue; + } + /* enqueue segment */ + else { + useg->next = queue; + } + } + if ((flags & TCP_SYN) || (flags & TCP_FIN)) { + ++len; + } + pcb->snd_lbb += len; + + pcb->snd_buf -= len; + + /* update number of segments on the queues */ + pcb->snd_queuelen = queuelen; + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue: %"S16_F" (after enqueued)\n", pcb->snd_queuelen)); + if (pcb->snd_queuelen != 0) { + LWIP_ASSERT("tcp_enqueue: valid queue length", + pcb->unacked != NULL || pcb->unsent != NULL); + } + + /* Set the PSH flag in the last segment that we enqueued, but only + if the segment has data (indicated by seglen > 0). */ + if (seg != NULL && seglen > 0 && seg->tcphdr != NULL) { + TCPH_SET_FLAG(seg->tcphdr, TCP_PSH); + } + + return ERR_OK; +memerr: + TCP_STATS_INC(tcp.memerr); + + if (queue != NULL) { + tcp_segs_free(queue); + } + if (pcb->snd_queuelen != 0) { + LWIP_ASSERT("tcp_enqueue: valid queue length", pcb->unacked != NULL || + pcb->unsent != NULL); + } + LWIP_DEBUGF(TCP_QLEN_DEBUG | DBG_STATE, ("tcp_enqueue: %"S16_F" (with mem err)\n", pcb->snd_queuelen)); + return ERR_MEM; +} + +/* find out what we can send and send it */ +err_t +tcp_output(struct tcp_pcb *pcb) +{ + struct pbuf *p; + struct tcp_hdr *tcphdr; + struct tcp_seg *seg, *useg; + u32_t wnd; +#if TCP_CWND_DEBUG + s16_t i = 0; +#endif /* TCP_CWND_DEBUG */ + + /* First, check if we are invoked by the TCP input processing + code. If so, we do not output anything. Instead, we rely on the + input processing code to call us when input processing is done + with. */ + if (tcp_input_pcb == pcb) { + return ERR_OK; + } + + wnd = LWIP_MIN(pcb->snd_wnd, pcb->cwnd); + + seg = pcb->unsent; + + /* useg should point to last segment on unacked queue */ + useg = pcb->unacked; + if (useg != NULL) { + for (; useg->next != NULL; useg = useg->next); + } + + /* If the TF_ACK_NOW flag is set and no data will be sent (either + * because the ->unsent queue is empty or because the window does + * not allow it), construct an empty ACK segment and send it. + * + * If data is to be sent, we will just piggyback the ACK (see below). + */ + if (pcb->flags & TF_ACK_NOW && + (seg == NULL || + ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len > wnd)) { + p = pbuf_alloc(PBUF_IP, TCP_HLEN, PBUF_RAM); + if (p == NULL) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: (ACK) could not allocate pbuf\n")); + return ERR_BUF; + } + LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: sending ACK for %"U32_F"\n", pcb->rcv_nxt)); + /* remove ACK flags from the PCB, as we send an empty ACK now */ + pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW); + + tcphdr = p->payload; + tcphdr->src = htons(pcb->local_port); + tcphdr->dest = htons(pcb->remote_port); + tcphdr->seqno = htonl(pcb->snd_nxt); + tcphdr->ackno = htonl(pcb->rcv_nxt); + TCPH_FLAGS_SET(tcphdr, TCP_ACK); + tcphdr->wnd = htons(pcb->rcv_wnd); + tcphdr->urgp = 0; + TCPH_HDRLEN_SET(tcphdr, 5); + + tcphdr->chksum = 0; +#if CHECKSUM_GEN_TCP + tcphdr->chksum = inet_chksum_pseudo(p, &(pcb->local_ip), &(pcb->remote_ip), + IP_PROTO_TCP, p->tot_len); +#endif + ip_output(p, &(pcb->local_ip), &(pcb->remote_ip), pcb->ttl, pcb->tos, + IP_PROTO_TCP); + pbuf_free(p); + + return ERR_OK; + } + +#if TCP_OUTPUT_DEBUG + if (seg == NULL) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: nothing to send (%p)\n", (void*)pcb->unsent)); + } +#endif /* TCP_OUTPUT_DEBUG */ +#if TCP_CWND_DEBUG + if (seg == NULL) { + LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %"U32_F", cwnd %"U16_F", wnd %"U32_F", seg == NULL, ack %"U32_F"\n", + pcb->snd_wnd, pcb->cwnd, wnd, + pcb->lastack)); + } else { + LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %"U32_F", cwnd %"U16_F", wnd %"U32_F", effwnd %"U32_F", seq %"U32_F", ack %"U32_F"\n", + pcb->snd_wnd, pcb->cwnd, wnd, + ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len, + ntohl(seg->tcphdr->seqno), pcb->lastack)); + } +#endif /* TCP_CWND_DEBUG */ + /* data available and window allows it to be sent? */ + while (seg != NULL && + ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len <= wnd) { +#if TCP_CWND_DEBUG + LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %"U32_F", cwnd %"U16_F", wnd %"U32_F", effwnd %"U32_F", seq %"U32_F", ack %"U32_F", i %"S16_F"\n", + pcb->snd_wnd, pcb->cwnd, wnd, + ntohl(seg->tcphdr->seqno) + seg->len - + pcb->lastack, + ntohl(seg->tcphdr->seqno), pcb->lastack, i)); + ++i; +#endif /* TCP_CWND_DEBUG */ + + pcb->unsent = seg->next; + + if (pcb->state != SYN_SENT) { + TCPH_SET_FLAG(seg->tcphdr, TCP_ACK); + pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW); + } + + tcp_output_segment(seg, pcb); + pcb->snd_nxt = ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg); + if (TCP_SEQ_LT(pcb->snd_max, pcb->snd_nxt)) { + pcb->snd_max = pcb->snd_nxt; + } + /* put segment on unacknowledged list if length > 0 */ + if (TCP_TCPLEN(seg) > 0) { + seg->next = NULL; + /* unacked list is empty? */ + if (pcb->unacked == NULL) { + pcb->unacked = seg; + useg = seg; + /* unacked list is not empty? */ + } else { + /* In the case of fast retransmit, the packet should not go to the tail + * of the unacked queue, but rather at the head. We need to check for + * this case. -STJ Jul 27, 2004 */ + if (TCP_SEQ_LT(ntohl(seg->tcphdr->seqno), ntohl(useg->tcphdr->seqno))){ + /* add segment to head of unacked list */ + seg->next = pcb->unacked; + pcb->unacked = seg; + } else { + /* add segment to tail of unacked list */ + useg->next = seg; + useg = useg->next; + } + } + /* do not queue empty segments on the unacked list */ + } else { + tcp_seg_free(seg); + } + seg = pcb->unsent; + } + return ERR_OK; +} + +/** + * Actually send a TCP segment over IP + */ +static void +tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb) +{ + u16_t len; + struct netif *netif; + + /** @bug Exclude retransmitted segments from this count. */ + snmp_inc_tcpoutsegs(); + + /* The TCP header has already been constructed, but the ackno and + wnd fields remain. */ + seg->tcphdr->ackno = htonl(pcb->rcv_nxt); + + /* silly window avoidance */ + if (pcb->rcv_wnd < pcb->mss) { + seg->tcphdr->wnd = 0; + } else { + /* advertise our receive window size in this TCP segment */ + seg->tcphdr->wnd = htons(pcb->rcv_wnd); + } + + /* If we don't have a local IP address, we get one by + calling ip_route(). */ + if (ip_addr_isany(&(pcb->local_ip))) { + netif = ip_route(&(pcb->remote_ip)); + if (netif == NULL) { + return; + } + ip_addr_set(&(pcb->local_ip), &(netif->ip_addr)); + } + + pcb->rtime = 0; + + if (pcb->rttest == 0) { + pcb->rttest = tcp_ticks; + pcb->rtseq = ntohl(seg->tcphdr->seqno); + + LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_output_segment: rtseq %"U32_F"\n", pcb->rtseq)); + } + LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output_segment: %"U32_F":%"U32_F"\n", + htonl(seg->tcphdr->seqno), htonl(seg->tcphdr->seqno) + + seg->len)); + + len = (u16_t)((u8_t *)seg->tcphdr - (u8_t *)seg->p->payload); + + seg->p->len -= len; + seg->p->tot_len -= len; + + seg->p->payload = seg->tcphdr; + + seg->tcphdr->chksum = 0; +#if CHECKSUM_GEN_TCP + seg->tcphdr->chksum = inet_chksum_pseudo(seg->p, + &(pcb->local_ip), + &(pcb->remote_ip), + IP_PROTO_TCP, seg->p->tot_len); +#endif + TCP_STATS_INC(tcp.xmit); + + ip_output(seg->p, &(pcb->local_ip), &(pcb->remote_ip), pcb->ttl, pcb->tos, + IP_PROTO_TCP); +} + +void +tcp_rst(u32_t seqno, u32_t ackno, + struct ip_addr *local_ip, struct ip_addr *remote_ip, + u16_t local_port, u16_t remote_port) +{ + struct pbuf *p; + struct tcp_hdr *tcphdr; + p = pbuf_alloc(PBUF_IP, TCP_HLEN, PBUF_RAM); + if (p == NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_rst: could not allocate memory for pbuf\n")); + return; + } + + tcphdr = p->payload; + tcphdr->src = htons(local_port); + tcphdr->dest = htons(remote_port); + tcphdr->seqno = htonl(seqno); + tcphdr->ackno = htonl(ackno); + TCPH_FLAGS_SET(tcphdr, TCP_RST | TCP_ACK); + tcphdr->wnd = htons(TCP_WND); + tcphdr->urgp = 0; + TCPH_HDRLEN_SET(tcphdr, 5); + + tcphdr->chksum = 0; +#if CHECKSUM_GEN_TCP + tcphdr->chksum = inet_chksum_pseudo(p, local_ip, remote_ip, + IP_PROTO_TCP, p->tot_len); +#endif + TCP_STATS_INC(tcp.xmit); + snmp_inc_tcpoutrsts(); + /* Send output with hardcoded TTL since we have no access to the pcb */ + ip_output(p, local_ip, remote_ip, TCP_TTL, 0, IP_PROTO_TCP); + pbuf_free(p); + LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_rst: seqno %"U32_F" ackno %"U32_F".\n", seqno, ackno)); +} + +/* requeue all unacked segments for retransmission */ +void +tcp_rexmit_rto(struct tcp_pcb *pcb) +{ + struct tcp_seg *seg; + + if (pcb->unacked == NULL) { + return; + } + + /* Move all unacked segments to the head of the unsent queue */ + for (seg = pcb->unacked; seg->next != NULL; seg = seg->next); + /* concatenate unsent queue after unacked queue */ + seg->next = pcb->unsent; + /* unsent queue is the concatenated queue (of unacked, unsent) */ + pcb->unsent = pcb->unacked; + /* unacked queue is now empty */ + pcb->unacked = NULL; + + pcb->snd_nxt = ntohl(pcb->unsent->tcphdr->seqno); + /* increment number of retransmissions */ + ++pcb->nrtx; + + /* Don't take any RTT measurements after retransmitting. */ + pcb->rttest = 0; + + /* Do the actual retransmission */ + tcp_output(pcb); +} + +void +tcp_rexmit(struct tcp_pcb *pcb) +{ + struct tcp_seg *seg; + + if (pcb->unacked == NULL) { + return; + } + + /* Move the first unacked segment to the unsent queue */ + seg = pcb->unacked->next; + pcb->unacked->next = pcb->unsent; + pcb->unsent = pcb->unacked; + pcb->unacked = seg; + + pcb->snd_nxt = ntohl(pcb->unsent->tcphdr->seqno); + + ++pcb->nrtx; + + /* Don't take any rtt measurements after retransmitting. */ + pcb->rttest = 0; + + /* Do the actual retransmission. */ + snmp_inc_tcpretranssegs(); + tcp_output(pcb); + +} + + +void +tcp_keepalive(struct tcp_pcb *pcb) +{ + struct pbuf *p; + struct tcp_hdr *tcphdr; + + LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: sending KEEPALIVE probe to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", + ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip), + ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip))); + + LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: tcp_ticks %"U32_F" pcb->tmr %"U32_F" pcb->keep_cnt %"U16_F"\n", tcp_ticks, pcb->tmr, pcb->keep_cnt)); + + p = pbuf_alloc(PBUF_IP, TCP_HLEN, PBUF_RAM); + + if(p == NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: could not allocate memory for pbuf\n")); + return; + } + + tcphdr = p->payload; + tcphdr->src = htons(pcb->local_port); + tcphdr->dest = htons(pcb->remote_port); + tcphdr->seqno = htonl(pcb->snd_nxt - 1); + tcphdr->ackno = htonl(pcb->rcv_nxt); + tcphdr->wnd = htons(pcb->rcv_wnd); + tcphdr->urgp = 0; + TCPH_HDRLEN_SET(tcphdr, 5); + + tcphdr->chksum = 0; +#if CHECKSUM_GEN_TCP + tcphdr->chksum = inet_chksum_pseudo(p, &pcb->local_ip, &pcb->remote_ip, IP_PROTO_TCP, p->tot_len); +#endif + TCP_STATS_INC(tcp.xmit); + + /* Send output to IP */ + ip_output(p, &pcb->local_ip, &pcb->remote_ip, pcb->ttl, 0, IP_PROTO_TCP); + + pbuf_free(p); + + LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_keepalive: seqno %"U32_F" ackno %"U32_F".\n", pcb->snd_nxt - 1, pcb->rcv_nxt)); +} + +#endif /* LWIP_TCP */ + + + + + + + + + diff --git a/20080212/Demo/Common/ethernet/lwIP/core/udp.c b/20080212/Demo/Common/ethernet/lwIP/core/udp.c new file mode 100644 index 000000000..3d5980f47 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/core/udp.c @@ -0,0 +1,665 @@ +/** + * @file + * User Datagram Protocol module + * + */ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + + +/* udp.c + * + * The code for the User Datagram Protocol UDP. + * + */ + +#include + +#include "lwip/opt.h" + +#include "lwip/def.h" +#include "lwip/memp.h" +#include "lwip/inet.h" +#include "lwip/ip_addr.h" +#include "lwip/netif.h" +#include "lwip/udp.h" +#include "lwip/icmp.h" + +#include "lwip/stats.h" + +#include "arch/perf.h" +#include "lwip/snmp.h" + +/* The list of UDP PCBs */ +#if LWIP_UDP +/* exported in udp.h (was static) */ +struct udp_pcb *udp_pcbs = NULL; + +static struct udp_pcb *pcb_cache = NULL; + +void +udp_init(void) +{ + udp_pcbs = pcb_cache = NULL; +} + +/** + * Process an incoming UDP datagram. + * + * Given an incoming UDP datagram (as a chain of pbufs) this function + * finds a corresponding UDP PCB and + * + * @param pbuf pbuf to be demultiplexed to a UDP PCB. + * @param netif network interface on which the datagram was received. + * + */ +void +udp_input(struct pbuf *p, struct netif *inp) +{ + struct udp_hdr *udphdr; + struct udp_pcb *pcb; + struct udp_pcb *uncon_pcb; + struct ip_hdr *iphdr; + u16_t src, dest; + u8_t local_match; + + PERF_START; + + UDP_STATS_INC(udp.recv); + + iphdr = p->payload; + + if (p->tot_len < (IPH_HL(iphdr) * 4 + UDP_HLEN)) { + /* drop short packets */ +// LWIP_DEBUGF(UDP_DEBUG, +// ("udp_input: short UDP datagram (%"U16_F" bytes) discarded\n", p->tot_len)); + + LWIP_DEBUGF(UDP_DEBUG, + ("udp_input: short UDP datagram (%u bytes) discarded\n", p->tot_len)); + + UDP_STATS_INC(udp.lenerr); + UDP_STATS_INC(udp.drop); + snmp_inc_udpinerrors(); + pbuf_free(p); + goto end; + } + + pbuf_header(p, -((s16_t)(IPH_HL(iphdr) * 4))); + + udphdr = (struct udp_hdr *)p->payload; + + LWIP_DEBUGF(UDP_DEBUG, ("udp_input: received datagram of length %"U16_F"\n", p->tot_len)); + + src = ntohs(udphdr->src); + dest = ntohs(udphdr->dest); + + udp_debug_print(udphdr); + + /* print the UDP source and destination */ + LWIP_DEBUGF(UDP_DEBUG, + ("udp (%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F") <-- " + "(%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F")\n", + ip4_addr1(&iphdr->dest), ip4_addr2(&iphdr->dest), + ip4_addr3(&iphdr->dest), ip4_addr4(&iphdr->dest), ntohs(udphdr->dest), + ip4_addr1(&iphdr->src), ip4_addr2(&iphdr->src), + ip4_addr3(&iphdr->src), ip4_addr4(&iphdr->src), ntohs(udphdr->src))); + + local_match = 0; + uncon_pcb = NULL; + /* Iterate through the UDP pcb list for a matching pcb */ + for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) { + /* print the PCB local and remote address */ + LWIP_DEBUGF(UDP_DEBUG, + ("pcb (%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F") --- " + "(%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F")\n", + ip4_addr1(&pcb->local_ip), ip4_addr2(&pcb->local_ip), + ip4_addr3(&pcb->local_ip), ip4_addr4(&pcb->local_ip), pcb->local_port, + ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip), + ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip), pcb->remote_port)); + + /* compare PCB local addr+port to UDP destination addr+port */ + if ((pcb->local_port == dest) && + (ip_addr_isany(&pcb->local_ip) || + ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest)) || + ip_addr_isbroadcast(&(iphdr->dest), inp))) { + local_match = 1; + if ((uncon_pcb == NULL) && + ((pcb->flags & UDP_FLAGS_CONNECTED) == 0)) { + /* the first unconnected matching PCB */ + uncon_pcb = pcb; + } + } + /* compare PCB remote addr+port to UDP source addr+port */ + if ((local_match != 0) && + (pcb->remote_port == src) && + (ip_addr_isany(&pcb->remote_ip) || + ip_addr_cmp(&(pcb->remote_ip), &(iphdr->src)))) { + /* the first fully matching PCB */ + break; + } + } + /* no fully matching pcb found? then look for an unconnected pcb */ + if (pcb == NULL) { + pcb = uncon_pcb; + } + + /* Check checksum if this is a match or if it was directed at us. */ + if (pcb != NULL || ip_addr_cmp(&inp->ip_addr, &iphdr->dest)) { + LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE, ("udp_input: calculating checksum\n")); +#ifdef IPv6 + if (iphdr->nexthdr == IP_PROTO_UDPLITE) { +#else + if (IPH_PROTO(iphdr) == IP_PROTO_UDPLITE) { +#endif /* IPv4 */ + /* Do the UDP Lite checksum */ +#if CHECKSUM_CHECK_UDP + if (inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src), + (struct ip_addr *)&(iphdr->dest), + IP_PROTO_UDPLITE, ntohs(udphdr->len)) != 0) { + LWIP_DEBUGF(UDP_DEBUG | 2, + ("udp_input: UDP Lite datagram discarded due to failing checksum\n")); + UDP_STATS_INC(udp.chkerr); + UDP_STATS_INC(udp.drop); + snmp_inc_udpinerrors(); + pbuf_free(p); + goto end; + } +#endif + } else { +#if CHECKSUM_CHECK_UDP + if (udphdr->chksum != 0) { + if (inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src), + (struct ip_addr *)&(iphdr->dest), + IP_PROTO_UDP, p->tot_len) != 0) { + LWIP_DEBUGF(UDP_DEBUG | 2, + ("udp_input: UDP datagram discarded due to failing checksum\n")); + UDP_STATS_INC(udp.chkerr); + UDP_STATS_INC(udp.drop); + snmp_inc_udpinerrors(); + pbuf_free(p); + goto end; + } + } +#endif + } + pbuf_header(p, -UDP_HLEN); + if (pcb != NULL) { + snmp_inc_udpindatagrams(); + /* callback */ + if (pcb->recv != NULL) + pcb->recv(pcb->recv_arg, pcb, p, &(iphdr->src), src); + } else { + LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE, ("udp_input: not for us.\n")); + + /* No match was found, send ICMP destination port unreachable unless + destination address was broadcast/multicast. */ + + if (!ip_addr_isbroadcast(&iphdr->dest, inp) && + !ip_addr_ismulticast(&iphdr->dest)) { + + /* restore pbuf pointer */ + p->payload = iphdr; + icmp_dest_unreach(p, ICMP_DUR_PORT); + } + UDP_STATS_INC(udp.proterr); + UDP_STATS_INC(udp.drop); + snmp_inc_udpnoports(); + pbuf_free(p); + } + } else { + pbuf_free(p); + } +end: + PERF_STOP("udp_input"); +} + +/** + * Send data to a specified address using UDP. + * + * @param pcb UDP PCB used to send the data. + * @param pbuf chain of pbuf's to be sent. + * @param dst_ip Destination IP address. + * @param dst_port Destination UDP port. + * + * If the PCB already has a remote address association, it will + * be restored after the data is sent. + * + * @return lwIP error code. + * - ERR_OK. Successful. No error occured. + * - ERR_MEM. Out of memory. + * - ERR_RTE. Could not find route to destination address. + * + * @see udp_disconnect() udp_send() + */ +err_t +udp_sendto(struct udp_pcb *pcb, struct pbuf *p, + struct ip_addr *dst_ip, u16_t dst_port) +{ + err_t err; + /* temporary space for current PCB remote address */ + struct ip_addr pcb_remote_ip; + u16_t pcb_remote_port; + /* remember current remote peer address of PCB */ + pcb_remote_ip.addr = pcb->remote_ip.addr; + pcb_remote_port = pcb->remote_port; + /* copy packet destination address to PCB remote peer address */ + pcb->remote_ip.addr = dst_ip->addr; + pcb->remote_port = dst_port; + /* send to the packet destination address */ + err = udp_send(pcb, p); + /* restore PCB remote peer address */ + pcb->remote_ip.addr = pcb_remote_ip.addr; + pcb->remote_port = pcb_remote_port; + return err; +} + +/** + * Send data using UDP. + * + * @param pcb UDP PCB used to send the data. + * @param pbuf chain of pbuf's to be sent. + * + * @return lwIP error code. + * - ERR_OK. Successful. No error occured. + * - ERR_MEM. Out of memory. + * - ERR_RTE. Could not find route to destination address. + * + * @see udp_disconnect() udp_sendto() + */ +err_t +udp_send(struct udp_pcb *pcb, struct pbuf *p) +{ + struct udp_hdr *udphdr; + struct netif *netif; + struct ip_addr *src_ip; + err_t err; + struct pbuf *q; /* q will be sent down the stack */ + + LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 3, ("udp_send\n")); + + /* if the PCB is not yet bound to a port, bind it here */ + if (pcb->local_port == 0) { + LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 2, ("udp_send: not yet bound to a port, binding now\n")); + err = udp_bind(pcb, &pcb->local_ip, pcb->local_port); + if (err != ERR_OK) { + LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 2, ("udp_send: forced port bind failed\n")); + return err; + } + } + /* find the outgoing network interface for this packet */ + netif = ip_route(&(pcb->remote_ip)); + /* no outgoing network interface could be found? */ + if (netif == NULL) { + LWIP_DEBUGF(UDP_DEBUG | 1, ("udp_send: No route to 0x%"X32_F"\n", pcb->remote_ip.addr)); + UDP_STATS_INC(udp.rterr); + return ERR_RTE; + } + + /* not enough space to add an UDP header to first pbuf in given p chain? */ + if (pbuf_header(p, UDP_HLEN)) { + /* allocate header in a seperate new pbuf */ + q = pbuf_alloc(PBUF_IP, UDP_HLEN, PBUF_RAM); + /* new header pbuf could not be allocated? */ + if (q == NULL) { + LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 2, ("udp_send: could not allocate header\n")); + return ERR_MEM; + } + /* chain header q in front of given pbuf p */ + pbuf_chain(q, p); + /* first pbuf q points to header pbuf */ + LWIP_DEBUGF(UDP_DEBUG, + ("udp_send: added header pbuf %p before given pbuf %p\n", (void *)q, (void *)p)); + /* adding a header within p succeeded */ + } else { + /* first pbuf q equals given pbuf */ + q = p; + LWIP_DEBUGF(UDP_DEBUG, ("udp_send: added header in given pbuf %p\n", (void *)p)); + } + /* q now represents the packet to be sent */ + udphdr = q->payload; + udphdr->src = htons(pcb->local_port); + udphdr->dest = htons(pcb->remote_port); + /* in UDP, 0 checksum means 'no checksum' */ + udphdr->chksum = 0x0000; + + /* PCB local address is IP_ANY_ADDR? */ + if (ip_addr_isany(&pcb->local_ip)) { + /* use outgoing network interface IP address as source address */ + src_ip = &(netif->ip_addr); + } else { + /* use UDP PCB local IP address as source address */ + src_ip = &(pcb->local_ip); + } + + LWIP_DEBUGF(UDP_DEBUG, ("udp_send: sending datagram of length %"U16_F"\n", q->tot_len)); + + /* UDP Lite protocol? */ + if (pcb->flags & UDP_FLAGS_UDPLITE) { + LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP LITE packet length %"U16_F"\n", q->tot_len)); + /* set UDP message length in UDP header */ + udphdr->len = htons(pcb->chksum_len); + /* calculate checksum */ +#if CHECKSUM_GEN_UDP + udphdr->chksum = inet_chksum_pseudo(q, src_ip, &(pcb->remote_ip), + IP_PROTO_UDP, pcb->chksum_len); + /* chksum zero must become 0xffff, as zero means 'no checksum' */ + if (udphdr->chksum == 0x0000) + udphdr->chksum = 0xffff; +#else + udphdr->chksum = 0x0000; +#endif + /* output to IP */ + LWIP_DEBUGF(UDP_DEBUG, ("udp_send: ip_output_if (,,,,IP_PROTO_UDPLITE,)\n")); + err = ip_output_if(q, src_ip, &pcb->remote_ip, pcb->ttl, pcb->tos, IP_PROTO_UDPLITE, netif); + } else { /* UDP */ + LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP packet length %"U16_F"\n", q->tot_len)); + udphdr->len = htons(q->tot_len); + /* calculate checksum */ +#if CHECKSUM_GEN_UDP + if ((pcb->flags & UDP_FLAGS_NOCHKSUM) == 0) { + udphdr->chksum = inet_chksum_pseudo(q, src_ip, &pcb->remote_ip, IP_PROTO_UDP, q->tot_len); + /* chksum zero must become 0xffff, as zero means 'no checksum' */ + if (udphdr->chksum == 0x0000) udphdr->chksum = 0xffff; + } +#else + udphdr->chksum = 0x0000; +#endif + LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP checksum 0x%04"X16_F"\n", udphdr->chksum)); + LWIP_DEBUGF(UDP_DEBUG, ("udp_send: ip_output_if (,,,,IP_PROTO_UDP,)\n")); + /* output to IP */ + err = ip_output_if(q, src_ip, &pcb->remote_ip, pcb->ttl, pcb->tos, IP_PROTO_UDP, netif); + } + /* TODO: must this be increased even if error occured? */ + snmp_inc_udpoutdatagrams(); + + /* did we chain a seperate header pbuf earlier? */ + if (q != p) { + /* free the header pbuf */ + pbuf_free(q); + q = NULL; + /* p is still referenced by the caller, and will live on */ + } + + UDP_STATS_INC(udp.xmit); + return err; +} + +/** + * Bind an UDP PCB. + * + * @param pcb UDP PCB to be bound with a local address ipaddr and port. + * @param ipaddr local IP address to bind with. Use IP_ADDR_ANY to + * bind to all local interfaces. + * @param port local UDP port to bind with. + * + * @return lwIP error code. + * - ERR_OK. Successful. No error occured. + * - ERR_USE. The specified ipaddr and port are already bound to by + * another UDP PCB. + * + * @see udp_disconnect() + */ +err_t +udp_bind(struct udp_pcb *pcb, struct ip_addr *ipaddr, u16_t port) +{ + struct udp_pcb *ipcb; + u8_t rebind; + + LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 3, ("udp_bind(ipaddr = ")); + ip_addr_debug_print(UDP_DEBUG, ipaddr); + LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 3, (", port = %"U16_F")\n", port)); + + rebind = 0; + /* Check for double bind and rebind of the same pcb */ + for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) { + /* is this UDP PCB already on active list? */ + if (pcb == ipcb) { + /* pcb may occur at most once in active list */ + LWIP_ASSERT("rebind == 0", rebind == 0); + /* pcb already in list, just rebind */ + rebind = 1; + } + + /* this code does not allow upper layer to share a UDP port for + listening to broadcast or multicast traffic (See SO_REUSE_ADDR and + SO_REUSE_PORT under *BSD). TODO: See where it fits instead, OR + combine with implementation of UDP PCB flags. Leon Woestenberg. */ +#ifdef LWIP_UDP_TODO + /* port matches that of PCB in list? */ + else + if ((ipcb->local_port == port) && + /* IP address matches, or one is IP_ADDR_ANY? */ + (ip_addr_isany(&(ipcb->local_ip)) || + ip_addr_isany(ipaddr) || + ip_addr_cmp(&(ipcb->local_ip), ipaddr))) { + /* other PCB already binds to this local IP and port */ + LWIP_DEBUGF(UDP_DEBUG, + ("udp_bind: local port %"U16_F" already bound by another pcb\n", port)); + return ERR_USE; + } +#endif + } + + ip_addr_set(&pcb->local_ip, ipaddr); + + /* no port specified? */ + if (port == 0) { +#ifndef UDP_LOCAL_PORT_RANGE_START +#define UDP_LOCAL_PORT_RANGE_START 4096 +#define UDP_LOCAL_PORT_RANGE_END 0x7fff +#endif + port = UDP_LOCAL_PORT_RANGE_START; + ipcb = udp_pcbs; + while ((ipcb != NULL) && (port != UDP_LOCAL_PORT_RANGE_END)) { + if (ipcb->local_port == port) { + port++; + ipcb = udp_pcbs; + } else + ipcb = ipcb->next; + } + if (ipcb != NULL) { + /* no more ports available in local range */ + LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: out of free UDP ports\n")); + return ERR_USE; + } + } + pcb->local_port = port; + snmp_insert_udpidx_tree(pcb); + /* pcb not active yet? */ + if (rebind == 0) { + /* place the PCB on the active list if not already there */ + pcb->next = udp_pcbs; + udp_pcbs = pcb; + } + LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | DBG_STATE, + ("udp_bind: bound to %"U16_F".%"U16_F".%"U16_F".%"U16_F", port %"U16_F"\n", + (u16_t)(ntohl(pcb->local_ip.addr) >> 24 & 0xff), + (u16_t)(ntohl(pcb->local_ip.addr) >> 16 & 0xff), + (u16_t)(ntohl(pcb->local_ip.addr) >> 8 & 0xff), + (u16_t)(ntohl(pcb->local_ip.addr) & 0xff), pcb->local_port)); + return ERR_OK; +} +/** + * Connect an UDP PCB. + * + * This will associate the UDP PCB with the remote address. + * + * @param pcb UDP PCB to be connected with remote address ipaddr and port. + * @param ipaddr remote IP address to connect with. + * @param port remote UDP port to connect with. + * + * @return lwIP error code + * + * @see udp_disconnect() + */ +err_t +udp_connect(struct udp_pcb *pcb, struct ip_addr *ipaddr, u16_t port) +{ + struct udp_pcb *ipcb; + + if (pcb->local_port == 0) { + err_t err = udp_bind(pcb, &pcb->local_ip, pcb->local_port); + if (err != ERR_OK) + return err; + } + + ip_addr_set(&pcb->remote_ip, ipaddr); + pcb->remote_port = port; + pcb->flags |= UDP_FLAGS_CONNECTED; +/** TODO: this functionality belongs in upper layers */ +#ifdef LWIP_UDP_TODO + /* Nail down local IP for netconn_addr()/getsockname() */ + if (ip_addr_isany(&pcb->local_ip) && !ip_addr_isany(&pcb->remote_ip)) { + struct netif *netif; + + if ((netif = ip_route(&(pcb->remote_ip))) == NULL) { + LWIP_DEBUGF(UDP_DEBUG, ("udp_connect: No route to 0x%lx\n", pcb->remote_ip.addr)); + UDP_STATS_INC(udp.rterr); + return ERR_RTE; + } + /** TODO: this will bind the udp pcb locally, to the interface which + is used to route output packets to the remote address. However, we + might want to accept incoming packets on any interface! */ + pcb->local_ip = netif->ip_addr; + } else if (ip_addr_isany(&pcb->remote_ip)) { + pcb->local_ip.addr = 0; + } +#endif + LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | DBG_STATE, + ("udp_connect: connected to %"U16_F".%"U16_F".%"U16_F".%"U16_F",port %"U16_F"\n", + (u16_t)(ntohl(pcb->remote_ip.addr) >> 24 & 0xff), + (u16_t)(ntohl(pcb->remote_ip.addr) >> 16 & 0xff), + (u16_t)(ntohl(pcb->remote_ip.addr) >> 8 & 0xff), + (u16_t)(ntohl(pcb->remote_ip.addr) & 0xff), pcb->remote_port)); + + /* Insert UDP PCB into the list of active UDP PCBs. */ + for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) { + if (pcb == ipcb) { + /* already on the list, just return */ + return ERR_OK; + } + } + /* PCB not yet on the list, add PCB now */ + pcb->next = udp_pcbs; + udp_pcbs = pcb; + return ERR_OK; +} + +void +udp_disconnect(struct udp_pcb *pcb) +{ + /* reset remote address association */ + ip_addr_set(&pcb->remote_ip, IP_ADDR_ANY); + pcb->remote_port = 0; + /* mark PCB as unconnected */ + pcb->flags &= ~UDP_FLAGS_CONNECTED; +} + +void +udp_recv(struct udp_pcb *pcb, + void (* recv)(void *arg, struct udp_pcb *upcb, struct pbuf *p, + struct ip_addr *addr, u16_t port), + void *recv_arg) +{ + /* remember recv() callback and user data */ + pcb->recv = recv; + pcb->recv_arg = recv_arg; +} + +/** + * Remove an UDP PCB. + * + * @param pcb UDP PCB to be removed. The PCB is removed from the list of + * UDP PCB's and the data structure is freed from memory. + * + * @see udp_new() + */ +void +udp_remove(struct udp_pcb *pcb) +{ + struct udp_pcb *pcb2; + + snmp_delete_udpidx_tree(pcb); + /* pcb to be removed is first in list? */ + if (udp_pcbs == pcb) { + /* make list start at 2nd pcb */ + udp_pcbs = udp_pcbs->next; + /* pcb not 1st in list */ + } else + for (pcb2 = udp_pcbs; pcb2 != NULL; pcb2 = pcb2->next) { + /* find pcb in udp_pcbs list */ + if (pcb2->next != NULL && pcb2->next == pcb) { + /* remove pcb from list */ + pcb2->next = pcb->next; + } + } + memp_free(MEMP_UDP_PCB, pcb); +} + +/** + * Create a UDP PCB. + * + * @return The UDP PCB which was created. NULL if the PCB data structure + * could not be allocated. + * + * @see udp_remove() + */ +struct udp_pcb * +udp_new(void) +{ + struct udp_pcb *pcb; + pcb = memp_malloc(MEMP_UDP_PCB); + /* could allocate UDP PCB? */ + if (pcb != NULL) { + /* initialize PCB to all zeroes */ + memset(pcb, 0, sizeof(struct udp_pcb)); + pcb->ttl = UDP_TTL; + } + return pcb; +} + +#if UDP_DEBUG +void +udp_debug_print(struct udp_hdr *udphdr) +{ + LWIP_DEBUGF(UDP_DEBUG, ("UDP header:\n")); + LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(UDP_DEBUG, ("| %5"U16_F" | %5"U16_F" | (src port, dest port)\n", + ntohs(udphdr->src), ntohs(udphdr->dest))); + LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(UDP_DEBUG, ("| %5"U16_F" | 0x%04"X16_F" | (len, chksum)\n", + ntohs(udphdr->len), ntohs(udphdr->chksum))); + LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n")); +} +#endif /* UDP_DEBUG */ + +#endif /* LWIP_UDP */ diff --git a/20080212/Demo/Common/ethernet/lwIP/include/ipv4/lwip/icmp.h b/20080212/Demo/Common/ethernet/lwIP/include/ipv4/lwip/icmp.h new file mode 100644 index 000000000..04307e743 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/include/ipv4/lwip/icmp.h @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_ICMP_H__ +#define __LWIP_ICMP_H__ + +#include "lwip/arch.h" + +#include "lwip/opt.h" +#include "lwip/pbuf.h" + +#include "lwip/ip_addr.h" +#include "lwip/netif.h" + +#define ICMP_ER 0 /* echo reply */ +#define ICMP_DUR 3 /* destination unreachable */ +#define ICMP_SQ 4 /* source quench */ +#define ICMP_RD 5 /* redirect */ +#define ICMP_ECHO 8 /* echo */ +#define ICMP_TE 11 /* time exceeded */ +#define ICMP_PP 12 /* parameter problem */ +#define ICMP_TS 13 /* timestamp */ +#define ICMP_TSR 14 /* timestamp reply */ +#define ICMP_IRQ 15 /* information request */ +#define ICMP_IR 16 /* information reply */ + +enum icmp_dur_type { + ICMP_DUR_NET = 0, /* net unreachable */ + ICMP_DUR_HOST = 1, /* host unreachable */ + ICMP_DUR_PROTO = 2, /* protocol unreachable */ + ICMP_DUR_PORT = 3, /* port unreachable */ + ICMP_DUR_FRAG = 4, /* fragmentation needed and DF set */ + ICMP_DUR_SR = 5 /* source route failed */ +}; + +enum icmp_te_type { + ICMP_TE_TTL = 0, /* time to live exceeded in transit */ + ICMP_TE_FRAG = 1 /* fragment reassembly time exceeded */ +}; + +void icmp_input(struct pbuf *p, struct netif *inp); + +void icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t); +void icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t); + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct icmp_echo_hdr { + PACK_STRUCT_FIELD(u16_t _type_code); + PACK_STRUCT_FIELD(u16_t chksum); + PACK_STRUCT_FIELD(u16_t id); + PACK_STRUCT_FIELD(u16_t seqno); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END + +PACK_STRUCT_BEGIN +struct icmp_dur_hdr { + PACK_STRUCT_FIELD(u16_t _type_code); + PACK_STRUCT_FIELD(u16_t chksum); + PACK_STRUCT_FIELD(u32_t unused); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END + +PACK_STRUCT_BEGIN +struct icmp_te_hdr { + PACK_STRUCT_FIELD(u16_t _type_code); + PACK_STRUCT_FIELD(u16_t chksum); + PACK_STRUCT_FIELD(u32_t unused); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#define ICMPH_TYPE(hdr) (ntohs((hdr)->_type_code) >> 8) +#define ICMPH_CODE(hdr) (ntohs((hdr)->_type_code) & 0xff) + +#define ICMPH_TYPE_SET(hdr, type) ((hdr)->_type_code = htons(ICMPH_CODE(hdr) | ((type) << 8))) +#define ICMPH_CODE_SET(hdr, code) ((hdr)->_type_code = htons((code) | (ICMPH_TYPE(hdr) << 8))) + +#endif /* __LWIP_ICMP_H__ */ + diff --git a/20080212/Demo/Common/ethernet/lwIP/include/ipv4/lwip/inet.h b/20080212/Demo/Common/ethernet/lwIP/include/ipv4/lwip/inet.h new file mode 100644 index 000000000..9e77b74c3 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/include/ipv4/lwip/inet.h @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_INET_H__ +#define __LWIP_INET_H__ + +#include "lwip/arch.h" + +#include "lwip/opt.h" +#include "lwip/pbuf.h" +#include "lwip/ip_addr.h" + +u16_t inet_chksum(void *dataptr, u16_t len); +#if 0 /* optimized routine */ +u16_t inet_chksum4(u8_t *dataptr, u16_t len); +#endif +u16_t inet_chksum_pbuf(struct pbuf *p); +u16_t inet_chksum_pseudo(struct pbuf *p, + struct ip_addr *src, struct ip_addr *dest, + u8_t proto, u16_t proto_len); + +u32_t inet_addr(const char *cp); +int inet_aton(const char *cp, struct in_addr *addr); +char *inet_ntoa(struct in_addr addr); /* returns ptr to static buffer; not reentrant! */ + +#ifdef htons +#undef htons +#endif /* htons */ +#ifdef htonl +#undef htonl +#endif /* htonl */ +#ifdef ntohs +#undef ntohs +#endif /* ntohs */ +#ifdef ntohl +#undef ntohl +#endif /* ntohl */ + +#ifndef LWIP_PLATFORM_BYTESWAP +#define LWIP_PLATFORM_BYTESWAP 0 +#endif + +#if BYTE_ORDER == BIG_ENDIAN +#define htons(x) (x) +#define ntohs(x) (x) +#define htonl(x) (x) +#define ntohl(x) (x) +#else /* BYTE_ORDER != BIG_ENDIAN */ +#ifdef LWIP_PREFIX_BYTEORDER_FUNCS +/* workaround for naming collisions on some platforms */ +#define htons lwip_htons +#define ntohs lwip_ntohs +#define htonl lwip_htonl +#define ntohl lwip_ntohl +#endif +#if LWIP_PLATFORM_BYTESWAP +#define htons(x) LWIP_PLATFORM_HTONS(x) +#define ntohs(x) LWIP_PLATFORM_HTONS(x) +#define htonl(x) LWIP_PLATFORM_HTONL(x) +#define ntohl(x) LWIP_PLATFORM_HTONL(x) +#else +u16_t htons(u16_t x); +u16_t ntohs(u16_t x); +u32_t htonl(u32_t x); +u32_t ntohl(u32_t x); +#endif + +#endif + +#endif /* __LWIP_INET_H__ */ + diff --git a/20080212/Demo/Common/ethernet/lwIP/include/ipv4/lwip/ip.h b/20080212/Demo/Common/ethernet/lwIP/include/ipv4/lwip/ip.h new file mode 100644 index 000000000..e5a8da0a9 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/include/ipv4/lwip/ip.h @@ -0,0 +1,154 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_IP_H__ +#define __LWIP_IP_H__ + +#include "lwip/arch.h" + +#include "lwip/def.h" +#include "lwip/pbuf.h" +#include "lwip/ip_addr.h" + +#include "lwip/err.h" + + +void ip_init(void); +struct netif *ip_route(struct ip_addr *dest); +err_t ip_input(struct pbuf *p, struct netif *inp); +err_t ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, + u8_t ttl, u8_t tos, u8_t proto); +err_t ip_output_if(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, + u8_t ttl, u8_t tos, u8_t proto, + struct netif *netif); + +#define IP_HLEN 20 + +#define IP_PROTO_ICMP 1 +#define IP_PROTO_UDP 17 +#define IP_PROTO_UDPLITE 136 +#define IP_PROTO_TCP 6 + +/* This is passed as the destination address to ip_output_if (not + to ip_output), meaning that an IP header already is constructed + in the pbuf. This is used when TCP retransmits. */ +#ifdef IP_HDRINCL +#undef IP_HDRINCL +#endif /* IP_HDRINCL */ +#define IP_HDRINCL NULL + + +/* This is the common part of all PCB types. It needs to be at the + beginning of a PCB type definition. It is located here so that + changes to this common part are made in one location instead of + having to change all PCB structs. */ +#define IP_PCB struct ip_addr local_ip; \ + struct ip_addr remote_ip; \ + /* Socket options */ \ + u16_t so_options; \ + /* Type Of Service */ \ + u8_t tos; \ + /* Time To Live */ \ + u8_t ttl + +/* + * Option flags per-socket. These are the same like SO_XXX. + */ +#define SOF_DEBUG (u16_t)0x0001U /* turn on debugging info recording */ +#define SOF_ACCEPTCONN (u16_t)0x0002U /* socket has had listen() */ +#define SOF_REUSEADDR (u16_t)0x0004U /* allow local address reuse */ +#define SOF_KEEPALIVE (u16_t)0x0008U /* keep connections alive */ +#define SOF_DONTROUTE (u16_t)0x0010U /* just use interface addresses */ +#define SOF_BROADCAST (u16_t)0x0020U /* permit sending of broadcast msgs */ +#define SOF_USELOOPBACK (u16_t)0x0040U /* bypass hardware when possible */ +#define SOF_LINGER (u16_t)0x0080U /* linger on close if data present */ +#define SOF_OOBINLINE (u16_t)0x0100U /* leave received OOB data in line */ +#define SOF_REUSEPORT (u16_t)0x0200U /* allow local address & port reuse */ + + + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct ip_hdr { + /* version / header length / type of service */ + PACK_STRUCT_FIELD(u16_t _v_hl_tos); + /* total length */ + PACK_STRUCT_FIELD(u16_t _len); + /* identification */ + PACK_STRUCT_FIELD(u16_t _id); + /* fragment offset field */ + PACK_STRUCT_FIELD(u16_t _offset); +#define IP_RF 0x8000 /* reserved fragment flag */ +#define IP_DF 0x4000 /* dont fragment flag */ +#define IP_MF 0x2000 /* more fragments flag */ +#define IP_OFFMASK 0x1fff /* mask for fragmenting bits */ + /* time to live / protocol*/ + PACK_STRUCT_FIELD(u16_t _ttl_proto); + /* checksum */ + PACK_STRUCT_FIELD(u16_t _chksum); + /* source and destination IP addresses */ + PACK_STRUCT_FIELD(struct ip_addr src); + PACK_STRUCT_FIELD(struct ip_addr dest); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#define IPH_V(hdr) (ntohs((hdr)->_v_hl_tos) >> 12) +#define IPH_HL(hdr) ((ntohs((hdr)->_v_hl_tos) >> 8) & 0x0f) +#define IPH_TOS(hdr) (ntohs((hdr)->_v_hl_tos) & 0xff) +#define IPH_LEN(hdr) ((hdr)->_len) +#define IPH_ID(hdr) ((hdr)->_id) +#define IPH_OFFSET(hdr) ((hdr)->_offset) +#define IPH_TTL(hdr) (ntohs((hdr)->_ttl_proto) >> 8) +#define IPH_PROTO(hdr) (ntohs((hdr)->_ttl_proto) & 0xff) +#define IPH_CHKSUM(hdr) ((hdr)->_chksum) + +#define IPH_VHLTOS_SET(hdr, v, hl, tos) (hdr)->_v_hl_tos = (htons(((v) << 12) | ((hl) << 8) | (tos))) +#define IPH_LEN_SET(hdr, len) (hdr)->_len = (len) +#define IPH_ID_SET(hdr, id) (hdr)->_id = (id) +#define IPH_OFFSET_SET(hdr, off) (hdr)->_offset = (off) +#define IPH_TTL_SET(hdr, ttl) (hdr)->_ttl_proto = (htons(IPH_PROTO(hdr) | ((u16_t)(ttl) << 8))) +#define IPH_PROTO_SET(hdr, proto) (hdr)->_ttl_proto = (htons((proto) | (IPH_TTL(hdr) << 8))) +#define IPH_CHKSUM_SET(hdr, chksum) (hdr)->_chksum = (chksum) + +#if IP_DEBUG +void ip_debug_print(struct pbuf *p); +#else +#define ip_debug_print(p) +#endif /* IP_DEBUG */ + +#endif /* __LWIP_IP_H__ */ + + diff --git a/20080212/Demo/Common/ethernet/lwIP/include/ipv4/lwip/ip_addr.h b/20080212/Demo/Common/ethernet/lwIP/include/ipv4/lwip/ip_addr.h new file mode 100644 index 000000000..1f0f75481 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/include/ipv4/lwip/ip_addr.h @@ -0,0 +1,160 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_IP_ADDR_H__ +#define __LWIP_IP_ADDR_H__ + +#include "lwip/arch.h" + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct ip_addr { + PACK_STRUCT_FIELD(u32_t addr); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +/* + * struct ipaddr2 is used in the definition of the ARP packet format in + * order to support compilers that don't have structure packing. + */ +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct ip_addr2 { + PACK_STRUCT_FIELD(u16_t addrw[2]); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +/* For compatibility with BSD code */ +struct in_addr { + u32_t s_addr; +}; + +struct netif; + +extern const struct ip_addr ip_addr_any; +extern const struct ip_addr ip_addr_broadcast; + +/** IP_ADDR_ can be used as a fixed IP address + * for the wildcard and the broadcast address + */ +#define IP_ADDR_ANY ((struct ip_addr *)&ip_addr_any) +#define IP_ADDR_BROADCAST ((struct ip_addr *)&ip_addr_broadcast) + +#define INADDR_NONE ((u32_t)0xffffffff) /* 255.255.255.255 */ +#define INADDR_LOOPBACK ((u32_t)0x7f000001) /* 127.0.0.1 */ + +/* Definitions of the bits in an Internet address integer. + + On subnets, host and network parts are found according to + the subnet mask, not these masks. */ + +#define IN_CLASSA(a) ((((u32_t)(a)) & 0x80000000) == 0) +#define IN_CLASSA_NET 0xff000000 +#define IN_CLASSA_NSHIFT 24 +#define IN_CLASSA_HOST (0xffffffff & ~IN_CLASSA_NET) +#define IN_CLASSA_MAX 128 + +#define IN_CLASSB(a) ((((u32_t)(a)) & 0xc0000000) == 0x80000000) +#define IN_CLASSB_NET 0xffff0000 +#define IN_CLASSB_NSHIFT 16 +#define IN_CLASSB_HOST (0xffffffff & ~IN_CLASSB_NET) +#define IN_CLASSB_MAX 65536 + +#define IN_CLASSC(a) ((((u32_t)(a)) & 0xe0000000) == 0xc0000000) +#define IN_CLASSC_NET 0xffffff00 +#define IN_CLASSC_NSHIFT 8 +#define IN_CLASSC_HOST (0xffffffff & ~IN_CLASSC_NET) + +#define IN_CLASSD(a) (((u32_t)(a) & 0xf0000000) == 0xe0000000) +#define IN_CLASSD_NET 0xf0000000 /* These ones aren't really */ +#define IN_CLASSD_NSHIFT 28 /* net and host fields, but */ +#define IN_CLASSD_HOST 0x0fffffff /* routing needn't know. */ +#define IN_MULTICAST(a) IN_CLASSD(a) + +#define IN_EXPERIMENTAL(a) (((u32_t)(a) & 0xf0000000) == 0xf0000000) +#define IN_BADCLASS(a) (((u32_t)(a) & 0xf0000000) == 0xf0000000) + +#define IN_LOOPBACKNET 127 /* official! */ + +#define IP4_ADDR(ipaddr, a,b,c,d) \ + (ipaddr)->addr = htonl(((u32_t)((a) & 0xff) << 24) | \ + ((u32_t)((b) & 0xff) << 16) | \ + ((u32_t)((c) & 0xff) << 8) | \ + (u32_t)((d) & 0xff)) + +#define ip_addr_set(dest, src) (dest)->addr = \ + ((src) == NULL? 0:\ + (src)->addr) +/** + * Determine if two address are on the same network. + * + * @arg addr1 IP address 1 + * @arg addr2 IP address 2 + * @arg mask network identifier mask + * @return !0 if the network identifiers of both address match + */ +#define ip_addr_netcmp(addr1, addr2, mask) (((addr1)->addr & \ + (mask)->addr) == \ + ((addr2)->addr & \ + (mask)->addr)) +#define ip_addr_cmp(addr1, addr2) ((addr1)->addr == (addr2)->addr) + +#define ip_addr_isany(addr1) ((addr1) == NULL || (addr1)->addr == 0) + +u8_t ip_addr_isbroadcast(struct ip_addr *, struct netif *); + +#define ip_addr_ismulticast(addr1) (((addr1)->addr & ntohl(0xf0000000)) == ntohl(0xe0000000)) + +#define ip_addr_debug_print(debug, ipaddr) \ + LWIP_DEBUGF(debug, ("%"U16_F".%"U16_F".%"U16_F".%"U16_F, \ + ipaddr ? (u16_t)(ntohl((ipaddr)->addr) >> 24) & 0xff : 0, \ + ipaddr ? (u16_t)(ntohl((ipaddr)->addr) >> 16) & 0xff : 0, \ + ipaddr ? (u16_t)(ntohl((ipaddr)->addr) >> 8) & 0xff : 0, \ + ipaddr ? (u16_t)ntohl((ipaddr)->addr) & 0xff : 0)) + +/* These are cast to u16_t, with the intent that they are often arguments + * to printf using the U16_F format from cc.h. */ +#define ip4_addr1(ipaddr) ((u16_t)(ntohl((ipaddr)->addr) >> 24) & 0xff) +#define ip4_addr2(ipaddr) ((u16_t)(ntohl((ipaddr)->addr) >> 16) & 0xff) +#define ip4_addr3(ipaddr) ((u16_t)(ntohl((ipaddr)->addr) >> 8) & 0xff) +#define ip4_addr4(ipaddr) ((u16_t)(ntohl((ipaddr)->addr)) & 0xff) + +#endif /* __LWIP_IP_ADDR_H__ */ diff --git a/20080212/Demo/Common/ethernet/lwIP/include/ipv4/lwip/ip_frag.h b/20080212/Demo/Common/ethernet/lwIP/include/ipv4/lwip/ip_frag.h new file mode 100644 index 000000000..30be1a8f2 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/include/ipv4/lwip/ip_frag.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Jani Monoses + * + */ + +#ifndef __LWIP_IP_FRAG_H__ +#define __LWIP_IP_FRAG_H__ + +#include "lwip/opt.h" +#include "lwip/err.h" +#include "lwip/pbuf.h" +#include "lwip/netif.h" +#include "lwip/ip_addr.h" + +void ip_frag_init(void); +void ip_reass_tmr(void); +struct pbuf * ip_reass(struct pbuf *p); +err_t ip_frag(struct pbuf *p, struct netif *netif, struct ip_addr *dest); + +#endif /* __LWIP_IP_FRAG_H__ */ + + diff --git a/20080212/Demo/Common/ethernet/lwIP/include/lwip/api.h b/20080212/Demo/Common/ethernet/lwIP/include/lwip/api.h new file mode 100644 index 000000000..1059eca2e --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/include/lwip/api.h @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_API_H__ +#define __LWIP_API_H__ + +#include "lwip/opt.h" +#include "lwip/pbuf.h" +#include "lwip/sys.h" + +#include "lwip/ip.h" + +#include "lwip/raw.h" +#include "lwip/udp.h" +#include "lwip/tcp.h" + +#include "lwip/err.h" + +#define NETCONN_NOCOPY 0x00 +#define NETCONN_COPY 0x01 + +enum netconn_type { + NETCONN_TCP, + NETCONN_UDP, + NETCONN_UDPLITE, + NETCONN_UDPNOCHKSUM, + NETCONN_RAW +}; + +enum netconn_state { + NETCONN_NONE, + NETCONN_WRITE, + NETCONN_ACCEPT, + NETCONN_RECV, + NETCONN_CONNECT, + NETCONN_CLOSE +}; + +enum netconn_evt { + NETCONN_EVT_RCVPLUS, + NETCONN_EVT_RCVMINUS, + NETCONN_EVT_SENDPLUS, + NETCONN_EVT_SENDMINUS +}; + +struct netbuf { + struct pbuf *p, *ptr; + struct ip_addr *fromaddr; + u16_t fromport; + err_t err; +}; + +struct netconn { + enum netconn_type type; + enum netconn_state state; + union { + struct tcp_pcb *tcp; + struct udp_pcb *udp; + struct raw_pcb *raw; + } pcb; + err_t err; + sys_mbox_t mbox; + sys_mbox_t recvmbox; + sys_mbox_t acceptmbox; + sys_sem_t sem; + int socket; + u16_t recv_avail; + void (* callback)(struct netconn *, enum netconn_evt, u16_t len); +}; + +/* Network buffer functions: */ +struct netbuf * netbuf_new (void); +void netbuf_delete (struct netbuf *buf); +void * netbuf_alloc (struct netbuf *buf, u16_t size); +void netbuf_free (struct netbuf *buf); +void netbuf_ref (struct netbuf *buf, + void *dataptr, u16_t size); +void netbuf_chain (struct netbuf *head, + struct netbuf *tail); + +u16_t netbuf_len (struct netbuf *buf); +err_t netbuf_data (struct netbuf *buf, + void **dataptr, u16_t *len); +s8_t netbuf_next (struct netbuf *buf); +void netbuf_first (struct netbuf *buf); + +void netbuf_copy (struct netbuf *buf, + void *dataptr, u16_t len); +void netbuf_copy_partial(struct netbuf *buf, void *dataptr, + u16_t len, u16_t offset); +struct ip_addr * netbuf_fromaddr (struct netbuf *buf); +u16_t netbuf_fromport (struct netbuf *buf); + +/* Network connection functions: */ +struct netconn * netconn_new (enum netconn_type type); +struct +netconn *netconn_new_with_callback(enum netconn_type t, + void (*callback)(struct netconn *, enum netconn_evt, u16_t len)); +struct +netconn *netconn_new_with_proto_and_callback(enum netconn_type t, u16_t proto, + void (*callback)(struct netconn *, enum netconn_evt, u16_t len)); +err_t netconn_delete (struct netconn *conn); +enum netconn_type netconn_type (struct netconn *conn); +err_t netconn_peer (struct netconn *conn, + struct ip_addr *addr, + u16_t *port); +err_t netconn_addr (struct netconn *conn, + struct ip_addr **addr, + u16_t *port); +err_t netconn_bind (struct netconn *conn, + struct ip_addr *addr, + u16_t port); +err_t netconn_connect (struct netconn *conn, + struct ip_addr *addr, + u16_t port); +err_t netconn_disconnect (struct netconn *conn); +err_t netconn_listen (struct netconn *conn); +struct netconn * netconn_accept (struct netconn *conn); +struct netbuf * netconn_recv (struct netconn *conn); +err_t netconn_send (struct netconn *conn, + struct netbuf *buf); +err_t netconn_write (struct netconn *conn, + void *dataptr, u16_t size, + u8_t copy); +err_t netconn_close (struct netconn *conn); + +err_t netconn_err (struct netconn *conn); + +#endif /* __LWIP_API_H__ */ + + diff --git a/20080212/Demo/Common/ethernet/lwIP/include/lwip/api_msg.h b/20080212/Demo/Common/ethernet/lwIP/include/lwip/api_msg.h new file mode 100644 index 000000000..87f3db5f1 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/include/lwip/api_msg.h @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_API_MSG_H__ +#define __LWIP_API_MSG_H__ + +#include "lwip/opt.h" +#include "lwip/pbuf.h" +#include "lwip/sys.h" + +#include "lwip/ip.h" + +#include "lwip/udp.h" +#include "lwip/tcp.h" + +#include "lwip/api.h" + +enum api_msg_type { + API_MSG_NEWCONN, + API_MSG_DELCONN, + + API_MSG_BIND, + API_MSG_CONNECT, + API_MSG_DISCONNECT, + + API_MSG_LISTEN, + API_MSG_ACCEPT, + + API_MSG_SEND, + API_MSG_RECV, + API_MSG_WRITE, + + API_MSG_CLOSE, + + API_MSG_MAX +}; + +struct api_msg_msg { + struct netconn *conn; + enum netconn_type conntype; + union { + struct pbuf *p; + struct { + struct ip_addr *ipaddr; + u16_t port; + } bc; + struct { + void *dataptr; + u16_t len; + u8_t copy; + } w; + sys_mbox_t mbox; + u16_t len; + } msg; +}; + +struct api_msg { + enum api_msg_type type; + struct api_msg_msg msg; +}; + +void api_msg_input(struct api_msg *msg); +void api_msg_post(struct api_msg *msg); + +#endif /* __LWIP_API_MSG_H__ */ + diff --git a/20080212/Demo/Common/ethernet/lwIP/include/lwip/arch.h b/20080212/Demo/Common/ethernet/lwIP/include/lwip/arch.h new file mode 100644 index 000000000..b43dd6445 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/include/lwip/arch.h @@ -0,0 +1,218 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_ARCH_H__ +#define __LWIP_ARCH_H__ + +#ifndef LITTLE_ENDIAN +#define LITTLE_ENDIAN 1234 +#endif + +#ifndef BIG_ENDIAN +#define BIG_ENDIAN 4321 +#endif + +#include "arch/cc.h" + +#ifndef PACK_STRUCT_BEGIN +#define PACK_STRUCT_BEGIN +#endif /* PACK_STRUCT_BEGIN */ + +#ifndef PACK_STRUCT_END +#define PACK_STRUCT_END +#endif /* PACK_STRUCT_END */ + +#ifndef PACK_STRUCT_FIELD +#define PACK_STRUCT_FIELD(x) x +#endif /* PACK_STRUCT_FIELD */ + +#ifndef PACK_STRUCT_STRUCT +#define PACK_STRUCT_STRUCT +#endif /* PACK_STRUCT_STRUCT */ + +#ifdef LWIP_PROVIDE_ERRNO + +#define EPERM 1 /* Operation not permitted */ +#define ENOENT 2 /* No such file or directory */ +#define ESRCH 3 /* No such process */ +#define EINTR 4 /* Interrupted system call */ +#define EIO 5 /* I/O error */ +#define ENXIO 6 /* No such device or address */ +#define E2BIG 7 /* Arg list too long */ +#define ENOEXEC 8 /* Exec format error */ +#define EBADF 9 /* Bad file number */ +#define ECHILD 10 /* No child processes */ +#define EAGAIN 11 /* Try again */ +#define ENOMEM 12 /* Out of memory */ +#define EACCES 13 /* Permission denied */ +#define EFAULT 14 /* Bad address */ +#define ENOTBLK 15 /* Block device required */ +#define EBUSY 16 /* Device or resource busy */ +#define EEXIST 17 /* File exists */ +#define EXDEV 18 /* Cross-device link */ +#define ENODEV 19 /* No such device */ +#define ENOTDIR 20 /* Not a directory */ +#define EISDIR 21 /* Is a directory */ +#define EINVAL 22 /* Invalid argument */ +#define ENFILE 23 /* File table overflow */ +#define EMFILE 24 /* Too many open files */ +#define ENOTTY 25 /* Not a typewriter */ +#define ETXTBSY 26 /* Text file busy */ +#define EFBIG 27 /* File too large */ +#define ENOSPC 28 /* No space left on device */ +#define ESPIPE 29 /* Illegal seek */ +#define EROFS 30 /* Read-only file system */ +#define EMLINK 31 /* Too many links */ +#define EPIPE 32 /* Broken pipe */ +#define EDOM 33 /* Math argument out of domain of func */ +#define ERANGE 34 /* Math result not representable */ +#define EDEADLK 35 /* Resource deadlock would occur */ +#define ENAMETOOLONG 36 /* File name too long */ +#define ENOLCK 37 /* No record locks available */ +#define ENOSYS 38 /* Function not implemented */ +#define ENOTEMPTY 39 /* Directory not empty */ +#define ELOOP 40 /* Too many symbolic links encountered */ +#define EWOULDBLOCK EAGAIN /* Operation would block */ +#define ENOMSG 42 /* No message of desired type */ +#define EIDRM 43 /* Identifier removed */ +#define ECHRNG 44 /* Channel number out of range */ +#define EL2NSYNC 45 /* Level 2 not synchronized */ +#define EL3HLT 46 /* Level 3 halted */ +#define EL3RST 47 /* Level 3 reset */ +#define ELNRNG 48 /* Link number out of range */ +#define EUNATCH 49 /* Protocol driver not attached */ +#define ENOCSI 50 /* No CSI structure available */ +#define EL2HLT 51 /* Level 2 halted */ +#define EBADE 52 /* Invalid exchange */ +#define EBADR 53 /* Invalid request descriptor */ +#define EXFULL 54 /* Exchange full */ +#define ENOANO 55 /* No anode */ +#define EBADRQC 56 /* Invalid request code */ +#define EBADSLT 57 /* Invalid slot */ + +#define EDEADLOCK EDEADLK + +#define EBFONT 59 /* Bad font file format */ +#define ENOSTR 60 /* Device not a stream */ +#define ENODATA 61 /* No data available */ +#define ETIME 62 /* Timer expired */ +#define ENOSR 63 /* Out of streams resources */ +#define ENONET 64 /* Machine is not on the network */ +#define ENOPKG 65 /* Package not installed */ +#define EREMOTE 66 /* Object is remote */ +#define ENOLINK 67 /* Link has been severed */ +#define EADV 68 /* Advertise error */ +#define ESRMNT 69 /* Srmount error */ +#define ECOMM 70 /* Communication error on send */ +#define EPROTO 71 /* Protocol error */ +#define EMULTIHOP 72 /* Multihop attempted */ +#define EDOTDOT 73 /* RFS specific error */ +#define EBADMSG 74 /* Not a data message */ +#define EOVERFLOW 75 /* Value too large for defined data type */ +#define ENOTUNIQ 76 /* Name not unique on network */ +#define EBADFD 77 /* File descriptor in bad state */ +#define EREMCHG 78 /* Remote address changed */ +#define ELIBACC 79 /* Can not access a needed shared library */ +#define ELIBBAD 80 /* Accessing a corrupted shared library */ +#define ELIBSCN 81 /* .lib section in a.out corrupted */ +#define ELIBMAX 82 /* Attempting to link in too many shared libraries */ +#define ELIBEXEC 83 /* Cannot exec a shared library directly */ +#define EILSEQ 84 /* Illegal byte sequence */ +#define ERESTART 85 /* Interrupted system call should be restarted */ +#define ESTRPIPE 86 /* Streams pipe error */ +#define EUSERS 87 /* Too many users */ +#define ENOTSOCK 88 /* Socket operation on non-socket */ +#define EDESTADDRREQ 89 /* Destination address required */ +#define EMSGSIZE 90 /* Message too long */ +#define EPROTOTYPE 91 /* Protocol wrong type for socket */ +#define ENOPROTOOPT 92 /* Protocol not available */ +#define EPROTONOSUPPORT 93 /* Protocol not supported */ +#define ESOCKTNOSUPPORT 94 /* Socket type not supported */ +#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ +#define EPFNOSUPPORT 96 /* Protocol family not supported */ +#define EAFNOSUPPORT 97 /* Address family not supported by protocol */ +#define EADDRINUSE 98 /* Address already in use */ +#define EADDRNOTAVAIL 99 /* Cannot assign requested address */ +#define ENETDOWN 100 /* Network is down */ +#define ENETUNREACH 101 /* Network is unreachable */ +#define ENETRESET 102 /* Network dropped connection because of reset */ +#define ECONNABORTED 103 /* Software caused connection abort */ +#define ECONNRESET 104 /* Connection reset by peer */ +#define ENOBUFS 105 /* No buffer space available */ +#define EISCONN 106 /* Transport endpoint is already connected */ +#define ENOTCONN 107 /* Transport endpoint is not connected */ +#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */ +#define ETOOMANYREFS 109 /* Too many references: cannot splice */ +#define ETIMEDOUT 110 /* Connection timed out */ +#define ECONNREFUSED 111 /* Connection refused */ +#define EHOSTDOWN 112 /* Host is down */ +#define EHOSTUNREACH 113 /* No route to host */ +#define EALREADY 114 /* Operation already in progress */ +#define EINPROGRESS 115 /* Operation now in progress */ +#define ESTALE 116 /* Stale NFS file handle */ +#define EUCLEAN 117 /* Structure needs cleaning */ +#define ENOTNAM 118 /* Not a XENIX named type file */ +#define ENAVAIL 119 /* No XENIX semaphores available */ +#define EISNAM 120 /* Is a named type file */ +#define EREMOTEIO 121 /* Remote I/O error */ +#define EDQUOT 122 /* Quota exceeded */ + +#define ENOMEDIUM 123 /* No medium found */ +#define EMEDIUMTYPE 124 /* Wrong medium type */ + + +#define ENSROK 0 /* DNS server returned answer with no data */ +#define ENSRNODATA 160 /* DNS server returned answer with no data */ +#define ENSRFORMERR 161 /* DNS server claims query was misformatted */ +#define ENSRSERVFAIL 162 /* DNS server returned general failure */ +#define ENSRNOTFOUND 163 /* Domain name not found */ +#define ENSRNOTIMP 164 /* DNS server does not implement requested operation */ +#define ENSRREFUSED 165 /* DNS server refused query */ +#define ENSRBADQUERY 166 /* Misformatted DNS query */ +#define ENSRBADNAME 167 /* Misformatted domain name */ +#define ENSRBADFAMILY 168 /* Unsupported address family */ +#define ENSRBADRESP 169 /* Misformatted DNS reply */ +#define ENSRCONNREFUSED 170 /* Could not contact DNS servers */ +#define ENSRTIMEOUT 171 /* Timeout while contacting DNS servers */ +#define ENSROF 172 /* End of file */ +#define ENSRFILE 173 /* Error reading file */ +#define ENSRNOMEM 174 /* Out of memory */ +#define ENSRDESTRUCTION 175 /* Application terminated lookup */ +#define ENSRQUERYDOMAINTOOLONG 176 /* Domain name is too long */ +#define ENSRCNAMELOOP 177 /* Domain name is too long */ + +#ifndef errno +extern int errno; +#endif + +#endif /* LWIP_PROVIDE_ERRNO */ + +#endif /* __LWIP_ARCH_H__ */ diff --git a/20080212/Demo/Common/ethernet/lwIP/include/lwip/debug.h b/20080212/Demo/Common/ethernet/lwIP/include/lwip/debug.h new file mode 100644 index 000000000..3649cbd6c --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/include/lwip/debug.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_DEBUG_H__ +#define __LWIP_DEBUG_H__ + +#include "arch/cc.h" + +/** lower two bits indicate debug level + * - 0 off + * - 1 warning + * - 2 serious + * - 3 severe + */ + +#define DBG_LEVEL_OFF 0 +#define DBG_LEVEL_WARNING 1 /* bad checksums, dropped packets, ... */ +#define DBG_LEVEL_SERIOUS 2 /* memory allocation failures, ... */ +#define DBG_LEVEL_SEVERE 3 /* */ +#define DBG_MASK_LEVEL 3 + +/** flag for LWIP_DEBUGF to enable that debug message */ +#define DBG_ON 0x80U +/** flag for LWIP_DEBUGF to disable that debug message */ +#define DBG_OFF 0x00U + +/** flag for LWIP_DEBUGF indicating a tracing message (to follow program flow) */ +#define DBG_TRACE 0x40U +/** flag for LWIP_DEBUGF indicating a state debug message (to follow module states) */ +#define DBG_STATE 0x20U +/** flag for LWIP_DEBUGF indicating newly added code, not thoroughly tested yet */ +#define DBG_FRESH 0x10U +/** flag for LWIP_DEBUGF to halt after printing this debug message */ +#define DBG_HALT 0x08U + +#ifndef LWIP_NOASSERT +# define LWIP_ASSERT(x,y) do { if(!(y)) LWIP_PLATFORM_ASSERT(x); } while(0) +#else +# define LWIP_ASSERT(x,y) +#endif + +#ifdef LWIP_DEBUG +/** print debug message only if debug message type is enabled... + * AND is of correct type AND is at least DBG_LEVEL + */ +# define LWIP_DEBUGF(debug,x) do { if (((debug) & DBG_ON) && ((debug) & DBG_TYPES_ON) && ((s16_t)((debug) & DBG_MASK_LEVEL) >= DBG_MIN_LEVEL)) { LWIP_PLATFORM_DIAG(x); if ((debug) & DBG_HALT) while(1); } } while(0) +# define LWIP_ERROR(x) do { LWIP_PLATFORM_DIAG(x); } while(0) +#else /* LWIP_DEBUG */ +# define LWIP_DEBUGF(debug,x) +# define LWIP_ERROR(x) +#endif /* LWIP_DEBUG */ + +#endif /* __LWIP_DEBUG_H__ */ + + + + + + diff --git a/20080212/Demo/Common/ethernet/lwIP/include/lwip/def.h b/20080212/Demo/Common/ethernet/lwIP/include/lwip/def.h new file mode 100644 index 000000000..f26bdd040 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/include/lwip/def.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_DEF_H__ +#define __LWIP_DEF_H__ + +/* this might define NULL already */ +#include "arch/cc.h" + +#define LWIP_MAX(x , y) (x) > (y) ? (x) : (y) +#define LWIP_MIN(x , y) (x) < (y) ? (x) : (y) + +#ifndef NULL +#define NULL ((void *)0) +#endif + + +#endif /* __LWIP_DEF_H__ */ + diff --git a/20080212/Demo/Common/ethernet/lwIP/include/lwip/dhcp.h b/20080212/Demo/Common/ethernet/lwIP/include/lwip/dhcp.h new file mode 100644 index 000000000..df51bdc96 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/include/lwip/dhcp.h @@ -0,0 +1,223 @@ +/** @file + */ + +#ifndef __LWIP_DHCP_H__ +#define __LWIP_DHCP_H__ + +#include "lwip/opt.h" +#include "lwip/netif.h" +#include "lwip/udp.h" + +/** period (in seconds) of the application calling dhcp_coarse_tmr() */ +#define DHCP_COARSE_TIMER_SECS 60 +/** period (in milliseconds) of the application calling dhcp_fine_tmr() */ +#define DHCP_FINE_TIMER_MSECS 500 + +struct dhcp +{ + /** current DHCP state machine state */ + u8_t state; + /** retries of current request */ + u8_t tries; + /** transaction identifier of last sent request */ + u32_t xid; + /** our connection to the DHCP server */ + struct udp_pcb *pcb; + /** (first) pbuf of incoming msg */ + struct pbuf *p; + /** incoming msg */ + struct dhcp_msg *msg_in; + /** incoming msg options */ + struct dhcp_msg *options_in; + /** ingoing msg options length */ + u16_t options_in_len; + + struct pbuf *p_out; /* pbuf of outcoming msg */ + struct dhcp_msg *msg_out; /* outgoing msg */ + u16_t options_out_len; /* outgoing msg options length */ + u16_t request_timeout; /* #ticks with period DHCP_FINE_TIMER_SECS for request timeout */ + u16_t t1_timeout; /* #ticks with period DHCP_COARSE_TIMER_SECS for renewal time */ + u16_t t2_timeout; /* #ticks with period DHCP_COARSE_TIMER_SECS for rebind time */ + struct ip_addr server_ip_addr; /* dhcp server address that offered this lease */ + struct ip_addr offered_ip_addr; + struct ip_addr offered_sn_mask; + struct ip_addr offered_gw_addr; + struct ip_addr offered_bc_addr; +#define DHCP_MAX_DNS 2 + u32_t dns_count; /* actual number of DNS servers obtained */ + struct ip_addr offered_dns_addr[DHCP_MAX_DNS]; /* DNS server addresses */ + + u32_t offered_t0_lease; /* lease period (in seconds) */ + u32_t offered_t1_renew; /* recommended renew time (usually 50% of lease period) */ + u32_t offered_t2_rebind; /* recommended rebind time (usually 66% of lease period) */ +/** Patch #1308 + * TODO: See dhcp.c "TODO"s + */ +#if 0 + struct ip_addr offered_si_addr; + u8_t *boot_file_name; +#endif +}; + +/* MUST be compiled with "pack structs" or equivalent! */ +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +/** minimum set of fields of any DHCP message */ +struct dhcp_msg +{ + PACK_STRUCT_FIELD(u8_t op); + PACK_STRUCT_FIELD(u8_t htype); + PACK_STRUCT_FIELD(u8_t hlen); + PACK_STRUCT_FIELD(u8_t hops); + PACK_STRUCT_FIELD(u32_t xid); + PACK_STRUCT_FIELD(u16_t secs); + PACK_STRUCT_FIELD(u16_t flags); + PACK_STRUCT_FIELD(struct ip_addr ciaddr); + PACK_STRUCT_FIELD(struct ip_addr yiaddr); + PACK_STRUCT_FIELD(struct ip_addr siaddr); + PACK_STRUCT_FIELD(struct ip_addr giaddr); +#define DHCP_CHADDR_LEN 16U + PACK_STRUCT_FIELD(u8_t chaddr[DHCP_CHADDR_LEN]); +#define DHCP_SNAME_LEN 64U + PACK_STRUCT_FIELD(u8_t sname[DHCP_SNAME_LEN]); +#define DHCP_FILE_LEN 128U + PACK_STRUCT_FIELD(u8_t file[DHCP_FILE_LEN]); + PACK_STRUCT_FIELD(u32_t cookie); +#define DHCP_MIN_OPTIONS_LEN 68U +/** make sure user does not configure this too small */ +#if ((defined(DHCP_OPTIONS_LEN)) && (DHCP_OPTIONS_LEN < DHCP_MIN_OPTIONS_LEN)) +# undef DHCP_OPTIONS_LEN +#endif +/** allow this to be configured in lwipopts.h, but not too small */ +#if (!defined(DHCP_OPTIONS_LEN)) +/** set this to be sufficient for your options in outgoing DHCP msgs */ +# define DHCP_OPTIONS_LEN DHCP_MIN_OPTIONS_LEN +#endif + PACK_STRUCT_FIELD(u8_t options[DHCP_OPTIONS_LEN]); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +/** start DHCP configuration */ +err_t dhcp_start(struct netif *netif); +/** enforce early lease renewal (not needed normally)*/ +err_t dhcp_renew(struct netif *netif); +/** release the DHCP lease, usually called before dhcp_stop()*/ +err_t dhcp_release(struct netif *netif); +/** stop DHCP configuration */ +void dhcp_stop(struct netif *netif); +/** inform server of our manual IP address */ +void dhcp_inform(struct netif *netif); + +/** if enabled, check whether the offered IP address is not in use, using ARP */ +#if DHCP_DOES_ARP_CHECK +void dhcp_arp_reply(struct netif *netif, struct ip_addr *addr); +#endif + +/** to be called every minute */ +void dhcp_coarse_tmr(void); +/** to be called every half second */ +void dhcp_fine_tmr(void); + +/** DHCP message item offsets and length */ +#define DHCP_MSG_OFS (UDP_DATA_OFS) + #define DHCP_OP_OFS (DHCP_MSG_OFS + 0) + #define DHCP_HTYPE_OFS (DHCP_MSG_OFS + 1) + #define DHCP_HLEN_OFS (DHCP_MSG_OFS + 2) + #define DHCP_HOPS_OFS (DHCP_MSG_OFS + 3) + #define DHCP_XID_OFS (DHCP_MSG_OFS + 4) + #define DHCP_SECS_OFS (DHCP_MSG_OFS + 8) + #define DHCP_FLAGS_OFS (DHCP_MSG_OFS + 10) + #define DHCP_CIADDR_OFS (DHCP_MSG_OFS + 12) + #define DHCP_YIADDR_OFS (DHCP_MSG_OFS + 16) + #define DHCP_SIADDR_OFS (DHCP_MSG_OFS + 20) + #define DHCP_GIADDR_OFS (DHCP_MSG_OFS + 24) + #define DHCP_CHADDR_OFS (DHCP_MSG_OFS + 28) + #define DHCP_SNAME_OFS (DHCP_MSG_OFS + 44) + #define DHCP_FILE_OFS (DHCP_MSG_OFS + 108) +#define DHCP_MSG_LEN 236 + +#define DHCP_COOKIE_OFS (DHCP_MSG_OFS + DHCP_MSG_LEN) +#define DHCP_OPTIONS_OFS (DHCP_MSG_OFS + DHCP_MSG_LEN + 4) + +#define DHCP_CLIENT_PORT 68 +#define DHCP_SERVER_PORT 67 + +/** DHCP client states */ +#define DHCP_REQUESTING 1 +#define DHCP_INIT 2 +#define DHCP_REBOOTING 3 +#define DHCP_REBINDING 4 +#define DHCP_RENEWING 5 +#define DHCP_SELECTING 6 +#define DHCP_INFORMING 7 +#define DHCP_CHECKING 8 +#define DHCP_PERMANENT 9 +#define DHCP_BOUND 10 +/** not yet implemented #define DHCP_RELEASING 11 */ +#define DHCP_BACKING_OFF 12 +#define DHCP_OFF 13 + +#define DHCP_BOOTREQUEST 1 +#define DHCP_BOOTREPLY 2 + +#define DHCP_DISCOVER 1 +#define DHCP_OFFER 2 +#define DHCP_REQUEST 3 +#define DHCP_DECLINE 4 +#define DHCP_ACK 5 +#define DHCP_NAK 6 +#define DHCP_RELEASE 7 +#define DHCP_INFORM 8 + +#define DHCP_HTYPE_ETH 1 + +#define DHCP_HLEN_ETH 6 + +#define DHCP_BROADCAST_FLAG 15 +#define DHCP_BROADCAST_MASK (1 << DHCP_FLAG_BROADCAST) + +/** BootP options */ +#define DHCP_OPTION_PAD 0 +#define DHCP_OPTION_SUBNET_MASK 1 /* RFC 2132 3.3 */ +#define DHCP_OPTION_ROUTER 3 +#define DHCP_OPTION_DNS_SERVER 6 +#define DHCP_OPTION_HOSTNAME 12 +#define DHCP_OPTION_IP_TTL 23 +#define DHCP_OPTION_MTU 26 +#define DHCP_OPTION_BROADCAST 28 +#define DHCP_OPTION_TCP_TTL 37 +#define DHCP_OPTION_END 255 + +/** DHCP options */ +#define DHCP_OPTION_REQUESTED_IP 50 /* RFC 2132 9.1, requested IP address */ +#define DHCP_OPTION_LEASE_TIME 51 /* RFC 2132 9.2, time in seconds, in 4 bytes */ +#define DHCP_OPTION_OVERLOAD 52 /* RFC2132 9.3, use file and/or sname field for options */ + +#define DHCP_OPTION_MESSAGE_TYPE 53 /* RFC 2132 9.6, important for DHCP */ +#define DHCP_OPTION_MESSAGE_TYPE_LEN 1 + + +#define DHCP_OPTION_SERVER_ID 54 /* RFC 2132 9.7, server IP address */ +#define DHCP_OPTION_PARAMETER_REQUEST_LIST 55 /* RFC 2132 9.8, requested option types */ + +#define DHCP_OPTION_MAX_MSG_SIZE 57 /* RFC 2132 9.10, message size accepted >= 576 */ +#define DHCP_OPTION_MAX_MSG_SIZE_LEN 2 + +#define DHCP_OPTION_T1 58 /* T1 renewal time */ +#define DHCP_OPTION_T2 59 /* T2 rebinding time */ +#define DHCP_OPTION_CLIENT_ID 61 +#define DHCP_OPTION_TFTP_SERVERNAME 66 +#define DHCP_OPTION_BOOTFILE 67 + +/** possible combinations of overloading the file and sname fields with options */ +#define DHCP_OVERLOAD_NONE 0 +#define DHCP_OVERLOAD_FILE 1 +#define DHCP_OVERLOAD_SNAME 2 +#define DHCP_OVERLOAD_SNAME_FILE 3 + +#endif /*__LWIP_DHCP_H__*/ diff --git a/20080212/Demo/Common/ethernet/lwIP/include/lwip/err.h b/20080212/Demo/Common/ethernet/lwIP/include/lwip/err.h new file mode 100644 index 000000000..fc90f2eab --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/include/lwip/err.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_ERR_H__ +#define __LWIP_ERR_H__ + +#include "lwip/opt.h" + +#include "arch/cc.h" + +typedef s8_t err_t; + +/* Definitions for error constants. */ + +#define ERR_OK 0 /* No error, everything OK. */ +#define ERR_MEM -1 /* Out of memory error. */ +#define ERR_BUF -2 /* Buffer error. */ + + +#define ERR_ABRT -3 /* Connection aborted. */ +#define ERR_RST -4 /* Connection reset. */ +#define ERR_CLSD -5 /* Connection closed. */ +#define ERR_CONN -6 /* Not connected. */ + +#define ERR_VAL -7 /* Illegal value. */ + +#define ERR_ARG -8 /* Illegal argument. */ + +#define ERR_RTE -9 /* Routing problem. */ + +#define ERR_USE -10 /* Address in use. */ + +#define ERR_IF -11 /* Low-level netif error */ +#define ERR_ISCONN -12 /* Already connected. */ + + +#ifdef LWIP_DEBUG +extern char *lwip_strerr(err_t err); +#else +#define lwip_strerr(x) "" +#endif /* LWIP_DEBUG */ +#endif /* __LWIP_ERR_H__ */ diff --git a/20080212/Demo/Common/ethernet/lwIP/include/lwip/mem.h b/20080212/Demo/Common/ethernet/lwIP/include/lwip/mem.h new file mode 100644 index 000000000..3d57389b5 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/include/lwip/mem.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_MEM_H__ +#define __LWIP_MEM_H__ + +#include "lwip/opt.h" +#include "lwip/arch.h" + +#if MEM_SIZE > 64000l +typedef u32_t mem_size_t; +#define MEM_SIZE_F U32_F +#else +typedef u16_t mem_size_t; +#define MEM_SIZE_F U16_F +#endif /* MEM_SIZE > 64000 */ + +#if MEM_LIBC_MALLOC +/* aliases for C library malloc() */ +#define mem_init() +#define mem_free(x) free(x) +#define mem_malloc(x) malloc(x) +#define mem_realloc(x, size) realloc(x,size) +#else +/* lwIP alternative malloc */ +void mem_init(void); +void *mem_malloc(mem_size_t size); +void mem_free(void *mem); +void *mem_realloc(void *mem, mem_size_t size); +#endif + +#ifndef MEM_ALIGN_SIZE +#define MEM_ALIGN_SIZE(size) (((size) + MEM_ALIGNMENT - 1) & ~(MEM_ALIGNMENT-1)) +#endif + +#ifndef MEM_ALIGN +#define MEM_ALIGN(addr) ((void *)(((mem_ptr_t)(addr) + MEM_ALIGNMENT - 1) & ~(mem_ptr_t)(MEM_ALIGNMENT-1))) +#endif + +#endif /* __LWIP_MEM_H__ */ + diff --git a/20080212/Demo/Common/ethernet/lwIP/include/lwip/memp.h b/20080212/Demo/Common/ethernet/lwIP/include/lwip/memp.h new file mode 100644 index 000000000..6da033f27 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/include/lwip/memp.h @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#ifndef __LWIP_MEMP_H__ +#define __LWIP_MEMP_H__ + +#include "lwip/opt.h" + +typedef enum { + MEMP_PBUF, + MEMP_RAW_PCB, + MEMP_UDP_PCB, + MEMP_TCP_PCB, + MEMP_TCP_PCB_LISTEN, + MEMP_TCP_SEG, + + MEMP_NETBUF, + MEMP_NETCONN, + MEMP_API_MSG, + MEMP_TCPIP_MSG, + + MEMP_SYS_TIMEOUT, + + MEMP_MAX +} memp_t; + +void memp_init(void); + +void *memp_malloc(memp_t type); +void *memp_realloc(memp_t fromtype, memp_t totype, void *mem); +void memp_free(memp_t type, void *mem); + +#endif /* __LWIP_MEMP_H__ */ + diff --git a/20080212/Demo/Common/ethernet/lwIP/include/lwip/netif.h b/20080212/Demo/Common/ethernet/lwIP/include/lwip/netif.h new file mode 100644 index 000000000..efc59fdc3 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/include/lwip/netif.h @@ -0,0 +1,165 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_NETIF_H__ +#define __LWIP_NETIF_H__ + +#include "lwip/opt.h" + +#include "lwip/err.h" + +#include "lwip/ip_addr.h" + +#include "lwip/inet.h" +#include "lwip/pbuf.h" +#if LWIP_DHCP +# include "lwip/dhcp.h" +#endif + +/** must be the maximum of all used hardware address lengths + across all types of interfaces in use */ +#define NETIF_MAX_HWADDR_LEN 6U + +/** TODO: define the use (where, when, whom) of netif flags */ + +/** whether the network interface is 'up'. this is + * a software flag used to control whether this network + * interface is enabled and processes traffic. + */ +#define NETIF_FLAG_UP 0x1U +/** if set, the netif has broadcast capability */ +#define NETIF_FLAG_BROADCAST 0x2U +/** if set, the netif is one end of a point-to-point connection */ +#define NETIF_FLAG_POINTTOPOINT 0x4U +/** if set, the interface is configured using DHCP */ +#define NETIF_FLAG_DHCP 0x08U +/** if set, the interface has an active link + * (set by the network interface driver) */ +#define NETIF_FLAG_LINK_UP 0x10U + +/** Generic data structure used for all lwIP network interfaces. + * The following fields should be filled in by the initialization + * function for the device driver: hwaddr_len, hwaddr[], mtu, flags */ + +struct netif { + /** pointer to next in linked list */ + struct netif *next; + + /** IP address configuration in network byte order */ + struct ip_addr ip_addr; + struct ip_addr netmask; + struct ip_addr gw; + + /** This function is called by the network device driver + * to pass a packet up the TCP/IP stack. */ + err_t (* input)(struct pbuf *p, struct netif *inp); + /** This function is called by the IP module when it wants + * to send a packet on the interface. This function typically + * first resolves the hardware address, then sends the packet. */ + err_t (* output)(struct netif *netif, struct pbuf *p, + struct ip_addr *ipaddr); + /** This function is called by the ARP module when it wants + * to send a packet on the interface. This function outputs + * the pbuf as-is on the link medium. */ + err_t (* linkoutput)(struct netif *netif, struct pbuf *p); + /** This field can be set by the device driver and could point + * to state information for the device. */ + void *state; +#if LWIP_DHCP + /** the DHCP client state information for this netif */ + struct dhcp *dhcp; +#endif + /** number of bytes used in hwaddr */ + u8_t hwaddr_len; + /** link level hardware address of this interface */ + u8_t hwaddr[NETIF_MAX_HWADDR_LEN]; + /** maximum transfer unit (in bytes) */ + u16_t mtu; + /** flags (see NETIF_FLAG_ above) */ + u8_t flags; + /** descriptive abbreviation */ + char name[2]; + /** number of this interface */ + u8_t num; +#if LWIP_SNMP + /** link type (ifType values per RFC1213) */ + u8_t link_type; + /** (estimate) link speed */ + u32_t link_speed; + /** timestamp at last change made (up/down) */ + u32_t ts; + /** counters */ + u32_t ifinoctets; + u32_t ifinucastpkts; + u32_t ifinnucastpkts; + u32_t ifindiscards; + u32_t ifoutoctets; + u32_t ifoutucastpkts; + u32_t ifoutnucastpkts; + u32_t ifoutdiscards; +#endif +}; + +/** The list of network interfaces. */ +extern struct netif *netif_list; +/** The default network interface. */ +extern struct netif *netif_default; + +/* netif_init() must be called first. */ +void netif_init(void); + +struct netif *netif_add(struct netif *netif, struct ip_addr *ipaddr, struct ip_addr *netmask, + struct ip_addr *gw, + void *state, + err_t (* init)(struct netif *netif), + err_t (* input)(struct pbuf *p, struct netif *netif)); + +void +netif_set_addr(struct netif *netif,struct ip_addr *ipaddr, struct ip_addr *netmask, + struct ip_addr *gw); +void netif_remove(struct netif * netif); + +/* Returns a network interface given its name. The name is of the form + "et0", where the first two letters are the "name" field in the + netif structure, and the digit is in the num field in the same + structure. */ +struct netif *netif_find(char *name); + +void netif_set_default(struct netif *netif); + +void netif_set_ipaddr(struct netif *netif, struct ip_addr *ipaddr); +void netif_set_netmask(struct netif *netif, struct ip_addr *netmast); +void netif_set_gw(struct netif *netif, struct ip_addr *gw); +void netif_set_up(struct netif *netif); +void netif_set_down(struct netif *netif); +u8_t netif_is_up(struct netif *netif); + +#endif /* __LWIP_NETIF_H__ */ diff --git a/20080212/Demo/Common/ethernet/lwIP/include/lwip/pbuf.h b/20080212/Demo/Common/ethernet/lwIP/include/lwip/pbuf.h new file mode 100644 index 000000000..0b187e121 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/include/lwip/pbuf.h @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#ifndef __LWIP_PBUF_H__ +#define __LWIP_PBUF_H__ + +#include "arch/cc.h" + + +#define PBUF_TRANSPORT_HLEN 20 +#define PBUF_IP_HLEN 20 + +typedef enum { + PBUF_TRANSPORT, + PBUF_IP, + PBUF_LINK, + PBUF_RAW +} pbuf_layer; + +typedef enum { + PBUF_RAM, + PBUF_ROM, + PBUF_REF, + PBUF_POOL +} pbuf_flag; + +/* Definitions for the pbuf flag field. These are NOT the flags that + * are passed to pbuf_alloc(). */ +#define PBUF_FLAG_RAM 0x00U /* Flags that pbuf data is stored in RAM */ +#define PBUF_FLAG_ROM 0x01U /* Flags that pbuf data is stored in ROM */ +#define PBUF_FLAG_POOL 0x02U /* Flags that the pbuf comes from the pbuf pool */ +#define PBUF_FLAG_REF 0x04U /* Flags thet the pbuf payload refers to RAM */ + +/** indicates this packet was broadcast on the link */ +#define PBUF_FLAG_LINK_BROADCAST 0x80U + +struct pbuf { + /** next pbuf in singly linked pbuf chain */ + struct pbuf *next; + + /** pointer to the actual data in the buffer */ + void *payload; + + /** + * total length of this buffer and all next buffers in chain + * belonging to the same packet. + * + * For non-queue packet chains this is the invariant: + * p->tot_len == p->len + (p->next? p->next->tot_len: 0) + */ + u16_t tot_len; + + /** length of this buffer */ + u16_t len; + + /** flags telling the type of pbuf, see PBUF_FLAG_ */ + u16_t flags; + + /** + * the reference count always equals the number of pointers + * that refer to this pbuf. This can be pointers from an application, + * the stack itself, or pbuf->next pointers from a chain. + */ + u16_t ref; + +}; + +void pbuf_init(void); + +struct pbuf *pbuf_alloc(pbuf_layer l, u16_t size, pbuf_flag flag); +void pbuf_realloc(struct pbuf *p, u16_t size); +u8_t pbuf_header(struct pbuf *p, s16_t header_size); +void pbuf_ref(struct pbuf *p); +void pbuf_ref_chain(struct pbuf *p); +u8_t pbuf_free(struct pbuf *p); +u8_t pbuf_clen(struct pbuf *p); +void pbuf_cat(struct pbuf *h, struct pbuf *t); +void pbuf_chain(struct pbuf *h, struct pbuf *t); +struct pbuf *pbuf_take(struct pbuf *f); +struct pbuf *pbuf_dechain(struct pbuf *p); +void pbuf_queue(struct pbuf *p, struct pbuf *n); +struct pbuf * pbuf_dequeue(struct pbuf *p); + +#endif /* __LWIP_PBUF_H__ */ diff --git a/20080212/Demo/Common/ethernet/lwIP/include/lwip/raw.h b/20080212/Demo/Common/ethernet/lwIP/include/lwip/raw.h new file mode 100644 index 000000000..83b32da9d --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/include/lwip/raw.h @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_RAW_H__ +#define __LWIP_RAW_H__ + +#include "lwip/arch.h" + +#include "lwip/pbuf.h" +#include "lwip/inet.h" +#include "lwip/ip.h" + +struct raw_pcb { +/* Common members of all PCB types */ + IP_PCB; + + struct raw_pcb *next; + + u16_t protocol; + + u8_t (* recv)(void *arg, struct raw_pcb *pcb, struct pbuf *p, + struct ip_addr *addr); + void *recv_arg; +}; + +/* The following functions is the application layer interface to the + RAW code. */ +struct raw_pcb * raw_new (u16_t proto); +void raw_remove (struct raw_pcb *pcb); +err_t raw_bind (struct raw_pcb *pcb, struct ip_addr *ipaddr); +err_t raw_connect (struct raw_pcb *pcb, struct ip_addr *ipaddr); + +void raw_recv (struct raw_pcb *pcb, + u8_t (* recv)(void *arg, struct raw_pcb *pcb, + struct pbuf *p, + struct ip_addr *addr), + void *recv_arg); +err_t raw_sendto (struct raw_pcb *pcb, struct pbuf *p, struct ip_addr *ipaddr); +err_t raw_send (struct raw_pcb *pcb, struct pbuf *p); + +/* The following functions are the lower layer interface to RAW. */ +u8_t raw_input (struct pbuf *p, struct netif *inp); +void raw_init (void); + + +#endif /* __LWIP_RAW_H__ */ diff --git a/20080212/Demo/Common/ethernet/lwIP/include/lwip/sio.h b/20080212/Demo/Common/ethernet/lwIP/include/lwip/sio.h new file mode 100644 index 000000000..5fc28a4d6 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/include/lwip/sio.h @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + */ + +/* + * This is the interface to the platform specific serial IO module + * It needs to be implemented by those platforms which need SLIP or PPP + */ + +#include "arch/cc.h" + +#ifndef __sio_fd_t_defined +typedef void * sio_fd_t; +#endif + +#ifndef sio_open +sio_fd_t sio_open(u8_t); +#endif + +#ifndef sio_send +void sio_send(u8_t, sio_fd_t); +#endif + +#ifndef sio_recv +u8_t sio_recv(sio_fd_t); +#endif + +#ifndef sio_read +u32_t sio_read(sio_fd_t, u8_t *, u32_t); +#endif + +#ifndef sio_write +u32_t sio_write(sio_fd_t, u8_t *, u32_t); +#endif + +#ifndef sio_read_abort +void sio_read_abort(sio_fd_t); +#endif diff --git a/20080212/Demo/Common/ethernet/lwIP/include/lwip/snmp.h b/20080212/Demo/Common/ethernet/lwIP/include/lwip/snmp.h new file mode 100644 index 000000000..987ebd90a --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/include/lwip/snmp.h @@ -0,0 +1,309 @@ +/* + * Copyright (c) 2001, 2002 Leon Woestenberg + * Copyright (c) 2001, 2002 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Leon Woestenberg + * + */ +#ifndef __LWIP_SNMP_H__ +#define __LWIP_SNMP_H__ + +#include "lwip/opt.h" +#include "lwip/netif.h" +#include "lwip/udp.h" + +/* SNMP support available? */ +#if defined(LWIP_SNMP) && (LWIP_SNMP > 0) + +/** fixed maximum length for object identifier type */ +#define LWIP_SNMP_OBJ_ID_LEN 32 +/** internal object identifier representation */ +struct snmp_obj_id +{ + u8_t len; + s32_t id[LWIP_SNMP_OBJ_ID_LEN]; +}; + +/* system */ +void snmp_set_sysdesr(u8_t* str, u8_t* strlen); +void snmp_set_sysobjid(struct snmp_obj_id *oid); +void snmp_get_sysobjid_ptr(struct snmp_obj_id **oid); +void snmp_inc_sysuptime(void); +void snmp_get_sysuptime(u32_t *value); +void snmp_set_syscontact(u8_t *ocstr, u8_t *ocstrlen); +void snmp_set_sysname(u8_t *ocstr, u8_t *ocstrlen); +void snmp_set_syslocation(u8_t *ocstr, u8_t *ocstrlen); + +/* network interface */ +void snmp_add_ifinoctets(struct netif *ni, u32_t value); +void snmp_inc_ifinucastpkts(struct netif *ni); +void snmp_inc_ifinnucastpkts(struct netif *ni); +void snmp_inc_ifindiscards(struct netif *ni); +void snmp_add_ifoutoctets(struct netif *ni, u32_t value); +void snmp_inc_ifoutucastpkts(struct netif *ni); +void snmp_inc_ifoutnucastpkts(struct netif *ni); +void snmp_inc_ifoutdiscards(struct netif *ni); +void snmp_inc_iflist(void); +void snmp_dec_iflist(void); + +/* ARP (for atTable and ipNetToMediaTable) */ +void snmp_insert_arpidx_tree(struct netif *ni, struct ip_addr *ip); +void snmp_delete_arpidx_tree(struct netif *ni, struct ip_addr *ip); + +/* IP */ +void snmp_inc_ipinreceives(void); +void snmp_inc_ipinhdrerrors(void); +void snmp_inc_ipinaddrerrors(void); +void snmp_inc_ipforwdatagrams(void); +void snmp_inc_ipinunknownprotos(void); +void snmp_inc_ipindiscards(void); +void snmp_inc_ipindelivers(void); +void snmp_inc_ipoutrequests(void); +void snmp_inc_ipoutdiscards(void); +void snmp_inc_ipoutnoroutes(void); +void snmp_inc_ipreasmreqds(void); +void snmp_inc_ipreasmoks(void); +void snmp_inc_ipreasmfails(void); +void snmp_inc_ipfragoks(void); +void snmp_inc_ipfragfails(void); +void snmp_inc_ipfragcreates(void); +void snmp_inc_iproutingdiscards(void); +void snmp_insert_ipaddridx_tree(struct netif *ni); +void snmp_delete_ipaddridx_tree(struct netif *ni); +void snmp_insert_iprteidx_tree(u8_t dflt, struct netif *ni); +void snmp_delete_iprteidx_tree(u8_t dflt, struct netif *ni); + +/* ICMP */ +void snmp_inc_icmpinmsgs(void); +void snmp_inc_icmpinerrors(void); +void snmp_inc_icmpindestunreachs(void); +void snmp_inc_icmpintimeexcds(void); +void snmp_inc_icmpinparmprobs(void); +void snmp_inc_icmpinsrcquenchs(void); +void snmp_inc_icmpinredirects(void); +void snmp_inc_icmpinechos(void); +void snmp_inc_icmpinechoreps(void); +void snmp_inc_icmpintimestamps(void); +void snmp_inc_icmpintimestampreps(void); +void snmp_inc_icmpinaddrmasks(void); +void snmp_inc_icmpinaddrmaskreps(void); +void snmp_inc_icmpoutmsgs(void); +void snmp_inc_icmpouterrors(void); +void snmp_inc_icmpoutdestunreachs(void); +void snmp_inc_icmpouttimeexcds(void); +void snmp_inc_icmpoutparmprobs(void); +void snmp_inc_icmpoutsrcquenchs(void); +void snmp_inc_icmpoutredirects(void); +void snmp_inc_icmpoutechos(void); +void snmp_inc_icmpoutechoreps(void); +void snmp_inc_icmpouttimestamps(void); +void snmp_inc_icmpouttimestampreps(void); +void snmp_inc_icmpoutaddrmasks(void); +void snmp_inc_icmpoutaddrmaskreps(void); + +/* TCP */ +void snmp_inc_tcpactiveopens(void); +void snmp_inc_tcppassiveopens(void); +void snmp_inc_tcpattemptfails(void); +void snmp_inc_tcpestabresets(void); +void snmp_inc_tcpinsegs(void); +void snmp_inc_tcpoutsegs(void); +void snmp_inc_tcpretranssegs(void); +void snmp_inc_tcpinerrs(void); +void snmp_inc_tcpoutrsts(void); + +/* UDP */ +void snmp_inc_udpindatagrams(void); +void snmp_inc_udpnoports(void); +void snmp_inc_udpinerrors(void); +void snmp_inc_udpoutdatagrams(void); +void snmp_insert_udpidx_tree(struct udp_pcb *pcb); +void snmp_delete_udpidx_tree(struct udp_pcb *pcb); + +/* SNMP */ +void snmp_inc_snmpinpkts(void); +void snmp_inc_snmpoutpkts(void); +void snmp_inc_snmpinbadversions(void); +void snmp_inc_snmpinbadcommunitynames(void); +void snmp_inc_snmpinbadcommunityuses(void); +void snmp_inc_snmpinasnparseerrs(void); +void snmp_inc_snmpintoobigs(void); +void snmp_inc_snmpinnosuchnames(void); +void snmp_inc_snmpinbadvalues(void); +void snmp_inc_snmpinreadonlys(void); +void snmp_inc_snmpingenerrs(void); +void snmp_add_snmpintotalreqvars(u8_t value); +void snmp_add_snmpintotalsetvars(u8_t value); +void snmp_inc_snmpingetrequests(void); +void snmp_inc_snmpingetnexts(void); +void snmp_inc_snmpinsetrequests(void); +void snmp_inc_snmpingetresponses(void); +void snmp_inc_snmpintraps(void); +void snmp_inc_snmpouttoobigs(void); +void snmp_inc_snmpoutnosuchnames(void); +void snmp_inc_snmpoutbadvalues(void); +void snmp_inc_snmpoutgenerrs(void); +void snmp_inc_snmpoutgetrequests(void); +void snmp_inc_snmpoutgetnexts(void); +void snmp_inc_snmpoutsetrequests(void); +void snmp_inc_snmpoutgetresponses(void); +void snmp_inc_snmpouttraps(void); +void snmp_get_snmpgrpid_ptr(struct snmp_obj_id **oid); +void snmp_set_snmpenableauthentraps(u8_t *value); +void snmp_get_snmpenableauthentraps(u8_t *value); + +/* LWIP_SNMP support not available */ +/* define everything to be empty */ +#else + +/* system */ +#define snmp_set_sysdesr(str, strlen) +#define snmp_get_sysobjid_ptr(oid) +#define snmp_inc_sysuptime() +#define snmp_get_sysuptime(value) + +/* network interface */ +#define snmp_add_ifinoctets(ni,value) +#define snmp_inc_ifinucastpkts(ni) +#define snmp_inc_ifinnucastpkts(ni) +#define snmp_inc_ifindiscards(ni) +#define snmp_add_ifoutoctets(ni,value) +#define snmp_inc_ifoutucastpkts(ni) +#define snmp_inc_ifoutnucastpkts(ni) +#define snmp_inc_ifoutdiscards(ni) +#define snmp_inc_iflist() +#define snmp_dec_iflist() + +/* ARP */ +#define snmp_insert_arpidx_tree(ni,ip) +#define snmp_delete_arpidx_tree(ni,ip) + +/* IP */ +#define snmp_inc_ipinreceives() +#define snmp_inc_ipinhdrerrors() +#define snmp_inc_ipinaddrerrors() +#define snmp_inc_ipforwdatagrams() +#define snmp_inc_ipinunknownprotos() +#define snmp_inc_ipindiscards() +#define snmp_inc_ipindelivers() +#define snmp_inc_ipoutrequests() +#define snmp_inc_ipoutdiscards() +#define snmp_inc_ipoutnoroutes() +#define snmp_inc_ipreasmreqds() +#define snmp_inc_ipreasmoks() +#define snmp_inc_ipreasmfails() +#define snmp_inc_ipfragoks() +#define snmp_inc_ipfragfails() +#define snmp_inc_ipfragcreates() +#define snmp_inc_iproutingdiscards() +#define snmp_insert_ipaddridx_tree(ni) +#define snmp_delete_ipaddridx_tree(ni) +#define snmp_insert_iprteidx_tree(dflt, ni) +#define snmp_delete_iprteidx_tree(dflt, ni) + +/* ICMP */ +#define snmp_inc_icmpinmsgs() +#define snmp_inc_icmpinerrors() +#define snmp_inc_icmpindestunreachs() +#define snmp_inc_icmpintimeexcds() +#define snmp_inc_icmpinparmprobs() +#define snmp_inc_icmpinsrcquenchs() +#define snmp_inc_icmpinredirects() +#define snmp_inc_icmpinechos() +#define snmp_inc_icmpinechoreps() +#define snmp_inc_icmpintimestamps() +#define snmp_inc_icmpintimestampreps() +#define snmp_inc_icmpinaddrmasks() +#define snmp_inc_icmpinaddrmaskreps() +#define snmp_inc_icmpoutmsgs() +#define snmp_inc_icmpouterrors() +#define snmp_inc_icmpoutdestunreachs() +#define snmp_inc_icmpouttimeexcds() +#define snmp_inc_icmpoutparmprobs() +#define snmp_inc_icmpoutsrcquenchs() +#define snmp_inc_icmpoutredirects() +#define snmp_inc_icmpoutechos() +#define snmp_inc_icmpoutechoreps() +#define snmp_inc_icmpouttimestamps() +#define snmp_inc_icmpouttimestampreps() +#define snmp_inc_icmpoutaddrmasks() +#define snmp_inc_icmpoutaddrmaskreps() +/* TCP */ +#define snmp_inc_tcpactiveopens() +#define snmp_inc_tcppassiveopens() +#define snmp_inc_tcpattemptfails() +#define snmp_inc_tcpestabresets() +#define snmp_inc_tcpinsegs() +#define snmp_inc_tcpoutsegs() +#define snmp_inc_tcpretranssegs() +#define snmp_inc_tcpinerrs() +#define snmp_inc_tcpoutrsts() + +/* UDP */ +#define snmp_inc_udpindatagrams() +#define snmp_inc_udpnoports() +#define snmp_inc_udpinerrors() +#define snmp_inc_udpoutdatagrams() +#define snmp_insert_udpidx_tree(pcb) +#define snmp_delete_udpidx_tree(pcb) + +/* SNMP */ +#define snmp_inc_snmpinpkts() +#define snmp_inc_snmpoutpkts() +#define snmp_inc_snmpinbadversions() +#define snmp_inc_snmpinbadcommunitynames() +#define snmp_inc_snmpinbadcommunityuses() +#define snmp_inc_snmpinasnparseerrs() +#define snmp_inc_snmpintoobigs() +#define snmp_inc_snmpinnosuchnames() +#define snmp_inc_snmpinbadvalues() +#define snmp_inc_snmpinreadonlys() +#define snmp_inc_snmpingenerrs() +#define snmp_add_snmpintotalreqvars(value) +#define snmp_add_snmpintotalsetvars(value) +#define snmp_inc_snmpingetrequests() +#define snmp_inc_snmpingetnexts() +#define snmp_inc_snmpinsetrequests() +#define snmp_inc_snmpingetresponses() +#define snmp_inc_snmpintraps() +#define snmp_inc_snmpouttoobigs() +#define snmp_inc_snmpoutnosuchnames() +#define snmp_inc_snmpoutbadvalues() +#define snmp_inc_snmpoutgenerrs() +#define snmp_inc_snmpoutgetrequests() +#define snmp_inc_snmpoutgetnexts() +#define snmp_inc_snmpoutsetrequests() +#define snmp_inc_snmpoutgetresponses() +#define snmp_inc_snmpouttraps() +#define snmp_get_snmpgrpid_ptr(oid) +#define snmp_set_snmpenableauthentraps(value) +#define snmp_get_snmpenableauthentraps(value) + +#endif + +#endif /* __LWIP_SNMP_H__ */ diff --git a/20080212/Demo/Common/ethernet/lwIP/include/lwip/snmp_asn1.h b/20080212/Demo/Common/ethernet/lwIP/include/lwip/snmp_asn1.h new file mode 100644 index 000000000..d83d41d40 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/include/lwip/snmp_asn1.h @@ -0,0 +1,90 @@ +/** + * @file + * Abstract Syntax Notation One (ISO 8824, 8825) codec. + */ + +/* + * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Christiaan Simons + */ + +#ifndef __LWIP_SNMP_ASN1_H__ +#define __LWIP_SNMP_ASN1_H__ + +#include "lwip/opt.h" +#include "arch/cc.h" +#include "lwip/err.h" +#include "lwip/pbuf.h" +#include "lwip/snmp.h" + +#define SNMP_ASN1_UNIV (!0x80 | !0x40) +#define SNMP_ASN1_APPLIC (!0x80 | 0x40) +#define SNMP_ASN1_CONTXT ( 0x80 | !0x40) + +#define SNMP_ASN1_CONSTR (0x20) +#define SNMP_ASN1_PRIMIT (!0x20) + +/* universal tags */ +#define SNMP_ASN1_INTEG 2 +#define SNMP_ASN1_OC_STR 4 +#define SNMP_ASN1_NUL 5 +#define SNMP_ASN1_OBJ_ID 6 +#define SNMP_ASN1_SEQ 16 + +/* application specific (SNMP) tags */ +#define SNMP_ASN1_IPADDR 0 /* octet string size(4) */ +#define SNMP_ASN1_COUNTER 1 /* u32_t */ +#define SNMP_ASN1_GAUGE 2 /* u32_t */ +#define SNMP_ASN1_TIMETICKS 3 /* u32_t */ +#define SNMP_ASN1_OPAQUE 4 /* octet string */ + +/* context specific (SNMP) tags */ +#define SNMP_ASN1_PDU_GET_REQ 0 +#define SNMP_ASN1_PDU_GET_NEXT_REQ 1 +#define SNMP_ASN1_PDU_GET_RESP 2 +#define SNMP_ASN1_PDU_SET_REQ 3 +#define SNMP_ASN1_PDU_TRAP 4 + +err_t snmp_asn1_dec_type(struct pbuf *p, u16_t ofs, u8_t *type); +err_t snmp_asn1_dec_length(struct pbuf *p, u16_t ofs, u8_t *octets_used, u16_t *length); +err_t snmp_asn1_dec_u32t(struct pbuf *p, u16_t ofs, u16_t len, u32_t *value); +err_t snmp_asn1_dec_s32t(struct pbuf *p, u16_t ofs, u16_t len, s32_t *value); +err_t snmp_asn1_dec_oid(struct pbuf *p, u16_t ofs, u16_t len, struct snmp_obj_id *oid); +err_t snmp_asn1_dec_raw(struct pbuf *p, u16_t ofs, u16_t len, u16_t raw_len, u8_t *raw); + +void snmp_asn1_enc_length_cnt(u16_t length, u8_t *octets_needed); +void snmp_asn1_enc_u32t_cnt(u32_t value, u16_t *octets_needed); +void snmp_asn1_enc_s32t_cnt(s32_t value, u16_t *octets_needed); +void snmp_asn1_enc_oid_cnt(u8_t ident_len, s32_t *ident, u16_t *octets_needed); +err_t snmp_asn1_enc_type(struct pbuf *p, u16_t ofs, u8_t type); +err_t snmp_asn1_enc_length(struct pbuf *p, u16_t ofs, u16_t length); +err_t snmp_asn1_enc_u32t(struct pbuf *p, u16_t ofs, u8_t octets_needed, u32_t value); +err_t snmp_asn1_enc_s32t(struct pbuf *p, u16_t ofs, u8_t octets_needed, s32_t value); +err_t snmp_asn1_enc_oid(struct pbuf *p, u16_t ofs, u8_t ident_len, s32_t *ident); +err_t snmp_asn1_enc_raw(struct pbuf *p, u16_t ofs, u8_t raw_len, u8_t *raw); + +#endif diff --git a/20080212/Demo/Common/ethernet/lwIP/include/lwip/snmp_msg.h b/20080212/Demo/Common/ethernet/lwIP/include/lwip/snmp_msg.h new file mode 100644 index 000000000..4d91d3046 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/include/lwip/snmp_msg.h @@ -0,0 +1,292 @@ +/** + * @file + * SNMP Agent message handling structures. + */ + +/* + * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Christiaan Simons + */ + +#ifndef __LWIP_SNMP_MSG_H__ +#define __LWIP_SNMP_MSG_H__ + +#include "lwip/opt.h" +#include "arch/cc.h" +#include "lwip/snmp.h" +#include "lwip/snmp_structs.h" + +#if SNMP_PRIVATE_MIB +#include "private_mib.h" +#endif + +#define SNMP_IN_PORT 161 +#define SNMP_TRAP_PORT 162 + +#define SNMP_ES_NOERROR 0 +#define SNMP_ES_TOOBIG 1 +#define SNMP_ES_NOSUCHNAME 2 +#define SNMP_ES_BADVALUE 3 +#define SNMP_ES_READONLY 4 +#define SNMP_ES_GENERROR 5 + +#define SNMP_GENTRAP_COLDSTART 0 +#define SNMP_GENTRAP_WARMSTART 1 +#define SNMP_GENTRAP_AUTHFAIL 4 +#define SNMP_GENTRAP_ENTERPRISESPC 6 + +struct snmp_varbind +{ + /* next pointer, NULL for last in list */ + struct snmp_varbind *next; + /* previous pointer, NULL for first in list */ + struct snmp_varbind *prev; + + /* object identifier length (in s32_t) */ + u8_t ident_len; + /* object identifier array */ + s32_t *ident; + + /* object value ASN1 type */ + u8_t value_type; + /* object value length (in u8_t) */ + u8_t value_len; + /* object value */ + void *value; + + /* encoding varbind seq length length */ + u8_t seqlenlen; + /* encoding object identifier length length */ + u8_t olenlen; + /* encoding object value length length */ + u8_t vlenlen; + /* encoding varbind seq length */ + u16_t seqlen; + /* encoding object identifier length */ + u16_t olen; + /* encoding object value length */ + u16_t vlen; +}; + +struct snmp_varbind_root +{ + struct snmp_varbind *head; + struct snmp_varbind *tail; + /* number of variable bindings in list */ + u8_t count; + /* encoding varbind-list seq length length */ + u8_t seqlenlen; + /* encoding varbind-list seq length */ + u16_t seqlen; +}; + +/** output response message header length fields */ +struct snmp_resp_header_lengths +{ + /* encoding error-index length length */ + u8_t erridxlenlen; + /* encoding error-status length length */ + u8_t errstatlenlen; + /* encoding request id length length */ + u8_t ridlenlen; + /* encoding pdu length length */ + u8_t pdulenlen; + /* encoding community length length */ + u8_t comlenlen; + /* encoding version length length */ + u8_t verlenlen; + /* encoding sequence length length */ + u8_t seqlenlen; + + /* encoding error-index length */ + u16_t erridxlen; + /* encoding error-status length */ + u16_t errstatlen; + /* encoding request id length */ + u16_t ridlen; + /* encoding pdu length */ + u16_t pdulen; + /* encoding community length */ + u16_t comlen; + /* encoding version length */ + u16_t verlen; + /* encoding sequence length */ + u16_t seqlen; +}; + +/** output response message header length fields */ +struct snmp_trap_header_lengths +{ + /* encoding timestamp length length */ + u8_t tslenlen; + /* encoding specific-trap length length */ + u8_t strplenlen; + /* encoding generic-trap length length */ + u8_t gtrplenlen; + /* encoding agent-addr length length */ + u8_t aaddrlenlen; + /* encoding enterprise-id length length */ + u8_t eidlenlen; + /* encoding pdu length length */ + u8_t pdulenlen; + /* encoding community length length */ + u8_t comlenlen; + /* encoding version length length */ + u8_t verlenlen; + /* encoding sequence length length */ + u8_t seqlenlen; + + /* encoding timestamp length */ + u16_t tslen; + /* encoding specific-trap length */ + u16_t strplen; + /* encoding generic-trap length */ + u16_t gtrplen; + /* encoding agent-addr length */ + u16_t aaddrlen; + /* encoding enterprise-id length */ + u16_t eidlen; + /* encoding pdu length */ + u16_t pdulen; + /* encoding community length */ + u16_t comlen; + /* encoding version length */ + u16_t verlen; + /* encoding sequence length */ + u16_t seqlen; +}; + +/* Accepting new SNMP messages. */ +#define SNMP_MSG_EMPTY 0 +/* Search for matching object for variable binding. */ +#define SNMP_MSG_SEARCH_OBJ 1 +/* Perform SNMP operation on in-memory object. + Pass-through states, for symmetry only. */ +#define SNMP_MSG_INTERNAL_GET_OBJDEF 2 +#define SNMP_MSG_INTERNAL_GET_VALUE 3 +#define SNMP_MSG_INTERNAL_SET_TEST 4 +#define SNMP_MSG_INTERNAL_GET_OBJDEF_S 5 +#define SNMP_MSG_INTERNAL_SET_VALUE 6 +/* Perform SNMP operation on object located externally. + In theory this could be used for building a proxy agent. + Practical use is for an enterprise spc. app. gateway. */ +#define SNMP_MSG_EXTERNAL_GET_OBJDEF 7 +#define SNMP_MSG_EXTERNAL_GET_VALUE 8 +#define SNMP_MSG_EXTERNAL_SET_TEST 9 +#define SNMP_MSG_EXTERNAL_GET_OBJDEF_S 10 +#define SNMP_MSG_EXTERNAL_SET_VALUE 11 + +#define SNMP_COMMUNITY_STR_LEN 64 +struct snmp_msg_pstat +{ + /* lwIP local port (161) binding */ + struct udp_pcb *pcb; + /* source IP address */ + struct ip_addr sip; + /* source UDP port */ + u16_t sp; + /* request type */ + u8_t rt; + /* request ID */ + s32_t rid; + /* error status */ + s32_t error_status; + /* error index */ + s32_t error_index; + /* community name (zero terminated) */ + u8_t community[SNMP_COMMUNITY_STR_LEN + 1]; + /* community string length (exclusive zero term) */ + u8_t com_strlen; + /* one out of MSG_EMPTY, MSG_DEMUX, MSG_INTERNAL, MSG_EXTERNAL_x */ + u8_t state; + /* saved arguments for MSG_EXTERNAL_x */ + struct mib_external_node *ext_mib_node; + struct snmp_name_ptr ext_name_ptr; + struct obj_def ext_object_def; + struct snmp_obj_id ext_oid; + /* index into input variable binding list */ + u8_t vb_idx; + /* ptr into input variable binding list */ + struct snmp_varbind *vb_ptr; + /* list of variable bindings from input */ + struct snmp_varbind_root invb; + /* list of variable bindings to output */ + struct snmp_varbind_root outvb; + /* output response lengths used in ASN encoding */ + struct snmp_resp_header_lengths rhl; +}; + +struct snmp_msg_trap +{ + /* lwIP local port (161) binding */ + struct udp_pcb *pcb; + /* destination IP address in network order */ + struct ip_addr dip; + + /* source enterprise ID (sysObjectID) */ + struct snmp_obj_id *enterprise; + /* source IP address, raw network order format */ + u8_t sip_raw[4]; + /* generic trap code */ + u32_t gen_trap; + /* specific trap code */ + u32_t spc_trap; + /* timestamp */ + u32_t ts; + /* list of variable bindings to output */ + struct snmp_varbind_root outvb; + /* output trap lengths used in ASN encoding */ + struct snmp_trap_header_lengths thl; +}; + +/** Agent Version constant, 0 = v1 oddity */ +extern const s32_t snmp_version; +/** Agent default "public" community string */ +extern const char snmp_publiccommunity[7]; + +extern struct snmp_msg_trap trap_msg; + +/** Agent setup, start listening to port 161. */ +void snmp_init(void); +void snmp_trap_dst_enable(u8_t dst_idx, u8_t enable); +void snmp_trap_dst_ip_set(u8_t dst_idx, struct ip_addr *dst); + +/** Varbind-list functions. */ +struct snmp_varbind* snmp_varbind_alloc(struct snmp_obj_id *oid, u8_t type, u8_t len); +void snmp_varbind_free(struct snmp_varbind *vb); +void snmp_varbind_list_free(struct snmp_varbind_root *root); +void snmp_varbind_tail_add(struct snmp_varbind_root *root, struct snmp_varbind *vb); +struct snmp_varbind* snmp_varbind_tail_remove(struct snmp_varbind_root *root); + +/** Handle an internal (recv) or external (private response) event. */ +void snmp_msg_event(u8_t request_id); +err_t snmp_send_response(struct snmp_msg_pstat *m_stat); +err_t snmp_send_trap(s8_t generic_trap, struct snmp_obj_id *eoid, s32_t specific_trap); +void snmp_coldstart_trap(void); +void snmp_authfail_trap(void); + +#endif diff --git a/20080212/Demo/Common/ethernet/lwIP/include/lwip/snmp_structs.h b/20080212/Demo/Common/ethernet/lwIP/include/lwip/snmp_structs.h new file mode 100644 index 000000000..f76632e1d --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/include/lwip/snmp_structs.h @@ -0,0 +1,253 @@ +/** + * @file + * Generic MIB tree structures. + * + * @todo namespace prefixes + */ + +/* + * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Christiaan Simons + */ + +#ifndef __LWIP_SNMP_STRUCTS_H__ +#define __LWIP_SNMP_STRUCTS_H__ + +#include "lwip/opt.h" +#if LWIP_SNMP + +#include "arch/cc.h" +#include "lwip/snmp.h" + +#if SNMP_PRIVATE_MIB +#include "private_mib.h" +#endif + +/* MIB object instance */ +#define MIB_OBJECT_NONE 0 +#define MIB_OBJECT_SCALAR 1 +#define MIB_OBJECT_TAB 2 + +/* MIB object access */ +#define MIB_OBJECT_READ_ONLY 0 +#define MIB_OBJECT_READ_WRITE 1 +#define MIB_OBJECT_WRITE_ONLY 2 +#define MIB_OBJECT_NOT_ACCESSIBLE 3 + +/** object definition returned by (get_object_def)() */ +struct obj_def +{ + /* MIB_OBJECT_NONE (0), MIB_OBJECT_SCALAR (1), MIB_OBJECT_TAB (2) */ + u8_t instance; + /* 0 read-only, 1 read-write, 2 write-only, 3 not-accessible */ + u8_t access; + /* ASN type for this object */ + u8_t asn_type; + /* value length (host length) */ + u16_t v_len; + /* length of instance part of supplied object identifier */ + u8_t id_inst_len; + /* instance part of supplied object identifier */ + s32_t *id_inst_ptr; +}; + +struct snmp_name_ptr +{ + u8_t ident_len; + s32_t *ident; +}; + +/** MIB const scalar (.0) node */ +#define MIB_NODE_SC 0x01 +/** MIB const array node */ +#define MIB_NODE_AR 0x02 +/** MIB array node (mem_malloced from RAM) */ +#define MIB_NODE_RA 0x03 +/** MIB list root node (mem_malloced from RAM) */ +#define MIB_NODE_LR 0x04 +/** MIB node for external objects */ +#define MIB_NODE_EX 0x05 + +/** node "base class" layout, the mandatory fields for a node */ +struct mib_node +{ + /** returns struct obj_def for the given object identifier */ + void (*get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od); + /** returns object value for the given object identifier, + @note the caller must allocate at least len bytes for the value */ + void (*get_value)(struct obj_def *od, u16_t len, void *value); + /** tests length and/or range BEFORE setting */ + u8_t (*set_test)(struct obj_def *od, u16_t len, void *value); + /** sets object value, only to be called when set_test() */ + void (*set_value)(struct obj_def *od, u16_t len, void *value); + /** One out of MIB_NODE_AR, MIB_NODE_LR or MIB_NODE_EX */ + const u8_t node_type; + /* array or max list length */ + const u16_t maxlength; +}; + +/** derived node for scalars .0 index */ +typedef struct mib_node mib_scalar_node; + +/** derived node, points to a fixed size const array + of sub-identifiers plus a 'child' pointer */ +struct mib_array_node +{ + /* inherited "base class" members */ + void (* const get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od); + void (* const get_value)(struct obj_def *od, u16_t len, void *value); + u8_t (*set_test)(struct obj_def *od, u16_t len, void *value); + void (*set_value)(struct obj_def *od, u16_t len, void *value); + + const u8_t node_type; + const u16_t maxlength; + + /* aditional struct members */ + const s32_t *objid; + struct mib_node* const *nptr; +}; + +/** derived node, points to a fixed size mem_malloced array + of sub-identifiers plus a 'child' pointer */ +struct mib_ram_array_node +{ + /* inherited "base class" members */ + void (*get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od); + void (*get_value)(struct obj_def *od, u16_t len, void *value); + u8_t (*set_test)(struct obj_def *od, u16_t len, void *value); + void (*set_value)(struct obj_def *od, u16_t len, void *value); + + u8_t node_type; + u16_t maxlength; + + /* aditional struct members */ + s32_t *objid; + struct mib_node **nptr; +}; + +struct mib_list_node +{ + struct mib_list_node *prev; + struct mib_list_node *next; + s32_t objid; + struct mib_node *nptr; +}; + +/** derived node, points to a doubly linked list + of sub-identifiers plus a 'child' pointer */ +struct mib_list_rootnode +{ + /* inherited "base class" members */ + void (*get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od); + void (*get_value)(struct obj_def *od, u16_t len, void *value); + u8_t (*set_test)(struct obj_def *od, u16_t len, void *value); + void (*set_value)(struct obj_def *od, u16_t len, void *value); + + u8_t node_type; + u16_t maxlength; + + /* aditional struct members */ + struct mib_list_node *head; + struct mib_list_node *tail; + /* counts list nodes in list */ + u16_t count; +}; + +/** derived node, has access functions for mib object in external memory or device + using 'tree_level' and 'idx', with a range 0 .. (level_length() - 1) */ +struct mib_external_node +{ + /* inherited "base class" members */ + void (*get_object_def)(u8_t ident_len, s32_t *ident, struct obj_def *od); + void (*get_value)(struct obj_def *od, u16_t len, void *value); + u8_t (*set_test)(struct obj_def *od, u16_t len, void *value); + void (*set_value)(struct obj_def *od, u16_t len, void *value); + + u8_t node_type; + u16_t maxlength; + + /* aditional struct members */ + /** points to an extenal (in memory) record of some sort of addressing + information, passed to and interpreted by the funtions below */ + void* addr_inf; + /** tree levels under this node */ + u8_t tree_levels; + /** number of objects at this level */ + u16_t (*level_length)(void* addr_inf, u8_t level); + /** compares object sub identifier with external id + return zero when equal, nonzero when unequal */ + s32_t (*ident_cmp)(void* addr_inf, u8_t level, u16_t idx, s32_t sub_id); + void (*get_objid)(void* addr_inf, u8_t level, u16_t idx, s32_t *sub_id); + + /** async Questions */ + void (*get_object_def_q)(void* addr_inf, u8_t rid, u8_t ident_len, s32_t *ident); + void (*get_value_q)(u8_t rid, struct obj_def *od); + void (*set_test_q)(u8_t rid, struct obj_def *od); + void (*set_value_q)(u8_t rid, struct obj_def *od, u16_t len, void *value); + /** async Answers */ + void (*get_object_def_a)(u8_t rid, u8_t ident_len, s32_t *ident, struct obj_def *od); + void (*get_value_a)(u8_t rid, struct obj_def *od, u16_t len, void *value); + u8_t (*set_test_a)(u8_t rid, struct obj_def *od, u16_t len, void *value); + void (*set_value_a)(u8_t rid, struct obj_def *od, u16_t len, void *value); + /** async Panic Close (agent returns error reply, + e.g. used for external transaction cleanup) */ + void (*get_object_def_pc)(u8_t rid, u8_t ident_len, s32_t *ident); + void (*get_value_pc)(u8_t rid, struct obj_def *od); + void (*set_test_pc)(u8_t rid, struct obj_def *od); + void (*set_value_pc)(u8_t rid, struct obj_def *od); +}; + +/** export MIB tree from mib2.c */ +extern const struct mib_array_node internet; + +/** dummy function pointers for non-leaf MIB nodes from mib2.c */ +void noleafs_get_object_def(u8_t ident_len, s32_t *ident, struct obj_def *od); +void noleafs_get_value(struct obj_def *od, u16_t len, void *value); +u8_t noleafs_set_test(struct obj_def *od, u16_t len, void *value); +void noleafs_set_value(struct obj_def *od, u16_t len, void *value); + +void snmp_oidtoip(s32_t *ident, struct ip_addr *ip); +void snmp_iptooid(struct ip_addr *ip, s32_t *ident); +void snmp_ifindextonetif(s32_t ifindex, struct netif **netif); +void snmp_netiftoifindex(struct netif *netif, s32_t *ifidx); + +struct mib_list_node* snmp_mib_ln_alloc(s32_t id); +void snmp_mib_ln_free(struct mib_list_node *ln); +struct mib_list_rootnode* snmp_mib_lrn_alloc(void); +void snmp_mib_lrn_free(struct mib_list_rootnode *lrn); + +s8_t snmp_mib_node_insert(struct mib_list_rootnode *rn, s32_t objid, struct mib_list_node **insn); +s8_t snmp_mib_node_find(struct mib_list_rootnode *rn, s32_t objid, struct mib_list_node **fn); +struct mib_list_rootnode *snmp_mib_node_delete(struct mib_list_rootnode *rn, struct mib_list_node *n); + +struct mib_node* snmp_search_tree(struct mib_node *node, u8_t ident_len, s32_t *ident, struct snmp_name_ptr *np); +struct mib_node* snmp_expand_tree(struct mib_node *node, u8_t ident_len, s32_t *ident, struct snmp_obj_id *oidret); +u8_t snmp_iso_prefix_tst(u8_t ident_len, s32_t *ident); +u8_t snmp_iso_prefix_expand(u8_t ident_len, s32_t *ident, struct snmp_obj_id *oidret); + +#endif /* LWIP_SNMP */ +#endif diff --git a/20080212/Demo/Common/ethernet/lwIP/include/lwip/sockets.h b/20080212/Demo/Common/ethernet/lwIP/include/lwip/sockets.h new file mode 100644 index 000000000..9c25035ad --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/include/lwip/sockets.h @@ -0,0 +1,271 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + + +#ifndef __LWIP_SOCKETS_H__ +#define __LWIP_SOCKETS_H__ +#include "lwip/ip_addr.h" + +struct sockaddr_in { + u8_t sin_len; + u8_t sin_family; + u16_t sin_port; + struct in_addr sin_addr; + char sin_zero[8]; +}; + +struct sockaddr { + u8_t sa_len; + u8_t sa_family; + char sa_data[14]; +}; + +#ifndef socklen_t +# define socklen_t int +#endif + + +#define SOCK_STREAM 1 +#define SOCK_DGRAM 2 +#define SOCK_RAW 3 + +/* + * Option flags per-socket. + */ +#define SO_DEBUG 0x0001 /* turn on debugging info recording */ +#define SO_ACCEPTCONN 0x0002 /* socket has had listen() */ +#define SO_REUSEADDR 0x0004 /* allow local address reuse */ +#define SO_KEEPALIVE 0x0008 /* keep connections alive */ +#define SO_DONTROUTE 0x0010 /* just use interface addresses */ +#define SO_BROADCAST 0x0020 /* permit sending of broadcast msgs */ +#define SO_USELOOPBACK 0x0040 /* bypass hardware when possible */ +#define SO_LINGER 0x0080 /* linger on close if data present */ +#define SO_OOBINLINE 0x0100 /* leave received OOB data in line */ +#define SO_REUSEPORT 0x0200 /* allow local address & port reuse */ + +#define SO_DONTLINGER (int)(~SO_LINGER) + +/* + * Additional options, not kept in so_options. + */ +#define SO_SNDBUF 0x1001 /* send buffer size */ +#define SO_RCVBUF 0x1002 /* receive buffer size */ +#define SO_SNDLOWAT 0x1003 /* send low-water mark */ +#define SO_RCVLOWAT 0x1004 /* receive low-water mark */ +#define SO_SNDTIMEO 0x1005 /* send timeout */ +#define SO_RCVTIMEO 0x1006 /* receive timeout */ +#define SO_ERROR 0x1007 /* get error status and clear */ +#define SO_TYPE 0x1008 /* get socket type */ + + + +/* + * Structure used for manipulating linger option. + */ +struct linger { + int l_onoff; /* option on/off */ + int l_linger; /* linger time */ +}; + +/* + * Level number for (get/set)sockopt() to apply to socket itself. + */ +#define SOL_SOCKET 0xfff /* options for socket level */ + + +#define AF_UNSPEC 0 +#define AF_INET 2 +#define PF_INET AF_INET +#define PF_UNSPEC AF_UNSPEC + +#define IPPROTO_IP 0 +#define IPPROTO_TCP 6 +#define IPPROTO_UDP 17 + +#define INADDR_ANY 0 +#define INADDR_BROADCAST 0xffffffff + +/* Flags we can use with send and recv. */ +#define MSG_DONTWAIT 0x40 /* Nonblocking i/o for this operation only */ + + +/* + * Options for level IPPROTO_IP + */ +#define IP_TOS 1 +#define IP_TTL 2 + + +#define IPTOS_TOS_MASK 0x1E +#define IPTOS_TOS(tos) ((tos) & IPTOS_TOS_MASK) +#define IPTOS_LOWDELAY 0x10 +#define IPTOS_THROUGHPUT 0x08 +#define IPTOS_RELIABILITY 0x04 +#define IPTOS_LOWCOST 0x02 +#define IPTOS_MINCOST IPTOS_LOWCOST + +/* + * Definitions for IP precedence (also in ip_tos) (hopefully unused) + */ +#define IPTOS_PREC_MASK 0xe0 +#define IPTOS_PREC(tos) ((tos) & IPTOS_PREC_MASK) +#define IPTOS_PREC_NETCONTROL 0xe0 +#define IPTOS_PREC_INTERNETCONTROL 0xc0 +#define IPTOS_PREC_CRITIC_ECP 0xa0 +#define IPTOS_PREC_FLASHOVERRIDE 0x80 +#define IPTOS_PREC_FLASH 0x60 +#define IPTOS_PREC_IMMEDIATE 0x40 +#define IPTOS_PREC_PRIORITY 0x20 +#define IPTOS_PREC_ROUTINE 0x00 + + +/* + * Commands for ioctlsocket(), taken from the BSD file fcntl.h. + * + * + * Ioctl's have the command encoded in the lower word, + * and the size of any in or out parameters in the upper + * word. The high 2 bits of the upper word are used + * to encode the in/out status of the parameter; for now + * we restrict parameters to at most 128 bytes. + */ +#if !defined(FIONREAD) || !defined(FIONBIO) +#define IOCPARM_MASK 0x7f /* parameters must be < 128 bytes */ +#define IOC_VOID 0x20000000 /* no parameters */ +#define IOC_OUT 0x40000000 /* copy out parameters */ +#define IOC_IN 0x80000000 /* copy in parameters */ +#define IOC_INOUT (IOC_IN|IOC_OUT) + /* 0x20000000 distinguishes new & + old ioctl's */ +#define _IO(x,y) (IOC_VOID|((x)<<8)|(y)) + +#define _IOR(x,y,t) (IOC_OUT|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y)) + +#define _IOW(x,y,t) (IOC_IN|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y)) +#endif + +#ifndef FIONREAD +#define FIONREAD _IOR('f', 127, unsigned long) /* get # bytes to read */ +#endif +#ifndef FIONBIO +#define FIONBIO _IOW('f', 126, unsigned long) /* set/clear non-blocking i/o */ +#endif + +/* Socket I/O Controls */ +#ifndef SIOCSHIWAT +#define SIOCSHIWAT _IOW('s', 0, unsigned long) /* set high watermark */ +#define SIOCGHIWAT _IOR('s', 1, unsigned long) /* get high watermark */ +#define SIOCSLOWAT _IOW('s', 2, unsigned long) /* set low watermark */ +#define SIOCGLOWAT _IOR('s', 3, unsigned long) /* get low watermark */ +#define SIOCATMARK _IOR('s', 7, unsigned long) /* at oob mark? */ +#endif + +#ifndef O_NONBLOCK +#define O_NONBLOCK 04000U +#endif + +#ifndef FD_SET + #undef FD_SETSIZE + #define FD_SETSIZE 16 + #define FD_SET(n, p) ((p)->fd_bits[(n)/8] |= (1 << ((n) & 7))) + #define FD_CLR(n, p) ((p)->fd_bits[(n)/8] &= ~(1 << ((n) & 7))) + #define FD_ISSET(n,p) ((p)->fd_bits[(n)/8] & (1 << ((n) & 7))) + #define FD_ZERO(p) memset((void*)(p),0,sizeof(*(p))) + + typedef struct fd_set { + unsigned char fd_bits [(FD_SETSIZE+7)/8]; + } fd_set; + +/* + * only define this in sockets.c so it does not interfere + * with other projects namespaces where timeval is present + */ +#ifndef LWIP_TIMEVAL_PRIVATE +#define LWIP_TIMEVAL_PRIVATE 1 +#endif + +#if LWIP_TIMEVAL_PRIVATE + struct timeval { + long tv_sec; /* seconds */ + long tv_usec; /* and microseconds */ + }; +#endif + +#endif + +int lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen); +int lwip_bind(int s, struct sockaddr *name, socklen_t namelen); +int lwip_shutdown(int s, int how); +int lwip_getpeername (int s, struct sockaddr *name, socklen_t *namelen); +int lwip_getsockname (int s, struct sockaddr *name, socklen_t *namelen); +int lwip_getsockopt (int s, int level, int optname, void *optval, socklen_t *optlen); +int lwip_setsockopt (int s, int level, int optname, const void *optval, socklen_t optlen); +int lwip_close(int s); +int lwip_connect(int s, struct sockaddr *name, socklen_t namelen); +int lwip_listen(int s, int backlog); +int lwip_recv(int s, void *mem, int len, unsigned int flags); +int lwip_read(int s, void *mem, int len); +int lwip_recvfrom(int s, void *mem, int len, unsigned int flags, + struct sockaddr *from, socklen_t *fromlen); +int lwip_send(int s, void *dataptr, int size, unsigned int flags); +int lwip_sendto(int s, void *dataptr, int size, unsigned int flags, + struct sockaddr *to, socklen_t tolen); +int lwip_socket(int domain, int type, int protocol); +int lwip_write(int s, void *dataptr, int size); +int lwip_select(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset, + struct timeval *timeout); +int lwip_ioctl(int s, long cmd, void *argp); + +#if LWIP_COMPAT_SOCKETS +#define accept(a,b,c) lwip_accept(a,b,c) +#define bind(a,b,c) lwip_bind(a,b,c) +#define shutdown(a,b) lwip_shutdown(a,b) +#define close(s) lwip_close(s) +#define connect(a,b,c) lwip_connect(a,b,c) +#define getsockname(a,b,c) lwip_getsockname(a,b,c) +#define getpeername(a,b,c) lwip_getpeername(a,b,c) +#define setsockopt(a,b,c,d,e) lwip_setsockopt(a,b,c,d,e) +#define getsockopt(a,b,c,d,e) lwip_getsockopt(a,b,c,d,e) +#define listen(a,b) lwip_listen(a,b) +#define recv(a,b,c,d) lwip_recv(a,b,c,d) +#define read(a,b,c) lwip_read(a,b,c) +#define recvfrom(a,b,c,d,e,f) lwip_recvfrom(a,b,c,d,e,f) +#define send(a,b,c,d) lwip_send(a,b,c,d) +#define sendto(a,b,c,d,e,f) lwip_sendto(a,b,c,d,e,f) +#define socket(a,b,c) lwip_socket(a,b,c) +#define write(a,b,c) lwip_write(a,b,c) +#define select(a,b,c,d,e) lwip_select(a,b,c,d,e) +#define ioctlsocket(a,b,c) lwip_ioctl(a,b,c) +#endif /* LWIP_COMPAT_SOCKETS */ + +#endif /* __LWIP_SOCKETS_H__ */ + diff --git a/20080212/Demo/Common/ethernet/lwIP/include/lwip/stats.h b/20080212/Demo/Common/ethernet/lwIP/include/lwip/stats.h new file mode 100644 index 000000000..29dfd5731 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/include/lwip/stats.h @@ -0,0 +1,158 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_STATS_H__ +#define __LWIP_STATS_H__ + +#include "lwip/opt.h" +#include "arch/cc.h" + +#include "lwip/mem.h" +#include "lwip/memp.h" + +#if LWIP_STATS + +struct stats_proto { + u16_t xmit; /* Transmitted packets. */ + u16_t rexmit; /* Retransmitted packets. */ + u16_t recv; /* Received packets. */ + u16_t fw; /* Forwarded packets. */ + u16_t drop; /* Dropped packets. */ + u16_t chkerr; /* Checksum error. */ + u16_t lenerr; /* Invalid length error. */ + u16_t memerr; /* Out of memory error. */ + u16_t rterr; /* Routing error. */ + u16_t proterr; /* Protocol error. */ + u16_t opterr; /* Error in options. */ + u16_t err; /* Misc error. */ + u16_t cachehit; +}; + +struct stats_mem { + mem_size_t avail; + mem_size_t used; + mem_size_t max; + mem_size_t err; +}; + +struct stats_pbuf { + u16_t avail; + u16_t used; + u16_t max; + u16_t err; + + u16_t alloc_locked; + u16_t refresh_locked; +}; + +struct stats_syselem { + u16_t used; + u16_t max; + u16_t err; +}; + +struct stats_sys { + struct stats_syselem sem; + struct stats_syselem mbox; +}; + +struct stats_ { + struct stats_proto link; + struct stats_proto ip_frag; + struct stats_proto ip; + struct stats_proto icmp; + struct stats_proto udp; + struct stats_proto tcp; + struct stats_pbuf pbuf; + struct stats_mem mem; + struct stats_mem memp[MEMP_MAX]; + struct stats_sys sys; +}; + +extern struct stats_ lwip_stats; + + +void stats_init(void); + +#define STATS_INC(x) ++lwip_stats.x +#else +#define stats_init() +#define STATS_INC(x) +#endif /* LWIP_STATS */ + +#if TCP_STATS +#define TCP_STATS_INC(x) STATS_INC(x) +#else +#define TCP_STATS_INC(x) +#endif + +#if UDP_STATS +#define UDP_STATS_INC(x) STATS_INC(x) +#else +#define UDP_STATS_INC(x) +#endif + +#if ICMP_STATS +#define ICMP_STATS_INC(x) STATS_INC(x) +#else +#define ICMP_STATS_INC(x) +#endif + +#if IP_STATS +#define IP_STATS_INC(x) STATS_INC(x) +#else +#define IP_STATS_INC(x) +#endif + +#if IPFRAG_STATS +#define IPFRAG_STATS_INC(x) STATS_INC(x) +#else +#define IPFRAG_STATS_INC(x) +#endif + +#if LINK_STATS +#define LINK_STATS_INC(x) STATS_INC(x) +#else +#define LINK_STATS_INC(x) +#endif + +/* Display of statistics */ +#if LWIP_STATS_DISPLAY +void stats_display(void); +#else +#define stats_display() +#endif + +#endif /* __LWIP_STATS_H__ */ + + + + diff --git a/20080212/Demo/Common/ethernet/lwIP/include/lwip/sys.h b/20080212/Demo/Common/ethernet/lwIP/include/lwip/sys.h new file mode 100644 index 000000000..ce8d5ffbd --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/include/lwip/sys.h @@ -0,0 +1,183 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_SYS_H__ +#define __LWIP_SYS_H__ + +#include "arch/cc.h" + +#include "lwip/opt.h" + + +#if NO_SYS + +/* For a totally minimal and standalone system, we provide null + definitions of the sys_ functions. */ +typedef u8_t sys_sem_t; +typedef u8_t sys_mbox_t; +struct sys_timeo {u8_t dummy;}; + +#define sys_init() +#define sys_timeout(m,h,a) +#define sys_untimeout(m,a) +#define sys_sem_new(c) c +#define sys_sem_signal(s) +#define sys_sem_wait(s) +#define sys_sem_free(s) +#define sys_mbox_new() 0 +#define sys_mbox_fetch(m,d) +#define sys_mbox_post(m,d) +#define sys_mbox_free(m) + +#define sys_thread_new(t,a,p) + +#else /* NO_SYS */ + +#include "arch/sys_arch.h" + +/** Return code for timeouts from sys_arch_mbox_fetch and sys_arch_sem_wait */ +#define SYS_ARCH_TIMEOUT 0xffffffff + +typedef void (* sys_timeout_handler)(void *arg); + +struct sys_timeo { + struct sys_timeo *next; + u32_t time; + sys_timeout_handler h; + void *arg; +}; + +struct sys_timeouts { + struct sys_timeo *next; +}; + +/* sys_init() must be called before anthing else. */ +void sys_init(void); + +/* + * sys_timeout(): + * + * Schedule a timeout a specified amount of milliseconds in the + * future. When the timeout occurs, the specified timeout handler will + * be called. The handler will be passed the "arg" argument when + * called. + * + */ +void sys_timeout(u32_t msecs, sys_timeout_handler h, void *arg); +void sys_untimeout(sys_timeout_handler h, void *arg); +struct sys_timeouts *sys_arch_timeouts(void); + +/* Semaphore functions. */ +sys_sem_t sys_sem_new(u8_t count); +void sys_sem_signal(sys_sem_t sem); +u32_t sys_arch_sem_wait(sys_sem_t sem, u32_t timeout); +void sys_sem_free(sys_sem_t sem); +void sys_sem_wait(sys_sem_t sem); +int sys_sem_wait_timeout(sys_sem_t sem, u32_t timeout); + +/* Time functions. */ +#ifndef sys_msleep +void sys_msleep(u32_t ms); /* only has a (close to) 1 jiffy resolution. */ +#endif +#ifndef sys_jiffies +u32_t sys_jiffies(void); /* since power up. */ +#endif + +/* Mailbox functions. */ +sys_mbox_t sys_mbox_new(void); +void sys_mbox_post(sys_mbox_t mbox, void *msg); +u32_t sys_arch_mbox_fetch(sys_mbox_t mbox, void **msg, u32_t timeout); +void sys_mbox_free(sys_mbox_t mbox); +void sys_mbox_fetch(sys_mbox_t mbox, void **msg); + + +/* Thread functions. */ +sys_thread_t sys_thread_new(void (* thread)(void *arg), void *arg, int prio); + +/* The following functions are used only in Unix code, and + can be omitted when porting the stack. */ +/* Returns the current time in microseconds. */ +unsigned long sys_now(void); + +#endif /* NO_SYS */ + +/* Critical Region Protection */ +/* These functions must be implemented in the sys_arch.c file. + In some implementations they can provide a more light-weight protection + mechanism than using semaphores. Otherwise semaphores can be used for + implementation */ +#ifndef SYS_ARCH_PROTECT +/** SYS_LIGHTWEIGHT_PROT + * define SYS_LIGHTWEIGHT_PROT in lwipopts.h if you want inter-task protection + * for certain critical regions during buffer allocation, deallocation and memory + * allocation and deallocation. + */ +#if SYS_LIGHTWEIGHT_PROT + +/** SYS_ARCH_DECL_PROTECT + * declare a protection variable. This macro will default to defining a variable of + * type sys_prot_t. If a particular port needs a different implementation, then + * this macro may be defined in sys_arch.h. + */ +#define SYS_ARCH_DECL_PROTECT(lev) sys_prot_t lev +/** SYS_ARCH_PROTECT + * Perform a "fast" protect. This could be implemented by + * disabling interrupts for an embedded system or by using a semaphore or + * mutex. The implementation should allow calling SYS_ARCH_PROTECT when + * already protected. The old protection level is returned in the variable + * "lev". This macro will default to calling the sys_arch_protect() function + * which should be implemented in sys_arch.c. If a particular port needs a + * different implementation, then this macro may be defined in sys_arch.h + */ +#define SYS_ARCH_PROTECT(lev) lev = sys_arch_protect() +/** SYS_ARCH_UNPROTECT + * Perform a "fast" set of the protection level to "lev". This could be + * implemented by setting the interrupt level to "lev" within the MACRO or by + * using a semaphore or mutex. This macro will default to calling the + * sys_arch_unprotect() function which should be implemented in + * sys_arch.c. If a particular port needs a different implementation, then + * this macro may be defined in sys_arch.h + */ +#define SYS_ARCH_UNPROTECT(lev) sys_arch_unprotect(lev) +sys_prot_t sys_arch_protect(void); +void sys_arch_unprotect(sys_prot_t pval); + +#else + +#define SYS_ARCH_DECL_PROTECT(lev) +#define SYS_ARCH_PROTECT(lev) +#define SYS_ARCH_UNPROTECT(lev) + +#endif /* SYS_LIGHTWEIGHT_PROT */ + +#endif /* SYS_ARCH_PROTECT */ + +#endif /* __LWIP_SYS_H__ */ diff --git a/20080212/Demo/Common/ethernet/lwIP/include/lwip/tcp.h b/20080212/Demo/Common/ethernet/lwIP/include/lwip/tcp.h new file mode 100644 index 000000000..b4f78bf56 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/include/lwip/tcp.h @@ -0,0 +1,531 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_TCP_H__ +#define __LWIP_TCP_H__ + +#include "lwip/sys.h" +#include "lwip/mem.h" + +#include "lwip/pbuf.h" +#include "lwip/opt.h" +#include "lwip/ip.h" +#include "lwip/icmp.h" + +#include "lwip/err.h" + +struct tcp_pcb; + +/* Functions for interfacing with TCP: */ + +/* Lower layer interface to TCP: */ +void tcp_init (void); /* Must be called first to + initialize TCP. */ +void tcp_tmr (void); /* Must be called every + TCP_TMR_INTERVAL + ms. (Typically 250 ms). */ +/* Application program's interface: */ +struct tcp_pcb * tcp_new (void); +struct tcp_pcb * tcp_alloc (u8_t prio); + +void tcp_arg (struct tcp_pcb *pcb, void *arg); +void tcp_accept (struct tcp_pcb *pcb, + err_t (* accept)(void *arg, struct tcp_pcb *newpcb, + err_t err)); +void tcp_recv (struct tcp_pcb *pcb, + err_t (* recv)(void *arg, struct tcp_pcb *tpcb, + struct pbuf *p, err_t err)); +void tcp_sent (struct tcp_pcb *pcb, + err_t (* sent)(void *arg, struct tcp_pcb *tpcb, + u16_t len)); +void tcp_poll (struct tcp_pcb *pcb, + err_t (* poll)(void *arg, struct tcp_pcb *tpcb), + u8_t interval); +void tcp_err (struct tcp_pcb *pcb, + void (* err)(void *arg, err_t err)); + +#define tcp_mss(pcb) ((pcb)->mss) +#define tcp_sndbuf(pcb) ((pcb)->snd_buf) + +void tcp_recved (struct tcp_pcb *pcb, u16_t len); +err_t tcp_bind (struct tcp_pcb *pcb, struct ip_addr *ipaddr, + u16_t port); +err_t tcp_connect (struct tcp_pcb *pcb, struct ip_addr *ipaddr, + u16_t port, err_t (* connected)(void *arg, + struct tcp_pcb *tpcb, + err_t err)); +struct tcp_pcb * tcp_listen (struct tcp_pcb *pcb); +void tcp_abort (struct tcp_pcb *pcb); +err_t tcp_close (struct tcp_pcb *pcb); +err_t tcp_write (struct tcp_pcb *pcb, const void *dataptr, u16_t len, + u8_t copy); + +void tcp_setprio (struct tcp_pcb *pcb, u8_t prio); + +#define TCP_PRIO_MIN 1 +#define TCP_PRIO_NORMAL 64 +#define TCP_PRIO_MAX 127 + +/* It is also possible to call these two functions at the right + intervals (instead of calling tcp_tmr()). */ +void tcp_slowtmr (void); +void tcp_fasttmr (void); + + +/* Only used by IP to pass a TCP segment to TCP: */ +void tcp_input (struct pbuf *p, struct netif *inp); +/* Used within the TCP code only: */ +err_t tcp_output (struct tcp_pcb *pcb); +void tcp_rexmit (struct tcp_pcb *pcb); +void tcp_rexmit_rto (struct tcp_pcb *pcb); + + + +#define TCP_SEQ_LT(a,b) ((s32_t)((a)-(b)) < 0) +#define TCP_SEQ_LEQ(a,b) ((s32_t)((a)-(b)) <= 0) +#define TCP_SEQ_GT(a,b) ((s32_t)((a)-(b)) > 0) +#define TCP_SEQ_GEQ(a,b) ((s32_t)((a)-(b)) >= 0) +/* is b<=a<=c? */ +#if 0 /* see bug #10548 */ +#define TCP_SEQ_BETWEEN(a,b,c) ((c)-(b) >= (a)-(b)) +#endif +#define TCP_SEQ_BETWEEN(a,b,c) (TCP_SEQ_GEQ(a,b) && TCP_SEQ_LEQ(a,c)) +#define TCP_FIN 0x01U +#define TCP_SYN 0x02U +#define TCP_RST 0x04U +#define TCP_PSH 0x08U +#define TCP_ACK 0x10U +#define TCP_URG 0x20U +#define TCP_ECE 0x40U +#define TCP_CWR 0x80U + +#define TCP_FLAGS 0x3fU + +/* Length of the TCP header, excluding options. */ +#define TCP_HLEN 20 + +#ifndef TCP_TMR_INTERVAL +#define TCP_TMR_INTERVAL 250 /* The TCP timer interval in + milliseconds. */ +#endif /* TCP_TMR_INTERVAL */ + +#ifndef TCP_FAST_INTERVAL +#define TCP_FAST_INTERVAL TCP_TMR_INTERVAL /* the fine grained timeout in + milliseconds */ +#endif /* TCP_FAST_INTERVAL */ + +#ifndef TCP_SLOW_INTERVAL +#define TCP_SLOW_INTERVAL (2*TCP_TMR_INTERVAL) /* the coarse grained timeout in + milliseconds */ +#endif /* TCP_SLOW_INTERVAL */ + +#define TCP_FIN_WAIT_TIMEOUT 20000 /* milliseconds */ +#define TCP_SYN_RCVD_TIMEOUT 20000 /* milliseconds */ + +#define TCP_OOSEQ_TIMEOUT 6U /* x RTO */ + +#define TCP_MSL 60000 /* The maximum segment lifetime in microseconds */ + +/* + * User-settable options (used with setsockopt). + */ +#define TCP_NODELAY 0x01 /* don't delay send to coalesce packets */ +#define TCP_KEEPALIVE 0x02 /* send KEEPALIVE probes when idle for pcb->keepalive miliseconds */ + +/* Keepalive values */ +#define TCP_KEEPDEFAULT 7200000 /* KEEPALIVE timer in miliseconds */ +#define TCP_KEEPINTVL 75000 /* Time between KEEPALIVE probes in miliseconds */ +#define TCP_KEEPCNT 9 /* Counter for KEEPALIVE probes */ +#define TCP_MAXIDLE TCP_KEEPCNT * TCP_KEEPINTVL /* Maximum KEEPALIVE probe time */ + + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct tcp_hdr { + PACK_STRUCT_FIELD(u16_t src); + PACK_STRUCT_FIELD(u16_t dest); + PACK_STRUCT_FIELD(u32_t seqno); + PACK_STRUCT_FIELD(u32_t ackno); + PACK_STRUCT_FIELD(u16_t _hdrlen_rsvd_flags); + PACK_STRUCT_FIELD(u16_t wnd); + PACK_STRUCT_FIELD(u16_t chksum); + PACK_STRUCT_FIELD(u16_t urgp); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#define TCPH_OFFSET(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) >> 8) +#define TCPH_HDRLEN(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) >> 12) +#define TCPH_FLAGS(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) & TCP_FLAGS) + +#define TCPH_OFFSET_SET(phdr, offset) (phdr)->_hdrlen_rsvd_flags = htons(((offset) << 8) | TCPH_FLAGS(phdr)) +#define TCPH_HDRLEN_SET(phdr, len) (phdr)->_hdrlen_rsvd_flags = htons(((len) << 12) | TCPH_FLAGS(phdr)) +#define TCPH_FLAGS_SET(phdr, flags) (phdr)->_hdrlen_rsvd_flags = htons((ntohs((phdr)->_hdrlen_rsvd_flags) & ~TCP_FLAGS) | (flags)) +#define TCPH_SET_FLAG(phdr, flags ) (phdr)->_hdrlen_rsvd_flags = htons(ntohs((phdr)->_hdrlen_rsvd_flags) | (flags)) +#define TCPH_UNSET_FLAG(phdr, flags) (phdr)->_hdrlen_rsvd_flags = htons(ntohs((phdr)->_hdrlen_rsvd_flags) | (TCPH_FLAGS(phdr) & ~(flags)) ) + +#define TCP_TCPLEN(seg) ((seg)->len + ((TCPH_FLAGS((seg)->tcphdr) & TCP_FIN || \ + TCPH_FLAGS((seg)->tcphdr) & TCP_SYN)? 1: 0)) + +enum tcp_state { + CLOSED = 0, + LISTEN = 1, + SYN_SENT = 2, + SYN_RCVD = 3, + ESTABLISHED = 4, + FIN_WAIT_1 = 5, + FIN_WAIT_2 = 6, + CLOSE_WAIT = 7, + CLOSING = 8, + LAST_ACK = 9, + TIME_WAIT = 10 +}; + +/* the TCP protocol control block */ +struct tcp_pcb { +/** common PCB members */ + IP_PCB; +/** protocol specific PCB members */ + struct tcp_pcb *next; /* for the linked list */ + enum tcp_state state; /* TCP state */ + u8_t prio; + void *callback_arg; + + u16_t local_port; + u16_t remote_port; + + u8_t flags; +#define TF_ACK_DELAY (u8_t)0x01U /* Delayed ACK. */ +#define TF_ACK_NOW (u8_t)0x02U /* Immediate ACK. */ +#define TF_INFR (u8_t)0x04U /* In fast recovery. */ +#define TF_RESET (u8_t)0x08U /* Connection was reset. */ +#define TF_CLOSED (u8_t)0x10U /* Connection was sucessfully closed. */ +#define TF_GOT_FIN (u8_t)0x20U /* Connection was closed by the remote end. */ +#define TF_NODELAY (u8_t)0x40U /* Disable Nagle algorithm */ + + /* receiver variables */ + u32_t rcv_nxt; /* next seqno expected */ + u16_t rcv_wnd; /* receiver window */ + + /* Timers */ + u32_t tmr; + u8_t polltmr, pollinterval; + + /* Retransmission timer. */ + u16_t rtime; + + u16_t mss; /* maximum segment size */ + + /* RTT (round trip time) estimation variables */ + u32_t rttest; /* RTT estimate in 500ms ticks */ + u32_t rtseq; /* sequence number being timed */ + s16_t sa, sv; /* @todo document this */ + + u16_t rto; /* retransmission time-out */ + u8_t nrtx; /* number of retransmissions */ + + /* fast retransmit/recovery */ + u32_t lastack; /* Highest acknowledged seqno. */ + u8_t dupacks; + + /* congestion avoidance/control variables */ + u16_t cwnd; + u16_t ssthresh; + + /* sender variables */ + u32_t snd_nxt, /* next seqno to be sent */ + snd_max, /* Highest seqno sent. */ + snd_wnd, /* sender window */ + snd_wl1, snd_wl2, /* Sequence and acknowledgement numbers of last + window update. */ + snd_lbb; /* Sequence number of next byte to be buffered. */ + + u16_t acked; + + u16_t snd_buf; /* Available buffer space for sending (in bytes). */ + u8_t snd_queuelen; /* Available buffer space for sending (in tcp_segs). */ + + + /* These are ordered by sequence number: */ + struct tcp_seg *unsent; /* Unsent (queued) segments. */ + struct tcp_seg *unacked; /* Sent but unacknowledged segments. */ +#if TCP_QUEUE_OOSEQ + struct tcp_seg *ooseq; /* Received out of sequence segments. */ +#endif /* TCP_QUEUE_OOSEQ */ + +#if LWIP_CALLBACK_API + /* Function to be called when more send buffer space is available. */ + err_t (* sent)(void *arg, struct tcp_pcb *pcb, u16_t space); + + /* Function to be called when (in-sequence) data has arrived. */ + err_t (* recv)(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err); + + /* Function to be called when a connection has been set up. */ + err_t (* connected)(void *arg, struct tcp_pcb *pcb, err_t err); + + /* Function to call when a listener has been connected. */ + err_t (* accept)(void *arg, struct tcp_pcb *newpcb, err_t err); + + /* Function which is called periodically. */ + err_t (* poll)(void *arg, struct tcp_pcb *pcb); + + /* Function to be called whenever a fatal error occurs. */ + void (* errf)(void *arg, err_t err); +#endif /* LWIP_CALLBACK_API */ + + /* idle time before KEEPALIVE is sent */ + u32_t keepalive; + + /* KEEPALIVE counter */ + u8_t keep_cnt; +}; + +struct tcp_pcb_listen { +/* Common members of all PCB types */ + IP_PCB; + +/* Protocol specific PCB members */ + struct tcp_pcb_listen *next; /* for the linked list */ + + /* Even if state is obviously LISTEN this is here for + * field compatibility with tpc_pcb to which it is cast sometimes + * Until a cleaner solution emerges this is here.FIXME + */ + enum tcp_state state; /* TCP state */ + + u8_t prio; + void *callback_arg; + + u16_t local_port; + +#if LWIP_CALLBACK_API + /* Function to call when a listener has been connected. */ + err_t (* accept)(void *arg, struct tcp_pcb *newpcb, err_t err); +#endif /* LWIP_CALLBACK_API */ +}; + +#if LWIP_EVENT_API + +enum lwip_event { + LWIP_EVENT_ACCEPT, + LWIP_EVENT_SENT, + LWIP_EVENT_RECV, + LWIP_EVENT_CONNECTED, + LWIP_EVENT_POLL, + LWIP_EVENT_ERR +}; + +err_t lwip_tcp_event(void *arg, struct tcp_pcb *pcb, + enum lwip_event, + struct pbuf *p, + u16_t size, + err_t err); + +#define TCP_EVENT_ACCEPT(pcb,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ + LWIP_EVENT_ACCEPT, NULL, 0, err) +#define TCP_EVENT_SENT(pcb,space,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ + LWIP_EVENT_SENT, NULL, space, ERR_OK) +#define TCP_EVENT_RECV(pcb,p,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ + LWIP_EVENT_RECV, (p), 0, (err)) +#define TCP_EVENT_CONNECTED(pcb,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ + LWIP_EVENT_CONNECTED, NULL, 0, (err)) +#define TCP_EVENT_POLL(pcb,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ + LWIP_EVENT_POLL, NULL, 0, ERR_OK) +#define TCP_EVENT_ERR(errf,arg,err) lwip_tcp_event((arg), NULL, \ + LWIP_EVENT_ERR, NULL, 0, (err)) +#else /* LWIP_EVENT_API */ +#define TCP_EVENT_ACCEPT(pcb,err,ret) \ + if((pcb)->accept != NULL) \ + (ret = (pcb)->accept((pcb)->callback_arg,(pcb),(err))) +#define TCP_EVENT_SENT(pcb,space,ret) \ + if((pcb)->sent != NULL) \ + (ret = (pcb)->sent((pcb)->callback_arg,(pcb),(space))) +#define TCP_EVENT_RECV(pcb,p,err,ret) \ + if((pcb)->recv != NULL) \ + { ret = (pcb)->recv((pcb)->callback_arg,(pcb),(p),(err)); } else { \ + if (p) pbuf_free(p); } +#define TCP_EVENT_CONNECTED(pcb,err,ret) \ + if((pcb)->connected != NULL) \ + (ret = (pcb)->connected((pcb)->callback_arg,(pcb),(err))) +#define TCP_EVENT_POLL(pcb,ret) \ + if((pcb)->poll != NULL) \ + (ret = (pcb)->poll((pcb)->callback_arg,(pcb))) +#define TCP_EVENT_ERR(errf,arg,err) \ + if((errf) != NULL) \ + (errf)((arg),(err)) +#endif /* LWIP_EVENT_API */ + +/* This structure represents a TCP segment on the unsent and unacked queues */ +struct tcp_seg { + struct tcp_seg *next; /* used when putting segements on a queue */ + struct pbuf *p; /* buffer containing data + TCP header */ + void *dataptr; /* pointer to the TCP data in the pbuf */ + u16_t len; /* the TCP length of this segment */ + struct tcp_hdr *tcphdr; /* the TCP header */ +}; + +/* Internal functions and global variables: */ +struct tcp_pcb *tcp_pcb_copy(struct tcp_pcb *pcb); +void tcp_pcb_purge(struct tcp_pcb *pcb); +void tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb); + +u8_t tcp_segs_free(struct tcp_seg *seg); +u8_t tcp_seg_free(struct tcp_seg *seg); +struct tcp_seg *tcp_seg_copy(struct tcp_seg *seg); + +#define tcp_ack(pcb) if((pcb)->flags & TF_ACK_DELAY) { \ + (pcb)->flags &= ~TF_ACK_DELAY; \ + (pcb)->flags |= TF_ACK_NOW; \ + tcp_output(pcb); \ + } else { \ + (pcb)->flags |= TF_ACK_DELAY; \ + } + +#define tcp_ack_now(pcb) (pcb)->flags |= TF_ACK_NOW; \ + tcp_output(pcb) + +err_t tcp_send_ctrl(struct tcp_pcb *pcb, u8_t flags); +err_t tcp_enqueue(struct tcp_pcb *pcb, void *dataptr, u16_t len, + u8_t flags, u8_t copy, + u8_t *optdata, u8_t optlen); + +void tcp_rexmit_seg(struct tcp_pcb *pcb, struct tcp_seg *seg); + +void tcp_rst(u32_t seqno, u32_t ackno, + struct ip_addr *local_ip, struct ip_addr *remote_ip, + u16_t local_port, u16_t remote_port); + +u32_t tcp_next_iss(void); + +void tcp_keepalive(struct tcp_pcb *pcb); + +extern struct tcp_pcb *tcp_input_pcb; +extern u32_t tcp_ticks; + +#if TCP_DEBUG || TCP_INPUT_DEBUG || TCP_OUTPUT_DEBUG +void tcp_debug_print(struct tcp_hdr *tcphdr); +void tcp_debug_print_flags(u8_t flags); +void tcp_debug_print_state(enum tcp_state s); +void tcp_debug_print_pcbs(void); +s16_t tcp_pcbs_sane(void); +#else +# define tcp_debug_print(tcphdr) +# define tcp_debug_print_flags(flags) +# define tcp_debug_print_state(s) +# define tcp_debug_print_pcbs() +# define tcp_pcbs_sane() 1 +#endif /* TCP_DEBUG */ + +#if NO_SYS +#define tcp_timer_needed() +#else +void tcp_timer_needed(void); +#endif + +/* The TCP PCB lists. */ +union tcp_listen_pcbs_t { /* List of all TCP PCBs in LISTEN state. */ + struct tcp_pcb_listen *listen_pcbs; + struct tcp_pcb *pcbs; +}; +extern union tcp_listen_pcbs_t tcp_listen_pcbs; +extern struct tcp_pcb *tcp_active_pcbs; /* List of all TCP PCBs that are in a + state in which they accept or send + data. */ +extern struct tcp_pcb *tcp_tw_pcbs; /* List of all TCP PCBs in TIME-WAIT. */ + +extern struct tcp_pcb *tcp_tmp_pcb; /* Only used for temporary storage. */ + +/* Axioms about the above lists: + 1) Every TCP PCB that is not CLOSED is in one of the lists. + 2) A PCB is only in one of the lists. + 3) All PCBs in the tcp_listen_pcbs list is in LISTEN state. + 4) All PCBs in the tcp_tw_pcbs list is in TIME-WAIT state. +*/ + +/* Define two macros, TCP_REG and TCP_RMV that registers a TCP PCB + with a PCB list or removes a PCB from a list, respectively. */ +#if 0 +#define TCP_REG(pcbs, npcb) do {\ + LWIP_DEBUGF(TCP_DEBUG, ("TCP_REG %p local port %d\n", npcb, npcb->local_port)); \ + for(tcp_tmp_pcb = *pcbs; \ + tcp_tmp_pcb != NULL; \ + tcp_tmp_pcb = tcp_tmp_pcb->next) { \ + LWIP_ASSERT("TCP_REG: already registered\n", tcp_tmp_pcb != npcb); \ + } \ + LWIP_ASSERT("TCP_REG: pcb->state != CLOSED", npcb->state != CLOSED); \ + npcb->next = *pcbs; \ + LWIP_ASSERT("TCP_REG: npcb->next != npcb", npcb->next != npcb); \ + *(pcbs) = npcb; \ + LWIP_ASSERT("TCP_RMV: tcp_pcbs sane", tcp_pcbs_sane()); \ + tcp_timer_needed(); \ + } while(0) +#define TCP_RMV(pcbs, npcb) do { \ + LWIP_ASSERT("TCP_RMV: pcbs != NULL", *pcbs != NULL); \ + LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removing %p from %p\n", npcb, *pcbs)); \ + if(*pcbs == npcb) { \ + *pcbs = (*pcbs)->next; \ + } else for(tcp_tmp_pcb = *pcbs; tcp_tmp_pcb != NULL; tcp_tmp_pcb = tcp_tmp_pcb->next) { \ + if(tcp_tmp_pcb->next != NULL && tcp_tmp_pcb->next == npcb) { \ + tcp_tmp_pcb->next = npcb->next; \ + break; \ + } \ + } \ + npcb->next = NULL; \ + LWIP_ASSERT("TCP_RMV: tcp_pcbs sane", tcp_pcbs_sane()); \ + LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removed %p from %p\n", npcb, *pcbs)); \ + } while(0) + +#else /* LWIP_DEBUG */ +#define TCP_REG(pcbs, npcb) do { \ + npcb->next = *pcbs; \ + *(pcbs) = npcb; \ + tcp_timer_needed(); \ + } while(0) +#define TCP_RMV(pcbs, npcb) do { \ + if(*(pcbs) == npcb) { \ + (*(pcbs)) = (*pcbs)->next; \ + } else for(tcp_tmp_pcb = *pcbs; tcp_tmp_pcb != NULL; tcp_tmp_pcb = tcp_tmp_pcb->next) { \ + if(tcp_tmp_pcb->next != NULL && tcp_tmp_pcb->next == npcb) { \ + tcp_tmp_pcb->next = npcb->next; \ + break; \ + } \ + } \ + npcb->next = NULL; \ + } while(0) +#endif /* LWIP_DEBUG */ +#endif /* __LWIP_TCP_H__ */ + + + diff --git a/20080212/Demo/Common/ethernet/lwIP/include/lwip/tcpip.h b/20080212/Demo/Common/ethernet/lwIP/include/lwip/tcpip.h new file mode 100644 index 000000000..242664ef7 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/include/lwip/tcpip.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_TCPIP_H__ +#define __LWIP_TCPIP_H__ + +#include "lwip/api_msg.h" +#include "lwip/pbuf.h" + +void tcpip_init(void (* tcpip_init_done)(void *), void *arg); +void tcpip_apimsg(struct api_msg *apimsg); +err_t tcpip_input(struct pbuf *p, struct netif *inp); +err_t tcpip_callback(void (*f)(void *ctx), void *ctx); + +void tcpip_tcp_timer_needed(void); + +enum tcpip_msg_type { + TCPIP_MSG_API, + TCPIP_MSG_INPUT, + TCPIP_MSG_CALLBACK +}; + +struct tcpip_msg { + enum tcpip_msg_type type; + sys_sem_t *sem; + union { + struct api_msg *apimsg; + struct { + struct pbuf *p; + struct netif *netif; + } inp; + struct { + void (*f)(void *ctx); + void *ctx; + } cb; + } msg; +}; + + +#endif /* __LWIP_TCPIP_H__ */ diff --git a/20080212/Demo/Common/ethernet/lwIP/include/lwip/udp.h b/20080212/Demo/Common/ethernet/lwIP/include/lwip/udp.h new file mode 100644 index 000000000..adefdc9dd --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/include/lwip/udp.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIP_UDP_H__ +#define __LWIP_UDP_H__ + +#include "lwip/arch.h" + +#include "lwip/pbuf.h" +#include "lwip/inet.h" +#include "lwip/ip.h" + +#define UDP_HLEN 8 + +struct udp_hdr { + PACK_STRUCT_FIELD(u16_t src); + PACK_STRUCT_FIELD(u16_t dest); /* src/dest UDP ports */ + PACK_STRUCT_FIELD(u16_t len); + PACK_STRUCT_FIELD(u16_t chksum); +} PACK_STRUCT_STRUCT; + +#define UDP_FLAGS_NOCHKSUM 0x01U +#define UDP_FLAGS_UDPLITE 0x02U +#define UDP_FLAGS_CONNECTED 0x04U + +struct udp_pcb { +/* Common members of all PCB types */ + IP_PCB; + +/* Protocol specific PCB members */ + + struct udp_pcb *next; + + u8_t flags; + u16_t local_port, remote_port; + + u16_t chksum_len; + + void (* recv)(void *arg, struct udp_pcb *pcb, struct pbuf *p, + struct ip_addr *addr, u16_t port); + void *recv_arg; +}; +/* udp_pcbs export for exernal reference (e.g. SNMP agent) */ +extern struct udp_pcb *udp_pcbs; + +/* The following functions is the application layer interface to the + UDP code. */ +struct udp_pcb * udp_new (void); +void udp_remove (struct udp_pcb *pcb); +err_t udp_bind (struct udp_pcb *pcb, struct ip_addr *ipaddr, + u16_t port); +err_t udp_connect (struct udp_pcb *pcb, struct ip_addr *ipaddr, + u16_t port); +void udp_disconnect (struct udp_pcb *pcb); +void udp_recv (struct udp_pcb *pcb, + void (* recv)(void *arg, struct udp_pcb *upcb, + struct pbuf *p, + struct ip_addr *addr, + u16_t port), + void *recv_arg); +err_t udp_sendto (struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *dst_ip, u16_t dst_port); +err_t udp_send (struct udp_pcb *pcb, struct pbuf *p); + +#define udp_flags(pcb) ((pcb)->flags) +#define udp_setflags(pcb, f) ((pcb)->flags = (f)) + +/* The following functions are the lower layer interface to UDP. */ +void udp_input (struct pbuf *p, struct netif *inp); +void udp_init (void); + +#if UDP_DEBUG +void udp_debug_print(struct udp_hdr *udphdr); +#else +#define udp_debug_print(udphdr) +#endif +#endif /* __LWIP_UDP_H__ */ + + diff --git a/20080212/Demo/Common/ethernet/lwIP/include/netif/etharp.h b/20080212/Demo/Common/ethernet/lwIP/include/netif/etharp.h new file mode 100644 index 000000000..cc0a35f4e --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/include/netif/etharp.h @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * Copyright (c) 2003-2004 Leon Woestenberg + * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#ifndef __NETIF_ETHARP_H__ +#define __NETIF_ETHARP_H__ + +#ifndef ETH_PAD_SIZE +#define ETH_PAD_SIZE 0 +#endif + +#include "lwip/pbuf.h" +#include "lwip/ip_addr.h" +#include "lwip/netif.h" +#include "lwip/ip.h" + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct eth_addr { + PACK_STRUCT_FIELD(u8_t addr[6]); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct eth_hdr { +#if ETH_PAD_SIZE + PACK_STRUCT_FIELD(u8_t padding[ETH_PAD_SIZE]); +#endif + PACK_STRUCT_FIELD(struct eth_addr dest); + PACK_STRUCT_FIELD(struct eth_addr src); + PACK_STRUCT_FIELD(u16_t type); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +/** the ARP message */ +struct etharp_hdr { + PACK_STRUCT_FIELD(struct eth_hdr ethhdr); + PACK_STRUCT_FIELD(u16_t hwtype); + PACK_STRUCT_FIELD(u16_t proto); + PACK_STRUCT_FIELD(u16_t _hwlen_protolen); + PACK_STRUCT_FIELD(u16_t opcode); + PACK_STRUCT_FIELD(struct eth_addr shwaddr); + PACK_STRUCT_FIELD(struct ip_addr2 sipaddr); + PACK_STRUCT_FIELD(struct eth_addr dhwaddr); + PACK_STRUCT_FIELD(struct ip_addr2 dipaddr); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct ethip_hdr { + PACK_STRUCT_FIELD(struct eth_hdr eth); + PACK_STRUCT_FIELD(struct ip_hdr ip); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +/** 5 seconds period */ +#define ARP_TMR_INTERVAL 5000 + +#define ETHTYPE_ARP 0x0806 +#define ETHTYPE_IP 0x0800 + + +void etharp_init(void); +void etharp_tmr(void); +s8_t etharp_find_addr(struct netif *netif, struct ip_addr *ipaddr, + struct eth_addr **eth_ret, struct ip_addr **ip_ret); +void etharp_ip_input(struct netif *netif, struct pbuf *p); +void etharp_arp_input(struct netif *netif, struct eth_addr *ethaddr, + struct pbuf *p); +err_t etharp_output(struct netif *netif, struct ip_addr *ipaddr, + struct pbuf *q); +err_t etharp_query(struct netif *netif, struct ip_addr *ipaddr, struct pbuf *q); +err_t etharp_request(struct netif *netif, struct ip_addr *ipaddr); + +#endif /* __NETIF_ARP_H__ */ diff --git a/20080212/Demo/Common/ethernet/lwIP/include/netif/loopif.h b/20080212/Demo/Common/ethernet/lwIP/include/netif/loopif.h new file mode 100644 index 000000000..7fd548733 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/include/netif/loopif.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __NETIF_LOOPIF_H__ +#define __NETIF_LOOPIF_H__ + +#include "lwip/netif.h" + +err_t loopif_init(struct netif *netif); + +#endif /* __NETIF_LOOPIF_H__ */ diff --git a/20080212/Demo/Common/ethernet/lwIP/include/netif/slipif.h b/20080212/Demo/Common/ethernet/lwIP/include/netif/slipif.h new file mode 100644 index 000000000..d9060fc97 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/include/netif/slipif.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __NETIF_SLIPIF_H__ +#define __NETIF_SLIPIF_H__ + +#include "lwip/netif.h" + +err_t slipif_init(struct netif * netif); + +#endif + diff --git a/20080212/Demo/Common/ethernet/lwIP/netif/FILES b/20080212/Demo/Common/ethernet/lwIP/netif/FILES new file mode 100644 index 000000000..825d40715 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/netif/FILES @@ -0,0 +1,27 @@ +This directory contains generic network interface device drivers that +do not contain any hardware or architecture specific code. The files +are: + +etharp.c + Implements the ARP (Address Resolution Protocol) over + Ethernet. The code in this file should be used together with + Ethernet device drivers. Note that this module has been + largely made Ethernet independent so you should be able to + adapt this for other link layers (such as Firewire). + +ethernetif.c + An example of how an Ethernet device driver could look. This + file can be used as a "skeleton" for developing new Ethernet + network device drivers. It uses the etharp.c ARP code. + +loopif.c + An example network interface that shows how a "loopback" + interface would work. This is not really intended for actual + use, but as a very basic example of how initialization and + output functions work. + +slipif.c + A generic implementation of the SLIP (Serial Line IP) + protocol. It requires a sio (serial I/O) module to work. + +ppp/ Point-to-Point Protocol stack diff --git a/20080212/Demo/Common/ethernet/lwIP/netif/etharp.c b/20080212/Demo/Common/ethernet/lwIP/netif/etharp.c new file mode 100644 index 000000000..22eeb9a08 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/netif/etharp.c @@ -0,0 +1,892 @@ +/** + * @file + * Address Resolution Protocol module for IP over Ethernet + * + * Functionally, ARP is divided into two parts. The first maps an IP address + * to a physical address when sending a packet, and the second part answers + * requests from other machines for our physical address. + * + * This implementation complies with RFC 826 (Ethernet ARP). It supports + * Gratuitious ARP from RFC3220 (IP Mobility Support for IPv4) section 4.6 + * if an interface calls etharp_query(our_netif, its_ip_addr, NULL) upon + * address change. + */ + +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * Copyright (c) 2003-2004 Leon Woestenberg + * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + */ +#include +#include "lwip/opt.h" +#include "lwip/inet.h" +#include "netif/etharp.h" +#include "lwip/ip.h" +#include "lwip/stats.h" +#include "lwip/snmp.h" + +/* ARP needs to inform DHCP of any ARP replies? */ +#if (LWIP_DHCP && DHCP_DOES_ARP_CHECK) +# include "lwip/dhcp.h" +#endif + +/** the time an ARP entry stays valid after its last update, + * (240 * 5) seconds = 20 minutes. + */ +#define ARP_MAXAGE 240 +/** the time an ARP entry stays pending after first request, + * (2 * 5) seconds = 10 seconds. + * + * @internal Keep this number at least 2, otherwise it might + * run out instantly if the timeout occurs directly after a request. + */ +#define ARP_MAXPENDING 2 + +#define HWTYPE_ETHERNET 1 + +/** ARP message types */ +#define ARP_REQUEST 1 +#define ARP_REPLY 2 + +#define ARPH_HWLEN(hdr) (ntohs((hdr)->_hwlen_protolen) >> 8) +#define ARPH_PROTOLEN(hdr) (ntohs((hdr)->_hwlen_protolen) & 0xff) + +#define ARPH_HWLEN_SET(hdr, len) (hdr)->_hwlen_protolen = htons(ARPH_PROTOLEN(hdr) | ((len) << 8)) +#define ARPH_PROTOLEN_SET(hdr, len) (hdr)->_hwlen_protolen = htons((len) | (ARPH_HWLEN(hdr) << 8)) + +enum etharp_state { + ETHARP_STATE_EMPTY, + ETHARP_STATE_PENDING, + ETHARP_STATE_STABLE, + /** @internal transitional state used in etharp_tmr() for convenience*/ + ETHARP_STATE_EXPIRED +}; + +struct etharp_entry { +#if ARP_QUEUEING + /** + * Pointer to queue of pending outgoing packets on this ARP entry. + */ + struct pbuf *p; +#endif + struct ip_addr ipaddr; + struct eth_addr ethaddr; + enum etharp_state state; + u8_t ctime; + struct netif *netif; +}; + +static const struct eth_addr ethbroadcast = {{0xff,0xff,0xff,0xff,0xff,0xff}}; +static struct etharp_entry arp_table[ARP_TABLE_SIZE]; + +/** + * Try hard to create a new entry - we want the IP address to appear in + * the cache (even if this means removing an active entry or so). */ +#define ETHARP_TRY_HARD 1 + +static s8_t find_entry(struct ip_addr *ipaddr, u8_t flags); +static err_t update_arp_entry(struct netif *netif, struct ip_addr *ipaddr, struct eth_addr *ethaddr, u8_t flags); +/** + * Initializes ARP module. + */ +void +etharp_init(void) +{ + u8_t i; + /* clear ARP entries */ + for(i = 0; i < ARP_TABLE_SIZE; ++i) { + arp_table[i].state = ETHARP_STATE_EMPTY; +#if ARP_QUEUEING + arp_table[i].p = NULL; +#endif + arp_table[i].ctime = 0; + arp_table[i].netif = NULL; + } +} + +/** + * Clears expired entries in the ARP table. + * + * This function should be called every ETHARP_TMR_INTERVAL microseconds (5 seconds), + * in order to expire entries in the ARP table. + */ +void +etharp_tmr(void) +{ + u8_t i; + + LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer\n")); + /* remove expired entries from the ARP table */ + for (i = 0; i < ARP_TABLE_SIZE; ++i) { + arp_table[i].ctime++; + /* stable entry? */ + if ((arp_table[i].state == ETHARP_STATE_STABLE) && + /* entry has become old? */ + (arp_table[i].ctime >= ARP_MAXAGE)) { + LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: expired stable entry %"U16_F".\n", (u16_t)i)); + arp_table[i].state = ETHARP_STATE_EXPIRED; + /* pending entry? */ + } else if (arp_table[i].state == ETHARP_STATE_PENDING) { + /* entry unresolved/pending for too long? */ + if (arp_table[i].ctime >= ARP_MAXPENDING) { + LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: expired pending entry %"U16_F".\n", (u16_t)i)); + arp_table[i].state = ETHARP_STATE_EXPIRED; +#if ARP_QUEUEING + } else if (arp_table[i].p != NULL) { + /* resend an ARP query here */ +#endif + } + } + /* clean up entries that have just been expired */ + if (arp_table[i].state == ETHARP_STATE_EXPIRED) { + /* remove from SNMP ARP index tree */ + snmp_delete_arpidx_tree(arp_table[i].netif, &arp_table[i].ipaddr); +#if ARP_QUEUEING + /* and empty packet queue */ + if (arp_table[i].p != NULL) { + /* remove all queued packets */ + LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: freeing entry %"U16_F", packet queue %p.\n", (u16_t)i, (void *)(arp_table[i].p))); + pbuf_free(arp_table[i].p); + arp_table[i].p = NULL; + } +#endif + /* recycle entry for re-use */ + arp_table[i].state = ETHARP_STATE_EMPTY; + } + } +} + +/** + * Search the ARP table for a matching or new entry. + * + * If an IP address is given, return a pending or stable ARP entry that matches + * the address. If no match is found, create a new entry with this address set, + * but in state ETHARP_EMPTY. The caller must check and possibly change the + * state of the returned entry. + * + * If ipaddr is NULL, return a initialized new entry in state ETHARP_EMPTY. + * + * In all cases, attempt to create new entries from an empty entry. If no + * empty entries are available and ETHARP_TRY_HARD flag is set, recycle + * old entries. Heuristic choose the least important entry for recycling. + * + * @param ipaddr IP address to find in ARP cache, or to add if not found. + * @param flags + * - ETHARP_TRY_HARD: Try hard to create a entry by allowing recycling of + * active (stable or pending) entries. + * + * @return The ARP entry index that matched or is created, ERR_MEM if no + * entry is found or could be recycled. + */ +static s8_t find_entry(struct ip_addr *ipaddr, u8_t flags) +{ + s8_t old_pending = ARP_TABLE_SIZE, old_stable = ARP_TABLE_SIZE; + s8_t empty = ARP_TABLE_SIZE; + u8_t i = 0, age_pending = 0, age_stable = 0; +#if ARP_QUEUEING + /* oldest entry with packets on queue */ + s8_t old_queue = ARP_TABLE_SIZE; + /* its age */ + u8_t age_queue = 0; +#endif + + /** + * a) do a search through the cache, remember candidates + * b) select candidate entry + * c) create new entry + */ + + /* a) in a single search sweep, do all of this + * 1) remember the first empty entry (if any) + * 2) remember the oldest stable entry (if any) + * 3) remember the oldest pending entry without queued packets (if any) + * 4) remember the oldest pending entry with queued packets (if any) + * 5) search for a matching IP entry, either pending or stable + * until 5 matches, or all entries are searched for. + */ + + for (i = 0; i < ARP_TABLE_SIZE; ++i) { + /* no empty entry found yet and now we do find one? */ + if ((empty == ARP_TABLE_SIZE) && (arp_table[i].state == ETHARP_STATE_EMPTY)) { + LWIP_DEBUGF(ETHARP_DEBUG, ("find_entry: found empty entry %"U16_F"\n", (u16_t)i)); + /* remember first empty entry */ + empty = i; + } + /* pending entry? */ + else if (arp_table[i].state == ETHARP_STATE_PENDING) { + /* if given, does IP address match IP address in ARP entry? */ + if (ipaddr && ip_addr_cmp(ipaddr, &arp_table[i].ipaddr)) { + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: found matching pending entry %"U16_F"\n", (u16_t)i)); + /* found exact IP address match, simply bail out */ + return i; +#if ARP_QUEUEING + /* pending with queued packets? */ + } else if (arp_table[i].p != NULL) { + if (arp_table[i].ctime >= age_queue) { + old_queue = i; + age_queue = arp_table[i].ctime; + } +#endif + /* pending without queued packets? */ + } else { + if (arp_table[i].ctime >= age_pending) { + old_pending = i; + age_pending = arp_table[i].ctime; + } + } + } + /* stable entry? */ + else if (arp_table[i].state == ETHARP_STATE_STABLE) { + /* if given, does IP address match IP address in ARP entry? */ + if (ipaddr && ip_addr_cmp(ipaddr, &arp_table[i].ipaddr)) { + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: found matching stable entry %"U16_F"\n", (u16_t)i)); + /* found exact IP address match, simply bail out */ + return i; + /* remember entry with oldest stable entry in oldest, its age in maxtime */ + } else if (arp_table[i].ctime >= age_stable) { + old_stable = i; + age_stable = arp_table[i].ctime; + } + } + } + /* { we have no match } => try to create a new entry */ + + /* no empty entry found and not allowed to recycle? */ + if ((empty == ARP_TABLE_SIZE) && ((flags & ETHARP_TRY_HARD) == 0)) + { + return (s8_t)ERR_MEM; + } + + /* b) choose the least destructive entry to recycle: + * 1) empty entry + * 2) oldest stable entry + * 3) oldest pending entry without queued packets + * 4) oldest pending entry without queued packets + * + * { ETHARP_TRY_HARD is set at this point } + */ + + /* 1) empty entry available? */ + if (empty < ARP_TABLE_SIZE) { + i = empty; + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: selecting empty entry %"U16_F"\n", (u16_t)i)); + } + /* 2) found recyclable stable entry? */ + else if (old_stable < ARP_TABLE_SIZE) { + /* recycle oldest stable*/ + i = old_stable; + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: selecting oldest stable entry %"U16_F"\n", (u16_t)i)); +#if ARP_QUEUEING + /* no queued packets should exist on stable entries */ + LWIP_ASSERT("arp_table[i].p == NULL", arp_table[i].p == NULL); +#endif + /* 3) found recyclable pending entry without queued packets? */ + } else if (old_pending < ARP_TABLE_SIZE) { + /* recycle oldest pending */ + i = old_pending; + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: selecting oldest pending entry %"U16_F" (without queue)\n", (u16_t)i)); +#if ARP_QUEUEING + /* 4) found recyclable pending entry with queued packets? */ + } else if (old_queue < ARP_TABLE_SIZE) { + /* recycle oldest pending */ + i = old_queue; + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: selecting oldest pending entry %"U16_F", freeing packet queue %p\n", (u16_t)i, (void *)(arp_table[i].p))); + pbuf_free(arp_table[i].p); + arp_table[i].p = NULL; +#endif + /* no empty or recyclable entries found */ + } else { + return (s8_t)ERR_MEM; + } + + /* { empty or recyclable entry found } */ + LWIP_ASSERT("i < ARP_TABLE_SIZE", i < ARP_TABLE_SIZE); + + if (arp_table[i].state != ETHARP_STATE_EMPTY) + { + snmp_delete_arpidx_tree(arp_table[i].netif, &arp_table[i].ipaddr); + } + /* recycle entry (no-op for an already empty entry) */ + arp_table[i].state = ETHARP_STATE_EMPTY; + + /* IP address given? */ + if (ipaddr != NULL) { + /* set IP address */ + ip_addr_set(&arp_table[i].ipaddr, ipaddr); + } + arp_table[i].ctime = 0; + return (err_t)i; +} + +/** + * Update (or insert) a IP/MAC address pair in the ARP cache. + * + * If a pending entry is resolved, any queued packets will be sent + * at this point. + * + * @param ipaddr IP address of the inserted ARP entry. + * @param ethaddr Ethernet address of the inserted ARP entry. + * @param flags Defines behaviour: + * - ETHARP_TRY_HARD Allows ARP to insert this as a new item. If not specified, + * only existing ARP entries will be updated. + * + * @return + * - ERR_OK Succesfully updated ARP cache. + * - ERR_MEM If we could not add a new ARP entry when ETHARP_TRY_HARD was set. + * - ERR_ARG Non-unicast address given, those will not appear in ARP cache. + * + * @see pbuf_free() + */ +static err_t +update_arp_entry(struct netif *netif, struct ip_addr *ipaddr, struct eth_addr *ethaddr, u8_t flags) +{ + s8_t i; + u8_t k; + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 3, ("update_arp_entry()\n")); + LWIP_ASSERT("netif->hwaddr_len != 0", netif->hwaddr_len != 0); + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: %"U16_F".%"U16_F".%"U16_F".%"U16_F" - %02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F"\n", + ip4_addr1(ipaddr), ip4_addr2(ipaddr), ip4_addr3(ipaddr), ip4_addr4(ipaddr), + ethaddr->addr[0], ethaddr->addr[1], ethaddr->addr[2], + ethaddr->addr[3], ethaddr->addr[4], ethaddr->addr[5])); + /* non-unicast address? */ + if (ip_addr_isany(ipaddr) || + ip_addr_isbroadcast(ipaddr, netif) || + ip_addr_ismulticast(ipaddr)) { + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: will not add non-unicast IP address to ARP cache\n")); + return ERR_ARG; + } + /* find or create ARP entry */ + i = find_entry(ipaddr, flags); + /* bail out if no entry could be found */ + if (i < 0) return (err_t)i; + + /* mark it stable */ + arp_table[i].state = ETHARP_STATE_STABLE; + /* record network interface */ + arp_table[i].netif = netif; + + /* insert in SNMP ARP index tree */ + snmp_insert_arpidx_tree(netif, &arp_table[i].ipaddr); + + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: updating stable entry %"S16_F"\n", (s16_t)i)); + /* update address */ + k = netif->hwaddr_len; + while (k > 0) { + k--; + arp_table[i].ethaddr.addr[k] = ethaddr->addr[k]; + } + /* reset time stamp */ + arp_table[i].ctime = 0; +/* this is where we will send out queued packets! */ +#if ARP_QUEUEING + while (arp_table[i].p != NULL) { + /* get the first packet on the queue */ + struct pbuf *p = arp_table[i].p; + /* Ethernet header */ + struct eth_hdr *ethhdr = p->payload; + /* remember (and reference) remainder of queue */ + /* note: this will also terminate the p pbuf chain */ + arp_table[i].p = pbuf_dequeue(p); + /* fill-in Ethernet header */ + k = netif->hwaddr_len; + while(k > 0) { + k--; + ethhdr->dest.addr[k] = ethaddr->addr[k]; + ethhdr->src.addr[k] = netif->hwaddr[k]; + } + ethhdr->type = htons(ETHTYPE_IP); + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: sending queued IP packet %p.\n", (void *)p)); + /* send the queued IP packet */ + netif->linkoutput(netif, p); + /* free the queued IP packet */ + pbuf_free(p); + } +#endif + return ERR_OK; +} + +/** + * Finds (stable) ethernet/IP address pair from ARP table + * using interface and IP address index. + * @note the addresses in the ARP table are in network order! + * + * @param netif points to interface index + * @param ipaddr points to the (network order) IP address index + * @param eth_ret points to return pointer + * @param ip_ret points to return pointer + * @return table index if found, -1 otherwise + */ +s8_t +etharp_find_addr(struct netif *netif, struct ip_addr *ipaddr, + struct eth_addr **eth_ret, struct ip_addr **ip_ret) +{ + s8_t i; + + i = 0; + while (i < ARP_TABLE_SIZE) + { + if ((arp_table[i].state == ETHARP_STATE_STABLE) && + (arp_table[i].netif == netif) && + ip_addr_cmp(ipaddr, &arp_table[i].ipaddr) ) + { + *eth_ret = &arp_table[i].ethaddr; + *ip_ret = &arp_table[i].ipaddr; + return i; + } + i++; + } + return -1; +} + +/** + * Updates the ARP table using the given IP packet. + * + * Uses the incoming IP packet's source address to update the + * ARP cache for the local network. The function does not alter + * or free the packet. This function must be called before the + * packet p is passed to the IP layer. + * + * @param netif The lwIP network interface on which the IP packet pbuf arrived. + * @param pbuf The IP packet that arrived on netif. + * + * @return NULL + * + * @see pbuf_free() + */ +void +etharp_ip_input(struct netif *netif, struct pbuf *p) +{ + struct ethip_hdr *hdr; + LWIP_ASSERT("netif != NULL", netif != NULL); + /* Only insert an entry if the source IP address of the + incoming IP packet comes from a host on the local network. */ + hdr = p->payload; + /* source is not on the local network? */ + if (!ip_addr_netcmp(&(hdr->ip.src), &(netif->ip_addr), &(netif->netmask))) { + /* do nothing */ + return; + } + + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_ip_input: updating ETHARP table.\n")); + /* update ARP table */ + /* @todo We could use ETHARP_TRY_HARD if we think we are going to talk + * back soon (for example, if the destination IP address is ours. */ + update_arp_entry(netif, &(hdr->ip.src), &(hdr->eth.src), 0); +} + + +/** + * Responds to ARP requests to us. Upon ARP replies to us, add entry to cache + * send out queued IP packets. Updates cache with snooped address pairs. + * + * Should be called for incoming ARP packets. The pbuf in the argument + * is freed by this function. + * + * @param netif The lwIP network interface on which the ARP packet pbuf arrived. + * @param pbuf The ARP packet that arrived on netif. Is freed by this function. + * @param ethaddr Ethernet address of netif. + * + * @return NULL + * + * @see pbuf_free() + */ +void +etharp_arp_input(struct netif *netif, struct eth_addr *ethaddr, struct pbuf *p) +{ + struct etharp_hdr *hdr; + /* these are aligned properly, whereas the ARP header fields might not be */ + struct ip_addr sipaddr, dipaddr; + u8_t i; + u8_t for_us; + + LWIP_ASSERT("netif != NULL", netif != NULL); + + /* drop short ARP packets */ + if (p->tot_len < sizeof(struct etharp_hdr)) { + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 1, ("etharp_arp_input: packet dropped, too short (%"S16_F"/%"S16_F")\n", p->tot_len, (s16_t)sizeof(struct etharp_hdr))); + pbuf_free(p); + return; + } + + hdr = p->payload; + + /* Copy struct ip_addr2 to aligned ip_addr, to support compilers without + * structure packing (not using structure copy which breaks strict-aliasing rules). */ + memcpy(&sipaddr, &hdr->sipaddr, sizeof(sipaddr)); + memcpy(&dipaddr, &hdr->dipaddr, sizeof(dipaddr)); + + /* this interface is not configured? */ + if (netif->ip_addr.addr == 0) { + for_us = 0; + } else { + /* ARP packet directed to us? */ + for_us = ip_addr_cmp(&dipaddr, &(netif->ip_addr)); + } + + /* ARP message directed to us? */ + if (for_us) { + /* add IP address in ARP cache; assume requester wants to talk to us. + * can result in directly sending the queued packets for this host. */ + update_arp_entry(netif, &sipaddr, &(hdr->shwaddr), ETHARP_TRY_HARD); + /* ARP message not directed to us? */ + } else { + /* update the source IP address in the cache, if present */ + update_arp_entry(netif, &sipaddr, &(hdr->shwaddr), 0); + } + + /* now act on the message itself */ + switch (htons(hdr->opcode)) { + /* ARP request? */ + case ARP_REQUEST: + /* ARP request. If it asked for our address, we send out a + * reply. In any case, we time-stamp any existing ARP entry, + * and possiby send out an IP packet that was queued on it. */ + + LWIP_DEBUGF (ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: incoming ARP request\n")); + /* ARP request for our address? */ + if (for_us) { + + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: replying to ARP request for our IP address\n")); + /* re-use pbuf to send ARP reply */ + hdr->opcode = htons(ARP_REPLY); + + hdr->dipaddr = hdr->sipaddr; + hdr->sipaddr = *(struct ip_addr2 *)&netif->ip_addr; + + i = netif->hwaddr_len; + while(i > 0) { + i--; + hdr->dhwaddr.addr[i] = hdr->shwaddr.addr[i]; + hdr->shwaddr.addr[i] = ethaddr->addr[i]; + hdr->ethhdr.dest.addr[i] = hdr->dhwaddr.addr[i]; + hdr->ethhdr.src.addr[i] = ethaddr->addr[i]; + } + + hdr->hwtype = htons(HWTYPE_ETHERNET); + ARPH_HWLEN_SET(hdr, netif->hwaddr_len); + + hdr->proto = htons(ETHTYPE_IP); + ARPH_PROTOLEN_SET(hdr, sizeof(struct ip_addr)); + + hdr->ethhdr.type = htons(ETHTYPE_ARP); + /* return ARP reply */ + netif->linkoutput(netif, p); + /* we are not configured? */ + } else if (netif->ip_addr.addr == 0) { + /* { for_us == 0 and netif->ip_addr.addr == 0 } */ + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: we are unconfigured, ARP request ignored.\n")); + /* request was not directed to us */ + } else { + /* { for_us == 0 and netif->ip_addr.addr != 0 } */ + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: ARP request was not for us.\n")); + } + break; + case ARP_REPLY: + /* ARP reply. We already updated the ARP cache earlier. */ + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: incoming ARP reply\n")); +#if (LWIP_DHCP && DHCP_DOES_ARP_CHECK) + /* DHCP wants to know about ARP replies from any host with an + * IP address also offered to us by the DHCP server. We do not + * want to take a duplicate IP address on a single network. + * @todo How should we handle redundant (fail-over) interfaces? + * */ + dhcp_arp_reply(netif, &sipaddr); +#endif + break; + default: + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: ARP unknown opcode type %"S16_F"\n", htons(hdr->opcode))); + break; + } + /* free ARP packet */ + pbuf_free(p); +} + +/** + * Resolve and fill-in Ethernet address header for outgoing packet. + * + * For IP multicast and broadcast, corresponding Ethernet addresses + * are selected and the packet is transmitted on the link. + * + * For unicast addresses, the packet is submitted to etharp_query(). In + * case the IP address is outside the local network, the IP address of + * the gateway is used. + * + * @param netif The lwIP network interface which the IP packet will be sent on. + * @param ipaddr The IP address of the packet destination. + * @param pbuf The pbuf(s) containing the IP packet to be sent. + * + * @return + * - ERR_RTE No route to destination (no gateway to external networks), + * or the return type of either etharp_query() or netif->linkoutput(). + */ +err_t +etharp_output(struct netif *netif, struct ip_addr *ipaddr, struct pbuf *q) +{ + struct eth_addr *dest, *srcaddr, mcastaddr; + struct eth_hdr *ethhdr; + u8_t i; + + /* make room for Ethernet header - should not fail */ + if (pbuf_header(q, sizeof(struct eth_hdr)) != 0) { + /* bail out */ + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 2, ("etharp_output: could not allocate room for header.\n")); + LINK_STATS_INC(link.lenerr); + return ERR_BUF; + } + + /* assume unresolved Ethernet address */ + dest = NULL; + /* Determine on destination hardware address. Broadcasts and multicasts + * are special, other IP addresses are looked up in the ARP table. */ + + /* broadcast destination IP address? */ + if (ip_addr_isbroadcast(ipaddr, netif)) { + /* broadcast on Ethernet also */ + dest = (struct eth_addr *)ðbroadcast; + /* multicast destination IP address? */ + } else if (ip_addr_ismulticast(ipaddr)) { + /* Hash IP multicast address to MAC address.*/ + mcastaddr.addr[0] = 0x01; + mcastaddr.addr[1] = 0x00; + mcastaddr.addr[2] = 0x5e; + mcastaddr.addr[3] = ip4_addr2(ipaddr) & 0x7f; + mcastaddr.addr[4] = ip4_addr3(ipaddr); + mcastaddr.addr[5] = ip4_addr4(ipaddr); + /* destination Ethernet address is multicast */ + dest = &mcastaddr; + /* unicast destination IP address? */ + } else { + /* outside local network? */ + if (!ip_addr_netcmp(ipaddr, &(netif->ip_addr), &(netif->netmask))) { + /* interface has default gateway? */ + if (netif->gw.addr != 0) { + /* send to hardware address of default gateway IP address */ + ipaddr = &(netif->gw); + /* no default gateway available */ + } else { + /* no route to destination error (default gateway missing) */ + return ERR_RTE; + } + } + /* queue on destination Ethernet address belonging to ipaddr */ + return etharp_query(netif, ipaddr, q); + } + + /* continuation for multicast/broadcast destinations */ + /* obtain source Ethernet address of the given interface */ + srcaddr = (struct eth_addr *)netif->hwaddr; + ethhdr = q->payload; + i = netif->hwaddr_len; + while(i > 0) { + i--; + ethhdr->dest.addr[i] = dest->addr[i]; + ethhdr->src.addr[i] = srcaddr->addr[i]; + } + ethhdr->type = htons(ETHTYPE_IP); + /* send packet directly on the link */ + return netif->linkoutput(netif, q); +} + +/** + * Send an ARP request for the given IP address and/or queue a packet. + * + * If the IP address was not yet in the cache, a pending ARP cache entry + * is added and an ARP request is sent for the given address. The packet + * is queued on this entry. + * + * If the IP address was already pending in the cache, a new ARP request + * is sent for the given address. The packet is queued on this entry. + * + * If the IP address was already stable in the cache, and a packet is + * given, it is directly sent and no ARP request is sent out. + * + * If the IP address was already stable in the cache, and no packet is + * given, an ARP request is sent out. + * + * @param netif The lwIP network interface on which ipaddr + * must be queried for. + * @param ipaddr The IP address to be resolved. + * @param q If non-NULL, a pbuf that must be delivered to the IP address. + * q is not freed by this function. + * + * @return + * - ERR_BUF Could not make room for Ethernet header. + * - ERR_MEM Hardware address unknown, and no more ARP entries available + * to query for address or queue the packet. + * - ERR_MEM Could not queue packet due to memory shortage. + * - ERR_RTE No route to destination (no gateway to external networks). + * - ERR_ARG Non-unicast address given, those will not appear in ARP cache. + * + */ +err_t etharp_query(struct netif *netif, struct ip_addr *ipaddr, struct pbuf *q) +{ + struct eth_addr * srcaddr = (struct eth_addr *)netif->hwaddr; + err_t result = ERR_MEM; + s8_t i; /* ARP entry index */ + u8_t k; /* Ethernet address octet index */ + + /* non-unicast address? */ + if (ip_addr_isbroadcast(ipaddr, netif) || + ip_addr_ismulticast(ipaddr) || + ip_addr_isany(ipaddr)) { + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: will not add non-unicast IP address to ARP cache\n")); + return ERR_ARG; + } + + /* find entry in ARP cache, ask to create entry if queueing packet */ + i = find_entry(ipaddr, ETHARP_TRY_HARD); + + /* could not find or create entry? */ + if (i < 0) + { + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: could not create ARP entry\n")); + if (q) LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: packet dropped\n")); + return (err_t)i; + } + + /* mark a fresh entry as pending (we just sent a request) */ + if (arp_table[i].state == ETHARP_STATE_EMPTY) { + arp_table[i].state = ETHARP_STATE_PENDING; + } + + /* { i is either a STABLE or (new or existing) PENDING entry } */ + LWIP_ASSERT("arp_table[i].state == PENDING or STABLE", + ((arp_table[i].state == ETHARP_STATE_PENDING) || + (arp_table[i].state == ETHARP_STATE_STABLE))); + + /* do we have a pending entry? or an implicit query request? */ + if ((arp_table[i].state == ETHARP_STATE_PENDING) || (q == NULL)) { + /* try to resolve it; send out ARP request */ + result = etharp_request(netif, ipaddr); + } + + /* packet given? */ + if (q != NULL) { + /* stable entry? */ + if (arp_table[i].state == ETHARP_STATE_STABLE) { + /* we have a valid IP->Ethernet address mapping, + * fill in the Ethernet header for the outgoing packet */ + struct eth_hdr *ethhdr = q->payload; + k = netif->hwaddr_len; + while(k > 0) { + k--; + ethhdr->dest.addr[k] = arp_table[i].ethaddr.addr[k]; + ethhdr->src.addr[k] = srcaddr->addr[k]; + } + ethhdr->type = htons(ETHTYPE_IP); + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: sending packet %p\n", (void *)q)); + /* send the packet */ + result = netif->linkoutput(netif, q); + /* pending entry? (either just created or already pending */ + } else if (arp_table[i].state == ETHARP_STATE_PENDING) { +#if ARP_QUEUEING /* queue the given q packet */ + struct pbuf *p; + /* copy any PBUF_REF referenced payloads into PBUF_RAM */ + /* (the caller of lwIP assumes the referenced payload can be + * freed after it returns from the lwIP call that brought us here) */ + p = pbuf_take(q); + /* packet could be taken over? */ + if (p != NULL) { + /* queue packet ... */ + if (arp_table[i].p == NULL) { + /* ... in the empty queue */ + pbuf_ref(p); + arp_table[i].p = p; +#if 0 /* multi-packet-queueing disabled, see bug #11400 */ + } else { + /* ... at tail of non-empty queue */ + pbuf_queue(arp_table[i].p, p); +#endif + } + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: queued packet %p on ARP entry %"S16_F"\n", (void *)q, (s16_t)i)); + result = ERR_OK; + } else { + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: could not queue a copy of PBUF_REF packet %p (out of memory)\n", (void *)q)); + /* { result == ERR_MEM } through initialization */ + } +#else /* ARP_QUEUEING == 0 */ + /* q && state == PENDING && ARP_QUEUEING == 0 => result = ERR_MEM */ + /* { result == ERR_MEM } through initialization */ + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: Ethernet destination address unknown, queueing disabled, packet %p dropped\n", (void *)q)); +#endif + } + } + return result; +} + +err_t etharp_request(struct netif *netif, struct ip_addr *ipaddr) +{ + struct pbuf *p; + struct eth_addr * srcaddr = (struct eth_addr *)netif->hwaddr; + err_t result = ERR_OK; + u8_t k; /* ARP entry index */ + + /* allocate a pbuf for the outgoing ARP request packet */ + p = pbuf_alloc(PBUF_LINK, sizeof(struct etharp_hdr), PBUF_RAM); + /* could allocate a pbuf for an ARP request? */ + if (p != NULL) { + struct etharp_hdr *hdr = p->payload; + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_request: sending ARP request.\n")); + hdr->opcode = htons(ARP_REQUEST); + k = netif->hwaddr_len; + while(k > 0) { + k--; + hdr->shwaddr.addr[k] = srcaddr->addr[k]; + /* the hardware address is what we ask for, in + * a request it is a don't-care value, we use zeroes */ + hdr->dhwaddr.addr[k] = 0x00; + } + hdr->dipaddr = *(struct ip_addr2 *)ipaddr; + hdr->sipaddr = *(struct ip_addr2 *)&netif->ip_addr; + + hdr->hwtype = htons(HWTYPE_ETHERNET); + ARPH_HWLEN_SET(hdr, netif->hwaddr_len); + + hdr->proto = htons(ETHTYPE_IP); + ARPH_PROTOLEN_SET(hdr, sizeof(struct ip_addr)); + k = netif->hwaddr_len; + while(k > 0) { + k--; + /* broadcast to all network interfaces on the local network */ + hdr->ethhdr.dest.addr[k] = 0xff; + hdr->ethhdr.src.addr[k] = srcaddr->addr[k]; + } + hdr->ethhdr.type = htons(ETHTYPE_ARP); + /* send ARP query */ + result = netif->linkoutput(netif, p); + /* free ARP query packet */ + pbuf_free(p); + p = NULL; + /* could not allocate pbuf for ARP request */ + } else { + result = ERR_MEM; + LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 2, ("etharp_request: could not allocate pbuf for ARP request.\n")); + } + return result; +} diff --git a/20080212/Demo/Common/ethernet/lwIP/netif/ethernetif.c b/20080212/Demo/Common/ethernet/lwIP/netif/ethernetif.c new file mode 100644 index 000000000..300775ffd --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/netif/ethernetif.c @@ -0,0 +1,326 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +/* + * This file is a skeleton for developing Ethernet network interface + * drivers for lwIP. Add code to the low_level functions and do a + * search-and-replace for the word "ethernetif" to replace it with + * something that better describes your network interface. + */ + +#include "lwip/opt.h" +#include "lwip/def.h" +#include "lwip/mem.h" +#include "lwip/pbuf.h" +#include "lwip/sys.h" +#include + +#include "netif/etharp.h" + +/* Define those to better describe your network interface. */ +#define IFNAME0 'e' +#define IFNAME1 'n' + +struct ethernetif { + struct eth_addr *ethaddr; + /* Add whatever per-interface state that is needed here. */ +}; + +static const struct eth_addr ethbroadcast = {{0xff,0xff,0xff,0xff,0xff,0xff}}; + +/* Forward declarations. */ +static void ethernetif_input(struct netif *netif); +static err_t ethernetif_output(struct netif *netif, struct pbuf *p, + struct ip_addr *ipaddr); + +static void +low_level_init(struct netif *netif) +{ + struct ethernetif *ethernetif = netif->state; + + /* set MAC hardware address length */ + netif->hwaddr_len = 6; + + /* set MAC hardware address */ + netif->hwaddr[0] = ; + ... + netif->hwaddr[5] = ; + + /* maximum transfer unit */ + netif->mtu = 1500; + + /* broadcast capability */ + netif->flags = NETIF_FLAG_BROADCAST; + + /* Do whatever else is needed to initialize interface. */ +} + +/* + * low_level_output(): + * + * Should do the actual transmission of the packet. The packet is + * contained in the pbuf that is passed to the function. This pbuf + * might be chained. + * + */ + +static err_t +low_level_output(struct netif *netif, struct pbuf *p) +{ + struct ethernetif *ethernetif = netif->state; + struct pbuf *q; + + initiate transfer(); + +#if ETH_PAD_SIZE + pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */ +#endif + + for(q = p; q != NULL; q = q->next) { + /* Send the data from the pbuf to the interface, one pbuf at a + time. The size of the data in each pbuf is kept in the ->len + variable. */ + send data from(q->payload, q->len); + } + + signal that packet should be sent(); + +#if ETH_PAD_SIZE + pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */ +#endif + +#if LINK_STATS + lwip_stats.link.xmit++; +#endif /* LINK_STATS */ + + return ERR_OK; +} + +/* + * low_level_input(): + * + * Should allocate a pbuf and transfer the bytes of the incoming + * packet from the interface into the pbuf. + * + */ + +static struct pbuf * +low_level_input(struct netif *netif) +{ + struct ethernetif *ethernetif = netif->state; + struct pbuf *p, *q; + u16_t len; + + /* Obtain the size of the packet and put it into the "len" + variable. */ + len = ; + +#if ETH_PAD_SIZE + len += ETH_PAD_SIZE; /* allow room for Ethernet padding */ +#endif + + /* We allocate a pbuf chain of pbufs from the pool. */ + p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL); + + if (p != NULL) { + +#if ETH_PAD_SIZE + pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */ +#endif + + /* We iterate over the pbuf chain until we have read the entire + * packet into the pbuf. */ + for(q = p; q != NULL; q = q->next) { + /* Read enough bytes to fill this pbuf in the chain. The + * available data in the pbuf is given by the q->len + * variable. */ + read data into(q->payload, q->len); + } + acknowledge that packet has been read(); + +#if ETH_PAD_SIZE + pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */ +#endif + +#if LINK_STATS + lwip_stats.link.recv++; +#endif /* LINK_STATS */ + } else { + drop packet(); +#if LINK_STATS + lwip_stats.link.memerr++; + lwip_stats.link.drop++; +#endif /* LINK_STATS */ + } + + return p; +} + +/* + * ethernetif_output(): + * + * This function is called by the TCP/IP stack when an IP packet + * should be sent. It calls the function called low_level_output() to + * do the actual transmission of the packet. + * + */ + +static err_t +ethernetif_output(struct netif *netif, struct pbuf *p, + struct ip_addr *ipaddr) +{ + + /* resolve hardware address, then send (or queue) packet */ + return etharp_output(netif, ipaddr, p); + +} + +/* + * ethernetif_input(): + * + * This function should be called when a packet is ready to be read + * from the interface. It uses the function low_level_input() that + * should handle the actual reception of bytes from the network + * interface. + * + */ + +static void +ethernetif_input(struct netif *netif) +{ + struct ethernetif *ethernetif; + struct eth_hdr *ethhdr; + struct pbuf *p; + + ethernetif = netif->state; + + /* move received packet into a new pbuf */ + p = low_level_input(netif); + /* no packet could be read, silently ignore this */ + if (p == NULL) return; + /* points to packet payload, which starts with an Ethernet header */ + ethhdr = p->payload; + +#if LINK_STATS + lwip_stats.link.recv++; +#endif /* LINK_STATS */ + + ethhdr = p->payload; + + switch (htons(ethhdr->type)) { + /* IP packet? */ + case ETHTYPE_IP: +#if 0 +/* CSi disabled ARP table update on ingress IP packets. + This seems to work but needs thorough testing. */ + /* update ARP table */ + etharp_ip_input(netif, p); +#endif + /* skip Ethernet header */ + pbuf_header(p, -sizeof(struct eth_hdr)); + /* pass to network layer */ + netif->input(p, netif); + break; + + case ETHTYPE_ARP: + /* pass p to ARP module */ + etharp_arp_input(netif, ethernetif->ethaddr, p); + break; + default: + pbuf_free(p); + p = NULL; + break; + } +} + +static void +arp_timer(void *arg) +{ + etharp_tmr(); + sys_timeout(ARP_TMR_INTERVAL, arp_timer, NULL); +} + +/* + * ethernetif_init(): + * + * Should be called at the beginning of the program to set up the + * network interface. It calls the function low_level_init() to do the + * actual setup of the hardware. + * + */ + +err_t +ethernetif_init(struct netif *netif) +{ + struct ethernetif *ethernetif; + + ethernetif = mem_malloc(sizeof(struct ethernetif)); + + if (ethernetif == NULL) + { + LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_init: out of memory\n")); + return ERR_MEM; + } + +#if LWIP_SNMP + /* ifType ethernetCsmacd(6) @see RFC1213 */ + netif->link_type = 6; + /* your link speed here */ + netif->link_speed = ; + netif->ts = 0; + netif->ifinoctets = 0; + netif->ifinucastpkts = 0; + netif->ifinnucastpkts = 0; + netif->ifindiscards = 0; + netif->ifoutoctets = 0; + netif->ifoutucastpkts = 0; + netif->ifoutnucastpkts = 0; + netif->ifoutdiscards = 0; +#endif + + netif->state = ethernetif; + netif->name[0] = IFNAME0; + netif->name[1] = IFNAME1; + netif->output = ethernetif_output; + netif->linkoutput = low_level_output; + + ethernetif->ethaddr = (struct eth_addr *)&(netif->hwaddr[0]); + + low_level_init(netif); + + etharp_init(); + + sys_timeout(ARP_TMR_INTERVAL, arp_timer, NULL); + + return ERR_OK; +} + diff --git a/20080212/Demo/Common/ethernet/lwIP/netif/loopif.c b/20080212/Demo/Common/ethernet/lwIP/netif/loopif.c new file mode 100644 index 000000000..cd523fb03 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/netif/loopif.c @@ -0,0 +1,119 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#include "lwip/opt.h" + +#if LWIP_HAVE_LOOPIF + +#include "netif/loopif.h" +#include "lwip/mem.h" + +#if defined(LWIP_DEBUG) && defined(LWIP_TCPDUMP) +#include "netif/tcpdump.h" +#endif /* LWIP_DEBUG && LWIP_TCPDUMP */ + +#include "lwip/tcp.h" +#include "lwip/ip.h" + +static void +loopif_input( void * arg ) +{ + struct netif *netif = (struct netif *)( ((void **)arg)[ 0 ] ); + struct pbuf *r = (struct pbuf *)( ((void **)arg)[ 1 ] ); + + mem_free( arg ); + netif -> input( r, netif ); +} + +static err_t +loopif_output(struct netif *netif, struct pbuf *p, + struct ip_addr *ipaddr) +{ + struct pbuf *q, *r; + u8_t *ptr; + void **arg; + +#if defined(LWIP_DEBUG) && defined(LWIP_TCPDUMP) + tcpdump(p); +#endif /* LWIP_DEBUG && LWIP_TCPDUMP */ + + r = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM); + if (r != NULL) { + ptr = r->payload; + + for(q = p; q != NULL; q = q->next) { + memcpy(ptr, q->payload, q->len); + ptr += q->len; + } + + arg = mem_malloc( sizeof( void *[2])); + if( NULL == arg ) { + return ERR_MEM; + } + + arg[0] = netif; + arg[1] = r; + /** + * workaround (patch #1779) to try to prevent bug #2595: + * When connecting to "localhost" with the loopif interface, + * tcp_output doesn't get the opportunity to finnish sending the + * segment before tcp_process gets it, resulting in tcp_process + * referencing pcb->unacked-> which still is NULL. + * + * TODO: Is there still a race condition here? Leon + */ + sys_timeout( 1, loopif_input, arg ); + + return ERR_OK; + } + return ERR_MEM; +} + +err_t +loopif_init(struct netif *netif) +{ + netif->name[0] = 'l'; + netif->name[1] = 'o'; +#if 0 /** TODO: I think this should be enabled, or not? Leon */ + netif->input = loopif_input; +#endif + netif->output = loopif_output; + return ERR_OK; +} + +#endif /* LWIP_HAVE_LOOPIF */ + + + + + + + diff --git a/20080212/Demo/Common/ethernet/lwIP/netif/ppp/auth.c b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/auth.c new file mode 100644 index 000000000..0786a2e81 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/auth.c @@ -0,0 +1,927 @@ +/***************************************************************************** +* auth.c - Network Authentication and Phase Control program file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* Copyright (c) 1997 by Global Election Systems Inc. All rights reserved. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-12-08 Guy Lancaster , Global Election Systems Inc. +* Ported from public pppd code. +*****************************************************************************/ +/* + * auth.c - PPP authentication and phase control. + * + * Copyright (c) 1993 The Australian National University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by the Australian National University. The name of the University + * may not be used to endorse or promote products derived from this + * software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * Copyright (c) 1989 Carnegie Mellon University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Carnegie Mellon University. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +#include "ppp.h" +#if PPP_SUPPORT > 0 +#include "fsm.h" +#include "lcp.h" +#include "pap.h" +#include "chap.h" +#include "auth.h" +#include "ipcp.h" + +#if CBCP_SUPPORT > 0 +#include "cbcp.h" +#endif + +#include "pppdebug.h" + + +/*************************/ +/*** LOCAL DEFINITIONS ***/ +/*************************/ + +/* Bits in auth_pending[] */ +#define PAP_WITHPEER 1 +#define PAP_PEER 2 +#define CHAP_WITHPEER 4 +#define CHAP_PEER 8 + + + +/************************/ +/*** LOCAL DATA TYPES ***/ +/************************/ +/* Used for storing a sequence of words. Usually malloced. */ +struct wordlist { + struct wordlist *next; + char word[1]; +}; + + + +/***********************************/ +/*** LOCAL FUNCTION DECLARATIONS ***/ +/***********************************/ +extern char *crypt (const char *, const char *); + +/* Prototypes for procedures local to this file. */ + +static void network_phase (int); +static void check_idle (void *); +static void connect_time_expired (void *); +#if 0 +static int login (char *, char *, char **, int *); +#endif +static void logout (void); +static int null_login (int); +static int get_pap_passwd (int, char *, char *); +static int have_pap_secret (void); +static int have_chap_secret (char *, char *, u32_t); +static int ip_addr_check (u32_t, struct wordlist *); +#if 0 /* PAP_SUPPORT > 0 || CHAP_SUPPORT > 0 */ +static void set_allowed_addrs(int unit, struct wordlist *addrs); +static void free_wordlist (struct wordlist *); +#endif +#if CBCP_SUPPORT > 0 +static void callback_phase (int); +#endif + + +/******************************/ +/*** PUBLIC DATA STRUCTURES ***/ +/******************************/ + + +/*****************************/ +/*** LOCAL DATA STRUCTURES ***/ +/*****************************/ +#if PAP_SUPPORT > 0 || CHAP_SUPPORT > 0 +/* The name by which the peer authenticated itself to us. */ +static char peer_authname[MAXNAMELEN]; +#endif + +/* Records which authentication operations haven't completed yet. */ +static int auth_pending[NUM_PPP]; + +/* Set if we have successfully called login() */ +static int logged_in; + +/* Set if we have run the /etc/ppp/auth-up script. */ +static int did_authup; + +/* List of addresses which the peer may use. */ +static struct wordlist *addresses[NUM_PPP]; + +/* Number of network protocols which we have opened. */ +static int num_np_open; + +/* Number of network protocols which have come up. */ +static int num_np_up; + +#if PAP_SUPPORT > 0 || CHAP_SUPPORT > 0 +/* Set if we got the contents of passwd[] from the pap-secrets file. */ +static int passwd_from_file; +#endif + + + +/***********************************/ +/*** PUBLIC FUNCTION DEFINITIONS ***/ +/***********************************/ +/* + * An Open on LCP has requested a change from Dead to Establish phase. + * Do what's necessary to bring the physical layer up. + */ +void link_required(int unit) +{ + AUTHDEBUG((LOG_INFO, "link_required: %d\n", unit)); +} + +/* + * LCP has terminated the link; go to the Dead phase and take the + * physical layer down. + */ +void link_terminated(int unit) +{ + AUTHDEBUG((LOG_INFO, "link_terminated: %d\n", unit)); + + if (lcp_phase[unit] == PHASE_DEAD) + return; + if (logged_in) + logout(); + lcp_phase[unit] = PHASE_DEAD; + AUTHDEBUG((LOG_NOTICE, "Connection terminated.\n")); + pppMainWakeup(unit); +} + +/* + * LCP has gone down; it will either die or try to re-establish. + */ +void link_down(int unit) +{ + int i; + struct protent *protp; + + AUTHDEBUG((LOG_INFO, "link_down: %d\n", unit)); + if (did_authup) { + /* XXX Do link down processing. */ + did_authup = 0; + } + for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) { + if (!protp->enabled_flag) + continue; + if (protp->protocol != PPP_LCP && protp->lowerdown != NULL) + (*protp->lowerdown)(unit); + if (protp->protocol < 0xC000 && protp->close != NULL) + (*protp->close)(unit, "LCP down"); + } + num_np_open = 0; + num_np_up = 0; + if (lcp_phase[unit] != PHASE_DEAD) + lcp_phase[unit] = PHASE_TERMINATE; + pppMainWakeup(unit); +} + +/* + * The link is established. + * Proceed to the Dead, Authenticate or Network phase as appropriate. + */ +void link_established(int unit) +{ + int auth; + int i; + struct protent *protp; + lcp_options *wo = &lcp_wantoptions[unit]; + lcp_options *go = &lcp_gotoptions[unit]; +#if PAP_SUPPORT > 0 || CHAP_SUPPORT > 0 + lcp_options *ho = &lcp_hisoptions[unit]; +#endif + + AUTHDEBUG((LOG_INFO, "link_established: %d\n", unit)); + /* + * Tell higher-level protocols that LCP is up. + */ + for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) + if (protp->protocol != PPP_LCP && protp->enabled_flag + && protp->lowerup != NULL) + (*protp->lowerup)(unit); + + if (ppp_settings.auth_required && !(go->neg_chap || go->neg_upap)) { + /* + * We wanted the peer to authenticate itself, and it refused: + * treat it as though it authenticated with PAP using a username + * of "" and a password of "". If that's not OK, boot it out. + */ + if (!wo->neg_upap || !null_login(unit)) { + AUTHDEBUG((LOG_WARNING, "peer refused to authenticate\n")); + lcp_close(unit, "peer refused to authenticate"); + return; + } + } + + lcp_phase[unit] = PHASE_AUTHENTICATE; + auth = 0; +#if CHAP_SUPPORT > 0 + if (go->neg_chap) { + ChapAuthPeer(unit, ppp_settings.our_name, go->chap_mdtype); + auth |= CHAP_PEER; + } +#endif +#if PAP_SUPPORT > 0 && CHAP_SUPPORT > 0 + else +#endif +#if PAP_SUPPORT > 0 + if (go->neg_upap) { + upap_authpeer(unit); + auth |= PAP_PEER; + } +#endif +#if CHAP_SUPPORT > 0 + if (ho->neg_chap) { + ChapAuthWithPeer(unit, ppp_settings.user, ho->chap_mdtype); + auth |= CHAP_WITHPEER; + } +#endif +#if PAP_SUPPORT > 0 && CHAP_SUPPORT > 0 + else +#endif +#if PAP_SUPPORT > 0 + if (ho->neg_upap) { + if (ppp_settings.passwd[0] == 0) { + passwd_from_file = 1; + if (!get_pap_passwd(unit, ppp_settings.user, ppp_settings.passwd)) + AUTHDEBUG((LOG_ERR, "No secret found for PAP login\n")); + } + upap_authwithpeer(unit, ppp_settings.user, ppp_settings.passwd); + auth |= PAP_WITHPEER; + } +#endif + auth_pending[unit] = auth; + + if (!auth) + network_phase(unit); +} + + +/* + * The peer has failed to authenticate himself using `protocol'. + */ +void auth_peer_fail(int unit, u16_t protocol) +{ + AUTHDEBUG((LOG_INFO, "auth_peer_fail: %d proto=%X\n", unit, protocol)); + /* + * Authentication failure: take the link down + */ + lcp_close(unit, "Authentication failed"); +} + + +#if PAP_SUPPORT > 0 || CHAP_SUPPORT > 0 +/* + * The peer has been successfully authenticated using `protocol'. + */ +void auth_peer_success(int unit, u16_t protocol, char *name, int namelen) +{ + int pbit; + + AUTHDEBUG((LOG_INFO, "auth_peer_success: %d proto=%X\n", unit, protocol)); + switch (protocol) { + case PPP_CHAP: + pbit = CHAP_PEER; + break; + case PPP_PAP: + pbit = PAP_PEER; + break; + default: + AUTHDEBUG((LOG_WARNING, "auth_peer_success: unknown protocol %x\n", + protocol)); + return; + } + + /* + * Save the authenticated name of the peer for later. + */ + if (namelen > sizeof(peer_authname) - 1) + namelen = sizeof(peer_authname) - 1; + BCOPY(name, peer_authname, namelen); + peer_authname[namelen] = 0; + + /* + * If there is no more authentication still to be done, + * proceed to the network (or callback) phase. + */ + if ((auth_pending[unit] &= ~pbit) == 0) + network_phase(unit); +} + +/* + * We have failed to authenticate ourselves to the peer using `protocol'. + */ +void auth_withpeer_fail(int unit, u16_t protocol) +{ + int errCode = PPPERR_AUTHFAIL; + + AUTHDEBUG((LOG_INFO, "auth_withpeer_fail: %d proto=%X\n", unit, protocol)); + if (passwd_from_file) + BZERO(ppp_settings.passwd, MAXSECRETLEN); + /* + * XXX Warning: the unit number indicates the interface which is + * not necessarily the PPP connection. It works here as long + * as we are only supporting PPP interfaces. + */ + pppIOCtl(unit, PPPCTLS_ERRCODE, &errCode); + + /* + * We've failed to authenticate ourselves to our peer. + * He'll probably take the link down, and there's not much + * we can do except wait for that. + */ +} + +/* + * We have successfully authenticated ourselves with the peer using `protocol'. + */ +void auth_withpeer_success(int unit, u16_t protocol) +{ + int pbit; + + AUTHDEBUG((LOG_INFO, "auth_withpeer_success: %d proto=%X\n", unit, protocol)); + switch (protocol) { + case PPP_CHAP: + pbit = CHAP_WITHPEER; + break; + case PPP_PAP: + if (passwd_from_file) + BZERO(ppp_settings.passwd, MAXSECRETLEN); + pbit = PAP_WITHPEER; + break; + default: + AUTHDEBUG((LOG_WARNING, "auth_peer_success: unknown protocol %x\n", + protocol)); + pbit = 0; + } + + /* + * If there is no more authentication still being done, + * proceed to the network (or callback) phase. + */ + if ((auth_pending[unit] &= ~pbit) == 0) + network_phase(unit); +} +#endif + + +/* + * np_up - a network protocol has come up. + */ +void np_up(int unit, u16_t proto) +{ + AUTHDEBUG((LOG_INFO, "np_up: %d proto=%X\n", unit, proto)); + if (num_np_up == 0) { + AUTHDEBUG((LOG_INFO, "np_up: maxconnect=%d idle_time_limit=%d\n",ppp_settings.maxconnect,ppp_settings.idle_time_limit)); + /* + * At this point we consider that the link has come up successfully. + */ + if (ppp_settings.idle_time_limit > 0) + TIMEOUT(check_idle, NULL, ppp_settings.idle_time_limit); + + /* + * Set a timeout to close the connection once the maximum + * connect time has expired. + */ + if (ppp_settings.maxconnect > 0) + TIMEOUT(connect_time_expired, 0, ppp_settings.maxconnect); + } + ++num_np_up; +} + +/* + * np_down - a network protocol has gone down. + */ +void np_down(int unit, u16_t proto) +{ + AUTHDEBUG((LOG_INFO, "np_down: %d proto=%X\n", unit, proto)); + if (--num_np_up == 0 && ppp_settings.idle_time_limit > 0) { + UNTIMEOUT(check_idle, NULL); + } +} + +/* + * np_finished - a network protocol has finished using the link. + */ +void np_finished(int unit, u16_t proto) +{ + AUTHDEBUG((LOG_INFO, "np_finished: %d proto=%X\n", unit, proto)); + if (--num_np_open <= 0) { + /* no further use for the link: shut up shop. */ + lcp_close(0, "No network protocols running"); + } +} + +/* + * auth_reset - called when LCP is starting negotiations to recheck + * authentication options, i.e. whether we have appropriate secrets + * to use for authenticating ourselves and/or the peer. + */ +void auth_reset(int unit) +{ + lcp_options *go = &lcp_gotoptions[unit]; + lcp_options *ao = &lcp_allowoptions[0]; + ipcp_options *ipwo = &ipcp_wantoptions[0]; + u32_t remote; + + AUTHDEBUG((LOG_INFO, "auth_reset: %d\n", unit)); + ao->neg_upap = !ppp_settings.refuse_pap && (ppp_settings.passwd[0] != 0 || get_pap_passwd(unit, NULL, NULL)); + ao->neg_chap = !ppp_settings.refuse_chap && ppp_settings.passwd[0] != 0 /*have_chap_secret(ppp_settings.user, ppp_settings.remote_name, (u32_t)0)*/; + + if (go->neg_upap && !have_pap_secret()) + go->neg_upap = 0; + if (go->neg_chap) { + remote = ipwo->accept_remote? 0: ipwo->hisaddr; + if (!have_chap_secret(ppp_settings.remote_name, ppp_settings.our_name, remote)) + go->neg_chap = 0; + } +} + + +#if PAP_SUPPORT > 0 +/* + * check_passwd - Check the user name and passwd against the PAP secrets + * file. If requested, also check against the system password database, + * and login the user if OK. + * + * returns: + * UPAP_AUTHNAK: Authentication failed. + * UPAP_AUTHACK: Authentication succeeded. + * In either case, msg points to an appropriate message. + */ +int check_passwd( + int unit, + char *auser, + int userlen, + char *apasswd, + int passwdlen, + char **msg, + int *msglen +) +{ +#if 1 + *msg = (char *) 0; + return UPAP_AUTHACK; /* XXX Assume all entries OK. */ +#else + int ret = 0; + struct wordlist *addrs = NULL; + char passwd[256], user[256]; + char secret[MAXWORDLEN]; + static u_short attempts = 0; + + /* + * Make copies of apasswd and auser, then null-terminate them. + */ + BCOPY(apasswd, passwd, passwdlen); + passwd[passwdlen] = '\0'; + BCOPY(auser, user, userlen); + user[userlen] = '\0'; + *msg = (char *) 0; + + /* XXX Validate user name and password. */ + ret = UPAP_AUTHACK; /* XXX Assume all entries OK. */ + + if (ret == UPAP_AUTHNAK) { + if (*msg == (char *) 0) + *msg = "Login incorrect"; + *msglen = strlen(*msg); + /* + * Frustrate passwd stealer programs. + * Allow 10 tries, but start backing off after 3 (stolen from login). + * On 10'th, drop the connection. + */ + if (attempts++ >= 10) { + AUTHDEBUG((LOG_WARNING, "%d LOGIN FAILURES BY %s\n", attempts, user)); + /*ppp_panic("Excess Bad Logins");*/ + } + if (attempts > 3) { + sys_msleep((attempts - 3) * 5); + } + if (addrs != NULL) { + free_wordlist(addrs); + } + } else { + attempts = 0; /* Reset count */ + if (*msg == (char *) 0) + *msg = "Login ok"; + *msglen = strlen(*msg); + set_allowed_addrs(unit, addrs); + } + + BZERO(passwd, sizeof(passwd)); + BZERO(secret, sizeof(secret)); + + return ret; +#endif +} +#endif + + +/* + * auth_ip_addr - check whether the peer is authorized to use + * a given IP address. Returns 1 if authorized, 0 otherwise. + */ +int auth_ip_addr(int unit, u32_t addr) +{ + return ip_addr_check(addr, addresses[unit]); +} + +/* + * bad_ip_adrs - return 1 if the IP address is one we don't want + * to use, such as an address in the loopback net or a multicast address. + * addr is in network byte order. + */ +int bad_ip_adrs(u32_t addr) +{ + addr = ntohl(addr); + return (addr >> IN_CLASSA_NSHIFT) == IN_LOOPBACKNET + || IN_MULTICAST(addr) || IN_BADCLASS(addr); +} + + +#if CHAP_SUPPORT > 0 +/* + * get_secret - open the CHAP secret file and return the secret + * for authenticating the given client on the given server. + * (We could be either client or server). + */ +int get_secret( + int unit, + char *client, + char *server, + char *secret, + int *secret_len, + int save_addrs +) +{ +#if 1 + int len; + struct wordlist *addrs; + + addrs = NULL; + + if(!client || !client[0] || strcmp(client, ppp_settings.user)) { + return 0; + } + + len = strlen(ppp_settings.passwd); + if (len > MAXSECRETLEN) { + AUTHDEBUG((LOG_ERR, "Secret for %s on %s is too long\n", client, server)); + len = MAXSECRETLEN; + } + BCOPY(ppp_settings.passwd, secret, len); + *secret_len = len; + + return 1; +#else + int ret = 0, len; + struct wordlist *addrs; + char secbuf[MAXWORDLEN]; + + addrs = NULL; + secbuf[0] = 0; + + /* XXX Find secret. */ + if (ret < 0) + return 0; + + if (save_addrs) + set_allowed_addrs(unit, addrs); + + len = strlen(secbuf); + if (len > MAXSECRETLEN) { + AUTHDEBUG((LOG_ERR, "Secret for %s on %s is too long\n", client, server)); + len = MAXSECRETLEN; + } + BCOPY(secbuf, secret, len); + BZERO(secbuf, sizeof(secbuf)); + *secret_len = len; + + return 1; +#endif +} +#endif + + +#if 0 /* UNUSED */ +/* + * auth_check_options - called to check authentication options. + */ +void auth_check_options(void) +{ + lcp_options *wo = &lcp_wantoptions[0]; + int can_auth; + ipcp_options *ipwo = &ipcp_wantoptions[0]; + u32_t remote; + + /* Default our_name to hostname, and user to our_name */ + if (ppp_settings.our_name[0] == 0 || ppp_settings.usehostname) + strcpy(ppp_settings.our_name, ppp_settings.hostname); + if (ppp_settings.user[0] == 0) + strcpy(ppp_settings.user, ppp_settings.our_name); + + /* If authentication is required, ask peer for CHAP or PAP. */ + if (ppp_settings.auth_required && !wo->neg_chap && !wo->neg_upap) { + wo->neg_chap = 1; + wo->neg_upap = 1; + } + + /* + * Check whether we have appropriate secrets to use + * to authenticate the peer. + */ + can_auth = wo->neg_upap && have_pap_secret(); + if (!can_auth && wo->neg_chap) { + remote = ipwo->accept_remote? 0: ipwo->hisaddr; + can_auth = have_chap_secret(ppp_settings.remote_name, ppp_settings.our_name, remote); + } + + if (ppp_settings.auth_required && !can_auth) { + ppp_panic("No auth secret"); + } +} +#endif + + +/**********************************/ +/*** LOCAL FUNCTION DEFINITIONS ***/ +/**********************************/ +/* + * Proceed to the network phase. + */ +static void network_phase(int unit) +{ + int i; + struct protent *protp; + lcp_options *go = &lcp_gotoptions[unit]; + + /* + * If the peer had to authenticate, run the auth-up script now. + */ + if ((go->neg_chap || go->neg_upap) && !did_authup) { + /* XXX Do setup for peer authentication. */ + did_authup = 1; + } + +#if CBCP_SUPPORT > 0 + /* + * If we negotiated callback, do it now. + */ + if (go->neg_cbcp) { + lcp_phase[unit] = PHASE_CALLBACK; + (*cbcp_protent.open)(unit); + return; + } +#endif + + lcp_phase[unit] = PHASE_NETWORK; + for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) + if (protp->protocol < 0xC000 && protp->enabled_flag + && protp->open != NULL) { + (*protp->open)(unit); + if (protp->protocol != PPP_CCP) + ++num_np_open; + } + + if (num_np_open == 0) + /* nothing to do */ + lcp_close(0, "No network protocols running"); +} + +/* + * check_idle - check whether the link has been idle for long + * enough that we can shut it down. + */ +static void check_idle(void *arg) +{ + struct ppp_idle idle; + u_short itime; + + (void)arg; + if (!get_idle_time(0, &idle)) + return; + itime = LWIP_MIN(idle.xmit_idle, idle.recv_idle); + if (itime >= ppp_settings.idle_time_limit) { + /* link is idle: shut it down. */ + AUTHDEBUG((LOG_INFO, "Terminating connection due to lack of activity.\n")); + lcp_close(0, "Link inactive"); + } else { + TIMEOUT(check_idle, NULL, ppp_settings.idle_time_limit - itime); + } +} + +/* + * connect_time_expired - log a message and close the connection. + */ +static void connect_time_expired(void *arg) +{ + (void)arg; + + AUTHDEBUG((LOG_INFO, "Connect time expired\n")); + lcp_close(0, "Connect time expired"); /* Close connection */ +} + +#if 0 +/* + * login - Check the user name and password against the system + * password database, and login the user if OK. + * + * returns: + * UPAP_AUTHNAK: Login failed. + * UPAP_AUTHACK: Login succeeded. + * In either case, msg points to an appropriate message. + */ +static int login(char *user, char *passwd, char **msg, int *msglen) +{ + /* XXX Fail until we decide that we want to support logins. */ + return (UPAP_AUTHNAK); +} +#endif + +/* + * logout - Logout the user. + */ +static void logout(void) +{ + logged_in = 0; +} + + +/* + * null_login - Check if a username of "" and a password of "" are + * acceptable, and iff so, set the list of acceptable IP addresses + * and return 1. + */ +static int null_login(int unit) +{ + (void)unit; + /* XXX Fail until we decide that we want to support logins. */ + return 0; +} + + +/* + * get_pap_passwd - get a password for authenticating ourselves with + * our peer using PAP. Returns 1 on success, 0 if no suitable password + * could be found. + */ +static int get_pap_passwd(int unit, char *user, char *passwd) +{ +/* normally we would reject PAP if no password is provided, + but this causes problems with some providers (like CHT in Taiwan) + who incorrectly request PAP and expect a bogus/empty password, so + always provide a default user/passwd of "none"/"none" +*/ + if(user) + strcpy(user, "none"); + if(passwd) + strcpy(passwd, "none"); + + return 1; +} + + +/* + * have_pap_secret - check whether we have a PAP file with any + * secrets that we could possibly use for authenticating the peer. + */ +static int have_pap_secret(void) +{ + /* XXX Fail until we set up our passwords. */ + return 0; +} + + +/* + * have_chap_secret - check whether we have a CHAP file with a + * secret that we could possibly use for authenticating `client' + * on `server'. Either can be the null string, meaning we don't + * know the identity yet. + */ +static int have_chap_secret(char *client, char *server, u32_t remote) +{ + (void)client; + (void)server; + (void)remote; + /* XXX Fail until we set up our passwords. */ + return 0; +} + + +#if 0 /* PAP_SUPPORT > 0 || CHAP_SUPPORT > 0 */ +/* + * set_allowed_addrs() - set the list of allowed addresses. + */ +static void set_allowed_addrs(int unit, struct wordlist *addrs) +{ + if (addresses[unit] != NULL) + free_wordlist(addresses[unit]); + addresses[unit] = addrs; + +#if 0 + /* + * If there's only one authorized address we might as well + * ask our peer for that one right away + */ + if (addrs != NULL && addrs->next == NULL) { + char *p = addrs->word; + struct ipcp_options *wo = &ipcp_wantoptions[unit]; + u32_t a; + struct hostent *hp; + + if (wo->hisaddr == 0 && *p != '!' && *p != '-' + && strchr(p, '/') == NULL) { + hp = gethostbyname(p); + if (hp != NULL && hp->h_addrtype == AF_INET) + a = *(u32_t *)hp->h_addr; + else + a = inet_addr(p); + if (a != (u32_t) -1) + wo->hisaddr = a; + } + } +#endif +} +#endif + +static int ip_addr_check(u32_t addr, struct wordlist *addrs) +{ + + /* don't allow loopback or multicast address */ + if (bad_ip_adrs(addr)) + return 0; + + if (addrs == NULL) + return !ppp_settings.auth_required; /* no addresses authorized */ + + /* XXX All other addresses allowed. */ + return 1; +} + +#if 0 /* PAP_SUPPORT > 0 || CHAP_SUPPORT */ +/* + * free_wordlist - release memory allocated for a wordlist. + */ +static void free_wordlist(struct wordlist *wp) +{ + struct wordlist *next; + + while (wp != NULL) { + next = wp->next; + free(wp); + wp = next; + } +} +#endif + +#endif /* PPP_SUPPORT */ diff --git a/20080212/Demo/Common/ethernet/lwIP/netif/ppp/auth.h b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/auth.h new file mode 100644 index 000000000..58174056c --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/auth.h @@ -0,0 +1,94 @@ +/***************************************************************************** +* auth.h - PPP Authentication and phase control header file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1998 Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-12-04 Guy Lancaster , Global Election Systems Inc. +* Original derived from BSD pppd.h. +*****************************************************************************/ +/* + * pppd.h - PPP daemon global declarations. + * + * Copyright (c) 1989 Carnegie Mellon University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Carnegie Mellon University. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + */ + +#ifndef AUTH_H +#define AUTH_H + +/*********************** +*** PUBLIC FUNCTIONS *** +***********************/ +void link_required (int); /* we are starting to use the link */ +void link_terminated (int); /* we are finished with the link */ +void link_down (int); /* the LCP layer has left the Opened state */ +void link_established (int); /* the link is up; authenticate now */ +void np_up (int, u16_t); /* a network protocol has come up */ +void np_down (int, u16_t); /* a network protocol has gone down */ +void np_finished (int, u16_t); /* a network protocol no longer needs link */ +void auth_peer_fail (int, u16_t);/* peer failed to authenticate itself */ + +/* peer successfully authenticated itself */ +void auth_peer_success (int, u16_t, char *, int); + +/* we failed to authenticate ourselves */ +void auth_withpeer_fail (int, u16_t); + +/* we successfully authenticated ourselves */ +void auth_withpeer_success (int, u16_t); + +/* check authentication options supplied */ +void auth_check_options (void); +void auth_reset (int); /* check what secrets we have */ + +/* Check peer-supplied username/password */ +int check_passwd (int, char *, int, char *, int, char **, int *); + +/* get "secret" for chap */ +int get_secret (int, char *, char *, char *, int *, int); + +/* check if IP address is authorized */ +int auth_ip_addr (int, u32_t); + +/* check if IP address is unreasonable */ +int bad_ip_adrs (u32_t); + + +#endif /* AUTH_H */ diff --git a/20080212/Demo/Common/ethernet/lwIP/netif/ppp/chap.c b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/chap.c new file mode 100644 index 000000000..30441bdc8 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/chap.c @@ -0,0 +1,872 @@ +/*** WARNING - THIS HAS NEVER BEEN FINISHED ***/ +/***************************************************************************** +* chap.c - Network Challenge Handshake Authentication Protocol program file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1997 by Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-12-04 Guy Lancaster , Global Election Systems Inc. +* Original based on BSD chap.c. +*****************************************************************************/ +/* + * chap.c - Challenge Handshake Authentication Protocol. + * + * Copyright (c) 1993 The Australian National University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by the Australian National University. The name of the University + * may not be used to endorse or promote products derived from this + * software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * Copyright (c) 1991 Gregory M. Christy. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Gregory M. Christy. The name of the author may not be used to + * endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +#include "ppp.h" +#if PPP_SUPPORT > 0 +#include "magic.h" + +#if CHAP_SUPPORT > 0 + +#include "randm.h" +#include "auth.h" +#include "md5.h" +#include "chap.h" +#include "chpms.h" +#include "pppdebug.h" + + +/*************************/ +/*** LOCAL DEFINITIONS ***/ +/*************************/ + + +/************************/ +/*** LOCAL DATA TYPES ***/ +/************************/ + + +/***********************************/ +/*** LOCAL FUNCTION DECLARATIONS ***/ +/***********************************/ +/* + * Protocol entry points. + */ +static void ChapInit (int); +static void ChapLowerUp (int); +static void ChapLowerDown (int); +static void ChapInput (int, u_char *, int); +static void ChapProtocolReject (int); +static int ChapPrintPkt (u_char *, int, + void (*) (void *, char *, ...), void *); + +static void ChapChallengeTimeout (void *); +static void ChapResponseTimeout (void *); +static void ChapReceiveChallenge (chap_state *, u_char *, int, int); +static void ChapRechallenge (void *); +static void ChapReceiveResponse (chap_state *, u_char *, int, int); +static void ChapReceiveSuccess(chap_state *cstate, u_char *inp, u_char id, int len); +static void ChapReceiveFailure(chap_state *cstate, u_char *inp, u_char id, int len); +static void ChapSendStatus (chap_state *, int); +static void ChapSendChallenge (chap_state *); +static void ChapSendResponse (chap_state *); +static void ChapGenChallenge (chap_state *); + + +/******************************/ +/*** PUBLIC DATA STRUCTURES ***/ +/******************************/ +chap_state chap[NUM_PPP]; /* CHAP state; one for each unit */ + +struct protent chap_protent = { + PPP_CHAP, + ChapInit, + ChapInput, + ChapProtocolReject, + ChapLowerUp, + ChapLowerDown, + NULL, + NULL, +#if 0 + ChapPrintPkt, + NULL, +#endif + 1, + "CHAP", +#if 0 + NULL, + NULL, + NULL +#endif +}; + + + +/*****************************/ +/*** LOCAL DATA STRUCTURES ***/ +/*****************************/ +static char *ChapCodenames[] = { + "Challenge", "Response", "Success", "Failure" +}; + + + +/***********************************/ +/*** PUBLIC FUNCTION DEFINITIONS ***/ +/***********************************/ +/* + * ChapAuthWithPeer - Authenticate us with our peer (start client). + * + */ +void ChapAuthWithPeer(int unit, char *our_name, int digest) +{ + chap_state *cstate = &chap[unit]; + + cstate->resp_name = our_name; + cstate->resp_type = digest; + + if (cstate->clientstate == CHAPCS_INITIAL || + cstate->clientstate == CHAPCS_PENDING) { + /* lower layer isn't up - wait until later */ + cstate->clientstate = CHAPCS_PENDING; + return; + } + + /* + * We get here as a result of LCP coming up. + * So even if CHAP was open before, we will + * have to re-authenticate ourselves. + */ + cstate->clientstate = CHAPCS_LISTEN; +} + + +/* + * ChapAuthPeer - Authenticate our peer (start server). + */ +void ChapAuthPeer(int unit, char *our_name, int digest) +{ + chap_state *cstate = &chap[unit]; + + cstate->chal_name = our_name; + cstate->chal_type = digest; + + if (cstate->serverstate == CHAPSS_INITIAL || + cstate->serverstate == CHAPSS_PENDING) { + /* lower layer isn't up - wait until later */ + cstate->serverstate = CHAPSS_PENDING; + return; + } + + ChapGenChallenge(cstate); + ChapSendChallenge(cstate); /* crank it up dude! */ + cstate->serverstate = CHAPSS_INITIAL_CHAL; +} + + + + +/**********************************/ +/*** LOCAL FUNCTION DEFINITIONS ***/ +/**********************************/ +/* + * ChapInit - Initialize a CHAP unit. + */ +static void ChapInit(int unit) +{ + chap_state *cstate = &chap[unit]; + + BZERO(cstate, sizeof(*cstate)); + cstate->unit = unit; + cstate->clientstate = CHAPCS_INITIAL; + cstate->serverstate = CHAPSS_INITIAL; + cstate->timeouttime = CHAP_DEFTIMEOUT; + cstate->max_transmits = CHAP_DEFTRANSMITS; + /* random number generator is initialized in magic_init */ +} + + +/* + * ChapChallengeTimeout - Timeout expired on sending challenge. + */ +static void ChapChallengeTimeout(void *arg) +{ + chap_state *cstate = (chap_state *) arg; + + /* if we aren't sending challenges, don't worry. then again we */ + /* probably shouldn't be here either */ + if (cstate->serverstate != CHAPSS_INITIAL_CHAL && + cstate->serverstate != CHAPSS_RECHALLENGE) + return; + + if (cstate->chal_transmits >= cstate->max_transmits) { + /* give up on peer */ + CHAPDEBUG((LOG_ERR, "Peer failed to respond to CHAP challenge\n")); + cstate->serverstate = CHAPSS_BADAUTH; + auth_peer_fail(cstate->unit, PPP_CHAP); + return; + } + + ChapSendChallenge(cstate); /* Re-send challenge */ +} + + +/* + * ChapResponseTimeout - Timeout expired on sending response. + */ +static void ChapResponseTimeout(void *arg) +{ + chap_state *cstate = (chap_state *) arg; + + /* if we aren't sending a response, don't worry. */ + if (cstate->clientstate != CHAPCS_RESPONSE) + return; + + ChapSendResponse(cstate); /* re-send response */ +} + + +/* + * ChapRechallenge - Time to challenge the peer again. + */ +static void ChapRechallenge(void *arg) +{ + chap_state *cstate = (chap_state *) arg; + + /* if we aren't sending a response, don't worry. */ + if (cstate->serverstate != CHAPSS_OPEN) + return; + + ChapGenChallenge(cstate); + ChapSendChallenge(cstate); + cstate->serverstate = CHAPSS_RECHALLENGE; +} + + +/* + * ChapLowerUp - The lower layer is up. + * + * Start up if we have pending requests. + */ +static void ChapLowerUp(int unit) +{ + chap_state *cstate = &chap[unit]; + + if (cstate->clientstate == CHAPCS_INITIAL) + cstate->clientstate = CHAPCS_CLOSED; + else if (cstate->clientstate == CHAPCS_PENDING) + cstate->clientstate = CHAPCS_LISTEN; + + if (cstate->serverstate == CHAPSS_INITIAL) + cstate->serverstate = CHAPSS_CLOSED; + else if (cstate->serverstate == CHAPSS_PENDING) { + ChapGenChallenge(cstate); + ChapSendChallenge(cstate); + cstate->serverstate = CHAPSS_INITIAL_CHAL; + } +} + + +/* + * ChapLowerDown - The lower layer is down. + * + * Cancel all timeouts. + */ +static void ChapLowerDown(int unit) +{ + chap_state *cstate = &chap[unit]; + + /* Timeout(s) pending? Cancel if so. */ + if (cstate->serverstate == CHAPSS_INITIAL_CHAL || + cstate->serverstate == CHAPSS_RECHALLENGE) + UNTIMEOUT(ChapChallengeTimeout, cstate); + else if (cstate->serverstate == CHAPSS_OPEN + && cstate->chal_interval != 0) + UNTIMEOUT(ChapRechallenge, cstate); + if (cstate->clientstate == CHAPCS_RESPONSE) + UNTIMEOUT(ChapResponseTimeout, cstate); + + cstate->clientstate = CHAPCS_INITIAL; + cstate->serverstate = CHAPSS_INITIAL; +} + + +/* + * ChapProtocolReject - Peer doesn't grok CHAP. + */ +static void ChapProtocolReject(int unit) +{ + chap_state *cstate = &chap[unit]; + + if (cstate->serverstate != CHAPSS_INITIAL && + cstate->serverstate != CHAPSS_CLOSED) + auth_peer_fail(unit, PPP_CHAP); + if (cstate->clientstate != CHAPCS_INITIAL && + cstate->clientstate != CHAPCS_CLOSED) + auth_withpeer_fail(unit, PPP_CHAP); + ChapLowerDown(unit); /* shutdown chap */ +} + + +/* + * ChapInput - Input CHAP packet. + */ +static void ChapInput(int unit, u_char *inpacket, int packet_len) +{ + chap_state *cstate = &chap[unit]; + u_char *inp; + u_char code, id; + int len; + + /* + * Parse header (code, id and length). + * If packet too short, drop it. + */ + inp = inpacket; + if (packet_len < CHAP_HEADERLEN) { + CHAPDEBUG((LOG_INFO, "ChapInput: rcvd short header.\n")); + return; + } + GETCHAR(code, inp); + GETCHAR(id, inp); + GETSHORT(len, inp); + if (len < CHAP_HEADERLEN) { + CHAPDEBUG((LOG_INFO, "ChapInput: rcvd illegal length.\n")); + return; + } + if (len > packet_len) { + CHAPDEBUG((LOG_INFO, "ChapInput: rcvd short packet.\n")); + return; + } + len -= CHAP_HEADERLEN; + + /* + * Action depends on code (as in fact it usually does :-). + */ + switch (code) { + case CHAP_CHALLENGE: + ChapReceiveChallenge(cstate, inp, id, len); + break; + + case CHAP_RESPONSE: + ChapReceiveResponse(cstate, inp, id, len); + break; + + case CHAP_FAILURE: + ChapReceiveFailure(cstate, inp, id, len); + break; + + case CHAP_SUCCESS: + ChapReceiveSuccess(cstate, inp, id, len); + break; + + default: /* Need code reject? */ + CHAPDEBUG((LOG_WARNING, "Unknown CHAP code (%d) received.\n", code)); + break; + } +} + + +/* + * ChapReceiveChallenge - Receive Challenge and send Response. + */ +static void ChapReceiveChallenge(chap_state *cstate, u_char *inp, int id, int len) +{ + int rchallenge_len; + u_char *rchallenge; + int secret_len; + char secret[MAXSECRETLEN]; + char rhostname[256]; + MD5_CTX mdContext; + u_char hash[MD5_SIGNATURE_SIZE]; + + CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: Rcvd id %d.\n", id)); + if (cstate->clientstate == CHAPCS_CLOSED || + cstate->clientstate == CHAPCS_PENDING) { + CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: in state %d\n", + cstate->clientstate)); + return; + } + + if (len < 2) { + CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: rcvd short packet.\n")); + return; + } + + GETCHAR(rchallenge_len, inp); + len -= sizeof (u_char) + rchallenge_len; /* now name field length */ + if (len < 0) { + CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: rcvd short packet.\n")); + return; + } + rchallenge = inp; + INCPTR(rchallenge_len, inp); + + if (len >= sizeof(rhostname)) + len = sizeof(rhostname) - 1; + BCOPY(inp, rhostname, len); + rhostname[len] = '\000'; + + CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: received name field '%s'\n", + rhostname)); + + /* Microsoft doesn't send their name back in the PPP packet */ + if (ppp_settings.remote_name[0] != 0 && (ppp_settings.explicit_remote || rhostname[0] == 0)) { + strncpy(rhostname, ppp_settings.remote_name, sizeof(rhostname)); + rhostname[sizeof(rhostname) - 1] = 0; + CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: using '%s' as remote name\n", + rhostname)); + } + + /* get secret for authenticating ourselves with the specified host */ + if (!get_secret(cstate->unit, cstate->resp_name, rhostname, + secret, &secret_len, 0)) { + secret_len = 0; /* assume null secret if can't find one */ + CHAPDEBUG((LOG_WARNING, "No CHAP secret found for authenticating us to %s\n", rhostname)); + } + + /* cancel response send timeout if necessary */ + if (cstate->clientstate == CHAPCS_RESPONSE) + UNTIMEOUT(ChapResponseTimeout, cstate); + + cstate->resp_id = id; + cstate->resp_transmits = 0; + + /* generate MD based on negotiated type */ + switch (cstate->resp_type) { + + case CHAP_DIGEST_MD5: + MD5Init(&mdContext); + MD5Update(&mdContext, &cstate->resp_id, 1); + MD5Update(&mdContext, (u_char*)secret, secret_len); + MD5Update(&mdContext, rchallenge, rchallenge_len); + MD5Final(hash, &mdContext); + BCOPY(hash, cstate->response, MD5_SIGNATURE_SIZE); + cstate->resp_length = MD5_SIGNATURE_SIZE; + break; + +#ifdef CHAPMS + case CHAP_MICROSOFT: + ChapMS(cstate, rchallenge, rchallenge_len, secret, secret_len); + break; +#endif + + default: + CHAPDEBUG((LOG_INFO, "unknown digest type %d\n", cstate->resp_type)); + return; + } + + BZERO(secret, sizeof(secret)); + ChapSendResponse(cstate); +} + + +/* + * ChapReceiveResponse - Receive and process response. + */ +static void ChapReceiveResponse(chap_state *cstate, u_char *inp, int id, int len) +{ + u_char *remmd, remmd_len; + int secret_len, old_state; + int code; + char rhostname[256]; + MD5_CTX mdContext; + char secret[MAXSECRETLEN]; + u_char hash[MD5_SIGNATURE_SIZE]; + + CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: Rcvd id %d.\n", id)); + + if (cstate->serverstate == CHAPSS_CLOSED || + cstate->serverstate == CHAPSS_PENDING) { + CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: in state %d\n", + cstate->serverstate)); + return; + } + + if (id != cstate->chal_id) + return; /* doesn't match ID of last challenge */ + + /* + * If we have received a duplicate or bogus Response, + * we have to send the same answer (Success/Failure) + * as we did for the first Response we saw. + */ + if (cstate->serverstate == CHAPSS_OPEN) { + ChapSendStatus(cstate, CHAP_SUCCESS); + return; + } + if (cstate->serverstate == CHAPSS_BADAUTH) { + ChapSendStatus(cstate, CHAP_FAILURE); + return; + } + + if (len < 2) { + CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: rcvd short packet.\n")); + return; + } + GETCHAR(remmd_len, inp); /* get length of MD */ + remmd = inp; /* get pointer to MD */ + INCPTR(remmd_len, inp); + + len -= sizeof (u_char) + remmd_len; + if (len < 0) { + CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: rcvd short packet.\n")); + return; + } + + UNTIMEOUT(ChapChallengeTimeout, cstate); + + if (len >= sizeof(rhostname)) + len = sizeof(rhostname) - 1; + BCOPY(inp, rhostname, len); + rhostname[len] = '\000'; + + CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: received name field: %s\n", + rhostname)); + + /* + * Get secret for authenticating them with us, + * do the hash ourselves, and compare the result. + */ + code = CHAP_FAILURE; + if (!get_secret(cstate->unit, rhostname, cstate->chal_name, + secret, &secret_len, 1)) { +/* CHAPDEBUG((LOG_WARNING, TL_CHAP, "No CHAP secret found for authenticating %s\n", rhostname)); */ + CHAPDEBUG((LOG_WARNING, "No CHAP secret found for authenticating %s\n", + rhostname)); + } else { + + /* generate MD based on negotiated type */ + switch (cstate->chal_type) { + + case CHAP_DIGEST_MD5: /* only MD5 is defined for now */ + if (remmd_len != MD5_SIGNATURE_SIZE) + break; /* it's not even the right length */ + MD5Init(&mdContext); + MD5Update(&mdContext, &cstate->chal_id, 1); + MD5Update(&mdContext, (u_char*)secret, secret_len); + MD5Update(&mdContext, cstate->challenge, cstate->chal_len); + MD5Final(hash, &mdContext); + + /* compare local and remote MDs and send the appropriate status */ + if (memcmp (hash, remmd, MD5_SIGNATURE_SIZE) == 0) + code = CHAP_SUCCESS; /* they are the same! */ + break; + + default: + CHAPDEBUG((LOG_INFO, "unknown digest type %d\n", cstate->chal_type)); + } + } + + BZERO(secret, sizeof(secret)); + ChapSendStatus(cstate, code); + + if (code == CHAP_SUCCESS) { + old_state = cstate->serverstate; + cstate->serverstate = CHAPSS_OPEN; + if (old_state == CHAPSS_INITIAL_CHAL) { + auth_peer_success(cstate->unit, PPP_CHAP, rhostname, len); + } + if (cstate->chal_interval != 0) + TIMEOUT(ChapRechallenge, cstate, cstate->chal_interval); + } else { + CHAPDEBUG((LOG_ERR, "CHAP peer authentication failed\n")); + cstate->serverstate = CHAPSS_BADAUTH; + auth_peer_fail(cstate->unit, PPP_CHAP); + } +} + +/* + * ChapReceiveSuccess - Receive Success + */ +static void ChapReceiveSuccess(chap_state *cstate, u_char *inp, u_char id, int len) +{ + + CHAPDEBUG((LOG_INFO, "ChapReceiveSuccess: Rcvd id %d.\n", id)); + + if (cstate->clientstate == CHAPCS_OPEN) + /* presumably an answer to a duplicate response */ + return; + + if (cstate->clientstate != CHAPCS_RESPONSE) { + /* don't know what this is */ + CHAPDEBUG((LOG_INFO, "ChapReceiveSuccess: in state %d\n", + cstate->clientstate)); + return; + } + + UNTIMEOUT(ChapResponseTimeout, cstate); + + /* + * Print message. + */ + if (len > 0) + PRINTMSG(inp, len); + + cstate->clientstate = CHAPCS_OPEN; + + auth_withpeer_success(cstate->unit, PPP_CHAP); +} + + +/* + * ChapReceiveFailure - Receive failure. + */ +static void ChapReceiveFailure(chap_state *cstate, u_char *inp, u_char id, int len) +{ + CHAPDEBUG((LOG_INFO, "ChapReceiveFailure: Rcvd id %d.\n", id)); + + if (cstate->clientstate != CHAPCS_RESPONSE) { + /* don't know what this is */ + CHAPDEBUG((LOG_INFO, "ChapReceiveFailure: in state %d\n", + cstate->clientstate)); + return; + } + + UNTIMEOUT(ChapResponseTimeout, cstate); + + /* + * Print message. + */ + if (len > 0) + PRINTMSG(inp, len); + + CHAPDEBUG((LOG_ERR, "CHAP authentication failed\n")); + auth_withpeer_fail(cstate->unit, PPP_CHAP); +} + + +/* + * ChapSendChallenge - Send an Authenticate challenge. + */ +static void ChapSendChallenge(chap_state *cstate) +{ + u_char *outp; + int chal_len, name_len; + int outlen; + + chal_len = cstate->chal_len; + name_len = strlen(cstate->chal_name); + outlen = CHAP_HEADERLEN + sizeof (u_char) + chal_len + name_len; + outp = outpacket_buf[cstate->unit]; + + MAKEHEADER(outp, PPP_CHAP); /* paste in a CHAP header */ + + PUTCHAR(CHAP_CHALLENGE, outp); + PUTCHAR(cstate->chal_id, outp); + PUTSHORT(outlen, outp); + + PUTCHAR(chal_len, outp); /* put length of challenge */ + BCOPY(cstate->challenge, outp, chal_len); + INCPTR(chal_len, outp); + + BCOPY(cstate->chal_name, outp, name_len); /* append hostname */ + + pppWrite(cstate->unit, outpacket_buf[cstate->unit], outlen + PPP_HDRLEN); + + CHAPDEBUG((LOG_INFO, "ChapSendChallenge: Sent id %d.\n", cstate->chal_id)); + + TIMEOUT(ChapChallengeTimeout, cstate, cstate->timeouttime); + ++cstate->chal_transmits; +} + + +/* + * ChapSendStatus - Send a status response (ack or nak). + */ +static void ChapSendStatus(chap_state *cstate, int code) +{ + u_char *outp; + int outlen, msglen; + char msg[256]; + + if (code == CHAP_SUCCESS) + strcpy(msg, "Welcome!"); + else + strcpy(msg, "I don't like you. Go 'way."); + msglen = strlen(msg); + + outlen = CHAP_HEADERLEN + msglen; + outp = outpacket_buf[cstate->unit]; + + MAKEHEADER(outp, PPP_CHAP); /* paste in a header */ + + PUTCHAR(code, outp); + PUTCHAR(cstate->chal_id, outp); + PUTSHORT(outlen, outp); + BCOPY(msg, outp, msglen); + pppWrite(cstate->unit, outpacket_buf[cstate->unit], outlen + PPP_HDRLEN); + + CHAPDEBUG((LOG_INFO, "ChapSendStatus: Sent code %d, id %d.\n", code, + cstate->chal_id)); +} + +/* + * ChapGenChallenge is used to generate a pseudo-random challenge string of + * a pseudo-random length between min_len and max_len. The challenge + * string and its length are stored in *cstate, and various other fields of + * *cstate are initialized. + */ + +static void ChapGenChallenge(chap_state *cstate) +{ + int chal_len; + u_char *ptr = cstate->challenge; + int i; + + /* pick a random challenge length between MIN_CHALLENGE_LENGTH and + MAX_CHALLENGE_LENGTH */ + chal_len = (unsigned) + ((((magic() >> 16) * + (MAX_CHALLENGE_LENGTH - MIN_CHALLENGE_LENGTH)) >> 16) + + MIN_CHALLENGE_LENGTH); + cstate->chal_len = chal_len; + cstate->chal_id = ++cstate->id; + cstate->chal_transmits = 0; + + /* generate a random string */ + for (i = 0; i < chal_len; i++ ) + *ptr++ = (char) (magic() & 0xff); +} + +/* + * ChapSendResponse - send a response packet with values as specified + * in *cstate. + */ +/* ARGSUSED */ +static void ChapSendResponse(chap_state *cstate) +{ + u_char *outp; + int outlen, md_len, name_len; + + md_len = cstate->resp_length; + name_len = strlen(cstate->resp_name); + outlen = CHAP_HEADERLEN + sizeof (u_char) + md_len + name_len; + outp = outpacket_buf[cstate->unit]; + + MAKEHEADER(outp, PPP_CHAP); + + PUTCHAR(CHAP_RESPONSE, outp); /* we are a response */ + PUTCHAR(cstate->resp_id, outp); /* copy id from challenge packet */ + PUTSHORT(outlen, outp); /* packet length */ + + PUTCHAR(md_len, outp); /* length of MD */ + BCOPY(cstate->response, outp, md_len); /* copy MD to buffer */ + INCPTR(md_len, outp); + + BCOPY(cstate->resp_name, outp, name_len); /* append our name */ + + /* send the packet */ + pppWrite(cstate->unit, outpacket_buf[cstate->unit], outlen + PPP_HDRLEN); + + cstate->clientstate = CHAPCS_RESPONSE; + TIMEOUT(ChapResponseTimeout, cstate, cstate->timeouttime); + ++cstate->resp_transmits; +} + +/* + * ChapPrintPkt - print the contents of a CHAP packet. + */ +static int ChapPrintPkt( + u_char *p, + int plen, + void (*printer) (void *, char *, ...), + void *arg +) +{ + int code, id, len; + int clen, nlen; + u_char x; + + if (plen < CHAP_HEADERLEN) + return 0; + GETCHAR(code, p); + GETCHAR(id, p); + GETSHORT(len, p); + if (len < CHAP_HEADERLEN || len > plen) + return 0; + + if (code >= 1 && code <= sizeof(ChapCodenames) / sizeof(char *)) + printer(arg, " %s", ChapCodenames[code-1]); + else + printer(arg, " code=0x%x", code); + printer(arg, " id=0x%x", id); + len -= CHAP_HEADERLEN; + switch (code) { + case CHAP_CHALLENGE: + case CHAP_RESPONSE: + if (len < 1) + break; + clen = p[0]; + if (len < clen + 1) + break; + ++p; + nlen = len - clen - 1; + printer(arg, " <"); + for (; clen > 0; --clen) { + GETCHAR(x, p); + printer(arg, "%.2x", x); + } + printer(arg, ">, name = %.*Z", nlen, p); + break; + case CHAP_FAILURE: + case CHAP_SUCCESS: + printer(arg, " %.*Z", len, p); + break; + default: + for (clen = len; clen > 0; --clen) { + GETCHAR(x, p); + printer(arg, " %.2x", x); + } + } + + return len + CHAP_HEADERLEN; +} + +#endif + +#endif /* PPP_SUPPORT */ diff --git a/20080212/Demo/Common/ethernet/lwIP/netif/ppp/chap.h b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/chap.h new file mode 100644 index 000000000..1aca13414 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/chap.h @@ -0,0 +1,167 @@ +/***************************************************************************** +* chap.h - Network Challenge Handshake Authentication Protocol header file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1998 Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-12-03 Guy Lancaster , Global Election Systems Inc. +* Original built from BSD network code. +******************************************************************************/ +/* + * chap.h - Challenge Handshake Authentication Protocol definitions. + * + * Copyright (c) 1993 The Australian National University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by the Australian National University. The name of the University + * may not be used to endorse or promote products derived from this + * software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * Copyright (c) 1991 Gregory M. Christy + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by the author. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * $Id: chap.h,v 1.1 2003/05/27 14:37:56 jani Exp $ + */ + +#ifndef CHAP_H +#define CHAP_H + +/************************* +*** PUBLIC DEFINITIONS *** +*************************/ + +/* Code + ID + length */ +#define CHAP_HEADERLEN 4 + +/* + * CHAP codes. + */ + +#define CHAP_DIGEST_MD5 5 /* use MD5 algorithm */ +#define MD5_SIGNATURE_SIZE 16 /* 16 bytes in a MD5 message digest */ +#define CHAP_MICROSOFT 0x80 /* use Microsoft-compatible alg. */ +#define MS_CHAP_RESPONSE_LEN 49 /* Response length for MS-CHAP */ + +#define CHAP_CHALLENGE 1 +#define CHAP_RESPONSE 2 +#define CHAP_SUCCESS 3 +#define CHAP_FAILURE 4 + +/* + * Challenge lengths (for challenges we send) and other limits. + */ +#define MIN_CHALLENGE_LENGTH 32 +#define MAX_CHALLENGE_LENGTH 64 +#define MAX_RESPONSE_LENGTH 64 /* sufficient for MD5 or MS-CHAP */ + +/* + * Client (peer) states. + */ +#define CHAPCS_INITIAL 0 /* Lower layer down, not opened */ +#define CHAPCS_CLOSED 1 /* Lower layer up, not opened */ +#define CHAPCS_PENDING 2 /* Auth us to peer when lower up */ +#define CHAPCS_LISTEN 3 /* Listening for a challenge */ +#define CHAPCS_RESPONSE 4 /* Sent response, waiting for status */ +#define CHAPCS_OPEN 5 /* We've received Success */ + +/* + * Server (authenticator) states. + */ +#define CHAPSS_INITIAL 0 /* Lower layer down, not opened */ +#define CHAPSS_CLOSED 1 /* Lower layer up, not opened */ +#define CHAPSS_PENDING 2 /* Auth peer when lower up */ +#define CHAPSS_INITIAL_CHAL 3 /* We've sent the first challenge */ +#define CHAPSS_OPEN 4 /* We've sent a Success msg */ +#define CHAPSS_RECHALLENGE 5 /* We've sent another challenge */ +#define CHAPSS_BADAUTH 6 /* We've sent a Failure msg */ + +/************************ +*** PUBLIC DATA TYPES *** +************************/ + +/* + * Each interface is described by a chap structure. + */ + +typedef struct chap_state { + int unit; /* Interface unit number */ + int clientstate; /* Client state */ + int serverstate; /* Server state */ + u_char challenge[MAX_CHALLENGE_LENGTH]; /* last challenge string sent */ + u_char chal_len; /* challenge length */ + u_char chal_id; /* ID of last challenge */ + u_char chal_type; /* hash algorithm for challenges */ + u_char id; /* Current id */ + char *chal_name; /* Our name to use with challenge */ + int chal_interval; /* Time until we challenge peer again */ + int timeouttime; /* Timeout time in seconds */ + int max_transmits; /* Maximum # of challenge transmissions */ + int chal_transmits; /* Number of transmissions of challenge */ + int resp_transmits; /* Number of transmissions of response */ + u_char response[MAX_RESPONSE_LENGTH]; /* Response to send */ + u_char resp_length; /* length of response */ + u_char resp_id; /* ID for response messages */ + u_char resp_type; /* hash algorithm for responses */ + char *resp_name; /* Our name to send with response */ +} chap_state; + + +/****************** +*** PUBLIC DATA *** +******************/ +extern chap_state chap[]; + +extern struct protent chap_protent; + + +/*********************** +*** PUBLIC FUNCTIONS *** +***********************/ + +void ChapAuthWithPeer (int, char *, int); +void ChapAuthPeer (int, char *, int); + +#endif /* CHAP_H */ + diff --git a/20080212/Demo/Common/ethernet/lwIP/netif/ppp/chpms.c b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/chpms.c new file mode 100644 index 000000000..306434460 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/chpms.c @@ -0,0 +1,398 @@ +/*** WARNING - THIS CODE HAS NOT BEEN FINISHED! ***/ +/***************************************************************************** +* chpms.c - Network MicroSoft Challenge Handshake Authentication Protocol program file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* Copyright (c) 1997 by Global Election Systems Inc. All rights reserved. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-12-08 Guy Lancaster , Global Election Systems Inc. +* Original based on BSD chap_ms.c. +*****************************************************************************/ +/* + * chap_ms.c - Microsoft MS-CHAP compatible implementation. + * + * Copyright (c) 1995 Eric Rosenquist, Strata Software Limited. + * http://www.strataware.com/ + * + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Eric Rosenquist. The name of the author may not be used to + * endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +/* + * Modifications by Lauri Pesonen / lpesonen@clinet.fi, april 1997 + * + * Implemented LANManager type password response to MS-CHAP challenges. + * Now pppd provides both NT style and LANMan style blocks, and the + * prefered is set by option "ms-lanman". Default is to use NT. + * The hash text (StdText) was taken from Win95 RASAPI32.DLL. + * + * You should also use DOMAIN\\USERNAME as described in README.MSCHAP80 + */ + +#define USE_CRYPT + + +#include "ppp.h" + +#if MSCHAP_SUPPORT > 0 + +#include "md4.h" +#ifndef USE_CRYPT +#include "des.h" +#endif +#include "chap.h" +#include "chpms.h" +#include "pppdebug.h" + + +/*************************/ +/*** LOCAL DEFINITIONS ***/ +/*************************/ + + +/************************/ +/*** LOCAL DATA TYPES ***/ +/************************/ +typedef struct { + u_char LANManResp[24]; + u_char NTResp[24]; + u_char UseNT; /* If 1, ignore the LANMan response field */ +} MS_ChapResponse; +/* We use MS_CHAP_RESPONSE_LEN, rather than sizeof(MS_ChapResponse), + in case this struct gets padded. */ + + + +/***********************************/ +/*** LOCAL FUNCTION DECLARATIONS ***/ +/***********************************/ + +/* XXX Don't know what to do with these. */ +extern void setkey(const char *); +extern void encrypt(char *, int); + +static void DesEncrypt (u_char *, u_char *, u_char *); +static void MakeKey (u_char *, u_char *); + +#ifdef USE_CRYPT +static void Expand (u_char *, u_char *); +static void Collapse (u_char *, u_char *); +#endif + +static void ChallengeResponse( + u_char *challenge, /* IN 8 octets */ + u_char *pwHash, /* IN 16 octets */ + u_char *response /* OUT 24 octets */ +); +static void ChapMS_NT( + char *rchallenge, + int rchallenge_len, + char *secret, + int secret_len, + MS_ChapResponse *response +); +static u_char Get7Bits( + u_char *input, + int startBit +); + + +/***********************************/ +/*** PUBLIC FUNCTION DEFINITIONS ***/ +/***********************************/ +void ChapMS( + chap_state *cstate, + char *rchallenge, + int rchallenge_len, + char *secret, + int secret_len +) +{ + MS_ChapResponse response; +#ifdef MSLANMAN + extern int ms_lanman; +#endif + +#if 0 + CHAPDEBUG((LOG_INFO, "ChapMS: secret is '%.*s'\n", secret_len, secret)); +#endif + BZERO(&response, sizeof(response)); + + /* Calculate both always */ + ChapMS_NT(rchallenge, rchallenge_len, secret, secret_len, &response); + +#ifdef MSLANMAN + ChapMS_LANMan(rchallenge, rchallenge_len, secret, secret_len, &response); + + /* prefered method is set by option */ + response.UseNT = !ms_lanman; +#else + response.UseNT = 1; +#endif + + BCOPY(&response, cstate->response, MS_CHAP_RESPONSE_LEN); + cstate->resp_length = MS_CHAP_RESPONSE_LEN; +} + + +/**********************************/ +/*** LOCAL FUNCTION DEFINITIONS ***/ +/**********************************/ +static void ChallengeResponse( + u_char *challenge, /* IN 8 octets */ + u_char *pwHash, /* IN 16 octets */ + u_char *response /* OUT 24 octets */ +) +{ + char ZPasswordHash[21]; + + BZERO(ZPasswordHash, sizeof(ZPasswordHash)); + BCOPY(pwHash, ZPasswordHash, 16); + +#if 0 + log_packet(ZPasswordHash, sizeof(ZPasswordHash), "ChallengeResponse - ZPasswordHash", LOG_DEBUG); +#endif + + DesEncrypt(challenge, ZPasswordHash + 0, response + 0); + DesEncrypt(challenge, ZPasswordHash + 7, response + 8); + DesEncrypt(challenge, ZPasswordHash + 14, response + 16); + +#if 0 + log_packet(response, 24, "ChallengeResponse - response", LOG_DEBUG); +#endif +} + + +#ifdef USE_CRYPT +static void DesEncrypt( + u_char *clear, /* IN 8 octets */ + u_char *key, /* IN 7 octets */ + u_char *cipher /* OUT 8 octets */ +) +{ + u_char des_key[8]; + u_char crypt_key[66]; + u_char des_input[66]; + + MakeKey(key, des_key); + + Expand(des_key, crypt_key); + setkey(crypt_key); + +#if 0 + CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet input : %02X%02X%02X%02X%02X%02X%02X%02X\n", + clear[0], clear[1], clear[2], clear[3], clear[4], clear[5], clear[6], clear[7])); +#endif + + Expand(clear, des_input); + encrypt(des_input, 0); + Collapse(des_input, cipher); + +#if 0 + CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet output: %02X%02X%02X%02X%02X%02X%02X%02X\n", + cipher[0], cipher[1], cipher[2], cipher[3], cipher[4], cipher[5], cipher[6], cipher[7])); +#endif +} + +#else /* USE_CRYPT */ + +static void DesEncrypt( + u_char *clear, /* IN 8 octets */ + u_char *key, /* IN 7 octets */ + u_char *cipher /* OUT 8 octets */ +) +{ + des_cblock des_key; + des_key_schedule key_schedule; + + MakeKey(key, des_key); + + des_set_key(&des_key, key_schedule); + +#if 0 + CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet input : %02X%02X%02X%02X%02X%02X%02X%02X\n", + clear[0], clear[1], clear[2], clear[3], clear[4], clear[5], clear[6], clear[7])); +#endif + + des_ecb_encrypt((des_cblock *)clear, (des_cblock *)cipher, key_schedule, 1); + +#if 0 + CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet output: %02X%02X%02X%02X%02X%02X%02X%02X\n", + cipher[0], cipher[1], cipher[2], cipher[3], cipher[4], cipher[5], cipher[6], cipher[7])); +#endif +} + +#endif /* USE_CRYPT */ + + +static u_char Get7Bits( + u_char *input, + int startBit +) +{ + register unsigned int word; + + word = (unsigned)input[startBit / 8] << 8; + word |= (unsigned)input[startBit / 8 + 1]; + + word >>= 15 - (startBit % 8 + 7); + + return word & 0xFE; +} + +#ifdef USE_CRYPT + +/* in == 8-byte string (expanded version of the 56-bit key) + * out == 64-byte string where each byte is either 1 or 0 + * Note that the low-order "bit" is always ignored by by setkey() + */ +static void Expand(u_char *in, u_char *out) +{ + int j, c; + int i; + + for(i = 0; i < 64; in++){ + c = *in; + for(j = 7; j >= 0; j--) + *out++ = (c >> j) & 01; + i += 8; + } +} + +/* The inverse of Expand + */ +static void Collapse(u_char *in, u_char *out) +{ + int j; + int i; + unsigned int c; + + for (i = 0; i < 64; i += 8, out++) { + c = 0; + for (j = 7; j >= 0; j--, in++) + c |= *in << j; + *out = c & 0xff; + } +} +#endif + +static void MakeKey( + u_char *key, /* IN 56 bit DES key missing parity bits */ + u_char *des_key /* OUT 64 bit DES key with parity bits added */ +) +{ + des_key[0] = Get7Bits(key, 0); + des_key[1] = Get7Bits(key, 7); + des_key[2] = Get7Bits(key, 14); + des_key[3] = Get7Bits(key, 21); + des_key[4] = Get7Bits(key, 28); + des_key[5] = Get7Bits(key, 35); + des_key[6] = Get7Bits(key, 42); + des_key[7] = Get7Bits(key, 49); + +#ifndef USE_CRYPT + des_set_odd_parity((des_cblock *)des_key); +#endif + +#if 0 + CHAPDEBUG((LOG_INFO, "MakeKey: 56-bit input : %02X%02X%02X%02X%02X%02X%02X\n", + key[0], key[1], key[2], key[3], key[4], key[5], key[6])); + CHAPDEBUG((LOG_INFO, "MakeKey: 64-bit output: %02X%02X%02X%02X%02X%02X%02X%02X\n", + des_key[0], des_key[1], des_key[2], des_key[3], des_key[4], des_key[5], des_key[6], des_key[7])); +#endif +} + +static void ChapMS_NT( + char *rchallenge, + int rchallenge_len, + char *secret, + int secret_len, + MS_ChapResponse *response +) +{ + int i; + MDstruct md4Context; + u_char unicodePassword[MAX_NT_PASSWORD * 2]; + static int low_byte_first = -1; + + /* Initialize the Unicode version of the secret (== password). */ + /* This implicitly supports 8-bit ISO8859/1 characters. */ + BZERO(unicodePassword, sizeof(unicodePassword)); + for (i = 0; i < secret_len; i++) + unicodePassword[i * 2] = (u_char)secret[i]; + + MDbegin(&md4Context); + MDupdate(&md4Context, unicodePassword, secret_len * 2 * 8); /* Unicode is 2 bytes/char, *8 for bit count */ + + if (low_byte_first == -1) + low_byte_first = (htons((unsigned short int)1) != 1); + if (low_byte_first == 0) + MDreverse((u_long *)&md4Context); /* sfb 961105 */ + + MDupdate(&md4Context, NULL, 0); /* Tell MD4 we're done */ + + ChallengeResponse(rchallenge, (char *)md4Context.buffer, response->NTResp); +} + +#ifdef MSLANMAN +static u_char *StdText = (u_char *)"KGS!@#$%"; /* key from rasapi32.dll */ + +static ChapMS_LANMan( + char *rchallenge, + int rchallenge_len, + char *secret, + int secret_len, + MS_ChapResponse *response +) +{ + int i; + u_char UcasePassword[MAX_NT_PASSWORD]; /* max is actually 14 */ + u_char PasswordHash[16]; + + /* LANMan password is case insensitive */ + BZERO(UcasePassword, sizeof(UcasePassword)); + for (i = 0; i < secret_len; i++) + UcasePassword[i] = (u_char)toupper(secret[i]); + DesEncrypt( StdText, UcasePassword + 0, PasswordHash + 0 ); + DesEncrypt( StdText, UcasePassword + 7, PasswordHash + 8 ); + ChallengeResponse(rchallenge, PasswordHash, response->LANManResp); +} +#endif + +#endif /* MSCHAP_SUPPORT */ + diff --git a/20080212/Demo/Common/ethernet/lwIP/netif/ppp/chpms.h b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/chpms.h new file mode 100644 index 000000000..0b30c6554 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/chpms.h @@ -0,0 +1,64 @@ +/***************************************************************************** +* chpms.h - Network Microsoft Challenge Handshake Protocol header file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1998 Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 98-01-30 Guy Lancaster , Global Election Systems Inc. +* Original built from BSD network code. +******************************************************************************/ +/* + * chap.h - Challenge Handshake Authentication Protocol definitions. + * + * Copyright (c) 1995 Eric Rosenquist, Strata Software Limited. + * http://www.strataware.com/ + * + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Eric Rosenquist. The name of the author may not be used to + * endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * $Id: chpms.h,v 1.3 2004/02/07 00:30:03 likewise Exp $ + */ + +#ifndef CHPMS_H +#define CHPMS_H + +#define MAX_NT_PASSWORD 256 /* Maximum number of (Unicode) chars in an NT password */ + +void ChapMS (chap_state *, char *, int, char *, int); + +#endif /* CHPMS_H */ diff --git a/20080212/Demo/Common/ethernet/lwIP/netif/ppp/fsm.c b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/fsm.c new file mode 100644 index 000000000..6cad71525 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/fsm.c @@ -0,0 +1,838 @@ +/***************************************************************************** +* fsm.c - Network Control Protocol Finite State Machine program file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1997 by Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-12-01 Guy Lancaster , Global Election Systems Inc. +* Original based on BSD fsm.c. +*****************************************************************************/ +/* + * fsm.c - {Link, IP} Control Protocol Finite State Machine. + * + * Copyright (c) 1989 Carnegie Mellon University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Carnegie Mellon University. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + + +/* + * TODO: + * Randomize fsm id on link/init. + * Deal with variable outgoing MTU. + */ + +#include "ppp.h" +#if PPP_SUPPORT > 0 +#include "fsm.h" +#include "pppdebug.h" + + +/*************************/ +/*** LOCAL DEFINITIONS ***/ +/*************************/ + + +/************************/ +/*** LOCAL DATA TYPES ***/ +/************************/ + + +/***********************************/ +/*** LOCAL FUNCTION DECLARATIONS ***/ +/***********************************/ +static void fsm_timeout (void *); +static void fsm_rconfreq (fsm *, u_char, u_char *, int); +static void fsm_rconfack (fsm *, int, u_char *, int); +static void fsm_rconfnakrej (fsm *, int, int, u_char *, int); +static void fsm_rtermreq (fsm *, int, u_char *, int); +static void fsm_rtermack (fsm *); +static void fsm_rcoderej (fsm *, u_char *, int); +static void fsm_sconfreq (fsm *, int); + +#define PROTO_NAME(f) ((f)->callbacks->proto_name) + + +/******************************/ +/*** PUBLIC DATA STRUCTURES ***/ +/******************************/ + + +/*****************************/ +/*** LOCAL DATA STRUCTURES ***/ +/*****************************/ +int peer_mru[NUM_PPP]; + + +/***********************************/ +/*** PUBLIC FUNCTION DEFINITIONS ***/ +/***********************************/ + +/* + * fsm_init - Initialize fsm. + * + * Initialize fsm state. + */ +void fsm_init(fsm *f) +{ + f->state = INITIAL; + f->flags = 0; + f->id = 0; /* XXX Start with random id? */ + f->timeouttime = FSM_DEFTIMEOUT; + f->maxconfreqtransmits = FSM_DEFMAXCONFREQS; + f->maxtermtransmits = FSM_DEFMAXTERMREQS; + f->maxnakloops = FSM_DEFMAXNAKLOOPS; + f->term_reason_len = 0; +} + + +/* + * fsm_lowerup - The lower layer is up. + */ +void fsm_lowerup(fsm *f) +{ + int oldState = f->state; + + switch( f->state ){ + case INITIAL: + f->state = CLOSED; + break; + + case STARTING: + if( f->flags & OPT_SILENT ) + f->state = STOPPED; + else { + /* Send an initial configure-request */ + fsm_sconfreq(f, 0); + f->state = REQSENT; + } + break; + + default: + FSMDEBUG((LOG_INFO, "%s: Up event in state %d!\n", + PROTO_NAME(f), f->state)); + } + + FSMDEBUG((LOG_INFO, "%s: lowerup state %d -> %d\n", + PROTO_NAME(f), oldState, f->state)); +} + + +/* + * fsm_lowerdown - The lower layer is down. + * + * Cancel all timeouts and inform upper layers. + */ +void fsm_lowerdown(fsm *f) +{ + int oldState = f->state; + + switch( f->state ){ + case CLOSED: + f->state = INITIAL; + break; + + case STOPPED: + f->state = STARTING; + if( f->callbacks->starting ) + (*f->callbacks->starting)(f); + break; + + case CLOSING: + f->state = INITIAL; + UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ + break; + + case STOPPING: + case REQSENT: + case ACKRCVD: + case ACKSENT: + f->state = STARTING; + UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ + break; + + case OPENED: + if( f->callbacks->down ) + (*f->callbacks->down)(f); + f->state = STARTING; + break; + + default: + FSMDEBUG((LOG_INFO, "%s: Down event in state %d!\n", + PROTO_NAME(f), f->state)); + } + + FSMDEBUG((LOG_INFO, "%s: lowerdown state %d -> %d\n", + PROTO_NAME(f), oldState, f->state)); +} + + +/* + * fsm_open - Link is allowed to come up. + */ +void fsm_open(fsm *f) +{ + int oldState = f->state; + + switch( f->state ){ + case INITIAL: + f->state = STARTING; + if( f->callbacks->starting ) + (*f->callbacks->starting)(f); + break; + + case CLOSED: + if( f->flags & OPT_SILENT ) + f->state = STOPPED; + else { + /* Send an initial configure-request */ + fsm_sconfreq(f, 0); + f->state = REQSENT; + } + break; + + case CLOSING: + f->state = STOPPING; + /* fall through */ + case STOPPED: + case OPENED: + if( f->flags & OPT_RESTART ){ + fsm_lowerdown(f); + fsm_lowerup(f); + } + break; + } + + FSMDEBUG((LOG_INFO, "%s: open state %d -> %d\n", + PROTO_NAME(f), oldState, f->state)); +} + + +/* + * fsm_close - Start closing connection. + * + * Cancel timeouts and either initiate close or possibly go directly to + * the CLOSED state. + */ +void fsm_close(fsm *f, char *reason) +{ + int oldState = f->state; + + f->term_reason = reason; + f->term_reason_len = (reason == NULL? 0: strlen(reason)); + switch( f->state ){ + case STARTING: + f->state = INITIAL; + break; + case STOPPED: + f->state = CLOSED; + break; + case STOPPING: + f->state = CLOSING; + break; + + case REQSENT: + case ACKRCVD: + case ACKSENT: + case OPENED: + if( f->state != OPENED ) + UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ + else if( f->callbacks->down ) + (*f->callbacks->down)(f); /* Inform upper layers we're down */ + + /* Init restart counter, send Terminate-Request */ + f->retransmits = f->maxtermtransmits; + fsm_sdata(f, TERMREQ, f->reqid = ++f->id, + (u_char *) f->term_reason, f->term_reason_len); + TIMEOUT(fsm_timeout, f, f->timeouttime); + --f->retransmits; + + f->state = CLOSING; + break; + } + + FSMDEBUG((LOG_INFO, "%s: close reason=%s state %d -> %d\n", + PROTO_NAME(f), reason, oldState, f->state)); +} + + +/* + * fsm_sdata - Send some data. + * + * Used for all packets sent to our peer by this module. + */ +void fsm_sdata( + fsm *f, + u_char code, + u_char id, + u_char *data, + int datalen +) +{ + u_char *outp; + int outlen; + + /* Adjust length to be smaller than MTU */ + outp = outpacket_buf[f->unit]; + if (datalen > peer_mru[f->unit] - (int)HEADERLEN) + datalen = peer_mru[f->unit] - HEADERLEN; + if (datalen && data != outp + PPP_HDRLEN + HEADERLEN) + BCOPY(data, outp + PPP_HDRLEN + HEADERLEN, datalen); + outlen = datalen + HEADERLEN; + MAKEHEADER(outp, f->protocol); + PUTCHAR(code, outp); + PUTCHAR(id, outp); + PUTSHORT(outlen, outp); + pppWrite(f->unit, outpacket_buf[f->unit], outlen + PPP_HDRLEN); + FSMDEBUG((LOG_INFO, "fsm_sdata(%s): Sent code %d,%d,%d.\n", + PROTO_NAME(f), code, id, outlen)); +} + + +/* + * fsm_input - Input packet. + */ +void fsm_input(fsm *f, u_char *inpacket, int l) +{ + u_char *inp = inpacket; + u_char code, id; + int len; + + /* + * Parse header (code, id and length). + * If packet too short, drop it. + */ + if (l < HEADERLEN) { + FSMDEBUG((LOG_WARNING, "fsm_input(%x): Rcvd short header.\n", + f->protocol)); + return; + } + GETCHAR(code, inp); + GETCHAR(id, inp); + GETSHORT(len, inp); + if (len < HEADERLEN) { + FSMDEBUG((LOG_INFO, "fsm_input(%x): Rcvd illegal length.\n", + f->protocol)); + return; + } + if (len > l) { + FSMDEBUG((LOG_INFO, "fsm_input(%x): Rcvd short packet.\n", + f->protocol)); + return; + } + len -= HEADERLEN; /* subtract header length */ + + if( f->state == INITIAL || f->state == STARTING ){ + FSMDEBUG((LOG_INFO, "fsm_input(%x): Rcvd packet in state %d.\n", + f->protocol, f->state)); + return; + } + FSMDEBUG((LOG_INFO, "fsm_input(%s):%d,%d,%d\n", PROTO_NAME(f), code, id, l)); + /* + * Action depends on code. + */ + switch (code) { + case CONFREQ: + fsm_rconfreq(f, id, inp, len); + break; + + case CONFACK: + fsm_rconfack(f, id, inp, len); + break; + + case CONFNAK: + case CONFREJ: + fsm_rconfnakrej(f, code, id, inp, len); + break; + + case TERMREQ: + fsm_rtermreq(f, id, inp, len); + break; + + case TERMACK: + fsm_rtermack(f); + break; + + case CODEREJ: + fsm_rcoderej(f, inp, len); + break; + + default: + if( !f->callbacks->extcode + || !(*f->callbacks->extcode)(f, code, id, inp, len) ) + fsm_sdata(f, CODEREJ, ++f->id, inpacket, len + HEADERLEN); + break; + } +} + + +/* + * fsm_protreject - Peer doesn't speak this protocol. + * + * Treat this as a catastrophic error (RXJ-). + */ +void fsm_protreject(fsm *f) +{ + switch( f->state ){ + case CLOSING: + UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ + /* fall through */ + case CLOSED: + f->state = CLOSED; + if( f->callbacks->finished ) + (*f->callbacks->finished)(f); + break; + + case STOPPING: + case REQSENT: + case ACKRCVD: + case ACKSENT: + UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ + /* fall through */ + case STOPPED: + f->state = STOPPED; + if( f->callbacks->finished ) + (*f->callbacks->finished)(f); + break; + + case OPENED: + if( f->callbacks->down ) + (*f->callbacks->down)(f); + + /* Init restart counter, send Terminate-Request */ + f->retransmits = f->maxtermtransmits; + fsm_sdata(f, TERMREQ, f->reqid = ++f->id, + (u_char *) f->term_reason, f->term_reason_len); + TIMEOUT(fsm_timeout, f, f->timeouttime); + --f->retransmits; + + f->state = STOPPING; + break; + + default: + FSMDEBUG((LOG_INFO, "%s: Protocol-reject event in state %d!\n", + PROTO_NAME(f), f->state)); + } +} + + + + + +/**********************************/ +/*** LOCAL FUNCTION DEFINITIONS ***/ +/**********************************/ + +/* + * fsm_timeout - Timeout expired. + */ +static void fsm_timeout(void *arg) +{ + fsm *f = (fsm *) arg; + + switch (f->state) { + case CLOSING: + case STOPPING: + if( f->retransmits <= 0 ){ + FSMDEBUG((LOG_WARNING, "%s: timeout sending Terminate-Request state=%d\n", + PROTO_NAME(f), f->state)); + /* + * We've waited for an ack long enough. Peer probably heard us. + */ + f->state = (f->state == CLOSING)? CLOSED: STOPPED; + if( f->callbacks->finished ) + (*f->callbacks->finished)(f); + } else { + FSMDEBUG((LOG_WARNING, "%s: timeout resending Terminate-Requests state=%d\n", + PROTO_NAME(f), f->state)); + /* Send Terminate-Request */ + fsm_sdata(f, TERMREQ, f->reqid = ++f->id, + (u_char *) f->term_reason, f->term_reason_len); + TIMEOUT(fsm_timeout, f, f->timeouttime); + --f->retransmits; + } + break; + + case REQSENT: + case ACKRCVD: + case ACKSENT: + if (f->retransmits <= 0) { + FSMDEBUG((LOG_WARNING, "%s: timeout sending Config-Requests state=%d\n", + PROTO_NAME(f), f->state)); + f->state = STOPPED; + if( (f->flags & OPT_PASSIVE) == 0 && f->callbacks->finished ) + (*f->callbacks->finished)(f); + + } else { + FSMDEBUG((LOG_WARNING, "%s: timeout resending Config-Request state=%d\n", + PROTO_NAME(f), f->state)); + /* Retransmit the configure-request */ + if (f->callbacks->retransmit) + (*f->callbacks->retransmit)(f); + fsm_sconfreq(f, 1); /* Re-send Configure-Request */ + if( f->state == ACKRCVD ) + f->state = REQSENT; + } + break; + + default: + FSMDEBUG((LOG_INFO, "%s: Timeout event in state %d!\n", + PROTO_NAME(f), f->state)); + } +} + + +/* + * fsm_rconfreq - Receive Configure-Request. + */ +static void fsm_rconfreq(fsm *f, u_char id, u_char *inp, int len) +{ + int code, reject_if_disagree; + + FSMDEBUG((LOG_INFO, "fsm_rconfreq(%s): Rcvd id %d state=%d\n", + PROTO_NAME(f), id, f->state)); + switch( f->state ){ + case CLOSED: + /* Go away, we're closed */ + fsm_sdata(f, TERMACK, id, NULL, 0); + return; + case CLOSING: + case STOPPING: + return; + + case OPENED: + /* Go down and restart negotiation */ + if( f->callbacks->down ) + (*f->callbacks->down)(f); /* Inform upper layers */ + fsm_sconfreq(f, 0); /* Send initial Configure-Request */ + break; + + case STOPPED: + /* Negotiation started by our peer */ + fsm_sconfreq(f, 0); /* Send initial Configure-Request */ + f->state = REQSENT; + break; + } + + /* + * Pass the requested configuration options + * to protocol-specific code for checking. + */ + if (f->callbacks->reqci){ /* Check CI */ + reject_if_disagree = (f->nakloops >= f->maxnakloops); + code = (*f->callbacks->reqci)(f, inp, &len, reject_if_disagree); + } + else if (len) + code = CONFREJ; /* Reject all CI */ + else + code = CONFACK; + + /* send the Ack, Nak or Rej to the peer */ + fsm_sdata(f, (u_char)code, id, inp, len); + + if (code == CONFACK) { + if (f->state == ACKRCVD) { + UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ + f->state = OPENED; + if (f->callbacks->up) + (*f->callbacks->up)(f); /* Inform upper layers */ + } + else + f->state = ACKSENT; + f->nakloops = 0; + } + else { + /* we sent CONFACK or CONFREJ */ + if (f->state != ACKRCVD) + f->state = REQSENT; + if( code == CONFNAK ) + ++f->nakloops; + } +} + + +/* + * fsm_rconfack - Receive Configure-Ack. + */ +static void fsm_rconfack(fsm *f, int id, u_char *inp, int len) +{ + FSMDEBUG((LOG_INFO, "fsm_rconfack(%s): Rcvd id %d state=%d\n", + PROTO_NAME(f), id, f->state)); + + if (id != f->reqid || f->seen_ack) /* Expected id? */ + return; /* Nope, toss... */ + if( !(f->callbacks->ackci? (*f->callbacks->ackci)(f, inp, len): + (len == 0)) ){ + /* Ack is bad - ignore it */ + FSMDEBUG((LOG_INFO, "%s: received bad Ack (length %d)\n", + PROTO_NAME(f), len)); + return; + } + f->seen_ack = 1; + + switch (f->state) { + case CLOSED: + case STOPPED: + fsm_sdata(f, TERMACK, (u_char)id, NULL, 0); + break; + + case REQSENT: + f->state = ACKRCVD; + f->retransmits = f->maxconfreqtransmits; + break; + + case ACKRCVD: + /* Huh? an extra valid Ack? oh well... */ + UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ + fsm_sconfreq(f, 0); + f->state = REQSENT; + break; + + case ACKSENT: + UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ + f->state = OPENED; + f->retransmits = f->maxconfreqtransmits; + if (f->callbacks->up) + (*f->callbacks->up)(f); /* Inform upper layers */ + break; + + case OPENED: + /* Go down and restart negotiation */ + if (f->callbacks->down) + (*f->callbacks->down)(f); /* Inform upper layers */ + fsm_sconfreq(f, 0); /* Send initial Configure-Request */ + f->state = REQSENT; + break; + } +} + + +/* + * fsm_rconfnakrej - Receive Configure-Nak or Configure-Reject. + */ +static void fsm_rconfnakrej(fsm *f, int code, int id, u_char *inp, int len) +{ + int (*proc) (fsm *, u_char *, int); + int ret; + + FSMDEBUG((LOG_INFO, "fsm_rconfnakrej(%s): Rcvd id %d state=%d\n", + PROTO_NAME(f), id, f->state)); + + if (id != f->reqid || f->seen_ack) /* Expected id? */ + return; /* Nope, toss... */ + proc = (code == CONFNAK)? f->callbacks->nakci: f->callbacks->rejci; + if (!proc || !(ret = proc(f, inp, len))) { + /* Nak/reject is bad - ignore it */ + FSMDEBUG((LOG_INFO, "%s: received bad %s (length %d)\n", + PROTO_NAME(f), (code==CONFNAK? "Nak": "reject"), len)); + return; + } + f->seen_ack = 1; + + switch (f->state) { + case CLOSED: + case STOPPED: + fsm_sdata(f, TERMACK, (u_char)id, NULL, 0); + break; + + case REQSENT: + case ACKSENT: + /* They didn't agree to what we wanted - try another request */ + UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ + if (ret < 0) + f->state = STOPPED; /* kludge for stopping CCP */ + else + fsm_sconfreq(f, 0); /* Send Configure-Request */ + break; + + case ACKRCVD: + /* Got a Nak/reject when we had already had an Ack?? oh well... */ + UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ + fsm_sconfreq(f, 0); + f->state = REQSENT; + break; + + case OPENED: + /* Go down and restart negotiation */ + if (f->callbacks->down) + (*f->callbacks->down)(f); /* Inform upper layers */ + fsm_sconfreq(f, 0); /* Send initial Configure-Request */ + f->state = REQSENT; + break; + } +} + + +/* + * fsm_rtermreq - Receive Terminate-Req. + */ +static void fsm_rtermreq(fsm *f, int id, u_char *p, int len) +{ + FSMDEBUG((LOG_INFO, "fsm_rtermreq(%s): Rcvd id %d state=%d\n", + PROTO_NAME(f), id, f->state)); + + switch (f->state) { + case ACKRCVD: + case ACKSENT: + f->state = REQSENT; /* Start over but keep trying */ + break; + + case OPENED: + if (len > 0) { + FSMDEBUG((LOG_INFO, "%s terminated by peer (%x)\n", PROTO_NAME(f), p)); + } else { + FSMDEBUG((LOG_INFO, "%s terminated by peer\n", PROTO_NAME(f))); + } + if (f->callbacks->down) + (*f->callbacks->down)(f); /* Inform upper layers */ + f->retransmits = 0; + f->state = STOPPING; + TIMEOUT(fsm_timeout, f, f->timeouttime); + break; + } + + fsm_sdata(f, TERMACK, (u_char)id, NULL, 0); +} + + +/* + * fsm_rtermack - Receive Terminate-Ack. + */ +static void fsm_rtermack(fsm *f) +{ + FSMDEBUG((LOG_INFO, "fsm_rtermack(%s): state=%d\n", + PROTO_NAME(f), f->state)); + + switch (f->state) { + case CLOSING: + UNTIMEOUT(fsm_timeout, f); + f->state = CLOSED; + if( f->callbacks->finished ) + (*f->callbacks->finished)(f); + break; + case STOPPING: + UNTIMEOUT(fsm_timeout, f); + f->state = STOPPED; + if( f->callbacks->finished ) + (*f->callbacks->finished)(f); + break; + + case ACKRCVD: + f->state = REQSENT; + break; + + case OPENED: + if (f->callbacks->down) + (*f->callbacks->down)(f); /* Inform upper layers */ + fsm_sconfreq(f, 0); + break; + } +} + + +/* + * fsm_rcoderej - Receive an Code-Reject. + */ +static void fsm_rcoderej(fsm *f, u_char *inp, int len) +{ + u_char code, id; + + FSMDEBUG((LOG_INFO, "fsm_rcoderej(%s): state=%d\n", + PROTO_NAME(f), f->state)); + + if (len < HEADERLEN) { + FSMDEBUG((LOG_INFO, "fsm_rcoderej: Rcvd short Code-Reject packet!\n")); + return; + } + GETCHAR(code, inp); + GETCHAR(id, inp); + FSMDEBUG((LOG_WARNING, "%s: Rcvd Code-Reject for code %d, id %d\n", + PROTO_NAME(f), code, id)); + + if( f->state == ACKRCVD ) + f->state = REQSENT; +} + + +/* + * fsm_sconfreq - Send a Configure-Request. + */ +static void fsm_sconfreq(fsm *f, int retransmit) +{ + u_char *outp; + int cilen; + + if( f->state != REQSENT && f->state != ACKRCVD && f->state != ACKSENT ){ + /* Not currently negotiating - reset options */ + if( f->callbacks->resetci ) + (*f->callbacks->resetci)(f); + f->nakloops = 0; + } + + if( !retransmit ){ + /* New request - reset retransmission counter, use new ID */ + f->retransmits = f->maxconfreqtransmits; + f->reqid = ++f->id; + } + + f->seen_ack = 0; + + /* + * Make up the request packet + */ + outp = outpacket_buf[f->unit] + PPP_HDRLEN + HEADERLEN; + if( f->callbacks->cilen && f->callbacks->addci ){ + cilen = (*f->callbacks->cilen)(f); + if( cilen > peer_mru[f->unit] - (int)HEADERLEN ) + cilen = peer_mru[f->unit] - HEADERLEN; + if (f->callbacks->addci) + (*f->callbacks->addci)(f, outp, &cilen); + } else + cilen = 0; + + /* send the request to our peer */ + fsm_sdata(f, CONFREQ, f->reqid, outp, cilen); + + /* start the retransmit timer */ + --f->retransmits; + TIMEOUT(fsm_timeout, f, f->timeouttime); + + FSMDEBUG((LOG_INFO, "%s: sending Configure-Request, id %d\n", + PROTO_NAME(f), f->reqid)); +} + +#endif /* PPP_SUPPORT */ diff --git a/20080212/Demo/Common/ethernet/lwIP/netif/ppp/fsm.h b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/fsm.h new file mode 100644 index 000000000..4cca402e0 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/fsm.h @@ -0,0 +1,187 @@ +/***************************************************************************** +* fsm.h - Network Control Protocol Finite State Machine header file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* Copyright (c) 1997 Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-11-05 Guy Lancaster , Global Election Systems Inc. +* Original based on BSD code. +*****************************************************************************/ +/* + * fsm.h - {Link, IP} Control Protocol Finite State Machine definitions. + * + * Copyright (c) 1989 Carnegie Mellon University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Carnegie Mellon University. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * $Id: fsm.h,v 1.1 2003/05/27 14:37:56 jani Exp $ + */ + +#ifndef FSM_H +#define FSM_H + + +/***************************************************************************** +************************* PUBLIC DEFINITIONS ********************************* +*****************************************************************************/ +/* + * LCP Packet header = Code, id, length. + */ +#define HEADERLEN (sizeof (u_char) + sizeof (u_char) + sizeof (u_short)) + + +/* + * CP (LCP, IPCP, etc.) codes. + */ +#define CONFREQ 1 /* Configuration Request */ +#define CONFACK 2 /* Configuration Ack */ +#define CONFNAK 3 /* Configuration Nak */ +#define CONFREJ 4 /* Configuration Reject */ +#define TERMREQ 5 /* Termination Request */ +#define TERMACK 6 /* Termination Ack */ +#define CODEREJ 7 /* Code Reject */ + +/* + * Link states. + */ +#define INITIAL 0 /* Down, hasn't been opened */ +#define STARTING 1 /* Down, been opened */ +#define CLOSED 2 /* Up, hasn't been opened */ +#define STOPPED 3 /* Open, waiting for down event */ +#define CLOSING 4 /* Terminating the connection, not open */ +#define STOPPING 5 /* Terminating, but open */ +#define REQSENT 6 /* We've sent a Config Request */ +#define ACKRCVD 7 /* We've received a Config Ack */ +#define ACKSENT 8 /* We've sent a Config Ack */ +#define OPENED 9 /* Connection available */ + + +/* + * Flags - indicate options controlling FSM operation + */ +#define OPT_PASSIVE 1 /* Don't die if we don't get a response */ +#define OPT_RESTART 2 /* Treat 2nd OPEN as DOWN, UP */ +#define OPT_SILENT 4 /* Wait for peer to speak first */ + + +/***************************************************************************** +************************* PUBLIC DATA TYPES ********************************** +*****************************************************************************/ +/* + * Each FSM is described by an fsm structure and fsm callbacks. + */ +typedef struct fsm { + int unit; /* Interface unit number */ + u_short protocol; /* Data Link Layer Protocol field value */ + int state; /* State */ + int flags; /* Contains option bits */ + u_char id; /* Current id */ + u_char reqid; /* Current request id */ + u_char seen_ack; /* Have received valid Ack/Nak/Rej to Req */ + int timeouttime; /* Timeout time in milliseconds */ + int maxconfreqtransmits;/* Maximum Configure-Request transmissions */ + int retransmits; /* Number of retransmissions left */ + int maxtermtransmits; /* Maximum Terminate-Request transmissions */ + int nakloops; /* Number of nak loops since last ack */ + int maxnakloops; /* Maximum number of nak loops tolerated */ + struct fsm_callbacks* callbacks;/* Callback routines */ + char* term_reason; /* Reason for closing protocol */ + int term_reason_len; /* Length of term_reason */ +} fsm; + + +typedef struct fsm_callbacks { + void (*resetci) /* Reset our Configuration Information */ + (fsm*); + int (*cilen) /* Length of our Configuration Information */ + (fsm*); + void (*addci) /* Add our Configuration Information */ + (fsm*, u_char*, int*); + int (*ackci) /* ACK our Configuration Information */ + (fsm*, u_char*, int); + int (*nakci) /* NAK our Configuration Information */ + (fsm*, u_char*, int); + int (*rejci) /* Reject our Configuration Information */ + (fsm*, u_char*, int); + int (*reqci) /* Request peer's Configuration Information */ + (fsm*, u_char*, int*, int); + void (*up) /* Called when fsm reaches OPENED state */ + (fsm*); + void (*down) /* Called when fsm leaves OPENED state */ + (fsm*); + void (*starting) /* Called when we want the lower layer */ + (fsm*); + void (*finished) /* Called when we don't want the lower layer */ + (fsm*); + void (*protreject) /* Called when Protocol-Reject received */ + (int); + void (*retransmit) /* Retransmission is necessary */ + (fsm*); + int (*extcode) /* Called when unknown code received */ + (fsm*, int, u_char, u_char*, int); + char *proto_name; /* String name for protocol (for messages) */ +} fsm_callbacks; + + +/***************************************************************************** +*********************** PUBLIC DATA STRUCTURES ******************************* +*****************************************************************************/ +/* + * Variables + */ +extern int peer_mru[]; /* currently negotiated peer MRU (per unit) */ + + +/***************************************************************************** +************************** PUBLIC FUNCTIONS ********************************** +*****************************************************************************/ + +/* + * Prototypes + */ +void fsm_init (fsm*); +void fsm_lowerup (fsm*); +void fsm_lowerdown (fsm*); +void fsm_open (fsm*); +void fsm_close (fsm*, char*); +void fsm_input (fsm*, u_char*, int); +void fsm_protreject (fsm*); +void fsm_sdata (fsm*, u_char, u_char, u_char*, int); + + +#endif /* FSM_H */ + diff --git a/20080212/Demo/Common/ethernet/lwIP/netif/ppp/ipcp.c b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/ipcp.c new file mode 100644 index 000000000..ec3207a0c --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/ipcp.c @@ -0,0 +1,1377 @@ +/***************************************************************************** +* ipcp.c - Network PPP IP Control Protocol program file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1997 by Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-12-08 Guy Lancaster , Global Election Systems Inc. +* Original. +*****************************************************************************/ +/* + * ipcp.c - PPP IP Control Protocol. + * + * Copyright (c) 1989 Carnegie Mellon University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Carnegie Mellon University. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +#include + +#include "ppp.h" +#if PPP_SUPPORT > 0 +#include "auth.h" +#include "fsm.h" +#include "vj.h" +#include "ipcp.h" +#include "pppdebug.h" + + +/*************************/ +/*** LOCAL DEFINITIONS ***/ +/*************************/ +/* #define OLD_CI_ADDRS 1 */ /* Support deprecated address negotiation. */ + +/* + * Lengths of configuration options. + */ +#define CILEN_VOID 2 +#define CILEN_COMPRESS 4 /* min length for compression protocol opt. */ +#define CILEN_VJ 6 /* length for RFC1332 Van-Jacobson opt. */ +#define CILEN_ADDR 6 /* new-style single address option */ +#define CILEN_ADDRS 10 /* old-style dual address option */ + + + +/***********************************/ +/*** LOCAL FUNCTION DECLARATIONS ***/ +/***********************************/ +/* + * Callbacks for fsm code. (CI = Configuration Information) + */ +static void ipcp_resetci (fsm *); /* Reset our CI */ +static int ipcp_cilen (fsm *); /* Return length of our CI */ +static void ipcp_addci (fsm *, u_char *, int *); /* Add our CI */ +static int ipcp_ackci (fsm *, u_char *, int); /* Peer ack'd our CI */ +static int ipcp_nakci (fsm *, u_char *, int); /* Peer nak'd our CI */ +static int ipcp_rejci (fsm *, u_char *, int); /* Peer rej'd our CI */ +static int ipcp_reqci (fsm *, u_char *, int *, int); /* Rcv CI */ +static void ipcp_up (fsm *); /* We're UP */ +static void ipcp_down (fsm *); /* We're DOWN */ +#if 0 +static void ipcp_script (fsm *, char *); /* Run an up/down script */ +#endif +static void ipcp_finished (fsm *); /* Don't need lower layer */ + +/* + * Protocol entry points from main code. + */ +static void ipcp_init (int); +static void ipcp_open (int); +static void ipcp_close (int, char *); +static void ipcp_lowerup (int); +static void ipcp_lowerdown (int); +static void ipcp_input (int, u_char *, int); +static void ipcp_protrej (int); + +static void ipcp_clear_addrs (int); + +#define CODENAME(x) ((x) == CONFACK ? "ACK" : \ + (x) == CONFNAK ? "NAK" : "REJ") + + + +/******************************/ +/*** PUBLIC DATA STRUCTURES ***/ +/******************************/ +/* global vars */ +ipcp_options ipcp_wantoptions[NUM_PPP]; /* Options that we want to request */ +ipcp_options ipcp_gotoptions[NUM_PPP]; /* Options that peer ack'd */ +ipcp_options ipcp_allowoptions[NUM_PPP]; /* Options we allow peer to request */ +ipcp_options ipcp_hisoptions[NUM_PPP]; /* Options that we ack'd */ + +fsm ipcp_fsm[NUM_PPP]; /* IPCP fsm structure */ + +struct protent ipcp_protent = { + PPP_IPCP, + ipcp_init, + ipcp_input, + ipcp_protrej, + ipcp_lowerup, + ipcp_lowerdown, + ipcp_open, + ipcp_close, +#if 0 + ipcp_printpkt, + NULL, +#endif + 1, + "IPCP", +#if 0 + ip_check_options, + NULL, + ip_active_pkt +#endif +}; + + + +/*****************************/ +/*** LOCAL DATA STRUCTURES ***/ +/*****************************/ +/* local vars */ +static int cis_received[NUM_PPP]; /* # Conf-Reqs received */ +static int default_route_set[NUM_PPP]; /* Have set up a default route */ + +static fsm_callbacks ipcp_callbacks = { /* IPCP callback routines */ + ipcp_resetci, /* Reset our Configuration Information */ + ipcp_cilen, /* Length of our Configuration Information */ + ipcp_addci, /* Add our Configuration Information */ + ipcp_ackci, /* ACK our Configuration Information */ + ipcp_nakci, /* NAK our Configuration Information */ + ipcp_rejci, /* Reject our Configuration Information */ + ipcp_reqci, /* Request peer's Configuration Information */ + ipcp_up, /* Called when fsm reaches OPENED state */ + ipcp_down, /* Called when fsm leaves OPENED state */ + NULL, /* Called when we want the lower layer up */ + ipcp_finished, /* Called when we want the lower layer down */ + NULL, /* Called when Protocol-Reject received */ + NULL, /* Retransmission is necessary */ + NULL, /* Called to handle protocol-specific codes */ + "IPCP" /* String name of protocol */ +}; + + + +/**********************************/ +/*** LOCAL FUNCTION DEFINITIONS ***/ +/**********************************/ + +/* + * Non-standard inet_ntoa left here for compat with original ppp + * sources. Assumes u32_t instead of struct in_addr. + */ + +char * _inet_ntoa(u32_t n) +{ + struct in_addr ia; + ia.s_addr = n; + return inet_ntoa(ia); +} + +#define inet_ntoa _inet_ntoa + +/* + * ipcp_init - Initialize IPCP. + */ +static void ipcp_init(int unit) +{ + fsm *f = &ipcp_fsm[unit]; + ipcp_options *wo = &ipcp_wantoptions[unit]; + ipcp_options *ao = &ipcp_allowoptions[unit]; + + f->unit = unit; + f->protocol = PPP_IPCP; + f->callbacks = &ipcp_callbacks; + fsm_init(&ipcp_fsm[unit]); + + memset(wo, 0, sizeof(*wo)); + memset(ao, 0, sizeof(*ao)); + + wo->neg_addr = 1; + wo->ouraddr = 0; +#if VJ_SUPPORT > 0 + wo->neg_vj = 1; +#else + wo->neg_vj = 0; +#endif + wo->vj_protocol = IPCP_VJ_COMP; + wo->maxslotindex = MAX_SLOTS - 1; + wo->cflag = 0; + + wo->default_route = 1; + + ao->neg_addr = 1; +#if VJ_SUPPORT > 0 + ao->neg_vj = 1; +#else + ao->neg_vj = 0; +#endif + ao->maxslotindex = MAX_SLOTS - 1; + ao->cflag = 1; + + ao->default_route = 1; +} + + +/* + * ipcp_open - IPCP is allowed to come up. + */ +static void ipcp_open(int unit) +{ + fsm_open(&ipcp_fsm[unit]); +} + + +/* + * ipcp_close - Take IPCP down. + */ +static void ipcp_close(int unit, char *reason) +{ + fsm_close(&ipcp_fsm[unit], reason); +} + + +/* + * ipcp_lowerup - The lower layer is up. + */ +static void ipcp_lowerup(int unit) +{ + fsm_lowerup(&ipcp_fsm[unit]); +} + + +/* + * ipcp_lowerdown - The lower layer is down. + */ +static void ipcp_lowerdown(int unit) +{ + fsm_lowerdown(&ipcp_fsm[unit]); +} + + +/* + * ipcp_input - Input IPCP packet. + */ +static void ipcp_input(int unit, u_char *p, int len) +{ + fsm_input(&ipcp_fsm[unit], p, len); +} + + +/* + * ipcp_protrej - A Protocol-Reject was received for IPCP. + * + * Pretend the lower layer went down, so we shut up. + */ +static void ipcp_protrej(int unit) +{ + fsm_lowerdown(&ipcp_fsm[unit]); +} + + +/* + * ipcp_resetci - Reset our CI. + */ +static void ipcp_resetci(fsm *f) +{ + ipcp_options *wo = &ipcp_wantoptions[f->unit]; + + wo->req_addr = wo->neg_addr && ipcp_allowoptions[f->unit].neg_addr; + if (wo->ouraddr == 0) + wo->accept_local = 1; + if (wo->hisaddr == 0) + wo->accept_remote = 1; + /* Request DNS addresses from the peer */ + wo->req_dns1 = ppp_settings.usepeerdns; + wo->req_dns2 = ppp_settings.usepeerdns; + ipcp_gotoptions[f->unit] = *wo; + cis_received[f->unit] = 0; +} + + +/* + * ipcp_cilen - Return length of our CI. + */ +static int ipcp_cilen(fsm *f) +{ + ipcp_options *go = &ipcp_gotoptions[f->unit]; + ipcp_options *wo = &ipcp_wantoptions[f->unit]; + ipcp_options *ho = &ipcp_hisoptions[f->unit]; + +#define LENCIVJ(neg, old) (neg ? (old? CILEN_COMPRESS : CILEN_VJ) : 0) +#define LENCIADDR(neg, old) (neg ? (old? CILEN_ADDRS : CILEN_ADDR) : 0) +#define LENCIDNS(neg) (neg ? (CILEN_ADDR) : 0) + + /* + * First see if we want to change our options to the old + * forms because we have received old forms from the peer. + */ + if (wo->neg_addr && !go->neg_addr && !go->old_addrs) { + /* use the old style of address negotiation */ + go->neg_addr = 1; + go->old_addrs = 1; + } + if (wo->neg_vj && !go->neg_vj && !go->old_vj) { + /* try an older style of VJ negotiation */ + if (cis_received[f->unit] == 0) { + /* keep trying the new style until we see some CI from the peer */ + go->neg_vj = 1; + } else { + /* use the old style only if the peer did */ + if (ho->neg_vj && ho->old_vj) { + go->neg_vj = 1; + go->old_vj = 1; + go->vj_protocol = ho->vj_protocol; + } + } + } + + return (LENCIADDR(go->neg_addr, go->old_addrs) + + LENCIVJ(go->neg_vj, go->old_vj) + + LENCIDNS(go->req_dns1) + + LENCIDNS(go->req_dns2)); +} + + +/* + * ipcp_addci - Add our desired CIs to a packet. + */ +static void ipcp_addci(fsm *f, u_char *ucp, int *lenp) +{ + ipcp_options *go = &ipcp_gotoptions[f->unit]; + int len = *lenp; + +#define ADDCIVJ(opt, neg, val, old, maxslotindex, cflag) \ + if (neg) { \ + int vjlen = old? CILEN_COMPRESS : CILEN_VJ; \ + if (len >= vjlen) { \ + PUTCHAR(opt, ucp); \ + PUTCHAR(vjlen, ucp); \ + PUTSHORT(val, ucp); \ + if (!old) { \ + PUTCHAR(maxslotindex, ucp); \ + PUTCHAR(cflag, ucp); \ + } \ + len -= vjlen; \ + } else \ + neg = 0; \ + } + +#define ADDCIADDR(opt, neg, old, val1, val2) \ + if (neg) { \ + int addrlen = (old? CILEN_ADDRS: CILEN_ADDR); \ + if (len >= addrlen) { \ + u32_t l; \ + PUTCHAR(opt, ucp); \ + PUTCHAR(addrlen, ucp); \ + l = ntohl(val1); \ + PUTLONG(l, ucp); \ + if (old) { \ + l = ntohl(val2); \ + PUTLONG(l, ucp); \ + } \ + len -= addrlen; \ + } else \ + neg = 0; \ + } + +#define ADDCIDNS(opt, neg, addr) \ + if (neg) { \ + if (len >= CILEN_ADDR) { \ + u32_t l; \ + PUTCHAR(opt, ucp); \ + PUTCHAR(CILEN_ADDR, ucp); \ + l = ntohl(addr); \ + PUTLONG(l, ucp); \ + len -= CILEN_ADDR; \ + } else \ + neg = 0; \ + } + + ADDCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), go->neg_addr, + go->old_addrs, go->ouraddr, go->hisaddr); + + ADDCIVJ(CI_COMPRESSTYPE, go->neg_vj, go->vj_protocol, go->old_vj, + go->maxslotindex, go->cflag); + + ADDCIDNS(CI_MS_DNS1, go->req_dns1, go->dnsaddr[0]); + + ADDCIDNS(CI_MS_DNS2, go->req_dns2, go->dnsaddr[1]); + + *lenp -= len; +} + + +/* + * ipcp_ackci - Ack our CIs. + * + * Returns: + * 0 - Ack was bad. + * 1 - Ack was good. + */ +static int ipcp_ackci(fsm *f, u_char *p, int len) +{ + ipcp_options *go = &ipcp_gotoptions[f->unit]; + u_short cilen, citype, cishort; + u32_t cilong; + u_char cimaxslotindex, cicflag; + + /* + * CIs must be in exactly the same order that we sent... + * Check packet length and CI length at each step. + * If we find any deviations, then this packet is bad. + */ + +#define ACKCIVJ(opt, neg, val, old, maxslotindex, cflag) \ + if (neg) { \ + int vjlen = old? CILEN_COMPRESS : CILEN_VJ; \ + if ((len -= vjlen) < 0) \ + goto bad; \ + GETCHAR(citype, p); \ + GETCHAR(cilen, p); \ + if (cilen != vjlen || \ + citype != opt) \ + goto bad; \ + GETSHORT(cishort, p); \ + if (cishort != val) \ + goto bad; \ + if (!old) { \ + GETCHAR(cimaxslotindex, p); \ + if (cimaxslotindex != maxslotindex) \ + goto bad; \ + GETCHAR(cicflag, p); \ + if (cicflag != cflag) \ + goto bad; \ + } \ + } + +#define ACKCIADDR(opt, neg, old, val1, val2) \ + if (neg) { \ + int addrlen = (old? CILEN_ADDRS: CILEN_ADDR); \ + u32_t l; \ + if ((len -= addrlen) < 0) \ + goto bad; \ + GETCHAR(citype, p); \ + GETCHAR(cilen, p); \ + if (cilen != addrlen || \ + citype != opt) \ + goto bad; \ + GETLONG(l, p); \ + cilong = htonl(l); \ + if (val1 != cilong) \ + goto bad; \ + if (old) { \ + GETLONG(l, p); \ + cilong = htonl(l); \ + if (val2 != cilong) \ + goto bad; \ + } \ + } + +#define ACKCIDNS(opt, neg, addr) \ + if (neg) { \ + u32_t l; \ + if ((len -= CILEN_ADDR) < 0) \ + goto bad; \ + GETCHAR(citype, p); \ + GETCHAR(cilen, p); \ + if (cilen != CILEN_ADDR || \ + citype != opt) \ + goto bad; \ + GETLONG(l, p); \ + cilong = htonl(l); \ + if (addr != cilong) \ + goto bad; \ + } + + ACKCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), go->neg_addr, + go->old_addrs, go->ouraddr, go->hisaddr); + + ACKCIVJ(CI_COMPRESSTYPE, go->neg_vj, go->vj_protocol, go->old_vj, + go->maxslotindex, go->cflag); + + ACKCIDNS(CI_MS_DNS1, go->req_dns1, go->dnsaddr[0]); + + ACKCIDNS(CI_MS_DNS2, go->req_dns2, go->dnsaddr[1]); + + /* + * If there are any remaining CIs, then this packet is bad. + */ + if (len != 0) + goto bad; + return (1); + +bad: + IPCPDEBUG((LOG_INFO, "ipcp_ackci: received bad Ack!\n")); + return (0); +} + +/* + * ipcp_nakci - Peer has sent a NAK for some of our CIs. + * This should not modify any state if the Nak is bad + * or if IPCP is in the OPENED state. + * + * Returns: + * 0 - Nak was bad. + * 1 - Nak was good. + */ +static int ipcp_nakci(fsm *f, u_char *p, int len) +{ + ipcp_options *go = &ipcp_gotoptions[f->unit]; + u_char cimaxslotindex, cicflag; + u_char citype, cilen, *next; + u_short cishort; + u32_t ciaddr1, ciaddr2, l, cidnsaddr; + ipcp_options no; /* options we've seen Naks for */ + ipcp_options try; /* options to request next time */ + + BZERO(&no, sizeof(no)); + try = *go; + + /* + * Any Nak'd CIs must be in exactly the same order that we sent. + * Check packet length and CI length at each step. + * If we find any deviations, then this packet is bad. + */ +#define NAKCIADDR(opt, neg, old, code) \ + if (go->neg && \ + len >= (cilen = (old? CILEN_ADDRS: CILEN_ADDR)) && \ + p[1] == cilen && \ + p[0] == opt) { \ + len -= cilen; \ + INCPTR(2, p); \ + GETLONG(l, p); \ + ciaddr1 = htonl(l); \ + if (old) { \ + GETLONG(l, p); \ + ciaddr2 = htonl(l); \ + no.old_addrs = 1; \ + } else \ + ciaddr2 = 0; \ + no.neg = 1; \ + code \ + } + +#define NAKCIVJ(opt, neg, code) \ + if (go->neg && \ + ((cilen = p[1]) == CILEN_COMPRESS || cilen == CILEN_VJ) && \ + len >= cilen && \ + p[0] == opt) { \ + len -= cilen; \ + INCPTR(2, p); \ + GETSHORT(cishort, p); \ + no.neg = 1; \ + code \ + } + +#define NAKCIDNS(opt, neg, code) \ + if (go->neg && \ + ((cilen = p[1]) == CILEN_ADDR) && \ + len >= cilen && \ + p[0] == opt) { \ + len -= cilen; \ + INCPTR(2, p); \ + GETLONG(l, p); \ + cidnsaddr = htonl(l); \ + no.neg = 1; \ + code \ + } + + /* + * Accept the peer's idea of {our,his} address, if different + * from our idea, only if the accept_{local,remote} flag is set. + */ + NAKCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), neg_addr, go->old_addrs, + if (go->accept_local && ciaddr1) { /* Do we know our address? */ + try.ouraddr = ciaddr1; + IPCPDEBUG((LOG_INFO, "local IP address %s\n", + inet_ntoa(ciaddr1))); + } + if (go->accept_remote && ciaddr2) { /* Does he know his? */ + try.hisaddr = ciaddr2; + IPCPDEBUG((LOG_INFO, "remote IP address %s\n", + inet_ntoa(ciaddr2))); + } + ); + + /* + * Accept the peer's value of maxslotindex provided that it + * is less than what we asked for. Turn off slot-ID compression + * if the peer wants. Send old-style compress-type option if + * the peer wants. + */ + NAKCIVJ(CI_COMPRESSTYPE, neg_vj, + if (cilen == CILEN_VJ) { + GETCHAR(cimaxslotindex, p); + GETCHAR(cicflag, p); + if (cishort == IPCP_VJ_COMP) { + try.old_vj = 0; + if (cimaxslotindex < go->maxslotindex) + try.maxslotindex = cimaxslotindex; + if (!cicflag) + try.cflag = 0; + } else { + try.neg_vj = 0; + } + } else { + if (cishort == IPCP_VJ_COMP || cishort == IPCP_VJ_COMP_OLD) { + try.old_vj = 1; + try.vj_protocol = cishort; + } else { + try.neg_vj = 0; + } + } + ); + + NAKCIDNS(CI_MS_DNS1, req_dns1, + try.dnsaddr[0] = cidnsaddr; + IPCPDEBUG((LOG_INFO, "primary DNS address %s\n", inet_ntoa(cidnsaddr))); + ); + + NAKCIDNS(CI_MS_DNS2, req_dns2, + try.dnsaddr[1] = cidnsaddr; + IPCPDEBUG((LOG_INFO, "secondary DNS address %s\n", inet_ntoa(cidnsaddr))); + ); + + /* + * There may be remaining CIs, if the peer is requesting negotiation + * on an option that we didn't include in our request packet. + * If they want to negotiate about IP addresses, we comply. + * If they want us to ask for compression, we refuse. + */ + while (len > CILEN_VOID) { + GETCHAR(citype, p); + GETCHAR(cilen, p); + if( (len -= cilen) < 0 ) + goto bad; + next = p + cilen - 2; + + switch (citype) { + case CI_COMPRESSTYPE: + if (go->neg_vj || no.neg_vj || + (cilen != CILEN_VJ && cilen != CILEN_COMPRESS)) + goto bad; + no.neg_vj = 1; + break; + case CI_ADDRS: + if ((go->neg_addr && go->old_addrs) || no.old_addrs + || cilen != CILEN_ADDRS) + goto bad; + try.neg_addr = 1; + try.old_addrs = 1; + GETLONG(l, p); + ciaddr1 = htonl(l); + if (ciaddr1 && go->accept_local) + try.ouraddr = ciaddr1; + GETLONG(l, p); + ciaddr2 = htonl(l); + if (ciaddr2 && go->accept_remote) + try.hisaddr = ciaddr2; + no.old_addrs = 1; + break; + case CI_ADDR: + if (go->neg_addr || no.neg_addr || cilen != CILEN_ADDR) + goto bad; + try.old_addrs = 0; + GETLONG(l, p); + ciaddr1 = htonl(l); + if (ciaddr1 && go->accept_local) + try.ouraddr = ciaddr1; + if (try.ouraddr != 0) + try.neg_addr = 1; + no.neg_addr = 1; + break; + } + p = next; + } + + /* If there is still anything left, this packet is bad. */ + if (len != 0) + goto bad; + + /* + * OK, the Nak is good. Now we can update state. + */ + if (f->state != OPENED) + *go = try; + + return 1; + +bad: + IPCPDEBUG((LOG_INFO, "ipcp_nakci: received bad Nak!\n")); + return 0; +} + + +/* + * ipcp_rejci - Reject some of our CIs. + */ +static int ipcp_rejci(fsm *f, u_char *p, int len) +{ + ipcp_options *go = &ipcp_gotoptions[f->unit]; + u_char cimaxslotindex, ciflag, cilen; + u_short cishort; + u32_t cilong; + ipcp_options try; /* options to request next time */ + + try = *go; + /* + * Any Rejected CIs must be in exactly the same order that we sent. + * Check packet length and CI length at each step. + * If we find any deviations, then this packet is bad. + */ +#define REJCIADDR(opt, neg, old, val1, val2) \ + if (go->neg && \ + len >= (cilen = old? CILEN_ADDRS: CILEN_ADDR) && \ + p[1] == cilen && \ + p[0] == opt) { \ + u32_t l; \ + len -= cilen; \ + INCPTR(2, p); \ + GETLONG(l, p); \ + cilong = htonl(l); \ + /* Check rejected value. */ \ + if (cilong != val1) \ + goto bad; \ + if (old) { \ + GETLONG(l, p); \ + cilong = htonl(l); \ + /* Check rejected value. */ \ + if (cilong != val2) \ + goto bad; \ + } \ + try.neg = 0; \ + } + +#define REJCIVJ(opt, neg, val, old, maxslot, cflag) \ + if (go->neg && \ + p[1] == (old? CILEN_COMPRESS : CILEN_VJ) && \ + len >= p[1] && \ + p[0] == opt) { \ + len -= p[1]; \ + INCPTR(2, p); \ + GETSHORT(cishort, p); \ + /* Check rejected value. */ \ + if (cishort != val) \ + goto bad; \ + if (!old) { \ + GETCHAR(cimaxslotindex, p); \ + if (cimaxslotindex != maxslot) \ + goto bad; \ + GETCHAR(ciflag, p); \ + if (ciflag != cflag) \ + goto bad; \ + } \ + try.neg = 0; \ + } + +#define REJCIDNS(opt, neg, dnsaddr) \ + if (go->neg && \ + ((cilen = p[1]) == CILEN_ADDR) && \ + len >= cilen && \ + p[0] == opt) { \ + u32_t l; \ + len -= cilen; \ + INCPTR(2, p); \ + GETLONG(l, p); \ + cilong = htonl(l); \ + /* Check rejected value. */ \ + if (cilong != dnsaddr) \ + goto bad; \ + try.neg = 0; \ + } + + REJCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), neg_addr, + go->old_addrs, go->ouraddr, go->hisaddr); + + REJCIVJ(CI_COMPRESSTYPE, neg_vj, go->vj_protocol, go->old_vj, + go->maxslotindex, go->cflag); + + REJCIDNS(CI_MS_DNS1, req_dns1, go->dnsaddr[0]); + + REJCIDNS(CI_MS_DNS2, req_dns2, go->dnsaddr[1]); + + /* + * If there are any remaining CIs, then this packet is bad. + */ + if (len != 0) + goto bad; + /* + * Now we can update state. + */ + if (f->state != OPENED) + *go = try; + return 1; + +bad: + IPCPDEBUG((LOG_INFO, "ipcp_rejci: received bad Reject!\n")); + return 0; +} + + +/* + * ipcp_reqci - Check the peer's requested CIs and send appropriate response. + * + * Returns: CONFACK, CONFNAK or CONFREJ and input packet modified + * appropriately. If reject_if_disagree is non-zero, doesn't return + * CONFNAK; returns CONFREJ if it can't return CONFACK. + */ +static int ipcp_reqci( + fsm *f, + u_char *inp, /* Requested CIs */ + int *len, /* Length of requested CIs */ + int reject_if_disagree +) +{ + ipcp_options *wo = &ipcp_wantoptions[f->unit]; + ipcp_options *ho = &ipcp_hisoptions[f->unit]; + ipcp_options *ao = &ipcp_allowoptions[f->unit]; +#ifdef OLD_CI_ADDRS + ipcp_options *go = &ipcp_gotoptions[f->unit]; +#endif + u_char *cip, *next; /* Pointer to current and next CIs */ + u_short cilen, citype; /* Parsed len, type */ + u_short cishort; /* Parsed short value */ + u32_t tl, ciaddr1; /* Parsed address values */ +#ifdef OLD_CI_ADDRS + u32_t ciaddr2; /* Parsed address values */ +#endif + int rc = CONFACK; /* Final packet return code */ + int orc; /* Individual option return code */ + u_char *p; /* Pointer to next char to parse */ + u_char *ucp = inp; /* Pointer to current output char */ + int l = *len; /* Length left */ + u_char maxslotindex, cflag; + int d; + + cis_received[f->unit] = 1; + + /* + * Reset all his options. + */ + BZERO(ho, sizeof(*ho)); + + /* + * Process all his options. + */ + next = inp; + while (l) { + orc = CONFACK; /* Assume success */ + cip = p = next; /* Remember begining of CI */ + if (l < 2 || /* Not enough data for CI header or */ + p[1] < 2 || /* CI length too small or */ + p[1] > l) { /* CI length too big? */ + IPCPDEBUG((LOG_INFO, "ipcp_reqci: bad CI length!\n")); + orc = CONFREJ; /* Reject bad CI */ + cilen = l; /* Reject till end of packet */ + l = 0; /* Don't loop again */ + goto endswitch; + } + GETCHAR(citype, p); /* Parse CI type */ + GETCHAR(cilen, p); /* Parse CI length */ + l -= cilen; /* Adjust remaining length */ + next += cilen; /* Step to next CI */ + + switch (citype) { /* Check CI type */ +#ifdef OLD_CI_ADDRS /* Need to save space... */ + case CI_ADDRS: + IPCPDEBUG((LOG_INFO, "ipcp_reqci: received ADDRS\n")); + if (!ao->neg_addr || + cilen != CILEN_ADDRS) { /* Check CI length */ + orc = CONFREJ; /* Reject CI */ + break; + } + + /* + * If he has no address, or if we both have his address but + * disagree about it, then NAK it with our idea. + * In particular, if we don't know his address, but he does, + * then accept it. + */ + GETLONG(tl, p); /* Parse source address (his) */ + ciaddr1 = htonl(tl); + IPCPDEBUG((LOG_INFO, "his addr %s\n", inet_ntoa(ciaddr1))); + if (ciaddr1 != wo->hisaddr + && (ciaddr1 == 0 || !wo->accept_remote)) { + orc = CONFNAK; + if (!reject_if_disagree) { + DECPTR(sizeof(u32_t), p); + tl = ntohl(wo->hisaddr); + PUTLONG(tl, p); + } + } else if (ciaddr1 == 0 && wo->hisaddr == 0) { + /* + * If neither we nor he knows his address, reject the option. + */ + orc = CONFREJ; + wo->req_addr = 0; /* don't NAK with 0.0.0.0 later */ + break; + } + + /* + * If he doesn't know our address, or if we both have our address + * but disagree about it, then NAK it with our idea. + */ + GETLONG(tl, p); /* Parse desination address (ours) */ + ciaddr2 = htonl(tl); + IPCPDEBUG((LOG_INFO, "our addr %s\n", inet_ntoa(ciaddr2))); + if (ciaddr2 != wo->ouraddr) { + if (ciaddr2 == 0 || !wo->accept_local) { + orc = CONFNAK; + if (!reject_if_disagree) { + DECPTR(sizeof(u32_t), p); + tl = ntohl(wo->ouraddr); + PUTLONG(tl, p); + } + } else { + go->ouraddr = ciaddr2; /* accept peer's idea */ + } + } + + ho->neg_addr = 1; + ho->old_addrs = 1; + ho->hisaddr = ciaddr1; + ho->ouraddr = ciaddr2; + break; +#endif + + case CI_ADDR: + if (!ao->neg_addr) { + IPCPDEBUG((LOG_INFO, "ipcp_reqci: Reject ADDR not allowed\n")); + orc = CONFREJ; /* Reject CI */ + break; + } else if (cilen != CILEN_ADDR) { /* Check CI length */ + IPCPDEBUG((LOG_INFO, "ipcp_reqci: Reject ADDR bad len\n")); + orc = CONFREJ; /* Reject CI */ + break; + } + + /* + * If he has no address, or if we both have his address but + * disagree about it, then NAK it with our idea. + * In particular, if we don't know his address, but he does, + * then accept it. + */ + GETLONG(tl, p); /* Parse source address (his) */ + ciaddr1 = htonl(tl); + if (ciaddr1 != wo->hisaddr + && (ciaddr1 == 0 || !wo->accept_remote)) { + orc = CONFNAK; + if (!reject_if_disagree) { + DECPTR(sizeof(u32_t), p); + tl = ntohl(wo->hisaddr); + PUTLONG(tl, p); + } + IPCPDEBUG((LOG_INFO, "ipcp_reqci: Nak ADDR %s\n", inet_ntoa(ciaddr1))); + } else if (ciaddr1 == 0 && wo->hisaddr == 0) { + /* + * Don't ACK an address of 0.0.0.0 - reject it instead. + */ + IPCPDEBUG((LOG_INFO, "ipcp_reqci: Reject ADDR %s\n", inet_ntoa(ciaddr1))); + orc = CONFREJ; + wo->req_addr = 0; /* don't NAK with 0.0.0.0 later */ + break; + } + + ho->neg_addr = 1; + ho->hisaddr = ciaddr1; + IPCPDEBUG((LOG_INFO, "ipcp_reqci: ADDR %s\n", inet_ntoa(ciaddr1))); + break; + + case CI_MS_DNS1: + case CI_MS_DNS2: + /* Microsoft primary or secondary DNS request */ + d = citype == CI_MS_DNS2; + + /* If we do not have a DNS address then we cannot send it */ + if (ao->dnsaddr[d] == 0 || + cilen != CILEN_ADDR) { /* Check CI length */ + IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting DNS%d Request\n", d+1)); + orc = CONFREJ; /* Reject CI */ + break; + } + GETLONG(tl, p); + if (htonl(tl) != ao->dnsaddr[d]) { + IPCPDEBUG((LOG_INFO, "ipcp_reqci: Naking DNS%d Request %d\n", + d+1, inet_ntoa(tl))); + DECPTR(sizeof(u32_t), p); + tl = ntohl(ao->dnsaddr[d]); + PUTLONG(tl, p); + orc = CONFNAK; + } + IPCPDEBUG((LOG_INFO, "ipcp_reqci: received DNS%d Request\n", d+1)); + break; + + case CI_MS_WINS1: + case CI_MS_WINS2: + /* Microsoft primary or secondary WINS request */ + d = citype == CI_MS_WINS2; + IPCPDEBUG((LOG_INFO, "ipcp_reqci: received WINS%d Request\n", d+1)); + + /* If we do not have a DNS address then we cannot send it */ + if (ao->winsaddr[d] == 0 || + cilen != CILEN_ADDR) { /* Check CI length */ + orc = CONFREJ; /* Reject CI */ + break; + } + GETLONG(tl, p); + if (htonl(tl) != ao->winsaddr[d]) { + DECPTR(sizeof(u32_t), p); + tl = ntohl(ao->winsaddr[d]); + PUTLONG(tl, p); + orc = CONFNAK; + } + break; + + case CI_COMPRESSTYPE: + if (!ao->neg_vj) { + IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting COMPRESSTYPE not allowed\n")); + orc = CONFREJ; + break; + } else if (cilen != CILEN_VJ && cilen != CILEN_COMPRESS) { + IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting COMPRESSTYPE len=%d\n", cilen)); + orc = CONFREJ; + break; + } + GETSHORT(cishort, p); + + if (!(cishort == IPCP_VJ_COMP || + (cishort == IPCP_VJ_COMP_OLD && cilen == CILEN_COMPRESS))) { + IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting COMPRESSTYPE %d\n", cishort)); + orc = CONFREJ; + break; + } + + ho->neg_vj = 1; + ho->vj_protocol = cishort; + if (cilen == CILEN_VJ) { + GETCHAR(maxslotindex, p); + if (maxslotindex > ao->maxslotindex) { + IPCPDEBUG((LOG_INFO, "ipcp_reqci: Naking VJ max slot %d\n", maxslotindex)); + orc = CONFNAK; + if (!reject_if_disagree){ + DECPTR(1, p); + PUTCHAR(ao->maxslotindex, p); + } + } + GETCHAR(cflag, p); + if (cflag && !ao->cflag) { + IPCPDEBUG((LOG_INFO, "ipcp_reqci: Naking VJ cflag %d\n", cflag)); + orc = CONFNAK; + if (!reject_if_disagree){ + DECPTR(1, p); + PUTCHAR(wo->cflag, p); + } + } + ho->maxslotindex = maxslotindex; + ho->cflag = cflag; + } else { + ho->old_vj = 1; + ho->maxslotindex = MAX_SLOTS - 1; + ho->cflag = 1; + } + IPCPDEBUG((LOG_INFO, + "ipcp_reqci: received COMPRESSTYPE p=%d old=%d maxslot=%d cflag=%d\n", + ho->vj_protocol, ho->old_vj, ho->maxslotindex, ho->cflag)); + break; + + default: + IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting unknown CI type %d\n", citype)); + orc = CONFREJ; + break; + } + +endswitch: + if (orc == CONFACK && /* Good CI */ + rc != CONFACK) /* but prior CI wasnt? */ + continue; /* Don't send this one */ + + if (orc == CONFNAK) { /* Nak this CI? */ + if (reject_if_disagree) { /* Getting fed up with sending NAKs? */ + IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting too many naks\n")); + orc = CONFREJ; /* Get tough if so */ + } else { + if (rc == CONFREJ) /* Rejecting prior CI? */ + continue; /* Don't send this one */ + if (rc == CONFACK) { /* Ack'd all prior CIs? */ + rc = CONFNAK; /* Not anymore... */ + ucp = inp; /* Backup */ + } + } + } + + if (orc == CONFREJ && /* Reject this CI */ + rc != CONFREJ) { /* but no prior ones? */ + rc = CONFREJ; + ucp = inp; /* Backup */ + } + + /* Need to move CI? */ + if (ucp != cip) + BCOPY(cip, ucp, cilen); /* Move it */ + + /* Update output pointer */ + INCPTR(cilen, ucp); + } + + /* + * If we aren't rejecting this packet, and we want to negotiate + * their address, and they didn't send their address, then we + * send a NAK with a CI_ADDR option appended. We assume the + * input buffer is long enough that we can append the extra + * option safely. + */ + if (rc != CONFREJ && !ho->neg_addr && + wo->req_addr && !reject_if_disagree) { + IPCPDEBUG((LOG_INFO, "ipcp_reqci: Requesting peer address\n")); + if (rc == CONFACK) { + rc = CONFNAK; + ucp = inp; /* reset pointer */ + wo->req_addr = 0; /* don't ask again */ + } + PUTCHAR(CI_ADDR, ucp); + PUTCHAR(CILEN_ADDR, ucp); + tl = ntohl(wo->hisaddr); + PUTLONG(tl, ucp); + } + + *len = (int)(ucp - inp); /* Compute output length */ + IPCPDEBUG((LOG_INFO, "ipcp_reqci: returning Configure-%s\n", CODENAME(rc))); + return (rc); /* Return final code */ +} + + +#if 0 +/* + * ip_check_options - check that any IP-related options are OK, + * and assign appropriate defaults. + */ +static void ip_check_options(u_long localAddr) +{ + ipcp_options *wo = &ipcp_wantoptions[0]; + + /* + * Load our default IP address but allow the remote host to give us + * a new address. + */ + if (wo->ouraddr == 0 && !ppp_settings.disable_defaultip) { + wo->accept_local = 1; /* don't insist on this default value */ + wo->ouraddr = htonl(localAddr); + } +} +#endif + + +/* + * ipcp_up - IPCP has come UP. + * + * Configure the IP network interface appropriately and bring it up. + */ +static void ipcp_up(fsm *f) +{ + u32_t mask; + ipcp_options *ho = &ipcp_hisoptions[f->unit]; + ipcp_options *go = &ipcp_gotoptions[f->unit]; + ipcp_options *wo = &ipcp_wantoptions[f->unit]; + + np_up(f->unit, PPP_IP); + IPCPDEBUG((LOG_INFO, "ipcp: up\n")); + + /* + * We must have a non-zero IP address for both ends of the link. + */ + if (!ho->neg_addr) + ho->hisaddr = wo->hisaddr; + + if (ho->hisaddr == 0) { + IPCPDEBUG((LOG_ERR, "Could not determine remote IP address\n")); + ipcp_close(f->unit, "Could not determine remote IP address"); + return; + } + if (go->ouraddr == 0) { + IPCPDEBUG((LOG_ERR, "Could not determine local IP address\n")); + ipcp_close(f->unit, "Could not determine local IP address"); + return; + } + + if (ppp_settings.usepeerdns && (go->dnsaddr[0] || go->dnsaddr[1])) { + /*pppGotDNSAddrs(go->dnsaddr[0], go->dnsaddr[1]);*/ + } + + /* + * Check that the peer is allowed to use the IP address it wants. + */ + if (!auth_ip_addr(f->unit, ho->hisaddr)) { + IPCPDEBUG((LOG_ERR, "Peer is not authorized to use remote address %s\n", + inet_ntoa(ho->hisaddr))); + ipcp_close(f->unit, "Unauthorized remote IP address"); + return; + } + + /* set tcp compression */ + sifvjcomp(f->unit, ho->neg_vj, ho->cflag, ho->maxslotindex); + + /* + * Set IP addresses and (if specified) netmask. + */ + mask = GetMask(go->ouraddr); + + if (!sifaddr(f->unit, go->ouraddr, ho->hisaddr, mask, go->dnsaddr[0], go->dnsaddr[1])) { + IPCPDEBUG((LOG_WARNING, "sifaddr failed\n")); + ipcp_close(f->unit, "Interface configuration failed"); + return; + } + + /* bring the interface up for IP */ + if (!sifup(f->unit)) { + IPCPDEBUG((LOG_WARNING, "sifup failed\n")); + ipcp_close(f->unit, "Interface configuration failed"); + return; + } + + sifnpmode(f->unit, PPP_IP, NPMODE_PASS); + + /* assign a default route through the interface if required */ + if (ipcp_wantoptions[f->unit].default_route) + if (sifdefaultroute(f->unit, go->ouraddr, ho->hisaddr)) + default_route_set[f->unit] = 1; + + IPCPDEBUG((LOG_NOTICE, "local IP address %s\n", inet_ntoa(go->ouraddr))); + IPCPDEBUG((LOG_NOTICE, "remote IP address %s\n", inet_ntoa(ho->hisaddr))); + if (go->dnsaddr[0]) { + IPCPDEBUG((LOG_NOTICE, "primary DNS address %s\n", inet_ntoa(go->dnsaddr[0]))); + } + if (go->dnsaddr[1]) { + IPCPDEBUG((LOG_NOTICE, "secondary DNS address %s\n", inet_ntoa(go->dnsaddr[1]))); + } +} + + +/* + * ipcp_down - IPCP has gone DOWN. + * + * Take the IP network interface down, clear its addresses + * and delete routes through it. + */ +static void ipcp_down(fsm *f) +{ + IPCPDEBUG((LOG_INFO, "ipcp: down\n")); + np_down(f->unit, PPP_IP); + sifvjcomp(f->unit, 0, 0, 0); + + sifdown(f->unit); + ipcp_clear_addrs(f->unit); +} + + +/* + * ipcp_clear_addrs() - clear the interface addresses, routes, etc. + */ +static void ipcp_clear_addrs(int unit) +{ + u32_t ouraddr, hisaddr; + + ouraddr = ipcp_gotoptions[unit].ouraddr; + hisaddr = ipcp_hisoptions[unit].hisaddr; + if (default_route_set[unit]) { + cifdefaultroute(unit, ouraddr, hisaddr); + default_route_set[unit] = 0; + } + cifaddr(unit, ouraddr, hisaddr); +} + + +/* + * ipcp_finished - possibly shut down the lower layers. + */ +static void ipcp_finished(fsm *f) +{ + np_finished(f->unit, PPP_IP); +} + +#if 0 +static int ipcp_printpkt( + u_char *p, + int plen, + void (*printer) (void *, char *, ...), + void *arg +) +{ + (void)p; + (void)plen; + (void)printer; + (void)arg; + return 0; +} + +/* + * ip_active_pkt - see if this IP packet is worth bringing the link up for. + * We don't bring the link up for IP fragments or for TCP FIN packets + * with no data. + */ +#define IP_HDRLEN 20 /* bytes */ +#define IP_OFFMASK 0x1fff +#define IPPROTO_TCP 6 +#define TCP_HDRLEN 20 +#define TH_FIN 0x01 + +/* + * We use these macros because the IP header may be at an odd address, + * and some compilers might use word loads to get th_off or ip_hl. + */ + +#define net_short(x) (((x)[0] << 8) + (x)[1]) +#define get_iphl(x) (((unsigned char *)(x))[0] & 0xF) +#define get_ipoff(x) net_short((unsigned char *)(x) + 6) +#define get_ipproto(x) (((unsigned char *)(x))[9]) +#define get_tcpoff(x) (((unsigned char *)(x))[12] >> 4) +#define get_tcpflags(x) (((unsigned char *)(x))[13]) + +static int ip_active_pkt(u_char *pkt, int len) +{ + u_char *tcp; + int hlen; + + len -= PPP_HDRLEN; + pkt += PPP_HDRLEN; + if (len < IP_HDRLEN) + return 0; + if ((get_ipoff(pkt) & IP_OFFMASK) != 0) + return 0; + if (get_ipproto(pkt) != IPPROTO_TCP) + return 1; + hlen = get_iphl(pkt) * 4; + if (len < hlen + TCP_HDRLEN) + return 0; + tcp = pkt + hlen; + if ((get_tcpflags(tcp) & TH_FIN) != 0 && len == hlen + get_tcpoff(tcp) * 4) + return 0; + return 1; +} +#endif + +#endif /* PPP_SUPPORT */ diff --git a/20080212/Demo/Common/ethernet/lwIP/netif/ppp/ipcp.h b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/ipcp.h new file mode 100644 index 000000000..28fc36ed8 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/ipcp.h @@ -0,0 +1,126 @@ +/***************************************************************************** +* ipcp.h - PPP IP NCP: Internet Protocol Network Control Protocol header file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1997 Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-12-04 Guy Lancaster , Global Election Systems Inc. +* Original derived from BSD codes. +*****************************************************************************/ +/* + * ipcp.h - IP Control Protocol definitions. + * + * Copyright (c) 1989 Carnegie Mellon University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Carnegie Mellon University. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * $Id: ipcp.h,v 1.1 2003/05/27 14:37:56 jani Exp $ + */ + +#ifndef IPCP_H +#define IPCP_H + +/************************* +*** PUBLIC DEFINITIONS *** +*************************/ +/* + * Options. + */ +#define CI_ADDRS 1 /* IP Addresses */ +#define CI_COMPRESSTYPE 2 /* Compression Type */ +#define CI_ADDR 3 + +#define CI_MS_WINS1 128 /* Primary WINS value */ +#define CI_MS_DNS1 129 /* Primary DNS value */ +#define CI_MS_WINS2 130 /* Secondary WINS value */ +#define CI_MS_DNS2 131 /* Secondary DNS value */ + +#define IPCP_VJMODE_OLD 1 /* "old" mode (option # = 0x0037) */ +#define IPCP_VJMODE_RFC1172 2 /* "old-rfc"mode (option # = 0x002d) */ +#define IPCP_VJMODE_RFC1332 3 /* "new-rfc"mode (option # = 0x002d, */ + /* maxslot and slot number compression) */ + +#define IPCP_VJ_COMP 0x002d /* current value for VJ compression option*/ +#define IPCP_VJ_COMP_OLD 0x0037 /* "old" (i.e, broken) value for VJ */ + /* compression option*/ + + +/************************ +*** PUBLIC DATA TYPES *** +************************/ + +typedef struct ipcp_options { + u_int neg_addr : 1; /* Negotiate IP Address? */ + u_int old_addrs : 1; /* Use old (IP-Addresses) option? */ + u_int req_addr : 1; /* Ask peer to send IP address? */ + u_int default_route : 1; /* Assign default route through interface? */ + u_int proxy_arp : 1; /* Make proxy ARP entry for peer? */ + u_int neg_vj : 1; /* Van Jacobson Compression? */ + u_int old_vj : 1; /* use old (short) form of VJ option? */ + u_int accept_local : 1; /* accept peer's value for ouraddr */ + u_int accept_remote : 1; /* accept peer's value for hisaddr */ + u_int req_dns1 : 1; /* Ask peer to send primary DNS address? */ + u_int req_dns2 : 1; /* Ask peer to send secondary DNS address? */ + u_short vj_protocol; /* protocol value to use in VJ option */ + u_char maxslotindex; /* VJ slots - 1. */ + u_char cflag; /* VJ slot compression flag. */ + u32_t ouraddr, hisaddr; /* Addresses in NETWORK BYTE ORDER */ + u32_t dnsaddr[2]; /* Primary and secondary MS DNS entries */ + u32_t winsaddr[2]; /* Primary and secondary MS WINS entries */ +} ipcp_options; + + +/***************************** +*** PUBLIC DATA STRUCTURES *** +*****************************/ + +extern fsm ipcp_fsm[]; +extern ipcp_options ipcp_wantoptions[]; +extern ipcp_options ipcp_gotoptions[]; +extern ipcp_options ipcp_allowoptions[]; +extern ipcp_options ipcp_hisoptions[]; + +extern struct protent ipcp_protent; + + +/*********************** +*** PUBLIC FUNCTIONS *** +***********************/ + + +#endif /* IPCP_H */ + diff --git a/20080212/Demo/Common/ethernet/lwIP/netif/ppp/lcp.c b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/lcp.c new file mode 100644 index 000000000..41dbc5dd2 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/lcp.c @@ -0,0 +1,1991 @@ +/***************************************************************************** +* lcp.c - Network Link Control Protocol program file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1997 by Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-12-01 Guy Lancaster , Global Election Systems Inc. +* Original. +*****************************************************************************/ + +/* + * lcp.c - PPP Link Control Protocol. + * + * Copyright (c) 1989 Carnegie Mellon University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Carnegie Mellon University. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +#include + +#include "ppp.h" +#if PPP_SUPPORT > 0 +#include "fsm.h" +#include "chap.h" +#include "magic.h" +#include "auth.h" +#include "lcp.h" +#include "pppdebug.h" + + +/*************************/ +/*** LOCAL DEFINITIONS ***/ +/*************************/ +/* + * Length of each type of configuration option (in octets) + */ +#define CILEN_VOID 2 +#define CILEN_CHAR 3 +#define CILEN_SHORT 4 /* CILEN_VOID + sizeof(short) */ +#define CILEN_CHAP 5 /* CILEN_VOID + sizeof(short) + 1 */ +#define CILEN_LONG 6 /* CILEN_VOID + sizeof(long) */ +#define CILEN_LQR 8 /* CILEN_VOID + sizeof(short) + sizeof(long) */ +#define CILEN_CBCP 3 + + +/***********************************/ +/*** LOCAL FUNCTION DECLARATIONS ***/ +/***********************************/ +/* + * Callbacks for fsm code. (CI = Configuration Information) + */ +static void lcp_resetci (fsm*); /* Reset our CI */ +static int lcp_cilen (fsm*); /* Return length of our CI */ +static void lcp_addci (fsm*, u_char*, int*); /* Add our CI to pkt */ +static int lcp_ackci (fsm*, u_char*, int);/* Peer ack'd our CI */ +static int lcp_nakci (fsm*, u_char*, int);/* Peer nak'd our CI */ +static int lcp_rejci (fsm*, u_char*, int);/* Peer rej'd our CI */ +static int lcp_reqci (fsm*, u_char*, int*, int); /* Rcv peer CI */ +static void lcp_up (fsm*); /* We're UP */ +static void lcp_down (fsm*); /* We're DOWN */ +static void lcp_starting (fsm*); /* We need lower layer up */ +static void lcp_finished (fsm*); /* We need lower layer down */ +static int lcp_extcode (fsm*, int, u_char, u_char*, int); + +static void lcp_rprotrej (fsm*, u_char*, int); + +/* + * routines to send LCP echos to peer + */ +static void lcp_echo_lowerup (int); +static void lcp_echo_lowerdown (int); +static void LcpEchoTimeout (void*); +static void lcp_received_echo_reply (fsm*, int, u_char*, int); +static void LcpSendEchoRequest (fsm*); +static void LcpLinkFailure (fsm*); +static void LcpEchoCheck (fsm*); + +/* + * Protocol entry points. + * Some of these are called directly. + */ +static void lcp_input (int, u_char *, int); +static void lcp_protrej (int); + +#define CODENAME(x) ((x) == CONFACK ? "ACK" : \ + (x) == CONFNAK ? "NAK" : "REJ") + + +/******************************/ +/*** PUBLIC DATA STRUCTURES ***/ +/******************************/ +/* global vars */ +LinkPhase lcp_phase[NUM_PPP]; /* Phase of link session (RFC 1661) */ +lcp_options lcp_wantoptions[NUM_PPP]; /* Options that we want to request */ +lcp_options lcp_gotoptions[NUM_PPP]; /* Options that peer ack'd */ +lcp_options lcp_allowoptions[NUM_PPP]; /* Options we allow peer to request */ +lcp_options lcp_hisoptions[NUM_PPP]; /* Options that we ack'd */ +ext_accm xmit_accm[NUM_PPP]; /* extended transmit ACCM */ + + + +/*****************************/ +/*** LOCAL DATA STRUCTURES ***/ +/*****************************/ +static fsm lcp_fsm[NUM_PPP]; /* LCP fsm structure (global)*/ +static u_int lcp_echo_interval = LCP_ECHOINTERVAL; /* Interval between LCP echo-requests */ +static u_int lcp_echo_fails = LCP_MAXECHOFAILS; /* Tolerance to unanswered echo-requests */ +static u32_t lcp_echos_pending = 0; /* Number of outstanding echo msgs */ +static u32_t lcp_echo_number = 0; /* ID number of next echo frame */ +static u32_t lcp_echo_timer_running = 0; /* TRUE if a timer is running */ + +static u_char nak_buffer[PPP_MRU]; /* where we construct a nak packet */ + +static fsm_callbacks lcp_callbacks = { /* LCP callback routines */ + lcp_resetci, /* Reset our Configuration Information */ + lcp_cilen, /* Length of our Configuration Information */ + lcp_addci, /* Add our Configuration Information */ + lcp_ackci, /* ACK our Configuration Information */ + lcp_nakci, /* NAK our Configuration Information */ + lcp_rejci, /* Reject our Configuration Information */ + lcp_reqci, /* Request peer's Configuration Information */ + lcp_up, /* Called when fsm reaches OPENED state */ + lcp_down, /* Called when fsm leaves OPENED state */ + lcp_starting, /* Called when we want the lower layer up */ + lcp_finished, /* Called when we want the lower layer down */ + NULL, /* Called when Protocol-Reject received */ + NULL, /* Retransmission is necessary */ + lcp_extcode, /* Called to handle LCP-specific codes */ + "LCP" /* String name of protocol */ +}; + +struct protent lcp_protent = { + PPP_LCP, + lcp_init, + lcp_input, + lcp_protrej, + lcp_lowerup, + lcp_lowerdown, + lcp_open, + lcp_close, +#if 0 + lcp_printpkt, + NULL, +#endif + 1, + "LCP", +#if 0 + NULL, + NULL, + NULL +#endif +}; + +int lcp_loopbackfail = DEFLOOPBACKFAIL; + + + +/***********************************/ +/*** PUBLIC FUNCTION DEFINITIONS ***/ +/***********************************/ +/* + * lcp_init - Initialize LCP. + */ +void lcp_init(int unit) +{ + fsm *f = &lcp_fsm[unit]; + lcp_options *wo = &lcp_wantoptions[unit]; + lcp_options *ao = &lcp_allowoptions[unit]; + + f->unit = unit; + f->protocol = PPP_LCP; + f->callbacks = &lcp_callbacks; + + fsm_init(f); + + wo->passive = 0; + wo->silent = 0; + wo->restart = 0; /* Set to 1 in kernels or multi-line + * implementations */ + wo->neg_mru = 1; + wo->mru = PPP_DEFMRU; + wo->neg_asyncmap = 1; + wo->asyncmap = 0x00000000l; /* Assume don't need to escape any ctl chars. */ + wo->neg_chap = 0; /* Set to 1 on server */ + wo->neg_upap = 0; /* Set to 1 on server */ + wo->chap_mdtype = CHAP_DIGEST_MD5; + wo->neg_magicnumber = 1; + wo->neg_pcompression = 1; + wo->neg_accompression = 1; + wo->neg_lqr = 0; /* no LQR implementation yet */ + wo->neg_cbcp = 0; + + ao->neg_mru = 1; + ao->mru = PPP_MAXMRU; + ao->neg_asyncmap = 1; + ao->asyncmap = 0x00000000l; /* Assume don't need to escape any ctl chars. */ + ao->neg_chap = (CHAP_SUPPORT != 0); + ao->chap_mdtype = CHAP_DIGEST_MD5; + ao->neg_upap = (PAP_SUPPORT != 0); + ao->neg_magicnumber = 1; + ao->neg_pcompression = 1; + ao->neg_accompression = 1; + ao->neg_lqr = 0; /* no LQR implementation yet */ + ao->neg_cbcp = (CBCP_SUPPORT != 0); + + /* + * Set transmit escape for the flag and escape characters plus anything + * set for the allowable options. + */ + memset(xmit_accm[unit], 0, sizeof(xmit_accm[0])); + xmit_accm[unit][15] = 0x60; + xmit_accm[unit][0] = (u_char)(ao->asyncmap & 0xFF); + xmit_accm[unit][1] = (u_char)((ao->asyncmap >> 8) & 0xFF); + xmit_accm[unit][2] = (u_char)((ao->asyncmap >> 16) & 0xFF); + xmit_accm[unit][3] = (u_char)((ao->asyncmap >> 24) & 0xFF); + LCPDEBUG((LOG_INFO, "lcp_init: xmit_accm=%X %X %X %X\n", + xmit_accm[unit][0], + xmit_accm[unit][1], + xmit_accm[unit][2], + xmit_accm[unit][3])); + + lcp_phase[unit] = PHASE_INITIALIZE; +} + + +/* + * lcp_open - LCP is allowed to come up. + */ +void lcp_open(int unit) +{ + fsm *f = &lcp_fsm[unit]; + lcp_options *wo = &lcp_wantoptions[unit]; + + f->flags = 0; + if (wo->passive) + f->flags |= OPT_PASSIVE; + if (wo->silent) + f->flags |= OPT_SILENT; + fsm_open(f); + + lcp_phase[unit] = PHASE_ESTABLISH; +} + + +/* + * lcp_close - Take LCP down. + */ +void lcp_close(int unit, char *reason) +{ + fsm *f = &lcp_fsm[unit]; + + if (lcp_phase[unit] != PHASE_DEAD) + lcp_phase[unit] = PHASE_TERMINATE; + if (f->state == STOPPED && f->flags & (OPT_PASSIVE|OPT_SILENT)) { + /* + * This action is not strictly according to the FSM in RFC1548, + * but it does mean that the program terminates if you do an + * lcp_close() in passive/silent mode when a connection hasn't + * been established. + */ + f->state = CLOSED; + lcp_finished(f); + } + else + fsm_close(&lcp_fsm[unit], reason); +} + + +/* + * lcp_lowerup - The lower layer is up. + */ +void lcp_lowerup(int unit) +{ + lcp_options *wo = &lcp_wantoptions[unit]; + + /* + * Don't use A/C or protocol compression on transmission, + * but accept A/C and protocol compressed packets + * if we are going to ask for A/C and protocol compression. + */ + ppp_set_xaccm(unit, &xmit_accm[unit]); + ppp_send_config(unit, PPP_MRU, 0xffffffffl, 0, 0); + ppp_recv_config(unit, PPP_MRU, 0x00000000l, + wo->neg_pcompression, wo->neg_accompression); + peer_mru[unit] = PPP_MRU; + lcp_allowoptions[unit].asyncmap + = (u_long)xmit_accm[unit][0] + | ((u_long)xmit_accm[unit][1] << 8) + | ((u_long)xmit_accm[unit][2] << 16) + | ((u_long)xmit_accm[unit][3] << 24); + LCPDEBUG((LOG_INFO, "lcp_lowerup: asyncmap=%X %X %X %X\n", + xmit_accm[unit][3], + xmit_accm[unit][2], + xmit_accm[unit][1], + xmit_accm[unit][0])); + + fsm_lowerup(&lcp_fsm[unit]); +} + + +/* + * lcp_lowerdown - The lower layer is down. + */ +void lcp_lowerdown(int unit) +{ + fsm_lowerdown(&lcp_fsm[unit]); +} + +/* + * lcp_sprotrej - Send a Protocol-Reject for some protocol. + */ +void lcp_sprotrej(int unit, u_char *p, int len) +{ + /* + * Send back the protocol and the information field of the + * rejected packet. We only get here if LCP is in the OPENED state. + */ + + fsm_sdata(&lcp_fsm[unit], PROTREJ, ++lcp_fsm[unit].id, + p, len); +} + + + +/**********************************/ +/*** LOCAL FUNCTION DEFINITIONS ***/ +/**********************************/ +/* + * lcp_input - Input LCP packet. + */ +static void lcp_input(int unit, u_char *p, int len) +{ + fsm *f = &lcp_fsm[unit]; + + fsm_input(f, p, len); +} + + +/* + * lcp_extcode - Handle a LCP-specific code. + */ +static int lcp_extcode(fsm *f, int code, u_char id, u_char *inp, int len) +{ + u_char *magp; + + switch( code ){ + case PROTREJ: + lcp_rprotrej(f, inp, len); + break; + + case ECHOREQ: + if (f->state != OPENED) + break; + LCPDEBUG((LOG_INFO, "lcp: Echo-Request, Rcvd id %d\n", id)); + magp = inp; + PUTLONG(lcp_gotoptions[f->unit].magicnumber, magp); + fsm_sdata(f, ECHOREP, id, inp, len); + break; + + case ECHOREP: + lcp_received_echo_reply(f, id, inp, len); + break; + + case DISCREQ: + break; + + default: + return 0; + } + return 1; +} + + +/* + * lcp_rprotrej - Receive an Protocol-Reject. + * + * Figure out which protocol is rejected and inform it. + */ +static void lcp_rprotrej(fsm *f, u_char *inp, int len) +{ + int i; + struct protent *protp; + u_short prot; + + if (len < sizeof (u_short)) { + LCPDEBUG((LOG_INFO, + "lcp_rprotrej: Rcvd short Protocol-Reject packet!\n")); + return; + } + + GETSHORT(prot, inp); + + LCPDEBUG((LOG_INFO, + "lcp_rprotrej: Rcvd Protocol-Reject packet for %x!\n", + prot)); + + /* + * Protocol-Reject packets received in any state other than the LCP + * OPENED state SHOULD be silently discarded. + */ + if( f->state != OPENED ){ + LCPDEBUG((LOG_INFO, "Protocol-Reject discarded: LCP in state %d\n", + f->state)); + return; + } + + /* + * Upcall the proper Protocol-Reject routine. + */ + for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) + if (protp->protocol == prot && protp->enabled_flag) { + (*protp->protrej)(f->unit); + return; + } + + LCPDEBUG((LOG_WARNING, "Protocol-Reject for unsupported protocol 0x%x\n", + prot)); +} + + +/* + * lcp_protrej - A Protocol-Reject was received. + */ +static void lcp_protrej(int unit) +{ + (void)unit; + /* + * Can't reject LCP! + */ + LCPDEBUG((LOG_WARNING, + "lcp_protrej: Received Protocol-Reject for LCP!\n")); + fsm_protreject(&lcp_fsm[unit]); +} + + +/* + * lcp_resetci - Reset our CI. + */ +static void lcp_resetci(fsm *f) +{ + lcp_wantoptions[f->unit].magicnumber = magic(); + lcp_wantoptions[f->unit].numloops = 0; + lcp_gotoptions[f->unit] = lcp_wantoptions[f->unit]; + peer_mru[f->unit] = PPP_MRU; + auth_reset(f->unit); +} + + +/* + * lcp_cilen - Return length of our CI. + */ +static int lcp_cilen(fsm *f) +{ + lcp_options *go = &lcp_gotoptions[f->unit]; + +#define LENCIVOID(neg) ((neg) ? CILEN_VOID : 0) +#define LENCICHAP(neg) ((neg) ? CILEN_CHAP : 0) +#define LENCISHORT(neg) ((neg) ? CILEN_SHORT : 0) +#define LENCILONG(neg) ((neg) ? CILEN_LONG : 0) +#define LENCILQR(neg) ((neg) ? CILEN_LQR: 0) +#define LENCICBCP(neg) ((neg) ? CILEN_CBCP: 0) + /* + * NB: we only ask for one of CHAP and UPAP, even if we will + * accept either. + */ + return (LENCISHORT(go->neg_mru && go->mru != PPP_DEFMRU) + + LENCILONG(go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl) + + LENCICHAP(go->neg_chap) + + LENCISHORT(!go->neg_chap && go->neg_upap) + + LENCILQR(go->neg_lqr) + + LENCICBCP(go->neg_cbcp) + + LENCILONG(go->neg_magicnumber) + + LENCIVOID(go->neg_pcompression) + + LENCIVOID(go->neg_accompression)); +} + + +/* + * lcp_addci - Add our desired CIs to a packet. + */ +static void lcp_addci(fsm *f, u_char *ucp, int *lenp) +{ + lcp_options *go = &lcp_gotoptions[f->unit]; + u_char *start_ucp = ucp; + +#define ADDCIVOID(opt, neg) \ + if (neg) { \ + LCPDEBUG((LOG_INFO, "lcp_addci: opt=%d\n", opt)); \ + PUTCHAR(opt, ucp); \ + PUTCHAR(CILEN_VOID, ucp); \ + } +#define ADDCISHORT(opt, neg, val) \ + if (neg) { \ + LCPDEBUG((LOG_INFO, "lcp_addci: INT opt=%d %X\n", opt, val)); \ + PUTCHAR(opt, ucp); \ + PUTCHAR(CILEN_SHORT, ucp); \ + PUTSHORT(val, ucp); \ + } +#define ADDCICHAP(opt, neg, val, digest) \ + if (neg) { \ + LCPDEBUG((LOG_INFO, "lcp_addci: CHAP opt=%d %X\n", opt, val)); \ + PUTCHAR(opt, ucp); \ + PUTCHAR(CILEN_CHAP, ucp); \ + PUTSHORT(val, ucp); \ + PUTCHAR(digest, ucp); \ + } +#define ADDCILONG(opt, neg, val) \ + if (neg) { \ + LCPDEBUG((LOG_INFO, "lcp_addci: L opt=%d %lX\n", opt, val)); \ + PUTCHAR(opt, ucp); \ + PUTCHAR(CILEN_LONG, ucp); \ + PUTLONG(val, ucp); \ + } +#define ADDCILQR(opt, neg, val) \ + if (neg) { \ + LCPDEBUG((LOG_INFO, "lcp_addci: LQR opt=%d %lX\n", opt, val)); \ + PUTCHAR(opt, ucp); \ + PUTCHAR(CILEN_LQR, ucp); \ + PUTSHORT(PPP_LQR, ucp); \ + PUTLONG(val, ucp); \ + } +#define ADDCICHAR(opt, neg, val) \ + if (neg) { \ + LCPDEBUG((LOG_INFO, "lcp_addci: CHAR opt=%d %X '%z'\n", opt, val, val)); \ + PUTCHAR(opt, ucp); \ + PUTCHAR(CILEN_CHAR, ucp); \ + PUTCHAR(val, ucp); \ + } + + ADDCISHORT(CI_MRU, go->neg_mru && go->mru != PPP_DEFMRU, go->mru); + ADDCILONG(CI_ASYNCMAP, go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl, + go->asyncmap); + ADDCICHAP(CI_AUTHTYPE, go->neg_chap, PPP_CHAP, go->chap_mdtype); + ADDCISHORT(CI_AUTHTYPE, !go->neg_chap && go->neg_upap, PPP_PAP); + ADDCILQR(CI_QUALITY, go->neg_lqr, go->lqr_period); + ADDCICHAR(CI_CALLBACK, go->neg_cbcp, CBCP_OPT); + ADDCILONG(CI_MAGICNUMBER, go->neg_magicnumber, go->magicnumber); + ADDCIVOID(CI_PCOMPRESSION, go->neg_pcompression); + ADDCIVOID(CI_ACCOMPRESSION, go->neg_accompression); + + if (ucp - start_ucp != *lenp) { + /* this should never happen, because peer_mtu should be 1500 */ + LCPDEBUG((LOG_ERR, "Bug in lcp_addci: wrong length\n")); + } +} + + +/* + * lcp_ackci - Ack our CIs. + * This should not modify any state if the Ack is bad. + * + * Returns: + * 0 - Ack was bad. + * 1 - Ack was good. + */ +static int lcp_ackci(fsm *f, u_char *p, int len) +{ + lcp_options *go = &lcp_gotoptions[f->unit]; + u_char cilen, citype, cichar; + u_short cishort; + u32_t cilong; + + /* + * CIs must be in exactly the same order that we sent. + * Check packet length and CI length at each step. + * If we find any deviations, then this packet is bad. + */ +#define ACKCIVOID(opt, neg) \ + if (neg) { \ + if ((len -= CILEN_VOID) < 0) \ + goto bad; \ + GETCHAR(citype, p); \ + GETCHAR(cilen, p); \ + if (cilen != CILEN_VOID || \ + citype != opt) \ + goto bad; \ + } +#define ACKCISHORT(opt, neg, val) \ + if (neg) { \ + if ((len -= CILEN_SHORT) < 0) \ + goto bad; \ + GETCHAR(citype, p); \ + GETCHAR(cilen, p); \ + if (cilen != CILEN_SHORT || \ + citype != opt) \ + goto bad; \ + GETSHORT(cishort, p); \ + if (cishort != val) \ + goto bad; \ + } +#define ACKCICHAR(opt, neg, val) \ + if (neg) { \ + if ((len -= CILEN_CHAR) < 0) \ + goto bad; \ + GETCHAR(citype, p); \ + GETCHAR(cilen, p); \ + if (cilen != CILEN_CHAR || \ + citype != opt) \ + goto bad; \ + GETCHAR(cichar, p); \ + if (cichar != val) \ + goto bad; \ + } +#define ACKCICHAP(opt, neg, val, digest) \ + if (neg) { \ + if ((len -= CILEN_CHAP) < 0) \ + goto bad; \ + GETCHAR(citype, p); \ + GETCHAR(cilen, p); \ + if (cilen != CILEN_CHAP || \ + citype != opt) \ + goto bad; \ + GETSHORT(cishort, p); \ + if (cishort != val) \ + goto bad; \ + GETCHAR(cichar, p); \ + if (cichar != digest) \ + goto bad; \ + } +#define ACKCILONG(opt, neg, val) \ + if (neg) { \ + if ((len -= CILEN_LONG) < 0) \ + goto bad; \ + GETCHAR(citype, p); \ + GETCHAR(cilen, p); \ + if (cilen != CILEN_LONG || \ + citype != opt) \ + goto bad; \ + GETLONG(cilong, p); \ + if (cilong != val) \ + goto bad; \ + } +#define ACKCILQR(opt, neg, val) \ + if (neg) { \ + if ((len -= CILEN_LQR) < 0) \ + goto bad; \ + GETCHAR(citype, p); \ + GETCHAR(cilen, p); \ + if (cilen != CILEN_LQR || \ + citype != opt) \ + goto bad; \ + GETSHORT(cishort, p); \ + if (cishort != PPP_LQR) \ + goto bad; \ + GETLONG(cilong, p); \ + if (cilong != val) \ + goto bad; \ + } + + ACKCISHORT(CI_MRU, go->neg_mru && go->mru != PPP_DEFMRU, go->mru); + ACKCILONG(CI_ASYNCMAP, go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl, + go->asyncmap); + ACKCICHAP(CI_AUTHTYPE, go->neg_chap, PPP_CHAP, go->chap_mdtype); + ACKCISHORT(CI_AUTHTYPE, !go->neg_chap && go->neg_upap, PPP_PAP); + ACKCILQR(CI_QUALITY, go->neg_lqr, go->lqr_period); + ACKCICHAR(CI_CALLBACK, go->neg_cbcp, CBCP_OPT); + ACKCILONG(CI_MAGICNUMBER, go->neg_magicnumber, go->magicnumber); + ACKCIVOID(CI_PCOMPRESSION, go->neg_pcompression); + ACKCIVOID(CI_ACCOMPRESSION, go->neg_accompression); + + /* + * If there are any remaining CIs, then this packet is bad. + */ + if (len != 0) + goto bad; + LCPDEBUG((LOG_INFO, "lcp_acki: Ack\n")); + return (1); +bad: + LCPDEBUG((LOG_WARNING, "lcp_acki: received bad Ack!\n")); + return (0); +} + + +/* + * lcp_nakci - Peer has sent a NAK for some of our CIs. + * This should not modify any state if the Nak is bad + * or if LCP is in the OPENED state. + * + * Returns: + * 0 - Nak was bad. + * 1 - Nak was good. + */ +static int lcp_nakci(fsm *f, u_char *p, int len) +{ + lcp_options *go = &lcp_gotoptions[f->unit]; + lcp_options *wo = &lcp_wantoptions[f->unit]; + u_char citype, cichar, *next; + u_short cishort; + u32_t cilong; + lcp_options no; /* options we've seen Naks for */ + lcp_options try; /* options to request next time */ + int looped_back = 0; + int cilen; + + BZERO(&no, sizeof(no)); + try = *go; + + /* + * Any Nak'd CIs must be in exactly the same order that we sent. + * Check packet length and CI length at each step. + * If we find any deviations, then this packet is bad. + */ +#define NAKCIVOID(opt, neg, code) \ + if (go->neg && \ + len >= CILEN_VOID && \ + p[1] == CILEN_VOID && \ + p[0] == opt) { \ + len -= CILEN_VOID; \ + INCPTR(CILEN_VOID, p); \ + no.neg = 1; \ + code \ + } +#define NAKCICHAP(opt, neg, code) \ + if (go->neg && \ + len >= CILEN_CHAP && \ + p[1] == CILEN_CHAP && \ + p[0] == opt) { \ + len -= CILEN_CHAP; \ + INCPTR(2, p); \ + GETSHORT(cishort, p); \ + GETCHAR(cichar, p); \ + no.neg = 1; \ + code \ + } +#define NAKCICHAR(opt, neg, code) \ + if (go->neg && \ + len >= CILEN_CHAR && \ + p[1] == CILEN_CHAR && \ + p[0] == opt) { \ + len -= CILEN_CHAR; \ + INCPTR(2, p); \ + GETCHAR(cichar, p); \ + no.neg = 1; \ + code \ + } +#define NAKCISHORT(opt, neg, code) \ + if (go->neg && \ + len >= CILEN_SHORT && \ + p[1] == CILEN_SHORT && \ + p[0] == opt) { \ + len -= CILEN_SHORT; \ + INCPTR(2, p); \ + GETSHORT(cishort, p); \ + no.neg = 1; \ + code \ + } +#define NAKCILONG(opt, neg, code) \ + if (go->neg && \ + len >= CILEN_LONG && \ + p[1] == CILEN_LONG && \ + p[0] == opt) { \ + len -= CILEN_LONG; \ + INCPTR(2, p); \ + GETLONG(cilong, p); \ + no.neg = 1; \ + code \ + } +#define NAKCILQR(opt, neg, code) \ + if (go->neg && \ + len >= CILEN_LQR && \ + p[1] == CILEN_LQR && \ + p[0] == opt) { \ + len -= CILEN_LQR; \ + INCPTR(2, p); \ + GETSHORT(cishort, p); \ + GETLONG(cilong, p); \ + no.neg = 1; \ + code \ + } + + /* + * We don't care if they want to send us smaller packets than + * we want. Therefore, accept any MRU less than what we asked for, + * but then ignore the new value when setting the MRU in the kernel. + * If they send us a bigger MRU than what we asked, accept it, up to + * the limit of the default MRU we'd get if we didn't negotiate. + */ + if (go->neg_mru && go->mru != PPP_DEFMRU) { + NAKCISHORT(CI_MRU, neg_mru, + if (cishort <= wo->mru || cishort < PPP_DEFMRU) + try.mru = cishort; + ); + } + + /* + * Add any characters they want to our (receive-side) asyncmap. + */ + if (go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl) { + NAKCILONG(CI_ASYNCMAP, neg_asyncmap, + try.asyncmap = go->asyncmap | cilong; + ); + } + + /* + * If they've nak'd our authentication-protocol, check whether + * they are proposing a different protocol, or a different + * hash algorithm for CHAP. + */ + if ((go->neg_chap || go->neg_upap) + && len >= CILEN_SHORT + && p[0] == CI_AUTHTYPE && p[1] >= CILEN_SHORT && p[1] <= len) { + cilen = p[1]; + len -= cilen; + no.neg_chap = go->neg_chap; + no.neg_upap = go->neg_upap; + INCPTR(2, p); + GETSHORT(cishort, p); + if (cishort == PPP_PAP && cilen == CILEN_SHORT) { + /* + * If we were asking for CHAP, they obviously don't want to do it. + * If we weren't asking for CHAP, then we were asking for PAP, + * in which case this Nak is bad. + */ + if (!go->neg_chap) + goto bad; + try.neg_chap = 0; + + } else if (cishort == PPP_CHAP && cilen == CILEN_CHAP) { + GETCHAR(cichar, p); + if (go->neg_chap) { + /* + * We were asking for CHAP/MD5; they must want a different + * algorithm. If they can't do MD5, we'll have to stop + * asking for CHAP. + */ + if (cichar != go->chap_mdtype) + try.neg_chap = 0; + } else { + /* + * Stop asking for PAP if we were asking for it. + */ + try.neg_upap = 0; + } + + } else { + /* + * We don't recognize what they're suggesting. + * Stop asking for what we were asking for. + */ + if (go->neg_chap) + try.neg_chap = 0; + else + try.neg_upap = 0; + p += cilen - CILEN_SHORT; + } + } + + /* + * If they can't cope with our link quality protocol, we'll have + * to stop asking for LQR. We haven't got any other protocol. + * If they Nak the reporting period, take their value XXX ? + */ + NAKCILQR(CI_QUALITY, neg_lqr, + if (cishort != PPP_LQR) + try.neg_lqr = 0; + else + try.lqr_period = cilong; + ); + + /* + * Only implementing CBCP...not the rest of the callback options + */ + NAKCICHAR(CI_CALLBACK, neg_cbcp, + try.neg_cbcp = 0; + ); + + /* + * Check for a looped-back line. + */ + NAKCILONG(CI_MAGICNUMBER, neg_magicnumber, + try.magicnumber = magic(); + looped_back = 1; + ); + + /* + * Peer shouldn't send Nak for protocol compression or + * address/control compression requests; they should send + * a Reject instead. If they send a Nak, treat it as a Reject. + */ + NAKCIVOID(CI_PCOMPRESSION, neg_pcompression, + try.neg_pcompression = 0; + ); + NAKCIVOID(CI_ACCOMPRESSION, neg_accompression, + try.neg_accompression = 0; + ); + + /* + * There may be remaining CIs, if the peer is requesting negotiation + * on an option that we didn't include in our request packet. + * If we see an option that we requested, or one we've already seen + * in this packet, then this packet is bad. + * If we wanted to respond by starting to negotiate on the requested + * option(s), we could, but we don't, because except for the + * authentication type and quality protocol, if we are not negotiating + * an option, it is because we were told not to. + * For the authentication type, the Nak from the peer means + * `let me authenticate myself with you' which is a bit pointless. + * For the quality protocol, the Nak means `ask me to send you quality + * reports', but if we didn't ask for them, we don't want them. + * An option we don't recognize represents the peer asking to + * negotiate some option we don't support, so ignore it. + */ + while (len > CILEN_VOID) { + GETCHAR(citype, p); + GETCHAR(cilen, p); + if (cilen < CILEN_VOID || (len -= cilen) < 0) + goto bad; + next = p + cilen - 2; + + switch (citype) { + case CI_MRU: + if ((go->neg_mru && go->mru != PPP_DEFMRU) + || no.neg_mru || cilen != CILEN_SHORT) + goto bad; + GETSHORT(cishort, p); + if (cishort < PPP_DEFMRU) + try.mru = cishort; + break; + case CI_ASYNCMAP: + if ((go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl) + || no.neg_asyncmap || cilen != CILEN_LONG) + goto bad; + break; + case CI_AUTHTYPE: + if (go->neg_chap || no.neg_chap || go->neg_upap || no.neg_upap) + goto bad; + break; + case CI_MAGICNUMBER: + if (go->neg_magicnumber || no.neg_magicnumber || + cilen != CILEN_LONG) + goto bad; + break; + case CI_PCOMPRESSION: + if (go->neg_pcompression || no.neg_pcompression + || cilen != CILEN_VOID) + goto bad; + break; + case CI_ACCOMPRESSION: + if (go->neg_accompression || no.neg_accompression + || cilen != CILEN_VOID) + goto bad; + break; + case CI_QUALITY: + if (go->neg_lqr || no.neg_lqr || cilen != CILEN_LQR) + goto bad; + break; + } + p = next; + } + + /* If there is still anything left, this packet is bad. */ + if (len != 0) + goto bad; + + /* + * OK, the Nak is good. Now we can update state. + */ + if (f->state != OPENED) { + if (looped_back) { + if (++try.numloops >= lcp_loopbackfail) { + LCPDEBUG((LOG_NOTICE, "Serial line is looped back.\n")); + lcp_close(f->unit, "Loopback detected"); + } + } + else + try.numloops = 0; + *go = try; + } + + return 1; + +bad: + LCPDEBUG((LOG_WARNING, "lcp_nakci: received bad Nak!\n")); + return 0; +} + + +/* + * lcp_rejci - Peer has Rejected some of our CIs. + * This should not modify any state if the Reject is bad + * or if LCP is in the OPENED state. + * + * Returns: + * 0 - Reject was bad. + * 1 - Reject was good. + */ +static int lcp_rejci(fsm *f, u_char *p, int len) +{ + lcp_options *go = &lcp_gotoptions[f->unit]; + u_char cichar; + u_short cishort; + u32_t cilong; + lcp_options try; /* options to request next time */ + + try = *go; + + /* + * Any Rejected CIs must be in exactly the same order that we sent. + * Check packet length and CI length at each step. + * If we find any deviations, then this packet is bad. + */ +#define REJCIVOID(opt, neg) \ + if (go->neg && \ + len >= CILEN_VOID && \ + p[1] == CILEN_VOID && \ + p[0] == opt) { \ + len -= CILEN_VOID; \ + INCPTR(CILEN_VOID, p); \ + try.neg = 0; \ + LCPDEBUG((LOG_INFO, "lcp_rejci: void opt %d rejected\n", opt)); \ + } +#define REJCISHORT(opt, neg, val) \ + if (go->neg && \ + len >= CILEN_SHORT && \ + p[1] == CILEN_SHORT && \ + p[0] == opt) { \ + len -= CILEN_SHORT; \ + INCPTR(2, p); \ + GETSHORT(cishort, p); \ + /* Check rejected value. */ \ + if (cishort != val) \ + goto bad; \ + try.neg = 0; \ + LCPDEBUG((LOG_INFO,"lcp_rejci: short opt %d rejected\n", opt)); \ + } +#define REJCICHAP(opt, neg, val, digest) \ + if (go->neg && \ + len >= CILEN_CHAP && \ + p[1] == CILEN_CHAP && \ + p[0] == opt) { \ + len -= CILEN_CHAP; \ + INCPTR(2, p); \ + GETSHORT(cishort, p); \ + GETCHAR(cichar, p); \ + /* Check rejected value. */ \ + if (cishort != val || cichar != digest) \ + goto bad; \ + try.neg = 0; \ + try.neg_upap = 0; \ + LCPDEBUG((LOG_INFO,"lcp_rejci: chap opt %d rejected\n", opt)); \ + } +#define REJCILONG(opt, neg, val) \ + if (go->neg && \ + len >= CILEN_LONG && \ + p[1] == CILEN_LONG && \ + p[0] == opt) { \ + len -= CILEN_LONG; \ + INCPTR(2, p); \ + GETLONG(cilong, p); \ + /* Check rejected value. */ \ + if (cilong != val) \ + goto bad; \ + try.neg = 0; \ + LCPDEBUG((LOG_INFO,"lcp_rejci: long opt %d rejected\n", opt)); \ + } +#define REJCILQR(opt, neg, val) \ + if (go->neg && \ + len >= CILEN_LQR && \ + p[1] == CILEN_LQR && \ + p[0] == opt) { \ + len -= CILEN_LQR; \ + INCPTR(2, p); \ + GETSHORT(cishort, p); \ + GETLONG(cilong, p); \ + /* Check rejected value. */ \ + if (cishort != PPP_LQR || cilong != val) \ + goto bad; \ + try.neg = 0; \ + LCPDEBUG((LOG_INFO,"lcp_rejci: LQR opt %d rejected\n", opt)); \ + } +#define REJCICBCP(opt, neg, val) \ + if (go->neg && \ + len >= CILEN_CBCP && \ + p[1] == CILEN_CBCP && \ + p[0] == opt) { \ + len -= CILEN_CBCP; \ + INCPTR(2, p); \ + GETCHAR(cichar, p); \ + /* Check rejected value. */ \ + if (cichar != val) \ + goto bad; \ + try.neg = 0; \ + LCPDEBUG((LOG_INFO,"lcp_rejci: Callback opt %d rejected\n", opt)); \ + } + + REJCISHORT(CI_MRU, neg_mru, go->mru); + REJCILONG(CI_ASYNCMAP, neg_asyncmap, go->asyncmap); + REJCICHAP(CI_AUTHTYPE, neg_chap, PPP_CHAP, go->chap_mdtype); + if (!go->neg_chap) { + REJCISHORT(CI_AUTHTYPE, neg_upap, PPP_PAP); + } + REJCILQR(CI_QUALITY, neg_lqr, go->lqr_period); + REJCICBCP(CI_CALLBACK, neg_cbcp, CBCP_OPT); + REJCILONG(CI_MAGICNUMBER, neg_magicnumber, go->magicnumber); + REJCIVOID(CI_PCOMPRESSION, neg_pcompression); + REJCIVOID(CI_ACCOMPRESSION, neg_accompression); + + /* + * If there are any remaining CIs, then this packet is bad. + */ + if (len != 0) + goto bad; + /* + * Now we can update state. + */ + if (f->state != OPENED) + *go = try; + return 1; + +bad: + LCPDEBUG((LOG_WARNING, "lcp_rejci: received bad Reject!\n")); + return 0; +} + + +/* + * lcp_reqci - Check the peer's requested CIs and send appropriate response. + * + * Returns: CONFACK, CONFNAK or CONFREJ and input packet modified + * appropriately. If reject_if_disagree is non-zero, doesn't return + * CONFNAK; returns CONFREJ if it can't return CONFACK. + */ +static int lcp_reqci(fsm *f, + u_char *inp, /* Requested CIs */ + int *lenp, /* Length of requested CIs */ + int reject_if_disagree) +{ + lcp_options *go = &lcp_gotoptions[f->unit]; + lcp_options *ho = &lcp_hisoptions[f->unit]; + lcp_options *ao = &lcp_allowoptions[f->unit]; + u_char *cip, *next; /* Pointer to current and next CIs */ + int cilen, citype, cichar; /* Parsed len, type, char value */ + u_short cishort; /* Parsed short value */ + u32_t cilong; /* Parse long value */ + int rc = CONFACK; /* Final packet return code */ + int orc; /* Individual option return code */ + u_char *p; /* Pointer to next char to parse */ + u_char *rejp; /* Pointer to next char in reject frame */ + u_char *nakp; /* Pointer to next char in Nak frame */ + int l = *lenp; /* Length left */ +#if TRACELCP > 0 + char traceBuf[80]; + int traceNdx = 0; +#endif + + /* + * Reset all his options. + */ + BZERO(ho, sizeof(*ho)); + + /* + * Process all his options. + */ + next = inp; + nakp = nak_buffer; + rejp = inp; + while (l) { + orc = CONFACK; /* Assume success */ + cip = p = next; /* Remember begining of CI */ + if (l < 2 || /* Not enough data for CI header or */ + p[1] < 2 || /* CI length too small or */ + p[1] > l) { /* CI length too big? */ + LCPDEBUG((LOG_WARNING, "lcp_reqci: bad CI length!\n")); + orc = CONFREJ; /* Reject bad CI */ + cilen = l; /* Reject till end of packet */ + l = 0; /* Don't loop again */ + citype = 0; + goto endswitch; + } + GETCHAR(citype, p); /* Parse CI type */ + GETCHAR(cilen, p); /* Parse CI length */ + l -= cilen; /* Adjust remaining length */ + next += cilen; /* Step to next CI */ + + switch (citype) { /* Check CI type */ + case CI_MRU: + if (!ao->neg_mru) { /* Allow option? */ + LCPDEBUG((LOG_INFO, "lcp_reqci: Reject MRU - not allowed\n")); + orc = CONFREJ; /* Reject CI */ + break; + } else if (cilen != CILEN_SHORT) { /* Check CI length */ + LCPDEBUG((LOG_INFO, "lcp_reqci: Reject MRU - bad length\n")); + orc = CONFREJ; /* Reject CI */ + break; + } + GETSHORT(cishort, p); /* Parse MRU */ + + /* + * He must be able to receive at least our minimum. + * No need to check a maximum. If he sends a large number, + * we'll just ignore it. + */ + if (cishort < PPP_MINMRU) { + LCPDEBUG((LOG_INFO, "lcp_reqci: Nak - MRU too small\n")); + orc = CONFNAK; /* Nak CI */ + PUTCHAR(CI_MRU, nakp); + PUTCHAR(CILEN_SHORT, nakp); + PUTSHORT(PPP_MINMRU, nakp); /* Give him a hint */ + break; + } + ho->neg_mru = 1; /* Remember he sent MRU */ + ho->mru = cishort; /* And remember value */ +#if TRACELCP > 0 + snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " MRU %d", cishort); + traceNdx = strlen(traceBuf); +#endif + break; + + case CI_ASYNCMAP: + if (!ao->neg_asyncmap) { + LCPDEBUG((LOG_INFO, "lcp_reqci: Reject ASYNCMAP not allowed\n")); + orc = CONFREJ; + break; + } else if (cilen != CILEN_LONG) { + LCPDEBUG((LOG_INFO, "lcp_reqci: Reject ASYNCMAP bad length\n")); + orc = CONFREJ; + break; + } + GETLONG(cilong, p); + + /* + * Asyncmap must have set at least the bits + * which are set in lcp_allowoptions[unit].asyncmap. + */ + if ((ao->asyncmap & ~cilong) != 0) { + LCPDEBUG((LOG_INFO, "lcp_reqci: Nak ASYNCMAP %lX missing %lX\n", + cilong, ao->asyncmap)); + orc = CONFNAK; + PUTCHAR(CI_ASYNCMAP, nakp); + PUTCHAR(CILEN_LONG, nakp); + PUTLONG(ao->asyncmap | cilong, nakp); + break; + } + ho->neg_asyncmap = 1; + ho->asyncmap = cilong; +#if TRACELCP > 0 + snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " ASYNCMAP=%lX", cilong); + traceNdx = strlen(traceBuf); +#endif + break; + + case CI_AUTHTYPE: + if (cilen < CILEN_SHORT) { + LCPDEBUG((LOG_INFO, "lcp_reqci: Reject AUTHTYPE missing arg\n")); + orc = CONFREJ; + break; + } else if (!(ao->neg_upap || ao->neg_chap)) { + /* + * Reject the option if we're not willing to authenticate. + */ + LCPDEBUG((LOG_INFO, "lcp_reqci: Reject AUTHTYPE not allowed\n")); + orc = CONFREJ; + break; + } + GETSHORT(cishort, p); + + /* + * Authtype must be UPAP or CHAP. + * + * Note: if both ao->neg_upap and ao->neg_chap are set, + * and the peer sends a Configure-Request with two + * authenticate-protocol requests, one for CHAP and one + * for UPAP, then we will reject the second request. + * Whether we end up doing CHAP or UPAP depends then on + * the ordering of the CIs in the peer's Configure-Request. + */ + + if (cishort == PPP_PAP) { + if (ho->neg_chap) { /* we've already accepted CHAP */ + LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE PAP already accepted\n")); + orc = CONFREJ; + break; + } else if (cilen != CILEN_SHORT) { + LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE PAP bad len\n")); + orc = CONFREJ; + break; + } + if (!ao->neg_upap) { /* we don't want to do PAP */ + LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE PAP not allowed\n")); + orc = CONFNAK; /* NAK it and suggest CHAP */ + PUTCHAR(CI_AUTHTYPE, nakp); + PUTCHAR(CILEN_CHAP, nakp); + PUTSHORT(PPP_CHAP, nakp); + PUTCHAR(ao->chap_mdtype, nakp); + break; + } + ho->neg_upap = 1; +#if TRACELCP > 0 + snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " PAP (%X)", cishort); + traceNdx = strlen(traceBuf); +#endif + break; + } + if (cishort == PPP_CHAP) { + if (ho->neg_upap) { /* we've already accepted PAP */ + LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE CHAP accepted PAP\n")); + orc = CONFREJ; + break; + } else if (cilen != CILEN_CHAP) { + LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE CHAP bad len\n")); + orc = CONFREJ; + break; + } + if (!ao->neg_chap) { /* we don't want to do CHAP */ + LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE CHAP not allowed\n")); + orc = CONFNAK; /* NAK it and suggest PAP */ + PUTCHAR(CI_AUTHTYPE, nakp); + PUTCHAR(CILEN_SHORT, nakp); + PUTSHORT(PPP_PAP, nakp); + break; + } + GETCHAR(cichar, p); /* get digest type*/ + if (cichar != CHAP_DIGEST_MD5 +#ifdef CHAPMS + && cichar != CHAP_MICROSOFT +#endif + ) { + LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE CHAP digest=%d\n", cichar)); + orc = CONFNAK; + PUTCHAR(CI_AUTHTYPE, nakp); + PUTCHAR(CILEN_CHAP, nakp); + PUTSHORT(PPP_CHAP, nakp); + PUTCHAR(ao->chap_mdtype, nakp); + break; + } +#if TRACELCP > 0 + snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CHAP %X,%d", cishort, cichar); + traceNdx = strlen(traceBuf); +#endif + ho->chap_mdtype = cichar; /* save md type */ + ho->neg_chap = 1; + break; + } + + /* + * We don't recognize the protocol they're asking for. + * Nak it with something we're willing to do. + * (At this point we know ao->neg_upap || ao->neg_chap.) + */ + orc = CONFNAK; + PUTCHAR(CI_AUTHTYPE, nakp); + if (ao->neg_chap) { + LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE %d req CHAP\n", cishort)); + PUTCHAR(CILEN_CHAP, nakp); + PUTSHORT(PPP_CHAP, nakp); + PUTCHAR(ao->chap_mdtype, nakp); + } + else { + LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE %d req PAP\n", cishort)); + PUTCHAR(CILEN_SHORT, nakp); + PUTSHORT(PPP_PAP, nakp); + } + break; + + case CI_QUALITY: + GETSHORT(cishort, p); + GETLONG(cilong, p); +#if TRACELCP > 0 + snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " QUALITY (%x %x)", cishort, (unsigned int) cilong); + traceNdx = strlen(traceBuf); +#endif + + if (!ao->neg_lqr || + cilen != CILEN_LQR) { + orc = CONFREJ; + break; + } + + /* + * Check the protocol and the reporting period. + * XXX When should we Nak this, and what with? + */ + if (cishort != PPP_LQR) { + orc = CONFNAK; + PUTCHAR(CI_QUALITY, nakp); + PUTCHAR(CILEN_LQR, nakp); + PUTSHORT(PPP_LQR, nakp); + PUTLONG(ao->lqr_period, nakp); + break; + } + break; + + case CI_MAGICNUMBER: + if (!(ao->neg_magicnumber || go->neg_magicnumber) || + cilen != CILEN_LONG) { + orc = CONFREJ; + break; + } + GETLONG(cilong, p); +#if TRACELCP > 0 + snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " MAGICNUMBER (%lX)", cilong); + traceNdx = strlen(traceBuf); +#endif + + /* + * He must have a different magic number. + */ + if (go->neg_magicnumber && + cilong == go->magicnumber) { + cilong = magic(); /* Don't put magic() inside macro! */ + orc = CONFNAK; + PUTCHAR(CI_MAGICNUMBER, nakp); + PUTCHAR(CILEN_LONG, nakp); + PUTLONG(cilong, nakp); + break; + } + ho->neg_magicnumber = 1; + ho->magicnumber = cilong; + break; + + + case CI_PCOMPRESSION: +#if TRACELCP > 0 + snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " PCOMPRESSION"); + traceNdx = strlen(traceBuf); +#endif + if (!ao->neg_pcompression || + cilen != CILEN_VOID) { + orc = CONFREJ; + break; + } + ho->neg_pcompression = 1; + break; + + case CI_ACCOMPRESSION: +#if TRACELCP > 0 + snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " ACCOMPRESSION"); + traceNdx = strlen(traceBuf); +#endif + if (!ao->neg_accompression || + cilen != CILEN_VOID) { + orc = CONFREJ; + break; + } + ho->neg_accompression = 1; + break; + + case CI_MRRU: +#if TRACELCP > 0 + snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CI_MRRU"); + traceNdx = strlen(traceBuf); +#endif + orc = CONFREJ; + break; + + case CI_SSNHF: +#if TRACELCP > 0 + snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CI_SSNHF"); + traceNdx = strlen(traceBuf); +#endif + orc = CONFREJ; + break; + + case CI_EPDISC: +#if TRACELCP > 0 + snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CI_EPDISC"); + traceNdx = strlen(traceBuf); +#endif + orc = CONFREJ; + break; + + default: +#if TRACELCP + snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " unknown %d", citype); + traceNdx = strlen(traceBuf); +#endif + orc = CONFREJ; + break; + } + + endswitch: +#if TRACELCP + if (traceNdx >= 80 - 32) { + LCPDEBUG((LOG_INFO, "lcp_reqci: rcvd%s\n", traceBuf)); + traceNdx = 0; + } +#endif + if (orc == CONFACK && /* Good CI */ + rc != CONFACK) /* but prior CI wasnt? */ + continue; /* Don't send this one */ + + if (orc == CONFNAK) { /* Nak this CI? */ + if (reject_if_disagree /* Getting fed up with sending NAKs? */ + && citype != CI_MAGICNUMBER) { + orc = CONFREJ; /* Get tough if so */ + } + else { + if (rc == CONFREJ) /* Rejecting prior CI? */ + continue; /* Don't send this one */ + rc = CONFNAK; + } + } + if (orc == CONFREJ) { /* Reject this CI */ + rc = CONFREJ; + if (cip != rejp) /* Need to move rejected CI? */ + BCOPY(cip, rejp, cilen); /* Move it */ + INCPTR(cilen, rejp); /* Update output pointer */ + } + } + + /* + * If we wanted to send additional NAKs (for unsent CIs), the + * code would go here. The extra NAKs would go at *nakp. + * At present there are no cases where we want to ask the + * peer to negotiate an option. + */ + + switch (rc) { + case CONFACK: + *lenp = (int)(next - inp); + break; + case CONFNAK: + /* + * Copy the Nak'd options from the nak_buffer to the caller's buffer. + */ + *lenp = (int)(nakp - nak_buffer); + BCOPY(nak_buffer, inp, *lenp); + break; + case CONFREJ: + *lenp = (int)(rejp - inp); + break; + } + +#if TRACELCP > 0 + if (traceNdx > 0) { + LCPDEBUG((LOG_INFO, "lcp_reqci: %s\n", traceBuf)); + } +#endif + LCPDEBUG((LOG_INFO, "lcp_reqci: returning CONF%s.\n", CODENAME(rc))); + return (rc); /* Return final code */ +} + + +/* + * lcp_up - LCP has come UP. + */ +static void lcp_up(fsm *f) +{ + lcp_options *wo = &lcp_wantoptions[f->unit]; + lcp_options *ho = &lcp_hisoptions[f->unit]; + lcp_options *go = &lcp_gotoptions[f->unit]; + lcp_options *ao = &lcp_allowoptions[f->unit]; + + if (!go->neg_magicnumber) + go->magicnumber = 0; + if (!ho->neg_magicnumber) + ho->magicnumber = 0; + + /* + * Set our MTU to the smaller of the MTU we wanted and + * the MRU our peer wanted. If we negotiated an MRU, + * set our MRU to the larger of value we wanted and + * the value we got in the negotiation. + */ + ppp_send_config(f->unit, LWIP_MIN(ao->mru, (ho->neg_mru? ho->mru: PPP_MRU)), + (ho->neg_asyncmap? ho->asyncmap: 0xffffffffl), + ho->neg_pcompression, ho->neg_accompression); + /* + * If the asyncmap hasn't been negotiated, we really should + * set the receive asyncmap to ffffffff, but we set it to 0 + * for backwards contemptibility. + */ + ppp_recv_config(f->unit, (go->neg_mru? LWIP_MAX(wo->mru, go->mru): PPP_MRU), + (go->neg_asyncmap? go->asyncmap: 0x00000000), + go->neg_pcompression, go->neg_accompression); + + if (ho->neg_mru) + peer_mru[f->unit] = ho->mru; + + lcp_echo_lowerup(f->unit); /* Enable echo messages */ + + link_established(f->unit); +} + + +/* + * lcp_down - LCP has gone DOWN. + * + * Alert other protocols. + */ +static void lcp_down(fsm *f) +{ + lcp_options *go = &lcp_gotoptions[f->unit]; + + lcp_echo_lowerdown(f->unit); + + link_down(f->unit); + + ppp_send_config(f->unit, PPP_MRU, 0xffffffffl, 0, 0); + ppp_recv_config(f->unit, PPP_MRU, + (go->neg_asyncmap? go->asyncmap: 0x00000000), + go->neg_pcompression, go->neg_accompression); + peer_mru[f->unit] = PPP_MRU; +} + + +/* + * lcp_starting - LCP needs the lower layer up. + */ +static void lcp_starting(fsm *f) +{ + link_required(f->unit); +} + + +/* + * lcp_finished - LCP has finished with the lower layer. + */ +static void lcp_finished(fsm *f) +{ + link_terminated(f->unit); +} + + +#if 0 +/* + * print_string - print a readable representation of a string using + * printer. + */ +static void print_string( + char *p, + int len, + void (*printer) (void *, char *, ...), + void *arg +) +{ + int c; + + printer(arg, "\""); + for (; len > 0; --len) { + c = *p++; + if (' ' <= c && c <= '~') { + if (c == '\\' || c == '"') + printer(arg, "\\"); + printer(arg, "%c", c); + } else { + switch (c) { + case '\n': + printer(arg, "\\n"); + break; + case '\r': + printer(arg, "\\r"); + break; + case '\t': + printer(arg, "\\t"); + break; + default: + printer(arg, "\\%.3o", c); + } + } + } + printer(arg, "\""); +} + + +/* + * lcp_printpkt - print the contents of an LCP packet. + */ +static char *lcp_codenames[] = { + "ConfReq", "ConfAck", "ConfNak", "ConfRej", + "TermReq", "TermAck", "CodeRej", "ProtRej", + "EchoReq", "EchoRep", "DiscReq" +}; + +static int lcp_printpkt( + u_char *p, + int plen, + void (*printer) (void *, char *, ...), + void *arg +) +{ + int code, id, len, olen; + u_char *pstart, *optend; + u_short cishort; + u32_t cilong; + + if (plen < HEADERLEN) + return 0; + pstart = p; + GETCHAR(code, p); + GETCHAR(id, p); + GETSHORT(len, p); + if (len < HEADERLEN || len > plen) + return 0; + + if (code >= 1 && code <= sizeof(lcp_codenames) / sizeof(char *)) + printer(arg, " %s", lcp_codenames[code-1]); + else + printer(arg, " code=0x%x", code); + printer(arg, " id=0x%x", id); + len -= HEADERLEN; + switch (code) { + case CONFREQ: + case CONFACK: + case CONFNAK: + case CONFREJ: + /* print option list */ + while (len >= 2) { + GETCHAR(code, p); + GETCHAR(olen, p); + p -= 2; + if (olen < 2 || olen > len) { + break; + } + printer(arg, " <"); + len -= olen; + optend = p + olen; + switch (code) { + case CI_MRU: + if (olen == CILEN_SHORT) { + p += 2; + GETSHORT(cishort, p); + printer(arg, "mru %d", cishort); + } + break; + case CI_ASYNCMAP: + if (olen == CILEN_LONG) { + p += 2; + GETLONG(cilong, p); + printer(arg, "asyncmap 0x%lx", cilong); + } + break; + case CI_AUTHTYPE: + if (olen >= CILEN_SHORT) { + p += 2; + printer(arg, "auth "); + GETSHORT(cishort, p); + switch (cishort) { + case PPP_PAP: + printer(arg, "pap"); + break; + case PPP_CHAP: + printer(arg, "chap"); + break; + default: + printer(arg, "0x%x", cishort); + } + } + break; + case CI_QUALITY: + if (olen >= CILEN_SHORT) { + p += 2; + printer(arg, "quality "); + GETSHORT(cishort, p); + switch (cishort) { + case PPP_LQR: + printer(arg, "lqr"); + break; + default: + printer(arg, "0x%x", cishort); + } + } + break; + case CI_CALLBACK: + if (olen >= CILEN_CHAR) { + p += 2; + printer(arg, "callback "); + GETSHORT(cishort, p); + switch (cishort) { + case CBCP_OPT: + printer(arg, "CBCP"); + break; + default: + printer(arg, "0x%x", cishort); + } + } + break; + case CI_MAGICNUMBER: + if (olen == CILEN_LONG) { + p += 2; + GETLONG(cilong, p); + printer(arg, "magic 0x%x", cilong); + } + break; + case CI_PCOMPRESSION: + if (olen == CILEN_VOID) { + p += 2; + printer(arg, "pcomp"); + } + break; + case CI_ACCOMPRESSION: + if (olen == CILEN_VOID) { + p += 2; + printer(arg, "accomp"); + } + break; + } + while (p < optend) { + GETCHAR(code, p); + printer(arg, " %.2x", code); + } + printer(arg, ">"); + } + break; + + case TERMACK: + case TERMREQ: + if (len > 0 && *p >= ' ' && *p < 0x7f) { + printer(arg, " "); + print_string((char*)p, len, printer, arg); + p += len; + len = 0; + } + break; + + case ECHOREQ: + case ECHOREP: + case DISCREQ: + if (len >= 4) { + GETLONG(cilong, p); + printer(arg, " magic=0x%x", cilong); + p += 4; + len -= 4; + } + break; + } + + /* print the rest of the bytes in the packet */ + for (; len > 0; --len) { + GETCHAR(code, p); + printer(arg, " %.2x", code); + } + + return (int)(p - pstart); +} +#endif + +/* + * Time to shut down the link because there is nothing out there. + */ + +static void LcpLinkFailure (fsm *f) +{ + if (f->state == OPENED) { + LCPDEBUG((LOG_INFO, "No response to %d echo-requests\n", lcp_echos_pending)); + LCPDEBUG((LOG_NOTICE, "Serial link appears to be disconnected.\n")); + lcp_close(f->unit, "Peer not responding"); + } +} + +/* + * Timer expired for the LCP echo requests from this process. + */ + +static void LcpEchoCheck (fsm *f) +{ + LcpSendEchoRequest (f); + + /* + * Start the timer for the next interval. + */ + LWIP_ASSERT("lcp_echo_timer_running == 0", lcp_echo_timer_running == 0); + + TIMEOUT (LcpEchoTimeout, f, lcp_echo_interval); + lcp_echo_timer_running = 1; +} + +/* + * LcpEchoTimeout - Timer expired on the LCP echo + */ + +static void LcpEchoTimeout (void *arg) +{ + if (lcp_echo_timer_running != 0) { + lcp_echo_timer_running = 0; + LcpEchoCheck ((fsm *) arg); + } +} + +/* + * LcpEchoReply - LCP has received a reply to the echo + */ +static void lcp_received_echo_reply (fsm *f, int id, u_char *inp, int len) +{ + u32_t magic; + + (void)id; + + /* Check the magic number - don't count replies from ourselves. */ + if (len < 4) { + LCPDEBUG((LOG_WARNING, "lcp: received short Echo-Reply, length %d\n", len)); + return; + } + GETLONG(magic, inp); + if (lcp_gotoptions[f->unit].neg_magicnumber + && magic == lcp_gotoptions[f->unit].magicnumber) { + LCPDEBUG((LOG_WARNING, "appear to have received our own echo-reply!\n")); + return; + } + + /* Reset the number of outstanding echo frames */ + lcp_echos_pending = 0; +} + +/* + * LcpSendEchoRequest - Send an echo request frame to the peer + */ + +static void LcpSendEchoRequest (fsm *f) +{ + u32_t lcp_magic; + u_char pkt[4], *pktp; + + /* + * Detect the failure of the peer at this point. + */ + if (lcp_echo_fails != 0) { + if (lcp_echos_pending++ >= lcp_echo_fails) { + LcpLinkFailure(f); + lcp_echos_pending = 0; + } + } + + /* + * Make and send the echo request frame. + */ + if (f->state == OPENED) { + lcp_magic = lcp_gotoptions[f->unit].magicnumber; + pktp = pkt; + PUTLONG(lcp_magic, pktp); + fsm_sdata(f, ECHOREQ, (u_char)(lcp_echo_number++ & 0xFF), pkt, (int)(pktp - pkt)); + } +} + +/* + * lcp_echo_lowerup - Start the timer for the LCP frame + */ + +static void lcp_echo_lowerup (int unit) +{ + fsm *f = &lcp_fsm[unit]; + + /* Clear the parameters for generating echo frames */ + lcp_echos_pending = 0; + lcp_echo_number = 0; + lcp_echo_timer_running = 0; + + /* If a timeout interval is specified then start the timer */ + if (lcp_echo_interval != 0) + LcpEchoCheck (f); +} + +/* + * lcp_echo_lowerdown - Stop the timer for the LCP frame + */ + +static void lcp_echo_lowerdown (int unit) +{ + fsm *f = &lcp_fsm[unit]; + + if (lcp_echo_timer_running != 0) { + UNTIMEOUT (LcpEchoTimeout, f); + lcp_echo_timer_running = 0; + } +} + +#endif /* PPP_SUPPORT */ diff --git a/20080212/Demo/Common/ethernet/lwIP/netif/ppp/lcp.h b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/lcp.h new file mode 100644 index 000000000..2c0c34007 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/lcp.h @@ -0,0 +1,169 @@ +/***************************************************************************** +* lcp.h - Network Link Control Protocol header file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1997 Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-11-05 Guy Lancaster , Global Election Systems Inc. +* Original derived from BSD codes. +*****************************************************************************/ +/* + * lcp.h - Link Control Protocol definitions. + * + * Copyright (c) 1989 Carnegie Mellon University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Carnegie Mellon University. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * $Id: lcp.h,v 1.1 2003/05/27 14:37:56 jani Exp $ + */ + +#ifndef LCP_H +#define LCP_H + + +/************************* +*** PUBLIC DEFINITIONS *** +*************************/ +/* + * Options. + */ +#define CI_MRU 1 /* Maximum Receive Unit */ +#define CI_ASYNCMAP 2 /* Async Control Character Map */ +#define CI_AUTHTYPE 3 /* Authentication Type */ +#define CI_QUALITY 4 /* Quality Protocol */ +#define CI_MAGICNUMBER 5 /* Magic Number */ +#define CI_PCOMPRESSION 7 /* Protocol Field Compression */ +#define CI_ACCOMPRESSION 8 /* Address/Control Field Compression */ +#define CI_CALLBACK 13 /* callback */ +#define CI_MRRU 17 /* max reconstructed receive unit; multilink */ +#define CI_SSNHF 18 /* short sequence numbers for multilink */ +#define CI_EPDISC 19 /* endpoint discriminator */ + +/* + * LCP-specific packet types. + */ +#define PROTREJ 8 /* Protocol Reject */ +#define ECHOREQ 9 /* Echo Request */ +#define ECHOREP 10 /* Echo Reply */ +#define DISCREQ 11 /* Discard Request */ +#define CBCP_OPT 6 /* Use callback control protocol */ + + +/************************ +*** PUBLIC DATA TYPES *** +************************/ + +/* + * The state of options is described by an lcp_options structure. + */ +typedef struct lcp_options { + u_int passive : 1; /* Don't die if we don't get a response */ + u_int silent : 1; /* Wait for the other end to start first */ + u_int restart : 1; /* Restart vs. exit after close */ + u_int neg_mru : 1; /* Negotiate the MRU? */ + u_int neg_asyncmap : 1; /* Negotiate the async map? */ + u_int neg_upap : 1; /* Ask for UPAP authentication? */ + u_int neg_chap : 1; /* Ask for CHAP authentication? */ + u_int neg_magicnumber : 1; /* Ask for magic number? */ + u_int neg_pcompression : 1; /* HDLC Protocol Field Compression? */ + u_int neg_accompression : 1; /* HDLC Address/Control Field Compression? */ + u_int neg_lqr : 1; /* Negotiate use of Link Quality Reports */ + u_int neg_cbcp : 1; /* Negotiate use of CBCP */ +#ifdef PPP_MULTILINK + u_int neg_mrru : 1; /* Negotiate multilink MRRU */ + u_int neg_ssnhf : 1; /* Negotiate short sequence numbers */ + u_int neg_endpoint : 1; /* Negotiate endpoint discriminator */ +#endif + u_short mru; /* Value of MRU */ +#ifdef PPP_MULTILINK + u_short mrru; /* Value of MRRU, and multilink enable */ +#endif + u_char chap_mdtype; /* which MD type (hashing algorithm) */ + u32_t asyncmap; /* Value of async map */ + u32_t magicnumber; + int numloops; /* Number of loops during magic number neg. */ + u32_t lqr_period; /* Reporting period for LQR 1/100ths second */ +#ifdef PPP_MULTILINK + struct epdisc endpoint; /* endpoint discriminator */ +#endif +} lcp_options; + +/* + * Values for phase from BSD pppd.h based on RFC 1661. + */ +typedef enum { + PHASE_DEAD = 0, + PHASE_INITIALIZE, + PHASE_ESTABLISH, + PHASE_AUTHENTICATE, + PHASE_CALLBACK, + PHASE_NETWORK, + PHASE_TERMINATE +} LinkPhase; + + +/***************************** +*** PUBLIC DATA STRUCTURES *** +*****************************/ + +extern LinkPhase lcp_phase[NUM_PPP]; /* Phase of link session (RFC 1661) */ +extern lcp_options lcp_wantoptions[]; +extern lcp_options lcp_gotoptions[]; +extern lcp_options lcp_allowoptions[]; +extern lcp_options lcp_hisoptions[]; +extern ext_accm xmit_accm[]; + + +/*********************** +*** PUBLIC FUNCTIONS *** +***********************/ + +void lcp_init (int); +void lcp_open (int); +void lcp_close (int, char *); +void lcp_lowerup (int); +void lcp_lowerdown (int); +void lcp_sprotrej (int, u_char *, int); /* send protocol reject */ + +extern struct protent lcp_protent; + +/* Default number of times we receive our magic number from the peer + before deciding the link is looped-back. */ +#define DEFLOOPBACKFAIL 10 + +#endif /* LCP_H */ + diff --git a/20080212/Demo/Common/ethernet/lwIP/netif/ppp/magic.c b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/magic.c new file mode 100644 index 000000000..6e9d47538 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/magic.c @@ -0,0 +1,79 @@ +/***************************************************************************** +* magic.c - Network Random Number Generator program file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1997 by Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-12-04 Guy Lancaster , Global Election Systems Inc. +* Original based on BSD magic.c. +*****************************************************************************/ +/* + * magic.c - PPP Magic Number routines. + * + * Copyright (c) 1989 Carnegie Mellon University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Carnegie Mellon University. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +#include "ppp.h" +#include "randm.h" +#include "magic.h" + + +/***********************************/ +/*** PUBLIC FUNCTION DEFINITIONS ***/ +/***********************************/ +/* + * magicInit - Initialize the magic number generator. + * + * Since we use another random number generator that has its own + * initialization, we do nothing here. + */ +void magicInit() +{ + return; +} + +/* + * magic - Returns the next magic number. + */ +u32_t magic() +{ + return avRandom(); +} + + diff --git a/20080212/Demo/Common/ethernet/lwIP/netif/ppp/magic.h b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/magic.h new file mode 100644 index 000000000..6e9b10b58 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/magic.h @@ -0,0 +1,64 @@ +/***************************************************************************** +* magic.h - Network Random Number Generator header file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1997 Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-12-04 Guy Lancaster , Global Election Systems Inc. +* Original derived from BSD codes. +*****************************************************************************/ +/* + * magic.h - PPP Magic Number definitions. + * + * Copyright (c) 1989 Carnegie Mellon University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Carnegie Mellon University. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * $Id: magic.h,v 1.1 2003/05/27 14:37:56 jani Exp $ + */ + +#ifndef MAGIC_H +#define MAGIC_H + +/***************************************************************************** +************************** PUBLIC FUNCTIONS ********************************** +*****************************************************************************/ + +void magicInit(void); /* Initialize the magic number generator */ +u32_t magic(void); /* Returns the next magic number */ + +#endif /* MAGIC_H */ diff --git a/20080212/Demo/Common/ethernet/lwIP/netif/ppp/md5.c b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/md5.c new file mode 100644 index 000000000..488d64af5 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/md5.c @@ -0,0 +1,306 @@ +/* + *********************************************************************** + ** md5.c -- the source code for MD5 routines ** + ** RSA Data Security, Inc. MD5 Message-Digest Algorithm ** + ** Created: 2/17/90 RLR ** + ** Revised: 1/91 SRD,AJ,BSK,JT Reference C ver., 7/10 constant corr. ** + *********************************************************************** + */ + +/* + *********************************************************************** + ** Copyright (C) 1990, RSA Data Security, Inc. All rights reserved. ** + ** ** + ** License to copy and use this software is granted provided that ** + ** it is identified as the "RSA Data Security, Inc. MD5 Message- ** + ** Digest Algorithm" in all material mentioning or referencing this ** + ** software or this function. ** + ** ** + ** License is also granted to make and use derivative works ** + ** provided that such works are identified as "derived from the RSA ** + ** Data Security, Inc. MD5 Message-Digest Algorithm" in all ** + ** material mentioning or referencing the derived work. ** + ** ** + ** RSA Data Security, Inc. makes no representations concerning ** + ** either the merchantability of this software or the suitability ** + ** of this software for any particular purpose. It is provided "as ** + ** is" without express or implied warranty of any kind. ** + ** ** + ** These notices must be retained in any copies of any part of this ** + ** documentation and/or software. ** + *********************************************************************** + */ + +#include "ppp.h" +#include "md5.h" +#include "pppdebug.h" + +#if CHAP_SUPPORT > 0 || MD5_SUPPORT > 0 + +/* + *********************************************************************** + ** Message-digest routines: ** + ** To form the message digest for a message M ** + ** (1) Initialize a context buffer mdContext using MD5Init ** + ** (2) Call MD5Update on mdContext and M ** + ** (3) Call MD5Final on mdContext ** + ** The message digest is now in mdContext->digest[0...15] ** + *********************************************************************** + */ + +/* forward declaration */ +static void Transform (u32_t *buf, u32_t *in); + +static unsigned char PADDING[64] = { + 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +}; + +/* F, G, H and I are basic MD5 functions */ +#define F(x, y, z) (((x) & (y)) | ((~x) & (z))) +#define G(x, y, z) (((x) & (z)) | ((y) & (~z))) +#define H(x, y, z) ((x) ^ (y) ^ (z)) +#define I(x, y, z) ((y) ^ ((x) | (~z))) + +/* ROTATE_LEFT rotates x left n bits */ +#define ROTATE_LEFT(x, n) (((x) << (n)) | ((x) >> (32-(n)))) + +/* FF, GG, HH, and II transformations for rounds 1, 2, 3, and 4 */ +/* Rotation is separate from addition to prevent recomputation */ +#define FF(a, b, c, d, x, s, ac) \ + {(a) += F ((b), (c), (d)) + (x) + (u32_t)(ac); \ + (a) = ROTATE_LEFT ((a), (s)); \ + (a) += (b); \ + } +#define GG(a, b, c, d, x, s, ac) \ + {(a) += G ((b), (c), (d)) + (x) + (u32_t)(ac); \ + (a) = ROTATE_LEFT ((a), (s)); \ + (a) += (b); \ + } +#define HH(a, b, c, d, x, s, ac) \ + {(a) += H ((b), (c), (d)) + (x) + (u32_t)(ac); \ + (a) = ROTATE_LEFT ((a), (s)); \ + (a) += (b); \ + } +#define II(a, b, c, d, x, s, ac) \ + {(a) += I ((b), (c), (d)) + (x) + (u32_t)(ac); \ + (a) = ROTATE_LEFT ((a), (s)); \ + (a) += (b); \ + } + +#ifdef __STDC__ +#define UL(x) x##UL +#else +#ifdef WIN32 +#define UL(x) x##UL +#else +#define UL(x) x +#endif +#endif + +/* The routine MD5Init initializes the message-digest context + mdContext. All fields are set to zero. + */ +void MD5Init (MD5_CTX *mdContext) +{ + mdContext->i[0] = mdContext->i[1] = (u32_t)0; + + /* Load magic initialization constants. + */ + mdContext->buf[0] = (u32_t)0x67452301UL; + mdContext->buf[1] = (u32_t)0xefcdab89UL; + mdContext->buf[2] = (u32_t)0x98badcfeUL; + mdContext->buf[3] = (u32_t)0x10325476UL; +} + +/* The routine MD5Update updates the message-digest context to + account for the presence of each of the characters inBuf[0..inLen-1] + in the message whose digest is being computed. + */ +void MD5Update(MD5_CTX *mdContext, unsigned char *inBuf, unsigned int inLen) +{ + u32_t in[16]; + int mdi; + unsigned int i, ii; + +#if 0 + ppp_trace(LOG_INFO, "MD5Update: %u:%.*H\n", inLen, MIN(inLen, 20) * 2, inBuf); + ppp_trace(LOG_INFO, "MD5Update: %u:%s\n", inLen, inBuf); +#endif + + /* compute number of bytes mod 64 */ + mdi = (int)((mdContext->i[0] >> 3) & 0x3F); + + /* update number of bits */ + if ((mdContext->i[0] + ((u32_t)inLen << 3)) < mdContext->i[0]) + mdContext->i[1]++; + mdContext->i[0] += ((u32_t)inLen << 3); + mdContext->i[1] += ((u32_t)inLen >> 29); + + while (inLen--) { + /* add new character to buffer, increment mdi */ + mdContext->in[mdi++] = *inBuf++; + + /* transform if necessary */ + if (mdi == 0x40) { + for (i = 0, ii = 0; i < 16; i++, ii += 4) + in[i] = (((u32_t)mdContext->in[ii+3]) << 24) | + (((u32_t)mdContext->in[ii+2]) << 16) | + (((u32_t)mdContext->in[ii+1]) << 8) | + ((u32_t)mdContext->in[ii]); + Transform (mdContext->buf, in); + mdi = 0; + } + } +} + +/* The routine MD5Final terminates the message-digest computation and + ends with the desired message digest in mdContext->digest[0...15]. + */ +void MD5Final (unsigned char hash[], MD5_CTX *mdContext) +{ + u32_t in[16]; + int mdi; + unsigned int i, ii; + unsigned int padLen; + + /* save number of bits */ + in[14] = mdContext->i[0]; + in[15] = mdContext->i[1]; + + /* compute number of bytes mod 64 */ + mdi = (int)((mdContext->i[0] >> 3) & 0x3F); + + /* pad out to 56 mod 64 */ + padLen = (mdi < 56) ? (56 - mdi) : (120 - mdi); + MD5Update (mdContext, PADDING, padLen); + + /* append length in bits and transform */ + for (i = 0, ii = 0; i < 14; i++, ii += 4) + in[i] = (((u32_t)mdContext->in[ii+3]) << 24) | + (((u32_t)mdContext->in[ii+2]) << 16) | + (((u32_t)mdContext->in[ii+1]) << 8) | + ((u32_t)mdContext->in[ii]); + Transform (mdContext->buf, in); + + /* store buffer in digest */ + for (i = 0, ii = 0; i < 4; i++, ii += 4) { + mdContext->digest[ii] = (unsigned char)(mdContext->buf[i] & 0xFF); + mdContext->digest[ii+1] = + (unsigned char)((mdContext->buf[i] >> 8) & 0xFF); + mdContext->digest[ii+2] = + (unsigned char)((mdContext->buf[i] >> 16) & 0xFF); + mdContext->digest[ii+3] = + (unsigned char)((mdContext->buf[i] >> 24) & 0xFF); + } + memcpy(hash, mdContext->digest, 16); +} + +/* Basic MD5 step. Transforms buf based on in. + */ +static void Transform (u32_t *buf, u32_t *in) +{ + u32_t a = buf[0], b = buf[1], c = buf[2], d = buf[3]; + + /* Round 1 */ +#define S11 7 +#define S12 12 +#define S13 17 +#define S14 22 + FF ( a, b, c, d, in[ 0], S11, UL(3614090360)); /* 1 */ + FF ( d, a, b, c, in[ 1], S12, UL(3905402710)); /* 2 */ + FF ( c, d, a, b, in[ 2], S13, UL( 606105819)); /* 3 */ + FF ( b, c, d, a, in[ 3], S14, UL(3250441966)); /* 4 */ + FF ( a, b, c, d, in[ 4], S11, UL(4118548399)); /* 5 */ + FF ( d, a, b, c, in[ 5], S12, UL(1200080426)); /* 6 */ + FF ( c, d, a, b, in[ 6], S13, UL(2821735955)); /* 7 */ + FF ( b, c, d, a, in[ 7], S14, UL(4249261313)); /* 8 */ + FF ( a, b, c, d, in[ 8], S11, UL(1770035416)); /* 9 */ + FF ( d, a, b, c, in[ 9], S12, UL(2336552879)); /* 10 */ + FF ( c, d, a, b, in[10], S13, UL(4294925233)); /* 11 */ + FF ( b, c, d, a, in[11], S14, UL(2304563134)); /* 12 */ + FF ( a, b, c, d, in[12], S11, UL(1804603682)); /* 13 */ + FF ( d, a, b, c, in[13], S12, UL(4254626195)); /* 14 */ + FF ( c, d, a, b, in[14], S13, UL(2792965006)); /* 15 */ + FF ( b, c, d, a, in[15], S14, UL(1236535329)); /* 16 */ + + /* Round 2 */ +#define S21 5 +#define S22 9 +#define S23 14 +#define S24 20 + GG ( a, b, c, d, in[ 1], S21, UL(4129170786)); /* 17 */ + GG ( d, a, b, c, in[ 6], S22, UL(3225465664)); /* 18 */ + GG ( c, d, a, b, in[11], S23, UL( 643717713)); /* 19 */ + GG ( b, c, d, a, in[ 0], S24, UL(3921069994)); /* 20 */ + GG ( a, b, c, d, in[ 5], S21, UL(3593408605)); /* 21 */ + GG ( d, a, b, c, in[10], S22, UL( 38016083)); /* 22 */ + GG ( c, d, a, b, in[15], S23, UL(3634488961)); /* 23 */ + GG ( b, c, d, a, in[ 4], S24, UL(3889429448)); /* 24 */ + GG ( a, b, c, d, in[ 9], S21, UL( 568446438)); /* 25 */ + GG ( d, a, b, c, in[14], S22, UL(3275163606)); /* 26 */ + GG ( c, d, a, b, in[ 3], S23, UL(4107603335)); /* 27 */ + GG ( b, c, d, a, in[ 8], S24, UL(1163531501)); /* 28 */ + GG ( a, b, c, d, in[13], S21, UL(2850285829)); /* 29 */ + GG ( d, a, b, c, in[ 2], S22, UL(4243563512)); /* 30 */ + GG ( c, d, a, b, in[ 7], S23, UL(1735328473)); /* 31 */ + GG ( b, c, d, a, in[12], S24, UL(2368359562)); /* 32 */ + + /* Round 3 */ +#define S31 4 +#define S32 11 +#define S33 16 +#define S34 23 + HH ( a, b, c, d, in[ 5], S31, UL(4294588738)); /* 33 */ + HH ( d, a, b, c, in[ 8], S32, UL(2272392833)); /* 34 */ + HH ( c, d, a, b, in[11], S33, UL(1839030562)); /* 35 */ + HH ( b, c, d, a, in[14], S34, UL(4259657740)); /* 36 */ + HH ( a, b, c, d, in[ 1], S31, UL(2763975236)); /* 37 */ + HH ( d, a, b, c, in[ 4], S32, UL(1272893353)); /* 38 */ + HH ( c, d, a, b, in[ 7], S33, UL(4139469664)); /* 39 */ + HH ( b, c, d, a, in[10], S34, UL(3200236656)); /* 40 */ + HH ( a, b, c, d, in[13], S31, UL( 681279174)); /* 41 */ + HH ( d, a, b, c, in[ 0], S32, UL(3936430074)); /* 42 */ + HH ( c, d, a, b, in[ 3], S33, UL(3572445317)); /* 43 */ + HH ( b, c, d, a, in[ 6], S34, UL( 76029189)); /* 44 */ + HH ( a, b, c, d, in[ 9], S31, UL(3654602809)); /* 45 */ + HH ( d, a, b, c, in[12], S32, UL(3873151461)); /* 46 */ + HH ( c, d, a, b, in[15], S33, UL( 530742520)); /* 47 */ + HH ( b, c, d, a, in[ 2], S34, UL(3299628645)); /* 48 */ + + /* Round 4 */ +#define S41 6 +#define S42 10 +#define S43 15 +#define S44 21 + II ( a, b, c, d, in[ 0], S41, UL(4096336452)); /* 49 */ + II ( d, a, b, c, in[ 7], S42, UL(1126891415)); /* 50 */ + II ( c, d, a, b, in[14], S43, UL(2878612391)); /* 51 */ + II ( b, c, d, a, in[ 5], S44, UL(4237533241)); /* 52 */ + II ( a, b, c, d, in[12], S41, UL(1700485571)); /* 53 */ + II ( d, a, b, c, in[ 3], S42, UL(2399980690)); /* 54 */ + II ( c, d, a, b, in[10], S43, UL(4293915773)); /* 55 */ + II ( b, c, d, a, in[ 1], S44, UL(2240044497)); /* 56 */ + II ( a, b, c, d, in[ 8], S41, UL(1873313359)); /* 57 */ + II ( d, a, b, c, in[15], S42, UL(4264355552)); /* 58 */ + II ( c, d, a, b, in[ 6], S43, UL(2734768916)); /* 59 */ + II ( b, c, d, a, in[13], S44, UL(1309151649)); /* 60 */ + II ( a, b, c, d, in[ 4], S41, UL(4149444226)); /* 61 */ + II ( d, a, b, c, in[11], S42, UL(3174756917)); /* 62 */ + II ( c, d, a, b, in[ 2], S43, UL( 718787259)); /* 63 */ + II ( b, c, d, a, in[ 9], S44, UL(3951481745)); /* 64 */ + + buf[0] += a; + buf[1] += b; + buf[2] += c; + buf[3] += d; +} + +#endif + diff --git a/20080212/Demo/Common/ethernet/lwIP/netif/ppp/md5.h b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/md5.h new file mode 100644 index 000000000..83d318cfb --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/md5.h @@ -0,0 +1,55 @@ +/* + *********************************************************************** + ** md5.h -- header file for implementation of MD5 ** + ** RSA Data Security, Inc. MD5 Message-Digest Algorithm ** + ** Created: 2/17/90 RLR ** + ** Revised: 12/27/90 SRD,AJ,BSK,JT Reference C version ** + ** Revised (for MD5): RLR 4/27/91 ** + ** -- G modified to have y&~z instead of y&z ** + ** -- FF, GG, HH modified to add in last register done ** + ** -- Access pattern: round 2 works mod 5, round 3 works mod 3 ** + ** -- distinct additive constant for each step ** + ** -- round 4 added, working mod 7 ** + *********************************************************************** + */ + +/* + *********************************************************************** + ** Copyright (C) 1990, RSA Data Security, Inc. All rights reserved. ** + ** ** + ** License to copy and use this software is granted provided that ** + ** it is identified as the "RSA Data Security, Inc. MD5 Message- ** + ** Digest Algorithm" in all material mentioning or referencing this ** + ** software or this function. ** + ** ** + ** License is also granted to make and use derivative works ** + ** provided that such works are identified as "derived from the RSA ** + ** Data Security, Inc. MD5 Message-Digest Algorithm" in all ** + ** material mentioning or referencing the derived work. ** + ** ** + ** RSA Data Security, Inc. makes no representations concerning ** + ** either the merchantability of this software or the suitability ** + ** of this software for any particular purpose. It is provided "as ** + ** is" without express or implied warranty of any kind. ** + ** ** + ** These notices must be retained in any copies of any part of this ** + ** documentation and/or software. ** + *********************************************************************** + */ + +#ifndef MD5_H +#define MD5_H + +/* Data structure for MD5 (Message-Digest) computation */ +typedef struct { + u32_t i[2]; /* number of _bits_ handled mod 2^64 */ + u32_t buf[4]; /* scratch buffer */ + unsigned char in[64]; /* input buffer */ + unsigned char digest[16]; /* actual digest after MD5Final call */ +} MD5_CTX; + +void MD5Init (MD5_CTX *mdContext); +void MD5Update (MD5_CTX *mdContext, unsigned char *inBuf, unsigned int inLen); +void MD5Final (unsigned char hash[], MD5_CTX *mdContext); + +#endif /* MD5_H */ diff --git a/20080212/Demo/Common/ethernet/lwIP/netif/ppp/pap.c b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/pap.c new file mode 100644 index 000000000..4b105ef3e --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/pap.c @@ -0,0 +1,608 @@ +/***************************************************************************** +* pap.c - Network Password Authentication Protocol program file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1997 by Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-12-12 Guy Lancaster , Global Election Systems Inc. +* Original. +*****************************************************************************/ +/* + * upap.c - User/Password Authentication Protocol. + * + * Copyright (c) 1989 Carnegie Mellon University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Carnegie Mellon University. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +#include "ppp.h" +#include "auth.h" +#include "pap.h" +#include "pppdebug.h" + + +#if PAP_SUPPORT > 0 + +/***********************************/ +/*** LOCAL FUNCTION DECLARATIONS ***/ +/***********************************/ +/* + * Protocol entry points. + */ +static void upap_init (int); +static void upap_lowerup (int); +static void upap_lowerdown (int); +static void upap_input (int, u_char *, int); +static void upap_protrej (int); + +static void upap_timeout (void *); +static void upap_reqtimeout (void *); +static void upap_rauthreq (upap_state *, u_char *, int, int); +static void upap_rauthack (upap_state *, u_char *, int, int); +static void upap_rauthnak (upap_state *, u_char *, int, int); +static void upap_sauthreq (upap_state *); +static void upap_sresp (upap_state *, u_char, u_char, char *, int); + + + + +/******************************/ +/*** PUBLIC DATA STRUCTURES ***/ +/******************************/ +struct protent pap_protent = { + PPP_PAP, + upap_init, + upap_input, + upap_protrej, + upap_lowerup, + upap_lowerdown, + NULL, + NULL, +#if 0 + upap_printpkt, + NULL, +#endif + 1, + "PAP", +#if 0 + NULL, + NULL, + NULL +#endif +}; + +upap_state upap[NUM_PPP]; /* UPAP state; one for each unit */ + + + +/***********************************/ +/*** PUBLIC FUNCTION DEFINITIONS ***/ +/***********************************/ +/* + * Set the default login name and password for the pap sessions + */ +void upap_setloginpasswd(int unit, const char *luser, const char *lpassword) +{ + upap_state *u = &upap[unit]; + + /* Save the username and password we're given */ + u->us_user = luser; + u->us_userlen = strlen(luser); + u->us_passwd = lpassword; + u->us_passwdlen = strlen(lpassword); +} + + +/* + * upap_authwithpeer - Authenticate us with our peer (start client). + * + * Set new state and send authenticate's. + */ +void upap_authwithpeer(int unit, char *user, char *password) +{ + upap_state *u = &upap[unit]; + + UPAPDEBUG((LOG_INFO, "upap_authwithpeer: %d user=%s password=%s s=%d\n", + unit, user, password, u->us_clientstate)); + + upap_setloginpasswd(unit, user, password); + + u->us_transmits = 0; + + /* Lower layer up yet? */ + if (u->us_clientstate == UPAPCS_INITIAL || + u->us_clientstate == UPAPCS_PENDING) { + u->us_clientstate = UPAPCS_PENDING; + return; + } + + upap_sauthreq(u); /* Start protocol */ +} + + +/* + * upap_authpeer - Authenticate our peer (start server). + * + * Set new state. + */ +void upap_authpeer(int unit) +{ + upap_state *u = &upap[unit]; + + /* Lower layer up yet? */ + if (u->us_serverstate == UPAPSS_INITIAL || + u->us_serverstate == UPAPSS_PENDING) { + u->us_serverstate = UPAPSS_PENDING; + return; + } + + u->us_serverstate = UPAPSS_LISTEN; + if (u->us_reqtimeout > 0) + TIMEOUT(upap_reqtimeout, u, u->us_reqtimeout); +} + + + +/**********************************/ +/*** LOCAL FUNCTION DEFINITIONS ***/ +/**********************************/ +/* + * upap_init - Initialize a UPAP unit. + */ +static void upap_init(int unit) +{ + upap_state *u = &upap[unit]; + + UPAPDEBUG((LOG_INFO, "upap_init: %d\n", unit)); + u->us_unit = unit; + u->us_user = NULL; + u->us_userlen = 0; + u->us_passwd = NULL; + u->us_passwdlen = 0; + u->us_clientstate = UPAPCS_INITIAL; + u->us_serverstate = UPAPSS_INITIAL; + u->us_id = 0; + u->us_timeouttime = UPAP_DEFTIMEOUT; + u->us_maxtransmits = 10; + u->us_reqtimeout = UPAP_DEFREQTIME; +} + +/* + * upap_timeout - Retransmission timer for sending auth-reqs expired. + */ +static void upap_timeout(void *arg) +{ + upap_state *u = (upap_state *) arg; + + UPAPDEBUG((LOG_INFO, "upap_timeout: %d timeout %d expired s=%d\n", + u->us_unit, u->us_timeouttime, u->us_clientstate)); + + if (u->us_clientstate != UPAPCS_AUTHREQ) + return; + + if (u->us_transmits >= u->us_maxtransmits) { + /* give up in disgust */ + UPAPDEBUG((LOG_ERR, "No response to PAP authenticate-requests\n")); + u->us_clientstate = UPAPCS_BADAUTH; + auth_withpeer_fail(u->us_unit, PPP_PAP); + return; + } + + upap_sauthreq(u); /* Send Authenticate-Request */ +} + + +/* + * upap_reqtimeout - Give up waiting for the peer to send an auth-req. + */ +static void upap_reqtimeout(void *arg) +{ + upap_state *u = (upap_state *) arg; + + if (u->us_serverstate != UPAPSS_LISTEN) + return; /* huh?? */ + + auth_peer_fail(u->us_unit, PPP_PAP); + u->us_serverstate = UPAPSS_BADAUTH; +} + + +/* + * upap_lowerup - The lower layer is up. + * + * Start authenticating if pending. + */ +static void upap_lowerup(int unit) +{ + upap_state *u = &upap[unit]; + + UPAPDEBUG((LOG_INFO, "upap_lowerup: %d s=%d\n", unit, u->us_clientstate)); + + if (u->us_clientstate == UPAPCS_INITIAL) + u->us_clientstate = UPAPCS_CLOSED; + else if (u->us_clientstate == UPAPCS_PENDING) { + upap_sauthreq(u); /* send an auth-request */ + } + + if (u->us_serverstate == UPAPSS_INITIAL) + u->us_serverstate = UPAPSS_CLOSED; + else if (u->us_serverstate == UPAPSS_PENDING) { + u->us_serverstate = UPAPSS_LISTEN; + if (u->us_reqtimeout > 0) + TIMEOUT(upap_reqtimeout, u, u->us_reqtimeout); + } +} + + +/* + * upap_lowerdown - The lower layer is down. + * + * Cancel all timeouts. + */ +static void upap_lowerdown(int unit) +{ + upap_state *u = &upap[unit]; + + UPAPDEBUG((LOG_INFO, "upap_lowerdown: %d s=%d\n", unit, u->us_clientstate)); + + if (u->us_clientstate == UPAPCS_AUTHREQ) /* Timeout pending? */ + UNTIMEOUT(upap_timeout, u); /* Cancel timeout */ + if (u->us_serverstate == UPAPSS_LISTEN && u->us_reqtimeout > 0) + UNTIMEOUT(upap_reqtimeout, u); + + u->us_clientstate = UPAPCS_INITIAL; + u->us_serverstate = UPAPSS_INITIAL; +} + + +/* + * upap_protrej - Peer doesn't speak this protocol. + * + * This shouldn't happen. In any case, pretend lower layer went down. + */ +static void upap_protrej(int unit) +{ + upap_state *u = &upap[unit]; + + if (u->us_clientstate == UPAPCS_AUTHREQ) { + UPAPDEBUG((LOG_ERR, "PAP authentication failed due to protocol-reject\n")); + auth_withpeer_fail(unit, PPP_PAP); + } + if (u->us_serverstate == UPAPSS_LISTEN) { + UPAPDEBUG((LOG_ERR, "PAP authentication of peer failed (protocol-reject)\n")); + auth_peer_fail(unit, PPP_PAP); + } + upap_lowerdown(unit); +} + + +/* + * upap_input - Input UPAP packet. + */ +static void upap_input(int unit, u_char *inpacket, int l) +{ + upap_state *u = &upap[unit]; + u_char *inp; + u_char code, id; + int len; + + /* + * Parse header (code, id and length). + * If packet too short, drop it. + */ + inp = inpacket; + if (l < UPAP_HEADERLEN) { + UPAPDEBUG((LOG_INFO, "pap_input: rcvd short header.\n")); + return; + } + GETCHAR(code, inp); + GETCHAR(id, inp); + GETSHORT(len, inp); + if (len < UPAP_HEADERLEN) { + UPAPDEBUG((LOG_INFO, "pap_input: rcvd illegal length.\n")); + return; + } + if (len > l) { + UPAPDEBUG((LOG_INFO, "pap_input: rcvd short packet.\n")); + return; + } + len -= UPAP_HEADERLEN; + + /* + * Action depends on code. + */ + switch (code) { + case UPAP_AUTHREQ: + upap_rauthreq(u, inp, id, len); + break; + + case UPAP_AUTHACK: + upap_rauthack(u, inp, id, len); + break; + + case UPAP_AUTHNAK: + upap_rauthnak(u, inp, id, len); + break; + + default: /* XXX Need code reject */ + break; + } +} + + +/* + * upap_rauth - Receive Authenticate. + */ +static void upap_rauthreq( + upap_state *u, + u_char *inp, + int id, + int len +) +{ + u_char ruserlen, rpasswdlen; + char *ruser, *rpasswd; + int retcode; + char *msg; + int msglen; + + UPAPDEBUG((LOG_INFO, "pap_rauth: Rcvd id %d.\n", id)); + + if (u->us_serverstate < UPAPSS_LISTEN) + return; + + /* + * If we receive a duplicate authenticate-request, we are + * supposed to return the same status as for the first request. + */ + if (u->us_serverstate == UPAPSS_OPEN) { + upap_sresp(u, UPAP_AUTHACK, id, "", 0); /* return auth-ack */ + return; + } + if (u->us_serverstate == UPAPSS_BADAUTH) { + upap_sresp(u, UPAP_AUTHNAK, id, "", 0); /* return auth-nak */ + return; + } + + /* + * Parse user/passwd. + */ + if (len < sizeof (u_char)) { + UPAPDEBUG((LOG_INFO, "pap_rauth: rcvd short packet.\n")); + return; + } + GETCHAR(ruserlen, inp); + len -= sizeof (u_char) + ruserlen + sizeof (u_char); + if (len < 0) { + UPAPDEBUG((LOG_INFO, "pap_rauth: rcvd short packet.\n")); + return; + } + ruser = (char *) inp; + INCPTR(ruserlen, inp); + GETCHAR(rpasswdlen, inp); + if (len < rpasswdlen) { + UPAPDEBUG((LOG_INFO, "pap_rauth: rcvd short packet.\n")); + return; + } + rpasswd = (char *) inp; + + /* + * Check the username and password given. + */ + retcode = check_passwd(u->us_unit, ruser, ruserlen, rpasswd, + rpasswdlen, &msg, &msglen); + BZERO(rpasswd, rpasswdlen); + + upap_sresp(u, retcode, id, msg, msglen); + + if (retcode == UPAP_AUTHACK) { + u->us_serverstate = UPAPSS_OPEN; + auth_peer_success(u->us_unit, PPP_PAP, ruser, ruserlen); + } else { + u->us_serverstate = UPAPSS_BADAUTH; + auth_peer_fail(u->us_unit, PPP_PAP); + } + + if (u->us_reqtimeout > 0) + UNTIMEOUT(upap_reqtimeout, u); +} + + +/* + * upap_rauthack - Receive Authenticate-Ack. + */ +static void upap_rauthack( + upap_state *u, + u_char *inp, + int id, + int len +) +{ + u_char msglen; + char *msg; + + UPAPDEBUG((LOG_INFO, "pap_rauthack: Rcvd id %d s=%d\n", id, u->us_clientstate)); + + if (u->us_clientstate != UPAPCS_AUTHREQ) /* XXX */ + return; + + /* + * Parse message. + */ + if (len < sizeof (u_char)) { + UPAPDEBUG((LOG_INFO, "pap_rauthack: rcvd short packet.\n")); + return; + } + GETCHAR(msglen, inp); + len -= sizeof (u_char); + if (len < msglen) { + UPAPDEBUG((LOG_INFO, "pap_rauthack: rcvd short packet.\n")); + return; + } + msg = (char *) inp; + PRINTMSG(msg, msglen); + + u->us_clientstate = UPAPCS_OPEN; + + auth_withpeer_success(u->us_unit, PPP_PAP); +} + + +/* + * upap_rauthnak - Receive Authenticate-Nakk. + */ +static void upap_rauthnak( + upap_state *u, + u_char *inp, + int id, + int len +) +{ + u_char msglen; + char *msg; + + UPAPDEBUG((LOG_INFO, "pap_rauthnak: Rcvd id %d s=%d\n", id, u->us_clientstate)); + + if (u->us_clientstate != UPAPCS_AUTHREQ) /* XXX */ + return; + + /* + * Parse message. + */ + if (len < sizeof (u_char)) { + UPAPDEBUG((LOG_INFO, "pap_rauthnak: rcvd short packet.\n")); + return; + } + GETCHAR(msglen, inp); + len -= sizeof (u_char); + if (len < msglen) { + UPAPDEBUG((LOG_INFO, "pap_rauthnak: rcvd short packet.\n")); + return; + } + msg = (char *) inp; + PRINTMSG(msg, msglen); + + u->us_clientstate = UPAPCS_BADAUTH; + + UPAPDEBUG((LOG_ERR, "PAP authentication failed\n")); + auth_withpeer_fail(u->us_unit, PPP_PAP); +} + + +/* + * upap_sauthreq - Send an Authenticate-Request. + */ +static void upap_sauthreq(upap_state *u) +{ + u_char *outp; + int outlen; + + outlen = UPAP_HEADERLEN + 2 * sizeof (u_char) + + u->us_userlen + u->us_passwdlen; + outp = outpacket_buf[u->us_unit]; + + MAKEHEADER(outp, PPP_PAP); + + PUTCHAR(UPAP_AUTHREQ, outp); + PUTCHAR(++u->us_id, outp); + PUTSHORT(outlen, outp); + PUTCHAR(u->us_userlen, outp); + BCOPY(u->us_user, outp, u->us_userlen); + INCPTR(u->us_userlen, outp); + PUTCHAR(u->us_passwdlen, outp); + BCOPY(u->us_passwd, outp, u->us_passwdlen); + + pppWrite(u->us_unit, outpacket_buf[u->us_unit], outlen + PPP_HDRLEN); + + UPAPDEBUG((LOG_INFO, "pap_sauth: Sent id %d\n", u->us_id)); + + TIMEOUT(upap_timeout, u, u->us_timeouttime); + ++u->us_transmits; + u->us_clientstate = UPAPCS_AUTHREQ; +} + + +/* + * upap_sresp - Send a response (ack or nak). + */ +static void upap_sresp( + upap_state *u, + u_char code, + u_char id, + char *msg, + int msglen +) +{ + u_char *outp; + int outlen; + + outlen = UPAP_HEADERLEN + sizeof (u_char) + msglen; + outp = outpacket_buf[u->us_unit]; + MAKEHEADER(outp, PPP_PAP); + + PUTCHAR(code, outp); + PUTCHAR(id, outp); + PUTSHORT(outlen, outp); + PUTCHAR(msglen, outp); + BCOPY(msg, outp, msglen); + pppWrite(u->us_unit, outpacket_buf[u->us_unit], outlen + PPP_HDRLEN); + + UPAPDEBUG((LOG_INFO, "pap_sresp: Sent code %d, id %d s=%d\n", + code, id, u->us_clientstate)); +} + +#if 0 +/* + * upap_printpkt - print the contents of a PAP packet. + */ +static int upap_printpkt( + u_char *p, + int plen, + void (*printer) (void *, char *, ...), + void *arg +) +{ + (void)p; + (void)plen; + (void)printer; + (void)arg; + return 0; +} +#endif + +#endif /* PAP_SUPPORT */ + diff --git a/20080212/Demo/Common/ethernet/lwIP/netif/ppp/pap.h b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/pap.h new file mode 100644 index 000000000..59eb2c71e --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/pap.h @@ -0,0 +1,129 @@ +/***************************************************************************** +* pap.h - PPP Password Authentication Protocol header file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1997 Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-12-04 Guy Lancaster , Global Election Systems Inc. +* Original derived from BSD codes. +*****************************************************************************/ +/* + * upap.h - User/Password Authentication Protocol definitions. + * + * Copyright (c) 1989 Carnegie Mellon University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Carnegie Mellon University. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + + +#ifndef PAP_H +#define PAP_H + +/************************* +*** PUBLIC DEFINITIONS *** +*************************/ +/* + * Packet header = Code, id, length. + */ +#define UPAP_HEADERLEN (sizeof (u_char) + sizeof (u_char) + sizeof (u_short)) + + +/* + * UPAP codes. + */ +#define UPAP_AUTHREQ 1 /* Authenticate-Request */ +#define UPAP_AUTHACK 2 /* Authenticate-Ack */ +#define UPAP_AUTHNAK 3 /* Authenticate-Nak */ + +/* + * Client states. + */ +#define UPAPCS_INITIAL 0 /* Connection down */ +#define UPAPCS_CLOSED 1 /* Connection up, haven't requested auth */ +#define UPAPCS_PENDING 2 /* Connection down, have requested auth */ +#define UPAPCS_AUTHREQ 3 /* We've sent an Authenticate-Request */ +#define UPAPCS_OPEN 4 /* We've received an Ack */ +#define UPAPCS_BADAUTH 5 /* We've received a Nak */ + +/* + * Server states. + */ +#define UPAPSS_INITIAL 0 /* Connection down */ +#define UPAPSS_CLOSED 1 /* Connection up, haven't requested auth */ +#define UPAPSS_PENDING 2 /* Connection down, have requested auth */ +#define UPAPSS_LISTEN 3 /* Listening for an Authenticate */ +#define UPAPSS_OPEN 4 /* We've sent an Ack */ +#define UPAPSS_BADAUTH 5 /* We've sent a Nak */ + + +/************************ +*** PUBLIC DATA TYPES *** +************************/ + +/* + * Each interface is described by upap structure. + */ +typedef struct upap_state { + int us_unit; /* Interface unit number */ + const char *us_user; /* User */ + int us_userlen; /* User length */ + const char *us_passwd; /* Password */ + int us_passwdlen; /* Password length */ + int us_clientstate; /* Client state */ + int us_serverstate; /* Server state */ + u_char us_id; /* Current id */ + int us_timeouttime; /* Timeout (seconds) for auth-req retrans. */ + int us_transmits; /* Number of auth-reqs sent */ + int us_maxtransmits; /* Maximum number of auth-reqs to send */ + int us_reqtimeout; /* Time to wait for auth-req from peer */ +} upap_state; + + +/*********************** +*** PUBLIC FUNCTIONS *** +***********************/ + +extern upap_state upap[]; + +void upap_setloginpasswd(int unit, const char *luser, const char *lpassword); +void upap_authwithpeer (int, char *, char *); +void upap_authpeer (int); + +extern struct protent pap_protent; + +#endif /* PAP_H */ + diff --git a/20080212/Demo/Common/ethernet/lwIP/netif/ppp/ppp.c b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/ppp.c new file mode 100644 index 000000000..afd4116bc --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/ppp.c @@ -0,0 +1,1631 @@ +/***************************************************************************** +* ppp.c - Network Point to Point Protocol program file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1997 by Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-11-05 Guy Lancaster , Global Election Systems Inc. +* Original. +*****************************************************************************/ + +/* + * ppp_defs.h - PPP definitions. + * + * if_pppvar.h - private structures and declarations for PPP. + * + * Copyright (c) 1994 The Australian National University. + * All rights reserved. + * + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, provided that the above copyright + * notice appears in all copies. This software is provided without any + * warranty, express or implied. The Australian National University + * makes no representations about the suitability of this software for + * any purpose. + * + * IN NO EVENT SHALL THE AUSTRALIAN NATIONAL UNIVERSITY BE LIABLE TO ANY + * PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES + * ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF + * THE AUSTRALIAN NATIONAL UNIVERSITY HAVE BEEN ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * THE AUSTRALIAN NATIONAL UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS + * ON AN "AS IS" BASIS, AND THE AUSTRALIAN NATIONAL UNIVERSITY HAS NO + * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, + * OR MODIFICATIONS. + */ + +/* + * if_ppp.h - Point-to-Point Protocol definitions. + * + * Copyright (c) 1989 Carnegie Mellon University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Carnegie Mellon University. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +#include + +#include "ppp.h" +#if PPP_SUPPORT > 0 +#include "randm.h" +#include "fsm.h" +#if PAP_SUPPORT > 0 +#include "pap.h" +#endif +#if CHAP_SUPPORT > 0 +#include "chap.h" +#endif +#include "ipcp.h" +#include "lcp.h" +#include "magic.h" +#include "auth.h" +#if VJ_SUPPORT > 0 +#include "vj.h" +#endif + +#include "pppdebug.h" + +/*************************/ +/*** LOCAL DEFINITIONS ***/ +/*************************/ + +/* + * The basic PPP frame. + */ +#define PPP_ADDRESS(p) (((u_char *)(p))[0]) +#define PPP_CONTROL(p) (((u_char *)(p))[1]) +#define PPP_PROTOCOL(p) ((((u_char *)(p))[2] << 8) + ((u_char *)(p))[3]) + +/* PPP packet parser states. Current state indicates operation yet to be + * completed. */ +typedef enum { + PDIDLE = 0, /* Idle state - waiting. */ + PDSTART, /* Process start flag. */ + PDADDRESS, /* Process address field. */ + PDCONTROL, /* Process control field. */ + PDPROTOCOL1, /* Process protocol field 1. */ + PDPROTOCOL2, /* Process protocol field 2. */ + PDDATA /* Process data byte. */ +} PPPDevStates; + +#define ESCAPE_P(accm, c) ((accm)[(c) >> 3] & pppACCMMask[c & 0x07]) + +/************************/ +/*** LOCAL DATA TYPES ***/ +/************************/ +/* + * PPP interface control block. + */ +typedef struct PPPControl_s { + char openFlag; /* True when in use. */ + char oldFrame; /* Old framing character for fd. */ + sio_fd_t fd; /* File device ID of port. */ + int kill_link; /* Shut the link down. */ + int sig_hup; /* Carrier lost. */ + int if_up; /* True when the interface is up. */ + int errCode; /* Code indicating why interface is down. */ + struct pbuf *inHead, *inTail; /* The input packet. */ + PPPDevStates inState; /* The input process state. */ + char inEscaped; /* Escape next character. */ + u16_t inProtocol; /* The input protocol code. */ + u16_t inFCS; /* Input Frame Check Sequence value. */ + int mtu; /* Peer's mru */ + int pcomp; /* Does peer accept protocol compression? */ + int accomp; /* Does peer accept addr/ctl compression? */ + u_long lastXMit; /* Time of last transmission. */ + ext_accm inACCM; /* Async-Ctl-Char-Map for input. */ + ext_accm outACCM; /* Async-Ctl-Char-Map for output. */ +#if VJ_SUPPORT > 0 + int vjEnabled; /* Flag indicating VJ compression enabled. */ + struct vjcompress vjComp; /* Van Jabobsen compression header. */ +#endif + + struct netif netif; + + struct ppp_addrs addrs; + + void (*linkStatusCB)(void *ctx, int errCode, void *arg); + void *linkStatusCtx; + +} PPPControl; + + +/* + * Ioctl definitions. + */ + +struct npioctl { + int protocol; /* PPP procotol, e.g. PPP_IP */ + enum NPmode mode; +}; + + + +/***********************************/ +/*** LOCAL FUNCTION DECLARATIONS ***/ +/***********************************/ +static void pppMain(void *pd); +static void pppDrop(PPPControl *pc); +static void pppInProc(int pd, u_char *s, int l); + + +/******************************/ +/*** PUBLIC DATA STRUCTURES ***/ +/******************************/ +u_long subnetMask; + +static PPPControl pppControl[NUM_PPP]; /* The PPP interface control blocks. */ + +/* + * PPP Data Link Layer "protocol" table. + * One entry per supported protocol. + * The last entry must be NULL. + */ +struct protent *ppp_protocols[] = { + &lcp_protent, +#if PAP_SUPPORT > 0 + &pap_protent, +#endif +#if CHAP_SUPPORT > 0 + &chap_protent, +#endif +#if CBCP_SUPPORT > 0 + &cbcp_protent, +#endif + &ipcp_protent, +#if CCP_SUPPORT > 0 + &ccp_protent, +#endif + NULL +}; + + +/* + * Buffers for outgoing packets. This must be accessed only from the appropriate + * PPP task so that it doesn't need to be protected to avoid collisions. + */ +u_char outpacket_buf[NUM_PPP][PPP_MRU+PPP_HDRLEN]; + + +/*****************************/ +/*** LOCAL DATA STRUCTURES ***/ +/*****************************/ + +/* + * FCS lookup table as calculated by genfcstab. + */ +static const u_short fcstab[256] = { + 0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf, + 0x8c48, 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7, + 0x1081, 0x0108, 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e, + 0x9cc9, 0x8d40, 0xbfdb, 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876, + 0x2102, 0x308b, 0x0210, 0x1399, 0x6726, 0x76af, 0x4434, 0x55bd, + 0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, 0xfae7, 0xc87c, 0xd9f5, + 0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, 0x54b5, 0x453c, + 0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, 0xc974, + 0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb, + 0xce4c, 0xdfc5, 0xed5e, 0xfcd7, 0x8868, 0x99e1, 0xab7a, 0xbaf3, + 0x5285, 0x430c, 0x7197, 0x601e, 0x14a1, 0x0528, 0x37b3, 0x263a, + 0xdecd, 0xcf44, 0xfddf, 0xec56, 0x98e9, 0x8960, 0xbbfb, 0xaa72, + 0x6306, 0x728f, 0x4014, 0x519d, 0x2522, 0x34ab, 0x0630, 0x17b9, + 0xef4e, 0xfec7, 0xcc5c, 0xddd5, 0xa96a, 0xb8e3, 0x8a78, 0x9bf1, + 0x7387, 0x620e, 0x5095, 0x411c, 0x35a3, 0x242a, 0x16b1, 0x0738, + 0xffcf, 0xee46, 0xdcdd, 0xcd54, 0xb9eb, 0xa862, 0x9af9, 0x8b70, + 0x8408, 0x9581, 0xa71a, 0xb693, 0xc22c, 0xd3a5, 0xe13e, 0xf0b7, + 0x0840, 0x19c9, 0x2b52, 0x3adb, 0x4e64, 0x5fed, 0x6d76, 0x7cff, + 0x9489, 0x8500, 0xb79b, 0xa612, 0xd2ad, 0xc324, 0xf1bf, 0xe036, + 0x18c1, 0x0948, 0x3bd3, 0x2a5a, 0x5ee5, 0x4f6c, 0x7df7, 0x6c7e, + 0xa50a, 0xb483, 0x8618, 0x9791, 0xe32e, 0xf2a7, 0xc03c, 0xd1b5, + 0x2942, 0x38cb, 0x0a50, 0x1bd9, 0x6f66, 0x7eef, 0x4c74, 0x5dfd, + 0xb58b, 0xa402, 0x9699, 0x8710, 0xf3af, 0xe226, 0xd0bd, 0xc134, + 0x39c3, 0x284a, 0x1ad1, 0x0b58, 0x7fe7, 0x6e6e, 0x5cf5, 0x4d7c, + 0xc60c, 0xd785, 0xe51e, 0xf497, 0x8028, 0x91a1, 0xa33a, 0xb2b3, + 0x4a44, 0x5bcd, 0x6956, 0x78df, 0x0c60, 0x1de9, 0x2f72, 0x3efb, + 0xd68d, 0xc704, 0xf59f, 0xe416, 0x90a9, 0x8120, 0xb3bb, 0xa232, + 0x5ac5, 0x4b4c, 0x79d7, 0x685e, 0x1ce1, 0x0d68, 0x3ff3, 0x2e7a, + 0xe70e, 0xf687, 0xc41c, 0xd595, 0xa12a, 0xb0a3, 0x8238, 0x93b1, + 0x6b46, 0x7acf, 0x4854, 0x59dd, 0x2d62, 0x3ceb, 0x0e70, 0x1ff9, + 0xf78f, 0xe606, 0xd49d, 0xc514, 0xb1ab, 0xa022, 0x92b9, 0x8330, + 0x7bc7, 0x6a4e, 0x58d5, 0x495c, 0x3de3, 0x2c6a, 0x1ef1, 0x0f78 +}; + +/* PPP's Asynchronous-Control-Character-Map. The mask array is used + * to select the specific bit for a character. */ +static u_char pppACCMMask[] = { + 0x01, + 0x02, + 0x04, + 0x08, + 0x10, + 0x20, + 0x40, + 0x80 +}; + + +/***********************************/ +/*** PUBLIC FUNCTION DEFINITIONS ***/ +/***********************************/ +/* Initialize the PPP subsystem. */ + +struct ppp_settings ppp_settings; + +void pppInit(void) +{ + struct protent *protp; + int i, j; + + memset(&ppp_settings, 0, sizeof(ppp_settings)); + ppp_settings.usepeerdns = 1; + pppSetAuth(PPPAUTHTYPE_NONE, NULL, NULL); + + magicInit(); + + for (i = 0; i < NUM_PPP; i++) { + pppControl[i].openFlag = 0; + + subnetMask = htonl(0xffffff00); + + /* + * Initialize to the standard option set. + */ + for (j = 0; (protp = ppp_protocols[j]) != NULL; ++j) + (*protp->init)(i); + } + +#if LINK_STATS + /* Clear the statistics. */ + memset(&lwip_stats.link, 0, sizeof(lwip_stats.link)); +#endif +} + +void pppSetAuth(enum pppAuthType authType, const char *user, const char *passwd) +{ + switch(authType) { + case PPPAUTHTYPE_NONE: + default: +#ifdef LWIP_PPP_STRICT_PAP_REJECT + ppp_settings.refuse_pap = 1; +#else + /* some providers request pap and accept an empty login/pw */ + ppp_settings.refuse_pap = 0; +#endif + ppp_settings.refuse_chap = 1; + break; + case PPPAUTHTYPE_ANY: +/* Warning: Using PPPAUTHTYPE_ANY might have security consequences. + * RFC 1994 says: + * + * In practice, within or associated with each PPP server, there is a + * database which associates "user" names with authentication + * information ("secrets"). It is not anticipated that a particular + * named user would be authenticated by multiple methods. This would + * make the user vulnerable to attacks which negotiate the least secure + * method from among a set (such as PAP rather than CHAP). If the same + * secret was used, PAP would reveal the secret to be used later with + * CHAP. + * + * Instead, for each user name there should be an indication of exactly + * one method used to authenticate that user name. If a user needs to + * make use of different authentication methods under different + * circumstances, then distinct user names SHOULD be employed, each of + * which identifies exactly one authentication method. + * + */ + ppp_settings.refuse_pap = 0; + ppp_settings.refuse_chap = 0; + break; + case PPPAUTHTYPE_PAP: + ppp_settings.refuse_pap = 0; + ppp_settings.refuse_chap = 1; + break; + case PPPAUTHTYPE_CHAP: + ppp_settings.refuse_pap = 1; + ppp_settings.refuse_chap = 0; + break; + } + + if(user) { + strncpy(ppp_settings.user, user, sizeof(ppp_settings.user)-1); + ppp_settings.user[sizeof(ppp_settings.user)-1] = '\0'; + } else + ppp_settings.user[0] = '\0'; + + if(passwd) { + strncpy(ppp_settings.passwd, passwd, sizeof(ppp_settings.passwd)-1); + ppp_settings.passwd[sizeof(ppp_settings.passwd)-1] = '\0'; + } else + ppp_settings.passwd[0] = '\0'; +} + +/* Open a new PPP connection using the given I/O device. + * This initializes the PPP control block but does not + * attempt to negotiate the LCP session. If this port + * connects to a modem, the modem connection must be + * established before calling this. + * Return a new PPP connection descriptor on success or + * an error code (negative) on failure. */ +int pppOpen(sio_fd_t fd, void (*linkStatusCB)(void *ctx, int errCode, void *arg), void *linkStatusCtx) +{ + PPPControl *pc; + int pd; + + /* Find a free PPP session descriptor. Critical region? */ + for (pd = 0; pd < NUM_PPP && pppControl[pd].openFlag != 0; pd++); + if (pd >= NUM_PPP) + pd = PPPERR_OPEN; + else + pppControl[pd].openFlag = !0; + + /* Launch a deamon thread. */ + if (pd >= 0) { + + pppControl[pd].openFlag = 1; + + lcp_init(pd); + pc = &pppControl[pd]; + pc->fd = fd; + pc->kill_link = 0; + pc->sig_hup = 0; + pc->if_up = 0; + pc->errCode = 0; + pc->inState = PDIDLE; + pc->inHead = NULL; + pc->inTail = NULL; + pc->inEscaped = 0; + pc->lastXMit = 0; + +#if VJ_SUPPORT > 0 + pc->vjEnabled = 0; + vj_compress_init(&pc->vjComp); +#endif + + /* + * Default the in and out accm so that escape and flag characters + * are always escaped. + */ + memset(pc->inACCM, 0, sizeof(ext_accm)); + pc->inACCM[15] = 0x60; + memset(pc->outACCM, 0, sizeof(ext_accm)); + pc->outACCM[15] = 0x60; + + pc->linkStatusCB = linkStatusCB; + pc->linkStatusCtx = linkStatusCtx; + + sys_thread_new(pppMain, (void*)pd, PPP_THREAD_PRIO); + if(!linkStatusCB) { + while(pd >= 0 && !pc->if_up) { + sys_msleep(500); + if (lcp_phase[pd] == PHASE_DEAD) { + pppClose(pd); + if (pc->errCode) + pd = pc->errCode; + else + pd = PPPERR_CONNECT; + } + } + } + } + return pd; +} + +/* Close a PPP connection and release the descriptor. + * Any outstanding packets in the queues are dropped. + * Return 0 on success, an error code on failure. */ +int pppClose(int pd) +{ + PPPControl *pc = &pppControl[pd]; + int st = 0; + + /* Disconnect */ + pc->kill_link = !0; + pppMainWakeup(pd); + + if(!pc->linkStatusCB) { + while(st >= 0 && lcp_phase[pd] != PHASE_DEAD) { + sys_msleep(500); + break; + } + } + return st; +} + +/* This function is called when carrier is lost on the PPP channel. */ +void pppSigHUP(int pd) +{ + PPPControl *pc = &pppControl[pd]; + + pc->sig_hup = 1; + pppMainWakeup(pd); +} + +static void nPut(PPPControl *pc, struct pbuf *nb) +{ + struct pbuf *b; + int c; + + for(b = nb; b != NULL; b = b->next) { + if((c = sio_write(pc->fd, b->payload, b->len)) != b->len) { + PPPDEBUG((LOG_WARNING, + "PPP nPut: incomplete sio_write(%d,, %u) = %d\n", pc->fd, b->len, c)); +#if LINK_STATS + lwip_stats.link.err++; +#endif /* LINK_STATS */ + pc->lastXMit = 0; /* prepend PPP_FLAG to next packet */ + break; + } + } + pbuf_free(nb); + +#if LINK_STATS + lwip_stats.link.xmit++; +#endif /* LINK_STATS */ +} + +/* + * pppAppend - append given character to end of given pbuf. If outACCM + * is not NULL and the character needs to be escaped, do so. + * If pbuf is full, append another. + * Return the current pbuf. + */ +static struct pbuf *pppAppend(u_char c, struct pbuf *nb, ext_accm *outACCM) +{ + struct pbuf *tb = nb; + + /* Make sure there is room for the character and an escape code. + * Sure we don't quite fill the buffer if the character doesn't + * get escaped but is one character worth complicating this? */ + /* Note: We assume no packet header. */ + if (nb && (PBUF_POOL_BUFSIZE - nb->len) < 2) { + tb = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL); + if (tb) { + nb->next = tb; + } +#if LINK_STATS + else { + lwip_stats.link.memerr++; + } +#endif /* LINK_STATS */ + nb = tb; + } + if (nb) { + if (outACCM && ESCAPE_P(*outACCM, c)) { + *((u_char*)nb->payload + nb->len++) = PPP_ESCAPE; + *((u_char*)nb->payload + nb->len++) = c ^ PPP_TRANS; + } + else + *((u_char*)nb->payload + nb->len++) = c; + } + + return tb; +} + +/* Send a packet on the given connection. */ +static err_t pppifOutput(struct netif *netif, struct pbuf *pb, struct ip_addr *ipaddr) +{ + int pd = (int)netif->state; + u_short protocol = PPP_IP; + PPPControl *pc = &pppControl[pd]; + u_int fcsOut = PPP_INITFCS; + struct pbuf *headMB = NULL, *tailMB = NULL, *p; + u_char c; + + (void)ipaddr; + + /* Validate parameters. */ + /* We let any protocol value go through - it can't hurt us + * and the peer will just drop it if it's not accepting it. */ + if (pd < 0 || pd >= NUM_PPP || !pc->openFlag || !pb) { + PPPDEBUG((LOG_WARNING, "pppifOutput[%d]: bad parms prot=%d pb=%p\n", + pd, protocol, pb)); +#if LINK_STATS + lwip_stats.link.opterr++; + lwip_stats.link.drop++; +#endif + return ERR_ARG; + } + + /* Check that the link is up. */ + if (lcp_phase[pd] == PHASE_DEAD) { + PPPDEBUG((LOG_ERR, "pppifOutput[%d]: link not up\n", pd)); +#if LINK_STATS + lwip_stats.link.rterr++; + lwip_stats.link.drop++; +#endif + return ERR_RTE; + } + + /* Grab an output buffer. */ + headMB = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL); + if (headMB == NULL) { + PPPDEBUG((LOG_WARNING, "pppifOutput[%d]: first alloc fail\n", pd)); +#if LINK_STATS + lwip_stats.link.memerr++; + lwip_stats.link.drop++; +#endif /* LINK_STATS */ + return ERR_MEM; + } + +#if VJ_SUPPORT > 0 + /* + * Attempt Van Jacobson header compression if VJ is configured and + * this is an IP packet. + */ + if (protocol == PPP_IP && pc->vjEnabled) { + switch (vj_compress_tcp(&pc->vjComp, pb)) { + case TYPE_IP: + /* No change... + protocol = PPP_IP_PROTOCOL; + */ + break; + case TYPE_COMPRESSED_TCP: + protocol = PPP_VJC_COMP; + break; + case TYPE_UNCOMPRESSED_TCP: + protocol = PPP_VJC_UNCOMP; + break; + default: + PPPDEBUG((LOG_WARNING, "pppifOutput[%d]: bad IP packet\n", pd)); +#if LINK_STATS + lwip_stats.link.proterr++; + lwip_stats.link.drop++; +#endif + pbuf_free(headMB); + return ERR_VAL; + } + } +#endif + + tailMB = headMB; + + /* Build the PPP header. */ + if ((sys_jiffies() - pc->lastXMit) >= PPP_MAXIDLEFLAG) + tailMB = pppAppend(PPP_FLAG, tailMB, NULL); + pc->lastXMit = sys_jiffies(); + if (!pc->accomp) { + fcsOut = PPP_FCS(fcsOut, PPP_ALLSTATIONS); + tailMB = pppAppend(PPP_ALLSTATIONS, tailMB, &pc->outACCM); + fcsOut = PPP_FCS(fcsOut, PPP_UI); + tailMB = pppAppend(PPP_UI, tailMB, &pc->outACCM); + } + if (!pc->pcomp || protocol > 0xFF) { + c = (protocol >> 8) & 0xFF; + fcsOut = PPP_FCS(fcsOut, c); + tailMB = pppAppend(c, tailMB, &pc->outACCM); + } + c = protocol & 0xFF; + fcsOut = PPP_FCS(fcsOut, c); + tailMB = pppAppend(c, tailMB, &pc->outACCM); + + /* Load packet. */ + for(p = pb; p; p = p->next) { + int n; + u_char *sPtr; + + sPtr = (u_char*)p->payload; + n = p->len; + while (n-- > 0) { + c = *sPtr++; + + /* Update FCS before checking for special characters. */ + fcsOut = PPP_FCS(fcsOut, c); + + /* Copy to output buffer escaping special characters. */ + tailMB = pppAppend(c, tailMB, &pc->outACCM); + } + } + + /* Add FCS and trailing flag. */ + c = ~fcsOut & 0xFF; + tailMB = pppAppend(c, tailMB, &pc->outACCM); + c = (~fcsOut >> 8) & 0xFF; + tailMB = pppAppend(c, tailMB, &pc->outACCM); + tailMB = pppAppend(PPP_FLAG, tailMB, NULL); + + /* If we failed to complete the packet, throw it away. */ + if (!tailMB) { + PPPDEBUG((LOG_WARNING, + "pppifOutput[%d]: Alloc err - dropping proto=%d\n", + pd, protocol)); + pbuf_free(headMB); +#if LINK_STATS + lwip_stats.link.memerr++; + lwip_stats.link.drop++; +#endif + return ERR_MEM; + } + + /* Send it. */ + PPPDEBUG((LOG_INFO, "pppifOutput[%d]: proto=0x%04X\n", pd, protocol)); + + nPut(pc, headMB); + + return ERR_OK; +} + +/* Get and set parameters for the given connection. + * Return 0 on success, an error code on failure. */ +int pppIOCtl(int pd, int cmd, void *arg) +{ + PPPControl *pc = &pppControl[pd]; + int st = 0; + + if (pd < 0 || pd >= NUM_PPP) + st = PPPERR_PARAM; + else { + switch(cmd) { + case PPPCTLG_UPSTATUS: /* Get the PPP up status. */ + if (arg) + *(int *)arg = (int)(pc->if_up); + else + st = PPPERR_PARAM; + break; + case PPPCTLS_ERRCODE: /* Set the PPP error code. */ + if (arg) + pc->errCode = *(int *)arg; + else + st = PPPERR_PARAM; + break; + case PPPCTLG_ERRCODE: /* Get the PPP error code. */ + if (arg) + *(int *)arg = (int)(pc->errCode); + else + st = PPPERR_PARAM; + break; + case PPPCTLG_FD: + if (arg) + *(sio_fd_t *)arg = pc->fd; + else + st = PPPERR_PARAM; + break; + default: + st = PPPERR_PARAM; + break; + } + } + + return st; +} + +/* + * Return the Maximum Transmission Unit for the given PPP connection. + */ +u_int pppMTU(int pd) +{ + PPPControl *pc = &pppControl[pd]; + u_int st; + + /* Validate parameters. */ + if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) + st = 0; + else + st = pc->mtu; + + return st; +} + +/* + * Write n characters to a ppp link. + * RETURN: >= 0 Number of characters written + * -1 Failed to write to device + */ +int pppWrite(int pd, const u_char *s, int n) +{ + PPPControl *pc = &pppControl[pd]; + u_char c; + u_int fcsOut = PPP_INITFCS; + struct pbuf *headMB = NULL, *tailMB; + headMB = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL); + if (headMB == NULL) { +#if LINK_STATS + lwip_stats.link.memerr++; + lwip_stats.link.proterr++; +#endif /* LINK_STATS */ + return PPPERR_ALLOC; + } + + tailMB = headMB; + + /* If the link has been idle, we'll send a fresh flag character to + * flush any noise. */ + if ((sys_jiffies() - pc->lastXMit) >= PPP_MAXIDLEFLAG) + tailMB = pppAppend(PPP_FLAG, tailMB, NULL); + pc->lastXMit = sys_jiffies(); + + /* Load output buffer. */ + while (n-- > 0) { + c = *s++; + + /* Update FCS before checking for special characters. */ + fcsOut = PPP_FCS(fcsOut, c); + + /* Copy to output buffer escaping special characters. */ + tailMB = pppAppend(c, tailMB, &pc->outACCM); + } + + /* Add FCS and trailing flag. */ + c = ~fcsOut & 0xFF; + tailMB = pppAppend(c, tailMB, &pc->outACCM); + c = (~fcsOut >> 8) & 0xFF; + tailMB = pppAppend(c, tailMB, &pc->outACCM); + tailMB = pppAppend(PPP_FLAG, tailMB, NULL); + + /* If we failed to complete the packet, throw it away. + * Otherwise send it. */ + if (!tailMB) { + PPPDEBUG((LOG_WARNING, + "pppWrite[%d]: Alloc err - dropping pbuf len=%d\n", pd, headMB->len)); +/* "pppWrite[%d]: Alloc err - dropping %d:%.*H", pd, headMB->len, LWIP_MIN(headMB->len * 2, 40), headMB->payload)); */ + pbuf_free(headMB); +#if LINK_STATS + lwip_stats.link.memerr++; + lwip_stats.link.proterr++; +#endif /* LINK_STATS */ + return PPPERR_ALLOC; + } + + PPPDEBUG((LOG_INFO, "pppWrite[%d]: len=%d\n", pd, headMB->len)); +/* "pppWrite[%d]: %d:%.*H", pd, headMB->len, LWIP_MIN(headMB->len * 2, 40), headMB->payload)); */ + nPut(pc, headMB); + + return PPPERR_NONE; +} + +/* + * ppp_send_config - configure the transmit characteristics of + * the ppp interface. + */ +void ppp_send_config( + int unit, + int mtu, + u32_t asyncmap, + int pcomp, + int accomp +) +{ + PPPControl *pc = &pppControl[unit]; + int i; + + pc->mtu = mtu; + pc->pcomp = pcomp; + pc->accomp = accomp; + + /* Load the ACCM bits for the 32 control codes. */ + for (i = 0; i < 32/8; i++) + pc->outACCM[i] = (u_char)((asyncmap >> (8 * i)) & 0xFF); + PPPDEBUG((LOG_INFO, "ppp_send_config[%d]: outACCM=%X %X %X %X\n", + unit, + pc->outACCM[0], pc->outACCM[1], pc->outACCM[2], pc->outACCM[3])); +} + + +/* + * ppp_set_xaccm - set the extended transmit ACCM for the interface. + */ +void ppp_set_xaccm(int unit, ext_accm *accm) +{ + memcpy(pppControl[unit].outACCM, accm, sizeof(ext_accm)); + PPPDEBUG((LOG_INFO, "ppp_set_xaccm[%d]: outACCM=%X %X %X %X\n", + unit, + pppControl[unit].outACCM[0], + pppControl[unit].outACCM[1], + pppControl[unit].outACCM[2], + pppControl[unit].outACCM[3])); +} + + +/* + * ppp_recv_config - configure the receive-side characteristics of + * the ppp interface. + */ +void ppp_recv_config( + int unit, + int mru, + u32_t asyncmap, + int pcomp, + int accomp +) +{ + PPPControl *pc = &pppControl[unit]; + int i; + + (void)accomp; + (void)pcomp; + (void)mru; + + /* Load the ACCM bits for the 32 control codes. */ + for (i = 0; i < 32 / 8; i++) + pc->inACCM[i] = (u_char)(asyncmap >> (i * 8)); + PPPDEBUG((LOG_INFO, "ppp_recv_config[%d]: inACCM=%X %X %X %X\n", + unit, + pc->inACCM[0], pc->inACCM[1], pc->inACCM[2], pc->inACCM[3])); +} + +#if 0 +/* + * ccp_test - ask kernel whether a given compression method + * is acceptable for use. Returns 1 if the method and parameters + * are OK, 0 if the method is known but the parameters are not OK + * (e.g. code size should be reduced), or -1 if the method is unknown. + */ +int ccp_test( + int unit, + int opt_len, + int for_transmit, + u_char *opt_ptr +) +{ + return 0; /* XXX Currently no compression. */ +} + +/* + * ccp_flags_set - inform kernel about the current state of CCP. + */ +void ccp_flags_set(int unit, int isopen, int isup) +{ + /* XXX */ +} + +/* + * ccp_fatal_error - returns 1 if decompression was disabled as a + * result of an error detected after decompression of a packet, + * 0 otherwise. This is necessary because of patent nonsense. + */ +int ccp_fatal_error(int unit) +{ + /* XXX */ + return 0; +} +#endif + +/* + * get_idle_time - return how long the link has been idle. + */ +int get_idle_time(int u, struct ppp_idle *ip) +{ + /* XXX */ + (void)u; + (void)ip; + + return 0; +} + + +/* + * Return user specified netmask, modified by any mask we might determine + * for address `addr' (in network byte order). + * Here we scan through the system's list of interfaces, looking for + * any non-point-to-point interfaces which might appear to be on the same + * network as `addr'. If we find any, we OR in their netmask to the + * user-specified netmask. + */ +u32_t GetMask(u32_t addr) +{ + u32_t mask, nmask; + + htonl(addr); + if (IN_CLASSA(addr)) /* determine network mask for address class */ + nmask = IN_CLASSA_NET; + else if (IN_CLASSB(addr)) + nmask = IN_CLASSB_NET; + else + nmask = IN_CLASSC_NET; + /* class D nets are disallowed by bad_ip_adrs */ + mask = subnetMask | htonl(nmask); + + /* XXX + * Scan through the system's network interfaces. + * Get each netmask and OR them into our mask. + */ + + return mask; +} + +/* + * sifvjcomp - config tcp header compression + */ +int sifvjcomp( + int pd, + int vjcomp, + int cidcomp, + int maxcid +) +{ +#if VJ_SUPPORT > 0 + PPPControl *pc = &pppControl[pd]; + + pc->vjEnabled = vjcomp; + pc->vjComp.compressSlot = cidcomp; + pc->vjComp.maxSlotIndex = maxcid; + PPPDEBUG((LOG_INFO, "sifvjcomp: VJ compress enable=%d slot=%d max slot=%d\n", + vjcomp, cidcomp, maxcid)); +#endif + + return 0; +} + +/* + * pppifNetifInit - netif init callback + */ +static err_t pppifNetifInit(struct netif *netif) +{ + netif->name[0] = 'p'; + netif->name[1] = 'p'; + netif->output = pppifOutput; + netif->mtu = pppMTU((int)netif->state); + return ERR_OK; +} + + +/* + * sifup - Config the interface up and enable IP packets to pass. + */ +int sifup(int pd) +{ + PPPControl *pc = &pppControl[pd]; + int st = 1; + + if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) { + st = 0; + PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd)); + } else { + netif_remove(&pc->netif); + if (netif_add(&pc->netif, &pc->addrs.our_ipaddr, &pc->addrs.netmask, &pc->addrs.his_ipaddr, (void *)pd, pppifNetifInit, ip_input)) { + + netif_set_up(&pc->netif); + pc->if_up = 1; + pc->errCode = PPPERR_NONE; + + PPPDEBUG((LOG_DEBUG, "sifup: unit %d: linkStatusCB=%lx errCode=%d\n", pd, pc->linkStatusCB, pc->errCode)); + if(pc->linkStatusCB) + pc->linkStatusCB(pc->linkStatusCtx, pc->errCode, &pc->addrs); + } else { + st = 0; + PPPDEBUG((LOG_ERR, "sifup[%d]: netif_add failed\n", pd)); + } + } + + return st; +} + +/* + * sifnpmode - Set the mode for handling packets for a given NP. + */ +int sifnpmode(int u, int proto, enum NPmode mode) +{ + (void)u; + (void)proto; + (void)mode; + return 0; +} + +/* + * sifdown - Config the interface down and disable IP. + */ +int sifdown(int pd) +{ + PPPControl *pc = &pppControl[pd]; + int st = 1; + + if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) { + st = 0; + PPPDEBUG((LOG_WARNING, "sifdown[%d]: bad parms\n", pd)); + } else { + pc->if_up = 0; + netif_remove(&pc->netif); + PPPDEBUG((LOG_DEBUG, "sifdown: unit %d: linkStatusCB=%lx errCode=%d\n", pd, pc->linkStatusCB, pc->errCode)); + if(pc->linkStatusCB) + pc->linkStatusCB(pc->linkStatusCtx, PPPERR_CONNECT, NULL); + } + return st; +} + +/* + * sifaddr - Config the interface IP addresses and netmask. + */ +int sifaddr( + int pd, /* Interface unit ??? */ + u32_t o, /* Our IP address ??? */ + u32_t h, /* His IP address ??? */ + u32_t m, /* IP subnet mask ??? */ + u32_t ns1, /* Primary DNS */ + u32_t ns2 /* Secondary DNS */ +) +{ + PPPControl *pc = &pppControl[pd]; + int st = 1; + + if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) { + st = 0; + PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd)); + } else { + memcpy(&pc->addrs.our_ipaddr, &o, sizeof(o)); + memcpy(&pc->addrs.his_ipaddr, &h, sizeof(h)); + memcpy(&pc->addrs.netmask, &m, sizeof(m)); + memcpy(&pc->addrs.dns1, &ns1, sizeof(ns1)); + memcpy(&pc->addrs.dns2, &ns2, sizeof(ns2)); + } + return st; +} + +/* + * cifaddr - Clear the interface IP addresses, and delete routes + * through the interface if possible. + */ +int cifaddr( + int pd, /* Interface unit ??? */ + u32_t o, /* Our IP address ??? */ + u32_t h /* IP broadcast address ??? */ +) +{ + PPPControl *pc = &pppControl[pd]; + int st = 1; + + (void)o; + (void)h; + if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) { + st = 0; + PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd)); + } else { + IP4_ADDR(&pc->addrs.our_ipaddr, 0,0,0,0); + IP4_ADDR(&pc->addrs.his_ipaddr, 0,0,0,0); + IP4_ADDR(&pc->addrs.netmask, 255,255,255,0); + IP4_ADDR(&pc->addrs.dns1, 0,0,0,0); + IP4_ADDR(&pc->addrs.dns2, 0,0,0,0); + } + return st; +} + +/* + * sifdefaultroute - assign a default route through the address given. + */ +int sifdefaultroute(int pd, u32_t l, u32_t g) +{ + PPPControl *pc = &pppControl[pd]; + int st = 1; + + (void)l; + (void)g; + if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) { + st = 0; + PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd)); + } else { + netif_set_default(&pc->netif); + } + + /* TODO: check how PPP handled the netMask, previously not set by ipSetDefault */ + + return st; +} + +/* + * cifdefaultroute - delete a default route through the address given. + */ +int cifdefaultroute(int pd, u32_t l, u32_t g) +{ + PPPControl *pc = &pppControl[pd]; + int st = 1; + + (void)l; + (void)g; + if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) { + st = 0; + PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd)); + } else { + netif_set_default(NULL); + } + + return st; +} + +void +pppMainWakeup(int pd) +{ + PPPDEBUG((LOG_DEBUG, "pppMainWakeup: unit %d\n", pd)); + sio_read_abort(pppControl[pd].fd); +} + +/* these callbacks are necessary because lcp_* functions + must be called in the same context as pppInput(), + namely the tcpip_thread(), essentially because + they manipulate timeouts which are thread-private +*/ + +static void +pppStartCB(void *arg) +{ + int pd = (int)arg; + + PPPDEBUG((LOG_DEBUG, "pppStartCB: unit %d\n", pd)); + lcp_lowerup(pd); + lcp_open(pd); /* Start protocol */ +} + +static void +pppStopCB(void *arg) +{ + int pd = (int)arg; + + PPPDEBUG((LOG_DEBUG, "pppStopCB: unit %d\n", pd)); + lcp_close(pd, "User request"); +} + +static void +pppHupCB(void *arg) +{ + int pd = (int)arg; + + PPPDEBUG((LOG_DEBUG, "pppHupCB: unit %d\n", pd)); + lcp_lowerdown(pd); + link_terminated(pd); +} +/**********************************/ +/*** LOCAL FUNCTION DEFINITIONS ***/ +/**********************************/ +/* The main PPP process function. This implements the state machine according + * to section 4 of RFC 1661: The Point-To-Point Protocol. */ +static void pppMain(void *arg) +{ + int pd = (int)arg; + struct pbuf *p; + PPPControl* pc; + + pc = &pppControl[pd]; + + p = pbuf_alloc(PBUF_RAW, PPP_MRU+PPP_HDRLEN, PBUF_RAM); + if(!p) { + LWIP_ASSERT("p != NULL", p); + pc->errCode = PPPERR_ALLOC; + goto out; + } + + /* + * Start the connection and handle incoming events (packet or timeout). + */ + PPPDEBUG((LOG_INFO, "pppMain: unit %d: Connecting\n", pd)); + tcpip_callback(pppStartCB, arg); + while (lcp_phase[pd] != PHASE_DEAD) { + if (pc->kill_link) { + PPPDEBUG((LOG_DEBUG, "pppMainWakeup: unit %d kill_link -> pppStopCB\n", pd)); + pc->errCode = PPPERR_USER; + /* This will leave us at PHASE_DEAD. */ + tcpip_callback(pppStopCB, arg); + pc->kill_link = 0; + } + else if (pc->sig_hup) { + PPPDEBUG((LOG_DEBUG, "pppMainWakeup: unit %d sig_hup -> pppHupCB\n", pd)); + pc->sig_hup = 0; + tcpip_callback(pppHupCB, arg); + } else { + int c = sio_read(pc->fd, p->payload, p->len); + if(c > 0) { + pppInProc(pd, p->payload, c); + } else { + PPPDEBUG((LOG_DEBUG, "pppMainWakeup: unit %d sio_read len=%d returned %d\n", pd, p->len, c)); + sys_msleep(1); /* give other tasks a chance to run */ + } + } + } + PPPDEBUG((LOG_INFO, "pppMain: unit %d: PHASE_DEAD\n", pd)); + pbuf_free(p); + +out: + PPPDEBUG((LOG_DEBUG, "pppMain: unit %d: linkStatusCB=%lx errCode=%d\n", pd, pc->linkStatusCB, pc->errCode)); + if(pc->linkStatusCB) + pc->linkStatusCB(pc->linkStatusCtx, pc->errCode ? pc->errCode : PPPERR_PROTOCOL, NULL); + + pc->openFlag = 0; +} + +static struct pbuf *pppSingleBuf(struct pbuf *p) +{ + struct pbuf *q, *b; + u_char *pl; + + if(p->tot_len == p->len) + return p; + + q = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM); + if(!q) { + PPPDEBUG((LOG_ERR, + "pppSingleBuf: unable to alloc new buf (%d)\n", p->tot_len)); + return p; /* live dangerously */ + } + + for(b = p, pl = q->payload; b != NULL; b = b->next) { + memcpy(pl, b->payload, b->len); + pl += b->len; + } + + pbuf_free(p); + + return q; +} + +struct pppInputHeader { + int unit; + u16_t proto; +}; + +/* + * Pass the processed input packet to the appropriate handler. + * This function and all handlers run in the context of the tcpip_thread + */ +static void pppInput(void *arg) +{ + struct pbuf *nb = (struct pbuf *)arg; + u16_t protocol; + int pd; + + pd = ((struct pppInputHeader *)nb->payload)->unit; + protocol = ((struct pppInputHeader *)nb->payload)->proto; + + pbuf_header(nb, -(int)sizeof(struct pppInputHeader)); + +#if LINK_STATS + lwip_stats.link.recv++; +#endif /* LINK_STATS */ + + /* + * Toss all non-LCP packets unless LCP is OPEN. + * Until we get past the authentication phase, toss all packets + * except LCP, LQR and authentication packets. + */ + if((lcp_phase[pd] <= PHASE_AUTHENTICATE) && (protocol != PPP_LCP)) { + if(!((protocol == PPP_LQR) || (protocol == PPP_PAP) || (protocol == PPP_CHAP)) || + (lcp_phase[pd] != PHASE_AUTHENTICATE)) { + PPPDEBUG((LOG_INFO, "pppInput: discarding proto 0x%04X in phase %d\n", protocol, lcp_phase[pd])); + goto drop; + } + } + + switch(protocol) { + case PPP_VJC_COMP: /* VJ compressed TCP */ +#if VJ_SUPPORT > 0 + PPPDEBUG((LOG_INFO, "pppInput[%d]: vj_comp in pbuf len=%d\n", pd, nb->len)); + /* + * Clip off the VJ header and prepend the rebuilt TCP/IP header and + * pass the result to IP. + */ + if (vj_uncompress_tcp(&nb, &pppControl[pd].vjComp) >= 0) { + if (pppControl[pd].netif.input != NULL) { + pppControl[pd].netif.input(nb, &pppControl[pd].netif); + } + return; + } + /* Something's wrong so drop it. */ + PPPDEBUG((LOG_WARNING, "pppInput[%d]: Dropping VJ compressed\n", pd)); +#else + /* No handler for this protocol so drop the packet. */ + PPPDEBUG((LOG_INFO, "pppInput[%d]: drop VJ Comp in %d:%s\n", pd, nb->len, nb->payload)); +#endif /* VJ_SUPPORT > 0 */ + break; + case PPP_VJC_UNCOMP: /* VJ uncompressed TCP */ +#if VJ_SUPPORT > 0 + PPPDEBUG((LOG_INFO, "pppInput[%d]: vj_un in pbuf len=%d\n", pd, nb->len)); + /* + * Process the TCP/IP header for VJ header compression and then pass + * the packet to IP. + */ + if (vj_uncompress_uncomp(nb, &pppControl[pd].vjComp) >= 0) { + if (pppControl[pd].netif.input != NULL) { + pppControl[pd].netif.input(nb, &pppControl[pd].netif); + } + return; + } + /* Something's wrong so drop it. */ + PPPDEBUG((LOG_WARNING, "pppInput[%d]: Dropping VJ uncompressed\n", pd)); +#else + /* No handler for this protocol so drop the packet. */ + PPPDEBUG((LOG_INFO, + "pppInput[%d]: drop VJ UnComp in %d:.*H\n", + pd, nb->len, LWIP_MIN(nb->len * 2, 40), nb->payload)); +#endif /* VJ_SUPPORT > 0 */ + break; + case PPP_IP: /* Internet Protocol */ + PPPDEBUG((LOG_INFO, "pppInput[%d]: ip in pbuf len=%d\n", pd, nb->len)); + if (pppControl[pd].netif.input != NULL) { + pppControl[pd].netif.input(nb, &pppControl[pd].netif); + } + return; + default: + { + struct protent *protp; + int i; + + /* + * Upcall the proper protocol input routine. + */ + for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) { + if (protp->protocol == protocol && protp->enabled_flag) { + PPPDEBUG((LOG_INFO, "pppInput[%d]: %s len=%d\n", pd, protp->name, nb->len)); + nb = pppSingleBuf(nb); + (*protp->input)(pd, nb->payload, nb->len); + goto out; + } + } + + /* No handler for this protocol so reject the packet. */ + PPPDEBUG((LOG_INFO, "pppInput[%d]: rejecting unsupported proto 0x%04X len=%d\n", pd, protocol, nb->len)); + pbuf_header(nb, sizeof(protocol)); +#if BYTE_ORDER == LITTLE_ENDIAN + protocol = htons(protocol); + memcpy(nb->payload, &protocol, sizeof(protocol)); +#endif + lcp_sprotrej(pd, nb->payload, nb->len); + } + break; + } + +drop: +#if LINK_STATS + lwip_stats.link.drop++; +#endif + +out: + pbuf_free(nb); + return; +} + + +/* + * Drop the input packet. + */ +static void pppDrop(PPPControl *pc) +{ + if (pc->inHead != NULL) { +#if 0 + PPPDEBUG((LOG_INFO, "pppDrop: %d:%.*H\n", pc->inHead->len, min(60, pc->inHead->len * 2), pc->inHead->payload)); +#endif + PPPDEBUG((LOG_INFO, "pppDrop: pbuf len=%d\n", pc->inHead->len)); + if (pc->inTail && (pc->inTail != pc->inHead)) + pbuf_free(pc->inTail); + pbuf_free(pc->inHead); + pc->inHead = NULL; + pc->inTail = NULL; + } +#if VJ_SUPPORT > 0 + vj_uncompress_err(&pc->vjComp); +#endif + +#if LINK_STATS + lwip_stats.link.drop++; +#endif /* LINK_STATS */ +} + + +/* + * Process a received octet string. + */ +static void pppInProc(int pd, u_char *s, int l) +{ + PPPControl *pc = &pppControl[pd]; + struct pbuf *nextNBuf; + u_char curChar; + + PPPDEBUG((LOG_DEBUG, "pppInProc[%d]: got %d bytes\n", pd, l)); + while (l-- > 0) { + curChar = *s++; + + /* Handle special characters. */ + if (ESCAPE_P(pc->inACCM, curChar)) { + /* Check for escape sequences. */ + /* XXX Note that this does not handle an escaped 0x5d character which + * would appear as an escape character. Since this is an ASCII ']' + * and there is no reason that I know of to escape it, I won't complicate + * the code to handle this case. GLL */ + if (curChar == PPP_ESCAPE) + pc->inEscaped = 1; + /* Check for the flag character. */ + else if (curChar == PPP_FLAG) { + /* If this is just an extra flag character, ignore it. */ + if (pc->inState <= PDADDRESS) + ; + /* If we haven't received the packet header, drop what has come in. */ + else if (pc->inState < PDDATA) { + PPPDEBUG((LOG_WARNING, + "pppInProc[%d]: Dropping incomplete packet %d\n", + pd, pc->inState)); +#if LINK_STATS + lwip_stats.link.lenerr++; +#endif + pppDrop(pc); + } + /* If the fcs is invalid, drop the packet. */ + else if (pc->inFCS != PPP_GOODFCS) { + PPPDEBUG((LOG_INFO, + "pppInProc[%d]: Dropping bad fcs 0x%04X proto=0x%04X\n", + pd, pc->inFCS, pc->inProtocol)); +#if LINK_STATS + lwip_stats.link.chkerr++; +#endif + pppDrop(pc); + } + /* Otherwise it's a good packet so pass it on. */ + else { + + /* Trim off the checksum. */ + if(pc->inTail->len >= 2) { + pc->inTail->len -= 2; + + pc->inTail->tot_len = pc->inTail->len; + if (pc->inTail != pc->inHead) { + pbuf_cat(pc->inHead, pc->inTail); + } + } else { + pc->inTail->tot_len = pc->inTail->len; + if (pc->inTail != pc->inHead) { + pbuf_cat(pc->inHead, pc->inTail); + } + + pbuf_realloc(pc->inHead, pc->inHead->tot_len - 2); + } + + /* Dispatch the packet thereby consuming it. */ + if(tcpip_callback(pppInput, pc->inHead) != ERR_OK) { + PPPDEBUG((LOG_ERR, + "pppInProc[%d]: tcpip_callback() failed, dropping packet\n", pd)); + pbuf_free(pc->inHead); +#if LINK_STATS + lwip_stats.link.drop++; +#endif + } + pc->inHead = NULL; + pc->inTail = NULL; + } + + /* Prepare for a new packet. */ + pc->inFCS = PPP_INITFCS; + pc->inState = PDADDRESS; + pc->inEscaped = 0; + } + /* Other characters are usually control characters that may have + * been inserted by the physical layer so here we just drop them. */ + else { + PPPDEBUG((LOG_WARNING, + "pppInProc[%d]: Dropping ACCM char <%d>\n", pd, curChar)); + } + } + /* Process other characters. */ + else { + /* Unencode escaped characters. */ + if (pc->inEscaped) { + pc->inEscaped = 0; + curChar ^= PPP_TRANS; + } + + /* Process character relative to current state. */ + switch(pc->inState) { + case PDIDLE: /* Idle state - waiting. */ + /* Drop the character if it's not 0xff + * we would have processed a flag character above. */ + if (curChar != PPP_ALLSTATIONS) { + break; + } + + /* Fall through */ + case PDSTART: /* Process start flag. */ + /* Prepare for a new packet. */ + pc->inFCS = PPP_INITFCS; + + /* Fall through */ + case PDADDRESS: /* Process address field. */ + if (curChar == PPP_ALLSTATIONS) { + pc->inState = PDCONTROL; + break; + } + /* Else assume compressed address and control fields so + * fall through to get the protocol... */ + case PDCONTROL: /* Process control field. */ + /* If we don't get a valid control code, restart. */ + if (curChar == PPP_UI) { + pc->inState = PDPROTOCOL1; + break; + } +#if 0 + else { + PPPDEBUG((LOG_WARNING, + "pppInProc[%d]: Invalid control <%d>\n", pd, curChar)); + pc->inState = PDSTART; + } +#endif + case PDPROTOCOL1: /* Process protocol field 1. */ + /* If the lower bit is set, this is the end of the protocol + * field. */ + if (curChar & 1) { + pc->inProtocol = curChar; + pc->inState = PDDATA; + } + else { + pc->inProtocol = (u_int)curChar << 8; + pc->inState = PDPROTOCOL2; + } + break; + case PDPROTOCOL2: /* Process protocol field 2. */ + pc->inProtocol |= curChar; + pc->inState = PDDATA; + break; + case PDDATA: /* Process data byte. */ + /* Make space to receive processed data. */ + if (pc->inTail == NULL || pc->inTail->len == PBUF_POOL_BUFSIZE) { + if(pc->inTail) { + pc->inTail->tot_len = pc->inTail->len; + if (pc->inTail != pc->inHead) { + pbuf_cat(pc->inHead, pc->inTail); + } + } + /* If we haven't started a packet, we need a packet header. */ + nextNBuf = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL); + if (nextNBuf == NULL) { + /* No free buffers. Drop the input packet and let the + * higher layers deal with it. Continue processing + * the received pbuf chain in case a new packet starts. */ + PPPDEBUG((LOG_ERR, "pppInProc[%d]: NO FREE MBUFS!\n", pd)); +#if LINK_STATS + lwip_stats.link.memerr++; +#endif /* LINK_STATS */ + pppDrop(pc); + pc->inState = PDSTART; /* Wait for flag sequence. */ + break; + } + if (pc->inHead == NULL) { + struct pppInputHeader *pih = nextNBuf->payload; + + pih->unit = pd; + pih->proto = pc->inProtocol; + + nextNBuf->len += sizeof(*pih); + + pc->inHead = nextNBuf; + } + pc->inTail = nextNBuf; + } + /* Load character into buffer. */ + ((u_char*)pc->inTail->payload)[pc->inTail->len++] = curChar; + break; + } + + /* update the frame check sequence number. */ + pc->inFCS = PPP_FCS(pc->inFCS, curChar); + } + } + avRandomize(); +} + +#endif /* PPP_SUPPORT */ diff --git a/20080212/Demo/Common/ethernet/lwIP/netif/ppp/ppp.h b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/ppp.h new file mode 100644 index 000000000..094324813 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/ppp.h @@ -0,0 +1,446 @@ +/***************************************************************************** +* ppp.h - Network Point to Point Protocol header file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1997 Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-11-05 Guy Lancaster , Global Election Systems Inc. +* Original derived from BSD codes. +*****************************************************************************/ + +#ifndef PPP_H +#define PPP_H + +#include "lwip/opt.h" + +#if PPP_SUPPORT > 0 +#include "lwip/sio.h" +#include "lwip/api.h" +#include "lwip/sockets.h" +#include "lwip/stats.h" +#include "lwip/mem.h" +#include "lwip/tcpip.h" +#include "lwip/netif.h" + +/* + * pppd.h - PPP daemon global declarations. + * + * Copyright (c) 1989 Carnegie Mellon University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Carnegie Mellon University. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + */ +/* + * ppp_defs.h - PPP definitions. + * + * Copyright (c) 1994 The Australian National University. + * All rights reserved. + * + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, provided that the above copyright + * notice appears in all copies. This software is provided without any + * warranty, express or implied. The Australian National University + * makes no representations about the suitability of this software for + * any purpose. + * + * IN NO EVENT SHALL THE AUSTRALIAN NATIONAL UNIVERSITY BE LIABLE TO ANY + * PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES + * ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF + * THE AUSTRALIAN NATIONAL UNIVERSITY HAVE BEEN ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * THE AUSTRALIAN NATIONAL UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS + * ON AN "AS IS" BASIS, AND THE AUSTRALIAN NATIONAL UNIVERSITY HAS NO + * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, + * OR MODIFICATIONS. + */ + +#define TIMEOUT(f, a, t) sys_untimeout((f), (a)), sys_timeout((t)*1000, (f), (a)) +#define UNTIMEOUT(f, a) sys_untimeout((f), (a)) + + +# ifndef __u_char_defined + +/* Type definitions for BSD code. */ +typedef unsigned long u_long; +typedef unsigned int u_int; +typedef unsigned short u_short; +typedef unsigned char u_char; + +#endif + +/* + * Constants and structures defined by the internet system, + * Per RFC 790, September 1981, and numerous additions. + */ + +/* + * The basic PPP frame. + */ +#define PPP_HDRLEN 4 /* octets for standard ppp header */ +#define PPP_FCSLEN 2 /* octets for FCS */ + + +/* + * Significant octet values. + */ +#define PPP_ALLSTATIONS 0xff /* All-Stations broadcast address */ +#define PPP_UI 0x03 /* Unnumbered Information */ +#define PPP_FLAG 0x7e /* Flag Sequence */ +#define PPP_ESCAPE 0x7d /* Asynchronous Control Escape */ +#define PPP_TRANS 0x20 /* Asynchronous transparency modifier */ + +/* + * Protocol field values. + */ +#define PPP_IP 0x21 /* Internet Protocol */ +#define PPP_AT 0x29 /* AppleTalk Protocol */ +#define PPP_VJC_COMP 0x2d /* VJ compressed TCP */ +#define PPP_VJC_UNCOMP 0x2f /* VJ uncompressed TCP */ +#define PPP_COMP 0xfd /* compressed packet */ +#define PPP_IPCP 0x8021 /* IP Control Protocol */ +#define PPP_ATCP 0x8029 /* AppleTalk Control Protocol */ +#define PPP_CCP 0x80fd /* Compression Control Protocol */ +#define PPP_LCP 0xc021 /* Link Control Protocol */ +#define PPP_PAP 0xc023 /* Password Authentication Protocol */ +#define PPP_LQR 0xc025 /* Link Quality Report protocol */ +#define PPP_CHAP 0xc223 /* Cryptographic Handshake Auth. Protocol */ +#define PPP_CBCP 0xc029 /* Callback Control Protocol */ + +/* + * Values for FCS calculations. + */ +#define PPP_INITFCS 0xffff /* Initial FCS value */ +#define PPP_GOODFCS 0xf0b8 /* Good final FCS value */ +#define PPP_FCS(fcs, c) (((fcs) >> 8) ^ fcstab[((fcs) ^ (c)) & 0xff]) + +/* + * Extended asyncmap - allows any character to be escaped. + */ +typedef u_char ext_accm[32]; + +/* + * What to do with network protocol (NP) packets. + */ +enum NPmode { + NPMODE_PASS, /* pass the packet through */ + NPMODE_DROP, /* silently drop the packet */ + NPMODE_ERROR, /* return an error */ + NPMODE_QUEUE /* save it up for later. */ +}; + +/* + * Inline versions of get/put char/short/long. + * Pointer is advanced; we assume that both arguments + * are lvalues and will already be in registers. + * cp MUST be u_char *. + */ +#define GETCHAR(c, cp) { \ + (c) = *(cp)++; \ +} +#define PUTCHAR(c, cp) { \ + *(cp)++ = (u_char) (c); \ +} + + +#define GETSHORT(s, cp) { \ + (s) = *(cp); (cp)++; (s) << 8; \ + (s) |= *(cp); (cp)++; \ +} +#define PUTSHORT(s, cp) { \ + *(cp)++ = (u_char) ((s) >> 8); \ + *(cp)++ = (u_char) (s); \ +} + +#define GETLONG(l, cp) { \ + (l) = *(cp); (cp)++; (l) << 8; \ + (l) |= *(cp); (cp)++; (l) <<= 8; \ + (l) |= *(cp); (cp)++; (l) <<= 8; \ + (l) |= *(cp); (cp)++; \ +} +#define PUTLONG(l, cp) { \ + *(cp)++ = (u_char) ((l) >> 24); \ + *(cp)++ = (u_char) ((l) >> 16); \ + *(cp)++ = (u_char) ((l) >> 8); \ + *(cp)++ = (u_char) (l); \ +} + + +#define INCPTR(n, cp) ((cp) += (n)) +#define DECPTR(n, cp) ((cp) -= (n)) + +#define BCMP(s0, s1, l) memcmp((u_char *)(s0), (u_char *)(s1), (l)) +#define BCOPY(s, d, l) memcpy((d), (s), (l)) +#define BZERO(s, n) memset(s, 0, n) +#if PPP_DEBUG +#define PRINTMSG(m, l) { m[l] = '\0'; ppp_trace(LOG_INFO, "Remote message: %s\n", m); } +#else +#define PRINTMSG(m, l) +#endif + +/* + * MAKEHEADER - Add PPP Header fields to a packet. + */ +#define MAKEHEADER(p, t) { \ + PUTCHAR(PPP_ALLSTATIONS, p); \ + PUTCHAR(PPP_UI, p); \ + PUTSHORT(t, p); } + +/************************* +*** PUBLIC DEFINITIONS *** +*************************/ + +/* Error codes. */ +#define PPPERR_NONE 0 /* No error. */ +#define PPPERR_PARAM -1 /* Invalid parameter. */ +#define PPPERR_OPEN -2 /* Unable to open PPP session. */ +#define PPPERR_DEVICE -3 /* Invalid I/O device for PPP. */ +#define PPPERR_ALLOC -4 /* Unable to allocate resources. */ +#define PPPERR_USER -5 /* User interrupt. */ +#define PPPERR_CONNECT -6 /* Connection lost. */ +#define PPPERR_AUTHFAIL -7 /* Failed authentication challenge. */ +#define PPPERR_PROTOCOL -8 /* Failed to meet protocol. */ + +/* + * PPP IOCTL commands. + */ +/* + * Get the up status - 0 for down, non-zero for up. The argument must + * point to an int. + */ +#define PPPCTLG_UPSTATUS 100 /* Get the up status - 0 down else up */ +#define PPPCTLS_ERRCODE 101 /* Set the error code */ +#define PPPCTLG_ERRCODE 102 /* Get the error code */ +#define PPPCTLG_FD 103 /* Get the fd associated with the ppp */ + +/************************ +*** PUBLIC DATA TYPES *** +************************/ + +/* + * The following struct gives the addresses of procedures to call + * for a particular protocol. + */ +struct protent { + u_short protocol; /* PPP protocol number */ + /* Initialization procedure */ + void (*init) (int unit); + /* Process a received packet */ + void (*input) (int unit, u_char *pkt, int len); + /* Process a received protocol-reject */ + void (*protrej) (int unit); + /* Lower layer has come up */ + void (*lowerup) (int unit); + /* Lower layer has gone down */ + void (*lowerdown) (int unit); + /* Open the protocol */ + void (*open) (int unit); + /* Close the protocol */ + void (*close) (int unit, char *reason); +#if 0 + /* Print a packet in readable form */ + int (*printpkt) (u_char *pkt, int len, + void (*printer) (void *, char *, ...), + void *arg); + /* Process a received data packet */ + void (*datainput) (int unit, u_char *pkt, int len); +#endif + int enabled_flag; /* 0 iff protocol is disabled */ + char *name; /* Text name of protocol */ +#if 0 + /* Check requested options, assign defaults */ + void (*check_options) (u_long); + /* Configure interface for demand-dial */ + int (*demand_conf) (int unit); + /* Say whether to bring up link for this pkt */ + int (*active_pkt) (u_char *pkt, int len); +#endif +}; + +/* + * The following structure records the time in seconds since + * the last NP packet was sent or received. + */ +struct ppp_idle { + u_short xmit_idle; /* seconds since last NP packet sent */ + u_short recv_idle; /* seconds since last NP packet received */ +}; + +struct ppp_settings { + + u_int disable_defaultip : 1; /* Don't use hostname for default IP addrs */ + u_int auth_required : 1; /* Peer is required to authenticate */ + u_int explicit_remote : 1; /* remote_name specified with remotename opt */ + u_int refuse_pap : 1; /* Don't wanna auth. ourselves with PAP */ + u_int refuse_chap : 1; /* Don't wanna auth. ourselves with CHAP */ + u_int usehostname : 1; /* Use hostname for our_name */ + u_int usepeerdns : 1; /* Ask peer for DNS adds */ + + u_short idle_time_limit; /* Shut down link if idle for this long */ + int maxconnect; /* Maximum connect time (seconds) */ + + char user[MAXNAMELEN + 1];/* Username for PAP */ + char passwd[MAXSECRETLEN + 1]; /* Password for PAP, secret for CHAP */ + char our_name[MAXNAMELEN + 1]; /* Our name for authentication purposes */ + char remote_name[MAXNAMELEN + 1]; /* Peer's name for authentication */ +}; + +struct ppp_addrs { + struct ip_addr our_ipaddr, his_ipaddr, netmask, dns1, dns2; +}; + +/***************************** +*** PUBLIC DATA STRUCTURES *** +*****************************/ +/* Buffers for outgoing packets. */ +extern u_char outpacket_buf[NUM_PPP][PPP_MRU+PPP_HDRLEN]; + +extern struct ppp_settings ppp_settings; + +extern struct protent *ppp_protocols[];/* Table of pointers to supported protocols */ + + +/*********************** +*** PUBLIC FUNCTIONS *** +***********************/ + +/* Initialize the PPP subsystem. */ +void pppInit(void); + +/* Warning: Using PPPAUTHTYPE_ANY might have security consequences. + * RFC 1994 says: + * + * In practice, within or associated with each PPP server, there is a + * database which associates "user" names with authentication + * information ("secrets"). It is not anticipated that a particular + * named user would be authenticated by multiple methods. This would + * make the user vulnerable to attacks which negotiate the least secure + * method from among a set (such as PAP rather than CHAP). If the same + * secret was used, PAP would reveal the secret to be used later with + * CHAP. + * + * Instead, for each user name there should be an indication of exactly + * one method used to authenticate that user name. If a user needs to + * make use of different authentication methods under different + * circumstances, then distinct user names SHOULD be employed, each of + * which identifies exactly one authentication method. + * + */ +enum pppAuthType { + PPPAUTHTYPE_NONE, + PPPAUTHTYPE_ANY, + PPPAUTHTYPE_PAP, + PPPAUTHTYPE_CHAP +}; + +void pppSetAuth(enum pppAuthType authType, const char *user, const char *passwd); + +/* + * Open a new PPP connection using the given I/O device. + * This initializes the PPP control block but does not + * attempt to negotiate the LCP session. + * Return a new PPP connection descriptor on success or + * an error code (negative) on failure. + */ +int pppOpen(sio_fd_t fd, void (*linkStatusCB)(void *ctx, int errCode, void *arg), void *linkStatusCtx); + +/* + * Close a PPP connection and release the descriptor. + * Any outstanding packets in the queues are dropped. + * Return 0 on success, an error code on failure. + */ +int pppClose(int pd); + +/* + * Indicate to the PPP process that the line has disconnected. + */ +void pppSigHUP(int pd); + +/* + * Get and set parameters for the given connection. + * Return 0 on success, an error code on failure. + */ +int pppIOCtl(int pd, int cmd, void *arg); + +/* + * Return the Maximum Transmission Unit for the given PPP connection. + */ +u_int pppMTU(int pd); + +/* + * Write n characters to a ppp link. + * RETURN: >= 0 Number of characters written + * -1 Failed to write to device + */ +int pppWrite(int pd, const u_char *s, int n); + +void pppMainWakeup(int pd); + +/* Configure i/f transmit parameters */ +void ppp_send_config (int, int, u32_t, int, int); +/* Set extended transmit ACCM */ +void ppp_set_xaccm (int, ext_accm *); +/* Configure i/f receive parameters */ +void ppp_recv_config (int, int, u32_t, int, int); +/* Find out how long link has been idle */ +int get_idle_time (int, struct ppp_idle *); + +/* Configure VJ TCP header compression */ +int sifvjcomp (int, int, int, int); +/* Configure i/f down (for IP) */ +int sifup (int); +/* Set mode for handling packets for proto */ +int sifnpmode (int u, int proto, enum NPmode mode); +/* Configure i/f down (for IP) */ +int sifdown (int); +/* Configure IP addresses for i/f */ +int sifaddr (int, u32_t, u32_t, u32_t, u32_t, u32_t); +/* Reset i/f IP addresses */ +int cifaddr (int, u32_t, u32_t); +/* Create default route through i/f */ +int sifdefaultroute (int, u32_t, u32_t); +/* Delete default route through i/f */ +int cifdefaultroute (int, u32_t, u32_t); + +/* Get appropriate netmask for address */ +u32_t GetMask (u32_t); + +#endif /* PPP_SUPPORT */ + +#endif /* PPP_H */ diff --git a/20080212/Demo/Common/ethernet/lwIP/netif/ppp/pppdebug.h b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/pppdebug.h new file mode 100644 index 000000000..e4cf25a39 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/pppdebug.h @@ -0,0 +1,89 @@ +/***************************************************************************** +* pppdebug.h - System debugging utilities. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1998 Global Election Systems Inc. +* portions Copyright (c) 2001 by Cognizant Pty Ltd. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY (please don't use tabs!) +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 98-07-29 Guy Lancaster , Global Election Systems Inc. +* Original. +* +***************************************************************************** +*/ +#ifndef PPPDEBUG_H +#define PPPDEBUG_H + +/************************ +*** PUBLIC DATA TYPES *** +************************/ +/* Trace levels. */ +typedef enum { + LOG_CRITICAL = 0, + LOG_ERR = 1, + LOG_NOTICE = 2, + LOG_WARNING = 3, + LOG_INFO = 5, + LOG_DETAIL = 6, + LOG_DEBUG = 7 +} LogCodes; + + +/*********************** +*** PUBLIC FUNCTIONS *** +***********************/ +/* + * ppp_trace - a form of printf to send tracing information to stderr + */ +void ppp_trace(int level, const char *format,...); + +#if PPP_DEBUG > 0 + +#define AUTHDEBUG(a) ppp_trace a +#define IPCPDEBUG(a) ppp_trace a +#define UPAPDEBUG(a) ppp_trace a +#define LCPDEBUG(a) ppp_trace a +#define FSMDEBUG(a) ppp_trace a +#define CHAPDEBUG(a) ppp_trace a +#define PPPDEBUG(a) ppp_trace a + +#define TRACELCP 1 + +#else + +#define AUTHDEBUG(a) +#define IPCPDEBUG(a) +#define UPAPDEBUG(a) +#define LCPDEBUG(a) +#define FSMDEBUG(a) +#define CHAPDEBUG(a) + +#define PPPDEBUG(a) + +#define TRACELCP 0 + +#endif + +#endif /* PPPDEBUG_H */ diff --git a/20080212/Demo/Common/ethernet/lwIP/netif/ppp/randm.c b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/randm.c new file mode 100644 index 000000000..d4431dd8e --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/randm.c @@ -0,0 +1,242 @@ +/***************************************************************************** +* randm.c - Random number generator program file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* Copyright (c) 1998 by Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 98-06-03 Guy Lancaster , Global Election Systems Inc. +* Extracted from avos. +*****************************************************************************/ + +#include "ppp.h" +#if PPP_SUPPORT > 0 +#include "md5.h" +#include "randm.h" + +#include "pppdebug.h" + + +#if MD5_SUPPORT>0 /* this module depends on MD5 */ +#define RANDPOOLSZ 16 /* Bytes stored in the pool of randomness. */ + +/*****************************/ +/*** LOCAL DATA STRUCTURES ***/ +/*****************************/ +static char randPool[RANDPOOLSZ]; /* Pool of randomness. */ +static long randCount = 0; /* Pseudo-random incrementer */ + + +/***********************************/ +/*** PUBLIC FUNCTION DEFINITIONS ***/ +/***********************************/ +/* + * Initialize the random number generator. + * + * Since this is to be called on power up, we don't have much + * system randomess to work with. Here all we use is the + * real-time clock. We'll accumulate more randomness as soon + * as things start happening. + */ +void avRandomInit() +{ + avChurnRand(NULL, 0); +} + +/* + * Churn the randomness pool on a random event. Call this early and often + * on random and semi-random system events to build randomness in time for + * usage. For randomly timed events, pass a null pointer and a zero length + * and this will use the system timer and other sources to add randomness. + * If new random data is available, pass a pointer to that and it will be + * included. + * + * Ref: Applied Cryptography 2nd Ed. by Bruce Schneier p. 427 + */ +void avChurnRand(char *randData, u32_t randLen) +{ + MD5_CTX md5; + +/* ppp_trace(LOG_INFO, "churnRand: %u@%P\n", randLen, randData); */ + MD5Init(&md5); + MD5Update(&md5, (u_char *)randPool, sizeof(randPool)); + if (randData) + MD5Update(&md5, (u_char *)randData, randLen); + else { + struct { + /* INCLUDE fields for any system sources of randomness */ + char foobar; + } sysData; + + /* Load sysData fields here. */ + ; + MD5Update(&md5, (u_char *)&sysData, sizeof(sysData)); + } + MD5Final((u_char *)randPool, &md5); +/* ppp_trace(LOG_INFO, "churnRand: -> 0\n"); */ +} + +/* + * Use the random pool to generate random data. This degrades to pseudo + * random when used faster than randomness is supplied using churnRand(). + * Note: It's important that there be sufficient randomness in randPool + * before this is called for otherwise the range of the result may be + * narrow enough to make a search feasible. + * + * Ref: Applied Cryptography 2nd Ed. by Bruce Schneier p. 427 + * + * XXX Why does he not just call churnRand() for each block? Probably + * so that you don't ever publish the seed which could possibly help + * predict future values. + * XXX Why don't we preserve md5 between blocks and just update it with + * randCount each time? Probably there is a weakness but I wish that + * it was documented. + */ +void avGenRand(char *buf, u32_t bufLen) +{ + MD5_CTX md5; + u_char tmp[16]; + u32_t n; + + while (bufLen > 0) { + n = LWIP_MIN(bufLen, RANDPOOLSZ); + MD5Init(&md5); + MD5Update(&md5, (u_char *)randPool, sizeof(randPool)); + MD5Update(&md5, (u_char *)&randCount, sizeof(randCount)); + MD5Final(tmp, &md5); + randCount++; + memcpy(buf, tmp, n); + buf += n; + bufLen -= n; + } +} + +/* + * Return a new random number. + */ +u32_t avRandom() +{ + u32_t newRand; + + avGenRand((char *)&newRand, sizeof(newRand)); + + return newRand; +} + +#else /* MD5_SUPPORT */ + + +/*****************************/ +/*** LOCAL DATA STRUCTURES ***/ +/*****************************/ +static int avRandomized = 0; /* Set when truely randomized. */ +static u32_t avRandomSeed = 0; /* Seed used for random number generation. */ + + +/***********************************/ +/*** PUBLIC FUNCTION DEFINITIONS ***/ +/***********************************/ +/* + * Initialize the random number generator. + * + * Here we attempt to compute a random number seed but even if + * it isn't random, we'll randomize it later. + * + * The current method uses the fields from the real time clock, + * the idle process counter, the millisecond counter, and the + * hardware timer tick counter. When this is invoked + * in startup(), then the idle counter and timer values may + * repeat after each boot and the real time clock may not be + * operational. Thus we call it again on the first random + * event. + */ +void avRandomInit() +{ +#if 0 + /* Get a pointer into the last 4 bytes of clockBuf. */ + u32_t *lptr1 = (u32_t *)((char *)&clockBuf[3]); + + /* + * Initialize our seed using the real-time clock, the idle + * counter, the millisecond timer, and the hardware timer + * tick counter. The real-time clock and the hardware + * tick counter are the best sources of randomness but + * since the tick counter is only 16 bit (and truncated + * at that), the idle counter and millisecond timer + * (which may be small values) are added to help + * randomize the lower 16 bits of the seed. + */ + readClk(); + avRandomSeed += *(u32_t *)clockBuf + *lptr1 + OSIdleCtr + + ppp_mtime() + ((u32_t)TM1 << 16) + TM1; +#else + avRandomSeed += sys_jiffies(); /* XXX */ +#endif + + /* Initialize the Borland random number generator. */ + srand((unsigned)avRandomSeed); +} + +/* + * Randomize our random seed value. Here we use the fact that + * this function is called at *truely random* times by the polling + * and network functions. Here we only get 16 bits of new random + * value but we use the previous value to randomize the other 16 + * bits. + */ +void avRandomize(void) +{ + static u32_t last_jiffies; + + if (!avRandomized) { + avRandomized = !0; + avRandomInit(); + /* The initialization function also updates the seed. */ + } else { +/* avRandomSeed += (avRandomSeed << 16) + TM1; */ + avRandomSeed += (sys_jiffies() - last_jiffies); /* XXX */ + } + last_jiffies = sys_jiffies(); +} + +/* + * Return a new random number. + * Here we use the Borland rand() function to supply a pseudo random + * number which we make truely random by combining it with our own + * seed which is randomized by truely random events. + * Thus the numbers will be truely random unless there have been no + * operator or network events in which case it will be pseudo random + * seeded by the real time clock. + */ +u32_t avRandom() +{ + return ((((u32_t)rand() << 16) + rand()) + avRandomSeed); +} + + + +#endif /* MD5_SUPPORT */ +#endif /* PPP_SUPPORT */ + diff --git a/20080212/Demo/Common/ethernet/lwIP/netif/ppp/randm.h b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/randm.h new file mode 100644 index 000000000..2563d8976 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/randm.h @@ -0,0 +1,81 @@ +/***************************************************************************** +* randm.h - Random number generator header file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* Copyright (c) 1998 Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 98-05-29 Guy Lancaster , Global Election Systems Inc. +* Extracted from avos. +*****************************************************************************/ + +#ifndef RANDM_H +#define RANDM_H + +/*********************** +*** PUBLIC FUNCTIONS *** +***********************/ +/* + * Initialize the random number generator. + */ +void avRandomInit(void); + +/* + * Churn the randomness pool on a random event. Call this early and often + * on random and semi-random system events to build randomness in time for + * usage. For randomly timed events, pass a null pointer and a zero length + * and this will use the system timer and other sources to add randomness. + * If new random data is available, pass a pointer to that and it will be + * included. + */ +void avChurnRand(char *randData, u32_t randLen); + +/* + * Randomize our random seed value. To be called for truely random events + * such as user operations and network traffic. + */ +#if MD5_SUPPORT +#define avRandomize() avChurnRand(NULL, 0) +#else +void avRandomize(void); +#endif + +/* + * Use the random pool to generate random data. This degrades to pseudo + * random when used faster than randomness is supplied using churnRand(). + * Thus it's important to make sure that the results of this are not + * published directly because one could predict the next result to at + * least some degree. Also, it's important to get a good seed before + * the first use. + */ +void avGenRand(char *buf, u32_t bufLen); + +/* + * Return a new random number. + */ +u32_t avRandom(void); + + +#endif /* RANDM_H */ diff --git a/20080212/Demo/Common/ethernet/lwIP/netif/ppp/vj.c b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/vj.c new file mode 100644 index 000000000..2c11affe3 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/vj.c @@ -0,0 +1,633 @@ +/* + * Routines to compress and uncompess tcp packets (for transmission + * over low speed serial lines. + * + * Copyright (c) 1989 Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by the University of California, Berkeley. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * Van Jacobson (van@helios.ee.lbl.gov), Dec 31, 1989: + * - Initial distribution. + * + * Modified June 1993 by Paul Mackerras, paulus@cs.anu.edu.au, + * so that the entire packet being decompressed doesn't have + * to be in contiguous memory (just the compressed header). + * + * Modified March 1998 by Guy Lancaster, glanca@gesn.com, + * for a 16 bit processor. + */ + +#include + +#include "ppp.h" +#include "vj.h" +#include "pppdebug.h" + +#if VJ_SUPPORT > 0 + +#if LINK_STATS +#define INCR(counter) ++comp->stats.counter +#else +#define INCR(counter) +#endif + +#if defined(NO_CHAR_BITFIELDS) +#define getip_hl(base) ((base).ip_hl_v&0xf) +#define getth_off(base) (((base).th_x2_off&0xf0)>>4) +#else +#define getip_hl(base) ((base).ip_hl) +#define getth_off(base) ((base).th_off) +#endif + +void vj_compress_init(struct vjcompress *comp) +{ + register u_int i; + register struct cstate *tstate = comp->tstate; + +#if MAX_SLOTS == 0 + memset((char *)comp, 0, sizeof(*comp)); +#endif + comp->maxSlotIndex = MAX_SLOTS - 1; + comp->compressSlot = 0; /* Disable slot ID compression by default. */ + for (i = MAX_SLOTS - 1; i > 0; --i) { + tstate[i].cs_id = i; + tstate[i].cs_next = &tstate[i - 1]; + } + tstate[0].cs_next = &tstate[MAX_SLOTS - 1]; + tstate[0].cs_id = 0; + comp->last_cs = &tstate[0]; + comp->last_recv = 255; + comp->last_xmit = 255; + comp->flags = VJF_TOSS; +} + + +/* ENCODE encodes a number that is known to be non-zero. ENCODEZ + * checks for zero (since zero has to be encoded in the long, 3 byte + * form). + */ +#define ENCODE(n) { \ + if ((u_short)(n) >= 256) { \ + *cp++ = 0; \ + cp[1] = (n); \ + cp[0] = (n) >> 8; \ + cp += 2; \ + } else { \ + *cp++ = (n); \ + } \ +} +#define ENCODEZ(n) { \ + if ((u_short)(n) >= 256 || (u_short)(n) == 0) { \ + *cp++ = 0; \ + cp[1] = (n); \ + cp[0] = (n) >> 8; \ + cp += 2; \ + } else { \ + *cp++ = (n); \ + } \ +} + +#define DECODEL(f) { \ + if (*cp == 0) {\ + u32_t tmp = ntohl(f) + ((cp[1] << 8) | cp[2]); \ + (f) = htonl(tmp); \ + cp += 3; \ + } else { \ + u32_t tmp = ntohl(f) + (u32_t)*cp++; \ + (f) = htonl(tmp); \ + } \ +} + +#define DECODES(f) { \ + if (*cp == 0) {\ + u_short tmp = ntohs(f) + (((u_short)cp[1] << 8) | cp[2]); \ + (f) = htons(tmp); \ + cp += 3; \ + } else { \ + u_short tmp = ntohs(f) + (u_short)*cp++; \ + (f) = htons(tmp); \ + } \ +} + +#define DECODEU(f) { \ + if (*cp == 0) {\ + (f) = htons(((u_short)cp[1] << 8) | cp[2]); \ + cp += 3; \ + } else { \ + (f) = htons((u_short)*cp++); \ + } \ +} + +/* + * vj_compress_tcp - Attempt to do Van Jacobsen header compression on a + * packet. This assumes that nb and comp are not null and that the first + * buffer of the chain contains a valid IP header. + * Return the VJ type code indicating whether or not the packet was + * compressed. + */ +u_int vj_compress_tcp( + struct vjcompress *comp, + struct pbuf *pb +) +{ + register struct ip *ip = (struct ip *)pb->payload; + register struct cstate *cs = comp->last_cs->cs_next; + register u_short hlen = getip_hl(*ip); + register struct tcphdr *oth; + register struct tcphdr *th; + register u_short deltaS, deltaA; + register u_long deltaL; + register u_int changes = 0; + u_char new_seq[16]; + register u_char *cp = new_seq; + + /* + * Check that the packet is IP proto TCP. + */ + if (ip->ip_p != IPPROTO_TCP) + return (TYPE_IP); + + /* + * Bail if this is an IP fragment or if the TCP packet isn't + * `compressible' (i.e., ACK isn't set or some other control bit is + * set). + */ + if ((ip->ip_off & htons(0x3fff)) || pb->tot_len < 40) + return (TYPE_IP); + th = (struct tcphdr *)&((long *)ip)[hlen]; + if ((th->th_flags & (TCP_SYN|TCP_FIN|TCP_RST|TCP_ACK)) != TCP_ACK) + return (TYPE_IP); + + /* + * Packet is compressible -- we're going to send either a + * COMPRESSED_TCP or UNCOMPRESSED_TCP packet. Either way we need + * to locate (or create) the connection state. Special case the + * most recently used connection since it's most likely to be used + * again & we don't have to do any reordering if it's used. + */ + INCR(vjs_packets); + if (ip->ip_src.s_addr != cs->cs_ip.ip_src.s_addr + || ip->ip_dst.s_addr != cs->cs_ip.ip_dst.s_addr + || *(long *)th != ((long *)&cs->cs_ip)[getip_hl(cs->cs_ip)]) { + /* + * Wasn't the first -- search for it. + * + * States are kept in a circularly linked list with + * last_cs pointing to the end of the list. The + * list is kept in lru order by moving a state to the + * head of the list whenever it is referenced. Since + * the list is short and, empirically, the connection + * we want is almost always near the front, we locate + * states via linear search. If we don't find a state + * for the datagram, the oldest state is (re-)used. + */ + register struct cstate *lcs; + register struct cstate *lastcs = comp->last_cs; + + do { + lcs = cs; cs = cs->cs_next; + INCR(vjs_searches); + if (ip->ip_src.s_addr == cs->cs_ip.ip_src.s_addr + && ip->ip_dst.s_addr == cs->cs_ip.ip_dst.s_addr + && *(long *)th == ((long *)&cs->cs_ip)[getip_hl(cs->cs_ip)]) + goto found; + } while (cs != lastcs); + + /* + * Didn't find it -- re-use oldest cstate. Send an + * uncompressed packet that tells the other side what + * connection number we're using for this conversation. + * Note that since the state list is circular, the oldest + * state points to the newest and we only need to set + * last_cs to update the lru linkage. + */ + INCR(vjs_misses); + comp->last_cs = lcs; + hlen += getth_off(*th); + hlen <<= 2; + /* Check that the IP/TCP headers are contained in the first buffer. */ + if (hlen > pb->len) + return (TYPE_IP); + goto uncompressed; + + found: + /* + * Found it -- move to the front on the connection list. + */ + if (cs == lastcs) + comp->last_cs = lcs; + else { + lcs->cs_next = cs->cs_next; + cs->cs_next = lastcs->cs_next; + lastcs->cs_next = cs; + } + } + + oth = (struct tcphdr *)&((long *)&cs->cs_ip)[hlen]; + deltaS = hlen; + hlen += getth_off(*th); + hlen <<= 2; + /* Check that the IP/TCP headers are contained in the first buffer. */ + if (hlen > pb->len) { + PPPDEBUG((LOG_INFO, "vj_compress_tcp: header len %d spans buffers\n", + hlen)); + return (TYPE_IP); + } + + /* + * Make sure that only what we expect to change changed. The first + * line of the `if' checks the IP protocol version, header length & + * type of service. The 2nd line checks the "Don't fragment" bit. + * The 3rd line checks the time-to-live and protocol (the protocol + * check is unnecessary but costless). The 4th line checks the TCP + * header length. The 5th line checks IP options, if any. The 6th + * line checks TCP options, if any. If any of these things are + * different between the previous & current datagram, we send the + * current datagram `uncompressed'. + */ + if (((u_short *)ip)[0] != ((u_short *)&cs->cs_ip)[0] + || ((u_short *)ip)[3] != ((u_short *)&cs->cs_ip)[3] + || ((u_short *)ip)[4] != ((u_short *)&cs->cs_ip)[4] + || getth_off(*th) != getth_off(*oth) + || (deltaS > 5 && BCMP(ip + 1, &cs->cs_ip + 1, (deltaS - 5) << 2)) + || (getth_off(*th) > 5 && BCMP(th + 1, oth + 1, (getth_off(*th) - 5) << 2))) + goto uncompressed; + + /* + * Figure out which of the changing fields changed. The + * receiver expects changes in the order: urgent, window, + * ack, seq (the order minimizes the number of temporaries + * needed in this section of code). + */ + if (th->th_flags & TCP_URG) { + deltaS = ntohs(th->th_urp); + ENCODEZ(deltaS); + changes |= NEW_U; + } else if (th->th_urp != oth->th_urp) + /* argh! URG not set but urp changed -- a sensible + * implementation should never do this but RFC793 + * doesn't prohibit the change so we have to deal + * with it. */ + goto uncompressed; + + if ((deltaS = (u_short)(ntohs(th->th_win) - ntohs(oth->th_win))) != 0) { + ENCODE(deltaS); + changes |= NEW_W; + } + + if ((deltaL = ntohl(th->th_ack) - ntohl(oth->th_ack)) != 0) { + if (deltaL > 0xffff) + goto uncompressed; + deltaA = (u_short)deltaL; + ENCODE(deltaA); + changes |= NEW_A; + } + + if ((deltaL = ntohl(th->th_seq) - ntohl(oth->th_seq)) != 0) { + if (deltaL > 0xffff) + goto uncompressed; + deltaS = (u_short)deltaL; + ENCODE(deltaS); + changes |= NEW_S; + } + + switch(changes) { + + case 0: + /* + * Nothing changed. If this packet contains data and the + * last one didn't, this is probably a data packet following + * an ack (normal on an interactive connection) and we send + * it compressed. Otherwise it's probably a retransmit, + * retransmitted ack or window probe. Send it uncompressed + * in case the other side missed the compressed version. + */ + if (ip->ip_len != cs->cs_ip.ip_len && + ntohs(cs->cs_ip.ip_len) == hlen) + break; + + /* (fall through) */ + + case SPECIAL_I: + case SPECIAL_D: + /* + * actual changes match one of our special case encodings -- + * send packet uncompressed. + */ + goto uncompressed; + + case NEW_S|NEW_A: + if (deltaS == deltaA && deltaS == ntohs(cs->cs_ip.ip_len) - hlen) { + /* special case for echoed terminal traffic */ + changes = SPECIAL_I; + cp = new_seq; + } + break; + + case NEW_S: + if (deltaS == ntohs(cs->cs_ip.ip_len) - hlen) { + /* special case for data xfer */ + changes = SPECIAL_D; + cp = new_seq; + } + break; + } + + deltaS = (u_short)(ntohs(ip->ip_id) - ntohs(cs->cs_ip.ip_id)); + if (deltaS != 1) { + ENCODEZ(deltaS); + changes |= NEW_I; + } + if (th->th_flags & TCP_PSH) + changes |= TCP_PUSH_BIT; + /* + * Grab the cksum before we overwrite it below. Then update our + * state with this packet's header. + */ + deltaA = ntohs(th->th_sum); + BCOPY(ip, &cs->cs_ip, hlen); + + /* + * We want to use the original packet as our compressed packet. + * (cp - new_seq) is the number of bytes we need for compressed + * sequence numbers. In addition we need one byte for the change + * mask, one for the connection id and two for the tcp checksum. + * So, (cp - new_seq) + 4 bytes of header are needed. hlen is how + * many bytes of the original packet to toss so subtract the two to + * get the new packet size. + */ + deltaS = (u_short)(cp - new_seq); + if (!comp->compressSlot || comp->last_xmit != cs->cs_id) { + comp->last_xmit = cs->cs_id; + hlen -= deltaS + 4; + pbuf_header(pb, -hlen); + cp = (u_char *)pb->payload; + *cp++ = changes | NEW_C; + *cp++ = cs->cs_id; + } else { + hlen -= deltaS + 3; + pbuf_header(pb, -hlen); + cp = (u_char *)pb->payload; + *cp++ = changes; + } + *cp++ = deltaA >> 8; + *cp++ = deltaA; + BCOPY(new_seq, cp, deltaS); + INCR(vjs_compressed); + return (TYPE_COMPRESSED_TCP); + + /* + * Update connection state cs & send uncompressed packet (that is, + * a regular ip/tcp packet but with the 'conversation id' we hope + * to use on future compressed packets in the protocol field). + */ +uncompressed: + BCOPY(ip, &cs->cs_ip, hlen); + ip->ip_p = cs->cs_id; + comp->last_xmit = cs->cs_id; + return (TYPE_UNCOMPRESSED_TCP); +} + +/* + * Called when we may have missed a packet. + */ +void vj_uncompress_err(struct vjcompress *comp) +{ + comp->flags |= VJF_TOSS; + INCR(vjs_errorin); +} + +/* + * "Uncompress" a packet of type TYPE_UNCOMPRESSED_TCP. + * Return 0 on success, -1 on failure. + */ +int vj_uncompress_uncomp( + struct pbuf *nb, + struct vjcompress *comp +) +{ + register u_int hlen; + register struct cstate *cs; + register struct ip *ip; + + ip = (struct ip *)nb->payload; + hlen = getip_hl(*ip) << 2; + if (ip->ip_p >= MAX_SLOTS + || hlen + sizeof(struct tcphdr) > nb->len + || (hlen += getth_off(*((struct tcphdr *)&((char *)ip)[hlen])) << 2) + > nb->len + || hlen > MAX_HDR) { + PPPDEBUG((LOG_INFO, "vj_uncompress_uncomp: bad cid=%d, hlen=%d buflen=%d\n", + ip->ip_p, hlen, nb->len)); + comp->flags |= VJF_TOSS; + INCR(vjs_errorin); + return -1; + } + cs = &comp->rstate[comp->last_recv = ip->ip_p]; + comp->flags &=~ VJF_TOSS; + ip->ip_p = IPPROTO_TCP; + BCOPY(ip, &cs->cs_ip, hlen); + cs->cs_hlen = hlen; + INCR(vjs_uncompressedin); + return 0; +} + +/* + * Uncompress a packet of type TYPE_COMPRESSED_TCP. + * The packet is composed of a buffer chain and the first buffer + * must contain an accurate chain length. + * The first buffer must include the entire compressed TCP/IP header. + * This procedure replaces the compressed header with the uncompressed + * header and returns the length of the VJ header. + */ +int vj_uncompress_tcp( + struct pbuf **nb, + struct vjcompress *comp +) +{ + u_char *cp; + struct tcphdr *th; + struct cstate *cs; + u_short *bp; + struct pbuf *n0 = *nb; + u32_t tmp; + u_int vjlen, hlen, changes; + + INCR(vjs_compressedin); + cp = (u_char *)n0->payload; + changes = *cp++; + if (changes & NEW_C) { + /* + * Make sure the state index is in range, then grab the state. + * If we have a good state index, clear the 'discard' flag. + */ + if (*cp >= MAX_SLOTS) { + PPPDEBUG((LOG_INFO, "vj_uncompress_tcp: bad cid=%d\n", *cp)); + goto bad; + } + + comp->flags &=~ VJF_TOSS; + comp->last_recv = *cp++; + } else { + /* + * this packet has an implicit state index. If we've + * had a line error since the last time we got an + * explicit state index, we have to toss the packet. + */ + if (comp->flags & VJF_TOSS) { + PPPDEBUG((LOG_INFO, "vj_uncompress_tcp: tossing\n")); + INCR(vjs_tossed); + return (-1); + } + } + cs = &comp->rstate[comp->last_recv]; + hlen = getip_hl(cs->cs_ip) << 2; + th = (struct tcphdr *)&((u_char *)&cs->cs_ip)[hlen]; + th->th_sum = htons((*cp << 8) | cp[1]); + cp += 2; + if (changes & TCP_PUSH_BIT) + th->th_flags |= TCP_PSH; + else + th->th_flags &=~ TCP_PSH; + + switch (changes & SPECIALS_MASK) { + case SPECIAL_I: + { + register u32_t i = ntohs(cs->cs_ip.ip_len) - cs->cs_hlen; + /* some compilers can't nest inline assembler.. */ + tmp = ntohl(th->th_ack) + i; + th->th_ack = htonl(tmp); + tmp = ntohl(th->th_seq) + i; + th->th_seq = htonl(tmp); + } + break; + + case SPECIAL_D: + /* some compilers can't nest inline assembler.. */ + tmp = ntohl(th->th_seq) + ntohs(cs->cs_ip.ip_len) - cs->cs_hlen; + th->th_seq = htonl(tmp); + break; + + default: + if (changes & NEW_U) { + th->th_flags |= TCP_URG; + DECODEU(th->th_urp); + } else + th->th_flags &=~ TCP_URG; + if (changes & NEW_W) + DECODES(th->th_win); + if (changes & NEW_A) + DECODEL(th->th_ack); + if (changes & NEW_S) + DECODEL(th->th_seq); + break; + } + if (changes & NEW_I) { + DECODES(cs->cs_ip.ip_id); + } else { + cs->cs_ip.ip_id = ntohs(cs->cs_ip.ip_id) + 1; + cs->cs_ip.ip_id = htons(cs->cs_ip.ip_id); + } + + /* + * At this point, cp points to the first byte of data in the + * packet. Fill in the IP total length and update the IP + * header checksum. + */ + vjlen = (u_short)(cp - (u_char*)n0->payload); + if (n0->len < vjlen) { + /* + * We must have dropped some characters (crc should detect + * this but the old slip framing won't) + */ + PPPDEBUG((LOG_INFO, "vj_uncompress_tcp: head buffer %d too short %d\n", + n0->len, vjlen)); + goto bad; + } + +#if BYTE_ORDER == LITTLE_ENDIAN + tmp = n0->tot_len - vjlen + cs->cs_hlen; + cs->cs_ip.ip_len = htons(tmp); +#else + cs->cs_ip.ip_len = htons(n0->tot_len - vjlen + cs->cs_hlen); +#endif + + /* recompute the ip header checksum */ + bp = (u_short *) &cs->cs_ip; + cs->cs_ip.ip_sum = 0; + for (tmp = 0; hlen > 0; hlen -= 2) + tmp += *bp++; + tmp = (tmp & 0xffff) + (tmp >> 16); + tmp = (tmp & 0xffff) + (tmp >> 16); + cs->cs_ip.ip_sum = (u_short)(~tmp); + + /* Remove the compressed header and prepend the uncompressed header. */ + pbuf_header(n0, -vjlen); + + if(MEM_ALIGN(n0->payload) != n0->payload) { + struct pbuf *np, *q; + u8_t *bufptr; + + np = pbuf_alloc(PBUF_RAW, n0->len + cs->cs_hlen, PBUF_POOL); + if(!np) { + PPPDEBUG((LOG_WARNING, "vj_uncompress_tcp: realign failed\n")); + *nb = NULL; + goto bad; + } + + pbuf_header(np, -cs->cs_hlen); + + bufptr = n0->payload; + for(q = np; q != NULL; q = q->next) { + memcpy(q->payload, bufptr, q->len); + bufptr += q->len; + } + + if(n0->next) { + pbuf_chain(np, n0->next); + pbuf_dechain(n0); + } + pbuf_free(n0); + n0 = np; + } + + if(pbuf_header(n0, cs->cs_hlen)) { + struct pbuf *np; + + LWIP_ASSERT("vj_uncompress_tcp: cs->cs_hlen <= PBUF_POOL_BUFSIZE", cs->cs_hlen <= PBUF_POOL_BUFSIZE); + np = pbuf_alloc(PBUF_RAW, cs->cs_hlen, PBUF_POOL); + if(!np) { + PPPDEBUG((LOG_WARNING, "vj_uncompress_tcp: prepend failed\n")); + *nb = NULL; + goto bad; + } + pbuf_cat(np, n0); + n0 = np; + } + LWIP_ASSERT("n0->len >= cs->cs_hlen", n0->len >= cs->cs_hlen); + memcpy(n0->payload, &cs->cs_ip, cs->cs_hlen); + + *nb = n0; + + return vjlen; + +bad: + comp->flags |= VJF_TOSS; + INCR(vjs_errorin); + return (-1); +} + +#endif + + diff --git a/20080212/Demo/Common/ethernet/lwIP/netif/ppp/vj.h b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/vj.h new file mode 100644 index 000000000..9da271481 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/vj.h @@ -0,0 +1,155 @@ +/* + * Definitions for tcp compression routines. + * + * $Id: vj.h,v 1.4 2004/02/07 00:30:03 likewise Exp $ + * + * Copyright (c) 1989 Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by the University of California, Berkeley. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * Van Jacobson (van@helios.ee.lbl.gov), Dec 31, 1989: + * - Initial distribution. + */ + +#ifndef VJ_H +#define VJ_H + +#include "vjbsdhdr.h" + +#define MAX_SLOTS 16 /* must be > 2 and < 256 */ +#define MAX_HDR 128 + +/* + * Compressed packet format: + * + * The first octet contains the packet type (top 3 bits), TCP + * 'push' bit, and flags that indicate which of the 4 TCP sequence + * numbers have changed (bottom 5 bits). The next octet is a + * conversation number that associates a saved IP/TCP header with + * the compressed packet. The next two octets are the TCP checksum + * from the original datagram. The next 0 to 15 octets are + * sequence number changes, one change per bit set in the header + * (there may be no changes and there are two special cases where + * the receiver implicitly knows what changed -- see below). + * + * There are 5 numbers which can change (they are always inserted + * in the following order): TCP urgent pointer, window, + * acknowlegement, sequence number and IP ID. (The urgent pointer + * is different from the others in that its value is sent, not the + * change in value.) Since typical use of SLIP links is biased + * toward small packets (see comments on MTU/MSS below), changes + * use a variable length coding with one octet for numbers in the + * range 1 - 255 and 3 octets (0, MSB, LSB) for numbers in the + * range 256 - 65535 or 0. (If the change in sequence number or + * ack is more than 65535, an uncompressed packet is sent.) + */ + +/* + * Packet types (must not conflict with IP protocol version) + * + * The top nibble of the first octet is the packet type. There are + * three possible types: IP (not proto TCP or tcp with one of the + * control flags set); uncompressed TCP (a normal IP/TCP packet but + * with the 8-bit protocol field replaced by an 8-bit connection id -- + * this type of packet syncs the sender & receiver); and compressed + * TCP (described above). + * + * LSB of 4-bit field is TCP "PUSH" bit (a worthless anachronism) and + * is logically part of the 4-bit "changes" field that follows. Top + * three bits are actual packet type. For backward compatibility + * and in the interest of conserving bits, numbers are chosen so the + * IP protocol version number (4) which normally appears in this nibble + * means "IP packet". + */ + +/* packet types */ +#define TYPE_IP 0x40 +#define TYPE_UNCOMPRESSED_TCP 0x70 +#define TYPE_COMPRESSED_TCP 0x80 +#define TYPE_ERROR 0x00 + +/* Bits in first octet of compressed packet */ +#define NEW_C 0x40 /* flag bits for what changed in a packet */ +#define NEW_I 0x20 +#define NEW_S 0x08 +#define NEW_A 0x04 +#define NEW_W 0x02 +#define NEW_U 0x01 + +/* reserved, special-case values of above */ +#define SPECIAL_I (NEW_S|NEW_W|NEW_U) /* echoed interactive traffic */ +#define SPECIAL_D (NEW_S|NEW_A|NEW_W|NEW_U) /* unidirectional data */ +#define SPECIALS_MASK (NEW_S|NEW_A|NEW_W|NEW_U) + +#define TCP_PUSH_BIT 0x10 + + +/* + * "state" data for each active tcp conversation on the wire. This is + * basically a copy of the entire IP/TCP header from the last packet + * we saw from the conversation together with a small identifier + * the transmit & receive ends of the line use to locate saved header. + */ +struct cstate { + struct cstate *cs_next; /* next most recently used state (xmit only) */ + u_short cs_hlen; /* size of hdr (receive only) */ + u_char cs_id; /* connection # associated with this state */ + u_char cs_filler; + union { + char csu_hdr[MAX_HDR]; + struct ip csu_ip; /* ip/tcp hdr from most recent packet */ + } vjcs_u; +}; +#define cs_ip vjcs_u.csu_ip +#define cs_hdr vjcs_u.csu_hdr + + +struct vjstat { + unsigned long vjs_packets; /* outbound packets */ + unsigned long vjs_compressed; /* outbound compressed packets */ + unsigned long vjs_searches; /* searches for connection state */ + unsigned long vjs_misses; /* times couldn't find conn. state */ + unsigned long vjs_uncompressedin; /* inbound uncompressed packets */ + unsigned long vjs_compressedin; /* inbound compressed packets */ + unsigned long vjs_errorin; /* inbound unknown type packets */ + unsigned long vjs_tossed; /* inbound packets tossed because of error */ +}; + +/* + * all the state data for one serial line (we need one of these per line). + */ +struct vjcompress { + struct cstate *last_cs; /* most recently used tstate */ + u_char last_recv; /* last rcvd conn. id */ + u_char last_xmit; /* last sent conn. id */ + u_short flags; + u_char maxSlotIndex; + u_char compressSlot; /* Flag indicating OK to compress slot ID. */ +#if LINK_STATS + struct vjstat stats; +#endif + struct cstate tstate[MAX_SLOTS]; /* xmit connection states */ + struct cstate rstate[MAX_SLOTS]; /* receive connection states */ +}; + +/* flag values */ +#define VJF_TOSS 1U /* tossing rcvd frames because of input err */ + +extern void vj_compress_init (struct vjcompress *comp); +extern u_int vj_compress_tcp (struct vjcompress *comp, struct pbuf *pb); +extern void vj_uncompress_err (struct vjcompress *comp); +extern int vj_uncompress_uncomp(struct pbuf *nb, struct vjcompress *comp); +extern int vj_uncompress_tcp(struct pbuf **nb, struct vjcompress *comp); + +#endif /* VJ_H */ diff --git a/20080212/Demo/Common/ethernet/lwIP/netif/ppp/vjbsdhdr.h b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/vjbsdhdr.h new file mode 100644 index 000000000..a7d180c16 --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/netif/ppp/vjbsdhdr.h @@ -0,0 +1,76 @@ +#ifndef VJBSDHDR_H +#define VJBSDHDR_H + +#include "lwip/tcp.h" + + +/* + * Structure of an internet header, naked of options. + * + * We declare ip_len and ip_off to be short, rather than u_short + * pragmatically since otherwise unsigned comparisons can result + * against negative integers quite easily, and fail in subtle ways. + */ +PACK_STRUCT_BEGIN +struct ip +{ +#if defined(NO_CHAR_BITFIELDS) + u_char ip_hl_v; /* bug in GCC for mips means the bitfield stuff will sometimes break - so we use a char for both and get round it with macro's instead... */ +#else +#if BYTE_ORDER == LITTLE_ENDIAN + unsigned ip_hl:4, /* header length */ + ip_v:4; /* version */ +#elif BYTE_ORDER == BIG_ENDIAN + unsigned ip_v:4, /* version */ + ip_hl:4; /* header length */ +#else + COMPLAIN - NO BYTE ORDER SELECTED! +#endif +#endif + u_char ip_tos; /* type of service */ + u_short ip_len; /* total length */ + u_short ip_id; /* identification */ + u_short ip_off; /* fragment offset field */ +#define IP_DF 0x4000 /* dont fragment flag */ +#define IP_MF 0x2000 /* more fragments flag */ +#define IP_OFFMASK 0x1fff /* mask for fragmenting bits */ + u_char ip_ttl; /* time to live */ + u_char ip_p; /* protocol */ + u_short ip_sum; /* checksum */ + struct in_addr ip_src,ip_dst; /* source and dest address */ +}; +PACK_STRUCT_END + +typedef u32_t tcp_seq; + +/* + * TCP header. + * Per RFC 793, September, 1981. + */ +PACK_STRUCT_BEGIN +struct tcphdr +{ + u_short th_sport; /* source port */ + u_short th_dport; /* destination port */ + tcp_seq th_seq; /* sequence number */ + tcp_seq th_ack; /* acknowledgement number */ +#if defined(NO_CHAR_BITFIELDS) + u_char th_x2_off; +#else +#if BYTE_ORDER == LITTLE_ENDIAN + unsigned th_x2:4, /* (unused) */ + th_off:4; /* data offset */ +#endif +#if BYTE_ORDER == BIG_ENDIAN + unsigned th_off:4, /* data offset */ + th_x2:4; /* (unused) */ +#endif +#endif + u_char th_flags; + u_short th_win; /* window */ + u_short th_sum; /* checksum */ + u_short th_urp; /* urgent pointer */ +}; +PACK_STRUCT_END + +#endif /* VJBSDHDR_H */ diff --git a/20080212/Demo/Common/ethernet/lwIP/netif/slipif.c b/20080212/Demo/Common/ethernet/lwIP/netif/slipif.c new file mode 100644 index 000000000..ba8510b0d --- /dev/null +++ b/20080212/Demo/Common/ethernet/lwIP/netif/slipif.c @@ -0,0 +1,213 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is built upon the file: src/arch/rtxc/netif/sioslip.c + * + * Author: Magnus Ivarsson + */ + +/* + * This is an arch independent SLIP netif. The specific serial hooks must be + * provided by another file. They are sio_open, sio_recv and sio_send + */ + +#include "netif/slipif.h" +#include "lwip/opt.h" +#include "lwip/def.h" +#include "lwip/pbuf.h" +#include "lwip/sys.h" +#include "lwip/stats.h" +#include "lwip/sio.h" + +#define SLIP_END 0300 +#define SLIP_ESC 0333 +#define SLIP_ESC_END 0334 +#define SLIP_ESC_ESC 0335 + +#define MAX_SIZE 1500 + +/** + * Send a pbuf doing the necessary SLIP encapsulation + * + * Uses the serial layer's sio_send() + */ +err_t +slipif_output(struct netif *netif, struct pbuf *p, struct ip_addr *ipaddr) +{ + struct pbuf *q; + u16_t i; + u8_t c; + + /* Send pbuf out on the serial I/O device. */ + sio_send(SLIP_END, netif->state); + + for (q = p; q != NULL; q = q->next) { + for (i = 0; i < q->len; i++) { + c = ((u8_t *)q->payload)[i]; + switch (c) { + case SLIP_END: + sio_send(SLIP_ESC, netif->state); + sio_send(SLIP_ESC_END, netif->state); + break; + case SLIP_ESC: + sio_send(SLIP_ESC, netif->state); + sio_send(SLIP_ESC_ESC, netif->state); + break; + default: + sio_send(c, netif->state); + break; + } + } + } + sio_send(SLIP_END, netif->state); + return 0; +} + +/** + * Handle the incoming SLIP stream character by character + * + * Poll the serial layer by calling sio_recv() + * + * @return The IP packet when SLIP_END is received + */ +static struct pbuf * +slipif_input(struct netif *netif) +{ + u8_t c; + struct pbuf *p, *q; + u16_t recved; + u16_t i; + + q = p = NULL; + recved = i = 0; + c = 0; + + while (1) { + c = sio_recv(netif->state); + switch (c) { + case SLIP_END: + if (recved > 0) { + /* Received whole packet. */ + pbuf_realloc(q, recved); + + LINK_STATS_INC(link.recv); + + LWIP_DEBUGF(SLIP_DEBUG, ("slipif: Got packet\n")); + return q; + } + break; + + case SLIP_ESC: + c = sio_recv(netif->state); + switch (c) { + case SLIP_ESC_END: + c = SLIP_END; + break; + case SLIP_ESC_ESC: + c = SLIP_ESC; + break; + } + /* FALLTHROUGH */ + + default: + if (p == NULL) { + LWIP_DEBUGF(SLIP_DEBUG, ("slipif_input: alloc\n")); + p = pbuf_alloc(PBUF_LINK, PBUF_POOL_BUFSIZE, PBUF_POOL); + + if (p == NULL) { + LINK_STATS_INC(link.drop); + LWIP_DEBUGF(SLIP_DEBUG, ("slipif_input: no new pbuf! (DROP)\n")); + } + + if (q != NULL) { + pbuf_cat(q, p); + } else { + q = p; + } + } + if (p != NULL && recved < MAX_SIZE) { + ((u8_t *)p->payload)[i] = c; + recved++; + i++; + if (i >= p->len) { + i = 0; + if (p->next != NULL && p->next->len > 0) + p = p->next; + else + p = NULL; + } + } + break; + } + + } + return NULL; +} + +/** + * The SLIP input thread. + * + * Feed the IP layer with incoming packets + */ +static void +slipif_loop(void *nf) +{ + struct pbuf *p; + struct netif *netif = (struct netif *)nf; + + while (1) { + p = slipif_input(netif); + netif->input(p, netif); + } +} + +/** + * SLIP netif initialization + * + * Call the arch specific sio_open and remember + * the opened device in the state field of the netif. + */ +err_t +slipif_init(struct netif *netif) +{ + + LWIP_DEBUGF(SLIP_DEBUG, ("slipif_init: netif->num=%"U16_F"\n", (u16_t)netif->num)); + + netif->name[0] = 's'; + netif->name[1] = 'l'; + netif->output = slipif_output; + netif->mtu = 1500; + netif->flags = NETIF_FLAG_POINTTOPOINT; + + netif->state = sio_open(netif->num); + if (!netif->state) + return ERR_IF; + + sys_thread_new(slipif_loop, netif, SLIPIF_THREAD_PRIO); + return ERR_OK; +} diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/README b/20080212/Demo/Common/ethernet/uIP/uip-1.0/README new file mode 100644 index 000000000..909f6520f --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/README @@ -0,0 +1,13 @@ +uIP is a very small implementation of the TCP/IP stack that is written +by Adam Dunkels . More information can be obtained +at the uIP homepage at http://www.sics.se/~adam/uip/. + +This is version $Name: uip-1-0 $. + +The directory structure look as follows: + +apps/ - Example applications +doc/ - Documentation +lib/ - Library code used by some applications +uip/ - uIP TCP/IP stack code +unix/ - uIP as a user space process under FreeBSD or Linux diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/README b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/README new file mode 100644 index 000000000..f88920952 --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/README @@ -0,0 +1,2 @@ +This directory contains a few example applications. They are not all +heavily tested, however. diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/Makefile.webserver b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/Makefile.webserver new file mode 100644 index 000000000..f38c47a72 --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/Makefile.webserver @@ -0,0 +1 @@ +APP_SOURCES += httpd.c http-strings.c httpd-fs.c httpd-cgi.c diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/http-strings b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/http-strings new file mode 100644 index 000000000..0d3c30cdd --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/http-strings @@ -0,0 +1,35 @@ +http_http "http://" +http_200 "200 " +http_301 "301 " +http_302 "302 " +http_get "GET " +http_10 "HTTP/1.0" +http_11 "HTTP/1.1" +http_content_type "content-type: " +http_texthtml "text/html" +http_location "location: " +http_host "host: " +http_crnl "\r\n" +http_index_html "/index.html" +http_404_html "/404.html" +http_referer "Referer:" +http_header_200 "HTTP/1.0 200 OK\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" +http_header_404 "HTTP/1.0 404 Not found\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" +http_content_type_plain "Content-type: text/plain\r\n\r\n" +http_content_type_html "Content-type: text/html\r\n\r\n" +http_content_type_css "Content-type: text/css\r\n\r\n" +http_content_type_text "Content-type: text/text\r\n\r\n" +http_content_type_png "Content-type: image/png\r\n\r\n" +http_content_type_gif "Content-type: image/gif\r\n\r\n" +http_content_type_jpg "Content-type: image/jpeg\r\n\r\n" +http_content_type_binary "Content-type: application/octet-stream\r\n\r\n" +http_html ".html" +http_shtml ".shtml" +http_htm ".htm" +http_css ".css" +http_png ".png" +http_gif ".gif" +http_jpg ".jpg" +http_text ".txt" +http_txt ".txt" + diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/http-strings.c b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/http-strings.c new file mode 100644 index 000000000..ef7a41c7d --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/http-strings.c @@ -0,0 +1,102 @@ +const char http_http[8] = +/* "http://" */ +{0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, }; +const char http_200[5] = +/* "200 " */ +{0x32, 0x30, 0x30, 0x20, }; +const char http_301[5] = +/* "301 " */ +{0x33, 0x30, 0x31, 0x20, }; +const char http_302[5] = +/* "302 " */ +{0x33, 0x30, 0x32, 0x20, }; +const char http_get[5] = +/* "GET " */ +{0x47, 0x45, 0x54, 0x20, }; +const char http_10[9] = +/* "HTTP/1.0" */ +{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, }; +const char http_11[9] = +/* "HTTP/1.1" */ +{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x31, }; +const char http_content_type[15] = +/* "content-type: " */ +{0x63, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, }; +const char http_texthtml[10] = +/* "text/html" */ +{0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_location[11] = +/* "location: " */ +{0x6c, 0x6f, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, }; +const char http_host[7] = +/* "host: " */ +{0x68, 0x6f, 0x73, 0x74, 0x3a, 0x20, }; +const char http_crnl[3] = +/* "\r\n" */ +{0xd, 0xa, }; +const char http_index_html[12] = +/* "/index.html" */ +{0x2f, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_404_html[10] = +/* "/404.html" */ +{0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_referer[9] = +/* "Referer:" */ +{0x52, 0x65, 0x66, 0x65, 0x72, 0x65, 0x72, 0x3a, }; +const char http_header_200[84] = +/* "HTTP/1.0 200 OK\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */ +{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x32, 0x30, 0x30, 0x20, 0x4f, 0x4b, 0xd, 0xa, 0x53, 0x65, 0x72, 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x73, 0x69, 0x63, 0x73, 0x2e, 0x73, 0x65, 0x2f, 0x7e, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, 0x70, 0x2f, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0xd, 0xa, }; +const char http_header_404[91] = +/* "HTTP/1.0 404 Not found\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */ +{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x34, 0x30, 0x34, 0x20, 0x4e, 0x6f, 0x74, 0x20, 0x66, 0x6f, 0x75, 0x6e, 0x64, 0xd, 0xa, 0x53, 0x65, 0x72, 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x73, 0x69, 0x63, 0x73, 0x2e, 0x73, 0x65, 0x2f, 0x7e, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, 0x70, 0x2f, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0xd, 0xa, }; +const char http_content_type_plain[29] = +/* "Content-type: text/plain\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x70, 0x6c, 0x61, 0x69, 0x6e, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_html[28] = +/* "Content-type: text/html\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_css [27] = +/* "Content-type: text/css\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x63, 0x73, 0x73, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_text[28] = +/* "Content-type: text/text\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x74, 0x65, 0x78, 0x74, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_png [28] = +/* "Content-type: image/png\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x70, 0x6e, 0x67, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_gif [28] = +/* "Content-type: image/gif\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x67, 0x69, 0x66, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_jpg [29] = +/* "Content-type: image/jpeg\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x6a, 0x70, 0x65, 0x67, 0xd, 0xa, 0xd, 0xa, }; +const char http_content_type_binary[43] = +/* "Content-type: application/octet-stream\r\n\r\n" */ +{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x61, 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x2f, 0x6f, 0x63, 0x74, 0x65, 0x74, 0x2d, 0x73, 0x74, 0x72, 0x65, 0x61, 0x6d, 0xd, 0xa, 0xd, 0xa, }; +const char http_html[6] = +/* ".html" */ +{0x2e, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_shtml[7] = +/* ".shtml" */ +{0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, }; +const char http_htm[5] = +/* ".htm" */ +{0x2e, 0x68, 0x74, 0x6d, }; +const char http_css[5] = +/* ".css" */ +{0x2e, 0x63, 0x73, 0x73, }; +const char http_png[5] = +/* ".png" */ +{0x2e, 0x70, 0x6e, 0x67, }; +const char http_gif[5] = +/* ".gif" */ +{0x2e, 0x67, 0x69, 0x66, }; +const char http_jpg[5] = +/* ".jpg" */ +{0x2e, 0x6a, 0x70, 0x67, }; +const char http_text[5] = +/* ".txt" */ +{0x2e, 0x74, 0x78, 0x74, }; +const char http_txt[5] = +/* ".txt" */ +{0x2e, 0x74, 0x78, 0x74, }; diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/http-strings.h b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/http-strings.h new file mode 100644 index 000000000..acbe7e17f --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/http-strings.h @@ -0,0 +1,34 @@ +extern const char http_http[8]; +extern const char http_200[5]; +extern const char http_301[5]; +extern const char http_302[5]; +extern const char http_get[5]; +extern const char http_10[9]; +extern const char http_11[9]; +extern const char http_content_type[15]; +extern const char http_texthtml[10]; +extern const char http_location[11]; +extern const char http_host[7]; +extern const char http_crnl[3]; +extern const char http_index_html[12]; +extern const char http_404_html[10]; +extern const char http_referer[9]; +extern const char http_header_200[84]; +extern const char http_header_404[91]; +extern const char http_content_type_plain[29]; +extern const char http_content_type_html[28]; +extern const char http_content_type_css [27]; +extern const char http_content_type_text[28]; +extern const char http_content_type_png [28]; +extern const char http_content_type_gif [28]; +extern const char http_content_type_jpg [29]; +extern const char http_content_type_binary[43]; +extern const char http_html[6]; +extern const char http_shtml[7]; +extern const char http_htm[5]; +extern const char http_css[5]; +extern const char http_png[5]; +extern const char http_gif[5]; +extern const char http_jpg[5]; +extern const char http_text[5]; +extern const char http_txt[5]; diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-cgi.c b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-cgi.c new file mode 100644 index 000000000..f845c7aa8 --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-cgi.c @@ -0,0 +1,203 @@ +/** + * \addtogroup httpd + * @{ + */ + +/** + * \file + * Web server script interface + * \author + * Adam Dunkels + * + */ + +/* + * Copyright (c) 2001-2006, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: httpd-cgi.c,v 1.2 2006/06/11 21:46:37 adam Exp $ + * + */ + +#include "uip.h" +#include "psock.h" +#include "httpd.h" +#include "httpd-cgi.h" +#include "httpd-fs.h" + +#include +#include + +HTTPD_CGI_CALL(file, "file-stats", file_stats); +HTTPD_CGI_CALL(tcp, "tcp-connections", tcp_stats); +HTTPD_CGI_CALL(net, "net-stats", net_stats); + +static const struct httpd_cgi_call *calls[] = { &file, &tcp, &net, NULL }; + +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(nullfunction(struct httpd_state *s, char *ptr)) +{ + PSOCK_BEGIN(&s->sout); + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +httpd_cgifunction +httpd_cgi(char *name) +{ + const struct httpd_cgi_call **f; + + /* Find the matching name in the table, return the function. */ + for(f = calls; *f != NULL; ++f) { + if(strncmp((*f)->name, name, strlen((*f)->name)) == 0) { + return (*f)->function; + } + } + return nullfunction; +} +/*---------------------------------------------------------------------------*/ +static unsigned short +generate_file_stats(void *arg) +{ + char *f = (char *)arg; + return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, "%5u", httpd_fs_count(f)); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(file_stats(struct httpd_state *s, char *ptr)) +{ + PSOCK_BEGIN(&s->sout); + + PSOCK_GENERATOR_SEND(&s->sout, generate_file_stats, strchr(ptr, ' ') + 1); + + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +static const char closed[] = /* "CLOSED",*/ +{0x43, 0x4c, 0x4f, 0x53, 0x45, 0x44, 0}; +static const char syn_rcvd[] = /* "SYN-RCVD",*/ +{0x53, 0x59, 0x4e, 0x2d, 0x52, 0x43, 0x56, + 0x44, 0}; +static const char syn_sent[] = /* "SYN-SENT",*/ +{0x53, 0x59, 0x4e, 0x2d, 0x53, 0x45, 0x4e, + 0x54, 0}; +static const char established[] = /* "ESTABLISHED",*/ +{0x45, 0x53, 0x54, 0x41, 0x42, 0x4c, 0x49, 0x53, 0x48, + 0x45, 0x44, 0}; +static const char fin_wait_1[] = /* "FIN-WAIT-1",*/ +{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49, + 0x54, 0x2d, 0x31, 0}; +static const char fin_wait_2[] = /* "FIN-WAIT-2",*/ +{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49, + 0x54, 0x2d, 0x32, 0}; +static const char closing[] = /* "CLOSING",*/ +{0x43, 0x4c, 0x4f, 0x53, 0x49, + 0x4e, 0x47, 0}; +static const char time_wait[] = /* "TIME-WAIT,"*/ +{0x54, 0x49, 0x4d, 0x45, 0x2d, 0x57, 0x41, + 0x49, 0x54, 0}; +static const char last_ack[] = /* "LAST-ACK"*/ +{0x4c, 0x41, 0x53, 0x54, 0x2d, 0x41, 0x43, + 0x4b, 0}; + +static const char *states[] = { + closed, + syn_rcvd, + syn_sent, + established, + fin_wait_1, + fin_wait_2, + closing, + time_wait, + last_ack}; + + +static unsigned short +generate_tcp_stats(void *arg) +{ + struct uip_conn *conn; + struct httpd_state *s = (struct httpd_state *)arg; + + conn = &uip_conns[s->count]; + return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, + "

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\r\n", + htons(conn->lport), + htons(conn->ripaddr[0]) >> 8, + htons(conn->ripaddr[0]) & 0xff, + htons(conn->ripaddr[1]) >> 8, + htons(conn->ripaddr[1]) & 0xff, + htons(conn->rport), + states[conn->tcpstateflags & UIP_TS_MASK], + conn->nrtx, + conn->timer, + (uip_outstanding(conn))? '*':' ', + (uip_stopped(conn))? '!':' '); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(tcp_stats(struct httpd_state *s, char *ptr)) +{ + + PSOCK_BEGIN(&s->sout); + + for(s->count = 0; s->count < UIP_CONNS; ++s->count) { + if((uip_conns[s->count].tcpstateflags & UIP_TS_MASK) != UIP_CLOSED) { + PSOCK_GENERATOR_SEND(&s->sout, generate_tcp_stats, s); + } + } + + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +static unsigned short +generate_net_stats(void *arg) +{ + struct httpd_state *s = (struct httpd_state *)arg; + return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, + "%5u\n", ((uip_stats_t *)&uip_stat)[s->count]); +} + +static +PT_THREAD(net_stats(struct httpd_state *s, char *ptr)) +{ + PSOCK_BEGIN(&s->sout); + +#if UIP_STATISTICS + + for(s->count = 0; s->count < sizeof(uip_stat) / sizeof(uip_stats_t); + ++s->count) { + PSOCK_GENERATOR_SEND(&s->sout, generate_net_stats, s); + } + +#endif /* UIP_STATISTICS */ + + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +/** @} */ diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-cgi.h b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-cgi.h new file mode 100644 index 000000000..7ae928321 --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-cgi.h @@ -0,0 +1,84 @@ +/** + * \addtogroup httpd + * @{ + */ + +/** + * \file + * Web server script interface header file + * \author + * Adam Dunkels + * + */ + + + +/* + * Copyright (c) 2001, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: httpd-cgi.h,v 1.2 2006/06/11 21:46:38 adam Exp $ + * + */ + +#ifndef __HTTPD_CGI_H__ +#define __HTTPD_CGI_H__ + +#include "psock.h" +#include "httpd.h" + +typedef PT_THREAD((* httpd_cgifunction)(struct httpd_state *, char *)); + +httpd_cgifunction httpd_cgi(char *name); + +struct httpd_cgi_call { + const char *name; + const httpd_cgifunction function; +}; + +/** + * \brief HTTPD CGI function declaration + * \param name The C variable name of the function + * \param str The string name of the function, used in the script file + * \param function A pointer to the function that implements it + * + * This macro is used for declaring a HTTPD CGI + * function. This function is then added to the list of + * HTTPD CGI functions with the httpd_cgi_add() function. + * + * \hideinitializer + */ +#define HTTPD_CGI_CALL(name, str, function) \ +static PT_THREAD(function(struct httpd_state *, char *)); \ +static const struct httpd_cgi_call name = {str, function} + +void httpd_cgi_init(void); +#endif /* __HTTPD_CGI_H__ */ + +/** @} */ diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs.c b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs.c new file mode 100644 index 000000000..dc4aef011 --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs.c @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: httpd-fs.c,v 1.1 2006/06/07 09:13:08 adam Exp $ + */ + +#include "httpd.h" +#include "httpd-fs.h" +#include "httpd-fsdata.h" + +#ifndef NULL +#define NULL 0 +#endif /* NULL */ + +#include "httpd-fsdata.c" + +#if HTTPD_FS_STATISTICS +static u16_t count[HTTPD_FS_NUMFILES]; +#endif /* HTTPD_FS_STATISTICS */ + +/*-----------------------------------------------------------------------------------*/ +static u8_t +httpd_fs_strcmp(const char *str1, const char *str2) +{ + u8_t i; + i = 0; + loop: + + if(str2[i] == 0 || + str1[i] == '\r' || + str1[i] == '\n') { + return 0; + } + + if(str1[i] != str2[i]) { + return 1; + } + + + ++i; + goto loop; +} +/*-----------------------------------------------------------------------------------*/ +int +httpd_fs_open(const char *name, struct httpd_fs_file *file) +{ +#if HTTPD_FS_STATISTICS + u16_t i = 0; +#endif /* HTTPD_FS_STATISTICS */ + struct httpd_fsdata_file_noconst *f; + + for(f = (struct httpd_fsdata_file_noconst *)HTTPD_FS_ROOT; + f != NULL; + f = (struct httpd_fsdata_file_noconst *)f->next) { + + if(httpd_fs_strcmp(name, f->name) == 0) { + file->data = f->data; + file->len = f->len; +#if HTTPD_FS_STATISTICS + ++count[i]; +#endif /* HTTPD_FS_STATISTICS */ + return 1; + } +#if HTTPD_FS_STATISTICS + ++i; +#endif /* HTTPD_FS_STATISTICS */ + + } + return 0; +} +/*-----------------------------------------------------------------------------------*/ +void +httpd_fs_init(void) +{ +#if HTTPD_FS_STATISTICS + u16_t i; + for(i = 0; i < HTTPD_FS_NUMFILES; i++) { + count[i] = 0; + } +#endif /* HTTPD_FS_STATISTICS */ +} +/*-----------------------------------------------------------------------------------*/ +#if HTTPD_FS_STATISTICS +u16_t httpd_fs_count +(char *name) +{ + struct httpd_fsdata_file_noconst *f; + u16_t i; + + i = 0; + for(f = (struct httpd_fsdata_file_noconst *)HTTPD_FS_ROOT; + f != NULL; + f = (struct httpd_fsdata_file_noconst *)f->next) { + + if(httpd_fs_strcmp(name, f->name) == 0) { + return count[i]; + } + ++i; + } + return 0; +} +#endif /* HTTPD_FS_STATISTICS */ +/*-----------------------------------------------------------------------------------*/ diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs.h b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs.h new file mode 100644 index 000000000..b594eea56 --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: httpd-fs.h,v 1.1 2006/06/07 09:13:08 adam Exp $ + */ +#ifndef __HTTPD_FS_H__ +#define __HTTPD_FS_H__ + +#define HTTPD_FS_STATISTICS 1 + +struct httpd_fs_file { + char *data; + int len; +}; + +/* file must be allocated by caller and will be filled in + by the function. */ +int httpd_fs_open(const char *name, struct httpd_fs_file *file); + +#ifdef HTTPD_FS_STATISTICS +#if HTTPD_FS_STATISTICS == 1 +u16_t httpd_fs_count(char *name); +#endif /* HTTPD_FS_STATISTICS */ +#endif /* HTTPD_FS_STATISTICS */ + +void httpd_fs_init(void); + +#endif /* __HTTPD_FS_H__ */ diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/404.html b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/404.html new file mode 100644 index 000000000..43e7f4cad --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/404.html @@ -0,0 +1,8 @@ + + + + + \ No newline at end of file diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/fade.png b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/fade.png new file mode 100644 index 0000000000000000000000000000000000000000..a9e69f75deda76937ede6e5d6d3bc94b8d43375e GIT binary patch literal 196 zcmeAS@N?(olHy`uVBq!ia0vp^EI`b~!2~2_W@bbJDb50q$YKTtZeb8+WSBKa0w~B{ z;_2(kevOSoMA~wF^nu4fA=whwh!W@g+}zZ>5(ej@)Wnk16ovB4k_?5Aj8p}8Pv3y| zDXMuug;t&}jv*Y^OM4837z6~4=$X%RNd5c2`3sj!Z^-PEXJ*+>C@xH&c%{T_Whmnh n&4?5GJ&rV%a4+Vsxy|yzf%X2v&wqfbP0l+XkKD_%S1 literal 0 HcmV?d00001 diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/files.shtml b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/files.shtml new file mode 100644 index 000000000..361cc1dc1 --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/files.shtml @@ -0,0 +1,35 @@ +%!: /header.html +

File statistics

+
+
+

404 - file not found

+

Go here instead.

+
LocalRemoteStateRetransmissionsTimerFlags
%d%u.%u.%u.%u:%u%s%u%u%c %c
+ + + + + + + + + + + + + + +
/index.html%! file-stats /index.html +
/files.shtml%! file-stats /files.shtml +
/tcp.shtml%! file-stats /tcp.shtml +
/stats.shtml%! file-stats /stats.shtml +
/style.css%! file-stats /style.css +
/404.html%! file-stats /404.html +
/fade.png%! file-stats /fade.png +
+ +%!: /footer.html diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/footer.html b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/footer.html new file mode 100644 index 000000000..290832ddc --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/footer.html @@ -0,0 +1,2 @@ + + \ No newline at end of file diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/header.html b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/header.html new file mode 100644 index 000000000..0c3c4efa9 --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/header.html @@ -0,0 +1,18 @@ + + + + Welcome to the uIP web server! + + + + +

+
Front page
+
File statistics
+
Network statistics
+
Network + connections
+
+
+ +
diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/index.html b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/index.html new file mode 100644 index 000000000..7af64c8df --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/index.html @@ -0,0 +1,29 @@ + + + + Welcome to the uIP web server! + + + + +
+
Front page
+
File statistics
+
Network statistics
+
Network + connections
+
+
+ +
+

+ These web pages are served by a small web server running on top of + the uIP embedded TCP/IP + stack. +

+

+ Click on the links above for web server statistics. +

+ + + diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/processes.shtml b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/processes.shtml new file mode 100644 index 000000000..be857f9eb --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/processes.shtml @@ -0,0 +1,5 @@ +%!: /header.html +

System processes


+ +%! processes +%!: /footer.html \ No newline at end of file diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/stats.shtml b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/stats.shtml new file mode 100644 index 000000000..7eb381af9 --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/stats.shtml @@ -0,0 +1,31 @@ +%!: /header.html +

Network statistics

+
+
IDNamePriorityPoll handlerEvent handlerProcstate
+
+IP           Packets received
+             Packets sent
+	     Packets dropped
+IP errors    IP version/header length
+             IP length, high byte
+             IP length, low byte
+             IP fragments
+             Header checksum
+             Wrong protocol
+ICMP	     Packets received
+             Packets sent
+             Packets dropped
+             Type errors
+TCP          Packets received
+             Packets sent
+             Packets dropped
+             Checksum errors
+             Data packets without ACKs
+             Resets
+             Retransmissions
+	     No connection avaliable
+	     Connection attempts to closed ports
+
%! net-stats
+
+ +%!: /footer.html diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/style.css b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/style.css new file mode 100644 index 000000000..089fe84f2 --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/style.css @@ -0,0 +1,92 @@ +h1 +{ + text-align: center; + font-size:14pt; + font-family:arial,helvetica; + font-weight:bold; + padding:10px; +} + +body +{ + + background-color: #fffeec; + color:black; + + font-size:8pt; + font-family:arial,helvetica; +} + +.menu +{ + margin: 4px; + width:60%; + + padding:2px; + + border: solid 1px; + background-color: #fffcd2; + text-align:left; + + font-size:9pt; + font-family:arial,helvetica; +} + +div.menubox +{ + width: 25%; + border: 0; + float: left; +text-align: center; +} + +.contentblock +{ + margin: 4px; + width:60%; + + padding:2px; + + border: 1px dotted; + background-color: white; + + font-size:8pt; + font-family:arial,helvetica; + +} + +p.intro +{ + margin-left:20px; + margin-right:20px; + + font-size:10pt; +/* font-weight:bold; */ + font-family:arial,helvetica; +} + +p.clink +{ + font-size:12pt; + font-family:courier,monospace; + text-align:center; +} + +p.clink9 +{ + font-size:9pt; + font-family:courier,monospace; + text-align:center; +} + + +p +{ + padding-left:10px; +} + +p.right +{ + text-align:right; +} + diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/tcp.shtml b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/tcp.shtml new file mode 100644 index 000000000..2404aedf0 --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/tcp.shtml @@ -0,0 +1,5 @@ +%!: /header.html +

Current connections


+ +%! tcp-connections +%!: /footer.html \ No newline at end of file diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fsdata.c b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fsdata.c new file mode 100644 index 000000000..29e5a1b96 --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fsdata.c @@ -0,0 +1,607 @@ +static const unsigned char data_processes_shtml[] = { + /* /processes.shtml */ + 0x2f, 0x70, 0x72, 0x6f, 0x63, 0x65, 0x73, 0x73, 0x65, 0x73, 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0, + 0x25, 0x21, 0x3a, 0x20, 0x2f, 0x68, 0x65, 0x61, 0x64, 0x65, + 0x72, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0xa, 0x3c, 0x68, 0x31, + 0x3e, 0x53, 0x79, 0x73, 0x74, 0x65, 0x6d, 0x20, 0x70, 0x72, + 0x6f, 0x63, 0x65, 0x73, 0x73, 0x65, 0x73, 0x3c, 0x2f, 0x68, + 0x31, 0x3e, 0x3c, 0x62, 0x72, 0x3e, 0x3c, 0x74, 0x61, 0x62, + 0x6c, 0x65, 0x20, 0x77, 0x69, 0x64, 0x74, 0x68, 0x3d, 0x22, + 0x31, 0x30, 0x30, 0x25, 0x22, 0x3e, 0xa, 0x3c, 0x74, 0x72, + 0x3e, 0x3c, 0x74, 0x68, 0x3e, 0x49, 0x44, 0x3c, 0x2f, 0x74, + 0x68, 0x3e, 0x3c, 0x74, 0x68, 0x3e, 0x4e, 0x61, 0x6d, 0x65, + 0x3c, 0x2f, 0x74, 0x68, 0x3e, 0x3c, 0x74, 0x68, 0x3e, 0x50, + 0x72, 0x69, 0x6f, 0x72, 0x69, 0x74, 0x79, 0x3c, 0x2f, 0x74, + 0x68, 0x3e, 0x3c, 0x74, 0x68, 0x3e, 0x50, 0x6f, 0x6c, 0x6c, + 0x20, 0x68, 0x61, 0x6e, 0x64, 0x6c, 0x65, 0x72, 0x3c, 0x2f, + 0x74, 0x68, 0x3e, 0x3c, 0x74, 0x68, 0x3e, 0x45, 0x76, 0x65, + 0x6e, 0x74, 0x20, 0x68, 0x61, 0x6e, 0x64, 0x6c, 0x65, 0x72, + 0x3c, 0x2f, 0x74, 0x68, 0x3e, 0x3c, 0x74, 0x68, 0x3e, 0x50, + 0x72, 0x6f, 0x63, 0x73, 0x74, 0x61, 0x74, 0x65, 0x3c, 0x2f, + 0x74, 0x68, 0x3e, 0x3c, 0x2f, 0x74, 0x72, 0x3e, 0xa, 0x25, + 0x21, 0x20, 0x70, 0x72, 0x6f, 0x63, 0x65, 0x73, 0x73, 0x65, + 0x73, 0xa, 0x25, 0x21, 0x3a, 0x20, 0x2f, 0x66, 0x6f, 0x6f, + 0x74, 0x65, 0x72, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0}; + +static const unsigned char data_404_html[] = { + /* /404.html */ + 0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0, + 0x3c, 0x68, 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0x6d, 0x69, 0x73, 0x73, 0x69, + 0x6f, 0x6e, 0x73, 0xa, 0x9, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x4e, 0x6f, 0x20, 0x63, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, + 0x69, 0x6f, 0x6e, 0x20, 0x61, 0x76, 0x61, 0x6c, 0x69, 0x61, + 0x62, 0x6c, 0x65, 0xa, 0x9, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, + 0x20, 0x61, 0x74, 0x74, 0x65, 0x6d, 0x70, 0x74, 0x73, 0x20, + 0x74, 0x6f, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0x64, 0x20, + 0x70, 0x6f, 0x72, 0x74, 0x73, 0xa, 0x3c, 0x2f, 0x70, 0x72, + 0x65, 0x3e, 0x3c, 0x2f, 0x74, 0x64, 0x3e, 0x3c, 0x74, 0x64, + 0x3e, 0x3c, 0x70, 0x72, 0x65, 0x3e, 0x25, 0x21, 0x20, 0x6e, + 0x65, 0x74, 0x2d, 0x73, 0x74, 0x61, 0x74, 0x73, 0xa, 0x3c, + 0x2f, 0x70, 0x72, 0x65, 0x3e, 0x3c, 0x2f, 0x74, 0x61, 0x62, + 0x6c, 0x65, 0x3e, 0xa, 0x3c, 0x2f, 0x63, 0x65, 0x6e, 0x74, + 0x65, 0x72, 0x3e, 0xa, 0x25, 0x21, 0x3a, 0x20, 0x2f, 0x66, + 0x6f, 0x6f, 0x74, 0x65, 0x72, 0x2e, 0x68, 0x74, 0x6d, 0x6c, + 0xa, 0}; + +const struct httpd_fsdata_file file_processes_shtml[] = {{NULL, data_processes_shtml, data_processes_shtml + 17, sizeof(data_processes_shtml) - 17}}; + +const struct httpd_fsdata_file file_404_html[] = {{file_processes_shtml, data_404_html, data_404_html + 10, sizeof(data_404_html) - 10}}; + +const struct httpd_fsdata_file file_files_shtml[] = {{file_404_html, data_files_shtml, data_files_shtml + 13, sizeof(data_files_shtml) - 13}}; + +const struct httpd_fsdata_file file_footer_html[] = {{file_files_shtml, data_footer_html, data_footer_html + 13, sizeof(data_footer_html) - 13}}; + +const struct httpd_fsdata_file file_header_html[] = {{file_footer_html, data_header_html, data_header_html + 13, sizeof(data_header_html) - 13}}; + +const struct httpd_fsdata_file file_index_html[] = {{file_header_html, data_index_html, data_index_html + 12, sizeof(data_index_html) - 12}}; + +const struct httpd_fsdata_file file_style_css[] = {{file_index_html, data_style_css, data_style_css + 11, sizeof(data_style_css) - 11}}; + +const struct httpd_fsdata_file file_tcp_shtml[] = {{file_style_css, data_tcp_shtml, data_tcp_shtml + 11, sizeof(data_tcp_shtml) - 11}}; + +const struct httpd_fsdata_file file_fade_png[] = {{file_tcp_shtml, data_fade_png, data_fade_png + 10, sizeof(data_fade_png) - 10}}; + +const struct httpd_fsdata_file file_stats_shtml[] = {{file_fade_png, data_stats_shtml, data_stats_shtml + 13, sizeof(data_stats_shtml) - 13}}; + +#define HTTPD_FS_ROOT file_stats_shtml + +#define HTTPD_FS_NUMFILES 10 diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fsdata.h b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fsdata.h new file mode 100644 index 000000000..52d35c265 --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fsdata.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: httpd-fsdata.h,v 1.1 2006/06/07 09:13:08 adam Exp $ + */ +#ifndef __HTTPD_FSDATA_H__ +#define __HTTPD_FSDATA_H__ + +#include "uip.h" + +struct httpd_fsdata_file { + const struct httpd_fsdata_file *next; + const char *name; + const char *data; + const int len; +#ifdef HTTPD_FS_STATISTICS +#if HTTPD_FS_STATISTICS == 1 + u16_t count; +#endif /* HTTPD_FS_STATISTICS */ +#endif /* HTTPD_FS_STATISTICS */ +}; + +struct httpd_fsdata_file_noconst { + struct httpd_fsdata_file *next; + char *name; + char *data; + int len; +#ifdef HTTPD_FS_STATISTICS +#if HTTPD_FS_STATISTICS == 1 + u16_t count; +#endif /* HTTPD_FS_STATISTICS */ +#endif /* HTTPD_FS_STATISTICS */ +}; + +#endif /* __HTTPD_FSDATA_H__ */ diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd.c b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd.c new file mode 100644 index 000000000..e808688d2 --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd.c @@ -0,0 +1,338 @@ +/** + * \addtogroup apps + * @{ + */ + +/** + * \defgroup httpd Web server + * @{ + * The uIP web server is a very simplistic implementation of an HTTP + * server. It can serve web pages and files from a read-only ROM + * filesystem, and provides a very small scripting language. + + */ + +/** + * \file + * Web server + * \author + * Adam Dunkels + */ + + +/* + * Copyright (c) 2004, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: httpd.c,v 1.2 2006/06/11 21:46:38 adam Exp $ + */ + +#include "uip.h" +#include "httpd.h" +#include "httpd-fs.h" +#include "httpd-cgi.h" +#include "http-strings.h" + +#include + +#define STATE_WAITING 0 +#define STATE_OUTPUT 1 + +#define ISO_nl 0x0a +#define ISO_space 0x20 +#define ISO_bang 0x21 +#define ISO_percent 0x25 +#define ISO_period 0x2e +#define ISO_slash 0x2f +#define ISO_colon 0x3a + + +/*---------------------------------------------------------------------------*/ +static unsigned short +generate_part_of_file(void *state) +{ + struct httpd_state *s = (struct httpd_state *)state; + + if(s->file.len > uip_mss()) { + s->len = uip_mss(); + } else { + s->len = s->file.len; + } + memcpy(uip_appdata, s->file.data, s->len); + + return s->len; +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(send_file(struct httpd_state *s)) +{ + PSOCK_BEGIN(&s->sout); + + do { + PSOCK_GENERATOR_SEND(&s->sout, generate_part_of_file, s); + s->file.len -= s->len; + s->file.data += s->len; + } while(s->file.len > 0); + + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(send_part_of_file(struct httpd_state *s)) +{ + PSOCK_BEGIN(&s->sout); + + PSOCK_SEND(&s->sout, s->file.data, s->len); + + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +static void +next_scriptstate(struct httpd_state *s) +{ + char *p; + p = strchr(s->scriptptr, ISO_nl) + 1; + s->scriptlen -= (unsigned short)(p - s->scriptptr); + s->scriptptr = p; +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(handle_script(struct httpd_state *s)) +{ + char *ptr; + + PT_BEGIN(&s->scriptpt); + + + while(s->file.len > 0) { + + /* Check if we should start executing a script. */ + if(*s->file.data == ISO_percent && + *(s->file.data + 1) == ISO_bang) { + s->scriptptr = s->file.data + 3; + s->scriptlen = s->file.len - 3; + if(*(s->scriptptr - 1) == ISO_colon) { + httpd_fs_open(s->scriptptr + 1, &s->file); + PT_WAIT_THREAD(&s->scriptpt, send_file(s)); + } else { + PT_WAIT_THREAD(&s->scriptpt, + httpd_cgi(s->scriptptr)(s, s->scriptptr)); + } + next_scriptstate(s); + + /* The script is over, so we reset the pointers and continue + sending the rest of the file. */ + s->file.data = s->scriptptr; + s->file.len = s->scriptlen; + } else { + /* See if we find the start of script marker in the block of HTML + to be sent. */ + + if(s->file.len > uip_mss()) { + s->len = uip_mss(); + } else { + s->len = s->file.len; + } + + if(*s->file.data == ISO_percent) { + ptr = strchr(s->file.data + 1, ISO_percent); + } else { + ptr = strchr(s->file.data, ISO_percent); + } + if(ptr != NULL && + ptr != s->file.data) { + s->len = (int)(ptr - s->file.data); + if(s->len >= uip_mss()) { + s->len = uip_mss(); + } + } + PT_WAIT_THREAD(&s->scriptpt, send_part_of_file(s)); + s->file.data += s->len; + s->file.len -= s->len; + + } + } + + PT_END(&s->scriptpt); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(send_headers(struct httpd_state *s, const char *statushdr)) +{ + char *ptr; + + PSOCK_BEGIN(&s->sout); + + PSOCK_SEND_STR(&s->sout, statushdr); + + ptr = strrchr(s->filename, ISO_period); + if(ptr == NULL) { + PSOCK_SEND_STR(&s->sout, http_content_type_binary); + } else if(strncmp(http_html, ptr, 5) == 0 || + strncmp(http_shtml, ptr, 6) == 0) { + PSOCK_SEND_STR(&s->sout, http_content_type_html); + } else if(strncmp(http_css, ptr, 4) == 0) { + PSOCK_SEND_STR(&s->sout, http_content_type_css); + } else if(strncmp(http_png, ptr, 4) == 0) { + PSOCK_SEND_STR(&s->sout, http_content_type_png); + } else if(strncmp(http_gif, ptr, 4) == 0) { + PSOCK_SEND_STR(&s->sout, http_content_type_gif); + } else if(strncmp(http_jpg, ptr, 4) == 0) { + PSOCK_SEND_STR(&s->sout, http_content_type_jpg); + } else { + PSOCK_SEND_STR(&s->sout, http_content_type_plain); + } + PSOCK_END(&s->sout); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(handle_output(struct httpd_state *s)) +{ + char *ptr; + + PT_BEGIN(&s->outputpt); + + if(!httpd_fs_open(s->filename, &s->file)) { + httpd_fs_open(http_404_html, &s->file); + strcpy(s->filename, http_404_html); + PT_WAIT_THREAD(&s->outputpt, + send_headers(s, + http_header_404)); + PT_WAIT_THREAD(&s->outputpt, + send_file(s)); + } else { + PT_WAIT_THREAD(&s->outputpt, + send_headers(s, + http_header_200)); + ptr = strchr(s->filename, ISO_period); + if(ptr != NULL && strncmp(ptr, http_shtml, 6) == 0) { + PT_INIT(&s->scriptpt); + PT_WAIT_THREAD(&s->outputpt, handle_script(s)); + } else { + PT_WAIT_THREAD(&s->outputpt, + send_file(s)); + } + } + PSOCK_CLOSE(&s->sout); + PT_END(&s->outputpt); +} +/*---------------------------------------------------------------------------*/ +static +PT_THREAD(handle_input(struct httpd_state *s)) +{ + PSOCK_BEGIN(&s->sin); + + PSOCK_READTO(&s->sin, ISO_space); + + + if(strncmp(s->inputbuf, http_get, 4) != 0) { + PSOCK_CLOSE_EXIT(&s->sin); + } + PSOCK_READTO(&s->sin, ISO_space); + + if(s->inputbuf[0] != ISO_slash) { + PSOCK_CLOSE_EXIT(&s->sin); + } + + if(s->inputbuf[1] == ISO_space) { + strncpy(s->filename, http_index_html, sizeof(s->filename)); + } else { + s->inputbuf[PSOCK_DATALEN(&s->sin) - 1] = 0; + strncpy(s->filename, &s->inputbuf[0], sizeof(s->filename)); + } + + /* httpd_log_file(uip_conn->ripaddr, s->filename);*/ + + s->state = STATE_OUTPUT; + + while(1) { + PSOCK_READTO(&s->sin, ISO_nl); + + if(strncmp(s->inputbuf, http_referer, 8) == 0) { + s->inputbuf[PSOCK_DATALEN(&s->sin) - 2] = 0; + /* httpd_log(&s->inputbuf[9]);*/ + } + } + + PSOCK_END(&s->sin); +} +/*---------------------------------------------------------------------------*/ +static void +handle_connection(struct httpd_state *s) +{ + handle_input(s); + if(s->state == STATE_OUTPUT) { + handle_output(s); + } +} +/*---------------------------------------------------------------------------*/ +void +httpd_appcall(void) +{ + struct httpd_state *s = (struct httpd_state *)&(uip_conn->appstate); + + if(uip_closed() || uip_aborted() || uip_timedout()) { + } else if(uip_connected()) { + PSOCK_INIT(&s->sin, s->inputbuf, sizeof(s->inputbuf) - 1); + PSOCK_INIT(&s->sout, s->inputbuf, sizeof(s->inputbuf) - 1); + PT_INIT(&s->outputpt); + s->state = STATE_WAITING; + /* timer_set(&s->timer, CLOCK_SECOND * 100);*/ + s->timer = 0; + handle_connection(s); + } else if(s != NULL) { + if(uip_poll()) { + ++s->timer; + if(s->timer >= 20) { + uip_abort(); + } + } else { + s->timer = 0; + } + handle_connection(s); + } else { + uip_abort(); + } +} +/*---------------------------------------------------------------------------*/ +/** + * \brief Initialize the web server + * + * This function initializes the web server and should be + * called at system boot-up. + */ +void +httpd_init(void) +{ + uip_listen(HTONS(80)); +} +/*---------------------------------------------------------------------------*/ +/** @} */ diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd.h b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd.h new file mode 100644 index 000000000..7f7a6666e --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2001-2005, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: httpd.h,v 1.2 2006/06/11 21:46:38 adam Exp $ + * + */ + +#ifndef __HTTPD_H__ +#define __HTTPD_H__ + +#include "psock.h" +#include "httpd-fs.h" + +struct httpd_state { + unsigned char timer; + struct psock sin, sout; + struct pt outputpt, scriptpt; + char inputbuf[50]; + char filename[20]; + char state; + struct httpd_fs_file file; + int len; + char *scriptptr; + int scriptlen; + + unsigned short count; +}; + +void httpd_init(void); +void httpd_appcall(void); + +void httpd_log(char *msg); +void httpd_log_file(u16_t *requester, char *file); + +#endif /* __HTTPD_H__ */ diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/makefsdata b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/makefsdata new file mode 100644 index 000000000..8d2715a8a --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/makefsdata @@ -0,0 +1,78 @@ +#!/usr/bin/perl + +open(OUTPUT, "> httpd-fsdata.c"); + +chdir("httpd-fs"); + +opendir(DIR, "."); +@files = grep { !/^\./ && !/(CVS|~)/ } readdir(DIR); +closedir(DIR); + +foreach $file (@files) { + + if(-d $file && $file !~ /^\./) { + print "Processing directory $file\n"; + opendir(DIR, $file); + @newfiles = grep { !/^\./ && !/(CVS|~)/ } readdir(DIR); + closedir(DIR); + printf "Adding files @newfiles\n"; + @files = (@files, map { $_ = "$file/$_" } @newfiles); + next; + } +} + +foreach $file (@files) { + if(-f $file) { + + print "Adding file $file\n"; + + open(FILE, $file) || die "Could not open file $file\n"; + + $file =~ s-^-/-; + $fvar = $file; + $fvar =~ s-/-_-g; + $fvar =~ s-\.-_-g; + # for AVR, add PROGMEM here + print(OUTPUT "static const unsigned char data".$fvar."[] = {\n"); + print(OUTPUT "\t/* $file */\n\t"); + for($j = 0; $j < length($file); $j++) { + printf(OUTPUT "%#02x, ", unpack("C", substr($file, $j, 1))); + } + printf(OUTPUT "0,\n"); + + + $i = 0; + while(read(FILE, $data, 1)) { + if($i == 0) { + print(OUTPUT "\t"); + } + printf(OUTPUT "%#02x, ", unpack("C", $data)); + $i++; + if($i == 10) { + print(OUTPUT "\n"); + $i = 0; + } + } + print(OUTPUT "0};\n\n"); + close(FILE); + push(@fvars, $fvar); + push(@pfiles, $file); + } +} + +for($i = 0; $i < @fvars; $i++) { + $file = $pfiles[$i]; + $fvar = $fvars[$i]; + + if($i == 0) { + $prevfile = "NULL"; + } else { + $prevfile = "file" . $fvars[$i - 1]; + } + print(OUTPUT "const struct httpd_fsdata_file file".$fvar."[] = {{$prevfile, data$fvar, "); + print(OUTPUT "data$fvar + ". (length($file) + 1) .", "); + print(OUTPUT "sizeof(data$fvar) - ". (length($file) + 1) ."}};\n\n"); +} + +print(OUTPUT "#define HTTPD_FS_ROOT file$fvars[$i - 1]\n\n"); +print(OUTPUT "#define HTTPD_FS_NUMFILES $i\n"); diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/makestrings b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/makestrings new file mode 100644 index 000000000..8a13c6d29 --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/makestrings @@ -0,0 +1,40 @@ +#!/usr/bin/perl + + +sub stringify { + my $name = shift(@_); + open(OUTPUTC, "> $name.c"); + open(OUTPUTH, "> $name.h"); + + open(FILE, "$name"); + + while() { + if(/(.+) "(.+)"/) { + $var = $1; + $data = $2; + + $datan = $data; + $datan =~ s/\\r/\r/g; + $datan =~ s/\\n/\n/g; + $datan =~ s/\\01/\01/g; + $datan =~ s/\\0/\0/g; + + printf(OUTPUTC "const char $var\[%d] = \n", length($datan) + 1); + printf(OUTPUTC "/* \"$data\" */\n"); + printf(OUTPUTC "{"); + for($j = 0; $j < length($datan); $j++) { + printf(OUTPUTC "%#02x, ", unpack("C", substr($datan, $j, 1))); + } + printf(OUTPUTC "};\n"); + + printf(OUTPUTH "extern const char $var\[%d];\n", length($datan) + 1); + + } + } + close(OUTPUTC); + close(OUTPUTH); +} +stringify("http-strings"); + +exit 0; + diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/webserver.h b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/webserver.h new file mode 100644 index 000000000..1acb290b8 --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/webserver.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2002, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: webserver.h,v 1.2 2006/06/11 21:46:38 adam Exp $ + * + */ +#ifndef __WEBSERVER_H__ +#define __WEBSERVER_H__ + +#include "httpd.h" + +typedef struct httpd_state uip_tcp_appstate_t; +/* UIP_APPCALL: the name of the application function. This function + must return void and take no arguments (i.e., C type "void + appfunc(void)"). */ +#ifndef UIP_APPCALL +#define UIP_APPCALL httpd_appcall +#endif + + +#endif /* __WEBSERVER_H__ */ diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip-1.0-changelog.txt b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip-1.0-changelog.txt new file mode 100644 index 000000000..7a97704ea --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip-1.0-changelog.txt @@ -0,0 +1,98 @@ +* A new API: protosockets that are similar to BSD sockets but does not + require any underlying multithreading system. + +* Very rudimentary IPv6 support + +* New application: DHCP client. Web server rewritten with protosockets. + +* Removed uIP zero-copy functionality in order to simplify uIP device + driver coding: outbound packets are now *always* stored in full in + the uip_buf buffer. + +* Checksum computation is now part of uip.c, but it still is possible + to implement them in assembly code by specifying a configuration + option. Checksum code now runs on architectures with 2-byte alignment. + +* Added TCP persistent timer. + +* Made all IP address representations use the new uip_ipaddr_ip + datatype for clarity. + +* Updated window behavior so that sending to a host with a small open + window works better now. + +* UDP API change: uip_udp_new() now takes port numbers in network byte + order like TCP functions. + +* Allow reception of packets when no IP address is configured to make + DHCP work. + +* Moved Ethernet address into main uIP module from ARP module. + +* Made constants explicit #defines and moved them out of the code + (header sizes, TCP options, TCP header length field). + +* If uip_len is less than that reported by the IP header, the packet + is discarded. If uip_len is greater than the length reported by the + IP header, uip_len is adjusted. + +* Moved header size definitions into header file. + +* Added uIP call for polling an application without triggering any + timer events. Removed redundant assignments of uip_len and uip_slen. + +* Removed compiler warning about icmp_input label being defined when + UIP_PINGADDRCONF was not used. + +* Added UIP_APPDATA_SIZE macro that holds the available buffer size + for user data. + +* Added uip_udp_bind() call. + +* Moved checksum code into main uIP module. + +* Switched the TCP, UDP and IP header structures to be structs rather + than typedefs. + +* Prefixed TCP state names with UIP_ to avoid name space + contamination. + +* Changed declarations of uip_appdatap and friends to void * to avoid + explicit typecasts. + +* Bugfixes + + o TCP: Fixed bug with high byte of peer window size. + + o TCP: Fixed bug that in some cases prevented concurrent reception and + transmission of TCP data. + + o TCP: uip_connect() didn't correctly calculate age of TIME_WAIT + connections. + + o TCP: Array index for uip_conns[] array was out of bounds in + comparison. Comparison changed to make index within bounds. + + o TCP: if the remote host crashes and tries to reestablish an old + connection, uIP should respond with an ACK with the correct + sequence and acknowledgment numbers, to which the remote host + should respond with an ACK. uIP did not respond with the correct + ACK. + + o TCP: Fixed check for SYNACK segment: now checks only relevant TCP + control flags and discards flags reserved for future expansion. + + o TCP: Fixed bug where uIP did not inform application that a connection + had been aborted during an active open. + + o TCP: FIN segment was accepted even though application had stopped + incoming data with uip_stop(). + + o TCP: A FINACK segment would not always correctly acknowledge data. + + o UDP: checksums are now calculated after all fields have been + filled in. + + o UDP: network byte order on lastport in uip_udp_new(). + + o IP: memset() bugs in IP fragment reassembly code fixed. diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/Makefile.include b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/Makefile.include new file mode 100644 index 000000000..43ba24744 --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/Makefile.include @@ -0,0 +1,47 @@ + + +ifdef APPS + APPDIRS = $(foreach APP, $(APPS), ../apps/$(APP)) + -include $(foreach APP, $(APPS), ../apps/$(APP)/Makefile.$(APP)) + CFLAGS += $(addprefix -I../apps/,$(APPS)) +endif + +ifndef CCDEP + CCDEP = $(CC) +endif +ifndef CCDEPCFLAGS + CCDEPCFLAGS = $(CFLAGS) +endif +ifndef OBJECTDIR + OBJECTDIR = obj +endif + +ifeq (${wildcard $(OBJECTDIR)},) + DUMMY := ${shell mkdir $(OBJECTDIR)} +endif + + +vpath %.c . ../uip ../lib $(APPDIRS) + +$(OBJECTDIR)/%.o: %.c + $(CC) $(CFLAGS) -c $< -o $@ + +$(OBJECTDIR)/%.d: %.c + @set -e; rm -f $@; \ + $(CCDEP) -MM $(CCDEPCFLAGS) $< > $@.$$$$; \ + sed 's,\($*\)\.o[ :]*,$(OBJECTDIR)/\1.o $@ : ,g' < $@.$$$$ > $@; \ + rm -f $@.$$$$ + +UIP_SOURCES=uip.c uip_arp.c uiplib.c psock.c timer.c uip-neighbor.c + + +ifneq ($(MAKECMDGOALS),clean) +-include $(addprefix $(OBJECTDIR)/,$(UIP_SOURCES:.c=.d) \ + $(APP_SOURCES:.c=.d)) +endif + +uip.a: ${addprefix $(OBJECTDIR)/, $(UIP_SOURCES:.c=.o)} + $(AR) rcf $@ $^ + +apps.a: ${addprefix $(OBJECTDIR)/, $(APP_SOURCES:.c=.o)} + $(AR) rcf $@ $^ diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/clock.h b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/clock.h new file mode 100644 index 000000000..dae68745f --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/clock.h @@ -0,0 +1,88 @@ +/** + * \defgroup clock Clock interface + * + * The clock interface is the interface between the \ref timer "timer library" + * and the platform specific clock functionality. The clock + * interface must be implemented for each platform that uses the \ref + * timer "timer library". + * + * The clock interface does only one this: it measures time. The clock + * interface provides a macro, CLOCK_SECOND, which corresponds to one + * second of system time. + * + * \sa \ref timer "Timer library" + * + * @{ + */ + +/* + * Copyright (c) 2004, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * Author: Adam Dunkels + * + * $Id: clock.h,v 1.3 2006/06/11 21:46:39 adam Exp $ + */ +#ifndef __CLOCK_H__ +#define __CLOCK_H__ + +#include "clock-arch.h" + +/** + * Initialize the clock library. + * + * This function initializes the clock library and should be called + * from the main() function of the system. + * + */ +void clock_init(void); + +/** + * Get the current clock time. + * + * This function returns the current system clock time. + * + * \return The current clock time, measured in system ticks. + */ +clock_time_t clock_time(void); + +/** + * A second, measured in system clock time. + * + * \hideinitializer + */ +#ifdef CLOCK_CONF_SECOND +#define CLOCK_SECOND CLOCK_CONF_SECOND +#else +#define CLOCK_SECOND (clock_time_t)32 +#endif + +#endif /* __CLOCK_H__ */ + +/** @} */ diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/lc-addrlabels.h b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/lc-addrlabels.h new file mode 100644 index 000000000..9dff03d09 --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/lc-addrlabels.h @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2004-2005, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * Author: Adam Dunkels + * + * $Id: lc-addrlabels.h,v 1.3 2006/06/12 08:00:30 adam Exp $ + */ + +/** + * \addtogroup lc + * @{ + */ + +/** + * \file + * Implementation of local continuations based on the "Labels as + * values" feature of gcc + * \author + * Adam Dunkels + * + * This implementation of local continuations is based on a special + * feature of the GCC C compiler called "labels as values". This + * feature allows assigning pointers with the address of the code + * corresponding to a particular C label. + * + * For more information, see the GCC documentation: + * http://gcc.gnu.org/onlinedocs/gcc/Labels-as-Values.html + * + * Thanks to dividuum for finding the nice local scope label + * implementation. + */ + +#ifndef __LC_ADDRLABELS_H__ +#define __LC_ADDRLABELS_H__ + +/** \hideinitializer */ +typedef void * lc_t; + +#define LC_INIT(s) s = NULL + + +#define LC_RESUME(s) \ + do { \ + if(s != NULL) { \ + goto *s; \ + } \ + } while(0) + +#define LC_SET(s) \ + do { ({ __label__ resume; resume: (s) = &&resume; }); }while(0) + +#define LC_END(s) + +#endif /* __LC_ADDRLABELS_H__ */ + +/** @} */ diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/lc-switch.h b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/lc-switch.h new file mode 100644 index 000000000..17c881161 --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/lc-switch.h @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2004-2005, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * Author: Adam Dunkels + * + * $Id: lc-switch.h,v 1.2 2006/06/12 08:00:30 adam Exp $ + */ + +/** + * \addtogroup lc + * @{ + */ + +/** + * \file + * Implementation of local continuations based on switch() statment + * \author Adam Dunkels + * + * This implementation of local continuations uses the C switch() + * statement to resume execution of a function somewhere inside the + * function's body. The implementation is based on the fact that + * switch() statements are able to jump directly into the bodies of + * control structures such as if() or while() statmenets. + * + * This implementation borrows heavily from Simon Tatham's coroutines + * implementation in C: + * http://www.chiark.greenend.org.uk/~sgtatham/coroutines.html + */ + +#ifndef __LC_SWITCH_H__ +#define __LC_SWTICH_H__ + +/* WARNING! lc implementation using switch() does not work if an + LC_SET() is done within another switch() statement! */ + +/** \hideinitializer */ +typedef unsigned short lc_t; + +#define LC_INIT(s) s = 0; + +#define LC_RESUME(s) switch(s) { case 0: + +#define LC_SET(s) s = __LINE__; case __LINE__: + +#define LC_END(s) } + +#endif /* __LC_SWITCH_H__ */ + +/** @} */ diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/lc.h b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/lc.h new file mode 100644 index 000000000..3ad83cd0a --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/lc.h @@ -0,0 +1,131 @@ +/* + * Copyright (c) 2004-2005, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * Author: Adam Dunkels + * + * $Id: lc.h,v 1.2 2006/06/12 08:00:30 adam Exp $ + */ + +/** + * \addtogroup pt + * @{ + */ + +/** + * \defgroup lc Local continuations + * @{ + * + * Local continuations form the basis for implementing protothreads. A + * local continuation can be set in a specific function to + * capture the state of the function. After a local continuation has + * been set can be resumed in order to restore the state of the + * function at the point where the local continuation was set. + * + * + */ + +/** + * \file lc.h + * Local continuations + * \author + * Adam Dunkels + * + */ + +#ifdef DOXYGEN +/** + * Initialize a local continuation. + * + * This operation initializes the local continuation, thereby + * unsetting any previously set continuation state. + * + * \hideinitializer + */ +#define LC_INIT(lc) + +/** + * Set a local continuation. + * + * The set operation saves the state of the function at the point + * where the operation is executed. As far as the set operation is + * concerned, the state of the function does not include the + * call-stack or local (automatic) variables, but only the program + * counter and such CPU registers that needs to be saved. + * + * \hideinitializer + */ +#define LC_SET(lc) + +/** + * Resume a local continuation. + * + * The resume operation resumes a previously set local continuation, thus + * restoring the state in which the function was when the local + * continuation was set. If the local continuation has not been + * previously set, the resume operation does nothing. + * + * \hideinitializer + */ +#define LC_RESUME(lc) + +/** + * Mark the end of local continuation usage. + * + * The end operation signifies that local continuations should not be + * used any more in the function. This operation is not needed for + * most implementations of local continuation, but is required by a + * few implementations. + * + * \hideinitializer + */ +#define LC_END(lc) + +/** + * \var typedef lc_t; + * + * The local continuation type. + * + * \hideinitializer + */ +#endif /* DOXYGEN */ + +#ifndef __LC_H__ +#define __LC_H__ + +#ifdef LC_CONF_INCLUDE +#include LC_CONF_INCLUDE +#else +#include "lc-switch.h" +#endif /* LC_CONF_INCLUDE */ + +#endif /* __LC_H__ */ + +/** @} */ +/** @} */ diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/psock.c b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/psock.c new file mode 100644 index 000000000..6b5920f78 --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/psock.c @@ -0,0 +1,338 @@ +/* + * Copyright (c) 2004, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * Author: Adam Dunkels + * + * $Id: psock.c,v 1.2 2006/06/12 08:00:30 adam Exp $ + */ + +#include +#include + +#include "uipopt.h" +#include "psock.h" +#include "uip.h" + +#define STATE_NONE 0 +#define STATE_ACKED 1 +#define STATE_READ 2 +#define STATE_BLOCKED_NEWDATA 3 +#define STATE_BLOCKED_CLOSE 4 +#define STATE_BLOCKED_SEND 5 +#define STATE_DATA_SENT 6 + +/* + * Return value of the buffering functions that indicates that a + * buffer was not filled by incoming data. + * + */ +#define BUF_NOT_FULL 0 +#define BUF_NOT_FOUND 0 + +/* + * Return value of the buffering functions that indicates that a + * buffer was completely filled by incoming data. + * + */ +#define BUF_FULL 1 + +/* + * Return value of the buffering functions that indicates that an + * end-marker byte was found. + * + */ +#define BUF_FOUND 2 + +/*---------------------------------------------------------------------------*/ +static void +buf_setup(struct psock_buf *buf, + u8_t *bufptr, u16_t bufsize) +{ + buf->ptr = bufptr; + buf->left = bufsize; +} +/*---------------------------------------------------------------------------*/ +static u8_t +buf_bufdata(struct psock_buf *buf, u16_t len, + u8_t **dataptr, u16_t *datalen) +{ + if(*datalen < buf->left) { + memcpy(buf->ptr, *dataptr, *datalen); + buf->ptr += *datalen; + buf->left -= *datalen; + *dataptr += *datalen; + *datalen = 0; + return BUF_NOT_FULL; + } else if(*datalen == buf->left) { + memcpy(buf->ptr, *dataptr, *datalen); + buf->ptr += *datalen; + buf->left = 0; + *dataptr += *datalen; + *datalen = 0; + return BUF_FULL; + } else { + memcpy(buf->ptr, *dataptr, buf->left); + buf->ptr += buf->left; + *datalen -= buf->left; + *dataptr += buf->left; + buf->left = 0; + return BUF_FULL; + } +} +/*---------------------------------------------------------------------------*/ +static u8_t +buf_bufto(register struct psock_buf *buf, u8_t endmarker, + register u8_t **dataptr, register u16_t *datalen) +{ + u8_t c; + while(buf->left > 0 && *datalen > 0) { + c = *buf->ptr = **dataptr; + ++*dataptr; + ++buf->ptr; + --*datalen; + --buf->left; + + if(c == endmarker) { + return BUF_FOUND; + } + } + + if(*datalen == 0) { + return BUF_NOT_FOUND; + } + + while(*datalen > 0) { + c = **dataptr; + --*datalen; + ++*dataptr; + + if(c == endmarker) { + return BUF_FOUND | BUF_FULL; + } + } + + return BUF_FULL; +} +/*---------------------------------------------------------------------------*/ +static char +send_data(register struct psock *s) +{ + if(s->state != STATE_DATA_SENT || uip_rexmit()) { + if(s->sendlen > uip_mss()) { + uip_send(s->sendptr, uip_mss()); + } else { + uip_send(s->sendptr, s->sendlen); + } + s->state = STATE_DATA_SENT; + return 1; + } + return 0; +} +/*---------------------------------------------------------------------------*/ +static char +data_acked(register struct psock *s) +{ + if(s->state == STATE_DATA_SENT && uip_acked()) { + if(s->sendlen > uip_mss()) { + s->sendlen -= uip_mss(); + s->sendptr += uip_mss(); + } else { + s->sendptr += s->sendlen; + s->sendlen = 0; + } + s->state = STATE_ACKED; + return 1; + } + return 0; +} +/*---------------------------------------------------------------------------*/ +PT_THREAD(psock_send(register struct psock *s, const char *buf, + unsigned int len)) +{ + PT_BEGIN(&s->psockpt); + + /* If there is no data to send, we exit immediately. */ + if(len == 0) { + PT_EXIT(&s->psockpt); + } + + /* Save the length of and a pointer to the data that is to be + sent. */ + s->sendptr = buf; + s->sendlen = len; + + s->state = STATE_NONE; + + /* We loop here until all data is sent. The s->sendlen variable is + updated by the data_sent() function. */ + while(s->sendlen > 0) { + + /* + * The condition for this PT_WAIT_UNTIL is a little tricky: the + * protothread will wait here until all data has been acknowledged + * (data_acked() returns true) and until all data has been sent + * (send_data() returns true). The two functions data_acked() and + * send_data() must be called in succession to ensure that all + * data is sent. Therefore the & operator is used instead of the + * && operator, which would cause only the data_acked() function + * to be called when it returns false. + */ + PT_WAIT_UNTIL(&s->psockpt, data_acked(s) & send_data(s)); + } + + s->state = STATE_NONE; + + PT_END(&s->psockpt); +} +/*---------------------------------------------------------------------------*/ +PT_THREAD(psock_generator_send(register struct psock *s, + unsigned short (*generate)(void *), void *arg)) +{ + PT_BEGIN(&s->psockpt); + + /* Ensure that there is a generator function to call. */ + if(generate == NULL) { + PT_EXIT(&s->psockpt); + } + + /* Call the generator function to generate the data in the + uip_appdata buffer. */ + s->sendlen = generate(arg); + s->sendptr = uip_appdata; + + s->state = STATE_NONE; + do { + /* Call the generator function again if we are called to perform a + retransmission. */ + if(uip_rexmit()) { + generate(arg); + } + /* Wait until all data is sent and acknowledged. */ + PT_WAIT_UNTIL(&s->psockpt, data_acked(s) & send_data(s)); + } while(s->sendlen > 0); + + s->state = STATE_NONE; + + PT_END(&s->psockpt); +} +/*---------------------------------------------------------------------------*/ +u16_t +psock_datalen(struct psock *psock) +{ + return psock->bufsize - psock->buf.left; +} +/*---------------------------------------------------------------------------*/ +char +psock_newdata(struct psock *s) +{ + if(s->readlen > 0) { + /* There is data in the uip_appdata buffer that has not yet been + read with the PSOCK_READ functions. */ + return 1; + } else if(s->state == STATE_READ) { + /* All data in uip_appdata buffer already consumed. */ + s->state = STATE_BLOCKED_NEWDATA; + return 0; + } else if(uip_newdata()) { + /* There is new data that has not been consumed. */ + return 1; + } else { + /* There is no new data. */ + return 0; + } +} +/*---------------------------------------------------------------------------*/ +PT_THREAD(psock_readto(register struct psock *psock, unsigned char c)) +{ + PT_BEGIN(&psock->psockpt); + + buf_setup(&psock->buf, psock->bufptr, psock->bufsize); + + /* XXX: Should add buf_checkmarker() before do{} loop, if + incoming data has been handled while waiting for a write. */ + + do { + if(psock->readlen == 0) { + PT_WAIT_UNTIL(&psock->psockpt, psock_newdata(psock)); + psock->state = STATE_READ; + psock->readptr = (u8_t *)uip_appdata; + psock->readlen = uip_datalen(); + } + } while((buf_bufto(&psock->buf, c, + &psock->readptr, + &psock->readlen) & BUF_FOUND) == 0); + + if(psock_datalen(psock) == 0) { + psock->state = STATE_NONE; + PT_RESTART(&psock->psockpt); + } + PT_END(&psock->psockpt); +} +/*---------------------------------------------------------------------------*/ +PT_THREAD(psock_readbuf(register struct psock *psock)) +{ + PT_BEGIN(&psock->psockpt); + + buf_setup(&psock->buf, psock->bufptr, psock->bufsize); + + /* XXX: Should add buf_checkmarker() before do{} loop, if + incoming data has been handled while waiting for a write. */ + + do { + if(psock->readlen == 0) { + PT_WAIT_UNTIL(&psock->psockpt, psock_newdata(psock)); + printf("Waited for newdata\n"); + psock->state = STATE_READ; + psock->readptr = (u8_t *)uip_appdata; + psock->readlen = uip_datalen(); + } + } while(buf_bufdata(&psock->buf, psock->bufsize, + &psock->readptr, + &psock->readlen) != BUF_FULL); + + if(psock_datalen(psock) == 0) { + psock->state = STATE_NONE; + PT_RESTART(&psock->psockpt); + } + PT_END(&psock->psockpt); +} +/*---------------------------------------------------------------------------*/ +void +psock_init(register struct psock *psock, char *buffer, unsigned int buffersize) +{ + psock->state = STATE_NONE; + psock->readlen = 0; + psock->bufptr = buffer; + psock->bufsize = buffersize; + buf_setup(&psock->buf, buffer, buffersize); + PT_INIT(&psock->pt); + PT_INIT(&psock->psockpt); +} +/*---------------------------------------------------------------------------*/ diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/psock.h b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/psock.h new file mode 100644 index 000000000..8d4125878 --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/psock.h @@ -0,0 +1,380 @@ +/* + * Copyright (c) 2004, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * Author: Adam Dunkels + * + * $Id: psock.h,v 1.3 2006/06/12 08:00:30 adam Exp $ + */ + +/** + * \defgroup psock Protosockets library + * @{ + * + * The protosocket library provides an interface to the uIP stack that is + * similar to the traditional BSD socket interface. Unlike programs + * written for the ordinary uIP event-driven interface, programs + * written with the protosocket library are executed in a sequential + * fashion and does not have to be implemented as explicit state + * machines. + * + * Protosockets only work with TCP connections. + * + * The protosocket library uses \ref pt protothreads to provide + * sequential control flow. This makes the protosockets lightweight in + * terms of memory, but also means that protosockets inherits the + * functional limitations of protothreads. Each protosocket lives only + * within a single function. Automatic variables (stack variables) are + * not retained across a protosocket library function call. + * + * \note Because the protosocket library uses protothreads, local + * variables will not always be saved across a call to a protosocket + * library function. It is therefore advised that local variables are + * used with extreme care. + * + * The protosocket library provides functions for sending data without + * having to deal with retransmissions and acknowledgements, as well + * as functions for reading data without having to deal with data + * being split across more than one TCP segment. + * + * Because each protosocket runs as a protothread, the protosocket has to be + * started with a call to PSOCK_BEGIN() at the start of the function + * in which the protosocket is used. Similarly, the protosocket protothread can + * be terminated by a call to PSOCK_EXIT(). + * + */ + +/** + * \file + * Protosocket library header file + * \author + * Adam Dunkels + * + */ + +#ifndef __PSOCK_H__ +#define __PSOCK_H__ + +#include "uipopt.h" +#include "pt.h" + + /* + * The structure that holds the state of a buffer. + * + * This structure holds the state of a uIP buffer. The structure has + * no user-visible elements, but is used through the functions + * provided by the library. + * + */ +struct psock_buf { + u8_t *ptr; + unsigned short left; +}; + +/** + * The representation of a protosocket. + * + * The protosocket structrure is an opaque structure with no user-visible + * elements. + */ +struct psock { + struct pt pt, psockpt; /* Protothreads - one that's using the psock + functions, and one that runs inside the + psock functions. */ + const u8_t *sendptr; /* Pointer to the next data to be sent. */ + u8_t *readptr; /* Pointer to the next data to be read. */ + + char *bufptr; /* Pointer to the buffer used for buffering + incoming data. */ + + u16_t sendlen; /* The number of bytes left to be sent. */ + u16_t readlen; /* The number of bytes left to be read. */ + + struct psock_buf buf; /* The structure holding the state of the + input buffer. */ + unsigned int bufsize; /* The size of the input buffer. */ + + unsigned char state; /* The state of the protosocket. */ +}; + +void psock_init(struct psock *psock, char *buffer, unsigned int buffersize); +/** + * Initialize a protosocket. + * + * This macro initializes a protosocket and must be called before the + * protosocket is used. The initialization also specifies the input buffer + * for the protosocket. + * + * \param psock (struct psock *) A pointer to the protosocket to be + * initialized + * + * \param buffer (char *) A pointer to the input buffer for the + * protosocket. + * + * \param buffersize (unsigned int) The size of the input buffer. + * + * \hideinitializer + */ +#define PSOCK_INIT(psock, buffer, buffersize) \ + psock_init(psock, buffer, buffersize) + +/** + * Start the protosocket protothread in a function. + * + * This macro starts the protothread associated with the protosocket and + * must come before other protosocket calls in the function it is used. + * + * \param psock (struct psock *) A pointer to the protosocket to be + * started. + * + * \hideinitializer + */ +#define PSOCK_BEGIN(psock) PT_BEGIN(&((psock)->pt)) + +PT_THREAD(psock_send(struct psock *psock, const char *buf, unsigned int len)); +/** + * Send data. + * + * This macro sends data over a protosocket. The protosocket protothread blocks + * until all data has been sent and is known to have been received by + * the remote end of the TCP connection. + * + * \param psock (struct psock *) A pointer to the protosocket over which + * data is to be sent. + * + * \param data (char *) A pointer to the data that is to be sent. + * + * \param datalen (unsigned int) The length of the data that is to be + * sent. + * + * \hideinitializer + */ +#define PSOCK_SEND(psock, data, datalen) \ + PT_WAIT_THREAD(&((psock)->pt), psock_send(psock, data, datalen)) + +/** + * \brief Send a null-terminated string. + * \param psock Pointer to the protosocket. + * \param str The string to be sent. + * + * This function sends a null-terminated string over the + * protosocket. + * + * \hideinitializer + */ +#define PSOCK_SEND_STR(psock, str) \ + PT_WAIT_THREAD(&((psock)->pt), psock_send(psock, str, strlen(str))) + +PT_THREAD(psock_generator_send(struct psock *psock, + unsigned short (*f)(void *), void *arg)); + +/** + * \brief Generate data with a function and send it + * \param psock Pointer to the protosocket. + * \param generator Pointer to the generator function + * \param arg Argument to the generator function + * + * This function generates data and sends it over the + * protosocket. This can be used to dynamically generate + * data for a transmission, instead of generating the data + * in a buffer beforehand. This function reduces the need for + * buffer memory. The generator function is implemented by + * the application, and a pointer to the function is given + * as an argument with the call to PSOCK_GENERATOR_SEND(). + * + * The generator function should place the generated data + * directly in the uip_appdata buffer, and return the + * length of the generated data. The generator function is + * called by the protosocket layer when the data first is + * sent, and once for every retransmission that is needed. + * + * \hideinitializer + */ +#define PSOCK_GENERATOR_SEND(psock, generator, arg) \ + PT_WAIT_THREAD(&((psock)->pt), \ + psock_generator_send(psock, generator, arg)) + + +/** + * Close a protosocket. + * + * This macro closes a protosocket and can only be called from within the + * protothread in which the protosocket lives. + * + * \param psock (struct psock *) A pointer to the protosocket that is to + * be closed. + * + * \hideinitializer + */ +#define PSOCK_CLOSE(psock) uip_close() + +PT_THREAD(psock_readbuf(struct psock *psock)); +/** + * Read data until the buffer is full. + * + * This macro will block waiting for data and read the data into the + * input buffer specified with the call to PSOCK_INIT(). Data is read + * until the buffer is full.. + * + * \param psock (struct psock *) A pointer to the protosocket from which + * data should be read. + * + * \hideinitializer + */ +#define PSOCK_READBUF(psock) \ + PT_WAIT_THREAD(&((psock)->pt), psock_readbuf(psock)) + +PT_THREAD(psock_readto(struct psock *psock, unsigned char c)); +/** + * Read data up to a specified character. + * + * This macro will block waiting for data and read the data into the + * input buffer specified with the call to PSOCK_INIT(). Data is only + * read until the specifieed character appears in the data stream. + * + * \param psock (struct psock *) A pointer to the protosocket from which + * data should be read. + * + * \param c (char) The character at which to stop reading. + * + * \hideinitializer + */ +#define PSOCK_READTO(psock, c) \ + PT_WAIT_THREAD(&((psock)->pt), psock_readto(psock, c)) + +/** + * The length of the data that was previously read. + * + * This macro returns the length of the data that was previously read + * using PSOCK_READTO() or PSOCK_READ(). + * + * \param psock (struct psock *) A pointer to the protosocket holding the data. + * + * \hideinitializer + */ +#define PSOCK_DATALEN(psock) psock_datalen(psock) + +u16_t psock_datalen(struct psock *psock); + +/** + * Exit the protosocket's protothread. + * + * This macro terminates the protothread of the protosocket and should + * almost always be used in conjunction with PSOCK_CLOSE(). + * + * \sa PSOCK_CLOSE_EXIT() + * + * \param psock (struct psock *) A pointer to the protosocket. + * + * \hideinitializer + */ +#define PSOCK_EXIT(psock) PT_EXIT(&((psock)->pt)) + +/** + * Close a protosocket and exit the protosocket's protothread. + * + * This macro closes a protosocket and exits the protosocket's protothread. + * + * \param psock (struct psock *) A pointer to the protosocket. + * + * \hideinitializer + */ +#define PSOCK_CLOSE_EXIT(psock) \ + do { \ + PSOCK_CLOSE(psock); \ + PSOCK_EXIT(psock); \ + } while(0) + +/** + * Declare the end of a protosocket's protothread. + * + * This macro is used for declaring that the protosocket's protothread + * ends. It must always be used together with a matching PSOCK_BEGIN() + * macro. + * + * \param psock (struct psock *) A pointer to the protosocket. + * + * \hideinitializer + */ +#define PSOCK_END(psock) PT_END(&((psock)->pt)) + +char psock_newdata(struct psock *s); + +/** + * Check if new data has arrived on a protosocket. + * + * This macro is used in conjunction with the PSOCK_WAIT_UNTIL() + * macro to check if data has arrived on a protosocket. + * + * \param psock (struct psock *) A pointer to the protosocket. + * + * \hideinitializer + */ +#define PSOCK_NEWDATA(psock) psock_newdata(psock) + +/** + * Wait until a condition is true. + * + * This macro blocks the protothread until the specified condition is + * true. The macro PSOCK_NEWDATA() can be used to check if new data + * arrives when the protosocket is waiting. + * + * Typically, this macro is used as follows: + * + \code + PT_THREAD(thread(struct psock *s, struct timer *t)) + { + PSOCK_BEGIN(s); + + PSOCK_WAIT_UNTIL(s, PSOCK_NEWADATA(s) || timer_expired(t)); + + if(PSOCK_NEWDATA(s)) { + PSOCK_READTO(s, '\n'); + } else { + handle_timed_out(s); + } + + PSOCK_END(s); + } + \endcode + * + * \param psock (struct psock *) A pointer to the protosocket. + * \param condition The condition to wait for. + * + * \hideinitializer + */ +#define PSOCK_WAIT_UNTIL(psock, condition) \ + PT_WAIT_UNTIL(&((psock)->pt), (condition)); + +#define PSOCK_WAIT_THREAD(psock, condition) \ + PT_WAIT_THREAD(&((psock)->pt), (condition)) + +#endif /* __PSOCK_H__ */ + +/** @} */ diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/pt.h b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/pt.h new file mode 100644 index 000000000..00ddd4429 --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/pt.h @@ -0,0 +1,323 @@ +/* + * Copyright (c) 2004-2005, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * Author: Adam Dunkels + * + * $Id: pt.h,v 1.2 2006/06/12 08:00:30 adam Exp $ + */ + +/** + * \addtogroup pt + * @{ + */ + +/** + * \file + * Protothreads implementation. + * \author + * Adam Dunkels + * + */ + +#ifndef __PT_H__ +#define __PT_H__ + +#include "lc.h" + +struct pt { + lc_t lc; +}; + +#define PT_WAITING 0 +#define PT_EXITED 1 +#define PT_ENDED 2 +#define PT_YIELDED 3 + +/** + * \name Initialization + * @{ + */ + +/** + * Initialize a protothread. + * + * Initializes a protothread. Initialization must be done prior to + * starting to execute the protothread. + * + * \param pt A pointer to the protothread control structure. + * + * \sa PT_SPAWN() + * + * \hideinitializer + */ +#define PT_INIT(pt) LC_INIT((pt)->lc) + +/** @} */ + +/** + * \name Declaration and definition + * @{ + */ + +/** + * Declaration of a protothread. + * + * This macro is used to declare a protothread. All protothreads must + * be declared with this macro. + * + * \param name_args The name and arguments of the C function + * implementing the protothread. + * + * \hideinitializer + */ +#define PT_THREAD(name_args) char name_args + +/** + * Declare the start of a protothread inside the C function + * implementing the protothread. + * + * This macro is used to declare the starting point of a + * protothread. It should be placed at the start of the function in + * which the protothread runs. All C statements above the PT_BEGIN() + * invokation will be executed each time the protothread is scheduled. + * + * \param pt A pointer to the protothread control structure. + * + * \hideinitializer + */ +#define PT_BEGIN(pt) { char PT_YIELD_FLAG = 1; LC_RESUME((pt)->lc) + +/** + * Declare the end of a protothread. + * + * This macro is used for declaring that a protothread ends. It must + * always be used together with a matching PT_BEGIN() macro. + * + * \param pt A pointer to the protothread control structure. + * + * \hideinitializer + */ +#define PT_END(pt) LC_END((pt)->lc); PT_YIELD_FLAG = 0; \ + PT_INIT(pt); return PT_ENDED; } + +/** @} */ + +/** + * \name Blocked wait + * @{ + */ + +/** + * Block and wait until condition is true. + * + * This macro blocks the protothread until the specified condition is + * true. + * + * \param pt A pointer to the protothread control structure. + * \param condition The condition. + * + * \hideinitializer + */ +#define PT_WAIT_UNTIL(pt, condition) \ + do { \ + LC_SET((pt)->lc); \ + if(!(condition)) { \ + return PT_WAITING; \ + } \ + } while(0) + +/** + * Block and wait while condition is true. + * + * This function blocks and waits while condition is true. See + * PT_WAIT_UNTIL(). + * + * \param pt A pointer to the protothread control structure. + * \param cond The condition. + * + * \hideinitializer + */ +#define PT_WAIT_WHILE(pt, cond) PT_WAIT_UNTIL((pt), !(cond)) + +/** @} */ + +/** + * \name Hierarchical protothreads + * @{ + */ + +/** + * Block and wait until a child protothread completes. + * + * This macro schedules a child protothread. The current protothread + * will block until the child protothread completes. + * + * \note The child protothread must be manually initialized with the + * PT_INIT() function before this function is used. + * + * \param pt A pointer to the protothread control structure. + * \param thread The child protothread with arguments + * + * \sa PT_SPAWN() + * + * \hideinitializer + */ +#define PT_WAIT_THREAD(pt, thread) PT_WAIT_WHILE((pt), PT_SCHEDULE(thread)) + +/** + * Spawn a child protothread and wait until it exits. + * + * This macro spawns a child protothread and waits until it exits. The + * macro can only be used within a protothread. + * + * \param pt A pointer to the protothread control structure. + * \param child A pointer to the child protothread's control structure. + * \param thread The child protothread with arguments + * + * \hideinitializer + */ +#define PT_SPAWN(pt, child, thread) \ + do { \ + PT_INIT((child)); \ + PT_WAIT_THREAD((pt), (thread)); \ + } while(0) + +/** @} */ + +/** + * \name Exiting and restarting + * @{ + */ + +/** + * Restart the protothread. + * + * This macro will block and cause the running protothread to restart + * its execution at the place of the PT_BEGIN() call. + * + * \param pt A pointer to the protothread control structure. + * + * \hideinitializer + */ +#define PT_RESTART(pt) \ + do { \ + PT_INIT(pt); \ + return PT_WAITING; \ + } while(0) + +/** + * Exit the protothread. + * + * This macro causes the protothread to exit. If the protothread was + * spawned by another protothread, the parent protothread will become + * unblocked and can continue to run. + * + * \param pt A pointer to the protothread control structure. + * + * \hideinitializer + */ +#define PT_EXIT(pt) \ + do { \ + PT_INIT(pt); \ + return PT_EXITED; \ + } while(0) + +/** @} */ + +/** + * \name Calling a protothread + * @{ + */ + +/** + * Schedule a protothread. + * + * This function shedules a protothread. The return value of the + * function is non-zero if the protothread is running or zero if the + * protothread has exited. + * + * \param f The call to the C function implementing the protothread to + * be scheduled + * + * \hideinitializer + */ +#define PT_SCHEDULE(f) ((f) == PT_WAITING) + +/** @} */ + +/** + * \name Yielding from a protothread + * @{ + */ + +/** + * Yield from the current protothread. + * + * This function will yield the protothread, thereby allowing other + * processing to take place in the system. + * + * \param pt A pointer to the protothread control structure. + * + * \hideinitializer + */ +#define PT_YIELD(pt) \ + do { \ + PT_YIELD_FLAG = 0; \ + LC_SET((pt)->lc); \ + if(PT_YIELD_FLAG == 0) { \ + return PT_YIELDED; \ + } \ + } while(0) + +/** + * \brief Yield from the protothread until a condition occurs. + * \param pt A pointer to the protothread control structure. + * \param cond The condition. + * + * This function will yield the protothread, until the + * specified condition evaluates to true. + * + * + * \hideinitializer + */ +#define PT_YIELD_UNTIL(pt, cond) \ + do { \ + PT_YIELD_FLAG = 0; \ + LC_SET((pt)->lc); \ + if((PT_YIELD_FLAG == 0) || !(cond)) { \ + return PT_YIELDED; \ + } \ + } while(0) + +/** @} */ + +#endif /* __PT_H__ */ + +/** @} */ diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/timer.c b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/timer.c new file mode 100644 index 000000000..8c270b233 --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/timer.c @@ -0,0 +1,127 @@ +/** + * \addtogroup timer + * @{ + */ + +/** + * \file + * Timer library implementation. + * \author + * Adam Dunkels + */ + +/* + * Copyright (c) 2004, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * Author: Adam Dunkels + * + * $Id: timer.c,v 1.2 2006/06/12 08:00:30 adam Exp $ + */ + +#include "clock.h" +#include "timer.h" + +/*---------------------------------------------------------------------------*/ +/** + * Set a timer. + * + * This function is used to set a timer for a time sometime in the + * future. The function timer_expired() will evaluate to true after + * the timer has expired. + * + * \param t A pointer to the timer + * \param interval The interval before the timer expires. + * + */ +void +timer_set(struct timer *t, clock_time_t interval) +{ + t->interval = interval; + t->start = clock_time(); +} +/*---------------------------------------------------------------------------*/ +/** + * Reset the timer with the same interval. + * + * This function resets the timer with the same interval that was + * given to the timer_set() function. The start point of the interval + * is the exact time that the timer last expired. Therefore, this + * function will cause the timer to be stable over time, unlike the + * timer_rester() function. + * + * \param t A pointer to the timer. + * + * \sa timer_restart() + */ +void +timer_reset(struct timer *t) +{ + t->start += t->interval; +} +/*---------------------------------------------------------------------------*/ +/** + * Restart the timer from the current point in time + * + * This function restarts a timer with the same interval that was + * given to the timer_set() function. The timer will start at the + * current time. + * + * \note A periodic timer will drift if this function is used to reset + * it. For preioric timers, use the timer_reset() function instead. + * + * \param t A pointer to the timer. + * + * \sa timer_reset() + */ +void +timer_restart(struct timer *t) +{ + t->start = clock_time(); +} +/*---------------------------------------------------------------------------*/ +/** + * Check if a timer has expired. + * + * This function tests if a timer has expired and returns true or + * false depending on its status. + * + * \param t A pointer to the timer + * + * \return Non-zero if the timer has expired, zero otherwise. + * + */ +int +timer_expired(struct timer *t) +{ + return (clock_time_t)(clock_time() - t->start) >= (clock_time_t)t->interval; +} +/*---------------------------------------------------------------------------*/ + +/** @} */ diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/timer.h b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/timer.h new file mode 100644 index 000000000..e28e3ca5f --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/timer.h @@ -0,0 +1,86 @@ +/** + * \defgroup timer Timer library + * + * The timer library provides functions for setting, resetting and + * restarting timers, and for checking if a timer has expired. An + * application must "manually" check if its timers have expired; this + * is not done automatically. + * + * A timer is declared as a \c struct \c timer and all access to the + * timer is made by a pointer to the declared timer. + * + * \note The timer library uses the \ref clock "Clock library" to + * measure time. Intervals should be specified in the format used by + * the clock library. + * + * @{ + */ + + +/** + * \file + * Timer library header file. + * \author + * Adam Dunkels + */ + +/* + * Copyright (c) 2004, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * Author: Adam Dunkels + * + * $Id: timer.h,v 1.3 2006/06/11 21:46:39 adam Exp $ + */ +#ifndef __TIMER_H__ +#define __TIMER_H__ + +#include "clock.h" + +/** + * A timer. + * + * This structure is used for declaring a timer. The timer must be set + * with timer_set() before it can be used. + * + * \hideinitializer + */ +struct timer { + clock_time_t start; + clock_time_t interval; +}; + +void timer_set(struct timer *t, clock_time_t interval); +void timer_reset(struct timer *t); +void timer_restart(struct timer *t); +int timer_expired(struct timer *t); + +#endif /* __TIMER_H__ */ + +/** @} */ diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-fw.c b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-fw.c new file mode 100644 index 000000000..2a85a6d9a --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-fw.c @@ -0,0 +1,532 @@ +/* + * Copyright (c) 2004, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * Author: Adam Dunkels + * + * $Id: uip-fw.c,v 1.2 2006/06/12 08:00:30 adam Exp $ + */ +/** + * \addtogroup uip + * @{ + */ + +/** + * \defgroup uipfw uIP packet forwarding + * @{ + * + */ + +/** + * \file + * uIP packet forwarding. + * \author Adam Dunkels + * + * This file implements a number of simple functions which do packet + * forwarding over multiple network interfaces with uIP. + * + */ + +#include "uip.h" +#include "uip_arch.h" +#include "uip-fw.h" + +#include /* for memcpy() */ + +/* + * The list of registered network interfaces. + */ +static struct uip_fw_netif *netifs = NULL; + +/* + * A pointer to the default network interface. + */ +static struct uip_fw_netif *defaultnetif = NULL; + +struct tcpip_hdr { + /* IP header. */ + u8_t vhl, + tos; + u16_t len, + ipid, + ipoffset; + u8_t ttl, + proto; + u16_t ipchksum; + u16_t srcipaddr[2], + destipaddr[2]; + + /* TCP header. */ + u16_t srcport, + destport; + u8_t seqno[4], + ackno[4], + tcpoffset, + flags, + wnd[2]; + u16_t tcpchksum; + u8_t urgp[2]; + u8_t optdata[4]; +} PACK_STRUCT_END; + +struct icmpip_hdr { + /* IP header. */ + u8_t vhl, + tos, + len[2], + ipid[2], + ipoffset[2], + ttl, + proto; + u16_t ipchksum; + u16_t srcipaddr[2], + destipaddr[2]; + /* ICMP (echo) header. */ + u8_t type, icode; + u16_t icmpchksum; + u16_t id, seqno; + u8_t payload[1]; +} PACK_STRUCT_END; + +/* ICMP ECHO. */ +#define ICMP_ECHO 8 + +/* ICMP TIME-EXCEEDED. */ +#define ICMP_TE 11 + +/* + * Pointer to the TCP/IP headers of the packet in the uip_buf buffer. + */ +#define BUF ((struct tcpip_hdr *)&uip_buf[UIP_LLH_LEN]) + +/* + * Pointer to the ICMP/IP headers of the packet in the uip_buf buffer. + */ +#define ICMPBUF ((struct icmpip_hdr *)&uip_buf[UIP_LLH_LEN]) + +/* + * Certain fields of an IP packet that are used for identifying + * duplicate packets. + */ +struct fwcache_entry { + u16_t timer; + + u16_t srcipaddr[2]; + u16_t destipaddr[2]; + u16_t ipid; + u8_t proto; + u8_t unused; + +#if notdef + u16_t payload[2]; +#endif + +#if UIP_REASSEMBLY > 0 + u16_t len, offset; +#endif +}; + +/* + * The number of packets to remember when looking for duplicates. + */ +#ifdef UIP_CONF_FWCACHE_SIZE +#define FWCACHE_SIZE UIP_CONF_FWCACHE_SIZE +#else +#define FWCACHE_SIZE 2 +#endif + + +/* + * A cache of packet header fields which are used for + * identifying duplicate packets. + */ +static struct fwcache_entry fwcache[FWCACHE_SIZE]; + +/** + * \internal + * The time that a packet cache is active. + */ +#define FW_TIME 20 + +/*------------------------------------------------------------------------------*/ +/** + * Initialize the uIP packet forwarding module. + */ +/*------------------------------------------------------------------------------*/ +void +uip_fw_init(void) +{ + struct uip_fw_netif *t; + defaultnetif = NULL; + while(netifs != NULL) { + t = netifs; + netifs = netifs->next; + t->next = NULL; + } +} +/*------------------------------------------------------------------------------*/ +/** + * \internal + * Check if an IP address is within the network defined by an IP + * address and a netmask. + * + * \param ipaddr The IP address to be checked. + * \param netipaddr The IP address of the network. + * \param netmask The netmask of the network. + * + * \return Non-zero if IP address is in network, zero otherwise. + */ +/*------------------------------------------------------------------------------*/ +static unsigned char +ipaddr_maskcmp(u16_t *ipaddr, u16_t *netipaddr, u16_t *netmask) +{ + return (ipaddr[0] & netmask [0]) == (netipaddr[0] & netmask[0]) && + (ipaddr[1] & netmask[1]) == (netipaddr[1] & netmask[1]); +} +/*------------------------------------------------------------------------------*/ +/** + * \internal + * Send out an ICMP TIME-EXCEEDED message. + * + * This function replaces the packet in the uip_buf buffer with the + * ICMP packet. + */ +/*------------------------------------------------------------------------------*/ +static void +time_exceeded(void) +{ + u16_t tmp16; + + /* We don't send out ICMP errors for ICMP messages. */ + if(ICMPBUF->proto == UIP_PROTO_ICMP) { + uip_len = 0; + return; + } + /* Copy fields from packet header into payload of this ICMP packet. */ + memcpy(&(ICMPBUF->payload[0]), ICMPBUF, 28); + + /* Set the ICMP type and code. */ + ICMPBUF->type = ICMP_TE; + ICMPBUF->icode = 0; + + /* Calculate the ICMP checksum. */ + ICMPBUF->icmpchksum = 0; + ICMPBUF->icmpchksum = ~uip_chksum((u16_t *)&(ICMPBUF->type), 36); + + /* Set the IP destination address to be the source address of the + original packet. */ + tmp16= BUF->destipaddr[0]; + BUF->destipaddr[0] = BUF->srcipaddr[0]; + BUF->srcipaddr[0] = tmp16; + tmp16 = BUF->destipaddr[1]; + BUF->destipaddr[1] = BUF->srcipaddr[1]; + BUF->srcipaddr[1] = tmp16; + + /* Set our IP address as the source address. */ + BUF->srcipaddr[0] = uip_hostaddr[0]; + BUF->srcipaddr[1] = uip_hostaddr[1]; + + /* The size of the ICMP time exceeded packet is 36 + the size of the + IP header (20) = 56. */ + uip_len = 56; + ICMPBUF->len[0] = 0; + ICMPBUF->len[1] = uip_len; + + /* Fill in the other fields in the IP header. */ + ICMPBUF->vhl = 0x45; + ICMPBUF->tos = 0; + ICMPBUF->ipoffset[0] = ICMPBUF->ipoffset[1] = 0; + ICMPBUF->ttl = UIP_TTL; + ICMPBUF->proto = UIP_PROTO_ICMP; + + /* Calculate IP checksum. */ + ICMPBUF->ipchksum = 0; + ICMPBUF->ipchksum = ~(uip_ipchksum()); + + +} +/*------------------------------------------------------------------------------*/ +/** + * \internal + * Register a packet in the forwarding cache so that it won't be + * forwarded again. + */ +/*------------------------------------------------------------------------------*/ +static void +fwcache_register(void) +{ + struct fwcache_entry *fw; + int i, oldest; + + oldest = FW_TIME; + fw = NULL; + + /* Find the oldest entry in the cache. */ + for(i = 0; i < FWCACHE_SIZE; ++i) { + if(fwcache[i].timer == 0) { + fw = &fwcache[i]; + break; + } else if(fwcache[i].timer <= oldest) { + fw = &fwcache[i]; + oldest = fwcache[i].timer; + } + } + + fw->timer = FW_TIME; + fw->ipid = BUF->ipid; + fw->srcipaddr[0] = BUF->srcipaddr[0]; + fw->srcipaddr[1] = BUF->srcipaddr[1]; + fw->destipaddr[0] = BUF->destipaddr[0]; + fw->destipaddr[1] = BUF->destipaddr[1]; + fw->proto = BUF->proto; +#if notdef + fw->payload[0] = BUF->srcport; + fw->payload[1] = BUF->destport; +#endif +#if UIP_REASSEMBLY > 0 + fw->len = BUF->len; + fw->offset = BUF->ipoffset; +#endif +} +/*------------------------------------------------------------------------------*/ +/** + * \internal + * Find a network interface for the IP packet in uip_buf. + */ +/*------------------------------------------------------------------------------*/ +static struct uip_fw_netif * +find_netif(void) +{ + struct uip_fw_netif *netif; + + /* Walk through every network interface to check for a match. */ + for(netif = netifs; netif != NULL; netif = netif->next) { + if(ipaddr_maskcmp(BUF->destipaddr, netif->ipaddr, + netif->netmask)) { + /* If there was a match, we break the loop. */ + return netif; + } + } + + /* If no matching netif was found, we use default netif. */ + return defaultnetif; +} +/*------------------------------------------------------------------------------*/ +/** + * Output an IP packet on the correct network interface. + * + * The IP packet should be present in the uip_buf buffer and its + * length in the global uip_len variable. + * + * \retval UIP_FW_ZEROLEN Indicates that a zero-length packet + * transmission was attempted and that no packet was sent. + * + * \retval UIP_FW_NOROUTE No suitable network interface could be found + * for the outbound packet, and the packet was not sent. + * + * \return The return value from the actual network interface output + * function is passed unmodified as a return value. + */ +/*------------------------------------------------------------------------------*/ +u8_t +uip_fw_output(void) +{ + struct uip_fw_netif *netif; + + if(uip_len == 0) { + return UIP_FW_ZEROLEN; + } + + fwcache_register(); + +#if UIP_BROADCAST + /* Link local broadcasts go out on all interfaces. */ + if(/*BUF->proto == UIP_PROTO_UDP &&*/ + BUF->destipaddr[0] == 0xffff && + BUF->destipaddr[1] == 0xffff) { + if(defaultnetif != NULL) { + defaultnetif->output(); + } + for(netif = netifs; netif != NULL; netif = netif->next) { + netif->output(); + } + return UIP_FW_OK; + } +#endif /* UIP_BROADCAST */ + + netif = find_netif(); + /* printf("uip_fw_output: netif %p ->output %p len %d\n", netif, + netif->output, + uip_len);*/ + + if(netif == NULL) { + return UIP_FW_NOROUTE; + } + /* If we now have found a suitable network interface, we call its + output function to send out the packet. */ + return netif->output(); +} +/*------------------------------------------------------------------------------*/ +/** + * Forward an IP packet in the uip_buf buffer. + * + * + * + * \return UIP_FW_FORWARDED if the packet was forwarded, UIP_FW_LOCAL if + * the packet should be processed locally. + */ +/*------------------------------------------------------------------------------*/ +u8_t +uip_fw_forward(void) +{ + struct fwcache_entry *fw; + + /* First check if the packet is destined for ourselves and return 0 + to indicate that the packet should be processed locally. */ + if(BUF->destipaddr[0] == uip_hostaddr[0] && + BUF->destipaddr[1] == uip_hostaddr[1]) { + return UIP_FW_LOCAL; + } + + /* If we use ping IP address configuration, and our IP address is + not yet configured, we should intercept all ICMP echo packets. */ +#if UIP_PINGADDRCONF + if((uip_hostaddr[0] | uip_hostaddr[1]) == 0 && + BUF->proto == UIP_PROTO_ICMP && + ICMPBUF->type == ICMP_ECHO) { + return UIP_FW_LOCAL; + } +#endif /* UIP_PINGADDRCONF */ + + /* Check if the packet is in the forwarding cache already, and if so + we drop it. */ + + for(fw = fwcache; fw < &fwcache[FWCACHE_SIZE]; ++fw) { + if(fw->timer != 0 && +#if UIP_REASSEMBLY > 0 + fw->len == BUF->len && + fw->offset == BUF->ipoffset && +#endif + fw->ipid == BUF->ipid && + fw->srcipaddr[0] == BUF->srcipaddr[0] && + fw->srcipaddr[1] == BUF->srcipaddr[1] && + fw->destipaddr[0] == BUF->destipaddr[0] && + fw->destipaddr[1] == BUF->destipaddr[1] && +#if notdef + fw->payload[0] == BUF->srcport && + fw->payload[1] == BUF->destport && +#endif + fw->proto == BUF->proto) { + /* Drop packet. */ + return UIP_FW_FORWARDED; + } + } + + /* If the TTL reaches zero we produce an ICMP time exceeded message + in the uip_buf buffer and forward that packet back to the sender + of the packet. */ + if(BUF->ttl <= 1) { + /* No time exceeded for broadcasts and multicasts! */ + if(BUF->destipaddr[0] == 0xffff && BUF->destipaddr[1] == 0xffff) { + return UIP_FW_LOCAL; + } + time_exceeded(); + } + + /* Decrement the TTL (time-to-live) value in the IP header */ + BUF->ttl = BUF->ttl - 1; + + /* Update the IP checksum. */ + if(BUF->ipchksum >= HTONS(0xffff - 0x0100)) { + BUF->ipchksum = BUF->ipchksum + HTONS(0x0100) + 1; + } else { + BUF->ipchksum = BUF->ipchksum + HTONS(0x0100); + } + + if(uip_len > 0) { + uip_appdata = &uip_buf[UIP_LLH_LEN + UIP_TCPIP_HLEN]; + uip_fw_output(); + } + +#if UIP_BROADCAST + if(BUF->destipaddr[0] == 0xffff && BUF->destipaddr[1] == 0xffff) { + return UIP_FW_LOCAL; + } +#endif /* UIP_BROADCAST */ + + /* Return non-zero to indicate that the packet was forwarded and that no + other processing should be made. */ + return UIP_FW_FORWARDED; +} +/*------------------------------------------------------------------------------*/ +/** + * Register a network interface with the forwarding module. + * + * \param netif A pointer to the network interface that is to be + * registered. + */ +/*------------------------------------------------------------------------------*/ +void +uip_fw_register(struct uip_fw_netif *netif) +{ + netif->next = netifs; + netifs = netif; +} +/*------------------------------------------------------------------------------*/ +/** + * Register a default network interface. + * + * All packets that don't go out on any of the other interfaces will + * be routed to the default interface. + * + * \param netif A pointer to the network interface that is to be + * registered. + */ +/*------------------------------------------------------------------------------*/ +void +uip_fw_default(struct uip_fw_netif *netif) +{ + defaultnetif = netif; +} +/*------------------------------------------------------------------------------*/ +/** + * Perform periodic processing. + */ +/*------------------------------------------------------------------------------*/ +void +uip_fw_periodic(void) +{ + struct fwcache_entry *fw; + for(fw = fwcache; fw < &fwcache[FWCACHE_SIZE]; ++fw) { + if(fw->timer > 0) { + --fw->timer; + } + } +} +/*------------------------------------------------------------------------------*/ diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-fw.h b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-fw.h new file mode 100644 index 000000000..e854ecefe --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-fw.h @@ -0,0 +1,176 @@ +/** + * \addtogroup uipfw + * @{ + */ + +/** + * \file + * uIP packet forwarding header file. + * \author Adam Dunkels + */ + +/* + * Copyright (c) 2004, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * Author: Adam Dunkels + * + * $Id: uip-fw.h,v 1.2 2006/06/12 08:00:30 adam Exp $ + */ +#ifndef __UIP_FW_H__ +#define __UIP_FW_H__ + +#include "uip.h" + +/** + * Representation of a uIP network interface. + */ +struct uip_fw_netif { + struct uip_fw_netif *next; /**< Pointer to the next interface when + linked in a list. */ + u16_t ipaddr[2]; /**< The IP address of this interface. */ + u16_t netmask[2]; /**< The netmask of the interface. */ + u8_t (* output)(void); + /**< A pointer to the function that + sends a packet. */ +}; + +/** + * Intantiating macro for a uIP network interface. + * + * Example: + \code + struct uip_fw_netif slipnetif = + {UIP_FW_NETIF(192,168,76,1, 255,255,255,0, slip_output)}; + \endcode + * \param ip1,ip2,ip3,ip4 The IP address of the network interface. + * + * \param nm1,nm2,nm3,nm4 The netmask of the network interface. + * + * \param outputfunc A pointer to the output function of the network interface. + * + * \hideinitializer + */ +#define UIP_FW_NETIF(ip1,ip2,ip3,ip4, nm1,nm2,nm3,nm4, outputfunc) \ + NULL, \ + {HTONS((ip1 << 8) | ip2), HTONS((ip3 << 8) | ip4)}, \ + {HTONS((nm1 << 8) | nm2), HTONS((nm3 << 8) | nm4)}, \ + outputfunc + +/** + * Set the IP address of a network interface. + * + * \param netif A pointer to the uip_fw_netif structure for the network interface. + * + * \param addr A pointer to an IP address. + * + * \hideinitializer + */ +#define uip_fw_setipaddr(netif, addr) \ + do { (netif)->ipaddr[0] = ((u16_t *)(addr))[0]; \ + (netif)->ipaddr[1] = ((u16_t *)(addr))[1]; } while(0) +/** + * Set the netmask of a network interface. + * + * \param netif A pointer to the uip_fw_netif structure for the network interface. + * + * \param addr A pointer to an IP address representing the netmask. + * + * \hideinitializer + */ +#define uip_fw_setnetmask(netif, addr) \ + do { (netif)->netmask[0] = ((u16_t *)(addr))[0]; \ + (netif)->netmask[1] = ((u16_t *)(addr))[1]; } while(0) + +void uip_fw_init(void); +u8_t uip_fw_forward(void); +u8_t uip_fw_output(void); +void uip_fw_register(struct uip_fw_netif *netif); +void uip_fw_default(struct uip_fw_netif *netif); +void uip_fw_periodic(void); + + +/** + * A non-error message that indicates that a packet should be + * processed locally. + * + * \hideinitializer + */ +#define UIP_FW_LOCAL 0 + +/** + * A non-error message that indicates that something went OK. + * + * \hideinitializer + */ +#define UIP_FW_OK 0 + +/** + * A non-error message that indicates that a packet was forwarded. + * + * \hideinitializer + */ +#define UIP_FW_FORWARDED 1 + +/** + * A non-error message that indicates that a zero-length packet + * transmission was attempted, and that no packet was sent. + * + * \hideinitializer + */ +#define UIP_FW_ZEROLEN 2 + +/** + * An error message that indicates that a packet that was too large + * for the outbound network interface was detected. + * + * \hideinitializer + */ +#define UIP_FW_TOOLARGE 3 + +/** + * An error message that indicates that no suitable interface could be + * found for an outbound packet. + * + * \hideinitializer + */ +#define UIP_FW_NOROUTE 4 + +/** + * An error message that indicates that a packet that should be + * forwarded or output was dropped. + * + * \hideinitializer + */ +#define UIP_FW_DROPPED 5 + + +#endif /* __UIP_FW_H__ */ + +/** @} */ diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-neighbor.c b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-neighbor.c new file mode 100644 index 000000000..6920960f6 --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-neighbor.c @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2006, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: uip-neighbor.c,v 1.2 2006/06/12 08:00:30 adam Exp $ + */ + +/** + * \file + * Database of link-local neighbors, used by IPv6 code and + * to be used by a future ARP code rewrite. + * \author + * Adam Dunkels + */ + +#include "uip-neighbor.h" + +#include +#include + +#define MAX_TIME 128 + +#ifdef UIP_NEIGHBOR_CONF_ENTRIES +#define ENTRIES UIP_NEIGHBOR_CONF_ENTRIES +#else /* UIP_NEIGHBOR_CONF_ENTRIES */ +#define ENTRIES 8 +#endif /* UIP_NEIGHBOR_CONF_ENTRIES */ + +struct neighbor_entry { + uip_ipaddr_t ipaddr; + struct uip_neighbor_addr addr; + u8_t time; +}; +static struct neighbor_entry entries[ENTRIES]; + +/*---------------------------------------------------------------------------*/ +void +uip_neighbor_init(void) +{ + int i; + + for(i = 0; i < ENTRIES; ++i) { + entries[i].time = MAX_TIME; + } +} +/*---------------------------------------------------------------------------*/ +void +uip_neighbor_periodic(void) +{ + int i; + + for(i = 0; i < ENTRIES; ++i) { + if(entries[i].time < MAX_TIME) { + entries[i].time++; + } + } +} +/*---------------------------------------------------------------------------*/ +void +uip_neighbor_add(uip_ipaddr_t ipaddr, struct uip_neighbor_addr *addr) +{ + int i, oldest; + u8_t oldest_time; + + printf("Adding neighbor with link address %02x:%02x:%02x:%02x:%02x:%02x\n", + addr->addr.addr[0], addr->addr.addr[1], addr->addr.addr[2], addr->addr.addr[3], + addr->addr.addr[4], addr->addr.addr[5]); + + /* Find the first unused entry or the oldest used entry. */ + oldest_time = 0; + oldest = 0; + for(i = 0; i < ENTRIES; ++i) { + if(entries[i].time == MAX_TIME) { + oldest = i; + break; + } + if(uip_ipaddr_cmp(entries[i].ipaddr, addr)) { + oldest = i; + break; + } + if(entries[i].time > oldest_time) { + oldest = i; + oldest_time = entries[i].time; + } + } + + /* Use the oldest or first free entry (either pointed to by the + "oldest" variable). */ + entries[oldest].time = 0; + uip_ipaddr_copy(entries[oldest].ipaddr, ipaddr); + memcpy(&entries[oldest].addr, addr, sizeof(struct uip_neighbor_addr)); +} +/*---------------------------------------------------------------------------*/ +static struct neighbor_entry * +find_entry(uip_ipaddr_t ipaddr) +{ + int i; + + for(i = 0; i < ENTRIES; ++i) { + if(uip_ipaddr_cmp(entries[i].ipaddr, ipaddr)) { + return &entries[i]; + } + } + return NULL; +} +/*---------------------------------------------------------------------------*/ +void +uip_neighbor_update(uip_ipaddr_t ipaddr) +{ + struct neighbor_entry *e; + + e = find_entry(ipaddr); + if(e != NULL) { + e->time = 0; + } +} +/*---------------------------------------------------------------------------*/ +struct uip_neighbor_addr * +uip_neighbor_lookup(uip_ipaddr_t ipaddr) +{ + struct neighbor_entry *e; + + e = find_entry(ipaddr); + if(e != NULL) { + /* printf("Lookup neighbor with link address %02x:%02x:%02x:%02x:%02x:%02x\n", + e->addr.addr.addr[0], e->addr.addr.addr[1], e->addr.addr.addr[2], e->addr.addr.addr[3], + e->addr.addr.addr[4], e->addr.addr.addr[5]);*/ + + return &e->addr; + } + return NULL; +} +/*---------------------------------------------------------------------------*/ diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-neighbor.h b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-neighbor.h new file mode 100644 index 000000000..aca096f2c --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-neighbor.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2006, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: uip-neighbor.h,v 1.2 2006/06/12 08:00:30 adam Exp $ + */ + +/** + * \file + * Header file for database of link-local neighbors, used by + * IPv6 code and to be used by future ARP code. + * \author + * Adam Dunkels + */ + +#ifndef __UIP_NEIGHBOR_H__ +#define __UIP_NEIGHBOR_H__ + +#include "uip.h" + +struct uip_neighbor_addr { +#if UIP_NEIGHBOR_CONF_ADDRTYPE + UIP_NEIGHBOR_CONF_ADDRTYPE addr; +#else + struct uip_eth_addr addr; +#endif +}; + +void uip_neighbor_init(void); +void uip_neighbor_add(uip_ipaddr_t ipaddr, struct uip_neighbor_addr *addr); +void uip_neighbor_update(uip_ipaddr_t ipaddr); +struct uip_neighbor_addr *uip_neighbor_lookup(uip_ipaddr_t ipaddr); +void uip_neighbor_periodic(void); + +#endif /* __UIP-NEIGHBOR_H__ */ diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-split.c b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-split.c new file mode 100644 index 000000000..639b9fcd5 --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-split.c @@ -0,0 +1,136 @@ +/* + * Copyright (c) 2004, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * Author: Adam Dunkels + * + * $Id: uip-split.c,v 1.2 2006/06/12 08:00:30 adam Exp $ + */ + +#include + +#include "uip-split.h" +#include "uip.h" +#include "uip-fw.h" +#include "uip_arch.h" + + + +#define BUF ((struct uip_tcpip_hdr *)&uip_buf[UIP_LLH_LEN]) + +/*-----------------------------------------------------------------------------*/ +void +uip_split_output(void) +{ + u16_t tcplen, len1, len2; + + /* We only try to split maximum sized TCP segments. */ + if(BUF->proto == UIP_PROTO_TCP && + uip_len == UIP_BUFSIZE - UIP_LLH_LEN) { + + tcplen = uip_len - UIP_TCPIP_HLEN; + /* Split the segment in two. If the original packet length was + odd, we make the second packet one byte larger. */ + len1 = len2 = tcplen / 2; + if(len1 + len2 < tcplen) { + ++len2; + } + + /* Create the first packet. This is done by altering the length + field of the IP header and updating the checksums. */ + uip_len = len1 + UIP_TCPIP_HLEN; +#if UIP_CONF_IPV6 + /* For IPv6, the IP length field does not include the IPv6 IP header + length. */ + BUF->len[0] = ((uip_len - UIP_IPH_LEN) >> 8); + BUF->len[1] = ((uip_len - UIP_IPH_LEN) & 0xff); +#else /* UIP_CONF_IPV6 */ + BUF->len[0] = uip_len >> 8; + BUF->len[1] = uip_len & 0xff; +#endif /* UIP_CONF_IPV6 */ + + /* Recalculate the TCP checksum. */ + BUF->tcpchksum = 0; + BUF->tcpchksum = ~(uip_tcpchksum()); + +#if !UIP_CONF_IPV6 + /* Recalculate the IP checksum. */ + BUF->ipchksum = 0; + BUF->ipchksum = ~(uip_ipchksum()); +#endif /* UIP_CONF_IPV6 */ + + /* Transmit the first packet. */ + /* uip_fw_output();*/ + tcpip_output(); + + /* Now, create the second packet. To do this, it is not enough to + just alter the length field, but we must also update the TCP + sequence number and point the uip_appdata to a new place in + memory. This place is detemined by the length of the first + packet (len1). */ + uip_len = len2 + UIP_TCPIP_HLEN; +#if UIP_CONF_IPV6 + /* For IPv6, the IP length field does not include the IPv6 IP header + length. */ + BUF->len[0] = ((uip_len - UIP_IPH_LEN) >> 8); + BUF->len[1] = ((uip_len - UIP_IPH_LEN) & 0xff); +#else /* UIP_CONF_IPV6 */ + BUF->len[0] = uip_len >> 8; + BUF->len[1] = uip_len & 0xff; +#endif /* UIP_CONF_IPV6 */ + + /* uip_appdata += len1;*/ + memcpy(uip_appdata, (u8_t *)uip_appdata + len1, len2); + + uip_add32(BUF->seqno, len1); + BUF->seqno[0] = uip_acc32[0]; + BUF->seqno[1] = uip_acc32[1]; + BUF->seqno[2] = uip_acc32[2]; + BUF->seqno[3] = uip_acc32[3]; + + /* Recalculate the TCP checksum. */ + BUF->tcpchksum = 0; + BUF->tcpchksum = ~(uip_tcpchksum()); + +#if !UIP_CONF_IPV6 + /* Recalculate the IP checksum. */ + BUF->ipchksum = 0; + BUF->ipchksum = ~(uip_ipchksum()); +#endif /* UIP_CONF_IPV6 */ + + /* Transmit the second packet. */ + /* uip_fw_output();*/ + tcpip_output(); + } else { + /* uip_fw_output();*/ + tcpip_output(); + } + +} +/*-----------------------------------------------------------------------------*/ diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-split.h b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-split.h new file mode 100644 index 000000000..446e19200 --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-split.h @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2004, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * Author: Adam Dunkels + * + * $Id: uip-split.h,v 1.2 2006/06/12 08:00:30 adam Exp $ + */ +/** + * \addtogroup uip + * @{ + */ + +/** + * \defgroup uipsplit uIP TCP throughput booster hack + * @{ + * + * The basic uIP TCP implementation only allows each TCP connection to + * have a single TCP segment in flight at any given time. Because of + * the delayed ACK algorithm employed by most TCP receivers, uIP's + * limit on the amount of in-flight TCP segments seriously reduces the + * maximum achievable throughput for sending data from uIP. + * + * The uip-split module is a hack which tries to remedy this + * situation. By splitting maximum sized outgoing TCP segments into + * two, the delayed ACK algorithm is not invoked at TCP + * receivers. This improves the throughput when sending data from uIP + * by orders of magnitude. + * + * The uip-split module uses the uip-fw module (uIP IP packet + * forwarding) for sending packets. Therefore, the uip-fw module must + * be set up with the appropriate network interfaces for this module + * to work. + */ + + +/** + * \file + * Module for splitting outbound TCP segments in two to avoid the + * delayed ACK throughput degradation. + * \author + * Adam Dunkels + * + */ + +#ifndef __UIP_SPLIT_H__ +#define __UIP_SPLIT_H__ + +/** + * Handle outgoing packets. + * + * This function inspects an outgoing packet in the uip_buf buffer and + * sends it out using the uip_fw_output() function. If the packet is a + * full-sized TCP segment it will be split into two segments and + * transmitted separately. This function should be called instead of + * the actual device driver output function, or the uip_fw_output() + * function. + * + * The headers of the outgoing packet is assumed to be in the uip_buf + * buffer and the payload is assumed to be wherever uip_appdata + * points. The length of the outgoing packet is assumed to be in the + * uip_len variable. + * + */ +void uip_split_output(void); + +#endif /* __UIP_SPLIT_H__ */ + +/** @} */ +/** @} */ diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/uip.c b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/uip.c new file mode 100644 index 000000000..803ec5654 --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/uip.c @@ -0,0 +1,1904 @@ +#define DEBUG_PRINTF(...) /*printf(__VA_ARGS__)*/ + +/** + * \defgroup uip The uIP TCP/IP stack + * @{ + * + * uIP is an implementation of the TCP/IP protocol stack intended for + * small 8-bit and 16-bit microcontrollers. + * + * uIP provides the necessary protocols for Internet communication, + * with a very small code footprint and RAM requirements - the uIP + * code size is on the order of a few kilobytes and RAM usage is on + * the order of a few hundred bytes. + */ + +/** + * \file + * The uIP TCP/IP stack code. + * \author Adam Dunkels + */ + +/* + * Copyright (c) 2001-2003, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: uip.c,v 1.65 2006/06/11 21:46:39 adam Exp $ + * + */ + +/* + * uIP is a small implementation of the IP, UDP and TCP protocols (as + * well as some basic ICMP stuff). The implementation couples the IP, + * UDP, TCP and the application layers very tightly. To keep the size + * of the compiled code down, this code frequently uses the goto + * statement. While it would be possible to break the uip_process() + * function into many smaller functions, this would increase the code + * size because of the overhead of parameter passing and the fact that + * the optimier would not be as efficient. + * + * The principle is that we have a small buffer, called the uip_buf, + * in which the device driver puts an incoming packet. The TCP/IP + * stack parses the headers in the packet, and calls the + * application. If the remote host has sent data to the application, + * this data is present in the uip_buf and the application read the + * data from there. It is up to the application to put this data into + * a byte stream if needed. The application will not be fed with data + * that is out of sequence. + * + * If the application whishes to send data to the peer, it should put + * its data into the uip_buf. The uip_appdata pointer points to the + * first available byte. The TCP/IP stack will calculate the + * checksums, and fill in the necessary header fields and finally send + * the packet back to the peer. +*/ + +#include "uip.h" +#include "uipopt.h" +#include "uip_arch.h" + +#if UIP_CONF_IPV6 +#include "uip-neighbor.h" +#endif /* UIP_CONF_IPV6 */ + +#include + +/*---------------------------------------------------------------------------*/ +/* Variable definitions. */ + + +/* The IP address of this host. If it is defined to be fixed (by + setting UIP_FIXEDADDR to 1 in uipopt.h), the address is set + here. Otherwise, the address */ +#if UIP_FIXEDADDR > 0 +const uip_ipaddr_t uip_hostaddr = + {HTONS((UIP_IPADDR0 << 8) | UIP_IPADDR1), + HTONS((UIP_IPADDR2 << 8) | UIP_IPADDR3)}; +const uip_ipaddr_t uip_draddr = + {HTONS((UIP_DRIPADDR0 << 8) | UIP_DRIPADDR1), + HTONS((UIP_DRIPADDR2 << 8) | UIP_DRIPADDR3)}; +const uip_ipaddr_t uip_netmask = + {HTONS((UIP_NETMASK0 << 8) | UIP_NETMASK1), + HTONS((UIP_NETMASK2 << 8) | UIP_NETMASK3)}; +#else +uip_ipaddr_t uip_hostaddr, uip_draddr, uip_netmask; +#endif /* UIP_FIXEDADDR */ + +static const uip_ipaddr_t all_ones_addr = +#if UIP_CONF_IPV6 + {0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff}; +#else /* UIP_CONF_IPV6 */ + {0xffff,0xffff}; +#endif /* UIP_CONF_IPV6 */ +static const uip_ipaddr_t all_zeroes_addr = +#if UIP_CONF_IPV6 + {0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000}; +#else /* UIP_CONF_IPV6 */ + {0x0000,0x0000}; +#endif /* UIP_CONF_IPV6 */ + +#if UIP_FIXEDETHADDR +const struct uip_eth_addr uip_ethaddr = {{UIP_ETHADDR0, + UIP_ETHADDR1, + UIP_ETHADDR2, + UIP_ETHADDR3, + UIP_ETHADDR4, + UIP_ETHADDR5}}; +#else +struct uip_eth_addr uip_ethaddr = {{0,0,0,0,0,0}}; +#endif + +#ifndef UIP_CONF_EXTERNAL_BUFFER + +#ifdef __ICCARM__ + #pragma data_alignment=4 + u8_t uip_buf[UIP_BUFSIZE + 2]; /* The packet buffer that contains incoming packets. */ +#else + u8_t uip_buf[UIP_BUFSIZE + 2] ALIGN_STRUCT_END; /* The packet buffer that contains incoming packets. */ +#endif + +#endif /* UIP_CONF_EXTERNAL_BUFFER */ + +void *uip_appdata; /* The uip_appdata pointer points to + application data. */ +void *uip_sappdata; /* The uip_appdata pointer points to + the application data which is to + be sent. */ +#if UIP_URGDATA > 0 +void *uip_urgdata; /* The uip_urgdata pointer points to + urgent data (out-of-band data), if + present. */ +u16_t uip_urglen, uip_surglen; +#endif /* UIP_URGDATA > 0 */ + +u16_t uip_len, uip_slen; + /* The uip_len is either 8 or 16 bits, + depending on the maximum packet + size. */ + +u8_t uip_flags; /* The uip_flags variable is used for + communication between the TCP/IP stack + and the application program. */ +struct uip_conn *uip_conn; /* uip_conn always points to the current + connection. */ + +struct uip_conn uip_conns[UIP_CONNS]; + /* The uip_conns array holds all TCP + connections. */ +u16_t uip_listenports[UIP_LISTENPORTS]; + /* The uip_listenports list all currently + listning ports. */ +#if UIP_UDP +struct uip_udp_conn *uip_udp_conn; +struct uip_udp_conn uip_udp_conns[UIP_UDP_CONNS]; +#endif /* UIP_UDP */ + +static u16_t ipid; /* Ths ipid variable is an increasing + number that is used for the IP ID + field. */ + +void uip_setipid(u16_t id) { ipid = id; } + +static u8_t iss[4]; /* The iss variable is used for the TCP + initial sequence number. */ + +#if UIP_ACTIVE_OPEN +static u16_t lastport; /* Keeps track of the last port used for + a new connection. */ +#endif /* UIP_ACTIVE_OPEN */ + +/* Temporary variables. */ +u8_t uip_acc32[4]; +static u8_t c, opt; +static u16_t tmp16; + +/* Structures and definitions. */ +#define TCP_FIN 0x01 +#define TCP_SYN 0x02 +#define TCP_RST 0x04 +#define TCP_PSH 0x08 +#define TCP_ACK 0x10 +#define TCP_URG 0x20 +#define TCP_CTL 0x3f + +#define TCP_OPT_END 0 /* End of TCP options list */ +#define TCP_OPT_NOOP 1 /* "No-operation" TCP option */ +#define TCP_OPT_MSS 2 /* Maximum segment size TCP option */ + +#define TCP_OPT_MSS_LEN 4 /* Length of TCP MSS option. */ + +#define ICMP_ECHO_REPLY 0 +#define ICMP_ECHO 8 + +#define ICMP6_ECHO_REPLY 129 +#define ICMP6_ECHO 128 +#define ICMP6_NEIGHBOR_SOLICITATION 135 +#define ICMP6_NEIGHBOR_ADVERTISEMENT 136 + +#define ICMP6_FLAG_S (1 << 6) + +#define ICMP6_OPTION_SOURCE_LINK_ADDRESS 1 +#define ICMP6_OPTION_TARGET_LINK_ADDRESS 2 + + +/* Macros. */ +#define BUF ((struct uip_tcpip_hdr *)&uip_buf[UIP_LLH_LEN]) +#define FBUF ((struct uip_tcpip_hdr *)&uip_reassbuf[0]) +#define ICMPBUF ((struct uip_icmpip_hdr *)&uip_buf[UIP_LLH_LEN]) +#define UDPBUF ((struct uip_udpip_hdr *)&uip_buf[UIP_LLH_LEN]) + + +#if UIP_STATISTICS == 1 +struct uip_stats uip_stat; +#define UIP_STAT(s) s +#else +#define UIP_STAT(s) +#endif /* UIP_STATISTICS == 1 */ + +#if UIP_LOGGING == 1 +#include +void uip_log(char *msg); +#define UIP_LOG(m) uip_log(m) +#else +#define UIP_LOG(m) +#endif /* UIP_LOGGING == 1 */ + +#if ! UIP_ARCH_ADD32 +void +uip_add32(u8_t *op32, u16_t op16) +{ + uip_acc32[3] = op32[3] + (op16 & 0xff); + uip_acc32[2] = op32[2] + (op16 >> 8); + uip_acc32[1] = op32[1]; + uip_acc32[0] = op32[0]; + + if(uip_acc32[2] < (op16 >> 8)) { + ++uip_acc32[1]; + if(uip_acc32[1] == 0) { + ++uip_acc32[0]; + } + } + + + if(uip_acc32[3] < (op16 & 0xff)) { + ++uip_acc32[2]; + if(uip_acc32[2] == 0) { + ++uip_acc32[1]; + if(uip_acc32[1] == 0) { + ++uip_acc32[0]; + } + } + } +} + +#endif /* UIP_ARCH_ADD32 */ + +#if ! UIP_ARCH_CHKSUM +/*---------------------------------------------------------------------------*/ +static u16_t +chksum(u16_t sum, const u8_t *data, u16_t len) +{ + u16_t t; + const u8_t *dataptr; + const u8_t *last_byte; + + dataptr = data; + last_byte = data + len - 1; + + while(dataptr < last_byte) { /* At least two more bytes */ + t = (dataptr[0] << 8) + dataptr[1]; + sum += t; + if(sum < t) { + sum++; /* carry */ + } + dataptr += 2; + } + + if(dataptr == last_byte) { + t = (dataptr[0] << 8) + 0; + sum += t; + if(sum < t) { + sum++; /* carry */ + } + } + + /* Return sum in host byte order. */ + return sum; +} +/*---------------------------------------------------------------------------*/ +u16_t +uip_chksum(u16_t *data, u16_t len) +{ + return htons(chksum(0, (u8_t *)data, len)); +} +/*---------------------------------------------------------------------------*/ +#ifndef UIP_ARCH_IPCHKSUM +u16_t +uip_ipchksum(void) +{ + u16_t sum; + + sum = chksum(0, &uip_buf[UIP_LLH_LEN], UIP_IPH_LEN); + DEBUG_PRINTF("uip_ipchksum: sum 0x%04x\n", sum); + return (sum == 0) ? 0xffff : htons(sum); +} +#endif +/*---------------------------------------------------------------------------*/ +static u16_t +upper_layer_chksum(u8_t proto) +{ + u16_t upper_layer_len; + u16_t sum; + +#if UIP_CONF_IPV6 + upper_layer_len = (((u16_t)(BUF->len[0]) << 8) + BUF->len[1]); +#else /* UIP_CONF_IPV6 */ + upper_layer_len = (((u16_t)(BUF->len[0]) << 8) + BUF->len[1]) - UIP_IPH_LEN; +#endif /* UIP_CONF_IPV6 */ + + /* First sum pseudoheader. */ + + /* IP protocol and length fields. This addition cannot carry. */ + sum = upper_layer_len + proto; + /* Sum IP source and destination addresses. */ + sum = chksum(sum, (u8_t *)&BUF->srcipaddr[0], 2 * sizeof(uip_ipaddr_t)); + + /* Sum TCP header and data. */ + sum = chksum(sum, &uip_buf[UIP_IPH_LEN + UIP_LLH_LEN], + upper_layer_len); + + return (sum == 0) ? 0xffff : htons(sum); +} +/*---------------------------------------------------------------------------*/ +#if UIP_CONF_IPV6 +u16_t +uip_icmp6chksum(void) +{ + return upper_layer_chksum(UIP_PROTO_ICMP6); + +} +#endif /* UIP_CONF_IPV6 */ +/*---------------------------------------------------------------------------*/ +u16_t +uip_tcpchksum(void) +{ + return upper_layer_chksum(UIP_PROTO_TCP); +} +/*---------------------------------------------------------------------------*/ +#if UIP_UDP_CHECKSUMS +u16_t +uip_udpchksum(void) +{ + return upper_layer_chksum(UIP_PROTO_UDP); +} +#endif /* UIP_UDP_CHECKSUMS */ +#endif /* UIP_ARCH_CHKSUM */ +/*---------------------------------------------------------------------------*/ +void +uip_init(void) +{ + for(c = 0; c < UIP_LISTENPORTS; ++c) { + uip_listenports[c] = 0; + } + for(c = 0; c < UIP_CONNS; ++c) { + uip_conns[c].tcpstateflags = UIP_CLOSED; + } +#if UIP_ACTIVE_OPEN + lastport = 1024; +#endif /* UIP_ACTIVE_OPEN */ + +#if UIP_UDP + for(c = 0; c < UIP_UDP_CONNS; ++c) { + uip_udp_conns[c].lport = 0; + } +#endif /* UIP_UDP */ + + + /* IPv4 initialization. */ +#if UIP_FIXEDADDR == 0 + /* uip_hostaddr[0] = uip_hostaddr[1] = 0;*/ +#endif /* UIP_FIXEDADDR */ + +} +/*---------------------------------------------------------------------------*/ +#if UIP_ACTIVE_OPEN +struct uip_conn * +uip_connect(uip_ipaddr_t *ripaddr, u16_t rport) +{ + register struct uip_conn *conn, *cconn; + + /* Find an unused local port. */ + again: + ++lastport; + + if(lastport >= 32000) { + lastport = 4096; + } + + /* Check if this port is already in use, and if so try to find + another one. */ + for(c = 0; c < UIP_CONNS; ++c) { + conn = &uip_conns[c]; + if(conn->tcpstateflags != UIP_CLOSED && + conn->lport == htons(lastport)) { + goto again; + } + } + + conn = 0; + for(c = 0; c < UIP_CONNS; ++c) { + cconn = &uip_conns[c]; + if(cconn->tcpstateflags == UIP_CLOSED) { + conn = cconn; + break; + } + if(cconn->tcpstateflags == UIP_TIME_WAIT) { + if(conn == 0 || + cconn->timer > conn->timer) { + conn = cconn; + } + } + } + + if(conn == 0) { + return 0; + } + + conn->tcpstateflags = UIP_SYN_SENT; + + conn->snd_nxt[0] = iss[0]; + conn->snd_nxt[1] = iss[1]; + conn->snd_nxt[2] = iss[2]; + conn->snd_nxt[3] = iss[3]; + + conn->initialmss = conn->mss = UIP_TCP_MSS; + + conn->len = 1; /* TCP length of the SYN is one. */ + conn->nrtx = 0; + conn->timer = 1; /* Send the SYN next time around. */ + conn->rto = UIP_RTO; + conn->sa = 0; + conn->sv = 16; /* Initial value of the RTT variance. */ + conn->lport = htons(lastport); + conn->rport = rport; + uip_ipaddr_copy(&conn->ripaddr, ripaddr); + + return conn; +} +#endif /* UIP_ACTIVE_OPEN */ +/*---------------------------------------------------------------------------*/ +#if UIP_UDP +struct uip_udp_conn * +uip_udp_new(uip_ipaddr_t *ripaddr, u16_t rport) +{ + register struct uip_udp_conn *conn; + + /* Find an unused local port. */ + again: + ++lastport; + + if(lastport >= 32000) { + lastport = 4096; + } + + for(c = 0; c < UIP_UDP_CONNS; ++c) { + if(uip_udp_conns[c].lport == htons(lastport)) { + goto again; + } + } + + + conn = 0; + for(c = 0; c < UIP_UDP_CONNS; ++c) { + if(uip_udp_conns[c].lport == 0) { + conn = &uip_udp_conns[c]; + break; + } + } + + if(conn == 0) { + return 0; + } + + conn->lport = HTONS(lastport); + conn->rport = rport; + if(ripaddr == NULL) { + memset(conn->ripaddr, 0, sizeof(uip_ipaddr_t)); + } else { + uip_ipaddr_copy(&conn->ripaddr, ripaddr); + } + conn->ttl = UIP_TTL; + + return conn; +} +#endif /* UIP_UDP */ +/*---------------------------------------------------------------------------*/ +void +uip_unlisten(u16_t port) +{ + for(c = 0; c < UIP_LISTENPORTS; ++c) { + if(uip_listenports[c] == port) { + uip_listenports[c] = 0; + return; + } + } +} +/*---------------------------------------------------------------------------*/ +void +uip_listen(u16_t port) +{ + for(c = 0; c < UIP_LISTENPORTS; ++c) { + if(uip_listenports[c] == 0) { + uip_listenports[c] = port; + return; + } + } +} +/*---------------------------------------------------------------------------*/ +/* XXX: IP fragment reassembly: not well-tested. */ + +#if UIP_REASSEMBLY && !UIP_CONF_IPV6 +#define UIP_REASS_BUFSIZE (UIP_BUFSIZE - UIP_LLH_LEN) +static u8_t uip_reassbuf[UIP_REASS_BUFSIZE]; +static u8_t uip_reassbitmap[UIP_REASS_BUFSIZE / (8 * 8)]; +static const u8_t bitmap_bits[8] = {0xff, 0x7f, 0x3f, 0x1f, + 0x0f, 0x07, 0x03, 0x01}; +static u16_t uip_reasslen; +static u8_t uip_reassflags; +#define UIP_REASS_FLAG_LASTFRAG 0x01 +static u8_t uip_reasstmr; + +#define IP_MF 0x20 + +static u8_t +uip_reass(void) +{ + u16_t offset, len; + u16_t i; + + /* If ip_reasstmr is zero, no packet is present in the buffer, so we + write the IP header of the fragment into the reassembly + buffer. The timer is updated with the maximum age. */ + if(uip_reasstmr == 0) { + memcpy(uip_reassbuf, &BUF->vhl, UIP_IPH_LEN); + uip_reasstmr = UIP_REASS_MAXAGE; + uip_reassflags = 0; + /* Clear the bitmap. */ + memset(uip_reassbitmap, 0, sizeof(uip_reassbitmap)); + } + + /* Check if the incoming fragment matches the one currently present + in the reasembly buffer. If so, we proceed with copying the + fragment into the buffer. */ + if(BUF->srcipaddr[0] == FBUF->srcipaddr[0] && + BUF->srcipaddr[1] == FBUF->srcipaddr[1] && + BUF->destipaddr[0] == FBUF->destipaddr[0] && + BUF->destipaddr[1] == FBUF->destipaddr[1] && + BUF->ipid[0] == FBUF->ipid[0] && + BUF->ipid[1] == FBUF->ipid[1]) { + + len = (BUF->len[0] << 8) + BUF->len[1] - (BUF->vhl & 0x0f) * 4; + offset = (((BUF->ipoffset[0] & 0x3f) << 8) + BUF->ipoffset[1]) * 8; + + /* If the offset or the offset + fragment length overflows the + reassembly buffer, we discard the entire packet. */ + if(offset > UIP_REASS_BUFSIZE || + offset + len > UIP_REASS_BUFSIZE) { + uip_reasstmr = 0; + goto nullreturn; + } + + /* Copy the fragment into the reassembly buffer, at the right + offset. */ + memcpy(&uip_reassbuf[UIP_IPH_LEN + offset], + (char *)BUF + (int)((BUF->vhl & 0x0f) * 4), + len); + + /* Update the bitmap. */ + if(offset / (8 * 8) == (offset + len) / (8 * 8)) { + /* If the two endpoints are in the same byte, we only update + that byte. */ + + uip_reassbitmap[offset / (8 * 8)] |= + bitmap_bits[(offset / 8 ) & 7] & + ~bitmap_bits[((offset + len) / 8 ) & 7]; + } else { + /* If the two endpoints are in different bytes, we update the + bytes in the endpoints and fill the stuff inbetween with + 0xff. */ + uip_reassbitmap[offset / (8 * 8)] |= + bitmap_bits[(offset / 8 ) & 7]; + for(i = 1 + offset / (8 * 8); i < (offset + len) / (8 * 8); ++i) { + uip_reassbitmap[i] = 0xff; + } + uip_reassbitmap[(offset + len) / (8 * 8)] |= + ~bitmap_bits[((offset + len) / 8 ) & 7]; + } + + /* If this fragment has the More Fragments flag set to zero, we + know that this is the last fragment, so we can calculate the + size of the entire packet. We also set the + IP_REASS_FLAG_LASTFRAG flag to indicate that we have received + the final fragment. */ + + if((BUF->ipoffset[0] & IP_MF) == 0) { + uip_reassflags |= UIP_REASS_FLAG_LASTFRAG; + uip_reasslen = offset + len; + } + + /* Finally, we check if we have a full packet in the buffer. We do + this by checking if we have the last fragment and if all bits + in the bitmap are set. */ + if(uip_reassflags & UIP_REASS_FLAG_LASTFRAG) { + /* Check all bytes up to and including all but the last byte in + the bitmap. */ + for(i = 0; i < uip_reasslen / (8 * 8) - 1; ++i) { + if(uip_reassbitmap[i] != 0xff) { + goto nullreturn; + } + } + /* Check the last byte in the bitmap. It should contain just the + right amount of bits. */ + if(uip_reassbitmap[uip_reasslen / (8 * 8)] != + (u8_t)~bitmap_bits[uip_reasslen / 8 & 7]) { + goto nullreturn; + } + + /* If we have come this far, we have a full packet in the + buffer, so we allocate a pbuf and copy the packet into it. We + also reset the timer. */ + uip_reasstmr = 0; + memcpy(BUF, FBUF, uip_reasslen); + + /* Pretend to be a "normal" (i.e., not fragmented) IP packet + from now on. */ + BUF->ipoffset[0] = BUF->ipoffset[1] = 0; + BUF->len[0] = uip_reasslen >> 8; + BUF->len[1] = uip_reasslen & 0xff; + BUF->ipchksum = 0; + BUF->ipchksum = ~(uip_ipchksum()); + + return uip_reasslen; + } + } + + nullreturn: + return 0; +} +#endif /* UIP_REASSEMBLY */ +/*---------------------------------------------------------------------------*/ +static void +uip_add_rcv_nxt(u16_t n) +{ + uip_add32(uip_conn->rcv_nxt, n); + uip_conn->rcv_nxt[0] = uip_acc32[0]; + uip_conn->rcv_nxt[1] = uip_acc32[1]; + uip_conn->rcv_nxt[2] = uip_acc32[2]; + uip_conn->rcv_nxt[3] = uip_acc32[3]; +} +/*---------------------------------------------------------------------------*/ +void +uip_process(u8_t flag) +{ + register struct uip_conn *uip_connr = uip_conn; + +#if UIP_UDP + if(flag == UIP_UDP_SEND_CONN) { + goto udp_send; + } +#endif /* UIP_UDP */ + + uip_sappdata = uip_appdata = &uip_buf[UIP_IPTCPH_LEN + UIP_LLH_LEN]; + + /* Check if we were invoked because of a poll request for a + particular connection. */ + if(flag == UIP_POLL_REQUEST) { + if((uip_connr->tcpstateflags & UIP_TS_MASK) == UIP_ESTABLISHED && + !uip_outstanding(uip_connr)) { + uip_flags = UIP_POLL; + UIP_APPCALL(); + goto appsend; + } + goto drop; + + /* Check if we were invoked because of the perodic timer fireing. */ + } else if(flag == UIP_TIMER) { +#if UIP_REASSEMBLY + if(uip_reasstmr != 0) { + --uip_reasstmr; + } +#endif /* UIP_REASSEMBLY */ + /* Increase the initial sequence number. */ + if(++iss[3] == 0) { + if(++iss[2] == 0) { + if(++iss[1] == 0) { + ++iss[0]; + } + } + } + + /* Reset the length variables. */ + uip_len = 0; + uip_slen = 0; + + /* Check if the connection is in a state in which we simply wait + for the connection to time out. If so, we increase the + connection's timer and remove the connection if it times + out. */ + if(uip_connr->tcpstateflags == UIP_TIME_WAIT || + uip_connr->tcpstateflags == UIP_FIN_WAIT_2) { + ++(uip_connr->timer); + if(uip_connr->timer == UIP_TIME_WAIT_TIMEOUT) { + uip_connr->tcpstateflags = UIP_CLOSED; + } + } else if(uip_connr->tcpstateflags != UIP_CLOSED) { + /* If the connection has outstanding data, we increase the + connection's timer and see if it has reached the RTO value + in which case we retransmit. */ + if(uip_outstanding(uip_connr)) { + uip_connr->timer = uip_connr->timer - 1; + if(uip_connr->timer == 0) { + if(uip_connr->nrtx == UIP_MAXRTX || + ((uip_connr->tcpstateflags == UIP_SYN_SENT || + uip_connr->tcpstateflags == UIP_SYN_RCVD) && + uip_connr->nrtx == UIP_MAXSYNRTX)) { + uip_connr->tcpstateflags = UIP_CLOSED; + + /* We call UIP_APPCALL() with uip_flags set to + UIP_TIMEDOUT to inform the application that the + connection has timed out. */ + uip_flags = UIP_TIMEDOUT; + UIP_APPCALL(); + + /* We also send a reset packet to the remote host. */ + BUF->flags = TCP_RST | TCP_ACK; + goto tcp_send_nodata; + } + + /* Exponential backoff. */ + uip_connr->timer = UIP_RTO << (uip_connr->nrtx > 4? + 4: + uip_connr->nrtx); + ++(uip_connr->nrtx); + + /* Ok, so we need to retransmit. We do this differently + depending on which state we are in. In ESTABLISHED, we + call upon the application so that it may prepare the + data for the retransmit. In SYN_RCVD, we resend the + SYNACK that we sent earlier and in LAST_ACK we have to + retransmit our FINACK. */ + UIP_STAT(++uip_stat.tcp.rexmit); + switch(uip_connr->tcpstateflags & UIP_TS_MASK) { + case UIP_SYN_RCVD: + /* In the SYN_RCVD state, we should retransmit our + SYNACK. */ + goto tcp_send_synack; + +#if UIP_ACTIVE_OPEN + case UIP_SYN_SENT: + /* In the SYN_SENT state, we retransmit out SYN. */ + BUF->flags = 0; + goto tcp_send_syn; +#endif /* UIP_ACTIVE_OPEN */ + + case UIP_ESTABLISHED: + /* In the ESTABLISHED state, we call upon the application + to do the actual retransmit after which we jump into + the code for sending out the packet (the apprexmit + label). */ + uip_flags = UIP_REXMIT; + UIP_APPCALL(); + goto apprexmit; + + case UIP_FIN_WAIT_1: + case UIP_CLOSING: + case UIP_LAST_ACK: + /* In all these states we should retransmit a FINACK. */ + goto tcp_send_finack; + + } + } + } else if((uip_connr->tcpstateflags & UIP_TS_MASK) == UIP_ESTABLISHED) { + /* If there was no need for a retransmission, we poll the + application for new data. */ + uip_flags = UIP_POLL; + UIP_APPCALL(); + goto appsend; + } + } + goto drop; + } +#if UIP_UDP + if(flag == UIP_UDP_TIMER) { + if(uip_udp_conn->lport != 0) { + uip_conn = NULL; + uip_sappdata = uip_appdata = &uip_buf[UIP_LLH_LEN + UIP_IPUDPH_LEN]; + uip_len = uip_slen = 0; + uip_flags = UIP_POLL; + UIP_UDP_APPCALL(); + goto udp_send; + } else { + goto drop; + } + } +#endif + + /* This is where the input processing starts. */ + UIP_STAT(++uip_stat.ip.recv); + + /* Start of IP input header processing code. */ + +#if UIP_CONF_IPV6 + /* Check validity of the IP header. */ + if((BUF->vtc & 0xf0) != 0x60) { /* IP version and header length. */ + UIP_STAT(++uip_stat.ip.drop); + UIP_STAT(++uip_stat.ip.vhlerr); + UIP_LOG("ipv6: invalid version."); + goto drop; + } +#else /* UIP_CONF_IPV6 */ + /* Check validity of the IP header. */ + if(BUF->vhl != 0x45) { /* IP version and header length. */ + UIP_STAT(++uip_stat.ip.drop); + UIP_STAT(++uip_stat.ip.vhlerr); + UIP_LOG("ip: invalid version or header length."); + goto drop; + } +#endif /* UIP_CONF_IPV6 */ + + /* Check the size of the packet. If the size reported to us in + uip_len is smaller the size reported in the IP header, we assume + that the packet has been corrupted in transit. If the size of + uip_len is larger than the size reported in the IP packet header, + the packet has been padded and we set uip_len to the correct + value.. */ + + if((BUF->len[0] << 8) + BUF->len[1] <= uip_len) { + uip_len = (BUF->len[0] << 8) + BUF->len[1]; +#if UIP_CONF_IPV6 + uip_len += 40; /* The length reported in the IPv6 header is the + length of the payload that follows the + header. However, uIP uses the uip_len variable + for holding the size of the entire packet, + including the IP header. For IPv4 this is not a + problem as the length field in the IPv4 header + contains the length of the entire packet. But + for IPv6 we need to add the size of the IPv6 + header (40 bytes). */ +#endif /* UIP_CONF_IPV6 */ + } else { + UIP_LOG("ip: packet shorter than reported in IP header."); + goto drop; + } + +#if !UIP_CONF_IPV6 + /* Check the fragment flag. */ + if((BUF->ipoffset[0] & 0x3f) != 0 || + BUF->ipoffset[1] != 0) { +#if UIP_REASSEMBLY + uip_len = uip_reass(); + if(uip_len == 0) { + goto drop; + } +#else /* UIP_REASSEMBLY */ + UIP_STAT(++uip_stat.ip.drop); + UIP_STAT(++uip_stat.ip.fragerr); + UIP_LOG("ip: fragment dropped."); + goto drop; +#endif /* UIP_REASSEMBLY */ + } +#endif /* UIP_CONF_IPV6 */ + + if(uip_ipaddr_cmp(uip_hostaddr, all_zeroes_addr)) { + /* If we are configured to use ping IP address configuration and + hasn't been assigned an IP address yet, we accept all ICMP + packets. */ +#if UIP_PINGADDRCONF && !UIP_CONF_IPV6 + if(BUF->proto == UIP_PROTO_ICMP) { + UIP_LOG("ip: possible ping config packet received."); + goto icmp_input; + } else { + UIP_LOG("ip: packet dropped since no address assigned."); + goto drop; + } +#endif /* UIP_PINGADDRCONF */ + + } else { + /* If IP broadcast support is configured, we check for a broadcast + UDP packet, which may be destined to us. */ +#if UIP_BROADCAST + DEBUG_PRINTF("UDP IP checksum 0x%04x\n", uip_ipchksum()); + if(BUF->proto == UIP_PROTO_UDP && + uip_ipaddr_cmp(BUF->destipaddr, all_ones_addr) + /*&& + uip_ipchksum() == 0xffff*/) { + goto udp_input; + } +#endif /* UIP_BROADCAST */ + + /* Check if the packet is destined for our IP address. */ +#if !UIP_CONF_IPV6 + if(!uip_ipaddr_cmp(BUF->destipaddr, uip_hostaddr)) { + UIP_STAT(++uip_stat.ip.drop); + goto drop; + } +#else /* UIP_CONF_IPV6 */ + /* For IPv6, packet reception is a little trickier as we need to + make sure that we listen to certain multicast addresses (all + hosts multicast address, and the solicited-node multicast + address) as well. However, we will cheat here and accept all + multicast packets that are sent to the ff02::/16 addresses. */ + if(!uip_ipaddr_cmp(BUF->destipaddr, uip_hostaddr) && + BUF->destipaddr[0] != HTONS(0xff02)) { + UIP_STAT(++uip_stat.ip.drop); + goto drop; + } +#endif /* UIP_CONF_IPV6 */ + } + +#if !UIP_CONF_IPV6 + if(uip_ipchksum() != 0xffff) { /* Compute and check the IP header + checksum. */ + UIP_STAT(++uip_stat.ip.drop); + UIP_STAT(++uip_stat.ip.chkerr); + UIP_LOG("ip: bad checksum."); + goto drop; + } +#endif /* UIP_CONF_IPV6 */ + + if(BUF->proto == UIP_PROTO_TCP) { /* Check for TCP packet. If so, + proceed with TCP input + processing. */ + goto tcp_input; + } + +#if UIP_UDP + if(BUF->proto == UIP_PROTO_UDP) { + goto udp_input; + } +#endif /* UIP_UDP */ + +#if !UIP_CONF_IPV6 + /* ICMPv4 processing code follows. */ + if(BUF->proto != UIP_PROTO_ICMP) { /* We only allow ICMP packets from + here. */ + UIP_STAT(++uip_stat.ip.drop); + UIP_STAT(++uip_stat.ip.protoerr); + UIP_LOG("ip: neither tcp nor icmp."); + goto drop; + } + +#if UIP_PINGADDRCONF + icmp_input: +#endif /* UIP_PINGADDRCONF */ + UIP_STAT(++uip_stat.icmp.recv); + + /* ICMP echo (i.e., ping) processing. This is simple, we only change + the ICMP type from ECHO to ECHO_REPLY and adjust the ICMP + checksum before we return the packet. */ + if(ICMPBUF->type != ICMP_ECHO) { + UIP_STAT(++uip_stat.icmp.drop); + UIP_STAT(++uip_stat.icmp.typeerr); + UIP_LOG("icmp: not icmp echo."); + goto drop; + } + + /* If we are configured to use ping IP address assignment, we use + the destination IP address of this ping packet and assign it to + ourself. */ +#if UIP_PINGADDRCONF + if((uip_hostaddr[0] | uip_hostaddr[1]) == 0) { + uip_hostaddr[0] = BUF->destipaddr[0]; + uip_hostaddr[1] = BUF->destipaddr[1]; + } +#endif /* UIP_PINGADDRCONF */ + + ICMPBUF->type = ICMP_ECHO_REPLY; + + if(ICMPBUF->icmpchksum >= HTONS(0xffff - (ICMP_ECHO << 8))) { + ICMPBUF->icmpchksum += HTONS(ICMP_ECHO << 8) + 1; + } else { + ICMPBUF->icmpchksum += HTONS(ICMP_ECHO << 8); + } + + /* Swap IP addresses. */ + uip_ipaddr_copy(BUF->destipaddr, BUF->srcipaddr); + uip_ipaddr_copy(BUF->srcipaddr, uip_hostaddr); + + UIP_STAT(++uip_stat.icmp.sent); + goto send; + + /* End of IPv4 input header processing code. */ +#else /* !UIP_CONF_IPV6 */ + + /* This is IPv6 ICMPv6 processing code. */ + DEBUG_PRINTF("icmp6_input: length %d\n", uip_len); + + if(BUF->proto != UIP_PROTO_ICMP6) { /* We only allow ICMPv6 packets from + here. */ + UIP_STAT(++uip_stat.ip.drop); + UIP_STAT(++uip_stat.ip.protoerr); + UIP_LOG("ip: neither tcp nor icmp6."); + goto drop; + } + + UIP_STAT(++uip_stat.icmp.recv); + + /* If we get a neighbor solicitation for our address we should send + a neighbor advertisement message back. */ + if(ICMPBUF->type == ICMP6_NEIGHBOR_SOLICITATION) { + if(uip_ipaddr_cmp(ICMPBUF->icmp6data, uip_hostaddr)) { + + if(ICMPBUF->options[0] == ICMP6_OPTION_SOURCE_LINK_ADDRESS) { + /* Save the sender's address in our neighbor list. */ + uip_neighbor_add(ICMPBUF->srcipaddr, &(ICMPBUF->options[2])); + } + + /* We should now send a neighbor advertisement back to where the + neighbor solicication came from. */ + ICMPBUF->type = ICMP6_NEIGHBOR_ADVERTISEMENT; + ICMPBUF->flags = ICMP6_FLAG_S; /* Solicited flag. */ + + ICMPBUF->reserved1 = ICMPBUF->reserved2 = ICMPBUF->reserved3 = 0; + + uip_ipaddr_copy(ICMPBUF->destipaddr, ICMPBUF->srcipaddr); + uip_ipaddr_copy(ICMPBUF->srcipaddr, uip_hostaddr); + ICMPBUF->options[0] = ICMP6_OPTION_TARGET_LINK_ADDRESS; + ICMPBUF->options[1] = 1; /* Options length, 1 = 8 bytes. */ + memcpy(&(ICMPBUF->options[2]), &uip_ethaddr, sizeof(uip_ethaddr)); + ICMPBUF->icmpchksum = 0; + ICMPBUF->icmpchksum = ~uip_icmp6chksum(); + goto send; + + } + goto drop; + } else if(ICMPBUF->type == ICMP6_ECHO) { + /* ICMP echo (i.e., ping) processing. This is simple, we only + change the ICMP type from ECHO to ECHO_REPLY and update the + ICMP checksum before we return the packet. */ + + ICMPBUF->type = ICMP6_ECHO_REPLY; + + uip_ipaddr_copy(BUF->destipaddr, BUF->srcipaddr); + uip_ipaddr_copy(BUF->srcipaddr, uip_hostaddr); + ICMPBUF->icmpchksum = 0; + ICMPBUF->icmpchksum = ~uip_icmp6chksum(); + + UIP_STAT(++uip_stat.icmp.sent); + goto send; + } else { + DEBUG_PRINTF("Unknown icmp6 message type %d\n", ICMPBUF->type); + UIP_STAT(++uip_stat.icmp.drop); + UIP_STAT(++uip_stat.icmp.typeerr); + UIP_LOG("icmp: unknown ICMP message."); + goto drop; + } + + /* End of IPv6 ICMP processing. */ + +#endif /* !UIP_CONF_IPV6 */ + +#if UIP_UDP + /* UDP input processing. */ + udp_input: + /* UDP processing is really just a hack. We don't do anything to the + UDP/IP headers, but let the UDP application do all the hard + work. If the application sets uip_slen, it has a packet to + send. */ +#if UIP_UDP_CHECKSUMS + uip_len = uip_len - UIP_IPUDPH_LEN; + uip_appdata = &uip_buf[UIP_LLH_LEN + UIP_IPUDPH_LEN]; + if(UDPBUF->udpchksum != 0 && uip_udpchksum() != 0xffff) { + UIP_STAT(++uip_stat.udp.drop); + UIP_STAT(++uip_stat.udp.chkerr); + UIP_LOG("udp: bad checksum."); + goto drop; + } +#else /* UIP_UDP_CHECKSUMS */ + uip_len = uip_len - UIP_IPUDPH_LEN; +#endif /* UIP_UDP_CHECKSUMS */ + + /* Demultiplex this UDP packet between the UDP "connections". */ + for(uip_udp_conn = &uip_udp_conns[0]; + uip_udp_conn < &uip_udp_conns[UIP_UDP_CONNS]; + ++uip_udp_conn) { + /* If the local UDP port is non-zero, the connection is considered + to be used. If so, the local port number is checked against the + destination port number in the received packet. If the two port + numbers match, the remote port number is checked if the + connection is bound to a remote port. Finally, if the + connection is bound to a remote IP address, the source IP + address of the packet is checked. */ + if(uip_udp_conn->lport != 0 && + UDPBUF->destport == uip_udp_conn->lport && + (uip_udp_conn->rport == 0 || + UDPBUF->srcport == uip_udp_conn->rport) && + (uip_ipaddr_cmp(uip_udp_conn->ripaddr, all_zeroes_addr) || + uip_ipaddr_cmp(uip_udp_conn->ripaddr, all_ones_addr) || + uip_ipaddr_cmp(BUF->srcipaddr, uip_udp_conn->ripaddr))) { + goto udp_found; + } + } + UIP_LOG("udp: no matching connection found"); + goto drop; + + udp_found: + UIP_STAT(++uip_stat.udp.recv); + uip_conn = NULL; + uip_flags = UIP_NEWDATA; + uip_sappdata = uip_appdata = &uip_buf[UIP_LLH_LEN + UIP_IPUDPH_LEN]; + uip_slen = 0; + UIP_UDP_APPCALL(); + udp_send: + if(uip_slen == 0) { + goto drop; + } + uip_len = uip_slen + UIP_IPUDPH_LEN; + +#if UIP_CONF_IPV6 + /* For IPv6, the IP length field does not include the IPv6 IP header + length. */ + BUF->len[0] = ((uip_len - UIP_IPH_LEN) >> 8); + BUF->len[1] = ((uip_len - UIP_IPH_LEN) & 0xff); +#else /* UIP_CONF_IPV6 */ + BUF->len[0] = (uip_len >> 8); + BUF->len[1] = (uip_len & 0xff); +#endif /* UIP_CONF_IPV6 */ + + BUF->ttl = uip_udp_conn->ttl; + BUF->proto = UIP_PROTO_UDP; + + UDPBUF->udplen = HTONS(uip_slen + UIP_UDPH_LEN); + UDPBUF->udpchksum = 0; + + BUF->srcport = uip_udp_conn->lport; + BUF->destport = uip_udp_conn->rport; + + uip_ipaddr_copy(BUF->srcipaddr, uip_hostaddr); + uip_ipaddr_copy(BUF->destipaddr, uip_udp_conn->ripaddr); + + uip_appdata = &uip_buf[UIP_LLH_LEN + UIP_IPTCPH_LEN]; + +#if UIP_UDP_CHECKSUMS + /* Calculate UDP checksum. */ + UDPBUF->udpchksum = ~(uip_udpchksum()); + if(UDPBUF->udpchksum == 0) { + UDPBUF->udpchksum = 0xffff; + } +#endif /* UIP_UDP_CHECKSUMS */ + UIP_STAT(++uip_stat.udp.sent); + goto ip_send_nolen; +#endif /* UIP_UDP */ + + /* TCP input processing. */ + tcp_input: + UIP_STAT(++uip_stat.tcp.recv); + + /* Start of TCP input header processing code. */ + + if(uip_tcpchksum() != 0xffff) { /* Compute and check the TCP + checksum. */ + UIP_STAT(++uip_stat.tcp.drop); + UIP_STAT(++uip_stat.tcp.chkerr); + UIP_LOG("tcp: bad checksum."); + goto drop; + } + + + /* Demultiplex this segment. */ + /* First check any active connections. */ + for(uip_connr = &uip_conns[0]; uip_connr <= &uip_conns[UIP_CONNS - 1]; + ++uip_connr) { + if(uip_connr->tcpstateflags != UIP_CLOSED && + BUF->destport == uip_connr->lport && + BUF->srcport == uip_connr->rport && + uip_ipaddr_cmp(BUF->srcipaddr, uip_connr->ripaddr)) { + goto found; + } + } + + /* If we didn't find and active connection that expected the packet, + either this packet is an old duplicate, or this is a SYN packet + destined for a connection in LISTEN. If the SYN flag isn't set, + it is an old packet and we send a RST. */ + if((BUF->flags & TCP_CTL) != TCP_SYN) { + goto reset; + } + + tmp16 = BUF->destport; + /* Next, check listening connections. */ + for(c = 0; c < UIP_LISTENPORTS; ++c) { + if(tmp16 == uip_listenports[c]) + goto found_listen; + } + + /* No matching connection found, so we send a RST packet. */ + UIP_STAT(++uip_stat.tcp.synrst); + reset: + + /* We do not send resets in response to resets. */ + if(BUF->flags & TCP_RST) { + goto drop; + } + + UIP_STAT(++uip_stat.tcp.rst); + + BUF->flags = TCP_RST | TCP_ACK; + uip_len = UIP_IPTCPH_LEN; + BUF->tcpoffset = 5 << 4; + + /* Flip the seqno and ackno fields in the TCP header. */ + c = BUF->seqno[3]; + BUF->seqno[3] = BUF->ackno[3]; + BUF->ackno[3] = c; + + c = BUF->seqno[2]; + BUF->seqno[2] = BUF->ackno[2]; + BUF->ackno[2] = c; + + c = BUF->seqno[1]; + BUF->seqno[1] = BUF->ackno[1]; + BUF->ackno[1] = c; + + c = BUF->seqno[0]; + BUF->seqno[0] = BUF->ackno[0]; + BUF->ackno[0] = c; + + /* We also have to increase the sequence number we are + acknowledging. If the least significant byte overflowed, we need + to propagate the carry to the other bytes as well. */ + if(++BUF->ackno[3] == 0) { + if(++BUF->ackno[2] == 0) { + if(++BUF->ackno[1] == 0) { + ++BUF->ackno[0]; + } + } + } + + /* Swap port numbers. */ + tmp16 = BUF->srcport; + BUF->srcport = BUF->destport; + BUF->destport = tmp16; + + /* Swap IP addresses. */ + uip_ipaddr_copy(BUF->destipaddr, BUF->srcipaddr); + uip_ipaddr_copy(BUF->srcipaddr, uip_hostaddr); + + /* And send out the RST packet! */ + goto tcp_send_noconn; + + /* This label will be jumped to if we matched the incoming packet + with a connection in LISTEN. In that case, we should create a new + connection and send a SYNACK in return. */ + found_listen: + /* First we check if there are any connections avaliable. Unused + connections are kept in the same table as used connections, but + unused ones have the tcpstate set to CLOSED. Also, connections in + TIME_WAIT are kept track of and we'll use the oldest one if no + CLOSED connections are found. Thanks to Eddie C. Dost for a very + nice algorithm for the TIME_WAIT search. */ + uip_connr = 0; + for(c = 0; c < UIP_CONNS; ++c) { + if(uip_conns[c].tcpstateflags == UIP_CLOSED) { + uip_connr = &uip_conns[c]; + break; + } + if(uip_conns[c].tcpstateflags == UIP_TIME_WAIT) { + if(uip_connr == 0 || + uip_conns[c].timer > uip_connr->timer) { + uip_connr = &uip_conns[c]; + } + } + } + + if(uip_connr == 0) { + /* All connections are used already, we drop packet and hope that + the remote end will retransmit the packet at a time when we + have more spare connections. */ + UIP_STAT(++uip_stat.tcp.syndrop); + UIP_LOG("tcp: found no unused connections."); + goto drop; + } + uip_conn = uip_connr; + + /* Fill in the necessary fields for the new connection. */ + uip_connr->rto = uip_connr->timer = UIP_RTO; + uip_connr->sa = 0; + uip_connr->sv = 4; + uip_connr->nrtx = 0; + uip_connr->lport = BUF->destport; + uip_connr->rport = BUF->srcport; + uip_ipaddr_copy(uip_connr->ripaddr, BUF->srcipaddr); + uip_connr->tcpstateflags = UIP_SYN_RCVD; + + uip_connr->snd_nxt[0] = iss[0]; + uip_connr->snd_nxt[1] = iss[1]; + uip_connr->snd_nxt[2] = iss[2]; + uip_connr->snd_nxt[3] = iss[3]; + uip_connr->len = 1; + + /* rcv_nxt should be the seqno from the incoming packet + 1. */ + uip_connr->rcv_nxt[3] = BUF->seqno[3]; + uip_connr->rcv_nxt[2] = BUF->seqno[2]; + uip_connr->rcv_nxt[1] = BUF->seqno[1]; + uip_connr->rcv_nxt[0] = BUF->seqno[0]; + uip_add_rcv_nxt(1); + + /* Parse the TCP MSS option, if present. */ + if((BUF->tcpoffset & 0xf0) > 0x50) { + for(c = 0; c < ((BUF->tcpoffset >> 4) - 5) << 2 ;) { + opt = uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + c]; + if(opt == TCP_OPT_END) { + /* End of options. */ + break; + } else if(opt == TCP_OPT_NOOP) { + ++c; + /* NOP option. */ + } else if(opt == TCP_OPT_MSS && + uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == TCP_OPT_MSS_LEN) { + /* An MSS option with the right option length. */ + tmp16 = ((u16_t)uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 2 + c] << 8) | + (u16_t)uip_buf[UIP_IPTCPH_LEN + UIP_LLH_LEN + 3 + c]; + uip_connr->initialmss = uip_connr->mss = + tmp16 > UIP_TCP_MSS? UIP_TCP_MSS: tmp16; + + /* And we are done processing options. */ + break; + } else { + /* All other options have a length field, so that we easily + can skip past them. */ + if(uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0) { + /* If the length field is zero, the options are malformed + and we don't process them further. */ + break; + } + c += uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c]; + } + } + } + + /* Our response will be a SYNACK. */ +#if UIP_ACTIVE_OPEN + tcp_send_synack: + BUF->flags = TCP_ACK; + + tcp_send_syn: + BUF->flags |= TCP_SYN; +#else /* UIP_ACTIVE_OPEN */ + tcp_send_synack: + BUF->flags = TCP_SYN | TCP_ACK; +#endif /* UIP_ACTIVE_OPEN */ + + /* We send out the TCP Maximum Segment Size option with our + SYNACK. */ + BUF->optdata[0] = TCP_OPT_MSS; + BUF->optdata[1] = TCP_OPT_MSS_LEN; + BUF->optdata[2] = (UIP_TCP_MSS) / 256; + BUF->optdata[3] = (UIP_TCP_MSS) & 255; + uip_len = UIP_IPTCPH_LEN + TCP_OPT_MSS_LEN; + BUF->tcpoffset = ((UIP_TCPH_LEN + TCP_OPT_MSS_LEN) / 4) << 4; + goto tcp_send; + + /* This label will be jumped to if we found an active connection. */ + found: + uip_conn = uip_connr; + uip_flags = 0; + /* We do a very naive form of TCP reset processing; we just accept + any RST and kill our connection. We should in fact check if the + sequence number of this reset is wihtin our advertised window + before we accept the reset. */ + if(BUF->flags & TCP_RST) { + uip_connr->tcpstateflags = UIP_CLOSED; + UIP_LOG("tcp: got reset, aborting connection."); + uip_flags = UIP_ABORT; + UIP_APPCALL(); + goto drop; + } + /* Calculated the length of the data, if the application has sent + any data to us. */ + c = (BUF->tcpoffset >> 4) << 2; + /* uip_len will contain the length of the actual TCP data. This is + calculated by subtracing the length of the TCP header (in + c) and the length of the IP header (20 bytes). */ + uip_len = uip_len - c - UIP_IPH_LEN; + + /* First, check if the sequence number of the incoming packet is + what we're expecting next. If not, we send out an ACK with the + correct numbers in. */ + if(!(((uip_connr->tcpstateflags & UIP_TS_MASK) == UIP_SYN_SENT) && + ((BUF->flags & TCP_CTL) == (TCP_SYN | TCP_ACK)))) { + if((uip_len > 0 || ((BUF->flags & (TCP_SYN | TCP_FIN)) != 0)) && + (BUF->seqno[0] != uip_connr->rcv_nxt[0] || + BUF->seqno[1] != uip_connr->rcv_nxt[1] || + BUF->seqno[2] != uip_connr->rcv_nxt[2] || + BUF->seqno[3] != uip_connr->rcv_nxt[3])) { + goto tcp_send_ack; + } + } + + /* Next, check if the incoming segment acknowledges any outstanding + data. If so, we update the sequence number, reset the length of + the outstanding data, calculate RTT estimations, and reset the + retransmission timer. */ + if((BUF->flags & TCP_ACK) && uip_outstanding(uip_connr)) { + uip_add32(uip_connr->snd_nxt, uip_connr->len); + + if(BUF->ackno[0] == uip_acc32[0] && + BUF->ackno[1] == uip_acc32[1] && + BUF->ackno[2] == uip_acc32[2] && + BUF->ackno[3] == uip_acc32[3]) { + /* Update sequence number. */ + uip_connr->snd_nxt[0] = uip_acc32[0]; + uip_connr->snd_nxt[1] = uip_acc32[1]; + uip_connr->snd_nxt[2] = uip_acc32[2]; + uip_connr->snd_nxt[3] = uip_acc32[3]; + + + /* Do RTT estimation, unless we have done retransmissions. */ + if(uip_connr->nrtx == 0) { + signed char m; + m = uip_connr->rto - uip_connr->timer; + /* This is taken directly from VJs original code in his paper */ + m = m - (uip_connr->sa >> 3); + uip_connr->sa += m; + if(m < 0) { + m = -m; + } + m = m - (uip_connr->sv >> 2); + uip_connr->sv += m; + uip_connr->rto = (uip_connr->sa >> 3) + uip_connr->sv; + + } + /* Set the acknowledged flag. */ + uip_flags = UIP_ACKDATA; + /* Reset the retransmission timer. */ + uip_connr->timer = uip_connr->rto; + + /* Reset length of outstanding data. */ + uip_connr->len = 0; + } + + } + + /* Do different things depending on in what state the connection is. */ + switch(uip_connr->tcpstateflags & UIP_TS_MASK) { + /* CLOSED and LISTEN are not handled here. CLOSE_WAIT is not + implemented, since we force the application to close when the + peer sends a FIN (hence the application goes directly from + ESTABLISHED to LAST_ACK). */ + case UIP_SYN_RCVD: + /* In SYN_RCVD we have sent out a SYNACK in response to a SYN, and + we are waiting for an ACK that acknowledges the data we sent + out the last time. Therefore, we want to have the UIP_ACKDATA + flag set. If so, we enter the ESTABLISHED state. */ + if(uip_flags & UIP_ACKDATA) { + uip_connr->tcpstateflags = UIP_ESTABLISHED; + uip_flags = UIP_CONNECTED; + uip_connr->len = 0; + if(uip_len > 0) { + uip_flags |= UIP_NEWDATA; + uip_add_rcv_nxt(uip_len); + } + uip_slen = 0; + UIP_APPCALL(); + goto appsend; + } + goto drop; +#if UIP_ACTIVE_OPEN + case UIP_SYN_SENT: + /* In SYN_SENT, we wait for a SYNACK that is sent in response to + our SYN. The rcv_nxt is set to sequence number in the SYNACK + plus one, and we send an ACK. We move into the ESTABLISHED + state. */ + if((uip_flags & UIP_ACKDATA) && + (BUF->flags & TCP_CTL) == (TCP_SYN | TCP_ACK)) { + + /* Parse the TCP MSS option, if present. */ + if((BUF->tcpoffset & 0xf0) > 0x50) { + for(c = 0; c < ((BUF->tcpoffset >> 4) - 5) << 2 ;) { + opt = uip_buf[UIP_IPTCPH_LEN + UIP_LLH_LEN + c]; + if(opt == TCP_OPT_END) { + /* End of options. */ + break; + } else if(opt == TCP_OPT_NOOP) { + ++c; + /* NOP option. */ + } else if(opt == TCP_OPT_MSS && + uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == TCP_OPT_MSS_LEN) { + /* An MSS option with the right option length. */ + tmp16 = (uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 2 + c] << 8) | + uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 3 + c]; + uip_connr->initialmss = + uip_connr->mss = tmp16 > UIP_TCP_MSS? UIP_TCP_MSS: tmp16; + + /* And we are done processing options. */ + break; + } else { + /* All other options have a length field, so that we easily + can skip past them. */ + if(uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0) { + /* If the length field is zero, the options are malformed + and we don't process them further. */ + break; + } + c += uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c]; + } + } + } + uip_connr->tcpstateflags = UIP_ESTABLISHED; + uip_connr->rcv_nxt[0] = BUF->seqno[0]; + uip_connr->rcv_nxt[1] = BUF->seqno[1]; + uip_connr->rcv_nxt[2] = BUF->seqno[2]; + uip_connr->rcv_nxt[3] = BUF->seqno[3]; + uip_add_rcv_nxt(1); + uip_flags = UIP_CONNECTED | UIP_NEWDATA; + uip_connr->len = 0; + uip_len = 0; + uip_slen = 0; + UIP_APPCALL(); + goto appsend; + } + /* Inform the application that the connection failed */ + uip_flags = UIP_ABORT; + UIP_APPCALL(); + /* The connection is closed after we send the RST */ + uip_conn->tcpstateflags = UIP_CLOSED; + goto reset; +#endif /* UIP_ACTIVE_OPEN */ + + case UIP_ESTABLISHED: + /* In the ESTABLISHED state, we call upon the application to feed + data into the uip_buf. If the UIP_ACKDATA flag is set, the + application should put new data into the buffer, otherwise we are + retransmitting an old segment, and the application should put that + data into the buffer. + + If the incoming packet is a FIN, we should close the connection on + this side as well, and we send out a FIN and enter the LAST_ACK + state. We require that there is no outstanding data; otherwise the + sequence numbers will be screwed up. */ + + if(BUF->flags & TCP_FIN && !(uip_connr->tcpstateflags & UIP_STOPPED)) { + if(uip_outstanding(uip_connr)) { + goto drop; + } + uip_add_rcv_nxt(1 + uip_len); + uip_flags |= UIP_CLOSE; + if(uip_len > 0) { + uip_flags |= UIP_NEWDATA; + } + UIP_APPCALL(); + uip_connr->len = 1; + uip_connr->tcpstateflags = UIP_LAST_ACK; + uip_connr->nrtx = 0; + tcp_send_finack: + BUF->flags = TCP_FIN | TCP_ACK; + goto tcp_send_nodata; + } + + /* Check the URG flag. If this is set, the segment carries urgent + data that we must pass to the application. */ + if((BUF->flags & TCP_URG) != 0) { +#if UIP_URGDATA > 0 + uip_urglen = (BUF->urgp[0] << 8) | BUF->urgp[1]; + if(uip_urglen > uip_len) { + /* There is more urgent data in the next segment to come. */ + uip_urglen = uip_len; + } + uip_add_rcv_nxt(uip_urglen); + uip_len -= uip_urglen; + uip_urgdata = uip_appdata; + uip_appdata += uip_urglen; + } else { + uip_urglen = 0; +#else /* UIP_URGDATA > 0 */ + uip_appdata = ((char *)uip_appdata) + ((BUF->urgp[0] << 8) | BUF->urgp[1]); + uip_len -= (BUF->urgp[0] << 8) | BUF->urgp[1]; +#endif /* UIP_URGDATA > 0 */ + } + + /* If uip_len > 0 we have TCP data in the packet, and we flag this + by setting the UIP_NEWDATA flag and update the sequence number + we acknowledge. If the application has stopped the dataflow + using uip_stop(), we must not accept any data packets from the + remote host. */ + if(uip_len > 0 && !(uip_connr->tcpstateflags & UIP_STOPPED)) { + uip_flags |= UIP_NEWDATA; + uip_add_rcv_nxt(uip_len); + } + + /* Check if the available buffer space advertised by the other end + is smaller than the initial MSS for this connection. If so, we + set the current MSS to the window size to ensure that the + application does not send more data than the other end can + handle. + + If the remote host advertises a zero window, we set the MSS to + the initial MSS so that the application will send an entire MSS + of data. This data will not be acknowledged by the receiver, + and the application will retransmit it. This is called the + "persistent timer" and uses the retransmission mechanim. + */ + tmp16 = ((u16_t)BUF->wnd[0] << 8) + (u16_t)BUF->wnd[1]; + if(tmp16 > uip_connr->initialmss || + tmp16 == 0) { + tmp16 = uip_connr->initialmss; + } + uip_connr->mss = tmp16; + + /* If this packet constitutes an ACK for outstanding data (flagged + by the UIP_ACKDATA flag, we should call the application since it + might want to send more data. If the incoming packet had data + from the peer (as flagged by the UIP_NEWDATA flag), the + application must also be notified. + + When the application is called, the global variable uip_len + contains the length of the incoming data. The application can + access the incoming data through the global pointer + uip_appdata, which usually points UIP_IPTCPH_LEN + UIP_LLH_LEN + bytes into the uip_buf array. + + If the application wishes to send any data, this data should be + put into the uip_appdata and the length of the data should be + put into uip_len. If the application don't have any data to + send, uip_len must be set to 0. */ + if(uip_flags & (UIP_NEWDATA | UIP_ACKDATA)) { + uip_slen = 0; + UIP_APPCALL(); + + appsend: + + if(uip_flags & UIP_ABORT) { + uip_slen = 0; + uip_connr->tcpstateflags = UIP_CLOSED; + BUF->flags = TCP_RST | TCP_ACK; + goto tcp_send_nodata; + } + + if(uip_flags & UIP_CLOSE) { + uip_slen = 0; + uip_connr->len = 1; + uip_connr->tcpstateflags = UIP_FIN_WAIT_1; + uip_connr->nrtx = 0; + BUF->flags = TCP_FIN | TCP_ACK; + goto tcp_send_nodata; + } + + /* If uip_slen > 0, the application has data to be sent. */ + if(uip_slen > 0) { + + /* If the connection has acknowledged data, the contents of + the ->len variable should be discarded. */ + if((uip_flags & UIP_ACKDATA) != 0) { + uip_connr->len = 0; + } + + /* If the ->len variable is non-zero the connection has + already data in transit and cannot send anymore right + now. */ + if(uip_connr->len == 0) { + + /* The application cannot send more than what is allowed by + the mss (the minumum of the MSS and the available + window). */ + if(uip_slen > uip_connr->mss) { + uip_slen = uip_connr->mss; + } + + /* Remember how much data we send out now so that we know + when everything has been acknowledged. */ + uip_connr->len = uip_slen; + } else { + + /* If the application already had unacknowledged data, we + make sure that the application does not send (i.e., + retransmit) out more than it previously sent out. */ + uip_slen = uip_connr->len; + } + } + uip_connr->nrtx = 0; + apprexmit: + uip_appdata = uip_sappdata; + + /* If the application has data to be sent, or if the incoming + packet had new data in it, we must send out a packet. */ + if(uip_slen > 0 && uip_connr->len > 0) { + /* Add the length of the IP and TCP headers. */ + uip_len = uip_connr->len + UIP_TCPIP_HLEN; + /* We always set the ACK flag in response packets. */ + BUF->flags = TCP_ACK | TCP_PSH; + /* Send the packet. */ + goto tcp_send_noopts; + } + /* If there is no data to send, just send out a pure ACK if + there is newdata. */ + if(uip_flags & UIP_NEWDATA) { + uip_len = UIP_TCPIP_HLEN; + BUF->flags = TCP_ACK; + goto tcp_send_noopts; + } + } + goto drop; + case UIP_LAST_ACK: + /* We can close this connection if the peer has acknowledged our + FIN. This is indicated by the UIP_ACKDATA flag. */ + if(uip_flags & UIP_ACKDATA) { + uip_connr->tcpstateflags = UIP_CLOSED; + uip_flags = UIP_CLOSE; + UIP_APPCALL(); + } + break; + + case UIP_FIN_WAIT_1: + /* The application has closed the connection, but the remote host + hasn't closed its end yet. Thus we do nothing but wait for a + FIN from the other side. */ + if(uip_len > 0) { + uip_add_rcv_nxt(uip_len); + } + if(BUF->flags & TCP_FIN) { + if(uip_flags & UIP_ACKDATA) { + uip_connr->tcpstateflags = UIP_TIME_WAIT; + uip_connr->timer = 0; + uip_connr->len = 0; + } else { + uip_connr->tcpstateflags = UIP_CLOSING; + } + uip_add_rcv_nxt(1); + uip_flags = UIP_CLOSE; + UIP_APPCALL(); + goto tcp_send_ack; + } else if(uip_flags & UIP_ACKDATA) { + uip_connr->tcpstateflags = UIP_FIN_WAIT_2; + uip_connr->len = 0; + goto drop; + } + if(uip_len > 0) { + goto tcp_send_ack; + } + goto drop; + + case UIP_FIN_WAIT_2: + if(uip_len > 0) { + uip_add_rcv_nxt(uip_len); + } + if(BUF->flags & TCP_FIN) { + uip_connr->tcpstateflags = UIP_TIME_WAIT; + uip_connr->timer = 0; + uip_add_rcv_nxt(1); + uip_flags = UIP_CLOSE; + UIP_APPCALL(); + goto tcp_send_ack; + } + if(uip_len > 0) { + goto tcp_send_ack; + } + goto drop; + + case UIP_TIME_WAIT: + goto tcp_send_ack; + + case UIP_CLOSING: + if(uip_flags & UIP_ACKDATA) { + uip_connr->tcpstateflags = UIP_TIME_WAIT; + uip_connr->timer = 0; + } + } + goto drop; + + + /* We jump here when we are ready to send the packet, and just want + to set the appropriate TCP sequence numbers in the TCP header. */ + tcp_send_ack: + BUF->flags = TCP_ACK; + tcp_send_nodata: + uip_len = UIP_IPTCPH_LEN; + tcp_send_noopts: + BUF->tcpoffset = (UIP_TCPH_LEN / 4) << 4; + tcp_send: + /* We're done with the input processing. We are now ready to send a + reply. Our job is to fill in all the fields of the TCP and IP + headers before calculating the checksum and finally send the + packet. */ + BUF->ackno[0] = uip_connr->rcv_nxt[0]; + BUF->ackno[1] = uip_connr->rcv_nxt[1]; + BUF->ackno[2] = uip_connr->rcv_nxt[2]; + BUF->ackno[3] = uip_connr->rcv_nxt[3]; + + BUF->seqno[0] = uip_connr->snd_nxt[0]; + BUF->seqno[1] = uip_connr->snd_nxt[1]; + BUF->seqno[2] = uip_connr->snd_nxt[2]; + BUF->seqno[3] = uip_connr->snd_nxt[3]; + + BUF->proto = UIP_PROTO_TCP; + + BUF->srcport = uip_connr->lport; + BUF->destport = uip_connr->rport; + + uip_ipaddr_copy(BUF->srcipaddr, uip_hostaddr); + uip_ipaddr_copy(BUF->destipaddr, uip_connr->ripaddr); + + if(uip_connr->tcpstateflags & UIP_STOPPED) { + /* If the connection has issued uip_stop(), we advertise a zero + window so that the remote host will stop sending data. */ + BUF->wnd[0] = BUF->wnd[1] = 0; + } else { + BUF->wnd[0] = ((UIP_RECEIVE_WINDOW) >> 8); + BUF->wnd[1] = ((UIP_RECEIVE_WINDOW) & 0xff); + } + + tcp_send_noconn: + BUF->ttl = UIP_TTL; +#if UIP_CONF_IPV6 + /* For IPv6, the IP length field does not include the IPv6 IP header + length. */ + BUF->len[0] = ((uip_len - UIP_IPH_LEN) >> 8); + BUF->len[1] = ((uip_len - UIP_IPH_LEN) & 0xff); +#else /* UIP_CONF_IPV6 */ + BUF->len[0] = (uip_len >> 8); + BUF->len[1] = (uip_len & 0xff); +#endif /* UIP_CONF_IPV6 */ + + BUF->urgp[0] = BUF->urgp[1] = 0; + + /* Calculate TCP checksum. */ + BUF->tcpchksum = 0; + BUF->tcpchksum = ~(uip_tcpchksum()); + + ip_send_nolen: + +#if UIP_CONF_IPV6 + BUF->vtc = 0x60; + BUF->tcflow = 0x00; + BUF->flow = 0x00; +#else /* UIP_CONF_IPV6 */ + BUF->vhl = 0x45; + BUF->tos = 0; + BUF->ipoffset[0] = BUF->ipoffset[1] = 0; + ++ipid; + BUF->ipid[0] = ipid >> 8; + BUF->ipid[1] = ipid & 0xff; + /* Calculate IP checksum. */ + BUF->ipchksum = 0; + BUF->ipchksum = ~(uip_ipchksum()); + DEBUG_PRINTF("uip ip_send_nolen: chkecum 0x%04x\n", uip_ipchksum()); +#endif /* UIP_CONF_IPV6 */ + + UIP_STAT(++uip_stat.tcp.sent); + send: + DEBUG_PRINTF("Sending packet with length %d (%d)\n", uip_len, + (BUF->len[0] << 8) | BUF->len[1]); + + UIP_STAT(++uip_stat.ip.sent); + /* Return and let the caller do the actual transmission. */ + uip_flags = 0; + return; + drop: + uip_len = 0; + uip_flags = 0; + return; +} +/*---------------------------------------------------------------------------*/ +u16_t +htons(u16_t val) +{ + return HTONS(val); +} +/*---------------------------------------------------------------------------*/ +void +uip_send(const void *data, int len) +{ + if(len > 0) { + uip_slen = len; + if(data != uip_sappdata) { + memcpy(uip_sappdata, (data), uip_slen); + } + } +} +/** @} */ diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/uip.h b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/uip.h new file mode 100644 index 000000000..82da6fbd2 --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/uip.h @@ -0,0 +1,1638 @@ + +/** + * \addtogroup uip + * @{ + */ + +/** + * \file + * Header file for the uIP TCP/IP stack. + * \author Adam Dunkels + * + * The uIP TCP/IP stack header file contains definitions for a number + * of C macros that are used by uIP programs as well as internal uIP + * structures, TCP/IP header structures and function declarations. + * + */ + + +/* + * Copyright (c) 2001-2003, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: uip.h,v 1.40 2006/06/08 07:12:07 adam Exp $ + * + */ + +#ifndef __UIP_H__ +#define __UIP_H__ + +#include "uipopt.h" + +/** + * Repressentation of an IP address. + * + */ +typedef u16_t uip_ip4addr_t[2]; +typedef u16_t uip_ip6addr_t[8]; +#if UIP_CONF_IPV6 +typedef uip_ip6addr_t uip_ipaddr_t; +#else /* UIP_CONF_IPV6 */ +typedef uip_ip4addr_t uip_ipaddr_t; +#endif /* UIP_CONF_IPV6 */ + +/*---------------------------------------------------------------------------*/ +/* First, the functions that should be called from the + * system. Initialization, the periodic timer and incoming packets are + * handled by the following three functions. + */ + +/** + * \defgroup uipconffunc uIP configuration functions + * @{ + * + * The uIP configuration functions are used for setting run-time + * parameters in uIP such as IP addresses. + */ + +/** + * Set the IP address of this host. + * + * The IP address is represented as a 4-byte array where the first + * octet of the IP address is put in the first member of the 4-byte + * array. + * + * Example: + \code + + uip_ipaddr_t addr; + + uip_ipaddr(&addr, 192,168,1,2); + uip_sethostaddr(&addr); + + \endcode + * \param addr A pointer to an IP address of type uip_ipaddr_t; + * + * \sa uip_ipaddr() + * + * \hideinitializer + */ +#define uip_sethostaddr(addr) uip_ipaddr_copy(uip_hostaddr, (addr)) + +/** + * Get the IP address of this host. + * + * The IP address is represented as a 4-byte array where the first + * octet of the IP address is put in the first member of the 4-byte + * array. + * + * Example: + \code + uip_ipaddr_t hostaddr; + + uip_gethostaddr(&hostaddr); + \endcode + * \param addr A pointer to a uip_ipaddr_t variable that will be + * filled in with the currently configured IP address. + * + * \hideinitializer + */ +#define uip_gethostaddr(addr) uip_ipaddr_copy((addr), uip_hostaddr) + +/** + * Set the default router's IP address. + * + * \param addr A pointer to a uip_ipaddr_t variable containing the IP + * address of the default router. + * + * \sa uip_ipaddr() + * + * \hideinitializer + */ +#define uip_setdraddr(addr) uip_ipaddr_copy(uip_draddr, (addr)) + +/** + * Set the netmask. + * + * \param addr A pointer to a uip_ipaddr_t variable containing the IP + * address of the netmask. + * + * \sa uip_ipaddr() + * + * \hideinitializer + */ +#define uip_setnetmask(addr) uip_ipaddr_copy(uip_netmask, (addr)) + + +/** + * Get the default router's IP address. + * + * \param addr A pointer to a uip_ipaddr_t variable that will be + * filled in with the IP address of the default router. + * + * \hideinitializer + */ +#define uip_getdraddr(addr) uip_ipaddr_copy((addr), uip_draddr) + +/** + * Get the netmask. + * + * \param addr A pointer to a uip_ipaddr_t variable that will be + * filled in with the value of the netmask. + * + * \hideinitializer + */ +#define uip_getnetmask(addr) uip_ipaddr_copy((addr), uip_netmask) + +/** @} */ + +/** + * \defgroup uipinit uIP initialization functions + * @{ + * + * The uIP initialization functions are used for booting uIP. + */ + +/** + * uIP initialization function. + * + * This function should be called at boot up to initilize the uIP + * TCP/IP stack. + */ +void uip_init(void); + +/** + * uIP initialization function. + * + * This function may be used at boot time to set the initial ip_id. + */ +void uip_setipid(u16_t id); + +/** @} */ + +/** + * \defgroup uipdevfunc uIP device driver functions + * @{ + * + * These functions are used by a network device driver for interacting + * with uIP. + */ + +/** + * Process an incoming packet. + * + * This function should be called when the device driver has received + * a packet from the network. The packet from the device driver must + * be present in the uip_buf buffer, and the length of the packet + * should be placed in the uip_len variable. + * + * When the function returns, there may be an outbound packet placed + * in the uip_buf packet buffer. If so, the uip_len variable is set to + * the length of the packet. If no packet is to be sent out, the + * uip_len variable is set to 0. + * + * The usual way of calling the function is presented by the source + * code below. + \code + uip_len = devicedriver_poll(); + if(uip_len > 0) { + uip_input(); + if(uip_len > 0) { + devicedriver_send(); + } + } + \endcode + * + * \note If you are writing a uIP device driver that needs ARP + * (Address Resolution Protocol), e.g., when running uIP over + * Ethernet, you will need to call the uIP ARP code before calling + * this function: + \code + #define BUF ((struct uip_eth_hdr *)&uip_buf[0]) + uip_len = ethernet_devicedrver_poll(); + if(uip_len > 0) { + if(BUF->type == HTONS(UIP_ETHTYPE_IP)) { + uip_arp_ipin(); + uip_input(); + if(uip_len > 0) { + uip_arp_out(); + ethernet_devicedriver_send(); + } + } else if(BUF->type == HTONS(UIP_ETHTYPE_ARP)) { + uip_arp_arpin(); + if(uip_len > 0) { + ethernet_devicedriver_send(); + } + } + \endcode + * + * \hideinitializer + */ +#define uip_input() uip_process(UIP_DATA) + +/** + * Periodic processing for a connection identified by its number. + * + * This function does the necessary periodic processing (timers, + * polling) for a uIP TCP conneciton, and should be called when the + * periodic uIP timer goes off. It should be called for every + * connection, regardless of whether they are open of closed. + * + * When the function returns, it may have an outbound packet waiting + * for service in the uIP packet buffer, and if so the uip_len + * variable is set to a value larger than zero. The device driver + * should be called to send out the packet. + * + * The ususal way of calling the function is through a for() loop like + * this: + \code + for(i = 0; i < UIP_CONNS; ++i) { + uip_periodic(i); + if(uip_len > 0) { + devicedriver_send(); + } + } + \endcode + * + * \note If you are writing a uIP device driver that needs ARP + * (Address Resolution Protocol), e.g., when running uIP over + * Ethernet, you will need to call the uip_arp_out() function before + * calling the device driver: + \code + for(i = 0; i < UIP_CONNS; ++i) { + uip_periodic(i); + if(uip_len > 0) { + uip_arp_out(); + ethernet_devicedriver_send(); + } + } + \endcode + * + * \param conn The number of the connection which is to be periodically polled. + * + * \hideinitializer + */ +#define uip_periodic(conn) do { uip_conn = &uip_conns[conn]; \ + uip_process(UIP_TIMER); } while (0) + +/** + * + * + */ +#define uip_conn_active(conn) (uip_conns[conn].tcpstateflags != UIP_CLOSED) + +/** + * Perform periodic processing for a connection identified by a pointer + * to its structure. + * + * Same as uip_periodic() but takes a pointer to the actual uip_conn + * struct instead of an integer as its argument. This function can be + * used to force periodic processing of a specific connection. + * + * \param conn A pointer to the uip_conn struct for the connection to + * be processed. + * + * \hideinitializer + */ +#define uip_periodic_conn(conn) do { uip_conn = conn; \ + uip_process(UIP_TIMER); } while (0) + +/** + * Reuqest that a particular connection should be polled. + * + * Similar to uip_periodic_conn() but does not perform any timer + * processing. The application is polled for new data. + * + * \param conn A pointer to the uip_conn struct for the connection to + * be processed. + * + * \hideinitializer + */ +#define uip_poll_conn(conn) do { uip_conn = conn; \ + uip_process(UIP_POLL_REQUEST); } while (0) + + +#if UIP_UDP +/** + * Periodic processing for a UDP connection identified by its number. + * + * This function is essentially the same as uip_periodic(), but for + * UDP connections. It is called in a similar fashion as the + * uip_periodic() function: + \code + for(i = 0; i < UIP_UDP_CONNS; i++) { + uip_udp_periodic(i); + if(uip_len > 0) { + devicedriver_send(); + } + } + \endcode + * + * \note As for the uip_periodic() function, special care has to be + * taken when using uIP together with ARP and Ethernet: + \code + for(i = 0; i < UIP_UDP_CONNS; i++) { + uip_udp_periodic(i); + if(uip_len > 0) { + uip_arp_out(); + ethernet_devicedriver_send(); + } + } + \endcode + * + * \param conn The number of the UDP connection to be processed. + * + * \hideinitializer + */ +#define uip_udp_periodic(conn) do { uip_udp_conn = &uip_udp_conns[conn]; \ + uip_process(UIP_UDP_TIMER); } while (0) + +/** + * Periodic processing for a UDP connection identified by a pointer to + * its structure. + * + * Same as uip_udp_periodic() but takes a pointer to the actual + * uip_conn struct instead of an integer as its argument. This + * function can be used to force periodic processing of a specific + * connection. + * + * \param conn A pointer to the uip_udp_conn struct for the connection + * to be processed. + * + * \hideinitializer + */ +#define uip_udp_periodic_conn(conn) do { uip_udp_conn = conn; \ + uip_process(UIP_UDP_TIMER); } while (0) + + +#endif /* UIP_UDP */ + +/** + * The uIP packet buffer. + * + * The uip_buf array is used to hold incoming and outgoing + * packets. The device driver should place incoming data into this + * buffer. When sending data, the device driver should read the link + * level headers and the TCP/IP headers from this buffer. The size of + * the link level headers is configured by the UIP_LLH_LEN define. + * + * \note The application data need not be placed in this buffer, so + * the device driver must read it from the place pointed to by the + * uip_appdata pointer as illustrated by the following example: + \code + void + devicedriver_send(void) + { + hwsend(&uip_buf[0], UIP_LLH_LEN); + if(uip_len <= UIP_LLH_LEN + UIP_TCPIP_HLEN) { + hwsend(&uip_buf[UIP_LLH_LEN], uip_len - UIP_LLH_LEN); + } else { + hwsend(&uip_buf[UIP_LLH_LEN], UIP_TCPIP_HLEN); + hwsend(uip_appdata, uip_len - UIP_TCPIP_HLEN - UIP_LLH_LEN); + } + } + \endcode + */ +#ifndef UIP_CONF_EXTERNAL_BUFFER + extern u8_t uip_buf[UIP_BUFSIZE+2]; +#else + extern unsigned char *uip_buf; +#endif + +/** @} */ + +/*---------------------------------------------------------------------------*/ +/* Functions that are used by the uIP application program. Opening and + * closing connections, sending and receiving data, etc. is all + * handled by the functions below. +*/ +/** + * \defgroup uipappfunc uIP application functions + * @{ + * + * Functions used by an application running of top of uIP. + */ + +/** + * Start listening to the specified port. + * + * \note Since this function expects the port number in network byte + * order, a conversion using HTONS() or htons() is necessary. + * + \code + uip_listen(HTONS(80)); + \endcode + * + * \param port A 16-bit port number in network byte order. + */ +void uip_listen(u16_t port); + +/** + * Stop listening to the specified port. + * + * \note Since this function expects the port number in network byte + * order, a conversion using HTONS() or htons() is necessary. + * + \code + uip_unlisten(HTONS(80)); + \endcode + * + * \param port A 16-bit port number in network byte order. + */ +void uip_unlisten(u16_t port); + +/** + * Connect to a remote host using TCP. + * + * This function is used to start a new connection to the specified + * port on the specied host. It allocates a new connection identifier, + * sets the connection to the SYN_SENT state and sets the + * retransmission timer to 0. This will cause a TCP SYN segment to be + * sent out the next time this connection is periodically processed, + * which usually is done within 0.5 seconds after the call to + * uip_connect(). + * + * \note This function is avaliable only if support for active open + * has been configured by defining UIP_ACTIVE_OPEN to 1 in uipopt.h. + * + * \note Since this function requires the port number to be in network + * byte order, a conversion using HTONS() or htons() is necessary. + * + \code + uip_ipaddr_t ipaddr; + + uip_ipaddr(&ipaddr, 192,168,1,2); + uip_connect(&ipaddr, HTONS(80)); + \endcode + * + * \param ripaddr The IP address of the remote hot. + * + * \param port A 16-bit port number in network byte order. + * + * \return A pointer to the uIP connection identifier for the new connection, + * or NULL if no connection could be allocated. + * + */ +struct uip_conn *uip_connect(uip_ipaddr_t *ripaddr, u16_t port); + + + +/** + * \internal + * + * Check if a connection has outstanding (i.e., unacknowledged) data. + * + * \param conn A pointer to the uip_conn structure for the connection. + * + * \hideinitializer + */ +#define uip_outstanding(conn) ((conn)->len) + +/** + * Send data on the current connection. + * + * This function is used to send out a single segment of TCP + * data. Only applications that have been invoked by uIP for event + * processing can send data. + * + * The amount of data that actually is sent out after a call to this + * funcion is determined by the maximum amount of data TCP allows. uIP + * will automatically crop the data so that only the appropriate + * amount of data is sent. The function uip_mss() can be used to query + * uIP for the amount of data that actually will be sent. + * + * \note This function does not guarantee that the sent data will + * arrive at the destination. If the data is lost in the network, the + * application will be invoked with the uip_rexmit() event being + * set. The application will then have to resend the data using this + * function. + * + * \param data A pointer to the data which is to be sent. + * + * \param len The maximum amount of data bytes to be sent. + * + * \hideinitializer + */ +void uip_send(const void *data, int len); + +/** + * The length of any incoming data that is currently avaliable (if avaliable) + * in the uip_appdata buffer. + * + * The test function uip_data() must first be used to check if there + * is any data available at all. + * + * \hideinitializer + */ +/*void uip_datalen(void);*/ +#define uip_datalen() uip_len + +/** + * The length of any out-of-band data (urgent data) that has arrived + * on the connection. + * + * \note The configuration parameter UIP_URGDATA must be set for this + * function to be enabled. + * + * \hideinitializer + */ +#define uip_urgdatalen() uip_urglen + +/** + * Close the current connection. + * + * This function will close the current connection in a nice way. + * + * \hideinitializer + */ +#define uip_close() (uip_flags = UIP_CLOSE) + +/** + * Abort the current connection. + * + * This function will abort (reset) the current connection, and is + * usually used when an error has occured that prevents using the + * uip_close() function. + * + * \hideinitializer + */ +#define uip_abort() (uip_flags = UIP_ABORT) + +/** + * Tell the sending host to stop sending data. + * + * This function will close our receiver's window so that we stop + * receiving data for the current connection. + * + * \hideinitializer + */ +#define uip_stop() (uip_conn->tcpstateflags |= UIP_STOPPED) + +/** + * Find out if the current connection has been previously stopped with + * uip_stop(). + * + * \hideinitializer + */ +#define uip_stopped(conn) ((conn)->tcpstateflags & UIP_STOPPED) + +/** + * Restart the current connection, if is has previously been stopped + * with uip_stop(). + * + * This function will open the receiver's window again so that we + * start receiving data for the current connection. + * + * \hideinitializer + */ +#define uip_restart() do { uip_flags |= UIP_NEWDATA; \ + uip_conn->tcpstateflags &= ~UIP_STOPPED; \ + } while(0) + + +/* uIP tests that can be made to determine in what state the current + connection is, and what the application function should do. */ + +/** + * Is the current connection a UDP connection? + * + * This function checks whether the current connection is a UDP connection. + * + * \hideinitializer + * + */ +#define uip_udpconnection() (uip_conn == NULL) + +/** + * Is new incoming data available? + * + * Will reduce to non-zero if there is new data for the application + * present at the uip_appdata pointer. The size of the data is + * avaliable through the uip_len variable. + * + * \hideinitializer + */ +#define uip_newdata() (uip_flags & UIP_NEWDATA) + +/** + * Has previously sent data been acknowledged? + * + * Will reduce to non-zero if the previously sent data has been + * acknowledged by the remote host. This means that the application + * can send new data. + * + * \hideinitializer + */ +#define uip_acked() (uip_flags & UIP_ACKDATA) + +/** + * Has the connection just been connected? + * + * Reduces to non-zero if the current connection has been connected to + * a remote host. This will happen both if the connection has been + * actively opened (with uip_connect()) or passively opened (with + * uip_listen()). + * + * \hideinitializer + */ +#define uip_connected() (uip_flags & UIP_CONNECTED) + +/** + * Has the connection been closed by the other end? + * + * Is non-zero if the connection has been closed by the remote + * host. The application may then do the necessary clean-ups. + * + * \hideinitializer + */ +#define uip_closed() (uip_flags & UIP_CLOSE) + +/** + * Has the connection been aborted by the other end? + * + * Non-zero if the current connection has been aborted (reset) by the + * remote host. + * + * \hideinitializer + */ +#define uip_aborted() (uip_flags & UIP_ABORT) + +/** + * Has the connection timed out? + * + * Non-zero if the current connection has been aborted due to too many + * retransmissions. + * + * \hideinitializer + */ +#define uip_timedout() (uip_flags & UIP_TIMEDOUT) + +/** + * Do we need to retransmit previously data? + * + * Reduces to non-zero if the previously sent data has been lost in + * the network, and the application should retransmit it. The + * application should send the exact same data as it did the last + * time, using the uip_send() function. + * + * \hideinitializer + */ +#define uip_rexmit() (uip_flags & UIP_REXMIT) + +/** + * Is the connection being polled by uIP? + * + * Is non-zero if the reason the application is invoked is that the + * current connection has been idle for a while and should be + * polled. + * + * The polling event can be used for sending data without having to + * wait for the remote host to send data. + * + * \hideinitializer + */ +#define uip_poll() (uip_flags & UIP_POLL) + +/** + * Get the initial maxium segment size (MSS) of the current + * connection. + * + * \hideinitializer + */ +#define uip_initialmss() (uip_conn->initialmss) + +/** + * Get the current maxium segment size that can be sent on the current + * connection. + * + * The current maxiumum segment size that can be sent on the + * connection is computed from the receiver's window and the MSS of + * the connection (which also is available by calling + * uip_initialmss()). + * + * \hideinitializer + */ +#define uip_mss() (uip_conn->mss) + +/** + * Set up a new UDP connection. + * + * This function sets up a new UDP connection. The function will + * automatically allocate an unused local port for the new + * connection. However, another port can be chosen by using the + * uip_udp_bind() call, after the uip_udp_new() function has been + * called. + * + * Example: + \code + uip_ipaddr_t addr; + struct uip_udp_conn *c; + + uip_ipaddr(&addr, 192,168,2,1); + c = uip_udp_new(&addr, HTONS(12345)); + if(c != NULL) { + uip_udp_bind(c, HTONS(12344)); + } + \endcode + * \param ripaddr The IP address of the remote host. + * + * \param rport The remote port number in network byte order. + * + * \return The uip_udp_conn structure for the new connection or NULL + * if no connection could be allocated. + */ +struct uip_udp_conn *uip_udp_new(uip_ipaddr_t *ripaddr, u16_t rport); + +/** + * Removed a UDP connection. + * + * \param conn A pointer to the uip_udp_conn structure for the connection. + * + * \hideinitializer + */ +#define uip_udp_remove(conn) (conn)->lport = 0 + +/** + * Bind a UDP connection to a local port. + * + * \param conn A pointer to the uip_udp_conn structure for the + * connection. + * + * \param port The local port number, in network byte order. + * + * \hideinitializer + */ +#define uip_udp_bind(conn, port) (conn)->lport = port + +/** + * Send a UDP datagram of length len on the current connection. + * + * This function can only be called in response to a UDP event (poll + * or newdata). The data must be present in the uip_buf buffer, at the + * place pointed to by the uip_appdata pointer. + * + * \param len The length of the data in the uip_buf buffer. + * + * \hideinitializer + */ +#define uip_udp_send(len) uip_send((char *)uip_appdata, len) + +/** @} */ + +/* uIP convenience and converting functions. */ + +/** + * \defgroup uipconvfunc uIP conversion functions + * @{ + * + * These functions can be used for converting between different data + * formats used by uIP. + */ + +/** + * Construct an IP address from four bytes. + * + * This function constructs an IP address of the type that uIP handles + * internally from four bytes. The function is handy for specifying IP + * addresses to use with e.g. the uip_connect() function. + * + * Example: + \code + uip_ipaddr_t ipaddr; + struct uip_conn *c; + + uip_ipaddr(&ipaddr, 192,168,1,2); + c = uip_connect(&ipaddr, HTONS(80)); + \endcode + * + * \param addr A pointer to a uip_ipaddr_t variable that will be + * filled in with the IP address. + * + * \param addr0 The first octet of the IP address. + * \param addr1 The second octet of the IP address. + * \param addr2 The third octet of the IP address. + * \param addr3 The forth octet of the IP address. + * + * \hideinitializer + */ +#define uip_ipaddr(addr, addr0,addr1,addr2,addr3) do { \ + ((u16_t *)(addr))[0] = HTONS(((addr0) << 8) | (addr1)); \ + ((u16_t *)(addr))[1] = HTONS(((addr2) << 8) | (addr3)); \ + } while(0) + +/** + * Construct an IPv6 address from eight 16-bit words. + * + * This function constructs an IPv6 address. + * + * \hideinitializer + */ +#define uip_ip6addr(addr, addr0,addr1,addr2,addr3,addr4,addr5,addr6,addr7) do { \ + ((u16_t *)(addr))[0] = HTONS((addr0)); \ + ((u16_t *)(addr))[1] = HTONS((addr1)); \ + ((u16_t *)(addr))[2] = HTONS((addr2)); \ + ((u16_t *)(addr))[3] = HTONS((addr3)); \ + ((u16_t *)(addr))[4] = HTONS((addr4)); \ + ((u16_t *)(addr))[5] = HTONS((addr5)); \ + ((u16_t *)(addr))[6] = HTONS((addr6)); \ + ((u16_t *)(addr))[7] = HTONS((addr7)); \ + } while(0) + +/** + * Copy an IP address to another IP address. + * + * Copies an IP address from one place to another. + * + * Example: + \code + uip_ipaddr_t ipaddr1, ipaddr2; + + uip_ipaddr(&ipaddr1, 192,16,1,2); + uip_ipaddr_copy(&ipaddr2, &ipaddr1); + \endcode + * + * \param dest The destination for the copy. + * \param src The source from where to copy. + * + * \hideinitializer + */ +#if !UIP_CONF_IPV6 +#define uip_ipaddr_copy(dest, src) do { \ + ((u16_t *)dest)[0] = ((u16_t *)src)[0]; \ + ((u16_t *)dest)[1] = ((u16_t *)src)[1]; \ + } while(0) +#else /* !UIP_CONF_IPV6 */ +#define uip_ipaddr_copy(dest, src) memcpy(dest, src, sizeof(uip_ip6addr_t)) +#endif /* !UIP_CONF_IPV6 */ + +/** + * Compare two IP addresses + * + * Compares two IP addresses. + * + * Example: + \code + uip_ipaddr_t ipaddr1, ipaddr2; + + uip_ipaddr(&ipaddr1, 192,16,1,2); + if(uip_ipaddr_cmp(&ipaddr2, &ipaddr1)) { + printf("They are the same"); + } + \endcode + * + * \param addr1 The first IP address. + * \param addr2 The second IP address. + * + * \hideinitializer + */ +#if !UIP_CONF_IPV6 +#define uip_ipaddr_cmp(addr1, addr2) (((u16_t *)addr1)[0] == ((u16_t *)addr2)[0] && \ + ((u16_t *)addr1)[1] == ((u16_t *)addr2)[1]) +#else /* !UIP_CONF_IPV6 */ +#define uip_ipaddr_cmp(addr1, addr2) (memcmp(addr1, addr2, sizeof(uip_ip6addr_t)) == 0) +#endif /* !UIP_CONF_IPV6 */ + +/** + * Compare two IP addresses with netmasks + * + * Compares two IP addresses with netmasks. The masks are used to mask + * out the bits that are to be compared. + * + * Example: + \code + uip_ipaddr_t ipaddr1, ipaddr2, mask; + + uip_ipaddr(&mask, 255,255,255,0); + uip_ipaddr(&ipaddr1, 192,16,1,2); + uip_ipaddr(&ipaddr2, 192,16,1,3); + if(uip_ipaddr_maskcmp(&ipaddr1, &ipaddr2, &mask)) { + printf("They are the same"); + } + \endcode + * + * \param addr1 The first IP address. + * \param addr2 The second IP address. + * \param mask The netmask. + * + * \hideinitializer + */ +#define uip_ipaddr_maskcmp(addr1, addr2, mask) \ + (((((u16_t *)addr1)[0] & ((u16_t *)mask)[0]) == \ + (((u16_t *)addr2)[0] & ((u16_t *)mask)[0])) && \ + ((((u16_t *)addr1)[1] & ((u16_t *)mask)[1]) == \ + (((u16_t *)addr2)[1] & ((u16_t *)mask)[1]))) + + +/** + * Mask out the network part of an IP address. + * + * Masks out the network part of an IP address, given the address and + * the netmask. + * + * Example: + \code + uip_ipaddr_t ipaddr1, ipaddr2, netmask; + + uip_ipaddr(&ipaddr1, 192,16,1,2); + uip_ipaddr(&netmask, 255,255,255,0); + uip_ipaddr_mask(&ipaddr2, &ipaddr1, &netmask); + \endcode + * + * In the example above, the variable "ipaddr2" will contain the IP + * address 192.168.1.0. + * + * \param dest Where the result is to be placed. + * \param src The IP address. + * \param mask The netmask. + * + * \hideinitializer + */ +#define uip_ipaddr_mask(dest, src, mask) do { \ + ((u16_t *)dest)[0] = ((u16_t *)src)[0] & ((u16_t *)mask)[0]; \ + ((u16_t *)dest)[1] = ((u16_t *)src)[1] & ((u16_t *)mask)[1]; \ + } while(0) + +/** + * Pick the first octet of an IP address. + * + * Picks out the first octet of an IP address. + * + * Example: + \code + uip_ipaddr_t ipaddr; + u8_t octet; + + uip_ipaddr(&ipaddr, 1,2,3,4); + octet = uip_ipaddr1(&ipaddr); + \endcode + * + * In the example above, the variable "octet" will contain the value 1. + * + * \hideinitializer + */ +#define uip_ipaddr1(addr) (htons(((u16_t *)(addr))[0]) >> 8) + +/** + * Pick the second octet of an IP address. + * + * Picks out the second octet of an IP address. + * + * Example: + \code + uip_ipaddr_t ipaddr; + u8_t octet; + + uip_ipaddr(&ipaddr, 1,2,3,4); + octet = uip_ipaddr2(&ipaddr); + \endcode + * + * In the example above, the variable "octet" will contain the value 2. + * + * \hideinitializer + */ +#define uip_ipaddr2(addr) (htons(((u16_t *)(addr))[0]) & 0xff) + +/** + * Pick the third octet of an IP address. + * + * Picks out the third octet of an IP address. + * + * Example: + \code + uip_ipaddr_t ipaddr; + u8_t octet; + + uip_ipaddr(&ipaddr, 1,2,3,4); + octet = uip_ipaddr3(&ipaddr); + \endcode + * + * In the example above, the variable "octet" will contain the value 3. + * + * \hideinitializer + */ +#define uip_ipaddr3(addr) (htons(((u16_t *)(addr))[1]) >> 8) + +/** + * Pick the fourth octet of an IP address. + * + * Picks out the fourth octet of an IP address. + * + * Example: + \code + uip_ipaddr_t ipaddr; + u8_t octet; + + uip_ipaddr(&ipaddr, 1,2,3,4); + octet = uip_ipaddr4(&ipaddr); + \endcode + * + * In the example above, the variable "octet" will contain the value 4. + * + * \hideinitializer + */ +#define uip_ipaddr4(addr) (htons(((u16_t *)(addr))[1]) & 0xff) + +/** + * Convert 16-bit quantity from host byte order to network byte order. + * + * This macro is primarily used for converting constants from host + * byte order to network byte order. For converting variables to + * network byte order, use the htons() function instead. + * + * \hideinitializer + */ +#ifndef HTONS +# if UIP_BYTE_ORDER == UIP_BIG_ENDIAN +# define HTONS(n) (n) +# else /* UIP_BYTE_ORDER == UIP_BIG_ENDIAN */ +# define HTONS(n) (u16_t)((((u16_t) (n)) << 8) | (((u16_t) (n)) >> 8)) +# endif /* UIP_BYTE_ORDER == UIP_BIG_ENDIAN */ +#else +#error "HTONS already defined!" +#endif /* HTONS */ + +/** + * Convert 16-bit quantity from host byte order to network byte order. + * + * This function is primarily used for converting variables from host + * byte order to network byte order. For converting constants to + * network byte order, use the HTONS() macro instead. + */ +#ifndef htons +u16_t htons(u16_t val); +#endif /* htons */ +#ifndef ntohs +#define ntohs htons +#endif + +/** @} */ + +/** + * Pointer to the application data in the packet buffer. + * + * This pointer points to the application data when the application is + * called. If the application wishes to send data, the application may + * use this space to write the data into before calling uip_send(). + */ +extern void *uip_appdata; + +#if UIP_URGDATA > 0 +/* u8_t *uip_urgdata: + * + * This pointer points to any urgent data that has been received. Only + * present if compiled with support for urgent data (UIP_URGDATA). + */ +extern void *uip_urgdata; +#endif /* UIP_URGDATA > 0 */ + + +/** + * \defgroup uipdrivervars Variables used in uIP device drivers + * @{ + * + * uIP has a few global variables that are used in device drivers for + * uIP. + */ + +/** + * The length of the packet in the uip_buf buffer. + * + * The global variable uip_len holds the length of the packet in the + * uip_buf buffer. + * + * When the network device driver calls the uIP input function, + * uip_len should be set to the length of the packet in the uip_buf + * buffer. + * + * When sending packets, the device driver should use the contents of + * the uip_len variable to determine the length of the outgoing + * packet. + * + */ +extern u16_t uip_len; + +/** @} */ + +#if UIP_URGDATA > 0 +extern u16_t uip_urglen, uip_surglen; +#endif /* UIP_URGDATA > 0 */ + + +/** + * Representation of a uIP TCP connection. + * + * The uip_conn structure is used for identifying a connection. All + * but one field in the structure are to be considered read-only by an + * application. The only exception is the appstate field whos purpose + * is to let the application store application-specific state (e.g., + * file pointers) for the connection. The type of this field is + * configured in the "uipopt.h" header file. + */ +struct uip_conn { + uip_ipaddr_t ripaddr; /**< The IP address of the remote host. */ + + u16_t lport; /**< The local TCP port, in network byte order. */ + u16_t rport; /**< The local remote TCP port, in network byte + order. */ + + u8_t rcv_nxt[4]; /**< The sequence number that we expect to + receive next. */ + u8_t snd_nxt[4]; /**< The sequence number that was last sent by + us. */ + u16_t len; /**< Length of the data that was previously sent. */ + u16_t mss; /**< Current maximum segment size for the + connection. */ + u16_t initialmss; /**< Initial maximum segment size for the + connection. */ + u8_t sa; /**< Retransmission time-out calculation state + variable. */ + u8_t sv; /**< Retransmission time-out calculation state + variable. */ + u8_t rto; /**< Retransmission time-out. */ + u8_t tcpstateflags; /**< TCP state and flags. */ + u8_t timer; /**< The retransmission timer. */ + u8_t nrtx; /**< The number of retransmissions for the last + segment sent. */ + + /** The application state. */ + uip_tcp_appstate_t appstate; +}; + + +/** + * Pointer to the current TCP connection. + * + * The uip_conn pointer can be used to access the current TCP + * connection. + */ +extern struct uip_conn *uip_conn; +/* The array containing all uIP connections. */ +extern struct uip_conn uip_conns[UIP_CONNS]; +/** + * \addtogroup uiparch + * @{ + */ + +/** + * 4-byte array used for the 32-bit sequence number calculations. + */ +extern u8_t uip_acc32[4]; + +/** @} */ + + +#if UIP_UDP +/** + * Representation of a uIP UDP connection. + */ +struct uip_udp_conn { + uip_ipaddr_t ripaddr; /**< The IP address of the remote peer. */ + u16_t lport; /**< The local port number in network byte order. */ + u16_t rport; /**< The remote port number in network byte order. */ + u8_t ttl; /**< Default time-to-live. */ + + /** The application state. */ + uip_udp_appstate_t appstate; +}; + +/** + * The current UDP connection. + */ +extern struct uip_udp_conn *uip_udp_conn; +extern struct uip_udp_conn uip_udp_conns[UIP_UDP_CONNS]; +#endif /* UIP_UDP */ + +/** + * The structure holding the TCP/IP statistics that are gathered if + * UIP_STATISTICS is set to 1. + * + */ +struct uip_stats { + struct { + uip_stats_t drop; /**< Number of dropped packets at the IP + layer. */ + uip_stats_t recv; /**< Number of received packets at the IP + layer. */ + uip_stats_t sent; /**< Number of sent packets at the IP + layer. */ + uip_stats_t vhlerr; /**< Number of packets dropped due to wrong + IP version or header length. */ + uip_stats_t hblenerr; /**< Number of packets dropped due to wrong + IP length, high byte. */ + uip_stats_t lblenerr; /**< Number of packets dropped due to wrong + IP length, low byte. */ + uip_stats_t fragerr; /**< Number of packets dropped since they + were IP fragments. */ + uip_stats_t chkerr; /**< Number of packets dropped due to IP + checksum errors. */ + uip_stats_t protoerr; /**< Number of packets dropped since they + were neither ICMP, UDP nor TCP. */ + } ip; /**< IP statistics. */ + struct { + uip_stats_t drop; /**< Number of dropped ICMP packets. */ + uip_stats_t recv; /**< Number of received ICMP packets. */ + uip_stats_t sent; /**< Number of sent ICMP packets. */ + uip_stats_t typeerr; /**< Number of ICMP packets with a wrong + type. */ + } icmp; /**< ICMP statistics. */ + struct { + uip_stats_t drop; /**< Number of dropped TCP segments. */ + uip_stats_t recv; /**< Number of recived TCP segments. */ + uip_stats_t sent; /**< Number of sent TCP segments. */ + uip_stats_t chkerr; /**< Number of TCP segments with a bad + checksum. */ + uip_stats_t ackerr; /**< Number of TCP segments with a bad ACK + number. */ + uip_stats_t rst; /**< Number of recevied TCP RST (reset) segments. */ + uip_stats_t rexmit; /**< Number of retransmitted TCP segments. */ + uip_stats_t syndrop; /**< Number of dropped SYNs due to too few + connections was avaliable. */ + uip_stats_t synrst; /**< Number of SYNs for closed ports, + triggering a RST. */ + } tcp; /**< TCP statistics. */ +#if UIP_UDP + struct { + uip_stats_t drop; /**< Number of dropped UDP segments. */ + uip_stats_t recv; /**< Number of recived UDP segments. */ + uip_stats_t sent; /**< Number of sent UDP segments. */ + uip_stats_t chkerr; /**< Number of UDP segments with a bad + checksum. */ + } udp; /**< UDP statistics. */ +#endif /* UIP_UDP */ +}; + +/** + * The uIP TCP/IP statistics. + * + * This is the variable in which the uIP TCP/IP statistics are gathered. + */ +extern struct uip_stats uip_stat; + + +/*---------------------------------------------------------------------------*/ +/* All the stuff below this point is internal to uIP and should not be + * used directly by an application or by a device driver. + */ +/*---------------------------------------------------------------------------*/ +/* u8_t uip_flags: + * + * When the application is called, uip_flags will contain the flags + * that are defined in this file. Please read below for more + * infomation. + */ +extern u8_t uip_flags; + +/* The following flags may be set in the global variable uip_flags + before calling the application callback. The UIP_ACKDATA, + UIP_NEWDATA, and UIP_CLOSE flags may both be set at the same time, + whereas the others are mutualy exclusive. Note that these flags + should *NOT* be accessed directly, but only through the uIP + functions/macros. */ + +#define UIP_ACKDATA 1 /* Signifies that the outstanding data was + acked and the application should send + out new data instead of retransmitting + the last data. */ +#define UIP_NEWDATA 2 /* Flags the fact that the peer has sent + us new data. */ +#define UIP_REXMIT 4 /* Tells the application to retransmit the + data that was last sent. */ +#define UIP_POLL 8 /* Used for polling the application, to + check if the application has data that + it wants to send. */ +#define UIP_CLOSE 16 /* The remote host has closed the + connection, thus the connection has + gone away. Or the application signals + that it wants to close the + connection. */ +#define UIP_ABORT 32 /* The remote host has aborted the + connection, thus the connection has + gone away. Or the application signals + that it wants to abort the + connection. */ +#define UIP_CONNECTED 64 /* We have got a connection from a remote + host and have set up a new connection + for it, or an active connection has + been successfully established. */ + +#define UIP_TIMEDOUT 128 /* The connection has been aborted due to + too many retransmissions. */ + +/* uip_process(flag): + * + * The actual uIP function which does all the work. + */ +void uip_process(u8_t flag); + +/* The following flags are passed as an argument to the uip_process() + function. They are used to distinguish between the two cases where + uip_process() is called. It can be called either because we have + incoming data that should be processed, or because the periodic + timer has fired. These values are never used directly, but only in + the macrose defined in this file. */ + +#define UIP_DATA 1 /* Tells uIP that there is incoming + data in the uip_buf buffer. The + length of the data is stored in the + global variable uip_len. */ +#define UIP_TIMER 2 /* Tells uIP that the periodic timer + has fired. */ +#define UIP_POLL_REQUEST 3 /* Tells uIP that a connection should + be polled. */ +#define UIP_UDP_SEND_CONN 4 /* Tells uIP that a UDP datagram + should be constructed in the + uip_buf buffer. */ +#if UIP_UDP +#define UIP_UDP_TIMER 5 +#endif /* UIP_UDP */ + +/* The TCP states used in the uip_conn->tcpstateflags. */ +#define UIP_CLOSED 0 +#define UIP_SYN_RCVD 1 +#define UIP_SYN_SENT 2 +#define UIP_ESTABLISHED 3 +#define UIP_FIN_WAIT_1 4 +#define UIP_FIN_WAIT_2 5 +#define UIP_CLOSING 6 +#define UIP_TIME_WAIT 7 +#define UIP_LAST_ACK 8 +#define UIP_TS_MASK 15 + +#define UIP_STOPPED 16 + +/* The TCP and IP headers. */ + +#ifdef __ICCARM__ + #pragma pack(1) +#endif + +struct uip_tcpip_hdr { +#if UIP_CONF_IPV6 + /* IPv6 header. */ + u8_t vtc, + tcflow; + u16_t flow; + u8_t len[2]; + u8_t proto, ttl; + uip_ip6addr_t srcipaddr, destipaddr; +#else /* UIP_CONF_IPV6 */ + /* IPv4 header. */ + u8_t vhl, + tos, + len[2], + ipid[2], + ipoffset[2], + ttl, + proto; + u16_t ipchksum; + u16_t srcipaddr[2], + destipaddr[2]; +#endif /* UIP_CONF_IPV6 */ + + /* TCP header. */ + u16_t srcport, + destport; + u8_t seqno[4], + ackno[4], + tcpoffset, + flags, + wnd[2]; + u16_t tcpchksum; + u8_t urgp[2]; + u8_t optdata[4]; +} PACK_STRUCT_END; + +#ifdef __ICCARM__ + #pragma pack() +#endif + +/* The ICMP and IP headers. */ +#ifdef __ICCARM__ + #pragma pack(1) +#endif + +struct uip_icmpip_hdr { +#if UIP_CONF_IPV6 + /* IPv6 header. */ + u8_t vtc, + tcf; + u16_t flow; + u8_t len[2]; + u8_t proto, ttl; + uip_ip6addr_t srcipaddr, destipaddr; +#else /* UIP_CONF_IPV6 */ + /* IPv4 header. */ + u8_t vhl, + tos, + len[2], + ipid[2], + ipoffset[2], + ttl, + proto; + u16_t ipchksum; + u16_t srcipaddr[2], + destipaddr[2]; +#endif /* UIP_CONF_IPV6 */ + + /* ICMP (echo) header. */ + u8_t type, icode; + u16_t icmpchksum; +#if !UIP_CONF_IPV6 + u16_t id, seqno; +#else /* !UIP_CONF_IPV6 */ + u8_t flags, reserved1, reserved2, reserved3; + u8_t icmp6data[16]; + u8_t options[1]; +#endif /* !UIP_CONF_IPV6 */ +} PACK_STRUCT_END; + +#ifdef __ICCARM__ + #pragma pack() +#endif + + +/* The UDP and IP headers. */ +#ifdef __ICCARM__ + #pragma pack(1) +#endif + +struct uip_udpip_hdr { +#if UIP_CONF_IPV6 + /* IPv6 header. */ + u8_t vtc, + tcf; + u16_t flow; + u8_t len[2]; + u8_t proto, ttl; + uip_ip6addr_t srcipaddr, destipaddr; +#else /* UIP_CONF_IPV6 */ + /* IP header. */ + u8_t vhl, + tos, + len[2], + ipid[2], + ipoffset[2], + ttl, + proto; + u16_t ipchksum; + u16_t srcipaddr[2], + destipaddr[2]; +#endif /* UIP_CONF_IPV6 */ + + /* UDP header. */ + u16_t srcport, + destport; + u16_t udplen; + u16_t udpchksum; +} PACK_STRUCT_END; + +#ifdef __ICCARM__ + #pragma pack() +#endif + + + +/** + * The buffer size available for user data in the \ref uip_buf buffer. + * + * This macro holds the available size for user data in the \ref + * uip_buf buffer. The macro is intended to be used for checking + * bounds of available user data. + * + * Example: + \code + snprintf(uip_appdata, UIP_APPDATA_SIZE, "%u\n", i); + \endcode + * + * \hideinitializer + */ +#define UIP_APPDATA_SIZE (UIP_BUFSIZE - UIP_LLH_LEN - UIP_TCPIP_HLEN) + + +#define UIP_PROTO_ICMP 1 +#define UIP_PROTO_TCP 6 +#define UIP_PROTO_UDP 17 +#define UIP_PROTO_ICMP6 58 + +/* Header sizes. */ +#if UIP_CONF_IPV6 +#define UIP_IPH_LEN 40 +#else /* UIP_CONF_IPV6 */ +#define UIP_IPH_LEN 20 /* Size of IP header */ +#endif /* UIP_CONF_IPV6 */ +#define UIP_UDPH_LEN 8 /* Size of UDP header */ +#define UIP_TCPH_LEN 20 /* Size of TCP header */ +#define UIP_IPUDPH_LEN (UIP_UDPH_LEN + UIP_IPH_LEN) /* Size of IP + + UDP + header */ +#define UIP_IPTCPH_LEN (UIP_TCPH_LEN + UIP_IPH_LEN) /* Size of IP + + TCP + header */ +#define UIP_TCPIP_HLEN UIP_IPTCPH_LEN + + +#if UIP_FIXEDADDR +extern const uip_ipaddr_t uip_hostaddr, uip_netmask, uip_draddr; +#else /* UIP_FIXEDADDR */ +extern uip_ipaddr_t uip_hostaddr, uip_netmask, uip_draddr; +#endif /* UIP_FIXEDADDR */ + + + +/** + * Representation of a 48-bit Ethernet address. + */ +#ifdef __ICCARM__ + #pragma pack(1) +#endif + +struct uip_eth_addr { + u8_t addr[6]; +} PACK_STRUCT_END; + +#ifdef __ICCARM__ + #pragma pack() +#endif + +/** + * Calculate the Internet checksum over a buffer. + * + * The Internet checksum is the one's complement of the one's + * complement sum of all 16-bit words in the buffer. + * + * See RFC1071. + * + * \param buf A pointer to the buffer over which the checksum is to be + * computed. + * + * \param len The length of the buffer over which the checksum is to + * be computed. + * + * \return The Internet checksum of the buffer. + */ +u16_t uip_chksum(u16_t *buf, u16_t len); + +/** + * Calculate the IP header checksum of the packet header in uip_buf. + * + * The IP header checksum is the Internet checksum of the 20 bytes of + * the IP header. + * + * \return The IP header checksum of the IP header in the uip_buf + * buffer. + */ +u16_t uip_ipchksum(void); + +/** + * Calculate the TCP checksum of the packet in uip_buf and uip_appdata. + * + * The TCP checksum is the Internet checksum of data contents of the + * TCP segment, and a pseudo-header as defined in RFC793. + * + * \return The TCP checksum of the TCP segment in uip_buf and pointed + * to by uip_appdata. + */ +u16_t uip_tcpchksum(void); + +/** + * Calculate the UDP checksum of the packet in uip_buf and uip_appdata. + * + * The UDP checksum is the Internet checksum of data contents of the + * UDP segment, and a pseudo-header as defined in RFC768. + * + * \return The UDP checksum of the UDP segment in uip_buf and pointed + * to by uip_appdata. + */ +u16_t uip_udpchksum(void); + + +#endif /* __UIP_H__ */ + + +/** @} */ diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/uip_arch.h b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/uip_arch.h new file mode 100644 index 000000000..5ea45787c --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/uip_arch.h @@ -0,0 +1,138 @@ +/** + * \addtogroup uip + * {@ + */ + +/** + * \defgroup uiparch Architecture specific uIP functions + * @{ + * + * The functions in the architecture specific module implement the IP + * check sum and 32-bit additions. + * + * The IP checksum calculation is the most computationally expensive + * operation in the TCP/IP stack and it therefore pays off to + * implement this in efficient assembler. The purpose of the uip-arch + * module is to let the checksum functions to be implemented in + * architecture specific assembler. + * + */ + +/** + * \file + * Declarations of architecture specific functions. + * \author Adam Dunkels + */ + +/* + * Copyright (c) 2001, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: uip_arch.h,v 1.2 2006/06/07 09:15:19 adam Exp $ + * + */ + +#ifndef __UIP_ARCH_H__ +#define __UIP_ARCH_H__ + +#include "uip.h" + +/** + * Carry out a 32-bit addition. + * + * Because not all architectures for which uIP is intended has native + * 32-bit arithmetic, uIP uses an external C function for doing the + * required 32-bit additions in the TCP protocol processing. This + * function should add the two arguments and place the result in the + * global variable uip_acc32. + * + * \note The 32-bit integer pointed to by the op32 parameter and the + * result in the uip_acc32 variable are in network byte order (big + * endian). + * + * \param op32 A pointer to a 4-byte array representing a 32-bit + * integer in network byte order (big endian). + * + * \param op16 A 16-bit integer in host byte order. + */ +void uip_add32(u8_t *op32, u16_t op16); + +/** + * Calculate the Internet checksum over a buffer. + * + * The Internet checksum is the one's complement of the one's + * complement sum of all 16-bit words in the buffer. + * + * See RFC1071. + * + * \note This function is not called in the current version of uIP, + * but future versions might make use of it. + * + * \param buf A pointer to the buffer over which the checksum is to be + * computed. + * + * \param len The length of the buffer over which the checksum is to + * be computed. + * + * \return The Internet checksum of the buffer. + */ +u16_t uip_chksum(u16_t *buf, u16_t len); + +/** + * Calculate the IP header checksum of the packet header in uip_buf. + * + * The IP header checksum is the Internet checksum of the 20 bytes of + * the IP header. + * + * \return The IP header checksum of the IP header in the uip_buf + * buffer. + */ +u16_t uip_ipchksum(void); + +/** + * Calculate the TCP checksum of the packet in uip_buf and uip_appdata. + * + * The TCP checksum is the Internet checksum of data contents of the + * TCP segment, and a pseudo-header as defined in RFC793. + * + * \note The uip_appdata pointer that points to the packet data may + * point anywhere in memory, so it is not possible to simply calculate + * the Internet checksum of the contents of the uip_buf buffer. + * + * \return The TCP checksum of the TCP segment in uip_buf and pointed + * to by uip_appdata. + */ +u16_t uip_tcpchksum(void); + +u16_t uip_udpchksum(void); + +/** @} */ +/** @} */ + +#endif /* __UIP_ARCH_H__ */ diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/uip_arp.c b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/uip_arp.c new file mode 100644 index 000000000..44c7975fc --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/uip_arp.c @@ -0,0 +1,439 @@ +/** + * \addtogroup uip + * @{ + */ + +/** + * \defgroup uiparp uIP Address Resolution Protocol + * @{ + * + * The Address Resolution Protocol ARP is used for mapping between IP + * addresses and link level addresses such as the Ethernet MAC + * addresses. ARP uses broadcast queries to ask for the link level + * address of a known IP address and the host which is configured with + * the IP address for which the query was meant, will respond with its + * link level address. + * + * \note This ARP implementation only supports Ethernet. + */ + +/** + * \file + * Implementation of the ARP Address Resolution Protocol. + * \author Adam Dunkels + * + */ + +/* + * Copyright (c) 2001-2003, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: uip_arp.c,v 1.8 2006/06/02 23:36:21 adam Exp $ + * + */ + + +#include "uip_arp.h" + +#include + +#ifdef __ICCARM__ + #pragma pack(1) +#endif + +struct arp_hdr { + struct uip_eth_hdr ethhdr; + u16_t hwtype; + u16_t protocol; + u8_t hwlen; + u8_t protolen; + u16_t opcode; + struct uip_eth_addr shwaddr; + u16_t sipaddr[2]; + struct uip_eth_addr dhwaddr; + u16_t dipaddr[2]; +} PACK_STRUCT_END; + +#ifdef __ICCARM__ + #pragma pack() +#endif + +#ifdef __ICCARM__ + #pragma pack(1) +#endif + +struct ethip_hdr { + struct uip_eth_hdr ethhdr; + /* IP header. */ + u8_t vhl, + tos, + len[2], + ipid[2], + ipoffset[2], + ttl, + proto; + u16_t ipchksum; + u16_t srcipaddr[2], + destipaddr[2]; +} PACK_STRUCT_END; + +#ifdef __ICCARM__ + #pragma pack() +#endif + +#define ARP_REQUEST 1 +#define ARP_REPLY 2 + +#define ARP_HWTYPE_ETH 1 + +struct arp_entry { + u16_t ipaddr[2]; + struct uip_eth_addr ethaddr; + u8_t time; +}; + +static const struct uip_eth_addr broadcast_ethaddr = + {{0xff,0xff,0xff,0xff,0xff,0xff}}; +static const u16_t broadcast_ipaddr[2] = {0xffff,0xffff}; + +static struct arp_entry arp_table[UIP_ARPTAB_SIZE]; +static u16_t ipaddr[2]; +static u8_t i, c; + +static u8_t arptime; +static u8_t tmpage; + +#define BUF ((struct arp_hdr *)&uip_buf[0]) +#define IPBUF ((struct ethip_hdr *)&uip_buf[0]) +/*-----------------------------------------------------------------------------------*/ +/** + * Initialize the ARP module. + * + */ +/*-----------------------------------------------------------------------------------*/ +void +uip_arp_init(void) +{ + for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { + memset(arp_table[i].ipaddr, 0, 4); + } +} +/*-----------------------------------------------------------------------------------*/ +/** + * Periodic ARP processing function. + * + * This function performs periodic timer processing in the ARP module + * and should be called at regular intervals. The recommended interval + * is 10 seconds between the calls. + * + */ +/*-----------------------------------------------------------------------------------*/ +void +uip_arp_timer(void) +{ + struct arp_entry *tabptr; + + ++arptime; + for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { + tabptr = &arp_table[i]; + if((tabptr->ipaddr[0] | tabptr->ipaddr[1]) != 0 && + arptime - tabptr->time >= UIP_ARP_MAXAGE) { + memset(tabptr->ipaddr, 0, 4); + } + } + +} +/*-----------------------------------------------------------------------------------*/ +static void +uip_arp_update(u16_t *ipaddr, struct uip_eth_addr *ethaddr) +{ + register struct arp_entry *tabptr; + /* Walk through the ARP mapping table and try to find an entry to + update. If none is found, the IP -> MAC address mapping is + inserted in the ARP table. */ + for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { + + tabptr = &arp_table[i]; + /* Only check those entries that are actually in use. */ + if(tabptr->ipaddr[0] != 0 && + tabptr->ipaddr[1] != 0) { + + /* Check if the source IP address of the incoming packet matches + the IP address in this ARP table entry. */ + if(ipaddr[0] == tabptr->ipaddr[0] && + ipaddr[1] == tabptr->ipaddr[1]) { + + /* An old entry found, update this and return. */ + memcpy(tabptr->ethaddr.addr, ethaddr->addr, 6); + tabptr->time = arptime; + + return; + } + } + } + + /* If we get here, no existing ARP table entry was found, so we + create one. */ + + /* First, we try to find an unused entry in the ARP table. */ + for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { + tabptr = &arp_table[i]; + if(tabptr->ipaddr[0] == 0 && + tabptr->ipaddr[1] == 0) { + break; + } + } + + /* If no unused entry is found, we try to find the oldest entry and + throw it away. */ + if(i == UIP_ARPTAB_SIZE) { + tmpage = 0; + c = 0; + for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { + tabptr = &arp_table[i]; + if(arptime - tabptr->time > tmpage) { + tmpage = arptime - tabptr->time; + c = i; + } + } + i = c; + tabptr = &arp_table[i]; + } + + /* Now, i is the ARP table entry which we will fill with the new + information. */ + memcpy(tabptr->ipaddr, ipaddr, 4); + memcpy(tabptr->ethaddr.addr, ethaddr->addr, 6); + tabptr->time = arptime; +} +/*-----------------------------------------------------------------------------------*/ +/** + * ARP processing for incoming IP packets + * + * This function should be called by the device driver when an IP + * packet has been received. The function will check if the address is + * in the ARP cache, and if so the ARP cache entry will be + * refreshed. If no ARP cache entry was found, a new one is created. + * + * This function expects an IP packet with a prepended Ethernet header + * in the uip_buf[] buffer, and the length of the packet in the global + * variable uip_len. + */ +/*-----------------------------------------------------------------------------------*/ +#if 1 +void +uip_arp_ipin(void) +{ + uip_len -= sizeof(struct uip_eth_hdr); + + /* Only insert/update an entry if the source IP address of the + incoming IP packet comes from a host on the local network. */ + if((IPBUF->srcipaddr[0] & uip_netmask[0]) != + (uip_hostaddr[0] & uip_netmask[0])) { + return; + } + if((IPBUF->srcipaddr[1] & uip_netmask[1]) != + (uip_hostaddr[1] & uip_netmask[1])) { + return; + } + uip_arp_update(IPBUF->srcipaddr, &(IPBUF->ethhdr.src)); + + return; +} +#endif /* 0 */ +/*-----------------------------------------------------------------------------------*/ +/** + * ARP processing for incoming ARP packets. + * + * This function should be called by the device driver when an ARP + * packet has been received. The function will act differently + * depending on the ARP packet type: if it is a reply for a request + * that we previously sent out, the ARP cache will be filled in with + * the values from the ARP reply. If the incoming ARP packet is an ARP + * request for our IP address, an ARP reply packet is created and put + * into the uip_buf[] buffer. + * + * When the function returns, the value of the global variable uip_len + * indicates whether the device driver should send out a packet or + * not. If uip_len is zero, no packet should be sent. If uip_len is + * non-zero, it contains the length of the outbound packet that is + * present in the uip_buf[] buffer. + * + * This function expects an ARP packet with a prepended Ethernet + * header in the uip_buf[] buffer, and the length of the packet in the + * global variable uip_len. + */ +/*-----------------------------------------------------------------------------------*/ +void +uip_arp_arpin(void) +{ + + if(uip_len < sizeof(struct arp_hdr)) { + uip_len = 0; + return; + } + uip_len = 0; + + switch(BUF->opcode) { + case HTONS(ARP_REQUEST): + /* ARP request. If it asked for our address, we send out a + reply. */ + if(uip_ipaddr_cmp(BUF->dipaddr, uip_hostaddr)) { + /* First, we register the one who made the request in our ARP + table, since it is likely that we will do more communication + with this host in the future. */ + uip_arp_update(BUF->sipaddr, &BUF->shwaddr); + + /* The reply opcode is 2. */ + BUF->opcode = HTONS(2); + + memcpy(BUF->dhwaddr.addr, BUF->shwaddr.addr, 6); + memcpy(BUF->shwaddr.addr, uip_ethaddr.addr, 6); + memcpy(BUF->ethhdr.src.addr, uip_ethaddr.addr, 6); + memcpy(BUF->ethhdr.dest.addr, BUF->dhwaddr.addr, 6); + + BUF->dipaddr[0] = BUF->sipaddr[0]; + BUF->dipaddr[1] = BUF->sipaddr[1]; + BUF->sipaddr[0] = uip_hostaddr[0]; + BUF->sipaddr[1] = uip_hostaddr[1]; + + BUF->ethhdr.type = HTONS(UIP_ETHTYPE_ARP); + uip_len = sizeof(struct arp_hdr); + } + break; + case HTONS(ARP_REPLY): + /* ARP reply. We insert or update the ARP table if it was meant + for us. */ + if(uip_ipaddr_cmp(BUF->dipaddr, uip_hostaddr)) { + uip_arp_update(BUF->sipaddr, &BUF->shwaddr); + } + break; + } + + return; +} +/*-----------------------------------------------------------------------------------*/ +/** + * Prepend Ethernet header to an outbound IP packet and see if we need + * to send out an ARP request. + * + * This function should be called before sending out an IP packet. The + * function checks the destination IP address of the IP packet to see + * what Ethernet MAC address that should be used as a destination MAC + * address on the Ethernet. + * + * If the destination IP address is in the local network (determined + * by logical ANDing of netmask and our IP address), the function + * checks the ARP cache to see if an entry for the destination IP + * address is found. If so, an Ethernet header is prepended and the + * function returns. If no ARP cache entry is found for the + * destination IP address, the packet in the uip_buf[] is replaced by + * an ARP request packet for the IP address. The IP packet is dropped + * and it is assumed that they higher level protocols (e.g., TCP) + * eventually will retransmit the dropped packet. + * + * If the destination IP address is not on the local network, the IP + * address of the default router is used instead. + * + * When the function returns, a packet is present in the uip_buf[] + * buffer, and the length of the packet is in the global variable + * uip_len. + */ +/*-----------------------------------------------------------------------------------*/ +void +uip_arp_out(void) +{ + struct arp_entry *tabptr; + + /* Find the destination IP address in the ARP table and construct + the Ethernet header. If the destination IP addres isn't on the + local network, we use the default router's IP address instead. + + If not ARP table entry is found, we overwrite the original IP + packet with an ARP request for the IP address. */ + + /* First check if destination is a local broadcast. */ + if(uip_ipaddr_cmp(IPBUF->destipaddr, broadcast_ipaddr)) { + memcpy(IPBUF->ethhdr.dest.addr, broadcast_ethaddr.addr, 6); + } else { + /* Check if the destination address is on the local network. */ + if(!uip_ipaddr_maskcmp(IPBUF->destipaddr, uip_hostaddr, uip_netmask)) { + /* Destination address was not on the local network, so we need to + use the default router's IP address instead of the destination + address when determining the MAC address. */ + uip_ipaddr_copy(ipaddr, uip_draddr); + } else { + /* Else, we use the destination IP address. */ + uip_ipaddr_copy(ipaddr, IPBUF->destipaddr); + } + + for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { + tabptr = &arp_table[i]; + if(uip_ipaddr_cmp(ipaddr, tabptr->ipaddr)) { + break; + } + } + + if(i == UIP_ARPTAB_SIZE) { + /* The destination address was not in our ARP table, so we + overwrite the IP packet with an ARP request. */ + + memset(BUF->ethhdr.dest.addr, 0xff, 6); + memset(BUF->dhwaddr.addr, 0x00, 6); + memcpy(BUF->ethhdr.src.addr, uip_ethaddr.addr, 6); + memcpy(BUF->shwaddr.addr, uip_ethaddr.addr, 6); + + uip_ipaddr_copy(BUF->dipaddr, ipaddr); + uip_ipaddr_copy(BUF->sipaddr, uip_hostaddr); + BUF->opcode = HTONS(ARP_REQUEST); /* ARP request. */ + BUF->hwtype = HTONS(ARP_HWTYPE_ETH); + BUF->protocol = HTONS(UIP_ETHTYPE_IP); + BUF->hwlen = 6; + BUF->protolen = 4; + BUF->ethhdr.type = HTONS(UIP_ETHTYPE_ARP); + + uip_appdata = &uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN]; + + uip_len = sizeof(struct arp_hdr); + return; + } + + /* Build an ethernet header. */ + memcpy(IPBUF->ethhdr.dest.addr, tabptr->ethaddr.addr, 6); + } + memcpy(IPBUF->ethhdr.src.addr, uip_ethaddr.addr, 6); + + IPBUF->ethhdr.type = HTONS(UIP_ETHTYPE_IP); + + uip_len += sizeof(struct uip_eth_hdr); +} +/*-----------------------------------------------------------------------------------*/ + +/** @} */ +/** @} */ diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/uip_arp.h b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/uip_arp.h new file mode 100644 index 000000000..b6b2b66b4 --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/uip_arp.h @@ -0,0 +1,152 @@ +/** + * \addtogroup uip + * @{ + */ + +/** + * \addtogroup uiparp + * @{ + */ + +/** + * \file + * Macros and definitions for the ARP module. + * \author Adam Dunkels + */ + + +/* + * Copyright (c) 2001-2003, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: uip_arp.h,v 1.5 2006/06/11 21:46:39 adam Exp $ + * + */ + +#ifndef __UIP_ARP_H__ +#define __UIP_ARP_H__ + +#include "uip.h" + + +extern struct uip_eth_addr uip_ethaddr; + +/** + * The Ethernet header. + */ +#ifdef __ICCARM__ + #pragma pack(1) +#endif + +struct uip_eth_hdr { + struct uip_eth_addr dest; + struct uip_eth_addr src; + u16_t type; +}PACK_STRUCT_END; + +#ifdef __ICCARM__ + #pragma pack() +#endif + +#define UIP_ETHTYPE_ARP 0x0806 +#define UIP_ETHTYPE_IP 0x0800 +#define UIP_ETHTYPE_IP6 0x86dd + + +/* The uip_arp_init() function must be called before any of the other + ARP functions. */ +void uip_arp_init(void); + +/* The uip_arp_ipin() function should be called whenever an IP packet + arrives from the Ethernet. This function refreshes the ARP table or + inserts a new mapping if none exists. The function assumes that an + IP packet with an Ethernet header is present in the uip_buf buffer + and that the length of the packet is in the uip_len variable. */ +void uip_arp_ipin(void); +//#define uip_arp_ipin() + +/* The uip_arp_arpin() should be called when an ARP packet is received + by the Ethernet driver. This function also assumes that the + Ethernet frame is present in the uip_buf buffer. When the + uip_arp_arpin() function returns, the contents of the uip_buf + buffer should be sent out on the Ethernet if the uip_len variable + is > 0. */ +void uip_arp_arpin(void); + +/* The uip_arp_out() function should be called when an IP packet + should be sent out on the Ethernet. This function creates an + Ethernet header before the IP header in the uip_buf buffer. The + Ethernet header will have the correct Ethernet MAC destination + address filled in if an ARP table entry for the destination IP + address (or the IP address of the default router) is present. If no + such table entry is found, the IP packet is overwritten with an ARP + request and we rely on TCP to retransmit the packet that was + overwritten. In any case, the uip_len variable holds the length of + the Ethernet frame that should be transmitted. */ +void uip_arp_out(void); + +/* The uip_arp_timer() function should be called every ten seconds. It + is responsible for flushing old entries in the ARP table. */ +void uip_arp_timer(void); + +/** @} */ + +/** + * \addtogroup uipconffunc + * @{ + */ + + +/** + * Specifiy the Ethernet MAC address. + * + * The ARP code needs to know the MAC address of the Ethernet card in + * order to be able to respond to ARP queries and to generate working + * Ethernet headers. + * + * \note This macro only specifies the Ethernet MAC address to the ARP + * code. It cannot be used to change the MAC address of the Ethernet + * card. + * + * \param eaddr A pointer to a struct uip_eth_addr containing the + * Ethernet MAC address of the Ethernet card. + * + * \hideinitializer + */ +#define uip_setethaddr(eaddr) do {uip_ethaddr.addr[0] = eaddr.addr[0]; \ + uip_ethaddr.addr[1] = eaddr.addr[1];\ + uip_ethaddr.addr[2] = eaddr.addr[2];\ + uip_ethaddr.addr[3] = eaddr.addr[3];\ + uip_ethaddr.addr[4] = eaddr.addr[4];\ + uip_ethaddr.addr[5] = eaddr.addr[5];} while(0) + +/** @} */ +/** @} */ + +#endif /* __UIP_ARP_H__ */ diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/uiplib.c b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/uiplib.c new file mode 100644 index 000000000..647b0b270 --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/uiplib.c @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2004, Adam Dunkels and the Swedish Institute of + * Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: uiplib.c,v 1.2 2006/06/12 08:00:31 adam Exp $ + * + */ + + +#include "uip.h" +#include "uiplib.h" + + +/*-----------------------------------------------------------------------------------*/ +unsigned char +uiplib_ipaddrconv(char *addrstr, unsigned char *ipaddr) +{ + unsigned char tmp; + char c; + unsigned char i, j; + + tmp = 0; + + for(i = 0; i < 4; ++i) { + j = 0; + do { + c = *addrstr; + ++j; + if(j > 4) { + return 0; + } + if(c == '.' || c == 0) { + *ipaddr = tmp; + ++ipaddr; + tmp = 0; + } else if(c >= '0' && c <= '9') { + tmp = (tmp * 10) + (c - '0'); + } else { + return 0; + } + ++addrstr; + } while(c != '.' && c != 0); + } + return 1; +} + +/*-----------------------------------------------------------------------------------*/ diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/uiplib.h b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/uiplib.h new file mode 100644 index 000000000..6eb0c66f5 --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/uiplib.h @@ -0,0 +1,71 @@ +/** + * \file + * Various uIP library functions. + * \author + * Adam Dunkels + * + */ + +/* + * Copyright (c) 2002, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: uiplib.h,v 1.1 2006/06/07 09:15:19 adam Exp $ + * + */ +#ifndef __UIPLIB_H__ +#define __UIPLIB_H__ + +/** + * \addtogroup uipconvfunc + * @{ + */ + +/** + * Convert a textual representation of an IP address to a numerical representation. + * + * This function takes a textual representation of an IP address in + * the form a.b.c.d and converts it into a 4-byte array that can be + * used by other uIP functions. + * + * \param addrstr A pointer to a string containing the IP address in + * textual form. + * + * \param addr A pointer to a 4-byte array that will be filled in with + * the numerical representation of the address. + * + * \retval 0 If the IP address could not be parsed. + * \retval Non-zero If the IP address was parsed. + */ +unsigned char uiplib_ipaddrconv(char *addrstr, unsigned char *addr); + +/** @} */ + +#endif /* __UIPLIB_H__ */ diff --git a/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/uipopt.h b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/uipopt.h new file mode 100644 index 000000000..f7c3e0f80 --- /dev/null +++ b/20080212/Demo/Common/ethernet/uIP/uip-1.0/uip/uipopt.h @@ -0,0 +1,539 @@ +/** + * \defgroup uipopt Configuration options for uIP + * @{ + * + * uIP is configured using the per-project configuration file + * uipopt.h. This file contains all compile-time options for uIP and + * should be tweaked to match each specific project. The uIP + * distribution contains a documented example "uipopt.h" that can be + * copied and modified for each project. + * + * \note Most of the configuration options in the uipopt.h should not + * be changed, but rather the per-project uip-conf.h file. + */ + +/** + * \file + * Configuration options for uIP. + * \author Adam Dunkels + * + * This file is used for tweaking various configuration options for + * uIP. You should make a copy of this file into one of your project's + * directories instead of editing this example "uipopt.h" file that + * comes with the uIP distribution. + */ + +/* + * Copyright (c) 2001-2003, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: uipopt.h,v 1.4 2006/06/12 08:00:31 adam Exp $ + * + */ + +#ifndef __UIPOPT_H__ +#define __UIPOPT_H__ + +#ifndef UIP_LITTLE_ENDIAN +#define UIP_LITTLE_ENDIAN 3412 +#endif /* UIP_LITTLE_ENDIAN */ +#ifndef UIP_BIG_ENDIAN +#define UIP_BIG_ENDIAN 1234 +#endif /* UIP_BIG_ENDIAN */ + +#include "uip-conf.h" + +/*------------------------------------------------------------------------------*/ + +/** + * \name Static configuration options + * @{ + * + * These configuration options can be used for setting the IP address + * settings statically, but only if UIP_FIXEDADDR is set to 1. The + * configuration options for a specific node includes IP address, + * netmask and default router as well as the Ethernet address. The + * netmask, default router and Ethernet address are appliciable only + * if uIP should be run over Ethernet. + * + * All of these should be changed to suit your project. +*/ + +/** + * Determines if uIP should use a fixed IP address or not. + * + * If uIP should use a fixed IP address, the settings are set in the + * uipopt.h file. If not, the macros uip_sethostaddr(), + * uip_setdraddr() and uip_setnetmask() should be used instead. + * + * \hideinitializer + */ +#define UIP_FIXEDADDR 0 + +/** + * Ping IP address asignment. + * + * uIP uses a "ping" packets for setting its own IP address if this + * option is set. If so, uIP will start with an empty IP address and + * the destination IP address of the first incoming "ping" (ICMP echo) + * packet will be used for setting the hosts IP address. + * + * \note This works only if UIP_FIXEDADDR is 0. + * + * \hideinitializer + */ +#ifdef UIP_CONF_PINGADDRCONF +#define UIP_PINGADDRCONF UIP_CONF_PINGADDRCONF +#else /* UIP_CONF_PINGADDRCONF */ +#define UIP_PINGADDRCONF 0 +#endif /* UIP_CONF_PINGADDRCONF */ + + +/** + * Specifies if the uIP ARP module should be compiled with a fixed + * Ethernet MAC address or not. + * + * If this configuration option is 0, the macro uip_setethaddr() can + * be used to specify the Ethernet address at run-time. + * + * \hideinitializer + */ +#define UIP_FIXEDETHADDR 0 + +/** @} */ +/*------------------------------------------------------------------------------*/ +/** + * \name IP configuration options + * @{ + * + */ +/** + * The IP TTL (time to live) of IP packets sent by uIP. + * + * This should normally not be changed. + */ +#define UIP_TTL 64 + +/** + * Turn on support for IP packet reassembly. + * + * uIP supports reassembly of fragmented IP packets. This features + * requires an additonal amount of RAM to hold the reassembly buffer + * and the reassembly code size is approximately 700 bytes. The + * reassembly buffer is of the same size as the uip_buf buffer + * (configured by UIP_BUFSIZE). + * + * \note IP packet reassembly is not heavily tested. + * + * \hideinitializer + */ +#define UIP_REASSEMBLY 0 + +/** + * The maximum time an IP fragment should wait in the reassembly + * buffer before it is dropped. + * + */ +#define UIP_REASS_MAXAGE 40 + +/** @} */ + +/*------------------------------------------------------------------------------*/ +/** + * \name UDP configuration options + * @{ + */ + +/** + * Toggles wether UDP support should be compiled in or not. + * + * \hideinitializer + */ +#ifdef UIP_CONF_UDP +#define UIP_UDP UIP_CONF_UDP +#else /* UIP_CONF_UDP */ +#define UIP_UDP 0 +#endif /* UIP_CONF_UDP */ + +/** + * Toggles if UDP checksums should be used or not. + * + * \note Support for UDP checksums is currently not included in uIP, + * so this option has no function. + * + * \hideinitializer + */ +#ifdef UIP_CONF_UDP_CHECKSUMS +#define UIP_UDP_CHECKSUMS UIP_CONF_UDP_CHECKSUMS +#else +#define UIP_UDP_CHECKSUMS 0 +#endif + +/** + * The maximum amount of concurrent UDP connections. + * + * \hideinitializer + */ +#ifdef UIP_CONF_UDP_CONNS +#define UIP_UDP_CONNS UIP_CONF_UDP_CONNS +#else /* UIP_CONF_UDP_CONNS */ +#define UIP_UDP_CONNS 10 +#endif /* UIP_CONF_UDP_CONNS */ + +/** + * The name of the function that should be called when UDP datagrams arrive. + * + * \hideinitializer + */ + + +/** @} */ +/*------------------------------------------------------------------------------*/ +/** + * \name TCP configuration options + * @{ + */ + +/** + * Determines if support for opening connections from uIP should be + * compiled in. + * + * If the applications that are running on top of uIP for this project + * do not need to open outgoing TCP connections, this configration + * option can be turned off to reduce the code size of uIP. + * + * \hideinitializer + */ +#define UIP_ACTIVE_OPEN 1 + +/** + * The maximum number of simultaneously open TCP connections. + * + * Since the TCP connections are statically allocated, turning this + * configuration knob down results in less RAM used. Each TCP + * connection requires approximatly 30 bytes of memory. + * + * \hideinitializer + */ +#ifndef UIP_CONF_MAX_CONNECTIONS +#define UIP_CONNS 10 +#else /* UIP_CONF_MAX_CONNECTIONS */ +#define UIP_CONNS UIP_CONF_MAX_CONNECTIONS +#endif /* UIP_CONF_MAX_CONNECTIONS */ + + +/** + * The maximum number of simultaneously listening TCP ports. + * + * Each listening TCP port requires 2 bytes of memory. + * + * \hideinitializer + */ +#ifndef UIP_CONF_MAX_LISTENPORTS +#define UIP_LISTENPORTS 20 +#else /* UIP_CONF_MAX_LISTENPORTS */ +#define UIP_LISTENPORTS UIP_CONF_MAX_LISTENPORTS +#endif /* UIP_CONF_MAX_LISTENPORTS */ + +/** + * Determines if support for TCP urgent data notification should be + * compiled in. + * + * Urgent data (out-of-band data) is a rarely used TCP feature that + * very seldom would be required. + * + * \hideinitializer + */ +#define UIP_URGDATA 0 + +/** + * The initial retransmission timeout counted in timer pulses. + * + * This should not be changed. + */ +#define UIP_RTO 3 + +/** + * The maximum number of times a segment should be retransmitted + * before the connection should be aborted. + * + * This should not be changed. + */ +#define UIP_MAXRTX 8 + +/** + * The maximum number of times a SYN segment should be retransmitted + * before a connection request should be deemed to have been + * unsuccessful. + * + * This should not need to be changed. + */ +#define UIP_MAXSYNRTX 5 + +/** + * The TCP maximum segment size. + * + * This is should not be to set to more than + * UIP_BUFSIZE - UIP_LLH_LEN - UIP_TCPIP_HLEN. + */ +#define UIP_TCP_MSS (UIP_BUFSIZE - UIP_LLH_LEN - UIP_TCPIP_HLEN) + +/** + * The size of the advertised receiver's window. + * + * Should be set low (i.e., to the size of the uip_buf buffer) is the + * application is slow to process incoming data, or high (32768 bytes) + * if the application processes data quickly. + * + * \hideinitializer + */ +#ifndef UIP_CONF_RECEIVE_WINDOW +#define UIP_RECEIVE_WINDOW UIP_TCP_MSS +#else +#define UIP_RECEIVE_WINDOW UIP_CONF_RECEIVE_WINDOW +#endif + +/** + * How long a connection should stay in the TIME_WAIT state. + * + * This configiration option has no real implication, and it should be + * left untouched. + */ +#define UIP_TIME_WAIT_TIMEOUT 120 + + +/** @} */ +/*------------------------------------------------------------------------------*/ +/** + * \name ARP configuration options + * @{ + */ + +/** + * The size of the ARP table. + * + * This option should be set to a larger value if this uIP node will + * have many connections from the local network. + * + * \hideinitializer + */ +#ifdef UIP_CONF_ARPTAB_SIZE +#define UIP_ARPTAB_SIZE UIP_CONF_ARPTAB_SIZE +#else +#define UIP_ARPTAB_SIZE 8 +#endif + +/** + * The maxium age of ARP table entries measured in 10ths of seconds. + * + * An UIP_ARP_MAXAGE of 120 corresponds to 20 minutes (BSD + * default). + */ +#define UIP_ARP_MAXAGE 120 + +/** @} */ + +/*------------------------------------------------------------------------------*/ + +/** + * \name General configuration options + * @{ + */ + +/** + * The size of the uIP packet buffer. + * + * The uIP packet buffer should not be smaller than 60 bytes, and does + * not need to be larger than 1500 bytes. Lower size results in lower + * TCP throughput, larger size results in higher TCP throughput. + * + * \hideinitializer + */ +#ifndef UIP_CONF_BUFFER_SIZE +#define UIP_BUFSIZE 1500 +#else /* UIP_CONF_BUFFER_SIZE */ +#define UIP_BUFSIZE UIP_CONF_BUFFER_SIZE +#endif /* UIP_CONF_BUFFER_SIZE */ + + +/** + * Determines if statistics support should be compiled in. + * + * The statistics is useful for debugging and to show the user. + * + * \hideinitializer + */ +#ifndef UIP_CONF_STATISTICS +#define UIP_STATISTICS 0 +#else /* UIP_CONF_STATISTICS */ +#define UIP_STATISTICS UIP_CONF_STATISTICS +#endif /* UIP_CONF_STATISTICS */ + +/** + * Determines if logging of certain events should be compiled in. + * + * This is useful mostly for debugging. The function uip_log() + * must be implemented to suit the architecture of the project, if + * logging is turned on. + * + * \hideinitializer + */ +#ifndef UIP_CONF_LOGGING +#define UIP_LOGGING 0 +#else /* UIP_CONF_LOGGING */ +#define UIP_LOGGING UIP_CONF_LOGGING +#endif /* UIP_CONF_LOGGING */ + +/** + * Broadcast support. + * + * This flag configures IP broadcast support. This is useful only + * together with UDP. + * + * \hideinitializer + * + */ +#ifndef UIP_CONF_BROADCAST +#define UIP_BROADCAST 0 +#else /* UIP_CONF_BROADCAST */ +#define UIP_BROADCAST UIP_CONF_BROADCAST +#endif /* UIP_CONF_BROADCAST */ + +/** + * Print out a uIP log message. + * + * This function must be implemented by the module that uses uIP, and + * is called by uIP whenever a log message is generated. + */ +void uip_log(char *msg); + +/** + * The link level header length. + * + * This is the offset into the uip_buf where the IP header can be + * found. For Ethernet, this should be set to 14. For SLIP, this + * should be set to 0. + * + * \hideinitializer + */ +#ifdef UIP_CONF_LLH_LEN +#define UIP_LLH_LEN UIP_CONF_LLH_LEN +#else /* UIP_CONF_LLH_LEN */ +#define UIP_LLH_LEN 14 +#endif /* UIP_CONF_LLH_LEN */ + +/** @} */ +/*------------------------------------------------------------------------------*/ +/** + * \name CPU architecture configuration + * @{ + * + * The CPU architecture configuration is where the endianess of the + * CPU on which uIP is to be run is specified. Most CPUs today are + * little endian, and the most notable exception are the Motorolas + * which are big endian. The BYTE_ORDER macro should be changed to + * reflect the CPU architecture on which uIP is to be run. + */ + +/** + * The byte order of the CPU architecture on which uIP is to be run. + * + * This option can be either BIG_ENDIAN (Motorola byte order) or + * LITTLE_ENDIAN (Intel byte order). + * + * \hideinitializer + */ +#ifdef UIP_CONF_BYTE_ORDER +#define UIP_BYTE_ORDER UIP_CONF_BYTE_ORDER +#else /* UIP_CONF_BYTE_ORDER */ +#define UIP_BYTE_ORDER UIP_LITTLE_ENDIAN +#endif /* UIP_CONF_BYTE_ORDER */ + +/** @} */ +/*------------------------------------------------------------------------------*/ + +/** + * \name Appication specific configurations + * @{ + * + * An uIP application is implemented using a single application + * function that is called by uIP whenever a TCP/IP event occurs. The + * name of this function must be registered with uIP at compile time + * using the UIP_APPCALL definition. + * + * uIP applications can store the application state within the + * uip_conn structure by specifying the type of the application + * structure by typedef:ing the type uip_tcp_appstate_t and uip_udp_appstate_t. + * + * The file containing the definitions must be included in the + * uipopt.h file. + * + * The following example illustrates how this can look. + \code + +void httpd_appcall(void); +#define UIP_APPCALL httpd_appcall + +struct httpd_state { + u8_t state; + u16_t count; + char *dataptr; + char *script; +}; +typedef struct httpd_state uip_tcp_appstate_t + \endcode + */ + +/** + * \var #define UIP_APPCALL + * + * The name of the application function that uIP should call in + * response to TCP/IP events. + * + */ + +/** + * \var typedef uip_tcp_appstate_t + * + * The type of the application state that is to be stored in the + * uip_conn structure. This usually is typedef:ed to a struct holding + * application state information. + */ + +/** + * \var typedef uip_udp_appstate_t + * + * The type of the application state that is to be stored in the + * uip_conn structure. This usually is typedef:ed to a struct holding + * application state information. + */ +/** @} */ +/** @} */ + +#endif /* __UIPOPT_H__ */ diff --git a/20080212/Demo/Common/include/AltBlckQ.h b/20080212/Demo/Common/include/AltBlckQ.h new file mode 100644 index 000000000..f4acadc23 --- /dev/null +++ b/20080212/Demo/Common/include/AltBlckQ.h @@ -0,0 +1,51 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef ALT_BLOCK_Q_H +#define ALT_BLOCK_Q_H + +void vStartAltBlockingQueueTasks( unsigned portBASE_TYPE uxPriority ); +portBASE_TYPE xAreAltBlockingQueuesStillRunning( void ); + +#endif + + diff --git a/20080212/Demo/Common/include/AltBlock.h b/20080212/Demo/Common/include/AltBlock.h new file mode 100644 index 000000000..5732888c7 --- /dev/null +++ b/20080212/Demo/Common/include/AltBlock.h @@ -0,0 +1,51 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FAST_BLOCK_TIME_TEST_H +#define FAST_BLOCK_TIME_TEST_H + +void vCreateAltBlockTimeTasks( void ); +portBASE_TYPE xAreAltBlockTimeTestTasksStillRunning( void ); + +#endif + + diff --git a/20080212/Demo/Common/include/AltPollQ.h b/20080212/Demo/Common/include/AltPollQ.h new file mode 100644 index 000000000..b16c95d4c --- /dev/null +++ b/20080212/Demo/Common/include/AltPollQ.h @@ -0,0 +1,51 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef ALT_POLLED_Q_H +#define ALT_POLLED_Q_H + +void vStartAltPolledQueueTasks( unsigned portBASE_TYPE uxPriority ); +portBASE_TYPE xAreAltPollingQueuesStillRunning( void ); + +#endif + + diff --git a/20080212/Demo/Common/include/AltQTest.h b/20080212/Demo/Common/include/AltQTest.h new file mode 100644 index 000000000..50bc9d8b6 --- /dev/null +++ b/20080212/Demo/Common/include/AltQTest.h @@ -0,0 +1,52 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FAST_GEN_Q_TEST_H +#define FAST_GEN_Q_TEST_H + +void vStartAltGenericQueueTasks( unsigned portBASE_TYPE uxPriority ); +portBASE_TYPE xAreAltGenericQueueTasksStillRunning( void ); + +#endif /* GEN_Q_TEST_H */ + + + diff --git a/20080212/Demo/Common/include/BlockQ.h b/20080212/Demo/Common/include/BlockQ.h new file mode 100644 index 000000000..e6e4a2725 --- /dev/null +++ b/20080212/Demo/Common/include/BlockQ.h @@ -0,0 +1,51 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef BLOCK_Q_H +#define BLOCK_Q_H + +void vStartBlockingQueueTasks( unsigned portBASE_TYPE uxPriority ); +portBASE_TYPE xAreBlockingQueuesStillRunning( void ); + +#endif + + diff --git a/20080212/Demo/Common/include/GenQTest.h b/20080212/Demo/Common/include/GenQTest.h new file mode 100644 index 000000000..1a8818bd8 --- /dev/null +++ b/20080212/Demo/Common/include/GenQTest.h @@ -0,0 +1,52 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef GEN_Q_TEST_H +#define GEN_Q_TEST_H + +void vStartGenericQueueTasks( unsigned portBASE_TYPE uxPriority ); +portBASE_TYPE xAreGenericQueueTasksStillRunning( void ); + +#endif /* GEN_Q_TEST_H */ + + + diff --git a/20080212/Demo/Common/include/PollQ.h b/20080212/Demo/Common/include/PollQ.h new file mode 100644 index 000000000..b7f68775a --- /dev/null +++ b/20080212/Demo/Common/include/PollQ.h @@ -0,0 +1,51 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef POLLED_Q_H +#define POLLED_Q_H + +void vStartPolledQueueTasks( unsigned portBASE_TYPE uxPriority ); +portBASE_TYPE xArePollingQueuesStillRunning( void ); + +#endif + + diff --git a/20080212/Demo/Common/include/QPeek.h b/20080212/Demo/Common/include/QPeek.h new file mode 100644 index 000000000..18c9f74e7 --- /dev/null +++ b/20080212/Demo/Common/include/QPeek.h @@ -0,0 +1,52 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef Q_PEEK_TEST_H +#define Q_PEEK_TEST_H + +void vStartQueuePeekTasks( void ); +portBASE_TYPE xAreQueuePeekTasksStillRunning( void ); + +#endif /* Q_PEEK_TEST_H */ + + + diff --git a/20080212/Demo/Common/include/blocktim.h b/20080212/Demo/Common/include/blocktim.h new file mode 100644 index 000000000..809cbf9cb --- /dev/null +++ b/20080212/Demo/Common/include/blocktim.h @@ -0,0 +1,51 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef BLOCK_TIME_TEST_H +#define BLOCK_TIME_TEST_H + +void vCreateBlockTimeTasks( void ); +portBASE_TYPE xAreBlockTimeTestTasksStillRunning( void ); + +#endif + + diff --git a/20080212/Demo/Common/include/comtest.h b/20080212/Demo/Common/include/comtest.h new file mode 100644 index 000000000..63e3c3a6e --- /dev/null +++ b/20080212/Demo/Common/include/comtest.h @@ -0,0 +1,52 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef COMTEST_H +#define COMTEST_H + +void vAltStartComTestTasks( unsigned portBASE_TYPE uxPriority, unsigned portLONG ulBaudRate, unsigned portBASE_TYPE uxLED ); +void vStartComTestTasks( unsigned portBASE_TYPE uxPriority, eCOMPort ePort, eBaud eBaudRate ); +portBASE_TYPE xAreComTestTasksStillRunning( void ); +void vComTestUnsuspendTask( void ); + +#endif + diff --git a/20080212/Demo/Common/include/comtest2.h b/20080212/Demo/Common/include/comtest2.h new file mode 100644 index 000000000..a92b8ffe3 --- /dev/null +++ b/20080212/Demo/Common/include/comtest2.h @@ -0,0 +1,50 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef COMTEST_H +#define COMTEST_H + +void vAltStartComTestTasks( unsigned portBASE_TYPE uxPriority, unsigned portLONG ulBaudRate, unsigned portBASE_TYPE uxLED ); +portBASE_TYPE xAreComTestTasksStillRunning( void ); + +#endif + diff --git a/20080212/Demo/Common/include/countsem.h b/20080212/Demo/Common/include/countsem.h new file mode 100644 index 000000000..eef61e0b8 --- /dev/null +++ b/20080212/Demo/Common/include/countsem.h @@ -0,0 +1,50 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef COUNT_SEMAPHORE_TEST_H +#define COUNT_SEMAPHORE_TEST_H + +void vStartCountingSemaphoreTasks( void ); +portBASE_TYPE xAreCountingSemaphoreTasksStillRunning( void ); + +#endif + diff --git a/20080212/Demo/Common/include/crflash.h b/20080212/Demo/Common/include/crflash.h new file mode 100644 index 000000000..f536cfa91 --- /dev/null +++ b/20080212/Demo/Common/include/crflash.h @@ -0,0 +1,62 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef CRFLASH_LED_H +#define CRFLASH_LED_H + +/* + * Create the co-routines used to flash the LED's at different rates. + * + * @param uxPriority The number of 'fixed delay' co-routines to create. This + * also effects the number of LED's that will be utilised. For example, + * passing in 3 will cause LED's 0 to 2 to be utilised. + */ +void vStartFlashCoRoutines( unsigned portBASE_TYPE uxPriority ); + +/* + * Return pdPASS or pdFAIL depending on whether an error has been detected + * or not. + */ +portBASE_TYPE xAreFlashCoRoutinesStillRunning( void ); + +#endif + diff --git a/20080212/Demo/Common/include/crhook.h b/20080212/Demo/Common/include/crhook.h new file mode 100644 index 000000000..f3f027e89 --- /dev/null +++ b/20080212/Demo/Common/include/crhook.h @@ -0,0 +1,58 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef CRHOOK_H +#define CRHOOK_H + +/* + * Create the co-routines used to communicate wit the tick hook. + */ +void vStartHookCoRoutines( void ); + +/* + * Return pdPASS or pdFAIL depending on whether an error has been detected + * or not. + */ +portBASE_TYPE xAreHookCoRoutinesStillRunning( void ); + +#endif + diff --git a/20080212/Demo/Common/include/death.h b/20080212/Demo/Common/include/death.h new file mode 100644 index 000000000..81ff30255 --- /dev/null +++ b/20080212/Demo/Common/include/death.h @@ -0,0 +1,51 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef SUICIDE_TASK_H +#define SUICIDE_TASK_H + +void vCreateSuicidalTasks( unsigned portBASE_TYPE uxPriority ); +portBASE_TYPE xIsCreateTaskStillRunning( void ); + +#endif + + diff --git a/20080212/Demo/Common/include/dynamic.h b/20080212/Demo/Common/include/dynamic.h new file mode 100644 index 000000000..e7ac73132 --- /dev/null +++ b/20080212/Demo/Common/include/dynamic.h @@ -0,0 +1,51 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef DYNAMIC_MANIPULATION_H +#define DYNAMIC_MANIPULATION_H + +void vStartDynamicPriorityTasks( void ); +portBASE_TYPE xAreDynamicPriorityTasksStillRunning( void ); + +#endif + + diff --git a/20080212/Demo/Common/include/fileIO.h b/20080212/Demo/Common/include/fileIO.h new file mode 100644 index 000000000..a3af285e3 --- /dev/null +++ b/20080212/Demo/Common/include/fileIO.h @@ -0,0 +1,51 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FILE_IO_H +#define FILE_OI_H + +void vDisplayMessage( const portCHAR * const pcMessageToPrint ); +void vWriteMessageToDisk( const portCHAR * const pcMessage ); +void vWriteBufferToDisk( const portCHAR * const pcBuffer, unsigned portLONG ulBufferLength ); + +#endif + diff --git a/20080212/Demo/Common/include/flash.h b/20080212/Demo/Common/include/flash.h new file mode 100644 index 000000000..2467bcb0f --- /dev/null +++ b/20080212/Demo/Common/include/flash.h @@ -0,0 +1,49 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FLASH_LED_H +#define FLASH_LED_H + +void vStartLEDFlashTasks( unsigned portBASE_TYPE uxPriority ); + +#endif + diff --git a/20080212/Demo/Common/include/flop.h b/20080212/Demo/Common/include/flop.h new file mode 100644 index 000000000..9866347c2 --- /dev/null +++ b/20080212/Demo/Common/include/flop.h @@ -0,0 +1,51 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FLOP_TASKS_H +#define FLOP_TASKS_H + +void vStartMathTasks( unsigned portBASE_TYPE uxPriority ); +portBASE_TYPE xAreMathsTaskStillRunning( void ); + +#endif + + diff --git a/20080212/Demo/Common/include/integer.h b/20080212/Demo/Common/include/integer.h new file mode 100644 index 000000000..7b962cb21 --- /dev/null +++ b/20080212/Demo/Common/include/integer.h @@ -0,0 +1,51 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef INTEGER_TASKS_H +#define INTEGER_TASKS_H + +void vStartIntegerMathTasks( unsigned portBASE_TYPE uxPriority ); +portBASE_TYPE xAreIntegerMathsTaskStillRunning( void ); + +#endif + + diff --git a/20080212/Demo/Common/include/mevents.h b/20080212/Demo/Common/include/mevents.h new file mode 100644 index 000000000..83d8af531 --- /dev/null +++ b/20080212/Demo/Common/include/mevents.h @@ -0,0 +1,51 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef EVENTS_TEST_H +#define EVENTS_TEST_H + +void vStartMultiEventTasks( void ); +portBASE_TYPE xAreMultiEventTasksStillRunning( void ); + +#endif + + diff --git a/20080212/Demo/Common/include/partest.h b/20080212/Demo/Common/include/partest.h new file mode 100644 index 000000000..d96d0282f --- /dev/null +++ b/20080212/Demo/Common/include/partest.h @@ -0,0 +1,53 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef PARTEST_H +#define PARTEST_H + +#define partstDEFAULT_PORT_ADDRESS ( ( unsigned portSHORT ) 0x378 ) + +void vParTestInitialise( void ); +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ); +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ); + +#endif + diff --git a/20080212/Demo/Common/include/print.h b/20080212/Demo/Common/include/print.h new file mode 100644 index 000000000..4e450cf0c --- /dev/null +++ b/20080212/Demo/Common/include/print.h @@ -0,0 +1,52 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef PRINT_H +#define PRINT_H + +void vPrintInitialise( void ); +void vPrintDisplayMessage( const portCHAR * const * pcMessageToSend ); +const portCHAR *pcPrintGetNextMessage( portTickType xPrintRate ); + +#endif + + diff --git a/20080212/Demo/Common/include/recmutex.h b/20080212/Demo/Common/include/recmutex.h new file mode 100644 index 000000000..ebf6912b3 --- /dev/null +++ b/20080212/Demo/Common/include/recmutex.h @@ -0,0 +1,50 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef RECURSIVE_MUTEX_TEST_H +#define RECURSIVE_MUTEX_TEST_H + +void vStartRecursiveMutexTasks( void ); +portBASE_TYPE xAreRecursiveMutexTasksStillRunning( void ); + +#endif + diff --git a/20080212/Demo/Common/include/semtest.h b/20080212/Demo/Common/include/semtest.h new file mode 100644 index 000000000..5f08755eb --- /dev/null +++ b/20080212/Demo/Common/include/semtest.h @@ -0,0 +1,50 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef SEMAPHORE_TEST_H +#define SEMAPHORE_TEST_H + +void vStartSemaphoreTasks( unsigned portBASE_TYPE uxPriority ); +portBASE_TYPE xAreSemaphoreTasksStillRunning( void ); + +#endif + diff --git a/20080212/Demo/Common/include/serial.h b/20080212/Demo/Common/include/serial.h new file mode 100644 index 000000000..b8ddf9508 --- /dev/null +++ b/20080212/Demo/Common/include/serial.h @@ -0,0 +1,113 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef SERIAL_COMMS_H +#define SERIAL_COMMS_H + +typedef void * xComPortHandle; + +typedef enum +{ + serCOM1, + serCOM2, + serCOM3, + serCOM4, + serCOM5, + serCOM6, + serCOM7, + serCOM8 +} eCOMPort; + +typedef enum +{ + serNO_PARITY, + serODD_PARITY, + serEVEN_PARITY, + serMARK_PARITY, + serSPACE_PARITY +} eParity; + +typedef enum +{ + serSTOP_1, + serSTOP_2 +} eStopBits; + +typedef enum +{ + serBITS_5, + serBITS_6, + serBITS_7, + serBITS_8 +} eDataBits; + +typedef enum +{ + ser50, + ser75, + ser110, + ser134, + ser150, + ser200, + ser300, + ser600, + ser1200, + ser1800, + ser2400, + ser4800, + ser9600, + ser19200, + ser38400, + ser57600, + ser115200 +} eBaud; + +xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ); +xComPortHandle xSerialPortInit( eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits, unsigned portBASE_TYPE uxBufferLength ); +void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength ); +signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ); +signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ); +portBASE_TYPE xSerialWaitForSemaphore( xComPortHandle xPort ); +void vSerialClose( xComPortHandle xPort ); + +#endif + diff --git a/20080212/Demo/Cygnal/FreeRTOSConfig.h b/20080212/Demo/Cygnal/FreeRTOSConfig.h new file mode 100644 index 000000000..e49009cee --- /dev/null +++ b/20080212/Demo/Cygnal/FreeRTOSConfig.h @@ -0,0 +1,95 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include "c8051f120.h" + +/* THE VALUE FOR configSTACK_START MUST BE OBTAINED FROM THE .MEM FILE. */ +#define configSTACK_START ( 0x0e ) + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 98000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 200 - ( unsigned portSHORT ) configSTACK_START ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 6 * 1024 ) ) +#define configMAX_TASK_NAME_LEN ( 8 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 1 +#define configIDLE_SHOULD_YIELD 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + + + + + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/Cygnal/Makefile b/20080212/Demo/Cygnal/Makefile new file mode 100644 index 000000000..d5686864c --- /dev/null +++ b/20080212/Demo/Cygnal/Makefile @@ -0,0 +1,101 @@ +# FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. +# +# This file is part of the FreeRTOS.org distribution. +# +# FreeRTOS.org is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# FreeRTOS.org is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with FreeRTOS.org; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +# +# A special exception to the GPL can be applied should you wish to distribute +# a combined work that includes FreeRTOS.org, without being obliged to provide +# the source code for any proprietary components. See the licensing section +# of http://www.FreeRTOS.org for full details of how and when the exception +# can be applied. +# +# *************************************************************************** +# See http://www.FreeRTOS.org for documentation, latest information, license +# and contact details. Please ensure to read the configuration and relevant +# port sections of the online documentation. +# *************************************************************************** + + +CC=sdcc +NO_OPT=--nogcse --noinvariant --noinduction --nojtbound --noloopreverse --nolabelopt --nooverlay --peep-asm +DEBUG=--debug + +CFLAGS=--model-large -I. -I../Common/include -I../include -I../../Source/include \ + -DSDCC_CYGNAL $(DEBUG) --less-pedantic --xram-size 8448 --stack-auto \ + --no-peep --int-long-reent --float-reent + +DEMO_DIR = ../Common +SOURCE_DIR = ../../Source +PORT_DIR = ../../Source/portable/SDCC/Cygnal + +SRC = \ +ParTest/ParTest.c \ +serial/serial.c \ +$(DEMO_DIR)/Full/flash.c \ +$(DEMO_DIR)/Full/print.c \ +$(DEMO_DIR)/Minimal/integer.c \ +$(DEMO_DIR)/Minimal/PollQ.c \ +$(DEMO_DIR)/Minimal/comtest.c \ +$(DEMO_DIR)/Full/semtest.c \ +$(SOURCE_DIR)/tasks.c \ +$(SOURCE_DIR)/queue.c \ +$(SOURCE_DIR)/list.c \ +$(SOURCE_DIR)/portable/MemMang/heap_1.c \ +$(PORT_DIR)/port.c + + +# Define all object files. +OBJ = $(SRC:.c=.rel) + + + + + +###################################### +# THIS VERSION WILL ONLY BUILD FILES THAT HAVE CHANGED, BUT MAY HAVE A DANGEROUS +# COMMAND LINE. IT WORKS FINE UNDER WINDOWS, BUT I HAVE COMMENTED IT OUT IN +# CASE IT CAUSES PROBLEMS ON OTHER SYSTEMS. + +#main : main.c Makefile ../../Source/portable/SDCC/Cygnal/portmacro.h $(OBJ) +# $(CC) $(CFLAGS) main.c $(OBJ) + +#%.rel : %.c Makefile ../../Source/portable/SDCC/Cygnal/portmacro.h +# $(CC) -c $(CFLAGS) -o$< $< + + + + + +###################################### +# INSTEAD OF THE FOUR LINES ABOVE, THIS VERSION CAN BE USED BUT WILL CAUSE ALL +# FILES TO BUILD EVERY TIME. + +main : main.c Makefile ../../Source/portable/SDCC/Cygnal/portmacro.h $(OBJ) + $(CC) $(CFLAGS) main.c $(OBJ) + +%.rel : %.c Makefile ../../Source/portable/SDCC/Cygnal/portmacro.h + $(CC) -c $(CFLAGS) $< + + + + + + + + + + + diff --git a/20080212/Demo/Cygnal/ParTest/ParTest.c b/20080212/Demo/Cygnal/ParTest/ParTest.c new file mode 100644 index 000000000..207315e9e --- /dev/null +++ b/20080212/Demo/Cygnal/ParTest/ParTest.c @@ -0,0 +1,191 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ +#include + +#include "FreeRTOS.h" +#include "task.h" +#include "partest.h" + +#define partstPUSH_PULL ( ( unsigned portCHAR ) 0xff ) +#define partstALL_OUTPUTS_OFF ( ( unsigned portCHAR ) 0xff ) + +/* LED to output is dependent on how the LED's are wired. */ +#define partstOUTPUT_0 ( ( unsigned portCHAR ) 0x02 ) +#define partstOUTPUT_1 ( ( unsigned portCHAR ) 0x08 ) +#define partstOUTPUT_2 ( ( unsigned portCHAR ) 0x20 ) +#define partstOUTPUT_3 ( ( unsigned portCHAR ) 0x01 ) +#define partstOUTPUT_4 ( ( unsigned portCHAR ) 0x04 ) +#define partstOUTPUT_5 ( ( unsigned portCHAR ) 0x10 ) +#define partstOUTPUT_6 ( ( unsigned portCHAR ) 0x40 ) +#define partstOUTPUT_7 ( ( unsigned portCHAR ) 0x80 ) + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ +unsigned portCHAR ucOriginalSFRPage; + + /* Remember the SFR page before it is changed so it can get set back + before the function exits. */ + ucOriginalSFRPage = SFRPAGE; + + /* Setup the SFR page to access the config SFR's. */ + SFRPAGE = CONFIG_PAGE; + + /* Set the on board LED to push pull. */ + P3MDOUT |= partstPUSH_PULL; + + /* Return the SFR page. */ + SFRPAGE = ucOriginalSFRPage; + + P3 = partstALL_OUTPUTS_OFF; +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, portBASE_TYPE xValue ) +{ +portBASE_TYPE xError = pdFALSE; + + vTaskSuspendAll(); + { + if( xValue == pdFALSE ) + { + switch( uxLED ) + { + case 0 : P3 |= partstOUTPUT_0; + break; + case 1 : P3 |= partstOUTPUT_1; + break; + case 2 : P3 |= partstOUTPUT_2; + break; + case 3 : P3 |= partstOUTPUT_3; + break; + case 4 : P3 |= partstOUTPUT_4; + break; + case 5 : P3 |= partstOUTPUT_5; + break; + case 6 : P3 |= partstOUTPUT_6; + break; + case 7 : P3 |= partstOUTPUT_7; + break; + default : /* There are no other LED's wired in. */ + xError = pdTRUE; + break; + } + } + else + { + switch( uxLED ) + { + case 0 : P3 &= ~partstOUTPUT_0; + break; + case 1 : P3 &= ~partstOUTPUT_1; + break; + case 2 : P3 &= ~partstOUTPUT_2; + break; + case 3 : P3 &= ~partstOUTPUT_3; + break; + case 4 : P3 &= ~partstOUTPUT_4; + break; + case 5 : P3 &= ~partstOUTPUT_5; + break; + case 6 : P3 &= ~partstOUTPUT_6; + break; + case 7 : P3 &= ~partstOUTPUT_7; + break; + default : /* There are no other LED's wired in. */ + break; + } + } + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned portCHAR ucBit; +portBASE_TYPE xError = pdFALSE; + + vTaskSuspendAll(); + { + switch( uxLED ) + { + case 0 : ucBit = partstOUTPUT_0; + break; + case 1 : ucBit = partstOUTPUT_1; + break; + case 2 : ucBit = partstOUTPUT_2; + break; + case 3 : ucBit = partstOUTPUT_3; + break; + case 4 : ucBit = partstOUTPUT_4; + break; + case 5 : ucBit = partstOUTPUT_5; + break; + case 6 : ucBit = partstOUTPUT_6; + break; + case 7 : ucBit = partstOUTPUT_7; + break; + default : /* There are no other LED's wired in. */ + xError = pdTRUE; + break; + } + + if( xError != pdTRUE ) + { + if( P3 & ucBit ) + { + P3 &= ~ucBit; + } + else + { + P3 |= ucBit; + } + } + } + xTaskResumeAll(); +} + + diff --git a/20080212/Demo/Cygnal/c8051f120.h b/20080212/Demo/Cygnal/c8051f120.h new file mode 100644 index 000000000..2986ab9c7 --- /dev/null +++ b/20080212/Demo/Cygnal/c8051f120.h @@ -0,0 +1,456 @@ +/*------------------------------------------------------------------------- + Register Declarations for the Cygnal C8051F12x Processor Range + + Copyright (C) 2003 - Maarten Brock, sourceforge.brock@dse.nl + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +-------------------------------------------------------------------------*/ + +#ifndef C8051F120_H +#define C8051F120_H + + +/* BYTE Registers */ + +/* All Pages */ +sfr at 0x80 P0 ; /* PORT 0 */ +sfr at 0x81 SP ; /* STACK POINTER */ +sfr at 0x82 DPL ; /* DATA POINTER - LOW BYTE */ +sfr at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */ +sfr at 0x84 SFRPAGE ; /* SFR PAGE SELECT */ +sfr at 0x85 SFRNEXT ; /* SFR STACK NEXT PAGE */ +sfr at 0x86 SFRLAST ; /* SFR STACK LAST PAGE */ +sfr at 0x87 PCON ; /* POWER CONTROL */ +sfr at 0x90 P1 ; /* PORT 1 */ +sfr at 0xA0 P2 ; /* PORT 2 */ +sfr at 0xA8 IE ; /* INTERRUPT ENABLE */ +sfr at 0xB0 P3 ; /* PORT 3 */ +sfr at 0xB1 PSBANK ; /* FLASH BANK SELECT */ +sfr at 0xB8 IP ; /* INTERRUPT PRIORITY */ +sfr at 0xD0 PSW ; /* PROGRAM STATUS WORD */ +sfr at 0xE0 ACC ; /* ACCUMULATOR */ +sfr at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */ +sfr at 0xE7 EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */ +sfr at 0xF0 B ; /* B REGISTER */ +sfr at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */ +sfr at 0xF7 EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */ +sfr at 0xFF WDTCN ; /* WATCHDOG TIMER CONTROL */ + +/* Page 0x00 */ +sfr at 0x88 TCON ; /* TIMER CONTROL */ +sfr at 0x89 TMOD ; /* TIMER MODE */ +sfr at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */ +sfr at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */ +sfr at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */ +sfr at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */ +sfr at 0x8E CKCON ; /* TIMER 0/1 CLOCK CONTROL */ +sfr at 0x8F PSCTL ; /* FLASH WRITE/ERASE CONTROL */ +sfr at 0x91 SSTA0 ; /* UART 0 STATUS */ +sfr at 0x98 SCON0 ; /* UART 0 CONTROL */ +sfr at 0x98 SCON ; /* UART 0 CONTROL */ +sfr at 0x99 SBUF0 ; /* UART 0 BUFFER */ +sfr at 0x99 SBUF ; /* UART 0 BUFFER */ +sfr at 0x9A SPI0CFG ; /* SPI 0 CONFIGURATION */ +sfr at 0x9B SPI0DAT ; /* SPI 0 DATA */ +sfr at 0x9D SPI0CKR ; /* SPI 0 CLOCK RATE CONTROL */ +sfr at 0xA1 EMI0TC ; /* EMIF TIMING CONTROL */ +sfr at 0xA2 EMI0CN ; /* EMIF CONTROL */ +sfr at 0xA2 _XPAGE ; /* XDATA/PDATA PAGE */ +sfr at 0xA3 EMI0CF ; /* EMIF CONFIGURATION */ +sfr at 0xA9 SADDR0 ; /* UART 0 SLAVE ADDRESS */ +sfr at 0xB7 FLSCL ; /* FLASH SCALE */ +sfr at 0xB9 SADEN0 ; /* UART 0 SLAVE ADDRESS MASK */ +sfr at 0xBA AMX0CF ; /* ADC 0 MUX CONFIGURATION */ +sfr at 0xBB AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */ +sfr at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */ +sfr at 0xBE ADC0L ; /* ADC 0 DATA - LOW BYTE */ +sfr at 0xBF ADC0H ; /* ADC 0 DATA - HIGH BYTE */ +sfr at 0xC0 SMB0CN ; /* SMBUS 0 CONTROL */ +sfr at 0xC1 SMB0STA ; /* SMBUS 0 STATUS */ +sfr at 0xC2 SMB0DAT ; /* SMBUS 0 DATA */ +sfr at 0xC3 SMB0ADR ; /* SMBUS 0 SLAVE ADDRESS */ +sfr at 0xC4 ADC0GTL ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */ +sfr at 0xC5 ADC0GTH ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */ +sfr at 0xC6 ADC0LTL ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */ +sfr at 0xC7 ADC0LTH ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */ +sfr at 0xC8 TMR2CN ; /* TIMER 2 CONTROL */ +sfr at 0xC9 TMR2CF ; /* TIMER 2 CONFIGURATION */ +sfr at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */ +sfr at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */ +sfr at 0xCC TMR2L ; /* TIMER 2 - LOW BYTE */ +sfr at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */ +sfr at 0xCD TMR2H ; /* TIMER 2 - HIGH BYTE */ +sfr at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */ +sfr at 0xCF SMB0CR ; /* SMBUS 0 CLOCK RATE */ +sfr at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */ +sfr at 0xD2 DAC0L ; /* DAC 0 REGISTER - LOW BYTE */ +sfr at 0xD3 DAC0H ; /* DAC 0 REGISTER - HIGH BYTE */ +sfr at 0xD4 DAC0CN ; /* DAC 0 CONTROL */ +sfr at 0xD8 PCA0CN ; /* PCA 0 COUNTER CONTROL */ +sfr at 0xD9 PCA0MD ; /* PCA 0 COUNTER MODE */ +sfr at 0xDA PCA0CPM0 ; /* PCA 0 MODULE 0 CONTROL */ +sfr at 0xDB PCA0CPM1 ; /* PCA 0 MODULE 1 CONTROL */ +sfr at 0xDC PCA0CPM2 ; /* PCA 0 MODULE 2 CONTROL */ +sfr at 0xDD PCA0CPM3 ; /* PCA 0 MODULE 3 CONTROL */ +sfr at 0xDE PCA0CPM4 ; /* PCA 0 MODULE 4 CONTROL */ +sfr at 0xDF PCA0CPM5 ; /* PCA 0 MODULE 5 CONTROL */ +sfr at 0xE1 PCA0CPL5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - LOW BYTE */ +sfr at 0xE2 PCA0CPH5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - HIGH BYTE */ +sfr at 0xE8 ADC0CN ; /* ADC 0 CONTROL */ +sfr at 0xE9 PCA0CPL2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - LOW BYTE */ +sfr at 0xEA PCA0CPH2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - HIGH BYTE */ +sfr at 0xEB PCA0CPL3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - LOW BYTE */ +sfr at 0xEC PCA0CPH3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - HIGH BYTE */ +sfr at 0xED PCA0CPL4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - LOW BYTE */ +sfr at 0xEE PCA0CPH4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - HIGH BYTE */ +sfr at 0xEF RSTSRC ; /* RESET SOURCE */ +sfr at 0xF8 SPI0CN ; /* SPI 0 CONTROL */ +sfr at 0xF9 PCA0L ; /* PCA 0 TIMER - LOW BYTE */ +sfr at 0xFA PCA0H ; /* PCA 0 TIMER - HIGH BYTE */ +sfr at 0xFB PCA0CPL0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - LOW BYTE */ +sfr at 0xFC PCA0CPH0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - HIGH BYTE */ +sfr at 0xFD PCA0CPL1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - LOW BYTE */ +sfr at 0xFE PCA0CPH1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - HIGH BYTE */ + +/* Page 0x01 */ +sfr at 0x88 CPT0CN ; /* COMPARATOR 0 CONTROL */ +sfr at 0x89 CPT0MD ; /* COMPARATOR 0 CONFIGURATION */ +sfr at 0x98 SCON1 ; /* UART 1 CONTROL */ +sfr at 0x99 SBUF1 ; /* UART 1 BUFFER */ +sfr at 0xC8 TMR3CN ; /* TIMER 3 CONTROL */ +sfr at 0xC9 TMR3CF ; /* TIMER 3 CONFIGURATION */ +sfr at 0xCA RCAP3L ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */ +sfr at 0xCB RCAP3H ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */ +sfr at 0xCC TMR3L ; /* TIMER 3 - LOW BYTE */ +sfr at 0xCD TMR3H ; /* TIMER 3 - HIGH BYTE */ +sfr at 0xD2 DAC1L ; /* DAC 1 REGISTER - LOW BYTE */ +sfr at 0xD3 DAC1H ; /* DAC 1 REGISTER - HIGH BYTE */ +sfr at 0xD4 DAC1CN ; /* DAC 1 CONTROL */ + +/* Page 0x02 */ +sfr at 0x88 CPT1CN ; /* COMPARATOR 1 CONTROL */ +sfr at 0x89 CPT1MD ; /* COMPARATOR 1 CONFIGURATION */ +sfr at 0xBA AMX2CF ; /* ADC 2 MUX CONFIGURATION */ +sfr at 0xBB AMX2SL ; /* ADC 2 MUX CHANNEL SELECTION */ +sfr at 0xBC ADC2CF ; /* ADC 2 CONFIGURATION */ +sfr at 0xBE ADC2 ; /* ADC 2 DATA */ +sfr at 0xC4 ADC2GT ; /* ADC 2 GREATER-THAN REGISTER */ +sfr at 0xC6 ADC2LT ; /* ADC 2 LESS-THAN REGISTER */ +sfr at 0xC8 TMR4CN ; /* TIMER 4 CONTROL */ +sfr at 0xC9 TMR4CF ; /* TIMER 4 CONFIGURATION */ +sfr at 0xCA RCAP4L ; /* TIMER 4 CAPTURE REGISTER - LOW BYTE */ +sfr at 0xCB RCAP4H ; /* TIMER 4 CAPTURE REGISTER - HIGH BYTE */ +sfr at 0xCC TMR4L ; /* TIMER 4 - LOW BYTE */ +sfr at 0xCD TMR4H ; /* TIMER 4 - HIGH BYTE */ + +/* Page 0x02 */ +sfr at 0x91 MAC0BL ; /* MAC0 B Register Low Byte */ +sfr at 0x92 MAC0BH ; /* MAC0 B Register High Byte */ +sfr at 0x93 MAC0ACC0 ; /* MAC0 Accumulator Byte 0 (LSB) */ +sfr at 0x94 MAC0ACC1 ; /* MAC0 Accumulator Byte 1 */ +sfr at 0x95 MAC0ACC2 ; /* MAC0 Accumulator Byte 2 */ +sfr at 0x96 MAC0ACC3 ; /* MAC0 Accumulator Byte 3 (MSB) */ +sfr at 0x97 MAC0OVR ; /* MAC0 Accumulator Overflow */ +sfr at 0xC0 MAC0STA ; /* MAC0 Status Register */ +sfr at 0xC1 MAC0AL ; /* MAC0 A Register Low Byte */ +sfr at 0xC2 MAC0AH ; /* MAC0 A Register High Byte */ +sfr at 0xC3 MAC0CF ; /* MAC0 Configuration */ +sfr at 0xCE MAC0RNDL ; /* MAC0 Rounding Register Low Byte */ +sfr at 0xCF MAC0RNDH ; /* MAC0 Rounding Register High Byte */ + +/* Page 0x0F */ +sfr at 0x88 FLSTAT ; /* FLASH STATUS */ +sfr at 0x89 PLL0CN ; /* PLL 0 CONTROL */ +sfr at 0x8A OSCICN ; /* INTERNAL OSCILLATOR CONTROL */ +sfr at 0x8B OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */ +sfr at 0x8C OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */ +sfr at 0x8D PLL0DIV ; /* PLL 0 DIVIDER */ +sfr at 0x8E PLL0MUL ; /* PLL 0 MULTIPLIER */ +sfr at 0x8F PLL0FLT ; /* PLL 0 FILTER */ +sfr at 0x96 SFRPGCN ; /* SFR PAGE CONTROL */ +sfr at 0x97 CLKSEL ; /* SYSTEM CLOCK SELECT */ +sfr at 0x9A CCH0MA ; /* CACHE MISS ACCUMULATOR */ +sfr at 0x9C P4MDOUT ; /* PORT 4 OUTPUT MODE */ +sfr at 0x9D P5MDOUT ; /* PORT 5 OUTPUT MODE */ +sfr at 0x9E P6MDOUT ; /* PORT 6 OUTPUT MODE */ +sfr at 0x9F P7MDOUT ; /* PORT 7 OUTPUT MODE */ +sfr at 0xA1 CCH0CN ; /* CACHE CONTROL */ +sfr at 0xA2 CCH0TN ; /* CACHE TUNING REGISTER */ +sfr at 0xA3 CCH0LC ; /* CACHE LOCK */ +sfr at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE */ +sfr at 0xA5 P1MDOUT ; /* PORT 1 OUTPUT MODE */ +sfr at 0xA6 P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */ +sfr at 0xA7 P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */ +sfr at 0xAD P1MDIN ; /* PORT 1 INPUT MODE */ +sfr at 0xB7 FLACL ; /* FLASH ACCESS LIMIT */ +sfr at 0xC8 P4 ; /* PORT 4 */ +sfr at 0xD8 P5 ; /* PORT 5 */ +sfr at 0xE1 XBR0 ; /* CROSSBAR CONFIGURATION REGISTER 0 */ +sfr at 0xE2 XBR1 ; /* CROSSBAR CONFIGURATION REGISTER 1 */ +sfr at 0xE3 XBR2 ; /* CROSSBAR CONFIGURATION REGISTER 2 */ +sfr at 0xE8 ADC2CN ; /* ADC 2 CONTROL */ +sfr at 0xE8 P6 ; /* PORT 6 */ +sfr at 0xF8 P7 ; /* PORT 7 */ + + +/* BIT Registers */ + +/* P0 0x80 */ +sbit at 0x80 P0_0 ; +sbit at 0x81 P0_1 ; +sbit at 0x82 P0_2 ; +sbit at 0x83 P0_3 ; +sbit at 0x84 P0_4 ; +sbit at 0x85 P0_5 ; +sbit at 0x86 P0_6 ; +sbit at 0x87 P0_7 ; + +/* TCON 0x88 */ +sbit at 0x88 IT0 ; /* EXT. INTERRUPT 0 TYPE */ +sbit at 0x89 IE0 ; /* EXT. INTERRUPT 0 EDGE FLAG */ +sbit at 0x8A IT1 ; /* EXT. INTERRUPT 1 TYPE */ +sbit at 0x8B IE1 ; /* EXT. INTERRUPT 1 EDGE FLAG */ +sbit at 0x8C TR0 ; /* TIMER 0 ON/OFF CONTROL */ +sbit at 0x8D TF0 ; /* TIMER 0 OVERFLOW FLAG */ +sbit at 0x8E TR1 ; /* TIMER 1 ON/OFF CONTROL */ +sbit at 0x8F TF1 ; /* TIMER 1 OVERFLOW FLAG */ + +/* CPT0CN 0x88 */ +sbit at 0x88 CP0HYN0 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 0 */ +sbit at 0x89 CP0HYN1 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 1 */ +sbit at 0x8A CP0HYP0 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 0 */ +sbit at 0x8B CP0HYP1 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 1 */ +sbit at 0x8C CP0FIF ; /* COMPARATOR 0 FALLING EDGE INTERRUPT */ +sbit at 0x8D CP0RIF ; /* COMPARATOR 0 RISING EDGE INTERRUPT */ +sbit at 0x8E CP0OUT ; /* COMPARATOR 0 OUTPUT */ +sbit at 0x8F CP0EN ; /* COMPARATOR 0 ENABLE */ + +/* CPT1CN 0x88 */ +sbit at 0x88 CP1HYN0 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 0 */ +sbit at 0x89 CP1HYN1 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 1 */ +sbit at 0x8A CP1HYP0 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 0 */ +sbit at 0x8B CP1HYP1 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 1 */ +sbit at 0x8C CP1FIF ; /* COMPARATOR 1 FALLING EDGE INTERRUPT */ +sbit at 0x8D CP1RIF ; /* COMPARATOR 1 RISING EDGE INTERRUPT */ +sbit at 0x8E CP1OUT ; /* COMPARATOR 1 OUTPUT */ +sbit at 0x8F CP1EN ; /* COMPARATOR 1 ENABLE */ + +/* FLSTAT 0x88 */ +sbit at 0x88 FLHBUSY ; /* FLASH BUSY */ + +/* SCON0 0x98 */ +sbit at 0x98 RI0 ; /* UART 0 RX INTERRUPT FLAG */ +sbit at 0x98 RI ; /* UART 0 RX INTERRUPT FLAG */ +sbit at 0x99 TI0 ; /* UART 0 TX INTERRUPT FLAG */ +sbit at 0x99 TI ; /* UART 0 TX INTERRUPT FLAG */ +sbit at 0x9A RB80 ; /* UART 0 RX BIT 8 */ +sbit at 0x9B TB80 ; /* UART 0 TX BIT 8 */ +sbit at 0x9C REN0 ; /* UART 0 RX ENABLE */ +sbit at 0x9C REN ; /* UART 0 RX ENABLE */ +sbit at 0x9D SM20 ; /* UART 0 MULTIPROCESSOR EN */ +sbit at 0x9E SM10 ; /* UART 0 MODE 1 */ +sbit at 0x9F SM00 ; /* UART 0 MODE 0 */ + +/* SCON1 0x98 */ +sbit at 0x98 RI1 ; /* UART 1 RX INTERRUPT FLAG */ +sbit at 0x99 TI1 ; /* UART 1 TX INTERRUPT FLAG */ +sbit at 0x9A RB81 ; /* UART 1 RX BIT 8 */ +sbit at 0x9B TB81 ; /* UART 1 TX BIT 8 */ +sbit at 0x9C REN1 ; /* UART 1 RX ENABLE */ +sbit at 0x9D MCE1 ; /* UART 1 MCE */ +sbit at 0x9F S1MODE ; /* UART 1 MODE */ + +/* IE 0xA8 */ +sbit at 0xA8 EX0 ; /* EXTERNAL INTERRUPT 0 ENABLE */ +sbit at 0xA9 ET0 ; /* TIMER 0 INTERRUPT ENABLE */ +sbit at 0xAA EX1 ; /* EXTERNAL INTERRUPT 1 ENABLE */ +sbit at 0xAB ET1 ; /* TIMER 1 INTERRUPT ENABLE */ +sbit at 0xAC ES0 ; /* UART0 INTERRUPT ENABLE */ +sbit at 0xAC ES ; /* UART0 INTERRUPT ENABLE */ +sbit at 0xAD ET2 ; /* TIMER 2 INTERRUPT ENABLE */ +sbit at 0xAF EA ; /* GLOBAL INTERRUPT ENABLE */ + +/* IP 0xB8 */ +sbit at 0xB8 PX0 ; /* EXTERNAL INTERRUPT 0 PRIORITY */ +sbit at 0xB9 PT0 ; /* TIMER 0 PRIORITY */ +sbit at 0xBA PX1 ; /* EXTERNAL INTERRUPT 1 PRIORITY */ +sbit at 0xBB PT1 ; /* TIMER 1 PRIORITY */ +sbit at 0xBC PS ; /* SERIAL PORT PRIORITY */ +sbit at 0xBD PT2 ; /* TIMER 2 PRIORITY */ + +/* SMB0CN 0xC0 */ +sbit at 0xC0 SMBTOE ; /* SMBUS 0 TIMEOUT ENABLE */ +sbit at 0xC1 SMBFTE ; /* SMBUS 0 FREE TIMER ENABLE */ +sbit at 0xC2 AA ; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */ +sbit at 0xC3 SI ; /* SMBUS 0 INTERRUPT PENDING FLAG */ +sbit at 0xC4 STO ; /* SMBUS 0 STOP FLAG */ +sbit at 0xC5 STA ; /* SMBUS 0 START FLAG */ +sbit at 0xC6 ENSMB ; /* SMBUS 0 ENABLE */ +sbit at 0xC7 BUSY ; /* SMBUS 0 BUSY */ + +/* TMR2CN 0xC8 */ +sbit at 0xC8 CPRL2 ; /* TIMER 2 CAPTURE SELECT */ +sbit at 0xC9 CT2 ; /* TIMER 2 COUNTER SELECT */ +sbit at 0xCA TR2 ; /* TIMER 2 ON/OFF CONTROL */ +sbit at 0xCB EXEN2 ; /* TIMER 2 EXTERNAL ENABLE FLAG */ +sbit at 0xCE EXF2 ; /* TIMER 2 EXTERNAL FLAG */ +sbit at 0xCF TF2 ; /* TIMER 2 OVERFLOW FLAG */ + +/* TMR3CN 0xC8 */ +sbit at 0xC8 CPRL3 ; /* TIMER 3 CAPTURE SELECT */ +sbit at 0xC9 CT3 ; /* TIMER 3 COUNTER SELECT */ +sbit at 0xCA TR3 ; /* TIMER 3 ON/OFF CONTROL */ +sbit at 0xCB EXEN3 ; /* TIMER 3 EXTERNAL ENABLE FLAG */ +sbit at 0xCE EXF3 ; /* TIMER 3 EXTERNAL FLAG */ +sbit at 0xCF TF3 ; /* TIMER 3 OVERFLOW FLAG */ + +/* TMR4CN 0xC8 */ +sbit at 0xC8 CPRL4 ; /* TIMER 4 CAPTURE SELECT */ +sbit at 0xC9 CT4 ; /* TIMER 4 COUNTER SELECT */ +sbit at 0xCA TR4 ; /* TIMER 4 ON/OFF CONTROL */ +sbit at 0xCB EXEN4 ; /* TIMER 4 EXTERNAL ENABLE FLAG */ +sbit at 0xCE EXF4 ; /* TIMER 4 EXTERNAL FLAG */ +sbit at 0xCF TF4 ; /* TIMER 4 OVERFLOW FLAG */ + +/* P4 0xC8 */ +sbit at 0xC8 P4_0 ; +sbit at 0xC9 P4_1 ; +sbit at 0xCA P4_2 ; +sbit at 0xCB P4_3 ; +sbit at 0xCC P4_4 ; +sbit at 0xCD P4_5 ; +sbit at 0xCE P4_6 ; +sbit at 0xCF P4_7 ; + +/* PSW 0xD0 */ +sbit at 0xD0 P ; /* ACCUMULATOR PARITY FLAG */ +sbit at 0xD1 F1 ; /* USER FLAG 1 */ +sbit at 0xD2 OV ; /* OVERFLOW FLAG */ +sbit at 0xD3 RS0 ; /* REGISTER BANK SELECT 0 */ +sbit at 0xD4 RS1 ; /* REGISTER BANK SELECT 1 */ +sbit at 0xD5 F0 ; /* USER FLAG 0 */ +sbit at 0xD6 AC ; /* AUXILIARY CARRY FLAG */ +sbit at 0xD7 CY ; /* CARRY FLAG */ + +/* PCA0CN D8H */ +sbit at 0xD8 CCF0 ; /* PCA 0 MODULE 0 INTERRUPT FLAG */ +sbit at 0xD9 CCF1 ; /* PCA 0 MODULE 1 INTERRUPT FLAG */ +sbit at 0xDA CCF2 ; /* PCA 0 MODULE 2 INTERRUPT FLAG */ +sbit at 0xDB CCF3 ; /* PCA 0 MODULE 3 INTERRUPT FLAG */ +sbit at 0xDC CCF4 ; /* PCA 0 MODULE 4 INTERRUPT FLAG */ +sbit at 0xDD CCF5 ; /* PCA 0 MODULE 5 INTERRUPT FLAG */ +sbit at 0xDE CR ; /* PCA 0 COUNTER RUN CONTROL BIT */ +sbit at 0xDF CF ; /* PCA 0 COUNTER OVERFLOW FLAG */ + +/* P5 0xD8 */ +sbit at 0xD8 P5_0 ; +sbit at 0xD9 P5_1 ; +sbit at 0xDA P5_2 ; +sbit at 0xDB P5_3 ; +sbit at 0xDC P5_4 ; +sbit at 0xDD P5_5 ; +sbit at 0xDE P5_6 ; +sbit at 0xDF P5_7 ; + +/* ADC0CN E8H */ +sbit at 0xE8 AD0LJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */ +sbit at 0xE9 AD0WINT ; /* ADC 0 WINDOW INTERRUPT FLAG */ +sbit at 0xEA AD0CM0 ; /* ADC 0 CONVERT START MODE BIT 0 */ +sbit at 0xEB AD0CM1 ; /* ADC 0 CONVERT START MODE BIT 1 */ +sbit at 0xEC AD0BUSY ; /* ADC 0 BUSY FLAG */ +sbit at 0xED AD0INT ; /* ADC 0 EOC INTERRUPT FLAG */ +sbit at 0xEE AD0TM ; /* ADC 0 TRACK MODE */ +sbit at 0xEF AD0EN ; /* ADC 0 ENABLE */ + +/* ADC2CN E8H */ +sbit at 0xE8 AD2WINT ; /* ADC 2 WINDOW INTERRUPT FLAG */ +sbit at 0xE9 AD2CM0 ; /* ADC 2 CONVERT START MODE BIT 0 */ +sbit at 0xEA AD2CM1 ; /* ADC 2 CONVERT START MODE BIT 1 */ +sbit at 0xEB AD2CM2 ; /* ADC 2 CONVERT START MODE BIT 2 */ +sbit at 0xEC AD2BUSY ; /* ADC 2 BUSY FLAG */ +sbit at 0xED AD2INT ; /* ADC 2 EOC INTERRUPT FLAG */ +sbit at 0xEE AD2TM ; /* ADC 2 TRACK MODE */ +sbit at 0xEF AD2EN ; /* ADC 2 ENABLE */ + +/* P6 0xE8 */ +sbit at 0xE8 P6_0 ; +sbit at 0xE9 P6_1 ; +sbit at 0xEA P6_2 ; +sbit at 0xEB P6_3 ; +sbit at 0xEC P6_4 ; +sbit at 0xED P6_5 ; +sbit at 0xEE P6_6 ; +sbit at 0xEF P6_7 ; + +/* SPI0CN F8H */ +sbit at 0xF8 SPIEN ; /* SPI 0 SPI ENABLE */ +sbit at 0xF9 TXBMT ; /* SPI 0 TX BUFFER EMPTY FLAG */ +sbit at 0xFA NSSMD0 ; /* SPI 0 SLAVE SELECT MODE 0 */ +sbit at 0xFB NSSMD1 ; /* SPI 0 SLAVE SELECT MODE 1 */ +sbit at 0xFC RXOVRN ; /* SPI 0 RX OVERRUN FLAG */ +sbit at 0xFD MODF ; /* SPI 0 MODE FAULT FLAG */ +sbit at 0xFE WCOL ; /* SPI 0 WRITE COLLISION FLAG */ +sbit at 0xFF SPIF ; /* SPI 0 INTERRUPT FLAG */ + +/* P7 0xF8 */ +sbit at 0xF8 P7_0 ; +sbit at 0xF9 P7_1 ; +sbit at 0xFA P7_2 ; +sbit at 0xFB P7_3 ; +sbit at 0xFC P7_4 ; +sbit at 0xFD P7_5 ; +sbit at 0xFE P7_6 ; +sbit at 0xFF P7_7 ; + + +/* Predefined SFR Bit Masks */ + +#define IDLE 0x01 /* PCON */ +#define STOP 0x02 /* PCON */ +#define ECCF 0x01 /* PCA0CPMn */ +#define PWM 0x02 /* PCA0CPMn */ +#define TOG 0x04 /* PCA0CPMn */ +#define MAT 0x08 /* PCA0CPMn */ +#define CAPN 0x10 /* PCA0CPMn */ +#define CAPP 0x20 /* PCA0CPMn */ +#define ECOM 0x40 /* PCA0CPMn */ +#define PWM16 0x80 /* PCA0CPMn */ +#define PORSF 0x02 /* RSTSRC */ +#define SWRSF 0x10 /* RSTSRC */ + + +/* SFR PAGE DEFINITIONS */ + +#define CONFIG_PAGE 0x0F /* SYSTEM AND PORT CONFIGURATION PAGE */ +#define LEGACY_PAGE 0x00 /* LEGACY SFR PAGE */ +#define TIMER01_PAGE 0x00 /* TIMER 0 AND TIMER 1 */ +#define CPT0_PAGE 0x01 /* COMPARATOR 0 */ +#define CPT1_PAGE 0x02 /* COMPARATOR 1 */ +#define UART0_PAGE 0x00 /* UART 0 */ +#define UART1_PAGE 0x01 /* UART 1 */ +#define SPI0_PAGE 0x00 /* SPI 0 */ +#define EMI0_PAGE 0x00 /* EXTERNAL MEMORY INTERFACE */ +#define ADC0_PAGE 0x00 /* ADC 0 */ +#define ADC2_PAGE 0x02 /* ADC 2 */ +#define SMB0_PAGE 0x00 /* SMBUS 0 */ +#define TMR2_PAGE 0x00 /* TIMER 2 */ +#define TMR3_PAGE 0x01 /* TIMER 3 */ +#define TMR4_PAGE 0x02 /* TIMER 4 */ +#define DAC0_PAGE 0x00 /* DAC 0 */ +#define DAC1_PAGE 0x01 /* DAC 1 */ +#define PCA0_PAGE 0x00 /* PCA 0 */ +#define PLL0_PAGE 0x0F /* PLL 0 */ + +#endif diff --git a/20080212/Demo/Cygnal/main.c b/20080212/Demo/Cygnal/main.c new file mode 100644 index 000000000..f2af3a718 --- /dev/null +++ b/20080212/Demo/Cygnal/main.c @@ -0,0 +1,573 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + * Creates the demo application tasks, then starts the scheduler. The WEB + * documentation provides more details of the demo application tasks. + * + * Main. c also creates four other tasks: + * + * 1) vErrorChecks() + * This only executes every few seconds but has the highest priority so is + * guaranteed to get processor time. Its main function is to check that all + * the standard demo application tasks are still operational and have not + * experienced any errors. vErrorChecks() will toggle the on board LED + * every mainNO_ERROR_FLASH_PERIOD milliseconds if none of the demo application + * tasks have reported an error. Should any task report an error at any time + * the rate at which the on board LED is toggled is increased to + * mainERROR_FLASH_PERIOD - providing visual feedback that something has gone + * wrong. + * + * 2) vRegisterCheck() + * This is a very simple task that checks that all the registers are always + * in their expected state. The task only makes use of the A register, so + * all the other registers should always contain their initial values. + * An incorrect value indicates an error in the context switch mechanism. + * The task operates at the idle priority so will be preempted regularly. + * Any error will cause the toggle rate of the on board LED to increase to + * mainERROR_FLASH_PERIOD milliseconds. + * + * 3 and 4) vFLOPCheck1() and vFLOPCheck2() + * These are very basic versions of the standard FLOP tasks. They are good + * at detecting errors in the context switch mechanism, and also check that + * the floating point libraries are correctly built to be re-enterant. The + * stack restrictions of the 8051 prevent the use of the standard FLOP demo + * tasks. + */ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo application includes. */ +#include "partest.h" +#include "flash.h" +#include "integer.h" +#include "PollQ.h" +#include "comtest2.h" +#include "semtest.h" + +/* Demo task priorities. */ +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainINTEGER_PRIORITY tskIDLE_PRIORITY + +/* Constants required to disable the watchdog. */ +#define mainDISABLE_BYTE_1 ( ( unsigned portCHAR ) 0xde ) +#define mainDISABLE_BYTE_2 ( ( unsigned portCHAR ) 0xad ) + +/* Constants to setup and use the on board LED. */ +#define ucLED_BIT ( ( unsigned portCHAR ) 0x40 ) +#define mainPORT_1_BIT_6 ( ( unsigned portCHAR ) 0x40 ) +#define mainENABLE_CROSS_BAR ( ( unsigned portCHAR ) 0x40 ) + +/* Constants to set the clock frequency. */ +#define mainSELECT_INTERNAL_OSC ( ( unsigned portCHAR ) 0x80 ) +#define mainDIVIDE_CLOCK_BY_1 ( ( unsigned portCHAR ) 0x03 ) +#define mainPLL_USES_INTERNAL_OSC ( ( unsigned portCHAR ) 0x04 ) +#define mainFLASH_READ_TIMING ( ( unsigned portCHAR ) 0x30 ) +#define mainPLL_POWER_ON ( ( unsigned portCHAR ) 0x01 ) +#define mainPLL_NO_PREDIVIDE ( ( unsigned portCHAR ) 0x01 ) +#define mainPLL_FILTER ( ( unsigned portCHAR ) 0x01 ) +#define mainPLL_MULTIPLICATION ( ( unsigned portCHAR ) 0x04 ) +#define mainENABLE_PLL ( ( unsigned portCHAR ) 0x02 ) +#define mainPLL_LOCKED ( ( unsigned portCHAR ) 0x10 ) +#define mainSELECT_PLL_AS_SOURCE ( ( unsigned portCHAR ) 0x02 ) + +/* Toggle rate for the on board LED - which is dependent on whether or not +an error has been detected. */ +#define mainNO_ERROR_FLASH_PERIOD ( ( portTickType ) 5000 ) +#define mainERROR_FLASH_PERIOD ( ( portTickType ) 250 ) + +/* Baud rate used by the serial port tasks. */ +#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 115200 ) + +/* Pass an invalid LED number to the COM test task as we don't want it to flash +an LED. There are only 8 LEDs (excluding the on board LED) wired in and these +are all used by the flash tasks. */ +#define mainCOM_TEST_LED ( 200 ) + +/* We want the Cygnal to act as much as possible as a standard 8052. */ +#define mainAUTO_SFR_OFF ( ( unsigned portCHAR ) 0 ) + +/* Constants required to setup the IO pins for serial comms. */ +#define mainENABLE_COMS ( ( unsigned portCHAR ) 0x04 ) +#define mainCOMS_LINES_TO_PUSH_PULL ( ( unsigned portCHAR ) 0x03 ) + +/* Pointer passed as a parameter to vRegisterCheck() just so it has some know +values to check for in the DPH, DPL and B registers. */ +#define mainDUMMY_POINTER ( ( xdata void * ) 0xabcd ) + +/* Macro that lets vErrorChecks() know that one of the tasks defined in +main. c has detected an error. A critical region is used around xLatchError +as it is accessed from vErrorChecks(), which has a higher priority. */ +#define mainLATCH_ERROR() \ +{ \ + portENTER_CRITICAL(); \ + xLatchedError = pdTRUE; \ + portEXIT_CRITICAL(); \ +} + +/* + * Setup the Cygnal microcontroller for its fastest operation. + */ +static void prvSetupSystemClock( void ); + +/* + * Setup the peripherals, including the on board LED. + */ +static void prvSetupHardware( void ); + +/* + * Toggle the state of the on board LED. + */ +static void prvToggleOnBoardLED( void ); + +/* + * See comments at the top of the file for details. + */ +static void vErrorChecks( void *pvParameters ); + +/* + * See comments at the top of the file for details. + */ +static void vRegisterCheck( void *pvParameters ); + +/* + * See comments at the top of the file for details. + */ +static void vFLOPCheck1( void *pvParameters ); + +/* + * See comments at the top of the file for details. + */ +static void vFLOPCheck2( void *pvParameters ); + +/* File scope variable used to communicate the occurrence of an error between +tasks. */ +static portBASE_TYPE xLatchedError = pdFALSE; + +/*-----------------------------------------------------------*/ + +/* + * Starts all the other tasks, then starts the scheduler. + */ +void main( void ) +{ + /* Initialise the hardware including the system clock and on board + LED. */ + prvSetupHardware(); + + /* Initialise the port that controls the external LED's utilized by the + flash tasks. */ + vParTestInitialise(); + + /* Start the used standard demo tasks. */ + vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartIntegerMathTasks( mainINTEGER_PRIORITY ); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + + /* Start the tasks defined in this file. The first three never block so + must not be used with the co-operative scheduler. */ + #if configUSE_PREEMPTION == 1 + { + xTaskCreate( vRegisterCheck, "RegChck", configMINIMAL_STACK_SIZE, mainDUMMY_POINTER, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL ); + xTaskCreate( vFLOPCheck1, "FLOP", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL ); + xTaskCreate( vFLOPCheck2, "FLOP", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL ); + } + #endif + + xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, ( xTaskHandle * ) NULL ); + + /* Finally kick off the scheduler. This function should never return. */ + vTaskStartScheduler(); + + /* Should never reach here as the tasks will now be executing under control + of the scheduler. */ +} +/*-----------------------------------------------------------*/ + +/* + * Setup the hardware prior to using the scheduler. Most of the Cygnal + * specific initialisation is performed here leaving standard 8052 setup + * only in the driver code. + */ +static void prvSetupHardware( void ) +{ +unsigned portCHAR ucOriginalSFRPage; + + /* Remember the SFR page before it is changed so it can get set back + before the function exits. */ + ucOriginalSFRPage = SFRPAGE; + + /* Setup the SFR page to access the config SFR's. */ + SFRPAGE = CONFIG_PAGE; + + /* Don't allow the microcontroller to automatically switch SFR page, as the + SFR page is not stored as part of the task context. */ + SFRPGCN = mainAUTO_SFR_OFF; + + /* Disable the watchdog. */ + WDTCN = mainDISABLE_BYTE_1; + WDTCN = mainDISABLE_BYTE_2; + + /* Set the on board LED to push pull. */ + P1MDOUT |= mainPORT_1_BIT_6; + + /* Setup the cross bar to enable serial comms here as it is not part of the + standard 8051 setup and therefore is not in the driver code. */ + XBR0 |= mainENABLE_COMS; + P0MDOUT |= mainCOMS_LINES_TO_PUSH_PULL; + + /* Enable the cross bar so our hardware setup takes effect. */ + XBR2 = mainENABLE_CROSS_BAR; + + /* Setup a fast system clock. */ + prvSetupSystemClock(); + + /* Return the SFR page. */ + SFRPAGE = ucOriginalSFRPage; +} +/*-----------------------------------------------------------*/ + +static void prvSetupSystemClock( void ) +{ +volatile unsigned portSHORT usWait; +const unsigned portSHORT usWaitTime = ( unsigned portSHORT ) 0x2ff; +unsigned portCHAR ucOriginalSFRPage; + + /* Remember the SFR page so we can set it back at the end. */ + ucOriginalSFRPage = SFRPAGE; + SFRPAGE = CONFIG_PAGE; + + /* Use the internal oscillator set to its fasted frequency. */ + OSCICN = mainSELECT_INTERNAL_OSC | mainDIVIDE_CLOCK_BY_1; + + /* Ensure the clock is stable. */ + for( usWait = 0; usWait < usWaitTime; usWait++ ); + + /* Setup the clock source for the PLL. */ + PLL0CN &= ~mainPLL_USES_INTERNAL_OSC; + + /* Change the read timing for the flash ready for the fast clock. */ + SFRPAGE = LEGACY_PAGE; + FLSCL |= mainFLASH_READ_TIMING; + + /* Turn on the PLL power. */ + SFRPAGE = CONFIG_PAGE; + PLL0CN |= mainPLL_POWER_ON; + + /* Don't predivide the clock. */ + PLL0DIV = mainPLL_NO_PREDIVIDE; + + /* Set filter for fastest clock. */ + PLL0FLT = mainPLL_FILTER; + PLL0MUL = mainPLL_MULTIPLICATION; + + /* Ensure the clock is stable. */ + for( usWait = 0; usWait < usWaitTime; usWait++ ); + + /* Enable the PLL and wait for it to lock. */ + PLL0CN |= mainENABLE_PLL; + for( usWait = 0; usWait < usWaitTime; usWait++ ) + { + if( PLL0CN & mainPLL_LOCKED ) + { + break; + } + } + + /* Select the PLL as the clock source. */ + CLKSEL |= mainSELECT_PLL_AS_SOURCE; + + /* Return the SFR back to its original value. */ + SFRPAGE = ucOriginalSFRPage; +} +/*-----------------------------------------------------------*/ + +static void prvToggleOnBoardLED( void ) +{ + /* If the on board LED is on, turn it off and visa versa. */ + if( P1 & ucLED_BIT ) + { + P1 &= ~ucLED_BIT; + } + else + { + P1 |= ucLED_BIT; + } +} +/*-----------------------------------------------------------*/ + +/* + * See the documentation at the top of this file. + */ +static void vErrorChecks( void *pvParameters ) +{ +portBASE_TYPE xErrorHasOccurred = pdFALSE; + + /* Just to prevent compiler warnings. */ + ( void ) pvParameters; + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. The delay period depends on whether an error + has ever been detected. */ + for( ;; ) + { + if( xLatchedError == pdFALSE ) + { + /* No errors have been detected so delay for a longer period. The + on board LED will get toggled every mainNO_ERROR_FLASH_PERIOD ms. */ + vTaskDelay( mainNO_ERROR_FLASH_PERIOD ); + } + else + { + /* We have at some time recognised an error in one of the demo + application tasks, delay for a shorter period. The on board LED + will get toggled every mainERROR_FLASH_PERIOD ms. */ + vTaskDelay( mainERROR_FLASH_PERIOD ); + } + + + + /* Check the demo application tasks for errors. */ + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + /* If an error has occurred, latch it to cause the LED flash rate to + increase. */ + if( xErrorHasOccurred == pdTRUE ) + { + xLatchedError = pdTRUE; + } + + /* Toggle the LED to indicate the completion of a check cycle. The + frequency of check cycles is dependent on whether or not we have + latched an error. */ + prvToggleOnBoardLED(); + } +} +/*-----------------------------------------------------------*/ + +/* + * See the documentation at the top of this file. Also see the standard FLOP + * demo task documentation for the rationale of these tasks. + */ +static void vFLOPCheck1( void *pvParameters ) +{ +volatile portFLOAT fVal1, fVal2, fResult; + + ( void ) pvParameters; + + for( ;; ) + { + fVal1 = ( portFLOAT ) -1234.5678; + fVal2 = ( portFLOAT ) 2345.6789; + + fResult = fVal1 + fVal2; + if( ( fResult > ( portFLOAT ) 1111.15 ) || ( fResult < ( portFLOAT ) 1111.05 ) ) + { + mainLATCH_ERROR(); + } + + fResult = fVal1 / fVal2; + if( ( fResult > ( portFLOAT ) -0.51 ) || ( fResult < ( portFLOAT ) -0.53 ) ) + { + mainLATCH_ERROR(); + } + } +} +/*-----------------------------------------------------------*/ + +/* + * See the documentation at the top of this file. + */ +static void vFLOPCheck2( void *pvParameters ) +{ +volatile portFLOAT fVal1, fVal2, fResult; + + ( void ) pvParameters; + + for( ;; ) + { + fVal1 = ( portFLOAT ) -12340.5678; + fVal2 = ( portFLOAT ) 23450.6789; + + fResult = fVal1 + fVal2; + if( ( fResult > ( portFLOAT ) 11110.15 ) || ( fResult < ( portFLOAT ) 11110.05 ) ) + { + mainLATCH_ERROR(); + } + + fResult = fVal1 / -fVal2; + if( ( fResult > ( portFLOAT ) 0.53 ) || ( fResult < ( portFLOAT ) 0.51 ) ) + { + mainLATCH_ERROR(); + } + } +} +/*-----------------------------------------------------------*/ + +/* + * See the documentation at the top of this file. + */ +static void vRegisterCheck( void *pvParameters ) +{ + ( void ) pvParameters; + + for( ;; ) + { + if( SP != configSTACK_START ) + { + mainLATCH_ERROR(); + } + + _asm + MOV ACC, ar0 + _endasm; + + if( ACC != 0 ) + { + mainLATCH_ERROR(); + } + + _asm + MOV ACC, ar1 + _endasm; + + if( ACC != 1 ) + { + mainLATCH_ERROR(); + } + _asm + MOV ACC, ar2 + _endasm; + + if( ACC != 2 ) + { + mainLATCH_ERROR(); + } + _asm + MOV ACC, ar3 + _endasm; + + if( ACC != 3 ) + { + mainLATCH_ERROR(); + } + _asm + MOV ACC, ar4 + _endasm; + + if( ACC != 4 ) + { + mainLATCH_ERROR(); + } + _asm + MOV ACC, ar5 + _endasm; + + if( ACC != 5 ) + { + mainLATCH_ERROR(); + } + _asm + MOV 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+[WorkState_v1_1.Frames.ChildFrames] +ptn_Child1=Document-0 +[WorkState_v1_1.Frames.ChildFrames.Document-0] +ptn_Child1=ViewFrame-0 +[WorkState_v1_1.Frames.ChildFrames.Document-0.ViewFrame-0] +DocPathName=E:\Dev\FreeRTOS\Demo\Cygnal\main.c +DocumentString=ide Document +DocTemplateIndex=0 +WindowPlacement=MCAAAAAAAAAAAAAABAAAAAAAPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPGDAAAAAAGDAAAAAAMPDAAAAAIFCAAAAA +IsActiveChildFrame=True +[WorkState_v1_1.ProjectTarget] +ProjectTarget=SC88F000 +[WorkState_v1_1.WorkSpaceName] +WorkSpaceName=E:\Dev\FreeRTOS\Demo\Cygnal\sdcc.wsp +[WorkState_v1_1.SerialPort] +SerialPort=1 +[WorkState_v1_1.StepInc] +StepInc=0 +[WorkState_v1_1.DisassemblyAutoView] +DisassemblyAutoView=0 +[WorkState_v1_1.Watch0Base] +Watch0Base=1 +[WorkState_v1_1.Watch1Base] +Watch1Base=1 +[WorkState_v1_1.Vendor] +Vendor=3 +[WorkState_v1_1.Assembler] +Assembler=D:\devtools\Cygnal\IDEfiles\C51\BIN\a51.exe +[WorkState_v1_1.AssFlag] +AssFlag=-f -i -s +[WorkState_v1_1.AssFormat] +AssFormat= +[WorkState_v1_1.Compiler] +Compiler=D:\devtools\Cygnal\IDEfiles\C51\BIN\C51.exe +[WorkState_v1_1.CompFlag] +CompFlag=-c -l -s m=3 +[WorkState_v1_1.CompFormat] +CompFormat= +[WorkState_v1_1.RunOptimizer] +RunOptimizer=0 +[WorkState_v1_1.Linker] +Linker=D:\devtools\Cygnal\IDEfiles\C51\BIN\bl51.exe +[WorkState_v1_1.LinkFlag] +LinkFlag=i=\mc\lib51\medium.lib -l l=\mc\lib51 -s +[WorkState_v1_1.LinkFormat] +LinkFormat= +[WorkState_v1_1.PreprocFlag] +PreprocFlag=-c -l +[WorkState_v1_1.PreprocFormat] +PreprocFormat= +[WorkState_v1_1.DisList] +DisList=1 +[WorkState_v1_1.DisOP] +DisOP=1 +[WorkState_v1_1.ParseErr] +ParseErr=1 +[WorkState_v1_1.Download] +Download=0 +[WorkState_v1_1.AutoSave] +AutoSave=1 +[WorkState_v1_1.UseMake] +UseMake=1 +[WorkState_v1_1.ErrorFormat] +ErrorFormat=CS CS CS CS CS LN +[WorkState_v1_1.ErrorString] +ErrorString=%s %s %s %s %s %d +[WorkState_v1_1.MultiDeviceJTAG] +DevicesAfterTarget=0 +DevicesBeforeTarget=0 +BitsAfterTargetIR=0 +BitsBeforeTargetIR=0 +[WorkState_v1_1.BankingPN] +BankingPN=32767 +[WorkState_v1_1.OutputFile] +OutputFile=main. +[WorkState_v1_1.MakeFile] +MakeFile= +[WorkState_v1_1.CExt] +CExt=.obj +[WorkState_v1_1.IDEVer] +IDEVer=2.3 +[WorkState_v1_1.ECProtocol] +ECProtocol=0 +[WorkState_v1_1.Adapter] +Adapter=2 +[WorkState_v1_1.PFiles] +[WorkState_v1_1.AFiles] +[WorkState_v1_1.CFiles] +[WorkState_v1_1.LFiles] +[WorkState_v1_1.BankMap] +[WorkState_v1_1.Folders] +ptn_Child1=FolderName +[WorkState_v1_1.Folders.FolderName] +FolderName=Demo App Files +ptn_Child1=FolderName +[WorkState_v1_1.Folders.FolderName.FolderName] +FolderName=FreeRTOS Files +[WorkState_v1_1.Demo App Files] +ptn_Child1=FileName +[WorkState_v1_1.Demo App Files.FileName] +FileName=main.c +ptn_Child1=FileName +[WorkState_v1_1.Demo App Files.FileName.FileName] +FileName=serial\serial.c +ptn_Child1=FileName +[WorkState_v1_1.Demo App Files.FileName.FileName.FileName] +FileName=ParTest\ParTest.c +ptn_Child1=FileName +[WorkState_v1_1.Demo App Files.FileName.FileName.FileName.FileName] +FileName=E:\Dev\FreeRTOS\Demo\Common\Full\semtest.c +ptn_Child1=FileName +[WorkState_v1_1.Demo App Files.FileName.FileName.FileName.FileName.FileName] +FileName=E:\Dev\FreeRTOS\Demo\Common\Full\print.c +ptn_Child1=FileName +[WorkState_v1_1.Demo App Files.FileName.FileName.FileName.FileName.FileName.FileName] +FileName=E:\Dev\FreeRTOS\Demo\Common\Full\flash.c +ptn_Child1=FileName +[WorkState_v1_1.Demo App Files.FileName.FileName.FileName.FileName.FileName.FileName.FileName] +FileName=E:\Dev\FreeRTOS\Demo\Common\Minimal\comtest.c +ptn_Child1=FileName +[WorkState_v1_1.Demo App Files.FileName.FileName.FileName.FileName.FileName.FileName.FileName.FileName] +FileName=E:\Dev\FreeRTOS\Demo\Common\Minimal\integer.c +ptn_Child1=FileName +[WorkState_v1_1.Demo App Files.FileName.FileName.FileName.FileName.FileName.FileName.FileName.FileName.FileName] +FileName=E:\Dev\FreeRTOS\Demo\Common\Minimal\PollQ.c +[WorkState_v1_1.FreeRTOS Files] +ptn_Child1=FileName +[WorkState_v1_1.FreeRTOS Files.FileName] +FileName=E:\Dev\FreeRTOS\Source\tasks.c +ptn_Child1=FileName +[WorkState_v1_1.FreeRTOS Files.FileName.FileName] +FileName=E:\Dev\FreeRTOS\Source\queue.c +ptn_Child1=FileName +[WorkState_v1_1.FreeRTOS Files.FileName.FileName.FileName] +FileName=E:\Dev\FreeRTOS\Source\list.c +ptn_Child1=FileName +[WorkState_v1_1.FreeRTOS Files.FileName.FileName.FileName.FileName] +FileName=E:\Dev\FreeRTOS\Source\portable\MemMang\heap_1.c +ptn_Child1=FileName +[WorkState_v1_1.FreeRTOS Files.FileName.FileName.FileName.FileName.FileName] +FileName=E:\Dev\FreeRTOS\Source\portable\SDCC\Cygnal\port.c diff --git a/20080212/Demo/Cygnal/serial/serial.c b/20080212/Demo/Cygnal/serial/serial.c new file mode 100644 index 000000000..7a152ab29 --- /dev/null +++ b/20080212/Demo/Cygnal/serial/serial.c @@ -0,0 +1,225 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR DEMO PURPOSES */ +#include +#include "FreeRTOS.h" +#include "queue.h" +#include "task.h" +#include "serial.h" + +/* Constants required to setup the serial control register. */ +#define ser8_BIT_MODE ( ( unsigned portCHAR ) 0x40 ) +#define serRX_ENABLE ( ( unsigned portCHAR ) 0x10 ) + +/* Constants to setup the timer used to generate the baud rate. */ +#define serCLOCK_DIV_48 ( ( unsigned portCHAR ) 0x03 ) +#define serUSE_PRESCALED_CLOCK ( ( unsigned portCHAR ) 0x10 ) +#define ser8BIT_WITH_RELOAD ( ( unsigned portCHAR ) 0x20 ) +#define serSMOD ( ( unsigned portCHAR ) 0x10 ) + +static xQueueHandle xRxedChars; +static xQueueHandle xCharsForTx; + +data static unsigned portBASE_TYPE uxTxEmpty; + +/*-----------------------------------------------------------*/ + +xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) +{ +unsigned portLONG ulReloadValue; +const portFLOAT fBaudConst = ( portFLOAT ) configCPU_CLOCK_HZ * ( portFLOAT ) 2.0; +unsigned portCHAR ucOriginalSFRPage; + + portENTER_CRITICAL(); + { + ucOriginalSFRPage = SFRPAGE; + SFRPAGE = 0; + + uxTxEmpty = pdTRUE; + + /* Create the queues used by the com test task. */ + xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( portCHAR ) ); + xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( portCHAR ) ); + + /* Calculate the baud rate to use timer 1. */ + ulReloadValue = ( unsigned portLONG ) ( ( ( portFLOAT ) 256 - ( fBaudConst / ( portFLOAT ) ( 32 * ulWantedBaud ) ) ) + ( portFLOAT ) 0.5 ); + + /* Set timer one for desired mode of operation. */ + TMOD &= 0x08; + TMOD |= ser8BIT_WITH_RELOAD; + SSTA0 |= serSMOD; + + /* Set the reload and start values for the time. */ + TL1 = ( unsigned portCHAR ) ulReloadValue; + TH1 = ( unsigned portCHAR ) ulReloadValue; + + /* Setup the control register for standard n, 8, 1 - variable baud rate. */ + SCON = ser8_BIT_MODE | serRX_ENABLE; + + /* Enable the serial port interrupts */ + ES = 1; + + /* Start the timer. */ + TR1 = 1; + + SFRPAGE = ucOriginalSFRPage; + } + portEXIT_CRITICAL(); + + /* Unlike some ports, this serial code does not allow for more than one + com port. We therefore don't return a pointer to a port structure and can + instead just return NULL. */ + return NULL; +} +/*-----------------------------------------------------------*/ + +void vSerialISR( void ) interrupt 4 +{ +portCHAR cChar; +portBASE_TYPE xTaskWokenByRx = pdFALSE, xTaskWokenByTx = pdFALSE; + + /* 8051 port interrupt routines MUST be placed within a critical section + if taskYIELD() is used within the ISR! */ + + portENTER_CRITICAL(); + { + if( RI ) + { + /* Get the character and post it on the queue of Rxed characters. + If the post causes a task to wake force a context switch as the woken task + may have a higher priority than the task we have interrupted. */ + cChar = SBUF; + RI = 0; + + if( xQueueSendFromISR( xRxedChars, &cChar, pdFALSE ) ) + { + xTaskWokenByRx = ( portBASE_TYPE ) pdTRUE; + } + } + + if( TI ) + { + if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == ( portBASE_TYPE ) pdTRUE ) + { + /* Send the next character queued for Tx. */ + SBUF = cChar; + } + else + { + /* Queue empty, nothing to send. */ + uxTxEmpty = pdTRUE; + } + + TI = 0; + } + + if( xTaskWokenByRx || xTaskWokenByTx ) + { + portYIELD(); + } + } + portEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) +{ + /* There is only one port supported. */ + ( void ) pxPort; + + /* Get the next character from the buffer. Return false if no characters + are available, or arrive before xBlockTime expires. */ + if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) + { + return ( portBASE_TYPE ) pdTRUE; + } + else + { + return ( portBASE_TYPE ) pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) +{ +portBASE_TYPE xReturn; + + /* There is only one port supported. */ + ( void ) pxPort; + + portENTER_CRITICAL(); + { + if( uxTxEmpty == pdTRUE ) + { + SBUF = cOutChar; + uxTxEmpty = pdFALSE; + xReturn = ( portBASE_TYPE ) pdTRUE; + } + else + { + xReturn = xQueueSend( xCharsForTx, &cOutChar, xBlockTime ); + + if( xReturn == ( portBASE_TYPE ) pdFALSE ) + { + xReturn = ( portBASE_TYPE ) pdTRUE; + } + } + } + portEXIT_CRITICAL(); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +void vSerialClose( xComPortHandle xPort ) +{ + /* Not implemented in this port. */ + ( void ) xPort; +} +/*-----------------------------------------------------------*/ + + + + + diff --git a/20080212/Demo/Flshlite/FRConfig.h b/20080212/Demo/Flshlite/FRConfig.h new file mode 100644 index 000000000..49b869a76 --- /dev/null +++ b/20080212/Demo/Flshlite/FRConfig.h @@ -0,0 +1,97 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include + +/*----------------------------------------------------------- + * Application specific definitions for the x86 port. + *----------------------------------------------------------*/ + +/* These are the only definitions that can be modified!. */ +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 10 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 128 ) /* This can be made smaller if required. */ +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 32 * 1024 ) ) +#define configMAX_TASK_NAME_LEN ( 16 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 1 +#define configIDLE_SHOULD_YIELD 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* The maximum number of characters a task name can take, +including the null terminator. */ +#define configMAX_TASK_NAME_LEN ( 16 ) + +/* Set the following definitions to 1 to include the component, or zero +to exclude the component. */ + +/* Include/exclude the stated API function. */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + +/* Use/don't use the trace visualisation. */ +#define configUSE_TRACE_FACILITY 0 + +/* + * The tick count (and times defined in tick count units) can be either a 16bit + * or a 32 bit value. See documentation on http://www.FreeRTOS.org to decide + * which to use. + */ +#define configUSE_16_BIT_TICKS 1 + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/Flshlite/FileIO/fileIO.c b/20080212/Demo/Flshlite/FileIO/fileIO.c new file mode 100644 index 000000000..d0e0cf8e5 --- /dev/null +++ b/20080212/Demo/Flshlite/FileIO/fileIO.c @@ -0,0 +1,116 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#include +#include +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo program include files. */ +#include "fileio.h" + +void vDisplayMessage( const portCHAR * const pcMessageToPrint ) +{ + #ifdef USE_STDIO + taskENTER_CRITICAL(); + printf( "%s", pcMessageToPrint ); + fflush( stdout ); + taskEXIT_CRITICAL(); + #else + /* Stop warnings. */ + ( void ) pcMessageToPrint; + #endif +} +/*-----------------------------------------------------------*/ + +void vWriteMessageToDisk( const portCHAR * const pcMessage ) +{ +#ifdef USE_STDIO +const portCHAR * const pcFileName = "c:\\RTOSlog.txt"; +const portCHAR * const pcSeparator = "\r\n-----------------------\r\n"; +FILE *pf; + + taskENTER_CRITICAL(); + { + pf = fopen( pcFileName, "a" ); + if( pf != NULL ) + { + fwrite( pcMessage, strlen( pcMessage ), ( unsigned portSHORT ) 1, pf ); + fwrite( pcSeparator, strlen( pcSeparator ), ( unsigned portSHORT ) 1, pf ); + fclose( pf ); + } + } + taskEXIT_CRITICAL(); +#else + /* Stop warnings. */ + ( void ) pcMessage; +#endif /*USE_STDIO*/ +} +/*-----------------------------------------------------------*/ + +void vWriteBufferToDisk( const portCHAR * const pcBuffer, unsigned portLONG ulBufferLength ) +{ +#ifdef USE_STDIO +const portCHAR * const pcFileName = "c:\\trace.bin"; +FILE *pf; + + taskENTER_CRITICAL(); + { + pf = fopen( pcFileName, "wb" ); + if( pf ) + { + fwrite( pcBuffer, ( size_t ) ulBufferLength, ( unsigned portSHORT ) 1, pf ); + fclose( pf ); + } + } + taskEXIT_CRITICAL(); +#else + /* Stop warnings. */ + ( void ) pcBuffer; + ( void ) ulBufferLength; +#endif /*USE_STDIO*/ +} + + diff --git a/20080212/Demo/Flshlite/FreeRTOSConfig.h b/20080212/Demo/Flshlite/FreeRTOSConfig.h new file mode 100644 index 000000000..aa7691cdb --- /dev/null +++ b/20080212/Demo/Flshlite/FreeRTOSConfig.h @@ -0,0 +1,89 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include +#include + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 10 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 128 ) /* This can be made smaller if required. */ +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 32 * 1024 ) ) +#define configMAX_TASK_NAME_LEN ( 16 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 1 +#define configIDLE_SHOULD_YIELD 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/Flshlite/ParTest/ParTest.c b/20080212/Demo/Flshlite/ParTest/ParTest.c new file mode 100644 index 000000000..5f99965b1 --- /dev/null +++ b/20080212/Demo/Flshlite/ParTest/ParTest.c @@ -0,0 +1,140 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V1.01: + + + Types used updated. + + Add vParTestToggleLED(); + +Changes from V2.0.0 + + + Use scheduler suspends in place of critical sections. +*/ + + +#include "FreeRTOS.h" +#include "task.h" +#include "partest.h" + +#define partstALL_OUTPUTS_OFF ( ( unsigned portSHORT) 0x00 ) +#define partstMAX_OUTPUT_LED ( ( unsigned portCHAR ) 7 ) +#define partstPORT_F_ADDR ( ( unsigned portSHORT ) 0x605 ) +#define partstPORT_DIRECTION_REG ( ( unsigned portSHORT ) 0x606 ) +#define partstPORT_F_DIR_BIT ( ( unsigned portSHORT ) 0x20 ) + +/*lint -e956 File scope parameters okay here. */ +static volatile unsigned portCHAR ucCurrentOutputValue = partstALL_OUTPUTS_OFF; +/*lint +e956 */ + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ +unsigned portSHORT usInput; + + ucCurrentOutputValue = partstALL_OUTPUTS_OFF; + + /* Set the direction to output for port F. */ + usInput = portINPUT_BYTE( partstPORT_DIRECTION_REG ); + usInput |= partstPORT_F_DIR_BIT; + portOUTPUT_BYTE( partstPORT_DIRECTION_REG, usInput ); + + /* Start with all outputs off. */ + portOUTPUT_BYTE( partstPORT_F_ADDR, partstALL_OUTPUTS_OFF ); +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, portBASE_TYPE xValue ) +{ +unsigned portCHAR ucBit = ( unsigned portCHAR ) 1; + + if( uxLED <= partstMAX_OUTPUT_LED ) + { + ucBit <<= uxLED; + } + + vTaskSuspendAll(); + { + if( xValue == pdTRUE ) + { + ucBit ^= ( unsigned portCHAR ) 0xff; + ucCurrentOutputValue &= ucBit; + } + else + { + ucCurrentOutputValue |= ucBit; + } + + portOUTPUT_BYTE( partstPORT_F_ADDR, ( unsigned ) ucCurrentOutputValue ); + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned portCHAR ucBit; + + if( uxLED <= partstMAX_OUTPUT_LED ) + { + ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED; + + vTaskSuspendAll(); + { + if( ucCurrentOutputValue & ucBit ) + { + ucCurrentOutputValue &= ~ucBit; + } + else + { + ucCurrentOutputValue |= ucBit; + } + + portOUTPUT_BYTE( partstPORT_F_ADDR, ( unsigned ) ucCurrentOutputValue ); + } + xTaskResumeAll(); + } +} + diff --git a/20080212/Demo/Flshlite/RTOSDEMO.IDE b/20080212/Demo/Flshlite/RTOSDEMO.IDE new file mode 100644 index 0000000000000000000000000000000000000000..00741f4b4ec484ed8406e1a92bc5468ace6ddfc9 GIT binary patch literal 41836 zcmeHwdtg=7neWQ;oV-I4LJ|TTLWmJV2muiRkvs_+l9&WUL@+N%AS5vfh>8{w6|J>M zt)f!3Rw=dCTE}T^$2yMF=}^b9y-vq*ypH2IUa#YL+fM6nJ6@~z_xslV_TJe!Ikk5> z^T)mSOTM-C-s^j<_u6Z%y-w}$=wR1SZ=~+5vm$My!#n$W#v_dbgMF!{$i$l`&G(-D z@THHwWXwpCF$LWrQ*KN+&YU{qozl1B4PaTqj)JndpBM02A>&7hcpeA3AK~v&_+JM; z2K)x_ao{(BPXNCKd=mHvz^8zJ2>dqiJHV%b-vxdT_(#BJfZqo`3;bi?bHG0VJ`em; z;17U*2K*uL&w;0aKLWl0{0rcVz`q2(1pG1ZC&2##d>Qyxz@GyD8u$wEZ-B1?{}%Wf z@V^3I2mT%K4dCAc-vs^x@Gam!0^bJyH{d(K{|e8F(ph3-B`FR^T?^<-jgr zH?RlT3+w}K2krp&0|$URfxCc%z}>(h;4m-+7!Ozu@D}Td9R*Trl_uUG=j3^@)MS004B3^vecP>V#ZtpH zjCw0a$K5d2e1&whES3GdqdmpaB50WK^^f+bOtusX@g@N>`^^Iqk78*-G)(vghFm_j zED93VH8!9!+2Saq)6U`Uof^iLNFj@1g9F_f#uiE;N#fTxreSQk6yh1yHL}l!l}d}I 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z9&+wqb^OeO)~-$PDgSo()OX6c|Jb=-euI5J>iCbr?*?7wA^W_^@ejhMoTnZCXYgsq z(i`pbosRz?eCm14@$+u7_bu>wI@fXdwD&dVzWiqUd@p>6G#|oe`0~Tn-wU65A9MV- zoad2StlZ7;8Ggj^f9UuhIezu6HoV{Q?|1y4I({lX9izSV@M+&s_>_0b@jrILm)~Ze z4>|tBj{lnDXMfIyH#+`)$A8lC--TZbxeIU<3*}!9pZ57@HTe-^|f6(zCf=@lKJAVE#OV{l92Oa-u_@w)#b6zwF$H@3rBp z;gfHlbN{&GzwJDqeV?W4bo^T#|2fA$?f4bPEnPSK7RY +#include +#include "FreeRTOS.h" +#include "task.h" +#include "partest.h" +#include "serial.h" + +/* Demo file headers. */ +#include "BlockQ.h" +#include "PollQ.h" +#include "death.h" +#include "flash.h" +#include "integer.h" +#include "print.h" +#include "comtest.h" +#include "fileio.h" +#include "semtest.h" + +/* Priority definitions for all the tasks in the demo application. */ +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainPRINT_TASK_PRIORITY ( tskIDLE_PRIORITY + 5 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_BLOCK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainSEMAPHORE_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +#define mainPRINT_STACK_SIZE ( ( unsigned portSHORT ) 256 ) +#define mainDEBUG_LOG_BUFFER_SIZE ( ( unsigned portSHORT ) 20480 ) + +/* Constant definitions for accessing the build in LED on the Flashlite 186. */ +#define mainLED_REG_DIR ( ( unsigned portSHORT ) 0xff78 ) +#define mainLED_REG ( ( unsigned portSHORT ) 0xff7a ) + +/* If an error is detected in a task then the vErrorChecks() task will enter +an infinite loop flashing the LED at this rate. */ +#define mainERROR_FLASH_RATE ( ( portTickType ) 100 / portTICK_RATE_MS ) + +/* Task function for the "Print" task as described at the top of the file. */ +static void vErrorChecks( void *pvParameters ); + +/* Function that checks the unique count of all the other tasks as described at +the top of the file. */ +static void prvCheckOtherTasksAreStillRunning( void ); + +/* Functions to setup and use the built in LED on the Flashlite 186 board. */ +static void prvToggleLED( void ); +static void prvInitLED( void ); + +/* Key presses can be used to start/stop the trace visualisation utility or stop +the scheduler. */ +static void prvCheckForKeyPresses( void ); + +/* Buffer used by the trace visualisation utility. */ +static portCHAR pcWriteBuffer[ mainDEBUG_LOG_BUFFER_SIZE ]; + +/*-----------------------------------------------------------*/ +portSHORT main( void ) +{ + /* Initialise hardware and utilities. */ + vParTestInitialise(); + vPrintInitialise(); + prvInitLED(); + + /* CREATE ALL THE DEMO APPLICATION TASKS. */ + + vStartComTestTasks( mainCOM_TEST_PRIORITY, serCOM2, ser38400 ); + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartBlockingQueueTasks( mainQUEUE_BLOCK_PRIORITY ); + vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); + vStartSemaphoreTasks( mainSEMAPHORE_TASK_PRIORITY ); + + /* Create the "Print" task as described at the top of the file. */ + xTaskCreate( vErrorChecks, "Print", mainPRINT_STACK_SIZE, NULL, mainPRINT_TASK_PRIORITY, NULL ); + + /* This task has to be created last as it keeps account of the number of tasks + it expects to see running. */ + vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); + + /* Set the scheduler running. This function will not return unless a task + calls vTaskEndScheduler(). */ + vTaskStartScheduler(); + + return 1; +} +/*-----------------------------------------------------------*/ + +static void vErrorChecks( void *pvParameters ) +{ +portTickType xExpectedWakeTime; +const portTickType xPrintRate = ( portTickType ) 5000 / portTICK_RATE_MS; +const portLONG lMaxAllowableTimeDifference = ( portLONG ) 0; +portTickType xWakeTime; +portLONG lTimeDifference; +const portCHAR *pcReceivedMessage; +const portCHAR * const pcTaskBlockedTooLongMsg = "Print task blocked too long!\r\n"; + + /* Stop warnings. */ + ( void ) pvParameters; + + /* Loop continuously, blocking, then checking all the other tasks are still + running, before blocking once again. This task blocks on the queue of messages + that require displaying so will wake either by its time out expiring, or a + message becoming available. */ + for( ;; ) + { + /* Calculate the time we will unblock if no messages are received + on the queue. This is used to check that we have not blocked for too long. */ + xExpectedWakeTime = xTaskGetTickCount(); + xExpectedWakeTime += xPrintRate; + + /* Block waiting for either a time out or a message to be posted that + required displaying. */ + pcReceivedMessage = pcPrintGetNextMessage( xPrintRate ); + + /* Was a message received? */ + if( pcReceivedMessage == NULL ) + { + /* A message was not received so we timed out, did we unblock at the + expected time? */ + xWakeTime = xTaskGetTickCount(); + + /* Calculate the difference between the time we unblocked and the + time we should have unblocked. */ + if( xWakeTime > xExpectedWakeTime ) + { + lTimeDifference = ( portLONG ) ( xWakeTime - xExpectedWakeTime ); + } + else + { + lTimeDifference = ( portLONG ) ( xExpectedWakeTime - xWakeTime ); + } + + if( lTimeDifference > lMaxAllowableTimeDifference ) + { + /* We blocked too long - create a message that will get + printed out the next time around. */ + vPrintDisplayMessage( &pcTaskBlockedTooLongMsg ); + } + + /* Check the other tasks are still running, just in case. */ + prvCheckOtherTasksAreStillRunning(); + } + else + { + /* We unblocked due to a message becoming available. Send the message + for printing. */ + vDisplayMessage( pcReceivedMessage ); + } + + /* Key presses are used to invoke the trace visualisation utility, or + end the program. */ + prvCheckForKeyPresses(); + } +} /*lint !e715 !e818 pvParameters is not used but all task functions must take this form. */ +/*-----------------------------------------------------------*/ + +static void prvCheckForKeyPresses( void ) +{ + #ifdef USE_STDIO + + portSHORT sIn; + + + taskENTER_CRITICAL(); + sIn = kbhit(); + taskEXIT_CRITICAL(); + + if( sIn ) + { + unsigned portLONG ulBufferLength; + + /* Key presses can be used to start/stop the trace utility, or end the + program. */ + sIn = getch(); + switch( sIn ) + { + /* Only define keys for turning on and off the trace if the trace + is being used. */ + #if configUSE_TRACE_FACILITY == 1 + case 't' : vTaskList( pcWriteBuffer ); + vWriteMessageToDisk( pcWriteBuffer ); + break; + + case 's' : vTaskStartTrace( pcWriteBuffer, mainDEBUG_LOG_BUFFER_SIZE ); + break; + + case 'e' : ulBufferLength = ulTaskEndTrace(); + vWriteBufferToDisk( pcWriteBuffer, ulBufferLength ); + break; + #endif + + default : vTaskEndScheduler(); + break; + } + } + + #else + ( void ) pcWriteBuffer; + #endif +} +/*-----------------------------------------------------------*/ + +static void prvCheckOtherTasksAreStillRunning( void ) +{ +portSHORT sErrorHasOccurred = pdFALSE; + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + vDisplayMessage( "Com test count unchanged!\r\n" ); + sErrorHasOccurred = pdTRUE; + } + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + vDisplayMessage( "Integer maths task count unchanged!\r\n" ); + sErrorHasOccurred = pdTRUE; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + vDisplayMessage( "Blocking queues count unchanged!\r\n" ); + sErrorHasOccurred = pdTRUE; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + vDisplayMessage( "Polling queue count unchanged!\r\n" ); + sErrorHasOccurred = pdTRUE; + } + + if( xIsCreateTaskStillRunning() != pdTRUE ) + { + vDisplayMessage( "Incorrect number of tasks running!\r\n" ); + sErrorHasOccurred = pdTRUE; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + vDisplayMessage( "Semaphore take count unchanged!\r\n" ); + sErrorHasOccurred = pdTRUE; + } + + if( sErrorHasOccurred == pdFALSE ) + { + vDisplayMessage( "OK " ); + /* Toggle the LED if everything is okay so we know if an error occurs even if not + using console IO. */ + prvToggleLED(); + } + else + { + for( ;; ) + { + /* An error has occurred in one of the tasks. Don't go any further and + flash the LED rapidly in case console IO is not being used. */ + prvToggleLED(); + vTaskDelay( mainERROR_FLASH_RATE ); + } + } +} +/*-----------------------------------------------------------*/ + +static void prvInitLED( void ) +{ +unsigned portSHORT usPortDirection; +const unsigned portSHORT usLEDOut = 0x400; + + /* Set the LED bit to an output. */ + + usPortDirection = inpw( mainLED_REG_DIR ); + usPortDirection &= ~usLEDOut; + outpw( mainLED_REG_DIR, usPortDirection ); +} +/*-----------------------------------------------------------*/ + +static void prvToggleLED( void ) +{ +static portSHORT sLED = pdTRUE; +unsigned portSHORT usLEDState; +const unsigned portSHORT usLEDBit = 0x400; + + /* Flip the state of the LED. */ + usLEDState = inpw( mainLED_REG ); + if( sLED ) + { + usLEDState &= ~usLEDBit; + } + else + { + usLEDState |= usLEDBit; + } + outpw( mainLED_REG, usLEDState ); + + sLED = !sLED; +} + + diff --git a/20080212/Demo/Flshlite/rtosdemo.DSW b/20080212/Demo/Flshlite/rtosdemo.DSW new file mode 100644 index 0000000000000000000000000000000000000000..003116e97148560e555b34f468fdc74b4eef2c3b GIT binary patch literal 3466 zcmeHJO>7%g5T3VjoTW`#w<4+%BjKok5Fj@;aY|bWY1up{R{ayL*AarPTzkDFChJ{m z*N%DvBux!Zc95(!ctiWns` z@0*!7J2UUkde^JF2{oa*PRBacNo1S0m6!xJw*LT|1lavj?4)#QBnpqPD10|O9KAU5 zoWNtq%T|p2_gVA+`u7&UkE;r zGtbBFLmq);3WGExkKFhVFv(MJ4rGYI>p0#A55p|zZ~|O-0sM;Jbe0!A%WAbdP1ga_ zZ55O!t7@rO=4wUHE%7SXw31c^)3$0(x9wRz5?1=`+P5P8kgo8~I`Wpl-9bZyJix{iZihK|2l&OODerEHZe>Oxi56qQ%=xgx(q zvpx;uxI_|+VXrm4RG#C7QZhHk;azM!8SX;EidAb@(@7Ivfv?5teu2swB$EdI_4;VE zU9VHC+m=x`O(Qj1Z+054Z{Yg0T<2KGv+0<2w_%a8XEp+jc@$^QWCA?!4;)Lvt8lj{ za}+BIK5sYc@N|5)&<~+LlK~^XN5Ck;N7ILA55tN0&Bl2h*Kb%YH);AUsK!TyD{gv7 zO;5wgzDVf|)Z)8@na;pNP!Az9gc>1ah0rr0v>ZY!A=C_^XG3T;gzOM%g^&|MAIHZ; z4fHxZmO7G#Px@-kq|)$de6MgAL5G=XBKWK?!V&nq&jFi64j1|yreW%yoBdDC!Up>& z@&^V3;Oqjk6X}US3f)m-jxQNmjdR+=M!8hcRBkMmG+lWj&y4~v6qMq;vA~r@+{da2 zG#GXe&l6sLfN$!K=w1=0$7Q%GVy#Or4#lU=Oa_vad`szcevNFtypYf796N$HV>UOR zT-Z@E+fQad*E++4v{RxuAfn0mb`Wi_b;(YAIT1+GZ7uowYG1$QZ|s7B)_edS$4q*a zQ%?V$C=Q5dGW;OMRI8V`C~782%D<^uSIWoB1KrO{a0o9l2G{5!+yNbmB)tMX zOBx>BwS52C@j%LGIU9>oJ`%_ZYuv76wvDs7xvlvY#&08MBnIv8$N*E4GGUj?L=IsgCw literal 0 HcmV?d00001 diff --git a/20080212/Demo/Flshlite/rtosdemo.lk1 b/20080212/Demo/Flshlite/rtosdemo.lk1 new file mode 100644 index 000000000..9ce583f24 --- /dev/null +++ b/20080212/Demo/Flshlite/rtosdemo.lk1 @@ -0,0 +1,2 @@ +FIL list.obj,heap_2.obj,portcomn.obj,port.obj,queue.obj,tasks.obj,blockq.obj,comtest.obj,death.obj,flash.obj,integer.obj,pollq.obj,print.obj,semtest.obj,fileio.obj,main.obj,partest.obj,serial.obj + diff --git a/20080212/Demo/Flshlite/rtosdemo.mk b/20080212/Demo/Flshlite/rtosdemo.mk new file mode 100644 index 000000000..cc665e818 --- /dev/null +++ b/20080212/Demo/Flshlite/rtosdemo.mk @@ -0,0 +1,3 @@ +project : E:\Dev\FreeRTOS\Demo\Flshlite\rtosdemo.exe .SYMBOLIC + +!include E:\Dev\FreeRTOS\Demo\Flshlite\rtosdemo.mk1 diff --git a/20080212/Demo/Flshlite/rtosdemo.mk1 b/20080212/Demo/Flshlite/rtosdemo.mk1 new file mode 100644 index 000000000..789b4302e --- /dev/null +++ b/20080212/Demo/Flshlite/rtosdemo.mk1 @@ -0,0 +1,191 @@ +!define BLANK "" +E:\Dev\FreeRTOS\Demo\Flshlite\list.obj : E:\Dev\FreeRTOS\source\list.c .AUTO& +DEPEND + @E: + cd E:\Dev\FreeRTOS\Demo\Flshlite + *wcc ..\..\source\list.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;..\..\& +source\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -za -s& + -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=dos -m& +l + +E:\Dev\FreeRTOS\Demo\Flshlite\heap_2.obj : E:\Dev\FreeRTOS\SOURCE\PORTABLE\M& +EMMANG\heap_2.c .AUTODEPEND + @E: + cd E:\Dev\FreeRTOS\Demo\Flshlite + *wcc ..\..\SOURCE\PORTABLE\MEMMANG\heap_2.c -i=D:\DEVTOOLS\OPENWA~1\h;..\co& +mmon\include;..\..\source\include;..\..\source\portable\owatcom\16bitdos\com& +mon -w4 -e25 -za -s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fp& +c -zu -1 -bt=dos -ml + +E:\Dev\FreeRTOS\Demo\Flshlite\portcomn.obj : E:\Dev\FreeRTOS\source\portable& +\owatcom\16bitdos\common\portcomn.c .AUTODEPEND + @E: + cd E:\Dev\FreeRTOS\Demo\Flshlite + *wcc ..\..\source\portable\owatcom\16bitdos\common\portcomn.c -i=D:\DEVTOOL& +S\OPENWA~1\h;..\common\include;..\..\source\include;..\..\source\portable\ow& +atcom\16bitdos\common -w4 -e25 -za -s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -& +zq -otexan -of -fpc -zu -1 -bt=dos -ml + +E:\Dev\FreeRTOS\Demo\Flshlite\port.obj : E:\Dev\FreeRTOS\source\portable\owa& +tcom\16bitdos\flsh186\port.c .AUTODEPEND + @E: + cd E:\Dev\FreeRTOS\Demo\Flshlite + *wcc ..\..\source\portable\owatcom\16bitdos\flsh186\port.c -i=D:\DEVTOOLS\O& +PENWA~1\h;..\common\include;..\..\source\include;..\..\source\portable\owatc& +om\16bitdos\common -w4 -e25 -za -s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq & +-otexan -of -fpc -zu -1 -bt=dos -ml + +E:\Dev\FreeRTOS\Demo\Flshlite\queue.obj : E:\Dev\FreeRTOS\source\queue.c .AU& +TODEPEND + @E: + cd E:\Dev\FreeRTOS\Demo\Flshlite + *wcc ..\..\source\queue.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;..\..& +\source\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -za -& +s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=dos -& +ml + +E:\Dev\FreeRTOS\Demo\Flshlite\tasks.obj : E:\Dev\FreeRTOS\source\tasks.c .AU& +TODEPEND + @E: + cd E:\Dev\FreeRTOS\Demo\Flshlite + *wcc ..\..\source\tasks.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;..\..& +\source\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -za -& +s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=dos -& +ml + +E:\Dev\FreeRTOS\Demo\Flshlite\blockq.obj : E:\Dev\FreeRTOS\Demo\common\full\& +blockq.c .AUTODEPEND + @E: + cd E:\Dev\FreeRTOS\Demo\Flshlite + *wcc ..\common\full\blockq.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;..& +\..\source\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -z& +a -s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=do& +s -ml + +E:\Dev\FreeRTOS\Demo\Flshlite\comtest.obj : E:\Dev\FreeRTOS\Demo\common\full& +\comtest.c .AUTODEPEND + @E: + cd E:\Dev\FreeRTOS\Demo\Flshlite + *wcc ..\common\full\comtest.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;.& +.\..\source\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -& +za -s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=d& +os -ml + +E:\Dev\FreeRTOS\Demo\Flshlite\death.obj : E:\Dev\FreeRTOS\Demo\common\full\d& +eath.c .AUTODEPEND + @E: + cd E:\Dev\FreeRTOS\Demo\Flshlite + *wcc ..\common\full\death.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;..\& +..\source\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -za& + -s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=dos& + -ml + +E:\Dev\FreeRTOS\Demo\Flshlite\flash.obj : E:\Dev\FreeRTOS\Demo\common\full\f& +lash.c .AUTODEPEND + @E: + cd E:\Dev\FreeRTOS\Demo\Flshlite + *wcc ..\common\full\flash.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;..\& +..\source\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -za& + -s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=dos& + -ml + +E:\Dev\FreeRTOS\Demo\Flshlite\integer.obj : E:\Dev\FreeRTOS\Demo\common\full& +\integer.c .AUTODEPEND + @E: + cd E:\Dev\FreeRTOS\Demo\Flshlite + *wcc ..\common\full\integer.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;.& +.\..\source\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -& +za -s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=d& +os -ml + +E:\Dev\FreeRTOS\Demo\Flshlite\pollq.obj : E:\Dev\FreeRTOS\Demo\common\full\p& +ollq.c .AUTODEPEND + @E: + cd E:\Dev\FreeRTOS\Demo\Flshlite + *wcc ..\common\full\pollq.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;..\& +..\source\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -za& + -s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=dos& + -ml + +E:\Dev\FreeRTOS\Demo\Flshlite\print.obj : E:\Dev\FreeRTOS\Demo\common\full\p& +rint.c .AUTODEPEND + @E: + cd E:\Dev\FreeRTOS\Demo\Flshlite + *wcc ..\common\full\print.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;..\& +..\source\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -za& + -s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=dos& + -ml + +E:\Dev\FreeRTOS\Demo\Flshlite\semtest.obj : E:\Dev\FreeRTOS\Demo\common\full& +\semtest.c .AUTODEPEND + @E: + cd E:\Dev\FreeRTOS\Demo\Flshlite + *wcc ..\common\full\semtest.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;.& +.\..\source\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -& +za -s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=d& +os -ml + +E:\Dev\FreeRTOS\Demo\Flshlite\fileio.obj : E:\Dev\FreeRTOS\Demo\Flshlite\fil& +eio\fileio.c .AUTODEPEND + @E: + cd E:\Dev\FreeRTOS\Demo\Flshlite + *wcc fileio\fileio.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;..\..\sour& +ce\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -za -s -dO& +PEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=dos -ml + +E:\Dev\FreeRTOS\Demo\Flshlite\main.obj : E:\Dev\FreeRTOS\Demo\Flshlite\main.& +c .AUTODEPEND + @E: + cd E:\Dev\FreeRTOS\Demo\Flshlite + *wcc main.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;..\..\source\includ& +e;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -za -s -dOPEN_WATCO& +M_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=dos -ml + +E:\Dev\FreeRTOS\Demo\Flshlite\partest.obj : E:\Dev\FreeRTOS\Demo\Flshlite\pa& +rtest\partest.c .AUTODEPEND + @E: + cd E:\Dev\FreeRTOS\Demo\Flshlite + *wcc partest\partest.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;..\..\so& +urce\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -za -s -& +dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=dos -ml + +E:\Dev\FreeRTOS\Demo\Flshlite\serial.obj : E:\Dev\FreeRTOS\Demo\Flshlite\ser& +ial\serial.c .AUTODEPEND + @E: + cd E:\Dev\FreeRTOS\Demo\Flshlite + *wcc serial\serial.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;..\..\sour& +ce\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -za -s -dO& +PEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=dos -ml + +E:\Dev\FreeRTOS\Demo\Flshlite\rtosdemo.exe : E:\Dev\FreeRTOS\Demo\Flshlite\l& +ist.obj E:\Dev\FreeRTOS\Demo\Flshlite\heap_2.obj E:\Dev\FreeRTOS\Demo\Flshli& +te\portcomn.obj E:\Dev\FreeRTOS\Demo\Flshlite\port.obj E:\Dev\FreeRTOS\Demo\& +Flshlite\queue.obj E:\Dev\FreeRTOS\Demo\Flshlite\tasks.obj E:\Dev\FreeRTOS\D& +emo\Flshlite\blockq.obj E:\Dev\FreeRTOS\Demo\Flshlite\comtest.obj E:\Dev\Fre& +eRTOS\Demo\Flshlite\death.obj E:\Dev\FreeRTOS\Demo\Flshlite\flash.obj E:\Dev& +\FreeRTOS\Demo\Flshlite\integer.obj E:\Dev\FreeRTOS\Demo\Flshlite\pollq.obj & +E:\Dev\FreeRTOS\Demo\Flshlite\print.obj E:\Dev\FreeRTOS\Demo\Flshlite\semtes& +t.obj E:\Dev\FreeRTOS\Demo\Flshlite\fileio.obj E:\Dev\FreeRTOS\Demo\Flshlite& +\main.obj E:\Dev\FreeRTOS\Demo\Flshlite\partest.obj E:\Dev\FreeRTOS\Demo\Fls& +hlite\serial.obj E:\Dev\FreeRTOS\source\include\list.h E:\Dev\FreeRTOS\sourc& +e\include\portable.h E:\Dev\FreeRTOS\source\include\projdefs.h E:\Dev\FreeRT& +OS\source\include\queue.h E:\Dev\FreeRTOS\source\include\semphr.h E:\Dev\Fre& +eRTOS\source\include\task.h E:\Dev\FreeRTOS\source\portable\owatcom\16bitdos& +\common\portasm.h E:\Dev\FreeRTOS\source\portable\owatcom\16bitdos\flsh186\p& +ortmacro.h E:\Dev\FreeRTOS\Demo\common\include\blockq.h E:\Dev\FreeRTOS\Demo& +\common\include\comtest.h E:\Dev\FreeRTOS\Demo\common\include\death.h E:\Dev& +\FreeRTOS\Demo\common\include\fileio.h E:\Dev\FreeRTOS\Demo\common\include\f& +lash.h E:\Dev\FreeRTOS\Demo\common\include\flop.h E:\Dev\FreeRTOS\Demo\commo& +n\include\partest.h E:\Dev\FreeRTOS\Demo\common\include\pollq.h E:\Dev\FreeR& +TOS\Demo\common\include\print.h E:\Dev\FreeRTOS\Demo\common\include\semtest.& +h E:\Dev\FreeRTOS\Demo\common\include\serial.h E:\Dev\FreeRTOS\Demo\Flshlite& +\FreeRTOSConfig.h .AUTODEPEND + @E: + cd E:\Dev\FreeRTOS\Demo\Flshlite + @%write rtosdemo.lk1 FIL list.obj,heap_2.obj,portcomn.obj,port.obj,queue.ob& +j,tasks.obj,blockq.obj,comtest.obj,death.obj,flash.obj,integer.obj,pollq.obj& +,print.obj,semtest.obj,fileio.obj,main.obj,partest.obj,serial.obj + @%append rtosdemo.lk1 + *wlink name rtosdemo SYS dos op m op maxe=25 op d op q op symf op el @rtosd& +emo.lk1 + diff --git a/20080212/Demo/Flshlite/rtosdemo.tgt b/20080212/Demo/Flshlite/rtosdemo.tgt new file mode 100644 index 000000000..367e27550 --- /dev/null +++ b/20080212/Demo/Flshlite/rtosdemo.tgt @@ -0,0 +1,1159 @@ +40 +targetIdent +0 +MProject +1 +MComponent +0 +2 +WString +3 +EXE +3 +WString +5 +de6en +1 +0 +0 +4 +MCommand +0 +5 +MCommand +0 +6 +MItem +12 +rtosdemo.exe +7 +WString +3 +EXE +8 +WVList +4 +9 +MRState +10 +WString +5 +WLINK +11 +WString +14 +?????Debug All +1 +0 +12 +MRState +13 +WString +5 +WLINK +14 +WString +16 +?????Debug Dwarf +1 +1 +15 +MCState +16 +WString +5 +WLINK +17 +WString +11 +?????Dosseg +0 +1 +18 +MCState +19 +WString +5 +WLINK +20 +WString +24 +?????Eliminate dead code +0 +1 +21 +WVList +2 +22 +ActionStates +23 +WString +6 +&Debug +24 +WVList +0 +25 +ActionStates +26 +WString +5 +&Make +27 +WVList +0 +-1 +1 +1 +0 +28 +WPickList +40 +29 +MItem +3 +*.c +30 +WString +4 +COBJ +31 +WVList +26 +32 +MVState +33 +WString +3 +WCC +34 +WString +25 +d????Include directories: +1 +35 +WString +97 +$(%watcom)\h;..\common\include;..\..\source\include;..\..\source\portable\owatcom\16bitdos\common +0 +36 +MCState +37 +WString +3 +WCC +38 +WString +26 +?????Force ANSI compliance +1 +1 +39 +MCState +40 +WString +3 +WCC +41 +WString +33 +?????Disable stack depth checking +1 +1 +42 +MVState +43 +WString +3 +WCC +44 +WString +23 +?????Macro definitions: +1 +45 +WString +43 +OPEN_WATCOM_FLASH_LITE_186_PORT DEBUG_BUILD +0 +46 +MCState +47 +WString +3 +WCC +48 +WString +34 +?????Change char default to signed +1 +1 +49 +MRState +50 +WString +3 +WCC +51 +WString +21 +?????Compiler default +1 +0 +52 +MRState +53 +WString +3 +WCC +54 +WString +21 +?????Compiler default +1 +0 +55 +MRState +56 +WString +3 +WCC +57 +WString +25 +?????Floating-point calls +1 +1 +58 +MCState +59 +WString +3 +WCC +60 +WString +31 +???e?SS not assumed equal to DS +1 +1 +61 +MRState +62 +WString +3 +WCC +63 +WString +9 +??6??8086 +1 +0 +64 +MRState +65 +WString +3 +WCC +66 +WString +10 +??6??80186 +1 +1 +67 +MVState +68 +WString +3 +WCC +69 +WString +25 +d????Include directories: +0 +70 +WString +97 +$(%watcom)\h;..\common\include;..\..\source\include;..\..\source\portable\owatcom\16bitdos\common +0 +71 +MCState +72 +WString +3 +WCC +73 +WString +26 +?????Force ANSI compliance +0 +1 +74 +MCState +75 +WString +3 +WCC +76 +WString +33 +?????Disable stack depth checking +0 +1 +77 +MVState +78 +WString +3 +WCC +79 +WString +23 +?????Macro definitions: +0 +80 +WString +31 +OPEN_WATCOM_FLASH_LITE_186_PORT +0 +81 +MCState +82 +WString +3 +WCC +83 +WString +34 +?????Change char default to signed +0 +1 +84 +MRState +85 +WString +3 +WCC +86 +WString +33 +?????Do not generate stack frames +0 +0 +87 +MRState +88 +WString +3 +WCC +89 +WString +23 +?????Generate as needed +0 +1 +90 +MRState +91 +WString +3 +WCC +92 +WString +29 +?????No debugging information +0 +1 +93 +MRState +94 +WString +3 +WCC +95 +WString +28 +?????Line number information +0 +0 +96 +MRState +97 +WString +3 +WCC +98 +WString +21 +?????Compiler default +0 +0 +99 +MRState +100 +WString +3 +WCC +101 +WString +21 +?????Compiler default +0 +0 +102 +MRState +103 +WString +3 +WCC +104 +WString +25 +?????Floating-point calls +0 +1 +105 +MCState +106 +WString +3 +WCC +107 +WString +31 +???e?SS not assumed equal to DS +0 +1 +108 +MRState +109 +WString +3 +WCC +110 +WString +9 +??6??8086 +0 +0 +111 +MRState +112 +WString +3 +WCC +113 +WString +10 +??6??80186 +0 +1 +114 +WVList +0 +-1 +1 +1 +0 +115 +MItem +19 +..\..\source\list.c +116 +WString +4 +COBJ +117 +WVList +0 +118 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+MItem +27 +..\common\include\semtest.h +260 +WString +3 +NIL +261 +WVList +0 +262 +WVList +0 +187 +1 +1 +0 +263 +MItem +26 +..\common\include\serial.h +264 +WString +3 +NIL +265 +WVList +0 +266 +WVList +0 +187 +1 +1 +0 +267 +MItem +16 +FreeRTOSConfig.h +268 +WString +3 +NIL +269 +WVList +0 +270 +WVList +0 +187 +1 +1 +0 diff --git a/20080212/Demo/Flshlite/rtosdemo.wpj b/20080212/Demo/Flshlite/rtosdemo.wpj new file mode 100644 index 000000000..c6a320465 --- /dev/null +++ b/20080212/Demo/Flshlite/rtosdemo.wpj @@ -0,0 +1,43 @@ +40 +projectIdent +0 +VpeMain +1 +WRect +-25 +-34 +10291 +10026 +2 +MProject +3 +MCommand +0 +4 +MCommand +0 +1 +5 +WFileName +12 +rtosdemo.tgt +6 +WVList +1 +7 +VComponent +8 +WRect +0 +0 +7200 +5888 +0 +0 +9 +WFileName +12 +rtosdemo.tgt +0 +19 +7 diff --git a/20080212/Demo/Flshlite/serial/serial.c b/20080212/Demo/Flshlite/serial/serial.c new file mode 100644 index 000000000..690a59cb3 --- /dev/null +++ b/20080212/Demo/Flshlite/serial/serial.c @@ -0,0 +1,490 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V1.00: + + + Call to the more efficient portSWITCH_CONTEXT() replaces the call to + taskYIELD() in the ISR. + +Changes from V1.01: + + + The semaphore task is not operational. This does nothing but check + the semaphore from ISR functionality. + + ISR modified slightly so only Rx or Tx is serviced per ISR - not both. + +Changes from V1.2.0: + + + Change so Tx uses a DMA channel, and Rx uses an interrupt. + +Changes from V1.2.3 + + + The function xPortInitMinimal() has been renamed to + xSerialPortInitMinimal() and the function xPortInit() has been renamed + to xSerialPortInit(). + +Changes from V1.2.5 + + + Reverted back to the non-DMA serial port driver, with a slightly modified + ISR. This is a better test of the scheduler mechanisms. + + A critical section is now used in vInterruptOn(). + + Flag sTxInterruptOn has been added to the port structure. This allows + checking of the interrupt enable status without performing any IO. + +Changes from V2.0.0 + + + Use portTickType in place of unsigned pdLONG for delay periods. + + Slightly more efficient vSerialSendString() implementation. + + cQueueReieveFromISR() used in place of xQueueReceive() in ISR. +*/ + +#include +#include +#include "FreeRTOS.h" +#include "queue.h" +#include "task.h" +#include "portasm.h" +#include "semphr.h" + +#define serMAX_PORTS ( ( unsigned portSHORT ) 2 ) + +#define serPORT_0_INT_REG ( 0xff44 ) +#define serPORT_0_BAUD_REG ( 0xff88 ) +#define serPORT_0_RX_REG ( 0xff86 ) +#define serPORT_0_TX_REG ( 0xff84 ) +#define serPORT_0_STATUS_REG ( 0xff82 ) +#define serPORT_0_CTRL_REG ( 0xff80 ) +#define serPORT_0_IRQ ( 0x14 ) + +#define serPORT_1_INT_REG ( 0xff42 ) +#define serPORT_1_BAUD_REG ( 0xff18 ) +#define serPORT_1_RX_REG ( 0xff16 ) +#define serPORT_1_TX_REG ( 0xff14 ) +#define serPORT_1_STATUS_REG ( 0xff12 ) +#define serPORT_1_CTRL_REG ( 0xff10 ) +#define serPORT_1_IRQ ( 0x11 ) + +#define serTX_EMPTY ( ( unsigned portSHORT ) 0x40 ) +#define serRX_READY ( ( unsigned portSHORT ) 0x80 ) + +#define serRESET_PIC( usEOI_TYPE ) portOUTPUT_WORD( ( unsigned portSHORT ) 0xff22, usEOI_TYPE ) +#define serTX_HOLD_EMPTY_INT ( ( unsigned portSHORT ) 0x100 ) + +#define serENABLE_INTERRUPTS ( ( unsigned portSHORT ) 0x80 ) +#define serMODE ( ( unsigned portSHORT ) 0x01 ) +#define serENABLE_TX_MACHINES ( ( unsigned portSHORT ) 0x40 ) +#define serENABLE_RX_MACHINES ( ( unsigned portSHORT ) 0x20 ) +#define serINTERRUPT_MASK ( ( unsigned portSHORT ) 0x08 ) +#define serCLEAR_ALL_STATUS_BITS ( ( unsigned portSHORT ) 0x00 ) +#define serINTERRUPT_PRIORITY ( ( unsigned portSHORT ) 0x01 ) /*< Just below the scheduler priority. */ + +#define serDONT_BLOCK ( ( portTickType ) 0 ) + +typedef enum +{ + serCOM1 = 0, + serCOM2, + serCOM3, + serCOM4, + serCOM5, + serCOM6, + serCOM7, + serCOM8 +} eCOMPort; + +typedef enum +{ + serNO_PARITY, + serODD_PARITY, + serEVEN_PARITY, + serMARK_PARITY, + serSPACE_PARITY +} eParity; + +typedef enum +{ + serSTOP_1, + serSTOP_2 +} eStopBits; + +typedef enum +{ + serBITS_5, + serBITS_6, + serBITS_7, + serBITS_8 +} eDataBits; + +typedef enum +{ + ser50 = 0, + ser75, + ser110, + ser134, + ser150, + ser200, + ser300, + ser600, + ser1200, + ser1800, + ser2400, + ser4800, + ser9600, + ser19200, + ser38400, + ser57600, + ser115200 +} eBaud; + +/* Must be same order as eBaud definitions. */ +static const unsigned portSHORT usBaudRateDivisor[] = +{ + 0, /* Not sure if the first 6 are correct. First cannot be used. */ + 29127, + 19859, + 16302, + 14564, + 10923, + 6879, + 3437, + 1718, + 1145, + 859, + 429, + 214, + 107, + 54, + 35, + 18 +}; + + +typedef struct xCOM_PORT +{ + /* Hardware parameters for this port. */ + portSHORT sTxInterruptOn; + unsigned portSHORT usIntReg; + unsigned portSHORT usBaudReg; + unsigned portSHORT usRxReg; + unsigned portSHORT usTxReg; + unsigned portSHORT usStatusReg; + unsigned portSHORT usCtrlReg; + + unsigned portSHORT usIRQVector; + + /* Queues used for communications with com test task. */ + xQueueHandle xRxedChars; + xQueueHandle xCharsForTx; + + /* This semaphore does nothing useful except test a feature of the + scheduler. */ + xSemaphoreHandle xTestSem; + +} xComPort; + +static xComPort xPorts[ serMAX_PORTS ] = +{ + { pdFALSE, serPORT_0_INT_REG, serPORT_0_BAUD_REG, serPORT_0_RX_REG, serPORT_0_TX_REG, serPORT_0_STATUS_REG, serPORT_0_CTRL_REG, serPORT_0_IRQ, NULL, NULL, NULL }, + { pdFALSE, serPORT_1_INT_REG, serPORT_1_BAUD_REG, serPORT_1_RX_REG, serPORT_1_TX_REG, serPORT_1_STATUS_REG, serPORT_1_CTRL_REG, serPORT_1_IRQ, NULL, NULL, NULL } +}; + +typedef xComPort * xComPortHandle; + +/* These prototypes are repeated here so we don't have to include the serial header. This allows +the xComPortHandle structure details to be private to this file. */ +xComPortHandle xSerialPortInit( eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits, unsigned portBASE_TYPE uxBufferLength ); +portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, portCHAR *pcRxedChar, portTickType xBlockTime ); +portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, portCHAR cOutChar, portTickType xBlockTime ); +void vSerialClose( xComPortHandle xPort ); +portSHORT sSerialWaitForSemaphore( xComPortHandle xPort ); +/*-----------------------------------------------------------*/ + +static portSHORT xComPortISR( xComPort * const pxPort ); + +#define vInterruptOn( pxPort, usInterrupt ) \ +{ \ +unsigned portSHORT usIn; \ + \ + portENTER_CRITICAL(); \ + { \ + if( pxPort->sTxInterruptOn == pdFALSE ) \ + { \ + usIn = portINPUT_WORD( pxPort->usCtrlReg ); \ + portOUTPUT_WORD( pxPort->usCtrlReg, usIn | usInterrupt ); \ + \ + pxPort->sTxInterruptOn = pdTRUE; \ + } \ + } \ + portEXIT_CRITICAL(); \ +} +/*-----------------------------------------------------------*/ + +#define vInterruptOff( pxPort, usInterrupt ) \ +{ \ + unsigned portSHORT usIn = portINPUT_WORD( pxPort->usCtrlReg ); \ + if( usIn & usInterrupt ) \ + { \ + portOUTPUT_WORD( pxPort->usCtrlReg, usIn & ~usInterrupt); \ + pxPort->sTxInterruptOn = pdFALSE; \ + } \ +} +/*-----------------------------------------------------------*/ + + +/* Define an interrupt handler for each port */ +#define COM_IRQ_WRAPPER(N) \ + static void __interrupt COM_IRQ##N##_WRAPPER( void ) \ + { \ + if( xComPortISR( &( xPorts[##N##] ) ) ) \ + { \ + portSWITCH_CONTEXT(); \ + } \ + } + + + +COM_IRQ_WRAPPER( 0 ) +COM_IRQ_WRAPPER( 1 ) + +static pxISR xISRs[ serMAX_PORTS ] = +{ + COM_IRQ0_WRAPPER, + COM_IRQ1_WRAPPER +}; + +/*-----------------------------------------------------------*/ + +xComPortHandle xSerialPortInit( eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits, unsigned portBASE_TYPE uxBufferLength ) +{ +unsigned portSHORT usPort; +xComPortHandle pxPort = NULL; + +/* BAUDDIV = ( Microprocessor Clock / Baud Rate ) / 16 */ + + /* Only n, 8, 1 is supported so these parameters are not required for this + port. */ + ( void ) eWantedParity; + ( void ) eWantedDataBits; + ( void ) eWantedStopBits; + + /* Currently only n,8,1 is supported. */ + + usPort = ( unsigned portSHORT ) ePort; + + if( usPort < serMAX_PORTS ) + { + pxPort = &( xPorts[ usPort ] ); + + portENTER_CRITICAL(); + { + unsigned portSHORT usInWord; + + /* Create the queues used by the com test task. */ + pxPort->xRxedChars = xQueueCreate( uxBufferLength, ( unsigned portBASE_TYPE ) sizeof( portCHAR ) ); + pxPort->xCharsForTx = xQueueCreate( uxBufferLength, ( unsigned portBASE_TYPE ) sizeof( portCHAR ) ); + + /* Create the test semaphore. This does nothing useful except test a feature of the scheduler. */ + vSemaphoreCreateBinary( pxPort->xTestSem ); + + /* There is no ISR here already to restore later. */ + _dos_setvect( ( portSHORT ) pxPort->usIRQVector, xISRs[ usPort ] ); + + usInWord = portINPUT_WORD( pxPort->usIntReg ); + usInWord &= ~serINTERRUPT_MASK; + usInWord |= serINTERRUPT_PRIORITY; + portOUTPUT_WORD( pxPort->usIntReg, usInWord ); + + portOUTPUT_WORD( pxPort->usBaudReg, usBaudRateDivisor[ eWantedBaud ] ); + portOUTPUT_WORD( pxPort->usCtrlReg, serENABLE_INTERRUPTS | serMODE | serENABLE_TX_MACHINES | serENABLE_RX_MACHINES ); + + portOUTPUT_WORD( pxPort->usStatusReg, serCLEAR_ALL_STATUS_BITS ); + } + portEXIT_CRITICAL(); + } + + return pxPort; +} /*lint !e715 Some parameters are not used as only a subset of the serial port functionality is currently implemented. */ +/*-----------------------------------------------------------*/ + +void vSerialPutString( xComPortHandle pxPort, const portCHAR * const pcString, unsigned portSHORT usStringLength ) +{ +unsigned portSHORT usByte; +portCHAR *pcNextChar; + + pcNextChar = ( portCHAR * ) pcString; + + for( usByte = 0; usByte < usStringLength; usByte++ ) + { + xQueueSend( pxPort->xCharsForTx, pcNextChar, serDONT_BLOCK ); + pcNextChar++; + } + + vInterruptOn( pxPort, serTX_HOLD_EMPTY_INT ); +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, portCHAR *pcRxedChar, portTickType xBlockTime ) +{ + /* Get the next character from the buffer, note that this routine is only + called having checked that the is (at least) one to get */ + if( xQueueReceive( pxPort->xRxedChars, pcRxedChar, xBlockTime ) ) + { + return pdTRUE; + } + else + { + return pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, portCHAR cOutChar, portTickType xBlockTime ) +{ + if( xQueueSend( pxPort->xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) + { + return pdFAIL; + } + + vInterruptOn( pxPort, serTX_HOLD_EMPTY_INT ); + + return pdPASS; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xSerialWaitForSemaphore( xComPortHandle xPort ) +{ +const portTickType xBlockTime = ( portTickType ) 0xffff; + + /* This function does nothing interesting, but test the + semaphore from ISR mechanism. */ + return xSemaphoreTake( xPort->xTestSem, xBlockTime ); +} +/*-----------------------------------------------------------*/ + +void vSerialClose( xComPortHandle xPort ) +{ +unsigned portSHORT usOutput; + + /* Turn off the interrupts. We may also want to delete the queues and/or + re-install the original ISR. */ + + portENTER_CRITICAL(); + { + usOutput = portINPUT_WORD( xPort->usCtrlReg ); + + usOutput &= ~serENABLE_INTERRUPTS; + usOutput &= ~serENABLE_TX_MACHINES; + usOutput &= ~serENABLE_RX_MACHINES; + portOUTPUT_WORD( xPort->usCtrlReg, usOutput ); + + usOutput = portINPUT_WORD( xPort->usIntReg ); + usOutput |= serINTERRUPT_MASK; + portOUTPUT_WORD( xPort->usIntReg, usOutput ); + } + portEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +static portBASE_TYPE xComPortISR( xComPort * const pxPort ) +{ +unsigned portSHORT usStatusRegister; +portCHAR cChar; +portBASE_TYPE xTaskWokenByPost = pdFALSE, xAnotherTaskWokenByPost = pdFALSE, xTaskWokenByTx = pdFALSE, xContinue = pdTRUE; + + /* NOTE: THIS IS NOT AN EFFICIENT ISR AS IT IS DESIGNED SOLELY TO TEST + THE SCHEDULER FUNCTIONALITY. REAL APPLICATIONS SHOULD NOT USE THIS + FUNCTION. */ + + + while( xContinue == pdTRUE ) + { + xContinue = pdFALSE; + usStatusRegister = portINPUT_WORD( pxPort->usStatusReg ); + + if( usStatusRegister & serRX_READY ) + { + cChar = ( portCHAR ) portINPUT_WORD( pxPort->usRxReg ); + xTaskWokenByPost = xQueueSendFromISR( pxPort->xRxedChars, &cChar, xTaskWokenByPost ); + + /* Also release the semaphore - this does nothing interesting and is just a test. */ + xAnotherTaskWokenByPost = xSemaphoreGiveFromISR( pxPort->xTestSem, xAnotherTaskWokenByPost ); + + /* We have performed an action this cycle - there may be other to perform. */ + xContinue = pdTRUE; + } + + if( pxPort->sTxInterruptOn && ( usStatusRegister & serTX_EMPTY ) ) + { + if( xQueueReceiveFromISR( pxPort->xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE ) + { + portOUTPUT_WORD( pxPort->usTxReg, ( unsigned portSHORT ) cChar ); + + /* We have performed an action this cycle - there may be others to perform. */ + xContinue = pdTRUE; + } + else + { + /* Queue empty, nothing to send */ + vInterruptOff( pxPort, serTX_HOLD_EMPTY_INT ); + } + } + } + + serRESET_PIC( pxPort->usIRQVector ); + + /* If posting to the queue woke a task that was blocked on the queue we may + want to switch to the woken task - depending on its priority relative to + the task interrupted by this ISR. */ + if( xTaskWokenByPost || xAnotherTaskWokenByPost || xTaskWokenByTx) + { + return pdTRUE; + } + else + { + return pdFALSE; + } +} + + + + + diff --git a/20080212/Demo/H8S/RTOSDemo.hws b/20080212/Demo/H8S/RTOSDemo.hws new file mode 100644 index 000000000..8899830b2 --- /dev/null +++ b/20080212/Demo/H8S/RTOSDemo.hws @@ -0,0 +1,38 @@ +[HIMDBVersion] +2.0 +[DATABASE_VERSION] +"7.0" +[WORKSPACE_DETAILS] +"RTOSDemo" "C:\E\Dev\FreeRTOS\Demo\H8S" "C:\E\Dev\FreeRTOS\Demo\H8S\RTOSDemo.hws" "H8S,H8/300" "KPIT GNUH8 [ELF]" +[SHARED_WORKSPACE_CONTROL_STATUS] +"" "" "" +"" "" "" +[PROJECTS] +"RTOSDemo" "C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo" "C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\rtosdemo.hwp" 0 +[INFORMATION] +"No workspace information available" +[SCRAP] +[PROJECT_DEPENDENCY] +[WORKSPACE_PROPERTIES] +[VCS] +"" "" "" 0 +[VCS_PROJECT] +[HELP_FILES] +[GENERAL_DATA_PROJECT] +[SYSMENUTOOLS] +"GNUH8 Archive Editor" "1.1" +"Hitachi Mapview" "1.0" +"Hitachi H Series Librarian Interface" "1.1" +"Hitachi Call Walker" "1.1" +[USERMENUTOOLS] +[CUSTOMPLACEHOLDERS] +[MAKEFILE_BUILD_INFO] +"$(WORKSPDIR)\make\$(WORKSPNAME).mak" "" 0 0 +[VD_CONFIGURATION_OPTIONS] +"ACTIVE_DESKTOP" "0" +[VD_CONFIGURATIONS] +"0" "Default1" "1" +"1" "Default2" "1" +"2" "Default3" "1" +"3" "Default4" "1" +[END] diff --git a/20080212/Demo/H8S/RTOSDemo.tws b/20080212/Demo/H8S/RTOSDemo.tws new file mode 100644 index 000000000..8815cdd95 --- /dev/null +++ b/20080212/Demo/H8S/RTOSDemo.tws @@ -0,0 +1,28 @@ +[HIMDBVersion] +2.0 +[DATABASE_VERSION] +"1.0" +[CURRENT_PROJECT] +"RTOSDemo" +[GENERAL_DATA] +"EDITOR_WINDOWS_MAXIMISED" "1" +[BREAKPOINTS] +[OPEN_WORKSPACE_FILES] +"C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\partest\partest.c" +"c:\e\Dev\FreeRTOS\Source\queue.c" +"C:\E\Dev\FreeRTOS\Source\portable\GCC\H8S2329\portmacro.h" +"C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\serial\serial.c" +"c:\e\Dev\FreeRTOS\Source\portable\GCC\H8S2329\port.c" +"C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\main.c" +"C:\E\Dev\FreeRTOS\Source\include\portable.h" +"c:\e\Dev\FreeRTOS\Demo\Common\Minimal\BlockQ.c" +[WORKSPACE_FILE_STATES] +"c:\e\Dev\FreeRTOS\Demo\Common\Minimal\BlockQ.c" "0,0,954,459,0" +"C:\E\Dev\FreeRTOS\Source\include\portable.h" "44,66,958,463,0" +"C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\partest\partest.c" "-4,-34,1098,699,1" +"C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\main.c" "66,99,958,463,0" +"c:\e\Dev\FreeRTOS\Source\portable\GCC\H8S2329\port.c" "88,132,958,463,0" +"C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\serial\serial.c" "110,165,958,463,0" +"C:\E\Dev\FreeRTOS\Source\portable\GCC\H8S2329\portmacro.h" "132,198,958,463,0" +"c:\e\Dev\FreeRTOS\Source\queue.c" "0,0,958,463,0" +[END] diff --git a/20080212/Demo/H8S/RTOSDemo/2329S.h b/20080212/Demo/H8S/RTOSDemo/2329S.h new file mode 100644 index 000000000..eafb53788 --- /dev/null +++ b/20080212/Demo/H8S/RTOSDemo/2329S.h @@ -0,0 +1,142 @@ +#ifndef INC_2329_H +#define INC_2329_H + +/* DATA TYPES MIGHT NOT BE CORRECT. */ + +#define BASE2329 0xFF0000 + +/* Definitions for GPIO. */ + +#define P1DDR ( *( ( volatile unsigned char * ) 0xFFFEB0 ) ) +#define P1DR ( *( ( volatile unsigned char * ) 0xFFFF60 ) ) +#define PORT1 ( *( ( volatile unsigned char * ) 0xFFFF50 ) ) +#define P2DDR ( *( ( volatile unsigned char * ) 0xFFFEB1 ) ) +#define P2DR ( *( ( volatile unsigned char * ) 0xFFFF61 ) ) +#define PORT2 ( *( ( volatile unsigned char * ) 0xFFFF51 ) ) +#define P3DDR ( *( ( volatile unsigned char * ) 0xFFFEB2 ) ) +#define P3DR ( *( ( volatile unsigned char * ) 0xFFFF62 ) ) +#define PORT3 ( *( ( volatile unsigned char * ) 0xFFFF52 ) ) +#define P3ODR ( *( ( volatile unsigned char * ) 0xFFFF76 ) ) +#define PORT4 ( *( ( volatile unsigned char * ) 0xFFFF53 ) ) +#define P5DDR ( *( ( volatile unsigned char * ) 0xFFFEB4 ) ) +#define P5DR ( *( ( volatile unsigned char * ) 0xFFFF64 ) ) +#define PORT5 ( *( ( volatile unsigned char * ) 0xFFFF54 ) ) +#define PFCR2 ( *( ( volatile unsigned char * ) 0xFFFFAC ) ) +#define SYSCR ( *( ( volatile unsigned char * ) 0xFFFF39 ) ) +#define P6DDR ( *( ( volatile unsigned char * ) 0xFFFEB5 ) ) +#define P6DR ( *( ( volatile unsigned char * ) 0xFFFF65 ) ) +#define PORT6 ( *( ( volatile unsigned char * ) 0xFFFF55 ) ) +#define PFCR2 ( *( ( volatile unsigned char * ) 0xFFFFAC ) ) +#define PADDR ( *( ( volatile unsigned char * ) 0xFFFEB9 ) ) +#define PADR ( *( ( volatile unsigned char * ) 0xFFFF69 ) ) +#define PORTA ( *( ( volatile unsigned char * ) 0xFFFF59 ) ) +#define PAPCR ( *( ( volatile unsigned char * ) 0xFFFF70 ) ) +#define PAODR ( *( ( volatile unsigned char * ) 0xFFFF77 ) ) +#define PFCR1 ( *( ( volatile unsigned char * ) 0xFFFF45 ) ) +#define PBDDR ( *( ( volatile unsigned char * ) 0xFFFEBA ) ) +#define PBDR ( *( ( volatile unsigned char * ) 0xFFFF6A ) ) +#define PORTB ( *( ( volatile unsigned char * ) 0xFFFF5A ) ) +#define PBPCR ( *( ( volatile unsigned char * ) 0xFFFF71 ) ) +#define PCDDR ( *( ( volatile unsigned char * ) 0xFFFEBB ) ) +#define PCDR ( *( ( volatile unsigned char * ) 0xFFFF6B ) ) +#define PORTC ( *( ( volatile unsigned char * ) 0xFFFF5B ) ) +#define PCPCR ( *( ( volatile unsigned char * ) 0xFFFF72 ) ) +#define PDDDR ( *( ( volatile unsigned char * ) 0xFFFEBC ) ) +#define PDDR ( *( ( volatile unsigned char * ) 0xFFFF6C ) ) +#define PORTD ( *( ( volatile unsigned char * ) 0xFFFF5C ) ) +#define PDPCR ( *( ( volatile unsigned char * ) 0xFFFF73 ) ) +#define PEDDR ( *( ( volatile unsigned char * ) 0xFFFEBD ) ) +#define PEDR ( *( ( volatile unsigned char * ) 0xFFFF6D ) ) +#define PORTE ( *( ( volatile unsigned char * ) 0xFFFF5D ) ) +#define PEPCR ( *( ( volatile unsigned char * ) 0xFFFF74 ) ) +#define PFDDR ( *( ( volatile unsigned char * ) 0xFFFEBE ) ) +#define PFDR ( *( ( volatile unsigned char * ) 0xFFFF6E ) ) +#define PORTF ( *( ( volatile unsigned char * ) 0xFFFF5E ) ) +#define PFCR2 ( *( ( volatile unsigned char * ) 0xFFFFAC ) ) +#define SYSCR ( *( ( volatile unsigned char * ) 0xFFFF39 ) ) +#define PGDDR ( *( ( volatile unsigned char * ) 0xFFFEBF ) ) +#define PGDR ( *( ( volatile unsigned char * ) 0xFFFF6F ) ) +#define PORTG ( *( ( volatile unsigned char * ) 0xFFFF5F ) ) +#define PFCR2 ( *( ( volatile unsigned char * ) 0xFFFFAC ) ) + + +/* Definitions for TPU. */ + +#define TCR0 ( *( ( volatile unsigned char * ) 0xFFFFD0 ) ) +#define TMDR0 ( *( ( volatile unsigned char * ) 0xFFFFD1 ) ) +#define TIOR0H ( *( ( volatile unsigned char * ) 0xFFFFD2 ) ) +#define TIOR0L ( *( ( volatile unsigned char * ) 0xFFFFD3 ) ) +#define TIER0 ( *( ( volatile unsigned char * ) 0xFFFFD4 ) ) +#define TSR0 ( *( ( volatile unsigned char * ) 0xFFFFD5 ) ) +#define TCNT0 ( *( ( volatile unsigned short * ) 0xFFFFD6 ) ) +#define TGR0A ( *( ( volatile unsigned short * ) 0xFFFFD8 ) ) +#define TGR0B ( *( ( volatile unsigned short * ) 0xFFFFDA ) ) +#define TGR0C ( *( ( volatile unsigned short * ) 0xFFFFDC ) ) +#define TGR0D ( *( ( volatile unsigned short * ) 0xFFFFDE ) ) +#define TCR1 ( *( ( volatile unsigned char * ) 0xFFFFE0 ) ) +#define TMDR1 ( *( ( volatile unsigned char * ) 0xFFFFE1 ) ) +#define TIOR1 ( *( ( volatile unsigned char * ) 0xFFFFE2 ) ) +#define TIER1 ( *( ( volatile unsigned char * ) 0xFFFFE4 ) ) +#define TSR1 ( *( ( volatile unsigned char * ) 0xFFFFE5 ) ) +#define TCNT1 ( *( ( volatile unsigned short * ) 0xFFFFE6 ) ) +#define TGR1A ( *( ( volatile unsigned short * ) 0xFFFFE8 ) ) +#define TGR1B ( *( ( volatile unsigned short * ) 0xFFFFEA ) ) +#define TCR2 ( *( ( volatile unsigned char * ) 0xFFFFF0 ) ) +#define TMDR2 ( *( ( volatile unsigned char * ) 0xFFFFF1 ) ) +#define TIOR2 ( *( ( volatile unsigned char * ) 0xFFFFF2 ) ) +#define TIER2 ( *( ( volatile unsigned char * ) 0xFFFFF4 ) ) +#define TSR2 ( *( ( volatile unsigned char * ) 0xFFFFF5 ) ) +#define TCNT2 ( *( ( volatile unsigned short * ) 0xFFFFF6 ) ) +#define TGR2A ( *( ( volatile unsigned short * ) 0xFFFFF8 ) ) +#define TGR2B ( *( ( volatile unsigned short * ) 0xFFFFFA ) ) +#define TCR3 ( *( ( volatile unsigned char * ) 0xFFFE80 ) ) +#define TMDR3 ( *( ( volatile unsigned char * ) 0xFFFE81 ) ) +#define TIOR3H ( *( ( volatile unsigned char * ) 0xFFFE82 ) ) +#define TIOR3L ( *( ( volatile unsigned char * ) 0xFFFE83 ) ) +#define TIER3 ( *( ( volatile unsigned char * ) 0xFFFE84 ) ) +#define TSR3 ( *( ( volatile unsigned char * ) 0xFFFE85 ) ) +#define TCNT3 ( *( ( volatile unsigned short * ) 0xFFFE86 ) ) +#define TGR3A ( *( ( volatile unsigned short * ) 0xFFFE88 ) ) +#define TGR3B ( *( ( volatile unsigned short * ) 0xFFFE8A ) ) +#define TGR3C ( *( ( volatile unsigned short * ) 0xFFFE8C ) ) +#define TGR3D ( *( ( volatile unsigned short * ) 0xFFFE8E ) ) +#define TCR4 ( *( ( volatile unsigned char * ) 0xFFFE90 ) ) +#define TMDR4 ( *( ( volatile unsigned char * ) 0xFFFE91 ) ) +#define TIOR4 ( *( ( volatile unsigned char * ) 0xFFFE92 ) ) +#define TIER4 ( *( ( volatile unsigned char * ) 0xFFFE94 ) ) +#define TSR4 ( *( ( volatile unsigned char * ) 0xFFFE95 ) ) +#define TCNT4 ( *( ( volatile unsigned short * ) 0xFFFE96 ) ) +#define TGR4A ( *( ( volatile unsigned short * ) 0xFFFE98 ) ) +#define TGR4B ( *( ( volatile unsigned short * ) 0xFFFE9A ) ) +#define TCR5 ( *( ( volatile unsigned char * ) 0xFFFEA0 ) ) +#define TMDR5 ( *( ( volatile unsigned char * ) 0xFFFEA1 ) ) +#define TIOR5 ( *( ( volatile unsigned char * ) 0xFFFEA2 ) ) +#define TIER5 ( *( ( volatile unsigned char * ) 0xFFFEA4 ) ) +#define TSR5 ( *( ( volatile unsigned char * ) 0xFFFEA5 ) ) +#define TCNT5 ( *( ( volatile unsigned short * ) 0xFFFEA6 ) ) +#define TGR5A ( *( ( volatile unsigned short * ) 0xFFFEA8 ) ) +#define TGR5B ( *( ( volatile unsigned short * ) 0xFFFEAA ) ) +#define TSTR ( *( ( volatile unsigned char * ) 0xFFFFC0 ) ) +#define TSYR ( *( ( volatile unsigned char * ) 0xFFFFC1 ) ) + + +#define MSTPCR ( *( ( volatile unsigned short * ) 0xFFFF3C ) ) +#define SCKCR ( *( ( volatile unsigned short * ) 0xFFFF3A ) ) + +/* Serial port. */ + +#define SMR0 ( *( ( volatile unsigned char * ) 0xFFFF78 ) ) +#define BRR0 ( *( ( volatile unsigned char * ) 0xFFFF79 ) ) +#define SCR0 ( *( ( volatile unsigned char * ) 0xFFFF7A ) ) +#define TDR0 ( *( ( volatile unsigned char * ) 0xFFFF7B ) ) +#define SSR0 ( *( ( volatile unsigned char * ) 0xFFFF7C ) ) +#define RDR0 ( *( ( volatile unsigned char * ) 0xFFFF7D ) ) +#define SCMR0 ( *( ( volatile unsigned char * ) 0xFFFF7E ) ) +#define SMR1 ( *( ( volatile unsigned char * ) 0xFFFF80 ) ) +#define BRR1 ( *( ( volatile unsigned char * ) 0xFFFF81 ) ) +#define SCR1 ( *( ( volatile unsigned char * ) 0xFFFF82 ) ) +#define TDR1 ( *( ( volatile unsigned char * ) 0xFFFF83 ) ) +#define SSR1 ( *( ( volatile unsigned char * ) 0xFFFF84 ) ) +#define RDR1 ( *( ( volatile unsigned char * ) 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b/20080212/Demo/H8S/RTOSDemo/Debug/gnuconfig.ini @@ -0,0 +1,6 @@ +[HEWGNUBARNEYMCGREW] +SELECTEDCPU=H8/S2000 +SELECTEDMODE=Advanced +INT32=N +SELECTEDRENESAS=N +SELECTEDENDIAN=Big endian diff --git a/20080212/Demo/H8S/RTOSDemo/FreeRTOSConfig.h b/20080212/Demo/H8S/RTOSDemo/FreeRTOSConfig.h new file mode 100644 index 000000000..293fb016e --- /dev/null +++ b/20080212/Demo/H8S/RTOSDemo/FreeRTOSConfig.h @@ -0,0 +1,91 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/* IO definitions for the chosen device. */ +#include <2329S.h> + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 22118400 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 200 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 15 * 1024 ) ) +#define configMAX_TASK_NAME_LEN ( 8 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 1 +#define configIDLE_SHOULD_YIELD 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + + + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/H8S/RTOSDemo/ParTest/ParTest.c b/20080212/Demo/H8S/RTOSDemo/ParTest/ParTest.c new file mode 100644 index 000000000..b76dafc03 --- /dev/null +++ b/20080212/Demo/H8S/RTOSDemo/ParTest/ParTest.c @@ -0,0 +1,156 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "portable.h" + +/* Demo application include files. */ +#include "partest.h" + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + * + * This is for the demo application which uses port 2 for LED outputs. + *-----------------------------------------------------------*/ + +/* Value for the LED to be off. */ +#define partstLED_OUTPUTS ( ( unsigned portCHAR ) 0xff ) + +/* P2.0 is not used as an output so there are only 7 LEDs on port 2. */ +#define partstMAX_LEDs ( 7 ) +#define partstALL_OUTPUTS_OFF ( ( unsigned portCHAR ) 0 ) + +/* Maps the LED outputs used by the standard demo application files to +convenient outputs for the EDK2329. Mainly this insures that the LED +used by the Check task is one of the on board LEDs so the demo can be +executed on an EDK without any modification. */ +static inline unsigned portCHAR prvMapLED( unsigned portBASE_TYPE uxLED ); + +/*-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ + /* LED's are connected to port 2. P2.1 and P2.2 are built onto the EDK. + P2.3 to P2.7 are soldered onto the expansion port. */ + P2DDR = partstLED_OUTPUTS; + P2DR = partstALL_OUTPUTS_OFF; +} +/*-----------------------------------------------------------*/ + +/* + * Described at the top of the file. + */ +static inline unsigned portCHAR prvMapLED( unsigned portBASE_TYPE uxLED ) +{ + switch( uxLED ) + { + case 0 : return ( unsigned portCHAR ) 2; + case 1 : return ( unsigned portCHAR ) 3; + case 2 : return ( unsigned portCHAR ) 4; + case 3 : return ( unsigned portCHAR ) 5; + case 4 : return ( unsigned portCHAR ) 6; + case 5 : return ( unsigned portCHAR ) 0; + case 6 : return ( unsigned portCHAR ) 1; + default : return 0; + } +} +/*-----------------------------------------------------------*/ + +/* + * Turn an LED on or off. + */ +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ +unsigned portCHAR ucLED; + + if( uxLED < partstMAX_LEDs ) + { + ucLED = prvMapLED( uxLED ); + + /* Set a bit in the required LED position. LED 0 is bit 1. */ + ucLED = ( unsigned portCHAR ) 1 << ( ucLED + 1 ); + + if( xValue ) + { + portENTER_CRITICAL(); + P2DR |= ucLED; + portEXIT_CRITICAL(); + } + else + { + portENTER_CRITICAL(); + P2DR &= ~ucLED; + portEXIT_CRITICAL(); + } + } +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned portCHAR ucLED; + + if( uxLED < partstMAX_LEDs ) + { + ucLED = prvMapLED( uxLED ); + + /* Set a bit in the required LED position. LED 0 is bit 1. */ + ucLED = ( unsigned portCHAR ) 1 << ( ucLED + 1 ); + + portENTER_CRITICAL(); + { + if( P2DR & ucLED ) + { + P2DR &= ~ucLED; + } + else + { + P2DR |= ucLED; + } + } + portEXIT_CRITICAL(); + } +} + + + diff --git a/20080212/Demo/H8S/RTOSDemo/RTOSDemo.hwp b/20080212/Demo/H8S/RTOSDemo/RTOSDemo.hwp new file mode 100644 index 000000000..0181e689d --- /dev/null +++ b/20080212/Demo/H8S/RTOSDemo/RTOSDemo.hwp @@ -0,0 +1,243 @@ +[HIMDBVersion] +2.0 +[DATABASE_VERSION] +"2.7" +[PROJECT_DETAILS] +"RTOSDemo" "C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo" "C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\rtosdemo.hwp" "H8S,H8/300" "KPIT GNUH8 [ELF]" "C Application" "" "" +[INFORMATION] +"No project information available" +[TOOL_CHAIN] +"KPIT GNUH8 [ELF] Toolchain" "v0601" +[CONFIGURATIONS] +"Release" "C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\release" +"Debug" "C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\debug" +[BUILD_PHASES] +"GNU Assembler" 1 +"GNU Compiler" 1 +"GNU Linker" 1 +[DEFINITION_PARSERS] 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+[LINKAGE_ORDER_Debug] +[BUILD_FILE_ORDER_Linker output file] +[BUILD_FILE_ORDER_C header file] +[BUILD_FILE_ORDER_S-Record file] +[BUILD_FILE_ORDER_Linker map file] +[GENERAL_DATA_CONFIGURATION_Release] +[BUILD_FILE_ORDER_Object file] +[GENERAL_DATA_CONFIGURATION_SESSION_Debug_Simulator] +[GENERAL_DATA_CONFIGURATION_SESSION_Release_Release session] +[GENERAL_DATA_CONFIGURATION_SESSION_Release_Simulator] +[GENERAL_DATA_CONFIGURATION_SESSION_Debug_Release session] +[BUILD_FILE_ORDER_Archive file] +[EXCLUDED_FILES_Release] +[BUILD_FILE_ORDER_C++ header file] +[GENERAL_DATA_CONFIGURATION_Debug] +[LINKAGE_ORDER_Release] +[END] diff --git a/20080212/Demo/H8S/RTOSDemo/RTOSDemo.tps b/20080212/Demo/H8S/RTOSDemo/RTOSDemo.tps new file mode 100644 index 000000000..fb0b77171 --- /dev/null +++ b/20080212/Demo/H8S/RTOSDemo/RTOSDemo.tps @@ -0,0 +1,33 @@ +[HIMDBVersion] +2.0 +[DATABASE_VERSION] +"1.1" +[SESSIONS_] +"Release session" +"Simulator" +[CONFIGURATIONS] +"Debug" +"Release" +[CURRENT_CONFIGURATION] +"Release" +[CURRENT_SESSION] +"Release session" +[GENERAL_DATA_PROJECT] +"FDT_UserBootAreaFiles" "" +[GENERAL_DATA_CONFIGURATION_Debug] +"PROJECT_FILES_MODIFIED_DATA_TAG" "TRUE" +[SESSIONS_Debug] +"Release session" +"Simulator" +[GENERAL_DATA_CONFIGURATION_Release] +"PROJECT_FILES_MODIFIED_DATA_TAG" "FALSE" +[SESSIONS_Release] +"Release session" +"Simulator" +[GENERAL_DATA_CONFIGURATION_SESSION_Debug_Simulator] +[GENERAL_DATA_SESSION_Release session] +[GENERAL_DATA_CONFIGURATION_SESSION_Release_Release session] +[GENERAL_DATA_CONFIGURATION_SESSION_Release_Simulator] +[GENERAL_DATA_SESSION_Simulator] +[GENERAL_DATA_CONFIGURATION_SESSION_Debug_Release session] +[END] diff --git a/20080212/Demo/H8S/RTOSDemo/Release session.hsf b/20080212/Demo/H8S/RTOSDemo/Release session.hsf new file mode 100644 index 000000000..496933dae --- /dev/null +++ b/20080212/Demo/H8S/RTOSDemo/Release session.hsf @@ -0,0 +1,247 @@ +[HIMDBVersion] +2.0 +[DATABASE_VERSION] +"2.0" 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+"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryCtrlDataCount0" "4" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWndViewBInstanceKey0" "{WK_00000001_REGISTER}ViewB" +"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_BREAK_PC_BREAK_COUNT" "0" +"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_SYSTEM_CALL_SYSTEM_CALL_ADDRESS" "0x00000000" +"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_CONFIG_ENDIAN" "BIG" +"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_COUNT" "11" +"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP1" "0x00FF7C00,0x00FFFBFF, 8, 3,RAM" +"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_BREAK_BREAK_SEQUENCE_COUNT" "0" +"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd1ColWidth1" "250" +"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE_COMB_BUFFER" ",,,," +"{48FF5DA0-6FFA-11D5-B7CE-00E029352378}CoverageCtrlViews" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ColWidth1" "100" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH" "pxCreatedTask," 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"0x00000000" +"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP3" "0x00FFFF28,0x00FFFFFF, 8, 2,RAM" +"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONTROL_REGS_CREG0" "0x00FFFF39,2,0x00000101" +"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ImageCtrlViews" "0" +"{48FF5DA0-6FFA-11D5-B7CE-00E029352378}CoverageCtrlViewsFromDiffFile" "0" +"{EEDC9301-6FBE-11D5-8613-00A024591A38}StackTraceCtrlViews" "0" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ColWidth3" "100" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ScrollHorz" "0" +[LANGUAGE] +"English" +[CONFIG_INFO_VD1] +1 +[CONFIG_INFO_VD2] +0 +[CONFIG_INFO_VD3] +0 +[CONFIG_INFO_VD4] +0 +[WINDOW_POSITION_STATE_DATA_VD1] +"{WK_TB00000009_VERSIONCONTROL}" "TOOLBAR 0" 59419 0 4 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000004_TEMPLATES}" "TOOLBAR 0" 59419 0 8 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"TCL Toolkit" "WINDOW" 59422 1 0 "-1.000000" -1 -1000 -1000 -1 -1 17 0 "" "-1" +"{WK_TB00000002_EDITOR}" "TOOLBAR 0" 59419 0 2 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000012_MAP}" "TOOLBAR 0" 59419 0 3 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000017_FDT}" "TOOLBAR 0" 59419 0 1 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_00000001_MAP}RTOSDemoRelease session" "WINDOW" 59421 -1 -1 "-1.000000" -1 -1000 -1000 -1 -1 18 0 "" "-1" +"{WK_TB00000003_BOOKMARKS}" "TOOLBAR 0" 59419 1 0 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000018_DEFAULTWINDOW}" "TOOLBAR 0" 59419 1 1 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000008_DEBUGRUN}" "TOOLBAR 0" 59419 0 5 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000005_SEARCH}" "TOOLBAR 0" 59419 0 7 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_00000001_OUTPUT}" "WINDOW" 59422 0 0 "1.00" 180 0 0 350 200 18 0 "" "0.0" +"{WK_00000002_WORKSPACE}" "WINDOW" 59420 0 0 "1.00" 280 0 0 350 200 18 0 "" "0.0" +"{WK_TB00000001_STANDARD}" "TOOLBAR 0" 59419 0 0 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000007_DEBUG}" "TOOLBAR 0" 59419 0 6 "0.00" 0 0 0 0 0 17 0 "" "0.0" +[WINDOW_POSITION_STATE_DATA_VD2] +[WINDOW_POSITION_STATE_DATA_VD3] +[WINDOW_POSITION_STATE_DATA_VD4] +[WINDOW_Z_ORDER] +"C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\partest\partest.c" +"C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\serial\serial.c" +"c:\e\Dev\FreeRTOS\Source\queue.c" +"C:\E\Dev\FreeRTOS\Source\portable\GCC\H8S2329\portmacro.h" +"c:\e\Dev\FreeRTOS\Source\portable\GCC\H8S2329\port.c" +"C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\main.c" +"C:\E\Dev\FreeRTOS\Source\include\portable.h" +"c:\e\Dev\FreeRTOS\Demo\Common\Minimal\BlockQ.c" +[TARGET_NAME] +"" +[DEBUGGER_OPTIONS] +"" +[DOWNLOAD_MODULES] +[CONNECT_ON_GO] +"TRUE" +[DOWNLOAD_MODULES_AFTER_BUILD] +"TRUE" +[REMOVE_BREAKPOINTS_ON_DOWNLOAD] +"FALSE" +[COMMAND_FILES] +[DEFAULT_DEBUG_FORMAT] +"" +[FLASH_DETAILS] +"2212.000000" 1 -127 "B" 0 "COM1" 115200 1 "H8S/2329BF" 1 0 0 0 1 0 0 "D:\DevTools\Hitachi\FDT2.2\Kernels\ProtB\2329\hitachi\1_1_00\" "" "" "" "" +[BREAKPOINTS] +[END] diff --git a/20080212/Demo/H8S/RTOSDemo/Release/gnuconfig.ini b/20080212/Demo/H8S/RTOSDemo/Release/gnuconfig.ini new file mode 100644 index 000000000..894ac975f --- /dev/null +++ b/20080212/Demo/H8S/RTOSDemo/Release/gnuconfig.ini @@ -0,0 +1,6 @@ +[HEWGNUBARNEYMCGREW] +SELECTEDCPU=H8/S2000 +SELECTEDMODE=Advanced +INT32=N +SELECTEDRENESAS=N +SELECTEDENDIAN=Big endian diff --git a/20080212/Demo/H8S/RTOSDemo/Simulator sessions.hsf b/20080212/Demo/H8S/RTOSDemo/Simulator sessions.hsf new file mode 100644 index 000000000..96edb92f7 --- /dev/null +++ b/20080212/Demo/H8S/RTOSDemo/Simulator sessions.hsf @@ -0,0 +1,245 @@ +[HIMDBVersion] +2.0 +[DATABASE_VERSION] +"2.0" +[SESSION_DETAILS] +"" +[INFORMATION] +"" +[GENERAL_DATA] +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth1" "200" +"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewAInstanceKey0" "{WK_00000001_MEMORY}RTOSDemoSimulator" +"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd2ScrollVert" "0" +"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_COLOR" "0,0,0,0" +"{2BA6A3EE-6488-11D5-80D4-00C04F68EAD7}LabelCtrlViews" "0" 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+[COMMAND_FILES] +[DEFAULT_DEBUG_FORMAT] +"Elf/Dwarf2_KPIT" +[FLASH_DETAILS] +"2212.000000" 1 -127 "B" 0 "COM1" 115200 1 "H8S/2329BF" 1 0 0 0 1 0 0 "D:\DevTools\Hitachi\FDT2.2\Kernels\ProtB\2329\hitachi\1_1_00\" "" "" "" "" +[BREAKPOINTS] +[END] diff --git a/20080212/Demo/H8S/RTOSDemo/main.c b/20080212/Demo/H8S/RTOSDemo/main.c new file mode 100644 index 000000000..98d50c6d1 --- /dev/null +++ b/20080212/Demo/H8S/RTOSDemo/main.c @@ -0,0 +1,382 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + * Creates all the demo application tasks, then starts the scheduler. The WEB + * documentation provides more details of the demo application tasks. + * + * Main.c also creates a task called "Check". This only executes every three + * seconds but has the highest priority so is guaranteed to get processor time. + * Its main function is to check that all the other tasks are still operational. + * Each task (other than the "flash" tasks) maintains a unique count that is + * incremented each time the task successfully completes its function. Should + * any error occur within such a task the count is permanently halted. The + * check task inspects the count of each task to ensure it has changed since + * the last time the check task executed. If all the count variables have + * changed all the tasks are still executing error free, and the check task + * toggles the onboard LED. Should any task contain an error at any time + * the LED toggle rate will change from 3 seconds to 500ms. + * + * To check the operation of the memory allocator the check task also + * dynamically creates a task before delaying, and deletes it again when it + * wakes. If memory cannot be allocated for the new task the call to xTaskCreate + * will fail and an error is signalled. The dynamically created task itself + * allocates and frees memory just to give the allocator a bit more exercise. + * + */ + +/* Standard includes. */ +#include +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo application file headers. */ +#include "flash.h" +#include "integer.h" +#include "PollQ.h" +#include "comtest2.h" +#include "semtest.h" +#include "flop.h" +#include "dynamic.h" +#include "BlockQ.h" +#include "serial.h" +#include "partest.h" + +/* Priority definitions for most of the tasks in the demo application. Some +tasks just use the idle priority. */ +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) + +/* Baud rate used by the serial port tasks (ComTest tasks). */ +#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 115200 ) + +/* LED used by the serial port tasks. This is toggled on each character Tx, +and mainCOM_TEST_LED + 1 is toggles on each character Rx. */ +#define mainCOM_TEST_LED ( 3 ) + +/* LED that is toggled by the check task. The check task periodically checks +that all the other tasks are operating without error. If no errors are found +the LED is toggled with mainCHECK_PERIOD frequency. If an error is found +the the toggle rate increases to mainERROR_CHECK_PERIOD. */ +#define mainCHECK_TASK_LED ( 5 ) +#define mainCHECK_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS ) +#define mainERROR_CHECK_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS ) + +/* Constants used by the vMemCheckTask() task. */ +#define mainCOUNT_INITIAL_VALUE ( ( unsigned portLONG ) 0 ) +#define mainNO_TASK ( 0 ) + +/* The size of the memory blocks allocated by the vMemCheckTask() task. */ +#define mainMEM_CHECK_SIZE_1 ( ( size_t ) 51 ) +#define mainMEM_CHECK_SIZE_2 ( ( size_t ) 52 ) +#define mainMEM_CHECK_SIZE_3 ( ( size_t ) 151 ) + +/* + * The 'Check' task. + */ +static void vErrorChecks( void *pvParameters ); + +/* + * Checks the unique counts of other tasks to ensure they are still operational. + */ +static portLONG prvCheckOtherTasksAreStillRunning( unsigned portLONG ulMemCheckTaskCount ); + +/* + * Dynamically created and deleted during each cycle of the vErrorChecks() + * task. This is done to check the operation of the memory allocator. + * See the top of vErrorChecks for more details. + */ +static void vMemCheckTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* + * Start all the tasks then start the scheduler. + */ +int main( void ) +{ + /* Setup the LED's for output. */ + vParTestInitialise(); + + /* Start the various standard demo application tasks. */ + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); + vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartMathTasks( tskIDLE_PRIORITY ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartDynamicPriorityTasks(); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + + /* Start the 'Check' task. */ + xTaskCreate( vErrorChecks, ( signed portCHAR * )"Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* In this port, to use preemptive scheduler define configUSE_PREEMPTION + as 1 in portmacro.h. To use the cooperative scheduler define + configUSE_PREEMPTION as 0. */ + vTaskStartScheduler(); + + /* Should never get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +/* + * Cycle for ever, delaying then checking all the other tasks are still + * operating without error. If an error is detected then the delay period + * is decreased from mainCHECK_PERIOD to mainERROR_CHECK_PERIOD so + * the on board LED flash rate will increase. + * + * In addition to the standard tests the memory allocator is tested through + * the dynamic creation and deletion of a task each cycle. Each time the + * task is created memory must be allocated for its stack. When the task is + * deleted this memory is returned to the heap. If the task cannot be created + * then it is likely that the memory allocation failed. In addition the + * dynamically created task allocates and frees memory while it runs. + */ +static void vErrorChecks( void *pvParameters ) +{ +portTickType xDelayPeriod = mainCHECK_PERIOD; +volatile unsigned portLONG ulMemCheckTaskRunningCount; +xTaskHandle xCreatedTask; +portTickType xLastWakeTime; + + /* Initialise xLastWakeTime to ensure the first call to vTaskDelayUntil() + functions correctly. */ + xLastWakeTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Set ulMemCheckTaskRunningCount to a known value so we can check + later that it has changed. */ + ulMemCheckTaskRunningCount = mainCOUNT_INITIAL_VALUE; + + /* Dynamically create a task - passing ulMemCheckTaskRunningCount as a + parameter. */ + xCreatedTask = mainNO_TASK; + if( xTaskCreate( vMemCheckTask, ( signed portCHAR * ) "MEM_CHECK", configMINIMAL_STACK_SIZE, ( void * ) &ulMemCheckTaskRunningCount, tskIDLE_PRIORITY, &xCreatedTask ) != pdPASS ) + { + /* Could not create the task - we have probably run out of heap. */ + xDelayPeriod = mainERROR_CHECK_PERIOD; + } + + + /* Delay until it is time to execute again. The delay period is + shorter following an error. */ + vTaskDelayUntil( &xLastWakeTime, xDelayPeriod ); + + + /* Delete the dynamically created task. */ + if( xCreatedTask != mainNO_TASK ) + { + vTaskDelete( xCreatedTask ); + } + + /* Check all the standard demo application tasks are executing without + error. ulMemCheckTaskRunningCount is checked to ensure it was + modified by the task just deleted. */ + if( prvCheckOtherTasksAreStillRunning( ulMemCheckTaskRunningCount ) != pdPASS ) + { + /* An error has been detected in one of the tasks - flash faster. */ + xDelayPeriod = mainERROR_CHECK_PERIOD; + } + + vParTestToggleLED( mainCHECK_TASK_LED ); + } +} +/*-----------------------------------------------------------*/ + +/* + * Check each set of tasks in turn to see if they have experienced any + * error conditions. + */ +static portLONG prvCheckOtherTasksAreStillRunning( unsigned portLONG ulMemCheckTaskCount ) +{ +portLONG lNoErrorsDiscovered = ( portLONG ) pdTRUE; + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + lNoErrorsDiscovered = pdFALSE; + } + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + lNoErrorsDiscovered = pdFALSE; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + lNoErrorsDiscovered = pdFALSE; + } + + if( xAreMathsTaskStillRunning() != pdTRUE ) + { + lNoErrorsDiscovered = pdFALSE; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + lNoErrorsDiscovered = pdFALSE; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + lNoErrorsDiscovered = pdFALSE; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + lNoErrorsDiscovered = pdFALSE; + } + + if( ulMemCheckTaskCount == mainCOUNT_INITIAL_VALUE ) + { + /* The vMemCheckTask task did not increment the counter - it must + have failed. */ + lNoErrorsDiscovered = pdFALSE; + } + + return lNoErrorsDiscovered; +} +/*-----------------------------------------------------------*/ + +static void vMemCheckTask( void *pvParameters ) +{ +unsigned portLONG *pulMemCheckTaskRunningCounter; +void *pvMem1, *pvMem2, *pvMem3; +static portLONG lErrorOccurred = pdFALSE; + + /* This task is dynamically created then deleted during each cycle of the + vErrorChecks task to check the operation of the memory allocator. Each time + the task is created memory is allocated for the stack and TCB. Each time + the task is deleted this memory is returned to the heap. This task itself + exercises the allocator by allocating and freeing blocks. + + The task executes at the idle priority so does not require a delay. + + pulMemCheckTaskRunningCounter is incremented each cycle to indicate to the + vErrorChecks() task that this task is still executing without error. */ + + pulMemCheckTaskRunningCounter = ( unsigned portLONG * ) pvParameters; + + for( ;; ) + { + if( lErrorOccurred == pdFALSE ) + { + /* We have never seen an error so increment the counter. */ + ( *pulMemCheckTaskRunningCounter )++; + } + else + { + /* Reset the count so an error is detected by the + prvCheckOtherTasksAreStillRunning() function. */ + *pulMemCheckTaskRunningCounter = mainCOUNT_INITIAL_VALUE; + } + + /* Allocate some memory - just to give the allocator some extra + exercise. This has to be in a critical section to ensure the + task does not get deleted while it has memory allocated. */ + vTaskSuspendAll(); + { + pvMem1 = pvPortMalloc( mainMEM_CHECK_SIZE_1 ); + if( pvMem1 == NULL ) + { + lErrorOccurred = pdTRUE; + } + else + { + memset( pvMem1, 0xaa, mainMEM_CHECK_SIZE_1 ); + vPortFree( pvMem1 ); + } + } + xTaskResumeAll(); + + /* Again - with a different size block. */ + vTaskSuspendAll(); + { + pvMem2 = pvPortMalloc( mainMEM_CHECK_SIZE_2 ); + if( pvMem2 == NULL ) + { + lErrorOccurred = pdTRUE; + } + else + { + memset( pvMem2, 0xaa, mainMEM_CHECK_SIZE_2 ); + vPortFree( pvMem2 ); + } + } + xTaskResumeAll(); + + /* Again - with a different size block. */ + vTaskSuspendAll(); + { + pvMem3 = pvPortMalloc( mainMEM_CHECK_SIZE_3 ); + if( pvMem3 == NULL ) + { + lErrorOccurred = pdTRUE; + } + else + { + memset( pvMem3, 0xaa, mainMEM_CHECK_SIZE_3 ); + vPortFree( pvMem3 ); + } + } + xTaskResumeAll(); + } +} +/*-----------------------------------------------------------*/ + +/* + * Called by the startup code. Initial processor setup can be placed in this + * function. + */ +void hw_initialise (void) +{ +} + diff --git a/20080212/Demo/H8S/RTOSDemo/serial/serial.c b/20080212/Demo/H8S/RTOSDemo/serial/serial.c new file mode 100644 index 000000000..62361dd6a --- /dev/null +++ b/20080212/Demo/H8S/RTOSDemo/serial/serial.c @@ -0,0 +1,270 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER for port 1. + +Note that this driver is written to test the RTOS port and is not intended +to represent an optimised solution. In particular no use is made of the DMA +peripheral. */ + +/* Standard include files. */ +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "queue.h" +#include "task.h" + +/* Demo application include files. */ +#include "serial.h" + +/* The queues used to communicate between the task code and the interrupt +service routines. */ +static xQueueHandle xRxedChars; +static xQueueHandle xCharsForTx; + +/* Hardware specific constants. */ +#define serTX_INTERRUPT ( ( unsigned portCHAR ) 0x80 ) +#define serRX_INTERRUPT ( ( unsigned portCHAR ) 0x40 ) +#define serTX_ENABLE ( ( unsigned portCHAR ) 0x20 ) +#define serRX_ENABLE ( ( unsigned portCHAR ) 0x10 ) + +/* Macros to turn on and off the serial port THRE interrupt while leaving the +other register bits in their correct state. The Rx interrupt is always +enabled. */ +#define serTX_INTERRUPT_ON() SCR1 = serTX_INTERRUPT | serRX_INTERRUPT | serTX_ENABLE | serRX_ENABLE; +#define serTX_INTERRUPT_OFF() SCR1 = serRX_INTERRUPT | serTX_ENABLE | serRX_ENABLE; + +/* Bit used to switch on the channel 1 serial port in the module stop +register. */ +#define serMSTP6 ( ( unsigned portSHORT ) 0x0040 ) + +/* Interrupt service routines. Note that the Rx and Tx service routines can +cause a context switch and are therefore defined with the saveall attribute in +addition to the interrupt_handler attribute. See the FreeRTOS.org WEB site +documentation for a full explanation.*/ +void vCOM_1_Rx_ISR( void ) __attribute__ ( ( saveall, interrupt_handler ) ); +void vCOM_1_Tx_ISR( void ) __attribute__ ( ( saveall, interrupt_handler ) ); +void vCOM_1_Error_ISR( void ) __attribute__ ( ( interrupt_handler ) ); + +/*-----------------------------------------------------------*/ + +/* + * Initialise port 1 for interrupt driven communications. + */ +xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) +{ + /* Create the queues used to communicate between the tasks and the + interrupt service routines. */ + xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + + /* No parity, 8 data bits and 1 stop bit is the default so does not require + configuration - setup the remains of the hardware. */ + portENTER_CRITICAL(); + { + /* Turn channel 1 on. */ + MSTPCR &= ~serMSTP6; + + /* Enable the channels and the Rx interrupt. The Tx interrupt is only + enabled when data is being transmitted. */ + SCR1 = serRX_INTERRUPT | serTX_ENABLE | serRX_ENABLE; + + /* Bit rate settings for 22.1184MHz clock only!. */ + switch( ulWantedBaud ) + { + case 4800 : BRR1 = 143; + break; + case 9600 : BRR1 = 71; + break; + case 19200 : BRR1 = 35; + break; + case 38400 : BRR1 = 17; + break; + case 57600 : BRR1 = 11; + break; + case 115200 : BRR1 = 5; + break; + default : BRR1 = 5; + break; + } + } + portEXIT_CRITICAL(); + + /* Unlike some ports, this driver code does not allow for more than one + com port. We therefore don't return a pointer to a port structure and can + instead just return NULL. */ + return NULL; +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) +{ + /* Get the next character from the buffer queue. Return false if no characters + are available, or arrive before xBlockTime expires. */ + if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) + { + return pdTRUE; + } + else + { + return pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) +{ +signed portBASE_TYPE xReturn = pdPASS; + + /* Return false if after the block time there is no room on the Tx queue. */ + portENTER_CRITICAL(); + { + /* Send a character to the queue of characters waiting transmission. + The queue is serviced by the Tx ISR. */ + if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) + { + /* Could not post onto the queue. */ + xReturn = pdFAIL; + } + else + { + /* The message was posted onto the queue so we turn on the Tx + interrupt to allow the Tx ISR to remove the character from the + queue. */ + serTX_INTERRUPT_ON(); + } + } + portEXIT_CRITICAL(); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +void vSerialClose( xComPortHandle xPort ) +{ + /* Not supported. */ + ( void ) xPort; +} +/*-----------------------------------------------------------*/ + +void vCOM_1_Rx_ISR( void ) +{ + /* This can cause a context switch so this macro must be the first line + in the function. */ + portENTER_SWITCHING_ISR(); + + /* As this is a switching ISR the local variables must be declared as + static. */ + static portCHAR cRxByte; + static portBASE_TYPE xTaskWokenByPost; + + /* Get the character. */ + cRxByte = RDR1; + + /* Post the character onto the queue of received characters - noting + whether or not this wakes a task. */ + xTaskWokenByPost = xQueueSendFromISR( xRxedChars, &cRxByte, pdFALSE ); + + /* Clear the interrupt. */ + SSR1 &= ~serRX_INTERRUPT; + + /* This must be the last line in the function. We pass cTaskWokenByPost so + a context switch will occur if the received character woke a task that has + a priority higher than the task we interrupted. */ + portEXIT_SWITCHING_ISR( xTaskWokenByPost ); +} +/*-----------------------------------------------------------*/ + +void vCOM_1_Tx_ISR( void ) +{ + /* This can cause a context switch so this macro must be the first line + in the function. */ + portENTER_SWITCHING_ISR(); + + /* As this is a switching ISR the local variables must be declared as + static. */ + static portCHAR cTxByte; + static signed portBASE_TYPE xTaskWokenByTx; + + /* This variable is static so must be explicitly reinitialised each + time the function executes. */ + xTaskWokenByTx = pdFALSE; + + /* The interrupt was caused by the THR becoming empty. Are there any + more characters to transmit? Note whether or not the Tx interrupt has + woken a task. */ + if( xQueueReceiveFromISR( xCharsForTx, &cTxByte, &xTaskWokenByTx ) == pdTRUE ) + { + /* A character was retrieved from the queue so can be sent to the + THR now. */ + TDR1 = cTxByte; + + /* Clear the interrupt. */ + SSR1 &= ~serTX_INTERRUPT; + } + else + { + /* Queue empty, nothing to send so turn off the Tx interrupt. */ + serTX_INTERRUPT_OFF(); + } + + /* This must be the last line in the function. We pass cTaskWokenByTx so + a context switch will occur if the Tx'ed character woke a task that has + a priority higher than the task we interrupted. */ + portEXIT_SWITCHING_ISR( xTaskWokenByTx ); +} +/*-----------------------------------------------------------*/ + +/* + * This ISR cannot cause a context switch so requires no special + * considerations. + */ +void vCOM_1_Error_ISR( void ) +{ +volatile unsigned portCHAR ucIn; + + ucIn = SSR1; + SSR1 = 0; +} + diff --git a/20080212/Demo/H8S/RTOSDemo/start.asm b/20080212/Demo/H8S/RTOSDemo/start.asm new file mode 100644 index 000000000..be99b2108 --- /dev/null +++ b/20080212/Demo/H8S/RTOSDemo/start.asm @@ -0,0 +1,115 @@ +;/**************************************************************** +;KPIT Cummins Infosystems Ltd, Pune, India. - 4th September 2003. +; +;This program is distributed in the hope that it will be useful, +;but WITHOUT ANY WARRANTY; without even the implied warranty of +;MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE +; +;*****************************************************************/ + + +;********************************************************************* +; File: start.asm +; +; +; desc: +; +; System initialisation routine - entry point for the application. +; The stack pointer is initialised, then the hardware initialisation +; routine called. The static data areas are then initialised, before +; the main function is executed. A simple exit funtion is also +; supplied +; +;********************************************************************* + +#ifdef __H8300H__ + +#ifdef __NORMAL_MODE__ + .h8300hn +#else + .h8300h +#endif + +#endif /*_H8300H_ */ + +#ifdef __H8300S__ + +#ifdef __NORMAL_MODE__ + .h8300sn +#else + .h8300s +#endif + +#endif /* __H8300S__ */ + + .section .text + .global _start +#if DEBUG + .extern _exit +#endif + + .extern _hw_initialise + .extern _main + + .extern _data + .extern _mdata + .extern _edata + .extern _bss + .extern _ebss + .extern _stack + +_start: + ; initialise the SP for non-vectored code + mov.l #_stack,er7 + ; call the hardware initialiser + jsr @_hw_initialise +#ifdef ROMSTART + ; get the boundaries for the .data section initialisation + mov.l #_data,er0 + mov.l #_edata,er1 + mov.l #_mdata,er2 + cmp.l er0,er1 + beq start_1 +start_l: + mov.b @er2,r3l ;get from src + mov.b r3l,@er0 ;place in dest + inc.l #1,er2 ;inc src + inc.l #1,er0 ;inc dest + cmp.l er0,er1 ;dest == edata? + bne start_l +start_1: +#endif //ROMSTART + ; zero out bss + mov.l #_bss,er0 + mov.l #_ebss,er1 + cmp.l er0,er1 + beq start_3 + sub.b r2l,r2l +start_2: + mov.b r2l,@er0 + inc.l #1,er0 + cmp.l er0,er1 + bne start_2 +start_3: +#ifdef CPPAPP + ;Initialize global constructor + jsr @___main +#endif + + ; call the mainline + jsr @_main + + + mov.l er0,er4 + + ;call to exit +#if DEBUG + jsr @_exit +#endif +#if RELEASE + exit: + bra exit +#endif + + + diff --git a/20080212/Demo/H8S/RTOSDemo/vects.c b/20080212/Demo/H8S/RTOSDemo/vects.c new file mode 100644 index 000000000..f220983a9 --- /dev/null +++ b/20080212/Demo/H8S/RTOSDemo/vects.c @@ -0,0 +1,137 @@ +/**************************************************************** +KPIT Cummins Infosystems Ltd, Pune, India. - 19-June-2003. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +*****************************************************************/ + +void start(void); /* Startup code (in start.asm) */ + +/* + * Manual context switch trap function. + */ +void vPortYield( void ); + +/* + * The RTOS tick ISR. + */ +void vTickISR( void ); + +/* + * Serial port ISR functions. + */ +void vCOM_1_Rx_ISR( void ); +void vCOM_1_Tx_ISR( void ); +void vCOM_1_Error_ISR( void ); + + +typedef void (*fp) (void); +#define VECT_SECT __attribute__ ((section (".vects"))) + +const fp HardwareVectors[] VECT_SECT = { +start, /* vector 0 */ +(fp)(0), /* vector 1 */ +(fp)(0), /* vector 2 */ +(fp)(0), /* vector 3 */ +(fp)(0), /* vector 4 */ +(fp)(0), /* vector 5 */ +(fp)(0), /* vector 6 */ +(fp)(0), /* vector 7 */ +vPortYield, /* vector 8 */ +(fp)(0), /* vector 9 */ +(fp)(0), /* vector 10 */ +(fp)(0), /* vector 11 */ +(fp)(0), /* vector 12 */ +(fp)(0), /* vector 13 */ +(fp)(0), /* vector 14 */ +(fp)(0), /* vector 15 */ +(fp)(0), /* vector 16 */ +(fp)(0), /* vector 17 */ +(fp)(0), /* vector 18 */ +(fp)(0), /* vector 19 */ +(fp)(0), /* vector 20 */ +(fp)(0), /* vector 21 */ +(fp)(0), /* vector 22 */ +(fp)(0), /* vector 23 */ +(fp)(0), /* vector 24 */ +(fp)(0), /* vector 25 */ +(fp)(0), /* vector 26 */ +(fp)(0), /* vector 27 */ +(fp)(0), /* vector 28 */ +(fp)(0), /* vector 29 */ +(fp)(0), /* vector 30 */ +(fp)(0), /* vector 31 */ +(fp)(0), /* vector 32 */ +(fp)(0), /* vector 33 */ +(fp)(0), /* vector 34 */ +(fp)(0), /* vector 35 */ +(fp)(0), /* vector 36 */ +(fp)(0), /* vector 37 */ +(fp)(0), /* vector 38 */ +(fp)(0), /* vector 39 */ +vTickISR, /* vector 40 */ +(fp)(0), /* vector 41 */ +(fp)(0), /* vector 42 */ +(fp)(0), /* vector 43 */ +(fp)(0), /* vector 44 */ +(fp)(0), /* vector 45 */ +(fp)(0), /* vector 46 */ +(fp)(0), /* vector 47 */ +(fp)(0), /* vector 48 */ +(fp)(0), /* vector 49 */ +(fp)(0), /* vector 50 */ +(fp)(0), /* vector 51 */ +(fp)(0), /* vector 52 */ +(fp)(0), /* vector 53 */ +(fp)(0), /* vector 54 */ +(fp)(0), /* vector 55 */ +(fp)(0), /* vector 56 */ +(fp)(0), /* vector 57 */ +(fp)(0), /* vector 58 */ +(fp)(0), /* vector 59 */ +(fp)(0), /* vector 60 */ +(fp)(0), /* vector 61 */ +(fp)(0), /* vector 62 */ +(fp)(0), /* vector 63 */ +(fp)(0), /* vector 64 */ +(fp)(0), /* vector 65 */ +(fp)(0), /* vector 66 */ +(fp)(0), /* vector 67 */ +(fp)(0), /* vector 68 */ +(fp)(0), /* vector 69 */ +(fp)(0), /* vector 70 */ +(fp)(0), /* vector 71 */ +(fp)(0), /* vector 72 */ +(fp)(0), /* vector 73 */ +(fp)(0), /* vector 74 */ +(fp)(0), /* vector 75 */ +(fp)(0), /* vector 76 */ +(fp)(0), /* vector 77 */ +(fp)(0), /* vector 78 */ +(fp)(0), /* vector 79 */ +(fp)(0), /* vector 80 */ +(fp)(0), /* vector 81 */ +(fp)(0), /* vector 82 */ +(fp)(0), /* vector 83 */ +vCOM_1_Error_ISR, /* vector 84 */ +vCOM_1_Rx_ISR, /* vector 85 */ +vCOM_1_Tx_ISR, /* vector 86 */ +(fp)(0), /* vector 87 */ +(fp)(0), /* vector 88 */ +(fp)(0), /* vector 89 */ +(fp)(0), /* vector 90 */ +(fp)(0), /* vector 91 */ +(fp)(0), /* vector 92 */ +(fp)(0), /* vector 93 */ +(fp)(0), /* vector 94 */ +(fp)(0), /* vector 95 */ +(fp)(0), /* vector 96 */ +(fp)(0), /* vector 97 */ +(fp)(0), /* vector 98 */ +(fp)(0), /* vector 99 */ +(fp)(0), /* vector 100 */ +(fp)(0), /* vector 101 */ +(fp)(0), /* vector 102 */ +(fp)(0) /* vector 103 */ +}; diff --git a/20080212/Demo/HCS12_CodeWarrior_banked/CODE/Byte1.C b/20080212/Demo/HCS12_CodeWarrior_banked/CODE/Byte1.C new file mode 100644 index 000000000..7acd81842 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_banked/CODE/Byte1.C @@ -0,0 +1,145 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : Byte1.C +** Project : RTOSDemo +** Processor : MC9S12DP256BCPV +** Beantype : ByteIO +** Version : Bean 02.019, Driver 01.03, CPU db: 2.87.283 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 16/06/2005, 21:10 +** Abstract : +** This bean "ByteIO" implements an one-byte input/output. +** It uses one 8-bit port. +** Note: This bean is set to work in Output direction only. +** Methods of this bean are mostly implemented as a macros +** (if supported by target langauage and compiler). +** Settings : +** Port name : B +** +** Initial direction : Output (direction cannot be changed) +** Initial output value : 255 = 0FFH +** Initial pull option : off +** +** 8-bit data register : PORTB [1] +** 8-bit control register : DDRB [3] +** +** ---------------------------------------------------- +** Bit | Pin | Name +** ---------------------------------------------------- +** 0 | 24 | PB0_ADDR0_DATA0 +** 1 | 25 | PB1_ADDR1_DATA1 +** 2 | 26 | PB2_ADDR2_DATA2 +** 3 | 27 | PB3_ADDR3_DATA3 +** 4 | 28 | PB4_ADDR4_DATA4 +** 5 | 29 | PB5_ADDR5_DATA5 +** 6 | 30 | PB6_ADDR6_DATA6 +** 7 | 31 | PB7_ADDR7_DATA7 +** ---------------------------------------------------- +** Contents : +** PutBit - void Byte1_PutBit(byte Bit,bool Val); +** NegBit - void Byte1_NegBit(byte Bit); +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + + +/* MODULE Byte1. */ + +#include "Byte1.h" +/*Including shared modules, which are used for all project*/ +#include "PE_Types.h" +#include "PE_Error.h" +#include "PE_Const.h" +#include "IO_Map.h" +#include "PE_Timer.h" + +#include "Cpu.h" + +/* Definition of DATA and CODE segments for this bean. User can specify where + these segments will be located on "Build options" tab of the selected CPU bean. */ +#pragma DATA_SEG Byte1_DATA /* Data section for this module. */ +#pragma CODE_SEG Byte1_CODE /* Code section for this module. */ + +/* +** =================================================================== +** Method : Byte1_GetMsk (bean ByteIO) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +byte Byte1_Table[8]={ 1, 2, 4, 8, 16, 32, 64, 128 }; /* Table of mask constants */ + +byte Byte1_GetMsk(byte Value) +{ + return((Value<8)?Byte1_Table[Value]:0); /* Return appropriate bit mask */ +} + +/* +** =================================================================== +** Method : Byte1_PutBit (bean ByteIO) +** +** Description : +** This method writes the new value to the specified bit +** of the output value. +** Parameters : +** NAME - DESCRIPTION +** Bitnum - Number of the bit (0 to 7) +** Val - New value of the bit (FALSE or TRUE) +** FALSE = "0" or "Low", TRUE = "1" or "High" +** Returns : Nothing +** =================================================================== +*/ +void Byte1_PutBit(byte BitNum, byte Value) +{ + byte Mask=Byte1_GetMsk(BitNum); /* Temporary variable - bit mask */ + + if (Mask) /* Is bit mask correct? */ + if (Value) { /* Is it one to be written? */ + PORTB |= Mask; /* Set appropriate bit on port */ + } + else { /* Is it zero to be written? */ + PORTB &= ~Mask; /* Clear appropriate bit on port */ + } +} + +/* +** =================================================================== +** Method : Byte1_NegBit (bean ByteIO) +** +** Description : +** This method negates (invertes) the specified bit of the +** output value. +** Parameters : +** NAME - DESCRIPTION +** Bit - Number of the bit to invert (0 to 7) +** Returns : Nothing +** =================================================================== +*/ +void Byte1_NegBit(byte BitNum) +{ + byte Mask=Byte1_GetMsk(BitNum); /* Temporary variable - bit mask */ + + if (Mask) { /* Is bit mask correct? */ + PORTB ^= Mask; /* Negate appropriate bit on port */ + } +} + + +/* END Byte1. */ + +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/20080212/Demo/HCS12_CodeWarrior_banked/CODE/Byte1.H b/20080212/Demo/HCS12_CodeWarrior_banked/CODE/Byte1.H new file mode 100644 index 000000000..028d1e3c1 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_banked/CODE/Byte1.H @@ -0,0 +1,111 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : Byte1.H +** Project : RTOSDemo +** Processor : MC9S12DP256BCPV +** Beantype : ByteIO +** Version : Bean 02.019, Driver 01.03, CPU db: 2.87.283 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 16/06/2005, 21:10 +** Abstract : +** This bean "ByteIO" implements an one-byte input/output. +** It uses one 8-bit port. +** Note: This bean is set to work in Output direction only. +** Methods of this bean are mostly implemented as a macros +** (if supported by target langauage and compiler). +** Settings : +** Port name : B +** +** Initial direction : Output (direction cannot be changed) +** Initial output value : 255 = 0FFH +** Initial pull option : off +** +** 8-bit data register : PORTB [1] +** 8-bit control register : DDRB [3] +** +** ---------------------------------------------------- +** Bit | Pin | Name +** ---------------------------------------------------- +** 0 | 24 | PB0_ADDR0_DATA0 +** 1 | 25 | PB1_ADDR1_DATA1 +** 2 | 26 | PB2_ADDR2_DATA2 +** 3 | 27 | PB3_ADDR3_DATA3 +** 4 | 28 | PB4_ADDR4_DATA4 +** 5 | 29 | PB5_ADDR5_DATA5 +** 6 | 30 | PB6_ADDR6_DATA6 +** 7 | 31 | PB7_ADDR7_DATA7 +** ---------------------------------------------------- +** Contents : +** PutBit - void Byte1_PutBit(byte Bit,bool Val); +** NegBit - void Byte1_NegBit(byte Bit); +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + +#ifndef __Byte1_H +#define __Byte1_H + +/* MODULE Byte1. */ + +/*Including shared modules, which are used in the whole project*/ +#include "PE_Types.h" +#include "PE_Error.h" +#include "PE_Const.h" +#include "IO_Map.h" +#include "PE_Timer.h" + +#include "Cpu.h" + +#pragma CODE_SEG Byte1_CODE /* Code section for this module. */ + +/* +** =================================================================== +** Method : Byte1_PutBit (bean ByteIO) +** +** Description : +** This method writes the new value to the specified bit +** of the output value. +** Parameters : +** NAME - DESCRIPTION +** BitNum - Number of the bit (0 to 7) +** Val - New value of the bit (FALSE or TRUE) +** FALSE = "0" or "Low", TRUE = "1" or "High" +** Returns : Nothing +** =================================================================== +*/ +void Byte1_PutBit(byte BitNum, byte Value); + +/* +** =================================================================== +** Method : Byte1_NegBit (bean ByteIO) +** +** Description : +** This method negates (invertes) the specified bit of the +** output value. +** Parameters : +** NAME - DESCRIPTION +** BitNum - Number of the bit to invert (0 to 7) +** Returns : Nothing +** =================================================================== +*/ +void Byte1_NegBit(byte BitNum); + +#pragma CODE_SEG DEFAULT /* Change code section to DEFAULT. */ + +/* END Byte1. */ + +#endif /* __Byte1_H*/ +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/20080212/Demo/HCS12_CodeWarrior_banked/CODE/COM0.C b/20080212/Demo/HCS12_CodeWarrior_banked/CODE/COM0.C new file mode 100644 index 000000000..e575af48c --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_banked/CODE/COM0.C @@ -0,0 +1,205 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : COM0.C +** Project : RTOSDemo +** Processor : MC9S12DP256BCPV +** Beantype : AsynchroSerial +** Version : Bean 02.231, Driver 01.08, CPU db: 2.87.283 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 19/06/2005, 15:07 +** Abstract : +** This bean "AsynchroSerial" implements an asynchronous serial +** communication. The bean supports different settings of +** parity, word width, stop-bit and communication speed, +** user can select interrupt or polling handler. +** Communication speed can be changed also in runtime. +** The bean requires one on-chip asynchronous serial channel. +** Settings : +** Serial channel : SCI0 +** +** Protocol +** Init baud rate : 38400baud +** Width : 8 bits +** Stop bits : 1 +** Parity : none +** Breaks : Disabled +** +** Registers +** Input buffer : SCI0DRL [207] +** Output buffer : SCI0DRL [207] +** Control register : SCI0CR1 [202] +** Mode register : SCI0CR2 [203] +** Baud setting reg. : SCI0BD [200] +** Special register : SCI0SR1 [204] +** +** Input interrupt +** Vector name : INT_SCI0 +** Priority : 1 +** +** Output interrupt +** Vector name : INT_SCI0 +** Priority : 1 +** +** Used pins : +** ---------------------------------------------------- +** Function | On package | Name +** ---------------------------------------------------- +** Input | 89 | PS0_RxD0 +** Output | 90 | PS1_TxD0 +** ---------------------------------------------------- +** +** +** Used baud modes : +** ---------------------------------------------------- +** No. | Mode ID | Baud rate +** ---------------------------------------------------- +** 0 | Bm_38400baud | 38400baud +** 1 | Bm_19200baud | 19200baud +** 2 | Bm_9600baud | 9600baud +** 3 | Bm_4800baud | 4800baud +** ---------------------------------------------------- +** Contents : +** SetBaudRateMode - byte COM0_SetBaudRateMode(byte Mod); +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + +/* MODULE COM0. */ + +#pragma MESSAGE DISABLE C4002 /* WARNING C4002: Result not used is ignored */ +#pragma MESSAGE DISABLE C4301 /* INFORMATION C4301: Inline expansion done for function call */ + +#include "COM0.h" +#include "TickTimer.h" +#include "Byte1.h" + +/* Definition of DATA and CODE segments for this bean. User can specify where + these segments will be located on "Build options" tab of the selected CPU bean. */ +#pragma DATA_SEG COM0_DATA /* Data section for this module. */ +#pragma CODE_SEG COM0_CODE /* Code section for this module. */ + + +#define OVERRUN_ERR 1 /* Overrun error flag bit */ +#define FRAMING_ERR 2 /* Framing error flag bit */ +#define PARITY_ERR 4 /* Parity error flag bit */ +#define CHAR_IN_RX 8 /* Char is in RX buffer */ +#define FULL_TX 16 /* Full transmit buffer */ +#define RUNINT_FROM_TX 32 /* Interrupt is in progress */ +#define FULL_RX 64 /* Full receive buffer */ +#define NOISE_ERR 128 /* Noise erorr flag bit */ +#define IDLE_ERR 256 /* Idle character flag bit */ +#define BREAK_ERR 512 /* Break detect */ + +static word SerFlag; /* Flags for serial communication */ + /* Bits: 0 - OverRun error */ + /* 1 - Framing error */ + /* 2 - Parity error */ + /* 3 - Char in RX buffer */ + /* 4 - Full TX buffer */ + /* 5 - Running int from TX */ + /* 6 - Full RX buffer */ + /* 7 - Noise error */ + /* 8 - Idle character */ + /* 9 - Break detected */ + /* 10 - Unused */ +static word PrescHigh; +static byte NumMode; /* Number of selected baud mode */ + + +/* +** =================================================================== +** Method : HWEnDi (bean AsynchroSerial) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +static void HWEnDi(void) +{ + SCI0CR2_TE = 1; /* Enable transmitter */ + SCI0CR2_RE = 1; /* Enable receiver */ + SCI0CR2_RIE = 1; /* Enable recieve interrupt */ +} + +/* +** =================================================================== +** Method : COM0_SetBaudRateMode (bean AsynchroSerial) +** +** Description : +** This method changes the channel communication speed (baud +** rate). This method can be used only if you specify a list +** of possible period settings at design time (see - Runtime setting - from a list of values). +** Each of these settings constitutes a mode and Processor +** Expert^[TM] assigns them a mode identifier. The prescaler +** and compare values corresponding to each mode are +** calculated at design time. You may switch modes at +** runtime by referring only to a mode identifier. No +** run-time calculations are performed, all the calculations +** are performed at design time. +** Parameters : +** NAME - DESCRIPTION +** Mod - Timing mode to set +** Returns : +** --- - Error code, possible codes: +** ERR_OK - OK +** ERR_SPEED - This device does not work in +** the active speed mode +** =================================================================== +*/ +byte COM0_SetBaudRateMode(byte Mod) +{ + static const word COM0_PrescHigh[4] = {41,81,163,326}; + + if(Mod >= 4) /* Is mode in baud mode list */ + return ERR_VALUE; /* If no then error */ + NumMode = Mod; /* New baud mode */ + PrescHigh = COM0_PrescHigh[Mod]; /* Prescaler in high speed mode */ + SCI0BD = PrescHigh; /* Set prescaler bits */ + return ERR_OK; /* OK */ +} + +/* +** =================================================================== +** Method : COM0_Init (bean AsynchroSerial) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +void COM0_Init(void) +{ + PrescHigh = 41; /* Precaler in high speed mode */ + SerFlag = 0; /* Reset flags */ + NumMode = 0; /* Number of selected baud mode */ + /* SCI0CR1: LOOPS=0,SCISWAI=1,RSRC=0,M=0,WAKE=0,ILT=0,PE=0,PT=0 */ + SCI0CR1 = 64; /* Set the SCI configuration */ + /* SCI0SR2: ??=0,??=0,??=0,??=0,??=0,BRK13=0,TXDIR=0,RAF=0 */ + SCI0SR2 = 0; /* Set the Break Character Length and Transmitter pin data direction in Single-wire mode */ + SCI0SR1; /* Reset interrupt request flags */ + /* SCI0CR2: SCTIE=0,TCIE=0,RIE=0,ILIE=0,TE=0,RE=0,RWU=0,SBK=0 */ + SCI0CR2 = 0; /* Disable error interrupts */ + SCI0BD = PrescHigh; /* Set prescaler bits */ + HWEnDi(); /* Enable/disable device according to status flags */ +} + + +/* END COM0. */ + + +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/20080212/Demo/HCS12_CodeWarrior_banked/CODE/COM0.H b/20080212/Demo/HCS12_CodeWarrior_banked/CODE/COM0.H new file mode 100644 index 000000000..3f0e99a23 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_banked/CODE/COM0.H @@ -0,0 +1,191 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : COM0.H +** Project : RTOSDemo +** Processor : MC9S12DP256BCPV +** Beantype : AsynchroSerial +** Version : Bean 02.231, Driver 01.08, CPU db: 2.87.283 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 19/06/2005, 15:07 +** Abstract : +** This bean "AsynchroSerial" implements an asynchronous serial +** communication. The bean supports different settings of +** parity, word width, stop-bit and communication speed, +** user can select interrupt or polling handler. +** Communication speed can be changed also in runtime. +** The bean requires one on-chip asynchronous serial channel. +** Settings : +** Serial channel : SCI0 +** +** Protocol +** Init baud rate : 38400baud +** Width : 8 bits +** Stop bits : 1 +** Parity : none +** Breaks : Disabled +** +** Registers +** Input buffer : SCI0DRL [207] +** Output buffer : SCI0DRL [207] +** Control register : SCI0CR1 [202] +** Mode register : SCI0CR2 [203] +** Baud setting reg. : SCI0BD [200] +** Special register : SCI0SR1 [204] +** +** Input interrupt +** Vector name : INT_SCI0 +** Priority : 1 +** +** Output interrupt +** Vector name : INT_SCI0 +** Priority : 1 +** +** Used pins : +** ---------------------------------------------------- +** Function | On package | Name +** ---------------------------------------------------- +** Input | 89 | PS0_RxD0 +** Output | 90 | PS1_TxD0 +** ---------------------------------------------------- +** +** +** Used baud modes : +** ---------------------------------------------------- +** No. | Mode ID | Baud rate +** ---------------------------------------------------- +** 0 | Bm_38400baud | 38400baud +** 1 | Bm_19200baud | 19200baud +** 2 | Bm_9600baud | 9600baud +** 3 | Bm_4800baud | 4800baud +** ---------------------------------------------------- +** Contents : +** SetBaudRateMode - byte COM0_SetBaudRateMode(byte Mod); +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + +#ifndef __COM0 +#define __COM0 + +/* MODULE COM0. */ + +#include "Cpu.h" + +#define COM0_Bm_38400baud 0 /* Constant for switch to mode 0 */ +#define COM0_Bm_19200baud 1 /* Constant for switch to mode 1 */ +#define COM0_Bm_9600baud 2 /* Constant for switch to mode 2 */ +#define COM0_Bm_4800baud 3 /* Constant for switch to mode 3 */ + + + +#ifndef __BWUserType_tItem +#define __BWUserType_tItem + typedef struct { /* Item of the index table for possible baudrates */ + word div; /* divisior */ + byte val; /* values of the prescalers */ + } tItem; +#endif +#ifndef __BWUserType_COM0_TError +#define __BWUserType_COM0_TError +typedef union { + byte err; + struct { + bool OverRun : 1; /* OverRun error flag */ + bool Framing : 1; /* Framing error flag */ + bool Parity : 1; /* Parity error flag */ + bool RxBufOvf : 1; /* Rx buffer full error flag */ + bool Noise : 1; /* Noise error */ + bool Break : 1; /* Break detect */ + bool Idle : 1; /* Idle characted */ + }errName; +} COM0_TError; +#endif +#ifndef __BWUserType_TDirection +#define __BWUserType_TDirection + typedef enum { /* */ + TXD_INPUT, + TXD_OUTPUT + } TDirection; +#endif + +#ifndef __BWUserType_COM0_TComData +#define __BWUserType_COM0_TComData + typedef byte COM0_TComData ; /* User type for communication. Size of this type depends on the communication data witdh. */ +#endif + +#pragma CODE_SEG COM0_CODE /* Code section for this module. */ + +byte COM0_SetBaudRateMode(byte Mod); +/* +** =================================================================== +** Method : COM0_SetBaudRateMode (bean AsynchroSerial) +** +** Description : +** This method changes the channel communication speed (baud +** rate). This method can be used only if you specify a list +** of possible period settings at design time (see - Runtime setting - from a list of values). +** Each of these settings constitutes a mode and Processor +** Expert^[TM] assigns them a mode identifier. The prescaler +** and compare values corresponding to each mode are +** calculated at design time. You may switch modes at +** runtime by referring only to a mode identifier. No +** run-time calculations are performed, all the calculations +** are performed at design time. +** Parameters : +** NAME - DESCRIPTION +** Mod - Timing mode to set +** Returns : +** --- - Error code, possible codes: +** ERR_OK - OK +** ERR_SPEED - This device does not work in +** the active speed mode +** =================================================================== +*/ + +#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */ +__interrupt void COM0_Interrupt(void); +#pragma CODE_SEG COM0_CODE /* Code section for this module. */ +/* +** =================================================================== +** Method : COM0_Interrupt (bean AsynchroSerial) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ + + +void COM0_Init(void); +/* +** =================================================================== +** Method : COM0_Init (bean AsynchroSerial) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ + + +#pragma CODE_SEG DEFAULT /* Change code section to DEFAULT. */ + +/* END COM0. */ + +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ + +#endif /* ifndef __COM0 */ diff --git a/20080212/Demo/HCS12_CodeWarrior_banked/CODE/Copy of Vectors.c b/20080212/Demo/HCS12_CodeWarrior_banked/CODE/Copy of Vectors.c new file mode 100644 index 000000000..7842537ce --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_banked/CODE/Copy of Vectors.c @@ -0,0 +1,112 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : Cpu.C +** Project : RTOSDemo +** Processor : MC9S12DP256BCPV +** Beantype : MC9S12DP256_112 +** Version : Bean 01.148, Driver 01.09, CPU db: 2.87.283 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 16/06/2005, 19:18 +** Abstract : +** This bean "MC9S12DP256_112" implements properties, methods, +** and events of the CPU. +** Settings : +** +** Contents : +** EnableInt - void Cpu_EnableInt(void); +** DisableInt - void Cpu_DisableInt(void); +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + + +#include "Cpu.h" +#include "TickTimer.h" +#include "Byte1.h" + +extern void near _EntryPoint(void); /* Startup routine */ +extern void near vPortTickInterrupt( void ); +extern void near vPortYield( void ); +extern void near vCOM0_ISR( void ); + +typedef void (*near tIsrFunc)(void); +const tIsrFunc _vect[] @0xFF80 = { /* Interrupt table */ + Cpu_Interrupt, /* 0 Default (unused) interrupt */ + Cpu_Interrupt, /* 1 Default (unused) interrupt */ + Cpu_Interrupt, /* 2 Default (unused) interrupt */ + Cpu_Interrupt, /* 3 Default (unused) interrupt */ + Cpu_Interrupt, /* 4 Default (unused) interrupt */ + Cpu_Interrupt, /* 5 Default (unused) interrupt */ + Cpu_Interrupt, /* 6 Default (unused) interrupt */ + Cpu_Interrupt, /* 7 Default (unused) interrupt */ + Cpu_Interrupt, /* 8 Default (unused) interrupt */ + Cpu_Interrupt, /* 9 Default (unused) interrupt */ + Cpu_Interrupt, /* 10 Default (unused) interrupt */ + Cpu_Interrupt, /* 11 Default (unused) interrupt */ + Cpu_Interrupt, /* 12 Default (unused) interrupt */ + Cpu_Interrupt, /* 13 Default (unused) interrupt */ + Cpu_Interrupt, /* 14 Default (unused) interrupt */ + Cpu_Interrupt, /* 15 Default (unused) interrupt */ + Cpu_Interrupt, /* 16 Default (unused) interrupt */ + Cpu_Interrupt, /* 17 Default (unused) interrupt */ + Cpu_Interrupt, /* 18 Default (unused) interrupt */ + Cpu_Interrupt, /* 19 Default (unused) interrupt */ + Cpu_Interrupt, /* 20 Default (unused) interrupt */ + Cpu_Interrupt, /* 21 Default (unused) interrupt */ + Cpu_Interrupt, /* 22 Default (unused) interrupt */ + Cpu_Interrupt, /* 23 Default (unused) interrupt */ + Cpu_Interrupt, /* 24 Default (unused) interrupt */ + Cpu_Interrupt, /* 25 Default (unused) interrupt */ + Cpu_Interrupt, /* 26 Default (unused) interrupt */ + Cpu_Interrupt, /* 27 Default (unused) interrupt */ + Cpu_Interrupt, /* 28 Default (unused) interrupt */ + Cpu_Interrupt, /* 29 Default (unused) interrupt */ + Cpu_Interrupt, /* 30 Default (unused) interrupt */ + Cpu_Interrupt, /* 31 Default (unused) interrupt */ + Cpu_Interrupt, /* 32 Default (unused) interrupt */ + Cpu_Interrupt, /* 33 Default (unused) interrupt */ + Cpu_Interrupt, /* 34 Default (unused) interrupt */ + Cpu_Interrupt, /* 35 Default (unused) interrupt */ + Cpu_Interrupt, /* 36 Default (unused) interrupt */ + Cpu_Interrupt, /* 37 Default (unused) interrupt */ + Cpu_Interrupt, /* 38 Default (unused) interrupt */ + Cpu_Interrupt, /* 39 Default (unused) interrupt */ + Cpu_Interrupt, /* 40 Default (unused) interrupt */ + Cpu_Interrupt, /* 41 Default (unused) interrupt */ + Cpu_Interrupt, /* 42 Default (unused) interrupt */ + vCOM0_ISR, + Cpu_Interrupt, /* 44 Default (unused) interrupt */ + Cpu_Interrupt, /* 45 Default (unused) interrupt */ + Cpu_Interrupt, /* 46 Default (unused) interrupt */ + Cpu_Interrupt, /* 47 Default (unused) interrupt */ + Cpu_Interrupt, /* 48 Default (unused) interrupt */ + Cpu_Interrupt, /* 49 Default (unused) interrupt */ + Cpu_Interrupt, /* 50 Default (unused) interrupt */ + Cpu_Interrupt, /* 51 Default (unused) interrupt */ + Cpu_Interrupt, /* 52 Default (unused) interrupt */ + Cpu_Interrupt, /* 53 Default (unused) interrupt */ + Cpu_Interrupt, /* 54 Default (unused) interrupt */ + vPortTickInterrupt, + Cpu_Interrupt, /* 56 Default (unused) interrupt */ + Cpu_Interrupt, /* 57 Default (unused) interrupt */ + Cpu_Interrupt, /* 58 Default (unused) interrupt */ + vPortYield, /* 59 Default (unused) interrupt */ + Cpu_Interrupt, /* 60 Default (unused) interrupt */ + Cpu_Interrupt, /* 61 Default (unused) interrupt */ + Cpu_Interrupt, /* 62 Default (unused) interrupt */ + _EntryPoint /* Reset vector */ + }; +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/20080212/Demo/HCS12_CodeWarrior_banked/CODE/Cpu.C b/20080212/Demo/HCS12_CodeWarrior_banked/CODE/Cpu.C new file mode 100644 index 000000000..a204a0b7c --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_banked/CODE/Cpu.C @@ -0,0 +1,198 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : Cpu.C +** Project : RTOSDemo +** Processor : MC9S12DP256BCPV +** Beantype : MC9S12DP256_112 +** Version : Bean 01.148, Driver 01.09, CPU db: 2.87.283 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 18/06/2005, 16:21 +** Abstract : +** This bean "MC9S12DP256_112" implements properties, methods, +** and events of the CPU. +** Settings : +** +** Contents : +** EnableInt - void Cpu_EnableInt(void); +** DisableInt - void Cpu_DisableInt(void); +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + +/* MODULE Cpu. */ + +#include "TickTimer.h" +#include "Byte1.h" +#include "COM0.h" +#include "PE_Types.h" +#include "PE_Error.h" +#include "PE_Const.h" +#include "IO_Map.h" +#include "PE_Timer.h" +#include "Events.h" +#include "Cpu.h" + +#define CGM_DELAY 3071UL + + +/* Global variables */ +volatile byte CCR_reg; /* Current CCR reegister */ +byte CpuMode = HIGH_SPEED; /* Current speed mode */ + + +/* +** =================================================================== +** Method : Cpu_Interrupt (bean MC9S12DP256_112) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */ + +__interrupt void Cpu_Interrupt(void) +{ +} + +#pragma CODE_SEG DEFAULT /* Change code section to DEFAULT. */ + +/* +** =================================================================== +** Method : Cpu_DisableInt (bean MC9S12DP256_112) +** +** Description : +** Disable maskable interrupts +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +/* +void Cpu_DisableInt(void) + +** This method is implemented as macro in the header module. ** +*/ + +/* +** =================================================================== +** Method : Cpu_EnableInt (bean MC9S12DP256_112) +** +** Description : +** Enable maskable interrupts +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +/* +void Cpu_EnableInt(void) + +** This method is implemented as macro in the header module. ** +*/ + +/* +** =================================================================== +** Method : _EntryPoint (bean MC9S12DP256_112) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +extern void _Startup(void); /* Forward declaration of external startup function declared in file Start12.c */ +#define INITRG_ADR 0x0011 /* Register map position register */ +#pragma NO_FRAME +#pragma NO_EXIT +void _EntryPoint(void) +{ + /*** ### MC9S12DP256_112 "Cpu" init code ... ***/ + /*** PE initialization code after reset ***/ + /* Initialization of the registers INITRG, INITRM, INITEE is done to protect them to be written accidentally later by the application */ + *(byte*)INITRG_ADR = 0; /* Set the register map position */ + asm nop; /* nop instruction */ + INITRM=1; /* Set the RAM map position */ + INITEE=1; /* Set the EEPROM map position */ + /* MISC: ??=0,??=0,??=0,??=0,EXSTR1=0,EXSTR0=0,ROMHM=0,ROMON=1 */ + MISC=1; + /* System clock initialization */ + CLKSEL=0; + CLKSEL_PLLSEL = 0; /* Select clock source from XTAL */ + PLLCTL_PLLON = 0; /* Disable the PLL */ + SYNR = 24; /* Set the multiplier register */ + REFDV = 15; /* Set the divider register */ + PLLCTL = 192; + PLLCTL_PLLON = 1; /* Enable the PLL */ + while(!CRGFLG_LOCK); /* Wait */ + CLKSEL_PLLSEL = 1; /* Select clock source from PLL */ + /*** End of PE initialization code after reset ***/ + + __asm jmp _Startup; /* Jump to C startup code */ +} + +/* +** =================================================================== +** Method : PE_low_level_init (bean MC9S12DP256_112) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +void PE_low_level_init(void) +{ + /* Common initialization of the CPU registers */ +/* TSCR1: TEN=0,TSWAI=0,TSFRZ=1 */ + output( TSCR1, input( TSCR1 ) & ~192 | 32 ); +/* TCTL2: OM0=0,OL0=0 */ + output( TCTL2, input( TCTL2 ) & ~3 ); +/* TCTL1: OM7=0,OL7=0 */ + output( TCTL1, input( TCTL1 ) & ~192 ); +/* TIE: C0I=0 */ + output( TIE, input( TIE ) & ~1 ); +/* TTOV: TOV0=0 */ + output( TTOV, input( TTOV ) & ~1 ); +/* TSCR2: TOI=0,TCRE=1 */ + output( TSCR2, input( TSCR2 ) & ~128 | 8 ); +/* TIOS: IOS7=1,IOS0=1 */ + output( TIOS, input( TIOS ) | 129 ); +/* PWMCTL: PSWAI=0,PFRZ=0 */ + output( PWMCTL, input( PWMCTL ) & ~12 ); +/* PWMSDN: PWMIF=0,PWMIE=0,PWMRSTRT=0,PWMLVL=0,??=0,PWM7IN=0,PWM7INL=0,PWM7ENA=0 */ + output( PWMSDN, 0 ); +/* ICSYS: SH37=0,SH26=0,SH15=0,SH04=0,TFMOD=0,PACMX=0,BUFEN=0,LATQ=0 */ + output( ICSYS, 0 ); +/* MCCTL: MODMC=1 */ + output( MCCTL, input( MCCTL ) | 64 ); + /* ### MC9S12DP256_112 "Cpu" init code ... */ + /* ### TimerInt "TickTimer" init code ... */ + TickTimer_Init(); + /* ### ByteIO "Byte1" init code ... */ + PORTB = 255; /* Prepare value for output */ + DDRB = 255; /* Set direction to output */ + /* ### Asynchro serial "COM0" init code ... */ + DDRS &= ~1; + PTS |= 2; + DDRS |= 2; + COM0_Init(); + /* Common peripheral initialization - ENABLE */ +/* TSCR1: TEN=1 */ + output( TSCR1, input( TSCR1 ) | 128 ); + INTCR_IRQEN = 0; /* Disable the IRQ interrupt. IRQ interrupt is enabled after CPU reset by default. */ + __DI(); /* Disable interrupts */ +} + +/* END Cpu. */ + +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/20080212/Demo/HCS12_CodeWarrior_banked/CODE/Cpu.H b/20080212/Demo/HCS12_CodeWarrior_banked/CODE/Cpu.H new file mode 100644 index 000000000..2c554db7f --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_banked/CODE/Cpu.H @@ -0,0 +1,111 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : Cpu.H +** Project : RTOSDemo +** Processor : MC9S12DP256BCPV +** Beantype : MC9S12DP256_112 +** Version : Bean 01.148, Driver 01.09, CPU db: 2.87.283 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 14/06/2005, 16:34 +** Abstract : +** This bean "MC9S12DP256_112" implements properties, methods, +** and events of the CPU. +** Settings : +** +** Contents : +** EnableInt - void Cpu_EnableInt(void); +** DisableInt - void Cpu_DisableInt(void); +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + +#ifndef __Cpu +#define __Cpu + +/* Active configuration define symbol */ +#define PEcfg_112pin 1 + +/*Include shared modules, which are used for whole project*/ +#include "PE_Types.h" +#include "PE_Error.h" +#include "PE_Const.h" +#include "IO_Map.h" +#include "PE_Timer.h" + +/* MODULE Cpu. */ + + +/* Global variables */ +extern volatile byte CCR_reg; /* Current CCR reegister */ +extern byte CpuMode; /* Current speed mode */ + + + + +#define Cpu_DisableInt() __DI() /* Disable interrupts */ +/* +** =================================================================== +** Method : Cpu_DisableInt (bean MC9S12DP256_112) +** +** Description : +** Disable maskable interrupts +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ + +#define Cpu_EnableInt() __EI() /* Enable interrupts */ +/* +** =================================================================== +** Method : Cpu_EnableInt (bean MC9S12DP256_112) +** +** Description : +** Enable maskable interrupts +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ + +#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */ + +__interrupt void Cpu_Interrupt(void); +/* +** =================================================================== +** Method : Cpu_Interrupt (bean MC9S12DP256_112) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ + +#pragma CODE_SEG DEFAULT /* Change code section to DEFAULT. */ + +void PE_low_level_init(void); +/* +** =================================================================== +** Method : PE_low_level_init (bean MC9S12DP256_112) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ + +/* END Cpu. */ + +#endif /* ifndef __Cpu */ +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/20080212/Demo/HCS12_CodeWarrior_banked/CODE/Events.C b/20080212/Demo/HCS12_CodeWarrior_banked/CODE/Events.C new file mode 100644 index 000000000..de1680f54 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_banked/CODE/Events.C @@ -0,0 +1,153 @@ +/** ################################################################### +** Filename : Events.C +** Project : RTOSDemo +** Processor : MC9S12DP256BCPV +** Beantype : Events +** Version : Driver 01.01 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 14/06/2005, 16:34 +** Abstract : +** This is user's event module. +** Put your event handler code here. +** Settings : +** Contents : +** TickTimer_OnInterrupt - void TickTimer_OnInterrupt(void); +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ +/* MODULE Events */ + + +/*Including used modules for compilling procedure*/ +#include "Cpu.h" +#include "Events.h" +#include "TickTimer.h" +#include "Byte1.h" +#include "COM0.h" + +/*Include shared modules, which are used for whole project*/ +#include "PE_Types.h" +#include "PE_Error.h" +#include "PE_Const.h" +#include "IO_Map.h" +#include "PE_Timer.h" + +/* +** =================================================================== +** Event : TickTimer_OnInterrupt (module Events) +** +** From bean : TickTimer [TimerInt] +** Description : +** When a timer interrupt occurs this event is called (only +** when the bean is enabled - "Enable" and the events are +** enabled - "EnableEvent"). +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +void TickTimer_OnInterrupt(void) +{ + /* Write your code here ... */ +} + + +/* +** =================================================================== +** Event : COM0_OnError (module Events) +** +** From bean : COM0 [AsynchroSerial] +** Description : +** This event is called when a channel error (not the error +** returned by a given method) occurs. The errors can be +** read using method. +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +void COM0_OnError(void) +{ + /* Write your code here ... */ +} + +/* +** =================================================================== +** Event : COM0_OnRxChar (module Events) +** +** From bean : COM0 [AsynchroSerial] +** Description : +** This event is called after a correct character is +** received. This +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +void COM0_OnRxChar(void) +{ + /* Write your code here ... */ +} + +/* +** =================================================================== +** Event : COM0_OnTxChar (module Events) +** +** From bean : COM0 [AsynchroSerial] +** Description : +** This event is called after a character is transmitted. +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +void COM0_OnTxChar(void) +{ + /* Write your code here ... */ +} + +/* +** =================================================================== +** Event : COM0_OnFullRxBuf (module Events) +** +** From bean : COM0 [AsynchroSerial] +** Description : +** This event is called when the input buffer is full. +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +void COM0_OnFullRxBuf(void) +{ + /* Write your code here ... */ +} + +/* +** =================================================================== +** Event : COM0_OnFreeTxBuf (module Events) +** +** From bean : COM0 [AsynchroSerial] +** Description : +** This event is called after the last character in output +** buffer is transmitted. +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +void COM0_OnFreeTxBuf(void) +{ + /* Write your code here ... */ +} + +/* END Events */ + +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/20080212/Demo/HCS12_CodeWarrior_banked/CODE/Events.H b/20080212/Demo/HCS12_CodeWarrior_banked/CODE/Events.H new file mode 100644 index 000000000..f8f27b947 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_banked/CODE/Events.H @@ -0,0 +1,130 @@ +/** ################################################################### +** Filename : Events.H +** Project : RTOSDemo +** Processor : MC9S12DP256BCPV +** Beantype : Events +** Version : Driver 01.01 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 14/06/2005, 16:34 +** Abstract : +** This is user's event module. +** Put your event handler code here. +** Settings : +** Contents : +** TickTimer_OnInterrupt - void TickTimer_OnInterrupt(void); +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + +#ifndef __Events_H +#define __Events_H +/* MODULE Events */ + +#include "PE_Types.h" +#include "PE_Error.h" +#include "PE_Const.h" +#include "IO_Map.h" +#include "PE_Timer.h" + +void TickTimer_OnInterrupt(void); +/* +** =================================================================== +** Event : TickTimer_OnInterrupt (module Events) +** +** From bean : TickTimer [TimerInt] +** Description : +** When a timer interrupt occurs this event is called (only +** when the bean is enabled - "Enable" and the events are +** enabled - "EnableEvent"). +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ + + +void COM0_OnError(void); +/* +** =================================================================== +** Event : COM0_OnError (module Events) +** +** From bean : COM0 [AsynchroSerial] +** Description : +** This event is called when a channel error (not the error +** returned by a given method) occurs. The errors can be +** read using method. +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ + +void COM0_OnRxChar(void); +/* +** =================================================================== +** Event : COM0_OnRxChar (module Events) +** +** From bean : COM0 [AsynchroSerial] +** Description : +** This event is called after a correct character is +** received. This +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ + +void COM0_OnTxChar(void); +/* +** =================================================================== +** Event : COM0_OnTxChar (module Events) +** +** From bean : COM0 [AsynchroSerial] +** Description : +** This event is called after a character is transmitted. +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ + +void COM0_OnFullRxBuf(void); +/* +** =================================================================== +** Event : COM0_OnFullRxBuf (module Events) +** +** From bean : COM0 [AsynchroSerial] +** Description : +** This event is called when the input buffer is full. +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ + +void COM0_OnFreeTxBuf(void); +/* +** =================================================================== +** Event : COM0_OnFreeTxBuf (module Events) +** +** From bean : COM0 [AsynchroSerial] +** Description : +** This event is called after the last character in output +** buffer is transmitted. +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ + +/* END Events */ +#endif /* __Events_H*/ + +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/20080212/Demo/HCS12_CodeWarrior_banked/CODE/IO_Map.C b/20080212/Demo/HCS12_CodeWarrior_banked/CODE/IO_Map.C new file mode 100644 index 000000000..549a0292f --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_banked/CODE/IO_Map.C @@ -0,0 +1,559 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : IO_Map.C +** Project : RTOSDemo +** Processor : MC9S12DP256BCPV +** Beantype : IO_Map +** Version : Driver 01.01 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 13/06/2005, 20:14 +** Abstract : +** This bean "IO_Map" implements an IO devices mapping. +** Settings : +** +** Contents : +** No public methods +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ +/* Based on CPU DB MC9S12DP256_112, version 2.87.278 */ +#include "PE_types.h" +#include "IO_Map.h" + +volatile ARMCOPSTR _ARMCOP; /* CRG COP Timer Arm/Reset Register */ +volatile ATD0DIENSTR _ATD0DIEN; /* ATD 0 Input Enable Mask Register */ +volatile ATD0STAT0STR _ATD0STAT0; /* ATD 0 Status Register 0 */ +volatile ATD0STAT1STR _ATD0STAT1; /* ATD 0 Status Register 1 */ +volatile ATD1DIENSTR _ATD1DIEN; /* ATD 1 Input Enable Mask Register */ +volatile ATD1STAT0STR _ATD1STAT0; /* ATD 1 Status Register 0 */ +volatile ATD1STAT1STR _ATD1STAT1; /* ATD 1 Status Register 1 */ +volatile BDMCCRSTR _BDMCCR; /* BDM CCR Holding Register */ +volatile BDMINRSTR _BDMINR; /* BDM Internal Register Position Register */ +volatile BDMSTSSTR _BDMSTS; /* BDM Status Register */ +volatile BKP0HSTR _BKP0H; /* First Address High Byte Breakpoint Register */ +volatile BKP0LSTR _BKP0L; /* First Address Low Byte Breakpoint Register */ +volatile BKP0XSTR _BKP0X; /* First Address Memory Expansion Breakpoint Register */ +volatile BKP1HSTR _BKP1H; /* Data (Second Address) High Byte Breakpoint Register */ +volatile BKP1LSTR _BKP1L; /* Data (Second Address) Low Byte Breakpoint Register */ +volatile BKP1XSTR _BKP1X; /* Second Address Memory Expansion Breakpoint Register */ +volatile BKPCT0STR _BKPCT0; /* Breakpoint Control Register 0 */ +volatile BKPCT1STR _BKPCT1; /* Breakpoint Control Register 1 */ +volatile CAN0BTR0STR _CAN0BTR0; /* MSCAN 0 Bus Timing Register 0 */ +volatile CAN0BTR1STR _CAN0BTR1; /* MSCAN 0 Bus Timing Register 1 */ +volatile CAN0CTL0STR _CAN0CTL0; /* MSCAN 0 Control 0 Register */ +volatile CAN0CTL1STR _CAN0CTL1; /* MSCAN 0 Control 1 Register */ +volatile CAN0IDACSTR _CAN0IDAC; /* MSCAN 0 Identifier Acceptance Control Register */ +volatile CAN0IDAR0STR _CAN0IDAR0; /* MSCAN 0 Identifier Acceptance Register 0 */ +volatile CAN0IDAR1STR _CAN0IDAR1; /* MSCAN 0 Identifier Acceptance Register 1 */ +volatile CAN0IDAR2STR _CAN0IDAR2; /* MSCAN 0 Identifier Acceptance Register 2 */ +volatile CAN0IDAR3STR _CAN0IDAR3; /* MSCAN 0 Identifier Acceptance Register 3 */ +volatile CAN0IDAR4STR _CAN0IDAR4; /* MSCAN 0 Identifier Acceptance Register 4 */ +volatile CAN0IDAR5STR _CAN0IDAR5; /* MSCAN 0 Identifier Acceptance Register 5 */ +volatile CAN0IDAR6STR _CAN0IDAR6; /* MSCAN 0 Identifier Acceptance Register 6 */ +volatile CAN0IDAR7STR _CAN0IDAR7; /* MSCAN 0 Identifier Acceptance Register 7 */ +volatile CAN0IDMR0STR _CAN0IDMR0; /* MSCAN 0 Identifier Mask Register 0 */ +volatile CAN0IDMR1STR _CAN0IDMR1; /* MSCAN 0 Identifier Mask Register 1 */ +volatile CAN0IDMR2STR _CAN0IDMR2; /* MSCAN 0 Identifier Mask Register 2 */ +volatile CAN0IDMR3STR _CAN0IDMR3; /* MSCAN 0 Identifier Mask Register 3 */ +volatile CAN0IDMR4STR _CAN0IDMR4; /* MSCAN 0 Identifier Mask Register 4 */ +volatile CAN0IDMR5STR _CAN0IDMR5; /* MSCAN 0 Identifier Mask Register 5 */ +volatile CAN0IDMR6STR _CAN0IDMR6; /* MSCAN 0 Identifier Mask Register 6 */ +volatile CAN0IDMR7STR _CAN0IDMR7; /* MSCAN 0 Identifier Mask Register 7 */ +volatile CAN0RFLGSTR _CAN0RFLG; /* MSCAN 0 Receiver Flag Register */ +volatile CAN0RIERSTR _CAN0RIER; /* MSCAN 0 Receiver Interrupt Enable Register */ +volatile CAN0RXDLRSTR _CAN0RXDLR; /* MSCAN 0 Receive Data Length Register */ +volatile CAN0RXDSR0STR _CAN0RXDSR0; /* MSCAN 0 Receive Data Segment Register 0 */ +volatile CAN0RXDSR1STR _CAN0RXDSR1; /* MSCAN 0 Receive Data Segment Register 1 */ +volatile CAN0RXDSR2STR _CAN0RXDSR2; /* MSCAN 0 Receive Data Segment Register 2 */ +volatile CAN0RXDSR3STR _CAN0RXDSR3; /* MSCAN 0 Receive Data Segment Register 3 */ +volatile CAN0RXDSR4STR _CAN0RXDSR4; /* MSCAN 0 Receive Data Segment Register 4 */ +volatile CAN0RXDSR5STR _CAN0RXDSR5; /* MSCAN 0 Receive Data Segment Register 5 */ +volatile CAN0RXDSR6STR _CAN0RXDSR6; /* MSCAN 0 Receive Data Segment Register 6 */ +volatile CAN0RXDSR7STR _CAN0RXDSR7; /* MSCAN 0 Receive Data Segment Register 7 */ +volatile CAN0RXERRSTR _CAN0RXERR; /* MSCAN 0 Receive Error Counter Register */ +volatile CAN0RXIDR0STR _CAN0RXIDR0; /* MSCAN 0 Receive Identifier Register 0 */ +volatile CAN0RXIDR1STR _CAN0RXIDR1; /* MSCAN 0 Receive Identifier Register 1 */ +volatile CAN0RXIDR2STR _CAN0RXIDR2; /* MSCAN 0 Receive Identifier Register 2 */ +volatile CAN0RXIDR3STR _CAN0RXIDR3; /* MSCAN 0 Receive Identifier Register 3 */ +volatile CAN0TAAKSTR _CAN0TAAK; /* MSCAN 0 Transmitter Message Abort Control */ +volatile CAN0TARQSTR _CAN0TARQ; /* MSCAN 0 Transmitter Message Abort Request */ +volatile CAN0TBSELSTR _CAN0TBSEL; /* MSCAN 0 Transmit Buffer Selection */ +volatile CAN0TFLGSTR _CAN0TFLG; /* MSCAN 0 Transmitter Flag Register */ +volatile CAN0TIERSTR _CAN0TIER; /* MSCAN 0 Transmitter Interrupt Enable Register */ +volatile CAN0TXDLRSTR _CAN0TXDLR; /* MSCAN 0 Transmit Data Length Register */ +volatile CAN0TXDSR0STR _CAN0TXDSR0; /* MSCAN 0 Transmit Data Segment Register 0 */ +volatile CAN0TXDSR1STR _CAN0TXDSR1; /* MSCAN 0 Transmit Data Segment Register 1 */ +volatile CAN0TXDSR2STR _CAN0TXDSR2; /* MSCAN 0 Transmit Data Segment Register 2 */ +volatile CAN0TXDSR3STR _CAN0TXDSR3; /* MSCAN 0 Transmit Data Segment Register 3 */ +volatile CAN0TXDSR4STR _CAN0TXDSR4; /* MSCAN 0 Transmit Data Segment Register 4 */ +volatile CAN0TXDSR5STR _CAN0TXDSR5; /* MSCAN 0 Transmit Data Segment Register 5 */ +volatile CAN0TXDSR6STR _CAN0TXDSR6; /* MSCAN 0 Transmit Data Segment Register 6 */ +volatile CAN0TXDSR7STR _CAN0TXDSR7; /* MSCAN 0 Transmit Data Segment Register 7 */ +volatile CAN0TXERRSTR _CAN0TXERR; /* MSCAN 0 Transmit Error Counter Register */ +volatile CAN0TXIDR0STR _CAN0TXIDR0; /* MSCAN 0 Transmit Identifier Register 0 */ +volatile CAN0TXIDR1STR _CAN0TXIDR1; /* MSCAN 0 Transmit Identifier Register 1 */ +volatile CAN0TXIDR2STR _CAN0TXIDR2; /* MSCAN 0 Transmit Identifier Register 2 */ +volatile CAN0TXIDR3STR _CAN0TXIDR3; /* MSCAN 0 Transmit Identifier Register 3 */ +volatile CAN0TXTBPRSTR _CAN0TXTBPR; /* MSCAN 0 Transmit Buffer Priority */ +volatile CAN1BTR0STR _CAN1BTR0; /* MSCAN 1 Bus Timing Register 0 */ +volatile CAN1BTR1STR _CAN1BTR1; /* MSCAN 1 Bus Timing Register 1 */ +volatile CAN1CTL0STR _CAN1CTL0; /* MSCAN 1 Control 0 Register */ +volatile CAN1CTL1STR _CAN1CTL1; /* MSCAN 1 Control 1 Register */ +volatile CAN1IDACSTR _CAN1IDAC; /* MSCAN 1 Identifier Acceptance Control Register */ +volatile CAN1IDAR0STR _CAN1IDAR0; /* MSCAN 1 Identifier Acceptance Register 0 */ +volatile CAN1IDAR1STR _CAN1IDAR1; /* MSCAN 1 Identifier Acceptance Register 1 */ +volatile CAN1IDAR2STR _CAN1IDAR2; /* MSCAN 1 Identifier Acceptance Register 2 */ +volatile CAN1IDAR3STR _CAN1IDAR3; /* MSCAN 1 Identifier Acceptance Register 3 */ +volatile CAN1IDAR4STR _CAN1IDAR4; /* MSCAN 1 Identifier Acceptance Register 4 */ +volatile CAN1IDAR5STR _CAN1IDAR5; /* MSCAN 1 Identifier Acceptance Register 5 */ +volatile CAN1IDAR6STR _CAN1IDAR6; /* MSCAN 1 Identifier Acceptance Register 6 */ +volatile CAN1IDAR7STR _CAN1IDAR7; /* MSCAN 1 Identifier Acceptance Register 7 */ +volatile CAN1IDMR0STR _CAN1IDMR0; /* MSCAN 1 Identifier Mask Register 0 */ +volatile CAN1IDMR1STR _CAN1IDMR1; /* MSCAN 1 Identifier Mask Register 1 */ +volatile CAN1IDMR2STR _CAN1IDMR2; /* MSCAN 1 Identifier Mask Register 2 */ +volatile CAN1IDMR3STR _CAN1IDMR3; /* MSCAN 1 Identifier Mask Register 3 */ +volatile CAN1IDMR4STR _CAN1IDMR4; /* MSCAN 1 Identifier Mask Register 4 */ +volatile CAN1IDMR5STR _CAN1IDMR5; /* MSCAN 1 Identifier Mask Register 5 */ +volatile CAN1IDMR6STR _CAN1IDMR6; /* MSCAN 1 Identifier Mask Register 6 */ +volatile CAN1IDMR7STR _CAN1IDMR7; /* MSCAN 1 Identifier Mask Register 7 */ +volatile CAN1RFLGSTR _CAN1RFLG; /* MSCAN 1 Receiver Flag Register */ +volatile CAN1RIERSTR _CAN1RIER; /* MSCAN 1 Receiver Interrupt Enable Register */ +volatile CAN1RXDLRSTR _CAN1RXDLR; /* MSCAN 1 Receive Data Length Register */ +volatile CAN1RXDSR0STR _CAN1RXDSR0; /* MSCAN 1 Receive Data Segment Register 0 */ +volatile CAN1RXDSR1STR _CAN1RXDSR1; /* MSCAN 1 Receive Data Segment Register 1 */ +volatile CAN1RXDSR2STR _CAN1RXDSR2; /* MSCAN 1 Receive Data Segment Register 2 */ +volatile CAN1RXDSR3STR _CAN1RXDSR3; /* MSCAN 1 Receive Data Segment Register 3 */ +volatile CAN1RXDSR4STR _CAN1RXDSR4; /* MSCAN 1 Receive Data Segment Register 4 */ +volatile CAN1RXDSR5STR _CAN1RXDSR5; /* MSCAN 1 Receive Data Segment Register 5 */ +volatile CAN1RXDSR6STR _CAN1RXDSR6; /* MSCAN 1 Receive Data Segment Register 6 */ +volatile CAN1RXDSR7STR _CAN1RXDSR7; /* MSCAN 1 Receive Data Segment Register 7 */ +volatile CAN1RXERRSTR _CAN1RXERR; /* MSCAN 1 Receive Error Counter Register */ +volatile CAN1RXIDR0STR _CAN1RXIDR0; /* MSCAN 1 Receive Identifier Register 0 */ +volatile CAN1RXIDR1STR _CAN1RXIDR1; /* MSCAN 1 Receive Identifier Register 1 */ +volatile CAN1RXIDR2STR _CAN1RXIDR2; /* MSCAN 1 Receive Identifier Register 2 */ +volatile CAN1RXIDR3STR _CAN1RXIDR3; /* MSCAN 1 Receive Identifier Register 3 */ +volatile CAN1TAAKSTR _CAN1TAAK; /* MSCAN 1 Transmitter Message Abort Control */ +volatile CAN1TARQSTR _CAN1TARQ; /* MSCAN 1 Transmitter Message Abort Request */ +volatile CAN1TBSELSTR _CAN1TBSEL; /* MSCAN 1 Transmit Buffer Selection */ +volatile CAN1TFLGSTR _CAN1TFLG; /* MSCAN 1 Transmitter Flag Register */ +volatile CAN1TIERSTR _CAN1TIER; /* MSCAN 1 Transmitter Interrupt Enable Register */ +volatile CAN1TXDLRSTR _CAN1TXDLR; /* MSCAN 1 Transmit Data Length Register */ +volatile CAN1TXDSR0STR _CAN1TXDSR0; /* MSCAN 1 Transmit Data Segment Register 0 */ +volatile CAN1TXDSR1STR _CAN1TXDSR1; /* MSCAN 1 Transmit Data Segment Register 1 */ +volatile CAN1TXDSR2STR _CAN1TXDSR2; /* MSCAN 1 Transmit Data Segment Register 2 */ +volatile CAN1TXDSR3STR _CAN1TXDSR3; /* MSCAN 1 Transmit Data Segment Register 3 */ +volatile CAN1TXDSR4STR _CAN1TXDSR4; /* MSCAN 1 Transmit Data Segment Register 4 */ +volatile CAN1TXDSR5STR _CAN1TXDSR5; /* MSCAN 1 Transmit Data Segment Register 5 */ +volatile CAN1TXDSR6STR _CAN1TXDSR6; /* MSCAN 1 Transmit Data Segment Register 6 */ +volatile CAN1TXDSR7STR _CAN1TXDSR7; /* MSCAN 1 Transmit Data Segment Register 7 */ +volatile CAN1TXERRSTR _CAN1TXERR; /* MSCAN 1 Transmit Error Counter Register */ +volatile CAN1TXIDR0STR _CAN1TXIDR0; /* MSCAN 1 Transmit Identifier Register 0 */ +volatile CAN1TXIDR1STR _CAN1TXIDR1; /* MSCAN 1 Transmit Identifier Register 1 */ +volatile CAN1TXIDR2STR _CAN1TXIDR2; /* MSCAN 1 Transmit Identifier Register 2 */ +volatile CAN1TXIDR3STR _CAN1TXIDR3; /* MSCAN 1 Transmit Identifier Register 3 */ +volatile CAN1TXTBPRSTR _CAN1TXTBPR; /* MSCAN 1 Transmit Buffer Priority */ +volatile CAN2BTR0STR _CAN2BTR0; /* MSCAN 2 Bus Timing Register 0 */ +volatile CAN2BTR1STR _CAN2BTR1; /* MSCAN 2 Bus Timing Register 1 */ +volatile CAN2CTL0STR _CAN2CTL0; /* MSCAN 2 Control 0 Register */ +volatile CAN2CTL1STR _CAN2CTL1; /* MSCAN 2 Control 1 Register */ +volatile CAN2IDACSTR _CAN2IDAC; /* MSCAN 2 Identifier Acceptance Control Register */ +volatile CAN2IDAR0STR _CAN2IDAR0; /* MSCAN 2 Identifier Acceptance Register 0 */ +volatile CAN2IDAR1STR _CAN2IDAR1; /* MSCAN 2 Identifier Acceptance Register 1 */ +volatile CAN2IDAR2STR _CAN2IDAR2; /* MSCAN 2 Identifier Acceptance Register 2 */ +volatile CAN2IDAR3STR _CAN2IDAR3; /* MSCAN 2 Identifier Acceptance Register 3 */ +volatile CAN2IDAR4STR _CAN2IDAR4; /* MSCAN 2 Identifier Acceptance Register 4 */ +volatile CAN2IDAR5STR _CAN2IDAR5; /* MSCAN 2 Identifier Acceptance Register 5 */ +volatile CAN2IDAR6STR _CAN2IDAR6; /* MSCAN 2 Identifier Acceptance Register 6 */ +volatile CAN2IDAR7STR _CAN2IDAR7; /* MSCAN 2 Identifier Acceptance Register 7 */ +volatile CAN2IDMR0STR _CAN2IDMR0; /* MSCAN 2 Identifier Mask Register 0 */ +volatile CAN2IDMR1STR _CAN2IDMR1; /* MSCAN 2 Identifier Mask Register 1 */ +volatile CAN2IDMR2STR _CAN2IDMR2; /* MSCAN 2 Identifier Mask Register 2 */ +volatile CAN2IDMR3STR _CAN2IDMR3; /* MSCAN 2 Identifier Mask Register 3 */ +volatile CAN2IDMR4STR _CAN2IDMR4; /* MSCAN 2 Identifier Mask Register 4 */ +volatile CAN2IDMR5STR _CAN2IDMR5; /* MSCAN 2 Identifier Mask Register 5 */ +volatile CAN2IDMR6STR _CAN2IDMR6; /* MSCAN 2 Identifier Mask Register 6 */ +volatile CAN2IDMR7STR _CAN2IDMR7; /* MSCAN 2 Identifier Mask Register 7 */ +volatile CAN2RFLGSTR _CAN2RFLG; /* MSCAN 2 Receiver Flag Register */ +volatile CAN2RIERSTR _CAN2RIER; /* MSCAN 2 Receiver Interrupt Enable Register */ +volatile CAN2RXDLRSTR _CAN2RXDLR; /* MSCAN 2 Receive Data Length Register */ +volatile CAN2RXDSR0STR _CAN2RXDSR0; /* MSCAN 2 Receive Data Segment Register 0 */ +volatile CAN2RXDSR1STR _CAN2RXDSR1; /* MSCAN 2 Receive Data Segment Register 1 */ +volatile CAN2RXDSR2STR _CAN2RXDSR2; /* MSCAN 2 Receive Data Segment Register 2 */ +volatile CAN2RXDSR3STR _CAN2RXDSR3; /* MSCAN 2 Receive Data Segment Register 3 */ +volatile CAN2RXDSR4STR _CAN2RXDSR4; /* MSCAN 2 Receive Data Segment Register 4 */ +volatile CAN2RXDSR5STR _CAN2RXDSR5; /* MSCAN 2 Receive Data Segment Register 5 */ +volatile CAN2RXDSR6STR _CAN2RXDSR6; /* MSCAN 2 Receive Data Segment Register 6 */ +volatile CAN2RXDSR7STR _CAN2RXDSR7; /* MSCAN 2 Receive Data Segment Register 7 */ +volatile CAN2RXERRSTR _CAN2RXERR; /* MSCAN 2 Receive Error Counter Register */ +volatile CAN2RXIDR0STR _CAN2RXIDR0; /* MSCAN 2 Receive Identifier Register 0 */ +volatile CAN2RXIDR1STR _CAN2RXIDR1; /* MSCAN 2 Receive Identifier Register 1 */ +volatile CAN2RXIDR2STR _CAN2RXIDR2; /* MSCAN 2 Receive Identifier Register 2 */ +volatile CAN2RXIDR3STR _CAN2RXIDR3; /* MSCAN 2 Receive Identifier Register 3 */ +volatile CAN2TAAKSTR _CAN2TAAK; /* MSCAN 2 Transmitter Message Abort Control */ +volatile CAN2TARQSTR _CAN2TARQ; /* MSCAN 2 Transmitter Message Abort Request */ +volatile CAN2TBSELSTR _CAN2TBSEL; /* MSCAN 2 Transmit Buffer Selection */ +volatile CAN2TFLGSTR _CAN2TFLG; /* MSCAN 2 Transmitter Flag Register */ +volatile CAN2TIERSTR _CAN2TIER; /* MSCAN 2 Transmitter Interrupt Enable Register */ +volatile CAN2TXDLRSTR _CAN2TXDLR; /* MSCAN 2 Transmit Data Length Register */ +volatile CAN2TXDSR0STR _CAN2TXDSR0; /* MSCAN 2 Transmit Data Segment Register 0 */ +volatile CAN2TXDSR1STR _CAN2TXDSR1; /* MSCAN 2 Transmit Data Segment Register 1 */ +volatile CAN2TXDSR2STR _CAN2TXDSR2; /* MSCAN 2 Transmit Data Segment Register 2 */ +volatile CAN2TXDSR3STR _CAN2TXDSR3; /* MSCAN 2 Transmit Data Segment Register 3 */ +volatile CAN2TXDSR4STR _CAN2TXDSR4; /* MSCAN 2 Transmit Data Segment Register 4 */ +volatile CAN2TXDSR5STR _CAN2TXDSR5; /* MSCAN 2 Transmit Data Segment Register 5 */ +volatile CAN2TXDSR6STR _CAN2TXDSR6; /* MSCAN 2 Transmit Data Segment Register 6 */ +volatile CAN2TXDSR7STR _CAN2TXDSR7; /* MSCAN 2 Transmit Data Segment Register 7 */ +volatile CAN2TXERRSTR _CAN2TXERR; /* MSCAN 2 Transmit Error Counter Register */ +volatile CAN2TXIDR0STR _CAN2TXIDR0; /* MSCAN 2 Transmit Identifier Register 0 */ +volatile CAN2TXIDR1STR _CAN2TXIDR1; /* MSCAN 2 Transmit Identifier Register 1 */ +volatile CAN2TXIDR2STR _CAN2TXIDR2; /* MSCAN 2 Transmit Identifier Register 2 */ +volatile CAN2TXIDR3STR _CAN2TXIDR3; /* MSCAN 2 Transmit Identifier Register 3 */ +volatile CAN2TXTBPRSTR _CAN2TXTBPR; /* MSCAN 2 Transmit Buffer Priority */ +volatile CAN3BTR0STR _CAN3BTR0; /* MSCAN 3 Bus Timing Register 0 */ +volatile CAN3BTR1STR _CAN3BTR1; /* MSCAN 3 Bus Timing Register 1 */ +volatile CAN3CTL0STR _CAN3CTL0; /* MSCAN 3 Control 0 Register */ +volatile CAN3CTL1STR _CAN3CTL1; /* MSCAN 3 Control 1 Register */ +volatile CAN3IDACSTR _CAN3IDAC; /* MSCAN 3 Identifier Acceptance Control Register */ +volatile CAN3IDAR0STR _CAN3IDAR0; /* MSCAN 3 Identifier Acceptance Register 0 */ +volatile CAN3IDAR1STR _CAN3IDAR1; /* MSCAN 3 Identifier Acceptance Register 1 */ +volatile CAN3IDAR2STR _CAN3IDAR2; /* MSCAN 3 Identifier Acceptance Register 2 */ +volatile CAN3IDAR3STR _CAN3IDAR3; /* MSCAN 3 Identifier Acceptance Register 3 */ +volatile CAN3IDAR4STR _CAN3IDAR4; /* MSCAN 3 Identifier Acceptance Register 4 */ +volatile CAN3IDAR5STR _CAN3IDAR5; /* MSCAN 3 Identifier Acceptance Register 5 */ +volatile CAN3IDAR6STR _CAN3IDAR6; /* MSCAN 3 Identifier Acceptance Register 6 */ +volatile CAN3IDAR7STR _CAN3IDAR7; /* MSCAN 3 Identifier Acceptance Register 7 */ +volatile CAN3IDMR0STR _CAN3IDMR0; /* MSCAN 3 Identifier Mask Register 0 */ +volatile CAN3IDMR1STR _CAN3IDMR1; /* MSCAN 3 Identifier Mask Register 1 */ +volatile CAN3IDMR2STR _CAN3IDMR2; /* MSCAN 3 Identifier Mask Register 2 */ +volatile CAN3IDMR3STR _CAN3IDMR3; /* MSCAN 3 Identifier Mask Register 3 */ +volatile CAN3IDMR4STR _CAN3IDMR4; /* MSCAN 3 Identifier Mask Register 4 */ +volatile CAN3IDMR5STR _CAN3IDMR5; /* MSCAN 3 Identifier Mask Register 5 */ +volatile CAN3IDMR6STR _CAN3IDMR6; /* MSCAN 3 Identifier Mask Register 6 */ +volatile CAN3IDMR7STR _CAN3IDMR7; /* MSCAN 3 Identifier Mask Register 7 */ +volatile CAN3RFLGSTR _CAN3RFLG; /* MSCAN 3 Receiver Flag Register */ +volatile CAN3RIERSTR _CAN3RIER; /* MSCAN 3 Receiver Interrupt Enable Register */ +volatile CAN3RXDLRSTR _CAN3RXDLR; /* MSCAN 3 Receive Data Length Register */ +volatile CAN3RXDSR0STR _CAN3RXDSR0; /* MSCAN 3 Receive Data Segment Register 0 */ +volatile CAN3RXDSR1STR _CAN3RXDSR1; /* MSCAN 3 Receive Data Segment Register 1 */ +volatile CAN3RXDSR2STR _CAN3RXDSR2; /* MSCAN 3 Receive Data Segment Register 2 */ +volatile CAN3RXDSR3STR _CAN3RXDSR3; /* MSCAN 3 Receive Data Segment Register 3 */ +volatile CAN3RXDSR4STR _CAN3RXDSR4; /* MSCAN 3 Receive Data Segment Register 4 */ +volatile CAN3RXDSR5STR _CAN3RXDSR5; /* MSCAN 3 Receive Data Segment Register 5 */ +volatile CAN3RXDSR6STR _CAN3RXDSR6; /* MSCAN 3 Receive Data Segment Register 6 */ +volatile CAN3RXDSR7STR _CAN3RXDSR7; /* MSCAN 3 Receive Data Segment Register 7 */ +volatile CAN3RXERRSTR _CAN3RXERR; /* MSCAN 3 Receive Error Counter Register */ +volatile CAN3RXIDR0STR _CAN3RXIDR0; /* MSCAN 3 Receive Identifier Register 0 */ +volatile CAN3RXIDR1STR _CAN3RXIDR1; /* MSCAN 3 Receive Identifier Register 1 */ +volatile CAN3RXIDR2STR _CAN3RXIDR2; /* MSCAN 3 Receive Identifier Register 2 */ +volatile CAN3RXIDR3STR _CAN3RXIDR3; /* MSCAN 3 Receive Identifier Register 3 */ +volatile CAN3TAAKSTR _CAN3TAAK; /* MSCAN 3 Transmitter Message Abort Control */ +volatile CAN3TARQSTR _CAN3TARQ; /* MSCAN 3 Transmitter Message Abort Request */ +volatile CAN3TBSELSTR _CAN3TBSEL; /* MSCAN 3 Transmit Buffer Selection */ +volatile CAN3TFLGSTR _CAN3TFLG; /* MSCAN 3 Transmitter Flag Register */ +volatile CAN3TIERSTR _CAN3TIER; /* MSCAN 3 Transmitter Interrupt Enable Register */ +volatile CAN3TXDLRSTR _CAN3TXDLR; /* MSCAN 3 Transmit Data Length Register */ +volatile CAN3TXDSR0STR _CAN3TXDSR0; /* MSCAN 3 Transmit Data Segment Register 0 */ +volatile CAN3TXDSR1STR _CAN3TXDSR1; /* MSCAN 3 Transmit Data Segment Register 1 */ +volatile CAN3TXDSR2STR _CAN3TXDSR2; /* MSCAN 3 Transmit Data Segment Register 2 */ +volatile CAN3TXDSR3STR _CAN3TXDSR3; /* MSCAN 3 Transmit Data Segment Register 3 */ +volatile CAN3TXDSR4STR _CAN3TXDSR4; /* MSCAN 3 Transmit Data Segment Register 4 */ +volatile CAN3TXDSR5STR _CAN3TXDSR5; /* MSCAN 3 Transmit Data Segment Register 5 */ +volatile CAN3TXDSR6STR _CAN3TXDSR6; /* MSCAN 3 Transmit Data Segment Register 6 */ +volatile CAN3TXDSR7STR _CAN3TXDSR7; /* MSCAN 3 Transmit Data Segment Register 7 */ +volatile CAN3TXERRSTR _CAN3TXERR; /* MSCAN 3 Transmit Error Counter Register */ +volatile CAN3TXIDR0STR _CAN3TXIDR0; /* MSCAN 3 Transmit Identifier Register 0 */ +volatile CAN3TXIDR1STR _CAN3TXIDR1; /* MSCAN 3 Transmit Identifier Register 1 */ +volatile CAN3TXIDR2STR _CAN3TXIDR2; /* MSCAN 3 Transmit Identifier Register 2 */ +volatile CAN3TXIDR3STR _CAN3TXIDR3; /* MSCAN 3 Transmit Identifier Register 3 */ +volatile CAN3TXTBPRSTR _CAN3TXTBPR; /* MSCAN 3 Transmit Buffer Priority */ +volatile CAN4BTR0STR _CAN4BTR0; /* MSCAN4 Bus Timing Register 0 */ +volatile CAN4BTR1STR _CAN4BTR1; /* MSCAN4 Bus Timing Register 1 */ +volatile CAN4CTL0STR _CAN4CTL0; /* MSCAN4 Control 0 Register */ +volatile CAN4CTL1STR _CAN4CTL1; /* MSCAN4 Control 1 Register */ +volatile CAN4IDACSTR _CAN4IDAC; /* MSCAN4 Identifier Acceptance Control Register */ +volatile CAN4IDAR0STR _CAN4IDAR0; /* MSCAN4 Identifier Acceptance Register 0 */ +volatile CAN4IDAR1STR _CAN4IDAR1; /* MSCAN4 Identifier Acceptance Register 1 */ +volatile CAN4IDAR2STR _CAN4IDAR2; /* MSCAN4 Identifier Acceptance Register 2 */ +volatile CAN4IDAR3STR _CAN4IDAR3; /* MSCAN4 Identifier Acceptance Register 3 */ +volatile CAN4IDAR4STR _CAN4IDAR4; /* MSCAN4 Identifier Acceptance Register 4 */ +volatile CAN4IDAR5STR _CAN4IDAR5; /* MSCAN4 Identifier Acceptance Register 5 */ +volatile CAN4IDAR6STR _CAN4IDAR6; /* MSCAN4 Identifier Acceptance Register 6 */ +volatile CAN4IDAR7STR _CAN4IDAR7; /* MSCAN4 Identifier Acceptance Register 7 */ +volatile CAN4IDMR0STR _CAN4IDMR0; /* MSCAN4 Identifier Mask Register 0 */ +volatile CAN4IDMR1STR _CAN4IDMR1; /* MSCAN4 Identifier Mask Register 1 */ +volatile CAN4IDMR2STR _CAN4IDMR2; /* MSCAN4 Identifier Mask Register 2 */ +volatile CAN4IDMR3STR _CAN4IDMR3; /* MSCAN4 Identifier Mask Register 3 */ +volatile CAN4IDMR4STR _CAN4IDMR4; /* MSCAN4 Identifier Mask Register 4 */ +volatile CAN4IDMR5STR _CAN4IDMR5; /* MSCAN4 Identifier Mask Register 5 */ +volatile CAN4IDMR6STR _CAN4IDMR6; /* MSCAN4 Identifier Mask Register 6 */ +volatile CAN4IDMR7STR _CAN4IDMR7; /* MSCAN4 Identifier Mask Register 7 */ +volatile CAN4RFLGSTR _CAN4RFLG; /* MSCAN4 Receiver Flag Register */ +volatile CAN4RIERSTR _CAN4RIER; /* MSCAN4 Receiver Interrupt Enable Register */ +volatile CAN4RXDLRSTR _CAN4RXDLR; /* MSCAN4 Receive Data Length Register */ +volatile CAN4RXDSR0STR _CAN4RXDSR0; /* MSCAN4 Receive Data Segment Register 0 */ +volatile CAN4RXDSR1STR _CAN4RXDSR1; /* MSCAN4 Receive Data Segment Register 1 */ +volatile CAN4RXDSR2STR _CAN4RXDSR2; /* MSCAN4 Receive Data Segment Register 2 */ +volatile CAN4RXDSR3STR _CAN4RXDSR3; /* MSCAN4 Receive Data Segment Register 3 */ +volatile CAN4RXDSR4STR _CAN4RXDSR4; /* MSCAN4 Receive Data Segment Register 4 */ +volatile CAN4RXDSR5STR _CAN4RXDSR5; /* MSCAN4 Receive Data Segment Register 5 */ +volatile CAN4RXDSR6STR _CAN4RXDSR6; /* MSCAN4 Receive Data Segment Register 6 */ +volatile CAN4RXDSR7STR _CAN4RXDSR7; /* MSCAN4 Receive Data Segment Register 7 */ +volatile CAN4RXERRSTR _CAN4RXERR; /* MSCAN4 Receive Error Counter Register */ +volatile CAN4RXIDR0STR _CAN4RXIDR0; /* MSCAN4 Receive Identifier Register 0 */ +volatile CAN4RXIDR1STR _CAN4RXIDR1; /* MSCAN4 Receive Identifier Register 1 */ +volatile CAN4RXIDR2STR _CAN4RXIDR2; /* MSCAN4 Receive Identifier Register 2 */ +volatile CAN4RXIDR3STR _CAN4RXIDR3; /* MSCAN4 Receive Identifier Register 3 */ +volatile CAN4TAAKSTR _CAN4TAAK; /* MSCAN4 Transmitter Message Abort Control */ +volatile CAN4TARQSTR _CAN4TARQ; /* MSCAN 4 Transmitter Message Abort Request */ +volatile CAN4TBSELSTR _CAN4TBSEL; /* MSCAN4 Transmit Buffer Selection */ +volatile CAN4TFLGSTR _CAN4TFLG; /* MSCAN4 Transmitter Flag Register */ +volatile CAN4TIERSTR _CAN4TIER; /* MSCAN4 Transmitter Interrupt Enable Register */ +volatile CAN4TXDLRSTR _CAN4TXDLR; /* MSCAN4 Transmit Data Length Register */ +volatile CAN4TXDSR0STR _CAN4TXDSR0; /* MSCAN4 Transmit Data Segment Register 0 */ +volatile CAN4TXDSR1STR _CAN4TXDSR1; /* MSCAN4 Transmit Data Segment Register 1 */ +volatile CAN4TXDSR2STR _CAN4TXDSR2; /* MSCAN4 Transmit Data Segment Register 2 */ +volatile CAN4TXDSR3STR _CAN4TXDSR3; /* MSCAN4 Transmit Data Segment Register 3 */ +volatile CAN4TXDSR4STR _CAN4TXDSR4; /* MSCAN4 Transmit Data Segment Register 4 */ +volatile CAN4TXDSR5STR _CAN4TXDSR5; /* MSCAN4 Transmit Data Segment Register 5 */ +volatile CAN4TXDSR6STR _CAN4TXDSR6; /* MSCAN4 Transmit Data Segment Register 6 */ +volatile CAN4TXDSR7STR _CAN4TXDSR7; /* MSCAN4 Transmit Data Segment Register 7 */ +volatile CAN4TXERRSTR _CAN4TXERR; /* MSCAN4 Transmit Error Counter Register */ +volatile CAN4TXIDR0STR _CAN4TXIDR0; /* MSCAN4 Transmit Identifier Register 0 */ +volatile CAN4TXIDR1STR _CAN4TXIDR1; /* MSCAN4 Transmit Identifier Register 1 */ +volatile CAN4TXIDR2STR _CAN4TXIDR2; /* MSCAN4 Transmit Identifier Register 2 */ +volatile CAN4TXIDR3STR _CAN4TXIDR3; /* MSCAN4 Transmit Identifier Register 3 */ +volatile CAN4TXTBPRSTR _CAN4TXTBPR; /* MSCAN4 Transmit Transmit Buffer Priority */ +volatile CFORCSTR _CFORC; /* Timer Compare Force Register */ +volatile CLKSELSTR _CLKSEL; /* CRG Clock Select Register */ +volatile COPCTLSTR _COPCTL; /* CRG COP Control Register */ +volatile CRGFLGSTR _CRGFLG; /* CRG Flags Register */ +volatile CRGINTSTR _CRGINT; /* CRG Interrupt Enable Register */ +volatile CTCTLSTR _CTCTL; /* CRG Test Control Register */ +volatile CTFLGSTR _CTFLG; /* CRG Test Flags Register */ +volatile DDRESTR _DDRE; /* Port E Data Direction Register */ +volatile DDRHSTR _DDRH; /* Port H Data Direction Register */ +volatile DDRJSTR _DDRJ; /* Port J Data Direction Register */ +volatile DDRKSTR _DDRK; /* Port K Data Direction Register */ +volatile DDRMSTR _DDRM; /* Port M Data Direction Register */ +volatile DDRPSTR _DDRP; /* Port P Data Direction Register */ +volatile DDRSSTR _DDRS; /* Port S Data Direction Register */ +volatile DDRTSTR _DDRT; /* Port T Data Direction Register */ +volatile DLCBARDSTR _DLCBARD; /* BDLC Analog Round Trip Delay Register */ +volatile DLCBCR1STR _DLCBCR1; /* BDLC Control Register 1 */ +volatile DLCBCR2STR _DLCBCR2; /* BDLC Control Register 2 */ +volatile DLCBDRSTR _DLCBDR; /* BDLC Data Register */ +volatile DLCBRSRSTR _DLCBRSR; /* BDLC Rate Select Register */ +volatile DLCBSVRSTR _DLCBSVR; /* BDLC State Vector Register */ +volatile DLCSCRSTR _DLCSCR; /* BDLC Control Register */ +volatile DLYCTSTR _DLYCT; /* Delay Counter Control Register */ +volatile EBICTLSTR _EBICTL; /* External Bus Interface Control */ +volatile ECLKDIVSTR _ECLKDIV; /* EEPROM Clock Divider Register */ +volatile ECMDSTR _ECMD; /* EEPROM Command Buffer and Register */ +volatile ECNFGSTR _ECNFG; /* EEPROM Configuration Register */ +volatile EPROTSTR _EPROT; /* EEPROM Protection Register */ +volatile ESTATSTR _ESTAT; /* EEPROM Status Register */ +volatile FCLKDIVSTR _FCLKDIV; /* Flash Clock Divider Register */ +volatile FCMDSTR _FCMD; /* Flash Command Buffer and Register */ +volatile FCNFGSTR _FCNFG; /* Flash Configuration Register */ +volatile FORBYPSTR _FORBYP; /* Crg force and bypass test register */ +volatile FPROTSTR _FPROT; /* Flash Protection Register */ +volatile FSECSTR _FSEC; /* Flash Security Register */ +volatile FSTATSTR _FSTAT; /* Flash Status Register */ +volatile HPRIOSTR _HPRIO; /* Highest Priority I Interrupt */ +volatile IBADSTR _IBAD; /* IIC Address Register */ +volatile IBCRSTR _IBCR; /* IIC Control Register */ +volatile IBDRSTR _IBDR; /* IIC Data I/O Register */ +volatile IBFDSTR _IBFD; /* IIC Frequency Divider Register */ +volatile IBSRSTR _IBSR; /* IIC Status Register */ +volatile ICOVWSTR _ICOVW; /* Input Control Overwrite Register */ +volatile ICPARSTR _ICPAR; /* Input Control Pulse Accumulator Register */ +volatile ICSYSSTR _ICSYS; /* Input Control System Control Register */ +volatile INITEESTR _INITEE; /* Initialization of Internal EEPROM Position Register */ +volatile INITRGSTR _INITRG; /* Initialization of Internal Register Position Register */ +volatile INITRMSTR _INITRM; /* Initialization of Internal RAM Position Register */ +volatile INTCRSTR _INTCR; /* Interrupt Control Register */ +volatile ITCRSTR _ITCR; /* Interrupt Test Control Register */ +volatile ITESTSTR _ITEST; /* Interrupt Test Register */ +volatile MCCTLSTR _MCCTL; /* Modulus Down Counter underflow */ +volatile MCFLGSTR _MCFLG; /* 16-Bit Modulus Down Counter Flag Register */ +volatile MEMSIZ0STR _MEMSIZ0; /* Memory Size Register Zero */ +volatile MEMSIZ1STR _MEMSIZ1; /* Memory Size Register One */ +volatile MISCSTR _MISC; /* Miscellaneous Mapping Control Register */ +volatile MODESTR _MODE; /* Mode Register */ +volatile MODRRSTR _MODRR; /* Module Routing Register */ +volatile MTST0STR _MTST0; /* MTST0 */ +volatile MTST1STR _MTST1; /* MTST1 */ +volatile OC7DSTR _OC7D; /* Output Compare 7 Data Register */ +volatile OC7MSTR _OC7M; /* Output Compare 7 Mask Register */ +volatile PACTLSTR _PACTL; /* 16-Bit Pulse Accumulator A Control Register */ +volatile PAFLGSTR _PAFLG; /* Pulse Accumulator A Flag Register */ +volatile PARTIDHSTR _PARTIDH; /* Part ID Register High */ +volatile PARTIDLSTR _PARTIDL; /* Part ID Register Low */ +volatile PBCTLSTR _PBCTL; /* 16-Bit Pulse Accumulator B Control Register */ +volatile PBFLGSTR _PBFLG; /* Pulse Accumulator B Flag Register */ +volatile PEARSTR _PEAR; /* Port E Assignment Register */ +volatile PERHSTR _PERH; /* Port H Pull Device Enable Register */ +volatile PERJSTR _PERJ; /* Port J Pull Device Enable Register */ +volatile PERMSTR _PERM; /* Port M Pull Device Enable Register */ +volatile PERPSTR _PERP; /* Port P Pull Device Enable Register */ +volatile PERSSTR _PERS; /* Port S Pull Device Enable Register */ +volatile PERTSTR _PERT; /* Port T Pull Device Enable Register */ +volatile PIEHSTR _PIEH; /* Port H Interrupt Enable Register */ +volatile PIEJSTR _PIEJ; /* Port J Interrupt Enable Register */ +volatile PIEPSTR _PIEP; /* Port P Interrupt Enable Register */ +volatile PIFHSTR _PIFH; /* Port H Interrupt Flag Register */ +volatile PIFJSTR _PIFJ; /* Port J Interrupt Flag Register */ +volatile PIFPSTR _PIFP; /* Port P Interrupt Flag Register */ +volatile PLLCTLSTR _PLLCTL; /* CRG PLL Control Register */ +volatile PORTAD0STR _PORTAD0; /* Port AD0 Register */ +volatile PORTAD1STR _PORTAD1; /* Port AD1 Register */ +volatile PORTESTR _PORTE; /* Port E Register */ +volatile PORTKSTR _PORTK; /* Port K Data Register */ +volatile PPAGESTR _PPAGE; /* Page Index Register */ +volatile PPSHSTR _PPSH; /* Port H Polarity Select Register */ +volatile PPSJSTR _PPSJ; /* PortJP Polarity Select Register */ +volatile PPSMSTR _PPSM; /* Port M Polarity Select Register */ +volatile PPSPSTR _PPSP; /* Port P Polarity Select Register */ +volatile PPSSSTR _PPSS; /* Port S Polarity Select Register */ +volatile PPSTSTR _PPST; /* Port T Polarity Select Register */ +volatile PTHSTR _PTH; /* Port H I/O Register */ +volatile PTIHSTR _PTIH; /* Port H Input Register */ +volatile PTIJSTR _PTIJ; /* Port J Input Register */ +volatile PTIMSTR _PTIM; /* Port M Input */ +volatile PTIPSTR _PTIP; /* Port P Input */ +volatile PTISSTR _PTIS; /* Port S Input */ +volatile PTITSTR _PTIT; /* Port T Input */ +volatile PTJSTR _PTJ; /* Port J I/O Register */ +volatile PTMSTR _PTM; /* Port M I/O Register */ +volatile PTPSTR _PTP; /* Port P I/O Register */ +volatile PTSSTR _PTS; /* Port S I/O Register */ +volatile PTTSTR _PTT; /* Port T I/O Register */ +volatile PUCRSTR _PUCR; /* Pull-Up Control Register */ +volatile PWMCAESTR _PWMCAE; /* PWM Center Align Enable Register */ +volatile PWMCLKSTR _PWMCLK; /* PWM Clock Select Register */ +volatile PWMCTLSTR _PWMCTL; /* PWM Control Register */ +volatile PWMESTR _PWME; /* PWM Enable Register */ +volatile PWMPOLSTR _PWMPOL; /* PWM Polarity Register */ +volatile PWMPRCLKSTR _PWMPRCLK; /* PWM Prescale Clock Select Register */ +volatile PWMSCLASTR _PWMSCLA; /* PWM Scale A Register */ +volatile PWMSCLBSTR _PWMSCLB; /* PWM Scale B Register */ +volatile PWMSDNSTR _PWMSDN; /* PWM Shutdown Register */ +volatile RDRHSTR _RDRH; /* Port H Reduced Drive Register */ +volatile RDRIVSTR _RDRIV; /* Reduced Drive of I/O Lines */ +volatile RDRJSTR _RDRJ; /* Port J Reduced Drive Register */ +volatile RDRMSTR _RDRM; /* Port M Reduced Drive Register */ +volatile RDRPSTR _RDRP; /* Port P Reduced Drive Register */ +volatile RDRSSTR _RDRS; /* Port S Reduced Drive Register */ +volatile RDRTSTR _RDRT; /* Port T Reduced Drive Register */ +volatile REFDVSTR _REFDV; /* CRG Reference Divider Register */ +volatile RTICTLSTR _RTICTL; /* CRG RTI Control Register */ +volatile SCI0CR1STR _SCI0CR1; /* SCI 0 Control Register 1 */ +volatile SCI0CR2STR _SCI0CR2; /* SCI 0 Control Register 2 */ +volatile SCI0DRHSTR _SCI0DRH; /* SCI 0 Data Register High */ +volatile SCI0DRLSTR _SCI0DRL; /* SCI 0 Data Register Low */ +volatile SCI0SR1STR _SCI0SR1; /* SCI 0 Status Register 1 */ +volatile SCI0SR2STR _SCI0SR2; /* SCI 0 Status Register 2 */ +volatile SCI1CR1STR _SCI1CR1; /* SCI 1 Control Register 1 */ +volatile SCI1CR2STR _SCI1CR2; /* SCI 1 Control Register 2 */ +volatile SCI1DRHSTR _SCI1DRH; /* SCI 1 Data Register High */ +volatile SCI1DRLSTR _SCI1DRL; /* SCI 1 Data Register Low */ +volatile SCI1SR1STR _SCI1SR1; /* SCI 1 Status Register 1 */ +volatile SCI1SR2STR _SCI1SR2; /* SCI 1 Status Register 2 */ +volatile SPI0BRSTR _SPI0BR; /* SPI 0 Baud Rate Register */ +volatile SPI0CR1STR _SPI0CR1; /* SPI 0 Control Register */ +volatile SPI0CR2STR _SPI0CR2; /* SPI 0 Control Register 2 */ +volatile SPI0DRSTR _SPI0DR; /* SPI 0 Data Register */ +volatile SPI0SRSTR _SPI0SR; /* SPI 0 Status Register */ +volatile SPI1BRSTR _SPI1BR; /* SPI 1 Baud Rate Register */ +volatile SPI1CR1STR _SPI1CR1; /* SPI 1 Control Register */ +volatile SPI1CR2STR _SPI1CR2; /* SPI 1 Control Register 2 */ +volatile SPI1DRSTR _SPI1DR; /* SPI 1 Data Register */ +volatile SPI1SRSTR _SPI1SR; /* SPI 1 Status Register */ +volatile SPI2BRSTR _SPI2BR; /* SPI 2 Baud Rate Register */ +volatile SPI2CR1STR _SPI2CR1; /* SPI 2 Control Register */ +volatile SPI2CR2STR _SPI2CR2; /* SPI 2 Control Register 2 */ +volatile SPI2DRSTR _SPI2DR; /* SPI 2 Data Register */ +volatile SPI2SRSTR _SPI2SR; /* SPI 2 Status Register */ +volatile SYNRSTR _SYNR; /* CRG Synthesizer Register */ +volatile TCTL1STR _TCTL1; /* Timer Control Registers 1 */ +volatile TCTL2STR _TCTL2; /* Timer Control Registers 2 */ +volatile TCTL3STR _TCTL3; /* Timer Control Register 3 */ +volatile TCTL4STR _TCTL4; /* Timer Control Register 4 */ +volatile TFLG1STR _TFLG1; /* Main Timer Interrupt Flag 1 */ +volatile TFLG2STR _TFLG2; /* Main Timer Interrupt Flag 2 */ +volatile TIESTR _TIE; /* Timer Interrupt Enable Register */ +volatile TIMTSTSTR _TIMTST; /* Timer Test Register */ +volatile TIOSSTR _TIOS; /* Timer Input Capture/Output Compare Select */ +volatile TSCR1STR _TSCR1; /* Timer System Control Register1 */ +volatile TSCR2STR _TSCR2; /* Timer System Control Register 2 */ +volatile TTOVSTR _TTOV; /* Timer Toggle On Overflow Register */ +volatile WOMMSTR _WOMM; /* Port M Wired-Or Mode Register */ +volatile WOMSSTR _WOMS; /* Port S Wired-Or Mode Register */ +volatile ATD0CTL23STR _ATD0CTL23; /* ATD 0 Control Register 23 */ +volatile ATD0CTL45STR _ATD0CTL45; /* ATD 0 Control Register 45 */ +volatile ATD0DR0STR _ATD0DR0; /* ATD 0 Conversion Result Register 0 */ +volatile ATD0DR1STR _ATD0DR1; /* ATD 0 Conversion Result Register 1 */ +volatile ATD0DR2STR _ATD0DR2; /* ATD 0 Conversion Result Register 2 */ +volatile ATD0DR3STR _ATD0DR3; /* ATD 0 Conversion Result Register 3 */ +volatile ATD0DR4STR _ATD0DR4; /* ATD 0 Conversion Result Register 4 */ +volatile ATD0DR5STR _ATD0DR5; /* ATD 0 Conversion Result Register 5 */ +volatile ATD0DR6STR _ATD0DR6; /* ATD 0 Conversion Result Register 6 */ +volatile ATD0DR7STR _ATD0DR7; /* ATD 0 Conversion Result Register 7 */ +volatile ATD1CTL23STR _ATD1CTL23; /* ATD 1 Control Register 23 */ +volatile ATD1CTL45STR _ATD1CTL45; /* ATD 1 Control Register 45 */ +volatile ATD1DR0STR _ATD1DR0; /* ATD 1 Conversion Result Register 0 */ +volatile ATD1DR1STR _ATD1DR1; /* ATD 1 Conversion Result Register 1 */ +volatile ATD1DR2STR _ATD1DR2; /* ATD 1 Conversion Result Register 2 */ +volatile ATD1DR3STR _ATD1DR3; /* ATD 1 Conversion Result Register 3 */ +volatile ATD1DR4STR _ATD1DR4; /* ATD 1 Conversion Result Register 4 */ +volatile ATD1DR5STR _ATD1DR5; /* ATD 1 Conversion Result Register 5 */ +volatile ATD1DR6STR _ATD1DR6; /* ATD 1 Conversion Result Register 6 */ +volatile ATD1DR7STR _ATD1DR7; /* ATD 1 Conversion Result Register 7 */ +volatile DDRABSTR _DDRAB; /* Port AB Data Direction Register */ +volatile MCCNTSTR _MCCNT; /* Modulus Down-Counter Count Register */ +volatile PA10HSTR _PA10H; /* 8-Bit Pulse Accumulators Holding 10 Register */ +volatile PA32HSTR _PA32H; /* 8-Bit Pulse Accumulators Holding 32 Register */ +volatile PACN10STR _PACN10; /* Pulse Accumulators Count 10 Register */ +volatile PACN32STR _PACN32; /* Pulse Accumulators Count 32 Register */ +volatile PORTABSTR _PORTAB; /* Port AB Register */ +volatile PWMCNT01STR _PWMCNT01; /* PWM Channel Counter 01 Register */ +volatile PWMCNT23STR _PWMCNT23; /* PWM Channel Counter 23 Register */ +volatile PWMCNT45STR _PWMCNT45; /* PWM Channel Counter 45 Register */ +volatile PWMCNT67STR _PWMCNT67; /* PWM Channel Counter 67 Register */ +volatile PWMDTY01STR _PWMDTY01; /* PWM Channel Duty 01 Register */ +volatile PWMDTY23STR _PWMDTY23; /* PWM Channel Duty 23 Register */ +volatile PWMDTY45STR _PWMDTY45; /* PWM Channel Duty 45 Register */ +volatile PWMDTY67STR _PWMDTY67; /* PWM Channel Duty 67 Register */ +volatile PWMPER01STR _PWMPER01; /* PWM Channel Period 01 Register */ +volatile PWMPER23STR _PWMPER23; /* PWM Channel Period 23 Register */ +volatile PWMPER45STR _PWMPER45; /* PWM Channel Period 45 Register */ +volatile PWMPER67STR _PWMPER67; /* PWM Channel Period 67 Register */ +volatile SCI0BDSTR _SCI0BD; /* SCI 0 Baud Rate Register */ +volatile SCI1BDSTR _SCI1BD; /* SCI 1 Baud Rate Register */ +volatile TC0STR _TC0; /* Timer Input Capture/Output Compare Register 0 */ +volatile TC0HSTR _TC0H; /* Timer Input Capture Holding Registers 0 */ +volatile TC1STR _TC1; /* Timer Input Capture/Output Compare Register 1 */ +volatile TC1HSTR _TC1H; /* Timer Input Capture Holding Registers 1 */ +volatile TC2STR _TC2; /* Timer Input Capture/Output Compare Register 2 */ +volatile TC2HSTR _TC2H; /* Timer Input Capture Holding Registers 2 */ +volatile TC3STR _TC3; /* Timer Input Capture/Output Compare Register 3 */ +volatile TC3HSTR _TC3H; /* Timer Input Capture Holding Registers 3 */ +volatile TC4STR _TC4; /* Timer Input Capture/Output Compare Register 4 */ +volatile TC5STR _TC5; /* Timer Input Capture/Output Compare Register 5 */ +volatile TC6STR _TC6; /* Timer Input Capture/Output Compare Register 6 */ +volatile TC7STR _TC7; /* Timer Input Capture/Output Compare Register 7 */ +volatile TCNTSTR _TCNT; /* Timer Count Register */ +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/20080212/Demo/HCS12_CodeWarrior_banked/CODE/IO_Map.H b/20080212/Demo/HCS12_CodeWarrior_banked/CODE/IO_Map.H new file mode 100644 index 000000000..678b0b350 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_banked/CODE/IO_Map.H @@ -0,0 +1,18408 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : IO_Map.H +** Project : RTOSDemo +** Processor : MC9S12DP256BCPV +** Beantype : IO_Map +** Version : Driver 01.01 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 13/06/2005, 20:14 +** Abstract : +** This bean "IO_Map" implements an IO devices mapping. +** Settings : +** +** Contents : +** No public methods +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + +/* Linker pragmas */ +#pragma LINK_INFO DERIVATIVE "MC9S12DP256B" +#pragma LINK_INFO OSCFREQUENCY "16000000" + + +#define REG_BASE 0x0000 /* Base address for the I/O register block */ + +/* Based on CPU DB MC9S12DP256_112, version 2.87.278 (RegistersPrg V1.027) */ +#ifndef _MC9S12DP256_112_H +#define _MC9S12DP256_112_H + +#include "PE_Types.h" + +#pragma MESSAGE DISABLE C1106 /* WARNING C1106: Non-standard bitfield type */ + +/*********************************************/ +/* */ +/* PE I/O map format */ +/* */ +/*********************************************/ + +/*** PORTAB - Port AB Register; 0x00000000 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PORTA - Port A Register; 0x00000000 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Port A Bit0, ADDR8, DATA8, DATA0 */ + byte BIT1 :1; /* Port A Bit1, ADDR9, DATA9 DATA1 */ + byte BIT2 :1; /* Port A Bit2, ADDR10, DATA10, DATA2 */ + byte BIT3 :1; /* Port A Bit3, ADDR11, DATA11, DATA3 */ + byte BIT4 :1; /* Port A Bit4, ADDR12, DATA12, DATA4 */ + byte BIT5 :1; /* Port A Bit5, ADDR13, DATA13, DATA5 */ + byte BIT6 :1; /* Port A Bit6, ADDR14, DATA14, DATA6 */ + byte BIT7 :1; /* Port A Bit7, ADDR15, DATA15, DATA7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } PORTASTR; + #define PORTA _PORTAB.Overlap_STR.PORTASTR.Byte + #define PORTA_BIT0 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT0 + #define PORTA_BIT1 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT1 + #define PORTA_BIT2 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT2 + #define PORTA_BIT3 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT3 + #define PORTA_BIT4 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT4 + #define PORTA_BIT5 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT5 + #define PORTA_BIT6 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT6 + #define PORTA_BIT7 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT7 + #define PORTA_BIT _PORTAB.Overlap_STR.PORTASTR.MergedBits.grpBIT + + /*** PORTB - Port B Register; 0x00000001 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Port B Bit 0, ADDR0, DATA0 */ + byte BIT1 :1; /* Port B Bit1, ADDR1, DATA1 */ + byte BIT2 :1; /* Port B Bit2, ADDR2, DATA2 */ + byte BIT3 :1; /* Port B Bit3, ADDR3, DATA3 */ + byte BIT4 :1; /* Port B Bit4, ADDR4, DATA4 */ + byte BIT5 :1; /* Port B Bit5, ADDR5, DATA5 */ + byte BIT6 :1; /* Port B Bit6, ADDR6, DATA6 */ + byte BIT7 :1; /* Port B Bit7, ADDR7, DATA7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } PORTBSTR; + #define PORTB _PORTAB.Overlap_STR.PORTBSTR.Byte + #define PORTB_BIT0 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT0 + #define PORTB_BIT1 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT1 + #define PORTB_BIT2 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT2 + #define PORTB_BIT3 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT3 + #define PORTB_BIT4 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT4 + #define PORTB_BIT5 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT5 + #define PORTB_BIT6 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT6 + #define PORTB_BIT7 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT7 + #define PORTB_BIT _PORTAB.Overlap_STR.PORTBSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word BIT0 :1; /* Port B Bit 0, ADDR0, DATA0 */ + word BIT1 :1; /* Port B Bit1, ADDR1, DATA1 */ + word BIT2 :1; /* Port B Bit2, ADDR2, DATA2 */ + word BIT3 :1; /* Port B Bit3, ADDR3, DATA3 */ + word BIT4 :1; /* Port B Bit4, ADDR4, DATA4 */ + word BIT5 :1; /* Port B Bit5, ADDR5, DATA5 */ + word BIT6 :1; /* Port B Bit6, ADDR6, DATA6 */ + word BIT7 :1; /* Port B Bit7, ADDR7, DATA7 */ + word BIT8 :1; /* Port A Bit0, ADDR8, DATA8, DATA0 */ + word BIT9 :1; /* Port A Bit1, ADDR9, DATA9 DATA1 */ + word BIT10 :1; /* Port A Bit2, ADDR10, DATA10, DATA2 */ + word BIT11 :1; /* Port A Bit3, ADDR11, DATA11, DATA3 */ + word BIT12 :1; /* Port A Bit4, ADDR12, DATA12, DATA4 */ + word BIT13 :1; /* Port A Bit5, ADDR13, DATA13, DATA5 */ + word BIT14 :1; /* Port A Bit6, ADDR14, DATA14, DATA6 */ + word BIT15 :1; /* Port A Bit7, ADDR15, DATA15, DATA7 */ + } Bits; + struct { + word grpBIT :16; + } MergedBits; +} PORTABSTR; +extern volatile PORTABSTR _PORTAB @(REG_BASE + 0x00000000); +#define PORTAB _PORTAB.Word +#define PORTAB_BIT0 _PORTAB.Bits.BIT0 +#define PORTAB_BIT1 _PORTAB.Bits.BIT1 +#define PORTAB_BIT2 _PORTAB.Bits.BIT2 +#define PORTAB_BIT3 _PORTAB.Bits.BIT3 +#define PORTAB_BIT4 _PORTAB.Bits.BIT4 +#define PORTAB_BIT5 _PORTAB.Bits.BIT5 +#define PORTAB_BIT6 _PORTAB.Bits.BIT6 +#define PORTAB_BIT7 _PORTAB.Bits.BIT7 +#define PORTAB_BIT8 _PORTAB.Bits.BIT8 +#define PORTAB_BIT9 _PORTAB.Bits.BIT9 +#define PORTAB_BIT10 _PORTAB.Bits.BIT10 +#define PORTAB_BIT11 _PORTAB.Bits.BIT11 +#define PORTAB_BIT12 _PORTAB.Bits.BIT12 +#define PORTAB_BIT13 _PORTAB.Bits.BIT13 +#define PORTAB_BIT14 _PORTAB.Bits.BIT14 +#define PORTAB_BIT15 _PORTAB.Bits.BIT15 +#define PORTAB_BIT _PORTAB.MergedBits.grpBIT + + +/*** DDRAB - Port AB Data Direction Register; 0x00000002 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** DDRA - Port A Data Direction Register; 0x00000002 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Data Direction Port A Bit 0 */ + byte BIT1 :1; /* Data Direction Port A Bit 1 */ + byte BIT2 :1; /* Data Direction Port A Bit 2 */ + byte BIT3 :1; /* Data Direction Port A Bit 3 */ + byte BIT4 :1; /* Data Direction Port A Bit 4 */ + byte BIT5 :1; /* Data Direction Port A Bit 5 */ + byte BIT6 :1; /* Data Direction Port A Bit 6 */ + byte BIT7 :1; /* Data Direction Port A Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } DDRASTR; + #define DDRA _DDRAB.Overlap_STR.DDRASTR.Byte + #define DDRA_BIT0 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT0 + #define DDRA_BIT1 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT1 + #define DDRA_BIT2 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT2 + #define DDRA_BIT3 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT3 + #define DDRA_BIT4 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT4 + #define DDRA_BIT5 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT5 + #define DDRA_BIT6 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT6 + #define DDRA_BIT7 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT7 + #define DDRA_BIT _DDRAB.Overlap_STR.DDRASTR.MergedBits.grpBIT + + /*** DDRB - Port B Data Direction Register; 0x00000003 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Data Direction Port B Bit 0 */ + byte BIT1 :1; /* Data Direction Port B Bit 1 */ + byte BIT2 :1; /* Data Direction Port B Bit 2 */ + byte BIT3 :1; /* Data Direction Port B Bit 3 */ + byte BIT4 :1; /* Data Direction Port B Bit 4 */ + byte BIT5 :1; /* Data Direction Port B Bit 5 */ + byte BIT6 :1; /* Data Direction Port B Bit 6 */ + byte BIT7 :1; /* Data Direction Port B Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } DDRBSTR; + #define DDRB _DDRAB.Overlap_STR.DDRBSTR.Byte + #define DDRB_BIT0 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT0 + #define DDRB_BIT1 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT1 + #define DDRB_BIT2 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT2 + #define DDRB_BIT3 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT3 + #define DDRB_BIT4 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT4 + #define DDRB_BIT5 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT5 + #define DDRB_BIT6 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT6 + #define DDRB_BIT7 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT7 + #define DDRB_BIT _DDRAB.Overlap_STR.DDRBSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word BIT0 :1; /* Data Direction Port B Bit 0 */ + word BIT1 :1; /* Data Direction Port B Bit 1 */ + word BIT2 :1; /* Data Direction Port B Bit 2 */ + word BIT3 :1; /* Data Direction Port B Bit 3 */ + word BIT4 :1; /* Data Direction Port B Bit 4 */ + word BIT5 :1; /* Data Direction Port B Bit 5 */ + word BIT6 :1; /* Data Direction Port B Bit 6 */ + word BIT7 :1; /* Data Direction Port B Bit 7 */ + word BIT8 :1; /* Data Direction Port A Bit 8 */ + word BIT9 :1; /* Data Direction Port A Bit 9 */ + word BIT10 :1; /* Data Direction Port A Bit 10 */ + word BIT11 :1; /* Data Direction Port A Bit 11 */ + word BIT12 :1; /* Data Direction Port A Bit 12 */ + word BIT13 :1; /* Data Direction Port A Bit 13 */ + word BIT14 :1; /* Data Direction Port A Bit 14 */ + word BIT15 :1; /* Data Direction Port A Bit 15 */ + } Bits; + struct { + word grpBIT :16; + } MergedBits; +} DDRABSTR; +extern volatile DDRABSTR _DDRAB @(REG_BASE + 0x00000002); +#define DDRAB _DDRAB.Word +#define DDRAB_BIT0 _DDRAB.Bits.BIT0 +#define DDRAB_BIT1 _DDRAB.Bits.BIT1 +#define DDRAB_BIT2 _DDRAB.Bits.BIT2 +#define DDRAB_BIT3 _DDRAB.Bits.BIT3 +#define DDRAB_BIT4 _DDRAB.Bits.BIT4 +#define DDRAB_BIT5 _DDRAB.Bits.BIT5 +#define DDRAB_BIT6 _DDRAB.Bits.BIT6 +#define DDRAB_BIT7 _DDRAB.Bits.BIT7 +#define DDRAB_BIT8 _DDRAB.Bits.BIT8 +#define DDRAB_BIT9 _DDRAB.Bits.BIT9 +#define DDRAB_BIT10 _DDRAB.Bits.BIT10 +#define DDRAB_BIT11 _DDRAB.Bits.BIT11 +#define DDRAB_BIT12 _DDRAB.Bits.BIT12 +#define DDRAB_BIT13 _DDRAB.Bits.BIT13 +#define DDRAB_BIT14 _DDRAB.Bits.BIT14 +#define DDRAB_BIT15 _DDRAB.Bits.BIT15 +#define DDRAB_BIT _DDRAB.MergedBits.grpBIT + + +/*** TCNT - Timer Count Register; 0x00000044 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TCNTHi - Timer Count Register High; 0x00000044 ***/ + union { + byte Byte; + struct { + byte BIT15 :1; /* Timer Count Register Bit 15 */ + byte BIT14 :1; /* Timer Count Register Bit 14 */ + byte BIT13 :1; /* Timer Count Register Bit 13 */ + byte BIT12 :1; /* Timer Count Register Bit 12 */ + byte BIT11 :1; /* Timer Count Register Bit 11 */ + byte BIT10 :1; /* Timer Count Register Bit 10 */ + byte BIT9 :1; /* Timer Count Register Bit 9 */ + byte BIT8 :1; /* Timer Count Register Bit 8 */ + } Bits; + } TCNTHiSTR; + #define TCNTHi _TCNT.Overlap_STR.TCNTHiSTR.Byte + #define TCNTHi_BIT15 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT15 + #define TCNTHi_BIT14 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT14 + #define TCNTHi_BIT13 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT13 + #define TCNTHi_BIT12 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT12 + #define TCNTHi_BIT11 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT11 + #define TCNTHi_BIT10 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT10 + #define TCNTHi_BIT9 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT9 + #define TCNTHi_BIT8 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT8 + + /*** TCNTLo - Timer Count Register Low; 0x00000045 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Count Register Bit 0 */ + byte BIT1 :1; /* Timer Count Register Bit 1 */ + byte BIT2 :1; /* Timer Count Register Bit 2 */ + byte BIT3 :1; /* Timer Count Register Bit 3 */ + byte BIT4 :1; /* Timer Count Bit Register 4 */ + byte BIT5 :1; /* Timer Count Bit Register 5 */ + byte BIT6 :1; /* Timer Count Bit Register 6 */ + byte BIT7 :1; /* Timer Count Bit Register 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } TCNTLoSTR; + #define TCNTLo _TCNT.Overlap_STR.TCNTLoSTR.Byte + #define TCNTLo_BIT0 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT0 + #define TCNTLo_BIT1 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT1 + #define TCNTLo_BIT2 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT2 + #define TCNTLo_BIT3 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT3 + #define TCNTLo_BIT4 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT4 + #define TCNTLo_BIT5 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT5 + #define TCNTLo_BIT6 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT6 + #define TCNTLo_BIT7 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT7 + #define TCNTLo_BIT _TCNT.Overlap_STR.TCNTLoSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} TCNTSTR; +extern volatile TCNTSTR _TCNT @(REG_BASE + 0x00000044); +#define TCNT _TCNT.Word +#define TCNT_BIT _TCNT.MergedBits.grpBIT + + +/*** TC0 - Timer Input Capture/Output Compare Register 0; 0x00000050 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC0Hi - Timer Input Capture/Output Compare Register 0 High; 0x00000050 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Timer Input Capture/Output Compare Register 0 Bit 8 */ + byte BIT9 :1; /* Timer Input Capture/Output Compare Register 0 Bit 9 */ + byte BIT10 :1; /* Timer Input Capture/Output Compare Register 0 Bit 10 */ + byte BIT11 :1; /* Timer Input Capture/Output Compare Register 0 Bit 11 */ + byte BIT12 :1; /* Timer Input Capture/Output Compare Register 0 Bit 12 */ + byte BIT13 :1; /* Timer Input Capture/Output Compare Register 0 Bit 13 */ + byte BIT14 :1; /* Timer Input Capture/Output Compare Register 0 Bit 14 */ + byte BIT15 :1; /* Timer Input Capture/Output Compare Register 0 Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } TC0HiSTR; + #define TC0Hi _TC0.Overlap_STR.TC0HiSTR.Byte + #define TC0Hi_BIT8 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT8 + #define TC0Hi_BIT9 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT9 + #define TC0Hi_BIT10 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT10 + #define TC0Hi_BIT11 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT11 + #define TC0Hi_BIT12 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT12 + #define TC0Hi_BIT13 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT13 + #define TC0Hi_BIT14 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT14 + #define TC0Hi_BIT15 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT15 + #define TC0Hi_BIT_8 _TC0.Overlap_STR.TC0HiSTR.MergedBits.grpBIT_8 + #define TC0Hi_BIT TC0Hi_BIT_8 + + /*** TC0Lo - Timer Input Capture/Output Compare Register 0 Low; 0x00000051 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Input Capture/Output Compare Register 0 Bit 0 */ + byte BIT1 :1; /* Timer Input Capture/Output Compare Register 0 Bit 1 */ + byte BIT2 :1; /* Timer Input Capture/Output Compare Register 0 Bit 2 */ + byte BIT3 :1; /* Timer Input Capture/Output Compare Register 0 Bit 3 */ + byte BIT4 :1; /* Timer Input Capture/Output Compare Register 0 Bit 4 */ + byte BIT5 :1; /* Timer Input Capture/Output Compare Register 0 Bit 5 */ + byte BIT6 :1; /* Timer Input Capture/Output Compare Register 0 Bit 6 */ + byte BIT7 :1; /* Timer Input Capture/Output Compare Register 0 Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } TC0LoSTR; + #define TC0Lo _TC0.Overlap_STR.TC0LoSTR.Byte + #define TC0Lo_BIT0 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT0 + #define TC0Lo_BIT1 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT1 + #define TC0Lo_BIT2 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT2 + #define TC0Lo_BIT3 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT3 + #define TC0Lo_BIT4 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT4 + #define TC0Lo_BIT5 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT5 + #define TC0Lo_BIT6 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT6 + #define TC0Lo_BIT7 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT7 + #define TC0Lo_BIT _TC0.Overlap_STR.TC0LoSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} TC0STR; +extern volatile TC0STR _TC0 @(REG_BASE + 0x00000050); +#define TC0 _TC0.Word +#define TC0_BIT _TC0.MergedBits.grpBIT + + +/*** TC1 - Timer Input Capture/Output Compare Register 1; 0x00000052 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC1Hi - Timer Input Capture/Output Compare Register 1 High; 0x00000052 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Timer Input Capture/Output Compare Register 1 Bit 8 */ + byte BIT9 :1; /* Timer Input Capture/Output Compare Register 1 Bit 9 */ + byte BIT10 :1; /* Timer Input Capture/Output Compare Register 1 Bit 10 */ + byte BIT11 :1; /* Timer Input Capture/Output Compare Register 1 Bit 11 */ + byte BIT12 :1; /* Timer Input Capture/Output Compare Register 1 Bit 12 */ + byte BIT13 :1; /* Timer Input Capture/Output Compare Register 1 Bit 13 */ + byte BIT14 :1; /* Timer Input Capture/Output Compare Register 1 Bit 14 */ + byte BIT15 :1; /* Timer Input Capture/Output Compare Register 1 Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } TC1HiSTR; + #define TC1Hi _TC1.Overlap_STR.TC1HiSTR.Byte + #define TC1Hi_BIT8 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT8 + #define TC1Hi_BIT9 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT9 + #define TC1Hi_BIT10 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT10 + #define TC1Hi_BIT11 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT11 + #define TC1Hi_BIT12 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT12 + #define TC1Hi_BIT13 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT13 + #define TC1Hi_BIT14 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT14 + #define TC1Hi_BIT15 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT15 + #define TC1Hi_BIT_8 _TC1.Overlap_STR.TC1HiSTR.MergedBits.grpBIT_8 + #define TC1Hi_BIT TC1Hi_BIT_8 + + /*** TC1Lo - Timer Input Capture/Output Compare Register 1 Low; 0x00000053 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Input Capture/Output Compare Register 1 Bit 0 */ + byte BIT1 :1; /* Timer Input Capture/Output Compare Register 1 Bit 1 */ + byte BIT2 :1; /* Timer Input Capture/Output Compare Register 1 Bit 2 */ + byte BIT3 :1; /* Timer Input Capture/Output Compare Register 1 Bit 3 */ + byte BIT4 :1; /* Timer Input Capture/Output Compare Register 1 Bit 4 */ + byte BIT5 :1; /* Timer Input Capture/Output Compare Register 1 Bit 5 */ + byte BIT6 :1; /* Timer Input Capture/Output Compare Register 1 Bit 6 */ + byte BIT7 :1; /* Timer Input Capture/Output Compare Register 1 Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } TC1LoSTR; + #define TC1Lo _TC1.Overlap_STR.TC1LoSTR.Byte + #define TC1Lo_BIT0 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT0 + #define TC1Lo_BIT1 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT1 + #define TC1Lo_BIT2 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT2 + #define TC1Lo_BIT3 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT3 + #define TC1Lo_BIT4 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT4 + #define TC1Lo_BIT5 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT5 + #define TC1Lo_BIT6 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT6 + #define TC1Lo_BIT7 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT7 + #define TC1Lo_BIT _TC1.Overlap_STR.TC1LoSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} TC1STR; +extern volatile TC1STR _TC1 @(REG_BASE + 0x00000052); +#define TC1 _TC1.Word +#define TC1_BIT _TC1.MergedBits.grpBIT + + +/*** TC2 - Timer Input Capture/Output Compare Register 2; 0x00000054 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC2Hi - Timer Input Capture/Output Compare Register 2 High; 0x00000054 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Timer Input Capture/Output Compare Register 2 Bit 8 */ + byte BIT9 :1; /* Timer Input Capture/Output Compare Register 2 Bit 9 */ + byte BIT10 :1; /* Timer Input Capture/Output Compare Register 2 Bit 10 */ + byte BIT11 :1; /* Timer Input Capture/Output Compare Register 2 Bit 11 */ + byte BIT12 :1; /* Timer Input Capture/Output Compare Register 2 Bit 12 */ + byte BIT13 :1; /* Timer Input Capture/Output Compare Register 2 Bit 13 */ + byte BIT14 :1; /* Timer Input Capture/Output Compare Register 2 Bit 14 */ + byte BIT15 :1; /* Timer Input Capture/Output Compare Register 2 Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } TC2HiSTR; + #define TC2Hi _TC2.Overlap_STR.TC2HiSTR.Byte + #define TC2Hi_BIT8 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT8 + #define TC2Hi_BIT9 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT9 + #define TC2Hi_BIT10 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT10 + #define TC2Hi_BIT11 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT11 + #define TC2Hi_BIT12 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT12 + #define TC2Hi_BIT13 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT13 + #define TC2Hi_BIT14 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT14 + #define TC2Hi_BIT15 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT15 + #define TC2Hi_BIT_8 _TC2.Overlap_STR.TC2HiSTR.MergedBits.grpBIT_8 + #define TC2Hi_BIT TC2Hi_BIT_8 + + /*** TC2Lo - Timer Input Capture/Output Compare Register 2 Low; 0x00000055 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Input Capture/Output Compare Register 2 Bit 0 */ + byte BIT1 :1; /* Timer Input Capture/Output Compare Register 2 Bit 1 */ + byte BIT2 :1; /* Timer Input Capture/Output Compare Register 2 Bit 2 */ + byte BIT3 :1; /* Timer Input Capture/Output Compare Register 2 Bit 3 */ + byte BIT4 :1; /* Timer Input Capture/Output Compare Register 2 Bit 4 */ + byte BIT5 :1; /* Timer Input Capture/Output Compare Register 2 Bit 5 */ + byte BIT6 :1; /* Timer Input Capture/Output Compare Register 2 Bit 6 */ + byte BIT7 :1; /* Timer Input Capture/Output Compare Register 2 Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } TC2LoSTR; + #define TC2Lo _TC2.Overlap_STR.TC2LoSTR.Byte + #define TC2Lo_BIT0 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT0 + #define TC2Lo_BIT1 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT1 + #define TC2Lo_BIT2 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT2 + #define TC2Lo_BIT3 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT3 + #define TC2Lo_BIT4 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT4 + #define TC2Lo_BIT5 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT5 + #define TC2Lo_BIT6 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT6 + #define TC2Lo_BIT7 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT7 + #define TC2Lo_BIT _TC2.Overlap_STR.TC2LoSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} TC2STR; +extern volatile TC2STR _TC2 @(REG_BASE + 0x00000054); +#define TC2 _TC2.Word +#define TC2_BIT _TC2.MergedBits.grpBIT + + +/*** TC3 - Timer Input Capture/Output Compare Register 3; 0x00000056 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC3Hi - Timer Input Capture/Output Compare Register 3 High; 0x00000056 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Timer Input Capture/Output Compare Register 3 Bit 8 */ + byte BIT9 :1; /* Timer Input Capture/Output Compare Register 3 Bit 9 */ + byte BIT10 :1; /* Timer Input Capture/Output Compare Register 3 Bit 10 */ + byte BIT11 :1; /* Timer Input Capture/Output Compare Register 3 Bit 11 */ + byte BIT12 :1; /* Timer Input Capture/Output Compare Register 3 Bit 12 */ + byte BIT13 :1; /* Timer Input Capture/Output Compare Register 3 Bit 13 */ + byte BIT14 :1; /* Timer Input Capture/Output Compare Register 3 Bit 14 */ + byte BIT15 :1; /* Timer Input Capture/Output Compare Register 3 Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } TC3HiSTR; + #define TC3Hi _TC3.Overlap_STR.TC3HiSTR.Byte + #define TC3Hi_BIT8 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT8 + #define TC3Hi_BIT9 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT9 + #define TC3Hi_BIT10 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT10 + #define TC3Hi_BIT11 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT11 + #define TC3Hi_BIT12 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT12 + #define TC3Hi_BIT13 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT13 + #define TC3Hi_BIT14 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT14 + #define TC3Hi_BIT15 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT15 + #define TC3Hi_BIT_8 _TC3.Overlap_STR.TC3HiSTR.MergedBits.grpBIT_8 + #define TC3Hi_BIT TC3Hi_BIT_8 + + /*** TC3Lo - Timer Input Capture/Output Compare Register 3 Low; 0x00000057 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Input Capture/Output Compare Register 3 Bit 0 */ + byte BIT1 :1; /* Timer Input Capture/Output Compare Register 3 Bit 1 */ + byte BIT2 :1; /* Timer Input Capture/Output Compare Register 3 Bit 2 */ + byte BIT3 :1; /* Timer Input Capture/Output Compare Register 3 Bit 3 */ + byte BIT4 :1; /* Timer Input Capture/Output Compare Register 3 Bit 4 */ + byte BIT5 :1; /* Timer Input Capture/Output Compare Register 3 Bit 5 */ + byte BIT6 :1; /* Timer Input Capture/Output Compare Register 3 Bit 6 */ + byte BIT7 :1; /* Timer Input Capture/Output Compare Register 3 Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } TC3LoSTR; + #define TC3Lo _TC3.Overlap_STR.TC3LoSTR.Byte + #define TC3Lo_BIT0 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT0 + #define TC3Lo_BIT1 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT1 + #define TC3Lo_BIT2 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT2 + #define TC3Lo_BIT3 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT3 + #define TC3Lo_BIT4 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT4 + #define TC3Lo_BIT5 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT5 + #define TC3Lo_BIT6 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT6 + #define TC3Lo_BIT7 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT7 + #define TC3Lo_BIT _TC3.Overlap_STR.TC3LoSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} TC3STR; +extern volatile TC3STR _TC3 @(REG_BASE + 0x00000056); +#define TC3 _TC3.Word +#define TC3_BIT _TC3.MergedBits.grpBIT + + +/*** TC4 - Timer Input Capture/Output Compare Register 4; 0x00000058 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC4Hi - Timer Input Capture/Output Compare Register 4 High; 0x00000058 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Timer Input Capture/Output Compare Register 4 Bit 8 */ + byte BIT9 :1; /* Timer Input Capture/Output Compare Register 4 Bit 9 */ + byte BIT10 :1; /* Timer Input Capture/Output Compare Register 4 Bit 10 */ + byte BIT11 :1; /* Timer Input Capture/Output Compare Register 4 Bit 11 */ + byte BIT12 :1; /* Timer Input Capture/Output Compare Register 4 Bit 12 */ + byte BIT13 :1; /* Timer Input Capture/Output Compare Register 4 Bit 13 */ + byte BIT14 :1; /* Timer Input Capture/Output Compare Register 4 Bit 14 */ + byte BIT15 :1; /* Timer Input Capture/Output Compare Register 4 Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } TC4HiSTR; + #define TC4Hi _TC4.Overlap_STR.TC4HiSTR.Byte + #define TC4Hi_BIT8 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT8 + #define TC4Hi_BIT9 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT9 + #define TC4Hi_BIT10 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT10 + #define TC4Hi_BIT11 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT11 + #define TC4Hi_BIT12 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT12 + #define TC4Hi_BIT13 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT13 + #define TC4Hi_BIT14 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT14 + #define TC4Hi_BIT15 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT15 + #define TC4Hi_BIT_8 _TC4.Overlap_STR.TC4HiSTR.MergedBits.grpBIT_8 + #define TC4Hi_BIT TC4Hi_BIT_8 + + /*** TC4Lo - Timer Input Capture/Output Compare Register 4 Low; 0x00000059 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Input Capture/Output Compare Register 4 Bit 0 */ + byte BIT1 :1; /* Timer Input Capture/Output Compare Register 4 Bit 1 */ + byte BIT2 :1; /* Timer Input Capture/Output Compare Register 4 Bit 2 */ + byte BIT3 :1; /* Timer Input Capture/Output Compare Register 4 Bit 3 */ + byte BIT4 :1; /* Timer Input Capture/Output Compare Register 4 Bit 4 */ + byte BIT5 :1; /* Timer Input Capture/Output Compare Register 4 Bit 5 */ + byte BIT6 :1; /* Timer Input Capture/Output Compare Register 4 Bit 6 */ + byte BIT7 :1; /* Timer Input Capture/Output Compare Register 4 Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } TC4LoSTR; + #define TC4Lo _TC4.Overlap_STR.TC4LoSTR.Byte + #define TC4Lo_BIT0 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT0 + #define TC4Lo_BIT1 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT1 + #define TC4Lo_BIT2 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT2 + #define TC4Lo_BIT3 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT3 + #define TC4Lo_BIT4 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT4 + #define TC4Lo_BIT5 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT5 + #define TC4Lo_BIT6 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT6 + #define TC4Lo_BIT7 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT7 + #define TC4Lo_BIT _TC4.Overlap_STR.TC4LoSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} TC4STR; +extern volatile TC4STR _TC4 @(REG_BASE + 0x00000058); +#define TC4 _TC4.Word +#define TC4_BIT _TC4.MergedBits.grpBIT + + +/*** TC5 - Timer Input Capture/Output Compare Register 5; 0x0000005A ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC5Hi - Timer Input Capture/Output Compare Register 5 High; 0x0000005A ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Timer Input Capture/Output Compare Register 5 Bit 8 */ + byte BIT9 :1; /* Timer Input Capture/Output Compare Register 5 Bit 9 */ + byte BIT10 :1; /* Timer Input Capture/Output Compare Register 5 Bit 10 */ + byte BIT11 :1; /* Timer Input Capture/Output Compare Register 5 Bit 11 */ + byte BIT12 :1; /* Timer Input Capture/Output Compare Register 5 Bit 12 */ + byte BIT13 :1; /* Timer Input Capture/Output Compare Register 5 Bit 13 */ + byte BIT14 :1; /* Timer Input Capture/Output Compare Register 5 Bit 14 */ + byte BIT15 :1; /* Timer Input Capture/Output Compare Register 5 Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } TC5HiSTR; + #define TC5Hi _TC5.Overlap_STR.TC5HiSTR.Byte + #define TC5Hi_BIT8 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT8 + #define TC5Hi_BIT9 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT9 + #define TC5Hi_BIT10 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT10 + #define TC5Hi_BIT11 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT11 + #define TC5Hi_BIT12 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT12 + #define TC5Hi_BIT13 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT13 + #define TC5Hi_BIT14 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT14 + #define TC5Hi_BIT15 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT15 + #define TC5Hi_BIT_8 _TC5.Overlap_STR.TC5HiSTR.MergedBits.grpBIT_8 + #define TC5Hi_BIT TC5Hi_BIT_8 + + /*** TC5Lo - Timer Input Capture/Output Compare Register 5 Low; 0x0000005B ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Input Capture/Output Compare Register 5 Bit 0 */ + byte BIT1 :1; /* Timer Input Capture/Output Compare Register 5 Bit 1 */ + byte BIT2 :1; /* Timer Input Capture/Output Compare Register 5 Bit 2 */ + byte BIT3 :1; /* Timer Input Capture/Output Compare Register 5 Bit 3 */ + byte BIT4 :1; /* Timer Input Capture/Output Compare Register 5 Bit 4 */ + byte BIT5 :1; /* Timer Input Capture/Output Compare Register 5 Bit 5 */ + byte BIT6 :1; /* Timer Input Capture/Output Compare Register 5 Bit 6 */ + byte BIT7 :1; /* Timer Input Capture/Output Compare Register 5 Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } TC5LoSTR; + #define TC5Lo _TC5.Overlap_STR.TC5LoSTR.Byte + #define TC5Lo_BIT0 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT0 + #define TC5Lo_BIT1 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT1 + #define TC5Lo_BIT2 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT2 + #define TC5Lo_BIT3 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT3 + #define TC5Lo_BIT4 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT4 + #define TC5Lo_BIT5 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT5 + #define TC5Lo_BIT6 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT6 + #define TC5Lo_BIT7 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT7 + #define TC5Lo_BIT _TC5.Overlap_STR.TC5LoSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} TC5STR; +extern volatile TC5STR _TC5 @(REG_BASE + 0x0000005A); +#define TC5 _TC5.Word +#define TC5_BIT _TC5.MergedBits.grpBIT + + +/*** TC6 - Timer Input Capture/Output Compare Register 6; 0x0000005C ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC6Hi - Timer Input Capture/Output Compare Register 6 High; 0x0000005C ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Timer Input Capture/Output Compare Register 6 Bit 8 */ + byte BIT9 :1; /* Timer Input Capture/Output Compare Register 6 Bit 9 */ + byte BIT10 :1; /* Timer Input Capture/Output Compare Register 6 Bit 10 */ + byte BIT11 :1; /* Timer Input Capture/Output Compare Register 6 Bit 11 */ + byte BIT12 :1; /* Timer Input Capture/Output Compare Register 6 Bit 12 */ + byte BIT13 :1; /* Timer Input Capture/Output Compare Register 6 Bit 13 */ + byte BIT14 :1; /* Timer Input Capture/Output Compare Register 6 Bit 14 */ + byte BIT15 :1; /* Timer Input Capture/Output Compare Register 6 Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } TC6HiSTR; + #define TC6Hi _TC6.Overlap_STR.TC6HiSTR.Byte + #define TC6Hi_BIT8 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT8 + #define TC6Hi_BIT9 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT9 + #define TC6Hi_BIT10 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT10 + #define TC6Hi_BIT11 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT11 + #define TC6Hi_BIT12 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT12 + #define TC6Hi_BIT13 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT13 + #define TC6Hi_BIT14 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT14 + #define TC6Hi_BIT15 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT15 + #define TC6Hi_BIT_8 _TC6.Overlap_STR.TC6HiSTR.MergedBits.grpBIT_8 + #define TC6Hi_BIT TC6Hi_BIT_8 + + /*** TC6Lo - Timer Input Capture/Output Compare Register 6 Low; 0x0000005D ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Input Capture/Output Compare Register 6 Bit 0 */ + byte BIT1 :1; /* Timer Input Capture/Output Compare Register 6 Bit 1 */ + byte BIT2 :1; /* Timer Input Capture/Output Compare Register 6 Bit 2 */ + byte BIT3 :1; /* Timer Input Capture/Output Compare Register 6 Bit 3 */ + byte BIT4 :1; /* Timer Input Capture/Output Compare Register 6 Bit 4 */ + byte BIT5 :1; /* Timer Input Capture/Output Compare Register 6 Bit 5 */ + byte BIT6 :1; /* Timer Input Capture/Output Compare Register 6 Bit 6 */ + byte BIT7 :1; /* Timer Input Capture/Output Compare Register 6 Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } TC6LoSTR; + #define TC6Lo _TC6.Overlap_STR.TC6LoSTR.Byte + #define TC6Lo_BIT0 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT0 + #define TC6Lo_BIT1 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT1 + #define TC6Lo_BIT2 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT2 + #define TC6Lo_BIT3 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT3 + #define TC6Lo_BIT4 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT4 + #define TC6Lo_BIT5 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT5 + #define TC6Lo_BIT6 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT6 + #define TC6Lo_BIT7 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT7 + #define TC6Lo_BIT _TC6.Overlap_STR.TC6LoSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} TC6STR; +extern volatile TC6STR _TC6 @(REG_BASE + 0x0000005C); +#define TC6 _TC6.Word +#define TC6_BIT _TC6.MergedBits.grpBIT + + +/*** TC7 - Timer Input Capture/Output Compare Register 7; 0x0000005E ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC7Hi - Timer Input Capture/Output Compare Register 7 High; 0x0000005E ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Timer Input Capture/Output Compare Register 7 Bit 8 */ + byte BIT9 :1; /* Timer Input Capture/Output Compare Register 7 Bit 9 */ + byte BIT10 :1; /* Timer Input Capture/Output Compare Register 7 Bit 10 */ + byte BIT11 :1; /* Timer Input Capture/Output Compare Register 7 Bit 11 */ + byte BIT12 :1; /* Timer Input Capture/Output Compare Register 7 Bit 12 */ + byte BIT13 :1; /* Timer Input Capture/Output Compare Register 7 Bit 13 */ + byte BIT14 :1; /* Timer Input Capture/Output Compare Register 7 Bit 14 */ + byte BIT15 :1; /* Timer Input Capture/Output Compare Register 7 Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } TC7HiSTR; + #define TC7Hi _TC7.Overlap_STR.TC7HiSTR.Byte + #define TC7Hi_BIT8 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT8 + #define TC7Hi_BIT9 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT9 + #define TC7Hi_BIT10 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT10 + #define TC7Hi_BIT11 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT11 + #define TC7Hi_BIT12 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT12 + #define TC7Hi_BIT13 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT13 + #define TC7Hi_BIT14 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT14 + #define TC7Hi_BIT15 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT15 + #define TC7Hi_BIT_8 _TC7.Overlap_STR.TC7HiSTR.MergedBits.grpBIT_8 + #define TC7Hi_BIT TC7Hi_BIT_8 + + /*** TC7Lo - Timer Input Capture/Output Compare Register 7 Low; 0x0000005F ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Input Capture/Output Compare Register 7 Bit 0 */ + byte BIT1 :1; /* Timer Input Capture/Output Compare Register 7 Bit 1 */ + byte BIT2 :1; /* Timer Input Capture/Output Compare Register 7 Bit 2 */ + byte BIT3 :1; /* Timer Input Capture/Output Compare Register 7 Bit 3 */ + byte BIT4 :1; /* Timer Input Capture/Output Compare Register 7 Bit 4 */ + byte BIT5 :1; /* Timer Input Capture/Output Compare Register 7 Bit 5 */ + byte BIT6 :1; /* Timer Input Capture/Output Compare Register 7 Bit 6 */ + byte BIT7 :1; /* Timer Input Capture/Output Compare Register 7 Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } TC7LoSTR; + #define TC7Lo _TC7.Overlap_STR.TC7LoSTR.Byte + #define TC7Lo_BIT0 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT0 + #define TC7Lo_BIT1 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT1 + #define TC7Lo_BIT2 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT2 + #define TC7Lo_BIT3 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT3 + #define TC7Lo_BIT4 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT4 + #define TC7Lo_BIT5 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT5 + #define TC7Lo_BIT6 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT6 + #define TC7Lo_BIT7 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT7 + #define TC7Lo_BIT _TC7.Overlap_STR.TC7LoSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} TC7STR; +extern volatile TC7STR _TC7 @(REG_BASE + 0x0000005E); +#define TC7 _TC7.Word +#define TC7_BIT _TC7.MergedBits.grpBIT + + +/*** PACN32 - Pulse Accumulators Count 32 Register; 0x00000062 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PACN3 - Pulse Accumulators Count 3 Register; 0x00000062 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PACN3STR; + #define PACN3 _PACN32.Overlap_STR.PACN3STR.Byte + #define PACN3_BIT _PACN32.Overlap_STR.PACN3STR.MergedBits.grpBIT + + /*** PACN2 - Pulse Accumulators Count 2 Register; 0x00000063 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PACN2STR; + #define PACN2 _PACN32.Overlap_STR.PACN2STR.Byte + #define PACN2_BIT _PACN32.Overlap_STR.PACN2STR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} PACN32STR; +extern volatile PACN32STR _PACN32 @(REG_BASE + 0x00000062); +#define PACN32 _PACN32.Word +#define PACN32_BIT _PACN32.MergedBits.grpBIT + + +/*** PACN10 - Pulse Accumulators Count 10 Register; 0x00000064 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PACN1 - Pulse Accumulators Count 1 Register; 0x00000064 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PACN1STR; + #define PACN1 _PACN10.Overlap_STR.PACN1STR.Byte + #define PACN1_BIT _PACN10.Overlap_STR.PACN1STR.MergedBits.grpBIT + + /*** PACN0 - Pulse Accumulators Count 0 Register; 0x00000065 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PACN0STR; + #define PACN0 _PACN10.Overlap_STR.PACN0STR.Byte + #define PACN0_BIT _PACN10.Overlap_STR.PACN0STR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} PACN10STR; +extern volatile PACN10STR _PACN10 @(REG_BASE + 0x00000064); +#define PACN10 _PACN10.Word +#define PACN10_BIT _PACN10.MergedBits.grpBIT + + +/*** PA32H - 8-Bit Pulse Accumulators Holding 32 Register; 0x00000072 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PA3H - 8-Bit Pulse Accumulators Holding 3 Register; 0x00000072 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Pulse Accumulator Bit 0 */ + byte BIT1 :1; /* Pulse Accumulator Bit 1 */ + byte BIT2 :1; /* Pulse Accumulator Bit 2 */ + byte BIT3 :1; /* Pulse Accumulator Bit 3 */ + byte BIT4 :1; /* Pulse Accumulator Bit 4 */ + byte BIT5 :1; /* Pulse Accumulator Bit 5 */ + byte BIT6 :1; /* Pulse Accumulator Bit 6 */ + byte BIT7 :1; /* Pulse Accumulator Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } PA3HSTR; + #define PA3H _PA32H.Overlap_STR.PA3HSTR.Byte + #define PA3H_BIT0 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT0 + #define PA3H_BIT1 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT1 + #define PA3H_BIT2 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT2 + #define PA3H_BIT3 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT3 + #define PA3H_BIT4 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT4 + #define PA3H_BIT5 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT5 + #define PA3H_BIT6 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT6 + #define PA3H_BIT7 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT7 + #define PA3H_BIT _PA32H.Overlap_STR.PA3HSTR.MergedBits.grpBIT + + /*** PA2H - 8-Bit Pulse Accumulators Holding 2 Register; 0x00000073 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Pulse Accumulator Bit 0 */ + byte BIT1 :1; /* Pulse Accumulator Bit 1 */ + byte BIT2 :1; /* Pulse Accumulator Bit 2 */ + byte BIT3 :1; /* Pulse Accumulator Bit 3 */ + byte BIT4 :1; /* Pulse Accumulator Bit 4 */ + byte BIT5 :1; /* Pulse Accumulator Bit 5 */ + byte BIT6 :1; /* Pulse Accumulator Bit 6 */ + byte BIT7 :1; /* Pulse Accumulator Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } PA2HSTR; + #define PA2H _PA32H.Overlap_STR.PA2HSTR.Byte + #define PA2H_BIT0 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT0 + #define PA2H_BIT1 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT1 + #define PA2H_BIT2 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT2 + #define PA2H_BIT3 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT3 + #define PA2H_BIT4 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT4 + #define PA2H_BIT5 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT5 + #define PA2H_BIT6 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT6 + #define PA2H_BIT7 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT7 + #define PA2H_BIT _PA32H.Overlap_STR.PA2HSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word BIT0 :1; /* Pulse Accumulator Bit 0 */ + word BIT1 :1; /* Pulse Accumulator Bit 1 */ + word BIT2 :1; /* Pulse Accumulator Bit 2 */ + word BIT3 :1; /* Pulse Accumulator Bit 3 */ + word BIT4 :1; /* Pulse Accumulator Bit 4 */ + word BIT5 :1; /* Pulse Accumulator Bit 5 */ + word BIT6 :1; /* Pulse Accumulator Bit 6 */ + word BIT7 :1; /* Pulse Accumulator Bit 7 */ + word BIT8 :1; /* Pulse Accumulator Bit 8 */ + word BIT9 :1; /* Pulse Accumulator Bit 9 */ + word BIT10 :1; /* Pulse Accumulator Bit 10 */ + word BIT11 :1; /* Pulse Accumulator Bit 11 */ + word BIT12 :1; /* Pulse Accumulator Bit 12 */ + word BIT13 :1; /* Pulse Accumulator Bit 13 */ + word BIT14 :1; /* Pulse Accumulator Bit 14 */ + word BIT15 :1; /* Pulse Accumulator Bit 15 */ + } Bits; + struct { + word grpBIT :16; + } MergedBits; +} PA32HSTR; +extern volatile PA32HSTR _PA32H @(REG_BASE + 0x00000072); +#define PA32H _PA32H.Word +#define PA32H_BIT0 _PA32H.Bits.BIT0 +#define PA32H_BIT1 _PA32H.Bits.BIT1 +#define PA32H_BIT2 _PA32H.Bits.BIT2 +#define PA32H_BIT3 _PA32H.Bits.BIT3 +#define PA32H_BIT4 _PA32H.Bits.BIT4 +#define PA32H_BIT5 _PA32H.Bits.BIT5 +#define PA32H_BIT6 _PA32H.Bits.BIT6 +#define PA32H_BIT7 _PA32H.Bits.BIT7 +#define PA32H_BIT8 _PA32H.Bits.BIT8 +#define PA32H_BIT9 _PA32H.Bits.BIT9 +#define PA32H_BIT10 _PA32H.Bits.BIT10 +#define PA32H_BIT11 _PA32H.Bits.BIT11 +#define PA32H_BIT12 _PA32H.Bits.BIT12 +#define PA32H_BIT13 _PA32H.Bits.BIT13 +#define PA32H_BIT14 _PA32H.Bits.BIT14 +#define PA32H_BIT15 _PA32H.Bits.BIT15 +#define PA32H_BIT _PA32H.MergedBits.grpBIT + + +/*** PA10H - 8-Bit Pulse Accumulators Holding 10 Register; 0x00000074 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PA1H - 8-Bit Pulse Accumulators Holding 1 Register; 0x00000074 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Pulse Accumulator Bit 0 */ + byte BIT1 :1; /* Pulse Accumulator Bit 1 */ + byte BIT2 :1; /* Pulse Accumulator Bit 2 */ + byte BIT3 :1; /* Pulse Accumulator Bit 3 */ + byte BIT4 :1; /* Pulse Accumulator Bit 4 */ + byte BIT5 :1; /* Pulse Accumulator Bit 5 */ + byte BIT6 :1; /* Pulse Accumulator Bit 6 */ + byte BIT7 :1; /* Pulse Accumulator Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } PA1HSTR; + #define PA1H _PA10H.Overlap_STR.PA1HSTR.Byte + #define PA1H_BIT0 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT0 + #define PA1H_BIT1 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT1 + #define PA1H_BIT2 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT2 + #define PA1H_BIT3 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT3 + #define PA1H_BIT4 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT4 + #define PA1H_BIT5 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT5 + #define PA1H_BIT6 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT6 + #define PA1H_BIT7 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT7 + #define PA1H_BIT _PA10H.Overlap_STR.PA1HSTR.MergedBits.grpBIT + + /*** PA0H - 8-Bit Pulse Accumulators Holding 0 Register; 0x00000075 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Pulse Accumulator Bit 0 */ + byte BIT1 :1; /* Pulse Accumulator Bit 1 */ + byte BIT2 :1; /* Pulse Accumulator Bit 2 */ + byte BIT3 :1; /* Pulse Accumulator Bit 3 */ + byte BIT4 :1; /* Pulse Accumulator Bit 4 */ + byte BIT5 :1; /* Pulse Accumulator Bit 5 */ + byte BIT6 :1; /* Pulse Accumulator Bit 6 */ + byte BIT7 :1; /* Pulse Accumulator Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } PA0HSTR; + #define PA0H _PA10H.Overlap_STR.PA0HSTR.Byte + #define PA0H_BIT0 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT0 + #define PA0H_BIT1 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT1 + #define PA0H_BIT2 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT2 + #define PA0H_BIT3 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT3 + #define PA0H_BIT4 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT4 + #define PA0H_BIT5 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT5 + #define PA0H_BIT6 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT6 + #define PA0H_BIT7 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT7 + #define PA0H_BIT _PA10H.Overlap_STR.PA0HSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word BIT0 :1; /* Pulse Accumulator Bit 0 */ + word BIT1 :1; /* Pulse Accumulator Bit 1 */ + word BIT2 :1; /* Pulse Accumulator Bit 2 */ + word BIT3 :1; /* Pulse Accumulator Bit 3 */ + word BIT4 :1; /* Pulse Accumulator Bit 4 */ + word BIT5 :1; /* Pulse Accumulator Bit 5 */ + word BIT6 :1; /* Pulse Accumulator Bit 6 */ + word BIT7 :1; /* Pulse Accumulator Bit 7 */ + word BIT8 :1; /* Pulse Accumulator Bit 8 */ + word BIT9 :1; /* Pulse Accumulator Bit 9 */ + word BIT10 :1; /* Pulse Accumulator Bit 10 */ + word BIT11 :1; /* Pulse Accumulator Bit 11 */ + word BIT12 :1; /* Pulse Accumulator Bit 12 */ + word BIT13 :1; /* Pulse Accumulator Bit 13 */ + word BIT14 :1; /* Pulse Accumulator Bit 14 */ + word BIT15 :1; /* Pulse Accumulator Bit 15 */ + } Bits; + struct { + word grpBIT :16; + } MergedBits; +} PA10HSTR; +extern volatile PA10HSTR _PA10H @(REG_BASE + 0x00000074); +#define PA10H _PA10H.Word +#define PA10H_BIT0 _PA10H.Bits.BIT0 +#define PA10H_BIT1 _PA10H.Bits.BIT1 +#define PA10H_BIT2 _PA10H.Bits.BIT2 +#define PA10H_BIT3 _PA10H.Bits.BIT3 +#define PA10H_BIT4 _PA10H.Bits.BIT4 +#define PA10H_BIT5 _PA10H.Bits.BIT5 +#define PA10H_BIT6 _PA10H.Bits.BIT6 +#define PA10H_BIT7 _PA10H.Bits.BIT7 +#define PA10H_BIT8 _PA10H.Bits.BIT8 +#define PA10H_BIT9 _PA10H.Bits.BIT9 +#define PA10H_BIT10 _PA10H.Bits.BIT10 +#define PA10H_BIT11 _PA10H.Bits.BIT11 +#define PA10H_BIT12 _PA10H.Bits.BIT12 +#define PA10H_BIT13 _PA10H.Bits.BIT13 +#define PA10H_BIT14 _PA10H.Bits.BIT14 +#define PA10H_BIT15 _PA10H.Bits.BIT15 +#define PA10H_BIT _PA10H.MergedBits.grpBIT + + +/*** MCCNT - Modulus Down-Counter Count Register; 0x00000076 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** MCCNThi - Modulus Down-Counter Count Register High; 0x00000076 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Modulus Down-Counter Bit 8 */ + byte BIT9 :1; /* Modulus Down-Counter Bit 9 */ + byte BIT10 :1; /* Modulus Down-Counter Bit 10 */ + byte BIT11 :1; /* Modulus Down-Counter Bit 11 */ + byte BIT12 :1; /* Modulus Down-Counter Bit 12 */ + byte BIT13 :1; /* Modulus Down-Counter Bit 13 */ + byte BIT14 :1; /* Modulus Down-Counter Bit 14 */ + byte BIT15 :1; /* Modulus Down-Counter Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } MCCNThiSTR; + #define MCCNThi _MCCNT.Overlap_STR.MCCNThiSTR.Byte + #define MCCNThi_BIT8 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT8 + #define MCCNThi_BIT9 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT9 + #define MCCNThi_BIT10 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT10 + #define MCCNThi_BIT11 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT11 + #define MCCNThi_BIT12 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT12 + #define MCCNThi_BIT13 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT13 + #define MCCNThi_BIT14 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT14 + #define MCCNThi_BIT15 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT15 + #define MCCNThi_BIT_8 _MCCNT.Overlap_STR.MCCNThiSTR.MergedBits.grpBIT_8 + #define MCCNThi_BIT MCCNThi_BIT_8 + + /*** MCCNTlo - Modulus Down-Counter Count Register Low; 0x00000077 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Modulus Down-Counter Bit 0 */ + byte BIT1 :1; /* Modulus Down-Counter Bit 1 */ + byte BIT2 :1; /* Modulus Down-Counter Bit 2 */ + byte BIT3 :1; /* Modulus Down-Counter Bit 3 */ + byte BIT4 :1; /* Modulus Down-Counter Bit 4 */ + byte BIT5 :1; /* Modulus Down-Counter Bit 5 */ + byte BIT6 :1; /* Modulus Down-Counter Bit 6 */ + byte BIT7 :1; /* Modulus Down-Counter Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } MCCNTloSTR; + #define MCCNTlo _MCCNT.Overlap_STR.MCCNTloSTR.Byte + #define MCCNTlo_BIT0 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT0 + #define MCCNTlo_BIT1 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT1 + #define MCCNTlo_BIT2 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT2 + #define MCCNTlo_BIT3 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT3 + #define MCCNTlo_BIT4 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT4 + #define MCCNTlo_BIT5 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT5 + #define MCCNTlo_BIT6 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT6 + #define MCCNTlo_BIT7 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT7 + #define MCCNTlo_BIT _MCCNT.Overlap_STR.MCCNTloSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} MCCNTSTR; +extern volatile MCCNTSTR _MCCNT @(REG_BASE + 0x00000076); +#define MCCNT _MCCNT.Word +#define MCCNT_BIT _MCCNT.MergedBits.grpBIT + + +/*** TC0H - Timer Input Capture Holding Registers 0; 0x00000078 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC0Hhi - Timer Input Capture Holding Registers 0 High; 0x00000078 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Timer Input Capture Holding Bit 8 */ + byte BIT9 :1; /* Timer Input Capture Holding Bit 9 */ + byte BIT10 :1; /* Timer Input Capture Holding Bit 10 */ + byte BIT11 :1; /* Timer Input Capture Holding Bit 11 */ + byte BIT12 :1; /* Timer Input Capture Holding Bit 12 */ + byte BIT13 :1; /* Timer Input Capture Holding Bit 13 */ + byte BIT14 :1; /* Timer Input Capture Holding Bit 14 */ + byte BIT15 :1; /* Timer Input Capture Holding Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } TC0HhiSTR; + #define TC0Hhi _TC0H.Overlap_STR.TC0HhiSTR.Byte + #define TC0Hhi_BIT8 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT8 + #define TC0Hhi_BIT9 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT9 + #define TC0Hhi_BIT10 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT10 + #define TC0Hhi_BIT11 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT11 + #define TC0Hhi_BIT12 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT12 + #define TC0Hhi_BIT13 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT13 + #define TC0Hhi_BIT14 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT14 + #define TC0Hhi_BIT15 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT15 + #define TC0Hhi_BIT_8 _TC0H.Overlap_STR.TC0HhiSTR.MergedBits.grpBIT_8 + #define TC0Hhi_BIT TC0Hhi_BIT_8 + + /*** TC0Hlo - Timer Input Capture Holding Registers 0 Low; 0x00000079 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Input Capture Holding Bit 0 */ + byte BIT1 :1; /* Timer Input Capture Holding Bit 1 */ + byte BIT2 :1; /* Timer Input Capture Holding Bit 2 */ + byte BIT3 :1; /* Timer Input Capture Holding Bit 3 */ + byte BIT4 :1; /* Timer Input Capture Holding Bit 4 */ + byte BIT5 :1; /* Timer Input Capture Holding Bit 5 */ + byte BIT6 :1; /* Timer Input Capture Holding Bit 6 */ + byte BIT7 :1; /* Timer Input Capture Holding Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } TC0HloSTR; + #define TC0Hlo _TC0H.Overlap_STR.TC0HloSTR.Byte + #define TC0Hlo_BIT0 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT0 + #define TC0Hlo_BIT1 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT1 + #define TC0Hlo_BIT2 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT2 + #define TC0Hlo_BIT3 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT3 + #define TC0Hlo_BIT4 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT4 + #define TC0Hlo_BIT5 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT5 + #define TC0Hlo_BIT6 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT6 + #define TC0Hlo_BIT7 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT7 + #define TC0Hlo_BIT _TC0H.Overlap_STR.TC0HloSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word BIT0 :1; /* Timer Input Capture Holding Bit 0 */ + word BIT1 :1; /* Timer Input Capture Holding Bit 1 */ + word BIT2 :1; /* Timer Input Capture Holding Bit 2 */ + word BIT3 :1; /* Timer Input Capture Holding Bit 3 */ + word BIT4 :1; /* Timer Input Capture Holding Bit 4 */ + word BIT5 :1; /* Timer Input Capture Holding Bit 5 */ + word BIT6 :1; /* Timer Input Capture Holding Bit 6 */ + word BIT7 :1; /* Timer Input Capture Holding Bit 7 */ + word BIT8 :1; /* Timer Input Capture Holding Bit 8 */ + word BIT9 :1; /* Timer Input Capture Holding Bit 9 */ + word BIT10 :1; /* Timer Input Capture Holding Bit 10 */ + word BIT11 :1; /* Timer Input Capture Holding Bit 11 */ + word BIT12 :1; /* Timer Input Capture Holding Bit 12 */ + word BIT13 :1; /* Timer Input Capture Holding Bit 13 */ + word BIT14 :1; /* Timer Input Capture Holding Bit 14 */ + word BIT15 :1; /* Timer Input Capture Holding Bit 15 */ + } Bits; + struct { + word grpBIT :16; + } MergedBits; +} TC0HSTR; +extern volatile TC0HSTR _TC0H @(REG_BASE + 0x00000078); +#define TC0H _TC0H.Word +#define TC0H_BIT0 _TC0H.Bits.BIT0 +#define TC0H_BIT1 _TC0H.Bits.BIT1 +#define TC0H_BIT2 _TC0H.Bits.BIT2 +#define TC0H_BIT3 _TC0H.Bits.BIT3 +#define TC0H_BIT4 _TC0H.Bits.BIT4 +#define TC0H_BIT5 _TC0H.Bits.BIT5 +#define TC0H_BIT6 _TC0H.Bits.BIT6 +#define TC0H_BIT7 _TC0H.Bits.BIT7 +#define TC0H_BIT8 _TC0H.Bits.BIT8 +#define TC0H_BIT9 _TC0H.Bits.BIT9 +#define TC0H_BIT10 _TC0H.Bits.BIT10 +#define TC0H_BIT11 _TC0H.Bits.BIT11 +#define TC0H_BIT12 _TC0H.Bits.BIT12 +#define TC0H_BIT13 _TC0H.Bits.BIT13 +#define TC0H_BIT14 _TC0H.Bits.BIT14 +#define TC0H_BIT15 _TC0H.Bits.BIT15 +#define TC0H_BIT _TC0H.MergedBits.grpBIT + + +/*** TC1H - Timer Input Capture Holding Registers 1; 0x0000007A ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC1Hhi - Timer Input Capture Holding Registers 1 High; 0x0000007A ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Timer Input Capture Holding Bit 8 */ + byte BIT9 :1; /* Timer Input Capture Holding Bit 9 */ + byte BIT10 :1; /* Timer Input Capture Holding Bit 10 */ + byte BIT11 :1; /* Timer Input Capture Holding Bit 11 */ + byte BIT12 :1; /* Timer Input Capture Holding Bit 12 */ + byte BIT13 :1; /* Timer Input Capture Holding Bit 13 */ + byte BIT14 :1; /* Timer Input Capture Holding Bit 14 */ + byte BIT15 :1; /* Timer Input Capture Holding Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } TC1HhiSTR; + #define TC1Hhi _TC1H.Overlap_STR.TC1HhiSTR.Byte + #define TC1Hhi_BIT8 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT8 + #define TC1Hhi_BIT9 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT9 + #define TC1Hhi_BIT10 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT10 + #define TC1Hhi_BIT11 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT11 + #define TC1Hhi_BIT12 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT12 + #define TC1Hhi_BIT13 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT13 + #define TC1Hhi_BIT14 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT14 + #define TC1Hhi_BIT15 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT15 + #define TC1Hhi_BIT_8 _TC1H.Overlap_STR.TC1HhiSTR.MergedBits.grpBIT_8 + #define TC1Hhi_BIT TC1Hhi_BIT_8 + + /*** TC1Hlo - Timer Input Capture Holding Registers 1 Low; 0x0000007B ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Input Capture Holding Bit 0 */ + byte BIT1 :1; /* Timer Input Capture Holding Bit 1 */ + byte BIT2 :1; /* Timer Input Capture Holding Bit 2 */ + byte BIT3 :1; /* Timer Input Capture Holding Bit 3 */ + byte BIT4 :1; /* Timer Input Capture Holding Bit 4 */ + byte BIT5 :1; /* Timer Input Capture Holding Bit 5 */ + byte BIT6 :1; /* Timer Input Capture Holding Bit 6 */ + byte BIT7 :1; /* Timer Input Capture Holding Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } TC1HloSTR; + #define TC1Hlo _TC1H.Overlap_STR.TC1HloSTR.Byte + #define TC1Hlo_BIT0 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT0 + #define TC1Hlo_BIT1 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT1 + #define TC1Hlo_BIT2 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT2 + #define TC1Hlo_BIT3 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT3 + #define TC1Hlo_BIT4 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT4 + #define TC1Hlo_BIT5 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT5 + #define TC1Hlo_BIT6 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT6 + #define TC1Hlo_BIT7 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT7 + #define TC1Hlo_BIT _TC1H.Overlap_STR.TC1HloSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word BIT0 :1; /* Timer Input Capture Holding Bit 0 */ + word BIT1 :1; /* Timer Input Capture Holding Bit 1 */ + word BIT2 :1; /* Timer Input Capture Holding Bit 2 */ + word BIT3 :1; /* Timer Input Capture Holding Bit 3 */ + word BIT4 :1; /* Timer Input Capture Holding Bit 4 */ + word BIT5 :1; /* Timer Input Capture Holding Bit 5 */ + word BIT6 :1; /* Timer Input Capture Holding Bit 6 */ + word BIT7 :1; /* Timer Input Capture Holding Bit 7 */ + word BIT8 :1; /* Timer Input Capture Holding Bit 8 */ + word BIT9 :1; /* Timer Input Capture Holding Bit 9 */ + word BIT10 :1; /* Timer Input Capture Holding Bit 10 */ + word BIT11 :1; /* Timer Input Capture Holding Bit 11 */ + word BIT12 :1; /* Timer Input Capture Holding Bit 12 */ + word BIT13 :1; /* Timer Input Capture Holding Bit 13 */ + word BIT14 :1; /* Timer Input Capture Holding Bit 14 */ + word BIT15 :1; /* Timer Input Capture Holding Bit 15 */ + } Bits; + struct { + word grpBIT :16; + } MergedBits; +} TC1HSTR; +extern volatile TC1HSTR _TC1H @(REG_BASE + 0x0000007A); +#define TC1H _TC1H.Word +#define TC1H_BIT0 _TC1H.Bits.BIT0 +#define TC1H_BIT1 _TC1H.Bits.BIT1 +#define TC1H_BIT2 _TC1H.Bits.BIT2 +#define TC1H_BIT3 _TC1H.Bits.BIT3 +#define TC1H_BIT4 _TC1H.Bits.BIT4 +#define TC1H_BIT5 _TC1H.Bits.BIT5 +#define TC1H_BIT6 _TC1H.Bits.BIT6 +#define TC1H_BIT7 _TC1H.Bits.BIT7 +#define TC1H_BIT8 _TC1H.Bits.BIT8 +#define TC1H_BIT9 _TC1H.Bits.BIT9 +#define TC1H_BIT10 _TC1H.Bits.BIT10 +#define TC1H_BIT11 _TC1H.Bits.BIT11 +#define TC1H_BIT12 _TC1H.Bits.BIT12 +#define TC1H_BIT13 _TC1H.Bits.BIT13 +#define TC1H_BIT14 _TC1H.Bits.BIT14 +#define TC1H_BIT15 _TC1H.Bits.BIT15 +#define TC1H_BIT _TC1H.MergedBits.grpBIT + + +/*** TC2H - Timer Input Capture Holding Registers 2; 0x0000007C ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC2Hhi - Timer Input Capture Holding Registers 2 High; 0x0000007C ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Timer Input Capture Holding Bit 8 */ + byte BIT9 :1; /* Timer Input Capture Holding Bit 9 */ + byte BIT10 :1; /* Timer Input Capture Holding Bit 10 */ + byte BIT11 :1; /* Timer Input Capture Holding Bit 11 */ + byte BIT12 :1; /* Timer Input Capture Holding Bit 12 */ + byte BIT13 :1; /* Timer Input Capture Holding Bit 13 */ + byte BIT14 :1; /* Timer Input Capture Holding Bit 14 */ + byte BIT15 :1; /* Timer Input Capture Holding Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } TC2HhiSTR; + #define TC2Hhi _TC2H.Overlap_STR.TC2HhiSTR.Byte + #define TC2Hhi_BIT8 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT8 + #define TC2Hhi_BIT9 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT9 + #define TC2Hhi_BIT10 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT10 + #define TC2Hhi_BIT11 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT11 + #define TC2Hhi_BIT12 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT12 + #define TC2Hhi_BIT13 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT13 + #define TC2Hhi_BIT14 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT14 + #define TC2Hhi_BIT15 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT15 + #define TC2Hhi_BIT_8 _TC2H.Overlap_STR.TC2HhiSTR.MergedBits.grpBIT_8 + #define TC2Hhi_BIT TC2Hhi_BIT_8 + + /*** TC2Hlo - Timer Input Capture Holding Registers 2 Low; 0x0000007D ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Input Capture Holding Bit 0 */ + byte BIT1 :1; /* Timer Input Capture Holding Bit 1 */ + byte BIT2 :1; /* Timer Input Capture Holding Bit 2 */ + byte BIT3 :1; /* Timer Input Capture Holding Bit 3 */ + byte BIT4 :1; /* Timer Input Capture Holding Bit 4 */ + byte BIT5 :1; /* Timer Input Capture Holding Bit 5 */ + byte BIT6 :1; /* Timer Input Capture Holding Bit 6 */ + byte BIT7 :1; /* Timer Input Capture Holding Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } TC2HloSTR; + #define TC2Hlo _TC2H.Overlap_STR.TC2HloSTR.Byte + #define TC2Hlo_BIT0 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT0 + #define TC2Hlo_BIT1 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT1 + #define TC2Hlo_BIT2 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT2 + #define TC2Hlo_BIT3 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT3 + #define TC2Hlo_BIT4 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT4 + #define TC2Hlo_BIT5 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT5 + #define TC2Hlo_BIT6 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT6 + #define TC2Hlo_BIT7 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT7 + #define TC2Hlo_BIT _TC2H.Overlap_STR.TC2HloSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word BIT0 :1; /* Timer Input Capture Holding Bit 0 */ + word BIT1 :1; /* Timer Input Capture Holding Bit 1 */ + word BIT2 :1; /* Timer Input Capture Holding Bit 2 */ + word BIT3 :1; /* Timer Input Capture Holding Bit 3 */ + word BIT4 :1; /* Timer Input Capture Holding Bit 4 */ + word BIT5 :1; /* Timer Input Capture Holding Bit 5 */ + word BIT6 :1; /* Timer Input Capture Holding Bit 6 */ + word BIT7 :1; /* Timer Input Capture Holding Bit 7 */ + word BIT8 :1; /* Timer Input Capture Holding Bit 8 */ + word BIT9 :1; /* Timer Input Capture Holding Bit 9 */ + word BIT10 :1; /* Timer Input Capture Holding Bit 10 */ + word BIT11 :1; /* Timer Input Capture Holding Bit 11 */ + word BIT12 :1; /* Timer Input Capture Holding Bit 12 */ + word BIT13 :1; /* Timer Input Capture Holding Bit 13 */ + word BIT14 :1; /* Timer Input Capture Holding Bit 14 */ + word BIT15 :1; /* Timer Input Capture Holding Bit 15 */ + } Bits; + struct { + word grpBIT :16; + } MergedBits; +} TC2HSTR; +extern volatile TC2HSTR _TC2H @(REG_BASE + 0x0000007C); +#define TC2H _TC2H.Word +#define TC2H_BIT0 _TC2H.Bits.BIT0 +#define TC2H_BIT1 _TC2H.Bits.BIT1 +#define TC2H_BIT2 _TC2H.Bits.BIT2 +#define TC2H_BIT3 _TC2H.Bits.BIT3 +#define TC2H_BIT4 _TC2H.Bits.BIT4 +#define TC2H_BIT5 _TC2H.Bits.BIT5 +#define TC2H_BIT6 _TC2H.Bits.BIT6 +#define TC2H_BIT7 _TC2H.Bits.BIT7 +#define TC2H_BIT8 _TC2H.Bits.BIT8 +#define TC2H_BIT9 _TC2H.Bits.BIT9 +#define TC2H_BIT10 _TC2H.Bits.BIT10 +#define TC2H_BIT11 _TC2H.Bits.BIT11 +#define TC2H_BIT12 _TC2H.Bits.BIT12 +#define TC2H_BIT13 _TC2H.Bits.BIT13 +#define TC2H_BIT14 _TC2H.Bits.BIT14 +#define TC2H_BIT15 _TC2H.Bits.BIT15 +#define TC2H_BIT _TC2H.MergedBits.grpBIT + + +/*** TC3H - Timer Input Capture Holding Registers 3; 0x0000007E ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC3Hhi - Timer Input Capture Holding Registers 3 High; 0x0000007E ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Timer Input Capture Holding Bit 8 */ + byte BIT9 :1; /* Timer Input Capture Holding Bit 9 */ + byte BIT10 :1; /* Timer Input Capture Holding Bit 10 */ + byte BIT11 :1; /* Timer Input Capture Holding Bit 11 */ + byte BIT12 :1; /* Timer Input Capture Holding Bit 12 */ + byte BIT13 :1; /* Timer Input Capture Holding Bit 13 */ + byte BIT14 :1; /* Timer Input Capture Holding Bit 14 */ + byte BIT15 :1; /* Timer Input Capture Holding Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } TC3HhiSTR; + #define TC3Hhi _TC3H.Overlap_STR.TC3HhiSTR.Byte + #define TC3Hhi_BIT8 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT8 + #define TC3Hhi_BIT9 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT9 + #define TC3Hhi_BIT10 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT10 + #define TC3Hhi_BIT11 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT11 + #define TC3Hhi_BIT12 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT12 + #define TC3Hhi_BIT13 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT13 + #define TC3Hhi_BIT14 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT14 + #define TC3Hhi_BIT15 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT15 + #define TC3Hhi_BIT_8 _TC3H.Overlap_STR.TC3HhiSTR.MergedBits.grpBIT_8 + #define TC3Hhi_BIT TC3Hhi_BIT_8 + + /*** TC3Hlo - Timer Input Capture Holding Registers 3 Low; 0x0000007F ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Input Capture Holding Bit 0 */ + byte BIT1 :1; /* Timer Input Capture Holding Bit 1 */ + byte BIT2 :1; /* Timer Input Capture Holding Bit 2 */ + byte BIT3 :1; /* Timer Input Capture Holding Bit 3 */ + byte BIT4 :1; /* Timer Input Capture Holding Bit 4 */ + byte BIT5 :1; /* Timer Input Capture Holding Bit 5 */ + byte BIT6 :1; /* Timer Input Capture Holding Bit 6 */ + byte BIT7 :1; /* Timer Input Capture Holding Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } TC3HloSTR; + #define TC3Hlo _TC3H.Overlap_STR.TC3HloSTR.Byte + #define TC3Hlo_BIT0 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT0 + #define TC3Hlo_BIT1 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT1 + #define TC3Hlo_BIT2 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT2 + #define TC3Hlo_BIT3 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT3 + #define TC3Hlo_BIT4 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT4 + #define TC3Hlo_BIT5 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT5 + #define TC3Hlo_BIT6 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT6 + #define TC3Hlo_BIT7 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT7 + #define TC3Hlo_BIT _TC3H.Overlap_STR.TC3HloSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word BIT0 :1; /* Timer Input Capture Holding Bit 0 */ + word BIT1 :1; /* Timer Input Capture Holding Bit 1 */ + word BIT2 :1; /* Timer Input Capture Holding Bit 2 */ + word BIT3 :1; /* Timer Input Capture Holding Bit 3 */ + word BIT4 :1; /* Timer Input Capture Holding Bit 4 */ + word BIT5 :1; /* Timer Input Capture Holding Bit 5 */ + word BIT6 :1; /* Timer Input Capture Holding Bit 6 */ + word BIT7 :1; /* Timer Input Capture Holding Bit 7 */ + word BIT8 :1; /* Timer Input Capture Holding Bit 8 */ + word BIT9 :1; /* Timer Input Capture Holding Bit 9 */ + word BIT10 :1; /* Timer Input Capture Holding Bit 10 */ + word BIT11 :1; /* Timer Input Capture Holding Bit 11 */ + word BIT12 :1; /* Timer Input Capture Holding Bit 12 */ + word BIT13 :1; /* Timer Input Capture Holding Bit 13 */ + word BIT14 :1; /* Timer Input Capture Holding Bit 14 */ + word BIT15 :1; /* Timer Input Capture Holding Bit 15 */ + } Bits; + struct { + word grpBIT :16; + } MergedBits; +} TC3HSTR; +extern volatile TC3HSTR _TC3H @(REG_BASE + 0x0000007E); +#define TC3H _TC3H.Word +#define TC3H_BIT0 _TC3H.Bits.BIT0 +#define TC3H_BIT1 _TC3H.Bits.BIT1 +#define TC3H_BIT2 _TC3H.Bits.BIT2 +#define TC3H_BIT3 _TC3H.Bits.BIT3 +#define TC3H_BIT4 _TC3H.Bits.BIT4 +#define TC3H_BIT5 _TC3H.Bits.BIT5 +#define TC3H_BIT6 _TC3H.Bits.BIT6 +#define TC3H_BIT7 _TC3H.Bits.BIT7 +#define TC3H_BIT8 _TC3H.Bits.BIT8 +#define TC3H_BIT9 _TC3H.Bits.BIT9 +#define TC3H_BIT10 _TC3H.Bits.BIT10 +#define TC3H_BIT11 _TC3H.Bits.BIT11 +#define TC3H_BIT12 _TC3H.Bits.BIT12 +#define TC3H_BIT13 _TC3H.Bits.BIT13 +#define TC3H_BIT14 _TC3H.Bits.BIT14 +#define TC3H_BIT15 _TC3H.Bits.BIT15 +#define TC3H_BIT _TC3H.MergedBits.grpBIT + + +/*** ATD0CTL23 - ATD 0 Control Register 23; 0x00000082 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD0CTL2 - ATD 0 Control Register 2; 0x00000082 ***/ + union { + byte Byte; + struct { + byte ASCIF :1; /* ATD 0 Sequence Complete Interrupt Flag */ + byte ASCIE :1; /* ATD 0 Sequence Complete Interrupt Enable */ + byte ETRIGE :1; /* External Trigger Mode enable */ + byte ETRIGP :1; /* External Trigger Polarity */ + byte ETRIGLE :1; /* External Trigger Level/Edge control */ + byte AWAI :1; /* ATD 0 Wait Mode */ + byte AFFC :1; /* ATD 0 Fast Conversion Complete Flag Clear */ + byte ADPU :1; /* ATD 0 Disable / Power Down */ + } Bits; + } ATD0CTL2STR; + #define ATD0CTL2 _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Byte + #define ATD0CTL2_ASCIF _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ASCIF + #define ATD0CTL2_ASCIE _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ASCIE + #define ATD0CTL2_ETRIGE _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ETRIGE + #define ATD0CTL2_ETRIGP _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ETRIGP + #define ATD0CTL2_ETRIGLE _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ETRIGLE + #define ATD0CTL2_AWAI _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.AWAI + #define ATD0CTL2_AFFC _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.AFFC + #define ATD0CTL2_ADPU _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ADPU + + /*** ATD0CTL3 - ATD 0 Control Register 3; 0x00000083 ***/ + union { + byte Byte; + struct { + byte FRZ0 :1; /* Background Debug Freeze Enable */ + byte FRZ1 :1; /* Background Debug Freeze Enable */ + byte FIFO :1; /* Result Register FIFO Mode */ + byte S1C :1; /* Conversion Sequence Length 1 */ + byte S2C :1; /* Conversion Sequence Length 2 */ + byte S4C :1; /* Conversion Sequence Length 4 */ + byte S8C :1; /* Conversion Sequence Length 8 */ + byte :1; + } Bits; + struct { + byte grpFRZ :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; + } ATD0CTL3STR; + #define ATD0CTL3 _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Byte + #define ATD0CTL3_FRZ0 _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.FRZ0 + #define ATD0CTL3_FRZ1 _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.FRZ1 + #define ATD0CTL3_FIFO _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.FIFO + #define ATD0CTL3_S1C _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.S1C + #define ATD0CTL3_S2C _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.S2C + #define ATD0CTL3_S4C _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.S4C + #define ATD0CTL3_S8C _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.S8C + #define ATD0CTL3_FRZ _ATD0CTL23.Overlap_STR.ATD0CTL3STR.MergedBits.grpFRZ + + } Overlap_STR; + + struct { + word FRZ0 :1; /* Background Debug Freeze Enable */ + word FRZ1 :1; /* Background Debug Freeze Enable */ + word FIFO :1; /* Result Register FIFO Mode */ + word S1C :1; /* Conversion Sequence Length 1 */ + word S2C :1; /* Conversion Sequence Length 2 */ + word S4C :1; /* Conversion Sequence Length 4 */ + word S8C :1; /* Conversion Sequence Length 8 */ + word :1; + word ASCIF :1; /* ATD 0 Sequence Complete Interrupt Flag */ + word ASCIE :1; /* ATD 0 Sequence Complete Interrupt Enable */ + word ETRIGE :1; /* External Trigger Mode enable */ + word ETRIGP :1; /* External Trigger Polarity */ + word ETRIGLE :1; /* External Trigger Level/Edge control */ + word AWAI :1; /* ATD 0 Wait Mode */ + word AFFC :1; /* ATD 0 Fast Conversion Complete Flag Clear */ + word ADPU :1; /* ATD 0 Disable / Power Down */ + } Bits; + struct { + word grpFRZ :2; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + } MergedBits; +} ATD0CTL23STR; +extern volatile ATD0CTL23STR _ATD0CTL23 @(REG_BASE + 0x00000082); +#define ATD0CTL23 _ATD0CTL23.Word +#define ATD0CTL23_FRZ0 _ATD0CTL23.Bits.FRZ0 +#define ATD0CTL23_FRZ1 _ATD0CTL23.Bits.FRZ1 +#define ATD0CTL23_FIFO _ATD0CTL23.Bits.FIFO +#define ATD0CTL23_S1C _ATD0CTL23.Bits.S1C +#define ATD0CTL23_S2C _ATD0CTL23.Bits.S2C +#define ATD0CTL23_S4C _ATD0CTL23.Bits.S4C +#define ATD0CTL23_S8C _ATD0CTL23.Bits.S8C +#define ATD0CTL23_ASCIF _ATD0CTL23.Bits.ASCIF +#define ATD0CTL23_ASCIE _ATD0CTL23.Bits.ASCIE +#define ATD0CTL23_ETRIGE _ATD0CTL23.Bits.ETRIGE +#define ATD0CTL23_ETRIGP _ATD0CTL23.Bits.ETRIGP +#define ATD0CTL23_ETRIGLE _ATD0CTL23.Bits.ETRIGLE +#define ATD0CTL23_AWAI _ATD0CTL23.Bits.AWAI +#define ATD0CTL23_AFFC _ATD0CTL23.Bits.AFFC +#define ATD0CTL23_ADPU _ATD0CTL23.Bits.ADPU +#define ATD0CTL23_FRZ _ATD0CTL23.MergedBits.grpFRZ + + +/*** ATD0CTL45 - ATD 0 Control Register 45; 0x00000084 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD0CTL4 - ATD 0 Control Register 4; 0x00000084 ***/ + union { + byte Byte; + struct { + byte PRS0 :1; /* ATD 0 Clock Prescaler 0 */ + byte PRS1 :1; /* ATD 0 Clock Prescaler 1 */ + byte PRS2 :1; /* ATD 0 Clock Prescaler 2 */ + byte PRS3 :1; /* ATD 0 Clock Prescaler 3 */ + byte PRS4 :1; /* ATD 0 Clock Prescaler 4 */ + byte SMP0 :1; /* Sample Time Select 0 */ + byte SMP1 :1; /* Sample Time Select 1 */ + byte SRES8 :1; /* ATD 0 Resolution Select */ + } Bits; + struct { + byte grpPRS :5; + byte grpSMP :2; + byte grpSRES_8 :1; + } MergedBits; + } ATD0CTL4STR; + #define ATD0CTL4 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Byte + #define ATD0CTL4_PRS0 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.PRS0 + #define ATD0CTL4_PRS1 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.PRS1 + #define ATD0CTL4_PRS2 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.PRS2 + #define ATD0CTL4_PRS3 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.PRS3 + #define ATD0CTL4_PRS4 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.PRS4 + #define ATD0CTL4_SMP0 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.SMP0 + #define ATD0CTL4_SMP1 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.SMP1 + #define ATD0CTL4_SRES8 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.SRES8 + #define ATD0CTL4_PRS _ATD0CTL45.Overlap_STR.ATD0CTL4STR.MergedBits.grpPRS + #define ATD0CTL4_SMP _ATD0CTL45.Overlap_STR.ATD0CTL4STR.MergedBits.grpSMP + + /*** ATD0CTL5 - ATD 0 Control Register 5; 0x00000085 ***/ + union { + byte Byte; + struct { + byte CA :1; /* Analog Input Channel Select Code A */ + byte CB :1; /* Analog Input Channel Select Code B */ + byte CC :1; /* Analog Input Channel Select Code C */ + byte :1; + byte MULT :1; /* Multi-Channel Sample Mode */ + byte SCAN :1; /* Continuous Conversion Sequence Mode */ + byte DSGN :1; /* Signed/Unsigned Result Data Mode */ + byte DJM :1; /* Result Register Data Justification Mode */ + } Bits; + } ATD0CTL5STR; + #define ATD0CTL5 _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Byte + #define ATD0CTL5_CA _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.CA + #define ATD0CTL5_CB _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.CB + #define ATD0CTL5_CC _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.CC + #define ATD0CTL5_MULT _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.MULT + #define ATD0CTL5_SCAN _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.SCAN + #define ATD0CTL5_DSGN _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.DSGN + #define ATD0CTL5_DJM _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.DJM + + } Overlap_STR; + + struct { + word CA :1; /* Analog Input Channel Select Code A */ + word CB :1; /* Analog Input Channel Select Code B */ + word CC :1; /* Analog Input Channel Select Code C */ + word :1; + word MULT :1; /* Multi-Channel Sample Mode */ + word SCAN :1; /* Continuous Conversion Sequence Mode */ + word DSGN :1; /* Signed/Unsigned Result Data Mode */ + word DJM :1; /* Result Register Data Justification Mode */ + word PRS0 :1; /* ATD 0 Clock Prescaler 0 */ + word PRS1 :1; /* ATD 0 Clock Prescaler 1 */ + word PRS2 :1; /* ATD 0 Clock Prescaler 2 */ + word PRS3 :1; /* ATD 0 Clock Prescaler 3 */ + word PRS4 :1; /* ATD 0 Clock Prescaler 4 */ + word SMP0 :1; /* Sample Time Select 0 */ + word SMP1 :1; /* Sample Time Select 1 */ + word SRES8 :1; /* ATD 0 Resolution Select */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpPRS :5; + word grpSMP :2; + word grpSRES_8 :1; + } MergedBits; +} ATD0CTL45STR; +extern volatile ATD0CTL45STR _ATD0CTL45 @(REG_BASE + 0x00000084); +#define ATD0CTL45 _ATD0CTL45.Word +#define ATD0CTL45_CA _ATD0CTL45.Bits.CA +#define ATD0CTL45_CB _ATD0CTL45.Bits.CB +#define ATD0CTL45_CC _ATD0CTL45.Bits.CC +#define ATD0CTL45_MULT _ATD0CTL45.Bits.MULT +#define ATD0CTL45_SCAN _ATD0CTL45.Bits.SCAN +#define ATD0CTL45_DSGN _ATD0CTL45.Bits.DSGN +#define ATD0CTL45_DJM _ATD0CTL45.Bits.DJM +#define ATD0CTL45_PRS0 _ATD0CTL45.Bits.PRS0 +#define ATD0CTL45_PRS1 _ATD0CTL45.Bits.PRS1 +#define ATD0CTL45_PRS2 _ATD0CTL45.Bits.PRS2 +#define ATD0CTL45_PRS3 _ATD0CTL45.Bits.PRS3 +#define ATD0CTL45_PRS4 _ATD0CTL45.Bits.PRS4 +#define ATD0CTL45_SMP0 _ATD0CTL45.Bits.SMP0 +#define ATD0CTL45_SMP1 _ATD0CTL45.Bits.SMP1 +#define ATD0CTL45_SRES8 _ATD0CTL45.Bits.SRES8 +#define ATD0CTL45_PRS _ATD0CTL45.MergedBits.grpPRS +#define ATD0CTL45_SMP _ATD0CTL45.MergedBits.grpSMP + + +/*** ATD0DR0 - ATD 0 Conversion Result Register 0; 0x00000090 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD0DR0H - ATD 0 Conversion Result Register 0 High; 0x00000090 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } ATD0DR0HSTR; + #define ATD0DR0H _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Byte + #define ATD0DR0H_BIT8 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT8 + #define ATD0DR0H_BIT9 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT9 + #define ATD0DR0H_BIT10 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT10 + #define ATD0DR0H_BIT11 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT11 + #define ATD0DR0H_BIT12 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT12 + #define ATD0DR0H_BIT13 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT13 + #define ATD0DR0H_BIT14 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT14 + #define ATD0DR0H_BIT15 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT15 + #define ATD0DR0H_BIT_8 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.MergedBits.grpBIT_8 + #define ATD0DR0H_BIT ATD0DR0H_BIT_8 + + /*** ATD0DR0L - ATD 0 Conversion Result Register 0 Low; 0x00000091 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD0DR0LSTR; + #define ATD0DR0L _ATD0DR0.Overlap_STR.ATD0DR0LSTR.Byte + #define ATD0DR0L_BIT6 _ATD0DR0.Overlap_STR.ATD0DR0LSTR.Bits.BIT6 + #define ATD0DR0L_BIT7 _ATD0DR0.Overlap_STR.ATD0DR0LSTR.Bits.BIT7 + #define ATD0DR0L_BIT_6 _ATD0DR0.Overlap_STR.ATD0DR0LSTR.MergedBits.grpBIT_6 + #define ATD0DR0L_BIT ATD0DR0L_BIT_6 + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD0DR0STR; +extern volatile ATD0DR0STR _ATD0DR0 @(REG_BASE + 0x00000090); +#define ATD0DR0 _ATD0DR0.Word +#define ATD0DR0_BIT6 _ATD0DR0.Bits.BIT6 +#define ATD0DR0_BIT7 _ATD0DR0.Bits.BIT7 +#define ATD0DR0_BIT8 _ATD0DR0.Bits.BIT8 +#define ATD0DR0_BIT9 _ATD0DR0.Bits.BIT9 +#define ATD0DR0_BIT10 _ATD0DR0.Bits.BIT10 +#define ATD0DR0_BIT11 _ATD0DR0.Bits.BIT11 +#define ATD0DR0_BIT12 _ATD0DR0.Bits.BIT12 +#define ATD0DR0_BIT13 _ATD0DR0.Bits.BIT13 +#define ATD0DR0_BIT14 _ATD0DR0.Bits.BIT14 +#define ATD0DR0_BIT15 _ATD0DR0.Bits.BIT15 +#define ATD0DR0_BIT_6 _ATD0DR0.MergedBits.grpBIT_6 +#define ATD0DR0_BIT ATD0DR0_BIT_6 + + +/*** ATD0DR1 - ATD 0 Conversion Result Register 1; 0x00000092 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD0DR1H - ATD 0 Conversion Result Register 1 High; 0x00000092 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } ATD0DR1HSTR; + #define ATD0DR1H _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Byte + #define ATD0DR1H_BIT8 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT8 + #define ATD0DR1H_BIT9 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT9 + #define ATD0DR1H_BIT10 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT10 + #define ATD0DR1H_BIT11 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT11 + #define ATD0DR1H_BIT12 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT12 + #define ATD0DR1H_BIT13 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT13 + #define ATD0DR1H_BIT14 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT14 + #define ATD0DR1H_BIT15 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT15 + #define ATD0DR1H_BIT_8 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.MergedBits.grpBIT_8 + #define ATD0DR1H_BIT ATD0DR1H_BIT_8 + + /*** ATD0DR1L - ATD 0 Conversion Result Register 1 Low; 0x00000093 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD0DR1LSTR; + #define ATD0DR1L _ATD0DR1.Overlap_STR.ATD0DR1LSTR.Byte + #define ATD0DR1L_BIT6 _ATD0DR1.Overlap_STR.ATD0DR1LSTR.Bits.BIT6 + #define ATD0DR1L_BIT7 _ATD0DR1.Overlap_STR.ATD0DR1LSTR.Bits.BIT7 + #define ATD0DR1L_BIT_6 _ATD0DR1.Overlap_STR.ATD0DR1LSTR.MergedBits.grpBIT_6 + #define ATD0DR1L_BIT ATD0DR1L_BIT_6 + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD0DR1STR; +extern volatile ATD0DR1STR _ATD0DR1 @(REG_BASE + 0x00000092); +#define ATD0DR1 _ATD0DR1.Word +#define ATD0DR1_BIT6 _ATD0DR1.Bits.BIT6 +#define ATD0DR1_BIT7 _ATD0DR1.Bits.BIT7 +#define ATD0DR1_BIT8 _ATD0DR1.Bits.BIT8 +#define ATD0DR1_BIT9 _ATD0DR1.Bits.BIT9 +#define ATD0DR1_BIT10 _ATD0DR1.Bits.BIT10 +#define ATD0DR1_BIT11 _ATD0DR1.Bits.BIT11 +#define ATD0DR1_BIT12 _ATD0DR1.Bits.BIT12 +#define ATD0DR1_BIT13 _ATD0DR1.Bits.BIT13 +#define ATD0DR1_BIT14 _ATD0DR1.Bits.BIT14 +#define ATD0DR1_BIT15 _ATD0DR1.Bits.BIT15 +#define ATD0DR1_BIT_6 _ATD0DR1.MergedBits.grpBIT_6 +#define ATD0DR1_BIT ATD0DR1_BIT_6 + + +/*** ATD0DR2 - ATD 0 Conversion Result Register 2; 0x00000094 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD0DR2H - ATD 0 Conversion Result Register 2 High; 0x00000094 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } ATD0DR2HSTR; + #define ATD0DR2H _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Byte + #define ATD0DR2H_BIT8 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT8 + #define ATD0DR2H_BIT9 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT9 + #define ATD0DR2H_BIT10 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT10 + #define ATD0DR2H_BIT11 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT11 + #define ATD0DR2H_BIT12 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT12 + #define ATD0DR2H_BIT13 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT13 + #define ATD0DR2H_BIT14 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT14 + #define ATD0DR2H_BIT15 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT15 + #define ATD0DR2H_BIT_8 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.MergedBits.grpBIT_8 + #define ATD0DR2H_BIT ATD0DR2H_BIT_8 + + /*** ATD0DR2L - ATD 0 Conversion Result Register 2 Low; 0x00000095 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD0DR2LSTR; + #define ATD0DR2L _ATD0DR2.Overlap_STR.ATD0DR2LSTR.Byte + #define ATD0DR2L_BIT6 _ATD0DR2.Overlap_STR.ATD0DR2LSTR.Bits.BIT6 + #define ATD0DR2L_BIT7 _ATD0DR2.Overlap_STR.ATD0DR2LSTR.Bits.BIT7 + #define ATD0DR2L_BIT_6 _ATD0DR2.Overlap_STR.ATD0DR2LSTR.MergedBits.grpBIT_6 + #define ATD0DR2L_BIT ATD0DR2L_BIT_6 + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD0DR2STR; +extern volatile ATD0DR2STR _ATD0DR2 @(REG_BASE + 0x00000094); +#define ATD0DR2 _ATD0DR2.Word +#define ATD0DR2_BIT6 _ATD0DR2.Bits.BIT6 +#define ATD0DR2_BIT7 _ATD0DR2.Bits.BIT7 +#define ATD0DR2_BIT8 _ATD0DR2.Bits.BIT8 +#define ATD0DR2_BIT9 _ATD0DR2.Bits.BIT9 +#define ATD0DR2_BIT10 _ATD0DR2.Bits.BIT10 +#define ATD0DR2_BIT11 _ATD0DR2.Bits.BIT11 +#define ATD0DR2_BIT12 _ATD0DR2.Bits.BIT12 +#define ATD0DR2_BIT13 _ATD0DR2.Bits.BIT13 +#define ATD0DR2_BIT14 _ATD0DR2.Bits.BIT14 +#define ATD0DR2_BIT15 _ATD0DR2.Bits.BIT15 +#define ATD0DR2_BIT_6 _ATD0DR2.MergedBits.grpBIT_6 +#define ATD0DR2_BIT ATD0DR2_BIT_6 + + +/*** ATD0DR3 - ATD 0 Conversion Result Register 3; 0x00000096 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD0DR3H - ATD 0 Conversion Result Register 3 High; 0x00000096 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } ATD0DR3HSTR; + #define ATD0DR3H _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Byte + #define ATD0DR3H_BIT8 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT8 + #define ATD0DR3H_BIT9 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT9 + #define ATD0DR3H_BIT10 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT10 + #define ATD0DR3H_BIT11 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT11 + #define ATD0DR3H_BIT12 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT12 + #define ATD0DR3H_BIT13 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT13 + #define ATD0DR3H_BIT14 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT14 + #define ATD0DR3H_BIT15 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT15 + #define ATD0DR3H_BIT_8 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.MergedBits.grpBIT_8 + #define ATD0DR3H_BIT ATD0DR3H_BIT_8 + + /*** ATD0DR3L - ATD 0 Conversion Result Register 3 Low; 0x00000097 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD0DR3LSTR; + #define ATD0DR3L _ATD0DR3.Overlap_STR.ATD0DR3LSTR.Byte + #define ATD0DR3L_BIT6 _ATD0DR3.Overlap_STR.ATD0DR3LSTR.Bits.BIT6 + #define ATD0DR3L_BIT7 _ATD0DR3.Overlap_STR.ATD0DR3LSTR.Bits.BIT7 + #define ATD0DR3L_BIT_6 _ATD0DR3.Overlap_STR.ATD0DR3LSTR.MergedBits.grpBIT_6 + #define ATD0DR3L_BIT ATD0DR3L_BIT_6 + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD0DR3STR; +extern volatile ATD0DR3STR _ATD0DR3 @(REG_BASE + 0x00000096); +#define ATD0DR3 _ATD0DR3.Word +#define ATD0DR3_BIT6 _ATD0DR3.Bits.BIT6 +#define ATD0DR3_BIT7 _ATD0DR3.Bits.BIT7 +#define ATD0DR3_BIT8 _ATD0DR3.Bits.BIT8 +#define ATD0DR3_BIT9 _ATD0DR3.Bits.BIT9 +#define ATD0DR3_BIT10 _ATD0DR3.Bits.BIT10 +#define ATD0DR3_BIT11 _ATD0DR3.Bits.BIT11 +#define ATD0DR3_BIT12 _ATD0DR3.Bits.BIT12 +#define ATD0DR3_BIT13 _ATD0DR3.Bits.BIT13 +#define ATD0DR3_BIT14 _ATD0DR3.Bits.BIT14 +#define ATD0DR3_BIT15 _ATD0DR3.Bits.BIT15 +#define ATD0DR3_BIT_6 _ATD0DR3.MergedBits.grpBIT_6 +#define ATD0DR3_BIT ATD0DR3_BIT_6 + + +/*** ATD0DR4 - ATD 0 Conversion Result Register 4; 0x00000098 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD0DR4H - ATD 0 Conversion Result Register 4 High; 0x00000098 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } ATD0DR4HSTR; + #define ATD0DR4H _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Byte + #define ATD0DR4H_BIT8 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT8 + #define ATD0DR4H_BIT9 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT9 + #define ATD0DR4H_BIT10 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT10 + #define ATD0DR4H_BIT11 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT11 + #define ATD0DR4H_BIT12 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT12 + #define ATD0DR4H_BIT13 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT13 + #define ATD0DR4H_BIT14 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT14 + #define ATD0DR4H_BIT15 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT15 + #define ATD0DR4H_BIT_8 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.MergedBits.grpBIT_8 + #define ATD0DR4H_BIT ATD0DR4H_BIT_8 + + /*** ATD0DR4L - ATD 0 Conversion Result Register 4 Low; 0x00000099 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD0DR4LSTR; + #define ATD0DR4L _ATD0DR4.Overlap_STR.ATD0DR4LSTR.Byte + #define ATD0DR4L_BIT6 _ATD0DR4.Overlap_STR.ATD0DR4LSTR.Bits.BIT6 + #define ATD0DR4L_BIT7 _ATD0DR4.Overlap_STR.ATD0DR4LSTR.Bits.BIT7 + #define ATD0DR4L_BIT_6 _ATD0DR4.Overlap_STR.ATD0DR4LSTR.MergedBits.grpBIT_6 + #define ATD0DR4L_BIT ATD0DR4L_BIT_6 + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD0DR4STR; +extern volatile ATD0DR4STR _ATD0DR4 @(REG_BASE + 0x00000098); +#define ATD0DR4 _ATD0DR4.Word +#define ATD0DR4_BIT6 _ATD0DR4.Bits.BIT6 +#define ATD0DR4_BIT7 _ATD0DR4.Bits.BIT7 +#define ATD0DR4_BIT8 _ATD0DR4.Bits.BIT8 +#define ATD0DR4_BIT9 _ATD0DR4.Bits.BIT9 +#define ATD0DR4_BIT10 _ATD0DR4.Bits.BIT10 +#define ATD0DR4_BIT11 _ATD0DR4.Bits.BIT11 +#define ATD0DR4_BIT12 _ATD0DR4.Bits.BIT12 +#define ATD0DR4_BIT13 _ATD0DR4.Bits.BIT13 +#define ATD0DR4_BIT14 _ATD0DR4.Bits.BIT14 +#define ATD0DR4_BIT15 _ATD0DR4.Bits.BIT15 +#define ATD0DR4_BIT_6 _ATD0DR4.MergedBits.grpBIT_6 +#define ATD0DR4_BIT ATD0DR4_BIT_6 + + +/*** ATD0DR5 - ATD 0 Conversion Result Register 5; 0x0000009A ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD0DR5H - ATD 0 Conversion Result Register 5 High; 0x0000009A ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } ATD0DR5HSTR; + #define ATD0DR5H _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Byte + #define ATD0DR5H_BIT8 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT8 + #define ATD0DR5H_BIT9 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT9 + #define ATD0DR5H_BIT10 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT10 + #define ATD0DR5H_BIT11 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT11 + #define ATD0DR5H_BIT12 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT12 + #define ATD0DR5H_BIT13 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT13 + #define ATD0DR5H_BIT14 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT14 + #define ATD0DR5H_BIT15 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT15 + #define ATD0DR5H_BIT_8 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.MergedBits.grpBIT_8 + #define ATD0DR5H_BIT ATD0DR5H_BIT_8 + + /*** ATD0DR5L - ATD 0 Conversion Result Register 5 Low; 0x0000009B ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD0DR5LSTR; + #define ATD0DR5L _ATD0DR5.Overlap_STR.ATD0DR5LSTR.Byte + #define ATD0DR5L_BIT6 _ATD0DR5.Overlap_STR.ATD0DR5LSTR.Bits.BIT6 + #define ATD0DR5L_BIT7 _ATD0DR5.Overlap_STR.ATD0DR5LSTR.Bits.BIT7 + #define ATD0DR5L_BIT_6 _ATD0DR5.Overlap_STR.ATD0DR5LSTR.MergedBits.grpBIT_6 + #define ATD0DR5L_BIT ATD0DR5L_BIT_6 + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD0DR5STR; +extern volatile ATD0DR5STR _ATD0DR5 @(REG_BASE + 0x0000009A); +#define ATD0DR5 _ATD0DR5.Word +#define ATD0DR5_BIT6 _ATD0DR5.Bits.BIT6 +#define ATD0DR5_BIT7 _ATD0DR5.Bits.BIT7 +#define ATD0DR5_BIT8 _ATD0DR5.Bits.BIT8 +#define ATD0DR5_BIT9 _ATD0DR5.Bits.BIT9 +#define ATD0DR5_BIT10 _ATD0DR5.Bits.BIT10 +#define ATD0DR5_BIT11 _ATD0DR5.Bits.BIT11 +#define ATD0DR5_BIT12 _ATD0DR5.Bits.BIT12 +#define ATD0DR5_BIT13 _ATD0DR5.Bits.BIT13 +#define ATD0DR5_BIT14 _ATD0DR5.Bits.BIT14 +#define ATD0DR5_BIT15 _ATD0DR5.Bits.BIT15 +#define ATD0DR5_BIT_6 _ATD0DR5.MergedBits.grpBIT_6 +#define ATD0DR5_BIT ATD0DR5_BIT_6 + + +/*** ATD0DR6 - ATD 0 Conversion Result Register 6; 0x0000009C ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD0DR6H - ATD 0 Conversion Result Register 6 High; 0x0000009C ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } ATD0DR6HSTR; + #define ATD0DR6H _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Byte + #define ATD0DR6H_BIT8 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT8 + #define ATD0DR6H_BIT9 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT9 + #define ATD0DR6H_BIT10 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT10 + #define ATD0DR6H_BIT11 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT11 + #define ATD0DR6H_BIT12 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT12 + #define ATD0DR6H_BIT13 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT13 + #define ATD0DR6H_BIT14 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT14 + #define ATD0DR6H_BIT15 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT15 + #define ATD0DR6H_BIT_8 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.MergedBits.grpBIT_8 + #define ATD0DR6H_BIT ATD0DR6H_BIT_8 + + /*** ATD0DR6L - ATD 0 Conversion Result Register 6 Low; 0x0000009D ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD0DR6LSTR; + #define ATD0DR6L _ATD0DR6.Overlap_STR.ATD0DR6LSTR.Byte + #define ATD0DR6L_BIT6 _ATD0DR6.Overlap_STR.ATD0DR6LSTR.Bits.BIT6 + #define ATD0DR6L_BIT7 _ATD0DR6.Overlap_STR.ATD0DR6LSTR.Bits.BIT7 + #define ATD0DR6L_BIT_6 _ATD0DR6.Overlap_STR.ATD0DR6LSTR.MergedBits.grpBIT_6 + #define ATD0DR6L_BIT ATD0DR6L_BIT_6 + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD0DR6STR; +extern volatile ATD0DR6STR _ATD0DR6 @(REG_BASE + 0x0000009C); +#define ATD0DR6 _ATD0DR6.Word +#define ATD0DR6_BIT6 _ATD0DR6.Bits.BIT6 +#define ATD0DR6_BIT7 _ATD0DR6.Bits.BIT7 +#define ATD0DR6_BIT8 _ATD0DR6.Bits.BIT8 +#define ATD0DR6_BIT9 _ATD0DR6.Bits.BIT9 +#define ATD0DR6_BIT10 _ATD0DR6.Bits.BIT10 +#define ATD0DR6_BIT11 _ATD0DR6.Bits.BIT11 +#define ATD0DR6_BIT12 _ATD0DR6.Bits.BIT12 +#define ATD0DR6_BIT13 _ATD0DR6.Bits.BIT13 +#define ATD0DR6_BIT14 _ATD0DR6.Bits.BIT14 +#define ATD0DR6_BIT15 _ATD0DR6.Bits.BIT15 +#define ATD0DR6_BIT_6 _ATD0DR6.MergedBits.grpBIT_6 +#define ATD0DR6_BIT ATD0DR6_BIT_6 + + +/*** ATD0DR7 - ATD 0 Conversion Result Register 7; 0x0000009E ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD0DR7H - ATD 0 Conversion Result Register 7 High; 0x0000009E ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } ATD0DR7HSTR; + #define ATD0DR7H _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Byte + #define ATD0DR7H_BIT8 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT8 + #define ATD0DR7H_BIT9 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT9 + #define ATD0DR7H_BIT10 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT10 + #define ATD0DR7H_BIT11 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT11 + #define ATD0DR7H_BIT12 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT12 + #define ATD0DR7H_BIT13 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT13 + #define ATD0DR7H_BIT14 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT14 + #define ATD0DR7H_BIT15 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT15 + #define ATD0DR7H_BIT_8 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.MergedBits.grpBIT_8 + #define ATD0DR7H_BIT ATD0DR7H_BIT_8 + + /*** ATD0DR7L - ATD 0 Conversion Result Register 7 Low; 0x0000009F ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD0DR7LSTR; + #define ATD0DR7L _ATD0DR7.Overlap_STR.ATD0DR7LSTR.Byte + #define ATD0DR7L_BIT6 _ATD0DR7.Overlap_STR.ATD0DR7LSTR.Bits.BIT6 + #define ATD0DR7L_BIT7 _ATD0DR7.Overlap_STR.ATD0DR7LSTR.Bits.BIT7 + #define ATD0DR7L_BIT_6 _ATD0DR7.Overlap_STR.ATD0DR7LSTR.MergedBits.grpBIT_6 + #define ATD0DR7L_BIT ATD0DR7L_BIT_6 + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD0DR7STR; +extern volatile ATD0DR7STR _ATD0DR7 @(REG_BASE + 0x0000009E); +#define ATD0DR7 _ATD0DR7.Word +#define ATD0DR7_BIT6 _ATD0DR7.Bits.BIT6 +#define ATD0DR7_BIT7 _ATD0DR7.Bits.BIT7 +#define ATD0DR7_BIT8 _ATD0DR7.Bits.BIT8 +#define ATD0DR7_BIT9 _ATD0DR7.Bits.BIT9 +#define ATD0DR7_BIT10 _ATD0DR7.Bits.BIT10 +#define ATD0DR7_BIT11 _ATD0DR7.Bits.BIT11 +#define ATD0DR7_BIT12 _ATD0DR7.Bits.BIT12 +#define ATD0DR7_BIT13 _ATD0DR7.Bits.BIT13 +#define ATD0DR7_BIT14 _ATD0DR7.Bits.BIT14 +#define ATD0DR7_BIT15 _ATD0DR7.Bits.BIT15 +#define ATD0DR7_BIT_6 _ATD0DR7.MergedBits.grpBIT_6 +#define ATD0DR7_BIT ATD0DR7_BIT_6 + + +/*** PWMCNT01 - PWM Channel Counter 01 Register; 0x000000AC ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMCNT0 - PWM Channel Counter 0 Register; 0x000000AC ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMCNT0STR; + #define PWMCNT0 _PWMCNT01.Overlap_STR.PWMCNT0STR.Byte + #define PWMCNT0_BIT _PWMCNT01.Overlap_STR.PWMCNT0STR.MergedBits.grpBIT + + /*** PWMCNT1 - PWM Channel Counter 1 Register; 0x000000AD ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMCNT1STR; + #define PWMCNT1 _PWMCNT01.Overlap_STR.PWMCNT1STR.Byte + #define PWMCNT1_BIT _PWMCNT01.Overlap_STR.PWMCNT1STR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} PWMCNT01STR; +extern volatile PWMCNT01STR _PWMCNT01 @(REG_BASE + 0x000000AC); +#define PWMCNT01 _PWMCNT01.Word +#define PWMCNT01_BIT _PWMCNT01.MergedBits.grpBIT + + +/*** PWMCNT23 - PWM Channel Counter 23 Register; 0x000000AE ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMCNT2 - PWM Channel Counter 2 Register; 0x000000AE ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMCNT2STR; + #define PWMCNT2 _PWMCNT23.Overlap_STR.PWMCNT2STR.Byte + #define PWMCNT2_BIT _PWMCNT23.Overlap_STR.PWMCNT2STR.MergedBits.grpBIT + + /*** PWMCNT3 - PWM Channel Counter 3 Register; 0x000000AF ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMCNT3STR; + #define PWMCNT3 _PWMCNT23.Overlap_STR.PWMCNT3STR.Byte + #define PWMCNT3_BIT _PWMCNT23.Overlap_STR.PWMCNT3STR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} PWMCNT23STR; +extern volatile PWMCNT23STR _PWMCNT23 @(REG_BASE + 0x000000AE); +#define PWMCNT23 _PWMCNT23.Word +#define PWMCNT23_BIT _PWMCNT23.MergedBits.grpBIT + + +/*** PWMCNT45 - PWM Channel Counter 45 Register; 0x000000B0 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMCNT4 - PWM Channel Counter 4 Register; 0x000000B0 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMCNT4STR; + #define PWMCNT4 _PWMCNT45.Overlap_STR.PWMCNT4STR.Byte + #define PWMCNT4_BIT _PWMCNT45.Overlap_STR.PWMCNT4STR.MergedBits.grpBIT + + /*** PWMCNT5 - PWM Channel Counter 5 Register; 0x000000B1 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMCNT5STR; + #define PWMCNT5 _PWMCNT45.Overlap_STR.PWMCNT5STR.Byte + #define PWMCNT5_BIT _PWMCNT45.Overlap_STR.PWMCNT5STR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} PWMCNT45STR; +extern volatile PWMCNT45STR _PWMCNT45 @(REG_BASE + 0x000000B0); +#define PWMCNT45 _PWMCNT45.Word +#define PWMCNT45_BIT _PWMCNT45.MergedBits.grpBIT + + +/*** PWMCNT67 - PWM Channel Counter 67 Register; 0x000000B2 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMCNT6 - PWM Channel Counter 6 Register; 0x000000B2 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMCNT6STR; + #define PWMCNT6 _PWMCNT67.Overlap_STR.PWMCNT6STR.Byte + #define PWMCNT6_BIT _PWMCNT67.Overlap_STR.PWMCNT6STR.MergedBits.grpBIT + + /*** PWMCNT7 - PWM Channel Counter 7 Register; 0x000000B3 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMCNT7STR; + #define PWMCNT7 _PWMCNT67.Overlap_STR.PWMCNT7STR.Byte + #define PWMCNT7_BIT _PWMCNT67.Overlap_STR.PWMCNT7STR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} PWMCNT67STR; +extern volatile PWMCNT67STR _PWMCNT67 @(REG_BASE + 0x000000B2); +#define PWMCNT67 _PWMCNT67.Word +#define PWMCNT67_BIT _PWMCNT67.MergedBits.grpBIT + + +/*** PWMPER01 - PWM Channel Period 01 Register; 0x000000B4 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMPER0 - PWM Channel Period 0 Register; 0x000000B4 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMPER0STR; + #define PWMPER0 _PWMPER01.Overlap_STR.PWMPER0STR.Byte + #define PWMPER0_BIT _PWMPER01.Overlap_STR.PWMPER0STR.MergedBits.grpBIT + + /*** PWMPER1 - PWM Channel Period 1 Register; 0x000000B5 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMPER1STR; + #define PWMPER1 _PWMPER01.Overlap_STR.PWMPER1STR.Byte + #define PWMPER1_BIT _PWMPER01.Overlap_STR.PWMPER1STR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} PWMPER01STR; +extern volatile PWMPER01STR _PWMPER01 @(REG_BASE + 0x000000B4); +#define PWMPER01 _PWMPER01.Word +#define PWMPER01_BIT _PWMPER01.MergedBits.grpBIT + + +/*** PWMPER23 - PWM Channel Period 23 Register; 0x000000B6 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMPER2 - PWM Channel Period 2 Register; 0x000000B6 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMPER2STR; + #define PWMPER2 _PWMPER23.Overlap_STR.PWMPER2STR.Byte + #define PWMPER2_BIT _PWMPER23.Overlap_STR.PWMPER2STR.MergedBits.grpBIT + + /*** PWMPER3 - PWM Channel Period 3 Register; 0x000000B7 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMPER3STR; + #define PWMPER3 _PWMPER23.Overlap_STR.PWMPER3STR.Byte + #define PWMPER3_BIT _PWMPER23.Overlap_STR.PWMPER3STR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} PWMPER23STR; +extern volatile PWMPER23STR _PWMPER23 @(REG_BASE + 0x000000B6); +#define PWMPER23 _PWMPER23.Word +#define PWMPER23_BIT _PWMPER23.MergedBits.grpBIT + + +/*** PWMPER45 - PWM Channel Period 45 Register; 0x000000B8 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMPER4 - PWM Channel Period 4 Register; 0x000000B8 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMPER4STR; + #define PWMPER4 _PWMPER45.Overlap_STR.PWMPER4STR.Byte + #define PWMPER4_BIT _PWMPER45.Overlap_STR.PWMPER4STR.MergedBits.grpBIT + + /*** PWMPER5 - PWM Channel Period 5 Register; 0x000000B9 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMPER5STR; + #define PWMPER5 _PWMPER45.Overlap_STR.PWMPER5STR.Byte + #define PWMPER5_BIT _PWMPER45.Overlap_STR.PWMPER5STR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} PWMPER45STR; +extern volatile PWMPER45STR _PWMPER45 @(REG_BASE + 0x000000B8); +#define PWMPER45 _PWMPER45.Word +#define PWMPER45_BIT _PWMPER45.MergedBits.grpBIT + + +/*** PWMPER67 - PWM Channel Period 67 Register; 0x000000BA ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMPER6 - PWM Channel Period 6 Register; 0x000000BA ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMPER6STR; + #define PWMPER6 _PWMPER67.Overlap_STR.PWMPER6STR.Byte + #define PWMPER6_BIT _PWMPER67.Overlap_STR.PWMPER6STR.MergedBits.grpBIT + + /*** PWMPER7 - PWM Channel Period 7 Register; 0x000000BB ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMPER7STR; + #define PWMPER7 _PWMPER67.Overlap_STR.PWMPER7STR.Byte + #define PWMPER7_BIT _PWMPER67.Overlap_STR.PWMPER7STR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} PWMPER67STR; +extern volatile PWMPER67STR _PWMPER67 @(REG_BASE + 0x000000BA); +#define PWMPER67 _PWMPER67.Word +#define PWMPER67_BIT _PWMPER67.MergedBits.grpBIT + + +/*** PWMDTY01 - PWM Channel Duty 01 Register; 0x000000BC ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMDTY0 - PWM Channel Duty 0 Register; 0x000000BC ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMDTY0STR; + #define PWMDTY0 _PWMDTY01.Overlap_STR.PWMDTY0STR.Byte + #define PWMDTY0_BIT _PWMDTY01.Overlap_STR.PWMDTY0STR.MergedBits.grpBIT + + /*** PWMDTY1 - PWM Channel Duty 1 Register; 0x000000BD ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMDTY1STR; + #define PWMDTY1 _PWMDTY01.Overlap_STR.PWMDTY1STR.Byte + #define PWMDTY1_BIT _PWMDTY01.Overlap_STR.PWMDTY1STR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} PWMDTY01STR; +extern volatile PWMDTY01STR _PWMDTY01 @(REG_BASE + 0x000000BC); +#define PWMDTY01 _PWMDTY01.Word +#define PWMDTY01_BIT _PWMDTY01.MergedBits.grpBIT + + +/*** PWMDTY23 - PWM Channel Duty 23 Register; 0x000000BE ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMDTY2 - PWM Channel Duty 2 Register; 0x000000BE ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMDTY2STR; + #define PWMDTY2 _PWMDTY23.Overlap_STR.PWMDTY2STR.Byte + #define PWMDTY2_BIT _PWMDTY23.Overlap_STR.PWMDTY2STR.MergedBits.grpBIT + + /*** PWMDTY3 - PWM Channel Duty 3 Register; 0x000000BF ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMDTY3STR; + #define PWMDTY3 _PWMDTY23.Overlap_STR.PWMDTY3STR.Byte + #define PWMDTY3_BIT _PWMDTY23.Overlap_STR.PWMDTY3STR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} PWMDTY23STR; +extern volatile PWMDTY23STR _PWMDTY23 @(REG_BASE + 0x000000BE); +#define PWMDTY23 _PWMDTY23.Word +#define PWMDTY23_BIT _PWMDTY23.MergedBits.grpBIT + + +/*** PWMDTY45 - PWM Channel Duty 45 Register; 0x000000C0 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMDTY4 - PWM Channel Duty 4 Register; 0x000000C0 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMDTY4STR; + #define PWMDTY4 _PWMDTY45.Overlap_STR.PWMDTY4STR.Byte + #define PWMDTY4_BIT _PWMDTY45.Overlap_STR.PWMDTY4STR.MergedBits.grpBIT + + /*** PWMDTY5 - PWM Channel Duty 5 Register; 0x000000C1 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMDTY5STR; + #define PWMDTY5 _PWMDTY45.Overlap_STR.PWMDTY5STR.Byte + #define PWMDTY5_BIT _PWMDTY45.Overlap_STR.PWMDTY5STR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} PWMDTY45STR; +extern volatile PWMDTY45STR _PWMDTY45 @(REG_BASE + 0x000000C0); +#define PWMDTY45 _PWMDTY45.Word +#define PWMDTY45_BIT _PWMDTY45.MergedBits.grpBIT + + +/*** PWMDTY67 - PWM Channel Duty 67 Register; 0x000000C2 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMDTY6 - PWM Channel Duty 6 Register; 0x000000C2 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMDTY6STR; + #define PWMDTY6 _PWMDTY67.Overlap_STR.PWMDTY6STR.Byte + #define PWMDTY6_BIT _PWMDTY67.Overlap_STR.PWMDTY6STR.MergedBits.grpBIT + + /*** PWMDTY7 - PWM Channel Duty 7 Register; 0x000000C3 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMDTY7STR; + #define PWMDTY7 _PWMDTY67.Overlap_STR.PWMDTY7STR.Byte + #define PWMDTY7_BIT _PWMDTY67.Overlap_STR.PWMDTY7STR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} PWMDTY67STR; +extern volatile PWMDTY67STR _PWMDTY67 @(REG_BASE + 0x000000C2); +#define PWMDTY67 _PWMDTY67.Word +#define PWMDTY67_BIT _PWMDTY67.MergedBits.grpBIT + + +/*** SCI0BD - SCI 0 Baud Rate Register; 0x000000C8 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** SCI0BDH - SCI 0 Baud Rate Register High; 0x000000C8 ***/ + union { + byte Byte; + struct { + byte SBR8 :1; /* SCI 0 baud rate Bit 8 */ + byte SBR9 :1; /* SCI 0 baud rate Bit 9 */ + byte SBR10 :1; /* SCI 0 baud rate Bit 10 */ + byte SBR11 :1; /* SCI 0 baud rate Bit 11 */ + byte SBR12 :1; /* SCI 0 baud rate Bit 12 */ + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpSBR_8 :5; + byte :1; + byte :1; + byte :1; + } MergedBits; + } SCI0BDHSTR; + #define SCI0BDH _SCI0BD.Overlap_STR.SCI0BDHSTR.Byte + #define SCI0BDH_SBR8 _SCI0BD.Overlap_STR.SCI0BDHSTR.Bits.SBR8 + #define SCI0BDH_SBR9 _SCI0BD.Overlap_STR.SCI0BDHSTR.Bits.SBR9 + #define SCI0BDH_SBR10 _SCI0BD.Overlap_STR.SCI0BDHSTR.Bits.SBR10 + #define SCI0BDH_SBR11 _SCI0BD.Overlap_STR.SCI0BDHSTR.Bits.SBR11 + #define SCI0BDH_SBR12 _SCI0BD.Overlap_STR.SCI0BDHSTR.Bits.SBR12 + #define SCI0BDH_SBR_8 _SCI0BD.Overlap_STR.SCI0BDHSTR.MergedBits.grpSBR_8 + #define SCI0BDH_SBR SCI0BDH_SBR_8 + + /*** SCI0BDL - SCI 0 Baud Rate Register Low; 0x000000C9 ***/ + union { + byte Byte; + struct { + byte SBR0 :1; /* SCI 0 baud rate Bit 0 */ + byte SBR1 :1; /* SCI 0 baud rate Bit 1 */ + byte SBR2 :1; /* SCI 0 baud rate Bit 2 */ + byte SBR3 :1; /* SCI 0 baud rate Bit 3 */ + byte SBR4 :1; /* SCI 0 baud rate Bit 4 */ + byte SBR5 :1; /* SCI 0 baud rate Bit 5 */ + byte SBR6 :1; /* SCI 0 baud rate Bit 6 */ + byte SBR7 :1; /* SCI 0 baud rate Bit 7 */ + } Bits; + struct { + byte grpSBR :8; + } MergedBits; + } SCI0BDLSTR; + #define SCI0BDL _SCI0BD.Overlap_STR.SCI0BDLSTR.Byte + #define SCI0BDL_SBR0 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR0 + #define SCI0BDL_SBR1 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR1 + #define SCI0BDL_SBR2 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR2 + #define SCI0BDL_SBR3 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR3 + #define SCI0BDL_SBR4 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR4 + #define SCI0BDL_SBR5 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR5 + #define SCI0BDL_SBR6 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR6 + #define SCI0BDL_SBR7 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR7 + #define SCI0BDL_SBR _SCI0BD.Overlap_STR.SCI0BDLSTR.MergedBits.grpSBR + + } Overlap_STR; + + struct { + word SBR0 :1; /* SCI 0 baud rate Bit 0 */ + word SBR1 :1; /* SCI 0 baud rate Bit 1 */ + word SBR2 :1; /* SCI 0 baud rate Bit 2 */ + word SBR3 :1; /* SCI 0 baud rate Bit 3 */ + word SBR4 :1; /* SCI 0 baud rate Bit 4 */ + word SBR5 :1; /* SCI 0 baud rate Bit 5 */ + word SBR6 :1; /* SCI 0 baud rate Bit 6 */ + word SBR7 :1; /* SCI 0 baud rate Bit 7 */ + word SBR8 :1; /* SCI 0 baud rate Bit 8 */ + word SBR9 :1; /* SCI 0 baud rate Bit 9 */ + word SBR10 :1; /* SCI 0 baud rate Bit 10 */ + word SBR11 :1; /* SCI 0 baud rate Bit 11 */ + word SBR12 :1; /* SCI 0 baud rate Bit 12 */ + word :1; + word :1; + word :1; + } Bits; + struct { + word grpSBR :13; + word :1; + word :1; + word :1; + } MergedBits; +} SCI0BDSTR; +extern volatile SCI0BDSTR _SCI0BD @(REG_BASE + 0x000000C8); +#define SCI0BD _SCI0BD.Word +#define SCI0BD_SBR0 _SCI0BD.Bits.SBR0 +#define SCI0BD_SBR1 _SCI0BD.Bits.SBR1 +#define SCI0BD_SBR2 _SCI0BD.Bits.SBR2 +#define SCI0BD_SBR3 _SCI0BD.Bits.SBR3 +#define SCI0BD_SBR4 _SCI0BD.Bits.SBR4 +#define SCI0BD_SBR5 _SCI0BD.Bits.SBR5 +#define SCI0BD_SBR6 _SCI0BD.Bits.SBR6 +#define SCI0BD_SBR7 _SCI0BD.Bits.SBR7 +#define SCI0BD_SBR8 _SCI0BD.Bits.SBR8 +#define SCI0BD_SBR9 _SCI0BD.Bits.SBR9 +#define SCI0BD_SBR10 _SCI0BD.Bits.SBR10 +#define SCI0BD_SBR11 _SCI0BD.Bits.SBR11 +#define SCI0BD_SBR12 _SCI0BD.Bits.SBR12 +#define SCI0BD_SBR _SCI0BD.MergedBits.grpSBR + + +/*** SCI1BD - SCI 1 Baud Rate Register; 0x000000D0 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** SCI1BDH - SCI 1 Baud Rate Register High; 0x000000D0 ***/ + union { + byte Byte; + struct { + byte SBR8 :1; /* SCI 1 baud rate Bit 8 */ + byte SBR9 :1; /* SCI 1 baud rate Bit 9 */ + byte SBR10 :1; /* SCI 1 baud rate Bit 10 */ + byte SBR11 :1; /* SCI 1 baud rate Bit 11 */ + byte SBR12 :1; /* SCI 1 baud rate Bit 12 */ + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpSBR_8 :5; + byte :1; + byte :1; + byte :1; + } MergedBits; + } SCI1BDHSTR; + #define SCI1BDH _SCI1BD.Overlap_STR.SCI1BDHSTR.Byte + #define SCI1BDH_SBR8 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR8 + #define SCI1BDH_SBR9 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR9 + #define SCI1BDH_SBR10 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR10 + #define SCI1BDH_SBR11 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR11 + #define SCI1BDH_SBR12 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR12 + #define SCI1BDH_SBR_8 _SCI1BD.Overlap_STR.SCI1BDHSTR.MergedBits.grpSBR_8 + #define SCI1BDH_SBR SCI1BDH_SBR_8 + + /*** SCI1BDL - SCI 1 Baud Rate Register Low; 0x000000D1 ***/ + union { + byte Byte; + struct { + byte SBR0 :1; /* SCI 1 baud rate Bit 0 */ + byte SBR1 :1; /* SCI 1 baud rate Bit 1 */ + byte SBR2 :1; /* SCI 1 baud rate Bit 2 */ + byte SBR3 :1; /* SCI 1 baud rate Bit 3 */ + byte SBR4 :1; /* SCI 1 baud rate Bit 4 */ + byte SBR5 :1; /* SCI 1 baud rate Bit 5 */ + byte SBR6 :1; /* SCI 1 baud rate Bit 6 */ + byte SBR7 :1; /* SCI 1 baud rate Bit 7 */ + } Bits; + struct { + byte grpSBR :8; + } MergedBits; + } SCI1BDLSTR; + #define SCI1BDL _SCI1BD.Overlap_STR.SCI1BDLSTR.Byte + #define SCI1BDL_SBR0 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR0 + #define SCI1BDL_SBR1 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR1 + #define SCI1BDL_SBR2 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR2 + #define SCI1BDL_SBR3 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR3 + #define SCI1BDL_SBR4 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR4 + #define SCI1BDL_SBR5 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR5 + #define SCI1BDL_SBR6 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR6 + #define SCI1BDL_SBR7 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR7 + #define SCI1BDL_SBR _SCI1BD.Overlap_STR.SCI1BDLSTR.MergedBits.grpSBR + + } Overlap_STR; + + struct { + word SBR0 :1; /* SCI 1 baud rate Bit 0 */ + word SBR1 :1; /* SCI 1 baud rate Bit 1 */ + word SBR2 :1; /* SCI 1 baud rate Bit 2 */ + word SBR3 :1; /* SCI 1 baud rate Bit 3 */ + word SBR4 :1; /* SCI 1 baud rate Bit 4 */ + word SBR5 :1; /* SCI 1 baud rate Bit 5 */ + word SBR6 :1; /* SCI 1 baud rate Bit 6 */ + word SBR7 :1; /* SCI 1 baud rate Bit 7 */ + word SBR8 :1; /* SCI 1 baud rate Bit 8 */ + word SBR9 :1; /* SCI 1 baud rate Bit 9 */ + word SBR10 :1; /* SCI 1 baud rate Bit 10 */ + word SBR11 :1; /* SCI 1 baud rate Bit 11 */ + word SBR12 :1; /* SCI 1 baud rate Bit 12 */ + word :1; + word :1; + word :1; + } Bits; + struct { + word grpSBR :13; + word :1; + word :1; + word :1; + } MergedBits; +} SCI1BDSTR; +extern volatile SCI1BDSTR _SCI1BD @(REG_BASE + 0x000000D0); +#define SCI1BD _SCI1BD.Word +#define SCI1BD_SBR0 _SCI1BD.Bits.SBR0 +#define SCI1BD_SBR1 _SCI1BD.Bits.SBR1 +#define SCI1BD_SBR2 _SCI1BD.Bits.SBR2 +#define SCI1BD_SBR3 _SCI1BD.Bits.SBR3 +#define SCI1BD_SBR4 _SCI1BD.Bits.SBR4 +#define SCI1BD_SBR5 _SCI1BD.Bits.SBR5 +#define SCI1BD_SBR6 _SCI1BD.Bits.SBR6 +#define SCI1BD_SBR7 _SCI1BD.Bits.SBR7 +#define SCI1BD_SBR8 _SCI1BD.Bits.SBR8 +#define SCI1BD_SBR9 _SCI1BD.Bits.SBR9 +#define SCI1BD_SBR10 _SCI1BD.Bits.SBR10 +#define SCI1BD_SBR11 _SCI1BD.Bits.SBR11 +#define SCI1BD_SBR12 _SCI1BD.Bits.SBR12 +#define SCI1BD_SBR _SCI1BD.MergedBits.grpSBR + + +/*** ATD1CTL23 - ATD 1 Control Register 23; 0x00000122 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD1CTL2 - ATD 1 Control Register 2; 0x00000122 ***/ + union { + byte Byte; + struct { + byte ASCIF :1; /* ATD 1 Sequence Complete Interrupt Flag */ + byte ASCIE :1; /* ATD 1 Sequence Complete Interrupt Enable */ + byte ETRIGE :1; /* External Trigger Mode enable */ + byte ETRIGP :1; /* External Trigger Polarity */ + byte ETRIGLE :1; /* External Trigger Level/Edge control */ + byte AWAI :1; /* ATD 1 Wait Mode */ + byte AFFC :1; /* ATD 1 Fast Conversion Complete Flag Clear */ + byte ADPU :1; /* ATD 1 Disable / Power Down */ + } Bits; + } ATD1CTL2STR; + #define ATD1CTL2 _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Byte + #define ATD1CTL2_ASCIF _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ASCIF + #define ATD1CTL2_ASCIE _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ASCIE + #define ATD1CTL2_ETRIGE _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ETRIGE + #define ATD1CTL2_ETRIGP _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ETRIGP + #define ATD1CTL2_ETRIGLE _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ETRIGLE + #define ATD1CTL2_AWAI _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.AWAI + #define ATD1CTL2_AFFC _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.AFFC + #define ATD1CTL2_ADPU _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ADPU + + /*** ATD1CTL3 - ATD 1 Control Register 3; 0x00000123 ***/ + union { + byte Byte; + struct { + byte FRZ0 :1; /* Background Debug Freeze Enable */ + byte FRZ1 :1; /* Background Debug Freeze Enable */ + byte FIFO :1; /* Result Register FIFO Mode */ + byte S1C :1; /* Conversion Sequence Length 1 */ + byte S2C :1; /* Conversion Sequence Length 2 */ + byte S4C :1; /* Conversion Sequence Length 4 */ + byte S8C :1; /* Conversion Sequence Length 8 */ + byte :1; + } Bits; + struct { + byte grpFRZ :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; + } ATD1CTL3STR; + #define ATD1CTL3 _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Byte + #define ATD1CTL3_FRZ0 _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.FRZ0 + #define ATD1CTL3_FRZ1 _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.FRZ1 + #define ATD1CTL3_FIFO _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.FIFO + #define ATD1CTL3_S1C _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.S1C + #define ATD1CTL3_S2C _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.S2C + #define ATD1CTL3_S4C _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.S4C + #define ATD1CTL3_S8C _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.S8C + #define ATD1CTL3_FRZ _ATD1CTL23.Overlap_STR.ATD1CTL3STR.MergedBits.grpFRZ + + } Overlap_STR; + + struct { + word FRZ0 :1; /* Background Debug Freeze Enable */ + word FRZ1 :1; /* Background Debug Freeze Enable */ + word FIFO :1; /* Result Register FIFO Mode */ + word S1C :1; /* Conversion Sequence Length 1 */ + word S2C :1; /* Conversion Sequence Length 2 */ + word S4C :1; /* Conversion Sequence Length 4 */ + word S8C :1; /* Conversion Sequence Length 8 */ + word :1; + word ASCIF :1; /* ATD 1 Sequence Complete Interrupt Flag */ + word ASCIE :1; /* ATD 1 Sequence Complete Interrupt Enable */ + word ETRIGE :1; /* External Trigger Mode enable */ + word ETRIGP :1; /* External Trigger Polarity */ + word ETRIGLE :1; /* External Trigger Level/Edge control */ + word AWAI :1; /* ATD 1 Wait Mode */ + word AFFC :1; /* ATD 1 Fast Conversion Complete Flag Clear */ + word ADPU :1; /* ATD 1 Disable / Power Down */ + } Bits; + struct { + word grpFRZ :2; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + } MergedBits; +} ATD1CTL23STR; +extern volatile ATD1CTL23STR _ATD1CTL23 @(REG_BASE + 0x00000122); +#define ATD1CTL23 _ATD1CTL23.Word +#define ATD1CTL23_FRZ0 _ATD1CTL23.Bits.FRZ0 +#define ATD1CTL23_FRZ1 _ATD1CTL23.Bits.FRZ1 +#define ATD1CTL23_FIFO _ATD1CTL23.Bits.FIFO +#define ATD1CTL23_S1C _ATD1CTL23.Bits.S1C +#define ATD1CTL23_S2C _ATD1CTL23.Bits.S2C +#define ATD1CTL23_S4C _ATD1CTL23.Bits.S4C +#define ATD1CTL23_S8C _ATD1CTL23.Bits.S8C +#define ATD1CTL23_ASCIF _ATD1CTL23.Bits.ASCIF +#define ATD1CTL23_ASCIE _ATD1CTL23.Bits.ASCIE +#define ATD1CTL23_ETRIGE _ATD1CTL23.Bits.ETRIGE +#define ATD1CTL23_ETRIGP _ATD1CTL23.Bits.ETRIGP +#define ATD1CTL23_ETRIGLE _ATD1CTL23.Bits.ETRIGLE +#define ATD1CTL23_AWAI _ATD1CTL23.Bits.AWAI +#define ATD1CTL23_AFFC _ATD1CTL23.Bits.AFFC +#define ATD1CTL23_ADPU _ATD1CTL23.Bits.ADPU +#define ATD1CTL23_FRZ _ATD1CTL23.MergedBits.grpFRZ + + +/*** ATD1CTL45 - ATD 1 Control Register 45; 0x00000124 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD1CTL4 - ATD 1 Control Register 4; 0x00000124 ***/ + union { + byte Byte; + struct { + byte PRS0 :1; /* ATD 1 Clock Prescaler 0 */ + byte PRS1 :1; /* ATD 1 Clock Prescaler 1 */ + byte PRS2 :1; /* ATD 1 Clock Prescaler 2 */ + byte PRS3 :1; /* ATD 1 Clock Prescaler 3 */ + byte PRS4 :1; /* ATD 1 Clock Prescaler 4 */ + byte SMP0 :1; /* Sample Time Select 0 */ + byte SMP1 :1; /* Sample Time Select 1 */ + byte SRES8 :1; /* ATD 1 Resolution Select */ + } Bits; + struct { + byte grpPRS :5; + byte grpSMP :2; + byte grpSRES_8 :1; + } MergedBits; + } ATD1CTL4STR; + #define ATD1CTL4 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Byte + #define ATD1CTL4_PRS0 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.PRS0 + #define ATD1CTL4_PRS1 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.PRS1 + #define ATD1CTL4_PRS2 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.PRS2 + #define ATD1CTL4_PRS3 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.PRS3 + #define ATD1CTL4_PRS4 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.PRS4 + #define ATD1CTL4_SMP0 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.SMP0 + #define ATD1CTL4_SMP1 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.SMP1 + #define ATD1CTL4_SRES8 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.SRES8 + #define ATD1CTL4_PRS _ATD1CTL45.Overlap_STR.ATD1CTL4STR.MergedBits.grpPRS + #define ATD1CTL4_SMP _ATD1CTL45.Overlap_STR.ATD1CTL4STR.MergedBits.grpSMP + + /*** ATD1CTL5 - ATD 1 Control Register 5; 0x00000125 ***/ + union { + byte Byte; + struct { + byte CA :1; /* Analog Input Channel Select Code A */ + byte CB :1; /* Analog Input Channel Select Code B */ + byte CC :1; /* Analog Input Channel Select Code C */ + byte :1; + byte MULT :1; /* Multi-Channel Sample Mode */ + byte SCAN :1; /* Continuous Conversion Sequence Mode */ + byte DSGN :1; /* Signed/Unsigned Result Data Mode */ + byte DJM :1; /* Result Register Data Justification Mode */ + } Bits; + } ATD1CTL5STR; + #define ATD1CTL5 _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Byte + #define ATD1CTL5_CA _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.CA + #define ATD1CTL5_CB _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.CB + #define ATD1CTL5_CC _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.CC + #define ATD1CTL5_MULT _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.MULT + #define ATD1CTL5_SCAN _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.SCAN + #define ATD1CTL5_DSGN _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.DSGN + #define ATD1CTL5_DJM _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.DJM + + } Overlap_STR; + + struct { + word CA :1; /* Analog Input Channel Select Code A */ + word CB :1; /* Analog Input Channel Select Code B */ + word CC :1; /* Analog Input Channel Select Code C */ + word :1; + word MULT :1; /* Multi-Channel Sample Mode */ + word SCAN :1; /* Continuous Conversion Sequence Mode */ + word DSGN :1; /* Signed/Unsigned Result Data Mode */ + word DJM :1; /* Result Register Data Justification Mode */ + word PRS0 :1; /* ATD 1 Clock Prescaler 0 */ + word PRS1 :1; /* ATD 1 Clock Prescaler 1 */ + word PRS2 :1; /* ATD 1 Clock Prescaler 2 */ + word PRS3 :1; /* ATD 1 Clock Prescaler 3 */ + word PRS4 :1; /* ATD 1 Clock Prescaler 4 */ + word SMP0 :1; /* Sample Time Select 0 */ + word SMP1 :1; /* Sample Time Select 1 */ + word SRES8 :1; /* ATD 1 Resolution Select */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpPRS :5; + word grpSMP :2; + word grpSRES_8 :1; + } MergedBits; +} ATD1CTL45STR; +extern volatile ATD1CTL45STR _ATD1CTL45 @(REG_BASE + 0x00000124); +#define ATD1CTL45 _ATD1CTL45.Word +#define ATD1CTL45_CA _ATD1CTL45.Bits.CA +#define ATD1CTL45_CB _ATD1CTL45.Bits.CB +#define ATD1CTL45_CC _ATD1CTL45.Bits.CC +#define ATD1CTL45_MULT _ATD1CTL45.Bits.MULT +#define ATD1CTL45_SCAN _ATD1CTL45.Bits.SCAN +#define ATD1CTL45_DSGN _ATD1CTL45.Bits.DSGN +#define ATD1CTL45_DJM _ATD1CTL45.Bits.DJM +#define ATD1CTL45_PRS0 _ATD1CTL45.Bits.PRS0 +#define ATD1CTL45_PRS1 _ATD1CTL45.Bits.PRS1 +#define ATD1CTL45_PRS2 _ATD1CTL45.Bits.PRS2 +#define ATD1CTL45_PRS3 _ATD1CTL45.Bits.PRS3 +#define ATD1CTL45_PRS4 _ATD1CTL45.Bits.PRS4 +#define ATD1CTL45_SMP0 _ATD1CTL45.Bits.SMP0 +#define ATD1CTL45_SMP1 _ATD1CTL45.Bits.SMP1 +#define ATD1CTL45_SRES8 _ATD1CTL45.Bits.SRES8 +#define ATD1CTL45_PRS _ATD1CTL45.MergedBits.grpPRS +#define ATD1CTL45_SMP _ATD1CTL45.MergedBits.grpSMP + + +/*** ATD1DR0 - ATD 1 Conversion Result Register 0; 0x00000130 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD1DR0H - ATD 1 Conversion Result Register 0 High; 0x00000130 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } ATD1DR0HSTR; + #define ATD1DR0H _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Byte + #define ATD1DR0H_BIT8 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT8 + #define ATD1DR0H_BIT9 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT9 + #define ATD1DR0H_BIT10 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT10 + #define ATD1DR0H_BIT11 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT11 + #define ATD1DR0H_BIT12 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT12 + #define ATD1DR0H_BIT13 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT13 + #define ATD1DR0H_BIT14 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT14 + #define ATD1DR0H_BIT15 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT15 + #define ATD1DR0H_BIT_8 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.MergedBits.grpBIT_8 + #define ATD1DR0H_BIT ATD1DR0H_BIT_8 + + /*** ATD1DR0L - ATD 1 Conversion Result Register 0 Low; 0x00000131 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD1DR0LSTR; + #define ATD1DR0L _ATD1DR0.Overlap_STR.ATD1DR0LSTR.Byte + #define ATD1DR0L_BIT6 _ATD1DR0.Overlap_STR.ATD1DR0LSTR.Bits.BIT6 + #define ATD1DR0L_BIT7 _ATD1DR0.Overlap_STR.ATD1DR0LSTR.Bits.BIT7 + #define ATD1DR0L_BIT_6 _ATD1DR0.Overlap_STR.ATD1DR0LSTR.MergedBits.grpBIT_6 + #define ATD1DR0L_BIT ATD1DR0L_BIT_6 + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD1DR0STR; +extern volatile ATD1DR0STR _ATD1DR0 @(REG_BASE + 0x00000130); +#define ATD1DR0 _ATD1DR0.Word +#define ATD1DR0_BIT6 _ATD1DR0.Bits.BIT6 +#define ATD1DR0_BIT7 _ATD1DR0.Bits.BIT7 +#define ATD1DR0_BIT8 _ATD1DR0.Bits.BIT8 +#define ATD1DR0_BIT9 _ATD1DR0.Bits.BIT9 +#define ATD1DR0_BIT10 _ATD1DR0.Bits.BIT10 +#define ATD1DR0_BIT11 _ATD1DR0.Bits.BIT11 +#define ATD1DR0_BIT12 _ATD1DR0.Bits.BIT12 +#define ATD1DR0_BIT13 _ATD1DR0.Bits.BIT13 +#define ATD1DR0_BIT14 _ATD1DR0.Bits.BIT14 +#define ATD1DR0_BIT15 _ATD1DR0.Bits.BIT15 +#define ATD1DR0_BIT_6 _ATD1DR0.MergedBits.grpBIT_6 +#define ATD1DR0_BIT ATD1DR0_BIT_6 + + +/*** ATD1DR1 - ATD 1 Conversion Result Register 1; 0x00000132 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD1DR1H - ATD 1 Conversion Result Register 1 High; 0x00000132 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } ATD1DR1HSTR; + #define ATD1DR1H _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Byte + #define ATD1DR1H_BIT8 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT8 + #define ATD1DR1H_BIT9 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT9 + #define ATD1DR1H_BIT10 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT10 + #define ATD1DR1H_BIT11 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT11 + #define ATD1DR1H_BIT12 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT12 + #define ATD1DR1H_BIT13 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT13 + #define ATD1DR1H_BIT14 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT14 + #define ATD1DR1H_BIT15 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT15 + #define ATD1DR1H_BIT_8 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.MergedBits.grpBIT_8 + #define ATD1DR1H_BIT ATD1DR1H_BIT_8 + + /*** ATD1DR1L - ATD 1 Conversion Result Register 1 Low; 0x00000133 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD1DR1LSTR; + #define ATD1DR1L _ATD1DR1.Overlap_STR.ATD1DR1LSTR.Byte + #define ATD1DR1L_BIT6 _ATD1DR1.Overlap_STR.ATD1DR1LSTR.Bits.BIT6 + #define ATD1DR1L_BIT7 _ATD1DR1.Overlap_STR.ATD1DR1LSTR.Bits.BIT7 + #define ATD1DR1L_BIT_6 _ATD1DR1.Overlap_STR.ATD1DR1LSTR.MergedBits.grpBIT_6 + #define ATD1DR1L_BIT ATD1DR1L_BIT_6 + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD1DR1STR; +extern volatile ATD1DR1STR _ATD1DR1 @(REG_BASE + 0x00000132); +#define ATD1DR1 _ATD1DR1.Word +#define ATD1DR1_BIT6 _ATD1DR1.Bits.BIT6 +#define ATD1DR1_BIT7 _ATD1DR1.Bits.BIT7 +#define ATD1DR1_BIT8 _ATD1DR1.Bits.BIT8 +#define ATD1DR1_BIT9 _ATD1DR1.Bits.BIT9 +#define ATD1DR1_BIT10 _ATD1DR1.Bits.BIT10 +#define ATD1DR1_BIT11 _ATD1DR1.Bits.BIT11 +#define ATD1DR1_BIT12 _ATD1DR1.Bits.BIT12 +#define ATD1DR1_BIT13 _ATD1DR1.Bits.BIT13 +#define ATD1DR1_BIT14 _ATD1DR1.Bits.BIT14 +#define ATD1DR1_BIT15 _ATD1DR1.Bits.BIT15 +#define ATD1DR1_BIT_6 _ATD1DR1.MergedBits.grpBIT_6 +#define ATD1DR1_BIT ATD1DR1_BIT_6 + + +/*** ATD1DR2 - ATD 1 Conversion Result Register 2; 0x00000134 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD1DR2H - ATD 1 Conversion Result Register 2 High; 0x00000134 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } ATD1DR2HSTR; + #define ATD1DR2H _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Byte + #define ATD1DR2H_BIT8 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT8 + #define ATD1DR2H_BIT9 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT9 + #define ATD1DR2H_BIT10 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT10 + #define ATD1DR2H_BIT11 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT11 + #define ATD1DR2H_BIT12 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT12 + #define ATD1DR2H_BIT13 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT13 + #define ATD1DR2H_BIT14 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT14 + #define ATD1DR2H_BIT15 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT15 + #define ATD1DR2H_BIT_8 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.MergedBits.grpBIT_8 + #define ATD1DR2H_BIT ATD1DR2H_BIT_8 + + /*** ATD1DR2L - ATD 1 Conversion Result Register 2 Low; 0x00000135 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD1DR2LSTR; + #define ATD1DR2L _ATD1DR2.Overlap_STR.ATD1DR2LSTR.Byte + #define ATD1DR2L_BIT6 _ATD1DR2.Overlap_STR.ATD1DR2LSTR.Bits.BIT6 + #define ATD1DR2L_BIT7 _ATD1DR2.Overlap_STR.ATD1DR2LSTR.Bits.BIT7 + #define ATD1DR2L_BIT_6 _ATD1DR2.Overlap_STR.ATD1DR2LSTR.MergedBits.grpBIT_6 + #define ATD1DR2L_BIT ATD1DR2L_BIT_6 + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD1DR2STR; +extern volatile ATD1DR2STR _ATD1DR2 @(REG_BASE + 0x00000134); +#define ATD1DR2 _ATD1DR2.Word +#define ATD1DR2_BIT6 _ATD1DR2.Bits.BIT6 +#define ATD1DR2_BIT7 _ATD1DR2.Bits.BIT7 +#define ATD1DR2_BIT8 _ATD1DR2.Bits.BIT8 +#define ATD1DR2_BIT9 _ATD1DR2.Bits.BIT9 +#define ATD1DR2_BIT10 _ATD1DR2.Bits.BIT10 +#define ATD1DR2_BIT11 _ATD1DR2.Bits.BIT11 +#define ATD1DR2_BIT12 _ATD1DR2.Bits.BIT12 +#define ATD1DR2_BIT13 _ATD1DR2.Bits.BIT13 +#define ATD1DR2_BIT14 _ATD1DR2.Bits.BIT14 +#define ATD1DR2_BIT15 _ATD1DR2.Bits.BIT15 +#define ATD1DR2_BIT_6 _ATD1DR2.MergedBits.grpBIT_6 +#define ATD1DR2_BIT ATD1DR2_BIT_6 + + +/*** ATD1DR3 - ATD 1 Conversion Result Register 3; 0x00000136 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD1DR3H - ATD 1 Conversion Result Register 3 High; 0x00000136 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } ATD1DR3HSTR; + #define ATD1DR3H _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Byte + #define ATD1DR3H_BIT8 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT8 + #define ATD1DR3H_BIT9 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT9 + #define ATD1DR3H_BIT10 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT10 + #define ATD1DR3H_BIT11 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT11 + #define ATD1DR3H_BIT12 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT12 + #define ATD1DR3H_BIT13 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT13 + #define ATD1DR3H_BIT14 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT14 + #define ATD1DR3H_BIT15 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT15 + #define ATD1DR3H_BIT_8 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.MergedBits.grpBIT_8 + #define ATD1DR3H_BIT ATD1DR3H_BIT_8 + + /*** ATD1DR3L - ATD 1 Conversion Result Register 3 Low; 0x00000137 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD1DR3LSTR; + #define ATD1DR3L _ATD1DR3.Overlap_STR.ATD1DR3LSTR.Byte + #define ATD1DR3L_BIT6 _ATD1DR3.Overlap_STR.ATD1DR3LSTR.Bits.BIT6 + #define ATD1DR3L_BIT7 _ATD1DR3.Overlap_STR.ATD1DR3LSTR.Bits.BIT7 + #define ATD1DR3L_BIT_6 _ATD1DR3.Overlap_STR.ATD1DR3LSTR.MergedBits.grpBIT_6 + #define ATD1DR3L_BIT ATD1DR3L_BIT_6 + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD1DR3STR; +extern volatile ATD1DR3STR _ATD1DR3 @(REG_BASE + 0x00000136); +#define ATD1DR3 _ATD1DR3.Word +#define ATD1DR3_BIT6 _ATD1DR3.Bits.BIT6 +#define ATD1DR3_BIT7 _ATD1DR3.Bits.BIT7 +#define ATD1DR3_BIT8 _ATD1DR3.Bits.BIT8 +#define ATD1DR3_BIT9 _ATD1DR3.Bits.BIT9 +#define ATD1DR3_BIT10 _ATD1DR3.Bits.BIT10 +#define ATD1DR3_BIT11 _ATD1DR3.Bits.BIT11 +#define ATD1DR3_BIT12 _ATD1DR3.Bits.BIT12 +#define ATD1DR3_BIT13 _ATD1DR3.Bits.BIT13 +#define ATD1DR3_BIT14 _ATD1DR3.Bits.BIT14 +#define ATD1DR3_BIT15 _ATD1DR3.Bits.BIT15 +#define ATD1DR3_BIT_6 _ATD1DR3.MergedBits.grpBIT_6 +#define ATD1DR3_BIT ATD1DR3_BIT_6 + + +/*** ATD1DR4 - ATD 1 Conversion Result Register 4; 0x00000138 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD1DR4H - ATD 1 Conversion Result Register 4 High; 0x00000138 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } ATD1DR4HSTR; + #define ATD1DR4H _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Byte + #define ATD1DR4H_BIT8 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT8 + #define ATD1DR4H_BIT9 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT9 + #define ATD1DR4H_BIT10 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT10 + #define ATD1DR4H_BIT11 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT11 + #define ATD1DR4H_BIT12 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT12 + #define ATD1DR4H_BIT13 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT13 + #define ATD1DR4H_BIT14 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT14 + #define ATD1DR4H_BIT15 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT15 + #define ATD1DR4H_BIT_8 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.MergedBits.grpBIT_8 + #define ATD1DR4H_BIT ATD1DR4H_BIT_8 + + /*** ATD1DR4L - ATD 1 Conversion Result Register 4 Low; 0x00000139 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD1DR4LSTR; + #define ATD1DR4L _ATD1DR4.Overlap_STR.ATD1DR4LSTR.Byte + #define ATD1DR4L_BIT6 _ATD1DR4.Overlap_STR.ATD1DR4LSTR.Bits.BIT6 + #define ATD1DR4L_BIT7 _ATD1DR4.Overlap_STR.ATD1DR4LSTR.Bits.BIT7 + #define ATD1DR4L_BIT_6 _ATD1DR4.Overlap_STR.ATD1DR4LSTR.MergedBits.grpBIT_6 + #define ATD1DR4L_BIT ATD1DR4L_BIT_6 + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD1DR4STR; +extern volatile ATD1DR4STR _ATD1DR4 @(REG_BASE + 0x00000138); +#define ATD1DR4 _ATD1DR4.Word +#define ATD1DR4_BIT6 _ATD1DR4.Bits.BIT6 +#define ATD1DR4_BIT7 _ATD1DR4.Bits.BIT7 +#define ATD1DR4_BIT8 _ATD1DR4.Bits.BIT8 +#define ATD1DR4_BIT9 _ATD1DR4.Bits.BIT9 +#define ATD1DR4_BIT10 _ATD1DR4.Bits.BIT10 +#define ATD1DR4_BIT11 _ATD1DR4.Bits.BIT11 +#define ATD1DR4_BIT12 _ATD1DR4.Bits.BIT12 +#define ATD1DR4_BIT13 _ATD1DR4.Bits.BIT13 +#define ATD1DR4_BIT14 _ATD1DR4.Bits.BIT14 +#define ATD1DR4_BIT15 _ATD1DR4.Bits.BIT15 +#define ATD1DR4_BIT_6 _ATD1DR4.MergedBits.grpBIT_6 +#define ATD1DR4_BIT ATD1DR4_BIT_6 + + +/*** ATD1DR5 - ATD 1 Conversion Result Register 5; 0x0000013A ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD1DR5H - ATD 1 Conversion Result Register 5 High; 0x0000013A ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } ATD1DR5HSTR; + #define ATD1DR5H _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Byte + #define ATD1DR5H_BIT8 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT8 + #define ATD1DR5H_BIT9 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT9 + #define ATD1DR5H_BIT10 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT10 + #define ATD1DR5H_BIT11 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT11 + #define ATD1DR5H_BIT12 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT12 + #define ATD1DR5H_BIT13 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT13 + #define ATD1DR5H_BIT14 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT14 + #define ATD1DR5H_BIT15 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT15 + #define ATD1DR5H_BIT_8 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.MergedBits.grpBIT_8 + #define ATD1DR5H_BIT ATD1DR5H_BIT_8 + + /*** ATD1DR5L - ATD 1 Conversion Result Register 5 Low; 0x0000013B ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD1DR5LSTR; + #define ATD1DR5L _ATD1DR5.Overlap_STR.ATD1DR5LSTR.Byte + #define ATD1DR5L_BIT6 _ATD1DR5.Overlap_STR.ATD1DR5LSTR.Bits.BIT6 + #define ATD1DR5L_BIT7 _ATD1DR5.Overlap_STR.ATD1DR5LSTR.Bits.BIT7 + #define ATD1DR5L_BIT_6 _ATD1DR5.Overlap_STR.ATD1DR5LSTR.MergedBits.grpBIT_6 + #define ATD1DR5L_BIT ATD1DR5L_BIT_6 + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD1DR5STR; +extern volatile ATD1DR5STR _ATD1DR5 @(REG_BASE + 0x0000013A); +#define ATD1DR5 _ATD1DR5.Word +#define ATD1DR5_BIT6 _ATD1DR5.Bits.BIT6 +#define ATD1DR5_BIT7 _ATD1DR5.Bits.BIT7 +#define ATD1DR5_BIT8 _ATD1DR5.Bits.BIT8 +#define ATD1DR5_BIT9 _ATD1DR5.Bits.BIT9 +#define ATD1DR5_BIT10 _ATD1DR5.Bits.BIT10 +#define ATD1DR5_BIT11 _ATD1DR5.Bits.BIT11 +#define ATD1DR5_BIT12 _ATD1DR5.Bits.BIT12 +#define ATD1DR5_BIT13 _ATD1DR5.Bits.BIT13 +#define ATD1DR5_BIT14 _ATD1DR5.Bits.BIT14 +#define ATD1DR5_BIT15 _ATD1DR5.Bits.BIT15 +#define ATD1DR5_BIT_6 _ATD1DR5.MergedBits.grpBIT_6 +#define ATD1DR5_BIT ATD1DR5_BIT_6 + + +/*** ATD1DR6 - ATD 1 Conversion Result Register 6; 0x0000013C ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD1DR6H - ATD 1 Conversion Result Register 6 High; 0x0000013C ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } ATD1DR6HSTR; + #define ATD1DR6H _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Byte + #define ATD1DR6H_BIT8 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT8 + #define ATD1DR6H_BIT9 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT9 + #define ATD1DR6H_BIT10 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT10 + #define ATD1DR6H_BIT11 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT11 + #define ATD1DR6H_BIT12 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT12 + #define ATD1DR6H_BIT13 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT13 + #define ATD1DR6H_BIT14 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT14 + #define ATD1DR6H_BIT15 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT15 + #define ATD1DR6H_BIT_8 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.MergedBits.grpBIT_8 + #define ATD1DR6H_BIT ATD1DR6H_BIT_8 + + /*** ATD1DR6L - ATD 1 Conversion Result Register 6 Low; 0x0000013D ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD1DR6LSTR; + #define ATD1DR6L _ATD1DR6.Overlap_STR.ATD1DR6LSTR.Byte + #define ATD1DR6L_BIT6 _ATD1DR6.Overlap_STR.ATD1DR6LSTR.Bits.BIT6 + #define ATD1DR6L_BIT7 _ATD1DR6.Overlap_STR.ATD1DR6LSTR.Bits.BIT7 + #define ATD1DR6L_BIT_6 _ATD1DR6.Overlap_STR.ATD1DR6LSTR.MergedBits.grpBIT_6 + #define ATD1DR6L_BIT ATD1DR6L_BIT_6 + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD1DR6STR; +extern volatile ATD1DR6STR _ATD1DR6 @(REG_BASE + 0x0000013C); +#define ATD1DR6 _ATD1DR6.Word +#define ATD1DR6_BIT6 _ATD1DR6.Bits.BIT6 +#define ATD1DR6_BIT7 _ATD1DR6.Bits.BIT7 +#define ATD1DR6_BIT8 _ATD1DR6.Bits.BIT8 +#define ATD1DR6_BIT9 _ATD1DR6.Bits.BIT9 +#define ATD1DR6_BIT10 _ATD1DR6.Bits.BIT10 +#define ATD1DR6_BIT11 _ATD1DR6.Bits.BIT11 +#define ATD1DR6_BIT12 _ATD1DR6.Bits.BIT12 +#define ATD1DR6_BIT13 _ATD1DR6.Bits.BIT13 +#define ATD1DR6_BIT14 _ATD1DR6.Bits.BIT14 +#define ATD1DR6_BIT15 _ATD1DR6.Bits.BIT15 +#define ATD1DR6_BIT_6 _ATD1DR6.MergedBits.grpBIT_6 +#define ATD1DR6_BIT ATD1DR6_BIT_6 + + +/*** ATD1DR7 - ATD 1 Conversion Result Register 7; 0x0000013E ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD1DR7H - ATD 1 Conversion Result Register 7 High; 0x0000013E ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } ATD1DR7HSTR; + #define ATD1DR7H _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Byte + #define ATD1DR7H_BIT8 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT8 + #define ATD1DR7H_BIT9 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT9 + #define ATD1DR7H_BIT10 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT10 + #define ATD1DR7H_BIT11 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT11 + #define ATD1DR7H_BIT12 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT12 + #define ATD1DR7H_BIT13 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT13 + #define ATD1DR7H_BIT14 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT14 + #define ATD1DR7H_BIT15 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT15 + #define ATD1DR7H_BIT_8 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.MergedBits.grpBIT_8 + #define ATD1DR7H_BIT ATD1DR7H_BIT_8 + + /*** ATD1DR7L - ATD 1 Conversion Result Register 7 Low; 0x0000013F ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD1DR7LSTR; + #define ATD1DR7L _ATD1DR7.Overlap_STR.ATD1DR7LSTR.Byte + #define ATD1DR7L_BIT6 _ATD1DR7.Overlap_STR.ATD1DR7LSTR.Bits.BIT6 + #define ATD1DR7L_BIT7 _ATD1DR7.Overlap_STR.ATD1DR7LSTR.Bits.BIT7 + #define ATD1DR7L_BIT_6 _ATD1DR7.Overlap_STR.ATD1DR7LSTR.MergedBits.grpBIT_6 + #define ATD1DR7L_BIT ATD1DR7L_BIT_6 + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD1DR7STR; +extern volatile ATD1DR7STR _ATD1DR7 @(REG_BASE + 0x0000013E); +#define ATD1DR7 _ATD1DR7.Word +#define ATD1DR7_BIT6 _ATD1DR7.Bits.BIT6 +#define ATD1DR7_BIT7 _ATD1DR7.Bits.BIT7 +#define ATD1DR7_BIT8 _ATD1DR7.Bits.BIT8 +#define ATD1DR7_BIT9 _ATD1DR7.Bits.BIT9 +#define ATD1DR7_BIT10 _ATD1DR7.Bits.BIT10 +#define ATD1DR7_BIT11 _ATD1DR7.Bits.BIT11 +#define ATD1DR7_BIT12 _ATD1DR7.Bits.BIT12 +#define ATD1DR7_BIT13 _ATD1DR7.Bits.BIT13 +#define ATD1DR7_BIT14 _ATD1DR7.Bits.BIT14 +#define ATD1DR7_BIT15 _ATD1DR7.Bits.BIT15 +#define ATD1DR7_BIT_6 _ATD1DR7.MergedBits.grpBIT_6 +#define ATD1DR7_BIT ATD1DR7_BIT_6 + + +/*** PORTE - Port E Register; 0x00000008 ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* Port E Bit 0, XIRQ */ + byte BIT1 :1; /* Port E Bit 1, IRQ */ + byte BIT2 :1; /* Port E Bit 2, R/W */ + byte BIT3 :1; /* Port E Bit 3, LSTRB, TAGLO */ + byte BIT4 :1; /* Port E Bit 4, ECLK */ + byte BIT5 :1; /* Port E Bit 5, MODA, IPIPE0, RCRTO */ + byte BIT6 :1; /* Port E Bit 6, MODB, IPIPE1, SCGTO */ + byte BIT7 :1; /* Port E Bit 7, XCLKS, NOACC */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} PORTESTR; +extern volatile PORTESTR _PORTE @(REG_BASE + 0x00000008); +#define PORTE _PORTE.Byte +#define PORTE_BIT0 _PORTE.Bits.BIT0 +#define PORTE_BIT1 _PORTE.Bits.BIT1 +#define PORTE_BIT2 _PORTE.Bits.BIT2 +#define PORTE_BIT3 _PORTE.Bits.BIT3 +#define PORTE_BIT4 _PORTE.Bits.BIT4 +#define PORTE_BIT5 _PORTE.Bits.BIT5 +#define PORTE_BIT6 _PORTE.Bits.BIT6 +#define PORTE_BIT7 _PORTE.Bits.BIT7 +#define PORTE_BIT _PORTE.MergedBits.grpBIT + + +/*** DDRE - Port E Data Direction Register; 0x00000009 ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* Data Direction Port A Bit 0 */ + byte BIT1 :1; /* Data Direction Port A Bit 1 */ + byte BIT2 :1; /* Data Direction Port A Bit 2 */ + byte BIT3 :1; /* Data Direction Port A Bit 3 */ + byte BIT4 :1; /* Data Direction Port A Bit 4 */ + byte BIT5 :1; /* Data Direction Port A Bit 5 */ + byte BIT6 :1; /* Data Direction Port A Bit 6 */ + byte BIT7 :1; /* Data Direction Port A Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} DDRESTR; +extern volatile DDRESTR _DDRE @(REG_BASE + 0x00000009); +#define DDRE _DDRE.Byte +#define DDRE_BIT0 _DDRE.Bits.BIT0 +#define DDRE_BIT1 _DDRE.Bits.BIT1 +#define DDRE_BIT2 _DDRE.Bits.BIT2 +#define DDRE_BIT3 _DDRE.Bits.BIT3 +#define DDRE_BIT4 _DDRE.Bits.BIT4 +#define DDRE_BIT5 _DDRE.Bits.BIT5 +#define DDRE_BIT6 _DDRE.Bits.BIT6 +#define DDRE_BIT7 _DDRE.Bits.BIT7 +#define DDRE_BIT _DDRE.MergedBits.grpBIT + + +/*** PEAR - Port E Assignment Register; 0x0000000A ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte RDWE :1; /* Read / Write Enable */ + byte LSTRE :1; /* Low Strobe (LSTRB) Enable */ + byte NECLK :1; /* No External E Clock */ + byte PIPOE :1; /* Pipe Status Signal Output Enable */ + byte :1; + byte NOACCE :1; /* CPU No Access Output Enable */ + } Bits; +} PEARSTR; +extern volatile PEARSTR _PEAR @(REG_BASE + 0x0000000A); +#define PEAR _PEAR.Byte +#define PEAR_RDWE _PEAR.Bits.RDWE +#define PEAR_LSTRE _PEAR.Bits.LSTRE +#define PEAR_NECLK _PEAR.Bits.NECLK +#define PEAR_PIPOE _PEAR.Bits.PIPOE +#define PEAR_NOACCE _PEAR.Bits.NOACCE + + +/*** MODE - Mode Register; 0x0000000B ***/ +typedef union { + byte Byte; + struct { + byte EME :1; /* Emulate Port E */ + byte EMK :1; /* Emulate Port K */ + byte :1; + byte IVIS :1; /* Internal Visibility */ + byte :1; + byte MODA :1; /* Mode Select Bit A */ + byte MODB :1; /* Mode Select Bit B */ + byte MODC :1; /* Mode Select Bit C */ + } Bits; +} MODESTR; +extern volatile MODESTR _MODE @(REG_BASE + 0x0000000B); +#define MODE _MODE.Byte +#define MODE_EME _MODE.Bits.EME +#define MODE_EMK _MODE.Bits.EMK +#define MODE_IVIS _MODE.Bits.IVIS +#define MODE_MODA _MODE.Bits.MODA +#define MODE_MODB _MODE.Bits.MODB +#define MODE_MODC _MODE.Bits.MODC + + +/*** PUCR - Pull-Up Control Register; 0x0000000C ***/ +typedef union { + byte Byte; + struct { + byte PUPAE :1; /* Pull-Up Port A Enable */ + byte PUPBE :1; /* Pull-Up Port B Enable */ + byte :1; + byte :1; + byte PUPEE :1; /* Pull-Up Port E Enable */ + byte :1; + byte :1; + byte PUPKE :1; /* Pull-Up Port K Enable */ + } Bits; +} PUCRSTR; +extern volatile PUCRSTR _PUCR @(REG_BASE + 0x0000000C); +#define PUCR _PUCR.Byte +#define PUCR_PUPAE _PUCR.Bits.PUPAE +#define PUCR_PUPBE _PUCR.Bits.PUPBE +#define PUCR_PUPEE _PUCR.Bits.PUPEE +#define PUCR_PUPKE _PUCR.Bits.PUPKE + + +/*** RDRIV - Reduced Drive of I/O Lines; 0x0000000D ***/ +typedef union { + byte Byte; + struct { + byte RDPA :1; /* Reduced Drive of Port A */ + byte RDPB :1; /* Reduced Drive of Port B */ + byte :1; + byte :1; + byte RDPE :1; /* Reduced Drive of Port E */ + byte :1; + byte :1; + byte RDPK :1; /* Reduced Drive of Port K */ + } Bits; +} RDRIVSTR; +extern volatile RDRIVSTR _RDRIV @(REG_BASE + 0x0000000D); +#define RDRIV _RDRIV.Byte +#define RDRIV_RDPA _RDRIV.Bits.RDPA +#define RDRIV_RDPB _RDRIV.Bits.RDPB +#define RDRIV_RDPE _RDRIV.Bits.RDPE +#define RDRIV_RDPK _RDRIV.Bits.RDPK + + +/*** EBICTL - External Bus Interface Control; 0x0000000E ***/ +typedef union { + byte Byte; + struct { + byte ESTR :1; /* E Stretches */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} EBICTLSTR; +extern volatile EBICTLSTR _EBICTL @(REG_BASE + 0x0000000E); +#define EBICTL _EBICTL.Byte +#define EBICTL_ESTR _EBICTL.Bits.ESTR + + +/*** INITRM - Initialization of Internal RAM Position Register; 0x00000010 ***/ +typedef union { + byte Byte; + struct { + byte RAMHAL :1; /* Internal RAM map alignment */ + byte :1; + byte :1; + byte RAM11 :1; /* Internal RAM map position Bit 11 */ + byte RAM12 :1; /* Internal RAM map position Bit 12 */ + byte RAM13 :1; /* Internal RAM map position Bit 13 */ + byte RAM14 :1; /* Internal RAM map position Bit 14 */ + byte RAM15 :1; /* Internal RAM map position Bit 15 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte grpRAM_11 :5; + } MergedBits; +} INITRMSTR; +extern volatile INITRMSTR _INITRM @(REG_BASE + 0x00000010); +#define INITRM _INITRM.Byte +#define INITRM_RAMHAL _INITRM.Bits.RAMHAL +#define INITRM_RAM11 _INITRM.Bits.RAM11 +#define INITRM_RAM12 _INITRM.Bits.RAM12 +#define INITRM_RAM13 _INITRM.Bits.RAM13 +#define INITRM_RAM14 _INITRM.Bits.RAM14 +#define INITRM_RAM15 _INITRM.Bits.RAM15 +#define INITRM_RAM_11 _INITRM.MergedBits.grpRAM_11 +#define INITRM_RAM INITRM_RAM_11 + + +/*** INITRG - Initialization of Internal Register Position Register; 0x00000011 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte REG11 :1; /* Internal register map position REG11 */ + byte REG12 :1; /* Internal register map position REG12 */ + byte REG13 :1; /* Internal register map position REG13 */ + byte REG14 :1; /* Internal register map position REG14 */ + byte :1; + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte grpREG_11 :4; + byte :1; + } MergedBits; +} INITRGSTR; +extern volatile INITRGSTR _INITRG @(REG_BASE + 0x00000011); +#define INITRG _INITRG.Byte +#define INITRG_REG11 _INITRG.Bits.REG11 +#define INITRG_REG12 _INITRG.Bits.REG12 +#define INITRG_REG13 _INITRG.Bits.REG13 +#define INITRG_REG14 _INITRG.Bits.REG14 +#define INITRG_REG_11 _INITRG.MergedBits.grpREG_11 +#define INITRG_REG INITRG_REG_11 + + +/*** INITEE - Initialization of Internal EEPROM Position Register; 0x00000012 ***/ +typedef union { + byte Byte; + struct { + byte EEON :1; /* Internal EEPROM On */ + byte :1; + byte :1; + byte :1; + byte EE12 :1; /* Internal EEPROM map position Bit 12 */ + byte EE13 :1; /* Internal EEPROM map position Bit 13 */ + byte EE14 :1; /* Internal EEPROM map position Bit 14 */ + byte EE15 :1; /* Internal EEPROM map position Bit 15 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte grpEE_12 :4; + } MergedBits; +} INITEESTR; +extern volatile INITEESTR _INITEE @(REG_BASE + 0x00000012); +#define INITEE _INITEE.Byte +#define INITEE_EEON _INITEE.Bits.EEON +#define INITEE_EE12 _INITEE.Bits.EE12 +#define INITEE_EE13 _INITEE.Bits.EE13 +#define INITEE_EE14 _INITEE.Bits.EE14 +#define INITEE_EE15 _INITEE.Bits.EE15 +#define INITEE_EE_12 _INITEE.MergedBits.grpEE_12 +#define INITEE_EE INITEE_EE_12 + + +/*** MISC - Miscellaneous Mapping Control Register; 0x00000013 ***/ +typedef union { + byte Byte; + struct { + byte ROMON :1; /* Enable Flash EEPROM */ + byte ROMHM :1; /* Flash EEPROM only in second half of memory map */ + byte EXSTR0 :1; /* External Access Stretch Bit 0 */ + byte EXSTR1 :1; /* External Access Stretch Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte :1; + byte :1; + byte grpEXSTR :2; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} MISCSTR; +extern volatile MISCSTR _MISC @(REG_BASE + 0x00000013); +#define MISC _MISC.Byte +#define MISC_ROMON _MISC.Bits.ROMON +#define MISC_ROMHM _MISC.Bits.ROMHM +#define MISC_EXSTR0 _MISC.Bits.EXSTR0 +#define MISC_EXSTR1 _MISC.Bits.EXSTR1 +#define MISC_EXSTR _MISC.MergedBits.grpEXSTR + + +/*** MTST0 - MTST0; 0x00000014 ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* MTST0 Bit 0 */ + byte BIT1 :1; /* MTST0 Bit 1 */ + byte BIT2 :1; /* MTST0 Bit 2 */ + byte BIT3 :1; /* MTST0 Bit 3 */ + byte BIT4 :1; /* MTST0 Bit 4 */ + byte BIT5 :1; /* MTST0 Bit 5 */ + byte BIT6 :1; /* MTST0 Bit 6 */ + byte BIT7 :1; /* MTST0 Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} MTST0STR; +extern volatile MTST0STR _MTST0 @(REG_BASE + 0x00000014); +#define MTST0 _MTST0.Byte +#define MTST0_BIT0 _MTST0.Bits.BIT0 +#define MTST0_BIT1 _MTST0.Bits.BIT1 +#define MTST0_BIT2 _MTST0.Bits.BIT2 +#define MTST0_BIT3 _MTST0.Bits.BIT3 +#define MTST0_BIT4 _MTST0.Bits.BIT4 +#define MTST0_BIT5 _MTST0.Bits.BIT5 +#define MTST0_BIT6 _MTST0.Bits.BIT6 +#define MTST0_BIT7 _MTST0.Bits.BIT7 +#define MTST0_BIT _MTST0.MergedBits.grpBIT + + +/*** ITCR - Interrupt Test Control Register; 0x00000015 ***/ +typedef union { + byte Byte; + struct { + byte ADR0 :1; /* Test register select Bit 0 */ + byte ADR1 :1; /* Test register select Bit 1 */ + byte ADR2 :1; /* Test register select Bit 2 */ + byte ADR3 :1; /* Test register select Bit 3 */ + byte WRTINT :1; /* Write to the Interrupt Test Registers */ + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpADR :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} ITCRSTR; +extern volatile ITCRSTR _ITCR @(REG_BASE + 0x00000015); +#define ITCR _ITCR.Byte +#define ITCR_ADR0 _ITCR.Bits.ADR0 +#define ITCR_ADR1 _ITCR.Bits.ADR1 +#define ITCR_ADR2 _ITCR.Bits.ADR2 +#define ITCR_ADR3 _ITCR.Bits.ADR3 +#define ITCR_WRTINT _ITCR.Bits.WRTINT +#define ITCR_ADR _ITCR.MergedBits.grpADR + + +/*** ITEST - Interrupt Test Register; 0x00000016 ***/ +typedef union { + byte Byte; + struct { + byte INT0 :1; /* Interrupt Test Register Bit 0 */ + byte INT2 :1; /* Interrupt Test Register Bit 1 */ + byte INT4 :1; /* Interrupt Test Register Bit 2 */ + byte INT6 :1; /* Interrupt Test Register Bit 3 */ + byte INT8 :1; /* Interrupt Test Register Bit 4 */ + byte INTA :1; /* Interrupt Test Register Bit 5 */ + byte INTC :1; /* Interrupt Test Register Bit 6 */ + byte INTE :1; /* Interrupt Test Register Bit 7 */ + } Bits; +} ITESTSTR; +extern volatile ITESTSTR _ITEST @(REG_BASE + 0x00000016); +#define ITEST _ITEST.Byte +#define ITEST_INT0 _ITEST.Bits.INT0 +#define ITEST_INT2 _ITEST.Bits.INT2 +#define ITEST_INT4 _ITEST.Bits.INT4 +#define ITEST_INT6 _ITEST.Bits.INT6 +#define ITEST_INT8 _ITEST.Bits.INT8 +#define ITEST_INTA _ITEST.Bits.INTA +#define ITEST_INTC _ITEST.Bits.INTC +#define ITEST_INTE _ITEST.Bits.INTE + + +/*** MTST1 - MTST1; 0x00000017 ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* MTST1 Bit 0 */ + byte BIT1 :1; /* MTST1 Bit 1 */ + byte BIT2 :1; /* MTST1 Bit 2 */ + byte BIT3 :1; /* MTST1 Bit 3 */ + byte BIT4 :1; /* MTST1 Bit 4 */ + byte BIT5 :1; /* MTST1 Bit 5 */ + byte BIT6 :1; /* MTST1 Bit 6 */ + byte BIT7 :1; /* MTST1 Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} MTST1STR; +extern volatile MTST1STR _MTST1 @(REG_BASE + 0x00000017); +#define MTST1 _MTST1.Byte +#define MTST1_BIT0 _MTST1.Bits.BIT0 +#define MTST1_BIT1 _MTST1.Bits.BIT1 +#define MTST1_BIT2 _MTST1.Bits.BIT2 +#define MTST1_BIT3 _MTST1.Bits.BIT3 +#define MTST1_BIT4 _MTST1.Bits.BIT4 +#define MTST1_BIT5 _MTST1.Bits.BIT5 +#define MTST1_BIT6 _MTST1.Bits.BIT6 +#define MTST1_BIT7 _MTST1.Bits.BIT7 +#define MTST1_BIT _MTST1.MergedBits.grpBIT + + +/*** PARTIDH - Part ID Register High; 0x0000001A ***/ +typedef union { + byte Byte; + struct { + byte ID15 :1; /* Part ID Register Bit 15 */ + byte ID14 :1; /* Part ID Register Bit 14 */ + byte ID13 :1; /* Part ID Register Bit 13 */ + byte ID12 :1; /* Part ID Register Bit 12 */ + byte ID11 :1; /* Part ID Register Bit 11 */ + byte ID10 :1; /* Part ID Register Bit 10 */ + byte ID9 :1; /* Part ID Register Bit 9 */ + byte ID8 :1; /* Part ID Register Bit 8 */ + } Bits; +} PARTIDHSTR; +extern volatile PARTIDHSTR _PARTIDH @(REG_BASE + 0x0000001A); +#define PARTIDH _PARTIDH.Byte +#define PARTIDH_ID15 _PARTIDH.Bits.ID15 +#define PARTIDH_ID14 _PARTIDH.Bits.ID14 +#define PARTIDH_ID13 _PARTIDH.Bits.ID13 +#define PARTIDH_ID12 _PARTIDH.Bits.ID12 +#define PARTIDH_ID11 _PARTIDH.Bits.ID11 +#define PARTIDH_ID10 _PARTIDH.Bits.ID10 +#define PARTIDH_ID9 _PARTIDH.Bits.ID9 +#define PARTIDH_ID8 _PARTIDH.Bits.ID8 + + +/*** PARTIDL - Part ID Register Low; 0x0000001B ***/ +typedef union { + byte Byte; + struct { + byte ID0 :1; /* Part ID Register Bit 0 */ + byte ID1 :1; /* Part ID Register Bit 1 */ + byte ID2 :1; /* Part ID Register Bit 2 */ + byte ID3 :1; /* Part ID Register Bit 3 */ + byte ID4 :1; /* Part ID Register Bit 4 */ + byte ID5 :1; /* Part ID Register Bit 5 */ + byte ID6 :1; /* Part ID Register Bit 6 */ + byte ID7 :1; /* Part ID Register Bit 7 */ + } Bits; + struct { + byte grpID :8; + } MergedBits; +} PARTIDLSTR; +extern volatile PARTIDLSTR _PARTIDL @(REG_BASE + 0x0000001B); +#define PARTIDL _PARTIDL.Byte +#define PARTIDL_ID0 _PARTIDL.Bits.ID0 +#define PARTIDL_ID1 _PARTIDL.Bits.ID1 +#define PARTIDL_ID2 _PARTIDL.Bits.ID2 +#define PARTIDL_ID3 _PARTIDL.Bits.ID3 +#define PARTIDL_ID4 _PARTIDL.Bits.ID4 +#define PARTIDL_ID5 _PARTIDL.Bits.ID5 +#define PARTIDL_ID6 _PARTIDL.Bits.ID6 +#define PARTIDL_ID7 _PARTIDL.Bits.ID7 +#define PARTIDL_ID _PARTIDL.MergedBits.grpID + + +/*** MEMSIZ0 - Memory Size Register Zero; 0x0000001C ***/ +typedef union { + byte Byte; + struct { + byte ram_sw0 :1; /* Allocated RAM Memory Space Bit 0 */ + byte ram_sw1 :1; /* Allocated RAM Memory Space Bit 1 */ + byte ram_sw2 :1; /* Allocated RAM Memory Space Bit 2 */ + byte :1; + byte eep_sw0 :1; /* Allocated EEPROM Memory Space Bit 0 */ + byte eep_sw1 :1; /* Allocated EEPROM Memory Space Bit 1 */ + byte :1; + byte reg_sw0 :1; /* Allocated System Register Space */ + } Bits; + struct { + byte grpram_sw :3; + byte :1; + byte grpeep_sw :2; + byte :1; + byte grpreg_sw :1; + } MergedBits; +} MEMSIZ0STR; +extern volatile MEMSIZ0STR _MEMSIZ0 @(REG_BASE + 0x0000001C); +#define MEMSIZ0 _MEMSIZ0.Byte +#define MEMSIZ0_ram_sw0 _MEMSIZ0.Bits.ram_sw0 +#define MEMSIZ0_ram_sw1 _MEMSIZ0.Bits.ram_sw1 +#define MEMSIZ0_ram_sw2 _MEMSIZ0.Bits.ram_sw2 +#define MEMSIZ0_eep_sw0 _MEMSIZ0.Bits.eep_sw0 +#define MEMSIZ0_eep_sw1 _MEMSIZ0.Bits.eep_sw1 +#define MEMSIZ0_reg_sw0 _MEMSIZ0.Bits.reg_sw0 +#define MEMSIZ0_ram_sw _MEMSIZ0.MergedBits.grpram_sw +#define MEMSIZ0_eep_sw _MEMSIZ0.MergedBits.grpeep_sw + + +/*** MEMSIZ1 - Memory Size Register One; 0x0000001D ***/ +typedef union { + byte Byte; + struct { + byte pag_sw0 :1; /* Allocated Off-Chip Memory Options Bit 0 */ + byte pag_sw1 :1; /* Allocated Off-Chip Memory Options Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte rom_sw0 :1; /* Allocated Flash EEPROM/ROM Physical Memory Space Bit 0 */ + byte rom_sw1 :1; /* Allocated Flash EEPROM/ROM Physical Memory Space Bit 1 */ + } Bits; + struct { + byte grppag_sw :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte grprom_sw :2; + } MergedBits; +} MEMSIZ1STR; +extern volatile MEMSIZ1STR _MEMSIZ1 @(REG_BASE + 0x0000001D); +#define MEMSIZ1 _MEMSIZ1.Byte +#define MEMSIZ1_pag_sw0 _MEMSIZ1.Bits.pag_sw0 +#define MEMSIZ1_pag_sw1 _MEMSIZ1.Bits.pag_sw1 +#define MEMSIZ1_rom_sw0 _MEMSIZ1.Bits.rom_sw0 +#define MEMSIZ1_rom_sw1 _MEMSIZ1.Bits.rom_sw1 +#define MEMSIZ1_pag_sw _MEMSIZ1.MergedBits.grppag_sw +#define MEMSIZ1_rom_sw _MEMSIZ1.MergedBits.grprom_sw + + +/*** INTCR - Interrupt Control Register; 0x0000001E ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte IRQEN :1; /* External IRQ Enable */ + byte IRQE :1; /* IRQ Select Edge Sensitive Only */ + } Bits; +} INTCRSTR; +extern volatile INTCRSTR _INTCR @(REG_BASE + 0x0000001E); +#define INTCR _INTCR.Byte +#define INTCR_IRQEN _INTCR.Bits.IRQEN +#define INTCR_IRQE _INTCR.Bits.IRQE + + +/*** HPRIO - Highest Priority I Interrupt; 0x0000001F ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte PSEL1 :1; /* Highest Priority I Interrupt Bit 1 */ + byte PSEL2 :1; /* Highest Priority I Interrupt Bit 2 */ + byte PSEL3 :1; /* Highest Priority I Interrupt Bit 3 */ + byte PSEL4 :1; /* Highest Priority I Interrupt Bit 4 */ + byte PSEL5 :1; /* Highest Priority I Interrupt Bit 5 */ + byte PSEL6 :1; /* Highest Priority I Interrupt Bit 6 */ + byte PSEL7 :1; /* Highest Priority I Interrupt Bit 7 */ + } Bits; + struct { + byte :1; + byte grpPSEL_1 :7; + } MergedBits; +} HPRIOSTR; +extern volatile HPRIOSTR _HPRIO @(REG_BASE + 0x0000001F); +#define HPRIO _HPRIO.Byte +#define HPRIO_PSEL1 _HPRIO.Bits.PSEL1 +#define HPRIO_PSEL2 _HPRIO.Bits.PSEL2 +#define HPRIO_PSEL3 _HPRIO.Bits.PSEL3 +#define HPRIO_PSEL4 _HPRIO.Bits.PSEL4 +#define HPRIO_PSEL5 _HPRIO.Bits.PSEL5 +#define HPRIO_PSEL6 _HPRIO.Bits.PSEL6 +#define HPRIO_PSEL7 _HPRIO.Bits.PSEL7 +#define HPRIO_PSEL_1 _HPRIO.MergedBits.grpPSEL_1 +#define HPRIO_PSEL HPRIO_PSEL_1 + + +/*** BKPCT0 - Breakpoint Control Register 0; 0x00000028 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte BKTAG :1; /* Breakpoint on Tag */ + byte BKBDM :1; /* Breakpoint Background Debug Mode Enable */ + byte BKFULL :1; /* Full Breakpoint Mode Enable */ + byte BKEN :1; /* Breakpoint Enable */ + } Bits; +} BKPCT0STR; +extern volatile BKPCT0STR _BKPCT0 @(REG_BASE + 0x00000028); +#define BKPCT0 _BKPCT0.Byte +#define BKPCT0_BKTAG _BKPCT0.Bits.BKTAG +#define BKPCT0_BKBDM _BKPCT0.Bits.BKBDM +#define BKPCT0_BKFULL _BKPCT0.Bits.BKFULL +#define BKPCT0_BKEN _BKPCT0.Bits.BKEN + + +/*** BKPCT1 - Breakpoint Control Register 1; 0x00000029 ***/ +typedef union { + byte Byte; + struct { + byte BK1RW :1; /* R/W Compare Value 1 */ + byte BK1RWE :1; /* R/W Compare Enable 1 */ + byte BK0RW :1; /* R/W Compare Value 0 */ + byte BK0RWE :1; /* R/W Compare Enable 0 */ + byte BK1MBL :1; /* Breakpoint Mask Low Byte for Second Address */ + byte BK1MBH :1; /* Breakpoint Mask High Byte for Second Address */ + byte BK0MBL :1; /* Breakpoint Mask Low Byte for First Address */ + byte BK0MBH :1; /* Breakpoint Mask High Byte for First Address */ + } Bits; +} BKPCT1STR; +extern volatile BKPCT1STR _BKPCT1 @(REG_BASE + 0x00000029); +#define BKPCT1 _BKPCT1.Byte +#define BKPCT1_BK1RW _BKPCT1.Bits.BK1RW +#define BKPCT1_BK1RWE _BKPCT1.Bits.BK1RWE +#define BKPCT1_BK0RW _BKPCT1.Bits.BK0RW +#define BKPCT1_BK0RWE _BKPCT1.Bits.BK0RWE +#define BKPCT1_BK1MBL _BKPCT1.Bits.BK1MBL +#define BKPCT1_BK1MBH _BKPCT1.Bits.BK1MBH +#define BKPCT1_BK0MBL _BKPCT1.Bits.BK0MBL +#define BKPCT1_BK0MBH _BKPCT1.Bits.BK0MBH + + +/*** BKP0X - First Address Memory Expansion Breakpoint Register; 0x0000002A ***/ +typedef union { + byte Byte; + struct { + byte BK0V0 :1; /* First Address Breakpoint Expansion Address Value Bit 0 */ + byte BK0V1 :1; /* First Address Breakpoint Expansion Address Value Bit 1 */ + byte BK0V2 :1; /* First Address Breakpoint Expansion Address Value Bit 2 */ + byte BK0V3 :1; /* First Address Breakpoint Expansion Address Value Bit 3 */ + byte BK0V4 :1; /* First Address Breakpoint Expansion Address Value Bit 4 */ + byte BK0V5 :1; /* First Address Breakpoint Expansion Address Value Bit 5 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpBK0V :6; + byte :1; + byte :1; + } MergedBits; +} BKP0XSTR; +extern volatile BKP0XSTR _BKP0X @(REG_BASE + 0x0000002A); +#define BKP0X _BKP0X.Byte +#define BKP0X_BK0V0 _BKP0X.Bits.BK0V0 +#define BKP0X_BK0V1 _BKP0X.Bits.BK0V1 +#define BKP0X_BK0V2 _BKP0X.Bits.BK0V2 +#define BKP0X_BK0V3 _BKP0X.Bits.BK0V3 +#define BKP0X_BK0V4 _BKP0X.Bits.BK0V4 +#define BKP0X_BK0V5 _BKP0X.Bits.BK0V5 +#define BKP0X_BK0V _BKP0X.MergedBits.grpBK0V + + +/*** BKP0H - First Address High Byte Breakpoint Register; 0x0000002B ***/ +typedef union { + byte Byte; + struct { + byte BIT8 :1; /* First Address Breakpoint Register Bit 8 */ + byte BIT9 :1; /* First Address Breakpoint Register Bit 9 */ + byte BIT10 :1; /* First Address Breakpoint Register Bit 10 */ + byte BIT11 :1; /* First Address Breakpoint Register Bit 11 */ + byte BIT12 :1; /* First Address Breakpoint Register Bit 12 */ + byte BIT13 :1; /* First Address Breakpoint Register Bit 13 */ + byte BIT14 :1; /* First Address Breakpoint Register Bit 14 */ + byte BIT15 :1; /* First Address Breakpoint Register Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; +} BKP0HSTR; +extern volatile BKP0HSTR _BKP0H @(REG_BASE + 0x0000002B); +#define BKP0H _BKP0H.Byte +#define BKP0H_BIT8 _BKP0H.Bits.BIT8 +#define BKP0H_BIT9 _BKP0H.Bits.BIT9 +#define BKP0H_BIT10 _BKP0H.Bits.BIT10 +#define BKP0H_BIT11 _BKP0H.Bits.BIT11 +#define BKP0H_BIT12 _BKP0H.Bits.BIT12 +#define BKP0H_BIT13 _BKP0H.Bits.BIT13 +#define BKP0H_BIT14 _BKP0H.Bits.BIT14 +#define BKP0H_BIT15 _BKP0H.Bits.BIT15 +#define BKP0H_BIT_8 _BKP0H.MergedBits.grpBIT_8 +#define BKP0H_BIT BKP0H_BIT_8 + + +/*** BKP0L - First Address Low Byte Breakpoint Register; 0x0000002C ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* First Address Breakpoint Register Bit 0 */ + byte BIT1 :1; /* First Address Breakpoint Register Bit 1 */ + byte BIT2 :1; /* First Address Breakpoint Register Bit 2 */ + byte BIT3 :1; /* First Address Breakpoint Register Bit 3 */ + byte BIT4 :1; /* First Address Breakpoint Register Bit 4 */ + byte BIT5 :1; /* First Address Breakpoint Register Bit 5 */ + byte BIT6 :1; /* First Address Breakpoint Register Bit 6 */ + byte BIT7 :1; /* First Address Breakpoint Register Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} BKP0LSTR; +extern volatile BKP0LSTR _BKP0L @(REG_BASE + 0x0000002C); +#define BKP0L _BKP0L.Byte +#define BKP0L_BIT0 _BKP0L.Bits.BIT0 +#define BKP0L_BIT1 _BKP0L.Bits.BIT1 +#define BKP0L_BIT2 _BKP0L.Bits.BIT2 +#define BKP0L_BIT3 _BKP0L.Bits.BIT3 +#define BKP0L_BIT4 _BKP0L.Bits.BIT4 +#define BKP0L_BIT5 _BKP0L.Bits.BIT5 +#define BKP0L_BIT6 _BKP0L.Bits.BIT6 +#define BKP0L_BIT7 _BKP0L.Bits.BIT7 +#define BKP0L_BIT _BKP0L.MergedBits.grpBIT + + +/*** BKP1X - Second Address Memory Expansion Breakpoint Register; 0x0000002D ***/ +typedef union { + byte Byte; + struct { + byte BK1V0 :1; /* Second Address Breakpoint Expansion Address Value Bit 0 */ + byte BK1V1 :1; /* Second Address Breakpoint Expansion Address Value Bit 1 */ + byte BK1V2 :1; /* Second Address Breakpoint Expansion Address Value Bit 2 */ + byte BK1V3 :1; /* Second Address Breakpoint Expansion Address Value Bit 3 */ + byte BK1V4 :1; /* Second Address Breakpoint Expansion Address Value Bit 4 */ + byte BK1V5 :1; /* Second Address Breakpoint Expansion Address Value Bit 5 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpBK1V :6; + byte :1; + byte :1; + } MergedBits; +} BKP1XSTR; +extern volatile BKP1XSTR _BKP1X @(REG_BASE + 0x0000002D); +#define BKP1X _BKP1X.Byte +#define BKP1X_BK1V0 _BKP1X.Bits.BK1V0 +#define BKP1X_BK1V1 _BKP1X.Bits.BK1V1 +#define BKP1X_BK1V2 _BKP1X.Bits.BK1V2 +#define BKP1X_BK1V3 _BKP1X.Bits.BK1V3 +#define BKP1X_BK1V4 _BKP1X.Bits.BK1V4 +#define BKP1X_BK1V5 _BKP1X.Bits.BK1V5 +#define BKP1X_BK1V _BKP1X.MergedBits.grpBK1V + + +/*** BKP1H - Data (Second Address) High Byte Breakpoint Register; 0x0000002E ***/ +typedef union { + byte Byte; + struct { + byte BIT8 :1; /* Data (Second Address) Breakpoint Register Bit 8 */ + byte BIT9 :1; /* Data (Second Address) Breakpoint Register Bit 9 */ + byte BIT10 :1; /* Data (Second Address) Breakpoint Register Bit 10 */ + byte BIT11 :1; /* Data (Second Address) Breakpoint Register Bit 11 */ + byte BIT12 :1; /* Data (Second Address) Breakpoint Register Bit 12 */ + byte BIT13 :1; /* Data (Second Address) Breakpoint Register Bit 13 */ + byte BIT14 :1; /* Data (Second Address) Breakpoint Register Bit 14 */ + byte BIT15 :1; /* Data (Second Address) Breakpoint Register Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; +} BKP1HSTR; +extern volatile BKP1HSTR _BKP1H @(REG_BASE + 0x0000002E); +#define BKP1H _BKP1H.Byte +#define BKP1H_BIT8 _BKP1H.Bits.BIT8 +#define BKP1H_BIT9 _BKP1H.Bits.BIT9 +#define BKP1H_BIT10 _BKP1H.Bits.BIT10 +#define BKP1H_BIT11 _BKP1H.Bits.BIT11 +#define BKP1H_BIT12 _BKP1H.Bits.BIT12 +#define BKP1H_BIT13 _BKP1H.Bits.BIT13 +#define BKP1H_BIT14 _BKP1H.Bits.BIT14 +#define BKP1H_BIT15 _BKP1H.Bits.BIT15 +#define BKP1H_BIT_8 _BKP1H.MergedBits.grpBIT_8 +#define BKP1H_BIT BKP1H_BIT_8 + + +/*** BKP1L - Data (Second Address) Low Byte Breakpoint Register; 0x0000002F ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* Data (Second Address) Breakpoint Register Bit 0 */ + byte BIT1 :1; /* Data (Second Address) Breakpoint Register Bit 1 */ + byte BIT2 :1; /* Data (Second Address) Breakpoint Register Bit 2 */ + byte BIT3 :1; /* Data (Second Address) Breakpoint Register Bit 3 */ + byte BIT4 :1; /* Data (Second Address) Breakpoint Register Bit 4 */ + byte BIT5 :1; /* Data (Second Address) Breakpoint Register Bit 5 */ + byte BIT6 :1; /* Data (Second Address) Breakpoint Register Bit 6 */ + byte BIT7 :1; /* Data (Second Address) Breakpoint Register Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} BKP1LSTR; +extern volatile BKP1LSTR _BKP1L @(REG_BASE + 0x0000002F); +#define BKP1L _BKP1L.Byte +#define BKP1L_BIT0 _BKP1L.Bits.BIT0 +#define BKP1L_BIT1 _BKP1L.Bits.BIT1 +#define BKP1L_BIT2 _BKP1L.Bits.BIT2 +#define BKP1L_BIT3 _BKP1L.Bits.BIT3 +#define BKP1L_BIT4 _BKP1L.Bits.BIT4 +#define BKP1L_BIT5 _BKP1L.Bits.BIT5 +#define BKP1L_BIT6 _BKP1L.Bits.BIT6 +#define BKP1L_BIT7 _BKP1L.Bits.BIT7 +#define BKP1L_BIT _BKP1L.MergedBits.grpBIT + + +/*** PPAGE - Page Index Register; 0x00000030 ***/ +typedef union { + byte Byte; + struct { + byte PIX0 :1; /* Page Index Register Bit 0 */ + byte PIX1 :1; /* Page Index Register Bit 1 */ + byte PIX2 :1; /* Page Index Register Bit 2 */ + byte PIX3 :1; /* Page Index Register Bit 3 */ + byte PIX4 :1; /* Page Index Register Bit 4 */ + byte PIX5 :1; /* Page Index Register Bit 5 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpPIX :6; + byte :1; + byte :1; + } MergedBits; +} PPAGESTR; +extern volatile PPAGESTR _PPAGE @(REG_BASE + 0x00000030); +#define PPAGE _PPAGE.Byte +#define PPAGE_PIX0 _PPAGE.Bits.PIX0 +#define PPAGE_PIX1 _PPAGE.Bits.PIX1 +#define PPAGE_PIX2 _PPAGE.Bits.PIX2 +#define PPAGE_PIX3 _PPAGE.Bits.PIX3 +#define PPAGE_PIX4 _PPAGE.Bits.PIX4 +#define PPAGE_PIX5 _PPAGE.Bits.PIX5 +#define PPAGE_PIX _PPAGE.MergedBits.grpPIX + + +/*** PORTK - Port K Data Register; 0x00000032 ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* Port K Bit 0 */ + byte BIT1 :1; /* Port K Bit 1 */ + byte BIT2 :1; /* Port K Bit 2 */ + byte BIT3 :1; /* Port K Bit 3 */ + byte BIT4 :1; /* Port K Bit 4 */ + byte BIT5 :1; /* Port K Bit 5 */ + byte :1; + byte BIT7 :1; /* Port K Bit 7 */ + } Bits; + struct { + byte grpBIT :6; + byte :1; + byte grpBIT_7 :1; + } MergedBits; +} PORTKSTR; +extern volatile PORTKSTR _PORTK @(REG_BASE + 0x00000032); +#define PORTK _PORTK.Byte +#define PORTK_BIT0 _PORTK.Bits.BIT0 +#define PORTK_BIT1 _PORTK.Bits.BIT1 +#define PORTK_BIT2 _PORTK.Bits.BIT2 +#define PORTK_BIT3 _PORTK.Bits.BIT3 +#define PORTK_BIT4 _PORTK.Bits.BIT4 +#define PORTK_BIT5 _PORTK.Bits.BIT5 +#define PORTK_BIT7 _PORTK.Bits.BIT7 +#define PORTK_BIT _PORTK.MergedBits.grpBIT + + +/*** DDRK - Port K Data Direction Register; 0x00000033 ***/ +typedef union { + byte Byte; + struct { + byte DDK0 :1; /* Port K Data Direction Bit 0 */ + byte DDK1 :1; /* Port K Data Direction Bit 1 */ + byte DDK2 :1; /* Port K Data Direction Bit 2 */ + byte DDK3 :1; /* Port K Data Direction Bit 3 */ + byte DDK4 :1; /* Port K Data Direction Bit 4 */ + byte DDK5 :1; /* Port K Data Direction Bit 5 */ + byte :1; + byte DDK7 :1; /* Port K Data Direction Bit 7 */ + } Bits; + struct { + byte grpDDK :6; + byte :1; + byte grpDDK_7 :1; + } MergedBits; +} DDRKSTR; +extern volatile DDRKSTR _DDRK @(REG_BASE + 0x00000033); +#define DDRK _DDRK.Byte +#define DDRK_DDK0 _DDRK.Bits.DDK0 +#define DDRK_DDK1 _DDRK.Bits.DDK1 +#define DDRK_DDK2 _DDRK.Bits.DDK2 +#define DDRK_DDK3 _DDRK.Bits.DDK3 +#define DDRK_DDK4 _DDRK.Bits.DDK4 +#define DDRK_DDK5 _DDRK.Bits.DDK5 +#define DDRK_DDK7 _DDRK.Bits.DDK7 +#define DDRK_DDK _DDRK.MergedBits.grpDDK + + +/*** SYNR - CRG Synthesizer Register; 0x00000034 ***/ +typedef union { + byte Byte; + struct { + byte SYN0 :1; /* CRG Synthesizer Bit 0 */ + byte SYN1 :1; /* CRG Synthesizer Bit 1 */ + byte SYN2 :1; /* CRG Synthesizer Bit 2 */ + byte SYN3 :1; /* CRG Synthesizer Bit 3 */ + byte SYN4 :1; /* CRG Synthesizer Bit 4 */ + byte SYN5 :1; /* CRG Synthesizer Bit 5 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpSYN :6; + byte :1; + byte :1; + } MergedBits; +} SYNRSTR; +extern volatile SYNRSTR _SYNR @(REG_BASE + 0x00000034); +#define SYNR _SYNR.Byte +#define SYNR_SYN0 _SYNR.Bits.SYN0 +#define SYNR_SYN1 _SYNR.Bits.SYN1 +#define SYNR_SYN2 _SYNR.Bits.SYN2 +#define SYNR_SYN3 _SYNR.Bits.SYN3 +#define SYNR_SYN4 _SYNR.Bits.SYN4 +#define SYNR_SYN5 _SYNR.Bits.SYN5 +#define SYNR_SYN _SYNR.MergedBits.grpSYN + + +/*** REFDV - CRG Reference Divider Register; 0x00000035 ***/ +typedef union { + byte Byte; + struct { + byte REFDV0 :1; /* CRG Reference Divider Bit 0 */ + byte REFDV1 :1; /* CRG Reference Divider Bit 1 */ + byte REFDV2 :1; /* CRG Reference Divider Bit 2 */ + byte REFDV3 :1; /* CRG Reference Divider Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpREFDV :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} REFDVSTR; +extern volatile REFDVSTR _REFDV @(REG_BASE + 0x00000035); +#define REFDV _REFDV.Byte +#define REFDV_REFDV0 _REFDV.Bits.REFDV0 +#define REFDV_REFDV1 _REFDV.Bits.REFDV1 +#define REFDV_REFDV2 _REFDV.Bits.REFDV2 +#define REFDV_REFDV3 _REFDV.Bits.REFDV3 +#define REFDV_REFDV _REFDV.MergedBits.grpREFDV + + +/*** CTFLG - CRG Test Flags Register; 0x00000036 ***/ +typedef union { + byte Byte; + struct { + byte TOUT0 :1; /* CRG Test Flags Bit 0 */ + byte TOUT1 :1; /* CRG Test Flags Bit 1 */ + byte TOUT2 :1; /* CRG Test Flags Bit 2 */ + byte TOUT3 :1; /* CRG Test Flags Bit 3 */ + byte TOUT4 :1; /* CRG Test Flags Bit 4 */ + byte TOUT5 :1; /* CRG Test Flags Bit 5 */ + byte TOUT6 :1; /* CRG Test Flags Bit 6 */ + byte TOUT7 :1; /* CRG Test Flags Bit 7 */ + } Bits; + struct { + byte grpTOUT :8; + } MergedBits; +} CTFLGSTR; +extern volatile CTFLGSTR _CTFLG @(REG_BASE + 0x00000036); +#define CTFLG _CTFLG.Byte +#define CTFLG_TOUT0 _CTFLG.Bits.TOUT0 +#define CTFLG_TOUT1 _CTFLG.Bits.TOUT1 +#define CTFLG_TOUT2 _CTFLG.Bits.TOUT2 +#define CTFLG_TOUT3 _CTFLG.Bits.TOUT3 +#define CTFLG_TOUT4 _CTFLG.Bits.TOUT4 +#define CTFLG_TOUT5 _CTFLG.Bits.TOUT5 +#define CTFLG_TOUT6 _CTFLG.Bits.TOUT6 +#define CTFLG_TOUT7 _CTFLG.Bits.TOUT7 +#define CTFLG_TOUT _CTFLG.MergedBits.grpTOUT + + +/*** CRGFLG - CRG Flags Register; 0x00000037 ***/ +typedef union { + byte Byte; + struct { + byte SCM :1; /* Self-clock mode Status */ + byte SCMIF :1; /* Self-clock mode Interrupt Flag */ + byte TRACK :1; /* Track Status */ + byte LOCK :1; /* Lock Status */ + byte LOCKIF :1; /* PLL Lock Interrupt Flag */ + byte :1; + byte PORF :1; /* Power on Reset Flag */ + byte RTIF :1; /* Real Time Interrupt Flag */ + } Bits; +} CRGFLGSTR; +extern volatile CRGFLGSTR _CRGFLG @(REG_BASE + 0x00000037); +#define CRGFLG _CRGFLG.Byte +#define CRGFLG_SCM _CRGFLG.Bits.SCM +#define CRGFLG_SCMIF _CRGFLG.Bits.SCMIF +#define CRGFLG_TRACK _CRGFLG.Bits.TRACK +#define CRGFLG_LOCK _CRGFLG.Bits.LOCK +#define CRGFLG_LOCKIF _CRGFLG.Bits.LOCKIF +#define CRGFLG_PORF _CRGFLG.Bits.PORF +#define CRGFLG_RTIF _CRGFLG.Bits.RTIF + + +/*** CRGINT - CRG Interrupt Enable Register; 0x00000038 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte SCMIE :1; /* Self-clock mode Interrupt Enable */ + byte :1; + byte :1; + byte LOCKIE :1; /* Lock Interrupt Enable */ + byte :1; + byte :1; + byte RTIE :1; /* Real Time Interrupt Enable */ + } Bits; +} CRGINTSTR; +extern volatile CRGINTSTR _CRGINT @(REG_BASE + 0x00000038); +#define CRGINT _CRGINT.Byte +#define CRGINT_SCMIE _CRGINT.Bits.SCMIE +#define CRGINT_LOCKIE _CRGINT.Bits.LOCKIE +#define CRGINT_RTIE _CRGINT.Bits.RTIE + + +/*** CLKSEL - CRG Clock Select Register; 0x00000039 ***/ +typedef union { + byte Byte; + struct { + byte COPWAI :1; /* COP stops in WAIT mode */ + byte RTIWAI :1; /* RTI stops in WAIT mode */ + byte CWAI :1; /* CLK24 and CLK23 stop in WAIT mode */ + byte PLLWAI :1; /* PLL stops in WAIT mode */ + byte ROAWAI :1; /* Reduced Oscillator Amplitude in WAIT mode */ + byte SYSWAI :1; /* System clocks stop in WAIT mode */ + byte PSTP :1; /* Pseudo Stop */ + byte PLLSEL :1; /* PLL selected for system clock */ + } Bits; +} CLKSELSTR; +extern volatile CLKSELSTR _CLKSEL @(REG_BASE + 0x00000039); +#define CLKSEL _CLKSEL.Byte +#define CLKSEL_COPWAI _CLKSEL.Bits.COPWAI +#define CLKSEL_RTIWAI _CLKSEL.Bits.RTIWAI +#define CLKSEL_CWAI _CLKSEL.Bits.CWAI +#define CLKSEL_PLLWAI _CLKSEL.Bits.PLLWAI +#define CLKSEL_ROAWAI _CLKSEL.Bits.ROAWAI +#define CLKSEL_SYSWAI _CLKSEL.Bits.SYSWAI +#define CLKSEL_PSTP _CLKSEL.Bits.PSTP +#define CLKSEL_PLLSEL _CLKSEL.Bits.PLLSEL + + +/*** PLLCTL - CRG PLL Control Register; 0x0000003A ***/ +typedef union { + byte Byte; + struct { + byte SCME :1; /* Self-clock mode enable */ + byte :1; + byte :1; + byte :1; + byte ACQ :1; /* Acquisition */ + byte AUTO :1; /* Automatic Bandwidth Control */ + byte PLLON :1; /* Phase Lock Loop On */ + byte CME :1; /* Crystal Monitor Enable */ + } Bits; +} PLLCTLSTR; +extern volatile PLLCTLSTR _PLLCTL @(REG_BASE + 0x0000003A); +#define PLLCTL _PLLCTL.Byte +#define PLLCTL_SCME _PLLCTL.Bits.SCME +#define PLLCTL_ACQ _PLLCTL.Bits.ACQ +#define PLLCTL_AUTO _PLLCTL.Bits.AUTO +#define PLLCTL_PLLON _PLLCTL.Bits.PLLON +#define PLLCTL_CME _PLLCTL.Bits.CME + + +/*** RTICTL - CRG RTI Control Register; 0x0000003B ***/ +typedef union { + byte Byte; + struct { + byte RTR0 :1; /* Real Time Interrupt Modulus Counter Select */ + byte RTR1 :1; /* Real Time Interrupt Modulus Counter Select */ + byte RTR2 :1; /* Real Time Interrupt Modulus Counter Select */ + byte RTR3 :1; /* Real Time Interrupt Modulus Counter Select */ + byte RTR4 :1; /* Real Time Interrupt Prescale Rate Select */ + byte RTR5 :1; /* Real Time Interrupt Prescale Rate Select */ + byte RTR6 :1; /* Real Time Interrupt Prescale Rate Select */ + byte :1; + } Bits; + struct { + byte grpRTR :7; + byte :1; + } MergedBits; +} RTICTLSTR; +extern volatile RTICTLSTR _RTICTL @(REG_BASE + 0x0000003B); +#define RTICTL _RTICTL.Byte +#define RTICTL_RTR0 _RTICTL.Bits.RTR0 +#define RTICTL_RTR1 _RTICTL.Bits.RTR1 +#define RTICTL_RTR2 _RTICTL.Bits.RTR2 +#define RTICTL_RTR3 _RTICTL.Bits.RTR3 +#define RTICTL_RTR4 _RTICTL.Bits.RTR4 +#define RTICTL_RTR5 _RTICTL.Bits.RTR5 +#define RTICTL_RTR6 _RTICTL.Bits.RTR6 +#define RTICTL_RTR _RTICTL.MergedBits.grpRTR + + +/*** COPCTL - CRG COP Control Register; 0x0000003C ***/ +typedef union { + byte Byte; + struct { + byte CR0 :1; /* COP Watchdog Timer Rate select Bit 0 */ + byte CR1 :1; /* COP Watchdog Timer Rate select Bit 1 */ + byte CR2 :1; /* COP Watchdog Timer Rate select Bit 2 */ + byte :1; + byte :1; + byte :1; + byte RSBCK :1; /* COP and RTI stop in Active BDM mode Bit */ + byte WCOP :1; /* Window COP mode */ + } Bits; + struct { + byte grpCR :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} COPCTLSTR; +extern volatile COPCTLSTR _COPCTL @(REG_BASE + 0x0000003C); +#define COPCTL _COPCTL.Byte +#define COPCTL_CR0 _COPCTL.Bits.CR0 +#define COPCTL_CR1 _COPCTL.Bits.CR1 +#define COPCTL_CR2 _COPCTL.Bits.CR2 +#define COPCTL_RSBCK _COPCTL.Bits.RSBCK +#define COPCTL_WCOP _COPCTL.Bits.WCOP +#define COPCTL_CR _COPCTL.MergedBits.grpCR + + +/*** FORBYP - Crg force and bypass test register; 0x0000003D ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* Bit 0 */ + byte BIT1 :1; /* Bit 1 */ + byte BIT2 :1; /* Bit 2 */ + byte BIT3 :1; /* Bit 3 */ + byte BIT4 :1; /* Bit 4 */ + byte BIT5 :1; /* Bit 5 */ + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} FORBYPSTR; +extern volatile FORBYPSTR _FORBYP @(REG_BASE + 0x0000003D); +#define FORBYP _FORBYP.Byte +#define FORBYP_BIT0 _FORBYP.Bits.BIT0 +#define FORBYP_BIT1 _FORBYP.Bits.BIT1 +#define FORBYP_BIT2 _FORBYP.Bits.BIT2 +#define FORBYP_BIT3 _FORBYP.Bits.BIT3 +#define FORBYP_BIT4 _FORBYP.Bits.BIT4 +#define FORBYP_BIT5 _FORBYP.Bits.BIT5 +#define FORBYP_BIT6 _FORBYP.Bits.BIT6 +#define FORBYP_BIT7 _FORBYP.Bits.BIT7 +#define FORBYP_BIT _FORBYP.MergedBits.grpBIT + + +/*** CTCTL - CRG Test Control Register; 0x0000003E ***/ +typedef union { + byte Byte; + struct { + byte TCTL0 :1; /* CRG Test Control Bit 0 */ + byte TCTL1 :1; /* CRG Test Control Bit 1 */ + byte TCTL2 :1; /* CRG Test Control Bit 2 */ + byte TCTL3 :1; /* CRG Test Control Bit 3 */ + byte TCTL4 :1; /* CRG Test Control Bit 4 */ + byte TCTL5 :1; /* CRG Test Control Bit 5 */ + byte TCTL6 :1; /* CRG Test Control Bit 6 */ + byte TCTL7 :1; /* CRG Test Control Bit 7 */ + } Bits; + struct { + byte grpTCTL :8; + } MergedBits; +} CTCTLSTR; +extern volatile CTCTLSTR _CTCTL @(REG_BASE + 0x0000003E); +#define CTCTL _CTCTL.Byte +#define CTCTL_TCTL0 _CTCTL.Bits.TCTL0 +#define CTCTL_TCTL1 _CTCTL.Bits.TCTL1 +#define CTCTL_TCTL2 _CTCTL.Bits.TCTL2 +#define CTCTL_TCTL3 _CTCTL.Bits.TCTL3 +#define CTCTL_TCTL4 _CTCTL.Bits.TCTL4 +#define CTCTL_TCTL5 _CTCTL.Bits.TCTL5 +#define CTCTL_TCTL6 _CTCTL.Bits.TCTL6 +#define CTCTL_TCTL7 _CTCTL.Bits.TCTL7 +#define CTCTL_TCTL _CTCTL.MergedBits.grpTCTL + + +/*** ARMCOP - CRG COP Timer Arm/Reset Register; 0x0000003F ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* CRG COP Timer Arm/Reset Bit 0 */ + byte BIT1 :1; /* CRG COP Timer Arm/Reset Bit 1 */ + byte BIT2 :1; /* CRG COP Timer Arm/Reset Bit 2 */ + byte BIT3 :1; /* CRG COP Timer Arm/Reset Bit 3 */ + byte BIT4 :1; /* CRG COP Timer Arm/Reset Bit 4 */ + byte BIT5 :1; /* CRG COP Timer Arm/Reset Bit 5 */ + byte BIT6 :1; /* CRG COP Timer Arm/Reset Bit 6 */ + byte BIT7 :1; /* CRG COP Timer Arm/Reset Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} ARMCOPSTR; +extern volatile ARMCOPSTR _ARMCOP @(REG_BASE + 0x0000003F); +#define ARMCOP _ARMCOP.Byte +#define ARMCOP_BIT0 _ARMCOP.Bits.BIT0 +#define ARMCOP_BIT1 _ARMCOP.Bits.BIT1 +#define ARMCOP_BIT2 _ARMCOP.Bits.BIT2 +#define ARMCOP_BIT3 _ARMCOP.Bits.BIT3 +#define ARMCOP_BIT4 _ARMCOP.Bits.BIT4 +#define ARMCOP_BIT5 _ARMCOP.Bits.BIT5 +#define ARMCOP_BIT6 _ARMCOP.Bits.BIT6 +#define ARMCOP_BIT7 _ARMCOP.Bits.BIT7 +#define ARMCOP_BIT _ARMCOP.MergedBits.grpBIT + + +/*** TIOS - Timer Input Capture/Output Compare Select; 0x00000040 ***/ +typedef union { + byte Byte; + struct { + byte IOS0 :1; /* Input Capture or Output Compare Channel Configuration Bit 0 */ + byte IOS1 :1; /* Input Capture or Output Compare Channel Configuration Bit 1 */ + byte IOS2 :1; /* Input Capture or Output Compare Channel Configuration Bit 2 */ + byte IOS3 :1; /* Input Capture or Output Compare Channel Configuration Bit 3 */ + byte IOS4 :1; /* Input Capture or Output Compare Channel Configuration Bit 4 */ + byte IOS5 :1; /* Input Capture or Output Compare Channel Configuration Bit 5 */ + byte IOS6 :1; /* Input Capture or Output Compare Channel Configuration Bit 6 */ + byte IOS7 :1; /* Input Capture or Output Compare Channel Configuration Bit 7 */ + } Bits; + struct { + byte grpIOS :8; + } MergedBits; +} TIOSSTR; +extern volatile TIOSSTR _TIOS @(REG_BASE + 0x00000040); +#define TIOS _TIOS.Byte +#define TIOS_IOS0 _TIOS.Bits.IOS0 +#define TIOS_IOS1 _TIOS.Bits.IOS1 +#define TIOS_IOS2 _TIOS.Bits.IOS2 +#define TIOS_IOS3 _TIOS.Bits.IOS3 +#define TIOS_IOS4 _TIOS.Bits.IOS4 +#define TIOS_IOS5 _TIOS.Bits.IOS5 +#define TIOS_IOS6 _TIOS.Bits.IOS6 +#define TIOS_IOS7 _TIOS.Bits.IOS7 +#define TIOS_IOS _TIOS.MergedBits.grpIOS + + +/*** CFORC - Timer Compare Force Register; 0x00000041 ***/ +typedef union { + byte Byte; + struct { + byte FOC0 :1; /* Force Output Compare Action for Channel 0 */ + byte FOC1 :1; /* Force Output Compare Action for Channel 1 */ + byte FOC2 :1; /* Force Output Compare Action for Channel 2 */ + byte FOC3 :1; /* Force Output Compare Action for Channel 3 */ + byte FOC4 :1; /* Force Output Compare Action for Channel 4 */ + byte FOC5 :1; /* Force Output Compare Action for Channel 5 */ + byte FOC6 :1; /* Force Output Compare Action for Channel 6 */ + byte FOC7 :1; /* Force Output Compare Action for Channel 7 */ + } Bits; + struct { + byte grpFOC :8; + } MergedBits; +} CFORCSTR; +extern volatile CFORCSTR _CFORC @(REG_BASE + 0x00000041); +#define CFORC _CFORC.Byte +#define CFORC_FOC0 _CFORC.Bits.FOC0 +#define CFORC_FOC1 _CFORC.Bits.FOC1 +#define CFORC_FOC2 _CFORC.Bits.FOC2 +#define CFORC_FOC3 _CFORC.Bits.FOC3 +#define CFORC_FOC4 _CFORC.Bits.FOC4 +#define CFORC_FOC5 _CFORC.Bits.FOC5 +#define CFORC_FOC6 _CFORC.Bits.FOC6 +#define CFORC_FOC7 _CFORC.Bits.FOC7 +#define CFORC_FOC _CFORC.MergedBits.grpFOC + + +/*** OC7M - Output Compare 7 Mask Register; 0x00000042 ***/ +typedef union { + byte Byte; + struct { + byte OC7M0 :1; /* Output Compare 7 Mask Bit 0 */ + byte OC7M1 :1; /* Output Compare 7 Mask Bit 1 */ + byte OC7M2 :1; /* Output Compare 7 Mask Bit 2 */ + byte OC7M3 :1; /* Output Compare 7 Mask Bit 3 */ + byte OC7M4 :1; /* Output Compare 7 Mask Bit 4 */ + byte OC7M5 :1; /* Output Compare 7 Mask Bit 5 */ + byte OC7M6 :1; /* Output Compare 7 Mask Bit 6 */ + byte OC7M7 :1; /* Output Compare 7 Mask Bit 7 */ + } Bits; + struct { + byte grpOC7M :8; + } MergedBits; +} OC7MSTR; +extern volatile OC7MSTR _OC7M @(REG_BASE + 0x00000042); +#define OC7M _OC7M.Byte +#define OC7M_OC7M0 _OC7M.Bits.OC7M0 +#define OC7M_OC7M1 _OC7M.Bits.OC7M1 +#define OC7M_OC7M2 _OC7M.Bits.OC7M2 +#define OC7M_OC7M3 _OC7M.Bits.OC7M3 +#define OC7M_OC7M4 _OC7M.Bits.OC7M4 +#define OC7M_OC7M5 _OC7M.Bits.OC7M5 +#define OC7M_OC7M6 _OC7M.Bits.OC7M6 +#define OC7M_OC7M7 _OC7M.Bits.OC7M7 +#define OC7M_OC7M _OC7M.MergedBits.grpOC7M + + +/*** OC7D - Output Compare 7 Data Register; 0x00000043 ***/ +typedef union { + byte Byte; + struct { + byte grpOC7D :8; + } MergedBits; +} OC7DSTR; +extern volatile OC7DSTR _OC7D @(REG_BASE + 0x00000043); +#define OC7D _OC7D.Byte +#define OC7D_OC7D _OC7D.MergedBits.grpOC7D + + +/*** TSCR1 - Timer System Control Register1; 0x00000046 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte TFFCA :1; /* Timer Fast Flag Clear All */ + byte TSFRZ :1; /* Timer and Modulus Counter Stop While in Freeze Mode */ + byte TSWAI :1; /* Timer Module Stops While in Wait */ + byte TEN :1; /* Timer Enable */ + } Bits; +} TSCR1STR; +extern volatile TSCR1STR _TSCR1 @(REG_BASE + 0x00000046); +#define TSCR1 _TSCR1.Byte +#define TSCR1_TFFCA _TSCR1.Bits.TFFCA +#define TSCR1_TSFRZ _TSCR1.Bits.TSFRZ +#define TSCR1_TSWAI _TSCR1.Bits.TSWAI +#define TSCR1_TEN _TSCR1.Bits.TEN + + +/*** TTOV - Timer Toggle On Overflow Register; 0x00000047 ***/ +typedef union { + byte Byte; + struct { + byte TOV0 :1; /* Toggle On Overflow Bit 0 */ + byte TOV1 :1; /* Toggle On Overflow Bit 1 */ + byte TOV2 :1; /* Toggle On Overflow Bit 2 */ + byte TOV3 :1; /* Toggle On Overflow Bit 3 */ + byte TOV4 :1; /* Toggle On Overflow Bit 4 */ + byte TOV5 :1; /* Toggle On Overflow Bit 5 */ + byte TOV6 :1; /* Toggle On Overflow Bit 6 */ + byte TOV7 :1; /* Toggle On Overflow Bit 7 */ + } Bits; + struct { + byte grpTOV :8; + } MergedBits; +} TTOVSTR; +extern volatile TTOVSTR _TTOV @(REG_BASE + 0x00000047); +#define TTOV _TTOV.Byte +#define TTOV_TOV0 _TTOV.Bits.TOV0 +#define TTOV_TOV1 _TTOV.Bits.TOV1 +#define TTOV_TOV2 _TTOV.Bits.TOV2 +#define TTOV_TOV3 _TTOV.Bits.TOV3 +#define TTOV_TOV4 _TTOV.Bits.TOV4 +#define TTOV_TOV5 _TTOV.Bits.TOV5 +#define TTOV_TOV6 _TTOV.Bits.TOV6 +#define TTOV_TOV7 _TTOV.Bits.TOV7 +#define TTOV_TOV _TTOV.MergedBits.grpTOV + + +/*** TCTL1 - Timer Control Registers 1; 0x00000048 ***/ +typedef union { + byte Byte; + struct { + byte OL4 :1; /* Output Level Bit 4 */ + byte OM4 :1; /* Output Mode Bit 4 */ + byte OL5 :1; /* Output Level Bit 5 */ + byte OM5 :1; /* Output Mode Bit 5 */ + byte OL6 :1; /* Output Level Bit 6 */ + byte OM6 :1; /* Output Mode Bit 6 */ + byte OL7 :1; /* Output Level Bit 7 */ + byte OM7 :1; /* Output Mode Bit 7 */ + } Bits; +} TCTL1STR; +extern volatile TCTL1STR _TCTL1 @(REG_BASE + 0x00000048); +#define TCTL1 _TCTL1.Byte +#define TCTL1_OL4 _TCTL1.Bits.OL4 +#define TCTL1_OM4 _TCTL1.Bits.OM4 +#define TCTL1_OL5 _TCTL1.Bits.OL5 +#define TCTL1_OM5 _TCTL1.Bits.OM5 +#define TCTL1_OL6 _TCTL1.Bits.OL6 +#define TCTL1_OM6 _TCTL1.Bits.OM6 +#define TCTL1_OL7 _TCTL1.Bits.OL7 +#define TCTL1_OM7 _TCTL1.Bits.OM7 + + +/*** TCTL2 - Timer Control Registers 2; 0x00000049 ***/ +typedef union { + byte Byte; + struct { + byte OL0 :1; /* Output Level Bit 0 */ + byte OM0 :1; /* Output Mode Bit 0 */ + byte OL1 :1; /* Output Level Bit 1 */ + byte OM1 :1; /* Output Mode Bit 1 */ + byte OL2 :1; /* Output Level Bit 2 */ + byte OM2 :1; /* Output Mode Bit 2 */ + byte OL3 :1; /* Output Level Bit 3 */ + byte OM3 :1; /* Output Mode Bit 3 */ + } Bits; +} TCTL2STR; +extern volatile TCTL2STR _TCTL2 @(REG_BASE + 0x00000049); +#define TCTL2 _TCTL2.Byte +#define TCTL2_OL0 _TCTL2.Bits.OL0 +#define TCTL2_OM0 _TCTL2.Bits.OM0 +#define TCTL2_OL1 _TCTL2.Bits.OL1 +#define TCTL2_OM1 _TCTL2.Bits.OM1 +#define TCTL2_OL2 _TCTL2.Bits.OL2 +#define TCTL2_OM2 _TCTL2.Bits.OM2 +#define TCTL2_OL3 _TCTL2.Bits.OL3 +#define TCTL2_OM3 _TCTL2.Bits.OM3 + + +/*** TCTL3 - Timer Control Register 3; 0x0000004A ***/ +typedef union { + byte Byte; + struct { + byte EDG4A :1; /* Input Capture Edge Control 4A */ + byte EDG4B :1; /* Input Capture Edge Control 4B */ + byte EDG5A :1; /* Input Capture Edge Control 5A */ + byte EDG5B :1; /* Input Capture Edge Control 5B */ + byte EDG6A :1; /* Input Capture Edge Control 6A */ + byte EDG6B :1; /* Input Capture Edge Control 6B */ + byte EDG7A :1; /* Input Capture Edge Control 7A */ + byte EDG7B :1; /* Input Capture Edge Control 7B */ + } Bits; +} TCTL3STR; +extern volatile TCTL3STR _TCTL3 @(REG_BASE + 0x0000004A); +#define TCTL3 _TCTL3.Byte +#define TCTL3_EDG4A _TCTL3.Bits.EDG4A +#define TCTL3_EDG4B _TCTL3.Bits.EDG4B +#define TCTL3_EDG5A _TCTL3.Bits.EDG5A +#define TCTL3_EDG5B _TCTL3.Bits.EDG5B +#define TCTL3_EDG6A _TCTL3.Bits.EDG6A +#define TCTL3_EDG6B _TCTL3.Bits.EDG6B +#define TCTL3_EDG7A _TCTL3.Bits.EDG7A +#define TCTL3_EDG7B _TCTL3.Bits.EDG7B + + +/*** TCTL4 - Timer Control Register 4; 0x0000004B ***/ +typedef union { + byte Byte; + struct { + byte EDG0A :1; /* Input Capture Edge Control 0A */ + byte EDG0B :1; /* Input Capture Edge Control 0B */ + byte EDG1A :1; /* Input Capture Edge Control 1A */ + byte EDG1B :1; /* Input Capture Edge Control 1B */ + byte EDG2A :1; /* Input Capture Edge Control 2A */ + byte EDG2B :1; /* Input Capture Edge Control 2B */ + byte EDG3A :1; /* Input Capture Edge Control 3A */ + byte EDG3B :1; /* Input Capture Edge Control 3B */ + } Bits; +} TCTL4STR; +extern volatile TCTL4STR _TCTL4 @(REG_BASE + 0x0000004B); +#define TCTL4 _TCTL4.Byte +#define TCTL4_EDG0A _TCTL4.Bits.EDG0A +#define TCTL4_EDG0B _TCTL4.Bits.EDG0B +#define TCTL4_EDG1A _TCTL4.Bits.EDG1A +#define TCTL4_EDG1B _TCTL4.Bits.EDG1B +#define TCTL4_EDG2A _TCTL4.Bits.EDG2A +#define TCTL4_EDG2B _TCTL4.Bits.EDG2B +#define TCTL4_EDG3A _TCTL4.Bits.EDG3A +#define TCTL4_EDG3B _TCTL4.Bits.EDG3B + + +/*** TIE - Timer Interrupt Enable Register; 0x0000004C ***/ +typedef union { + byte Byte; + struct { + byte C0I :1; /* Input Capture/Output Compare Interrupt Enable Bit 0 */ + byte C1I :1; /* Input Capture/Output Compare Interrupt Enable Bit 1 */ + byte C2I :1; /* Input Capture/Output Compare Interrupt Enable Bit 2 */ + byte C3I :1; /* Input Capture/Output Compare Interrupt Enable Bit 3 */ + byte C4I :1; /* Input Capture/Output Compare Interrupt Enable Bit 4 */ + byte C5I :1; /* Input Capture/Output Compare Interrupt Enable Bit 5 */ + byte C6I :1; /* Input Capture/Output Compare Interrupt Enable Bit 6 */ + byte C7I :1; /* Input Capture/Output Compare Interrupt Enable Bit 7 */ + } Bits; +} TIESTR; +extern volatile TIESTR _TIE @(REG_BASE + 0x0000004C); +#define TIE _TIE.Byte +#define TIE_C0I _TIE.Bits.C0I +#define TIE_C1I _TIE.Bits.C1I +#define TIE_C2I _TIE.Bits.C2I +#define TIE_C3I _TIE.Bits.C3I +#define TIE_C4I _TIE.Bits.C4I +#define TIE_C5I _TIE.Bits.C5I +#define TIE_C6I _TIE.Bits.C6I +#define TIE_C7I _TIE.Bits.C7I + + +/*** TSCR2 - Timer System Control Register 2; 0x0000004D ***/ +typedef union { + byte Byte; + struct { + byte PR0 :1; /* Timer Prescaler Select Bit 0 */ + byte PR1 :1; /* Timer Prescaler Select Bit 1 */ + byte PR2 :1; /* Timer Prescaler Select Bit 2 */ + byte TCRE :1; /* Timer Counter Reset Enable */ + byte :1; + byte :1; + byte :1; + byte TOI :1; /* Timer Overflow Interrupt Enable */ + } Bits; + struct { + byte grpPR :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} TSCR2STR; +extern volatile TSCR2STR _TSCR2 @(REG_BASE + 0x0000004D); +#define TSCR2 _TSCR2.Byte +#define TSCR2_PR0 _TSCR2.Bits.PR0 +#define TSCR2_PR1 _TSCR2.Bits.PR1 +#define TSCR2_PR2 _TSCR2.Bits.PR2 +#define TSCR2_TCRE _TSCR2.Bits.TCRE +#define TSCR2_TOI _TSCR2.Bits.TOI +#define TSCR2_PR _TSCR2.MergedBits.grpPR + + +/*** TFLG1 - Main Timer Interrupt Flag 1; 0x0000004E ***/ +typedef union { + byte Byte; + struct { + byte C0F :1; /* Input Capture/Output Compare Channel Flag 0 */ + byte C1F :1; /* Input Capture/Output Compare Channel Flag 1 */ + byte C2F :1; /* Input Capture/Output Compare Channel Flag 2 */ + byte C3F :1; /* Input Capture/Output Compare Channel Flag 3 */ + byte C4F :1; /* Input Capture/Output Compare Channel Flag 4 */ + byte C5F :1; /* Input Capture/Output Compare Channel Flag 5 */ + byte C6F :1; /* Input Capture/Output Compare Channel Flag 6 */ + byte C7F :1; /* Input Capture/Output Compare Channel Flag 7 */ + } Bits; +} TFLG1STR; +extern volatile TFLG1STR _TFLG1 @(REG_BASE + 0x0000004E); +#define TFLG1 _TFLG1.Byte +#define TFLG1_C0F _TFLG1.Bits.C0F +#define TFLG1_C1F _TFLG1.Bits.C1F +#define TFLG1_C2F _TFLG1.Bits.C2F +#define TFLG1_C3F _TFLG1.Bits.C3F +#define TFLG1_C4F _TFLG1.Bits.C4F +#define TFLG1_C5F _TFLG1.Bits.C5F +#define TFLG1_C6F _TFLG1.Bits.C6F +#define TFLG1_C7F _TFLG1.Bits.C7F + + +/*** TFLG2 - Main Timer Interrupt Flag 2; 0x0000004F ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte TOF :1; /* Timer Overflow Flag */ + } Bits; +} TFLG2STR; +extern volatile TFLG2STR _TFLG2 @(REG_BASE + 0x0000004F); +#define TFLG2 _TFLG2.Byte +#define TFLG2_TOF _TFLG2.Bits.TOF + + +/*** PACTL - 16-Bit Pulse Accumulator A Control Register; 0x00000060 ***/ +typedef union { + byte Byte; + struct { + byte PAI :1; /* Pulse Accumulator Input Interrupt enable */ + byte PAOVI :1; /* Pulse Accumulator A Overflow Interrupt enable */ + byte CLK0 :1; /* Clock Select Bit 0 */ + byte CLK1 :1; /* Clock Select Bit 1 */ + byte PEDGE :1; /* Pulse Accumulator Edge Control */ + byte PAMOD :1; /* Pulse Accumulator Mode */ + byte PAEN :1; /* Pulse Accumulator A System Enable */ + byte :1; + } Bits; + struct { + byte :1; + byte :1; + byte grpCLK :2; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} PACTLSTR; +extern volatile PACTLSTR _PACTL @(REG_BASE + 0x00000060); +#define PACTL _PACTL.Byte +#define PACTL_PAI _PACTL.Bits.PAI +#define PACTL_PAOVI _PACTL.Bits.PAOVI +#define PACTL_CLK0 _PACTL.Bits.CLK0 +#define PACTL_CLK1 _PACTL.Bits.CLK1 +#define PACTL_PEDGE _PACTL.Bits.PEDGE +#define PACTL_PAMOD _PACTL.Bits.PAMOD +#define PACTL_PAEN _PACTL.Bits.PAEN +#define PACTL_CLK _PACTL.MergedBits.grpCLK + + +/*** PAFLG - Pulse Accumulator A Flag Register; 0x00000061 ***/ +typedef union { + byte Byte; + struct { + byte PAIF :1; /* Pulse Accumulator Input edge Flag */ + byte PAOVF :1; /* Pulse Accumulator A Overflow Flag */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} PAFLGSTR; +extern volatile PAFLGSTR _PAFLG @(REG_BASE + 0x00000061); +#define PAFLG _PAFLG.Byte +#define PAFLG_PAIF _PAFLG.Bits.PAIF +#define PAFLG_PAOVF _PAFLG.Bits.PAOVF + + +/*** MCCTL - Modulus Down Counter underflow; 0x00000066 ***/ +typedef union { + byte Byte; + struct { + byte MCPR0 :1; /* Modulus Counter Prescaler select 0 */ + byte MCPR1 :1; /* Modulus Counter Prescaler select 1 */ + byte MCEN :1; /* Modulus Down-Counter Enable */ + byte FLMC :1; /* Force Load Register into the Modulus Counter Count Register */ + byte ICLAT :1; /* Input Capture Force Latch Action */ + byte RDMCL :1; /* Read Modulus Down-Counter Load */ + byte MODMC :1; /* Modulus Mode Enable */ + byte MCZI :1; /* Modulus Counter Underflow Interrupt Enable */ + } Bits; + struct { + byte grpMCPR :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} MCCTLSTR; +extern volatile MCCTLSTR _MCCTL @(REG_BASE + 0x00000066); +#define MCCTL _MCCTL.Byte +#define MCCTL_MCPR0 _MCCTL.Bits.MCPR0 +#define MCCTL_MCPR1 _MCCTL.Bits.MCPR1 +#define MCCTL_MCEN _MCCTL.Bits.MCEN +#define MCCTL_FLMC _MCCTL.Bits.FLMC +#define MCCTL_ICLAT _MCCTL.Bits.ICLAT +#define MCCTL_RDMCL _MCCTL.Bits.RDMCL +#define MCCTL_MODMC _MCCTL.Bits.MODMC +#define MCCTL_MCZI _MCCTL.Bits.MCZI +#define MCCTL_MCPR _MCCTL.MergedBits.grpMCPR + + +/*** MCFLG - 16-Bit Modulus Down Counter Flag Register; 0x00000067 ***/ +typedef union { + byte Byte; + struct { + byte POLF0 :1; /* First Input Capture Polarity Status 0 */ + byte POLF1 :1; /* First Input Capture Polarity Status 1 */ + byte POLF2 :1; /* First Input Capture Polarity Status 2 */ + byte POLF3 :1; /* First Input Capture Polarity Status 3 */ + byte :1; + byte :1; + byte :1; + byte MCZF :1; /* Modulus Counter Underflow Flag */ + } Bits; + struct { + byte grpPOLF :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} MCFLGSTR; +extern volatile MCFLGSTR _MCFLG @(REG_BASE + 0x00000067); +#define MCFLG _MCFLG.Byte +#define MCFLG_POLF0 _MCFLG.Bits.POLF0 +#define MCFLG_POLF1 _MCFLG.Bits.POLF1 +#define MCFLG_POLF2 _MCFLG.Bits.POLF2 +#define MCFLG_POLF3 _MCFLG.Bits.POLF3 +#define MCFLG_MCZF _MCFLG.Bits.MCZF +#define MCFLG_POLF _MCFLG.MergedBits.grpPOLF + + +/*** ICPAR - Input Control Pulse Accumulator Register; 0x00000068 ***/ +typedef union { + byte Byte; + struct { + byte PA0EN :1; /* 8-Bit Pulse Accumulator 0 Enable */ + byte PA1EN :1; /* 8-Bit Pulse Accumulator 1 Enable */ + byte PA2EN :1; /* 8-Bit Pulse Accumulator 2 Enable */ + byte PA3EN :1; /* 8-Bit Pulse Accumulator 3 Enable */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} ICPARSTR; +extern volatile ICPARSTR _ICPAR @(REG_BASE + 0x00000068); +#define ICPAR _ICPAR.Byte +#define ICPAR_PA0EN _ICPAR.Bits.PA0EN +#define ICPAR_PA1EN _ICPAR.Bits.PA1EN +#define ICPAR_PA2EN _ICPAR.Bits.PA2EN +#define ICPAR_PA3EN _ICPAR.Bits.PA3EN + + +/*** DLYCT - Delay Counter Control Register; 0x00000069 ***/ +typedef union { + byte Byte; + struct { + byte DLY0 :1; /* Delay Counter Select 0 */ + byte DLY1 :1; /* Delay Counter Select 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpDLY :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} DLYCTSTR; +extern volatile DLYCTSTR _DLYCT @(REG_BASE + 0x00000069); +#define DLYCT _DLYCT.Byte +#define DLYCT_DLY0 _DLYCT.Bits.DLY0 +#define DLYCT_DLY1 _DLYCT.Bits.DLY1 +#define DLYCT_DLY _DLYCT.MergedBits.grpDLY + + +/*** ICOVW - Input Control Overwrite Register; 0x0000006A ***/ +typedef union { + byte Byte; + struct { + byte NOVW0 :1; /* No Input Capture Overwrite 0 */ + byte NOVW1 :1; /* No Input Capture Overwrite 1 */ + byte NOVW2 :1; /* No Input Capture Overwrite 2 */ + byte NOVW3 :1; /* No Input Capture Overwrite 3 */ + byte NOVW4 :1; /* No Input Capture Overwrite 4 */ + byte NOVW5 :1; /* No Input Capture Overwrite 5 */ + byte NOVW6 :1; /* No Input Capture Overwrite 6 */ + byte NOVW7 :1; /* No Input Capture Overwrite 7 */ + } Bits; + struct { + byte grpNOVW :8; + } MergedBits; +} ICOVWSTR; +extern volatile ICOVWSTR _ICOVW @(REG_BASE + 0x0000006A); +#define ICOVW _ICOVW.Byte +#define ICOVW_NOVW0 _ICOVW.Bits.NOVW0 +#define ICOVW_NOVW1 _ICOVW.Bits.NOVW1 +#define ICOVW_NOVW2 _ICOVW.Bits.NOVW2 +#define ICOVW_NOVW3 _ICOVW.Bits.NOVW3 +#define ICOVW_NOVW4 _ICOVW.Bits.NOVW4 +#define ICOVW_NOVW5 _ICOVW.Bits.NOVW5 +#define ICOVW_NOVW6 _ICOVW.Bits.NOVW6 +#define ICOVW_NOVW7 _ICOVW.Bits.NOVW7 +#define ICOVW_NOVW _ICOVW.MergedBits.grpNOVW + + +/*** ICSYS - Input Control System Control Register; 0x0000006B ***/ +typedef union { + byte Byte; + struct { + byte LATQ :1; /* Input Control Latch or Queue Mode Enable */ + byte BUFEN :1; /* IC Buffer Enable */ + byte PACMX :1; /* 8-Bit Pulse Accumulators Maximum Count */ + byte TFMOD :1; /* Timer Flag-setting Mode */ + byte SH04 :1; /* Share Input action of Input Capture Channels 0 and 4 */ + byte SH15 :1; /* Share Input action of Input Capture Channels 1 and 5 */ + byte SH26 :1; /* Share Input action of Input Capture Channels 2 and 6 */ + byte SH37 :1; /* Share Input action of Input Capture Channels 3 and 7 */ + } Bits; +} ICSYSSTR; +extern volatile ICSYSSTR _ICSYS @(REG_BASE + 0x0000006B); +#define ICSYS _ICSYS.Byte +#define ICSYS_LATQ _ICSYS.Bits.LATQ +#define ICSYS_BUFEN _ICSYS.Bits.BUFEN +#define ICSYS_PACMX _ICSYS.Bits.PACMX +#define ICSYS_TFMOD _ICSYS.Bits.TFMOD +#define ICSYS_SH04 _ICSYS.Bits.SH04 +#define ICSYS_SH15 _ICSYS.Bits.SH15 +#define ICSYS_SH26 _ICSYS.Bits.SH26 +#define ICSYS_SH37 _ICSYS.Bits.SH37 + + +/*** TIMTST - Timer Test Register; 0x0000006D ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte TCBYP :1; /* Main Timer Divider Chain Bypass */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} TIMTSTSTR; +extern volatile TIMTSTSTR _TIMTST @(REG_BASE + 0x0000006D); +#define TIMTST _TIMTST.Byte +#define TIMTST_TCBYP _TIMTST.Bits.TCBYP + + +/*** PBCTL - 16-Bit Pulse Accumulator B Control Register; 0x00000070 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte PBOVI :1; /* Pulse Accumulator B Overflow Interrupt enable */ + byte :1; + byte :1; + byte :1; + byte :1; + byte PBEN :1; /* Pulse Accumulator B System Enable */ + byte :1; + } Bits; +} PBCTLSTR; +extern volatile PBCTLSTR _PBCTL @(REG_BASE + 0x00000070); +#define PBCTL _PBCTL.Byte +#define PBCTL_PBOVI _PBCTL.Bits.PBOVI +#define PBCTL_PBEN _PBCTL.Bits.PBEN + + +/*** PBFLG - Pulse Accumulator B Flag Register; 0x00000071 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte PBOVF :1; /* Pulse Accumulator B Overflow Flag */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} PBFLGSTR; +extern volatile PBFLGSTR _PBFLG @(REG_BASE + 0x00000071); +#define PBFLG _PBFLG.Byte +#define PBFLG_PBOVF _PBFLG.Bits.PBOVF + + +/*** ATD0STAT0 - ATD 0 Status Register 0; 0x00000086 ***/ +typedef union { + byte Byte; + struct { + byte CC0 :1; /* Conversion Counter 0 */ + byte CC1 :1; /* Conversion Counter 1 */ + byte CC2 :1; /* Conversion Counter 2 */ + byte :1; + byte FIFOR :1; /* FIFO Over Run Flag */ + byte ETORF :1; /* External Trigger Overrun Flag */ + byte :1; + byte SCF :1; /* Sequence Complete Flag */ + } Bits; + struct { + byte grpCC :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} ATD0STAT0STR; +extern volatile ATD0STAT0STR _ATD0STAT0 @(REG_BASE + 0x00000086); +#define ATD0STAT0 _ATD0STAT0.Byte +#define ATD0STAT0_CC0 _ATD0STAT0.Bits.CC0 +#define ATD0STAT0_CC1 _ATD0STAT0.Bits.CC1 +#define ATD0STAT0_CC2 _ATD0STAT0.Bits.CC2 +#define ATD0STAT0_FIFOR _ATD0STAT0.Bits.FIFOR +#define ATD0STAT0_ETORF _ATD0STAT0.Bits.ETORF +#define ATD0STAT0_SCF _ATD0STAT0.Bits.SCF +#define ATD0STAT0_CC _ATD0STAT0.MergedBits.grpCC + + +/*** ATD0STAT1 - ATD 0 Status Register 1; 0x0000008B ***/ +typedef union { + byte Byte; + struct { + byte CCF0 :1; /* Conversion Complete Flag 0 */ + byte CCF1 :1; /* Conversion Complete Flag 1 */ + byte CCF2 :1; /* Conversion Complete Flag 2 */ + byte CCF3 :1; /* Conversion Complete Flag 3 */ + byte CCF4 :1; /* Conversion Complete Flag 4 */ + byte CCF5 :1; /* Conversion Complete Flag 5 */ + byte CCF6 :1; /* Conversion Complete Flag 6 */ + byte CCF7 :1; /* Conversion Complete Flag 7 */ + } Bits; + struct { + byte grpCCF :8; + } MergedBits; +} ATD0STAT1STR; +extern volatile ATD0STAT1STR _ATD0STAT1 @(REG_BASE + 0x0000008B); +#define ATD0STAT1 _ATD0STAT1.Byte +#define ATD0STAT1_CCF0 _ATD0STAT1.Bits.CCF0 +#define ATD0STAT1_CCF1 _ATD0STAT1.Bits.CCF1 +#define ATD0STAT1_CCF2 _ATD0STAT1.Bits.CCF2 +#define ATD0STAT1_CCF3 _ATD0STAT1.Bits.CCF3 +#define ATD0STAT1_CCF4 _ATD0STAT1.Bits.CCF4 +#define ATD0STAT1_CCF5 _ATD0STAT1.Bits.CCF5 +#define ATD0STAT1_CCF6 _ATD0STAT1.Bits.CCF6 +#define ATD0STAT1_CCF7 _ATD0STAT1.Bits.CCF7 +#define ATD0STAT1_CCF _ATD0STAT1.MergedBits.grpCCF + + +/*** ATD0DIEN - ATD 0 Input Enable Mask Register; 0x0000008D ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* Disable/Enable Digital Input Buffer Bit 0 */ + byte BIT1 :1; /* Disable/Enable Digital Input Buffer Bit 1 */ + byte BIT2 :1; /* Disable/Enable Digital Input Buffer Bit 2 */ + byte BIT3 :1; /* Disable/Enable Digital Input Buffer Bit 3 */ + byte BIT4 :1; /* Disable/Enable Digital Input Buffer Bit 4 */ + byte BIT5 :1; /* Disable/Enable Digital Input Buffer Bit 5 */ + byte BIT6 :1; /* Disable/Enable Digital Input Buffer Bit 6 */ + byte BIT7 :1; /* Disable/Enable Digital Input Buffer Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} ATD0DIENSTR; +extern volatile ATD0DIENSTR _ATD0DIEN @(REG_BASE + 0x0000008D); +#define ATD0DIEN _ATD0DIEN.Byte +#define ATD0DIEN_BIT0 _ATD0DIEN.Bits.BIT0 +#define ATD0DIEN_BIT1 _ATD0DIEN.Bits.BIT1 +#define ATD0DIEN_BIT2 _ATD0DIEN.Bits.BIT2 +#define ATD0DIEN_BIT3 _ATD0DIEN.Bits.BIT3 +#define ATD0DIEN_BIT4 _ATD0DIEN.Bits.BIT4 +#define ATD0DIEN_BIT5 _ATD0DIEN.Bits.BIT5 +#define ATD0DIEN_BIT6 _ATD0DIEN.Bits.BIT6 +#define ATD0DIEN_BIT7 _ATD0DIEN.Bits.BIT7 +#define ATD0DIEN_BIT _ATD0DIEN.MergedBits.grpBIT + + +/*** PORTAD0 - Port AD0 Register; 0x0000008F ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* AN0 */ + byte BIT1 :1; /* AN1 */ + byte BIT2 :1; /* AN2 */ + byte BIT3 :1; /* AN3 */ + byte BIT4 :1; /* AN4 */ + byte BIT5 :1; /* AN5 */ + byte BIT6 :1; /* AN6 */ + byte BIT7 :1; /* AN7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} PORTAD0STR; +extern volatile PORTAD0STR _PORTAD0 @(REG_BASE + 0x0000008F); +#define PORTAD0 _PORTAD0.Byte +#define PORTAD0_BIT0 _PORTAD0.Bits.BIT0 +#define PORTAD0_BIT1 _PORTAD0.Bits.BIT1 +#define PORTAD0_BIT2 _PORTAD0.Bits.BIT2 +#define PORTAD0_BIT3 _PORTAD0.Bits.BIT3 +#define PORTAD0_BIT4 _PORTAD0.Bits.BIT4 +#define PORTAD0_BIT5 _PORTAD0.Bits.BIT5 +#define PORTAD0_BIT6 _PORTAD0.Bits.BIT6 +#define PORTAD0_BIT7 _PORTAD0.Bits.BIT7 +#define PORTAD0_BIT _PORTAD0.MergedBits.grpBIT + + +/*** PWME - PWM Enable Register; 0x000000A0 ***/ +typedef union { + byte Byte; + struct { + byte PWME0 :1; /* Pulse Width Channel 0 Enable */ + byte PWME1 :1; /* Pulse Width Channel 1 Enable */ + byte PWME2 :1; /* Pulse Width Channel 2 Enable */ + byte PWME3 :1; /* Pulse Width Channel 3 Enable */ + byte PWME4 :1; /* Pulse Width Channel 4 Enable */ + byte PWME5 :1; /* Pulse Width Channel 5 Enable */ + byte PWME6 :1; /* Pulse Width Channel 6 Enable */ + byte PWME7 :1; /* Pulse Width Channel 7 Enable */ + } Bits; + struct { + byte grpPWME :8; + } MergedBits; +} PWMESTR; +extern volatile PWMESTR _PWME @(REG_BASE + 0x000000A0); +#define PWME _PWME.Byte +#define PWME_PWME0 _PWME.Bits.PWME0 +#define PWME_PWME1 _PWME.Bits.PWME1 +#define PWME_PWME2 _PWME.Bits.PWME2 +#define PWME_PWME3 _PWME.Bits.PWME3 +#define PWME_PWME4 _PWME.Bits.PWME4 +#define PWME_PWME5 _PWME.Bits.PWME5 +#define PWME_PWME6 _PWME.Bits.PWME6 +#define PWME_PWME7 _PWME.Bits.PWME7 +#define PWME_PWME _PWME.MergedBits.grpPWME + + +/*** PWMPOL - PWM Polarity Register; 0x000000A1 ***/ +typedef union { + byte Byte; + struct { + byte PPOL0 :1; /* Pulse Width Channel 0 Polarity */ + byte PPOL1 :1; /* Pulse Width Channel 1 Polarity */ + byte PPOL2 :1; /* Pulse Width Channel 2 Polarity */ + byte PPOL3 :1; /* Pulse Width Channel 3 Polarity */ + byte PPOL4 :1; /* Pulse Width Channel 4 Polarity */ + byte PPOL5 :1; /* Pulse Width Channel 5 Polarity */ + byte PPOL6 :1; /* Pulse Width Channel 6 Polarity */ + byte PPOL7 :1; /* Pulse Width Channel 7 Polarity */ + } Bits; + struct { + byte grpPPOL :8; + } MergedBits; +} PWMPOLSTR; +extern volatile PWMPOLSTR _PWMPOL @(REG_BASE + 0x000000A1); +#define PWMPOL _PWMPOL.Byte +#define PWMPOL_PPOL0 _PWMPOL.Bits.PPOL0 +#define PWMPOL_PPOL1 _PWMPOL.Bits.PPOL1 +#define PWMPOL_PPOL2 _PWMPOL.Bits.PPOL2 +#define PWMPOL_PPOL3 _PWMPOL.Bits.PPOL3 +#define PWMPOL_PPOL4 _PWMPOL.Bits.PPOL4 +#define PWMPOL_PPOL5 _PWMPOL.Bits.PPOL5 +#define PWMPOL_PPOL6 _PWMPOL.Bits.PPOL6 +#define PWMPOL_PPOL7 _PWMPOL.Bits.PPOL7 +#define PWMPOL_PPOL _PWMPOL.MergedBits.grpPPOL + + +/*** PWMCLK - PWM Clock Select Register; 0x000000A2 ***/ +typedef union { + byte Byte; + struct { + byte PCLK0 :1; /* Pulse Width Channel 0 Clock Select */ + byte PCLK1 :1; /* Pulse Width Channel 1 Clock Select */ + byte PCLK2 :1; /* Pulse Width Channel 2 Clock Select */ + byte PCLK3 :1; /* Pulse Width Channel 3 Clock Select */ + byte PCLK4 :1; /* Pulse Width Channel 4 Clock Select */ + byte PCLK5 :1; /* Pulse Width Channel 5 Clock Select */ + byte PCLK6 :1; /* Pulse Width Channel 6 Clock Select */ + byte PCLK7 :1; /* Pulse Width Channel 7 Clock Select */ + } Bits; + struct { + byte grpPCLK :8; + } MergedBits; +} PWMCLKSTR; +extern volatile PWMCLKSTR _PWMCLK @(REG_BASE + 0x000000A2); +#define PWMCLK _PWMCLK.Byte +#define PWMCLK_PCLK0 _PWMCLK.Bits.PCLK0 +#define PWMCLK_PCLK1 _PWMCLK.Bits.PCLK1 +#define PWMCLK_PCLK2 _PWMCLK.Bits.PCLK2 +#define PWMCLK_PCLK3 _PWMCLK.Bits.PCLK3 +#define PWMCLK_PCLK4 _PWMCLK.Bits.PCLK4 +#define PWMCLK_PCLK5 _PWMCLK.Bits.PCLK5 +#define PWMCLK_PCLK6 _PWMCLK.Bits.PCLK6 +#define PWMCLK_PCLK7 _PWMCLK.Bits.PCLK7 +#define PWMCLK_PCLK _PWMCLK.MergedBits.grpPCLK + + +/*** PWMPRCLK - PWM Prescale Clock Select Register; 0x000000A3 ***/ +typedef union { + byte Byte; + struct { + byte PCKA0 :1; /* Prescaler Select for Clock A 0 */ + byte PCKA1 :1; /* Prescaler Select for Clock A 1 */ + byte PCKA2 :1; /* Prescaler Select for Clock A 2 */ + byte :1; + byte PCKB0 :1; /* Prescaler Select for Clock B 0 */ + byte PCKB1 :1; /* Prescaler Select for Clock B 1 */ + byte PCKB2 :1; /* Prescaler Select for Clock B 2 */ + byte :1; + } Bits; + struct { + byte grpPCKA :3; + byte :1; + byte grpPCKB :3; + byte :1; + } MergedBits; +} PWMPRCLKSTR; +extern volatile PWMPRCLKSTR _PWMPRCLK @(REG_BASE + 0x000000A3); +#define PWMPRCLK _PWMPRCLK.Byte +#define PWMPRCLK_PCKA0 _PWMPRCLK.Bits.PCKA0 +#define PWMPRCLK_PCKA1 _PWMPRCLK.Bits.PCKA1 +#define PWMPRCLK_PCKA2 _PWMPRCLK.Bits.PCKA2 +#define PWMPRCLK_PCKB0 _PWMPRCLK.Bits.PCKB0 +#define PWMPRCLK_PCKB1 _PWMPRCLK.Bits.PCKB1 +#define PWMPRCLK_PCKB2 _PWMPRCLK.Bits.PCKB2 +#define PWMPRCLK_PCKA _PWMPRCLK.MergedBits.grpPCKA +#define PWMPRCLK_PCKB _PWMPRCLK.MergedBits.grpPCKB + + +/*** PWMCAE - PWM Center Align Enable Register; 0x000000A4 ***/ +typedef union { + byte Byte; + struct { + byte CAE0 :1; /* Center Aligned Output Mode on channel 0 */ + byte CAE1 :1; /* Center Aligned Output Mode on channel 1 */ + byte CAE2 :1; /* Center Aligned Output Mode on channel 2 */ + byte CAE3 :1; /* Center Aligned Output Mode on channel 3 */ + byte CAE4 :1; /* Center Aligned Output Mode on channel 4 */ + byte CAE5 :1; /* Center Aligned Output Mode on channel 5 */ + byte CAE6 :1; /* Center Aligned Output Mode on channel 6 */ + byte CAE7 :1; /* Center Aligned Output Mode on channel 7 */ + } Bits; + struct { + byte grpCAE :8; + } MergedBits; +} PWMCAESTR; +extern volatile PWMCAESTR _PWMCAE @(REG_BASE + 0x000000A4); +#define PWMCAE _PWMCAE.Byte +#define PWMCAE_CAE0 _PWMCAE.Bits.CAE0 +#define PWMCAE_CAE1 _PWMCAE.Bits.CAE1 +#define PWMCAE_CAE2 _PWMCAE.Bits.CAE2 +#define PWMCAE_CAE3 _PWMCAE.Bits.CAE3 +#define PWMCAE_CAE4 _PWMCAE.Bits.CAE4 +#define PWMCAE_CAE5 _PWMCAE.Bits.CAE5 +#define PWMCAE_CAE6 _PWMCAE.Bits.CAE6 +#define PWMCAE_CAE7 _PWMCAE.Bits.CAE7 +#define PWMCAE_CAE _PWMCAE.MergedBits.grpCAE + + +/*** PWMCTL - PWM Control Register; 0x000000A5 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte PFRZ :1; /* PWM Counters Stop in Freeze Mode */ + byte PSWAI :1; /* PWM Stops in Wait Mode */ + byte CON01 :1; /* Concatenate channels 0 and 1 */ + byte CON23 :1; /* Concatenate channels 2 and 3 */ + byte CON45 :1; /* Concatenate channels 4 and 5 */ + byte CON67 :1; /* Concatenate channels 6 and 7 */ + } Bits; +} PWMCTLSTR; +extern volatile PWMCTLSTR _PWMCTL @(REG_BASE + 0x000000A5); +#define PWMCTL _PWMCTL.Byte +#define PWMCTL_PFRZ _PWMCTL.Bits.PFRZ +#define PWMCTL_PSWAI _PWMCTL.Bits.PSWAI +#define PWMCTL_CON01 _PWMCTL.Bits.CON01 +#define PWMCTL_CON23 _PWMCTL.Bits.CON23 +#define PWMCTL_CON45 _PWMCTL.Bits.CON45 +#define PWMCTL_CON67 _PWMCTL.Bits.CON67 + + +/*** PWMSCLA - PWM Scale A Register; 0x000000A8 ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* PWM Scale A Bit 0 */ + byte BIT1 :1; /* PWM Scale A Bit 1 */ + byte BIT2 :1; /* PWM Scale A Bit 2 */ + byte BIT3 :1; /* PWM Scale A Bit 3 */ + byte BIT4 :1; /* PWM Scale A Bit 4 */ + byte BIT5 :1; /* PWM Scale A Bit 5 */ + byte BIT6 :1; /* PWM Scale A Bit 6 */ + byte BIT7 :1; /* PWM Scale A Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} PWMSCLASTR; +extern volatile PWMSCLASTR _PWMSCLA @(REG_BASE + 0x000000A8); +#define PWMSCLA _PWMSCLA.Byte +#define PWMSCLA_BIT0 _PWMSCLA.Bits.BIT0 +#define PWMSCLA_BIT1 _PWMSCLA.Bits.BIT1 +#define PWMSCLA_BIT2 _PWMSCLA.Bits.BIT2 +#define PWMSCLA_BIT3 _PWMSCLA.Bits.BIT3 +#define PWMSCLA_BIT4 _PWMSCLA.Bits.BIT4 +#define PWMSCLA_BIT5 _PWMSCLA.Bits.BIT5 +#define PWMSCLA_BIT6 _PWMSCLA.Bits.BIT6 +#define PWMSCLA_BIT7 _PWMSCLA.Bits.BIT7 +#define PWMSCLA_BIT _PWMSCLA.MergedBits.grpBIT + + +/*** PWMSCLB - PWM Scale B Register; 0x000000A9 ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* PWM Scale B Bit 0 */ + byte BIT1 :1; /* PWM Scale B Bit 1 */ + byte BIT2 :1; /* PWM Scale B Bit 2 */ + byte BIT3 :1; /* PWM Scale B Bit 3 */ + byte BIT4 :1; /* PWM Scale B Bit 4 */ + byte BIT5 :1; /* PWM Scale B Bit 5 */ + byte BIT6 :1; /* PWM Scale B Bit 6 */ + byte BIT7 :1; /* PWM Scale B Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} PWMSCLBSTR; +extern volatile PWMSCLBSTR _PWMSCLB @(REG_BASE + 0x000000A9); +#define PWMSCLB _PWMSCLB.Byte +#define PWMSCLB_BIT0 _PWMSCLB.Bits.BIT0 +#define PWMSCLB_BIT1 _PWMSCLB.Bits.BIT1 +#define PWMSCLB_BIT2 _PWMSCLB.Bits.BIT2 +#define PWMSCLB_BIT3 _PWMSCLB.Bits.BIT3 +#define PWMSCLB_BIT4 _PWMSCLB.Bits.BIT4 +#define PWMSCLB_BIT5 _PWMSCLB.Bits.BIT5 +#define PWMSCLB_BIT6 _PWMSCLB.Bits.BIT6 +#define PWMSCLB_BIT7 _PWMSCLB.Bits.BIT7 +#define PWMSCLB_BIT _PWMSCLB.MergedBits.grpBIT + + +/*** PWMSDN - PWM Shutdown Register; 0x000000C4 ***/ +typedef union { + byte Byte; + struct { + byte PWM7ENA :1; /* PWM emergency shutdown Enable */ + byte PWM7INL :1; /* PWM shutdown active input level for ch. 7 */ + byte PWM7IN :1; /* PWM channel 7 input status */ + byte :1; + byte PWMLVL :1; /* PWM shutdown output Level */ + byte PWMRSTRT :1; /* PWM Restart */ + byte PWMIE :1; /* PWM Interrupt Enable */ + byte PWMIF :1; /* PWM Interrupt Flag */ + } Bits; +} PWMSDNSTR; +extern volatile PWMSDNSTR _PWMSDN @(REG_BASE + 0x000000C4); +#define PWMSDN _PWMSDN.Byte +#define PWMSDN_PWM7ENA _PWMSDN.Bits.PWM7ENA +#define PWMSDN_PWM7INL _PWMSDN.Bits.PWM7INL +#define PWMSDN_PWM7IN _PWMSDN.Bits.PWM7IN +#define PWMSDN_PWMLVL _PWMSDN.Bits.PWMLVL +#define PWMSDN_PWMRSTRT _PWMSDN.Bits.PWMRSTRT +#define PWMSDN_PWMIE _PWMSDN.Bits.PWMIE +#define PWMSDN_PWMIF _PWMSDN.Bits.PWMIF + + +/*** SCI0CR1 - SCI 0 Control Register 1; 0x000000CA ***/ +typedef union { + byte Byte; + struct { + byte PT :1; /* Parity Type Bit */ + byte PE :1; /* Parity Enable Bit */ + byte ILT :1; /* Idle Line Type Bit */ + byte WAKE :1; /* Wakeup Condition Bit */ + byte M :1; /* Data Format Mode Bit */ + byte RSRC :1; /* Receiver Source Bit */ + byte SCISWAI :1; /* SCI 0 Stop in Wait Mode Bit */ + byte LOOPS :1; /* Loop Select Bit */ + } Bits; +} SCI0CR1STR; +extern volatile SCI0CR1STR _SCI0CR1 @(REG_BASE + 0x000000CA); +#define SCI0CR1 _SCI0CR1.Byte +#define SCI0CR1_PT _SCI0CR1.Bits.PT +#define SCI0CR1_PE _SCI0CR1.Bits.PE +#define SCI0CR1_ILT _SCI0CR1.Bits.ILT +#define SCI0CR1_WAKE _SCI0CR1.Bits.WAKE +#define SCI0CR1_M _SCI0CR1.Bits.M +#define SCI0CR1_RSRC _SCI0CR1.Bits.RSRC +#define SCI0CR1_SCISWAI _SCI0CR1.Bits.SCISWAI +#define SCI0CR1_LOOPS _SCI0CR1.Bits.LOOPS + + +/*** SCI0CR2 - SCI 0 Control Register 2; 0x000000CB ***/ +typedef union { + byte Byte; + struct { + byte SBK :1; /* Send Break Bit */ + byte RWU :1; /* Receiver Wakeup Bit */ + byte RE :1; /* Receiver Enable Bit */ + byte TE :1; /* Transmitter Enable Bit */ + byte ILIE :1; /* Idle Line Interrupt Enable Bit */ + byte RIE :1; /* Receiver Full Interrupt Enable Bit */ + byte TCIE :1; /* Transmission Complete Interrupt Enable Bit */ + byte SCTIE :1; /* Transmitter Interrupt Enable Bit */ + } Bits; +} SCI0CR2STR; +extern volatile SCI0CR2STR _SCI0CR2 @(REG_BASE + 0x000000CB); +#define SCI0CR2 _SCI0CR2.Byte +#define SCI0CR2_SBK _SCI0CR2.Bits.SBK +#define SCI0CR2_RWU _SCI0CR2.Bits.RWU +#define SCI0CR2_RE _SCI0CR2.Bits.RE +#define SCI0CR2_TE _SCI0CR2.Bits.TE +#define SCI0CR2_ILIE _SCI0CR2.Bits.ILIE +#define SCI0CR2_RIE _SCI0CR2.Bits.RIE +#define SCI0CR2_TCIE _SCI0CR2.Bits.TCIE +#define SCI0CR2_SCTIE _SCI0CR2.Bits.SCTIE + + +/*** SCI0SR1 - SCI 0 Status Register 1; 0x000000CC ***/ +typedef union { + byte Byte; + struct { + byte PF :1; /* Parity Error Flag */ + byte FE :1; /* Framing Error Flag */ + byte NF :1; /* Noise Flag */ + byte OR :1; /* Overrun Flag */ + byte IDLE :1; /* Idle Line Flag */ + byte RDRF :1; /* Receive Data Register Full Flag */ + byte TC :1; /* Transmit Complete Flag */ + byte TDRE :1; /* Transmit Data Register Empty Flag */ + } Bits; +} SCI0SR1STR; +extern volatile SCI0SR1STR _SCI0SR1 @(REG_BASE + 0x000000CC); +#define SCI0SR1 _SCI0SR1.Byte +#define SCI0SR1_PF _SCI0SR1.Bits.PF +#define SCI0SR1_FE _SCI0SR1.Bits.FE +#define SCI0SR1_NF _SCI0SR1.Bits.NF +#define SCI0SR1_OR _SCI0SR1.Bits.OR +#define SCI0SR1_IDLE _SCI0SR1.Bits.IDLE +#define SCI0SR1_RDRF _SCI0SR1.Bits.RDRF +#define SCI0SR1_TC _SCI0SR1.Bits.TC +#define SCI0SR1_TDRE _SCI0SR1.Bits.TDRE + + +/*** SCI0SR2 - SCI 0 Status Register 2; 0x000000CD ***/ +typedef union { + byte Byte; + struct { + byte RAF :1; /* Receiver Active Flag */ + byte TXDIR :1; /* Transmitter pin data direction in Single-Wire mode */ + byte BRK13 :1; /* Break Transmit character length */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} SCI0SR2STR; +extern volatile SCI0SR2STR _SCI0SR2 @(REG_BASE + 0x000000CD); +#define SCI0SR2 _SCI0SR2.Byte +#define SCI0SR2_RAF _SCI0SR2.Bits.RAF +#define SCI0SR2_TXDIR _SCI0SR2.Bits.TXDIR +#define SCI0SR2_BRK13 _SCI0SR2.Bits.BRK13 + + +/*** SCI0DRH - SCI 0 Data Register High; 0x000000CE ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte T8 :1; /* Transmit Bit 8 */ + byte R8 :1; /* Received Bit 8 */ + } Bits; +} SCI0DRHSTR; +extern volatile SCI0DRHSTR _SCI0DRH @(REG_BASE + 0x000000CE); +#define SCI0DRH _SCI0DRH.Byte +#define SCI0DRH_T8 _SCI0DRH.Bits.T8 +#define SCI0DRH_R8 _SCI0DRH.Bits.R8 + + +/*** SCI0DRL - SCI 0 Data Register Low; 0x000000CF ***/ +typedef union { + byte Byte; + struct { + byte R0_T0 :1; /* Received bit 0 or Transmit bit 0 */ + byte R1_T1 :1; /* Received bit 1 or Transmit bit 1 */ + byte R2_T2 :1; /* Received bit 2 or Transmit bit 2 */ + byte R3_T3 :1; /* Received bit 3 or Transmit bit 3 */ + byte R4_T4 :1; /* Received bit 4 or Transmit bit 4 */ + byte R5_T5 :1; /* Received bit 5 or Transmit bit 5 */ + byte R6_T6 :1; /* Received bit 6 or Transmit bit 6 */ + byte R7_T7 :1; /* Received bit 7 or Transmit bit 7 */ + } Bits; +} SCI0DRLSTR; +extern volatile SCI0DRLSTR _SCI0DRL @(REG_BASE + 0x000000CF); +#define SCI0DRL _SCI0DRL.Byte +#define SCI0DRL_R0_T0 _SCI0DRL.Bits.R0_T0 +#define SCI0DRL_R1_T1 _SCI0DRL.Bits.R1_T1 +#define SCI0DRL_R2_T2 _SCI0DRL.Bits.R2_T2 +#define SCI0DRL_R3_T3 _SCI0DRL.Bits.R3_T3 +#define SCI0DRL_R4_T4 _SCI0DRL.Bits.R4_T4 +#define SCI0DRL_R5_T5 _SCI0DRL.Bits.R5_T5 +#define SCI0DRL_R6_T6 _SCI0DRL.Bits.R6_T6 +#define SCI0DRL_R7_T7 _SCI0DRL.Bits.R7_T7 + + +/*** SCI1CR1 - SCI 1 Control Register 1; 0x000000D2 ***/ +typedef union { + byte Byte; + struct { + byte PT :1; /* Parity Type Bit */ + byte PE :1; /* Parity Enable Bit */ + byte ILT :1; /* Idle Line Type Bit */ + byte WAKE :1; /* Wakeup Condition Bit */ + byte M :1; /* Data Format Mode Bit */ + byte RSRC :1; /* Receiver Source Bit */ + byte SCISWAI :1; /* SCI 1 Stop in Wait Mode Bit */ + byte LOOPS :1; /* Loop Select Bit */ + } Bits; +} SCI1CR1STR; +extern volatile SCI1CR1STR _SCI1CR1 @(REG_BASE + 0x000000D2); +#define SCI1CR1 _SCI1CR1.Byte +#define SCI1CR1_PT _SCI1CR1.Bits.PT +#define SCI1CR1_PE _SCI1CR1.Bits.PE +#define SCI1CR1_ILT _SCI1CR1.Bits.ILT +#define SCI1CR1_WAKE _SCI1CR1.Bits.WAKE +#define SCI1CR1_M _SCI1CR1.Bits.M +#define SCI1CR1_RSRC _SCI1CR1.Bits.RSRC +#define SCI1CR1_SCISWAI _SCI1CR1.Bits.SCISWAI +#define SCI1CR1_LOOPS _SCI1CR1.Bits.LOOPS + + +/*** SCI1CR2 - SCI 1 Control Register 2; 0x000000D3 ***/ +typedef union { + byte Byte; + struct { + byte SBK :1; /* Send Break Bit */ + byte RWU :1; /* Receiver Wakeup Bit */ + byte RE :1; /* Receiver Enable Bit */ + byte TE :1; /* Transmitter Enable Bit */ + byte ILIE :1; /* Idle Line Interrupt Enable Bit */ + byte RIE :1; /* Receiver Full Interrupt Enable Bit */ + byte TCIE :1; /* Transmission Complete Interrupt Enable Bit */ + byte SCTIE :1; /* Transmitter Interrupt Enable Bit */ + } Bits; +} SCI1CR2STR; +extern volatile SCI1CR2STR _SCI1CR2 @(REG_BASE + 0x000000D3); +#define SCI1CR2 _SCI1CR2.Byte +#define SCI1CR2_SBK _SCI1CR2.Bits.SBK +#define SCI1CR2_RWU _SCI1CR2.Bits.RWU +#define SCI1CR2_RE _SCI1CR2.Bits.RE +#define SCI1CR2_TE _SCI1CR2.Bits.TE +#define SCI1CR2_ILIE _SCI1CR2.Bits.ILIE +#define SCI1CR2_RIE _SCI1CR2.Bits.RIE +#define SCI1CR2_TCIE _SCI1CR2.Bits.TCIE +#define SCI1CR2_SCTIE _SCI1CR2.Bits.SCTIE + + +/*** SCI1SR1 - SCI 1 Status Register 1; 0x000000D4 ***/ +typedef union { + byte Byte; + struct { + byte PF :1; /* Parity Error Flag */ + byte FE :1; /* Framing Error Flag */ + byte NF :1; /* Noise Flag */ + byte OR :1; /* Overrun Flag */ + byte IDLE :1; /* Idle Line Flag */ + byte RDRF :1; /* Receive Data Register Full Flag */ + byte TC :1; /* Transmit Complete Flag */ + byte TDRE :1; /* Transmit Data Register Empty Flag */ + } Bits; +} SCI1SR1STR; +extern volatile SCI1SR1STR _SCI1SR1 @(REG_BASE + 0x000000D4); +#define SCI1SR1 _SCI1SR1.Byte +#define SCI1SR1_PF _SCI1SR1.Bits.PF +#define SCI1SR1_FE _SCI1SR1.Bits.FE +#define SCI1SR1_NF _SCI1SR1.Bits.NF +#define SCI1SR1_OR _SCI1SR1.Bits.OR +#define SCI1SR1_IDLE _SCI1SR1.Bits.IDLE +#define SCI1SR1_RDRF _SCI1SR1.Bits.RDRF +#define SCI1SR1_TC _SCI1SR1.Bits.TC +#define SCI1SR1_TDRE _SCI1SR1.Bits.TDRE + + +/*** SCI1SR2 - SCI 1 Status Register 2; 0x000000D5 ***/ +typedef union { + byte Byte; + struct { + byte RAF :1; /* Receiver Active Flag */ + byte TXDIR :1; /* Transmitter pin data direction in Single-Wire mode */ + byte BRK13 :1; /* Break Transmit character length */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} SCI1SR2STR; +extern volatile SCI1SR2STR _SCI1SR2 @(REG_BASE + 0x000000D5); +#define SCI1SR2 _SCI1SR2.Byte +#define SCI1SR2_RAF _SCI1SR2.Bits.RAF +#define SCI1SR2_TXDIR _SCI1SR2.Bits.TXDIR +#define SCI1SR2_BRK13 _SCI1SR2.Bits.BRK13 + + +/*** SCI1DRH - SCI 1 Data Register High; 0x000000D6 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte T8 :1; /* Transmit Bit 8 */ + byte R8 :1; /* Received Bit 8 */ + } Bits; +} SCI1DRHSTR; +extern volatile SCI1DRHSTR _SCI1DRH @(REG_BASE + 0x000000D6); +#define SCI1DRH _SCI1DRH.Byte +#define SCI1DRH_T8 _SCI1DRH.Bits.T8 +#define SCI1DRH_R8 _SCI1DRH.Bits.R8 + + +/*** SCI1DRL - SCI 1 Data Register Low; 0x000000D7 ***/ +typedef union { + byte Byte; + struct { + byte R0_T0 :1; /* Received bit 0 or Transmit bit 0 */ + byte R1_T1 :1; /* Received bit 1 or Transmit bit 1 */ + byte R2_T2 :1; /* Received bit 2 or Transmit bit 2 */ + byte R3_T3 :1; /* Received bit 3 or Transmit bit 3 */ + byte R4_T4 :1; /* Received bit 4 or Transmit bit 4 */ + byte R5_T5 :1; /* Received bit 5 or Transmit bit 5 */ + byte R6_T6 :1; /* Received bit 6 or Transmit bit 6 */ + byte R7_T7 :1; /* Received bit 7 or Transmit bit 7 */ + } Bits; +} SCI1DRLSTR; +extern volatile SCI1DRLSTR _SCI1DRL @(REG_BASE + 0x000000D7); +#define SCI1DRL _SCI1DRL.Byte +#define SCI1DRL_R0_T0 _SCI1DRL.Bits.R0_T0 +#define SCI1DRL_R1_T1 _SCI1DRL.Bits.R1_T1 +#define SCI1DRL_R2_T2 _SCI1DRL.Bits.R2_T2 +#define SCI1DRL_R3_T3 _SCI1DRL.Bits.R3_T3 +#define SCI1DRL_R4_T4 _SCI1DRL.Bits.R4_T4 +#define SCI1DRL_R5_T5 _SCI1DRL.Bits.R5_T5 +#define SCI1DRL_R6_T6 _SCI1DRL.Bits.R6_T6 +#define SCI1DRL_R7_T7 _SCI1DRL.Bits.R7_T7 + + +/*** SPI0CR1 - SPI 0 Control Register; 0x000000D8 ***/ +typedef union { + byte Byte; + struct { + byte LSBFE :1; /* SPI 0 LSB-First Enable */ + byte SSOE :1; /* Slave Select Output Enable */ + byte CPHA :1; /* SPI 0 Clock Phase Bit */ + byte CPOL :1; /* SPI 0 Clock Polarity Bit */ + byte MSTR :1; /* SPI 0 Master/Slave Mode Select Bit */ + byte SPTIE :1; /* SPI 0 Transmit Interrupt Enable */ + byte SPE :1; /* SPI 0 System Enable Bit */ + byte SPIE :1; /* SPI 0 Interrupt Enable Bit */ + } Bits; +} SPI0CR1STR; +extern volatile SPI0CR1STR _SPI0CR1 @(REG_BASE + 0x000000D8); +#define SPI0CR1 _SPI0CR1.Byte +#define SPI0CR1_LSBFE _SPI0CR1.Bits.LSBFE +#define SPI0CR1_SSOE _SPI0CR1.Bits.SSOE +#define SPI0CR1_CPHA _SPI0CR1.Bits.CPHA +#define SPI0CR1_CPOL _SPI0CR1.Bits.CPOL +#define SPI0CR1_MSTR _SPI0CR1.Bits.MSTR +#define SPI0CR1_SPTIE _SPI0CR1.Bits.SPTIE +#define SPI0CR1_SPE _SPI0CR1.Bits.SPE +#define SPI0CR1_SPIE _SPI0CR1.Bits.SPIE + + +/*** SPI0CR2 - SPI 0 Control Register 2; 0x000000D9 ***/ +typedef union { + byte Byte; + struct { + byte SPC0 :1; /* Serial Pin Control Bit 0 */ + byte SPISWAI :1; /* SPI 0 Stop in Wait Mode Bit */ + byte :1; + byte BIDIROE :1; /* Output enable in the Bidirectional mode of operation */ + byte MODFEN :1; /* Mode Fault Enable Bit */ + byte :1; + byte :1; + byte :1; + } Bits; +} SPI0CR2STR; +extern volatile SPI0CR2STR _SPI0CR2 @(REG_BASE + 0x000000D9); +#define SPI0CR2 _SPI0CR2.Byte +#define SPI0CR2_SPC0 _SPI0CR2.Bits.SPC0 +#define SPI0CR2_SPISWAI _SPI0CR2.Bits.SPISWAI +#define SPI0CR2_BIDIROE _SPI0CR2.Bits.BIDIROE +#define SPI0CR2_MODFEN _SPI0CR2.Bits.MODFEN + + +/*** SPI0BR - SPI 0 Baud Rate Register; 0x000000DA ***/ +typedef union { + byte Byte; + struct { + byte SPR0 :1; /* SPI 0 Baud Rate Selection Bit 0 */ + byte SPR1 :1; /* SPI 0 Baud Rate Selection Bit 1 */ + byte SPR2 :1; /* SPI 0 Baud Rate Selection Bit 2 */ + byte :1; + byte SPPR0 :1; /* SPI 0 Baud Rate Preselection Bits 0 */ + byte SPPR1 :1; /* SPI 0 Baud Rate Preselection Bits 1 */ + byte SPPR2 :1; /* SPI 0 Baud Rate Preselection Bits 2 */ + byte :1; + } Bits; + struct { + byte grpSPR :3; + byte :1; + byte grpSPPR :3; + byte :1; + } MergedBits; +} SPI0BRSTR; +extern volatile SPI0BRSTR _SPI0BR @(REG_BASE + 0x000000DA); +#define SPI0BR _SPI0BR.Byte +#define SPI0BR_SPR0 _SPI0BR.Bits.SPR0 +#define SPI0BR_SPR1 _SPI0BR.Bits.SPR1 +#define SPI0BR_SPR2 _SPI0BR.Bits.SPR2 +#define SPI0BR_SPPR0 _SPI0BR.Bits.SPPR0 +#define SPI0BR_SPPR1 _SPI0BR.Bits.SPPR1 +#define SPI0BR_SPPR2 _SPI0BR.Bits.SPPR2 +#define SPI0BR_SPR _SPI0BR.MergedBits.grpSPR +#define SPI0BR_SPPR _SPI0BR.MergedBits.grpSPPR + + +/*** SPI0SR - SPI 0 Status Register; 0x000000DB ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte MODF :1; /* Mode Fault Flag */ + byte SPTEF :1; /* SPI 0 Transmit Empty Interrupt Flag */ + byte :1; + byte SPIF :1; /* SPIF Receive Interrupt Flag */ + } Bits; +} SPI0SRSTR; +extern volatile SPI0SRSTR _SPI0SR @(REG_BASE + 0x000000DB); +#define SPI0SR _SPI0SR.Byte +#define SPI0SR_MODF _SPI0SR.Bits.MODF +#define SPI0SR_SPTEF _SPI0SR.Bits.SPTEF +#define SPI0SR_SPIF _SPI0SR.Bits.SPIF + + +/*** SPI0DR - SPI 0 Data Register; 0x000000DD ***/ +typedef union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; +} SPI0DRSTR; +extern volatile SPI0DRSTR _SPI0DR @(REG_BASE + 0x000000DD); +#define SPI0DR _SPI0DR.Byte +#define SPI0DR_BIT _SPI0DR.MergedBits.grpBIT + + +/*** IBAD - IIC Address Register; 0x000000E0 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte ADR1 :1; /* Slave Address Bit 1 */ + byte ADR2 :1; /* Slave Address Bit 2 */ + byte ADR3 :1; /* Slave Address Bit 3 */ + byte ADR4 :1; /* Slave Address Bit 4 */ + byte ADR5 :1; /* Slave Address Bit 5 */ + byte ADR6 :1; /* Slave Address Bit 6 */ + byte ADR7 :1; /* Slave Address Bit 7 */ + } Bits; + struct { + byte :1; + byte grpADR_1 :7; + } MergedBits; +} IBADSTR; +extern volatile IBADSTR _IBAD @(REG_BASE + 0x000000E0); +#define IBAD _IBAD.Byte +#define IBAD_ADR1 _IBAD.Bits.ADR1 +#define IBAD_ADR2 _IBAD.Bits.ADR2 +#define IBAD_ADR3 _IBAD.Bits.ADR3 +#define IBAD_ADR4 _IBAD.Bits.ADR4 +#define IBAD_ADR5 _IBAD.Bits.ADR5 +#define IBAD_ADR6 _IBAD.Bits.ADR6 +#define IBAD_ADR7 _IBAD.Bits.ADR7 +#define IBAD_ADR_1 _IBAD.MergedBits.grpADR_1 +#define IBAD_ADR IBAD_ADR_1 + + +/*** IBFD - IIC Frequency Divider Register; 0x000000E1 ***/ +typedef union { + byte Byte; + struct { + byte IBC0 :1; /* I-Bus Clock Rate 0 */ + byte IBC1 :1; /* I-Bus Clock Rate 1 */ + byte IBC2 :1; /* I-Bus Clock Rate 2 */ + byte IBC3 :1; /* I-Bus Clock Rate 3 */ + byte IBC4 :1; /* I-Bus Clock Rate 4 */ + byte IBC5 :1; /* I-Bus Clock Rate 5 */ + byte IBC6 :1; /* I-Bus Clock Rate 6 */ + byte IBC7 :1; /* I-Bus Clock Rate 7 */ + } Bits; + struct { + byte grpIBC :8; + } MergedBits; +} IBFDSTR; +extern volatile IBFDSTR _IBFD @(REG_BASE + 0x000000E1); +#define IBFD _IBFD.Byte +#define IBFD_IBC0 _IBFD.Bits.IBC0 +#define IBFD_IBC1 _IBFD.Bits.IBC1 +#define IBFD_IBC2 _IBFD.Bits.IBC2 +#define IBFD_IBC3 _IBFD.Bits.IBC3 +#define IBFD_IBC4 _IBFD.Bits.IBC4 +#define IBFD_IBC5 _IBFD.Bits.IBC5 +#define IBFD_IBC6 _IBFD.Bits.IBC6 +#define IBFD_IBC7 _IBFD.Bits.IBC7 +#define IBFD_IBC _IBFD.MergedBits.grpIBC + + +/*** IBCR - IIC Control Register; 0x000000E2 ***/ +typedef union { + byte Byte; + struct { + byte IBSWAI :1; /* I-Bus Interface Stop in WAIT mode */ + byte :1; + byte RSTA :1; /* Repeat Start */ + byte TXAK :1; /* Transmit Acknowledge enable */ + byte TX_RX :1; /* Transmit/Receive mode select bit */ + byte MS_SL :1; /* Master/Slave mode select bit */ + byte IBIE :1; /* I-Bus Interrupt Enable */ + byte IBEN :1; /* I-Bus Enable */ + } Bits; +} IBCRSTR; +extern volatile IBCRSTR _IBCR @(REG_BASE + 0x000000E2); +#define IBCR _IBCR.Byte +#define IBCR_IBSWAI _IBCR.Bits.IBSWAI +#define IBCR_RSTA _IBCR.Bits.RSTA +#define IBCR_TXAK _IBCR.Bits.TXAK +#define IBCR_TX_RX _IBCR.Bits.TX_RX +#define IBCR_MS_SL _IBCR.Bits.MS_SL +#define IBCR_IBIE _IBCR.Bits.IBIE +#define IBCR_IBEN _IBCR.Bits.IBEN + + +/*** IBSR - IIC Status Register; 0x000000E3 ***/ +typedef union { + byte Byte; + struct { + byte RXAK :1; /* Received Acknowledge */ + byte IBIF :1; /* I-Bus Interrupt */ + byte SRW :1; /* Slave Read/Write */ + byte :1; + byte IBAL :1; /* Arbitration Lost */ + byte IBB :1; /* Bus busy bit */ + byte IAAS :1; /* Addressed as a slave bit */ + byte TCF :1; /* Data transferring bit */ + } Bits; +} IBSRSTR; +extern volatile IBSRSTR _IBSR @(REG_BASE + 0x000000E3); +#define IBSR _IBSR.Byte +#define IBSR_RXAK _IBSR.Bits.RXAK +#define IBSR_IBIF _IBSR.Bits.IBIF +#define IBSR_SRW _IBSR.Bits.SRW +#define IBSR_IBAL _IBSR.Bits.IBAL +#define IBSR_IBB _IBSR.Bits.IBB +#define IBSR_IAAS _IBSR.Bits.IAAS +#define IBSR_TCF _IBSR.Bits.TCF + + +/*** IBDR - IIC Data I/O Register; 0x000000E4 ***/ +typedef union { + byte Byte; + struct { + byte D0 :1; /* IIC Data Bit 0 */ + byte D1 :1; /* IIC Data Bit 1 */ + byte D2 :1; /* IIC Data Bit 2 */ + byte D3 :1; /* IIC Data Bit 3 */ + byte D4 :1; /* IIC Data Bit 4 */ + byte D5 :1; /* IIC Data Bit 5 */ + byte D6 :1; /* IIC Data Bit 6 */ + byte D7 :1; /* IIC Data Bit 7 */ + } Bits; + struct { + byte grpD :8; + } MergedBits; +} IBDRSTR; +extern volatile IBDRSTR _IBDR @(REG_BASE + 0x000000E4); +#define IBDR _IBDR.Byte +#define IBDR_D0 _IBDR.Bits.D0 +#define IBDR_D1 _IBDR.Bits.D1 +#define IBDR_D2 _IBDR.Bits.D2 +#define IBDR_D3 _IBDR.Bits.D3 +#define IBDR_D4 _IBDR.Bits.D4 +#define IBDR_D5 _IBDR.Bits.D5 +#define IBDR_D6 _IBDR.Bits.D6 +#define IBDR_D7 _IBDR.Bits.D7 +#define IBDR_D _IBDR.MergedBits.grpD + + +/*** DLCBCR1 - BDLC Control Register 1; 0x000000E8 ***/ +typedef union { + byte Byte; + struct { + byte WCM :1; /* Wait Clock Mode */ + byte IE :1; /* Interrupt Enable */ + byte :1; + byte :1; + byte :1; + byte :1; + byte CLKS :1; /* Clock Select */ + byte IMSG :1; /* Ignore Message */ + } Bits; +} DLCBCR1STR; +extern volatile DLCBCR1STR _DLCBCR1 @(REG_BASE + 0x000000E8); +#define DLCBCR1 _DLCBCR1.Byte +#define DLCBCR1_WCM _DLCBCR1.Bits.WCM +#define DLCBCR1_IE _DLCBCR1.Bits.IE +#define DLCBCR1_CLKS _DLCBCR1.Bits.CLKS +#define DLCBCR1_IMSG _DLCBCR1.Bits.IMSG + + +/*** DLCBSVR - BDLC State Vector Register; 0x000000E9 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte I0 :1; /* Interrupt State Vector Bit 0 */ + byte I1 :1; /* Interrupt State Vector Bit 1 */ + byte I2 :1; /* Interrupt State Vector Bit 2 */ + byte I3 :1; /* Interrupt State Vector Bit 3 */ + byte :1; + byte :1; + } Bits; + struct { + byte :1; + byte :1; + byte grpI :4; + byte :1; + byte :1; + } MergedBits; +} DLCBSVRSTR; +extern volatile DLCBSVRSTR _DLCBSVR @(REG_BASE + 0x000000E9); +#define DLCBSVR _DLCBSVR.Byte +#define DLCBSVR_I0 _DLCBSVR.Bits.I0 +#define DLCBSVR_I1 _DLCBSVR.Bits.I1 +#define DLCBSVR_I2 _DLCBSVR.Bits.I2 +#define DLCBSVR_I3 _DLCBSVR.Bits.I3 +#define DLCBSVR_I _DLCBSVR.MergedBits.grpI + + +/*** DLCBCR2 - BDLC Control Register 2; 0x000000EA ***/ +typedef union { + byte Byte; + struct { + byte TMIFR0 :1; /* Transmit In-Frame Response Control 0 */ + byte TMIFR1 :1; /* Transmit In-Frame Response Control 1 */ + byte TSIFR :1; /* Transmit In-Frame Response Control 2 */ + byte TEOD :1; /* Transmit End of Data */ + byte NBFS :1; /* Normalization Bit Format Select */ + byte RX4XE :1; /* Receive 4X Enable */ + byte DLOOP :1; /* Digital Loopback Mode */ + byte SMRST :1; /* State Machine Reset */ + } Bits; + struct { + byte grpTMIFR :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} DLCBCR2STR; +extern volatile DLCBCR2STR _DLCBCR2 @(REG_BASE + 0x000000EA); +#define DLCBCR2 _DLCBCR2.Byte +#define DLCBCR2_TMIFR0 _DLCBCR2.Bits.TMIFR0 +#define DLCBCR2_TMIFR1 _DLCBCR2.Bits.TMIFR1 +#define DLCBCR2_TSIFR _DLCBCR2.Bits.TSIFR +#define DLCBCR2_TEOD _DLCBCR2.Bits.TEOD +#define DLCBCR2_NBFS _DLCBCR2.Bits.NBFS +#define DLCBCR2_RX4XE _DLCBCR2.Bits.RX4XE +#define DLCBCR2_DLOOP _DLCBCR2.Bits.DLOOP +#define DLCBCR2_SMRST _DLCBCR2.Bits.SMRST +#define DLCBCR2_TMIFR _DLCBCR2.MergedBits.grpTMIFR + + +/*** DLCBDR - BDLC Data Register; 0x000000EB ***/ +typedef union { + byte Byte; + struct { + byte D0 :1; /* Receive/Transmit Data Bit 0 */ + byte D1 :1; /* Receive/Transmit Data Bit 1 */ + byte D2 :1; /* Receive/Transmit Data Bit 2 */ + byte D3 :1; /* Receive/Transmit Data Bit 3 */ + byte D4 :1; /* Receive/Transmit Data Bit 4 */ + byte D5 :1; /* Receive/Transmit Data Bit 5 */ + byte D6 :1; /* Receive/Transmit Data Bit 6 */ + byte D7 :1; /* Receive/Transmit Data Bit 7 */ + } Bits; + struct { + byte grpD :8; + } MergedBits; +} DLCBDRSTR; +extern volatile DLCBDRSTR _DLCBDR @(REG_BASE + 0x000000EB); +#define DLCBDR _DLCBDR.Byte +#define DLCBDR_D0 _DLCBDR.Bits.D0 +#define DLCBDR_D1 _DLCBDR.Bits.D1 +#define DLCBDR_D2 _DLCBDR.Bits.D2 +#define DLCBDR_D3 _DLCBDR.Bits.D3 +#define DLCBDR_D4 _DLCBDR.Bits.D4 +#define DLCBDR_D5 _DLCBDR.Bits.D5 +#define DLCBDR_D6 _DLCBDR.Bits.D6 +#define DLCBDR_D7 _DLCBDR.Bits.D7 +#define DLCBDR_D _DLCBDR.MergedBits.grpD + + +/*** DLCBARD - BDLC Analog Round Trip Delay Register; 0x000000EC ***/ +typedef union { + byte Byte; + struct { + byte BO0 :1; /* BDLC Analog Roundtrip Delay Offset Field 0 */ + byte BO1 :1; /* BDLC Analog Roundtrip Delay Offset Field 1 */ + byte BO2 :1; /* BDLC Analog Roundtrip Delay Offset Field 2 */ + byte BO3 :1; /* BDLC Analog Roundtrip Delay Offset Field 3 */ + byte :1; + byte :1; + byte RXPOL :1; /* Receive Pin Polarity */ + byte :1; + } Bits; + struct { + byte grpBO :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} DLCBARDSTR; +extern volatile DLCBARDSTR _DLCBARD @(REG_BASE + 0x000000EC); +#define DLCBARD _DLCBARD.Byte +#define DLCBARD_BO0 _DLCBARD.Bits.BO0 +#define DLCBARD_BO1 _DLCBARD.Bits.BO1 +#define DLCBARD_BO2 _DLCBARD.Bits.BO2 +#define DLCBARD_BO3 _DLCBARD.Bits.BO3 +#define DLCBARD_RXPOL _DLCBARD.Bits.RXPOL +#define DLCBARD_BO _DLCBARD.MergedBits.grpBO + + +/*** DLCBRSR - BDLC Rate Select Register; 0x000000ED ***/ +typedef union { + byte Byte; + struct { + byte R0 :1; /* Rate Select 0 */ + byte R1 :1; /* Rate Select 1 */ + byte R2 :1; /* Rate Select 2 */ + byte R3 :1; /* Rate Select 3 */ + byte R4 :1; /* Rate Select 4 */ + byte R5 :1; /* Rate Select 5 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpR :6; + byte :1; + byte :1; + } MergedBits; +} DLCBRSRSTR; +extern volatile DLCBRSRSTR _DLCBRSR @(REG_BASE + 0x000000ED); +#define DLCBRSR _DLCBRSR.Byte +#define DLCBRSR_R0 _DLCBRSR.Bits.R0 +#define DLCBRSR_R1 _DLCBRSR.Bits.R1 +#define DLCBRSR_R2 _DLCBRSR.Bits.R2 +#define DLCBRSR_R3 _DLCBRSR.Bits.R3 +#define DLCBRSR_R4 _DLCBRSR.Bits.R4 +#define DLCBRSR_R5 _DLCBRSR.Bits.R5 +#define DLCBRSR_R _DLCBRSR.MergedBits.grpR + + +/*** DLCSCR - BDLC Control Register; 0x000000EE ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte BDLCE :1; /* BDLC Enable */ + byte :1; + byte :1; + byte :1; + } Bits; +} DLCSCRSTR; +extern volatile DLCSCRSTR _DLCSCR @(REG_BASE + 0x000000EE); +#define DLCSCR _DLCSCR.Byte +#define DLCSCR_BDLCE _DLCSCR.Bits.BDLCE + + +/*** SPI1CR1 - SPI 1 Control Register; 0x000000F0 ***/ +typedef union { + byte Byte; + struct { + byte LSBFE :1; /* SPI 1 LSB-First Enable */ + byte SSOE :1; /* Slave Select Output Enable */ + byte CPHA :1; /* SPI 1 Clock Phase Bit */ + byte CPOL :1; /* SPI 1 Clock Polarity Bit */ + byte MSTR :1; /* SPI 1 Master/Slave Mode Select Bit */ + byte SPTIE :1; /* SPI 1 Transmit Interrupt Enable */ + byte SPE :1; /* SPI 1 System Enable Bit */ + byte SPIE :1; /* SPI 1 Interrupt Enable Bit */ + } Bits; +} SPI1CR1STR; +extern volatile SPI1CR1STR _SPI1CR1 @(REG_BASE + 0x000000F0); +#define SPI1CR1 _SPI1CR1.Byte +#define SPI1CR1_LSBFE _SPI1CR1.Bits.LSBFE +#define SPI1CR1_SSOE _SPI1CR1.Bits.SSOE +#define SPI1CR1_CPHA _SPI1CR1.Bits.CPHA +#define SPI1CR1_CPOL _SPI1CR1.Bits.CPOL +#define SPI1CR1_MSTR _SPI1CR1.Bits.MSTR +#define SPI1CR1_SPTIE _SPI1CR1.Bits.SPTIE +#define SPI1CR1_SPE _SPI1CR1.Bits.SPE +#define SPI1CR1_SPIE _SPI1CR1.Bits.SPIE + + +/*** SPI1CR2 - SPI 1 Control Register 2; 0x000000F1 ***/ +typedef union { + byte Byte; + struct { + byte SPC0 :1; /* Serial Pin Control Bit 0 */ + byte SPISWAI :1; /* SPI 1 Stop in Wait Mode Bit */ + byte :1; + byte BIDIROE :1; /* Output enable in the Bidirectional mode of operation */ + byte MODFEN :1; /* Mode Fault Enable Bit */ + byte :1; + byte :1; + byte :1; + } Bits; +} SPI1CR2STR; +extern volatile SPI1CR2STR _SPI1CR2 @(REG_BASE + 0x000000F1); +#define SPI1CR2 _SPI1CR2.Byte +#define SPI1CR2_SPC0 _SPI1CR2.Bits.SPC0 +#define SPI1CR2_SPISWAI _SPI1CR2.Bits.SPISWAI +#define SPI1CR2_BIDIROE _SPI1CR2.Bits.BIDIROE +#define SPI1CR2_MODFEN _SPI1CR2.Bits.MODFEN + + +/*** SPI1BR - SPI 1 Baud Rate Register; 0x000000F2 ***/ +typedef union { + byte Byte; + struct { + byte SPR0 :1; /* SPI 1 Baud Rate Selection Bit 0 */ + byte SPR1 :1; /* SPI 1 Baud Rate Selection Bit 1 */ + byte SPR2 :1; /* SPI 1 Baud Rate Selection Bit 2 */ + byte :1; + byte SPPR0 :1; /* SPI 1 Baud Rate Preselection Bits 0 */ + byte SPPR1 :1; /* SPI 1 Baud Rate Preselection Bits 1 */ + byte SPPR2 :1; /* SPI 1 Baud Rate Preselection Bits 2 */ + byte :1; + } Bits; + struct { + byte grpSPR :3; + byte :1; + byte grpSPPR :3; + byte :1; + } MergedBits; +} SPI1BRSTR; +extern volatile SPI1BRSTR _SPI1BR @(REG_BASE + 0x000000F2); +#define SPI1BR _SPI1BR.Byte +#define SPI1BR_SPR0 _SPI1BR.Bits.SPR0 +#define SPI1BR_SPR1 _SPI1BR.Bits.SPR1 +#define SPI1BR_SPR2 _SPI1BR.Bits.SPR2 +#define SPI1BR_SPPR0 _SPI1BR.Bits.SPPR0 +#define SPI1BR_SPPR1 _SPI1BR.Bits.SPPR1 +#define SPI1BR_SPPR2 _SPI1BR.Bits.SPPR2 +#define SPI1BR_SPR _SPI1BR.MergedBits.grpSPR +#define SPI1BR_SPPR _SPI1BR.MergedBits.grpSPPR + + +/*** SPI1SR - SPI 1 Status Register; 0x000000F3 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte MODF :1; /* Mode Fault Flag */ + byte SPTEF :1; /* SPI 1 Transmit Empty Interrupt Flag */ + byte :1; + byte SPIF :1; /* SPIF Receive Interrupt Flag */ + } Bits; +} SPI1SRSTR; +extern volatile SPI1SRSTR _SPI1SR @(REG_BASE + 0x000000F3); +#define SPI1SR _SPI1SR.Byte +#define SPI1SR_MODF _SPI1SR.Bits.MODF +#define SPI1SR_SPTEF _SPI1SR.Bits.SPTEF +#define SPI1SR_SPIF _SPI1SR.Bits.SPIF + + +/*** SPI1DR - SPI 1 Data Register; 0x000000F5 ***/ +typedef union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; +} SPI1DRSTR; +extern volatile SPI1DRSTR _SPI1DR @(REG_BASE + 0x000000F5); +#define SPI1DR _SPI1DR.Byte +#define SPI1DR_BIT _SPI1DR.MergedBits.grpBIT + + +/*** SPI2CR1 - SPI 2 Control Register; 0x000000F8 ***/ +typedef union { + byte Byte; + struct { + byte LSBFE :1; /* SPI 2 LSB-First Enable */ + byte SSOE :1; /* Slave Select Output Enable */ + byte CPHA :1; /* SPI 2 Clock Phase Bit */ + byte CPOL :1; /* SPI 2 Clock Polarity Bit */ + byte MSTR :1; /* SPI 2 Master/Slave Mode Select Bit */ + byte SPTIE :1; /* SPI 2 Transmit Interrupt Enable */ + byte SPE :1; /* SPI 2 System Enable Bit */ + byte SPIE :1; /* SPI 2 Interrupt Enable Bit */ + } Bits; +} SPI2CR1STR; +extern volatile SPI2CR1STR _SPI2CR1 @(REG_BASE + 0x000000F8); +#define SPI2CR1 _SPI2CR1.Byte +#define SPI2CR1_LSBFE _SPI2CR1.Bits.LSBFE +#define SPI2CR1_SSOE _SPI2CR1.Bits.SSOE +#define SPI2CR1_CPHA _SPI2CR1.Bits.CPHA +#define SPI2CR1_CPOL _SPI2CR1.Bits.CPOL +#define SPI2CR1_MSTR _SPI2CR1.Bits.MSTR +#define SPI2CR1_SPTIE _SPI2CR1.Bits.SPTIE +#define SPI2CR1_SPE _SPI2CR1.Bits.SPE +#define SPI2CR1_SPIE _SPI2CR1.Bits.SPIE + + +/*** SPI2CR2 - SPI 2 Control Register 2; 0x000000F9 ***/ +typedef union { + byte Byte; + struct { + byte SPC0 :1; /* Serial Pin Control Bit 0 */ + byte SPISWAI :1; /* SPI 2 Stop in Wait Mode Bit */ + byte :1; + byte BIDIROE :1; /* Output enable in the Bidirectional mode of operation */ + byte MODFEN :1; /* Mode Fault Enable Bit */ + byte :1; + byte :1; + byte :1; + } Bits; +} SPI2CR2STR; +extern volatile SPI2CR2STR _SPI2CR2 @(REG_BASE + 0x000000F9); +#define SPI2CR2 _SPI2CR2.Byte +#define SPI2CR2_SPC0 _SPI2CR2.Bits.SPC0 +#define SPI2CR2_SPISWAI _SPI2CR2.Bits.SPISWAI +#define SPI2CR2_BIDIROE _SPI2CR2.Bits.BIDIROE +#define SPI2CR2_MODFEN _SPI2CR2.Bits.MODFEN + + +/*** SPI2BR - SPI 2 Baud Rate Register; 0x000000FA ***/ +typedef union { + byte Byte; + struct { + byte SPR0 :1; /* SPI 2 Baud Rate Selection Bit 0 */ + byte SPR1 :1; /* SPI 2 Baud Rate Selection Bit 1 */ + byte SPR2 :1; /* SPI 2 Baud Rate Selection Bit 2 */ + byte :1; + byte SPPR0 :1; /* SPI 2 Baud Rate Preselection Bits 0 */ + byte SPPR1 :1; /* SPI 2 Baud Rate Preselection Bits 1 */ + byte SPPR2 :1; /* SPI 2 Baud Rate Preselection Bits 2 */ + byte :1; + } Bits; + struct { + byte grpSPR :3; + byte :1; + byte grpSPPR :3; + byte :1; + } MergedBits; +} SPI2BRSTR; +extern volatile SPI2BRSTR _SPI2BR @(REG_BASE + 0x000000FA); +#define SPI2BR _SPI2BR.Byte +#define SPI2BR_SPR0 _SPI2BR.Bits.SPR0 +#define SPI2BR_SPR1 _SPI2BR.Bits.SPR1 +#define SPI2BR_SPR2 _SPI2BR.Bits.SPR2 +#define SPI2BR_SPPR0 _SPI2BR.Bits.SPPR0 +#define SPI2BR_SPPR1 _SPI2BR.Bits.SPPR1 +#define SPI2BR_SPPR2 _SPI2BR.Bits.SPPR2 +#define SPI2BR_SPR _SPI2BR.MergedBits.grpSPR +#define SPI2BR_SPPR _SPI2BR.MergedBits.grpSPPR + + +/*** SPI2SR - SPI 2 Status Register; 0x000000FB ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte MODF :1; /* Mode Fault Flag */ + byte SPTEF :1; /* SPI 2 Transmit Empty Interrupt Flag */ + byte :1; + byte SPIF :1; /* SPIF Receive Interrupt Flag */ + } Bits; +} SPI2SRSTR; +extern volatile SPI2SRSTR _SPI2SR @(REG_BASE + 0x000000FB); +#define SPI2SR _SPI2SR.Byte +#define SPI2SR_MODF _SPI2SR.Bits.MODF +#define SPI2SR_SPTEF _SPI2SR.Bits.SPTEF +#define SPI2SR_SPIF _SPI2SR.Bits.SPIF + + +/*** SPI2DR - SPI 2 Data Register; 0x000000FD ***/ +typedef union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; +} SPI2DRSTR; +extern volatile SPI2DRSTR _SPI2DR @(REG_BASE + 0x000000FD); +#define SPI2DR _SPI2DR.Byte +#define SPI2DR_BIT _SPI2DR.MergedBits.grpBIT + + +/*** FCLKDIV - Flash Clock Divider Register; 0x00000100 ***/ +typedef union { + byte Byte; + struct { + byte FDIV0 :1; /* Flash Clock Divider Bit 0 */ + byte FDIV1 :1; /* Flash Clock Divider Bit 1 */ + byte FDIV2 :1; /* Flash Clock Divider Bit 2 */ + byte FDIV3 :1; /* Flash Clock Divider Bit 3 */ + byte FDIV4 :1; /* Flash Clock Divider Bit 4 */ + byte FDIV5 :1; /* Flash Clock Divider Bit 5 */ + byte PRDIV8 :1; /* Enable Prescaler by 8 */ + byte FDIVLD :1; /* Flash Clock Divider Loaded */ + } Bits; + struct { + byte grpFDIV :6; + byte grpPRDIV_8 :1; + byte :1; + } MergedBits; +} FCLKDIVSTR; +extern volatile FCLKDIVSTR _FCLKDIV @(REG_BASE + 0x00000100); +#define FCLKDIV _FCLKDIV.Byte +#define FCLKDIV_FDIV0 _FCLKDIV.Bits.FDIV0 +#define FCLKDIV_FDIV1 _FCLKDIV.Bits.FDIV1 +#define FCLKDIV_FDIV2 _FCLKDIV.Bits.FDIV2 +#define FCLKDIV_FDIV3 _FCLKDIV.Bits.FDIV3 +#define FCLKDIV_FDIV4 _FCLKDIV.Bits.FDIV4 +#define FCLKDIV_FDIV5 _FCLKDIV.Bits.FDIV5 +#define FCLKDIV_PRDIV8 _FCLKDIV.Bits.PRDIV8 +#define FCLKDIV_FDIVLD _FCLKDIV.Bits.FDIVLD +#define FCLKDIV_FDIV _FCLKDIV.MergedBits.grpFDIV + + +/*** FSEC - Flash Security Register; 0x00000101 ***/ +typedef union { + byte Byte; + struct { + byte SEC0 :1; /* Memory security bit 0 */ + byte SEC1 :1; /* Memory security bit 1 */ + byte NV2 :1; /* Non Volatile flag bit 2 */ + byte NV3 :1; /* Non Volatile flag bit 3 */ + byte NV4 :1; /* Non Volatile flag bit 4 */ + byte NV5 :1; /* Non Volatile flag bit 5 */ + byte NV6 :1; /* Non Volatile flag bit 6 */ + byte KEYEN :1; /* Enable backdoor key to security */ + } Bits; + struct { + byte grpSEC :2; + byte grpNV_2 :5; + byte :1; + } MergedBits; +} FSECSTR; +extern volatile FSECSTR _FSEC @(REG_BASE + 0x00000101); +#define FSEC _FSEC.Byte +#define FSEC_SEC0 _FSEC.Bits.SEC0 +#define FSEC_SEC1 _FSEC.Bits.SEC1 +#define FSEC_NV2 _FSEC.Bits.NV2 +#define FSEC_NV3 _FSEC.Bits.NV3 +#define FSEC_NV4 _FSEC.Bits.NV4 +#define FSEC_NV5 _FSEC.Bits.NV5 +#define FSEC_NV6 _FSEC.Bits.NV6 +#define FSEC_KEYEN _FSEC.Bits.KEYEN +#define FSEC_SEC _FSEC.MergedBits.grpSEC +#define FSEC_NV_2 _FSEC.MergedBits.grpNV_2 +#define FSEC_NV FSEC_NV_2 + + +/*** FCNFG - Flash Configuration Register; 0x00000103 ***/ +typedef union { + byte Byte; + struct { + byte BKSEL0 :1; /* Register bank select 0 */ + byte BKSEL1 :1; /* Register bank select 1 */ + byte :1; + byte :1; + byte :1; + byte KEYACC :1; /* Enable Security Key Writing */ + byte CCIE :1; /* Command Complete Interrupt Enable */ + byte CBEIE :1; /* Command Buffers Empty Interrupt Enable */ + } Bits; + struct { + byte grpBKSEL :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} FCNFGSTR; +extern volatile FCNFGSTR _FCNFG @(REG_BASE + 0x00000103); +#define FCNFG _FCNFG.Byte +#define FCNFG_BKSEL0 _FCNFG.Bits.BKSEL0 +#define FCNFG_BKSEL1 _FCNFG.Bits.BKSEL1 +#define FCNFG_KEYACC _FCNFG.Bits.KEYACC +#define FCNFG_CCIE _FCNFG.Bits.CCIE +#define FCNFG_CBEIE _FCNFG.Bits.CBEIE +#define FCNFG_BKSEL _FCNFG.MergedBits.grpBKSEL + + +/*** FPROT - Flash Protection Register; 0x00000104 ***/ +typedef union { + byte Byte; + struct { + byte FPLS0 :1; /* Flash Protection Lower Address size 0 */ + byte FPLS1 :1; /* Flash Protection Lower Address size 1 */ + byte FPLDIS :1; /* Flash Protection Lower address range disable */ + byte FPHS0 :1; /* Flash Protection Higher address size 0 */ + byte FPHS1 :1; /* Flash Protection Higher address size 1 */ + byte FPHDIS :1; /* Flash Protection Higher address range disable */ + byte NV6 :1; /* Non Volatile Flag Bit */ + byte FPOPEN :1; /* Opens the flash block or subsections of it for program or erase */ + } Bits; + struct { + byte grpFPLS :2; + byte :1; + byte grpFPHS :2; + byte :1; + byte grpNV_6 :1; + byte :1; + } MergedBits; +} FPROTSTR; +extern volatile FPROTSTR _FPROT @(REG_BASE + 0x00000104); +#define FPROT _FPROT.Byte +#define FPROT_FPLS0 _FPROT.Bits.FPLS0 +#define FPROT_FPLS1 _FPROT.Bits.FPLS1 +#define FPROT_FPLDIS _FPROT.Bits.FPLDIS +#define FPROT_FPHS0 _FPROT.Bits.FPHS0 +#define FPROT_FPHS1 _FPROT.Bits.FPHS1 +#define FPROT_FPHDIS _FPROT.Bits.FPHDIS +#define FPROT_NV6 _FPROT.Bits.NV6 +#define FPROT_FPOPEN _FPROT.Bits.FPOPEN +#define FPROT_FPLS _FPROT.MergedBits.grpFPLS +#define FPROT_FPHS _FPROT.MergedBits.grpFPHS + + +/*** FSTAT - Flash Status Register; 0x00000105 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte BLANK :1; /* Blank Verify Flag */ + byte :1; + byte ACCERR :1; /* Access error */ + byte PVIOL :1; /* Protection violation */ + byte CCIF :1; /* Command Complete Interrupt Flag */ + byte CBEIF :1; /* Command Buffers Empty Interrupt Flag */ + } Bits; +} FSTATSTR; +extern volatile FSTATSTR _FSTAT @(REG_BASE + 0x00000105); +#define FSTAT _FSTAT.Byte +#define FSTAT_BLANK _FSTAT.Bits.BLANK +#define FSTAT_ACCERR _FSTAT.Bits.ACCERR +#define FSTAT_PVIOL _FSTAT.Bits.PVIOL +#define FSTAT_CCIF _FSTAT.Bits.CCIF +#define FSTAT_CBEIF _FSTAT.Bits.CBEIF + + +/*** FCMD - Flash Command Buffer and Register; 0x00000106 ***/ +typedef union { + byte Byte; + struct { + byte CMDB0 :1; /* NVM User Mode Command Bit 0 */ + byte :1; + byte CMDB2 :1; /* NVM User Mode Command Bit 2 */ + byte :1; + byte :1; + byte CMDB5 :1; /* NVM User Mode Command Bit 5 */ + byte CMDB6 :1; /* NVM User Mode Command Bit 6 */ + byte :1; + } Bits; + struct { + byte grpCMDB :1; + byte :1; + byte grpCMDB_2 :1; + byte :1; + byte :1; + byte grpCMDB_5 :2; + byte :1; + } MergedBits; +} FCMDSTR; +extern volatile FCMDSTR _FCMD @(REG_BASE + 0x00000106); +#define FCMD _FCMD.Byte +#define FCMD_CMDB0 _FCMD.Bits.CMDB0 +#define FCMD_CMDB2 _FCMD.Bits.CMDB2 +#define FCMD_CMDB5 _FCMD.Bits.CMDB5 +#define FCMD_CMDB6 _FCMD.Bits.CMDB6 +#define FCMD_CMDB_5 _FCMD.MergedBits.grpCMDB_5 +#define FCMD_CMDB FCMD_CMDB_5 + + +/*** ECLKDIV - EEPROM Clock Divider Register; 0x00000110 ***/ +typedef union { + byte Byte; + struct { + byte EDIV0 :1; /* EEPROM Clock Divider 0 */ + byte EDIV1 :1; /* EEPROM Clock Divider 1 */ + byte EDIV2 :1; /* EEPROM Clock Divider 2 */ + byte EDIV3 :1; /* EEPROM Clock Divider 3 */ + byte EDIV4 :1; /* EEPROM Clock Divider 4 */ + byte EDIV5 :1; /* EEPROM Clock Divider 5 */ + byte PRDIV8 :1; /* Enable Prescaler by 8 */ + byte EDIVLD :1; /* EEPROM Clock Divider Loaded */ + } Bits; + struct { + byte grpEDIV :6; + byte grpPRDIV_8 :1; + byte :1; + } MergedBits; +} ECLKDIVSTR; +extern volatile ECLKDIVSTR _ECLKDIV @(REG_BASE + 0x00000110); +#define ECLKDIV _ECLKDIV.Byte +#define ECLKDIV_EDIV0 _ECLKDIV.Bits.EDIV0 +#define ECLKDIV_EDIV1 _ECLKDIV.Bits.EDIV1 +#define ECLKDIV_EDIV2 _ECLKDIV.Bits.EDIV2 +#define ECLKDIV_EDIV3 _ECLKDIV.Bits.EDIV3 +#define ECLKDIV_EDIV4 _ECLKDIV.Bits.EDIV4 +#define ECLKDIV_EDIV5 _ECLKDIV.Bits.EDIV5 +#define ECLKDIV_PRDIV8 _ECLKDIV.Bits.PRDIV8 +#define ECLKDIV_EDIVLD _ECLKDIV.Bits.EDIVLD +#define ECLKDIV_EDIV _ECLKDIV.MergedBits.grpEDIV + + +/*** ECNFG - EEPROM Configuration Register; 0x00000113 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte CCIE :1; /* Command Complete Interrupt Enable */ + byte CBEIE :1; /* Command Buffers Empty Interrupt Enable */ + } Bits; +} ECNFGSTR; +extern volatile ECNFGSTR _ECNFG @(REG_BASE + 0x00000113); +#define ECNFG _ECNFG.Byte +#define ECNFG_CCIE _ECNFG.Bits.CCIE +#define ECNFG_CBEIE _ECNFG.Bits.CBEIE + + +/*** EPROT - EEPROM Protection Register; 0x00000114 ***/ +typedef union { + byte Byte; + struct { + byte EP0 :1; /* EEPROM Protection address size 0 */ + byte EP1 :1; /* EEPROM Protection address size 1 */ + byte EP2 :1; /* EEPROM Protection address size 2 */ + byte EPDIS :1; /* EEPROM Protection disable */ + byte :1; + byte :1; + byte :1; + byte EPOPEN :1; /* Opens the EEPROM block or a subsection of it for program or erase */ + } Bits; + struct { + byte grpEP :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} EPROTSTR; +extern volatile EPROTSTR _EPROT @(REG_BASE + 0x00000114); +#define EPROT _EPROT.Byte +#define EPROT_EP0 _EPROT.Bits.EP0 +#define EPROT_EP1 _EPROT.Bits.EP1 +#define EPROT_EP2 _EPROT.Bits.EP2 +#define EPROT_EPDIS _EPROT.Bits.EPDIS +#define EPROT_EPOPEN _EPROT.Bits.EPOPEN +#define EPROT_EP _EPROT.MergedBits.grpEP + + +/*** ESTAT - EEPROM Status Register; 0x00000115 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte BLANK :1; /* Blank Verify Flag */ + byte :1; + byte ACCERR :1; /* Access error */ + byte PVIOL :1; /* Protection violation */ + byte CCIF :1; /* Command Complete Interrupt Flag */ + byte CBEIF :1; /* Command Buffer Empty Interrupt Flag */ + } Bits; +} ESTATSTR; +extern volatile ESTATSTR _ESTAT @(REG_BASE + 0x00000115); +#define ESTAT _ESTAT.Byte +#define ESTAT_BLANK _ESTAT.Bits.BLANK +#define ESTAT_ACCERR _ESTAT.Bits.ACCERR +#define ESTAT_PVIOL _ESTAT.Bits.PVIOL +#define ESTAT_CCIF _ESTAT.Bits.CCIF +#define ESTAT_CBEIF _ESTAT.Bits.CBEIF + + +/*** ECMD - EEPROM Command Buffer and Register; 0x00000116 ***/ +typedef union { + byte Byte; + struct { + byte CMDB0 :1; /* EEPROM User Mode Command 0 */ + byte :1; + byte CMDB2 :1; /* EEPROM User Mode Command 2 */ + byte :1; + byte :1; + byte CMDB5 :1; /* EEPROM User Mode Command 5 */ + byte CMDB6 :1; /* EEPROM User Mode Command 6 */ + byte :1; + } Bits; + struct { + byte grpCMDB :1; + byte :1; + byte grpCMDB_2 :1; + byte :1; + byte :1; + byte grpCMDB_5 :2; + byte :1; + } MergedBits; +} ECMDSTR; +extern volatile ECMDSTR _ECMD @(REG_BASE + 0x00000116); +#define ECMD _ECMD.Byte +#define ECMD_CMDB0 _ECMD.Bits.CMDB0 +#define ECMD_CMDB2 _ECMD.Bits.CMDB2 +#define ECMD_CMDB5 _ECMD.Bits.CMDB5 +#define ECMD_CMDB6 _ECMD.Bits.CMDB6 +#define ECMD_CMDB_5 _ECMD.MergedBits.grpCMDB_5 +#define ECMD_CMDB ECMD_CMDB_5 + + +/*** ATD1STAT0 - ATD 1 Status Register 0; 0x00000126 ***/ +typedef union { + byte Byte; + struct { + byte CC0 :1; /* Conversion Counter 0 */ + byte CC1 :1; /* Conversion Counter 1 */ + byte CC2 :1; /* Conversion Counter 2 */ + byte :1; + byte FIFOR :1; /* FIFO Over Run Flag */ + byte ETORF :1; /* External Trigger Overrun Flag */ + byte :1; + byte SCF :1; /* Sequence Complete Flag */ + } Bits; + struct { + byte grpCC :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} ATD1STAT0STR; +extern volatile ATD1STAT0STR _ATD1STAT0 @(REG_BASE + 0x00000126); +#define ATD1STAT0 _ATD1STAT0.Byte +#define ATD1STAT0_CC0 _ATD1STAT0.Bits.CC0 +#define ATD1STAT0_CC1 _ATD1STAT0.Bits.CC1 +#define ATD1STAT0_CC2 _ATD1STAT0.Bits.CC2 +#define ATD1STAT0_FIFOR _ATD1STAT0.Bits.FIFOR +#define ATD1STAT0_ETORF _ATD1STAT0.Bits.ETORF +#define ATD1STAT0_SCF _ATD1STAT0.Bits.SCF +#define ATD1STAT0_CC _ATD1STAT0.MergedBits.grpCC + + +/*** ATD1STAT1 - ATD 1 Status Register 1; 0x0000012B ***/ +typedef union { + byte Byte; + struct { + byte CCF0 :1; /* Conversion Complete Flag 0 */ + byte CCF1 :1; /* Conversion Complete Flag 1 */ + byte CCF2 :1; /* Conversion Complete Flag 2 */ + byte CCF3 :1; /* Conversion Complete Flag 3 */ + byte CCF4 :1; /* Conversion Complete Flag 4 */ + byte CCF5 :1; /* Conversion Complete Flag 5 */ + byte CCF6 :1; /* Conversion Complete Flag 6 */ + byte CCF7 :1; /* Conversion Complete Flag 7 */ + } Bits; + struct { + byte grpCCF :8; + } MergedBits; +} ATD1STAT1STR; +extern volatile ATD1STAT1STR _ATD1STAT1 @(REG_BASE + 0x0000012B); +#define ATD1STAT1 _ATD1STAT1.Byte +#define ATD1STAT1_CCF0 _ATD1STAT1.Bits.CCF0 +#define ATD1STAT1_CCF1 _ATD1STAT1.Bits.CCF1 +#define ATD1STAT1_CCF2 _ATD1STAT1.Bits.CCF2 +#define ATD1STAT1_CCF3 _ATD1STAT1.Bits.CCF3 +#define ATD1STAT1_CCF4 _ATD1STAT1.Bits.CCF4 +#define ATD1STAT1_CCF5 _ATD1STAT1.Bits.CCF5 +#define ATD1STAT1_CCF6 _ATD1STAT1.Bits.CCF6 +#define ATD1STAT1_CCF7 _ATD1STAT1.Bits.CCF7 +#define ATD1STAT1_CCF _ATD1STAT1.MergedBits.grpCCF + + +/*** ATD1DIEN - ATD 1 Input Enable Mask Register; 0x0000012D ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* Disable/Enable Digital Input Buffer Bit 0 */ + byte BIT1 :1; /* Disable/Enable Digital Input Buffer Bit 1 */ + byte BIT2 :1; /* Disable/Enable Digital Input Buffer Bit 2 */ + byte BIT3 :1; /* Disable/Enable Digital Input Buffer Bit 3 */ + byte BIT4 :1; /* Disable/Enable Digital Input Buffer Bit 4 */ + byte BIT5 :1; /* Disable/Enable Digital Input Buffer Bit 5 */ + byte BIT6 :1; /* Disable/Enable Digital Input Buffer Bit 6 */ + byte BIT7 :1; /* Disable/Enable Digital Input Buffer Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} ATD1DIENSTR; +extern volatile ATD1DIENSTR _ATD1DIEN @(REG_BASE + 0x0000012D); +#define ATD1DIEN _ATD1DIEN.Byte +#define ATD1DIEN_BIT0 _ATD1DIEN.Bits.BIT0 +#define ATD1DIEN_BIT1 _ATD1DIEN.Bits.BIT1 +#define ATD1DIEN_BIT2 _ATD1DIEN.Bits.BIT2 +#define ATD1DIEN_BIT3 _ATD1DIEN.Bits.BIT3 +#define ATD1DIEN_BIT4 _ATD1DIEN.Bits.BIT4 +#define ATD1DIEN_BIT5 _ATD1DIEN.Bits.BIT5 +#define ATD1DIEN_BIT6 _ATD1DIEN.Bits.BIT6 +#define ATD1DIEN_BIT7 _ATD1DIEN.Bits.BIT7 +#define ATD1DIEN_BIT _ATD1DIEN.MergedBits.grpBIT + + +/*** PORTAD1 - Port AD1 Register; 0x0000012F ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* AN0 */ + byte BIT1 :1; /* AN1 */ + byte BIT2 :1; /* AN2 */ + byte BIT3 :1; /* AN3 */ + byte BIT4 :1; /* AN4 */ + byte BIT5 :1; /* AN5 */ + byte BIT6 :1; /* AN6 */ + byte BIT7 :1; /* AN7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} PORTAD1STR; +extern volatile PORTAD1STR _PORTAD1 @(REG_BASE + 0x0000012F); +#define PORTAD1 _PORTAD1.Byte +#define PORTAD1_BIT0 _PORTAD1.Bits.BIT0 +#define PORTAD1_BIT1 _PORTAD1.Bits.BIT1 +#define PORTAD1_BIT2 _PORTAD1.Bits.BIT2 +#define PORTAD1_BIT3 _PORTAD1.Bits.BIT3 +#define PORTAD1_BIT4 _PORTAD1.Bits.BIT4 +#define PORTAD1_BIT5 _PORTAD1.Bits.BIT5 +#define PORTAD1_BIT6 _PORTAD1.Bits.BIT6 +#define PORTAD1_BIT7 _PORTAD1.Bits.BIT7 +#define PORTAD1_BIT _PORTAD1.MergedBits.grpBIT + + +/*** CAN0CTL0 - MSCAN 0 Control 0 Register; 0x00000140 ***/ +typedef union { + byte Byte; + struct { + byte INITRQ :1; /* Initialization Mode Request */ + byte SLPRQ :1; /* Sleep Mode Request */ + byte WUPE :1; /* Wake-Up Enable */ + byte TIME :1; /* Timer Enable */ + byte SYNCH :1; /* Synchronized Status */ + byte CSWAI :1; /* CAN Stops in Wait Mode */ + byte RXACT :1; /* Receiver Active Status */ + byte RXFRM :1; /* Received Frame Flag */ + } Bits; +} CAN0CTL0STR; +extern volatile CAN0CTL0STR _CAN0CTL0 @(REG_BASE + 0x00000140); +#define CAN0CTL0 _CAN0CTL0.Byte +#define CAN0CTL0_INITRQ _CAN0CTL0.Bits.INITRQ +#define CAN0CTL0_SLPRQ _CAN0CTL0.Bits.SLPRQ +#define CAN0CTL0_WUPE _CAN0CTL0.Bits.WUPE +#define CAN0CTL0_TIME _CAN0CTL0.Bits.TIME +#define CAN0CTL0_SYNCH _CAN0CTL0.Bits.SYNCH +#define CAN0CTL0_CSWAI _CAN0CTL0.Bits.CSWAI +#define CAN0CTL0_RXACT _CAN0CTL0.Bits.RXACT +#define CAN0CTL0_RXFRM _CAN0CTL0.Bits.RXFRM + + +/*** CAN0CTL1 - MSCAN 0 Control 1 Register; 0x00000141 ***/ +typedef union { + byte Byte; + struct { + byte INITAK :1; /* Initialization Mode Acknowledge */ + byte SLPAK :1; /* Sleep Mode Acknowledge */ + byte WUPM :1; /* Wake-Up Mode */ + byte :1; + byte LISTEN :1; /* Listen Only Mode */ + byte LOOPB :1; /* Loop Back Self Test Mode */ + byte CLKSRC :1; /* MSCAN 0 Clock Source */ + byte CANE :1; /* MSCAN 0 Enable */ + } Bits; +} CAN0CTL1STR; +extern volatile CAN0CTL1STR _CAN0CTL1 @(REG_BASE + 0x00000141); +#define CAN0CTL1 _CAN0CTL1.Byte +#define CAN0CTL1_INITAK _CAN0CTL1.Bits.INITAK +#define CAN0CTL1_SLPAK _CAN0CTL1.Bits.SLPAK +#define CAN0CTL1_WUPM _CAN0CTL1.Bits.WUPM +#define CAN0CTL1_LISTEN _CAN0CTL1.Bits.LISTEN +#define CAN0CTL1_LOOPB _CAN0CTL1.Bits.LOOPB +#define CAN0CTL1_CLKSRC _CAN0CTL1.Bits.CLKSRC +#define CAN0CTL1_CANE _CAN0CTL1.Bits.CANE + + +/*** CAN0BTR0 - MSCAN 0 Bus Timing Register 0; 0x00000142 ***/ +typedef union { + byte Byte; + struct { + byte BRP0 :1; /* Baud Rate Prescaler 0 */ + byte BRP1 :1; /* Baud Rate Prescaler 1 */ + byte BRP2 :1; /* Baud Rate Prescaler 2 */ + byte BRP3 :1; /* Baud Rate Prescaler 3 */ + byte BRP4 :1; /* Baud Rate Prescaler 4 */ + byte BRP5 :1; /* Baud Rate Prescaler 5 */ + byte SJW0 :1; /* Synchronization Jump Width 0 */ + byte SJW1 :1; /* Synchronization Jump Width 1 */ + } Bits; + struct { + byte grpBRP :6; + byte grpSJW :2; + } MergedBits; +} CAN0BTR0STR; +extern volatile CAN0BTR0STR _CAN0BTR0 @(REG_BASE + 0x00000142); +#define CAN0BTR0 _CAN0BTR0.Byte +#define CAN0BTR0_BRP0 _CAN0BTR0.Bits.BRP0 +#define CAN0BTR0_BRP1 _CAN0BTR0.Bits.BRP1 +#define CAN0BTR0_BRP2 _CAN0BTR0.Bits.BRP2 +#define CAN0BTR0_BRP3 _CAN0BTR0.Bits.BRP3 +#define CAN0BTR0_BRP4 _CAN0BTR0.Bits.BRP4 +#define CAN0BTR0_BRP5 _CAN0BTR0.Bits.BRP5 +#define CAN0BTR0_SJW0 _CAN0BTR0.Bits.SJW0 +#define CAN0BTR0_SJW1 _CAN0BTR0.Bits.SJW1 +#define CAN0BTR0_BRP _CAN0BTR0.MergedBits.grpBRP +#define CAN0BTR0_SJW _CAN0BTR0.MergedBits.grpSJW + + +/*** CAN0BTR1 - MSCAN 0 Bus Timing Register 1; 0x00000143 ***/ +typedef union { + byte Byte; + struct { + byte TSEG10 :1; /* Time Segment 1 */ + byte TSEG11 :1; /* Time Segment 1 */ + byte TSEG12 :1; /* Time Segment 1 */ + byte TSEG13 :1; /* Time Segment 1 */ + byte TSEG20 :1; /* Time Segment 2 */ + byte TSEG21 :1; /* Time Segment 2 */ + byte TSEG22 :1; /* Time Segment 2 */ + byte SAMP :1; /* Sampling */ + } Bits; + struct { + byte grpTSEG_10 :4; + byte grpTSEG_20 :3; + byte :1; + } MergedBits; +} CAN0BTR1STR; +extern volatile CAN0BTR1STR _CAN0BTR1 @(REG_BASE + 0x00000143); +#define CAN0BTR1 _CAN0BTR1.Byte +#define CAN0BTR1_TSEG10 _CAN0BTR1.Bits.TSEG10 +#define CAN0BTR1_TSEG11 _CAN0BTR1.Bits.TSEG11 +#define CAN0BTR1_TSEG12 _CAN0BTR1.Bits.TSEG12 +#define CAN0BTR1_TSEG13 _CAN0BTR1.Bits.TSEG13 +#define CAN0BTR1_TSEG20 _CAN0BTR1.Bits.TSEG20 +#define CAN0BTR1_TSEG21 _CAN0BTR1.Bits.TSEG21 +#define CAN0BTR1_TSEG22 _CAN0BTR1.Bits.TSEG22 +#define CAN0BTR1_SAMP _CAN0BTR1.Bits.SAMP +#define CAN0BTR1_TSEG_10 _CAN0BTR1.MergedBits.grpTSEG_10 +#define CAN0BTR1_TSEG_20 _CAN0BTR1.MergedBits.grpTSEG_20 +#define CAN0BTR1_TSEG CAN0BTR1_TSEG_10 + + +/*** CAN0RFLG - MSCAN 0 Receiver Flag Register; 0x00000144 ***/ +typedef union { + byte Byte; + struct { + byte RXF :1; /* Receive Buffer Full */ + byte OVRIF :1; /* Overrun Interrupt Flag */ + byte TSTAT0 :1; /* Transmitter Status Bit 0 */ + byte TSTAT1 :1; /* Transmitter Status Bit 1 */ + byte RSTAT0 :1; /* Receiver Status Bit 0 */ + byte RSTAT1 :1; /* Receiver Status Bit 1 */ + byte CSCIF :1; /* CAN Status Change Interrupt Flag */ + byte WUPIF :1; /* Wake-up Interrupt Flag */ + } Bits; + struct { + byte :1; + byte :1; + byte grpTSTAT :2; + byte grpRSTAT :2; + byte :1; + byte :1; + } MergedBits; +} CAN0RFLGSTR; +extern volatile CAN0RFLGSTR _CAN0RFLG @(REG_BASE + 0x00000144); +#define CAN0RFLG _CAN0RFLG.Byte +#define CAN0RFLG_RXF _CAN0RFLG.Bits.RXF +#define CAN0RFLG_OVRIF _CAN0RFLG.Bits.OVRIF +#define CAN0RFLG_TSTAT0 _CAN0RFLG.Bits.TSTAT0 +#define CAN0RFLG_TSTAT1 _CAN0RFLG.Bits.TSTAT1 +#define CAN0RFLG_RSTAT0 _CAN0RFLG.Bits.RSTAT0 +#define CAN0RFLG_RSTAT1 _CAN0RFLG.Bits.RSTAT1 +#define CAN0RFLG_CSCIF _CAN0RFLG.Bits.CSCIF +#define CAN0RFLG_WUPIF _CAN0RFLG.Bits.WUPIF +#define CAN0RFLG_TSTAT _CAN0RFLG.MergedBits.grpTSTAT +#define CAN0RFLG_RSTAT _CAN0RFLG.MergedBits.grpRSTAT + + +/*** CAN0RIER - MSCAN 0 Receiver Interrupt Enable Register; 0x00000145 ***/ +typedef union { + byte Byte; + struct { + byte RXFIE :1; /* Receiver Full Interrupt Enable */ + byte OVRIE :1; /* Overrun Interrupt Enable */ + byte TSTATE0 :1; /* Transmitter Status Change Enable 0 */ + byte TSTATE1 :1; /* Transmitter Status Change Enable 1 */ + byte RSTATE0 :1; /* Receiver Status Change Enable 0 */ + byte RSTATE1 :1; /* Receiver Status Change Enable 1 */ + byte CSCIE :1; /* CAN Status Change Interrupt Enable */ + byte WUPIE :1; /* Wake-up Interrupt Enable */ + } Bits; + struct { + byte :1; + byte :1; + byte grpTSTATE :2; + byte grpRSTATE :2; + byte :1; + byte :1; + } MergedBits; +} CAN0RIERSTR; +extern volatile CAN0RIERSTR _CAN0RIER @(REG_BASE + 0x00000145); +#define CAN0RIER _CAN0RIER.Byte +#define CAN0RIER_RXFIE _CAN0RIER.Bits.RXFIE +#define CAN0RIER_OVRIE _CAN0RIER.Bits.OVRIE +#define CAN0RIER_TSTATE0 _CAN0RIER.Bits.TSTATE0 +#define CAN0RIER_TSTATE1 _CAN0RIER.Bits.TSTATE1 +#define CAN0RIER_RSTATE0 _CAN0RIER.Bits.RSTATE0 +#define CAN0RIER_RSTATE1 _CAN0RIER.Bits.RSTATE1 +#define CAN0RIER_CSCIE _CAN0RIER.Bits.CSCIE +#define CAN0RIER_WUPIE _CAN0RIER.Bits.WUPIE +#define CAN0RIER_TSTATE _CAN0RIER.MergedBits.grpTSTATE +#define CAN0RIER_RSTATE _CAN0RIER.MergedBits.grpRSTATE + + +/*** CAN0TFLG - MSCAN 0 Transmitter Flag Register; 0x00000146 ***/ +typedef union { + byte Byte; + struct { + byte TXE0 :1; /* Transmitter Buffer Empty 0 */ + byte TXE1 :1; /* Transmitter Buffer Empty 1 */ + byte TXE2 :1; /* Transmitter Buffer Empty 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpTXE :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN0TFLGSTR; +extern volatile CAN0TFLGSTR _CAN0TFLG @(REG_BASE + 0x00000146); +#define CAN0TFLG _CAN0TFLG.Byte +#define CAN0TFLG_TXE0 _CAN0TFLG.Bits.TXE0 +#define CAN0TFLG_TXE1 _CAN0TFLG.Bits.TXE1 +#define CAN0TFLG_TXE2 _CAN0TFLG.Bits.TXE2 +#define CAN0TFLG_TXE _CAN0TFLG.MergedBits.grpTXE + + +/*** CAN0TIER - MSCAN 0 Transmitter Interrupt Enable Register; 0x00000147 ***/ +typedef union { + byte Byte; + struct { + byte TXEIE0 :1; /* Transmitter Empty Interrupt Enable 0 */ + byte TXEIE1 :1; /* Transmitter Empty Interrupt Enable 1 */ + byte TXEIE2 :1; /* Transmitter Empty Interrupt Enable 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpTXEIE :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN0TIERSTR; +extern volatile CAN0TIERSTR _CAN0TIER @(REG_BASE + 0x00000147); +#define CAN0TIER _CAN0TIER.Byte +#define CAN0TIER_TXEIE0 _CAN0TIER.Bits.TXEIE0 +#define CAN0TIER_TXEIE1 _CAN0TIER.Bits.TXEIE1 +#define CAN0TIER_TXEIE2 _CAN0TIER.Bits.TXEIE2 +#define CAN0TIER_TXEIE _CAN0TIER.MergedBits.grpTXEIE + + +/*** CAN0TARQ - MSCAN 0 Transmitter Message Abort Request; 0x00000148 ***/ +typedef union { + byte Byte; + struct { + byte ABTRQ0 :1; /* Abort Request 0 */ + byte ABTRQ1 :1; /* Abort Request 1 */ + byte ABTRQ2 :1; /* Abort Request 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpABTRQ :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN0TARQSTR; +extern volatile CAN0TARQSTR _CAN0TARQ @(REG_BASE + 0x00000148); +#define CAN0TARQ _CAN0TARQ.Byte +#define CAN0TARQ_ABTRQ0 _CAN0TARQ.Bits.ABTRQ0 +#define CAN0TARQ_ABTRQ1 _CAN0TARQ.Bits.ABTRQ1 +#define CAN0TARQ_ABTRQ2 _CAN0TARQ.Bits.ABTRQ2 +#define CAN0TARQ_ABTRQ _CAN0TARQ.MergedBits.grpABTRQ + + +/*** CAN0TAAK - MSCAN 0 Transmitter Message Abort Control; 0x00000149 ***/ +typedef union { + byte Byte; + struct { + byte ABTAK0 :1; /* Abort Acknowledge 0 */ + byte ABTAK1 :1; /* Abort Acknowledge 1 */ + byte ABTAK2 :1; /* Abort Acknowledge 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpABTAK :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN0TAAKSTR; +extern volatile CAN0TAAKSTR _CAN0TAAK @(REG_BASE + 0x00000149); +#define CAN0TAAK _CAN0TAAK.Byte +#define CAN0TAAK_ABTAK0 _CAN0TAAK.Bits.ABTAK0 +#define CAN0TAAK_ABTAK1 _CAN0TAAK.Bits.ABTAK1 +#define CAN0TAAK_ABTAK2 _CAN0TAAK.Bits.ABTAK2 +#define CAN0TAAK_ABTAK _CAN0TAAK.MergedBits.grpABTAK + + +/*** CAN0TBSEL - MSCAN 0 Transmit Buffer Selection; 0x0000014A ***/ +typedef union { + byte Byte; + struct { + byte TX0 :1; /* Transmit Buffer Select 0 */ + byte TX1 :1; /* Transmit Buffer Select 1 */ + byte TX2 :1; /* Transmit Buffer Select 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpTX :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN0TBSELSTR; +extern volatile CAN0TBSELSTR _CAN0TBSEL @(REG_BASE + 0x0000014A); +#define CAN0TBSEL _CAN0TBSEL.Byte +#define CAN0TBSEL_TX0 _CAN0TBSEL.Bits.TX0 +#define CAN0TBSEL_TX1 _CAN0TBSEL.Bits.TX1 +#define CAN0TBSEL_TX2 _CAN0TBSEL.Bits.TX2 +#define CAN0TBSEL_TX _CAN0TBSEL.MergedBits.grpTX + + +/*** CAN0IDAC - MSCAN 0 Identifier Acceptance Control Register; 0x0000014B ***/ +typedef union { + byte Byte; + struct { + byte IDHIT0 :1; /* Identifier Acceptance Hit Indicator 0 */ + byte IDHIT1 :1; /* Identifier Acceptance Hit Indicator 1 */ + byte IDHIT2 :1; /* Identifier Acceptance Hit Indicator 2 */ + byte :1; + byte IDAM0 :1; /* Identifier Acceptance Mode 0 */ + byte IDAM1 :1; /* Identifier Acceptance Mode 1 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpIDHIT :3; + byte :1; + byte grpIDAM :2; + byte :1; + byte :1; + } MergedBits; +} CAN0IDACSTR; +extern volatile CAN0IDACSTR _CAN0IDAC @(REG_BASE + 0x0000014B); +#define CAN0IDAC _CAN0IDAC.Byte +#define CAN0IDAC_IDHIT0 _CAN0IDAC.Bits.IDHIT0 +#define CAN0IDAC_IDHIT1 _CAN0IDAC.Bits.IDHIT1 +#define CAN0IDAC_IDHIT2 _CAN0IDAC.Bits.IDHIT2 +#define CAN0IDAC_IDAM0 _CAN0IDAC.Bits.IDAM0 +#define CAN0IDAC_IDAM1 _CAN0IDAC.Bits.IDAM1 +#define CAN0IDAC_IDHIT _CAN0IDAC.MergedBits.grpIDHIT +#define CAN0IDAC_IDAM _CAN0IDAC.MergedBits.grpIDAM + + +/*** CAN0RXERR - MSCAN 0 Receive Error Counter Register; 0x0000014E ***/ +typedef union { + byte Byte; + struct { + byte RXERR0 :1; /* Bit 0 */ + byte RXERR1 :1; /* Bit 1 */ + byte RXERR2 :1; /* Bit 2 */ + byte RXERR3 :1; /* Bit 3 */ + byte RXERR4 :1; /* Bit 4 */ + byte RXERR5 :1; /* Bit 5 */ + byte RXERR6 :1; /* Bit 6 */ + byte RXERR7 :1; /* Bit 7 */ + } Bits; + struct { + byte grpRXERR :8; + } MergedBits; +} CAN0RXERRSTR; +extern volatile CAN0RXERRSTR _CAN0RXERR @(REG_BASE + 0x0000014E); +#define CAN0RXERR _CAN0RXERR.Byte +#define CAN0RXERR_RXERR0 _CAN0RXERR.Bits.RXERR0 +#define CAN0RXERR_RXERR1 _CAN0RXERR.Bits.RXERR1 +#define CAN0RXERR_RXERR2 _CAN0RXERR.Bits.RXERR2 +#define CAN0RXERR_RXERR3 _CAN0RXERR.Bits.RXERR3 +#define CAN0RXERR_RXERR4 _CAN0RXERR.Bits.RXERR4 +#define CAN0RXERR_RXERR5 _CAN0RXERR.Bits.RXERR5 +#define CAN0RXERR_RXERR6 _CAN0RXERR.Bits.RXERR6 +#define CAN0RXERR_RXERR7 _CAN0RXERR.Bits.RXERR7 +#define CAN0RXERR_RXERR _CAN0RXERR.MergedBits.grpRXERR + + +/*** CAN0TXERR - MSCAN 0 Transmit Error Counter Register; 0x0000014F ***/ +typedef union { + byte Byte; + struct { + byte TXERR0 :1; /* Bit 0 */ + byte TXERR1 :1; /* Bit 1 */ + byte TXERR2 :1; /* Bit 2 */ + byte TXERR3 :1; /* Bit 3 */ + byte TXERR4 :1; /* Bit 4 */ + byte TXERR5 :1; /* Bit 5 */ + byte TXERR6 :1; /* Bit 6 */ + byte TXERR7 :1; /* Bit 7 */ + } Bits; + struct { + byte grpTXERR :8; + } MergedBits; +} CAN0TXERRSTR; +extern volatile CAN0TXERRSTR _CAN0TXERR @(REG_BASE + 0x0000014F); +#define CAN0TXERR _CAN0TXERR.Byte +#define CAN0TXERR_TXERR0 _CAN0TXERR.Bits.TXERR0 +#define CAN0TXERR_TXERR1 _CAN0TXERR.Bits.TXERR1 +#define CAN0TXERR_TXERR2 _CAN0TXERR.Bits.TXERR2 +#define CAN0TXERR_TXERR3 _CAN0TXERR.Bits.TXERR3 +#define CAN0TXERR_TXERR4 _CAN0TXERR.Bits.TXERR4 +#define CAN0TXERR_TXERR5 _CAN0TXERR.Bits.TXERR5 +#define CAN0TXERR_TXERR6 _CAN0TXERR.Bits.TXERR6 +#define CAN0TXERR_TXERR7 _CAN0TXERR.Bits.TXERR7 +#define CAN0TXERR_TXERR _CAN0TXERR.MergedBits.grpTXERR + + +/*** CAN0IDAR0 - MSCAN 0 Identifier Acceptance Register 0; 0x00000150 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN0IDAR0STR; +extern volatile CAN0IDAR0STR _CAN0IDAR0 @(REG_BASE + 0x00000150); +#define CAN0IDAR0 _CAN0IDAR0.Byte +#define CAN0IDAR0_AC0 _CAN0IDAR0.Bits.AC0 +#define CAN0IDAR0_AC1 _CAN0IDAR0.Bits.AC1 +#define CAN0IDAR0_AC2 _CAN0IDAR0.Bits.AC2 +#define CAN0IDAR0_AC3 _CAN0IDAR0.Bits.AC3 +#define CAN0IDAR0_AC4 _CAN0IDAR0.Bits.AC4 +#define CAN0IDAR0_AC5 _CAN0IDAR0.Bits.AC5 +#define CAN0IDAR0_AC6 _CAN0IDAR0.Bits.AC6 +#define CAN0IDAR0_AC7 _CAN0IDAR0.Bits.AC7 +#define CAN0IDAR0_AC _CAN0IDAR0.MergedBits.grpAC + + +/*** CAN0IDAR1 - MSCAN 0 Identifier Acceptance Register 1; 0x00000151 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN0IDAR1STR; +extern volatile CAN0IDAR1STR _CAN0IDAR1 @(REG_BASE + 0x00000151); +#define CAN0IDAR1 _CAN0IDAR1.Byte +#define CAN0IDAR1_AC0 _CAN0IDAR1.Bits.AC0 +#define CAN0IDAR1_AC1 _CAN0IDAR1.Bits.AC1 +#define CAN0IDAR1_AC2 _CAN0IDAR1.Bits.AC2 +#define CAN0IDAR1_AC3 _CAN0IDAR1.Bits.AC3 +#define CAN0IDAR1_AC4 _CAN0IDAR1.Bits.AC4 +#define CAN0IDAR1_AC5 _CAN0IDAR1.Bits.AC5 +#define CAN0IDAR1_AC6 _CAN0IDAR1.Bits.AC6 +#define CAN0IDAR1_AC7 _CAN0IDAR1.Bits.AC7 +#define CAN0IDAR1_AC _CAN0IDAR1.MergedBits.grpAC + + +/*** CAN0IDAR2 - MSCAN 0 Identifier Acceptance Register 2; 0x00000152 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN0IDAR2STR; +extern volatile CAN0IDAR2STR _CAN0IDAR2 @(REG_BASE + 0x00000152); +#define CAN0IDAR2 _CAN0IDAR2.Byte +#define CAN0IDAR2_AC0 _CAN0IDAR2.Bits.AC0 +#define CAN0IDAR2_AC1 _CAN0IDAR2.Bits.AC1 +#define CAN0IDAR2_AC2 _CAN0IDAR2.Bits.AC2 +#define CAN0IDAR2_AC3 _CAN0IDAR2.Bits.AC3 +#define CAN0IDAR2_AC4 _CAN0IDAR2.Bits.AC4 +#define CAN0IDAR2_AC5 _CAN0IDAR2.Bits.AC5 +#define CAN0IDAR2_AC6 _CAN0IDAR2.Bits.AC6 +#define CAN0IDAR2_AC7 _CAN0IDAR2.Bits.AC7 +#define CAN0IDAR2_AC _CAN0IDAR2.MergedBits.grpAC + + +/*** CAN0IDAR3 - MSCAN 0 Identifier Acceptance Register 3; 0x00000153 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN0IDAR3STR; +extern volatile CAN0IDAR3STR _CAN0IDAR3 @(REG_BASE + 0x00000153); +#define CAN0IDAR3 _CAN0IDAR3.Byte +#define CAN0IDAR3_AC0 _CAN0IDAR3.Bits.AC0 +#define CAN0IDAR3_AC1 _CAN0IDAR3.Bits.AC1 +#define CAN0IDAR3_AC2 _CAN0IDAR3.Bits.AC2 +#define CAN0IDAR3_AC3 _CAN0IDAR3.Bits.AC3 +#define CAN0IDAR3_AC4 _CAN0IDAR3.Bits.AC4 +#define CAN0IDAR3_AC5 _CAN0IDAR3.Bits.AC5 +#define CAN0IDAR3_AC6 _CAN0IDAR3.Bits.AC6 +#define CAN0IDAR3_AC7 _CAN0IDAR3.Bits.AC7 +#define CAN0IDAR3_AC _CAN0IDAR3.MergedBits.grpAC + + +/*** CAN0IDMR0 - MSCAN 0 Identifier Mask Register 0; 0x00000154 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN0IDMR0STR; +extern volatile CAN0IDMR0STR _CAN0IDMR0 @(REG_BASE + 0x00000154); +#define CAN0IDMR0 _CAN0IDMR0.Byte +#define CAN0IDMR0_AM0 _CAN0IDMR0.Bits.AM0 +#define CAN0IDMR0_AM1 _CAN0IDMR0.Bits.AM1 +#define CAN0IDMR0_AM2 _CAN0IDMR0.Bits.AM2 +#define CAN0IDMR0_AM3 _CAN0IDMR0.Bits.AM3 +#define CAN0IDMR0_AM4 _CAN0IDMR0.Bits.AM4 +#define CAN0IDMR0_AM5 _CAN0IDMR0.Bits.AM5 +#define CAN0IDMR0_AM6 _CAN0IDMR0.Bits.AM6 +#define CAN0IDMR0_AM7 _CAN0IDMR0.Bits.AM7 +#define CAN0IDMR0_AM _CAN0IDMR0.MergedBits.grpAM + + +/*** CAN0IDMR1 - MSCAN 0 Identifier Mask Register 1; 0x00000155 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN0IDMR1STR; +extern volatile CAN0IDMR1STR _CAN0IDMR1 @(REG_BASE + 0x00000155); +#define CAN0IDMR1 _CAN0IDMR1.Byte +#define CAN0IDMR1_AM0 _CAN0IDMR1.Bits.AM0 +#define CAN0IDMR1_AM1 _CAN0IDMR1.Bits.AM1 +#define CAN0IDMR1_AM2 _CAN0IDMR1.Bits.AM2 +#define CAN0IDMR1_AM3 _CAN0IDMR1.Bits.AM3 +#define CAN0IDMR1_AM4 _CAN0IDMR1.Bits.AM4 +#define CAN0IDMR1_AM5 _CAN0IDMR1.Bits.AM5 +#define CAN0IDMR1_AM6 _CAN0IDMR1.Bits.AM6 +#define CAN0IDMR1_AM7 _CAN0IDMR1.Bits.AM7 +#define CAN0IDMR1_AM _CAN0IDMR1.MergedBits.grpAM + + +/*** CAN0IDMR2 - MSCAN 0 Identifier Mask Register 2; 0x00000156 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN0IDMR2STR; +extern volatile CAN0IDMR2STR _CAN0IDMR2 @(REG_BASE + 0x00000156); +#define CAN0IDMR2 _CAN0IDMR2.Byte +#define CAN0IDMR2_AM0 _CAN0IDMR2.Bits.AM0 +#define CAN0IDMR2_AM1 _CAN0IDMR2.Bits.AM1 +#define CAN0IDMR2_AM2 _CAN0IDMR2.Bits.AM2 +#define CAN0IDMR2_AM3 _CAN0IDMR2.Bits.AM3 +#define CAN0IDMR2_AM4 _CAN0IDMR2.Bits.AM4 +#define CAN0IDMR2_AM5 _CAN0IDMR2.Bits.AM5 +#define CAN0IDMR2_AM6 _CAN0IDMR2.Bits.AM6 +#define CAN0IDMR2_AM7 _CAN0IDMR2.Bits.AM7 +#define CAN0IDMR2_AM _CAN0IDMR2.MergedBits.grpAM + + +/*** CAN0IDMR3 - MSCAN 0 Identifier Mask Register 3; 0x00000157 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN0IDMR3STR; +extern volatile CAN0IDMR3STR _CAN0IDMR3 @(REG_BASE + 0x00000157); +#define CAN0IDMR3 _CAN0IDMR3.Byte +#define CAN0IDMR3_AM0 _CAN0IDMR3.Bits.AM0 +#define CAN0IDMR3_AM1 _CAN0IDMR3.Bits.AM1 +#define CAN0IDMR3_AM2 _CAN0IDMR3.Bits.AM2 +#define CAN0IDMR3_AM3 _CAN0IDMR3.Bits.AM3 +#define CAN0IDMR3_AM4 _CAN0IDMR3.Bits.AM4 +#define CAN0IDMR3_AM5 _CAN0IDMR3.Bits.AM5 +#define CAN0IDMR3_AM6 _CAN0IDMR3.Bits.AM6 +#define CAN0IDMR3_AM7 _CAN0IDMR3.Bits.AM7 +#define CAN0IDMR3_AM _CAN0IDMR3.MergedBits.grpAM + + +/*** CAN0IDAR4 - MSCAN 0 Identifier Acceptance Register 4; 0x00000158 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN0IDAR4STR; +extern volatile CAN0IDAR4STR _CAN0IDAR4 @(REG_BASE + 0x00000158); +#define CAN0IDAR4 _CAN0IDAR4.Byte +#define CAN0IDAR4_AC0 _CAN0IDAR4.Bits.AC0 +#define CAN0IDAR4_AC1 _CAN0IDAR4.Bits.AC1 +#define CAN0IDAR4_AC2 _CAN0IDAR4.Bits.AC2 +#define CAN0IDAR4_AC3 _CAN0IDAR4.Bits.AC3 +#define CAN0IDAR4_AC4 _CAN0IDAR4.Bits.AC4 +#define CAN0IDAR4_AC5 _CAN0IDAR4.Bits.AC5 +#define CAN0IDAR4_AC6 _CAN0IDAR4.Bits.AC6 +#define CAN0IDAR4_AC7 _CAN0IDAR4.Bits.AC7 +#define CAN0IDAR4_AC _CAN0IDAR4.MergedBits.grpAC + + +/*** CAN0IDAR5 - MSCAN 0 Identifier Acceptance Register 5; 0x00000159 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN0IDAR5STR; +extern volatile CAN0IDAR5STR _CAN0IDAR5 @(REG_BASE + 0x00000159); +#define CAN0IDAR5 _CAN0IDAR5.Byte +#define CAN0IDAR5_AC0 _CAN0IDAR5.Bits.AC0 +#define CAN0IDAR5_AC1 _CAN0IDAR5.Bits.AC1 +#define CAN0IDAR5_AC2 _CAN0IDAR5.Bits.AC2 +#define CAN0IDAR5_AC3 _CAN0IDAR5.Bits.AC3 +#define CAN0IDAR5_AC4 _CAN0IDAR5.Bits.AC4 +#define CAN0IDAR5_AC5 _CAN0IDAR5.Bits.AC5 +#define CAN0IDAR5_AC6 _CAN0IDAR5.Bits.AC6 +#define CAN0IDAR5_AC7 _CAN0IDAR5.Bits.AC7 +#define CAN0IDAR5_AC _CAN0IDAR5.MergedBits.grpAC + + +/*** CAN0IDAR6 - MSCAN 0 Identifier Acceptance Register 6; 0x0000015A ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN0IDAR6STR; +extern volatile CAN0IDAR6STR _CAN0IDAR6 @(REG_BASE + 0x0000015A); +#define CAN0IDAR6 _CAN0IDAR6.Byte +#define CAN0IDAR6_AC0 _CAN0IDAR6.Bits.AC0 +#define CAN0IDAR6_AC1 _CAN0IDAR6.Bits.AC1 +#define CAN0IDAR6_AC2 _CAN0IDAR6.Bits.AC2 +#define CAN0IDAR6_AC3 _CAN0IDAR6.Bits.AC3 +#define CAN0IDAR6_AC4 _CAN0IDAR6.Bits.AC4 +#define CAN0IDAR6_AC5 _CAN0IDAR6.Bits.AC5 +#define CAN0IDAR6_AC6 _CAN0IDAR6.Bits.AC6 +#define CAN0IDAR6_AC7 _CAN0IDAR6.Bits.AC7 +#define CAN0IDAR6_AC _CAN0IDAR6.MergedBits.grpAC + + +/*** CAN0IDAR7 - MSCAN 0 Identifier Acceptance Register 7; 0x0000015B ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN0IDAR7STR; +extern volatile CAN0IDAR7STR _CAN0IDAR7 @(REG_BASE + 0x0000015B); +#define CAN0IDAR7 _CAN0IDAR7.Byte +#define CAN0IDAR7_AC0 _CAN0IDAR7.Bits.AC0 +#define CAN0IDAR7_AC1 _CAN0IDAR7.Bits.AC1 +#define CAN0IDAR7_AC2 _CAN0IDAR7.Bits.AC2 +#define CAN0IDAR7_AC3 _CAN0IDAR7.Bits.AC3 +#define CAN0IDAR7_AC4 _CAN0IDAR7.Bits.AC4 +#define CAN0IDAR7_AC5 _CAN0IDAR7.Bits.AC5 +#define CAN0IDAR7_AC6 _CAN0IDAR7.Bits.AC6 +#define CAN0IDAR7_AC7 _CAN0IDAR7.Bits.AC7 +#define CAN0IDAR7_AC _CAN0IDAR7.MergedBits.grpAC + + +/*** CAN0IDMR4 - MSCAN 0 Identifier Mask Register 4; 0x0000015C ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN0IDMR4STR; +extern volatile CAN0IDMR4STR _CAN0IDMR4 @(REG_BASE + 0x0000015C); +#define CAN0IDMR4 _CAN0IDMR4.Byte +#define CAN0IDMR4_AM0 _CAN0IDMR4.Bits.AM0 +#define CAN0IDMR4_AM1 _CAN0IDMR4.Bits.AM1 +#define CAN0IDMR4_AM2 _CAN0IDMR4.Bits.AM2 +#define CAN0IDMR4_AM3 _CAN0IDMR4.Bits.AM3 +#define CAN0IDMR4_AM4 _CAN0IDMR4.Bits.AM4 +#define CAN0IDMR4_AM5 _CAN0IDMR4.Bits.AM5 +#define CAN0IDMR4_AM6 _CAN0IDMR4.Bits.AM6 +#define CAN0IDMR4_AM7 _CAN0IDMR4.Bits.AM7 +#define CAN0IDMR4_AM _CAN0IDMR4.MergedBits.grpAM + + +/*** CAN0IDMR5 - MSCAN 0 Identifier Mask Register 5; 0x0000015D ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN0IDMR5STR; +extern volatile CAN0IDMR5STR _CAN0IDMR5 @(REG_BASE + 0x0000015D); +#define CAN0IDMR5 _CAN0IDMR5.Byte +#define CAN0IDMR5_AM0 _CAN0IDMR5.Bits.AM0 +#define CAN0IDMR5_AM1 _CAN0IDMR5.Bits.AM1 +#define CAN0IDMR5_AM2 _CAN0IDMR5.Bits.AM2 +#define CAN0IDMR5_AM3 _CAN0IDMR5.Bits.AM3 +#define CAN0IDMR5_AM4 _CAN0IDMR5.Bits.AM4 +#define CAN0IDMR5_AM5 _CAN0IDMR5.Bits.AM5 +#define CAN0IDMR5_AM6 _CAN0IDMR5.Bits.AM6 +#define CAN0IDMR5_AM7 _CAN0IDMR5.Bits.AM7 +#define CAN0IDMR5_AM _CAN0IDMR5.MergedBits.grpAM + + +/*** CAN0IDMR6 - MSCAN 0 Identifier Mask Register 6; 0x0000015E ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN0IDMR6STR; +extern volatile CAN0IDMR6STR _CAN0IDMR6 @(REG_BASE + 0x0000015E); +#define CAN0IDMR6 _CAN0IDMR6.Byte +#define CAN0IDMR6_AM0 _CAN0IDMR6.Bits.AM0 +#define CAN0IDMR6_AM1 _CAN0IDMR6.Bits.AM1 +#define CAN0IDMR6_AM2 _CAN0IDMR6.Bits.AM2 +#define CAN0IDMR6_AM3 _CAN0IDMR6.Bits.AM3 +#define CAN0IDMR6_AM4 _CAN0IDMR6.Bits.AM4 +#define CAN0IDMR6_AM5 _CAN0IDMR6.Bits.AM5 +#define CAN0IDMR6_AM6 _CAN0IDMR6.Bits.AM6 +#define CAN0IDMR6_AM7 _CAN0IDMR6.Bits.AM7 +#define CAN0IDMR6_AM _CAN0IDMR6.MergedBits.grpAM + + +/*** CAN0IDMR7 - MSCAN 0 Identifier Mask Register 7; 0x0000015F ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN0IDMR7STR; +extern volatile CAN0IDMR7STR _CAN0IDMR7 @(REG_BASE + 0x0000015F); +#define CAN0IDMR7 _CAN0IDMR7.Byte +#define CAN0IDMR7_AM0 _CAN0IDMR7.Bits.AM0 +#define CAN0IDMR7_AM1 _CAN0IDMR7.Bits.AM1 +#define CAN0IDMR7_AM2 _CAN0IDMR7.Bits.AM2 +#define CAN0IDMR7_AM3 _CAN0IDMR7.Bits.AM3 +#define CAN0IDMR7_AM4 _CAN0IDMR7.Bits.AM4 +#define CAN0IDMR7_AM5 _CAN0IDMR7.Bits.AM5 +#define CAN0IDMR7_AM6 _CAN0IDMR7.Bits.AM6 +#define CAN0IDMR7_AM7 _CAN0IDMR7.Bits.AM7 +#define CAN0IDMR7_AM _CAN0IDMR7.MergedBits.grpAM + + +/*** CAN0RXIDR0 - MSCAN 0 Receive Identifier Register 0; 0x00000160 ***/ +typedef union { + byte Byte; + struct { + byte ID21 :1; /* Extended format identifier Bit 21 */ + byte ID22 :1; /* Extended format identifier Bit 22 */ + byte ID23 :1; /* Extended format identifier Bit 23 */ + byte ID24 :1; /* Extended format identifier Bit 24 */ + byte ID25 :1; /* Extended format identifier Bit 25 */ + byte ID26 :1; /* Extended format identifier Bit 26 */ + byte ID27 :1; /* Extended format identifier Bit 27 */ + byte ID28 :1; /* Extended format identifier Bit 28 */ + } Bits; + struct { + byte grpID_21 :8; + } MergedBits; +} CAN0RXIDR0STR; +extern volatile CAN0RXIDR0STR _CAN0RXIDR0 @(REG_BASE + 0x00000160); +#define CAN0RXIDR0 _CAN0RXIDR0.Byte +#define CAN0RXIDR0_ID21 _CAN0RXIDR0.Bits.ID21 +#define CAN0RXIDR0_ID22 _CAN0RXIDR0.Bits.ID22 +#define CAN0RXIDR0_ID23 _CAN0RXIDR0.Bits.ID23 +#define CAN0RXIDR0_ID24 _CAN0RXIDR0.Bits.ID24 +#define CAN0RXIDR0_ID25 _CAN0RXIDR0.Bits.ID25 +#define CAN0RXIDR0_ID26 _CAN0RXIDR0.Bits.ID26 +#define CAN0RXIDR0_ID27 _CAN0RXIDR0.Bits.ID27 +#define CAN0RXIDR0_ID28 _CAN0RXIDR0.Bits.ID28 +#define CAN0RXIDR0_ID_21 _CAN0RXIDR0.MergedBits.grpID_21 +#define CAN0RXIDR0_ID CAN0RXIDR0_ID_21 + + +/*** CAN0RXIDR1 - MSCAN 0 Receive Identifier Register 1; 0x00000161 ***/ +typedef union { + byte Byte; + struct { + byte ID15 :1; /* Extended format identifier Bit 15 */ + byte ID16 :1; /* Extended format identifier Bit 16 */ + byte ID17 :1; /* Extended format identifier Bit 17 */ + byte IDE :1; /* ID Extended */ + byte SRR :1; /* Substitute Remote Request */ + byte ID18 :1; /* Extended format identifier Bit 18 */ + byte ID19 :1; /* Extended format identifier Bit 19 */ + byte ID20 :1; /* Extended format identifier Bit 20 */ + } Bits; + struct { + byte grpID_15 :3; + byte :1; + byte :1; + byte grpID_18 :3; + } MergedBits; +} CAN0RXIDR1STR; +extern volatile CAN0RXIDR1STR _CAN0RXIDR1 @(REG_BASE + 0x00000161); +#define CAN0RXIDR1 _CAN0RXIDR1.Byte +#define CAN0RXIDR1_ID15 _CAN0RXIDR1.Bits.ID15 +#define CAN0RXIDR1_ID16 _CAN0RXIDR1.Bits.ID16 +#define CAN0RXIDR1_ID17 _CAN0RXIDR1.Bits.ID17 +#define CAN0RXIDR1_IDE _CAN0RXIDR1.Bits.IDE +#define CAN0RXIDR1_SRR _CAN0RXIDR1.Bits.SRR +#define CAN0RXIDR1_ID18 _CAN0RXIDR1.Bits.ID18 +#define CAN0RXIDR1_ID19 _CAN0RXIDR1.Bits.ID19 +#define CAN0RXIDR1_ID20 _CAN0RXIDR1.Bits.ID20 +#define CAN0RXIDR1_ID_15 _CAN0RXIDR1.MergedBits.grpID_15 +#define CAN0RXIDR1_ID_18 _CAN0RXIDR1.MergedBits.grpID_18 +#define CAN0RXIDR1_ID CAN0RXIDR1_ID_15 + + +/*** CAN0RXIDR2 - MSCAN 0 Receive Identifier Register 2; 0x00000162 ***/ +typedef union { + byte Byte; + struct { + byte ID7 :1; /* Extended format identifier Bit 7 */ + byte ID8 :1; /* Extended format identifier Bit 8 */ + byte ID9 :1; /* Extended format identifier Bit 9 */ + byte ID10 :1; /* Extended format identifier Bit 10 */ + byte ID11 :1; /* Extended format identifier Bit 11 */ + byte ID12 :1; /* Extended format identifier Bit 12 */ + byte ID13 :1; /* Extended format identifier Bit 13 */ + byte ID14 :1; /* Extended format identifier Bit 14 */ + } Bits; + struct { + byte grpID_7 :8; + } MergedBits; +} CAN0RXIDR2STR; +extern volatile CAN0RXIDR2STR _CAN0RXIDR2 @(REG_BASE + 0x00000162); +#define CAN0RXIDR2 _CAN0RXIDR2.Byte +#define CAN0RXIDR2_ID7 _CAN0RXIDR2.Bits.ID7 +#define CAN0RXIDR2_ID8 _CAN0RXIDR2.Bits.ID8 +#define CAN0RXIDR2_ID9 _CAN0RXIDR2.Bits.ID9 +#define CAN0RXIDR2_ID10 _CAN0RXIDR2.Bits.ID10 +#define CAN0RXIDR2_ID11 _CAN0RXIDR2.Bits.ID11 +#define CAN0RXIDR2_ID12 _CAN0RXIDR2.Bits.ID12 +#define CAN0RXIDR2_ID13 _CAN0RXIDR2.Bits.ID13 +#define CAN0RXIDR2_ID14 _CAN0RXIDR2.Bits.ID14 +#define CAN0RXIDR2_ID_7 _CAN0RXIDR2.MergedBits.grpID_7 +#define CAN0RXIDR2_ID CAN0RXIDR2_ID_7 + + +/*** CAN0RXIDR3 - MSCAN 0 Receive Identifier Register 3; 0x00000163 ***/ +typedef union { + byte Byte; + struct { + byte RTR :1; /* Remote Transmission Request */ + byte ID0 :1; /* Extended format identifier Bit 0 */ + byte ID1 :1; /* Extended format identifier Bit 1 */ + byte ID2 :1; /* Extended format identifier Bit 2 */ + byte ID3 :1; /* Extended format identifier Bit 3 */ + byte ID4 :1; /* Extended format identifier Bit 4 */ + byte ID5 :1; /* Extended format identifier Bit 5 */ + byte ID6 :1; /* Extended format identifier Bit 6 */ + } Bits; + struct { + byte :1; + byte grpID :7; + } MergedBits; +} CAN0RXIDR3STR; +extern volatile CAN0RXIDR3STR _CAN0RXIDR3 @(REG_BASE + 0x00000163); +#define CAN0RXIDR3 _CAN0RXIDR3.Byte +#define CAN0RXIDR3_RTR _CAN0RXIDR3.Bits.RTR +#define CAN0RXIDR3_ID0 _CAN0RXIDR3.Bits.ID0 +#define CAN0RXIDR3_ID1 _CAN0RXIDR3.Bits.ID1 +#define CAN0RXIDR3_ID2 _CAN0RXIDR3.Bits.ID2 +#define CAN0RXIDR3_ID3 _CAN0RXIDR3.Bits.ID3 +#define CAN0RXIDR3_ID4 _CAN0RXIDR3.Bits.ID4 +#define CAN0RXIDR3_ID5 _CAN0RXIDR3.Bits.ID5 +#define CAN0RXIDR3_ID6 _CAN0RXIDR3.Bits.ID6 +#define CAN0RXIDR3_ID _CAN0RXIDR3.MergedBits.grpID + + +/*** CAN0RXDSR0 - MSCAN 0 Receive Data Segment Register 0; 0x00000164 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN0RXDSR0STR; +extern volatile CAN0RXDSR0STR _CAN0RXDSR0 @(REG_BASE + 0x00000164); +#define CAN0RXDSR0 _CAN0RXDSR0.Byte +#define CAN0RXDSR0_DB0 _CAN0RXDSR0.Bits.DB0 +#define CAN0RXDSR0_DB1 _CAN0RXDSR0.Bits.DB1 +#define CAN0RXDSR0_DB2 _CAN0RXDSR0.Bits.DB2 +#define CAN0RXDSR0_DB3 _CAN0RXDSR0.Bits.DB3 +#define CAN0RXDSR0_DB4 _CAN0RXDSR0.Bits.DB4 +#define CAN0RXDSR0_DB5 _CAN0RXDSR0.Bits.DB5 +#define CAN0RXDSR0_DB6 _CAN0RXDSR0.Bits.DB6 +#define CAN0RXDSR0_DB7 _CAN0RXDSR0.Bits.DB7 +#define CAN0RXDSR0_DB _CAN0RXDSR0.MergedBits.grpDB + + +/*** CAN0RXDSR1 - MSCAN 0 Receive Data Segment Register 1; 0x00000165 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN0RXDSR1STR; +extern volatile CAN0RXDSR1STR _CAN0RXDSR1 @(REG_BASE + 0x00000165); +#define CAN0RXDSR1 _CAN0RXDSR1.Byte +#define CAN0RXDSR1_DB0 _CAN0RXDSR1.Bits.DB0 +#define CAN0RXDSR1_DB1 _CAN0RXDSR1.Bits.DB1 +#define CAN0RXDSR1_DB2 _CAN0RXDSR1.Bits.DB2 +#define CAN0RXDSR1_DB3 _CAN0RXDSR1.Bits.DB3 +#define CAN0RXDSR1_DB4 _CAN0RXDSR1.Bits.DB4 +#define CAN0RXDSR1_DB5 _CAN0RXDSR1.Bits.DB5 +#define CAN0RXDSR1_DB6 _CAN0RXDSR1.Bits.DB6 +#define CAN0RXDSR1_DB7 _CAN0RXDSR1.Bits.DB7 +#define CAN0RXDSR1_DB _CAN0RXDSR1.MergedBits.grpDB + + +/*** CAN0RXDSR2 - MSCAN 0 Receive Data Segment Register 2; 0x00000166 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN0RXDSR2STR; +extern volatile CAN0RXDSR2STR _CAN0RXDSR2 @(REG_BASE + 0x00000166); +#define CAN0RXDSR2 _CAN0RXDSR2.Byte +#define CAN0RXDSR2_DB0 _CAN0RXDSR2.Bits.DB0 +#define CAN0RXDSR2_DB1 _CAN0RXDSR2.Bits.DB1 +#define CAN0RXDSR2_DB2 _CAN0RXDSR2.Bits.DB2 +#define CAN0RXDSR2_DB3 _CAN0RXDSR2.Bits.DB3 +#define CAN0RXDSR2_DB4 _CAN0RXDSR2.Bits.DB4 +#define CAN0RXDSR2_DB5 _CAN0RXDSR2.Bits.DB5 +#define CAN0RXDSR2_DB6 _CAN0RXDSR2.Bits.DB6 +#define CAN0RXDSR2_DB7 _CAN0RXDSR2.Bits.DB7 +#define CAN0RXDSR2_DB _CAN0RXDSR2.MergedBits.grpDB + + +/*** CAN0RXDSR3 - MSCAN 0 Receive Data Segment Register 3; 0x00000167 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN0RXDSR3STR; +extern volatile CAN0RXDSR3STR _CAN0RXDSR3 @(REG_BASE + 0x00000167); +#define CAN0RXDSR3 _CAN0RXDSR3.Byte +#define CAN0RXDSR3_DB0 _CAN0RXDSR3.Bits.DB0 +#define CAN0RXDSR3_DB1 _CAN0RXDSR3.Bits.DB1 +#define CAN0RXDSR3_DB2 _CAN0RXDSR3.Bits.DB2 +#define CAN0RXDSR3_DB3 _CAN0RXDSR3.Bits.DB3 +#define CAN0RXDSR3_DB4 _CAN0RXDSR3.Bits.DB4 +#define CAN0RXDSR3_DB5 _CAN0RXDSR3.Bits.DB5 +#define CAN0RXDSR3_DB6 _CAN0RXDSR3.Bits.DB6 +#define CAN0RXDSR3_DB7 _CAN0RXDSR3.Bits.DB7 +#define CAN0RXDSR3_DB _CAN0RXDSR3.MergedBits.grpDB + + +/*** CAN0RXDSR4 - MSCAN 0 Receive Data Segment Register 4; 0x00000168 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN0RXDSR4STR; +extern volatile CAN0RXDSR4STR _CAN0RXDSR4 @(REG_BASE + 0x00000168); +#define CAN0RXDSR4 _CAN0RXDSR4.Byte +#define CAN0RXDSR4_DB0 _CAN0RXDSR4.Bits.DB0 +#define CAN0RXDSR4_DB1 _CAN0RXDSR4.Bits.DB1 +#define CAN0RXDSR4_DB2 _CAN0RXDSR4.Bits.DB2 +#define CAN0RXDSR4_DB3 _CAN0RXDSR4.Bits.DB3 +#define CAN0RXDSR4_DB4 _CAN0RXDSR4.Bits.DB4 +#define CAN0RXDSR4_DB5 _CAN0RXDSR4.Bits.DB5 +#define CAN0RXDSR4_DB6 _CAN0RXDSR4.Bits.DB6 +#define CAN0RXDSR4_DB7 _CAN0RXDSR4.Bits.DB7 +#define CAN0RXDSR4_DB _CAN0RXDSR4.MergedBits.grpDB + + +/*** CAN0RXDSR5 - MSCAN 0 Receive Data Segment Register 5; 0x00000169 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN0RXDSR5STR; +extern volatile CAN0RXDSR5STR _CAN0RXDSR5 @(REG_BASE + 0x00000169); +#define CAN0RXDSR5 _CAN0RXDSR5.Byte +#define CAN0RXDSR5_DB0 _CAN0RXDSR5.Bits.DB0 +#define CAN0RXDSR5_DB1 _CAN0RXDSR5.Bits.DB1 +#define CAN0RXDSR5_DB2 _CAN0RXDSR5.Bits.DB2 +#define CAN0RXDSR5_DB3 _CAN0RXDSR5.Bits.DB3 +#define CAN0RXDSR5_DB4 _CAN0RXDSR5.Bits.DB4 +#define CAN0RXDSR5_DB5 _CAN0RXDSR5.Bits.DB5 +#define CAN0RXDSR5_DB6 _CAN0RXDSR5.Bits.DB6 +#define CAN0RXDSR5_DB7 _CAN0RXDSR5.Bits.DB7 +#define CAN0RXDSR5_DB _CAN0RXDSR5.MergedBits.grpDB + + +/*** CAN0RXDSR6 - MSCAN 0 Receive Data Segment Register 6; 0x0000016A ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN0RXDSR6STR; +extern volatile CAN0RXDSR6STR _CAN0RXDSR6 @(REG_BASE + 0x0000016A); +#define CAN0RXDSR6 _CAN0RXDSR6.Byte +#define CAN0RXDSR6_DB0 _CAN0RXDSR6.Bits.DB0 +#define CAN0RXDSR6_DB1 _CAN0RXDSR6.Bits.DB1 +#define CAN0RXDSR6_DB2 _CAN0RXDSR6.Bits.DB2 +#define CAN0RXDSR6_DB3 _CAN0RXDSR6.Bits.DB3 +#define CAN0RXDSR6_DB4 _CAN0RXDSR6.Bits.DB4 +#define CAN0RXDSR6_DB5 _CAN0RXDSR6.Bits.DB5 +#define CAN0RXDSR6_DB6 _CAN0RXDSR6.Bits.DB6 +#define CAN0RXDSR6_DB7 _CAN0RXDSR6.Bits.DB7 +#define CAN0RXDSR6_DB _CAN0RXDSR6.MergedBits.grpDB + + +/*** CAN0RXDSR7 - MSCAN 0 Receive Data Segment Register 7; 0x0000016B ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN0RXDSR7STR; +extern volatile CAN0RXDSR7STR _CAN0RXDSR7 @(REG_BASE + 0x0000016B); +#define CAN0RXDSR7 _CAN0RXDSR7.Byte +#define CAN0RXDSR7_DB0 _CAN0RXDSR7.Bits.DB0 +#define CAN0RXDSR7_DB1 _CAN0RXDSR7.Bits.DB1 +#define CAN0RXDSR7_DB2 _CAN0RXDSR7.Bits.DB2 +#define CAN0RXDSR7_DB3 _CAN0RXDSR7.Bits.DB3 +#define CAN0RXDSR7_DB4 _CAN0RXDSR7.Bits.DB4 +#define CAN0RXDSR7_DB5 _CAN0RXDSR7.Bits.DB5 +#define CAN0RXDSR7_DB6 _CAN0RXDSR7.Bits.DB6 +#define CAN0RXDSR7_DB7 _CAN0RXDSR7.Bits.DB7 +#define CAN0RXDSR7_DB _CAN0RXDSR7.MergedBits.grpDB + + +/*** CAN0RXDLR - MSCAN 0 Receive Data Length Register; 0x0000016C ***/ +typedef union { + byte Byte; + struct { + byte DLC0 :1; /* Data Length Code Bit 0 */ + byte DLC1 :1; /* Data Length Code Bit 1 */ + byte DLC2 :1; /* Data Length Code Bit 2 */ + byte DLC3 :1; /* Data Length Code Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpDLC :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN0RXDLRSTR; +extern volatile CAN0RXDLRSTR _CAN0RXDLR @(REG_BASE + 0x0000016C); +#define CAN0RXDLR _CAN0RXDLR.Byte +#define CAN0RXDLR_DLC0 _CAN0RXDLR.Bits.DLC0 +#define CAN0RXDLR_DLC1 _CAN0RXDLR.Bits.DLC1 +#define CAN0RXDLR_DLC2 _CAN0RXDLR.Bits.DLC2 +#define CAN0RXDLR_DLC3 _CAN0RXDLR.Bits.DLC3 +#define CAN0RXDLR_DLC _CAN0RXDLR.MergedBits.grpDLC + + +/*** CAN0TXIDR0 - MSCAN 0 Transmit Identifier Register 0; 0x00000170 ***/ +typedef union { + byte Byte; + struct { + byte ID21 :1; /* Extended format identifier Bit 21 */ + byte ID22 :1; /* Extended format identifier Bit 22 */ + byte ID23 :1; /* Extended format identifier Bit 23 */ + byte ID24 :1; /* Extended format identifier Bit 24 */ + byte ID25 :1; /* Extended format identifier Bit 25 */ + byte ID26 :1; /* Extended format identifier Bit 26 */ + byte ID27 :1; /* Extended format identifier Bit 27 */ + byte ID28 :1; /* Extended format identifier Bit 28 */ + } Bits; + struct { + byte grpID_21 :8; + } MergedBits; +} CAN0TXIDR0STR; +extern volatile CAN0TXIDR0STR _CAN0TXIDR0 @(REG_BASE + 0x00000170); +#define CAN0TXIDR0 _CAN0TXIDR0.Byte +#define CAN0TXIDR0_ID21 _CAN0TXIDR0.Bits.ID21 +#define CAN0TXIDR0_ID22 _CAN0TXIDR0.Bits.ID22 +#define CAN0TXIDR0_ID23 _CAN0TXIDR0.Bits.ID23 +#define CAN0TXIDR0_ID24 _CAN0TXIDR0.Bits.ID24 +#define CAN0TXIDR0_ID25 _CAN0TXIDR0.Bits.ID25 +#define CAN0TXIDR0_ID26 _CAN0TXIDR0.Bits.ID26 +#define CAN0TXIDR0_ID27 _CAN0TXIDR0.Bits.ID27 +#define CAN0TXIDR0_ID28 _CAN0TXIDR0.Bits.ID28 +#define CAN0TXIDR0_ID_21 _CAN0TXIDR0.MergedBits.grpID_21 +#define CAN0TXIDR0_ID CAN0TXIDR0_ID_21 + + +/*** CAN0TXIDR1 - MSCAN 0 Transmit Identifier Register 1; 0x00000171 ***/ +typedef union { + byte Byte; + struct { + byte ID15 :1; /* Extended format identifier Bit 15 */ + byte ID16 :1; /* Extended format identifier Bit 16 */ + byte ID17 :1; /* Extended format identifier Bit 17 */ + byte IDE :1; /* ID Extended */ + byte SRR :1; /* Substitute Remote Request */ + byte ID18 :1; /* Extended format identifier Bit 18 */ + byte ID19 :1; /* Extended format identifier Bit 19 */ + byte ID20 :1; /* Extended format identifier Bit 20 */ + } Bits; + struct { + byte grpID_15 :3; + byte :1; + byte :1; + byte grpID_18 :3; + } MergedBits; +} CAN0TXIDR1STR; +extern volatile CAN0TXIDR1STR _CAN0TXIDR1 @(REG_BASE + 0x00000171); +#define CAN0TXIDR1 _CAN0TXIDR1.Byte +#define CAN0TXIDR1_ID15 _CAN0TXIDR1.Bits.ID15 +#define CAN0TXIDR1_ID16 _CAN0TXIDR1.Bits.ID16 +#define CAN0TXIDR1_ID17 _CAN0TXIDR1.Bits.ID17 +#define CAN0TXIDR1_IDE _CAN0TXIDR1.Bits.IDE +#define CAN0TXIDR1_SRR _CAN0TXIDR1.Bits.SRR +#define CAN0TXIDR1_ID18 _CAN0TXIDR1.Bits.ID18 +#define CAN0TXIDR1_ID19 _CAN0TXIDR1.Bits.ID19 +#define CAN0TXIDR1_ID20 _CAN0TXIDR1.Bits.ID20 +#define CAN0TXIDR1_ID_15 _CAN0TXIDR1.MergedBits.grpID_15 +#define CAN0TXIDR1_ID_18 _CAN0TXIDR1.MergedBits.grpID_18 +#define CAN0TXIDR1_ID CAN0TXIDR1_ID_15 + + +/*** CAN0TXIDR2 - MSCAN 0 Transmit Identifier Register 2; 0x00000172 ***/ +typedef union { + byte Byte; + struct { + byte ID7 :1; /* Extended format identifier Bit 7 */ + byte ID8 :1; /* Extended format identifier Bit 8 */ + byte ID9 :1; /* Extended format identifier Bit 9 */ + byte ID10 :1; /* Extended format identifier Bit 10 */ + byte ID11 :1; /* Extended format identifier Bit 11 */ + byte ID12 :1; /* Extended format identifier Bit 12 */ + byte ID13 :1; /* Extended format identifier Bit 13 */ + byte ID14 :1; /* Extended format identifier Bit 14 */ + } Bits; + struct { + byte grpID_7 :8; + } MergedBits; +} CAN0TXIDR2STR; +extern volatile CAN0TXIDR2STR _CAN0TXIDR2 @(REG_BASE + 0x00000172); +#define CAN0TXIDR2 _CAN0TXIDR2.Byte +#define CAN0TXIDR2_ID7 _CAN0TXIDR2.Bits.ID7 +#define CAN0TXIDR2_ID8 _CAN0TXIDR2.Bits.ID8 +#define CAN0TXIDR2_ID9 _CAN0TXIDR2.Bits.ID9 +#define CAN0TXIDR2_ID10 _CAN0TXIDR2.Bits.ID10 +#define CAN0TXIDR2_ID11 _CAN0TXIDR2.Bits.ID11 +#define CAN0TXIDR2_ID12 _CAN0TXIDR2.Bits.ID12 +#define CAN0TXIDR2_ID13 _CAN0TXIDR2.Bits.ID13 +#define CAN0TXIDR2_ID14 _CAN0TXIDR2.Bits.ID14 +#define CAN0TXIDR2_ID_7 _CAN0TXIDR2.MergedBits.grpID_7 +#define CAN0TXIDR2_ID CAN0TXIDR2_ID_7 + + +/*** CAN0TXIDR3 - MSCAN 0 Transmit Identifier Register 3; 0x00000173 ***/ +typedef union { + byte Byte; + struct { + byte RTR :1; /* Remote Transmission Request */ + byte ID0 :1; /* Extended format identifier Bit 0 */ + byte ID1 :1; /* Extended format identifier Bit 1 */ + byte ID2 :1; /* Extended format identifier Bit 2 */ + byte ID3 :1; /* Extended format identifier Bit 3 */ + byte ID4 :1; /* Extended format identifier Bit 4 */ + byte ID5 :1; /* Extended format identifier Bit 5 */ + byte ID6 :1; /* Extended format identifier Bit 6 */ + } Bits; + struct { + byte :1; + byte grpID :7; + } MergedBits; +} CAN0TXIDR3STR; +extern volatile CAN0TXIDR3STR _CAN0TXIDR3 @(REG_BASE + 0x00000173); +#define CAN0TXIDR3 _CAN0TXIDR3.Byte +#define CAN0TXIDR3_RTR _CAN0TXIDR3.Bits.RTR +#define CAN0TXIDR3_ID0 _CAN0TXIDR3.Bits.ID0 +#define CAN0TXIDR3_ID1 _CAN0TXIDR3.Bits.ID1 +#define CAN0TXIDR3_ID2 _CAN0TXIDR3.Bits.ID2 +#define CAN0TXIDR3_ID3 _CAN0TXIDR3.Bits.ID3 +#define CAN0TXIDR3_ID4 _CAN0TXIDR3.Bits.ID4 +#define CAN0TXIDR3_ID5 _CAN0TXIDR3.Bits.ID5 +#define CAN0TXIDR3_ID6 _CAN0TXIDR3.Bits.ID6 +#define CAN0TXIDR3_ID _CAN0TXIDR3.MergedBits.grpID + + +/*** CAN0TXDSR0 - MSCAN 0 Transmit Data Segment Register 0; 0x00000174 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN0TXDSR0STR; +extern volatile CAN0TXDSR0STR _CAN0TXDSR0 @(REG_BASE + 0x00000174); +#define CAN0TXDSR0 _CAN0TXDSR0.Byte +#define CAN0TXDSR0_DB0 _CAN0TXDSR0.Bits.DB0 +#define CAN0TXDSR0_DB1 _CAN0TXDSR0.Bits.DB1 +#define CAN0TXDSR0_DB2 _CAN0TXDSR0.Bits.DB2 +#define CAN0TXDSR0_DB3 _CAN0TXDSR0.Bits.DB3 +#define CAN0TXDSR0_DB4 _CAN0TXDSR0.Bits.DB4 +#define CAN0TXDSR0_DB5 _CAN0TXDSR0.Bits.DB5 +#define CAN0TXDSR0_DB6 _CAN0TXDSR0.Bits.DB6 +#define CAN0TXDSR0_DB7 _CAN0TXDSR0.Bits.DB7 +#define CAN0TXDSR0_DB _CAN0TXDSR0.MergedBits.grpDB + + +/*** CAN0TXDSR1 - MSCAN 0 Transmit Data Segment Register 1; 0x00000175 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN0TXDSR1STR; +extern volatile CAN0TXDSR1STR _CAN0TXDSR1 @(REG_BASE + 0x00000175); +#define CAN0TXDSR1 _CAN0TXDSR1.Byte +#define CAN0TXDSR1_DB0 _CAN0TXDSR1.Bits.DB0 +#define CAN0TXDSR1_DB1 _CAN0TXDSR1.Bits.DB1 +#define CAN0TXDSR1_DB2 _CAN0TXDSR1.Bits.DB2 +#define CAN0TXDSR1_DB3 _CAN0TXDSR1.Bits.DB3 +#define CAN0TXDSR1_DB4 _CAN0TXDSR1.Bits.DB4 +#define CAN0TXDSR1_DB5 _CAN0TXDSR1.Bits.DB5 +#define CAN0TXDSR1_DB6 _CAN0TXDSR1.Bits.DB6 +#define CAN0TXDSR1_DB7 _CAN0TXDSR1.Bits.DB7 +#define CAN0TXDSR1_DB _CAN0TXDSR1.MergedBits.grpDB + + +/*** CAN0TXDSR2 - MSCAN 0 Transmit Data Segment Register 2; 0x00000176 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN0TXDSR2STR; +extern volatile CAN0TXDSR2STR _CAN0TXDSR2 @(REG_BASE + 0x00000176); +#define CAN0TXDSR2 _CAN0TXDSR2.Byte +#define CAN0TXDSR2_DB0 _CAN0TXDSR2.Bits.DB0 +#define CAN0TXDSR2_DB1 _CAN0TXDSR2.Bits.DB1 +#define CAN0TXDSR2_DB2 _CAN0TXDSR2.Bits.DB2 +#define CAN0TXDSR2_DB3 _CAN0TXDSR2.Bits.DB3 +#define CAN0TXDSR2_DB4 _CAN0TXDSR2.Bits.DB4 +#define CAN0TXDSR2_DB5 _CAN0TXDSR2.Bits.DB5 +#define CAN0TXDSR2_DB6 _CAN0TXDSR2.Bits.DB6 +#define CAN0TXDSR2_DB7 _CAN0TXDSR2.Bits.DB7 +#define CAN0TXDSR2_DB _CAN0TXDSR2.MergedBits.grpDB + + +/*** CAN0TXDSR3 - MSCAN 0 Transmit Data Segment Register 3; 0x00000177 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN0TXDSR3STR; +extern volatile CAN0TXDSR3STR _CAN0TXDSR3 @(REG_BASE + 0x00000177); +#define CAN0TXDSR3 _CAN0TXDSR3.Byte +#define CAN0TXDSR3_DB0 _CAN0TXDSR3.Bits.DB0 +#define CAN0TXDSR3_DB1 _CAN0TXDSR3.Bits.DB1 +#define CAN0TXDSR3_DB2 _CAN0TXDSR3.Bits.DB2 +#define CAN0TXDSR3_DB3 _CAN0TXDSR3.Bits.DB3 +#define CAN0TXDSR3_DB4 _CAN0TXDSR3.Bits.DB4 +#define CAN0TXDSR3_DB5 _CAN0TXDSR3.Bits.DB5 +#define CAN0TXDSR3_DB6 _CAN0TXDSR3.Bits.DB6 +#define CAN0TXDSR3_DB7 _CAN0TXDSR3.Bits.DB7 +#define CAN0TXDSR3_DB _CAN0TXDSR3.MergedBits.grpDB + + +/*** CAN0TXDSR4 - MSCAN 0 Transmit Data Segment Register 4; 0x00000178 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN0TXDSR4STR; +extern volatile CAN0TXDSR4STR _CAN0TXDSR4 @(REG_BASE + 0x00000178); +#define CAN0TXDSR4 _CAN0TXDSR4.Byte +#define CAN0TXDSR4_DB0 _CAN0TXDSR4.Bits.DB0 +#define CAN0TXDSR4_DB1 _CAN0TXDSR4.Bits.DB1 +#define CAN0TXDSR4_DB2 _CAN0TXDSR4.Bits.DB2 +#define CAN0TXDSR4_DB3 _CAN0TXDSR4.Bits.DB3 +#define CAN0TXDSR4_DB4 _CAN0TXDSR4.Bits.DB4 +#define CAN0TXDSR4_DB5 _CAN0TXDSR4.Bits.DB5 +#define CAN0TXDSR4_DB6 _CAN0TXDSR4.Bits.DB6 +#define CAN0TXDSR4_DB7 _CAN0TXDSR4.Bits.DB7 +#define CAN0TXDSR4_DB _CAN0TXDSR4.MergedBits.grpDB + + +/*** CAN0TXDSR5 - MSCAN 0 Transmit Data Segment Register 5; 0x00000179 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN0TXDSR5STR; +extern volatile CAN0TXDSR5STR _CAN0TXDSR5 @(REG_BASE + 0x00000179); +#define CAN0TXDSR5 _CAN0TXDSR5.Byte +#define CAN0TXDSR5_DB0 _CAN0TXDSR5.Bits.DB0 +#define CAN0TXDSR5_DB1 _CAN0TXDSR5.Bits.DB1 +#define CAN0TXDSR5_DB2 _CAN0TXDSR5.Bits.DB2 +#define CAN0TXDSR5_DB3 _CAN0TXDSR5.Bits.DB3 +#define CAN0TXDSR5_DB4 _CAN0TXDSR5.Bits.DB4 +#define CAN0TXDSR5_DB5 _CAN0TXDSR5.Bits.DB5 +#define CAN0TXDSR5_DB6 _CAN0TXDSR5.Bits.DB6 +#define CAN0TXDSR5_DB7 _CAN0TXDSR5.Bits.DB7 +#define CAN0TXDSR5_DB _CAN0TXDSR5.MergedBits.grpDB + + +/*** CAN0TXDSR6 - MSCAN 0 Transmit Data Segment Register 6; 0x0000017A ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN0TXDSR6STR; +extern volatile CAN0TXDSR6STR _CAN0TXDSR6 @(REG_BASE + 0x0000017A); +#define CAN0TXDSR6 _CAN0TXDSR6.Byte +#define CAN0TXDSR6_DB0 _CAN0TXDSR6.Bits.DB0 +#define CAN0TXDSR6_DB1 _CAN0TXDSR6.Bits.DB1 +#define CAN0TXDSR6_DB2 _CAN0TXDSR6.Bits.DB2 +#define CAN0TXDSR6_DB3 _CAN0TXDSR6.Bits.DB3 +#define CAN0TXDSR6_DB4 _CAN0TXDSR6.Bits.DB4 +#define CAN0TXDSR6_DB5 _CAN0TXDSR6.Bits.DB5 +#define CAN0TXDSR6_DB6 _CAN0TXDSR6.Bits.DB6 +#define CAN0TXDSR6_DB7 _CAN0TXDSR6.Bits.DB7 +#define CAN0TXDSR6_DB _CAN0TXDSR6.MergedBits.grpDB + + +/*** CAN0TXDSR7 - MSCAN 0 Transmit Data Segment Register 7; 0x0000017B ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN0TXDSR7STR; +extern volatile CAN0TXDSR7STR _CAN0TXDSR7 @(REG_BASE + 0x0000017B); +#define CAN0TXDSR7 _CAN0TXDSR7.Byte +#define CAN0TXDSR7_DB0 _CAN0TXDSR7.Bits.DB0 +#define CAN0TXDSR7_DB1 _CAN0TXDSR7.Bits.DB1 +#define CAN0TXDSR7_DB2 _CAN0TXDSR7.Bits.DB2 +#define CAN0TXDSR7_DB3 _CAN0TXDSR7.Bits.DB3 +#define CAN0TXDSR7_DB4 _CAN0TXDSR7.Bits.DB4 +#define CAN0TXDSR7_DB5 _CAN0TXDSR7.Bits.DB5 +#define CAN0TXDSR7_DB6 _CAN0TXDSR7.Bits.DB6 +#define CAN0TXDSR7_DB7 _CAN0TXDSR7.Bits.DB7 +#define CAN0TXDSR7_DB _CAN0TXDSR7.MergedBits.grpDB + + +/*** CAN0TXDLR - MSCAN 0 Transmit Data Length Register; 0x0000017C ***/ +typedef union { + byte Byte; + struct { + byte DLC0 :1; /* Data Length Code Bit 0 */ + byte DLC1 :1; /* Data Length Code Bit 1 */ + byte DLC2 :1; /* Data Length Code Bit 2 */ + byte DLC3 :1; /* Data Length Code Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpDLC :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN0TXDLRSTR; +extern volatile CAN0TXDLRSTR _CAN0TXDLR @(REG_BASE + 0x0000017C); +#define CAN0TXDLR _CAN0TXDLR.Byte +#define CAN0TXDLR_DLC0 _CAN0TXDLR.Bits.DLC0 +#define CAN0TXDLR_DLC1 _CAN0TXDLR.Bits.DLC1 +#define CAN0TXDLR_DLC2 _CAN0TXDLR.Bits.DLC2 +#define CAN0TXDLR_DLC3 _CAN0TXDLR.Bits.DLC3 +#define CAN0TXDLR_DLC _CAN0TXDLR.MergedBits.grpDLC + + +/*** CAN0TXTBPR - MSCAN 0 Transmit Buffer Priority; 0x0000017F ***/ +typedef union { + byte Byte; + struct { + byte PRIO0 :1; /* Transmit Buffer Priority Bit 0 */ + byte PRIO1 :1; /* Transmit Buffer Priority Bit 1 */ + byte PRIO2 :1; /* Transmit Buffer Priority Bit 2 */ + byte PRIO3 :1; /* Transmit Buffer Priority Bit 3 */ + byte PRIO4 :1; /* Transmit Buffer Priority Bit 4 */ + byte PRIO5 :1; /* Transmit Buffer Priority Bit 5 */ + byte PRIO6 :1; /* Transmit Buffer Priority Bit 6 */ + byte PRIO7 :1; /* Transmit Buffer Priority Bit 7 */ + } Bits; + struct { + byte grpPRIO :8; + } MergedBits; +} CAN0TXTBPRSTR; +extern volatile CAN0TXTBPRSTR _CAN0TXTBPR @(REG_BASE + 0x0000017F); +#define CAN0TXTBPR _CAN0TXTBPR.Byte +#define CAN0TXTBPR_PRIO0 _CAN0TXTBPR.Bits.PRIO0 +#define CAN0TXTBPR_PRIO1 _CAN0TXTBPR.Bits.PRIO1 +#define CAN0TXTBPR_PRIO2 _CAN0TXTBPR.Bits.PRIO2 +#define CAN0TXTBPR_PRIO3 _CAN0TXTBPR.Bits.PRIO3 +#define CAN0TXTBPR_PRIO4 _CAN0TXTBPR.Bits.PRIO4 +#define CAN0TXTBPR_PRIO5 _CAN0TXTBPR.Bits.PRIO5 +#define CAN0TXTBPR_PRIO6 _CAN0TXTBPR.Bits.PRIO6 +#define CAN0TXTBPR_PRIO7 _CAN0TXTBPR.Bits.PRIO7 +#define CAN0TXTBPR_PRIO _CAN0TXTBPR.MergedBits.grpPRIO + + +/*** CAN1CTL0 - MSCAN 1 Control 0 Register; 0x00000180 ***/ +typedef union { + byte Byte; + struct { + byte INITRQ :1; /* Initialization Mode Request */ + byte SLPRQ :1; /* Sleep Mode Request */ + byte WUPE :1; /* Wake-Up Enable */ + byte TIME :1; /* Timer Enable */ + byte SYNCH :1; /* Synchronized Status */ + byte CSWAI :1; /* CAN Stops in Wait Mode */ + byte RXACT :1; /* Receiver Active Status */ + byte RXFRM :1; /* Received Frame Flag */ + } Bits; +} CAN1CTL0STR; +extern volatile CAN1CTL0STR _CAN1CTL0 @(REG_BASE + 0x00000180); +#define CAN1CTL0 _CAN1CTL0.Byte +#define CAN1CTL0_INITRQ _CAN1CTL0.Bits.INITRQ +#define CAN1CTL0_SLPRQ _CAN1CTL0.Bits.SLPRQ +#define CAN1CTL0_WUPE _CAN1CTL0.Bits.WUPE +#define CAN1CTL0_TIME _CAN1CTL0.Bits.TIME +#define CAN1CTL0_SYNCH _CAN1CTL0.Bits.SYNCH +#define CAN1CTL0_CSWAI _CAN1CTL0.Bits.CSWAI +#define CAN1CTL0_RXACT _CAN1CTL0.Bits.RXACT +#define CAN1CTL0_RXFRM _CAN1CTL0.Bits.RXFRM + + +/*** CAN1CTL1 - MSCAN 1 Control 1 Register; 0x00000181 ***/ +typedef union { + byte Byte; + struct { + byte INITAK :1; /* Initialization Mode Acknowledge */ + byte SLPAK :1; /* Sleep Mode Acknowledge */ + byte WUPM :1; /* Wake-Up Mode */ + byte :1; + byte LISTEN :1; /* Listen Only Mode */ + byte LOOPB :1; /* Loop Back Self Test Mode */ + byte CLKSRC :1; /* MSCAN 1 Clock Source */ + byte CANE :1; /* MSCAN 1 Enable */ + } Bits; +} CAN1CTL1STR; +extern volatile CAN1CTL1STR _CAN1CTL1 @(REG_BASE + 0x00000181); +#define CAN1CTL1 _CAN1CTL1.Byte +#define CAN1CTL1_INITAK _CAN1CTL1.Bits.INITAK +#define CAN1CTL1_SLPAK _CAN1CTL1.Bits.SLPAK +#define CAN1CTL1_WUPM _CAN1CTL1.Bits.WUPM +#define CAN1CTL1_LISTEN _CAN1CTL1.Bits.LISTEN +#define CAN1CTL1_LOOPB _CAN1CTL1.Bits.LOOPB +#define CAN1CTL1_CLKSRC _CAN1CTL1.Bits.CLKSRC +#define CAN1CTL1_CANE _CAN1CTL1.Bits.CANE + + +/*** CAN1BTR0 - MSCAN 1 Bus Timing Register 0; 0x00000182 ***/ +typedef union { + byte Byte; + struct { + byte BRP0 :1; /* Baud Rate Prescaler 0 */ + byte BRP1 :1; /* Baud Rate Prescaler 1 */ + byte BRP2 :1; /* Baud Rate Prescaler 2 */ + byte BRP3 :1; /* Baud Rate Prescaler 3 */ + byte BRP4 :1; /* Baud Rate Prescaler 4 */ + byte BRP5 :1; /* Baud Rate Prescaler 5 */ + byte SJW0 :1; /* Synchronization Jump Width 0 */ + byte SJW1 :1; /* Synchronization Jump Width 1 */ + } Bits; + struct { + byte grpBRP :6; + byte grpSJW :2; + } MergedBits; +} CAN1BTR0STR; +extern volatile CAN1BTR0STR _CAN1BTR0 @(REG_BASE + 0x00000182); +#define CAN1BTR0 _CAN1BTR0.Byte +#define CAN1BTR0_BRP0 _CAN1BTR0.Bits.BRP0 +#define CAN1BTR0_BRP1 _CAN1BTR0.Bits.BRP1 +#define CAN1BTR0_BRP2 _CAN1BTR0.Bits.BRP2 +#define CAN1BTR0_BRP3 _CAN1BTR0.Bits.BRP3 +#define CAN1BTR0_BRP4 _CAN1BTR0.Bits.BRP4 +#define CAN1BTR0_BRP5 _CAN1BTR0.Bits.BRP5 +#define CAN1BTR0_SJW0 _CAN1BTR0.Bits.SJW0 +#define CAN1BTR0_SJW1 _CAN1BTR0.Bits.SJW1 +#define CAN1BTR0_BRP _CAN1BTR0.MergedBits.grpBRP +#define CAN1BTR0_SJW _CAN1BTR0.MergedBits.grpSJW + + +/*** CAN1BTR1 - MSCAN 1 Bus Timing Register 1; 0x00000183 ***/ +typedef union { + byte Byte; + struct { + byte TSEG10 :1; /* Time Segment 1 */ + byte TSEG11 :1; /* Time Segment 1 */ + byte TSEG12 :1; /* Time Segment 1 */ + byte TSEG13 :1; /* Time Segment 1 */ + byte TSEG20 :1; /* Time Segment 2 */ + byte TSEG21 :1; /* Time Segment 2 */ + byte TSEG22 :1; /* Time Segment 2 */ + byte SAMP :1; /* Sampling */ + } Bits; + struct { + byte grpTSEG_10 :4; + byte grpTSEG_20 :3; + byte :1; + } MergedBits; +} CAN1BTR1STR; +extern volatile CAN1BTR1STR _CAN1BTR1 @(REG_BASE + 0x00000183); +#define CAN1BTR1 _CAN1BTR1.Byte +#define CAN1BTR1_TSEG10 _CAN1BTR1.Bits.TSEG10 +#define CAN1BTR1_TSEG11 _CAN1BTR1.Bits.TSEG11 +#define CAN1BTR1_TSEG12 _CAN1BTR1.Bits.TSEG12 +#define CAN1BTR1_TSEG13 _CAN1BTR1.Bits.TSEG13 +#define CAN1BTR1_TSEG20 _CAN1BTR1.Bits.TSEG20 +#define CAN1BTR1_TSEG21 _CAN1BTR1.Bits.TSEG21 +#define CAN1BTR1_TSEG22 _CAN1BTR1.Bits.TSEG22 +#define CAN1BTR1_SAMP _CAN1BTR1.Bits.SAMP +#define CAN1BTR1_TSEG_10 _CAN1BTR1.MergedBits.grpTSEG_10 +#define CAN1BTR1_TSEG_20 _CAN1BTR1.MergedBits.grpTSEG_20 +#define CAN1BTR1_TSEG CAN1BTR1_TSEG_10 + + +/*** CAN1RFLG - MSCAN 1 Receiver Flag Register; 0x00000184 ***/ +typedef union { + byte Byte; + struct { + byte RXF :1; /* Receive Buffer Full */ + byte OVRIF :1; /* Overrun Interrupt Flag */ + byte TSTAT0 :1; /* Transmitter Status Bit 0 */ + byte TSTAT1 :1; /* Transmitter Status Bit 1 */ + byte RSTAT0 :1; /* Receiver Status Bit 0 */ + byte RSTAT1 :1; /* Receiver Status Bit 1 */ + byte CSCIF :1; /* CAN Status Change Interrupt Flag */ + byte WUPIF :1; /* Wake-up Interrupt Flag */ + } Bits; + struct { + byte :1; + byte :1; + byte grpTSTAT :2; + byte grpRSTAT :2; + byte :1; + byte :1; + } MergedBits; +} CAN1RFLGSTR; +extern volatile CAN1RFLGSTR _CAN1RFLG @(REG_BASE + 0x00000184); +#define CAN1RFLG _CAN1RFLG.Byte +#define CAN1RFLG_RXF _CAN1RFLG.Bits.RXF +#define CAN1RFLG_OVRIF _CAN1RFLG.Bits.OVRIF +#define CAN1RFLG_TSTAT0 _CAN1RFLG.Bits.TSTAT0 +#define CAN1RFLG_TSTAT1 _CAN1RFLG.Bits.TSTAT1 +#define CAN1RFLG_RSTAT0 _CAN1RFLG.Bits.RSTAT0 +#define CAN1RFLG_RSTAT1 _CAN1RFLG.Bits.RSTAT1 +#define CAN1RFLG_CSCIF _CAN1RFLG.Bits.CSCIF +#define CAN1RFLG_WUPIF _CAN1RFLG.Bits.WUPIF +#define CAN1RFLG_TSTAT _CAN1RFLG.MergedBits.grpTSTAT +#define CAN1RFLG_RSTAT _CAN1RFLG.MergedBits.grpRSTAT + + +/*** CAN1RIER - MSCAN 1 Receiver Interrupt Enable Register; 0x00000185 ***/ +typedef union { + byte Byte; + struct { + byte RXFIE :1; /* Receiver Full Interrupt Enable */ + byte OVRIE :1; /* Overrun Interrupt Enable */ + byte TSTATE0 :1; /* Transmitter Status Change Enable 0 */ + byte TSTATE1 :1; /* Transmitter Status Change Enable 1 */ + byte RSTATE0 :1; /* Receiver Status Change Enable 0 */ + byte RSTATE1 :1; /* Receiver Status Change Enable 1 */ + byte CSCIE :1; /* CAN Status Change Interrupt Enable */ + byte WUPIE :1; /* Wake-up Interrupt Enable */ + } Bits; + struct { + byte :1; + byte :1; + byte grpTSTATE :2; + byte grpRSTATE :2; + byte :1; + byte :1; + } MergedBits; +} CAN1RIERSTR; +extern volatile CAN1RIERSTR _CAN1RIER @(REG_BASE + 0x00000185); +#define CAN1RIER _CAN1RIER.Byte +#define CAN1RIER_RXFIE _CAN1RIER.Bits.RXFIE +#define CAN1RIER_OVRIE _CAN1RIER.Bits.OVRIE +#define CAN1RIER_TSTATE0 _CAN1RIER.Bits.TSTATE0 +#define CAN1RIER_TSTATE1 _CAN1RIER.Bits.TSTATE1 +#define CAN1RIER_RSTATE0 _CAN1RIER.Bits.RSTATE0 +#define CAN1RIER_RSTATE1 _CAN1RIER.Bits.RSTATE1 +#define CAN1RIER_CSCIE _CAN1RIER.Bits.CSCIE +#define CAN1RIER_WUPIE _CAN1RIER.Bits.WUPIE +#define CAN1RIER_TSTATE _CAN1RIER.MergedBits.grpTSTATE +#define CAN1RIER_RSTATE _CAN1RIER.MergedBits.grpRSTATE + + +/*** CAN1TFLG - MSCAN 1 Transmitter Flag Register; 0x00000186 ***/ +typedef union { + byte Byte; + struct { + byte TXE0 :1; /* Transmitter Buffer Empty 0 */ + byte TXE1 :1; /* Transmitter Buffer Empty 1 */ + byte TXE2 :1; /* Transmitter Buffer Empty 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpTXE :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN1TFLGSTR; +extern volatile CAN1TFLGSTR _CAN1TFLG @(REG_BASE + 0x00000186); +#define CAN1TFLG _CAN1TFLG.Byte +#define CAN1TFLG_TXE0 _CAN1TFLG.Bits.TXE0 +#define CAN1TFLG_TXE1 _CAN1TFLG.Bits.TXE1 +#define CAN1TFLG_TXE2 _CAN1TFLG.Bits.TXE2 +#define CAN1TFLG_TXE _CAN1TFLG.MergedBits.grpTXE + + +/*** CAN1TIER - MSCAN 1 Transmitter Interrupt Enable Register; 0x00000187 ***/ +typedef union { + byte Byte; + struct { + byte TXEIE0 :1; /* Transmitter Empty Interrupt Enable 0 */ + byte TXEIE1 :1; /* Transmitter Empty Interrupt Enable 1 */ + byte TXEIE2 :1; /* Transmitter Empty Interrupt Enable 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpTXEIE :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN1TIERSTR; +extern volatile CAN1TIERSTR _CAN1TIER @(REG_BASE + 0x00000187); +#define CAN1TIER _CAN1TIER.Byte +#define CAN1TIER_TXEIE0 _CAN1TIER.Bits.TXEIE0 +#define CAN1TIER_TXEIE1 _CAN1TIER.Bits.TXEIE1 +#define CAN1TIER_TXEIE2 _CAN1TIER.Bits.TXEIE2 +#define CAN1TIER_TXEIE _CAN1TIER.MergedBits.grpTXEIE + + +/*** CAN1TARQ - MSCAN 1 Transmitter Message Abort Request; 0x00000188 ***/ +typedef union { + byte Byte; + struct { + byte ABTRQ0 :1; /* Abort Request 0 */ + byte ABTRQ1 :1; /* Abort Request 1 */ + byte ABTRQ2 :1; /* Abort Request 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpABTRQ :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN1TARQSTR; +extern volatile CAN1TARQSTR _CAN1TARQ @(REG_BASE + 0x00000188); +#define CAN1TARQ _CAN1TARQ.Byte +#define CAN1TARQ_ABTRQ0 _CAN1TARQ.Bits.ABTRQ0 +#define CAN1TARQ_ABTRQ1 _CAN1TARQ.Bits.ABTRQ1 +#define CAN1TARQ_ABTRQ2 _CAN1TARQ.Bits.ABTRQ2 +#define CAN1TARQ_ABTRQ _CAN1TARQ.MergedBits.grpABTRQ + + +/*** CAN1TAAK - MSCAN 1 Transmitter Message Abort Control; 0x00000189 ***/ +typedef union { + byte Byte; + struct { + byte ABTAK0 :1; /* Abort Acknowledge 0 */ + byte ABTAK1 :1; /* Abort Acknowledge 1 */ + byte ABTAK2 :1; /* Abort Acknowledge 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpABTAK :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN1TAAKSTR; +extern volatile CAN1TAAKSTR _CAN1TAAK @(REG_BASE + 0x00000189); +#define CAN1TAAK _CAN1TAAK.Byte +#define CAN1TAAK_ABTAK0 _CAN1TAAK.Bits.ABTAK0 +#define CAN1TAAK_ABTAK1 _CAN1TAAK.Bits.ABTAK1 +#define CAN1TAAK_ABTAK2 _CAN1TAAK.Bits.ABTAK2 +#define CAN1TAAK_ABTAK _CAN1TAAK.MergedBits.grpABTAK + + +/*** CAN1TBSEL - MSCAN 1 Transmit Buffer Selection; 0x0000018A ***/ +typedef union { + byte Byte; + struct { + byte TX0 :1; /* Transmit Buffer Select 0 */ + byte TX1 :1; /* Transmit Buffer Select 1 */ + byte TX2 :1; /* Transmit Buffer Select 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpTX :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN1TBSELSTR; +extern volatile CAN1TBSELSTR _CAN1TBSEL @(REG_BASE + 0x0000018A); +#define CAN1TBSEL _CAN1TBSEL.Byte +#define CAN1TBSEL_TX0 _CAN1TBSEL.Bits.TX0 +#define CAN1TBSEL_TX1 _CAN1TBSEL.Bits.TX1 +#define CAN1TBSEL_TX2 _CAN1TBSEL.Bits.TX2 +#define CAN1TBSEL_TX _CAN1TBSEL.MergedBits.grpTX + + +/*** CAN1IDAC - MSCAN 1 Identifier Acceptance Control Register; 0x0000018B ***/ +typedef union { + byte Byte; + struct { + byte IDHIT0 :1; /* Identifier Acceptance Hit Indicator 0 */ + byte IDHIT1 :1; /* Identifier Acceptance Hit Indicator 1 */ + byte IDHIT2 :1; /* Identifier Acceptance Hit Indicator 2 */ + byte :1; + byte IDAM0 :1; /* Identifier Acceptance Mode 0 */ + byte IDAM1 :1; /* Identifier Acceptance Mode 1 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpIDHIT :3; + byte :1; + byte grpIDAM :2; + byte :1; + byte :1; + } MergedBits; +} CAN1IDACSTR; +extern volatile CAN1IDACSTR _CAN1IDAC @(REG_BASE + 0x0000018B); +#define CAN1IDAC _CAN1IDAC.Byte +#define CAN1IDAC_IDHIT0 _CAN1IDAC.Bits.IDHIT0 +#define CAN1IDAC_IDHIT1 _CAN1IDAC.Bits.IDHIT1 +#define CAN1IDAC_IDHIT2 _CAN1IDAC.Bits.IDHIT2 +#define CAN1IDAC_IDAM0 _CAN1IDAC.Bits.IDAM0 +#define CAN1IDAC_IDAM1 _CAN1IDAC.Bits.IDAM1 +#define CAN1IDAC_IDHIT _CAN1IDAC.MergedBits.grpIDHIT +#define CAN1IDAC_IDAM _CAN1IDAC.MergedBits.grpIDAM + + +/*** CAN1RXERR - MSCAN 1 Receive Error Counter Register; 0x0000018E ***/ +typedef union { + byte Byte; + struct { + byte RXERR0 :1; /* Bit 0 */ + byte RXERR1 :1; /* Bit 1 */ + byte RXERR2 :1; /* Bit 2 */ + byte RXERR3 :1; /* Bit 3 */ + byte RXERR4 :1; /* Bit 4 */ + byte RXERR5 :1; /* Bit 5 */ + byte RXERR6 :1; /* Bit 6 */ + byte RXERR7 :1; /* Bit 7 */ + } Bits; + struct { + byte grpRXERR :8; + } MergedBits; +} CAN1RXERRSTR; +extern volatile CAN1RXERRSTR _CAN1RXERR @(REG_BASE + 0x0000018E); +#define CAN1RXERR _CAN1RXERR.Byte +#define CAN1RXERR_RXERR0 _CAN1RXERR.Bits.RXERR0 +#define CAN1RXERR_RXERR1 _CAN1RXERR.Bits.RXERR1 +#define CAN1RXERR_RXERR2 _CAN1RXERR.Bits.RXERR2 +#define CAN1RXERR_RXERR3 _CAN1RXERR.Bits.RXERR3 +#define CAN1RXERR_RXERR4 _CAN1RXERR.Bits.RXERR4 +#define CAN1RXERR_RXERR5 _CAN1RXERR.Bits.RXERR5 +#define CAN1RXERR_RXERR6 _CAN1RXERR.Bits.RXERR6 +#define CAN1RXERR_RXERR7 _CAN1RXERR.Bits.RXERR7 +#define CAN1RXERR_RXERR _CAN1RXERR.MergedBits.grpRXERR + + +/*** CAN1TXERR - MSCAN 1 Transmit Error Counter Register; 0x0000018F ***/ +typedef union { + byte Byte; + struct { + byte TXERR0 :1; /* Bit 0 */ + byte TXERR1 :1; /* Bit 1 */ + byte TXERR2 :1; /* Bit 2 */ + byte TXERR3 :1; /* Bit 3 */ + byte TXERR4 :1; /* Bit 4 */ + byte TXERR5 :1; /* Bit 5 */ + byte TXERR6 :1; /* Bit 6 */ + byte TXERR7 :1; /* Bit 7 */ + } Bits; + struct { + byte grpTXERR :8; + } MergedBits; +} CAN1TXERRSTR; +extern volatile CAN1TXERRSTR _CAN1TXERR @(REG_BASE + 0x0000018F); +#define CAN1TXERR _CAN1TXERR.Byte +#define CAN1TXERR_TXERR0 _CAN1TXERR.Bits.TXERR0 +#define CAN1TXERR_TXERR1 _CAN1TXERR.Bits.TXERR1 +#define CAN1TXERR_TXERR2 _CAN1TXERR.Bits.TXERR2 +#define CAN1TXERR_TXERR3 _CAN1TXERR.Bits.TXERR3 +#define CAN1TXERR_TXERR4 _CAN1TXERR.Bits.TXERR4 +#define CAN1TXERR_TXERR5 _CAN1TXERR.Bits.TXERR5 +#define CAN1TXERR_TXERR6 _CAN1TXERR.Bits.TXERR6 +#define CAN1TXERR_TXERR7 _CAN1TXERR.Bits.TXERR7 +#define CAN1TXERR_TXERR _CAN1TXERR.MergedBits.grpTXERR + + +/*** CAN1IDAR0 - MSCAN 1 Identifier Acceptance Register 0; 0x00000190 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN1IDAR0STR; +extern volatile CAN1IDAR0STR _CAN1IDAR0 @(REG_BASE + 0x00000190); +#define CAN1IDAR0 _CAN1IDAR0.Byte +#define CAN1IDAR0_AC0 _CAN1IDAR0.Bits.AC0 +#define CAN1IDAR0_AC1 _CAN1IDAR0.Bits.AC1 +#define CAN1IDAR0_AC2 _CAN1IDAR0.Bits.AC2 +#define CAN1IDAR0_AC3 _CAN1IDAR0.Bits.AC3 +#define CAN1IDAR0_AC4 _CAN1IDAR0.Bits.AC4 +#define CAN1IDAR0_AC5 _CAN1IDAR0.Bits.AC5 +#define CAN1IDAR0_AC6 _CAN1IDAR0.Bits.AC6 +#define CAN1IDAR0_AC7 _CAN1IDAR0.Bits.AC7 +#define CAN1IDAR0_AC _CAN1IDAR0.MergedBits.grpAC + + +/*** CAN1IDAR1 - MSCAN 1 Identifier Acceptance Register 1; 0x00000191 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN1IDAR1STR; +extern volatile CAN1IDAR1STR _CAN1IDAR1 @(REG_BASE + 0x00000191); +#define CAN1IDAR1 _CAN1IDAR1.Byte +#define CAN1IDAR1_AC0 _CAN1IDAR1.Bits.AC0 +#define CAN1IDAR1_AC1 _CAN1IDAR1.Bits.AC1 +#define CAN1IDAR1_AC2 _CAN1IDAR1.Bits.AC2 +#define CAN1IDAR1_AC3 _CAN1IDAR1.Bits.AC3 +#define CAN1IDAR1_AC4 _CAN1IDAR1.Bits.AC4 +#define CAN1IDAR1_AC5 _CAN1IDAR1.Bits.AC5 +#define CAN1IDAR1_AC6 _CAN1IDAR1.Bits.AC6 +#define CAN1IDAR1_AC7 _CAN1IDAR1.Bits.AC7 +#define CAN1IDAR1_AC _CAN1IDAR1.MergedBits.grpAC + + +/*** CAN1IDAR2 - MSCAN 1 Identifier Acceptance Register 2; 0x00000192 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN1IDAR2STR; +extern volatile CAN1IDAR2STR _CAN1IDAR2 @(REG_BASE + 0x00000192); +#define CAN1IDAR2 _CAN1IDAR2.Byte +#define CAN1IDAR2_AC0 _CAN1IDAR2.Bits.AC0 +#define CAN1IDAR2_AC1 _CAN1IDAR2.Bits.AC1 +#define CAN1IDAR2_AC2 _CAN1IDAR2.Bits.AC2 +#define CAN1IDAR2_AC3 _CAN1IDAR2.Bits.AC3 +#define CAN1IDAR2_AC4 _CAN1IDAR2.Bits.AC4 +#define CAN1IDAR2_AC5 _CAN1IDAR2.Bits.AC5 +#define CAN1IDAR2_AC6 _CAN1IDAR2.Bits.AC6 +#define CAN1IDAR2_AC7 _CAN1IDAR2.Bits.AC7 +#define CAN1IDAR2_AC _CAN1IDAR2.MergedBits.grpAC + + +/*** CAN1IDAR3 - MSCAN 1 Identifier Acceptance Register 3; 0x00000193 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN1IDAR3STR; +extern volatile CAN1IDAR3STR _CAN1IDAR3 @(REG_BASE + 0x00000193); +#define CAN1IDAR3 _CAN1IDAR3.Byte +#define CAN1IDAR3_AC0 _CAN1IDAR3.Bits.AC0 +#define CAN1IDAR3_AC1 _CAN1IDAR3.Bits.AC1 +#define CAN1IDAR3_AC2 _CAN1IDAR3.Bits.AC2 +#define CAN1IDAR3_AC3 _CAN1IDAR3.Bits.AC3 +#define CAN1IDAR3_AC4 _CAN1IDAR3.Bits.AC4 +#define CAN1IDAR3_AC5 _CAN1IDAR3.Bits.AC5 +#define CAN1IDAR3_AC6 _CAN1IDAR3.Bits.AC6 +#define CAN1IDAR3_AC7 _CAN1IDAR3.Bits.AC7 +#define CAN1IDAR3_AC _CAN1IDAR3.MergedBits.grpAC + + +/*** CAN1IDMR0 - MSCAN 1 Identifier Mask Register 0; 0x00000194 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN1IDMR0STR; +extern volatile CAN1IDMR0STR _CAN1IDMR0 @(REG_BASE + 0x00000194); +#define CAN1IDMR0 _CAN1IDMR0.Byte +#define CAN1IDMR0_AM0 _CAN1IDMR0.Bits.AM0 +#define CAN1IDMR0_AM1 _CAN1IDMR0.Bits.AM1 +#define CAN1IDMR0_AM2 _CAN1IDMR0.Bits.AM2 +#define CAN1IDMR0_AM3 _CAN1IDMR0.Bits.AM3 +#define CAN1IDMR0_AM4 _CAN1IDMR0.Bits.AM4 +#define CAN1IDMR0_AM5 _CAN1IDMR0.Bits.AM5 +#define CAN1IDMR0_AM6 _CAN1IDMR0.Bits.AM6 +#define CAN1IDMR0_AM7 _CAN1IDMR0.Bits.AM7 +#define CAN1IDMR0_AM _CAN1IDMR0.MergedBits.grpAM + + +/*** CAN1IDMR1 - MSCAN 1 Identifier Mask Register 1; 0x00000195 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN1IDMR1STR; +extern volatile CAN1IDMR1STR _CAN1IDMR1 @(REG_BASE + 0x00000195); +#define CAN1IDMR1 _CAN1IDMR1.Byte +#define CAN1IDMR1_AM0 _CAN1IDMR1.Bits.AM0 +#define CAN1IDMR1_AM1 _CAN1IDMR1.Bits.AM1 +#define CAN1IDMR1_AM2 _CAN1IDMR1.Bits.AM2 +#define CAN1IDMR1_AM3 _CAN1IDMR1.Bits.AM3 +#define CAN1IDMR1_AM4 _CAN1IDMR1.Bits.AM4 +#define CAN1IDMR1_AM5 _CAN1IDMR1.Bits.AM5 +#define CAN1IDMR1_AM6 _CAN1IDMR1.Bits.AM6 +#define CAN1IDMR1_AM7 _CAN1IDMR1.Bits.AM7 +#define CAN1IDMR1_AM _CAN1IDMR1.MergedBits.grpAM + + +/*** CAN1IDMR2 - MSCAN 1 Identifier Mask Register 2; 0x00000196 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN1IDMR2STR; +extern volatile CAN1IDMR2STR _CAN1IDMR2 @(REG_BASE + 0x00000196); +#define CAN1IDMR2 _CAN1IDMR2.Byte +#define CAN1IDMR2_AM0 _CAN1IDMR2.Bits.AM0 +#define CAN1IDMR2_AM1 _CAN1IDMR2.Bits.AM1 +#define CAN1IDMR2_AM2 _CAN1IDMR2.Bits.AM2 +#define CAN1IDMR2_AM3 _CAN1IDMR2.Bits.AM3 +#define CAN1IDMR2_AM4 _CAN1IDMR2.Bits.AM4 +#define CAN1IDMR2_AM5 _CAN1IDMR2.Bits.AM5 +#define CAN1IDMR2_AM6 _CAN1IDMR2.Bits.AM6 +#define CAN1IDMR2_AM7 _CAN1IDMR2.Bits.AM7 +#define CAN1IDMR2_AM _CAN1IDMR2.MergedBits.grpAM + + +/*** CAN1IDMR3 - MSCAN 1 Identifier Mask Register 3; 0x00000197 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN1IDMR3STR; +extern volatile CAN1IDMR3STR _CAN1IDMR3 @(REG_BASE + 0x00000197); +#define CAN1IDMR3 _CAN1IDMR3.Byte +#define CAN1IDMR3_AM0 _CAN1IDMR3.Bits.AM0 +#define CAN1IDMR3_AM1 _CAN1IDMR3.Bits.AM1 +#define CAN1IDMR3_AM2 _CAN1IDMR3.Bits.AM2 +#define CAN1IDMR3_AM3 _CAN1IDMR3.Bits.AM3 +#define CAN1IDMR3_AM4 _CAN1IDMR3.Bits.AM4 +#define CAN1IDMR3_AM5 _CAN1IDMR3.Bits.AM5 +#define CAN1IDMR3_AM6 _CAN1IDMR3.Bits.AM6 +#define CAN1IDMR3_AM7 _CAN1IDMR3.Bits.AM7 +#define CAN1IDMR3_AM _CAN1IDMR3.MergedBits.grpAM + + +/*** CAN1IDAR4 - MSCAN 1 Identifier Acceptance Register 4; 0x00000198 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN1IDAR4STR; +extern volatile CAN1IDAR4STR _CAN1IDAR4 @(REG_BASE + 0x00000198); +#define CAN1IDAR4 _CAN1IDAR4.Byte +#define CAN1IDAR4_AC0 _CAN1IDAR4.Bits.AC0 +#define CAN1IDAR4_AC1 _CAN1IDAR4.Bits.AC1 +#define CAN1IDAR4_AC2 _CAN1IDAR4.Bits.AC2 +#define CAN1IDAR4_AC3 _CAN1IDAR4.Bits.AC3 +#define CAN1IDAR4_AC4 _CAN1IDAR4.Bits.AC4 +#define CAN1IDAR4_AC5 _CAN1IDAR4.Bits.AC5 +#define CAN1IDAR4_AC6 _CAN1IDAR4.Bits.AC6 +#define CAN1IDAR4_AC7 _CAN1IDAR4.Bits.AC7 +#define CAN1IDAR4_AC _CAN1IDAR4.MergedBits.grpAC + + +/*** CAN1IDAR5 - MSCAN 1 Identifier Acceptance Register 5; 0x00000199 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN1IDAR5STR; +extern volatile CAN1IDAR5STR _CAN1IDAR5 @(REG_BASE + 0x00000199); +#define CAN1IDAR5 _CAN1IDAR5.Byte +#define CAN1IDAR5_AC0 _CAN1IDAR5.Bits.AC0 +#define CAN1IDAR5_AC1 _CAN1IDAR5.Bits.AC1 +#define CAN1IDAR5_AC2 _CAN1IDAR5.Bits.AC2 +#define CAN1IDAR5_AC3 _CAN1IDAR5.Bits.AC3 +#define CAN1IDAR5_AC4 _CAN1IDAR5.Bits.AC4 +#define CAN1IDAR5_AC5 _CAN1IDAR5.Bits.AC5 +#define CAN1IDAR5_AC6 _CAN1IDAR5.Bits.AC6 +#define CAN1IDAR5_AC7 _CAN1IDAR5.Bits.AC7 +#define CAN1IDAR5_AC _CAN1IDAR5.MergedBits.grpAC + + +/*** CAN1IDAR6 - MSCAN 1 Identifier Acceptance Register 6; 0x0000019A ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN1IDAR6STR; +extern volatile CAN1IDAR6STR _CAN1IDAR6 @(REG_BASE + 0x0000019A); +#define CAN1IDAR6 _CAN1IDAR6.Byte +#define CAN1IDAR6_AC0 _CAN1IDAR6.Bits.AC0 +#define CAN1IDAR6_AC1 _CAN1IDAR6.Bits.AC1 +#define CAN1IDAR6_AC2 _CAN1IDAR6.Bits.AC2 +#define CAN1IDAR6_AC3 _CAN1IDAR6.Bits.AC3 +#define CAN1IDAR6_AC4 _CAN1IDAR6.Bits.AC4 +#define CAN1IDAR6_AC5 _CAN1IDAR6.Bits.AC5 +#define CAN1IDAR6_AC6 _CAN1IDAR6.Bits.AC6 +#define CAN1IDAR6_AC7 _CAN1IDAR6.Bits.AC7 +#define CAN1IDAR6_AC _CAN1IDAR6.MergedBits.grpAC + + +/*** CAN1IDAR7 - MSCAN 1 Identifier Acceptance Register 7; 0x0000019B ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN1IDAR7STR; +extern volatile CAN1IDAR7STR _CAN1IDAR7 @(REG_BASE + 0x0000019B); +#define CAN1IDAR7 _CAN1IDAR7.Byte +#define CAN1IDAR7_AC0 _CAN1IDAR7.Bits.AC0 +#define CAN1IDAR7_AC1 _CAN1IDAR7.Bits.AC1 +#define CAN1IDAR7_AC2 _CAN1IDAR7.Bits.AC2 +#define CAN1IDAR7_AC3 _CAN1IDAR7.Bits.AC3 +#define CAN1IDAR7_AC4 _CAN1IDAR7.Bits.AC4 +#define CAN1IDAR7_AC5 _CAN1IDAR7.Bits.AC5 +#define CAN1IDAR7_AC6 _CAN1IDAR7.Bits.AC6 +#define CAN1IDAR7_AC7 _CAN1IDAR7.Bits.AC7 +#define CAN1IDAR7_AC _CAN1IDAR7.MergedBits.grpAC + + +/*** CAN1IDMR4 - MSCAN 1 Identifier Mask Register 4; 0x0000019C ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN1IDMR4STR; +extern volatile CAN1IDMR4STR _CAN1IDMR4 @(REG_BASE + 0x0000019C); +#define CAN1IDMR4 _CAN1IDMR4.Byte +#define CAN1IDMR4_AM0 _CAN1IDMR4.Bits.AM0 +#define CAN1IDMR4_AM1 _CAN1IDMR4.Bits.AM1 +#define CAN1IDMR4_AM2 _CAN1IDMR4.Bits.AM2 +#define CAN1IDMR4_AM3 _CAN1IDMR4.Bits.AM3 +#define CAN1IDMR4_AM4 _CAN1IDMR4.Bits.AM4 +#define CAN1IDMR4_AM5 _CAN1IDMR4.Bits.AM5 +#define CAN1IDMR4_AM6 _CAN1IDMR4.Bits.AM6 +#define CAN1IDMR4_AM7 _CAN1IDMR4.Bits.AM7 +#define CAN1IDMR4_AM _CAN1IDMR4.MergedBits.grpAM + + +/*** CAN1IDMR5 - MSCAN 1 Identifier Mask Register 5; 0x0000019D ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN1IDMR5STR; +extern volatile CAN1IDMR5STR _CAN1IDMR5 @(REG_BASE + 0x0000019D); +#define CAN1IDMR5 _CAN1IDMR5.Byte +#define CAN1IDMR5_AM0 _CAN1IDMR5.Bits.AM0 +#define CAN1IDMR5_AM1 _CAN1IDMR5.Bits.AM1 +#define CAN1IDMR5_AM2 _CAN1IDMR5.Bits.AM2 +#define CAN1IDMR5_AM3 _CAN1IDMR5.Bits.AM3 +#define CAN1IDMR5_AM4 _CAN1IDMR5.Bits.AM4 +#define CAN1IDMR5_AM5 _CAN1IDMR5.Bits.AM5 +#define CAN1IDMR5_AM6 _CAN1IDMR5.Bits.AM6 +#define CAN1IDMR5_AM7 _CAN1IDMR5.Bits.AM7 +#define CAN1IDMR5_AM _CAN1IDMR5.MergedBits.grpAM + + +/*** CAN1IDMR6 - MSCAN 1 Identifier Mask Register 6; 0x0000019E ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN1IDMR6STR; +extern volatile CAN1IDMR6STR _CAN1IDMR6 @(REG_BASE + 0x0000019E); +#define CAN1IDMR6 _CAN1IDMR6.Byte +#define CAN1IDMR6_AM0 _CAN1IDMR6.Bits.AM0 +#define CAN1IDMR6_AM1 _CAN1IDMR6.Bits.AM1 +#define CAN1IDMR6_AM2 _CAN1IDMR6.Bits.AM2 +#define CAN1IDMR6_AM3 _CAN1IDMR6.Bits.AM3 +#define CAN1IDMR6_AM4 _CAN1IDMR6.Bits.AM4 +#define CAN1IDMR6_AM5 _CAN1IDMR6.Bits.AM5 +#define CAN1IDMR6_AM6 _CAN1IDMR6.Bits.AM6 +#define CAN1IDMR6_AM7 _CAN1IDMR6.Bits.AM7 +#define CAN1IDMR6_AM _CAN1IDMR6.MergedBits.grpAM + + +/*** CAN1IDMR7 - MSCAN 1 Identifier Mask Register 7; 0x0000019F ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN1IDMR7STR; +extern volatile CAN1IDMR7STR _CAN1IDMR7 @(REG_BASE + 0x0000019F); +#define CAN1IDMR7 _CAN1IDMR7.Byte +#define CAN1IDMR7_AM0 _CAN1IDMR7.Bits.AM0 +#define CAN1IDMR7_AM1 _CAN1IDMR7.Bits.AM1 +#define CAN1IDMR7_AM2 _CAN1IDMR7.Bits.AM2 +#define CAN1IDMR7_AM3 _CAN1IDMR7.Bits.AM3 +#define CAN1IDMR7_AM4 _CAN1IDMR7.Bits.AM4 +#define CAN1IDMR7_AM5 _CAN1IDMR7.Bits.AM5 +#define CAN1IDMR7_AM6 _CAN1IDMR7.Bits.AM6 +#define CAN1IDMR7_AM7 _CAN1IDMR7.Bits.AM7 +#define CAN1IDMR7_AM _CAN1IDMR7.MergedBits.grpAM + + +/*** CAN1RXIDR0 - MSCAN 1 Receive Identifier Register 0; 0x000001A0 ***/ +typedef union { + byte Byte; + struct { + byte ID21 :1; /* Extended format identifier Bit 21 */ + byte ID22 :1; /* Extended format identifier Bit 22 */ + byte ID23 :1; /* Extended format identifier Bit 23 */ + byte ID24 :1; /* Extended format identifier Bit 24 */ + byte ID25 :1; /* Extended format identifier Bit 25 */ + byte ID26 :1; /* Extended format identifier Bit 26 */ + byte ID27 :1; /* Extended format identifier Bit 27 */ + byte ID28 :1; /* Extended format identifier Bit 28 */ + } Bits; + struct { + byte grpID_21 :8; + } MergedBits; +} CAN1RXIDR0STR; +extern volatile CAN1RXIDR0STR _CAN1RXIDR0 @(REG_BASE + 0x000001A0); +#define CAN1RXIDR0 _CAN1RXIDR0.Byte +#define CAN1RXIDR0_ID21 _CAN1RXIDR0.Bits.ID21 +#define CAN1RXIDR0_ID22 _CAN1RXIDR0.Bits.ID22 +#define CAN1RXIDR0_ID23 _CAN1RXIDR0.Bits.ID23 +#define CAN1RXIDR0_ID24 _CAN1RXIDR0.Bits.ID24 +#define CAN1RXIDR0_ID25 _CAN1RXIDR0.Bits.ID25 +#define CAN1RXIDR0_ID26 _CAN1RXIDR0.Bits.ID26 +#define CAN1RXIDR0_ID27 _CAN1RXIDR0.Bits.ID27 +#define CAN1RXIDR0_ID28 _CAN1RXIDR0.Bits.ID28 +#define CAN1RXIDR0_ID_21 _CAN1RXIDR0.MergedBits.grpID_21 +#define CAN1RXIDR0_ID CAN1RXIDR0_ID_21 + + +/*** CAN1RXIDR1 - MSCAN 1 Receive Identifier Register 1; 0x000001A1 ***/ +typedef union { + byte Byte; + struct { + byte ID15 :1; /* Extended format identifier Bit 15 */ + byte ID16 :1; /* Extended format identifier Bit 16 */ + byte ID17 :1; /* Extended format identifier Bit 17 */ + byte IDE :1; /* ID Extended */ + byte SRR :1; /* Substitute Remote Request */ + byte ID18 :1; /* Extended format identifier Bit 18 */ + byte ID19 :1; /* Extended format identifier Bit 19 */ + byte ID20 :1; /* Extended format identifier Bit 20 */ + } Bits; + struct { + byte grpID_15 :3; + byte :1; + byte :1; + byte grpID_18 :3; + } MergedBits; +} CAN1RXIDR1STR; +extern volatile CAN1RXIDR1STR _CAN1RXIDR1 @(REG_BASE + 0x000001A1); +#define CAN1RXIDR1 _CAN1RXIDR1.Byte +#define CAN1RXIDR1_ID15 _CAN1RXIDR1.Bits.ID15 +#define CAN1RXIDR1_ID16 _CAN1RXIDR1.Bits.ID16 +#define CAN1RXIDR1_ID17 _CAN1RXIDR1.Bits.ID17 +#define CAN1RXIDR1_IDE _CAN1RXIDR1.Bits.IDE +#define CAN1RXIDR1_SRR _CAN1RXIDR1.Bits.SRR +#define CAN1RXIDR1_ID18 _CAN1RXIDR1.Bits.ID18 +#define CAN1RXIDR1_ID19 _CAN1RXIDR1.Bits.ID19 +#define CAN1RXIDR1_ID20 _CAN1RXIDR1.Bits.ID20 +#define CAN1RXIDR1_ID_15 _CAN1RXIDR1.MergedBits.grpID_15 +#define CAN1RXIDR1_ID_18 _CAN1RXIDR1.MergedBits.grpID_18 +#define CAN1RXIDR1_ID CAN1RXIDR1_ID_15 + + +/*** CAN1RXIDR2 - MSCAN 1 Receive Identifier Register 2; 0x000001A2 ***/ +typedef union { + byte Byte; + struct { + byte ID7 :1; /* Extended format identifier Bit 7 */ + byte ID8 :1; /* Extended format identifier Bit 8 */ + byte ID9 :1; /* Extended format identifier Bit 9 */ + byte ID10 :1; /* Extended format identifier Bit 10 */ + byte ID11 :1; /* Extended format identifier Bit 11 */ + byte ID12 :1; /* Extended format identifier Bit 12 */ + byte ID13 :1; /* Extended format identifier Bit 13 */ + byte ID14 :1; /* Extended format identifier Bit 14 */ + } Bits; + struct { + byte grpID_7 :8; + } MergedBits; +} CAN1RXIDR2STR; +extern volatile CAN1RXIDR2STR _CAN1RXIDR2 @(REG_BASE + 0x000001A2); +#define CAN1RXIDR2 _CAN1RXIDR2.Byte +#define CAN1RXIDR2_ID7 _CAN1RXIDR2.Bits.ID7 +#define CAN1RXIDR2_ID8 _CAN1RXIDR2.Bits.ID8 +#define CAN1RXIDR2_ID9 _CAN1RXIDR2.Bits.ID9 +#define CAN1RXIDR2_ID10 _CAN1RXIDR2.Bits.ID10 +#define CAN1RXIDR2_ID11 _CAN1RXIDR2.Bits.ID11 +#define CAN1RXIDR2_ID12 _CAN1RXIDR2.Bits.ID12 +#define CAN1RXIDR2_ID13 _CAN1RXIDR2.Bits.ID13 +#define CAN1RXIDR2_ID14 _CAN1RXIDR2.Bits.ID14 +#define CAN1RXIDR2_ID_7 _CAN1RXIDR2.MergedBits.grpID_7 +#define CAN1RXIDR2_ID CAN1RXIDR2_ID_7 + + +/*** CAN1RXIDR3 - MSCAN 1 Receive Identifier Register 3; 0x000001A3 ***/ +typedef union { + byte Byte; + struct { + byte RTR :1; /* Remote Transmission Request */ + byte ID0 :1; /* Extended format identifier Bit 0 */ + byte ID1 :1; /* Extended format identifier Bit 1 */ + byte ID2 :1; /* Extended format identifier Bit 2 */ + byte ID3 :1; /* Extended format identifier Bit 3 */ + byte ID4 :1; /* Extended format identifier Bit 4 */ + byte ID5 :1; /* Extended format identifier Bit 5 */ + byte ID6 :1; /* Extended format identifier Bit 6 */ + } Bits; + struct { + byte :1; + byte grpID :7; + } MergedBits; +} CAN1RXIDR3STR; +extern volatile CAN1RXIDR3STR _CAN1RXIDR3 @(REG_BASE + 0x000001A3); +#define CAN1RXIDR3 _CAN1RXIDR3.Byte +#define CAN1RXIDR3_RTR _CAN1RXIDR3.Bits.RTR +#define CAN1RXIDR3_ID0 _CAN1RXIDR3.Bits.ID0 +#define CAN1RXIDR3_ID1 _CAN1RXIDR3.Bits.ID1 +#define CAN1RXIDR3_ID2 _CAN1RXIDR3.Bits.ID2 +#define CAN1RXIDR3_ID3 _CAN1RXIDR3.Bits.ID3 +#define CAN1RXIDR3_ID4 _CAN1RXIDR3.Bits.ID4 +#define CAN1RXIDR3_ID5 _CAN1RXIDR3.Bits.ID5 +#define CAN1RXIDR3_ID6 _CAN1RXIDR3.Bits.ID6 +#define CAN1RXIDR3_ID _CAN1RXIDR3.MergedBits.grpID + + +/*** CAN1RXDSR0 - MSCAN 1 Receive Data Segment Register 0; 0x000001A4 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN1RXDSR0STR; +extern volatile CAN1RXDSR0STR _CAN1RXDSR0 @(REG_BASE + 0x000001A4); +#define CAN1RXDSR0 _CAN1RXDSR0.Byte +#define CAN1RXDSR0_DB0 _CAN1RXDSR0.Bits.DB0 +#define CAN1RXDSR0_DB1 _CAN1RXDSR0.Bits.DB1 +#define CAN1RXDSR0_DB2 _CAN1RXDSR0.Bits.DB2 +#define CAN1RXDSR0_DB3 _CAN1RXDSR0.Bits.DB3 +#define CAN1RXDSR0_DB4 _CAN1RXDSR0.Bits.DB4 +#define CAN1RXDSR0_DB5 _CAN1RXDSR0.Bits.DB5 +#define CAN1RXDSR0_DB6 _CAN1RXDSR0.Bits.DB6 +#define CAN1RXDSR0_DB7 _CAN1RXDSR0.Bits.DB7 +#define CAN1RXDSR0_DB _CAN1RXDSR0.MergedBits.grpDB + + +/*** CAN1RXDSR1 - MSCAN 1 Receive Data Segment Register 1; 0x000001A5 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN1RXDSR1STR; +extern volatile CAN1RXDSR1STR _CAN1RXDSR1 @(REG_BASE + 0x000001A5); +#define CAN1RXDSR1 _CAN1RXDSR1.Byte +#define CAN1RXDSR1_DB0 _CAN1RXDSR1.Bits.DB0 +#define CAN1RXDSR1_DB1 _CAN1RXDSR1.Bits.DB1 +#define CAN1RXDSR1_DB2 _CAN1RXDSR1.Bits.DB2 +#define CAN1RXDSR1_DB3 _CAN1RXDSR1.Bits.DB3 +#define CAN1RXDSR1_DB4 _CAN1RXDSR1.Bits.DB4 +#define CAN1RXDSR1_DB5 _CAN1RXDSR1.Bits.DB5 +#define CAN1RXDSR1_DB6 _CAN1RXDSR1.Bits.DB6 +#define CAN1RXDSR1_DB7 _CAN1RXDSR1.Bits.DB7 +#define CAN1RXDSR1_DB _CAN1RXDSR1.MergedBits.grpDB + + +/*** CAN1RXDSR2 - MSCAN 1 Receive Data Segment Register 2; 0x000001A6 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN1RXDSR2STR; +extern volatile CAN1RXDSR2STR _CAN1RXDSR2 @(REG_BASE + 0x000001A6); +#define CAN1RXDSR2 _CAN1RXDSR2.Byte +#define CAN1RXDSR2_DB0 _CAN1RXDSR2.Bits.DB0 +#define CAN1RXDSR2_DB1 _CAN1RXDSR2.Bits.DB1 +#define CAN1RXDSR2_DB2 _CAN1RXDSR2.Bits.DB2 +#define CAN1RXDSR2_DB3 _CAN1RXDSR2.Bits.DB3 +#define CAN1RXDSR2_DB4 _CAN1RXDSR2.Bits.DB4 +#define CAN1RXDSR2_DB5 _CAN1RXDSR2.Bits.DB5 +#define CAN1RXDSR2_DB6 _CAN1RXDSR2.Bits.DB6 +#define CAN1RXDSR2_DB7 _CAN1RXDSR2.Bits.DB7 +#define CAN1RXDSR2_DB _CAN1RXDSR2.MergedBits.grpDB + + +/*** CAN1RXDSR3 - MSCAN 1 Receive Data Segment Register 3; 0x000001A7 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN1RXDSR3STR; +extern volatile CAN1RXDSR3STR _CAN1RXDSR3 @(REG_BASE + 0x000001A7); +#define CAN1RXDSR3 _CAN1RXDSR3.Byte +#define CAN1RXDSR3_DB0 _CAN1RXDSR3.Bits.DB0 +#define CAN1RXDSR3_DB1 _CAN1RXDSR3.Bits.DB1 +#define CAN1RXDSR3_DB2 _CAN1RXDSR3.Bits.DB2 +#define CAN1RXDSR3_DB3 _CAN1RXDSR3.Bits.DB3 +#define CAN1RXDSR3_DB4 _CAN1RXDSR3.Bits.DB4 +#define CAN1RXDSR3_DB5 _CAN1RXDSR3.Bits.DB5 +#define CAN1RXDSR3_DB6 _CAN1RXDSR3.Bits.DB6 +#define CAN1RXDSR3_DB7 _CAN1RXDSR3.Bits.DB7 +#define CAN1RXDSR3_DB _CAN1RXDSR3.MergedBits.grpDB + + +/*** CAN1RXDSR4 - MSCAN 1 Receive Data Segment Register 4; 0x000001A8 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN1RXDSR4STR; +extern volatile CAN1RXDSR4STR _CAN1RXDSR4 @(REG_BASE + 0x000001A8); +#define CAN1RXDSR4 _CAN1RXDSR4.Byte +#define CAN1RXDSR4_DB0 _CAN1RXDSR4.Bits.DB0 +#define CAN1RXDSR4_DB1 _CAN1RXDSR4.Bits.DB1 +#define CAN1RXDSR4_DB2 _CAN1RXDSR4.Bits.DB2 +#define CAN1RXDSR4_DB3 _CAN1RXDSR4.Bits.DB3 +#define CAN1RXDSR4_DB4 _CAN1RXDSR4.Bits.DB4 +#define CAN1RXDSR4_DB5 _CAN1RXDSR4.Bits.DB5 +#define CAN1RXDSR4_DB6 _CAN1RXDSR4.Bits.DB6 +#define CAN1RXDSR4_DB7 _CAN1RXDSR4.Bits.DB7 +#define CAN1RXDSR4_DB _CAN1RXDSR4.MergedBits.grpDB + + +/*** CAN1RXDSR5 - MSCAN 1 Receive Data Segment Register 5; 0x000001A9 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN1RXDSR5STR; +extern volatile CAN1RXDSR5STR _CAN1RXDSR5 @(REG_BASE + 0x000001A9); +#define CAN1RXDSR5 _CAN1RXDSR5.Byte +#define CAN1RXDSR5_DB0 _CAN1RXDSR5.Bits.DB0 +#define CAN1RXDSR5_DB1 _CAN1RXDSR5.Bits.DB1 +#define CAN1RXDSR5_DB2 _CAN1RXDSR5.Bits.DB2 +#define CAN1RXDSR5_DB3 _CAN1RXDSR5.Bits.DB3 +#define CAN1RXDSR5_DB4 _CAN1RXDSR5.Bits.DB4 +#define CAN1RXDSR5_DB5 _CAN1RXDSR5.Bits.DB5 +#define CAN1RXDSR5_DB6 _CAN1RXDSR5.Bits.DB6 +#define CAN1RXDSR5_DB7 _CAN1RXDSR5.Bits.DB7 +#define CAN1RXDSR5_DB _CAN1RXDSR5.MergedBits.grpDB + + +/*** CAN1RXDSR6 - MSCAN 1 Receive Data Segment Register 6; 0x000001AA ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN1RXDSR6STR; +extern volatile CAN1RXDSR6STR _CAN1RXDSR6 @(REG_BASE + 0x000001AA); +#define CAN1RXDSR6 _CAN1RXDSR6.Byte +#define CAN1RXDSR6_DB0 _CAN1RXDSR6.Bits.DB0 +#define CAN1RXDSR6_DB1 _CAN1RXDSR6.Bits.DB1 +#define CAN1RXDSR6_DB2 _CAN1RXDSR6.Bits.DB2 +#define CAN1RXDSR6_DB3 _CAN1RXDSR6.Bits.DB3 +#define CAN1RXDSR6_DB4 _CAN1RXDSR6.Bits.DB4 +#define CAN1RXDSR6_DB5 _CAN1RXDSR6.Bits.DB5 +#define CAN1RXDSR6_DB6 _CAN1RXDSR6.Bits.DB6 +#define CAN1RXDSR6_DB7 _CAN1RXDSR6.Bits.DB7 +#define CAN1RXDSR6_DB _CAN1RXDSR6.MergedBits.grpDB + + +/*** CAN1RXDSR7 - MSCAN 1 Receive Data Segment Register 7; 0x000001AB ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN1RXDSR7STR; +extern volatile CAN1RXDSR7STR _CAN1RXDSR7 @(REG_BASE + 0x000001AB); +#define CAN1RXDSR7 _CAN1RXDSR7.Byte +#define CAN1RXDSR7_DB0 _CAN1RXDSR7.Bits.DB0 +#define CAN1RXDSR7_DB1 _CAN1RXDSR7.Bits.DB1 +#define CAN1RXDSR7_DB2 _CAN1RXDSR7.Bits.DB2 +#define CAN1RXDSR7_DB3 _CAN1RXDSR7.Bits.DB3 +#define CAN1RXDSR7_DB4 _CAN1RXDSR7.Bits.DB4 +#define CAN1RXDSR7_DB5 _CAN1RXDSR7.Bits.DB5 +#define CAN1RXDSR7_DB6 _CAN1RXDSR7.Bits.DB6 +#define CAN1RXDSR7_DB7 _CAN1RXDSR7.Bits.DB7 +#define CAN1RXDSR7_DB _CAN1RXDSR7.MergedBits.grpDB + + +/*** CAN1RXDLR - MSCAN 1 Receive Data Length Register; 0x000001AC ***/ +typedef union { + byte Byte; + struct { + byte DLC0 :1; /* Data Length Code Bit 0 */ + byte DLC1 :1; /* Data Length Code Bit 1 */ + byte DLC2 :1; /* Data Length Code Bit 2 */ + byte DLC3 :1; /* Data Length Code Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpDLC :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN1RXDLRSTR; +extern volatile CAN1RXDLRSTR _CAN1RXDLR @(REG_BASE + 0x000001AC); +#define CAN1RXDLR _CAN1RXDLR.Byte +#define CAN1RXDLR_DLC0 _CAN1RXDLR.Bits.DLC0 +#define CAN1RXDLR_DLC1 _CAN1RXDLR.Bits.DLC1 +#define CAN1RXDLR_DLC2 _CAN1RXDLR.Bits.DLC2 +#define CAN1RXDLR_DLC3 _CAN1RXDLR.Bits.DLC3 +#define CAN1RXDLR_DLC _CAN1RXDLR.MergedBits.grpDLC + + +/*** CAN1TXIDR0 - MSCAN 1 Transmit Identifier Register 0; 0x000001B0 ***/ +typedef union { + byte Byte; + struct { + byte ID21 :1; /* Extended format identifier Bit 21 */ + byte ID22 :1; /* Extended format identifier Bit 22 */ + byte ID23 :1; /* Extended format identifier Bit 23 */ + byte ID24 :1; /* Extended format identifier Bit 24 */ + byte ID25 :1; /* Extended format identifier Bit 25 */ + byte ID26 :1; /* Extended format identifier Bit 26 */ + byte ID27 :1; /* Extended format identifier Bit 27 */ + byte ID28 :1; /* Extended format identifier Bit 28 */ + } Bits; + struct { + byte grpID_21 :8; + } MergedBits; +} CAN1TXIDR0STR; +extern volatile CAN1TXIDR0STR _CAN1TXIDR0 @(REG_BASE + 0x000001B0); +#define CAN1TXIDR0 _CAN1TXIDR0.Byte +#define CAN1TXIDR0_ID21 _CAN1TXIDR0.Bits.ID21 +#define CAN1TXIDR0_ID22 _CAN1TXIDR0.Bits.ID22 +#define CAN1TXIDR0_ID23 _CAN1TXIDR0.Bits.ID23 +#define CAN1TXIDR0_ID24 _CAN1TXIDR0.Bits.ID24 +#define CAN1TXIDR0_ID25 _CAN1TXIDR0.Bits.ID25 +#define CAN1TXIDR0_ID26 _CAN1TXIDR0.Bits.ID26 +#define CAN1TXIDR0_ID27 _CAN1TXIDR0.Bits.ID27 +#define CAN1TXIDR0_ID28 _CAN1TXIDR0.Bits.ID28 +#define CAN1TXIDR0_ID_21 _CAN1TXIDR0.MergedBits.grpID_21 +#define CAN1TXIDR0_ID CAN1TXIDR0_ID_21 + + +/*** CAN1TXIDR1 - MSCAN 1 Transmit Identifier Register 1; 0x000001B1 ***/ +typedef union { + byte Byte; + struct { + byte ID15 :1; /* Extended format identifier Bit 15 */ + byte ID16 :1; /* Extended format identifier Bit 16 */ + byte ID17 :1; /* Extended format identifier Bit 17 */ + byte IDE :1; /* ID Extended */ + byte SRR :1; /* Substitute Remote Request */ + byte ID18 :1; /* Extended format identifier Bit 18 */ + byte ID19 :1; /* Extended format identifier Bit 19 */ + byte ID20 :1; /* Extended format identifier Bit 20 */ + } Bits; + struct { + byte grpID_15 :3; + byte :1; + byte :1; + byte grpID_18 :3; + } MergedBits; +} CAN1TXIDR1STR; +extern volatile CAN1TXIDR1STR _CAN1TXIDR1 @(REG_BASE + 0x000001B1); +#define CAN1TXIDR1 _CAN1TXIDR1.Byte +#define CAN1TXIDR1_ID15 _CAN1TXIDR1.Bits.ID15 +#define CAN1TXIDR1_ID16 _CAN1TXIDR1.Bits.ID16 +#define CAN1TXIDR1_ID17 _CAN1TXIDR1.Bits.ID17 +#define CAN1TXIDR1_IDE _CAN1TXIDR1.Bits.IDE +#define CAN1TXIDR1_SRR _CAN1TXIDR1.Bits.SRR +#define CAN1TXIDR1_ID18 _CAN1TXIDR1.Bits.ID18 +#define CAN1TXIDR1_ID19 _CAN1TXIDR1.Bits.ID19 +#define CAN1TXIDR1_ID20 _CAN1TXIDR1.Bits.ID20 +#define CAN1TXIDR1_ID_15 _CAN1TXIDR1.MergedBits.grpID_15 +#define CAN1TXIDR1_ID_18 _CAN1TXIDR1.MergedBits.grpID_18 +#define CAN1TXIDR1_ID CAN1TXIDR1_ID_15 + + +/*** CAN1TXIDR2 - MSCAN 1 Transmit Identifier Register 2; 0x000001B2 ***/ +typedef union { + byte Byte; + struct { + byte ID7 :1; /* Extended format identifier Bit 7 */ + byte ID8 :1; /* Extended format identifier Bit 8 */ + byte ID9 :1; /* Extended format identifier Bit 9 */ + byte ID10 :1; /* Extended format identifier Bit 10 */ + byte ID11 :1; /* Extended format identifier Bit 11 */ + byte ID12 :1; /* Extended format identifier Bit 12 */ + byte ID13 :1; /* Extended format identifier Bit 13 */ + byte ID14 :1; /* Extended format identifier Bit 14 */ + } Bits; + struct { + byte grpID_7 :8; + } MergedBits; +} CAN1TXIDR2STR; +extern volatile CAN1TXIDR2STR _CAN1TXIDR2 @(REG_BASE + 0x000001B2); +#define CAN1TXIDR2 _CAN1TXIDR2.Byte +#define CAN1TXIDR2_ID7 _CAN1TXIDR2.Bits.ID7 +#define CAN1TXIDR2_ID8 _CAN1TXIDR2.Bits.ID8 +#define CAN1TXIDR2_ID9 _CAN1TXIDR2.Bits.ID9 +#define CAN1TXIDR2_ID10 _CAN1TXIDR2.Bits.ID10 +#define CAN1TXIDR2_ID11 _CAN1TXIDR2.Bits.ID11 +#define CAN1TXIDR2_ID12 _CAN1TXIDR2.Bits.ID12 +#define CAN1TXIDR2_ID13 _CAN1TXIDR2.Bits.ID13 +#define CAN1TXIDR2_ID14 _CAN1TXIDR2.Bits.ID14 +#define CAN1TXIDR2_ID_7 _CAN1TXIDR2.MergedBits.grpID_7 +#define CAN1TXIDR2_ID CAN1TXIDR2_ID_7 + + +/*** CAN1TXIDR3 - MSCAN 1 Transmit Identifier Register 3; 0x000001B3 ***/ +typedef union { + byte Byte; + struct { + byte RTR :1; /* Remote Transmission Request */ + byte ID0 :1; /* Extended format identifier Bit 0 */ + byte ID1 :1; /* Extended format identifier Bit 1 */ + byte ID2 :1; /* Extended format identifier Bit 2 */ + byte ID3 :1; /* Extended format identifier Bit 3 */ + byte ID4 :1; /* Extended format identifier Bit 4 */ + byte ID5 :1; /* Extended format identifier Bit 5 */ + byte ID6 :1; /* Extended format identifier Bit 6 */ + } Bits; + struct { + byte :1; + byte grpID :7; + } MergedBits; +} CAN1TXIDR3STR; +extern volatile CAN1TXIDR3STR _CAN1TXIDR3 @(REG_BASE + 0x000001B3); +#define CAN1TXIDR3 _CAN1TXIDR3.Byte +#define CAN1TXIDR3_RTR _CAN1TXIDR3.Bits.RTR +#define CAN1TXIDR3_ID0 _CAN1TXIDR3.Bits.ID0 +#define CAN1TXIDR3_ID1 _CAN1TXIDR3.Bits.ID1 +#define CAN1TXIDR3_ID2 _CAN1TXIDR3.Bits.ID2 +#define CAN1TXIDR3_ID3 _CAN1TXIDR3.Bits.ID3 +#define CAN1TXIDR3_ID4 _CAN1TXIDR3.Bits.ID4 +#define CAN1TXIDR3_ID5 _CAN1TXIDR3.Bits.ID5 +#define CAN1TXIDR3_ID6 _CAN1TXIDR3.Bits.ID6 +#define CAN1TXIDR3_ID _CAN1TXIDR3.MergedBits.grpID + + +/*** CAN1TXDSR0 - MSCAN 1 Transmit Data Segment Register 0; 0x000001B4 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN1TXDSR0STR; +extern volatile CAN1TXDSR0STR _CAN1TXDSR0 @(REG_BASE + 0x000001B4); +#define CAN1TXDSR0 _CAN1TXDSR0.Byte +#define CAN1TXDSR0_DB0 _CAN1TXDSR0.Bits.DB0 +#define CAN1TXDSR0_DB1 _CAN1TXDSR0.Bits.DB1 +#define CAN1TXDSR0_DB2 _CAN1TXDSR0.Bits.DB2 +#define CAN1TXDSR0_DB3 _CAN1TXDSR0.Bits.DB3 +#define CAN1TXDSR0_DB4 _CAN1TXDSR0.Bits.DB4 +#define CAN1TXDSR0_DB5 _CAN1TXDSR0.Bits.DB5 +#define CAN1TXDSR0_DB6 _CAN1TXDSR0.Bits.DB6 +#define CAN1TXDSR0_DB7 _CAN1TXDSR0.Bits.DB7 +#define CAN1TXDSR0_DB _CAN1TXDSR0.MergedBits.grpDB + + +/*** CAN1TXDSR1 - MSCAN 1 Transmit Data Segment Register 1; 0x000001B5 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN1TXDSR1STR; +extern volatile CAN1TXDSR1STR _CAN1TXDSR1 @(REG_BASE + 0x000001B5); +#define CAN1TXDSR1 _CAN1TXDSR1.Byte +#define CAN1TXDSR1_DB0 _CAN1TXDSR1.Bits.DB0 +#define CAN1TXDSR1_DB1 _CAN1TXDSR1.Bits.DB1 +#define CAN1TXDSR1_DB2 _CAN1TXDSR1.Bits.DB2 +#define CAN1TXDSR1_DB3 _CAN1TXDSR1.Bits.DB3 +#define CAN1TXDSR1_DB4 _CAN1TXDSR1.Bits.DB4 +#define CAN1TXDSR1_DB5 _CAN1TXDSR1.Bits.DB5 +#define CAN1TXDSR1_DB6 _CAN1TXDSR1.Bits.DB6 +#define CAN1TXDSR1_DB7 _CAN1TXDSR1.Bits.DB7 +#define CAN1TXDSR1_DB _CAN1TXDSR1.MergedBits.grpDB + + +/*** CAN1TXDSR2 - MSCAN 1 Transmit Data Segment Register 2; 0x000001B6 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN1TXDSR2STR; +extern volatile CAN1TXDSR2STR _CAN1TXDSR2 @(REG_BASE + 0x000001B6); +#define CAN1TXDSR2 _CAN1TXDSR2.Byte +#define CAN1TXDSR2_DB0 _CAN1TXDSR2.Bits.DB0 +#define CAN1TXDSR2_DB1 _CAN1TXDSR2.Bits.DB1 +#define CAN1TXDSR2_DB2 _CAN1TXDSR2.Bits.DB2 +#define CAN1TXDSR2_DB3 _CAN1TXDSR2.Bits.DB3 +#define CAN1TXDSR2_DB4 _CAN1TXDSR2.Bits.DB4 +#define CAN1TXDSR2_DB5 _CAN1TXDSR2.Bits.DB5 +#define CAN1TXDSR2_DB6 _CAN1TXDSR2.Bits.DB6 +#define CAN1TXDSR2_DB7 _CAN1TXDSR2.Bits.DB7 +#define CAN1TXDSR2_DB _CAN1TXDSR2.MergedBits.grpDB + + +/*** CAN1TXDSR3 - MSCAN 1 Transmit Data Segment Register 3; 0x000001B7 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN1TXDSR3STR; +extern volatile CAN1TXDSR3STR _CAN1TXDSR3 @(REG_BASE + 0x000001B7); +#define CAN1TXDSR3 _CAN1TXDSR3.Byte +#define CAN1TXDSR3_DB0 _CAN1TXDSR3.Bits.DB0 +#define CAN1TXDSR3_DB1 _CAN1TXDSR3.Bits.DB1 +#define CAN1TXDSR3_DB2 _CAN1TXDSR3.Bits.DB2 +#define CAN1TXDSR3_DB3 _CAN1TXDSR3.Bits.DB3 +#define CAN1TXDSR3_DB4 _CAN1TXDSR3.Bits.DB4 +#define CAN1TXDSR3_DB5 _CAN1TXDSR3.Bits.DB5 +#define CAN1TXDSR3_DB6 _CAN1TXDSR3.Bits.DB6 +#define CAN1TXDSR3_DB7 _CAN1TXDSR3.Bits.DB7 +#define CAN1TXDSR3_DB _CAN1TXDSR3.MergedBits.grpDB + + +/*** CAN1TXDSR4 - MSCAN 1 Transmit Data Segment Register 4; 0x000001B8 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN1TXDSR4STR; +extern volatile CAN1TXDSR4STR _CAN1TXDSR4 @(REG_BASE + 0x000001B8); +#define CAN1TXDSR4 _CAN1TXDSR4.Byte +#define CAN1TXDSR4_DB0 _CAN1TXDSR4.Bits.DB0 +#define CAN1TXDSR4_DB1 _CAN1TXDSR4.Bits.DB1 +#define CAN1TXDSR4_DB2 _CAN1TXDSR4.Bits.DB2 +#define CAN1TXDSR4_DB3 _CAN1TXDSR4.Bits.DB3 +#define CAN1TXDSR4_DB4 _CAN1TXDSR4.Bits.DB4 +#define CAN1TXDSR4_DB5 _CAN1TXDSR4.Bits.DB5 +#define CAN1TXDSR4_DB6 _CAN1TXDSR4.Bits.DB6 +#define CAN1TXDSR4_DB7 _CAN1TXDSR4.Bits.DB7 +#define CAN1TXDSR4_DB _CAN1TXDSR4.MergedBits.grpDB + + +/*** CAN1TXDSR5 - MSCAN 1 Transmit Data Segment Register 5; 0x000001B9 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN1TXDSR5STR; +extern volatile CAN1TXDSR5STR _CAN1TXDSR5 @(REG_BASE + 0x000001B9); +#define CAN1TXDSR5 _CAN1TXDSR5.Byte +#define CAN1TXDSR5_DB0 _CAN1TXDSR5.Bits.DB0 +#define CAN1TXDSR5_DB1 _CAN1TXDSR5.Bits.DB1 +#define CAN1TXDSR5_DB2 _CAN1TXDSR5.Bits.DB2 +#define CAN1TXDSR5_DB3 _CAN1TXDSR5.Bits.DB3 +#define CAN1TXDSR5_DB4 _CAN1TXDSR5.Bits.DB4 +#define CAN1TXDSR5_DB5 _CAN1TXDSR5.Bits.DB5 +#define CAN1TXDSR5_DB6 _CAN1TXDSR5.Bits.DB6 +#define CAN1TXDSR5_DB7 _CAN1TXDSR5.Bits.DB7 +#define CAN1TXDSR5_DB _CAN1TXDSR5.MergedBits.grpDB + + +/*** CAN1TXDSR6 - MSCAN 1 Transmit Data Segment Register 6; 0x000001BA ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN1TXDSR6STR; +extern volatile CAN1TXDSR6STR _CAN1TXDSR6 @(REG_BASE + 0x000001BA); +#define CAN1TXDSR6 _CAN1TXDSR6.Byte +#define CAN1TXDSR6_DB0 _CAN1TXDSR6.Bits.DB0 +#define CAN1TXDSR6_DB1 _CAN1TXDSR6.Bits.DB1 +#define CAN1TXDSR6_DB2 _CAN1TXDSR6.Bits.DB2 +#define CAN1TXDSR6_DB3 _CAN1TXDSR6.Bits.DB3 +#define CAN1TXDSR6_DB4 _CAN1TXDSR6.Bits.DB4 +#define CAN1TXDSR6_DB5 _CAN1TXDSR6.Bits.DB5 +#define CAN1TXDSR6_DB6 _CAN1TXDSR6.Bits.DB6 +#define CAN1TXDSR6_DB7 _CAN1TXDSR6.Bits.DB7 +#define CAN1TXDSR6_DB _CAN1TXDSR6.MergedBits.grpDB + + +/*** CAN1TXDSR7 - MSCAN 1 Transmit Data Segment Register 7; 0x000001BB ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN1TXDSR7STR; +extern volatile CAN1TXDSR7STR _CAN1TXDSR7 @(REG_BASE + 0x000001BB); +#define CAN1TXDSR7 _CAN1TXDSR7.Byte +#define CAN1TXDSR7_DB0 _CAN1TXDSR7.Bits.DB0 +#define CAN1TXDSR7_DB1 _CAN1TXDSR7.Bits.DB1 +#define CAN1TXDSR7_DB2 _CAN1TXDSR7.Bits.DB2 +#define CAN1TXDSR7_DB3 _CAN1TXDSR7.Bits.DB3 +#define CAN1TXDSR7_DB4 _CAN1TXDSR7.Bits.DB4 +#define CAN1TXDSR7_DB5 _CAN1TXDSR7.Bits.DB5 +#define CAN1TXDSR7_DB6 _CAN1TXDSR7.Bits.DB6 +#define CAN1TXDSR7_DB7 _CAN1TXDSR7.Bits.DB7 +#define CAN1TXDSR7_DB _CAN1TXDSR7.MergedBits.grpDB + + +/*** CAN1TXDLR - MSCAN 1 Transmit Data Length Register; 0x000001BC ***/ +typedef union { + byte Byte; + struct { + byte DLC0 :1; /* Data Length Code Bit 0 */ + byte DLC1 :1; /* Data Length Code Bit 1 */ + byte DLC2 :1; /* Data Length Code Bit 2 */ + byte DLC3 :1; /* Data Length Code Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpDLC :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN1TXDLRSTR; +extern volatile CAN1TXDLRSTR _CAN1TXDLR @(REG_BASE + 0x000001BC); +#define CAN1TXDLR _CAN1TXDLR.Byte +#define CAN1TXDLR_DLC0 _CAN1TXDLR.Bits.DLC0 +#define CAN1TXDLR_DLC1 _CAN1TXDLR.Bits.DLC1 +#define CAN1TXDLR_DLC2 _CAN1TXDLR.Bits.DLC2 +#define CAN1TXDLR_DLC3 _CAN1TXDLR.Bits.DLC3 +#define CAN1TXDLR_DLC _CAN1TXDLR.MergedBits.grpDLC + + +/*** CAN1TXTBPR - MSCAN 1 Transmit Buffer Priority; 0x000001BF ***/ +typedef union { + byte Byte; + struct { + byte PRIO0 :1; /* Transmit Buffer Priority Bit 0 */ + byte PRIO1 :1; /* Transmit Buffer Priority Bit 1 */ + byte PRIO2 :1; /* Transmit Buffer Priority Bit 2 */ + byte PRIO3 :1; /* Transmit Buffer Priority Bit 3 */ + byte PRIO4 :1; /* Transmit Buffer Priority Bit 4 */ + byte PRIO5 :1; /* Transmit Buffer Priority Bit 5 */ + byte PRIO6 :1; /* Transmit Buffer Priority Bit 6 */ + byte PRIO7 :1; /* Transmit Buffer Priority Bit 7 */ + } Bits; + struct { + byte grpPRIO :8; + } MergedBits; +} CAN1TXTBPRSTR; +extern volatile CAN1TXTBPRSTR _CAN1TXTBPR @(REG_BASE + 0x000001BF); +#define CAN1TXTBPR _CAN1TXTBPR.Byte +#define CAN1TXTBPR_PRIO0 _CAN1TXTBPR.Bits.PRIO0 +#define CAN1TXTBPR_PRIO1 _CAN1TXTBPR.Bits.PRIO1 +#define CAN1TXTBPR_PRIO2 _CAN1TXTBPR.Bits.PRIO2 +#define CAN1TXTBPR_PRIO3 _CAN1TXTBPR.Bits.PRIO3 +#define CAN1TXTBPR_PRIO4 _CAN1TXTBPR.Bits.PRIO4 +#define CAN1TXTBPR_PRIO5 _CAN1TXTBPR.Bits.PRIO5 +#define CAN1TXTBPR_PRIO6 _CAN1TXTBPR.Bits.PRIO6 +#define CAN1TXTBPR_PRIO7 _CAN1TXTBPR.Bits.PRIO7 +#define CAN1TXTBPR_PRIO _CAN1TXTBPR.MergedBits.grpPRIO + + +/*** CAN2CTL0 - MSCAN 2 Control 0 Register; 0x000001C0 ***/ +typedef union { + byte Byte; + struct { + byte INITRQ :1; /* Initialization Mode Request */ + byte SLPRQ :1; /* Sleep Mode Request */ + byte WUPE :1; /* Wake-Up Enable */ + byte TIME :1; /* Timer Enable */ + byte SYNCH :1; /* Synchronized Status */ + byte CSWAI :1; /* CAN Stops in Wait Mode */ + byte RXACT :1; /* Receiver Active Status */ + byte RXFRM :1; /* Received Frame Flag */ + } Bits; +} CAN2CTL0STR; +extern volatile CAN2CTL0STR _CAN2CTL0 @(REG_BASE + 0x000001C0); +#define CAN2CTL0 _CAN2CTL0.Byte +#define CAN2CTL0_INITRQ _CAN2CTL0.Bits.INITRQ +#define CAN2CTL0_SLPRQ _CAN2CTL0.Bits.SLPRQ +#define CAN2CTL0_WUPE _CAN2CTL0.Bits.WUPE +#define CAN2CTL0_TIME _CAN2CTL0.Bits.TIME +#define CAN2CTL0_SYNCH _CAN2CTL0.Bits.SYNCH +#define CAN2CTL0_CSWAI _CAN2CTL0.Bits.CSWAI +#define CAN2CTL0_RXACT _CAN2CTL0.Bits.RXACT +#define CAN2CTL0_RXFRM _CAN2CTL0.Bits.RXFRM + + +/*** CAN2CTL1 - MSCAN 2 Control 1 Register; 0x000001C1 ***/ +typedef union { + byte Byte; + struct { + byte INITAK :1; /* Initialization Mode Acknowledge */ + byte SLPAK :1; /* Sleep Mode Acknowledge */ + byte WUPM :1; /* Wake-Up Mode */ + byte :1; + byte LISTEN :1; /* Listen Only Mode */ + byte LOOPB :1; /* Loop Back Self Test Mode */ + byte CLKSRC :1; /* MSCAN 2 Clock Source */ + byte CANE :1; /* MSCAN 2 Enable */ + } Bits; +} CAN2CTL1STR; +extern volatile CAN2CTL1STR _CAN2CTL1 @(REG_BASE + 0x000001C1); +#define CAN2CTL1 _CAN2CTL1.Byte +#define CAN2CTL1_INITAK _CAN2CTL1.Bits.INITAK +#define CAN2CTL1_SLPAK _CAN2CTL1.Bits.SLPAK +#define CAN2CTL1_WUPM _CAN2CTL1.Bits.WUPM +#define CAN2CTL1_LISTEN _CAN2CTL1.Bits.LISTEN +#define CAN2CTL1_LOOPB _CAN2CTL1.Bits.LOOPB +#define CAN2CTL1_CLKSRC _CAN2CTL1.Bits.CLKSRC +#define CAN2CTL1_CANE _CAN2CTL1.Bits.CANE + + +/*** CAN2BTR0 - MSCAN 2 Bus Timing Register 0; 0x000001C2 ***/ +typedef union { + byte Byte; + struct { + byte BRP0 :1; /* Baud Rate Prescaler 0 */ + byte BRP1 :1; /* Baud Rate Prescaler 1 */ + byte BRP2 :1; /* Baud Rate Prescaler 2 */ + byte BRP3 :1; /* Baud Rate Prescaler 3 */ + byte BRP4 :1; /* Baud Rate Prescaler 4 */ + byte BRP5 :1; /* Baud Rate Prescaler 5 */ + byte SJW0 :1; /* Synchronization Jump Width 0 */ + byte SJW1 :1; /* Synchronization Jump Width 1 */ + } Bits; + struct { + byte grpBRP :6; + byte grpSJW :2; + } MergedBits; +} CAN2BTR0STR; +extern volatile CAN2BTR0STR _CAN2BTR0 @(REG_BASE + 0x000001C2); +#define CAN2BTR0 _CAN2BTR0.Byte +#define CAN2BTR0_BRP0 _CAN2BTR0.Bits.BRP0 +#define CAN2BTR0_BRP1 _CAN2BTR0.Bits.BRP1 +#define CAN2BTR0_BRP2 _CAN2BTR0.Bits.BRP2 +#define CAN2BTR0_BRP3 _CAN2BTR0.Bits.BRP3 +#define CAN2BTR0_BRP4 _CAN2BTR0.Bits.BRP4 +#define CAN2BTR0_BRP5 _CAN2BTR0.Bits.BRP5 +#define CAN2BTR0_SJW0 _CAN2BTR0.Bits.SJW0 +#define CAN2BTR0_SJW1 _CAN2BTR0.Bits.SJW1 +#define CAN2BTR0_BRP _CAN2BTR0.MergedBits.grpBRP +#define CAN2BTR0_SJW _CAN2BTR0.MergedBits.grpSJW + + +/*** CAN2BTR1 - MSCAN 2 Bus Timing Register 1; 0x000001C3 ***/ +typedef union { + byte Byte; + struct { + byte TSEG10 :1; /* Time Segment 1 */ + byte TSEG11 :1; /* Time Segment 1 */ + byte TSEG12 :1; /* Time Segment 1 */ + byte TSEG13 :1; /* Time Segment 1 */ + byte TSEG20 :1; /* Time Segment 2 */ + byte TSEG21 :1; /* Time Segment 2 */ + byte TSEG22 :1; /* Time Segment 2 */ + byte SAMP :1; /* Sampling */ + } Bits; + struct { + byte grpTSEG_10 :4; + byte grpTSEG_20 :3; + byte :1; + } MergedBits; +} CAN2BTR1STR; +extern volatile CAN2BTR1STR _CAN2BTR1 @(REG_BASE + 0x000001C3); +#define CAN2BTR1 _CAN2BTR1.Byte +#define CAN2BTR1_TSEG10 _CAN2BTR1.Bits.TSEG10 +#define CAN2BTR1_TSEG11 _CAN2BTR1.Bits.TSEG11 +#define CAN2BTR1_TSEG12 _CAN2BTR1.Bits.TSEG12 +#define CAN2BTR1_TSEG13 _CAN2BTR1.Bits.TSEG13 +#define CAN2BTR1_TSEG20 _CAN2BTR1.Bits.TSEG20 +#define CAN2BTR1_TSEG21 _CAN2BTR1.Bits.TSEG21 +#define CAN2BTR1_TSEG22 _CAN2BTR1.Bits.TSEG22 +#define CAN2BTR1_SAMP _CAN2BTR1.Bits.SAMP +#define CAN2BTR1_TSEG_10 _CAN2BTR1.MergedBits.grpTSEG_10 +#define CAN2BTR1_TSEG_20 _CAN2BTR1.MergedBits.grpTSEG_20 +#define CAN2BTR1_TSEG CAN2BTR1_TSEG_10 + + +/*** CAN2RFLG - MSCAN 2 Receiver Flag Register; 0x000001C4 ***/ +typedef union { + byte Byte; + struct { + byte RXF :1; /* Receive Buffer Full */ + byte OVRIF :1; /* Overrun Interrupt Flag */ + byte TSTAT0 :1; /* Transmitter Status Bit 0 */ + byte TSTAT1 :1; /* Transmitter Status Bit 1 */ + byte RSTAT0 :1; /* Receiver Status Bit 0 */ + byte RSTAT1 :1; /* Receiver Status Bit 1 */ + byte CSCIF :1; /* CAN Status Change Interrupt Flag */ + byte WUPIF :1; /* Wake-up Interrupt Flag */ + } Bits; + struct { + byte :1; + byte :1; + byte grpTSTAT :2; + byte grpRSTAT :2; + byte :1; + byte :1; + } MergedBits; +} CAN2RFLGSTR; +extern volatile CAN2RFLGSTR _CAN2RFLG @(REG_BASE + 0x000001C4); +#define CAN2RFLG _CAN2RFLG.Byte +#define CAN2RFLG_RXF _CAN2RFLG.Bits.RXF +#define CAN2RFLG_OVRIF _CAN2RFLG.Bits.OVRIF +#define CAN2RFLG_TSTAT0 _CAN2RFLG.Bits.TSTAT0 +#define CAN2RFLG_TSTAT1 _CAN2RFLG.Bits.TSTAT1 +#define CAN2RFLG_RSTAT0 _CAN2RFLG.Bits.RSTAT0 +#define CAN2RFLG_RSTAT1 _CAN2RFLG.Bits.RSTAT1 +#define CAN2RFLG_CSCIF _CAN2RFLG.Bits.CSCIF +#define CAN2RFLG_WUPIF _CAN2RFLG.Bits.WUPIF +#define CAN2RFLG_TSTAT _CAN2RFLG.MergedBits.grpTSTAT +#define CAN2RFLG_RSTAT _CAN2RFLG.MergedBits.grpRSTAT + + +/*** CAN2RIER - MSCAN 2 Receiver Interrupt Enable Register; 0x000001C5 ***/ +typedef union { + byte Byte; + struct { + byte RXFIE :1; /* Receiver Full Interrupt Enable */ + byte OVRIE :1; /* Overrun Interrupt Enable */ + byte TSTATE0 :1; /* Transmitter Status Change Enable 0 */ + byte TSTATE1 :1; /* Transmitter Status Change Enable 1 */ + byte RSTATE0 :1; /* Receiver Status Change Enable 0 */ + byte RSTATE1 :1; /* Receiver Status Change Enable 1 */ + byte CSCIE :1; /* CAN Status Change Interrupt Enable */ + byte WUPIE :1; /* Wake-up Interrupt Enable */ + } Bits; + struct { + byte :1; + byte :1; + byte grpTSTATE :2; + byte grpRSTATE :2; + byte :1; + byte :1; + } MergedBits; +} CAN2RIERSTR; +extern volatile CAN2RIERSTR _CAN2RIER @(REG_BASE + 0x000001C5); +#define CAN2RIER _CAN2RIER.Byte +#define CAN2RIER_RXFIE _CAN2RIER.Bits.RXFIE +#define CAN2RIER_OVRIE _CAN2RIER.Bits.OVRIE +#define CAN2RIER_TSTATE0 _CAN2RIER.Bits.TSTATE0 +#define CAN2RIER_TSTATE1 _CAN2RIER.Bits.TSTATE1 +#define CAN2RIER_RSTATE0 _CAN2RIER.Bits.RSTATE0 +#define CAN2RIER_RSTATE1 _CAN2RIER.Bits.RSTATE1 +#define CAN2RIER_CSCIE _CAN2RIER.Bits.CSCIE +#define CAN2RIER_WUPIE _CAN2RIER.Bits.WUPIE +#define CAN2RIER_TSTATE _CAN2RIER.MergedBits.grpTSTATE +#define CAN2RIER_RSTATE _CAN2RIER.MergedBits.grpRSTATE + + +/*** CAN2TFLG - MSCAN 2 Transmitter Flag Register; 0x000001C6 ***/ +typedef union { + byte Byte; + struct { + byte TXE0 :1; /* Transmitter Buffer Empty 0 */ + byte TXE1 :1; /* Transmitter Buffer Empty 1 */ + byte TXE2 :1; /* Transmitter Buffer Empty 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpTXE :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN2TFLGSTR; +extern volatile CAN2TFLGSTR _CAN2TFLG @(REG_BASE + 0x000001C6); +#define CAN2TFLG _CAN2TFLG.Byte +#define CAN2TFLG_TXE0 _CAN2TFLG.Bits.TXE0 +#define CAN2TFLG_TXE1 _CAN2TFLG.Bits.TXE1 +#define CAN2TFLG_TXE2 _CAN2TFLG.Bits.TXE2 +#define CAN2TFLG_TXE _CAN2TFLG.MergedBits.grpTXE + + +/*** CAN2TIER - MSCAN 2 Transmitter Interrupt Enable Register; 0x000001C7 ***/ +typedef union { + byte Byte; + struct { + byte TXEIE0 :1; /* Transmitter Empty Interrupt Enable 0 */ + byte TXEIE1 :1; /* Transmitter Empty Interrupt Enable 1 */ + byte TXEIE2 :1; /* Transmitter Empty Interrupt Enable 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpTXEIE :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN2TIERSTR; +extern volatile CAN2TIERSTR _CAN2TIER @(REG_BASE + 0x000001C7); +#define CAN2TIER _CAN2TIER.Byte +#define CAN2TIER_TXEIE0 _CAN2TIER.Bits.TXEIE0 +#define CAN2TIER_TXEIE1 _CAN2TIER.Bits.TXEIE1 +#define CAN2TIER_TXEIE2 _CAN2TIER.Bits.TXEIE2 +#define CAN2TIER_TXEIE _CAN2TIER.MergedBits.grpTXEIE + + +/*** CAN2TARQ - MSCAN 2 Transmitter Message Abort Request; 0x000001C8 ***/ +typedef union { + byte Byte; + struct { + byte ABTRQ0 :1; /* Abort Request 0 */ + byte ABTRQ1 :1; /* Abort Request 1 */ + byte ABTRQ2 :1; /* Abort Request 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpABTRQ :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN2TARQSTR; +extern volatile CAN2TARQSTR _CAN2TARQ @(REG_BASE + 0x000001C8); +#define CAN2TARQ _CAN2TARQ.Byte +#define CAN2TARQ_ABTRQ0 _CAN2TARQ.Bits.ABTRQ0 +#define CAN2TARQ_ABTRQ1 _CAN2TARQ.Bits.ABTRQ1 +#define CAN2TARQ_ABTRQ2 _CAN2TARQ.Bits.ABTRQ2 +#define CAN2TARQ_ABTRQ _CAN2TARQ.MergedBits.grpABTRQ + + +/*** CAN2TAAK - MSCAN 2 Transmitter Message Abort Control; 0x000001C9 ***/ +typedef union { + byte Byte; + struct { + byte ABTAK0 :1; /* Abort Acknowledge 0 */ + byte ABTAK1 :1; /* Abort Acknowledge 1 */ + byte ABTAK2 :1; /* Abort Acknowledge 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpABTAK :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN2TAAKSTR; +extern volatile CAN2TAAKSTR _CAN2TAAK @(REG_BASE + 0x000001C9); +#define CAN2TAAK _CAN2TAAK.Byte +#define CAN2TAAK_ABTAK0 _CAN2TAAK.Bits.ABTAK0 +#define CAN2TAAK_ABTAK1 _CAN2TAAK.Bits.ABTAK1 +#define CAN2TAAK_ABTAK2 _CAN2TAAK.Bits.ABTAK2 +#define CAN2TAAK_ABTAK _CAN2TAAK.MergedBits.grpABTAK + + +/*** CAN2TBSEL - MSCAN 2 Transmit Buffer Selection; 0x000001CA ***/ +typedef union { + byte Byte; + struct { + byte TX0 :1; /* Transmit Buffer Select 0 */ + byte TX1 :1; /* Transmit Buffer Select 1 */ + byte TX2 :1; /* Transmit Buffer Select 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpTX :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN2TBSELSTR; +extern volatile CAN2TBSELSTR _CAN2TBSEL @(REG_BASE + 0x000001CA); +#define CAN2TBSEL _CAN2TBSEL.Byte +#define CAN2TBSEL_TX0 _CAN2TBSEL.Bits.TX0 +#define CAN2TBSEL_TX1 _CAN2TBSEL.Bits.TX1 +#define CAN2TBSEL_TX2 _CAN2TBSEL.Bits.TX2 +#define CAN2TBSEL_TX _CAN2TBSEL.MergedBits.grpTX + + +/*** CAN2IDAC - MSCAN 2 Identifier Acceptance Control Register; 0x000001CB ***/ +typedef union { + byte Byte; + struct { + byte IDHIT0 :1; /* Identifier Acceptance Hit Indicator 0 */ + byte IDHIT1 :1; /* Identifier Acceptance Hit Indicator 1 */ + byte IDHIT2 :1; /* Identifier Acceptance Hit Indicator 2 */ + byte :1; + byte IDAM0 :1; /* Identifier Acceptance Mode 0 */ + byte IDAM1 :1; /* Identifier Acceptance Mode 1 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpIDHIT :3; + byte :1; + byte grpIDAM :2; + byte :1; + byte :1; + } MergedBits; +} CAN2IDACSTR; +extern volatile CAN2IDACSTR _CAN2IDAC @(REG_BASE + 0x000001CB); +#define CAN2IDAC _CAN2IDAC.Byte +#define CAN2IDAC_IDHIT0 _CAN2IDAC.Bits.IDHIT0 +#define CAN2IDAC_IDHIT1 _CAN2IDAC.Bits.IDHIT1 +#define CAN2IDAC_IDHIT2 _CAN2IDAC.Bits.IDHIT2 +#define CAN2IDAC_IDAM0 _CAN2IDAC.Bits.IDAM0 +#define CAN2IDAC_IDAM1 _CAN2IDAC.Bits.IDAM1 +#define CAN2IDAC_IDHIT _CAN2IDAC.MergedBits.grpIDHIT +#define CAN2IDAC_IDAM _CAN2IDAC.MergedBits.grpIDAM + + +/*** CAN2RXERR - MSCAN 2 Receive Error Counter Register; 0x000001CE ***/ +typedef union { + byte Byte; + struct { + byte RXERR0 :1; /* Bit 0 */ + byte RXERR1 :1; /* Bit 1 */ + byte RXERR2 :1; /* Bit 2 */ + byte RXERR3 :1; /* Bit 3 */ + byte RXERR4 :1; /* Bit 4 */ + byte RXERR5 :1; /* Bit 5 */ + byte RXERR6 :1; /* Bit 6 */ + byte RXERR7 :1; /* Bit 7 */ + } Bits; + struct { + byte grpRXERR :8; + } MergedBits; +} CAN2RXERRSTR; +extern volatile CAN2RXERRSTR _CAN2RXERR @(REG_BASE + 0x000001CE); +#define CAN2RXERR _CAN2RXERR.Byte +#define CAN2RXERR_RXERR0 _CAN2RXERR.Bits.RXERR0 +#define CAN2RXERR_RXERR1 _CAN2RXERR.Bits.RXERR1 +#define CAN2RXERR_RXERR2 _CAN2RXERR.Bits.RXERR2 +#define CAN2RXERR_RXERR3 _CAN2RXERR.Bits.RXERR3 +#define CAN2RXERR_RXERR4 _CAN2RXERR.Bits.RXERR4 +#define CAN2RXERR_RXERR5 _CAN2RXERR.Bits.RXERR5 +#define CAN2RXERR_RXERR6 _CAN2RXERR.Bits.RXERR6 +#define CAN2RXERR_RXERR7 _CAN2RXERR.Bits.RXERR7 +#define CAN2RXERR_RXERR _CAN2RXERR.MergedBits.grpRXERR + + +/*** CAN2TXERR - MSCAN 2 Transmit Error Counter Register; 0x000001CF ***/ +typedef union { + byte Byte; + struct { + byte TXERR0 :1; /* Bit 0 */ + byte TXERR1 :1; /* Bit 1 */ + byte TXERR2 :1; /* Bit 2 */ + byte TXERR3 :1; /* Bit 3 */ + byte TXERR4 :1; /* Bit 4 */ + byte TXERR5 :1; /* Bit 5 */ + byte TXERR6 :1; /* Bit 6 */ + byte TXERR7 :1; /* Bit 7 */ + } Bits; + struct { + byte grpTXERR :8; + } MergedBits; +} CAN2TXERRSTR; +extern volatile CAN2TXERRSTR _CAN2TXERR @(REG_BASE + 0x000001CF); +#define CAN2TXERR _CAN2TXERR.Byte +#define CAN2TXERR_TXERR0 _CAN2TXERR.Bits.TXERR0 +#define CAN2TXERR_TXERR1 _CAN2TXERR.Bits.TXERR1 +#define CAN2TXERR_TXERR2 _CAN2TXERR.Bits.TXERR2 +#define CAN2TXERR_TXERR3 _CAN2TXERR.Bits.TXERR3 +#define CAN2TXERR_TXERR4 _CAN2TXERR.Bits.TXERR4 +#define CAN2TXERR_TXERR5 _CAN2TXERR.Bits.TXERR5 +#define CAN2TXERR_TXERR6 _CAN2TXERR.Bits.TXERR6 +#define CAN2TXERR_TXERR7 _CAN2TXERR.Bits.TXERR7 +#define CAN2TXERR_TXERR _CAN2TXERR.MergedBits.grpTXERR + + +/*** CAN2IDAR0 - MSCAN 2 Identifier Acceptance Register 0; 0x000001D0 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN2IDAR0STR; +extern volatile CAN2IDAR0STR _CAN2IDAR0 @(REG_BASE + 0x000001D0); +#define CAN2IDAR0 _CAN2IDAR0.Byte +#define CAN2IDAR0_AC0 _CAN2IDAR0.Bits.AC0 +#define CAN2IDAR0_AC1 _CAN2IDAR0.Bits.AC1 +#define CAN2IDAR0_AC2 _CAN2IDAR0.Bits.AC2 +#define CAN2IDAR0_AC3 _CAN2IDAR0.Bits.AC3 +#define CAN2IDAR0_AC4 _CAN2IDAR0.Bits.AC4 +#define CAN2IDAR0_AC5 _CAN2IDAR0.Bits.AC5 +#define CAN2IDAR0_AC6 _CAN2IDAR0.Bits.AC6 +#define CAN2IDAR0_AC7 _CAN2IDAR0.Bits.AC7 +#define CAN2IDAR0_AC _CAN2IDAR0.MergedBits.grpAC + + +/*** CAN2IDAR1 - MSCAN 2 Identifier Acceptance Register 1; 0x000001D1 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN2IDAR1STR; +extern volatile CAN2IDAR1STR _CAN2IDAR1 @(REG_BASE + 0x000001D1); +#define CAN2IDAR1 _CAN2IDAR1.Byte +#define CAN2IDAR1_AC0 _CAN2IDAR1.Bits.AC0 +#define CAN2IDAR1_AC1 _CAN2IDAR1.Bits.AC1 +#define CAN2IDAR1_AC2 _CAN2IDAR1.Bits.AC2 +#define CAN2IDAR1_AC3 _CAN2IDAR1.Bits.AC3 +#define CAN2IDAR1_AC4 _CAN2IDAR1.Bits.AC4 +#define CAN2IDAR1_AC5 _CAN2IDAR1.Bits.AC5 +#define CAN2IDAR1_AC6 _CAN2IDAR1.Bits.AC6 +#define CAN2IDAR1_AC7 _CAN2IDAR1.Bits.AC7 +#define CAN2IDAR1_AC _CAN2IDAR1.MergedBits.grpAC + + +/*** CAN2IDAR2 - MSCAN 2 Identifier Acceptance Register 2; 0x000001D2 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN2IDAR2STR; +extern volatile CAN2IDAR2STR _CAN2IDAR2 @(REG_BASE + 0x000001D2); +#define CAN2IDAR2 _CAN2IDAR2.Byte +#define CAN2IDAR2_AC0 _CAN2IDAR2.Bits.AC0 +#define CAN2IDAR2_AC1 _CAN2IDAR2.Bits.AC1 +#define CAN2IDAR2_AC2 _CAN2IDAR2.Bits.AC2 +#define CAN2IDAR2_AC3 _CAN2IDAR2.Bits.AC3 +#define CAN2IDAR2_AC4 _CAN2IDAR2.Bits.AC4 +#define CAN2IDAR2_AC5 _CAN2IDAR2.Bits.AC5 +#define CAN2IDAR2_AC6 _CAN2IDAR2.Bits.AC6 +#define CAN2IDAR2_AC7 _CAN2IDAR2.Bits.AC7 +#define CAN2IDAR2_AC _CAN2IDAR2.MergedBits.grpAC + + +/*** CAN2IDAR3 - MSCAN 2 Identifier Acceptance Register 3; 0x000001D3 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN2IDAR3STR; +extern volatile CAN2IDAR3STR _CAN2IDAR3 @(REG_BASE + 0x000001D3); +#define CAN2IDAR3 _CAN2IDAR3.Byte +#define CAN2IDAR3_AC0 _CAN2IDAR3.Bits.AC0 +#define CAN2IDAR3_AC1 _CAN2IDAR3.Bits.AC1 +#define CAN2IDAR3_AC2 _CAN2IDAR3.Bits.AC2 +#define CAN2IDAR3_AC3 _CAN2IDAR3.Bits.AC3 +#define CAN2IDAR3_AC4 _CAN2IDAR3.Bits.AC4 +#define CAN2IDAR3_AC5 _CAN2IDAR3.Bits.AC5 +#define CAN2IDAR3_AC6 _CAN2IDAR3.Bits.AC6 +#define CAN2IDAR3_AC7 _CAN2IDAR3.Bits.AC7 +#define CAN2IDAR3_AC _CAN2IDAR3.MergedBits.grpAC + + +/*** CAN2IDMR0 - MSCAN 2 Identifier Mask Register 0; 0x000001D4 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN2IDMR0STR; +extern volatile CAN2IDMR0STR _CAN2IDMR0 @(REG_BASE + 0x000001D4); +#define CAN2IDMR0 _CAN2IDMR0.Byte +#define CAN2IDMR0_AM0 _CAN2IDMR0.Bits.AM0 +#define CAN2IDMR0_AM1 _CAN2IDMR0.Bits.AM1 +#define CAN2IDMR0_AM2 _CAN2IDMR0.Bits.AM2 +#define CAN2IDMR0_AM3 _CAN2IDMR0.Bits.AM3 +#define CAN2IDMR0_AM4 _CAN2IDMR0.Bits.AM4 +#define CAN2IDMR0_AM5 _CAN2IDMR0.Bits.AM5 +#define CAN2IDMR0_AM6 _CAN2IDMR0.Bits.AM6 +#define CAN2IDMR0_AM7 _CAN2IDMR0.Bits.AM7 +#define CAN2IDMR0_AM _CAN2IDMR0.MergedBits.grpAM + + +/*** CAN2IDMR1 - MSCAN 2 Identifier Mask Register 1; 0x000001D5 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN2IDMR1STR; +extern volatile CAN2IDMR1STR _CAN2IDMR1 @(REG_BASE + 0x000001D5); +#define CAN2IDMR1 _CAN2IDMR1.Byte +#define CAN2IDMR1_AM0 _CAN2IDMR1.Bits.AM0 +#define CAN2IDMR1_AM1 _CAN2IDMR1.Bits.AM1 +#define CAN2IDMR1_AM2 _CAN2IDMR1.Bits.AM2 +#define CAN2IDMR1_AM3 _CAN2IDMR1.Bits.AM3 +#define CAN2IDMR1_AM4 _CAN2IDMR1.Bits.AM4 +#define CAN2IDMR1_AM5 _CAN2IDMR1.Bits.AM5 +#define CAN2IDMR1_AM6 _CAN2IDMR1.Bits.AM6 +#define CAN2IDMR1_AM7 _CAN2IDMR1.Bits.AM7 +#define CAN2IDMR1_AM _CAN2IDMR1.MergedBits.grpAM + + +/*** CAN2IDMR2 - MSCAN 2 Identifier Mask Register 2; 0x000001D6 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN2IDMR2STR; +extern volatile CAN2IDMR2STR _CAN2IDMR2 @(REG_BASE + 0x000001D6); +#define CAN2IDMR2 _CAN2IDMR2.Byte +#define CAN2IDMR2_AM0 _CAN2IDMR2.Bits.AM0 +#define CAN2IDMR2_AM1 _CAN2IDMR2.Bits.AM1 +#define CAN2IDMR2_AM2 _CAN2IDMR2.Bits.AM2 +#define CAN2IDMR2_AM3 _CAN2IDMR2.Bits.AM3 +#define CAN2IDMR2_AM4 _CAN2IDMR2.Bits.AM4 +#define CAN2IDMR2_AM5 _CAN2IDMR2.Bits.AM5 +#define CAN2IDMR2_AM6 _CAN2IDMR2.Bits.AM6 +#define CAN2IDMR2_AM7 _CAN2IDMR2.Bits.AM7 +#define CAN2IDMR2_AM _CAN2IDMR2.MergedBits.grpAM + + +/*** CAN2IDMR3 - MSCAN 2 Identifier Mask Register 3; 0x000001D7 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN2IDMR3STR; +extern volatile CAN2IDMR3STR _CAN2IDMR3 @(REG_BASE + 0x000001D7); +#define CAN2IDMR3 _CAN2IDMR3.Byte +#define CAN2IDMR3_AM0 _CAN2IDMR3.Bits.AM0 +#define CAN2IDMR3_AM1 _CAN2IDMR3.Bits.AM1 +#define CAN2IDMR3_AM2 _CAN2IDMR3.Bits.AM2 +#define CAN2IDMR3_AM3 _CAN2IDMR3.Bits.AM3 +#define CAN2IDMR3_AM4 _CAN2IDMR3.Bits.AM4 +#define CAN2IDMR3_AM5 _CAN2IDMR3.Bits.AM5 +#define CAN2IDMR3_AM6 _CAN2IDMR3.Bits.AM6 +#define CAN2IDMR3_AM7 _CAN2IDMR3.Bits.AM7 +#define CAN2IDMR3_AM _CAN2IDMR3.MergedBits.grpAM + + +/*** CAN2IDAR4 - MSCAN 2 Identifier Acceptance Register 4; 0x000001D8 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN2IDAR4STR; +extern volatile CAN2IDAR4STR _CAN2IDAR4 @(REG_BASE + 0x000001D8); +#define CAN2IDAR4 _CAN2IDAR4.Byte +#define CAN2IDAR4_AC0 _CAN2IDAR4.Bits.AC0 +#define CAN2IDAR4_AC1 _CAN2IDAR4.Bits.AC1 +#define CAN2IDAR4_AC2 _CAN2IDAR4.Bits.AC2 +#define CAN2IDAR4_AC3 _CAN2IDAR4.Bits.AC3 +#define CAN2IDAR4_AC4 _CAN2IDAR4.Bits.AC4 +#define CAN2IDAR4_AC5 _CAN2IDAR4.Bits.AC5 +#define CAN2IDAR4_AC6 _CAN2IDAR4.Bits.AC6 +#define CAN2IDAR4_AC7 _CAN2IDAR4.Bits.AC7 +#define CAN2IDAR4_AC _CAN2IDAR4.MergedBits.grpAC + + +/*** CAN2IDAR5 - MSCAN 2 Identifier Acceptance Register 5; 0x000001D9 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN2IDAR5STR; +extern volatile CAN2IDAR5STR _CAN2IDAR5 @(REG_BASE + 0x000001D9); +#define CAN2IDAR5 _CAN2IDAR5.Byte +#define CAN2IDAR5_AC0 _CAN2IDAR5.Bits.AC0 +#define CAN2IDAR5_AC1 _CAN2IDAR5.Bits.AC1 +#define CAN2IDAR5_AC2 _CAN2IDAR5.Bits.AC2 +#define CAN2IDAR5_AC3 _CAN2IDAR5.Bits.AC3 +#define CAN2IDAR5_AC4 _CAN2IDAR5.Bits.AC4 +#define CAN2IDAR5_AC5 _CAN2IDAR5.Bits.AC5 +#define CAN2IDAR5_AC6 _CAN2IDAR5.Bits.AC6 +#define CAN2IDAR5_AC7 _CAN2IDAR5.Bits.AC7 +#define CAN2IDAR5_AC _CAN2IDAR5.MergedBits.grpAC + + +/*** CAN2IDAR6 - MSCAN 2 Identifier Acceptance Register 6; 0x000001DA ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN2IDAR6STR; +extern volatile CAN2IDAR6STR _CAN2IDAR6 @(REG_BASE + 0x000001DA); +#define CAN2IDAR6 _CAN2IDAR6.Byte +#define CAN2IDAR6_AC0 _CAN2IDAR6.Bits.AC0 +#define CAN2IDAR6_AC1 _CAN2IDAR6.Bits.AC1 +#define CAN2IDAR6_AC2 _CAN2IDAR6.Bits.AC2 +#define CAN2IDAR6_AC3 _CAN2IDAR6.Bits.AC3 +#define CAN2IDAR6_AC4 _CAN2IDAR6.Bits.AC4 +#define CAN2IDAR6_AC5 _CAN2IDAR6.Bits.AC5 +#define CAN2IDAR6_AC6 _CAN2IDAR6.Bits.AC6 +#define CAN2IDAR6_AC7 _CAN2IDAR6.Bits.AC7 +#define CAN2IDAR6_AC _CAN2IDAR6.MergedBits.grpAC + + +/*** CAN2IDAR7 - MSCAN 2 Identifier Acceptance Register 7; 0x000001DB ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN2IDAR7STR; +extern volatile CAN2IDAR7STR _CAN2IDAR7 @(REG_BASE + 0x000001DB); +#define CAN2IDAR7 _CAN2IDAR7.Byte +#define CAN2IDAR7_AC0 _CAN2IDAR7.Bits.AC0 +#define CAN2IDAR7_AC1 _CAN2IDAR7.Bits.AC1 +#define CAN2IDAR7_AC2 _CAN2IDAR7.Bits.AC2 +#define CAN2IDAR7_AC3 _CAN2IDAR7.Bits.AC3 +#define CAN2IDAR7_AC4 _CAN2IDAR7.Bits.AC4 +#define CAN2IDAR7_AC5 _CAN2IDAR7.Bits.AC5 +#define CAN2IDAR7_AC6 _CAN2IDAR7.Bits.AC6 +#define CAN2IDAR7_AC7 _CAN2IDAR7.Bits.AC7 +#define CAN2IDAR7_AC _CAN2IDAR7.MergedBits.grpAC + + +/*** CAN2IDMR4 - MSCAN 2 Identifier Mask Register 4; 0x000001DC ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN2IDMR4STR; +extern volatile CAN2IDMR4STR _CAN2IDMR4 @(REG_BASE + 0x000001DC); +#define CAN2IDMR4 _CAN2IDMR4.Byte +#define CAN2IDMR4_AM0 _CAN2IDMR4.Bits.AM0 +#define CAN2IDMR4_AM1 _CAN2IDMR4.Bits.AM1 +#define CAN2IDMR4_AM2 _CAN2IDMR4.Bits.AM2 +#define CAN2IDMR4_AM3 _CAN2IDMR4.Bits.AM3 +#define CAN2IDMR4_AM4 _CAN2IDMR4.Bits.AM4 +#define CAN2IDMR4_AM5 _CAN2IDMR4.Bits.AM5 +#define CAN2IDMR4_AM6 _CAN2IDMR4.Bits.AM6 +#define CAN2IDMR4_AM7 _CAN2IDMR4.Bits.AM7 +#define CAN2IDMR4_AM _CAN2IDMR4.MergedBits.grpAM + + +/*** CAN2IDMR5 - MSCAN 2 Identifier Mask Register 5; 0x000001DD ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN2IDMR5STR; +extern volatile CAN2IDMR5STR _CAN2IDMR5 @(REG_BASE + 0x000001DD); +#define CAN2IDMR5 _CAN2IDMR5.Byte +#define CAN2IDMR5_AM0 _CAN2IDMR5.Bits.AM0 +#define CAN2IDMR5_AM1 _CAN2IDMR5.Bits.AM1 +#define CAN2IDMR5_AM2 _CAN2IDMR5.Bits.AM2 +#define CAN2IDMR5_AM3 _CAN2IDMR5.Bits.AM3 +#define CAN2IDMR5_AM4 _CAN2IDMR5.Bits.AM4 +#define CAN2IDMR5_AM5 _CAN2IDMR5.Bits.AM5 +#define CAN2IDMR5_AM6 _CAN2IDMR5.Bits.AM6 +#define CAN2IDMR5_AM7 _CAN2IDMR5.Bits.AM7 +#define CAN2IDMR5_AM _CAN2IDMR5.MergedBits.grpAM + + +/*** CAN2IDMR6 - MSCAN 2 Identifier Mask Register 6; 0x000001DE ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN2IDMR6STR; +extern volatile CAN2IDMR6STR _CAN2IDMR6 @(REG_BASE + 0x000001DE); +#define CAN2IDMR6 _CAN2IDMR6.Byte +#define CAN2IDMR6_AM0 _CAN2IDMR6.Bits.AM0 +#define CAN2IDMR6_AM1 _CAN2IDMR6.Bits.AM1 +#define CAN2IDMR6_AM2 _CAN2IDMR6.Bits.AM2 +#define CAN2IDMR6_AM3 _CAN2IDMR6.Bits.AM3 +#define CAN2IDMR6_AM4 _CAN2IDMR6.Bits.AM4 +#define CAN2IDMR6_AM5 _CAN2IDMR6.Bits.AM5 +#define CAN2IDMR6_AM6 _CAN2IDMR6.Bits.AM6 +#define CAN2IDMR6_AM7 _CAN2IDMR6.Bits.AM7 +#define CAN2IDMR6_AM _CAN2IDMR6.MergedBits.grpAM + + +/*** CAN2IDMR7 - MSCAN 2 Identifier Mask Register 7; 0x000001DF ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN2IDMR7STR; +extern volatile CAN2IDMR7STR _CAN2IDMR7 @(REG_BASE + 0x000001DF); +#define CAN2IDMR7 _CAN2IDMR7.Byte +#define CAN2IDMR7_AM0 _CAN2IDMR7.Bits.AM0 +#define CAN2IDMR7_AM1 _CAN2IDMR7.Bits.AM1 +#define CAN2IDMR7_AM2 _CAN2IDMR7.Bits.AM2 +#define CAN2IDMR7_AM3 _CAN2IDMR7.Bits.AM3 +#define CAN2IDMR7_AM4 _CAN2IDMR7.Bits.AM4 +#define CAN2IDMR7_AM5 _CAN2IDMR7.Bits.AM5 +#define CAN2IDMR7_AM6 _CAN2IDMR7.Bits.AM6 +#define CAN2IDMR7_AM7 _CAN2IDMR7.Bits.AM7 +#define CAN2IDMR7_AM _CAN2IDMR7.MergedBits.grpAM + + +/*** CAN2RXIDR0 - MSCAN 2 Receive Identifier Register 0; 0x000001E0 ***/ +typedef union { + byte Byte; + struct { + byte ID21 :1; /* Extended format identifier Bit 21 */ + byte ID22 :1; /* Extended format identifier Bit 22 */ + byte ID23 :1; /* Extended format identifier Bit 23 */ + byte ID24 :1; /* Extended format identifier Bit 24 */ + byte ID25 :1; /* Extended format identifier Bit 25 */ + byte ID26 :1; /* Extended format identifier Bit 26 */ + byte ID27 :1; /* Extended format identifier Bit 27 */ + byte ID28 :1; /* Extended format identifier Bit 28 */ + } Bits; + struct { + byte grpID_21 :8; + } MergedBits; +} CAN2RXIDR0STR; +extern volatile CAN2RXIDR0STR _CAN2RXIDR0 @(REG_BASE + 0x000001E0); +#define CAN2RXIDR0 _CAN2RXIDR0.Byte +#define CAN2RXIDR0_ID21 _CAN2RXIDR0.Bits.ID21 +#define CAN2RXIDR0_ID22 _CAN2RXIDR0.Bits.ID22 +#define CAN2RXIDR0_ID23 _CAN2RXIDR0.Bits.ID23 +#define CAN2RXIDR0_ID24 _CAN2RXIDR0.Bits.ID24 +#define CAN2RXIDR0_ID25 _CAN2RXIDR0.Bits.ID25 +#define CAN2RXIDR0_ID26 _CAN2RXIDR0.Bits.ID26 +#define CAN2RXIDR0_ID27 _CAN2RXIDR0.Bits.ID27 +#define CAN2RXIDR0_ID28 _CAN2RXIDR0.Bits.ID28 +#define CAN2RXIDR0_ID_21 _CAN2RXIDR0.MergedBits.grpID_21 +#define CAN2RXIDR0_ID CAN2RXIDR0_ID_21 + + +/*** CAN2RXIDR1 - MSCAN 2 Receive Identifier Register 1; 0x000001E1 ***/ +typedef union { + byte Byte; + struct { + byte ID15 :1; /* Extended format identifier Bit 15 */ + byte ID16 :1; /* Extended format identifier Bit 16 */ + byte ID17 :1; /* Extended format identifier Bit 17 */ + byte IDE :1; /* ID Extended */ + byte SRR :1; /* Substitute Remote Request */ + byte ID18 :1; /* Extended format identifier Bit 18 */ + byte ID19 :1; /* Extended format identifier Bit 19 */ + byte ID20 :1; /* Extended format identifier Bit 20 */ + } Bits; + struct { + byte grpID_15 :3; + byte :1; + byte :1; + byte grpID_18 :3; + } MergedBits; +} CAN2RXIDR1STR; +extern volatile CAN2RXIDR1STR _CAN2RXIDR1 @(REG_BASE + 0x000001E1); +#define CAN2RXIDR1 _CAN2RXIDR1.Byte +#define CAN2RXIDR1_ID15 _CAN2RXIDR1.Bits.ID15 +#define CAN2RXIDR1_ID16 _CAN2RXIDR1.Bits.ID16 +#define CAN2RXIDR1_ID17 _CAN2RXIDR1.Bits.ID17 +#define CAN2RXIDR1_IDE _CAN2RXIDR1.Bits.IDE +#define CAN2RXIDR1_SRR _CAN2RXIDR1.Bits.SRR +#define CAN2RXIDR1_ID18 _CAN2RXIDR1.Bits.ID18 +#define CAN2RXIDR1_ID19 _CAN2RXIDR1.Bits.ID19 +#define CAN2RXIDR1_ID20 _CAN2RXIDR1.Bits.ID20 +#define CAN2RXIDR1_ID_15 _CAN2RXIDR1.MergedBits.grpID_15 +#define CAN2RXIDR1_ID_18 _CAN2RXIDR1.MergedBits.grpID_18 +#define CAN2RXIDR1_ID CAN2RXIDR1_ID_15 + + +/*** CAN2RXIDR2 - MSCAN 2 Receive Identifier Register 2; 0x000001E2 ***/ +typedef union { + byte Byte; + struct { + byte ID7 :1; /* Extended format identifier Bit 7 */ + byte ID8 :1; /* Extended format identifier Bit 8 */ + byte ID9 :1; /* Extended format identifier Bit 9 */ + byte ID10 :1; /* Extended format identifier Bit 10 */ + byte ID11 :1; /* Extended format identifier Bit 11 */ + byte ID12 :1; /* Extended format identifier Bit 12 */ + byte ID13 :1; /* Extended format identifier Bit 13 */ + byte ID14 :1; /* Extended format identifier Bit 14 */ + } Bits; + struct { + byte grpID_7 :8; + } MergedBits; +} CAN2RXIDR2STR; +extern volatile CAN2RXIDR2STR _CAN2RXIDR2 @(REG_BASE + 0x000001E2); +#define CAN2RXIDR2 _CAN2RXIDR2.Byte +#define CAN2RXIDR2_ID7 _CAN2RXIDR2.Bits.ID7 +#define CAN2RXIDR2_ID8 _CAN2RXIDR2.Bits.ID8 +#define CAN2RXIDR2_ID9 _CAN2RXIDR2.Bits.ID9 +#define CAN2RXIDR2_ID10 _CAN2RXIDR2.Bits.ID10 +#define CAN2RXIDR2_ID11 _CAN2RXIDR2.Bits.ID11 +#define CAN2RXIDR2_ID12 _CAN2RXIDR2.Bits.ID12 +#define CAN2RXIDR2_ID13 _CAN2RXIDR2.Bits.ID13 +#define CAN2RXIDR2_ID14 _CAN2RXIDR2.Bits.ID14 +#define CAN2RXIDR2_ID_7 _CAN2RXIDR2.MergedBits.grpID_7 +#define CAN2RXIDR2_ID CAN2RXIDR2_ID_7 + + +/*** CAN2RXIDR3 - MSCAN 2 Receive Identifier Register 3; 0x000001E3 ***/ +typedef union { + byte Byte; + struct { + byte RTR :1; /* Remote Transmission Request */ + byte ID0 :1; /* Extended format identifier Bit 0 */ + byte ID1 :1; /* Extended format identifier Bit 1 */ + byte ID2 :1; /* Extended format identifier Bit 2 */ + byte ID3 :1; /* Extended format identifier Bit 3 */ + byte ID4 :1; /* Extended format identifier Bit 4 */ + byte ID5 :1; /* Extended format identifier Bit 5 */ + byte ID6 :1; /* Extended format identifier Bit 6 */ + } Bits; + struct { + byte :1; + byte grpID :7; + } MergedBits; +} CAN2RXIDR3STR; +extern volatile CAN2RXIDR3STR _CAN2RXIDR3 @(REG_BASE + 0x000001E3); +#define CAN2RXIDR3 _CAN2RXIDR3.Byte +#define CAN2RXIDR3_RTR _CAN2RXIDR3.Bits.RTR +#define CAN2RXIDR3_ID0 _CAN2RXIDR3.Bits.ID0 +#define CAN2RXIDR3_ID1 _CAN2RXIDR3.Bits.ID1 +#define CAN2RXIDR3_ID2 _CAN2RXIDR3.Bits.ID2 +#define CAN2RXIDR3_ID3 _CAN2RXIDR3.Bits.ID3 +#define CAN2RXIDR3_ID4 _CAN2RXIDR3.Bits.ID4 +#define CAN2RXIDR3_ID5 _CAN2RXIDR3.Bits.ID5 +#define CAN2RXIDR3_ID6 _CAN2RXIDR3.Bits.ID6 +#define CAN2RXIDR3_ID _CAN2RXIDR3.MergedBits.grpID + + +/*** CAN2RXDSR0 - MSCAN 2 Receive Data Segment Register 0; 0x000001E4 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN2RXDSR0STR; +extern volatile CAN2RXDSR0STR _CAN2RXDSR0 @(REG_BASE + 0x000001E4); +#define CAN2RXDSR0 _CAN2RXDSR0.Byte +#define CAN2RXDSR0_DB0 _CAN2RXDSR0.Bits.DB0 +#define CAN2RXDSR0_DB1 _CAN2RXDSR0.Bits.DB1 +#define CAN2RXDSR0_DB2 _CAN2RXDSR0.Bits.DB2 +#define CAN2RXDSR0_DB3 _CAN2RXDSR0.Bits.DB3 +#define CAN2RXDSR0_DB4 _CAN2RXDSR0.Bits.DB4 +#define CAN2RXDSR0_DB5 _CAN2RXDSR0.Bits.DB5 +#define CAN2RXDSR0_DB6 _CAN2RXDSR0.Bits.DB6 +#define CAN2RXDSR0_DB7 _CAN2RXDSR0.Bits.DB7 +#define CAN2RXDSR0_DB _CAN2RXDSR0.MergedBits.grpDB + + +/*** CAN2RXDSR1 - MSCAN 2 Receive Data Segment Register 1; 0x000001E5 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN2RXDSR1STR; +extern volatile CAN2RXDSR1STR _CAN2RXDSR1 @(REG_BASE + 0x000001E5); +#define CAN2RXDSR1 _CAN2RXDSR1.Byte +#define CAN2RXDSR1_DB0 _CAN2RXDSR1.Bits.DB0 +#define CAN2RXDSR1_DB1 _CAN2RXDSR1.Bits.DB1 +#define CAN2RXDSR1_DB2 _CAN2RXDSR1.Bits.DB2 +#define CAN2RXDSR1_DB3 _CAN2RXDSR1.Bits.DB3 +#define CAN2RXDSR1_DB4 _CAN2RXDSR1.Bits.DB4 +#define CAN2RXDSR1_DB5 _CAN2RXDSR1.Bits.DB5 +#define CAN2RXDSR1_DB6 _CAN2RXDSR1.Bits.DB6 +#define CAN2RXDSR1_DB7 _CAN2RXDSR1.Bits.DB7 +#define CAN2RXDSR1_DB _CAN2RXDSR1.MergedBits.grpDB + + +/*** CAN2RXDSR2 - MSCAN 2 Receive Data Segment Register 2; 0x000001E6 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN2RXDSR2STR; +extern volatile CAN2RXDSR2STR _CAN2RXDSR2 @(REG_BASE + 0x000001E6); +#define CAN2RXDSR2 _CAN2RXDSR2.Byte +#define CAN2RXDSR2_DB0 _CAN2RXDSR2.Bits.DB0 +#define CAN2RXDSR2_DB1 _CAN2RXDSR2.Bits.DB1 +#define CAN2RXDSR2_DB2 _CAN2RXDSR2.Bits.DB2 +#define CAN2RXDSR2_DB3 _CAN2RXDSR2.Bits.DB3 +#define CAN2RXDSR2_DB4 _CAN2RXDSR2.Bits.DB4 +#define CAN2RXDSR2_DB5 _CAN2RXDSR2.Bits.DB5 +#define CAN2RXDSR2_DB6 _CAN2RXDSR2.Bits.DB6 +#define CAN2RXDSR2_DB7 _CAN2RXDSR2.Bits.DB7 +#define CAN2RXDSR2_DB _CAN2RXDSR2.MergedBits.grpDB + + +/*** CAN2RXDSR3 - MSCAN 2 Receive Data Segment Register 3; 0x000001E7 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN2RXDSR3STR; +extern volatile CAN2RXDSR3STR _CAN2RXDSR3 @(REG_BASE + 0x000001E7); +#define CAN2RXDSR3 _CAN2RXDSR3.Byte +#define CAN2RXDSR3_DB0 _CAN2RXDSR3.Bits.DB0 +#define CAN2RXDSR3_DB1 _CAN2RXDSR3.Bits.DB1 +#define CAN2RXDSR3_DB2 _CAN2RXDSR3.Bits.DB2 +#define CAN2RXDSR3_DB3 _CAN2RXDSR3.Bits.DB3 +#define CAN2RXDSR3_DB4 _CAN2RXDSR3.Bits.DB4 +#define CAN2RXDSR3_DB5 _CAN2RXDSR3.Bits.DB5 +#define CAN2RXDSR3_DB6 _CAN2RXDSR3.Bits.DB6 +#define CAN2RXDSR3_DB7 _CAN2RXDSR3.Bits.DB7 +#define CAN2RXDSR3_DB _CAN2RXDSR3.MergedBits.grpDB + + +/*** CAN2RXDSR4 - MSCAN 2 Receive Data Segment Register 4; 0x000001E8 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN2RXDSR4STR; +extern volatile CAN2RXDSR4STR _CAN2RXDSR4 @(REG_BASE + 0x000001E8); +#define CAN2RXDSR4 _CAN2RXDSR4.Byte +#define CAN2RXDSR4_DB0 _CAN2RXDSR4.Bits.DB0 +#define CAN2RXDSR4_DB1 _CAN2RXDSR4.Bits.DB1 +#define CAN2RXDSR4_DB2 _CAN2RXDSR4.Bits.DB2 +#define CAN2RXDSR4_DB3 _CAN2RXDSR4.Bits.DB3 +#define CAN2RXDSR4_DB4 _CAN2RXDSR4.Bits.DB4 +#define CAN2RXDSR4_DB5 _CAN2RXDSR4.Bits.DB5 +#define CAN2RXDSR4_DB6 _CAN2RXDSR4.Bits.DB6 +#define CAN2RXDSR4_DB7 _CAN2RXDSR4.Bits.DB7 +#define CAN2RXDSR4_DB _CAN2RXDSR4.MergedBits.grpDB + + +/*** CAN2RXDSR5 - MSCAN 2 Receive Data Segment Register 5; 0x000001E9 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN2RXDSR5STR; +extern volatile CAN2RXDSR5STR _CAN2RXDSR5 @(REG_BASE + 0x000001E9); +#define CAN2RXDSR5 _CAN2RXDSR5.Byte +#define CAN2RXDSR5_DB0 _CAN2RXDSR5.Bits.DB0 +#define CAN2RXDSR5_DB1 _CAN2RXDSR5.Bits.DB1 +#define CAN2RXDSR5_DB2 _CAN2RXDSR5.Bits.DB2 +#define CAN2RXDSR5_DB3 _CAN2RXDSR5.Bits.DB3 +#define CAN2RXDSR5_DB4 _CAN2RXDSR5.Bits.DB4 +#define CAN2RXDSR5_DB5 _CAN2RXDSR5.Bits.DB5 +#define CAN2RXDSR5_DB6 _CAN2RXDSR5.Bits.DB6 +#define CAN2RXDSR5_DB7 _CAN2RXDSR5.Bits.DB7 +#define CAN2RXDSR5_DB _CAN2RXDSR5.MergedBits.grpDB + + +/*** CAN2RXDSR6 - MSCAN 2 Receive Data Segment Register 6; 0x000001EA ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN2RXDSR6STR; +extern volatile CAN2RXDSR6STR _CAN2RXDSR6 @(REG_BASE + 0x000001EA); +#define CAN2RXDSR6 _CAN2RXDSR6.Byte +#define CAN2RXDSR6_DB0 _CAN2RXDSR6.Bits.DB0 +#define CAN2RXDSR6_DB1 _CAN2RXDSR6.Bits.DB1 +#define CAN2RXDSR6_DB2 _CAN2RXDSR6.Bits.DB2 +#define CAN2RXDSR6_DB3 _CAN2RXDSR6.Bits.DB3 +#define CAN2RXDSR6_DB4 _CAN2RXDSR6.Bits.DB4 +#define CAN2RXDSR6_DB5 _CAN2RXDSR6.Bits.DB5 +#define CAN2RXDSR6_DB6 _CAN2RXDSR6.Bits.DB6 +#define CAN2RXDSR6_DB7 _CAN2RXDSR6.Bits.DB7 +#define CAN2RXDSR6_DB _CAN2RXDSR6.MergedBits.grpDB + + +/*** CAN2RXDSR7 - MSCAN 2 Receive Data Segment Register 7; 0x000001EB ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN2RXDSR7STR; +extern volatile CAN2RXDSR7STR _CAN2RXDSR7 @(REG_BASE + 0x000001EB); +#define CAN2RXDSR7 _CAN2RXDSR7.Byte +#define CAN2RXDSR7_DB0 _CAN2RXDSR7.Bits.DB0 +#define CAN2RXDSR7_DB1 _CAN2RXDSR7.Bits.DB1 +#define CAN2RXDSR7_DB2 _CAN2RXDSR7.Bits.DB2 +#define CAN2RXDSR7_DB3 _CAN2RXDSR7.Bits.DB3 +#define CAN2RXDSR7_DB4 _CAN2RXDSR7.Bits.DB4 +#define CAN2RXDSR7_DB5 _CAN2RXDSR7.Bits.DB5 +#define CAN2RXDSR7_DB6 _CAN2RXDSR7.Bits.DB6 +#define CAN2RXDSR7_DB7 _CAN2RXDSR7.Bits.DB7 +#define CAN2RXDSR7_DB _CAN2RXDSR7.MergedBits.grpDB + + +/*** CAN2RXDLR - MSCAN 2 Receive Data Length Register; 0x000001EC ***/ +typedef union { + byte Byte; + struct { + byte DLC0 :1; /* Data Length Code Bit 0 */ + byte DLC1 :1; /* Data Length Code Bit 1 */ + byte DLC2 :1; /* Data Length Code Bit 2 */ + byte DLC3 :1; /* Data Length Code Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpDLC :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN2RXDLRSTR; +extern volatile CAN2RXDLRSTR _CAN2RXDLR @(REG_BASE + 0x000001EC); +#define CAN2RXDLR _CAN2RXDLR.Byte +#define CAN2RXDLR_DLC0 _CAN2RXDLR.Bits.DLC0 +#define CAN2RXDLR_DLC1 _CAN2RXDLR.Bits.DLC1 +#define CAN2RXDLR_DLC2 _CAN2RXDLR.Bits.DLC2 +#define CAN2RXDLR_DLC3 _CAN2RXDLR.Bits.DLC3 +#define CAN2RXDLR_DLC _CAN2RXDLR.MergedBits.grpDLC + + +/*** CAN2TXIDR0 - MSCAN 2 Transmit Identifier Register 0; 0x000001F0 ***/ +typedef union { + byte Byte; + struct { + byte ID21 :1; /* Extended format identifier Bit 21 */ + byte ID22 :1; /* Extended format identifier Bit 22 */ + byte ID23 :1; /* Extended format identifier Bit 23 */ + byte ID24 :1; /* Extended format identifier Bit 24 */ + byte ID25 :1; /* Extended format identifier Bit 25 */ + byte ID26 :1; /* Extended format identifier Bit 26 */ + byte ID27 :1; /* Extended format identifier Bit 27 */ + byte ID28 :1; /* Extended format identifier Bit 28 */ + } Bits; + struct { + byte grpID_21 :8; + } MergedBits; +} CAN2TXIDR0STR; +extern volatile CAN2TXIDR0STR _CAN2TXIDR0 @(REG_BASE + 0x000001F0); +#define CAN2TXIDR0 _CAN2TXIDR0.Byte +#define CAN2TXIDR0_ID21 _CAN2TXIDR0.Bits.ID21 +#define CAN2TXIDR0_ID22 _CAN2TXIDR0.Bits.ID22 +#define CAN2TXIDR0_ID23 _CAN2TXIDR0.Bits.ID23 +#define CAN2TXIDR0_ID24 _CAN2TXIDR0.Bits.ID24 +#define CAN2TXIDR0_ID25 _CAN2TXIDR0.Bits.ID25 +#define CAN2TXIDR0_ID26 _CAN2TXIDR0.Bits.ID26 +#define CAN2TXIDR0_ID27 _CAN2TXIDR0.Bits.ID27 +#define CAN2TXIDR0_ID28 _CAN2TXIDR0.Bits.ID28 +#define CAN2TXIDR0_ID_21 _CAN2TXIDR0.MergedBits.grpID_21 +#define CAN2TXIDR0_ID CAN2TXIDR0_ID_21 + + +/*** CAN2TXIDR1 - MSCAN 2 Transmit Identifier Register 1; 0x000001F1 ***/ +typedef union { + byte Byte; + struct { + byte ID15 :1; /* Extended format identifier Bit 15 */ + byte ID16 :1; /* Extended format identifier Bit 16 */ + byte ID17 :1; /* Extended format identifier Bit 17 */ + byte IDE :1; /* ID Extended */ + byte SRR :1; /* Substitute Remote Request */ + byte ID18 :1; /* Extended format identifier Bit 18 */ + byte ID19 :1; /* Extended format identifier Bit 19 */ + byte ID20 :1; /* Extended format identifier Bit 20 */ + } Bits; + struct { + byte grpID_15 :3; + byte :1; + byte :1; + byte grpID_18 :3; + } MergedBits; +} CAN2TXIDR1STR; +extern volatile CAN2TXIDR1STR _CAN2TXIDR1 @(REG_BASE + 0x000001F1); +#define CAN2TXIDR1 _CAN2TXIDR1.Byte +#define CAN2TXIDR1_ID15 _CAN2TXIDR1.Bits.ID15 +#define CAN2TXIDR1_ID16 _CAN2TXIDR1.Bits.ID16 +#define CAN2TXIDR1_ID17 _CAN2TXIDR1.Bits.ID17 +#define CAN2TXIDR1_IDE _CAN2TXIDR1.Bits.IDE +#define CAN2TXIDR1_SRR _CAN2TXIDR1.Bits.SRR +#define CAN2TXIDR1_ID18 _CAN2TXIDR1.Bits.ID18 +#define CAN2TXIDR1_ID19 _CAN2TXIDR1.Bits.ID19 +#define CAN2TXIDR1_ID20 _CAN2TXIDR1.Bits.ID20 +#define CAN2TXIDR1_ID_15 _CAN2TXIDR1.MergedBits.grpID_15 +#define CAN2TXIDR1_ID_18 _CAN2TXIDR1.MergedBits.grpID_18 +#define CAN2TXIDR1_ID CAN2TXIDR1_ID_15 + + +/*** CAN2TXIDR2 - MSCAN 2 Transmit Identifier Register 2; 0x000001F2 ***/ +typedef union { + byte Byte; + struct { + byte ID7 :1; /* Extended format identifier Bit 7 */ + byte ID8 :1; /* Extended format identifier Bit 8 */ + byte ID9 :1; /* Extended format identifier Bit 9 */ + byte ID10 :1; /* Extended format identifier Bit 10 */ + byte ID11 :1; /* Extended format identifier Bit 11 */ + byte ID12 :1; /* Extended format identifier Bit 12 */ + byte ID13 :1; /* Extended format identifier Bit 13 */ + byte ID14 :1; /* Extended format identifier Bit 14 */ + } Bits; + struct { + byte grpID_7 :8; + } MergedBits; +} CAN2TXIDR2STR; +extern volatile CAN2TXIDR2STR _CAN2TXIDR2 @(REG_BASE + 0x000001F2); +#define CAN2TXIDR2 _CAN2TXIDR2.Byte +#define CAN2TXIDR2_ID7 _CAN2TXIDR2.Bits.ID7 +#define CAN2TXIDR2_ID8 _CAN2TXIDR2.Bits.ID8 +#define CAN2TXIDR2_ID9 _CAN2TXIDR2.Bits.ID9 +#define CAN2TXIDR2_ID10 _CAN2TXIDR2.Bits.ID10 +#define CAN2TXIDR2_ID11 _CAN2TXIDR2.Bits.ID11 +#define CAN2TXIDR2_ID12 _CAN2TXIDR2.Bits.ID12 +#define CAN2TXIDR2_ID13 _CAN2TXIDR2.Bits.ID13 +#define CAN2TXIDR2_ID14 _CAN2TXIDR2.Bits.ID14 +#define CAN2TXIDR2_ID_7 _CAN2TXIDR2.MergedBits.grpID_7 +#define CAN2TXIDR2_ID CAN2TXIDR2_ID_7 + + +/*** CAN2TXIDR3 - MSCAN 2 Transmit Identifier Register 3; 0x000001F3 ***/ +typedef union { + byte Byte; + struct { + byte RTR :1; /* Remote Transmission Request */ + byte ID0 :1; /* Extended format identifier Bit 0 */ + byte ID1 :1; /* Extended format identifier Bit 1 */ + byte ID2 :1; /* Extended format identifier Bit 2 */ + byte ID3 :1; /* Extended format identifier Bit 3 */ + byte ID4 :1; /* Extended format identifier Bit 4 */ + byte ID5 :1; /* Extended format identifier Bit 5 */ + byte ID6 :1; /* Extended format identifier Bit 6 */ + } Bits; + struct { + byte :1; + byte grpID :7; + } MergedBits; +} CAN2TXIDR3STR; +extern volatile CAN2TXIDR3STR _CAN2TXIDR3 @(REG_BASE + 0x000001F3); +#define CAN2TXIDR3 _CAN2TXIDR3.Byte +#define CAN2TXIDR3_RTR _CAN2TXIDR3.Bits.RTR +#define CAN2TXIDR3_ID0 _CAN2TXIDR3.Bits.ID0 +#define CAN2TXIDR3_ID1 _CAN2TXIDR3.Bits.ID1 +#define CAN2TXIDR3_ID2 _CAN2TXIDR3.Bits.ID2 +#define CAN2TXIDR3_ID3 _CAN2TXIDR3.Bits.ID3 +#define CAN2TXIDR3_ID4 _CAN2TXIDR3.Bits.ID4 +#define CAN2TXIDR3_ID5 _CAN2TXIDR3.Bits.ID5 +#define CAN2TXIDR3_ID6 _CAN2TXIDR3.Bits.ID6 +#define CAN2TXIDR3_ID _CAN2TXIDR3.MergedBits.grpID + + +/*** CAN2TXDSR0 - MSCAN 2 Transmit Data Segment Register 0; 0x000001F4 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN2TXDSR0STR; +extern volatile CAN2TXDSR0STR _CAN2TXDSR0 @(REG_BASE + 0x000001F4); +#define CAN2TXDSR0 _CAN2TXDSR0.Byte +#define CAN2TXDSR0_DB0 _CAN2TXDSR0.Bits.DB0 +#define CAN2TXDSR0_DB1 _CAN2TXDSR0.Bits.DB1 +#define CAN2TXDSR0_DB2 _CAN2TXDSR0.Bits.DB2 +#define CAN2TXDSR0_DB3 _CAN2TXDSR0.Bits.DB3 +#define CAN2TXDSR0_DB4 _CAN2TXDSR0.Bits.DB4 +#define CAN2TXDSR0_DB5 _CAN2TXDSR0.Bits.DB5 +#define CAN2TXDSR0_DB6 _CAN2TXDSR0.Bits.DB6 +#define CAN2TXDSR0_DB7 _CAN2TXDSR0.Bits.DB7 +#define CAN2TXDSR0_DB _CAN2TXDSR0.MergedBits.grpDB + + +/*** CAN2TXDSR1 - MSCAN 2 Transmit Data Segment Register 1; 0x000001F5 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN2TXDSR1STR; +extern volatile CAN2TXDSR1STR _CAN2TXDSR1 @(REG_BASE + 0x000001F5); +#define CAN2TXDSR1 _CAN2TXDSR1.Byte +#define CAN2TXDSR1_DB0 _CAN2TXDSR1.Bits.DB0 +#define CAN2TXDSR1_DB1 _CAN2TXDSR1.Bits.DB1 +#define CAN2TXDSR1_DB2 _CAN2TXDSR1.Bits.DB2 +#define CAN2TXDSR1_DB3 _CAN2TXDSR1.Bits.DB3 +#define CAN2TXDSR1_DB4 _CAN2TXDSR1.Bits.DB4 +#define CAN2TXDSR1_DB5 _CAN2TXDSR1.Bits.DB5 +#define CAN2TXDSR1_DB6 _CAN2TXDSR1.Bits.DB6 +#define CAN2TXDSR1_DB7 _CAN2TXDSR1.Bits.DB7 +#define CAN2TXDSR1_DB _CAN2TXDSR1.MergedBits.grpDB + + +/*** CAN2TXDSR2 - MSCAN 2 Transmit Data Segment Register 2; 0x000001F6 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN2TXDSR2STR; +extern volatile CAN2TXDSR2STR _CAN2TXDSR2 @(REG_BASE + 0x000001F6); +#define CAN2TXDSR2 _CAN2TXDSR2.Byte +#define CAN2TXDSR2_DB0 _CAN2TXDSR2.Bits.DB0 +#define CAN2TXDSR2_DB1 _CAN2TXDSR2.Bits.DB1 +#define CAN2TXDSR2_DB2 _CAN2TXDSR2.Bits.DB2 +#define CAN2TXDSR2_DB3 _CAN2TXDSR2.Bits.DB3 +#define CAN2TXDSR2_DB4 _CAN2TXDSR2.Bits.DB4 +#define CAN2TXDSR2_DB5 _CAN2TXDSR2.Bits.DB5 +#define CAN2TXDSR2_DB6 _CAN2TXDSR2.Bits.DB6 +#define CAN2TXDSR2_DB7 _CAN2TXDSR2.Bits.DB7 +#define CAN2TXDSR2_DB _CAN2TXDSR2.MergedBits.grpDB + + +/*** CAN2TXDSR3 - MSCAN 2 Transmit Data Segment Register 3; 0x000001F7 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN2TXDSR3STR; +extern volatile CAN2TXDSR3STR _CAN2TXDSR3 @(REG_BASE + 0x000001F7); +#define CAN2TXDSR3 _CAN2TXDSR3.Byte +#define CAN2TXDSR3_DB0 _CAN2TXDSR3.Bits.DB0 +#define CAN2TXDSR3_DB1 _CAN2TXDSR3.Bits.DB1 +#define CAN2TXDSR3_DB2 _CAN2TXDSR3.Bits.DB2 +#define CAN2TXDSR3_DB3 _CAN2TXDSR3.Bits.DB3 +#define CAN2TXDSR3_DB4 _CAN2TXDSR3.Bits.DB4 +#define CAN2TXDSR3_DB5 _CAN2TXDSR3.Bits.DB5 +#define CAN2TXDSR3_DB6 _CAN2TXDSR3.Bits.DB6 +#define CAN2TXDSR3_DB7 _CAN2TXDSR3.Bits.DB7 +#define CAN2TXDSR3_DB _CAN2TXDSR3.MergedBits.grpDB + + +/*** CAN2TXDSR4 - MSCAN 2 Transmit Data Segment Register 4; 0x000001F8 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN2TXDSR4STR; +extern volatile CAN2TXDSR4STR _CAN2TXDSR4 @(REG_BASE + 0x000001F8); +#define CAN2TXDSR4 _CAN2TXDSR4.Byte +#define CAN2TXDSR4_DB0 _CAN2TXDSR4.Bits.DB0 +#define CAN2TXDSR4_DB1 _CAN2TXDSR4.Bits.DB1 +#define CAN2TXDSR4_DB2 _CAN2TXDSR4.Bits.DB2 +#define CAN2TXDSR4_DB3 _CAN2TXDSR4.Bits.DB3 +#define CAN2TXDSR4_DB4 _CAN2TXDSR4.Bits.DB4 +#define CAN2TXDSR4_DB5 _CAN2TXDSR4.Bits.DB5 +#define CAN2TXDSR4_DB6 _CAN2TXDSR4.Bits.DB6 +#define CAN2TXDSR4_DB7 _CAN2TXDSR4.Bits.DB7 +#define CAN2TXDSR4_DB _CAN2TXDSR4.MergedBits.grpDB + + +/*** CAN2TXDSR5 - MSCAN 2 Transmit Data Segment Register 5; 0x000001F9 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN2TXDSR5STR; +extern volatile CAN2TXDSR5STR _CAN2TXDSR5 @(REG_BASE + 0x000001F9); +#define CAN2TXDSR5 _CAN2TXDSR5.Byte +#define CAN2TXDSR5_DB0 _CAN2TXDSR5.Bits.DB0 +#define CAN2TXDSR5_DB1 _CAN2TXDSR5.Bits.DB1 +#define CAN2TXDSR5_DB2 _CAN2TXDSR5.Bits.DB2 +#define CAN2TXDSR5_DB3 _CAN2TXDSR5.Bits.DB3 +#define CAN2TXDSR5_DB4 _CAN2TXDSR5.Bits.DB4 +#define CAN2TXDSR5_DB5 _CAN2TXDSR5.Bits.DB5 +#define CAN2TXDSR5_DB6 _CAN2TXDSR5.Bits.DB6 +#define CAN2TXDSR5_DB7 _CAN2TXDSR5.Bits.DB7 +#define CAN2TXDSR5_DB _CAN2TXDSR5.MergedBits.grpDB + + +/*** CAN2TXDSR6 - MSCAN 2 Transmit Data Segment Register 6; 0x000001FA ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN2TXDSR6STR; +extern volatile CAN2TXDSR6STR _CAN2TXDSR6 @(REG_BASE + 0x000001FA); +#define CAN2TXDSR6 _CAN2TXDSR6.Byte +#define CAN2TXDSR6_DB0 _CAN2TXDSR6.Bits.DB0 +#define CAN2TXDSR6_DB1 _CAN2TXDSR6.Bits.DB1 +#define CAN2TXDSR6_DB2 _CAN2TXDSR6.Bits.DB2 +#define CAN2TXDSR6_DB3 _CAN2TXDSR6.Bits.DB3 +#define CAN2TXDSR6_DB4 _CAN2TXDSR6.Bits.DB4 +#define CAN2TXDSR6_DB5 _CAN2TXDSR6.Bits.DB5 +#define CAN2TXDSR6_DB6 _CAN2TXDSR6.Bits.DB6 +#define CAN2TXDSR6_DB7 _CAN2TXDSR6.Bits.DB7 +#define CAN2TXDSR6_DB _CAN2TXDSR6.MergedBits.grpDB + + +/*** CAN2TXDSR7 - MSCAN 2 Transmit Data Segment Register 7; 0x000001FB ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN2TXDSR7STR; +extern volatile CAN2TXDSR7STR _CAN2TXDSR7 @(REG_BASE + 0x000001FB); +#define CAN2TXDSR7 _CAN2TXDSR7.Byte +#define CAN2TXDSR7_DB0 _CAN2TXDSR7.Bits.DB0 +#define CAN2TXDSR7_DB1 _CAN2TXDSR7.Bits.DB1 +#define CAN2TXDSR7_DB2 _CAN2TXDSR7.Bits.DB2 +#define CAN2TXDSR7_DB3 _CAN2TXDSR7.Bits.DB3 +#define CAN2TXDSR7_DB4 _CAN2TXDSR7.Bits.DB4 +#define CAN2TXDSR7_DB5 _CAN2TXDSR7.Bits.DB5 +#define CAN2TXDSR7_DB6 _CAN2TXDSR7.Bits.DB6 +#define CAN2TXDSR7_DB7 _CAN2TXDSR7.Bits.DB7 +#define CAN2TXDSR7_DB _CAN2TXDSR7.MergedBits.grpDB + + +/*** CAN2TXDLR - MSCAN 2 Transmit Data Length Register; 0x000001FC ***/ +typedef union { + byte Byte; + struct { + byte DLC0 :1; /* Data Length Code Bit 0 */ + byte DLC1 :1; /* Data Length Code Bit 1 */ + byte DLC2 :1; /* Data Length Code Bit 2 */ + byte DLC3 :1; /* Data Length Code Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpDLC :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN2TXDLRSTR; +extern volatile CAN2TXDLRSTR _CAN2TXDLR @(REG_BASE + 0x000001FC); +#define CAN2TXDLR _CAN2TXDLR.Byte +#define CAN2TXDLR_DLC0 _CAN2TXDLR.Bits.DLC0 +#define CAN2TXDLR_DLC1 _CAN2TXDLR.Bits.DLC1 +#define CAN2TXDLR_DLC2 _CAN2TXDLR.Bits.DLC2 +#define CAN2TXDLR_DLC3 _CAN2TXDLR.Bits.DLC3 +#define CAN2TXDLR_DLC _CAN2TXDLR.MergedBits.grpDLC + + +/*** CAN2TXTBPR - MSCAN 2 Transmit Buffer Priority; 0x000001FF ***/ +typedef union { + byte Byte; + struct { + byte PRIO0 :1; /* Transmit Buffer Priority Bit 0 */ + byte PRIO1 :1; /* Transmit Buffer Priority Bit 1 */ + byte PRIO2 :1; /* Transmit Buffer Priority Bit 2 */ + byte PRIO3 :1; /* Transmit Buffer Priority Bit 3 */ + byte PRIO4 :1; /* Transmit Buffer Priority Bit 4 */ + byte PRIO5 :1; /* Transmit Buffer Priority Bit 5 */ + byte PRIO6 :1; /* Transmit Buffer Priority Bit 6 */ + byte PRIO7 :1; /* Transmit Buffer Priority Bit 7 */ + } Bits; + struct { + byte grpPRIO :8; + } MergedBits; +} CAN2TXTBPRSTR; +extern volatile CAN2TXTBPRSTR _CAN2TXTBPR @(REG_BASE + 0x000001FF); +#define CAN2TXTBPR _CAN2TXTBPR.Byte +#define CAN2TXTBPR_PRIO0 _CAN2TXTBPR.Bits.PRIO0 +#define CAN2TXTBPR_PRIO1 _CAN2TXTBPR.Bits.PRIO1 +#define CAN2TXTBPR_PRIO2 _CAN2TXTBPR.Bits.PRIO2 +#define CAN2TXTBPR_PRIO3 _CAN2TXTBPR.Bits.PRIO3 +#define CAN2TXTBPR_PRIO4 _CAN2TXTBPR.Bits.PRIO4 +#define CAN2TXTBPR_PRIO5 _CAN2TXTBPR.Bits.PRIO5 +#define CAN2TXTBPR_PRIO6 _CAN2TXTBPR.Bits.PRIO6 +#define CAN2TXTBPR_PRIO7 _CAN2TXTBPR.Bits.PRIO7 +#define CAN2TXTBPR_PRIO _CAN2TXTBPR.MergedBits.grpPRIO + + +/*** CAN3CTL0 - MSCAN 3 Control 0 Register; 0x00000200 ***/ +typedef union { + byte Byte; + struct { + byte INITRQ :1; /* Initialization Mode Request */ + byte SLPRQ :1; /* Sleep Mode Request */ + byte WUPE :1; /* Wake-Up Enable */ + byte TIME :1; /* Timer Enable */ + byte SYNCH :1; /* Synchronized Status */ + byte CSWAI :1; /* CAN Stops in Wait Mode */ + byte RXACT :1; /* Receiver Active Status */ + byte RXFRM :1; /* Received Frame Flag */ + } Bits; +} CAN3CTL0STR; +extern volatile CAN3CTL0STR _CAN3CTL0 @(REG_BASE + 0x00000200); +#define CAN3CTL0 _CAN3CTL0.Byte +#define CAN3CTL0_INITRQ _CAN3CTL0.Bits.INITRQ +#define CAN3CTL0_SLPRQ _CAN3CTL0.Bits.SLPRQ +#define CAN3CTL0_WUPE _CAN3CTL0.Bits.WUPE +#define CAN3CTL0_TIME _CAN3CTL0.Bits.TIME +#define CAN3CTL0_SYNCH _CAN3CTL0.Bits.SYNCH +#define CAN3CTL0_CSWAI _CAN3CTL0.Bits.CSWAI +#define CAN3CTL0_RXACT _CAN3CTL0.Bits.RXACT +#define CAN3CTL0_RXFRM _CAN3CTL0.Bits.RXFRM + + +/*** CAN3CTL1 - MSCAN 3 Control 1 Register; 0x00000201 ***/ +typedef union { + byte Byte; + struct { + byte INITAK :1; /* Initialization Mode Acknowledge */ + byte SLPAK :1; /* Sleep Mode Acknowledge */ + byte WUPM :1; /* Wake-Up Mode */ + byte :1; + byte LISTEN :1; /* Listen Only Mode */ + byte LOOPB :1; /* Loop Back Self Test Mode */ + byte CLKSRC :1; /* MSCAN 3 Clock Source */ + byte CANE :1; /* MSCAN 3 Enable */ + } Bits; +} CAN3CTL1STR; +extern volatile CAN3CTL1STR _CAN3CTL1 @(REG_BASE + 0x00000201); +#define CAN3CTL1 _CAN3CTL1.Byte +#define CAN3CTL1_INITAK _CAN3CTL1.Bits.INITAK +#define CAN3CTL1_SLPAK _CAN3CTL1.Bits.SLPAK +#define CAN3CTL1_WUPM _CAN3CTL1.Bits.WUPM +#define CAN3CTL1_LISTEN _CAN3CTL1.Bits.LISTEN +#define CAN3CTL1_LOOPB _CAN3CTL1.Bits.LOOPB +#define CAN3CTL1_CLKSRC _CAN3CTL1.Bits.CLKSRC +#define CAN3CTL1_CANE _CAN3CTL1.Bits.CANE + + +/*** CAN3BTR0 - MSCAN 3 Bus Timing Register 0; 0x00000202 ***/ +typedef union { + byte Byte; + struct { + byte BRP0 :1; /* Baud Rate Prescaler 0 */ + byte BRP1 :1; /* Baud Rate Prescaler 1 */ + byte BRP2 :1; /* Baud Rate Prescaler 2 */ + byte BRP3 :1; /* Baud Rate Prescaler 3 */ + byte BRP4 :1; /* Baud Rate Prescaler 4 */ + byte BRP5 :1; /* Baud Rate Prescaler 5 */ + byte SJW0 :1; /* Synchronization Jump Width 0 */ + byte SJW1 :1; /* Synchronization Jump Width 1 */ + } Bits; + struct { + byte grpBRP :6; + byte grpSJW :2; + } MergedBits; +} CAN3BTR0STR; +extern volatile CAN3BTR0STR _CAN3BTR0 @(REG_BASE + 0x00000202); +#define CAN3BTR0 _CAN3BTR0.Byte +#define CAN3BTR0_BRP0 _CAN3BTR0.Bits.BRP0 +#define CAN3BTR0_BRP1 _CAN3BTR0.Bits.BRP1 +#define CAN3BTR0_BRP2 _CAN3BTR0.Bits.BRP2 +#define CAN3BTR0_BRP3 _CAN3BTR0.Bits.BRP3 +#define CAN3BTR0_BRP4 _CAN3BTR0.Bits.BRP4 +#define CAN3BTR0_BRP5 _CAN3BTR0.Bits.BRP5 +#define CAN3BTR0_SJW0 _CAN3BTR0.Bits.SJW0 +#define CAN3BTR0_SJW1 _CAN3BTR0.Bits.SJW1 +#define CAN3BTR0_BRP _CAN3BTR0.MergedBits.grpBRP +#define CAN3BTR0_SJW _CAN3BTR0.MergedBits.grpSJW + + +/*** CAN3BTR1 - MSCAN 3 Bus Timing Register 1; 0x00000203 ***/ +typedef union { + byte Byte; + struct { + byte TSEG10 :1; /* Time Segment 1 */ + byte TSEG11 :1; /* Time Segment 1 */ + byte TSEG12 :1; /* Time Segment 1 */ + byte TSEG13 :1; /* Time Segment 1 */ + byte TSEG20 :1; /* Time Segment 2 */ + byte TSEG21 :1; /* Time Segment 2 */ + byte TSEG22 :1; /* Time Segment 2 */ + byte SAMP :1; /* Sampling */ + } Bits; + struct { + byte grpTSEG_10 :4; + byte grpTSEG_20 :3; + byte :1; + } MergedBits; +} CAN3BTR1STR; +extern volatile CAN3BTR1STR _CAN3BTR1 @(REG_BASE + 0x00000203); +#define CAN3BTR1 _CAN3BTR1.Byte +#define CAN3BTR1_TSEG10 _CAN3BTR1.Bits.TSEG10 +#define CAN3BTR1_TSEG11 _CAN3BTR1.Bits.TSEG11 +#define CAN3BTR1_TSEG12 _CAN3BTR1.Bits.TSEG12 +#define CAN3BTR1_TSEG13 _CAN3BTR1.Bits.TSEG13 +#define CAN3BTR1_TSEG20 _CAN3BTR1.Bits.TSEG20 +#define CAN3BTR1_TSEG21 _CAN3BTR1.Bits.TSEG21 +#define CAN3BTR1_TSEG22 _CAN3BTR1.Bits.TSEG22 +#define CAN3BTR1_SAMP _CAN3BTR1.Bits.SAMP +#define CAN3BTR1_TSEG_10 _CAN3BTR1.MergedBits.grpTSEG_10 +#define CAN3BTR1_TSEG_20 _CAN3BTR1.MergedBits.grpTSEG_20 +#define CAN3BTR1_TSEG CAN3BTR1_TSEG_10 + + +/*** CAN3RFLG - MSCAN 3 Receiver Flag Register; 0x00000204 ***/ +typedef union { + byte Byte; + struct { + byte RXF :1; /* Receive Buffer Full */ + byte OVRIF :1; /* Overrun Interrupt Flag */ + byte TSTAT0 :1; /* Transmitter Status Bit 0 */ + byte TSTAT1 :1; /* Transmitter Status Bit 1 */ + byte RSTAT0 :1; /* Receiver Status Bit 0 */ + byte RSTAT1 :1; /* Receiver Status Bit 1 */ + byte CSCIF :1; /* CAN Status Change Interrupt Flag */ + byte WUPIF :1; /* Wake-up Interrupt Flag */ + } Bits; + struct { + byte :1; + byte :1; + byte grpTSTAT :2; + byte grpRSTAT :2; + byte :1; + byte :1; + } MergedBits; +} CAN3RFLGSTR; +extern volatile CAN3RFLGSTR _CAN3RFLG @(REG_BASE + 0x00000204); +#define CAN3RFLG _CAN3RFLG.Byte +#define CAN3RFLG_RXF _CAN3RFLG.Bits.RXF +#define CAN3RFLG_OVRIF _CAN3RFLG.Bits.OVRIF +#define CAN3RFLG_TSTAT0 _CAN3RFLG.Bits.TSTAT0 +#define CAN3RFLG_TSTAT1 _CAN3RFLG.Bits.TSTAT1 +#define CAN3RFLG_RSTAT0 _CAN3RFLG.Bits.RSTAT0 +#define CAN3RFLG_RSTAT1 _CAN3RFLG.Bits.RSTAT1 +#define CAN3RFLG_CSCIF _CAN3RFLG.Bits.CSCIF +#define CAN3RFLG_WUPIF _CAN3RFLG.Bits.WUPIF +#define CAN3RFLG_TSTAT _CAN3RFLG.MergedBits.grpTSTAT +#define CAN3RFLG_RSTAT _CAN3RFLG.MergedBits.grpRSTAT + + +/*** CAN3RIER - MSCAN 3 Receiver Interrupt Enable Register; 0x00000205 ***/ +typedef union { + byte Byte; + struct { + byte RXFIE :1; /* Receiver Full Interrupt Enable */ + byte OVRIE :1; /* Overrun Interrupt Enable */ + byte TSTATE0 :1; /* Transmitter Status Change Enable 0 */ + byte TSTATE1 :1; /* Transmitter Status Change Enable 1 */ + byte RSTATE0 :1; /* Receiver Status Change Enable 0 */ + byte RSTATE1 :1; /* Receiver Status Change Enable 1 */ + byte CSCIE :1; /* CAN Status Change Interrupt Enable */ + byte WUPIE :1; /* Wake-up Interrupt Enable */ + } Bits; + struct { + byte :1; + byte :1; + byte grpTSTATE :2; + byte grpRSTATE :2; + byte :1; + byte :1; + } MergedBits; +} CAN3RIERSTR; +extern volatile CAN3RIERSTR _CAN3RIER @(REG_BASE + 0x00000205); +#define CAN3RIER _CAN3RIER.Byte +#define CAN3RIER_RXFIE _CAN3RIER.Bits.RXFIE +#define CAN3RIER_OVRIE _CAN3RIER.Bits.OVRIE +#define CAN3RIER_TSTATE0 _CAN3RIER.Bits.TSTATE0 +#define CAN3RIER_TSTATE1 _CAN3RIER.Bits.TSTATE1 +#define CAN3RIER_RSTATE0 _CAN3RIER.Bits.RSTATE0 +#define CAN3RIER_RSTATE1 _CAN3RIER.Bits.RSTATE1 +#define CAN3RIER_CSCIE _CAN3RIER.Bits.CSCIE +#define CAN3RIER_WUPIE _CAN3RIER.Bits.WUPIE +#define CAN3RIER_TSTATE _CAN3RIER.MergedBits.grpTSTATE +#define CAN3RIER_RSTATE _CAN3RIER.MergedBits.grpRSTATE + + +/*** CAN3TFLG - MSCAN 3 Transmitter Flag Register; 0x00000206 ***/ +typedef union { + byte Byte; + struct { + byte TXE0 :1; /* Transmitter Buffer Empty 0 */ + byte TXE1 :1; /* Transmitter Buffer Empty 1 */ + byte TXE2 :1; /* Transmitter Buffer Empty 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpTXE :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN3TFLGSTR; +extern volatile CAN3TFLGSTR _CAN3TFLG @(REG_BASE + 0x00000206); +#define CAN3TFLG _CAN3TFLG.Byte +#define CAN3TFLG_TXE0 _CAN3TFLG.Bits.TXE0 +#define CAN3TFLG_TXE1 _CAN3TFLG.Bits.TXE1 +#define CAN3TFLG_TXE2 _CAN3TFLG.Bits.TXE2 +#define CAN3TFLG_TXE _CAN3TFLG.MergedBits.grpTXE + + +/*** CAN3TIER - MSCAN 3 Transmitter Interrupt Enable Register; 0x00000207 ***/ +typedef union { + byte Byte; + struct { + byte TXEIE0 :1; /* Transmitter Empty Interrupt Enable 0 */ + byte TXEIE1 :1; /* Transmitter Empty Interrupt Enable 1 */ + byte TXEIE2 :1; /* Transmitter Empty Interrupt Enable 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpTXEIE :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN3TIERSTR; +extern volatile CAN3TIERSTR _CAN3TIER @(REG_BASE + 0x00000207); +#define CAN3TIER _CAN3TIER.Byte +#define CAN3TIER_TXEIE0 _CAN3TIER.Bits.TXEIE0 +#define CAN3TIER_TXEIE1 _CAN3TIER.Bits.TXEIE1 +#define CAN3TIER_TXEIE2 _CAN3TIER.Bits.TXEIE2 +#define CAN3TIER_TXEIE _CAN3TIER.MergedBits.grpTXEIE + + +/*** CAN3TARQ - MSCAN 3 Transmitter Message Abort Request; 0x00000208 ***/ +typedef union { + byte Byte; + struct { + byte ABTRQ0 :1; /* Abort Request 0 */ + byte ABTRQ1 :1; /* Abort Request 1 */ + byte ABTRQ2 :1; /* Abort Request 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpABTRQ :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN3TARQSTR; +extern volatile CAN3TARQSTR _CAN3TARQ @(REG_BASE + 0x00000208); +#define CAN3TARQ _CAN3TARQ.Byte +#define CAN3TARQ_ABTRQ0 _CAN3TARQ.Bits.ABTRQ0 +#define CAN3TARQ_ABTRQ1 _CAN3TARQ.Bits.ABTRQ1 +#define CAN3TARQ_ABTRQ2 _CAN3TARQ.Bits.ABTRQ2 +#define CAN3TARQ_ABTRQ _CAN3TARQ.MergedBits.grpABTRQ + + +/*** CAN3TAAK - MSCAN 3 Transmitter Message Abort Control; 0x00000209 ***/ +typedef union { + byte Byte; + struct { + byte ABTAK0 :1; /* Abort Acknowledge 0 */ + byte ABTAK1 :1; /* Abort Acknowledge 1 */ + byte ABTAK2 :1; /* Abort Acknowledge 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpABTAK :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN3TAAKSTR; +extern volatile CAN3TAAKSTR _CAN3TAAK @(REG_BASE + 0x00000209); +#define CAN3TAAK _CAN3TAAK.Byte +#define CAN3TAAK_ABTAK0 _CAN3TAAK.Bits.ABTAK0 +#define CAN3TAAK_ABTAK1 _CAN3TAAK.Bits.ABTAK1 +#define CAN3TAAK_ABTAK2 _CAN3TAAK.Bits.ABTAK2 +#define CAN3TAAK_ABTAK _CAN3TAAK.MergedBits.grpABTAK + + +/*** CAN3TBSEL - MSCAN 3 Transmit Buffer Selection; 0x0000020A ***/ +typedef union { + byte Byte; + struct { + byte TX0 :1; /* Transmit Buffer Select 0 */ + byte TX1 :1; /* Transmit Buffer Select 1 */ + byte TX2 :1; /* Transmit Buffer Select 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpTX :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN3TBSELSTR; +extern volatile CAN3TBSELSTR _CAN3TBSEL @(REG_BASE + 0x0000020A); +#define CAN3TBSEL _CAN3TBSEL.Byte +#define CAN3TBSEL_TX0 _CAN3TBSEL.Bits.TX0 +#define CAN3TBSEL_TX1 _CAN3TBSEL.Bits.TX1 +#define CAN3TBSEL_TX2 _CAN3TBSEL.Bits.TX2 +#define CAN3TBSEL_TX _CAN3TBSEL.MergedBits.grpTX + + +/*** CAN3IDAC - MSCAN 3 Identifier Acceptance Control Register; 0x0000020B ***/ +typedef union { + byte Byte; + struct { + byte IDHIT0 :1; /* Identifier Acceptance Hit Indicator 0 */ + byte IDHIT1 :1; /* Identifier Acceptance Hit Indicator 1 */ + byte IDHIT2 :1; /* Identifier Acceptance Hit Indicator 2 */ + byte :1; + byte IDAM0 :1; /* Identifier Acceptance Mode 0 */ + byte IDAM1 :1; /* Identifier Acceptance Mode 1 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpIDHIT :3; + byte :1; + byte grpIDAM :2; + byte :1; + byte :1; + } MergedBits; +} CAN3IDACSTR; +extern volatile CAN3IDACSTR _CAN3IDAC @(REG_BASE + 0x0000020B); +#define CAN3IDAC _CAN3IDAC.Byte +#define CAN3IDAC_IDHIT0 _CAN3IDAC.Bits.IDHIT0 +#define CAN3IDAC_IDHIT1 _CAN3IDAC.Bits.IDHIT1 +#define CAN3IDAC_IDHIT2 _CAN3IDAC.Bits.IDHIT2 +#define CAN3IDAC_IDAM0 _CAN3IDAC.Bits.IDAM0 +#define CAN3IDAC_IDAM1 _CAN3IDAC.Bits.IDAM1 +#define CAN3IDAC_IDHIT _CAN3IDAC.MergedBits.grpIDHIT +#define CAN3IDAC_IDAM _CAN3IDAC.MergedBits.grpIDAM + + +/*** CAN3RXERR - MSCAN 3 Receive Error Counter Register; 0x0000020E ***/ +typedef union { + byte Byte; + struct { + byte RXERR0 :1; /* Bit 0 */ + byte RXERR1 :1; /* Bit 1 */ + byte RXERR2 :1; /* Bit 2 */ + byte RXERR3 :1; /* Bit 3 */ + byte RXERR4 :1; /* Bit 4 */ + byte RXERR5 :1; /* Bit 5 */ + byte RXERR6 :1; /* Bit 6 */ + byte RXERR7 :1; /* Bit 7 */ + } Bits; + struct { + byte grpRXERR :8; + } MergedBits; +} CAN3RXERRSTR; +extern volatile CAN3RXERRSTR _CAN3RXERR @(REG_BASE + 0x0000020E); +#define CAN3RXERR _CAN3RXERR.Byte +#define CAN3RXERR_RXERR0 _CAN3RXERR.Bits.RXERR0 +#define CAN3RXERR_RXERR1 _CAN3RXERR.Bits.RXERR1 +#define CAN3RXERR_RXERR2 _CAN3RXERR.Bits.RXERR2 +#define CAN3RXERR_RXERR3 _CAN3RXERR.Bits.RXERR3 +#define CAN3RXERR_RXERR4 _CAN3RXERR.Bits.RXERR4 +#define CAN3RXERR_RXERR5 _CAN3RXERR.Bits.RXERR5 +#define CAN3RXERR_RXERR6 _CAN3RXERR.Bits.RXERR6 +#define CAN3RXERR_RXERR7 _CAN3RXERR.Bits.RXERR7 +#define CAN3RXERR_RXERR _CAN3RXERR.MergedBits.grpRXERR + + +/*** CAN3TXERR - MSCAN 3 Transmit Error Counter Register; 0x0000020F ***/ +typedef union { + byte Byte; + struct { + byte TXERR0 :1; /* Bit 0 */ + byte TXERR1 :1; /* Bit 1 */ + byte TXERR2 :1; /* Bit 2 */ + byte TXERR3 :1; /* Bit 3 */ + byte TXERR4 :1; /* Bit 4 */ + byte TXERR5 :1; /* Bit 5 */ + byte TXERR6 :1; /* Bit 6 */ + byte TXERR7 :1; /* Bit 7 */ + } Bits; + struct { + byte grpTXERR :8; + } MergedBits; +} CAN3TXERRSTR; +extern volatile CAN3TXERRSTR _CAN3TXERR @(REG_BASE + 0x0000020F); +#define CAN3TXERR _CAN3TXERR.Byte +#define CAN3TXERR_TXERR0 _CAN3TXERR.Bits.TXERR0 +#define CAN3TXERR_TXERR1 _CAN3TXERR.Bits.TXERR1 +#define CAN3TXERR_TXERR2 _CAN3TXERR.Bits.TXERR2 +#define CAN3TXERR_TXERR3 _CAN3TXERR.Bits.TXERR3 +#define CAN3TXERR_TXERR4 _CAN3TXERR.Bits.TXERR4 +#define CAN3TXERR_TXERR5 _CAN3TXERR.Bits.TXERR5 +#define CAN3TXERR_TXERR6 _CAN3TXERR.Bits.TXERR6 +#define CAN3TXERR_TXERR7 _CAN3TXERR.Bits.TXERR7 +#define CAN3TXERR_TXERR _CAN3TXERR.MergedBits.grpTXERR + + +/*** CAN3IDAR0 - MSCAN 3 Identifier Acceptance Register 0; 0x00000210 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN3IDAR0STR; +extern volatile CAN3IDAR0STR _CAN3IDAR0 @(REG_BASE + 0x00000210); +#define CAN3IDAR0 _CAN3IDAR0.Byte +#define CAN3IDAR0_AC0 _CAN3IDAR0.Bits.AC0 +#define CAN3IDAR0_AC1 _CAN3IDAR0.Bits.AC1 +#define CAN3IDAR0_AC2 _CAN3IDAR0.Bits.AC2 +#define CAN3IDAR0_AC3 _CAN3IDAR0.Bits.AC3 +#define CAN3IDAR0_AC4 _CAN3IDAR0.Bits.AC4 +#define CAN3IDAR0_AC5 _CAN3IDAR0.Bits.AC5 +#define CAN3IDAR0_AC6 _CAN3IDAR0.Bits.AC6 +#define CAN3IDAR0_AC7 _CAN3IDAR0.Bits.AC7 +#define CAN3IDAR0_AC _CAN3IDAR0.MergedBits.grpAC + + +/*** CAN3IDAR1 - MSCAN 3 Identifier Acceptance Register 1; 0x00000211 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN3IDAR1STR; +extern volatile CAN3IDAR1STR _CAN3IDAR1 @(REG_BASE + 0x00000211); +#define CAN3IDAR1 _CAN3IDAR1.Byte +#define CAN3IDAR1_AC0 _CAN3IDAR1.Bits.AC0 +#define CAN3IDAR1_AC1 _CAN3IDAR1.Bits.AC1 +#define CAN3IDAR1_AC2 _CAN3IDAR1.Bits.AC2 +#define CAN3IDAR1_AC3 _CAN3IDAR1.Bits.AC3 +#define CAN3IDAR1_AC4 _CAN3IDAR1.Bits.AC4 +#define CAN3IDAR1_AC5 _CAN3IDAR1.Bits.AC5 +#define CAN3IDAR1_AC6 _CAN3IDAR1.Bits.AC6 +#define CAN3IDAR1_AC7 _CAN3IDAR1.Bits.AC7 +#define CAN3IDAR1_AC _CAN3IDAR1.MergedBits.grpAC + + +/*** CAN3IDAR2 - MSCAN 3 Identifier Acceptance Register 2; 0x00000212 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN3IDAR2STR; +extern volatile CAN3IDAR2STR _CAN3IDAR2 @(REG_BASE + 0x00000212); +#define CAN3IDAR2 _CAN3IDAR2.Byte +#define CAN3IDAR2_AC0 _CAN3IDAR2.Bits.AC0 +#define CAN3IDAR2_AC1 _CAN3IDAR2.Bits.AC1 +#define CAN3IDAR2_AC2 _CAN3IDAR2.Bits.AC2 +#define CAN3IDAR2_AC3 _CAN3IDAR2.Bits.AC3 +#define CAN3IDAR2_AC4 _CAN3IDAR2.Bits.AC4 +#define CAN3IDAR2_AC5 _CAN3IDAR2.Bits.AC5 +#define CAN3IDAR2_AC6 _CAN3IDAR2.Bits.AC6 +#define CAN3IDAR2_AC7 _CAN3IDAR2.Bits.AC7 +#define CAN3IDAR2_AC _CAN3IDAR2.MergedBits.grpAC + + +/*** CAN3IDAR3 - MSCAN 3 Identifier Acceptance Register 3; 0x00000213 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN3IDAR3STR; +extern volatile CAN3IDAR3STR _CAN3IDAR3 @(REG_BASE + 0x00000213); +#define CAN3IDAR3 _CAN3IDAR3.Byte +#define CAN3IDAR3_AC0 _CAN3IDAR3.Bits.AC0 +#define CAN3IDAR3_AC1 _CAN3IDAR3.Bits.AC1 +#define CAN3IDAR3_AC2 _CAN3IDAR3.Bits.AC2 +#define CAN3IDAR3_AC3 _CAN3IDAR3.Bits.AC3 +#define CAN3IDAR3_AC4 _CAN3IDAR3.Bits.AC4 +#define CAN3IDAR3_AC5 _CAN3IDAR3.Bits.AC5 +#define CAN3IDAR3_AC6 _CAN3IDAR3.Bits.AC6 +#define CAN3IDAR3_AC7 _CAN3IDAR3.Bits.AC7 +#define CAN3IDAR3_AC _CAN3IDAR3.MergedBits.grpAC + + +/*** CAN3IDMR0 - MSCAN 3 Identifier Mask Register 0; 0x00000214 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN3IDMR0STR; +extern volatile CAN3IDMR0STR _CAN3IDMR0 @(REG_BASE + 0x00000214); +#define CAN3IDMR0 _CAN3IDMR0.Byte +#define CAN3IDMR0_AM0 _CAN3IDMR0.Bits.AM0 +#define CAN3IDMR0_AM1 _CAN3IDMR0.Bits.AM1 +#define CAN3IDMR0_AM2 _CAN3IDMR0.Bits.AM2 +#define CAN3IDMR0_AM3 _CAN3IDMR0.Bits.AM3 +#define CAN3IDMR0_AM4 _CAN3IDMR0.Bits.AM4 +#define CAN3IDMR0_AM5 _CAN3IDMR0.Bits.AM5 +#define CAN3IDMR0_AM6 _CAN3IDMR0.Bits.AM6 +#define CAN3IDMR0_AM7 _CAN3IDMR0.Bits.AM7 +#define CAN3IDMR0_AM _CAN3IDMR0.MergedBits.grpAM + + +/*** CAN3IDMR1 - MSCAN 3 Identifier Mask Register 1; 0x00000215 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN3IDMR1STR; +extern volatile CAN3IDMR1STR _CAN3IDMR1 @(REG_BASE + 0x00000215); +#define CAN3IDMR1 _CAN3IDMR1.Byte +#define CAN3IDMR1_AM0 _CAN3IDMR1.Bits.AM0 +#define CAN3IDMR1_AM1 _CAN3IDMR1.Bits.AM1 +#define CAN3IDMR1_AM2 _CAN3IDMR1.Bits.AM2 +#define CAN3IDMR1_AM3 _CAN3IDMR1.Bits.AM3 +#define CAN3IDMR1_AM4 _CAN3IDMR1.Bits.AM4 +#define CAN3IDMR1_AM5 _CAN3IDMR1.Bits.AM5 +#define CAN3IDMR1_AM6 _CAN3IDMR1.Bits.AM6 +#define CAN3IDMR1_AM7 _CAN3IDMR1.Bits.AM7 +#define CAN3IDMR1_AM _CAN3IDMR1.MergedBits.grpAM + + +/*** CAN3IDMR2 - MSCAN 3 Identifier Mask Register 2; 0x00000216 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN3IDMR2STR; +extern volatile CAN3IDMR2STR _CAN3IDMR2 @(REG_BASE + 0x00000216); +#define CAN3IDMR2 _CAN3IDMR2.Byte +#define CAN3IDMR2_AM0 _CAN3IDMR2.Bits.AM0 +#define CAN3IDMR2_AM1 _CAN3IDMR2.Bits.AM1 +#define CAN3IDMR2_AM2 _CAN3IDMR2.Bits.AM2 +#define CAN3IDMR2_AM3 _CAN3IDMR2.Bits.AM3 +#define CAN3IDMR2_AM4 _CAN3IDMR2.Bits.AM4 +#define CAN3IDMR2_AM5 _CAN3IDMR2.Bits.AM5 +#define CAN3IDMR2_AM6 _CAN3IDMR2.Bits.AM6 +#define CAN3IDMR2_AM7 _CAN3IDMR2.Bits.AM7 +#define CAN3IDMR2_AM _CAN3IDMR2.MergedBits.grpAM + + +/*** CAN3IDMR3 - MSCAN 3 Identifier Mask Register 3; 0x00000217 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN3IDMR3STR; +extern volatile CAN3IDMR3STR _CAN3IDMR3 @(REG_BASE + 0x00000217); +#define CAN3IDMR3 _CAN3IDMR3.Byte +#define CAN3IDMR3_AM0 _CAN3IDMR3.Bits.AM0 +#define CAN3IDMR3_AM1 _CAN3IDMR3.Bits.AM1 +#define CAN3IDMR3_AM2 _CAN3IDMR3.Bits.AM2 +#define CAN3IDMR3_AM3 _CAN3IDMR3.Bits.AM3 +#define CAN3IDMR3_AM4 _CAN3IDMR3.Bits.AM4 +#define CAN3IDMR3_AM5 _CAN3IDMR3.Bits.AM5 +#define CAN3IDMR3_AM6 _CAN3IDMR3.Bits.AM6 +#define CAN3IDMR3_AM7 _CAN3IDMR3.Bits.AM7 +#define CAN3IDMR3_AM _CAN3IDMR3.MergedBits.grpAM + + +/*** CAN3IDAR4 - MSCAN 3 Identifier Acceptance Register 4; 0x00000218 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN3IDAR4STR; +extern volatile CAN3IDAR4STR _CAN3IDAR4 @(REG_BASE + 0x00000218); +#define CAN3IDAR4 _CAN3IDAR4.Byte +#define CAN3IDAR4_AC0 _CAN3IDAR4.Bits.AC0 +#define CAN3IDAR4_AC1 _CAN3IDAR4.Bits.AC1 +#define CAN3IDAR4_AC2 _CAN3IDAR4.Bits.AC2 +#define CAN3IDAR4_AC3 _CAN3IDAR4.Bits.AC3 +#define CAN3IDAR4_AC4 _CAN3IDAR4.Bits.AC4 +#define CAN3IDAR4_AC5 _CAN3IDAR4.Bits.AC5 +#define CAN3IDAR4_AC6 _CAN3IDAR4.Bits.AC6 +#define CAN3IDAR4_AC7 _CAN3IDAR4.Bits.AC7 +#define CAN3IDAR4_AC _CAN3IDAR4.MergedBits.grpAC + + +/*** CAN3IDAR5 - MSCAN 3 Identifier Acceptance Register 5; 0x00000219 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN3IDAR5STR; +extern volatile CAN3IDAR5STR _CAN3IDAR5 @(REG_BASE + 0x00000219); +#define CAN3IDAR5 _CAN3IDAR5.Byte +#define CAN3IDAR5_AC0 _CAN3IDAR5.Bits.AC0 +#define CAN3IDAR5_AC1 _CAN3IDAR5.Bits.AC1 +#define CAN3IDAR5_AC2 _CAN3IDAR5.Bits.AC2 +#define CAN3IDAR5_AC3 _CAN3IDAR5.Bits.AC3 +#define CAN3IDAR5_AC4 _CAN3IDAR5.Bits.AC4 +#define CAN3IDAR5_AC5 _CAN3IDAR5.Bits.AC5 +#define CAN3IDAR5_AC6 _CAN3IDAR5.Bits.AC6 +#define CAN3IDAR5_AC7 _CAN3IDAR5.Bits.AC7 +#define CAN3IDAR5_AC _CAN3IDAR5.MergedBits.grpAC + + +/*** CAN3IDAR6 - MSCAN 3 Identifier Acceptance Register 6; 0x0000021A ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN3IDAR6STR; +extern volatile CAN3IDAR6STR _CAN3IDAR6 @(REG_BASE + 0x0000021A); +#define CAN3IDAR6 _CAN3IDAR6.Byte +#define CAN3IDAR6_AC0 _CAN3IDAR6.Bits.AC0 +#define CAN3IDAR6_AC1 _CAN3IDAR6.Bits.AC1 +#define CAN3IDAR6_AC2 _CAN3IDAR6.Bits.AC2 +#define CAN3IDAR6_AC3 _CAN3IDAR6.Bits.AC3 +#define CAN3IDAR6_AC4 _CAN3IDAR6.Bits.AC4 +#define CAN3IDAR6_AC5 _CAN3IDAR6.Bits.AC5 +#define CAN3IDAR6_AC6 _CAN3IDAR6.Bits.AC6 +#define CAN3IDAR6_AC7 _CAN3IDAR6.Bits.AC7 +#define CAN3IDAR6_AC _CAN3IDAR6.MergedBits.grpAC + + +/*** CAN3IDAR7 - MSCAN 3 Identifier Acceptance Register 7; 0x0000021B ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN3IDAR7STR; +extern volatile CAN3IDAR7STR _CAN3IDAR7 @(REG_BASE + 0x0000021B); +#define CAN3IDAR7 _CAN3IDAR7.Byte +#define CAN3IDAR7_AC0 _CAN3IDAR7.Bits.AC0 +#define CAN3IDAR7_AC1 _CAN3IDAR7.Bits.AC1 +#define CAN3IDAR7_AC2 _CAN3IDAR7.Bits.AC2 +#define CAN3IDAR7_AC3 _CAN3IDAR7.Bits.AC3 +#define CAN3IDAR7_AC4 _CAN3IDAR7.Bits.AC4 +#define CAN3IDAR7_AC5 _CAN3IDAR7.Bits.AC5 +#define CAN3IDAR7_AC6 _CAN3IDAR7.Bits.AC6 +#define CAN3IDAR7_AC7 _CAN3IDAR7.Bits.AC7 +#define CAN3IDAR7_AC _CAN3IDAR7.MergedBits.grpAC + + +/*** CAN3IDMR4 - MSCAN 3 Identifier Mask Register 4; 0x0000021C ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN3IDMR4STR; +extern volatile CAN3IDMR4STR _CAN3IDMR4 @(REG_BASE + 0x0000021C); +#define CAN3IDMR4 _CAN3IDMR4.Byte +#define CAN3IDMR4_AM0 _CAN3IDMR4.Bits.AM0 +#define CAN3IDMR4_AM1 _CAN3IDMR4.Bits.AM1 +#define CAN3IDMR4_AM2 _CAN3IDMR4.Bits.AM2 +#define CAN3IDMR4_AM3 _CAN3IDMR4.Bits.AM3 +#define CAN3IDMR4_AM4 _CAN3IDMR4.Bits.AM4 +#define CAN3IDMR4_AM5 _CAN3IDMR4.Bits.AM5 +#define CAN3IDMR4_AM6 _CAN3IDMR4.Bits.AM6 +#define CAN3IDMR4_AM7 _CAN3IDMR4.Bits.AM7 +#define CAN3IDMR4_AM _CAN3IDMR4.MergedBits.grpAM + + +/*** CAN3IDMR5 - MSCAN 3 Identifier Mask Register 5; 0x0000021D ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN3IDMR5STR; +extern volatile CAN3IDMR5STR _CAN3IDMR5 @(REG_BASE + 0x0000021D); +#define CAN3IDMR5 _CAN3IDMR5.Byte +#define CAN3IDMR5_AM0 _CAN3IDMR5.Bits.AM0 +#define CAN3IDMR5_AM1 _CAN3IDMR5.Bits.AM1 +#define CAN3IDMR5_AM2 _CAN3IDMR5.Bits.AM2 +#define CAN3IDMR5_AM3 _CAN3IDMR5.Bits.AM3 +#define CAN3IDMR5_AM4 _CAN3IDMR5.Bits.AM4 +#define CAN3IDMR5_AM5 _CAN3IDMR5.Bits.AM5 +#define CAN3IDMR5_AM6 _CAN3IDMR5.Bits.AM6 +#define CAN3IDMR5_AM7 _CAN3IDMR5.Bits.AM7 +#define CAN3IDMR5_AM _CAN3IDMR5.MergedBits.grpAM + + +/*** CAN3IDMR6 - MSCAN 3 Identifier Mask Register 6; 0x0000021E ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN3IDMR6STR; +extern volatile CAN3IDMR6STR _CAN3IDMR6 @(REG_BASE + 0x0000021E); +#define CAN3IDMR6 _CAN3IDMR6.Byte +#define CAN3IDMR6_AM0 _CAN3IDMR6.Bits.AM0 +#define CAN3IDMR6_AM1 _CAN3IDMR6.Bits.AM1 +#define CAN3IDMR6_AM2 _CAN3IDMR6.Bits.AM2 +#define CAN3IDMR6_AM3 _CAN3IDMR6.Bits.AM3 +#define CAN3IDMR6_AM4 _CAN3IDMR6.Bits.AM4 +#define CAN3IDMR6_AM5 _CAN3IDMR6.Bits.AM5 +#define CAN3IDMR6_AM6 _CAN3IDMR6.Bits.AM6 +#define CAN3IDMR6_AM7 _CAN3IDMR6.Bits.AM7 +#define CAN3IDMR6_AM _CAN3IDMR6.MergedBits.grpAM + + +/*** CAN3IDMR7 - MSCAN 3 Identifier Mask Register 7; 0x0000021F ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN3IDMR7STR; +extern volatile CAN3IDMR7STR _CAN3IDMR7 @(REG_BASE + 0x0000021F); +#define CAN3IDMR7 _CAN3IDMR7.Byte +#define CAN3IDMR7_AM0 _CAN3IDMR7.Bits.AM0 +#define CAN3IDMR7_AM1 _CAN3IDMR7.Bits.AM1 +#define CAN3IDMR7_AM2 _CAN3IDMR7.Bits.AM2 +#define CAN3IDMR7_AM3 _CAN3IDMR7.Bits.AM3 +#define CAN3IDMR7_AM4 _CAN3IDMR7.Bits.AM4 +#define CAN3IDMR7_AM5 _CAN3IDMR7.Bits.AM5 +#define CAN3IDMR7_AM6 _CAN3IDMR7.Bits.AM6 +#define CAN3IDMR7_AM7 _CAN3IDMR7.Bits.AM7 +#define CAN3IDMR7_AM _CAN3IDMR7.MergedBits.grpAM + + +/*** CAN3RXIDR0 - MSCAN 3 Receive Identifier Register 0; 0x00000220 ***/ +typedef union { + byte Byte; + struct { + byte ID21 :1; /* Extended format identifier Bit 21 */ + byte ID22 :1; /* Extended format identifier Bit 22 */ + byte ID23 :1; /* Extended format identifier Bit 23 */ + byte ID24 :1; /* Extended format identifier Bit 24 */ + byte ID25 :1; /* Extended format identifier Bit 25 */ + byte ID26 :1; /* Extended format identifier Bit 26 */ + byte ID27 :1; /* Extended format identifier Bit 27 */ + byte ID28 :1; /* Extended format identifier Bit 28 */ + } Bits; + struct { + byte grpID_21 :8; + } MergedBits; +} CAN3RXIDR0STR; +extern volatile CAN3RXIDR0STR _CAN3RXIDR0 @(REG_BASE + 0x00000220); +#define CAN3RXIDR0 _CAN3RXIDR0.Byte +#define CAN3RXIDR0_ID21 _CAN3RXIDR0.Bits.ID21 +#define CAN3RXIDR0_ID22 _CAN3RXIDR0.Bits.ID22 +#define CAN3RXIDR0_ID23 _CAN3RXIDR0.Bits.ID23 +#define CAN3RXIDR0_ID24 _CAN3RXIDR0.Bits.ID24 +#define CAN3RXIDR0_ID25 _CAN3RXIDR0.Bits.ID25 +#define CAN3RXIDR0_ID26 _CAN3RXIDR0.Bits.ID26 +#define CAN3RXIDR0_ID27 _CAN3RXIDR0.Bits.ID27 +#define CAN3RXIDR0_ID28 _CAN3RXIDR0.Bits.ID28 +#define CAN3RXIDR0_ID_21 _CAN3RXIDR0.MergedBits.grpID_21 +#define CAN3RXIDR0_ID CAN3RXIDR0_ID_21 + + +/*** CAN3RXIDR1 - MSCAN 3 Receive Identifier Register 1; 0x00000221 ***/ +typedef union { + byte Byte; + struct { + byte ID15 :1; /* Extended format identifier Bit 15 */ + byte ID16 :1; /* Extended format identifier Bit 16 */ + byte ID17 :1; /* Extended format identifier Bit 17 */ + byte IDE :1; /* ID Extended */ + byte SRR :1; /* Substitute Remote Request */ + byte ID18 :1; /* Extended format identifier Bit 18 */ + byte ID19 :1; /* Extended format identifier Bit 19 */ + byte ID20 :1; /* Extended format identifier Bit 20 */ + } Bits; + struct { + byte grpID_15 :3; + byte :1; + byte :1; + byte grpID_18 :3; + } MergedBits; +} CAN3RXIDR1STR; +extern volatile CAN3RXIDR1STR _CAN3RXIDR1 @(REG_BASE + 0x00000221); +#define CAN3RXIDR1 _CAN3RXIDR1.Byte +#define CAN3RXIDR1_ID15 _CAN3RXIDR1.Bits.ID15 +#define CAN3RXIDR1_ID16 _CAN3RXIDR1.Bits.ID16 +#define CAN3RXIDR1_ID17 _CAN3RXIDR1.Bits.ID17 +#define CAN3RXIDR1_IDE _CAN3RXIDR1.Bits.IDE +#define CAN3RXIDR1_SRR _CAN3RXIDR1.Bits.SRR +#define CAN3RXIDR1_ID18 _CAN3RXIDR1.Bits.ID18 +#define CAN3RXIDR1_ID19 _CAN3RXIDR1.Bits.ID19 +#define CAN3RXIDR1_ID20 _CAN3RXIDR1.Bits.ID20 +#define CAN3RXIDR1_ID_15 _CAN3RXIDR1.MergedBits.grpID_15 +#define CAN3RXIDR1_ID_18 _CAN3RXIDR1.MergedBits.grpID_18 +#define CAN3RXIDR1_ID CAN3RXIDR1_ID_15 + + +/*** CAN3RXIDR2 - MSCAN 3 Receive Identifier Register 2; 0x00000222 ***/ +typedef union { + byte Byte; + struct { + byte ID7 :1; /* Extended format identifier Bit 7 */ + byte ID8 :1; /* Extended format identifier Bit 8 */ + byte ID9 :1; /* Extended format identifier Bit 9 */ + byte ID10 :1; /* Extended format identifier Bit 10 */ + byte ID11 :1; /* Extended format identifier Bit 11 */ + byte ID12 :1; /* Extended format identifier Bit 12 */ + byte ID13 :1; /* Extended format identifier Bit 13 */ + byte ID14 :1; /* Extended format identifier Bit 14 */ + } Bits; + struct { + byte grpID_7 :8; + } MergedBits; +} CAN3RXIDR2STR; +extern volatile CAN3RXIDR2STR _CAN3RXIDR2 @(REG_BASE + 0x00000222); +#define CAN3RXIDR2 _CAN3RXIDR2.Byte +#define CAN3RXIDR2_ID7 _CAN3RXIDR2.Bits.ID7 +#define CAN3RXIDR2_ID8 _CAN3RXIDR2.Bits.ID8 +#define CAN3RXIDR2_ID9 _CAN3RXIDR2.Bits.ID9 +#define CAN3RXIDR2_ID10 _CAN3RXIDR2.Bits.ID10 +#define CAN3RXIDR2_ID11 _CAN3RXIDR2.Bits.ID11 +#define CAN3RXIDR2_ID12 _CAN3RXIDR2.Bits.ID12 +#define CAN3RXIDR2_ID13 _CAN3RXIDR2.Bits.ID13 +#define CAN3RXIDR2_ID14 _CAN3RXIDR2.Bits.ID14 +#define CAN3RXIDR2_ID_7 _CAN3RXIDR2.MergedBits.grpID_7 +#define CAN3RXIDR2_ID CAN3RXIDR2_ID_7 + + +/*** CAN3RXIDR3 - MSCAN 3 Receive Identifier Register 3; 0x00000223 ***/ +typedef union { + byte Byte; + struct { + byte RTR :1; /* Remote Transmission Request */ + byte ID0 :1; /* Extended format identifier Bit 0 */ + byte ID1 :1; /* Extended format identifier Bit 1 */ + byte ID2 :1; /* Extended format identifier Bit 2 */ + byte ID3 :1; /* Extended format identifier Bit 3 */ + byte ID4 :1; /* Extended format identifier Bit 4 */ + byte ID5 :1; /* Extended format identifier Bit 5 */ + byte ID6 :1; /* Extended format identifier Bit 6 */ + } Bits; + struct { + byte :1; + byte grpID :7; + } MergedBits; +} CAN3RXIDR3STR; +extern volatile CAN3RXIDR3STR _CAN3RXIDR3 @(REG_BASE + 0x00000223); +#define CAN3RXIDR3 _CAN3RXIDR3.Byte +#define CAN3RXIDR3_RTR _CAN3RXIDR3.Bits.RTR +#define CAN3RXIDR3_ID0 _CAN3RXIDR3.Bits.ID0 +#define CAN3RXIDR3_ID1 _CAN3RXIDR3.Bits.ID1 +#define CAN3RXIDR3_ID2 _CAN3RXIDR3.Bits.ID2 +#define CAN3RXIDR3_ID3 _CAN3RXIDR3.Bits.ID3 +#define CAN3RXIDR3_ID4 _CAN3RXIDR3.Bits.ID4 +#define CAN3RXIDR3_ID5 _CAN3RXIDR3.Bits.ID5 +#define CAN3RXIDR3_ID6 _CAN3RXIDR3.Bits.ID6 +#define CAN3RXIDR3_ID _CAN3RXIDR3.MergedBits.grpID + + +/*** CAN3RXDSR0 - MSCAN 3 Receive Data Segment Register 0; 0x00000224 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN3RXDSR0STR; +extern volatile CAN3RXDSR0STR _CAN3RXDSR0 @(REG_BASE + 0x00000224); +#define CAN3RXDSR0 _CAN3RXDSR0.Byte +#define CAN3RXDSR0_DB0 _CAN3RXDSR0.Bits.DB0 +#define CAN3RXDSR0_DB1 _CAN3RXDSR0.Bits.DB1 +#define CAN3RXDSR0_DB2 _CAN3RXDSR0.Bits.DB2 +#define CAN3RXDSR0_DB3 _CAN3RXDSR0.Bits.DB3 +#define CAN3RXDSR0_DB4 _CAN3RXDSR0.Bits.DB4 +#define CAN3RXDSR0_DB5 _CAN3RXDSR0.Bits.DB5 +#define CAN3RXDSR0_DB6 _CAN3RXDSR0.Bits.DB6 +#define CAN3RXDSR0_DB7 _CAN3RXDSR0.Bits.DB7 +#define CAN3RXDSR0_DB _CAN3RXDSR0.MergedBits.grpDB + + +/*** CAN3RXDSR1 - MSCAN 3 Receive Data Segment Register 1; 0x00000225 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN3RXDSR1STR; +extern volatile CAN3RXDSR1STR _CAN3RXDSR1 @(REG_BASE + 0x00000225); +#define CAN3RXDSR1 _CAN3RXDSR1.Byte +#define CAN3RXDSR1_DB0 _CAN3RXDSR1.Bits.DB0 +#define CAN3RXDSR1_DB1 _CAN3RXDSR1.Bits.DB1 +#define CAN3RXDSR1_DB2 _CAN3RXDSR1.Bits.DB2 +#define CAN3RXDSR1_DB3 _CAN3RXDSR1.Bits.DB3 +#define CAN3RXDSR1_DB4 _CAN3RXDSR1.Bits.DB4 +#define CAN3RXDSR1_DB5 _CAN3RXDSR1.Bits.DB5 +#define CAN3RXDSR1_DB6 _CAN3RXDSR1.Bits.DB6 +#define CAN3RXDSR1_DB7 _CAN3RXDSR1.Bits.DB7 +#define CAN3RXDSR1_DB _CAN3RXDSR1.MergedBits.grpDB + + +/*** CAN3RXDSR2 - MSCAN 3 Receive Data Segment Register 2; 0x00000226 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN3RXDSR2STR; +extern volatile CAN3RXDSR2STR _CAN3RXDSR2 @(REG_BASE + 0x00000226); +#define CAN3RXDSR2 _CAN3RXDSR2.Byte +#define CAN3RXDSR2_DB0 _CAN3RXDSR2.Bits.DB0 +#define CAN3RXDSR2_DB1 _CAN3RXDSR2.Bits.DB1 +#define CAN3RXDSR2_DB2 _CAN3RXDSR2.Bits.DB2 +#define CAN3RXDSR2_DB3 _CAN3RXDSR2.Bits.DB3 +#define CAN3RXDSR2_DB4 _CAN3RXDSR2.Bits.DB4 +#define CAN3RXDSR2_DB5 _CAN3RXDSR2.Bits.DB5 +#define CAN3RXDSR2_DB6 _CAN3RXDSR2.Bits.DB6 +#define CAN3RXDSR2_DB7 _CAN3RXDSR2.Bits.DB7 +#define CAN3RXDSR2_DB _CAN3RXDSR2.MergedBits.grpDB + + +/*** CAN3RXDSR3 - MSCAN 3 Receive Data Segment Register 3; 0x00000227 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN3RXDSR3STR; +extern volatile CAN3RXDSR3STR _CAN3RXDSR3 @(REG_BASE + 0x00000227); +#define CAN3RXDSR3 _CAN3RXDSR3.Byte +#define CAN3RXDSR3_DB0 _CAN3RXDSR3.Bits.DB0 +#define CAN3RXDSR3_DB1 _CAN3RXDSR3.Bits.DB1 +#define CAN3RXDSR3_DB2 _CAN3RXDSR3.Bits.DB2 +#define CAN3RXDSR3_DB3 _CAN3RXDSR3.Bits.DB3 +#define CAN3RXDSR3_DB4 _CAN3RXDSR3.Bits.DB4 +#define CAN3RXDSR3_DB5 _CAN3RXDSR3.Bits.DB5 +#define CAN3RXDSR3_DB6 _CAN3RXDSR3.Bits.DB6 +#define CAN3RXDSR3_DB7 _CAN3RXDSR3.Bits.DB7 +#define CAN3RXDSR3_DB _CAN3RXDSR3.MergedBits.grpDB + + +/*** CAN3RXDSR4 - MSCAN 3 Receive Data Segment Register 4; 0x00000228 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN3RXDSR4STR; +extern volatile CAN3RXDSR4STR _CAN3RXDSR4 @(REG_BASE + 0x00000228); +#define CAN3RXDSR4 _CAN3RXDSR4.Byte +#define CAN3RXDSR4_DB0 _CAN3RXDSR4.Bits.DB0 +#define CAN3RXDSR4_DB1 _CAN3RXDSR4.Bits.DB1 +#define CAN3RXDSR4_DB2 _CAN3RXDSR4.Bits.DB2 +#define CAN3RXDSR4_DB3 _CAN3RXDSR4.Bits.DB3 +#define CAN3RXDSR4_DB4 _CAN3RXDSR4.Bits.DB4 +#define CAN3RXDSR4_DB5 _CAN3RXDSR4.Bits.DB5 +#define CAN3RXDSR4_DB6 _CAN3RXDSR4.Bits.DB6 +#define CAN3RXDSR4_DB7 _CAN3RXDSR4.Bits.DB7 +#define CAN3RXDSR4_DB _CAN3RXDSR4.MergedBits.grpDB + + +/*** CAN3RXDSR5 - MSCAN 3 Receive Data Segment Register 5; 0x00000229 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN3RXDSR5STR; +extern volatile CAN3RXDSR5STR _CAN3RXDSR5 @(REG_BASE + 0x00000229); +#define CAN3RXDSR5 _CAN3RXDSR5.Byte +#define CAN3RXDSR5_DB0 _CAN3RXDSR5.Bits.DB0 +#define CAN3RXDSR5_DB1 _CAN3RXDSR5.Bits.DB1 +#define CAN3RXDSR5_DB2 _CAN3RXDSR5.Bits.DB2 +#define CAN3RXDSR5_DB3 _CAN3RXDSR5.Bits.DB3 +#define CAN3RXDSR5_DB4 _CAN3RXDSR5.Bits.DB4 +#define CAN3RXDSR5_DB5 _CAN3RXDSR5.Bits.DB5 +#define CAN3RXDSR5_DB6 _CAN3RXDSR5.Bits.DB6 +#define CAN3RXDSR5_DB7 _CAN3RXDSR5.Bits.DB7 +#define CAN3RXDSR5_DB _CAN3RXDSR5.MergedBits.grpDB + + +/*** CAN3RXDSR6 - MSCAN 3 Receive Data Segment Register 6; 0x0000022A ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN3RXDSR6STR; +extern volatile CAN3RXDSR6STR _CAN3RXDSR6 @(REG_BASE + 0x0000022A); +#define CAN3RXDSR6 _CAN3RXDSR6.Byte +#define CAN3RXDSR6_DB0 _CAN3RXDSR6.Bits.DB0 +#define CAN3RXDSR6_DB1 _CAN3RXDSR6.Bits.DB1 +#define CAN3RXDSR6_DB2 _CAN3RXDSR6.Bits.DB2 +#define CAN3RXDSR6_DB3 _CAN3RXDSR6.Bits.DB3 +#define CAN3RXDSR6_DB4 _CAN3RXDSR6.Bits.DB4 +#define CAN3RXDSR6_DB5 _CAN3RXDSR6.Bits.DB5 +#define CAN3RXDSR6_DB6 _CAN3RXDSR6.Bits.DB6 +#define CAN3RXDSR6_DB7 _CAN3RXDSR6.Bits.DB7 +#define CAN3RXDSR6_DB _CAN3RXDSR6.MergedBits.grpDB + + +/*** CAN3RXDSR7 - MSCAN 3 Receive Data Segment Register 7; 0x0000022B ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN3RXDSR7STR; +extern volatile CAN3RXDSR7STR _CAN3RXDSR7 @(REG_BASE + 0x0000022B); +#define CAN3RXDSR7 _CAN3RXDSR7.Byte +#define CAN3RXDSR7_DB0 _CAN3RXDSR7.Bits.DB0 +#define CAN3RXDSR7_DB1 _CAN3RXDSR7.Bits.DB1 +#define CAN3RXDSR7_DB2 _CAN3RXDSR7.Bits.DB2 +#define CAN3RXDSR7_DB3 _CAN3RXDSR7.Bits.DB3 +#define CAN3RXDSR7_DB4 _CAN3RXDSR7.Bits.DB4 +#define CAN3RXDSR7_DB5 _CAN3RXDSR7.Bits.DB5 +#define CAN3RXDSR7_DB6 _CAN3RXDSR7.Bits.DB6 +#define CAN3RXDSR7_DB7 _CAN3RXDSR7.Bits.DB7 +#define CAN3RXDSR7_DB _CAN3RXDSR7.MergedBits.grpDB + + +/*** CAN3RXDLR - MSCAN 3 Receive Data Length Register; 0x0000022C ***/ +typedef union { + byte Byte; + struct { + byte DLC0 :1; /* Data Length Code Bit 0 */ + byte DLC1 :1; /* Data Length Code Bit 1 */ + byte DLC2 :1; /* Data Length Code Bit 2 */ + byte DLC3 :1; /* Data Length Code Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpDLC :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN3RXDLRSTR; +extern volatile CAN3RXDLRSTR _CAN3RXDLR @(REG_BASE + 0x0000022C); +#define CAN3RXDLR _CAN3RXDLR.Byte +#define CAN3RXDLR_DLC0 _CAN3RXDLR.Bits.DLC0 +#define CAN3RXDLR_DLC1 _CAN3RXDLR.Bits.DLC1 +#define CAN3RXDLR_DLC2 _CAN3RXDLR.Bits.DLC2 +#define CAN3RXDLR_DLC3 _CAN3RXDLR.Bits.DLC3 +#define CAN3RXDLR_DLC _CAN3RXDLR.MergedBits.grpDLC + + +/*** CAN3TXIDR0 - MSCAN 3 Transmit Identifier Register 0; 0x00000230 ***/ +typedef union { + byte Byte; + struct { + byte ID21 :1; /* Extended format identifier Bit 21 */ + byte ID22 :1; /* Extended format identifier Bit 22 */ + byte ID23 :1; /* Extended format identifier Bit 23 */ + byte ID24 :1; /* Extended format identifier Bit 24 */ + byte ID25 :1; /* Extended format identifier Bit 25 */ + byte ID26 :1; /* Extended format identifier Bit 26 */ + byte ID27 :1; /* Extended format identifier Bit 27 */ + byte ID28 :1; /* Extended format identifier Bit 28 */ + } Bits; + struct { + byte grpID_21 :8; + } MergedBits; +} CAN3TXIDR0STR; +extern volatile CAN3TXIDR0STR _CAN3TXIDR0 @(REG_BASE + 0x00000230); +#define CAN3TXIDR0 _CAN3TXIDR0.Byte +#define CAN3TXIDR0_ID21 _CAN3TXIDR0.Bits.ID21 +#define CAN3TXIDR0_ID22 _CAN3TXIDR0.Bits.ID22 +#define CAN3TXIDR0_ID23 _CAN3TXIDR0.Bits.ID23 +#define CAN3TXIDR0_ID24 _CAN3TXIDR0.Bits.ID24 +#define CAN3TXIDR0_ID25 _CAN3TXIDR0.Bits.ID25 +#define CAN3TXIDR0_ID26 _CAN3TXIDR0.Bits.ID26 +#define CAN3TXIDR0_ID27 _CAN3TXIDR0.Bits.ID27 +#define CAN3TXIDR0_ID28 _CAN3TXIDR0.Bits.ID28 +#define CAN3TXIDR0_ID_21 _CAN3TXIDR0.MergedBits.grpID_21 +#define CAN3TXIDR0_ID CAN3TXIDR0_ID_21 + + +/*** CAN3TXIDR1 - MSCAN 3 Transmit Identifier Register 1; 0x00000231 ***/ +typedef union { + byte Byte; + struct { + byte ID15 :1; /* Extended format identifier Bit 15 */ + byte ID16 :1; /* Extended format identifier Bit 16 */ + byte ID17 :1; /* Extended format identifier Bit 17 */ + byte IDE :1; /* ID Extended */ + byte SRR :1; /* Substitute Remote Request */ + byte ID18 :1; /* Extended format identifier Bit 18 */ + byte ID19 :1; /* Extended format identifier Bit 19 */ + byte ID20 :1; /* Extended format identifier Bit 20 */ + } Bits; + struct { + byte grpID_15 :3; + byte :1; + byte :1; + byte grpID_18 :3; + } MergedBits; +} CAN3TXIDR1STR; +extern volatile CAN3TXIDR1STR _CAN3TXIDR1 @(REG_BASE + 0x00000231); +#define CAN3TXIDR1 _CAN3TXIDR1.Byte +#define CAN3TXIDR1_ID15 _CAN3TXIDR1.Bits.ID15 +#define CAN3TXIDR1_ID16 _CAN3TXIDR1.Bits.ID16 +#define CAN3TXIDR1_ID17 _CAN3TXIDR1.Bits.ID17 +#define CAN3TXIDR1_IDE _CAN3TXIDR1.Bits.IDE +#define CAN3TXIDR1_SRR _CAN3TXIDR1.Bits.SRR +#define CAN3TXIDR1_ID18 _CAN3TXIDR1.Bits.ID18 +#define CAN3TXIDR1_ID19 _CAN3TXIDR1.Bits.ID19 +#define CAN3TXIDR1_ID20 _CAN3TXIDR1.Bits.ID20 +#define CAN3TXIDR1_ID_15 _CAN3TXIDR1.MergedBits.grpID_15 +#define CAN3TXIDR1_ID_18 _CAN3TXIDR1.MergedBits.grpID_18 +#define CAN3TXIDR1_ID CAN3TXIDR1_ID_15 + + +/*** CAN3TXIDR2 - MSCAN 3 Transmit Identifier Register 2; 0x00000232 ***/ +typedef union { + byte Byte; + struct { + byte ID7 :1; /* Extended format identifier Bit 7 */ + byte ID8 :1; /* Extended format identifier Bit 8 */ + byte ID9 :1; /* Extended format identifier Bit 9 */ + byte ID10 :1; /* Extended format identifier Bit 10 */ + byte ID11 :1; /* Extended format identifier Bit 11 */ + byte ID12 :1; /* Extended format identifier Bit 12 */ + byte ID13 :1; /* Extended format identifier Bit 13 */ + byte ID14 :1; /* Extended format identifier Bit 14 */ + } Bits; + struct { + byte grpID_7 :8; + } MergedBits; +} CAN3TXIDR2STR; +extern volatile CAN3TXIDR2STR _CAN3TXIDR2 @(REG_BASE + 0x00000232); +#define CAN3TXIDR2 _CAN3TXIDR2.Byte +#define CAN3TXIDR2_ID7 _CAN3TXIDR2.Bits.ID7 +#define CAN3TXIDR2_ID8 _CAN3TXIDR2.Bits.ID8 +#define CAN3TXIDR2_ID9 _CAN3TXIDR2.Bits.ID9 +#define CAN3TXIDR2_ID10 _CAN3TXIDR2.Bits.ID10 +#define CAN3TXIDR2_ID11 _CAN3TXIDR2.Bits.ID11 +#define CAN3TXIDR2_ID12 _CAN3TXIDR2.Bits.ID12 +#define CAN3TXIDR2_ID13 _CAN3TXIDR2.Bits.ID13 +#define CAN3TXIDR2_ID14 _CAN3TXIDR2.Bits.ID14 +#define CAN3TXIDR2_ID_7 _CAN3TXIDR2.MergedBits.grpID_7 +#define CAN3TXIDR2_ID CAN3TXIDR2_ID_7 + + +/*** CAN3TXIDR3 - MSCAN 3 Transmit Identifier Register 3; 0x00000233 ***/ +typedef union { + byte Byte; + struct { + byte RTR :1; /* Remote Transmission Request */ + byte ID0 :1; /* Extended format identifier Bit 0 */ + byte ID1 :1; /* Extended format identifier Bit 1 */ + byte ID2 :1; /* Extended format identifier Bit 2 */ + byte ID3 :1; /* Extended format identifier Bit 3 */ + byte ID4 :1; /* Extended format identifier Bit 4 */ + byte ID5 :1; /* Extended format identifier Bit 5 */ + byte ID6 :1; /* Extended format identifier Bit 6 */ + } Bits; + struct { + byte :1; + byte grpID :7; + } MergedBits; +} CAN3TXIDR3STR; +extern volatile CAN3TXIDR3STR _CAN3TXIDR3 @(REG_BASE + 0x00000233); +#define CAN3TXIDR3 _CAN3TXIDR3.Byte +#define CAN3TXIDR3_RTR _CAN3TXIDR3.Bits.RTR +#define CAN3TXIDR3_ID0 _CAN3TXIDR3.Bits.ID0 +#define CAN3TXIDR3_ID1 _CAN3TXIDR3.Bits.ID1 +#define CAN3TXIDR3_ID2 _CAN3TXIDR3.Bits.ID2 +#define CAN3TXIDR3_ID3 _CAN3TXIDR3.Bits.ID3 +#define CAN3TXIDR3_ID4 _CAN3TXIDR3.Bits.ID4 +#define CAN3TXIDR3_ID5 _CAN3TXIDR3.Bits.ID5 +#define CAN3TXIDR3_ID6 _CAN3TXIDR3.Bits.ID6 +#define CAN3TXIDR3_ID _CAN3TXIDR3.MergedBits.grpID + + +/*** CAN3TXDSR0 - MSCAN 3 Transmit Data Segment Register 0; 0x00000234 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN3TXDSR0STR; +extern volatile CAN3TXDSR0STR _CAN3TXDSR0 @(REG_BASE + 0x00000234); +#define CAN3TXDSR0 _CAN3TXDSR0.Byte +#define CAN3TXDSR0_DB0 _CAN3TXDSR0.Bits.DB0 +#define CAN3TXDSR0_DB1 _CAN3TXDSR0.Bits.DB1 +#define CAN3TXDSR0_DB2 _CAN3TXDSR0.Bits.DB2 +#define CAN3TXDSR0_DB3 _CAN3TXDSR0.Bits.DB3 +#define CAN3TXDSR0_DB4 _CAN3TXDSR0.Bits.DB4 +#define CAN3TXDSR0_DB5 _CAN3TXDSR0.Bits.DB5 +#define CAN3TXDSR0_DB6 _CAN3TXDSR0.Bits.DB6 +#define CAN3TXDSR0_DB7 _CAN3TXDSR0.Bits.DB7 +#define CAN3TXDSR0_DB _CAN3TXDSR0.MergedBits.grpDB + + +/*** CAN3TXDSR1 - MSCAN 3 Transmit Data Segment Register 1; 0x00000235 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN3TXDSR1STR; +extern volatile CAN3TXDSR1STR _CAN3TXDSR1 @(REG_BASE + 0x00000235); +#define CAN3TXDSR1 _CAN3TXDSR1.Byte +#define CAN3TXDSR1_DB0 _CAN3TXDSR1.Bits.DB0 +#define CAN3TXDSR1_DB1 _CAN3TXDSR1.Bits.DB1 +#define CAN3TXDSR1_DB2 _CAN3TXDSR1.Bits.DB2 +#define CAN3TXDSR1_DB3 _CAN3TXDSR1.Bits.DB3 +#define CAN3TXDSR1_DB4 _CAN3TXDSR1.Bits.DB4 +#define CAN3TXDSR1_DB5 _CAN3TXDSR1.Bits.DB5 +#define CAN3TXDSR1_DB6 _CAN3TXDSR1.Bits.DB6 +#define CAN3TXDSR1_DB7 _CAN3TXDSR1.Bits.DB7 +#define CAN3TXDSR1_DB _CAN3TXDSR1.MergedBits.grpDB + + +/*** CAN3TXDSR2 - MSCAN 3 Transmit Data Segment Register 2; 0x00000236 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN3TXDSR2STR; +extern volatile CAN3TXDSR2STR _CAN3TXDSR2 @(REG_BASE + 0x00000236); +#define CAN3TXDSR2 _CAN3TXDSR2.Byte +#define CAN3TXDSR2_DB0 _CAN3TXDSR2.Bits.DB0 +#define CAN3TXDSR2_DB1 _CAN3TXDSR2.Bits.DB1 +#define CAN3TXDSR2_DB2 _CAN3TXDSR2.Bits.DB2 +#define CAN3TXDSR2_DB3 _CAN3TXDSR2.Bits.DB3 +#define CAN3TXDSR2_DB4 _CAN3TXDSR2.Bits.DB4 +#define CAN3TXDSR2_DB5 _CAN3TXDSR2.Bits.DB5 +#define CAN3TXDSR2_DB6 _CAN3TXDSR2.Bits.DB6 +#define CAN3TXDSR2_DB7 _CAN3TXDSR2.Bits.DB7 +#define CAN3TXDSR2_DB _CAN3TXDSR2.MergedBits.grpDB + + +/*** CAN3TXDSR3 - MSCAN 3 Transmit Data Segment Register 3; 0x00000237 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN3TXDSR3STR; +extern volatile CAN3TXDSR3STR _CAN3TXDSR3 @(REG_BASE + 0x00000237); +#define CAN3TXDSR3 _CAN3TXDSR3.Byte +#define CAN3TXDSR3_DB0 _CAN3TXDSR3.Bits.DB0 +#define CAN3TXDSR3_DB1 _CAN3TXDSR3.Bits.DB1 +#define CAN3TXDSR3_DB2 _CAN3TXDSR3.Bits.DB2 +#define CAN3TXDSR3_DB3 _CAN3TXDSR3.Bits.DB3 +#define CAN3TXDSR3_DB4 _CAN3TXDSR3.Bits.DB4 +#define CAN3TXDSR3_DB5 _CAN3TXDSR3.Bits.DB5 +#define CAN3TXDSR3_DB6 _CAN3TXDSR3.Bits.DB6 +#define CAN3TXDSR3_DB7 _CAN3TXDSR3.Bits.DB7 +#define CAN3TXDSR3_DB _CAN3TXDSR3.MergedBits.grpDB + + +/*** CAN3TXDSR4 - MSCAN 3 Transmit Data Segment Register 4; 0x00000238 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN3TXDSR4STR; +extern volatile CAN3TXDSR4STR _CAN3TXDSR4 @(REG_BASE + 0x00000238); +#define CAN3TXDSR4 _CAN3TXDSR4.Byte +#define CAN3TXDSR4_DB0 _CAN3TXDSR4.Bits.DB0 +#define CAN3TXDSR4_DB1 _CAN3TXDSR4.Bits.DB1 +#define CAN3TXDSR4_DB2 _CAN3TXDSR4.Bits.DB2 +#define CAN3TXDSR4_DB3 _CAN3TXDSR4.Bits.DB3 +#define CAN3TXDSR4_DB4 _CAN3TXDSR4.Bits.DB4 +#define CAN3TXDSR4_DB5 _CAN3TXDSR4.Bits.DB5 +#define CAN3TXDSR4_DB6 _CAN3TXDSR4.Bits.DB6 +#define CAN3TXDSR4_DB7 _CAN3TXDSR4.Bits.DB7 +#define CAN3TXDSR4_DB _CAN3TXDSR4.MergedBits.grpDB + + +/*** CAN3TXDSR5 - MSCAN 3 Transmit Data Segment Register 5; 0x00000239 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN3TXDSR5STR; +extern volatile CAN3TXDSR5STR _CAN3TXDSR5 @(REG_BASE + 0x00000239); +#define CAN3TXDSR5 _CAN3TXDSR5.Byte +#define CAN3TXDSR5_DB0 _CAN3TXDSR5.Bits.DB0 +#define CAN3TXDSR5_DB1 _CAN3TXDSR5.Bits.DB1 +#define CAN3TXDSR5_DB2 _CAN3TXDSR5.Bits.DB2 +#define CAN3TXDSR5_DB3 _CAN3TXDSR5.Bits.DB3 +#define CAN3TXDSR5_DB4 _CAN3TXDSR5.Bits.DB4 +#define CAN3TXDSR5_DB5 _CAN3TXDSR5.Bits.DB5 +#define CAN3TXDSR5_DB6 _CAN3TXDSR5.Bits.DB6 +#define CAN3TXDSR5_DB7 _CAN3TXDSR5.Bits.DB7 +#define CAN3TXDSR5_DB _CAN3TXDSR5.MergedBits.grpDB + + +/*** CAN3TXDSR6 - MSCAN 3 Transmit Data Segment Register 6; 0x0000023A ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN3TXDSR6STR; +extern volatile CAN3TXDSR6STR _CAN3TXDSR6 @(REG_BASE + 0x0000023A); +#define CAN3TXDSR6 _CAN3TXDSR6.Byte +#define CAN3TXDSR6_DB0 _CAN3TXDSR6.Bits.DB0 +#define CAN3TXDSR6_DB1 _CAN3TXDSR6.Bits.DB1 +#define CAN3TXDSR6_DB2 _CAN3TXDSR6.Bits.DB2 +#define CAN3TXDSR6_DB3 _CAN3TXDSR6.Bits.DB3 +#define CAN3TXDSR6_DB4 _CAN3TXDSR6.Bits.DB4 +#define CAN3TXDSR6_DB5 _CAN3TXDSR6.Bits.DB5 +#define CAN3TXDSR6_DB6 _CAN3TXDSR6.Bits.DB6 +#define CAN3TXDSR6_DB7 _CAN3TXDSR6.Bits.DB7 +#define CAN3TXDSR6_DB _CAN3TXDSR6.MergedBits.grpDB + + +/*** CAN3TXDSR7 - MSCAN 3 Transmit Data Segment Register 7; 0x0000023B ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN3TXDSR7STR; +extern volatile CAN3TXDSR7STR _CAN3TXDSR7 @(REG_BASE + 0x0000023B); +#define CAN3TXDSR7 _CAN3TXDSR7.Byte +#define CAN3TXDSR7_DB0 _CAN3TXDSR7.Bits.DB0 +#define CAN3TXDSR7_DB1 _CAN3TXDSR7.Bits.DB1 +#define CAN3TXDSR7_DB2 _CAN3TXDSR7.Bits.DB2 +#define CAN3TXDSR7_DB3 _CAN3TXDSR7.Bits.DB3 +#define CAN3TXDSR7_DB4 _CAN3TXDSR7.Bits.DB4 +#define CAN3TXDSR7_DB5 _CAN3TXDSR7.Bits.DB5 +#define CAN3TXDSR7_DB6 _CAN3TXDSR7.Bits.DB6 +#define CAN3TXDSR7_DB7 _CAN3TXDSR7.Bits.DB7 +#define CAN3TXDSR7_DB _CAN3TXDSR7.MergedBits.grpDB + + +/*** CAN3TXDLR - MSCAN 3 Transmit Data Length Register; 0x0000023C ***/ +typedef union { + byte Byte; + struct { + byte DLC0 :1; /* Data Length Code Bit 0 */ + byte DLC1 :1; /* Data Length Code Bit 1 */ + byte DLC2 :1; /* Data Length Code Bit 2 */ + byte DLC3 :1; /* Data Length Code Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpDLC :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN3TXDLRSTR; +extern volatile CAN3TXDLRSTR _CAN3TXDLR @(REG_BASE + 0x0000023C); +#define CAN3TXDLR _CAN3TXDLR.Byte +#define CAN3TXDLR_DLC0 _CAN3TXDLR.Bits.DLC0 +#define CAN3TXDLR_DLC1 _CAN3TXDLR.Bits.DLC1 +#define CAN3TXDLR_DLC2 _CAN3TXDLR.Bits.DLC2 +#define CAN3TXDLR_DLC3 _CAN3TXDLR.Bits.DLC3 +#define CAN3TXDLR_DLC _CAN3TXDLR.MergedBits.grpDLC + + +/*** CAN3TXTBPR - MSCAN 3 Transmit Buffer Priority; 0x0000023F ***/ +typedef union { + byte Byte; + struct { + byte PRIO0 :1; /* Transmit Buffer Priority Bit 0 */ + byte PRIO1 :1; /* Transmit Buffer Priority Bit 1 */ + byte PRIO2 :1; /* Transmit Buffer Priority Bit 2 */ + byte PRIO3 :1; /* Transmit Buffer Priority Bit 3 */ + byte PRIO4 :1; /* Transmit Buffer Priority Bit 4 */ + byte PRIO5 :1; /* Transmit Buffer Priority Bit 5 */ + byte PRIO6 :1; /* Transmit Buffer Priority Bit 6 */ + byte PRIO7 :1; /* Transmit Buffer Priority Bit 7 */ + } Bits; + struct { + byte grpPRIO :8; + } MergedBits; +} CAN3TXTBPRSTR; +extern volatile CAN3TXTBPRSTR _CAN3TXTBPR @(REG_BASE + 0x0000023F); +#define CAN3TXTBPR _CAN3TXTBPR.Byte +#define CAN3TXTBPR_PRIO0 _CAN3TXTBPR.Bits.PRIO0 +#define CAN3TXTBPR_PRIO1 _CAN3TXTBPR.Bits.PRIO1 +#define CAN3TXTBPR_PRIO2 _CAN3TXTBPR.Bits.PRIO2 +#define CAN3TXTBPR_PRIO3 _CAN3TXTBPR.Bits.PRIO3 +#define CAN3TXTBPR_PRIO4 _CAN3TXTBPR.Bits.PRIO4 +#define CAN3TXTBPR_PRIO5 _CAN3TXTBPR.Bits.PRIO5 +#define CAN3TXTBPR_PRIO6 _CAN3TXTBPR.Bits.PRIO6 +#define CAN3TXTBPR_PRIO7 _CAN3TXTBPR.Bits.PRIO7 +#define CAN3TXTBPR_PRIO _CAN3TXTBPR.MergedBits.grpPRIO + + +/*** PTT - Port T I/O Register; 0x00000240 ***/ +typedef union { + byte Byte; + struct { + byte PTT0 :1; /* Port T Bit 0 */ + byte PTT1 :1; /* Port T Bit 1 */ + byte PTT2 :1; /* Port T Bit 2 */ + byte PTT3 :1; /* Port T Bit 3 */ + byte PTT4 :1; /* Port T Bit 4 */ + byte PTT5 :1; /* Port T Bit 5 */ + byte PTT6 :1; /* Port T Bit 6 */ + byte PTT7 :1; /* Port T Bit 7 */ + } Bits; + struct { + byte grpPTT :8; + } MergedBits; +} PTTSTR; +extern volatile PTTSTR _PTT @(REG_BASE + 0x00000240); +#define PTT _PTT.Byte +#define PTT_PTT0 _PTT.Bits.PTT0 +#define PTT_PTT1 _PTT.Bits.PTT1 +#define PTT_PTT2 _PTT.Bits.PTT2 +#define PTT_PTT3 _PTT.Bits.PTT3 +#define PTT_PTT4 _PTT.Bits.PTT4 +#define PTT_PTT5 _PTT.Bits.PTT5 +#define PTT_PTT6 _PTT.Bits.PTT6 +#define PTT_PTT7 _PTT.Bits.PTT7 +#define PTT_PTT _PTT.MergedBits.grpPTT + + +/*** PTIT - Port T Input; 0x00000241 ***/ +typedef union { + byte Byte; + struct { + byte PTIT0 :1; /* Port T Bit 0 */ + byte PTIT1 :1; /* Port T Bit 1 */ + byte PTIT2 :1; /* Port T Bit 2 */ + byte PTIT3 :1; /* Port T Bit 3 */ + byte PTIT4 :1; /* Port T Bit 4 */ + byte PTIT5 :1; /* Port T Bit 5 */ + byte PTIT6 :1; /* Port T Bit 6 */ + byte PTIT7 :1; /* Port T Bit 7 */ + } Bits; + struct { + byte grpPTIT :8; + } MergedBits; +} PTITSTR; +extern volatile PTITSTR _PTIT @(REG_BASE + 0x00000241); +#define PTIT _PTIT.Byte +#define PTIT_PTIT0 _PTIT.Bits.PTIT0 +#define PTIT_PTIT1 _PTIT.Bits.PTIT1 +#define PTIT_PTIT2 _PTIT.Bits.PTIT2 +#define PTIT_PTIT3 _PTIT.Bits.PTIT3 +#define PTIT_PTIT4 _PTIT.Bits.PTIT4 +#define PTIT_PTIT5 _PTIT.Bits.PTIT5 +#define PTIT_PTIT6 _PTIT.Bits.PTIT6 +#define PTIT_PTIT7 _PTIT.Bits.PTIT7 +#define PTIT_PTIT _PTIT.MergedBits.grpPTIT + + +/*** DDRT - Port T Data Direction Register; 0x00000242 ***/ +typedef union { + byte Byte; + struct { + byte DDRT0 :1; /* Data Direction Port T Bit 0 */ + byte DDRT1 :1; /* Data Direction Port T Bit 1 */ + byte DDRT2 :1; /* Data Direction Port T Bit 2 */ + byte DDRT3 :1; /* Data Direction Port T Bit 3 */ + byte DDRT4 :1; /* Data Direction Port T Bit 4 */ + byte DDRT5 :1; /* Data Direction Port T Bit 5 */ + byte DDRT6 :1; /* Data Direction Port T Bit 6 */ + byte DDRT7 :1; /* Data Direction Port T Bit 7 */ + } Bits; + struct { + byte grpDDRT :8; + } MergedBits; +} DDRTSTR; +extern volatile DDRTSTR _DDRT @(REG_BASE + 0x00000242); +#define DDRT _DDRT.Byte +#define DDRT_DDRT0 _DDRT.Bits.DDRT0 +#define DDRT_DDRT1 _DDRT.Bits.DDRT1 +#define DDRT_DDRT2 _DDRT.Bits.DDRT2 +#define DDRT_DDRT3 _DDRT.Bits.DDRT3 +#define DDRT_DDRT4 _DDRT.Bits.DDRT4 +#define DDRT_DDRT5 _DDRT.Bits.DDRT5 +#define DDRT_DDRT6 _DDRT.Bits.DDRT6 +#define DDRT_DDRT7 _DDRT.Bits.DDRT7 +#define DDRT_DDRT _DDRT.MergedBits.grpDDRT + + +/*** RDRT - Port T Reduced Drive Register; 0x00000243 ***/ +typedef union { + byte Byte; + struct { + byte RDRT0 :1; /* Reduced Drive Port T Bit 0 */ + byte RDRT1 :1; /* Reduced Drive Port T Bit 1 */ + byte RDRT2 :1; /* Reduced Drive Port T Bit 2 */ + byte RDRT3 :1; /* Reduced Drive Port T Bit 3 */ + byte RDRT4 :1; /* Reduced Drive Port T Bit 4 */ + byte RDRT5 :1; /* Reduced Drive Port T Bit 5 */ + byte RDRT6 :1; /* Reduced Drive Port T Bit 6 */ + byte RDRT7 :1; /* Reduced Drive Port T Bit 7 */ + } Bits; + struct { + byte grpRDRT :8; + } MergedBits; +} RDRTSTR; +extern volatile RDRTSTR _RDRT @(REG_BASE + 0x00000243); +#define RDRT _RDRT.Byte +#define RDRT_RDRT0 _RDRT.Bits.RDRT0 +#define RDRT_RDRT1 _RDRT.Bits.RDRT1 +#define RDRT_RDRT2 _RDRT.Bits.RDRT2 +#define RDRT_RDRT3 _RDRT.Bits.RDRT3 +#define RDRT_RDRT4 _RDRT.Bits.RDRT4 +#define RDRT_RDRT5 _RDRT.Bits.RDRT5 +#define RDRT_RDRT6 _RDRT.Bits.RDRT6 +#define RDRT_RDRT7 _RDRT.Bits.RDRT7 +#define RDRT_RDRT _RDRT.MergedBits.grpRDRT + + +/*** PERT - Port T Pull Device Enable Register; 0x00000244 ***/ +typedef union { + byte Byte; + struct { + byte PERT0 :1; /* Pull Device Enable Port T Bit 0 */ + byte PERT1 :1; /* Pull Device Enable Port T Bit 1 */ + byte PERT2 :1; /* Pull Device Enable Port T Bit 2 */ + byte PERT3 :1; /* Pull Device Enable Port T Bit 3 */ + byte PERT4 :1; /* Pull Device Enable Port T Bit 4 */ + byte PERT5 :1; /* Pull Device Enable Port T Bit 5 */ + byte PERT6 :1; /* Pull Device Enable Port T Bit 6 */ + byte PERT7 :1; /* Pull Device Enable Port T Bit 7 */ + } Bits; + struct { + byte grpPERT :8; + } MergedBits; +} PERTSTR; +extern volatile PERTSTR _PERT @(REG_BASE + 0x00000244); +#define PERT _PERT.Byte +#define PERT_PERT0 _PERT.Bits.PERT0 +#define PERT_PERT1 _PERT.Bits.PERT1 +#define PERT_PERT2 _PERT.Bits.PERT2 +#define PERT_PERT3 _PERT.Bits.PERT3 +#define PERT_PERT4 _PERT.Bits.PERT4 +#define PERT_PERT5 _PERT.Bits.PERT5 +#define PERT_PERT6 _PERT.Bits.PERT6 +#define PERT_PERT7 _PERT.Bits.PERT7 +#define PERT_PERT _PERT.MergedBits.grpPERT + + +/*** PPST - Port T Polarity Select Register; 0x00000245 ***/ +typedef union { + byte Byte; + struct { + byte PPST0 :1; /* Pull Select Port T Bit 0 */ + byte PPST1 :1; /* Pull Select Port T Bit 1 */ + byte PPST2 :1; /* Pull Select Port T Bit 2 */ + byte PPST3 :1; /* Pull Select Port T Bit 3 */ + byte PPST4 :1; /* Pull Select Port T Bit 4 */ + byte PPST5 :1; /* Pull Select Port T Bit 5 */ + byte PPST6 :1; /* Pull Select Port T Bit 6 */ + byte PPST7 :1; /* Pull Select Port T Bit 7 */ + } Bits; + struct { + byte grpPPST :8; + } MergedBits; +} PPSTSTR; +extern volatile PPSTSTR _PPST @(REG_BASE + 0x00000245); +#define PPST _PPST.Byte +#define PPST_PPST0 _PPST.Bits.PPST0 +#define PPST_PPST1 _PPST.Bits.PPST1 +#define PPST_PPST2 _PPST.Bits.PPST2 +#define PPST_PPST3 _PPST.Bits.PPST3 +#define PPST_PPST4 _PPST.Bits.PPST4 +#define PPST_PPST5 _PPST.Bits.PPST5 +#define PPST_PPST6 _PPST.Bits.PPST6 +#define PPST_PPST7 _PPST.Bits.PPST7 +#define PPST_PPST _PPST.MergedBits.grpPPST + + +/*** PTS - Port S I/O Register; 0x00000248 ***/ +typedef union { + byte Byte; + struct { + byte PTS0 :1; /* Port S Bit 0 */ + byte PTS1 :1; /* Port S Bit 1 */ + byte PTS2 :1; /* Port S Bit 2 */ + byte PTS3 :1; /* Port S Bit 3 */ + byte PTS4 :1; /* Port S Bit 4 */ + byte PTS5 :1; /* Port S Bit 5 */ + byte PTS6 :1; /* Port S Bit 6 */ + byte PTS7 :1; /* Port S Bit 7 */ + } Bits; + struct { + byte grpPTS :8; + } MergedBits; +} PTSSTR; +extern volatile PTSSTR _PTS @(REG_BASE + 0x00000248); +#define PTS _PTS.Byte +#define PTS_PTS0 _PTS.Bits.PTS0 +#define PTS_PTS1 _PTS.Bits.PTS1 +#define PTS_PTS2 _PTS.Bits.PTS2 +#define PTS_PTS3 _PTS.Bits.PTS3 +#define PTS_PTS4 _PTS.Bits.PTS4 +#define PTS_PTS5 _PTS.Bits.PTS5 +#define PTS_PTS6 _PTS.Bits.PTS6 +#define PTS_PTS7 _PTS.Bits.PTS7 +#define PTS_PTS _PTS.MergedBits.grpPTS + + +/*** PTIS - Port S Input; 0x00000249 ***/ +typedef union { + byte Byte; + struct { + byte PTIS0 :1; /* Port S Bit 0 */ + byte PTIS1 :1; /* Port S Bit 1 */ + byte PTIS2 :1; /* Port S Bit 2 */ + byte PTIS3 :1; /* Port S Bit 3 */ + byte PTIS4 :1; /* Port S Bit 4 */ + byte PTIS5 :1; /* Port S Bit 5 */ + byte PTIS6 :1; /* Port S Bit 6 */ + byte PTIS7 :1; /* Port S Bit 7 */ + } Bits; + struct { + byte grpPTIS :8; + } MergedBits; +} PTISSTR; +extern volatile PTISSTR _PTIS @(REG_BASE + 0x00000249); +#define PTIS _PTIS.Byte +#define PTIS_PTIS0 _PTIS.Bits.PTIS0 +#define PTIS_PTIS1 _PTIS.Bits.PTIS1 +#define PTIS_PTIS2 _PTIS.Bits.PTIS2 +#define PTIS_PTIS3 _PTIS.Bits.PTIS3 +#define PTIS_PTIS4 _PTIS.Bits.PTIS4 +#define PTIS_PTIS5 _PTIS.Bits.PTIS5 +#define PTIS_PTIS6 _PTIS.Bits.PTIS6 +#define PTIS_PTIS7 _PTIS.Bits.PTIS7 +#define PTIS_PTIS _PTIS.MergedBits.grpPTIS + + +/*** DDRS - Port S Data Direction Register; 0x0000024A ***/ +typedef union { + byte Byte; + struct { + byte DDRS0 :1; /* Data Direction Port S Bit 0 */ + byte DDRS1 :1; /* Data Direction Port S Bit 1 */ + byte DDRS2 :1; /* Data Direction Port S Bit 2 */ + byte DDRS3 :1; /* Data Direction Port S Bit 3 */ + byte DDRS4 :1; /* Data Direction Port S Bit 4 */ + byte DDRS5 :1; /* Data Direction Port S Bit 5 */ + byte DDRS6 :1; /* Data Direction Port S Bit 6 */ + byte DDRS7 :1; /* Data Direction Port S Bit 7 */ + } Bits; + struct { + byte grpDDRS :8; + } MergedBits; +} DDRSSTR; +extern volatile DDRSSTR _DDRS @(REG_BASE + 0x0000024A); +#define DDRS _DDRS.Byte +#define DDRS_DDRS0 _DDRS.Bits.DDRS0 +#define DDRS_DDRS1 _DDRS.Bits.DDRS1 +#define DDRS_DDRS2 _DDRS.Bits.DDRS2 +#define DDRS_DDRS3 _DDRS.Bits.DDRS3 +#define DDRS_DDRS4 _DDRS.Bits.DDRS4 +#define DDRS_DDRS5 _DDRS.Bits.DDRS5 +#define DDRS_DDRS6 _DDRS.Bits.DDRS6 +#define DDRS_DDRS7 _DDRS.Bits.DDRS7 +#define DDRS_DDRS _DDRS.MergedBits.grpDDRS + + +/*** RDRS - Port S Reduced Drive Register; 0x0000024B ***/ +typedef union { + byte Byte; + struct { + byte RDRS0 :1; /* Reduced Drive Port S Bit 0 */ + byte RDRS1 :1; /* Reduced Drive Port S Bit 1 */ + byte RDRS2 :1; /* Reduced Drive Port S Bit 2 */ + byte RDRS3 :1; /* Reduced Drive Port S Bit 3 */ + byte RDRS4 :1; /* Reduced Drive Port S Bit 4 */ + byte RDRS5 :1; /* Reduced Drive Port S Bit 5 */ + byte RDRS6 :1; /* Reduced Drive Port S Bit 6 */ + byte RDRS7 :1; /* Reduced Drive Port S Bit 7 */ + } Bits; + struct { + byte grpRDRS :8; + } MergedBits; +} RDRSSTR; +extern volatile RDRSSTR _RDRS @(REG_BASE + 0x0000024B); +#define RDRS _RDRS.Byte +#define RDRS_RDRS0 _RDRS.Bits.RDRS0 +#define RDRS_RDRS1 _RDRS.Bits.RDRS1 +#define RDRS_RDRS2 _RDRS.Bits.RDRS2 +#define RDRS_RDRS3 _RDRS.Bits.RDRS3 +#define RDRS_RDRS4 _RDRS.Bits.RDRS4 +#define RDRS_RDRS5 _RDRS.Bits.RDRS5 +#define RDRS_RDRS6 _RDRS.Bits.RDRS6 +#define RDRS_RDRS7 _RDRS.Bits.RDRS7 +#define RDRS_RDRS _RDRS.MergedBits.grpRDRS + + +/*** PERS - Port S Pull Device Enable Register; 0x0000024C ***/ +typedef union { + byte Byte; + struct { + byte PERS0 :1; /* Pull Device Enable Port S Bit 0 */ + byte PERS1 :1; /* Pull Device Enable Port S Bit 1 */ + byte PERS2 :1; /* Pull Device Enable Port S Bit 2 */ + byte PERS3 :1; /* Pull Device Enable Port S Bit 3 */ + byte PERS4 :1; /* Pull Device Enable Port S Bit 4 */ + byte PERS5 :1; /* Pull Device Enable Port S Bit 5 */ + byte PERS6 :1; /* Pull Device Enable Port S Bit 6 */ + byte PERS7 :1; /* Pull Device Enable Port S Bit 7 */ + } Bits; + struct { + byte grpPERS :8; + } MergedBits; +} PERSSTR; +extern volatile PERSSTR _PERS @(REG_BASE + 0x0000024C); +#define PERS _PERS.Byte +#define PERS_PERS0 _PERS.Bits.PERS0 +#define PERS_PERS1 _PERS.Bits.PERS1 +#define PERS_PERS2 _PERS.Bits.PERS2 +#define PERS_PERS3 _PERS.Bits.PERS3 +#define PERS_PERS4 _PERS.Bits.PERS4 +#define PERS_PERS5 _PERS.Bits.PERS5 +#define PERS_PERS6 _PERS.Bits.PERS6 +#define PERS_PERS7 _PERS.Bits.PERS7 +#define PERS_PERS _PERS.MergedBits.grpPERS + + +/*** PPSS - Port S Polarity Select Register; 0x0000024D ***/ +typedef union { + byte Byte; + struct { + byte PPSS0 :1; /* Pull Select Port S Bit 0 */ + byte PPSS1 :1; /* Pull Select Port S Bit 1 */ + byte PPSS2 :1; /* Pull Select Port S Bit 2 */ + byte PPSS3 :1; /* Pull Select Port S Bit 3 */ + byte PPSS4 :1; /* Pull Select Port S Bit 4 */ + byte PPSS5 :1; /* Pull Select Port S Bit 5 */ + byte PPSS6 :1; /* Pull Select Port S Bit 6 */ + byte PPSS7 :1; /* Pull Select Port S Bit 7 */ + } Bits; + struct { + byte grpPPSS :8; + } MergedBits; +} PPSSSTR; +extern volatile PPSSSTR _PPSS @(REG_BASE + 0x0000024D); +#define PPSS _PPSS.Byte +#define PPSS_PPSS0 _PPSS.Bits.PPSS0 +#define PPSS_PPSS1 _PPSS.Bits.PPSS1 +#define PPSS_PPSS2 _PPSS.Bits.PPSS2 +#define PPSS_PPSS3 _PPSS.Bits.PPSS3 +#define PPSS_PPSS4 _PPSS.Bits.PPSS4 +#define PPSS_PPSS5 _PPSS.Bits.PPSS5 +#define PPSS_PPSS6 _PPSS.Bits.PPSS6 +#define PPSS_PPSS7 _PPSS.Bits.PPSS7 +#define PPSS_PPSS _PPSS.MergedBits.grpPPSS + + +/*** WOMS - Port S Wired-Or Mode Register; 0x0000024E ***/ +typedef union { + byte Byte; + struct { + byte WOMS0 :1; /* Wired-Or Mode Port S Bit 0 */ + byte WOMS1 :1; /* Wired-Or Mode Port S Bit 1 */ + byte WOMS2 :1; /* Wired-Or Mode Port S Bit 2 */ + byte WOMS3 :1; /* Wired-Or Mode Port S Bit 3 */ + byte WOMS4 :1; /* Wired-Or Mode Port S Bit 4 */ + byte WOMS5 :1; /* Wired-Or Mode Port S Bit 5 */ + byte WOMS6 :1; /* Wired-Or Mode Port S Bit 6 */ + byte WOMS7 :1; /* Wired-Or Mode Port S Bit 7 */ + } Bits; + struct { + byte grpWOMS :8; + } MergedBits; +} WOMSSTR; +extern volatile WOMSSTR _WOMS @(REG_BASE + 0x0000024E); +#define WOMS _WOMS.Byte +#define WOMS_WOMS0 _WOMS.Bits.WOMS0 +#define WOMS_WOMS1 _WOMS.Bits.WOMS1 +#define WOMS_WOMS2 _WOMS.Bits.WOMS2 +#define WOMS_WOMS3 _WOMS.Bits.WOMS3 +#define WOMS_WOMS4 _WOMS.Bits.WOMS4 +#define WOMS_WOMS5 _WOMS.Bits.WOMS5 +#define WOMS_WOMS6 _WOMS.Bits.WOMS6 +#define WOMS_WOMS7 _WOMS.Bits.WOMS7 +#define WOMS_WOMS _WOMS.MergedBits.grpWOMS + + +/*** PTM - Port M I/O Register; 0x00000250 ***/ +typedef union { + byte Byte; + struct { + byte PTM0 :1; /* Port T Bit 0 */ + byte PTM1 :1; /* Port T Bit 1 */ + byte PTM2 :1; /* Port T Bit 2 */ + byte PTM3 :1; /* Port T Bit 3 */ + byte PTM4 :1; /* Port T Bit 4 */ + byte PTM5 :1; /* Port T Bit 5 */ + byte PTM6 :1; /* Port T Bit 6 */ + byte PTM7 :1; /* Port T Bit 7 */ + } Bits; + struct { + byte grpPTM :8; + } MergedBits; +} PTMSTR; +extern volatile PTMSTR _PTM @(REG_BASE + 0x00000250); +#define PTM _PTM.Byte +#define PTM_PTM0 _PTM.Bits.PTM0 +#define PTM_PTM1 _PTM.Bits.PTM1 +#define PTM_PTM2 _PTM.Bits.PTM2 +#define PTM_PTM3 _PTM.Bits.PTM3 +#define PTM_PTM4 _PTM.Bits.PTM4 +#define PTM_PTM5 _PTM.Bits.PTM5 +#define PTM_PTM6 _PTM.Bits.PTM6 +#define PTM_PTM7 _PTM.Bits.PTM7 +#define PTM_PTM _PTM.MergedBits.grpPTM + + +/*** PTIM - Port M Input; 0x00000251 ***/ +typedef union { + byte Byte; + struct { + byte PTIM0 :1; /* Port M Bit 0 */ + byte PTIM1 :1; /* Port M Bit 1 */ + byte PTIM2 :1; /* Port M Bit 2 */ + byte PTIM3 :1; /* Port M Bit 3 */ + byte PTIM4 :1; /* Port M Bit 4 */ + byte PTIM5 :1; /* Port M Bit 5 */ + byte PTIM6 :1; /* Port M Bit 6 */ + byte PTIM7 :1; /* Port M Bit 7 */ + } Bits; + struct { + byte grpPTIM :8; + } MergedBits; +} PTIMSTR; +extern volatile PTIMSTR _PTIM @(REG_BASE + 0x00000251); +#define PTIM _PTIM.Byte +#define PTIM_PTIM0 _PTIM.Bits.PTIM0 +#define PTIM_PTIM1 _PTIM.Bits.PTIM1 +#define PTIM_PTIM2 _PTIM.Bits.PTIM2 +#define PTIM_PTIM3 _PTIM.Bits.PTIM3 +#define PTIM_PTIM4 _PTIM.Bits.PTIM4 +#define PTIM_PTIM5 _PTIM.Bits.PTIM5 +#define PTIM_PTIM6 _PTIM.Bits.PTIM6 +#define PTIM_PTIM7 _PTIM.Bits.PTIM7 +#define PTIM_PTIM _PTIM.MergedBits.grpPTIM + + +/*** DDRM - Port M Data Direction Register; 0x00000252 ***/ +typedef union { + byte Byte; + struct { + byte DDRM0 :1; /* Data Direction Port M Bit 0 */ + byte DDRM1 :1; /* Data Direction Port M Bit 1 */ + byte DDRM2 :1; /* Data Direction Port M Bit 2 */ + byte DDRM3 :1; /* Data Direction Port M Bit 3 */ + byte DDRM4 :1; /* Data Direction Port M Bit 4 */ + byte DDRM5 :1; /* Data Direction Port M Bit 5 */ + byte DDRM6 :1; /* Data Direction Port M Bit 6 */ + byte DDRM7 :1; /* Data Direction Port M Bit 7 */ + } Bits; + struct { + byte grpDDRM :8; + } MergedBits; +} DDRMSTR; +extern volatile DDRMSTR _DDRM @(REG_BASE + 0x00000252); +#define DDRM _DDRM.Byte +#define DDRM_DDRM0 _DDRM.Bits.DDRM0 +#define DDRM_DDRM1 _DDRM.Bits.DDRM1 +#define DDRM_DDRM2 _DDRM.Bits.DDRM2 +#define DDRM_DDRM3 _DDRM.Bits.DDRM3 +#define DDRM_DDRM4 _DDRM.Bits.DDRM4 +#define DDRM_DDRM5 _DDRM.Bits.DDRM5 +#define DDRM_DDRM6 _DDRM.Bits.DDRM6 +#define DDRM_DDRM7 _DDRM.Bits.DDRM7 +#define DDRM_DDRM _DDRM.MergedBits.grpDDRM + + +/*** RDRM - Port M Reduced Drive Register; 0x00000253 ***/ +typedef union { + byte Byte; + struct { + byte RDRM0 :1; /* Reduced Drive Port M Bit 0 */ + byte RDRM1 :1; /* Reduced Drive Port M Bit 1 */ + byte RDRM2 :1; /* Reduced Drive Port M Bit 2 */ + byte RDRM3 :1; /* Reduced Drive Port M Bit 3 */ + byte RDRM4 :1; /* Reduced Drive Port M Bit 4 */ + byte RDRM5 :1; /* Reduced Drive Port M Bit 5 */ + byte RDRM6 :1; /* Reduced Drive Port M Bit 6 */ + byte RDRM7 :1; /* Reduced Drive Port M Bit 7 */ + } Bits; + struct { + byte grpRDRM :8; + } MergedBits; +} RDRMSTR; +extern volatile RDRMSTR _RDRM @(REG_BASE + 0x00000253); +#define RDRM _RDRM.Byte +#define RDRM_RDRM0 _RDRM.Bits.RDRM0 +#define RDRM_RDRM1 _RDRM.Bits.RDRM1 +#define RDRM_RDRM2 _RDRM.Bits.RDRM2 +#define RDRM_RDRM3 _RDRM.Bits.RDRM3 +#define RDRM_RDRM4 _RDRM.Bits.RDRM4 +#define RDRM_RDRM5 _RDRM.Bits.RDRM5 +#define RDRM_RDRM6 _RDRM.Bits.RDRM6 +#define RDRM_RDRM7 _RDRM.Bits.RDRM7 +#define RDRM_RDRM _RDRM.MergedBits.grpRDRM + + +/*** PERM - Port M Pull Device Enable Register; 0x00000254 ***/ +typedef union { + byte Byte; + struct { + byte PERM0 :1; /* Pull Device Enable Port M Bit 0 */ + byte PERM1 :1; /* Pull Device Enable Port M Bit 1 */ + byte PERM2 :1; /* Pull Device Enable Port M Bit 2 */ + byte PERM3 :1; /* Pull Device Enable Port M Bit 3 */ + byte PERM4 :1; /* Pull Device Enable Port M Bit 4 */ + byte PERM5 :1; /* Pull Device Enable Port M Bit 5 */ + byte PERM6 :1; /* Pull Device Enable Port M Bit 6 */ + byte PERM7 :1; /* Pull Device Enable Port M Bit 7 */ + } Bits; + struct { + byte grpPERM :8; + } MergedBits; +} PERMSTR; +extern volatile PERMSTR _PERM @(REG_BASE + 0x00000254); +#define PERM _PERM.Byte +#define PERM_PERM0 _PERM.Bits.PERM0 +#define PERM_PERM1 _PERM.Bits.PERM1 +#define PERM_PERM2 _PERM.Bits.PERM2 +#define PERM_PERM3 _PERM.Bits.PERM3 +#define PERM_PERM4 _PERM.Bits.PERM4 +#define PERM_PERM5 _PERM.Bits.PERM5 +#define PERM_PERM6 _PERM.Bits.PERM6 +#define PERM_PERM7 _PERM.Bits.PERM7 +#define PERM_PERM _PERM.MergedBits.grpPERM + + +/*** PPSM - Port M Polarity Select Register; 0x00000255 ***/ +typedef union { + byte Byte; + struct { + byte PPSM0 :1; /* Pull Select Port M Bit 0 */ + byte PPSM1 :1; /* Pull Select Port M Bit 1 */ + byte PPSM2 :1; /* Pull Select Port M Bit 2 */ + byte PPSM3 :1; /* Pull Select Port M Bit 3 */ + byte PPSM4 :1; /* Pull Select Port M Bit 4 */ + byte PPSM5 :1; /* Pull Select Port M Bit 5 */ + byte PPSM6 :1; /* Pull Select Port M Bit 6 */ + byte PPSM7 :1; /* Pull Select Port M Bit 7 */ + } Bits; + struct { + byte grpPPSM :8; + } MergedBits; +} PPSMSTR; +extern volatile PPSMSTR _PPSM @(REG_BASE + 0x00000255); +#define PPSM _PPSM.Byte +#define PPSM_PPSM0 _PPSM.Bits.PPSM0 +#define PPSM_PPSM1 _PPSM.Bits.PPSM1 +#define PPSM_PPSM2 _PPSM.Bits.PPSM2 +#define PPSM_PPSM3 _PPSM.Bits.PPSM3 +#define PPSM_PPSM4 _PPSM.Bits.PPSM4 +#define PPSM_PPSM5 _PPSM.Bits.PPSM5 +#define PPSM_PPSM6 _PPSM.Bits.PPSM6 +#define PPSM_PPSM7 _PPSM.Bits.PPSM7 +#define PPSM_PPSM _PPSM.MergedBits.grpPPSM + + +/*** WOMM - Port M Wired-Or Mode Register; 0x00000256 ***/ +typedef union { + byte Byte; + struct { + byte WOMM0 :1; /* Wired-Or Mode Port M Bit 0 */ + byte WOMM1 :1; /* Wired-Or Mode Port M Bit 1 */ + byte WOMM2 :1; /* Wired-Or Mode Port M Bit 2 */ + byte WOMM3 :1; /* Wired-Or Mode Port M Bit 3 */ + byte WOMM4 :1; /* Wired-Or Mode Port M Bit 4 */ + byte WOMM5 :1; /* Wired-Or Mode Port M Bit 5 */ + byte WOMM6 :1; /* Wired-Or Mode Port M Bit 6 */ + byte WOMM7 :1; /* Wired-Or Mode Port M Bit 7 */ + } Bits; + struct { + byte grpWOMM :8; + } MergedBits; +} WOMMSTR; +extern volatile WOMMSTR _WOMM @(REG_BASE + 0x00000256); +#define WOMM _WOMM.Byte +#define WOMM_WOMM0 _WOMM.Bits.WOMM0 +#define WOMM_WOMM1 _WOMM.Bits.WOMM1 +#define WOMM_WOMM2 _WOMM.Bits.WOMM2 +#define WOMM_WOMM3 _WOMM.Bits.WOMM3 +#define WOMM_WOMM4 _WOMM.Bits.WOMM4 +#define WOMM_WOMM5 _WOMM.Bits.WOMM5 +#define WOMM_WOMM6 _WOMM.Bits.WOMM6 +#define WOMM_WOMM7 _WOMM.Bits.WOMM7 +#define WOMM_WOMM _WOMM.MergedBits.grpWOMM + + +/*** MODRR - Module Routing Register; 0x00000257 ***/ +typedef union { + byte Byte; + struct { + byte MODRR0 :1; /* CAN0 Routing */ + byte MODRR1 :1; /* CAN0 Routing */ + byte MODRR2 :1; /* CAN4 Routing */ + byte MODRR3 :1; /* CAN4 Routing */ + byte MODRR4 :1; /* SPI0 Routing */ + byte MODRR5 :1; /* SPI1 Routing */ + byte MODRR6 :1; /* SPI2 Routing */ + byte :1; + } Bits; + struct { + byte grpMODRR :7; + byte :1; + } MergedBits; +} MODRRSTR; +extern volatile MODRRSTR _MODRR @(REG_BASE + 0x00000257); +#define MODRR _MODRR.Byte +#define MODRR_MODRR0 _MODRR.Bits.MODRR0 +#define MODRR_MODRR1 _MODRR.Bits.MODRR1 +#define MODRR_MODRR2 _MODRR.Bits.MODRR2 +#define MODRR_MODRR3 _MODRR.Bits.MODRR3 +#define MODRR_MODRR4 _MODRR.Bits.MODRR4 +#define MODRR_MODRR5 _MODRR.Bits.MODRR5 +#define MODRR_MODRR6 _MODRR.Bits.MODRR6 +#define MODRR_MODRR _MODRR.MergedBits.grpMODRR + + +/*** PTP - Port P I/O Register; 0x00000258 ***/ +typedef union { + byte Byte; + struct { + byte PTP0 :1; /* Port P Bit 0 */ + byte PTP1 :1; /* Port P Bit 1 */ + byte PTP2 :1; /* Port P Bit 2 */ + byte PTP3 :1; /* Port P Bit 3 */ + byte PTP4 :1; /* Port P Bit 4 */ + byte PTP5 :1; /* Port P Bit 5 */ + byte PTP6 :1; /* Port P Bit 6 */ + byte PTP7 :1; /* Port P Bit 7 */ + } Bits; + struct { + byte grpPTP :8; + } MergedBits; +} PTPSTR; +extern volatile PTPSTR _PTP @(REG_BASE + 0x00000258); +#define PTP _PTP.Byte +#define PTP_PTP0 _PTP.Bits.PTP0 +#define PTP_PTP1 _PTP.Bits.PTP1 +#define PTP_PTP2 _PTP.Bits.PTP2 +#define PTP_PTP3 _PTP.Bits.PTP3 +#define PTP_PTP4 _PTP.Bits.PTP4 +#define PTP_PTP5 _PTP.Bits.PTP5 +#define PTP_PTP6 _PTP.Bits.PTP6 +#define PTP_PTP7 _PTP.Bits.PTP7 +#define PTP_PTP _PTP.MergedBits.grpPTP + + +/*** PTIP - Port P Input; 0x00000259 ***/ +typedef union { + byte Byte; + struct { + byte PTIP0 :1; /* Port P Bit 0 */ + byte PTIP1 :1; /* Port P Bit 1 */ + byte PTIP2 :1; /* Port P Bit 2 */ + byte PTIP3 :1; /* Port P Bit 3 */ + byte PTIP4 :1; /* Port P Bit 4 */ + byte PTIP5 :1; /* Port P Bit 5 */ + byte PTIP6 :1; /* Port P Bit 6 */ + byte PTIP7 :1; /* Port P Bit 7 */ + } Bits; + struct { + byte grpPTIP :8; + } MergedBits; +} PTIPSTR; +extern volatile PTIPSTR _PTIP @(REG_BASE + 0x00000259); +#define PTIP _PTIP.Byte +#define PTIP_PTIP0 _PTIP.Bits.PTIP0 +#define PTIP_PTIP1 _PTIP.Bits.PTIP1 +#define PTIP_PTIP2 _PTIP.Bits.PTIP2 +#define PTIP_PTIP3 _PTIP.Bits.PTIP3 +#define PTIP_PTIP4 _PTIP.Bits.PTIP4 +#define PTIP_PTIP5 _PTIP.Bits.PTIP5 +#define PTIP_PTIP6 _PTIP.Bits.PTIP6 +#define PTIP_PTIP7 _PTIP.Bits.PTIP7 +#define PTIP_PTIP _PTIP.MergedBits.grpPTIP + + +/*** DDRP - Port P Data Direction Register; 0x0000025A ***/ +typedef union { + byte Byte; + struct { + byte DDRP0 :1; /* Data Direction Port P Bit 0 */ + byte DDRP1 :1; /* Data Direction Port P Bit 1 */ + byte DDRP2 :1; /* Data Direction Port P Bit 2 */ + byte DDRP3 :1; /* Data Direction Port P Bit 3 */ + byte DDRP4 :1; /* Data Direction Port P Bit 4 */ + byte DDRP5 :1; /* Data Direction Port P Bit 5 */ + byte DDRP6 :1; /* Data Direction Port P Bit 6 */ + byte DDRP7 :1; /* Data Direction Port P Bit 7 */ + } Bits; + struct { + byte grpDDRP :8; + } MergedBits; +} DDRPSTR; +extern volatile DDRPSTR _DDRP @(REG_BASE + 0x0000025A); +#define DDRP _DDRP.Byte +#define DDRP_DDRP0 _DDRP.Bits.DDRP0 +#define DDRP_DDRP1 _DDRP.Bits.DDRP1 +#define DDRP_DDRP2 _DDRP.Bits.DDRP2 +#define DDRP_DDRP3 _DDRP.Bits.DDRP3 +#define DDRP_DDRP4 _DDRP.Bits.DDRP4 +#define DDRP_DDRP5 _DDRP.Bits.DDRP5 +#define DDRP_DDRP6 _DDRP.Bits.DDRP6 +#define DDRP_DDRP7 _DDRP.Bits.DDRP7 +#define DDRP_DDRP _DDRP.MergedBits.grpDDRP + + +/*** RDRP - Port P Reduced Drive Register; 0x0000025B ***/ +typedef union { + byte Byte; + struct { + byte RDRP0 :1; /* Reduced Drive Port P Bit 0 */ + byte RDRP1 :1; /* Reduced Drive Port P Bit 1 */ + byte RDRP2 :1; /* Reduced Drive Port P Bit 2 */ + byte RDRP3 :1; /* Reduced Drive Port P Bit 3 */ + byte RDRP4 :1; /* Reduced Drive Port P Bit 4 */ + byte RDRP5 :1; /* Reduced Drive Port P Bit 5 */ + byte RDRP6 :1; /* Reduced Drive Port P Bit 6 */ + byte RDRP7 :1; /* Reduced Drive Port P Bit 7 */ + } Bits; + struct { + byte grpRDRP :8; + } MergedBits; +} RDRPSTR; +extern volatile RDRPSTR _RDRP @(REG_BASE + 0x0000025B); +#define RDRP _RDRP.Byte +#define RDRP_RDRP0 _RDRP.Bits.RDRP0 +#define RDRP_RDRP1 _RDRP.Bits.RDRP1 +#define RDRP_RDRP2 _RDRP.Bits.RDRP2 +#define RDRP_RDRP3 _RDRP.Bits.RDRP3 +#define RDRP_RDRP4 _RDRP.Bits.RDRP4 +#define RDRP_RDRP5 _RDRP.Bits.RDRP5 +#define RDRP_RDRP6 _RDRP.Bits.RDRP6 +#define RDRP_RDRP7 _RDRP.Bits.RDRP7 +#define RDRP_RDRP _RDRP.MergedBits.grpRDRP + + +/*** PERP - Port P Pull Device Enable Register; 0x0000025C ***/ +typedef union { + byte Byte; + struct { + byte PERP0 :1; /* Pull Device Enable Port P Bit 0 */ + byte PERP1 :1; /* Pull Device Enable Port P Bit 1 */ + byte PERP2 :1; /* Pull Device Enable Port P Bit 2 */ + byte PERP3 :1; /* Pull Device Enable Port P Bit 3 */ + byte PERP4 :1; /* Pull Device Enable Port P Bit 4 */ + byte PERP5 :1; /* Pull Device Enable Port P Bit 5 */ + byte PERP6 :1; /* Pull Device Enable Port P Bit 6 */ + byte PERP7 :1; /* Pull Device Enable Port P Bit 7 */ + } Bits; + struct { + byte grpPERP :8; + } MergedBits; +} PERPSTR; +extern volatile PERPSTR _PERP @(REG_BASE + 0x0000025C); +#define PERP _PERP.Byte +#define PERP_PERP0 _PERP.Bits.PERP0 +#define PERP_PERP1 _PERP.Bits.PERP1 +#define PERP_PERP2 _PERP.Bits.PERP2 +#define PERP_PERP3 _PERP.Bits.PERP3 +#define PERP_PERP4 _PERP.Bits.PERP4 +#define PERP_PERP5 _PERP.Bits.PERP5 +#define PERP_PERP6 _PERP.Bits.PERP6 +#define PERP_PERP7 _PERP.Bits.PERP7 +#define PERP_PERP _PERP.MergedBits.grpPERP + + +/*** PPSP - Port P Polarity Select Register; 0x0000025D ***/ +typedef union { + byte Byte; + struct { + byte PPSP0 :1; /* Pull Select Port P Bit 0 */ + byte PPSP1 :1; /* Pull Select Port P Bit 1 */ + byte PPSP2 :1; /* Pull Select Port P Bit 2 */ + byte PPSP3 :1; /* Pull Select Port P Bit 3 */ + byte PPSP4 :1; /* Pull Select Port P Bit 4 */ + byte PPSP5 :1; /* Pull Select Port P Bit 5 */ + byte PPSP6 :1; /* Pull Select Port P Bit 6 */ + byte PPSP7 :1; /* Pull Select Port P Bit 7 */ + } Bits; + struct { + byte grpPPSP :8; + } MergedBits; +} PPSPSTR; +extern volatile PPSPSTR _PPSP @(REG_BASE + 0x0000025D); +#define PPSP _PPSP.Byte +#define PPSP_PPSP0 _PPSP.Bits.PPSP0 +#define PPSP_PPSP1 _PPSP.Bits.PPSP1 +#define PPSP_PPSP2 _PPSP.Bits.PPSP2 +#define PPSP_PPSP3 _PPSP.Bits.PPSP3 +#define PPSP_PPSP4 _PPSP.Bits.PPSP4 +#define PPSP_PPSP5 _PPSP.Bits.PPSP5 +#define PPSP_PPSP6 _PPSP.Bits.PPSP6 +#define PPSP_PPSP7 _PPSP.Bits.PPSP7 +#define PPSP_PPSP _PPSP.MergedBits.grpPPSP + + +/*** PIEP - Port P Interrupt Enable Register; 0x0000025E ***/ +typedef union { + byte Byte; + struct { + byte PIEP0 :1; /* Interrupt Enable Port P Bit 0 */ + byte PIEP1 :1; /* Interrupt Enable Port P Bit 1 */ + byte PIEP2 :1; /* Interrupt Enable Port P Bit 2 */ + byte PIEP3 :1; /* Interrupt Enable Port P Bit 3 */ + byte PIEP4 :1; /* Interrupt Enable Port P Bit 4 */ + byte PIEP5 :1; /* Interrupt Enable Port P Bit 5 */ + byte PIEP6 :1; /* Interrupt Enable Port P Bit 6 */ + byte PIEP7 :1; /* Interrupt Enable Port P Bit 7 */ + } Bits; + struct { + byte grpPIEP :8; + } MergedBits; +} PIEPSTR; +extern volatile PIEPSTR _PIEP @(REG_BASE + 0x0000025E); +#define PIEP _PIEP.Byte +#define PIEP_PIEP0 _PIEP.Bits.PIEP0 +#define PIEP_PIEP1 _PIEP.Bits.PIEP1 +#define PIEP_PIEP2 _PIEP.Bits.PIEP2 +#define PIEP_PIEP3 _PIEP.Bits.PIEP3 +#define PIEP_PIEP4 _PIEP.Bits.PIEP4 +#define PIEP_PIEP5 _PIEP.Bits.PIEP5 +#define PIEP_PIEP6 _PIEP.Bits.PIEP6 +#define PIEP_PIEP7 _PIEP.Bits.PIEP7 +#define PIEP_PIEP _PIEP.MergedBits.grpPIEP + + +/*** PIFP - Port P Interrupt Flag Register; 0x0000025F ***/ +typedef union { + byte Byte; + struct { + byte PIFP0 :1; /* Interrupt Flags Port P Bit 0 */ + byte PIFP1 :1; /* Interrupt Flags Port P Bit 1 */ + byte PIFP2 :1; /* Interrupt Flags Port P Bit 2 */ + byte PIFP3 :1; /* Interrupt Flags Port P Bit 3 */ + byte PIFP4 :1; /* Interrupt Flags Port P Bit 4 */ + byte PIFP5 :1; /* Interrupt Flags Port P Bit 5 */ + byte PIFP6 :1; /* Interrupt Flags Port P Bit 6 */ + byte PIFP7 :1; /* Interrupt Flags Port P Bit 7 */ + } Bits; + struct { + byte grpPIFP :8; + } MergedBits; +} PIFPSTR; +extern volatile PIFPSTR _PIFP @(REG_BASE + 0x0000025F); +#define PIFP _PIFP.Byte +#define PIFP_PIFP0 _PIFP.Bits.PIFP0 +#define PIFP_PIFP1 _PIFP.Bits.PIFP1 +#define PIFP_PIFP2 _PIFP.Bits.PIFP2 +#define PIFP_PIFP3 _PIFP.Bits.PIFP3 +#define PIFP_PIFP4 _PIFP.Bits.PIFP4 +#define PIFP_PIFP5 _PIFP.Bits.PIFP5 +#define PIFP_PIFP6 _PIFP.Bits.PIFP6 +#define PIFP_PIFP7 _PIFP.Bits.PIFP7 +#define PIFP_PIFP _PIFP.MergedBits.grpPIFP + + +/*** PTH - Port H I/O Register; 0x00000260 ***/ +typedef union { + byte Byte; + struct { + byte PTH0 :1; /* Port H Bit 0 */ + byte PTH1 :1; /* Port H Bit 1 */ + byte PTH2 :1; /* Port H Bit 2 */ + byte PTH3 :1; /* Port H Bit 3 */ + byte PTH4 :1; /* Port H Bit 4 */ + byte PTH5 :1; /* Port H Bit 5 */ + byte PTH6 :1; /* Port H Bit 6 */ + byte PTH7 :1; /* Port H Bit 7 */ + } Bits; + struct { + byte grpPTH :8; + } MergedBits; +} PTHSTR; +extern volatile PTHSTR _PTH @(REG_BASE + 0x00000260); +#define PTH _PTH.Byte +#define PTH_PTH0 _PTH.Bits.PTH0 +#define PTH_PTH1 _PTH.Bits.PTH1 +#define PTH_PTH2 _PTH.Bits.PTH2 +#define PTH_PTH3 _PTH.Bits.PTH3 +#define PTH_PTH4 _PTH.Bits.PTH4 +#define PTH_PTH5 _PTH.Bits.PTH5 +#define PTH_PTH6 _PTH.Bits.PTH6 +#define PTH_PTH7 _PTH.Bits.PTH7 +#define PTH_PTH _PTH.MergedBits.grpPTH + + +/*** PTIH - Port H Input Register; 0x00000261 ***/ +typedef union { + byte Byte; + struct { + byte PTIH0 :1; /* Port H Bit 0 */ + byte PTIH1 :1; /* Port H Bit 1 */ + byte PTIH2 :1; /* Port H Bit 2 */ + byte PTIH3 :1; /* Port H Bit 3 */ + byte PTIH4 :1; /* Port H Bit 4 */ + byte PTIH5 :1; /* Port H Bit 5 */ + byte PTIH6 :1; /* Port H Bit 6 */ + byte PTIH7 :1; /* Port H Bit 7 */ + } Bits; + struct { + byte grpPTIH :8; + } MergedBits; +} PTIHSTR; +extern volatile PTIHSTR _PTIH @(REG_BASE + 0x00000261); +#define PTIH _PTIH.Byte +#define PTIH_PTIH0 _PTIH.Bits.PTIH0 +#define PTIH_PTIH1 _PTIH.Bits.PTIH1 +#define PTIH_PTIH2 _PTIH.Bits.PTIH2 +#define PTIH_PTIH3 _PTIH.Bits.PTIH3 +#define PTIH_PTIH4 _PTIH.Bits.PTIH4 +#define PTIH_PTIH5 _PTIH.Bits.PTIH5 +#define PTIH_PTIH6 _PTIH.Bits.PTIH6 +#define PTIH_PTIH7 _PTIH.Bits.PTIH7 +#define PTIH_PTIH _PTIH.MergedBits.grpPTIH + + +/*** DDRH - Port H Data Direction Register; 0x00000262 ***/ +typedef union { + byte Byte; + struct { + byte DDRH0 :1; /* Data Direction Port H Bit 0 */ + byte DDRH1 :1; /* Data Direction Port H Bit 1 */ + byte DDRH2 :1; /* Data Direction Port H Bit 2 */ + byte DDRH3 :1; /* Data Direction Port H Bit 3 */ + byte DDRH4 :1; /* Data Direction Port H Bit 4 */ + byte DDRH5 :1; /* Data Direction Port H Bit 5 */ + byte DDRH6 :1; /* Data Direction Port H Bit 6 */ + byte DDRH7 :1; /* Data Direction Port H Bit 7 */ + } Bits; + struct { + byte grpDDRH :8; + } MergedBits; +} DDRHSTR; +extern volatile DDRHSTR _DDRH @(REG_BASE + 0x00000262); +#define DDRH _DDRH.Byte +#define DDRH_DDRH0 _DDRH.Bits.DDRH0 +#define DDRH_DDRH1 _DDRH.Bits.DDRH1 +#define DDRH_DDRH2 _DDRH.Bits.DDRH2 +#define DDRH_DDRH3 _DDRH.Bits.DDRH3 +#define DDRH_DDRH4 _DDRH.Bits.DDRH4 +#define DDRH_DDRH5 _DDRH.Bits.DDRH5 +#define DDRH_DDRH6 _DDRH.Bits.DDRH6 +#define DDRH_DDRH7 _DDRH.Bits.DDRH7 +#define DDRH_DDRH _DDRH.MergedBits.grpDDRH + + +/*** RDRH - Port H Reduced Drive Register; 0x00000263 ***/ +typedef union { + byte Byte; + struct { + byte RDRH0 :1; /* Reduced Drive Port H Bit 0 */ + byte RDRH1 :1; /* Reduced Drive Port H Bit 1 */ + byte RDRH2 :1; /* Reduced Drive Port H Bit 2 */ + byte RDRH3 :1; /* Reduced Drive Port H Bit 3 */ + byte RDRH4 :1; /* Reduced Drive Port H Bit 4 */ + byte RDRH5 :1; /* Reduced Drive Port H Bit 5 */ + byte RDRH6 :1; /* Reduced Drive Port H Bit 6 */ + byte RDRH7 :1; /* Reduced Drive Port H Bit 7 */ + } Bits; + struct { + byte grpRDRH :8; + } MergedBits; +} RDRHSTR; +extern volatile RDRHSTR _RDRH @(REG_BASE + 0x00000263); +#define RDRH _RDRH.Byte +#define RDRH_RDRH0 _RDRH.Bits.RDRH0 +#define RDRH_RDRH1 _RDRH.Bits.RDRH1 +#define RDRH_RDRH2 _RDRH.Bits.RDRH2 +#define RDRH_RDRH3 _RDRH.Bits.RDRH3 +#define RDRH_RDRH4 _RDRH.Bits.RDRH4 +#define RDRH_RDRH5 _RDRH.Bits.RDRH5 +#define RDRH_RDRH6 _RDRH.Bits.RDRH6 +#define RDRH_RDRH7 _RDRH.Bits.RDRH7 +#define RDRH_RDRH _RDRH.MergedBits.grpRDRH + + +/*** PERH - Port H Pull Device Enable Register; 0x00000264 ***/ +typedef union { + byte Byte; + struct { + byte PERH0 :1; /* Pull Device Enable Port H Bit 0 */ + byte PERH1 :1; /* Pull Device Enable Port H Bit 1 */ + byte PERH2 :1; /* Pull Device Enable Port H Bit 2 */ + byte PERH3 :1; /* Pull Device Enable Port H Bit 3 */ + byte PERH4 :1; /* Pull Device Enable Port H Bit 4 */ + byte PERH5 :1; /* Pull Device Enable Port H Bit 5 */ + byte PERH6 :1; /* Pull Device Enable Port H Bit 6 */ + byte PERH7 :1; /* Pull Device Enable Port H Bit 7 */ + } Bits; + struct { + byte grpPERH :8; + } MergedBits; +} PERHSTR; +extern volatile PERHSTR _PERH @(REG_BASE + 0x00000264); +#define PERH _PERH.Byte +#define PERH_PERH0 _PERH.Bits.PERH0 +#define PERH_PERH1 _PERH.Bits.PERH1 +#define PERH_PERH2 _PERH.Bits.PERH2 +#define PERH_PERH3 _PERH.Bits.PERH3 +#define PERH_PERH4 _PERH.Bits.PERH4 +#define PERH_PERH5 _PERH.Bits.PERH5 +#define PERH_PERH6 _PERH.Bits.PERH6 +#define PERH_PERH7 _PERH.Bits.PERH7 +#define PERH_PERH _PERH.MergedBits.grpPERH + + +/*** PPSH - Port H Polarity Select Register; 0x00000265 ***/ +typedef union { + byte Byte; + struct { + byte PPSH0 :1; /* Pull Select Port H Bit 0 */ + byte PPSH1 :1; /* Pull Select Port H Bit 1 */ + byte PPSH2 :1; /* Pull Select Port H Bit 2 */ + byte PPSH3 :1; /* Pull Select Port H Bit 3 */ + byte PPSH4 :1; /* Pull Select Port H Bit 4 */ + byte PPSH5 :1; /* Pull Select Port H Bit 5 */ + byte PPSH6 :1; /* Pull Select Port H Bit 6 */ + byte PPSH7 :1; /* Pull Select Port H Bit 7 */ + } Bits; + struct { + byte grpPPSH :8; + } MergedBits; +} PPSHSTR; +extern volatile PPSHSTR _PPSH @(REG_BASE + 0x00000265); +#define PPSH _PPSH.Byte +#define PPSH_PPSH0 _PPSH.Bits.PPSH0 +#define PPSH_PPSH1 _PPSH.Bits.PPSH1 +#define PPSH_PPSH2 _PPSH.Bits.PPSH2 +#define PPSH_PPSH3 _PPSH.Bits.PPSH3 +#define PPSH_PPSH4 _PPSH.Bits.PPSH4 +#define PPSH_PPSH5 _PPSH.Bits.PPSH5 +#define PPSH_PPSH6 _PPSH.Bits.PPSH6 +#define PPSH_PPSH7 _PPSH.Bits.PPSH7 +#define PPSH_PPSH _PPSH.MergedBits.grpPPSH + + +/*** PIEH - Port H Interrupt Enable Register; 0x00000266 ***/ +typedef union { + byte Byte; + struct { + byte PIEH0 :1; /* Interrupt Enable Port H Bit 0 */ + byte PIEH1 :1; /* Interrupt Enable Port H Bit 1 */ + byte PIEH2 :1; /* Interrupt Enable Port H Bit 2 */ + byte PIEH3 :1; /* Interrupt Enable Port H Bit 3 */ + byte PIEH4 :1; /* Interrupt Enable Port H Bit 4 */ + byte PIEH5 :1; /* Interrupt Enable Port H Bit 5 */ + byte PIEH6 :1; /* Interrupt Enable Port H Bit 6 */ + byte PIEH7 :1; /* Interrupt Enable Port H Bit 7 */ + } Bits; + struct { + byte grpPIEH :8; + } MergedBits; +} PIEHSTR; +extern volatile PIEHSTR _PIEH @(REG_BASE + 0x00000266); +#define PIEH _PIEH.Byte +#define PIEH_PIEH0 _PIEH.Bits.PIEH0 +#define PIEH_PIEH1 _PIEH.Bits.PIEH1 +#define PIEH_PIEH2 _PIEH.Bits.PIEH2 +#define PIEH_PIEH3 _PIEH.Bits.PIEH3 +#define PIEH_PIEH4 _PIEH.Bits.PIEH4 +#define PIEH_PIEH5 _PIEH.Bits.PIEH5 +#define PIEH_PIEH6 _PIEH.Bits.PIEH6 +#define PIEH_PIEH7 _PIEH.Bits.PIEH7 +#define PIEH_PIEH _PIEH.MergedBits.grpPIEH + + +/*** PIFH - Port H Interrupt Flag Register; 0x00000267 ***/ +typedef union { + byte Byte; + struct { + byte PIFH0 :1; /* Interrupt Flags Port H Bit 0 */ + byte PIFH1 :1; /* Interrupt Flags Port H Bit 1 */ + byte PIFH2 :1; /* Interrupt Flags Port H Bit 2 */ + byte PIFH3 :1; /* Interrupt Flags Port H Bit 3 */ + byte PIFH4 :1; /* Interrupt Flags Port H Bit 4 */ + byte PIFH5 :1; /* Interrupt Flags Port H Bit 5 */ + byte PIFH6 :1; /* Interrupt Flags Port H Bit 6 */ + byte PIFH7 :1; /* Interrupt Flags Port H Bit 7 */ + } Bits; + struct { + byte grpPIFH :8; + } MergedBits; +} PIFHSTR; +extern volatile PIFHSTR _PIFH @(REG_BASE + 0x00000267); +#define PIFH _PIFH.Byte +#define PIFH_PIFH0 _PIFH.Bits.PIFH0 +#define PIFH_PIFH1 _PIFH.Bits.PIFH1 +#define PIFH_PIFH2 _PIFH.Bits.PIFH2 +#define PIFH_PIFH3 _PIFH.Bits.PIFH3 +#define PIFH_PIFH4 _PIFH.Bits.PIFH4 +#define PIFH_PIFH5 _PIFH.Bits.PIFH5 +#define PIFH_PIFH6 _PIFH.Bits.PIFH6 +#define PIFH_PIFH7 _PIFH.Bits.PIFH7 +#define PIFH_PIFH _PIFH.MergedBits.grpPIFH + + +/*** PTJ - Port J I/O Register; 0x00000268 ***/ +typedef union { + byte Byte; + struct { + byte PTJ0 :1; /* Port J Bit 0 */ + byte PTJ1 :1; /* Port J Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte PTJ6 :1; /* Port J Bit 6 */ + byte PTJ7 :1; /* Port J Bit 7 */ + } Bits; + struct { + byte grpPTJ :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpPTJ_6 :2; + } MergedBits; +} PTJSTR; +extern volatile PTJSTR _PTJ @(REG_BASE + 0x00000268); +#define PTJ _PTJ.Byte +#define PTJ_PTJ0 _PTJ.Bits.PTJ0 +#define PTJ_PTJ1 _PTJ.Bits.PTJ1 +#define PTJ_PTJ6 _PTJ.Bits.PTJ6 +#define PTJ_PTJ7 _PTJ.Bits.PTJ7 +#define PTJ_PTJ _PTJ.MergedBits.grpPTJ +#define PTJ_PTJ_6 _PTJ.MergedBits.grpPTJ_6 + + +/*** PTIJ - Port J Input Register; 0x00000269 ***/ +typedef union { + byte Byte; + struct { + byte PTIJ0 :1; /* Port J Bit 0 */ + byte PTIJ1 :1; /* Port J Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte PTIJ6 :1; /* Port J Bit 6 */ + byte PTIJ7 :1; /* Port J Bit 7 */ + } Bits; + struct { + byte grpPTIJ :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpPTIJ_6 :2; + } MergedBits; +} PTIJSTR; +extern volatile PTIJSTR _PTIJ @(REG_BASE + 0x00000269); +#define PTIJ _PTIJ.Byte +#define PTIJ_PTIJ0 _PTIJ.Bits.PTIJ0 +#define PTIJ_PTIJ1 _PTIJ.Bits.PTIJ1 +#define PTIJ_PTIJ6 _PTIJ.Bits.PTIJ6 +#define PTIJ_PTIJ7 _PTIJ.Bits.PTIJ7 +#define PTIJ_PTIJ _PTIJ.MergedBits.grpPTIJ +#define PTIJ_PTIJ_6 _PTIJ.MergedBits.grpPTIJ_6 + + +/*** DDRJ - Port J Data Direction Register; 0x0000026A ***/ +typedef union { + byte Byte; + struct { + byte DDRJ0 :1; /* Data Direction Port J Bit 0 */ + byte DDRJ1 :1; /* Data Direction Port J Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte DDRJ6 :1; /* Data Direction Port J Bit 6 */ + byte DDRJ7 :1; /* Data Direction Port J Bit 7 */ + } Bits; + struct { + byte grpDDRJ :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpDDRJ_6 :2; + } MergedBits; +} DDRJSTR; +extern volatile DDRJSTR _DDRJ @(REG_BASE + 0x0000026A); +#define DDRJ _DDRJ.Byte +#define DDRJ_DDRJ0 _DDRJ.Bits.DDRJ0 +#define DDRJ_DDRJ1 _DDRJ.Bits.DDRJ1 +#define DDRJ_DDRJ6 _DDRJ.Bits.DDRJ6 +#define DDRJ_DDRJ7 _DDRJ.Bits.DDRJ7 +#define DDRJ_DDRJ _DDRJ.MergedBits.grpDDRJ +#define DDRJ_DDRJ_6 _DDRJ.MergedBits.grpDDRJ_6 + + +/*** RDRJ - Port J Reduced Drive Register; 0x0000026B ***/ +typedef union { + byte Byte; + struct { + byte RDRJ0 :1; /* Reduced Drive Port J Bit 0 */ + byte RDRJ1 :1; /* Reduced Drive Port J Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte RDRJ6 :1; /* Reduced Drive Port J Bit 6 */ + byte RDRJ7 :1; /* Reduced Drive Port J Bit 7 */ + } Bits; + struct { + byte grpRDRJ :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpRDRJ_6 :2; + } MergedBits; +} RDRJSTR; +extern volatile RDRJSTR _RDRJ @(REG_BASE + 0x0000026B); +#define RDRJ _RDRJ.Byte +#define RDRJ_RDRJ0 _RDRJ.Bits.RDRJ0 +#define RDRJ_RDRJ1 _RDRJ.Bits.RDRJ1 +#define RDRJ_RDRJ6 _RDRJ.Bits.RDRJ6 +#define RDRJ_RDRJ7 _RDRJ.Bits.RDRJ7 +#define RDRJ_RDRJ _RDRJ.MergedBits.grpRDRJ +#define RDRJ_RDRJ_6 _RDRJ.MergedBits.grpRDRJ_6 + + +/*** PERJ - Port J Pull Device Enable Register; 0x0000026C ***/ +typedef union { + byte Byte; + struct { + byte PERJ0 :1; /* Pull Device Enable Port J Bit 0 */ + byte PERJ1 :1; /* Pull Device Enable Port J Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte PERJ6 :1; /* Pull Device Enable Port J Bit 6 */ + byte PERJ7 :1; /* Pull Device Enable Port J Bit 7 */ + } Bits; + struct { + byte grpPERJ :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpPERJ_6 :2; + } MergedBits; +} PERJSTR; +extern volatile PERJSTR _PERJ @(REG_BASE + 0x0000026C); +#define PERJ _PERJ.Byte +#define PERJ_PERJ0 _PERJ.Bits.PERJ0 +#define PERJ_PERJ1 _PERJ.Bits.PERJ1 +#define PERJ_PERJ6 _PERJ.Bits.PERJ6 +#define PERJ_PERJ7 _PERJ.Bits.PERJ7 +#define PERJ_PERJ _PERJ.MergedBits.grpPERJ +#define PERJ_PERJ_6 _PERJ.MergedBits.grpPERJ_6 + + +/*** PPSJ - PortJP Polarity Select Register; 0x0000026D ***/ +typedef union { + byte Byte; + struct { + byte PPSJ0 :1; /* Pull Select Port J Bit 0 */ + byte PPSJ1 :1; /* Pull Select Port J Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte PPSJ6 :1; /* Pull Select Port J Bit 6 */ + byte PPSJ7 :1; /* Pull Select Port J Bit 7 */ + } Bits; + struct { + byte grpPPSJ :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpPPSJ_6 :2; + } MergedBits; +} PPSJSTR; +extern volatile PPSJSTR _PPSJ @(REG_BASE + 0x0000026D); +#define PPSJ _PPSJ.Byte +#define PPSJ_PPSJ0 _PPSJ.Bits.PPSJ0 +#define PPSJ_PPSJ1 _PPSJ.Bits.PPSJ1 +#define PPSJ_PPSJ6 _PPSJ.Bits.PPSJ6 +#define PPSJ_PPSJ7 _PPSJ.Bits.PPSJ7 +#define PPSJ_PPSJ _PPSJ.MergedBits.grpPPSJ +#define PPSJ_PPSJ_6 _PPSJ.MergedBits.grpPPSJ_6 + + +/*** PIEJ - Port J Interrupt Enable Register; 0x0000026E ***/ +typedef union { + byte Byte; + struct { + byte PIEJ0 :1; /* Interrupt Enable Port J Bit 0 */ + byte PIEJ1 :1; /* Interrupt Enable Port J Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte PIEJ6 :1; /* Interrupt Enable Port J Bit 6 */ + byte PIEJ7 :1; /* Interrupt Enable Port J Bit 7 */ + } Bits; + struct { + byte grpPIEJ :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpPIEJ_6 :2; + } MergedBits; +} PIEJSTR; +extern volatile PIEJSTR _PIEJ @(REG_BASE + 0x0000026E); +#define PIEJ _PIEJ.Byte +#define PIEJ_PIEJ0 _PIEJ.Bits.PIEJ0 +#define PIEJ_PIEJ1 _PIEJ.Bits.PIEJ1 +#define PIEJ_PIEJ6 _PIEJ.Bits.PIEJ6 +#define PIEJ_PIEJ7 _PIEJ.Bits.PIEJ7 +#define PIEJ_PIEJ _PIEJ.MergedBits.grpPIEJ +#define PIEJ_PIEJ_6 _PIEJ.MergedBits.grpPIEJ_6 + + +/*** PIFJ - Port J Interrupt Flag Register; 0x0000026F ***/ +typedef union { + byte Byte; + struct { + byte PIFJ0 :1; /* Interrupt Flags Port J Bit 0 */ + byte PIFJ1 :1; /* Interrupt Flags Port J Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte PIFJ6 :1; /* Interrupt Flags Port J Bit 6 */ + byte PIFJ7 :1; /* Interrupt Flags Port J Bit 7 */ + } Bits; + struct { + byte grpPIFJ :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpPIFJ_6 :2; + } MergedBits; +} PIFJSTR; +extern volatile PIFJSTR _PIFJ @(REG_BASE + 0x0000026F); +#define PIFJ _PIFJ.Byte +#define PIFJ_PIFJ0 _PIFJ.Bits.PIFJ0 +#define PIFJ_PIFJ1 _PIFJ.Bits.PIFJ1 +#define PIFJ_PIFJ6 _PIFJ.Bits.PIFJ6 +#define PIFJ_PIFJ7 _PIFJ.Bits.PIFJ7 +#define PIFJ_PIFJ _PIFJ.MergedBits.grpPIFJ +#define PIFJ_PIFJ_6 _PIFJ.MergedBits.grpPIFJ_6 + + +/*** CAN4CTL0 - MSCAN4 Control 0 Register; 0x00000280 ***/ +typedef union { + byte Byte; + struct { + byte INITRQ :1; /* Initialization Mode Request */ + byte SLPRQ :1; /* Sleep Mode Request */ + byte WUPE :1; /* Wake-Up Enable */ + byte TIME :1; /* Timer Enable */ + byte SYNCH :1; /* Synchronized Status */ + byte CSWAI :1; /* CAN Stops in Wait Mode */ + byte RXACT :1; /* Receiver Active Status */ + byte RXFRM :1; /* Received Frame Flag */ + } Bits; +} CAN4CTL0STR; +extern volatile CAN4CTL0STR _CAN4CTL0 @(REG_BASE + 0x00000280); +#define CAN4CTL0 _CAN4CTL0.Byte +#define CAN4CTL0_INITRQ _CAN4CTL0.Bits.INITRQ +#define CAN4CTL0_SLPRQ _CAN4CTL0.Bits.SLPRQ +#define CAN4CTL0_WUPE _CAN4CTL0.Bits.WUPE +#define CAN4CTL0_TIME _CAN4CTL0.Bits.TIME +#define CAN4CTL0_SYNCH _CAN4CTL0.Bits.SYNCH +#define CAN4CTL0_CSWAI _CAN4CTL0.Bits.CSWAI +#define CAN4CTL0_RXACT _CAN4CTL0.Bits.RXACT +#define CAN4CTL0_RXFRM _CAN4CTL0.Bits.RXFRM + + +/*** CAN4CTL1 - MSCAN4 Control 1 Register; 0x00000281 ***/ +typedef union { + byte Byte; + struct { + byte INITAK :1; /* Initialization Mode Acknowledge */ + byte SLPAK :1; /* Sleep Mode Acknowledge */ + byte WUPM :1; /* Wake-Up Mode */ + byte :1; + byte LISTEN :1; /* Listen Only Mode */ + byte LOOPB :1; /* Loop Back Self Test Mode */ + byte CLKSRC :1; /* MSCAN4 Clock Source */ + byte CANE :1; /* MSCAN4 Enable */ + } Bits; +} CAN4CTL1STR; +extern volatile CAN4CTL1STR _CAN4CTL1 @(REG_BASE + 0x00000281); +#define CAN4CTL1 _CAN4CTL1.Byte +#define CAN4CTL1_INITAK _CAN4CTL1.Bits.INITAK +#define CAN4CTL1_SLPAK _CAN4CTL1.Bits.SLPAK +#define CAN4CTL1_WUPM _CAN4CTL1.Bits.WUPM +#define CAN4CTL1_LISTEN _CAN4CTL1.Bits.LISTEN +#define CAN4CTL1_LOOPB _CAN4CTL1.Bits.LOOPB +#define CAN4CTL1_CLKSRC _CAN4CTL1.Bits.CLKSRC +#define CAN4CTL1_CANE _CAN4CTL1.Bits.CANE + + +/*** CAN4BTR0 - MSCAN4 Bus Timing Register 0; 0x00000282 ***/ +typedef union { + byte Byte; + struct { + byte BRP0 :1; /* Baud Rate Prescaler 0 */ + byte BRP1 :1; /* Baud Rate Prescaler 1 */ + byte BRP2 :1; /* Baud Rate Prescaler 2 */ + byte BRP3 :1; /* Baud Rate Prescaler 3 */ + byte BRP4 :1; /* Baud Rate Prescaler 4 */ + byte BRP5 :1; /* Baud Rate Prescaler 5 */ + byte SJW0 :1; /* Synchronization Jump Width 0 */ + byte SJW1 :1; /* Synchronization Jump Width 1 */ + } Bits; + struct { + byte grpBRP :6; + byte grpSJW :2; + } MergedBits; +} CAN4BTR0STR; +extern volatile CAN4BTR0STR _CAN4BTR0 @(REG_BASE + 0x00000282); +#define CAN4BTR0 _CAN4BTR0.Byte +#define CAN4BTR0_BRP0 _CAN4BTR0.Bits.BRP0 +#define CAN4BTR0_BRP1 _CAN4BTR0.Bits.BRP1 +#define CAN4BTR0_BRP2 _CAN4BTR0.Bits.BRP2 +#define CAN4BTR0_BRP3 _CAN4BTR0.Bits.BRP3 +#define CAN4BTR0_BRP4 _CAN4BTR0.Bits.BRP4 +#define CAN4BTR0_BRP5 _CAN4BTR0.Bits.BRP5 +#define CAN4BTR0_SJW0 _CAN4BTR0.Bits.SJW0 +#define CAN4BTR0_SJW1 _CAN4BTR0.Bits.SJW1 +#define CAN4BTR0_BRP _CAN4BTR0.MergedBits.grpBRP +#define CAN4BTR0_SJW _CAN4BTR0.MergedBits.grpSJW + + +/*** CAN4BTR1 - MSCAN4 Bus Timing Register 1; 0x00000283 ***/ +typedef union { + byte Byte; + struct { + byte TSEG10 :1; /* Time Segment 1 */ + byte TSEG11 :1; /* Time Segment 1 */ + byte TSEG12 :1; /* Time Segment 1 */ + byte TSEG13 :1; /* Time Segment 1 */ + byte TSEG20 :1; /* Time Segment 2 */ + byte TSEG21 :1; /* Time Segment 2 */ + byte TSEG22 :1; /* Time Segment 2 */ + byte SAMP :1; /* Sampling */ + } Bits; + struct { + byte grpTSEG_10 :4; + byte grpTSEG_20 :3; + byte :1; + } MergedBits; +} CAN4BTR1STR; +extern volatile CAN4BTR1STR _CAN4BTR1 @(REG_BASE + 0x00000283); +#define CAN4BTR1 _CAN4BTR1.Byte +#define CAN4BTR1_TSEG10 _CAN4BTR1.Bits.TSEG10 +#define CAN4BTR1_TSEG11 _CAN4BTR1.Bits.TSEG11 +#define CAN4BTR1_TSEG12 _CAN4BTR1.Bits.TSEG12 +#define CAN4BTR1_TSEG13 _CAN4BTR1.Bits.TSEG13 +#define CAN4BTR1_TSEG20 _CAN4BTR1.Bits.TSEG20 +#define CAN4BTR1_TSEG21 _CAN4BTR1.Bits.TSEG21 +#define CAN4BTR1_TSEG22 _CAN4BTR1.Bits.TSEG22 +#define CAN4BTR1_SAMP _CAN4BTR1.Bits.SAMP +#define CAN4BTR1_TSEG_10 _CAN4BTR1.MergedBits.grpTSEG_10 +#define CAN4BTR1_TSEG_20 _CAN4BTR1.MergedBits.grpTSEG_20 +#define CAN4BTR1_TSEG CAN4BTR1_TSEG_10 + + +/*** CAN4RFLG - MSCAN4 Receiver Flag Register; 0x00000284 ***/ +typedef union { + byte Byte; + struct { + byte RXF :1; /* Receive Buffer Full */ + byte OVRIF :1; /* Overrun Interrupt Flag */ + byte TSTAT0 :1; /* Transmitter Status Bit 0 */ + byte TSTAT1 :1; /* Transmitter Status Bit 1 */ + byte RSTAT0 :1; /* Receiver Status Bit 0 */ + byte RSTAT1 :1; /* Receiver Status Bit 1 */ + byte CSCIF :1; /* CAN Status Change Interrupt Flag */ + byte WUPIF :1; /* Wake-up Interrupt Flag */ + } Bits; + struct { + byte :1; + byte :1; + byte grpTSTAT :2; + byte grpRSTAT :2; + byte :1; + byte :1; + } MergedBits; +} CAN4RFLGSTR; +extern volatile CAN4RFLGSTR _CAN4RFLG @(REG_BASE + 0x00000284); +#define CAN4RFLG _CAN4RFLG.Byte +#define CAN4RFLG_RXF _CAN4RFLG.Bits.RXF +#define CAN4RFLG_OVRIF _CAN4RFLG.Bits.OVRIF +#define CAN4RFLG_TSTAT0 _CAN4RFLG.Bits.TSTAT0 +#define CAN4RFLG_TSTAT1 _CAN4RFLG.Bits.TSTAT1 +#define CAN4RFLG_RSTAT0 _CAN4RFLG.Bits.RSTAT0 +#define CAN4RFLG_RSTAT1 _CAN4RFLG.Bits.RSTAT1 +#define CAN4RFLG_CSCIF _CAN4RFLG.Bits.CSCIF +#define CAN4RFLG_WUPIF _CAN4RFLG.Bits.WUPIF +#define CAN4RFLG_TSTAT _CAN4RFLG.MergedBits.grpTSTAT +#define CAN4RFLG_RSTAT _CAN4RFLG.MergedBits.grpRSTAT + + +/*** CAN4RIER - MSCAN4 Receiver Interrupt Enable Register; 0x00000285 ***/ +typedef union { + byte Byte; + struct { + byte RXFIE :1; /* Receiver Full Interrupt Enable */ + byte OVRIE :1; /* Overrun Interrupt Enable */ + byte TSTATE0 :1; /* Transmitter Status Change Enable 0 */ + byte TSTATE1 :1; /* Transmitter Status Change Enable 1 */ + byte RSTATE0 :1; /* Receiver Status Change Enable 0 */ + byte RSTATE1 :1; /* Receiver Status Change Enable 1 */ + byte CSCIE :1; /* CAN Status Change Interrupt Enable */ + byte WUPIE :1; /* Wake-up Interrupt Enable */ + } Bits; + struct { + byte :1; + byte :1; + byte grpTSTATE :2; + byte grpRSTATE :2; + byte :1; + byte :1; + } MergedBits; +} CAN4RIERSTR; +extern volatile CAN4RIERSTR _CAN4RIER @(REG_BASE + 0x00000285); +#define CAN4RIER _CAN4RIER.Byte +#define CAN4RIER_RXFIE _CAN4RIER.Bits.RXFIE +#define CAN4RIER_OVRIE _CAN4RIER.Bits.OVRIE +#define CAN4RIER_TSTATE0 _CAN4RIER.Bits.TSTATE0 +#define CAN4RIER_TSTATE1 _CAN4RIER.Bits.TSTATE1 +#define CAN4RIER_RSTATE0 _CAN4RIER.Bits.RSTATE0 +#define CAN4RIER_RSTATE1 _CAN4RIER.Bits.RSTATE1 +#define CAN4RIER_CSCIE _CAN4RIER.Bits.CSCIE +#define CAN4RIER_WUPIE _CAN4RIER.Bits.WUPIE +#define CAN4RIER_TSTATE _CAN4RIER.MergedBits.grpTSTATE +#define CAN4RIER_RSTATE _CAN4RIER.MergedBits.grpRSTATE + + +/*** CAN4TFLG - MSCAN4 Transmitter Flag Register; 0x00000286 ***/ +typedef union { + byte Byte; + struct { + byte TXE0 :1; /* Transmitter Buffer Empty 0 */ + byte TXE1 :1; /* Transmitter Buffer Empty 1 */ + byte TXE2 :1; /* Transmitter Buffer Empty 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpTXE :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN4TFLGSTR; +extern volatile CAN4TFLGSTR _CAN4TFLG @(REG_BASE + 0x00000286); +#define CAN4TFLG _CAN4TFLG.Byte +#define CAN4TFLG_TXE0 _CAN4TFLG.Bits.TXE0 +#define CAN4TFLG_TXE1 _CAN4TFLG.Bits.TXE1 +#define CAN4TFLG_TXE2 _CAN4TFLG.Bits.TXE2 +#define CAN4TFLG_TXE _CAN4TFLG.MergedBits.grpTXE + + +/*** CAN4TIER - MSCAN4 Transmitter Interrupt Enable Register; 0x00000287 ***/ +typedef union { + byte Byte; + struct { + byte TXEIE0 :1; /* Transmitter Empty Interrupt Enable 0 */ + byte TXEIE1 :1; /* Transmitter Empty Interrupt Enable 1 */ + byte TXEIE2 :1; /* Transmitter Empty Interrupt Enable 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpTXEIE :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN4TIERSTR; +extern volatile CAN4TIERSTR _CAN4TIER @(REG_BASE + 0x00000287); +#define CAN4TIER _CAN4TIER.Byte +#define CAN4TIER_TXEIE0 _CAN4TIER.Bits.TXEIE0 +#define CAN4TIER_TXEIE1 _CAN4TIER.Bits.TXEIE1 +#define CAN4TIER_TXEIE2 _CAN4TIER.Bits.TXEIE2 +#define CAN4TIER_TXEIE _CAN4TIER.MergedBits.grpTXEIE + + +/*** CAN4TARQ - MSCAN 4 Transmitter Message Abort Request; 0x00000288 ***/ +typedef union { + byte Byte; + struct { + byte ABTRQ0 :1; /* Abort Request 0 */ + byte ABTRQ1 :1; /* Abort Request 1 */ + byte ABTRQ2 :1; /* Abort Request 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpABTRQ :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN4TARQSTR; +extern volatile CAN4TARQSTR _CAN4TARQ @(REG_BASE + 0x00000288); +#define CAN4TARQ _CAN4TARQ.Byte +#define CAN4TARQ_ABTRQ0 _CAN4TARQ.Bits.ABTRQ0 +#define CAN4TARQ_ABTRQ1 _CAN4TARQ.Bits.ABTRQ1 +#define CAN4TARQ_ABTRQ2 _CAN4TARQ.Bits.ABTRQ2 +#define CAN4TARQ_ABTRQ _CAN4TARQ.MergedBits.grpABTRQ + + +/*** CAN4TAAK - MSCAN4 Transmitter Message Abort Control; 0x00000289 ***/ +typedef union { + byte Byte; + struct { + byte ABTAK0 :1; /* Abort Acknowledge 0 */ + byte ABTAK1 :1; /* Abort Acknowledge 1 */ + byte ABTAK2 :1; /* Abort Acknowledge 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpABTAK :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN4TAAKSTR; +extern volatile CAN4TAAKSTR _CAN4TAAK @(REG_BASE + 0x00000289); +#define CAN4TAAK _CAN4TAAK.Byte +#define CAN4TAAK_ABTAK0 _CAN4TAAK.Bits.ABTAK0 +#define CAN4TAAK_ABTAK1 _CAN4TAAK.Bits.ABTAK1 +#define CAN4TAAK_ABTAK2 _CAN4TAAK.Bits.ABTAK2 +#define CAN4TAAK_ABTAK _CAN4TAAK.MergedBits.grpABTAK + + +/*** CAN4TBSEL - MSCAN4 Transmit Buffer Selection; 0x0000028A ***/ +typedef union { + byte Byte; + struct { + byte TX0 :1; /* Transmit Buffer Select 0 */ + byte TX1 :1; /* Transmit Buffer Select 1 */ + byte TX2 :1; /* Transmit Buffer Select 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpTX :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN4TBSELSTR; +extern volatile CAN4TBSELSTR _CAN4TBSEL @(REG_BASE + 0x0000028A); +#define CAN4TBSEL _CAN4TBSEL.Byte +#define CAN4TBSEL_TX0 _CAN4TBSEL.Bits.TX0 +#define CAN4TBSEL_TX1 _CAN4TBSEL.Bits.TX1 +#define CAN4TBSEL_TX2 _CAN4TBSEL.Bits.TX2 +#define CAN4TBSEL_TX _CAN4TBSEL.MergedBits.grpTX + + +/*** CAN4IDAC - MSCAN4 Identifier Acceptance Control Register; 0x0000028B ***/ +typedef union { + byte Byte; + struct { + byte IDHIT0 :1; /* Identifier Acceptance Hit Indicator 0 */ + byte IDHIT1 :1; /* Identifier Acceptance Hit Indicator 1 */ + byte IDHIT2 :1; /* Identifier Acceptance Hit Indicator 2 */ + byte :1; + byte IDAM0 :1; /* Identifier Acceptance Mode 0 */ + byte IDAM1 :1; /* Identifier Acceptance Mode 1 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpIDHIT :3; + byte :1; + byte grpIDAM :2; + byte :1; + byte :1; + } MergedBits; +} CAN4IDACSTR; +extern volatile CAN4IDACSTR _CAN4IDAC @(REG_BASE + 0x0000028B); +#define CAN4IDAC _CAN4IDAC.Byte +#define CAN4IDAC_IDHIT0 _CAN4IDAC.Bits.IDHIT0 +#define CAN4IDAC_IDHIT1 _CAN4IDAC.Bits.IDHIT1 +#define CAN4IDAC_IDHIT2 _CAN4IDAC.Bits.IDHIT2 +#define CAN4IDAC_IDAM0 _CAN4IDAC.Bits.IDAM0 +#define CAN4IDAC_IDAM1 _CAN4IDAC.Bits.IDAM1 +#define CAN4IDAC_IDHIT _CAN4IDAC.MergedBits.grpIDHIT +#define CAN4IDAC_IDAM _CAN4IDAC.MergedBits.grpIDAM + + +/*** CAN4RXERR - MSCAN4 Receive Error Counter Register; 0x0000028E ***/ +typedef union { + byte Byte; + struct { + byte RXERR0 :1; /* Bit 0 */ + byte RXERR1 :1; /* Bit 1 */ + byte RXERR2 :1; /* Bit 2 */ + byte RXERR3 :1; /* Bit 3 */ + byte RXERR4 :1; /* Bit 4 */ + byte RXERR5 :1; /* Bit 5 */ + byte RXERR6 :1; /* Bit 6 */ + byte RXERR7 :1; /* Bit 7 */ + } Bits; + struct { + byte grpRXERR :8; + } MergedBits; +} CAN4RXERRSTR; +extern volatile CAN4RXERRSTR _CAN4RXERR @(REG_BASE + 0x0000028E); +#define CAN4RXERR _CAN4RXERR.Byte +#define CAN4RXERR_RXERR0 _CAN4RXERR.Bits.RXERR0 +#define CAN4RXERR_RXERR1 _CAN4RXERR.Bits.RXERR1 +#define CAN4RXERR_RXERR2 _CAN4RXERR.Bits.RXERR2 +#define CAN4RXERR_RXERR3 _CAN4RXERR.Bits.RXERR3 +#define CAN4RXERR_RXERR4 _CAN4RXERR.Bits.RXERR4 +#define CAN4RXERR_RXERR5 _CAN4RXERR.Bits.RXERR5 +#define CAN4RXERR_RXERR6 _CAN4RXERR.Bits.RXERR6 +#define CAN4RXERR_RXERR7 _CAN4RXERR.Bits.RXERR7 +#define CAN4RXERR_RXERR _CAN4RXERR.MergedBits.grpRXERR + + +/*** CAN4TXERR - MSCAN4 Transmit Error Counter Register; 0x0000028F ***/ +typedef union { + byte Byte; + struct { + byte TXERR0 :1; /* Bit 0 */ + byte TXERR1 :1; /* Bit 1 */ + byte TXERR2 :1; /* Bit 2 */ + byte TXERR3 :1; /* Bit 3 */ + byte TXERR4 :1; /* Bit 4 */ + byte TXERR5 :1; /* Bit 5 */ + byte TXERR6 :1; /* Bit 6 */ + byte TXERR7 :1; /* Bit 7 */ + } Bits; + struct { + byte grpTXERR :8; + } MergedBits; +} CAN4TXERRSTR; +extern volatile CAN4TXERRSTR _CAN4TXERR @(REG_BASE + 0x0000028F); +#define CAN4TXERR _CAN4TXERR.Byte +#define CAN4TXERR_TXERR0 _CAN4TXERR.Bits.TXERR0 +#define CAN4TXERR_TXERR1 _CAN4TXERR.Bits.TXERR1 +#define CAN4TXERR_TXERR2 _CAN4TXERR.Bits.TXERR2 +#define CAN4TXERR_TXERR3 _CAN4TXERR.Bits.TXERR3 +#define CAN4TXERR_TXERR4 _CAN4TXERR.Bits.TXERR4 +#define CAN4TXERR_TXERR5 _CAN4TXERR.Bits.TXERR5 +#define CAN4TXERR_TXERR6 _CAN4TXERR.Bits.TXERR6 +#define CAN4TXERR_TXERR7 _CAN4TXERR.Bits.TXERR7 +#define CAN4TXERR_TXERR _CAN4TXERR.MergedBits.grpTXERR + + +/*** CAN4IDAR0 - MSCAN4 Identifier Acceptance Register 0; 0x00000290 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN4IDAR0STR; +extern volatile CAN4IDAR0STR _CAN4IDAR0 @(REG_BASE + 0x00000290); +#define CAN4IDAR0 _CAN4IDAR0.Byte +#define CAN4IDAR0_AC0 _CAN4IDAR0.Bits.AC0 +#define CAN4IDAR0_AC1 _CAN4IDAR0.Bits.AC1 +#define CAN4IDAR0_AC2 _CAN4IDAR0.Bits.AC2 +#define CAN4IDAR0_AC3 _CAN4IDAR0.Bits.AC3 +#define CAN4IDAR0_AC4 _CAN4IDAR0.Bits.AC4 +#define CAN4IDAR0_AC5 _CAN4IDAR0.Bits.AC5 +#define CAN4IDAR0_AC6 _CAN4IDAR0.Bits.AC6 +#define CAN4IDAR0_AC7 _CAN4IDAR0.Bits.AC7 +#define CAN4IDAR0_AC _CAN4IDAR0.MergedBits.grpAC + + +/*** CAN4IDAR1 - MSCAN4 Identifier Acceptance Register 1; 0x00000291 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN4IDAR1STR; +extern volatile CAN4IDAR1STR _CAN4IDAR1 @(REG_BASE + 0x00000291); +#define CAN4IDAR1 _CAN4IDAR1.Byte +#define CAN4IDAR1_AC0 _CAN4IDAR1.Bits.AC0 +#define CAN4IDAR1_AC1 _CAN4IDAR1.Bits.AC1 +#define CAN4IDAR1_AC2 _CAN4IDAR1.Bits.AC2 +#define CAN4IDAR1_AC3 _CAN4IDAR1.Bits.AC3 +#define CAN4IDAR1_AC4 _CAN4IDAR1.Bits.AC4 +#define CAN4IDAR1_AC5 _CAN4IDAR1.Bits.AC5 +#define CAN4IDAR1_AC6 _CAN4IDAR1.Bits.AC6 +#define CAN4IDAR1_AC7 _CAN4IDAR1.Bits.AC7 +#define CAN4IDAR1_AC _CAN4IDAR1.MergedBits.grpAC + + +/*** CAN4IDAR2 - MSCAN4 Identifier Acceptance Register 2; 0x00000292 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN4IDAR2STR; +extern volatile CAN4IDAR2STR _CAN4IDAR2 @(REG_BASE + 0x00000292); +#define CAN4IDAR2 _CAN4IDAR2.Byte +#define CAN4IDAR2_AC0 _CAN4IDAR2.Bits.AC0 +#define CAN4IDAR2_AC1 _CAN4IDAR2.Bits.AC1 +#define CAN4IDAR2_AC2 _CAN4IDAR2.Bits.AC2 +#define CAN4IDAR2_AC3 _CAN4IDAR2.Bits.AC3 +#define CAN4IDAR2_AC4 _CAN4IDAR2.Bits.AC4 +#define CAN4IDAR2_AC5 _CAN4IDAR2.Bits.AC5 +#define CAN4IDAR2_AC6 _CAN4IDAR2.Bits.AC6 +#define CAN4IDAR2_AC7 _CAN4IDAR2.Bits.AC7 +#define CAN4IDAR2_AC _CAN4IDAR2.MergedBits.grpAC + + +/*** CAN4IDAR3 - MSCAN4 Identifier Acceptance Register 3; 0x00000293 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN4IDAR3STR; +extern volatile CAN4IDAR3STR _CAN4IDAR3 @(REG_BASE + 0x00000293); +#define CAN4IDAR3 _CAN4IDAR3.Byte +#define CAN4IDAR3_AC0 _CAN4IDAR3.Bits.AC0 +#define CAN4IDAR3_AC1 _CAN4IDAR3.Bits.AC1 +#define CAN4IDAR3_AC2 _CAN4IDAR3.Bits.AC2 +#define CAN4IDAR3_AC3 _CAN4IDAR3.Bits.AC3 +#define CAN4IDAR3_AC4 _CAN4IDAR3.Bits.AC4 +#define CAN4IDAR3_AC5 _CAN4IDAR3.Bits.AC5 +#define CAN4IDAR3_AC6 _CAN4IDAR3.Bits.AC6 +#define CAN4IDAR3_AC7 _CAN4IDAR3.Bits.AC7 +#define CAN4IDAR3_AC _CAN4IDAR3.MergedBits.grpAC + + +/*** CAN4IDMR0 - MSCAN4 Identifier Mask Register 0; 0x00000294 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN4IDMR0STR; +extern volatile CAN4IDMR0STR _CAN4IDMR0 @(REG_BASE + 0x00000294); +#define CAN4IDMR0 _CAN4IDMR0.Byte +#define CAN4IDMR0_AM0 _CAN4IDMR0.Bits.AM0 +#define CAN4IDMR0_AM1 _CAN4IDMR0.Bits.AM1 +#define CAN4IDMR0_AM2 _CAN4IDMR0.Bits.AM2 +#define CAN4IDMR0_AM3 _CAN4IDMR0.Bits.AM3 +#define CAN4IDMR0_AM4 _CAN4IDMR0.Bits.AM4 +#define CAN4IDMR0_AM5 _CAN4IDMR0.Bits.AM5 +#define CAN4IDMR0_AM6 _CAN4IDMR0.Bits.AM6 +#define CAN4IDMR0_AM7 _CAN4IDMR0.Bits.AM7 +#define CAN4IDMR0_AM _CAN4IDMR0.MergedBits.grpAM + + +/*** CAN4IDMR1 - MSCAN4 Identifier Mask Register 1; 0x00000295 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN4IDMR1STR; +extern volatile CAN4IDMR1STR _CAN4IDMR1 @(REG_BASE + 0x00000295); +#define CAN4IDMR1 _CAN4IDMR1.Byte +#define CAN4IDMR1_AM0 _CAN4IDMR1.Bits.AM0 +#define CAN4IDMR1_AM1 _CAN4IDMR1.Bits.AM1 +#define CAN4IDMR1_AM2 _CAN4IDMR1.Bits.AM2 +#define CAN4IDMR1_AM3 _CAN4IDMR1.Bits.AM3 +#define CAN4IDMR1_AM4 _CAN4IDMR1.Bits.AM4 +#define CAN4IDMR1_AM5 _CAN4IDMR1.Bits.AM5 +#define CAN4IDMR1_AM6 _CAN4IDMR1.Bits.AM6 +#define CAN4IDMR1_AM7 _CAN4IDMR1.Bits.AM7 +#define CAN4IDMR1_AM _CAN4IDMR1.MergedBits.grpAM + + +/*** CAN4IDMR2 - MSCAN4 Identifier Mask Register 2; 0x00000296 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN4IDMR2STR; +extern volatile CAN4IDMR2STR _CAN4IDMR2 @(REG_BASE + 0x00000296); +#define CAN4IDMR2 _CAN4IDMR2.Byte +#define CAN4IDMR2_AM0 _CAN4IDMR2.Bits.AM0 +#define CAN4IDMR2_AM1 _CAN4IDMR2.Bits.AM1 +#define CAN4IDMR2_AM2 _CAN4IDMR2.Bits.AM2 +#define CAN4IDMR2_AM3 _CAN4IDMR2.Bits.AM3 +#define CAN4IDMR2_AM4 _CAN4IDMR2.Bits.AM4 +#define CAN4IDMR2_AM5 _CAN4IDMR2.Bits.AM5 +#define CAN4IDMR2_AM6 _CAN4IDMR2.Bits.AM6 +#define CAN4IDMR2_AM7 _CAN4IDMR2.Bits.AM7 +#define CAN4IDMR2_AM _CAN4IDMR2.MergedBits.grpAM + + +/*** CAN4IDMR3 - MSCAN4 Identifier Mask Register 3; 0x00000297 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN4IDMR3STR; +extern volatile CAN4IDMR3STR _CAN4IDMR3 @(REG_BASE + 0x00000297); +#define CAN4IDMR3 _CAN4IDMR3.Byte +#define CAN4IDMR3_AM0 _CAN4IDMR3.Bits.AM0 +#define CAN4IDMR3_AM1 _CAN4IDMR3.Bits.AM1 +#define CAN4IDMR3_AM2 _CAN4IDMR3.Bits.AM2 +#define CAN4IDMR3_AM3 _CAN4IDMR3.Bits.AM3 +#define CAN4IDMR3_AM4 _CAN4IDMR3.Bits.AM4 +#define CAN4IDMR3_AM5 _CAN4IDMR3.Bits.AM5 +#define CAN4IDMR3_AM6 _CAN4IDMR3.Bits.AM6 +#define CAN4IDMR3_AM7 _CAN4IDMR3.Bits.AM7 +#define CAN4IDMR3_AM _CAN4IDMR3.MergedBits.grpAM + + +/*** CAN4IDAR4 - MSCAN4 Identifier Acceptance Register 4; 0x00000298 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN4IDAR4STR; +extern volatile CAN4IDAR4STR _CAN4IDAR4 @(REG_BASE + 0x00000298); +#define CAN4IDAR4 _CAN4IDAR4.Byte +#define CAN4IDAR4_AC0 _CAN4IDAR4.Bits.AC0 +#define CAN4IDAR4_AC1 _CAN4IDAR4.Bits.AC1 +#define CAN4IDAR4_AC2 _CAN4IDAR4.Bits.AC2 +#define CAN4IDAR4_AC3 _CAN4IDAR4.Bits.AC3 +#define CAN4IDAR4_AC4 _CAN4IDAR4.Bits.AC4 +#define CAN4IDAR4_AC5 _CAN4IDAR4.Bits.AC5 +#define CAN4IDAR4_AC6 _CAN4IDAR4.Bits.AC6 +#define CAN4IDAR4_AC7 _CAN4IDAR4.Bits.AC7 +#define CAN4IDAR4_AC _CAN4IDAR4.MergedBits.grpAC + + +/*** CAN4IDAR5 - MSCAN4 Identifier Acceptance Register 5; 0x00000299 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN4IDAR5STR; +extern volatile CAN4IDAR5STR _CAN4IDAR5 @(REG_BASE + 0x00000299); +#define CAN4IDAR5 _CAN4IDAR5.Byte +#define CAN4IDAR5_AC0 _CAN4IDAR5.Bits.AC0 +#define CAN4IDAR5_AC1 _CAN4IDAR5.Bits.AC1 +#define CAN4IDAR5_AC2 _CAN4IDAR5.Bits.AC2 +#define CAN4IDAR5_AC3 _CAN4IDAR5.Bits.AC3 +#define CAN4IDAR5_AC4 _CAN4IDAR5.Bits.AC4 +#define CAN4IDAR5_AC5 _CAN4IDAR5.Bits.AC5 +#define CAN4IDAR5_AC6 _CAN4IDAR5.Bits.AC6 +#define CAN4IDAR5_AC7 _CAN4IDAR5.Bits.AC7 +#define CAN4IDAR5_AC _CAN4IDAR5.MergedBits.grpAC + + +/*** CAN4IDAR6 - MSCAN4 Identifier Acceptance Register 6; 0x0000029A ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN4IDAR6STR; +extern volatile CAN4IDAR6STR _CAN4IDAR6 @(REG_BASE + 0x0000029A); +#define CAN4IDAR6 _CAN4IDAR6.Byte +#define CAN4IDAR6_AC0 _CAN4IDAR6.Bits.AC0 +#define CAN4IDAR6_AC1 _CAN4IDAR6.Bits.AC1 +#define CAN4IDAR6_AC2 _CAN4IDAR6.Bits.AC2 +#define CAN4IDAR6_AC3 _CAN4IDAR6.Bits.AC3 +#define CAN4IDAR6_AC4 _CAN4IDAR6.Bits.AC4 +#define CAN4IDAR6_AC5 _CAN4IDAR6.Bits.AC5 +#define CAN4IDAR6_AC6 _CAN4IDAR6.Bits.AC6 +#define CAN4IDAR6_AC7 _CAN4IDAR6.Bits.AC7 +#define CAN4IDAR6_AC _CAN4IDAR6.MergedBits.grpAC + + +/*** CAN4IDAR7 - MSCAN4 Identifier Acceptance Register 7; 0x0000029B ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CAN4IDAR7STR; +extern volatile CAN4IDAR7STR _CAN4IDAR7 @(REG_BASE + 0x0000029B); +#define CAN4IDAR7 _CAN4IDAR7.Byte +#define CAN4IDAR7_AC0 _CAN4IDAR7.Bits.AC0 +#define CAN4IDAR7_AC1 _CAN4IDAR7.Bits.AC1 +#define CAN4IDAR7_AC2 _CAN4IDAR7.Bits.AC2 +#define CAN4IDAR7_AC3 _CAN4IDAR7.Bits.AC3 +#define CAN4IDAR7_AC4 _CAN4IDAR7.Bits.AC4 +#define CAN4IDAR7_AC5 _CAN4IDAR7.Bits.AC5 +#define CAN4IDAR7_AC6 _CAN4IDAR7.Bits.AC6 +#define CAN4IDAR7_AC7 _CAN4IDAR7.Bits.AC7 +#define CAN4IDAR7_AC _CAN4IDAR7.MergedBits.grpAC + + +/*** CAN4IDMR4 - MSCAN4 Identifier Mask Register 4; 0x0000029C ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN4IDMR4STR; +extern volatile CAN4IDMR4STR _CAN4IDMR4 @(REG_BASE + 0x0000029C); +#define CAN4IDMR4 _CAN4IDMR4.Byte +#define CAN4IDMR4_AM0 _CAN4IDMR4.Bits.AM0 +#define CAN4IDMR4_AM1 _CAN4IDMR4.Bits.AM1 +#define CAN4IDMR4_AM2 _CAN4IDMR4.Bits.AM2 +#define CAN4IDMR4_AM3 _CAN4IDMR4.Bits.AM3 +#define CAN4IDMR4_AM4 _CAN4IDMR4.Bits.AM4 +#define CAN4IDMR4_AM5 _CAN4IDMR4.Bits.AM5 +#define CAN4IDMR4_AM6 _CAN4IDMR4.Bits.AM6 +#define CAN4IDMR4_AM7 _CAN4IDMR4.Bits.AM7 +#define CAN4IDMR4_AM _CAN4IDMR4.MergedBits.grpAM + + +/*** CAN4IDMR5 - MSCAN4 Identifier Mask Register 5; 0x0000029D ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN4IDMR5STR; +extern volatile CAN4IDMR5STR _CAN4IDMR5 @(REG_BASE + 0x0000029D); +#define CAN4IDMR5 _CAN4IDMR5.Byte +#define CAN4IDMR5_AM0 _CAN4IDMR5.Bits.AM0 +#define CAN4IDMR5_AM1 _CAN4IDMR5.Bits.AM1 +#define CAN4IDMR5_AM2 _CAN4IDMR5.Bits.AM2 +#define CAN4IDMR5_AM3 _CAN4IDMR5.Bits.AM3 +#define CAN4IDMR5_AM4 _CAN4IDMR5.Bits.AM4 +#define CAN4IDMR5_AM5 _CAN4IDMR5.Bits.AM5 +#define CAN4IDMR5_AM6 _CAN4IDMR5.Bits.AM6 +#define CAN4IDMR5_AM7 _CAN4IDMR5.Bits.AM7 +#define CAN4IDMR5_AM _CAN4IDMR5.MergedBits.grpAM + + +/*** CAN4IDMR6 - MSCAN4 Identifier Mask Register 6; 0x0000029E ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN4IDMR6STR; +extern volatile CAN4IDMR6STR _CAN4IDMR6 @(REG_BASE + 0x0000029E); +#define CAN4IDMR6 _CAN4IDMR6.Byte +#define CAN4IDMR6_AM0 _CAN4IDMR6.Bits.AM0 +#define CAN4IDMR6_AM1 _CAN4IDMR6.Bits.AM1 +#define CAN4IDMR6_AM2 _CAN4IDMR6.Bits.AM2 +#define CAN4IDMR6_AM3 _CAN4IDMR6.Bits.AM3 +#define CAN4IDMR6_AM4 _CAN4IDMR6.Bits.AM4 +#define CAN4IDMR6_AM5 _CAN4IDMR6.Bits.AM5 +#define CAN4IDMR6_AM6 _CAN4IDMR6.Bits.AM6 +#define CAN4IDMR6_AM7 _CAN4IDMR6.Bits.AM7 +#define CAN4IDMR6_AM _CAN4IDMR6.MergedBits.grpAM + + +/*** CAN4IDMR7 - MSCAN4 Identifier Mask Register 7; 0x0000029F ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CAN4IDMR7STR; +extern volatile CAN4IDMR7STR _CAN4IDMR7 @(REG_BASE + 0x0000029F); +#define CAN4IDMR7 _CAN4IDMR7.Byte +#define CAN4IDMR7_AM0 _CAN4IDMR7.Bits.AM0 +#define CAN4IDMR7_AM1 _CAN4IDMR7.Bits.AM1 +#define CAN4IDMR7_AM2 _CAN4IDMR7.Bits.AM2 +#define CAN4IDMR7_AM3 _CAN4IDMR7.Bits.AM3 +#define CAN4IDMR7_AM4 _CAN4IDMR7.Bits.AM4 +#define CAN4IDMR7_AM5 _CAN4IDMR7.Bits.AM5 +#define CAN4IDMR7_AM6 _CAN4IDMR7.Bits.AM6 +#define CAN4IDMR7_AM7 _CAN4IDMR7.Bits.AM7 +#define CAN4IDMR7_AM _CAN4IDMR7.MergedBits.grpAM + + +/*** CAN4RXIDR0 - MSCAN4 Receive Identifier Register 0; 0x000002A0 ***/ +typedef union { + byte Byte; + struct { + byte ID21 :1; /* Extended format identifier Bit 21 */ + byte ID22 :1; /* Extended format identifier Bit 22 */ + byte ID23 :1; /* Extended format identifier Bit 23 */ + byte ID24 :1; /* Extended format identifier Bit 24 */ + byte ID25 :1; /* Extended format identifier Bit 25 */ + byte ID26 :1; /* Extended format identifier Bit 26 */ + byte ID27 :1; /* Extended format identifier Bit 27 */ + byte ID28 :1; /* Extended format identifier Bit 28 */ + } Bits; + struct { + byte grpID_21 :8; + } MergedBits; +} CAN4RXIDR0STR; +extern volatile CAN4RXIDR0STR _CAN4RXIDR0 @(REG_BASE + 0x000002A0); +#define CAN4RXIDR0 _CAN4RXIDR0.Byte +#define CAN4RXIDR0_ID21 _CAN4RXIDR0.Bits.ID21 +#define CAN4RXIDR0_ID22 _CAN4RXIDR0.Bits.ID22 +#define CAN4RXIDR0_ID23 _CAN4RXIDR0.Bits.ID23 +#define CAN4RXIDR0_ID24 _CAN4RXIDR0.Bits.ID24 +#define CAN4RXIDR0_ID25 _CAN4RXIDR0.Bits.ID25 +#define CAN4RXIDR0_ID26 _CAN4RXIDR0.Bits.ID26 +#define CAN4RXIDR0_ID27 _CAN4RXIDR0.Bits.ID27 +#define CAN4RXIDR0_ID28 _CAN4RXIDR0.Bits.ID28 +#define CAN4RXIDR0_ID_21 _CAN4RXIDR0.MergedBits.grpID_21 +#define CAN4RXIDR0_ID CAN4RXIDR0_ID_21 + + +/*** CAN4RXIDR1 - MSCAN4 Receive Identifier Register 1; 0x000002A1 ***/ +typedef union { + byte Byte; + struct { + byte ID15 :1; /* Extended format identifier Bit 15 */ + byte ID16 :1; /* Extended format identifier Bit 16 */ + byte ID17 :1; /* Extended format identifier Bit 17 */ + byte IDE :1; /* ID Extended */ + byte SRR :1; /* Substitute Remote Request */ + byte ID18 :1; /* Extended format identifier Bit 18 */ + byte ID19 :1; /* Extended format identifier Bit 19 */ + byte ID20 :1; /* Extended format identifier Bit 20 */ + } Bits; + struct { + byte grpID_15 :3; + byte :1; + byte :1; + byte grpID_18 :3; + } MergedBits; +} CAN4RXIDR1STR; +extern volatile CAN4RXIDR1STR _CAN4RXIDR1 @(REG_BASE + 0x000002A1); +#define CAN4RXIDR1 _CAN4RXIDR1.Byte +#define CAN4RXIDR1_ID15 _CAN4RXIDR1.Bits.ID15 +#define CAN4RXIDR1_ID16 _CAN4RXIDR1.Bits.ID16 +#define CAN4RXIDR1_ID17 _CAN4RXIDR1.Bits.ID17 +#define CAN4RXIDR1_IDE _CAN4RXIDR1.Bits.IDE +#define CAN4RXIDR1_SRR _CAN4RXIDR1.Bits.SRR +#define CAN4RXIDR1_ID18 _CAN4RXIDR1.Bits.ID18 +#define CAN4RXIDR1_ID19 _CAN4RXIDR1.Bits.ID19 +#define CAN4RXIDR1_ID20 _CAN4RXIDR1.Bits.ID20 +#define CAN4RXIDR1_ID_15 _CAN4RXIDR1.MergedBits.grpID_15 +#define CAN4RXIDR1_ID_18 _CAN4RXIDR1.MergedBits.grpID_18 +#define CAN4RXIDR1_ID CAN4RXIDR1_ID_15 + + +/*** CAN4RXIDR2 - MSCAN4 Receive Identifier Register 2; 0x000002A2 ***/ +typedef union { + byte Byte; + struct { + byte ID7 :1; /* Extended format identifier Bit 7 */ + byte ID8 :1; /* Extended format identifier Bit 8 */ + byte ID9 :1; /* Extended format identifier Bit 9 */ + byte ID10 :1; /* Extended format identifier Bit 10 */ + byte ID11 :1; /* Extended format identifier Bit 11 */ + byte ID12 :1; /* Extended format identifier Bit 12 */ + byte ID13 :1; /* Extended format identifier Bit 13 */ + byte ID14 :1; /* Extended format identifier Bit 14 */ + } Bits; + struct { + byte grpID_7 :8; + } MergedBits; +} CAN4RXIDR2STR; +extern volatile CAN4RXIDR2STR _CAN4RXIDR2 @(REG_BASE + 0x000002A2); +#define CAN4RXIDR2 _CAN4RXIDR2.Byte +#define CAN4RXIDR2_ID7 _CAN4RXIDR2.Bits.ID7 +#define CAN4RXIDR2_ID8 _CAN4RXIDR2.Bits.ID8 +#define CAN4RXIDR2_ID9 _CAN4RXIDR2.Bits.ID9 +#define CAN4RXIDR2_ID10 _CAN4RXIDR2.Bits.ID10 +#define CAN4RXIDR2_ID11 _CAN4RXIDR2.Bits.ID11 +#define CAN4RXIDR2_ID12 _CAN4RXIDR2.Bits.ID12 +#define CAN4RXIDR2_ID13 _CAN4RXIDR2.Bits.ID13 +#define CAN4RXIDR2_ID14 _CAN4RXIDR2.Bits.ID14 +#define CAN4RXIDR2_ID_7 _CAN4RXIDR2.MergedBits.grpID_7 +#define CAN4RXIDR2_ID CAN4RXIDR2_ID_7 + + +/*** CAN4RXIDR3 - MSCAN4 Receive Identifier Register 3; 0x000002A3 ***/ +typedef union { + byte Byte; + struct { + byte RTR :1; /* Remote Transmission Request */ + byte ID0 :1; /* Extended format identifier Bit 0 */ + byte ID1 :1; /* Extended format identifier Bit 1 */ + byte ID2 :1; /* Extended format identifier Bit 2 */ + byte ID3 :1; /* Extended format identifier Bit 3 */ + byte ID4 :1; /* Extended format identifier Bit 4 */ + byte ID5 :1; /* Extended format identifier Bit 5 */ + byte ID6 :1; /* Extended format identifier Bit 6 */ + } Bits; + struct { + byte :1; + byte grpID :7; + } MergedBits; +} CAN4RXIDR3STR; +extern volatile CAN4RXIDR3STR _CAN4RXIDR3 @(REG_BASE + 0x000002A3); +#define CAN4RXIDR3 _CAN4RXIDR3.Byte +#define CAN4RXIDR3_RTR _CAN4RXIDR3.Bits.RTR +#define CAN4RXIDR3_ID0 _CAN4RXIDR3.Bits.ID0 +#define CAN4RXIDR3_ID1 _CAN4RXIDR3.Bits.ID1 +#define CAN4RXIDR3_ID2 _CAN4RXIDR3.Bits.ID2 +#define CAN4RXIDR3_ID3 _CAN4RXIDR3.Bits.ID3 +#define CAN4RXIDR3_ID4 _CAN4RXIDR3.Bits.ID4 +#define CAN4RXIDR3_ID5 _CAN4RXIDR3.Bits.ID5 +#define CAN4RXIDR3_ID6 _CAN4RXIDR3.Bits.ID6 +#define CAN4RXIDR3_ID _CAN4RXIDR3.MergedBits.grpID + + +/*** CAN4RXDSR0 - MSCAN4 Receive Data Segment Register 0; 0x000002A4 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN4RXDSR0STR; +extern volatile CAN4RXDSR0STR _CAN4RXDSR0 @(REG_BASE + 0x000002A4); +#define CAN4RXDSR0 _CAN4RXDSR0.Byte +#define CAN4RXDSR0_DB0 _CAN4RXDSR0.Bits.DB0 +#define CAN4RXDSR0_DB1 _CAN4RXDSR0.Bits.DB1 +#define CAN4RXDSR0_DB2 _CAN4RXDSR0.Bits.DB2 +#define CAN4RXDSR0_DB3 _CAN4RXDSR0.Bits.DB3 +#define CAN4RXDSR0_DB4 _CAN4RXDSR0.Bits.DB4 +#define CAN4RXDSR0_DB5 _CAN4RXDSR0.Bits.DB5 +#define CAN4RXDSR0_DB6 _CAN4RXDSR0.Bits.DB6 +#define CAN4RXDSR0_DB7 _CAN4RXDSR0.Bits.DB7 +#define CAN4RXDSR0_DB _CAN4RXDSR0.MergedBits.grpDB + + +/*** CAN4RXDSR1 - MSCAN4 Receive Data Segment Register 1; 0x000002A5 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN4RXDSR1STR; +extern volatile CAN4RXDSR1STR _CAN4RXDSR1 @(REG_BASE + 0x000002A5); +#define CAN4RXDSR1 _CAN4RXDSR1.Byte +#define CAN4RXDSR1_DB0 _CAN4RXDSR1.Bits.DB0 +#define CAN4RXDSR1_DB1 _CAN4RXDSR1.Bits.DB1 +#define CAN4RXDSR1_DB2 _CAN4RXDSR1.Bits.DB2 +#define CAN4RXDSR1_DB3 _CAN4RXDSR1.Bits.DB3 +#define CAN4RXDSR1_DB4 _CAN4RXDSR1.Bits.DB4 +#define CAN4RXDSR1_DB5 _CAN4RXDSR1.Bits.DB5 +#define CAN4RXDSR1_DB6 _CAN4RXDSR1.Bits.DB6 +#define CAN4RXDSR1_DB7 _CAN4RXDSR1.Bits.DB7 +#define CAN4RXDSR1_DB _CAN4RXDSR1.MergedBits.grpDB + + +/*** CAN4RXDSR2 - MSCAN4 Receive Data Segment Register 2; 0x000002A6 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN4RXDSR2STR; +extern volatile CAN4RXDSR2STR _CAN4RXDSR2 @(REG_BASE + 0x000002A6); +#define CAN4RXDSR2 _CAN4RXDSR2.Byte +#define CAN4RXDSR2_DB0 _CAN4RXDSR2.Bits.DB0 +#define CAN4RXDSR2_DB1 _CAN4RXDSR2.Bits.DB1 +#define CAN4RXDSR2_DB2 _CAN4RXDSR2.Bits.DB2 +#define CAN4RXDSR2_DB3 _CAN4RXDSR2.Bits.DB3 +#define CAN4RXDSR2_DB4 _CAN4RXDSR2.Bits.DB4 +#define CAN4RXDSR2_DB5 _CAN4RXDSR2.Bits.DB5 +#define CAN4RXDSR2_DB6 _CAN4RXDSR2.Bits.DB6 +#define CAN4RXDSR2_DB7 _CAN4RXDSR2.Bits.DB7 +#define CAN4RXDSR2_DB _CAN4RXDSR2.MergedBits.grpDB + + +/*** CAN4RXDSR3 - MSCAN4 Receive Data Segment Register 3; 0x000002A7 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN4RXDSR3STR; +extern volatile CAN4RXDSR3STR _CAN4RXDSR3 @(REG_BASE + 0x000002A7); +#define CAN4RXDSR3 _CAN4RXDSR3.Byte +#define CAN4RXDSR3_DB0 _CAN4RXDSR3.Bits.DB0 +#define CAN4RXDSR3_DB1 _CAN4RXDSR3.Bits.DB1 +#define CAN4RXDSR3_DB2 _CAN4RXDSR3.Bits.DB2 +#define CAN4RXDSR3_DB3 _CAN4RXDSR3.Bits.DB3 +#define CAN4RXDSR3_DB4 _CAN4RXDSR3.Bits.DB4 +#define CAN4RXDSR3_DB5 _CAN4RXDSR3.Bits.DB5 +#define CAN4RXDSR3_DB6 _CAN4RXDSR3.Bits.DB6 +#define CAN4RXDSR3_DB7 _CAN4RXDSR3.Bits.DB7 +#define CAN4RXDSR3_DB _CAN4RXDSR3.MergedBits.grpDB + + +/*** CAN4RXDSR4 - MSCAN4 Receive Data Segment Register 4; 0x000002A8 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN4RXDSR4STR; +extern volatile CAN4RXDSR4STR _CAN4RXDSR4 @(REG_BASE + 0x000002A8); +#define CAN4RXDSR4 _CAN4RXDSR4.Byte +#define CAN4RXDSR4_DB0 _CAN4RXDSR4.Bits.DB0 +#define CAN4RXDSR4_DB1 _CAN4RXDSR4.Bits.DB1 +#define CAN4RXDSR4_DB2 _CAN4RXDSR4.Bits.DB2 +#define CAN4RXDSR4_DB3 _CAN4RXDSR4.Bits.DB3 +#define CAN4RXDSR4_DB4 _CAN4RXDSR4.Bits.DB4 +#define CAN4RXDSR4_DB5 _CAN4RXDSR4.Bits.DB5 +#define CAN4RXDSR4_DB6 _CAN4RXDSR4.Bits.DB6 +#define CAN4RXDSR4_DB7 _CAN4RXDSR4.Bits.DB7 +#define CAN4RXDSR4_DB _CAN4RXDSR4.MergedBits.grpDB + + +/*** CAN4RXDSR5 - MSCAN4 Receive Data Segment Register 5; 0x000002A9 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN4RXDSR5STR; +extern volatile CAN4RXDSR5STR _CAN4RXDSR5 @(REG_BASE + 0x000002A9); +#define CAN4RXDSR5 _CAN4RXDSR5.Byte +#define CAN4RXDSR5_DB0 _CAN4RXDSR5.Bits.DB0 +#define CAN4RXDSR5_DB1 _CAN4RXDSR5.Bits.DB1 +#define CAN4RXDSR5_DB2 _CAN4RXDSR5.Bits.DB2 +#define CAN4RXDSR5_DB3 _CAN4RXDSR5.Bits.DB3 +#define CAN4RXDSR5_DB4 _CAN4RXDSR5.Bits.DB4 +#define CAN4RXDSR5_DB5 _CAN4RXDSR5.Bits.DB5 +#define CAN4RXDSR5_DB6 _CAN4RXDSR5.Bits.DB6 +#define CAN4RXDSR5_DB7 _CAN4RXDSR5.Bits.DB7 +#define CAN4RXDSR5_DB _CAN4RXDSR5.MergedBits.grpDB + + +/*** CAN4RXDSR6 - MSCAN4 Receive Data Segment Register 6; 0x000002AA ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN4RXDSR6STR; +extern volatile CAN4RXDSR6STR _CAN4RXDSR6 @(REG_BASE + 0x000002AA); +#define CAN4RXDSR6 _CAN4RXDSR6.Byte +#define CAN4RXDSR6_DB0 _CAN4RXDSR6.Bits.DB0 +#define CAN4RXDSR6_DB1 _CAN4RXDSR6.Bits.DB1 +#define CAN4RXDSR6_DB2 _CAN4RXDSR6.Bits.DB2 +#define CAN4RXDSR6_DB3 _CAN4RXDSR6.Bits.DB3 +#define CAN4RXDSR6_DB4 _CAN4RXDSR6.Bits.DB4 +#define CAN4RXDSR6_DB5 _CAN4RXDSR6.Bits.DB5 +#define CAN4RXDSR6_DB6 _CAN4RXDSR6.Bits.DB6 +#define CAN4RXDSR6_DB7 _CAN4RXDSR6.Bits.DB7 +#define CAN4RXDSR6_DB _CAN4RXDSR6.MergedBits.grpDB + + +/*** CAN4RXDSR7 - MSCAN4 Receive Data Segment Register 7; 0x000002AB ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN4RXDSR7STR; +extern volatile CAN4RXDSR7STR _CAN4RXDSR7 @(REG_BASE + 0x000002AB); +#define CAN4RXDSR7 _CAN4RXDSR7.Byte +#define CAN4RXDSR7_DB0 _CAN4RXDSR7.Bits.DB0 +#define CAN4RXDSR7_DB1 _CAN4RXDSR7.Bits.DB1 +#define CAN4RXDSR7_DB2 _CAN4RXDSR7.Bits.DB2 +#define CAN4RXDSR7_DB3 _CAN4RXDSR7.Bits.DB3 +#define CAN4RXDSR7_DB4 _CAN4RXDSR7.Bits.DB4 +#define CAN4RXDSR7_DB5 _CAN4RXDSR7.Bits.DB5 +#define CAN4RXDSR7_DB6 _CAN4RXDSR7.Bits.DB6 +#define CAN4RXDSR7_DB7 _CAN4RXDSR7.Bits.DB7 +#define CAN4RXDSR7_DB _CAN4RXDSR7.MergedBits.grpDB + + +/*** CAN4RXDLR - MSCAN4 Receive Data Length Register; 0x000002AC ***/ +typedef union { + byte Byte; + struct { + byte DLC0 :1; /* Data Length Code Bit 0 */ + byte DLC1 :1; /* Data Length Code Bit 1 */ + byte DLC2 :1; /* Data Length Code Bit 2 */ + byte DLC3 :1; /* Data Length Code Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpDLC :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN4RXDLRSTR; +extern volatile CAN4RXDLRSTR _CAN4RXDLR @(REG_BASE + 0x000002AC); +#define CAN4RXDLR _CAN4RXDLR.Byte +#define CAN4RXDLR_DLC0 _CAN4RXDLR.Bits.DLC0 +#define CAN4RXDLR_DLC1 _CAN4RXDLR.Bits.DLC1 +#define CAN4RXDLR_DLC2 _CAN4RXDLR.Bits.DLC2 +#define CAN4RXDLR_DLC3 _CAN4RXDLR.Bits.DLC3 +#define CAN4RXDLR_DLC _CAN4RXDLR.MergedBits.grpDLC + + +/*** CAN4TXIDR0 - MSCAN4 Transmit Identifier Register 0; 0x000002B0 ***/ +typedef union { + byte Byte; + struct { + byte ID21 :1; /* Extended format identifier Bit 21 */ + byte ID22 :1; /* Extended format identifier Bit 22 */ + byte ID23 :1; /* Extended format identifier Bit 23 */ + byte ID24 :1; /* Extended format identifier Bit 24 */ + byte ID25 :1; /* Extended format identifier Bit 25 */ + byte ID26 :1; /* Extended format identifier Bit 26 */ + byte ID27 :1; /* Extended format identifier Bit 27 */ + byte ID28 :1; /* Extended format identifier Bit 28 */ + } Bits; + struct { + byte grpID_21 :8; + } MergedBits; +} CAN4TXIDR0STR; +extern volatile CAN4TXIDR0STR _CAN4TXIDR0 @(REG_BASE + 0x000002B0); +#define CAN4TXIDR0 _CAN4TXIDR0.Byte +#define CAN4TXIDR0_ID21 _CAN4TXIDR0.Bits.ID21 +#define CAN4TXIDR0_ID22 _CAN4TXIDR0.Bits.ID22 +#define CAN4TXIDR0_ID23 _CAN4TXIDR0.Bits.ID23 +#define CAN4TXIDR0_ID24 _CAN4TXIDR0.Bits.ID24 +#define CAN4TXIDR0_ID25 _CAN4TXIDR0.Bits.ID25 +#define CAN4TXIDR0_ID26 _CAN4TXIDR0.Bits.ID26 +#define CAN4TXIDR0_ID27 _CAN4TXIDR0.Bits.ID27 +#define CAN4TXIDR0_ID28 _CAN4TXIDR0.Bits.ID28 +#define CAN4TXIDR0_ID_21 _CAN4TXIDR0.MergedBits.grpID_21 +#define CAN4TXIDR0_ID CAN4TXIDR0_ID_21 + + +/*** CAN4TXIDR1 - MSCAN4 Transmit Identifier Register 1; 0x000002B1 ***/ +typedef union { + byte Byte; + struct { + byte ID15 :1; /* Extended format identifier Bit 15 */ + byte ID16 :1; /* Extended format identifier Bit 16 */ + byte ID17 :1; /* Extended format identifier Bit 17 */ + byte IDE :1; /* ID Extended */ + byte SRR :1; /* Substitute Remote Request */ + byte ID18 :1; /* Extended format identifier Bit 18 */ + byte ID19 :1; /* Extended format identifier Bit 19 */ + byte ID20 :1; /* Extended format identifier Bit 20 */ + } Bits; + struct { + byte grpID_15 :3; + byte :1; + byte :1; + byte grpID_18 :3; + } MergedBits; +} CAN4TXIDR1STR; +extern volatile CAN4TXIDR1STR _CAN4TXIDR1 @(REG_BASE + 0x000002B1); +#define CAN4TXIDR1 _CAN4TXIDR1.Byte +#define CAN4TXIDR1_ID15 _CAN4TXIDR1.Bits.ID15 +#define CAN4TXIDR1_ID16 _CAN4TXIDR1.Bits.ID16 +#define CAN4TXIDR1_ID17 _CAN4TXIDR1.Bits.ID17 +#define CAN4TXIDR1_IDE _CAN4TXIDR1.Bits.IDE +#define CAN4TXIDR1_SRR _CAN4TXIDR1.Bits.SRR +#define CAN4TXIDR1_ID18 _CAN4TXIDR1.Bits.ID18 +#define CAN4TXIDR1_ID19 _CAN4TXIDR1.Bits.ID19 +#define CAN4TXIDR1_ID20 _CAN4TXIDR1.Bits.ID20 +#define CAN4TXIDR1_ID_15 _CAN4TXIDR1.MergedBits.grpID_15 +#define CAN4TXIDR1_ID_18 _CAN4TXIDR1.MergedBits.grpID_18 +#define CAN4TXIDR1_ID CAN4TXIDR1_ID_15 + + +/*** CAN4TXIDR2 - MSCAN4 Transmit Identifier Register 2; 0x000002B2 ***/ +typedef union { + byte Byte; + struct { + byte ID7 :1; /* Extended format identifier Bit 7 */ + byte ID8 :1; /* Extended format identifier Bit 8 */ + byte ID9 :1; /* Extended format identifier Bit 9 */ + byte ID10 :1; /* Extended format identifier Bit 10 */ + byte ID11 :1; /* Extended format identifier Bit 11 */ + byte ID12 :1; /* Extended format identifier Bit 12 */ + byte ID13 :1; /* Extended format identifier Bit 13 */ + byte ID14 :1; /* Extended format identifier Bit 14 */ + } Bits; + struct { + byte grpID_7 :8; + } MergedBits; +} CAN4TXIDR2STR; +extern volatile CAN4TXIDR2STR _CAN4TXIDR2 @(REG_BASE + 0x000002B2); +#define CAN4TXIDR2 _CAN4TXIDR2.Byte +#define CAN4TXIDR2_ID7 _CAN4TXIDR2.Bits.ID7 +#define CAN4TXIDR2_ID8 _CAN4TXIDR2.Bits.ID8 +#define CAN4TXIDR2_ID9 _CAN4TXIDR2.Bits.ID9 +#define CAN4TXIDR2_ID10 _CAN4TXIDR2.Bits.ID10 +#define CAN4TXIDR2_ID11 _CAN4TXIDR2.Bits.ID11 +#define CAN4TXIDR2_ID12 _CAN4TXIDR2.Bits.ID12 +#define CAN4TXIDR2_ID13 _CAN4TXIDR2.Bits.ID13 +#define CAN4TXIDR2_ID14 _CAN4TXIDR2.Bits.ID14 +#define CAN4TXIDR2_ID_7 _CAN4TXIDR2.MergedBits.grpID_7 +#define CAN4TXIDR2_ID CAN4TXIDR2_ID_7 + + +/*** CAN4TXIDR3 - MSCAN4 Transmit Identifier Register 3; 0x000002B3 ***/ +typedef union { + byte Byte; + struct { + byte RTR :1; /* Remote Transmission Request */ + byte ID0 :1; /* Extended format identifier Bit 0 */ + byte ID1 :1; /* Extended format identifier Bit 1 */ + byte ID2 :1; /* Extended format identifier Bit 2 */ + byte ID3 :1; /* Extended format identifier Bit 3 */ + byte ID4 :1; /* Extended format identifier Bit 4 */ + byte ID5 :1; /* Extended format identifier Bit 5 */ + byte ID6 :1; /* Extended format identifier Bit 6 */ + } Bits; + struct { + byte :1; + byte grpID :7; + } MergedBits; +} CAN4TXIDR3STR; +extern volatile CAN4TXIDR3STR _CAN4TXIDR3 @(REG_BASE + 0x000002B3); +#define CAN4TXIDR3 _CAN4TXIDR3.Byte +#define CAN4TXIDR3_RTR _CAN4TXIDR3.Bits.RTR +#define CAN4TXIDR3_ID0 _CAN4TXIDR3.Bits.ID0 +#define CAN4TXIDR3_ID1 _CAN4TXIDR3.Bits.ID1 +#define CAN4TXIDR3_ID2 _CAN4TXIDR3.Bits.ID2 +#define CAN4TXIDR3_ID3 _CAN4TXIDR3.Bits.ID3 +#define CAN4TXIDR3_ID4 _CAN4TXIDR3.Bits.ID4 +#define CAN4TXIDR3_ID5 _CAN4TXIDR3.Bits.ID5 +#define CAN4TXIDR3_ID6 _CAN4TXIDR3.Bits.ID6 +#define CAN4TXIDR3_ID _CAN4TXIDR3.MergedBits.grpID + + +/*** CAN4TXDSR0 - MSCAN4 Transmit Data Segment Register 0; 0x000002B4 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN4TXDSR0STR; +extern volatile CAN4TXDSR0STR _CAN4TXDSR0 @(REG_BASE + 0x000002B4); +#define CAN4TXDSR0 _CAN4TXDSR0.Byte +#define CAN4TXDSR0_DB0 _CAN4TXDSR0.Bits.DB0 +#define CAN4TXDSR0_DB1 _CAN4TXDSR0.Bits.DB1 +#define CAN4TXDSR0_DB2 _CAN4TXDSR0.Bits.DB2 +#define CAN4TXDSR0_DB3 _CAN4TXDSR0.Bits.DB3 +#define CAN4TXDSR0_DB4 _CAN4TXDSR0.Bits.DB4 +#define CAN4TXDSR0_DB5 _CAN4TXDSR0.Bits.DB5 +#define CAN4TXDSR0_DB6 _CAN4TXDSR0.Bits.DB6 +#define CAN4TXDSR0_DB7 _CAN4TXDSR0.Bits.DB7 +#define CAN4TXDSR0_DB _CAN4TXDSR0.MergedBits.grpDB + + +/*** CAN4TXDSR1 - MSCAN4 Transmit Data Segment Register 1; 0x000002B5 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN4TXDSR1STR; +extern volatile CAN4TXDSR1STR _CAN4TXDSR1 @(REG_BASE + 0x000002B5); +#define CAN4TXDSR1 _CAN4TXDSR1.Byte +#define CAN4TXDSR1_DB0 _CAN4TXDSR1.Bits.DB0 +#define CAN4TXDSR1_DB1 _CAN4TXDSR1.Bits.DB1 +#define CAN4TXDSR1_DB2 _CAN4TXDSR1.Bits.DB2 +#define CAN4TXDSR1_DB3 _CAN4TXDSR1.Bits.DB3 +#define CAN4TXDSR1_DB4 _CAN4TXDSR1.Bits.DB4 +#define CAN4TXDSR1_DB5 _CAN4TXDSR1.Bits.DB5 +#define CAN4TXDSR1_DB6 _CAN4TXDSR1.Bits.DB6 +#define CAN4TXDSR1_DB7 _CAN4TXDSR1.Bits.DB7 +#define CAN4TXDSR1_DB _CAN4TXDSR1.MergedBits.grpDB + + +/*** CAN4TXDSR2 - MSCAN4 Transmit Data Segment Register 2; 0x000002B6 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN4TXDSR2STR; +extern volatile CAN4TXDSR2STR _CAN4TXDSR2 @(REG_BASE + 0x000002B6); +#define CAN4TXDSR2 _CAN4TXDSR2.Byte +#define CAN4TXDSR2_DB0 _CAN4TXDSR2.Bits.DB0 +#define CAN4TXDSR2_DB1 _CAN4TXDSR2.Bits.DB1 +#define CAN4TXDSR2_DB2 _CAN4TXDSR2.Bits.DB2 +#define CAN4TXDSR2_DB3 _CAN4TXDSR2.Bits.DB3 +#define CAN4TXDSR2_DB4 _CAN4TXDSR2.Bits.DB4 +#define CAN4TXDSR2_DB5 _CAN4TXDSR2.Bits.DB5 +#define CAN4TXDSR2_DB6 _CAN4TXDSR2.Bits.DB6 +#define CAN4TXDSR2_DB7 _CAN4TXDSR2.Bits.DB7 +#define CAN4TXDSR2_DB _CAN4TXDSR2.MergedBits.grpDB + + +/*** CAN4TXDSR3 - MSCAN4 Transmit Data Segment Register 3; 0x000002B7 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN4TXDSR3STR; +extern volatile CAN4TXDSR3STR _CAN4TXDSR3 @(REG_BASE + 0x000002B7); +#define CAN4TXDSR3 _CAN4TXDSR3.Byte +#define CAN4TXDSR3_DB0 _CAN4TXDSR3.Bits.DB0 +#define CAN4TXDSR3_DB1 _CAN4TXDSR3.Bits.DB1 +#define CAN4TXDSR3_DB2 _CAN4TXDSR3.Bits.DB2 +#define CAN4TXDSR3_DB3 _CAN4TXDSR3.Bits.DB3 +#define CAN4TXDSR3_DB4 _CAN4TXDSR3.Bits.DB4 +#define CAN4TXDSR3_DB5 _CAN4TXDSR3.Bits.DB5 +#define CAN4TXDSR3_DB6 _CAN4TXDSR3.Bits.DB6 +#define CAN4TXDSR3_DB7 _CAN4TXDSR3.Bits.DB7 +#define CAN4TXDSR3_DB _CAN4TXDSR3.MergedBits.grpDB + + +/*** CAN4TXDSR4 - MSCAN4 Transmit Data Segment Register 4; 0x000002B8 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN4TXDSR4STR; +extern volatile CAN4TXDSR4STR _CAN4TXDSR4 @(REG_BASE + 0x000002B8); +#define CAN4TXDSR4 _CAN4TXDSR4.Byte +#define CAN4TXDSR4_DB0 _CAN4TXDSR4.Bits.DB0 +#define CAN4TXDSR4_DB1 _CAN4TXDSR4.Bits.DB1 +#define CAN4TXDSR4_DB2 _CAN4TXDSR4.Bits.DB2 +#define CAN4TXDSR4_DB3 _CAN4TXDSR4.Bits.DB3 +#define CAN4TXDSR4_DB4 _CAN4TXDSR4.Bits.DB4 +#define CAN4TXDSR4_DB5 _CAN4TXDSR4.Bits.DB5 +#define CAN4TXDSR4_DB6 _CAN4TXDSR4.Bits.DB6 +#define CAN4TXDSR4_DB7 _CAN4TXDSR4.Bits.DB7 +#define CAN4TXDSR4_DB _CAN4TXDSR4.MergedBits.grpDB + + +/*** CAN4TXDSR5 - MSCAN4 Transmit Data Segment Register 5; 0x000002B9 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN4TXDSR5STR; +extern volatile CAN4TXDSR5STR _CAN4TXDSR5 @(REG_BASE + 0x000002B9); +#define CAN4TXDSR5 _CAN4TXDSR5.Byte +#define CAN4TXDSR5_DB0 _CAN4TXDSR5.Bits.DB0 +#define CAN4TXDSR5_DB1 _CAN4TXDSR5.Bits.DB1 +#define CAN4TXDSR5_DB2 _CAN4TXDSR5.Bits.DB2 +#define CAN4TXDSR5_DB3 _CAN4TXDSR5.Bits.DB3 +#define CAN4TXDSR5_DB4 _CAN4TXDSR5.Bits.DB4 +#define CAN4TXDSR5_DB5 _CAN4TXDSR5.Bits.DB5 +#define CAN4TXDSR5_DB6 _CAN4TXDSR5.Bits.DB6 +#define CAN4TXDSR5_DB7 _CAN4TXDSR5.Bits.DB7 +#define CAN4TXDSR5_DB _CAN4TXDSR5.MergedBits.grpDB + + +/*** CAN4TXDSR6 - MSCAN4 Transmit Data Segment Register 6; 0x000002BA ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN4TXDSR6STR; +extern volatile CAN4TXDSR6STR _CAN4TXDSR6 @(REG_BASE + 0x000002BA); +#define CAN4TXDSR6 _CAN4TXDSR6.Byte +#define CAN4TXDSR6_DB0 _CAN4TXDSR6.Bits.DB0 +#define CAN4TXDSR6_DB1 _CAN4TXDSR6.Bits.DB1 +#define CAN4TXDSR6_DB2 _CAN4TXDSR6.Bits.DB2 +#define CAN4TXDSR6_DB3 _CAN4TXDSR6.Bits.DB3 +#define CAN4TXDSR6_DB4 _CAN4TXDSR6.Bits.DB4 +#define CAN4TXDSR6_DB5 _CAN4TXDSR6.Bits.DB5 +#define CAN4TXDSR6_DB6 _CAN4TXDSR6.Bits.DB6 +#define CAN4TXDSR6_DB7 _CAN4TXDSR6.Bits.DB7 +#define CAN4TXDSR6_DB _CAN4TXDSR6.MergedBits.grpDB + + +/*** CAN4TXDSR7 - MSCAN4 Transmit Data Segment Register 7; 0x000002BB ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CAN4TXDSR7STR; +extern volatile CAN4TXDSR7STR _CAN4TXDSR7 @(REG_BASE + 0x000002BB); +#define CAN4TXDSR7 _CAN4TXDSR7.Byte +#define CAN4TXDSR7_DB0 _CAN4TXDSR7.Bits.DB0 +#define CAN4TXDSR7_DB1 _CAN4TXDSR7.Bits.DB1 +#define CAN4TXDSR7_DB2 _CAN4TXDSR7.Bits.DB2 +#define CAN4TXDSR7_DB3 _CAN4TXDSR7.Bits.DB3 +#define CAN4TXDSR7_DB4 _CAN4TXDSR7.Bits.DB4 +#define CAN4TXDSR7_DB5 _CAN4TXDSR7.Bits.DB5 +#define CAN4TXDSR7_DB6 _CAN4TXDSR7.Bits.DB6 +#define CAN4TXDSR7_DB7 _CAN4TXDSR7.Bits.DB7 +#define CAN4TXDSR7_DB _CAN4TXDSR7.MergedBits.grpDB + + +/*** CAN4TXDLR - MSCAN4 Transmit Data Length Register; 0x000002BC ***/ +typedef union { + byte Byte; + struct { + byte DLC0 :1; /* Data Length Code Bit 0 */ + byte DLC1 :1; /* Data Length Code Bit 1 */ + byte DLC2 :1; /* Data Length Code Bit 2 */ + byte DLC3 :1; /* Data Length Code Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpDLC :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN4TXDLRSTR; +extern volatile CAN4TXDLRSTR _CAN4TXDLR @(REG_BASE + 0x000002BC); +#define CAN4TXDLR _CAN4TXDLR.Byte +#define CAN4TXDLR_DLC0 _CAN4TXDLR.Bits.DLC0 +#define CAN4TXDLR_DLC1 _CAN4TXDLR.Bits.DLC1 +#define CAN4TXDLR_DLC2 _CAN4TXDLR.Bits.DLC2 +#define CAN4TXDLR_DLC3 _CAN4TXDLR.Bits.DLC3 +#define CAN4TXDLR_DLC _CAN4TXDLR.MergedBits.grpDLC + + +/*** CAN4TXTBPR - MSCAN4 Transmit Transmit Buffer Priority; 0x000002BF ***/ +typedef union { + byte Byte; + struct { + byte PRIO0 :1; /* Transmit Buffer Priority Bit 0 */ + byte PRIO1 :1; /* Transmit Buffer Priority Bit 1 */ + byte PRIO2 :1; /* Transmit Buffer Priority Bit 2 */ + byte PRIO3 :1; /* Transmit Buffer Priority Bit 3 */ + byte PRIO4 :1; /* Transmit Buffer Priority Bit 4 */ + byte PRIO5 :1; /* Transmit Buffer Priority Bit 5 */ + byte PRIO6 :1; /* Transmit Buffer Priority Bit 6 */ + byte PRIO7 :1; /* Transmit Buffer Priority Bit 7 */ + } Bits; + struct { + byte grpPRIO :8; + } MergedBits; +} CAN4TXTBPRSTR; +extern volatile CAN4TXTBPRSTR _CAN4TXTBPR @(REG_BASE + 0x000002BF); +#define CAN4TXTBPR _CAN4TXTBPR.Byte +#define CAN4TXTBPR_PRIO0 _CAN4TXTBPR.Bits.PRIO0 +#define CAN4TXTBPR_PRIO1 _CAN4TXTBPR.Bits.PRIO1 +#define CAN4TXTBPR_PRIO2 _CAN4TXTBPR.Bits.PRIO2 +#define CAN4TXTBPR_PRIO3 _CAN4TXTBPR.Bits.PRIO3 +#define CAN4TXTBPR_PRIO4 _CAN4TXTBPR.Bits.PRIO4 +#define CAN4TXTBPR_PRIO5 _CAN4TXTBPR.Bits.PRIO5 +#define CAN4TXTBPR_PRIO6 _CAN4TXTBPR.Bits.PRIO6 +#define CAN4TXTBPR_PRIO7 _CAN4TXTBPR.Bits.PRIO7 +#define CAN4TXTBPR_PRIO _CAN4TXTBPR.MergedBits.grpPRIO + + +/*** BDMSTS - BDM Status Register; 0x0000FF01 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte UNSEC :1; /* Unsecure */ + byte CLKSW :1; /* Clock switch */ + byte TRACE :1; /* TRACE1 BDM firmware command is being executed */ + byte SDV :1; /* Shift data valid */ + byte ENTAG :1; /* Tagging enable */ + byte BDMACT :1; /* BDM active status */ + byte ENBDM :1; /* Enable BDM */ + } Bits; +} BDMSTSSTR; +extern volatile BDMSTSSTR _BDMSTS @(0x0000FF01); +#define BDMSTS _BDMSTS.Byte +#define BDMSTS_UNSEC _BDMSTS.Bits.UNSEC +#define BDMSTS_CLKSW _BDMSTS.Bits.CLKSW +#define BDMSTS_TRACE _BDMSTS.Bits.TRACE +#define BDMSTS_SDV _BDMSTS.Bits.SDV +#define BDMSTS_ENTAG _BDMSTS.Bits.ENTAG +#define BDMSTS_BDMACT _BDMSTS.Bits.BDMACT +#define BDMSTS_ENBDM _BDMSTS.Bits.ENBDM + + +/*** BDMCCR - BDM CCR Holding Register; 0x0000FF06 ***/ +typedef union { + byte Byte; + struct { + byte CCR0 :1; /* BDM CCR Holding Bit 0 */ + byte CCR1 :1; /* BDM CCR Holding Bit 1 */ + byte CCR2 :1; /* BDM CCR Holding Bit 2 */ + byte CCR3 :1; /* BDM CCR Holding Bit 3 */ + byte CCR4 :1; /* BDM CCR Holding Bit 4 */ + byte CCR5 :1; /* BDM CCR Holding Bit 5 */ + byte CCR6 :1; /* BDM CCR Holding Bit 6 */ + byte CCR7 :1; /* BDM CCR Holding Bit 7 */ + } Bits; + struct { + byte grpCCR :8; + } MergedBits; +} BDMCCRSTR; +extern volatile BDMCCRSTR _BDMCCR @(0x0000FF06); +#define BDMCCR _BDMCCR.Byte +#define BDMCCR_CCR0 _BDMCCR.Bits.CCR0 +#define BDMCCR_CCR1 _BDMCCR.Bits.CCR1 +#define BDMCCR_CCR2 _BDMCCR.Bits.CCR2 +#define BDMCCR_CCR3 _BDMCCR.Bits.CCR3 +#define BDMCCR_CCR4 _BDMCCR.Bits.CCR4 +#define BDMCCR_CCR5 _BDMCCR.Bits.CCR5 +#define BDMCCR_CCR6 _BDMCCR.Bits.CCR6 +#define BDMCCR_CCR7 _BDMCCR.Bits.CCR7 +#define BDMCCR_CCR _BDMCCR.MergedBits.grpCCR + + +/*** BDMINR - BDM Internal Register Position Register; 0x0000FF07 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte REG11 :1; /* Internal register map position */ + byte REG12 :1; /* Internal register map position */ + byte REG13 :1; /* Internal register map position */ + byte REG14 :1; /* Internal register map position */ + byte REG15 :1; /* Internal register map position */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte grpREG_11 :5; + } MergedBits; +} BDMINRSTR; +extern volatile BDMINRSTR _BDMINR @(0x0000FF07); +#define BDMINR _BDMINR.Byte +#define BDMINR_REG11 _BDMINR.Bits.REG11 +#define BDMINR_REG12 _BDMINR.Bits.REG12 +#define BDMINR_REG13 _BDMINR.Bits.REG13 +#define BDMINR_REG14 _BDMINR.Bits.REG14 +#define BDMINR_REG15 _BDMINR.Bits.REG15 +#define BDMINR_REG_11 _BDMINR.MergedBits.grpREG_11 +#define BDMINR_REG BDMINR_REG_11 + + + /* Watchdog reset macro */ +#ifdef _lint + #define __RESET_WATCHDOG() /* empty */ +#else + #define __RESET_WATCHDOG() {asm sta COPCTL;} /* Just write a byte to feed the dog */ +#endif + +#endif + +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ + diff --git a/20080212/Demo/HCS12_CodeWarrior_banked/CODE/PESL.h b/20080212/Demo/HCS12_CodeWarrior_banked/CODE/PESL.h new file mode 100644 index 000000000..a01bb9a21 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_banked/CODE/PESL.h @@ -0,0 +1,52 @@ +/* ================================================================================================================================= ** +** ================================================================================================================================= ** +** CONFIGURATION FILE FOR PESL LIBRARY ** +** ================================================================================================================================= ** +** ================================================================================================================================= */ + +#define _MC9S12A128_112 1 +#define _MC9S12A128_80 2 +#define _MC9S12A256_112 3 +#define _MC9S12A256_80 4 +#define _MC9S12A64_112 5 +#define _MC9S12A64_80 6 +#define _MC9S12C32_48 7 +#define _MC9S12C32_52 8 +#define _MC9S12C32_80 9 +#define _MC9S12D64_112 10 +#define _MC9S12D64_80 11 +#define _MC9S12DB128_112 12 +#define _MC9S12DG128_112 13 +#define _MC9S12DG128_80 14 +#define _MC9S12DG256_112 15 +#define _MC9S12DJ128_112 16 +#define _MC9S12DJ128_80 17 +#define _MC9S12DJ256_112 18 +#define _MC9S12DJ256_80 19 +#define _MC9S12DJ64_112 20 +#define _MC9S12DJ64_80 21 +#define _MC9S12DP256_112 22 +#define _MC9S12DT128_112 23 +#define _MC9S12DT256_112 24 +#define _MC9S12A32_80 25 +#define _MC9S12D32_80 26 +#define _MC9S12DP512_112 27 +#define _MC9S12A512_112 28 +#define _MC9S12E128_112 29 +#define _MC9S12E128_80 30 +#define _MC9S12E64_112 31 + + +/* Selected target MCU */ + +#define CPUtype _MC9S12DP256_112 + + +/* PESL library */ + +#pragma MESSAGE DISABLE C4000 /* WARNING C4000: Condition is always TRUE */ +#pragma MESSAGE DISABLE C4001 /* WARNING C4001: Condition is always FALSE */ + +#include "PESLlib.h" + + diff --git a/20080212/Demo/HCS12_CodeWarrior_banked/CODE/PE_Const.H b/20080212/Demo/HCS12_CodeWarrior_banked/CODE/PE_Const.H new file mode 100644 index 000000000..c278f4a88 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_banked/CODE/PE_Const.H @@ -0,0 +1,50 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : PE_Const.H +** Project : RTOSDemo +** Processor : MC9S12DP256BCPV +** Beantype : PE_Const +** Version : Driver 01.00 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 13/06/2005, 20:14 +** Abstract : +** This bean "PE_Const" contains internal definitions +** of the constants. +** Settings : +** Contents : +** No public methods +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + +#ifndef __PE_Const_H +#define __PE_Const_H + +/* Constants for detecting running mode */ +#define HIGH_SPEED 0 /* High speed */ +#define LOW_SPEED 1 /* Low speed */ +#define SLOW_SPEED 2 /* Slow speed */ + +/* Reset cause constants */ +#define RSTSRC_POR 1 /* Power-on reset */ +#define RSTSRC_PIN 8 /* External reset bit */ +#define RSTSRC_COP 4 /* COP reset */ +#define RSTSRC_ILOP 2 /* Illegal opcode reset */ +#define RSTSRC_ILAD 16 /* Illegal address reset */ +#define RSTSRC_LVI 32 /* Low voltage inhibit reset */ + +#endif /* _PE_Const_H */ +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/20080212/Demo/HCS12_CodeWarrior_banked/CODE/PE_Error.H b/20080212/Demo/HCS12_CodeWarrior_banked/CODE/PE_Error.H new file mode 100644 index 000000000..813974ecc --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_banked/CODE/PE_Error.H @@ -0,0 +1,53 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : PE_Error.H +** Project : RTOSDemo +** Processor : MC9S12DP256BCPV +** Beantype : PE_Error +** Version : Driver 01.00 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 13/06/2005, 20:14 +** Abstract : +** This bean "PE_Error" contains internal definitions +** of the error constants. +** Settings : +** Contents : +** No public methods +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + +#ifndef __PE_Error_H +#define __PE_Error_H + +#define ERR_OK 0 /* OK */ +#define ERR_SPEED 1 /* This device does not work in the active speed mode. */ +#define ERR_RANGE 2 /* Parameter out of range. */ +#define ERR_VALUE 3 /* Parameter of incorrect value. */ +#define ERR_OVERFLOW 4 /* Timer overflow. */ +#define ERR_MATH 5 /* Overflow during evaluation. */ +#define ERR_ENABLED 6 /* Device is enabled. */ +#define ERR_DISABLED 7 /* Device is disabled. */ +#define ERR_BUSY 8 /* Device is busy. */ +#define ERR_NOTAVAIL 9 /* Requested value or method not available. */ +#define ERR_RXEMPTY 10 /* No data in receiver. */ +#define ERR_TXFULL 11 /* Transmitter is full. */ +#define ERR_BUSOFF 12 /* Bus not available. */ +#define ERR_OVERRUN 13 /* Overrun error is detected. */ +#define ERR_FRAMING 14 /* Framing error is detected. */ +#define ERR_PARITY 15 /* Parity error is detected. */ +#define ERR_NOISE 16 /* Noise error is detected. */ +#define ERR_IDLE 17 /* Idle error is detectes. */ +#define ERR_FAULT 18 /* Fault error is detected. */ +#define ERR_BREAK 19 /* Break char is received during communication. */ +#define ERR_CRC 20 /* CRC error is detected. */ +#define ERR_ARBITR 21 /* A node losts arbitration. This error occurs if two nodes start transmission at the same time. */ +#define ERR_PROTECT 22 /* Protection error is detected. */ + +#endif __PE_Error_H diff --git a/20080212/Demo/HCS12_CodeWarrior_banked/CODE/PE_Timer.C b/20080212/Demo/HCS12_CodeWarrior_banked/CODE/PE_Timer.C new file mode 100644 index 000000000..c94f087a6 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_banked/CODE/PE_Timer.C @@ -0,0 +1,205 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : PE_Timer.C +** Project : RTOSDemo +** Processor : MC9S12DP256BCPV +** Beantype : PE_Timer +** Version : Driver 01.00 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 14/06/2005, 16:34 +** Abstract : +** This bean "PE_Timer" implements internal methods and definitions +** used by beans working with timers. +** Settings : +** Contents : +** No public methods +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + + +/* MODULE PE_Timer. */ + +#include "PE_Timer.h" + + + +typedef unsigned long UINT32; + +typedef union { + UINT32 val; + struct { + unsigned short hi16,lo16; + } s; +} OP_UINT32; + +typedef struct { + unsigned short dummy; + UINT32 mid; +} M_UINT32; + +typedef struct { + UINT32 hi32, lo32; +} UINT64; + +typedef union { + UINT64 val; + M_UINT32 m; +} OP_UINT64; + +/* +** =================================================================== +** Method : PE_Timer_LngMul (bean PE_Timer) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +void PE_Timer_LngMul(dword va1, dword va2, dlong *var) +{ + OP_UINT32 *va = (OP_UINT32*)&va1; + OP_UINT32 *vb = (OP_UINT32*)&va2; + OP_UINT64 *vr = (OP_UINT64*)var; + + vr->val.hi32 = 0UL; + vr->val.lo32 = ((UINT32)va->s.lo16)*((UINT32)vb->s.lo16); + { + OP_UINT32 tmp; + + tmp.val = ((UINT32)va->s.lo16)*((UINT32)vb->s.hi16); + vr->m.mid += (UINT32)tmp.s.lo16; + vr->val.hi32 += (UINT32)tmp.s.hi16; + } + { + OP_UINT32 tmp; + + tmp.val = ((UINT32)va->s.hi16)*((UINT32)vb->s.lo16); + vr->m.mid += (UINT32)tmp.s.lo16; + vr->val.hi32 += (UINT32)tmp.s.hi16; + } + vr->val.hi32 += ((UINT32)va->s.hi16)*((UINT32)vb->s.hi16); +} + +/* +** =================================================================== +** Method : PE_Timer_LngHi1 (bean PE_Timer) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +bool PE_Timer_LngHi1(dword High, dword Low, word *Out) +{ + if ((High == 0) && ((Low >> 24) == 0)) + if ((Low & 0x80) != 0) { + if ((Low >> 8) < 0xFFFF) { + *Out = ((unsigned int)(Low >> 8))+1; + return FALSE; + } + } + else { + *Out = (unsigned int)(Low >> 8); + return FALSE; + } + *Out = (unsigned int)(Low >> 8); + return TRUE; +} + +/* +** =================================================================== +** Method : PE_Timer_LngHi2 (bean PE_Timer) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +bool PE_Timer_LngHi2(dword High, dword Low, word *Out) +{ + if (High == 0) + if ((Low & 0x8000) != 0) { + if ((Low >> 16) < 0xFFFF) { + *Out = ((unsigned int)(Low >> 16))+1; + return FALSE; + } + } + else { + *Out = (unsigned int)(Low >> 16); + return FALSE; + } + *Out = (unsigned int)(Low >> 16); + return TRUE; +} + +/* +** =================================================================== +** Method : PE_Timer_LngHi3 (bean PE_Timer) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +bool PE_Timer_LngHi3(dword High, dword Low, word *Out) +{ + if ((High >> 8) == 0) + if ((Low & 0x800000) != 0) { + if (((Low >> 24) | (High << 8)) < 0xFFFF) { + *Out = ((unsigned int)((Low >> 24) | (High << 8)))+1; + return FALSE; + } + } + else { + *Out = (unsigned int)((Low >> 24) | (High << 8)); + return FALSE; + } + *Out = (unsigned int)((Low >> 24) | (High << 8)); + return TRUE; +} + +/* +** =================================================================== +** Method : PE_Timer_LngHi4 (bean PE_Timer) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +bool PE_Timer_LngHi4(dword High, dword Low, word *Out) +{ + if ((High >> 16) == 0) + if ((Low & 0x80000000) != 0) { + if (High < 0xFFFF) { + *Out = ((unsigned int)High)+1; + return FALSE; + } + } + else { + *Out = (unsigned int)High; + return FALSE; + } + *Out = (unsigned int)High; + return TRUE; +} + + + +/* END PE_Timer. */ + +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/20080212/Demo/HCS12_CodeWarrior_banked/CODE/PE_Timer.H b/20080212/Demo/HCS12_CodeWarrior_banked/CODE/PE_Timer.H new file mode 100644 index 000000000..6ba554b94 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_banked/CODE/PE_Timer.H @@ -0,0 +1,97 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : PE_Timer.H +** Project : RTOSDemo +** Processor : MC9S12DP256BCPV +** Beantype : PE_Timer +** Version : Driver 01.00 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 14/06/2005, 16:34 +** Abstract : +** This bean "PE_Timer" implements internal methods and definitions +** used by beans working with timers. +** Settings : +** Contents : +** No public methods +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ +#ifndef __PE_Timer +#define __PE_Timer +/*Include shared modules, which are used for whole project*/ +#include "PE_types.h" +#include "PE_const.h" + +/* MODULE PE_Timer. */ + +void PE_Timer_LngMul(dword va1, dword va2, dlong *var); +/* +** =================================================================== +** Method : PE_Timer_LngMul (bean PE_Timer) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ + +bool PE_Timer_LngHi1(dword Low, dword High, word *Out); +/* +** =================================================================== +** Method : PE_Timer_LngHi1 (bean PE_Timer) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ + +bool PE_Timer_LngHi2(dword Low, dword High, word *Out); +/* +** =================================================================== +** Method : PE_Timer_LngHi2 (bean PE_Timer) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ + +bool PE_Timer_LngHi3(dword Low, dword High, word *Out); +/* +** =================================================================== +** Method : PE_Timer_LngHi3 (bean PE_Timer) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ + +bool PE_Timer_LngHi4(dword Low, dword High, word *Out); +/* +** =================================================================== +** Method : PE_Timer_LngHi4 (bean PE_Timer) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ + + +#endif /* END PE_Timer. */ +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/20080212/Demo/HCS12_CodeWarrior_banked/CODE/PE_Types.H b/20080212/Demo/HCS12_CodeWarrior_banked/CODE/PE_Types.H new file mode 100644 index 000000000..196279ded --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_banked/CODE/PE_Types.H @@ -0,0 +1,87 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : PE_Types.H +** Project : RTOSDemo +** Processor : MC9S12DP256BCPV +** Beantype : PE_Types +** Version : Driver 01.04 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 13/06/2005, 20:14 +** Abstract : +** This bean "PE_Types" contains internal definitions +** of the types. +** Settings : +** Contents : +** No public methods +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + +#ifndef __PE_Types_H +#define __PE_Types_H + +#define FALSE 0 +#define TRUE 1 + +/*Types definition*/ +typedef unsigned char bool; +typedef unsigned char byte; +typedef unsigned int word; +typedef unsigned long dword; +typedef unsigned long dlong[2]; +typedef void (*tIntFunc)(void); + +/* Motorola types */ +typedef unsigned char VUINT8; +typedef signed char VINT8; +typedef unsigned short int VUINT16; +typedef signed short int VINT16; +typedef unsigned long int VUINT32; + +#define in16(var,l,h) var = ((word)(l)) | (((word)(h)) << 8) +#define out16(l,h,val) { l = (byte)val; h = (byte)(val >> 8); } + +#define output(P, V) P = (V) +#define input(P) (P) + +#define __DI() { asm sei; } /* Disable global interrupts */ +#define __EI() { asm cli; } /* Enable global interrupts */ +#define EnterCritical() { __asm pshc; __asm sei; __asm movb 1,SP+,CCR_reg; } /* This macro is used by Processor Expert. It saves CCR register and disable global interrupts. */ +#define ExitCritical() { __asm movb CCR_reg, 1,-SP; __asm pulc; } /* This macro is used by Processor Expert. It restores CCR register saved in SaveStatusReg(). */ +/* obsolete definition for backward compatibility */ +#define SaveStatusReg() EnterCritical() +#define RestoreStatusReg() ExitCritical() + + +typedef struct { /* Black&White Image */ + word width; /* Image width */ + word height; /* Image height */ + byte *pixmap; /* Image pixel bitmap */ + word size; /* Image size */ + char *name; /* Image name */ +} TIMAGE; +typedef TIMAGE* PIMAGE ; /* Pointer to image */ + +/* 16-bit register (Motorola format - big endian) */ +typedef union { + word w; + struct { + byte high,low; + } b; +} TWREG; + +#endif /* __PE_Types_H */ +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/20080212/Demo/HCS12_CodeWarrior_banked/CODE/RTOSDemo.C b/20080212/Demo/HCS12_CodeWarrior_banked/CODE/RTOSDemo.C new file mode 100644 index 000000000..9466aabd3 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_banked/CODE/RTOSDemo.C @@ -0,0 +1,67 @@ +/** ################################################################### +** Filename : RTOSDemo.C +** Project : RTOSDemo +** Processor : MC9S12DP256BCPV +** Version : Driver 01.05 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 13/06/2005, 20:14 +** Abstract : +** Main module. +** Here is to be placed user's code. +** Settings : +** Contents : +** No public methods +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ +/* MODULE RTOSDemo */ + +/* Including used modules for compilling procedure */ +#include "Cpu.h" +#include "Events.h" +#include "TickTimer.h" +#include "Byte1.h" +#include "COM0.h" +/* Include shared modules, which are used for whole project */ +#include "PE_Types.h" +#include "PE_Error.h" +#include "PE_Const.h" +#include "IO_Map.h" + +extern void vMain( void ); + +void main(void) +{ + /*** Processor Expert internal initialization. DON'T REMOVE THIS CODE!!! ***/ + PE_low_level_init(); + /*** End of Processor Expert internal initialization. ***/ + + /*Write your code here*/ + + /* Just jump to the real main(). */ + __asm + { + jmp vMain + } + + + /*** Processor Expert end of main routine. DON'T MODIFY THIS CODE!!! ***/ + for(;;); + /*** Processor Expert end of main routine. DON'T WRITE CODE BELOW!!! ***/ +} /*** End of main routine. DO NOT MODIFY THIS TEXT!!! ***/ + +/* END RTOSDemo */ +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/20080212/Demo/HCS12_CodeWarrior_banked/CODE/RTOSDemo.PRM b/20080212/Demo/HCS12_CodeWarrior_banked/CODE/RTOSDemo.PRM new file mode 100644 index 000000000..3cc861ac5 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_banked/CODE/RTOSDemo.PRM @@ -0,0 +1,64 @@ +/* +** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : RTOSDemo.PRM +** Project : RTOSDemo +** Processor : MC9S12DP256BCPV +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 19/06/2005, 15:54 +** Abstract : +** This file is used by the linker. It describes files to be linked, +** memory ranges, stack size, etc. For detailed description of the PRM file +** see CodeWarrior documentation. This file is generated by default. +** You can switch off generation by setting the property +** "Generate PRM file = no" on the "Build options" tab in CPU bean and then modify +** this file if needed. +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ################################################################### +*/ + +NAMES + +END + +SECTIONS + /* List of all sections specified on the "Build options" tab */ + RAM = READ_WRITE 0x00001000 TO 0x00003FFF; + ROM_C000 = READ_ONLY 0x0000C000 TO 0x0000C511; + ROM_4000 = READ_ONLY 0x00004000 TO 0x00004255; + ROM_PAGE30 = READ_ONLY 0x00308000 TO 0x00308255; + ROM_PAGE31 = READ_ONLY 0x00318000 TO 0x00318255; + ROM_PAGE32 = READ_ONLY 0x00328000 TO 0x00328255; + ROM_PAGE33 = READ_ONLY 0x00338000 TO 0x00338255; + ROM_PAGE34 = READ_ONLY 0x00348000 TO 0x00348255; + ROM_PAGE35 = READ_ONLY 0x00358000 TO 0x00358255; + ROM_PAGE36 = READ_ONLY 0x00368000 TO 0x00368255; + ROM_PAGE37 = READ_ONLY 0x00378000 TO 0x00378255; + ROM_PAGE38 = READ_ONLY 0x00388000 TO 0x00388255; + ROM_PAGE39 = READ_ONLY 0x00398000 TO 0x00398255; + ROM_PAGE3A = READ_ONLY 0x003A8000 TO 0x003A8255; + ROM_PAGE3B = READ_ONLY 0x003B8000 TO 0x003B8255; + ROM_PAGE3C = READ_ONLY 0x003C8000 TO 0x003C8255; + ROM_PAGE3D = READ_ONLY 0x003D8000 TO 0x003D8255; +END + +PLACEMENT + DEFAULT_RAM INTO RAM; + DEFAULT_ROM INTO ROM_PAGE30, ROM_PAGE31, ROM_PAGE32, ROM_PAGE33, ROM_PAGE34, ROM_PAGE35, ROM_PAGE36, +ROM_PAGE37, ROM_PAGE38, ROM_PAGE39, ROM_PAGE3A, ROM_PAGE3B, ROM_PAGE3C, ROM_PAGE3D; + _PRESTART, STARTUP, + ROM_VAR, STRINGS, + NON_BANKED, COPY INTO ROM_C000, ROM_4000; +END + +INIT _EntryPoint /* The entry point of the application. This function is generated into the CPU module. */ + +STACKSIZE 0x0080 /* Size of the system stack. Value can be changed on the "Build options" tab */ + diff --git a/20080212/Demo/HCS12_CodeWarrior_banked/CODE/TickTimer.C b/20080212/Demo/HCS12_CodeWarrior_banked/CODE/TickTimer.C new file mode 100644 index 000000000..5e735073e --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_banked/CODE/TickTimer.C @@ -0,0 +1,393 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : TickTimer.C +** Project : RTOSDemo +** Processor : MC9S12DP256BCPV +** Beantype : TimerInt +** Version : Bean 02.063, Driver 01.05, CPU db: 2.87.283 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 18/06/2005, 16:21 +** Abstract : +** This bean "TimerInt" implements a periodic interrupt. +** When the bean and its events are enabled, the "OnInterrupt" +** event is called periodically with the period that you specify. +** TimerInt supports also changing the period in runtime. +** The source of periodic interrupt can be timer compare or reload +** register or timer-overflow interrupt (of free running counter). +** Settings : +** Timer name : ECT (16-bit) +** Compare name : TC0 +** Counter shared : No +** +** High-speed CPU mode +** Prescaler : divide-by-8 +** Clock : 3124000 Hz +** Initial period/frequency +** Xtal ticks : 16000 +** microseconds : 1000 +** milliseconds : 1 +** seconds (real) : 0.0010000 +** Hz : 1000 +** kHz : 1 +** +** Runtime setting : period/frequency interval (continual setting) +** ticks : 16000 to 320000 ticks +** microseconds : 1000 to 20000 microseconds +** milliseconds : 1 to 20 milliseconds +** seconds (real) : 0.0010000 to 0.0200000 seconds +** Hz : 50 to 1000 Hz +** +** Initialization: +** Timer : Enabled +** Events : Enabled +** +** Timer registers +** Counter : TCNT [68] +** Mode : TIOS [64] +** Run : TSCR1 [70] +** Prescaler : TSCR2 [77] +** +** Compare registers +** Compare : TC0 [80] +** +** Flip-flop registers +** Mode : TCTL2 [73] +** Contents : +** Enable - byte TickTimer_Enable(void); +** SetPeriodTicks16 - byte TickTimer_SetPeriodTicks16(word Ticks); +** SetPeriodTicks32 - byte TickTimer_SetPeriodTicks32(dword Ticks); +** SetPeriodUS - byte TickTimer_SetPeriodUS(word Time); +** SetPeriodMS - byte TickTimer_SetPeriodMS(word Time); +** SetFreqHz - byte TickTimer_SetFreqHz(word Freq); +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + + +/* MODULE TickTimer. */ + +#include "Events.h" +#include "TickTimer.h" + +/* Definition of DATA and CODE segments for this bean. User can specify where + these segments will be located on "Build options" tab of the selected CPU bean. */ +#pragma DATA_SEG TickTimer_DATA /* Data section for this module. */ +#pragma CODE_SEG TickTimer_CODE /* Code section for this module. */ + +static word CmpHighVal; /* Compare register value for high speed CPU mode */ + + +/* +** =================================================================== +** Method : SetCV (bean TimerInt) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +static void SetCV(word Val) +{ + if (Val == 0) /* If the given value is zero */ + Val = 65535; /* then change it to the maximal one */ + TC0 = Val; /* Store given value to the compare register */ + TC7 = Val; /* Store given value to the modulo register */ +} + +/* +** =================================================================== +** Method : SetPV (bean TimerInt) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +static void SetPV(byte Val) +{ + TSCR2_PR = Val; /* Store given value to the prescaler */ +} + +/* +** =================================================================== +** Method : HWEnDi (bean TimerInt) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +static void HWEnDi(void) +{ + TFLG1 = 1; /* Reset interrupt request flag */ + TIE_C0I = 1; /* Enable interrupt */ +} + +/* +** =================================================================== +** Method : TickTimer_Enable (bean TimerInt) +** +** Description : +** Enable the bean - it starts the timer. Events may be +** generated ("DisableEvent"/"EnableEvent"). +** Parameters : None +** Returns : +** --- - Error code, possible codes: +** ERR_OK - OK +** ERR_SPEED - This device does not work in +** the active speed mode +** =================================================================== +*/ +byte TickTimer_Enable(void) +{ + HWEnDi(); /* Enable the device */ + return ERR_OK; /* OK */ +} + +/* +** =================================================================== +** Method : TickTimer_SetPeriodTicks16 (bean TimerInt) +** +** Description : +** This method sets the new period of the generated events. +** The period is expressed in Xtal ticks as a 16-bit unsigned +** integer number. +** This method is available only if runtime setting type +** 'from interval' is selected in the Timing dialog box in +** Runtime setting area. +** Parameters : +** NAME - DESCRIPTION +** Ticks - Period to set [in Xtal ticks] +** (16000 to 65535 ticks) +** Returns : +** --- - Error code, possible codes: +** ERR_OK - OK +** ERR_SPEED - This device does not work in +** the active speed mode +** ERR_MATH - Overflow during evaluation +** ERR_RANGE - Parameter out of range +** =================================================================== +*/ +byte TickTimer_SetPeriodTicks16(word Ticks) +{ + dlong rtval; /* Result of two 32-bit numbers multiplication */ + word rtword; /* Result of 64-bit number division */ + + if (Ticks < 16000) /* Is the given value out of range? */ + return ERR_RANGE; /* If yes then error */ + PE_Timer_LngMul((dword)Ticks,838592365,&rtval); /* Multiply given value and high speed CPU mode coefficient */ + if (PE_Timer_LngHi4(rtval[0],rtval[1],&rtword)) /* Is the result greater or equal than 65536 ? */ + rtword = 65535; /* If yes then use maximal possible value */ + CmpHighVal = rtword; /* Store result (compare register value for high speed CPU mode) to the variable CmpHighVal */ + SetCV(CmpHighVal); /* Store appropriate value to the compare register according to the selected high speed CPU mode */ + return ERR_OK; /* OK */ +} + +/* +** =================================================================== +** Method : TickTimer_SetPeriodTicks32 (bean TimerInt) +** +** Description : +** This method sets the new period of the generated events. +** The period is expressed in Xtal ticks as a 32-bit unsigned +** integer number. +** This method is available only if runtime setting type +** 'from interval' is selected in the Timing dialog box in +** Runtime setting area. +** Parameters : +** NAME - DESCRIPTION +** Ticks - Period to set [in Xtal ticks] +** (16000 to 320000 ticks) +** Returns : +** --- - Error code, possible codes: +** ERR_OK - OK +** ERR_SPEED - This device does not work in +** the active speed mode +** ERR_MATH - Overflow during evaluation +** ERR_RANGE - Parameter out of range +** =================================================================== +*/ +byte TickTimer_SetPeriodTicks32(dword Ticks) +{ + dlong rtval; /* Result of two 32-bit numbers multiplication */ + word rtword; /* Result of 64-bit number division */ + + if ((Ticks > 320000) || (Ticks < 16000)) /* Is the given value out of range? */ + return ERR_RANGE; /* Range error */ + PE_Timer_LngMul(Ticks,838592365,&rtval); /* Multiply given value and high speed CPU mode coefficient */ + if (PE_Timer_LngHi4(rtval[0],rtval[1],&rtword)) /* Is the result greater or equal than 65536 ? */ + rtword = 65535; /* If yes then use maximal possible value */ + CmpHighVal = rtword; /* Store result (compare register value for high speed CPU mode) to the variable CmpHighVal */ + SetCV(CmpHighVal); /* Store appropriate value to the compare register according to the selected high speed CPU mode */ + return ERR_OK; /* OK */ +} + +/* +** =================================================================== +** Method : TickTimer_SetPeriodUS (bean TimerInt) +** +** Description : +** This method sets the new period of the generated events. +** The period is expressed in microseconds as a 16-bit +** unsigned integer number. +** This method is available only if runtime setting type +** 'from interval' is selected in the Timing dialog box in +** Runtime setting area. +** Parameters : +** NAME - DESCRIPTION +** Time - Period to set [in microseconds] +** (1000 to 20000 microseconds) +** Returns : +** --- - Error code, possible codes: +** ERR_OK - OK +** ERR_SPEED - This device does not work in +** the active speed mode +** ERR_MATH - Overflow during evaluation +** ERR_RANGE - Parameter out of range +** =================================================================== +*/ +byte TickTimer_SetPeriodUS(word Time) +{ + dlong rtval; /* Result of two 32-bit numbers multiplication */ + word rtword; /* Result of 64-bit number division */ + + if ((Time > 20000) || (Time < 1000)) /* Is the given value out of range? */ + return ERR_RANGE; /* If yes then error */ + PE_Timer_LngMul((dword)Time,52412023,&rtval); /* Multiply given value and high speed CPU mode coefficient */ + if (PE_Timer_LngHi3(rtval[0],rtval[1],&rtword)) /* Is the result greater or equal than 65536 ? */ + rtword = 65535; /* If yes then use maximal possible value */ + CmpHighVal = rtword; /* Store result (compare register value for high speed CPU mode) to the variable CmpHighVal */ + SetCV(CmpHighVal); /* Store appropriate value to the compare register according to the selected high speed CPU mode */ + return ERR_OK; /* OK */ +} + +/* +** =================================================================== +** Method : TickTimer_SetPeriodMS (bean TimerInt) +** +** Description : +** This method sets the new period of the generated events. +** The period is expressed in miliseconds as a 16-bit +** unsigned integer number. +** This method is available only if runtime setting type +** 'from interval' is selected in the Timing dialog box in +** Runtime setting area. +** Parameters : +** NAME - DESCRIPTION +** Time - Period to set [in miliseconds] +** (1 to 20 milliseconds) +** Returns : +** --- - Error code, possible codes: +** ERR_OK - OK +** ERR_SPEED - This device does not work in +** the active speed mode +** ERR_MATH - Overflow during evaluation +** ERR_RANGE - Parameter out of range +** =================================================================== +*/ +byte TickTimer_SetPeriodMS(word Time) +{ + dlong rtval; /* Result of two 32-bit numbers multiplication */ + word rtword; /* Result of 64-bit number division */ + + if ((Time > 20) || (Time < 1)) /* Is the given value out of range? */ + return ERR_RANGE; /* If yes then error */ + PE_Timer_LngMul((dword)Time,204734464,&rtval); /* Multiply given value and high speed CPU mode coefficient */ + if (PE_Timer_LngHi2(rtval[0],rtval[1],&rtword)) /* Is the result greater or equal than 65536 ? */ + rtword = 65535; /* If yes then use maximal possible value */ + CmpHighVal = rtword; /* Store result (compare register value for high speed CPU mode) to the variable CmpHighVal */ + SetCV(CmpHighVal); /* Store appropriate value to the compare register according to the selected high speed CPU mode */ + return ERR_OK; /* OK */ +} + +/* +** =================================================================== +** Method : TickTimer_SetFreqHz (bean TimerInt) +** +** Description : +** This method sets the new frequency of the generated +** events. The frequency is expressed in Hz as a 16-bit +** unsigned integer number. +** This method is available only if runtime setting type +** 'from interval' is selected in the Timing dialog box in +** Runtime setting area. +** Parameters : +** NAME - DESCRIPTION +** Freq - Frequency to set [in Hz] +** (50 to 1000 Hz) +** Returns : +** --- - Error code, possible codes: +** ERR_OK - OK +** ERR_SPEED - This device does not work in +** the active speed mode +** ERR_MATH - Overflow during evaluation +** ERR_RANGE - Parameter out of range +** =================================================================== +*/ +byte TickTimer_SetFreqHz(word Freq) +{ + dlong rtval; /* Result of two 32-bit numbers division */ + word rtword; /* Result of 64-bit number division */ + + if ((Freq > 1000) || (Freq < 50)) /* Is the given value out of range? */ + return ERR_RANGE; /* If yes then error */ + rtval[1] = 799744000 / (dword)Freq; /* Divide high speed CPU mode coefficient by the given value */ + rtval[0] = 0; /* Convert result to the type dlong */ + if (PE_Timer_LngHi1(rtval[0],rtval[1],&rtword)) /* Is the result greater or equal than 65536 ? */ + rtword = 65535; /* If yes then use maximal possible value */ + CmpHighVal = rtword; /* Store result (compare register value for high speed CPU mode) to the variable CmpHighVal */ + SetCV(CmpHighVal); /* Store appropriate value to the compare register according to the selected high speed CPU mode */ + return ERR_OK; /* OK */ +} + +/* +** =================================================================== +** Method : TickTimer_Init (bean TimerInt) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +void TickTimer_Init(void) +{ + CmpHighVal = 3124; /* Compare register value for high speed CPU mode */ + SetCV(CmpHighVal); /* Store appropriate value to the compare register according to the selected high speed CPU mode */ + SetPV(3); /* Set prescaler register according to the selected high speed CPU mode */ + HWEnDi(); /* Enable/disable device according to status flags */ +} + +/* +** =================================================================== +** Method : TickTimer_Interrupt (bean TimerInt) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */ +__interrupt void TickTimer_Interrupt(void) +{ + TFLG1 = 1; /* Reset interrupt request flag */ + TickTimer_OnInterrupt(); /* Invoke user event */ +} + +#pragma CODE_SEG TickTimer_CODE /* Code section for this module. */ + +/* END TickTimer. */ + +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/20080212/Demo/HCS12_CodeWarrior_banked/CODE/TickTimer.H b/20080212/Demo/HCS12_CodeWarrior_banked/CODE/TickTimer.H new file mode 100644 index 000000000..8ddab4b3b --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_banked/CODE/TickTimer.H @@ -0,0 +1,276 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : TickTimer.H +** Project : RTOSDemo +** Processor : MC9S12DP256BCPV +** Beantype : TimerInt +** Version : Bean 02.063, Driver 01.05, CPU db: 2.87.283 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 18/06/2005, 16:21 +** Abstract : +** This bean "TimerInt" implements a periodic interrupt. +** When the bean and its events are enabled, the "OnInterrupt" +** event is called periodically with the period that you specify. +** TimerInt supports also changing the period in runtime. +** The source of periodic interrupt can be timer compare or reload +** register or timer-overflow interrupt (of free running counter). +** Settings : +** Timer name : ECT (16-bit) +** Compare name : TC0 +** Counter shared : No +** +** High-speed CPU mode +** Prescaler : divide-by-8 +** Clock : 3124000 Hz +** Initial period/frequency +** Xtal ticks : 16000 +** microseconds : 1000 +** milliseconds : 1 +** seconds (real) : 0.0010000 +** Hz : 1000 +** kHz : 1 +** +** Runtime setting : period/frequency interval (continual setting) +** ticks : 16000 to 320000 ticks +** microseconds : 1000 to 20000 microseconds +** milliseconds : 1 to 20 milliseconds +** seconds (real) : 0.0010000 to 0.0200000 seconds +** Hz : 50 to 1000 Hz +** +** Initialization: +** Timer : Enabled +** Events : Enabled +** +** Timer registers +** Counter : TCNT [68] +** Mode : TIOS [64] +** Run : TSCR1 [70] +** Prescaler : TSCR2 [77] +** +** Compare registers +** Compare : TC0 [80] +** +** Flip-flop registers +** Mode : TCTL2 [73] +** Contents : +** Enable - byte TickTimer_Enable(void); +** SetPeriodTicks16 - byte TickTimer_SetPeriodTicks16(word Ticks); +** SetPeriodTicks32 - byte TickTimer_SetPeriodTicks32(dword Ticks); +** SetPeriodUS - byte TickTimer_SetPeriodUS(word Time); +** SetPeriodMS - byte TickTimer_SetPeriodMS(word Time); +** SetFreqHz - byte TickTimer_SetFreqHz(word Freq); +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + +#ifndef __TickTimer +#define __TickTimer + +/* MODULE TickTimer. */ + +#include "Cpu.h" + +#pragma CODE_SEG TickTimer_CODE /* Code section for this module. */ + +#define TickTimer_SPT16Min 16000 /* Lower bound of interval for method SetPeriodTicks16 */ +#define TickTimer_SPT16Max 65535 /* Upper bound of interval for method SetPeriodTicks16 */ +#define TickTimer_SPT32Min 16000 /* Lower bound of interval for method SetPeriodTicks32 */ +#define TickTimer_SPT32Max 320000 /* Upper bound of interval for method SetPeriodTicks32 */ +#define TickTimer_SPUSMin 1000 /* Lower bound of interval for method SetPeriodUS */ +#define TickTimer_SPUSMax 20000 /* Upper bound of interval for method SetPeriodUS */ +#define TickTimer_SPMSMin 1 /* Lower bound of interval for method SetPeriodMS */ +#define TickTimer_SPMSMax 20 /* Upper bound of interval for method SetPeriodMS */ +#define TickTimer_SFHzMin 50 /* Lower bound of interval for method SetFreqHz */ +#define TickTimer_SFHzMax 1000 /* Upper bound of interval for method SetFreqHz */ + + +byte TickTimer_Enable(void); +/* +** =================================================================== +** Method : TickTimer_Enable (bean TimerInt) +** +** Description : +** Enable the bean - it starts the timer. Events may be +** generated ("DisableEvent"/"EnableEvent"). +** Parameters : None +** Returns : +** --- - Error code, possible codes: +** ERR_OK - OK +** ERR_SPEED - This device does not work in +** the active speed mode +** =================================================================== +*/ + +byte TickTimer_SetPeriodTicks16(word Ticks); +/* +** =================================================================== +** Method : TickTimer_SetPeriodTicks16 (bean TimerInt) +** +** Description : +** This method sets the new period of the generated events. +** The period is expressed in Xtal ticks as a 16-bit unsigned +** integer number. +** This method is available only if runtime setting type +** 'from interval' is selected in the Timing dialog box in +** Runtime setting area. +** Parameters : +** NAME - DESCRIPTION +** Ticks - Period to set [in Xtal ticks] +** (16000 to 65535 ticks) +** Returns : +** --- - Error code, possible codes: +** ERR_OK - OK +** ERR_SPEED - This device does not work in +** the active speed mode +** ERR_MATH - Overflow during evaluation +** ERR_RANGE - Parameter out of range +** =================================================================== +*/ + +byte TickTimer_SetPeriodTicks32(dword Ticks); +/* +** =================================================================== +** Method : TickTimer_SetPeriodTicks32 (bean TimerInt) +** +** Description : +** This method sets the new period of the generated events. +** The period is expressed in Xtal ticks as a 32-bit unsigned +** integer number. +** This method is available only if runtime setting type +** 'from interval' is selected in the Timing dialog box in +** Runtime setting area. +** Parameters : +** NAME - DESCRIPTION +** Ticks - Period to set [in Xtal ticks] +** (16000 to 320000 ticks) +** Returns : +** --- - Error code, possible codes: +** ERR_OK - OK +** ERR_SPEED - This device does not work in +** the active speed mode +** ERR_MATH - Overflow during evaluation +** ERR_RANGE - Parameter out of range +** =================================================================== +*/ + +byte TickTimer_SetPeriodUS(word Time); +/* +** =================================================================== +** Method : TickTimer_SetPeriodUS (bean TimerInt) +** +** Description : +** This method sets the new period of the generated events. +** The period is expressed in microseconds as a 16-bit +** unsigned integer number. +** This method is available only if runtime setting type +** 'from interval' is selected in the Timing dialog box in +** Runtime setting area. +** Parameters : +** NAME - DESCRIPTION +** Time - Period to set [in microseconds] +** (1000 to 20000 microseconds) +** Returns : +** --- - Error code, possible codes: +** ERR_OK - OK +** ERR_SPEED - This device does not work in +** the active speed mode +** ERR_MATH - Overflow during evaluation +** ERR_RANGE - Parameter out of range +** =================================================================== +*/ + +byte TickTimer_SetPeriodMS(word Time); +/* +** =================================================================== +** Method : TickTimer_SetPeriodMS (bean TimerInt) +** +** Description : +** This method sets the new period of the generated events. +** The period is expressed in miliseconds as a 16-bit +** unsigned integer number. +** This method is available only if runtime setting type +** 'from interval' is selected in the Timing dialog box in +** Runtime setting area. +** Parameters : +** NAME - DESCRIPTION +** Time - Period to set [in miliseconds] +** (1 to 20 milliseconds) +** Returns : +** --- - Error code, possible codes: +** ERR_OK - OK +** ERR_SPEED - This device does not work in +** the active speed mode +** ERR_MATH - Overflow during evaluation +** ERR_RANGE - Parameter out of range +** =================================================================== +*/ + +byte TickTimer_SetFreqHz(word Freq); +/* +** =================================================================== +** Method : TickTimer_SetFreqHz (bean TimerInt) +** +** Description : +** This method sets the new frequency of the generated +** events. The frequency is expressed in Hz as a 16-bit +** unsigned integer number. +** This method is available only if runtime setting type +** 'from interval' is selected in the Timing dialog box in +** Runtime setting area. +** Parameters : +** NAME - DESCRIPTION +** Freq - Frequency to set [in Hz] +** (50 to 1000 Hz) +** Returns : +** --- - Error code, possible codes: +** ERR_OK - OK +** ERR_SPEED - This device does not work in +** the active speed mode +** ERR_MATH - Overflow during evaluation +** ERR_RANGE - Parameter out of range +** =================================================================== +*/ + +#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */ +__interrupt void TickTimer_Interrupt(void); +#pragma CODE_SEG TickTimer_CODE /* Code section for this module. */ +/* +** =================================================================== +** Method : TickTimer_Interrupt (bean TimerInt) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ + +void TickTimer_Init(void); +/* +** =================================================================== +** Method : TickTimer_Init (bean TimerInt) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ + +#pragma CODE_SEG DEFAULT /* Change code section to DEFAULT. */ + +/* END TickTimer. */ + +#endif /* ifndef __TickTimer */ +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/20080212/Demo/HCS12_CodeWarrior_banked/CODE/Vectors.c b/20080212/Demo/HCS12_CodeWarrior_banked/CODE/Vectors.c new file mode 100644 index 000000000..633348f90 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_banked/CODE/Vectors.c @@ -0,0 +1,112 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : Cpu.C +** Project : RTOSDemo +** Processor : MC9S12DP256BCPV +** Beantype : MC9S12DP256_112 +** Version : Bean 01.148, Driver 01.09, CPU db: 2.87.283 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 16/06/2005, 19:18 +** Abstract : +** This bean "MC9S12DP256_112" implements properties, methods, +** and events of the CPU. +** Settings : +** +** Contents : +** EnableInt - void Cpu_EnableInt(void); +** DisableInt - void Cpu_DisableInt(void); +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + + +#include "Cpu.h" +#include "TickTimer.h" +#include "Byte1.h" + +extern void near _EntryPoint(void); /* Startup routine */ +extern void near vPortTickInterrupt( void ); +extern void near vPortYield( void ); +extern void near vCOM0_ISR( void ); + +typedef void (*near tIsrFunc)(void); +const tIsrFunc _vect[] @0xFF80 = { /* Interrupt table */ + Cpu_Interrupt, /* 0 Default (unused) interrupt */ + Cpu_Interrupt, /* 1 Default (unused) interrupt */ + Cpu_Interrupt, /* 2 Default (unused) interrupt */ + Cpu_Interrupt, /* 3 Default (unused) interrupt */ + Cpu_Interrupt, /* 4 Default (unused) interrupt */ + Cpu_Interrupt, /* 5 Default (unused) interrupt */ + Cpu_Interrupt, /* 6 Default (unused) interrupt */ + Cpu_Interrupt, /* 7 Default (unused) interrupt */ + Cpu_Interrupt, /* 8 Default (unused) interrupt */ + Cpu_Interrupt, /* 9 Default (unused) interrupt */ + Cpu_Interrupt, /* 10 Default (unused) interrupt */ + Cpu_Interrupt, /* 11 Default (unused) interrupt */ + Cpu_Interrupt, /* 12 Default (unused) interrupt */ + Cpu_Interrupt, /* 13 Default (unused) interrupt */ + Cpu_Interrupt, /* 14 Default (unused) interrupt */ + Cpu_Interrupt, /* 15 Default (unused) interrupt */ + Cpu_Interrupt, /* 16 Default (unused) interrupt */ + Cpu_Interrupt, /* 17 Default (unused) interrupt */ + Cpu_Interrupt, /* 18 Default (unused) interrupt */ + Cpu_Interrupt, /* 19 Default (unused) interrupt */ + Cpu_Interrupt, /* 20 Default (unused) interrupt */ + Cpu_Interrupt, /* 21 Default (unused) interrupt */ + Cpu_Interrupt, /* 22 Default (unused) interrupt */ + Cpu_Interrupt, /* 23 Default (unused) interrupt */ + Cpu_Interrupt, /* 24 Default (unused) interrupt */ + Cpu_Interrupt, /* 25 Default (unused) interrupt */ + Cpu_Interrupt, /* 26 Default (unused) interrupt */ + Cpu_Interrupt, /* 27 Default (unused) interrupt */ + Cpu_Interrupt, /* 28 Default (unused) interrupt */ + Cpu_Interrupt, /* 29 Default (unused) interrupt */ + Cpu_Interrupt, /* 30 Default (unused) interrupt */ + Cpu_Interrupt, /* 31 Default (unused) interrupt */ + Cpu_Interrupt, /* 32 Default (unused) interrupt */ + Cpu_Interrupt, /* 33 Default (unused) interrupt */ + Cpu_Interrupt, /* 34 Default (unused) interrupt */ + Cpu_Interrupt, /* 35 Default (unused) interrupt */ + Cpu_Interrupt, /* 36 Default (unused) interrupt */ + Cpu_Interrupt, /* 37 Default (unused) interrupt */ + Cpu_Interrupt, /* 38 Default (unused) interrupt */ + Cpu_Interrupt, /* 39 Default (unused) interrupt */ + Cpu_Interrupt, /* 40 Default (unused) interrupt */ + Cpu_Interrupt, /* 41 Default (unused) interrupt */ + Cpu_Interrupt, /* 42 Default (unused) interrupt */ + vCOM0_ISR, /* Defined in Demo/serial/serial.c */ + Cpu_Interrupt, /* 44 Default (unused) interrupt */ + Cpu_Interrupt, /* 45 Default (unused) interrupt */ + Cpu_Interrupt, /* 46 Default (unused) interrupt */ + Cpu_Interrupt, /* 47 Default (unused) interrupt */ + Cpu_Interrupt, /* 48 Default (unused) interrupt */ + Cpu_Interrupt, /* 49 Default (unused) interrupt */ + Cpu_Interrupt, /* 50 Default (unused) interrupt */ + Cpu_Interrupt, /* 51 Default (unused) interrupt */ + Cpu_Interrupt, /* 52 Default (unused) interrupt */ + Cpu_Interrupt, /* 53 Default (unused) interrupt */ + Cpu_Interrupt, /* 54 Default (unused) interrupt */ + vPortTickInterrupt, /* The RTOS tick. */ + Cpu_Interrupt, /* 56 Default (unused) interrupt */ + Cpu_Interrupt, /* 57 Default (unused) interrupt */ + Cpu_Interrupt, /* 58 Default (unused) interrupt */ + vPortYield, /* RTOS yield software interrupt. */ + Cpu_Interrupt, /* 60 Default (unused) interrupt */ + Cpu_Interrupt, /* 61 Default (unused) interrupt */ + Cpu_Interrupt, /* 62 Default (unused) interrupt */ + _EntryPoint /* Reset vector */ + }; +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/20080212/Demo/HCS12_CodeWarrior_banked/C_Layout.hwl b/20080212/Demo/HCS12_CodeWarrior_banked/C_Layout.hwl new file mode 100644 index 000000000..3b16d98a4 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_banked/C_Layout.hwl @@ -0,0 +1,20 @@ +OPEN source 0 0 60 39 +Source < attributes MARKS off +OPEN assembly 60 0 40 31 +Assembly < attributes ADR on,CODE off,ABSADR on,SYMB off,TOPPC 0xF88C +OPEN procedure 0 39 60 17 +Procedure < attributes VALUES on,TYPES off +OPEN register 60 31 40 25 +Register < attributes FORMAT AUTO,COMPLEMENT None +OPEN memory 60 56 40 22 +Memory < attributes FORMAT hex,COMPLEMENT None,WORD 1,ASC on,ADR on,ADDRESS 0x80 +OPEN data 0 56 60 22 +Data:1 < attributes SCOPE global,COMPLEMENT None,FORMAT Symb,MODE automatic,UPDATERATE 10,NAMEWIDTH 16 +OPEN data 0 78 60 22 +Data:2 < attributes SCOPE local,COMPLEMENT None,FORMAT Symb,MODE automatic,UPDATERATE 10,NAMEWIDTH 16 +OPEN command 60 78 40 22 +Command < attributes CACHESIZE 1000 +bckcolor 50331647 +font 'Courier New' 9 BLACK +AUTOSIZE on +ACTIVATE Data:2 Command Procedure Data:1 Source Register Assembly Memory diff --git a/20080212/Demo/HCS12_CodeWarrior_banked/DOC/RTOSDemo.sig b/20080212/Demo/HCS12_CodeWarrior_banked/DOC/RTOSDemo.sig new file mode 100644 index 000000000..8aea029d4 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_banked/DOC/RTOSDemo.sig @@ -0,0 +1,23 @@ +================================================================= +This file was generated from Processor Expert 03.33 + project "RTOSDemo", 19/06/2005, 15:54 +----------------------------------------------------------------- +There is no signal defined in this project. + Hint: Signals may be defined in the Bean Inspector (advanced or expert view) +================================================================= + +================================================================= + SIGNAL LIST +----------------------------------------------------------------- + SIGNAL NAME => PIN NAME +----------------------------------------------------------------- +================================================================= + + +================================================================= + PIN LIST +----------------------------------------------------------------- + PIN NAME => SIGNAL NAME +----------------------------------------------------------------- +================================================================= + diff --git a/20080212/Demo/HCS12_CodeWarrior_banked/DOC/RTOSDemo.txt b/20080212/Demo/HCS12_CodeWarrior_banked/DOC/RTOSDemo.txt new file mode 100644 index 000000000..479e92c6c --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_banked/DOC/RTOSDemo.txt @@ -0,0 +1,43 @@ +============================================================================= +List of methods in project: RTOSDemo + +THIS TEXT DESCRIPTION IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +============================================================================= + +Module "TickTimer" (bean TimerInt) + TickTimer_Enable -Enable the bean - it starts the timer. Events may be generated ("DisableEvent"/"EnableEvent"). + TickTimer_SetPeriodTicks16 -This method sets the new period of the generated events. The period is expressed in CPU [ticks] + as a 16-bit unsigned integer number. This method is available only if runtime setting type 'from interval' is + selected in the in Runtime setting area. + TickTimer_SetPeriodTicks32 -This method sets the new period of the generated events. The period is expressed in CPU [ticks] + as a 32-bit unsigned integer number. This method is available only if runtime setting type 'from interval' is + selected in the in Runtime setting area. + TickTimer_SetPeriodUS -This method sets the new period of the generated events. The period is expressed in [microseconds] as + a 16-bit unsigned integer number. This method is available only if runtime setting type 'from interval' is + selected in the in Runtime setting area. + TickTimer_SetPeriodMS -This method sets the new period of the generated events. The period is expressed in [miliseconds] as + a 16-bit unsigned integer number. This method is available only if runtime setting type 'from interval' is + selected in the in Runtime setting area. + TickTimer_SetFreqHz -This method sets the new frequency of the generated events. The frequency is expressed in [Hz] as a + 16-bit unsigned integer number. This method is available only if runtime setting type 'from interval' is + selected in the in Runtime setting area. + +Module "Byte1" (bean ByteIO) + Byte1_PutBit -Put the specified value to the specified bit/pin of the Input/Output bean. If direction is [input] saves the + value to a memory or a register, this value will be written to the pin after switching to the output mode - + using [SetDir(TRUE)]. If direction is [output] writes the value to the pin. + Byte1_NegBit -Negate (invert) the specified bit of the Input/Output bean. It is the same as [PutBit(Bit,!GetBit(Bit))]. + +Module "COM0" (bean AsynchroSerial) + COM0_SetBaudRateMode -This method changes the channel communication speed (baud rate). This method can be used only if you + specify a list of possible period settings at design time (see - Runtime setting - from a + list of values). Each of these settings constitutes a mode and Processor Expert^[TM] assigns them a mode + identifier. The prescaler and compare values corresponding to each mode are calculated at design time. You may + switch modes at runtime by referring only to a mode identifier. No run-time calculations are performed, all the + calculations are performed at design time. + +Module "Cpu" (bean MC9S12DP256_112) + Cpu_EnableInt -Enable maskable interrupts + Cpu_DisableInt -Disable maskable interrupts + +============================================================================= diff --git a/20080212/Demo/HCS12_CodeWarrior_banked/FreeRTOSConfig.h b/20080212/Demo/HCS12_CodeWarrior_banked/FreeRTOSConfig.h new file mode 100644 index 000000000..378216f1b --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_banked/FreeRTOSConfig.h @@ -0,0 +1,102 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include /* common defines and macros */ +#include "TickTimer.h" + +/* This port requires the compiler to generate code for the BANKED memory +model. */ +#define BANKED_MODEL + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 0 +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 80 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 10240 ) ) +#define configMAX_TASK_NAME_LEN ( 1 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 1 +#define configIDLE_SHOULD_YIELD 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* This parameter is normally required in order to set the RTOS tick timer. +This port is a bit different in that hardware setup uses the code generated by +the Processor Expert, making this definition obsolete. + +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 25000000 ) +*/ + + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + + + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/HCS12_CodeWarrior_banked/P&E_ICD.ini b/20080212/Demo/HCS12_CodeWarrior_banked/P&E_ICD.ini new file mode 100644 index 000000000..628984302 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_banked/P&E_ICD.ini @@ -0,0 +1,71 @@ +[Environment Variables] +GENPATH={Compiler}lib\HC12c\src;{Compiler}lib\HC12c\include;{Compiler}lib\HC12c\lib +LIBPATH={Compiler}lib\HC12c\include +OBJPATH={Project}bin +TEXTPATH={Project}bin +ABSPATH={Project}bin + +[HI-WAVE] +Target=icd12 +Layout=C_layout.hwl +LoadDialogOptions=AUTOERASEANDFLASH +CPU=HC12 +MainFrame=2,3,-1,-1,-1,-1,54,54,1254,908 +TOOLBAR=57600 57601 32795 0 57635 57634 57637 0 57671 57669 0 32777 32776 32782 32780 32781 32778 0 32806 +AEFWarningDialog=FALSE + +[ICD12] +CMDFILE0=CMDFILE STARTUP ON ".\cmd\p&e_icd_startup.cmd" +CMDFILE1=CMDFILE RESET ON ".\cmd\p&e_icd_reset.cmd" +CMDFILE2=CMDFILE PRELOAD ON ".\cmd\p&e_icd_preload.cmd" +CMDFILE3=CMDFILE POSTLOAD ON ".\cmd\p&e_icd_postload.cmd" +CMDFILE4=CMDFILE VPPON ON ".\cmd\p&e_icd_vppon.cmd" +CMDFILE5=CMDFILE VPPOFF ON ".\cmd\p&e_icd_vppoff.cmd" +CMDFILE6=CMDFILE UNSECURE ON ".\cmd\P&E_ICD_erase_unsecure_hcs12.cmd" +MCUID=0x3C6 +CHIPSECURE=CHIPSECURE SETUP 0xFF0F 0x3 0x2 +BDMClockSpeed=14 +BNKA_MCUID03C6_BANKWINDOW0=BANKWINDOW PPAGE ON 0x8000..0xBFFF 0x30 16 0x30 +BNKA_MCUID03C6_BANKWINDOW1=BANKWINDOW DPAGE OFF 0x7000..0x7FFF 0x34 256 0x0 +BNKA_MCUID03C6_BANKWINDOW2=BANKWINDOW EPAGE OFF 0x400..0x7FF 0x36 256 0x0 +HWBPD_MCUID03C6_HWBPM0=HWBPM MODE AUTOMATIC BPM22BITS 0x28 SKIP_OFF +HWBPD_MCUID03C6_BKPT_REMAP0=HWBPM REMAP_22BITS RANGE 0x4000 0x7FFF 0x3E +HWBPD_MCUID03C6_BKPT_REMAP1=HWBPM REMAP_22BITS RANGE 0xC000 0xFFFF 0x3F +HWBPD_MCUID03C6_HWBPM1=HWBPM SET16BITS 0x0 0x0 0x0 0x0 +HWBPD_MCUID03C6_HWBPM2=HWBPM SET22BITS 0x0 0x0 0x0 0x0 +BDMAutoSpeed=0 +COMDEVICE=SETCOMM COMPORT USB "USB-PE5014402" +SETCLKSW=1 +DETECTRUNNING=0 +ISRDISABLEDSTEP=0 +SHOWPROT=1 +NV_PARAMETER_FILE=C:\devtools\Metrowerks\CodeWarrior CW12_V3.1\prog\FPP\mcu03C6.fpp +NV_SAVE_WSP=0 +NV_AUTO_ID=1 +DMM_MCUID03C6_MODULE0=Registers 0x0 0x400 1 4 0 2 1 1 +DMM_MCUID03C6_MODULE1=Ram 0x1000 0x3000 2 5 0 3 1 1 +DMM_MCUID03C6_MODULE2=Eeprom 0x0 0x1000 3 5 1 4 1 1 +DMM_MCUID03C6_MODULE3=Banked£memory 0x8000 0x2f4000 100 6 0 6 1 0 +DMM_MCUID03C6_MODULE4=Banked£flash 0x308000 0xf4000 101 6 1 5 1 0 +DMM_MCUID03C6_MODULE5=Unbanked£flash£4000 0x4000 0x4000 102 5 1 5 1 1 +DMM_MCUID03C6_MODULE6=Unbanked£flash£C000 0xc000 0x4000 103 5 1 5 1 1 +HOTPLUGGING=0 +REALTIMEHWBP=0 +NOREADWHILERUNNING=0 +RESYNCONCOPRESET=0 + +[Recent Applications File List] +File1=E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_banked\bin\P&E_ICD.abs +File2=E:\Dev\FreeRTOS\Demo\MC9S12DP256_CodeWarrior\bin\P&E_ICD.abs +File3= +File4= +LoadFlags1=4099 +LoadFlags2=4099 +LoadFlags3=0 +LoadFlags4=0 + +[Recent Layout File List] +File1=C_layout.hwl +File2= +File3= +File4= diff --git a/20080212/Demo/HCS12_CodeWarrior_banked/ParTest/ParTest.c b/20080212/Demo/HCS12_CodeWarrior_banked/ParTest/ParTest.c new file mode 100644 index 000000000..365ee3927 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_banked/ParTest/ParTest.c @@ -0,0 +1,79 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "portable.h" + +/* Processor Expert created headers. */ +#include "byte1.h" + +/* Demo application include files. */ +#include "partest.h" + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ + /* This function is required as it is called from the standard demo + application files. All it does however is call the Processor Expert + created function. */ + portENTER_CRITICAL(); + Byte1_PutBit( uxLED, !xValue ); + portEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ + /* This function is required as it is called from the standard demo + application files. All it does however is call the processor Expert + created function. */ + portENTER_CRITICAL(); + Byte1_NegBit( uxLED ); + portEXIT_CRITICAL(); +} + + + diff --git a/20080212/Demo/HCS12_CodeWarrior_banked/RTOSDemo.G_C b/20080212/Demo/HCS12_CodeWarrior_banked/RTOSDemo.G_C new file mode 100644 index 000000000..7840d35f7 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_banked/RTOSDemo.G_C @@ -0,0 +1,500 @@ +;Please do not modify this file! +;The file contains internal information about the Processor Expert project generation +[Options] +ProjectName=RTOSDemo +ProjectDirectory=E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_banked\ +DestEventsDirectory=CODE\ +DestDriversSubDirectory= +DestDocumentationDirectory=DOC\ +DestCompiledFilesSubDirectory= +DestFpgaSubDirectory= +DestTemporaryDirectory= +[GenFiles] +LinkerFileGenerated=Yes +MakefileGenerated=No +GenSharedModules=5 +Line=PE_Types +Line=PE_Error +Line=PE_Const +Line=IO_Map +Line=PE_Timer +ShrdHeaderAge0=852337107 +ShrdCodeAge0=-1 +ShrdAsemblAge0=-1 +ShrdHeaderAge1=852337107 +ShrdCodeAge1=-1 +ShrdAsemblAge1=-1 +ShrdHeaderAge2=852337107 +ShrdCodeAge2=-1 +ShrdAsemblAge2=-1 +ShrdHeaderAge3=852337107 +ShrdCodeAge3=852337107 +ShrdAsemblAge3=-1 +ShrdHeaderAge4=852395090 +ShrdCodeAge4=852395090 +ShrdAsemblAge4=-1 +GenExtraFiles=2 +Line=E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_banked\CODE\Vectors.c +Line=E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_banked\CODE\PESL.h +XtraAge0=852534276 +XtraAge1=852337108 +GenExtraFileType1=4 +GenExtraFileType0=4 +GenEventModules=1 +Line=Events +GenMethodsInEvents=0 +GenAllModules=10 +Line=Byte1 +Line=COM0 +Line=Cpu +Line=Events +Line=IO_Map +Line=PE_Const +Line=PE_Error +Line=PE_Timer +Line=PE_Types +Line=TickTimer +GenExternModules=0 +GenBeanModules=3 +Line=COM0 +Line=Byte1 +Line=TickTimer +SignalListFile=E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_banked\DOC\RTOSDemo.sig +DestinationCompiler=MetrowerksHC12CC +ProjectModificationStamp=28 + +[4] +Generated=Yes +GenCompName=Cpu +GenEventModule=Events +HeaderAge=852395091 +CodeAge=852656823 +AsemblAge=-1 +GenNumMethods=10 +SetStopMode=No +SetWaitMode=No +DisableInt=Yes +EnableInt=Yes +GetIntVect=No +SetIntVect=No +GetSpeedMode=No +SetSlowSpeed=No +SetLowSpeed=No +SetHighSpeed=No +GenNumEvents=4 +OnClockMonitorFail_Selected=1 +OnClockMonitorFail_Name=Cpu_OnClockMonitorFail +OnClockMonitorFail_Priority=interrupts disabled +OnIllegalOpcode_Selected=1 +OnIllegalOpcode_Name=Cpu_OnIllegalOpcode +OnIllegalOpcode_Priority=interrupts disabled +OnReset_Selected=1 +OnReset_Name=Cpu_OnReset +OnReset_Priority=interrupts disabled +OnSwINT_Selected=1 +OnSwINT_Name=Cpu_OnSwINT +OnSwINT_Priority=interrupts disabled +GenSmartUserChangesDetected_Header=No +GenSmartUserChangesDetected_Code=No +GenSmartUserChangesDetected_Asembl=No + +[6] +Generated=Yes +GenCompName=TickTimer +GenEventModule=Events +HeaderAge=852656822 +CodeAge=852656822 +AsemblAge=-1 +GenNumMethods=14 +SetFreqMHz=No +SetFreqkHz=No +SetFreqHz=Yes +SetPeriodReal=No +SetPeriodSec=No +SetPeriodMS=Yes +SetPeriodUS=Yes +SetPeriodTicks32=Yes +SetPeriodTicks16=Yes +SetPeriodMode=No +DisableEvent=No +EnableEvent=No +Disable=No +Enable=Yes +GenNumEvents=3 +BeforeNewSpeed_Selected=1 +BeforeNewSpeed_Name=TickTimer_BeforeNewSpeed +BeforeNewSpeed_Priority=interrupts disabled +AfterNewSpeed_Selected=1 +AfterNewSpeed_Name=TickTimer_AfterNewSpeed +AfterNewSpeed_Priority=interrupts disabled +OnInterrupt_Selected=2 +OnInterrupt_Name=TickTimer_OnInterrupt +OnInterrupt_Priority=same as interrupt +GenSmartUserChangesDetected_Header=No +GenSmartUserChangesDetected_Code=No +GenSmartUserChangesDetected_Asembl=No +GenMethodPos=19 +MethodPos0=Enable +MethodType=method +ModuleType=Header +LineBeg=92 +LineEnd=108 +MethodPos1=SetPeriodTicks16 +MethodType=method +ModuleType=Header +LineBeg=109 +LineEnd=134 +MethodPos2=SetPeriodTicks32 +MethodType=method +ModuleType=Header +LineBeg=135 +LineEnd=160 +MethodPos3=SetPeriodUS +MethodType=method +ModuleType=Header +LineBeg=161 +LineEnd=186 +MethodPos4=SetPeriodMS +MethodType=method +ModuleType=Header +LineBeg=187 +LineEnd=212 +MethodPos5=SetFreqHz +MethodType=method +ModuleType=Header +LineBeg=213 +LineEnd=238 +MethodPos6=Interrupt +MethodType=internal_method +ModuleType=Header +LineBeg=239 +LineEnd=251 +MethodPos7=Init +MethodType=internal_method +ModuleType=Header +LineBeg=252 +LineEnd=262 +MethodPos8=SetCV +MethodType=internal_method +ModuleType=Code +LineBeg=85 +LineEnd=101 +MethodPos9=SetPV +MethodType=internal_method +ModuleType=Code +LineBeg=102 +LineEnd=115 +MethodPos10=HWEnDi +MethodType=internal_method +ModuleType=Code +LineBeg=116 +LineEnd=130 +MethodPos11=Enable +MethodType=method +ModuleType=Code +LineBeg=131 +LineEnd=151 +MethodPos12=SetPeriodTicks16 +MethodType=method +ModuleType=Code +LineBeg=152 +LineEnd=190 +MethodPos13=SetPeriodTicks32 +MethodType=method +ModuleType=Code +LineBeg=191 +LineEnd=229 +MethodPos14=SetPeriodUS +MethodType=method +ModuleType=Code +LineBeg=230 +LineEnd=268 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+ +[InterruptVectors] +WindowVisible=No +Rect=[0|0|0|0] + +[MemoryMap] +Rect=[422|156|355|480] +DisplayOnlyMemories=No +WindowVisible=No + +[Browser] +Rect=[0|0|0|0] +WindowVisible=No + +[BeanManager] +Rect=[0|0|0|0] +BeanInfoFilter= +DriverFilter= +DriverInfoFilter= +BeanSettingsProjectFilter= + +[Options] +AutosaveWithProject=No +AutosaveBeforeTool=No +NumberOfBackupCopies=0 +AutoSaveDesktop=Yes +AutoOpenPropEdit=Yes +AutoConnectDevice=Yes +SelectTemplate=No +ShowGenProgress=Yes +AutoShowGeneratedSrc=No +AutoShowEventModules=No +ShowMethodCode=No +GenerateUndo=No +CpuBitmapFileName=Config\PE\CPUbckgr.bmp +CpuBitmapTilled=No +ShowProducerLogo=No +AutoStartApplicationCode=No +ShowSourceLinAfterDbgInit=No +RestoreFilesAfterDebug=No + +[_end_] diff --git a/20080212/Demo/HCS12_CodeWarrior_banked/RTOSDemo.mcp b/20080212/Demo/HCS12_CodeWarrior_banked/RTOSDemo.mcp new file mode 100644 index 0000000000000000000000000000000000000000..dc22dc46c743cfe2e374d8a12b6e7f54bd57c38f GIT binary patch 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+[ItemState] +ItemSymbol=InfraredSCI +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=No + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=SCINarrowPulse +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=0 + +[EndOfChilds] + +[EndOfChilds] + +[EndOfChilds] +[ItemState] +ItemSymbol=COP8grp +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=Attention +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Index=1 +Value=No +[ItemState] +ItemSymbol=ClockPin +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=No + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=Clk +ReadOnly=Yes +UserReadOnly=No +BasAdvHid=BASIC +Value= +SharedPrphMode=No +[ItemState] +ItemSymbol=ClkPinSignal +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value= +[ItemState] +ItemSymbol=ClockPinDirection +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Index=0 +[ItemState] +ItemSymbol=BaudSource +ReadOnly=No +UserReadOnly=No +BasAdvHid=EXPERT + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=TxBaudSource +ReadOnly=No +UserReadOnly=No +BasAdvHid=EXPERT +Index=0 +[ItemState] +ItemSymbol=RxBaudSource +ReadOnly=No +UserReadOnly=No +BasAdvHid=EXPERT +Index=0 + +[EndOfChilds] + +[EndOfChilds] + +[EndOfChilds] +[ItemState] +ItemSymbol=_InitializationGrp +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=InitEnable +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=0 +Value=Yes +[ItemState] +ItemSymbol=InitEnableEvents +ReadOnly=Yes +UserReadOnly=No +BasAdvHid=ADVANCED +Index=0 +Value=Yes + +[EndOfChilds] +[ItemState] +ItemSymbol=_SpeedGrp +ReadOnly=No +UserReadOnly=No +BasAdvHid=EXPERT + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=HighSpeed +ReadOnly=No +UserReadOnly=No +BasAdvHid=EXPERT +Index=0 +Value=Yes +[ItemState] +ItemSymbol=LowSpeed +ReadOnly=No +UserReadOnly=No +BasAdvHid=EXPERT +Index=1 +Value=No +[ItemState] +ItemSymbol=SlowSpeed +ReadOnly=No +UserReadOnly=No +BasAdvHid=EXPERT +Index=1 +Value=No + +[EndOfChilds] + +[Methods] +List=Method +[ItemState] +ItemSymbol=Enable +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=Enable +[ItemState] +ItemSymbol=Disable +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=Disable +[ItemState] +ItemSymbol=EnableEvent +ReadOnly=Yes +UserReadOnly=No +BasAdvHid=ADVANCED +Index=1 +Value=No +LastSelection=No +LastUserSel=never +UsrMethodName=EnableEvent +[ItemState] +ItemSymbol=DisableEvent +ReadOnly=Yes +UserReadOnly=No +BasAdvHid=ADVANCED +Index=1 +Value=No +LastSelection=No +LastUserSel=never +UsrMethodName=DisableEvent +[ItemState] +ItemSymbol=RecvChar +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=RecvChar +[ItemState] +ItemSymbol=SendChar +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=SendChar +[ItemState] +ItemSymbol=RecvBlock +ReadOnly=Yes +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=No +LastUserSel=never +UsrMethodName=RecvBlock +[ItemState] +ItemSymbol=SendBlock +ReadOnly=Yes +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=No +LastUserSel=never +UsrMethodName=SendBlock +[ItemState] +ItemSymbol=ClearRxBuf +ReadOnly=Yes +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=No +LastUserSel=never +UsrMethodName=ClearRxBuf +[ItemState] +ItemSymbol=ClearTxBuf +ReadOnly=Yes +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=No +LastUserSel=never +UsrMethodName=ClearTxBuf +[ItemState] +ItemSymbol=CharsInRxBuf +ReadOnly=No +UserReadOnly=No +BasAdvHid=EXPERT +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=CharsInRxBuf +[ItemState] +ItemSymbol=GetCharsInRxBuf +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=GetCharsInRxBuf +[ItemState] +ItemSymbol=CharsInTxBuf +ReadOnly=No +UserReadOnly=No +BasAdvHid=EXPERT +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=CharsInTxBuf +[ItemState] +ItemSymbol=GetCharsInTxBuf +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=GetCharsInTxBuf +[ItemState] +ItemSymbol=SetBaudRateMode +ReadOnly=Yes +UserReadOnly=No +BasAdvHid=BASIC +Index=0 +Value=Yes +LastSelection=Yes +LastUserSel=always +UsrMethodName=SetBaudRateMode +[ItemState] +ItemSymbol=GetError +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=GetError +[ItemState] +ItemSymbol=GetBreak +ReadOnly=Yes +UserReadOnly=No +BasAdvHid=ADVANCED +Index=1 +Value=No +LastSelection=Yes +LastUserSel=never +UsrMethodName=GetBreak +[ItemState] +ItemSymbol=CPUCond2 +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=SetBreak0 +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Index=0 +Value=Yes +LastSelection=No +LastUserSel=yes +UsrMethodName=SetBreak + +[EndOfChilds] +[ItemState] +ItemSymbol=SetBreak +ReadOnly=Yes +UserReadOnly=No +BasAdvHid=ADVANCED +Index=1 +Value=No +LastSelection=Yes +LastUserSel=never +UsrMethodName=SetBreak +[ItemState] +ItemSymbol=SetAttentionMode +ReadOnly=No +UserReadOnly=No +BasAdvHid=@ HIDDEN @ +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=SetAttentionMode +[ItemState] +ItemSymbol=TurnTxOn +ReadOnly=No +UserReadOnly=No +BasAdvHid=EXPERT +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=TurnTxOn +[ItemState] +ItemSymbol=TurnTxOff +ReadOnly=No +UserReadOnly=No +BasAdvHid=EXPERT +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=TurnTxOff +[ItemState] +ItemSymbol=SetRxBaudGenerator +ReadOnly=No +UserReadOnly=No +BasAdvHid=@ HIDDEN @ +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=SetRxBaudGenerator +[ItemState] +ItemSymbol=SetTxBaudGenerator +ReadOnly=No +UserReadOnly=No +BasAdvHid=@ HIDDEN @ +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=SetTxBaudGenerator +[ItemState] +ItemSymbol=CPUCond +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=TurnRxOn +ReadOnly=No +UserReadOnly=No +BasAdvHid=EXPERT +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=TurnRxOn +[ItemState] +ItemSymbol=TurnRxOff +ReadOnly=No +UserReadOnly=No +BasAdvHid=EXPERT +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=TurnRxOff +[ItemState] +ItemSymbol=SetIdle +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=SetIdle +[ItemState] +ItemSymbol=LoopMode +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=LoopMode + +[EndOfChilds] +[ItemState] +ItemSymbol=CPUCond1 +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=Standby +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=Standby + +[EndOfChilds] +[ItemState] +ItemSymbol=ESCIMethodsGrp +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=GetArbiterStatus +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=GetArbiterStatus +[ItemState] +ItemSymbol=ResetArbiterCounter +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=ResetArbiterCounter +[ItemState] +ItemSymbol=GetArbiterCounter +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=GetArbiterCounter +[ItemState] +ItemSymbol=SetFallingEdgesMeasurement +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=SetFallingEdgesMeasurement +[ItemState] +ItemSymbol=SetLowLevelMeasurement +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=SetLowLevelMeasurement +[ItemState] +ItemSymbol=ClearArbiterFlags +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=ClearArbiterFlags +[ItemState] +ItemSymbol=SetArbitrationMode +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=SetArbitrationMode +[ItemState] +ItemSymbol=AdjustBaudRate +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=AdjustBaudRate + +[EndOfChilds] +[ItemState] +ItemSymbol=CPU_HCS08_HCS12 +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=SetDirection +ReadOnly=Yes +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=No +LastUserSel=never +UsrMethodName=SetDirection + +[EndOfChilds] +[ItemState] +ItemSymbol=56800grp +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=ConnectPin +ReadOnly=No +UserReadOnly=No +BasAdvHid=EXPERT +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=ConnectPin + +[EndOfChilds] + +[Events] +List=Event +[ItemState] +ItemSymbol=EventModule +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Value=Events +[ItemState] +ItemSymbol=BeforeNewSpeed +ReadOnly=No +UserReadOnly=No +BasAdvHid=EXPERT +Value=No + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=Name +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=COM0_BeforeNewSpeed + +[EndOfChilds] +LastSelection=No +LastUserSel=no +[ItemState] +ItemSymbol=AfterNewSpeed +ReadOnly=No +UserReadOnly=No +BasAdvHid=EXPERT +Value=No + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=Name +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=COM0_AfterNewSpeed + +[EndOfChilds] +LastSelection=No +LastUserSel=no +[ItemState] +ItemSymbol=OnError +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=No + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=Name +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=COM0_OnError +[ItemState] +ItemSymbol=Priority +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Value=same as interrupt + +[EndOfChilds] +LastSelection=Yes +LastUserSel=no +[ItemState] +ItemSymbol=OnRxChar +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=No + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=Name +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=COM0_OnRxChar +[ItemState] +ItemSymbol=Priority +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Value=same as interrupt + +[EndOfChilds] +LastSelection=Yes +LastUserSel=no +[ItemState] +ItemSymbol=OnTxChar +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=No + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=Name +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=COM0_OnTxChar +[ItemState] +ItemSymbol=Priority +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Value=same as interrupt + +[EndOfChilds] +LastSelection=Yes +LastUserSel=no +[ItemState] +ItemSymbol=OnFullRxBuf +ReadOnly=Yes +UserReadOnly=No +BasAdvHid=BASIC +Value=No + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=Name +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=COM0_OnFullRxBuf +[ItemState] +ItemSymbol=Priority +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Value=same as interrupt + +[EndOfChilds] +LastSelection=Yes +LastUserSel=never +[ItemState] +ItemSymbol=OnFreeTxBuf +ReadOnly=Yes +UserReadOnly=No +BasAdvHid=BASIC +Value=No + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=Name +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=COM0_OnFreeTxBuf +[ItemState] +ItemSymbol=Priority +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Value=same as interrupt + +[EndOfChilds] +LastSelection=Yes +LastUserSel=never +[ItemState] +ItemSymbol=OnBreak +ReadOnly=Yes +UserReadOnly=No +BasAdvHid=ADVANCED +Value=No + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=Name +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=COM0_OnBreak +[ItemState] +ItemSymbol=Priority +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Value=same as interrupt + +[EndOfChilds] +LastSelection=Yes +LastUserSel=never +[ItemState] +ItemSymbol=CPUCond0 +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=OnIdle +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Value=No + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=Name +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=COM0_OnIdle +[ItemState] +ItemSymbol=Priority +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Value=same as interrupt + +[EndOfChilds] +LastSelection=No +LastUserSel=no + +[EndOfChilds] + +[Program] +ProgType=event +ProgNumb=2 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This is needed because it contains the stack top, and without stack, far data cannot be accessed */ +struct _tagStartup _startupData; /* read-only: */ + /* _startupData is allocated in ROM and */ + /* initialized by the linker */ +#pragma DATA_SEG DEFAULT +#if defined(FAR_DATA) +#include "non_bank.sgm" +/* the init function must be in non banked memory if banked variables are used */ +/* because _SET_PAGE is called, which may change any page register. */ + +#ifdef __cplusplus + extern "C" +#endif +void _SET_PAGE(void); /* the inline assembler needs a prototype */ + /* this is a runtime routine with a special */ + /* calling convention, dont use it in c code! */ +static void Init(void); +static void Fini(void); +#else +#include "default.sgm" +#if defined( __BANKED__) || defined(__LARGE__) +static void __far Init(void); +static void __far Fini(void); +#endif /* defined( __BANKED__) || defined(__LARGE__) */ +#endif /* FAR_DATA */ + + +/* define value and bits for Windef Register */ +#ifdef HC812A4 +#define WINDEF (*(volatile unsigned char*) 0x37) +#if defined( __BANKED__) || defined(__LARGE__) || defined(__PPAGE__) +#define __ENABLE_PPAGE__ 0x40 +#else +#define __ENABLE_PPAGE__ 0x0 +#endif +#if defined(__DPAGE__) +#define __ENABLE_DPAGE__ 0x80 +#else +#define __ENABLE_DPAGE__ 0x0 +#endif +#if defined(__EPAGE__) +#define __ENABLE_EPAGE__ 0x20 +#else +#define __ENABLE_EPAGE__ 0x0 +#endif +#endif /* HC812A4 */ + +#ifdef _HCS12_SERIALMON + /* for Monitor based software remap the RAM & EEPROM to adhere + to EB386. Edit RAM and EEPROM sections in PRM file to match these. */ +#define ___INITRM (*(volatile unsigned char *) 0x0010) +#define ___INITRG (*(volatile unsigned char *) 0x0011) +#define ___INITEE (*(volatile unsigned char *) 0x0012) +#endif + +#if defined(_DO_FEED_COP_) +#define __FEED_COP_IN_HLI() } __asm movb #0x55, _COP_RST_ADR; __asm movb #0xAA, _COP_RST_ADR; __asm { +#else +#define __FEED_COP_IN_HLI() /* do nothing */ +#endif + +#if !defined(FAR_DATA) && (defined( __BANKED__) || defined(__LARGE__)) +static void __far Init(void) +#else +static void Init(void) +#endif + { +/* purpose: 1) zero out RAM-areas where data is allocated */ +/* 2) copy initialization data from ROM to RAM */ +/* 3) call global constructors in C++ */ +/* called from: _Startup, LibInits */ + __asm { +ZeroOut: +#if defined(__HIWARE_OBJECT_FILE_FORMAT__) && defined(__LARGE__) + LDX _startupData.pZeroOut:1 ; in the large memory model in the HIWARE format, pZeroOut is a 24 bit pointer +#else + LDX _startupData.pZeroOut ; *pZeroOut +#endif + LDY _startupData.nofZeroOuts ; nofZeroOuts + BEQ CopyDown ; if nothing to zero out + +NextZeroOut: PSHY ; save nofZeroOuts +#ifdef FAR_DATA + LDAB 1,X+ ; load page of destination address + LDY 2,X+ ; load offset of destination address + __PIC_JSR(_SET_PAGE) ; sets the page in the correct page register +#else /* FAR_DATA */ + LDY 2,X+ ; start address and advance *pZeroOut (X = X+4) +#endif /* FAR_DATA */ + LDD 2,X+ ; byte count +#ifdef __OPTIMIZE_FOR_SIZE__ /* -os, default */ +NextWord: CLR 1,Y+ ; clear memory byte + __FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */ + DBNE D, NextWord ; dec byte count +#else + LSRD ; /2 and save bit 0 in the carry + PSHX + LDX #0 +LoopClrW: STX 2,Y+ ; Word-Clear + __FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */ + DBNE D, LoopClrW + PULX + BCC LastClr ; handle last byte + CLR 1,Y+ +LastClr: +#endif + PULY ; restore nofZeroOuts + DEY ; dec nofZeroOuts + BNE NextZeroOut +CopyDown: +#ifdef __ELF_OBJECT_FILE_FORMAT__ + LDX _startupData.toCopyDownBeg ; load address of copy down desc. +#else + LDX _startupData.toCopyDownBeg:2 ; load address of copy down desc. +#endif +NextBlock: + LDD 2,X+ ; size of init-data -> D + BEQ funcInits ; end of copy down desc. +#ifdef FAR_DATA + PSHD ; save counter + LDAB 1,X+ ; load destination page + LDY 2,X+ ; destination address + __PIC_JSR(_SET_PAGE) ; sets the destinations page register + PULD ; restore counter +#else /* FAR_DATA */ + LDY 2,X+ ; load destination address +#endif /* FAR_DATA */ + +#ifdef __OPTIMIZE_FOR_SIZE__ /* -os, default */ +Copy: MOVB 1,X+,1,Y+ ; move a byte from ROM to the data area + __FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */ + DBNE D,Copy ; copy-byte loop +#else + LSRD ; /2 and save bit 0 in the carry +Copy: MOVW 2,X+,2,Y+ ; move a word from ROM to the data area + __FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */ + DBNE D,Copy ; copy-word loop + BCC NextBlock ; handle last byte? + MOVB 1,X+,1,Y+ ; copy the last byte +#endif + BRA NextBlock +funcInits: ; call of global construtors is only in c++ necessary +#if defined(__cplusplus) +#if defined(__ELF_OBJECT_FILE_FORMAT__) +#if defined( __BANKED__) || defined(__LARGE__) + LDY _startupData.nofInitBodies; load number of cpp. + BEQ done ; if cppcount == 0, goto done + LDX _startupData.initBodies ; load address of first module to initialize +nextInit: + LEAX 3,X ; increment to next init + PSHX ; save address of next function to initialize + PSHY ; save cpp counter + CALL [-3,X] ; use double indirect call to load the page register also + PULY ; restore cpp counter + PULX ; restore actual address + DEY ; decrement cpp counter + BNE nextInit +#else /* defined( __BANKED__) || defined(__LARGE__) */ + + LDD _startupData.nofInitBodies; load number of cpp. + BEQ done ; if cppcount == 0, goto done + LDX _startupData.initBodies ; load address of first module to initialize +nextInit: + LDY 2,X+ ; load address of first module to initialize + PSHD + PSHX ; save actual address + JSR 0,Y ; call initialization function + PULX ; restore actual address + PULD ; restore cpp counter + DBNE D, nextInit +#endif /* defined( __BANKED__) || defined(__LARGE__) */ +#else /* __ELF_OBJECT_FILE_FORMAT__ */ + LDX _startupData.mInits ; load address of first module to initialize +#if defined( __BANKED__) || defined(__LARGE__) +nextInit: LDY 3,X+ ; load address of initialization function + BEQ done ; stop when address == 0 + ; in common environments the offset of a function is never 0, so this test could be avoided +#ifdef __InitFunctionsMayHaveOffset0__ + BRCLR -1,X, done, 0xff ; stop when address == 0 +#endif /* __InitFunctionsMayHaveOffset0__ */ + PSHX ; save address of next function to initialize + CALL [-3,X] ; use double indirect call to load the page register also +#else /* defined( __BANKED__) || defined(__LARGE__) */ +nextInit: + LDY 2,X+ ; load address of first module to initialize + BEQ done ; stop when address of function == 0 + PSHX ; save actual address + JSR 0,Y ; call initialization function +#endif /* defined( __BANKED__) || defined(__LARGE__) */ + PULX ; restore actual address + BRA nextInit +#endif /* __ELF_OBJECT_FILE_FORMAT__ */ +done: +#endif /* __cplusplus */ + } +} + +#if defined( __ELF_OBJECT_FILE_FORMAT__) && defined(__cplusplus ) + +#if !defined(FAR_DATA) && (defined( __BANKED__) || defined(__LARGE__)) +static void __far Fini(void) +#else +static void Fini(void) +#endif +{ +/* purpose: 1) call global destructors in C++ */ + __asm { +#if defined( __BANKED__) || defined(__LARGE__) + + LDY _startupData.nofFiniBodies; load number of cpp. + BEQ done ; if cppcount == 0, goto done + LDX _startupData.finiBodies ; load address of first module to finalize +nextInit2: + LEAX 3,X ; increment to next init + PSHX ; save address of next function to finalize + PSHY ; save cpp counter + CALL [-3,X] ; use double indirect call to load the page register also + PULY ; restore cpp counter + PULX ; restore actual address + DEY ; decrement cpp counter + BNE nextInit2 +#else /* defined( __BANKED__) || defined(__LARGE__) */ + + LDD _startupData.nofFiniBodies; load number of cpp. + BEQ done ; if cppcount == 0, goto done + LDX _startupData.finiBodies ; load address of first module to finalize +nextInit2: + LDY 2,X+ ; load address of first module to finalize + PSHD + PSHX ; save actual address + JSR 0,Y ; call finalize function + PULX ; restore actual address + PULD ; restore cpp counter + DBNE D, nextInit2 +#endif /* defined( __BANKED__) || defined(__LARGE__) */ +done:; + } +} +#endif + + +#include "non_bank.sgm" + +#pragma MESSAGE DISABLE C12053 /* Stack-pointer change not in debugging-information */ +#pragma NO_FRAME +#pragma NO_ENTRY +#pragma NO_EXIT + +#ifdef __cplusplus + extern "C" +#endif + +/* The function _Startup must be called in order to initialize global variables and to call main */ +/* You can adapt this function or call it from your startup code to implement a different startup */ +/* functionality. */ + +/* You should also setup the needed IO registers as WINDEF (HC12A4 only) or the COP registers to run */ +/* on hardware */ + +/* to set the reset vector several ways are possible : */ +/* 1. define the function with "interrupt 0" as done below in the first case */ +/* 2. add the following line to your prm file : VECTOR ADDRESS 0xfffe _Startup */ +/* of course, even more posibilities exists */ +/* the reset vector must be set so that the application has a defined entry point */ + +#define STARTUP_FLAGS_NOT_INIT_SP (1<<1) + +#if defined(__SET_RESET_VECTOR__) +void __interrupt 0 _Startup(void) { +#else +void _Startup(void) { +#endif +/* purpose: 1) initialize the stack + 2) initialize the RAM, copy down init data etc (Init) + 3) call main; + parameters: NONE + called from: _PRESTART-code generated by the Linker + or directly referenced by the reset vector */ + for(;;) { /* forever: initialize the program; call the root-procedure */ + if (!(_startupData.flags&STARTUP_FLAGS_NOT_INIT_SP)) { + /* initialize the stack pointer */ + INIT_SP_FROM_STARTUP_DESC(); /*lint !e522 asm code */ /* HLI macro definition in hidef.h */ + } + +#ifdef _HCS12_SERIALMON + /* for Monitor based software remap the RAM & EEPROM to adhere + to EB386. Edit RAM and EEPROM sections in PRM file to match these. */ + ___INITRG = 0x00; /* lock registers block to 0x0000 */ + ___INITRM = 0x39; /* lock Ram to end at 0x3FFF */ + ___INITEE = 0x09; /* lock EEPROM block to end at 0x0fff */ +#endif + + /* Here user defined code could be inserted, the stack could be used */ +#if defined(_DO_DISABLE_COP_) + _DISABLE_COP(); +#endif + + /* Example : Set up WinDef Register to allow Paging */ +#ifdef HC812A4 /* HC12 A4 derivative needs WINDEF to configure which pages are available */ +#if (__ENABLE_EPAGE__ != 0 || __ENABLE_DPAGE__ != 0 || __ENABLE_PPAGE__ != 0) + WINDEF= __ENABLE_EPAGE__ | __ENABLE_DPAGE__ | __ENABLE_PPAGE__; +#endif +#endif + Init(); /* zero out, copy down, call constructors */ + /* Here user defined code could be inserted, all global variables are initilized */ +#if defined(_DO_ENABLE_COP_) + _ENABLE_COP(1); +#endif + + /* call main() */ + (*_startupData.main)(); + + /* call destructors. Only done when this file is compiled as C++ and for the ELF object file format */ + /* the HIWARE object file format does not support this */ +#if defined( __ELF_OBJECT_FILE_FORMAT__) && defined(__cplusplus ) + Fini(); +#endif + + } /* end loop forever */ +} diff --git a/20080212/Demo/HCS12_CodeWarrior_banked/Sources/datapage.c b/20080212/Demo/HCS12_CodeWarrior_banked/Sources/datapage.c new file mode 100644 index 000000000..80be5c566 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_banked/Sources/datapage.c @@ -0,0 +1,843 @@ +/****************************************************************************** + FILE : datapage.c + PURPOSE : paged data access runtime routines + MACHINE : Motorola 68HC12 (Target) + LANGUAGE : ANSI-C + HISTORY : 21.7.96 first version created +******************************************************************************/ + +/* + According to the -Cp option of the compiler the + __DPAGE__, __PPAGE__ and __EPAGE__ macros are defined. + If none of them is given as argument, then no page accesses should occur and + this runtime routine should not be used ! + To be on the save side, the runtime routines are created anyway. + If some of the -Cp options are given an adapted versions which only covers the + needed cases is produced. +*/ + +/* if no compiler option -Cp is given, it is assumed that all possible are given : */ + +/* Compile with option -DHCS12 to activate this code */ +#if defined(HCS12) || defined(_HCS12) /* HCS12 family has PPAGE register only at 0x30 */ +#define PPAGE_ADDR (0x30+REGISTER_BASE) +#ifndef __PPAGE__ /* may be set already by option -CPPPAGE */ +#define __PPAGE__ +#endif +/* Compile with option -DDG128 to activate this code */ +#elif defined DG128 /* HC912DG128 derivative has PPAGE register only at 0xFF */ +#define PPAGE_ADDR (0xFF+REGISTER_BASE) +#ifndef __PPAGE__ /* may be set already by option -CPPPAGE */ +#define __PPAGE__ +#endif +#elif defined(HC812A4) +/* all setting default to A4 already */ +#endif + + +#if !defined(__EPAGE__) && !defined(__PPAGE__) && !defined(__DPAGE__) +/* as default use all page registers */ +#define __DPAGE__ +#define __EPAGE__ +#define __PPAGE__ +#endif + +/* modify the following defines to your memory configuration */ + +#define EPAGE_LOW_BOUND 0x400u +#define EPAGE_HIGH_BOUND 0x7ffu + +#define DPAGE_LOW_BOUND 0x7000u +#define DPAGE_HIGH_BOUND 0x7fffu + +#define PPAGE_LOW_BOUND (DPAGE_HIGH_BOUND+1) +#define PPAGE_HIGH_BOUND 0xBFFFu + +#define REGISTER_BASE 0x0u +#ifndef DPAGE_ADDR +#define DPAGE_ADDR (0x34u+REGISTER_BASE) +#endif +#ifndef EPAGE_ADDR +#define EPAGE_ADDR (0x36u+REGISTER_BASE) +#endif +#ifndef PPAGE_ADDR +#define PPAGE_ADDR (0x35u+REGISTER_BASE) +#endif + +/* + The following parts about the defines are assumed in the code of _GET_PAGE_REG : + - the memory region controlled by DPAGE is above the area controlled by the EPAGE and + below the area controlled by the PPAGE. + - the lower bound of the PPAGE area is equal to be the higher bound of the DPAGE area + 1 +*/ +#if EPAGE_LOW_BOUND >= EPAGE_HIGH_BOUND || EPAGE_HIGH_BOUND >= DPAGE_LOW_BOUND || DPAGE_LOW_BOUND >= DPAGE_HIGH_BOUND || DPAGE_HIGH_BOUND >= PPAGE_LOW_BOUND || PPAGE_LOW_BOUND >= PPAGE_HIGH_BOUND +#error /* please adapt _GET_PAGE_REG for this non default page configuration */ +#endif + +#if DPAGE_HIGH_BOUND+1 != PPAGE_LOW_BOUND +#error /* please adapt _GET_PAGE_REG for this non default page configuration */ +#endif + +#include "hidef.h" +#include "non_bank.sgm" +#include "runtime.sgm" + +/* this module does either control if any access is in the bounds of the specified page or */ +/* ,if only one page is specified, just use this page. */ +/* This behavior is controlled by the define USE_SEVERAL_PAGES. */ +/* If !USE_SEVERAL_PAGES does increase the performance significantly */ +/* NOTE : When !USE_SEVERAL_PAGES, the page is also set for accesses outside of the area controlled */ +/* by this single page. But this is usually no problem because the page is set again before any other access */ + +#if !defined(__DPAGE__) && !defined(__EPAGE__) && !defined(__PPAGE__) +/* no page at all is specified */ +/* only specifing the right pages will speed up these functions a lot */ +#define USE_SEVERAL_PAGES 1 +#elif defined(__DPAGE__) && defined(__EPAGE__) || defined(__DPAGE__) && defined(__PPAGE__) || defined(__EPAGE__) && defined(__PPAGE__) +/* more than one page register is used */ +#define USE_SEVERAL_PAGES 1 +#else + +#define USE_SEVERAL_PAGES 0 + +#if defined(__DPAGE__) /* check which pages are used */ +#define PAGE_ADDR PPAGE_ADDR +#elif defined(__EPAGE__) +#define PAGE_ADDR EPAGE_ADDR +#elif defined(__PPAGE__) +#define PAGE_ADDR PPAGE_ADDR +#else /* we dont know which page, decide it at runtime */ +#error /* must not happen */ +#endif + +#endif + + +#if USE_SEVERAL_PAGES /* only needed for several pages support */ +/*--------------------------- _GET_PAGE_REG -------------------------------- + Runtime routine to detect the right register depending on the 16 bit offset part + of an address. + This function is only used by the functions below. + + Depending on the compiler options -Cp different versions of _GET_PAGE_REG are produced. + + Arguments : + - Y : offset part of an address + + Result : + if address Y is controlled by a page register : + - X : address of page register if Y is controlled by an page register + - Zero flag cleared + - all other registers remain unchanged + + if address Y is not controlled by a page register : + - Zero flag is set + - all registers remain unchanged + + --------------------------- _GET_PAGE_REG ----------------------------------*/ + +#if defined(__DPAGE__) + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +static void NEAR _GET_PAGE_REG(void) { /*lint -esym(528, _GET_PAGE_REG) used in asm code */ + asm { +L_DPAGE: + CPY #DPAGE_LOW_BOUND ; test of lower bound of DPAGE +#if defined(__EPAGE__) + BLO L_EPAGE ; EPAGE accesses are possible +#else + BLO L_NOPAGE ; no paged memory below accesses +#endif + CPY #DPAGE_HIGH_BOUND ; test of higher bound DPAGE/lower bound PPAGE +#if defined(__PPAGE__) + BHI L_PPAGE ; EPAGE accesses are possible +#else + BHI L_NOPAGE ; no paged memory above accesses +#endif +FOUND_DPAGE: + LDX #DPAGE_ADDR ; load page register address and clear zero flag + RTS + +#if defined(__PPAGE__) +L_PPAGE: + CPY #PPAGE_HIGH_BOUND ; test of higher bound of PPAGE + BHI L_NOPAGE +FOUND_PPAGE: + LDX #PPAGE_ADDR ; load page register address and clear zero flag + RTS +#endif + +#if defined(__EPAGE__) +L_EPAGE: + CPY #EPAGE_LOW_BOUND ; test of lower bound of EPAGE + BLO L_NOPAGE + CPY #EPAGE_HIGH_BOUND ; test of higher bound of EPAGE + BHI L_NOPAGE + +FOUND_EPAGE: + LDX #EPAGE_ADDR ; load page register address and clear zero flag + RTS +#endif + +L_NOPAGE: + ORCC #0x04 ; sets zero flag + RTS + } +} + +#else /* !defined(__DPAGE__) */ + +#if defined( __PPAGE__ ) + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +static void NEAR _GET_PAGE_REG(void) { /*lint -esym(528, _GET_PAGE_REG) used in asm code */ + asm { +L_PPAGE: + CPY #PPAGE_LOW_BOUND ; test of lower bound of PPAGE +#if defined( __EPAGE__ ) + BLO L_EPAGE +#else + BLO L_NOPAGE ; no paged memory below +#endif + CPY #PPAGE_HIGH_BOUND ; test of higher bound PPAGE + BHI L_NOPAGE +FOUND_PPAGE: + LDX #PPAGE_ADDR ; load page register address and clear zero flag + RTS +#if defined( __EPAGE__ ) +L_EPAGE: + CPY #EPAGE_LOW_BOUND ; test of lower bound of EPAGE + BLO L_NOPAGE + CPY #EPAGE_HIGH_BOUND ; test of higher bound of EPAGE + BHI L_NOPAGE +FOUND_EPAGE: + LDX #EPAGE_ADDR ; load page register address and clear zero flag + RTS +#endif + +L_NOPAGE: ; not in any allowed page area + ; its a far access to a non paged variable + ORCC #0x04 ; sets zero flag + RTS + } +} + +#else /* !defined(__DPAGE__ ) && !defined( __PPAGE__) */ +#if defined(__EPAGE__) + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +static void NEAR _GET_PAGE_REG(void) { /*lint -esym(528, _GET_PAGE_REG) used in asm code */ + asm { +L_EPAGE: + CPY #EPAGE_LOW_BOUND ; test of lower bound of EPAGE + BLO L_NOPAGE + CPY #EPAGE_HIGH_BOUND ; test of higher bound of EPAGE + BHI L_NOPAGE +FOUND_EPAGE: + LDX #EPAGE_ADDR ; load page register address and clear zero flag + RTS + +L_NOPAGE: ; not in any allowed page area + ; its a far access to a non paged variable + ORCC #0x04 ; sets zero flag + RTS + } +} + +#endif /* defined(__EPAGE__) */ +#endif /* defined(__PPAGE__) */ +#endif /* defined(__DPAGE__) */ + +#endif /* USE_SEVERAL_PAGES */ + +/*--------------------------- _SET_PAGE -------------------------------- + Runtime routine to set the right page register. This routine is used if the compiler + does not know the right page register, i.e. if the option -Cp is used for more than + one pageregister or if the runtime option is used for one of the -Cp options. + + Arguments : + - offset part of an address in the Y register + - page part of an address in the B register + + Result : + - page part written into the correct page register. + - the old page register content is destroyed + - all processor registers remains unchanged + --------------------------- _SET_PAGE ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _SET_PAGE(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ; save X register + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + STAB 0,X ; set page register +L_NOPAGE: + PULX ; restore X register + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + STAB PAGE_ADDR ; set page register + RTS + } +#endif /* USE_SEVERAL_PAGES */ +} + +/*--------------------------- _LOAD_FAR_8 -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of an address in the Y register + - page part of an address in the B register + + Result : + - value to be read in the B register + - all other registers remains unchanged + - all page register still contain the same value + --------------------------- _LOAD_FAR_8 ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _LOAD_FAR_8(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ; save X register + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + PSHA ; save A register + LDAA 0,X ; save page register + STAB 0,X ; set page register + LDAB 0,Y ; actual load, overwrites page + STAA 0,X ; restore page register + PULA ; restore A register + PULX ; restore X register + RTS +L_NOPAGE: + LDAB 0,Y ; actual load, overwrites page + PULX ; restore X register + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + PSHA ; save A register + LDAA PAGE_ADDR ; save page register + STAB PAGE_ADDR ; set page register + LDAB 0,Y ; actual load, overwrites page + STAA PAGE_ADDR ; restore page register + PULA ; restore A register + RTS + } +#endif /* USE_SEVERAL_PAGES */ +} + +/*--------------------------- _LOAD_FAR_16 -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of an address in the Y register + - page part of an address in the B register + + Result : + - value to be read in the Y register + - all other registers remains unchanged + - all page register still contain the same value + --------------------------- _LOAD_FAR_16 ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _LOAD_FAR_16(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ; save X register + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + PSHA ; save A register + LDAA 0,X ; save page register + STAB 0,X ; set page register + LDY 0,Y ; actual load, overwrites address + STAA 0,X ; restore page register + PULA ; restore A register + PULX ; restore X register + RTS +L_NOPAGE: + LDY 0,Y ; actual load, overwrites address + PULX ; restore X register + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + PSHA ; save A register + LDAA PAGE_ADDR ; save page register + STAB PAGE_ADDR ; set page register + LDY 0,Y ; actual load, overwrites address + STAA PAGE_ADDR ; restore page register + PULA ; restore A register + RTS + } +#endif /* USE_SEVERAL_PAGES */ +} +/*--------------------------- _LOAD_FAR_24 -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of an address in the Y register + - page part of an address in the B register + + Result : + - value to be read in the Y:B registers + - all other registers remains unchanged + - all page register still contain the same value + --------------------------- _LOAD_FAR_24 ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _LOAD_FAR_24(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ; save X register + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + PSHA ; save A register + LDAA 0,X ; save page register + STAB 0,X ; set page register + LDAB 0,Y ; actual load, overwrites page of address + LDY 1,Y ; actual load, overwrites offset of address + STAA 0,X ; restore page register + PULA ; restore A register + PULX ; restore X register + RTS +L_NOPAGE: + LDAB 0,Y ; actual load, overwrites page of address + LDY 1,Y ; actual load, overwrites offset of address + PULX ; restore X register + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + PSHA ; save A register + LDAA PAGE_ADDR ; save page register + STAB PAGE_ADDR ; set page register + LDAB 0,Y ; actual load, overwrites page of address + LDY 1,Y ; actual load, overwrites offset of address + STAA PAGE_ADDR ; restore page register + PULA ; restore A register + RTS + } +#endif /* USE_SEVERAL_PAGES */ + +} + +/*--------------------------- _LOAD_FAR_32 -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of an address in the Y register + - page part of an address in the B register + + Result : + - low 16 bit of value to be read in the D registers + - high 16 bit of value to be read in the Y registers + - all other registers remains unchanged + - all page register still contain the same value + --------------------------- _LOAD_FAR_32 ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _LOAD_FAR_32(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ; save X register + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + LDAA 0,X ; save page register + PSHA ; put it onto the stack + STAB 0,X ; set page register + LDD 2,Y ; actual load, low word + LDY 0,Y ; actual load, high word + MOVB 1,SP+,0,X ; restore page register + PULX ; restore X register + RTS +L_NOPAGE: + LDD 2,Y ; actual load, low word + LDY 0,Y ; actual load, high word + PULX ; restore X register + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + LDAA PAGE_ADDR ; save page register + PSHA ; put it onto the stack + STAB PAGE_ADDR ; set page register + LDD 2,Y ; actual load, low word + LDY 0,Y ; actual load, high word + MOVB 1,SP+,PAGE_ADDR; restore page register + RTS + } +#endif /* USE_SEVERAL_PAGES */ +} + +/*--------------------------- _STORE_FAR_8 -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of an address in the Y register + - page part of an address in the B register + - value to be stored in the B register + + Result : + - value stored at the address + - all registers remains unchanged + - all page register still contain the same value + --------------------------- _STORE_FAR_8 ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _STORE_FAR_8(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ; save X register + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + PSHB ; save B register + LDAB 0,X ; save page register + MOVB 0,SP, 0,X ; set page register + STAA 0,Y ; store the value passed in A + STAB 0,X ; restore page register + PULB ; restore B register + PULX ; restore X register + RTS +L_NOPAGE: + STAA 0,Y ; store the value passed in A + PULX ; restore X register + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + PSHB ; save A register + LDAB PAGE_ADDR ; save page register + MOVB 0,SP,PAGE_ADDR ; set page register + STAA 0,Y ; store the value passed in A + STAB PAGE_ADDR ; restore page register + PULB ; restore B register + RTS + } +#endif /* USE_SEVERAL_PAGES */ +} + +/*--------------------------- _STORE_FAR_16 -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of an address in the Y register + - page part of an address in the B register + - value to be stored in the X register + + Result : + - value stored at the address + - all registers remains unchanged + - all page register still contain the same value + --------------------------- _STORE_FAR_16 ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _STORE_FAR_16(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ; save X register + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + + PSHA + LDAA 0,X ; save page register + STAB 0,X ; set page register + MOVW 1,SP, 0,Y ; store the value passed in X + STAA 0,X ; restore page register + PULA ; restore A register + PULX ; restore X register + RTS + +L_NOPAGE: + STX 0,Y ; store the value passed in X + PULX ; restore X register + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + PSHA ; save A register + LDAA PAGE_ADDR ; save page register + STAB PAGE_ADDR ; set page register + STX 0,Y ; store the value passed in X + STAA PAGE_ADDR ; restore page register + PULA ; restore A register + RTS + } +#endif /* USE_SEVERAL_PAGES */ +} +/*--------------------------- _STORE_FAR_24 -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of an address in the Y register + - page part of an address in the B register + - value to be stored in the X:A registers (X : low 16 bit, A : high 8 bit) + + Result : + - value stored at the address + - all registers remains unchanged + - all page register still contain the same value + --------------------------- _STORE_FAR_24 ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _STORE_FAR_24(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ; save X register + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + + PSHA + LDAA 0,X ; save page register + STAB 0,X ; set page register + MOVW 1,SP, 1,Y ; store the value passed in X + MOVB 0,SP, 0,Y ; store the value passed in A + STAA 0,X ; restore page register + PULA ; restore A register + PULX ; restore X register + RTS + +L_NOPAGE: + STX 1,Y ; store the value passed in X + STAA 0,Y ; store the value passed in X + PULX ; restore X register + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + PSHA ; save A register + LDAA PAGE_ADDR ; save page register + STAB PAGE_ADDR ; set page register + MOVB 0,SP, 0,Y ; store the value passed in A + STX 1,Y ; store the value passed in X + STAA PAGE_ADDR ; restore page register + PULA ; restore A register + RTS + } +#endif /* USE_SEVERAL_PAGES */ +} +/*--------------------------- _STORE_FAR_32 -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of an address in the Y register + - page part of an address is on the stack at 3,SP (just below the return address) + - value to be stored in the X:D registers (D : low 16 bit, X : high 16 bit) + + Result : + - value stored at the address + - all registers remains unchanged + - the page part is removed from the stack + - all page register still contain the same value + --------------------------- _STORE_FAR_32 ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _STORE_FAR_32(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ; save X register + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + + PSHD + LDAA 0,X ; save page register + MOVB 6,SP, 0,X ; set page register + MOVW 2,SP, 0,Y ; store the value passed in X (high word) + MOVW 0,SP, 2,Y ; store the value passed in D (low word) + STAA 0,X ; restore page register + PULD ; restore A register + BRA done + +L_NOPAGE: + MOVW 0,SP, 0,Y ; store the value passed in X (high word) + STD 2,Y ; store the value passed in D (low word) +done: + PULX ; restore X register + MOVW 0,SP, 1,+SP ; move return address + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + PSHD ; save D register + LDAA PAGE_ADDR ; save page register + LDAB 4,SP ; load page part of address + STAB PAGE_ADDR ; set page register + STX 0,Y ; store the value passed in X + MOVW 0,SP, 2,Y ; store the value passed in D (low word) + STAA PAGE_ADDR ; restore page register + PULD ; restore D register + MOVW 0,SP, 1,+SP ; move return address + RTS + } +#endif /* USE_SEVERAL_PAGES */ +} + +/*--------------------------- _FAR_COPY -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of the source int the X register + - page part of the source in the A register + - offset part of the dest int the Y register + - page part of the dest in the B register + - number of bytes to be copied at 2,SP. The number of bytes is always > 0 + + Result : + - memory area copied + - no registers are saved, i.e. all registers may be destroied + - all page register still contain the same value + + + stack-structure at the loop-label: + 0,SP : destination offset + 2,SP : source page + 3,SP : destination page + 4,SP : source offset + 6,SP : return address + 8,SP : counter, > 0 + --------------------------- _FAR_COPY ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _FAR_COPY(void) { +#if USE_SEVERAL_PAGES + asm { + DEX ; source addr-=1, because loop counter ends at 1 + PSHX ; save source offset + PSHD ; save both pages + DEY ; destination addr-=1, because loop counter ends at 1 + PSHY ; save destination offset + LDX 8,SP ; load counter, assuming counter > 0 + +loop: + LDD 4,SP ; load source offset + LEAY D,X ; calcutate actual source address + LDAB 2,SP ; load source page + __PIC_JSR (_LOAD_FAR_8); load 1 source byte + PSHB ; save value + LDD 0+1,SP ; load destination offset + LEAY D,X ; calcutate acual destination address + PULA ; restore value + LDAB 3,SP ; load destination page + __PIC_JSR (_STORE_FAR_8); store one byte + DEX + BNE loop + LDX 6,SP ; load return address + LEAS 10,SP ; release stack + JMP 0,X ; return + } +#else + asm { + PSHD ; store page registers + TFR X,D + ADDD 4,SP ; calculate source end address + STD 4,SP + PULB ; reload source page + LDAA PAGE_ADDR ; save page register + PSHA +loop: + STAB PAGE_ADDR ; set source page + LDAA 1,X+ ; load value + MOVB 1,SP, PAGE_ADDR ; set destination page + STAA 1,Y+ + CPX 4,SP + BNE loop + + LDAA 2,SP+ ; restore old page value and release stack + STAA PAGE_ADDR ; store it into page register + LDX 4,SP+ ; release stack and load return address + JMP 0,X ; return + } +#endif +} + diff --git a/20080212/Demo/HCS12_CodeWarrior_banked/bin/P&E_ICD.map b/20080212/Demo/HCS12_CodeWarrior_banked/bin/P&E_ICD.map new file mode 100644 index 000000000..ff7f0c498 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_banked/bin/P&E_ICD.map @@ -0,0 +1,3994 @@ + +PROGRAM "E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_banked\bin\P&E_ICD.abs" + +********************************************************************************************* +TARGET SECTION +--------------------------------------------------------------------------------------------- +Processor : Motorola HC12 +Memory Model: BANKED +File Format : ELF\Dwarf 2.0 +Linker : SmartLinker V-5.0.22 Build 4047, Feb 17 2004 + +********************************************************************************************* +FILE SECTION +--------------------------------------------------------------------------------------------- +Start12.c.o Model: BANKED, Lang: ANSI-C +STRING.C.o (ansibi.lib) Model: BANKED, Lang: ANSI-C +rtshc12.c.o (ansibi.lib) Model: BANKED, Lang: ANSI-C +Cpu.C.o Model: BANKED, Lang: ANSI-C +IO_Map.C.o Model: BANKED, Lang: ANSI-C +Vectors.c.o Model: BANKED, Lang: ANSI-C +RTOSDemo.C.o Model: BANKED, Lang: ANSI-C +main.c.o Model: BANKED, Lang: ANSI-C +ParTest.c.o Model: BANKED, Lang: ANSI-C +serial.c.o Model: BANKED, Lang: ANSI-C +tasks.c.o Model: BANKED, Lang: ANSI-C +queue.c.o Model: BANKED, Lang: ANSI-C +list.c.o Model: BANKED, Lang: ANSI-C +heap_2.c.o Model: BANKED, Lang: ANSI-C +flash.c.o Model: BANKED, Lang: ANSI-C +dynamic.c.o Model: BANKED, Lang: ANSI-C +PollQ.c.o Model: BANKED, Lang: ANSI-C +TickTimer.C.o Model: BANKED, Lang: ANSI-C +Byte1.C.o Model: BANKED, Lang: ANSI-C +PE_Timer.C.o Model: BANKED, Lang: ANSI-C +comtest.c.o Model: BANKED, Lang: ANSI-C +COM0.C.o Model: BANKED, Lang: ANSI-C +port.c.o Model: BANKED, Lang: ANSI-C +integer.c.o Model: BANKED, Lang: ANSI-C +BlockQ.c.o Model: BANKED, Lang: ANSI-C +death.c.o Model: BANKED, Lang: ANSI-C + +********************************************************************************************* +STARTUP SECTION +--------------------------------------------------------------------------------------------- +Entry point: 0xC000 (_EntryPoint) +_startupData is allocated at 0xC07C and uses 24 Bytes +extern struct _tagStartup { + unsigned flags 0 + _PFunc main 0x30809A (main) + long stackOffset 0x3988 + unsigned nofZeroOut 1 + _Range pZeroOut 0x1000 10505 + _Copy *toCopyDownBeg 0xC3B5 + int nofLibInits 0 + _LibInit *libInits 0xC098 + int nofInitBodies 0 + _Cpp *initBodies 0xC09A + int nofFiniBodies 0 + _Cpp *finiBodies 0xC09A +} _startupData; + +********************************************************************************************* +SECTION-ALLOCATION SECTION +Section Name Size Type From To Segment +--------------------------------------------------------------------------------------------- +.data 1 R/W 0x1000 0x1000 RAM +.text 587 R 0x308000 0x30824A ROM_PAGE30 +.init 124 R 0xC000 0xC07B ROM_C000 +.startData 30 R 0xC07C 0xC099 ROM_C000 +.rodata1 183 R 0xC09A 0xC150 ROM_C000 +NON_BANKED 612 R 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0x398000 0x398196 ROM_PAGE39 +ROM_PAGE3A_533 588 R 0x3A8000 0x3A824B ROM_PAGE3A +ROM_PAGE3B_534 292 R 0x3B8000 0x3B8123 ROM_PAGE3B + +Summary of section sizes per section type: +READ_ONLY (R): 1DD4 (dec: 7636) +READ_WRITE (R/W): 2989 (dec: 10633) +NO_INIT (N/I): 241 (dec: 577) + +********************************************************************************************* +VECTOR-ALLOCATION SECTION + Address InitValue InitFunction +--------------------------------------------------------------------------------------------- + +********************************************************************************************* +OBJECT-ALLOCATION SECTION + Name Module Addr hSize dSize Ref Section RLIB +--------------------------------------------------------------------------------------------- +MODULE: -- Start12.c.o -- +- PROCEDURES: + Init 308000 29 41 2 .text + _Startup C151 12 18 1 NON_BANKED +- VARIABLES: + _startupData C07C 18 24 6 .startData +MODULE: -- STRING.C.o (ansibi.lib) -- +- PROCEDURES: + memcpy 308029 26 38 8 .text + memset 30804F 1E 30 2 .text + strncpy 30806D 2D 45 2 .text +- VARIABLES: +MODULE: -- rtshc12.c.o (ansibi.lib) -- +- PROCEDURES: + _LCMP C163 19 25 2 NON_BANKED + _LCMP_P C17C 15 21 3 NON_BANKED + _LNEG C191 D 13 2 NON_BANKED + _LINC C19E 5 5 4 NON_BANKED + _LMUL C1A3 27 39 1 NON_BANKED + _lDivMod C1CA E3 227 3 NON_BANKED + _LDIVU C2AD E 14 1 NON_BANKED + _NEG_P C2BB F 15 4 NON_BANKED + _LDIVS C2CA 35 53 2 NON_BANKED +- VARIABLES: +MODULE: -- Cpu.C.o -- +- PROCEDURES: + _EntryPoint C000 2E 46 1 .init + PE_low_level_init C02E 4E 78 2 .init + Cpu_Interrupt C2FF 1 1 60 NON_BANKED +- VARIABLES: +MODULE: -- IO_Map.C.o -- +- PROCEDURES: +- VARIABLES: + _ARMCOP 3F 1 1 0 .abs_section_3f + _ATD0DIEN 8D 1 1 0 .abs_section_8d + _ATD0STAT0 86 1 1 0 .abs_section_86 + _ATD0STAT1 8B 1 1 0 .abs_section_8b + _ATD1DIEN 12D 1 1 0 .abs_section_12d + _ATD1STAT0 126 1 1 0 .abs_section_126 + _ATD1STAT1 12B 1 1 0 .abs_section_12b + _BDMCCR FF06 1 1 0 .abs_section_ff06 + _BDMINR FF07 1 1 0 .abs_section_ff07 + _BDMSTS FF01 1 1 0 .abs_section_ff01 + _BKP0H 2B 1 1 0 .abs_section_2b + _BKP0L 2C 1 1 0 .abs_section_2c + _BKP0X 2A 1 1 0 .abs_section_2a + _BKP1H 2E 1 1 0 .abs_section_2e + _BKP1L 2F 1 1 0 .abs_section_2f + _BKP1X 2D 1 1 0 .abs_section_2d + _BKPCT0 28 1 1 0 .abs_section_28 + _BKPCT1 29 1 1 0 .abs_section_29 + _CAN0BTR0 142 1 1 0 .abs_section_142 + _CAN0BTR1 143 1 1 0 .abs_section_143 + _CAN0CTL0 140 1 1 0 .abs_section_140 + _CAN0CTL1 141 1 1 0 .abs_section_141 + _CAN0IDAC 14B 1 1 0 .abs_section_14b + _CAN0IDAR0 150 1 1 0 .abs_section_150 + _CAN0IDAR1 151 1 1 0 .abs_section_151 + _CAN0IDAR2 152 1 1 0 .abs_section_152 + _CAN0IDAR3 153 1 1 0 .abs_section_153 + _CAN0IDAR4 158 1 1 0 .abs_section_158 + _CAN0IDAR5 159 1 1 0 .abs_section_159 + _CAN0IDAR6 15A 1 1 0 .abs_section_15a + _CAN0IDAR7 15B 1 1 0 .abs_section_15b + _CAN0IDMR0 154 1 1 0 .abs_section_154 + _CAN0IDMR1 155 1 1 0 .abs_section_155 + _CAN0IDMR2 156 1 1 0 .abs_section_156 + _CAN0IDMR3 157 1 1 0 .abs_section_157 + _CAN0IDMR4 15C 1 1 0 .abs_section_15c + _CAN0IDMR5 15D 1 1 0 .abs_section_15d + _CAN0IDMR6 15E 1 1 0 .abs_section_15e + _CAN0IDMR7 15F 1 1 0 .abs_section_15f + _CAN0RFLG 144 1 1 0 .abs_section_144 + _CAN0RIER 145 1 1 0 .abs_section_145 + _CAN0RXDLR 16C 1 1 0 .abs_section_16c + _CAN0RXDSR0 164 1 1 0 .abs_section_164 + _CAN0RXDSR1 165 1 1 0 .abs_section_165 + _CAN0RXDSR2 166 1 1 0 .abs_section_166 + _CAN0RXDSR3 167 1 1 0 .abs_section_167 + _CAN0RXDSR4 168 1 1 0 .abs_section_168 + _CAN0RXDSR5 169 1 1 0 .abs_section_169 + _CAN0RXDSR6 16A 1 1 0 .abs_section_16a + _CAN0RXDSR7 16B 1 1 0 .abs_section_16b + _CAN0RXERR 14E 1 1 0 .abs_section_14e + _CAN0RXIDR0 160 1 1 0 .abs_section_160 + _CAN0RXIDR1 161 1 1 0 .abs_section_161 + _CAN0RXIDR2 162 1 1 0 .abs_section_162 + _CAN0RXIDR3 163 1 1 0 .abs_section_163 + _CAN0TAAK 149 1 1 0 .abs_section_149 + _CAN0TARQ 148 1 1 0 .abs_section_148 + _CAN0TBSEL 14A 1 1 0 .abs_section_14a + _CAN0TFLG 146 1 1 0 .abs_section_146 + _CAN0TIER 147 1 1 0 .abs_section_147 + _CAN0TXDLR 17C 1 1 0 .abs_section_17c + _CAN0TXDSR0 174 1 1 0 .abs_section_174 + _CAN0TXDSR1 175 1 1 0 .abs_section_175 + _CAN0TXDSR2 176 1 1 0 .abs_section_176 + _CAN0TXDSR3 177 1 1 0 .abs_section_177 + _CAN0TXDSR4 178 1 1 0 .abs_section_178 + _CAN0TXDSR5 179 1 1 0 .abs_section_179 + _CAN0TXDSR6 17A 1 1 0 .abs_section_17a + _CAN0TXDSR7 17B 1 1 0 .abs_section_17b + _CAN0TXERR 14F 1 1 0 .abs_section_14f + _CAN0TXIDR0 170 1 1 0 .abs_section_170 + _CAN0TXIDR1 171 1 1 0 .abs_section_171 + _CAN0TXIDR2 172 1 1 0 .abs_section_172 + _CAN0TXIDR3 173 1 1 0 .abs_section_173 + _CAN0TXTBPR 17F 1 1 0 .abs_section_17f + _CAN1BTR0 182 1 1 0 .abs_section_182 + _CAN1BTR1 183 1 1 0 .abs_section_183 + _CAN1CTL0 180 1 1 0 .abs_section_180 + _CAN1CTL1 181 1 1 0 .abs_section_181 + _CAN1IDAC 18B 1 1 0 .abs_section_18b + _CAN1IDAR0 190 1 1 0 .abs_section_190 + _CAN1IDAR1 191 1 1 0 .abs_section_191 + _CAN1IDAR2 192 1 1 0 .abs_section_192 + _CAN1IDAR3 193 1 1 0 .abs_section_193 + _CAN1IDAR4 198 1 1 0 .abs_section_198 + _CAN1IDAR5 199 1 1 0 .abs_section_199 + _CAN1IDAR6 19A 1 1 0 .abs_section_19a + _CAN1IDAR7 19B 1 1 0 .abs_section_19b + _CAN1IDMR0 194 1 1 0 .abs_section_194 + _CAN1IDMR1 195 1 1 0 .abs_section_195 + _CAN1IDMR2 196 1 1 0 .abs_section_196 + _CAN1IDMR3 197 1 1 0 .abs_section_197 + _CAN1IDMR4 19C 1 1 0 .abs_section_19c + _CAN1IDMR5 19D 1 1 0 .abs_section_19d + _CAN1IDMR6 19E 1 1 0 .abs_section_19e + _CAN1IDMR7 19F 1 1 0 .abs_section_19f + _CAN1RFLG 184 1 1 0 .abs_section_184 + _CAN1RIER 185 1 1 0 .abs_section_185 + _CAN1RXDLR 1AC 1 1 0 .abs_section_1ac + _CAN1RXDSR0 1A4 1 1 0 .abs_section_1a4 + _CAN1RXDSR1 1A5 1 1 0 .abs_section_1a5 + _CAN1RXDSR2 1A6 1 1 0 .abs_section_1a6 + _CAN1RXDSR3 1A7 1 1 0 .abs_section_1a7 + _CAN1RXDSR4 1A8 1 1 0 .abs_section_1a8 + _CAN1RXDSR5 1A9 1 1 0 .abs_section_1a9 + _CAN1RXDSR6 1AA 1 1 0 .abs_section_1aa + _CAN1RXDSR7 1AB 1 1 0 .abs_section_1ab + _CAN1RXERR 18E 1 1 0 .abs_section_18e + _CAN1RXIDR0 1A0 1 1 0 .abs_section_1a0 + _CAN1RXIDR1 1A1 1 1 0 .abs_section_1a1 + _CAN1RXIDR2 1A2 1 1 0 .abs_section_1a2 + _CAN1RXIDR3 1A3 1 1 0 .abs_section_1a3 + _CAN1TAAK 189 1 1 0 .abs_section_189 + _CAN1TARQ 188 1 1 0 .abs_section_188 + _CAN1TBSEL 18A 1 1 0 .abs_section_18a + _CAN1TFLG 186 1 1 0 .abs_section_186 + _CAN1TIER 187 1 1 0 .abs_section_187 + _CAN1TXDLR 1BC 1 1 0 .abs_section_1bc + _CAN1TXDSR0 1B4 1 1 0 .abs_section_1b4 + _CAN1TXDSR1 1B5 1 1 0 .abs_section_1b5 + _CAN1TXDSR2 1B6 1 1 0 .abs_section_1b6 + _CAN1TXDSR3 1B7 1 1 0 .abs_section_1b7 + _CAN1TXDSR4 1B8 1 1 0 .abs_section_1b8 + _CAN1TXDSR5 1B9 1 1 0 .abs_section_1b9 + _CAN1TXDSR6 1BA 1 1 0 .abs_section_1ba + _CAN1TXDSR7 1BB 1 1 0 .abs_section_1bb + _CAN1TXERR 18F 1 1 0 .abs_section_18f + _CAN1TXIDR0 1B0 1 1 0 .abs_section_1b0 + _CAN1TXIDR1 1B1 1 1 0 .abs_section_1b1 + _CAN1TXIDR2 1B2 1 1 0 .abs_section_1b2 + _CAN1TXIDR3 1B3 1 1 0 .abs_section_1b3 + _CAN1TXTBPR 1BF 1 1 0 .abs_section_1bf + _CAN2BTR0 1C2 1 1 0 .abs_section_1c2 + _CAN2BTR1 1C3 1 1 0 .abs_section_1c3 + _CAN2CTL0 1C0 1 1 0 .abs_section_1c0 + _CAN2CTL1 1C1 1 1 0 .abs_section_1c1 + _CAN2IDAC 1CB 1 1 0 .abs_section_1cb + _CAN2IDAR0 1D0 1 1 0 .abs_section_1d0 + _CAN2IDAR1 1D1 1 1 0 .abs_section_1d1 + _CAN2IDAR2 1D2 1 1 0 .abs_section_1d2 + _CAN2IDAR3 1D3 1 1 0 .abs_section_1d3 + _CAN2IDAR4 1D8 1 1 0 .abs_section_1d8 + _CAN2IDAR5 1D9 1 1 0 .abs_section_1d9 + _CAN2IDAR6 1DA 1 1 0 .abs_section_1da + _CAN2IDAR7 1DB 1 1 0 .abs_section_1db + _CAN2IDMR0 1D4 1 1 0 .abs_section_1d4 + _CAN2IDMR1 1D5 1 1 0 .abs_section_1d5 + _CAN2IDMR2 1D6 1 1 0 .abs_section_1d6 + _CAN2IDMR3 1D7 1 1 0 .abs_section_1d7 + _CAN2IDMR4 1DC 1 1 0 .abs_section_1dc + _CAN2IDMR5 1DD 1 1 0 .abs_section_1dd + _CAN2IDMR6 1DE 1 1 0 .abs_section_1de + _CAN2IDMR7 1DF 1 1 0 .abs_section_1df + _CAN2RFLG 1C4 1 1 0 .abs_section_1c4 + _CAN2RIER 1C5 1 1 0 .abs_section_1c5 + _CAN2RXDLR 1EC 1 1 0 .abs_section_1ec + _CAN2RXDSR0 1E4 1 1 0 .abs_section_1e4 + _CAN2RXDSR1 1E5 1 1 0 .abs_section_1e5 + _CAN2RXDSR2 1E6 1 1 0 .abs_section_1e6 + _CAN2RXDSR3 1E7 1 1 0 .abs_section_1e7 + _CAN2RXDSR4 1E8 1 1 0 .abs_section_1e8 + _CAN2RXDSR5 1E9 1 1 0 .abs_section_1e9 + _CAN2RXDSR6 1EA 1 1 0 .abs_section_1ea + _CAN2RXDSR7 1EB 1 1 0 .abs_section_1eb + _CAN2RXERR 1CE 1 1 0 .abs_section_1ce + _CAN2RXIDR0 1E0 1 1 0 .abs_section_1e0 + _CAN2RXIDR1 1E1 1 1 0 .abs_section_1e1 + _CAN2RXIDR2 1E2 1 1 0 .abs_section_1e2 + _CAN2RXIDR3 1E3 1 1 0 .abs_section_1e3 + _CAN2TAAK 1C9 1 1 0 .abs_section_1c9 + _CAN2TARQ 1C8 1 1 0 .abs_section_1c8 + _CAN2TBSEL 1CA 1 1 0 .abs_section_1ca + _CAN2TFLG 1C6 1 1 0 .abs_section_1c6 + _CAN2TIER 1C7 1 1 0 .abs_section_1c7 + _CAN2TXDLR 1FC 1 1 0 .abs_section_1fc + _CAN2TXDSR0 1F4 1 1 0 .abs_section_1f4 + _CAN2TXDSR1 1F5 1 1 0 .abs_section_1f5 + _CAN2TXDSR2 1F6 1 1 0 .abs_section_1f6 + _CAN2TXDSR3 1F7 1 1 0 .abs_section_1f7 + _CAN2TXDSR4 1F8 1 1 0 .abs_section_1f8 + _CAN2TXDSR5 1F9 1 1 0 .abs_section_1f9 + _CAN2TXDSR6 1FA 1 1 0 .abs_section_1fa + _CAN2TXDSR7 1FB 1 1 0 .abs_section_1fb + _CAN2TXERR 1CF 1 1 0 .abs_section_1cf + _CAN2TXIDR0 1F0 1 1 0 .abs_section_1f0 + _CAN2TXIDR1 1F1 1 1 0 .abs_section_1f1 + _CAN2TXIDR2 1F2 1 1 0 .abs_section_1f2 + _CAN2TXIDR3 1F3 1 1 0 .abs_section_1f3 + _CAN2TXTBPR 1FF 1 1 0 .abs_section_1ff + _CAN3BTR0 202 1 1 0 .abs_section_202 + _CAN3BTR1 203 1 1 0 .abs_section_203 + _CAN3CTL0 200 1 1 0 .abs_section_200 + _CAN3CTL1 201 1 1 0 .abs_section_201 + _CAN3IDAC 20B 1 1 0 .abs_section_20b + _CAN3IDAR0 210 1 1 0 .abs_section_210 + _CAN3IDAR1 211 1 1 0 .abs_section_211 + _CAN3IDAR2 212 1 1 0 .abs_section_212 + _CAN3IDAR3 213 1 1 0 .abs_section_213 + _CAN3IDAR4 218 1 1 0 .abs_section_218 + _CAN3IDAR5 219 1 1 0 .abs_section_219 + _CAN3IDAR6 21A 1 1 0 .abs_section_21a + _CAN3IDAR7 21B 1 1 0 .abs_section_21b + _CAN3IDMR0 214 1 1 0 .abs_section_214 + _CAN3IDMR1 215 1 1 0 .abs_section_215 + _CAN3IDMR2 216 1 1 0 .abs_section_216 + _CAN3IDMR3 217 1 1 0 .abs_section_217 + _CAN3IDMR4 21C 1 1 0 .abs_section_21c + _CAN3IDMR5 21D 1 1 0 .abs_section_21d + _CAN3IDMR6 21E 1 1 0 .abs_section_21e + _CAN3IDMR7 21F 1 1 0 .abs_section_21f + _CAN3RFLG 204 1 1 0 .abs_section_204 + _CAN3RIER 205 1 1 0 .abs_section_205 + _CAN3RXDLR 22C 1 1 0 .abs_section_22c + _CAN3RXDSR0 224 1 1 0 .abs_section_224 + _CAN3RXDSR1 225 1 1 0 .abs_section_225 + _CAN3RXDSR2 226 1 1 0 .abs_section_226 + _CAN3RXDSR3 227 1 1 0 .abs_section_227 + _CAN3RXDSR4 228 1 1 0 .abs_section_228 + _CAN3RXDSR5 229 1 1 0 .abs_section_229 + _CAN3RXDSR6 22A 1 1 0 .abs_section_22a + _CAN3RXDSR7 22B 1 1 0 .abs_section_22b + _CAN3RXERR 20E 1 1 0 .abs_section_20e + _CAN3RXIDR0 220 1 1 0 .abs_section_220 + _CAN3RXIDR1 221 1 1 0 .abs_section_221 + _CAN3RXIDR2 222 1 1 0 .abs_section_222 + _CAN3RXIDR3 223 1 1 0 .abs_section_223 + _CAN3TAAK 209 1 1 0 .abs_section_209 + _CAN3TARQ 208 1 1 0 .abs_section_208 + _CAN3TBSEL 20A 1 1 0 .abs_section_20a + _CAN3TFLG 206 1 1 0 .abs_section_206 + _CAN3TIER 207 1 1 0 .abs_section_207 + _CAN3TXDLR 23C 1 1 0 .abs_section_23c + _CAN3TXDSR0 234 1 1 0 .abs_section_234 + _CAN3TXDSR1 235 1 1 0 .abs_section_235 + _CAN3TXDSR2 236 1 1 0 .abs_section_236 + _CAN3TXDSR3 237 1 1 0 .abs_section_237 + _CAN3TXDSR4 238 1 1 0 .abs_section_238 + _CAN3TXDSR5 239 1 1 0 .abs_section_239 + _CAN3TXDSR6 23A 1 1 0 .abs_section_23a + _CAN3TXDSR7 23B 1 1 0 .abs_section_23b + _CAN3TXERR 20F 1 1 0 .abs_section_20f + _CAN3TXIDR0 230 1 1 0 .abs_section_230 + _CAN3TXIDR1 231 1 1 0 .abs_section_231 + _CAN3TXIDR2 232 1 1 0 .abs_section_232 + _CAN3TXIDR3 233 1 1 0 .abs_section_233 + _CAN3TXTBPR 23F 1 1 0 .abs_section_23f + _CAN4BTR0 282 1 1 0 .abs_section_282 + _CAN4BTR1 283 1 1 0 .abs_section_283 + _CAN4CTL0 280 1 1 0 .abs_section_280 + _CAN4CTL1 281 1 1 0 .abs_section_281 + _CAN4IDAC 28B 1 1 0 .abs_section_28b + _CAN4IDAR0 290 1 1 0 .abs_section_290 + _CAN4IDAR1 291 1 1 0 .abs_section_291 + _CAN4IDAR2 292 1 1 0 .abs_section_292 + _CAN4IDAR3 293 1 1 0 .abs_section_293 + _CAN4IDAR4 298 1 1 0 .abs_section_298 + _CAN4IDAR5 299 1 1 0 .abs_section_299 + _CAN4IDAR6 29A 1 1 0 .abs_section_29a + _CAN4IDAR7 29B 1 1 0 .abs_section_29b + _CAN4IDMR0 294 1 1 0 .abs_section_294 + _CAN4IDMR1 295 1 1 0 .abs_section_295 + _CAN4IDMR2 296 1 1 0 .abs_section_296 + _CAN4IDMR3 297 1 1 0 .abs_section_297 + _CAN4IDMR4 29C 1 1 0 .abs_section_29c + _CAN4IDMR5 29D 1 1 0 .abs_section_29d + _CAN4IDMR6 29E 1 1 0 .abs_section_29e + _CAN4IDMR7 29F 1 1 0 .abs_section_29f + _CAN4RFLG 284 1 1 0 .abs_section_284 + _CAN4RIER 285 1 1 0 .abs_section_285 + _CAN4RXDLR 2AC 1 1 0 .abs_section_2ac + _CAN4RXDSR0 2A4 1 1 0 .abs_section_2a4 + _CAN4RXDSR1 2A5 1 1 0 .abs_section_2a5 + _CAN4RXDSR2 2A6 1 1 0 .abs_section_2a6 + _CAN4RXDSR3 2A7 1 1 0 .abs_section_2a7 + _CAN4RXDSR4 2A8 1 1 0 .abs_section_2a8 + _CAN4RXDSR5 2A9 1 1 0 .abs_section_2a9 + _CAN4RXDSR6 2AA 1 1 0 .abs_section_2aa + _CAN4RXDSR7 2AB 1 1 0 .abs_section_2ab + _CAN4RXERR 28E 1 1 0 .abs_section_28e + _CAN4RXIDR0 2A0 1 1 0 .abs_section_2a0 + _CAN4RXIDR1 2A1 1 1 0 .abs_section_2a1 + _CAN4RXIDR2 2A2 1 1 0 .abs_section_2a2 + _CAN4RXIDR3 2A3 1 1 0 .abs_section_2a3 + _CAN4TAAK 289 1 1 0 .abs_section_289 + _CAN4TARQ 288 1 1 0 .abs_section_288 + _CAN4TBSEL 28A 1 1 0 .abs_section_28a + _CAN4TFLG 286 1 1 0 .abs_section_286 + _CAN4TIER 287 1 1 0 .abs_section_287 + _CAN4TXDLR 2BC 1 1 0 .abs_section_2bc + _CAN4TXDSR0 2B4 1 1 0 .abs_section_2b4 + _CAN4TXDSR1 2B5 1 1 0 .abs_section_2b5 + _CAN4TXDSR2 2B6 1 1 0 .abs_section_2b6 + _CAN4TXDSR3 2B7 1 1 0 .abs_section_2b7 + _CAN4TXDSR4 2B8 1 1 0 .abs_section_2b8 + _CAN4TXDSR5 2B9 1 1 0 .abs_section_2b9 + _CAN4TXDSR6 2BA 1 1 0 .abs_section_2ba + _CAN4TXDSR7 2BB 1 1 0 .abs_section_2bb + _CAN4TXERR 28F 1 1 0 .abs_section_28f + _CAN4TXIDR0 2B0 1 1 0 .abs_section_2b0 + _CAN4TXIDR1 2B1 1 1 0 .abs_section_2b1 + _CAN4TXIDR2 2B2 1 1 0 .abs_section_2b2 + _CAN4TXIDR3 2B3 1 1 0 .abs_section_2b3 + _CAN4TXTBPR 2BF 1 1 0 .abs_section_2bf + _CFORC 41 1 1 0 .abs_section_41 + _CLKSEL 39 1 1 3 .abs_section_39 + _COPCTL 3C 1 1 0 .abs_section_3c + _CRGFLG 37 1 1 1 .abs_section_37 + _CRGINT 38 1 1 0 .abs_section_38 + _CTCTL 3E 1 1 0 .abs_section_3e + _CTFLG 36 1 1 0 .abs_section_36 + _DDRE 9 1 1 0 .abs_section_9 + _DDRH 262 1 1 0 .abs_section_262 + _DDRJ 26A 1 1 0 .abs_section_26a + _DDRK 33 1 1 0 .abs_section_33 + _DDRM 252 1 1 0 .abs_section_252 + _DDRP 25A 1 1 0 .abs_section_25a + _DDRS 24A 1 1 2 .abs_section_24a + _DDRT 242 1 1 0 .abs_section_242 + _DLCBARD EC 1 1 0 .abs_section_ec + _DLCBCR1 E8 1 1 0 .abs_section_e8 + _DLCBCR2 EA 1 1 0 .abs_section_ea + _DLCBDR EB 1 1 0 .abs_section_eb + _DLCBRSR ED 1 1 0 .abs_section_ed + _DLCBSVR E9 1 1 0 .abs_section_e9 + _DLCSCR EE 1 1 0 .abs_section_ee + _DLYCT 69 1 1 0 .abs_section_69 + _EBICTL E 1 1 0 .abs_section_e + _ECLKDIV 110 1 1 0 .abs_section_110 + _ECMD 116 1 1 0 .abs_section_116 + _ECNFG 113 1 1 0 .abs_section_113 + _EPROT 114 1 1 0 .abs_section_114 + _ESTAT 115 1 1 0 .abs_section_115 + _FCLKDIV 100 1 1 0 .abs_section_100 + _FCMD 106 1 1 0 .abs_section_106 + _FCNFG 103 1 1 0 .abs_section_103 + _FORBYP 3D 1 1 0 .abs_section_3d + _FPROT 104 1 1 0 .abs_section_104 + _FSEC 101 1 1 0 .abs_section_101 + _FSTAT 105 1 1 0 .abs_section_105 + _HPRIO 1F 1 1 0 .abs_section_1f + _IBAD E0 1 1 0 .abs_section_e0 + _IBCR E2 1 1 0 .abs_section_e2 + _IBDR E4 1 1 0 .abs_section_e4 + _IBFD E1 1 1 0 .abs_section_e1 + _IBSR E3 1 1 0 .abs_section_e3 + _ICOVW 6A 1 1 0 .abs_section_6a + _ICPAR 68 1 1 0 .abs_section_68 + _ICSYS 6B 1 1 1 .abs_section_6b + _INITEE 12 1 1 1 .abs_section_12 + _INITRG 11 1 1 0 .abs_section_11 + _INITRM 10 1 1 1 .abs_section_10 + _INTCR 1E 1 1 1 .abs_section_1e + _ITCR 15 1 1 0 .abs_section_15 + _ITEST 16 1 1 0 .abs_section_16 + _MCCTL 66 1 1 1 .abs_section_66 + _MCFLG 67 1 1 0 .abs_section_67 + _MEMSIZ0 1C 1 1 0 .abs_section_1c + _MEMSIZ1 1D 1 1 0 .abs_section_1d + _MISC 13 1 1 1 .abs_section_13 + _MODE B 1 1 0 .abs_section_b + _MODRR 257 1 1 0 .abs_section_257 + _MTST0 14 1 1 0 .abs_section_14 + _MTST1 17 1 1 0 .abs_section_17 + _OC7D 43 1 1 0 .abs_section_43 + _OC7M 42 1 1 0 .abs_section_42 + _PACTL 60 1 1 0 .abs_section_60 + _PAFLG 61 1 1 0 .abs_section_61 + _PARTIDH 1A 1 1 0 .abs_section_1a + _PARTIDL 1B 1 1 0 .abs_section_1b + _PBCTL 70 1 1 0 .abs_section_70 + _PBFLG 71 1 1 0 .abs_section_71 + _PEAR A 1 1 0 .abs_section_a + _PERH 264 1 1 0 .abs_section_264 + _PERJ 26C 1 1 0 .abs_section_26c + _PERM 254 1 1 0 .abs_section_254 + _PERP 25C 1 1 0 .abs_section_25c + _PERS 24C 1 1 0 .abs_section_24c + _PERT 244 1 1 0 .abs_section_244 + _PIEH 266 1 1 0 .abs_section_266 + _PIEJ 26E 1 1 0 .abs_section_26e + _PIEP 25E 1 1 0 .abs_section_25e + _PIFH 267 1 1 0 .abs_section_267 + _PIFJ 26F 1 1 0 .abs_section_26f + _PIFP 25F 1 1 0 .abs_section_25f + _PLLCTL 3A 1 1 3 .abs_section_3a + _PORTAD0 8F 1 1 0 .abs_section_8f + _PORTAD1 12F 1 1 0 .abs_section_12f + _PORTE 8 1 1 0 .abs_section_8 + _PORTK 32 1 1 0 .abs_section_32 + _PPAGE 30 1 1 0 .abs_section_30 + _PPSH 265 1 1 0 .abs_section_265 + _PPSJ 26D 1 1 0 .abs_section_26d + _PPSM 255 1 1 0 .abs_section_255 + _PPSP 25D 1 1 0 .abs_section_25d + _PPSS 24D 1 1 0 .abs_section_24d + _PPST 245 1 1 0 .abs_section_245 + _PTH 260 1 1 0 .abs_section_260 + _PTIH 261 1 1 0 .abs_section_261 + _PTIJ 269 1 1 0 .abs_section_269 + _PTIM 251 1 1 0 .abs_section_251 + _PTIP 259 1 1 0 .abs_section_259 + _PTIS 249 1 1 0 .abs_section_249 + _PTIT 241 1 1 0 .abs_section_241 + _PTJ 268 1 1 0 .abs_section_268 + _PTM 250 1 1 0 .abs_section_250 + _PTP 258 1 1 0 .abs_section_258 + _PTS 248 1 1 1 .abs_section_248 + _PTT 240 1 1 0 .abs_section_240 + _PUCR C 1 1 0 .abs_section_c + _PWMCAE A4 1 1 0 .abs_section_a4 + _PWMCLK A2 1 1 0 .abs_section_a2 + _PWMCTL A5 1 1 1 .abs_section_a5 + _PWME A0 1 1 0 .abs_section_a0 + _PWMPOL A1 1 1 0 .abs_section_a1 + _PWMPRCLK A3 1 1 0 .abs_section_a3 + _PWMSCLA A8 1 1 0 .abs_section_a8 + _PWMSCLB A9 1 1 0 .abs_section_a9 + _PWMSDN C4 1 1 1 .abs_section_c4 + _RDRH 263 1 1 0 .abs_section_263 + _RDRIV D 1 1 0 .abs_section_d + _RDRJ 26B 1 1 0 .abs_section_26b + _RDRM 253 1 1 0 .abs_section_253 + _RDRP 25B 1 1 0 .abs_section_25b + _RDRS 24B 1 1 0 .abs_section_24b + _RDRT 243 1 1 0 .abs_section_243 + _REFDV 35 1 1 1 .abs_section_35 + _RTICTL 3B 1 1 0 .abs_section_3b + _SCI0CR1 CA 1 1 1 .abs_section_ca + _SCI0CR2 CB 1 1 7 .abs_section_cb + _SCI0DRH CE 1 1 0 .abs_section_ce + _SCI0DRL CF 1 1 3 .abs_section_cf + _SCI0SR1 CC 1 1 2 .abs_section_cc + _SCI0SR2 CD 1 1 1 .abs_section_cd + _SCI1CR1 D2 1 1 0 .abs_section_d2 + _SCI1CR2 D3 1 1 0 .abs_section_d3 + _SCI1DRH D6 1 1 0 .abs_section_d6 + _SCI1DRL D7 1 1 0 .abs_section_d7 + _SCI1SR1 D4 1 1 0 .abs_section_d4 + _SCI1SR2 D5 1 1 0 .abs_section_d5 + _SPI0BR DA 1 1 0 .abs_section_da + _SPI0CR1 D8 1 1 0 .abs_section_d8 + _SPI0CR2 D9 1 1 0 .abs_section_d9 + _SPI0DR DD 1 1 0 .abs_section_dd + _SPI0SR DB 1 1 0 .abs_section_db + _SPI1BR F2 1 1 0 .abs_section_f2 + _SPI1CR1 F0 1 1 0 .abs_section_f0 + _SPI1CR2 F1 1 1 0 .abs_section_f1 + _SPI1DR F5 1 1 0 .abs_section_f5 + _SPI1SR F3 1 1 0 .abs_section_f3 + _SPI2BR FA 1 1 0 .abs_section_fa + _SPI2CR1 F8 1 1 0 .abs_section_f8 + _SPI2CR2 F9 1 1 0 .abs_section_f9 + _SPI2DR FD 1 1 0 .abs_section_fd + _SPI2SR FB 1 1 0 .abs_section_fb + _SYNR 34 1 1 1 .abs_section_34 + _TCTL1 48 1 1 1 .abs_section_48 + _TCTL2 49 1 1 1 .abs_section_49 + _TCTL3 4A 1 1 0 .abs_section_4a + _TCTL4 4B 1 1 0 .abs_section_4b + _TFLG1 4E 1 1 3 .abs_section_4e + _TFLG2 4F 1 1 0 .abs_section_4f + _TIE 4C 1 1 3 .abs_section_4c + _TIMTST 6D 1 1 0 .abs_section_6d + _TIOS 40 1 1 1 .abs_section_40 + _TSCR1 46 1 1 3 .abs_section_46 + _TSCR2 4D 1 1 5 .abs_section_4d + _TTOV 47 1 1 1 .abs_section_47 + _WOMM 256 1 1 0 .abs_section_256 + _WOMS 24E 1 1 0 .abs_section_24e + _ATD0CTL23 82 2 2 0 .abs_section_82 + _ATD0CTL45 84 2 2 0 .abs_section_84 + _ATD0DR0 90 2 2 0 .abs_section_90 + _ATD0DR1 92 2 2 0 .abs_section_92 + _ATD0DR2 94 2 2 0 .abs_section_94 + _ATD0DR3 96 2 2 0 .abs_section_96 + _ATD0DR4 98 2 2 0 .abs_section_98 + _ATD0DR5 9A 2 2 0 .abs_section_9a + _ATD0DR6 9C 2 2 0 .abs_section_9c + _ATD0DR7 9E 2 2 0 .abs_section_9e + _ATD1CTL23 122 2 2 0 .abs_section_122 + _ATD1CTL45 124 2 2 0 .abs_section_124 + _ATD1DR0 130 2 2 0 .abs_section_130 + _ATD1DR1 132 2 2 0 .abs_section_132 + _ATD1DR2 134 2 2 0 .abs_section_134 + _ATD1DR3 136 2 2 0 .abs_section_136 + _ATD1DR4 138 2 2 0 .abs_section_138 + _ATD1DR5 13A 2 2 0 .abs_section_13a + _ATD1DR6 13C 2 2 0 .abs_section_13c + _ATD1DR7 13E 2 2 0 .abs_section_13e + _DDRAB 2 2 2 1 .abs_section_2 + _MCCNT 76 2 2 0 .abs_section_76 + _PA10H 74 2 2 0 .abs_section_74 + _PA32H 72 2 2 0 .abs_section_72 + _PACN10 64 2 2 0 .abs_section_64 + _PACN32 62 2 2 0 .abs_section_62 + _PORTAB 0 2 2 6 .abs_section_0 + _PWMCNT01 AC 2 2 0 .abs_section_ac + _PWMCNT23 AE 2 2 0 .abs_section_ae + _PWMCNT45 B0 2 2 0 .abs_section_b0 + _PWMCNT67 B2 2 2 0 .abs_section_b2 + _PWMDTY01 BC 2 2 0 .abs_section_bc + _PWMDTY23 BE 2 2 0 .abs_section_be + _PWMDTY45 C0 2 2 0 .abs_section_c0 + _PWMDTY67 C2 2 2 0 .abs_section_c2 + _PWMPER01 B4 2 2 0 .abs_section_b4 + _PWMPER23 B6 2 2 0 .abs_section_b6 + _PWMPER45 B8 2 2 0 .abs_section_b8 + _PWMPER67 BA 2 2 0 .abs_section_ba + _SCI0BD C8 2 2 2 .abs_section_c8 + _SCI1BD D0 2 2 0 .abs_section_d0 + _TC0 50 2 2 2 .abs_section_50 + _TC0H 78 2 2 0 .abs_section_78 + _TC1 52 2 2 0 .abs_section_52 + _TC1H 7A 2 2 0 .abs_section_7a + _TC2 54 2 2 0 .abs_section_54 + _TC2H 7C 2 2 0 .abs_section_7c + _TC3 56 2 2 0 .abs_section_56 + _TC3H 7E 2 2 0 .abs_section_7e + _TC4 58 2 2 0 .abs_section_58 + _TC5 5A 2 2 0 .abs_section_5a + _TC6 5C 2 2 0 .abs_section_5c + _TC7 5E 2 2 2 .abs_section_5e + _TCNT 44 2 2 0 .abs_section_44 +MODULE: -- Vectors.c.o -- +- PROCEDURES: +- VARIABLES: + _vect FF80 80 128 0 .abs_section_ff80 +MODULE: -- RTOSDemo.C.o -- +- PROCEDURES: + main 30809A 9 9 0 .text +- VARIABLES: +MODULE: -- main.c.o -- +- PROCEDURES: + vMain 3080A3 52 82 1 .text + vErrorChecks 3080F5 39 57 3 .text + prvCheckOtherTasksAreStillRunning 30812E 50 80 2 .text + vApplicationIdleHook 30817E 70 112 2 .text +- VARIABLES: + STRING.Check.1 C09A 6 6 1 .rodata1 + xLocalError 1001 1 1 2 .bss +MODULE: -- ParTest.c.o -- +- PROCEDURES: + vParTestSetLED 3081EE 23 35 4 .text + vParTestToggleLED 308211 14 20 10 .text +- VARIABLES: +MODULE: -- serial.c.o -- +- PROCEDURES: + xSerialPortInitMinimal 308225 26 38 2 .text + xSerialGetChar 318000 13 19 4 ROM_PAGE31_524 + xSerialPutChar 318013 18 24 2 ROM_PAGE31_524 + vCOM0_ISR C300 59 89 1 NON_BANKED +- VARIABLES: + xRxedChars 1002 2 2 3 .bss + xCharsForTx 1004 2 2 3 .bss +MODULE: -- tasks.c.o -- +- PROCEDURES: + xTaskCreate 31802B D5 213 48 ROM_PAGE31_524 + vTaskDelete 318100 4A 74 4 ROM_PAGE31_524 + vTaskDelayUntil 31814A 77 119 6 ROM_PAGE31_524 + vTaskDelay 3181C1 46 70 16 ROM_PAGE31_524 + uxTaskPriorityGet 318207 22 34 2 ROM_PAGE31_524 + vTaskPrioritySet 328000 69 105 4 ROM_PAGE32_525 + vTaskSuspend 328069 47 71 6 ROM_PAGE32_525 + vTaskResume 3280B0 5C 92 6 ROM_PAGE32_525 + vTaskStartScheduler 32810C 31 49 2 ROM_PAGE32_525 + vTaskSuspendAll 32813D 13 19 26 ROM_PAGE32_525 + xTaskResumeAll 328150 9F 159 30 ROM_PAGE32_525 + xTaskGetTickCount 3281EF 17 23 6 ROM_PAGE32_525 + uxTaskGetNumberOfTasks 328206 17 23 4 ROM_PAGE32_525 + vTaskIncrementTick 338000 84 132 4 ROM_PAGE33_526 + vTaskSwitchContext 338084 5B 91 4 ROM_PAGE33_526 + vTaskPlaceOnEventList 3380DF 41 65 4 ROM_PAGE33_526 + xTaskRemoveFromEventList 338120 69 105 8 ROM_PAGE33_526 + prvIdleTask 338189 12 18 3 ROM_PAGE33_526 + prvInitialiseTCBVariables 33819B 4D 77 2 ROM_PAGE33_526 + prvInitialiseTaskLists 3381E8 3C 60 2 ROM_PAGE33_526 + prvCheckTasksWaitingTermination 348000 53 83 2 ROM_PAGE34_527 + prvAllocateTCBAndStack 348053 3D 61 2 ROM_PAGE34_527 + prvDeleteTCB 348090 F 15 2 ROM_PAGE34_527 +- VARIABLES: + STRING.IDLE.2 C0A0 5 5 1 .rodata1 + pxCurrentTCB 1006 2 2 28 .bss + uxTasksDeleted 1008 1 1 3 .bss + uxCurrentNumberOfTasks 1009 1 1 5 .bss + xTickCount 100A 2 2 14 .bss + uxTopUsedPriority 100C 1 1 2 .bss + uxTopReadyPriority 100D 1 1 15 .bss + xSchedulerRunning 100E 1 1 3 .bss + uxSchedulerSuspended 100F 1 1 6 .bss + uxMissedTicks 1010 1 1 4 .bss + uxTaskNumber.1 1011 1 1 2 .bss + pxReadyTasksLists 1012 3C 60 11 .bss + xDelayedTaskList1 104E F 15 2 .bss + xDelayedTaskList2 105D F 15 2 .bss + pxDelayedTaskList 106C 2 2 8 .bss + pxOverflowDelayedTaskList 106E 2 2 6 .bss + xPendingReadyList 1070 F 15 4 .bss + xTasksWaitingTermination 107F F 15 5 .bss + xSuspendedTaskList 108E F 15 2 .bss +MODULE: -- queue.c.o -- +- PROCEDURES: + xQueueCreate 34809F 7B 123 14 ROM_PAGE34_527 + xQueueSend 34811A D4 212 9 ROM_PAGE34_527 + xQueueSendFromISR 3481EE 5D 93 2 ROM_PAGE34_527 + xQueueReceive 358000 CF 207 9 ROM_PAGE35_528 + xQueueReceiveFromISR 3580CF 61 97 2 ROM_PAGE35_528 + uxQueueMessagesWaiting 358130 1B 27 2 ROM_PAGE35_528 + prvUnlockQueue 35814B 71 113 8 ROM_PAGE35_528 + prvIsQueueEmpty 3581BC 22 34 2 ROM_PAGE35_528 + prvIsQueueFull 3581DE 25 37 2 ROM_PAGE35_528 +- VARIABLES: +MODULE: -- list.c.o -- +- PROCEDURES: + vListInitialise 358203 20 32 6 ROM_PAGE35_528 + vListInitialiseItem 358223 7 7 6 ROM_PAGE35_528 + vListInsertEnd 35822A 25 37 16 ROM_PAGE35_528 + vListInsert 368000 55 85 8 ROM_PAGE36_529 + vListRemove 368055 23 35 32 ROM_PAGE36_529 +- VARIABLES: +MODULE: -- heap_2.c.o -- +- PROCEDURES: + pvPortMalloc 368078 C1 193 14 ROM_PAGE36_529 + vPortFree 368139 3B 59 10 ROM_PAGE36_529 +- VARIABLES: + xHeapHasBeenInitialised.1 109D 1 1 2 .bss + xHeap 109E 2804 10244 2 .bss + xStart 38A2 4 4 6 .bss + xEnd 38A6 4 4 4 .bss +MODULE: -- flash.c.o -- +- PROCEDURES: + vStartLEDFlashTasks 368174 32 50 2 ROM_PAGE36_529 + vLEDFlashTask 3681A6 57 87 3 ROM_PAGE36_529 +- VARIABLES: + STRING.LEDx.1 C0A5 5 5 1 .rodata1 + uxFlashTaskNumber 38AA 1 1 2 .bss +MODULE: -- dynamic.c.o -- +- PROCEDURES: + vStartDynamicPriorityTasks 378000 9B 155 2 ROM_PAGE37_530 + vLimitedIncrementTask 37809B 27 39 3 ROM_PAGE37_530 + vContinuousIncrementTask 3780C2 38 56 3 ROM_PAGE37_530 + vCounterControlTask 3780FA A0 160 5 ROM_PAGE37_530 + vQueueSendWhenSuspendedTask 37819A 38 56 3 ROM_PAGE37_530 + vQueueReceiveWhenSuspendedTask 3781D2 54 84 3 ROM_PAGE37_530 + xAreDynamicPriorityTasksStillRunning 378226 2B 43 2 ROM_PAGE37_530 +- VARIABLES: + STRING.CNT_INC.1 C0AA 8 8 1 .rodata1 + STRING.LIM_INC.2 C0B2 8 8 1 .rodata1 + STRING.C_CTRL.3 C0BA 7 7 1 .rodata1 + STRING.SUSP_TX.4 C0C1 8 8 1 .rodata1 + STRING.SUSP_RX.5 C0C9 8 8 1 .rodata1 + usCheckVariable 38AB 2 2 3 .bss + xSuspendedQueueSendError 38AD 1 1 2 .bss + xSuspendedQueueReceiveError 38AE 1 1 3 .bss + ulValueToSend.6 38AF 4 4 5 .bss + ulExpectedValue.7 38B3 4 4 6 .bss + usLastTaskCheck.9 38B7 2 2 2 .bss + xContinousIncrementHandle 38B9 2 2 5 .bss + xLimitedIncrementHandle 38BB 2 2 2 .bss + ulCounter 38BD 4 4 10 .bss + ulReceivedValue.8 38C1 4 4 3 .bss + xSuspendedTestQueue 38EC 2 2 3 .common +MODULE: -- PollQ.c.o -- +- PROCEDURES: + vStartPolledQueueTasks 388000 4B 75 2 ROM_PAGE38_531 + vPolledQueueProducer 38804B 4F 79 3 ROM_PAGE38_531 + vPolledQueueConsumer 38809A 5C 92 3 ROM_PAGE38_531 + xArePollingQueuesStillRunning 3880F6 16 22 2 ROM_PAGE38_531 +- VARIABLES: + STRING.QConsNB.2 C0D1 8 8 1 .rodata1 + STRING.QProdNB.3 C0D9 8 8 1 .rodata1 + xPollingConsumerCount 38C5 1 1 3 .bss + xPollingProducerCount 38C6 1 1 3 .bss + xPolledQueue.1 38C7 2 2 3 .bss +MODULE: -- TickTimer.C.o -- +- PROCEDURES: + TickTimer_Enable 3B8124 9 9 2 TickTimer_CODE + TickTimer_SetFreqHz 3B812D 56 86 2 TickTimer_CODE + TickTimer_Init 3B8183 1C 28 2 TickTimer_CODE +- VARIABLES: + CmpHighVal 38F2 2 2 2 TickTimer_DATA +MODULE: -- Byte1.C.o -- +- PROCEDURES: + Byte1_PutBit 3B819F 21 33 2 Byte1_CODE + Byte1_NegBit 3B81C0 14 20 2 Byte1_CODE +- VARIABLES: + Byte1_Table 38F4 8 8 2 Byte1_DATA +MODULE: -- PE_Timer.C.o -- +- PROCEDURES: + PE_Timer_LngHi1 38810C 4A 74 2 ROM_PAGE38_531 +- VARIABLES: +MODULE: -- comtest.c.o -- +- PROCEDURES: + vAltStartComTestTasks 388156 4D 77 2 ROM_PAGE38_531 + vComTxTask 3881A3 4F 79 3 ROM_PAGE38_531 + vComRxTask 398000 7B 123 3 ROM_PAGE39_532 + xAreComTestTasksStillRunning 39807B D 13 2 ROM_PAGE39_532 +- VARIABLES: + STRING.COMTx.1 C0E1 6 6 1 .rodata1 + STRING.COMRx.2 C0E7 6 6 1 .rodata1 + xPort 38C9 2 2 3 .bss + uxBaseLED 38CB 1 1 5 .bss + uxRxLoops 38CC 1 1 3 .bss +MODULE: -- COM0.C.o -- +- PROCEDURES: + COM0_SetBaudRateMode 3B81D4 19 25 2 COM0_CODE + COM0_Init 3B81ED 25 37 2 COM0_CODE +- VARIABLES: + COM0_PrescHigh.1 38FC 8 8 1 COM0_DATA + SerFlag 3904 2 2 1 COM0_DATA + PrescHigh 3906 2 2 2 COM0_DATA + NumMode 3908 1 1 2 COM0_DATA +MODULE: -- port.c.o -- +- PROCEDURES: + pxPortInitialiseStack 398088 31 49 2 ROM_PAGE39_532 + xPortStartScheduler 3980B9 4 4 2 ROM_PAGE39_532 + xBankedStartScheduler C359 1A 26 1 NON_BANKED + vPortYield C373 1D 29 1 NON_BANKED + vPortTickInterrupt C390 25 37 1 NON_BANKED +- VARIABLES: + uxCriticalNesting 1000 1 1 101 .data +MODULE: -- integer.c.o -- +- PROCEDURES: + vStartIntegerMathTasks 3980BD 33 51 2 ROM_PAGE39_532 + vCompeteingIntMathTask 3980F0 87 135 3 ROM_PAGE39_532 + xAreIntegerMathsTaskStillRunning 398177 20 32 2 ROM_PAGE39_532 +- VARIABLES: + STRING.IntMath.1 C0ED 8 8 1 .rodata1 + xTaskCheck 38CD 1 1 3 .bss +MODULE: -- BlockQ.c.o -- +- PROCEDURES: + vStartBlockingQueueTasks 3A8000 143 323 7 ROM_PAGE3A_533 + vBlockingQueueProducer 3A8143 3F 63 9 ROM_PAGE3A_533 + vBlockingQueueConsumer 3A8182 47 71 9 ROM_PAGE3A_533 + xAreBlockingQueuesStillRunning 3A81C9 52 82 2 ROM_PAGE3A_533 +- VARIABLES: + STRING.QConsB1.1 C0F5 8 8 1 .rodata1 + STRING.QProdB2.2 C0FD 8 8 1 .rodata1 + STRING.QProdB3.3 C105 8 8 1 .rodata1 + STRING.QConsB4.4 C10D 8 8 1 .rodata1 + STRING.QProdB5.5 C115 8 8 1 .rodata1 + STRING.QConsB6.6 C11D 8 8 1 .rodata1 + sBlockingConsumerCount 38CE 6 6 4 .bss + sBlockingProducerCount 38D4 6 6 5 .bss + sLastBlockingConsumerCount.7 38DA 6 6 2 .bss + sLastBlockingProducerCount.8 38E0 6 6 2 .bss +MODULE: -- death.c.o -- +- PROCEDURES: + vCreateSuicidalTasks 3A821B 31 49 2 ROM_PAGE3A_533 + vSuicidalTask 3B8000 58 88 12 ROM_PAGE3B_534 + vCreateTasks 3B8058 92 146 4 ROM_PAGE3B_534 + xIsCreateTaskStillRunning 3B80EA 3A 58 2 ROM_PAGE3B_534 +- VARIABLES: + STRING.CREATOR.1 C125 8 8 1 .rodata1 + STRING.SUICIDE1.2 C12D 9 9 1 .rodata1 + STRING.SUICIDE2.3 C136 9 9 1 .rodata1 + STRING.SUICIDE1.4 C13F 9 9 1 .rodata1 + STRING.SUICIDE2.5 C148 9 9 1 .rodata1 + usCreationCount 38E6 2 2 4 .bss + uxTasksRunningAtStart 38E8 1 1 4 .bss + usLastCreationCount.6 38E9 2 2 2 .bss + uxTasksRunningNow.7 38EB 1 1 1 .bss + xCreatedTask1 38EE 2 2 2 .common + xCreatedTask2 38F0 2 2 2 .common + +********************************************************************************************* +MODULE STATISTIC + Name Data Code Const +--------------------------------------------------------------------------------------------- + Start12.c.o 0 59 0 + STRING.C.o (ansibi.lib) 0 113 0 + rtshc12.c.o (ansibi.lib) 0 412 0 + Cpu.C.o 0 125 0 + IO_Map.C.o 577 0 0 + Vectors.c.o 0 0 128 + RTOSDemo.C.o 0 9 0 + main.c.o 1 331 6 + ParTest.c.o 0 55 0 + serial.c.o 4 170 0 + tasks.c.o 151 1758 5 + queue.c.o 0 943 0 + list.c.o 0 196 0 + heap_2.c.o 10253 252 0 + flash.c.o 1 137 5 + dynamic.c.o 28 593 39 + PollQ.c.o 4 268 16 + TickTimer.C.o 2 123 0 + Byte1.C.o 8 53 0 + PE_Timer.C.o 0 74 0 + comtest.c.o 4 292 12 + COM0.C.o 13 62 0 + port.c.o 1 145 0 + integer.c.o 1 218 8 + BlockQ.c.o 24 539 48 + death.c.o 10 341 44 + other 128 30 27 + +********************************************************************************************* +SECTION USE IN OBJECT-ALLOCATION SECTION +--------------------------------------------------------------------------------------------- +SECTION: ".text" + Init memcpy memset strncpy main vMain vErrorChecks + prvCheckOtherTasksAreStillRunning vApplicationIdleHook vParTestSetLED + vParTestToggleLED xSerialPortInitMinimal +SECTION: ".data" + uxCriticalNesting +SECTION: ".bss" + xLocalError xRxedChars xCharsForTx pxCurrentTCB uxTasksDeleted + uxCurrentNumberOfTasks xTickCount uxTopUsedPriority uxTopReadyPriority + xSchedulerRunning uxSchedulerSuspended uxMissedTicks uxTaskNumber.1 + pxReadyTasksLists xDelayedTaskList1 xDelayedTaskList2 pxDelayedTaskList + pxOverflowDelayedTaskList xPendingReadyList xTasksWaitingTermination + xSuspendedTaskList xHeapHasBeenInitialised.1 xHeap xStart xEnd + uxFlashTaskNumber usCheckVariable xSuspendedQueueSendError + xSuspendedQueueReceiveError ulValueToSend.6 ulExpectedValue.7 + usLastTaskCheck.9 xContinousIncrementHandle xLimitedIncrementHandle ulCounter + ulReceivedValue.8 xPollingConsumerCount xPollingProducerCount xPolledQueue.1 + xPort uxBaseLED uxRxLoops xTaskCheck sBlockingConsumerCount + sBlockingProducerCount sLastBlockingConsumerCount.7 + sLastBlockingProducerCount.8 usCreationCount uxTasksRunningAtStart + usLastCreationCount.6 uxTasksRunningNow.7 +SECTION: ".init" + _EntryPoint PE_low_level_init +SECTION: ".rodata1" + STRING.Check.1 STRING.IDLE.2 STRING.LEDx.1 STRING.CNT_INC.1 STRING.LIM_INC.2 + STRING.C_CTRL.3 STRING.SUSP_TX.4 STRING.SUSP_RX.5 STRING.QConsNB.2 + STRING.QProdNB.3 STRING.COMTx.1 STRING.COMRx.2 STRING.IntMath.1 + STRING.QConsB1.1 STRING.QProdB2.2 STRING.QProdB3.3 STRING.QConsB4.4 + STRING.QProdB5.5 STRING.QConsB6.6 STRING.CREATOR.1 STRING.SUICIDE1.2 + STRING.SUICIDE2.3 STRING.SUICIDE1.4 STRING.SUICIDE2.5 +SECTION: "NON_BANKED" + _Startup _LCMP _LCMP_P _LNEG _LINC _LMUL _lDivMod _LDIVU _NEG_P _LDIVS + Cpu_Interrupt vCOM0_ISR xBankedStartScheduler vPortYield vPortTickInterrupt +SECTION: ".common" + xSuspendedTestQueue xCreatedTask1 xCreatedTask2 +SECTION: "TickTimer_CODE" + TickTimer_Enable TickTimer_SetFreqHz TickTimer_Init +SECTION: "Byte1_CODE" + Byte1_PutBit Byte1_NegBit +SECTION: "COM0_CODE" + COM0_SetBaudRateMode COM0_Init +SECTION: ".abs_section_3f" + _ARMCOP +SECTION: ".abs_section_8d" + _ATD0DIEN +SECTION: ".abs_section_86" + _ATD0STAT0 +SECTION: ".abs_section_8b" + _ATD0STAT1 +SECTION: ".abs_section_12d" + _ATD1DIEN +SECTION: ".abs_section_126" + _ATD1STAT0 +SECTION: ".abs_section_12b" + _ATD1STAT1 +SECTION: ".abs_section_ff06" + _BDMCCR +SECTION: ".abs_section_ff07" + _BDMINR +SECTION: ".abs_section_ff01" + _BDMSTS +SECTION: ".abs_section_2b" + _BKP0H +SECTION: ".abs_section_2c" + _BKP0L +SECTION: ".abs_section_2a" + _BKP0X +SECTION: ".abs_section_2e" + _BKP1H +SECTION: ".abs_section_2f" + _BKP1L +SECTION: ".abs_section_2d" + _BKP1X +SECTION: ".abs_section_28" + _BKPCT0 +SECTION: ".abs_section_29" + _BKPCT1 +SECTION: ".abs_section_142" + _CAN0BTR0 +SECTION: ".abs_section_143" + _CAN0BTR1 +SECTION: ".abs_section_140" + _CAN0CTL0 +SECTION: ".abs_section_141" + _CAN0CTL1 +SECTION: ".abs_section_14b" + _CAN0IDAC +SECTION: ".abs_section_150" + _CAN0IDAR0 +SECTION: ".abs_section_151" + _CAN0IDAR1 +SECTION: ".abs_section_152" + _CAN0IDAR2 +SECTION: ".abs_section_153" + _CAN0IDAR3 +SECTION: ".abs_section_158" + _CAN0IDAR4 +SECTION: ".abs_section_159" + _CAN0IDAR5 +SECTION: ".abs_section_15a" + _CAN0IDAR6 +SECTION: ".abs_section_15b" + _CAN0IDAR7 +SECTION: ".abs_section_154" + _CAN0IDMR0 +SECTION: ".abs_section_155" + _CAN0IDMR1 +SECTION: ".abs_section_156" + _CAN0IDMR2 +SECTION: ".abs_section_157" + _CAN0IDMR3 +SECTION: ".abs_section_15c" + _CAN0IDMR4 +SECTION: ".abs_section_15d" + _CAN0IDMR5 +SECTION: ".abs_section_15e" + _CAN0IDMR6 +SECTION: ".abs_section_15f" + _CAN0IDMR7 +SECTION: ".abs_section_144" + _CAN0RFLG +SECTION: ".abs_section_145" + _CAN0RIER +SECTION: ".abs_section_16c" + _CAN0RXDLR +SECTION: ".abs_section_164" + _CAN0RXDSR0 +SECTION: ".abs_section_165" + _CAN0RXDSR1 +SECTION: ".abs_section_166" + _CAN0RXDSR2 +SECTION: ".abs_section_167" + _CAN0RXDSR3 +SECTION: ".abs_section_168" + _CAN0RXDSR4 +SECTION: ".abs_section_169" + _CAN0RXDSR5 +SECTION: ".abs_section_16a" + _CAN0RXDSR6 +SECTION: ".abs_section_16b" + _CAN0RXDSR7 +SECTION: ".abs_section_14e" + _CAN0RXERR +SECTION: ".abs_section_160" + _CAN0RXIDR0 +SECTION: ".abs_section_161" + _CAN0RXIDR1 +SECTION: ".abs_section_162" + _CAN0RXIDR2 +SECTION: ".abs_section_163" + _CAN0RXIDR3 +SECTION: ".abs_section_149" + _CAN0TAAK +SECTION: ".abs_section_148" + _CAN0TARQ +SECTION: ".abs_section_14a" + _CAN0TBSEL +SECTION: ".abs_section_146" + _CAN0TFLG +SECTION: ".abs_section_147" + _CAN0TIER +SECTION: ".abs_section_17c" + _CAN0TXDLR +SECTION: ".abs_section_174" + _CAN0TXDSR0 +SECTION: ".abs_section_175" + _CAN0TXDSR1 +SECTION: ".abs_section_176" + _CAN0TXDSR2 +SECTION: ".abs_section_177" + _CAN0TXDSR3 +SECTION: ".abs_section_178" + _CAN0TXDSR4 +SECTION: ".abs_section_179" + _CAN0TXDSR5 +SECTION: ".abs_section_17a" + _CAN0TXDSR6 +SECTION: ".abs_section_17b" + _CAN0TXDSR7 +SECTION: ".abs_section_14f" + _CAN0TXERR +SECTION: ".abs_section_170" + _CAN0TXIDR0 +SECTION: ".abs_section_171" + _CAN0TXIDR1 +SECTION: ".abs_section_172" + _CAN0TXIDR2 +SECTION: ".abs_section_173" + _CAN0TXIDR3 +SECTION: ".abs_section_17f" + _CAN0TXTBPR +SECTION: ".abs_section_182" + _CAN1BTR0 +SECTION: ".abs_section_183" + _CAN1BTR1 +SECTION: ".abs_section_180" + _CAN1CTL0 +SECTION: ".abs_section_181" + _CAN1CTL1 +SECTION: ".abs_section_18b" + _CAN1IDAC +SECTION: ".abs_section_190" + _CAN1IDAR0 +SECTION: ".abs_section_191" + _CAN1IDAR1 +SECTION: ".abs_section_192" + _CAN1IDAR2 +SECTION: ".abs_section_193" + _CAN1IDAR3 +SECTION: ".abs_section_198" + _CAN1IDAR4 +SECTION: ".abs_section_199" + _CAN1IDAR5 +SECTION: ".abs_section_19a" + _CAN1IDAR6 +SECTION: ".abs_section_19b" + _CAN1IDAR7 +SECTION: ".abs_section_194" + _CAN1IDMR0 +SECTION: ".abs_section_195" + _CAN1IDMR1 +SECTION: ".abs_section_196" + _CAN1IDMR2 +SECTION: ".abs_section_197" + _CAN1IDMR3 +SECTION: ".abs_section_19c" + _CAN1IDMR4 +SECTION: ".abs_section_19d" + _CAN1IDMR5 +SECTION: ".abs_section_19e" + _CAN1IDMR6 +SECTION: ".abs_section_19f" + _CAN1IDMR7 +SECTION: ".abs_section_184" + _CAN1RFLG +SECTION: ".abs_section_185" + _CAN1RIER +SECTION: ".abs_section_1ac" + _CAN1RXDLR +SECTION: ".abs_section_1a4" + _CAN1RXDSR0 +SECTION: ".abs_section_1a5" + _CAN1RXDSR1 +SECTION: ".abs_section_1a6" + _CAN1RXDSR2 +SECTION: ".abs_section_1a7" + _CAN1RXDSR3 +SECTION: ".abs_section_1a8" + _CAN1RXDSR4 +SECTION: ".abs_section_1a9" + _CAN1RXDSR5 +SECTION: ".abs_section_1aa" + _CAN1RXDSR6 +SECTION: ".abs_section_1ab" + _CAN1RXDSR7 +SECTION: ".abs_section_18e" + _CAN1RXERR +SECTION: ".abs_section_1a0" + _CAN1RXIDR0 +SECTION: ".abs_section_1a1" + _CAN1RXIDR1 +SECTION: ".abs_section_1a2" + _CAN1RXIDR2 +SECTION: ".abs_section_1a3" + _CAN1RXIDR3 +SECTION: ".abs_section_189" + _CAN1TAAK +SECTION: ".abs_section_188" + _CAN1TARQ +SECTION: ".abs_section_18a" + _CAN1TBSEL +SECTION: ".abs_section_186" + _CAN1TFLG +SECTION: ".abs_section_187" + _CAN1TIER +SECTION: ".abs_section_1bc" + _CAN1TXDLR +SECTION: ".abs_section_1b4" + _CAN1TXDSR0 +SECTION: ".abs_section_1b5" + _CAN1TXDSR1 +SECTION: ".abs_section_1b6" + _CAN1TXDSR2 +SECTION: ".abs_section_1b7" + _CAN1TXDSR3 +SECTION: ".abs_section_1b8" + _CAN1TXDSR4 +SECTION: ".abs_section_1b9" + _CAN1TXDSR5 +SECTION: ".abs_section_1ba" + _CAN1TXDSR6 +SECTION: ".abs_section_1bb" + _CAN1TXDSR7 +SECTION: ".abs_section_18f" + _CAN1TXERR +SECTION: ".abs_section_1b0" + _CAN1TXIDR0 +SECTION: ".abs_section_1b1" + _CAN1TXIDR1 +SECTION: ".abs_section_1b2" + _CAN1TXIDR2 +SECTION: ".abs_section_1b3" + _CAN1TXIDR3 +SECTION: ".abs_section_1bf" + _CAN1TXTBPR +SECTION: ".abs_section_1c2" + _CAN2BTR0 +SECTION: ".abs_section_1c3" + _CAN2BTR1 +SECTION: ".abs_section_1c0" + _CAN2CTL0 +SECTION: ".abs_section_1c1" + _CAN2CTL1 +SECTION: ".abs_section_1cb" + _CAN2IDAC +SECTION: ".abs_section_1d0" + _CAN2IDAR0 +SECTION: ".abs_section_1d1" + _CAN2IDAR1 +SECTION: ".abs_section_1d2" + _CAN2IDAR2 +SECTION: ".abs_section_1d3" + _CAN2IDAR3 +SECTION: ".abs_section_1d8" + _CAN2IDAR4 +SECTION: ".abs_section_1d9" + _CAN2IDAR5 +SECTION: ".abs_section_1da" + _CAN2IDAR6 +SECTION: ".abs_section_1db" + _CAN2IDAR7 +SECTION: ".abs_section_1d4" + _CAN2IDMR0 +SECTION: ".abs_section_1d5" + _CAN2IDMR1 +SECTION: ".abs_section_1d6" + _CAN2IDMR2 +SECTION: ".abs_section_1d7" + _CAN2IDMR3 +SECTION: ".abs_section_1dc" + _CAN2IDMR4 +SECTION: ".abs_section_1dd" + _CAN2IDMR5 +SECTION: ".abs_section_1de" + _CAN2IDMR6 +SECTION: ".abs_section_1df" + _CAN2IDMR7 +SECTION: ".abs_section_1c4" + _CAN2RFLG +SECTION: ".abs_section_1c5" + _CAN2RIER +SECTION: ".abs_section_1ec" + _CAN2RXDLR +SECTION: ".abs_section_1e4" + _CAN2RXDSR0 +SECTION: ".abs_section_1e5" + _CAN2RXDSR1 +SECTION: ".abs_section_1e6" + _CAN2RXDSR2 +SECTION: ".abs_section_1e7" + _CAN2RXDSR3 +SECTION: ".abs_section_1e8" + _CAN2RXDSR4 +SECTION: ".abs_section_1e9" + _CAN2RXDSR5 +SECTION: ".abs_section_1ea" + _CAN2RXDSR6 +SECTION: ".abs_section_1eb" + _CAN2RXDSR7 +SECTION: ".abs_section_1ce" + _CAN2RXERR +SECTION: ".abs_section_1e0" + _CAN2RXIDR0 +SECTION: ".abs_section_1e1" + _CAN2RXIDR1 +SECTION: ".abs_section_1e2" + _CAN2RXIDR2 +SECTION: ".abs_section_1e3" + _CAN2RXIDR3 +SECTION: ".abs_section_1c9" + _CAN2TAAK +SECTION: ".abs_section_1c8" + _CAN2TARQ +SECTION: ".abs_section_1ca" + _CAN2TBSEL +SECTION: ".abs_section_1c6" + _CAN2TFLG +SECTION: ".abs_section_1c7" + _CAN2TIER +SECTION: ".abs_section_1fc" + _CAN2TXDLR +SECTION: ".abs_section_1f4" + _CAN2TXDSR0 +SECTION: ".abs_section_1f5" + _CAN2TXDSR1 +SECTION: ".abs_section_1f6" + _CAN2TXDSR2 +SECTION: ".abs_section_1f7" + _CAN2TXDSR3 +SECTION: ".abs_section_1f8" + _CAN2TXDSR4 +SECTION: ".abs_section_1f9" + _CAN2TXDSR5 +SECTION: ".abs_section_1fa" + _CAN2TXDSR6 +SECTION: ".abs_section_1fb" + _CAN2TXDSR7 +SECTION: ".abs_section_1cf" + _CAN2TXERR +SECTION: ".abs_section_1f0" + _CAN2TXIDR0 +SECTION: ".abs_section_1f1" + _CAN2TXIDR1 +SECTION: ".abs_section_1f2" + _CAN2TXIDR2 +SECTION: ".abs_section_1f3" + _CAN2TXIDR3 +SECTION: ".abs_section_1ff" + _CAN2TXTBPR +SECTION: ".abs_section_202" + _CAN3BTR0 +SECTION: ".abs_section_203" + _CAN3BTR1 +SECTION: ".abs_section_200" + _CAN3CTL0 +SECTION: ".abs_section_201" + _CAN3CTL1 +SECTION: ".abs_section_20b" + _CAN3IDAC +SECTION: ".abs_section_210" + _CAN3IDAR0 +SECTION: ".abs_section_211" + _CAN3IDAR1 +SECTION: ".abs_section_212" + _CAN3IDAR2 +SECTION: ".abs_section_213" + _CAN3IDAR3 +SECTION: ".abs_section_218" + _CAN3IDAR4 +SECTION: ".abs_section_219" + _CAN3IDAR5 +SECTION: ".abs_section_21a" + _CAN3IDAR6 +SECTION: ".abs_section_21b" + _CAN3IDAR7 +SECTION: ".abs_section_214" + _CAN3IDMR0 +SECTION: ".abs_section_215" + _CAN3IDMR1 +SECTION: ".abs_section_216" + _CAN3IDMR2 +SECTION: ".abs_section_217" + _CAN3IDMR3 +SECTION: ".abs_section_21c" + _CAN3IDMR4 +SECTION: ".abs_section_21d" + _CAN3IDMR5 +SECTION: ".abs_section_21e" + _CAN3IDMR6 +SECTION: ".abs_section_21f" + _CAN3IDMR7 +SECTION: ".abs_section_204" + _CAN3RFLG +SECTION: ".abs_section_205" + _CAN3RIER +SECTION: ".abs_section_22c" + _CAN3RXDLR +SECTION: ".abs_section_224" + _CAN3RXDSR0 +SECTION: ".abs_section_225" + _CAN3RXDSR1 +SECTION: ".abs_section_226" + _CAN3RXDSR2 +SECTION: ".abs_section_227" + _CAN3RXDSR3 +SECTION: ".abs_section_228" + _CAN3RXDSR4 +SECTION: ".abs_section_229" + _CAN3RXDSR5 +SECTION: ".abs_section_22a" + _CAN3RXDSR6 +SECTION: ".abs_section_22b" + _CAN3RXDSR7 +SECTION: ".abs_section_20e" + _CAN3RXERR +SECTION: ".abs_section_220" + _CAN3RXIDR0 +SECTION: ".abs_section_221" + _CAN3RXIDR1 +SECTION: ".abs_section_222" + _CAN3RXIDR2 +SECTION: ".abs_section_223" + _CAN3RXIDR3 +SECTION: ".abs_section_209" + _CAN3TAAK +SECTION: ".abs_section_208" + _CAN3TARQ +SECTION: ".abs_section_20a" + _CAN3TBSEL +SECTION: ".abs_section_206" + _CAN3TFLG +SECTION: ".abs_section_207" + _CAN3TIER +SECTION: ".abs_section_23c" + _CAN3TXDLR +SECTION: ".abs_section_234" + _CAN3TXDSR0 +SECTION: ".abs_section_235" + _CAN3TXDSR1 +SECTION: ".abs_section_236" + _CAN3TXDSR2 +SECTION: ".abs_section_237" + _CAN3TXDSR3 +SECTION: ".abs_section_238" + _CAN3TXDSR4 +SECTION: ".abs_section_239" + _CAN3TXDSR5 +SECTION: ".abs_section_23a" + _CAN3TXDSR6 +SECTION: ".abs_section_23b" + _CAN3TXDSR7 +SECTION: ".abs_section_20f" + _CAN3TXERR +SECTION: ".abs_section_230" + _CAN3TXIDR0 +SECTION: ".abs_section_231" + _CAN3TXIDR1 +SECTION: ".abs_section_232" + _CAN3TXIDR2 +SECTION: ".abs_section_233" + _CAN3TXIDR3 +SECTION: ".abs_section_23f" + _CAN3TXTBPR +SECTION: ".abs_section_282" + _CAN4BTR0 +SECTION: ".abs_section_283" + _CAN4BTR1 +SECTION: ".abs_section_280" + _CAN4CTL0 +SECTION: ".abs_section_281" + _CAN4CTL1 +SECTION: ".abs_section_28b" + _CAN4IDAC +SECTION: ".abs_section_290" + _CAN4IDAR0 +SECTION: ".abs_section_291" + _CAN4IDAR1 +SECTION: ".abs_section_292" + _CAN4IDAR2 +SECTION: ".abs_section_293" + _CAN4IDAR3 +SECTION: ".abs_section_298" + _CAN4IDAR4 +SECTION: ".abs_section_299" + _CAN4IDAR5 +SECTION: ".abs_section_29a" + _CAN4IDAR6 +SECTION: ".abs_section_29b" + _CAN4IDAR7 +SECTION: ".abs_section_294" + _CAN4IDMR0 +SECTION: ".abs_section_295" + _CAN4IDMR1 +SECTION: ".abs_section_296" + _CAN4IDMR2 +SECTION: ".abs_section_297" + _CAN4IDMR3 +SECTION: ".abs_section_29c" + _CAN4IDMR4 +SECTION: ".abs_section_29d" + _CAN4IDMR5 +SECTION: ".abs_section_29e" + _CAN4IDMR6 +SECTION: ".abs_section_29f" + _CAN4IDMR7 +SECTION: ".abs_section_284" + _CAN4RFLG +SECTION: ".abs_section_285" + _CAN4RIER +SECTION: ".abs_section_2ac" + _CAN4RXDLR +SECTION: ".abs_section_2a4" + _CAN4RXDSR0 +SECTION: ".abs_section_2a5" + _CAN4RXDSR1 +SECTION: ".abs_section_2a6" + _CAN4RXDSR2 +SECTION: ".abs_section_2a7" + _CAN4RXDSR3 +SECTION: ".abs_section_2a8" + _CAN4RXDSR4 +SECTION: ".abs_section_2a9" + _CAN4RXDSR5 +SECTION: ".abs_section_2aa" + _CAN4RXDSR6 +SECTION: ".abs_section_2ab" + _CAN4RXDSR7 +SECTION: ".abs_section_28e" + _CAN4RXERR +SECTION: ".abs_section_2a0" + _CAN4RXIDR0 +SECTION: ".abs_section_2a1" + _CAN4RXIDR1 +SECTION: ".abs_section_2a2" + _CAN4RXIDR2 +SECTION: ".abs_section_2a3" + _CAN4RXIDR3 +SECTION: ".abs_section_289" + _CAN4TAAK +SECTION: ".abs_section_288" + _CAN4TARQ +SECTION: ".abs_section_28a" + _CAN4TBSEL +SECTION: ".abs_section_286" + _CAN4TFLG +SECTION: ".abs_section_287" + _CAN4TIER +SECTION: ".abs_section_2bc" + _CAN4TXDLR +SECTION: ".abs_section_2b4" + _CAN4TXDSR0 +SECTION: ".abs_section_2b5" + _CAN4TXDSR1 +SECTION: ".abs_section_2b6" + _CAN4TXDSR2 +SECTION: ".abs_section_2b7" + _CAN4TXDSR3 +SECTION: ".abs_section_2b8" + _CAN4TXDSR4 +SECTION: ".abs_section_2b9" + _CAN4TXDSR5 +SECTION: ".abs_section_2ba" + _CAN4TXDSR6 +SECTION: ".abs_section_2bb" + _CAN4TXDSR7 +SECTION: ".abs_section_28f" + _CAN4TXERR +SECTION: ".abs_section_2b0" + _CAN4TXIDR0 +SECTION: ".abs_section_2b1" + _CAN4TXIDR1 +SECTION: ".abs_section_2b2" + _CAN4TXIDR2 +SECTION: ".abs_section_2b3" + _CAN4TXIDR3 +SECTION: ".abs_section_2bf" + _CAN4TXTBPR +SECTION: ".abs_section_41" + _CFORC +SECTION: ".abs_section_39" + _CLKSEL +SECTION: ".abs_section_3c" + _COPCTL +SECTION: ".abs_section_37" + _CRGFLG +SECTION: ".abs_section_38" + _CRGINT +SECTION: ".abs_section_3e" + _CTCTL +SECTION: ".abs_section_36" + _CTFLG +SECTION: ".abs_section_9" + _DDRE +SECTION: ".abs_section_262" + _DDRH +SECTION: ".abs_section_26a" + _DDRJ +SECTION: ".abs_section_33" + _DDRK +SECTION: ".abs_section_252" + _DDRM +SECTION: ".abs_section_25a" + _DDRP +SECTION: ".abs_section_24a" + _DDRS +SECTION: ".abs_section_242" + _DDRT +SECTION: ".abs_section_ec" + _DLCBARD +SECTION: ".abs_section_e8" + _DLCBCR1 +SECTION: ".abs_section_ea" + _DLCBCR2 +SECTION: ".abs_section_eb" + _DLCBDR +SECTION: ".abs_section_ed" + _DLCBRSR +SECTION: ".abs_section_e9" + _DLCBSVR +SECTION: ".abs_section_ee" + _DLCSCR +SECTION: ".abs_section_69" + _DLYCT +SECTION: ".abs_section_e" + _EBICTL +SECTION: ".abs_section_110" + _ECLKDIV +SECTION: ".abs_section_116" + _ECMD +SECTION: ".abs_section_113" + _ECNFG +SECTION: ".abs_section_114" + _EPROT +SECTION: ".abs_section_115" + _ESTAT +SECTION: ".abs_section_100" + _FCLKDIV +SECTION: ".abs_section_106" + _FCMD +SECTION: ".abs_section_103" + _FCNFG +SECTION: ".abs_section_3d" + _FORBYP +SECTION: ".abs_section_104" + _FPROT +SECTION: ".abs_section_101" + _FSEC +SECTION: ".abs_section_105" + _FSTAT +SECTION: ".abs_section_1f" + _HPRIO +SECTION: ".abs_section_e0" + _IBAD +SECTION: ".abs_section_e2" + _IBCR +SECTION: ".abs_section_e4" + _IBDR +SECTION: ".abs_section_e1" + _IBFD +SECTION: ".abs_section_e3" + _IBSR +SECTION: ".abs_section_6a" + _ICOVW +SECTION: ".abs_section_68" + _ICPAR +SECTION: ".abs_section_6b" + _ICSYS +SECTION: ".abs_section_12" + _INITEE +SECTION: ".abs_section_11" + _INITRG +SECTION: ".abs_section_10" + _INITRM +SECTION: ".abs_section_1e" + _INTCR +SECTION: ".abs_section_15" + _ITCR +SECTION: ".abs_section_16" + _ITEST +SECTION: ".abs_section_66" + _MCCTL +SECTION: ".abs_section_67" + _MCFLG +SECTION: ".abs_section_1c" + _MEMSIZ0 +SECTION: ".abs_section_1d" + _MEMSIZ1 +SECTION: ".abs_section_13" + _MISC +SECTION: ".abs_section_b" + _MODE +SECTION: ".abs_section_257" + _MODRR +SECTION: ".abs_section_14" + _MTST0 +SECTION: ".abs_section_17" + _MTST1 +SECTION: ".abs_section_43" + _OC7D +SECTION: ".abs_section_42" + _OC7M +SECTION: ".abs_section_60" + _PACTL +SECTION: ".abs_section_61" + _PAFLG +SECTION: ".abs_section_1a" + _PARTIDH +SECTION: ".abs_section_1b" + _PARTIDL +SECTION: ".abs_section_70" + _PBCTL +SECTION: ".abs_section_71" + _PBFLG +SECTION: ".abs_section_a" + _PEAR +SECTION: ".abs_section_264" + _PERH +SECTION: ".abs_section_26c" + _PERJ +SECTION: ".abs_section_254" + _PERM +SECTION: ".abs_section_25c" + _PERP +SECTION: ".abs_section_24c" + _PERS +SECTION: ".abs_section_244" + _PERT +SECTION: ".abs_section_266" + _PIEH +SECTION: ".abs_section_26e" + _PIEJ +SECTION: ".abs_section_25e" + _PIEP +SECTION: ".abs_section_267" + _PIFH +SECTION: ".abs_section_26f" + _PIFJ +SECTION: ".abs_section_25f" + _PIFP +SECTION: ".abs_section_3a" + _PLLCTL +SECTION: ".abs_section_8f" + _PORTAD0 +SECTION: ".abs_section_12f" + _PORTAD1 +SECTION: ".abs_section_8" + _PORTE +SECTION: ".abs_section_32" + _PORTK +SECTION: ".abs_section_30" + _PPAGE +SECTION: ".abs_section_265" + _PPSH +SECTION: ".abs_section_26d" + _PPSJ +SECTION: ".abs_section_255" + _PPSM +SECTION: ".abs_section_25d" + _PPSP +SECTION: ".abs_section_24d" + _PPSS +SECTION: ".abs_section_245" + _PPST +SECTION: ".abs_section_260" + _PTH +SECTION: ".abs_section_261" + _PTIH +SECTION: ".abs_section_269" + _PTIJ +SECTION: ".abs_section_251" + _PTIM +SECTION: ".abs_section_259" + _PTIP +SECTION: ".abs_section_249" + _PTIS +SECTION: ".abs_section_241" + _PTIT +SECTION: ".abs_section_268" + _PTJ +SECTION: ".abs_section_250" + _PTM +SECTION: ".abs_section_258" + _PTP +SECTION: ".abs_section_248" + _PTS +SECTION: ".abs_section_240" + _PTT +SECTION: ".abs_section_c" + _PUCR +SECTION: ".abs_section_a4" + _PWMCAE +SECTION: ".abs_section_a2" + _PWMCLK +SECTION: ".abs_section_a5" + _PWMCTL +SECTION: ".abs_section_a0" + _PWME +SECTION: ".abs_section_a1" + _PWMPOL +SECTION: ".abs_section_a3" + _PWMPRCLK +SECTION: ".abs_section_a8" + _PWMSCLA +SECTION: ".abs_section_a9" + _PWMSCLB +SECTION: ".abs_section_c4" + _PWMSDN +SECTION: ".abs_section_263" + _RDRH +SECTION: ".abs_section_d" + _RDRIV +SECTION: ".abs_section_26b" + _RDRJ +SECTION: ".abs_section_253" + _RDRM +SECTION: ".abs_section_25b" + _RDRP +SECTION: ".abs_section_24b" + _RDRS +SECTION: ".abs_section_243" + _RDRT +SECTION: ".abs_section_35" + _REFDV +SECTION: ".abs_section_3b" + _RTICTL +SECTION: ".abs_section_ca" + _SCI0CR1 +SECTION: ".abs_section_cb" + _SCI0CR2 +SECTION: ".abs_section_ce" + _SCI0DRH +SECTION: ".abs_section_cf" + _SCI0DRL +SECTION: ".abs_section_cc" + _SCI0SR1 +SECTION: ".abs_section_cd" + _SCI0SR2 +SECTION: ".abs_section_d2" + _SCI1CR1 +SECTION: ".abs_section_d3" + _SCI1CR2 +SECTION: ".abs_section_d6" + _SCI1DRH +SECTION: ".abs_section_d7" + _SCI1DRL +SECTION: ".abs_section_d4" + _SCI1SR1 +SECTION: ".abs_section_d5" + _SCI1SR2 +SECTION: ".abs_section_da" + _SPI0BR +SECTION: ".abs_section_d8" + _SPI0CR1 +SECTION: ".abs_section_d9" + _SPI0CR2 +SECTION: ".abs_section_dd" + _SPI0DR +SECTION: ".abs_section_db" + _SPI0SR +SECTION: ".abs_section_f2" + _SPI1BR +SECTION: ".abs_section_f0" + _SPI1CR1 +SECTION: ".abs_section_f1" + _SPI1CR2 +SECTION: ".abs_section_f5" + _SPI1DR +SECTION: ".abs_section_f3" + _SPI1SR +SECTION: ".abs_section_fa" + _SPI2BR +SECTION: ".abs_section_f8" + _SPI2CR1 +SECTION: ".abs_section_f9" + _SPI2CR2 +SECTION: ".abs_section_fd" + _SPI2DR +SECTION: ".abs_section_fb" + _SPI2SR +SECTION: ".abs_section_34" + _SYNR +SECTION: ".abs_section_48" + _TCTL1 +SECTION: ".abs_section_49" + _TCTL2 +SECTION: ".abs_section_4a" + _TCTL3 +SECTION: ".abs_section_4b" + _TCTL4 +SECTION: ".abs_section_4e" + _TFLG1 +SECTION: ".abs_section_4f" + _TFLG2 +SECTION: ".abs_section_4c" + _TIE +SECTION: ".abs_section_6d" + _TIMTST +SECTION: ".abs_section_40" + _TIOS +SECTION: ".abs_section_46" + _TSCR1 +SECTION: ".abs_section_4d" + _TSCR2 +SECTION: ".abs_section_47" + _TTOV +SECTION: ".abs_section_256" + _WOMM +SECTION: ".abs_section_24e" + _WOMS +SECTION: ".abs_section_82" + _ATD0CTL23 +SECTION: ".abs_section_84" + _ATD0CTL45 +SECTION: ".abs_section_90" + _ATD0DR0 +SECTION: ".abs_section_92" + _ATD0DR1 +SECTION: ".abs_section_94" + _ATD0DR2 +SECTION: ".abs_section_96" + _ATD0DR3 +SECTION: ".abs_section_98" + _ATD0DR4 +SECTION: ".abs_section_9a" + _ATD0DR5 +SECTION: ".abs_section_9c" + _ATD0DR6 +SECTION: ".abs_section_9e" + _ATD0DR7 +SECTION: ".abs_section_122" + _ATD1CTL23 +SECTION: ".abs_section_124" + _ATD1CTL45 +SECTION: ".abs_section_130" + _ATD1DR0 +SECTION: ".abs_section_132" + _ATD1DR1 +SECTION: ".abs_section_134" + _ATD1DR2 +SECTION: ".abs_section_136" + _ATD1DR3 +SECTION: ".abs_section_138" + _ATD1DR4 +SECTION: ".abs_section_13a" + _ATD1DR5 +SECTION: ".abs_section_13c" + _ATD1DR6 +SECTION: ".abs_section_13e" + _ATD1DR7 +SECTION: ".abs_section_2" + _DDRAB +SECTION: ".abs_section_76" + _MCCNT +SECTION: ".abs_section_74" + _PA10H +SECTION: ".abs_section_72" + _PA32H +SECTION: ".abs_section_64" + _PACN10 +SECTION: ".abs_section_62" + _PACN32 +SECTION: ".abs_section_0" + _PORTAB +SECTION: ".abs_section_ac" + _PWMCNT01 +SECTION: ".abs_section_ae" + _PWMCNT23 +SECTION: ".abs_section_b0" + _PWMCNT45 +SECTION: ".abs_section_b2" + _PWMCNT67 +SECTION: ".abs_section_bc" + _PWMDTY01 +SECTION: ".abs_section_be" + _PWMDTY23 +SECTION: ".abs_section_c0" + _PWMDTY45 +SECTION: ".abs_section_c2" + _PWMDTY67 +SECTION: ".abs_section_b4" + _PWMPER01 +SECTION: ".abs_section_b6" + _PWMPER23 +SECTION: ".abs_section_b8" + _PWMPER45 +SECTION: ".abs_section_ba" + _PWMPER67 +SECTION: ".abs_section_c8" + _SCI0BD +SECTION: ".abs_section_d0" + _SCI1BD +SECTION: ".abs_section_50" + _TC0 +SECTION: ".abs_section_78" + _TC0H +SECTION: ".abs_section_52" + _TC1 +SECTION: ".abs_section_7a" + _TC1H +SECTION: ".abs_section_54" + _TC2 +SECTION: ".abs_section_7c" + _TC2H +SECTION: ".abs_section_56" + _TC3 +SECTION: ".abs_section_7e" + _TC3H +SECTION: ".abs_section_58" + _TC4 +SECTION: ".abs_section_5a" + _TC5 +SECTION: ".abs_section_5c" + _TC6 +SECTION: ".abs_section_5e" + _TC7 +SECTION: ".abs_section_44" + _TCNT +SECTION: ".abs_section_ff80" + _vect +SECTION: "TickTimer_DATA" + CmpHighVal +SECTION: "Byte1_DATA" + Byte1_Table +SECTION: "COM0_DATA" + COM0_PrescHigh.1 SerFlag PrescHigh NumMode +SECTION: "ROM_PAGE31_524" + xSerialGetChar xSerialPutChar xTaskCreate vTaskDelete vTaskDelayUntil + vTaskDelay uxTaskPriorityGet +SECTION: "ROM_PAGE32_525" + vTaskPrioritySet vTaskSuspend vTaskResume vTaskStartScheduler + vTaskSuspendAll xTaskResumeAll xTaskGetTickCount uxTaskGetNumberOfTasks +SECTION: "ROM_PAGE33_526" + vTaskIncrementTick vTaskSwitchContext vTaskPlaceOnEventList + xTaskRemoveFromEventList prvIdleTask prvInitialiseTCBVariables + prvInitialiseTaskLists +SECTION: "ROM_PAGE34_527" + prvCheckTasksWaitingTermination prvAllocateTCBAndStack prvDeleteTCB + xQueueCreate xQueueSend xQueueSendFromISR +SECTION: "ROM_PAGE35_528" + xQueueReceive xQueueReceiveFromISR uxQueueMessagesWaiting prvUnlockQueue + prvIsQueueEmpty prvIsQueueFull vListInitialise vListInitialiseItem + vListInsertEnd +SECTION: "ROM_PAGE36_529" + vListInsert vListRemove pvPortMalloc vPortFree vStartLEDFlashTasks + vLEDFlashTask +SECTION: "ROM_PAGE37_530" + vStartDynamicPriorityTasks vLimitedIncrementTask vContinuousIncrementTask + vCounterControlTask vQueueSendWhenSuspendedTask + vQueueReceiveWhenSuspendedTask xAreDynamicPriorityTasksStillRunning +SECTION: "ROM_PAGE38_531" + vStartPolledQueueTasks vPolledQueueProducer vPolledQueueConsumer + xArePollingQueuesStillRunning PE_Timer_LngHi1 vAltStartComTestTasks + vComTxTask +SECTION: "ROM_PAGE39_532" + vComRxTask xAreComTestTasksStillRunning pxPortInitialiseStack + xPortStartScheduler vStartIntegerMathTasks vCompeteingIntMathTask + xAreIntegerMathsTaskStillRunning +SECTION: "ROM_PAGE3A_533" + vStartBlockingQueueTasks vBlockingQueueProducer vBlockingQueueConsumer + xAreBlockingQueuesStillRunning vCreateSuicidalTasks +SECTION: "ROM_PAGE3B_534" + vSuicidalTask vCreateTasks xIsCreateTaskStillRunning + +********************************************************************************************* +OBJECT LIST SORTED BY ADDRESS + Name Addr hSize dSize Ref Section RLIB +--------------------------------------------------------------------------------------------- + _PORTAB 0 2 2 6 .abs_section_0 + _DDRAB 2 2 2 1 .abs_section_2 + _PORTE 8 1 1 0 .abs_section_8 + _DDRE 9 1 1 0 .abs_section_9 + _PEAR A 1 1 0 .abs_section_a + _MODE B 1 1 0 .abs_section_b + _PUCR C 1 1 0 .abs_section_c + _RDRIV D 1 1 0 .abs_section_d + _EBICTL E 1 1 0 .abs_section_e + _INITRM 10 1 1 1 .abs_section_10 + _INITRG 11 1 1 0 .abs_section_11 + _INITEE 12 1 1 1 .abs_section_12 + _MISC 13 1 1 1 .abs_section_13 + _MTST0 14 1 1 0 .abs_section_14 + _ITCR 15 1 1 0 .abs_section_15 + _ITEST 16 1 1 0 .abs_section_16 + _MTST1 17 1 1 0 .abs_section_17 + _PARTIDH 1A 1 1 0 .abs_section_1a + _PARTIDL 1B 1 1 0 .abs_section_1b + _MEMSIZ0 1C 1 1 0 .abs_section_1c + _MEMSIZ1 1D 1 1 0 .abs_section_1d + _INTCR 1E 1 1 1 .abs_section_1e + _HPRIO 1F 1 1 0 .abs_section_1f + _BKPCT0 28 1 1 0 .abs_section_28 + _BKPCT1 29 1 1 0 .abs_section_29 + _BKP0X 2A 1 1 0 .abs_section_2a + _BKP0H 2B 1 1 0 .abs_section_2b + _BKP0L 2C 1 1 0 .abs_section_2c + _BKP1X 2D 1 1 0 .abs_section_2d + _BKP1H 2E 1 1 0 .abs_section_2e + _BKP1L 2F 1 1 0 .abs_section_2f + _PPAGE 30 1 1 0 .abs_section_30 + _PORTK 32 1 1 0 .abs_section_32 + _DDRK 33 1 1 0 .abs_section_33 + _SYNR 34 1 1 1 .abs_section_34 + _REFDV 35 1 1 1 .abs_section_35 + _CTFLG 36 1 1 0 .abs_section_36 + _CRGFLG 37 1 1 1 .abs_section_37 + _CRGINT 38 1 1 0 .abs_section_38 + _CLKSEL 39 1 1 3 .abs_section_39 + _PLLCTL 3A 1 1 3 .abs_section_3a + _RTICTL 3B 1 1 0 .abs_section_3b + _COPCTL 3C 1 1 0 .abs_section_3c + _FORBYP 3D 1 1 0 .abs_section_3d + _CTCTL 3E 1 1 0 .abs_section_3e + _ARMCOP 3F 1 1 0 .abs_section_3f + _TIOS 40 1 1 1 .abs_section_40 + _CFORC 41 1 1 0 .abs_section_41 + _OC7M 42 1 1 0 .abs_section_42 + _OC7D 43 1 1 0 .abs_section_43 + _TCNT 44 2 2 0 .abs_section_44 + _TSCR1 46 1 1 3 .abs_section_46 + _TTOV 47 1 1 1 .abs_section_47 + _TCTL1 48 1 1 1 .abs_section_48 + _TCTL2 49 1 1 1 .abs_section_49 + _TCTL3 4A 1 1 0 .abs_section_4a + _TCTL4 4B 1 1 0 .abs_section_4b + _TIE 4C 1 1 3 .abs_section_4c + _TSCR2 4D 1 1 5 .abs_section_4d + _TFLG1 4E 1 1 3 .abs_section_4e + _TFLG2 4F 1 1 0 .abs_section_4f + _TC0 50 2 2 2 .abs_section_50 + _TC1 52 2 2 0 .abs_section_52 + _TC2 54 2 2 0 .abs_section_54 + _TC3 56 2 2 0 .abs_section_56 + _TC4 58 2 2 0 .abs_section_58 + _TC5 5A 2 2 0 .abs_section_5a + _TC6 5C 2 2 0 .abs_section_5c + _TC7 5E 2 2 2 .abs_section_5e + _PACTL 60 1 1 0 .abs_section_60 + _PAFLG 61 1 1 0 .abs_section_61 + _PACN32 62 2 2 0 .abs_section_62 + _PACN10 64 2 2 0 .abs_section_64 + _MCCTL 66 1 1 1 .abs_section_66 + _MCFLG 67 1 1 0 .abs_section_67 + _ICPAR 68 1 1 0 .abs_section_68 + _DLYCT 69 1 1 0 .abs_section_69 + _ICOVW 6A 1 1 0 .abs_section_6a + _ICSYS 6B 1 1 1 .abs_section_6b + _TIMTST 6D 1 1 0 .abs_section_6d + _PBCTL 70 1 1 0 .abs_section_70 + _PBFLG 71 1 1 0 .abs_section_71 + _PA32H 72 2 2 0 .abs_section_72 + _PA10H 74 2 2 0 .abs_section_74 + _MCCNT 76 2 2 0 .abs_section_76 + _TC0H 78 2 2 0 .abs_section_78 + _TC1H 7A 2 2 0 .abs_section_7a + _TC2H 7C 2 2 0 .abs_section_7c + _TC3H 7E 2 2 0 .abs_section_7e + _ATD0CTL23 82 2 2 0 .abs_section_82 + _ATD0CTL45 84 2 2 0 .abs_section_84 + _ATD0STAT0 86 1 1 0 .abs_section_86 + _ATD0STAT1 8B 1 1 0 .abs_section_8b + _ATD0DIEN 8D 1 1 0 .abs_section_8d + _PORTAD0 8F 1 1 0 .abs_section_8f + _ATD0DR0 90 2 2 0 .abs_section_90 + _ATD0DR1 92 2 2 0 .abs_section_92 + _ATD0DR2 94 2 2 0 .abs_section_94 + _ATD0DR3 96 2 2 0 .abs_section_96 + _ATD0DR4 98 2 2 0 .abs_section_98 + _ATD0DR5 9A 2 2 0 .abs_section_9a + _ATD0DR6 9C 2 2 0 .abs_section_9c + _ATD0DR7 9E 2 2 0 .abs_section_9e + _PWME A0 1 1 0 .abs_section_a0 + _PWMPOL A1 1 1 0 .abs_section_a1 + _PWMCLK A2 1 1 0 .abs_section_a2 + _PWMPRCLK A3 1 1 0 .abs_section_a3 + _PWMCAE A4 1 1 0 .abs_section_a4 + _PWMCTL A5 1 1 1 .abs_section_a5 + _PWMSCLA A8 1 1 0 .abs_section_a8 + _PWMSCLB A9 1 1 0 .abs_section_a9 + _PWMCNT01 AC 2 2 0 .abs_section_ac + _PWMCNT23 AE 2 2 0 .abs_section_ae + _PWMCNT45 B0 2 2 0 .abs_section_b0 + _PWMCNT67 B2 2 2 0 .abs_section_b2 + _PWMPER01 B4 2 2 0 .abs_section_b4 + _PWMPER23 B6 2 2 0 .abs_section_b6 + _PWMPER45 B8 2 2 0 .abs_section_b8 + _PWMPER67 BA 2 2 0 .abs_section_ba + _PWMDTY01 BC 2 2 0 .abs_section_bc + _PWMDTY23 BE 2 2 0 .abs_section_be + _PWMDTY45 C0 2 2 0 .abs_section_c0 + _PWMDTY67 C2 2 2 0 .abs_section_c2 + _PWMSDN C4 1 1 1 .abs_section_c4 + _SCI0BD C8 2 2 2 .abs_section_c8 + _SCI0CR1 CA 1 1 1 .abs_section_ca + _SCI0CR2 CB 1 1 7 .abs_section_cb + _SCI0SR1 CC 1 1 2 .abs_section_cc + _SCI0SR2 CD 1 1 1 .abs_section_cd + _SCI0DRH CE 1 1 0 .abs_section_ce + _SCI0DRL CF 1 1 3 .abs_section_cf + _SCI1BD D0 2 2 0 .abs_section_d0 + _SCI1CR1 D2 1 1 0 .abs_section_d2 + _SCI1CR2 D3 1 1 0 .abs_section_d3 + _SCI1SR1 D4 1 1 0 .abs_section_d4 + _SCI1SR2 D5 1 1 0 .abs_section_d5 + _SCI1DRH D6 1 1 0 .abs_section_d6 + _SCI1DRL D7 1 1 0 .abs_section_d7 + _SPI0CR1 D8 1 1 0 .abs_section_d8 + _SPI0CR2 D9 1 1 0 .abs_section_d9 + _SPI0BR DA 1 1 0 .abs_section_da + _SPI0SR DB 1 1 0 .abs_section_db + _SPI0DR DD 1 1 0 .abs_section_dd + _IBAD E0 1 1 0 .abs_section_e0 + _IBFD E1 1 1 0 .abs_section_e1 + _IBCR E2 1 1 0 .abs_section_e2 + _IBSR E3 1 1 0 .abs_section_e3 + _IBDR E4 1 1 0 .abs_section_e4 + _DLCBCR1 E8 1 1 0 .abs_section_e8 + _DLCBSVR E9 1 1 0 .abs_section_e9 + _DLCBCR2 EA 1 1 0 .abs_section_ea + _DLCBDR EB 1 1 0 .abs_section_eb + _DLCBARD EC 1 1 0 .abs_section_ec + _DLCBRSR ED 1 1 0 .abs_section_ed + _DLCSCR EE 1 1 0 .abs_section_ee + _SPI1CR1 F0 1 1 0 .abs_section_f0 + _SPI1CR2 F1 1 1 0 .abs_section_f1 + _SPI1BR F2 1 1 0 .abs_section_f2 + _SPI1SR F3 1 1 0 .abs_section_f3 + _SPI1DR F5 1 1 0 .abs_section_f5 + _SPI2CR1 F8 1 1 0 .abs_section_f8 + _SPI2CR2 F9 1 1 0 .abs_section_f9 + _SPI2BR FA 1 1 0 .abs_section_fa + _SPI2SR FB 1 1 0 .abs_section_fb + _SPI2DR FD 1 1 0 .abs_section_fd + _FCLKDIV 100 1 1 0 .abs_section_100 + _FSEC 101 1 1 0 .abs_section_101 + _FCNFG 103 1 1 0 .abs_section_103 + _FPROT 104 1 1 0 .abs_section_104 + _FSTAT 105 1 1 0 .abs_section_105 + _FCMD 106 1 1 0 .abs_section_106 + _ECLKDIV 110 1 1 0 .abs_section_110 + _ECNFG 113 1 1 0 .abs_section_113 + _EPROT 114 1 1 0 .abs_section_114 + _ESTAT 115 1 1 0 .abs_section_115 + _ECMD 116 1 1 0 .abs_section_116 + _ATD1CTL23 122 2 2 0 .abs_section_122 + _ATD1CTL45 124 2 2 0 .abs_section_124 + _ATD1STAT0 126 1 1 0 .abs_section_126 + _ATD1STAT1 12B 1 1 0 .abs_section_12b + _ATD1DIEN 12D 1 1 0 .abs_section_12d + _PORTAD1 12F 1 1 0 .abs_section_12f + _ATD1DR0 130 2 2 0 .abs_section_130 + _ATD1DR1 132 2 2 0 .abs_section_132 + _ATD1DR2 134 2 2 0 .abs_section_134 + _ATD1DR3 136 2 2 0 .abs_section_136 + _ATD1DR4 138 2 2 0 .abs_section_138 + _ATD1DR5 13A 2 2 0 .abs_section_13a + _ATD1DR6 13C 2 2 0 .abs_section_13c + _ATD1DR7 13E 2 2 0 .abs_section_13e + _CAN0CTL0 140 1 1 0 .abs_section_140 + _CAN0CTL1 141 1 1 0 .abs_section_141 + _CAN0BTR0 142 1 1 0 .abs_section_142 + _CAN0BTR1 143 1 1 0 .abs_section_143 + _CAN0RFLG 144 1 1 0 .abs_section_144 + _CAN0RIER 145 1 1 0 .abs_section_145 + _CAN0TFLG 146 1 1 0 .abs_section_146 + _CAN0TIER 147 1 1 0 .abs_section_147 + _CAN0TARQ 148 1 1 0 .abs_section_148 + _CAN0TAAK 149 1 1 0 .abs_section_149 + _CAN0TBSEL 14A 1 1 0 .abs_section_14a + _CAN0IDAC 14B 1 1 0 .abs_section_14b + _CAN0RXERR 14E 1 1 0 .abs_section_14e + _CAN0TXERR 14F 1 1 0 .abs_section_14f + _CAN0IDAR0 150 1 1 0 .abs_section_150 + _CAN0IDAR1 151 1 1 0 .abs_section_151 + _CAN0IDAR2 152 1 1 0 .abs_section_152 + _CAN0IDAR3 153 1 1 0 .abs_section_153 + _CAN0IDMR0 154 1 1 0 .abs_section_154 + _CAN0IDMR1 155 1 1 0 .abs_section_155 + _CAN0IDMR2 156 1 1 0 .abs_section_156 + _CAN0IDMR3 157 1 1 0 .abs_section_157 + _CAN0IDAR4 158 1 1 0 .abs_section_158 + _CAN0IDAR5 159 1 1 0 .abs_section_159 + _CAN0IDAR6 15A 1 1 0 .abs_section_15a + _CAN0IDAR7 15B 1 1 0 .abs_section_15b + _CAN0IDMR4 15C 1 1 0 .abs_section_15c + _CAN0IDMR5 15D 1 1 0 .abs_section_15d + _CAN0IDMR6 15E 1 1 0 .abs_section_15e + _CAN0IDMR7 15F 1 1 0 .abs_section_15f + _CAN0RXIDR0 160 1 1 0 .abs_section_160 + _CAN0RXIDR1 161 1 1 0 .abs_section_161 + _CAN0RXIDR2 162 1 1 0 .abs_section_162 + _CAN0RXIDR3 163 1 1 0 .abs_section_163 + _CAN0RXDSR0 164 1 1 0 .abs_section_164 + _CAN0RXDSR1 165 1 1 0 .abs_section_165 + _CAN0RXDSR2 166 1 1 0 .abs_section_166 + _CAN0RXDSR3 167 1 1 0 .abs_section_167 + _CAN0RXDSR4 168 1 1 0 .abs_section_168 + _CAN0RXDSR5 169 1 1 0 .abs_section_169 + _CAN0RXDSR6 16A 1 1 0 .abs_section_16a + _CAN0RXDSR7 16B 1 1 0 .abs_section_16b + _CAN0RXDLR 16C 1 1 0 .abs_section_16c + _CAN0TXIDR0 170 1 1 0 .abs_section_170 + _CAN0TXIDR1 171 1 1 0 .abs_section_171 + _CAN0TXIDR2 172 1 1 0 .abs_section_172 + _CAN0TXIDR3 173 1 1 0 .abs_section_173 + _CAN0TXDSR0 174 1 1 0 .abs_section_174 + _CAN0TXDSR1 175 1 1 0 .abs_section_175 + _CAN0TXDSR2 176 1 1 0 .abs_section_176 + _CAN0TXDSR3 177 1 1 0 .abs_section_177 + _CAN0TXDSR4 178 1 1 0 .abs_section_178 + _CAN0TXDSR5 179 1 1 0 .abs_section_179 + _CAN0TXDSR6 17A 1 1 0 .abs_section_17a + _CAN0TXDSR7 17B 1 1 0 .abs_section_17b + _CAN0TXDLR 17C 1 1 0 .abs_section_17c + _CAN0TXTBPR 17F 1 1 0 .abs_section_17f + _CAN1CTL0 180 1 1 0 .abs_section_180 + _CAN1CTL1 181 1 1 0 .abs_section_181 + _CAN1BTR0 182 1 1 0 .abs_section_182 + _CAN1BTR1 183 1 1 0 .abs_section_183 + _CAN1RFLG 184 1 1 0 .abs_section_184 + _CAN1RIER 185 1 1 0 .abs_section_185 + _CAN1TFLG 186 1 1 0 .abs_section_186 + _CAN1TIER 187 1 1 0 .abs_section_187 + _CAN1TARQ 188 1 1 0 .abs_section_188 + _CAN1TAAK 189 1 1 0 .abs_section_189 + _CAN1TBSEL 18A 1 1 0 .abs_section_18a + _CAN1IDAC 18B 1 1 0 .abs_section_18b + _CAN1RXERR 18E 1 1 0 .abs_section_18e + _CAN1TXERR 18F 1 1 0 .abs_section_18f + _CAN1IDAR0 190 1 1 0 .abs_section_190 + _CAN1IDAR1 191 1 1 0 .abs_section_191 + _CAN1IDAR2 192 1 1 0 .abs_section_192 + _CAN1IDAR3 193 1 1 0 .abs_section_193 + _CAN1IDMR0 194 1 1 0 .abs_section_194 + _CAN1IDMR1 195 1 1 0 .abs_section_195 + _CAN1IDMR2 196 1 1 0 .abs_section_196 + _CAN1IDMR3 197 1 1 0 .abs_section_197 + _CAN1IDAR4 198 1 1 0 .abs_section_198 + _CAN1IDAR5 199 1 1 0 .abs_section_199 + _CAN1IDAR6 19A 1 1 0 .abs_section_19a + _CAN1IDAR7 19B 1 1 0 .abs_section_19b + _CAN1IDMR4 19C 1 1 0 .abs_section_19c + _CAN1IDMR5 19D 1 1 0 .abs_section_19d + _CAN1IDMR6 19E 1 1 0 .abs_section_19e + _CAN1IDMR7 19F 1 1 0 .abs_section_19f + _CAN1RXIDR0 1A0 1 1 0 .abs_section_1a0 + _CAN1RXIDR1 1A1 1 1 0 .abs_section_1a1 + _CAN1RXIDR2 1A2 1 1 0 .abs_section_1a2 + _CAN1RXIDR3 1A3 1 1 0 .abs_section_1a3 + _CAN1RXDSR0 1A4 1 1 0 .abs_section_1a4 + _CAN1RXDSR1 1A5 1 1 0 .abs_section_1a5 + _CAN1RXDSR2 1A6 1 1 0 .abs_section_1a6 + _CAN1RXDSR3 1A7 1 1 0 .abs_section_1a7 + _CAN1RXDSR4 1A8 1 1 0 .abs_section_1a8 + _CAN1RXDSR5 1A9 1 1 0 .abs_section_1a9 + _CAN1RXDSR6 1AA 1 1 0 .abs_section_1aa + _CAN1RXDSR7 1AB 1 1 0 .abs_section_1ab + _CAN1RXDLR 1AC 1 1 0 .abs_section_1ac + _CAN1TXIDR0 1B0 1 1 0 .abs_section_1b0 + _CAN1TXIDR1 1B1 1 1 0 .abs_section_1b1 + _CAN1TXIDR2 1B2 1 1 0 .abs_section_1b2 + _CAN1TXIDR3 1B3 1 1 0 .abs_section_1b3 + _CAN1TXDSR0 1B4 1 1 0 .abs_section_1b4 + _CAN1TXDSR1 1B5 1 1 0 .abs_section_1b5 + _CAN1TXDSR2 1B6 1 1 0 .abs_section_1b6 + _CAN1TXDSR3 1B7 1 1 0 .abs_section_1b7 + _CAN1TXDSR4 1B8 1 1 0 .abs_section_1b8 + _CAN1TXDSR5 1B9 1 1 0 .abs_section_1b9 + _CAN1TXDSR6 1BA 1 1 0 .abs_section_1ba + _CAN1TXDSR7 1BB 1 1 0 .abs_section_1bb + _CAN1TXDLR 1BC 1 1 0 .abs_section_1bc + _CAN1TXTBPR 1BF 1 1 0 .abs_section_1bf + _CAN2CTL0 1C0 1 1 0 .abs_section_1c0 + _CAN2CTL1 1C1 1 1 0 .abs_section_1c1 + _CAN2BTR0 1C2 1 1 0 .abs_section_1c2 + _CAN2BTR1 1C3 1 1 0 .abs_section_1c3 + _CAN2RFLG 1C4 1 1 0 .abs_section_1c4 + _CAN2RIER 1C5 1 1 0 .abs_section_1c5 + _CAN2TFLG 1C6 1 1 0 .abs_section_1c6 + _CAN2TIER 1C7 1 1 0 .abs_section_1c7 + _CAN2TARQ 1C8 1 1 0 .abs_section_1c8 + _CAN2TAAK 1C9 1 1 0 .abs_section_1c9 + _CAN2TBSEL 1CA 1 1 0 .abs_section_1ca + _CAN2IDAC 1CB 1 1 0 .abs_section_1cb + _CAN2RXERR 1CE 1 1 0 .abs_section_1ce + _CAN2TXERR 1CF 1 1 0 .abs_section_1cf + _CAN2IDAR0 1D0 1 1 0 .abs_section_1d0 + _CAN2IDAR1 1D1 1 1 0 .abs_section_1d1 + _CAN2IDAR2 1D2 1 1 0 .abs_section_1d2 + _CAN2IDAR3 1D3 1 1 0 .abs_section_1d3 + _CAN2IDMR0 1D4 1 1 0 .abs_section_1d4 + _CAN2IDMR1 1D5 1 1 0 .abs_section_1d5 + _CAN2IDMR2 1D6 1 1 0 .abs_section_1d6 + _CAN2IDMR3 1D7 1 1 0 .abs_section_1d7 + _CAN2IDAR4 1D8 1 1 0 .abs_section_1d8 + _CAN2IDAR5 1D9 1 1 0 .abs_section_1d9 + _CAN2IDAR6 1DA 1 1 0 .abs_section_1da + _CAN2IDAR7 1DB 1 1 0 .abs_section_1db + _CAN2IDMR4 1DC 1 1 0 .abs_section_1dc + _CAN2IDMR5 1DD 1 1 0 .abs_section_1dd + _CAN2IDMR6 1DE 1 1 0 .abs_section_1de + _CAN2IDMR7 1DF 1 1 0 .abs_section_1df + _CAN2RXIDR0 1E0 1 1 0 .abs_section_1e0 + _CAN2RXIDR1 1E1 1 1 0 .abs_section_1e1 + _CAN2RXIDR2 1E2 1 1 0 .abs_section_1e2 + _CAN2RXIDR3 1E3 1 1 0 .abs_section_1e3 + _CAN2RXDSR0 1E4 1 1 0 .abs_section_1e4 + _CAN2RXDSR1 1E5 1 1 0 .abs_section_1e5 + _CAN2RXDSR2 1E6 1 1 0 .abs_section_1e6 + _CAN2RXDSR3 1E7 1 1 0 .abs_section_1e7 + _CAN2RXDSR4 1E8 1 1 0 .abs_section_1e8 + _CAN2RXDSR5 1E9 1 1 0 .abs_section_1e9 + _CAN2RXDSR6 1EA 1 1 0 .abs_section_1ea + _CAN2RXDSR7 1EB 1 1 0 .abs_section_1eb + _CAN2RXDLR 1EC 1 1 0 .abs_section_1ec + _CAN2TXIDR0 1F0 1 1 0 .abs_section_1f0 + _CAN2TXIDR1 1F1 1 1 0 .abs_section_1f1 + _CAN2TXIDR2 1F2 1 1 0 .abs_section_1f2 + _CAN2TXIDR3 1F3 1 1 0 .abs_section_1f3 + _CAN2TXDSR0 1F4 1 1 0 .abs_section_1f4 + _CAN2TXDSR1 1F5 1 1 0 .abs_section_1f5 + _CAN2TXDSR2 1F6 1 1 0 .abs_section_1f6 + _CAN2TXDSR3 1F7 1 1 0 .abs_section_1f7 + _CAN2TXDSR4 1F8 1 1 0 .abs_section_1f8 + _CAN2TXDSR5 1F9 1 1 0 .abs_section_1f9 + _CAN2TXDSR6 1FA 1 1 0 .abs_section_1fa + _CAN2TXDSR7 1FB 1 1 0 .abs_section_1fb + _CAN2TXDLR 1FC 1 1 0 .abs_section_1fc + _CAN2TXTBPR 1FF 1 1 0 .abs_section_1ff + _CAN3CTL0 200 1 1 0 .abs_section_200 + _CAN3CTL1 201 1 1 0 .abs_section_201 + _CAN3BTR0 202 1 1 0 .abs_section_202 + _CAN3BTR1 203 1 1 0 .abs_section_203 + _CAN3RFLG 204 1 1 0 .abs_section_204 + _CAN3RIER 205 1 1 0 .abs_section_205 + _CAN3TFLG 206 1 1 0 .abs_section_206 + _CAN3TIER 207 1 1 0 .abs_section_207 + _CAN3TARQ 208 1 1 0 .abs_section_208 + _CAN3TAAK 209 1 1 0 .abs_section_209 + _CAN3TBSEL 20A 1 1 0 .abs_section_20a + _CAN3IDAC 20B 1 1 0 .abs_section_20b + _CAN3RXERR 20E 1 1 0 .abs_section_20e + _CAN3TXERR 20F 1 1 0 .abs_section_20f + _CAN3IDAR0 210 1 1 0 .abs_section_210 + _CAN3IDAR1 211 1 1 0 .abs_section_211 + _CAN3IDAR2 212 1 1 0 .abs_section_212 + _CAN3IDAR3 213 1 1 0 .abs_section_213 + _CAN3IDMR0 214 1 1 0 .abs_section_214 + _CAN3IDMR1 215 1 1 0 .abs_section_215 + _CAN3IDMR2 216 1 1 0 .abs_section_216 + _CAN3IDMR3 217 1 1 0 .abs_section_217 + _CAN3IDAR4 218 1 1 0 .abs_section_218 + _CAN3IDAR5 219 1 1 0 .abs_section_219 + _CAN3IDAR6 21A 1 1 0 .abs_section_21a + _CAN3IDAR7 21B 1 1 0 .abs_section_21b + _CAN3IDMR4 21C 1 1 0 .abs_section_21c + _CAN3IDMR5 21D 1 1 0 .abs_section_21d + _CAN3IDMR6 21E 1 1 0 .abs_section_21e + _CAN3IDMR7 21F 1 1 0 .abs_section_21f + _CAN3RXIDR0 220 1 1 0 .abs_section_220 + _CAN3RXIDR1 221 1 1 0 .abs_section_221 + _CAN3RXIDR2 222 1 1 0 .abs_section_222 + _CAN3RXIDR3 223 1 1 0 .abs_section_223 + _CAN3RXDSR0 224 1 1 0 .abs_section_224 + _CAN3RXDSR1 225 1 1 0 .abs_section_225 + _CAN3RXDSR2 226 1 1 0 .abs_section_226 + _CAN3RXDSR3 227 1 1 0 .abs_section_227 + _CAN3RXDSR4 228 1 1 0 .abs_section_228 + _CAN3RXDSR5 229 1 1 0 .abs_section_229 + _CAN3RXDSR6 22A 1 1 0 .abs_section_22a + _CAN3RXDSR7 22B 1 1 0 .abs_section_22b + _CAN3RXDLR 22C 1 1 0 .abs_section_22c + _CAN3TXIDR0 230 1 1 0 .abs_section_230 + _CAN3TXIDR1 231 1 1 0 .abs_section_231 + _CAN3TXIDR2 232 1 1 0 .abs_section_232 + _CAN3TXIDR3 233 1 1 0 .abs_section_233 + _CAN3TXDSR0 234 1 1 0 .abs_section_234 + _CAN3TXDSR1 235 1 1 0 .abs_section_235 + _CAN3TXDSR2 236 1 1 0 .abs_section_236 + _CAN3TXDSR3 237 1 1 0 .abs_section_237 + _CAN3TXDSR4 238 1 1 0 .abs_section_238 + _CAN3TXDSR5 239 1 1 0 .abs_section_239 + _CAN3TXDSR6 23A 1 1 0 .abs_section_23a + _CAN3TXDSR7 23B 1 1 0 .abs_section_23b + _CAN3TXDLR 23C 1 1 0 .abs_section_23c + _CAN3TXTBPR 23F 1 1 0 .abs_section_23f + _PTT 240 1 1 0 .abs_section_240 + _PTIT 241 1 1 0 .abs_section_241 + _DDRT 242 1 1 0 .abs_section_242 + _RDRT 243 1 1 0 .abs_section_243 + _PERT 244 1 1 0 .abs_section_244 + _PPST 245 1 1 0 .abs_section_245 + _PTS 248 1 1 1 .abs_section_248 + _PTIS 249 1 1 0 .abs_section_249 + _DDRS 24A 1 1 2 .abs_section_24a + _RDRS 24B 1 1 0 .abs_section_24b + _PERS 24C 1 1 0 .abs_section_24c + _PPSS 24D 1 1 0 .abs_section_24d + _WOMS 24E 1 1 0 .abs_section_24e + _PTM 250 1 1 0 .abs_section_250 + _PTIM 251 1 1 0 .abs_section_251 + _DDRM 252 1 1 0 .abs_section_252 + _RDRM 253 1 1 0 .abs_section_253 + _PERM 254 1 1 0 .abs_section_254 + _PPSM 255 1 1 0 .abs_section_255 + _WOMM 256 1 1 0 .abs_section_256 + _MODRR 257 1 1 0 .abs_section_257 + _PTP 258 1 1 0 .abs_section_258 + _PTIP 259 1 1 0 .abs_section_259 + _DDRP 25A 1 1 0 .abs_section_25a + _RDRP 25B 1 1 0 .abs_section_25b + _PERP 25C 1 1 0 .abs_section_25c + _PPSP 25D 1 1 0 .abs_section_25d + _PIEP 25E 1 1 0 .abs_section_25e + _PIFP 25F 1 1 0 .abs_section_25f + _PTH 260 1 1 0 .abs_section_260 + _PTIH 261 1 1 0 .abs_section_261 + _DDRH 262 1 1 0 .abs_section_262 + _RDRH 263 1 1 0 .abs_section_263 + _PERH 264 1 1 0 .abs_section_264 + _PPSH 265 1 1 0 .abs_section_265 + _PIEH 266 1 1 0 .abs_section_266 + _PIFH 267 1 1 0 .abs_section_267 + _PTJ 268 1 1 0 .abs_section_268 + _PTIJ 269 1 1 0 .abs_section_269 + _DDRJ 26A 1 1 0 .abs_section_26a + _RDRJ 26B 1 1 0 .abs_section_26b + _PERJ 26C 1 1 0 .abs_section_26c + _PPSJ 26D 1 1 0 .abs_section_26d + _PIEJ 26E 1 1 0 .abs_section_26e + _PIFJ 26F 1 1 0 .abs_section_26f + _CAN4CTL0 280 1 1 0 .abs_section_280 + _CAN4CTL1 281 1 1 0 .abs_section_281 + _CAN4BTR0 282 1 1 0 .abs_section_282 + _CAN4BTR1 283 1 1 0 .abs_section_283 + _CAN4RFLG 284 1 1 0 .abs_section_284 + _CAN4RIER 285 1 1 0 .abs_section_285 + _CAN4TFLG 286 1 1 0 .abs_section_286 + _CAN4TIER 287 1 1 0 .abs_section_287 + _CAN4TARQ 288 1 1 0 .abs_section_288 + _CAN4TAAK 289 1 1 0 .abs_section_289 + _CAN4TBSEL 28A 1 1 0 .abs_section_28a + _CAN4IDAC 28B 1 1 0 .abs_section_28b + _CAN4RXERR 28E 1 1 0 .abs_section_28e + _CAN4TXERR 28F 1 1 0 .abs_section_28f + _CAN4IDAR0 290 1 1 0 .abs_section_290 + _CAN4IDAR1 291 1 1 0 .abs_section_291 + _CAN4IDAR2 292 1 1 0 .abs_section_292 + _CAN4IDAR3 293 1 1 0 .abs_section_293 + _CAN4IDMR0 294 1 1 0 .abs_section_294 + _CAN4IDMR1 295 1 1 0 .abs_section_295 + _CAN4IDMR2 296 1 1 0 .abs_section_296 + _CAN4IDMR3 297 1 1 0 .abs_section_297 + _CAN4IDAR4 298 1 1 0 .abs_section_298 + _CAN4IDAR5 299 1 1 0 .abs_section_299 + _CAN4IDAR6 29A 1 1 0 .abs_section_29a + _CAN4IDAR7 29B 1 1 0 .abs_section_29b + _CAN4IDMR4 29C 1 1 0 .abs_section_29c + _CAN4IDMR5 29D 1 1 0 .abs_section_29d + _CAN4IDMR6 29E 1 1 0 .abs_section_29e + _CAN4IDMR7 29F 1 1 0 .abs_section_29f + _CAN4RXIDR0 2A0 1 1 0 .abs_section_2a0 + _CAN4RXIDR1 2A1 1 1 0 .abs_section_2a1 + _CAN4RXIDR2 2A2 1 1 0 .abs_section_2a2 + _CAN4RXIDR3 2A3 1 1 0 .abs_section_2a3 + _CAN4RXDSR0 2A4 1 1 0 .abs_section_2a4 + _CAN4RXDSR1 2A5 1 1 0 .abs_section_2a5 + _CAN4RXDSR2 2A6 1 1 0 .abs_section_2a6 + _CAN4RXDSR3 2A7 1 1 0 .abs_section_2a7 + _CAN4RXDSR4 2A8 1 1 0 .abs_section_2a8 + _CAN4RXDSR5 2A9 1 1 0 .abs_section_2a9 + _CAN4RXDSR6 2AA 1 1 0 .abs_section_2aa + _CAN4RXDSR7 2AB 1 1 0 .abs_section_2ab + _CAN4RXDLR 2AC 1 1 0 .abs_section_2ac + _CAN4TXIDR0 2B0 1 1 0 .abs_section_2b0 + _CAN4TXIDR1 2B1 1 1 0 .abs_section_2b1 + _CAN4TXIDR2 2B2 1 1 0 .abs_section_2b2 + _CAN4TXIDR3 2B3 1 1 0 .abs_section_2b3 + _CAN4TXDSR0 2B4 1 1 0 .abs_section_2b4 + _CAN4TXDSR1 2B5 1 1 0 .abs_section_2b5 + _CAN4TXDSR2 2B6 1 1 0 .abs_section_2b6 + _CAN4TXDSR3 2B7 1 1 0 .abs_section_2b7 + _CAN4TXDSR4 2B8 1 1 0 .abs_section_2b8 + _CAN4TXDSR5 2B9 1 1 0 .abs_section_2b9 + _CAN4TXDSR6 2BA 1 1 0 .abs_section_2ba + _CAN4TXDSR7 2BB 1 1 0 .abs_section_2bb + _CAN4TXDLR 2BC 1 1 0 .abs_section_2bc + _CAN4TXTBPR 2BF 1 1 0 .abs_section_2bf + uxCriticalNesting 1000 1 1 101 .data + xLocalError 1001 1 1 2 .bss + xRxedChars 1002 2 2 3 .bss + xCharsForTx 1004 2 2 3 .bss + pxCurrentTCB 1006 2 2 28 .bss + uxTasksDeleted 1008 1 1 3 .bss + uxCurrentNumberOfTasks 1009 1 1 5 .bss + xTickCount 100A 2 2 14 .bss + uxTopUsedPriority 100C 1 1 2 .bss + uxTopReadyPriority 100D 1 1 15 .bss + xSchedulerRunning 100E 1 1 3 .bss + uxSchedulerSuspended 100F 1 1 6 .bss + uxMissedTicks 1010 1 1 4 .bss + uxTaskNumber.1 1011 1 1 2 .bss + pxReadyTasksLists 1012 3C 60 11 .bss + xDelayedTaskList1 104E F 15 2 .bss + xDelayedTaskList2 105D F 15 2 .bss + pxDelayedTaskList 106C 2 2 8 .bss + pxOverflowDelayedTaskList 106E 2 2 6 .bss + xPendingReadyList 1070 F 15 4 .bss + xTasksWaitingTermination 107F F 15 5 .bss + xSuspendedTaskList 108E F 15 2 .bss + xHeapHasBeenInitialised.1 109D 1 1 2 .bss + xHeap 109E 2804 10244 2 .bss + xStart 38A2 4 4 6 .bss + xEnd 38A6 4 4 4 .bss + uxFlashTaskNumber 38AA 1 1 2 .bss + usCheckVariable 38AB 2 2 3 .bss + xSuspendedQueueSendError 38AD 1 1 2 .bss + xSuspendedQueueReceiveError 38AE 1 1 3 .bss + ulValueToSend.6 38AF 4 4 5 .bss + ulExpectedValue.7 38B3 4 4 6 .bss + usLastTaskCheck.9 38B7 2 2 2 .bss + xContinousIncrementHandle 38B9 2 2 5 .bss + xLimitedIncrementHandle 38BB 2 2 2 .bss + ulCounter 38BD 4 4 10 .bss + ulReceivedValue.8 38C1 4 4 3 .bss + xPollingConsumerCount 38C5 1 1 3 .bss + xPollingProducerCount 38C6 1 1 3 .bss + xPolledQueue.1 38C7 2 2 3 .bss + xPort 38C9 2 2 3 .bss + uxBaseLED 38CB 1 1 5 .bss + uxRxLoops 38CC 1 1 3 .bss + xTaskCheck 38CD 1 1 3 .bss + sBlockingConsumerCount 38CE 6 6 4 .bss + sBlockingProducerCount 38D4 6 6 5 .bss + sLastBlockingConsumerCount.7 38DA 6 6 2 .bss + sLastBlockingProducerCount.8 38E0 6 6 2 .bss + usCreationCount 38E6 2 2 4 .bss + uxTasksRunningAtStart 38E8 1 1 4 .bss + usLastCreationCount.6 38E9 2 2 2 .bss + uxTasksRunningNow.7 38EB 1 1 1 .bss + xSuspendedTestQueue 38EC 2 2 3 .common + xCreatedTask1 38EE 2 2 2 .common + xCreatedTask2 38F0 2 2 2 .common + CmpHighVal 38F2 2 2 2 TickTimer_DATA + Byte1_Table 38F4 8 8 2 Byte1_DATA + COM0_PrescHigh.1 38FC 8 8 1 COM0_DATA + SerFlag 3904 2 2 1 COM0_DATA + PrescHigh 3906 2 2 2 COM0_DATA + NumMode 3908 1 1 2 COM0_DATA + _EntryPoint C000 2E 46 1 .init + PE_low_level_init C02E 4E 78 2 .init + STRING.Check.1 C09A 6 6 1 .rodata1 + STRING.IDLE.2 C0A0 5 5 1 .rodata1 + STRING.LEDx.1 C0A5 5 5 1 .rodata1 + STRING.CNT_INC.1 C0AA 8 8 1 .rodata1 + STRING.LIM_INC.2 C0B2 8 8 1 .rodata1 + STRING.C_CTRL.3 C0BA 7 7 1 .rodata1 + STRING.SUSP_TX.4 C0C1 8 8 1 .rodata1 + STRING.SUSP_RX.5 C0C9 8 8 1 .rodata1 + STRING.QConsNB.2 C0D1 8 8 1 .rodata1 + STRING.QProdNB.3 C0D9 8 8 1 .rodata1 + STRING.COMTx.1 C0E1 6 6 1 .rodata1 + STRING.COMRx.2 C0E7 6 6 1 .rodata1 + STRING.IntMath.1 C0ED 8 8 1 .rodata1 + STRING.QConsB1.1 C0F5 8 8 1 .rodata1 + STRING.QProdB2.2 C0FD 8 8 1 .rodata1 + STRING.QProdB3.3 C105 8 8 1 .rodata1 + STRING.QConsB4.4 C10D 8 8 1 .rodata1 + STRING.QProdB5.5 C115 8 8 1 .rodata1 + STRING.QConsB6.6 C11D 8 8 1 .rodata1 + STRING.CREATOR.1 C125 8 8 1 .rodata1 + STRING.SUICIDE1.2 C12D 9 9 1 .rodata1 + STRING.SUICIDE2.3 C136 9 9 1 .rodata1 + STRING.SUICIDE1.4 C13F 9 9 1 .rodata1 + STRING.SUICIDE2.5 C148 9 9 1 .rodata1 + _Startup C151 12 18 1 NON_BANKED + _LCMP C163 19 25 2 NON_BANKED + _LCMP_P C17C 15 21 3 NON_BANKED + _LNEG C191 D 13 2 NON_BANKED + _LINC C19E 5 5 4 NON_BANKED + _LMUL C1A3 27 39 1 NON_BANKED + _lDivMod C1CA E3 227 3 NON_BANKED + _LDIVU C2AD E 14 1 NON_BANKED + _NEG_P C2BB F 15 4 NON_BANKED + _LDIVS C2CA 35 53 2 NON_BANKED + Cpu_Interrupt C2FF 1 1 60 NON_BANKED + vCOM0_ISR C300 59 89 1 NON_BANKED + xBankedStartScheduler C359 1A 26 1 NON_BANKED + vPortYield C373 1D 29 1 NON_BANKED + vPortTickInterrupt C390 25 37 1 NON_BANKED + _BDMSTS FF01 1 1 0 .abs_section_ff01 + _BDMCCR FF06 1 1 0 .abs_section_ff06 + _BDMINR FF07 1 1 0 .abs_section_ff07 + _vect FF80 80 128 0 .abs_section_ff80 + Init 308000 29 41 2 .text + memcpy 308029 26 38 8 .text + memset 30804F 1E 30 2 .text + strncpy 30806D 2D 45 2 .text + main 30809A 9 9 0 .text + vMain 3080A3 52 82 1 .text + vErrorChecks 3080F5 39 57 3 .text + prvCheckOtherTasksAreStillRunning 30812E 50 80 2 .text + vApplicationIdleHook 30817E 70 112 2 .text + vParTestSetLED 3081EE 23 35 4 .text + vParTestToggleLED 308211 14 20 10 .text + xSerialPortInitMinimal 308225 26 38 2 .text + xSerialGetChar 318000 13 19 4 ROM_PAGE31_524 + xSerialPutChar 318013 18 24 2 ROM_PAGE31_524 + xTaskCreate 31802B D5 213 48 ROM_PAGE31_524 + vTaskDelete 318100 4A 74 4 ROM_PAGE31_524 + vTaskDelayUntil 31814A 77 119 6 ROM_PAGE31_524 + vTaskDelay 3181C1 46 70 16 ROM_PAGE31_524 + uxTaskPriorityGet 318207 22 34 2 ROM_PAGE31_524 + vTaskPrioritySet 328000 69 105 4 ROM_PAGE32_525 + vTaskSuspend 328069 47 71 6 ROM_PAGE32_525 + vTaskResume 3280B0 5C 92 6 ROM_PAGE32_525 + vTaskStartScheduler 32810C 31 49 2 ROM_PAGE32_525 + vTaskSuspendAll 32813D 13 19 26 ROM_PAGE32_525 + xTaskResumeAll 328150 9F 159 30 ROM_PAGE32_525 + xTaskGetTickCount 3281EF 17 23 6 ROM_PAGE32_525 + uxTaskGetNumberOfTasks 328206 17 23 4 ROM_PAGE32_525 + vTaskIncrementTick 338000 84 132 4 ROM_PAGE33_526 + vTaskSwitchContext 338084 5B 91 4 ROM_PAGE33_526 + vTaskPlaceOnEventList 3380DF 41 65 4 ROM_PAGE33_526 + xTaskRemoveFromEventList 338120 69 105 8 ROM_PAGE33_526 + prvIdleTask 338189 12 18 3 ROM_PAGE33_526 + prvInitialiseTCBVariables 33819B 4D 77 2 ROM_PAGE33_526 + prvInitialiseTaskLists 3381E8 3C 60 2 ROM_PAGE33_526 + prvCheckTasksWaitingTermination 348000 53 83 2 ROM_PAGE34_527 + prvAllocateTCBAndStack 348053 3D 61 2 ROM_PAGE34_527 + prvDeleteTCB 348090 F 15 2 ROM_PAGE34_527 + xQueueCreate 34809F 7B 123 14 ROM_PAGE34_527 + xQueueSend 34811A D4 212 9 ROM_PAGE34_527 + xQueueSendFromISR 3481EE 5D 93 2 ROM_PAGE34_527 + xQueueReceive 358000 CF 207 9 ROM_PAGE35_528 + xQueueReceiveFromISR 3580CF 61 97 2 ROM_PAGE35_528 + uxQueueMessagesWaiting 358130 1B 27 2 ROM_PAGE35_528 + prvUnlockQueue 35814B 71 113 8 ROM_PAGE35_528 + prvIsQueueEmpty 3581BC 22 34 2 ROM_PAGE35_528 + prvIsQueueFull 3581DE 25 37 2 ROM_PAGE35_528 + vListInitialise 358203 20 32 6 ROM_PAGE35_528 + vListInitialiseItem 358223 7 7 6 ROM_PAGE35_528 + vListInsertEnd 35822A 25 37 16 ROM_PAGE35_528 + vListInsert 368000 55 85 8 ROM_PAGE36_529 + vListRemove 368055 23 35 32 ROM_PAGE36_529 + pvPortMalloc 368078 C1 193 14 ROM_PAGE36_529 + vPortFree 368139 3B 59 10 ROM_PAGE36_529 + vStartLEDFlashTasks 368174 32 50 2 ROM_PAGE36_529 + vLEDFlashTask 3681A6 57 87 3 ROM_PAGE36_529 + vStartDynamicPriorityTasks 378000 9B 155 2 ROM_PAGE37_530 + vLimitedIncrementTask 37809B 27 39 3 ROM_PAGE37_530 + vContinuousIncrementTask 3780C2 38 56 3 ROM_PAGE37_530 + vCounterControlTask 3780FA A0 160 5 ROM_PAGE37_530 + vQueueSendWhenSuspendedTask 37819A 38 56 3 ROM_PAGE37_530 + vQueueReceiveWhenSuspendedTask 3781D2 54 84 3 ROM_PAGE37_530 + xAreDynamicPriorityTasksStillRunning 378226 2B 43 2 ROM_PAGE37_530 + vStartPolledQueueTasks 388000 4B 75 2 ROM_PAGE38_531 + vPolledQueueProducer 38804B 4F 79 3 ROM_PAGE38_531 + vPolledQueueConsumer 38809A 5C 92 3 ROM_PAGE38_531 + xArePollingQueuesStillRunning 3880F6 16 22 2 ROM_PAGE38_531 + PE_Timer_LngHi1 38810C 4A 74 2 ROM_PAGE38_531 + vAltStartComTestTasks 388156 4D 77 2 ROM_PAGE38_531 + vComTxTask 3881A3 4F 79 3 ROM_PAGE38_531 + vComRxTask 398000 7B 123 3 ROM_PAGE39_532 + xAreComTestTasksStillRunning 39807B D 13 2 ROM_PAGE39_532 + pxPortInitialiseStack 398088 31 49 2 ROM_PAGE39_532 + xPortStartScheduler 3980B9 4 4 2 ROM_PAGE39_532 + vStartIntegerMathTasks 3980BD 33 51 2 ROM_PAGE39_532 + vCompeteingIntMathTask 3980F0 87 135 3 ROM_PAGE39_532 + xAreIntegerMathsTaskStillRunning 398177 20 32 2 ROM_PAGE39_532 + vStartBlockingQueueTasks 3A8000 143 323 7 ROM_PAGE3A_533 + vBlockingQueueProducer 3A8143 3F 63 9 ROM_PAGE3A_533 + vBlockingQueueConsumer 3A8182 47 71 9 ROM_PAGE3A_533 + xAreBlockingQueuesStillRunning 3A81C9 52 82 2 ROM_PAGE3A_533 + vCreateSuicidalTasks 3A821B 31 49 2 ROM_PAGE3A_533 + vSuicidalTask 3B8000 58 88 12 ROM_PAGE3B_534 + vCreateTasks 3B8058 92 146 4 ROM_PAGE3B_534 + xIsCreateTaskStillRunning 3B80EA 3A 58 2 ROM_PAGE3B_534 + TickTimer_Enable 3B8124 9 9 2 TickTimer_CODE + TickTimer_SetFreqHz 3B812D 56 86 2 TickTimer_CODE + TickTimer_Init 3B8183 1C 28 2 TickTimer_CODE + Byte1_PutBit 3B819F 21 33 2 Byte1_CODE + Byte1_NegBit 3B81C0 14 20 2 Byte1_CODE + COM0_SetBaudRateMode 3B81D4 19 25 2 COM0_CODE + COM0_Init 3B81ED 25 37 2 COM0_CODE + +********************************************************************************************* +UNUSED-OBJECTS SECTION +--------------------------------------------------------------------------------------------- +NOT USED PROCEDURES +STRING.C.o (ansibi.lib): + strerror memchr memcmp memcpy2 _memcpy_8bitCount memmove + _memset_clear_8bitCount strlen strset strcat strncat strcpy strcmp strncmp + strchr strrchr strspn strcspn strpbrk strstr strtok strcoll strxfrm +rtshc12.c.o (ansibi.lib): + _BSHL _BSHRS _BSHRU _BDIVMODU _BDIVMODS _ISHL _ISHRU _ISHRS _LSHL _LSHRU + _LSHRS _LADD _LSUB _LAND _LOR _LXOR _LCMP_PP _LABS _LCOM _LDEC _LMODU _LMODS + _ILSEXT _LTEST _COPY _CASE_DIRECT _CASE_DIRECT_BYTE _CASE_CHECKED + _CASE_CHECKED_BYTE _CASE_SEARCH _CASE_SEARCH_BYTE _CASE_SEARCH_8 + _CASE_SEARCH_8_BYTE _FCALL _FPCMP +serial.c.o: + vSerialClose +tasks.c.o: + vTaskEndScheduler +queue.c.o: + vQueueDelete +TickTimer.C.o: + TickTimer_Interrupt SetCV SetPV HWEnDi TickTimer_SetPeriodTicks16 + TickTimer_SetPeriodTicks32 TickTimer_SetPeriodUS TickTimer_SetPeriodMS +Byte1.C.o: + Byte1_GetMsk +PE_Timer.C.o: + PE_Timer_LngMul PE_Timer_LngHi2 PE_Timer_LngHi3 PE_Timer_LngHi4 +COM0.C.o: + HWEnDi +port.c.o: + vPortEndScheduler prvSetupTimerInterrupt +NOT USED VARIABLES +STRING.C.o (ansibi.lib): + STRING..1 next.2 +rtshc12.c.o (ansibi.lib): + _PowOfTwo_8 _PowOfTwo_16 _PowOfTwo_32 +Cpu.C.o: + CpuMode CCR_reg +heap_2.c.o: + heapSTRUCT_SIZE +death.c.o: + uxMaxNumberOfExtraTasksRunning + +********************************************************************************************* +COPYDOWN SECTION +--------------------------------------------------------------------------------------------- +------- ROM-ADDRESS: 0xC3B5 ---- SIZE 4 --- +Filling bytes inserted + 00011000 +------- ROM-ADDRESS: 0xC3B9 ---- RAM-ADDRESS: 0x1000 ---- SIZE 1 --- +Name of initialized Object : uxCriticalNesting + FF +------- ROM-ADDRESS: 0xC3BA ---- SIZE 4 --- +Filling bytes inserted + 001038F4 +------- ROM-ADDRESS: 0xC3BE ---- RAM-ADDRESS: 0x38F4 ---- SIZE 8 --- +Name of initialized Object : Byte1_Table + 0102040810 204080 +------- ROM-ADDRESS: 0xC3C6 ---- SIZE 1 --- +Filling bytes inserted + 00 +------- ROM-ADDRESS: 0xC3C7 ---- RAM-ADDRESS: 0x38FD ---- SIZE 7 --- +Name of initialized Object : COM0_PrescHigh.1:1 + 29005100A3 0146 +------- ROM-ADDRESS: 0xC3CE ---- SIZE 2 --- +Filling bytes inserted + 0000 + +********************************************************************************************* +OBJECT-DEPENDENCIES SECTION +--------------------------------------------------------------------------------------------- +_EntryPoint USES _INITRM _INITEE _MISC _CLKSEL _PLLCTL _SYNR + _REFDV _CRGFLG _Startup +PE_low_level_init USES _TSCR1 _TCTL2 _TCTL1 _TIE _TTOV _TSCR2 _TIOS + _PWMCTL _PWMSDN _ICSYS _MCCTL TickTimer_Init _PORTAB + _DDRAB _DDRS _PTS COM0_Init _INTCR +_Startup USES _startupData Init +_LDIVU USES _lDivMod +_LDIVS USES _NEG_P _lDivMod +vCOM0_ISR USES _SCI0SR1 _SCI0DRL xRxedChars xQueueSendFromISR + _SCI0CR2 xCharsForTx xQueueReceiveFromISR +xBankedStartScheduler USES TickTimer_SetFreqHz TickTimer_Enable + pxCurrentTCB uxCriticalNesting +vPortYield USES uxCriticalNesting pxCurrentTCB + vTaskSwitchContext +vPortTickInterrupt USES uxCriticalNesting pxCurrentTCB + vTaskIncrementTick vTaskSwitchContext _TFLG1 +_vect USES Cpu_Interrupt vCOM0_ISR vPortTickInterrupt + vPortYield _EntryPoint +Init USES _startupData +main USES PE_low_level_init vMain +vMain USES vStartLEDFlashTasks vStartPolledQueueTasks + vStartDynamicPriorityTasks vAltStartComTestTasks vStartBlockingQueueTasks + vStartIntegerMathTasks vCreateSuicidalTasks vErrorChecks + STRING.Check.1 xTaskCreate vTaskStartScheduler +vErrorChecks USES xTaskGetTickCount vTaskDelayUntil + prvCheckOtherTasksAreStillRunning _LCMP vParTestToggleLED +prvCheckOtherTasksAreStillRunning USES xArePollingQueuesStillRunning + xAreDynamicPriorityTasksStillRunning xAreComTestTasksStillRunning + xAreIntegerMathsTaskStillRunning xAreBlockingQueuesStillRunning + xIsCreateTaskStillRunning xLocalError +vApplicationIdleHook USES _LNEG _LDIVS _LCMP_P uxCriticalNesting + xLocalError +vParTestSetLED USES uxCriticalNesting Byte1_PutBit +vParTestToggleLED USES uxCriticalNesting Byte1_NegBit +xSerialPortInitMinimal USES xQueueCreate xRxedChars xCharsForTx + COM0_SetBaudRateMode +xSerialGetChar USES xRxedChars xQueueReceive +xSerialPutChar USES xCharsForTx xQueueSend _SCI0CR2 +xTaskCreate USES prvAllocateTCBAndStack + prvInitialiseTCBVariables pxPortInitialiseStack uxCriticalNesting + uxCurrentNumberOfTasks pxCurrentTCB prvInitialiseTaskLists + xSchedulerRunning uxTopUsedPriority uxTaskNumber.1 + uxTopReadyPriority pxReadyTasksLists vListInsertEnd +vTaskDelete USES uxCriticalNesting pxCurrentTCB vListRemove + xTasksWaitingTermination vListInsertEnd uxTasksDeleted +vTaskDelayUntil USES vTaskSuspendAll xTickCount pxCurrentTCB + vListRemove pxOverflowDelayedTaskList pxDelayedTaskList + vListInsert xTaskResumeAll +vTaskDelay USES vTaskSuspendAll xTickCount pxCurrentTCB + vListRemove pxOverflowDelayedTaskList pxDelayedTaskList + vListInsert xTaskResumeAll +uxTaskPriorityGet USES uxCriticalNesting pxCurrentTCB +vTaskPrioritySet USES uxCriticalNesting pxCurrentTCB + pxReadyTasksLists vListRemove uxTopReadyPriority vListInsertEnd +vTaskSuspend USES uxCriticalNesting pxCurrentTCB vListRemove + xSuspendedTaskList vListInsertEnd +vTaskResume USES uxCriticalNesting pxCurrentTCB vListRemove + uxTopReadyPriority pxReadyTasksLists vListInsertEnd +vTaskStartScheduler USES pxCurrentTCB prvIdleTask STRING.IDLE.2 + xTaskCreate xSchedulerRunning xTickCount + xPortStartScheduler +vTaskSuspendAll USES uxCriticalNesting uxSchedulerSuspended +xTaskResumeAll USES uxCriticalNesting uxSchedulerSuspended + uxCurrentNumberOfTasks vListRemove uxTopReadyPriority + pxReadyTasksLists vListInsertEnd pxCurrentTCB xPendingReadyList + uxMissedTicks vTaskIncrementTick +xTaskGetTickCount USES uxCriticalNesting xTickCount +uxTaskGetNumberOfTasks USES uxCriticalNesting uxCurrentNumberOfTasks +vTaskIncrementTick USES uxSchedulerSuspended xTickCount + pxDelayedTaskList pxOverflowDelayedTaskList vListRemove + uxTopReadyPriority pxReadyTasksLists vListInsertEnd uxMissedTicks +vTaskSwitchContext USES uxSchedulerSuspended uxTopReadyPriority + pxCurrentTCB pxReadyTasksLists +vTaskPlaceOnEventList USES pxCurrentTCB vListInsert xTickCount vListRemove + pxOverflowDelayedTaskList pxDelayedTaskList +xTaskRemoveFromEventList USES vListRemove uxSchedulerSuspended + uxTopReadyPriority pxReadyTasksLists xPendingReadyList + vListInsertEnd pxCurrentTCB +prvIdleTask USES prvCheckTasksWaitingTermination + pxReadyTasksLists vApplicationIdleHook +prvInitialiseTCBVariables USES strncpy vListInitialiseItem +prvInitialiseTaskLists USES pxReadyTasksLists xDelayedTaskList1 + xDelayedTaskList2 xPendingReadyList xTasksWaitingTermination + xSuspendedTaskList pxDelayedTaskList pxOverflowDelayedTaskList + vListInitialise +prvCheckTasksWaitingTermination USES uxTasksDeleted vTaskSuspendAll + xTasksWaitingTermination xTaskResumeAll uxCriticalNesting vListRemove + uxCurrentNumberOfTasks prvDeleteTCB +prvAllocateTCBAndStack USES pvPortMalloc vPortFree memset +prvDeleteTCB USES vPortFree +xQueueCreate USES pvPortMalloc vListInitialise vPortFree +xQueueSend USES vTaskSuspendAll uxCriticalNesting xQueueSend + prvIsQueueFull vTaskPlaceOnEventList prvUnlockQueue + xTaskResumeAll memcpy +xQueueSendFromISR USES memcpy xTaskRemoveFromEventList +xQueueReceive USES vTaskSuspendAll uxCriticalNesting xQueueReceive + prvIsQueueEmpty vTaskPlaceOnEventList prvUnlockQueue + xTaskResumeAll memcpy +xQueueReceiveFromISR USES memcpy xTaskRemoveFromEventList +uxQueueMessagesWaiting USES uxCriticalNesting +prvUnlockQueue USES uxCriticalNesting xTaskRemoveFromEventList +prvIsQueueEmpty USES uxCriticalNesting +prvIsQueueFull USES uxCriticalNesting +vListInitialise USES vListInitialiseItem +pvPortMalloc USES vTaskSuspendAll xHeapHasBeenInitialised.1 xHeap + xStart xEnd xTaskResumeAll +vPortFree USES vTaskSuspendAll xStart xTaskResumeAll +vStartLEDFlashTasks USES vLEDFlashTask STRING.LEDx.1 xTaskCreate +vLEDFlashTask USES uxCriticalNesting uxFlashTaskNumber + xTaskGetTickCount vTaskDelayUntil vParTestToggleLED +vStartDynamicPriorityTasks USES xQueueCreate xSuspendedTestQueue + vContinuousIncrementTask STRING.CNT_INC.1 ulCounter + xContinousIncrementHandle xTaskCreate vLimitedIncrementTask + STRING.LIM_INC.2 xLimitedIncrementHandle vCounterControlTask + STRING.C_CTRL.3 vQueueSendWhenSuspendedTask STRING.SUSP_TX.4 + vQueueReceiveWhenSuspendedTask STRING.SUSP_RX.5 +vLimitedIncrementTask USES _LINC _LCMP_P vTaskSuspend +vContinuousIncrementTask USES uxTaskPriorityGet vTaskPrioritySet _LINC +vCounterControlTask USES vCounterControlTask xContinousIncrementHandle + vTaskSuspend ulCounter vTaskResume vTaskDelay + vTaskSuspendAll xTaskResumeAll xLimitedIncrementHandle + uxCriticalNesting usCheckVariable +vQueueSendWhenSuspendedTask USES vTaskSuspendAll xSuspendedTestQueue + ulValueToSend.6 xQueueSend xSuspendedQueueSendError + xTaskResumeAll vTaskDelay _LINC +vQueueReceiveWhenSuspendedTask USES vTaskSuspendAll xSuspendedTestQueue + ulReceivedValue.8 xQueueReceive xTaskResumeAll + xSuspendedQueueReceiveError ulExpectedValue.7 _LINC +xAreDynamicPriorityTasksStillRunning USES usCheckVariable usLastTaskCheck.9 + xSuspendedQueueSendError xSuspendedQueueReceiveError +vStartPolledQueueTasks USES xQueueCreate xPolledQueue.1 + vPolledQueueConsumer STRING.QConsNB.2 xTaskCreate + vPolledQueueProducer STRING.QProdNB.3 +vPolledQueueProducer USES xQueueSend uxCriticalNesting + xPollingProducerCount vTaskDelay +vPolledQueueConsumer USES xQueueReceive uxCriticalNesting + xPollingConsumerCount uxQueueMessagesWaiting vTaskDelay +xArePollingQueuesStillRunning USES xPollingConsumerCount xPollingProducerCount +PE_Timer_LngHi1 USES _LCMP +vAltStartComTestTasks USES uxBaseLED xSerialPortInitMinimal vComTxTask + STRING.COMTx.1 xTaskCreate vComRxTask STRING.COMRx.2 +vComTxTask USES xPort xSerialPutChar uxBaseLED + vParTestToggleLED vParTestSetLED xTaskGetTickCount vTaskDelay +vComRxTask USES xPort xSerialGetChar uxBaseLED + vParTestToggleLED vParTestSetLED uxRxLoops +xAreComTestTasksStillRunning USES uxRxLoops +xPortStartScheduler USES xBankedStartScheduler +vStartIntegerMathTasks USES vCompeteingIntMathTask STRING.IntMath.1 + xTaskCheck xTaskCreate +vCompeteingIntMathTask USES _LNEG _LDIVS _LCMP_P uxCriticalNesting +xAreIntegerMathsTaskStillRunning USES xTaskCheck +vStartBlockingQueueTasks USES vStartBlockingQueueTasks xQueueCreate + sBlockingConsumerCount sBlockingProducerCount vBlockingQueueConsumer + STRING.QConsB1.1 xTaskCreate vBlockingQueueProducer + STRING.QProdB2.2 STRING.QProdB3.3 STRING.QConsB4.4 + STRING.QProdB5.5 STRING.QConsB6.6 pvPortMalloc +vBlockingQueueProducer USES xQueueSend +vBlockingQueueConsumer USES xQueueReceive +xAreBlockingQueuesStillRunning USES sLastBlockingConsumerCount.7 + sBlockingProducerCount sLastBlockingProducerCount.8 + sBlockingConsumerCount +vCreateSuicidalTasks USES pvPortMalloc vCreateTasks STRING.CREATOR.1 + xTaskCreate uxTaskGetNumberOfTasks uxTasksRunningAtStart +vSuicidalTask USES _LMUL vTaskDelay vTaskDelete +vCreateTasks USES vPortFree vTaskDelay vSuicidalTask + STRING.SUICIDE1.2 xCreatedTask1 xTaskCreate STRING.SUICIDE2.3 + STRING.SUICIDE1.4 xCreatedTask2 STRING.SUICIDE2.5 + usCreationCount vCreateTasks +xIsCreateTaskStillRunning USES usLastCreationCount.6 usCreationCount + uxTaskGetNumberOfTasks uxTasksRunningNow.7 uxTasksRunningAtStart +TickTimer_Enable USES _TFLG1 _TIE +TickTimer_SetFreqHz USES _LDIVU PE_Timer_LngHi1 CmpHighVal _TC0 _TC7 +TickTimer_Init USES CmpHighVal _TC0 _TC7 _TSCR2 _TFLG1 _TIE +Byte1_PutBit USES Byte1_Table _PORTAB +Byte1_NegBit USES Byte1_Table _PORTAB +COM0_SetBaudRateMode USES NumMode COM0_PrescHigh.1 PrescHigh _SCI0BD +COM0_Init USES PrescHigh SerFlag NumMode _SCI0CR1 _SCI0SR2 + _SCI0SR1 _SCI0CR2 _SCI0BD + +********************************************************************************************* +DEPENDENCY TREE +********************************************************************************************* + main and _Startup Group + | + +- main + | | + | +- PE_low_level_init + | | | + | | +- TickTimer_Init + | | | + | | +- COM0_Init + | | + | +- vMain + | | + | +- vStartLEDFlashTasks + | | | + | | +- vLEDFlashTask + | | | | + | | | +- xTaskGetTickCount + | | | | + | | | +- vTaskDelayUntil + | | | | | + | | | | +- vTaskSuspendAll + | | | | | + | | | | +- vListRemove + | | | | | + | | | | +- vListInsert + | | | | | + | | | | +- xTaskResumeAll + | | | | | + | | | | +- vListRemove (see above) + | | | | | + | | | | +- vListInsertEnd + | | | | | + | | | | +- vTaskIncrementTick + | | | | | + | | | | +- vListRemove (see above) + | | | | | + | | | | +- vListInsertEnd (see above) + | | | | + | | | +- vParTestToggleLED + | | | | + | | | +- Byte1_NegBit + | | | + | | +- xTaskCreate + | | | + | | +- prvAllocateTCBAndStack + | | | | + | | | +- pvPortMalloc + | | | | | + | | | | +- vTaskSuspendAll (see above) + | | | | | + | | | | +- xTaskResumeAll (see above) + | | | | + | | | +- vPortFree + | | | | | + | | | | +- vTaskSuspendAll (see above) + | | | | | + | | | | +- xTaskResumeAll (see above) + | | | | + | | | +- memset + | | | + | | +- prvInitialiseTCBVariables + | | | | + | | | +- strncpy + | | | | + | | | +- vListInitialiseItem + | | | + | | +- pxPortInitialiseStack + | | | + | | +- prvInitialiseTaskLists + | | | | + | | | +- vListInitialise + | | | | + | | | +- vListInitialiseItem (see above) + | | | + | | +- vListInsertEnd (see above) + | | + | +- vStartPolledQueueTasks + | | | + | | +- xQueueCreate + | | | | + | | | +- pvPortMalloc (see above) + | | | | + | | | +- vListInitialise (see above) + | | | | + | | | +- vPortFree (see above) + | | | + | | +- vPolledQueueConsumer + | | | | + | | | +- xQueueReceive + | | | | | + | | | | +- vTaskSuspendAll (see above) + | | | | | + | | | | +- prvIsQueueEmpty + | | | | | + | | | | +- vTaskPlaceOnEventList + | | | | | | + | | | | | +- vListInsert (see above) + | | | | | | + | | | | | +- vListRemove (see above) + | | | | | + | | | | +- prvUnlockQueue + | | | | | | + | | | | | +- xTaskRemoveFromEventList + | | | | | | + | | | | | +- vListRemove (see above) + | | | | | | + | | | | | +- vListInsertEnd (see above) + | | | | | + | | | | +- xTaskResumeAll (see above) + | | | | | + | | | | +- memcpy + | | | | + | | | +- uxQueueMessagesWaiting + | | | | + | | | +- vTaskDelay + | | | | + | | | +- vTaskSuspendAll (see above) + | | | | + | | | +- vListRemove (see above) + | | | | + | | | +- vListInsert (see above) + | | | | + | | | +- xTaskResumeAll (see above) + | | | + | | +- xTaskCreate (see above) + | | | + | | +- vPolledQueueProducer + | | | + | | +- xQueueSend + | | | | + | | | +- vTaskSuspendAll (see above) + | | | | + | | | +- prvIsQueueFull + | | | | + | | | +- vTaskPlaceOnEventList (see above) + | | | | + | | | +- prvUnlockQueue (see above) + | | | | + | | | +- xTaskResumeAll (see above) + | | | | + | | | +- memcpy (see above) + | | | + | | +- vTaskDelay (see above) + | | + | +- vStartDynamicPriorityTasks + | | | + | | +- xQueueCreate (see above) + | | | + | | +- vContinuousIncrementTask + | | | | + | | | +- uxTaskPriorityGet + | | | | + | | | +- vTaskPrioritySet + | | | | | + | | | | +- vListRemove (see above) + | | | | | + | | | | +- vListInsertEnd (see above) + | | | | + | | | +- _LINC + | | | + | | +- xTaskCreate (see above) + | | | + | | +- vLimitedIncrementTask + | | | | + | | | +- _LINC (see above) + | | | | + | | | +- _LCMP_P + | | | | + | | | +- vTaskSuspend + | | | | + | | | +- vListRemove (see above) + | | | | + | | | +- vListInsertEnd (see above) + | | | + | | +- vCounterControlTask + | | | | + | | | +- vTaskSuspend (see above) + | | | | + | | | +- vTaskResume + | | | | | + | | | | +- vListRemove (see above) + | | | | | + | | | | +- vListInsertEnd (see above) + | | | | + | | | +- vTaskDelay (see above) + | | | | + | | | +- vTaskSuspendAll (see above) + | | | | + | | | +- xTaskResumeAll (see above) + | | | + | | +- vQueueSendWhenSuspendedTask + | | | | + | | | +- vTaskSuspendAll (see above) + | | | | + | | | +- xQueueSend (see above) + | | | | + | | | +- xTaskResumeAll (see above) + | | | | + | | | +- vTaskDelay (see above) + | | | | + | | | +- _LINC (see above) + | | | + | | +- vQueueReceiveWhenSuspendedTask + | | | + | | +- vTaskSuspendAll (see above) + | | | + | | +- xQueueReceive (see above) + | | | + | | +- xTaskResumeAll (see above) + | | | + | | +- _LINC (see above) + | | + | +- vAltStartComTestTasks + | | | + | | +- xSerialPortInitMinimal + | | | | + | | | +- xQueueCreate (see above) + | | | | + | | | +- COM0_SetBaudRateMode + | | | + | | +- vComTxTask + | | | | + | | | +- xSerialPutChar + | | | | | + | | | | +- xQueueSend (see above) + | | | | + | | | +- vParTestToggleLED (see above) + | | | | + | | | +- vParTestSetLED + | | | | | + | | | | +- Byte1_PutBit + | | | | + | | | +- xTaskGetTickCount (see above) + | | | | + | | | +- vTaskDelay (see above) + | | | + | | +- xTaskCreate (see above) + | | | + | | +- vComRxTask + | | | + | | +- xSerialGetChar + | | | | + | | | +- xQueueReceive (see above) + | | | + | | +- vParTestToggleLED (see above) + | | | + | | +- vParTestSetLED (see above) + | | + | +- vStartBlockingQueueTasks + | | | + | | +- xQueueCreate (see above) + | | | + | | +- vBlockingQueueConsumer + | | | | + | | | +- xQueueReceive (see above) + | | | + | | +- xTaskCreate (see above) + | | | + | | +- vBlockingQueueProducer + | | | | + | | | +- xQueueSend (see above) + | | | + | | +- pvPortMalloc (see above) + | | + | +- vStartIntegerMathTasks + | | | + | | +- vCompeteingIntMathTask + | | | | + | | | +- _LNEG + | | | | + | | | +- _LDIVS + | | | | | + | | | | +- _NEG_P + | | | | | + | | | | +- _lDivMod + | | | | + | | | +- _LCMP_P (see above) + | | | + | | +- xTaskCreate (see above) + | | + | +- vCreateSuicidalTasks + | | | + | | +- pvPortMalloc (see above) + | | | + | | +- vCreateTasks + | | | | + | | | +- vPortFree (see above) + | | | | + | | | +- vTaskDelay (see above) + | | | | + | | | +- vSuicidalTask + | | | | | + | | | | +- _LMUL + | | | | | + | | | | +- vTaskDelay (see above) + | | | | | + | | | | +- vTaskDelete + | | | | | + | | | | +- vListRemove (see above) + | | | | | + | | | | +- vListInsertEnd (see above) + | | | | + | | | +- xTaskCreate (see above) + | | | + | | +- xTaskCreate (see above) + | | | + | | +- uxTaskGetNumberOfTasks + | | + | +- vErrorChecks + | | | + | | +- xTaskGetTickCount (see above) + | | | + | | +- vTaskDelayUntil (see above) + | | | + | | +- prvCheckOtherTasksAreStillRunning + | | | | + | | | +- xArePollingQueuesStillRunning + | | | | + | | | +- xAreDynamicPriorityTasksStillRunning + | | | | + | | | +- xAreComTestTasksStillRunning + | | | | + | | | +- xAreIntegerMathsTaskStillRunning + | | | | + | | | +- xAreBlockingQueuesStillRunning + | | | | + | | | +- xIsCreateTaskStillRunning + | | | | + | | | +- uxTaskGetNumberOfTasks (see above) + | | | + | | +- _LCMP + | | | + | | +- vParTestToggleLED (see above) + | | + | +- xTaskCreate (see above) + | | + | +- vTaskStartScheduler + | | + | +- prvIdleTask + | | | + | | +- prvCheckTasksWaitingTermination + | | | | + | | | +- vTaskSuspendAll (see above) + | | | | + | | | +- xTaskResumeAll (see above) + | | | | + | | | +- vListRemove (see above) + | | | | + | | | +- prvDeleteTCB + | | | | + | | | +- vPortFree (see above) + | | | + | | +- vApplicationIdleHook + | | | + | | +- _LNEG (see above) + | | | + | | +- _LDIVS (see above) + | | | + | | +- _LCMP_P (see above) + | | + | +- xTaskCreate (see above) + | | + | +- xPortStartScheduler + | | + | +- xBankedStartScheduler + | | + | +- TickTimer_SetFreqHz + | | | + | | +- _LDIVU + | | | | + | | | +- _lDivMod (see above) + | | | + | | +- PE_Timer_LngHi1 + | | | + | | +- _LCMP (see above) + | | + | +- TickTimer_Enable + | + +- _EntryPoint + | + +- _Startup + | + +- Init + + _vect + | + +- Cpu_Interrupt + | + +- vCOM0_ISR + | | + | +- xQueueSendFromISR + | | | + | | +- memcpy (see above) + | | | + | | +- xTaskRemoveFromEventList (see above) + | | + | +- xQueueReceiveFromISR + | | + | +- memcpy (see above) + | | + | +- xTaskRemoveFromEventList (see above) + | + +- vPortTickInterrupt + | | + | +- vTaskIncrementTick (see above) + | | + | +- vTaskSwitchContext + | + +- vPortYield + | | + | +- vTaskSwitchContext (see above) + | + +- _EntryPoint (see above) + +********************************************************************************************* +STATISTIC SECTION +--------------------------------------------------------------------------------------------- + +ExeFile: +-------- +Number of blocks to be downloaded: 18 +Total size of all blocks to be downloaded: 7636 + diff --git a/20080212/Demo/HCS12_CodeWarrior_banked/bin/Simulator.map b/20080212/Demo/HCS12_CodeWarrior_banked/bin/Simulator.map new file mode 100644 index 000000000..6c7e3b7e4 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_banked/bin/Simulator.map @@ -0,0 +1,4026 @@ + +PROGRAM "E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_banked\bin\Simulator.abs" + +********************************************************************************************* +TARGET SECTION +--------------------------------------------------------------------------------------------- +Processor : Motorola HC12 +Memory Model: BANKED +File Format : ELF\Dwarf 2.0 +Linker : SmartLinker V-5.0.22 Build 4047, Feb 17 2004 + +********************************************************************************************* +FILE SECTION +--------------------------------------------------------------------------------------------- +Start12.c.o Model: BANKED, Lang: ANSI-C +STRING.C.o (ansibi.lib) Model: BANKED, Lang: ANSI-C +rtshc12.c.o (ansibi.lib) Model: BANKED, Lang: ANSI-C +Cpu.C.o Model: BANKED, Lang: ANSI-C +IO_Map.C.o Model: BANKED, Lang: ANSI-C +Vectors.c.o Model: BANKED, Lang: ANSI-C +RTOSDemo.C.o Model: BANKED, Lang: ANSI-C +main.c.o Model: BANKED, Lang: ANSI-C +ParTest.c.o Model: BANKED, Lang: ANSI-C +serial.c.o Model: BANKED, Lang: ANSI-C +tasks.c.o Model: BANKED, Lang: ANSI-C +queue.c.o Model: BANKED, Lang: ANSI-C +list.c.o Model: BANKED, Lang: ANSI-C +heap_2.c.o Model: BANKED, Lang: ANSI-C +TickTimer.C.o Model: BANKED, Lang: ANSI-C +PE_Timer.C.o Model: BANKED, Lang: ANSI-C +Byte1.C.o Model: BANKED, Lang: ANSI-C +flash.c.o Model: BANKED, Lang: ANSI-C +dynamic.c.o Model: BANKED, Lang: ANSI-C +PollQ.c.o Model: BANKED, Lang: ANSI-C +comtest.c.o Model: BANKED, Lang: ANSI-C +COM0.C.o Model: BANKED, Lang: ANSI-C +port.c.o Model: BANKED, Lang: ANSI-C +integer.c.o Model: BANKED, Lang: ANSI-C +BlockQ.c.o Model: BANKED, Lang: ANSI-C +death.c.o Model: BANKED, Lang: ANSI-C + +********************************************************************************************* +STARTUP SECTION +--------------------------------------------------------------------------------------------- +Entry point: 0xC000 (_EntryPoint) +_startupData is allocated at 0xC07C and uses 24 Bytes +extern struct _tagStartup { + unsigned flags 0 + _PFunc main 0x30809A (main) + long stackOffset 0x3988 + unsigned nofZeroOut 1 + _Range pZeroOut 0x1000 10505 + _Copy *toCopyDownBeg 0xC3AE + int nofLibInits 0 + _LibInit *libInits 0xC098 + int nofInitBodies 0 + _Cpp *initBodies 0xC09A + int nofFiniBodies 0 + _Cpp *finiBodies 0xC09A +} _startupData; + +********************************************************************************************* +SECTION-ALLOCATION SECTION +Section Name Size Type From To Segment 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N/I 0x52 0x53 .absSeg512 +.abs_section_7a 2 N/I 0x7A 0x7B .absSeg513 +.abs_section_54 2 N/I 0x54 0x55 .absSeg514 +.abs_section_7c 2 N/I 0x7C 0x7D .absSeg515 +.abs_section_56 2 N/I 0x56 0x57 .absSeg516 +.abs_section_7e 2 N/I 0x7E 0x7F .absSeg517 +.abs_section_58 2 N/I 0x58 0x59 .absSeg518 +.abs_section_5a 2 N/I 0x5A 0x5B .absSeg519 +.abs_section_5c 2 N/I 0x5C 0x5D .absSeg520 +.abs_section_5e 2 N/I 0x5E 0x5F .absSeg521 +.abs_section_44 2 N/I 0x44 0x45 .absSeg522 +.abs_section_ff80 128 R 0xFF80 0xFFFF .absSeg523 +.bss 10475 R/W 0x1001 0x38EB RAM +.common 6 R/W 0x38EC 0x38F1 RAM +TickTimer_CODE 143 R 0x3B811C 0x3B81AA ROM_PAGE3B +Byte1_CODE 61 R 0x3B81AB 0x3B81E7 ROM_PAGE3B +COM0_CODE 67 R 0x3B81E8 0x3B822A ROM_PAGE3B +TickTimer_DATA 2 R/W 0x38F2 0x38F3 RAM +Byte1_DATA 8 R/W 0x38F4 0x38FB RAM +COM0_DATA 13 R/W 0x38FC 0x3908 RAM +.stack 128 R/W 0x3909 0x3988 RAM +ROM_PAGE31_524 552 R 0x318000 0x318227 ROM_PAGE31 +ROM_PAGE32_525 552 R 0x328000 0x328227 ROM_PAGE32 +ROM_PAGE33_526 564 R 0x338000 0x338233 ROM_PAGE33 +ROM_PAGE34_527 579 R 0x348000 0x348242 ROM_PAGE34 +ROM_PAGE35_528 589 R 0x358000 0x35824C ROM_PAGE35 +ROM_PAGE36_529 555 R 0x368000 0x36822A ROM_PAGE36 +ROM_PAGE37_530 578 R 0x378000 0x378241 ROM_PAGE37 +ROM_PAGE38_531 558 R 0x388000 0x38822D ROM_PAGE38 +ROM_PAGE39_532 288 R 0x398000 0x39811F ROM_PAGE39 +ROM_PAGE3A_533 574 R 0x3A8000 0x3A823D ROM_PAGE3A +ROM_PAGE3B_534 284 R 0x3B8000 0x3B811B ROM_PAGE3B + +Summary of section sizes per section type: +READ_ONLY (R): 1DD3 (dec: 7635) +READ_WRITE (R/W): 2989 (dec: 10633) +NO_INIT (N/I): 241 (dec: 577) + +********************************************************************************************* +VECTOR-ALLOCATION SECTION + Address InitValue InitFunction +--------------------------------------------------------------------------------------------- + +********************************************************************************************* +OBJECT-ALLOCATION SECTION + Name Module Addr hSize dSize Ref Section RLIB +--------------------------------------------------------------------------------------------- +MODULE: -- Start12.c.o -- +- PROCEDURES: + Init 308000 29 41 2 .text + _Startup C151 12 18 1 NON_BANKED +- VARIABLES: + _startupData C07C 18 24 6 .startData +MODULE: -- STRING.C.o (ansibi.lib) -- +- PROCEDURES: + memcpy 308029 26 38 8 .text + memset 30804F 1E 30 2 .text + strncpy 30806D 2D 45 2 .text +- VARIABLES: +MODULE: -- rtshc12.c.o (ansibi.lib) -- +- PROCEDURES: + _LCMP C163 19 25 2 NON_BANKED + _LCMP_P C17C 15 21 3 NON_BANKED + _LNEG C191 D 13 2 NON_BANKED + _LINC C19E 5 5 4 NON_BANKED + _LMUL C1A3 27 39 1 NON_BANKED + _lDivMod C1CA E3 227 3 NON_BANKED + _LDIVU C2AD E 14 1 NON_BANKED + _NEG_P C2BB F 15 4 NON_BANKED + _LDIVS C2CA 35 53 2 NON_BANKED +- VARIABLES: +MODULE: -- Cpu.C.o -- +- PROCEDURES: + _EntryPoint C000 2E 46 1 .init + PE_low_level_init C02E 4E 78 2 .init + Cpu_Interrupt C2FF 1 1 60 NON_BANKED +- VARIABLES: +MODULE: -- IO_Map.C.o -- +- PROCEDURES: +- VARIABLES: + _ARMCOP 3F 1 1 0 .abs_section_3f + _ATD0DIEN 8D 1 1 0 .abs_section_8d + _ATD0STAT0 86 1 1 0 .abs_section_86 + _ATD0STAT1 8B 1 1 0 .abs_section_8b + _ATD1DIEN 12D 1 1 0 .abs_section_12d + _ATD1STAT0 126 1 1 0 .abs_section_126 + _ATD1STAT1 12B 1 1 0 .abs_section_12b + _BDMCCR FF06 1 1 0 .abs_section_ff06 + _BDMINR FF07 1 1 0 .abs_section_ff07 + _BDMSTS FF01 1 1 0 .abs_section_ff01 + _BKP0H 2B 1 1 0 .abs_section_2b + _BKP0L 2C 1 1 0 .abs_section_2c + _BKP0X 2A 1 1 0 .abs_section_2a + _BKP1H 2E 1 1 0 .abs_section_2e + _BKP1L 2F 1 1 0 .abs_section_2f + _BKP1X 2D 1 1 0 .abs_section_2d + _BKPCT0 28 1 1 0 .abs_section_28 + _BKPCT1 29 1 1 0 .abs_section_29 + _CAN0BTR0 142 1 1 0 .abs_section_142 + _CAN0BTR1 143 1 1 0 .abs_section_143 + _CAN0CTL0 140 1 1 0 .abs_section_140 + _CAN0CTL1 141 1 1 0 .abs_section_141 + _CAN0IDAC 14B 1 1 0 .abs_section_14b + _CAN0IDAR0 150 1 1 0 .abs_section_150 + _CAN0IDAR1 151 1 1 0 .abs_section_151 + _CAN0IDAR2 152 1 1 0 .abs_section_152 + _CAN0IDAR3 153 1 1 0 .abs_section_153 + _CAN0IDAR4 158 1 1 0 .abs_section_158 + _CAN0IDAR5 159 1 1 0 .abs_section_159 + _CAN0IDAR6 15A 1 1 0 .abs_section_15a + _CAN0IDAR7 15B 1 1 0 .abs_section_15b + _CAN0IDMR0 154 1 1 0 .abs_section_154 + _CAN0IDMR1 155 1 1 0 .abs_section_155 + _CAN0IDMR2 156 1 1 0 .abs_section_156 + _CAN0IDMR3 157 1 1 0 .abs_section_157 + _CAN0IDMR4 15C 1 1 0 .abs_section_15c + _CAN0IDMR5 15D 1 1 0 .abs_section_15d + _CAN0IDMR6 15E 1 1 0 .abs_section_15e + _CAN0IDMR7 15F 1 1 0 .abs_section_15f + _CAN0RFLG 144 1 1 0 .abs_section_144 + _CAN0RIER 145 1 1 0 .abs_section_145 + _CAN0RXDLR 16C 1 1 0 .abs_section_16c + _CAN0RXDSR0 164 1 1 0 .abs_section_164 + _CAN0RXDSR1 165 1 1 0 .abs_section_165 + _CAN0RXDSR2 166 1 1 0 .abs_section_166 + _CAN0RXDSR3 167 1 1 0 .abs_section_167 + _CAN0RXDSR4 168 1 1 0 .abs_section_168 + _CAN0RXDSR5 169 1 1 0 .abs_section_169 + _CAN0RXDSR6 16A 1 1 0 .abs_section_16a + _CAN0RXDSR7 16B 1 1 0 .abs_section_16b + _CAN0RXERR 14E 1 1 0 .abs_section_14e + _CAN0RXIDR0 160 1 1 0 .abs_section_160 + _CAN0RXIDR1 161 1 1 0 .abs_section_161 + _CAN0RXIDR2 162 1 1 0 .abs_section_162 + _CAN0RXIDR3 163 1 1 0 .abs_section_163 + _CAN0TAAK 149 1 1 0 .abs_section_149 + _CAN0TARQ 148 1 1 0 .abs_section_148 + _CAN0TBSEL 14A 1 1 0 .abs_section_14a + _CAN0TFLG 146 1 1 0 .abs_section_146 + _CAN0TIER 147 1 1 0 .abs_section_147 + _CAN0TXDLR 17C 1 1 0 .abs_section_17c + _CAN0TXDSR0 174 1 1 0 .abs_section_174 + _CAN0TXDSR1 175 1 1 0 .abs_section_175 + _CAN0TXDSR2 176 1 1 0 .abs_section_176 + _CAN0TXDSR3 177 1 1 0 .abs_section_177 + _CAN0TXDSR4 178 1 1 0 .abs_section_178 + _CAN0TXDSR5 179 1 1 0 .abs_section_179 + _CAN0TXDSR6 17A 1 1 0 .abs_section_17a + _CAN0TXDSR7 17B 1 1 0 .abs_section_17b + _CAN0TXERR 14F 1 1 0 .abs_section_14f + _CAN0TXIDR0 170 1 1 0 .abs_section_170 + _CAN0TXIDR1 171 1 1 0 .abs_section_171 + _CAN0TXIDR2 172 1 1 0 .abs_section_172 + _CAN0TXIDR3 173 1 1 0 .abs_section_173 + _CAN0TXTBPR 17F 1 1 0 .abs_section_17f + _CAN1BTR0 182 1 1 0 .abs_section_182 + _CAN1BTR1 183 1 1 0 .abs_section_183 + _CAN1CTL0 180 1 1 0 .abs_section_180 + _CAN1CTL1 181 1 1 0 .abs_section_181 + _CAN1IDAC 18B 1 1 0 .abs_section_18b + _CAN1IDAR0 190 1 1 0 .abs_section_190 + _CAN1IDAR1 191 1 1 0 .abs_section_191 + _CAN1IDAR2 192 1 1 0 .abs_section_192 + _CAN1IDAR3 193 1 1 0 .abs_section_193 + _CAN1IDAR4 198 1 1 0 .abs_section_198 + _CAN1IDAR5 199 1 1 0 .abs_section_199 + _CAN1IDAR6 19A 1 1 0 .abs_section_19a + _CAN1IDAR7 19B 1 1 0 .abs_section_19b + _CAN1IDMR0 194 1 1 0 .abs_section_194 + _CAN1IDMR1 195 1 1 0 .abs_section_195 + _CAN1IDMR2 196 1 1 0 .abs_section_196 + _CAN1IDMR3 197 1 1 0 .abs_section_197 + _CAN1IDMR4 19C 1 1 0 .abs_section_19c + _CAN1IDMR5 19D 1 1 0 .abs_section_19d + _CAN1IDMR6 19E 1 1 0 .abs_section_19e + _CAN1IDMR7 19F 1 1 0 .abs_section_19f + _CAN1RFLG 184 1 1 0 .abs_section_184 + _CAN1RIER 185 1 1 0 .abs_section_185 + _CAN1RXDLR 1AC 1 1 0 .abs_section_1ac + _CAN1RXDSR0 1A4 1 1 0 .abs_section_1a4 + _CAN1RXDSR1 1A5 1 1 0 .abs_section_1a5 + _CAN1RXDSR2 1A6 1 1 0 .abs_section_1a6 + _CAN1RXDSR3 1A7 1 1 0 .abs_section_1a7 + _CAN1RXDSR4 1A8 1 1 0 .abs_section_1a8 + _CAN1RXDSR5 1A9 1 1 0 .abs_section_1a9 + _CAN1RXDSR6 1AA 1 1 0 .abs_section_1aa + _CAN1RXDSR7 1AB 1 1 0 .abs_section_1ab + _CAN1RXERR 18E 1 1 0 .abs_section_18e + _CAN1RXIDR0 1A0 1 1 0 .abs_section_1a0 + _CAN1RXIDR1 1A1 1 1 0 .abs_section_1a1 + _CAN1RXIDR2 1A2 1 1 0 .abs_section_1a2 + _CAN1RXIDR3 1A3 1 1 0 .abs_section_1a3 + _CAN1TAAK 189 1 1 0 .abs_section_189 + _CAN1TARQ 188 1 1 0 .abs_section_188 + _CAN1TBSEL 18A 1 1 0 .abs_section_18a + _CAN1TFLG 186 1 1 0 .abs_section_186 + _CAN1TIER 187 1 1 0 .abs_section_187 + _CAN1TXDLR 1BC 1 1 0 .abs_section_1bc + _CAN1TXDSR0 1B4 1 1 0 .abs_section_1b4 + _CAN1TXDSR1 1B5 1 1 0 .abs_section_1b5 + _CAN1TXDSR2 1B6 1 1 0 .abs_section_1b6 + _CAN1TXDSR3 1B7 1 1 0 .abs_section_1b7 + _CAN1TXDSR4 1B8 1 1 0 .abs_section_1b8 + _CAN1TXDSR5 1B9 1 1 0 .abs_section_1b9 + _CAN1TXDSR6 1BA 1 1 0 .abs_section_1ba + _CAN1TXDSR7 1BB 1 1 0 .abs_section_1bb + _CAN1TXERR 18F 1 1 0 .abs_section_18f + _CAN1TXIDR0 1B0 1 1 0 .abs_section_1b0 + _CAN1TXIDR1 1B1 1 1 0 .abs_section_1b1 + _CAN1TXIDR2 1B2 1 1 0 .abs_section_1b2 + _CAN1TXIDR3 1B3 1 1 0 .abs_section_1b3 + _CAN1TXTBPR 1BF 1 1 0 .abs_section_1bf + _CAN2BTR0 1C2 1 1 0 .abs_section_1c2 + _CAN2BTR1 1C3 1 1 0 .abs_section_1c3 + _CAN2CTL0 1C0 1 1 0 .abs_section_1c0 + _CAN2CTL1 1C1 1 1 0 .abs_section_1c1 + _CAN2IDAC 1CB 1 1 0 .abs_section_1cb + _CAN2IDAR0 1D0 1 1 0 .abs_section_1d0 + _CAN2IDAR1 1D1 1 1 0 .abs_section_1d1 + _CAN2IDAR2 1D2 1 1 0 .abs_section_1d2 + _CAN2IDAR3 1D3 1 1 0 .abs_section_1d3 + _CAN2IDAR4 1D8 1 1 0 .abs_section_1d8 + _CAN2IDAR5 1D9 1 1 0 .abs_section_1d9 + _CAN2IDAR6 1DA 1 1 0 .abs_section_1da + _CAN2IDAR7 1DB 1 1 0 .abs_section_1db + _CAN2IDMR0 1D4 1 1 0 .abs_section_1d4 + _CAN2IDMR1 1D5 1 1 0 .abs_section_1d5 + _CAN2IDMR2 1D6 1 1 0 .abs_section_1d6 + _CAN2IDMR3 1D7 1 1 0 .abs_section_1d7 + _CAN2IDMR4 1DC 1 1 0 .abs_section_1dc + _CAN2IDMR5 1DD 1 1 0 .abs_section_1dd + _CAN2IDMR6 1DE 1 1 0 .abs_section_1de + _CAN2IDMR7 1DF 1 1 0 .abs_section_1df + _CAN2RFLG 1C4 1 1 0 .abs_section_1c4 + _CAN2RIER 1C5 1 1 0 .abs_section_1c5 + _CAN2RXDLR 1EC 1 1 0 .abs_section_1ec + _CAN2RXDSR0 1E4 1 1 0 .abs_section_1e4 + _CAN2RXDSR1 1E5 1 1 0 .abs_section_1e5 + _CAN2RXDSR2 1E6 1 1 0 .abs_section_1e6 + _CAN2RXDSR3 1E7 1 1 0 .abs_section_1e7 + _CAN2RXDSR4 1E8 1 1 0 .abs_section_1e8 + _CAN2RXDSR5 1E9 1 1 0 .abs_section_1e9 + _CAN2RXDSR6 1EA 1 1 0 .abs_section_1ea + _CAN2RXDSR7 1EB 1 1 0 .abs_section_1eb + _CAN2RXERR 1CE 1 1 0 .abs_section_1ce + _CAN2RXIDR0 1E0 1 1 0 .abs_section_1e0 + _CAN2RXIDR1 1E1 1 1 0 .abs_section_1e1 + _CAN2RXIDR2 1E2 1 1 0 .abs_section_1e2 + _CAN2RXIDR3 1E3 1 1 0 .abs_section_1e3 + _CAN2TAAK 1C9 1 1 0 .abs_section_1c9 + _CAN2TARQ 1C8 1 1 0 .abs_section_1c8 + _CAN2TBSEL 1CA 1 1 0 .abs_section_1ca + _CAN2TFLG 1C6 1 1 0 .abs_section_1c6 + _CAN2TIER 1C7 1 1 0 .abs_section_1c7 + _CAN2TXDLR 1FC 1 1 0 .abs_section_1fc + _CAN2TXDSR0 1F4 1 1 0 .abs_section_1f4 + _CAN2TXDSR1 1F5 1 1 0 .abs_section_1f5 + _CAN2TXDSR2 1F6 1 1 0 .abs_section_1f6 + _CAN2TXDSR3 1F7 1 1 0 .abs_section_1f7 + _CAN2TXDSR4 1F8 1 1 0 .abs_section_1f8 + _CAN2TXDSR5 1F9 1 1 0 .abs_section_1f9 + _CAN2TXDSR6 1FA 1 1 0 .abs_section_1fa + _CAN2TXDSR7 1FB 1 1 0 .abs_section_1fb + _CAN2TXERR 1CF 1 1 0 .abs_section_1cf + _CAN2TXIDR0 1F0 1 1 0 .abs_section_1f0 + _CAN2TXIDR1 1F1 1 1 0 .abs_section_1f1 + _CAN2TXIDR2 1F2 1 1 0 .abs_section_1f2 + _CAN2TXIDR3 1F3 1 1 0 .abs_section_1f3 + _CAN2TXTBPR 1FF 1 1 0 .abs_section_1ff + _CAN3BTR0 202 1 1 0 .abs_section_202 + _CAN3BTR1 203 1 1 0 .abs_section_203 + _CAN3CTL0 200 1 1 0 .abs_section_200 + _CAN3CTL1 201 1 1 0 .abs_section_201 + _CAN3IDAC 20B 1 1 0 .abs_section_20b + _CAN3IDAR0 210 1 1 0 .abs_section_210 + _CAN3IDAR1 211 1 1 0 .abs_section_211 + _CAN3IDAR2 212 1 1 0 .abs_section_212 + _CAN3IDAR3 213 1 1 0 .abs_section_213 + _CAN3IDAR4 218 1 1 0 .abs_section_218 + _CAN3IDAR5 219 1 1 0 .abs_section_219 + _CAN3IDAR6 21A 1 1 0 .abs_section_21a + _CAN3IDAR7 21B 1 1 0 .abs_section_21b + _CAN3IDMR0 214 1 1 0 .abs_section_214 + _CAN3IDMR1 215 1 1 0 .abs_section_215 + _CAN3IDMR2 216 1 1 0 .abs_section_216 + _CAN3IDMR3 217 1 1 0 .abs_section_217 + _CAN3IDMR4 21C 1 1 0 .abs_section_21c + _CAN3IDMR5 21D 1 1 0 .abs_section_21d + _CAN3IDMR6 21E 1 1 0 .abs_section_21e + _CAN3IDMR7 21F 1 1 0 .abs_section_21f + _CAN3RFLG 204 1 1 0 .abs_section_204 + _CAN3RIER 205 1 1 0 .abs_section_205 + _CAN3RXDLR 22C 1 1 0 .abs_section_22c + _CAN3RXDSR0 224 1 1 0 .abs_section_224 + _CAN3RXDSR1 225 1 1 0 .abs_section_225 + _CAN3RXDSR2 226 1 1 0 .abs_section_226 + _CAN3RXDSR3 227 1 1 0 .abs_section_227 + _CAN3RXDSR4 228 1 1 0 .abs_section_228 + _CAN3RXDSR5 229 1 1 0 .abs_section_229 + _CAN3RXDSR6 22A 1 1 0 .abs_section_22a + _CAN3RXDSR7 22B 1 1 0 .abs_section_22b + _CAN3RXERR 20E 1 1 0 .abs_section_20e + _CAN3RXIDR0 220 1 1 0 .abs_section_220 + _CAN3RXIDR1 221 1 1 0 .abs_section_221 + _CAN3RXIDR2 222 1 1 0 .abs_section_222 + _CAN3RXIDR3 223 1 1 0 .abs_section_223 + _CAN3TAAK 209 1 1 0 .abs_section_209 + _CAN3TARQ 208 1 1 0 .abs_section_208 + _CAN3TBSEL 20A 1 1 0 .abs_section_20a + _CAN3TFLG 206 1 1 0 .abs_section_206 + _CAN3TIER 207 1 1 0 .abs_section_207 + _CAN3TXDLR 23C 1 1 0 .abs_section_23c + _CAN3TXDSR0 234 1 1 0 .abs_section_234 + _CAN3TXDSR1 235 1 1 0 .abs_section_235 + _CAN3TXDSR2 236 1 1 0 .abs_section_236 + _CAN3TXDSR3 237 1 1 0 .abs_section_237 + _CAN3TXDSR4 238 1 1 0 .abs_section_238 + _CAN3TXDSR5 239 1 1 0 .abs_section_239 + _CAN3TXDSR6 23A 1 1 0 .abs_section_23a + _CAN3TXDSR7 23B 1 1 0 .abs_section_23b + _CAN3TXERR 20F 1 1 0 .abs_section_20f + _CAN3TXIDR0 230 1 1 0 .abs_section_230 + _CAN3TXIDR1 231 1 1 0 .abs_section_231 + _CAN3TXIDR2 232 1 1 0 .abs_section_232 + _CAN3TXIDR3 233 1 1 0 .abs_section_233 + _CAN3TXTBPR 23F 1 1 0 .abs_section_23f + _CAN4BTR0 282 1 1 0 .abs_section_282 + _CAN4BTR1 283 1 1 0 .abs_section_283 + _CAN4CTL0 280 1 1 0 .abs_section_280 + _CAN4CTL1 281 1 1 0 .abs_section_281 + _CAN4IDAC 28B 1 1 0 .abs_section_28b + _CAN4IDAR0 290 1 1 0 .abs_section_290 + _CAN4IDAR1 291 1 1 0 .abs_section_291 + _CAN4IDAR2 292 1 1 0 .abs_section_292 + _CAN4IDAR3 293 1 1 0 .abs_section_293 + _CAN4IDAR4 298 1 1 0 .abs_section_298 + _CAN4IDAR5 299 1 1 0 .abs_section_299 + _CAN4IDAR6 29A 1 1 0 .abs_section_29a + _CAN4IDAR7 29B 1 1 0 .abs_section_29b + _CAN4IDMR0 294 1 1 0 .abs_section_294 + _CAN4IDMR1 295 1 1 0 .abs_section_295 + _CAN4IDMR2 296 1 1 0 .abs_section_296 + _CAN4IDMR3 297 1 1 0 .abs_section_297 + _CAN4IDMR4 29C 1 1 0 .abs_section_29c + _CAN4IDMR5 29D 1 1 0 .abs_section_29d + _CAN4IDMR6 29E 1 1 0 .abs_section_29e + _CAN4IDMR7 29F 1 1 0 .abs_section_29f + _CAN4RFLG 284 1 1 0 .abs_section_284 + _CAN4RIER 285 1 1 0 .abs_section_285 + _CAN4RXDLR 2AC 1 1 0 .abs_section_2ac + _CAN4RXDSR0 2A4 1 1 0 .abs_section_2a4 + _CAN4RXDSR1 2A5 1 1 0 .abs_section_2a5 + _CAN4RXDSR2 2A6 1 1 0 .abs_section_2a6 + _CAN4RXDSR3 2A7 1 1 0 .abs_section_2a7 + _CAN4RXDSR4 2A8 1 1 0 .abs_section_2a8 + _CAN4RXDSR5 2A9 1 1 0 .abs_section_2a9 + _CAN4RXDSR6 2AA 1 1 0 .abs_section_2aa + _CAN4RXDSR7 2AB 1 1 0 .abs_section_2ab + _CAN4RXERR 28E 1 1 0 .abs_section_28e + _CAN4RXIDR0 2A0 1 1 0 .abs_section_2a0 + _CAN4RXIDR1 2A1 1 1 0 .abs_section_2a1 + _CAN4RXIDR2 2A2 1 1 0 .abs_section_2a2 + _CAN4RXIDR3 2A3 1 1 0 .abs_section_2a3 + _CAN4TAAK 289 1 1 0 .abs_section_289 + _CAN4TARQ 288 1 1 0 .abs_section_288 + _CAN4TBSEL 28A 1 1 0 .abs_section_28a + _CAN4TFLG 286 1 1 0 .abs_section_286 + _CAN4TIER 287 1 1 0 .abs_section_287 + _CAN4TXDLR 2BC 1 1 0 .abs_section_2bc + _CAN4TXDSR0 2B4 1 1 0 .abs_section_2b4 + _CAN4TXDSR1 2B5 1 1 0 .abs_section_2b5 + _CAN4TXDSR2 2B6 1 1 0 .abs_section_2b6 + _CAN4TXDSR3 2B7 1 1 0 .abs_section_2b7 + _CAN4TXDSR4 2B8 1 1 0 .abs_section_2b8 + _CAN4TXDSR5 2B9 1 1 0 .abs_section_2b9 + _CAN4TXDSR6 2BA 1 1 0 .abs_section_2ba + _CAN4TXDSR7 2BB 1 1 0 .abs_section_2bb + _CAN4TXERR 28F 1 1 0 .abs_section_28f + _CAN4TXIDR0 2B0 1 1 0 .abs_section_2b0 + _CAN4TXIDR1 2B1 1 1 0 .abs_section_2b1 + _CAN4TXIDR2 2B2 1 1 0 .abs_section_2b2 + _CAN4TXIDR3 2B3 1 1 0 .abs_section_2b3 + _CAN4TXTBPR 2BF 1 1 0 .abs_section_2bf + _CFORC 41 1 1 0 .abs_section_41 + _CLKSEL 39 1 1 3 .abs_section_39 + _COPCTL 3C 1 1 0 .abs_section_3c + _CRGFLG 37 1 1 1 .abs_section_37 + _CRGINT 38 1 1 0 .abs_section_38 + _CTCTL 3E 1 1 0 .abs_section_3e + _CTFLG 36 1 1 0 .abs_section_36 + _DDRE 9 1 1 0 .abs_section_9 + _DDRH 262 1 1 0 .abs_section_262 + _DDRJ 26A 1 1 0 .abs_section_26a + _DDRK 33 1 1 0 .abs_section_33 + _DDRM 252 1 1 0 .abs_section_252 + _DDRP 25A 1 1 0 .abs_section_25a + _DDRS 24A 1 1 2 .abs_section_24a + _DDRT 242 1 1 0 .abs_section_242 + _DLCBARD EC 1 1 0 .abs_section_ec + _DLCBCR1 E8 1 1 0 .abs_section_e8 + _DLCBCR2 EA 1 1 0 .abs_section_ea + _DLCBDR EB 1 1 0 .abs_section_eb + _DLCBRSR ED 1 1 0 .abs_section_ed + _DLCBSVR E9 1 1 0 .abs_section_e9 + _DLCSCR EE 1 1 0 .abs_section_ee + _DLYCT 69 1 1 0 .abs_section_69 + _EBICTL E 1 1 0 .abs_section_e + _ECLKDIV 110 1 1 0 .abs_section_110 + _ECMD 116 1 1 0 .abs_section_116 + _ECNFG 113 1 1 0 .abs_section_113 + _EPROT 114 1 1 0 .abs_section_114 + _ESTAT 115 1 1 0 .abs_section_115 + _FCLKDIV 100 1 1 0 .abs_section_100 + _FCMD 106 1 1 0 .abs_section_106 + _FCNFG 103 1 1 0 .abs_section_103 + _FORBYP 3D 1 1 0 .abs_section_3d + _FPROT 104 1 1 0 .abs_section_104 + _FSEC 101 1 1 0 .abs_section_101 + _FSTAT 105 1 1 0 .abs_section_105 + _HPRIO 1F 1 1 0 .abs_section_1f + _IBAD E0 1 1 0 .abs_section_e0 + _IBCR E2 1 1 0 .abs_section_e2 + _IBDR E4 1 1 0 .abs_section_e4 + _IBFD E1 1 1 0 .abs_section_e1 + _IBSR E3 1 1 0 .abs_section_e3 + _ICOVW 6A 1 1 0 .abs_section_6a + _ICPAR 68 1 1 0 .abs_section_68 + _ICSYS 6B 1 1 1 .abs_section_6b + _INITEE 12 1 1 1 .abs_section_12 + _INITRG 11 1 1 0 .abs_section_11 + _INITRM 10 1 1 1 .abs_section_10 + _INTCR 1E 1 1 1 .abs_section_1e + _ITCR 15 1 1 0 .abs_section_15 + _ITEST 16 1 1 0 .abs_section_16 + _MCCTL 66 1 1 1 .abs_section_66 + _MCFLG 67 1 1 0 .abs_section_67 + _MEMSIZ0 1C 1 1 0 .abs_section_1c + _MEMSIZ1 1D 1 1 0 .abs_section_1d + _MISC 13 1 1 1 .abs_section_13 + _MODE B 1 1 0 .abs_section_b + _MODRR 257 1 1 0 .abs_section_257 + _MTST0 14 1 1 0 .abs_section_14 + _MTST1 17 1 1 0 .abs_section_17 + _OC7D 43 1 1 0 .abs_section_43 + _OC7M 42 1 1 0 .abs_section_42 + _PACTL 60 1 1 0 .abs_section_60 + _PAFLG 61 1 1 0 .abs_section_61 + _PARTIDH 1A 1 1 0 .abs_section_1a + _PARTIDL 1B 1 1 0 .abs_section_1b + _PBCTL 70 1 1 0 .abs_section_70 + _PBFLG 71 1 1 0 .abs_section_71 + _PEAR A 1 1 0 .abs_section_a + _PERH 264 1 1 0 .abs_section_264 + _PERJ 26C 1 1 0 .abs_section_26c + _PERM 254 1 1 0 .abs_section_254 + _PERP 25C 1 1 0 .abs_section_25c + _PERS 24C 1 1 0 .abs_section_24c + _PERT 244 1 1 0 .abs_section_244 + _PIEH 266 1 1 0 .abs_section_266 + _PIEJ 26E 1 1 0 .abs_section_26e + _PIEP 25E 1 1 0 .abs_section_25e + _PIFH 267 1 1 0 .abs_section_267 + _PIFJ 26F 1 1 0 .abs_section_26f + _PIFP 25F 1 1 0 .abs_section_25f + _PLLCTL 3A 1 1 3 .abs_section_3a + _PORTAD0 8F 1 1 0 .abs_section_8f + _PORTAD1 12F 1 1 0 .abs_section_12f + _PORTE 8 1 1 0 .abs_section_8 + _PORTK 32 1 1 0 .abs_section_32 + _PPAGE 30 1 1 0 .abs_section_30 + _PPSH 265 1 1 0 .abs_section_265 + _PPSJ 26D 1 1 0 .abs_section_26d + _PPSM 255 1 1 0 .abs_section_255 + _PPSP 25D 1 1 0 .abs_section_25d + _PPSS 24D 1 1 0 .abs_section_24d + _PPST 245 1 1 0 .abs_section_245 + _PTH 260 1 1 0 .abs_section_260 + _PTIH 261 1 1 0 .abs_section_261 + _PTIJ 269 1 1 0 .abs_section_269 + _PTIM 251 1 1 0 .abs_section_251 + _PTIP 259 1 1 0 .abs_section_259 + _PTIS 249 1 1 0 .abs_section_249 + _PTIT 241 1 1 0 .abs_section_241 + _PTJ 268 1 1 0 .abs_section_268 + _PTM 250 1 1 0 .abs_section_250 + _PTP 258 1 1 0 .abs_section_258 + _PTS 248 1 1 1 .abs_section_248 + _PTT 240 1 1 0 .abs_section_240 + _PUCR C 1 1 0 .abs_section_c + _PWMCAE A4 1 1 0 .abs_section_a4 + _PWMCLK A2 1 1 0 .abs_section_a2 + _PWMCTL A5 1 1 1 .abs_section_a5 + _PWME A0 1 1 0 .abs_section_a0 + _PWMPOL A1 1 1 0 .abs_section_a1 + _PWMPRCLK A3 1 1 0 .abs_section_a3 + _PWMSCLA A8 1 1 0 .abs_section_a8 + _PWMSCLB A9 1 1 0 .abs_section_a9 + _PWMSDN C4 1 1 1 .abs_section_c4 + _RDRH 263 1 1 0 .abs_section_263 + _RDRIV D 1 1 0 .abs_section_d + _RDRJ 26B 1 1 0 .abs_section_26b + _RDRM 253 1 1 0 .abs_section_253 + _RDRP 25B 1 1 0 .abs_section_25b + _RDRS 24B 1 1 0 .abs_section_24b + _RDRT 243 1 1 0 .abs_section_243 + _REFDV 35 1 1 1 .abs_section_35 + _RTICTL 3B 1 1 0 .abs_section_3b + _SCI0CR1 CA 1 1 1 .abs_section_ca + _SCI0CR2 CB 1 1 7 .abs_section_cb + _SCI0DRH CE 1 1 0 .abs_section_ce + _SCI0DRL CF 1 1 3 .abs_section_cf + _SCI0SR1 CC 1 1 2 .abs_section_cc + _SCI0SR2 CD 1 1 1 .abs_section_cd + _SCI1CR1 D2 1 1 0 .abs_section_d2 + _SCI1CR2 D3 1 1 0 .abs_section_d3 + _SCI1DRH D6 1 1 0 .abs_section_d6 + _SCI1DRL D7 1 1 0 .abs_section_d7 + _SCI1SR1 D4 1 1 0 .abs_section_d4 + _SCI1SR2 D5 1 1 0 .abs_section_d5 + _SPI0BR DA 1 1 0 .abs_section_da + _SPI0CR1 D8 1 1 0 .abs_section_d8 + _SPI0CR2 D9 1 1 0 .abs_section_d9 + _SPI0DR DD 1 1 0 .abs_section_dd + _SPI0SR DB 1 1 0 .abs_section_db + _SPI1BR F2 1 1 0 .abs_section_f2 + _SPI1CR1 F0 1 1 0 .abs_section_f0 + _SPI1CR2 F1 1 1 0 .abs_section_f1 + _SPI1DR F5 1 1 0 .abs_section_f5 + _SPI1SR F3 1 1 0 .abs_section_f3 + _SPI2BR FA 1 1 0 .abs_section_fa + _SPI2CR1 F8 1 1 0 .abs_section_f8 + _SPI2CR2 F9 1 1 0 .abs_section_f9 + _SPI2DR FD 1 1 0 .abs_section_fd + _SPI2SR FB 1 1 0 .abs_section_fb + _SYNR 34 1 1 1 .abs_section_34 + _TCTL1 48 1 1 1 .abs_section_48 + _TCTL2 49 1 1 1 .abs_section_49 + _TCTL3 4A 1 1 0 .abs_section_4a + _TCTL4 4B 1 1 0 .abs_section_4b + _TFLG1 4E 1 1 2 .abs_section_4e + _TFLG2 4F 1 1 0 .abs_section_4f + _TIE 4C 1 1 2 .abs_section_4c + _TIMTST 6D 1 1 0 .abs_section_6d + _TIOS 40 1 1 1 .abs_section_40 + _TSCR1 46 1 1 3 .abs_section_46 + _TSCR2 4D 1 1 5 .abs_section_4d + _TTOV 47 1 1 1 .abs_section_47 + _WOMM 256 1 1 0 .abs_section_256 + _WOMS 24E 1 1 0 .abs_section_24e + _ATD0CTL23 82 2 2 0 .abs_section_82 + _ATD0CTL45 84 2 2 0 .abs_section_84 + _ATD0DR0 90 2 2 0 .abs_section_90 + _ATD0DR1 92 2 2 0 .abs_section_92 + _ATD0DR2 94 2 2 0 .abs_section_94 + _ATD0DR3 96 2 2 0 .abs_section_96 + _ATD0DR4 98 2 2 0 .abs_section_98 + _ATD0DR5 9A 2 2 0 .abs_section_9a + _ATD0DR6 9C 2 2 0 .abs_section_9c + _ATD0DR7 9E 2 2 0 .abs_section_9e + _ATD1CTL23 122 2 2 0 .abs_section_122 + _ATD1CTL45 124 2 2 0 .abs_section_124 + _ATD1DR0 130 2 2 0 .abs_section_130 + _ATD1DR1 132 2 2 0 .abs_section_132 + _ATD1DR2 134 2 2 0 .abs_section_134 + _ATD1DR3 136 2 2 0 .abs_section_136 + _ATD1DR4 138 2 2 0 .abs_section_138 + _ATD1DR5 13A 2 2 0 .abs_section_13a + _ATD1DR6 13C 2 2 0 .abs_section_13c + _ATD1DR7 13E 2 2 0 .abs_section_13e + _DDRAB 2 2 2 1 .abs_section_2 + _MCCNT 76 2 2 0 .abs_section_76 + _PA10H 74 2 2 0 .abs_section_74 + _PA32H 72 2 2 0 .abs_section_72 + _PACN10 64 2 2 0 .abs_section_64 + _PACN32 62 2 2 0 .abs_section_62 + _PORTAB 0 2 2 6 .abs_section_0 + _PWMCNT01 AC 2 2 0 .abs_section_ac + _PWMCNT23 AE 2 2 0 .abs_section_ae + _PWMCNT45 B0 2 2 0 .abs_section_b0 + _PWMCNT67 B2 2 2 0 .abs_section_b2 + _PWMDTY01 BC 2 2 0 .abs_section_bc + _PWMDTY23 BE 2 2 0 .abs_section_be + _PWMDTY45 C0 2 2 0 .abs_section_c0 + _PWMDTY67 C2 2 2 0 .abs_section_c2 + _PWMPER01 B4 2 2 0 .abs_section_b4 + _PWMPER23 B6 2 2 0 .abs_section_b6 + _PWMPER45 B8 2 2 0 .abs_section_b8 + _PWMPER67 BA 2 2 0 .abs_section_ba + _SCI0BD C8 2 2 2 .abs_section_c8 + _SCI1BD D0 2 2 0 .abs_section_d0 + _TC0 50 2 2 1 .abs_section_50 + _TC0H 78 2 2 0 .abs_section_78 + _TC1 52 2 2 0 .abs_section_52 + _TC1H 7A 2 2 0 .abs_section_7a + _TC2 54 2 2 0 .abs_section_54 + _TC2H 7C 2 2 0 .abs_section_7c + _TC3 56 2 2 0 .abs_section_56 + _TC3H 7E 2 2 0 .abs_section_7e + _TC4 58 2 2 0 .abs_section_58 + _TC5 5A 2 2 0 .abs_section_5a + _TC6 5C 2 2 0 .abs_section_5c + _TC7 5E 2 2 1 .abs_section_5e + _TCNT 44 2 2 0 .abs_section_44 +MODULE: -- Vectors.c.o -- +- PROCEDURES: +- VARIABLES: + _vect FF80 80 128 0 .abs_section_ff80 +MODULE: -- RTOSDemo.C.o -- +- PROCEDURES: + main 30809A 9 9 0 .text +- VARIABLES: +MODULE: -- main.c.o -- +- PROCEDURES: + vMain 3080A3 52 82 1 .text + vErrorChecks 3080F5 33 51 3 .text + prvCheckOtherTasksAreStillRunning 308128 49 73 2 .text + vApplicationIdleHook 308171 70 112 2 .text +- VARIABLES: + STRING.Check.1 C09A 6 6 1 .rodata1 + xLocalError 1001 1 1 2 .bss +MODULE: -- ParTest.c.o -- +- PROCEDURES: + vParTestSetLED 3081E1 22 34 4 .text + vParTestToggleLED 308203 14 20 10 .text +- VARIABLES: +MODULE: -- serial.c.o -- +- PROCEDURES: + xSerialPortInitMinimal 308217 24 36 2 .text + xSerialGetChar 30823B 17 23 2 .text + xSerialPutChar 318000 1D 29 2 ROM_PAGE31_524 + vCOM0_ISR C300 59 89 1 NON_BANKED +- VARIABLES: + xRxedChars 1002 2 2 3 .bss + xCharsForTx 1004 2 2 3 .bss +MODULE: -- tasks.c.o -- +- PROCEDURES: + xTaskCreate 31801D D9 217 48 ROM_PAGE31_524 + vTaskDelete 3180F6 4A 74 4 ROM_PAGE31_524 + vTaskDelayUntil 318140 78 120 6 ROM_PAGE31_524 + vTaskDelay 3181B8 4A 74 16 ROM_PAGE31_524 + uxTaskPriorityGet 318202 26 38 2 ROM_PAGE31_524 + vTaskPrioritySet 328000 6B 107 4 ROM_PAGE32_525 + vTaskSuspend 32806B 47 71 6 ROM_PAGE32_525 + vTaskResume 3280B2 5B 91 6 ROM_PAGE32_525 + vTaskStartScheduler 32810D 35 53 2 ROM_PAGE32_525 + vTaskSuspendAll 328142 13 19 26 ROM_PAGE32_525 + xTaskResumeAll 328155 A5 165 30 ROM_PAGE32_525 + xTaskGetTickCount 3281FA 17 23 6 ROM_PAGE32_525 + uxTaskGetNumberOfTasks 328211 17 23 4 ROM_PAGE32_525 + vTaskIncrementTick 338000 84 132 4 ROM_PAGE33_526 + vTaskSwitchContext 338084 5B 91 4 ROM_PAGE33_526 + vTaskPlaceOnEventList 3380DF 44 68 4 ROM_PAGE33_526 + xTaskRemoveFromEventList 338123 6F 111 8 ROM_PAGE33_526 + prvIdleTask 338192 12 18 3 ROM_PAGE33_526 + prvInitialiseTCBVariables 3381A4 4F 79 2 ROM_PAGE33_526 + prvInitialiseTaskLists 3381F3 41 65 2 ROM_PAGE33_526 + prvCheckTasksWaitingTermination 348000 55 85 2 ROM_PAGE34_527 + prvAllocateTCBAndStack 348055 37 55 2 ROM_PAGE34_527 + prvDeleteTCB 34808C 11 17 2 ROM_PAGE34_527 +- VARIABLES: + STRING.IDLE.2 C0A0 5 5 1 .rodata1 + pxCurrentTCB 1006 2 2 28 .bss + uxTasksDeleted 1008 1 1 3 .bss + uxCurrentNumberOfTasks 1009 1 1 5 .bss + xTickCount 100A 2 2 14 .bss + uxTopUsedPriority 100C 1 1 2 .bss + uxTopReadyPriority 100D 1 1 15 .bss + xSchedulerRunning 100E 1 1 3 .bss + uxSchedulerSuspended 100F 1 1 6 .bss + uxMissedTicks 1010 1 1 4 .bss + uxTaskNumber.1 1011 1 1 2 .bss + pxReadyTasksLists 1012 3C 60 11 .bss + xDelayedTaskList1 104E F 15 2 .bss + xDelayedTaskList2 105D F 15 2 .bss + pxDelayedTaskList 106C 2 2 8 .bss + pxOverflowDelayedTaskList 106E 2 2 6 .bss + xPendingReadyList 1070 F 15 4 .bss + xTasksWaitingTermination 107F F 15 5 .bss + xSuspendedTaskList 108E F 15 2 .bss +MODULE: -- queue.c.o -- +- PROCEDURES: + xQueueCreate 34809D 7C 124 14 ROM_PAGE34_527 + xQueueSend 348119 D4 212 9 ROM_PAGE34_527 + xQueueSendFromISR 3481ED 56 86 2 ROM_PAGE34_527 + xQueueReceive 358000 CE 206 9 ROM_PAGE35_528 + xQueueReceiveFromISR 3580CE 60 96 2 ROM_PAGE35_528 + uxQueueMessagesWaiting 35812E 1B 27 2 ROM_PAGE35_528 + prvUnlockQueue 358149 71 113 8 ROM_PAGE35_528 + prvIsQueueEmpty 3581BA 21 33 2 ROM_PAGE35_528 + prvIsQueueFull 3581DB 24 36 2 ROM_PAGE35_528 +- VARIABLES: +MODULE: -- list.c.o -- +- PROCEDURES: + vListInitialise 3581FF 20 32 6 ROM_PAGE35_528 + vListInitialiseItem 35821F 7 7 6 ROM_PAGE35_528 + vListInsertEnd 358226 27 39 16 ROM_PAGE35_528 + vListInsert 368000 5A 90 8 ROM_PAGE36_529 + vListRemove 36805A 23 35 32 ROM_PAGE36_529 +- VARIABLES: +MODULE: -- heap_2.c.o -- +- PROCEDURES: + pvPortMalloc 36807D B6 182 14 ROM_PAGE36_529 + vPortFree 368133 34 52 10 ROM_PAGE36_529 +- VARIABLES: + xHeapHasBeenInitialised.1 109D 1 1 2 .bss + xHeap 109E 2804 10244 2 .bss + xStart 38A2 4 4 6 .bss + xEnd 38A6 4 4 4 .bss +MODULE: -- TickTimer.C.o -- +- PROCEDURES: + SetCV 3B811C F 15 4 TickTimer_CODE + SetPV 3B812B C 12 2 TickTimer_CODE + HWEnDi 3B8137 8 8 4 TickTimer_CODE + TickTimer_Enable 3B813F 6 6 2 TickTimer_CODE + TickTimer_SetFreqHz 3B8145 51 81 2 TickTimer_CODE + TickTimer_Init 3B8196 15 21 2 TickTimer_CODE +- VARIABLES: + CmpHighVal 38F2 2 2 2 TickTimer_DATA +MODULE: -- PE_Timer.C.o -- +- PROCEDURES: + PE_Timer_LngHi1 368167 43 67 2 ROM_PAGE36_529 +- VARIABLES: +MODULE: -- Byte1.C.o -- +- PROCEDURES: + Byte1_GetMsk 3B81AB D 13 4 Byte1_CODE + Byte1_PutBit 3B81B8 1F 31 2 Byte1_CODE + Byte1_NegBit 3B81D7 11 17 2 Byte1_CODE +- VARIABLES: + Byte1_Table 38F4 8 8 1 Byte1_DATA +MODULE: -- flash.c.o -- +- PROCEDURES: + vStartLEDFlashTasks 3681AA 2A 42 2 ROM_PAGE36_529 + vLEDFlashTask 3681D4 57 87 3 ROM_PAGE36_529 +- VARIABLES: + STRING.LEDx.1 C0A5 5 5 1 .rodata1 + uxFlashTaskNumber 38AA 1 1 2 .bss +MODULE: -- dynamic.c.o -- +- PROCEDURES: + vStartDynamicPriorityTasks 378000 9B 155 2 ROM_PAGE37_530 + vLimitedIncrementTask 37809B 22 34 3 ROM_PAGE37_530 + vContinuousIncrementTask 3780BD 33 51 3 ROM_PAGE37_530 + vCounterControlTask 3780F0 A0 160 5 ROM_PAGE37_530 + vQueueSendWhenSuspendedTask 378190 38 56 3 ROM_PAGE37_530 + vQueueReceiveWhenSuspendedTask 3781C8 53 83 3 ROM_PAGE37_530 + xAreDynamicPriorityTasksStillRunning 37821B 27 39 2 ROM_PAGE37_530 +- VARIABLES: + STRING.CNT_INC.1 C0AA 8 8 1 .rodata1 + STRING.LIM_INC.2 C0B2 8 8 1 .rodata1 + STRING.C_CTRL.3 C0BA 7 7 1 .rodata1 + STRING.SUSP_TX.4 C0C1 8 8 1 .rodata1 + STRING.SUSP_RX.5 C0C9 8 8 1 .rodata1 + usCheckVariable 38AB 2 2 4 .bss + xSuspendedQueueSendError 38AD 1 1 2 .bss + xSuspendedQueueReceiveError 38AE 1 1 3 .bss + ulValueToSend.6 38AF 4 4 5 .bss + ulExpectedValue.7 38B3 4 4 6 .bss + usLastTaskCheck.9 38B7 2 2 2 .bss + xContinousIncrementHandle 38B9 2 2 5 .bss + xLimitedIncrementHandle 38BB 2 2 2 .bss + ulCounter 38BD 4 4 10 .bss + ulReceivedValue.8 38C1 4 4 3 .bss + xSuspendedTestQueue 38EC 2 2 3 .common +MODULE: -- PollQ.c.o -- +- PROCEDURES: + vStartPolledQueueTasks 388000 49 73 2 ROM_PAGE38_531 + vPolledQueueProducer 388049 4F 79 3 ROM_PAGE38_531 + vPolledQueueConsumer 388098 5C 92 3 ROM_PAGE38_531 + xArePollingQueuesStillRunning 3880F4 1D 29 2 ROM_PAGE38_531 +- VARIABLES: + STRING.QConsNB.2 C0D1 8 8 1 .rodata1 + STRING.QProdNB.3 C0D9 8 8 1 .rodata1 + xPollingConsumerCount 38C5 1 1 3 .bss + xPollingProducerCount 38C6 1 1 3 .bss + xPolledQueue.1 38C7 2 2 3 .bss +MODULE: -- comtest.c.o -- +- PROCEDURES: + vAltStartComTestTasks 388111 4D 77 2 ROM_PAGE38_531 + vComTxTask 38815E 51 81 3 ROM_PAGE38_531 + vComRxTask 3881AF 6A 106 3 ROM_PAGE38_531 + xAreComTestTasksStillRunning 388219 15 21 2 ROM_PAGE38_531 +- VARIABLES: + STRING.COMTx.1 C0E1 6 6 1 .rodata1 + STRING.COMRx.2 C0E7 6 6 1 .rodata1 + xPort 38C9 2 2 2 .bss + uxBaseLED 38CB 1 1 5 .bss + uxRxLoops 38CC 1 1 3 .bss +MODULE: -- COM0.C.o -- +- PROCEDURES: + HWEnDi 3B81E8 A 10 2 COM0_CODE + COM0_SetBaudRateMode 3B81F2 19 25 2 COM0_CODE + COM0_Init 3B820B 20 32 2 COM0_CODE +- VARIABLES: + COM0_PrescHigh.1 38FC 8 8 1 COM0_DATA + SerFlag 3904 2 2 1 COM0_DATA + PrescHigh 3906 2 2 2 COM0_DATA + NumMode 3908 1 1 2 COM0_DATA +MODULE: -- port.c.o -- +- PROCEDURES: + pxPortInitialiseStack 398000 31 49 2 ROM_PAGE39_532 + prvSetupTimerInterrupt 398031 C 12 2 ROM_PAGE39_532 + xPortStartScheduler 39803D 4 4 2 ROM_PAGE39_532 + xBankedStartScheduler C359 13 19 1 NON_BANKED + vPortYield C36C 1D 29 1 NON_BANKED + vPortTickInterrupt C389 25 37 1 NON_BANKED +- VARIABLES: + uxCriticalNesting 1000 1 1 101 .data +MODULE: -- integer.c.o -- +- PROCEDURES: + vStartIntegerMathTasks 398041 33 51 2 ROM_PAGE39_532 + vCompeteingIntMathTask 398074 87 135 3 ROM_PAGE39_532 + xAreIntegerMathsTaskStillRunning 3980FB 25 37 2 ROM_PAGE39_532 +- VARIABLES: + STRING.IntMath.1 C0ED 8 8 1 .rodata1 + xTaskCheck 38CD 1 1 3 .bss +MODULE: -- BlockQ.c.o -- +- PROCEDURES: + vStartBlockingQueueTasks 3A8000 143 323 7 ROM_PAGE3A_533 + vBlockingQueueProducer 3A8143 3A 58 9 ROM_PAGE3A_533 + vBlockingQueueConsumer 3A817D 45 69 9 ROM_PAGE3A_533 + xAreBlockingQueuesStillRunning 3A81C2 49 73 2 ROM_PAGE3A_533 +- VARIABLES: + STRING.QConsB1.1 C0F5 8 8 1 .rodata1 + STRING.QProdB2.2 C0FD 8 8 1 .rodata1 + STRING.QProdB3.3 C105 8 8 1 .rodata1 + STRING.QConsB4.4 C10D 8 8 1 .rodata1 + STRING.QProdB5.5 C115 8 8 1 .rodata1 + STRING.QConsB6.6 C11D 8 8 1 .rodata1 + sBlockingConsumerCount 38CE 6 6 5 .bss + sBlockingProducerCount 38D4 6 6 5 .bss + sLastBlockingConsumerCount.7 38DA 6 6 2 .bss + sLastBlockingProducerCount.8 38E0 6 6 2 .bss +MODULE: -- death.c.o -- +- PROCEDURES: + vCreateSuicidalTasks 3A820B 33 51 2 ROM_PAGE3A_533 + vSuicidalTask 3B8000 52 82 12 ROM_PAGE3B_534 + vCreateTasks 3B8052 94 148 4 ROM_PAGE3B_534 + xIsCreateTaskStillRunning 3B80E6 36 54 2 ROM_PAGE3B_534 +- VARIABLES: + STRING.CREATOR.1 C125 8 8 1 .rodata1 + STRING.SUICIDE1.2 C12D 9 9 1 .rodata1 + STRING.SUICIDE2.3 C136 9 9 1 .rodata1 + STRING.SUICIDE1.4 C13F 9 9 1 .rodata1 + STRING.SUICIDE2.5 C148 9 9 1 .rodata1 + usCreationCount 38E6 2 2 4 .bss + uxTasksRunningAtStart 38E8 1 1 4 .bss + usLastCreationCount.6 38E9 2 2 2 .bss + uxTasksRunningNow.7 38EB 1 1 1 .bss + xCreatedTask1 38EE 2 2 2 .common + xCreatedTask2 38F0 2 2 2 .common + +********************************************************************************************* +MODULE STATISTIC + Name Data Code Const +--------------------------------------------------------------------------------------------- + Start12.c.o 0 59 0 + STRING.C.o (ansibi.lib) 0 113 0 + rtshc12.c.o (ansibi.lib) 0 412 0 + Cpu.C.o 0 125 0 + IO_Map.C.o 577 0 0 + Vectors.c.o 0 0 128 + RTOSDemo.C.o 0 9 0 + main.c.o 1 318 6 + ParTest.c.o 0 54 0 + serial.c.o 4 177 0 + tasks.c.o 151 1796 5 + queue.c.o 0 933 0 + list.c.o 0 203 0 + heap_2.c.o 10253 234 0 + TickTimer.C.o 2 143 0 + PE_Timer.C.o 0 67 0 + Byte1.C.o 8 61 0 + flash.c.o 1 129 5 + dynamic.c.o 28 578 39 + PollQ.c.o 4 273 16 + comtest.c.o 4 285 12 + COM0.C.o 13 67 0 + port.c.o 1 150 0 + integer.c.o 1 223 8 + BlockQ.c.o 24 523 48 + death.c.o 10 335 44 + other 128 30 27 + +********************************************************************************************* +SECTION USE IN OBJECT-ALLOCATION SECTION +--------------------------------------------------------------------------------------------- +SECTION: ".text" + Init memcpy memset strncpy main vMain vErrorChecks + prvCheckOtherTasksAreStillRunning vApplicationIdleHook vParTestSetLED + vParTestToggleLED xSerialPortInitMinimal xSerialGetChar +SECTION: ".data" + uxCriticalNesting +SECTION: ".bss" + xLocalError xRxedChars xCharsForTx pxCurrentTCB uxTasksDeleted + uxCurrentNumberOfTasks xTickCount uxTopUsedPriority uxTopReadyPriority + xSchedulerRunning uxSchedulerSuspended uxMissedTicks uxTaskNumber.1 + pxReadyTasksLists xDelayedTaskList1 xDelayedTaskList2 pxDelayedTaskList + pxOverflowDelayedTaskList xPendingReadyList xTasksWaitingTermination + xSuspendedTaskList xHeapHasBeenInitialised.1 xHeap xStart xEnd + uxFlashTaskNumber usCheckVariable xSuspendedQueueSendError + xSuspendedQueueReceiveError ulValueToSend.6 ulExpectedValue.7 + usLastTaskCheck.9 xContinousIncrementHandle xLimitedIncrementHandle ulCounter + ulReceivedValue.8 xPollingConsumerCount xPollingProducerCount xPolledQueue.1 + xPort uxBaseLED uxRxLoops xTaskCheck sBlockingConsumerCount + sBlockingProducerCount sLastBlockingConsumerCount.7 + sLastBlockingProducerCount.8 usCreationCount uxTasksRunningAtStart + usLastCreationCount.6 uxTasksRunningNow.7 +SECTION: ".init" + _EntryPoint PE_low_level_init +SECTION: ".rodata1" + STRING.Check.1 STRING.IDLE.2 STRING.LEDx.1 STRING.CNT_INC.1 STRING.LIM_INC.2 + STRING.C_CTRL.3 STRING.SUSP_TX.4 STRING.SUSP_RX.5 STRING.QConsNB.2 + STRING.QProdNB.3 STRING.COMTx.1 STRING.COMRx.2 STRING.IntMath.1 + STRING.QConsB1.1 STRING.QProdB2.2 STRING.QProdB3.3 STRING.QConsB4.4 + STRING.QProdB5.5 STRING.QConsB6.6 STRING.CREATOR.1 STRING.SUICIDE1.2 + STRING.SUICIDE2.3 STRING.SUICIDE1.4 STRING.SUICIDE2.5 +SECTION: "NON_BANKED" + _Startup _LCMP _LCMP_P _LNEG _LINC _LMUL _lDivMod _LDIVU _NEG_P _LDIVS + Cpu_Interrupt vCOM0_ISR xBankedStartScheduler vPortYield vPortTickInterrupt +SECTION: ".common" + xSuspendedTestQueue xCreatedTask1 xCreatedTask2 +SECTION: "TickTimer_CODE" + SetCV SetPV HWEnDi TickTimer_Enable TickTimer_SetFreqHz TickTimer_Init +SECTION: "Byte1_CODE" + Byte1_GetMsk Byte1_PutBit Byte1_NegBit +SECTION: "COM0_CODE" + HWEnDi COM0_SetBaudRateMode COM0_Init +SECTION: ".abs_section_3f" + _ARMCOP +SECTION: ".abs_section_8d" + _ATD0DIEN +SECTION: ".abs_section_86" + _ATD0STAT0 +SECTION: ".abs_section_8b" + _ATD0STAT1 +SECTION: ".abs_section_12d" + _ATD1DIEN +SECTION: ".abs_section_126" + _ATD1STAT0 +SECTION: ".abs_section_12b" + _ATD1STAT1 +SECTION: ".abs_section_ff06" + _BDMCCR +SECTION: ".abs_section_ff07" + _BDMINR +SECTION: ".abs_section_ff01" + _BDMSTS +SECTION: ".abs_section_2b" + _BKP0H +SECTION: ".abs_section_2c" + _BKP0L +SECTION: ".abs_section_2a" + _BKP0X +SECTION: ".abs_section_2e" + _BKP1H +SECTION: ".abs_section_2f" + _BKP1L +SECTION: ".abs_section_2d" + _BKP1X +SECTION: ".abs_section_28" + _BKPCT0 +SECTION: ".abs_section_29" + _BKPCT1 +SECTION: ".abs_section_142" + _CAN0BTR0 +SECTION: ".abs_section_143" + _CAN0BTR1 +SECTION: ".abs_section_140" + _CAN0CTL0 +SECTION: ".abs_section_141" + _CAN0CTL1 +SECTION: ".abs_section_14b" + _CAN0IDAC +SECTION: ".abs_section_150" + _CAN0IDAR0 +SECTION: ".abs_section_151" + _CAN0IDAR1 +SECTION: ".abs_section_152" + _CAN0IDAR2 +SECTION: ".abs_section_153" + _CAN0IDAR3 +SECTION: ".abs_section_158" + _CAN0IDAR4 +SECTION: ".abs_section_159" + _CAN0IDAR5 +SECTION: ".abs_section_15a" + _CAN0IDAR6 +SECTION: ".abs_section_15b" + _CAN0IDAR7 +SECTION: ".abs_section_154" + _CAN0IDMR0 +SECTION: ".abs_section_155" + _CAN0IDMR1 +SECTION: ".abs_section_156" + _CAN0IDMR2 +SECTION: ".abs_section_157" + _CAN0IDMR3 +SECTION: ".abs_section_15c" + _CAN0IDMR4 +SECTION: ".abs_section_15d" + _CAN0IDMR5 +SECTION: ".abs_section_15e" + _CAN0IDMR6 +SECTION: ".abs_section_15f" + _CAN0IDMR7 +SECTION: ".abs_section_144" + _CAN0RFLG +SECTION: ".abs_section_145" + _CAN0RIER +SECTION: ".abs_section_16c" + _CAN0RXDLR +SECTION: ".abs_section_164" + _CAN0RXDSR0 +SECTION: ".abs_section_165" + _CAN0RXDSR1 +SECTION: ".abs_section_166" + _CAN0RXDSR2 +SECTION: ".abs_section_167" + _CAN0RXDSR3 +SECTION: ".abs_section_168" + _CAN0RXDSR4 +SECTION: ".abs_section_169" + _CAN0RXDSR5 +SECTION: ".abs_section_16a" + _CAN0RXDSR6 +SECTION: ".abs_section_16b" + _CAN0RXDSR7 +SECTION: ".abs_section_14e" + _CAN0RXERR +SECTION: ".abs_section_160" + _CAN0RXIDR0 +SECTION: ".abs_section_161" + _CAN0RXIDR1 +SECTION: ".abs_section_162" + _CAN0RXIDR2 +SECTION: ".abs_section_163" + _CAN0RXIDR3 +SECTION: ".abs_section_149" + _CAN0TAAK +SECTION: ".abs_section_148" + _CAN0TARQ +SECTION: ".abs_section_14a" + _CAN0TBSEL +SECTION: ".abs_section_146" + _CAN0TFLG +SECTION: ".abs_section_147" + _CAN0TIER +SECTION: ".abs_section_17c" + _CAN0TXDLR +SECTION: ".abs_section_174" + _CAN0TXDSR0 +SECTION: ".abs_section_175" + _CAN0TXDSR1 +SECTION: ".abs_section_176" + _CAN0TXDSR2 +SECTION: ".abs_section_177" + _CAN0TXDSR3 +SECTION: ".abs_section_178" + _CAN0TXDSR4 +SECTION: ".abs_section_179" + _CAN0TXDSR5 +SECTION: ".abs_section_17a" + _CAN0TXDSR6 +SECTION: ".abs_section_17b" + _CAN0TXDSR7 +SECTION: ".abs_section_14f" + _CAN0TXERR +SECTION: ".abs_section_170" + _CAN0TXIDR0 +SECTION: ".abs_section_171" + _CAN0TXIDR1 +SECTION: ".abs_section_172" + _CAN0TXIDR2 +SECTION: ".abs_section_173" + _CAN0TXIDR3 +SECTION: ".abs_section_17f" + _CAN0TXTBPR +SECTION: ".abs_section_182" + _CAN1BTR0 +SECTION: ".abs_section_183" + _CAN1BTR1 +SECTION: ".abs_section_180" + _CAN1CTL0 +SECTION: ".abs_section_181" + _CAN1CTL1 +SECTION: ".abs_section_18b" + _CAN1IDAC +SECTION: ".abs_section_190" + _CAN1IDAR0 +SECTION: ".abs_section_191" + _CAN1IDAR1 +SECTION: ".abs_section_192" + _CAN1IDAR2 +SECTION: ".abs_section_193" + _CAN1IDAR3 +SECTION: ".abs_section_198" + _CAN1IDAR4 +SECTION: ".abs_section_199" + _CAN1IDAR5 +SECTION: ".abs_section_19a" + _CAN1IDAR6 +SECTION: ".abs_section_19b" + _CAN1IDAR7 +SECTION: ".abs_section_194" + _CAN1IDMR0 +SECTION: ".abs_section_195" + _CAN1IDMR1 +SECTION: ".abs_section_196" + _CAN1IDMR2 +SECTION: ".abs_section_197" + _CAN1IDMR3 +SECTION: ".abs_section_19c" + _CAN1IDMR4 +SECTION: ".abs_section_19d" + _CAN1IDMR5 +SECTION: ".abs_section_19e" + _CAN1IDMR6 +SECTION: ".abs_section_19f" + _CAN1IDMR7 +SECTION: ".abs_section_184" + _CAN1RFLG +SECTION: ".abs_section_185" + _CAN1RIER +SECTION: ".abs_section_1ac" + _CAN1RXDLR +SECTION: ".abs_section_1a4" + _CAN1RXDSR0 +SECTION: ".abs_section_1a5" + _CAN1RXDSR1 +SECTION: ".abs_section_1a6" + _CAN1RXDSR2 +SECTION: ".abs_section_1a7" + _CAN1RXDSR3 +SECTION: ".abs_section_1a8" + _CAN1RXDSR4 +SECTION: ".abs_section_1a9" + _CAN1RXDSR5 +SECTION: ".abs_section_1aa" + _CAN1RXDSR6 +SECTION: ".abs_section_1ab" + _CAN1RXDSR7 +SECTION: ".abs_section_18e" + _CAN1RXERR +SECTION: ".abs_section_1a0" + _CAN1RXIDR0 +SECTION: ".abs_section_1a1" + _CAN1RXIDR1 +SECTION: ".abs_section_1a2" + _CAN1RXIDR2 +SECTION: ".abs_section_1a3" + _CAN1RXIDR3 +SECTION: ".abs_section_189" + _CAN1TAAK +SECTION: ".abs_section_188" + _CAN1TARQ +SECTION: ".abs_section_18a" + _CAN1TBSEL +SECTION: ".abs_section_186" + _CAN1TFLG +SECTION: ".abs_section_187" + _CAN1TIER +SECTION: ".abs_section_1bc" + _CAN1TXDLR +SECTION: ".abs_section_1b4" + _CAN1TXDSR0 +SECTION: ".abs_section_1b5" + _CAN1TXDSR1 +SECTION: ".abs_section_1b6" + _CAN1TXDSR2 +SECTION: ".abs_section_1b7" + _CAN1TXDSR3 +SECTION: ".abs_section_1b8" + _CAN1TXDSR4 +SECTION: ".abs_section_1b9" + _CAN1TXDSR5 +SECTION: ".abs_section_1ba" + _CAN1TXDSR6 +SECTION: ".abs_section_1bb" + _CAN1TXDSR7 +SECTION: ".abs_section_18f" + _CAN1TXERR +SECTION: ".abs_section_1b0" + _CAN1TXIDR0 +SECTION: ".abs_section_1b1" + _CAN1TXIDR1 +SECTION: ".abs_section_1b2" + _CAN1TXIDR2 +SECTION: ".abs_section_1b3" + _CAN1TXIDR3 +SECTION: ".abs_section_1bf" + _CAN1TXTBPR +SECTION: ".abs_section_1c2" + _CAN2BTR0 +SECTION: ".abs_section_1c3" + _CAN2BTR1 +SECTION: ".abs_section_1c0" + _CAN2CTL0 +SECTION: ".abs_section_1c1" + _CAN2CTL1 +SECTION: ".abs_section_1cb" + _CAN2IDAC +SECTION: ".abs_section_1d0" + _CAN2IDAR0 +SECTION: ".abs_section_1d1" + _CAN2IDAR1 +SECTION: ".abs_section_1d2" + _CAN2IDAR2 +SECTION: ".abs_section_1d3" + _CAN2IDAR3 +SECTION: ".abs_section_1d8" + _CAN2IDAR4 +SECTION: ".abs_section_1d9" + _CAN2IDAR5 +SECTION: ".abs_section_1da" + _CAN2IDAR6 +SECTION: ".abs_section_1db" + _CAN2IDAR7 +SECTION: ".abs_section_1d4" + _CAN2IDMR0 +SECTION: ".abs_section_1d5" + _CAN2IDMR1 +SECTION: ".abs_section_1d6" + _CAN2IDMR2 +SECTION: ".abs_section_1d7" + _CAN2IDMR3 +SECTION: ".abs_section_1dc" + _CAN2IDMR4 +SECTION: ".abs_section_1dd" + _CAN2IDMR5 +SECTION: ".abs_section_1de" + _CAN2IDMR6 +SECTION: ".abs_section_1df" + _CAN2IDMR7 +SECTION: ".abs_section_1c4" + _CAN2RFLG +SECTION: ".abs_section_1c5" + _CAN2RIER +SECTION: ".abs_section_1ec" + _CAN2RXDLR +SECTION: ".abs_section_1e4" + _CAN2RXDSR0 +SECTION: ".abs_section_1e5" + _CAN2RXDSR1 +SECTION: ".abs_section_1e6" + _CAN2RXDSR2 +SECTION: ".abs_section_1e7" + _CAN2RXDSR3 +SECTION: ".abs_section_1e8" + _CAN2RXDSR4 +SECTION: ".abs_section_1e9" + _CAN2RXDSR5 +SECTION: ".abs_section_1ea" + _CAN2RXDSR6 +SECTION: ".abs_section_1eb" + _CAN2RXDSR7 +SECTION: ".abs_section_1ce" + _CAN2RXERR +SECTION: ".abs_section_1e0" + _CAN2RXIDR0 +SECTION: ".abs_section_1e1" + _CAN2RXIDR1 +SECTION: ".abs_section_1e2" + _CAN2RXIDR2 +SECTION: ".abs_section_1e3" + _CAN2RXIDR3 +SECTION: ".abs_section_1c9" + _CAN2TAAK +SECTION: ".abs_section_1c8" + _CAN2TARQ +SECTION: ".abs_section_1ca" + _CAN2TBSEL +SECTION: ".abs_section_1c6" + _CAN2TFLG +SECTION: ".abs_section_1c7" + _CAN2TIER +SECTION: ".abs_section_1fc" + _CAN2TXDLR +SECTION: ".abs_section_1f4" + _CAN2TXDSR0 +SECTION: ".abs_section_1f5" + _CAN2TXDSR1 +SECTION: ".abs_section_1f6" + _CAN2TXDSR2 +SECTION: ".abs_section_1f7" + _CAN2TXDSR3 +SECTION: ".abs_section_1f8" + _CAN2TXDSR4 +SECTION: ".abs_section_1f9" + _CAN2TXDSR5 +SECTION: ".abs_section_1fa" + _CAN2TXDSR6 +SECTION: ".abs_section_1fb" + _CAN2TXDSR7 +SECTION: ".abs_section_1cf" + _CAN2TXERR +SECTION: ".abs_section_1f0" + _CAN2TXIDR0 +SECTION: ".abs_section_1f1" + _CAN2TXIDR1 +SECTION: ".abs_section_1f2" + _CAN2TXIDR2 +SECTION: ".abs_section_1f3" + _CAN2TXIDR3 +SECTION: ".abs_section_1ff" + _CAN2TXTBPR +SECTION: ".abs_section_202" + _CAN3BTR0 +SECTION: ".abs_section_203" + _CAN3BTR1 +SECTION: ".abs_section_200" + _CAN3CTL0 +SECTION: ".abs_section_201" + _CAN3CTL1 +SECTION: ".abs_section_20b" + _CAN3IDAC +SECTION: ".abs_section_210" + _CAN3IDAR0 +SECTION: ".abs_section_211" + _CAN3IDAR1 +SECTION: ".abs_section_212" + _CAN3IDAR2 +SECTION: ".abs_section_213" + _CAN3IDAR3 +SECTION: ".abs_section_218" + _CAN3IDAR4 +SECTION: ".abs_section_219" + _CAN3IDAR5 +SECTION: ".abs_section_21a" + _CAN3IDAR6 +SECTION: ".abs_section_21b" + _CAN3IDAR7 +SECTION: ".abs_section_214" + _CAN3IDMR0 +SECTION: ".abs_section_215" + _CAN3IDMR1 +SECTION: ".abs_section_216" + _CAN3IDMR2 +SECTION: ".abs_section_217" + _CAN3IDMR3 +SECTION: ".abs_section_21c" + _CAN3IDMR4 +SECTION: ".abs_section_21d" + _CAN3IDMR5 +SECTION: ".abs_section_21e" + _CAN3IDMR6 +SECTION: ".abs_section_21f" + _CAN3IDMR7 +SECTION: ".abs_section_204" + _CAN3RFLG +SECTION: ".abs_section_205" + _CAN3RIER +SECTION: ".abs_section_22c" + _CAN3RXDLR +SECTION: ".abs_section_224" + _CAN3RXDSR0 +SECTION: ".abs_section_225" + _CAN3RXDSR1 +SECTION: ".abs_section_226" + _CAN3RXDSR2 +SECTION: ".abs_section_227" + _CAN3RXDSR3 +SECTION: ".abs_section_228" + _CAN3RXDSR4 +SECTION: ".abs_section_229" + _CAN3RXDSR5 +SECTION: ".abs_section_22a" + _CAN3RXDSR6 +SECTION: ".abs_section_22b" + _CAN3RXDSR7 +SECTION: ".abs_section_20e" + _CAN3RXERR +SECTION: ".abs_section_220" + _CAN3RXIDR0 +SECTION: ".abs_section_221" + _CAN3RXIDR1 +SECTION: ".abs_section_222" + _CAN3RXIDR2 +SECTION: ".abs_section_223" + _CAN3RXIDR3 +SECTION: ".abs_section_209" + _CAN3TAAK +SECTION: ".abs_section_208" + _CAN3TARQ +SECTION: ".abs_section_20a" + _CAN3TBSEL +SECTION: ".abs_section_206" + _CAN3TFLG +SECTION: ".abs_section_207" + _CAN3TIER +SECTION: ".abs_section_23c" + _CAN3TXDLR +SECTION: ".abs_section_234" + _CAN3TXDSR0 +SECTION: ".abs_section_235" + _CAN3TXDSR1 +SECTION: ".abs_section_236" + _CAN3TXDSR2 +SECTION: ".abs_section_237" + _CAN3TXDSR3 +SECTION: ".abs_section_238" + _CAN3TXDSR4 +SECTION: ".abs_section_239" + _CAN3TXDSR5 +SECTION: ".abs_section_23a" + _CAN3TXDSR6 +SECTION: ".abs_section_23b" + _CAN3TXDSR7 +SECTION: ".abs_section_20f" + _CAN3TXERR +SECTION: ".abs_section_230" + _CAN3TXIDR0 +SECTION: ".abs_section_231" + _CAN3TXIDR1 +SECTION: ".abs_section_232" + _CAN3TXIDR2 +SECTION: ".abs_section_233" + _CAN3TXIDR3 +SECTION: ".abs_section_23f" + _CAN3TXTBPR +SECTION: ".abs_section_282" + _CAN4BTR0 +SECTION: ".abs_section_283" + _CAN4BTR1 +SECTION: ".abs_section_280" + _CAN4CTL0 +SECTION: ".abs_section_281" + _CAN4CTL1 +SECTION: ".abs_section_28b" + _CAN4IDAC +SECTION: ".abs_section_290" + _CAN4IDAR0 +SECTION: ".abs_section_291" + _CAN4IDAR1 +SECTION: ".abs_section_292" + _CAN4IDAR2 +SECTION: ".abs_section_293" + _CAN4IDAR3 +SECTION: ".abs_section_298" + _CAN4IDAR4 +SECTION: ".abs_section_299" + _CAN4IDAR5 +SECTION: ".abs_section_29a" + _CAN4IDAR6 +SECTION: ".abs_section_29b" + _CAN4IDAR7 +SECTION: ".abs_section_294" + _CAN4IDMR0 +SECTION: ".abs_section_295" + _CAN4IDMR1 +SECTION: ".abs_section_296" + _CAN4IDMR2 +SECTION: ".abs_section_297" + _CAN4IDMR3 +SECTION: ".abs_section_29c" + _CAN4IDMR4 +SECTION: ".abs_section_29d" + _CAN4IDMR5 +SECTION: ".abs_section_29e" + _CAN4IDMR6 +SECTION: ".abs_section_29f" + _CAN4IDMR7 +SECTION: ".abs_section_284" + _CAN4RFLG +SECTION: ".abs_section_285" + _CAN4RIER +SECTION: ".abs_section_2ac" + _CAN4RXDLR +SECTION: ".abs_section_2a4" + _CAN4RXDSR0 +SECTION: ".abs_section_2a5" + _CAN4RXDSR1 +SECTION: ".abs_section_2a6" + _CAN4RXDSR2 +SECTION: ".abs_section_2a7" + _CAN4RXDSR3 +SECTION: ".abs_section_2a8" + _CAN4RXDSR4 +SECTION: ".abs_section_2a9" + _CAN4RXDSR5 +SECTION: ".abs_section_2aa" + _CAN4RXDSR6 +SECTION: ".abs_section_2ab" + _CAN4RXDSR7 +SECTION: ".abs_section_28e" + _CAN4RXERR +SECTION: ".abs_section_2a0" + _CAN4RXIDR0 +SECTION: ".abs_section_2a1" + _CAN4RXIDR1 +SECTION: ".abs_section_2a2" + _CAN4RXIDR2 +SECTION: ".abs_section_2a3" + _CAN4RXIDR3 +SECTION: ".abs_section_289" + _CAN4TAAK +SECTION: ".abs_section_288" + _CAN4TARQ +SECTION: ".abs_section_28a" + _CAN4TBSEL +SECTION: ".abs_section_286" + _CAN4TFLG +SECTION: ".abs_section_287" + _CAN4TIER +SECTION: ".abs_section_2bc" + _CAN4TXDLR +SECTION: ".abs_section_2b4" + _CAN4TXDSR0 +SECTION: ".abs_section_2b5" + _CAN4TXDSR1 +SECTION: ".abs_section_2b6" + _CAN4TXDSR2 +SECTION: ".abs_section_2b7" + _CAN4TXDSR3 +SECTION: ".abs_section_2b8" + _CAN4TXDSR4 +SECTION: ".abs_section_2b9" + _CAN4TXDSR5 +SECTION: ".abs_section_2ba" + _CAN4TXDSR6 +SECTION: ".abs_section_2bb" + _CAN4TXDSR7 +SECTION: ".abs_section_28f" + _CAN4TXERR +SECTION: ".abs_section_2b0" + _CAN4TXIDR0 +SECTION: ".abs_section_2b1" + _CAN4TXIDR1 +SECTION: ".abs_section_2b2" + _CAN4TXIDR2 +SECTION: ".abs_section_2b3" + _CAN4TXIDR3 +SECTION: ".abs_section_2bf" + _CAN4TXTBPR +SECTION: ".abs_section_41" + _CFORC +SECTION: ".abs_section_39" + _CLKSEL +SECTION: ".abs_section_3c" + _COPCTL +SECTION: ".abs_section_37" + _CRGFLG +SECTION: ".abs_section_38" + _CRGINT +SECTION: ".abs_section_3e" + _CTCTL +SECTION: ".abs_section_36" + _CTFLG +SECTION: ".abs_section_9" + _DDRE +SECTION: ".abs_section_262" + _DDRH +SECTION: ".abs_section_26a" + _DDRJ +SECTION: ".abs_section_33" + _DDRK +SECTION: ".abs_section_252" + _DDRM +SECTION: ".abs_section_25a" + _DDRP +SECTION: ".abs_section_24a" + _DDRS +SECTION: ".abs_section_242" + _DDRT +SECTION: ".abs_section_ec" + _DLCBARD +SECTION: ".abs_section_e8" + _DLCBCR1 +SECTION: ".abs_section_ea" + _DLCBCR2 +SECTION: ".abs_section_eb" + _DLCBDR +SECTION: ".abs_section_ed" + _DLCBRSR +SECTION: ".abs_section_e9" + _DLCBSVR +SECTION: ".abs_section_ee" + _DLCSCR +SECTION: ".abs_section_69" + _DLYCT +SECTION: ".abs_section_e" + _EBICTL +SECTION: ".abs_section_110" + _ECLKDIV +SECTION: ".abs_section_116" + _ECMD +SECTION: ".abs_section_113" + _ECNFG +SECTION: ".abs_section_114" + _EPROT +SECTION: ".abs_section_115" + _ESTAT +SECTION: ".abs_section_100" + _FCLKDIV +SECTION: ".abs_section_106" + _FCMD +SECTION: ".abs_section_103" + _FCNFG +SECTION: ".abs_section_3d" + _FORBYP +SECTION: ".abs_section_104" + _FPROT +SECTION: ".abs_section_101" + _FSEC +SECTION: ".abs_section_105" + _FSTAT +SECTION: ".abs_section_1f" + _HPRIO +SECTION: ".abs_section_e0" + _IBAD +SECTION: ".abs_section_e2" + _IBCR +SECTION: ".abs_section_e4" + _IBDR +SECTION: ".abs_section_e1" + _IBFD +SECTION: ".abs_section_e3" + _IBSR +SECTION: ".abs_section_6a" + _ICOVW +SECTION: ".abs_section_68" + _ICPAR +SECTION: ".abs_section_6b" + _ICSYS +SECTION: ".abs_section_12" + _INITEE +SECTION: ".abs_section_11" + _INITRG +SECTION: ".abs_section_10" + _INITRM +SECTION: ".abs_section_1e" + _INTCR +SECTION: ".abs_section_15" + _ITCR +SECTION: ".abs_section_16" + _ITEST +SECTION: ".abs_section_66" + _MCCTL +SECTION: ".abs_section_67" + _MCFLG +SECTION: ".abs_section_1c" + _MEMSIZ0 +SECTION: ".abs_section_1d" + _MEMSIZ1 +SECTION: ".abs_section_13" + _MISC +SECTION: ".abs_section_b" + _MODE +SECTION: ".abs_section_257" + _MODRR +SECTION: ".abs_section_14" + _MTST0 +SECTION: ".abs_section_17" + _MTST1 +SECTION: ".abs_section_43" + _OC7D +SECTION: ".abs_section_42" + _OC7M +SECTION: ".abs_section_60" + _PACTL +SECTION: ".abs_section_61" + _PAFLG +SECTION: ".abs_section_1a" + _PARTIDH +SECTION: ".abs_section_1b" + _PARTIDL +SECTION: ".abs_section_70" + _PBCTL +SECTION: ".abs_section_71" + _PBFLG +SECTION: ".abs_section_a" + _PEAR +SECTION: ".abs_section_264" + _PERH +SECTION: ".abs_section_26c" + _PERJ +SECTION: ".abs_section_254" + _PERM +SECTION: ".abs_section_25c" + _PERP +SECTION: ".abs_section_24c" + _PERS +SECTION: ".abs_section_244" + _PERT +SECTION: ".abs_section_266" + _PIEH +SECTION: ".abs_section_26e" + _PIEJ +SECTION: ".abs_section_25e" + _PIEP +SECTION: ".abs_section_267" + _PIFH +SECTION: ".abs_section_26f" + _PIFJ +SECTION: ".abs_section_25f" + _PIFP +SECTION: ".abs_section_3a" + _PLLCTL +SECTION: ".abs_section_8f" + _PORTAD0 +SECTION: ".abs_section_12f" + _PORTAD1 +SECTION: ".abs_section_8" + _PORTE +SECTION: ".abs_section_32" + _PORTK +SECTION: ".abs_section_30" + _PPAGE +SECTION: ".abs_section_265" + _PPSH +SECTION: ".abs_section_26d" + _PPSJ +SECTION: ".abs_section_255" + _PPSM +SECTION: ".abs_section_25d" + _PPSP +SECTION: ".abs_section_24d" + _PPSS +SECTION: ".abs_section_245" + _PPST +SECTION: ".abs_section_260" + _PTH +SECTION: ".abs_section_261" + _PTIH +SECTION: ".abs_section_269" + _PTIJ +SECTION: ".abs_section_251" + _PTIM +SECTION: ".abs_section_259" + _PTIP +SECTION: ".abs_section_249" + _PTIS +SECTION: ".abs_section_241" + _PTIT +SECTION: ".abs_section_268" + _PTJ +SECTION: ".abs_section_250" + _PTM +SECTION: ".abs_section_258" + _PTP +SECTION: ".abs_section_248" + _PTS +SECTION: ".abs_section_240" + _PTT +SECTION: ".abs_section_c" + _PUCR +SECTION: ".abs_section_a4" + _PWMCAE +SECTION: ".abs_section_a2" + _PWMCLK +SECTION: ".abs_section_a5" + _PWMCTL +SECTION: ".abs_section_a0" + _PWME +SECTION: ".abs_section_a1" + _PWMPOL +SECTION: ".abs_section_a3" + _PWMPRCLK +SECTION: ".abs_section_a8" + _PWMSCLA +SECTION: ".abs_section_a9" + _PWMSCLB +SECTION: ".abs_section_c4" + _PWMSDN +SECTION: ".abs_section_263" + _RDRH +SECTION: ".abs_section_d" + _RDRIV +SECTION: ".abs_section_26b" + _RDRJ +SECTION: ".abs_section_253" + _RDRM +SECTION: ".abs_section_25b" + _RDRP +SECTION: ".abs_section_24b" + _RDRS +SECTION: ".abs_section_243" + _RDRT +SECTION: ".abs_section_35" + _REFDV +SECTION: ".abs_section_3b" + _RTICTL +SECTION: ".abs_section_ca" + _SCI0CR1 +SECTION: ".abs_section_cb" + _SCI0CR2 +SECTION: ".abs_section_ce" + _SCI0DRH +SECTION: ".abs_section_cf" + _SCI0DRL +SECTION: ".abs_section_cc" + _SCI0SR1 +SECTION: ".abs_section_cd" + _SCI0SR2 +SECTION: ".abs_section_d2" + _SCI1CR1 +SECTION: ".abs_section_d3" + _SCI1CR2 +SECTION: ".abs_section_d6" + _SCI1DRH +SECTION: ".abs_section_d7" + _SCI1DRL +SECTION: ".abs_section_d4" + _SCI1SR1 +SECTION: ".abs_section_d5" + _SCI1SR2 +SECTION: ".abs_section_da" + _SPI0BR +SECTION: ".abs_section_d8" + _SPI0CR1 +SECTION: ".abs_section_d9" + _SPI0CR2 +SECTION: ".abs_section_dd" + _SPI0DR +SECTION: ".abs_section_db" + _SPI0SR +SECTION: ".abs_section_f2" + _SPI1BR +SECTION: ".abs_section_f0" + _SPI1CR1 +SECTION: ".abs_section_f1" + _SPI1CR2 +SECTION: ".abs_section_f5" + _SPI1DR +SECTION: ".abs_section_f3" + _SPI1SR +SECTION: ".abs_section_fa" + _SPI2BR +SECTION: ".abs_section_f8" + _SPI2CR1 +SECTION: ".abs_section_f9" + _SPI2CR2 +SECTION: ".abs_section_fd" + _SPI2DR +SECTION: ".abs_section_fb" + _SPI2SR +SECTION: ".abs_section_34" + _SYNR +SECTION: ".abs_section_48" + _TCTL1 +SECTION: ".abs_section_49" + _TCTL2 +SECTION: ".abs_section_4a" + _TCTL3 +SECTION: ".abs_section_4b" + _TCTL4 +SECTION: ".abs_section_4e" + _TFLG1 +SECTION: ".abs_section_4f" + _TFLG2 +SECTION: ".abs_section_4c" + _TIE +SECTION: ".abs_section_6d" + _TIMTST +SECTION: ".abs_section_40" + _TIOS +SECTION: ".abs_section_46" + _TSCR1 +SECTION: ".abs_section_4d" + _TSCR2 +SECTION: ".abs_section_47" + _TTOV +SECTION: ".abs_section_256" + _WOMM +SECTION: ".abs_section_24e" + _WOMS +SECTION: ".abs_section_82" + _ATD0CTL23 +SECTION: ".abs_section_84" + _ATD0CTL45 +SECTION: ".abs_section_90" + _ATD0DR0 +SECTION: ".abs_section_92" + _ATD0DR1 +SECTION: ".abs_section_94" + _ATD0DR2 +SECTION: ".abs_section_96" + _ATD0DR3 +SECTION: ".abs_section_98" + _ATD0DR4 +SECTION: ".abs_section_9a" + _ATD0DR5 +SECTION: ".abs_section_9c" + _ATD0DR6 +SECTION: ".abs_section_9e" + _ATD0DR7 +SECTION: ".abs_section_122" + _ATD1CTL23 +SECTION: ".abs_section_124" + _ATD1CTL45 +SECTION: ".abs_section_130" + _ATD1DR0 +SECTION: ".abs_section_132" + _ATD1DR1 +SECTION: ".abs_section_134" + _ATD1DR2 +SECTION: ".abs_section_136" + _ATD1DR3 +SECTION: ".abs_section_138" + _ATD1DR4 +SECTION: ".abs_section_13a" + _ATD1DR5 +SECTION: ".abs_section_13c" + _ATD1DR6 +SECTION: ".abs_section_13e" + _ATD1DR7 +SECTION: ".abs_section_2" + _DDRAB +SECTION: ".abs_section_76" + _MCCNT +SECTION: ".abs_section_74" + _PA10H +SECTION: ".abs_section_72" + _PA32H +SECTION: ".abs_section_64" + _PACN10 +SECTION: ".abs_section_62" + _PACN32 +SECTION: ".abs_section_0" + _PORTAB +SECTION: ".abs_section_ac" + _PWMCNT01 +SECTION: ".abs_section_ae" + _PWMCNT23 +SECTION: ".abs_section_b0" + _PWMCNT45 +SECTION: ".abs_section_b2" + _PWMCNT67 +SECTION: ".abs_section_bc" + _PWMDTY01 +SECTION: ".abs_section_be" + _PWMDTY23 +SECTION: ".abs_section_c0" + _PWMDTY45 +SECTION: ".abs_section_c2" + _PWMDTY67 +SECTION: ".abs_section_b4" + _PWMPER01 +SECTION: ".abs_section_b6" + _PWMPER23 +SECTION: ".abs_section_b8" + _PWMPER45 +SECTION: ".abs_section_ba" + _PWMPER67 +SECTION: ".abs_section_c8" + _SCI0BD +SECTION: ".abs_section_d0" + _SCI1BD +SECTION: ".abs_section_50" + _TC0 +SECTION: ".abs_section_78" + _TC0H +SECTION: ".abs_section_52" + _TC1 +SECTION: ".abs_section_7a" + _TC1H +SECTION: ".abs_section_54" + _TC2 +SECTION: ".abs_section_7c" + _TC2H +SECTION: ".abs_section_56" + _TC3 +SECTION: ".abs_section_7e" + _TC3H +SECTION: ".abs_section_58" + _TC4 +SECTION: ".abs_section_5a" + _TC5 +SECTION: ".abs_section_5c" + _TC6 +SECTION: ".abs_section_5e" + _TC7 +SECTION: ".abs_section_44" + _TCNT +SECTION: ".abs_section_ff80" + _vect +SECTION: "TickTimer_DATA" + CmpHighVal +SECTION: "Byte1_DATA" + Byte1_Table +SECTION: "COM0_DATA" + COM0_PrescHigh.1 SerFlag PrescHigh NumMode +SECTION: "ROM_PAGE31_524" + xSerialPutChar xTaskCreate vTaskDelete vTaskDelayUntil vTaskDelay + uxTaskPriorityGet +SECTION: "ROM_PAGE32_525" + vTaskPrioritySet vTaskSuspend vTaskResume vTaskStartScheduler + vTaskSuspendAll xTaskResumeAll xTaskGetTickCount uxTaskGetNumberOfTasks +SECTION: "ROM_PAGE33_526" + vTaskIncrementTick vTaskSwitchContext vTaskPlaceOnEventList + xTaskRemoveFromEventList prvIdleTask prvInitialiseTCBVariables + prvInitialiseTaskLists +SECTION: "ROM_PAGE34_527" + prvCheckTasksWaitingTermination prvAllocateTCBAndStack prvDeleteTCB + xQueueCreate xQueueSend xQueueSendFromISR +SECTION: "ROM_PAGE35_528" + xQueueReceive xQueueReceiveFromISR uxQueueMessagesWaiting prvUnlockQueue + prvIsQueueEmpty prvIsQueueFull vListInitialise vListInitialiseItem + vListInsertEnd +SECTION: "ROM_PAGE36_529" + vListInsert vListRemove pvPortMalloc vPortFree PE_Timer_LngHi1 + vStartLEDFlashTasks vLEDFlashTask +SECTION: "ROM_PAGE37_530" + vStartDynamicPriorityTasks vLimitedIncrementTask vContinuousIncrementTask + vCounterControlTask vQueueSendWhenSuspendedTask + vQueueReceiveWhenSuspendedTask xAreDynamicPriorityTasksStillRunning +SECTION: "ROM_PAGE38_531" + vStartPolledQueueTasks vPolledQueueProducer vPolledQueueConsumer + xArePollingQueuesStillRunning vAltStartComTestTasks vComTxTask vComRxTask + xAreComTestTasksStillRunning +SECTION: "ROM_PAGE39_532" + pxPortInitialiseStack prvSetupTimerInterrupt xPortStartScheduler + vStartIntegerMathTasks vCompeteingIntMathTask + xAreIntegerMathsTaskStillRunning +SECTION: "ROM_PAGE3A_533" + vStartBlockingQueueTasks vBlockingQueueProducer vBlockingQueueConsumer + xAreBlockingQueuesStillRunning vCreateSuicidalTasks +SECTION: "ROM_PAGE3B_534" + vSuicidalTask vCreateTasks xIsCreateTaskStillRunning + +********************************************************************************************* +OBJECT LIST SORTED BY ADDRESS + Name Addr hSize dSize Ref Section RLIB +--------------------------------------------------------------------------------------------- + _PORTAB 0 2 2 6 .abs_section_0 + _DDRAB 2 2 2 1 .abs_section_2 + _PORTE 8 1 1 0 .abs_section_8 + _DDRE 9 1 1 0 .abs_section_9 + _PEAR A 1 1 0 .abs_section_a + _MODE B 1 1 0 .abs_section_b + _PUCR C 1 1 0 .abs_section_c + _RDRIV D 1 1 0 .abs_section_d + _EBICTL E 1 1 0 .abs_section_e + _INITRM 10 1 1 1 .abs_section_10 + _INITRG 11 1 1 0 .abs_section_11 + _INITEE 12 1 1 1 .abs_section_12 + _MISC 13 1 1 1 .abs_section_13 + _MTST0 14 1 1 0 .abs_section_14 + _ITCR 15 1 1 0 .abs_section_15 + _ITEST 16 1 1 0 .abs_section_16 + _MTST1 17 1 1 0 .abs_section_17 + _PARTIDH 1A 1 1 0 .abs_section_1a + _PARTIDL 1B 1 1 0 .abs_section_1b + _MEMSIZ0 1C 1 1 0 .abs_section_1c + _MEMSIZ1 1D 1 1 0 .abs_section_1d + _INTCR 1E 1 1 1 .abs_section_1e + _HPRIO 1F 1 1 0 .abs_section_1f + _BKPCT0 28 1 1 0 .abs_section_28 + _BKPCT1 29 1 1 0 .abs_section_29 + _BKP0X 2A 1 1 0 .abs_section_2a + _BKP0H 2B 1 1 0 .abs_section_2b + _BKP0L 2C 1 1 0 .abs_section_2c + _BKP1X 2D 1 1 0 .abs_section_2d + _BKP1H 2E 1 1 0 .abs_section_2e + _BKP1L 2F 1 1 0 .abs_section_2f + _PPAGE 30 1 1 0 .abs_section_30 + _PORTK 32 1 1 0 .abs_section_32 + _DDRK 33 1 1 0 .abs_section_33 + _SYNR 34 1 1 1 .abs_section_34 + _REFDV 35 1 1 1 .abs_section_35 + _CTFLG 36 1 1 0 .abs_section_36 + _CRGFLG 37 1 1 1 .abs_section_37 + _CRGINT 38 1 1 0 .abs_section_38 + _CLKSEL 39 1 1 3 .abs_section_39 + _PLLCTL 3A 1 1 3 .abs_section_3a + _RTICTL 3B 1 1 0 .abs_section_3b + _COPCTL 3C 1 1 0 .abs_section_3c + _FORBYP 3D 1 1 0 .abs_section_3d + _CTCTL 3E 1 1 0 .abs_section_3e + _ARMCOP 3F 1 1 0 .abs_section_3f + _TIOS 40 1 1 1 .abs_section_40 + _CFORC 41 1 1 0 .abs_section_41 + _OC7M 42 1 1 0 .abs_section_42 + _OC7D 43 1 1 0 .abs_section_43 + _TCNT 44 2 2 0 .abs_section_44 + _TSCR1 46 1 1 3 .abs_section_46 + _TTOV 47 1 1 1 .abs_section_47 + _TCTL1 48 1 1 1 .abs_section_48 + _TCTL2 49 1 1 1 .abs_section_49 + _TCTL3 4A 1 1 0 .abs_section_4a + _TCTL4 4B 1 1 0 .abs_section_4b + _TIE 4C 1 1 2 .abs_section_4c + _TSCR2 4D 1 1 5 .abs_section_4d + _TFLG1 4E 1 1 2 .abs_section_4e + _TFLG2 4F 1 1 0 .abs_section_4f + _TC0 50 2 2 1 .abs_section_50 + _TC1 52 2 2 0 .abs_section_52 + _TC2 54 2 2 0 .abs_section_54 + _TC3 56 2 2 0 .abs_section_56 + _TC4 58 2 2 0 .abs_section_58 + _TC5 5A 2 2 0 .abs_section_5a + _TC6 5C 2 2 0 .abs_section_5c + _TC7 5E 2 2 1 .abs_section_5e + _PACTL 60 1 1 0 .abs_section_60 + _PAFLG 61 1 1 0 .abs_section_61 + _PACN32 62 2 2 0 .abs_section_62 + _PACN10 64 2 2 0 .abs_section_64 + _MCCTL 66 1 1 1 .abs_section_66 + _MCFLG 67 1 1 0 .abs_section_67 + _ICPAR 68 1 1 0 .abs_section_68 + _DLYCT 69 1 1 0 .abs_section_69 + _ICOVW 6A 1 1 0 .abs_section_6a + _ICSYS 6B 1 1 1 .abs_section_6b + _TIMTST 6D 1 1 0 .abs_section_6d + _PBCTL 70 1 1 0 .abs_section_70 + _PBFLG 71 1 1 0 .abs_section_71 + _PA32H 72 2 2 0 .abs_section_72 + _PA10H 74 2 2 0 .abs_section_74 + _MCCNT 76 2 2 0 .abs_section_76 + _TC0H 78 2 2 0 .abs_section_78 + _TC1H 7A 2 2 0 .abs_section_7a + _TC2H 7C 2 2 0 .abs_section_7c + _TC3H 7E 2 2 0 .abs_section_7e + _ATD0CTL23 82 2 2 0 .abs_section_82 + _ATD0CTL45 84 2 2 0 .abs_section_84 + _ATD0STAT0 86 1 1 0 .abs_section_86 + _ATD0STAT1 8B 1 1 0 .abs_section_8b + _ATD0DIEN 8D 1 1 0 .abs_section_8d + _PORTAD0 8F 1 1 0 .abs_section_8f + _ATD0DR0 90 2 2 0 .abs_section_90 + _ATD0DR1 92 2 2 0 .abs_section_92 + _ATD0DR2 94 2 2 0 .abs_section_94 + _ATD0DR3 96 2 2 0 .abs_section_96 + _ATD0DR4 98 2 2 0 .abs_section_98 + _ATD0DR5 9A 2 2 0 .abs_section_9a + _ATD0DR6 9C 2 2 0 .abs_section_9c + _ATD0DR7 9E 2 2 0 .abs_section_9e + _PWME A0 1 1 0 .abs_section_a0 + _PWMPOL A1 1 1 0 .abs_section_a1 + _PWMCLK A2 1 1 0 .abs_section_a2 + _PWMPRCLK A3 1 1 0 .abs_section_a3 + _PWMCAE A4 1 1 0 .abs_section_a4 + _PWMCTL A5 1 1 1 .abs_section_a5 + _PWMSCLA A8 1 1 0 .abs_section_a8 + _PWMSCLB A9 1 1 0 .abs_section_a9 + _PWMCNT01 AC 2 2 0 .abs_section_ac + _PWMCNT23 AE 2 2 0 .abs_section_ae + _PWMCNT45 B0 2 2 0 .abs_section_b0 + _PWMCNT67 B2 2 2 0 .abs_section_b2 + _PWMPER01 B4 2 2 0 .abs_section_b4 + _PWMPER23 B6 2 2 0 .abs_section_b6 + _PWMPER45 B8 2 2 0 .abs_section_b8 + _PWMPER67 BA 2 2 0 .abs_section_ba + _PWMDTY01 BC 2 2 0 .abs_section_bc + _PWMDTY23 BE 2 2 0 .abs_section_be + _PWMDTY45 C0 2 2 0 .abs_section_c0 + _PWMDTY67 C2 2 2 0 .abs_section_c2 + _PWMSDN C4 1 1 1 .abs_section_c4 + _SCI0BD C8 2 2 2 .abs_section_c8 + _SCI0CR1 CA 1 1 1 .abs_section_ca + _SCI0CR2 CB 1 1 7 .abs_section_cb + _SCI0SR1 CC 1 1 2 .abs_section_cc + _SCI0SR2 CD 1 1 1 .abs_section_cd + _SCI0DRH CE 1 1 0 .abs_section_ce + _SCI0DRL CF 1 1 3 .abs_section_cf + _SCI1BD D0 2 2 0 .abs_section_d0 + _SCI1CR1 D2 1 1 0 .abs_section_d2 + _SCI1CR2 D3 1 1 0 .abs_section_d3 + _SCI1SR1 D4 1 1 0 .abs_section_d4 + _SCI1SR2 D5 1 1 0 .abs_section_d5 + _SCI1DRH D6 1 1 0 .abs_section_d6 + _SCI1DRL D7 1 1 0 .abs_section_d7 + _SPI0CR1 D8 1 1 0 .abs_section_d8 + _SPI0CR2 D9 1 1 0 .abs_section_d9 + _SPI0BR DA 1 1 0 .abs_section_da + _SPI0SR DB 1 1 0 .abs_section_db + _SPI0DR DD 1 1 0 .abs_section_dd + _IBAD E0 1 1 0 .abs_section_e0 + _IBFD E1 1 1 0 .abs_section_e1 + _IBCR E2 1 1 0 .abs_section_e2 + _IBSR E3 1 1 0 .abs_section_e3 + _IBDR E4 1 1 0 .abs_section_e4 + _DLCBCR1 E8 1 1 0 .abs_section_e8 + _DLCBSVR E9 1 1 0 .abs_section_e9 + _DLCBCR2 EA 1 1 0 .abs_section_ea + _DLCBDR EB 1 1 0 .abs_section_eb + _DLCBARD EC 1 1 0 .abs_section_ec + _DLCBRSR ED 1 1 0 .abs_section_ed + _DLCSCR EE 1 1 0 .abs_section_ee + _SPI1CR1 F0 1 1 0 .abs_section_f0 + _SPI1CR2 F1 1 1 0 .abs_section_f1 + _SPI1BR F2 1 1 0 .abs_section_f2 + _SPI1SR F3 1 1 0 .abs_section_f3 + _SPI1DR F5 1 1 0 .abs_section_f5 + _SPI2CR1 F8 1 1 0 .abs_section_f8 + _SPI2CR2 F9 1 1 0 .abs_section_f9 + _SPI2BR FA 1 1 0 .abs_section_fa + _SPI2SR FB 1 1 0 .abs_section_fb + _SPI2DR FD 1 1 0 .abs_section_fd + _FCLKDIV 100 1 1 0 .abs_section_100 + _FSEC 101 1 1 0 .abs_section_101 + _FCNFG 103 1 1 0 .abs_section_103 + _FPROT 104 1 1 0 .abs_section_104 + _FSTAT 105 1 1 0 .abs_section_105 + _FCMD 106 1 1 0 .abs_section_106 + _ECLKDIV 110 1 1 0 .abs_section_110 + _ECNFG 113 1 1 0 .abs_section_113 + _EPROT 114 1 1 0 .abs_section_114 + _ESTAT 115 1 1 0 .abs_section_115 + _ECMD 116 1 1 0 .abs_section_116 + _ATD1CTL23 122 2 2 0 .abs_section_122 + _ATD1CTL45 124 2 2 0 .abs_section_124 + _ATD1STAT0 126 1 1 0 .abs_section_126 + _ATD1STAT1 12B 1 1 0 .abs_section_12b + _ATD1DIEN 12D 1 1 0 .abs_section_12d + _PORTAD1 12F 1 1 0 .abs_section_12f + _ATD1DR0 130 2 2 0 .abs_section_130 + _ATD1DR1 132 2 2 0 .abs_section_132 + _ATD1DR2 134 2 2 0 .abs_section_134 + _ATD1DR3 136 2 2 0 .abs_section_136 + _ATD1DR4 138 2 2 0 .abs_section_138 + _ATD1DR5 13A 2 2 0 .abs_section_13a + _ATD1DR6 13C 2 2 0 .abs_section_13c + _ATD1DR7 13E 2 2 0 .abs_section_13e + _CAN0CTL0 140 1 1 0 .abs_section_140 + _CAN0CTL1 141 1 1 0 .abs_section_141 + _CAN0BTR0 142 1 1 0 .abs_section_142 + _CAN0BTR1 143 1 1 0 .abs_section_143 + _CAN0RFLG 144 1 1 0 .abs_section_144 + _CAN0RIER 145 1 1 0 .abs_section_145 + _CAN0TFLG 146 1 1 0 .abs_section_146 + _CAN0TIER 147 1 1 0 .abs_section_147 + _CAN0TARQ 148 1 1 0 .abs_section_148 + _CAN0TAAK 149 1 1 0 .abs_section_149 + _CAN0TBSEL 14A 1 1 0 .abs_section_14a + _CAN0IDAC 14B 1 1 0 .abs_section_14b + _CAN0RXERR 14E 1 1 0 .abs_section_14e + _CAN0TXERR 14F 1 1 0 .abs_section_14f + _CAN0IDAR0 150 1 1 0 .abs_section_150 + _CAN0IDAR1 151 1 1 0 .abs_section_151 + _CAN0IDAR2 152 1 1 0 .abs_section_152 + _CAN0IDAR3 153 1 1 0 .abs_section_153 + _CAN0IDMR0 154 1 1 0 .abs_section_154 + _CAN0IDMR1 155 1 1 0 .abs_section_155 + _CAN0IDMR2 156 1 1 0 .abs_section_156 + _CAN0IDMR3 157 1 1 0 .abs_section_157 + _CAN0IDAR4 158 1 1 0 .abs_section_158 + _CAN0IDAR5 159 1 1 0 .abs_section_159 + _CAN0IDAR6 15A 1 1 0 .abs_section_15a + _CAN0IDAR7 15B 1 1 0 .abs_section_15b + _CAN0IDMR4 15C 1 1 0 .abs_section_15c + _CAN0IDMR5 15D 1 1 0 .abs_section_15d + _CAN0IDMR6 15E 1 1 0 .abs_section_15e + _CAN0IDMR7 15F 1 1 0 .abs_section_15f + _CAN0RXIDR0 160 1 1 0 .abs_section_160 + _CAN0RXIDR1 161 1 1 0 .abs_section_161 + _CAN0RXIDR2 162 1 1 0 .abs_section_162 + _CAN0RXIDR3 163 1 1 0 .abs_section_163 + _CAN0RXDSR0 164 1 1 0 .abs_section_164 + _CAN0RXDSR1 165 1 1 0 .abs_section_165 + _CAN0RXDSR2 166 1 1 0 .abs_section_166 + _CAN0RXDSR3 167 1 1 0 .abs_section_167 + _CAN0RXDSR4 168 1 1 0 .abs_section_168 + _CAN0RXDSR5 169 1 1 0 .abs_section_169 + _CAN0RXDSR6 16A 1 1 0 .abs_section_16a + _CAN0RXDSR7 16B 1 1 0 .abs_section_16b + _CAN0RXDLR 16C 1 1 0 .abs_section_16c + _CAN0TXIDR0 170 1 1 0 .abs_section_170 + _CAN0TXIDR1 171 1 1 0 .abs_section_171 + _CAN0TXIDR2 172 1 1 0 .abs_section_172 + _CAN0TXIDR3 173 1 1 0 .abs_section_173 + _CAN0TXDSR0 174 1 1 0 .abs_section_174 + _CAN0TXDSR1 175 1 1 0 .abs_section_175 + _CAN0TXDSR2 176 1 1 0 .abs_section_176 + _CAN0TXDSR3 177 1 1 0 .abs_section_177 + _CAN0TXDSR4 178 1 1 0 .abs_section_178 + _CAN0TXDSR5 179 1 1 0 .abs_section_179 + _CAN0TXDSR6 17A 1 1 0 .abs_section_17a + _CAN0TXDSR7 17B 1 1 0 .abs_section_17b + _CAN0TXDLR 17C 1 1 0 .abs_section_17c + _CAN0TXTBPR 17F 1 1 0 .abs_section_17f + _CAN1CTL0 180 1 1 0 .abs_section_180 + _CAN1CTL1 181 1 1 0 .abs_section_181 + _CAN1BTR0 182 1 1 0 .abs_section_182 + _CAN1BTR1 183 1 1 0 .abs_section_183 + _CAN1RFLG 184 1 1 0 .abs_section_184 + _CAN1RIER 185 1 1 0 .abs_section_185 + _CAN1TFLG 186 1 1 0 .abs_section_186 + _CAN1TIER 187 1 1 0 .abs_section_187 + _CAN1TARQ 188 1 1 0 .abs_section_188 + _CAN1TAAK 189 1 1 0 .abs_section_189 + _CAN1TBSEL 18A 1 1 0 .abs_section_18a + _CAN1IDAC 18B 1 1 0 .abs_section_18b + _CAN1RXERR 18E 1 1 0 .abs_section_18e + _CAN1TXERR 18F 1 1 0 .abs_section_18f + _CAN1IDAR0 190 1 1 0 .abs_section_190 + _CAN1IDAR1 191 1 1 0 .abs_section_191 + _CAN1IDAR2 192 1 1 0 .abs_section_192 + _CAN1IDAR3 193 1 1 0 .abs_section_193 + _CAN1IDMR0 194 1 1 0 .abs_section_194 + _CAN1IDMR1 195 1 1 0 .abs_section_195 + _CAN1IDMR2 196 1 1 0 .abs_section_196 + _CAN1IDMR3 197 1 1 0 .abs_section_197 + _CAN1IDAR4 198 1 1 0 .abs_section_198 + _CAN1IDAR5 199 1 1 0 .abs_section_199 + _CAN1IDAR6 19A 1 1 0 .abs_section_19a + _CAN1IDAR7 19B 1 1 0 .abs_section_19b + _CAN1IDMR4 19C 1 1 0 .abs_section_19c + _CAN1IDMR5 19D 1 1 0 .abs_section_19d + _CAN1IDMR6 19E 1 1 0 .abs_section_19e + _CAN1IDMR7 19F 1 1 0 .abs_section_19f + _CAN1RXIDR0 1A0 1 1 0 .abs_section_1a0 + _CAN1RXIDR1 1A1 1 1 0 .abs_section_1a1 + _CAN1RXIDR2 1A2 1 1 0 .abs_section_1a2 + _CAN1RXIDR3 1A3 1 1 0 .abs_section_1a3 + _CAN1RXDSR0 1A4 1 1 0 .abs_section_1a4 + _CAN1RXDSR1 1A5 1 1 0 .abs_section_1a5 + _CAN1RXDSR2 1A6 1 1 0 .abs_section_1a6 + _CAN1RXDSR3 1A7 1 1 0 .abs_section_1a7 + _CAN1RXDSR4 1A8 1 1 0 .abs_section_1a8 + _CAN1RXDSR5 1A9 1 1 0 .abs_section_1a9 + _CAN1RXDSR6 1AA 1 1 0 .abs_section_1aa + _CAN1RXDSR7 1AB 1 1 0 .abs_section_1ab + _CAN1RXDLR 1AC 1 1 0 .abs_section_1ac + _CAN1TXIDR0 1B0 1 1 0 .abs_section_1b0 + _CAN1TXIDR1 1B1 1 1 0 .abs_section_1b1 + _CAN1TXIDR2 1B2 1 1 0 .abs_section_1b2 + _CAN1TXIDR3 1B3 1 1 0 .abs_section_1b3 + _CAN1TXDSR0 1B4 1 1 0 .abs_section_1b4 + _CAN1TXDSR1 1B5 1 1 0 .abs_section_1b5 + _CAN1TXDSR2 1B6 1 1 0 .abs_section_1b6 + _CAN1TXDSR3 1B7 1 1 0 .abs_section_1b7 + _CAN1TXDSR4 1B8 1 1 0 .abs_section_1b8 + _CAN1TXDSR5 1B9 1 1 0 .abs_section_1b9 + _CAN1TXDSR6 1BA 1 1 0 .abs_section_1ba + _CAN1TXDSR7 1BB 1 1 0 .abs_section_1bb + _CAN1TXDLR 1BC 1 1 0 .abs_section_1bc + _CAN1TXTBPR 1BF 1 1 0 .abs_section_1bf + _CAN2CTL0 1C0 1 1 0 .abs_section_1c0 + _CAN2CTL1 1C1 1 1 0 .abs_section_1c1 + _CAN2BTR0 1C2 1 1 0 .abs_section_1c2 + _CAN2BTR1 1C3 1 1 0 .abs_section_1c3 + _CAN2RFLG 1C4 1 1 0 .abs_section_1c4 + _CAN2RIER 1C5 1 1 0 .abs_section_1c5 + _CAN2TFLG 1C6 1 1 0 .abs_section_1c6 + _CAN2TIER 1C7 1 1 0 .abs_section_1c7 + _CAN2TARQ 1C8 1 1 0 .abs_section_1c8 + _CAN2TAAK 1C9 1 1 0 .abs_section_1c9 + _CAN2TBSEL 1CA 1 1 0 .abs_section_1ca + _CAN2IDAC 1CB 1 1 0 .abs_section_1cb + _CAN2RXERR 1CE 1 1 0 .abs_section_1ce + _CAN2TXERR 1CF 1 1 0 .abs_section_1cf + _CAN2IDAR0 1D0 1 1 0 .abs_section_1d0 + _CAN2IDAR1 1D1 1 1 0 .abs_section_1d1 + _CAN2IDAR2 1D2 1 1 0 .abs_section_1d2 + _CAN2IDAR3 1D3 1 1 0 .abs_section_1d3 + _CAN2IDMR0 1D4 1 1 0 .abs_section_1d4 + _CAN2IDMR1 1D5 1 1 0 .abs_section_1d5 + _CAN2IDMR2 1D6 1 1 0 .abs_section_1d6 + _CAN2IDMR3 1D7 1 1 0 .abs_section_1d7 + _CAN2IDAR4 1D8 1 1 0 .abs_section_1d8 + _CAN2IDAR5 1D9 1 1 0 .abs_section_1d9 + _CAN2IDAR6 1DA 1 1 0 .abs_section_1da + _CAN2IDAR7 1DB 1 1 0 .abs_section_1db + _CAN2IDMR4 1DC 1 1 0 .abs_section_1dc + _CAN2IDMR5 1DD 1 1 0 .abs_section_1dd + _CAN2IDMR6 1DE 1 1 0 .abs_section_1de + _CAN2IDMR7 1DF 1 1 0 .abs_section_1df + _CAN2RXIDR0 1E0 1 1 0 .abs_section_1e0 + _CAN2RXIDR1 1E1 1 1 0 .abs_section_1e1 + _CAN2RXIDR2 1E2 1 1 0 .abs_section_1e2 + _CAN2RXIDR3 1E3 1 1 0 .abs_section_1e3 + _CAN2RXDSR0 1E4 1 1 0 .abs_section_1e4 + _CAN2RXDSR1 1E5 1 1 0 .abs_section_1e5 + _CAN2RXDSR2 1E6 1 1 0 .abs_section_1e6 + _CAN2RXDSR3 1E7 1 1 0 .abs_section_1e7 + _CAN2RXDSR4 1E8 1 1 0 .abs_section_1e8 + _CAN2RXDSR5 1E9 1 1 0 .abs_section_1e9 + _CAN2RXDSR6 1EA 1 1 0 .abs_section_1ea + _CAN2RXDSR7 1EB 1 1 0 .abs_section_1eb + _CAN2RXDLR 1EC 1 1 0 .abs_section_1ec + _CAN2TXIDR0 1F0 1 1 0 .abs_section_1f0 + _CAN2TXIDR1 1F1 1 1 0 .abs_section_1f1 + _CAN2TXIDR2 1F2 1 1 0 .abs_section_1f2 + _CAN2TXIDR3 1F3 1 1 0 .abs_section_1f3 + _CAN2TXDSR0 1F4 1 1 0 .abs_section_1f4 + _CAN2TXDSR1 1F5 1 1 0 .abs_section_1f5 + _CAN2TXDSR2 1F6 1 1 0 .abs_section_1f6 + _CAN2TXDSR3 1F7 1 1 0 .abs_section_1f7 + _CAN2TXDSR4 1F8 1 1 0 .abs_section_1f8 + _CAN2TXDSR5 1F9 1 1 0 .abs_section_1f9 + _CAN2TXDSR6 1FA 1 1 0 .abs_section_1fa + _CAN2TXDSR7 1FB 1 1 0 .abs_section_1fb + _CAN2TXDLR 1FC 1 1 0 .abs_section_1fc + _CAN2TXTBPR 1FF 1 1 0 .abs_section_1ff + _CAN3CTL0 200 1 1 0 .abs_section_200 + _CAN3CTL1 201 1 1 0 .abs_section_201 + _CAN3BTR0 202 1 1 0 .abs_section_202 + _CAN3BTR1 203 1 1 0 .abs_section_203 + _CAN3RFLG 204 1 1 0 .abs_section_204 + _CAN3RIER 205 1 1 0 .abs_section_205 + _CAN3TFLG 206 1 1 0 .abs_section_206 + _CAN3TIER 207 1 1 0 .abs_section_207 + _CAN3TARQ 208 1 1 0 .abs_section_208 + _CAN3TAAK 209 1 1 0 .abs_section_209 + _CAN3TBSEL 20A 1 1 0 .abs_section_20a + _CAN3IDAC 20B 1 1 0 .abs_section_20b + _CAN3RXERR 20E 1 1 0 .abs_section_20e + _CAN3TXERR 20F 1 1 0 .abs_section_20f + _CAN3IDAR0 210 1 1 0 .abs_section_210 + _CAN3IDAR1 211 1 1 0 .abs_section_211 + _CAN3IDAR2 212 1 1 0 .abs_section_212 + _CAN3IDAR3 213 1 1 0 .abs_section_213 + _CAN3IDMR0 214 1 1 0 .abs_section_214 + _CAN3IDMR1 215 1 1 0 .abs_section_215 + _CAN3IDMR2 216 1 1 0 .abs_section_216 + _CAN3IDMR3 217 1 1 0 .abs_section_217 + _CAN3IDAR4 218 1 1 0 .abs_section_218 + _CAN3IDAR5 219 1 1 0 .abs_section_219 + _CAN3IDAR6 21A 1 1 0 .abs_section_21a + _CAN3IDAR7 21B 1 1 0 .abs_section_21b + _CAN3IDMR4 21C 1 1 0 .abs_section_21c + _CAN3IDMR5 21D 1 1 0 .abs_section_21d + _CAN3IDMR6 21E 1 1 0 .abs_section_21e + _CAN3IDMR7 21F 1 1 0 .abs_section_21f + _CAN3RXIDR0 220 1 1 0 .abs_section_220 + _CAN3RXIDR1 221 1 1 0 .abs_section_221 + _CAN3RXIDR2 222 1 1 0 .abs_section_222 + _CAN3RXIDR3 223 1 1 0 .abs_section_223 + _CAN3RXDSR0 224 1 1 0 .abs_section_224 + _CAN3RXDSR1 225 1 1 0 .abs_section_225 + _CAN3RXDSR2 226 1 1 0 .abs_section_226 + _CAN3RXDSR3 227 1 1 0 .abs_section_227 + _CAN3RXDSR4 228 1 1 0 .abs_section_228 + _CAN3RXDSR5 229 1 1 0 .abs_section_229 + _CAN3RXDSR6 22A 1 1 0 .abs_section_22a + _CAN3RXDSR7 22B 1 1 0 .abs_section_22b + _CAN3RXDLR 22C 1 1 0 .abs_section_22c + _CAN3TXIDR0 230 1 1 0 .abs_section_230 + _CAN3TXIDR1 231 1 1 0 .abs_section_231 + _CAN3TXIDR2 232 1 1 0 .abs_section_232 + _CAN3TXIDR3 233 1 1 0 .abs_section_233 + _CAN3TXDSR0 234 1 1 0 .abs_section_234 + _CAN3TXDSR1 235 1 1 0 .abs_section_235 + _CAN3TXDSR2 236 1 1 0 .abs_section_236 + _CAN3TXDSR3 237 1 1 0 .abs_section_237 + _CAN3TXDSR4 238 1 1 0 .abs_section_238 + _CAN3TXDSR5 239 1 1 0 .abs_section_239 + _CAN3TXDSR6 23A 1 1 0 .abs_section_23a + _CAN3TXDSR7 23B 1 1 0 .abs_section_23b + _CAN3TXDLR 23C 1 1 0 .abs_section_23c + _CAN3TXTBPR 23F 1 1 0 .abs_section_23f + _PTT 240 1 1 0 .abs_section_240 + _PTIT 241 1 1 0 .abs_section_241 + _DDRT 242 1 1 0 .abs_section_242 + _RDRT 243 1 1 0 .abs_section_243 + _PERT 244 1 1 0 .abs_section_244 + _PPST 245 1 1 0 .abs_section_245 + _PTS 248 1 1 1 .abs_section_248 + _PTIS 249 1 1 0 .abs_section_249 + _DDRS 24A 1 1 2 .abs_section_24a + _RDRS 24B 1 1 0 .abs_section_24b + _PERS 24C 1 1 0 .abs_section_24c + _PPSS 24D 1 1 0 .abs_section_24d + _WOMS 24E 1 1 0 .abs_section_24e + _PTM 250 1 1 0 .abs_section_250 + _PTIM 251 1 1 0 .abs_section_251 + _DDRM 252 1 1 0 .abs_section_252 + _RDRM 253 1 1 0 .abs_section_253 + _PERM 254 1 1 0 .abs_section_254 + _PPSM 255 1 1 0 .abs_section_255 + _WOMM 256 1 1 0 .abs_section_256 + _MODRR 257 1 1 0 .abs_section_257 + _PTP 258 1 1 0 .abs_section_258 + _PTIP 259 1 1 0 .abs_section_259 + _DDRP 25A 1 1 0 .abs_section_25a + _RDRP 25B 1 1 0 .abs_section_25b + _PERP 25C 1 1 0 .abs_section_25c + _PPSP 25D 1 1 0 .abs_section_25d + _PIEP 25E 1 1 0 .abs_section_25e + _PIFP 25F 1 1 0 .abs_section_25f + _PTH 260 1 1 0 .abs_section_260 + _PTIH 261 1 1 0 .abs_section_261 + _DDRH 262 1 1 0 .abs_section_262 + _RDRH 263 1 1 0 .abs_section_263 + _PERH 264 1 1 0 .abs_section_264 + _PPSH 265 1 1 0 .abs_section_265 + _PIEH 266 1 1 0 .abs_section_266 + _PIFH 267 1 1 0 .abs_section_267 + _PTJ 268 1 1 0 .abs_section_268 + _PTIJ 269 1 1 0 .abs_section_269 + _DDRJ 26A 1 1 0 .abs_section_26a + _RDRJ 26B 1 1 0 .abs_section_26b + _PERJ 26C 1 1 0 .abs_section_26c + _PPSJ 26D 1 1 0 .abs_section_26d + _PIEJ 26E 1 1 0 .abs_section_26e + _PIFJ 26F 1 1 0 .abs_section_26f + _CAN4CTL0 280 1 1 0 .abs_section_280 + _CAN4CTL1 281 1 1 0 .abs_section_281 + _CAN4BTR0 282 1 1 0 .abs_section_282 + _CAN4BTR1 283 1 1 0 .abs_section_283 + _CAN4RFLG 284 1 1 0 .abs_section_284 + _CAN4RIER 285 1 1 0 .abs_section_285 + _CAN4TFLG 286 1 1 0 .abs_section_286 + _CAN4TIER 287 1 1 0 .abs_section_287 + _CAN4TARQ 288 1 1 0 .abs_section_288 + _CAN4TAAK 289 1 1 0 .abs_section_289 + _CAN4TBSEL 28A 1 1 0 .abs_section_28a + _CAN4IDAC 28B 1 1 0 .abs_section_28b + _CAN4RXERR 28E 1 1 0 .abs_section_28e + _CAN4TXERR 28F 1 1 0 .abs_section_28f + _CAN4IDAR0 290 1 1 0 .abs_section_290 + _CAN4IDAR1 291 1 1 0 .abs_section_291 + _CAN4IDAR2 292 1 1 0 .abs_section_292 + _CAN4IDAR3 293 1 1 0 .abs_section_293 + _CAN4IDMR0 294 1 1 0 .abs_section_294 + _CAN4IDMR1 295 1 1 0 .abs_section_295 + _CAN4IDMR2 296 1 1 0 .abs_section_296 + _CAN4IDMR3 297 1 1 0 .abs_section_297 + _CAN4IDAR4 298 1 1 0 .abs_section_298 + _CAN4IDAR5 299 1 1 0 .abs_section_299 + _CAN4IDAR6 29A 1 1 0 .abs_section_29a + _CAN4IDAR7 29B 1 1 0 .abs_section_29b + _CAN4IDMR4 29C 1 1 0 .abs_section_29c + _CAN4IDMR5 29D 1 1 0 .abs_section_29d + _CAN4IDMR6 29E 1 1 0 .abs_section_29e + _CAN4IDMR7 29F 1 1 0 .abs_section_29f + _CAN4RXIDR0 2A0 1 1 0 .abs_section_2a0 + _CAN4RXIDR1 2A1 1 1 0 .abs_section_2a1 + _CAN4RXIDR2 2A2 1 1 0 .abs_section_2a2 + _CAN4RXIDR3 2A3 1 1 0 .abs_section_2a3 + _CAN4RXDSR0 2A4 1 1 0 .abs_section_2a4 + _CAN4RXDSR1 2A5 1 1 0 .abs_section_2a5 + _CAN4RXDSR2 2A6 1 1 0 .abs_section_2a6 + _CAN4RXDSR3 2A7 1 1 0 .abs_section_2a7 + _CAN4RXDSR4 2A8 1 1 0 .abs_section_2a8 + _CAN4RXDSR5 2A9 1 1 0 .abs_section_2a9 + _CAN4RXDSR6 2AA 1 1 0 .abs_section_2aa + _CAN4RXDSR7 2AB 1 1 0 .abs_section_2ab + _CAN4RXDLR 2AC 1 1 0 .abs_section_2ac + _CAN4TXIDR0 2B0 1 1 0 .abs_section_2b0 + _CAN4TXIDR1 2B1 1 1 0 .abs_section_2b1 + _CAN4TXIDR2 2B2 1 1 0 .abs_section_2b2 + _CAN4TXIDR3 2B3 1 1 0 .abs_section_2b3 + _CAN4TXDSR0 2B4 1 1 0 .abs_section_2b4 + _CAN4TXDSR1 2B5 1 1 0 .abs_section_2b5 + _CAN4TXDSR2 2B6 1 1 0 .abs_section_2b6 + _CAN4TXDSR3 2B7 1 1 0 .abs_section_2b7 + _CAN4TXDSR4 2B8 1 1 0 .abs_section_2b8 + _CAN4TXDSR5 2B9 1 1 0 .abs_section_2b9 + _CAN4TXDSR6 2BA 1 1 0 .abs_section_2ba + _CAN4TXDSR7 2BB 1 1 0 .abs_section_2bb + _CAN4TXDLR 2BC 1 1 0 .abs_section_2bc + _CAN4TXTBPR 2BF 1 1 0 .abs_section_2bf + uxCriticalNesting 1000 1 1 101 .data + xLocalError 1001 1 1 2 .bss + xRxedChars 1002 2 2 3 .bss + xCharsForTx 1004 2 2 3 .bss + pxCurrentTCB 1006 2 2 28 .bss + uxTasksDeleted 1008 1 1 3 .bss + uxCurrentNumberOfTasks 1009 1 1 5 .bss + xTickCount 100A 2 2 14 .bss + uxTopUsedPriority 100C 1 1 2 .bss + uxTopReadyPriority 100D 1 1 15 .bss + xSchedulerRunning 100E 1 1 3 .bss + uxSchedulerSuspended 100F 1 1 6 .bss + uxMissedTicks 1010 1 1 4 .bss + uxTaskNumber.1 1011 1 1 2 .bss + pxReadyTasksLists 1012 3C 60 11 .bss + xDelayedTaskList1 104E F 15 2 .bss + xDelayedTaskList2 105D F 15 2 .bss + pxDelayedTaskList 106C 2 2 8 .bss + pxOverflowDelayedTaskList 106E 2 2 6 .bss + xPendingReadyList 1070 F 15 4 .bss + xTasksWaitingTermination 107F F 15 5 .bss + xSuspendedTaskList 108E F 15 2 .bss + xHeapHasBeenInitialised.1 109D 1 1 2 .bss + xHeap 109E 2804 10244 2 .bss + xStart 38A2 4 4 6 .bss + xEnd 38A6 4 4 4 .bss + uxFlashTaskNumber 38AA 1 1 2 .bss + usCheckVariable 38AB 2 2 4 .bss + xSuspendedQueueSendError 38AD 1 1 2 .bss + xSuspendedQueueReceiveError 38AE 1 1 3 .bss + ulValueToSend.6 38AF 4 4 5 .bss + ulExpectedValue.7 38B3 4 4 6 .bss + usLastTaskCheck.9 38B7 2 2 2 .bss + xContinousIncrementHandle 38B9 2 2 5 .bss + xLimitedIncrementHandle 38BB 2 2 2 .bss + ulCounter 38BD 4 4 10 .bss + ulReceivedValue.8 38C1 4 4 3 .bss + xPollingConsumerCount 38C5 1 1 3 .bss + xPollingProducerCount 38C6 1 1 3 .bss + xPolledQueue.1 38C7 2 2 3 .bss + xPort 38C9 2 2 2 .bss + uxBaseLED 38CB 1 1 5 .bss + uxRxLoops 38CC 1 1 3 .bss + xTaskCheck 38CD 1 1 3 .bss + sBlockingConsumerCount 38CE 6 6 5 .bss + sBlockingProducerCount 38D4 6 6 5 .bss + sLastBlockingConsumerCount.7 38DA 6 6 2 .bss + sLastBlockingProducerCount.8 38E0 6 6 2 .bss + usCreationCount 38E6 2 2 4 .bss + uxTasksRunningAtStart 38E8 1 1 4 .bss + usLastCreationCount.6 38E9 2 2 2 .bss + uxTasksRunningNow.7 38EB 1 1 1 .bss + xSuspendedTestQueue 38EC 2 2 3 .common + xCreatedTask1 38EE 2 2 2 .common + xCreatedTask2 38F0 2 2 2 .common + CmpHighVal 38F2 2 2 2 TickTimer_DATA + Byte1_Table 38F4 8 8 1 Byte1_DATA + COM0_PrescHigh.1 38FC 8 8 1 COM0_DATA + SerFlag 3904 2 2 1 COM0_DATA + PrescHigh 3906 2 2 2 COM0_DATA + NumMode 3908 1 1 2 COM0_DATA + _EntryPoint C000 2E 46 1 .init + PE_low_level_init C02E 4E 78 2 .init + STRING.Check.1 C09A 6 6 1 .rodata1 + STRING.IDLE.2 C0A0 5 5 1 .rodata1 + STRING.LEDx.1 C0A5 5 5 1 .rodata1 + STRING.CNT_INC.1 C0AA 8 8 1 .rodata1 + STRING.LIM_INC.2 C0B2 8 8 1 .rodata1 + STRING.C_CTRL.3 C0BA 7 7 1 .rodata1 + STRING.SUSP_TX.4 C0C1 8 8 1 .rodata1 + STRING.SUSP_RX.5 C0C9 8 8 1 .rodata1 + STRING.QConsNB.2 C0D1 8 8 1 .rodata1 + STRING.QProdNB.3 C0D9 8 8 1 .rodata1 + STRING.COMTx.1 C0E1 6 6 1 .rodata1 + STRING.COMRx.2 C0E7 6 6 1 .rodata1 + STRING.IntMath.1 C0ED 8 8 1 .rodata1 + STRING.QConsB1.1 C0F5 8 8 1 .rodata1 + STRING.QProdB2.2 C0FD 8 8 1 .rodata1 + STRING.QProdB3.3 C105 8 8 1 .rodata1 + STRING.QConsB4.4 C10D 8 8 1 .rodata1 + STRING.QProdB5.5 C115 8 8 1 .rodata1 + STRING.QConsB6.6 C11D 8 8 1 .rodata1 + STRING.CREATOR.1 C125 8 8 1 .rodata1 + STRING.SUICIDE1.2 C12D 9 9 1 .rodata1 + STRING.SUICIDE2.3 C136 9 9 1 .rodata1 + STRING.SUICIDE1.4 C13F 9 9 1 .rodata1 + STRING.SUICIDE2.5 C148 9 9 1 .rodata1 + _Startup C151 12 18 1 NON_BANKED + _LCMP C163 19 25 2 NON_BANKED + _LCMP_P C17C 15 21 3 NON_BANKED + _LNEG C191 D 13 2 NON_BANKED + _LINC C19E 5 5 4 NON_BANKED + _LMUL C1A3 27 39 1 NON_BANKED + _lDivMod C1CA E3 227 3 NON_BANKED + _LDIVU C2AD E 14 1 NON_BANKED + _NEG_P C2BB F 15 4 NON_BANKED + _LDIVS C2CA 35 53 2 NON_BANKED + Cpu_Interrupt C2FF 1 1 60 NON_BANKED + vCOM0_ISR C300 59 89 1 NON_BANKED + xBankedStartScheduler C359 13 19 1 NON_BANKED + vPortYield C36C 1D 29 1 NON_BANKED + vPortTickInterrupt C389 25 37 1 NON_BANKED + _BDMSTS FF01 1 1 0 .abs_section_ff01 + _BDMCCR FF06 1 1 0 .abs_section_ff06 + _BDMINR FF07 1 1 0 .abs_section_ff07 + _vect FF80 80 128 0 .abs_section_ff80 + Init 308000 29 41 2 .text + memcpy 308029 26 38 8 .text + memset 30804F 1E 30 2 .text + strncpy 30806D 2D 45 2 .text + main 30809A 9 9 0 .text + vMain 3080A3 52 82 1 .text + vErrorChecks 3080F5 33 51 3 .text + prvCheckOtherTasksAreStillRunning 308128 49 73 2 .text + vApplicationIdleHook 308171 70 112 2 .text + vParTestSetLED 3081E1 22 34 4 .text + vParTestToggleLED 308203 14 20 10 .text + xSerialPortInitMinimal 308217 24 36 2 .text + xSerialGetChar 30823B 17 23 2 .text + xSerialPutChar 318000 1D 29 2 ROM_PAGE31_524 + xTaskCreate 31801D D9 217 48 ROM_PAGE31_524 + vTaskDelete 3180F6 4A 74 4 ROM_PAGE31_524 + vTaskDelayUntil 318140 78 120 6 ROM_PAGE31_524 + vTaskDelay 3181B8 4A 74 16 ROM_PAGE31_524 + uxTaskPriorityGet 318202 26 38 2 ROM_PAGE31_524 + vTaskPrioritySet 328000 6B 107 4 ROM_PAGE32_525 + vTaskSuspend 32806B 47 71 6 ROM_PAGE32_525 + vTaskResume 3280B2 5B 91 6 ROM_PAGE32_525 + vTaskStartScheduler 32810D 35 53 2 ROM_PAGE32_525 + vTaskSuspendAll 328142 13 19 26 ROM_PAGE32_525 + xTaskResumeAll 328155 A5 165 30 ROM_PAGE32_525 + xTaskGetTickCount 3281FA 17 23 6 ROM_PAGE32_525 + uxTaskGetNumberOfTasks 328211 17 23 4 ROM_PAGE32_525 + vTaskIncrementTick 338000 84 132 4 ROM_PAGE33_526 + vTaskSwitchContext 338084 5B 91 4 ROM_PAGE33_526 + vTaskPlaceOnEventList 3380DF 44 68 4 ROM_PAGE33_526 + xTaskRemoveFromEventList 338123 6F 111 8 ROM_PAGE33_526 + prvIdleTask 338192 12 18 3 ROM_PAGE33_526 + prvInitialiseTCBVariables 3381A4 4F 79 2 ROM_PAGE33_526 + prvInitialiseTaskLists 3381F3 41 65 2 ROM_PAGE33_526 + prvCheckTasksWaitingTermination 348000 55 85 2 ROM_PAGE34_527 + prvAllocateTCBAndStack 348055 37 55 2 ROM_PAGE34_527 + prvDeleteTCB 34808C 11 17 2 ROM_PAGE34_527 + xQueueCreate 34809D 7C 124 14 ROM_PAGE34_527 + xQueueSend 348119 D4 212 9 ROM_PAGE34_527 + xQueueSendFromISR 3481ED 56 86 2 ROM_PAGE34_527 + xQueueReceive 358000 CE 206 9 ROM_PAGE35_528 + xQueueReceiveFromISR 3580CE 60 96 2 ROM_PAGE35_528 + uxQueueMessagesWaiting 35812E 1B 27 2 ROM_PAGE35_528 + prvUnlockQueue 358149 71 113 8 ROM_PAGE35_528 + prvIsQueueEmpty 3581BA 21 33 2 ROM_PAGE35_528 + prvIsQueueFull 3581DB 24 36 2 ROM_PAGE35_528 + vListInitialise 3581FF 20 32 6 ROM_PAGE35_528 + vListInitialiseItem 35821F 7 7 6 ROM_PAGE35_528 + vListInsertEnd 358226 27 39 16 ROM_PAGE35_528 + vListInsert 368000 5A 90 8 ROM_PAGE36_529 + vListRemove 36805A 23 35 32 ROM_PAGE36_529 + pvPortMalloc 36807D B6 182 14 ROM_PAGE36_529 + vPortFree 368133 34 52 10 ROM_PAGE36_529 + PE_Timer_LngHi1 368167 43 67 2 ROM_PAGE36_529 + vStartLEDFlashTasks 3681AA 2A 42 2 ROM_PAGE36_529 + vLEDFlashTask 3681D4 57 87 3 ROM_PAGE36_529 + vStartDynamicPriorityTasks 378000 9B 155 2 ROM_PAGE37_530 + vLimitedIncrementTask 37809B 22 34 3 ROM_PAGE37_530 + vContinuousIncrementTask 3780BD 33 51 3 ROM_PAGE37_530 + vCounterControlTask 3780F0 A0 160 5 ROM_PAGE37_530 + vQueueSendWhenSuspendedTask 378190 38 56 3 ROM_PAGE37_530 + vQueueReceiveWhenSuspendedTask 3781C8 53 83 3 ROM_PAGE37_530 + xAreDynamicPriorityTasksStillRunning 37821B 27 39 2 ROM_PAGE37_530 + vStartPolledQueueTasks 388000 49 73 2 ROM_PAGE38_531 + vPolledQueueProducer 388049 4F 79 3 ROM_PAGE38_531 + vPolledQueueConsumer 388098 5C 92 3 ROM_PAGE38_531 + xArePollingQueuesStillRunning 3880F4 1D 29 2 ROM_PAGE38_531 + vAltStartComTestTasks 388111 4D 77 2 ROM_PAGE38_531 + vComTxTask 38815E 51 81 3 ROM_PAGE38_531 + vComRxTask 3881AF 6A 106 3 ROM_PAGE38_531 + xAreComTestTasksStillRunning 388219 15 21 2 ROM_PAGE38_531 + pxPortInitialiseStack 398000 31 49 2 ROM_PAGE39_532 + prvSetupTimerInterrupt 398031 C 12 2 ROM_PAGE39_532 + xPortStartScheduler 39803D 4 4 2 ROM_PAGE39_532 + vStartIntegerMathTasks 398041 33 51 2 ROM_PAGE39_532 + vCompeteingIntMathTask 398074 87 135 3 ROM_PAGE39_532 + xAreIntegerMathsTaskStillRunning 3980FB 25 37 2 ROM_PAGE39_532 + vStartBlockingQueueTasks 3A8000 143 323 7 ROM_PAGE3A_533 + vBlockingQueueProducer 3A8143 3A 58 9 ROM_PAGE3A_533 + vBlockingQueueConsumer 3A817D 45 69 9 ROM_PAGE3A_533 + xAreBlockingQueuesStillRunning 3A81C2 49 73 2 ROM_PAGE3A_533 + vCreateSuicidalTasks 3A820B 33 51 2 ROM_PAGE3A_533 + vSuicidalTask 3B8000 52 82 12 ROM_PAGE3B_534 + vCreateTasks 3B8052 94 148 4 ROM_PAGE3B_534 + xIsCreateTaskStillRunning 3B80E6 36 54 2 ROM_PAGE3B_534 + SetCV 3B811C F 15 4 TickTimer_CODE + SetPV 3B812B C 12 2 TickTimer_CODE + HWEnDi 3B8137 8 8 4 TickTimer_CODE + TickTimer_Enable 3B813F 6 6 2 TickTimer_CODE + TickTimer_SetFreqHz 3B8145 51 81 2 TickTimer_CODE + TickTimer_Init 3B8196 15 21 2 TickTimer_CODE + Byte1_GetMsk 3B81AB D 13 4 Byte1_CODE + Byte1_PutBit 3B81B8 1F 31 2 Byte1_CODE + Byte1_NegBit 3B81D7 11 17 2 Byte1_CODE + HWEnDi 3B81E8 A 10 2 COM0_CODE + COM0_SetBaudRateMode 3B81F2 19 25 2 COM0_CODE + COM0_Init 3B820B 20 32 2 COM0_CODE + +********************************************************************************************* +UNUSED-OBJECTS SECTION +--------------------------------------------------------------------------------------------- +NOT USED PROCEDURES +STRING.C.o (ansibi.lib): + strerror memchr memcmp memcpy2 _memcpy_8bitCount memmove + _memset_clear_8bitCount strlen strset strcat strncat strcpy strcmp strncmp + strchr strrchr strspn strcspn strpbrk strstr strtok strcoll strxfrm +rtshc12.c.o (ansibi.lib): + _BSHL _BSHRS _BSHRU _BDIVMODU _BDIVMODS _ISHL _ISHRU _ISHRS _LSHL _LSHRU + _LSHRS _LADD _LSUB _LAND _LOR _LXOR _LCMP_PP _LABS _LCOM _LDEC _LMODU _LMODS + _ILSEXT _LTEST _COPY _CASE_DIRECT _CASE_DIRECT_BYTE _CASE_CHECKED + _CASE_CHECKED_BYTE _CASE_SEARCH _CASE_SEARCH_BYTE _CASE_SEARCH_8 + _CASE_SEARCH_8_BYTE _FCALL _FPCMP +serial.c.o: + vSerialClose +tasks.c.o: + vTaskEndScheduler +queue.c.o: + vQueueDelete +TickTimer.C.o: + TickTimer_Interrupt TickTimer_SetPeriodTicks16 TickTimer_SetPeriodTicks32 + TickTimer_SetPeriodUS TickTimer_SetPeriodMS +PE_Timer.C.o: + PE_Timer_LngMul PE_Timer_LngHi2 PE_Timer_LngHi3 PE_Timer_LngHi4 +port.c.o: + vPortEndScheduler +NOT USED VARIABLES +STRING.C.o (ansibi.lib): + STRING..1 next.2 +rtshc12.c.o (ansibi.lib): + _PowOfTwo_8 _PowOfTwo_16 _PowOfTwo_32 +Cpu.C.o: + CpuMode CCR_reg +heap_2.c.o: + heapSTRUCT_SIZE +death.c.o: + uxMaxNumberOfExtraTasksRunning + +********************************************************************************************* +COPYDOWN SECTION +--------------------------------------------------------------------------------------------- +------- ROM-ADDRESS: 0xC3AE ---- SIZE 4 --- +Filling bytes inserted + 00011000 +------- ROM-ADDRESS: 0xC3B2 ---- RAM-ADDRESS: 0x1000 ---- SIZE 1 --- +Name of initialized Object : uxCriticalNesting + FF +------- ROM-ADDRESS: 0xC3B3 ---- SIZE 4 --- +Filling bytes inserted + 001038F4 +------- ROM-ADDRESS: 0xC3B7 ---- RAM-ADDRESS: 0x38F4 ---- SIZE 8 --- +Name of initialized Object : Byte1_Table + 0102040810 204080 +------- ROM-ADDRESS: 0xC3BF ---- SIZE 1 --- +Filling bytes inserted + 00 +------- ROM-ADDRESS: 0xC3C0 ---- RAM-ADDRESS: 0x38FD ---- SIZE 7 --- +Name of initialized Object : COM0_PrescHigh.1:1 + 29005100A3 0146 +------- ROM-ADDRESS: 0xC3C7 ---- SIZE 2 --- +Filling bytes inserted + 0000 + +********************************************************************************************* +OBJECT-DEPENDENCIES SECTION +--------------------------------------------------------------------------------------------- +_EntryPoint USES _INITRM _INITEE _MISC _CLKSEL _PLLCTL _SYNR + _REFDV _CRGFLG _Startup +PE_low_level_init USES _TSCR1 _TCTL2 _TCTL1 _TIE _TTOV _TSCR2 _TIOS + _PWMCTL _PWMSDN _ICSYS _MCCTL TickTimer_Init _PORTAB + _DDRAB _DDRS _PTS COM0_Init _INTCR +_Startup USES _startupData Init +_LDIVU USES _lDivMod +_LDIVS USES _NEG_P _lDivMod +vCOM0_ISR USES _SCI0SR1 _SCI0DRL xRxedChars xQueueSendFromISR + _SCI0CR2 xCharsForTx xQueueReceiveFromISR +xBankedStartScheduler USES prvSetupTimerInterrupt pxCurrentTCB + uxCriticalNesting +vPortYield USES uxCriticalNesting pxCurrentTCB + vTaskSwitchContext +vPortTickInterrupt USES uxCriticalNesting pxCurrentTCB + vTaskIncrementTick vTaskSwitchContext _TFLG1 +_vect USES Cpu_Interrupt vCOM0_ISR vPortTickInterrupt + vPortYield _EntryPoint +Init USES _startupData +main USES PE_low_level_init vMain +vMain USES vStartLEDFlashTasks vStartPolledQueueTasks + vStartDynamicPriorityTasks vAltStartComTestTasks vStartBlockingQueueTasks + vStartIntegerMathTasks vCreateSuicidalTasks vErrorChecks + STRING.Check.1 xTaskCreate vTaskStartScheduler +vErrorChecks USES xTaskGetTickCount vTaskDelayUntil + prvCheckOtherTasksAreStillRunning _LCMP vParTestToggleLED +prvCheckOtherTasksAreStillRunning USES xArePollingQueuesStillRunning + xAreDynamicPriorityTasksStillRunning xAreComTestTasksStillRunning + xAreIntegerMathsTaskStillRunning xAreBlockingQueuesStillRunning + xIsCreateTaskStillRunning xLocalError +vApplicationIdleHook USES _LNEG _LDIVS _LCMP_P uxCriticalNesting + xLocalError +vParTestSetLED USES uxCriticalNesting Byte1_PutBit +vParTestToggleLED USES uxCriticalNesting Byte1_NegBit +xSerialPortInitMinimal USES xQueueCreate xRxedChars xCharsForTx + COM0_SetBaudRateMode +xSerialGetChar USES xRxedChars xQueueReceive +xSerialPutChar USES xCharsForTx xQueueSend _SCI0CR2 +xTaskCreate USES prvAllocateTCBAndStack + prvInitialiseTCBVariables pxPortInitialiseStack uxCriticalNesting + uxCurrentNumberOfTasks pxCurrentTCB prvInitialiseTaskLists + xSchedulerRunning uxTopUsedPriority uxTaskNumber.1 + uxTopReadyPriority pxReadyTasksLists vListInsertEnd +vTaskDelete USES uxCriticalNesting pxCurrentTCB vListRemove + xTasksWaitingTermination vListInsertEnd uxTasksDeleted +vTaskDelayUntil USES vTaskSuspendAll xTickCount pxCurrentTCB + vListRemove pxOverflowDelayedTaskList pxDelayedTaskList + vListInsert xTaskResumeAll +vTaskDelay USES vTaskSuspendAll xTickCount pxCurrentTCB + vListRemove pxOverflowDelayedTaskList pxDelayedTaskList + vListInsert xTaskResumeAll +uxTaskPriorityGet USES uxCriticalNesting pxCurrentTCB +vTaskPrioritySet USES uxCriticalNesting pxCurrentTCB + pxReadyTasksLists vListRemove uxTopReadyPriority vListInsertEnd +vTaskSuspend USES uxCriticalNesting pxCurrentTCB vListRemove + xSuspendedTaskList vListInsertEnd +vTaskResume USES uxCriticalNesting pxCurrentTCB vListRemove + uxTopReadyPriority pxReadyTasksLists vListInsertEnd +vTaskStartScheduler USES pxCurrentTCB prvIdleTask STRING.IDLE.2 + xTaskCreate xSchedulerRunning xTickCount + xPortStartScheduler +vTaskSuspendAll USES uxCriticalNesting uxSchedulerSuspended +xTaskResumeAll USES uxCriticalNesting uxSchedulerSuspended + uxCurrentNumberOfTasks vListRemove uxTopReadyPriority + pxReadyTasksLists vListInsertEnd pxCurrentTCB xPendingReadyList + uxMissedTicks vTaskIncrementTick +xTaskGetTickCount USES uxCriticalNesting xTickCount +uxTaskGetNumberOfTasks USES uxCriticalNesting uxCurrentNumberOfTasks +vTaskIncrementTick USES uxSchedulerSuspended xTickCount + pxDelayedTaskList pxOverflowDelayedTaskList vListRemove + uxTopReadyPriority pxReadyTasksLists vListInsertEnd uxMissedTicks +vTaskSwitchContext USES uxSchedulerSuspended uxTopReadyPriority + pxCurrentTCB pxReadyTasksLists +vTaskPlaceOnEventList USES pxCurrentTCB vListInsert xTickCount vListRemove + pxOverflowDelayedTaskList pxDelayedTaskList +xTaskRemoveFromEventList USES vListRemove uxSchedulerSuspended + uxTopReadyPriority pxReadyTasksLists xPendingReadyList + vListInsertEnd pxCurrentTCB +prvIdleTask USES prvCheckTasksWaitingTermination + pxReadyTasksLists vApplicationIdleHook +prvInitialiseTCBVariables USES strncpy vListInitialiseItem +prvInitialiseTaskLists USES pxReadyTasksLists xDelayedTaskList1 + xDelayedTaskList2 xPendingReadyList xTasksWaitingTermination + xSuspendedTaskList pxDelayedTaskList pxOverflowDelayedTaskList + vListInitialise +prvCheckTasksWaitingTermination USES uxTasksDeleted vTaskSuspendAll + xTasksWaitingTermination xTaskResumeAll uxCriticalNesting vListRemove + uxCurrentNumberOfTasks prvDeleteTCB +prvAllocateTCBAndStack USES pvPortMalloc vPortFree memset +prvDeleteTCB USES vPortFree +xQueueCreate USES pvPortMalloc vListInitialise vPortFree +xQueueSend USES vTaskSuspendAll uxCriticalNesting xQueueSend + prvIsQueueFull vTaskPlaceOnEventList prvUnlockQueue + xTaskResumeAll memcpy +xQueueSendFromISR USES memcpy xTaskRemoveFromEventList +xQueueReceive USES vTaskSuspendAll uxCriticalNesting xQueueReceive + prvIsQueueEmpty vTaskPlaceOnEventList prvUnlockQueue + xTaskResumeAll memcpy +xQueueReceiveFromISR USES memcpy xTaskRemoveFromEventList +uxQueueMessagesWaiting USES uxCriticalNesting +prvUnlockQueue USES uxCriticalNesting xTaskRemoveFromEventList +prvIsQueueEmpty USES uxCriticalNesting +prvIsQueueFull USES uxCriticalNesting +vListInitialise USES vListInitialiseItem +pvPortMalloc USES vTaskSuspendAll xHeapHasBeenInitialised.1 xHeap + xStart xEnd xTaskResumeAll +vPortFree USES vTaskSuspendAll xStart xTaskResumeAll +PE_Timer_LngHi1 USES _LCMP +vStartLEDFlashTasks USES vLEDFlashTask STRING.LEDx.1 xTaskCreate +vLEDFlashTask USES uxCriticalNesting uxFlashTaskNumber + xTaskGetTickCount vTaskDelayUntil vParTestToggleLED +vStartDynamicPriorityTasks USES xQueueCreate xSuspendedTestQueue + vContinuousIncrementTask STRING.CNT_INC.1 ulCounter + xContinousIncrementHandle xTaskCreate vLimitedIncrementTask + STRING.LIM_INC.2 xLimitedIncrementHandle vCounterControlTask + STRING.C_CTRL.3 vQueueSendWhenSuspendedTask STRING.SUSP_TX.4 + vQueueReceiveWhenSuspendedTask STRING.SUSP_RX.5 +vLimitedIncrementTask USES _LINC _LCMP_P vTaskSuspend +vContinuousIncrementTask USES uxTaskPriorityGet vTaskPrioritySet _LINC +vCounterControlTask USES vCounterControlTask xContinousIncrementHandle + vTaskSuspend ulCounter vTaskResume vTaskDelay + vTaskSuspendAll xTaskResumeAll xLimitedIncrementHandle + uxCriticalNesting usCheckVariable +vQueueSendWhenSuspendedTask USES vTaskSuspendAll xSuspendedTestQueue + ulValueToSend.6 xQueueSend xSuspendedQueueSendError + xTaskResumeAll vTaskDelay _LINC +vQueueReceiveWhenSuspendedTask USES vTaskSuspendAll xSuspendedTestQueue + ulReceivedValue.8 xQueueReceive xTaskResumeAll + xSuspendedQueueReceiveError ulExpectedValue.7 _LINC +xAreDynamicPriorityTasksStillRunning USES usCheckVariable usLastTaskCheck.9 + xSuspendedQueueSendError xSuspendedQueueReceiveError +vStartPolledQueueTasks USES xQueueCreate xPolledQueue.1 + vPolledQueueConsumer STRING.QConsNB.2 xTaskCreate + vPolledQueueProducer STRING.QProdNB.3 +vPolledQueueProducer USES xQueueSend uxCriticalNesting + xPollingProducerCount vTaskDelay +vPolledQueueConsumer USES xQueueReceive uxCriticalNesting + xPollingConsumerCount uxQueueMessagesWaiting vTaskDelay +xArePollingQueuesStillRunning USES xPollingConsumerCount xPollingProducerCount +vAltStartComTestTasks USES uxBaseLED xSerialPortInitMinimal vComTxTask + STRING.COMTx.1 xTaskCreate vComRxTask STRING.COMRx.2 +vComTxTask USES xPort xSerialPutChar uxBaseLED + vParTestToggleLED vParTestSetLED xTaskGetTickCount vTaskDelay +vComRxTask USES uxBaseLED vParTestToggleLED vParTestSetLED + uxRxLoops xPort xSerialGetChar +xAreComTestTasksStillRunning USES uxRxLoops +prvSetupTimerInterrupt USES TickTimer_SetFreqHz TickTimer_Enable +xPortStartScheduler USES xBankedStartScheduler +vStartIntegerMathTasks USES vCompeteingIntMathTask STRING.IntMath.1 + xTaskCheck xTaskCreate +vCompeteingIntMathTask USES _LNEG _LDIVS _LCMP_P uxCriticalNesting +xAreIntegerMathsTaskStillRunning USES xTaskCheck +vStartBlockingQueueTasks USES vStartBlockingQueueTasks xQueueCreate + sBlockingConsumerCount sBlockingProducerCount vBlockingQueueConsumer + STRING.QConsB1.1 xTaskCreate vBlockingQueueProducer + STRING.QProdB2.2 STRING.QProdB3.3 STRING.QConsB4.4 + STRING.QProdB5.5 STRING.QConsB6.6 pvPortMalloc +vBlockingQueueProducer USES xQueueSend +vBlockingQueueConsumer USES xQueueReceive +xAreBlockingQueuesStillRunning USES sBlockingConsumerCount + sLastBlockingConsumerCount.7 sBlockingProducerCount + sLastBlockingProducerCount.8 +vCreateSuicidalTasks USES pvPortMalloc vCreateTasks STRING.CREATOR.1 + xTaskCreate uxTaskGetNumberOfTasks uxTasksRunningAtStart +vSuicidalTask USES _LMUL vTaskDelay vTaskDelete +vCreateTasks USES vPortFree vTaskDelay vSuicidalTask + STRING.SUICIDE1.2 xCreatedTask1 xTaskCreate STRING.SUICIDE2.3 + STRING.SUICIDE1.4 xCreatedTask2 STRING.SUICIDE2.5 + usCreationCount vCreateTasks +xIsCreateTaskStillRunning USES usLastCreationCount.6 usCreationCount + uxTaskGetNumberOfTasks uxTasksRunningNow.7 uxTasksRunningAtStart +SetCV USES _TC0 _TC7 +SetPV USES _TSCR2 +HWEnDi USES _TFLG1 _TIE +TickTimer_Enable USES HWEnDi +TickTimer_SetFreqHz USES _LDIVU PE_Timer_LngHi1 CmpHighVal SetCV +TickTimer_Init USES CmpHighVal SetCV SetPV HWEnDi +Byte1_GetMsk USES Byte1_Table +Byte1_PutBit USES Byte1_GetMsk _PORTAB +Byte1_NegBit USES Byte1_GetMsk _PORTAB +HWEnDi USES _SCI0CR2 +COM0_SetBaudRateMode USES NumMode COM0_PrescHigh.1 PrescHigh _SCI0BD +COM0_Init USES PrescHigh SerFlag NumMode _SCI0CR1 _SCI0SR2 + _SCI0SR1 _SCI0CR2 _SCI0BD HWEnDi + +********************************************************************************************* +DEPENDENCY TREE +********************************************************************************************* + main and _Startup Group + | + +- main + | | + | +- PE_low_level_init + | | | + | | +- TickTimer_Init + | | | | + | | | +- SetCV + | | | | + | | | +- SetPV + | | | | + | | | +- HWEnDi + | | | + | | +- COM0_Init + | | | + | | +- HWEnDi + | | + | +- vMain + | | + | +- vStartLEDFlashTasks + | | | + | | +- vLEDFlashTask + | | | | + | | | +- xTaskGetTickCount + | | | | + | | | +- vTaskDelayUntil + | | | | | + | | | | +- vTaskSuspendAll + | | | | | + | | | | +- vListRemove + | | | | | + | | | | +- vListInsert + | | | | | + | | | | +- xTaskResumeAll + | | | | | + | | | | +- vListRemove (see above) + | | | | | + | | | | +- vListInsertEnd + | | | | | + | | | | +- vTaskIncrementTick + | | | | | + | | | | +- vListRemove (see above) + | | | | | + | | | | +- vListInsertEnd (see above) + | | | | + | | | +- vParTestToggleLED + | | | | + | | | +- Byte1_NegBit + | | | | + | | | +- Byte1_GetMsk + | | | + | | +- xTaskCreate + | | | + | | +- prvAllocateTCBAndStack + | | | | + | | | +- pvPortMalloc + | | | | | + | | | | +- vTaskSuspendAll (see above) + | | | | | + | | | | +- xTaskResumeAll (see above) + | | | | + | | | +- vPortFree + | | | | | + | | | | +- vTaskSuspendAll (see above) + | | | | | + | | | | +- xTaskResumeAll (see above) + | | | | + | | | +- memset + | | | + | | +- prvInitialiseTCBVariables + | | | | + | | | +- strncpy + | | | | + | | | +- vListInitialiseItem + | | | + | | +- pxPortInitialiseStack + | | | + | | +- prvInitialiseTaskLists + | | | | + | | | +- vListInitialise + | | | | + | | | +- vListInitialiseItem (see above) + | | | + | | +- vListInsertEnd (see above) + | | + | +- vStartPolledQueueTasks + | | | + | | +- xQueueCreate + | | | | + | | | +- pvPortMalloc (see above) + | | | | + | | | +- vListInitialise (see above) + | | | | + | | | +- vPortFree (see above) + | | | + | | +- vPolledQueueConsumer + | | | | + | | | +- xQueueReceive + | | | | | + | | | | +- vTaskSuspendAll (see above) + | | | | | + | | | | +- prvIsQueueEmpty + | | | | | + | | | | +- vTaskPlaceOnEventList + | | | | | | + | | | | | +- vListInsert (see above) + | | | | | | + | | | | | +- vListRemove (see above) + | | | | | + | | | | +- prvUnlockQueue + | | | | | | + | | | | | +- xTaskRemoveFromEventList + | | | | | | + | | | | | +- vListRemove (see above) + | | | | | | + | | | | | +- vListInsertEnd (see above) + | | | | | + | | | | +- xTaskResumeAll (see above) + | | | | | + | | | | +- memcpy + | | | | + | | | +- uxQueueMessagesWaiting + | | | | + | | | +- vTaskDelay + | | | | + | | | +- vTaskSuspendAll (see above) + | | | | + | | | +- vListRemove (see above) + | | | | + | | | +- vListInsert (see above) + | | | | + | | | +- xTaskResumeAll (see above) + | | | + | | +- xTaskCreate (see above) + | | | + | | +- vPolledQueueProducer + | | | + | | +- xQueueSend + | | | | + | | | +- vTaskSuspendAll (see above) + | | | | + | | | +- prvIsQueueFull + | | | | + | | | +- vTaskPlaceOnEventList (see above) + | | | | + | | | +- prvUnlockQueue (see above) + | | | | + | | | +- xTaskResumeAll (see above) + | | | | + | | | +- memcpy (see above) + | | | + | | +- vTaskDelay (see above) + | | + | +- vStartDynamicPriorityTasks + | | | + | | +- xQueueCreate (see above) + | | | + | | +- vContinuousIncrementTask + | | | | + | | | +- uxTaskPriorityGet + | | | | + | | | +- vTaskPrioritySet + | | | | | + | | | | +- vListRemove (see above) + | | | | | + | | | | +- vListInsertEnd (see above) + | | | | + | | | +- _LINC + | | | + | | +- xTaskCreate (see above) + | | | + | | +- vLimitedIncrementTask + | | | | + | | | +- _LINC (see above) + | | | | + | | | +- _LCMP_P + | | | | + | | | +- vTaskSuspend + | | | | + | | | +- vListRemove (see above) + | | | | + | | | +- vListInsertEnd (see above) + | | | + | | +- vCounterControlTask + | | | | + | | | +- vTaskSuspend (see above) + | | | | + | | | +- vTaskResume + | | | | | + | | | | +- vListRemove (see above) + | | | | | + | | | | +- vListInsertEnd (see above) + | | | | + | | | +- vTaskDelay (see above) + | | | | + | | | +- vTaskSuspendAll (see above) + | | | | + | | | +- xTaskResumeAll (see above) + | | | + | | +- vQueueSendWhenSuspendedTask + | | | | + | | | +- vTaskSuspendAll (see above) + | | | | + | | | +- xQueueSend (see above) + | | | | + | | | +- xTaskResumeAll (see above) + | | | | + | | | +- vTaskDelay (see above) + | | | | + | | | +- _LINC (see above) + | | | + | | +- vQueueReceiveWhenSuspendedTask + | | | + | | +- vTaskSuspendAll (see above) + | | | + | | +- xQueueReceive (see above) + | | | + | | +- xTaskResumeAll (see above) + | | | + | | +- _LINC (see above) + | | + | +- vAltStartComTestTasks + | | | + | | +- xSerialPortInitMinimal + | | | | + | | | +- xQueueCreate (see above) + | | | | + | | | +- COM0_SetBaudRateMode + | | | + | | +- vComTxTask + | | | | + | | | +- xSerialPutChar + | | | | | + | | | | +- xQueueSend (see above) + | | | | + | | | +- vParTestToggleLED (see above) + | | | | + | | | +- vParTestSetLED + | | | | | + | | | | +- Byte1_PutBit + | | | | | + | | | | +- Byte1_GetMsk (see above) + | | | | + | | | +- xTaskGetTickCount (see above) + | | | | + | | | +- vTaskDelay (see above) + | | | + | | +- xTaskCreate (see above) + | | | + | | +- vComRxTask + | | | + | | +- vParTestToggleLED (see above) + | | | + | | +- vParTestSetLED (see above) + | | | + | | +- xSerialGetChar + | | | + | | +- xQueueReceive (see above) + | | + | +- vStartBlockingQueueTasks + | | | + | | +- xQueueCreate (see above) + | | | + | | +- vBlockingQueueConsumer + | | | | + | | | +- xQueueReceive (see above) + | | | + | | +- xTaskCreate (see above) + | | | + | | +- vBlockingQueueProducer + | | | | + | | | +- xQueueSend (see above) + | | | + | | +- pvPortMalloc (see above) + | | + | +- vStartIntegerMathTasks + | | | + | | +- vCompeteingIntMathTask + | | | | + | | | +- _LNEG + | | | | + | | | +- _LDIVS + | | | | | + | | | | +- _NEG_P + | | | | | + | | | | +- _lDivMod + | | | | + | | | +- _LCMP_P (see above) + | | | + | | +- xTaskCreate (see above) + | | + | +- vCreateSuicidalTasks + | | | + | | +- pvPortMalloc (see above) + | | | + | | +- vCreateTasks + | | | | + | | | +- vPortFree (see above) + | | | | + | | | +- vTaskDelay (see above) + | | | | + | | | +- vSuicidalTask + | | | | | + | | | | +- _LMUL + | | | | | + | | | | +- vTaskDelay (see above) + | | | | | + | | | | +- vTaskDelete + | | | | | + | | | | +- vListRemove (see above) + | | | | | + | | | | +- vListInsertEnd (see above) + | | | | + | | | +- xTaskCreate (see above) + | | | + | | +- xTaskCreate (see above) + | | | + | | +- uxTaskGetNumberOfTasks + | | + | +- vErrorChecks + | | | + | | +- xTaskGetTickCount (see above) + | | | + | | +- vTaskDelayUntil (see above) + | | | + | | +- prvCheckOtherTasksAreStillRunning + | | | | + | | | +- xArePollingQueuesStillRunning + | | | | + | | | +- xAreDynamicPriorityTasksStillRunning + | | | | + | | | +- xAreComTestTasksStillRunning + | | | | + | | | +- xAreIntegerMathsTaskStillRunning + | | | | + | | | +- xAreBlockingQueuesStillRunning + | | | | + | | | +- xIsCreateTaskStillRunning + | | | | + | | | +- uxTaskGetNumberOfTasks (see above) + | | | + | | +- _LCMP + | | | + | | +- vParTestToggleLED (see above) + | | + | +- xTaskCreate (see above) + | | + | +- vTaskStartScheduler + | | + | +- prvIdleTask + | | | + | | +- prvCheckTasksWaitingTermination + | | | | + | | | +- vTaskSuspendAll (see above) + | | | | + | | | +- xTaskResumeAll (see above) + | | | | + | | | +- vListRemove (see above) + | | | | + | | | +- prvDeleteTCB + | | | | + | | | +- vPortFree (see above) + | | | + | | +- vApplicationIdleHook + | | | + | | +- _LNEG (see above) + | | | + | | +- _LDIVS (see above) + | | | + | | +- _LCMP_P (see above) + | | + | +- xTaskCreate (see above) + | | + | +- xPortStartScheduler + | | + | +- xBankedStartScheduler + | | + | +- prvSetupTimerInterrupt + | | + | +- TickTimer_SetFreqHz + | | | + | | +- _LDIVU + | | | | + | | | +- _lDivMod (see above) + | | | + | | +- PE_Timer_LngHi1 + | | | | + | | | +- _LCMP (see above) + | | | + | | +- SetCV (see above) + | | + | +- TickTimer_Enable + | | + | +- HWEnDi (see above) + | + +- _EntryPoint + | + +- _Startup + | + +- Init + + _vect + | + +- Cpu_Interrupt + | + +- vCOM0_ISR + | | + | +- xQueueSendFromISR + | | | + | | +- memcpy (see above) + | | | + | | +- xTaskRemoveFromEventList (see above) + | | + | +- xQueueReceiveFromISR + | | + | +- memcpy (see above) + | | + | +- xTaskRemoveFromEventList (see above) + | + +- vPortTickInterrupt + | | + | +- vTaskIncrementTick (see above) + | | + | +- vTaskSwitchContext + | + +- vPortYield + | | + | +- vTaskSwitchContext (see above) + | + +- _EntryPoint (see above) + +********************************************************************************************* +STATISTIC SECTION +--------------------------------------------------------------------------------------------- + +ExeFile: +-------- +Number of blocks to be downloaded: 19 +Total size of all blocks to be downloaded: 7635 + diff --git a/20080212/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Erase_unsecure_hcs12.cmd b/20080212/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Erase_unsecure_hcs12.cmd new file mode 100644 index 000000000..eecca9d13 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Erase_unsecure_hcs12.cmd @@ -0,0 +1,66 @@ +// HCS12 Core erasing + unsecuring command file: +// These commands mass erase the chip then program the security byte to 0xFE (unsecured state). + +// Evaluate the clock divider to set in ECLKDIV/FCLKDIV registers: + +// An average programming clock of 175 kHz is chosen. + +// If the oscillator frequency is less than 10 MHz, the value to store +// in ECLKDIV/FCLKDIV is equal to " oscillator frequency (kHz) / 175 ". + +// If the oscillator frequency is higher than 10 MHz, the value to store +// in ECLKDIV/FCLKDIV is equal to " oscillator frequency (kHz) / 1400 + 0x40 (to set PRDIV8 flag)". + +// Datasheet proposed values: +// +// oscillator frequency ECLKDIV/FCLKDIV value (hexadecimal) +// +// 16 MHz $49 +// 8 MHz $27 +// 4 MHz $13 +// 2 MHz $9 +// 1 MHz $4 + +define CLKDIV 0x49 + +FLASH MEMUNMAP // do not interact with regular flash programming monitor + +//mass erase flash +wb 0x100 CLKDIV // set FCLKDIV clock divider +wb 0x103 0 // FCFNG select block 0 +wb 0x102 0x10 // set the WRALL bit in FTSTMOD to affect all blocks +wb 0x104 0xFF // FPROT all protection disabled +wb 0x105 0x30 // clear PVIOL and ACCERR in FSTAT register +ww 0x108 0xD000 // write to FADDR address register +ww 0x10A 0x0000 // write to FDATA data register +wb 0x106 0x41 // write MASS ERASE command in FCMD register +wb 0x105 0x80 // clear CBEIF in FSTAT register to execute the command +wait 20 // wait for command to complete + +//mass erase eeprom +wb 0x110 CLKDIV // set ECLKDV clock divider +wb 0x114 0xFF // EPROT all protection disabled +wb 0x115 0x30 // clear PVIOL and ACCERR in ESTAT register +ww 0x118 0x0400 // write to EADDR eeprom address register +ww 0x11A 0x0000 // write to EDATA eeprom data register +wb 0x116 0x41 // write MASS ERASE command in ECMD register +wb 0x115 0x80 // clear CBEIF in ESTAT register to execute the command +wait 20 // wait for command to complete + +reset + +//reprogram Security byte to Unsecure state +wb 0x100 CLKDIV // set FCLKDIV clock divider +wb 0x103 0 // FCFNG select block 0 +wb 0x104 0xFF // FPROT all protection disabled +wb 0x105 0x30 // clear PVIOL and ACCERR in FSTAT register +ww 0xFF0E 0xFFFE // write security byte to "Unsecured" state +wb 0x106 0x20 // write MEMORY PROGRAM command in FCMD register +wb 0x105 0x80 // clear CBEIF in FSTAT register to execute the command +wait 20 // wait for command to complete + +reset + +FLASH MEMMAP // restore regular flash programming monitor +undef CLKDIV // undefine variable + diff --git a/20080212/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Postload.cmd b/20080212/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Postload.cmd new file mode 100644 index 000000000..0a5372487 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Postload.cmd @@ -0,0 +1,3 @@ +// After load the commands written below will be executed +// Show main function at startup +FindProc main diff --git a/20080212/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Preload.cmd b/20080212/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Preload.cmd new file mode 100644 index 000000000..691c5eede --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Preload.cmd @@ -0,0 +1 @@ +// Before load the commands written below will be executed diff --git a/20080212/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Reset.cmd b/20080212/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Reset.cmd new file mode 100644 index 000000000..f0fc87448 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Reset.cmd @@ -0,0 +1 @@ +// After reset the commands written below will be executed diff --git a/20080212/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Startup.cmd b/20080212/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Startup.cmd new file mode 100644 index 000000000..5f2b5a568 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Startup.cmd @@ -0,0 +1 @@ +// At startup the commands written below will be executed diff --git a/20080212/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Vppoff.cmd b/20080212/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Vppoff.cmd new file mode 100644 index 000000000..52e399a61 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Vppoff.cmd @@ -0,0 +1 @@ +// After programming the flash, the commands written below will be executed diff --git a/20080212/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Vppon.cmd b/20080212/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Vppon.cmd new file mode 100644 index 000000000..048a6d94d --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Vppon.cmd @@ -0,0 +1 @@ +// Before programming the flash, the commands written below will be executed diff --git a/20080212/Demo/HCS12_CodeWarrior_banked/cmd/Simulator_Postload.cmd b/20080212/Demo/HCS12_CodeWarrior_banked/cmd/Simulator_Postload.cmd new file mode 100644 index 000000000..0a5372487 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_banked/cmd/Simulator_Postload.cmd @@ -0,0 +1,3 @@ +// After load the commands written below will be executed +// Show main function at startup +FindProc main diff --git a/20080212/Demo/HCS12_CodeWarrior_banked/cmd/Simulator_Preload.cmd b/20080212/Demo/HCS12_CodeWarrior_banked/cmd/Simulator_Preload.cmd new file mode 100644 index 000000000..691c5eede --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_banked/cmd/Simulator_Preload.cmd @@ -0,0 +1 @@ +// Before load the commands written below will be executed diff --git a/20080212/Demo/HCS12_CodeWarrior_banked/cmd/Simulator_Reset.cmd b/20080212/Demo/HCS12_CodeWarrior_banked/cmd/Simulator_Reset.cmd new file mode 100644 index 000000000..f0fc87448 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_banked/cmd/Simulator_Reset.cmd @@ -0,0 +1 @@ +// After reset the commands written below will be executed diff --git a/20080212/Demo/HCS12_CodeWarrior_banked/cmd/Simulator_SetCPU.cmd b/20080212/Demo/HCS12_CodeWarrior_banked/cmd/Simulator_SetCPU.cmd new file mode 100644 index 000000000..5f2b5a568 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_banked/cmd/Simulator_SetCPU.cmd @@ -0,0 +1 @@ +// At startup the commands written below will be executed diff --git a/20080212/Demo/HCS12_CodeWarrior_banked/cmd/Simulator_Startup.cmd b/20080212/Demo/HCS12_CodeWarrior_banked/cmd/Simulator_Startup.cmd new file mode 100644 index 000000000..5f2b5a568 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_banked/cmd/Simulator_Startup.cmd @@ -0,0 +1 @@ +// At startup the commands written below will be executed diff --git a/20080212/Demo/HCS12_CodeWarrior_banked/main.c b/20080212/Demo/HCS12_CodeWarrior_banked/main.c new file mode 100644 index 000000000..5ff6d01b0 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_banked/main.c @@ -0,0 +1,301 @@ + +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +/* + * + * vMain() is effectively the demo application entry point. It is called by + * the main() function generated by the Processor Expert application. + * + * vMain() creates all the demo application tasks, then starts the scheduler. + * The WEB documentation provides more details of the demo application tasks. + * + * Main.c also creates a task called "Check". This only executes every three + * seconds but has the highest priority so is guaranteed to get processor time. + * Its main function is to check that all the other tasks are still operational. + * Each task (other than the "flash" tasks) maintains a unique count that is + * incremented each time the task successfully completes its function. Should + * any error occur within such a task the count is permanently halted. The + * check task inspects the count of each task to ensure it has changed since + * the last time the check task executed. If all the count variables have + * changed all the tasks are still executing error free, and the check task + * toggles the onboard LED. Should any task contain an error at any time + * the LED toggle rate will change from 3 seconds to 500ms. + * + * This file also includes the functionality implemented within the + * standard demo application file integer.c. This is done to demonstrate the + * use of an idle hook. See the documentation within integer.c for the + * rationale of the integer task functionality. + * */ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* Demo application includes. */ +#include "flash.h" +#include "PollQ.h" +#include "dynamic.h" +#include "partest.h" +#include "comtest2.h" +#include "BlockQ.h" +#include "integer.h" +#include "death.h" + + +/*----------------------------------------------------------- + Definitions. +-----------------------------------------------------------*/ + +/* Priorities assigned to demo application tasks. */ +#define mainFLASH_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainDEATH_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* LED that is toggled by the check task. The check task periodically checks +that all the other tasks are operating without error. If no errors are found +the LED is toggled with mainCHECK_PERIOD frequency. If an error is found +then the toggle rate increases to mainERROR_CHECK_PERIOD. */ +#define mainCHECK_TASK_LED ( 7 ) +#define mainCHECK_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS ) +#define mainERROR_CHECK_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS ) + +/* The constants used in the idle task calculation. */ +#define intgCONST1 ( ( portLONG ) 123 ) +#define intgCONST2 ( ( portLONG ) 234567 ) +#define intgCONST3 ( ( portLONG ) -3 ) +#define intgCONST4 ( ( portLONG ) 7 ) +#define intgEXPECTED_ANSWER ( ( ( intgCONST1 + intgCONST2 ) * intgCONST3 ) / intgCONST4 ) + + +/* Baud rate used by the serial port tasks (ComTest tasks). +IMPORTANT: The function COM0_SetBaudRateValue() which is generated by the +Processor Expert is used to set the baud rate. As configured in the FreeRTOS +download this value must be one of the following: + +0 to configure for 38400 baud. +1 to configure for 19200 baud. +2 to configure for 9600 baud. +3 to configure for 4800 baud. */ +#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 2 ) + +/* LED used by the serial port tasks. This is toggled on each character Tx, +and mainCOM_TEST_LED + 1 is toggles on each character Rx. */ +#define mainCOM_TEST_LED ( 3 ) + +/*----------------------------------------------------------- + Local functions prototypes. +-----------------------------------------------------------*/ + +/* + * The 'Check' task function. See the explanation at the top of the file. + */ +static void vErrorChecks( void* pvParameters ); + +/* + * The idle task hook - in which the integer task is implemented. See the + * explanation at the top of the file. + */ +void vApplicationIdleHook( void ); + +/* + * Checks the unique counts of other tasks to ensure they are still operational. + */ +static portLONG prvCheckOtherTasksAreStillRunning( void ); + + + +/*----------------------------------------------------------- + Local variables. +-----------------------------------------------------------*/ + +/* A few tasks are defined within this file. This flag is used to indicate +their status. If an error is detected in one of the locally defined tasks then +this flag is set to pdTRUE. */ +portBASE_TYPE xLocalError = pdFALSE; + + +/*-----------------------------------------------------------*/ + +/* + * This is called from the main() function generated by the Processor Expert. + */ +void vMain( void ) +{ + /* Start some of the standard demo tasks. */ + vStartLEDFlashTasks( mainFLASH_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartDynamicPriorityTasks(); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + + /* Start the locally defined tasks. There is also a task implemented as + the idle hook. */ + xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Must be the last demo created. */ + vCreateSuicidalTasks( mainDEATH_PRIORITY ); + + /* All the tasks have been created - start the scheduler. */ + vTaskStartScheduler(); + + /* Should not reach here! */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void vErrorChecks( void *pvParameters ) +{ +portTickType xDelayPeriod = mainCHECK_PERIOD; +portTickType xLastWakeTime; + + /* Initialise xLastWakeTime to ensure the first call to vTaskDelayUntil() + functions correctly. */ + xLastWakeTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Delay until it is time to execute again. The delay period is + shorter following an error. */ + vTaskDelayUntil( &xLastWakeTime, xDelayPeriod ); + + /* Check all the demo application tasks are executing without + error. If an error is found the delay period is shortened - this + has the effect of increasing the flash rate of the 'check' task + LED. */ + if( prvCheckOtherTasksAreStillRunning() == pdFAIL ) + { + /* An error has been detected in one of the tasks - flash faster. */ + xDelayPeriod = mainERROR_CHECK_PERIOD; + } + + /* Toggle the LED each cycle round. */ + vParTestToggleLED( mainCHECK_TASK_LED ); + } +} +/*-----------------------------------------------------------*/ + +static portLONG prvCheckOtherTasksAreStillRunning( void ) +{ +portBASE_TYPE xAllTasksPassed = pdPASS; + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + xAllTasksPassed = pdFAIL; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + xAllTasksPassed = pdFAIL; + } + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + xAllTasksPassed = pdFALSE; + } + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + xAllTasksPassed = pdFALSE; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + xAllTasksPassed = pdFALSE; + } + + if( xIsCreateTaskStillRunning() != pdTRUE ) + { + xAllTasksPassed = pdFALSE; + } + + /* Also check the status flag for the tasks defined within this function. */ + if( xLocalError != pdFALSE ) + { + xAllTasksPassed = pdFAIL; + } + + return xAllTasksPassed; +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ +/* This variable is effectively set to a constant so it is made volatile to +ensure the compiler does not just get rid of it. */ +volatile portLONG lValue; + + /* Keep performing a calculation and checking the result against a constant. */ + + /* Perform the calculation. This will store partial value in + registers, resulting in a good test of the context switch mechanism. */ + lValue = intgCONST1; + lValue += intgCONST2; + lValue *= intgCONST3; + lValue /= intgCONST4; + + /* Did we perform the calculation correctly with no corruption? */ + if( lValue != intgEXPECTED_ANSWER ) + { + /* Error! */ + portENTER_CRITICAL(); + xLocalError = pdTRUE; + portEXIT_CRITICAL(); + } + + /* Yield in case cooperative scheduling is being used. */ + #if configUSE_PREEMPTION == 0 + { + taskYIELD(); + } + #endif +} +/*-----------------------------------------------------------*/ + + + diff --git a/20080212/Demo/HCS12_CodeWarrior_banked/prm/burner.bbl b/20080212/Demo/HCS12_CodeWarrior_banked/prm/burner.bbl new file mode 100644 index 000000000..639ffdef3 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_banked/prm/burner.bbl @@ -0,0 +1,223 @@ +/* logical s-record file */ +OPENFILE "%ABS_FILE%.s19" +format=motorola +busWidth=1 +origin=0 +len=0x1000000 +destination=0 +SRECORD=Sx +SENDBYTE 1 "%ABS_FILE%" +CLOSE + +/* physical s-record file */ +OPENFILE "%ABS_FILE%.phy" +format = motorola +busWidth = 1 +len = 0x4000 + +origin = 0x008000 +destination = 0x000000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x018000 +destination = 0x004000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x028000 +destination = 0x008000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x038000 +destination = 0x00C000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x048000 +destination = 0x010000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x058000 +destination = 0x014000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x068000 +destination = 0x018000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x078000 +destination = 0x01C000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x088000 +destination = 0x020000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x098000 +destination = 0x024000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x0A8000 +destination = 0x028000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x0B8000 +destination = 0x02C000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x0C8000 +destination = 0x030000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x0D8000 +destination = 0x034000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x0E8000 +destination = 0x038000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x0F8000 +destination = 0x03C000 +SENDBYTE 1 "%ABS_FILE%" + +origin = 0x108000 +destination = 0x040000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x018000 +destination = 0x044000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x128000 +destination = 0x048000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x138000 +destination = 0x04C000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x148000 +destination = 0x050000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x158000 +destination = 0x054000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x168000 +destination = 0x058000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x178000 +destination = 0x05C000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x188000 +destination = 0x060000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x198000 +destination = 0x064000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x1A8000 +destination = 0x068000 +SENDBYTE 1 "%ABS_FILE%" +origin = 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Readme.txt +//------------------------------------------------------------------------ +This project stationery is designed to get you up and running +quickly with CodeWarrior for MC9S12DP256B. +It is set up for the selected CPU and target connection, +but can be easily modified. + +Sample code for the following language(s) is at your disposal: +- C + +The wizard has prepared CodeWarrior target(s) with the connection methods of +your choice: +- Simulator: + This interface/target is prepared to use the FCS (Full Chip Simulation). + +- P&E ICD12: + This enables to debug with the P&E ICD12 target interface. + The P&E ICD12 target interface allows to debug using the + BDM connector with P&E BDM Multilink or Cable12 hardware. + The BDM Multilink and Cable12 connect to the host parallel port. + Please consult your hardware documentation for additional details. + + +Additional connections can be chosen in the simulator/debugger, +use the menu Component > Set Target. + +//------------------------------------------------------------------------ +// Processor Expert +//------------------------------------------------------------------------ +This project is prepared to be designed with Processor Expert. +The project has an additional 'tab' named 'Processor Expert' where you +can configure the CPU and its beans. +The CPU selected is inserted into the Processor Expert project panel, in +the Debug and Release configurations. +Change of the configuration is possible by the mouse double-click on it. +All the installed Embedded Beans are accessible in the Bean Selector +window, grouped into folders according to their function. The mouse +double-click on selected Embedded Bean in the Bean Selector window adds +the Bean to the project. The mouse double-click on the Bean icon in the +Project panel opens the Bean Inspector window, which is used to set the +Bean properties. Source code is generated after selecting the +(Code Design 'Project_name.mcp') menu command from the CodeWarrior main +window (Processor Expert > Code design 'Project_name.mcp'). +Use the bean methods and events to write your code in the main module +'Project_name'.c and the event module Events.c. + +For more help please read Processor Expert help: + (Processor Expert > Help > 'Topic'). + +The following folders are used in CodeWarrior project window for +ProcessorExpert: +- User modules: contains your sources. The main module 'Project_name'.c + and event module Events.c are located here after the Processor Expert + code generation. +- Prm: Linker parameter file used for linking. Note that the file used + for the linker is specified in the Linker Preference Panel. To open + the Preference Panel, please press or open the + (Edit > 'Current Build Target Name' Settings...) menu item in the + CodeWarrior main window menu, while the project window is opened). + After Processor Expert code generation 'Project_name'.prm file + will be placed here. You can switch off the .prm file generation in + Processor Expert if you want (in the CPU bean, Build Options) +- Generated code: this folder appears after the Processor Expert code + generation and contains generated code from Processor Expert. +- Doc: other files generated from the Processor Expert (documentation) + +//------------------------------------------------------------------------ +// Getting Started +//------------------------------------------------------------------------ +To build/debug your project, use the menu Project > Debug or press F5. +This will open the simulator/debugger. +Press again F5 in the debugger (or menu Run > Start/Continue) to start +the application. The menu Run > Halt or F6 stops the application. +In the debugger menu Component > Open you can load additional components. + +//------------------------------------------------------------------------ +// Project structure +//------------------------------------------------------------------------ +The project generated contains various files/folders: +- readme.txt: this file +- Sources: folder with the application source code +- Startup Code: C/C++ startup code +- Prm: + - burner.bbl file to generate S-Records +- Linker Map: the .map file generated by the linker +- Libraries: needed library files (ANSI, derivative header/implementation files) +- Debugger Project File: contains a .ini file for the debugger for each + connection +- Debugger Cmd Files: contains sub-folders for each connection with command + files + +//------------------------------------------------------------------------ +// Adding your own code +//------------------------------------------------------------------------ +Once everything is working as expected, you can begin adding your own code +to the project. Keep in mind that we provide this as an example of how to +get up and running quickly with CodeWarrior. There are certainly other +ways to handle interrupts and set up your linker command file. Feel free +to modify any of the source files provided. + +//------------------------------------------------------------------------ +// Simulator/Debugger: Additional components +//------------------------------------------------------------------------ +In the simulator/debugger, you can load additional components. Try the menu +Component > Open. + +//------------------------------------------------------------------------ +// Additional documentation +//------------------------------------------------------------------------ +Check out the online documentation provided. Use in CodeWarrior IDE the +menu Help > Online Manuals. + +//------------------------------------------------------------------------ +// Contacting Metrowerks +//------------------------------------------------------------------------ +For bug reports, technical questions, and suggestions, please use the +forms installed in the Release_Notes folder and send them to: +USA: support@metrowerks.com +EUROPE: support_europe@metrowerks.com +ASIA/PACIFIC: j-emb-sup@metrowerks.com \ No newline at end of file diff --git a/20080212/Demo/HCS12_CodeWarrior_banked/serial/serial.c b/20080212/Demo/HCS12_CodeWarrior_banked/serial/serial.c new file mode 100644 index 000000000..ce448c157 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_banked/serial/serial.c @@ -0,0 +1,187 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER for port 1. + +Note that this driver is written to test the RTOS port and is not intended +to represent an optimised solution. */ + +/* Processor Expert generated includes. */ +#include "com0.h" + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "queue.h" +#include "task.h" + +/* Demo application include files. */ +#include "serial.h" + +/* The queues used to communicate between the task code and the interrupt +service routines. */ +static xQueueHandle xRxedChars; +static xQueueHandle xCharsForTx; + +/* Interrupt identification bits. */ +#define serOVERRUN_INTERRUPT ( 0x08 ) +#define serRX_INTERRUPT ( 0x20 ) +#define serTX_INTERRUPT ( 0x80 ) + +/*-----------------------------------------------------------*/ + + +/* + * Initialise port for interrupt driven communications. + */ +xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) +{ + /* Hardware setup is performed by the Processor Expert generated code. + This function just creates the queues used to communicate between the + interrupt code and the task code - then sets the required baud rate. */ + + xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + + COM0_SetBaudRateMode( ( portCHAR ) ulWantedBaud ); + + return NULL; +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) +{ + /* Get the next character from the buffer queue. Return false if no characters + are available, or arrive before xBlockTime expires. */ + if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) + { + return pdTRUE; + } + else + { + return pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) +{ + /* Place the character in the queue of characters to be transmitted. */ + if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) + { + return pdFAIL; + } + + /* Turn on the Tx interrupt so the ISR will remove the character from the + queue and send it. This does not need to be in a critical section as + if the interrupt has already removed the character the next interrupt + will simply turn off the Tx interrupt again. */ + SCI0CR2_SCTIE = 1;; + + return pdPASS; +} +/*-----------------------------------------------------------*/ + +void vSerialClose( xComPortHandle xPort ) +{ + /* Not supported. */ + ( void ) xPort; +} +/*-----------------------------------------------------------*/ + + +/* + * Interrupt service routine for the serial port. Must be in non-banked + * memory. + */ + +#pragma CODE_SEG __NEAR_SEG NON_BANKED + +__interrupt void vCOM0_ISR( void ) +{ +volatile unsigned portCHAR ucByte, ucStatus; +portBASE_TYPE xTaskWokenByPost = pdFALSE, xTaskWokenByTx = pdFALSE; + + /* What caused the interrupt? */ + ucStatus = SCI0SR1; + + if( ucStatus & serOVERRUN_INTERRUPT ) + { + /* The interrupt was caused by an overrun. Clear the error by reading + the data register. */ + ucByte = SCI0DRL; + } + + if( ucStatus & serRX_INTERRUPT ) + { + /* The interrupt was caused by a character being received. + Read the received byte. */ + ucByte = SCI0DRL; + + /* Post the character onto the queue of received characters - noting + whether or not this wakes a task. */ + xTaskWokenByPost = xQueueSendFromISR( xRxedChars, ( void * ) &ucByte, pdFALSE ); + } + + if( ( ucStatus & serTX_INTERRUPT ) && ( SCI0CR2_SCTIE ) ) + { + /* The interrupt was caused by a character being transmitted. */ + if( xQueueReceiveFromISR( xCharsForTx, ( void * ) &ucByte, &xTaskWokenByTx ) == pdTRUE ) + { + /* Clear the SCRF bit. */ + SCI0DRL = ucByte; + } + else + { + /* Disable transmit interrupt */ + SCI0CR2_SCTIE = 0; + } + } + + if( ( xTaskWokenByPost ) || ( xTaskWokenByTx ) ) + { + portYIELD(); + } +} + +#pragma CODE_SEG DEFAULT + diff --git a/20080212/Demo/HCS12_CodeWarrior_small/CODE/ButtonInterrupt.C b/20080212/Demo/HCS12_CodeWarrior_small/CODE/ButtonInterrupt.C new file mode 100644 index 000000000..cb2e67ac5 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_small/CODE/ButtonInterrupt.C @@ -0,0 +1,117 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : ButtonInterrupt.C +** Project : RTOSDemo +** Processor : MC9S12C32CFU +** Beantype : ExtInt +** Version : Bean 02.025, Driver 01.06, CPU db: 2.87.276 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 19/05/2005, 19:02 +** Abstract : +** This bean "ExtInt" implements an external +** interrupt, its control methods and interrupt/event +** handling procedure. +** The bean uses one pin which generates interrupt on +** selected edge. +** Settings : +** Interrupt name : INT_PortP +** User handling procedure : ButtonInterrupt_OnInterrupt +** +** Used pin : +** ---------------------------------------------------- +** Number (on package) | Name +** ---------------------------------------------------- +** 4 | PP0_PWM0_KWP0 +** ---------------------------------------------------- +** +** Port name : P +** +** Bit number (in port) : 0 +** Bit mask of the port : 1 +** +** Signal edge/level : falling +** Priority : 1 +** Pull option : up +** Initial state : Disabled +** +** Edge register : PPSP [605] +** Priority register : HPRIO [31] +** Enable register : PIEP [606] +** Request register : PIFP [607] +** +** Port data register : PTP [600] +** Port control register : DDRP [602] +** Contents : +** Enable - void ButtonInterrupt_Enable(void); +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + + +/* MODULE ButtonInterrupt. */ + +#include "ButtonInterrupt.h" +/*Including shared modules, which are used for all project*/ +#include "PE_Types.h" +#include "PE_Error.h" +#include "PE_Const.h" +#include "IO_Map.h" +#include "PE_Timer.h" +#include "Events.h" +#include "Cpu.h" + +/* Definition of DATA and CODE segments for this bean. User can specify where + these segments will be located on "Build options" tab of the selected CPU bean. */ +#pragma DATA_SEG ButtonInterrupt_DATA /* Data section for this module. */ +#pragma CODE_SEG ButtonInterrupt_CODE /* Code section for this module. */ + +/* +** =================================================================== +** Method : ButtonInterrupt_Enable (bean ExtInt) +** +** Description : +** Enable the bean - the external events are accepted. +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +void ButtonInterrupt_Enable(void) +{ + PIFP = 1; /* Clear flag */ + PIEP_PIEP0 = 1; /* Enable interrupt */ +} + +/* +** =================================================================== +** Method : ButtonInterrupt_Interrupt (bean ExtInt) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */ +__interrupt void ButtonInterrupt_Interrupt(void) +{ + PIFP = 1; /* Clear flag */ + ButtonInterrupt_OnInterrupt(); +} + +#pragma CODE_SEG ButtonInterrupt_CODE /* Code section for this module. */ + +/* END ButtonInterrupt. */ + +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/20080212/Demo/HCS12_CodeWarrior_small/CODE/ButtonInterrupt.H b/20080212/Demo/HCS12_CodeWarrior_small/CODE/ButtonInterrupt.H new file mode 100644 index 000000000..c23f5160b --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_small/CODE/ButtonInterrupt.H @@ -0,0 +1,109 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : ButtonInterrupt.H +** Project : RTOSDemo +** Processor : MC9S12C32CFU +** Beantype : ExtInt +** Version : Bean 02.025, Driver 01.06, CPU db: 2.87.276 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 19/05/2005, 19:02 +** Abstract : +** This bean "ExtInt" implements an external +** interrupt, its control methods and interrupt/event +** handling procedure. +** The bean uses one pin which generates interrupt on +** selected edge. +** Settings : +** Interrupt name : INT_PortP +** User handling procedure : ButtonInterrupt_OnInterrupt +** +** Used pin : +** ---------------------------------------------------- +** Number (on package) | Name +** ---------------------------------------------------- +** 4 | PP0_PWM0_KWP0 +** ---------------------------------------------------- +** +** Port name : P +** +** Bit number (in port) : 0 +** Bit mask of the port : 1 +** +** Signal edge/level : falling +** Priority : 1 +** Pull option : up +** Initial state : Disabled +** +** Edge register : PPSP [605] +** Priority register : HPRIO [31] +** Enable register : PIEP [606] +** Request register : PIFP [607] +** +** Port data register : PTP [600] +** Port control register : DDRP [602] +** Contents : +** Enable - void ButtonInterrupt_Enable(void); +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + +#ifndef __ButtonInterrupt_H +#define __ButtonInterrupt_H + +/* MODULE ButtonInterrupt. */ + +/*Including shared modules, which are used in the whole project*/ +#include "PE_Types.h" +#include "PE_Error.h" +#include "PE_Const.h" +#include "IO_Map.h" +#include "PE_Timer.h" +#include "Events.h" +#include "Cpu.h" + +#pragma CODE_SEG ButtonInterrupt_CODE /* Code section for this module. */ + +void ButtonInterrupt_Enable(void); +/* +** =================================================================== +** Method : ButtonInterrupt_Enable (bean ExtInt) +** +** Description : +** Enable the bean - the external events are accepted. +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ + +#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */ +__interrupt void ButtonInterrupt_Interrupt(void); +#pragma CODE_SEG ButtonInterrupt_CODE /* Code section for this module. */ +/* +** =================================================================== +** Method : ButtonInterrupt_Interrupt (bean ExtInt) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ + +#pragma CODE_SEG DEFAULT /* Change code section to DEFAULT. */ + +/* END ButtonInterrupt. */ + +#endif /* __ButtonInterrupt_H*/ +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/20080212/Demo/HCS12_CodeWarrior_small/CODE/Byte1.C b/20080212/Demo/HCS12_CodeWarrior_small/CODE/Byte1.C new file mode 100644 index 000000000..5a5dc9b50 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_small/CODE/Byte1.C @@ -0,0 +1,144 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : Byte1.C +** Project : RTOSDemo +** Processor : MC9S12C32CFU +** Beantype : ByteIO +** Version : Bean 02.019, Driver 01.03, CPU db: 2.87.276 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 10/05/2005, 11:49 +** Abstract : +** This bean "ByteIO" implements an one-byte input/output. +** It uses one 8-bit port. +** Note: This bean is set to work in Output direction only. +** Methods of this bean are mostly implemented as a macros +** (if supported by target langauage and compiler). +** Settings : +** Port name : B +** +** Initial direction : Output (direction cannot be changed) +** Initial output value : 0 = 000H +** Initial pull option : off +** +** 8-bit data register : PORTB [1] +** 8-bit control register : DDRB [3] +** +** ---------------------------------------------------- +** Bit | Pin | Name +** ---------------------------------------------------- +** 0 | 16 | PB0_ADDR0_DATA0 +** 1 | 17 | PB1_ADDR1_DATA1 +** 2 | 18 | PB2_ADDR2_DATA2 +** 3 | 19 | PB3_ADDR3_DATA3 +** 4 | 20 | PB4_ADDR4_DATA4 +** 5 | 21 | PB5_ADDR5_DATA5 +** 6 | 22 | PB6_ADDR6_DATA6 +** 7 | 23 | PB7_ADDR7_DATA7 +** ---------------------------------------------------- +** Contents : +** PutBit - void Byte1_PutBit(byte Bit,bool Val); +** NegBit - void Byte1_NegBit(byte Bit); +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + + +/* MODULE Byte1. */ + +#include "Byte1.h" +/*Including shared modules, which are used for all project*/ +#include "PE_Types.h" +#include "PE_Error.h" +#include "PE_Const.h" +#include "IO_Map.h" + +#include "Cpu.h" + +/* Definition of DATA and CODE segments for this bean. User can specify where + these segments will be located on "Build options" tab of the selected CPU bean. */ +#pragma DATA_SEG Byte1_DATA /* Data section for this module. */ +#pragma CODE_SEG Byte1_CODE /* Code section for this module. */ + +/* +** =================================================================== +** Method : Byte1_GetMsk (bean ByteIO) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +byte Byte1_Table[8]={ 1, 2, 4, 8, 16, 32, 64, 128 }; /* Table of mask constants */ + +byte Byte1_GetMsk(byte Value) +{ + return((Value<8)?Byte1_Table[Value]:0); /* Return appropriate bit mask */ +} + +/* +** =================================================================== +** Method : Byte1_PutBit (bean ByteIO) +** +** Description : +** This method writes the new value to the specified bit +** of the output value. +** Parameters : +** NAME - DESCRIPTION +** Bitnum - Number of the bit (0 to 7) +** Val - New value of the bit (FALSE or TRUE) +** FALSE = "0" or "Low", TRUE = "1" or "High" +** Returns : Nothing +** =================================================================== +*/ +void Byte1_PutBit(byte BitNum, byte Value) +{ + byte Mask=Byte1_GetMsk(BitNum); /* Temporary variable - bit mask */ + + if (Mask) /* Is bit mask correct? */ + if (Value) { /* Is it one to be written? */ + PORTB |= Mask; /* Set appropriate bit on port */ + } + else { /* Is it zero to be written? */ + PORTB &= ~Mask; /* Clear appropriate bit on port */ + } +} + +/* +** =================================================================== +** Method : Byte1_NegBit (bean ByteIO) +** +** Description : +** This method negates (invertes) the specified bit of the +** output value. +** Parameters : +** NAME - DESCRIPTION +** Bit - Number of the bit to invert (0 to 7) +** Returns : Nothing +** =================================================================== +*/ +void Byte1_NegBit(byte BitNum) +{ + byte Mask=Byte1_GetMsk(BitNum); /* Temporary variable - bit mask */ + + if (Mask) { /* Is bit mask correct? */ + PORTB ^= Mask; /* Negate appropriate bit on port */ + } +} + + +/* END Byte1. */ + +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/20080212/Demo/HCS12_CodeWarrior_small/CODE/Byte1.H b/20080212/Demo/HCS12_CodeWarrior_small/CODE/Byte1.H new file mode 100644 index 000000000..c33dd528f --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_small/CODE/Byte1.H @@ -0,0 +1,110 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : Byte1.H +** Project : RTOSDemo +** Processor : MC9S12C32CFU +** Beantype : ByteIO +** Version : Bean 02.019, Driver 01.03, CPU db: 2.87.276 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 10/05/2005, 11:49 +** Abstract : +** This bean "ByteIO" implements an one-byte input/output. +** It uses one 8-bit port. +** Note: This bean is set to work in Output direction only. +** Methods of this bean are mostly implemented as a macros +** (if supported by target langauage and compiler). +** Settings : +** Port name : B +** +** Initial direction : Output (direction cannot be changed) +** Initial output value : 0 = 000H +** Initial pull option : off +** +** 8-bit data register : PORTB [1] +** 8-bit control register : DDRB [3] +** +** ---------------------------------------------------- +** Bit | Pin | Name +** ---------------------------------------------------- +** 0 | 16 | PB0_ADDR0_DATA0 +** 1 | 17 | PB1_ADDR1_DATA1 +** 2 | 18 | PB2_ADDR2_DATA2 +** 3 | 19 | PB3_ADDR3_DATA3 +** 4 | 20 | PB4_ADDR4_DATA4 +** 5 | 21 | PB5_ADDR5_DATA5 +** 6 | 22 | PB6_ADDR6_DATA6 +** 7 | 23 | PB7_ADDR7_DATA7 +** ---------------------------------------------------- +** Contents : +** PutBit - void Byte1_PutBit(byte Bit,bool Val); +** NegBit - void Byte1_NegBit(byte Bit); +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + +#ifndef __Byte1_H +#define __Byte1_H + +/* MODULE Byte1. */ + +/*Including shared modules, which are used in the whole project*/ +#include "PE_Types.h" +#include "PE_Error.h" +#include "PE_Const.h" +#include "IO_Map.h" + +#include "Cpu.h" + +#pragma CODE_SEG Byte1_CODE /* Code section for this module. */ + +/* +** =================================================================== +** Method : Byte1_PutBit (bean ByteIO) +** +** Description : +** This method writes the new value to the specified bit +** of the output value. +** Parameters : +** NAME - DESCRIPTION +** BitNum - Number of the bit (0 to 7) +** Val - New value of the bit (FALSE or TRUE) +** FALSE = "0" or "Low", TRUE = "1" or "High" +** Returns : Nothing +** =================================================================== +*/ +void Byte1_PutBit(byte BitNum, byte Value); + +/* +** =================================================================== +** Method : Byte1_NegBit (bean ByteIO) +** +** Description : +** This method negates (invertes) the specified bit of the +** output value. +** Parameters : +** NAME - DESCRIPTION +** BitNum - Number of the bit to invert (0 to 7) +** Returns : Nothing +** =================================================================== +*/ +void Byte1_NegBit(byte BitNum); + +#pragma CODE_SEG DEFAULT /* Change code section to DEFAULT. */ + +/* END Byte1. */ + +#endif /* __Byte1_H*/ +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/20080212/Demo/HCS12_CodeWarrior_small/CODE/Copy of Vectors.c b/20080212/Demo/HCS12_CodeWarrior_small/CODE/Copy of Vectors.c new file mode 100644 index 000000000..38854b315 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_small/CODE/Copy of Vectors.c @@ -0,0 +1,115 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : Cpu.C +** Project : RTOSDemo +** Processor : MC9S12C32CFU +** Beantype : MC9S12C32_80 +** Version : Bean 01.002, Driver 01.09, CPU db: 2.87.276 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 17/05/2005, 18:22 +** Abstract : +** This bean "MC9S12C32_80" implements properties, methods, +** and events of the CPU. +** Settings : +** +** Contents : +** EnableInt - void Cpu_EnableInt(void); +** DisableInt - void Cpu_DisableInt(void); +** SetWaitMode - void Cpu_SetWaitMode(void); +** SetStopMode - void Cpu_SetStopMode(void); +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + + +#include "Cpu.h" +#include "Byte1.h" +#include "TickTimer.h" +#include "ButtonInterrupt.h" + +extern void near _EntryPoint(void); /* Startup routine */ +extern void near vPortTickInterrupt( void ); +extern void near vPortYield( void ); +extern void near vButtonPush( void ); + +typedef void (*near tIsrFunc)(void); +const tIsrFunc _vect[] @0xFF80 = { /* Interrupt table */ + Cpu_Interrupt, /* 0 Default (unused) interrupt */ + Cpu_Interrupt, /* 1 Default (unused) interrupt */ + Cpu_Interrupt, /* 2 Default (unused) interrupt */ + Cpu_Interrupt, /* 3 Default (unused) interrupt */ + Cpu_Interrupt, /* 4 Default (unused) interrupt */ + Cpu_Interrupt, /* 5 Default (unused) interrupt */ + Cpu_Interrupt, /* 6 Default (unused) interrupt */ + vButtonPush, /* 7 Default (unused) interrupt */ + Cpu_Interrupt, /* 8 Default (unused) interrupt */ + Cpu_Interrupt, /* 9 Default (unused) interrupt */ + Cpu_Interrupt, /* 10 Default (unused) interrupt */ + Cpu_Interrupt, /* 11 Default (unused) interrupt */ + Cpu_Interrupt, /* 12 Default (unused) interrupt */ + Cpu_Interrupt, /* 13 Default (unused) interrupt */ + Cpu_Interrupt, /* 14 Default (unused) interrupt */ + Cpu_Interrupt, /* 15 Default (unused) interrupt */ + Cpu_Interrupt, /* 16 Default (unused) interrupt */ + Cpu_Interrupt, /* 17 Default (unused) interrupt */ + Cpu_Interrupt, /* 18 Default (unused) interrupt */ + Cpu_Interrupt, /* 19 Default (unused) interrupt */ + Cpu_Interrupt, /* 20 Default (unused) interrupt */ + Cpu_Interrupt, /* 21 Default (unused) interrupt */ + Cpu_Interrupt, /* 22 Default (unused) interrupt */ + Cpu_Interrupt, /* 23 Default (unused) interrupt */ + Cpu_Interrupt, /* 24 Default (unused) interrupt */ + Cpu_Interrupt, /* 25 Default (unused) interrupt */ + Cpu_Interrupt, /* 26 Default (unused) interrupt */ + Cpu_Interrupt, /* 27 Default (unused) interrupt */ + Cpu_Interrupt, /* 28 Default (unused) interrupt */ + Cpu_Interrupt, /* 29 Default (unused) interrupt */ + Cpu_Interrupt, /* 30 Default (unused) interrupt */ + Cpu_Interrupt, /* 31 Default (unused) interrupt */ + Cpu_Interrupt, /* 32 Default (unused) interrupt */ + Cpu_Interrupt, /* 33 Default (unused) interrupt */ + Cpu_Interrupt, /* 34 Default (unused) interrupt */ + Cpu_Interrupt, /* 35 Default (unused) interrupt */ + Cpu_Interrupt, /* 36 Default (unused) interrupt */ + Cpu_Interrupt, /* 37 Default (unused) interrupt */ + Cpu_Interrupt, /* 38 Default (unused) interrupt */ + Cpu_Interrupt, /* 39 Default (unused) interrupt */ + Cpu_Interrupt, /* 40 Default (unused) interrupt */ + Cpu_Interrupt, /* 41 Default (unused) interrupt */ + Cpu_Interrupt, /* 42 Default (unused) interrupt */ + Cpu_Interrupt, /* 43 Default (unused) interrupt */ + Cpu_Interrupt, /* 44 Default (unused) interrupt */ + Cpu_Interrupt, /* 45 Default (unused) interrupt */ + Cpu_Interrupt, /* 46 Default (unused) interrupt */ + Cpu_Interrupt, /* 47 Default (unused) interrupt */ + Cpu_Interrupt, /* 48 Default (unused) interrupt */ + Cpu_Interrupt, /* 49 Default (unused) interrupt */ + Cpu_Interrupt, /* 50 Default (unused) interrupt */ + Cpu_Interrupt, /* 51 Default (unused) interrupt */ + Cpu_Interrupt, /* 52 Default (unused) interrupt */ + Cpu_Interrupt, /* 53 Default (unused) interrupt */ + Cpu_Interrupt, /* 54 Default (unused) interrupt */ + vPortTickInterrupt, + Cpu_Interrupt, /* 56 Default (unused) interrupt */ + Cpu_Interrupt, /* 57 Default (unused) interrupt */ + Cpu_Interrupt, /* 58 Default (unused) interrupt */ + vPortYield, /* 59 Default (unused) interrupt */ + Cpu_Interrupt, /* 60 Default (unused) interrupt */ + Cpu_Interrupt, /* 61 Default (unused) interrupt */ + Cpu_Interrupt, /* 62 Default (unused) interrupt */ + _EntryPoint /* Reset vector */ + }; +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ \ No newline at end of file diff --git a/20080212/Demo/HCS12_CodeWarrior_small/CODE/Cpu.C b/20080212/Demo/HCS12_CodeWarrior_small/CODE/Cpu.C new file mode 100644 index 000000000..970d653b8 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_small/CODE/Cpu.C @@ -0,0 +1,233 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : Cpu.C +** Project : RTOSDemo +** Processor : MC9S12C32CFU +** Beantype : MC9S12C32_80 +** Version : Bean 01.002, Driver 01.09, CPU db: 2.87.276 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 18/06/2005, 18:00 +** Abstract : +** This bean "MC9S12C32_80" implements properties, methods, +** and events of the CPU. +** Settings : +** +** Contents : +** EnableInt - void Cpu_EnableInt(void); +** DisableInt - void Cpu_DisableInt(void); +** SetWaitMode - void Cpu_SetWaitMode(void); +** SetStopMode - void Cpu_SetStopMode(void); +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + +/* MODULE Cpu. */ + +#include "Byte1.h" +#include "TickTimer.h" +#include "ButtonInterrupt.h" +#include "PE_Types.h" +#include "PE_Error.h" +#include "PE_Const.h" +#include "IO_Map.h" +#include "PE_Timer.h" +#include "Events.h" +#include "Cpu.h" + +#define CGM_DELAY 3071UL + + +/* Global variables */ +volatile byte CCR_reg; /* Current CCR reegister */ +byte CpuMode = HIGH_SPEED; /* Current speed mode */ + + +/* +** =================================================================== +** Method : Cpu_Interrupt (bean MC9S12C32_80) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */ + +__interrupt void Cpu_Interrupt(void) +{ +} + +#pragma CODE_SEG DEFAULT /* Change code section to DEFAULT. */ + +/* +** =================================================================== +** Method : Cpu_DisableInt (bean MC9S12C32_80) +** +** Description : +** Disable maskable interrupts +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +/* +void Cpu_DisableInt(void) + +** This method is implemented as macro in the header module. ** +*/ + +/* +** =================================================================== +** Method : Cpu_EnableInt (bean MC9S12C32_80) +** +** Description : +** Enable maskable interrupts +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +/* +void Cpu_EnableInt(void) + +** This method is implemented as macro in the header module. ** +*/ + +/* +** =================================================================== +** Method : Cpu_SetStopMode (bean MC9S12C32_80) +** +** Description : +** Set low power mode - Stop mode. For more information +** about the stop mode see documentation of this CPU. +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +/* +void Cpu_SetStopMode(void) + +** This method is implemented as macro in the header module. ** +*/ + +/* +** =================================================================== +** Method : Cpu_SetWaitMode (bean MC9S12C32_80) +** +** Description : +** Set low power mode - Wait mode. For more information +** about the wait mode see documentation of this CPU. +** Release from Watch mode: Reset or interrupt +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +/* +void Cpu_SetWaitMode(void) + +** This method is implemented as macro in the header module. ** +*/ + +/* +** =================================================================== +** Method : _EntryPoint (bean MC9S12C32_80) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +extern void _Startup(void); /* Forward declaration of external startup function declared in file Start12.c */ +#define INITRG_ADR 0x0011 /* Register map position register */ +#pragma NO_FRAME +#pragma NO_EXIT +void _EntryPoint(void) +{ + /*** ### MC9S12C32_80 "Cpu" init code ... ***/ + /*** PE initialization code after reset ***/ + /* Initialization of the registers INITRG, INITRM, INITEE is done to protect them to be written accidentally later by the application */ + *(byte*)INITRG_ADR = 0; /* Set the register map position */ + asm nop; /* nop instruction */ + INITRM=8; /* Set the RAM map position */ + /* MISC: ??=0,??=0,??=0,??=0,EXSTR1=0,EXSTR0=0,ROMHM=0,ROMON=1 */ + MISC=1; + /* System clock initialization */ + CLKSEL=0; + CLKSEL_PLLSEL = 0; /* Select clock source from XTAL */ + PLLCTL_PLLON = 0; /* Disable the PLL */ + SYNR = 23; /* Set the multiplier register */ + REFDV = 15; /* Set the divider register */ + PLLCTL = 192; + PLLCTL_PLLON = 1; /* Enable the PLL */ + while(!CRGFLG_LOCK); /* Wait */ + CLKSEL_PLLSEL = 1; /* Select clock source from PLL */ + /*** End of PE initialization code after reset ***/ + + __asm jmp _Startup; /* Jump to C startup code */ +} + +/* +** =================================================================== +** Method : PE_low_level_init (bean MC9S12C32_80) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +void PE_low_level_init(void) +{ + /* Common initialization of the CPU registers */ +/* TSCR1: TEN=0,TSWAI=0,TSFRZ=1 */ + output( TSCR1, input( TSCR1 ) & ~192 | 32 ); +/* TCTL2: OM0=0,OL0=0 */ + output( TCTL2, input( TCTL2 ) & ~3 ); +/* TCTL1: OM7=0,OL7=0 */ + output( TCTL1, input( TCTL1 ) & ~192 ); +/* TIE: C0I=0 */ + output( TIE, input( TIE ) & ~1 ); +/* TTOV: TOV0=0 */ + output( TTOV, input( TTOV ) & ~1 ); +/* TSCR2: TOI=0,TCRE=1 */ + output( TSCR2, input( TSCR2 ) & ~128 | 8 ); +/* TIOS: IOS7=1,IOS0=1 */ + output( TIOS, input( TIOS ) | 129 ); +/* PPSP: PPSP0=0 */ + output( PPSP, input( PPSP ) & ~1 ); +/* PERP: PERP0=1 */ + output( PERP, input( PERP ) | 1 ); +/* DDRP: DDRP0=0 */ + output( DDRP, input( DDRP ) & ~1 ); +/* PWMCTL: PSWAI=0,PFRZ=0 */ + output( PWMCTL, input( PWMCTL ) & ~12 ); +/* PWMSDN: PWMIF=0,PWMIE=0,PWMRSTRT=0,PWMLVL=0,??=0,PWM7IN=0,PWM7INL=0,PWM7ENA=0 */ + output( PWMSDN, 0 ); + /* ### MC9S12C32_80 "Cpu" init code ... */ + /* ### ByteIO "Byte1" init code ... */ + PORTB = 0; /* Prepare value for output */ + DDRB = 255; /* Set direction to output */ + /* ### TimerInt "TickTimer" init code ... */ + TickTimer_Init(); + /* ### External interrupt "ButtonInterrupt" init code ... */ + PIEP_PIEP0 = 0; /* Disable interrupt */ + /* Common peripheral initialization - ENABLE */ +/* TSCR1: TEN=1 */ + output( TSCR1, input( TSCR1 ) | 128 ); + INTCR_IRQEN = 0; /* Disable the IRQ interrupt. IRQ interrupt is enabled after CPU reset by default. */ + __DI(); /* Disable interrupts */ +} + +/* END Cpu. */ + +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/20080212/Demo/HCS12_CodeWarrior_small/CODE/Cpu.H b/20080212/Demo/HCS12_CodeWarrior_small/CODE/Cpu.H new file mode 100644 index 000000000..a08230e92 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_small/CODE/Cpu.H @@ -0,0 +1,140 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : Cpu.H +** Project : RTOSDemo +** Processor : MC9S12C32CFU +** Beantype : MC9S12C32_80 +** Version : Bean 01.002, Driver 01.09, CPU db: 2.87.276 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 17/05/2005, 08:36 +** Abstract : +** This bean "MC9S12C32_80" implements properties, methods, +** and events of the CPU. +** Settings : +** +** Contents : +** EnableInt - void Cpu_EnableInt(void); +** DisableInt - void Cpu_DisableInt(void); +** SetWaitMode - void Cpu_SetWaitMode(void); +** SetStopMode - void Cpu_SetStopMode(void); +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + +#ifndef __Cpu +#define __Cpu + +/* Active configuration define symbol */ +#define PEcfg_80pin 1 + +/*Include shared modules, which are used for whole project*/ +#include "PE_Types.h" +#include "PE_Error.h" +#include "PE_Const.h" +#include "IO_Map.h" +#include "PE_Timer.h" + +/* MODULE Cpu. */ + + +/* Global variables */ +extern volatile byte CCR_reg; /* Current CCR reegister */ +extern byte CpuMode; /* Current speed mode */ + + +#define Cpu_SetStopMode() __asm("STOP") /* Set STOP mode */ +/* +** =================================================================== +** Method : Cpu_SetStopMode (bean MC9S12C32_80) +** +** Description : +** Set low power mode - Stop mode. For more information +** about the stop mode see documentation of this CPU. +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ + +#define Cpu_SetWaitMode() __asm("WAIT") /* Set WAIT mode */ +/* +** =================================================================== +** Method : Cpu_SetWaitMode (bean MC9S12C32_80) +** +** Description : +** Set low power mode - Wait mode. For more information +** about the wait mode see documentation of this CPU. +** Release from Watch mode: Reset or interrupt +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ + + + +#define Cpu_DisableInt() __DI() /* Disable interrupts */ +/* +** =================================================================== +** Method : Cpu_DisableInt (bean MC9S12C32_80) +** +** Description : +** Disable maskable interrupts +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ + +#define Cpu_EnableInt() __EI() /* Enable interrupts */ +/* +** =================================================================== +** Method : Cpu_EnableInt (bean MC9S12C32_80) +** +** Description : +** Enable maskable interrupts +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ + +#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */ + +__interrupt void Cpu_Interrupt(void); +/* +** =================================================================== +** Method : Cpu_Interrupt (bean MC9S12C32_80) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ + +#pragma CODE_SEG DEFAULT /* Change code section to DEFAULT. */ + +void PE_low_level_init(void); +/* +** =================================================================== +** Method : PE_low_level_init (bean MC9S12C32_80) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ + +/* END Cpu. */ + +#endif /* ifndef __Cpu */ +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/20080212/Demo/HCS12_CodeWarrior_small/CODE/Events.C b/20080212/Demo/HCS12_CodeWarrior_small/CODE/Events.C new file mode 100644 index 000000000..6a3f6079a --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_small/CODE/Events.C @@ -0,0 +1,87 @@ +/** ################################################################### +** Filename : Events.C +** Project : RTOSDemo +** Processor : MC9S12C32CFU +** Beantype : Events +** Version : Driver 01.01 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 17/05/2005, 08:36 +** Abstract : +** This is user's event module. +** Put your event handler code here. +** Settings : +** Contents : +** vTaskTickInterrupt - void vTaskTickInterrupt(void); +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ +/* MODULE Events */ + + +/*Including used modules for compilling procedure*/ +#include "Cpu.h" +#include "Events.h" +#include "Byte1.h" +#include "TickTimer.h" +#include "ButtonInterrupt.h" + +/*Include shared modules, which are used for whole project*/ +#include "PE_Types.h" +#include "PE_Error.h" +#include "PE_Const.h" +#include "IO_Map.h" +#include "PE_Timer.h" + +/* +** =================================================================== +** Event : vTaskTickInterrupt (module Events) +** +** From bean : TickTimer [TimerInt] +** Description : +** When a timer interrupt occurs this event is called (only +** when the bean is enabled - "Enable" and the events are +** enabled - "EnableEvent"). +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +void vTaskTickInterrupt(void) +{ + /* Write your code here ... */ +} + + +/* +** =================================================================== +** Event : ButtonInterrupt_OnInterrupt (module Events) +** +** From bean : ButtonInterrupt [ExtInt] +** Description : +** This event is called when the active signal edge/level +** occurs. +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +void ButtonInterrupt_OnInterrupt(void) +{ + /* place your ButtonInterrupt interrupt procedure body here */ +} + + +/* END Events */ + +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/20080212/Demo/HCS12_CodeWarrior_small/CODE/Events.H b/20080212/Demo/HCS12_CodeWarrior_small/CODE/Events.H new file mode 100644 index 000000000..23f2c45b4 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_small/CODE/Events.H @@ -0,0 +1,74 @@ +/** ################################################################### +** Filename : Events.H +** Project : RTOSDemo +** Processor : MC9S12C32CFU +** Beantype : Events +** Version : Driver 01.01 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 17/05/2005, 08:36 +** Abstract : +** This is user's event module. +** Put your event handler code here. +** Settings : +** Contents : +** vTaskTickInterrupt - void vTaskTickInterrupt(void); +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + +#ifndef __Events_H +#define __Events_H +/* MODULE Events */ + +#include "PE_Types.h" +#include "PE_Error.h" +#include "PE_Const.h" +#include "IO_Map.h" +#include "PE_Timer.h" + +void vTaskTickInterrupt(void); +/* +** =================================================================== +** Event : vTaskTickInterrupt (module Events) +** +** From bean : TickTimer [TimerInt] +** Description : +** When a timer interrupt occurs this event is called (only +** when the bean is enabled - "Enable" and the events are +** enabled - "EnableEvent"). +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ + + +void ButtonInterrupt_OnInterrupt(void); +/* +** =================================================================== +** Event : ButtonInterrupt_OnInterrupt (module Events) +** +** From bean : ButtonInterrupt [ExtInt] +** Description : +** This event is called when the active signal edge/level +** occurs. +** Parameters : None +** Returns : Nothing +** =================================================================== +*/ +/* END Events */ +#endif /* __Events_H*/ + +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/20080212/Demo/HCS12_CodeWarrior_small/CODE/IO_Map.C b/20080212/Demo/HCS12_CodeWarrior_small/CODE/IO_Map.C new file mode 100644 index 000000000..ad23df3b1 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_small/CODE/IO_Map.C @@ -0,0 +1,260 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : IO_Map.C +** Project : RTOSDemo +** Processor : MC9S12C32CFU +** Beantype : IO_Map +** Version : Driver 01.01 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 10/05/2005, 11:11 +** Abstract : +** This bean "IO_Map" implements an IO devices mapping. +** Settings : +** +** Contents : +** No public methods +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ +/* Based on CPU DB MC9S12C32_80, version 2.87.264 */ +#include "PE_types.h" +#include "IO_Map.h" + +volatile ARMCOPSTR _ARMCOP; /* CRG COP Timer Arm/Reset Register */ +volatile ATDDIENSTR _ATDDIEN; /* ATD Input Enable Mask Register */ +volatile ATDSTAT0STR _ATDSTAT0; /* A/D Status Register 0 */ +volatile ATDSTAT1STR _ATDSTAT1; /* A/D Status Register 1 */ +volatile BDMCCRSTR _BDMCCR; /* BDM CCR Holding Register */ +volatile BDMINRSTR _BDMINR; /* BDM Internal Register Position Register */ +volatile BDMSTSSTR _BDMSTS; /* BDM Status Register */ +volatile BKP0HSTR _BKP0H; /* First Address High Byte Breakpoint Register */ +volatile BKP0LSTR _BKP0L; /* First Address Low Byte Breakpoint Register */ +volatile BKP0XSTR _BKP0X; /* First Address Memory Expansion Breakpoint Register */ +volatile BKP1HSTR _BKP1H; /* Data (Second Address) High Byte Breakpoint Register */ +volatile BKP1LSTR _BKP1L; /* Data (Second Address) Low Byte Breakpoint Register */ +volatile BKP1XSTR _BKP1X; /* Second Address Memory Expansion Breakpoint Register */ +volatile BKPCT0STR _BKPCT0; /* Breakpoint Control Register 0 */ +volatile BKPCT1STR _BKPCT1; /* Breakpoint Control Register 1 */ +volatile CANBTR0STR _CANBTR0; /* MSCAN Bus Timing Register 0 */ +volatile CANBTR1STR _CANBTR1; /* MSCAN Bus Timing Register 1 */ +volatile CANCTL0STR _CANCTL0; /* MSCAN Control 0 Register */ +volatile CANCTL1STR _CANCTL1; /* MSCAN Control 1 Register */ +volatile CANIDACSTR _CANIDAC; /* MSCAN Identifier Acceptance Control Register */ +volatile CANIDAR0STR _CANIDAR0; /* MSCAN Identifier Acceptance Register 0 */ +volatile CANIDAR1STR _CANIDAR1; /* MSCAN Identifier Acceptance Register 1 */ +volatile CANIDAR2STR _CANIDAR2; /* MSCAN Identifier Acceptance Register 2 */ +volatile CANIDAR3STR _CANIDAR3; /* MSCAN Identifier Acceptance Register 3 */ +volatile CANIDAR4STR _CANIDAR4; /* MSCAN Identifier Acceptance Register 4 */ +volatile CANIDAR5STR _CANIDAR5; /* MSCAN Identifier Acceptance Register 5 */ +volatile CANIDAR6STR _CANIDAR6; /* MSCAN Identifier Acceptance Register 6 */ +volatile CANIDAR7STR _CANIDAR7; /* MSCAN Identifier Acceptance Register 7 */ +volatile CANIDMR0STR _CANIDMR0; /* MSCAN Identifier Mask Register 0 */ +volatile CANIDMR1STR _CANIDMR1; /* MSCAN Identifier Mask Register 1 */ +volatile CANIDMR2STR _CANIDMR2; /* MSCAN Identifier Mask Register 2 */ +volatile CANIDMR3STR _CANIDMR3; /* MSCAN Identifier Mask Register 3 */ +volatile CANIDMR4STR _CANIDMR4; /* MSCAN Identifier Mask Register 4 */ +volatile CANIDMR5STR _CANIDMR5; /* MSCAN Identifier Mask Register 5 */ +volatile CANIDMR6STR _CANIDMR6; /* MSCAN Identifier Mask Register 6 */ +volatile CANIDMR7STR _CANIDMR7; /* MSCAN Identifier Mask Register 7 */ +volatile CANRFLGSTR _CANRFLG; /* MSCAN Receiver Flag Register */ +volatile CANRIERSTR _CANRIER; /* MSCAN Receiver Interrupt Enable Register */ +volatile CANRXDLRSTR _CANRXDLR; /* MSCAN Receive Data Length Register */ +volatile CANRXDSR0STR _CANRXDSR0; /* MSCAN Receive Data Segment Register 0 */ +volatile CANRXDSR1STR _CANRXDSR1; /* MSCAN Receive Data Segment Register 1 */ +volatile CANRXDSR2STR _CANRXDSR2; /* MSCAN Receive Data Segment Register 2 */ +volatile CANRXDSR3STR _CANRXDSR3; /* MSCAN Receive Data Segment Register 3 */ +volatile CANRXDSR4STR _CANRXDSR4; /* MSCAN Receive Data Segment Register 4 */ +volatile CANRXDSR5STR _CANRXDSR5; /* MSCAN Receive Data Segment Register 5 */ +volatile CANRXDSR6STR _CANRXDSR6; /* MSCAN Receive Data Segment Register 6 */ +volatile CANRXDSR7STR _CANRXDSR7; /* MSCAN Receive Data Segment Register 7 */ +volatile CANRXERRSTR _CANRXERR; /* MSCAN Receive Error Counter Register */ +volatile CANRXIDR0STR _CANRXIDR0; /* MSCAN Receive Identifier Register 0 */ +volatile CANRXIDR1STR _CANRXIDR1; /* MSCAN Receive Identifier Register 1 */ +volatile CANRXIDR2STR _CANRXIDR2; /* MSCAN Receive Identifier Register 2 */ +volatile CANRXIDR3STR _CANRXIDR3; /* MSCAN Receive Identifier Register 3 */ +volatile CANTAAKSTR _CANTAAK; /* MSCAN Transmitter Message Abort Control */ +volatile CANTARQSTR _CANTARQ; /* MSCAN Transmitter Message Abort Request */ +volatile CANTBSELSTR _CANTBSEL; /* MSCAN Transmit Buffer Selection */ +volatile CANTFLGSTR _CANTFLG; /* MSCAN Transmitter Flag Register */ +volatile CANTIERSTR _CANTIER; /* MSCAN Transmitter Interrupt Enable Register */ +volatile CANTXDLRSTR _CANTXDLR; /* MSCAN Transmit Data Length Register */ +volatile CANTXDSR0STR _CANTXDSR0; /* MSCAN Transmit Data Segment Register 0 */ +volatile CANTXDSR1STR _CANTXDSR1; /* MSCAN Transmit Data Segment Register 1 */ +volatile CANTXDSR2STR _CANTXDSR2; /* MSCAN Transmit Data Segment Register 2 */ +volatile CANTXDSR3STR _CANTXDSR3; /* MSCAN Transmit Data Segment Register 3 */ +volatile CANTXDSR4STR _CANTXDSR4; /* MSCAN Transmit Data Segment Register 4 */ +volatile CANTXDSR5STR _CANTXDSR5; /* MSCAN Transmit Data Segment Register 5 */ +volatile CANTXDSR6STR _CANTXDSR6; /* MSCAN Transmit Data Segment Register 6 */ +volatile CANTXDSR7STR _CANTXDSR7; /* MSCAN Transmit Data Segment Register 7 */ +volatile CANTXERRSTR _CANTXERR; /* MSCAN Transmit Error Counter Register */ +volatile CANTXIDR0STR _CANTXIDR0; /* MSCAN Transmit Identifier Register 0 */ +volatile CANTXIDR1STR _CANTXIDR1; /* MSCAN Transmit Identifier Register 1 */ +volatile CANTXIDR2STR _CANTXIDR2; /* MSCAN Transmit Identifier Register 2 */ +volatile CANTXIDR3STR _CANTXIDR3; /* MSCAN Transmit Identifier Register 3 */ +volatile CANTXTBPRSTR _CANTXTBPR; /* MSCAN Transmit Buffer Priority */ +volatile CFORCSTR _CFORC; /* Timer Compare Force Register */ +volatile CLKSELSTR _CLKSEL; /* CRG Clock Select Register */ +volatile COPCTLSTR _COPCTL; /* CRG COP Control Register */ +volatile CRGFLGSTR _CRGFLG; /* CRG Flags Register */ +volatile CRGINTSTR _CRGINT; /* CRG Interrupt Enable Register */ +volatile CTCTLSTR _CTCTL; /* CRG Test Control Register */ +volatile CTFLGSTR _CTFLG; /* CRG Test Flags Register */ +volatile DDRADSTR _DDRAD; /* Port AD Data Direction Register */ +volatile DDRESTR _DDRE; /* Port E Data Direction Register */ +volatile DDRJSTR _DDRJ; /* Port J Data Direction Register */ +volatile DDRKSTR _DDRK; /* Port K Data Direction Register */ +volatile DDRMSTR _DDRM; /* Port M Data Direction Register */ +volatile DDRPSTR _DDRP; /* Port P Data Direction Register */ +volatile DDRSSTR _DDRS; /* Port S Data Direction Register */ +volatile DDRTSTR _DDRT; /* Port T Data Direction Register */ +volatile EBICTLSTR _EBICTL; /* External Bus Interface Control */ +volatile FCLKDIVSTR _FCLKDIV; /* Flash Clock Divider Register */ +volatile FCMDSTR _FCMD; /* Flash Command Buffer and Register */ +volatile FCNFGSTR _FCNFG; /* Flash Configuration Register */ +volatile FPROTSTR _FPROT; /* Flash Protection Register */ +volatile FSECSTR _FSEC; /* Flash Security Register */ +volatile FSTATSTR _FSTAT; /* Flash Status Register */ +volatile HPRIOSTR _HPRIO; /* Highest Priority I Interrupt */ +volatile INITEESTR _INITEE; /* Initialization of Internal EEPROM Position Register */ +volatile INITRGSTR _INITRG; /* Initialization of Internal Register Position Register */ +volatile INITRMSTR _INITRM; /* Initialization of Internal RAM Position Register */ +volatile INTCRSTR _INTCR; /* Interrupt Control Register */ +volatile ITCRSTR _ITCR; /* Interrupt Test Control Register */ +volatile ITESTSTR _ITEST; /* Interrupt Test Register */ +volatile MEMSIZ0STR _MEMSIZ0; /* Memory Size Register Zero */ +volatile MEMSIZ1STR _MEMSIZ1; /* Memory Size Register One */ +volatile MISCSTR _MISC; /* Miscellaneous Mapping Control Register */ +volatile MODESTR _MODE; /* Mode Register */ +volatile MODRRSTR _MODRR; /* Module Routing Register */ +volatile MTST0STR _MTST0; /* MTST0 */ +volatile MTST1STR _MTST1; /* MTST1 */ +volatile OC7DSTR _OC7D; /* Output Compare 7 Data Register */ +volatile OC7MSTR _OC7M; /* Output Compare 7 Mask Register */ +volatile PACTLSTR _PACTL; /* 16-Bit Pulse Accumulator A Control Register */ +volatile PAFLGSTR _PAFLG; /* Pulse Accumulator A Flag Register */ +volatile PARTIDHSTR _PARTIDH; /* Part ID Register High */ +volatile PARTIDLSTR _PARTIDL; /* Part ID Register Low */ +volatile PEARSTR _PEAR; /* Port E Assignment Register */ +volatile PERADSTR _PERAD; /* Port AD Pull Device Enable Register */ +volatile PERJSTR _PERJ; /* Port J Pull Device Enable Register */ +volatile PERMSTR _PERM; /* Port M Pull Device Enable Register */ +volatile PERPSTR _PERP; /* Port P Pull Device Enable Register */ +volatile PERSSTR _PERS; /* Port S Pull Device Enable Register */ +volatile PERTSTR _PERT; /* Port T Pull Device Enable Register */ +volatile PIEJSTR _PIEJ; /* Port J Interrupt Enable Register */ +volatile PIEPSTR _PIEP; /* Port P Interrupt Enable Register */ +volatile PIFJSTR _PIFJ; /* Port J Interrupt Flag Register */ +volatile PIFPSTR _PIFP; /* Port P Interrupt Flag Register */ +volatile PLLCTLSTR _PLLCTL; /* CRG PLL Control Register */ +volatile PORTAD0STR _PORTAD0; /* Port AD0 Register */ +volatile PORTESTR _PORTE; /* Port E Register */ +volatile PORTKSTR _PORTK; /* Port K Data Register */ +volatile PPAGESTR _PPAGE; /* Page Index Register */ +volatile PPSADSTR _PPSAD; /* Port AD Polarity Select Register */ +volatile PPSJSTR _PPSJ; /* PortJP Polarity Select Register */ +volatile PPSMSTR _PPSM; /* Port M Polarity Select Register */ +volatile PPSPSTR _PPSP; /* Port P Polarity Select Register */ +volatile PPSSSTR _PPSS; /* Port S Polarity Select Register */ +volatile PPSTSTR _PPST; /* Port T Polarity Select Register */ +volatile PTADSTR _PTAD; /* Port AD I/O Register */ +volatile PTIADSTR _PTIAD; /* Port AD Input Register */ +volatile PTIJSTR _PTIJ; /* Port J Input Register */ +volatile PTIMSTR _PTIM; /* Port M Input */ +volatile PTIPSTR _PTIP; /* Port P Input */ +volatile PTISSTR _PTIS; /* Port S Input */ +volatile PTITSTR _PTIT; /* Port T Input */ +volatile PTJSTR _PTJ; /* Port J I/O Register */ +volatile PTMSTR _PTM; /* Port M I/O Register */ +volatile PTPSTR _PTP; /* Port P I/O Register */ +volatile PTSSTR _PTS; /* Port S I/O Register */ +volatile PTTSTR _PTT; /* Port T I/O Register */ +volatile PUCRSTR _PUCR; /* Pull-Up Control Register */ +volatile PWMCAESTR _PWMCAE; /* PWM Center Align Enable Register */ +volatile PWMCLKSTR _PWMCLK; /* PWM Clock Select Register */ +volatile PWMCTLSTR _PWMCTL; /* PWM Control Register */ +volatile PWMESTR _PWME; /* PWM Enable Register */ +volatile PWMPOLSTR _PWMPOL; /* PWM Polarity Register */ +volatile PWMPRCLKSTR _PWMPRCLK; /* PWM Prescale Clock Select Register */ +volatile PWMSCLASTR _PWMSCLA; /* PWM Scale A Register */ +volatile PWMSCLBSTR _PWMSCLB; /* PWM Scale B Register */ +volatile PWMSDNSTR _PWMSDN; /* PWM Shutdown Register */ +volatile RDRADSTR _RDRAD; /* Port AD Reduced Drive Register */ +volatile RDRIVSTR _RDRIV; /* Reduced Drive of I/O Lines */ +volatile RDRJSTR _RDRJ; /* Port J Reduced Drive Register */ +volatile RDRMSTR _RDRM; /* Port M Reduced Drive Register */ +volatile RDRPSTR _RDRP; /* Port P Reduced Drive Register */ +volatile RDRSSTR _RDRS; /* Port S Reduced Drive Register */ +volatile RDRTSTR _RDRT; /* Port T Reduced Drive Register */ +volatile REFDVSTR _REFDV; /* CRG Reference Divider Register */ +volatile RTICTLSTR _RTICTL; /* CRG RTI Control Register */ +volatile SCICR1STR _SCICR1; /* SCI Control Register 1 */ +volatile SCICR2STR _SCICR2; /* SCI Control Register 2 */ +volatile SCIDRHSTR _SCIDRH; /* SCI Data Register High */ +volatile SCIDRLSTR _SCIDRL; /* SCI Data Register Low */ +volatile SCISR1STR _SCISR1; /* SCI Status Register 1 */ +volatile SCISR2STR _SCISR2; /* SCI Status Register 2 */ +volatile SPIBRSTR _SPIBR; /* SPI Baud Rate Register */ +volatile SPICR1STR _SPICR1; /* SPI Control Register */ +volatile SPICR2STR _SPICR2; /* SPI Control Register 2 */ +volatile SPIDRSTR _SPIDR; /* SPI Data Register */ +volatile SPISRSTR _SPISR; /* SPI Status Register */ +volatile SYNRSTR _SYNR; /* CRG Synthesizer Register */ +volatile TCTL1STR _TCTL1; /* Timer Control Register 1 */ +volatile TCTL2STR _TCTL2; /* Timer Control Register 2 */ +volatile TCTL3STR _TCTL3; /* Timer Control Register 3 */ +volatile TCTL4STR _TCTL4; /* Timer Control Register 4 */ +volatile TFLG1STR _TFLG1; /* Main Timer Interrupt Flag 1 */ +volatile TFLG2STR _TFLG2; /* Main Timer Interrupt Flag 2 */ +volatile TIESTR _TIE; /* Timer Interrupt Enable Register */ +volatile TIOSSTR _TIOS; /* Timer Input Capture/Output Compare Select */ +volatile TSCR1STR _TSCR1; /* Timer System Control Register1 */ +volatile TSCR2STR _TSCR2; /* Timer System Control Register 2 */ +volatile TTOVSTR _TTOV; /* Timer Toggle On Overflow Register */ +volatile WOMMSTR _WOMM; /* Port M Wired-Or Mode Register */ +volatile WOMSSTR _WOMS; /* Port S Wired-Or Mode Register */ +volatile ATDCTL23STR _ATDCTL23; /* ATD Control Register 23 */ +volatile ATDCTL45STR _ATDCTL45; /* ATD Control Register 45 */ +volatile ATDDR0STR _ATDDR0; /* A/D Conversion Result Register 0 */ +volatile ATDDR1STR _ATDDR1; /* A/D Conversion Result Register 1 */ +volatile ATDDR2STR _ATDDR2; /* A/D Conversion Result Register 2 */ +volatile ATDDR3STR _ATDDR3; /* A/D Conversion Result Register 3 */ +volatile ATDDR4STR _ATDDR4; /* A/D Conversion Result Register 4 */ +volatile ATDDR5STR _ATDDR5; /* A/D Conversion Result Register 5 */ +volatile ATDDR6STR _ATDDR6; /* A/D Conversion Result Register 6 */ +volatile ATDDR7STR _ATDDR7; /* A/D Conversion Result Register 7 */ +volatile DDRABSTR _DDRAB; /* Port AB Data Direction Register */ +volatile PACNTSTR _PACNT; /* Pulse Accumulators Count Register */ +volatile PORTABSTR _PORTAB; /* Port AB Register */ +volatile PWMCNT01STR _PWMCNT01; /* PWM Channel Counter 01 Register */ +volatile PWMCNT23STR _PWMCNT23; /* PWM Channel Counter 23 Register */ +volatile PWMCNT45STR _PWMCNT45; /* PWM Channel Counter 45 Register */ +volatile PWMDTY01STR _PWMDTY01; /* PWM Channel Duty 01 Register */ +volatile PWMDTY23STR _PWMDTY23; /* PWM Channel Duty 23 Register */ +volatile PWMDTY45STR _PWMDTY45; /* PWM Channel Duty 45 Register */ +volatile PWMPER01STR _PWMPER01; /* PWM Channel Period 01 Register */ +volatile PWMPER23STR _PWMPER23; /* PWM Channel Period 23 Register */ +volatile PWMPER45STR _PWMPER45; /* PWM Channel Period 45 Register */ +volatile SCIBDSTR _SCIBD; /* SCI Baud Rate Register */ +volatile TC0STR _TC0; /* Timer Input Capture/Output Compare Register 0 */ +volatile TC1STR _TC1; /* Timer Input Capture/Output Compare Register 1 */ +volatile TC2STR _TC2; /* Timer Input Capture/Output Compare Register 2 */ +volatile TC3STR _TC3; /* Timer Input Capture/Output Compare Register 3 */ +volatile TC4STR _TC4; /* Timer Input Capture/Output Compare Register 4 */ +volatile TC5STR _TC5; /* Timer Input Capture/Output Compare Register 5 */ +volatile TC6STR _TC6; /* Timer Input Capture/Output Compare Register 6 */ +volatile TC7STR _TC7; /* Timer Input Capture/Output Compare Register 7 */ +volatile TCNTSTR _TCNT; /* Timer Count Register */ +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/20080212/Demo/HCS12_CodeWarrior_small/CODE/IO_Map.H b/20080212/Demo/HCS12_CodeWarrior_small/CODE/IO_Map.H new file mode 100644 index 000000000..2ff2281a1 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_small/CODE/IO_Map.H @@ -0,0 +1,8072 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : IO_Map.H +** Project : RTOSDemo +** Processor : MC9S12C32CFU +** Beantype : IO_Map +** Version : Driver 01.01 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 10/05/2005, 11:11 +** Abstract : +** This bean "IO_Map" implements an IO devices mapping. +** Settings : +** +** Contents : +** No public methods +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + +/* Linker pragmas */ +#pragma LINK_INFO DERIVATIVE "MC9S12C32" +#pragma LINK_INFO OSCFREQUENCY "16000000" + + +#define REG_BASE 0x0000 /* Base address for the I/O register block */ + +/* Based on CPU DB MC9S12C32_80, version 2.87.264 (RegistersPrg V1.027) */ +#ifndef _MC9S12C32_80_H +#define _MC9S12C32_80_H + +#include "PE_Types.h" + +#pragma MESSAGE DISABLE C1106 /* WARNING C1106: Non-standard bitfield type */ + +/*********************************************/ +/* */ +/* PE I/O map format */ +/* */ +/*********************************************/ + +/*** PORTAB - Port AB Register; 0x00000000 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PORTA - Port A Register; 0x00000000 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Port A Bit 0 */ + byte BIT1 :1; /* Port A Bit 1 */ + byte BIT2 :1; /* Port A Bit 2 */ + byte BIT3 :1; /* Port A Bit 3 */ + byte BIT4 :1; /* Port A Bit 4 */ + byte BIT5 :1; /* Port A Bit 5 */ + byte BIT6 :1; /* Port A Bit 6 */ + byte BIT7 :1; /* Port A Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } PORTASTR; + #define PORTA _PORTAB.Overlap_STR.PORTASTR.Byte + #define PORTA_BIT0 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT0 + #define PORTA_BIT1 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT1 + #define PORTA_BIT2 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT2 + #define PORTA_BIT3 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT3 + #define PORTA_BIT4 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT4 + #define PORTA_BIT5 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT5 + #define PORTA_BIT6 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT6 + #define PORTA_BIT7 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT7 + #define PORTA_BIT _PORTAB.Overlap_STR.PORTASTR.MergedBits.grpBIT + + /*** PORTB - Port B Register; 0x00000001 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Port B Bit 0 */ + byte BIT1 :1; /* Port B Bit 1 */ + byte BIT2 :1; /* Port B Bit 2 */ + byte BIT3 :1; /* Port B Bit 3 */ + byte BIT4 :1; /* Port B Bit 4 */ + byte BIT5 :1; /* Port B Bit 5 */ + byte BIT6 :1; /* Port B Bit 6 */ + byte BIT7 :1; /* Port B Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } PORTBSTR; + #define PORTB _PORTAB.Overlap_STR.PORTBSTR.Byte + #define PORTB_BIT0 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT0 + #define PORTB_BIT1 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT1 + #define PORTB_BIT2 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT2 + #define PORTB_BIT3 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT3 + #define PORTB_BIT4 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT4 + #define PORTB_BIT5 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT5 + #define PORTB_BIT6 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT6 + #define PORTB_BIT7 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT7 + #define PORTB_BIT _PORTAB.Overlap_STR.PORTBSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word BIT0 :1; /* Port AB Bit 0 */ + word BIT1 :1; /* Port AB Bit 1 */ + word BIT2 :1; /* Port AB Bit 2 */ + word BIT3 :1; /* Port AB Bit 3 */ + word BIT4 :1; /* Port AB Bit 4 */ + word BIT5 :1; /* Port AB Bit 5 */ + word BIT6 :1; /* Port AB Bit 6 */ + word BIT7 :1; /* Port AB Bit 7 */ + word BIT8 :1; /* Port AB Bit 8 */ + word BIT9 :1; /* Port AB Bit 9 */ + word BIT10 :1; /* Port AB Bit 10 */ + word BIT11 :1; /* Port AB Bit 11 */ + word BIT12 :1; /* Port AB Bit 12 */ + word BIT13 :1; /* Port AB Bit 13 */ + word BIT14 :1; /* Port AB Bit 14 */ + word BIT15 :1; /* Port AB Bit 15 */ + } Bits; + struct { + word grpBIT :16; + } MergedBits; +} PORTABSTR; +extern volatile PORTABSTR _PORTAB @(REG_BASE + 0x00000000); +#define PORTAB _PORTAB.Word +#define PORTAB_BIT0 _PORTAB.Bits.BIT0 +#define PORTAB_BIT1 _PORTAB.Bits.BIT1 +#define PORTAB_BIT2 _PORTAB.Bits.BIT2 +#define PORTAB_BIT3 _PORTAB.Bits.BIT3 +#define PORTAB_BIT4 _PORTAB.Bits.BIT4 +#define PORTAB_BIT5 _PORTAB.Bits.BIT5 +#define PORTAB_BIT6 _PORTAB.Bits.BIT6 +#define PORTAB_BIT7 _PORTAB.Bits.BIT7 +#define PORTAB_BIT8 _PORTAB.Bits.BIT8 +#define PORTAB_BIT9 _PORTAB.Bits.BIT9 +#define PORTAB_BIT10 _PORTAB.Bits.BIT10 +#define PORTAB_BIT11 _PORTAB.Bits.BIT11 +#define PORTAB_BIT12 _PORTAB.Bits.BIT12 +#define PORTAB_BIT13 _PORTAB.Bits.BIT13 +#define PORTAB_BIT14 _PORTAB.Bits.BIT14 +#define PORTAB_BIT15 _PORTAB.Bits.BIT15 +#define PORTAB_BIT _PORTAB.MergedBits.grpBIT + + +/*** DDRAB - Port AB Data Direction Register; 0x00000002 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** DDRA - Port A Data Direction Register; 0x00000002 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Data Direction Port A Bit 0 */ + byte BIT1 :1; /* Data Direction Port A Bit 1 */ + byte BIT2 :1; /* Data Direction Port A Bit 2 */ + byte BIT3 :1; /* Data Direction Port A Bit 3 */ + byte BIT4 :1; /* Data Direction Port A Bit 4 */ + byte BIT5 :1; /* Data Direction Port A Bit 5 */ + byte BIT6 :1; /* Data Direction Port A Bit 6 */ + byte BIT7 :1; /* Data Direction Port A Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } DDRASTR; + #define DDRA _DDRAB.Overlap_STR.DDRASTR.Byte + #define DDRA_BIT0 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT0 + #define DDRA_BIT1 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT1 + #define DDRA_BIT2 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT2 + #define DDRA_BIT3 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT3 + #define DDRA_BIT4 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT4 + #define DDRA_BIT5 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT5 + #define DDRA_BIT6 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT6 + #define DDRA_BIT7 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT7 + #define DDRA_BIT _DDRAB.Overlap_STR.DDRASTR.MergedBits.grpBIT + + /*** DDRB - Port B Data Direction Register; 0x00000003 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Data Direction Port B Bit 0 */ + byte BIT1 :1; /* Data Direction Port B Bit 1 */ + byte BIT2 :1; /* Data Direction Port B Bit 2 */ + byte BIT3 :1; /* Data Direction Port B Bit 3 */ + byte BIT4 :1; /* Data Direction Port B Bit 4 */ + byte BIT5 :1; /* Data Direction Port B Bit 5 */ + byte BIT6 :1; /* Data Direction Port B Bit 6 */ + byte BIT7 :1; /* Data Direction Port B Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } DDRBSTR; + #define DDRB _DDRAB.Overlap_STR.DDRBSTR.Byte + #define DDRB_BIT0 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT0 + #define DDRB_BIT1 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT1 + #define DDRB_BIT2 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT2 + #define DDRB_BIT3 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT3 + #define DDRB_BIT4 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT4 + #define DDRB_BIT5 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT5 + #define DDRB_BIT6 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT6 + #define DDRB_BIT7 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT7 + #define DDRB_BIT _DDRAB.Overlap_STR.DDRBSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word BIT0 :1; /* Data Direction Port B Bit 0 */ + word BIT1 :1; /* Data Direction Port B Bit 1 */ + word BIT2 :1; /* Data Direction Port B Bit 2 */ + word BIT3 :1; /* Data Direction Port B Bit 3 */ + word BIT4 :1; /* Data Direction Port B Bit 4 */ + word BIT5 :1; /* Data Direction Port B Bit 5 */ + word BIT6 :1; /* Data Direction Port B Bit 6 */ + word BIT7 :1; /* Data Direction Port B Bit 7 */ + word BIT8 :1; /* Data Direction Port A Bit 8 */ + word BIT9 :1; /* Data Direction Port A Bit 9 */ + word BIT10 :1; /* Data Direction Port A Bit 10 */ + word BIT11 :1; /* Data Direction Port A Bit 11 */ + word BIT12 :1; /* Data Direction Port A Bit 12 */ + word BIT13 :1; /* Data Direction Port A Bit 13 */ + word BIT14 :1; /* Data Direction Port A Bit 14 */ + word BIT15 :1; /* Data Direction Port A Bit 15 */ + } Bits; + struct { + word grpBIT :16; + } MergedBits; +} DDRABSTR; +extern volatile DDRABSTR _DDRAB @(REG_BASE + 0x00000002); +#define DDRAB _DDRAB.Word +#define DDRAB_BIT0 _DDRAB.Bits.BIT0 +#define DDRAB_BIT1 _DDRAB.Bits.BIT1 +#define DDRAB_BIT2 _DDRAB.Bits.BIT2 +#define DDRAB_BIT3 _DDRAB.Bits.BIT3 +#define DDRAB_BIT4 _DDRAB.Bits.BIT4 +#define DDRAB_BIT5 _DDRAB.Bits.BIT5 +#define DDRAB_BIT6 _DDRAB.Bits.BIT6 +#define DDRAB_BIT7 _DDRAB.Bits.BIT7 +#define DDRAB_BIT8 _DDRAB.Bits.BIT8 +#define DDRAB_BIT9 _DDRAB.Bits.BIT9 +#define DDRAB_BIT10 _DDRAB.Bits.BIT10 +#define DDRAB_BIT11 _DDRAB.Bits.BIT11 +#define DDRAB_BIT12 _DDRAB.Bits.BIT12 +#define DDRAB_BIT13 _DDRAB.Bits.BIT13 +#define DDRAB_BIT14 _DDRAB.Bits.BIT14 +#define DDRAB_BIT15 _DDRAB.Bits.BIT15 +#define DDRAB_BIT _DDRAB.MergedBits.grpBIT + + +/*** TCNT - Timer Count Register; 0x00000044 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TCNTHi - Timer Count Register High; 0x00000044 ***/ + union { + byte Byte; + struct { + byte BIT15 :1; /* Timer Count Register Bit 15 */ + byte BIT14 :1; /* Timer Count Register Bit 14 */ + byte BIT13 :1; /* Timer Count Register Bit 13 */ + byte BIT12 :1; /* Timer Count Register Bit 12 */ + byte BIT11 :1; /* Timer Count Register Bit 11 */ + byte BIT10 :1; /* Timer Count Register Bit 10 */ + byte BIT9 :1; /* Timer Count Register Bit 9 */ + byte BIT8 :1; /* Timer Count Register Bit 8 */ + } Bits; + } TCNTHiSTR; + #define TCNTHi _TCNT.Overlap_STR.TCNTHiSTR.Byte + #define TCNTHi_BIT15 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT15 + #define TCNTHi_BIT14 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT14 + #define TCNTHi_BIT13 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT13 + #define TCNTHi_BIT12 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT12 + #define TCNTHi_BIT11 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT11 + #define TCNTHi_BIT10 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT10 + #define TCNTHi_BIT9 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT9 + #define TCNTHi_BIT8 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT8 + + /*** TCNTLo - Timer Count Register Low; 0x00000045 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Count Register Bit 0 */ + byte BIT1 :1; /* Timer Count Register Bit 1 */ + byte BIT2 :1; /* Timer Count Register Bit 2 */ + byte BIT3 :1; /* Timer Count Register Bit 3 */ + byte BIT4 :1; /* Timer Count Bit Register 4 */ + byte BIT5 :1; /* Timer Count Bit Register 5 */ + byte BIT6 :1; /* Timer Count Bit Register 6 */ + byte BIT7 :1; /* Timer Count Bit Register 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } TCNTLoSTR; + #define TCNTLo _TCNT.Overlap_STR.TCNTLoSTR.Byte + #define TCNTLo_BIT0 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT0 + #define TCNTLo_BIT1 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT1 + #define TCNTLo_BIT2 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT2 + #define TCNTLo_BIT3 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT3 + #define TCNTLo_BIT4 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT4 + #define TCNTLo_BIT5 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT5 + #define TCNTLo_BIT6 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT6 + #define TCNTLo_BIT7 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT7 + #define TCNTLo_BIT _TCNT.Overlap_STR.TCNTLoSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} TCNTSTR; +extern volatile TCNTSTR _TCNT @(REG_BASE + 0x00000044); +#define TCNT _TCNT.Word +#define TCNT_BIT _TCNT.MergedBits.grpBIT + + +/*** TC0 - Timer Input Capture/Output Compare Register 0; 0x00000050 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC0Hi - Timer Input Capture/Output Compare Register 0 High; 0x00000050 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Timer Input Capture/Output Compare Register 0 Bit 8 */ + byte BIT9 :1; /* Timer Input Capture/Output Compare Register 0 Bit 9 */ + byte BIT10 :1; /* Timer Input Capture/Output Compare Register 0 Bit 10 */ + byte BIT11 :1; /* Timer Input Capture/Output Compare Register 0 Bit 11 */ + byte BIT12 :1; /* Timer Input Capture/Output Compare Register 0 Bit 12 */ + byte BIT13 :1; /* Timer Input Capture/Output Compare Register 0 Bit 13 */ + byte BIT14 :1; /* Timer Input Capture/Output Compare Register 0 Bit 14 */ + byte BIT15 :1; /* Timer Input Capture/Output Compare Register 0 Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } TC0HiSTR; + #define TC0Hi _TC0.Overlap_STR.TC0HiSTR.Byte + #define TC0Hi_BIT8 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT8 + #define TC0Hi_BIT9 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT9 + #define TC0Hi_BIT10 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT10 + #define TC0Hi_BIT11 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT11 + #define TC0Hi_BIT12 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT12 + #define TC0Hi_BIT13 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT13 + #define TC0Hi_BIT14 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT14 + #define TC0Hi_BIT15 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT15 + #define TC0Hi_BIT_8 _TC0.Overlap_STR.TC0HiSTR.MergedBits.grpBIT_8 + #define TC0Hi_BIT TC0Hi_BIT_8 + + /*** TC0Lo - Timer Input Capture/Output Compare Register 0 Low; 0x00000051 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Input Capture/Output Compare Register 0 Bit 0 */ + byte BIT1 :1; /* Timer Input Capture/Output Compare Register 0 Bit 1 */ + byte BIT2 :1; /* Timer Input Capture/Output Compare Register 0 Bit 2 */ + byte BIT3 :1; /* Timer Input Capture/Output Compare Register 0 Bit 3 */ + byte BIT4 :1; /* Timer Input Capture/Output Compare Register 0 Bit 4 */ + byte BIT5 :1; /* Timer Input Capture/Output Compare Register 0 Bit 5 */ + byte BIT6 :1; /* Timer Input Capture/Output Compare Register 0 Bit 6 */ + byte BIT7 :1; /* Timer Input Capture/Output Compare Register 0 Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } TC0LoSTR; + #define TC0Lo _TC0.Overlap_STR.TC0LoSTR.Byte + #define TC0Lo_BIT0 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT0 + #define TC0Lo_BIT1 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT1 + #define TC0Lo_BIT2 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT2 + #define TC0Lo_BIT3 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT3 + #define TC0Lo_BIT4 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT4 + #define TC0Lo_BIT5 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT5 + #define TC0Lo_BIT6 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT6 + #define TC0Lo_BIT7 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT7 + #define TC0Lo_BIT _TC0.Overlap_STR.TC0LoSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} TC0STR; +extern volatile TC0STR _TC0 @(REG_BASE + 0x00000050); +#define TC0 _TC0.Word +#define TC0_BIT _TC0.MergedBits.grpBIT + + +/*** TC1 - Timer Input Capture/Output Compare Register 1; 0x00000052 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC1Hi - Timer Input Capture/Output Compare Register 1 High; 0x00000052 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Timer Input Capture/Output Compare Register 1 Bit 8 */ + byte BIT9 :1; /* Timer Input Capture/Output Compare Register 1 Bit 9 */ + byte BIT10 :1; /* Timer Input Capture/Output Compare Register 1 Bit 10 */ + byte BIT11 :1; /* Timer Input Capture/Output Compare Register 1 Bit 11 */ + byte BIT12 :1; /* Timer Input Capture/Output Compare Register 1 Bit 12 */ + byte BIT13 :1; /* Timer Input Capture/Output Compare Register 1 Bit 13 */ + byte BIT14 :1; /* Timer Input Capture/Output Compare Register 1 Bit 14 */ + byte BIT15 :1; /* Timer Input Capture/Output Compare Register 1 Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } TC1HiSTR; + #define TC1Hi _TC1.Overlap_STR.TC1HiSTR.Byte + #define TC1Hi_BIT8 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT8 + #define TC1Hi_BIT9 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT9 + #define TC1Hi_BIT10 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT10 + #define TC1Hi_BIT11 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT11 + #define TC1Hi_BIT12 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT12 + #define TC1Hi_BIT13 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT13 + #define TC1Hi_BIT14 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT14 + #define TC1Hi_BIT15 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT15 + #define TC1Hi_BIT_8 _TC1.Overlap_STR.TC1HiSTR.MergedBits.grpBIT_8 + #define TC1Hi_BIT TC1Hi_BIT_8 + + /*** TC1Lo - Timer Input Capture/Output Compare Register 1 Low; 0x00000053 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Input Capture/Output Compare Register 1 Bit 0 */ + byte BIT1 :1; /* Timer Input Capture/Output Compare Register 1 Bit 1 */ + byte BIT2 :1; /* Timer Input Capture/Output Compare Register 1 Bit 2 */ + byte BIT3 :1; /* Timer Input Capture/Output Compare Register 1 Bit 3 */ + byte BIT4 :1; /* Timer Input Capture/Output Compare Register 1 Bit 4 */ + byte BIT5 :1; /* Timer Input Capture/Output Compare Register 1 Bit 5 */ + byte BIT6 :1; /* Timer Input Capture/Output Compare Register 1 Bit 6 */ + byte BIT7 :1; /* Timer Input Capture/Output Compare Register 1 Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } TC1LoSTR; + #define TC1Lo _TC1.Overlap_STR.TC1LoSTR.Byte + #define TC1Lo_BIT0 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT0 + #define TC1Lo_BIT1 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT1 + #define TC1Lo_BIT2 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT2 + #define TC1Lo_BIT3 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT3 + #define TC1Lo_BIT4 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT4 + #define TC1Lo_BIT5 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT5 + #define TC1Lo_BIT6 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT6 + #define TC1Lo_BIT7 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT7 + #define TC1Lo_BIT _TC1.Overlap_STR.TC1LoSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} TC1STR; +extern volatile TC1STR _TC1 @(REG_BASE + 0x00000052); +#define TC1 _TC1.Word +#define TC1_BIT _TC1.MergedBits.grpBIT + + +/*** TC2 - Timer Input Capture/Output Compare Register 2; 0x00000054 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC2Hi - Timer Input Capture/Output Compare Register 2 High; 0x00000054 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Timer Input Capture/Output Compare Register 2 Bit 8 */ + byte BIT9 :1; /* Timer Input Capture/Output Compare Register 2 Bit 9 */ + byte BIT10 :1; /* Timer Input Capture/Output Compare Register 2 Bit 10 */ + byte BIT11 :1; /* Timer Input Capture/Output Compare Register 2 Bit 11 */ + byte BIT12 :1; /* Timer Input Capture/Output Compare Register 2 Bit 12 */ + byte BIT13 :1; /* Timer Input Capture/Output Compare Register 2 Bit 13 */ + byte BIT14 :1; /* Timer Input Capture/Output Compare Register 2 Bit 14 */ + byte BIT15 :1; /* Timer Input Capture/Output Compare Register 2 Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } TC2HiSTR; + #define TC2Hi _TC2.Overlap_STR.TC2HiSTR.Byte + #define TC2Hi_BIT8 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT8 + #define TC2Hi_BIT9 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT9 + #define TC2Hi_BIT10 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT10 + #define TC2Hi_BIT11 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT11 + #define TC2Hi_BIT12 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT12 + #define TC2Hi_BIT13 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT13 + #define TC2Hi_BIT14 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT14 + #define TC2Hi_BIT15 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT15 + #define TC2Hi_BIT_8 _TC2.Overlap_STR.TC2HiSTR.MergedBits.grpBIT_8 + #define TC2Hi_BIT TC2Hi_BIT_8 + + /*** TC2Lo - Timer Input Capture/Output Compare Register 2 Low; 0x00000055 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Input Capture/Output Compare Register 2 Bit 0 */ + byte BIT1 :1; /* Timer Input Capture/Output Compare Register 2 Bit 1 */ + byte BIT2 :1; /* Timer Input Capture/Output Compare Register 2 Bit 2 */ + byte BIT3 :1; /* Timer Input Capture/Output Compare Register 2 Bit 3 */ + byte BIT4 :1; /* Timer Input Capture/Output Compare Register 2 Bit 4 */ + byte BIT5 :1; /* Timer Input Capture/Output Compare Register 2 Bit 5 */ + byte BIT6 :1; /* Timer Input Capture/Output Compare Register 2 Bit 6 */ + byte BIT7 :1; /* Timer Input Capture/Output Compare Register 2 Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } TC2LoSTR; + #define TC2Lo _TC2.Overlap_STR.TC2LoSTR.Byte + #define TC2Lo_BIT0 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT0 + #define TC2Lo_BIT1 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT1 + #define TC2Lo_BIT2 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT2 + #define TC2Lo_BIT3 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT3 + #define TC2Lo_BIT4 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT4 + #define TC2Lo_BIT5 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT5 + #define TC2Lo_BIT6 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT6 + #define TC2Lo_BIT7 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT7 + #define TC2Lo_BIT _TC2.Overlap_STR.TC2LoSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} TC2STR; +extern volatile TC2STR _TC2 @(REG_BASE + 0x00000054); +#define TC2 _TC2.Word +#define TC2_BIT _TC2.MergedBits.grpBIT + + +/*** TC3 - Timer Input Capture/Output Compare Register 3; 0x00000056 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC3Hi - Timer Input Capture/Output Compare Register 3 High; 0x00000056 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Timer Input Capture/Output Compare Register 3 Bit 8 */ + byte BIT9 :1; /* Timer Input Capture/Output Compare Register 3 Bit 9 */ + byte BIT10 :1; /* Timer Input Capture/Output Compare Register 3 Bit 10 */ + byte BIT11 :1; /* Timer Input Capture/Output Compare Register 3 Bit 11 */ + byte BIT12 :1; /* Timer Input Capture/Output Compare Register 3 Bit 12 */ + byte BIT13 :1; /* Timer Input Capture/Output Compare Register 3 Bit 13 */ + byte BIT14 :1; /* Timer Input Capture/Output Compare Register 3 Bit 14 */ + byte BIT15 :1; /* Timer Input Capture/Output Compare Register 3 Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } TC3HiSTR; + #define TC3Hi _TC3.Overlap_STR.TC3HiSTR.Byte + #define TC3Hi_BIT8 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT8 + #define TC3Hi_BIT9 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT9 + #define TC3Hi_BIT10 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT10 + #define TC3Hi_BIT11 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT11 + #define TC3Hi_BIT12 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT12 + #define TC3Hi_BIT13 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT13 + #define TC3Hi_BIT14 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT14 + #define TC3Hi_BIT15 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT15 + #define TC3Hi_BIT_8 _TC3.Overlap_STR.TC3HiSTR.MergedBits.grpBIT_8 + #define TC3Hi_BIT TC3Hi_BIT_8 + + /*** TC3Lo - Timer Input Capture/Output Compare Register 3 Low; 0x00000057 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Input Capture/Output Compare Register 3 Bit 0 */ + byte BIT1 :1; /* Timer Input Capture/Output Compare Register 3 Bit 1 */ + byte BIT2 :1; /* Timer Input Capture/Output Compare Register 3 Bit 2 */ + byte BIT3 :1; /* Timer Input Capture/Output Compare Register 3 Bit 3 */ + byte BIT4 :1; /* Timer Input Capture/Output Compare Register 3 Bit 4 */ + byte BIT5 :1; /* Timer Input Capture/Output Compare Register 3 Bit 5 */ + byte BIT6 :1; /* Timer Input Capture/Output Compare Register 3 Bit 6 */ + byte BIT7 :1; /* Timer Input Capture/Output Compare Register 3 Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } TC3LoSTR; + #define TC3Lo _TC3.Overlap_STR.TC3LoSTR.Byte + #define TC3Lo_BIT0 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT0 + #define TC3Lo_BIT1 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT1 + #define TC3Lo_BIT2 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT2 + #define TC3Lo_BIT3 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT3 + #define TC3Lo_BIT4 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT4 + #define TC3Lo_BIT5 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT5 + #define TC3Lo_BIT6 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT6 + #define TC3Lo_BIT7 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT7 + #define TC3Lo_BIT _TC3.Overlap_STR.TC3LoSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} TC3STR; +extern volatile TC3STR _TC3 @(REG_BASE + 0x00000056); +#define TC3 _TC3.Word +#define TC3_BIT _TC3.MergedBits.grpBIT + + +/*** TC4 - Timer Input Capture/Output Compare Register 4; 0x00000058 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC4Hi - Timer Input Capture/Output Compare Register 4 High; 0x00000058 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Timer Input Capture/Output Compare Register 4 Bit 8 */ + byte BIT9 :1; /* Timer Input Capture/Output Compare Register 4 Bit 9 */ + byte BIT10 :1; /* Timer Input Capture/Output Compare Register 4 Bit 10 */ + byte BIT11 :1; /* Timer Input Capture/Output Compare Register 4 Bit 11 */ + byte BIT12 :1; /* Timer Input Capture/Output Compare Register 4 Bit 12 */ + byte BIT13 :1; /* Timer Input Capture/Output Compare Register 4 Bit 13 */ + byte BIT14 :1; /* Timer Input Capture/Output Compare Register 4 Bit 14 */ + byte BIT15 :1; /* Timer Input Capture/Output Compare Register 4 Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } TC4HiSTR; + #define TC4Hi _TC4.Overlap_STR.TC4HiSTR.Byte + #define TC4Hi_BIT8 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT8 + #define TC4Hi_BIT9 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT9 + #define TC4Hi_BIT10 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT10 + #define TC4Hi_BIT11 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT11 + #define TC4Hi_BIT12 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT12 + #define TC4Hi_BIT13 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT13 + #define TC4Hi_BIT14 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT14 + #define TC4Hi_BIT15 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT15 + #define TC4Hi_BIT_8 _TC4.Overlap_STR.TC4HiSTR.MergedBits.grpBIT_8 + #define TC4Hi_BIT TC4Hi_BIT_8 + + /*** TC4Lo - Timer Input Capture/Output Compare Register 4 Low; 0x00000059 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Input Capture/Output Compare Register 4 Bit 0 */ + byte BIT1 :1; /* Timer Input Capture/Output Compare Register 4 Bit 1 */ + byte BIT2 :1; /* Timer Input Capture/Output Compare Register 4 Bit 2 */ + byte BIT3 :1; /* Timer Input Capture/Output Compare Register 4 Bit 3 */ + byte BIT4 :1; /* Timer Input Capture/Output Compare Register 4 Bit 4 */ + byte BIT5 :1; /* Timer Input Capture/Output Compare Register 4 Bit 5 */ + byte BIT6 :1; /* Timer Input Capture/Output Compare Register 4 Bit 6 */ + byte BIT7 :1; /* Timer Input Capture/Output Compare Register 4 Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } TC4LoSTR; + #define TC4Lo _TC4.Overlap_STR.TC4LoSTR.Byte + #define TC4Lo_BIT0 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT0 + #define TC4Lo_BIT1 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT1 + #define TC4Lo_BIT2 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT2 + #define TC4Lo_BIT3 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT3 + #define TC4Lo_BIT4 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT4 + #define TC4Lo_BIT5 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT5 + #define TC4Lo_BIT6 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT6 + #define TC4Lo_BIT7 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT7 + #define TC4Lo_BIT _TC4.Overlap_STR.TC4LoSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} TC4STR; +extern volatile TC4STR _TC4 @(REG_BASE + 0x00000058); +#define TC4 _TC4.Word +#define TC4_BIT _TC4.MergedBits.grpBIT + + +/*** TC5 - Timer Input Capture/Output Compare Register 5; 0x0000005A ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC5Hi - Timer Input Capture/Output Compare Register 5 High; 0x0000005A ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Timer Input Capture/Output Compare Register 5 Bit 8 */ + byte BIT9 :1; /* Timer Input Capture/Output Compare Register 5 Bit 9 */ + byte BIT10 :1; /* Timer Input Capture/Output Compare Register 5 Bit 10 */ + byte BIT11 :1; /* Timer Input Capture/Output Compare Register 5 Bit 11 */ + byte BIT12 :1; /* Timer Input Capture/Output Compare Register 5 Bit 12 */ + byte BIT13 :1; /* Timer Input Capture/Output Compare Register 5 Bit 13 */ + byte BIT14 :1; /* Timer Input Capture/Output Compare Register 5 Bit 14 */ + byte BIT15 :1; /* Timer Input Capture/Output Compare Register 5 Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } TC5HiSTR; + #define TC5Hi _TC5.Overlap_STR.TC5HiSTR.Byte + #define TC5Hi_BIT8 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT8 + #define TC5Hi_BIT9 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT9 + #define TC5Hi_BIT10 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT10 + #define TC5Hi_BIT11 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT11 + #define TC5Hi_BIT12 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT12 + #define TC5Hi_BIT13 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT13 + #define TC5Hi_BIT14 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT14 + #define TC5Hi_BIT15 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT15 + #define TC5Hi_BIT_8 _TC5.Overlap_STR.TC5HiSTR.MergedBits.grpBIT_8 + #define TC5Hi_BIT TC5Hi_BIT_8 + + /*** TC5Lo - Timer Input Capture/Output Compare Register 5 Low; 0x0000005B ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Input Capture/Output Compare Register 5 Bit 0 */ + byte BIT1 :1; /* Timer Input Capture/Output Compare Register 5 Bit 1 */ + byte BIT2 :1; /* Timer Input Capture/Output Compare Register 5 Bit 2 */ + byte BIT3 :1; /* Timer Input Capture/Output Compare Register 5 Bit 3 */ + byte BIT4 :1; /* Timer Input Capture/Output Compare Register 5 Bit 4 */ + byte BIT5 :1; /* Timer Input Capture/Output Compare Register 5 Bit 5 */ + byte BIT6 :1; /* Timer Input Capture/Output Compare Register 5 Bit 6 */ + byte BIT7 :1; /* Timer Input Capture/Output Compare Register 5 Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } TC5LoSTR; + #define TC5Lo _TC5.Overlap_STR.TC5LoSTR.Byte + #define TC5Lo_BIT0 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT0 + #define TC5Lo_BIT1 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT1 + #define TC5Lo_BIT2 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT2 + #define TC5Lo_BIT3 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT3 + #define TC5Lo_BIT4 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT4 + #define TC5Lo_BIT5 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT5 + #define TC5Lo_BIT6 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT6 + #define TC5Lo_BIT7 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT7 + #define TC5Lo_BIT _TC5.Overlap_STR.TC5LoSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} TC5STR; +extern volatile TC5STR _TC5 @(REG_BASE + 0x0000005A); +#define TC5 _TC5.Word +#define TC5_BIT _TC5.MergedBits.grpBIT + + +/*** TC6 - Timer Input Capture/Output Compare Register 6; 0x0000005C ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC6Hi - Timer Input Capture/Output Compare Register 6 High; 0x0000005C ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Timer Input Capture/Output Compare Register 6 Bit 8 */ + byte BIT9 :1; /* Timer Input Capture/Output Compare Register 6 Bit 9 */ + byte BIT10 :1; /* Timer Input Capture/Output Compare Register 6 Bit 10 */ + byte BIT11 :1; /* Timer Input Capture/Output Compare Register 6 Bit 11 */ + byte BIT12 :1; /* Timer Input Capture/Output Compare Register 6 Bit 12 */ + byte BIT13 :1; /* Timer Input Capture/Output Compare Register 6 Bit 13 */ + byte BIT14 :1; /* Timer Input Capture/Output Compare Register 6 Bit 14 */ + byte BIT15 :1; /* Timer Input Capture/Output Compare Register 6 Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } TC6HiSTR; + #define TC6Hi _TC6.Overlap_STR.TC6HiSTR.Byte + #define TC6Hi_BIT8 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT8 + #define TC6Hi_BIT9 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT9 + #define TC6Hi_BIT10 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT10 + #define TC6Hi_BIT11 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT11 + #define TC6Hi_BIT12 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT12 + #define TC6Hi_BIT13 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT13 + #define TC6Hi_BIT14 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT14 + #define TC6Hi_BIT15 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT15 + #define TC6Hi_BIT_8 _TC6.Overlap_STR.TC6HiSTR.MergedBits.grpBIT_8 + #define TC6Hi_BIT TC6Hi_BIT_8 + + /*** TC6Lo - Timer Input Capture/Output Compare Register 6 Low; 0x0000005D ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Input Capture/Output Compare Register 6 Bit 0 */ + byte BIT1 :1; /* Timer Input Capture/Output Compare Register 6 Bit 1 */ + byte BIT2 :1; /* Timer Input Capture/Output Compare Register 6 Bit 2 */ + byte BIT3 :1; /* Timer Input Capture/Output Compare Register 6 Bit 3 */ + byte BIT4 :1; /* Timer Input Capture/Output Compare Register 6 Bit 4 */ + byte BIT5 :1; /* Timer Input Capture/Output Compare Register 6 Bit 5 */ + byte BIT6 :1; /* Timer Input Capture/Output Compare Register 6 Bit 6 */ + byte BIT7 :1; /* Timer Input Capture/Output Compare Register 6 Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } TC6LoSTR; + #define TC6Lo _TC6.Overlap_STR.TC6LoSTR.Byte + #define TC6Lo_BIT0 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT0 + #define TC6Lo_BIT1 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT1 + #define TC6Lo_BIT2 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT2 + #define TC6Lo_BIT3 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT3 + #define TC6Lo_BIT4 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT4 + #define TC6Lo_BIT5 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT5 + #define TC6Lo_BIT6 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT6 + #define TC6Lo_BIT7 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT7 + #define TC6Lo_BIT _TC6.Overlap_STR.TC6LoSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} TC6STR; +extern volatile TC6STR _TC6 @(REG_BASE + 0x0000005C); +#define TC6 _TC6.Word +#define TC6_BIT _TC6.MergedBits.grpBIT + + +/*** TC7 - Timer Input Capture/Output Compare Register 7; 0x0000005E ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC7Hi - Timer Input Capture/Output Compare Register 7 High; 0x0000005E ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Timer Input Capture/Output Compare Register 7 Bit 8 */ + byte BIT9 :1; /* Timer Input Capture/Output Compare Register 7 Bit 9 */ + byte BIT10 :1; /* Timer Input Capture/Output Compare Register 7 Bit 10 */ + byte BIT11 :1; /* Timer Input Capture/Output Compare Register 7 Bit 11 */ + byte BIT12 :1; /* Timer Input Capture/Output Compare Register 7 Bit 12 */ + byte BIT13 :1; /* Timer Input Capture/Output Compare Register 7 Bit 13 */ + byte BIT14 :1; /* Timer Input Capture/Output Compare Register 7 Bit 14 */ + byte BIT15 :1; /* Timer Input Capture/Output Compare Register 7 Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } TC7HiSTR; + #define TC7Hi _TC7.Overlap_STR.TC7HiSTR.Byte + #define TC7Hi_BIT8 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT8 + #define TC7Hi_BIT9 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT9 + #define TC7Hi_BIT10 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT10 + #define TC7Hi_BIT11 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT11 + #define TC7Hi_BIT12 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT12 + #define TC7Hi_BIT13 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT13 + #define TC7Hi_BIT14 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT14 + #define TC7Hi_BIT15 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT15 + #define TC7Hi_BIT_8 _TC7.Overlap_STR.TC7HiSTR.MergedBits.grpBIT_8 + #define TC7Hi_BIT TC7Hi_BIT_8 + + /*** TC7Lo - Timer Input Capture/Output Compare Register 7 Low; 0x0000005F ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Input Capture/Output Compare Register 7 Bit 0 */ + byte BIT1 :1; /* Timer Input Capture/Output Compare Register 7 Bit 1 */ + byte BIT2 :1; /* Timer Input Capture/Output Compare Register 7 Bit 2 */ + byte BIT3 :1; /* Timer Input Capture/Output Compare Register 7 Bit 3 */ + byte BIT4 :1; /* Timer Input Capture/Output Compare Register 7 Bit 4 */ + byte BIT5 :1; /* Timer Input Capture/Output Compare Register 7 Bit 5 */ + byte BIT6 :1; /* Timer Input Capture/Output Compare Register 7 Bit 6 */ + byte BIT7 :1; /* Timer Input Capture/Output Compare Register 7 Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; + } TC7LoSTR; + #define TC7Lo _TC7.Overlap_STR.TC7LoSTR.Byte + #define TC7Lo_BIT0 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT0 + #define TC7Lo_BIT1 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT1 + #define TC7Lo_BIT2 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT2 + #define TC7Lo_BIT3 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT3 + #define TC7Lo_BIT4 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT4 + #define TC7Lo_BIT5 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT5 + #define TC7Lo_BIT6 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT6 + #define TC7Lo_BIT7 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT7 + #define TC7Lo_BIT _TC7.Overlap_STR.TC7LoSTR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} TC7STR; +extern volatile TC7STR _TC7 @(REG_BASE + 0x0000005E); +#define TC7 _TC7.Word +#define TC7_BIT _TC7.MergedBits.grpBIT + + +/*** PACNT - Pulse Accumulators Count Register; 0x00000062 ***/ +typedef union { + word Word; + struct { + word grpBIT :16; + } MergedBits; +} PACNTSTR; +extern volatile PACNTSTR _PACNT @(REG_BASE + 0x00000062); +#define PACNT _PACNT.Word +#define PACNT_BIT _PACNT.MergedBits.grpBIT + + +/*** ATDCTL23 - ATD Control Register 23; 0x00000082 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATDCTL2 - ATD Control Register 2; 0x00000082 ***/ + union { + byte Byte; + struct { + byte ASCIF :1; /* ATD Sequence Complete Interrupt Flag */ + byte ASCIE :1; /* ATD Sequence Complete Interrupt Enable */ + byte ETRIGE :1; /* External Trigger Mode enable */ + byte ETRIGP :1; /* External Trigger Polarity */ + byte ETRIGLE :1; /* External Trigger Level/Edge control */ + byte AWAI :1; /* ATD Wait Mode */ + byte AFFC :1; /* ATD Fast Conversion Complete Flag Clear */ + byte ADPU :1; /* ATD Disable / Power Down */ + } Bits; + } ATDCTL2STR; + #define ATDCTL2 _ATDCTL23.Overlap_STR.ATDCTL2STR.Byte + #define ATDCTL2_ASCIF _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.ASCIF + #define ATDCTL2_ASCIE _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.ASCIE + #define ATDCTL2_ETRIGE _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.ETRIGE + #define ATDCTL2_ETRIGP _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.ETRIGP + #define ATDCTL2_ETRIGLE _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.ETRIGLE + #define ATDCTL2_AWAI _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.AWAI + #define ATDCTL2_AFFC _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.AFFC + #define ATDCTL2_ADPU _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.ADPU + + /*** ATDCTL3 - ATD Control Register 3; 0x00000083 ***/ + union { + byte Byte; + struct { + byte FRZ0 :1; /* Background Debug Freeze Enable */ + byte FRZ1 :1; /* Background Debug Freeze Enable */ + byte FIFO :1; /* Result Register FIFO Mode */ + byte S1C :1; /* Conversion Sequence Length 1 */ + byte S2C :1; /* Conversion Sequence Length 2 */ + byte S4C :1; /* Conversion Sequence Length 4 */ + byte S8C :1; /* Conversion Sequence Length 8 */ + byte :1; + } Bits; + struct { + byte grpFRZ :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; + } ATDCTL3STR; + #define ATDCTL3 _ATDCTL23.Overlap_STR.ATDCTL3STR.Byte + #define ATDCTL3_FRZ0 _ATDCTL23.Overlap_STR.ATDCTL3STR.Bits.FRZ0 + #define ATDCTL3_FRZ1 _ATDCTL23.Overlap_STR.ATDCTL3STR.Bits.FRZ1 + #define ATDCTL3_FIFO _ATDCTL23.Overlap_STR.ATDCTL3STR.Bits.FIFO + #define ATDCTL3_S1C _ATDCTL23.Overlap_STR.ATDCTL3STR.Bits.S1C + #define ATDCTL3_S2C _ATDCTL23.Overlap_STR.ATDCTL3STR.Bits.S2C + #define ATDCTL3_S4C _ATDCTL23.Overlap_STR.ATDCTL3STR.Bits.S4C + #define ATDCTL3_S8C _ATDCTL23.Overlap_STR.ATDCTL3STR.Bits.S8C + #define ATDCTL3_FRZ _ATDCTL23.Overlap_STR.ATDCTL3STR.MergedBits.grpFRZ + + } Overlap_STR; + + struct { + word FRZ0 :1; /* Background Debug Freeze Enable */ + word FRZ1 :1; /* Background Debug Freeze Enable */ + word FIFO :1; /* Result Register FIFO Mode */ + word S1C :1; /* Conversion Sequence Length 1 */ + word S2C :1; /* Conversion Sequence Length 2 */ + word S4C :1; /* Conversion Sequence Length 4 */ + word S8C :1; /* Conversion Sequence Length 8 */ + word :1; + word ASCIF :1; /* ATD Sequence Complete Interrupt Flag */ + word ASCIE :1; /* ATD Sequence Complete Interrupt Enable */ + word ETRIGE :1; /* External Trigger Mode enable */ + word ETRIGP :1; /* External Trigger Polarity */ + word ETRIGLE :1; /* External Trigger Level/Edge control */ + word AWAI :1; /* ATD Wait Mode */ + word AFFC :1; /* ATD Fast Conversion Complete Flag Clear */ + word ADPU :1; /* ATD Disable / Power Down */ + } Bits; + struct { + word grpFRZ :2; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + } MergedBits; +} ATDCTL23STR; +extern volatile ATDCTL23STR _ATDCTL23 @(REG_BASE + 0x00000082); +#define ATDCTL23 _ATDCTL23.Word +#define ATDCTL23_FRZ0 _ATDCTL23.Bits.FRZ0 +#define ATDCTL23_FRZ1 _ATDCTL23.Bits.FRZ1 +#define ATDCTL23_FIFO _ATDCTL23.Bits.FIFO +#define ATDCTL23_S1C _ATDCTL23.Bits.S1C +#define ATDCTL23_S2C _ATDCTL23.Bits.S2C +#define ATDCTL23_S4C _ATDCTL23.Bits.S4C +#define ATDCTL23_S8C _ATDCTL23.Bits.S8C +#define ATDCTL23_ASCIF _ATDCTL23.Bits.ASCIF +#define ATDCTL23_ASCIE _ATDCTL23.Bits.ASCIE +#define ATDCTL23_ETRIGE _ATDCTL23.Bits.ETRIGE +#define ATDCTL23_ETRIGP _ATDCTL23.Bits.ETRIGP +#define ATDCTL23_ETRIGLE _ATDCTL23.Bits.ETRIGLE +#define ATDCTL23_AWAI _ATDCTL23.Bits.AWAI +#define ATDCTL23_AFFC _ATDCTL23.Bits.AFFC +#define ATDCTL23_ADPU _ATDCTL23.Bits.ADPU +#define ATDCTL23_FRZ _ATDCTL23.MergedBits.grpFRZ + + +/*** ATDCTL45 - ATD Control Register 45; 0x00000084 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATDCTL4 - ATD Control Register 4; 0x00000084 ***/ + union { + byte Byte; + struct { + byte PRS0 :1; /* ATD Clock Prescaler 0 */ + byte PRS1 :1; /* ATD Clock Prescaler 1 */ + byte PRS2 :1; /* ATD Clock Prescaler 2 */ + byte PRS3 :1; /* ATD Clock Prescaler 3 */ + byte PRS4 :1; /* ATD Clock Prescaler 4 */ + byte SMP0 :1; /* Sample Time Select 0 */ + byte SMP1 :1; /* Sample Time Select 1 */ + byte SRES8 :1; /* A/D Resolution Select */ + } Bits; + struct { + byte grpPRS :5; + byte grpSMP :2; + byte grpSRES_8 :1; + } MergedBits; + } ATDCTL4STR; + #define ATDCTL4 _ATDCTL45.Overlap_STR.ATDCTL4STR.Byte + #define ATDCTL4_PRS0 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.PRS0 + #define ATDCTL4_PRS1 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.PRS1 + #define ATDCTL4_PRS2 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.PRS2 + #define ATDCTL4_PRS3 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.PRS3 + #define ATDCTL4_PRS4 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.PRS4 + #define ATDCTL4_SMP0 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.SMP0 + #define ATDCTL4_SMP1 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.SMP1 + #define ATDCTL4_SRES8 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.SRES8 + #define ATDCTL4_PRS _ATDCTL45.Overlap_STR.ATDCTL4STR.MergedBits.grpPRS + #define ATDCTL4_SMP _ATDCTL45.Overlap_STR.ATDCTL4STR.MergedBits.grpSMP + + /*** ATDCTL5 - ATD Control Register 5; 0x00000085 ***/ + union { + byte Byte; + struct { + byte CA :1; /* Analog Input Channel Select Code A */ + byte CB :1; /* Analog Input Channel Select Code B */ + byte CC :1; /* Analog Input Channel Select Code C */ + byte :1; + byte MULT :1; /* Multi-Channel Sample Mode */ + byte SCAN :1; /* Continuous Conversion Sequence Mode */ + byte DSGN :1; /* Signed/Unsigned Result Data Mode */ + byte DJM :1; /* Result Register Data Justification Mode */ + } Bits; + } ATDCTL5STR; + #define ATDCTL5 _ATDCTL45.Overlap_STR.ATDCTL5STR.Byte + #define ATDCTL5_CA _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.CA + #define ATDCTL5_CB _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.CB + #define ATDCTL5_CC _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.CC + #define ATDCTL5_MULT _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.MULT + #define ATDCTL5_SCAN _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.SCAN + #define ATDCTL5_DSGN _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.DSGN + #define ATDCTL5_DJM _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.DJM + + } Overlap_STR; + + struct { + word CA :1; /* Analog Input Channel Select Code A */ + word CB :1; /* Analog Input Channel Select Code B */ + word CC :1; /* Analog Input Channel Select Code C */ + word :1; + word MULT :1; /* Multi-Channel Sample Mode */ + word SCAN :1; /* Continuous Conversion Sequence Mode */ + word DSGN :1; /* Signed/Unsigned Result Data Mode */ + word DJM :1; /* Result Register Data Justification Mode */ + word PRS0 :1; /* ATD Clock Prescaler 0 */ + word PRS1 :1; /* ATD Clock Prescaler 1 */ + word PRS2 :1; /* ATD Clock Prescaler 2 */ + word PRS3 :1; /* ATD Clock Prescaler 3 */ + word PRS4 :1; /* ATD Clock Prescaler 4 */ + word SMP0 :1; /* Sample Time Select 0 */ + word SMP1 :1; /* Sample Time Select 1 */ + word SRES8 :1; /* A/D Resolution Select */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpPRS :5; + word grpSMP :2; + word grpSRES_8 :1; + } MergedBits; +} ATDCTL45STR; +extern volatile ATDCTL45STR _ATDCTL45 @(REG_BASE + 0x00000084); +#define ATDCTL45 _ATDCTL45.Word +#define ATDCTL45_CA _ATDCTL45.Bits.CA +#define ATDCTL45_CB _ATDCTL45.Bits.CB +#define ATDCTL45_CC _ATDCTL45.Bits.CC +#define ATDCTL45_MULT _ATDCTL45.Bits.MULT +#define ATDCTL45_SCAN _ATDCTL45.Bits.SCAN +#define ATDCTL45_DSGN _ATDCTL45.Bits.DSGN +#define ATDCTL45_DJM _ATDCTL45.Bits.DJM +#define ATDCTL45_PRS0 _ATDCTL45.Bits.PRS0 +#define ATDCTL45_PRS1 _ATDCTL45.Bits.PRS1 +#define ATDCTL45_PRS2 _ATDCTL45.Bits.PRS2 +#define ATDCTL45_PRS3 _ATDCTL45.Bits.PRS3 +#define ATDCTL45_PRS4 _ATDCTL45.Bits.PRS4 +#define ATDCTL45_SMP0 _ATDCTL45.Bits.SMP0 +#define ATDCTL45_SMP1 _ATDCTL45.Bits.SMP1 +#define ATDCTL45_SRES8 _ATDCTL45.Bits.SRES8 +#define ATDCTL45_PRS _ATDCTL45.MergedBits.grpPRS +#define ATDCTL45_SMP _ATDCTL45.MergedBits.grpSMP + + +/*** ATDDR0 - A/D Conversion Result Register 0; 0x00000090 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATDDR0H - A/D Conversion Result Register 0 High; 0x00000090 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } ATDDR0HSTR; + #define ATDDR0H _ATDDR0.Overlap_STR.ATDDR0HSTR.Byte + #define ATDDR0H_BIT8 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT8 + #define ATDDR0H_BIT9 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT9 + #define ATDDR0H_BIT10 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT10 + #define ATDDR0H_BIT11 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT11 + #define ATDDR0H_BIT12 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT12 + #define ATDDR0H_BIT13 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT13 + #define ATDDR0H_BIT14 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT14 + #define ATDDR0H_BIT15 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT15 + #define ATDDR0H_BIT_8 _ATDDR0.Overlap_STR.ATDDR0HSTR.MergedBits.grpBIT_8 + #define ATDDR0H_BIT ATDDR0H_BIT_8 + + /*** ATDDR0L - A/D Conversion Result Register 0 Low; 0x00000091 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATDDR0LSTR; + #define ATDDR0L _ATDDR0.Overlap_STR.ATDDR0LSTR.Byte + #define ATDDR0L_BIT6 _ATDDR0.Overlap_STR.ATDDR0LSTR.Bits.BIT6 + #define ATDDR0L_BIT7 _ATDDR0.Overlap_STR.ATDDR0LSTR.Bits.BIT7 + #define ATDDR0L_BIT_6 _ATDDR0.Overlap_STR.ATDDR0LSTR.MergedBits.grpBIT_6 + #define ATDDR0L_BIT ATDDR0L_BIT_6 + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATDDR0STR; +extern volatile ATDDR0STR _ATDDR0 @(REG_BASE + 0x00000090); +#define ATDDR0 _ATDDR0.Word +#define ATDDR0_BIT6 _ATDDR0.Bits.BIT6 +#define ATDDR0_BIT7 _ATDDR0.Bits.BIT7 +#define ATDDR0_BIT8 _ATDDR0.Bits.BIT8 +#define ATDDR0_BIT9 _ATDDR0.Bits.BIT9 +#define ATDDR0_BIT10 _ATDDR0.Bits.BIT10 +#define ATDDR0_BIT11 _ATDDR0.Bits.BIT11 +#define ATDDR0_BIT12 _ATDDR0.Bits.BIT12 +#define ATDDR0_BIT13 _ATDDR0.Bits.BIT13 +#define ATDDR0_BIT14 _ATDDR0.Bits.BIT14 +#define ATDDR0_BIT15 _ATDDR0.Bits.BIT15 +#define ATDDR0_BIT_6 _ATDDR0.MergedBits.grpBIT_6 +#define ATDDR0_BIT ATDDR0_BIT_6 + + +/*** ATDDR1 - A/D Conversion Result Register 1; 0x00000092 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATDDR1H - A/D Conversion Result Register 1 High; 0x00000092 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } ATDDR1HSTR; + #define ATDDR1H _ATDDR1.Overlap_STR.ATDDR1HSTR.Byte + #define ATDDR1H_BIT8 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT8 + #define ATDDR1H_BIT9 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT9 + #define ATDDR1H_BIT10 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT10 + #define ATDDR1H_BIT11 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT11 + #define ATDDR1H_BIT12 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT12 + #define ATDDR1H_BIT13 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT13 + #define ATDDR1H_BIT14 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT14 + #define ATDDR1H_BIT15 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT15 + #define ATDDR1H_BIT_8 _ATDDR1.Overlap_STR.ATDDR1HSTR.MergedBits.grpBIT_8 + #define ATDDR1H_BIT ATDDR1H_BIT_8 + + /*** ATDDR1L - A/D Conversion Result Register 1 Low; 0x00000093 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATDDR1LSTR; + #define ATDDR1L _ATDDR1.Overlap_STR.ATDDR1LSTR.Byte + #define ATDDR1L_BIT6 _ATDDR1.Overlap_STR.ATDDR1LSTR.Bits.BIT6 + #define ATDDR1L_BIT7 _ATDDR1.Overlap_STR.ATDDR1LSTR.Bits.BIT7 + #define ATDDR1L_BIT_6 _ATDDR1.Overlap_STR.ATDDR1LSTR.MergedBits.grpBIT_6 + #define ATDDR1L_BIT ATDDR1L_BIT_6 + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATDDR1STR; +extern volatile ATDDR1STR _ATDDR1 @(REG_BASE + 0x00000092); +#define ATDDR1 _ATDDR1.Word +#define ATDDR1_BIT6 _ATDDR1.Bits.BIT6 +#define ATDDR1_BIT7 _ATDDR1.Bits.BIT7 +#define ATDDR1_BIT8 _ATDDR1.Bits.BIT8 +#define ATDDR1_BIT9 _ATDDR1.Bits.BIT9 +#define ATDDR1_BIT10 _ATDDR1.Bits.BIT10 +#define ATDDR1_BIT11 _ATDDR1.Bits.BIT11 +#define ATDDR1_BIT12 _ATDDR1.Bits.BIT12 +#define ATDDR1_BIT13 _ATDDR1.Bits.BIT13 +#define ATDDR1_BIT14 _ATDDR1.Bits.BIT14 +#define ATDDR1_BIT15 _ATDDR1.Bits.BIT15 +#define ATDDR1_BIT_6 _ATDDR1.MergedBits.grpBIT_6 +#define ATDDR1_BIT ATDDR1_BIT_6 + + +/*** ATDDR2 - A/D Conversion Result Register 2; 0x00000094 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATDDR2H - A/D Conversion Result Register 2 High; 0x00000094 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } ATDDR2HSTR; + #define ATDDR2H _ATDDR2.Overlap_STR.ATDDR2HSTR.Byte + #define ATDDR2H_BIT8 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT8 + #define ATDDR2H_BIT9 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT9 + #define ATDDR2H_BIT10 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT10 + #define ATDDR2H_BIT11 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT11 + #define ATDDR2H_BIT12 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT12 + #define ATDDR2H_BIT13 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT13 + #define ATDDR2H_BIT14 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT14 + #define ATDDR2H_BIT15 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT15 + #define ATDDR2H_BIT_8 _ATDDR2.Overlap_STR.ATDDR2HSTR.MergedBits.grpBIT_8 + #define ATDDR2H_BIT ATDDR2H_BIT_8 + + /*** ATDDR2L - A/D Conversion Result Register 2 Low; 0x00000095 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATDDR2LSTR; + #define ATDDR2L _ATDDR2.Overlap_STR.ATDDR2LSTR.Byte + #define ATDDR2L_BIT6 _ATDDR2.Overlap_STR.ATDDR2LSTR.Bits.BIT6 + #define ATDDR2L_BIT7 _ATDDR2.Overlap_STR.ATDDR2LSTR.Bits.BIT7 + #define ATDDR2L_BIT_6 _ATDDR2.Overlap_STR.ATDDR2LSTR.MergedBits.grpBIT_6 + #define ATDDR2L_BIT ATDDR2L_BIT_6 + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATDDR2STR; +extern volatile ATDDR2STR _ATDDR2 @(REG_BASE + 0x00000094); +#define ATDDR2 _ATDDR2.Word +#define ATDDR2_BIT6 _ATDDR2.Bits.BIT6 +#define ATDDR2_BIT7 _ATDDR2.Bits.BIT7 +#define ATDDR2_BIT8 _ATDDR2.Bits.BIT8 +#define ATDDR2_BIT9 _ATDDR2.Bits.BIT9 +#define ATDDR2_BIT10 _ATDDR2.Bits.BIT10 +#define ATDDR2_BIT11 _ATDDR2.Bits.BIT11 +#define ATDDR2_BIT12 _ATDDR2.Bits.BIT12 +#define ATDDR2_BIT13 _ATDDR2.Bits.BIT13 +#define ATDDR2_BIT14 _ATDDR2.Bits.BIT14 +#define ATDDR2_BIT15 _ATDDR2.Bits.BIT15 +#define ATDDR2_BIT_6 _ATDDR2.MergedBits.grpBIT_6 +#define ATDDR2_BIT ATDDR2_BIT_6 + + +/*** ATDDR3 - A/D Conversion Result Register 3; 0x00000096 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATDDR3H - A/D Conversion Result Register 3 High; 0x00000096 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } ATDDR3HSTR; + #define ATDDR3H _ATDDR3.Overlap_STR.ATDDR3HSTR.Byte + #define ATDDR3H_BIT8 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT8 + #define ATDDR3H_BIT9 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT9 + #define ATDDR3H_BIT10 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT10 + #define ATDDR3H_BIT11 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT11 + #define ATDDR3H_BIT12 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT12 + #define ATDDR3H_BIT13 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT13 + #define ATDDR3H_BIT14 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT14 + #define ATDDR3H_BIT15 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT15 + #define ATDDR3H_BIT_8 _ATDDR3.Overlap_STR.ATDDR3HSTR.MergedBits.grpBIT_8 + #define ATDDR3H_BIT ATDDR3H_BIT_8 + + /*** ATDDR3L - A/D Conversion Result Register 3 Low; 0x00000097 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATDDR3LSTR; + #define ATDDR3L _ATDDR3.Overlap_STR.ATDDR3LSTR.Byte + #define ATDDR3L_BIT6 _ATDDR3.Overlap_STR.ATDDR3LSTR.Bits.BIT6 + #define ATDDR3L_BIT7 _ATDDR3.Overlap_STR.ATDDR3LSTR.Bits.BIT7 + #define ATDDR3L_BIT_6 _ATDDR3.Overlap_STR.ATDDR3LSTR.MergedBits.grpBIT_6 + #define ATDDR3L_BIT ATDDR3L_BIT_6 + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATDDR3STR; +extern volatile ATDDR3STR _ATDDR3 @(REG_BASE + 0x00000096); +#define ATDDR3 _ATDDR3.Word +#define ATDDR3_BIT6 _ATDDR3.Bits.BIT6 +#define ATDDR3_BIT7 _ATDDR3.Bits.BIT7 +#define ATDDR3_BIT8 _ATDDR3.Bits.BIT8 +#define ATDDR3_BIT9 _ATDDR3.Bits.BIT9 +#define ATDDR3_BIT10 _ATDDR3.Bits.BIT10 +#define ATDDR3_BIT11 _ATDDR3.Bits.BIT11 +#define ATDDR3_BIT12 _ATDDR3.Bits.BIT12 +#define ATDDR3_BIT13 _ATDDR3.Bits.BIT13 +#define ATDDR3_BIT14 _ATDDR3.Bits.BIT14 +#define ATDDR3_BIT15 _ATDDR3.Bits.BIT15 +#define ATDDR3_BIT_6 _ATDDR3.MergedBits.grpBIT_6 +#define ATDDR3_BIT ATDDR3_BIT_6 + + +/*** ATDDR4 - A/D Conversion Result Register 4; 0x00000098 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATDDR4H - A/D Conversion Result Register 4 High; 0x00000098 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } ATDDR4HSTR; + #define ATDDR4H _ATDDR4.Overlap_STR.ATDDR4HSTR.Byte + #define ATDDR4H_BIT8 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT8 + #define ATDDR4H_BIT9 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT9 + #define ATDDR4H_BIT10 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT10 + #define ATDDR4H_BIT11 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT11 + #define ATDDR4H_BIT12 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT12 + #define ATDDR4H_BIT13 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT13 + #define ATDDR4H_BIT14 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT14 + #define ATDDR4H_BIT15 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT15 + #define ATDDR4H_BIT_8 _ATDDR4.Overlap_STR.ATDDR4HSTR.MergedBits.grpBIT_8 + #define ATDDR4H_BIT ATDDR4H_BIT_8 + + /*** ATDDR4L - A/D Conversion Result Register 4 Low; 0x00000099 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATDDR4LSTR; + #define ATDDR4L _ATDDR4.Overlap_STR.ATDDR4LSTR.Byte + #define ATDDR4L_BIT6 _ATDDR4.Overlap_STR.ATDDR4LSTR.Bits.BIT6 + #define ATDDR4L_BIT7 _ATDDR4.Overlap_STR.ATDDR4LSTR.Bits.BIT7 + #define ATDDR4L_BIT_6 _ATDDR4.Overlap_STR.ATDDR4LSTR.MergedBits.grpBIT_6 + #define ATDDR4L_BIT ATDDR4L_BIT_6 + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATDDR4STR; +extern volatile ATDDR4STR _ATDDR4 @(REG_BASE + 0x00000098); +#define ATDDR4 _ATDDR4.Word +#define ATDDR4_BIT6 _ATDDR4.Bits.BIT6 +#define ATDDR4_BIT7 _ATDDR4.Bits.BIT7 +#define ATDDR4_BIT8 _ATDDR4.Bits.BIT8 +#define ATDDR4_BIT9 _ATDDR4.Bits.BIT9 +#define ATDDR4_BIT10 _ATDDR4.Bits.BIT10 +#define ATDDR4_BIT11 _ATDDR4.Bits.BIT11 +#define ATDDR4_BIT12 _ATDDR4.Bits.BIT12 +#define ATDDR4_BIT13 _ATDDR4.Bits.BIT13 +#define ATDDR4_BIT14 _ATDDR4.Bits.BIT14 +#define ATDDR4_BIT15 _ATDDR4.Bits.BIT15 +#define ATDDR4_BIT_6 _ATDDR4.MergedBits.grpBIT_6 +#define ATDDR4_BIT ATDDR4_BIT_6 + + +/*** ATDDR5 - A/D Conversion Result Register 5; 0x0000009A ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATDDR5H - A/D Conversion Result Register 5 High; 0x0000009A ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } ATDDR5HSTR; + #define ATDDR5H _ATDDR5.Overlap_STR.ATDDR5HSTR.Byte + #define ATDDR5H_BIT8 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT8 + #define ATDDR5H_BIT9 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT9 + #define ATDDR5H_BIT10 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT10 + #define ATDDR5H_BIT11 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT11 + #define ATDDR5H_BIT12 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT12 + #define ATDDR5H_BIT13 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT13 + #define ATDDR5H_BIT14 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT14 + #define ATDDR5H_BIT15 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT15 + #define ATDDR5H_BIT_8 _ATDDR5.Overlap_STR.ATDDR5HSTR.MergedBits.grpBIT_8 + #define ATDDR5H_BIT ATDDR5H_BIT_8 + + /*** ATDDR5L - A/D Conversion Result Register 5 Low; 0x0000009B ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATDDR5LSTR; + #define ATDDR5L _ATDDR5.Overlap_STR.ATDDR5LSTR.Byte + #define ATDDR5L_BIT6 _ATDDR5.Overlap_STR.ATDDR5LSTR.Bits.BIT6 + #define ATDDR5L_BIT7 _ATDDR5.Overlap_STR.ATDDR5LSTR.Bits.BIT7 + #define ATDDR5L_BIT_6 _ATDDR5.Overlap_STR.ATDDR5LSTR.MergedBits.grpBIT_6 + #define ATDDR5L_BIT ATDDR5L_BIT_6 + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATDDR5STR; +extern volatile ATDDR5STR _ATDDR5 @(REG_BASE + 0x0000009A); +#define ATDDR5 _ATDDR5.Word +#define ATDDR5_BIT6 _ATDDR5.Bits.BIT6 +#define ATDDR5_BIT7 _ATDDR5.Bits.BIT7 +#define ATDDR5_BIT8 _ATDDR5.Bits.BIT8 +#define ATDDR5_BIT9 _ATDDR5.Bits.BIT9 +#define ATDDR5_BIT10 _ATDDR5.Bits.BIT10 +#define ATDDR5_BIT11 _ATDDR5.Bits.BIT11 +#define ATDDR5_BIT12 _ATDDR5.Bits.BIT12 +#define ATDDR5_BIT13 _ATDDR5.Bits.BIT13 +#define ATDDR5_BIT14 _ATDDR5.Bits.BIT14 +#define ATDDR5_BIT15 _ATDDR5.Bits.BIT15 +#define ATDDR5_BIT_6 _ATDDR5.MergedBits.grpBIT_6 +#define ATDDR5_BIT ATDDR5_BIT_6 + + +/*** ATDDR6 - A/D Conversion Result Register 6; 0x0000009C ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATDDR6H - A/D Conversion Result Register 6 High; 0x0000009C ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } ATDDR6HSTR; + #define ATDDR6H _ATDDR6.Overlap_STR.ATDDR6HSTR.Byte + #define ATDDR6H_BIT8 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT8 + #define ATDDR6H_BIT9 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT9 + #define ATDDR6H_BIT10 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT10 + #define ATDDR6H_BIT11 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT11 + #define ATDDR6H_BIT12 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT12 + #define ATDDR6H_BIT13 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT13 + #define ATDDR6H_BIT14 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT14 + #define ATDDR6H_BIT15 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT15 + #define ATDDR6H_BIT_8 _ATDDR6.Overlap_STR.ATDDR6HSTR.MergedBits.grpBIT_8 + #define ATDDR6H_BIT ATDDR6H_BIT_8 + + /*** ATDDR6L - A/D Conversion Result Register 6 Low; 0x0000009D ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATDDR6LSTR; + #define ATDDR6L _ATDDR6.Overlap_STR.ATDDR6LSTR.Byte + #define ATDDR6L_BIT6 _ATDDR6.Overlap_STR.ATDDR6LSTR.Bits.BIT6 + #define ATDDR6L_BIT7 _ATDDR6.Overlap_STR.ATDDR6LSTR.Bits.BIT7 + #define ATDDR6L_BIT_6 _ATDDR6.Overlap_STR.ATDDR6LSTR.MergedBits.grpBIT_6 + #define ATDDR6L_BIT ATDDR6L_BIT_6 + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATDDR6STR; +extern volatile ATDDR6STR _ATDDR6 @(REG_BASE + 0x0000009C); +#define ATDDR6 _ATDDR6.Word +#define ATDDR6_BIT6 _ATDDR6.Bits.BIT6 +#define ATDDR6_BIT7 _ATDDR6.Bits.BIT7 +#define ATDDR6_BIT8 _ATDDR6.Bits.BIT8 +#define ATDDR6_BIT9 _ATDDR6.Bits.BIT9 +#define ATDDR6_BIT10 _ATDDR6.Bits.BIT10 +#define ATDDR6_BIT11 _ATDDR6.Bits.BIT11 +#define ATDDR6_BIT12 _ATDDR6.Bits.BIT12 +#define ATDDR6_BIT13 _ATDDR6.Bits.BIT13 +#define ATDDR6_BIT14 _ATDDR6.Bits.BIT14 +#define ATDDR6_BIT15 _ATDDR6.Bits.BIT15 +#define ATDDR6_BIT_6 _ATDDR6.MergedBits.grpBIT_6 +#define ATDDR6_BIT ATDDR6_BIT_6 + + +/*** ATDDR7 - A/D Conversion Result Register 7; 0x0000009E ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATDDR7H - A/D Conversion Result Register 7 High; 0x0000009E ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; + } ATDDR7HSTR; + #define ATDDR7H _ATDDR7.Overlap_STR.ATDDR7HSTR.Byte + #define ATDDR7H_BIT8 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT8 + #define ATDDR7H_BIT9 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT9 + #define ATDDR7H_BIT10 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT10 + #define ATDDR7H_BIT11 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT11 + #define ATDDR7H_BIT12 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT12 + #define ATDDR7H_BIT13 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT13 + #define ATDDR7H_BIT14 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT14 + #define ATDDR7H_BIT15 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT15 + #define ATDDR7H_BIT_8 _ATDDR7.Overlap_STR.ATDDR7HSTR.MergedBits.grpBIT_8 + #define ATDDR7H_BIT ATDDR7H_BIT_8 + + /*** ATDDR7L - A/D Conversion Result Register 7 Low; 0x0000009F ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATDDR7LSTR; + #define ATDDR7L _ATDDR7.Overlap_STR.ATDDR7LSTR.Byte + #define ATDDR7L_BIT6 _ATDDR7.Overlap_STR.ATDDR7LSTR.Bits.BIT6 + #define ATDDR7L_BIT7 _ATDDR7.Overlap_STR.ATDDR7LSTR.Bits.BIT7 + #define ATDDR7L_BIT_6 _ATDDR7.Overlap_STR.ATDDR7LSTR.MergedBits.grpBIT_6 + #define ATDDR7L_BIT ATDDR7L_BIT_6 + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATDDR7STR; +extern volatile ATDDR7STR _ATDDR7 @(REG_BASE + 0x0000009E); +#define ATDDR7 _ATDDR7.Word +#define ATDDR7_BIT6 _ATDDR7.Bits.BIT6 +#define ATDDR7_BIT7 _ATDDR7.Bits.BIT7 +#define ATDDR7_BIT8 _ATDDR7.Bits.BIT8 +#define ATDDR7_BIT9 _ATDDR7.Bits.BIT9 +#define ATDDR7_BIT10 _ATDDR7.Bits.BIT10 +#define ATDDR7_BIT11 _ATDDR7.Bits.BIT11 +#define ATDDR7_BIT12 _ATDDR7.Bits.BIT12 +#define ATDDR7_BIT13 _ATDDR7.Bits.BIT13 +#define ATDDR7_BIT14 _ATDDR7.Bits.BIT14 +#define ATDDR7_BIT15 _ATDDR7.Bits.BIT15 +#define ATDDR7_BIT_6 _ATDDR7.MergedBits.grpBIT_6 +#define ATDDR7_BIT ATDDR7_BIT_6 + + +/*** SCIBD - SCI Baud Rate Register; 0x000000C8 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** SCIBDH - SCI Baud Rate Register High; 0x000000C8 ***/ + union { + byte Byte; + struct { + byte SBR8 :1; /* SCI baud rate Bit 8 */ + byte SBR9 :1; /* SCI baud rate Bit 9 */ + byte SBR10 :1; /* SCI baud rate Bit 10 */ + byte SBR11 :1; /* SCI baud rate Bit 11 */ + byte SBR12 :1; /* SCI baud rate Bit 12 */ + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpSBR_8 :5; + byte :1; + byte :1; + byte :1; + } MergedBits; + } SCIBDHSTR; + #define SCIBDH _SCIBD.Overlap_STR.SCIBDHSTR.Byte + #define SCIBDH_SBR8 _SCIBD.Overlap_STR.SCIBDHSTR.Bits.SBR8 + #define SCIBDH_SBR9 _SCIBD.Overlap_STR.SCIBDHSTR.Bits.SBR9 + #define SCIBDH_SBR10 _SCIBD.Overlap_STR.SCIBDHSTR.Bits.SBR10 + #define SCIBDH_SBR11 _SCIBD.Overlap_STR.SCIBDHSTR.Bits.SBR11 + #define SCIBDH_SBR12 _SCIBD.Overlap_STR.SCIBDHSTR.Bits.SBR12 + #define SCIBDH_SBR_8 _SCIBD.Overlap_STR.SCIBDHSTR.MergedBits.grpSBR_8 + #define SCIBDH_SBR SCIBDH_SBR_8 + + /*** SCIBDL - SCI Baud Rate Register Low; 0x000000C9 ***/ + union { + byte Byte; + struct { + byte SBR0 :1; /* SCI baud rate Bit 0 */ + byte SBR1 :1; /* SCI baud rate Bit 1 */ + byte SBR2 :1; /* SCI baud rate Bit 2 */ + byte SBR3 :1; /* SCI baud rate Bit 3 */ + byte SBR4 :1; /* SCI baud rate Bit 4 */ + byte SBR5 :1; /* SCI baud rate Bit 5 */ + byte SBR6 :1; /* SCI baud rate Bit 6 */ + byte SBR7 :1; /* SCI baud rate Bit 7 */ + } Bits; + struct { + byte grpSBR :8; + } MergedBits; + } SCIBDLSTR; + #define SCIBDL _SCIBD.Overlap_STR.SCIBDLSTR.Byte + #define SCIBDL_SBR0 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR0 + #define SCIBDL_SBR1 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR1 + #define SCIBDL_SBR2 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR2 + #define SCIBDL_SBR3 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR3 + #define SCIBDL_SBR4 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR4 + #define SCIBDL_SBR5 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR5 + #define SCIBDL_SBR6 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR6 + #define SCIBDL_SBR7 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR7 + #define SCIBDL_SBR _SCIBD.Overlap_STR.SCIBDLSTR.MergedBits.grpSBR + + } Overlap_STR; + + struct { + word SBR0 :1; /* SCI baud rate Bit 0 */ + word SBR1 :1; /* SCI baud rate Bit 1 */ + word SBR2 :1; /* SCI baud rate Bit 2 */ + word SBR3 :1; /* SCI baud rate Bit 3 */ + word SBR4 :1; /* SCI baud rate Bit 4 */ + word SBR5 :1; /* SCI baud rate Bit 5 */ + word SBR6 :1; /* SCI baud rate Bit 6 */ + word SBR7 :1; /* SCI baud rate Bit 7 */ + word SBR8 :1; /* SCI baud rate Bit 8 */ + word SBR9 :1; /* SCI baud rate Bit 9 */ + word SBR10 :1; /* SCI baud rate Bit 10 */ + word SBR11 :1; /* SCI baud rate Bit 11 */ + word SBR12 :1; /* SCI baud rate Bit 12 */ + word :1; + word :1; + word :1; + } Bits; + struct { + word grpSBR :13; + word :1; + word :1; + word :1; + } MergedBits; +} SCIBDSTR; +extern volatile SCIBDSTR _SCIBD @(REG_BASE + 0x000000C8); +#define SCIBD _SCIBD.Word +#define SCIBD_SBR0 _SCIBD.Bits.SBR0 +#define SCIBD_SBR1 _SCIBD.Bits.SBR1 +#define SCIBD_SBR2 _SCIBD.Bits.SBR2 +#define SCIBD_SBR3 _SCIBD.Bits.SBR3 +#define SCIBD_SBR4 _SCIBD.Bits.SBR4 +#define SCIBD_SBR5 _SCIBD.Bits.SBR5 +#define SCIBD_SBR6 _SCIBD.Bits.SBR6 +#define SCIBD_SBR7 _SCIBD.Bits.SBR7 +#define SCIBD_SBR8 _SCIBD.Bits.SBR8 +#define SCIBD_SBR9 _SCIBD.Bits.SBR9 +#define SCIBD_SBR10 _SCIBD.Bits.SBR10 +#define SCIBD_SBR11 _SCIBD.Bits.SBR11 +#define SCIBD_SBR12 _SCIBD.Bits.SBR12 +#define SCIBD_SBR _SCIBD.MergedBits.grpSBR + + +/*** PWMCNT01 - PWM Channel Counter 01 Register; 0x000000EC ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMCNT0 - PWM Channel Counter 0 Register; 0x000000EC ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMCNT0STR; + #define PWMCNT0 _PWMCNT01.Overlap_STR.PWMCNT0STR.Byte + #define PWMCNT0_BIT _PWMCNT01.Overlap_STR.PWMCNT0STR.MergedBits.grpBIT + + /*** PWMCNT1 - PWM Channel Counter 1 Register; 0x000000ED ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMCNT1STR; + #define PWMCNT1 _PWMCNT01.Overlap_STR.PWMCNT1STR.Byte + #define PWMCNT1_BIT _PWMCNT01.Overlap_STR.PWMCNT1STR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} PWMCNT01STR; +extern volatile PWMCNT01STR _PWMCNT01 @(REG_BASE + 0x000000EC); +#define PWMCNT01 _PWMCNT01.Word +#define PWMCNT01_BIT _PWMCNT01.MergedBits.grpBIT + + +/*** PWMCNT23 - PWM Channel Counter 23 Register; 0x000000EE ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMCNT2 - PWM Channel Counter 2 Register; 0x000000EE ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMCNT2STR; + #define PWMCNT2 _PWMCNT23.Overlap_STR.PWMCNT2STR.Byte + #define PWMCNT2_BIT _PWMCNT23.Overlap_STR.PWMCNT2STR.MergedBits.grpBIT + + /*** PWMCNT3 - PWM Channel Counter 3 Register; 0x000000EF ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMCNT3STR; + #define PWMCNT3 _PWMCNT23.Overlap_STR.PWMCNT3STR.Byte + #define PWMCNT3_BIT _PWMCNT23.Overlap_STR.PWMCNT3STR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} PWMCNT23STR; +extern volatile PWMCNT23STR _PWMCNT23 @(REG_BASE + 0x000000EE); +#define PWMCNT23 _PWMCNT23.Word +#define PWMCNT23_BIT _PWMCNT23.MergedBits.grpBIT + + +/*** PWMCNT45 - PWM Channel Counter 45 Register; 0x000000F0 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMCNT4 - PWM Channel Counter 4 Register; 0x000000F0 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMCNT4STR; + #define PWMCNT4 _PWMCNT45.Overlap_STR.PWMCNT4STR.Byte + #define PWMCNT4_BIT _PWMCNT45.Overlap_STR.PWMCNT4STR.MergedBits.grpBIT + + /*** PWMCNT5 - PWM Channel Counter 5 Register; 0x000000F1 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMCNT5STR; + #define PWMCNT5 _PWMCNT45.Overlap_STR.PWMCNT5STR.Byte + #define PWMCNT5_BIT _PWMCNT45.Overlap_STR.PWMCNT5STR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} PWMCNT45STR; +extern volatile PWMCNT45STR _PWMCNT45 @(REG_BASE + 0x000000F0); +#define PWMCNT45 _PWMCNT45.Word +#define PWMCNT45_BIT _PWMCNT45.MergedBits.grpBIT + + +/*** PWMPER01 - PWM Channel Period 01 Register; 0x000000F2 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMPER0 - PWM Channel Period 0 Register; 0x000000F2 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMPER0STR; + #define PWMPER0 _PWMPER01.Overlap_STR.PWMPER0STR.Byte + #define PWMPER0_BIT _PWMPER01.Overlap_STR.PWMPER0STR.MergedBits.grpBIT + + /*** PWMPER1 - PWM Channel Period 1 Register; 0x000000F3 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMPER1STR; + #define PWMPER1 _PWMPER01.Overlap_STR.PWMPER1STR.Byte + #define PWMPER1_BIT _PWMPER01.Overlap_STR.PWMPER1STR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} PWMPER01STR; +extern volatile PWMPER01STR _PWMPER01 @(REG_BASE + 0x000000F2); +#define PWMPER01 _PWMPER01.Word +#define PWMPER01_BIT _PWMPER01.MergedBits.grpBIT + + +/*** PWMPER23 - PWM Channel Period 23 Register; 0x000000F4 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMPER2 - PWM Channel Period 2 Register; 0x000000F4 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMPER2STR; + #define PWMPER2 _PWMPER23.Overlap_STR.PWMPER2STR.Byte + #define PWMPER2_BIT _PWMPER23.Overlap_STR.PWMPER2STR.MergedBits.grpBIT + + /*** PWMPER3 - PWM Channel Period 3 Register; 0x000000F5 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMPER3STR; + #define PWMPER3 _PWMPER23.Overlap_STR.PWMPER3STR.Byte + #define PWMPER3_BIT _PWMPER23.Overlap_STR.PWMPER3STR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} PWMPER23STR; +extern volatile PWMPER23STR _PWMPER23 @(REG_BASE + 0x000000F4); +#define PWMPER23 _PWMPER23.Word +#define PWMPER23_BIT _PWMPER23.MergedBits.grpBIT + + +/*** PWMPER45 - PWM Channel Period 45 Register; 0x000000F6 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMPER4 - PWM Channel Period 4 Register; 0x000000F6 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMPER4STR; + #define PWMPER4 _PWMPER45.Overlap_STR.PWMPER4STR.Byte + #define PWMPER4_BIT _PWMPER45.Overlap_STR.PWMPER4STR.MergedBits.grpBIT + + /*** PWMPER5 - PWM Channel Period 5 Register; 0x000000F7 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMPER5STR; + #define PWMPER5 _PWMPER45.Overlap_STR.PWMPER5STR.Byte + #define PWMPER5_BIT _PWMPER45.Overlap_STR.PWMPER5STR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} PWMPER45STR; +extern volatile PWMPER45STR _PWMPER45 @(REG_BASE + 0x000000F6); +#define PWMPER45 _PWMPER45.Word +#define PWMPER45_BIT _PWMPER45.MergedBits.grpBIT + + +/*** PWMDTY01 - PWM Channel Duty 01 Register; 0x000000F8 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMDTY0 - PWM Channel Duty 0 Register; 0x000000F8 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMDTY0STR; + #define PWMDTY0 _PWMDTY01.Overlap_STR.PWMDTY0STR.Byte + #define PWMDTY0_BIT _PWMDTY01.Overlap_STR.PWMDTY0STR.MergedBits.grpBIT + + /*** PWMDTY1 - PWM Channel Duty 1 Register; 0x000000F9 ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMDTY1STR; + #define PWMDTY1 _PWMDTY01.Overlap_STR.PWMDTY1STR.Byte + #define PWMDTY1_BIT _PWMDTY01.Overlap_STR.PWMDTY1STR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} PWMDTY01STR; +extern volatile PWMDTY01STR _PWMDTY01 @(REG_BASE + 0x000000F8); +#define PWMDTY01 _PWMDTY01.Word +#define PWMDTY01_BIT _PWMDTY01.MergedBits.grpBIT + + +/*** PWMDTY23 - PWM Channel Duty 23 Register; 0x000000FA ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMDTY2 - PWM Channel Duty 2 Register; 0x000000FA ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMDTY2STR; + #define PWMDTY2 _PWMDTY23.Overlap_STR.PWMDTY2STR.Byte + #define PWMDTY2_BIT _PWMDTY23.Overlap_STR.PWMDTY2STR.MergedBits.grpBIT + + /*** PWMDTY3 - PWM Channel Duty 3 Register; 0x000000FB ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMDTY3STR; + #define PWMDTY3 _PWMDTY23.Overlap_STR.PWMDTY3STR.Byte + #define PWMDTY3_BIT _PWMDTY23.Overlap_STR.PWMDTY3STR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} PWMDTY23STR; +extern volatile PWMDTY23STR _PWMDTY23 @(REG_BASE + 0x000000FA); +#define PWMDTY23 _PWMDTY23.Word +#define PWMDTY23_BIT _PWMDTY23.MergedBits.grpBIT + + +/*** PWMDTY45 - PWM Channel Duty 45 Register; 0x000000FC ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMDTY4 - PWM Channel Duty 4 Register; 0x000000FC ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMDTY4STR; + #define PWMDTY4 _PWMDTY45.Overlap_STR.PWMDTY4STR.Byte + #define PWMDTY4_BIT _PWMDTY45.Overlap_STR.PWMDTY4STR.MergedBits.grpBIT + + /*** PWMDTY5 - PWM Channel Duty 5 Register; 0x000000FD ***/ + union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; + } PWMDTY5STR; + #define PWMDTY5 _PWMDTY45.Overlap_STR.PWMDTY5STR.Byte + #define PWMDTY5_BIT _PWMDTY45.Overlap_STR.PWMDTY5STR.MergedBits.grpBIT + + } Overlap_STR; + + struct { + word grpBIT :16; + } MergedBits; +} PWMDTY45STR; +extern volatile PWMDTY45STR _PWMDTY45 @(REG_BASE + 0x000000FC); +#define PWMDTY45 _PWMDTY45.Word +#define PWMDTY45_BIT _PWMDTY45.MergedBits.grpBIT + + +/*** PORTE - Port E Register; 0x00000008 ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* Port E Bit 0 */ + byte BIT1 :1; /* Port E Bit 1 */ + byte BIT2 :1; /* Port E Bit 2 */ + byte BIT3 :1; /* Port E Bit 3 */ + byte BIT4 :1; /* Port E Bit 4 */ + byte BIT5 :1; /* Port E Bit 5 */ + byte BIT6 :1; /* Port E Bit 6 */ + byte BIT7 :1; /* Port E Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} PORTESTR; +extern volatile PORTESTR _PORTE @(REG_BASE + 0x00000008); +#define PORTE _PORTE.Byte +#define PORTE_BIT0 _PORTE.Bits.BIT0 +#define PORTE_BIT1 _PORTE.Bits.BIT1 +#define PORTE_BIT2 _PORTE.Bits.BIT2 +#define PORTE_BIT3 _PORTE.Bits.BIT3 +#define PORTE_BIT4 _PORTE.Bits.BIT4 +#define PORTE_BIT5 _PORTE.Bits.BIT5 +#define PORTE_BIT6 _PORTE.Bits.BIT6 +#define PORTE_BIT7 _PORTE.Bits.BIT7 +#define PORTE_BIT _PORTE.MergedBits.grpBIT + + +/*** DDRE - Port E Data Direction Register; 0x00000009 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte BIT2 :1; /* Data Direction Port A Bit 2 */ + byte BIT3 :1; /* Data Direction Port A Bit 3 */ + byte BIT4 :1; /* Data Direction Port A Bit 4 */ + byte BIT5 :1; /* Data Direction Port A Bit 5 */ + byte BIT6 :1; /* Data Direction Port A Bit 6 */ + byte BIT7 :1; /* Data Direction Port A Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte grpBIT_2 :6; + } MergedBits; +} DDRESTR; +extern volatile DDRESTR _DDRE @(REG_BASE + 0x00000009); +#define DDRE _DDRE.Byte +#define DDRE_BIT2 _DDRE.Bits.BIT2 +#define DDRE_BIT3 _DDRE.Bits.BIT3 +#define DDRE_BIT4 _DDRE.Bits.BIT4 +#define DDRE_BIT5 _DDRE.Bits.BIT5 +#define DDRE_BIT6 _DDRE.Bits.BIT6 +#define DDRE_BIT7 _DDRE.Bits.BIT7 +#define DDRE_BIT_2 _DDRE.MergedBits.grpBIT_2 +#define DDRE_BIT DDRE_BIT_2 + + +/*** PEAR - Port E Assignment Register; 0x0000000A ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte RDWE :1; /* Read / Write Enable */ + byte LSTRE :1; /* Low Strobe (LSTRB) Enable */ + byte NECLK :1; /* No External E Clock */ + byte PIPOE :1; /* Pipe Status Signal Output Enable */ + byte :1; + byte NOACCE :1; /* CPU No Access Output Enable */ + } Bits; +} PEARSTR; +extern volatile PEARSTR _PEAR @(REG_BASE + 0x0000000A); +#define PEAR _PEAR.Byte +#define PEAR_RDWE _PEAR.Bits.RDWE +#define PEAR_LSTRE _PEAR.Bits.LSTRE +#define PEAR_NECLK _PEAR.Bits.NECLK +#define PEAR_PIPOE _PEAR.Bits.PIPOE +#define PEAR_NOACCE _PEAR.Bits.NOACCE + + +/*** MODE - Mode Register; 0x0000000B ***/ +typedef union { + byte Byte; + struct { + byte EME :1; /* Emulate Port E */ + byte EMK :1; /* Emulate Port K */ + byte :1; + byte IVIS :1; /* Internal Visibility */ + byte :1; + byte MODA :1; /* Mode Select Bit A */ + byte MODB :1; /* Mode Select Bit B */ + byte MODC :1; /* Mode Select Bit C */ + } Bits; +} MODESTR; +extern volatile MODESTR _MODE @(REG_BASE + 0x0000000B); +#define MODE _MODE.Byte +#define MODE_EME _MODE.Bits.EME +#define MODE_EMK _MODE.Bits.EMK +#define MODE_IVIS _MODE.Bits.IVIS +#define MODE_MODA _MODE.Bits.MODA +#define MODE_MODB _MODE.Bits.MODB +#define MODE_MODC _MODE.Bits.MODC + + +/*** PUCR - Pull-Up Control Register; 0x0000000C ***/ +typedef union { + byte Byte; + struct { + byte PUPAE :1; /* Pull-Up Port A Enable */ + byte PUPBE :1; /* Pull-Up Port B Enable */ + byte :1; + byte :1; + byte PUPEE :1; /* Pull-Up Port E Enable */ + byte :1; + byte :1; + byte PUPKE :1; /* Pull-Up Port K Enable */ + } Bits; +} PUCRSTR; +extern volatile PUCRSTR _PUCR @(REG_BASE + 0x0000000C); +#define PUCR _PUCR.Byte +#define PUCR_PUPAE _PUCR.Bits.PUPAE +#define PUCR_PUPBE _PUCR.Bits.PUPBE +#define PUCR_PUPEE _PUCR.Bits.PUPEE +#define PUCR_PUPKE _PUCR.Bits.PUPKE + + +/*** RDRIV - Reduced Drive of I/O Lines; 0x0000000D ***/ +typedef union { + byte Byte; + struct { + byte RDPA :1; /* Reduced Drive of Port A */ + byte RDPB :1; /* Reduced Drive of Port B */ + byte :1; + byte :1; + byte RDPE :1; /* Reduced Drive of Port E */ + byte :1; + byte :1; + byte RDPK :1; /* Reduced Drive of Port K */ + } Bits; +} RDRIVSTR; +extern volatile RDRIVSTR _RDRIV @(REG_BASE + 0x0000000D); +#define RDRIV _RDRIV.Byte +#define RDRIV_RDPA _RDRIV.Bits.RDPA +#define RDRIV_RDPB _RDRIV.Bits.RDPB +#define RDRIV_RDPE _RDRIV.Bits.RDPE +#define RDRIV_RDPK _RDRIV.Bits.RDPK + + +/*** EBICTL - External Bus Interface Control; 0x0000000E ***/ +typedef union { + byte Byte; + struct { + byte ESTR :1; /* E Stretches */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} EBICTLSTR; +extern volatile EBICTLSTR _EBICTL @(REG_BASE + 0x0000000E); +#define EBICTL _EBICTL.Byte +#define EBICTL_ESTR _EBICTL.Bits.ESTR + + +/*** INITRM - Initialization of Internal RAM Position Register; 0x00000010 ***/ +typedef union { + byte Byte; + struct { + byte RAMHAL :1; /* Internal RAM map alignment */ + byte :1; + byte :1; + byte RAM11 :1; /* Internal RAM map position Bit 11 */ + byte RAM12 :1; /* Internal RAM map position Bit 12 */ + byte RAM13 :1; /* Internal RAM map position Bit 13 */ + byte RAM14 :1; /* Internal RAM map position Bit 14 */ + byte RAM15 :1; /* Internal RAM map position Bit 15 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte grpRAM_11 :5; + } MergedBits; +} INITRMSTR; +extern volatile INITRMSTR _INITRM @(REG_BASE + 0x00000010); +#define INITRM _INITRM.Byte +#define INITRM_RAMHAL _INITRM.Bits.RAMHAL +#define INITRM_RAM11 _INITRM.Bits.RAM11 +#define INITRM_RAM12 _INITRM.Bits.RAM12 +#define INITRM_RAM13 _INITRM.Bits.RAM13 +#define INITRM_RAM14 _INITRM.Bits.RAM14 +#define INITRM_RAM15 _INITRM.Bits.RAM15 +#define INITRM_RAM_11 _INITRM.MergedBits.grpRAM_11 +#define INITRM_RAM INITRM_RAM_11 + + +/*** INITRG - Initialization of Internal Register Position Register; 0x00000011 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte REG11 :1; /* Internal register map position REG11 */ + byte REG12 :1; /* Internal register map position REG12 */ + byte REG13 :1; /* Internal register map position REG13 */ + byte REG14 :1; /* Internal register map position REG14 */ + byte :1; + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte grpREG_11 :4; + byte :1; + } MergedBits; +} INITRGSTR; +extern volatile INITRGSTR _INITRG @(REG_BASE + 0x00000011); +#define INITRG _INITRG.Byte +#define INITRG_REG11 _INITRG.Bits.REG11 +#define INITRG_REG12 _INITRG.Bits.REG12 +#define INITRG_REG13 _INITRG.Bits.REG13 +#define INITRG_REG14 _INITRG.Bits.REG14 +#define INITRG_REG_11 _INITRG.MergedBits.grpREG_11 +#define INITRG_REG INITRG_REG_11 + + +/*** INITEE - Initialization of Internal EEPROM Position Register; 0x00000012 ***/ +typedef union { + byte Byte; + struct { + byte EEON :1; /* Internal EEPROM On */ + byte :1; + byte :1; + byte :1; + byte EE12 :1; /* Internal EEPROM map position Bit 12 */ + byte EE13 :1; /* Internal EEPROM map position Bit 13 */ + byte EE14 :1; /* Internal EEPROM map position Bit 14 */ + byte EE15 :1; /* Internal EEPROM map position Bit 15 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte grpEE_12 :4; + } MergedBits; +} INITEESTR; +extern volatile INITEESTR _INITEE @(REG_BASE + 0x00000012); +#define INITEE _INITEE.Byte +#define INITEE_EEON _INITEE.Bits.EEON +#define INITEE_EE12 _INITEE.Bits.EE12 +#define INITEE_EE13 _INITEE.Bits.EE13 +#define INITEE_EE14 _INITEE.Bits.EE14 +#define INITEE_EE15 _INITEE.Bits.EE15 +#define INITEE_EE_12 _INITEE.MergedBits.grpEE_12 +#define INITEE_EE INITEE_EE_12 + + +/*** MISC - Miscellaneous Mapping Control Register; 0x00000013 ***/ +typedef union { + byte Byte; + struct { + byte ROMON :1; /* Enable Flash EEPROM */ + byte ROMHM :1; /* Flash EEPROM only in second half of memory map */ + byte EXSTR0 :1; /* External Access Stretch Bit 0 */ + byte EXSTR1 :1; /* External Access Stretch Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte :1; + byte :1; + byte grpEXSTR :2; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} MISCSTR; +extern volatile MISCSTR _MISC @(REG_BASE + 0x00000013); +#define MISC _MISC.Byte +#define MISC_ROMON _MISC.Bits.ROMON +#define MISC_ROMHM _MISC.Bits.ROMHM +#define MISC_EXSTR0 _MISC.Bits.EXSTR0 +#define MISC_EXSTR1 _MISC.Bits.EXSTR1 +#define MISC_EXSTR _MISC.MergedBits.grpEXSTR + + +/*** MTST0 - MTST0; 0x00000014 ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* MTST0 Bit 0 */ + byte BIT1 :1; /* MTST0 Bit 1 */ + byte BIT2 :1; /* MTST0 Bit 2 */ + byte BIT3 :1; /* MTST0 Bit 3 */ + byte BIT4 :1; /* MTST0 Bit 4 */ + byte BIT5 :1; /* MTST0 Bit 5 */ + byte BIT6 :1; /* MTST0 Bit 6 */ + byte BIT7 :1; /* MTST0 Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} MTST0STR; +extern volatile MTST0STR _MTST0 @(REG_BASE + 0x00000014); +#define MTST0 _MTST0.Byte +#define MTST0_BIT0 _MTST0.Bits.BIT0 +#define MTST0_BIT1 _MTST0.Bits.BIT1 +#define MTST0_BIT2 _MTST0.Bits.BIT2 +#define MTST0_BIT3 _MTST0.Bits.BIT3 +#define MTST0_BIT4 _MTST0.Bits.BIT4 +#define MTST0_BIT5 _MTST0.Bits.BIT5 +#define MTST0_BIT6 _MTST0.Bits.BIT6 +#define MTST0_BIT7 _MTST0.Bits.BIT7 +#define MTST0_BIT _MTST0.MergedBits.grpBIT + + +/*** ITCR - Interrupt Test Control Register; 0x00000015 ***/ +typedef union { + byte Byte; + struct { + byte ADR0 :1; /* Test register select Bit 0 */ + byte ADR1 :1; /* Test register select Bit 1 */ + byte ADR2 :1; /* Test register select Bit 2 */ + byte ADR3 :1; /* Test register select Bit 3 */ + byte WRTINT :1; /* Write to the Interrupt Test Registers */ + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpADR :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} ITCRSTR; +extern volatile ITCRSTR _ITCR @(REG_BASE + 0x00000015); +#define ITCR _ITCR.Byte +#define ITCR_ADR0 _ITCR.Bits.ADR0 +#define ITCR_ADR1 _ITCR.Bits.ADR1 +#define ITCR_ADR2 _ITCR.Bits.ADR2 +#define ITCR_ADR3 _ITCR.Bits.ADR3 +#define ITCR_WRTINT _ITCR.Bits.WRTINT +#define ITCR_ADR _ITCR.MergedBits.grpADR + + +/*** ITEST - Interrupt Test Register; 0x00000016 ***/ +typedef union { + byte Byte; + struct { + byte INT0 :1; /* Interrupt Test Register Bit 0 */ + byte INT2 :1; /* Interrupt Test Register Bit 1 */ + byte INT4 :1; /* Interrupt Test Register Bit 2 */ + byte INT6 :1; /* Interrupt Test Register Bit 3 */ + byte INT8 :1; /* Interrupt Test Register Bit 4 */ + byte INTA :1; /* Interrupt Test Register Bit 5 */ + byte INTC :1; /* Interrupt Test Register Bit 6 */ + byte INTE :1; /* Interrupt Test Register Bit 7 */ + } Bits; +} ITESTSTR; +extern volatile ITESTSTR _ITEST @(REG_BASE + 0x00000016); +#define ITEST _ITEST.Byte +#define ITEST_INT0 _ITEST.Bits.INT0 +#define ITEST_INT2 _ITEST.Bits.INT2 +#define ITEST_INT4 _ITEST.Bits.INT4 +#define ITEST_INT6 _ITEST.Bits.INT6 +#define ITEST_INT8 _ITEST.Bits.INT8 +#define ITEST_INTA _ITEST.Bits.INTA +#define ITEST_INTC _ITEST.Bits.INTC +#define ITEST_INTE _ITEST.Bits.INTE + + +/*** MTST1 - MTST1; 0x00000017 ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* MTST1 Bit 0 */ + byte BIT1 :1; /* MTST1 Bit 1 */ + byte BIT2 :1; /* MTST1 Bit 2 */ + byte BIT3 :1; /* MTST1 Bit 3 */ + byte BIT4 :1; /* MTST1 Bit 4 */ + byte BIT5 :1; /* MTST1 Bit 5 */ + byte BIT6 :1; /* MTST1 Bit 6 */ + byte BIT7 :1; /* MTST1 Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} MTST1STR; +extern volatile MTST1STR _MTST1 @(REG_BASE + 0x00000017); +#define MTST1 _MTST1.Byte +#define MTST1_BIT0 _MTST1.Bits.BIT0 +#define MTST1_BIT1 _MTST1.Bits.BIT1 +#define MTST1_BIT2 _MTST1.Bits.BIT2 +#define MTST1_BIT3 _MTST1.Bits.BIT3 +#define MTST1_BIT4 _MTST1.Bits.BIT4 +#define MTST1_BIT5 _MTST1.Bits.BIT5 +#define MTST1_BIT6 _MTST1.Bits.BIT6 +#define MTST1_BIT7 _MTST1.Bits.BIT7 +#define MTST1_BIT _MTST1.MergedBits.grpBIT + + +/*** PARTIDH - Part ID Register High; 0x0000001A ***/ +typedef union { + byte Byte; + struct { + byte ID15 :1; /* Part ID Register Bit 15 */ + byte ID14 :1; /* Part ID Register Bit 14 */ + byte ID13 :1; /* Part ID Register Bit 13 */ + byte ID12 :1; /* Part ID Register Bit 12 */ + byte ID11 :1; /* Part ID Register Bit 11 */ + byte ID10 :1; /* Part ID Register Bit 10 */ + byte ID9 :1; /* Part ID Register Bit 9 */ + byte ID8 :1; /* Part ID Register Bit 8 */ + } Bits; +} PARTIDHSTR; +extern volatile PARTIDHSTR _PARTIDH @(REG_BASE + 0x0000001A); +#define PARTIDH _PARTIDH.Byte +#define PARTIDH_ID15 _PARTIDH.Bits.ID15 +#define PARTIDH_ID14 _PARTIDH.Bits.ID14 +#define PARTIDH_ID13 _PARTIDH.Bits.ID13 +#define PARTIDH_ID12 _PARTIDH.Bits.ID12 +#define PARTIDH_ID11 _PARTIDH.Bits.ID11 +#define PARTIDH_ID10 _PARTIDH.Bits.ID10 +#define PARTIDH_ID9 _PARTIDH.Bits.ID9 +#define PARTIDH_ID8 _PARTIDH.Bits.ID8 + + +/*** PARTIDL - Part ID Register Low; 0x0000001B ***/ +typedef union { + byte Byte; + struct { + byte ID0 :1; /* Part ID Register Bit 0 */ + byte ID1 :1; /* Part ID Register Bit 1 */ + byte ID2 :1; /* Part ID Register Bit 2 */ + byte ID3 :1; /* Part ID Register Bit 3 */ + byte ID4 :1; /* Part ID Register Bit 4 */ + byte ID5 :1; /* Part ID Register Bit 5 */ + byte ID6 :1; /* Part ID Register Bit 6 */ + byte ID7 :1; /* Part ID Register Bit 7 */ + } Bits; + struct { + byte grpID :8; + } MergedBits; +} PARTIDLSTR; +extern volatile PARTIDLSTR _PARTIDL @(REG_BASE + 0x0000001B); +#define PARTIDL _PARTIDL.Byte +#define PARTIDL_ID0 _PARTIDL.Bits.ID0 +#define PARTIDL_ID1 _PARTIDL.Bits.ID1 +#define PARTIDL_ID2 _PARTIDL.Bits.ID2 +#define PARTIDL_ID3 _PARTIDL.Bits.ID3 +#define PARTIDL_ID4 _PARTIDL.Bits.ID4 +#define PARTIDL_ID5 _PARTIDL.Bits.ID5 +#define PARTIDL_ID6 _PARTIDL.Bits.ID6 +#define PARTIDL_ID7 _PARTIDL.Bits.ID7 +#define PARTIDL_ID _PARTIDL.MergedBits.grpID + + +/*** MEMSIZ0 - Memory Size Register Zero; 0x0000001C ***/ +typedef union { + byte Byte; + struct { + byte ram_sw0 :1; /* Allocated RAM Memory Space Bit 0 */ + byte ram_sw1 :1; /* Allocated RAM Memory Space Bit 1 */ + byte ram_sw2 :1; /* Allocated RAM Memory Space Bit 2 */ + byte :1; + byte eep_sw0 :1; /* Allocated EEPROM Memory Space Bit 0 */ + byte eep_sw1 :1; /* Allocated EEPROM Memory Space Bit 1 */ + byte :1; + byte reg_sw0 :1; /* Allocated System Register Space */ + } Bits; + struct { + byte grpram_sw :3; + byte :1; + byte grpeep_sw :2; + byte :1; + byte grpreg_sw :1; + } MergedBits; +} MEMSIZ0STR; +extern volatile MEMSIZ0STR _MEMSIZ0 @(REG_BASE + 0x0000001C); +#define MEMSIZ0 _MEMSIZ0.Byte +#define MEMSIZ0_ram_sw0 _MEMSIZ0.Bits.ram_sw0 +#define MEMSIZ0_ram_sw1 _MEMSIZ0.Bits.ram_sw1 +#define MEMSIZ0_ram_sw2 _MEMSIZ0.Bits.ram_sw2 +#define MEMSIZ0_eep_sw0 _MEMSIZ0.Bits.eep_sw0 +#define MEMSIZ0_eep_sw1 _MEMSIZ0.Bits.eep_sw1 +#define MEMSIZ0_reg_sw0 _MEMSIZ0.Bits.reg_sw0 +#define MEMSIZ0_ram_sw _MEMSIZ0.MergedBits.grpram_sw +#define MEMSIZ0_eep_sw _MEMSIZ0.MergedBits.grpeep_sw + + +/*** MEMSIZ1 - Memory Size Register One; 0x0000001D ***/ +typedef union { + byte Byte; + struct { + byte pag_sw0 :1; /* Allocated Off-Chip Memory Options Bit 0 */ + byte pag_sw1 :1; /* Allocated Off-Chip Memory Options Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte rom_sw0 :1; /* Allocated Flash EEPROM/ROM Physical Memory Space Bit 0 */ + byte rom_sw1 :1; /* Allocated Flash EEPROM/ROM Physical Memory Space Bit 1 */ + } Bits; + struct { + byte grppag_sw :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte grprom_sw :2; + } MergedBits; +} MEMSIZ1STR; +extern volatile MEMSIZ1STR _MEMSIZ1 @(REG_BASE + 0x0000001D); +#define MEMSIZ1 _MEMSIZ1.Byte +#define MEMSIZ1_pag_sw0 _MEMSIZ1.Bits.pag_sw0 +#define MEMSIZ1_pag_sw1 _MEMSIZ1.Bits.pag_sw1 +#define MEMSIZ1_rom_sw0 _MEMSIZ1.Bits.rom_sw0 +#define MEMSIZ1_rom_sw1 _MEMSIZ1.Bits.rom_sw1 +#define MEMSIZ1_pag_sw _MEMSIZ1.MergedBits.grppag_sw +#define MEMSIZ1_rom_sw _MEMSIZ1.MergedBits.grprom_sw + + +/*** INTCR - Interrupt Control Register; 0x0000001E ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte IRQEN :1; /* External IRQ Enable */ + byte IRQE :1; /* IRQ Select Edge Sensitive Only */ + } Bits; +} INTCRSTR; +extern volatile INTCRSTR _INTCR @(REG_BASE + 0x0000001E); +#define INTCR _INTCR.Byte +#define INTCR_IRQEN _INTCR.Bits.IRQEN +#define INTCR_IRQE _INTCR.Bits.IRQE + + +/*** HPRIO - Highest Priority I Interrupt; 0x0000001F ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte PSEL1 :1; /* Highest Priority I Interrupt Bit 1 */ + byte PSEL2 :1; /* Highest Priority I Interrupt Bit 2 */ + byte PSEL3 :1; /* Highest Priority I Interrupt Bit 3 */ + byte PSEL4 :1; /* Highest Priority I Interrupt Bit 4 */ + byte PSEL5 :1; /* Highest Priority I Interrupt Bit 5 */ + byte PSEL6 :1; /* Highest Priority I Interrupt Bit 6 */ + byte PSEL7 :1; /* Highest Priority I Interrupt Bit 7 */ + } Bits; + struct { + byte :1; + byte grpPSEL_1 :7; + } MergedBits; +} HPRIOSTR; +extern volatile HPRIOSTR _HPRIO @(REG_BASE + 0x0000001F); +#define HPRIO _HPRIO.Byte +#define HPRIO_PSEL1 _HPRIO.Bits.PSEL1 +#define HPRIO_PSEL2 _HPRIO.Bits.PSEL2 +#define HPRIO_PSEL3 _HPRIO.Bits.PSEL3 +#define HPRIO_PSEL4 _HPRIO.Bits.PSEL4 +#define HPRIO_PSEL5 _HPRIO.Bits.PSEL5 +#define HPRIO_PSEL6 _HPRIO.Bits.PSEL6 +#define HPRIO_PSEL7 _HPRIO.Bits.PSEL7 +#define HPRIO_PSEL_1 _HPRIO.MergedBits.grpPSEL_1 +#define HPRIO_PSEL HPRIO_PSEL_1 + + +/*** BKPCT0 - Breakpoint Control Register 0; 0x00000028 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte BKTAG :1; /* Breakpoint on Tag */ + byte BKBDM :1; /* Breakpoint Background Debug Mode Enable */ + byte BKFULL :1; /* Full Breakpoint Mode Enable */ + byte BKEN :1; /* Breakpoint Enable */ + } Bits; +} BKPCT0STR; +extern volatile BKPCT0STR _BKPCT0 @(REG_BASE + 0x00000028); +#define BKPCT0 _BKPCT0.Byte +#define BKPCT0_BKTAG _BKPCT0.Bits.BKTAG +#define BKPCT0_BKBDM _BKPCT0.Bits.BKBDM +#define BKPCT0_BKFULL _BKPCT0.Bits.BKFULL +#define BKPCT0_BKEN _BKPCT0.Bits.BKEN + + +/*** BKPCT1 - Breakpoint Control Register 1; 0x00000029 ***/ +typedef union { + byte Byte; + struct { + byte BK1RW :1; /* R/W Compare Value 1 */ + byte BK1RWE :1; /* R/W Compare Enable 1 */ + byte BK0RW :1; /* R/W Compare Value 0 */ + byte BK0RWE :1; /* R/W Compare Enable 0 */ + byte BK1MBL :1; /* Breakpoint Mask Low Byte for Second Address */ + byte BK1MBH :1; /* Breakpoint Mask High Byte for Second Address */ + byte BK0MBL :1; /* Breakpoint Mask Low Byte for First Address */ + byte BK0MBH :1; /* Breakpoint Mask High Byte for First Address */ + } Bits; +} BKPCT1STR; +extern volatile BKPCT1STR _BKPCT1 @(REG_BASE + 0x00000029); +#define BKPCT1 _BKPCT1.Byte +#define BKPCT1_BK1RW _BKPCT1.Bits.BK1RW +#define BKPCT1_BK1RWE _BKPCT1.Bits.BK1RWE +#define BKPCT1_BK0RW _BKPCT1.Bits.BK0RW +#define BKPCT1_BK0RWE _BKPCT1.Bits.BK0RWE +#define BKPCT1_BK1MBL _BKPCT1.Bits.BK1MBL +#define BKPCT1_BK1MBH _BKPCT1.Bits.BK1MBH +#define BKPCT1_BK0MBL _BKPCT1.Bits.BK0MBL +#define BKPCT1_BK0MBH _BKPCT1.Bits.BK0MBH + + +/*** BKP0X - First Address Memory Expansion Breakpoint Register; 0x0000002A ***/ +typedef union { + byte Byte; + struct { + byte BK0V0 :1; /* First Address Breakpoint Expansion Address Value Bit 0 */ + byte BK0V1 :1; /* First Address Breakpoint Expansion Address Value Bit 1 */ + byte BK0V2 :1; /* First Address Breakpoint Expansion Address Value Bit 2 */ + byte BK0V3 :1; /* First Address Breakpoint Expansion Address Value Bit 3 */ + byte BK0V4 :1; /* First Address Breakpoint Expansion Address Value Bit 4 */ + byte BK0V5 :1; /* First Address Breakpoint Expansion Address Value Bit 5 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpBK0V :6; + byte :1; + byte :1; + } MergedBits; +} BKP0XSTR; +extern volatile BKP0XSTR _BKP0X @(REG_BASE + 0x0000002A); +#define BKP0X _BKP0X.Byte +#define BKP0X_BK0V0 _BKP0X.Bits.BK0V0 +#define BKP0X_BK0V1 _BKP0X.Bits.BK0V1 +#define BKP0X_BK0V2 _BKP0X.Bits.BK0V2 +#define BKP0X_BK0V3 _BKP0X.Bits.BK0V3 +#define BKP0X_BK0V4 _BKP0X.Bits.BK0V4 +#define BKP0X_BK0V5 _BKP0X.Bits.BK0V5 +#define BKP0X_BK0V _BKP0X.MergedBits.grpBK0V + + +/*** BKP0H - First Address High Byte Breakpoint Register; 0x0000002B ***/ +typedef union { + byte Byte; + struct { + byte BIT8 :1; /* First Address Breakpoint Register Bit 8 */ + byte BIT9 :1; /* First Address Breakpoint Register Bit 9 */ + byte BIT10 :1; /* First Address Breakpoint Register Bit 10 */ + byte BIT11 :1; /* First Address Breakpoint Register Bit 11 */ + byte BIT12 :1; /* First Address Breakpoint Register Bit 12 */ + byte BIT13 :1; /* First Address Breakpoint Register Bit 13 */ + byte BIT14 :1; /* First Address Breakpoint Register Bit 14 */ + byte BIT15 :1; /* First Address Breakpoint Register Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; +} BKP0HSTR; +extern volatile BKP0HSTR _BKP0H @(REG_BASE + 0x0000002B); +#define BKP0H _BKP0H.Byte +#define BKP0H_BIT8 _BKP0H.Bits.BIT8 +#define BKP0H_BIT9 _BKP0H.Bits.BIT9 +#define BKP0H_BIT10 _BKP0H.Bits.BIT10 +#define BKP0H_BIT11 _BKP0H.Bits.BIT11 +#define BKP0H_BIT12 _BKP0H.Bits.BIT12 +#define BKP0H_BIT13 _BKP0H.Bits.BIT13 +#define BKP0H_BIT14 _BKP0H.Bits.BIT14 +#define BKP0H_BIT15 _BKP0H.Bits.BIT15 +#define BKP0H_BIT_8 _BKP0H.MergedBits.grpBIT_8 +#define BKP0H_BIT BKP0H_BIT_8 + + +/*** BKP0L - First Address Low Byte Breakpoint Register; 0x0000002C ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* First Address Breakpoint Register Bit 0 */ + byte BIT1 :1; /* First Address Breakpoint Register Bit 1 */ + byte BIT2 :1; /* First Address Breakpoint Register Bit 2 */ + byte BIT3 :1; /* First Address Breakpoint Register Bit 3 */ + byte BIT4 :1; /* First Address Breakpoint Register Bit 4 */ + byte BIT5 :1; /* First Address Breakpoint Register Bit 5 */ + byte BIT6 :1; /* First Address Breakpoint Register Bit 6 */ + byte BIT7 :1; /* First Address Breakpoint Register Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} BKP0LSTR; +extern volatile BKP0LSTR _BKP0L @(REG_BASE + 0x0000002C); +#define BKP0L _BKP0L.Byte +#define BKP0L_BIT0 _BKP0L.Bits.BIT0 +#define BKP0L_BIT1 _BKP0L.Bits.BIT1 +#define BKP0L_BIT2 _BKP0L.Bits.BIT2 +#define BKP0L_BIT3 _BKP0L.Bits.BIT3 +#define BKP0L_BIT4 _BKP0L.Bits.BIT4 +#define BKP0L_BIT5 _BKP0L.Bits.BIT5 +#define BKP0L_BIT6 _BKP0L.Bits.BIT6 +#define BKP0L_BIT7 _BKP0L.Bits.BIT7 +#define BKP0L_BIT _BKP0L.MergedBits.grpBIT + + +/*** BKP1X - Second Address Memory Expansion Breakpoint Register; 0x0000002D ***/ +typedef union { + byte Byte; + struct { + byte BK1V0 :1; /* Second Address Breakpoint Expansion Address Value Bit 0 */ + byte BK1V1 :1; /* Second Address Breakpoint Expansion Address Value Bit 1 */ + byte BK1V2 :1; /* Second Address Breakpoint Expansion Address Value Bit 2 */ + byte BK1V3 :1; /* Second Address Breakpoint Expansion Address Value Bit 3 */ + byte BK1V4 :1; /* Second Address Breakpoint Expansion Address Value Bit 4 */ + byte BK1V5 :1; /* Second Address Breakpoint Expansion Address Value Bit 5 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpBK1V :6; + byte :1; + byte :1; + } MergedBits; +} BKP1XSTR; +extern volatile BKP1XSTR _BKP1X @(REG_BASE + 0x0000002D); +#define BKP1X _BKP1X.Byte +#define BKP1X_BK1V0 _BKP1X.Bits.BK1V0 +#define BKP1X_BK1V1 _BKP1X.Bits.BK1V1 +#define BKP1X_BK1V2 _BKP1X.Bits.BK1V2 +#define BKP1X_BK1V3 _BKP1X.Bits.BK1V3 +#define BKP1X_BK1V4 _BKP1X.Bits.BK1V4 +#define BKP1X_BK1V5 _BKP1X.Bits.BK1V5 +#define BKP1X_BK1V _BKP1X.MergedBits.grpBK1V + + +/*** BKP1H - Data (Second Address) High Byte Breakpoint Register; 0x0000002E ***/ +typedef union { + byte Byte; + struct { + byte BIT8 :1; /* Data (Second Address) Breakpoint Register Bit 8 */ + byte BIT9 :1; /* Data (Second Address) Breakpoint Register Bit 9 */ + byte BIT10 :1; /* Data (Second Address) Breakpoint Register Bit 10 */ + byte BIT11 :1; /* Data (Second Address) Breakpoint Register Bit 11 */ + byte BIT12 :1; /* Data (Second Address) Breakpoint Register Bit 12 */ + byte BIT13 :1; /* Data (Second Address) Breakpoint Register Bit 13 */ + byte BIT14 :1; /* Data (Second Address) Breakpoint Register Bit 14 */ + byte BIT15 :1; /* Data (Second Address) Breakpoint Register Bit 15 */ + } Bits; + struct { + byte grpBIT_8 :8; + } MergedBits; +} BKP1HSTR; +extern volatile BKP1HSTR _BKP1H @(REG_BASE + 0x0000002E); +#define BKP1H _BKP1H.Byte +#define BKP1H_BIT8 _BKP1H.Bits.BIT8 +#define BKP1H_BIT9 _BKP1H.Bits.BIT9 +#define BKP1H_BIT10 _BKP1H.Bits.BIT10 +#define BKP1H_BIT11 _BKP1H.Bits.BIT11 +#define BKP1H_BIT12 _BKP1H.Bits.BIT12 +#define BKP1H_BIT13 _BKP1H.Bits.BIT13 +#define BKP1H_BIT14 _BKP1H.Bits.BIT14 +#define BKP1H_BIT15 _BKP1H.Bits.BIT15 +#define BKP1H_BIT_8 _BKP1H.MergedBits.grpBIT_8 +#define BKP1H_BIT BKP1H_BIT_8 + + +/*** BKP1L - Data (Second Address) Low Byte Breakpoint Register; 0x0000002F ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* Data (Second Address) Breakpoint Register Bit 0 */ + byte BIT1 :1; /* Data (Second Address) Breakpoint Register Bit 1 */ + byte BIT2 :1; /* Data (Second Address) Breakpoint Register Bit 2 */ + byte BIT3 :1; /* Data (Second Address) Breakpoint Register Bit 3 */ + byte BIT4 :1; /* Data (Second Address) Breakpoint Register Bit 4 */ + byte BIT5 :1; /* Data (Second Address) Breakpoint Register Bit 5 */ + byte BIT6 :1; /* Data (Second Address) Breakpoint Register Bit 6 */ + byte BIT7 :1; /* Data (Second Address) Breakpoint Register Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} BKP1LSTR; +extern volatile BKP1LSTR _BKP1L @(REG_BASE + 0x0000002F); +#define BKP1L _BKP1L.Byte +#define BKP1L_BIT0 _BKP1L.Bits.BIT0 +#define BKP1L_BIT1 _BKP1L.Bits.BIT1 +#define BKP1L_BIT2 _BKP1L.Bits.BIT2 +#define BKP1L_BIT3 _BKP1L.Bits.BIT3 +#define BKP1L_BIT4 _BKP1L.Bits.BIT4 +#define BKP1L_BIT5 _BKP1L.Bits.BIT5 +#define BKP1L_BIT6 _BKP1L.Bits.BIT6 +#define BKP1L_BIT7 _BKP1L.Bits.BIT7 +#define BKP1L_BIT _BKP1L.MergedBits.grpBIT + + +/*** PPAGE - Page Index Register; 0x00000030 ***/ +typedef union { + byte Byte; + struct { + byte PIX0 :1; /* Page Index Register Bit 0 */ + byte PIX1 :1; /* Page Index Register Bit 1 */ + byte PIX2 :1; /* Page Index Register Bit 2 */ + byte PIX3 :1; /* Page Index Register Bit 3 */ + byte PIX4 :1; /* Page Index Register Bit 4 */ + byte PIX5 :1; /* Page Index Register Bit 5 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpPIX :6; + byte :1; + byte :1; + } MergedBits; +} PPAGESTR; +extern volatile PPAGESTR _PPAGE @(REG_BASE + 0x00000030); +#define PPAGE _PPAGE.Byte +#define PPAGE_PIX0 _PPAGE.Bits.PIX0 +#define PPAGE_PIX1 _PPAGE.Bits.PIX1 +#define PPAGE_PIX2 _PPAGE.Bits.PIX2 +#define PPAGE_PIX3 _PPAGE.Bits.PIX3 +#define PPAGE_PIX4 _PPAGE.Bits.PIX4 +#define PPAGE_PIX5 _PPAGE.Bits.PIX5 +#define PPAGE_PIX _PPAGE.MergedBits.grpPIX + + +/*** PORTK - Port K Data Register; 0x00000032 ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* Port K Bit 0, XAB14 */ + byte BIT1 :1; /* Port K Bit 1, XAB15 */ + byte BIT2 :1; /* Port K Bit 2, XAB16 */ + byte BIT3 :1; /* Port K Bit 3, XAB17 */ + byte BIT4 :1; /* Port K Bit 4, XAB18 */ + byte BIT5 :1; /* Port K Bit 5, XAB19 */ + byte BIT6 :1; /* Port K Bit 6 */ + byte BIT7 :1; /* Port K Bit 7, ECS/ROMONE */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} PORTKSTR; +extern volatile PORTKSTR _PORTK @(REG_BASE + 0x00000032); +#define PORTK _PORTK.Byte +#define PORTK_BIT0 _PORTK.Bits.BIT0 +#define PORTK_BIT1 _PORTK.Bits.BIT1 +#define PORTK_BIT2 _PORTK.Bits.BIT2 +#define PORTK_BIT3 _PORTK.Bits.BIT3 +#define PORTK_BIT4 _PORTK.Bits.BIT4 +#define PORTK_BIT5 _PORTK.Bits.BIT5 +#define PORTK_BIT6 _PORTK.Bits.BIT6 +#define PORTK_BIT7 _PORTK.Bits.BIT7 +#define PORTK_BIT _PORTK.MergedBits.grpBIT + + +/*** DDRK - Port K Data Direction Register; 0x00000033 ***/ +typedef union { + byte Byte; + struct { + byte DDK0 :1; /* Port K Data Direction Bit 0 */ + byte DDK1 :1; /* Port K Data Direction Bit 1 */ + byte DDK2 :1; /* Port K Data Direction Bit 2 */ + byte DDK3 :1; /* Port K Data Direction Bit 3 */ + byte DDK4 :1; /* Port K Data Direction Bit 4 */ + byte DDK5 :1; /* Port K Data Direction Bit 5 */ + byte :1; + byte DDK7 :1; /* Port K Data Direction Bit 7 */ + } Bits; + struct { + byte grpDDK :6; + byte :1; + byte grpDDK_7 :1; + } MergedBits; +} DDRKSTR; +extern volatile DDRKSTR _DDRK @(REG_BASE + 0x00000033); +#define DDRK _DDRK.Byte +#define DDRK_DDK0 _DDRK.Bits.DDK0 +#define DDRK_DDK1 _DDRK.Bits.DDK1 +#define DDRK_DDK2 _DDRK.Bits.DDK2 +#define DDRK_DDK3 _DDRK.Bits.DDK3 +#define DDRK_DDK4 _DDRK.Bits.DDK4 +#define DDRK_DDK5 _DDRK.Bits.DDK5 +#define DDRK_DDK7 _DDRK.Bits.DDK7 +#define DDRK_DDK _DDRK.MergedBits.grpDDK + + +/*** SYNR - CRG Synthesizer Register; 0x00000034 ***/ +typedef union { + byte Byte; + struct { + byte SYN0 :1; /* CRG Synthesizer Bit 0 */ + byte SYN1 :1; /* CRG Synthesizer Bit 1 */ + byte SYN2 :1; /* CRG Synthesizer Bit 2 */ + byte SYN3 :1; /* CRG Synthesizer Bit 3 */ + byte SYN4 :1; /* CRG Synthesizer Bit 4 */ + byte SYN5 :1; /* CRG Synthesizer Bit 5 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpSYN :6; + byte :1; + byte :1; + } MergedBits; +} SYNRSTR; +extern volatile SYNRSTR _SYNR @(REG_BASE + 0x00000034); +#define SYNR _SYNR.Byte +#define SYNR_SYN0 _SYNR.Bits.SYN0 +#define SYNR_SYN1 _SYNR.Bits.SYN1 +#define SYNR_SYN2 _SYNR.Bits.SYN2 +#define SYNR_SYN3 _SYNR.Bits.SYN3 +#define SYNR_SYN4 _SYNR.Bits.SYN4 +#define SYNR_SYN5 _SYNR.Bits.SYN5 +#define SYNR_SYN _SYNR.MergedBits.grpSYN + + +/*** REFDV - CRG Reference Divider Register; 0x00000035 ***/ +typedef union { + byte Byte; + struct { + byte REFDV0 :1; /* CRG Reference Divider Bit 0 */ + byte REFDV1 :1; /* CRG Reference Divider Bit 1 */ + byte REFDV2 :1; /* CRG Reference Divider Bit 2 */ + byte REFDV3 :1; /* CRG Reference Divider Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpREFDV :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} REFDVSTR; +extern volatile REFDVSTR _REFDV @(REG_BASE + 0x00000035); +#define REFDV _REFDV.Byte +#define REFDV_REFDV0 _REFDV.Bits.REFDV0 +#define REFDV_REFDV1 _REFDV.Bits.REFDV1 +#define REFDV_REFDV2 _REFDV.Bits.REFDV2 +#define REFDV_REFDV3 _REFDV.Bits.REFDV3 +#define REFDV_REFDV _REFDV.MergedBits.grpREFDV + + +/*** CTFLG - CRG Test Flags Register; 0x00000036 ***/ +typedef union { + byte Byte; + struct { + byte TOUT0 :1; /* CRG Test Flags Bit 0 */ + byte TOUT1 :1; /* CRG Test Flags Bit 1 */ + byte TOUT2 :1; /* CRG Test Flags Bit 2 */ + byte TOUT3 :1; /* CRG Test Flags Bit 3 */ + byte TOUT4 :1; /* CRG Test Flags Bit 4 */ + byte TOUT5 :1; /* CRG Test Flags Bit 5 */ + byte TOUT6 :1; /* CRG Test Flags Bit 6 */ + byte TOUT7 :1; /* CRG Test Flags Bit 7 */ + } Bits; + struct { + byte grpTOUT :8; + } MergedBits; +} CTFLGSTR; +extern volatile CTFLGSTR _CTFLG @(REG_BASE + 0x00000036); +#define CTFLG _CTFLG.Byte +#define CTFLG_TOUT0 _CTFLG.Bits.TOUT0 +#define CTFLG_TOUT1 _CTFLG.Bits.TOUT1 +#define CTFLG_TOUT2 _CTFLG.Bits.TOUT2 +#define CTFLG_TOUT3 _CTFLG.Bits.TOUT3 +#define CTFLG_TOUT4 _CTFLG.Bits.TOUT4 +#define CTFLG_TOUT5 _CTFLG.Bits.TOUT5 +#define CTFLG_TOUT6 _CTFLG.Bits.TOUT6 +#define CTFLG_TOUT7 _CTFLG.Bits.TOUT7 +#define CTFLG_TOUT _CTFLG.MergedBits.grpTOUT + + +/*** CRGFLG - CRG Flags Register; 0x00000037 ***/ +typedef union { + byte Byte; + struct { + byte SCM :1; /* Self-clock mode Status */ + byte SCMIF :1; /* Self-clock mode Interrupt Flag */ + byte TRACK :1; /* Track Status */ + byte LOCK :1; /* Lock Status */ + byte LOCKIF :1; /* PLL Lock Interrupt Flag */ + byte :1; + byte PORF :1; /* Power on Reset Flag */ + byte RTIF :1; /* Real Time Interrupt Flag */ + } Bits; +} CRGFLGSTR; +extern volatile CRGFLGSTR _CRGFLG @(REG_BASE + 0x00000037); +#define CRGFLG _CRGFLG.Byte +#define CRGFLG_SCM _CRGFLG.Bits.SCM +#define CRGFLG_SCMIF _CRGFLG.Bits.SCMIF +#define CRGFLG_TRACK _CRGFLG.Bits.TRACK +#define CRGFLG_LOCK _CRGFLG.Bits.LOCK +#define CRGFLG_LOCKIF _CRGFLG.Bits.LOCKIF +#define CRGFLG_PORF _CRGFLG.Bits.PORF +#define CRGFLG_RTIF _CRGFLG.Bits.RTIF + + +/*** CRGINT - CRG Interrupt Enable Register; 0x00000038 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte SCMIE :1; /* Self-clock mode Interrupt Enable */ + byte :1; + byte :1; + byte LOCKIE :1; /* Lock Interrupt Enable */ + byte :1; + byte :1; + byte RTIE :1; /* Real Time Interrupt Enable */ + } Bits; +} CRGINTSTR; +extern volatile CRGINTSTR _CRGINT @(REG_BASE + 0x00000038); +#define CRGINT _CRGINT.Byte +#define CRGINT_SCMIE _CRGINT.Bits.SCMIE +#define CRGINT_LOCKIE _CRGINT.Bits.LOCKIE +#define CRGINT_RTIE _CRGINT.Bits.RTIE + + +/*** CLKSEL - CRG Clock Select Register; 0x00000039 ***/ +typedef union { + byte Byte; + struct { + byte COPWAI :1; /* COP stops in WAIT mode */ + byte RTIWAI :1; /* RTI stops in WAIT mode */ + byte CWAI :1; /* CLK24 and CLK23 stop in WAIT mode */ + byte PLLWAI :1; /* PLL stops in WAIT mode */ + byte ROAWAI :1; /* Reduced Oscillator Amplitude in WAIT mode */ + byte SYSWAI :1; /* System clocks stop in WAIT mode */ + byte PSTP :1; /* Pseudo Stop */ + byte PLLSEL :1; /* PLL selected for system clock */ + } Bits; +} CLKSELSTR; +extern volatile CLKSELSTR _CLKSEL @(REG_BASE + 0x00000039); +#define CLKSEL _CLKSEL.Byte +#define CLKSEL_COPWAI _CLKSEL.Bits.COPWAI +#define CLKSEL_RTIWAI _CLKSEL.Bits.RTIWAI +#define CLKSEL_CWAI _CLKSEL.Bits.CWAI +#define CLKSEL_PLLWAI _CLKSEL.Bits.PLLWAI +#define CLKSEL_ROAWAI _CLKSEL.Bits.ROAWAI +#define CLKSEL_SYSWAI _CLKSEL.Bits.SYSWAI +#define CLKSEL_PSTP _CLKSEL.Bits.PSTP +#define CLKSEL_PLLSEL _CLKSEL.Bits.PLLSEL + + +/*** PLLCTL - CRG PLL Control Register; 0x0000003A ***/ +typedef union { + byte Byte; + struct { + byte SCME :1; /* Self-clock mode enable */ + byte :1; + byte :1; + byte :1; + byte ACQ :1; /* Acquisition */ + byte AUTO :1; /* Automatic Bandwidth Control */ + byte PLLON :1; /* Phase Lock Loop On */ + byte CME :1; /* Crystal Monitor Enable */ + } Bits; +} PLLCTLSTR; +extern volatile PLLCTLSTR _PLLCTL @(REG_BASE + 0x0000003A); +#define PLLCTL _PLLCTL.Byte +#define PLLCTL_SCME _PLLCTL.Bits.SCME +#define PLLCTL_ACQ _PLLCTL.Bits.ACQ +#define PLLCTL_AUTO _PLLCTL.Bits.AUTO +#define PLLCTL_PLLON _PLLCTL.Bits.PLLON +#define PLLCTL_CME _PLLCTL.Bits.CME + + +/*** RTICTL - CRG RTI Control Register; 0x0000003B ***/ +typedef union { + byte Byte; + struct { + byte RTR0 :1; /* Real Time Interrupt Modulus Counter Select */ + byte RTR1 :1; /* Real Time Interrupt Modulus Counter Select */ + byte RTR2 :1; /* Real Time Interrupt Modulus Counter Select */ + byte RTR3 :1; /* Real Time Interrupt Modulus Counter Select */ + byte RTR4 :1; /* Real Time Interrupt Prescale Rate Select */ + byte RTR5 :1; /* Real Time Interrupt Prescale Rate Select */ + byte RTR6 :1; /* Real Time Interrupt Prescale Rate Select */ + byte :1; + } Bits; + struct { + byte grpRTR :7; + byte :1; + } MergedBits; +} RTICTLSTR; +extern volatile RTICTLSTR _RTICTL @(REG_BASE + 0x0000003B); +#define RTICTL _RTICTL.Byte +#define RTICTL_RTR0 _RTICTL.Bits.RTR0 +#define RTICTL_RTR1 _RTICTL.Bits.RTR1 +#define RTICTL_RTR2 _RTICTL.Bits.RTR2 +#define RTICTL_RTR3 _RTICTL.Bits.RTR3 +#define RTICTL_RTR4 _RTICTL.Bits.RTR4 +#define RTICTL_RTR5 _RTICTL.Bits.RTR5 +#define RTICTL_RTR6 _RTICTL.Bits.RTR6 +#define RTICTL_RTR _RTICTL.MergedBits.grpRTR + + +/*** COPCTL - CRG COP Control Register; 0x0000003C ***/ +typedef union { + byte Byte; + struct { + byte CR0 :1; /* COP Watchdog Timer Rate select Bit 0 */ + byte CR1 :1; /* COP Watchdog Timer Rate select Bit 1 */ + byte CR2 :1; /* COP Watchdog Timer Rate select Bit 2 */ + byte :1; + byte :1; + byte :1; + byte RSBCK :1; /* COP and RTI stop in Active BDM mode Bit */ + byte WCOP :1; /* Window COP mode */ + } Bits; + struct { + byte grpCR :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} COPCTLSTR; +extern volatile COPCTLSTR _COPCTL @(REG_BASE + 0x0000003C); +#define COPCTL _COPCTL.Byte +#define COPCTL_CR0 _COPCTL.Bits.CR0 +#define COPCTL_CR1 _COPCTL.Bits.CR1 +#define COPCTL_CR2 _COPCTL.Bits.CR2 +#define COPCTL_RSBCK _COPCTL.Bits.RSBCK +#define COPCTL_WCOP _COPCTL.Bits.WCOP +#define COPCTL_CR _COPCTL.MergedBits.grpCR + + +/*** CTCTL - CRG Test Control Register; 0x0000003E ***/ +typedef union { + byte Byte; + struct { + byte TCTL0 :1; /* CRG Test Control Bit 0 */ + byte TCTL1 :1; /* CRG Test Control Bit 1 */ + byte TCTL2 :1; /* CRG Test Control Bit 2 */ + byte TCTL3 :1; /* CRG Test Control Bit 3 */ + byte TCTL4 :1; /* CRG Test Control Bit 4 */ + byte TCTL5 :1; /* CRG Test Control Bit 5 */ + byte TCTL6 :1; /* CRG Test Control Bit 6 */ + byte TCTL7 :1; /* CRG Test Control Bit 7 */ + } Bits; + struct { + byte grpTCTL :8; + } MergedBits; +} CTCTLSTR; +extern volatile CTCTLSTR _CTCTL @(REG_BASE + 0x0000003E); +#define CTCTL _CTCTL.Byte +#define CTCTL_TCTL0 _CTCTL.Bits.TCTL0 +#define CTCTL_TCTL1 _CTCTL.Bits.TCTL1 +#define CTCTL_TCTL2 _CTCTL.Bits.TCTL2 +#define CTCTL_TCTL3 _CTCTL.Bits.TCTL3 +#define CTCTL_TCTL4 _CTCTL.Bits.TCTL4 +#define CTCTL_TCTL5 _CTCTL.Bits.TCTL5 +#define CTCTL_TCTL6 _CTCTL.Bits.TCTL6 +#define CTCTL_TCTL7 _CTCTL.Bits.TCTL7 +#define CTCTL_TCTL _CTCTL.MergedBits.grpTCTL + + +/*** ARMCOP - CRG COP Timer Arm/Reset Register; 0x0000003F ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* CRG COP Timer Arm/Reset Bit 0 */ + byte BIT1 :1; /* CRG COP Timer Arm/Reset Bit 1 */ + byte BIT2 :1; /* CRG COP Timer Arm/Reset Bit 2 */ + byte BIT3 :1; /* CRG COP Timer Arm/Reset Bit 3 */ + byte BIT4 :1; /* CRG COP Timer Arm/Reset Bit 4 */ + byte BIT5 :1; /* CRG COP Timer Arm/Reset Bit 5 */ + byte BIT6 :1; /* CRG COP Timer Arm/Reset Bit 6 */ + byte BIT7 :1; /* CRG COP Timer Arm/Reset Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} ARMCOPSTR; +extern volatile ARMCOPSTR _ARMCOP @(REG_BASE + 0x0000003F); +#define ARMCOP _ARMCOP.Byte +#define ARMCOP_BIT0 _ARMCOP.Bits.BIT0 +#define ARMCOP_BIT1 _ARMCOP.Bits.BIT1 +#define ARMCOP_BIT2 _ARMCOP.Bits.BIT2 +#define ARMCOP_BIT3 _ARMCOP.Bits.BIT3 +#define ARMCOP_BIT4 _ARMCOP.Bits.BIT4 +#define ARMCOP_BIT5 _ARMCOP.Bits.BIT5 +#define ARMCOP_BIT6 _ARMCOP.Bits.BIT6 +#define ARMCOP_BIT7 _ARMCOP.Bits.BIT7 +#define ARMCOP_BIT _ARMCOP.MergedBits.grpBIT + + +/*** TIOS - Timer Input Capture/Output Compare Select; 0x00000040 ***/ +typedef union { + byte Byte; + struct { + byte IOS0 :1; /* Input Capture or Output Compare Channel Configuration Bit 0 */ + byte IOS1 :1; /* Input Capture or Output Compare Channel Configuration Bit 1 */ + byte IOS2 :1; /* Input Capture or Output Compare Channel Configuration Bit 2 */ + byte IOS3 :1; /* Input Capture or Output Compare Channel Configuration Bit 3 */ + byte IOS4 :1; /* Input Capture or Output Compare Channel Configuration Bit 4 */ + byte IOS5 :1; /* Input Capture or Output Compare Channel Configuration Bit 5 */ + byte IOS6 :1; /* Input Capture or Output Compare Channel Configuration Bit 6 */ + byte IOS7 :1; /* Input Capture or Output Compare Channel Configuration Bit 7 */ + } Bits; + struct { + byte grpIOS :8; + } MergedBits; +} TIOSSTR; +extern volatile TIOSSTR _TIOS @(REG_BASE + 0x00000040); +#define TIOS _TIOS.Byte +#define TIOS_IOS0 _TIOS.Bits.IOS0 +#define TIOS_IOS1 _TIOS.Bits.IOS1 +#define TIOS_IOS2 _TIOS.Bits.IOS2 +#define TIOS_IOS3 _TIOS.Bits.IOS3 +#define TIOS_IOS4 _TIOS.Bits.IOS4 +#define TIOS_IOS5 _TIOS.Bits.IOS5 +#define TIOS_IOS6 _TIOS.Bits.IOS6 +#define TIOS_IOS7 _TIOS.Bits.IOS7 +#define TIOS_IOS _TIOS.MergedBits.grpIOS + + +/*** CFORC - Timer Compare Force Register; 0x00000041 ***/ +typedef union { + byte Byte; + struct { + byte FOC0 :1; /* Force Output Compare Action for Channel 0 */ + byte FOC1 :1; /* Force Output Compare Action for Channel 1 */ + byte FOC2 :1; /* Force Output Compare Action for Channel 2 */ + byte FOC3 :1; /* Force Output Compare Action for Channel 3 */ + byte FOC4 :1; /* Force Output Compare Action for Channel 4 */ + byte FOC5 :1; /* Force Output Compare Action for Channel 5 */ + byte FOC6 :1; /* Force Output Compare Action for Channel 6 */ + byte FOC7 :1; /* Force Output Compare Action for Channel 7 */ + } Bits; + struct { + byte grpFOC :8; + } MergedBits; +} CFORCSTR; +extern volatile CFORCSTR _CFORC @(REG_BASE + 0x00000041); +#define CFORC _CFORC.Byte +#define CFORC_FOC0 _CFORC.Bits.FOC0 +#define CFORC_FOC1 _CFORC.Bits.FOC1 +#define CFORC_FOC2 _CFORC.Bits.FOC2 +#define CFORC_FOC3 _CFORC.Bits.FOC3 +#define CFORC_FOC4 _CFORC.Bits.FOC4 +#define CFORC_FOC5 _CFORC.Bits.FOC5 +#define CFORC_FOC6 _CFORC.Bits.FOC6 +#define CFORC_FOC7 _CFORC.Bits.FOC7 +#define CFORC_FOC _CFORC.MergedBits.grpFOC + + +/*** OC7M - Output Compare 7 Mask Register; 0x00000042 ***/ +typedef union { + byte Byte; + struct { + byte OC7M0 :1; /* Output Compare 7 Mask Bit 0 */ + byte OC7M1 :1; /* Output Compare 7 Mask Bit 1 */ + byte OC7M2 :1; /* Output Compare 7 Mask Bit 2 */ + byte OC7M3 :1; /* Output Compare 7 Mask Bit 3 */ + byte OC7M4 :1; /* Output Compare 7 Mask Bit 4 */ + byte OC7M5 :1; /* Output Compare 7 Mask Bit 5 */ + byte OC7M6 :1; /* Output Compare 7 Mask Bit 6 */ + byte OC7M7 :1; /* Output Compare 7 Mask Bit 7 */ + } Bits; + struct { + byte grpOC7M :8; + } MergedBits; +} OC7MSTR; +extern volatile OC7MSTR _OC7M @(REG_BASE + 0x00000042); +#define OC7M _OC7M.Byte +#define OC7M_OC7M0 _OC7M.Bits.OC7M0 +#define OC7M_OC7M1 _OC7M.Bits.OC7M1 +#define OC7M_OC7M2 _OC7M.Bits.OC7M2 +#define OC7M_OC7M3 _OC7M.Bits.OC7M3 +#define OC7M_OC7M4 _OC7M.Bits.OC7M4 +#define OC7M_OC7M5 _OC7M.Bits.OC7M5 +#define OC7M_OC7M6 _OC7M.Bits.OC7M6 +#define OC7M_OC7M7 _OC7M.Bits.OC7M7 +#define OC7M_OC7M _OC7M.MergedBits.grpOC7M + + +/*** OC7D - Output Compare 7 Data Register; 0x00000043 ***/ +typedef union { + byte Byte; + struct { + byte OC7D0 :1; /* Output Compare 7 Bit 0 */ + byte OC7D1 :1; /* Output Compare 7 Bit 1 */ + byte OC7D2 :1; /* Output Compare 7 Bit 2 */ + byte OC7D3 :1; /* Output Compare 7 Bit 3 */ + byte OC7D4 :1; /* Output Compare 7 Bit 4 */ + byte OC7D5 :1; /* Output Compare 7 Bit 5 */ + byte OC7D6 :1; /* Output Compare 7 Bit 6 */ + byte OC7D7 :1; /* Output Compare 7 Bit 7 */ + } Bits; + struct { + byte grpOC7D :8; + } MergedBits; +} OC7DSTR; +extern volatile OC7DSTR _OC7D @(REG_BASE + 0x00000043); +#define OC7D _OC7D.Byte +#define OC7D_OC7D0 _OC7D.Bits.OC7D0 +#define OC7D_OC7D1 _OC7D.Bits.OC7D1 +#define OC7D_OC7D2 _OC7D.Bits.OC7D2 +#define OC7D_OC7D3 _OC7D.Bits.OC7D3 +#define OC7D_OC7D4 _OC7D.Bits.OC7D4 +#define OC7D_OC7D5 _OC7D.Bits.OC7D5 +#define OC7D_OC7D6 _OC7D.Bits.OC7D6 +#define OC7D_OC7D7 _OC7D.Bits.OC7D7 +#define OC7D_OC7D _OC7D.MergedBits.grpOC7D + + +/*** TSCR1 - Timer System Control Register1; 0x00000046 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte TFFCA :1; /* Timer Fast Flag Clear All */ + byte TSFRZ :1; /* Timer and Modulus Counter Stop While in Freeze Mode */ + byte TSWAI :1; /* Timer Module Stops While in Wait */ + byte TEN :1; /* Timer Enable */ + } Bits; +} TSCR1STR; +extern volatile TSCR1STR _TSCR1 @(REG_BASE + 0x00000046); +#define TSCR1 _TSCR1.Byte +#define TSCR1_TFFCA _TSCR1.Bits.TFFCA +#define TSCR1_TSFRZ _TSCR1.Bits.TSFRZ +#define TSCR1_TSWAI _TSCR1.Bits.TSWAI +#define TSCR1_TEN _TSCR1.Bits.TEN + + +/*** TTOV - Timer Toggle On Overflow Register; 0x00000047 ***/ +typedef union { + byte Byte; + struct { + byte TOV0 :1; /* Toggle On Overflow Bit 0 */ + byte TOV1 :1; /* Toggle On Overflow Bit 1 */ + byte TOV2 :1; /* Toggle On Overflow Bit 2 */ + byte TOV3 :1; /* Toggle On Overflow Bit 3 */ + byte TOV4 :1; /* Toggle On Overflow Bit 4 */ + byte TOV5 :1; /* Toggle On Overflow Bit 5 */ + byte TOV6 :1; /* Toggle On Overflow Bit 6 */ + byte TOV7 :1; /* Toggle On Overflow Bit 7 */ + } Bits; + struct { + byte grpTOV :8; + } MergedBits; +} TTOVSTR; +extern volatile TTOVSTR _TTOV @(REG_BASE + 0x00000047); +#define TTOV _TTOV.Byte +#define TTOV_TOV0 _TTOV.Bits.TOV0 +#define TTOV_TOV1 _TTOV.Bits.TOV1 +#define TTOV_TOV2 _TTOV.Bits.TOV2 +#define TTOV_TOV3 _TTOV.Bits.TOV3 +#define TTOV_TOV4 _TTOV.Bits.TOV4 +#define TTOV_TOV5 _TTOV.Bits.TOV5 +#define TTOV_TOV6 _TTOV.Bits.TOV6 +#define TTOV_TOV7 _TTOV.Bits.TOV7 +#define TTOV_TOV _TTOV.MergedBits.grpTOV + + +/*** TCTL1 - Timer Control Register 1; 0x00000048 ***/ +typedef union { + byte Byte; + struct { + byte OL4 :1; /* Output Level Bit 4 */ + byte OM4 :1; /* Output Mode Bit 4 */ + byte OL5 :1; /* Output Level Bit 5 */ + byte OM5 :1; /* Output Mode Bit 5 */ + byte OL6 :1; /* Output Level Bit 6 */ + byte OM6 :1; /* Output Mode Bit 6 */ + byte OL7 :1; /* Output Level Bit 7 */ + byte OM7 :1; /* Output Mode Bit 7 */ + } Bits; +} TCTL1STR; +extern volatile TCTL1STR _TCTL1 @(REG_BASE + 0x00000048); +#define TCTL1 _TCTL1.Byte +#define TCTL1_OL4 _TCTL1.Bits.OL4 +#define TCTL1_OM4 _TCTL1.Bits.OM4 +#define TCTL1_OL5 _TCTL1.Bits.OL5 +#define TCTL1_OM5 _TCTL1.Bits.OM5 +#define TCTL1_OL6 _TCTL1.Bits.OL6 +#define TCTL1_OM6 _TCTL1.Bits.OM6 +#define TCTL1_OL7 _TCTL1.Bits.OL7 +#define TCTL1_OM7 _TCTL1.Bits.OM7 + + +/*** TCTL2 - Timer Control Register 2; 0x00000049 ***/ +typedef union { + byte Byte; + struct { + byte OL0 :1; /* Output Level Bit 0 */ + byte OM0 :1; /* Output Mode Bit 0 */ + byte OL1 :1; /* Output Level Bit 1 */ + byte OM1 :1; /* Output Mode Bit 1 */ + byte OL2 :1; /* Output Level Bit 2 */ + byte OM2 :1; /* Output Mode Bit 2 */ + byte OL3 :1; /* Output Level Bit 3 */ + byte OM3 :1; /* Output Mode Bit 3 */ + } Bits; +} TCTL2STR; +extern volatile TCTL2STR _TCTL2 @(REG_BASE + 0x00000049); +#define TCTL2 _TCTL2.Byte +#define TCTL2_OL0 _TCTL2.Bits.OL0 +#define TCTL2_OM0 _TCTL2.Bits.OM0 +#define TCTL2_OL1 _TCTL2.Bits.OL1 +#define TCTL2_OM1 _TCTL2.Bits.OM1 +#define TCTL2_OL2 _TCTL2.Bits.OL2 +#define TCTL2_OM2 _TCTL2.Bits.OM2 +#define TCTL2_OL3 _TCTL2.Bits.OL3 +#define TCTL2_OM3 _TCTL2.Bits.OM3 + + +/*** TCTL3 - Timer Control Register 3; 0x0000004A ***/ +typedef union { + byte Byte; + struct { + byte EDG4A :1; /* Input Capture Edge Control 4A */ + byte EDG4B :1; /* Input Capture Edge Control 4B */ + byte EDG5A :1; /* Input Capture Edge Control 5A */ + byte EDG5B :1; /* Input Capture Edge Control 5B */ + byte EDG6A :1; /* Input Capture Edge Control 6A */ + byte EDG6B :1; /* Input Capture Edge Control 6B */ + byte EDG7A :1; /* Input Capture Edge Control 7A */ + byte EDG7B :1; /* Input Capture Edge Control 7B */ + } Bits; +} TCTL3STR; +extern volatile TCTL3STR _TCTL3 @(REG_BASE + 0x0000004A); +#define TCTL3 _TCTL3.Byte +#define TCTL3_EDG4A _TCTL3.Bits.EDG4A +#define TCTL3_EDG4B _TCTL3.Bits.EDG4B +#define TCTL3_EDG5A _TCTL3.Bits.EDG5A +#define TCTL3_EDG5B _TCTL3.Bits.EDG5B +#define TCTL3_EDG6A _TCTL3.Bits.EDG6A +#define TCTL3_EDG6B _TCTL3.Bits.EDG6B +#define TCTL3_EDG7A _TCTL3.Bits.EDG7A +#define TCTL3_EDG7B _TCTL3.Bits.EDG7B + + +/*** TCTL4 - Timer Control Register 4; 0x0000004B ***/ +typedef union { + byte Byte; + struct { + byte EDG0A :1; /* Input Capture Edge Control 0A */ + byte EDG0B :1; /* Input Capture Edge Control 0B */ + byte EDG1A :1; /* Input Capture Edge Control 1A */ + byte EDG1B :1; /* Input Capture Edge Control 1B */ + byte EDG2A :1; /* Input Capture Edge Control 2A */ + byte EDG2B :1; /* Input Capture Edge Control 2B */ + byte EDG3A :1; /* Input Capture Edge Control 3A */ + byte EDG3B :1; /* Input Capture Edge Control 3B */ + } Bits; +} TCTL4STR; +extern volatile TCTL4STR _TCTL4 @(REG_BASE + 0x0000004B); +#define TCTL4 _TCTL4.Byte +#define TCTL4_EDG0A _TCTL4.Bits.EDG0A +#define TCTL4_EDG0B _TCTL4.Bits.EDG0B +#define TCTL4_EDG1A _TCTL4.Bits.EDG1A +#define TCTL4_EDG1B _TCTL4.Bits.EDG1B +#define TCTL4_EDG2A _TCTL4.Bits.EDG2A +#define TCTL4_EDG2B _TCTL4.Bits.EDG2B +#define TCTL4_EDG3A _TCTL4.Bits.EDG3A +#define TCTL4_EDG3B _TCTL4.Bits.EDG3B + + +/*** TIE - Timer Interrupt Enable Register; 0x0000004C ***/ +typedef union { + byte Byte; + struct { + byte C0I :1; /* Input Capture/Output Compare Interrupt Enable Bit 0 */ + byte C1I :1; /* Input Capture/Output Compare Interrupt Enable Bit 1 */ + byte C2I :1; /* Input Capture/Output Compare Interrupt Enable Bit 2 */ + byte C3I :1; /* Input Capture/Output Compare Interrupt Enable Bit 3 */ + byte C4I :1; /* Input Capture/Output Compare Interrupt Enable Bit 4 */ + byte C5I :1; /* Input Capture/Output Compare Interrupt Enable Bit 5 */ + byte C6I :1; /* Input Capture/Output Compare Interrupt Enable Bit 6 */ + byte C7I :1; /* Input Capture/Output Compare Interrupt Enable Bit 7 */ + } Bits; +} TIESTR; +extern volatile TIESTR _TIE @(REG_BASE + 0x0000004C); +#define TIE _TIE.Byte +#define TIE_C0I _TIE.Bits.C0I +#define TIE_C1I _TIE.Bits.C1I +#define TIE_C2I _TIE.Bits.C2I +#define TIE_C3I _TIE.Bits.C3I +#define TIE_C4I _TIE.Bits.C4I +#define TIE_C5I _TIE.Bits.C5I +#define TIE_C6I _TIE.Bits.C6I +#define TIE_C7I _TIE.Bits.C7I + + +/*** TSCR2 - Timer System Control Register 2; 0x0000004D ***/ +typedef union { + byte Byte; + struct { + byte PR0 :1; /* Timer Prescaler Select Bit 0 */ + byte PR1 :1; /* Timer Prescaler Select Bit 1 */ + byte PR2 :1; /* Timer Prescaler Select Bit 2 */ + byte TCRE :1; /* Timer Counter Reset Enable */ + byte :1; + byte :1; + byte :1; + byte TOI :1; /* Timer Overflow Interrupt Enable */ + } Bits; + struct { + byte grpPR :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} TSCR2STR; +extern volatile TSCR2STR _TSCR2 @(REG_BASE + 0x0000004D); +#define TSCR2 _TSCR2.Byte +#define TSCR2_PR0 _TSCR2.Bits.PR0 +#define TSCR2_PR1 _TSCR2.Bits.PR1 +#define TSCR2_PR2 _TSCR2.Bits.PR2 +#define TSCR2_TCRE _TSCR2.Bits.TCRE +#define TSCR2_TOI _TSCR2.Bits.TOI +#define TSCR2_PR _TSCR2.MergedBits.grpPR + + +/*** TFLG1 - Main Timer Interrupt Flag 1; 0x0000004E ***/ +typedef union { + byte Byte; + struct { + byte C0F :1; /* Input Capture/Output Compare Channel Flag 0 */ + byte C1F :1; /* Input Capture/Output Compare Channel Flag 1 */ + byte C2F :1; /* Input Capture/Output Compare Channel Flag 2 */ + byte C3F :1; /* Input Capture/Output Compare Channel Flag 3 */ + byte C4F :1; /* Input Capture/Output Compare Channel Flag 4 */ + byte C5F :1; /* Input Capture/Output Compare Channel Flag 5 */ + byte C6F :1; /* Input Capture/Output Compare Channel Flag 6 */ + byte C7F :1; /* Input Capture/Output Compare Channel Flag 7 */ + } Bits; +} TFLG1STR; +extern volatile TFLG1STR _TFLG1 @(REG_BASE + 0x0000004E); +#define TFLG1 _TFLG1.Byte +#define TFLG1_C0F _TFLG1.Bits.C0F +#define TFLG1_C1F _TFLG1.Bits.C1F +#define TFLG1_C2F _TFLG1.Bits.C2F +#define TFLG1_C3F _TFLG1.Bits.C3F +#define TFLG1_C4F _TFLG1.Bits.C4F +#define TFLG1_C5F _TFLG1.Bits.C5F +#define TFLG1_C6F _TFLG1.Bits.C6F +#define TFLG1_C7F _TFLG1.Bits.C7F + + +/*** TFLG2 - Main Timer Interrupt Flag 2; 0x0000004F ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte TOF :1; /* Timer Overflow Flag */ + } Bits; +} TFLG2STR; +extern volatile TFLG2STR _TFLG2 @(REG_BASE + 0x0000004F); +#define TFLG2 _TFLG2.Byte +#define TFLG2_TOF _TFLG2.Bits.TOF + + +/*** PACTL - 16-Bit Pulse Accumulator A Control Register; 0x00000060 ***/ +typedef union { + byte Byte; + struct { + byte PAI :1; /* Pulse Accumulator Input Interrupt enable */ + byte PAOVI :1; /* Pulse Accumulator A Overflow Interrupt enable */ + byte CLK0 :1; /* Clock Select Bit 0 */ + byte CLK1 :1; /* Clock Select Bit 1 */ + byte PEDGE :1; /* Pulse Accumulator Edge Control */ + byte PAMOD :1; /* Pulse Accumulator Mode */ + byte PAEN :1; /* Pulse Accumulator A System Enable */ + byte :1; + } Bits; + struct { + byte :1; + byte :1; + byte grpCLK :2; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} PACTLSTR; +extern volatile PACTLSTR _PACTL @(REG_BASE + 0x00000060); +#define PACTL _PACTL.Byte +#define PACTL_PAI _PACTL.Bits.PAI +#define PACTL_PAOVI _PACTL.Bits.PAOVI +#define PACTL_CLK0 _PACTL.Bits.CLK0 +#define PACTL_CLK1 _PACTL.Bits.CLK1 +#define PACTL_PEDGE _PACTL.Bits.PEDGE +#define PACTL_PAMOD _PACTL.Bits.PAMOD +#define PACTL_PAEN _PACTL.Bits.PAEN +#define PACTL_CLK _PACTL.MergedBits.grpCLK + + +/*** PAFLG - Pulse Accumulator A Flag Register; 0x00000061 ***/ +typedef union { + byte Byte; + struct { + byte PAIF :1; /* Pulse Accumulator Input edge Flag */ + byte PAOVF :1; /* Pulse Accumulator A Overflow Flag */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} PAFLGSTR; +extern volatile PAFLGSTR _PAFLG @(REG_BASE + 0x00000061); +#define PAFLG _PAFLG.Byte +#define PAFLG_PAIF _PAFLG.Bits.PAIF +#define PAFLG_PAOVF _PAFLG.Bits.PAOVF + + +/*** ATDSTAT0 - A/D Status Register 0; 0x00000086 ***/ +typedef union { + byte Byte; + struct { + byte CC0 :1; /* Conversion Counter 0 */ + byte CC1 :1; /* Conversion Counter 1 */ + byte CC2 :1; /* Conversion Counter 2 */ + byte :1; + byte FIFOR :1; /* FIFO Over Run Flag */ + byte ETORF :1; /* External Trigger Overrun Flag */ + byte :1; + byte SCF :1; /* Sequence Complete Flag */ + } Bits; + struct { + byte grpCC :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} ATDSTAT0STR; +extern volatile ATDSTAT0STR _ATDSTAT0 @(REG_BASE + 0x00000086); +#define ATDSTAT0 _ATDSTAT0.Byte +#define ATDSTAT0_CC0 _ATDSTAT0.Bits.CC0 +#define ATDSTAT0_CC1 _ATDSTAT0.Bits.CC1 +#define ATDSTAT0_CC2 _ATDSTAT0.Bits.CC2 +#define ATDSTAT0_FIFOR _ATDSTAT0.Bits.FIFOR +#define ATDSTAT0_ETORF _ATDSTAT0.Bits.ETORF +#define ATDSTAT0_SCF _ATDSTAT0.Bits.SCF +#define ATDSTAT0_CC _ATDSTAT0.MergedBits.grpCC + + +/*** ATDSTAT1 - A/D Status Register 1; 0x0000008B ***/ +typedef union { + byte Byte; + struct { + byte CCF0 :1; /* Conversion Complete Flag 0 */ + byte CCF1 :1; /* Conversion Complete Flag 1 */ + byte CCF2 :1; /* Conversion Complete Flag 2 */ + byte CCF3 :1; /* Conversion Complete Flag 3 */ + byte CCF4 :1; /* Conversion Complete Flag 4 */ + byte CCF5 :1; /* Conversion Complete Flag 5 */ + byte CCF6 :1; /* Conversion Complete Flag 6 */ + byte CCF7 :1; /* Conversion Complete Flag 7 */ + } Bits; + struct { + byte grpCCF :8; + } MergedBits; +} ATDSTAT1STR; +extern volatile ATDSTAT1STR _ATDSTAT1 @(REG_BASE + 0x0000008B); +#define ATDSTAT1 _ATDSTAT1.Byte +#define ATDSTAT1_CCF0 _ATDSTAT1.Bits.CCF0 +#define ATDSTAT1_CCF1 _ATDSTAT1.Bits.CCF1 +#define ATDSTAT1_CCF2 _ATDSTAT1.Bits.CCF2 +#define ATDSTAT1_CCF3 _ATDSTAT1.Bits.CCF3 +#define ATDSTAT1_CCF4 _ATDSTAT1.Bits.CCF4 +#define ATDSTAT1_CCF5 _ATDSTAT1.Bits.CCF5 +#define ATDSTAT1_CCF6 _ATDSTAT1.Bits.CCF6 +#define ATDSTAT1_CCF7 _ATDSTAT1.Bits.CCF7 +#define ATDSTAT1_CCF _ATDSTAT1.MergedBits.grpCCF + + +/*** ATDDIEN - ATD Input Enable Mask Register; 0x0000008D ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* Disable/Enable digital input buffer */ + byte BIT1 :1; /* Disable/Enable digital input buffer */ + byte BIT2 :1; /* Disable/Enable digital input buffer */ + byte BIT3 :1; /* Disable/Enable digital input buffer */ + byte BIT4 :1; /* Disable/Enable digital input buffer */ + byte BIT5 :1; /* Disable/Enable digital input buffer */ + byte BIT6 :1; /* Disable/Enable digital input buffer */ + byte BIT7 :1; /* Disable/Enable digital input buffer */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} ATDDIENSTR; +extern volatile ATDDIENSTR _ATDDIEN @(REG_BASE + 0x0000008D); +#define ATDDIEN _ATDDIEN.Byte +#define ATDDIEN_BIT0 _ATDDIEN.Bits.BIT0 +#define ATDDIEN_BIT1 _ATDDIEN.Bits.BIT1 +#define ATDDIEN_BIT2 _ATDDIEN.Bits.BIT2 +#define ATDDIEN_BIT3 _ATDDIEN.Bits.BIT3 +#define ATDDIEN_BIT4 _ATDDIEN.Bits.BIT4 +#define ATDDIEN_BIT5 _ATDDIEN.Bits.BIT5 +#define ATDDIEN_BIT6 _ATDDIEN.Bits.BIT6 +#define ATDDIEN_BIT7 _ATDDIEN.Bits.BIT7 +#define ATDDIEN_BIT _ATDDIEN.MergedBits.grpBIT + + +/*** PORTAD0 - Port AD0 Register; 0x0000008F ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* AN0 */ + byte BIT1 :1; /* AN1 */ + byte BIT2 :1; /* AN2 */ + byte BIT3 :1; /* AN3 */ + byte BIT4 :1; /* AN4 */ + byte BIT5 :1; /* AN5 */ + byte BIT6 :1; /* AN6 */ + byte BIT7 :1; /* AN7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} PORTAD0STR; +extern volatile PORTAD0STR _PORTAD0 @(REG_BASE + 0x0000008F); +#define PORTAD0 _PORTAD0.Byte +#define PORTAD0_BIT0 _PORTAD0.Bits.BIT0 +#define PORTAD0_BIT1 _PORTAD0.Bits.BIT1 +#define PORTAD0_BIT2 _PORTAD0.Bits.BIT2 +#define PORTAD0_BIT3 _PORTAD0.Bits.BIT3 +#define PORTAD0_BIT4 _PORTAD0.Bits.BIT4 +#define PORTAD0_BIT5 _PORTAD0.Bits.BIT5 +#define PORTAD0_BIT6 _PORTAD0.Bits.BIT6 +#define PORTAD0_BIT7 _PORTAD0.Bits.BIT7 +#define PORTAD0_BIT _PORTAD0.MergedBits.grpBIT + + +/*** SCICR1 - SCI Control Register 1; 0x000000CA ***/ +typedef union { + byte Byte; + struct { + byte PT :1; /* Parity Type Bit */ + byte PE :1; /* Parity Enable Bit */ + byte ILT :1; /* Idle Line Type Bit */ + byte WAKE :1; /* Wakeup Condition Bit */ + byte M :1; /* Data Format Mode Bit */ + byte RSRC :1; /* Receiver Source Bit */ + byte SCISWAI :1; /* SCI Stop in Wait Mode Bit */ + byte LOOPS :1; /* Loop Select Bit */ + } Bits; +} SCICR1STR; +extern volatile SCICR1STR _SCICR1 @(REG_BASE + 0x000000CA); +#define SCICR1 _SCICR1.Byte +#define SCICR1_PT _SCICR1.Bits.PT +#define SCICR1_PE _SCICR1.Bits.PE +#define SCICR1_ILT _SCICR1.Bits.ILT +#define SCICR1_WAKE _SCICR1.Bits.WAKE +#define SCICR1_M _SCICR1.Bits.M +#define SCICR1_RSRC _SCICR1.Bits.RSRC +#define SCICR1_SCISWAI _SCICR1.Bits.SCISWAI +#define SCICR1_LOOPS _SCICR1.Bits.LOOPS + + +/*** SCICR2 - SCI Control Register 2; 0x000000CB ***/ +typedef union { + byte Byte; + struct { + byte SBK :1; /* Send Break Bit */ + byte RWU :1; /* Receiver Wakeup Bit */ + byte RE :1; /* Receiver Enable Bit */ + byte TE :1; /* Transmitter Enable Bit */ + byte ILIE :1; /* Idle Line Interrupt Enable Bit */ + byte RIE :1; /* Receiver Full Interrupt Enable Bit */ + byte TCIE :1; /* Transmission Complete Interrupt Enable Bit */ + byte SCTIE :1; /* Transmitter Interrupt Enable Bit */ + } Bits; +} SCICR2STR; +extern volatile SCICR2STR _SCICR2 @(REG_BASE + 0x000000CB); +#define SCICR2 _SCICR2.Byte +#define SCICR2_SBK _SCICR2.Bits.SBK +#define SCICR2_RWU _SCICR2.Bits.RWU +#define SCICR2_RE _SCICR2.Bits.RE +#define SCICR2_TE _SCICR2.Bits.TE +#define SCICR2_ILIE _SCICR2.Bits.ILIE +#define SCICR2_RIE _SCICR2.Bits.RIE +#define SCICR2_TCIE _SCICR2.Bits.TCIE +#define SCICR2_SCTIE _SCICR2.Bits.SCTIE + + +/*** SCISR1 - SCI Status Register 1; 0x000000CC ***/ +typedef union { + byte Byte; + struct { + byte PF :1; /* Parity Error Flag */ + byte FE :1; /* Framing Error Flag */ + byte NF :1; /* Noise Flag */ + byte OR :1; /* Overrun Flag */ + byte IDLE :1; /* Idle Line Flag */ + byte RDRF :1; /* Receive Data Register Full Flag */ + byte TC :1; /* Transmit Complete Flag */ + byte TDRE :1; /* Transmit Data Register Empty Flag */ + } Bits; +} SCISR1STR; +extern volatile SCISR1STR _SCISR1 @(REG_BASE + 0x000000CC); +#define SCISR1 _SCISR1.Byte +#define SCISR1_PF _SCISR1.Bits.PF +#define SCISR1_FE _SCISR1.Bits.FE +#define SCISR1_NF _SCISR1.Bits.NF +#define SCISR1_OR _SCISR1.Bits.OR +#define SCISR1_IDLE _SCISR1.Bits.IDLE +#define SCISR1_RDRF _SCISR1.Bits.RDRF +#define SCISR1_TC _SCISR1.Bits.TC +#define SCISR1_TDRE _SCISR1.Bits.TDRE + + +/*** SCISR2 - SCI Status Register 2; 0x000000CD ***/ +typedef union { + byte Byte; + struct { + byte RAF :1; /* Receiver Active Flag */ + byte TXDIR :1; /* Transmitter pin data direction in Single-Wire mode */ + byte BRK13 :1; /* Break Transmit character length */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} SCISR2STR; +extern volatile SCISR2STR _SCISR2 @(REG_BASE + 0x000000CD); +#define SCISR2 _SCISR2.Byte +#define SCISR2_RAF _SCISR2.Bits.RAF +#define SCISR2_TXDIR _SCISR2.Bits.TXDIR +#define SCISR2_BRK13 _SCISR2.Bits.BRK13 + + +/*** SCIDRH - SCI Data Register High; 0x000000CE ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte T8 :1; /* Transmit Bit 8 */ + byte R8 :1; /* Received Bit 8 */ + } Bits; +} SCIDRHSTR; +extern volatile SCIDRHSTR _SCIDRH @(REG_BASE + 0x000000CE); +#define SCIDRH _SCIDRH.Byte +#define SCIDRH_T8 _SCIDRH.Bits.T8 +#define SCIDRH_R8 _SCIDRH.Bits.R8 + + +/*** SCIDRL - SCI Data Register Low; 0x000000CF ***/ +typedef union { + byte Byte; + struct { + byte R0_T0 :1; /* Received bit 0 or Transmit bit 0 */ + byte R1_T1 :1; /* Received bit 1 or Transmit bit 1 */ + byte R2_T2 :1; /* Received bit 2 or Transmit bit 2 */ + byte R3_T3 :1; /* Received bit 3 or Transmit bit 3 */ + byte R4_T4 :1; /* Received bit 4 or Transmit bit 4 */ + byte R5_T5 :1; /* Received bit 5 or Transmit bit 5 */ + byte R6_T6 :1; /* Received bit 6 or Transmit bit 6 */ + byte R7_T7 :1; /* Received bit 7 or Transmit bit 7 */ + } Bits; +} SCIDRLSTR; +extern volatile SCIDRLSTR _SCIDRL @(REG_BASE + 0x000000CF); +#define SCIDRL _SCIDRL.Byte +#define SCIDRL_R0_T0 _SCIDRL.Bits.R0_T0 +#define SCIDRL_R1_T1 _SCIDRL.Bits.R1_T1 +#define SCIDRL_R2_T2 _SCIDRL.Bits.R2_T2 +#define SCIDRL_R3_T3 _SCIDRL.Bits.R3_T3 +#define SCIDRL_R4_T4 _SCIDRL.Bits.R4_T4 +#define SCIDRL_R5_T5 _SCIDRL.Bits.R5_T5 +#define SCIDRL_R6_T6 _SCIDRL.Bits.R6_T6 +#define SCIDRL_R7_T7 _SCIDRL.Bits.R7_T7 + + +/*** SPICR1 - SPI Control Register; 0x000000D8 ***/ +typedef union { + byte Byte; + struct { + byte LSBFE :1; /* SPI LSB-First Enable */ + byte SSOE :1; /* Slave Select Output Enable */ + byte CPHA :1; /* SPI Clock Phase Bit */ + byte CPOL :1; /* SPI Clock Polarity Bit */ + byte MSTR :1; /* SPI Master/Slave Mode Select Bit */ + byte SPTIE :1; /* SPI Transmit Interrupt Enable */ + byte SPE :1; /* SPI System Enable Bit */ + byte SPIE :1; /* SPI Interrupt Enable Bit */ + } Bits; +} SPICR1STR; +extern volatile SPICR1STR _SPICR1 @(REG_BASE + 0x000000D8); +#define SPICR1 _SPICR1.Byte +#define SPICR1_LSBFE _SPICR1.Bits.LSBFE +#define SPICR1_SSOE _SPICR1.Bits.SSOE +#define SPICR1_CPHA _SPICR1.Bits.CPHA +#define SPICR1_CPOL _SPICR1.Bits.CPOL +#define SPICR1_MSTR _SPICR1.Bits.MSTR +#define SPICR1_SPTIE _SPICR1.Bits.SPTIE +#define SPICR1_SPE _SPICR1.Bits.SPE +#define SPICR1_SPIE _SPICR1.Bits.SPIE + + +/*** SPICR2 - SPI Control Register 2; 0x000000D9 ***/ +typedef union { + byte Byte; + struct { + byte SPC0 :1; /* Serial Pin Control Bit 0 */ + byte SPISWAI :1; /* SPI Stop in Wait Mode Bit */ + byte :1; + byte BIDIROE :1; /* Output enable in the Bidirectional mode of operation */ + byte MODFEN :1; /* Mode Fault Enable Bit */ + byte :1; + byte :1; + byte :1; + } Bits; +} SPICR2STR; +extern volatile SPICR2STR _SPICR2 @(REG_BASE + 0x000000D9); +#define SPICR2 _SPICR2.Byte +#define SPICR2_SPC0 _SPICR2.Bits.SPC0 +#define SPICR2_SPISWAI _SPICR2.Bits.SPISWAI +#define SPICR2_BIDIROE _SPICR2.Bits.BIDIROE +#define SPICR2_MODFEN _SPICR2.Bits.MODFEN + + +/*** SPIBR - SPI Baud Rate Register; 0x000000DA ***/ +typedef union { + byte Byte; + struct { + byte SPR0 :1; /* SPI Baud Rate Selection Bit 0 */ + byte SPR1 :1; /* SPI Baud Rate Selection Bit 1 */ + byte SPR2 :1; /* SPI Baud Rate Selection Bit 2 */ + byte :1; + byte SPPR0 :1; /* SPI Baud Rate Preselection Bits 0 */ + byte SPPR1 :1; /* SPI Baud Rate Preselection Bits 1 */ + byte SPPR2 :1; /* SPI Baud Rate Preselection Bits 2 */ + byte :1; + } Bits; + struct { + byte grpSPR :3; + byte :1; + byte grpSPPR :3; + byte :1; + } MergedBits; +} SPIBRSTR; +extern volatile SPIBRSTR _SPIBR @(REG_BASE + 0x000000DA); +#define SPIBR _SPIBR.Byte +#define SPIBR_SPR0 _SPIBR.Bits.SPR0 +#define SPIBR_SPR1 _SPIBR.Bits.SPR1 +#define SPIBR_SPR2 _SPIBR.Bits.SPR2 +#define SPIBR_SPPR0 _SPIBR.Bits.SPPR0 +#define SPIBR_SPPR1 _SPIBR.Bits.SPPR1 +#define SPIBR_SPPR2 _SPIBR.Bits.SPPR2 +#define SPIBR_SPR _SPIBR.MergedBits.grpSPR +#define SPIBR_SPPR _SPIBR.MergedBits.grpSPPR + + +/*** SPISR - SPI Status Register; 0x000000DB ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte MODF :1; /* Mode Fault Flag */ + byte SPTEF :1; /* SPI Transmit Empty Interrupt Flag */ + byte :1; + byte SPIF :1; /* SPIF Receive Interrupt Flag */ + } Bits; +} SPISRSTR; +extern volatile SPISRSTR _SPISR @(REG_BASE + 0x000000DB); +#define SPISR _SPISR.Byte +#define SPISR_MODF _SPISR.Bits.MODF +#define SPISR_SPTEF _SPISR.Bits.SPTEF +#define SPISR_SPIF _SPISR.Bits.SPIF + + +/*** SPIDR - SPI Data Register; 0x000000DD ***/ +typedef union { + byte Byte; + struct { + byte grpBIT :8; + } MergedBits; +} SPIDRSTR; +extern volatile SPIDRSTR _SPIDR @(REG_BASE + 0x000000DD); +#define SPIDR _SPIDR.Byte +#define SPIDR_BIT _SPIDR.MergedBits.grpBIT + + +/*** PWME - PWM Enable Register; 0x000000E0 ***/ +typedef union { + byte Byte; + struct { + byte PWME0 :1; /* Pulse Width Channel 0 Enable */ + byte PWME1 :1; /* Pulse Width Channel 1 Enable */ + byte PWME2 :1; /* Pulse Width Channel 2 Enable */ + byte PWME3 :1; /* Pulse Width Channel 3 Enable */ + byte PWME4 :1; /* Pulse Width Channel 4 Enable */ + byte PWME5 :1; /* Pulse Width Channel 5 Enable */ + byte PWME6 :1; /* Pulse Width Channel 6 Enable */ + byte PWME7 :1; /* Pulse Width Channel 7 Enable */ + } Bits; + struct { + byte grpPWME :8; + } MergedBits; +} PWMESTR; +extern volatile PWMESTR _PWME @(REG_BASE + 0x000000E0); +#define PWME _PWME.Byte +#define PWME_PWME0 _PWME.Bits.PWME0 +#define PWME_PWME1 _PWME.Bits.PWME1 +#define PWME_PWME2 _PWME.Bits.PWME2 +#define PWME_PWME3 _PWME.Bits.PWME3 +#define PWME_PWME4 _PWME.Bits.PWME4 +#define PWME_PWME5 _PWME.Bits.PWME5 +#define PWME_PWME6 _PWME.Bits.PWME6 +#define PWME_PWME7 _PWME.Bits.PWME7 +#define PWME_PWME _PWME.MergedBits.grpPWME + + +/*** PWMPOL - PWM Polarity Register; 0x000000E1 ***/ +typedef union { + byte Byte; + struct { + byte PPOL0 :1; /* Pulse Width Channel 0 Polarity */ + byte PPOL1 :1; /* Pulse Width Channel 1 Polarity */ + byte PPOL2 :1; /* Pulse Width Channel 2 Polarity */ + byte PPOL3 :1; /* Pulse Width Channel 3 Polarity */ + byte PPOL4 :1; /* Pulse Width Channel 4 Polarity */ + byte PPOL5 :1; /* Pulse Width Channel 5 Polarity */ + byte PPOL6 :1; /* Pulse Width Channel 6 Polarity */ + byte PPOL7 :1; /* Pulse Width Channel 7 Polarity */ + } Bits; + struct { + byte grpPPOL :8; + } MergedBits; +} PWMPOLSTR; +extern volatile PWMPOLSTR _PWMPOL @(REG_BASE + 0x000000E1); +#define PWMPOL _PWMPOL.Byte +#define PWMPOL_PPOL0 _PWMPOL.Bits.PPOL0 +#define PWMPOL_PPOL1 _PWMPOL.Bits.PPOL1 +#define PWMPOL_PPOL2 _PWMPOL.Bits.PPOL2 +#define PWMPOL_PPOL3 _PWMPOL.Bits.PPOL3 +#define PWMPOL_PPOL4 _PWMPOL.Bits.PPOL4 +#define PWMPOL_PPOL5 _PWMPOL.Bits.PPOL5 +#define PWMPOL_PPOL6 _PWMPOL.Bits.PPOL6 +#define PWMPOL_PPOL7 _PWMPOL.Bits.PPOL7 +#define PWMPOL_PPOL _PWMPOL.MergedBits.grpPPOL + + +/*** PWMCLK - PWM Clock Select Register; 0x000000E2 ***/ +typedef union { + byte Byte; + struct { + byte PCLK0 :1; /* Pulse Width Channel 0 Clock Select */ + byte PCLK1 :1; /* Pulse Width Channel 1 Clock Select */ + byte PCLK2 :1; /* Pulse Width Channel 2 Clock Select */ + byte PCLK3 :1; /* Pulse Width Channel 3 Clock Select */ + byte PCLK4 :1; /* Pulse Width Channel 4 Clock Select */ + byte PCLK5 :1; /* Pulse Width Channel 5 Clock Select */ + byte PCLK6 :1; /* Pulse Width Channel 6 Clock Select */ + byte PCLK7 :1; /* Pulse Width Channel 7 Clock Select */ + } Bits; + struct { + byte grpPCLK :8; + } MergedBits; +} PWMCLKSTR; +extern volatile PWMCLKSTR _PWMCLK @(REG_BASE + 0x000000E2); +#define PWMCLK _PWMCLK.Byte +#define PWMCLK_PCLK0 _PWMCLK.Bits.PCLK0 +#define PWMCLK_PCLK1 _PWMCLK.Bits.PCLK1 +#define PWMCLK_PCLK2 _PWMCLK.Bits.PCLK2 +#define PWMCLK_PCLK3 _PWMCLK.Bits.PCLK3 +#define PWMCLK_PCLK4 _PWMCLK.Bits.PCLK4 +#define PWMCLK_PCLK5 _PWMCLK.Bits.PCLK5 +#define PWMCLK_PCLK6 _PWMCLK.Bits.PCLK6 +#define PWMCLK_PCLK7 _PWMCLK.Bits.PCLK7 +#define PWMCLK_PCLK _PWMCLK.MergedBits.grpPCLK + + +/*** PWMPRCLK - PWM Prescale Clock Select Register; 0x000000E3 ***/ +typedef union { + byte Byte; + struct { + byte PCKA0 :1; /* Prescaler Select for Clock A 0 */ + byte PCKA1 :1; /* Prescaler Select for Clock A 1 */ + byte PCKA2 :1; /* Prescaler Select for Clock A 2 */ + byte :1; + byte PCKB0 :1; /* Prescaler Select for Clock B 0 */ + byte PCKB1 :1; /* Prescaler Select for Clock B 1 */ + byte PCKB2 :1; /* Prescaler Select for Clock B 2 */ + byte :1; + } Bits; + struct { + byte grpPCKA :3; + byte :1; + byte grpPCKB :3; + byte :1; + } MergedBits; +} PWMPRCLKSTR; +extern volatile PWMPRCLKSTR _PWMPRCLK @(REG_BASE + 0x000000E3); +#define PWMPRCLK _PWMPRCLK.Byte +#define PWMPRCLK_PCKA0 _PWMPRCLK.Bits.PCKA0 +#define PWMPRCLK_PCKA1 _PWMPRCLK.Bits.PCKA1 +#define PWMPRCLK_PCKA2 _PWMPRCLK.Bits.PCKA2 +#define PWMPRCLK_PCKB0 _PWMPRCLK.Bits.PCKB0 +#define PWMPRCLK_PCKB1 _PWMPRCLK.Bits.PCKB1 +#define PWMPRCLK_PCKB2 _PWMPRCLK.Bits.PCKB2 +#define PWMPRCLK_PCKA _PWMPRCLK.MergedBits.grpPCKA +#define PWMPRCLK_PCKB _PWMPRCLK.MergedBits.grpPCKB + + +/*** PWMCAE - PWM Center Align Enable Register; 0x000000E4 ***/ +typedef union { + byte Byte; + struct { + byte CAE0 :1; /* Center Aligned Output Mode on channel 0 */ + byte CAE1 :1; /* Center Aligned Output Mode on channel 1 */ + byte CAE2 :1; /* Center Aligned Output Mode on channel 2 */ + byte CAE3 :1; /* Center Aligned Output Mode on channel 3 */ + byte CAE4 :1; /* Center Aligned Output Mode on channel 4 */ + byte CAE5 :1; /* Center Aligned Output Mode on channel 5 */ + byte CAE6 :1; /* Center Aligned Output Mode on channel 6 */ + byte CAE7 :1; /* Center Aligned Output Mode on channel 7 */ + } Bits; + struct { + byte grpCAE :8; + } MergedBits; +} PWMCAESTR; +extern volatile PWMCAESTR _PWMCAE @(REG_BASE + 0x000000E4); +#define PWMCAE _PWMCAE.Byte +#define PWMCAE_CAE0 _PWMCAE.Bits.CAE0 +#define PWMCAE_CAE1 _PWMCAE.Bits.CAE1 +#define PWMCAE_CAE2 _PWMCAE.Bits.CAE2 +#define PWMCAE_CAE3 _PWMCAE.Bits.CAE3 +#define PWMCAE_CAE4 _PWMCAE.Bits.CAE4 +#define PWMCAE_CAE5 _PWMCAE.Bits.CAE5 +#define PWMCAE_CAE6 _PWMCAE.Bits.CAE6 +#define PWMCAE_CAE7 _PWMCAE.Bits.CAE7 +#define PWMCAE_CAE _PWMCAE.MergedBits.grpCAE + + +/*** PWMCTL - PWM Control Register; 0x000000E5 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte PFRZ :1; /* PWM Counters Stop in Freeze Mode */ + byte PSWAI :1; /* PWM Stops in Wait Mode */ + byte CON01 :1; /* Concatenate channels 0 and 1 */ + byte CON23 :1; /* Concatenate channels 2 and 3 */ + byte CON45 :1; /* Concatenate channels 4 and 5 */ + byte CON67 :1; /* Concatenate channels 6 and 7 */ + } Bits; +} PWMCTLSTR; +extern volatile PWMCTLSTR _PWMCTL @(REG_BASE + 0x000000E5); +#define PWMCTL _PWMCTL.Byte +#define PWMCTL_PFRZ _PWMCTL.Bits.PFRZ +#define PWMCTL_PSWAI _PWMCTL.Bits.PSWAI +#define PWMCTL_CON01 _PWMCTL.Bits.CON01 +#define PWMCTL_CON23 _PWMCTL.Bits.CON23 +#define PWMCTL_CON45 _PWMCTL.Bits.CON45 +#define PWMCTL_CON67 _PWMCTL.Bits.CON67 + + +/*** PWMSCLA - PWM Scale A Register; 0x000000E8 ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* PWM Scale A Bit 0 */ + byte BIT1 :1; /* PWM Scale A Bit 1 */ + byte BIT2 :1; /* PWM Scale A Bit 2 */ + byte BIT3 :1; /* PWM Scale A Bit 3 */ + byte BIT4 :1; /* PWM Scale A Bit 4 */ + byte BIT5 :1; /* PWM Scale A Bit 5 */ + byte BIT6 :1; /* PWM Scale A Bit 6 */ + byte BIT7 :1; /* PWM Scale A Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} PWMSCLASTR; +extern volatile PWMSCLASTR _PWMSCLA @(REG_BASE + 0x000000E8); +#define PWMSCLA _PWMSCLA.Byte +#define PWMSCLA_BIT0 _PWMSCLA.Bits.BIT0 +#define PWMSCLA_BIT1 _PWMSCLA.Bits.BIT1 +#define PWMSCLA_BIT2 _PWMSCLA.Bits.BIT2 +#define PWMSCLA_BIT3 _PWMSCLA.Bits.BIT3 +#define PWMSCLA_BIT4 _PWMSCLA.Bits.BIT4 +#define PWMSCLA_BIT5 _PWMSCLA.Bits.BIT5 +#define PWMSCLA_BIT6 _PWMSCLA.Bits.BIT6 +#define PWMSCLA_BIT7 _PWMSCLA.Bits.BIT7 +#define PWMSCLA_BIT _PWMSCLA.MergedBits.grpBIT + + +/*** PWMSCLB - PWM Scale B Register; 0x000000E9 ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* PWM Scale B Bit 0 */ + byte BIT1 :1; /* PWM Scale B Bit 1 */ + byte BIT2 :1; /* PWM Scale B Bit 2 */ + byte BIT3 :1; /* PWM Scale B Bit 3 */ + byte BIT4 :1; /* PWM Scale B Bit 4 */ + byte BIT5 :1; /* PWM Scale B Bit 5 */ + byte BIT6 :1; /* PWM Scale B Bit 6 */ + byte BIT7 :1; /* PWM Scale B Bit 7 */ + } Bits; + struct { + byte grpBIT :8; + } MergedBits; +} PWMSCLBSTR; +extern volatile PWMSCLBSTR _PWMSCLB @(REG_BASE + 0x000000E9); +#define PWMSCLB _PWMSCLB.Byte +#define PWMSCLB_BIT0 _PWMSCLB.Bits.BIT0 +#define PWMSCLB_BIT1 _PWMSCLB.Bits.BIT1 +#define PWMSCLB_BIT2 _PWMSCLB.Bits.BIT2 +#define PWMSCLB_BIT3 _PWMSCLB.Bits.BIT3 +#define PWMSCLB_BIT4 _PWMSCLB.Bits.BIT4 +#define PWMSCLB_BIT5 _PWMSCLB.Bits.BIT5 +#define PWMSCLB_BIT6 _PWMSCLB.Bits.BIT6 +#define PWMSCLB_BIT7 _PWMSCLB.Bits.BIT7 +#define PWMSCLB_BIT _PWMSCLB.MergedBits.grpBIT + + +/*** PWMSDN - PWM Shutdown Register; 0x000000FE ***/ +typedef union { + byte Byte; + struct { + byte PWM7ENA :1; /* PWM emergency shutdown Enable */ + byte PWM7INL :1; /* PWM shutdown active input level for ch. 7 */ + byte PWM7IN :1; /* PWM channel 7 input status */ + byte :1; + byte PWMLVL :1; /* PWM shutdown output Level */ + byte PWMRSTRT :1; /* PWM Restart */ + byte PWMIE :1; /* PWM Interrupt Enable */ + byte PWMIF :1; /* PWM Interrupt Flag */ + } Bits; +} PWMSDNSTR; +extern volatile PWMSDNSTR _PWMSDN @(REG_BASE + 0x000000FE); +#define PWMSDN _PWMSDN.Byte +#define PWMSDN_PWM7ENA _PWMSDN.Bits.PWM7ENA +#define PWMSDN_PWM7INL _PWMSDN.Bits.PWM7INL +#define PWMSDN_PWM7IN _PWMSDN.Bits.PWM7IN +#define PWMSDN_PWMLVL _PWMSDN.Bits.PWMLVL +#define PWMSDN_PWMRSTRT _PWMSDN.Bits.PWMRSTRT +#define PWMSDN_PWMIE _PWMSDN.Bits.PWMIE +#define PWMSDN_PWMIF _PWMSDN.Bits.PWMIF + + +/*** FCLKDIV - Flash Clock Divider Register; 0x00000100 ***/ +typedef union { + byte Byte; + struct { + byte FDIV0 :1; /* Flash Clock Divider Bit 0 */ + byte FDIV1 :1; /* Flash Clock Divider Bit 1 */ + byte FDIV2 :1; /* Flash Clock Divider Bit 2 */ + byte FDIV3 :1; /* Flash Clock Divider Bit 3 */ + byte FDIV4 :1; /* Flash Clock Divider Bit 4 */ + byte FDIV5 :1; /* Flash Clock Divider Bit 5 */ + byte PRDIV8 :1; /* Enable Prescaler by 8 */ + byte FDIVLD :1; /* Flash Clock Divider Loaded */ + } Bits; + struct { + byte grpFDIV :6; + byte grpPRDIV_8 :1; + byte :1; + } MergedBits; +} FCLKDIVSTR; +extern volatile FCLKDIVSTR _FCLKDIV @(REG_BASE + 0x00000100); +#define FCLKDIV _FCLKDIV.Byte +#define FCLKDIV_FDIV0 _FCLKDIV.Bits.FDIV0 +#define FCLKDIV_FDIV1 _FCLKDIV.Bits.FDIV1 +#define FCLKDIV_FDIV2 _FCLKDIV.Bits.FDIV2 +#define FCLKDIV_FDIV3 _FCLKDIV.Bits.FDIV3 +#define FCLKDIV_FDIV4 _FCLKDIV.Bits.FDIV4 +#define FCLKDIV_FDIV5 _FCLKDIV.Bits.FDIV5 +#define FCLKDIV_PRDIV8 _FCLKDIV.Bits.PRDIV8 +#define FCLKDIV_FDIVLD _FCLKDIV.Bits.FDIVLD +#define FCLKDIV_FDIV _FCLKDIV.MergedBits.grpFDIV + + +/*** FSEC - Flash Security Register; 0x00000101 ***/ +typedef union { + byte Byte; + struct { + byte SEC0 :1; /* Memory security bit 0 */ + byte SEC1 :1; /* Memory security bit 1 */ + byte NV2 :1; /* Non Volatile flag bit 2 */ + byte NV3 :1; /* Non Volatile flag bit 3 */ + byte NV4 :1; /* Non Volatile flag bit 4 */ + byte NV5 :1; /* Non Volatile flag bit 5 */ + byte NV6 :1; /* Non Volatile flag bit 6 */ + byte KEYEN :1; /* Enable backdoor key to security */ + } Bits; + struct { + byte grpSEC :2; + byte grpNV_2 :5; + byte :1; + } MergedBits; +} FSECSTR; +extern volatile FSECSTR _FSEC @(REG_BASE + 0x00000101); +#define FSEC _FSEC.Byte +#define FSEC_SEC0 _FSEC.Bits.SEC0 +#define FSEC_SEC1 _FSEC.Bits.SEC1 +#define FSEC_NV2 _FSEC.Bits.NV2 +#define FSEC_NV3 _FSEC.Bits.NV3 +#define FSEC_NV4 _FSEC.Bits.NV4 +#define FSEC_NV5 _FSEC.Bits.NV5 +#define FSEC_NV6 _FSEC.Bits.NV6 +#define FSEC_KEYEN _FSEC.Bits.KEYEN +#define FSEC_SEC _FSEC.MergedBits.grpSEC +#define FSEC_NV_2 _FSEC.MergedBits.grpNV_2 +#define FSEC_NV FSEC_NV_2 + + +/*** FCNFG - Flash Configuration Register; 0x00000103 ***/ +typedef union { + byte Byte; + struct { + byte BKSEL0 :1; /* Register bank select 0 */ + byte BKSEL1 :1; /* Register bank select 1 */ + byte :1; + byte :1; + byte :1; + byte KEYACC :1; /* Enable Security Key Writing */ + byte CCIE :1; /* Command Complete Interrupt Enable */ + byte CBEIE :1; /* Command Buffers Empty Interrupt Enable */ + } Bits; + struct { + byte grpBKSEL :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} FCNFGSTR; +extern volatile FCNFGSTR _FCNFG @(REG_BASE + 0x00000103); +#define FCNFG _FCNFG.Byte +#define FCNFG_BKSEL0 _FCNFG.Bits.BKSEL0 +#define FCNFG_BKSEL1 _FCNFG.Bits.BKSEL1 +#define FCNFG_KEYACC _FCNFG.Bits.KEYACC +#define FCNFG_CCIE _FCNFG.Bits.CCIE +#define FCNFG_CBEIE _FCNFG.Bits.CBEIE +#define FCNFG_BKSEL _FCNFG.MergedBits.grpBKSEL + + +/*** FPROT - Flash Protection Register; 0x00000104 ***/ +typedef union { + byte Byte; + struct { + byte FPLS0 :1; /* Flash Protection Lower Address size 0 */ + byte FPLS1 :1; /* Flash Protection Lower Address size 1 */ + byte FPLDIS :1; /* Flash Protection Lower address range disable */ + byte FPHS0 :1; /* Flash Protection Higher address size 0 */ + byte FPHS1 :1; /* Flash Protection Higher address size 1 */ + byte FPHDIS :1; /* Flash Protection Higher address range disable */ + byte NV6 :1; /* Non Volatile Flag Bit */ + byte FPOPEN :1; /* Opens the flash block or subsections of it for program or erase */ + } Bits; + struct { + byte grpFPLS :2; + byte :1; + byte grpFPHS :2; + byte :1; + byte grpNV_6 :1; + byte :1; + } MergedBits; +} FPROTSTR; +extern volatile FPROTSTR _FPROT @(REG_BASE + 0x00000104); +#define FPROT _FPROT.Byte +#define FPROT_FPLS0 _FPROT.Bits.FPLS0 +#define FPROT_FPLS1 _FPROT.Bits.FPLS1 +#define FPROT_FPLDIS _FPROT.Bits.FPLDIS +#define FPROT_FPHS0 _FPROT.Bits.FPHS0 +#define FPROT_FPHS1 _FPROT.Bits.FPHS1 +#define FPROT_FPHDIS _FPROT.Bits.FPHDIS +#define FPROT_NV6 _FPROT.Bits.NV6 +#define FPROT_FPOPEN _FPROT.Bits.FPOPEN +#define FPROT_FPLS _FPROT.MergedBits.grpFPLS +#define FPROT_FPHS _FPROT.MergedBits.grpFPHS + + +/*** FSTAT - Flash Status Register; 0x00000105 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte BLANK :1; /* Blank Verify Flag */ + byte :1; + byte ACCERR :1; /* Access error */ + byte PVIOL :1; /* Protection violation */ + byte CCIF :1; /* Command Complete Interrupt Flag */ + byte CBEIF :1; /* Command Buffers Empty Interrupt Flag */ + } Bits; +} FSTATSTR; +extern volatile FSTATSTR _FSTAT @(REG_BASE + 0x00000105); +#define FSTAT _FSTAT.Byte +#define FSTAT_BLANK _FSTAT.Bits.BLANK +#define FSTAT_ACCERR _FSTAT.Bits.ACCERR +#define FSTAT_PVIOL _FSTAT.Bits.PVIOL +#define FSTAT_CCIF _FSTAT.Bits.CCIF +#define FSTAT_CBEIF _FSTAT.Bits.CBEIF + + +/*** FCMD - Flash Command Buffer and Register; 0x00000106 ***/ +typedef union { + byte Byte; + struct { + byte CMDB0 :1; /* NVM User Mode Command Bit 0 */ + byte :1; + byte CMDB2 :1; /* NVM User Mode Command Bit 2 */ + byte :1; + byte :1; + byte CMDB5 :1; /* NVM User Mode Command Bit 5 */ + byte CMDB6 :1; /* NVM User Mode Command Bit 6 */ + byte :1; + } Bits; + struct { + byte grpCMDB :1; + byte :1; + byte grpCMDB_2 :1; + byte :1; + byte :1; + byte grpCMDB_5 :2; + byte :1; + } MergedBits; +} FCMDSTR; +extern volatile FCMDSTR _FCMD @(REG_BASE + 0x00000106); +#define FCMD _FCMD.Byte +#define FCMD_CMDB0 _FCMD.Bits.CMDB0 +#define FCMD_CMDB2 _FCMD.Bits.CMDB2 +#define FCMD_CMDB5 _FCMD.Bits.CMDB5 +#define FCMD_CMDB6 _FCMD.Bits.CMDB6 +#define FCMD_CMDB_5 _FCMD.MergedBits.grpCMDB_5 +#define FCMD_CMDB FCMD_CMDB_5 + + +/*** CANCTL0 - MSCAN Control 0 Register; 0x00000140 ***/ +typedef union { + byte Byte; + struct { + byte INITRQ :1; /* Initialization Mode Request */ + byte SLPRQ :1; /* Sleep Mode Request */ + byte WUPE :1; /* Wake-Up Enable */ + byte TIME :1; /* Timer Enable */ + byte SYNCH :1; /* Synchronized Status */ + byte CSWAI :1; /* CAN Stops in Wait Mode */ + byte RXACT :1; /* Receiver Active Status */ + byte RXFRM :1; /* Received Frame Flag */ + } Bits; +} CANCTL0STR; +extern volatile CANCTL0STR _CANCTL0 @(REG_BASE + 0x00000140); +#define CANCTL0 _CANCTL0.Byte +#define CANCTL0_INITRQ _CANCTL0.Bits.INITRQ +#define CANCTL0_SLPRQ _CANCTL0.Bits.SLPRQ +#define CANCTL0_WUPE _CANCTL0.Bits.WUPE +#define CANCTL0_TIME _CANCTL0.Bits.TIME +#define CANCTL0_SYNCH _CANCTL0.Bits.SYNCH +#define CANCTL0_CSWAI _CANCTL0.Bits.CSWAI +#define CANCTL0_RXACT _CANCTL0.Bits.RXACT +#define CANCTL0_RXFRM _CANCTL0.Bits.RXFRM + + +/*** CANCTL1 - MSCAN Control 1 Register; 0x00000141 ***/ +typedef union { + byte Byte; + struct { + byte INITAK :1; /* Initialization Mode Acknowledge */ + byte SLPAK :1; /* Sleep Mode Acknowledge */ + byte WUPM :1; /* Wake-Up Mode */ + byte :1; + byte LISTEN :1; /* Listen Only Mode */ + byte LOOPB :1; /* Loop Back Self Test Mode */ + byte CLKSRC :1; /* MSCAN Clock Source */ + byte CANE :1; /* MSCAN Enable */ + } Bits; +} CANCTL1STR; +extern volatile CANCTL1STR _CANCTL1 @(REG_BASE + 0x00000141); +#define CANCTL1 _CANCTL1.Byte +#define CANCTL1_INITAK _CANCTL1.Bits.INITAK +#define CANCTL1_SLPAK _CANCTL1.Bits.SLPAK +#define CANCTL1_WUPM _CANCTL1.Bits.WUPM +#define CANCTL1_LISTEN _CANCTL1.Bits.LISTEN +#define CANCTL1_LOOPB _CANCTL1.Bits.LOOPB +#define CANCTL1_CLKSRC _CANCTL1.Bits.CLKSRC +#define CANCTL1_CANE _CANCTL1.Bits.CANE + + +/*** CANBTR0 - MSCAN Bus Timing Register 0; 0x00000142 ***/ +typedef union { + byte Byte; + struct { + byte BRP0 :1; /* Baud Rate Prescaler 0 */ + byte BRP1 :1; /* Baud Rate Prescaler 1 */ + byte BRP2 :1; /* Baud Rate Prescaler 2 */ + byte BRP3 :1; /* Baud Rate Prescaler 3 */ + byte BRP4 :1; /* Baud Rate Prescaler 4 */ + byte BRP5 :1; /* Baud Rate Prescaler 5 */ + byte SJW0 :1; /* Synchronization Jump Width 0 */ + byte SJW1 :1; /* Synchronization Jump Width 1 */ + } Bits; + struct { + byte grpBRP :6; + byte grpSJW :2; + } MergedBits; +} CANBTR0STR; +extern volatile CANBTR0STR _CANBTR0 @(REG_BASE + 0x00000142); +#define CANBTR0 _CANBTR0.Byte +#define CANBTR0_BRP0 _CANBTR0.Bits.BRP0 +#define CANBTR0_BRP1 _CANBTR0.Bits.BRP1 +#define CANBTR0_BRP2 _CANBTR0.Bits.BRP2 +#define CANBTR0_BRP3 _CANBTR0.Bits.BRP3 +#define CANBTR0_BRP4 _CANBTR0.Bits.BRP4 +#define CANBTR0_BRP5 _CANBTR0.Bits.BRP5 +#define CANBTR0_SJW0 _CANBTR0.Bits.SJW0 +#define CANBTR0_SJW1 _CANBTR0.Bits.SJW1 +#define CANBTR0_BRP _CANBTR0.MergedBits.grpBRP +#define CANBTR0_SJW _CANBTR0.MergedBits.grpSJW + + +/*** CANBTR1 - MSCAN Bus Timing Register 1; 0x00000143 ***/ +typedef union { + byte Byte; + struct { + byte TSEG10 :1; /* Time Segment 1 */ + byte TSEG11 :1; /* Time Segment 1 */ + byte TSEG12 :1; /* Time Segment 1 */ + byte TSEG13 :1; /* Time Segment 1 */ + byte TSEG20 :1; /* Time Segment 2 */ + byte TSEG21 :1; /* Time Segment 2 */ + byte TSEG22 :1; /* Time Segment 2 */ + byte SAMP :1; /* Sampling */ + } Bits; + struct { + byte grpTSEG_10 :4; + byte grpTSEG_20 :3; + byte :1; + } MergedBits; +} CANBTR1STR; +extern volatile CANBTR1STR _CANBTR1 @(REG_BASE + 0x00000143); +#define CANBTR1 _CANBTR1.Byte +#define CANBTR1_TSEG10 _CANBTR1.Bits.TSEG10 +#define CANBTR1_TSEG11 _CANBTR1.Bits.TSEG11 +#define CANBTR1_TSEG12 _CANBTR1.Bits.TSEG12 +#define CANBTR1_TSEG13 _CANBTR1.Bits.TSEG13 +#define CANBTR1_TSEG20 _CANBTR1.Bits.TSEG20 +#define CANBTR1_TSEG21 _CANBTR1.Bits.TSEG21 +#define CANBTR1_TSEG22 _CANBTR1.Bits.TSEG22 +#define CANBTR1_SAMP _CANBTR1.Bits.SAMP +#define CANBTR1_TSEG_10 _CANBTR1.MergedBits.grpTSEG_10 +#define CANBTR1_TSEG_20 _CANBTR1.MergedBits.grpTSEG_20 +#define CANBTR1_TSEG CANBTR1_TSEG_10 + + +/*** CANRFLG - MSCAN Receiver Flag Register; 0x00000144 ***/ +typedef union { + byte Byte; + struct { + byte RXF :1; /* Receive Buffer Full */ + byte OVRIF :1; /* Overrun Interrupt Flag */ + byte TSTAT0 :1; /* Transmitter Status Bit 0 */ + byte TSTAT1 :1; /* Transmitter Status Bit 1 */ + byte RSTAT0 :1; /* Receiver Status Bit 0 */ + byte RSTAT1 :1; /* Receiver Status Bit 1 */ + byte CSCIF :1; /* CAN Status Change Interrupt Flag */ + byte WUPIF :1; /* Wake-up Interrupt Flag */ + } Bits; + struct { + byte :1; + byte :1; + byte grpTSTAT :2; + byte grpRSTAT :2; + byte :1; + byte :1; + } MergedBits; +} CANRFLGSTR; +extern volatile CANRFLGSTR _CANRFLG @(REG_BASE + 0x00000144); +#define CANRFLG _CANRFLG.Byte +#define CANRFLG_RXF _CANRFLG.Bits.RXF +#define CANRFLG_OVRIF _CANRFLG.Bits.OVRIF +#define CANRFLG_TSTAT0 _CANRFLG.Bits.TSTAT0 +#define CANRFLG_TSTAT1 _CANRFLG.Bits.TSTAT1 +#define CANRFLG_RSTAT0 _CANRFLG.Bits.RSTAT0 +#define CANRFLG_RSTAT1 _CANRFLG.Bits.RSTAT1 +#define CANRFLG_CSCIF _CANRFLG.Bits.CSCIF +#define CANRFLG_WUPIF _CANRFLG.Bits.WUPIF +#define CANRFLG_TSTAT _CANRFLG.MergedBits.grpTSTAT +#define CANRFLG_RSTAT _CANRFLG.MergedBits.grpRSTAT + + +/*** CANRIER - MSCAN Receiver Interrupt Enable Register; 0x00000145 ***/ +typedef union { + byte Byte; + struct { + byte RXFIE :1; /* Receiver Full Interrupt Enable */ + byte OVRIE :1; /* Overrun Interrupt Enable */ + byte TSTATE0 :1; /* Transmitter Status Change Enable 0 */ + byte TSTATE1 :1; /* Transmitter Status Change Enable 1 */ + byte RSTATE0 :1; /* Receiver Status Change Enable 0 */ + byte RSTATE1 :1; /* Receiver Status Change Enable 1 */ + byte CSCIE :1; /* CAN Status Change Interrupt Enable */ + byte WUPIE :1; /* Wake-up Interrupt Enable */ + } Bits; + struct { + byte :1; + byte :1; + byte grpTSTATE :2; + byte grpRSTATE :2; + byte :1; + byte :1; + } MergedBits; +} CANRIERSTR; +extern volatile CANRIERSTR _CANRIER @(REG_BASE + 0x00000145); +#define CANRIER _CANRIER.Byte +#define CANRIER_RXFIE _CANRIER.Bits.RXFIE +#define CANRIER_OVRIE _CANRIER.Bits.OVRIE +#define CANRIER_TSTATE0 _CANRIER.Bits.TSTATE0 +#define CANRIER_TSTATE1 _CANRIER.Bits.TSTATE1 +#define CANRIER_RSTATE0 _CANRIER.Bits.RSTATE0 +#define CANRIER_RSTATE1 _CANRIER.Bits.RSTATE1 +#define CANRIER_CSCIE _CANRIER.Bits.CSCIE +#define CANRIER_WUPIE _CANRIER.Bits.WUPIE +#define CANRIER_TSTATE _CANRIER.MergedBits.grpTSTATE +#define CANRIER_RSTATE _CANRIER.MergedBits.grpRSTATE + + +/*** CANTFLG - MSCAN Transmitter Flag Register; 0x00000146 ***/ +typedef union { + byte Byte; + struct { + byte TXE0 :1; /* Transmitter Buffer Empty 0 */ + byte TXE1 :1; /* Transmitter Buffer Empty 1 */ + byte TXE2 :1; /* Transmitter Buffer Empty 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpTXE :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CANTFLGSTR; +extern volatile CANTFLGSTR _CANTFLG @(REG_BASE + 0x00000146); +#define CANTFLG _CANTFLG.Byte +#define CANTFLG_TXE0 _CANTFLG.Bits.TXE0 +#define CANTFLG_TXE1 _CANTFLG.Bits.TXE1 +#define CANTFLG_TXE2 _CANTFLG.Bits.TXE2 +#define CANTFLG_TXE _CANTFLG.MergedBits.grpTXE + + +/*** CANTIER - MSCAN Transmitter Interrupt Enable Register; 0x00000147 ***/ +typedef union { + byte Byte; + struct { + byte TXEIE0 :1; /* Transmitter Empty Interrupt Enable 0 */ + byte TXEIE1 :1; /* Transmitter Empty Interrupt Enable 1 */ + byte TXEIE2 :1; /* Transmitter Empty Interrupt Enable 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpTXEIE :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CANTIERSTR; +extern volatile CANTIERSTR _CANTIER @(REG_BASE + 0x00000147); +#define CANTIER _CANTIER.Byte +#define CANTIER_TXEIE0 _CANTIER.Bits.TXEIE0 +#define CANTIER_TXEIE1 _CANTIER.Bits.TXEIE1 +#define CANTIER_TXEIE2 _CANTIER.Bits.TXEIE2 +#define CANTIER_TXEIE _CANTIER.MergedBits.grpTXEIE + + +/*** CANTARQ - MSCAN Transmitter Message Abort Request; 0x00000148 ***/ +typedef union { + byte Byte; + struct { + byte ABTRQ0 :1; /* Abort Request 0 */ + byte ABTRQ1 :1; /* Abort Request 1 */ + byte ABTRQ2 :1; /* Abort Request 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpABTRQ :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CANTARQSTR; +extern volatile CANTARQSTR _CANTARQ @(REG_BASE + 0x00000148); +#define CANTARQ _CANTARQ.Byte +#define CANTARQ_ABTRQ0 _CANTARQ.Bits.ABTRQ0 +#define CANTARQ_ABTRQ1 _CANTARQ.Bits.ABTRQ1 +#define CANTARQ_ABTRQ2 _CANTARQ.Bits.ABTRQ2 +#define CANTARQ_ABTRQ _CANTARQ.MergedBits.grpABTRQ + + +/*** CANTAAK - MSCAN Transmitter Message Abort Control; 0x00000149 ***/ +typedef union { + byte Byte; + struct { + byte ABTAK0 :1; /* Abort Acknowledge 0 */ + byte ABTAK1 :1; /* Abort Acknowledge 1 */ + byte ABTAK2 :1; /* Abort Acknowledge 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpABTAK :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CANTAAKSTR; +extern volatile CANTAAKSTR _CANTAAK @(REG_BASE + 0x00000149); +#define CANTAAK _CANTAAK.Byte +#define CANTAAK_ABTAK0 _CANTAAK.Bits.ABTAK0 +#define CANTAAK_ABTAK1 _CANTAAK.Bits.ABTAK1 +#define CANTAAK_ABTAK2 _CANTAAK.Bits.ABTAK2 +#define CANTAAK_ABTAK _CANTAAK.MergedBits.grpABTAK + + +/*** CANTBSEL - MSCAN Transmit Buffer Selection; 0x0000014A ***/ +typedef union { + byte Byte; + struct { + byte TX0 :1; /* Transmit Buffer Select 0 */ + byte TX1 :1; /* Transmit Buffer Select 1 */ + byte TX2 :1; /* Transmit Buffer Select 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpTX :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CANTBSELSTR; +extern volatile CANTBSELSTR _CANTBSEL @(REG_BASE + 0x0000014A); +#define CANTBSEL _CANTBSEL.Byte +#define CANTBSEL_TX0 _CANTBSEL.Bits.TX0 +#define CANTBSEL_TX1 _CANTBSEL.Bits.TX1 +#define CANTBSEL_TX2 _CANTBSEL.Bits.TX2 +#define CANTBSEL_TX _CANTBSEL.MergedBits.grpTX + + +/*** CANIDAC - MSCAN Identifier Acceptance Control Register; 0x0000014B ***/ +typedef union { + byte Byte; + struct { + byte IDHIT0 :1; /* Identifier Acceptance Hit Indicator 0 */ + byte IDHIT1 :1; /* Identifier Acceptance Hit Indicator 1 */ + byte IDHIT2 :1; /* Identifier Acceptance Hit Indicator 2 */ + byte :1; + byte IDAM0 :1; /* Identifier Acceptance Mode 0 */ + byte IDAM1 :1; /* Identifier Acceptance Mode 1 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpIDHIT :3; + byte :1; + byte grpIDAM :2; + byte :1; + byte :1; + } MergedBits; +} CANIDACSTR; +extern volatile CANIDACSTR _CANIDAC @(REG_BASE + 0x0000014B); +#define CANIDAC _CANIDAC.Byte +#define CANIDAC_IDHIT0 _CANIDAC.Bits.IDHIT0 +#define CANIDAC_IDHIT1 _CANIDAC.Bits.IDHIT1 +#define CANIDAC_IDHIT2 _CANIDAC.Bits.IDHIT2 +#define CANIDAC_IDAM0 _CANIDAC.Bits.IDAM0 +#define CANIDAC_IDAM1 _CANIDAC.Bits.IDAM1 +#define CANIDAC_IDHIT _CANIDAC.MergedBits.grpIDHIT +#define CANIDAC_IDAM _CANIDAC.MergedBits.grpIDAM + + +/*** CANRXERR - MSCAN Receive Error Counter Register; 0x0000014E ***/ +typedef union { + byte Byte; + struct { + byte RXERR0 :1; /* Bit 0 */ + byte RXERR1 :1; /* Bit 1 */ + byte RXERR2 :1; /* Bit 2 */ + byte RXERR3 :1; /* Bit 3 */ + byte RXERR4 :1; /* Bit 4 */ + byte RXERR5 :1; /* Bit 5 */ + byte RXERR6 :1; /* Bit 6 */ + byte RXERR7 :1; /* Bit 7 */ + } Bits; + struct { + byte grpRXERR :8; + } MergedBits; +} CANRXERRSTR; +extern volatile CANRXERRSTR _CANRXERR @(REG_BASE + 0x0000014E); +#define CANRXERR _CANRXERR.Byte +#define CANRXERR_RXERR0 _CANRXERR.Bits.RXERR0 +#define CANRXERR_RXERR1 _CANRXERR.Bits.RXERR1 +#define CANRXERR_RXERR2 _CANRXERR.Bits.RXERR2 +#define CANRXERR_RXERR3 _CANRXERR.Bits.RXERR3 +#define CANRXERR_RXERR4 _CANRXERR.Bits.RXERR4 +#define CANRXERR_RXERR5 _CANRXERR.Bits.RXERR5 +#define CANRXERR_RXERR6 _CANRXERR.Bits.RXERR6 +#define CANRXERR_RXERR7 _CANRXERR.Bits.RXERR7 +#define CANRXERR_RXERR _CANRXERR.MergedBits.grpRXERR + + +/*** CANTXERR - MSCAN Transmit Error Counter Register; 0x0000014F ***/ +typedef union { + byte Byte; + struct { + byte TXERR0 :1; /* Bit 0 */ + byte TXERR1 :1; /* Bit 1 */ + byte TXERR2 :1; /* Bit 2 */ + byte TXERR3 :1; /* Bit 3 */ + byte TXERR4 :1; /* Bit 4 */ + byte TXERR5 :1; /* Bit 5 */ + byte TXERR6 :1; /* Bit 6 */ + byte TXERR7 :1; /* Bit 7 */ + } Bits; + struct { + byte grpTXERR :8; + } MergedBits; +} CANTXERRSTR; +extern volatile CANTXERRSTR _CANTXERR @(REG_BASE + 0x0000014F); +#define CANTXERR _CANTXERR.Byte +#define CANTXERR_TXERR0 _CANTXERR.Bits.TXERR0 +#define CANTXERR_TXERR1 _CANTXERR.Bits.TXERR1 +#define CANTXERR_TXERR2 _CANTXERR.Bits.TXERR2 +#define CANTXERR_TXERR3 _CANTXERR.Bits.TXERR3 +#define CANTXERR_TXERR4 _CANTXERR.Bits.TXERR4 +#define CANTXERR_TXERR5 _CANTXERR.Bits.TXERR5 +#define CANTXERR_TXERR6 _CANTXERR.Bits.TXERR6 +#define CANTXERR_TXERR7 _CANTXERR.Bits.TXERR7 +#define CANTXERR_TXERR _CANTXERR.MergedBits.grpTXERR + + +/*** CANIDAR0 - MSCAN Identifier Acceptance Register 0; 0x00000150 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CANIDAR0STR; +extern volatile CANIDAR0STR _CANIDAR0 @(REG_BASE + 0x00000150); +#define CANIDAR0 _CANIDAR0.Byte +#define CANIDAR0_AC0 _CANIDAR0.Bits.AC0 +#define CANIDAR0_AC1 _CANIDAR0.Bits.AC1 +#define CANIDAR0_AC2 _CANIDAR0.Bits.AC2 +#define CANIDAR0_AC3 _CANIDAR0.Bits.AC3 +#define CANIDAR0_AC4 _CANIDAR0.Bits.AC4 +#define CANIDAR0_AC5 _CANIDAR0.Bits.AC5 +#define CANIDAR0_AC6 _CANIDAR0.Bits.AC6 +#define CANIDAR0_AC7 _CANIDAR0.Bits.AC7 +#define CANIDAR0_AC _CANIDAR0.MergedBits.grpAC + + +/*** CANIDAR1 - MSCAN Identifier Acceptance Register 1; 0x00000151 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CANIDAR1STR; +extern volatile CANIDAR1STR _CANIDAR1 @(REG_BASE + 0x00000151); +#define CANIDAR1 _CANIDAR1.Byte +#define CANIDAR1_AC0 _CANIDAR1.Bits.AC0 +#define CANIDAR1_AC1 _CANIDAR1.Bits.AC1 +#define CANIDAR1_AC2 _CANIDAR1.Bits.AC2 +#define CANIDAR1_AC3 _CANIDAR1.Bits.AC3 +#define CANIDAR1_AC4 _CANIDAR1.Bits.AC4 +#define CANIDAR1_AC5 _CANIDAR1.Bits.AC5 +#define CANIDAR1_AC6 _CANIDAR1.Bits.AC6 +#define CANIDAR1_AC7 _CANIDAR1.Bits.AC7 +#define CANIDAR1_AC _CANIDAR1.MergedBits.grpAC + + +/*** CANIDAR2 - MSCAN Identifier Acceptance Register 2; 0x00000152 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CANIDAR2STR; +extern volatile CANIDAR2STR _CANIDAR2 @(REG_BASE + 0x00000152); +#define CANIDAR2 _CANIDAR2.Byte +#define CANIDAR2_AC0 _CANIDAR2.Bits.AC0 +#define CANIDAR2_AC1 _CANIDAR2.Bits.AC1 +#define CANIDAR2_AC2 _CANIDAR2.Bits.AC2 +#define CANIDAR2_AC3 _CANIDAR2.Bits.AC3 +#define CANIDAR2_AC4 _CANIDAR2.Bits.AC4 +#define CANIDAR2_AC5 _CANIDAR2.Bits.AC5 +#define CANIDAR2_AC6 _CANIDAR2.Bits.AC6 +#define CANIDAR2_AC7 _CANIDAR2.Bits.AC7 +#define CANIDAR2_AC _CANIDAR2.MergedBits.grpAC + + +/*** CANIDAR3 - MSCAN Identifier Acceptance Register 3; 0x00000153 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CANIDAR3STR; +extern volatile CANIDAR3STR _CANIDAR3 @(REG_BASE + 0x00000153); +#define CANIDAR3 _CANIDAR3.Byte +#define CANIDAR3_AC0 _CANIDAR3.Bits.AC0 +#define CANIDAR3_AC1 _CANIDAR3.Bits.AC1 +#define CANIDAR3_AC2 _CANIDAR3.Bits.AC2 +#define CANIDAR3_AC3 _CANIDAR3.Bits.AC3 +#define CANIDAR3_AC4 _CANIDAR3.Bits.AC4 +#define CANIDAR3_AC5 _CANIDAR3.Bits.AC5 +#define CANIDAR3_AC6 _CANIDAR3.Bits.AC6 +#define CANIDAR3_AC7 _CANIDAR3.Bits.AC7 +#define CANIDAR3_AC _CANIDAR3.MergedBits.grpAC + + +/*** CANIDMR0 - MSCAN Identifier Mask Register 0; 0x00000154 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CANIDMR0STR; +extern volatile CANIDMR0STR _CANIDMR0 @(REG_BASE + 0x00000154); +#define CANIDMR0 _CANIDMR0.Byte +#define CANIDMR0_AM0 _CANIDMR0.Bits.AM0 +#define CANIDMR0_AM1 _CANIDMR0.Bits.AM1 +#define CANIDMR0_AM2 _CANIDMR0.Bits.AM2 +#define CANIDMR0_AM3 _CANIDMR0.Bits.AM3 +#define CANIDMR0_AM4 _CANIDMR0.Bits.AM4 +#define CANIDMR0_AM5 _CANIDMR0.Bits.AM5 +#define CANIDMR0_AM6 _CANIDMR0.Bits.AM6 +#define CANIDMR0_AM7 _CANIDMR0.Bits.AM7 +#define CANIDMR0_AM _CANIDMR0.MergedBits.grpAM + + +/*** CANIDMR1 - MSCAN Identifier Mask Register 1; 0x00000155 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CANIDMR1STR; +extern volatile CANIDMR1STR _CANIDMR1 @(REG_BASE + 0x00000155); +#define CANIDMR1 _CANIDMR1.Byte +#define CANIDMR1_AM0 _CANIDMR1.Bits.AM0 +#define CANIDMR1_AM1 _CANIDMR1.Bits.AM1 +#define CANIDMR1_AM2 _CANIDMR1.Bits.AM2 +#define CANIDMR1_AM3 _CANIDMR1.Bits.AM3 +#define CANIDMR1_AM4 _CANIDMR1.Bits.AM4 +#define CANIDMR1_AM5 _CANIDMR1.Bits.AM5 +#define CANIDMR1_AM6 _CANIDMR1.Bits.AM6 +#define CANIDMR1_AM7 _CANIDMR1.Bits.AM7 +#define CANIDMR1_AM _CANIDMR1.MergedBits.grpAM + + +/*** CANIDMR2 - MSCAN Identifier Mask Register 2; 0x00000156 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CANIDMR2STR; +extern volatile CANIDMR2STR _CANIDMR2 @(REG_BASE + 0x00000156); +#define CANIDMR2 _CANIDMR2.Byte +#define CANIDMR2_AM0 _CANIDMR2.Bits.AM0 +#define CANIDMR2_AM1 _CANIDMR2.Bits.AM1 +#define CANIDMR2_AM2 _CANIDMR2.Bits.AM2 +#define CANIDMR2_AM3 _CANIDMR2.Bits.AM3 +#define CANIDMR2_AM4 _CANIDMR2.Bits.AM4 +#define CANIDMR2_AM5 _CANIDMR2.Bits.AM5 +#define CANIDMR2_AM6 _CANIDMR2.Bits.AM6 +#define CANIDMR2_AM7 _CANIDMR2.Bits.AM7 +#define CANIDMR2_AM _CANIDMR2.MergedBits.grpAM + + +/*** CANIDMR3 - MSCAN Identifier Mask Register 3; 0x00000157 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CANIDMR3STR; +extern volatile CANIDMR3STR _CANIDMR3 @(REG_BASE + 0x00000157); +#define CANIDMR3 _CANIDMR3.Byte +#define CANIDMR3_AM0 _CANIDMR3.Bits.AM0 +#define CANIDMR3_AM1 _CANIDMR3.Bits.AM1 +#define CANIDMR3_AM2 _CANIDMR3.Bits.AM2 +#define CANIDMR3_AM3 _CANIDMR3.Bits.AM3 +#define CANIDMR3_AM4 _CANIDMR3.Bits.AM4 +#define CANIDMR3_AM5 _CANIDMR3.Bits.AM5 +#define CANIDMR3_AM6 _CANIDMR3.Bits.AM6 +#define CANIDMR3_AM7 _CANIDMR3.Bits.AM7 +#define CANIDMR3_AM _CANIDMR3.MergedBits.grpAM + + +/*** CANIDAR4 - MSCAN Identifier Acceptance Register 4; 0x00000158 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CANIDAR4STR; +extern volatile CANIDAR4STR _CANIDAR4 @(REG_BASE + 0x00000158); +#define CANIDAR4 _CANIDAR4.Byte +#define CANIDAR4_AC0 _CANIDAR4.Bits.AC0 +#define CANIDAR4_AC1 _CANIDAR4.Bits.AC1 +#define CANIDAR4_AC2 _CANIDAR4.Bits.AC2 +#define CANIDAR4_AC3 _CANIDAR4.Bits.AC3 +#define CANIDAR4_AC4 _CANIDAR4.Bits.AC4 +#define CANIDAR4_AC5 _CANIDAR4.Bits.AC5 +#define CANIDAR4_AC6 _CANIDAR4.Bits.AC6 +#define CANIDAR4_AC7 _CANIDAR4.Bits.AC7 +#define CANIDAR4_AC _CANIDAR4.MergedBits.grpAC + + +/*** CANIDAR5 - MSCAN Identifier Acceptance Register 5; 0x00000159 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CANIDAR5STR; +extern volatile CANIDAR5STR _CANIDAR5 @(REG_BASE + 0x00000159); +#define CANIDAR5 _CANIDAR5.Byte +#define CANIDAR5_AC0 _CANIDAR5.Bits.AC0 +#define CANIDAR5_AC1 _CANIDAR5.Bits.AC1 +#define CANIDAR5_AC2 _CANIDAR5.Bits.AC2 +#define CANIDAR5_AC3 _CANIDAR5.Bits.AC3 +#define CANIDAR5_AC4 _CANIDAR5.Bits.AC4 +#define CANIDAR5_AC5 _CANIDAR5.Bits.AC5 +#define CANIDAR5_AC6 _CANIDAR5.Bits.AC6 +#define CANIDAR5_AC7 _CANIDAR5.Bits.AC7 +#define CANIDAR5_AC _CANIDAR5.MergedBits.grpAC + + +/*** CANIDAR6 - MSCAN Identifier Acceptance Register 6; 0x0000015A ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CANIDAR6STR; +extern volatile CANIDAR6STR _CANIDAR6 @(REG_BASE + 0x0000015A); +#define CANIDAR6 _CANIDAR6.Byte +#define CANIDAR6_AC0 _CANIDAR6.Bits.AC0 +#define CANIDAR6_AC1 _CANIDAR6.Bits.AC1 +#define CANIDAR6_AC2 _CANIDAR6.Bits.AC2 +#define CANIDAR6_AC3 _CANIDAR6.Bits.AC3 +#define CANIDAR6_AC4 _CANIDAR6.Bits.AC4 +#define CANIDAR6_AC5 _CANIDAR6.Bits.AC5 +#define CANIDAR6_AC6 _CANIDAR6.Bits.AC6 +#define CANIDAR6_AC7 _CANIDAR6.Bits.AC7 +#define CANIDAR6_AC _CANIDAR6.MergedBits.grpAC + + +/*** CANIDAR7 - MSCAN Identifier Acceptance Register 7; 0x0000015B ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; + struct { + byte grpAC :8; + } MergedBits; +} CANIDAR7STR; +extern volatile CANIDAR7STR _CANIDAR7 @(REG_BASE + 0x0000015B); +#define CANIDAR7 _CANIDAR7.Byte +#define CANIDAR7_AC0 _CANIDAR7.Bits.AC0 +#define CANIDAR7_AC1 _CANIDAR7.Bits.AC1 +#define CANIDAR7_AC2 _CANIDAR7.Bits.AC2 +#define CANIDAR7_AC3 _CANIDAR7.Bits.AC3 +#define CANIDAR7_AC4 _CANIDAR7.Bits.AC4 +#define CANIDAR7_AC5 _CANIDAR7.Bits.AC5 +#define CANIDAR7_AC6 _CANIDAR7.Bits.AC6 +#define CANIDAR7_AC7 _CANIDAR7.Bits.AC7 +#define CANIDAR7_AC _CANIDAR7.MergedBits.grpAC + + +/*** CANIDMR4 - MSCAN Identifier Mask Register 4; 0x0000015C ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CANIDMR4STR; +extern volatile CANIDMR4STR _CANIDMR4 @(REG_BASE + 0x0000015C); +#define CANIDMR4 _CANIDMR4.Byte +#define CANIDMR4_AM0 _CANIDMR4.Bits.AM0 +#define CANIDMR4_AM1 _CANIDMR4.Bits.AM1 +#define CANIDMR4_AM2 _CANIDMR4.Bits.AM2 +#define CANIDMR4_AM3 _CANIDMR4.Bits.AM3 +#define CANIDMR4_AM4 _CANIDMR4.Bits.AM4 +#define CANIDMR4_AM5 _CANIDMR4.Bits.AM5 +#define CANIDMR4_AM6 _CANIDMR4.Bits.AM6 +#define CANIDMR4_AM7 _CANIDMR4.Bits.AM7 +#define CANIDMR4_AM _CANIDMR4.MergedBits.grpAM + + +/*** CANIDMR5 - MSCAN Identifier Mask Register 5; 0x0000015D ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CANIDMR5STR; +extern volatile CANIDMR5STR _CANIDMR5 @(REG_BASE + 0x0000015D); +#define CANIDMR5 _CANIDMR5.Byte +#define CANIDMR5_AM0 _CANIDMR5.Bits.AM0 +#define CANIDMR5_AM1 _CANIDMR5.Bits.AM1 +#define CANIDMR5_AM2 _CANIDMR5.Bits.AM2 +#define CANIDMR5_AM3 _CANIDMR5.Bits.AM3 +#define CANIDMR5_AM4 _CANIDMR5.Bits.AM4 +#define CANIDMR5_AM5 _CANIDMR5.Bits.AM5 +#define CANIDMR5_AM6 _CANIDMR5.Bits.AM6 +#define CANIDMR5_AM7 _CANIDMR5.Bits.AM7 +#define CANIDMR5_AM _CANIDMR5.MergedBits.grpAM + + +/*** CANIDMR6 - MSCAN Identifier Mask Register 6; 0x0000015E ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CANIDMR6STR; +extern volatile CANIDMR6STR _CANIDMR6 @(REG_BASE + 0x0000015E); +#define CANIDMR6 _CANIDMR6.Byte +#define CANIDMR6_AM0 _CANIDMR6.Bits.AM0 +#define CANIDMR6_AM1 _CANIDMR6.Bits.AM1 +#define CANIDMR6_AM2 _CANIDMR6.Bits.AM2 +#define CANIDMR6_AM3 _CANIDMR6.Bits.AM3 +#define CANIDMR6_AM4 _CANIDMR6.Bits.AM4 +#define CANIDMR6_AM5 _CANIDMR6.Bits.AM5 +#define CANIDMR6_AM6 _CANIDMR6.Bits.AM6 +#define CANIDMR6_AM7 _CANIDMR6.Bits.AM7 +#define CANIDMR6_AM _CANIDMR6.MergedBits.grpAM + + +/*** CANIDMR7 - MSCAN Identifier Mask Register 7; 0x0000015F ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; + struct { + byte grpAM :8; + } MergedBits; +} CANIDMR7STR; +extern volatile CANIDMR7STR _CANIDMR7 @(REG_BASE + 0x0000015F); +#define CANIDMR7 _CANIDMR7.Byte +#define CANIDMR7_AM0 _CANIDMR7.Bits.AM0 +#define CANIDMR7_AM1 _CANIDMR7.Bits.AM1 +#define CANIDMR7_AM2 _CANIDMR7.Bits.AM2 +#define CANIDMR7_AM3 _CANIDMR7.Bits.AM3 +#define CANIDMR7_AM4 _CANIDMR7.Bits.AM4 +#define CANIDMR7_AM5 _CANIDMR7.Bits.AM5 +#define CANIDMR7_AM6 _CANIDMR7.Bits.AM6 +#define CANIDMR7_AM7 _CANIDMR7.Bits.AM7 +#define CANIDMR7_AM _CANIDMR7.MergedBits.grpAM + + +/*** CANRXIDR0 - MSCAN Receive Identifier Register 0; 0x00000160 ***/ +typedef union { + byte Byte; + struct { + byte ID21 :1; /* Extended format identifier Bit 21 */ + byte ID22 :1; /* Extended format identifier Bit 22 */ + byte ID23 :1; /* Extended format identifier Bit 23 */ + byte ID24 :1; /* Extended format identifier Bit 24 */ + byte ID25 :1; /* Extended format identifier Bit 25 */ + byte ID26 :1; /* Extended format identifier Bit 26 */ + byte ID27 :1; /* Extended format identifier Bit 27 */ + byte ID28 :1; /* Extended format identifier Bit 28 */ + } Bits; + struct { + byte grpID_21 :8; + } MergedBits; +} CANRXIDR0STR; +extern volatile CANRXIDR0STR _CANRXIDR0 @(REG_BASE + 0x00000160); +#define CANRXIDR0 _CANRXIDR0.Byte +#define CANRXIDR0_ID21 _CANRXIDR0.Bits.ID21 +#define CANRXIDR0_ID22 _CANRXIDR0.Bits.ID22 +#define CANRXIDR0_ID23 _CANRXIDR0.Bits.ID23 +#define CANRXIDR0_ID24 _CANRXIDR0.Bits.ID24 +#define CANRXIDR0_ID25 _CANRXIDR0.Bits.ID25 +#define CANRXIDR0_ID26 _CANRXIDR0.Bits.ID26 +#define CANRXIDR0_ID27 _CANRXIDR0.Bits.ID27 +#define CANRXIDR0_ID28 _CANRXIDR0.Bits.ID28 +#define CANRXIDR0_ID_21 _CANRXIDR0.MergedBits.grpID_21 +#define CANRXIDR0_ID CANRXIDR0_ID_21 + + +/*** CANRXIDR1 - MSCAN Receive Identifier Register 1; 0x00000161 ***/ +typedef union { + byte Byte; + struct { + byte ID15 :1; /* Extended format identifier Bit 15 */ + byte ID16 :1; /* Extended format identifier Bit 16 */ + byte ID17 :1; /* Extended format identifier Bit 17 */ + byte IDE :1; /* ID Extended */ + byte SRR :1; /* Substitute Remote Request */ + byte ID18 :1; /* Extended format identifier Bit 18 */ + byte ID19 :1; /* Extended format identifier Bit 19 */ + byte ID20 :1; /* Extended format identifier Bit 20 */ + } Bits; + struct { + byte grpID_15 :3; + byte :1; + byte :1; + byte grpID_18 :3; + } MergedBits; +} CANRXIDR1STR; +extern volatile CANRXIDR1STR _CANRXIDR1 @(REG_BASE + 0x00000161); +#define CANRXIDR1 _CANRXIDR1.Byte +#define CANRXIDR1_ID15 _CANRXIDR1.Bits.ID15 +#define CANRXIDR1_ID16 _CANRXIDR1.Bits.ID16 +#define CANRXIDR1_ID17 _CANRXIDR1.Bits.ID17 +#define CANRXIDR1_IDE _CANRXIDR1.Bits.IDE +#define CANRXIDR1_SRR _CANRXIDR1.Bits.SRR +#define CANRXIDR1_ID18 _CANRXIDR1.Bits.ID18 +#define CANRXIDR1_ID19 _CANRXIDR1.Bits.ID19 +#define CANRXIDR1_ID20 _CANRXIDR1.Bits.ID20 +#define CANRXIDR1_ID_15 _CANRXIDR1.MergedBits.grpID_15 +#define CANRXIDR1_ID_18 _CANRXIDR1.MergedBits.grpID_18 +#define CANRXIDR1_ID CANRXIDR1_ID_15 + + +/*** CANRXIDR2 - MSCAN Receive Identifier Register 2; 0x00000162 ***/ +typedef union { + byte Byte; + struct { + byte ID7 :1; /* Extended format identifier Bit 7 */ + byte ID8 :1; /* Extended format identifier Bit 8 */ + byte ID9 :1; /* Extended format identifier Bit 9 */ + byte ID10 :1; /* Extended format identifier Bit 10 */ + byte ID11 :1; /* Extended format identifier Bit 11 */ + byte ID12 :1; /* Extended format identifier Bit 12 */ + byte ID13 :1; /* Extended format identifier Bit 13 */ + byte ID14 :1; /* Extended format identifier Bit 14 */ + } Bits; + struct { + byte grpID_7 :8; + } MergedBits; +} CANRXIDR2STR; +extern volatile CANRXIDR2STR _CANRXIDR2 @(REG_BASE + 0x00000162); +#define CANRXIDR2 _CANRXIDR2.Byte +#define CANRXIDR2_ID7 _CANRXIDR2.Bits.ID7 +#define CANRXIDR2_ID8 _CANRXIDR2.Bits.ID8 +#define CANRXIDR2_ID9 _CANRXIDR2.Bits.ID9 +#define CANRXIDR2_ID10 _CANRXIDR2.Bits.ID10 +#define CANRXIDR2_ID11 _CANRXIDR2.Bits.ID11 +#define CANRXIDR2_ID12 _CANRXIDR2.Bits.ID12 +#define CANRXIDR2_ID13 _CANRXIDR2.Bits.ID13 +#define CANRXIDR2_ID14 _CANRXIDR2.Bits.ID14 +#define CANRXIDR2_ID_7 _CANRXIDR2.MergedBits.grpID_7 +#define CANRXIDR2_ID CANRXIDR2_ID_7 + + +/*** CANRXIDR3 - MSCAN Receive Identifier Register 3; 0x00000163 ***/ +typedef union { + byte Byte; + struct { + byte RTR :1; /* Remote Transmission Request */ + byte ID0 :1; /* Extended format identifier Bit 0 */ + byte ID1 :1; /* Extended format identifier Bit 1 */ + byte ID2 :1; /* Extended format identifier Bit 2 */ + byte ID3 :1; /* Extended format identifier Bit 3 */ + byte ID4 :1; /* Extended format identifier Bit 4 */ + byte ID5 :1; /* Extended format identifier Bit 5 */ + byte ID6 :1; /* Extended format identifier Bit 6 */ + } Bits; + struct { + byte :1; + byte grpID :7; + } MergedBits; +} CANRXIDR3STR; +extern volatile CANRXIDR3STR _CANRXIDR3 @(REG_BASE + 0x00000163); +#define CANRXIDR3 _CANRXIDR3.Byte +#define CANRXIDR3_RTR _CANRXIDR3.Bits.RTR +#define CANRXIDR3_ID0 _CANRXIDR3.Bits.ID0 +#define CANRXIDR3_ID1 _CANRXIDR3.Bits.ID1 +#define CANRXIDR3_ID2 _CANRXIDR3.Bits.ID2 +#define CANRXIDR3_ID3 _CANRXIDR3.Bits.ID3 +#define CANRXIDR3_ID4 _CANRXIDR3.Bits.ID4 +#define CANRXIDR3_ID5 _CANRXIDR3.Bits.ID5 +#define CANRXIDR3_ID6 _CANRXIDR3.Bits.ID6 +#define CANRXIDR3_ID _CANRXIDR3.MergedBits.grpID + + +/*** CANRXDSR0 - MSCAN Receive Data Segment Register 0; 0x00000164 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CANRXDSR0STR; +extern volatile CANRXDSR0STR _CANRXDSR0 @(REG_BASE + 0x00000164); +#define CANRXDSR0 _CANRXDSR0.Byte +#define CANRXDSR0_DB0 _CANRXDSR0.Bits.DB0 +#define CANRXDSR0_DB1 _CANRXDSR0.Bits.DB1 +#define CANRXDSR0_DB2 _CANRXDSR0.Bits.DB2 +#define CANRXDSR0_DB3 _CANRXDSR0.Bits.DB3 +#define CANRXDSR0_DB4 _CANRXDSR0.Bits.DB4 +#define CANRXDSR0_DB5 _CANRXDSR0.Bits.DB5 +#define CANRXDSR0_DB6 _CANRXDSR0.Bits.DB6 +#define CANRXDSR0_DB7 _CANRXDSR0.Bits.DB7 +#define CANRXDSR0_DB _CANRXDSR0.MergedBits.grpDB + + +/*** CANRXDSR1 - MSCAN Receive Data Segment Register 1; 0x00000165 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CANRXDSR1STR; +extern volatile CANRXDSR1STR _CANRXDSR1 @(REG_BASE + 0x00000165); +#define CANRXDSR1 _CANRXDSR1.Byte +#define CANRXDSR1_DB0 _CANRXDSR1.Bits.DB0 +#define CANRXDSR1_DB1 _CANRXDSR1.Bits.DB1 +#define CANRXDSR1_DB2 _CANRXDSR1.Bits.DB2 +#define CANRXDSR1_DB3 _CANRXDSR1.Bits.DB3 +#define CANRXDSR1_DB4 _CANRXDSR1.Bits.DB4 +#define CANRXDSR1_DB5 _CANRXDSR1.Bits.DB5 +#define CANRXDSR1_DB6 _CANRXDSR1.Bits.DB6 +#define CANRXDSR1_DB7 _CANRXDSR1.Bits.DB7 +#define CANRXDSR1_DB _CANRXDSR1.MergedBits.grpDB + + +/*** CANRXDSR2 - MSCAN Receive Data Segment Register 2; 0x00000166 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CANRXDSR2STR; +extern volatile CANRXDSR2STR _CANRXDSR2 @(REG_BASE + 0x00000166); +#define CANRXDSR2 _CANRXDSR2.Byte +#define CANRXDSR2_DB0 _CANRXDSR2.Bits.DB0 +#define CANRXDSR2_DB1 _CANRXDSR2.Bits.DB1 +#define CANRXDSR2_DB2 _CANRXDSR2.Bits.DB2 +#define CANRXDSR2_DB3 _CANRXDSR2.Bits.DB3 +#define CANRXDSR2_DB4 _CANRXDSR2.Bits.DB4 +#define CANRXDSR2_DB5 _CANRXDSR2.Bits.DB5 +#define CANRXDSR2_DB6 _CANRXDSR2.Bits.DB6 +#define CANRXDSR2_DB7 _CANRXDSR2.Bits.DB7 +#define CANRXDSR2_DB _CANRXDSR2.MergedBits.grpDB + + +/*** CANRXDSR3 - MSCAN Receive Data Segment Register 3; 0x00000167 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CANRXDSR3STR; +extern volatile CANRXDSR3STR _CANRXDSR3 @(REG_BASE + 0x00000167); +#define CANRXDSR3 _CANRXDSR3.Byte +#define CANRXDSR3_DB0 _CANRXDSR3.Bits.DB0 +#define CANRXDSR3_DB1 _CANRXDSR3.Bits.DB1 +#define CANRXDSR3_DB2 _CANRXDSR3.Bits.DB2 +#define CANRXDSR3_DB3 _CANRXDSR3.Bits.DB3 +#define CANRXDSR3_DB4 _CANRXDSR3.Bits.DB4 +#define CANRXDSR3_DB5 _CANRXDSR3.Bits.DB5 +#define CANRXDSR3_DB6 _CANRXDSR3.Bits.DB6 +#define CANRXDSR3_DB7 _CANRXDSR3.Bits.DB7 +#define CANRXDSR3_DB _CANRXDSR3.MergedBits.grpDB + + +/*** CANRXDSR4 - MSCAN Receive Data Segment Register 4; 0x00000168 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CANRXDSR4STR; +extern volatile CANRXDSR4STR _CANRXDSR4 @(REG_BASE + 0x00000168); +#define CANRXDSR4 _CANRXDSR4.Byte +#define CANRXDSR4_DB0 _CANRXDSR4.Bits.DB0 +#define CANRXDSR4_DB1 _CANRXDSR4.Bits.DB1 +#define CANRXDSR4_DB2 _CANRXDSR4.Bits.DB2 +#define CANRXDSR4_DB3 _CANRXDSR4.Bits.DB3 +#define CANRXDSR4_DB4 _CANRXDSR4.Bits.DB4 +#define CANRXDSR4_DB5 _CANRXDSR4.Bits.DB5 +#define CANRXDSR4_DB6 _CANRXDSR4.Bits.DB6 +#define CANRXDSR4_DB7 _CANRXDSR4.Bits.DB7 +#define CANRXDSR4_DB _CANRXDSR4.MergedBits.grpDB + + +/*** CANRXDSR5 - MSCAN Receive Data Segment Register 5; 0x00000169 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CANRXDSR5STR; +extern volatile CANRXDSR5STR _CANRXDSR5 @(REG_BASE + 0x00000169); +#define CANRXDSR5 _CANRXDSR5.Byte +#define CANRXDSR5_DB0 _CANRXDSR5.Bits.DB0 +#define CANRXDSR5_DB1 _CANRXDSR5.Bits.DB1 +#define CANRXDSR5_DB2 _CANRXDSR5.Bits.DB2 +#define CANRXDSR5_DB3 _CANRXDSR5.Bits.DB3 +#define CANRXDSR5_DB4 _CANRXDSR5.Bits.DB4 +#define CANRXDSR5_DB5 _CANRXDSR5.Bits.DB5 +#define CANRXDSR5_DB6 _CANRXDSR5.Bits.DB6 +#define CANRXDSR5_DB7 _CANRXDSR5.Bits.DB7 +#define CANRXDSR5_DB _CANRXDSR5.MergedBits.grpDB + + +/*** CANRXDSR6 - MSCAN Receive Data Segment Register 6; 0x0000016A ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CANRXDSR6STR; +extern volatile CANRXDSR6STR _CANRXDSR6 @(REG_BASE + 0x0000016A); +#define CANRXDSR6 _CANRXDSR6.Byte +#define CANRXDSR6_DB0 _CANRXDSR6.Bits.DB0 +#define CANRXDSR6_DB1 _CANRXDSR6.Bits.DB1 +#define CANRXDSR6_DB2 _CANRXDSR6.Bits.DB2 +#define CANRXDSR6_DB3 _CANRXDSR6.Bits.DB3 +#define CANRXDSR6_DB4 _CANRXDSR6.Bits.DB4 +#define CANRXDSR6_DB5 _CANRXDSR6.Bits.DB5 +#define CANRXDSR6_DB6 _CANRXDSR6.Bits.DB6 +#define CANRXDSR6_DB7 _CANRXDSR6.Bits.DB7 +#define CANRXDSR6_DB _CANRXDSR6.MergedBits.grpDB + + +/*** CANRXDSR7 - MSCAN Receive Data Segment Register 7; 0x0000016B ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CANRXDSR7STR; +extern volatile CANRXDSR7STR _CANRXDSR7 @(REG_BASE + 0x0000016B); +#define CANRXDSR7 _CANRXDSR7.Byte +#define CANRXDSR7_DB0 _CANRXDSR7.Bits.DB0 +#define CANRXDSR7_DB1 _CANRXDSR7.Bits.DB1 +#define CANRXDSR7_DB2 _CANRXDSR7.Bits.DB2 +#define CANRXDSR7_DB3 _CANRXDSR7.Bits.DB3 +#define CANRXDSR7_DB4 _CANRXDSR7.Bits.DB4 +#define CANRXDSR7_DB5 _CANRXDSR7.Bits.DB5 +#define CANRXDSR7_DB6 _CANRXDSR7.Bits.DB6 +#define CANRXDSR7_DB7 _CANRXDSR7.Bits.DB7 +#define CANRXDSR7_DB _CANRXDSR7.MergedBits.grpDB + + +/*** CANRXDLR - MSCAN Receive Data Length Register; 0x0000016C ***/ +typedef union { + byte Byte; + struct { + byte DLC0 :1; /* Data Length Code Bit 0 */ + byte DLC1 :1; /* Data Length Code Bit 1 */ + byte DLC2 :1; /* Data Length Code Bit 2 */ + byte DLC3 :1; /* Data Length Code Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpDLC :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CANRXDLRSTR; +extern volatile CANRXDLRSTR _CANRXDLR @(REG_BASE + 0x0000016C); +#define CANRXDLR _CANRXDLR.Byte +#define CANRXDLR_DLC0 _CANRXDLR.Bits.DLC0 +#define CANRXDLR_DLC1 _CANRXDLR.Bits.DLC1 +#define CANRXDLR_DLC2 _CANRXDLR.Bits.DLC2 +#define CANRXDLR_DLC3 _CANRXDLR.Bits.DLC3 +#define CANRXDLR_DLC _CANRXDLR.MergedBits.grpDLC + + +/*** CANTXIDR0 - MSCAN Transmit Identifier Register 0; 0x00000170 ***/ +typedef union { + byte Byte; + struct { + byte ID21 :1; /* Extended format identifier Bit 21 */ + byte ID22 :1; /* Extended format identifier Bit 22 */ + byte ID23 :1; /* Extended format identifier Bit 23 */ + byte ID24 :1; /* Extended format identifier Bit 24 */ + byte ID25 :1; /* Extended format identifier Bit 25 */ + byte ID26 :1; /* Extended format identifier Bit 26 */ + byte ID27 :1; /* Extended format identifier Bit 27 */ + byte ID28 :1; /* Extended format identifier Bit 28 */ + } Bits; + struct { + byte grpID_21 :8; + } MergedBits; +} CANTXIDR0STR; +extern volatile CANTXIDR0STR _CANTXIDR0 @(REG_BASE + 0x00000170); +#define CANTXIDR0 _CANTXIDR0.Byte +#define CANTXIDR0_ID21 _CANTXIDR0.Bits.ID21 +#define CANTXIDR0_ID22 _CANTXIDR0.Bits.ID22 +#define CANTXIDR0_ID23 _CANTXIDR0.Bits.ID23 +#define CANTXIDR0_ID24 _CANTXIDR0.Bits.ID24 +#define CANTXIDR0_ID25 _CANTXIDR0.Bits.ID25 +#define CANTXIDR0_ID26 _CANTXIDR0.Bits.ID26 +#define CANTXIDR0_ID27 _CANTXIDR0.Bits.ID27 +#define CANTXIDR0_ID28 _CANTXIDR0.Bits.ID28 +#define CANTXIDR0_ID_21 _CANTXIDR0.MergedBits.grpID_21 +#define CANTXIDR0_ID CANTXIDR0_ID_21 + + +/*** CANTXIDR1 - MSCAN Transmit Identifier Register 1; 0x00000171 ***/ +typedef union { + byte Byte; + struct { + byte ID15 :1; /* Extended format identifier Bit 15 */ + byte ID16 :1; /* Extended format identifier Bit 16 */ + byte ID17 :1; /* Extended format identifier Bit 17 */ + byte IDE :1; /* ID Extended */ + byte SRR :1; /* Substitute Remote Request */ + byte ID18 :1; /* Extended format identifier Bit 18 */ + byte ID19 :1; /* Extended format identifier Bit 19 */ + byte ID20 :1; /* Extended format identifier Bit 20 */ + } Bits; + struct { + byte grpID_15 :3; + byte :1; + byte :1; + byte grpID_18 :3; + } MergedBits; +} CANTXIDR1STR; +extern volatile CANTXIDR1STR _CANTXIDR1 @(REG_BASE + 0x00000171); +#define CANTXIDR1 _CANTXIDR1.Byte +#define CANTXIDR1_ID15 _CANTXIDR1.Bits.ID15 +#define CANTXIDR1_ID16 _CANTXIDR1.Bits.ID16 +#define CANTXIDR1_ID17 _CANTXIDR1.Bits.ID17 +#define CANTXIDR1_IDE _CANTXIDR1.Bits.IDE +#define CANTXIDR1_SRR _CANTXIDR1.Bits.SRR +#define CANTXIDR1_ID18 _CANTXIDR1.Bits.ID18 +#define CANTXIDR1_ID19 _CANTXIDR1.Bits.ID19 +#define CANTXIDR1_ID20 _CANTXIDR1.Bits.ID20 +#define CANTXIDR1_ID_15 _CANTXIDR1.MergedBits.grpID_15 +#define CANTXIDR1_ID_18 _CANTXIDR1.MergedBits.grpID_18 +#define CANTXIDR1_ID CANTXIDR1_ID_15 + + +/*** CANTXIDR2 - MSCAN Transmit Identifier Register 2; 0x00000172 ***/ +typedef union { + byte Byte; + struct { + byte ID7 :1; /* Extended format identifier Bit 7 */ + byte ID8 :1; /* Extended format identifier Bit 8 */ + byte ID9 :1; /* Extended format identifier Bit 9 */ + byte ID10 :1; /* Extended format identifier Bit 10 */ + byte ID11 :1; /* Extended format identifier Bit 11 */ + byte ID12 :1; /* Extended format identifier Bit 12 */ + byte ID13 :1; /* Extended format identifier Bit 13 */ + byte ID14 :1; /* Extended format identifier Bit 14 */ + } Bits; + struct { + byte grpID_7 :8; + } MergedBits; +} CANTXIDR2STR; +extern volatile CANTXIDR2STR _CANTXIDR2 @(REG_BASE + 0x00000172); +#define CANTXIDR2 _CANTXIDR2.Byte +#define CANTXIDR2_ID7 _CANTXIDR2.Bits.ID7 +#define CANTXIDR2_ID8 _CANTXIDR2.Bits.ID8 +#define CANTXIDR2_ID9 _CANTXIDR2.Bits.ID9 +#define CANTXIDR2_ID10 _CANTXIDR2.Bits.ID10 +#define CANTXIDR2_ID11 _CANTXIDR2.Bits.ID11 +#define CANTXIDR2_ID12 _CANTXIDR2.Bits.ID12 +#define CANTXIDR2_ID13 _CANTXIDR2.Bits.ID13 +#define CANTXIDR2_ID14 _CANTXIDR2.Bits.ID14 +#define CANTXIDR2_ID_7 _CANTXIDR2.MergedBits.grpID_7 +#define CANTXIDR2_ID CANTXIDR2_ID_7 + + +/*** CANTXIDR3 - MSCAN Transmit Identifier Register 3; 0x00000173 ***/ +typedef union { + byte Byte; + struct { + byte RTR :1; /* Remote Transmission Request */ + byte ID0 :1; /* Extended format identifier Bit 0 */ + byte ID1 :1; /* Extended format identifier Bit 1 */ + byte ID2 :1; /* Extended format identifier Bit 2 */ + byte ID3 :1; /* Extended format identifier Bit 3 */ + byte ID4 :1; /* Extended format identifier Bit 4 */ + byte ID5 :1; /* Extended format identifier Bit 5 */ + byte ID6 :1; /* Extended format identifier Bit 6 */ + } Bits; + struct { + byte :1; + byte grpID :7; + } MergedBits; +} CANTXIDR3STR; +extern volatile CANTXIDR3STR _CANTXIDR3 @(REG_BASE + 0x00000173); +#define CANTXIDR3 _CANTXIDR3.Byte +#define CANTXIDR3_RTR _CANTXIDR3.Bits.RTR +#define CANTXIDR3_ID0 _CANTXIDR3.Bits.ID0 +#define CANTXIDR3_ID1 _CANTXIDR3.Bits.ID1 +#define CANTXIDR3_ID2 _CANTXIDR3.Bits.ID2 +#define CANTXIDR3_ID3 _CANTXIDR3.Bits.ID3 +#define CANTXIDR3_ID4 _CANTXIDR3.Bits.ID4 +#define CANTXIDR3_ID5 _CANTXIDR3.Bits.ID5 +#define CANTXIDR3_ID6 _CANTXIDR3.Bits.ID6 +#define CANTXIDR3_ID _CANTXIDR3.MergedBits.grpID + + +/*** CANTXDSR0 - MSCAN Transmit Data Segment Register 0; 0x00000174 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CANTXDSR0STR; +extern volatile CANTXDSR0STR _CANTXDSR0 @(REG_BASE + 0x00000174); +#define CANTXDSR0 _CANTXDSR0.Byte +#define CANTXDSR0_DB0 _CANTXDSR0.Bits.DB0 +#define CANTXDSR0_DB1 _CANTXDSR0.Bits.DB1 +#define CANTXDSR0_DB2 _CANTXDSR0.Bits.DB2 +#define CANTXDSR0_DB3 _CANTXDSR0.Bits.DB3 +#define CANTXDSR0_DB4 _CANTXDSR0.Bits.DB4 +#define CANTXDSR0_DB5 _CANTXDSR0.Bits.DB5 +#define CANTXDSR0_DB6 _CANTXDSR0.Bits.DB6 +#define CANTXDSR0_DB7 _CANTXDSR0.Bits.DB7 +#define CANTXDSR0_DB _CANTXDSR0.MergedBits.grpDB + + +/*** CANTXDSR1 - MSCAN Transmit Data Segment Register 1; 0x00000175 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CANTXDSR1STR; +extern volatile CANTXDSR1STR _CANTXDSR1 @(REG_BASE + 0x00000175); +#define CANTXDSR1 _CANTXDSR1.Byte +#define CANTXDSR1_DB0 _CANTXDSR1.Bits.DB0 +#define CANTXDSR1_DB1 _CANTXDSR1.Bits.DB1 +#define CANTXDSR1_DB2 _CANTXDSR1.Bits.DB2 +#define CANTXDSR1_DB3 _CANTXDSR1.Bits.DB3 +#define CANTXDSR1_DB4 _CANTXDSR1.Bits.DB4 +#define CANTXDSR1_DB5 _CANTXDSR1.Bits.DB5 +#define CANTXDSR1_DB6 _CANTXDSR1.Bits.DB6 +#define CANTXDSR1_DB7 _CANTXDSR1.Bits.DB7 +#define CANTXDSR1_DB _CANTXDSR1.MergedBits.grpDB + + +/*** CANTXDSR2 - MSCAN Transmit Data Segment Register 2; 0x00000176 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CANTXDSR2STR; +extern volatile CANTXDSR2STR _CANTXDSR2 @(REG_BASE + 0x00000176); +#define CANTXDSR2 _CANTXDSR2.Byte +#define CANTXDSR2_DB0 _CANTXDSR2.Bits.DB0 +#define CANTXDSR2_DB1 _CANTXDSR2.Bits.DB1 +#define CANTXDSR2_DB2 _CANTXDSR2.Bits.DB2 +#define CANTXDSR2_DB3 _CANTXDSR2.Bits.DB3 +#define CANTXDSR2_DB4 _CANTXDSR2.Bits.DB4 +#define CANTXDSR2_DB5 _CANTXDSR2.Bits.DB5 +#define CANTXDSR2_DB6 _CANTXDSR2.Bits.DB6 +#define CANTXDSR2_DB7 _CANTXDSR2.Bits.DB7 +#define CANTXDSR2_DB _CANTXDSR2.MergedBits.grpDB + + +/*** CANTXDSR3 - MSCAN Transmit Data Segment Register 3; 0x00000177 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CANTXDSR3STR; +extern volatile CANTXDSR3STR _CANTXDSR3 @(REG_BASE + 0x00000177); +#define CANTXDSR3 _CANTXDSR3.Byte +#define CANTXDSR3_DB0 _CANTXDSR3.Bits.DB0 +#define CANTXDSR3_DB1 _CANTXDSR3.Bits.DB1 +#define CANTXDSR3_DB2 _CANTXDSR3.Bits.DB2 +#define CANTXDSR3_DB3 _CANTXDSR3.Bits.DB3 +#define CANTXDSR3_DB4 _CANTXDSR3.Bits.DB4 +#define CANTXDSR3_DB5 _CANTXDSR3.Bits.DB5 +#define CANTXDSR3_DB6 _CANTXDSR3.Bits.DB6 +#define CANTXDSR3_DB7 _CANTXDSR3.Bits.DB7 +#define CANTXDSR3_DB _CANTXDSR3.MergedBits.grpDB + + +/*** CANTXDSR4 - MSCAN Transmit Data Segment Register 4; 0x00000178 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CANTXDSR4STR; +extern volatile CANTXDSR4STR _CANTXDSR4 @(REG_BASE + 0x00000178); +#define CANTXDSR4 _CANTXDSR4.Byte +#define CANTXDSR4_DB0 _CANTXDSR4.Bits.DB0 +#define CANTXDSR4_DB1 _CANTXDSR4.Bits.DB1 +#define CANTXDSR4_DB2 _CANTXDSR4.Bits.DB2 +#define CANTXDSR4_DB3 _CANTXDSR4.Bits.DB3 +#define CANTXDSR4_DB4 _CANTXDSR4.Bits.DB4 +#define CANTXDSR4_DB5 _CANTXDSR4.Bits.DB5 +#define CANTXDSR4_DB6 _CANTXDSR4.Bits.DB6 +#define CANTXDSR4_DB7 _CANTXDSR4.Bits.DB7 +#define CANTXDSR4_DB _CANTXDSR4.MergedBits.grpDB + + +/*** CANTXDSR5 - MSCAN Transmit Data Segment Register 5; 0x00000179 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CANTXDSR5STR; +extern volatile CANTXDSR5STR _CANTXDSR5 @(REG_BASE + 0x00000179); +#define CANTXDSR5 _CANTXDSR5.Byte +#define CANTXDSR5_DB0 _CANTXDSR5.Bits.DB0 +#define CANTXDSR5_DB1 _CANTXDSR5.Bits.DB1 +#define CANTXDSR5_DB2 _CANTXDSR5.Bits.DB2 +#define CANTXDSR5_DB3 _CANTXDSR5.Bits.DB3 +#define CANTXDSR5_DB4 _CANTXDSR5.Bits.DB4 +#define CANTXDSR5_DB5 _CANTXDSR5.Bits.DB5 +#define CANTXDSR5_DB6 _CANTXDSR5.Bits.DB6 +#define CANTXDSR5_DB7 _CANTXDSR5.Bits.DB7 +#define CANTXDSR5_DB _CANTXDSR5.MergedBits.grpDB + + +/*** CANTXDSR6 - MSCAN Transmit Data Segment Register 6; 0x0000017A ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CANTXDSR6STR; +extern volatile CANTXDSR6STR _CANTXDSR6 @(REG_BASE + 0x0000017A); +#define CANTXDSR6 _CANTXDSR6.Byte +#define CANTXDSR6_DB0 _CANTXDSR6.Bits.DB0 +#define CANTXDSR6_DB1 _CANTXDSR6.Bits.DB1 +#define CANTXDSR6_DB2 _CANTXDSR6.Bits.DB2 +#define CANTXDSR6_DB3 _CANTXDSR6.Bits.DB3 +#define CANTXDSR6_DB4 _CANTXDSR6.Bits.DB4 +#define CANTXDSR6_DB5 _CANTXDSR6.Bits.DB5 +#define CANTXDSR6_DB6 _CANTXDSR6.Bits.DB6 +#define CANTXDSR6_DB7 _CANTXDSR6.Bits.DB7 +#define CANTXDSR6_DB _CANTXDSR6.MergedBits.grpDB + + +/*** CANTXDSR7 - MSCAN Transmit Data Segment Register 7; 0x0000017B ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; + struct { + byte grpDB :8; + } MergedBits; +} CANTXDSR7STR; +extern volatile CANTXDSR7STR _CANTXDSR7 @(REG_BASE + 0x0000017B); +#define CANTXDSR7 _CANTXDSR7.Byte +#define CANTXDSR7_DB0 _CANTXDSR7.Bits.DB0 +#define CANTXDSR7_DB1 _CANTXDSR7.Bits.DB1 +#define CANTXDSR7_DB2 _CANTXDSR7.Bits.DB2 +#define CANTXDSR7_DB3 _CANTXDSR7.Bits.DB3 +#define CANTXDSR7_DB4 _CANTXDSR7.Bits.DB4 +#define CANTXDSR7_DB5 _CANTXDSR7.Bits.DB5 +#define CANTXDSR7_DB6 _CANTXDSR7.Bits.DB6 +#define CANTXDSR7_DB7 _CANTXDSR7.Bits.DB7 +#define CANTXDSR7_DB _CANTXDSR7.MergedBits.grpDB + + +/*** CANTXDLR - MSCAN Transmit Data Length Register; 0x0000017C ***/ +typedef union { + byte Byte; + struct { + byte DLC0 :1; /* Data Length Code Bit 0 */ + byte DLC1 :1; /* Data Length Code Bit 1 */ + byte DLC2 :1; /* Data Length Code Bit 2 */ + byte DLC3 :1; /* Data Length Code Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpDLC :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CANTXDLRSTR; +extern volatile CANTXDLRSTR _CANTXDLR @(REG_BASE + 0x0000017C); +#define CANTXDLR _CANTXDLR.Byte +#define CANTXDLR_DLC0 _CANTXDLR.Bits.DLC0 +#define CANTXDLR_DLC1 _CANTXDLR.Bits.DLC1 +#define CANTXDLR_DLC2 _CANTXDLR.Bits.DLC2 +#define CANTXDLR_DLC3 _CANTXDLR.Bits.DLC3 +#define CANTXDLR_DLC _CANTXDLR.MergedBits.grpDLC + + +/*** CANTXTBPR - MSCAN Transmit Buffer Priority; 0x0000017F ***/ +typedef union { + byte Byte; + struct { + byte PRIO0 :1; /* Transmit Buffer Priority Bit 0 */ + byte PRIO1 :1; /* Transmit Buffer Priority Bit 1 */ + byte PRIO2 :1; /* Transmit Buffer Priority Bit 2 */ + byte PRIO3 :1; /* Transmit Buffer Priority Bit 3 */ + byte PRIO4 :1; /* Transmit Buffer Priority Bit 4 */ + byte PRIO5 :1; /* Transmit Buffer Priority Bit 5 */ + byte PRIO6 :1; /* Transmit Buffer Priority Bit 6 */ + byte PRIO7 :1; /* Transmit Buffer Priority Bit 7 */ + } Bits; + struct { + byte grpPRIO :8; + } MergedBits; +} CANTXTBPRSTR; +extern volatile CANTXTBPRSTR _CANTXTBPR @(REG_BASE + 0x0000017F); +#define CANTXTBPR _CANTXTBPR.Byte +#define CANTXTBPR_PRIO0 _CANTXTBPR.Bits.PRIO0 +#define CANTXTBPR_PRIO1 _CANTXTBPR.Bits.PRIO1 +#define CANTXTBPR_PRIO2 _CANTXTBPR.Bits.PRIO2 +#define CANTXTBPR_PRIO3 _CANTXTBPR.Bits.PRIO3 +#define CANTXTBPR_PRIO4 _CANTXTBPR.Bits.PRIO4 +#define CANTXTBPR_PRIO5 _CANTXTBPR.Bits.PRIO5 +#define CANTXTBPR_PRIO6 _CANTXTBPR.Bits.PRIO6 +#define CANTXTBPR_PRIO7 _CANTXTBPR.Bits.PRIO7 +#define CANTXTBPR_PRIO _CANTXTBPR.MergedBits.grpPRIO + + +/*** PTT - Port T I/O Register; 0x00000240 ***/ +typedef union { + byte Byte; + struct { + byte PTT0 :1; /* Port T Bit 0 */ + byte PTT1 :1; /* Port T Bit 1 */ + byte PTT2 :1; /* Port T Bit 2 */ + byte PTT3 :1; /* Port T Bit 3 */ + byte PTT4 :1; /* Port T Bit 4 */ + byte PTT5 :1; /* Port T Bit 5 */ + byte PTT6 :1; /* Port T Bit 6 */ + byte PTT7 :1; /* Port T Bit 7 */ + } Bits; + struct { + byte grpPTT :8; + } MergedBits; +} PTTSTR; +extern volatile PTTSTR _PTT @(REG_BASE + 0x00000240); +#define PTT _PTT.Byte +#define PTT_PTT0 _PTT.Bits.PTT0 +#define PTT_PTT1 _PTT.Bits.PTT1 +#define PTT_PTT2 _PTT.Bits.PTT2 +#define PTT_PTT3 _PTT.Bits.PTT3 +#define PTT_PTT4 _PTT.Bits.PTT4 +#define PTT_PTT5 _PTT.Bits.PTT5 +#define PTT_PTT6 _PTT.Bits.PTT6 +#define PTT_PTT7 _PTT.Bits.PTT7 +#define PTT_PTT _PTT.MergedBits.grpPTT + + +/*** PTIT - Port T Input; 0x00000241 ***/ +typedef union { + byte Byte; + struct { + byte PTIT0 :1; /* Port T Bit 0 */ + byte PTIT1 :1; /* Port T Bit 1 */ + byte PTIT2 :1; /* Port T Bit 2 */ + byte PTIT3 :1; /* Port T Bit 3 */ + byte PTIT4 :1; /* Port T Bit 4 */ + byte PTIT5 :1; /* Port T Bit 5 */ + byte PTIT6 :1; /* Port T Bit 6 */ + byte PTIT7 :1; /* Port T Bit 7 */ + } Bits; + struct { + byte grpPTIT :8; + } MergedBits; +} PTITSTR; +extern volatile PTITSTR _PTIT @(REG_BASE + 0x00000241); +#define PTIT _PTIT.Byte +#define PTIT_PTIT0 _PTIT.Bits.PTIT0 +#define PTIT_PTIT1 _PTIT.Bits.PTIT1 +#define PTIT_PTIT2 _PTIT.Bits.PTIT2 +#define PTIT_PTIT3 _PTIT.Bits.PTIT3 +#define PTIT_PTIT4 _PTIT.Bits.PTIT4 +#define PTIT_PTIT5 _PTIT.Bits.PTIT5 +#define PTIT_PTIT6 _PTIT.Bits.PTIT6 +#define PTIT_PTIT7 _PTIT.Bits.PTIT7 +#define PTIT_PTIT _PTIT.MergedBits.grpPTIT + + +/*** DDRT - Port T Data Direction Register; 0x00000242 ***/ +typedef union { + byte Byte; + struct { + byte DDRT0 :1; /* Data Direction Port T Bit 0 */ + byte DDRT1 :1; /* Data Direction Port T Bit 1 */ + byte DDRT2 :1; /* Data Direction Port T Bit 2 */ + byte DDRT3 :1; /* Data Direction Port T Bit 3 */ + byte DDRT4 :1; /* Data Direction Port T Bit 4 */ + byte DDRT5 :1; /* Data Direction Port T Bit 5 */ + byte DDRT6 :1; /* Data Direction Port T Bit 6 */ + byte DDRT7 :1; /* Data Direction Port T Bit 7 */ + } Bits; + struct { + byte grpDDRT :8; + } MergedBits; +} DDRTSTR; +extern volatile DDRTSTR _DDRT @(REG_BASE + 0x00000242); +#define DDRT _DDRT.Byte +#define DDRT_DDRT0 _DDRT.Bits.DDRT0 +#define DDRT_DDRT1 _DDRT.Bits.DDRT1 +#define DDRT_DDRT2 _DDRT.Bits.DDRT2 +#define DDRT_DDRT3 _DDRT.Bits.DDRT3 +#define DDRT_DDRT4 _DDRT.Bits.DDRT4 +#define DDRT_DDRT5 _DDRT.Bits.DDRT5 +#define DDRT_DDRT6 _DDRT.Bits.DDRT6 +#define DDRT_DDRT7 _DDRT.Bits.DDRT7 +#define DDRT_DDRT _DDRT.MergedBits.grpDDRT + + +/*** RDRT - Port T Reduced Drive Register; 0x00000243 ***/ +typedef union { + byte Byte; + struct { + byte RDRT0 :1; /* Reduced Drive Port T Bit 0 */ + byte RDRT1 :1; /* Reduced Drive Port T Bit 1 */ + byte RDRT2 :1; /* Reduced Drive Port T Bit 2 */ + byte RDRT3 :1; /* Reduced Drive Port T Bit 3 */ + byte RDRT4 :1; /* Reduced Drive Port T Bit 4 */ + byte RDRT5 :1; /* Reduced Drive Port T Bit 5 */ + byte RDRT6 :1; /* Reduced Drive Port T Bit 6 */ + byte RDRT7 :1; /* Reduced Drive Port T Bit 7 */ + } Bits; + struct { + byte grpRDRT :8; + } MergedBits; +} RDRTSTR; +extern volatile RDRTSTR _RDRT @(REG_BASE + 0x00000243); +#define RDRT _RDRT.Byte +#define RDRT_RDRT0 _RDRT.Bits.RDRT0 +#define RDRT_RDRT1 _RDRT.Bits.RDRT1 +#define RDRT_RDRT2 _RDRT.Bits.RDRT2 +#define RDRT_RDRT3 _RDRT.Bits.RDRT3 +#define RDRT_RDRT4 _RDRT.Bits.RDRT4 +#define RDRT_RDRT5 _RDRT.Bits.RDRT5 +#define RDRT_RDRT6 _RDRT.Bits.RDRT6 +#define RDRT_RDRT7 _RDRT.Bits.RDRT7 +#define RDRT_RDRT _RDRT.MergedBits.grpRDRT + + +/*** PERT - Port T Pull Device Enable Register; 0x00000244 ***/ +typedef union { + byte Byte; + struct { + byte PERT0 :1; /* Pull Device Enable Port T Bit 0 */ + byte PERT1 :1; /* Pull Device Enable Port T Bit 1 */ + byte PERT2 :1; /* Pull Device Enable Port T Bit 2 */ + byte PERT3 :1; /* Pull Device Enable Port T Bit 3 */ + byte PERT4 :1; /* Pull Device Enable Port T Bit 4 */ + byte PERT5 :1; /* Pull Device Enable Port T Bit 5 */ + byte PERT6 :1; /* Pull Device Enable Port T Bit 6 */ + byte PERT7 :1; /* Pull Device Enable Port T Bit 7 */ + } Bits; + struct { + byte grpPERT :8; + } MergedBits; +} PERTSTR; +extern volatile PERTSTR _PERT @(REG_BASE + 0x00000244); +#define PERT _PERT.Byte +#define PERT_PERT0 _PERT.Bits.PERT0 +#define PERT_PERT1 _PERT.Bits.PERT1 +#define PERT_PERT2 _PERT.Bits.PERT2 +#define PERT_PERT3 _PERT.Bits.PERT3 +#define PERT_PERT4 _PERT.Bits.PERT4 +#define PERT_PERT5 _PERT.Bits.PERT5 +#define PERT_PERT6 _PERT.Bits.PERT6 +#define PERT_PERT7 _PERT.Bits.PERT7 +#define PERT_PERT _PERT.MergedBits.grpPERT + + +/*** PPST - Port T Polarity Select Register; 0x00000245 ***/ +typedef union { + byte Byte; + struct { + byte PPST0 :1; /* Pull Select Port T Bit 0 */ + byte PPST1 :1; /* Pull Select Port T Bit 1 */ + byte PPST2 :1; /* Pull Select Port T Bit 2 */ + byte PPST3 :1; /* Pull Select Port T Bit 3 */ + byte PPST4 :1; /* Pull Select Port T Bit 4 */ + byte PPST5 :1; /* Pull Select Port T Bit 5 */ + byte PPST6 :1; /* Pull Select Port T Bit 6 */ + byte PPST7 :1; /* Pull Select Port T Bit 7 */ + } Bits; + struct { + byte grpPPST :8; + } MergedBits; +} PPSTSTR; +extern volatile PPSTSTR _PPST @(REG_BASE + 0x00000245); +#define PPST _PPST.Byte +#define PPST_PPST0 _PPST.Bits.PPST0 +#define PPST_PPST1 _PPST.Bits.PPST1 +#define PPST_PPST2 _PPST.Bits.PPST2 +#define PPST_PPST3 _PPST.Bits.PPST3 +#define PPST_PPST4 _PPST.Bits.PPST4 +#define PPST_PPST5 _PPST.Bits.PPST5 +#define PPST_PPST6 _PPST.Bits.PPST6 +#define PPST_PPST7 _PPST.Bits.PPST7 +#define PPST_PPST _PPST.MergedBits.grpPPST + + +/*** MODRR - Module Routing Register; 0x00000247 ***/ +typedef union { + byte Byte; + struct { + byte MODRR0 :1; /* Module Routing Bit 0 */ + byte MODRR1 :1; /* Module Routing Bit 1 */ + byte MODRR2 :1; /* Module Routing Bit 2 */ + byte MODRR3 :1; /* Module Routing Bit 3 */ + byte MODRR4 :1; /* Module Routing Bit 4 */ + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpMODRR :5; + byte :1; + byte :1; + byte :1; + } MergedBits; +} MODRRSTR; +extern volatile MODRRSTR _MODRR @(REG_BASE + 0x00000247); +#define MODRR _MODRR.Byte +#define MODRR_MODRR0 _MODRR.Bits.MODRR0 +#define MODRR_MODRR1 _MODRR.Bits.MODRR1 +#define MODRR_MODRR2 _MODRR.Bits.MODRR2 +#define MODRR_MODRR3 _MODRR.Bits.MODRR3 +#define MODRR_MODRR4 _MODRR.Bits.MODRR4 +#define MODRR_MODRR _MODRR.MergedBits.grpMODRR + + +/*** PTS - Port S I/O Register; 0x00000248 ***/ +typedef union { + byte Byte; + struct { + byte PTS0 :1; /* Port S Bit 0 */ + byte PTS1 :1; /* Port S Bit 1 */ + byte PTS2 :1; /* Port S Bit 2 */ + byte PTS3 :1; /* Port S Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpPTS :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} PTSSTR; +extern volatile PTSSTR _PTS @(REG_BASE + 0x00000248); +#define PTS _PTS.Byte +#define PTS_PTS0 _PTS.Bits.PTS0 +#define PTS_PTS1 _PTS.Bits.PTS1 +#define PTS_PTS2 _PTS.Bits.PTS2 +#define PTS_PTS3 _PTS.Bits.PTS3 +#define PTS_PTS _PTS.MergedBits.grpPTS + + +/*** PTIS - Port S Input; 0x00000249 ***/ +typedef union { + byte Byte; + struct { + byte PTIS0 :1; /* Port S Bit 0 */ + byte PTIS1 :1; /* Port S Bit 1 */ + byte PTIS2 :1; /* Port S Bit 2 */ + byte PTIS3 :1; /* Port S Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpPTIS :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} PTISSTR; +extern volatile PTISSTR _PTIS @(REG_BASE + 0x00000249); +#define PTIS _PTIS.Byte +#define PTIS_PTIS0 _PTIS.Bits.PTIS0 +#define PTIS_PTIS1 _PTIS.Bits.PTIS1 +#define PTIS_PTIS2 _PTIS.Bits.PTIS2 +#define PTIS_PTIS3 _PTIS.Bits.PTIS3 +#define PTIS_PTIS _PTIS.MergedBits.grpPTIS + + +/*** DDRS - Port S Data Direction Register; 0x0000024A ***/ +typedef union { + byte Byte; + struct { + byte DDRS0 :1; /* Data Direction Port S Bit 0 */ + byte DDRS1 :1; /* Data Direction Port S Bit 1 */ + byte DDRS2 :1; /* Data Direction Port S Bit 2 */ + byte DDRS3 :1; /* Data Direction Port S Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpDDRS :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} DDRSSTR; +extern volatile DDRSSTR _DDRS @(REG_BASE + 0x0000024A); +#define DDRS _DDRS.Byte +#define DDRS_DDRS0 _DDRS.Bits.DDRS0 +#define DDRS_DDRS1 _DDRS.Bits.DDRS1 +#define DDRS_DDRS2 _DDRS.Bits.DDRS2 +#define DDRS_DDRS3 _DDRS.Bits.DDRS3 +#define DDRS_DDRS _DDRS.MergedBits.grpDDRS + + +/*** RDRS - Port S Reduced Drive Register; 0x0000024B ***/ +typedef union { + byte Byte; + struct { + byte RDRS0 :1; /* Reduced Drive Port S Bit 0 */ + byte RDRS1 :1; /* Reduced Drive Port S Bit 1 */ + byte RDRS2 :1; /* Reduced Drive Port S Bit 2 */ + byte RDRS3 :1; /* Reduced Drive Port S Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpRDRS :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} RDRSSTR; +extern volatile RDRSSTR _RDRS @(REG_BASE + 0x0000024B); +#define RDRS _RDRS.Byte +#define RDRS_RDRS0 _RDRS.Bits.RDRS0 +#define RDRS_RDRS1 _RDRS.Bits.RDRS1 +#define RDRS_RDRS2 _RDRS.Bits.RDRS2 +#define RDRS_RDRS3 _RDRS.Bits.RDRS3 +#define RDRS_RDRS _RDRS.MergedBits.grpRDRS + + +/*** PERS - Port S Pull Device Enable Register; 0x0000024C ***/ +typedef union { + byte Byte; + struct { + byte PERS0 :1; /* Pull Device Enable Port S Bit 0 */ + byte PERS1 :1; /* Pull Device Enable Port S Bit 1 */ + byte PERS2 :1; /* Pull Device Enable Port S Bit 2 */ + byte PERS3 :1; /* Pull Device Enable Port S Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpPERS :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} PERSSTR; +extern volatile PERSSTR _PERS @(REG_BASE + 0x0000024C); +#define PERS _PERS.Byte +#define PERS_PERS0 _PERS.Bits.PERS0 +#define PERS_PERS1 _PERS.Bits.PERS1 +#define PERS_PERS2 _PERS.Bits.PERS2 +#define PERS_PERS3 _PERS.Bits.PERS3 +#define PERS_PERS _PERS.MergedBits.grpPERS + + +/*** PPSS - Port S Polarity Select Register; 0x0000024D ***/ +typedef union { + byte Byte; + struct { + byte PPSS0 :1; /* Pull Select Port S Bit 0 */ + byte PPSS1 :1; /* Pull Select Port S Bit 1 */ + byte PPSS2 :1; /* Pull Select Port S Bit 2 */ + byte PPSS3 :1; /* Pull Select Port S Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpPPSS :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} PPSSSTR; +extern volatile PPSSSTR _PPSS @(REG_BASE + 0x0000024D); +#define PPSS _PPSS.Byte +#define PPSS_PPSS0 _PPSS.Bits.PPSS0 +#define PPSS_PPSS1 _PPSS.Bits.PPSS1 +#define PPSS_PPSS2 _PPSS.Bits.PPSS2 +#define PPSS_PPSS3 _PPSS.Bits.PPSS3 +#define PPSS_PPSS _PPSS.MergedBits.grpPPSS + + +/*** WOMS - Port S Wired-Or Mode Register; 0x0000024E ***/ +typedef union { + byte Byte; + struct { + byte WOMS0 :1; /* Wired-Or Mode Port S Bit 0 */ + byte WOMS1 :1; /* Wired-Or Mode Port S Bit 1 */ + byte WOMS2 :1; /* Wired-Or Mode Port S Bit 2 */ + byte WOMS3 :1; /* Wired-Or Mode Port S Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpWOMS :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} WOMSSTR; +extern volatile WOMSSTR _WOMS @(REG_BASE + 0x0000024E); +#define WOMS _WOMS.Byte +#define WOMS_WOMS0 _WOMS.Bits.WOMS0 +#define WOMS_WOMS1 _WOMS.Bits.WOMS1 +#define WOMS_WOMS2 _WOMS.Bits.WOMS2 +#define WOMS_WOMS3 _WOMS.Bits.WOMS3 +#define WOMS_WOMS _WOMS.MergedBits.grpWOMS + + +/*** PTM - Port M I/O Register; 0x00000250 ***/ +typedef union { + byte Byte; + struct { + byte PTM0 :1; /* Port T Bit 0 */ + byte PTM1 :1; /* Port T Bit 1 */ + byte PTM2 :1; /* Port T Bit 2 */ + byte PTM3 :1; /* Port T Bit 3 */ + byte PTM4 :1; /* Port T Bit 4 */ + byte PTM5 :1; /* Port T Bit 5 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpPTM :6; + byte :1; + byte :1; + } MergedBits; +} PTMSTR; +extern volatile PTMSTR _PTM @(REG_BASE + 0x00000250); +#define PTM _PTM.Byte +#define PTM_PTM0 _PTM.Bits.PTM0 +#define PTM_PTM1 _PTM.Bits.PTM1 +#define PTM_PTM2 _PTM.Bits.PTM2 +#define PTM_PTM3 _PTM.Bits.PTM3 +#define PTM_PTM4 _PTM.Bits.PTM4 +#define PTM_PTM5 _PTM.Bits.PTM5 +#define PTM_PTM _PTM.MergedBits.grpPTM + + +/*** PTIM - Port M Input; 0x00000251 ***/ +typedef union { + byte Byte; + struct { + byte PTIM0 :1; /* Port M Bit 0 */ + byte PTIM1 :1; /* Port M Bit 1 */ + byte PTIM2 :1; /* Port M Bit 2 */ + byte PTIM3 :1; /* Port M Bit 3 */ + byte PTIM4 :1; /* Port M Bit 4 */ + byte PTIM5 :1; /* Port M Bit 5 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpPTIM :6; + byte :1; + byte :1; + } MergedBits; +} PTIMSTR; +extern volatile PTIMSTR _PTIM @(REG_BASE + 0x00000251); +#define PTIM _PTIM.Byte +#define PTIM_PTIM0 _PTIM.Bits.PTIM0 +#define PTIM_PTIM1 _PTIM.Bits.PTIM1 +#define PTIM_PTIM2 _PTIM.Bits.PTIM2 +#define PTIM_PTIM3 _PTIM.Bits.PTIM3 +#define PTIM_PTIM4 _PTIM.Bits.PTIM4 +#define PTIM_PTIM5 _PTIM.Bits.PTIM5 +#define PTIM_PTIM _PTIM.MergedBits.grpPTIM + + +/*** DDRM - Port M Data Direction Register; 0x00000252 ***/ +typedef union { + byte Byte; + struct { + byte DDRM0 :1; /* Data Direction Port M Bit 0 */ + byte DDRM1 :1; /* Data Direction Port M Bit 1 */ + byte DDRM2 :1; /* Data Direction Port M Bit 2 */ + byte DDRM3 :1; /* Data Direction Port M Bit 3 */ + byte DDRM4 :1; /* Data Direction Port M Bit 4 */ + byte DDRM5 :1; /* Data Direction Port M Bit 5 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpDDRM :6; + byte :1; + byte :1; + } MergedBits; +} DDRMSTR; +extern volatile DDRMSTR _DDRM @(REG_BASE + 0x00000252); +#define DDRM _DDRM.Byte +#define DDRM_DDRM0 _DDRM.Bits.DDRM0 +#define DDRM_DDRM1 _DDRM.Bits.DDRM1 +#define DDRM_DDRM2 _DDRM.Bits.DDRM2 +#define DDRM_DDRM3 _DDRM.Bits.DDRM3 +#define DDRM_DDRM4 _DDRM.Bits.DDRM4 +#define DDRM_DDRM5 _DDRM.Bits.DDRM5 +#define DDRM_DDRM _DDRM.MergedBits.grpDDRM + + +/*** RDRM - Port M Reduced Drive Register; 0x00000253 ***/ +typedef union { + byte Byte; + struct { + byte RDRM0 :1; /* Reduced Drive Port M Bit 0 */ + byte RDRM1 :1; /* Reduced Drive Port M Bit 1 */ + byte RDRM2 :1; /* Reduced Drive Port M Bit 2 */ + byte RDRM3 :1; /* Reduced Drive Port M Bit 3 */ + byte RDRM4 :1; /* Reduced Drive Port M Bit 4 */ + byte RDRM5 :1; /* Reduced Drive Port M Bit 5 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpRDRM :6; + byte :1; + byte :1; + } MergedBits; +} RDRMSTR; +extern volatile RDRMSTR _RDRM @(REG_BASE + 0x00000253); +#define RDRM _RDRM.Byte +#define RDRM_RDRM0 _RDRM.Bits.RDRM0 +#define RDRM_RDRM1 _RDRM.Bits.RDRM1 +#define RDRM_RDRM2 _RDRM.Bits.RDRM2 +#define RDRM_RDRM3 _RDRM.Bits.RDRM3 +#define RDRM_RDRM4 _RDRM.Bits.RDRM4 +#define RDRM_RDRM5 _RDRM.Bits.RDRM5 +#define RDRM_RDRM _RDRM.MergedBits.grpRDRM + + +/*** PERM - Port M Pull Device Enable Register; 0x00000254 ***/ +typedef union { + byte Byte; + struct { + byte PERM0 :1; /* Pull Device Enable Port M Bit 0 */ + byte PERM1 :1; /* Pull Device Enable Port M Bit 1 */ + byte PERM2 :1; /* Pull Device Enable Port M Bit 2 */ + byte PERM3 :1; /* Pull Device Enable Port M Bit 3 */ + byte PERM4 :1; /* Pull Device Enable Port M Bit 4 */ + byte PERM5 :1; /* Pull Device Enable Port M Bit 5 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpPERM :6; + byte :1; + byte :1; + } MergedBits; +} PERMSTR; +extern volatile PERMSTR _PERM @(REG_BASE + 0x00000254); +#define PERM _PERM.Byte +#define PERM_PERM0 _PERM.Bits.PERM0 +#define PERM_PERM1 _PERM.Bits.PERM1 +#define PERM_PERM2 _PERM.Bits.PERM2 +#define PERM_PERM3 _PERM.Bits.PERM3 +#define PERM_PERM4 _PERM.Bits.PERM4 +#define PERM_PERM5 _PERM.Bits.PERM5 +#define PERM_PERM _PERM.MergedBits.grpPERM + + +/*** PPSM - Port M Polarity Select Register; 0x00000255 ***/ +typedef union { + byte Byte; + struct { + byte PPSM0 :1; /* Pull Select Port M Bit 0 */ + byte PPSM1 :1; /* Pull Select Port M Bit 1 */ + byte PPSM2 :1; /* Pull Select Port M Bit 2 */ + byte PPSM3 :1; /* Pull Select Port M Bit 3 */ + byte PPSM4 :1; /* Pull Select Port M Bit 4 */ + byte PPSM5 :1; /* Pull Select Port M Bit 5 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpPPSM :6; + byte :1; + byte :1; + } MergedBits; +} PPSMSTR; +extern volatile PPSMSTR _PPSM @(REG_BASE + 0x00000255); +#define PPSM _PPSM.Byte +#define PPSM_PPSM0 _PPSM.Bits.PPSM0 +#define PPSM_PPSM1 _PPSM.Bits.PPSM1 +#define PPSM_PPSM2 _PPSM.Bits.PPSM2 +#define PPSM_PPSM3 _PPSM.Bits.PPSM3 +#define PPSM_PPSM4 _PPSM.Bits.PPSM4 +#define PPSM_PPSM5 _PPSM.Bits.PPSM5 +#define PPSM_PPSM _PPSM.MergedBits.grpPPSM + + +/*** WOMM - Port M Wired-Or Mode Register; 0x00000256 ***/ +typedef union { + byte Byte; + struct { + byte WOMM0 :1; /* Wired-Or Mode Port M Bit 0 */ + byte WOMM1 :1; /* Wired-Or Mode Port M Bit 1 */ + byte WOMM2 :1; /* Wired-Or Mode Port M Bit 2 */ + byte WOMM3 :1; /* Wired-Or Mode Port M Bit 3 */ + byte WOMM4 :1; /* Wired-Or Mode Port M Bit 4 */ + byte WOMM5 :1; /* Wired-Or Mode Port M Bit 5 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpWOMM :6; + byte :1; + byte :1; + } MergedBits; +} WOMMSTR; +extern volatile WOMMSTR _WOMM @(REG_BASE + 0x00000256); +#define WOMM _WOMM.Byte +#define WOMM_WOMM0 _WOMM.Bits.WOMM0 +#define WOMM_WOMM1 _WOMM.Bits.WOMM1 +#define WOMM_WOMM2 _WOMM.Bits.WOMM2 +#define WOMM_WOMM3 _WOMM.Bits.WOMM3 +#define WOMM_WOMM4 _WOMM.Bits.WOMM4 +#define WOMM_WOMM5 _WOMM.Bits.WOMM5 +#define WOMM_WOMM _WOMM.MergedBits.grpWOMM + + +/*** PTP - Port P I/O Register; 0x00000258 ***/ +typedef union { + byte Byte; + struct { + byte PTP0 :1; /* Port P Bit 0 */ + byte PTP1 :1; /* Port P Bit 1 */ + byte PTP2 :1; /* Port P Bit 2 */ + byte PTP3 :1; /* Port P Bit 3 */ + byte PTP4 :1; /* Port P Bit 4 */ + byte PTP5 :1; /* Port P Bit 5 */ + byte PTP6 :1; /* Port P Bit 6 */ + byte PTP7 :1; /* Port P Bit 7 */ + } Bits; + struct { + byte grpPTP :8; + } MergedBits; +} PTPSTR; +extern volatile PTPSTR _PTP @(REG_BASE + 0x00000258); +#define PTP _PTP.Byte +#define PTP_PTP0 _PTP.Bits.PTP0 +#define PTP_PTP1 _PTP.Bits.PTP1 +#define PTP_PTP2 _PTP.Bits.PTP2 +#define PTP_PTP3 _PTP.Bits.PTP3 +#define PTP_PTP4 _PTP.Bits.PTP4 +#define PTP_PTP5 _PTP.Bits.PTP5 +#define PTP_PTP6 _PTP.Bits.PTP6 +#define PTP_PTP7 _PTP.Bits.PTP7 +#define PTP_PTP _PTP.MergedBits.grpPTP + + +/*** PTIP - Port P Input; 0x00000259 ***/ +typedef union { + byte Byte; + struct { + byte PTIP0 :1; /* Port P Bit 0 */ + byte PTIP1 :1; /* Port P Bit 1 */ + byte PTIP2 :1; /* Port P Bit 2 */ + byte PTIP3 :1; /* Port P Bit 3 */ + byte PTIP4 :1; /* Port P Bit 4 */ + byte PTIP5 :1; /* Port P Bit 5 */ + byte PTIP6 :1; /* Port P Bit 6 */ + byte PTIP7 :1; /* Port P Bit 7 */ + } Bits; + struct { + byte grpPTIP :8; + } MergedBits; +} PTIPSTR; +extern volatile PTIPSTR _PTIP @(REG_BASE + 0x00000259); +#define PTIP _PTIP.Byte +#define PTIP_PTIP0 _PTIP.Bits.PTIP0 +#define PTIP_PTIP1 _PTIP.Bits.PTIP1 +#define PTIP_PTIP2 _PTIP.Bits.PTIP2 +#define PTIP_PTIP3 _PTIP.Bits.PTIP3 +#define PTIP_PTIP4 _PTIP.Bits.PTIP4 +#define PTIP_PTIP5 _PTIP.Bits.PTIP5 +#define PTIP_PTIP6 _PTIP.Bits.PTIP6 +#define PTIP_PTIP7 _PTIP.Bits.PTIP7 +#define PTIP_PTIP _PTIP.MergedBits.grpPTIP + + +/*** DDRP - Port P Data Direction Register; 0x0000025A ***/ +typedef union { + byte Byte; + struct { + byte DDRP0 :1; /* Data Direction Port P Bit 0 */ + byte DDRP1 :1; /* Data Direction Port P Bit 1 */ + byte DDRP2 :1; /* Data Direction Port P Bit 2 */ + byte DDRP3 :1; /* Data Direction Port P Bit 3 */ + byte DDRP4 :1; /* Data Direction Port P Bit 4 */ + byte DDRP5 :1; /* Data Direction Port P Bit 5 */ + byte DDRP6 :1; /* Data Direction Port P Bit 6 */ + byte DDRP7 :1; /* Data Direction Port P Bit 7 */ + } Bits; + struct { + byte grpDDRP :8; + } MergedBits; +} DDRPSTR; +extern volatile DDRPSTR _DDRP @(REG_BASE + 0x0000025A); +#define DDRP _DDRP.Byte +#define DDRP_DDRP0 _DDRP.Bits.DDRP0 +#define DDRP_DDRP1 _DDRP.Bits.DDRP1 +#define DDRP_DDRP2 _DDRP.Bits.DDRP2 +#define DDRP_DDRP3 _DDRP.Bits.DDRP3 +#define DDRP_DDRP4 _DDRP.Bits.DDRP4 +#define DDRP_DDRP5 _DDRP.Bits.DDRP5 +#define DDRP_DDRP6 _DDRP.Bits.DDRP6 +#define DDRP_DDRP7 _DDRP.Bits.DDRP7 +#define DDRP_DDRP _DDRP.MergedBits.grpDDRP + + +/*** RDRP - Port P Reduced Drive Register; 0x0000025B ***/ +typedef union { + byte Byte; + struct { + byte RDRP0 :1; /* Reduced Drive Port P Bit 0 */ + byte RDRP1 :1; /* Reduced Drive Port P Bit 1 */ + byte RDRP2 :1; /* Reduced Drive Port P Bit 2 */ + byte RDRP3 :1; /* Reduced Drive Port P Bit 3 */ + byte RDRP4 :1; /* Reduced Drive Port P Bit 4 */ + byte RDRP5 :1; /* Reduced Drive Port P Bit 5 */ + byte RDRP6 :1; /* Reduced Drive Port P Bit 6 */ + byte RDRP7 :1; /* Reduced Drive Port P Bit 7 */ + } Bits; + struct { + byte grpRDRP :8; + } MergedBits; +} RDRPSTR; +extern volatile RDRPSTR _RDRP @(REG_BASE + 0x0000025B); +#define RDRP _RDRP.Byte +#define RDRP_RDRP0 _RDRP.Bits.RDRP0 +#define RDRP_RDRP1 _RDRP.Bits.RDRP1 +#define RDRP_RDRP2 _RDRP.Bits.RDRP2 +#define RDRP_RDRP3 _RDRP.Bits.RDRP3 +#define RDRP_RDRP4 _RDRP.Bits.RDRP4 +#define RDRP_RDRP5 _RDRP.Bits.RDRP5 +#define RDRP_RDRP6 _RDRP.Bits.RDRP6 +#define RDRP_RDRP7 _RDRP.Bits.RDRP7 +#define RDRP_RDRP _RDRP.MergedBits.grpRDRP + + +/*** PERP - Port P Pull Device Enable Register; 0x0000025C ***/ +typedef union { + byte Byte; + struct { + byte PERP0 :1; /* Pull Device Enable Port P Bit 0 */ + byte PERP1 :1; /* Pull Device Enable Port P Bit 1 */ + byte PERP2 :1; /* Pull Device Enable Port P Bit 2 */ + byte PERP3 :1; /* Pull Device Enable Port P Bit 3 */ + byte PERP4 :1; /* Pull Device Enable Port P Bit 4 */ + byte PERP5 :1; /* Pull Device Enable Port P Bit 5 */ + byte PERP6 :1; /* Pull Device Enable Port P Bit 6 */ + byte PERP7 :1; /* Pull Device Enable Port P Bit 7 */ + } Bits; + struct { + byte grpPERP :8; + } MergedBits; +} PERPSTR; +extern volatile PERPSTR _PERP @(REG_BASE + 0x0000025C); +#define PERP _PERP.Byte +#define PERP_PERP0 _PERP.Bits.PERP0 +#define PERP_PERP1 _PERP.Bits.PERP1 +#define PERP_PERP2 _PERP.Bits.PERP2 +#define PERP_PERP3 _PERP.Bits.PERP3 +#define PERP_PERP4 _PERP.Bits.PERP4 +#define PERP_PERP5 _PERP.Bits.PERP5 +#define PERP_PERP6 _PERP.Bits.PERP6 +#define PERP_PERP7 _PERP.Bits.PERP7 +#define PERP_PERP _PERP.MergedBits.grpPERP + + +/*** PPSP - Port P Polarity Select Register; 0x0000025D ***/ +typedef union { + byte Byte; + struct { + byte PPSP0 :1; /* Pull Select Port P Bit 0 */ + byte PPSP1 :1; /* Pull Select Port P Bit 1 */ + byte PPSP2 :1; /* Pull Select Port P Bit 2 */ + byte PPSP3 :1; /* Pull Select Port P Bit 3 */ + byte PPSP4 :1; /* Pull Select Port P Bit 4 */ + byte PPSP5 :1; /* Pull Select Port P Bit 5 */ + byte PPSP6 :1; /* Pull Select Port P Bit 6 */ + byte PPSP7 :1; /* Pull Select Port P Bit 7 */ + } Bits; + struct { + byte grpPPSP :8; + } MergedBits; +} PPSPSTR; +extern volatile PPSPSTR _PPSP @(REG_BASE + 0x0000025D); +#define PPSP _PPSP.Byte +#define PPSP_PPSP0 _PPSP.Bits.PPSP0 +#define PPSP_PPSP1 _PPSP.Bits.PPSP1 +#define PPSP_PPSP2 _PPSP.Bits.PPSP2 +#define PPSP_PPSP3 _PPSP.Bits.PPSP3 +#define PPSP_PPSP4 _PPSP.Bits.PPSP4 +#define PPSP_PPSP5 _PPSP.Bits.PPSP5 +#define PPSP_PPSP6 _PPSP.Bits.PPSP6 +#define PPSP_PPSP7 _PPSP.Bits.PPSP7 +#define PPSP_PPSP _PPSP.MergedBits.grpPPSP + + +/*** PIEP - Port P Interrupt Enable Register; 0x0000025E ***/ +typedef union { + byte Byte; + struct { + byte PIEP0 :1; /* Interrupt Enable Port P Bit 0 */ + byte PIEP1 :1; /* Interrupt Enable Port P Bit 1 */ + byte PIEP2 :1; /* Interrupt Enable Port P Bit 2 */ + byte PIEP3 :1; /* Interrupt Enable Port P Bit 3 */ + byte PIEP4 :1; /* Interrupt Enable Port P Bit 4 */ + byte PIEP5 :1; /* Interrupt Enable Port P Bit 5 */ + byte PIEP6 :1; /* Interrupt Enable Port P Bit 6 */ + byte PIEP7 :1; /* Interrupt Enable Port P Bit 7 */ + } Bits; + struct { + byte grpPIEP :8; + } MergedBits; +} PIEPSTR; +extern volatile PIEPSTR _PIEP @(REG_BASE + 0x0000025E); +#define PIEP _PIEP.Byte +#define PIEP_PIEP0 _PIEP.Bits.PIEP0 +#define PIEP_PIEP1 _PIEP.Bits.PIEP1 +#define PIEP_PIEP2 _PIEP.Bits.PIEP2 +#define PIEP_PIEP3 _PIEP.Bits.PIEP3 +#define PIEP_PIEP4 _PIEP.Bits.PIEP4 +#define PIEP_PIEP5 _PIEP.Bits.PIEP5 +#define PIEP_PIEP6 _PIEP.Bits.PIEP6 +#define PIEP_PIEP7 _PIEP.Bits.PIEP7 +#define PIEP_PIEP _PIEP.MergedBits.grpPIEP + + +/*** PIFP - Port P Interrupt Flag Register; 0x0000025F ***/ +typedef union { + byte Byte; + struct { + byte PIFP0 :1; /* Interrupt Flags Port P Bit 0 */ + byte PIFP1 :1; /* Interrupt Flags Port P Bit 1 */ + byte PIFP2 :1; /* Interrupt Flags Port P Bit 2 */ + byte PIFP3 :1; /* Interrupt Flags Port P Bit 3 */ + byte PIFP4 :1; /* Interrupt Flags Port P Bit 4 */ + byte PIFP5 :1; /* Interrupt Flags Port P Bit 5 */ + byte PIFP6 :1; /* Interrupt Flags Port P Bit 6 */ + byte PIFP7 :1; /* Interrupt Flags Port P Bit 7 */ + } Bits; + struct { + byte grpPIFP :8; + } MergedBits; +} PIFPSTR; +extern volatile PIFPSTR _PIFP @(REG_BASE + 0x0000025F); +#define PIFP _PIFP.Byte +#define PIFP_PIFP0 _PIFP.Bits.PIFP0 +#define PIFP_PIFP1 _PIFP.Bits.PIFP1 +#define PIFP_PIFP2 _PIFP.Bits.PIFP2 +#define PIFP_PIFP3 _PIFP.Bits.PIFP3 +#define PIFP_PIFP4 _PIFP.Bits.PIFP4 +#define PIFP_PIFP5 _PIFP.Bits.PIFP5 +#define PIFP_PIFP6 _PIFP.Bits.PIFP6 +#define PIFP_PIFP7 _PIFP.Bits.PIFP7 +#define PIFP_PIFP _PIFP.MergedBits.grpPIFP + + +/*** PTJ - Port J I/O Register; 0x00000268 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte PTJ6 :1; /* Port J Bit 6 */ + byte PTJ7 :1; /* Port J Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpPTJ_6 :2; + } MergedBits; +} PTJSTR; +extern volatile PTJSTR _PTJ @(REG_BASE + 0x00000268); +#define PTJ _PTJ.Byte +#define PTJ_PTJ6 _PTJ.Bits.PTJ6 +#define PTJ_PTJ7 _PTJ.Bits.PTJ7 +#define PTJ_PTJ_6 _PTJ.MergedBits.grpPTJ_6 + + +/*** PTIJ - Port J Input Register; 0x00000269 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte PTIJ6 :1; /* Port J Bit 6 */ + byte PTIJ7 :1; /* Port J Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpPTIJ_6 :2; + } MergedBits; +} PTIJSTR; +extern volatile PTIJSTR _PTIJ @(REG_BASE + 0x00000269); +#define PTIJ _PTIJ.Byte +#define PTIJ_PTIJ6 _PTIJ.Bits.PTIJ6 +#define PTIJ_PTIJ7 _PTIJ.Bits.PTIJ7 +#define PTIJ_PTIJ_6 _PTIJ.MergedBits.grpPTIJ_6 + + +/*** DDRJ - Port J Data Direction Register; 0x0000026A ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte DDRJ6 :1; /* Data Direction Port J Bit 6 */ + byte DDRJ7 :1; /* Data Direction Port J Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpDDRJ_6 :2; + } MergedBits; +} DDRJSTR; +extern volatile DDRJSTR _DDRJ @(REG_BASE + 0x0000026A); +#define DDRJ _DDRJ.Byte +#define DDRJ_DDRJ6 _DDRJ.Bits.DDRJ6 +#define DDRJ_DDRJ7 _DDRJ.Bits.DDRJ7 +#define DDRJ_DDRJ_6 _DDRJ.MergedBits.grpDDRJ_6 + + +/*** RDRJ - Port J Reduced Drive Register; 0x0000026B ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte RDRJ6 :1; /* Reduced Drive Port J Bit 6 */ + byte RDRJ7 :1; /* Reduced Drive Port J Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpRDRJ_6 :2; + } MergedBits; +} RDRJSTR; +extern volatile RDRJSTR _RDRJ @(REG_BASE + 0x0000026B); +#define RDRJ _RDRJ.Byte +#define RDRJ_RDRJ6 _RDRJ.Bits.RDRJ6 +#define RDRJ_RDRJ7 _RDRJ.Bits.RDRJ7 +#define RDRJ_RDRJ_6 _RDRJ.MergedBits.grpRDRJ_6 + + +/*** PERJ - Port J Pull Device Enable Register; 0x0000026C ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte PERJ6 :1; /* Pull Device Enable Port J Bit 6 */ + byte PERJ7 :1; /* Pull Device Enable Port J Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpPERJ_6 :2; + } MergedBits; +} PERJSTR; +extern volatile PERJSTR _PERJ @(REG_BASE + 0x0000026C); +#define PERJ _PERJ.Byte +#define PERJ_PERJ6 _PERJ.Bits.PERJ6 +#define PERJ_PERJ7 _PERJ.Bits.PERJ7 +#define PERJ_PERJ_6 _PERJ.MergedBits.grpPERJ_6 + + +/*** PPSJ - PortJP Polarity Select Register; 0x0000026D ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte PPSJ6 :1; /* Pull Select Port J Bit 6 */ + byte PPSJ7 :1; /* Pull Select Port J Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpPPSJ_6 :2; + } MergedBits; +} PPSJSTR; +extern volatile PPSJSTR _PPSJ @(REG_BASE + 0x0000026D); +#define PPSJ _PPSJ.Byte +#define PPSJ_PPSJ6 _PPSJ.Bits.PPSJ6 +#define PPSJ_PPSJ7 _PPSJ.Bits.PPSJ7 +#define PPSJ_PPSJ_6 _PPSJ.MergedBits.grpPPSJ_6 + + +/*** PIEJ - Port J Interrupt Enable Register; 0x0000026E ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte PIEJ6 :1; /* Interrupt Enable Port J Bit 6 */ + byte PIEJ7 :1; /* Interrupt Enable Port J Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpPIEJ_6 :2; + } MergedBits; +} PIEJSTR; +extern volatile PIEJSTR _PIEJ @(REG_BASE + 0x0000026E); +#define PIEJ _PIEJ.Byte +#define PIEJ_PIEJ6 _PIEJ.Bits.PIEJ6 +#define PIEJ_PIEJ7 _PIEJ.Bits.PIEJ7 +#define PIEJ_PIEJ_6 _PIEJ.MergedBits.grpPIEJ_6 + + +/*** PIFJ - Port J Interrupt Flag Register; 0x0000026F ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte PIFJ6 :1; /* Interrupt Flags Port J Bit 6 */ + byte PIFJ7 :1; /* Interrupt Flags Port J Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpPIFJ_6 :2; + } MergedBits; +} PIFJSTR; +extern volatile PIFJSTR _PIFJ @(REG_BASE + 0x0000026F); +#define PIFJ _PIFJ.Byte +#define PIFJ_PIFJ6 _PIFJ.Bits.PIFJ6 +#define PIFJ_PIFJ7 _PIFJ.Bits.PIFJ7 +#define PIFJ_PIFJ_6 _PIFJ.MergedBits.grpPIFJ_6 + + +/*** PTAD - Port AD I/O Register; 0x00000270 ***/ +typedef union { + byte Byte; + struct { + byte PTAD0 :1; /* Port AD Bit 0 */ + byte PTAD1 :1; /* Port AD Bit 1 */ + byte PTAD2 :1; /* Port AD Bit 2 */ + byte PTAD3 :1; /* Port AD Bit 3 */ + byte PTAD4 :1; /* Port AD Bit 4 */ + byte PTAD5 :1; /* Port AD Bit 5 */ + byte PTAD6 :1; /* Port AD Bit 6 */ + byte PTAD7 :1; /* Port AD Bit 7 */ + } Bits; + struct { + byte grpPTAD :8; + } MergedBits; +} PTADSTR; +extern volatile PTADSTR _PTAD @(REG_BASE + 0x00000270); +#define PTAD _PTAD.Byte +#define PTAD_PTAD0 _PTAD.Bits.PTAD0 +#define PTAD_PTAD1 _PTAD.Bits.PTAD1 +#define PTAD_PTAD2 _PTAD.Bits.PTAD2 +#define PTAD_PTAD3 _PTAD.Bits.PTAD3 +#define PTAD_PTAD4 _PTAD.Bits.PTAD4 +#define PTAD_PTAD5 _PTAD.Bits.PTAD5 +#define PTAD_PTAD6 _PTAD.Bits.PTAD6 +#define PTAD_PTAD7 _PTAD.Bits.PTAD7 +#define PTAD_PTAD _PTAD.MergedBits.grpPTAD + + +/*** PTIAD - Port AD Input Register; 0x00000271 ***/ +typedef union { + byte Byte; + struct { + byte PTIAD0 :1; /* Port AD Bit 0 */ + byte PTIAD1 :1; /* Port AD Bit 1 */ + byte PTIAD2 :1; /* Port AD Bit 2 */ + byte PTIAD3 :1; /* Port AD Bit 3 */ + byte PTIAD4 :1; /* Port AD Bit 4 */ + byte PTIAD5 :1; /* Port AD Bit 5 */ + byte PTIAD6 :1; /* Port AD Bit 6 */ + byte PTIAD7 :1; /* Port AD Bit 7 */ + } Bits; + struct { + byte grpPTIAD :8; + } MergedBits; +} PTIADSTR; +extern volatile PTIADSTR _PTIAD @(REG_BASE + 0x00000271); +#define PTIAD _PTIAD.Byte +#define PTIAD_PTIAD0 _PTIAD.Bits.PTIAD0 +#define PTIAD_PTIAD1 _PTIAD.Bits.PTIAD1 +#define PTIAD_PTIAD2 _PTIAD.Bits.PTIAD2 +#define PTIAD_PTIAD3 _PTIAD.Bits.PTIAD3 +#define PTIAD_PTIAD4 _PTIAD.Bits.PTIAD4 +#define PTIAD_PTIAD5 _PTIAD.Bits.PTIAD5 +#define PTIAD_PTIAD6 _PTIAD.Bits.PTIAD6 +#define PTIAD_PTIAD7 _PTIAD.Bits.PTIAD7 +#define PTIAD_PTIAD _PTIAD.MergedBits.grpPTIAD + + +/*** DDRAD - Port AD Data Direction Register; 0x00000272 ***/ +typedef union { + byte Byte; + struct { + byte DDRAD0 :1; /* Port AD Data Direction Bit 0 */ + byte DDRAD1 :1; /* Port AD Data Direction Bit 1 */ + byte DDRAD2 :1; /* Port AD Data Direction Bit 2 */ + byte DDRAD3 :1; /* Port AD Data Direction Bit 3 */ + byte DDRAD4 :1; /* Port AD Data Direction Bit 4 */ + byte DDRAD5 :1; /* Port AD Data Direction Bit 5 */ + byte DDRAD6 :1; /* Port AD Data Direction Bit 6 */ + byte DDRAD7 :1; /* Port AD Data Direction Bit 7 */ + } Bits; + struct { + byte grpDDRAD :8; + } MergedBits; +} DDRADSTR; +extern volatile DDRADSTR _DDRAD @(REG_BASE + 0x00000272); +#define DDRAD _DDRAD.Byte +#define DDRAD_DDRAD0 _DDRAD.Bits.DDRAD0 +#define DDRAD_DDRAD1 _DDRAD.Bits.DDRAD1 +#define DDRAD_DDRAD2 _DDRAD.Bits.DDRAD2 +#define DDRAD_DDRAD3 _DDRAD.Bits.DDRAD3 +#define DDRAD_DDRAD4 _DDRAD.Bits.DDRAD4 +#define DDRAD_DDRAD5 _DDRAD.Bits.DDRAD5 +#define DDRAD_DDRAD6 _DDRAD.Bits.DDRAD6 +#define DDRAD_DDRAD7 _DDRAD.Bits.DDRAD7 +#define DDRAD_DDRAD _DDRAD.MergedBits.grpDDRAD + + +/*** RDRAD - Port AD Reduced Drive Register; 0x00000273 ***/ +typedef union { + byte Byte; + struct { + byte RDRAD0 :1; /* Port AD Reduced Drive Bit 0 */ + byte RDRAD1 :1; /* Port AD Reduced Drive Bit 1 */ + byte RDRAD2 :1; /* Port AD Reduced Drive Bit 2 */ + byte RDRAD3 :1; /* Port AD Reduced Drive Bit 3 */ + byte RDRAD4 :1; /* Port AD Reduced Drive Bit 4 */ + byte RDRAD5 :1; /* Port AD Reduced Drive Bit 5 */ + byte RDRAD6 :1; /* Port AD Reduced Drive Bit 6 */ + byte RDRAD7 :1; /* Port AD Reduced Drive Bit 7 */ + } Bits; + struct { + byte grpRDRAD :8; + } MergedBits; +} RDRADSTR; +extern volatile RDRADSTR _RDRAD @(REG_BASE + 0x00000273); +#define RDRAD _RDRAD.Byte +#define RDRAD_RDRAD0 _RDRAD.Bits.RDRAD0 +#define RDRAD_RDRAD1 _RDRAD.Bits.RDRAD1 +#define RDRAD_RDRAD2 _RDRAD.Bits.RDRAD2 +#define RDRAD_RDRAD3 _RDRAD.Bits.RDRAD3 +#define RDRAD_RDRAD4 _RDRAD.Bits.RDRAD4 +#define RDRAD_RDRAD5 _RDRAD.Bits.RDRAD5 +#define RDRAD_RDRAD6 _RDRAD.Bits.RDRAD6 +#define RDRAD_RDRAD7 _RDRAD.Bits.RDRAD7 +#define RDRAD_RDRAD _RDRAD.MergedBits.grpRDRAD + + +/*** PERAD - Port AD Pull Device Enable Register; 0x00000274 ***/ +typedef union { + byte Byte; + struct { + byte PERAD0 :1; /* Port AD Pull Device Enable Bit 0 */ + byte PERAD1 :1; /* Port AD Pull Device Enable Bit 1 */ + byte PERAD2 :1; /* Port AD Pull Device Enable Bit 2 */ + byte PERAD3 :1; /* Port AD Pull Device Enable Bit 3 */ + byte PERAD4 :1; /* Port AD Pull Device Enable Bit 4 */ + byte PERAD5 :1; /* Port AD Pull Device Enable Bit 5 */ + byte PERAD6 :1; /* Port AD Pull Device Enable Bit 6 */ + byte PERAD7 :1; /* Port AD Pull Device Enable Bit 7 */ + } Bits; + struct { + byte grpPERAD :8; + } MergedBits; +} PERADSTR; +extern volatile PERADSTR _PERAD @(REG_BASE + 0x00000274); +#define PERAD _PERAD.Byte +#define PERAD_PERAD0 _PERAD.Bits.PERAD0 +#define PERAD_PERAD1 _PERAD.Bits.PERAD1 +#define PERAD_PERAD2 _PERAD.Bits.PERAD2 +#define PERAD_PERAD3 _PERAD.Bits.PERAD3 +#define PERAD_PERAD4 _PERAD.Bits.PERAD4 +#define PERAD_PERAD5 _PERAD.Bits.PERAD5 +#define PERAD_PERAD6 _PERAD.Bits.PERAD6 +#define PERAD_PERAD7 _PERAD.Bits.PERAD7 +#define PERAD_PERAD _PERAD.MergedBits.grpPERAD + + +/*** PPSAD - Port AD Polarity Select Register; 0x00000275 ***/ +typedef union { + byte Byte; + struct { + byte PPSAD0 :1; /* Port AD Polarity Select Bit 0 */ + byte PPSAD1 :1; /* Port AD Polarity Select Bit 1 */ + byte PPSAD2 :1; /* Port AD Polarity Select Bit 2 */ + byte PPSAD3 :1; /* Port AD Polarity Select Bit 3 */ + byte PPSAD4 :1; /* Port AD Polarity Select Bit 4 */ + byte PPSAD5 :1; /* Port AD Polarity Select Bit 5 */ + byte PPSAD6 :1; /* Port AD Polarity Select Bit 6 */ + byte PPSAD7 :1; /* Port AD Polarity Select Bit 7 */ + } Bits; + struct { + byte grpPPSAD :8; + } MergedBits; +} PPSADSTR; +extern volatile PPSADSTR _PPSAD @(REG_BASE + 0x00000275); +#define PPSAD _PPSAD.Byte +#define PPSAD_PPSAD0 _PPSAD.Bits.PPSAD0 +#define PPSAD_PPSAD1 _PPSAD.Bits.PPSAD1 +#define PPSAD_PPSAD2 _PPSAD.Bits.PPSAD2 +#define PPSAD_PPSAD3 _PPSAD.Bits.PPSAD3 +#define PPSAD_PPSAD4 _PPSAD.Bits.PPSAD4 +#define PPSAD_PPSAD5 _PPSAD.Bits.PPSAD5 +#define PPSAD_PPSAD6 _PPSAD.Bits.PPSAD6 +#define PPSAD_PPSAD7 _PPSAD.Bits.PPSAD7 +#define PPSAD_PPSAD _PPSAD.MergedBits.grpPPSAD + + +/*** BDMSTS - BDM Status Register; 0x0000FF01 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte UNSEC :1; /* Unsecure */ + byte CLKSW :1; /* Clock switch */ + byte TRACE :1; /* TRACE1 BDM firmware command is being executed */ + byte SDV :1; /* Shift data valid */ + byte ENTAG :1; /* Tagging enable */ + byte BDMACT :1; /* BDM active status */ + byte ENBDM :1; /* Enable BDM */ + } Bits; +} BDMSTSSTR; +extern volatile BDMSTSSTR _BDMSTS @(0x0000FF01); +#define BDMSTS _BDMSTS.Byte +#define BDMSTS_UNSEC _BDMSTS.Bits.UNSEC +#define BDMSTS_CLKSW _BDMSTS.Bits.CLKSW +#define BDMSTS_TRACE _BDMSTS.Bits.TRACE +#define BDMSTS_SDV _BDMSTS.Bits.SDV +#define BDMSTS_ENTAG _BDMSTS.Bits.ENTAG +#define BDMSTS_BDMACT _BDMSTS.Bits.BDMACT +#define BDMSTS_ENBDM _BDMSTS.Bits.ENBDM + + +/*** BDMCCR - BDM CCR Holding Register; 0x0000FF06 ***/ +typedef union { + byte Byte; + struct { + byte CCR0 :1; /* BDM CCR Holding Bit 0 */ + byte CCR1 :1; /* BDM CCR Holding Bit 1 */ + byte CCR2 :1; /* BDM CCR Holding Bit 2 */ + byte CCR3 :1; /* BDM CCR Holding Bit 3 */ + byte CCR4 :1; /* BDM CCR Holding Bit 4 */ + byte CCR5 :1; /* BDM CCR Holding Bit 5 */ + byte CCR6 :1; /* BDM CCR Holding Bit 6 */ + byte CCR7 :1; /* BDM CCR Holding Bit 7 */ + } Bits; + struct { + byte grpCCR :8; + } MergedBits; +} BDMCCRSTR; +extern volatile BDMCCRSTR _BDMCCR @(0x0000FF06); +#define BDMCCR _BDMCCR.Byte +#define BDMCCR_CCR0 _BDMCCR.Bits.CCR0 +#define BDMCCR_CCR1 _BDMCCR.Bits.CCR1 +#define BDMCCR_CCR2 _BDMCCR.Bits.CCR2 +#define BDMCCR_CCR3 _BDMCCR.Bits.CCR3 +#define BDMCCR_CCR4 _BDMCCR.Bits.CCR4 +#define BDMCCR_CCR5 _BDMCCR.Bits.CCR5 +#define BDMCCR_CCR6 _BDMCCR.Bits.CCR6 +#define BDMCCR_CCR7 _BDMCCR.Bits.CCR7 +#define BDMCCR_CCR _BDMCCR.MergedBits.grpCCR + + +/*** BDMINR - BDM Internal Register Position Register; 0x0000FF07 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte REG11 :1; /* Internal register map position */ + byte REG12 :1; /* Internal register map position */ + byte REG13 :1; /* Internal register map position */ + byte REG14 :1; /* Internal register map position */ + byte REG15 :1; /* Internal register map position */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte grpREG_11 :5; + } MergedBits; +} BDMINRSTR; +extern volatile BDMINRSTR _BDMINR @(0x0000FF07); +#define BDMINR _BDMINR.Byte +#define BDMINR_REG11 _BDMINR.Bits.REG11 +#define BDMINR_REG12 _BDMINR.Bits.REG12 +#define BDMINR_REG13 _BDMINR.Bits.REG13 +#define BDMINR_REG14 _BDMINR.Bits.REG14 +#define BDMINR_REG15 _BDMINR.Bits.REG15 +#define BDMINR_REG_11 _BDMINR.MergedBits.grpREG_11 +#define BDMINR_REG BDMINR_REG_11 + + + /* Watchdog reset macro */ +#ifdef _lint + #define __RESET_WATCHDOG() /* empty */ +#else + #define __RESET_WATCHDOG() {asm sta COPCTL;} /* Just write a byte to feed the dog */ +#endif + +#endif + +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ + diff --git a/20080212/Demo/HCS12_CodeWarrior_small/CODE/PESL.h b/20080212/Demo/HCS12_CodeWarrior_small/CODE/PESL.h new file mode 100644 index 000000000..9f79f6868 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_small/CODE/PESL.h @@ -0,0 +1,52 @@ +/* ================================================================================================================================= ** +** ================================================================================================================================= ** +** CONFIGURATION FILE FOR PESL LIBRARY ** +** ================================================================================================================================= ** +** ================================================================================================================================= */ + +#define _MC9S12A128_112 1 +#define _MC9S12A128_80 2 +#define _MC9S12A256_112 3 +#define _MC9S12A256_80 4 +#define _MC9S12A64_112 5 +#define _MC9S12A64_80 6 +#define _MC9S12C32_48 7 +#define _MC9S12C32_52 8 +#define _MC9S12C32_80 9 +#define _MC9S12D64_112 10 +#define _MC9S12D64_80 11 +#define _MC9S12DB128_112 12 +#define _MC9S12DG128_112 13 +#define _MC9S12DG128_80 14 +#define _MC9S12DG256_112 15 +#define _MC9S12DJ128_112 16 +#define _MC9S12DJ128_80 17 +#define _MC9S12DJ256_112 18 +#define _MC9S12DJ256_80 19 +#define _MC9S12DJ64_112 20 +#define _MC9S12DJ64_80 21 +#define _MC9S12DP256_112 22 +#define _MC9S12DT128_112 23 +#define _MC9S12DT256_112 24 +#define _MC9S12A32_80 25 +#define _MC9S12D32_80 26 +#define _MC9S12DP512_112 27 +#define _MC9S12A512_112 28 +#define _MC9S12E128_112 29 +#define _MC9S12E128_80 30 +#define _MC9S12E64_112 31 + + +/* Selected target MCU */ + +#define CPUtype _MC9S12C32_80 + + +/* PESL library */ + +#pragma MESSAGE DISABLE C4000 /* WARNING C4000: Condition is always TRUE */ +#pragma MESSAGE DISABLE C4001 /* WARNING C4001: Condition is always FALSE */ + +#include "PESLlib.h" + + diff --git a/20080212/Demo/HCS12_CodeWarrior_small/CODE/PE_Const.H b/20080212/Demo/HCS12_CodeWarrior_small/CODE/PE_Const.H new file mode 100644 index 000000000..2f0b2f1ca --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_small/CODE/PE_Const.H @@ -0,0 +1,50 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : PE_Const.H +** Project : RTOSDemo +** Processor : MC9S12C32CFU +** Beantype : PE_Const +** Version : Driver 01.00 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 10/05/2005, 11:11 +** Abstract : +** This bean "PE_Const" contains internal definitions +** of the constants. +** Settings : +** Contents : +** No public methods +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + +#ifndef __PE_Const_H +#define __PE_Const_H + +/* Constants for detecting running mode */ +#define HIGH_SPEED 0 /* High speed */ +#define LOW_SPEED 1 /* Low speed */ +#define SLOW_SPEED 2 /* Slow speed */ + +/* Reset cause constants */ +#define RSTSRC_POR 1 /* Power-on reset */ +#define RSTSRC_PIN 8 /* External reset bit */ +#define RSTSRC_COP 4 /* COP reset */ +#define RSTSRC_ILOP 2 /* Illegal opcode reset */ +#define RSTSRC_ILAD 16 /* Illegal address reset */ +#define RSTSRC_LVI 32 /* Low voltage inhibit reset */ + +#endif /* _PE_Const_H */ +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/20080212/Demo/HCS12_CodeWarrior_small/CODE/PE_Error.H b/20080212/Demo/HCS12_CodeWarrior_small/CODE/PE_Error.H new file mode 100644 index 000000000..2025f4e0a --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_small/CODE/PE_Error.H @@ -0,0 +1,53 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : PE_Error.H +** Project : RTOSDemo +** Processor : MC9S12C32CFU +** Beantype : PE_Error +** Version : Driver 01.00 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 10/05/2005, 11:11 +** Abstract : +** This bean "PE_Error" contains internal definitions +** of the error constants. +** Settings : +** Contents : +** No public methods +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + +#ifndef __PE_Error_H +#define __PE_Error_H + +#define ERR_OK 0 /* OK */ +#define ERR_SPEED 1 /* This device does not work in the active speed mode. */ +#define ERR_RANGE 2 /* Parameter out of range. */ +#define ERR_VALUE 3 /* Parameter of incorrect value. */ +#define ERR_OVERFLOW 4 /* Timer overflow. */ +#define ERR_MATH 5 /* Overflow during evaluation. */ +#define ERR_ENABLED 6 /* Device is enabled. */ +#define ERR_DISABLED 7 /* Device is disabled. */ +#define ERR_BUSY 8 /* Device is busy. */ +#define ERR_NOTAVAIL 9 /* Requested value or method not available. */ +#define ERR_RXEMPTY 10 /* No data in receiver. */ +#define ERR_TXFULL 11 /* Transmitter is full. */ +#define ERR_BUSOFF 12 /* Bus not available. */ +#define ERR_OVERRUN 13 /* Overrun error is detected. */ +#define ERR_FRAMING 14 /* Framing error is detected. */ +#define ERR_PARITY 15 /* Parity error is detected. */ +#define ERR_NOISE 16 /* Noise error is detected. */ +#define ERR_IDLE 17 /* Idle error is detectes. */ +#define ERR_FAULT 18 /* Fault error is detected. */ +#define ERR_BREAK 19 /* Break char is received during communication. */ +#define ERR_CRC 20 /* CRC error is detected. */ +#define ERR_ARBITR 21 /* A node losts arbitration. This error occurs if two nodes start transmission at the same time. */ +#define ERR_PROTECT 22 /* Protection error is detected. */ + +#endif __PE_Error_H diff --git a/20080212/Demo/HCS12_CodeWarrior_small/CODE/PE_Timer.C b/20080212/Demo/HCS12_CodeWarrior_small/CODE/PE_Timer.C new file mode 100644 index 000000000..3618734f6 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_small/CODE/PE_Timer.C @@ -0,0 +1,69 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : PE_Timer.C +** Project : RTOSDemo +** Processor : MC9S12C32CFU +** Beantype : PE_Timer +** Version : Driver 01.00 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 17/05/2005, 08:44 +** Abstract : +** This bean "PE_Timer" implements internal methods and definitions +** used by beans working with timers. +** Settings : +** Contents : +** No public methods +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + + +/* MODULE PE_Timer. */ + +#include "PE_Timer.h" + + +/* +** =================================================================== +** Method : PE_Timer_LngHi1 (bean PE_Timer) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +bool PE_Timer_LngHi1(dword High, dword Low, word *Out) +{ + if ((High == 0) && ((Low >> 24) == 0)) + if ((Low & 0x80) != 0) { + if ((Low >> 8) < 0xFFFF) { + *Out = ((unsigned int)(Low >> 8))+1; + return FALSE; + } + } + else { + *Out = (unsigned int)(Low >> 8); + return FALSE; + } + *Out = (unsigned int)(Low >> 8); + return TRUE; +} + + + +/* END PE_Timer. */ + +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/20080212/Demo/HCS12_CodeWarrior_small/CODE/PE_Timer.H b/20080212/Demo/HCS12_CodeWarrior_small/CODE/PE_Timer.H new file mode 100644 index 000000000..1ec107559 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_small/CODE/PE_Timer.H @@ -0,0 +1,53 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : PE_Timer.H +** Project : RTOSDemo +** Processor : MC9S12C32CFU +** Beantype : PE_Timer +** Version : Driver 01.00 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 17/05/2005, 08:44 +** Abstract : +** This bean "PE_Timer" implements internal methods and definitions +** used by beans working with timers. +** Settings : +** Contents : +** No public methods +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ +#ifndef __PE_Timer +#define __PE_Timer +/*Include shared modules, which are used for whole project*/ +#include "PE_types.h" +#include "PE_const.h" + +/* MODULE PE_Timer. */ + +bool PE_Timer_LngHi1(dword Low, dword High, word *Out); +/* +** =================================================================== +** Method : PE_Timer_LngHi1 (bean PE_Timer) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ + + +#endif /* END PE_Timer. */ +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/20080212/Demo/HCS12_CodeWarrior_small/CODE/PE_Types.H b/20080212/Demo/HCS12_CodeWarrior_small/CODE/PE_Types.H new file mode 100644 index 000000000..42c849ebd --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_small/CODE/PE_Types.H @@ -0,0 +1,87 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : PE_Types.H +** Project : RTOSDemo +** Processor : MC9S12C32CFU +** Beantype : PE_Types +** Version : Driver 01.04 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 10/05/2005, 11:11 +** Abstract : +** This bean "PE_Types" contains internal definitions +** of the types. +** Settings : +** Contents : +** No public methods +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + +#ifndef __PE_Types_H +#define __PE_Types_H + +#define FALSE 0 +#define TRUE 1 + +/*Types definition*/ +typedef unsigned char bool; +typedef unsigned char byte; +typedef unsigned int word; +typedef unsigned long dword; +typedef unsigned long dlong[2]; +typedef void (*tIntFunc)(void); + +/* Motorola types */ +typedef unsigned char VUINT8; +typedef signed char VINT8; +typedef unsigned short int VUINT16; +typedef signed short int VINT16; +typedef unsigned long int VUINT32; + +#define in16(var,l,h) var = ((word)(l)) | (((word)(h)) << 8) +#define out16(l,h,val) { l = (byte)val; h = (byte)(val >> 8); } + +#define output(P, V) P = (V) +#define input(P) (P) + +#define __DI() { asm sei; } /* Disable global interrupts */ +#define __EI() { asm cli; } /* Enable global interrupts */ +#define EnterCritical() { __asm pshc; __asm sei; __asm movb 1,SP+,CCR_reg; } /* This macro is used by Processor Expert. It saves CCR register and disable global interrupts. */ +#define ExitCritical() { __asm movb CCR_reg, 1,-SP; __asm pulc; } /* This macro is used by Processor Expert. It restores CCR register saved in SaveStatusReg(). */ +/* obsolete definition for backward compatibility */ +#define SaveStatusReg() EnterCritical() +#define RestoreStatusReg() ExitCritical() + + +typedef struct { /* Black&White Image */ + word width; /* Image width */ + word height; /* Image height */ + byte *pixmap; /* Image pixel bitmap */ + word size; /* Image size */ + char *name; /* Image name */ +} TIMAGE; +typedef TIMAGE* PIMAGE ; /* Pointer to image */ + +/* 16-bit register (Motorola format - big endian) */ +typedef union { + word w; + struct { + byte high,low; + } b; +} TWREG; + +#endif /* __PE_Types_H */ +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/20080212/Demo/HCS12_CodeWarrior_small/CODE/RTOSDemo.C b/20080212/Demo/HCS12_CodeWarrior_small/CODE/RTOSDemo.C new file mode 100644 index 000000000..95899d4ea --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_small/CODE/RTOSDemo.C @@ -0,0 +1,66 @@ +/** ################################################################### +** Filename : RTOSDemo.C +** Project : RTOSDemo +** Processor : MC9S12C32CFU +** Version : Driver 01.05 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 10/05/2005, 11:11 +** Abstract : +** Main module. +** Here is to be placed user's code. +** Settings : +** Contents : +** No public methods +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ +/* MODULE RTOSDemo */ + +/* Including used modules for compilling procedure */ +#include "Cpu.h" +#include "Events.h" +#include "Byte1.h" +#include "TickTimer.h" +#include "ButtonInterrupt.h" +/* Include shared modules, which are used for whole project */ +#include "PE_Types.h" +#include "PE_Error.h" +#include "PE_Const.h" +#include "IO_Map.h" + +extern void vMain( void ); + +void main(void) +{ + /*** Processor Expert internal initialization. DON'T REMOVE THIS CODE!!! ***/ + PE_low_level_init(); + /*** End of Processor Expert internal initialization. ***/ + + /*Write your code here*/ + + /* Just jump to the real main(). */ + __asm + { + jmp vMain + } + + /*** Processor Expert end of main routine. DON'T MODIFY THIS CODE!!! ***/ + for(;;); + /*** Processor Expert end of main routine. DON'T WRITE CODE BELOW!!! ***/ +} /*** End of main routine. DO NOT MODIFY THIS TEXT!!! ***/ + +/* END RTOSDemo */ +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/20080212/Demo/HCS12_CodeWarrior_small/CODE/RTOSDemo.PRM b/20080212/Demo/HCS12_CodeWarrior_small/CODE/RTOSDemo.PRM new file mode 100644 index 000000000..cfa3147fd --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_small/CODE/RTOSDemo.PRM @@ -0,0 +1,48 @@ +/* +** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : RTOSDemo.PRM +** Project : RTOSDemo +** Processor : MC9S12C32CFU +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 18/06/2005, 18:00 +** Abstract : +** This file is used by the linker. It describes files to be linked, +** memory ranges, stack size, etc. For detailed description of the PRM file +** see CodeWarrior documentation. This file is generated by default. +** You can switch off generation by setting the property +** "Generate PRM file = no" on the "Build options" tab in CPU bean and then modify +** this file if needed. +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ################################################################### +*/ + +NAMES + +END + +SECTIONS + /* List of all sections specified on the "Build options" tab */ + RAM = READ_WRITE 0x00000800 TO 0x00000FFF; + ROM_C000 = READ_ONLY 0x0000C000 TO 0x0000FF7F; + ROM_4000 = READ_ONLY 0x00004000 TO 0x00007FFF; +END + +PLACEMENT + DEFAULT_RAM INTO RAM; + _PRESTART, STARTUP, + ROM_VAR, STRINGS, + NON_BANKED, DEFAULT_ROM, COPY INTO ROM_C000, ROM_4000; +END + +INIT _EntryPoint /* The entry point of the application. This function is generated into the CPU module. */ + +STACKSIZE 0x0030 /* Size of the system stack. Value can be changed on the "Build options" tab */ + diff --git a/20080212/Demo/HCS12_CodeWarrior_small/CODE/TickTimer.C b/20080212/Demo/HCS12_CodeWarrior_small/CODE/TickTimer.C new file mode 100644 index 000000000..d00bb65cc --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_small/CODE/TickTimer.C @@ -0,0 +1,243 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : TickTimer.C +** Project : RTOSDemo +** Processor : MC9S12C32CFU +** Beantype : TimerInt +** Version : Bean 02.063, Driver 01.05, CPU db: 2.87.276 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 18/06/2005, 17:53 +** Abstract : +** This bean "TimerInt" implements a periodic interrupt. +** When the bean and its events are enabled, the "OnInterrupt" +** event is called periodically with the period that you specify. +** TimerInt supports also changing the period in runtime. +** The source of periodic interrupt can be timer compare or reload +** register or timer-overflow interrupt (of free running counter). +** Settings : +** Timer name : TIM (16-bit) +** Compare name : TC0 +** Counter shared : No +** +** High-speed CPU mode +** Prescaler : divide-by-4 +** Clock : 5999000 Hz +** Initial period/frequency +** Xtal ticks : 16000 +** microseconds : 1000 +** milliseconds : 1 +** seconds (real) : 0.0010000 +** Hz : 1000 +** kHz : 1 +** +** Runtime setting : period/frequency interval (continual setting) +** ticks : 16000 to 160000 ticks +** microseconds : 1000 to 10000 microseconds +** milliseconds : 1 to 10 milliseconds +** seconds (real) : 0.0010000 to 0.0100000 seconds +** Hz : 100 to 1000 Hz +** +** Initialization: +** Timer : Disabled +** Events : Enabled +** +** Timer registers +** Counter : TCNT [68] +** Mode : TIOS [64] +** Run : TSCR1 [70] +** Prescaler : TSCR2 [77] +** +** Compare registers +** Compare : TC0 [80] +** +** Flip-flop registers +** Mode : TCTL2 [73] +** Contents : +** Enable - byte TickTimer_Enable(void); +** SetFreqHz - byte TickTimer_SetFreqHz(word Freq); +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + + +/* MODULE TickTimer. */ + +#include "Events.h" +#include "TickTimer.h" + +/* Definition of DATA and CODE segments for this bean. User can specify where + these segments will be located on "Build options" tab of the selected CPU bean. */ +#pragma DATA_SEG TickTimer_DATA /* Data section for this module. */ +#pragma CODE_SEG TickTimer_CODE /* Code section for this module. */ + +static bool EnUser; /* Enable/Disable device by user */ +static word CmpHighVal; /* Compare register value for high speed CPU mode */ + + +/* +** =================================================================== +** Method : SetCV (bean TimerInt) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +static void SetCV(word Val) +{ + if (Val == 0) /* If the given value is zero */ + Val = 65535; /* then change it to the maximal one */ + TC0 = Val; /* Store given value to the compare register */ + TC7 = Val; /* Store given value to the modulo register */ +} + +/* +** =================================================================== +** Method : SetPV (bean TimerInt) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +static void SetPV(byte Val) +{ + TSCR2_PR = Val; /* Store given value to the prescaler */ +} + +/* +** =================================================================== +** Method : HWEnDi (bean TimerInt) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +static void HWEnDi(void) +{ + if (EnUser) { /* Enable device? */ + TFLG1 = 1; /* Reset interrupt request flag */ + TIE_C0I = 1; /* Enable interrupt */ + } + else { /* Disable device? */ + TIE_C0I = 0; /* Disable interrupt */ + } +} + +/* +** =================================================================== +** Method : TickTimer_Enable (bean TimerInt) +** +** Description : +** Enable the bean - it starts the timer. Events may be +** generated ("DisableEvent"/"EnableEvent"). +** Parameters : None +** Returns : +** --- - Error code, possible codes: +** ERR_OK - OK +** ERR_SPEED - This device does not work in +** the active speed mode +** =================================================================== +*/ +byte TickTimer_Enable(void) +{ + if (!EnUser) { /* Is the device disabled by user? */ + EnUser = TRUE; /* If yes then set the flag "device enabled" */ + HWEnDi(); /* Enable the device */ + } + return ERR_OK; /* OK */ +} + +/* +** =================================================================== +** Method : TickTimer_SetFreqHz (bean TimerInt) +** +** Description : +** This method sets the new frequency of the generated +** events. The frequency is expressed in Hz as a 16-bit +** unsigned integer number. +** This method is available only if runtime setting type +** 'from interval' is selected in the Timing dialog box in +** Runtime setting area. +** Parameters : +** NAME - DESCRIPTION +** Freq - Frequency to set [in Hz] +** (100 to 1000 Hz) +** Returns : +** --- - Error code, possible codes: +** ERR_OK - OK +** ERR_SPEED - This device does not work in +** the active speed mode +** ERR_MATH - Overflow during evaluation +** ERR_RANGE - Parameter out of range +** =================================================================== +*/ +byte TickTimer_SetFreqHz(word Freq) +{ + dlong rtval; /* Result of two 32-bit numbers division */ + word rtword; /* Result of 64-bit number division */ + + if ((Freq > 1000) || (Freq < 100)) /* Is the given value out of range? */ + return ERR_RANGE; /* If yes then error */ + rtval[1] = 1535744000 / (dword)Freq; /* Divide high speed CPU mode coefficient by the given value */ + rtval[0] = 0; /* Convert result to the type dlong */ + if (PE_Timer_LngHi1(rtval[0],rtval[1],&rtword)) /* Is the result greater or equal than 65536 ? */ + rtword = 65535; /* If yes then use maximal possible value */ + CmpHighVal = rtword; /* Store result (compare register value for high speed CPU mode) to the variable CmpHighVal */ + SetCV(CmpHighVal); /* Store appropriate value to the compare register according to the selected high speed CPU mode */ + return ERR_OK; /* OK */ +} + +/* +** =================================================================== +** Method : TickTimer_Init (bean TimerInt) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +void TickTimer_Init(void) +{ + CmpHighVal = 5999; /* Compare register value for high speed CPU mode */ + EnUser = FALSE; /* Disable device */ + SetCV(CmpHighVal); /* Store appropriate value to the compare register according to the selected high speed CPU mode */ + SetPV(2); /* Set prescaler register according to the selected high speed CPU mode */ + HWEnDi(); /* Enable/disable device according to status flags */ +} + +/* +** =================================================================== +** Method : TickTimer_Interrupt (bean TimerInt) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ +#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */ +__interrupt void TickTimer_Interrupt(void) +{ + TFLG1 = 1; /* Reset interrupt request flag */ + vTaskTickInterrupt(); /* Invoke user event */ +} + +#pragma CODE_SEG TickTimer_CODE /* Code section for this module. */ + +/* END TickTimer. */ + +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/20080212/Demo/HCS12_CodeWarrior_small/CODE/TickTimer.H b/20080212/Demo/HCS12_CodeWarrior_small/CODE/TickTimer.H new file mode 100644 index 000000000..f0818fd9e --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_small/CODE/TickTimer.H @@ -0,0 +1,160 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : TickTimer.H +** Project : RTOSDemo +** Processor : MC9S12C32CFU +** Beantype : TimerInt +** Version : Bean 02.063, Driver 01.05, CPU db: 2.87.276 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 18/06/2005, 17:53 +** Abstract : +** This bean "TimerInt" implements a periodic interrupt. +** When the bean and its events are enabled, the "OnInterrupt" +** event is called periodically with the period that you specify. +** TimerInt supports also changing the period in runtime. +** The source of periodic interrupt can be timer compare or reload +** register or timer-overflow interrupt (of free running counter). +** Settings : +** Timer name : TIM (16-bit) +** Compare name : TC0 +** Counter shared : No +** +** High-speed CPU mode +** Prescaler : divide-by-4 +** Clock : 5999000 Hz +** Initial period/frequency +** Xtal ticks : 16000 +** microseconds : 1000 +** milliseconds : 1 +** seconds (real) : 0.0010000 +** Hz : 1000 +** kHz : 1 +** +** Runtime setting : period/frequency interval (continual setting) +** ticks : 16000 to 160000 ticks +** microseconds : 1000 to 10000 microseconds +** milliseconds : 1 to 10 milliseconds +** seconds (real) : 0.0010000 to 0.0100000 seconds +** Hz : 100 to 1000 Hz +** +** Initialization: +** Timer : Disabled +** Events : Enabled +** +** Timer registers +** Counter : TCNT [68] +** Mode : TIOS [64] +** Run : TSCR1 [70] +** Prescaler : TSCR2 [77] +** +** Compare registers +** Compare : TC0 [80] +** +** Flip-flop registers +** Mode : TCTL2 [73] +** Contents : +** Enable - byte TickTimer_Enable(void); +** SetFreqHz - byte TickTimer_SetFreqHz(word Freq); +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + +#ifndef __TickTimer +#define __TickTimer + +/* MODULE TickTimer. */ + +#include "Cpu.h" + +#pragma CODE_SEG TickTimer_CODE /* Code section for this module. */ + +#define TickTimer_SFHzMin 100 /* Lower bound of interval for method SetFreqHz */ +#define TickTimer_SFHzMax 1000 /* Upper bound of interval for method SetFreqHz */ + + +byte TickTimer_Enable(void); +/* +** =================================================================== +** Method : TickTimer_Enable (bean TimerInt) +** +** Description : +** Enable the bean - it starts the timer. Events may be +** generated ("DisableEvent"/"EnableEvent"). +** Parameters : None +** Returns : +** --- - Error code, possible codes: +** ERR_OK - OK +** ERR_SPEED - This device does not work in +** the active speed mode +** =================================================================== +*/ + +byte TickTimer_SetFreqHz(word Freq); +/* +** =================================================================== +** Method : TickTimer_SetFreqHz (bean TimerInt) +** +** Description : +** This method sets the new frequency of the generated +** events. The frequency is expressed in Hz as a 16-bit +** unsigned integer number. +** This method is available only if runtime setting type +** 'from interval' is selected in the Timing dialog box in +** Runtime setting area. +** Parameters : +** NAME - DESCRIPTION +** Freq - Frequency to set [in Hz] +** (100 to 1000 Hz) +** Returns : +** --- - Error code, possible codes: +** ERR_OK - OK +** ERR_SPEED - This device does not work in +** the active speed mode +** ERR_MATH - Overflow during evaluation +** ERR_RANGE - Parameter out of range +** =================================================================== +*/ + +#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */ +__interrupt void TickTimer_Interrupt(void); +#pragma CODE_SEG TickTimer_CODE /* Code section for this module. */ +/* +** =================================================================== +** Method : TickTimer_Interrupt (bean TimerInt) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ + +void TickTimer_Init(void); +/* +** =================================================================== +** Method : TickTimer_Init (bean TimerInt) +** +** Description : +** This method is internal. It is used by Processor Expert +** only. +** =================================================================== +*/ + +#pragma CODE_SEG DEFAULT /* Change code section to DEFAULT. */ + +/* END TickTimer. */ + +#endif /* ifndef __TickTimer */ +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ diff --git a/20080212/Demo/HCS12_CodeWarrior_small/CODE/Vectors.c b/20080212/Demo/HCS12_CodeWarrior_small/CODE/Vectors.c new file mode 100644 index 000000000..38854b315 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_small/CODE/Vectors.c @@ -0,0 +1,115 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : Cpu.C +** Project : RTOSDemo +** Processor : MC9S12C32CFU +** Beantype : MC9S12C32_80 +** Version : Bean 01.002, Driver 01.09, CPU db: 2.87.276 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 17/05/2005, 18:22 +** Abstract : +** This bean "MC9S12C32_80" implements properties, methods, +** and events of the CPU. +** Settings : +** +** Contents : +** EnableInt - void Cpu_EnableInt(void); +** DisableInt - void Cpu_DisableInt(void); +** SetWaitMode - void Cpu_SetWaitMode(void); +** SetStopMode - void Cpu_SetStopMode(void); +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + + +#include "Cpu.h" +#include "Byte1.h" +#include "TickTimer.h" +#include "ButtonInterrupt.h" + +extern void near _EntryPoint(void); /* Startup routine */ +extern void near vPortTickInterrupt( void ); +extern void near vPortYield( void ); +extern void near vButtonPush( void ); + +typedef void (*near tIsrFunc)(void); +const tIsrFunc _vect[] @0xFF80 = { /* Interrupt table */ + Cpu_Interrupt, /* 0 Default (unused) interrupt */ + Cpu_Interrupt, /* 1 Default (unused) interrupt */ + Cpu_Interrupt, /* 2 Default (unused) interrupt */ + Cpu_Interrupt, /* 3 Default (unused) interrupt */ + Cpu_Interrupt, /* 4 Default (unused) interrupt */ + Cpu_Interrupt, /* 5 Default (unused) interrupt */ + Cpu_Interrupt, /* 6 Default (unused) interrupt */ + vButtonPush, /* 7 Default (unused) interrupt */ + Cpu_Interrupt, /* 8 Default (unused) interrupt */ + Cpu_Interrupt, /* 9 Default (unused) interrupt */ + Cpu_Interrupt, /* 10 Default (unused) interrupt */ + Cpu_Interrupt, /* 11 Default (unused) interrupt */ + Cpu_Interrupt, /* 12 Default (unused) interrupt */ + Cpu_Interrupt, /* 13 Default (unused) interrupt */ + Cpu_Interrupt, /* 14 Default (unused) interrupt */ + Cpu_Interrupt, /* 15 Default (unused) interrupt */ + Cpu_Interrupt, /* 16 Default (unused) interrupt */ + Cpu_Interrupt, /* 17 Default (unused) interrupt */ + Cpu_Interrupt, /* 18 Default (unused) interrupt */ + Cpu_Interrupt, /* 19 Default (unused) interrupt */ + Cpu_Interrupt, /* 20 Default (unused) interrupt */ + Cpu_Interrupt, /* 21 Default (unused) interrupt */ + Cpu_Interrupt, /* 22 Default (unused) interrupt */ + Cpu_Interrupt, /* 23 Default (unused) interrupt */ + Cpu_Interrupt, /* 24 Default (unused) interrupt */ + Cpu_Interrupt, /* 25 Default (unused) interrupt */ + Cpu_Interrupt, /* 26 Default (unused) interrupt */ + Cpu_Interrupt, /* 27 Default (unused) interrupt */ + Cpu_Interrupt, /* 28 Default (unused) interrupt */ + Cpu_Interrupt, /* 29 Default (unused) interrupt */ + Cpu_Interrupt, /* 30 Default (unused) interrupt */ + Cpu_Interrupt, /* 31 Default (unused) interrupt */ + Cpu_Interrupt, /* 32 Default (unused) interrupt */ + Cpu_Interrupt, /* 33 Default (unused) interrupt */ + Cpu_Interrupt, /* 34 Default (unused) interrupt */ + Cpu_Interrupt, /* 35 Default (unused) interrupt */ + Cpu_Interrupt, /* 36 Default (unused) interrupt */ + Cpu_Interrupt, /* 37 Default (unused) interrupt */ + Cpu_Interrupt, /* 38 Default (unused) interrupt */ + Cpu_Interrupt, /* 39 Default (unused) interrupt */ + Cpu_Interrupt, /* 40 Default (unused) interrupt */ + Cpu_Interrupt, /* 41 Default (unused) interrupt */ + Cpu_Interrupt, /* 42 Default (unused) interrupt */ + Cpu_Interrupt, /* 43 Default (unused) interrupt */ + Cpu_Interrupt, /* 44 Default (unused) interrupt */ + Cpu_Interrupt, /* 45 Default (unused) interrupt */ + Cpu_Interrupt, /* 46 Default (unused) interrupt */ + Cpu_Interrupt, /* 47 Default (unused) interrupt */ + Cpu_Interrupt, /* 48 Default (unused) interrupt */ + Cpu_Interrupt, /* 49 Default (unused) interrupt */ + Cpu_Interrupt, /* 50 Default (unused) interrupt */ + Cpu_Interrupt, /* 51 Default (unused) interrupt */ + Cpu_Interrupt, /* 52 Default (unused) interrupt */ + Cpu_Interrupt, /* 53 Default (unused) interrupt */ + Cpu_Interrupt, /* 54 Default (unused) interrupt */ + vPortTickInterrupt, + Cpu_Interrupt, /* 56 Default (unused) interrupt */ + Cpu_Interrupt, /* 57 Default (unused) interrupt */ + Cpu_Interrupt, /* 58 Default (unused) interrupt */ + vPortYield, /* 59 Default (unused) interrupt */ + Cpu_Interrupt, /* 60 Default (unused) interrupt */ + Cpu_Interrupt, /* 61 Default (unused) interrupt */ + Cpu_Interrupt, /* 62 Default (unused) interrupt */ + _EntryPoint /* Reset vector */ + }; +/* +** ################################################################### +** +** This file was created by UNIS Processor Expert 03.33 for +** the Motorola HCS12 series of microcontrollers. +** +** ################################################################### +*/ \ No newline at end of file diff --git a/20080212/Demo/HCS12_CodeWarrior_small/C_Layout.hwl b/20080212/Demo/HCS12_CodeWarrior_small/C_Layout.hwl new file mode 100644 index 000000000..3b16d98a4 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_small/C_Layout.hwl @@ -0,0 +1,20 @@ +OPEN source 0 0 60 39 +Source < attributes MARKS off +OPEN assembly 60 0 40 31 +Assembly < attributes ADR on,CODE off,ABSADR on,SYMB off,TOPPC 0xF88C +OPEN procedure 0 39 60 17 +Procedure < attributes VALUES on,TYPES off +OPEN register 60 31 40 25 +Register < attributes FORMAT AUTO,COMPLEMENT None +OPEN memory 60 56 40 22 +Memory < attributes FORMAT hex,COMPLEMENT None,WORD 1,ASC on,ADR on,ADDRESS 0x80 +OPEN data 0 56 60 22 +Data:1 < attributes SCOPE global,COMPLEMENT None,FORMAT Symb,MODE automatic,UPDATERATE 10,NAMEWIDTH 16 +OPEN data 0 78 60 22 +Data:2 < attributes SCOPE local,COMPLEMENT None,FORMAT Symb,MODE automatic,UPDATERATE 10,NAMEWIDTH 16 +OPEN command 60 78 40 22 +Command < attributes CACHESIZE 1000 +bckcolor 50331647 +font 'Courier New' 9 BLACK +AUTOSIZE on +ACTIVATE Data:2 Command Procedure Data:1 Source Register Assembly Memory diff --git a/20080212/Demo/HCS12_CodeWarrior_small/DOC/RTOSDemo.sig b/20080212/Demo/HCS12_CodeWarrior_small/DOC/RTOSDemo.sig new file mode 100644 index 000000000..7931aed92 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_small/DOC/RTOSDemo.sig @@ -0,0 +1,23 @@ +================================================================= +This file was generated from Processor Expert 03.33 + project "RTOSDemo", 18/06/2005, 18:00 +----------------------------------------------------------------- +There is no signal defined in this project. + Hint: Signals may be defined in the Bean Inspector (advanced or expert view) +================================================================= + +================================================================= + SIGNAL LIST +----------------------------------------------------------------- + SIGNAL NAME => PIN NAME +----------------------------------------------------------------- +================================================================= + + +================================================================= + PIN LIST +----------------------------------------------------------------- + PIN NAME => SIGNAL NAME +----------------------------------------------------------------- +================================================================= + diff --git a/20080212/Demo/HCS12_CodeWarrior_small/DOC/RTOSDemo.txt b/20080212/Demo/HCS12_CodeWarrior_small/DOC/RTOSDemo.txt new file mode 100644 index 000000000..7bfe268c6 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_small/DOC/RTOSDemo.txt @@ -0,0 +1,32 @@ +============================================================================= +List of methods in project: RTOSDemo + +THIS TEXT DESCRIPTION IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +============================================================================= + +Module "Byte1" (bean ByteIO) + Byte1_PutBit -Put the specified value to the specified bit/pin of the Input/Output bean. If direction is [input] saves the + value to a memory or a register, this value will be written to the pin after switching to the output mode - + using [SetDir(TRUE)]. If direction is [output] writes the value to the pin. + Byte1_NegBit -Negate (invert) the specified bit of the Input/Output bean. It is the same as [PutBit(Bit,!GetBit(Bit))]. + +Module "TickTimer" (bean TimerInt) + TickTimer_Enable -Enable the bean - it starts the timer. Events may be generated ("DisableEvent"/"EnableEvent"). + TickTimer_SetFreqHz -This method sets the new frequency of the generated events. The frequency is expressed in [Hz] as a + 16-bit unsigned integer number. This method is available only if runtime setting type 'from interval' is + selected in the in Runtime setting area. + +Module "ButtonInterrupt" (bean ExtInt) + ButtonInterrupt_Enable -Enable the bean - the external events are accepted. + +Module "Cpu" (bean MC9S12C32_80) + Cpu_EnableInt -Enable maskable interrupts + Cpu_DisableInt -Disable maskable interrupts + Cpu_SetWaitMode -Set low power mode - Wait mode. +For more information about the wait mode see documentation of this CPU. + +Release from Wait mode: Reset or interrupt + Cpu_SetStopMode -Set low power mode - Stop mode. +For more information about the stop mode see documentation of this CPU. + +============================================================================= diff --git a/20080212/Demo/HCS12_CodeWarrior_small/FreeRTOSConfig.h b/20080212/Demo/HCS12_CodeWarrior_small/FreeRTOSConfig.h new file mode 100644 index 000000000..6266b41da --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_small/FreeRTOSConfig.h @@ -0,0 +1,98 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include /* common defines and macros */ +#include "TickTimer.h" + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 0 +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 70 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 2048 - 256 ) ) +#define configMAX_TASK_NAME_LEN ( 1 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 1 +#define configIDLE_SHOULD_YIELD 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* This parameter is normally required in order to set the RTOS tick timer. +This port is a bit different in that hardware setup uses the code generated by +the Processor Expert, making this definition obsolete. + +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 24000000 ) +*/ + + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + + + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/HCS12_CodeWarrior_small/ParTest/ParTest.c b/20080212/Demo/HCS12_CodeWarrior_small/ParTest/ParTest.c new file mode 100644 index 000000000..365ee3927 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_small/ParTest/ParTest.c @@ -0,0 +1,79 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "portable.h" + +/* Processor Expert created headers. */ +#include "byte1.h" + +/* Demo application include files. */ +#include "partest.h" + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ + /* This function is required as it is called from the standard demo + application files. All it does however is call the Processor Expert + created function. */ + portENTER_CRITICAL(); + Byte1_PutBit( uxLED, !xValue ); + portEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ + /* This function is required as it is called from the standard demo + application files. All it does however is call the processor Expert + created function. */ + portENTER_CRITICAL(); + Byte1_NegBit( uxLED ); + portEXIT_CRITICAL(); +} + + + diff --git a/20080212/Demo/HCS12_CodeWarrior_small/RTOSDemo.G_C b/20080212/Demo/HCS12_CodeWarrior_small/RTOSDemo.G_C new file mode 100644 index 000000000..f25c6b4af --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_small/RTOSDemo.G_C @@ -0,0 +1,368 @@ +;Please do not modify this file! +;The file contains internal information about the Processor Expert project generation +[Options] +ProjectName=RTOSDemo +ProjectDirectory=E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_small\ +DestEventsDirectory=CODE\ +DestDriversSubDirectory= +DestDocumentationDirectory=DOC\ +DestCompiledFilesSubDirectory= +DestFpgaSubDirectory= +DestTemporaryDirectory= +[GenFiles] +LinkerFileGenerated=Yes +MakefileGenerated=No +GenSharedModules=5 +Line=PE_Types +Line=PE_Error +Line=PE_Const +Line=IO_Map +Line=PE_Timer +ShrdHeaderAge0=850024804 +ShrdCodeAge0=-1 +ShrdAsemblAge0=-1 +ShrdHeaderAge1=850024804 +ShrdCodeAge1=-1 +ShrdAsemblAge1=-1 +ShrdHeaderAge2=850024804 +ShrdCodeAge2=-1 +ShrdAsemblAge2=-1 +ShrdHeaderAge3=850024804 +ShrdCodeAge3=850024804 +ShrdAsemblAge3=-1 +ShrdHeaderAge4=850478475 +ShrdCodeAge4=850478475 +ShrdAsemblAge4=-1 +GenExtraFiles=2 +Line=E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_small\CODE\Vectors.c +Line=E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_small\CODE\PESL.h +XtraAge0=852660312 +XtraAge1=850024804 +GenExtraFileType1=4 +GenExtraFileType0=4 +GenEventModules=1 +Line=Events +GenMethodsInEvents=0 +GenAllModules=10 +Line=ButtonInterrupt +Line=Byte1 +Line=Cpu +Line=Events +Line=IO_Map +Line=PE_Const +Line=PE_Error +Line=PE_Timer +Line=PE_Types +Line=TickTimer +GenExternModules=0 +GenBeanModules=3 +Line=ButtonInterrupt +Line=TickTimer +Line=Byte1 +SignalListFile=E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_small\DOC\RTOSDemo.sig +DestinationCompiler=MetrowerksHC12CC +ProjectModificationStamp=23 + +[18] +Generated=Yes +GenCompName=Cpu +GenEventModule=Events +HeaderAge=850478231 +CodeAge=852660246 +AsemblAge=-1 +GenNumMethods=10 +SetStopMode=Yes +SetWaitMode=Yes +DisableInt=Yes +EnableInt=Yes +GetIntVect=No +SetIntVect=No +GetSpeedMode=No +SetSlowSpeed=No +SetLowSpeed=No +SetHighSpeed=No +GenNumEvents=4 +OnClockMonitorFail_Selected=1 +OnClockMonitorFail_Name=Cpu_OnClockMonitorFail +OnClockMonitorFail_Priority=interrupts disabled +OnIllegalOpcode_Selected=1 +OnIllegalOpcode_Name=Cpu_OnIllegalOpcode +OnIllegalOpcode_Priority=interrupts disabled +OnReset_Selected=1 +OnReset_Name=Cpu_OnReset +OnReset_Priority=interrupts disabled +OnSwINT_Selected=1 +OnSwINT_Name=Cpu_OnSwINT +OnSwINT_Priority=interrupts disabled +GenSmartUserChangesDetected_Header=No +GenSmartUserChangesDetected_Code=No +GenSmartUserChangesDetected_Asembl=No + +[22] +Generated=Yes +GenCompName=Byte1 +GenEventModule=Events +HeaderAge=850026034 +CodeAge=850026034 +AsemblAge=-1 +GenNumMethods=9 +NegBit=Yes +ClrBit=No +SetBit=No +PutBit=Yes +GetBit=No +PutVal=No +GetVal=No +SetDir=No +GetDir=No +GenNumEvents=0 +GenSmartUserChangesDetected_Header=No +GenSmartUserChangesDetected_Code=No +GenSmartUserChangesDetected_Asembl=No +GenMethodPos=5 +MethodPos0=PutBit +MethodType=method +ModuleType=Header +LineBeg=65 +LineEnd=81 +MethodPos1=NegBit +MethodType=method +ModuleType=Header +LineBeg=82 +LineEnd=96 +MethodPos2=GetMsk +MethodType=internal_method +ModuleType=Code +LineBeg=67 +LineEnd=82 +MethodPos3=PutBit +MethodType=method +ModuleType=Code +LineBeg=83 +LineEnd=110 +MethodPos4=NegBit +MethodType=method +ModuleType=Code +LineBeg=111 +LineEnd=132 + +[25] +Generated=Yes +GenCompName=TickTimer +GenEventModule=Events +HeaderAge=852659892 +CodeAge=852659892 +AsemblAge=-1 +GenNumMethods=14 +SetFreqMHz=No +SetFreqkHz=No +SetFreqHz=Yes +SetPeriodReal=No +SetPeriodSec=No +SetPeriodMS=No +SetPeriodUS=No +SetPeriodTicks32=No +SetPeriodTicks16=No +SetPeriodMode=No +DisableEvent=No +EnableEvent=No +Disable=No +Enable=Yes +GenNumEvents=3 +BeforeNewSpeed_Selected=1 +BeforeNewSpeed_Name=TickTimer_BeforeNewSpeed +BeforeNewSpeed_Priority=interrupts disabled +AfterNewSpeed_Selected=1 +AfterNewSpeed_Name=TickTimer_AfterNewSpeed +AfterNewSpeed_Priority=interrupts disabled +OnInterrupt_Selected=2 +OnInterrupt_Name=vTaskTickInterrupt +OnInterrupt_Priority=same as interrupt +GenSmartUserChangesDetected_Header=No +GenSmartUserChangesDetected_Code=No +GenSmartUserChangesDetected_Asembl=No +GenMethodPos=11 +MethodPos0=Enable +MethodType=method +ModuleType=Header +LineBeg=80 +LineEnd=96 +MethodPos1=SetFreqHz +MethodType=method +ModuleType=Header +LineBeg=97 +LineEnd=122 +MethodPos2=Interrupt +MethodType=internal_method +ModuleType=Header +LineBeg=123 +LineEnd=135 +MethodPos3=Init +MethodType=internal_method +ModuleType=Header +LineBeg=136 +LineEnd=146 +MethodPos4=SetCV +MethodType=internal_method +ModuleType=Code +LineBeg=82 +LineEnd=98 +MethodPos5=SetPV +MethodType=internal_method +ModuleType=Code +LineBeg=99 +LineEnd=112 +MethodPos6=HWEnDi +MethodType=internal_method +ModuleType=Code +LineBeg=113 +LineEnd=132 +MethodPos7=Enable +MethodType=method +ModuleType=Code +LineBeg=133 +LineEnd=156 +MethodPos8=SetFreqHz +MethodType=method +ModuleType=Code +LineBeg=157 +LineEnd=196 +MethodPos9=Init +MethodType=internal_method +ModuleType=Code +LineBeg=197 +LineEnd=214 +MethodPos10=Interrupt +MethodType=internal_method +ModuleType=Code +LineBeg=215 +LineEnd=231 + +[26] +Generated=Yes +GenCompName=ButtonInterrupt +GenEventModule=Events +HeaderAge=850630744 +CodeAge=850630744 +AsemblAge=-1 +GenNumMethods=4 +SetEdge=No +GetVal=No +Disable=No +Enable=Yes +GenNumEvents=1 +OnInterrupt_Selected=2 +OnInterrupt_Name=ButtonInterrupt_OnInterrupt +OnInterrupt_Priority=same as interrupt +GenSmartUserChangesDetected_Header=No +GenSmartUserChangesDetected_Code=No +GenSmartUserChangesDetected_Asembl=No +GenMethodPos=4 +MethodPos0=Enable +MethodType=method +ModuleType=Header +LineBeg=71 +LineEnd=82 +MethodPos1=Interrupt +MethodType=internal_method +ModuleType=Header +LineBeg=83 +LineEnd=95 +MethodPos2=Enable +MethodType=method +ModuleType=Code +LineBeg=73 +LineEnd=88 +MethodPos3=Interrupt +MethodType=internal_method +ModuleType=Code +LineBeg=89 +LineEnd=105 + +[UsedSrcFiles] +SrcFile=Drivers\ByteIO.src=779379247 +SrcFile=Drivers\HCS12\ByteIO.drv=786325143 +SrcFile=Drivers\Common\Header.h=788035759 +SrcFile=Drivers\Common\ByteIOAbstract.Inc=697533609 +SrcFile=Drivers\Common\ByteIOSettings.Inc=662077581 +SrcFile=Drivers\Common\UsedPins.inc=662077580 +SrcFile=Drivers\HCS12\CreateCodeSection.prg=759717537 +SrcFile=Drivers\Common\ByteIOPutBit.Inc=662077581 +SrcFile=Drivers\Common\GeneralPutBit.inc=724263173 +SrcFile=Drivers\Common\GeneralMethod.inc=711812818 +SrcFile=Drivers\Common\GeneralParameters.inc=711813750 +SrcFile=Drivers\Common\GeneralReturnNothing.inc=711816104 +SrcFile=Drivers\Common\GeneralDamage.inc=711813453 +SrcFile=Drivers\Common\ByteIONegBit.Inc=662077581 +SrcFile=Drivers\Common\GeneralNegBit.inc=724263119 +SrcFile=Drivers\Common\Header.End=710308512 +SrcFile=Drivers\Common\Header.c=788035759 +SrcFile=Drivers\HCS12\CreateDataSection.prg=759780817 +SrcFile=Drivers\Common\GeneralInternal.Inc=724263004 +SrcFile=Drivers\TimerInt.src=779379233 +SrcFile=Drivers\HCS12\TimerInt.drv=790330280 +SrcFile=Drivers\Common\TimerIntAbstract.Inc=697533454 +SrcFile=Drivers\Common\TimerIntSettings.Inc=662077596 +SrcFile=Drivers\Common\TimerIntEnable.Inc=724722488 +SrcFile=Drivers\Common\GeneralParametersNone.inc=711813294 +SrcFile=Drivers\Common\TimerIntSetFreqHz.Inc=724921137 +SrcFile=Drivers\HCS12\CreateIntSection.prg=760697835 +SrcFile=Drivers\Common\TimerIntInterrupt.Inc=662077583 +SrcFile=Drivers\Common\TimerIntOnInterrupt.Inc=724722488 +SrcFile=Drivers\Common\GeneralEvent.inc=711816218 +SrcFile=Drivers\Common\GeneralInternalGlobal.Inc=724263104 +SrcFile=Drivers\Common\InitReg8.prg=727217490 +SrcFile=Drivers\Common\InitReg8Enable.prg=783766675 +SrcFile=Drivers\ExtInt.src=779379242 +SrcFile=Drivers\HCS12\ExternalInterrupt.drv=786325143 +SrcFile=Drivers\Common\ExternalInterruptAbstract.Inc=697533660 +SrcFile=Drivers\Common\ExternalInterruptSettings.Inc=662077582 +SrcFile=Drivers\Common\UsedPin.inc=662077580 +SrcFile=Drivers\Common\ExternalInterruptEnable.Inc=724459205 +SrcFile=Drivers\Common\ExternalInterruptOnInterrupt.inc=724459205 +SrcFile=Drivers\HCS12\PE_Types.drv=790261986 +SrcFile=Drivers\Common\PE_TypesAbstract.Inc=662077595 +SrcFile=Drivers\Common\PE_TypesSettings.Inc=662077595 +SrcFile=Drivers\HCS12\PE_Error.drv=744839008 +SrcFile=Drivers\Common\PE_ErrorAbstract.Inc=662077580 +SrcFile=Drivers\Common\ErrorDefinitions.Inc=781282486 +SrcFile=Drivers\HCS12\PE_Const.drv=744839020 +SrcFile=Drivers\Common\PE_ConstAbstract.Inc=662077595 +SrcFile=Drivers\Common\PE_ConstSettings.Inc=662077595 +SrcFile=Drivers\HCS12\IO_Map.drv=790392555 +SrcFile=Drivers\Common\IO_MapAbstract.Inc=662077601 +SrcFile=Drivers\Common\IO_MapSettings.Inc=662077601 +SrcFile=Drivers\HCS12\MC9S12C32_80h.prg=788297413 +SrcFile=Drivers\HCS12\MC9S12C32_80c.prg=787968924 +SrcFile=Drivers\HCS12\PE_Timer.drv=764054261 +SrcFile=Drivers\Common\PE_TimerConstants.Inc=662077594 +SrcFile=Drivers\Common\PE_TimerMethods.Inc=662077585 +SrcFile=Drivers\Common\PE_TimerAbstract.Inc=662077594 +SrcFile=Drivers\Common\PE_TimerSettings.Inc=662077581 +SrcFile=Drivers\Common\PE_TimerLngHi1.Inc=662077594 +SrcFile=Drivers\MC9S12C32_80.src=783110234 +SrcFile=Drivers\HCS12\MC9S12.drv=788297552 +SrcFile=Drivers\Common\MC9S12Abstract.Inc=786070990 +SrcFile=Drivers\Common\MC9S12Settings.Inc=786070990 +SrcFile=Drivers\Common\MC9S12SetStopMode.Inc=786070990 +SrcFile=Drivers\Common\MC9S12SetWaitMode.Inc=786070990 +SrcFile=Drivers\Common\MC9S12DisableInt.Inc=786070990 +SrcFile=Drivers\Common\MC9S12EnableInt.Inc=786070990 +SrcFile=Drivers\Common\GenReg8InitInfo.prg=754344225 +SrcFile=Drivers\Common\GenReg8BitsInitInfo.prg=777356856 +SrcFile=Drivers\Common\CommonInitialization.prg=760832797 +SrcFile=Drivers\Common\CommonRegInitialization.prg=785882407 +SrcFile=Drivers\Common\SetRegBits8.prg=775453568 +SrcFile=Drivers\Common\SetReg8.prg=776374479 +SrcFile=Drivers\Common\CommonEnabling.prg=783766630 +SrcFile=Drivers\Common\CommonRegEnabling.prg=785882407 +SrcFile=Drivers\HCS12\PESL.prg=790397020 +SrcFile=Drivers\Event.src=779379228 +SrcFile=Drivers\HCS12\Evnt.drv=763978411 +SrcFile=Drivers\Common\EvntAbstract.Inc=662077596 +SrcFile=Drivers\Common\EvntSettings.inc=662077580 +SrcFile=Drivers\Common\Header.In1=710699431 +SrcFile=Drivers\_PE_ProjectInfo.src=713322570 +SrcFile=Drivers\SW\_PE_ProjectInfo.drv=726426382 + +[_end_] diff --git a/20080212/Demo/HCS12_CodeWarrior_small/RTOSDemo.dsk b/20080212/Demo/HCS12_CodeWarrior_small/RTOSDemo.dsk new file mode 100644 index 000000000..14b46d97a --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_small/RTOSDemo.dsk @@ -0,0 +1,166 @@ +[Version] +PE_DesktopFileVersion=819 + +[Desktop] +StartupPrj=E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_small\RTOSDemo.pe + +[PE_IDE_PlugIn] + +[CpuExpert] + +[AppPanel] +AllFocusedNode=Cpu:MC9S12C32CFU +ConfigurationsInAllExpanded=Yes +CPUsInAllExpanded=Yes +FPGAsInAllExpanded=No +OperatingSystemInAllExpanded=Yes +BeansInAllExpanded=Yes +TasksInAllExpanded=No +ProgramsInAllExpanded=No +DocumentationInAllExpanded=No +PESLInAllExpanded=No +PESL_moduleInAllExpanded=No +ViewEnabledItemsOnly=No + +[CpuPanel] +Status=hiden +WindowState=NORMAL +Rect=[-568|282|617|532] +CpuPanViewMode=Default + +[ErrorPanel] +Status=hiden +WindowState=NORMAL +Rect=[4|94|1608|1130] + +[ResourceMeter] +Status=hiden +WindowState=NORMAL +Rect=[49|1168|617|178] + +[BeanSelector] +Status=Visible +WindowState=NORMAL +Rect=[-4|62|1608|1130] +BF_ForTgtCpuOnly=Yes +BF_LicensedOnly=Yes + +[ObjInspector] +Status=Visible +WindowState=MAXIMAL +Rect=[-4|62|1199|1100] +ColWidth01=263 +ColWidth02=479 +ColWidth11=188 +ColWidth12=317 +ColWidth21=180 +ColWidth22=352 +ColWidth31=255 +ColWidth32=479 +ColWidth41=133 +ColWidth42=266 +ViewItemLevel=2 + +[PrphInspector] +Status=hiden +WindowState=NORMAL +Rect=[-466|400|516|411] +ViewMode=PrphUsageReport +SortRegsByAddr=Yes +GroupRegisters=No +Peripheral= + +[Editor] +Rect=[-4|0|1199|1100] +FontName=Courier New +FontSize=10 +FontBold=No +FontItalic=No +FontScript=1 +ToolBar=Yes +ToolBarPosition=top +SyntaxHighlighting=Yes +NoHorizScrollBar=Yes +ShowLineNumbers=No +PreserveCurPosDuringPaste=No +UseTabChar=No +ModulesInOneWindow=Yes +TabSize=8 +HintDelay=2 +OpenFilesCount=0 +SelFile= +SelLine=-1 +FileHistory=0 + +[CpuStructure] +Rect=[0|0|0|0] + +[StrListEditor] +WindowWidth=450 +WindowHeight=333 + +[Breakpoints] +WindowVisible=No +Rect=[0|0|0|0] +BreakLine1=0 +BreakModule1= + +[Watches] +Rect=[0|0|0|0] +WindowVisible=No +WatchCount=0 +WatchHistoryCount=0 + +[Registers] +Rect=[0|0|100|500] +WindowVisible=No + +[Dump] +WindowVisible=No +Rect=[0|0|0|0] +Address=0 +DataSize=1 +DataType=num +HistoryAddrCount=0 + +[InterruptVectors] +WindowVisible=No +Rect=[0|0|0|0] + +[MemoryMap] +Rect=[422|156|355|480] +DisplayOnlyMemories=No +WindowVisible=No + +[Browser] +Rect=[0|0|0|0] +WindowVisible=No + +[BeanManager] +Rect=[0|0|0|0] +BeanInfoFilter= +DriverFilter= +DriverInfoFilter= +BeanSettingsProjectFilter= + +[Options] +AutosaveWithProject=No +AutosaveBeforeTool=No +NumberOfBackupCopies=0 +AutoSaveDesktop=Yes +AutoOpenPropEdit=Yes +AutoConnectDevice=Yes +SelectTemplate=No +ShowGenProgress=Yes +AutoShowGeneratedSrc=No +AutoShowEventModules=No +ShowMethodCode=No +GenerateUndo=No +CpuBitmapFileName=Config\PE\CPUbckgr.bmp +CpuBitmapTilled=No +ShowProducerLogo=No +AutoStartApplicationCode=No +ShowSourceLinAfterDbgInit=No +RestoreFilesAfterDebug=No + +[_end_] diff --git a/20080212/Demo/HCS12_CodeWarrior_small/RTOSDemo.mcp b/20080212/Demo/HCS12_CodeWarrior_small/RTOSDemo.mcp new file mode 100644 index 0000000000000000000000000000000000000000..14c456857e6eca0fcafed9cb4e289112e3edfc50 GIT binary patch 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+List=GrupItem +[ItemState] +ItemSymbol=ScndTmr +ReadOnly=Yes +UserReadOnly=No +BasAdvHid=EXPERT +Value= +SharedPrphMode=No +[ItemState] +ItemSymbol=ScndIntr +ReadOnly=Yes +UserReadOnly=No +BasAdvHid=ADVANCED +Value= +SharedPrphMode=No + +[EndOfChilds] + +[EndOfChilds] + +[EndOfChilds] +[ItemState] +ItemSymbol=COP8grp +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=COP8TimerSpeedBase +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +TypeSpecNameState=typeCOP8_TimerPrescalerDefault +Index=0 + +[EndOfChilds] +[ItemState] +ItemSymbol=InitPrescaler +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=InternPrescaler +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC + +[Childs] +List=GrupItem + +[EndOfChilds] +Value=Auto selected prescaler +[ItemState] +ItemSymbol=InternCompare +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC + +[Childs] +List=GrupItem + +[EndOfChilds] +Value=Auto selected prescaler + +[EndOfChilds] +Value=Auto selected prescaler +[ItemState] +ItemSymbol=_Tmg +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=1000 Hz +RuntimeSetting=1 +InitValue=1000 Hz +Precision=5 +PrecInProc=Yes +LowLimit=100 Hz +HighLimit=1000 Hz +List=0 +UnitText=Hz +[ItemState] +ItemSymbol=SameValuesInAllModes +ReadOnly=No +UserReadOnly=No +BasAdvHid=EXPERT +Index=0 +Value=Yes +[ItemState] +ItemSymbol=EntireTimer +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Index=1 +Value=No +[ItemState] +ItemSymbol=_InitGrp +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=InitEnable +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +[ItemState] +ItemSymbol=InitEnableEvent +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Index=0 +Value=Yes + +[EndOfChilds] +[ItemState] +ItemSymbol=_SpeedGrp +ReadOnly=No +UserReadOnly=No +BasAdvHid=EXPERT + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=HighSpeed +ReadOnly=No +UserReadOnly=No +BasAdvHid=EXPERT +Index=0 +Value=Yes +[ItemState] +ItemSymbol=LowSpeed +ReadOnly=No +UserReadOnly=No +BasAdvHid=EXPERT +Index=0 +Value=Yes +[ItemState] +ItemSymbol=SlowSpeed +ReadOnly=No +UserReadOnly=No +BasAdvHid=EXPERT +Index=0 +Value=Yes + +[EndOfChilds] +[ItemState] +ItemSymbol=MirrorECTmoduleGrp +ReadOnly=No +UserReadOnly=No +BasAdvHid=EXPERT + +[Childs] +List=GrupItem + +[EndOfChilds] + +[Methods] +List=Method +[ItemState] +ItemSymbol=Enable +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=0 +Value=Yes +LastSelection=No +LastUserSel=yes +UsrMethodName=Enable +[ItemState] +ItemSymbol=Disable +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=Disable +[ItemState] +ItemSymbol=EnableEvent +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=EnableEvent +[ItemState] +ItemSymbol=DisableEvent +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=DisableEvent +[ItemState] +ItemSymbol=SetPeriodMode +ReadOnly=Yes +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=Yes +LastUserSel=never +UsrMethodName=SetPeriodMode +[ItemState] +ItemSymbol=SetPeriodTicks16 +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=Yes +LastUserSel=no +UsrMethodName=SetPeriodTicks16 +[ItemState] +ItemSymbol=SetPeriodTicks32 +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=Yes +LastUserSel=no +UsrMethodName=SetPeriodTicks32 +[ItemState] +ItemSymbol=SetPeriodUS +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=Yes +LastUserSel=no +UsrMethodName=SetPeriodUS +[ItemState] +ItemSymbol=SetPeriodMS +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=Yes +LastUserSel=no +UsrMethodName=SetPeriodMS +[ItemState] +ItemSymbol=SetPeriodSec +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=SetPeriodSec +[ItemState] +ItemSymbol=SetPeriodReal +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=SetPeriodReal +[ItemState] +ItemSymbol=SetFreqHz +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=0 +Value=Yes +LastSelection=No +LastUserSel=yes +UsrMethodName=SetFreqHz +[ItemState] +ItemSymbol=SetFreqkHz +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=SetFreqkHz +[ItemState] +ItemSymbol=SetFreqMHz +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=SetFreqMHz + +[Events] +List=Event +[ItemState] +ItemSymbol=EventModule +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Value=Events +[ItemState] +ItemSymbol=BeforeNewSpeed +ReadOnly=No +UserReadOnly=No +BasAdvHid=EXPERT +Value=No + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=Name +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=TickTimer_BeforeNewSpeed + +[EndOfChilds] +LastSelection=No +LastUserSel=no +[ItemState] +ItemSymbol=AfterNewSpeed +ReadOnly=No +UserReadOnly=No +BasAdvHid=EXPERT +Value=No + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=Name +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=TickTimer_AfterNewSpeed + +[EndOfChilds] +LastSelection=No +LastUserSel=no +[ItemState] +ItemSymbol=OnInterrupt +ReadOnly=Yes +UserReadOnly=No +BasAdvHid=BASIC +Value=Yes + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=Name +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=vTaskTickInterrupt +[ItemState] +ItemSymbol=Priority +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Value=same as interrupt + +[EndOfChilds] +LastSelection=No +LastUserSel=always + +[ExtInt:ButtonInterrupt] +CompNumb=26 +CompEnabled=Yes +GenCodeMode=CHECK_n_WRITE +IconName=EXTINT +Comment=0 +Template= + +[Properties] +List=Property +[ItemState] +ItemSymbol=DeviceName +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Value=ButtonInterrupt +[ItemState] +ItemSymbol=_Pin +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=PP0_PWM0_KWP0 +SharedPrphMode=No +[ItemState] +ItemSymbol=PinSignal +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Value= +[ItemState] +ItemSymbol=PullMode +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +TypeSpecNameState=typePULL +Index=1 +[ItemState] +ItemSymbol=InitEdge +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=2 +[ItemState] +ItemSymbol=HCS08grp +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=Invert +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No + +[EndOfChilds] +[ItemState] +ItemSymbol=Int +ReadOnly=Yes +UserReadOnly=No +BasAdvHid=ADVANCED +Value=INT_PortP +SharedPrphMode=No +[ItemState] +ItemSymbol=InitPriority +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=medium priority +[ItemState] +ItemSymbol=JBJGcond +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=PTE4Int +ReadOnly=Yes +UserReadOnly=No +BasAdvHid=BASIC +Value=No + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=SHpin +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value= +SharedPrphMode=No +[ItemState] +ItemSymbol=SHPinSignal +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Value= +[ItemState] +ItemSymbol=SHPullMode +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +TypeSpecNameState=typePULL +Index=5 + +[EndOfChilds] + +[EndOfChilds] +[ItemState] +ItemSymbol=_InitGrp +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=InitEnable +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No + +[EndOfChilds] + +[Methods] +List=Method +[ItemState] +ItemSymbol=Enable +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=0 +Value=Yes +LastSelection=No +LastUserSel=yes +UsrMethodName=Enable +[ItemState] +ItemSymbol=Disable +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=Disable +[ItemState] +ItemSymbol=GetVal +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=GetVal +[ItemState] +ItemSymbol=SetEdge +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=SetEdge +[ItemState] +ItemSymbol=56800grp +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=ConnectPin +ReadOnly=No +UserReadOnly=No +BasAdvHid=EXPERT +Index=1 +Value=No +LastSelection=No +LastUserSel=no +UsrMethodName=ConnectPin + +[EndOfChilds] + +[Events] +List=Event +[ItemState] +ItemSymbol=EventModule +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Value=Events +[ItemState] +ItemSymbol=OnInterrupt +ReadOnly=Yes +UserReadOnly=No +BasAdvHid=BASIC +Value=Yes + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=Name +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=ButtonInterrupt_OnInterrupt +[ItemState] +ItemSymbol=Priority +ReadOnly=No +UserReadOnly=No +BasAdvHid=ADVANCED +Value=same as interrupt + +[EndOfChilds] +LastSelection=No +LastUserSel=always +[ItemState] +ItemSymbol=CPUCondJBJG +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=OnTriggerInterrupt +ReadOnly=Yes +UserReadOnly=No +BasAdvHid=BASIC +Value=No + +[Childs] +List=GrupItem +[ItemState] +ItemSymbol=Name +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=ButtonInterrupt_OnTriggerInterrupt +[ItemState] +ItemSymbol=Priority +ReadOnly=No +UserReadOnly=No +BasAdvHid=BASIC +Value=interrupts disabled + +[EndOfChilds] +LastSelection=No +LastUserSel=never + +[EndOfChilds] + +[Program] +ProgType=event +ProgNumb=2 +List=Property +EventModule=Events + +[_end_] diff --git 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move a byte from ROM to the data area + __FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */ + DBNE D,Copy ; copy-byte loop +#else + LSRD ; /2 and save bit 0 in the carry +Copy: MOVW 2,X+,2,Y+ ; move a word from ROM to the data area + __FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */ + DBNE D,Copy ; copy-word loop + BCC NextBlock ; handle last byte? + MOVB 1,X+,1,Y+ ; copy the last byte +#endif + BRA NextBlock +funcInits: ; call of global construtors is only in c++ necessary +#if defined(__cplusplus) +#if defined(__ELF_OBJECT_FILE_FORMAT__) +#if defined( __BANKED__) || defined(__LARGE__) + LDY _startupData.nofInitBodies; load number of cpp. + BEQ done ; if cppcount == 0, goto done + LDX _startupData.initBodies ; load address of first module to initialize +nextInit: + LEAX 3,X ; increment to next init + PSHX ; save address of next function to initialize + PSHY ; save cpp counter + CALL [-3,X] ; use double indirect call to load the page register also + PULY ; restore cpp counter + PULX ; restore actual address + DEY ; decrement cpp counter + BNE nextInit +#else /* defined( __BANKED__) || defined(__LARGE__) */ + + LDD _startupData.nofInitBodies; load number of cpp. + BEQ done ; if cppcount == 0, goto done + LDX _startupData.initBodies ; load address of first module to initialize +nextInit: + LDY 2,X+ ; load address of first module to initialize + PSHD + PSHX ; save actual address + JSR 0,Y ; call initialization function + PULX ; restore actual address + PULD ; restore cpp counter + DBNE D, nextInit +#endif /* defined( __BANKED__) || defined(__LARGE__) */ +#else /* __ELF_OBJECT_FILE_FORMAT__ */ + LDX _startupData.mInits ; load address of first module to initialize +#if defined( __BANKED__) || defined(__LARGE__) +nextInit: LDY 3,X+ ; load address of initialization function + BEQ done ; stop when address == 0 + ; in common environments the offset of a function is never 0, so this test could be avoided +#ifdef __InitFunctionsMayHaveOffset0__ + BRCLR -1,X, done, 0xff ; stop when address == 0 +#endif /* __InitFunctionsMayHaveOffset0__ */ + PSHX ; save address of next function to initialize + CALL [-3,X] ; use double indirect call to load the page register also +#else /* defined( __BANKED__) || defined(__LARGE__) */ +nextInit: + LDY 2,X+ ; load address of first module to initialize + BEQ done ; stop when address of function == 0 + PSHX ; save actual address + JSR 0,Y ; call initialization function +#endif /* defined( __BANKED__) || defined(__LARGE__) */ + PULX ; restore actual address + BRA nextInit +#endif /* __ELF_OBJECT_FILE_FORMAT__ */ +done: +#endif /* __cplusplus */ + } +} + +#if defined( __ELF_OBJECT_FILE_FORMAT__) && defined(__cplusplus ) + +#if !defined(FAR_DATA) && (defined( __BANKED__) || defined(__LARGE__)) +static void __far Fini(void) +#else +static void Fini(void) +#endif +{ +/* purpose: 1) call global destructors in C++ */ + __asm { +#if defined( __BANKED__) || defined(__LARGE__) + + LDY _startupData.nofFiniBodies; load number of cpp. + BEQ done ; if cppcount == 0, goto done + LDX _startupData.finiBodies ; load address of first module to finalize +nextInit2: + LEAX 3,X ; increment to next init + PSHX ; save address of next function to finalize + PSHY ; save cpp counter + CALL [-3,X] ; use double indirect call to load the page register also + PULY ; restore cpp counter + PULX ; restore actual address + DEY ; decrement cpp counter + BNE nextInit2 +#else /* defined( __BANKED__) || defined(__LARGE__) */ + + LDD _startupData.nofFiniBodies; load number of cpp. + BEQ done ; if cppcount == 0, goto done + LDX _startupData.finiBodies ; load address of first module to finalize +nextInit2: + LDY 2,X+ ; load address of first module to finalize + PSHD + PSHX ; save actual address + JSR 0,Y ; call finalize function + PULX ; restore actual address + PULD ; restore cpp counter + DBNE D, nextInit2 +#endif /* defined( __BANKED__) || defined(__LARGE__) */ +done:; + } +} +#endif + + +#include "non_bank.sgm" + +#pragma MESSAGE DISABLE C12053 /* Stack-pointer change not in debugging-information */ +#pragma NO_FRAME +#pragma NO_ENTRY +#pragma NO_EXIT + +#ifdef __cplusplus + extern "C" +#endif + +/* The function _Startup must be called in order to initialize global variables and to call main */ +/* You can adapt this function or call it from your startup code to implement a different startup */ +/* functionality. */ + +/* You should also setup the needed IO registers as WINDEF (HC12A4 only) or the COP registers to run */ +/* on hardware */ + +/* to set the reset vector several ways are possible : */ +/* 1. define the function with "interrupt 0" as done below in the first case */ +/* 2. add the following line to your prm file : VECTOR ADDRESS 0xfffe _Startup */ +/* of course, even more posibilities exists */ +/* the reset vector must be set so that the application has a defined entry point */ + +#define STARTUP_FLAGS_NOT_INIT_SP (1<<1) + +#if defined(__SET_RESET_VECTOR__) +void __interrupt 0 _Startup(void) { +#else +void _Startup(void) { +#endif +/* purpose: 1) initialize the stack + 2) initialize the RAM, copy down init data etc (Init) + 3) call main; + parameters: NONE + called from: _PRESTART-code generated by the Linker + or directly referenced by the reset vector */ + for(;;) { /* forever: initialize the program; call the root-procedure */ + if (!(_startupData.flags&STARTUP_FLAGS_NOT_INIT_SP)) { + /* initialize the stack pointer */ + INIT_SP_FROM_STARTUP_DESC(); /*lint !e522 asm code */ /* HLI macro definition in hidef.h */ + } + +#ifdef _HCS12_SERIALMON + /* for Monitor based software remap the RAM & EEPROM to adhere + to EB386. Edit RAM and EEPROM sections in PRM file to match these. */ + ___INITRG = 0x00; /* lock registers block to 0x0000 */ + ___INITRM = 0x39; /* lock Ram to end at 0x3FFF */ + ___INITEE = 0x09; /* lock EEPROM block to end at 0x0fff */ +#endif + + /* Here user defined code could be inserted, the stack could be used */ +#if defined(_DO_DISABLE_COP_) + _DISABLE_COP(); +#endif + + /* Example : Set up WinDef Register to allow Paging */ +#ifdef HC812A4 /* HC12 A4 derivative needs WINDEF to configure which pages are available */ +#if (__ENABLE_EPAGE__ != 0 || __ENABLE_DPAGE__ != 0 || __ENABLE_PPAGE__ != 0) + WINDEF= __ENABLE_EPAGE__ | __ENABLE_DPAGE__ | __ENABLE_PPAGE__; +#endif +#endif + Init(); /* zero out, copy down, call constructors */ + /* Here user defined code could be inserted, all global variables are initilized */ +#if defined(_DO_ENABLE_COP_) + _ENABLE_COP(1); +#endif + + /* call main() */ + (*_startupData.main)(); + + /* call destructors. Only done when this file is compiled as C++ and for the ELF object file format */ + /* the HIWARE object file format does not support this */ +#if defined( __ELF_OBJECT_FILE_FORMAT__) && defined(__cplusplus ) + Fini(); +#endif + + } /* end loop forever */ +} diff --git a/20080212/Demo/HCS12_CodeWarrior_small/Sources/datapage.c b/20080212/Demo/HCS12_CodeWarrior_small/Sources/datapage.c new file mode 100644 index 000000000..80be5c566 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_small/Sources/datapage.c @@ -0,0 +1,843 @@ +/****************************************************************************** + FILE : datapage.c + PURPOSE : paged data access runtime routines + MACHINE : Motorola 68HC12 (Target) + LANGUAGE : ANSI-C + HISTORY : 21.7.96 first version created +******************************************************************************/ + +/* + According to the -Cp option of the compiler the + __DPAGE__, __PPAGE__ and __EPAGE__ macros are defined. + If none of them is given as argument, then no page accesses should occur and + this runtime routine should not be used ! + To be on the save side, the runtime routines are created anyway. + If some of the -Cp options are given an adapted versions which only covers the + needed cases is produced. +*/ + +/* if no compiler option -Cp is given, it is assumed that all possible are given : */ + +/* Compile with option -DHCS12 to activate this code */ +#if defined(HCS12) || defined(_HCS12) /* HCS12 family has PPAGE register only at 0x30 */ +#define PPAGE_ADDR (0x30+REGISTER_BASE) +#ifndef __PPAGE__ /* may be set already by option -CPPPAGE */ +#define __PPAGE__ +#endif +/* Compile with option -DDG128 to activate this code */ +#elif defined DG128 /* HC912DG128 derivative has PPAGE register only at 0xFF */ +#define PPAGE_ADDR (0xFF+REGISTER_BASE) +#ifndef __PPAGE__ /* may be set already by option -CPPPAGE */ +#define __PPAGE__ +#endif +#elif defined(HC812A4) +/* all setting default to A4 already */ +#endif + + +#if !defined(__EPAGE__) && !defined(__PPAGE__) && !defined(__DPAGE__) +/* as default use all page registers */ +#define __DPAGE__ +#define __EPAGE__ +#define __PPAGE__ +#endif + +/* modify the following defines to your memory configuration */ + +#define EPAGE_LOW_BOUND 0x400u +#define EPAGE_HIGH_BOUND 0x7ffu + +#define DPAGE_LOW_BOUND 0x7000u +#define DPAGE_HIGH_BOUND 0x7fffu + +#define PPAGE_LOW_BOUND (DPAGE_HIGH_BOUND+1) +#define PPAGE_HIGH_BOUND 0xBFFFu + +#define REGISTER_BASE 0x0u +#ifndef DPAGE_ADDR +#define DPAGE_ADDR (0x34u+REGISTER_BASE) +#endif +#ifndef EPAGE_ADDR +#define EPAGE_ADDR (0x36u+REGISTER_BASE) +#endif +#ifndef PPAGE_ADDR +#define PPAGE_ADDR (0x35u+REGISTER_BASE) +#endif + +/* + The following parts about the defines are assumed in the code of _GET_PAGE_REG : + - the memory region controlled by DPAGE is above the area controlled by the EPAGE and + below the area controlled by the PPAGE. + - the lower bound of the PPAGE area is equal to be the higher bound of the DPAGE area + 1 +*/ +#if EPAGE_LOW_BOUND >= EPAGE_HIGH_BOUND || EPAGE_HIGH_BOUND >= DPAGE_LOW_BOUND || DPAGE_LOW_BOUND >= DPAGE_HIGH_BOUND || DPAGE_HIGH_BOUND >= PPAGE_LOW_BOUND || PPAGE_LOW_BOUND >= PPAGE_HIGH_BOUND +#error /* please adapt _GET_PAGE_REG for this non default page configuration */ +#endif + +#if DPAGE_HIGH_BOUND+1 != PPAGE_LOW_BOUND +#error /* please adapt _GET_PAGE_REG for this non default page configuration */ +#endif + +#include "hidef.h" +#include "non_bank.sgm" +#include "runtime.sgm" + +/* this module does either control if any access is in the bounds of the specified page or */ +/* ,if only one page is specified, just use this page. */ +/* This behavior is controlled by the define USE_SEVERAL_PAGES. */ +/* If !USE_SEVERAL_PAGES does increase the performance significantly */ +/* NOTE : When !USE_SEVERAL_PAGES, the page is also set for accesses outside of the area controlled */ +/* by this single page. But this is usually no problem because the page is set again before any other access */ + +#if !defined(__DPAGE__) && !defined(__EPAGE__) && !defined(__PPAGE__) +/* no page at all is specified */ +/* only specifing the right pages will speed up these functions a lot */ +#define USE_SEVERAL_PAGES 1 +#elif defined(__DPAGE__) && defined(__EPAGE__) || defined(__DPAGE__) && defined(__PPAGE__) || defined(__EPAGE__) && defined(__PPAGE__) +/* more than one page register is used */ +#define USE_SEVERAL_PAGES 1 +#else + +#define USE_SEVERAL_PAGES 0 + +#if defined(__DPAGE__) /* check which pages are used */ +#define PAGE_ADDR PPAGE_ADDR +#elif defined(__EPAGE__) +#define PAGE_ADDR EPAGE_ADDR +#elif defined(__PPAGE__) +#define PAGE_ADDR PPAGE_ADDR +#else /* we dont know which page, decide it at runtime */ +#error /* must not happen */ +#endif + +#endif + + +#if USE_SEVERAL_PAGES /* only needed for several pages support */ +/*--------------------------- _GET_PAGE_REG -------------------------------- + Runtime routine to detect the right register depending on the 16 bit offset part + of an address. + This function is only used by the functions below. + + Depending on the compiler options -Cp different versions of _GET_PAGE_REG are produced. + + Arguments : + - Y : offset part of an address + + Result : + if address Y is controlled by a page register : + - X : address of page register if Y is controlled by an page register + - Zero flag cleared + - all other registers remain unchanged + + if address Y is not controlled by a page register : + - Zero flag is set + - all registers remain unchanged + + --------------------------- _GET_PAGE_REG ----------------------------------*/ + +#if defined(__DPAGE__) + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +static void NEAR _GET_PAGE_REG(void) { /*lint -esym(528, _GET_PAGE_REG) used in asm code */ + asm { +L_DPAGE: + CPY #DPAGE_LOW_BOUND ; test of lower bound of DPAGE +#if defined(__EPAGE__) + BLO L_EPAGE ; EPAGE accesses are possible +#else + BLO L_NOPAGE ; no paged memory below accesses +#endif + CPY #DPAGE_HIGH_BOUND ; test of higher bound DPAGE/lower bound PPAGE +#if defined(__PPAGE__) + BHI L_PPAGE ; EPAGE accesses are possible +#else + BHI L_NOPAGE ; no paged memory above accesses +#endif +FOUND_DPAGE: + LDX #DPAGE_ADDR ; load page register address and clear zero flag + RTS + +#if defined(__PPAGE__) +L_PPAGE: + CPY #PPAGE_HIGH_BOUND ; test of higher bound of PPAGE + BHI L_NOPAGE +FOUND_PPAGE: + LDX #PPAGE_ADDR ; load page register address and clear zero flag + RTS +#endif + +#if defined(__EPAGE__) +L_EPAGE: + CPY #EPAGE_LOW_BOUND ; test of lower bound of EPAGE + BLO L_NOPAGE + CPY #EPAGE_HIGH_BOUND ; test of higher bound of EPAGE + BHI L_NOPAGE + +FOUND_EPAGE: + LDX #EPAGE_ADDR ; load page register address and clear zero flag + RTS +#endif + +L_NOPAGE: + ORCC #0x04 ; sets zero flag + RTS + } +} + +#else /* !defined(__DPAGE__) */ + +#if defined( __PPAGE__ ) + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +static void NEAR _GET_PAGE_REG(void) { /*lint -esym(528, _GET_PAGE_REG) used in asm code */ + asm { +L_PPAGE: + CPY #PPAGE_LOW_BOUND ; test of lower bound of PPAGE +#if defined( __EPAGE__ ) + BLO L_EPAGE +#else + BLO L_NOPAGE ; no paged memory below +#endif + CPY #PPAGE_HIGH_BOUND ; test of higher bound PPAGE + BHI L_NOPAGE +FOUND_PPAGE: + LDX #PPAGE_ADDR ; load page register address and clear zero flag + RTS +#if defined( __EPAGE__ ) +L_EPAGE: + CPY #EPAGE_LOW_BOUND ; test of lower bound of EPAGE + BLO L_NOPAGE + CPY #EPAGE_HIGH_BOUND ; test of higher bound of EPAGE + BHI L_NOPAGE +FOUND_EPAGE: + LDX #EPAGE_ADDR ; load page register address and clear zero flag + RTS +#endif + +L_NOPAGE: ; not in any allowed page area + ; its a far access to a non paged variable + ORCC #0x04 ; sets zero flag + RTS + } +} + +#else /* !defined(__DPAGE__ ) && !defined( __PPAGE__) */ +#if defined(__EPAGE__) + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +static void NEAR _GET_PAGE_REG(void) { /*lint -esym(528, _GET_PAGE_REG) used in asm code */ + asm { +L_EPAGE: + CPY #EPAGE_LOW_BOUND ; test of lower bound of EPAGE + BLO L_NOPAGE + CPY #EPAGE_HIGH_BOUND ; test of higher bound of EPAGE + BHI L_NOPAGE +FOUND_EPAGE: + LDX #EPAGE_ADDR ; load page register address and clear zero flag + RTS + +L_NOPAGE: ; not in any allowed page area + ; its a far access to a non paged variable + ORCC #0x04 ; sets zero flag + RTS + } +} + +#endif /* defined(__EPAGE__) */ +#endif /* defined(__PPAGE__) */ +#endif /* defined(__DPAGE__) */ + +#endif /* USE_SEVERAL_PAGES */ + +/*--------------------------- _SET_PAGE -------------------------------- + Runtime routine to set the right page register. This routine is used if the compiler + does not know the right page register, i.e. if the option -Cp is used for more than + one pageregister or if the runtime option is used for one of the -Cp options. + + Arguments : + - offset part of an address in the Y register + - page part of an address in the B register + + Result : + - page part written into the correct page register. + - the old page register content is destroyed + - all processor registers remains unchanged + --------------------------- _SET_PAGE ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _SET_PAGE(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ; save X register + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + STAB 0,X ; set page register +L_NOPAGE: + PULX ; restore X register + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + STAB PAGE_ADDR ; set page register + RTS + } +#endif /* USE_SEVERAL_PAGES */ +} + +/*--------------------------- _LOAD_FAR_8 -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of an address in the Y register + - page part of an address in the B register + + Result : + - value to be read in the B register + - all other registers remains unchanged + - all page register still contain the same value + --------------------------- _LOAD_FAR_8 ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _LOAD_FAR_8(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ; save X register + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + PSHA ; save A register + LDAA 0,X ; save page register + STAB 0,X ; set page register + LDAB 0,Y ; actual load, overwrites page + STAA 0,X ; restore page register + PULA ; restore A register + PULX ; restore X register + RTS +L_NOPAGE: + LDAB 0,Y ; actual load, overwrites page + PULX ; restore X register + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + PSHA ; save A register + LDAA PAGE_ADDR ; save page register + STAB PAGE_ADDR ; set page register + LDAB 0,Y ; actual load, overwrites page + STAA PAGE_ADDR ; restore page register + PULA ; restore A register + RTS + } +#endif /* USE_SEVERAL_PAGES */ +} + +/*--------------------------- _LOAD_FAR_16 -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of an address in the Y register + - page part of an address in the B register + + Result : + - value to be read in the Y register + - all other registers remains unchanged + - all page register still contain the same value + --------------------------- _LOAD_FAR_16 ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _LOAD_FAR_16(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ; save X register + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + PSHA ; save A register + LDAA 0,X ; save page register + STAB 0,X ; set page register + LDY 0,Y ; actual load, overwrites address + STAA 0,X ; restore page register + PULA ; restore A register + PULX ; restore X register + RTS +L_NOPAGE: + LDY 0,Y ; actual load, overwrites address + PULX ; restore X register + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + PSHA ; save A register + LDAA PAGE_ADDR ; save page register + STAB PAGE_ADDR ; set page register + LDY 0,Y ; actual load, overwrites address + STAA PAGE_ADDR ; restore page register + PULA ; restore A register + RTS + } +#endif /* USE_SEVERAL_PAGES */ +} +/*--------------------------- _LOAD_FAR_24 -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of an address in the Y register + - page part of an address in the B register + + Result : + - value to be read in the Y:B registers + - all other registers remains unchanged + - all page register still contain the same value + --------------------------- _LOAD_FAR_24 ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _LOAD_FAR_24(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ; save X register + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + PSHA ; save A register + LDAA 0,X ; save page register + STAB 0,X ; set page register + LDAB 0,Y ; actual load, overwrites page of address + LDY 1,Y ; actual load, overwrites offset of address + STAA 0,X ; restore page register + PULA ; restore A register + PULX ; restore X register + RTS +L_NOPAGE: + LDAB 0,Y ; actual load, overwrites page of address + LDY 1,Y ; actual load, overwrites offset of address + PULX ; restore X register + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + PSHA ; save A register + LDAA PAGE_ADDR ; save page register + STAB PAGE_ADDR ; set page register + LDAB 0,Y ; actual load, overwrites page of address + LDY 1,Y ; actual load, overwrites offset of address + STAA PAGE_ADDR ; restore page register + PULA ; restore A register + RTS + } +#endif /* USE_SEVERAL_PAGES */ + +} + +/*--------------------------- _LOAD_FAR_32 -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of an address in the Y register + - page part of an address in the B register + + Result : + - low 16 bit of value to be read in the D registers + - high 16 bit of value to be read in the Y registers + - all other registers remains unchanged + - all page register still contain the same value + --------------------------- _LOAD_FAR_32 ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _LOAD_FAR_32(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ; save X register + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + LDAA 0,X ; save page register + PSHA ; put it onto the stack + STAB 0,X ; set page register + LDD 2,Y ; actual load, low word + LDY 0,Y ; actual load, high word + MOVB 1,SP+,0,X ; restore page register + PULX ; restore X register + RTS +L_NOPAGE: + LDD 2,Y ; actual load, low word + LDY 0,Y ; actual load, high word + PULX ; restore X register + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + LDAA PAGE_ADDR ; save page register + PSHA ; put it onto the stack + STAB PAGE_ADDR ; set page register + LDD 2,Y ; actual load, low word + LDY 0,Y ; actual load, high word + MOVB 1,SP+,PAGE_ADDR; restore page register + RTS + } +#endif /* USE_SEVERAL_PAGES */ +} + +/*--------------------------- _STORE_FAR_8 -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of an address in the Y register + - page part of an address in the B register + - value to be stored in the B register + + Result : + - value stored at the address + - all registers remains unchanged + - all page register still contain the same value + --------------------------- _STORE_FAR_8 ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _STORE_FAR_8(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ; save X register + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + PSHB ; save B register + LDAB 0,X ; save page register + MOVB 0,SP, 0,X ; set page register + STAA 0,Y ; store the value passed in A + STAB 0,X ; restore page register + PULB ; restore B register + PULX ; restore X register + RTS +L_NOPAGE: + STAA 0,Y ; store the value passed in A + PULX ; restore X register + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + PSHB ; save A register + LDAB PAGE_ADDR ; save page register + MOVB 0,SP,PAGE_ADDR ; set page register + STAA 0,Y ; store the value passed in A + STAB PAGE_ADDR ; restore page register + PULB ; restore B register + RTS + } +#endif /* USE_SEVERAL_PAGES */ +} + +/*--------------------------- _STORE_FAR_16 -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of an address in the Y register + - page part of an address in the B register + - value to be stored in the X register + + Result : + - value stored at the address + - all registers remains unchanged + - all page register still contain the same value + --------------------------- _STORE_FAR_16 ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _STORE_FAR_16(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ; save X register + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + + PSHA + LDAA 0,X ; save page register + STAB 0,X ; set page register + MOVW 1,SP, 0,Y ; store the value passed in X + STAA 0,X ; restore page register + PULA ; restore A register + PULX ; restore X register + RTS + +L_NOPAGE: + STX 0,Y ; store the value passed in X + PULX ; restore X register + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + PSHA ; save A register + LDAA PAGE_ADDR ; save page register + STAB PAGE_ADDR ; set page register + STX 0,Y ; store the value passed in X + STAA PAGE_ADDR ; restore page register + PULA ; restore A register + RTS + } +#endif /* USE_SEVERAL_PAGES */ +} +/*--------------------------- _STORE_FAR_24 -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of an address in the Y register + - page part of an address in the B register + - value to be stored in the X:A registers (X : low 16 bit, A : high 8 bit) + + Result : + - value stored at the address + - all registers remains unchanged + - all page register still contain the same value + --------------------------- _STORE_FAR_24 ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _STORE_FAR_24(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ; save X register + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + + PSHA + LDAA 0,X ; save page register + STAB 0,X ; set page register + MOVW 1,SP, 1,Y ; store the value passed in X + MOVB 0,SP, 0,Y ; store the value passed in A + STAA 0,X ; restore page register + PULA ; restore A register + PULX ; restore X register + RTS + +L_NOPAGE: + STX 1,Y ; store the value passed in X + STAA 0,Y ; store the value passed in X + PULX ; restore X register + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + PSHA ; save A register + LDAA PAGE_ADDR ; save page register + STAB PAGE_ADDR ; set page register + MOVB 0,SP, 0,Y ; store the value passed in A + STX 1,Y ; store the value passed in X + STAA PAGE_ADDR ; restore page register + PULA ; restore A register + RTS + } +#endif /* USE_SEVERAL_PAGES */ +} +/*--------------------------- _STORE_FAR_32 -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of an address in the Y register + - page part of an address is on the stack at 3,SP (just below the return address) + - value to be stored in the X:D registers (D : low 16 bit, X : high 16 bit) + + Result : + - value stored at the address + - all registers remains unchanged + - the page part is removed from the stack + - all page register still contain the same value + --------------------------- _STORE_FAR_32 ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _STORE_FAR_32(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ; save X register + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + + PSHD + LDAA 0,X ; save page register + MOVB 6,SP, 0,X ; set page register + MOVW 2,SP, 0,Y ; store the value passed in X (high word) + MOVW 0,SP, 2,Y ; store the value passed in D (low word) + STAA 0,X ; restore page register + PULD ; restore A register + BRA done + +L_NOPAGE: + MOVW 0,SP, 0,Y ; store the value passed in X (high word) + STD 2,Y ; store the value passed in D (low word) +done: + PULX ; restore X register + MOVW 0,SP, 1,+SP ; move return address + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + PSHD ; save D register + LDAA PAGE_ADDR ; save page register + LDAB 4,SP ; load page part of address + STAB PAGE_ADDR ; set page register + STX 0,Y ; store the value passed in X + MOVW 0,SP, 2,Y ; store the value passed in D (low word) + STAA PAGE_ADDR ; restore page register + PULD ; restore D register + MOVW 0,SP, 1,+SP ; move return address + RTS + } +#endif /* USE_SEVERAL_PAGES */ +} + +/*--------------------------- _FAR_COPY -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of the source int the X register + - page part of the source in the A register + - offset part of the dest int the Y register + - page part of the dest in the B register + - number of bytes to be copied at 2,SP. The number of bytes is always > 0 + + Result : + - memory area copied + - no registers are saved, i.e. all registers may be destroied + - all page register still contain the same value + + + stack-structure at the loop-label: + 0,SP : destination offset + 2,SP : source page + 3,SP : destination page + 4,SP : source offset + 6,SP : return address + 8,SP : counter, > 0 + --------------------------- _FAR_COPY ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _FAR_COPY(void) { +#if USE_SEVERAL_PAGES + asm { + DEX ; source addr-=1, because loop counter ends at 1 + PSHX ; save source offset + PSHD ; save both pages + DEY ; destination addr-=1, because loop counter ends at 1 + PSHY ; save destination offset + LDX 8,SP ; load counter, assuming counter > 0 + +loop: + LDD 4,SP ; load source offset + LEAY D,X ; calcutate actual source address + LDAB 2,SP ; load source page + __PIC_JSR (_LOAD_FAR_8); load 1 source byte + PSHB ; save value + LDD 0+1,SP ; load destination offset + LEAY D,X ; calcutate acual destination address + PULA ; restore value + LDAB 3,SP ; load destination page + __PIC_JSR (_STORE_FAR_8); store one byte + DEX + BNE loop + LDX 6,SP ; load return address + LEAS 10,SP ; release stack + JMP 0,X ; return + } +#else + asm { + PSHD ; store page registers + TFR X,D + ADDD 4,SP ; calculate source end address + STD 4,SP + PULB ; reload source page + LDAA PAGE_ADDR ; save page register + PSHA +loop: + STAB PAGE_ADDR ; set source page + LDAA 1,X+ ; load value + MOVB 1,SP, PAGE_ADDR ; set destination page + STAA 1,Y+ + CPX 4,SP + BNE loop + + LDAA 2,SP+ ; restore old page value and release stack + STAA PAGE_ADDR ; store it into page register + LDX 4,SP+ ; release stack and load return address + JMP 0,X ; return + } +#endif +} + diff --git a/20080212/Demo/HCS12_CodeWarrior_small/bin/Simulator.map b/20080212/Demo/HCS12_CodeWarrior_small/bin/Simulator.map new file mode 100644 index 000000000..64c54c7eb --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_small/bin/Simulator.map @@ -0,0 +1,2175 @@ + +PROGRAM "E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_small\bin\Simulator.abs" + +********************************************************************************************* +TARGET SECTION +--------------------------------------------------------------------------------------------- +Processor : Motorola HC12 +Memory Model: SMALL +File Format : ELF\Dwarf 2.0 +Linker : SmartLinker V-5.0.22 Build 4047, Feb 17 2004 + +********************************************************************************************* +FILE SECTION +--------------------------------------------------------------------------------------------- +Start12.c.o Model: SMALL, Lang: ANSI-C +STRING.C.o (ansisi.lib) Model: SMALL, Lang: ANSI-C +rtshc12.c.o (ansisi.lib) Model: SMALL, Lang: ANSI-C +Cpu.C.o Model: SMALL, Lang: ANSI-C +Byte1.C.o Model: SMALL, Lang: ANSI-C +IO_Map.C.o Model: SMALL, Lang: ANSI-C +Vectors.c.o Model: SMALL, Lang: ANSI-C +RTOSDemo.C.o Model: SMALL, Lang: ANSI-C +tasks.c.o Model: SMALL, Lang: ANSI-C +queue.c.o Model: SMALL, Lang: ANSI-C +list.c.o Model: SMALL, Lang: ANSI-C +port.c.o Model: SMALL, Lang: ANSI-C +flash.c.o Model: SMALL, Lang: ANSI-C +main.c.o Model: SMALL, Lang: ANSI-C +heap_1.c.o Model: SMALL, Lang: ANSI-C +TickTimer.C.o Model: SMALL, Lang: ANSI-C +PE_Timer.C.o Model: SMALL, Lang: ANSI-C +ParTest.c.o Model: SMALL, Lang: ANSI-C +PollQ.c.o Model: SMALL, Lang: ANSI-C +dynamic.c.o Model: SMALL, Lang: ANSI-C +ButtonInterrupt.C.o Model: SMALL, Lang: ANSI-C + +********************************************************************************************* +STARTUP SECTION +--------------------------------------------------------------------------------------------- +Entry point: 0xC000 (_EntryPoint) +_startupData is allocated at 0xC076 and uses 23 Bytes +extern struct _tagStartup { + unsigned flags 0 + _PFunc main 0xC1FD (main) + long stackOffset 0xFED + unsigned nofZeroOut 1 + _Range pZeroOut 0x800 1982 + _Copy *toCopyDownBeg 0xD3CF + int nofLibInits 0 + _LibInit *libInits 0xC091 + int nofInitBodies 0 + _Cpp *initBodies 0xC093 + int nofFiniBodies 0 + _Cpp *finiBodies 0xC093 +} _startupData; + +********************************************************************************************* +SECTION-ALLOCATION SECTION +Section Name Size Type From To Segment +--------------------------------------------------------------------------------------------- +.data 1 R/W 0x800 0x800 RAM +.init 118 R 0xC000 0xC075 ROM_C000 +.startData 29 R 0xC076 0xC092 ROM_C000 +.rodata1 78 R 0xC093 0xC0E0 ROM_C000 +NON_BANKED 114 R 0xC0E1 0xC152 ROM_C000 +.text 4164 R 0xC153 0xD196 ROM_C000 +.copy 19 R 0xD3CF 0xD3E1 ROM_C000 +.abs_section_3f 1 N/I 0x3F 0x3F .absSeg0 +.abs_section_8d 1 N/I 0x8D 0x8D .absSeg1 +.abs_section_86 1 N/I 0x86 0x86 .absSeg2 +.abs_section_8b 1 N/I 0x8B 0x8B .absSeg3 +.abs_section_ff06 1 N/I 0xFF06 0xFF06 .absSeg4 +.abs_section_ff07 1 N/I 0xFF07 0xFF07 .absSeg5 +.abs_section_ff01 1 N/I 0xFF01 0xFF01 .absSeg6 +.abs_section_2b 1 N/I 0x2B 0x2B .absSeg7 +.abs_section_2c 1 N/I 0x2C 0x2C .absSeg8 +.abs_section_2a 1 N/I 0x2A 0x2A .absSeg9 +.abs_section_2e 1 N/I 0x2E 0x2E .absSeg10 +.abs_section_2f 1 N/I 0x2F 0x2F .absSeg11 +.abs_section_2d 1 N/I 0x2D 0x2D .absSeg12 +.abs_section_28 1 N/I 0x28 0x28 .absSeg13 +.abs_section_29 1 N/I 0x29 0x29 .absSeg14 +.abs_section_142 1 N/I 0x142 0x142 .absSeg15 +.abs_section_143 1 N/I 0x143 0x143 .absSeg16 +.abs_section_140 1 N/I 0x140 0x140 .absSeg17 +.abs_section_141 1 N/I 0x141 0x141 .absSeg18 +.abs_section_14b 1 N/I 0x14B 0x14B .absSeg19 +.abs_section_150 1 N/I 0x150 0x150 .absSeg20 +.abs_section_151 1 N/I 0x151 0x151 .absSeg21 +.abs_section_152 1 N/I 0x152 0x152 .absSeg22 +.abs_section_153 1 N/I 0x153 0x153 .absSeg23 +.abs_section_158 1 N/I 0x158 0x158 .absSeg24 +.abs_section_159 1 N/I 0x159 0x159 .absSeg25 +.abs_section_15a 1 N/I 0x15A 0x15A .absSeg26 +.abs_section_15b 1 N/I 0x15B 0x15B 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0x161 0x161 .absSeg49 +.abs_section_162 1 N/I 0x162 0x162 .absSeg50 +.abs_section_163 1 N/I 0x163 0x163 .absSeg51 +.abs_section_149 1 N/I 0x149 0x149 .absSeg52 +.abs_section_148 1 N/I 0x148 0x148 .absSeg53 +.abs_section_14a 1 N/I 0x14A 0x14A .absSeg54 +.abs_section_146 1 N/I 0x146 0x146 .absSeg55 +.abs_section_147 1 N/I 0x147 0x147 .absSeg56 +.abs_section_17c 1 N/I 0x17C 0x17C .absSeg57 +.abs_section_174 1 N/I 0x174 0x174 .absSeg58 +.abs_section_175 1 N/I 0x175 0x175 .absSeg59 +.abs_section_176 1 N/I 0x176 0x176 .absSeg60 +.abs_section_177 1 N/I 0x177 0x177 .absSeg61 +.abs_section_178 1 N/I 0x178 0x178 .absSeg62 +.abs_section_179 1 N/I 0x179 0x179 .absSeg63 +.abs_section_17a 1 N/I 0x17A 0x17A .absSeg64 +.abs_section_17b 1 N/I 0x17B 0x17B .absSeg65 +.abs_section_14f 1 N/I 0x14F 0x14F .absSeg66 +.abs_section_170 1 N/I 0x170 0x170 .absSeg67 +.abs_section_171 1 N/I 0x171 0x171 .absSeg68 +.abs_section_172 1 N/I 0x172 0x172 .absSeg69 +.abs_section_173 1 N/I 0x173 0x173 .absSeg70 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.absSeg204 +.abs_section_ec 2 N/I 0xEC 0xED .absSeg205 +.abs_section_ee 2 N/I 0xEE 0xEF .absSeg206 +.abs_section_f0 2 N/I 0xF0 0xF1 .absSeg207 +.abs_section_f8 2 N/I 0xF8 0xF9 .absSeg208 +.abs_section_fa 2 N/I 0xFA 0xFB .absSeg209 +.abs_section_fc 2 N/I 0xFC 0xFD .absSeg210 +.abs_section_f2 2 N/I 0xF2 0xF3 .absSeg211 +.abs_section_f4 2 N/I 0xF4 0xF5 .absSeg212 +.abs_section_f6 2 N/I 0xF6 0xF7 .absSeg213 +.abs_section_c8 2 N/I 0xC8 0xC9 .absSeg214 +.abs_section_50 2 N/I 0x50 0x51 .absSeg215 +.abs_section_52 2 N/I 0x52 0x53 .absSeg216 +.abs_section_54 2 N/I 0x54 0x55 .absSeg217 +.abs_section_56 2 N/I 0x56 0x57 .absSeg218 +.abs_section_58 2 N/I 0x58 0x59 .absSeg219 +.abs_section_5a 2 N/I 0x5A 0x5B .absSeg220 +.abs_section_5c 2 N/I 0x5C 0x5D .absSeg221 +.abs_section_5e 2 N/I 0x5E 0x5F .absSeg222 +.abs_section_44 2 N/I 0x44 0x45 .absSeg223 +.abs_section_ff80 128 R 0xFF80 0xFFFF .absSeg224 +.bss 1968 R/W 0x801 0xFB0 RAM +RUNTIME 373 R 0xD197 0xD30B ROM_C000 +.common 2 R/W 0xFB1 0xFB2 RAM +Byte1_CODE 28 R 0xD30C 0xD327 ROM_C000 +TickTimer_CODE 157 R 0xD328 0xD3C4 ROM_C000 +ButtonInterrupt_CODE 10 R 0xD3C5 0xD3CE ROM_C000 +Byte1_DATA 8 R/W 0xFB3 0xFBA RAM +TickTimer_DATA 3 R/W 0xFBB 0xFBD RAM +.stack 48 R/W 0xFBE 0xFED RAM + +Summary of section sizes per section type: +READ_ONLY (R): 1462 (dec: 5218) +READ_WRITE (R/W): 7EE (dec: 2030) +NO_INIT (N/I): 100 (dec: 256) + +********************************************************************************************* +VECTOR-ALLOCATION SECTION + Address InitValue InitFunction +--------------------------------------------------------------------------------------------- + +********************************************************************************************* +OBJECT-ALLOCATION SECTION + Name Module Addr hSize dSize Ref Section RLIB +--------------------------------------------------------------------------------------------- +MODULE: -- Start12.c.o -- +- PROCEDURES: + Init C153 29 41 1 .text + _Startup C17C 10 16 1 .text +- VARIABLES: + _startupData C076 17 23 6 .startData +MODULE: -- STRING.C.o (ansisi.lib) -- +- PROCEDURES: + memcpy C18C 26 38 3 .text + memset C1B2 1E 30 1 .text + strncpy C1D0 2D 45 1 .text +- VARIABLES: +MODULE: -- rtshc12.c.o (ansisi.lib) -- +- PROCEDURES: + _LCMP D197 19 25 2 RUNTIME + _LCMP_P D1B0 15 21 2 RUNTIME + _LNEG D1C5 D 13 1 RUNTIME + _LINC D1D2 5 5 4 RUNTIME + _lDivMod D1D7 E3 227 3 RUNTIME + _LDIVU D2BA E 14 1 RUNTIME + _NEG_P D2C8 F 15 4 RUNTIME + _LDIVS D2D7 35 53 1 RUNTIME +- VARIABLES: +MODULE: -- Cpu.C.o -- +- PROCEDURES: + _EntryPoint C000 2E 46 1 .init + PE_low_level_init C02E 48 72 1 .init + Cpu_Interrupt C0E1 1 1 60 NON_BANKED +- VARIABLES: +MODULE: -- Byte1.C.o -- +- PROCEDURES: + Byte1_GetMsk D30C D 13 1 Byte1_CODE + Byte1_NegBit D319 F 15 1 Byte1_CODE +- VARIABLES: + Byte1_Table FB3 8 8 1 Byte1_DATA +MODULE: -- IO_Map.C.o -- +- PROCEDURES: +- VARIABLES: + _ARMCOP 3F 1 1 0 .abs_section_3f + _ATDDIEN 8D 1 1 0 .abs_section_8d + _ATDSTAT0 86 1 1 0 .abs_section_86 + _ATDSTAT1 8B 1 1 0 .abs_section_8b + _BDMCCR FF06 1 1 0 .abs_section_ff06 + _BDMINR FF07 1 1 0 .abs_section_ff07 + _BDMSTS FF01 1 1 0 .abs_section_ff01 + _BKP0H 2B 1 1 0 .abs_section_2b + _BKP0L 2C 1 1 0 .abs_section_2c + _BKP0X 2A 1 1 0 .abs_section_2a + _BKP1H 2E 1 1 0 .abs_section_2e + _BKP1L 2F 1 1 0 .abs_section_2f + _BKP1X 2D 1 1 0 .abs_section_2d + _BKPCT0 28 1 1 0 .abs_section_28 + _BKPCT1 29 1 1 0 .abs_section_29 + _CANBTR0 142 1 1 0 .abs_section_142 + _CANBTR1 143 1 1 0 .abs_section_143 + _CANCTL0 140 1 1 0 .abs_section_140 + _CANCTL1 141 1 1 0 .abs_section_141 + _CANIDAC 14B 1 1 0 .abs_section_14b + _CANIDAR0 150 1 1 0 .abs_section_150 + _CANIDAR1 151 1 1 0 .abs_section_151 + _CANIDAR2 152 1 1 0 .abs_section_152 + _CANIDAR3 153 1 1 0 .abs_section_153 + _CANIDAR4 158 1 1 0 .abs_section_158 + _CANIDAR5 159 1 1 0 .abs_section_159 + _CANIDAR6 15A 1 1 0 .abs_section_15a + _CANIDAR7 15B 1 1 0 .abs_section_15b + _CANIDMR0 154 1 1 0 .abs_section_154 + _CANIDMR1 155 1 1 0 .abs_section_155 + _CANIDMR2 156 1 1 0 .abs_section_156 + _CANIDMR3 157 1 1 0 .abs_section_157 + _CANIDMR4 15C 1 1 0 .abs_section_15c + _CANIDMR5 15D 1 1 0 .abs_section_15d + _CANIDMR6 15E 1 1 0 .abs_section_15e + _CANIDMR7 15F 1 1 0 .abs_section_15f + _CANRFLG 144 1 1 0 .abs_section_144 + _CANRIER 145 1 1 0 .abs_section_145 + _CANRXDLR 16C 1 1 0 .abs_section_16c + _CANRXDSR0 164 1 1 0 .abs_section_164 + _CANRXDSR1 165 1 1 0 .abs_section_165 + _CANRXDSR2 166 1 1 0 .abs_section_166 + _CANRXDSR3 167 1 1 0 .abs_section_167 + _CANRXDSR4 168 1 1 0 .abs_section_168 + _CANRXDSR5 169 1 1 0 .abs_section_169 + _CANRXDSR6 16A 1 1 0 .abs_section_16a + _CANRXDSR7 16B 1 1 0 .abs_section_16b + _CANRXERR 14E 1 1 0 .abs_section_14e + _CANRXIDR0 160 1 1 0 .abs_section_160 + _CANRXIDR1 161 1 1 0 .abs_section_161 + _CANRXIDR2 162 1 1 0 .abs_section_162 + _CANRXIDR3 163 1 1 0 .abs_section_163 + _CANTAAK 149 1 1 0 .abs_section_149 + _CANTARQ 148 1 1 0 .abs_section_148 + _CANTBSEL 14A 1 1 0 .abs_section_14a + _CANTFLG 146 1 1 0 .abs_section_146 + _CANTIER 147 1 1 0 .abs_section_147 + _CANTXDLR 17C 1 1 0 .abs_section_17c + _CANTXDSR0 174 1 1 0 .abs_section_174 + _CANTXDSR1 175 1 1 0 .abs_section_175 + _CANTXDSR2 176 1 1 0 .abs_section_176 + _CANTXDSR3 177 1 1 0 .abs_section_177 + _CANTXDSR4 178 1 1 0 .abs_section_178 + _CANTXDSR5 179 1 1 0 .abs_section_179 + _CANTXDSR6 17A 1 1 0 .abs_section_17a + _CANTXDSR7 17B 1 1 0 .abs_section_17b + _CANTXERR 14F 1 1 0 .abs_section_14f + _CANTXIDR0 170 1 1 0 .abs_section_170 + _CANTXIDR1 171 1 1 0 .abs_section_171 + _CANTXIDR2 172 1 1 0 .abs_section_172 + _CANTXIDR3 173 1 1 0 .abs_section_173 + _CANTXTBPR 17F 1 1 0 .abs_section_17f + _CFORC 41 1 1 0 .abs_section_41 + _CLKSEL 39 1 1 3 .abs_section_39 + _COPCTL 3C 1 1 0 .abs_section_3c + _CRGFLG 37 1 1 1 .abs_section_37 + _CRGINT 38 1 1 0 .abs_section_38 + _CTCTL 3E 1 1 0 .abs_section_3e + _CTFLG 36 1 1 0 .abs_section_36 + _DDRAD 272 1 1 0 .abs_section_272 + _DDRE 9 1 1 0 .abs_section_9 + _DDRJ 26A 1 1 0 .abs_section_26a + _DDRK 33 1 1 0 .abs_section_33 + _DDRM 252 1 1 0 .abs_section_252 + _DDRP 25A 1 1 1 .abs_section_25a + _DDRS 24A 1 1 0 .abs_section_24a + _DDRT 242 1 1 0 .abs_section_242 + _EBICTL E 1 1 0 .abs_section_e + _FCLKDIV 100 1 1 0 .abs_section_100 + _FCMD 106 1 1 0 .abs_section_106 + _FCNFG 103 1 1 0 .abs_section_103 + _FPROT 104 1 1 0 .abs_section_104 + _FSEC 101 1 1 0 .abs_section_101 + _FSTAT 105 1 1 0 .abs_section_105 + _HPRIO 1F 1 1 0 .abs_section_1f + _INITEE 12 1 1 0 .abs_section_12 + _INITRG 11 1 1 0 .abs_section_11 + _INITRM 10 1 1 1 .abs_section_10 + _INTCR 1E 1 1 1 .abs_section_1e + _ITCR 15 1 1 0 .abs_section_15 + _ITEST 16 1 1 0 .abs_section_16 + _MEMSIZ0 1C 1 1 0 .abs_section_1c + _MEMSIZ1 1D 1 1 0 .abs_section_1d + _MISC 13 1 1 1 .abs_section_13 + _MODE B 1 1 0 .abs_section_b + _MODRR 247 1 1 0 .abs_section_247 + _MTST0 14 1 1 0 .abs_section_14 + _MTST1 17 1 1 0 .abs_section_17 + _OC7D 43 1 1 0 .abs_section_43 + _OC7M 42 1 1 0 .abs_section_42 + _PACTL 60 1 1 0 .abs_section_60 + _PAFLG 61 1 1 0 .abs_section_61 + _PARTIDH 1A 1 1 0 .abs_section_1a + _PARTIDL 1B 1 1 0 .abs_section_1b + _PEAR A 1 1 0 .abs_section_a + _PERAD 274 1 1 0 .abs_section_274 + _PERJ 26C 1 1 0 .abs_section_26c + _PERM 254 1 1 0 .abs_section_254 + _PERP 25C 1 1 1 .abs_section_25c + _PERS 24C 1 1 0 .abs_section_24c + _PERT 244 1 1 0 .abs_section_244 + _PIEJ 26E 1 1 0 .abs_section_26e + _PIEP 25E 1 1 2 .abs_section_25e + _PIFJ 26F 1 1 0 .abs_section_26f + _PIFP 25F 1 1 2 .abs_section_25f + _PLLCTL 3A 1 1 3 .abs_section_3a + _PORTAD0 8F 1 1 0 .abs_section_8f + _PORTE 8 1 1 0 .abs_section_8 + _PORTK 32 1 1 0 .abs_section_32 + _PPAGE 30 1 1 0 .abs_section_30 + _PPSAD 275 1 1 0 .abs_section_275 + _PPSJ 26D 1 1 0 .abs_section_26d + _PPSM 255 1 1 0 .abs_section_255 + _PPSP 25D 1 1 1 .abs_section_25d + _PPSS 24D 1 1 0 .abs_section_24d + _PPST 245 1 1 0 .abs_section_245 + _PTAD 270 1 1 0 .abs_section_270 + _PTIAD 271 1 1 0 .abs_section_271 + _PTIJ 269 1 1 0 .abs_section_269 + _PTIM 251 1 1 0 .abs_section_251 + _PTIP 259 1 1 0 .abs_section_259 + _PTIS 249 1 1 0 .abs_section_249 + _PTIT 241 1 1 0 .abs_section_241 + _PTJ 268 1 1 0 .abs_section_268 + _PTM 250 1 1 0 .abs_section_250 + _PTP 258 1 1 0 .abs_section_258 + _PTS 248 1 1 0 .abs_section_248 + _PTT 240 1 1 0 .abs_section_240 + _PUCR C 1 1 0 .abs_section_c + _PWMCAE E4 1 1 0 .abs_section_e4 + _PWMCLK E2 1 1 0 .abs_section_e2 + _PWMCTL E5 1 1 1 .abs_section_e5 + _PWME E0 1 1 0 .abs_section_e0 + _PWMPOL E1 1 1 0 .abs_section_e1 + _PWMPRCLK E3 1 1 0 .abs_section_e3 + _PWMSCLA E8 1 1 0 .abs_section_e8 + _PWMSCLB E9 1 1 0 .abs_section_e9 + _PWMSDN FE 1 1 1 .abs_section_fe + _RDRAD 273 1 1 0 .abs_section_273 + _RDRIV D 1 1 0 .abs_section_d + _RDRJ 26B 1 1 0 .abs_section_26b + _RDRM 253 1 1 0 .abs_section_253 + _RDRP 25B 1 1 0 .abs_section_25b + _RDRS 24B 1 1 0 .abs_section_24b + _RDRT 243 1 1 0 .abs_section_243 + _REFDV 35 1 1 1 .abs_section_35 + _RTICTL 3B 1 1 0 .abs_section_3b + _SCICR1 CA 1 1 0 .abs_section_ca + _SCICR2 CB 1 1 0 .abs_section_cb + _SCIDRH CE 1 1 0 .abs_section_ce + _SCIDRL CF 1 1 0 .abs_section_cf + _SCISR1 CC 1 1 0 .abs_section_cc + _SCISR2 CD 1 1 0 .abs_section_cd + _SPIBR DA 1 1 0 .abs_section_da + _SPICR1 D8 1 1 0 .abs_section_d8 + _SPICR2 D9 1 1 0 .abs_section_d9 + _SPIDR DD 1 1 0 .abs_section_dd + _SPISR DB 1 1 0 .abs_section_db + _SYNR 34 1 1 1 .abs_section_34 + _TCTL1 48 1 1 1 .abs_section_48 + _TCTL2 49 1 1 1 .abs_section_49 + _TCTL3 4A 1 1 0 .abs_section_4a + _TCTL4 4B 1 1 0 .abs_section_4b + _TFLG1 4E 1 1 2 .abs_section_4e + _TFLG2 4F 1 1 0 .abs_section_4f + _TIE 4C 1 1 3 .abs_section_4c + _TIOS 40 1 1 1 .abs_section_40 + _TSCR1 46 1 1 3 .abs_section_46 + _TSCR2 4D 1 1 5 .abs_section_4d + _TTOV 47 1 1 1 .abs_section_47 + _WOMM 256 1 1 0 .abs_section_256 + _WOMS 24E 1 1 0 .abs_section_24e + _ATDCTL23 82 2 2 0 .abs_section_82 + _ATDCTL45 84 2 2 0 .abs_section_84 + _ATDDR0 90 2 2 0 .abs_section_90 + _ATDDR1 92 2 2 0 .abs_section_92 + _ATDDR2 94 2 2 0 .abs_section_94 + _ATDDR3 96 2 2 0 .abs_section_96 + _ATDDR4 98 2 2 0 .abs_section_98 + _ATDDR5 9A 2 2 0 .abs_section_9a + _ATDDR6 9C 2 2 0 .abs_section_9c + _ATDDR7 9E 2 2 0 .abs_section_9e + _DDRAB 2 2 2 1 .abs_section_2 + _PACNT 62 2 2 0 .abs_section_62 + _PORTAB 0 2 2 3 .abs_section_0 + _PWMCNT01 EC 2 2 0 .abs_section_ec + _PWMCNT23 EE 2 2 0 .abs_section_ee + _PWMCNT45 F0 2 2 0 .abs_section_f0 + _PWMDTY01 F8 2 2 0 .abs_section_f8 + _PWMDTY23 FA 2 2 0 .abs_section_fa + _PWMDTY45 FC 2 2 0 .abs_section_fc + _PWMPER01 F2 2 2 0 .abs_section_f2 + _PWMPER23 F4 2 2 0 .abs_section_f4 + _PWMPER45 F6 2 2 0 .abs_section_f6 + _SCIBD C8 2 2 0 .abs_section_c8 + _TC0 50 2 2 1 .abs_section_50 + _TC1 52 2 2 0 .abs_section_52 + _TC2 54 2 2 0 .abs_section_54 + _TC3 56 2 2 0 .abs_section_56 + _TC4 58 2 2 0 .abs_section_58 + _TC5 5A 2 2 0 .abs_section_5a + _TC6 5C 2 2 0 .abs_section_5c + _TC7 5E 2 2 1 .abs_section_5e + _TCNT 44 2 2 0 .abs_section_44 +MODULE: -- Vectors.c.o -- +- PROCEDURES: +- VARIABLES: + _vect FF80 80 128 0 .abs_section_ff80 +MODULE: -- RTOSDemo.C.o -- +- PROCEDURES: + main C1FD 8 8 0 .text +- VARIABLES: +MODULE: -- tasks.c.o -- +- PROCEDURES: + xTaskCreate C205 CE 206 11 .text + vTaskDelayUntil C2D3 74 116 3 .text + vTaskDelay C347 46 70 4 .text + uxTaskPriorityGet C38D 26 38 1 .text + vTaskPrioritySet C3B3 69 105 2 .text + vTaskSuspend C41C 44 68 3 .text + vTaskResume C460 59 89 3 .text + vTaskStartScheduler C4B9 30 48 1 .text + vTaskSuspendAll C4E9 13 19 11 .text + xTaskResumeAll C4FC 9F 159 13 .text + xTaskGetTickCount C59B 17 23 2 .text + vTaskIncrementTick C5B2 81 129 2 .text + vTaskSwitchContext C633 5B 91 3 .text + vTaskPlaceOnEventList C68E 41 65 2 .text + xTaskRemoveFromEventList C6CF 6C 108 3 .text + prvIdleTask C73B 10 16 1 .text + prvInitialiseTCBVariables C74B 4C 76 1 .text + prvInitialiseTaskLists C797 3C 60 1 .text + prvCheckTasksWaitingTermination C7D3 1 1 1 .text + prvAllocateTCBAndStack C7D4 33 51 1 .text +- VARIABLES: + STRING.IDLE.2 C093 5 5 1 .rodata1 + pxCurrentTCB 801 2 2 29 .bss + uxCurrentNumberOfTasks 803 1 1 3 .bss + xTickCount 804 2 2 14 .bss + uxTopUsedPriority 806 1 1 2 .bss + uxTopReadyPriority 807 1 1 15 .bss + xSchedulerRunning 808 1 1 3 .bss + uxSchedulerSuspended 809 1 1 6 .bss + uxMissedTicks 80A 1 1 4 .bss + uxTaskNumber.1 80B 1 1 2 .bss + pxReadyTasksLists 80C 3C 60 11 .bss + xDelayedTaskList1 848 F 15 2 .bss + xDelayedTaskList2 857 F 15 2 .bss + pxDelayedTaskList 866 2 2 8 .bss + pxOverflowDelayedTaskList 868 2 2 6 .bss + xPendingReadyList 86A F 15 4 .bss + xSuspendedTaskList 879 F 15 2 .bss +MODULE: -- queue.c.o -- +- PROCEDURES: + xQueueCreate C807 77 119 3 .text + xQueueSend C87E CA 202 3 .text + xQueueSendFromISR C948 54 84 1 .text + xQueueReceive C99C C4 196 4 .text + uxQueueMessagesWaiting CA60 1B 27 1 .text + prvUnlockQueue CA7B 6F 111 4 .text + prvIsQueueEmpty CAEA 21 33 1 .text + prvIsQueueFull CB0B 24 36 1 .text +- VARIABLES: +MODULE: -- list.c.o -- +- PROCEDURES: + vListInitialise CB2F 1F 31 7 .text + vListInitialiseItem CB4E 7 7 3 .text + vListInsertEnd CB55 27 39 7 .text + vListInsert CB7C 5A 90 4 .text + vListRemove CBD6 23 35 13 .text +- VARIABLES: +MODULE: -- port.c.o -- +- PROCEDURES: + pxPortInitialiseStack CBF9 2B 43 1 .text + prvSetupTimerInterrupt CC24 9 9 1 .text + xPortStartScheduler CC2D 4 4 1 .text + xBankedStartScheduler C0E2 F 15 1 NON_BANKED + vPortYield C0F1 16 22 1 NON_BANKED + vPortTickInterrupt C107 1D 29 1 NON_BANKED +- VARIABLES: + uxCriticalNesting 800 1 1 91 .data +MODULE: -- flash.c.o -- +- PROCEDURES: + vStartLEDFlashTasks CC31 26 38 1 .text + vLEDFlashTask CC57 52 82 1 .text +- VARIABLES: + STRING.LEDx.1 C098 5 5 1 .rodata1 + uxFlashTaskNumber 888 1 1 2 .bss +MODULE: -- main.c.o -- +- PROCEDURES: + vMain CCA9 42 66 1 .text + vErrorChecks CCEB 2F 47 1 .text + prvCheckOtherTasksAreStillRunning CD1A 23 35 1 .text + vApplicationIdleHook CD3D 73 115 1 .text + vButtonTask CDB0 4F 79 1 .text + vButtonPush C124 2F 47 1 NON_BANKED +- VARIABLES: + STRING.Check.1 C09D 6 6 1 .rodata1 + STRING.Button.2 C0A3 7 7 1 .rodata1 + xLocalError 889 1 1 3 .bss + uxValToSend.3 88A 1 1 2 .bss + xButtonQueue 88B 2 2 3 .bss +MODULE: -- heap_1.c.o -- +- PROCEDURES: + pvPortMalloc CDFF 30 48 4 .text + vPortFree CE2F 1 1 2 .text +- VARIABLES: + xNextFreeByte 88D 2 2 5 .bss + xHeap 88F 704 1796 1 .bss +MODULE: -- TickTimer.C.o -- +- PROCEDURES: + SetCV D328 F 15 2 TickTimer_CODE + SetPV D337 C 12 1 TickTimer_CODE + HWEnDi D343 11 17 2 TickTimer_CODE + TickTimer_Enable D354 E 14 1 TickTimer_CODE + TickTimer_SetFreqHz D362 4F 79 1 TickTimer_CODE + TickTimer_Init D3B1 14 20 1 TickTimer_CODE +- VARIABLES: + EnUser FBB 1 1 4 TickTimer_DATA + CmpHighVal FBC 2 2 2 TickTimer_DATA +MODULE: -- PE_Timer.C.o -- +- PROCEDURES: + PE_Timer_LngHi1 CE30 43 67 1 .text +- VARIABLES: +MODULE: -- ParTest.c.o -- +- PROCEDURES: + vParTestToggleLED CE73 13 19 4 .text +- VARIABLES: +MODULE: -- PollQ.c.o -- +- PROCEDURES: + vStartPolledQueueTasks CE86 40 64 1 .text + vPolledQueueProducer CEC6 4D 77 1 .text + vPolledQueueConsumer CF13 59 89 1 .text + xArePollingQueuesStillRunning CF6C 1D 29 1 .text +- VARIABLES: + STRING.QConsNB.2 C0AA 8 8 1 .rodata1 + STRING.QProdNB.3 C0B2 8 8 1 .rodata1 + xPollingConsumerCount F93 1 1 3 .bss + xPollingProducerCount F94 1 1 3 .bss + xPolledQueue.1 F95 2 2 3 .bss +MODULE: -- dynamic.c.o -- +- PROCEDURES: + vStartDynamicPriorityTasks CF89 7C 124 1 .text + vLimitedIncrementTask D005 21 33 1 .text + vContinuousIncrementTask D026 30 48 1 .text + vCounterControlTask D056 98 152 3 .text + vQueueSendWhenSuspendedTask D0EE 34 52 1 .text + vQueueReceiveWhenSuspendedTask D122 4E 78 1 .text + xAreDynamicPriorityTasksStillRunning D170 27 39 1 .text +- VARIABLES: + STRING.CNT_INC.1 C0BA 8 8 1 .rodata1 + STRING.LIM_INC.2 C0C2 8 8 1 .rodata1 + STRING.C_CTRL.3 C0CA 7 7 1 .rodata1 + STRING.SUSP_TX.4 C0D1 8 8 1 .rodata1 + STRING.SUSP_RX.5 C0D9 8 8 1 .rodata1 + usCheckVariable F97 2 2 4 .bss + xSuspendedQueueSendError F99 1 1 2 .bss + xSuspendedQueueReceiveError F9A 1 1 3 .bss + ulValueToSend.6 F9B 4 4 5 .bss + ulExpectedValue.7 F9F 4 4 6 .bss + usLastTaskCheck.9 FA3 2 2 2 .bss + xContinousIncrementHandle FA5 2 2 5 .bss + xLimitedIncrementHandle FA7 2 2 2 .bss + ulCounter FA9 4 4 10 .bss + ulReceivedValue.8 FAD 4 4 3 .bss + xSuspendedTestQueue FB1 2 2 3 .common +MODULE: -- ButtonInterrupt.C.o -- +- PROCEDURES: + ButtonInterrupt_Enable D3C5 A 10 1 ButtonInterrupt_CODE +- VARIABLES: + +********************************************************************************************* +MODULE STATISTIC + Name Data Code Const +--------------------------------------------------------------------------------------------- + Start12.c.o 0 57 0 + STRING.C.o (ansisi.lib) 0 113 0 + rtshc12.c.o (ansisi.lib) 0 373 0 + Cpu.C.o 0 119 0 + Byte1.C.o 8 28 0 + IO_Map.C.o 256 0 0 + Vectors.c.o 0 0 128 + RTOSDemo.C.o 0 8 0 + tasks.c.o 135 1538 5 + queue.c.o 0 808 0 + list.c.o 0 202 0 + port.c.o 1 122 0 + flash.c.o 1 120 5 + main.c.o 4 389 13 + heap_1.c.o 1798 49 0 + TickTimer.C.o 3 157 0 + PE_Timer.C.o 0 67 0 + ParTest.c.o 0 19 0 + PollQ.c.o 4 259 16 + dynamic.c.o 28 526 39 + ButtonInterrupt.C.o 0 10 0 + other 48 29 19 + +********************************************************************************************* +SECTION USE IN OBJECT-ALLOCATION SECTION +--------------------------------------------------------------------------------------------- +SECTION: ".text" + Init _Startup memcpy memset strncpy main xTaskCreate vTaskDelayUntil + vTaskDelay uxTaskPriorityGet vTaskPrioritySet vTaskSuspend vTaskResume + vTaskStartScheduler vTaskSuspendAll xTaskResumeAll xTaskGetTickCount + vTaskIncrementTick vTaskSwitchContext vTaskPlaceOnEventList + xTaskRemoveFromEventList prvIdleTask prvInitialiseTCBVariables + prvInitialiseTaskLists prvCheckTasksWaitingTermination prvAllocateTCBAndStack + xQueueCreate xQueueSend xQueueSendFromISR xQueueReceive + uxQueueMessagesWaiting prvUnlockQueue prvIsQueueEmpty prvIsQueueFull + vListInitialise vListInitialiseItem vListInsertEnd vListInsert vListRemove + pxPortInitialiseStack prvSetupTimerInterrupt xPortStartScheduler + vStartLEDFlashTasks vLEDFlashTask vMain vErrorChecks + prvCheckOtherTasksAreStillRunning vApplicationIdleHook vButtonTask + pvPortMalloc vPortFree PE_Timer_LngHi1 vParTestToggleLED + vStartPolledQueueTasks vPolledQueueProducer vPolledQueueConsumer + xArePollingQueuesStillRunning vStartDynamicPriorityTasks + vLimitedIncrementTask vContinuousIncrementTask vCounterControlTask + vQueueSendWhenSuspendedTask vQueueReceiveWhenSuspendedTask + xAreDynamicPriorityTasksStillRunning +SECTION: ".data" + uxCriticalNesting +SECTION: ".bss" + pxCurrentTCB uxCurrentNumberOfTasks xTickCount uxTopUsedPriority + uxTopReadyPriority xSchedulerRunning uxSchedulerSuspended uxMissedTicks + uxTaskNumber.1 pxReadyTasksLists xDelayedTaskList1 xDelayedTaskList2 + pxDelayedTaskList pxOverflowDelayedTaskList xPendingReadyList + xSuspendedTaskList uxFlashTaskNumber xLocalError uxValToSend.3 xButtonQueue + xNextFreeByte xHeap xPollingConsumerCount xPollingProducerCount + xPolledQueue.1 usCheckVariable xSuspendedQueueSendError + xSuspendedQueueReceiveError ulValueToSend.6 ulExpectedValue.7 + usLastTaskCheck.9 xContinousIncrementHandle xLimitedIncrementHandle ulCounter + ulReceivedValue.8 +SECTION: ".init" + _EntryPoint PE_low_level_init +SECTION: ".rodata1" + STRING.IDLE.2 STRING.LEDx.1 STRING.Check.1 STRING.Button.2 STRING.QConsNB.2 + STRING.QProdNB.3 STRING.CNT_INC.1 STRING.LIM_INC.2 STRING.C_CTRL.3 + STRING.SUSP_TX.4 STRING.SUSP_RX.5 +SECTION: "NON_BANKED" + Cpu_Interrupt xBankedStartScheduler vPortYield vPortTickInterrupt + vButtonPush +SECTION: "RUNTIME" + _LCMP _LCMP_P _LNEG _LINC _lDivMod _LDIVU _NEG_P _LDIVS +SECTION: ".common" + xSuspendedTestQueue +SECTION: "Byte1_CODE" + Byte1_GetMsk Byte1_NegBit +SECTION: "TickTimer_CODE" + SetCV SetPV HWEnDi TickTimer_Enable TickTimer_SetFreqHz TickTimer_Init +SECTION: "ButtonInterrupt_CODE" + ButtonInterrupt_Enable +SECTION: "Byte1_DATA" + Byte1_Table +SECTION: ".abs_section_3f" + _ARMCOP +SECTION: ".abs_section_8d" + _ATDDIEN +SECTION: ".abs_section_86" + _ATDSTAT0 +SECTION: ".abs_section_8b" + _ATDSTAT1 +SECTION: ".abs_section_ff06" + _BDMCCR +SECTION: ".abs_section_ff07" + _BDMINR +SECTION: ".abs_section_ff01" + _BDMSTS +SECTION: ".abs_section_2b" + _BKP0H +SECTION: ".abs_section_2c" + _BKP0L +SECTION: ".abs_section_2a" + _BKP0X +SECTION: ".abs_section_2e" + _BKP1H +SECTION: ".abs_section_2f" + _BKP1L +SECTION: ".abs_section_2d" + _BKP1X +SECTION: ".abs_section_28" + _BKPCT0 +SECTION: ".abs_section_29" + _BKPCT1 +SECTION: ".abs_section_142" + _CANBTR0 +SECTION: ".abs_section_143" + _CANBTR1 +SECTION: ".abs_section_140" + _CANCTL0 +SECTION: ".abs_section_141" + _CANCTL1 +SECTION: ".abs_section_14b" + _CANIDAC +SECTION: ".abs_section_150" + _CANIDAR0 +SECTION: ".abs_section_151" + _CANIDAR1 +SECTION: ".abs_section_152" + _CANIDAR2 +SECTION: ".abs_section_153" + _CANIDAR3 +SECTION: ".abs_section_158" + _CANIDAR4 +SECTION: ".abs_section_159" + _CANIDAR5 +SECTION: ".abs_section_15a" + _CANIDAR6 +SECTION: ".abs_section_15b" + _CANIDAR7 +SECTION: ".abs_section_154" + _CANIDMR0 +SECTION: ".abs_section_155" + _CANIDMR1 +SECTION: ".abs_section_156" + _CANIDMR2 +SECTION: ".abs_section_157" + _CANIDMR3 +SECTION: ".abs_section_15c" + _CANIDMR4 +SECTION: ".abs_section_15d" + _CANIDMR5 +SECTION: ".abs_section_15e" + _CANIDMR6 +SECTION: ".abs_section_15f" + _CANIDMR7 +SECTION: ".abs_section_144" + _CANRFLG +SECTION: ".abs_section_145" + _CANRIER +SECTION: ".abs_section_16c" + _CANRXDLR +SECTION: ".abs_section_164" + _CANRXDSR0 +SECTION: ".abs_section_165" + _CANRXDSR1 +SECTION: ".abs_section_166" + _CANRXDSR2 +SECTION: ".abs_section_167" + _CANRXDSR3 +SECTION: ".abs_section_168" + _CANRXDSR4 +SECTION: ".abs_section_169" + _CANRXDSR5 +SECTION: ".abs_section_16a" + _CANRXDSR6 +SECTION: ".abs_section_16b" + _CANRXDSR7 +SECTION: ".abs_section_14e" + _CANRXERR +SECTION: ".abs_section_160" + _CANRXIDR0 +SECTION: ".abs_section_161" + _CANRXIDR1 +SECTION: ".abs_section_162" + _CANRXIDR2 +SECTION: ".abs_section_163" + _CANRXIDR3 +SECTION: ".abs_section_149" + _CANTAAK +SECTION: ".abs_section_148" + _CANTARQ +SECTION: ".abs_section_14a" + _CANTBSEL +SECTION: ".abs_section_146" + _CANTFLG +SECTION: ".abs_section_147" + _CANTIER +SECTION: ".abs_section_17c" + _CANTXDLR +SECTION: ".abs_section_174" + _CANTXDSR0 +SECTION: ".abs_section_175" + _CANTXDSR1 +SECTION: ".abs_section_176" + _CANTXDSR2 +SECTION: ".abs_section_177" + _CANTXDSR3 +SECTION: ".abs_section_178" + _CANTXDSR4 +SECTION: ".abs_section_179" + _CANTXDSR5 +SECTION: ".abs_section_17a" + _CANTXDSR6 +SECTION: ".abs_section_17b" + _CANTXDSR7 +SECTION: ".abs_section_14f" + _CANTXERR +SECTION: ".abs_section_170" + _CANTXIDR0 +SECTION: ".abs_section_171" + _CANTXIDR1 +SECTION: ".abs_section_172" + _CANTXIDR2 +SECTION: ".abs_section_173" + _CANTXIDR3 +SECTION: ".abs_section_17f" + _CANTXTBPR +SECTION: ".abs_section_41" + _CFORC +SECTION: ".abs_section_39" + _CLKSEL +SECTION: ".abs_section_3c" + _COPCTL +SECTION: ".abs_section_37" + _CRGFLG +SECTION: ".abs_section_38" + _CRGINT +SECTION: ".abs_section_3e" + _CTCTL +SECTION: ".abs_section_36" + _CTFLG +SECTION: ".abs_section_272" + _DDRAD +SECTION: ".abs_section_9" + _DDRE +SECTION: ".abs_section_26a" + _DDRJ +SECTION: ".abs_section_33" + _DDRK +SECTION: ".abs_section_252" + _DDRM +SECTION: ".abs_section_25a" + _DDRP +SECTION: ".abs_section_24a" + _DDRS +SECTION: ".abs_section_242" + _DDRT +SECTION: ".abs_section_e" + _EBICTL +SECTION: ".abs_section_100" + _FCLKDIV +SECTION: ".abs_section_106" + _FCMD +SECTION: ".abs_section_103" + _FCNFG +SECTION: ".abs_section_104" + _FPROT +SECTION: ".abs_section_101" + _FSEC +SECTION: ".abs_section_105" + _FSTAT +SECTION: ".abs_section_1f" + _HPRIO +SECTION: ".abs_section_12" + _INITEE +SECTION: ".abs_section_11" + _INITRG +SECTION: ".abs_section_10" + _INITRM +SECTION: ".abs_section_1e" + _INTCR +SECTION: ".abs_section_15" + _ITCR +SECTION: ".abs_section_16" + _ITEST +SECTION: ".abs_section_1c" + _MEMSIZ0 +SECTION: ".abs_section_1d" + _MEMSIZ1 +SECTION: ".abs_section_13" + _MISC +SECTION: ".abs_section_b" + _MODE +SECTION: ".abs_section_247" + _MODRR +SECTION: ".abs_section_14" + _MTST0 +SECTION: ".abs_section_17" + _MTST1 +SECTION: ".abs_section_43" + _OC7D +SECTION: ".abs_section_42" + _OC7M +SECTION: ".abs_section_60" + _PACTL +SECTION: ".abs_section_61" + _PAFLG +SECTION: ".abs_section_1a" + _PARTIDH +SECTION: ".abs_section_1b" + _PARTIDL +SECTION: ".abs_section_a" + _PEAR +SECTION: ".abs_section_274" + _PERAD +SECTION: ".abs_section_26c" + _PERJ +SECTION: ".abs_section_254" + _PERM +SECTION: ".abs_section_25c" + _PERP +SECTION: ".abs_section_24c" + _PERS +SECTION: ".abs_section_244" + _PERT +SECTION: ".abs_section_26e" + _PIEJ +SECTION: ".abs_section_25e" + _PIEP +SECTION: ".abs_section_26f" + _PIFJ +SECTION: ".abs_section_25f" + _PIFP +SECTION: ".abs_section_3a" + _PLLCTL +SECTION: ".abs_section_8f" + _PORTAD0 +SECTION: ".abs_section_8" + _PORTE +SECTION: ".abs_section_32" + _PORTK +SECTION: ".abs_section_30" + _PPAGE +SECTION: ".abs_section_275" + _PPSAD +SECTION: ".abs_section_26d" + _PPSJ +SECTION: ".abs_section_255" + _PPSM +SECTION: ".abs_section_25d" + _PPSP +SECTION: ".abs_section_24d" + _PPSS +SECTION: ".abs_section_245" + _PPST +SECTION: ".abs_section_270" + _PTAD +SECTION: ".abs_section_271" + _PTIAD +SECTION: ".abs_section_269" + _PTIJ +SECTION: ".abs_section_251" + _PTIM +SECTION: ".abs_section_259" + _PTIP +SECTION: ".abs_section_249" + _PTIS +SECTION: ".abs_section_241" + _PTIT +SECTION: ".abs_section_268" + _PTJ +SECTION: ".abs_section_250" + _PTM +SECTION: ".abs_section_258" + _PTP +SECTION: ".abs_section_248" + _PTS +SECTION: ".abs_section_240" + _PTT +SECTION: ".abs_section_c" + _PUCR +SECTION: ".abs_section_e4" + _PWMCAE +SECTION: ".abs_section_e2" + _PWMCLK +SECTION: ".abs_section_e5" + _PWMCTL +SECTION: ".abs_section_e0" + _PWME +SECTION: ".abs_section_e1" + _PWMPOL +SECTION: ".abs_section_e3" + _PWMPRCLK +SECTION: ".abs_section_e8" + _PWMSCLA +SECTION: ".abs_section_e9" + _PWMSCLB +SECTION: ".abs_section_fe" + _PWMSDN +SECTION: ".abs_section_273" + _RDRAD +SECTION: ".abs_section_d" + _RDRIV +SECTION: ".abs_section_26b" + _RDRJ +SECTION: ".abs_section_253" + _RDRM +SECTION: ".abs_section_25b" + _RDRP +SECTION: ".abs_section_24b" + _RDRS +SECTION: ".abs_section_243" + _RDRT +SECTION: ".abs_section_35" + _REFDV +SECTION: ".abs_section_3b" + _RTICTL +SECTION: ".abs_section_ca" + _SCICR1 +SECTION: ".abs_section_cb" + _SCICR2 +SECTION: ".abs_section_ce" + _SCIDRH +SECTION: ".abs_section_cf" + _SCIDRL +SECTION: ".abs_section_cc" + _SCISR1 +SECTION: ".abs_section_cd" + _SCISR2 +SECTION: ".abs_section_da" + _SPIBR +SECTION: ".abs_section_d8" + _SPICR1 +SECTION: ".abs_section_d9" + _SPICR2 +SECTION: ".abs_section_dd" + _SPIDR +SECTION: ".abs_section_db" + _SPISR +SECTION: ".abs_section_34" + _SYNR +SECTION: ".abs_section_48" + _TCTL1 +SECTION: ".abs_section_49" + _TCTL2 +SECTION: ".abs_section_4a" + _TCTL3 +SECTION: ".abs_section_4b" + _TCTL4 +SECTION: ".abs_section_4e" + _TFLG1 +SECTION: ".abs_section_4f" + _TFLG2 +SECTION: ".abs_section_4c" + _TIE +SECTION: ".abs_section_40" + _TIOS +SECTION: ".abs_section_46" + _TSCR1 +SECTION: ".abs_section_4d" + _TSCR2 +SECTION: ".abs_section_47" + _TTOV +SECTION: ".abs_section_256" + _WOMM +SECTION: ".abs_section_24e" + _WOMS +SECTION: ".abs_section_82" + _ATDCTL23 +SECTION: ".abs_section_84" + _ATDCTL45 +SECTION: ".abs_section_90" + _ATDDR0 +SECTION: ".abs_section_92" + _ATDDR1 +SECTION: ".abs_section_94" + _ATDDR2 +SECTION: ".abs_section_96" + _ATDDR3 +SECTION: ".abs_section_98" + _ATDDR4 +SECTION: ".abs_section_9a" + _ATDDR5 +SECTION: ".abs_section_9c" + _ATDDR6 +SECTION: ".abs_section_9e" + _ATDDR7 +SECTION: ".abs_section_2" + _DDRAB +SECTION: ".abs_section_62" + _PACNT +SECTION: ".abs_section_0" + _PORTAB +SECTION: ".abs_section_ec" + _PWMCNT01 +SECTION: ".abs_section_ee" + _PWMCNT23 +SECTION: ".abs_section_f0" + _PWMCNT45 +SECTION: ".abs_section_f8" + _PWMDTY01 +SECTION: ".abs_section_fa" + _PWMDTY23 +SECTION: ".abs_section_fc" + _PWMDTY45 +SECTION: ".abs_section_f2" + _PWMPER01 +SECTION: ".abs_section_f4" + _PWMPER23 +SECTION: ".abs_section_f6" + _PWMPER45 +SECTION: ".abs_section_c8" + _SCIBD +SECTION: ".abs_section_50" + _TC0 +SECTION: ".abs_section_52" + _TC1 +SECTION: ".abs_section_54" + _TC2 +SECTION: ".abs_section_56" + _TC3 +SECTION: ".abs_section_58" + _TC4 +SECTION: ".abs_section_5a" + _TC5 +SECTION: ".abs_section_5c" + _TC6 +SECTION: ".abs_section_5e" + _TC7 +SECTION: ".abs_section_44" + _TCNT +SECTION: ".abs_section_ff80" + _vect +SECTION: "TickTimer_DATA" + EnUser CmpHighVal + +********************************************************************************************* +OBJECT LIST SORTED BY ADDRESS + Name Addr hSize dSize Ref Section RLIB +--------------------------------------------------------------------------------------------- + _PORTAB 0 2 2 3 .abs_section_0 + _DDRAB 2 2 2 1 .abs_section_2 + _PORTE 8 1 1 0 .abs_section_8 + _DDRE 9 1 1 0 .abs_section_9 + _PEAR A 1 1 0 .abs_section_a + _MODE B 1 1 0 .abs_section_b + _PUCR C 1 1 0 .abs_section_c + _RDRIV D 1 1 0 .abs_section_d + _EBICTL E 1 1 0 .abs_section_e + _INITRM 10 1 1 1 .abs_section_10 + _INITRG 11 1 1 0 .abs_section_11 + _INITEE 12 1 1 0 .abs_section_12 + _MISC 13 1 1 1 .abs_section_13 + _MTST0 14 1 1 0 .abs_section_14 + _ITCR 15 1 1 0 .abs_section_15 + _ITEST 16 1 1 0 .abs_section_16 + _MTST1 17 1 1 0 .abs_section_17 + _PARTIDH 1A 1 1 0 .abs_section_1a + _PARTIDL 1B 1 1 0 .abs_section_1b + _MEMSIZ0 1C 1 1 0 .abs_section_1c + _MEMSIZ1 1D 1 1 0 .abs_section_1d + _INTCR 1E 1 1 1 .abs_section_1e + _HPRIO 1F 1 1 0 .abs_section_1f + _BKPCT0 28 1 1 0 .abs_section_28 + _BKPCT1 29 1 1 0 .abs_section_29 + _BKP0X 2A 1 1 0 .abs_section_2a + _BKP0H 2B 1 1 0 .abs_section_2b + _BKP0L 2C 1 1 0 .abs_section_2c + _BKP1X 2D 1 1 0 .abs_section_2d + _BKP1H 2E 1 1 0 .abs_section_2e + _BKP1L 2F 1 1 0 .abs_section_2f + _PPAGE 30 1 1 0 .abs_section_30 + _PORTK 32 1 1 0 .abs_section_32 + _DDRK 33 1 1 0 .abs_section_33 + _SYNR 34 1 1 1 .abs_section_34 + _REFDV 35 1 1 1 .abs_section_35 + _CTFLG 36 1 1 0 .abs_section_36 + _CRGFLG 37 1 1 1 .abs_section_37 + _CRGINT 38 1 1 0 .abs_section_38 + _CLKSEL 39 1 1 3 .abs_section_39 + _PLLCTL 3A 1 1 3 .abs_section_3a + _RTICTL 3B 1 1 0 .abs_section_3b + _COPCTL 3C 1 1 0 .abs_section_3c + _CTCTL 3E 1 1 0 .abs_section_3e + _ARMCOP 3F 1 1 0 .abs_section_3f + _TIOS 40 1 1 1 .abs_section_40 + _CFORC 41 1 1 0 .abs_section_41 + _OC7M 42 1 1 0 .abs_section_42 + _OC7D 43 1 1 0 .abs_section_43 + _TCNT 44 2 2 0 .abs_section_44 + _TSCR1 46 1 1 3 .abs_section_46 + _TTOV 47 1 1 1 .abs_section_47 + _TCTL1 48 1 1 1 .abs_section_48 + _TCTL2 49 1 1 1 .abs_section_49 + _TCTL3 4A 1 1 0 .abs_section_4a + _TCTL4 4B 1 1 0 .abs_section_4b + _TIE 4C 1 1 3 .abs_section_4c + _TSCR2 4D 1 1 5 .abs_section_4d + _TFLG1 4E 1 1 2 .abs_section_4e + _TFLG2 4F 1 1 0 .abs_section_4f + _TC0 50 2 2 1 .abs_section_50 + _TC1 52 2 2 0 .abs_section_52 + _TC2 54 2 2 0 .abs_section_54 + _TC3 56 2 2 0 .abs_section_56 + _TC4 58 2 2 0 .abs_section_58 + _TC5 5A 2 2 0 .abs_section_5a + _TC6 5C 2 2 0 .abs_section_5c + _TC7 5E 2 2 1 .abs_section_5e + _PACTL 60 1 1 0 .abs_section_60 + _PAFLG 61 1 1 0 .abs_section_61 + _PACNT 62 2 2 0 .abs_section_62 + _ATDCTL23 82 2 2 0 .abs_section_82 + _ATDCTL45 84 2 2 0 .abs_section_84 + _ATDSTAT0 86 1 1 0 .abs_section_86 + _ATDSTAT1 8B 1 1 0 .abs_section_8b + _ATDDIEN 8D 1 1 0 .abs_section_8d + _PORTAD0 8F 1 1 0 .abs_section_8f + _ATDDR0 90 2 2 0 .abs_section_90 + _ATDDR1 92 2 2 0 .abs_section_92 + _ATDDR2 94 2 2 0 .abs_section_94 + _ATDDR3 96 2 2 0 .abs_section_96 + _ATDDR4 98 2 2 0 .abs_section_98 + _ATDDR5 9A 2 2 0 .abs_section_9a + _ATDDR6 9C 2 2 0 .abs_section_9c + _ATDDR7 9E 2 2 0 .abs_section_9e + _SCIBD C8 2 2 0 .abs_section_c8 + _SCICR1 CA 1 1 0 .abs_section_ca + _SCICR2 CB 1 1 0 .abs_section_cb + _SCISR1 CC 1 1 0 .abs_section_cc + _SCISR2 CD 1 1 0 .abs_section_cd + _SCIDRH CE 1 1 0 .abs_section_ce + _SCIDRL CF 1 1 0 .abs_section_cf + _SPICR1 D8 1 1 0 .abs_section_d8 + _SPICR2 D9 1 1 0 .abs_section_d9 + _SPIBR DA 1 1 0 .abs_section_da + _SPISR DB 1 1 0 .abs_section_db + _SPIDR DD 1 1 0 .abs_section_dd + _PWME E0 1 1 0 .abs_section_e0 + _PWMPOL E1 1 1 0 .abs_section_e1 + _PWMCLK E2 1 1 0 .abs_section_e2 + _PWMPRCLK E3 1 1 0 .abs_section_e3 + _PWMCAE E4 1 1 0 .abs_section_e4 + _PWMCTL E5 1 1 1 .abs_section_e5 + _PWMSCLA E8 1 1 0 .abs_section_e8 + _PWMSCLB E9 1 1 0 .abs_section_e9 + _PWMCNT01 EC 2 2 0 .abs_section_ec + _PWMCNT23 EE 2 2 0 .abs_section_ee + _PWMCNT45 F0 2 2 0 .abs_section_f0 + _PWMPER01 F2 2 2 0 .abs_section_f2 + _PWMPER23 F4 2 2 0 .abs_section_f4 + _PWMPER45 F6 2 2 0 .abs_section_f6 + _PWMDTY01 F8 2 2 0 .abs_section_f8 + _PWMDTY23 FA 2 2 0 .abs_section_fa + _PWMDTY45 FC 2 2 0 .abs_section_fc + _PWMSDN FE 1 1 1 .abs_section_fe + _FCLKDIV 100 1 1 0 .abs_section_100 + _FSEC 101 1 1 0 .abs_section_101 + _FCNFG 103 1 1 0 .abs_section_103 + _FPROT 104 1 1 0 .abs_section_104 + _FSTAT 105 1 1 0 .abs_section_105 + _FCMD 106 1 1 0 .abs_section_106 + _CANCTL0 140 1 1 0 .abs_section_140 + _CANCTL1 141 1 1 0 .abs_section_141 + _CANBTR0 142 1 1 0 .abs_section_142 + _CANBTR1 143 1 1 0 .abs_section_143 + _CANRFLG 144 1 1 0 .abs_section_144 + _CANRIER 145 1 1 0 .abs_section_145 + _CANTFLG 146 1 1 0 .abs_section_146 + _CANTIER 147 1 1 0 .abs_section_147 + _CANTARQ 148 1 1 0 .abs_section_148 + _CANTAAK 149 1 1 0 .abs_section_149 + _CANTBSEL 14A 1 1 0 .abs_section_14a + _CANIDAC 14B 1 1 0 .abs_section_14b + _CANRXERR 14E 1 1 0 .abs_section_14e + _CANTXERR 14F 1 1 0 .abs_section_14f + _CANIDAR0 150 1 1 0 .abs_section_150 + _CANIDAR1 151 1 1 0 .abs_section_151 + _CANIDAR2 152 1 1 0 .abs_section_152 + _CANIDAR3 153 1 1 0 .abs_section_153 + _CANIDMR0 154 1 1 0 .abs_section_154 + _CANIDMR1 155 1 1 0 .abs_section_155 + _CANIDMR2 156 1 1 0 .abs_section_156 + _CANIDMR3 157 1 1 0 .abs_section_157 + _CANIDAR4 158 1 1 0 .abs_section_158 + _CANIDAR5 159 1 1 0 .abs_section_159 + _CANIDAR6 15A 1 1 0 .abs_section_15a + _CANIDAR7 15B 1 1 0 .abs_section_15b + _CANIDMR4 15C 1 1 0 .abs_section_15c + _CANIDMR5 15D 1 1 0 .abs_section_15d + _CANIDMR6 15E 1 1 0 .abs_section_15e + _CANIDMR7 15F 1 1 0 .abs_section_15f + _CANRXIDR0 160 1 1 0 .abs_section_160 + _CANRXIDR1 161 1 1 0 .abs_section_161 + _CANRXIDR2 162 1 1 0 .abs_section_162 + _CANRXIDR3 163 1 1 0 .abs_section_163 + _CANRXDSR0 164 1 1 0 .abs_section_164 + _CANRXDSR1 165 1 1 0 .abs_section_165 + _CANRXDSR2 166 1 1 0 .abs_section_166 + _CANRXDSR3 167 1 1 0 .abs_section_167 + _CANRXDSR4 168 1 1 0 .abs_section_168 + _CANRXDSR5 169 1 1 0 .abs_section_169 + _CANRXDSR6 16A 1 1 0 .abs_section_16a + _CANRXDSR7 16B 1 1 0 .abs_section_16b + _CANRXDLR 16C 1 1 0 .abs_section_16c + _CANTXIDR0 170 1 1 0 .abs_section_170 + _CANTXIDR1 171 1 1 0 .abs_section_171 + _CANTXIDR2 172 1 1 0 .abs_section_172 + _CANTXIDR3 173 1 1 0 .abs_section_173 + _CANTXDSR0 174 1 1 0 .abs_section_174 + _CANTXDSR1 175 1 1 0 .abs_section_175 + _CANTXDSR2 176 1 1 0 .abs_section_176 + _CANTXDSR3 177 1 1 0 .abs_section_177 + _CANTXDSR4 178 1 1 0 .abs_section_178 + _CANTXDSR5 179 1 1 0 .abs_section_179 + _CANTXDSR6 17A 1 1 0 .abs_section_17a + _CANTXDSR7 17B 1 1 0 .abs_section_17b + _CANTXDLR 17C 1 1 0 .abs_section_17c + _CANTXTBPR 17F 1 1 0 .abs_section_17f + _PTT 240 1 1 0 .abs_section_240 + _PTIT 241 1 1 0 .abs_section_241 + _DDRT 242 1 1 0 .abs_section_242 + _RDRT 243 1 1 0 .abs_section_243 + _PERT 244 1 1 0 .abs_section_244 + _PPST 245 1 1 0 .abs_section_245 + _MODRR 247 1 1 0 .abs_section_247 + _PTS 248 1 1 0 .abs_section_248 + _PTIS 249 1 1 0 .abs_section_249 + _DDRS 24A 1 1 0 .abs_section_24a + _RDRS 24B 1 1 0 .abs_section_24b + _PERS 24C 1 1 0 .abs_section_24c + _PPSS 24D 1 1 0 .abs_section_24d + _WOMS 24E 1 1 0 .abs_section_24e + _PTM 250 1 1 0 .abs_section_250 + _PTIM 251 1 1 0 .abs_section_251 + _DDRM 252 1 1 0 .abs_section_252 + _RDRM 253 1 1 0 .abs_section_253 + _PERM 254 1 1 0 .abs_section_254 + _PPSM 255 1 1 0 .abs_section_255 + _WOMM 256 1 1 0 .abs_section_256 + _PTP 258 1 1 0 .abs_section_258 + _PTIP 259 1 1 0 .abs_section_259 + _DDRP 25A 1 1 1 .abs_section_25a + _RDRP 25B 1 1 0 .abs_section_25b + _PERP 25C 1 1 1 .abs_section_25c + _PPSP 25D 1 1 1 .abs_section_25d + _PIEP 25E 1 1 2 .abs_section_25e + _PIFP 25F 1 1 2 .abs_section_25f + _PTJ 268 1 1 0 .abs_section_268 + _PTIJ 269 1 1 0 .abs_section_269 + _DDRJ 26A 1 1 0 .abs_section_26a + _RDRJ 26B 1 1 0 .abs_section_26b + _PERJ 26C 1 1 0 .abs_section_26c + _PPSJ 26D 1 1 0 .abs_section_26d + _PIEJ 26E 1 1 0 .abs_section_26e + _PIFJ 26F 1 1 0 .abs_section_26f + _PTAD 270 1 1 0 .abs_section_270 + _PTIAD 271 1 1 0 .abs_section_271 + _DDRAD 272 1 1 0 .abs_section_272 + _RDRAD 273 1 1 0 .abs_section_273 + _PERAD 274 1 1 0 .abs_section_274 + _PPSAD 275 1 1 0 .abs_section_275 + uxCriticalNesting 800 1 1 91 .data + pxCurrentTCB 801 2 2 29 .bss + uxCurrentNumberOfTasks 803 1 1 3 .bss + xTickCount 804 2 2 14 .bss + uxTopUsedPriority 806 1 1 2 .bss + uxTopReadyPriority 807 1 1 15 .bss + xSchedulerRunning 808 1 1 3 .bss + uxSchedulerSuspended 809 1 1 6 .bss + uxMissedTicks 80A 1 1 4 .bss + uxTaskNumber.1 80B 1 1 2 .bss + pxReadyTasksLists 80C 3C 60 11 .bss + xDelayedTaskList1 848 F 15 2 .bss + xDelayedTaskList2 857 F 15 2 .bss + pxDelayedTaskList 866 2 2 8 .bss + pxOverflowDelayedTaskList 868 2 2 6 .bss + xPendingReadyList 86A F 15 4 .bss + xSuspendedTaskList 879 F 15 2 .bss + uxFlashTaskNumber 888 1 1 2 .bss + xLocalError 889 1 1 3 .bss + uxValToSend.3 88A 1 1 2 .bss + xButtonQueue 88B 2 2 3 .bss + xNextFreeByte 88D 2 2 5 .bss + xHeap 88F 704 1796 1 .bss + xPollingConsumerCount F93 1 1 3 .bss + xPollingProducerCount F94 1 1 3 .bss + xPolledQueue.1 F95 2 2 3 .bss + usCheckVariable F97 2 2 4 .bss + xSuspendedQueueSendError F99 1 1 2 .bss + xSuspendedQueueReceiveError F9A 1 1 3 .bss + ulValueToSend.6 F9B 4 4 5 .bss + ulExpectedValue.7 F9F 4 4 6 .bss + usLastTaskCheck.9 FA3 2 2 2 .bss + xContinousIncrementHandle FA5 2 2 5 .bss + xLimitedIncrementHandle FA7 2 2 2 .bss + ulCounter FA9 4 4 10 .bss + ulReceivedValue.8 FAD 4 4 3 .bss + xSuspendedTestQueue FB1 2 2 3 .common + Byte1_Table FB3 8 8 1 Byte1_DATA + EnUser FBB 1 1 4 TickTimer_DATA + CmpHighVal FBC 2 2 2 TickTimer_DATA + _EntryPoint C000 2E 46 1 .init + PE_low_level_init C02E 48 72 1 .init + STRING.IDLE.2 C093 5 5 1 .rodata1 + STRING.LEDx.1 C098 5 5 1 .rodata1 + STRING.Check.1 C09D 6 6 1 .rodata1 + STRING.Button.2 C0A3 7 7 1 .rodata1 + STRING.QConsNB.2 C0AA 8 8 1 .rodata1 + STRING.QProdNB.3 C0B2 8 8 1 .rodata1 + STRING.CNT_INC.1 C0BA 8 8 1 .rodata1 + STRING.LIM_INC.2 C0C2 8 8 1 .rodata1 + STRING.C_CTRL.3 C0CA 7 7 1 .rodata1 + STRING.SUSP_TX.4 C0D1 8 8 1 .rodata1 + STRING.SUSP_RX.5 C0D9 8 8 1 .rodata1 + Cpu_Interrupt C0E1 1 1 60 NON_BANKED + xBankedStartScheduler C0E2 F 15 1 NON_BANKED + vPortYield C0F1 16 22 1 NON_BANKED + vPortTickInterrupt C107 1D 29 1 NON_BANKED + vButtonPush C124 2F 47 1 NON_BANKED + Init C153 29 41 1 .text + _Startup C17C 10 16 1 .text + memcpy C18C 26 38 3 .text + memset C1B2 1E 30 1 .text + strncpy C1D0 2D 45 1 .text + main C1FD 8 8 0 .text + xTaskCreate C205 CE 206 11 .text + vTaskDelayUntil C2D3 74 116 3 .text + vTaskDelay C347 46 70 4 .text + uxTaskPriorityGet C38D 26 38 1 .text + vTaskPrioritySet C3B3 69 105 2 .text + vTaskSuspend C41C 44 68 3 .text + vTaskResume C460 59 89 3 .text + vTaskStartScheduler C4B9 30 48 1 .text + vTaskSuspendAll C4E9 13 19 11 .text + xTaskResumeAll C4FC 9F 159 13 .text + xTaskGetTickCount C59B 17 23 2 .text + vTaskIncrementTick C5B2 81 129 2 .text + vTaskSwitchContext C633 5B 91 3 .text + vTaskPlaceOnEventList C68E 41 65 2 .text + xTaskRemoveFromEventList C6CF 6C 108 3 .text + prvIdleTask C73B 10 16 1 .text + prvInitialiseTCBVariables C74B 4C 76 1 .text + prvInitialiseTaskLists C797 3C 60 1 .text + prvCheckTasksWaitingTermination C7D3 1 1 1 .text + prvAllocateTCBAndStack C7D4 33 51 1 .text + xQueueCreate C807 77 119 3 .text + xQueueSend C87E CA 202 3 .text + xQueueSendFromISR C948 54 84 1 .text + xQueueReceive C99C C4 196 4 .text + uxQueueMessagesWaiting CA60 1B 27 1 .text + prvUnlockQueue CA7B 6F 111 4 .text + prvIsQueueEmpty CAEA 21 33 1 .text + prvIsQueueFull CB0B 24 36 1 .text + vListInitialise CB2F 1F 31 7 .text + vListInitialiseItem CB4E 7 7 3 .text + vListInsertEnd CB55 27 39 7 .text + vListInsert CB7C 5A 90 4 .text + vListRemove CBD6 23 35 13 .text + pxPortInitialiseStack CBF9 2B 43 1 .text + prvSetupTimerInterrupt CC24 9 9 1 .text + xPortStartScheduler CC2D 4 4 1 .text + vStartLEDFlashTasks CC31 26 38 1 .text + vLEDFlashTask CC57 52 82 1 .text + vMain CCA9 42 66 1 .text + vErrorChecks CCEB 2F 47 1 .text + prvCheckOtherTasksAreStillRunning CD1A 23 35 1 .text + vApplicationIdleHook CD3D 73 115 1 .text + vButtonTask CDB0 4F 79 1 .text + pvPortMalloc CDFF 30 48 4 .text + vPortFree CE2F 1 1 2 .text + PE_Timer_LngHi1 CE30 43 67 1 .text + vParTestToggleLED CE73 13 19 4 .text + vStartPolledQueueTasks CE86 40 64 1 .text + vPolledQueueProducer CEC6 4D 77 1 .text + vPolledQueueConsumer CF13 59 89 1 .text + xArePollingQueuesStillRunning CF6C 1D 29 1 .text + vStartDynamicPriorityTasks CF89 7C 124 1 .text + vLimitedIncrementTask D005 21 33 1 .text + vContinuousIncrementTask D026 30 48 1 .text + vCounterControlTask D056 98 152 3 .text + vQueueSendWhenSuspendedTask D0EE 34 52 1 .text + vQueueReceiveWhenSuspendedTask D122 4E 78 1 .text + xAreDynamicPriorityTasksStillRunning D170 27 39 1 .text + _LCMP D197 19 25 2 RUNTIME + _LCMP_P D1B0 15 21 2 RUNTIME + _LNEG D1C5 D 13 1 RUNTIME + _LINC D1D2 5 5 4 RUNTIME + _lDivMod D1D7 E3 227 3 RUNTIME + _LDIVU D2BA E 14 1 RUNTIME + _NEG_P D2C8 F 15 4 RUNTIME + _LDIVS D2D7 35 53 1 RUNTIME + Byte1_GetMsk D30C D 13 1 Byte1_CODE + Byte1_NegBit D319 F 15 1 Byte1_CODE + SetCV D328 F 15 2 TickTimer_CODE + SetPV D337 C 12 1 TickTimer_CODE + HWEnDi D343 11 17 2 TickTimer_CODE + TickTimer_Enable D354 E 14 1 TickTimer_CODE + TickTimer_SetFreqHz D362 4F 79 1 TickTimer_CODE + TickTimer_Init D3B1 14 20 1 TickTimer_CODE + ButtonInterrupt_Enable D3C5 A 10 1 ButtonInterrupt_CODE + _BDMSTS FF01 1 1 0 .abs_section_ff01 + _BDMCCR FF06 1 1 0 .abs_section_ff06 + _BDMINR FF07 1 1 0 .abs_section_ff07 + _vect FF80 80 128 0 .abs_section_ff80 + +********************************************************************************************* +UNUSED-OBJECTS SECTION +--------------------------------------------------------------------------------------------- +NOT USED PROCEDURES +STRING.C.o (ansisi.lib): + strerror memchr memcmp memcpy2 _memcpy_8bitCount memmove + _memset_clear_8bitCount strlen strset strcat strncat strcpy strcmp strncmp + strchr strrchr strspn strcspn strpbrk strstr strtok strcoll strxfrm +rtshc12.c.o (ansisi.lib): + _BSHL _BSHRS _BSHRU _BDIVMODU _BDIVMODS _ISHL _ISHRU _ISHRS _LSHL _LSHRU + _LSHRS _LADD _LSUB _LAND _LOR _LXOR _LCMP_PP _LABS _LCOM _LDEC _LMUL _LMODU + _LMODS _ILSEXT _LTEST _COPY _CASE_DIRECT _CASE_DIRECT_BYTE _CASE_CHECKED + _CASE_CHECKED_BYTE _CASE_SEARCH _CASE_SEARCH_BYTE _CASE_SEARCH_8 + _CASE_SEARCH_8_BYTE _FCALL _FPCMP +Byte1.C.o: + Byte1_PutBit +tasks.c.o: + vTaskEndScheduler uxTaskGetNumberOfTasks +queue.c.o: + xQueueReceiveFromISR vQueueDelete +port.c.o: + vPortEndScheduler +heap_1.c.o: + vPortInitialiseBlocks +TickTimer.C.o: + TickTimer_Interrupt +ParTest.c.o: + vParTestSetLED +ButtonInterrupt.C.o: + ButtonInterrupt_Interrupt +NOT USED VARIABLES +STRING.C.o (ansisi.lib): + STRING..1 next.2 +rtshc12.c.o (ansisi.lib): + _PowOfTwo_8 _PowOfTwo_16 _PowOfTwo_32 +Cpu.C.o: + CpuMode CCR_reg + +********************************************************************************************* +COPYDOWN SECTION +--------------------------------------------------------------------------------------------- +------- ROM-ADDRESS: 0xD3CF ---- SIZE 4 --- +Filling bytes inserted + 00010800 +------- ROM-ADDRESS: 0xD3D3 ---- RAM-ADDRESS: 0x800 ---- SIZE 1 --- +Name of initialized Object : uxCriticalNesting + FF +------- ROM-ADDRESS: 0xD3D4 ---- SIZE 4 --- +Filling bytes inserted + 00080FB3 +------- ROM-ADDRESS: 0xD3D8 ---- RAM-ADDRESS: 0xFB3 ---- SIZE 8 --- +Name of initialized Object : Byte1_Table + 0102040810 204080 +------- ROM-ADDRESS: 0xD3E0 ---- SIZE 2 --- +Filling bytes inserted + 0000 + +********************************************************************************************* +OBJECT-DEPENDENCIES SECTION +--------------------------------------------------------------------------------------------- +_EntryPoint USES _INITRM _MISC _CLKSEL _PLLCTL _SYNR _REFDV + _CRGFLG _Startup +PE_low_level_init USES _TSCR1 _TCTL2 _TCTL1 _TIE _TTOV _TSCR2 _TIOS + _PPSP _PERP _DDRP _PWMCTL _PWMSDN _PORTAB _DDRAB + TickTimer_Init _PIEP _INTCR +xBankedStartScheduler USES prvSetupTimerInterrupt pxCurrentTCB + uxCriticalNesting +vPortYield USES uxCriticalNesting pxCurrentTCB + vTaskSwitchContext +vPortTickInterrupt USES uxCriticalNesting pxCurrentTCB + vTaskIncrementTick vTaskSwitchContext _TFLG1 +vButtonPush USES uxValToSend.3 _PIFP xButtonQueue + xQueueSendFromISR uxCriticalNesting pxCurrentTCB + vTaskSwitchContext +Init USES _startupData +_Startup USES _startupData Init +main USES PE_low_level_init vMain +xTaskCreate USES prvAllocateTCBAndStack + prvInitialiseTCBVariables pxPortInitialiseStack uxCriticalNesting + uxCurrentNumberOfTasks pxCurrentTCB prvInitialiseTaskLists + xSchedulerRunning uxTopUsedPriority uxTaskNumber.1 + uxTopReadyPriority pxReadyTasksLists vListInsertEnd +vTaskDelayUntil USES vTaskSuspendAll xTickCount pxCurrentTCB + vListRemove pxOverflowDelayedTaskList pxDelayedTaskList + vListInsert xTaskResumeAll +vTaskDelay USES vTaskSuspendAll xTickCount pxCurrentTCB + vListRemove pxOverflowDelayedTaskList pxDelayedTaskList + vListInsert xTaskResumeAll +uxTaskPriorityGet USES uxCriticalNesting pxCurrentTCB +vTaskPrioritySet USES uxCriticalNesting pxCurrentTCB + pxReadyTasksLists vListRemove uxTopReadyPriority vListInsertEnd +vTaskSuspend USES uxCriticalNesting pxCurrentTCB vListRemove + xSuspendedTaskList vListInsertEnd +vTaskResume USES uxCriticalNesting pxCurrentTCB vListRemove + uxTopReadyPriority pxReadyTasksLists vListInsertEnd +vTaskStartScheduler USES pxCurrentTCB prvIdleTask STRING.IDLE.2 + xTaskCreate xSchedulerRunning xTickCount + xPortStartScheduler +vTaskSuspendAll USES uxCriticalNesting uxSchedulerSuspended +xTaskResumeAll USES uxCriticalNesting uxSchedulerSuspended + uxCurrentNumberOfTasks vListRemove uxTopReadyPriority + pxReadyTasksLists vListInsertEnd pxCurrentTCB xPendingReadyList + uxMissedTicks vTaskIncrementTick +xTaskGetTickCount USES uxCriticalNesting xTickCount +vTaskIncrementTick USES uxSchedulerSuspended xTickCount + pxDelayedTaskList pxOverflowDelayedTaskList vListRemove + uxTopReadyPriority pxReadyTasksLists vListInsertEnd uxMissedTicks +vTaskSwitchContext USES uxSchedulerSuspended uxTopReadyPriority + pxCurrentTCB pxReadyTasksLists +vTaskPlaceOnEventList USES pxCurrentTCB vListInsert xTickCount vListRemove + pxOverflowDelayedTaskList pxDelayedTaskList +xTaskRemoveFromEventList USES vListRemove uxSchedulerSuspended + uxTopReadyPriority pxReadyTasksLists xPendingReadyList + vListInsertEnd pxCurrentTCB +prvIdleTask USES prvCheckTasksWaitingTermination + pxReadyTasksLists vApplicationIdleHook +prvInitialiseTCBVariables USES strncpy vListInitialiseItem +prvInitialiseTaskLists USES pxReadyTasksLists vListInitialise + xDelayedTaskList1 xDelayedTaskList2 xPendingReadyList + xSuspendedTaskList pxDelayedTaskList pxOverflowDelayedTaskList +prvAllocateTCBAndStack USES pvPortMalloc vPortFree memset +xQueueCreate USES pvPortMalloc vListInitialise vPortFree +xQueueSend USES vTaskSuspendAll uxCriticalNesting xQueueSend + prvIsQueueFull vTaskPlaceOnEventList prvUnlockQueue + xTaskResumeAll memcpy +xQueueSendFromISR USES memcpy xTaskRemoveFromEventList +xQueueReceive USES vTaskSuspendAll uxCriticalNesting xQueueReceive + prvIsQueueEmpty vTaskPlaceOnEventList prvUnlockQueue + xTaskResumeAll memcpy +uxQueueMessagesWaiting USES uxCriticalNesting +prvUnlockQueue USES uxCriticalNesting xTaskRemoveFromEventList +prvIsQueueEmpty USES uxCriticalNesting +prvIsQueueFull USES uxCriticalNesting +vListInitialise USES vListInitialiseItem +prvSetupTimerInterrupt USES TickTimer_SetFreqHz TickTimer_Enable +xPortStartScheduler USES xBankedStartScheduler +vStartLEDFlashTasks USES vLEDFlashTask STRING.LEDx.1 xTaskCreate +vLEDFlashTask USES uxCriticalNesting uxFlashTaskNumber + xTaskGetTickCount vTaskDelayUntil vParTestToggleLED +vMain USES vStartLEDFlashTasks vStartPolledQueueTasks + vStartDynamicPriorityTasks vErrorChecks STRING.Check.1 xTaskCreate + vButtonTask STRING.Button.2 vTaskStartScheduler +vErrorChecks USES xTaskGetTickCount vTaskDelayUntil + prvCheckOtherTasksAreStillRunning _LCMP vParTestToggleLED +prvCheckOtherTasksAreStillRunning USES xArePollingQueuesStillRunning + xAreDynamicPriorityTasksStillRunning xLocalError +vApplicationIdleHook USES _LNEG _LDIVS _LCMP_P uxCriticalNesting + xLocalError +vButtonTask USES xQueueCreate xButtonQueue + ButtonInterrupt_Enable xQueueReceive uxCriticalNesting xLocalError + vParTestToggleLED +pvPortMalloc USES vTaskSuspendAll xNextFreeByte xHeap + xTaskResumeAll +PE_Timer_LngHi1 USES _LCMP +vParTestToggleLED USES uxCriticalNesting Byte1_NegBit +vStartPolledQueueTasks USES xQueueCreate xPolledQueue.1 + vPolledQueueConsumer STRING.QConsNB.2 xTaskCreate + vPolledQueueProducer STRING.QProdNB.3 +vPolledQueueProducer USES xQueueSend uxCriticalNesting + xPollingProducerCount vTaskDelay +vPolledQueueConsumer USES xQueueReceive uxCriticalNesting + xPollingConsumerCount uxQueueMessagesWaiting vTaskDelay +xArePollingQueuesStillRunning USES xPollingConsumerCount xPollingProducerCount +vStartDynamicPriorityTasks USES xQueueCreate xSuspendedTestQueue + vContinuousIncrementTask STRING.CNT_INC.1 ulCounter + xContinousIncrementHandle xTaskCreate vLimitedIncrementTask + STRING.LIM_INC.2 xLimitedIncrementHandle vCounterControlTask + STRING.C_CTRL.3 vQueueSendWhenSuspendedTask STRING.SUSP_TX.4 + vQueueReceiveWhenSuspendedTask STRING.SUSP_RX.5 +vLimitedIncrementTask USES _LINC _LCMP_P vTaskSuspend +vContinuousIncrementTask USES uxTaskPriorityGet vTaskPrioritySet _LINC +vCounterControlTask USES vCounterControlTask xContinousIncrementHandle + vTaskSuspend ulCounter vTaskResume vTaskDelay + vTaskSuspendAll xTaskResumeAll xLimitedIncrementHandle + uxCriticalNesting usCheckVariable +vQueueSendWhenSuspendedTask USES vTaskSuspendAll xSuspendedTestQueue + ulValueToSend.6 xQueueSend xSuspendedQueueSendError + xTaskResumeAll vTaskDelay _LINC +vQueueReceiveWhenSuspendedTask USES vTaskSuspendAll xSuspendedTestQueue + ulReceivedValue.8 xQueueReceive xTaskResumeAll + xSuspendedQueueReceiveError ulExpectedValue.7 _LINC +xAreDynamicPriorityTasksStillRunning USES usCheckVariable usLastTaskCheck.9 + xSuspendedQueueSendError xSuspendedQueueReceiveError +_LDIVU USES _lDivMod +_LDIVS USES _NEG_P _lDivMod +Byte1_GetMsk USES Byte1_Table +Byte1_NegBit USES Byte1_GetMsk _PORTAB +SetCV USES _TC0 _TC7 +SetPV USES _TSCR2 +HWEnDi USES EnUser _TFLG1 _TIE +TickTimer_Enable USES EnUser HWEnDi +TickTimer_SetFreqHz USES _LDIVU PE_Timer_LngHi1 CmpHighVal SetCV +TickTimer_Init USES CmpHighVal EnUser SetCV SetPV HWEnDi +ButtonInterrupt_Enable USES _PIFP _PIEP +_vect USES Cpu_Interrupt vButtonPush vPortTickInterrupt + vPortYield _EntryPoint + +********************************************************************************************* +DEPENDENCY TREE +********************************************************************************************* + main and _Startup Group + | + +- main + | | + | +- PE_low_level_init + | | | + | | +- TickTimer_Init + | | | + | | +- SetCV + | | | + | | +- SetPV + | | | + | | +- HWEnDi + | | + | +- vMain + | | + | +- vStartLEDFlashTasks + | | | + | | +- vLEDFlashTask + | | | | + | | | +- xTaskGetTickCount + | | | | + | | | +- vTaskDelayUntil + | | | | | + | | | | +- vTaskSuspendAll + | | | | | + | | | | +- vListRemove + | | | | | + | | | | +- vListInsert + | | | | | + | | | | +- xTaskResumeAll + | | | | | + | | | | +- vListRemove (see above) + | | | | | + | | | | +- vListInsertEnd + | | | | | + | | | | +- vTaskIncrementTick + | | | | | + | | | | +- vListRemove (see above) + | | | | | + | | | | +- vListInsertEnd (see above) + | | | | + | | | +- vParTestToggleLED + | | | | + | | | +- Byte1_NegBit + | | | | + | | | +- Byte1_GetMsk + | | | + | | +- xTaskCreate + | | | + | | +- prvAllocateTCBAndStack + | | | | + | | | +- pvPortMalloc + | | | | | + | | | | +- vTaskSuspendAll (see above) + | | | | | + | | | | +- xTaskResumeAll (see above) + | | | | + | | | +- vPortFree + | | | | + | | | +- memset + | | | + | | +- prvInitialiseTCBVariables + | | | | + | | | +- strncpy + | | | | + | | | +- vListInitialiseItem + | | | + | | +- pxPortInitialiseStack + | | | + | | +- prvInitialiseTaskLists + | | | | + | | | +- vListInitialise + | | | | + | | | +- vListInitialiseItem (see above) + | | | + | | +- vListInsertEnd (see above) + | | + | +- vStartPolledQueueTasks + | | | + | | +- xQueueCreate + | | | | + | | | +- pvPortMalloc (see above) + | | | | + | | | +- vListInitialise (see above) + | | | | + | | | +- vPortFree (see above) + | | | + | | +- vPolledQueueConsumer + | | | | + | | | +- xQueueReceive + | | | | | + | | | | +- vTaskSuspendAll (see above) + | | | | | + | | | | +- prvIsQueueEmpty + | | | | | + | | | | +- vTaskPlaceOnEventList + | | | | | | + | | | | | +- vListInsert (see above) + | | | | | | + | | | | | +- vListRemove (see above) + | | | | | + | | | | +- prvUnlockQueue + | | | | | | + | | | | | +- xTaskRemoveFromEventList + | | | | | | + | | | | | +- vListRemove (see above) + | | | | | | + | | | | | +- vListInsertEnd (see above) + | | | | | + | | | | +- xTaskResumeAll (see above) + | | | | | + | | | | +- memcpy + | | | | + | | | +- uxQueueMessagesWaiting + | | | | + | | | +- vTaskDelay + | | | | + | | | +- vTaskSuspendAll (see above) + | | | | + | | | +- vListRemove (see above) + | | | | + | | | +- vListInsert (see above) + | | | | + | | | +- xTaskResumeAll (see above) + | | | + | | +- xTaskCreate (see above) + | | | + | | +- vPolledQueueProducer + | | | + | | +- xQueueSend + | | | | + | | | +- vTaskSuspendAll (see above) + | | | | + | | | +- prvIsQueueFull + | | | | + | | | +- vTaskPlaceOnEventList (see above) + | | | | + | | | +- prvUnlockQueue (see above) + | | | | + | | | +- xTaskResumeAll (see above) + | | | | + | | | +- memcpy (see above) + | | | + | | +- vTaskDelay (see above) + | | + | +- vStartDynamicPriorityTasks + | | | + | | +- xQueueCreate (see above) + | | | + | | +- vContinuousIncrementTask + | | | | + | | | +- uxTaskPriorityGet + | | | | + | | | +- vTaskPrioritySet + | | | | | + | | | | +- vListRemove (see above) + | | | | | + | | | | +- vListInsertEnd (see above) + | | | | + | | | +- _LINC + | | | + | | +- xTaskCreate (see above) + | | | + | | +- vLimitedIncrementTask + | | | | + | | | +- _LINC (see above) + | | | | + | | | +- _LCMP_P + | | | | + | | | +- vTaskSuspend + | | | | + | | | +- vListRemove (see above) + | | | | + | | | +- vListInsertEnd (see above) + | | | + | | +- vCounterControlTask + | | | | + | | | +- vTaskSuspend (see above) + | | | | + | | | +- vTaskResume + | | | | | + | | | | +- vListRemove (see above) + | | | | | + | | | | +- vListInsertEnd (see above) + | | | | + | | | +- vTaskDelay (see above) + | | | | + | | | +- vTaskSuspendAll (see above) + | | | | + | | | +- xTaskResumeAll (see above) + | | | + | | +- vQueueSendWhenSuspendedTask + | | | | + | | | +- vTaskSuspendAll (see above) + | | | | + | | | +- xQueueSend (see above) + | | | | + | | | +- xTaskResumeAll (see above) + | | | | + | | | +- vTaskDelay (see above) + | | | | + | | | +- _LINC (see above) + | | | + | | +- vQueueReceiveWhenSuspendedTask + | | | + | | +- vTaskSuspendAll (see above) + | | | + | | +- xQueueReceive (see above) + | | | + | | +- xTaskResumeAll (see above) + | | | + | | +- _LINC (see above) + | | + | +- vErrorChecks + | | | + | | +- xTaskGetTickCount (see above) + | | | + | | +- vTaskDelayUntil (see above) + | | | + | | +- prvCheckOtherTasksAreStillRunning + | | | | + | | | +- xArePollingQueuesStillRunning + | | | | + | | | +- xAreDynamicPriorityTasksStillRunning + | | | + | | +- _LCMP + | | | + | | +- vParTestToggleLED (see above) + | | + | +- xTaskCreate (see above) + | | + | +- vButtonTask + | | | + | | +- xQueueCreate (see above) + | | | + | | +- ButtonInterrupt_Enable + | | | + | | +- xQueueReceive (see above) + | | | + | | +- vParTestToggleLED (see above) + | | + | +- vTaskStartScheduler + | | + | +- prvIdleTask + | | | + | | +- prvCheckTasksWaitingTermination + | | | + | | +- vApplicationIdleHook + | | | + | | +- _LNEG + | | | + | | +- _LDIVS + | | | | + | | | +- _NEG_P + | | | | + | | | +- _lDivMod + | | | + | | +- _LCMP_P (see above) + | | + | +- xTaskCreate (see above) + | | + | +- xPortStartScheduler + | | + | +- xBankedStartScheduler + | | + | +- prvSetupTimerInterrupt + | | + | +- TickTimer_SetFreqHz + | | | + | | +- _LDIVU + | | | | + | | | +- _lDivMod (see above) + | | | + | | +- PE_Timer_LngHi1 + | | | | + | | | +- _LCMP (see above) + | | | + | | +- SetCV (see above) + | | + | +- TickTimer_Enable + | | + | +- HWEnDi (see above) + | + +- _EntryPoint + | + +- _Startup + | + +- Init + + _vect + | + +- Cpu_Interrupt + | + +- vButtonPush + | | + | +- xQueueSendFromISR + | | | + | | +- memcpy (see above) + | | | + | | +- xTaskRemoveFromEventList (see above) + | | + | +- vTaskSwitchContext + | + +- vPortTickInterrupt + | | + | +- vTaskIncrementTick (see above) + | | + | +- vTaskSwitchContext (see above) + | + +- vPortYield + | | + | +- vTaskSwitchContext (see above) + | + +- _EntryPoint (see above) + +********************************************************************************************* +STATISTIC SECTION +--------------------------------------------------------------------------------------------- + +ExeFile: +-------- +Number of blocks to be downloaded: 9 +Total size of all blocks to be downloaded: 5218 + diff --git a/20080212/Demo/HCS12_CodeWarrior_small/bin/SofTec.map b/20080212/Demo/HCS12_CodeWarrior_small/bin/SofTec.map new file mode 100644 index 000000000..d221a8792 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_small/bin/SofTec.map @@ -0,0 +1,2175 @@ + +PROGRAM "E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_small\bin\SofTec.abs" + +********************************************************************************************* +TARGET SECTION +--------------------------------------------------------------------------------------------- +Processor : Motorola HC12 +Memory Model: SMALL +File Format : ELF\Dwarf 2.0 +Linker : SmartLinker V-5.0.22 Build 4047, Feb 17 2004 + +********************************************************************************************* +FILE SECTION +--------------------------------------------------------------------------------------------- +Start12.c.o Model: SMALL, Lang: ANSI-C +STRING.C.o (ansisi.lib) Model: SMALL, Lang: ANSI-C +rtshc12.c.o (ansisi.lib) Model: SMALL, Lang: ANSI-C +tasks.c.o Model: SMALL, Lang: ANSI-C +queue.c.o Model: SMALL, Lang: ANSI-C +list.c.o Model: SMALL, Lang: ANSI-C +port.c.o Model: SMALL, Lang: ANSI-C +flash.c.o Model: SMALL, Lang: ANSI-C +main.c.o Model: SMALL, Lang: ANSI-C +heap_1.c.o Model: SMALL, Lang: ANSI-C +ParTest.c.o Model: SMALL, Lang: ANSI-C +Cpu.C.o Model: SMALL, Lang: ANSI-C +Byte1.C.o Model: SMALL, Lang: ANSI-C +TickTimer.C.o Model: SMALL, Lang: ANSI-C +IO_Map.C.o Model: SMALL, Lang: ANSI-C +PE_Timer.C.o Model: SMALL, Lang: ANSI-C +Vectors.c.o Model: SMALL, Lang: ANSI-C +RTOSDemo.C.o Model: SMALL, Lang: ANSI-C +PollQ.c.o Model: SMALL, Lang: ANSI-C +dynamic.c.o Model: SMALL, Lang: ANSI-C +ButtonInterrupt.C.o Model: SMALL, Lang: ANSI-C + +********************************************************************************************* +STARTUP SECTION +--------------------------------------------------------------------------------------------- +Entry point: 0xC000 (_EntryPoint) +_startupData is allocated at 0xC076 and uses 23 Bytes +extern struct _tagStartup { + unsigned flags 0 + _PFunc main 0xCE77 (main) + long stackOffset 0xFED + unsigned nofZeroOut 1 + _Range pZeroOut 0x800 1982 + _Copy *toCopyDownBeg 0xD3C4 + int nofLibInits 0 + _LibInit *libInits 0xC091 + int nofInitBodies 0 + _Cpp *initBodies 0xC093 + int nofFiniBodies 0 + _Cpp *finiBodies 0xC093 +} _startupData; + +********************************************************************************************* +SECTION-ALLOCATION SECTION +Section Name Size Type From To Segment +--------------------------------------------------------------------------------------------- +.data 1 R/W 0x800 0x800 RAM +.init 118 R 0xC000 0xC075 ROM_C000 +.startData 29 R 0xC076 0xC092 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+--------------------------------------------------------------------------------------------- + +********************************************************************************************* +OBJECT-ALLOCATION SECTION + Name Module Addr hSize dSize Ref Section RLIB +--------------------------------------------------------------------------------------------- +MODULE: -- Start12.c.o -- +- PROCEDURES: + Init C153 29 41 1 .text + _Startup C17C 10 16 1 .text +- VARIABLES: + _startupData C076 17 23 6 .startData +MODULE: -- STRING.C.o (ansisi.lib) -- +- PROCEDURES: + _memcpy_8bitCount C18C 1C 28 3 .text + memset C1A8 1E 30 1 .text + strncpy C1C6 2D 45 1 .text +- VARIABLES: +MODULE: -- rtshc12.c.o (ansisi.lib) -- +- PROCEDURES: + _LCMP D199 19 25 2 RUNTIME + _LCMP_P D1B2 15 21 2 RUNTIME + _LNEG D1C7 D 13 1 RUNTIME + _LINC D1D4 5 5 4 RUNTIME + _lDivMod D1D9 E3 227 3 RUNTIME + _LDIVU D2BC E 14 1 RUNTIME + _NEG_P D2CA F 15 4 RUNTIME + _LDIVS D2D9 35 53 1 RUNTIME +- VARIABLES: +MODULE: -- tasks.c.o -- +- PROCEDURES: + xTaskCreate C1F3 CE 206 11 .text + vTaskDelayUntil C2C1 74 116 3 .text + vTaskDelay C335 46 70 4 .text + uxTaskPriorityGet C37B 26 38 1 .text + vTaskPrioritySet C3A1 69 105 2 .text + vTaskSuspend C40A 44 68 3 .text + vTaskResume C44E 59 89 3 .text + vTaskStartScheduler C4A7 30 48 1 .text + vTaskSuspendAll C4D7 13 19 11 .text + xTaskResumeAll C4EA 9F 159 13 .text + xTaskGetTickCount C589 17 23 2 .text + vTaskIncrementTick C5A0 81 129 2 .text + vTaskSwitchContext C621 5B 91 3 .text + vTaskPlaceOnEventList C67C 3E 62 2 .text + xTaskRemoveFromEventList C6BA 65 101 3 .text + prvIdleTask C71F 10 16 1 .text + prvInitialiseTCBVariables C72F 4A 74 1 .text + prvInitialiseTaskLists C779 37 55 1 .text + prvCheckTasksWaitingTermination C7B0 1 1 1 .text + prvAllocateTCBAndStack C7B1 39 57 1 .text +- VARIABLES: + STRING.IDLE.2 C093 5 5 1 .rodata1 + pxCurrentTCB 801 2 2 29 .bss + uxCurrentNumberOfTasks 803 1 1 3 .bss + xTickCount 804 2 2 14 .bss + uxTopUsedPriority 806 1 1 2 .bss + uxTopReadyPriority 807 1 1 15 .bss + xSchedulerRunning 808 1 1 3 .bss + uxSchedulerSuspended 809 1 1 6 .bss + uxMissedTicks 80A 1 1 4 .bss + uxTaskNumber.1 80B 1 1 2 .bss + pxReadyTasksLists 80C 3C 60 11 .bss + xDelayedTaskList1 848 F 15 2 .bss + xDelayedTaskList2 857 F 15 2 .bss + pxDelayedTaskList 866 2 2 8 .bss + pxOverflowDelayedTaskList 868 2 2 6 .bss + xPendingReadyList 86A F 15 4 .bss + xSuspendedTaskList 879 F 15 2 .bss +MODULE: -- queue.c.o -- +- PROCEDURES: + xQueueCreate C7EA 76 118 3 .text + xQueueSend C860 C9 201 3 .text + xQueueSendFromISR C929 58 88 1 .text + xQueueReceive C981 C3 195 4 .text + uxQueueMessagesWaiting CA44 1B 27 1 .text + prvUnlockQueue CA5F 6F 111 4 .text + prvIsQueueEmpty CACE 21 33 1 .text + prvIsQueueFull CAEF 24 36 1 .text +- VARIABLES: +MODULE: -- list.c.o -- +- PROCEDURES: + vListInitialise CB13 1F 31 7 .text + vListInitialiseItem CB32 7 7 3 .text + vListInsertEnd CB39 25 37 7 .text + vListInsert CB5E 54 84 4 .text + vListRemove CBB2 23 35 13 .text +- VARIABLES: +MODULE: -- port.c.o -- +- PROCEDURES: + pxPortInitialiseStack CBD5 2B 43 1 .text + prvSetupTimerInterrupt CC00 9 9 1 .text + xPortStartScheduler CC09 4 4 1 .text + xBankedStartScheduler C0E1 F 15 1 NON_BANKED + vPortYield C0F0 16 22 1 NON_BANKED + vPortTickInterrupt C106 1D 29 1 NON_BANKED +- VARIABLES: + uxCriticalNesting 800 1 1 91 .data +MODULE: -- flash.c.o -- +- PROCEDURES: + vStartLEDFlashTasks CC0D 2E 46 1 .text + vLEDFlashTask CC3B 52 82 1 .text +- VARIABLES: + STRING.LEDx.1 C098 5 5 1 .rodata1 + uxFlashTaskNumber 888 1 1 2 .bss +MODULE: -- main.c.o -- +- PROCEDURES: + vMain CC8D 42 66 1 .text + vErrorChecks CCCF 35 53 1 .text + prvCheckOtherTasksAreStillRunning CD04 26 38 1 .text + vApplicationIdleHook CD2A 73 115 1 .text + vButtonTask CD9D 4F 79 1 .text + vButtonPush C123 2F 47 1 NON_BANKED +- VARIABLES: + STRING.Check.1 C09D 6 6 1 .rodata1 + STRING.Button.2 C0A3 7 7 1 .rodata1 + xLocalError 889 1 1 3 .bss + uxValToSend.3 88A 1 1 2 .bss + xButtonQueue 88B 2 2 3 .bss +MODULE: -- heap_1.c.o -- +- PROCEDURES: + pvPortMalloc CDEC 2D 45 4 .text + vPortFree CE19 1 1 2 .text +- VARIABLES: + xNextFreeByte 88D 2 2 4 .bss + xHeap 88F 704 1796 1 .bss +MODULE: -- ParTest.c.o -- +- PROCEDURES: + vParTestToggleLED CE1A 13 19 4 .text +- VARIABLES: +MODULE: -- Cpu.C.o -- +- PROCEDURES: + _EntryPoint C000 2E 46 1 .init + PE_low_level_init C02E 48 72 1 .init + Cpu_Interrupt C152 1 1 60 NON_BANKED +- VARIABLES: +MODULE: -- Byte1.C.o -- +- PROCEDURES: + Byte1_GetMsk D3AD D 13 1 Byte1_CODE + Byte1_NegBit D3BA A 10 1 Byte1_CODE +- VARIABLES: + Byte1_Table FB3 8 8 1 Byte1_DATA +MODULE: -- TickTimer.C.o -- +- PROCEDURES: + SetCV D30E B 11 2 TickTimer_CODE + SetPV D319 9 9 1 TickTimer_CODE + HWEnDi D322 11 17 2 TickTimer_CODE + TickTimer_Enable D333 E 14 1 TickTimer_CODE + TickTimer_SetFreqHz D341 4E 78 1 TickTimer_CODE + TickTimer_Init D38F 14 20 1 TickTimer_CODE +- VARIABLES: + EnUser FBB 1 1 4 TickTimer_DATA + CmpHighVal FBC 2 2 2 TickTimer_DATA +MODULE: -- IO_Map.C.o -- +- PROCEDURES: +- VARIABLES: + _ARMCOP 3F 1 1 0 .abs_section_3f + _ATDDIEN 8D 1 1 0 .abs_section_8d + _ATDSTAT0 86 1 1 0 .abs_section_86 + _ATDSTAT1 8B 1 1 0 .abs_section_8b + _BDMCCR FF06 1 1 0 .abs_section_ff06 + _BDMINR FF07 1 1 0 .abs_section_ff07 + _BDMSTS FF01 1 1 0 .abs_section_ff01 + _BKP0H 2B 1 1 0 .abs_section_2b + _BKP0L 2C 1 1 0 .abs_section_2c + _BKP0X 2A 1 1 0 .abs_section_2a + _BKP1H 2E 1 1 0 .abs_section_2e + _BKP1L 2F 1 1 0 .abs_section_2f + _BKP1X 2D 1 1 0 .abs_section_2d + _BKPCT0 28 1 1 0 .abs_section_28 + _BKPCT1 29 1 1 0 .abs_section_29 + _CANBTR0 142 1 1 0 .abs_section_142 + _CANBTR1 143 1 1 0 .abs_section_143 + _CANCTL0 140 1 1 0 .abs_section_140 + _CANCTL1 141 1 1 0 .abs_section_141 + _CANIDAC 14B 1 1 0 .abs_section_14b + _CANIDAR0 150 1 1 0 .abs_section_150 + _CANIDAR1 151 1 1 0 .abs_section_151 + _CANIDAR2 152 1 1 0 .abs_section_152 + _CANIDAR3 153 1 1 0 .abs_section_153 + _CANIDAR4 158 1 1 0 .abs_section_158 + _CANIDAR5 159 1 1 0 .abs_section_159 + _CANIDAR6 15A 1 1 0 .abs_section_15a + _CANIDAR7 15B 1 1 0 .abs_section_15b + _CANIDMR0 154 1 1 0 .abs_section_154 + _CANIDMR1 155 1 1 0 .abs_section_155 + _CANIDMR2 156 1 1 0 .abs_section_156 + _CANIDMR3 157 1 1 0 .abs_section_157 + _CANIDMR4 15C 1 1 0 .abs_section_15c + _CANIDMR5 15D 1 1 0 .abs_section_15d + _CANIDMR6 15E 1 1 0 .abs_section_15e + _CANIDMR7 15F 1 1 0 .abs_section_15f + _CANRFLG 144 1 1 0 .abs_section_144 + _CANRIER 145 1 1 0 .abs_section_145 + _CANRXDLR 16C 1 1 0 .abs_section_16c + _CANRXDSR0 164 1 1 0 .abs_section_164 + _CANRXDSR1 165 1 1 0 .abs_section_165 + _CANRXDSR2 166 1 1 0 .abs_section_166 + _CANRXDSR3 167 1 1 0 .abs_section_167 + _CANRXDSR4 168 1 1 0 .abs_section_168 + _CANRXDSR5 169 1 1 0 .abs_section_169 + _CANRXDSR6 16A 1 1 0 .abs_section_16a + _CANRXDSR7 16B 1 1 0 .abs_section_16b + _CANRXERR 14E 1 1 0 .abs_section_14e + _CANRXIDR0 160 1 1 0 .abs_section_160 + _CANRXIDR1 161 1 1 0 .abs_section_161 + _CANRXIDR2 162 1 1 0 .abs_section_162 + _CANRXIDR3 163 1 1 0 .abs_section_163 + _CANTAAK 149 1 1 0 .abs_section_149 + _CANTARQ 148 1 1 0 .abs_section_148 + _CANTBSEL 14A 1 1 0 .abs_section_14a + _CANTFLG 146 1 1 0 .abs_section_146 + _CANTIER 147 1 1 0 .abs_section_147 + _CANTXDLR 17C 1 1 0 .abs_section_17c + _CANTXDSR0 174 1 1 0 .abs_section_174 + _CANTXDSR1 175 1 1 0 .abs_section_175 + _CANTXDSR2 176 1 1 0 .abs_section_176 + _CANTXDSR3 177 1 1 0 .abs_section_177 + _CANTXDSR4 178 1 1 0 .abs_section_178 + _CANTXDSR5 179 1 1 0 .abs_section_179 + _CANTXDSR6 17A 1 1 0 .abs_section_17a + _CANTXDSR7 17B 1 1 0 .abs_section_17b + _CANTXERR 14F 1 1 0 .abs_section_14f + _CANTXIDR0 170 1 1 0 .abs_section_170 + _CANTXIDR1 171 1 1 0 .abs_section_171 + _CANTXIDR2 172 1 1 0 .abs_section_172 + _CANTXIDR3 173 1 1 0 .abs_section_173 + _CANTXTBPR 17F 1 1 0 .abs_section_17f + _CFORC 41 1 1 0 .abs_section_41 + _CLKSEL 39 1 1 3 .abs_section_39 + _COPCTL 3C 1 1 0 .abs_section_3c + _CRGFLG 37 1 1 1 .abs_section_37 + _CRGINT 38 1 1 0 .abs_section_38 + _CTCTL 3E 1 1 0 .abs_section_3e + _CTFLG 36 1 1 0 .abs_section_36 + _DDRAD 272 1 1 0 .abs_section_272 + _DDRE 9 1 1 0 .abs_section_9 + _DDRJ 26A 1 1 0 .abs_section_26a + _DDRK 33 1 1 0 .abs_section_33 + _DDRM 252 1 1 0 .abs_section_252 + _DDRP 25A 1 1 1 .abs_section_25a + _DDRS 24A 1 1 0 .abs_section_24a + _DDRT 242 1 1 0 .abs_section_242 + _EBICTL E 1 1 0 .abs_section_e + _FCLKDIV 100 1 1 0 .abs_section_100 + _FCMD 106 1 1 0 .abs_section_106 + _FCNFG 103 1 1 0 .abs_section_103 + _FPROT 104 1 1 0 .abs_section_104 + _FSEC 101 1 1 0 .abs_section_101 + _FSTAT 105 1 1 0 .abs_section_105 + _HPRIO 1F 1 1 0 .abs_section_1f + _INITEE 12 1 1 0 .abs_section_12 + _INITRG 11 1 1 0 .abs_section_11 + _INITRM 10 1 1 1 .abs_section_10 + _INTCR 1E 1 1 1 .abs_section_1e + _ITCR 15 1 1 0 .abs_section_15 + _ITEST 16 1 1 0 .abs_section_16 + _MEMSIZ0 1C 1 1 0 .abs_section_1c + _MEMSIZ1 1D 1 1 0 .abs_section_1d + _MISC 13 1 1 1 .abs_section_13 + _MODE B 1 1 0 .abs_section_b + _MODRR 247 1 1 0 .abs_section_247 + _MTST0 14 1 1 0 .abs_section_14 + _MTST1 17 1 1 0 .abs_section_17 + _OC7D 43 1 1 0 .abs_section_43 + _OC7M 42 1 1 0 .abs_section_42 + _PACTL 60 1 1 0 .abs_section_60 + _PAFLG 61 1 1 0 .abs_section_61 + _PARTIDH 1A 1 1 0 .abs_section_1a + _PARTIDL 1B 1 1 0 .abs_section_1b + _PEAR A 1 1 0 .abs_section_a + _PERAD 274 1 1 0 .abs_section_274 + _PERJ 26C 1 1 0 .abs_section_26c + _PERM 254 1 1 0 .abs_section_254 + _PERP 25C 1 1 1 .abs_section_25c + _PERS 24C 1 1 0 .abs_section_24c + _PERT 244 1 1 0 .abs_section_244 + _PIEJ 26E 1 1 0 .abs_section_26e + _PIEP 25E 1 1 2 .abs_section_25e + _PIFJ 26F 1 1 0 .abs_section_26f + _PIFP 25F 1 1 2 .abs_section_25f + _PLLCTL 3A 1 1 3 .abs_section_3a + _PORTAD0 8F 1 1 0 .abs_section_8f + _PORTE 8 1 1 0 .abs_section_8 + _PORTK 32 1 1 0 .abs_section_32 + _PPAGE 30 1 1 0 .abs_section_30 + _PPSAD 275 1 1 0 .abs_section_275 + _PPSJ 26D 1 1 0 .abs_section_26d + _PPSM 255 1 1 0 .abs_section_255 + _PPSP 25D 1 1 1 .abs_section_25d + _PPSS 24D 1 1 0 .abs_section_24d + _PPST 245 1 1 0 .abs_section_245 + _PTAD 270 1 1 0 .abs_section_270 + _PTIAD 271 1 1 0 .abs_section_271 + _PTIJ 269 1 1 0 .abs_section_269 + _PTIM 251 1 1 0 .abs_section_251 + _PTIP 259 1 1 0 .abs_section_259 + _PTIS 249 1 1 0 .abs_section_249 + _PTIT 241 1 1 0 .abs_section_241 + _PTJ 268 1 1 0 .abs_section_268 + _PTM 250 1 1 0 .abs_section_250 + _PTP 258 1 1 0 .abs_section_258 + _PTS 248 1 1 0 .abs_section_248 + _PTT 240 1 1 0 .abs_section_240 + _PUCR C 1 1 0 .abs_section_c + _PWMCAE E4 1 1 0 .abs_section_e4 + _PWMCLK E2 1 1 0 .abs_section_e2 + _PWMCTL E5 1 1 1 .abs_section_e5 + _PWME E0 1 1 0 .abs_section_e0 + _PWMPOL E1 1 1 0 .abs_section_e1 + _PWMPRCLK E3 1 1 0 .abs_section_e3 + _PWMSCLA E8 1 1 0 .abs_section_e8 + _PWMSCLB E9 1 1 0 .abs_section_e9 + _PWMSDN FE 1 1 1 .abs_section_fe + _RDRAD 273 1 1 0 .abs_section_273 + _RDRIV D 1 1 0 .abs_section_d + _RDRJ 26B 1 1 0 .abs_section_26b + _RDRM 253 1 1 0 .abs_section_253 + _RDRP 25B 1 1 0 .abs_section_25b + _RDRS 24B 1 1 0 .abs_section_24b + _RDRT 243 1 1 0 .abs_section_243 + _REFDV 35 1 1 1 .abs_section_35 + _RTICTL 3B 1 1 0 .abs_section_3b + _SCICR1 CA 1 1 0 .abs_section_ca + _SCICR2 CB 1 1 0 .abs_section_cb + _SCIDRH CE 1 1 0 .abs_section_ce + _SCIDRL CF 1 1 0 .abs_section_cf + _SCISR1 CC 1 1 0 .abs_section_cc + _SCISR2 CD 1 1 0 .abs_section_cd + _SPIBR DA 1 1 0 .abs_section_da + _SPICR1 D8 1 1 0 .abs_section_d8 + _SPICR2 D9 1 1 0 .abs_section_d9 + _SPIDR DD 1 1 0 .abs_section_dd + _SPISR DB 1 1 0 .abs_section_db + _SYNR 34 1 1 1 .abs_section_34 + _TCTL1 48 1 1 1 .abs_section_48 + _TCTL2 49 1 1 1 .abs_section_49 + _TCTL3 4A 1 1 0 .abs_section_4a + _TCTL4 4B 1 1 0 .abs_section_4b + _TFLG1 4E 1 1 2 .abs_section_4e + _TFLG2 4F 1 1 0 .abs_section_4f + _TIE 4C 1 1 3 .abs_section_4c + _TIOS 40 1 1 1 .abs_section_40 + _TSCR1 46 1 1 3 .abs_section_46 + _TSCR2 4D 1 1 5 .abs_section_4d + _TTOV 47 1 1 1 .abs_section_47 + _WOMM 256 1 1 0 .abs_section_256 + _WOMS 24E 1 1 0 .abs_section_24e + _ATDCTL23 82 2 2 0 .abs_section_82 + _ATDCTL45 84 2 2 0 .abs_section_84 + _ATDDR0 90 2 2 0 .abs_section_90 + _ATDDR1 92 2 2 0 .abs_section_92 + _ATDDR2 94 2 2 0 .abs_section_94 + _ATDDR3 96 2 2 0 .abs_section_96 + _ATDDR4 98 2 2 0 .abs_section_98 + _ATDDR5 9A 2 2 0 .abs_section_9a + _ATDDR6 9C 2 2 0 .abs_section_9c + _ATDDR7 9E 2 2 0 .abs_section_9e + _DDRAB 2 2 2 1 .abs_section_2 + _PACNT 62 2 2 0 .abs_section_62 + _PORTAB 0 2 2 3 .abs_section_0 + _PWMCNT01 EC 2 2 0 .abs_section_ec + _PWMCNT23 EE 2 2 0 .abs_section_ee + _PWMCNT45 F0 2 2 0 .abs_section_f0 + _PWMDTY01 F8 2 2 0 .abs_section_f8 + _PWMDTY23 FA 2 2 0 .abs_section_fa + _PWMDTY45 FC 2 2 0 .abs_section_fc + _PWMPER01 F2 2 2 0 .abs_section_f2 + _PWMPER23 F4 2 2 0 .abs_section_f4 + _PWMPER45 F6 2 2 0 .abs_section_f6 + _SCIBD C8 2 2 0 .abs_section_c8 + _TC0 50 2 2 1 .abs_section_50 + _TC1 52 2 2 0 .abs_section_52 + _TC2 54 2 2 0 .abs_section_54 + _TC3 56 2 2 0 .abs_section_56 + _TC4 58 2 2 0 .abs_section_58 + _TC5 5A 2 2 0 .abs_section_5a + _TC6 5C 2 2 0 .abs_section_5c + _TC7 5E 2 2 1 .abs_section_5e + _TCNT 44 2 2 0 .abs_section_44 +MODULE: -- PE_Timer.C.o -- +- PROCEDURES: + PE_Timer_LngHi1 CE2D 4A 74 1 .text +- VARIABLES: +MODULE: -- Vectors.c.o -- +- PROCEDURES: +- VARIABLES: + _vect FF80 80 128 0 .abs_section_ff80 +MODULE: -- RTOSDemo.C.o -- +- PROCEDURES: + main CE77 8 8 0 .text +- VARIABLES: +MODULE: -- PollQ.c.o -- +- PROCEDURES: + vStartPolledQueueTasks CE7F 42 66 1 .text + vPolledQueueProducer CEC1 4D 77 1 .text + vPolledQueueConsumer CF0E 59 89 1 .text + xArePollingQueuesStillRunning CF67 15 21 1 .text +- VARIABLES: + STRING.QConsNB.2 C0AA 8 8 1 .rodata1 + STRING.QProdNB.3 C0B2 8 8 1 .rodata1 + xPollingConsumerCount F93 1 1 3 .bss + xPollingProducerCount F94 1 1 3 .bss + xPolledQueue.1 F95 2 2 3 .bss +MODULE: -- dynamic.c.o -- +- PROCEDURES: + vStartDynamicPriorityTasks CF7C 7C 124 1 .text + vLimitedIncrementTask CFF8 26 38 1 .text + vContinuousIncrementTask D01E 35 53 1 .text + vCounterControlTask D053 98 152 3 .text + vQueueSendWhenSuspendedTask D0EB 34 52 1 .text + vQueueReceiveWhenSuspendedTask D11F 4F 79 1 .text + xAreDynamicPriorityTasksStillRunning D16E 2B 43 1 .text +- VARIABLES: + STRING.CNT_INC.1 C0BA 8 8 1 .rodata1 + STRING.LIM_INC.2 C0C2 8 8 1 .rodata1 + STRING.C_CTRL.3 C0CA 7 7 1 .rodata1 + STRING.SUSP_TX.4 C0D1 8 8 1 .rodata1 + STRING.SUSP_RX.5 C0D9 8 8 1 .rodata1 + usCheckVariable F97 2 2 3 .bss + xSuspendedQueueSendError F99 1 1 2 .bss + xSuspendedQueueReceiveError F9A 1 1 3 .bss + ulValueToSend.6 F9B 4 4 5 .bss + ulExpectedValue.7 F9F 4 4 6 .bss + usLastTaskCheck.9 FA3 2 2 2 .bss + xContinousIncrementHandle FA5 2 2 5 .bss + xLimitedIncrementHandle FA7 2 2 2 .bss + ulCounter FA9 4 4 10 .bss + ulReceivedValue.8 FAD 4 4 3 .bss + xSuspendedTestQueue FB1 2 2 3 .common +MODULE: -- ButtonInterrupt.C.o -- +- PROCEDURES: + ButtonInterrupt_Enable D3A3 A 10 1 ButtonInterrupt_CODE +- VARIABLES: + +********************************************************************************************* +MODULE STATISTIC + Name Data Code Const +--------------------------------------------------------------------------------------------- + Start12.c.o 0 57 0 + STRING.C.o (ansisi.lib) 0 103 0 + rtshc12.c.o (ansisi.lib) 0 373 0 + tasks.c.o 135 1527 5 + queue.c.o 0 809 0 + list.c.o 0 194 0 + port.c.o 1 122 0 + flash.c.o 1 128 5 + main.c.o 4 398 13 + heap_1.c.o 1798 46 0 + ParTest.c.o 0 19 0 + Cpu.C.o 0 119 0 + Byte1.C.o 8 23 0 + TickTimer.C.o 3 149 0 + IO_Map.C.o 256 0 0 + PE_Timer.C.o 0 74 0 + Vectors.c.o 0 0 128 + RTOSDemo.C.o 0 8 0 + PollQ.c.o 4 253 16 + dynamic.c.o 28 541 39 + ButtonInterrupt.C.o 0 10 0 + other 48 29 19 + +********************************************************************************************* +SECTION USE IN OBJECT-ALLOCATION SECTION +--------------------------------------------------------------------------------------------- +SECTION: ".text" + Init _Startup _memcpy_8bitCount memset strncpy xTaskCreate vTaskDelayUntil + vTaskDelay uxTaskPriorityGet vTaskPrioritySet vTaskSuspend vTaskResume + vTaskStartScheduler vTaskSuspendAll xTaskResumeAll xTaskGetTickCount + vTaskIncrementTick vTaskSwitchContext vTaskPlaceOnEventList + xTaskRemoveFromEventList prvIdleTask prvInitialiseTCBVariables + prvInitialiseTaskLists prvCheckTasksWaitingTermination prvAllocateTCBAndStack + xQueueCreate xQueueSend xQueueSendFromISR xQueueReceive + uxQueueMessagesWaiting prvUnlockQueue prvIsQueueEmpty prvIsQueueFull + vListInitialise vListInitialiseItem vListInsertEnd vListInsert vListRemove + pxPortInitialiseStack prvSetupTimerInterrupt xPortStartScheduler + vStartLEDFlashTasks vLEDFlashTask vMain vErrorChecks + prvCheckOtherTasksAreStillRunning vApplicationIdleHook vButtonTask + pvPortMalloc vPortFree vParTestToggleLED PE_Timer_LngHi1 main + vStartPolledQueueTasks vPolledQueueProducer vPolledQueueConsumer + xArePollingQueuesStillRunning vStartDynamicPriorityTasks + vLimitedIncrementTask vContinuousIncrementTask vCounterControlTask + vQueueSendWhenSuspendedTask vQueueReceiveWhenSuspendedTask + xAreDynamicPriorityTasksStillRunning +SECTION: ".data" + uxCriticalNesting +SECTION: ".bss" + pxCurrentTCB uxCurrentNumberOfTasks xTickCount uxTopUsedPriority + uxTopReadyPriority xSchedulerRunning uxSchedulerSuspended uxMissedTicks + uxTaskNumber.1 pxReadyTasksLists xDelayedTaskList1 xDelayedTaskList2 + pxDelayedTaskList pxOverflowDelayedTaskList xPendingReadyList + xSuspendedTaskList uxFlashTaskNumber xLocalError uxValToSend.3 xButtonQueue + xNextFreeByte xHeap xPollingConsumerCount xPollingProducerCount + xPolledQueue.1 usCheckVariable xSuspendedQueueSendError + xSuspendedQueueReceiveError ulValueToSend.6 ulExpectedValue.7 + usLastTaskCheck.9 xContinousIncrementHandle xLimitedIncrementHandle ulCounter + ulReceivedValue.8 +SECTION: ".init" + _EntryPoint PE_low_level_init +SECTION: ".rodata1" + STRING.IDLE.2 STRING.LEDx.1 STRING.Check.1 STRING.Button.2 STRING.QConsNB.2 + STRING.QProdNB.3 STRING.CNT_INC.1 STRING.LIM_INC.2 STRING.C_CTRL.3 + STRING.SUSP_TX.4 STRING.SUSP_RX.5 +SECTION: "NON_BANKED" + xBankedStartScheduler vPortYield vPortTickInterrupt vButtonPush + Cpu_Interrupt +SECTION: "RUNTIME" + _LCMP _LCMP_P _LNEG _LINC _lDivMod _LDIVU _NEG_P _LDIVS +SECTION: ".common" + xSuspendedTestQueue +SECTION: "TickTimer_CODE" + SetCV SetPV HWEnDi TickTimer_Enable TickTimer_SetFreqHz TickTimer_Init +SECTION: "ButtonInterrupt_CODE" + ButtonInterrupt_Enable +SECTION: "Byte1_CODE" + Byte1_GetMsk Byte1_NegBit +SECTION: "Byte1_DATA" + Byte1_Table +SECTION: "TickTimer_DATA" + EnUser CmpHighVal +SECTION: ".abs_section_3f" + _ARMCOP +SECTION: ".abs_section_8d" + _ATDDIEN +SECTION: ".abs_section_86" + _ATDSTAT0 +SECTION: ".abs_section_8b" + _ATDSTAT1 +SECTION: ".abs_section_ff06" + _BDMCCR +SECTION: ".abs_section_ff07" + _BDMINR +SECTION: ".abs_section_ff01" + _BDMSTS +SECTION: ".abs_section_2b" + _BKP0H +SECTION: ".abs_section_2c" + _BKP0L +SECTION: ".abs_section_2a" + _BKP0X +SECTION: ".abs_section_2e" + _BKP1H +SECTION: ".abs_section_2f" + _BKP1L +SECTION: ".abs_section_2d" + _BKP1X +SECTION: ".abs_section_28" + _BKPCT0 +SECTION: ".abs_section_29" + _BKPCT1 +SECTION: ".abs_section_142" + _CANBTR0 +SECTION: ".abs_section_143" + _CANBTR1 +SECTION: ".abs_section_140" + _CANCTL0 +SECTION: ".abs_section_141" + _CANCTL1 +SECTION: ".abs_section_14b" + _CANIDAC +SECTION: ".abs_section_150" + _CANIDAR0 +SECTION: ".abs_section_151" + _CANIDAR1 +SECTION: ".abs_section_152" + _CANIDAR2 +SECTION: ".abs_section_153" + _CANIDAR3 +SECTION: ".abs_section_158" + _CANIDAR4 +SECTION: ".abs_section_159" + _CANIDAR5 +SECTION: ".abs_section_15a" + _CANIDAR6 +SECTION: ".abs_section_15b" + _CANIDAR7 +SECTION: ".abs_section_154" + _CANIDMR0 +SECTION: ".abs_section_155" + _CANIDMR1 +SECTION: ".abs_section_156" + _CANIDMR2 +SECTION: ".abs_section_157" + _CANIDMR3 +SECTION: ".abs_section_15c" + _CANIDMR4 +SECTION: ".abs_section_15d" + _CANIDMR5 +SECTION: ".abs_section_15e" + _CANIDMR6 +SECTION: ".abs_section_15f" + _CANIDMR7 +SECTION: ".abs_section_144" + _CANRFLG +SECTION: ".abs_section_145" + _CANRIER +SECTION: ".abs_section_16c" + _CANRXDLR +SECTION: ".abs_section_164" + _CANRXDSR0 +SECTION: ".abs_section_165" + _CANRXDSR1 +SECTION: ".abs_section_166" + _CANRXDSR2 +SECTION: ".abs_section_167" + _CANRXDSR3 +SECTION: ".abs_section_168" + _CANRXDSR4 +SECTION: ".abs_section_169" + _CANRXDSR5 +SECTION: ".abs_section_16a" + _CANRXDSR6 +SECTION: ".abs_section_16b" + _CANRXDSR7 +SECTION: ".abs_section_14e" + _CANRXERR +SECTION: ".abs_section_160" + _CANRXIDR0 +SECTION: ".abs_section_161" + _CANRXIDR1 +SECTION: ".abs_section_162" + _CANRXIDR2 +SECTION: ".abs_section_163" + _CANRXIDR3 +SECTION: ".abs_section_149" + _CANTAAK +SECTION: ".abs_section_148" + _CANTARQ +SECTION: ".abs_section_14a" + _CANTBSEL +SECTION: ".abs_section_146" + _CANTFLG +SECTION: ".abs_section_147" + _CANTIER +SECTION: ".abs_section_17c" + _CANTXDLR +SECTION: ".abs_section_174" + _CANTXDSR0 +SECTION: ".abs_section_175" + _CANTXDSR1 +SECTION: ".abs_section_176" + _CANTXDSR2 +SECTION: ".abs_section_177" + _CANTXDSR3 +SECTION: ".abs_section_178" + _CANTXDSR4 +SECTION: ".abs_section_179" + _CANTXDSR5 +SECTION: ".abs_section_17a" + _CANTXDSR6 +SECTION: ".abs_section_17b" + _CANTXDSR7 +SECTION: ".abs_section_14f" + _CANTXERR +SECTION: ".abs_section_170" + _CANTXIDR0 +SECTION: ".abs_section_171" + _CANTXIDR1 +SECTION: ".abs_section_172" + _CANTXIDR2 +SECTION: ".abs_section_173" + _CANTXIDR3 +SECTION: ".abs_section_17f" + _CANTXTBPR +SECTION: ".abs_section_41" + _CFORC +SECTION: ".abs_section_39" + _CLKSEL +SECTION: ".abs_section_3c" + _COPCTL +SECTION: ".abs_section_37" + _CRGFLG +SECTION: ".abs_section_38" + _CRGINT +SECTION: ".abs_section_3e" + _CTCTL +SECTION: ".abs_section_36" + _CTFLG +SECTION: ".abs_section_272" + _DDRAD +SECTION: ".abs_section_9" + _DDRE +SECTION: ".abs_section_26a" + _DDRJ +SECTION: ".abs_section_33" + _DDRK +SECTION: ".abs_section_252" + _DDRM +SECTION: ".abs_section_25a" + _DDRP +SECTION: ".abs_section_24a" + _DDRS +SECTION: ".abs_section_242" + _DDRT +SECTION: ".abs_section_e" + _EBICTL +SECTION: ".abs_section_100" + _FCLKDIV +SECTION: ".abs_section_106" + _FCMD +SECTION: ".abs_section_103" + _FCNFG +SECTION: ".abs_section_104" + _FPROT +SECTION: ".abs_section_101" + _FSEC +SECTION: ".abs_section_105" + _FSTAT +SECTION: ".abs_section_1f" + _HPRIO +SECTION: ".abs_section_12" + _INITEE +SECTION: ".abs_section_11" + _INITRG +SECTION: ".abs_section_10" + _INITRM +SECTION: ".abs_section_1e" + _INTCR +SECTION: ".abs_section_15" + _ITCR +SECTION: ".abs_section_16" + _ITEST +SECTION: ".abs_section_1c" + _MEMSIZ0 +SECTION: ".abs_section_1d" + _MEMSIZ1 +SECTION: ".abs_section_13" + _MISC +SECTION: ".abs_section_b" + _MODE +SECTION: ".abs_section_247" + _MODRR +SECTION: ".abs_section_14" + _MTST0 +SECTION: ".abs_section_17" + _MTST1 +SECTION: ".abs_section_43" + _OC7D +SECTION: ".abs_section_42" + _OC7M +SECTION: ".abs_section_60" + _PACTL +SECTION: ".abs_section_61" + _PAFLG +SECTION: ".abs_section_1a" + _PARTIDH +SECTION: ".abs_section_1b" + _PARTIDL +SECTION: ".abs_section_a" + _PEAR +SECTION: ".abs_section_274" + _PERAD +SECTION: ".abs_section_26c" + _PERJ +SECTION: ".abs_section_254" + _PERM +SECTION: ".abs_section_25c" + _PERP +SECTION: ".abs_section_24c" + _PERS +SECTION: ".abs_section_244" + _PERT +SECTION: ".abs_section_26e" + _PIEJ +SECTION: ".abs_section_25e" + _PIEP +SECTION: ".abs_section_26f" + _PIFJ +SECTION: ".abs_section_25f" + _PIFP +SECTION: ".abs_section_3a" + _PLLCTL +SECTION: ".abs_section_8f" + _PORTAD0 +SECTION: ".abs_section_8" + _PORTE +SECTION: ".abs_section_32" + _PORTK +SECTION: ".abs_section_30" + _PPAGE +SECTION: ".abs_section_275" + _PPSAD +SECTION: ".abs_section_26d" + _PPSJ +SECTION: ".abs_section_255" + _PPSM +SECTION: ".abs_section_25d" + _PPSP +SECTION: ".abs_section_24d" + _PPSS +SECTION: ".abs_section_245" + _PPST +SECTION: ".abs_section_270" + _PTAD +SECTION: ".abs_section_271" + _PTIAD +SECTION: ".abs_section_269" + _PTIJ +SECTION: ".abs_section_251" + _PTIM +SECTION: ".abs_section_259" + _PTIP +SECTION: ".abs_section_249" + _PTIS +SECTION: ".abs_section_241" + _PTIT +SECTION: ".abs_section_268" + _PTJ +SECTION: ".abs_section_250" + _PTM +SECTION: ".abs_section_258" + _PTP +SECTION: ".abs_section_248" + _PTS +SECTION: ".abs_section_240" + _PTT +SECTION: ".abs_section_c" + _PUCR +SECTION: ".abs_section_e4" + _PWMCAE +SECTION: ".abs_section_e2" + _PWMCLK +SECTION: ".abs_section_e5" + _PWMCTL +SECTION: ".abs_section_e0" + _PWME +SECTION: ".abs_section_e1" + _PWMPOL +SECTION: ".abs_section_e3" + _PWMPRCLK +SECTION: ".abs_section_e8" + _PWMSCLA +SECTION: ".abs_section_e9" + _PWMSCLB +SECTION: ".abs_section_fe" + _PWMSDN +SECTION: ".abs_section_273" + _RDRAD +SECTION: ".abs_section_d" + _RDRIV +SECTION: ".abs_section_26b" + _RDRJ +SECTION: ".abs_section_253" + _RDRM +SECTION: ".abs_section_25b" + _RDRP +SECTION: ".abs_section_24b" + _RDRS +SECTION: ".abs_section_243" + _RDRT +SECTION: ".abs_section_35" + _REFDV +SECTION: ".abs_section_3b" + _RTICTL +SECTION: ".abs_section_ca" + _SCICR1 +SECTION: ".abs_section_cb" + _SCICR2 +SECTION: ".abs_section_ce" + _SCIDRH +SECTION: ".abs_section_cf" + _SCIDRL +SECTION: ".abs_section_cc" + _SCISR1 +SECTION: ".abs_section_cd" + _SCISR2 +SECTION: ".abs_section_da" + _SPIBR +SECTION: ".abs_section_d8" + _SPICR1 +SECTION: ".abs_section_d9" + _SPICR2 +SECTION: ".abs_section_dd" + _SPIDR +SECTION: ".abs_section_db" + _SPISR +SECTION: ".abs_section_34" + _SYNR +SECTION: ".abs_section_48" + _TCTL1 +SECTION: ".abs_section_49" + _TCTL2 +SECTION: ".abs_section_4a" + _TCTL3 +SECTION: ".abs_section_4b" + _TCTL4 +SECTION: ".abs_section_4e" + _TFLG1 +SECTION: ".abs_section_4f" + _TFLG2 +SECTION: ".abs_section_4c" + _TIE +SECTION: ".abs_section_40" + _TIOS +SECTION: ".abs_section_46" + _TSCR1 +SECTION: ".abs_section_4d" + _TSCR2 +SECTION: ".abs_section_47" + _TTOV +SECTION: ".abs_section_256" + _WOMM +SECTION: ".abs_section_24e" + _WOMS +SECTION: ".abs_section_82" + _ATDCTL23 +SECTION: ".abs_section_84" + _ATDCTL45 +SECTION: ".abs_section_90" + _ATDDR0 +SECTION: ".abs_section_92" + _ATDDR1 +SECTION: ".abs_section_94" + _ATDDR2 +SECTION: ".abs_section_96" + _ATDDR3 +SECTION: ".abs_section_98" + _ATDDR4 +SECTION: ".abs_section_9a" + _ATDDR5 +SECTION: ".abs_section_9c" + _ATDDR6 +SECTION: ".abs_section_9e" + _ATDDR7 +SECTION: ".abs_section_2" + _DDRAB +SECTION: ".abs_section_62" + _PACNT +SECTION: ".abs_section_0" + _PORTAB +SECTION: ".abs_section_ec" + _PWMCNT01 +SECTION: ".abs_section_ee" + _PWMCNT23 +SECTION: ".abs_section_f0" + _PWMCNT45 +SECTION: ".abs_section_f8" + _PWMDTY01 +SECTION: ".abs_section_fa" + _PWMDTY23 +SECTION: ".abs_section_fc" + _PWMDTY45 +SECTION: ".abs_section_f2" + _PWMPER01 +SECTION: ".abs_section_f4" + _PWMPER23 +SECTION: ".abs_section_f6" + _PWMPER45 +SECTION: ".abs_section_c8" + _SCIBD +SECTION: ".abs_section_50" + _TC0 +SECTION: ".abs_section_52" + _TC1 +SECTION: ".abs_section_54" + _TC2 +SECTION: ".abs_section_56" + _TC3 +SECTION: ".abs_section_58" + _TC4 +SECTION: ".abs_section_5a" + _TC5 +SECTION: ".abs_section_5c" + _TC6 +SECTION: ".abs_section_5e" + _TC7 +SECTION: ".abs_section_44" + _TCNT +SECTION: ".abs_section_ff80" + _vect + +********************************************************************************************* +OBJECT LIST SORTED BY ADDRESS + Name Addr hSize dSize Ref Section RLIB +--------------------------------------------------------------------------------------------- + _PORTAB 0 2 2 3 .abs_section_0 + _DDRAB 2 2 2 1 .abs_section_2 + _PORTE 8 1 1 0 .abs_section_8 + _DDRE 9 1 1 0 .abs_section_9 + _PEAR A 1 1 0 .abs_section_a + _MODE B 1 1 0 .abs_section_b + _PUCR C 1 1 0 .abs_section_c + _RDRIV D 1 1 0 .abs_section_d + _EBICTL E 1 1 0 .abs_section_e + _INITRM 10 1 1 1 .abs_section_10 + _INITRG 11 1 1 0 .abs_section_11 + _INITEE 12 1 1 0 .abs_section_12 + _MISC 13 1 1 1 .abs_section_13 + _MTST0 14 1 1 0 .abs_section_14 + _ITCR 15 1 1 0 .abs_section_15 + _ITEST 16 1 1 0 .abs_section_16 + _MTST1 17 1 1 0 .abs_section_17 + _PARTIDH 1A 1 1 0 .abs_section_1a + _PARTIDL 1B 1 1 0 .abs_section_1b + _MEMSIZ0 1C 1 1 0 .abs_section_1c + _MEMSIZ1 1D 1 1 0 .abs_section_1d + _INTCR 1E 1 1 1 .abs_section_1e + _HPRIO 1F 1 1 0 .abs_section_1f + _BKPCT0 28 1 1 0 .abs_section_28 + _BKPCT1 29 1 1 0 .abs_section_29 + _BKP0X 2A 1 1 0 .abs_section_2a + _BKP0H 2B 1 1 0 .abs_section_2b + _BKP0L 2C 1 1 0 .abs_section_2c + _BKP1X 2D 1 1 0 .abs_section_2d + _BKP1H 2E 1 1 0 .abs_section_2e + _BKP1L 2F 1 1 0 .abs_section_2f + _PPAGE 30 1 1 0 .abs_section_30 + _PORTK 32 1 1 0 .abs_section_32 + _DDRK 33 1 1 0 .abs_section_33 + _SYNR 34 1 1 1 .abs_section_34 + _REFDV 35 1 1 1 .abs_section_35 + _CTFLG 36 1 1 0 .abs_section_36 + _CRGFLG 37 1 1 1 .abs_section_37 + _CRGINT 38 1 1 0 .abs_section_38 + _CLKSEL 39 1 1 3 .abs_section_39 + _PLLCTL 3A 1 1 3 .abs_section_3a + _RTICTL 3B 1 1 0 .abs_section_3b + _COPCTL 3C 1 1 0 .abs_section_3c + _CTCTL 3E 1 1 0 .abs_section_3e + _ARMCOP 3F 1 1 0 .abs_section_3f + _TIOS 40 1 1 1 .abs_section_40 + _CFORC 41 1 1 0 .abs_section_41 + _OC7M 42 1 1 0 .abs_section_42 + _OC7D 43 1 1 0 .abs_section_43 + _TCNT 44 2 2 0 .abs_section_44 + _TSCR1 46 1 1 3 .abs_section_46 + _TTOV 47 1 1 1 .abs_section_47 + _TCTL1 48 1 1 1 .abs_section_48 + _TCTL2 49 1 1 1 .abs_section_49 + _TCTL3 4A 1 1 0 .abs_section_4a + _TCTL4 4B 1 1 0 .abs_section_4b + _TIE 4C 1 1 3 .abs_section_4c + _TSCR2 4D 1 1 5 .abs_section_4d + _TFLG1 4E 1 1 2 .abs_section_4e + _TFLG2 4F 1 1 0 .abs_section_4f + _TC0 50 2 2 1 .abs_section_50 + _TC1 52 2 2 0 .abs_section_52 + _TC2 54 2 2 0 .abs_section_54 + _TC3 56 2 2 0 .abs_section_56 + _TC4 58 2 2 0 .abs_section_58 + _TC5 5A 2 2 0 .abs_section_5a + _TC6 5C 2 2 0 .abs_section_5c + _TC7 5E 2 2 1 .abs_section_5e + _PACTL 60 1 1 0 .abs_section_60 + _PAFLG 61 1 1 0 .abs_section_61 + _PACNT 62 2 2 0 .abs_section_62 + _ATDCTL23 82 2 2 0 .abs_section_82 + _ATDCTL45 84 2 2 0 .abs_section_84 + _ATDSTAT0 86 1 1 0 .abs_section_86 + _ATDSTAT1 8B 1 1 0 .abs_section_8b + _ATDDIEN 8D 1 1 0 .abs_section_8d + _PORTAD0 8F 1 1 0 .abs_section_8f + _ATDDR0 90 2 2 0 .abs_section_90 + _ATDDR1 92 2 2 0 .abs_section_92 + _ATDDR2 94 2 2 0 .abs_section_94 + _ATDDR3 96 2 2 0 .abs_section_96 + _ATDDR4 98 2 2 0 .abs_section_98 + _ATDDR5 9A 2 2 0 .abs_section_9a + _ATDDR6 9C 2 2 0 .abs_section_9c + _ATDDR7 9E 2 2 0 .abs_section_9e + _SCIBD C8 2 2 0 .abs_section_c8 + _SCICR1 CA 1 1 0 .abs_section_ca + _SCICR2 CB 1 1 0 .abs_section_cb + _SCISR1 CC 1 1 0 .abs_section_cc + _SCISR2 CD 1 1 0 .abs_section_cd + _SCIDRH CE 1 1 0 .abs_section_ce + _SCIDRL CF 1 1 0 .abs_section_cf + _SPICR1 D8 1 1 0 .abs_section_d8 + _SPICR2 D9 1 1 0 .abs_section_d9 + _SPIBR DA 1 1 0 .abs_section_da + _SPISR DB 1 1 0 .abs_section_db + _SPIDR DD 1 1 0 .abs_section_dd + _PWME E0 1 1 0 .abs_section_e0 + _PWMPOL E1 1 1 0 .abs_section_e1 + _PWMCLK E2 1 1 0 .abs_section_e2 + _PWMPRCLK E3 1 1 0 .abs_section_e3 + _PWMCAE E4 1 1 0 .abs_section_e4 + _PWMCTL E5 1 1 1 .abs_section_e5 + _PWMSCLA E8 1 1 0 .abs_section_e8 + _PWMSCLB E9 1 1 0 .abs_section_e9 + _PWMCNT01 EC 2 2 0 .abs_section_ec + _PWMCNT23 EE 2 2 0 .abs_section_ee + _PWMCNT45 F0 2 2 0 .abs_section_f0 + _PWMPER01 F2 2 2 0 .abs_section_f2 + _PWMPER23 F4 2 2 0 .abs_section_f4 + _PWMPER45 F6 2 2 0 .abs_section_f6 + _PWMDTY01 F8 2 2 0 .abs_section_f8 + _PWMDTY23 FA 2 2 0 .abs_section_fa + _PWMDTY45 FC 2 2 0 .abs_section_fc + _PWMSDN FE 1 1 1 .abs_section_fe + _FCLKDIV 100 1 1 0 .abs_section_100 + _FSEC 101 1 1 0 .abs_section_101 + _FCNFG 103 1 1 0 .abs_section_103 + _FPROT 104 1 1 0 .abs_section_104 + _FSTAT 105 1 1 0 .abs_section_105 + _FCMD 106 1 1 0 .abs_section_106 + _CANCTL0 140 1 1 0 .abs_section_140 + _CANCTL1 141 1 1 0 .abs_section_141 + _CANBTR0 142 1 1 0 .abs_section_142 + _CANBTR1 143 1 1 0 .abs_section_143 + _CANRFLG 144 1 1 0 .abs_section_144 + _CANRIER 145 1 1 0 .abs_section_145 + _CANTFLG 146 1 1 0 .abs_section_146 + _CANTIER 147 1 1 0 .abs_section_147 + _CANTARQ 148 1 1 0 .abs_section_148 + _CANTAAK 149 1 1 0 .abs_section_149 + _CANTBSEL 14A 1 1 0 .abs_section_14a + _CANIDAC 14B 1 1 0 .abs_section_14b + _CANRXERR 14E 1 1 0 .abs_section_14e + _CANTXERR 14F 1 1 0 .abs_section_14f + _CANIDAR0 150 1 1 0 .abs_section_150 + _CANIDAR1 151 1 1 0 .abs_section_151 + _CANIDAR2 152 1 1 0 .abs_section_152 + _CANIDAR3 153 1 1 0 .abs_section_153 + _CANIDMR0 154 1 1 0 .abs_section_154 + _CANIDMR1 155 1 1 0 .abs_section_155 + _CANIDMR2 156 1 1 0 .abs_section_156 + _CANIDMR3 157 1 1 0 .abs_section_157 + _CANIDAR4 158 1 1 0 .abs_section_158 + _CANIDAR5 159 1 1 0 .abs_section_159 + _CANIDAR6 15A 1 1 0 .abs_section_15a + _CANIDAR7 15B 1 1 0 .abs_section_15b + _CANIDMR4 15C 1 1 0 .abs_section_15c + _CANIDMR5 15D 1 1 0 .abs_section_15d + _CANIDMR6 15E 1 1 0 .abs_section_15e + _CANIDMR7 15F 1 1 0 .abs_section_15f + _CANRXIDR0 160 1 1 0 .abs_section_160 + _CANRXIDR1 161 1 1 0 .abs_section_161 + _CANRXIDR2 162 1 1 0 .abs_section_162 + _CANRXIDR3 163 1 1 0 .abs_section_163 + _CANRXDSR0 164 1 1 0 .abs_section_164 + _CANRXDSR1 165 1 1 0 .abs_section_165 + _CANRXDSR2 166 1 1 0 .abs_section_166 + _CANRXDSR3 167 1 1 0 .abs_section_167 + _CANRXDSR4 168 1 1 0 .abs_section_168 + _CANRXDSR5 169 1 1 0 .abs_section_169 + _CANRXDSR6 16A 1 1 0 .abs_section_16a + _CANRXDSR7 16B 1 1 0 .abs_section_16b + _CANRXDLR 16C 1 1 0 .abs_section_16c + _CANTXIDR0 170 1 1 0 .abs_section_170 + _CANTXIDR1 171 1 1 0 .abs_section_171 + _CANTXIDR2 172 1 1 0 .abs_section_172 + _CANTXIDR3 173 1 1 0 .abs_section_173 + _CANTXDSR0 174 1 1 0 .abs_section_174 + _CANTXDSR1 175 1 1 0 .abs_section_175 + _CANTXDSR2 176 1 1 0 .abs_section_176 + _CANTXDSR3 177 1 1 0 .abs_section_177 + _CANTXDSR4 178 1 1 0 .abs_section_178 + _CANTXDSR5 179 1 1 0 .abs_section_179 + _CANTXDSR6 17A 1 1 0 .abs_section_17a + _CANTXDSR7 17B 1 1 0 .abs_section_17b + _CANTXDLR 17C 1 1 0 .abs_section_17c + _CANTXTBPR 17F 1 1 0 .abs_section_17f + _PTT 240 1 1 0 .abs_section_240 + _PTIT 241 1 1 0 .abs_section_241 + _DDRT 242 1 1 0 .abs_section_242 + _RDRT 243 1 1 0 .abs_section_243 + _PERT 244 1 1 0 .abs_section_244 + _PPST 245 1 1 0 .abs_section_245 + _MODRR 247 1 1 0 .abs_section_247 + _PTS 248 1 1 0 .abs_section_248 + _PTIS 249 1 1 0 .abs_section_249 + _DDRS 24A 1 1 0 .abs_section_24a + _RDRS 24B 1 1 0 .abs_section_24b + _PERS 24C 1 1 0 .abs_section_24c + _PPSS 24D 1 1 0 .abs_section_24d + _WOMS 24E 1 1 0 .abs_section_24e + _PTM 250 1 1 0 .abs_section_250 + _PTIM 251 1 1 0 .abs_section_251 + _DDRM 252 1 1 0 .abs_section_252 + _RDRM 253 1 1 0 .abs_section_253 + _PERM 254 1 1 0 .abs_section_254 + _PPSM 255 1 1 0 .abs_section_255 + _WOMM 256 1 1 0 .abs_section_256 + _PTP 258 1 1 0 .abs_section_258 + _PTIP 259 1 1 0 .abs_section_259 + _DDRP 25A 1 1 1 .abs_section_25a + _RDRP 25B 1 1 0 .abs_section_25b + _PERP 25C 1 1 1 .abs_section_25c + _PPSP 25D 1 1 1 .abs_section_25d + _PIEP 25E 1 1 2 .abs_section_25e + _PIFP 25F 1 1 2 .abs_section_25f + _PTJ 268 1 1 0 .abs_section_268 + _PTIJ 269 1 1 0 .abs_section_269 + _DDRJ 26A 1 1 0 .abs_section_26a + _RDRJ 26B 1 1 0 .abs_section_26b + _PERJ 26C 1 1 0 .abs_section_26c + _PPSJ 26D 1 1 0 .abs_section_26d + _PIEJ 26E 1 1 0 .abs_section_26e + _PIFJ 26F 1 1 0 .abs_section_26f + _PTAD 270 1 1 0 .abs_section_270 + _PTIAD 271 1 1 0 .abs_section_271 + _DDRAD 272 1 1 0 .abs_section_272 + _RDRAD 273 1 1 0 .abs_section_273 + _PERAD 274 1 1 0 .abs_section_274 + _PPSAD 275 1 1 0 .abs_section_275 + uxCriticalNesting 800 1 1 91 .data + pxCurrentTCB 801 2 2 29 .bss + uxCurrentNumberOfTasks 803 1 1 3 .bss + xTickCount 804 2 2 14 .bss + uxTopUsedPriority 806 1 1 2 .bss + uxTopReadyPriority 807 1 1 15 .bss + xSchedulerRunning 808 1 1 3 .bss + uxSchedulerSuspended 809 1 1 6 .bss + uxMissedTicks 80A 1 1 4 .bss + uxTaskNumber.1 80B 1 1 2 .bss + pxReadyTasksLists 80C 3C 60 11 .bss + xDelayedTaskList1 848 F 15 2 .bss + xDelayedTaskList2 857 F 15 2 .bss + pxDelayedTaskList 866 2 2 8 .bss + pxOverflowDelayedTaskList 868 2 2 6 .bss + xPendingReadyList 86A F 15 4 .bss + xSuspendedTaskList 879 F 15 2 .bss + uxFlashTaskNumber 888 1 1 2 .bss + xLocalError 889 1 1 3 .bss + uxValToSend.3 88A 1 1 2 .bss + xButtonQueue 88B 2 2 3 .bss + xNextFreeByte 88D 2 2 4 .bss + xHeap 88F 704 1796 1 .bss + xPollingConsumerCount F93 1 1 3 .bss + xPollingProducerCount F94 1 1 3 .bss + xPolledQueue.1 F95 2 2 3 .bss + usCheckVariable F97 2 2 3 .bss + xSuspendedQueueSendError F99 1 1 2 .bss + xSuspendedQueueReceiveError F9A 1 1 3 .bss + ulValueToSend.6 F9B 4 4 5 .bss + ulExpectedValue.7 F9F 4 4 6 .bss + usLastTaskCheck.9 FA3 2 2 2 .bss + xContinousIncrementHandle FA5 2 2 5 .bss + xLimitedIncrementHandle FA7 2 2 2 .bss + ulCounter FA9 4 4 10 .bss + ulReceivedValue.8 FAD 4 4 3 .bss + xSuspendedTestQueue FB1 2 2 3 .common + Byte1_Table FB3 8 8 1 Byte1_DATA + EnUser FBB 1 1 4 TickTimer_DATA + CmpHighVal FBC 2 2 2 TickTimer_DATA + _EntryPoint C000 2E 46 1 .init + PE_low_level_init C02E 48 72 1 .init + STRING.IDLE.2 C093 5 5 1 .rodata1 + STRING.LEDx.1 C098 5 5 1 .rodata1 + STRING.Check.1 C09D 6 6 1 .rodata1 + STRING.Button.2 C0A3 7 7 1 .rodata1 + STRING.QConsNB.2 C0AA 8 8 1 .rodata1 + STRING.QProdNB.3 C0B2 8 8 1 .rodata1 + STRING.CNT_INC.1 C0BA 8 8 1 .rodata1 + STRING.LIM_INC.2 C0C2 8 8 1 .rodata1 + STRING.C_CTRL.3 C0CA 7 7 1 .rodata1 + STRING.SUSP_TX.4 C0D1 8 8 1 .rodata1 + STRING.SUSP_RX.5 C0D9 8 8 1 .rodata1 + xBankedStartScheduler C0E1 F 15 1 NON_BANKED + vPortYield C0F0 16 22 1 NON_BANKED + vPortTickInterrupt C106 1D 29 1 NON_BANKED + vButtonPush C123 2F 47 1 NON_BANKED + Cpu_Interrupt C152 1 1 60 NON_BANKED + Init C153 29 41 1 .text + _Startup C17C 10 16 1 .text + _memcpy_8bitCount C18C 1C 28 3 .text + memset C1A8 1E 30 1 .text + strncpy C1C6 2D 45 1 .text + xTaskCreate C1F3 CE 206 11 .text + vTaskDelayUntil C2C1 74 116 3 .text + vTaskDelay C335 46 70 4 .text + uxTaskPriorityGet C37B 26 38 1 .text + vTaskPrioritySet C3A1 69 105 2 .text + vTaskSuspend C40A 44 68 3 .text + vTaskResume C44E 59 89 3 .text + vTaskStartScheduler C4A7 30 48 1 .text + vTaskSuspendAll C4D7 13 19 11 .text + xTaskResumeAll C4EA 9F 159 13 .text + xTaskGetTickCount C589 17 23 2 .text + vTaskIncrementTick C5A0 81 129 2 .text + vTaskSwitchContext C621 5B 91 3 .text + vTaskPlaceOnEventList C67C 3E 62 2 .text + xTaskRemoveFromEventList C6BA 65 101 3 .text + prvIdleTask C71F 10 16 1 .text + prvInitialiseTCBVariables C72F 4A 74 1 .text + prvInitialiseTaskLists C779 37 55 1 .text + prvCheckTasksWaitingTermination C7B0 1 1 1 .text + prvAllocateTCBAndStack C7B1 39 57 1 .text + xQueueCreate C7EA 76 118 3 .text + xQueueSend C860 C9 201 3 .text + xQueueSendFromISR C929 58 88 1 .text + xQueueReceive C981 C3 195 4 .text + uxQueueMessagesWaiting CA44 1B 27 1 .text + prvUnlockQueue CA5F 6F 111 4 .text + prvIsQueueEmpty CACE 21 33 1 .text + prvIsQueueFull CAEF 24 36 1 .text + vListInitialise CB13 1F 31 7 .text + vListInitialiseItem CB32 7 7 3 .text + vListInsertEnd CB39 25 37 7 .text + vListInsert CB5E 54 84 4 .text + vListRemove CBB2 23 35 13 .text + pxPortInitialiseStack CBD5 2B 43 1 .text + prvSetupTimerInterrupt CC00 9 9 1 .text + xPortStartScheduler CC09 4 4 1 .text + vStartLEDFlashTasks CC0D 2E 46 1 .text + vLEDFlashTask CC3B 52 82 1 .text + vMain CC8D 42 66 1 .text + vErrorChecks CCCF 35 53 1 .text + prvCheckOtherTasksAreStillRunning CD04 26 38 1 .text + vApplicationIdleHook CD2A 73 115 1 .text + vButtonTask CD9D 4F 79 1 .text + pvPortMalloc CDEC 2D 45 4 .text + vPortFree CE19 1 1 2 .text + vParTestToggleLED CE1A 13 19 4 .text + PE_Timer_LngHi1 CE2D 4A 74 1 .text + main CE77 8 8 0 .text + vStartPolledQueueTasks CE7F 42 66 1 .text + vPolledQueueProducer CEC1 4D 77 1 .text + vPolledQueueConsumer CF0E 59 89 1 .text + xArePollingQueuesStillRunning CF67 15 21 1 .text + vStartDynamicPriorityTasks CF7C 7C 124 1 .text + vLimitedIncrementTask CFF8 26 38 1 .text + vContinuousIncrementTask D01E 35 53 1 .text + vCounterControlTask D053 98 152 3 .text + vQueueSendWhenSuspendedTask D0EB 34 52 1 .text + vQueueReceiveWhenSuspendedTask D11F 4F 79 1 .text + xAreDynamicPriorityTasksStillRunning D16E 2B 43 1 .text + _LCMP D199 19 25 2 RUNTIME + _LCMP_P D1B2 15 21 2 RUNTIME + _LNEG D1C7 D 13 1 RUNTIME + _LINC D1D4 5 5 4 RUNTIME + _lDivMod D1D9 E3 227 3 RUNTIME + _LDIVU D2BC E 14 1 RUNTIME + _NEG_P D2CA F 15 4 RUNTIME + _LDIVS D2D9 35 53 1 RUNTIME + SetCV D30E B 11 2 TickTimer_CODE + SetPV D319 9 9 1 TickTimer_CODE + HWEnDi D322 11 17 2 TickTimer_CODE + TickTimer_Enable D333 E 14 1 TickTimer_CODE + TickTimer_SetFreqHz D341 4E 78 1 TickTimer_CODE + TickTimer_Init D38F 14 20 1 TickTimer_CODE + ButtonInterrupt_Enable D3A3 A 10 1 ButtonInterrupt_CODE + Byte1_GetMsk D3AD D 13 1 Byte1_CODE + Byte1_NegBit D3BA A 10 1 Byte1_CODE + _BDMSTS FF01 1 1 0 .abs_section_ff01 + _BDMCCR FF06 1 1 0 .abs_section_ff06 + _BDMINR FF07 1 1 0 .abs_section_ff07 + _vect FF80 80 128 0 .abs_section_ff80 + +********************************************************************************************* +UNUSED-OBJECTS SECTION +--------------------------------------------------------------------------------------------- +NOT USED PROCEDURES +STRING.C.o (ansisi.lib): + strerror memchr memcmp memcpy2 memcpy memmove _memset_clear_8bitCount strlen + strset strcat strncat strcpy strcmp strncmp strchr strrchr strspn strcspn + strpbrk strstr strtok strcoll strxfrm +rtshc12.c.o (ansisi.lib): + _BSHL _BSHRS _BSHRU _BDIVMODU _BDIVMODS _ISHL _ISHRU _ISHRS _LSHL _LSHRU + _LSHRS _LADD _LSUB _LAND _LOR _LXOR _LCMP_PP _LABS _LCOM _LDEC _LMUL _LMODU + _LMODS _ILSEXT _LTEST _COPY _CASE_DIRECT _CASE_DIRECT_BYTE _CASE_CHECKED + _CASE_CHECKED_BYTE _CASE_SEARCH _CASE_SEARCH_BYTE _CASE_SEARCH_8 + _CASE_SEARCH_8_BYTE _FCALL _FPCMP +tasks.c.o: + vTaskEndScheduler uxTaskGetNumberOfTasks +queue.c.o: + xQueueReceiveFromISR vQueueDelete +port.c.o: + vPortEndScheduler +heap_1.c.o: + vPortInitialiseBlocks +ParTest.c.o: + vParTestSetLED +Byte1.C.o: + Byte1_PutBit +TickTimer.C.o: + TickTimer_Interrupt +ButtonInterrupt.C.o: + ButtonInterrupt_Interrupt +NOT USED VARIABLES +STRING.C.o (ansisi.lib): + STRING..1 next.2 +rtshc12.c.o (ansisi.lib): + _PowOfTwo_8 _PowOfTwo_16 _PowOfTwo_32 +Cpu.C.o: + CpuMode CCR_reg + +********************************************************************************************* +COPYDOWN SECTION +--------------------------------------------------------------------------------------------- +------- ROM-ADDRESS: 0xD3C4 ---- SIZE 4 --- +Filling bytes inserted + 00010800 +------- ROM-ADDRESS: 0xD3C8 ---- RAM-ADDRESS: 0x800 ---- SIZE 1 --- +Name of initialized Object : uxCriticalNesting + FF +------- ROM-ADDRESS: 0xD3C9 ---- SIZE 4 --- +Filling bytes inserted + 00080FB3 +------- ROM-ADDRESS: 0xD3CD ---- RAM-ADDRESS: 0xFB3 ---- SIZE 8 --- +Name of initialized Object : Byte1_Table + 0102040810 204080 +------- ROM-ADDRESS: 0xD3D5 ---- SIZE 2 --- +Filling bytes inserted + 0000 + +********************************************************************************************* +OBJECT-DEPENDENCIES SECTION +--------------------------------------------------------------------------------------------- +_EntryPoint USES _INITRM _MISC _CLKSEL _PLLCTL _SYNR _REFDV + _CRGFLG _Startup +PE_low_level_init USES _TSCR1 _TCTL2 _TCTL1 _TIE _TTOV _TSCR2 _TIOS + _PPSP _PERP _DDRP _PWMCTL _PWMSDN _PORTAB _DDRAB + TickTimer_Init _PIEP _INTCR +xBankedStartScheduler USES prvSetupTimerInterrupt pxCurrentTCB + uxCriticalNesting +vPortYield USES uxCriticalNesting pxCurrentTCB + vTaskSwitchContext +vPortTickInterrupt USES uxCriticalNesting pxCurrentTCB + vTaskIncrementTick vTaskSwitchContext _TFLG1 +vButtonPush USES uxValToSend.3 _PIFP xButtonQueue + xQueueSendFromISR uxCriticalNesting pxCurrentTCB + vTaskSwitchContext +Init USES _startupData +_Startup USES _startupData Init +xTaskCreate USES prvAllocateTCBAndStack + prvInitialiseTCBVariables pxPortInitialiseStack uxCriticalNesting + uxCurrentNumberOfTasks pxCurrentTCB prvInitialiseTaskLists + xSchedulerRunning uxTopUsedPriority uxTaskNumber.1 + uxTopReadyPriority pxReadyTasksLists vListInsertEnd +vTaskDelayUntil USES vTaskSuspendAll xTickCount pxCurrentTCB + vListRemove pxOverflowDelayedTaskList pxDelayedTaskList + vListInsert xTaskResumeAll +vTaskDelay USES vTaskSuspendAll xTickCount pxCurrentTCB + vListRemove pxOverflowDelayedTaskList pxDelayedTaskList + vListInsert xTaskResumeAll +uxTaskPriorityGet USES uxCriticalNesting pxCurrentTCB +vTaskPrioritySet USES uxCriticalNesting pxCurrentTCB + pxReadyTasksLists vListRemove uxTopReadyPriority vListInsertEnd +vTaskSuspend USES uxCriticalNesting pxCurrentTCB vListRemove + xSuspendedTaskList vListInsertEnd +vTaskResume USES uxCriticalNesting pxCurrentTCB vListRemove + uxTopReadyPriority pxReadyTasksLists vListInsertEnd +vTaskStartScheduler USES pxCurrentTCB prvIdleTask STRING.IDLE.2 + xTaskCreate xSchedulerRunning xTickCount + xPortStartScheduler +vTaskSuspendAll USES uxCriticalNesting uxSchedulerSuspended +xTaskResumeAll USES uxCriticalNesting uxSchedulerSuspended + uxCurrentNumberOfTasks vListRemove uxTopReadyPriority + pxReadyTasksLists vListInsertEnd pxCurrentTCB xPendingReadyList + uxMissedTicks vTaskIncrementTick +xTaskGetTickCount USES uxCriticalNesting xTickCount +vTaskIncrementTick USES uxSchedulerSuspended xTickCount + pxDelayedTaskList pxOverflowDelayedTaskList vListRemove + uxTopReadyPriority pxReadyTasksLists vListInsertEnd uxMissedTicks +vTaskSwitchContext USES uxSchedulerSuspended uxTopReadyPriority + pxCurrentTCB pxReadyTasksLists +vTaskPlaceOnEventList USES pxCurrentTCB vListInsert xTickCount vListRemove + pxOverflowDelayedTaskList pxDelayedTaskList +xTaskRemoveFromEventList USES vListRemove uxSchedulerSuspended + uxTopReadyPriority pxReadyTasksLists xPendingReadyList + vListInsertEnd pxCurrentTCB +prvIdleTask USES prvCheckTasksWaitingTermination + pxReadyTasksLists vApplicationIdleHook +prvInitialiseTCBVariables USES strncpy vListInitialiseItem +prvInitialiseTaskLists USES pxReadyTasksLists vListInitialise + xDelayedTaskList1 xDelayedTaskList2 xPendingReadyList + xSuspendedTaskList pxDelayedTaskList pxOverflowDelayedTaskList +prvAllocateTCBAndStack USES pvPortMalloc vPortFree memset +xQueueCreate USES pvPortMalloc vListInitialise vPortFree +xQueueSend USES vTaskSuspendAll uxCriticalNesting xQueueSend + prvIsQueueFull vTaskPlaceOnEventList prvUnlockQueue + xTaskResumeAll _memcpy_8bitCount +xQueueSendFromISR USES _memcpy_8bitCount xTaskRemoveFromEventList +xQueueReceive USES vTaskSuspendAll uxCriticalNesting xQueueReceive + prvIsQueueEmpty vTaskPlaceOnEventList prvUnlockQueue + xTaskResumeAll _memcpy_8bitCount +uxQueueMessagesWaiting USES uxCriticalNesting +prvUnlockQueue USES uxCriticalNesting xTaskRemoveFromEventList +prvIsQueueEmpty USES uxCriticalNesting +prvIsQueueFull USES uxCriticalNesting +vListInitialise USES vListInitialiseItem +prvSetupTimerInterrupt USES TickTimer_SetFreqHz TickTimer_Enable +xPortStartScheduler USES xBankedStartScheduler +vStartLEDFlashTasks USES vLEDFlashTask STRING.LEDx.1 xTaskCreate +vLEDFlashTask USES uxCriticalNesting uxFlashTaskNumber + xTaskGetTickCount vTaskDelayUntil vParTestToggleLED +vMain USES vStartLEDFlashTasks vStartPolledQueueTasks + vStartDynamicPriorityTasks vErrorChecks STRING.Check.1 xTaskCreate + vButtonTask STRING.Button.2 vTaskStartScheduler +vErrorChecks USES xTaskGetTickCount vTaskDelayUntil + prvCheckOtherTasksAreStillRunning _LCMP vParTestToggleLED +prvCheckOtherTasksAreStillRunning USES xArePollingQueuesStillRunning + xAreDynamicPriorityTasksStillRunning xLocalError +vApplicationIdleHook USES _LNEG _LDIVS _LCMP_P uxCriticalNesting + xLocalError +vButtonTask USES xQueueCreate xButtonQueue + ButtonInterrupt_Enable xQueueReceive uxCriticalNesting xLocalError + vParTestToggleLED +pvPortMalloc USES vTaskSuspendAll xNextFreeByte xHeap + xTaskResumeAll +vParTestToggleLED USES uxCriticalNesting Byte1_NegBit +PE_Timer_LngHi1 USES _LCMP +main USES PE_low_level_init vMain +vStartPolledQueueTasks USES xQueueCreate xPolledQueue.1 + vPolledQueueConsumer STRING.QConsNB.2 xTaskCreate + vPolledQueueProducer STRING.QProdNB.3 +vPolledQueueProducer USES xQueueSend uxCriticalNesting + xPollingProducerCount vTaskDelay +vPolledQueueConsumer USES xQueueReceive uxCriticalNesting + xPollingConsumerCount uxQueueMessagesWaiting vTaskDelay +xArePollingQueuesStillRunning USES xPollingConsumerCount xPollingProducerCount +vStartDynamicPriorityTasks USES xQueueCreate xSuspendedTestQueue + vContinuousIncrementTask STRING.CNT_INC.1 ulCounter + xContinousIncrementHandle xTaskCreate vLimitedIncrementTask + STRING.LIM_INC.2 xLimitedIncrementHandle vCounterControlTask + STRING.C_CTRL.3 vQueueSendWhenSuspendedTask STRING.SUSP_TX.4 + vQueueReceiveWhenSuspendedTask STRING.SUSP_RX.5 +vLimitedIncrementTask USES _LINC _LCMP_P vTaskSuspend +vContinuousIncrementTask USES uxTaskPriorityGet vTaskPrioritySet _LINC +vCounterControlTask USES vCounterControlTask xContinousIncrementHandle + vTaskSuspend ulCounter vTaskResume vTaskDelay + vTaskSuspendAll xTaskResumeAll xLimitedIncrementHandle + uxCriticalNesting usCheckVariable +vQueueSendWhenSuspendedTask USES vTaskSuspendAll xSuspendedTestQueue + ulValueToSend.6 xQueueSend xSuspendedQueueSendError + xTaskResumeAll vTaskDelay _LINC +vQueueReceiveWhenSuspendedTask USES vTaskSuspendAll xSuspendedTestQueue + ulReceivedValue.8 xQueueReceive xTaskResumeAll + xSuspendedQueueReceiveError ulExpectedValue.7 _LINC +xAreDynamicPriorityTasksStillRunning USES usCheckVariable usLastTaskCheck.9 + xSuspendedQueueSendError xSuspendedQueueReceiveError +_LDIVU USES _lDivMod +_LDIVS USES _NEG_P _lDivMod +SetCV USES _TC0 _TC7 +SetPV USES _TSCR2 +HWEnDi USES EnUser _TFLG1 _TIE +TickTimer_Enable USES EnUser HWEnDi +TickTimer_SetFreqHz USES _LDIVU PE_Timer_LngHi1 CmpHighVal SetCV +TickTimer_Init USES CmpHighVal EnUser SetCV SetPV HWEnDi +ButtonInterrupt_Enable USES _PIFP _PIEP +Byte1_GetMsk USES Byte1_Table +Byte1_NegBit USES Byte1_GetMsk _PORTAB +_vect USES Cpu_Interrupt vButtonPush vPortTickInterrupt + vPortYield _EntryPoint + +********************************************************************************************* +DEPENDENCY TREE +********************************************************************************************* + main and _Startup Group + | + +- main + | | + | +- PE_low_level_init + | | | + | | +- TickTimer_Init + | | | + | | +- SetCV + | | | + | | +- SetPV + | | | + | | +- HWEnDi + | | + | +- vMain + | | + | +- vStartLEDFlashTasks + | | | + | | +- vLEDFlashTask + | | | | + | | | +- xTaskGetTickCount + | | | | + | | | +- vTaskDelayUntil + | | | | | + | | | | +- vTaskSuspendAll + | | | | | + | | | | +- vListRemove + | | | | | + | | | | +- vListInsert + | | | | | + | | | | +- xTaskResumeAll + | | | | | + | | | | +- vListRemove (see above) + | | | | | + | | | | +- vListInsertEnd + | | | | | + | | | | +- vTaskIncrementTick + | | | | | + | | | | +- vListRemove (see above) + | | | | | + | | | | +- vListInsertEnd (see above) + | | | | + | | | +- vParTestToggleLED + | | | | + | | | +- Byte1_NegBit + | | | | + | | | +- Byte1_GetMsk + | | | + | | +- xTaskCreate + | | | + | | +- prvAllocateTCBAndStack + | | | | + | | | +- pvPortMalloc + | | | | | + | | | | +- vTaskSuspendAll (see above) + | | | | | + | | | | +- xTaskResumeAll (see above) + | | | | + | | | +- vPortFree + | | | | + | | | +- memset + | | | + | | +- prvInitialiseTCBVariables + | | | | + | | | +- strncpy + | | | | + | | | +- vListInitialiseItem + | | | + | | +- pxPortInitialiseStack + | | | + | | +- prvInitialiseTaskLists + | | | | + | | | +- vListInitialise + | | | | + | | | +- vListInitialiseItem (see above) + | | | + | | +- vListInsertEnd (see above) + | | + | +- vStartPolledQueueTasks + | | | + | | +- xQueueCreate + | | | | + | | | +- pvPortMalloc (see above) + | | | | + | | | +- vListInitialise (see above) + | | | | + | | | +- vPortFree (see above) + | | | + | | +- vPolledQueueConsumer + | | | | + | | | +- xQueueReceive + | | | | | + | | | | +- vTaskSuspendAll (see above) + | | | | | + | | | | +- prvIsQueueEmpty + | | | | | + | | | | +- vTaskPlaceOnEventList + | | | | | | + | | | | | +- vListInsert (see above) + | | | | | | + | | | | | +- vListRemove (see above) + | | | | | + | | | | +- prvUnlockQueue + | | | | | | + | | | | | +- xTaskRemoveFromEventList + | | | | | | + | | | | | +- vListRemove (see above) + | | | | | | + | | | | | +- vListInsertEnd (see above) + | | | | | + | | | | +- xTaskResumeAll (see above) + | | | | | + | | | | +- _memcpy_8bitCount + | | | | + | | | +- uxQueueMessagesWaiting + | | | | + | | | +- vTaskDelay + | | | | + | | | +- vTaskSuspendAll (see above) + | | | | + | | | +- vListRemove (see above) + | | | | + | | | +- vListInsert (see above) + | | | | + | | | +- xTaskResumeAll (see above) + | | | + | | +- xTaskCreate (see above) + | | | + | | +- vPolledQueueProducer + | | | + | | +- xQueueSend + | | | | + | | | +- vTaskSuspendAll (see above) + | | | | + | | | +- prvIsQueueFull + | | | | + | | | +- vTaskPlaceOnEventList (see above) + | | | | + | | | +- prvUnlockQueue (see above) + | | | | + | | | +- xTaskResumeAll (see above) + | | | | + | | | +- _memcpy_8bitCount (see above) + | | | + | | +- vTaskDelay (see above) + | | + | +- vStartDynamicPriorityTasks + | | | + | | +- xQueueCreate (see above) + | | | + | | +- vContinuousIncrementTask + | | | | + | | | +- uxTaskPriorityGet + | | | | + | | | +- vTaskPrioritySet + | | | | | + | | | | +- vListRemove (see above) + | | | | | + | | | | +- vListInsertEnd (see above) + | | | | + | | | +- _LINC + | | | + | | +- xTaskCreate (see above) + | | | + | | +- vLimitedIncrementTask + | | | | + | | | +- _LINC (see above) + | | | | + | | | +- _LCMP_P + | | | | + | | | +- vTaskSuspend + | | | | + | | | +- vListRemove (see above) + | | | | + | | | +- vListInsertEnd (see above) + | | | + | | +- vCounterControlTask + | | | | + | | | +- vTaskSuspend (see above) + | | | | + | | | +- vTaskResume + | | | | | + | | | | +- vListRemove (see above) + | | | | | + | | | | +- vListInsertEnd (see above) + | | | | + | | | +- vTaskDelay (see above) + | | | | + | | | +- vTaskSuspendAll (see above) + | | | | + | | | +- xTaskResumeAll (see above) + | | | + | | +- vQueueSendWhenSuspendedTask + | | | | + | | | +- vTaskSuspendAll (see above) + | | | | + | | | +- xQueueSend (see above) + | | | | + | | | +- xTaskResumeAll (see above) + | | | | + | | | +- vTaskDelay (see above) + | | | | + | | | +- _LINC (see above) + | | | + | | +- vQueueReceiveWhenSuspendedTask + | | | + | | +- vTaskSuspendAll (see above) + | | | + | | +- xQueueReceive (see above) + | | | + | | +- xTaskResumeAll (see above) + | | | + | | +- _LINC (see above) + | | + | +- vErrorChecks + | | | + | | +- xTaskGetTickCount (see above) + | | | + | | +- vTaskDelayUntil (see above) + | | | + | | +- prvCheckOtherTasksAreStillRunning + | | | | + | | | +- xArePollingQueuesStillRunning + | | | | + | | | +- xAreDynamicPriorityTasksStillRunning + | | | + | | +- _LCMP + | | | + | | +- vParTestToggleLED (see above) + | | + | +- xTaskCreate (see above) + | | + | +- vButtonTask + | | | + | | +- xQueueCreate (see above) + | | | + | | +- ButtonInterrupt_Enable + | | | + | | +- xQueueReceive (see above) + | | | + | | +- vParTestToggleLED (see above) + | | + | +- vTaskStartScheduler + | | + | +- prvIdleTask + | | | + | | +- prvCheckTasksWaitingTermination + | | | + | | +- vApplicationIdleHook + | | | + | | +- _LNEG + | | | + | | +- _LDIVS + | | | | + | | | +- _NEG_P + | | | | + | | | +- _lDivMod + | | | + | | +- _LCMP_P (see above) + | | + | +- xTaskCreate (see above) + | | + | +- xPortStartScheduler + | | + | +- xBankedStartScheduler + | | + | +- prvSetupTimerInterrupt + | | + | +- TickTimer_SetFreqHz + | | | + | | +- _LDIVU + | | | | + | | | +- _lDivMod (see above) + | | | + | | +- PE_Timer_LngHi1 + | | | | + | | | +- _LCMP (see above) + | | | + | | +- SetCV (see above) + | | + | +- TickTimer_Enable + | | + | +- HWEnDi (see above) + | + +- _EntryPoint + | + +- _Startup + | + +- Init + + _vect + | + +- Cpu_Interrupt + | + +- vButtonPush + | | + | +- xQueueSendFromISR + | | | + | | +- _memcpy_8bitCount (see above) + | | | + | | +- xTaskRemoveFromEventList (see above) + | | + | +- vTaskSwitchContext + | + +- vPortTickInterrupt + | | + | +- vTaskIncrementTick (see above) + | | + | +- vTaskSwitchContext (see above) + | + +- vPortYield + | | + | +- vTaskSwitchContext (see above) + | + +- _EntryPoint (see above) + +********************************************************************************************* +STATISTIC SECTION +--------------------------------------------------------------------------------------------- + +ExeFile: +-------- +Number of blocks to be downloaded: 11 +Total size of all blocks to be downloaded: 5207 + diff --git a/20080212/Demo/HCS12_CodeWarrior_small/cmd/Simulator_Postload.cmd b/20080212/Demo/HCS12_CodeWarrior_small/cmd/Simulator_Postload.cmd new file mode 100644 index 000000000..0a5372487 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_small/cmd/Simulator_Postload.cmd @@ -0,0 +1,3 @@ +// After load the commands written below will be executed +// Show main function at startup +FindProc main diff --git a/20080212/Demo/HCS12_CodeWarrior_small/cmd/Simulator_Preload.cmd b/20080212/Demo/HCS12_CodeWarrior_small/cmd/Simulator_Preload.cmd new file mode 100644 index 000000000..691c5eede --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_small/cmd/Simulator_Preload.cmd @@ -0,0 +1 @@ +// Before load the commands written below will be executed diff --git a/20080212/Demo/HCS12_CodeWarrior_small/cmd/Simulator_Reset.cmd b/20080212/Demo/HCS12_CodeWarrior_small/cmd/Simulator_Reset.cmd new file mode 100644 index 000000000..f0fc87448 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_small/cmd/Simulator_Reset.cmd @@ -0,0 +1 @@ +// After reset the commands written below will be executed diff --git a/20080212/Demo/HCS12_CodeWarrior_small/cmd/Simulator_SetCPU.cmd b/20080212/Demo/HCS12_CodeWarrior_small/cmd/Simulator_SetCPU.cmd new file mode 100644 index 000000000..5f2b5a568 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_small/cmd/Simulator_SetCPU.cmd @@ -0,0 +1 @@ +// At startup the commands written below will be executed diff --git a/20080212/Demo/HCS12_CodeWarrior_small/cmd/Simulator_Startup.cmd b/20080212/Demo/HCS12_CodeWarrior_small/cmd/Simulator_Startup.cmd new file mode 100644 index 000000000..5f2b5a568 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_small/cmd/Simulator_Startup.cmd @@ -0,0 +1 @@ +// At startup the commands written below will be executed diff --git a/20080212/Demo/HCS12_CodeWarrior_small/cmd/SofTec_Postload.cmd b/20080212/Demo/HCS12_CodeWarrior_small/cmd/SofTec_Postload.cmd new file mode 100644 index 000000000..0a5372487 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_small/cmd/SofTec_Postload.cmd @@ -0,0 +1,3 @@ +// After load the commands written below will be executed +// Show main function at startup +FindProc main diff --git a/20080212/Demo/HCS12_CodeWarrior_small/cmd/SofTec_Preload.cmd b/20080212/Demo/HCS12_CodeWarrior_small/cmd/SofTec_Preload.cmd new file mode 100644 index 000000000..691c5eede --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_small/cmd/SofTec_Preload.cmd @@ -0,0 +1 @@ +// Before load the commands written below will be executed diff --git a/20080212/Demo/HCS12_CodeWarrior_small/cmd/SofTec_Reset.cmd b/20080212/Demo/HCS12_CodeWarrior_small/cmd/SofTec_Reset.cmd new file mode 100644 index 000000000..f0fc87448 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_small/cmd/SofTec_Reset.cmd @@ -0,0 +1 @@ +// After reset the commands written below will be executed diff --git a/20080212/Demo/HCS12_CodeWarrior_small/cmd/SofTec_Startup.cmd b/20080212/Demo/HCS12_CodeWarrior_small/cmd/SofTec_Startup.cmd new file mode 100644 index 000000000..5f2b5a568 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_small/cmd/SofTec_Startup.cmd @@ -0,0 +1 @@ +// At startup the commands written below will be executed diff --git a/20080212/Demo/HCS12_CodeWarrior_small/main.c b/20080212/Demo/HCS12_CodeWarrior_small/main.c new file mode 100644 index 000000000..ef3a4192e --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_small/main.c @@ -0,0 +1,374 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +/* + * + * vMain() is effectively the demo application entry point. It is called by + * the main() function generated by the Processor Expert application. + * + * vMain() creates all the demo application tasks, then starts the scheduler. + * The WEB documentation provides more details of the demo application tasks. + * + * Main.c also creates a task called "Check". This only executes every three + * seconds but has the highest priority so is guaranteed to get processor time. + * Its main function is to check that all the other tasks are still operational. + * Each task (other than the "flash" tasks) maintains a unique count that is + * incremented each time the task successfully completes its function. Should + * any error occur within such a task the count is permanently halted. The + * check task inspects the count of each task to ensure it has changed since + * the last time the check task executed. If all the count variables have + * changed all the tasks are still executing error free, and the check task + * toggles the onboard LED. Should any task contain an error at any time + * the LED toggle rate will change from 3 seconds to 500ms. + * + * This file also includes the functionality normally implemented within the + * standard demo application file integer.c. Due to the limited memory + * available on the microcontroller the functionality has been included within + * the idle task hook [vApplicationIdleHook()] - instead of within the usual + * separate task. See the documentation within integer.c for the rationale + * of the integer task functionality. + * + * + * + * The demo applications included with other FreeRTOS ports make use of the + * standard ComTest tasks. These use a loopback connector to transmit and + * receive RS232 characters between two tasks. The test is important for two + * reasons: + * + * 1) It tests the mechanism of context switching from within an application + * ISR. + * + * 2) It generates some randomised timing. + * + * The demo board used to develop this port does not include an RS232 interface + * so the ComTest tasks could not easily be included. Instead these two tests + * are created using a 'Button Push' task. + * + * The 'Button Push' task blocks on a queue, waiting for data to arrive. A + * simple interrupt routine connected to the PP0 input on the demo board places + * data in the queue each time the PP0 button is pushed (this button is built + * onto the demo board). As the 'Button Push' task is created with a + * relatively high priority it will unblock and want to execute as soon as data + * arrives in the queue - resulting in a context switch within the PP0 input + * ISR. If the data retrieved from the queue is that expected the 'Button Push' + * task toggles LED 5. Therefore correct operation is indicated by the LED + * toggling each time the PP0 button is pressed. + * + * This test is not as satisfactory as the ComTest method - but the simple + * nature of the port makes is just about adequate. + * + */ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* Demo application includes. */ +#include "flash.h" +#include "PollQ.h" +#include "dynamic.h" +#include "partest.h" + +/* Processor expert includes. */ +#include "ButtonInterrupt.h" + +/*----------------------------------------------------------- + Definitions. +-----------------------------------------------------------*/ + +/* Priorities assigned to demo application tasks. */ +#define mainFLASH_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainBUTTON_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) + +/* LED that is toggled by the check task. The check task periodically checks +that all the other tasks are operating without error. If no errors are found +the LED is toggled with mainCHECK_PERIOD frequency. If an error is found +then the toggle rate increases to mainERROR_CHECK_PERIOD. */ +#define mainCHECK_TASK_LED ( 7 ) +#define mainCHECK_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS ) +#define mainERROR_CHECK_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS ) + +/* LED that is toggled by the button push interrupt. */ +#define mainBUTTON_PUSH_LED ( 5 ) + +/* The constants used in the idle task calculation. */ +#define intgCONST1 ( ( portLONG ) 123 ) +#define intgCONST2 ( ( portLONG ) 234567 ) +#define intgCONST3 ( ( portLONG ) -3 ) +#define intgCONST4 ( ( portLONG ) 7 ) +#define intgEXPECTED_ANSWER ( ( ( intgCONST1 + intgCONST2 ) * intgCONST3 ) / intgCONST4 ) + +/* The length of the queue between is button push ISR and the Button Push task +is greater than 1 to account for switch bounces generating multiple inputs. */ +#define mainBUTTON_QUEUE_SIZE 6 + +/*----------------------------------------------------------- + Local functions prototypes. +-----------------------------------------------------------*/ + +/* + * The 'Check' task function. See the explanation at the top of the file. + */ +static void vErrorChecks( void* pvParameters ); + +/* + * The 'Button Push' task. See the explanation at the top of the file. + */ +static void vButtonTask( void *pvParameters ); + +/* + * The idle task hook - in which the integer task is implemented. See the + * explanation at the top of the file. + */ +void vApplicationIdleHook( void ); + +/* + * Checks the unique counts of other tasks to ensure they are still operational. + */ +static portLONG prvCheckOtherTasksAreStillRunning( void ); + + + +/*----------------------------------------------------------- + Local variables. +-----------------------------------------------------------*/ + +/* A few tasks are defined within this file. This flag is used to indicate +their status. If an error is detected in one of the locally defined tasks then +this flag is set to pdTRUE. */ +portBASE_TYPE xLocalError = pdFALSE; + +/* The queue used to send data from the button push ISR to the Button Push +task. */ +static xQueueHandle xButtonQueue; + + +/*-----------------------------------------------------------*/ + +/* + * This is called from the main() function generated by the Processor Expert. + */ +void vMain( void ) +{ + /* Start some of the standard demo tasks. */ + vStartLEDFlashTasks( mainFLASH_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartDynamicPriorityTasks(); + + /* Start the locally defined tasks. There is also a task implemented as + the idle hook. */ + xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + xTaskCreate( vButtonTask, "Button", configMINIMAL_STACK_SIZE, NULL, mainBUTTON_TASK_PRIORITY, NULL ); + + /* All the tasks have been created - start the scheduler. */ + vTaskStartScheduler(); + + /* Should not reach here! */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void vErrorChecks( void *pvParameters ) +{ +portTickType xDelayPeriod = mainCHECK_PERIOD; +portTickType xLastWakeTime; + + /* Initialise xLastWakeTime to ensure the first call to vTaskDelayUntil() + functions correctly. */ + xLastWakeTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Delay until it is time to execute again. The delay period is + shorter following an error. */ + vTaskDelayUntil( &xLastWakeTime, xDelayPeriod ); + + /* Check all the demo application tasks are executing without + error. If an error is found the delay period is shortened - this + has the effect of increasing the flash rate of the 'check' task + LED. */ + if( prvCheckOtherTasksAreStillRunning() == pdFAIL ) + { + /* An error has been detected in one of the tasks - flash faster. */ + xDelayPeriod = mainERROR_CHECK_PERIOD; + } + + /* Toggle the LED each cycle round. */ + vParTestToggleLED( mainCHECK_TASK_LED ); + } +} +/*-----------------------------------------------------------*/ + +static portLONG prvCheckOtherTasksAreStillRunning( void ) +{ +portBASE_TYPE xAllTasksPassed = pdPASS; + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + xAllTasksPassed = pdFAIL; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + xAllTasksPassed = pdFAIL; + } + + /* Also check the status flag for the tasks defined within this function. */ + if( xLocalError != pdFALSE ) + { + xAllTasksPassed = pdFAIL; + } + + return xAllTasksPassed; +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ +/* This variable is effectively set to a constant so it is made volatile to +ensure the compiler does not just get rid of it. */ +volatile portLONG lValue; + + /* Keep performing a calculation and checking the result against a constant. */ + for( ;; ) + { + /* Perform the calculation. This will store partial value in + registers, resulting in a good test of the context switch mechanism. */ + lValue = intgCONST1; + lValue += intgCONST2; + lValue *= intgCONST3; + lValue /= intgCONST4; + + /* Did we perform the calculation correctly with no corruption? */ + if( lValue != intgEXPECTED_ANSWER ) + { + /* Error! */ + portENTER_CRITICAL(); + xLocalError = pdTRUE; + portEXIT_CRITICAL(); + } + + /* Yield in case cooperative scheduling is being used. */ + #if configUSE_PREEMPTION == 0 + { + taskYIELD(); + } + #endif + } +} +/*-----------------------------------------------------------*/ + +static void vButtonTask( void *pvParameters ) +{ +unsigned portBASE_TYPE uxExpected = 1, uxReceived; + + /* Create the queue used by the producer and consumer. */ + xButtonQueue = xQueueCreate( mainBUTTON_QUEUE_SIZE, ( unsigned portBASE_TYPE ) sizeof( unsigned portBASE_TYPE ) ); + + if( xButtonQueue ) + { + /* Now the queue is created it is safe to enable the button interrupt. */ + ButtonInterrupt_Enable(); + + for( ;; ) + { + /* Simply wait for data to arrive from the button push interrupt. */ + if( xQueueReceive( xButtonQueue, &uxReceived, portMAX_DELAY ) == pdPASS ) + { + /* Was the data we received that expected? */ + if( uxReceived != uxExpected ) + { + /* Error! */ + portENTER_CRITICAL(); + xLocalError = pdTRUE; + portEXIT_CRITICAL(); + } + else + { + /* Toggle the LED for every successful push. */ + vParTestToggleLED( mainBUTTON_PUSH_LED ); + } + + uxExpected++; + } + } + } + + /* Will only get here if the queue could not be created. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +#pragma CODE_SEG __NEAR_SEG NON_BANKED + + /* Button push ISR. */ + void interrupt vButtonPush( void ) + { + static unsigned portBASE_TYPE uxValToSend = 0; + + /* Send an incrementing value to the button push task each run. */ + uxValToSend++; + + /* Clear the interrupt flag. */ + PIFP = 1; + + /* Send the incremented value down the queue. The button push task is + blocked waiting for the data. As the button push task is high priority + it will wake and a context switch should be performed before leaving + the ISR. */ + if( xQueueSendFromISR( xButtonQueue, &uxValToSend, pdFALSE ) ) + { + /* NOTE: This macro can only be used if there are no local + variables defined. This function uses a static variable so it's + use is permitted. If the variable were not static portYIELD() + would have to be used in it's place. */ + portTASK_SWITCH_FROM_ISR(); + } + } + +#pragma CODE_SEG DEFAULT + + diff --git a/20080212/Demo/HCS12_CodeWarrior_small/prm/burner.bbl b/20080212/Demo/HCS12_CodeWarrior_small/prm/burner.bbl new file mode 100644 index 000000000..639ffdef3 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_small/prm/burner.bbl @@ -0,0 +1,223 @@ +/* logical s-record file */ +OPENFILE "%ABS_FILE%.s19" +format=motorola +busWidth=1 +origin=0 +len=0x1000000 +destination=0 +SRECORD=Sx +SENDBYTE 1 "%ABS_FILE%" +CLOSE + +/* physical s-record file */ +OPENFILE "%ABS_FILE%.phy" +format = motorola +busWidth = 1 +len = 0x4000 + +origin = 0x008000 +destination = 0x000000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x018000 +destination = 0x004000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x028000 +destination = 0x008000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x038000 +destination = 0x00C000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x048000 +destination = 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0x004000 +destination = 0x0F8000 +SENDBYTE 1 "%ABS_FILE%" + +origin = 0x3F8000 +destination = 0x0FC000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x00C000 +destination = 0x0FC000 +SENDBYTE 1 "%ABS_FILE%" + +CLOSE + diff --git a/20080212/Demo/HCS12_CodeWarrior_small/readme.txt b/20080212/Demo/HCS12_CodeWarrior_small/readme.txt new file mode 100644 index 000000000..417a9af56 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_small/readme.txt @@ -0,0 +1,117 @@ +//------------------------------------------------------------------------ +// Readme.txt +//------------------------------------------------------------------------ +This project stationery is designed to get you up and running +quickly with CodeWarrior for MC9S12C32. +It is set up for the selected CPU and target connection, +but can be easily modified. + +Sample code for the following language(s) is at your disposal: +- C + +The wizard has prepared CodeWarrior target(s) with the connection methods of +your choice: +- Simulator: + This interface/target is prepared to use the FCS (Full Chip Simulation). + +- SofTec: + This target interface connects to any of the USB-based SofTec Microsystems tools for HC(S)12. + + +Additional connections can be chosen in the simulator/debugger, +use the menu Component > Set Target. + +//------------------------------------------------------------------------ +// Processor Expert +//------------------------------------------------------------------------ +This project is prepared to be designed with Processor Expert. +The project has an additional 'tab' named 'Processor Expert' where you +can configure the CPU and its beans. +The CPU selected is inserted into the Processor Expert project panel, in +the Debug and Release configurations. +Change of the configuration is possible by the mouse double-click on it. +All the installed Embedded Beans are accessible in the Bean Selector +window, grouped into folders according to their function. The mouse +double-click on selected Embedded Bean in the Bean Selector window adds +the Bean to the project. The mouse double-click on the Bean icon in the +Project panel opens the Bean Inspector window, which is used to set the +Bean properties. Source code is generated after selecting the +(Code Design 'Project_name.mcp') menu command from the CodeWarrior main +window (Processor Expert > Code design 'Project_name.mcp'). +Use the bean methods and events to write your code in the main module +'Project_name'.c and the event module Events.c. + +For more help please read Processor Expert help: + (Processor Expert > Help > 'Topic'). + +The following folders are used in CodeWarrior project window for +ProcessorExpert: +- User modules: contains your sources. The main module 'Project_name'.c + and event module Events.c are located here after the Processor Expert + code generation. +- Prm: Linker parameter file used for linking. Note that the file used + for the linker is specified in the Linker Preference Panel. To open + the Preference Panel, please press or open the + (Edit > 'Current Build Target Name' Settings...) menu item in the + CodeWarrior main window menu, while the project window is opened). + After Processor Expert code generation 'Project_name'.prm file + will be placed here. You can switch off the .prm file generation in + Processor Expert if you want (in the CPU bean, Build Options) +- Generated code: this folder appears after the Processor Expert code + generation and contains generated code from Processor Expert. +- Doc: other files generated from the Processor Expert (documentation) + +//------------------------------------------------------------------------ +// Getting Started +//------------------------------------------------------------------------ +To build/debug your project, use the menu Project > Debug or press F5. +This will open the simulator/debugger. +Press again F5 in the debugger (or menu Run > Start/Continue) to start +the application. The menu Run > Halt or F6 stops the application. +In the debugger menu Component > Open you can load additional components. + +//------------------------------------------------------------------------ +// Project structure +//------------------------------------------------------------------------ +The project generated contains various files/folders: +- readme.txt: this file +- Sources: folder with the application source code +- Startup Code: C/C++ startup code +- Prm: + - burner.bbl file to generate S-Records +- Linker Map: the .map file generated by the linker +- Libraries: needed library files (ANSI, derivative header/implementation files) +- Debugger Project File: contains a .ini file for the debugger for each + connection +- Debugger Cmd Files: contains sub-folders for each connection with command + files + +//------------------------------------------------------------------------ +// Adding your own code +//------------------------------------------------------------------------ +Once everything is working as expected, you can begin adding your own code +to the project. Keep in mind that we provide this as an example of how to +get up and running quickly with CodeWarrior. There are certainly other +ways to handle interrupts and set up your linker command file. Feel free +to modify any of the source files provided. + +//------------------------------------------------------------------------ +// Simulator/Debugger: Additional components +//------------------------------------------------------------------------ +In the simulator/debugger, you can load additional components. Try the menu +Component > Open. + +//------------------------------------------------------------------------ +// Additional documentation +//------------------------------------------------------------------------ +Check out the online documentation provided. Use in CodeWarrior IDE the +menu Help > Online Manuals. + +//------------------------------------------------------------------------ +// Contacting Metrowerks +//------------------------------------------------------------------------ +For bug reports, technical questions, and suggestions, please use the +forms installed in the Release_Notes folder and send them to: +USA: support@metrowerks.com +EUROPE: support_europe@metrowerks.com +ASIA/PACIFIC: j-emb-sup@metrowerks.com \ No newline at end of file diff --git a/20080212/Demo/HCS12_CodeWarrior_small/serial/serial.c b/20080212/Demo/HCS12_CodeWarrior_small/serial/serial.c new file mode 100644 index 000000000..edbe1b702 --- /dev/null +++ b/20080212/Demo/HCS12_CodeWarrior_small/serial/serial.c @@ -0,0 +1,90 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER for port 1. + +Note that this driver is written to test the RTOS port and is not intended +to represent an optimised solution. */ + +/* Standard include files. */ +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "queue.h" +#include "task.h" + +/* Demo application include files. */ +#include "serial.h" + + +/* + * Initialise port 1 for interrupt driven communications. + */ +xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) +{ + return NULL; +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) +{ + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) +{ +signed portBASE_TYPE xReturn = pdPASS; + + return xReturn; +} +/*-----------------------------------------------------------*/ + +void vSerialClose( xComPortHandle xPort ) +{ + /* Not supported. */ + ( void ) xPort; +} +/*-----------------------------------------------------------*/ + diff --git a/20080212/Demo/HCS12_GCC_banked/FreeRTOSConfig.h b/20080212/Demo/HCS12_GCC_banked/FreeRTOSConfig.h new file mode 100644 index 000000000..effd50142 --- /dev/null +++ b/20080212/Demo/HCS12_GCC_banked/FreeRTOSConfig.h @@ -0,0 +1,102 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/** + * FreeRTOSConfig.h configures FreeRTOS for GCC/HCS12 version of FreeRTOS Demo + * + * Modified by Jefferson L Smith, Robotronics Inc. + */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/* This port requires the compiler to generate code for the BANKED memory +model. */ +#define BANKED_MODEL + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 0 +#define configTICK_RATE_HZ ( ( portTickType ) 977 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 300/*128*/ ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 10752 ) ) +#define configMAX_TASK_NAME_LEN ( 3 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 1 +#define configIDLE_SHOULD_YIELD 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* This parameter is normally affects the clock frequency. In this port, at the moment +it might just be used for reference. */ + +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 24000000 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + + + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/HCS12_GCC_banked/Makefile b/20080212/Demo/HCS12_GCC_banked/Makefile new file mode 100644 index 000000000..4d19f27c7 --- /dev/null +++ b/20080212/Demo/HCS12_GCC_banked/Makefile @@ -0,0 +1,64 @@ +# Demo for GCC/HCS12 port of FreeRTOS +# Author Jefferson Smith +# +SRCDIR=../.. +RTOS_BASEDIR=$(SRCDIR)/Source + +# what board to compile for +TARGET_BOARD ?= dragon12-rom +CPU=m68hcs12 + +DEVC_PREFIX=m6811-elf- +CC=$(DEVC_PREFIX)gcc +AS=$(DEVC_PREFIX)as +AR=$(DEVC_PREFIX)ar +OBJCOPY=$(DEVC_PREFIX)objcopy +OBJDUMP=$(DEVC_PREFIX)objdump + +CPPFLAGS+=-I. -I./asm-$(CPU)/arch-dragon12 -I../Common/include \ + -I$(RTOS_BASEDIR)/include -DGCC_HCS12 -DM6812_DEF_SCI=1 -DPORT_LED=M6811_PORTB + +CFLAGS+=-$(CPU) -mshort -mlong-calls -g -Os -Wall -Wmissing-prototypes \ + -Wno-char-subscripts -fomit-frame-pointer -msoft-reg-count=0 -mauto-incdec +#-Os -fomit-frame-pointer + +LDFLAGS+=-$(CPU) -mshort -mlong-calls -Wl,-T,ldscript-rtos.x + +OBJCOPY_FLAGS=--srec-len=0x20 --change-addresses 0xffff0000 + +CSRCS=main.c startup.c vectors.c serial.c sci.c ParTest.c gelfunc.c \ + ../Common/Minimal/flash.c \ + ../Common/Minimal/dynamic.c \ + ../Common/Minimal/BlockQ.c \ + ../Common/Minimal/PollQ.c \ + ../Common/Minimal/comtest.c \ + ../Common/Minimal/integer.c \ + ../Common/Minimal/death.c \ + +RTOS_OBJS = $(RTOS_BASEDIR)/portable/GCC/HCS12/port.c \ + $(RTOS_BASEDIR)/portable/MemMang/heap_2.c \ + $(RTOS_BASEDIR)/list.c \ + $(RTOS_BASEDIR)/tasks.c \ + $(RTOS_BASEDIR)/queue.c + +OBJS=$(CSRCS:.c=.o) $(RTOS_OBJS:.c=.o) + +# +# *.elf for the simulator and gdb +# *.s19 is original S Records from ld +# *.s2 is S2 Records (from SRecCvt.exe) +# +all:: main.elf main.lst main.s19 + +main.elf: $(OBJS) + $(CC) $(LDFLAGS) -o $@ $^ -lc -lbcc -lc + +%.lst: %.elf + $(OBJDUMP) -htS $< >$@ + +%.s19: %.elf + $(OBJCOPY) --output-target=srec $(OBJCOPY_FLAGS) $< $*.s19 + +clean:: + $(RM) $(OBJS) *.elf *.s19 + diff --git a/20080212/Demo/HCS12_GCC_banked/PE_Error.h b/20080212/Demo/HCS12_GCC_banked/PE_Error.h new file mode 100644 index 000000000..bc1ca1a57 --- /dev/null +++ b/20080212/Demo/HCS12_GCC_banked/PE_Error.h @@ -0,0 +1,53 @@ +/** ################################################################### +** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. +** Filename : PE_Error.H +** Project : RTOSDemo +** Processor : MC9S12DP256BCPV +** Beantype : PE_Error +** Version : Driver 01.00 +** Compiler : Metrowerks HC12 C Compiler +** Date/Time : 13/06/2005, 20:14 +** Abstract : +** This bean "PE_Error" contains internal definitions +** of the error constants. +** Settings : +** Contents : +** No public methods +** +** (c) Copyright UNIS, spol. s r.o. 1997-2002 +** UNIS, spol. s r.o. +** Jundrovska 33 +** 624 00 Brno +** Czech Republic +** http : www.processorexpert.com +** mail : info@processorexpert.com +** ###################################################################*/ + +#ifndef __PE_Error_H +#define __PE_Error_H + +#define ERR_OK 0 /* OK */ +#define ERR_SPEED 1 /* This device does not work in the active speed mode. */ +#define ERR_RANGE 2 /* Parameter out of range. */ +#define ERR_VALUE 3 /* Parameter of incorrect value. */ +#define ERR_OVERFLOW 4 /* Timer overflow. */ +#define ERR_MATH 5 /* Overflow during evaluation. */ +#define ERR_ENABLED 6 /* Device is enabled. */ +#define ERR_DISABLED 7 /* Device is disabled. */ +#define ERR_BUSY 8 /* Device is busy. */ +#define ERR_NOTAVAIL 9 /* Requested value or method not available. */ +#define ERR_RXEMPTY 10 /* No data in receiver. */ +#define ERR_TXFULL 11 /* Transmitter is full. */ +#define ERR_BUSOFF 12 /* Bus not available. */ +#define ERR_OVERRUN 13 /* Overrun error is detected. */ +#define ERR_FRAMING 14 /* Framing error is detected. */ +#define ERR_PARITY 15 /* Parity error is detected. */ +#define ERR_NOISE 16 /* Noise error is detected. */ +#define ERR_IDLE 17 /* Idle error is detectes. */ +#define ERR_FAULT 18 /* Fault error is detected. */ +#define ERR_BREAK 19 /* Break char is received during communication. */ +#define ERR_CRC 20 /* CRC error is detected. */ +#define ERR_ARBITR 21 /* A node losts arbitration. This error occurs if two nodes start transmission at the same time. */ +#define ERR_PROTECT 22 /* Protection error is detected. */ + +#endif //__PE_Error_H diff --git a/20080212/Demo/HCS12_GCC_banked/ParTest.c b/20080212/Demo/HCS12_GCC_banked/ParTest.c new file mode 100644 index 000000000..5943109e1 --- /dev/null +++ b/20080212/Demo/HCS12_GCC_banked/ParTest.c @@ -0,0 +1,88 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/** + * ParTest.c controls bits (LEDs) for GCC/HCS12 version of FreeRTOS Demo + * + * Modified from CodeWarrior/HCS12 by Jefferson L Smith, Robotronics Inc. + */ + +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "portable.h" + +/* Demo application include files. */ +#include "partest.h" + +#define LEDIO PORTIO_8(PORT_LED) + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ + /* This function is required as it is called from the standard demo + application files. It manipulates a bit to control one LED. */ + portENTER_CRITICAL(); + + if (xValue) { /* Is it one to be written? */ + LEDIO |= (1< +#include + +/* Initialize SCI serial port to default baudrate and enable. */ +extern inline void +serial_init (void) +{ + SCIBD = M6811_DEF_BAUD; + SCICR1 = 0x00; //typical 8 bit + SCICR2 = 0x0c; //Enable sci for polling +} + +/* Return != 0 if there is something to read on the serial line. */ +extern inline unsigned char +serial_receive_pending (void) +{ + return SCISR1 & RDRF; +} + +/* Wait until the SIO has finished to send the character. */ +extern inline void +serial_flush (void) +{ + while (!(SCISR1 & TDRE)) + cop_optional_reset (); +} + +/* Return != 0 if serial port is ready to send another char. */ +extern inline unsigned char +serial_send_ready (void) +{ + return SCISR1 & TDRE; +} + +/* Send the character on the serial line. */ +extern inline void +serial_send (char c) +{ + serial_flush (); + SCIDRL = c; + SCICR2 |= (1<<3); +} + +/* Wait for a character on the serial line and return it. */ +extern inline unsigned char +serial_recv (void) +{ + while (!(SCISR1 & RDRF)) + cop_optional_reset (); + + return SCIDRL; +} + +extern void serial_print (const char *msg); +extern void serial_getline (char *buf); + +#endif /* _M68HC11_SIO_H */ + diff --git a/20080212/Demo/HCS12_GCC_banked/cpu.h b/20080212/Demo/HCS12_GCC_banked/cpu.h new file mode 100644 index 000000000..dfbfbe767 --- /dev/null +++ b/20080212/Demo/HCS12_GCC_banked/cpu.h @@ -0,0 +1,39 @@ +/** + * sci.c controls SCI for GCC/HCS12 version of FreeRTOS Demo + * To replace CodeWarrior Cpu.h + * + * Author Jefferson L Smith, Robotronics Inc. + */ + +#ifndef __Cpu +#define __Cpu + +/*Types definition*/ +typedef unsigned char bool; +typedef unsigned char byte; +typedef unsigned int word; +typedef unsigned long dword; + +#define ATTR_INT __attribute__((interrupt)) +#define ATTR_FAR __attribute__((far)) +#define ATTR_NEAR __attribute__((near)) +#define ATTR_BANK0 __attribute__((far,section (".bank0"))) +#define ATTR_BANK1 __attribute__((far,section (".bank1"))) +#define ATTR_BANK2 __attribute__((far,section (".bank2"))) +#define ATTR_BANK3 __attribute__((far,section (".bank3"))) +#define ATTR_BANK4 __attribute__((far,section (".bank4"))) +#define ATTR_BANK5 __attribute__((far,section (".bank5"))) +#define ATTR_BANK6 __attribute__((far,section (".bank6"))) +#define ATTR_BANK7 __attribute__((far,section (".bank7"))) +#define ATTR_BANK8 __attribute__((far,section (".bank8"))) +#define ATTR_BANK9 __attribute__((far,section (".bank9"))) +#define ATTR_BANK10 __attribute__((far,section (".bank10"))) +#define ATTR_BANK11 __attribute__((far,section (".bank11"))) +#define ATTR_BANK12 __attribute__((far,section (".bank12"))) +#define ATTR_BANK13 __attribute__((far,section (".bank13"))) + +#include "PE_Error.h" +#include +#include + +#endif /* ifndef __Cpu */ diff --git a/20080212/Demo/HCS12_GCC_banked/gelfunc.c b/20080212/Demo/HCS12_GCC_banked/gelfunc.c new file mode 100644 index 000000000..dcecfb4da --- /dev/null +++ b/20080212/Demo/HCS12_GCC_banked/gelfunc.c @@ -0,0 +1,25 @@ +/* gelfunc.c -- functions from GEL 1.6 + Author Jefferson Smith, Robotronics Inc. + +*/ + +#include "asm-m68hcs12/ports_def.h" +void cop_reset (void); +void cop_optional_reset (void); + +/* Reset the COP. */ +void +cop_reset (void) +{ + ARMCOP = 0x55; + ARMCOP = 0xAA; +} + +void +cop_optional_reset (void) +{ +#if defined(M6811_USE_COP) && M6811_USE_COP == 1 + cop_reset (); +#endif +} + diff --git a/20080212/Demo/HCS12_GCC_banked/ldscript-rtos.x b/20080212/Demo/HCS12_GCC_banked/ldscript-rtos.x new file mode 100644 index 000000000..c495844ea --- /dev/null +++ b/20080212/Demo/HCS12_GCC_banked/ldscript-rtos.x @@ -0,0 +1,266 @@ +/* Linker script for MC689S12DP256 Flash + rom banks. + + Author Jefferson L Smith; Robotronics, Inc. 2006 + */ +OUTPUT_FORMAT("elf32-m68hc12", "elf32-m68hc12", + "elf32-m68hc12") +OUTPUT_ARCH(m68hc12) +ENTRY(_start) + +/* Get memory banks definition from some user configuration file. + This file must be located in some linker directory (search path + with -L

). See fixed memory banks emulation script. */ +INCLUDE memory.x; + +SECTIONS +{ + /* Concatenate .page0 sections. Put them in the page0 memory bank + unless we are creating a relocatable file. */ + .page0 : + { + *(.page0) + } > page0 + + /* PPAGE memory banks */ + + .bank0 : + { + *(.bank0) + . = ALIGN(2); + } > bank0 =0xff + .bank1 : + { + *(.bank1) + . = ALIGN(2); + } > bank1 =0xff + .bank2 : + { + *(.bank2) + . = ALIGN(2); + } > bank2 =0xff + .bank3 : + { + *(.bank3) + . = ALIGN(2); + } > bank3 =0xff + .bank4 : + { + *(.bank4) + . = ALIGN(2); + } > bank4 =0xff + .bank5 : + { + *(.bank5) + . = ALIGN(2); + } > bank5 =0xff + .bank6 : + { + *(.bank6) + . = ALIGN(2); + } > bank6 =0xff + .bank7 : + { + *(.bank7) + . = ALIGN(2); + } > bank7 =0xff + .bank8 : + { + *(.bank8) + . = ALIGN(2); + } > bank8 =0xff + .bank9 : + { + *(.bank9) + . = ALIGN(2); + } > bank9 =0xff + .bank10 : + { + *(.bank10) + . = ALIGN(2); + } > bank10 =0xff + .bank11 : + { + *(.bank11) + . = ALIGN(2); + } > bank11 =0xff + .bank12 : + { + *(.bank12) + . = ALIGN(2); + } > bank12 =0xff + .bank13 : + { + *(.bank13) + . = ALIGN(2); + } > bank13 =0xff + + /* Start of text section. */ + .text : + { + /* Put startup code at beginning so that _start keeps same address. */ + /* Startup code. */ + KEEP (*(.install0)) /* Section should setup the stack pointer. */ + KEEP (*(.install1)) /* Place holder for applications. */ + KEEP (*(.install2)) /* Optional installation of data sections in RAM. */ + KEEP (*(.install3)) /* Place holder for applications. */ + KEEP (*(.install4)) /* Section that calls the main. */ + *(.init) + *(.text) + *(.text.*) + *(.text_c) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + *(.gnu.linkonce.t.*) + *(.tramp) + *(.tramp.*) + /* Finish code. */ + KEEP (*(.fini0)) /* Beginning of finish code (_exit symbol). */ + KEEP (*(.fini1)) /* Place holder for applications. */ + KEEP (*(.fini2)) /* C++ destructors. */ + KEEP (*(.fini3)) /* Place holder for applications. */ + KEEP (*(.fini4)) /* Runtime exit. */ + _etext = .; + PROVIDE (etext = .); + . = ALIGN(2); + } > text AT>bank14 =0xff + + .text_h : + { + *(.text_h) /* Bootloader; high Flash area unbanked */ + . = ALIGN(2); + } > text_h AT>bank15 =0xff + .rodata : + { + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r*) + . = ALIGN(2); + } > text_h AT>bank15 =0xff + .eh_frame : + { + KEEP (*(.eh_frame)) + . = ALIGN(2); + } > text_h AT>bank15 =0xff + + /* Constructor and destructor tables are in ROM. */ + .ctors : + { + PROVIDE (__CTOR_LIST__ = .); + KEEP (*(.ctors)) + PROVIDE(__CTOR_END__ = .); + . = ALIGN(2); + } > text_h AT>bank15 =0xff + .dtors : + { + PROVIDE(__DTOR_LIST__ = .); + KEEP (*(.dtors)) + PROVIDE(__DTOR_END__ = .); + . = ALIGN(2); + } > text_h AT>bank15 =0xff + + /* Start of the data section image in ROM. */ + __data_image = .; + PROVIDE (__data_image = .); + + /* All read-only sections that normally go in PROM must be above. + We construct the DATA image section in PROM at end of all these + read-only sections. The data image must be copied at init time. + Refer to GNU ld, Section 3.6.8.2 Output Section LMA. */ + .data : + { + __data_section_start = .; + PROVIDE (__data_section_start = .); + *(.sdata) + *(.data) + *(.data.*) + *(.data1) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = .; + PROVIDE (edata = .); + . = ALIGN(2); + } > data AT>bank15 =0xff + __data_section_size = SIZEOF(.data); + __data_image_end = __data_image + __data_section_size; + PROVIDE (__data_section_size = SIZEOF(.data)); + /* .install : + { + . = _data_image_end; + } > text */ + /* Relocation for some bss and data sections. */ + .softregs : + { + __softregs_section_start = .; + *(.softregs) + __softregs_section_end = .; + } > data + __softregs_section_size = SIZEOF(.softregs); + .bss : + { + __bss_start = .; + *(.sbss) + *(.scommon) + *(.dynbss) + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + PROVIDE (_end = .); + } > data + __bss_size = SIZEOF(.bss); + PROVIDE (__bss_size = SIZEOF(.bss)); + .eeprom : + { + *(.eeprom) + *(.eeprom.*) + . = ALIGN(2); + } > eeprom =0xff + + /* If the 'vectors_addr' symbol is defined, it indicates the start address + of interrupt vectors. This depends on the 9S12 operating mode: + Addr + Hardware location LMA 0x10ff80, mirror 0xff80 + Called by dbug12 LMA 0x10ef80, mirror 0xef80 + Ram called by dbug12 0x3e00 + The default vectors address is (LMA) 0x10ff80. This can be overriden + with the '-defsym vectors_addr=0x...' ld option. + */ + PROVIDE (_vectors_addr = DEFINED (vectors_addr) ? vectors_addr : 0x10ff80); + .vectors DEFINED (vectors_addr) ? vectors_addr : 0x10ff80 : + { + KEEP (*(.vectors)) + } + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. + Treatment of DWARF debug section must be at end of the linker + script to avoid problems when there are undefined symbols. It's necessary + to avoid that the DWARF section is relocated before such undefined + symbols are found. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info) *(.gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } +} diff --git a/20080212/Demo/HCS12_GCC_banked/main.c b/20080212/Demo/HCS12_GCC_banked/main.c new file mode 100644 index 000000000..6ccee2035 --- /dev/null +++ b/20080212/Demo/HCS12_GCC_banked/main.c @@ -0,0 +1,301 @@ + +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +/* + * + * main() creates all the demo application tasks, then starts the scheduler. + * The WEB documentation provides more details of the demo application tasks. + * + * main.c also creates a task called "Check". This only executes every three + * seconds but has the highest priority so is guaranteed to get processor time. + * Its main function is to check that all the other tasks are still operational. + * Each task (other than the "flash" tasks) maintains a unique count that is + * incremented each time the task successfully completes its function. Should + * any error occur within such a task the count is permanently halted. The + * check task inspects the count of each task to ensure it has changed since + * the last time the check task executed. If all the count variables have + * changed all the tasks are still executing error free, and the check task + * toggles the onboard LED. Should any task contain an error at any time + * the LED toggle rate will change from 3 seconds to 500ms. + * + * This file also includes the functionality implemented within the + * standard demo application file integer.c. This is done to demonstrate the + * use of an idle hook. See the documentation within integer.c for the + * rationale of the integer task functionality. + * */ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +#include "cpu.h" + +/* special prototypes for memory-banked functions */ +void vStartPolledQueueTasks( unsigned portBASE_TYPE uxPriority ); +portBASE_TYPE xArePollingQueuesStillRunning( void ); + +/* Demo application includes. */ +#include "flash.h" +#include "PollQ.h" +#include "dynamic.h" +#include "partest.h" +#include "comtest2.h" +#include "BlockQ.h" +#include "integer.h" +#include "death.h" + + +/*----------------------------------------------------------- + Definitions. +-----------------------------------------------------------*/ + +/* Priorities assigned to demo application tasks. */ +#define mainFLASH_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainDEATH_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* LED that is toggled by the check task. The check task periodically checks +that all the other tasks are operating without error. If no errors are found +the LED is toggled with mainCHECK_PERIOD frequency. If an error is found +then the toggle rate increases to mainERROR_CHECK_PERIOD. */ +#define mainCHECK_TASK_LED ( 7 ) +#define mainCHECK_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS ) +#define mainERROR_CHECK_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS ) + +/* The constants used in the idle task calculation. */ +#define intgCONST1 ( ( portLONG ) 123 ) +#define intgCONST2 ( ( portLONG ) 234567 ) +#define intgCONST3 ( ( portLONG ) -3 ) +#define intgCONST4 ( ( portLONG ) 7 ) +#define intgEXPECTED_ANSWER ( ( ( intgCONST1 + intgCONST2 ) * intgCONST3 ) / intgCONST4 ) + + +/* Baud rate used by the serial port tasks (ComTest tasks). +IMPORTANT: The function COM0_SetBaudRateValue() which is generated by the +Processor Expert is used to set the baud rate. As configured in the FreeRTOS +download this value must be one of the following: + +0 to configure for 38400 baud. +1 to configure for 19200 baud. +2 to configure for 9600 baud. +3 to configure for 4800 baud. */ +#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 2 ) + +/* LED used by the serial port tasks. This is toggled on each character Tx, +and mainCOM_TEST_LED + 1 is toggles on each character Rx. */ +#define mainCOM_TEST_LED ( 3 ) + +/*----------------------------------------------------------- + Local functions prototypes. +-----------------------------------------------------------*/ + +/* + * The 'Check' task function. See the explanation at the top of the file. + */ +static void ATTR_BANK1 vErrorChecks( void* pvParameters ); + +/* + * The idle task hook - in which the integer task is implemented. See the + * explanation at the top of the file. + */ +void ATTR_BANK0 vApplicationIdleHook( void ); + +/* + * Checks the unique counts of other tasks to ensure they are still operational. + */ +static portLONG ATTR_BANK0 prvCheckOtherTasksAreStillRunning( void ); + + + +/*----------------------------------------------------------- + Local variables. +-----------------------------------------------------------*/ + +/* A few tasks are defined within this file. This flag is used to indicate +their status. If an error is detected in one of the locally defined tasks then +this flag is set to pdTRUE. */ +portBASE_TYPE xLocalError = pdFALSE; + + +/*-----------------------------------------------------------*/ + +/* This is called from startup. */ +int ATTR_BANK0 main ( void ) +{ + /* Start some of the standard demo tasks. */ + vStartLEDFlashTasks( mainFLASH_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartDynamicPriorityTasks(); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + + /* Start the locally defined tasks. There is also a task implemented as + the idle hook. */ + xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Must be the last demo created. */ + vCreateSuicidalTasks( mainDEATH_PRIORITY ); + + /* All the tasks have been created - start the scheduler. */ + vTaskStartScheduler(); + + /* Should not reach here! */ + for( ;; ); + return 0; +} +/*-----------------------------------------------------------*/ + +static void vErrorChecks( void *pvParameters ) +{ +portTickType xDelayPeriod = mainCHECK_PERIOD; +portTickType xLastWakeTime; + + /* Initialise xLastWakeTime to ensure the first call to vTaskDelayUntil() + functions correctly. */ + xLastWakeTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Delay until it is time to execute again. The delay period is + shorter following an error. */ + vTaskDelayUntil( &xLastWakeTime, xDelayPeriod ); + + /* Check all the demo application tasks are executing without + error. If an error is found the delay period is shortened - this + has the effect of increasing the flash rate of the 'check' task + LED. */ + if( prvCheckOtherTasksAreStillRunning() == pdFAIL ) + { + /* An error has been detected in one of the tasks - flash faster. */ + xDelayPeriod = mainERROR_CHECK_PERIOD; + } + + /* Toggle the LED each cycle round. */ + vParTestToggleLED( mainCHECK_TASK_LED ); + } +} +/*-----------------------------------------------------------*/ + +static portLONG prvCheckOtherTasksAreStillRunning( void ) +{ +portBASE_TYPE xAllTasksPassed = pdPASS; + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + xAllTasksPassed = pdFAIL; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + xAllTasksPassed = pdFAIL; + } + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + xAllTasksPassed = pdFALSE; + } + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + xAllTasksPassed = pdFALSE; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + xAllTasksPassed = pdFALSE; + } + + if( xIsCreateTaskStillRunning() != pdTRUE ) + { + xAllTasksPassed = pdFALSE; + } + + /* Also check the status flag for the tasks defined within this function. */ + if( xLocalError != pdFALSE ) + { + xAllTasksPassed = pdFAIL; + } + + return xAllTasksPassed; +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ +/* This variable is effectively set to a constant so it is made volatile to +ensure the compiler does not just get rid of it. */ +volatile portLONG lValue; + + /* Keep performing a calculation and checking the result against a constant. */ + + /* Perform the calculation. This will store partial value in + registers, resulting in a good test of the context switch mechanism. */ + lValue = intgCONST1; + lValue += intgCONST2; + lValue *= intgCONST3; + lValue /= intgCONST4; + + /* Did we perform the calculation correctly with no corruption? */ + if( lValue != intgEXPECTED_ANSWER ) + { + /* Error! */ + portENTER_CRITICAL(); + xLocalError = pdTRUE; + portEXIT_CRITICAL(); + } + + /* Yield in case cooperative scheduling is being used. */ + #if configUSE_PREEMPTION == 0 + { + taskYIELD(); + } + #endif +} +/*-----------------------------------------------------------*/ + diff --git a/20080212/Demo/HCS12_GCC_banked/memory.x b/20080212/Demo/HCS12_GCC_banked/memory.x new file mode 100644 index 000000000..97ff4b6dc --- /dev/null +++ b/20080212/Demo/HCS12_GCC_banked/memory.x @@ -0,0 +1,63 @@ +/* Flash Memory Banks + For Wytec Dragon12, Technological Arts Adapt9S12DP256 + with DBug12 v4 bootloader + + Author Jefferson L Smith; Robotronics, Inc. + */ + +MEMORY +{ + page0 (rwx) : ORIGIN = 0x0, LENGTH = 256 + + /* RAM */ + data (rwx) : ORIGIN = 0x1000, LENGTH = 12k + + eeprom (rx): ORIGIN = 0x0400, LENGTH = 3k + text (rx) : ORIGIN = 0x4000, LENGTH = 16k + + /* high fixed bank, reserve 0x100 vectors and security. */ + text_h (rx) : ORIGIN = 0xc000, LENGTH = 16k-0x100 + + /* Flash memory banks */ + bank0 (rx) : ORIGIN = 0x0d0000, LENGTH = 16k + bank1 (rx) : ORIGIN = 0x0d4000, LENGTH = 16k + bank2 (rx) : ORIGIN = 0x0d8000, LENGTH = 16k + bank3 (rx) : ORIGIN = 0x0dc000, LENGTH = 16k + bank4 (rx) : ORIGIN = 0x0e0000, LENGTH = 16k + bank5 (rx) : ORIGIN = 0x0e4000, LENGTH = 16k + bank6 (rx) : ORIGIN = 0x0e8000, LENGTH = 16k + bank7 (rx) : ORIGIN = 0x0ec000, LENGTH = 16k + bank8 (rx) : ORIGIN = 0x0f0000, LENGTH = 16k + bank9 (rx) : ORIGIN = 0x0f4000, LENGTH = 16k + bank10 (rx) : ORIGIN = 0x0f8000, LENGTH = 16k + bank11 (rx) : ORIGIN = 0x0fc000, LENGTH = 16k + bank12 (rx) : ORIGIN = 0x100000, LENGTH = 16k + bank13 (rx) : ORIGIN = 0x104000, LENGTH = 16k + + bank14 (rx) : ORIGIN = 0x108000, LENGTH = 16k + bank15 (rx) : ORIGIN = 0x10c000, LENGTH = 16k-0x100 +} +/* Setup the stack on the top of the data memory bank. */ +PROVIDE (_stack = 0x1000+12k); + +/* interrupt/reset vectors*/ +vectors_addr = 0x10ff80; + +SECTIONS +{ + /* PPAGE memory banks */ + + .bank2 : + { + ../Common/Minimal/flash.o(.text .rodata) + *(.bank2) + } > bank2 + + .bank3 : + { + ParTest.o(.text .rodata) + *(.bank3) + } > bank3 + +} + diff --git a/20080212/Demo/HCS12_GCC_banked/sci.c b/20080212/Demo/HCS12_GCC_banked/sci.c new file mode 100644 index 000000000..d32f7cde4 --- /dev/null +++ b/20080212/Demo/HCS12_GCC_banked/sci.c @@ -0,0 +1,75 @@ +/** + * sci.c controls SCI for GCC/HCS12 version of FreeRTOS Demo + * Parts taken from the CodeWarrior Demo in order to work similar. + * + * Author Jefferson L Smith, Robotronics Inc. + */ + +#include "sci.h" +#include + +//static word SerFlag; /* Flags for serial communication */ + /* Bits: 0 - OverRun error */ + /* 1 - Framing error */ + /* 2 - Parity error */ + /* 3 - Char in RX buffer */ + /* 4 - Full TX buffer */ + /* 5 - Running int from TX */ + /* 6 - Full RX buffer */ + /* 7 - Noise error */ + /* 8 - Idle character */ + /* 9 - Break detected */ + /* 10 - Unused */ +static word PrescaleValue; +//static byte NumMode; /* Number of selected baud mode */ + + +/** + * SCI_SetBaudRateMode + * + * Changes the speed (baud rate). + */ +byte SCI_SetBaudRateMode(byte Mod) +{ + // wired for 24 MHz bus --jeffs + static const word SCI_Presc[4] = {39,78,156,313}; + + if(Mod >= 4) /* Is mode in baud mode list */ + return ERR_VALUE; /* If no then error */ + //NumMode = Mod; /* New baud mode */ + PrescaleValue = SCI_Presc[Mod]; /* Prescaler in high speed mode */ + + /* SCI0CR1: LOOPS=0,SCISWAI=0,RSRC=0,M=0,WAKE=0,ILT=0,PE=0,PT=0 */ + SCICR1 = 0x00; /* Set the SCI configuration */ + /* SCI0SR2: ??=0,??=0,??=0,??=0,??=0,BRK13=0,TXDIR=0,RAF=0 */ + SCISR2 = 0x00; /* Set the Break Character Length and Transmitter pin data direction in Single-wire mode */ + SCISR1; /* Reset interrupt request flags */ + SCIBD = PrescaleValue; /* Set prescaler bits */ + /* SCI0CR2: SCTIE=0,TCIE=0,RIE=1,ILIE=0,TE=1,RE=1,RWU=0,SBK=0 */ + SCICR2 = 0x2c; /* Disable error interrupts */ + + return ERR_OK; /* OK */ +} + +#if 0 //(not used) + +/** + * SCI_Init (bean AsynchroSerial) + * + * This enables SCI. + */ +void SCI_Init(void) +{ + PrescaleValue = 39; /* Precaler in high speed mode */ + + /* SCI0CR1: LOOPS=0,SCISWAI=0,RSRC=0,M=0,WAKE=0,ILT=0,PE=0,PT=0 */ + SCICR1 = 0x00; /* Set the SCI configuration */ + /* SCI0SR2: ??=0,??=0,??=0,??=0,??=0,BRK13=0,TXDIR=0,RAF=0 */ + SCISR2 = 0x00; /* Set the Break Character Length and Transmitter pin data direction in Single-wire mode */ + SCISR1; /* Reset interrupt request flags */ + SCIBD = PrescaleValue; /* Set prescaler bits */ + /* SCI0CR2: SCTIE=0,TCIE=0,RIE=1,ILIE=0,TE=1,RE=1,RWU=0,SBK=0 */ + SCICR2 = 0x2c; /* Disable error interrupts */ +} +#endif + diff --git a/20080212/Demo/HCS12_GCC_banked/sci.h b/20080212/Demo/HCS12_GCC_banked/sci.h new file mode 100644 index 000000000..8a039f490 --- /dev/null +++ b/20080212/Demo/HCS12_GCC_banked/sci.h @@ -0,0 +1,34 @@ +/** + * sci.h controls SCI for GCC/HCS12 version of FreeRTOS Demo + * Parts taken from the CodeWarrior Demo in order to work similar. + * + * Author Jefferson L Smith, Robotronics Inc. + */ + +#ifndef __SCI +#define __SCI + +#include "cpu.h" + +#define COM0_Bm_38400baud 0 /* Constant for switch to mode 0 */ +#define COM0_Bm_19200baud 1 /* Constant for switch to mode 1 */ +#define COM0_Bm_9600baud 2 /* Constant for switch to mode 2 */ +#define COM0_Bm_4800baud 3 /* Constant for switch to mode 3 */ + + +/** + * SCI_SetBaudRateMode + * + * Changes the speed (baud rate). + */ +byte SCI_SetBaudRateMode(byte Mod); + + +/** + * SCI_Init (bean AsynchroSerial) + * + * This enables SCI. + */ +void SCI_Init(void); + +#endif /* ifndef __SCI */ diff --git a/20080212/Demo/HCS12_GCC_banked/serial.c b/20080212/Demo/HCS12_GCC_banked/serial.c new file mode 100644 index 000000000..93bc3b5d2 --- /dev/null +++ b/20080212/Demo/HCS12_GCC_banked/serial.c @@ -0,0 +1,150 @@ +/* + serial.c for using FreeRTOS + Copyright (C) 2005 Robotronics Inc. +*/ + + +/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER for port 1. + + GCC demo modifications by Jeff Smith, Robotronics Inc. 2005 +*/ + +#include "cpu.h" +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "queue.h" +#include "task.h" + +/* Demo application include files. */ +#include "sci.h" +#include "serial.h" + +/* The queues used to communicate between the task code and the interrupt +service routines. */ +static xQueueHandle xRxedChars; +static xQueueHandle xCharsForTx; + +/* Interrupt identification bits. */ +#define serOVERRUN_INTERRUPT ( '\x08' ) +#define serRX_INTERRUPT ( 0x20 ) +#define serTX_INTERRUPT ( 0x80 ) + +/*-----------------------------------------------------------*/ + + +/* + * Initialise port for interrupt driven communications. + */ +xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) +{ + /* Hardware setup is performed by the Processor Expert generated code. + This function just creates the queues used to communicate between the + interrupt code and the task code - then sets the required baud rate. */ + + xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + + SCI_SetBaudRateMode( ( portCHAR ) ulWantedBaud ); + + return NULL; +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) +{ + /* Get the next character from the buffer queue. Return false if no characters + are available, or arrive before xBlockTime expires. */ + if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) + { + return pdTRUE; + } + else + { + return pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) +{ + /* Place the character in the queue of characters to be transmitted. */ + if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) + { + return pdFAIL; + } + + /* Turn on the Tx interrupt so the ISR will remove the character from the + queue and send it. This does not need to be in a critical section as + if the interrupt has already removed the character the next interrupt + will simply turn off the Tx interrupt again. */ + SCICR2 |= 0x80; // TIE + + return pdPASS; +} +/*-----------------------------------------------------------*/ + +void vSerialClose( xComPortHandle xPort ) +{ + /* Not supported. */ + //( void ) xPort; +} +/*-----------------------------------------------------------*/ + + +/* + * Interrupt service routine for the serial port. Must be in non-banked + * memory. + */ + +void ATTR_INT ATTR_NEAR vCOM_ISR( void ); + +void vCOM_ISR( void ) +{ +volatile unsigned portCHAR ucByte, ucStatus; +portBASE_TYPE xTaskWokenByPost = pdFALSE, xTaskWokenByTx = pdFALSE; + + /* What caused the interrupt? */ + ucStatus = SCISR1; + + if( ucStatus & serOVERRUN_INTERRUPT ) + { + /* The interrupt was caused by an overrun. Clear the error by reading + the data register. */ + ucByte = SCIDRL; + } + else + if( ucStatus & serRX_INTERRUPT ) + { + /* The interrupt was caused by a character being received. + Read the received byte. */ + ucByte = SCIDRL; + + /* Post the character onto the queue of received characters - noting + whether or not this wakes a task. */ + xTaskWokenByPost = xQueueSendFromISR( xRxedChars, ( void * ) &ucByte, pdFALSE ); + } + + if( ( ucStatus & serTX_INTERRUPT ) && ( SCICR2 & 0x80 ) ) + { + /* The interrupt was caused by a character being transmitted. */ + if( xQueueReceiveFromISR( xCharsForTx, ( void * ) &ucByte, &xTaskWokenByTx ) == pdTRUE ) + { + /* Clear the SCRF bit. */ + SCIDRL = ucByte; + } + else + { + /* Disable transmit interrupt */ + SCICR2 &= ~0x80; // TIE + } + } + + if( ( xTaskWokenByPost ) || ( xTaskWokenByTx ) ) + { + portYIELD(); + } + +} + diff --git a/20080212/Demo/HCS12_GCC_banked/startup.c b/20080212/Demo/HCS12_GCC_banked/startup.c new file mode 100644 index 000000000..f7d8b5618 --- /dev/null +++ b/20080212/Demo/HCS12_GCC_banked/startup.c @@ -0,0 +1,96 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +/* + * startup.c + * Author Jefferson L Smith, Robotronics Inc. + * + * __premain() is the startup code to init hardware and ram to execute the + * C application. + * + */ + +#include +#include "cpu.h" + +void ATTR_NEAR __premain (void); + +void +__premain (void) +{ + // in case special mode enabled, avoid conflict on PORTE + PEAR |= NECLK; + // bgnd mode stops COP and RTI clocks + COPCTL = RSBCK; + // stops TCNT counter when debugging stops + TSCR1 |= (1<<5); // TFRZ + + // PLL + CLKSEL = 0; // disable PLL to configure + // xtal 16MHz, bus 24MHz + SYNR = 3 - 1; + REFDV = 2 - 1; + while (!(CRGFLG & 0x08)) // wait for PLL LOCK + cop_optional_reset(); + CLKSEL |= 0x80; // use PLL + + // init switch inputs + PERH = 0xff; // pullups + + // outputs +#if PORT_LED==M6811_PORTB //PORTB + DDRB = 0xff; // init LED +#elif PORT_LED==M6811_PORTA //PORTA + DDRA = 0xff; +#elif PORT_LED==M6811_PTT //PTT + DDRT = 0xff; +#elif PORT_LED==M6811_PTM //PTM + DDRM = 0xff; +#elif PORT_LED==M6811_PTP //PTP + DDRP = 0xff; +#elif PORT_LED==M6811_PTH //PTH + DDRH = 0xff; +#endif + +} + diff --git a/20080212/Demo/HCS12_GCC_banked/sys/interrupts.h b/20080212/Demo/HCS12_GCC_banked/sys/interrupts.h new file mode 100644 index 000000000..b783e4b95 --- /dev/null +++ b/20080212/Demo/HCS12_GCC_banked/sys/interrupts.h @@ -0,0 +1,73 @@ +/* Interrupt Vectors + Copyright (C) 2000, 2002, 2003 Free Software Foundation, Inc. + Written by Stephane Carrez (stcarrez@nerim.fr) + +This file is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by the +Free Software Foundation; either version 2, or (at your option) any +later version. + +In addition to the permissions in the GNU General Public License, the +Free Software Foundation gives you unlimited permission to link the +compiled version of this file with other programs, and to distribute +those programs without any restriction coming from the use of this +file. (The General Public License restrictions do apply in other +respects; for example, they cover modification of the file, and +distribution when not linked into another program.) + +This file is distributed in the hope that it will be useful, but +WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#ifndef _SYS_INTERRUPTS_H +#define _SYS_INTERRUPTS_H + +#include + +#ifdef mc6811 +//# include +#endif + +#ifdef mc68hcs12 +# include +#elif defined(mc6812) +//# include +#endif + +/*! Install an interrupt handler. + + Install the interrupt handler for an exception. The handler + is installed for \b bootstrap mode and also for \b normal operating + mode. + + @param id the interrupt number to be installed + @param handler the interrupt handler entry point +*/ +extern void +set_interrupt_handler (interrupt_vector_id id, interrupt_t handler); + +/*! Default and fatal interrupt handler. + + This function is an interrupt handler intended to be used to + handle all interrupt not used by a program. Since it is an + error to have an interrupt when it is not handled, the default + behavior is to print a message and stop. */ +extern void __attribute__((interrupt, noreturn)) +fatal_interrupt (void); + +#include + +/*! Entry point of any program. + + This function should never be called by itself. It represents the + entry point of any program. It is intended to be used in an + interrupt table to specify the function to jump to after reset. */ +extern void _start (void); + +#endif diff --git a/20080212/Demo/HCS12_GCC_banked/sys/param.h b/20080212/Demo/HCS12_GCC_banked/sys/param.h new file mode 100644 index 000000000..8dbf1a3a2 --- /dev/null +++ b/20080212/Demo/HCS12_GCC_banked/sys/param.h @@ -0,0 +1,56 @@ +/* param.h - Board specific parameters + Copyright (C) 2000, 2002, 2003 Free Software Foundation, Inc. + Written by Stephane Carrez (stcarrez@nerim.fr) + +This file is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by the +Free Software Foundation; either version 2, or (at your option) any +later version. + +In addition to the permissions in the GNU General Public License, the +Free Software Foundation gives you unlimited permission to link the +compiled version of this file with other programs, and to distribute +those programs without any restriction coming from the use of this +file. (The General Public License restrictions do apply in other +respects; for example, they cover modification of the file, and +distribution when not linked into another program.) + +This file is distributed in the hope that it will be useful, but +WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#ifndef _SYS_PARAM_H +#define _SYS_PARAM_H + +/*! Attribute unused. + Use this attribute to indicate that a parameter, a variable or a + static function is not used. The compiler will not warn about the + unused variable. */ +#define ATTRIBUTE_UNUSED __attribute__((unused)) + +/*! Attribute page0. + Use this attribute to put a global or static variable in page0. */ +#define PAGE0_ATTRIBUTE __attribute__((section(".page0"))) + +#ifdef mc6811 +//# include +#endif + +#ifdef mc68hcs12 +# include +#elif defined(mc6812) +//# include +#endif + +#include + +#define GNU_LINKER_WARNING(SYMBOL, MSG) \ + asm (".section .gnu.warning." SYMBOL "\n\t.string \"" MSG "\"\n\t.previous"); + +#endif diff --git a/20080212/Demo/HCS12_GCC_banked/sys/ports.h b/20080212/Demo/HCS12_GCC_banked/sys/ports.h new file mode 100644 index 000000000..934c2f399 --- /dev/null +++ b/20080212/Demo/HCS12_GCC_banked/sys/ports.h @@ -0,0 +1,69 @@ +/* sys/ports.h -- Definition of system ports + Copyright 2000, 2001, 2002 Free Software Foundation, Inc. + Written by Stephane Carrez (stcarrez@worldnet.fr) + +This file is part of GEL. + +GEL is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GEL is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GEL; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#ifndef _SYS_PORTS_H +#define _SYS_PORTS_H + +#ifdef __cplusplus +extern "C" { +#endif + + extern unsigned short get_timer_counter (void); + extern void set_timer_counter (unsigned short); + extern unsigned short get_input_capture_1 (void); + extern void set_input_capture_1 (unsigned short); + extern unsigned short get_input_capture_2 (void); + extern void set_input_capture_2 (unsigned short); + extern unsigned short get_input_capture_3 (void); + extern void set_input_capture_3 (unsigned short); + extern unsigned short get_output_compare_1 (void); + extern void set_output_compare_1 (unsigned short); + extern unsigned short get_output_compare_2 (void); + extern void set_output_compare_2 (unsigned short); + extern unsigned short get_output_compare_3 (void); + extern void set_output_compare_3 (unsigned short); + extern unsigned short get_output_compare_4 (void); + extern void set_output_compare_4 (unsigned short); + extern unsigned short get_output_compare_5 (void); + extern void set_output_compare_5 (unsigned short); + extern void set_bus_expanded (void); + extern void set_bus_single_chip (void); + extern void cop_reset (void); + extern void cop_optional_reset (void); + extern void timer_acknowledge (void); + extern void timer_initialize_rate (unsigned char); + +#ifdef mc6811 +//# include +#endif + +#ifdef mc68hcs12 +# include +#elif defined(mc6812) +//# include +#endif + +#ifdef __cplusplus +}; +#endif + +#endif /* _SYS_PORTS_H */ + diff --git a/20080212/Demo/HCS12_GCC_banked/sys/ports_def.h b/20080212/Demo/HCS12_GCC_banked/sys/ports_def.h new file mode 100644 index 000000000..8d2c74930 --- /dev/null +++ b/20080212/Demo/HCS12_GCC_banked/sys/ports_def.h @@ -0,0 +1,36 @@ +/* sys/ports_def.h -- Definition of system ports + Copyright 2000 Free Software Foundation, Inc. + Written by Stephane Carrez (stcarrez@worldnet.fr) + +This file is part of GEL. + +GEL is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GEL is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GEL; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#ifndef _SYS_PORTS_DEF_H +#define _SYS_PORTS_DEF_H + +#ifdef mc6811 +//# include +#endif + +#ifdef mc68hcs12 +# include +#elif defined(mc6812) +//# include +#endif + +#endif /* _SYS_PORTS_DEF_H */ + diff --git a/20080212/Demo/HCS12_GCC_banked/sys/sio.h b/20080212/Demo/HCS12_GCC_banked/sys/sio.h new file mode 100644 index 000000000..a28fe94fe --- /dev/null +++ b/20080212/Demo/HCS12_GCC_banked/sys/sio.h @@ -0,0 +1,80 @@ +/* sys/sio.h -- Utility methods to read/write the SIO + Copyright 2000 Free Software Foundation, Inc. + Written by Stephane Carrez (stcarrez@worldnet.fr) + +This file is part of GEL. + +GEL is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GEL is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GEL; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#ifndef _SYS_SIO_H +#define _SYS_SIO_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +extern void serial_init (void); + +/* Return != 0 if there is something to read on the serial line. */ +extern unsigned char serial_receive_pending (void); + +/* Wait until the SIO has finished to send the character. */ +extern void serial_flush (void); + +/* Return != 0 if serial port is ready to send another char. */ +extern unsigned char serial_send_ready (void); + +/* Send the character on the serial line. */ +extern void serial_send (char c); + +/* Wait for a character on the serial line and return it. */ +extern unsigned char serial_recv (void); + +/** Write the string on the serial line. + + @param msg null terminated string to write. + + @see serial_init, serial_send +*/ +extern void serial_print (const char *msg); + +/** Wait for a string from serial line. + + @param msg buffer that will hold the string. + + @see serial_init, serial_recv +*/ +extern void serial_getline (char *buf); + +#ifdef mc6811 +//# include +#endif + +#ifdef mc68hcs12 +# include +#elif defined(mc6812) +//# include +#endif + + +#ifdef __cplusplus +}; +#endif +#endif /* _SYS_SIO_H */ + diff --git a/20080212/Demo/HCS12_GCC_banked/vectors.c b/20080212/Demo/HCS12_GCC_banked/vectors.c new file mode 100644 index 000000000..2375a73b6 --- /dev/null +++ b/20080212/Demo/HCS12_GCC_banked/vectors.c @@ -0,0 +1,115 @@ +/* modrx.c -- wireless controller receiver for robots + Copyright 2004 Robotronics, Inc. + Author Jefferson Smith + + This file is part of the Modular Robot Design. +*/ + +#include "cpu.h" +#include +#include + +void fatal_interrupt () +{ + /* Infinite loop for debugging + Returning would not help as it's necessary to clear the interrupt flag. + */ + for (;;) cop_optional_reset(); +} + +#ifdef USE_INTERRUPT_TABLE + +/* NOTE: these ISR must be in non-banked memory (near) */ + +/* Manual context switch function. This is the SWI ISR. */ +void ATTR_INT ATTR_NEAR vPortYield( void ); + +/* Tick context switch function. This is the timer ISR. */ +void ATTR_INT ATTR_NEAR vPortTickInterrupt( void ); + +void ATTR_INT ATTR_NEAR vCOM_ISR( void ); + +/* Interrupt vectors table. + + Note: the `XXX_handler: foo' notation is a GNU extension which is + used here to ensure correct association of the handler in the struct. + This is why the order of handlers declared below does not follow + the MCU order. */ +const struct interrupt_vectors __attribute__((section(".vectors"))) vectors = +{ + pwm_shutdown_handler: fatal_interrupt, + ptpif_handler: fatal_interrupt, + can4_tx_handler: fatal_interrupt, + can4_rx_handler: fatal_interrupt, + can4_err_handler: fatal_interrupt, + can4_wake_handler: fatal_interrupt, + can3_tx_handler: fatal_interrupt, + can3_rx_handler: fatal_interrupt, + can3_err_handler: fatal_interrupt, + can3_wake_handler: fatal_interrupt, + can2_tx_handler: fatal_interrupt, + can2_rx_handler: fatal_interrupt, + can2_err_handler: fatal_interrupt, + can2_wake_handler: fatal_interrupt, + can1_tx_handler: fatal_interrupt, + can1_rx_handler: fatal_interrupt, + can1_err_handler: fatal_interrupt, + can1_wake_handler: fatal_interrupt, + can0_tx_handler: fatal_interrupt, + can0_rx_handler: fatal_interrupt, + can0_err_handler: fatal_interrupt, + can0_wake_handler: fatal_interrupt, + flash_handler: fatal_interrupt, + eeprom_handler: fatal_interrupt, + spi2_handler: fatal_interrupt, + spi1_handler: fatal_interrupt, + iic_handler: fatal_interrupt, + bdlc_handler: fatal_interrupt, + selfclk_mode_handler: fatal_interrupt, + pll_lock_handler: fatal_interrupt, + accb_overflow_handler: fatal_interrupt, + mccnt_underflow_handler: fatal_interrupt, + pthif_handler: fatal_interrupt, + ptjif_handler: fatal_interrupt, + atd1_handler: fatal_interrupt, + atd0_handler: fatal_interrupt, + sci1_handler: fatal_interrupt, + sci0_handler: fatal_interrupt, + spi0_handler: fatal_interrupt, + + /** Timer and Accumulator */ + acca_input_handler: fatal_interrupt, + acca_overflow_handler: fatal_interrupt, + timer_overflow_handler: fatal_interrupt, + + /** Input capture / Output compare Timers */ + tc7_handler: fatal_interrupt, + tc6_handler: fatal_interrupt, + tc5_handler: fatal_interrupt, + tc4_handler: fatal_interrupt, + tc3_handler: fatal_interrupt, + tc2_handler: fatal_interrupt, + tc1_handler: fatal_interrupt, + tc0_handler: fatal_interrupt, + + /** External Interrupts */ + rtii_handler: fatal_interrupt, + irq_handler: fatal_interrupt, + xirq_handler: fatal_interrupt, + + illegal_handler: fatal_interrupt, + cop_fail_handler: fatal_interrupt, + cop_clock_handler: fatal_interrupt, + + /** Vectors in use */ + swi_handler: vPortYield, + rtii_handler: vPortTickInterrupt, +#if M6812_DEF_SCI==1 + sci1_handler: vCOM_ISR, +#else + sci0_handler: vCOM_ISR, +#endif + reset_handler: _start +}; +#endif + diff --git a/20080212/Demo/MB91460_Softune/91460_template_91467d.dat b/20080212/Demo/MB91460_Softune/91460_template_91467d.dat new file mode 100644 index 000000000..ffa3fe96c --- /dev/null +++ b/20080212/Demo/MB91460_Softune/91460_template_91467d.dat @@ -0,0 +1,183 @@ +$CPUSERIES-911 +$Prj-STANDALONE +$0 +-g +-w 1 +-INF LIST +-I ".\SRC" +-I ".\SRC\watchdog" +-I "..\Common\include" +-I "..\..\Source\include" +-I "..\..\Source\portable\Softune\MB91460" +-I ".\SRC\utility" +-O 0 +-K SHORTADDRESS +-B +-K NOSCHEDULE +-K A1 +-K SARG +-Xdof +-INF STACK +-x vTaskIncrementTick,vTaskSwitchContext +-K NOEOPT +-K NOLIB +-K NOUNROLL +$other +-Xalign +-D__91467D +$time +1202736093 +$end +$1 +-g +-w 2 +-O 0 +-linf ON +-lsrc ON +-lsec ON +-lcros OFF +-linc ON +-lexp OBJ +-pl 60 +-pw 100 +-tab 8 +-Xdof +$other +$time +1119939829 +$end +$2 +-g +-AL 2 +-ra D_RAM=0x00028100/0x0002FFFF +-ra ID_RAM=0x00030000/0x00037FFF +-ro ROM_AREA=0x00040000/0x0014FFFF +-sc SSTACK/Stack+USTACK/Data+INIT/Data+DATA/Data=D_RAM +-sc IRAM/Code=ID_RAM +-sc CODE+@INIT+@IRAM+CONST=ROM_AREA +-sc CODE_START/Code=0x000F4000 +-sc INTVECT/Const=0x000FFC00 +-check_locate +-m +-mmi +-xlf +-slf +-mlf +-pl 60 +-pw 132 +-Xals +-Xalr +-na +-w 1 +-Xdof +$other +$time +1202753534 +$end +$3 +-dt s,d,r,a +-pl 60 +-pw 132 +-g +-Xdof +$other +$time +1202753534 +$end +$4 +-Xdof +$other +$time +1119274137 +$end +$5 +$other +$time +1119274137 +$end +$Prjend +$Prj-MONDEB_INTERNAL +$0 +-g +-w 1 +-O 4 +-K SPEED +-K LONGADDRESS +-B +-K SCHEDULE +-K A1 +-K SARG +-Xdof +-K EOPT +-K LIB +-K UNROLL +$other +-Xalign +$time +1161331678 +$end +$1 +-g +-w 2 +-O 0 +-linf ON +-lsrc ON +-lsec ON +-lcros OFF +-linc ON +-lexp OBJ +-pl 60 +-pw 100 +-tab 8 +-Xdof +$other +$time +1142592435 +$end +$2 +-g +-AL 2 +-ra D_RAM=0x00029000/0x0002FFFF +-ra ID_RAM=0x00030000/0x00037FFF +-ro ROM_AREA=0x00840000/0x0094FFFF +-ro SECURITY_AREA=0x00148000/0x0014800F +-sc DATA/Data+INIT/Data+SSTACK/Data+USTACK/Data=D_RAM +-sc IRAM/Code=ID_RAM +-sc CODE+@INIT+@IRAM+CONST=ROM_AREA +-sc CODE_START/Code=0x008F4000 +-check_locate +-m +-pl 60 +-pw 132 +-Xals +-Xalr +-na +-w 1 +-Xdof +$other +$time +1202753534 +$end +$3 +-dt s,d,r,a +-pl 60 +-pw 132 +-g +-Xdof +$other +$time +1202753534 +$end +$4 +-Xdof +$other +$time +1130252218 +$end +$5 +$other +$time +1130252218 +$end +$Prjend +$CPUSERIESEND diff --git a/20080212/Demo/MB91460_Softune/91467d_FreeRTOS.prj b/20080212/Demo/MB91460_Softune/91467d_FreeRTOS.prj new file mode 100644 index 000000000..e05a92c98 --- /dev/null +++ b/20080212/Demo/MB91460_Softune/91467d_FreeRTOS.prj @@ -0,0 +1,530 @@ +[Version] +DLLVer=02.5007.00.1 +PRJVer=1 + +[PRJKIND] +mode=1 + +[CPUTYPE] +CpuSerise=911 + +[DirInfo] +PRJ=C:\E\Dev\FreeRTOS\WorkingCopy2\Demo\MB91460_Softune\ + +[PrjInfo] +Count=2 +PrjInfo-0=STANDALONE +PrjInfo-1=MONDEB_INTERNAL +Active=STANDALONE + +[MEMBER] +F0=38 +F1=0 f Source Files +F2=0 c SRC\main.c +F3=0 a SRC\mb91467d.asm +F4=0 a SRC\Start91460.asm +F5=0 c SRC\vectors.c +F6=0 f Source Files\FreeRTOS +F7=0 c ..\..\Source\croutine.c +F8=0 c ..\..\Source\list.c +F9=0 c ..\..\Source\queue.c +F10=0 c ..\..\Source\tasks.c +F11=0 f Source Files\FreeRTOS\portable +F12=0 c ..\..\Source\portable\Softune\MB91460\__STD_LIB_sbrk.c +F13=0 c ..\..\Source\portable\Softune\MB91460\port.c +F14=0 f Source Files\FreeRTOS\portable\MemMang +F15=0 c ..\..\Source\portable\MemMang\heap_1.c +F16=0 c ..\..\Source\portable\MemMang\heap_2.c +F17=0 c ..\..\Source\portable\MemMang\heap_3.c +F18=0 f Source Files\serial +F19=0 c SRC\serial\serial.c +F20=0 f Source Files\watchdog +F21=0 c SRC\watchdog\watchdog.c +F22=0 f Source Files\utility +F23=0 c SRC\utility\taskutility.c +F24=0 f Source Files\Demo +F25=0 c ..\Common\Minimal\BlockQ.c +F26=0 c ..\Common\Minimal\blocktim.c +F27=0 c ..\Common\Minimal\comtest.c +F28=0 c ..\Common\Minimal\death.c +F29=0 c ..\Common\Minimal\dynamic.c +F30=0 c ..\Common\Minimal\flash.c +F31=0 c ..\Common\Minimal\flop.c +F32=0 c ..\Common\Minimal\GenQTest.c +F33=0 c ..\Common\Minimal\integer.c +F34=0 c SRC\partest\partest.c +F35=0 c ..\Common\Minimal\PollQ.c +F36=0 c ..\Common\Minimal\QPeek.c +F37=0 c ..\Common\Minimal\semtest.c +F38=0 f Include Files + +[OPTIONFILE] +FILE=91460_template_91467d.dat + +[CPUTYPE-STANDALONE] +CsvFile=Lib\911\911.csv +CpuName=MB91F467D +ChgChipInfo-0=12@16:0:17:1:18:2:19:3:20:4:21:5:22:6:23:7:24:8:25:9:26:10:27:11:28:12:29:13:30:14:31:15:32:16:33:17:34:18:35:19:36:20:37:21:38:22:39:23:40:24:41:25:42:26:43:27:44:28:45:29:46:30:47:31:48:32:49:33:50:34:51:35:52:36:53:37:54:38:55:39:56:40:57:41:58:42:59:43:60:44:61:45:62:46:63:47:64:48:65:49:66:50:67:51:68:52:69:53:70:54:71:55:72:56:73:57:74:58:75:59:76:60:77:61:78:62:79:63 +Count=1 +BusMode=2 +BusWidth=2 + +[DirInfo-STANDALONE] +CONFIG=STANDALONE\ +OBJ=STANDALONE\OBJ\ +LST=STANDALONE\LST\ +OPT=STANDALONE\OPT\ + +[MEMBER-STANDALONE] +F0=30 +F1=0 m 1 STANDALONE\ABS\91467d_FreeRTOS.abs +F2=9 c 1 ..\..\Source\portable\Softune\MB91460\port.c +F2-1=- ..\..\Source\include\FreeRTOS.h +F2-2=- ..\..\Source\include\projdefs.h +F2-3=- SRC\FreeRTOSConfig.h +F2-4=- ..\..\Source\include\portable.h +F2-5=- SRC\mb91467d.h +F2-6=- ..\..\Source\include\task.h +F2-7=- ..\..\Source\include\list.h +F2-8=- ..\..\Source\portable\Softune\MB91460\portmacro.h +F2-9=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h +F3=3 c 1 ..\..\Source\portable\Softune\MB91460\__STD_LIB_sbrk.c +F3-1=- SRC\FreeRTOSConfig.h +F3-2=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stdlib.h +F3-3=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h +F4=10 c 1 ..\..\Source\croutine.c +F4-1=- ..\..\Source\include\FreeRTOS.h +F4-2=- ..\..\Source\include\projdefs.h +F4-3=- SRC\FreeRTOSConfig.h +F4-4=- ..\..\Source\include\portable.h +F4-5=- ..\..\Source\include\task.h +F4-6=- ..\..\Source\include\list.h +F4-7=- ..\..\Source\include\croutine.h +F4-8=- ..\..\Source\portable\Softune\MB91460\portmacro.h +F4-9=- SRC\mb91467d.h +F4-10=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h +F5=9 c 1 ..\..\Source\list.c +F5-1=- ..\..\Source\include\FreeRTOS.h +F5-2=- ..\..\Source\include\projdefs.h +F5-3=- SRC\FreeRTOSConfig.h +F5-4=- ..\..\Source\include\portable.h +F5-5=- ..\..\Source\include\list.h +F5-6=- ..\..\Source\portable\Softune\MB91460\portmacro.h +F5-7=- SRC\mb91467d.h +F5-8=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stdlib.h +F5-9=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h +F6=12 c 1 ..\..\Source\queue.c +F6-1=- ..\..\Source\include\FreeRTOS.h +F6-2=- ..\..\Source\include\projdefs.h +F6-3=- SRC\FreeRTOSConfig.h +F6-4=- ..\..\Source\include\portable.h +F6-5=- ..\..\Source\portable\Softune\MB91460\portmacro.h +F6-6=- SRC\mb91467d.h +F6-7=- ..\..\Source\include\task.h +F6-8=- ..\..\Source\include\list.h +F6-9=- ..\..\Source\include\croutine.h +F6-10=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stdlib.h +F6-11=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h +F6-12=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\string.h +F7=13 c 1 ..\..\Source\tasks.c +F7-1=- ..\..\Source\include\FreeRTOS.h +F7-2=- ..\..\Source\include\projdefs.h +F7-3=- SRC\FreeRTOSConfig.h +F7-4=- ..\..\Source\include\portable.h +F7-5=- ..\..\Source\portable\Softune\MB91460\portmacro.h +F7-6=- SRC\mb91467d.h +F7-7=- ..\..\Source\include\task.h +F7-8=- ..\..\Source\include\list.h +F7-9=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stdio.h +F7-10=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h +F7-11=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stdarg.h +F7-12=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stdlib.h +F7-13=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\string.h +F8=2 c 1 SRC\vectors.c +F8-1=- SRC\mb91467d.h +F8-2=- SRC\watchdog\watchdog.h +F9=1 a 1 SRC\mb91467d.asm +F9-1=- SRC\mb91467d.h +F10=0 a 1 SRC\Start91460.asm +F11=12 c 1 ..\Common\Minimal\BlockQ.c +F11-1=- ..\..\Source\include\FreeRTOS.h +F11-2=- ..\..\Source\include\projdefs.h +F11-3=- SRC\FreeRTOSConfig.h +F11-4=- ..\..\Source\include\portable.h +F11-5=- ..\..\Source\portable\Softune\MB91460\portmacro.h +F11-6=- SRC\mb91467d.h +F11-7=- ..\..\Source\include\task.h +F11-8=- ..\..\Source\include\list.h +F11-9=- ..\..\Source\include\queue.h +F11-10=- ..\Common\include\BlockQ.h +F11-11=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stdlib.h +F11-12=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h +F12=11 c 1 ..\Common\Minimal\blocktim.c +F12-1=- ..\..\Source\include\FreeRTOS.h +F12-2=- ..\..\Source\include\projdefs.h +F12-3=- SRC\FreeRTOSConfig.h +F12-4=- ..\..\Source\include\portable.h +F12-5=- ..\..\Source\portable\Softune\MB91460\portmacro.h +F12-6=- SRC\mb91467d.h +F12-7=- ..\..\Source\include\task.h +F12-8=- ..\..\Source\include\list.h +F12-9=- ..\..\Source\include\queue.h +F12-10=- ..\Common\include\blocktim.h +F12-11=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h +F13=13 c 1 ..\Common\Minimal\comtest.c +F13-1=- ..\..\Source\include\FreeRTOS.h +F13-2=- ..\..\Source\include\projdefs.h +F13-3=- SRC\FreeRTOSConfig.h +F13-4=- ..\..\Source\include\portable.h +F13-5=- ..\..\Source\portable\Softune\MB91460\portmacro.h +F13-6=- SRC\mb91467d.h +F13-7=- ..\..\Source\include\task.h +F13-8=- ..\..\Source\include\list.h +F13-9=- ..\Common\include\serial.h +F13-10=- ..\Common\include\comtest.h +F13-11=- ..\Common\include\partest.h +F13-12=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stdlib.h +F13-13=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h +F14=11 c 1 ..\Common\Minimal\death.c +F14-1=- ..\..\Source\include\FreeRTOS.h +F14-2=- ..\..\Source\include\projdefs.h +F14-3=- SRC\FreeRTOSConfig.h +F14-4=- ..\..\Source\include\portable.h +F14-5=- ..\..\Source\portable\Softune\MB91460\portmacro.h +F14-6=- SRC\mb91467d.h +F14-7=- ..\..\Source\include\task.h +F14-8=- ..\..\Source\include\list.h +F14-9=- ..\Common\include\death.h +F14-10=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stdlib.h +F14-11=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h +F15=13 c 1 ..\Common\Minimal\dynamic.c +F15-1=- ..\..\Source\include\FreeRTOS.h +F15-2=- ..\..\Source\include\projdefs.h +F15-3=- SRC\FreeRTOSConfig.h +F15-4=- ..\..\Source\include\portable.h +F15-5=- ..\..\Source\portable\Softune\MB91460\portmacro.h +F15-6=- SRC\mb91467d.h +F15-7=- ..\..\Source\include\task.h +F15-8=- ..\..\Source\include\list.h +F15-9=- ..\..\Source\include\queue.h +F15-10=- ..\Common\include\dynamic.h +F15-11=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stdlib.h +F15-12=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h +F15-13=- ..\..\Source\include\semphr.h +F16=12 c 1 ..\Common\Minimal\flash.c +F16-1=- ..\..\Source\include\FreeRTOS.h +F16-2=- ..\..\Source\include\projdefs.h +F16-3=- SRC\FreeRTOSConfig.h +F16-4=- ..\..\Source\include\portable.h +F16-5=- ..\..\Source\portable\Softune\MB91460\portmacro.h +F16-6=- SRC\mb91467d.h +F16-7=- ..\..\Source\include\task.h +F16-8=- ..\..\Source\include\list.h +F16-9=- ..\Common\include\partest.h +F16-10=- ..\Common\include\flash.h +F16-11=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stdlib.h +F16-12=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h +F17=13 c 1 ..\Common\Minimal\flop.c +F17-1=- ..\..\Source\include\FreeRTOS.h +F17-2=- ..\..\Source\include\projdefs.h +F17-3=- SRC\FreeRTOSConfig.h +F17-4=- ..\..\Source\include\portable.h +F17-5=- ..\..\Source\portable\Softune\MB91460\portmacro.h +F17-6=- SRC\mb91467d.h +F17-7=- ..\..\Source\include\task.h +F17-8=- ..\..\Source\include\list.h +F17-9=- ..\Common\include\flop.h +F17-10=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stdlib.h +F17-11=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h +F17-12=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\math.h +F17-13=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\errno.h +F18=13 c 1 ..\Common\Minimal\GenQTest.c +F18-1=- ..\..\Source\include\FreeRTOS.h +F18-2=- ..\..\Source\include\projdefs.h +F18-3=- SRC\FreeRTOSConfig.h +F18-4=- ..\..\Source\include\portable.h +F18-5=- ..\..\Source\portable\Softune\MB91460\portmacro.h +F18-6=- SRC\mb91467d.h +F18-7=- ..\..\Source\include\task.h +F18-8=- ..\..\Source\include\list.h +F18-9=- ..\..\Source\include\queue.h +F18-10=- ..\Common\include\GenQTest.h +F18-11=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stdlib.h +F18-12=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h +F18-13=- ..\..\Source\include\semphr.h +F19=11 c 1 ..\Common\Minimal\integer.c +F19-1=- ..\..\Source\include\FreeRTOS.h +F19-2=- ..\..\Source\include\projdefs.h +F19-3=- SRC\FreeRTOSConfig.h +F19-4=- ..\..\Source\include\portable.h +F19-5=- ..\..\Source\portable\Softune\MB91460\portmacro.h +F19-6=- SRC\mb91467d.h +F19-7=- ..\..\Source\include\task.h +F19-8=- ..\..\Source\include\list.h +F19-9=- ..\Common\include\integer.h +F19-10=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stdlib.h +F19-11=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h +F20=12 c 1 ..\Common\Minimal\PollQ.c +F20-1=- ..\..\Source\include\FreeRTOS.h +F20-2=- ..\..\Source\include\projdefs.h +F20-3=- SRC\FreeRTOSConfig.h +F20-4=- ..\..\Source\include\portable.h +F20-5=- ..\..\Source\portable\Softune\MB91460\portmacro.h +F20-6=- SRC\mb91467d.h +F20-7=- ..\..\Source\include\task.h +F20-8=- ..\..\Source\include\list.h +F20-9=- ..\..\Source\include\queue.h +F20-10=- ..\Common\include\PollQ.h +F20-11=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stdlib.h +F20-12=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h +F21=13 c 1 ..\Common\Minimal\QPeek.c +F21-1=- ..\..\Source\include\FreeRTOS.h +F21-2=- ..\..\Source\include\projdefs.h +F21-3=- SRC\FreeRTOSConfig.h +F21-4=- ..\..\Source\include\portable.h +F21-5=- ..\..\Source\portable\Softune\MB91460\portmacro.h +F21-6=- SRC\mb91467d.h +F21-7=- ..\..\Source\include\task.h +F21-8=- ..\..\Source\include\list.h +F21-9=- ..\..\Source\include\queue.h +F21-10=- ..\Common\include\QPeek.h +F21-11=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stdlib.h +F21-12=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h +F21-13=- ..\..\Source\include\semphr.h +F22=13 c 1 ..\Common\Minimal\semtest.c +F22-1=- ..\..\Source\include\FreeRTOS.h +F22-2=- ..\..\Source\include\projdefs.h +F22-3=- SRC\FreeRTOSConfig.h +F22-4=- ..\..\Source\include\portable.h +F22-5=- ..\..\Source\portable\Softune\MB91460\portmacro.h +F22-6=- SRC\mb91467d.h +F22-7=- ..\..\Source\include\task.h +F22-8=- ..\..\Source\include\list.h +F22-9=- ..\..\Source\include\queue.h +F22-10=- ..\Common\include\semtest.h +F22-11=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stdlib.h +F22-12=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h +F22-13=- ..\..\Source\include\semphr.h +F23=10 c 1 ..\..\Source\portable\MemMang\heap_3.c +F23-1=- ..\..\Source\include\FreeRTOS.h +F23-2=- ..\..\Source\include\projdefs.h +F23-3=- SRC\FreeRTOSConfig.h +F23-4=- ..\..\Source\include\portable.h +F23-5=- ..\..\Source\portable\Softune\MB91460\portmacro.h +F23-6=- SRC\mb91467d.h +F23-7=- ..\..\Source\include\task.h +F23-8=- ..\..\Source\include\list.h +F23-9=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stdlib.h +F23-10=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h +F24=10 c 0 ..\..\Source\portable\MemMang\heap_1.c +F24-1=- ..\..\Source\include\FreeRTOS.h +F24-2=- ..\..\Source\include\projdefs.h +F24-3=- SRC\FreeRTOSConfig.h +F24-4=- ..\..\Source\include\portable.h +F24-5=- ..\..\Source\portable\Softune\MB91460\portmacro.h +F24-6=- SRC\mb91467d.h +F24-7=- ..\..\Source\include\task.h +F24-8=- ..\..\Source\include\list.h +F24-9=- ..\..\..\..\..\SoftuneV6_32bit_REV600008\LIB\911\INCLUDE\stdlib.h +F24-10=- ..\..\..\..\..\SoftuneV6_32bit_REV600008\LIB\911\INCLUDE\stddef.h +F25=10 c 0 ..\..\Source\portable\MemMang\heap_2.c +F25-1=- ..\..\Source\include\FreeRTOS.h +F25-2=- ..\..\Source\include\projdefs.h +F25-3=- SRC\FreeRTOSConfig.h +F25-4=- ..\..\Source\include\portable.h +F25-5=- ..\..\Source\portable\Softune\MB91460\portmacro.h +F25-6=- SRC\mb91467d.h +F25-7=- ..\..\Source\include\task.h +F25-8=- ..\..\Source\include\list.h +F25-9=- ..\..\..\..\..\SoftuneV6_32bit_REV600008\LIB\911\INCLUDE\stdlib.h +F25-10=- ..\..\..\..\..\SoftuneV6_32bit_REV600008\LIB\911\INCLUDE\stddef.h +F26=12 c 1 SRC\serial\serial.c +F26-1=- ..\..\Source\include\FreeRTOS.h +F26-2=- ..\..\Source\include\projdefs.h +F26-3=- SRC\FreeRTOSConfig.h +F26-4=- ..\..\Source\include\portable.h +F26-5=- ..\..\Source\portable\Softune\MB91460\portmacro.h +F26-6=- SRC\mb91467d.h +F26-7=- ..\..\Source\include\queue.h +F26-8=- ..\..\Source\include\task.h +F26-9=- ..\..\Source\include\list.h +F26-10=- ..\Common\include\serial.h +F26-11=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stdlib.h +F26-12=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h +F27=10 c 1 SRC\watchdog\watchdog.c +F27-1=- SRC\mb91467d.h +F27-2=- ..\..\Source\include\FreeRTOS.h +F27-3=- ..\..\Source\include\projdefs.h +F27-4=- SRC\FreeRTOSConfig.h +F27-5=- ..\..\Source\include\portable.h +F27-6=- ..\..\Source\portable\Softune\MB91460\portmacro.h +F27-7=- ..\..\Source\include\task.h +F27-8=- ..\..\Source\include\list.h +F27-9=- SRC\watchdog\watchdog.h +F27-10=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h +F28=12 c 1 SRC\utility\taskutility.c +F28-1=- SRC\mb91467d.h +F28-2=- SRC\vectors.h +F28-3=- ..\..\Source\include\FreeRTOS.h +F28-4=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h +F28-5=- ..\..\Source\include\projdefs.h +F28-6=- SRC\FreeRTOSConfig.h +F28-7=- ..\..\Source\include\portable.h +F28-8=- ..\..\Source\portable\Softune\MB91460\portmacro.h +F28-9=- ..\..\Source\include\task.h +F28-10=- ..\..\Source\include\list.h +F28-11=- ..\..\Source\include\semphr.h +F28-12=- ..\..\Source\include\queue.h +F29=25 c 1 SRC\main.c +F29-1=- SRC\mb91467d.h +F29-2=- SRC\vectors.h +F29-3=- SRC\watchdog\watchdog.h +F29-4=- ..\..\Source\include\FreeRTOS.h +F29-5=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h +F29-6=- ..\..\Source\include\projdefs.h +F29-7=- SRC\FreeRTOSConfig.h +F29-8=- ..\..\Source\include\portable.h +F29-9=- ..\..\Source\portable\Softune\MB91460\portmacro.h +F29-10=- ..\..\Source\include\task.h +F29-11=- ..\..\Source\include\list.h +F29-12=- ..\Common\include\flash.h +F29-13=- ..\Common\include\integer.h +F29-14=- ..\Common\include\comtest2.h +F29-15=- ..\Common\include\PollQ.h +F29-16=- ..\Common\include\semtest.h +F29-17=- ..\Common\include\BlockQ.h +F29-18=- ..\Common\include\dynamic.h +F29-19=- ..\Common\include\flop.h +F29-20=- ..\Common\include\GenQTest.h +F29-21=- ..\Common\include\QPeek.h +F29-22=- ..\Common\include\blocktim.h +F29-23=- ..\Common\include\death.h +F29-24=- SRC\utility\taskutility.h +F29-25=- ..\Common\include\partest.h +F30=9 c 1 SRC\partest\partest.c +F30-1=- SRC\mb91467d.h +F30-2=- ..\..\Source\include\FreeRTOS.h +F30-3=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h +F30-4=- ..\..\Source\include\projdefs.h +F30-5=- SRC\FreeRTOSConfig.h +F30-6=- ..\..\Source\include\portable.h +F30-7=- ..\..\Source\portable\Softune\MB91460\portmacro.h +F30-8=- ..\..\Source\include\task.h +F30-9=- ..\..\Source\include\list.h + +[BUILDMODE-STANDALONE] +kernel=1 + +[RUNSET-STANDALONE] +CONVERT=1 +CONVERTKIND=0 + +[DebState-STANDALONE] +SupCount=6 +Supfile-0=STANDALONE\Simulator.sup +Supfile-1=STANDALONE\MB2198-01-USB.sup +Supfile-2=STANDALONE\MB2198-01-COM1.sup +Supfile-3=STANDALONE\MB2198-01-LAN.sup +Supfile-4=STANDALONE\Mondeb_57K6_com1.sup +Supfile-5=STANDALONE\Mondeb_57K6_com2.sup +Current=Mondeb_57K6_com1.sup +AliasFile= +CPURunMode= + +[CPUTYPE-MONDEB_INTERNAL] +CsvFile=Lib\911\911.csv +CpuName=MB91F467D +Count=0 +BusMode=3 +BusWidth=2 + +[DirInfo-MONDEB_INTERNAL] +CONFIG=MONDEB_INTERNAL\ +OBJ=MONDEB_INTERNAL\OBJ\ +LST=MONDEB_INTERNAL\LST\ +OPT=MONDEB_INTERNAL\OPT\ + +[MEMBER-MONDEB_INTERNAL] +F0=30 +F1=0 m 1 MONDEB_INTERNAL\ABS\91467d_FreeRTOS.abs +F2=0 c 1 ..\..\Source\portable\Softune\MB91460\port.c +F3=0 c 1 ..\..\Source\portable\Softune\MB91460\__STD_LIB_sbrk.c +F4=0 c 1 ..\..\Source\croutine.c +F5=0 c 1 ..\..\Source\list.c +F6=0 c 1 ..\..\Source\queue.c +F7=0 c 1 ..\..\Source\tasks.c +F8=0 c 1 SRC\vectors.c +F9=0 a 1 SRC\mb91467d.asm +F10=0 a 1 SRC\Start91460.asm +F11=0 c 1 ..\Common\Minimal\BlockQ.c +F12=0 c 1 ..\Common\Minimal\blocktim.c +F13=0 c 1 ..\Common\Minimal\comtest.c +F14=0 c 1 ..\Common\Minimal\death.c +F15=0 c 1 ..\Common\Minimal\dynamic.c +F16=0 c 1 ..\Common\Minimal\flash.c +F17=0 c 1 ..\Common\Minimal\flop.c +F18=0 c 1 ..\Common\Minimal\GenQTest.c +F19=0 c 1 ..\Common\Minimal\integer.c +F20=0 c 1 ..\Common\Minimal\PollQ.c +F21=0 c 1 ..\Common\Minimal\QPeek.c +F22=0 c 1 ..\Common\Minimal\semtest.c +F23=0 c 1 ..\..\Source\portable\MemMang\heap_3.c +F24=0 c 1 ..\..\Source\portable\MemMang\heap_1.c +F25=0 c 1 ..\..\Source\portable\MemMang\heap_2.c +F26=0 c 1 SRC\serial\serial.c +F27=0 c 1 SRC\watchdog\watchdog.c +F28=0 c 1 SRC\utility\taskutility.c +F29=0 c 1 SRC\main.c +F30=0 c 1 SRC\partest\partest.c + +[BUILDMODE-MONDEB_INTERNAL] +kernel=1 + +[RUNSET-MONDEB_INTERNAL] +CONVERT=1 +CONVERTKIND=0 + +[DebState-MONDEB_INTERNAL] +SupCount=2 +Supfile-0=MONDEB_INTERNAL\Mondeb_57K6_com1.sup +Supfile-1=MONDEB_INTERNAL\Mondeb_57K6_com2.sup +Current=Mondeb_57K6_com1.sup +AliasFile= +CPURunMode= + +[AsmBefore] +Count=0 + +[AsmAfter] +Count=0 + +[CcBefore] +Count=0 + +[CcAfter] +Count=0 + +[LnkBefore] +Count=0 + +[LnkAfter] +Count=0 + +[LibBefore] +Count=0 + +[LibAfter] +Count=0 + +[CnvBefore] +Count=0 + +[CnvAfter] +Count=0 + +[ConfigBefore] +Count=0 + +[ConfigAfter] +Count=0 + diff --git a/20080212/Demo/MB91460_Softune/91467d_FreeRTOS.wsp b/20080212/Demo/MB91460_Softune/91467d_FreeRTOS.wsp new file mode 100644 index 000000000..512ab5b47 --- /dev/null +++ b/20080212/Demo/MB91460_Softune/91467d_FreeRTOS.wsp @@ -0,0 +1,25 @@ +[CPUTYPE] +CpuSerise=911 + +[PrjFile] +Count=1 +FILE-0=91467d_FreeRTOS.prj +ActivePrj=91467d_FreeRTOS.prj + +[SubPrj-91467d_FreeRTOS.prj] +Count=0 + +[DebState] +AutoSave=1 +Exec=0 +AutoLoad=1 + +[DirInfo] +WSP=C:\E\Dev\FreeRTOS\WorkingCopy2\Demo\MB91460_Softune\ + +[EditState] +STATE-1=SRC\main.c:18 +STATE-2=..\..\Source\queue.c:988 +STATE-3=..\..\Source\tasks.c:1342 +Count=3 + diff --git a/20080212/Demo/MB91460_Softune/PRC/set_MONITOR.prc b/20080212/Demo/MB91460_Softune/PRC/set_MONITOR.prc new file mode 100644 index 000000000..88927c74a --- /dev/null +++ b/20080212/Demo/MB91460_Softune/PRC/set_MONITOR.prc @@ -0,0 +1,53 @@ +# THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ +# MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ +# ELIGIBILITY FOR ANY PURPOSES. */ +# (C) Fujitsu Microelectronics Europe GmbH */ + +# Environment and memory manioulation after program upload + + +# Settings +SET VARIABLE abortIRQ0 = 0x1 +SET VARIABLE intVectorMonitorDebugger = 0x10FFC00 + + + + +# Disable all Interrupts +SET REGISTER I = 0x0 + +# Set Table Base Register +SET REGISTER TBR = intVectorMonitorDebugger + +# Run to smd_tbr and save TBR of Application +go ,Start91460\smd_tbr +SET VARIABLE intVectorApllication = %r0 +SET REGISTER TBR = intVectorApllication + +# Copy required vector table entries of monitor debugger in vector table of application +MOVE intVectorMonitorDebugger + 0x3C0..intVectorMonitorDebugger + 0x3FF, intVectorApllication + 0x3C0 + +# Prepare Entries for INT0 +IF %abortIRQ0 == 1 + MOVE intVectorMonitorDebugger + 0x3C0..intVectorMonitorDebugger + 0x3C3, intVectorApllication + 0x3BC + SET MEMORY/BYTE 0x32 = 0x3 + SET MEMORY/BYTE 0x30 = 0x0 + SET MEMORY/BYTE 0x31 = 0x1 + SET MEMORY/BYTE 0x440 = 0x10 + SET REGISTER ILM = 0x1E +ENDIF + +# Setting indicates software reset, which leads to that the clock settings are not changed. +SET REGISTER R4 = 0x8 + + +# Set TBR to Vector table of application +SET REGISTER TBR = intVectorApllication + + +# Run to smd_c and let the CS enabled +go noClockStartup,Start91460\smd_cs +set register r2 = %r2|0x3 + +# Run to main() +go ,main diff --git a/20080212/Demo/MB91460_Softune/PRC/set_MONITOR_INTERNAL.prc b/20080212/Demo/MB91460_Softune/PRC/set_MONITOR_INTERNAL.prc new file mode 100644 index 000000000..480cf02d9 --- /dev/null +++ b/20080212/Demo/MB91460_Softune/PRC/set_MONITOR_INTERNAL.prc @@ -0,0 +1,56 @@ +# THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ +# MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ +# ELIGIBILITY FOR ANY PURPOSES. */ +# (C) Fujitsu Microelectronics Europe GmbH */ + +# Environment and memory manioulation after program upload + + +# Settings + +SET VARIABLE abortIRQ0 = 0x1 +SET VARIABLE intVectorMonitorDebugger = 0xFFC00 + + + + +# Disable all Interrupts +SET REGISTER I = 0x0 + +# Set Table Base Register +SET REGISTER TBR = intVectorMonitorDebugger + + +# Run to smd_tbr and save TBR of Application +go ,Start91460\smd_tbr +SET VARIABLE intVectorApllication = %r0 +SET REGISTER TBR = intVectorApllication + +# Copy required vector table entries of monitor debugger in vector table of application +MOVE intVectorMonitorDebugger + 0x3C0..intVectorMonitorDebugger + 0x3FF, intVectorApllication + 0x3C0 + + +# Prepare Entries for INT0 +IF %abortIRQ0 == 0x1 + MOVE intVectorMonitorDebugger + 0x3C0..intVectorMonitorDebugger + 0x3C3, intVectorApllication + 0x3BC + SET MEMORY/BYTE 0x32 = 0x3 + SET MEMORY/BYTE 0x30 = 0x0 + SET MEMORY/BYTE 0x31 = 0x1 + SET MEMORY/BYTE 0x440 = 0x10 + SET REGISTER ILM = 0x1E +ENDIF + + +# Setting indicates software reset, which leads to that the clock settings are not changed. +SET REGISTER R4 = 0x8 + + +# Set TBR to Vector table of application +SET REGISTER TBR = intVectorApllication + +# Run to smd_c and let the CS enabled +go noClockStartup,Start91460\smd_cs +set register r2 = %r2|0x2 + +# Run to main() +go ,main \ No newline at end of file diff --git a/20080212/Demo/MB91460_Softune/PRC/set_RESET.prc b/20080212/Demo/MB91460_Softune/PRC/set_RESET.prc new file mode 100644 index 000000000..95972c095 --- /dev/null +++ b/20080212/Demo/MB91460_Softune/PRC/set_RESET.prc @@ -0,0 +1,16 @@ +# THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU +# MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR +# ELIGIBILITY FOR ANY PURPOSES. +# (C) Fujitsu Microelectronics Europe GmbH +# set_ROMS.prc +# =========== +# +# Procedurefile for the FR-Emulator - Target : MB91F467D. +# Should be executed before loading any target-file into +# the RAM of the emulator (use the debug settings). +# The procedure checks sets the ROM Select Register to allow +# the emulation of the whole ROM Area of the MB91F467D + +RESET + +SET MEMORY/HALFWORD 0x390 = 0xFF00 \ No newline at end of file diff --git a/20080212/Demo/MB91460_Softune/PRC/set_ROMS.prc b/20080212/Demo/MB91460_Softune/PRC/set_ROMS.prc new file mode 100644 index 000000000..6bb9ae37a --- /dev/null +++ b/20080212/Demo/MB91460_Softune/PRC/set_ROMS.prc @@ -0,0 +1,15 @@ +# THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU +# MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR +# ELIGIBILITY FOR ANY PURPOSES. +# (C) Fujitsu Microelectronics Europe GmbH +# set_ROMS.prc +# =========== +# +# Procedurefile for the FR-Emulator - Target : MB91F467D. +# Should be executed before loading any target-file into +# the RAM of the emulator (use the debug settings). +# The procedure checks sets the ROM Select Register to allow +# the emulation of the whole ROM Area of the MB91F467D + + +SET MEMORY/HALFWORD 0x390 = 0xFF00 diff --git a/20080212/Demo/MB91460_Softune/PRC/set_SIMULATE.prc b/20080212/Demo/MB91460_Softune/PRC/set_SIMULATE.prc new file mode 100644 index 000000000..fe0c27131 --- /dev/null +++ b/20080212/Demo/MB91460_Softune/PRC/set_SIMULATE.prc @@ -0,0 +1,13 @@ +# THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ +# MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ +# ELIGIBILITY FOR ANY PURPOSES. */ +# (C) Fujitsu Microelectronics Europe GmbH */ + +# Environment and memory manioulation after program upload + + + + +print "patch reset vector to \"__start\"\n"; +SET MEMORY/WORD 0xFFFFC=__start + diff --git a/20080212/Demo/MB91460_Softune/SRC/FreeRTOSConfig.h b/20080212/Demo/MB91460_Softune/SRC/FreeRTOSConfig.h new file mode 100644 index 000000000..af11cda28 --- /dev/null +++ b/20080212/Demo/MB91460_Softune/SRC/FreeRTOSConfig.h @@ -0,0 +1,81 @@ +/* + FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + + Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along + with commercial development and support options. + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 0 +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 64000000 ) /* Clock setup from start91460.asm in the demo application. */ +#define configPER_CLOCK_HZ ( ( unsigned portLONG ) 16000000 ) /* Clock setup from start91460.asm in the demo application. */ +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 6 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 100 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 32768 - 4192 ) ) +#define configMAX_TASK_NAME_LEN ( 20 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 4 ) + + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_vResumeFromISR 1 + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/MB91460_Softune/SRC/Start91460.asm b/20080212/Demo/MB91460_Softune/SRC/Start91460.asm new file mode 100644 index 000000000..bf5de40ea --- /dev/null +++ b/20080212/Demo/MB91460_Softune/SRC/Start91460.asm @@ -0,0 +1,2533 @@ +/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ +/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ +/* ELIGIBILITY FOR ANY PURPOSES. */ +/* (C) 2007,2008 Fujitsu Microelectronics Europe GmbH */ +;========================================================================================= +; 1 Contents +;========================================================================================= +; 1 Contents +; 2 Disclaimer +; +; 3 History +; +; 4 Settings +; 4.1 Controller device +; 4.2 Boot / flash security +; 4.3 Stack type and stack size +; 4.4 Copy code from flash to I-RAM +; 4.5 C++ start-up +; 4.6 Low-level library interface +; 4.7 Clock Configuration +; 4.7.1 Clock selection +; 4.7.2 Select Clock Modulator +; 4.8 External bus interface +; 4.8.1 Select chipselect +; 4.8.2 Set memory addressing for chipselects +; 4.8.3 Configure chipselect area +; 4.8.4 Set wait cycles for chipselects +; 4.8.5 Configure chipselects SDRAM memory only +; 4.8.6 Referesh control register RCR +; 4.8.7 Terminal and timing control register +; 4.8.8 Enable / disable I-cache +; 4.8.9 Enable CACHE for chipselect +; 4.8.10 Select external bus mode (data lines) +; 4.8.11 Select external bus mode (address lines) +; 4.8.12 Select external bus mode (control signals) +; +; 5 Definitions of Configurations +; +; 6 Section and data declaration +; 6.1 Define stack size +; 6.2 Define sections +; +; 7. S T A R T +; 7.1 Initialise stack pointer and table base register +; 7.2 Check for CSV reset and set CSV +; 7.3 Check clock condition +; 7.4 Restore default settings after reset +; 7.4.1 Disable clock modulator +; 7.4.2 Check if running on sub clock, change to main clock +; 7.4.3 Disable sub clock +; 7.4.4 Check if running on PLL, gear down PLL +; 7.4.5 Disable PLL +; 7.4.6 Set to main clock +; 7.5 Set memory controller +; 7.6 Clock startup +; 7.6.1 Set Voltage Regulator Settings +; 7.6.2 Power on clock modulator - clock modulator part I +; 7.6.3 Set CLKR register w/o clock mode +; 7.6.4 Start PLLs +; 7.6.5 Wait for PLL oscillation stabilisation +; 7.6.6 Set clocks +; 7.6.6.1 Set CPU and peripheral clock +; 7.6.6.2 Set external bus interface clock +; 7.6.6.3 Set CAN clock prescaler +; 7.6.6.4 Switch main clock mode +; 7.6.6.5 Switch sub clock mode +; 7.6.6.6 Switch to PLL mode +; 7.6.7 Enable frequncy modulation - clock modulator part II +; 7.7 Set BusInterface +; 7.7.1 Disable all CS +; 7.7.2 Clear TCR register +; 7.7.3 Set CS0 +; 7.7.4 Set CS1 +; 7.7.5 Set CS2 +; 7.7.6 Set CS3 +; 7.7.7 Set CS4 +; 7.7.8 Set CS5 +; 7.7.9 Set CS6 +; 7.7.10 Set CS7 +; 7.7.11 Set special SDRAM config register +; 7.7.12 set Port function register +; 7.7.13 Set TCR register +; 7.7.14 Enable cache for selected CS +; 7.7.15 Set SDRAM referesh control register +; 7.7.16 Enable used CS +; 7.7.17 I-cache on/off +; 7.7.18 Set port function register to general as I/O-port +; 7.8 Copy code from flash to I-RAM +; 7.9 Fill stacks +; 7.10 Clear data +; 7.11 Copy Init section from ROM to RAM +; 7.12 C library initialization +; 7.13 Call C++ constructors +; 7.14 Call main routine +; 7.15 Return from main function +; +;========================================================================================= +; 2 Disclaimer +;========================================================================================= +; Fujitsu Microelectronics Europe GmbH +; http://emea.fujitsu.com/microelectronics +; +; The following software is for demonstration purposes only. It is not fully +; tested, nor validated in order to fullfill its task under all circumstances. +; Therefore, this software or any part of it must only be used in an evaluation +; laboratory environment. +; This software is subject to the rules of our standard DISCLAIMER, that is +; delivered with our SW-tools on the Fujitsu Microcontrollers CD/DVD (V3.4 or +; higher "\START.HTM") or on our Internet Pages: +; http://www.fme.gsdc.de/gsdc.htm +; http://emea.fujitsu.com/microelectronics +; +;========================================================================================= +; 3 History +;========================================================================================= +; +;========================================================================================= +; MB914xx (FR60 CORE ONLY) Series C Compiler's +; +; Startup file for memory and basic controller initialisation +;========================================================================================= +;History: +; +; 2005-04-18 V1.0 UMa Release first version +; 2005-06-17 V1.1 UMa Added bus interface, modified c++ startup +; 2005-06-28 V1.2 UMa minor changes +; 2005-07-27 V1.3 UMa default values changed +; 2005-10-04 V1.4 UMa changed code 'Call main Routine' +; Added secutiy section for MB91F467D +; Added Flash Access Read Timing setting section; +; 2005-10-04 V1.5 UMa Added Flash Controller Section +; 2005-10-28 V1.6 UMa Check for CSV reset +; 2005-11.16 V1.7 UMa Monitor Debugger support added: Copy of intvect Table +; Ext. Int 0 as abort function +; Changed PLL-Startup, Reset HWWD added +; 2005-11-16 V1.7 UMa Examples for MUL_G changed +; 2006-02-14 V1.8 UMa mb91464a added +; Settings for Clock Spervisor added +; Name of Section SECURITY changed to SECURITY_VECTORS +; Example values for gear-up changed +; 2006-03-17 V1.9 UMa Changed Startup for Monitor Debugger +; 2006-04-24 v2.0 UMa Added MB91465K and MB91469G +; 2006-05-03 v2.1 UMa Added MB91461R; removed MB91V460A +; Added settings for the external bus-interface +; 2006-07-28 v2.2 UMa Added I-RAM copy function (ROM -> IRAM) +; Added default settings for FLASH Access Read Timing +; Settings +; Changed default settings for FLASH cache configuration +; Register +; Changed check for clock startup +; 2006-08-16 v2.3 MVo Corrected Boot Security Sector Addresses for MB91469G +; 2006-10-06 v2.4 UMa Added new devices +; Corrected typo in I_RAM to flash copy function +; Changed default settings for flash cache configuration +; Changed comments for SDRAM bus interface configuration +; Changed comments and default setting of CAN Prescaler +; Added Stack filler +; Added Settings for REGSEL Register +; 2007-02-13 v2.5 UMa Introduction of default configurations +; Changed I_RAM to flash copy function +; +; +;========================================================================================= +; 4 Settings +;========================================================================================= +; +; CHECK ALL OPTIONS WHETHER THEY FIT TO THE APPLICATION; +; +; Configure this startup file in the "Settings" section. Search for +; comments with leading "; <<<". This points to the items to be set. +;========================================================================================= +; +#set OFF 0 +#set ON 1 +#set DEFAULT 2 +#set LOW_PRIOR 31 +; +;========================================================================================= +; 4.1 Controller Device +;========================================================================================= +#set MB91464A 2 ; MB91460 series +; +#set MB91467B 10 ; MB91460 series +; +#set MB91467C 11 ; MB91460 series +; +#set MB91467D 4 ; MB91460 series +; +#set MB91469G 6 ; MB91460 series +; +#set MB91465K 3 ; MB91460 series +; +#set MB91463N 8 ; MB91460 series +; +#set MB91461R 1 ; MB91460 series +#set MB91467R 5 ; MB91460 series +; +#set MB91465X 9 ; MB91460 series +; +#set others 7 ; MB91460 series +; +; +; +#set DEVICE MB91467D ; <<< select device +; +;========================================================================================= +; 4.2 Boot / Flash Security +;========================================================================================= +; +#set BOOT_FLASH_SEC OFF ; <<< BOOT and Flash Security Vector +; +; The flash devices have two flash and two boot security vectors. It is important to set +; the four vectors correctly. Otherwise it might be possible, that the flash device is +; not accessible any more via the bootrom. Please read carefully the hardware manual. +; +; OFF: The security feature is switch off. The section SECURITY_VECTORS is reserved and +; the vectors are set. +; ON: IMPORTANT! The security vectors are not set. But the section SECURITY_VECTORS +; is reserved. +; +; Note: This feature is not supported by every device. Please check the data sheet. This +; feature is not available on MB91461R. +; +;========================================================================================= +; 4.3 Stack Type and Stack Size +;========================================================================================= +; +#set USRSTACK 0 ; user stack: for main program +#set SYSSTACK 1 ; system stack: for main program and +; ; interrupts +; +; +#set STACKUSE SYSSTACK ; <<< set active stack +; +#set STACK_RESERVE ON ; <<< reserve stack area in +; ; this module +#set STACK_SYS_SIZE 2000 ; <<< byte size of System stack +#set STACK_USR_SIZE 4 ; <<< byte size of User stack +; +#set STACK_FILL ON ; <<< fills the stack area with pattern +#set STACK_PATTERN 0x55AA55AA ; <<< the pattern to write to stack +; +; - If the active stack is set to SYSSTACK, it is used for main program and interrupts. +; In this case, the user stack could be set to a dummy size. If the active stack is +; set to user stack, it is used for the main program but the system stack is +; automatically activated, if an interrupt is serviced. Both stack areas must have a +; reasonable size. +; - If STACK_RESERVE is ON, the sections USTACK and SSTACK are reserved in this module. +; Otherwise, they have to be reserved in other modules. If STACK_RESERVE is OFF, the +; size definitions STACK_SYS_SIZE and STACK_USR_SIZE have no meaning. +; - Even if they are reverved in other modules, they are still initialised in this +; start-up file. +; +; Note: Several library functions require quite a big stack (due to ANSI). +; Check the stack information files (*.stk) in the LIB\911 directory. +; +;========================================================================================= +; 4.4 Copy code from Flash to I-RAM +;========================================================================================= +; +#set I_RAM OFF ; <<< select if code in section IRAM +; should be copied +; +; If this option is activated code located in the section IRAM is copied during startup +; from ROM to the instruction-RAM. The code is linked for the instruction-RAM. +; +;========================================================================================= +; 4.5 Low-Level Library Interface +;========================================================================================= +; +#set CLIBINIT OFF ; <<< select ext. libray usage +; +; This option has only to be set, if stream-IO/standard-IO function of the C-libraray +; have to be used (printf(), fopen()...). This also requires low-level functions to be +; defined by the application software. +; For other library functions like (e.g. sprintf()) all this is not necessary. However, +; several functions consume a large amount of stack. +; +;========================================================================================= +; 4.6 C++ start-up +;========================================================================================= +; +#set CPLUSPLUS OFF ; <<< activate if c++ files are used +; +; In the C++ specifications, when external or static objects are used, a constructor +; must be called followed by the main function. Because four-byte pointers to the main +; function are stored in the EXT_CTOR_DTOR section, call a constructor sequentially from +; the lower address of the four addresses in that section. If using C++ sources, +; activate this function to create the section EXT_CTOR_DTOR. +; +;========================================================================================= +; 4.7 Clock Configuration +;========================================================================================= +;========================================================================================= +; 4.7.1 Clock Selection +;========================================================================================= +; +; No clock settings +#set NO_CLOCK 0x01 +; +; Sub-oscillation input: 32 kHz +#set SUB_32KHZ_CPU__32KHZ_PER_32KHZ_EXT_32KHZ_CAN__2MHZ 0x11 +; +; Oscillation input: 4 MHz +#set MAIN_4MHZ_CPU___2MHZ_PER__1MHZ_EXT__1MHZ_CAN__2MHZ 0x21 +#set PLL_4MHZ__CPU__48MHZ_PER_16MHZ_EXT_24MHZ_CAN_16MHZ 0x22 +#set PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ 0x23 +#set PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_27MHZ_CAN_20MHZ 0x24 +#set PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_40MHZ_CAN_20MHZ 0x25 +#set PLL_4MHZ__CPU__96MHZ_PER_16MHZ_EXT_48MHZ_CAN_16MHZ 0x26 ;not MB91V460, ... +#set PLL_4MHZ__CPU_100MHZ_PER_20MHZ_EXT_50MHZ_CAN_20MHZ 0x27 ;not MB91V460, ... +; +; MB91461R only: Oscillation input: 10 MHz +#set PLL_10MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ 0x41 +; +; MB91461R only: Oscillation input: 20 MHz +#set PLL_20MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ 0x51 +; +; User settings +#set CLOCK_USER 0x61 +; +; +; +#set CLOCKSPEED PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ +; ; <<< Select clock configuration +; +; There are different default configurations available, where all necessary settings for +; clocks and the related registers are made. Beside this configurations, there is the +; possibility to define a user configuration in the chapter "Definition of +; Configurations" +; +; - NO_CLOCK means: +; The clock registers are not set by the start-up file. +; +; - PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ means: +; Main oszillation = 4 MHz, PLL is activated +; CPU clock (CLKB) = 64 MHZ +; Peripheral clock (CLKP) = 16 MHZ +; Ext. bus clock (CLKT) = 32 MHZ +; CAN clock (CLKCAN) = 16 MHz, using PLLx +; +; - CLOCK_USER: +; The user configuration definded in the chapter "Definition of Configurations" is set. +; +; Note: Not all frequencies are supported by every device. Please see the hardware +; manual. +; +;========================================================================================= +; 4.7.2 Select Clock Modulator +;========================================================================================= +; +#set CLOMO OFF ; <<< Enable /disable clock modulator +; +#set CMPR 0x026F ; <<< Ref. to the data sheet, CMPR +; +; Please refer to the data sheet of the device if you enable clock modulation. The +; register CMPR dependant on the PLL-Clock. +; +; Note: If the CLKCAN source is set either to main oscillator or to PLL output then the +; clock for the CAN is not influenced by the clock modulation. If the CLKCAN +; source is set CPU clock (CLKB) then the clock for the CAN is also modulated (if +; the clock modulator is enabled). +; +; Note: If the clock modulator is enabled, the wait states of the internal flash wait +; states must be adapted to maximum frequency. Please check the wait states +; settings. +; +; Note: This feature is not supported by every device, e.g. MB91461. Please check the +; data sheet. +; +;========================================================================================= +; 4.8 External Bus Interface +; +; The rest of the configuration is only applicable for devices with an external bus +; interface. +; +; If the device does not offer an external bus interface, the configuration can be +; stoped at this point. +; +;========================================================================================= +; +#set EXTBUS DEFAULT ; <<< Ext. Bus on/off +; +; ON - The ext. bus interface is enabled and is configured as +; set below. +; +; OFF - The ext. bus interface is diabled. The port function +; registers are set to general I/O. The registers of +; ext. bus interface will not be touched by the start-up +; file. +; Be aware, that the device might be conifgured in ext. +; bus mode by default after reset. +; +; DEFAULT - Neither the register nor the respective port function +; registers are touched by the start-up file. +; Be aware, that the device might be conifgured in ext. +; bus mode by default after reset. +; +; +; Note: This feature is not supported by every device. Please check the data sheet. The +; following devices for example do not offer an external bus interface: MB91464A, +; MB91467C, MB91465K, MB91463N, MB91465X. +; +;========================================================================================= +; 4.8.1 Select Chipselect (Only EXTBUS == ON) +;========================================================================================= +; +#set CS0 OFF ; <<< select CS (ON/OFF) +#set CS1 OFF ; <<< select CS (ON/OFF) +#set CS2 OFF ; <<< select CS (ON/OFF) +#set CS3 OFF ; <<< select CS (ON/OFF) +#set CS4 OFF ; <<< select CS (ON/OFF) +#set CS5 OFF ; <<< select CS (ON/OFF) +#set CS6 OFF ; <<< select CS (ON/OFF) +#set CS7 OFF ; <<< select CS (ON/OFF) +#set SDRAM OFF ; <<< select if a SDRAM is connected +; +; +#set ENACSX B'00000000 ; <<< set CS, ENACSX +; |||||||| +; ||||||||__ CS0 bit, enable/disable CS0 (1/0) +; |||||||___ CS1 bit, enable/disable CS1 (1/0) +; ||||||____ CS2 bit, enable/disable CS2 (1/0) +; |||||_____ CS3 bit, enable/disable CS3 (1/0) +; ||||______ CS4 bit, enable/disable CS4 (1/0) +; |||_______ CS5 bit, enable/disable CS5 (1/0) +; ||________ CS6 bit, enable/disable CS6 (1/0) +; |_________ CS7 bit, enable/disable CS7 (1/0) +; +; Note: If the SWB Monitor Debugger is used, set the CS1 (external RAM only) or CS0 and +; CS 1 (external RAM and flash) to off. +; +; Note: Not all Chipselects are supported by the different devices. Please check the +; data sheet. +; +;========================================================================================= +; 4.8.2 Set memory addressing for Chipselects (only EXTBUS == ON) +;========================================================================================= +; +#set AREASEL0 0x0000 ; <<< set start add. for CS0, ASR0 +#set AREASEL1 0x0000 ; <<< set start add. for CS1, ASR1 +#set AREASEL2 0x0000 ; <<< set start add. for CS2, ASR2 +#set AREASEL3 0x0000 ; <<< set start add. for CS3, ASR3 +#set AREASEL4 0x0000 ; <<< set start add. for CS4, ASR4 +#set AREASEL5 0x0000 ; <<< set start add. for CS5, ASR5 +#set AREASEL6 0x0000 ; <<< set start add. for CS6, ASR6 +#set AREASEL7 0x0000 ; <<< set start add. for CS7, ASR7 +; +; Configure the starting address of each used Chipselect. Chipselects which are not used +; (not set to ON in "Select Chipselect") need not be set (setting ignored). +; +; NOTE: Just the upper 16-bit of the start address must be set, e.g. when using start +; address 0x00080000 set 0x0008. +; +;========================================================================================= +; 4.8.3 Configure Chipselect Area (only EXTBUS == ON) +;========================================================================================= +; +#set CONFIGCS0 B'0000000000000000 ; <<< Config. CS0, ACR0 +#set CONFIGCS1 B'0000000000000000 ; <<< Config. CS1, ACR1 +#set CONFIGCS2 B'0000000000000000 ; <<< Config. CS2, ACR2 +#set CONFIGCS3 B'0000000000000000 ; <<< Config. CS3, ACR3 +#set CONFIGCS4 B'0000000000000000 ; <<< Config. CS4, ACR4 +#set CONFIGCS5 B'0000000000000000 ; <<< Config. CS5, ACR5 +#set CONFIGCS6 B'0000000000000000 ; <<< Config. CS6, ACR6 +#set CONFIGCS7 B'0000000000000000 ; <<< Config. CS7, ACR7 +; |||||||||||||||| +; ||||||||||||||||__ TYP0 bit, TYP0-4 bits select access type +; |||||||||||||||___ TYP1 bit +; ||||||||||||||____ TYP2 bit +; |||||||||||||_____ TYP3 bit +; ||||||||||||______ LEND bit, select little '1' or big endian '0' +; |||||||||||_______ WREN bit, en-/disable (1/0) Write access +; ||||||||||________ PFEN bit, en-/disable (1/0) pre-fetch +; |||||||||_________ SREN bit, en-/disable (1/0) share of BRQ & BGRNTX +; ||||||||__________ BST0 bit, BSTx bits select burst size +; |||||||___________ BST1 bit +; ||||||____________ DBW0 bit, DBWx select data bus width +; |||||_____________ DBW1 bit +; ||||______________ ASZ0 bit, ASZx bits select address size of CS +; |||_______________ ASZ1 bit +; ||________________ ASZ2 bit +; |_________________ ASZ3 bit +; +; Bit description: +; +; TYP3 TYP2 TYP1 TYP0 : Select access type of each CS +; 0 0 X X : Normal access (asynchronous SRAM, I/O, +; single/page/busrt-ROM/FLASH) +; 0 1 X X : Address/data multiplexed (8bit / 16bit bus width only) +; 0 X X 0 : WAIT insertion by RDY disabled +; 0 X X 1 : WAIT insertion by RDY enabled +; 0 X 0 X : The WR0X pin to the WR3X pin are used as write strobes +; (WRX is fixed at H-Level) +; 0 X 1 X : The WRX pin is used as write strobe +; 1 0 0 0 : Memory type A: SDRAM/FCRAM (Auto pre-charge used) +; 1 0 0 1 : Memory type B: FCRAM (Auto pre-charge used) +; 1 0 1 0 : setting not allowed +; 1 0 1 1 : setting not allowed +; 1 1 0 0 : setting not allowed +; 1 1 0 1 : setting not allowed +; 1 1 1 0 : setting not allowed +; 1 1 1 1 : mask area setting +; +; LEND : select BYTE ordering +; 0 : Big endian +; 1 : Little endian +; +; WREN : enable or disable write access +; 0 : disabled +; 1 : enabled, +; +; PFEN : Enable or disable the pre-fetch +; 0 : disabled +; 1 : enabled, +; +; SREN : Enable or disable the sharing of BRQ and BGRNTX +; 0 : disabled +; 1 : enabled (CSx pin High-Z) +; +; BST1 BST0 : set burst size of chip select area +; 0 0 : 1 burst (single access) +; 0 1 : 2 bursts (Address boundary 1 bit) +; 1 0 : 4 bursts (Address boundary 2 bit) +; 1 1 : 8 bursts (Address boundary 3 bit) +; +; DBW1 DBW0 : Set data bus width +; 0 0 : 8-bit (BYTE access) +; 0 1 : 16-bit (HALF-WORD access) +; 1 0 : 32-bit (WORD access) +; 1 1 : Reserved +; +; ASZ3 ASZ2 ASZ1 ASZ0 : Select memory size of each chipselect +; 0 0 0 0 : 64 Kbyte (0x01.0000 bytes; use ASR A[31:16] bits) +; 0 0 0 1 : 128 Kbyte (0x02.0000 bytes; use ASR A[31:17] bits) +; 0 0 1 0 : 256 Kbyte (0x04.0000 bytes; use ASR A[31:18] bits) +; 0 0 1 1 : 512 Kbyte (0x08.0000 bytes; use ASR A[31:19] bits) +; 0 1 0 0 : 1 Mbyte (0x10.0000 bytes; use ASR A[31:20] bits) +; 0 1 0 1 : 2 Mbyte (0x20.0000 bytes; use ASR A[31:21] bits) +; 0 1 1 0 : 4 Mbyte (0x40.0000 bytes; use ASR A[31:22] bits) +; 0 1 1 1 : 8 Mbyte (0x80.0000 bytes; use ASR A[31:23] bits) +; 1 0 0 0 : 16 Mbyte (0x100.0000 bytes; use ASR A[31:24] bits) +; 1 0 0 1 : 32 Mbyte (0x200.0000 bytes; use ASR A[31:25] bits) +; 1 0 1 0 : 64 Mbyte (0x400.0000 bytes; use ASR A[31:26] bits) +; 1 0 1 1 : 128 Mbyte (0x800.0000 bytes; use ASR A[31:27] bits) +; 1 1 0 0 : 256 Mbyte (0x1000.0000 bytes; use ASR A[31:28] bits) +; 1 1 0 1 : 512 Mbyte (0x2000.0000 bytes; use ASR A[31:29] bits) +; 1 1 1 0 : 1024 Mbyte(0x4000.0000 bytes; use ASR A[31:30] bits) +; 1 1 1 1 : 2048 Mbyte(0x8000.0000 bytes; use ASR A[31] bit) +; +;========================================================================================= +; 4.8.4 Set Wait cycles for Chipselects for ordinary businterface (only EXTBUS == ON) +;========================================================================================= +; +; Ordinary bus interface (w/o SDRAM and FRAM) (ACRx_Type = 0xxx) +; +#set WAITREG0 B'0000000000000000 ; <<< CS0 Waitstates, AWR0 +#set WAITREG1 B'0000000000000000 ; <<< CS1 Waitstates, AWR1 +#set WAITREG2 B'0000000000000000 ; <<< CS2 Waitstates, AWR2 +#set WAITREG3 B'0000000000000000 ; <<< CS3 Waitstates, AWR3 +#set WAITREG4 B'0000000000000000 ; <<< CS4 Waitstates, AWR4 +#set WAITREG5 B'0000000000000000 ; <<< CS5 Waitstates, AWR5 +; |||||||||||||||| +; ||||||||||||||||__ W00 bit, RDY/WRY-> CSX hold cycle +; |||||||||||||||___ W01 bit, CSX->RDX/WRX setup extension cycle +; ||||||||||||||____ W02 bit, Address -> CSX Delay selection +; |||||||||||||_____ W03 bit, WR0X to WR3X/WRX outout timing +; ||||||||||||______ W04 bit, W04/W05 Write recovery cycle +; |||||||||||_______ W05 bit +; ||||||||||________ W06 bit, W06/07 Read -> Write idle cycle +; |||||||||_________ W07 bit selection +; ||||||||__________ W08 bit, W08-W11 Intra-page access cycle +; |||||||___________ W09 bit select (0-15 cycles) +; ||||||____________ W10 bit +; |||||_____________ W11 bit +; ||||______________ W12 bit, W12-W15 First access wait cycle +; |||_______________ W13 bit select (0-15 cycles) +; ||________________ W14 bit +; |_________________ W15 bit +; +; +; SDRAM and FRAM bus interface (ACRx_Type = 100x) +; +#set WAITREG6 B'0000000000000000 ; <<< CS6 Waitstates, AWR6 +#set WAITREG7 B'0000000000000000 ; <<< CS7 Waitstates, AWR7 +; |||||||||||||||| +; ||||||||||||||||__ W00 bit, W0-W1 RAS precharge cycles +; |||||||||||||||___ W01 bit +; ||||||||||||||____ W02 bit, W2-W3 RAS active Time +; |||||||||||||_____ W03 bit +; ||||||||||||______ W04 bit, W4-W5 Write recovery cycle +; |||||||||||_______ W05 bit +; ||||||||||________ W06 bit, W6-W7 Read->Write idle cycle +; |||||||||_________ W07 bit +; ||||||||__________ W08 bit, W8-W10 CAS latency +; |||||||___________ W09 bit +; ||||||____________ W10 bit +; |||||_____________ W11 bit, reserved +; ||||______________ W12 bit, W12-W16 RAS-CAS delay +; |||_______________ W13 bit +; ||________________ W14 bit +; |_________________ W15 bit, reserved +; +; +; The bit meaning depends on the configured bus interface type. The bus interface can be +; configured for different memory types. Depending on the memory type, the wait register +; bits have a differnt meaning. CS0-5 should be configurable as ordinary bus interface +; (w/o SDRAM and FRAM) and CS6-7 should be configurable as SDRAM and FRAM. It is also +; possible and for some devices neccessary to configure other two chip selects as SDRAM +; or FRAM interface. In such a case be aware of the bit meanings. +; +; +; Ordinary bus interface (w/o SDRAM and FRAM) (ACRx_Type = 0xxx) +; -------------------------------------------------------------- +; +; Bit description: +; +; W00 : RDY/WRX -> CSX hold extension cycle +; 0 : 0 cycle +; 1 : 1 cycle +; +; W01 : CSX -> RDX/WRX setup extention cycle +; 0 : 0 cycle +; 1 : 1 cycle +; +; W02 : Address -> CSX Delay selection +; 0 : no delay selected +; 1 : delay selected +; +; W03 : WR0X to WR3X/WRX outout timing selection +; 0 : MCLK synchronous write output enable (ASX=L) +; 1 : Asynchronous write strobe output (norma operation) +; +; W05 W04 : select Write recovery cycle +; 0 0 : 0 cycle +; 0 1 : 1 cycle +; 1 0 : 2 cycles +; 1 1 : 3 cycles +; +; W07 W06 : Read -> Write idle cycle selection +; 0 0 : 0 cycle +; 0 1 : 1 cycle +; 1 0 : 2 cycles +; 1 1 : 3 cycles +; +; W11 W10 W09 W08 : Intra-page access cycle select (0-15 cycles) +; 0 0 0 0 : 0 Wait state +; 0 0 0 1 : 1 Auto-wait cycle +; 0 0 1 0 : 2 Auto-wait cycle +; .... +; 1 1 1 1 : 15 Auto wait cycles +; +; W15 W14 W13 W12 : First access wait cycle can be set (0-15 cycles) +; 0 0 0 0 : 0 Wait state +; 0 0 0 1 : 1 Auto-wait cycle +; 0 0 1 0 : 2 Auto-wait cycle +; .... +; 1 1 1 1 : 15 Auto wait cycles +; +; +; +; SDRAM and FRAM bus interface (ACRx_Type = 100x) +; ----------------------------------------------- +; +; Bit description: +; +; W01 W00 : RAS precharge cycles. +; 0 0 : 1 cycle +; 0 1 : 2 cycles +; 1 0 : 5 cycles +; 1 1 : 6 cycles +; +; W03 W02 : RAS active Time +; 0 0 : 1 cycle +; 0 1 : 2 cycles +; 1 0 : 5 cycles +; 1 1 : 6 cycles +; +; W05 W04 : set Write recovery cycle (1 - 4 cycles) +; 0 0 : Prohibited +; 0 1 : 2 cycles +; 1 0 : 3 cycles +; 1 1 : 4 cycles +; +; W07 W06 : set Read -> Write idle Cycle (1 - 4 cycles) +; 0 0 : 1 cycle +; 0 1 : 2 cycles +; 1 0 : 3 cycles +; 1 1 : 4 cycles +; +; W10 W09 W08 : set CAS latency (1 - 8 cycles) +; 0 0 0 : 1 cycle +; 0 0 1 : 2 cycle +; ... +; 1 1 1 : 8 cycle +; +; W11 : RESERVED, ALWAYS WRITE 0 ! +; +; W14 W13 W12 : set RAS-CAS delay (1 - 8 cycles) +; 0 0 0 : 1 cycle +; 0 0 1 : 2 cycle +; ... +; 1 1 1 : 8 cycle +; +; W15 : RESERVED, ALWAYS WRITE 0 ! +; + +; The bit meaning depends on the configured bus interface type +; +;========================================================================================= +; 4.8.5 Configure Chipselects for SDRAM memory only (only EXTBUS == ON and SDRAM) +;========================================================================================= +; +#set MEMCON B'00000111 ; <<< set special SDRAM register, MCRA +; |||||||| +; ||||||||__ ABS0 bit, set max. active banks (ABS1,0) +; |||||||___ ABS1 bit +; ||||||____ BANK bit, set number of banks connected to CS +; |||||_____ WBST bit, Write burst enable/disable +; ||||______ PSZ0 bit, Set page size (PSZ2-0) +; |||_______ PSZ1 bit +; ||________ PSZ2 bit +; |_________ reserved, always write 0 +; +; When connecting SDRAM/FCRAM TYP3-0=1000 in ACRx register the following register must +; be setup. +; +; Bit description: +; +; ABS1 ABS0 : Set maximum number of bank, active at same time +; 0 0 : 1 bank +; 0 1 : 2 banks +; 1 0 : 3 banks +; 1 1 : 4 banks +; +; BANK : Set number of connected SDRAM banks +; 0 : 2 banks +; 1 : 4 banks +; +; WBST : Write burst enable +; 0 : Single Write +; 1 : Busrt Write +; +; PSZ2 PSZ1 PS0 : Select page size of connected memory +; 0 0 0 : 8-bit column address = A0 to A7 +; 0 0 1 : 9-bit column address = A0 to A8 +; 0 1 0 : 10-bit column address = A0 to A9 +; 0 1 1 : 11-bit column address = A0 to A9, A11 +; 1 X X : setting disabled +; +; +;========================================================================================= +; 4.8.6 Referesh Control Register RCR (only EXTBUS == ON and SDRAM) +;========================================================================================= +; +#set REFRESH B'1110001001000111 ; <<< set Refresh Control Register, RCR +; |||||||||||||||| +; ||||||||||||||||__ TRC0 bit, set refresh cycle (TRC2-0) +; |||||||||||||||___ TRC1 bit +; ||||||||||||||____ TRC2 bit +; |||||||||||||_____ PON bit, set power-on control +; ||||||||||||______ RFC0 bit, set refresh count (RFC2-0) +; |||||||||||_______ RFC1 bit +; ||||||||||________ RFC2 bit +; |||||||||_________ BRST bit, set burst refresh control +; ||||||||__________ RFINT0 bit, set auto refresh interval +; |||||||___________ RFINT1 bit, (RFINT5-0) +; ||||||____________ RFINT2 bit +; |||||_____________ RFINT3 bit +; ||||______________ RFINT4 bit +; |||_______________ RFINT5 bit +; ||________________ RRLD bit, counter refresh strat control +; |_________________ SELF bit, self refresh control +; +; +; This register sets various SDRAM refresh controls. When SDRAM control is not set for +; any area, the setting of this register is meaningless, but do not change the register +; value at initial state. When a read is performed using a read-modify-write +; instruction, 0 always returns from the SELF, RRLD, and PON bits. +; +; Bit description: +; +; +; TRC2 TRC1 TRC0 : Refresh Cycle +; 0 0 0 : 4 +; 0 0 1 : 5 +; 0 1 0 : 6 +; 0 1 1 : 7 +; 1 0 0 : 8 +; 1 0 1 : 9 +; 1 1 0 : 10 +; 1 1 1 : 11 +; +; PON : Power-on control +; 0 : disabled +; 1 : power-on sequence started +; +; RFC2 RFC1 RFC0 : Refresh Count +; 0 0 0 : 256 +; 0 0 1 : 512 +; 0 1 0 : 1024 +; 0 1 1 : 2048 +; 1 0 0 : 4096 +; 1 0 1 : 8192 +; 1 1 0 : Setting disabled +; 1 1 1 : Refresh disabled +; +; BRST : Burst refresh control +; 0 : Decentralised refresh +; 1 : burst refresh +; +; RFINT[5-0] : auto refresh interval +; +; RRLD : Refresh counter Activation Control +; 0 : Disabled, +; 1 : Autorefresh performed once, then value of RFINT reloaded +; +; SELF : Self refresh control +; 0 : auto refresh or power down +; 1 : Transitions to self-refresch mode +; +; NOTE: PON bit is set after the above setting. Do not set PON bit to 1 in the +; above setting. Otherwise the settings are not correct set. +; +;========================================================================================= +; 4.8.7 Terminal and Timing Control Register (only EXTBUS == ON) +;========================================================================================= +; +#set TIMECONTR B'00000000 ; <<< set TCR register, TCR +; |||||||| +; ||||||||__ RDW0 bit, set wait cycle reduction (RDW0,1) +; |||||||___ RDW1 bit +; ||||||____ OHT0 bit, set output hold delay (OHT1,0) +; |||||_____ OHT1 bit +; ||||______ reserved, always write 0 +; |||_______ PCLR bit, prefetch buffer clear +; ||________ PSUS bit, prefetch suspend +; |_________ BREN bit, BRQ input enable +; +; This register controls the general functions of the external bus interface controller +; such as the common-pin function setting and timing control. +; +; Bit description: +; +; RDW1 RDW0 : Wait cycle reduction +; 0 0 : Normal Wait (AWR0 - 7 setting) +; 0 1 : 1/2 of AWR0 - 7 setting value +; 1 0 : 1/4 of AWR0 - 7 setting value +; 1 1 : 1/8 of AWR0 - 7 setting value +; +; OHT1 OHT0 : Output hold selection bit +; 0 0 : Output performed at falling edge of SYSCLK/MCLK +; 0 1 : Output performed about 3ns after falling edge of SYSCLK/MCLK +; 1 0 : Output performed about 4ns after falling edge of SYSCLK/MCLK +; 1 1 : Output performed about 5ns after falling edge of SYSCLK/MCLK +; +; PCLR : Prefetch buffer all clear +; 0 : normal state +; 1 : Prefetch buffer cleared +; +; PSUS : prefetch suspension bit +; 0 : Prefetch enabled +; 1 : Prefetch disabled +; +; BREN : BRQ input enable +; 0 : disabled, +; 1 : enabled, Bus sharing of BRQ/BGRNTX performed +; +; Note: This function is used to prevent an excessive access cycle wait while operating +; at a low-speed clock (such as while base clock operating at low speed or +; high frequency division rate for external bus clock). +; +;========================================================================================= +; 4.8.8 Enable/Disable I-CACHE (only EXTBUS == ON) +;========================================================================================= +; +#set C1024 1 ; CACHE Size: 1024 BYTE +#set C2048 2 ; CACHE Size: 2048 BYTE +#set C4096 3 ; CACHE Size: 4096 BYTE +; +; +#set CACHE OFF ; <<< Select use of cache +#set CACHE_SIZE C4096 ; <<< Select size of cache, ISIZE +; +; It is possible to use cache functionality on the I-Bus on several devices. Please +; check the corresponidng data sheet if this feature is available on a certain device +; and for the size of the cache. This is the general cache configuration. It is possible +; to configure for each CS area, if the cache should be used. +; +; Note: This feature is not supported by every device. Please check the data sheet. The +; feature is for example supported by MB91461R, MB91469G. +; +;========================================================================================= +; 4.8.9 Enable CACHE for chipselect (only EXTBUS == ON) +;========================================================================================= +; +#set CHEENA B'11111111 ; <<< en-/disable cache, CHER +; |||||||| +; ||||||||__ CHE0 bit, CS0 area +; |||||||___ CHE1 bit, CS1 area +; ||||||____ CHE2 bit, CS2 area +; |||||_____ CHE3 bit, CS3 area +; ||||______ CHE4 bit, CS4 area +; |||_______ CHE5 bit, CS5 area +; ||________ CHE6 bit, CS6 area +; |_________ CHE7 bit, CS7 area +; +; Additional to the general cache enable setting, select which CS area should be used +; with cache functionality. +; +; Note: Not all Chipselects are supported by the different devices. Please check the +; data sheet. +; +; Note: This feature is not supported by every device. Please check the data sheet. The +; Feature is supported by MB91461R, MB91469G. +; +;========================================================================================= +; 4.8.10 Select External bus mode (Data lines) (only EXTBUS == ON) +;========================================================================================= +; +#set PFUNC0 B'11111111 ;<<< Data lines or GIO, PFR00 +; |||||||| +; ||||||||__ D24 / P00_0 +; |||||||___ D25 / P00_1 +; ||||||____ D26 / P00_2 +; |||||_____ D27 / P00_3 +; ||||______ D28 / P00_4 +; |||_______ D29 / P00_5 +; ||________ D30 / P00_6 +; |_________ D31 / P00_7 +; +#set PFUNC1 B'11111111 ;<<< Data lines or GIO, PFR01 +; |||||||| +; ||||||||__ D16 / P01_0 +; |||||||___ D17 / P01_1 +; ||||||____ D18 / P01_2 +; |||||_____ D19 / P01_3 +; ||||______ D20 / P01_4 +; |||_______ D21 / P01_5 +; ||________ D22 / P01_6 +; |_________ D23 / P01_7 +; +#set PFUNC2 B'11111111 ;<<< Data lines or GIO, PFR02 +; |||||||| +; ||||||||__ D8 / P02_0 +; |||||||___ D9 / P02_1 +; ||||||____ D10 / P02_2 +; |||||_____ D11 / P02_3 +; ||||______ D12 / P02_4 +; |||_______ D13 / P02_5 +; ||________ D14 / P02_6 +; |_________ D15 / P02_7 +; +#set PFUNC3 B'11111111 ;<<< Data lines or GIO, PFR03 +; |||||||| +; ||||||||__ D0 / P03_0 +; |||||||___ D1 / P03_1 +; ||||||____ D2 / P03_2 +; |||||_____ D3 / P03_3 +; ||||______ D4 / P03_4 +; |||_______ D5 / P03_5 +; ||________ D6 / P03_6 +; |_________ D7 / P03_7 +; +; Select if the ports are set to +; 1 : External bus mode, I/O for data lines or +; 0 : General I/O port (GIO) +; +; Note: Not all data-lines are supported by the different devices. Please check the data +; sheet. +; +;========================================================================================= +; 4.8.11 Select External bus mode (Address lines) (only EXTBUS == ON) +;========================================================================================= +; +#set PFUNC4 B'11111111 ;<<< Address lines or GIO, PFR04 +; |||||||| +; ||||||||__ A24 / P04_0 +; |||||||___ A25 / P04_1 +; ||||||____ A26 / P04_2 +; |||||_____ A27 / P04_3 +; ||||______ A28 / P04_4 +; |||_______ A29 / P04_5 +; ||________ A30 / P04_6 +; |_________ A31 / P04_7 +; +#set PFUNC5 B'11111111 ;<<< Address lines or GIO, PFR05 +; |||||||| +; ||||||||__ A16 / P05_0 +; |||||||___ A17 / P05_1 +; ||||||____ A18 / P05_2 +; |||||_____ A19 / P05_3 +; ||||______ A20 / P05_4 +; |||_______ A21 / P05_5 +; ||________ A22 / P05_6 +; |_________ A23 / P05_7 +; +#set PFUNC6 B'11111111 ;<<< Address lines or GIO, PFR06 +; |||||||| +; ||||||||__ A8 / P06_0 +; |||||||___ A9 / P06_1 +; ||||||____ A10 / P06_2 +; |||||_____ A11 / P06_3 +; ||||______ A12 / P06_4 +; |||_______ A13 / P06_5 +; ||________ A14 / P06_6 +; |_________ A15 / P06_7 +; +#set PFUNC7 B'11111111 ;<<< Address lines or GIO, PFR07 +; |||||||| +; ||||||||__ A0 / P07_0 +; |||||||___ A1 / P07_1 +; ||||||____ A2 / P07_2 +; |||||_____ A3 / P07_3 +; ||||______ A4 / P07_4 +; |||_______ A5 / P07_5 +; ||________ A6 / P07_6 +; |_________ A7 / P07_7 +; +; Select if the ports are set to +; 1 : External bus mode, I/O for address lines or +; 0 : General I/O port (GIO) +; +; Note: Not all address-lines are supported by the different devices. Please check the +; data sheet. +; +;========================================================================================= +; 4.8.12 Select External bus mode (Control signals) (only EXTBUS == ON) +;========================================================================================= +; +#set PFUNC8 B'11111111 ;<<< Control signals or GIO, PFR08 +; |||||||| +; ||||||||__ WRX0 / P08_0 +; |||||||___ WRX1 / P08_1 +; ||||||____ WRX2 / P08_2 +; |||||_____ WRX3 / P08_3 +; ||||______ RDX / P08_4 +; |||_______ BGRNTX / P08_5 +; ||________ BRQ / P08_6 +; |_________ RDY / P08_7 +; +#set PFUNC9 B'11111111 ;<<< Control signals or GIO, PFR09 +; |||||||| +; ||||||||__ CSX0 / P09_0 +; |||||||___ CSX1 / P09_1 +; ||||||____ CSX2 / P09_2 +; |||||_____ CSX3 / P09_3 +; ||||______ CSX4 / P09_4 +; |||_______ CSX5 / P09_5 +; ||________ CSX6 / P09_6 +; |_________ CSX7 / P09_7 +; +#set PFUNC10 B'01011111 ;<<< Control signals or GIO, PFR10 +; |||||||| +; ||||||||__ SYSCLK or !SYSCLK / P10_0 +; |||||||___ ASX / P10_1 +; ||||||____ BAAX / P10_2 +; |||||_____ WEX / P10_3 +; ||||______ MCLKO or !MCLKO / P10_4 +; |||_______ MCLKI or !MCLKI/ P10_5 +; ||________ MCLKE / P10_6 +; |_________ - +; +#set EPFUNC10 B'00000000 ;<<< Control signals or GIO, EPFR10 +; |||||||| +; ||||||||__ 0:SYSCLK / 1:!SYSCLK +; |||||||___ - +; ||||||____ - +; |||||_____ - +; ||||______ 0:MCLKO / 1:!MCLKO +; |||_______ 0:MCLKI / 1:!MCLKI +; ||________ 0:MCLKI / 1:!MCLKI +; |_________ - +; +; +; Select if the ports are set to +; 1 : External bus mode, I/O for control lines or +; 0 : General I/O port (GIO) +; +; Note: Not all control-lines are supported by the different devices. Please check the +; data sheet. +; +;========================================================================================= +; 5 Definition of Configurations +;========================================================================================= +; +#set NOCLOCK 0 ; do not touch CKSCR register +#set MAINCLOCK 1 ; select main clock +; ; MB91461R : 1/4 of oscillation input +; ; Others: 1/2 of oscillation input +#set MAINPLLCLOCK 2 ; select main clock with PLL +#set SUBCLOCK 3 ; select subclock (if available) +; +#set PSCLOCK_CLKB 0x00 ; select core clock (initial) +#set PSCLOCK_PLL 0x10 ; select PLL output (x) +#set PSCLOCK_MAIN 0x30 ; select Main Oscillation +; +;========================================================================================= +; 5.1 CLOCKSPEED == CLOCK_USER <<< +;========================================================================================= +; Must be configured only in the case of CLOCKSPEED is set to CLOCK_USER. Please see the +; corresponding application note. +; +#if (CLOCKSPEED == CLOCK_USER ) + #set CLOCKSOURCE MAINPLLCLOCK ; <<< Clocksource + #set ENABLE_SUBCLOCK OFF ; <<< Subclock: ON/OFF + #set PLLSPEED 0x010F ; <<< 0x48Ch, 0x48Dh: PLLDIVM/N ; 64 MHz + #set DIV_G 0x0F ; <<< 0x48Eh: PLLDIVG; + #set MUL_G 0x0F ; <<< 0x48Fh: PLLMULG; + ; Clock Divider + #set CPUCLOCK 0x00 ; <<< 0x486h: DIV0R_B; => /1 ; 64 MHz + #set PERCLOCK 0x03 ; <<< 0x486h: DIV0R_P; => /4 ; 16 MHz + #set EXTBUSCLOCK 0x01 ; <<< 0x487h: DIV1R_T; => /2 ; 32 MHz + ; CAN Clock + #set PSCLOCKSOURCE PSCLOCK_PLL ; <<< 0x4C0h: CANPRE; => PLLx;128 MHz + #set PSDVC 0x07 ; <<< 0x4C0h: CANPRE_DVC;=> /8 ; 16 MHz + #set CANCLOCK 0x00 ; <<< 0x4C1h: CANCKD; + ; Voltage Regulator + #set REGULATORSEL 0x06 ; <<< 0x4CEh: REGSEL; + #set REGULATORCTRL 0x00 ; <<< 0x4CFh: REGCTR; + ; Memory Controller + #set FLASHCONTROL 0x032 ; <<< 0x7002h: FCHCR; + #set FLASHREADT 0xC413 ; <<< 0x7004h: FMWT; + #set FLASHMWT2 0x10 ; <<< 0x7006h: FMWT2; +#endif +; +;========================================================================================= +; 5.2 CLOCKSPEED == NO_CLOCK +;========================================================================================= +; +#if (CLOCKSPEED == NO_CLOCK ) + #set CLOCKSOURCE NOCLOCK +#endif +; +;========================================================================================= +; 5.2 CLOCKSPEED == SUB_32KHZ_CPU__32KHZ_PER_32KHZ_EXT_32KHZ_CAN__2MHZ +;========================================================================================= +; +#if (CLOCKSPEED == SUB_32KHZ_CPU__32KHZ_PER_32KHZ_EXT_32KHZ_CAN__2MHZ ) +; +; Start restriction; Maximum frequency + #if (DEVICE == MB91463N) || (DEVICE == MB91461R) + #error: Frequency is not supported by this device. + #endif +; End restriction +; + #set CLOCKSOURCE SUBCLOCK ; Clocksource + #set ENABLE_SUBCLOCK ON ; Subclock: ON/OFF + #set PLLSPEED 0x010F ; 0x48Ch, 0x48Dh: PLLDIVM/N ; n. a. + #set DIV_G 0x0F ; 0x48Eh: PLLDIVG; + #set MUL_G 0x0F ; 0x48Fh: PLLMULG; + ; Clock Divider + #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 32 KHz + #set PERCLOCK 0x00 ; 0x486h: DIV0R_P; => /1 ; 32 KHz + #set EXTBUSCLOCK 0x00 ; 0x487h: DIV1R_T; => /1 ; 32 KHz + ; CAN Clock + #set PSCLOCKSOURCE PSCLOCK_MAIN ; 0x4C0h: CANPRE; => MAIN ; 4 MHz + #set PSDVC 0x01 ; 0x4C0h: CANPRE_DVC; => /2 ; 2 MHz + #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled + ; Voltage Regulator + #set REGULATORSEL 0x06 ; 0x4CEh: REGSEL; + #set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR; + ; Memory Controller + #set FLASHCONTROL 0x032 ; 0x7002h: FCHCR; + #set FLASHREADT 0xC100 ; 0x7004h: FMWT; + #set FLASHMWT2 0x00 ; 0x7006h: FMWT2; +#endif +; +;========================================================================================= +; 5.3 CLOCKSPEED == MAIN__4MHZ_CPU___2MHZ_PER__1MHZ_EXT__1MHZ_CAN__2MHZ +;========================================================================================= +; +#if (CLOCKSPEED == MAIN_4MHZ_CPU___2MHZ_PER__1MHZ_EXT__1MHZ_CAN__2MHZ ) +; +; Start restriction; Maximum frequency + #if (DEVICE == MB91461R) + #error: Frequency is not supported by this device. + #endif +; End restriction +; + #set CLOCKSOURCE MAINCLOCK ; Clocksource + #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF + #set PLLSPEED 0x010F ; 0x48Ch, 0x48Dh: PLLDIVM/N ; n. a. + #set DIV_G 0x0F ; 0x48Eh: PLLDIVG; + #set MUL_G 0x0F ; 0x48Fh: PLLMULG; + ; Clock Divider + #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 2 MHz + #set PERCLOCK 0x01 ; 0x486h: DIV0R_P; => /2 ; 1 MHz + #set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 1 MHz + ; CAN Clock + #set PSCLOCKSOURCE PSCLOCK_MAIN ; 0x4C0h: CANPRE; => PLLx ; 4 MHz + #set PSDVC 0x01 ; 0x4C0h: CANPRE_DVC; => /2 ; 2 MHz + #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled + ; Voltage Regulator + #set REGULATORSEL 0x06 ; 0x4CEh: REGSEL; + #set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR; + ; Memory Controller + #set FLASHCONTROL 0x032 ; 0x7002h: FCHCR; + #set FLASHREADT 0xC100 ; 0x7004h: FMWT; + #set FLASHMWT2 0x00 ; 0x7006h: FMWT2; +#endif +; +;========================================================================================= +; 5.4 CLOCKSPEED == PLL_4MHZ__CPU__48MHZ_PER_16MHZ_EXT_24MHZ_CAN_16MHZ +;========================================================================================= +; +#if (CLOCKSPEED == PLL_4MHZ__CPU__48MHZ_PER_16MHZ_EXT_24MHZ_CAN_16MHZ ) +; +; Start restriction; Maximum frequency + #if (DEVICE == MB91461R) + #error: Frequency is not supported by this device. + #endif +; End restriction +; + #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource + #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF + #set PLLSPEED 0x010B ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 48 MHz + #set DIV_G 0x0F ; 0x48Eh: PLLDIVG; + #set MUL_G 0x0B ; 0x48Fh: PLLMULG; + ; Clock Divider + #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 48 MHz + #set PERCLOCK 0x02 ; 0x486h: DIV0R_P; => /3 ; 16 MHz + #set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 24 MHz + ; CAN Clock + #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 96 MHz + #set PSDVC 0x05 ; 0x4C0h: CANPRE_DVC; => /6 ; 16 MHz + #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled + ; Voltage Regulator + #if (DEVICE == MB91469G) + #set REGULATORSEL 0x36 ; 0x4CEh: REGSEL; + #else + #set REGULATORSEL 0x06 ; 0x4CEh: REGSEL; + #endif + #set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR; + ; Memory Controller + #set FLASHCONTROL 0x032 ; 0x7002h: FCHCR; + #set FLASHREADT 0xC201 ; 0x7004h: FMWT; + #set FLASHMWT2 0x00 ; 0x7006h: FMWT2; +#endif +; +;========================================================================================= +; 5.5 CLOCKSPEED == PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ +;========================================================================================= +; +#if (CLOCKSPEED == PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ ) +; +; Start restriction; Maximum frequency + #if (DEVICE == MB91461R) + #error: Frequency is not supported by this device. + #endif +; End restriction +; + #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource + #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF + #set PLLSPEED 0x010F ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 64 MHz + #set DIV_G 0x0F ; 0x48Eh: PLLDIVG; + #set MUL_G 0x0F ; 0x48Fh: PLLMULG; + ; Clock Divider + #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 64 MHz + #set PERCLOCK 0x03 ; 0x486h: DIV0R_P; => /4 ; 16 MHz + #set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 32 MHz + ; CAN Clock + #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 128 MHz + #set PSDVC 0x07 ; 0x4C0h: CANPRE_DVC; => /8 ; 16 MHz + #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled + ; Voltage Regulator + #set REGULATORSEL 0x06 ; 0x4CEh: REGSEL; + #set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR; + ; Memory Controller + #set FLASHCONTROL 0x032 ; 0x7002h: FCHCR; + #set FLASHREADT 0xC413 ; 0x7004h: FMWT; + #set FLASHMWT2 0x10 ; 0x7006h: FMWT2; +#endif +; +;========================================================================================= +; 5.6 CLOCKSPEED == PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_27MHZ_CAN_20MHZ +;========================================================================================= +; +#if (CLOCKSPEED == PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_27MHZ_CAN_20MHZ ) +; +; Start restriction; Maximum frequency + #if (DEVICE == MB91461R) + #error: Frequency is not supported by this device. + #endif +; End restriction +; + #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource + #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF + #set PLLSPEED 0x0113 ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 80 MHz + #set DIV_G 0x0F ; 0x48Eh: PLLDIVG; + #set MUL_G 0x13 ; 0x48Fh: PLLMULG; + ; Clock Divider + #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 80 MHz + #set PERCLOCK 0x03 ; 0x486h: DIV0R_P; => /4 ; 20 MHz + #set EXTBUSCLOCK 0x02 ; 0x487h: DIV1R_T; => /3 ; 27 MHz + ; CAN Clock + #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 160 MHz + #set PSDVC 0x07 ; 0x4C0h: CANPRE_DVC; => /8 ; 8 MHz + #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled + ; Voltage Regulator + #set REGULATORSEL 0x06 ; 0x4CEh: REGSEL; + #set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR; + ; Memory Controller + #set FLASHCONTROL 0x032 ; 0x7002h: FCHCR; + #set FLASHREADT 0xC413 ; 0x7004h: FMWT; + #set FLASHMWT2 0x10 ; 0x7006h: FMWT2; +#endif +; +;========================================================================================= +; 5.7 CLOCKSPEED == PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_40MHZ_CAN_20MHZ +;========================================================================================= +; +#if (CLOCKSPEED == PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_40MHZ_CAN_20MHZ ) +; +; Start restriction; Maximum frequency + #if (DEVICE == MB91461R) + #error: Frequency is not supported by this device. + #endif +; End restriction +; + #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource + #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF + #set PLLSPEED 0x0113 ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 80 MHz + #set DIV_G 0x0F ; 0x48Eh: PLLDIVG; + #set MUL_G 0x13 ; 0x48Fh: PLLMULG; + ; Clock Divider + #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 80 MHz + #set PERCLOCK 0x03 ; 0x486h: DIV0R_P; => /4 ; 20 MHz + #set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 40 MHz + ; CAN Clock + #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 160 MHz + #set PSDVC 0x07 ; 0x4C0h: CANPRE_DVC; => /8 ; 8 MHz + #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled + ; Voltage Regulator + #set REGULATORSEL 0x06 ; 0x4CEh: REGSEL; + #set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR; + ; Memory Controller + #set FLASHCONTROL 0x032 ; 0x7002h: FCHCR; + #set FLASHREADT 0xC413 ; 0x7004h: FMWT; + #set FLASHMWT2 0x10 ; 0x7006h: FMWT2; +#endif +; +;========================================================================================= +; 5.8 CLOCKSPEED == PLL_4MHZ__CPU__96MHZ_PER_16MHZ_EXT_48MHZ_CAN_16MHZ +;========================================================================================= +; +#if (CLOCKSPEED == PLL_4MHZ__CPU__96MHZ_PER_16MHZ_EXT_48MHZ_CAN_16MHZ ) +; +; Start restriction; Maximum frequency + #if (DEVICE == MB91464A) || (DEVICE == MB91465K) || (DEVICE == MB91463N) ||\ + (DEVICE == MB91461R) || (DEVICE == MB91467R) + #error: Frequency is not supported by this device. + #endif +; End restriction +; + #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource + #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF + #set PLLSPEED 0x0117 ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 96 MHz + #set DIV_G 0x0F ; 0x48Eh: PLLDIVG; + #set MUL_G 0x17 ; 0x48Fh: PLLMULG; + ; Clock Divider + #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 64 MHz + #set PERCLOCK 0x05 ; 0x486h: DIV0R_P; => /6 ; 16 MHz + #set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 32 MHz + ; CAN Clock + #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 192 MHz + #set PSDVC 0x0B ; 0x4C0h: CANPRE_DVC; => /12 ; 16 MHz + #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled + ; Voltage Regulator + #if (DEVICE == MB91469G) + #set REGULATORSEL 0x36 ; 0x4CEh: REGSEL; + #else + #set REGULATORSEL 0x06 ; 0x4CEh: REGSEL; + #endif + #set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR; + ; Memory Controller + #set FLASHCONTROL 0x032 ; 0x7002h: FCHCR; + #set FLASHREADT 0xC413 ; 0x7004h: FMWT; + #set FLASHMWT2 0x10 ; 0x7006h: FMWT2; +#endif +; +;========================================================================================= +; 5.9 CLOCKSPEED == PLL_4MHZ__CPU_100MHZ_PER_20MHZ_EXT_50MHZ_CAN_20MHZ +;========================================================================================= +; +#if (CLOCKSPEED == PLL_4MHZ__CPU_100MHZ_PER_20MHZ_EXT_50MHZ_CAN_20MHZ ) +; +; Start restriction; Maximum frequency + #if (DEVICE == MB91464A) || (DEVICE == MB91465K) || (DEVICE == MB91463N) ||\ + (DEVICE == MB91461R) || (DEVICE == MB91467R) || (DEVICE == MB91467D) + #error: Frequency is not supported by this device. + #endif +; End restriction +; + #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource + #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF + #set PLLSPEED 0x0118 ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 100 MHz + #set DIV_G 0x0F ; 0x48Eh: PLLDIVG; + #set MUL_G 0x17 ; 0x48Fh: PLLMULG; + ; Clock Divider + #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 100 MHz + #set PERCLOCK 0x04 ; 0x486h: DIV0R_P; => /5 ; 20 MHz + #set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 50 MHz + ; CAN Clock + #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 200 MHz + #set PSDVC 0x09 ; 0x4C0h: CANPRE_DVC; => /10 ; 20 MHz + #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled + ; Voltage Regulator + #if (DEVICE == MB91469G) + #set REGULATORSEL 0x36 ; 0x4CEh: REGSEL; + #else + #set REGULATORSEL 0x06 ; 0x4CEh: REGSEL; + #endif + #set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR; + ; Memory Controller + #set FLASHCONTROL 0x032 ; 0x7002h: FCHCR; + #set FLASHREADT 0xC413 ; 0x7004h: FMWT; + #set FLASHMWT2 0x10 ; 0x7006h: FMWT2; +#endif +; +;========================================================================================= +; 5.10 CLOCKSPEED == PLL_10MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ +;========================================================================================= +; +#if (CLOCKSPEED == PLL_10MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ ) +; +; Start restriction; Maximum frequency + #if (DEVICE == MB91464A) || (DEVICE == MB91467B) || (DEVICE == MB91467C) ||\ + (DEVICE == MB91467D) || (DEVICE == MB91469G) || (DEVICE == MB91465K) ||\ + (DEVICE == MB91463N) || (DEVICE == MB91467R) || (DEVICE == MB91465X) + #error: Frequency is not supported by this device. + #endif +; End restriction +; + #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource + #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF + #set PLLSPEED 0x0105 ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 60 MHz + #set DIV_G 0x0B ; 0x48Eh: PLLDIVG; + #set MUL_G 0x1F ; 0x48Fh: PLLMULG; + ; Clock Divider + #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 60 MHz + #set PERCLOCK 0x02 ; 0x486h: DIV0R_P; => /3 ; 20 MHz + #set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 30 MHz + ; CAN Clock + #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 120 MHz + #set PSDVC 0x05 ; 0x4C0h: CANPRE_DVC; => /6 ; 20 MHz + #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled + ; Voltage Regulator + ; - + ; Memory Controller + ; - +#endif +; +;========================================================================================= +; 5.11 CLOCKSPEED == PLL_20MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ +;========================================================================================= +; +#if (CLOCKSPEED == PLL_20MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ ) +; +; Start restriction; Maximum frequency + #if (DEVICE == MB91464A) || (DEVICE == MB91467B) || (DEVICE == MB91467C) ||\ + (DEVICE == MB91467D) || (DEVICE == MB91469G) || (DEVICE == MB91465K) ||\ + (DEVICE == MB91463N) || (DEVICE == MB91467R) || (DEVICE == MB91465X) + #error: Frequency is not supported by this device. + #endif +; End restriction +; + #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource + #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF + #set PLLSPEED 0x0102 ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 60 MHz + #set DIV_G 0x0F ; 0x48Eh: PLLDIVG; + #set MUL_G 0x1F ; 0x48Fh: PLLMULG; + ; Clock Divider + #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 60 MHz + #set PERCLOCK 0x02 ; 0x486h: DIV0R_P; => /3 ; 20 MHz + #set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 30 MHz + ; CAN Clock + #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 120 MHz + #set PSDVC 0x05 ; 0x4C0h: CANPRE_DVC; => /6 ; 20 MHz + #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled + ; Voltage Regulator + ; - + ; Memory Controller + ; - +#endif +; +;========================================================================================= +; 6 Section and Data Declaration +;========================================================================================= + + .export __start + .import _main + .import _RAM_INIT + .import _ROM_INIT + +#if CLIBINIT == ON + .export __exit + .import _exit + .import __stream_init +#endif + +#if CPLUSPLUS == ON + .export __abort + .import ___call_dtors + .import _atexit +#endif +;========================================================================================= +; 6.1 Define Stack Size +;========================================================================================= + .SECTION SSTACK, STACK, ALIGN=4 +#if STACK_RESERVE == ON + .EXPORT __systemstack, __systemstack_top + __systemstack: + .RES.B STACK_SYS_SIZE + __systemstack_top: +#endif + + .SECTION USTACK, STACK, ALIGN=4 +#if STACK_RESERVE == ON + .EXPORT __userstack, __userstack_top + __userstack: + .RES.B STACK_USR_SIZE + __userstack_top: + +#endif +;========================================================================================= +; 6.2 Define Sections +;========================================================================================= + .section DATA, data, align=4 + .section INIT, data, align=4 + .section IRAM, code, align=4 + .section CONST, const, align=4 + .section INTVECT, const, align=4 + +#if I_RAM + .import _RAM_IRAM + .import _ROM_IRAM +#endif + +#if (DEVICE != MB91461R) + #if (DEVICE == MB91469G) + .section SECURITY_VECTORS, code, locate = 0x248000 + #else + .section SECURITY_VECTORS, code, locate = 0x148000 + #endif + + #if (BOOT_FLASH_SEC == OFF) + .data.w 0xFFFFFFFF + .data.w 0xFFFFFFFF + .data.w 0xFFFFFFFF + .data.w 0xFFFFFFFF + #else + .res.w 4 + #endif +#endif + +#if CPLUSPLUS == ON + .section EXT_CTOR_DTOR, const, align=4 ; C++ constructors +#endif + +;----------------------------------------------------------------------------------------- +; MACRO Clear RC Watchdog +;----------------------------------------------------------------------------------------- +#macro ClearRCwatchdog + LDI #0x4C7,R7 ; clear RC watchdog + BANDL #0x7,@R7 +#endm +;----------------------------------------------------------------------------------------- +; MACRO WAIT_LOOP +;----------------------------------------------------------------------------------------- +#macro wait_loop loop_number +#local _wait64_loop + LDI #loop_number, R0 +_wait64_loop: + ADD #-1, R0 + BNE _wait64_loop +#endm + .section CODE, code, align=4 + .section CODE_START, code, align=4 + + +;========================================================================================= +; 7. S T A R T +;========================================================================================= +__start: ; start point +startnop: + NOP +; + ANDCCR #0xEF ; disable interrupts + STILM #LOW_PRIOR ; set interrupt level to low prior + ClearRCwatchdog ; clear harware watchdog + +;========================================================================================= +; 7.1 Initialise Stack Pointer and Table Base Register +;========================================================================================= +#if STACKUSE == SYSSTACK + ORCCR #0x20 + LDI #__userstack_top, SP ; initialize SP + ANDCCR #0xDF + LDI #__systemstack_top, SP ; initialize SP +#endif + +#if STACKUSE == USRSTACK + ANDCCR #0xDF + LDI #__systemstack_top, SP ; initialize SP + ORCCR #0x20 + LDI #__userstack_top, SP ; initialize SP +#endif + + LDI #INTVECT, R0 ; set Table Base +smd_tbr: + MOV R0, TBR + +#if (CLOCKSOURCE != NOCLOCK) +;========================================================================================= +; 7.2 Check for CSV reset and set CSV +;========================================================================================= +; Start restriction; No clock supervisor (CSV) +#if (DEVICE != MB91461R) && (DEVICE != MB91467R) && (DEVICE != MB91463N) +; End restriction + LDI:20 #0x04AD, R0 ; CSVCR + BORL #0x8, @R0 ; Enable Main Osc CSV + BTSTH #0x4, @R0 ; Check for Main Osc missing + BEQ NoMAINCSVreset ; Main osc available -> branch + ; to NoCSVreset + BANDL #0x7, @R0 ; Disable Main Osc CSV + + LDI #noClockStartup, R0 ; Main Clock missing -> no + JMP @R0 ; clock startup + +NoMAINCSVreset: + + + BORL #0x4, @R0 ; Enable Sub Osc CSV + BTSTH #0x2, @R0 ; Check for Sub Osc missing + BEQ NoSUBCSVreset ; Sub osc available -> branch + ; to NoCSVreset + BANDL #0xB, @R0 ; Disable Sub Osc SCSV +#if (CLOCKSOURCE == SUBCLOCK) + LDI #noClockStartup, R0 ; Sub Clock missing -> no + JMP @R0 ; clock startup +#endif +NoSUBCSVreset: +#endif +;========================================================================================= +; 7.3 Check Clock Condition +;========================================================================================= + LDI #0x484, R0 ; Check for Default Values + LDI #0x0F, R1 + ANDB R1, @R0 + BEQ clock_startup + +;========================================================================================= +; 7.4 Restore Default Settings after Reset +;========================================================================================= +;========================================================================================= +; 7.4.1 Disable Clock Modulator +;========================================================================================= + LDI #0x04BB, R0 ; Clock Modulator Control Reg + BANDL #0xD, @R0 ; Disable Frequency modulation +FMODwait: + BTSTL #8, @R0 ; Wait until Frequency modulation + BNE FMODwait ; is disabled + + BANDL #0xE, @R0 ; Power down clock modulator + +;========================================================================================= +; 7.4.2 Check if running on Sub Clock, change to Main Clock +;========================================================================================= + LDI:20 #0x0484,R12 ; Check if running on sub clock + LDUB @R12,R0 + LDI:8 #0x3,R1 + AND R1,R0 + CMP #0x3,R0 + BNE notOnSubClock + + LDI:20 #0x04CC,R12 ; Check if Main Clock is stopped + BTSTL #1, @R12 + BEQ mainNotStopped + + BANDL #0xE, @R12 ; Start Main Oscillation + + LDI #0x4C8, R0 ; Main Stabilisation Wait Time + LDI #0x04, R1 ; 32.7 ms + AND R1, @R0 + BORH #0x02, @R0 + + mainStabTime: ; Wait for stabilisation time + ClearRCwatchdog ; clear harware watchdog + BTSTH #8, @R0 + BEQ mainStabTime + LDI #0x0, R1 + STB R1, @R0 + +mainNotStopped: + LDI:20 #0x0484, R12 ; disable sub clock as source + BANDL #0xD, @R12 ; Clock source = 0x01 (Main/2) + +notOnSubClock: +;========================================================================================= +; 7.4.3 Disable Sub Clock +;========================================================================================= +#if ENABLE_SUBCLOCK != ON + LDI #0x0484, R0 ; Clock source control reg CLKR + BANDL #0x7, @R0 ; Disable PLL +#endif + +;========================================================================================= +; 7.4.4 Check if running on PLL, Gear Down PLL +;========================================================================================= + LDI:20 #0x0484,R12 ; Check if running on PLL + LDUB @R12,R0 + LDI:8 #0x3,R1 + AND R1,R0 + CMP #0x2,R0 + BNE notOnPll + + LDI:20 #0x0490, R11 ; clear flags + LDI:8 #0x0,R1 + STB R1, @R11 + LDI #0x04,R1 + STB R1, @R11 ; Set Flag for Simulator; no Effekt on + ; Emulator + + BANDL #0xC, @R12 ; disable PLL as clock source + ; Clock Source = 0x00 (Main/2) + + LDI:20 #0x048E,R12 ; check if DivG != 0 + LDUB @R12, R0 + LDI:8 #0xFF,R1 + AND R1,R0 + BEQ notOnPll + +gearDownLoop: + ClearRCwatchdog ; clear harware watchdog + BTSTL #4, @R11 ; Gear Down + BEQ gearDownLoop ; + + LDI #0x00,R1 ; Clear Flags + STB R1, @R11 ; + +notOnPll: +;========================================================================================= +; 7.4.5 Disable PLL +;========================================================================================= + LDI #0x0484, R0 ; Clock source control reg CLKR + BANDL #0xB, @R0 ; Disable PLL + +;========================================================================================= +; 7.4.6 Set to Main Clock +;========================================================================================= + LDI:20 #0x0484,R12 ; Check if running on PLL + BANDL #0xC, @R12 ; disable PLL as clock source + ; Clock Source = 0x00 (Main/2) + +clock_startup: +;========================================================================================= +; 7.5 Set Memory Controller +;========================================================================================= +; Start restriction; No embedded flash +#if DEVICE != MB91461R +; End restriction + LDI #0x7002, R1 ; FLASH Controller Reg. + LDI #FLASHCONTROL, R2 ; Flash Controller Settings + STH R2, @R1 ; set register + LDI #0x7004, R1 ; FLASH Memory Wait Timing Reg. + LDI #FLASHREADT, R2 ; wait settings + STH R2, @R1 ; set register + LDI #0x7006, R1 ; FLASH Memory Wait Timing Reg. + LDI #FLASHMWT2, R2 ; wait settings + STB R2, @R1 ; set register +#endif + ClearRCwatchdog + +;========================================================================================= +; 7.6 Clock startup +;========================================================================================= +;========================================================================================= +; 7.6.1 Set Voltage Regulator Settings +;========================================================================================= +; Start restriction; No regulator settings +#if DEVICE != MB91461R +; End restriction + LDI #0x04CF, R0 ; REGCTR + LDI #REGULATORCTRL, R1 + STB R1, @R0 + + LDI #0x04CE, R0 ; REGSEL + LDI #REGULATORSEL, R1 + STB R1, @R0 +#endif + +;========================================================================================= +; 7.6.2 Power on Clock Modulator - Clock Modulator Part I +;========================================================================================= +#if CLOMO == ON + LDI #0x04BB, R0 ; Clock Modulator Control Reg + LDI #0x11, R1 ; Load value to Power on CM + ORB R1, @R0 ; Power on clock modulaor +#endif + +;========================================================================================= +; 7.6.3 Set CLKR Register w/o Clock Mode +;========================================================================================= +; Set Clock source (Base Clock) for the three clock tree selections +; This select Base clock is used to select afterwards the 3 +; Clocks for the diffenrent internal trees. +; When PLL is used, first pll multiplication ratio is set and PLL is +; enabled. After waiting the PLL stabilisation time via timebase +; timer, PLL clock is selected as clock source. + LDI #0x048C, R0 ; PLL Cntl Reg. PLLDIVM/N + LDI:20 #PLLSPEED, R1 + STH R1, @R0 + + LDI #0x048E, R0 ; PLL Cntl Reg. PLLDIVG + LDI #DIV_G, R1 + STB R1, @R0 + + LDI #0x048F, R0 ; PLL Cntl Reg. PLLMULG + LDI #MUL_G, R1 + STB R1, @R0 + +;========================================================================================= +; 7.6.4 Start PLL +;========================================================================================= +#if ( ( CLOCKSOURCE == MAINPLLCLOCK ) || ( PSCLOCKSOURCE == PSCLOCK_PLL ) ) + LDI #0x0484, R0 ; Clock source control reg CLKR + LDI #0x04, R1 ; Use PLL x1, enable PLL + ORB R1, @R0 ; store data to CLKR register +#endif + + +#if ENABLE_SUBCLOCK == ON + LDI #0x0484, R0 ; Clock source control reg CLKR + LDI #0x08, R1 ; enable subclock operation + ORB R1, @R0 ; store data to CLKR register + LDI #0x4CA, R0 ; Sub Clock oszilation + LDI #0x00, R1 ; stabilitsation time = 32 ms + AND R1, @R0 + BORH #0x02, @R0 +#endif + +;========================================================================================= +; 7.6.5 Wait for PLL oscillation stabilisation +;========================================================================================= +#if ((CLOCKSOURCE==MAINPLLCLOCK)||(PSCLOCKSOURCE==PSCLOCK_PLL)) + LDI #0x0482, R12 ; TimeBaseTimer TBCR + LDI #0x00, R1 ; set 1024 us @ 2 MHz + STB R1, @R12 + + BANDH #7, @R12 ; clear interrupt flag + + LDI #0x0483, R0 ; clearTimeBaseTimer CTBR + LDI #0xA5, R1 + STB R1, @R0 + LDI #0x5A, R1 + STB R1, @R0 + + BANDH #7, @R12 ; clear interrupt flag + BORH #8, @R12 ; set interrupt flag for simulator + +PLLwait: + ClearRCwatchdog ; clear harware watchdog + BTSTH #8, @R12 + BEQ PLLwait +#endif + +;========================================================================================= +; 7.6.6 Set clocks +;========================================================================================= +;========================================================================================= +; 7.6.6.1 Set CPU and peripheral clock +;========================================================================================= +; CPU and peripheral clock are set in one register + LDI #0x0486, R2 ; Set DIVR0 (CPU-clock (CLKB) + LDI #((CPUCLOCK << 4) + PERCLOCK), R3 ; Load CPU clock setting + STB R3, @R2 +;========================================================================================= +; 7.6.6.2 Set External Bus interface clock +;========================================================================================= +; set External Bus clock +; Be aware to do smooth clock setting, to avoid wrong clock setting +; Take care, always write 0 to the lower 4 bits of DIVR1 register + LDI #0x0487, R2 ; Set DIVR1 + LDI #(EXTBUSCLOCK << 4), R3 ; Load Peripheral clock setting + STB R3, @R2 + +;========================================================================================= +; 7.6.6.3 Set CAN clock prescaler +;========================================================================================= +; Set CAN Prescaler, only clock relevant parameter + LDI #0x04C0, R0 ; Set CAN ClockParameter Register + LDI #(PSCLOCKSOURCE + PSDVC), R1 ; Load Divider + STB R1, @R0 ; Set Divider +; enable CAN clocks + LDI #0x04c1, R0 ; Set CAN Clock enable Register + LDI #CANCLOCK, R1 ; Load CANCLOCK + STB R1, @R0 ; set CANCLOCK + +;========================================================================================= +; 7.6.6.4 Switch Main Clock Mode +;========================================================================================= +#if CLOCKSOURCE == MAINCLOCK + +;========================================================================================= +; 7.6.6.5 Switch Subclock Mode +;========================================================================================= +#elif ( (CLOCKSOURCE == SUBCLOCK) ) + #if ENABLE_SUBCLOCK == ON + LDI #0x4CA, R12 +subStabTime: + ClearRCwatchdog ; clear harware watchdog + BTSTH #8, @R12 ; wait until sub clock stabilisation + BEQ subStabTime ; time is over + LDI #0x0, R1 + STB R1, @R12 + + LDI #0x0484, R0 ; Clock source control reg CLKR + LDI #0x01, R1 ; load value to select main clock + ORB R1, @R0 ; enable main clock (1/2 external) + LDI #0x03, R1 ; load value to select subclock + ORB R1, @R0 ; enable subclock as clock source + #else + #error: Wrong setting! The clock source is subclock, but the subclock is disabled. + #endif + +;========================================================================================= +; 7.6.7 Switch to PLL Mode +;========================================================================================= +#elif ( (CLOCKSOURCE == MAINPLLCLOCK) ) + +#if (DIV_G != 0x00) + LDI #0x0490, R0 ; PLL Ctrl Register + LDI #0x00,R1 + STB R1, @R0 ; Clear Flag + LDI #0x01,R1 + STB R1, @R0 ; Set Flag for Simulator; no Effekt on +#endif ; Emulator + + LDI #0x0484, R3 ; Clock source control reg CLKR + BORL #0x2, @R3 ; enable PLL as clock source + +#if (DIV_G != 0x00) +gearUpLoop: + ClearRCwatchdog ; clear harware watchdog + LDUB @R0, R2 ; LOAD PLLCTR to R2 + AND R1, R2 ; GRUP, counter reach 0 + BEQ gearUpLoop + + LDI #0x00,R1 + STB R1, @R0 ; Clear Gear-Up Flag +#endif + +#endif + +;========================================================================================= +; 7.6.8 Enable Frequncy Modulation - Clock Modulator Part II +;========================================================================================= +#if CLOMO == ON ; Only applicable if Modulator is on + LDI #0x04B8, R0 ; Clock Modulation Parameter Reg + LDI #CMPR, R1 ; Load CMP value + STH R1, @R0 ; Store CMP value in CMPR + + LDI #0x04BB, R0 ; Clock Modulator Control Reg + LDI #0x13, R1 ; Load value to FM on CM + ORB R1, @R0 ; FM on +#endif + +#endif +noClockStartup: + +;========================================================================================= +; 7.7 Set BusInterface +;========================================================================================= +; Start restriction; No ext. bus interface +#if (DEVICE != MB91464A) && (DEVICE != MB91467C) && (DEVICE != MB91465K) && \ + (DEVICE != MB91463N) && (DEVICE != MB91465X) +; End restriction +#if (EXTBUS == ON) +;========================================================================================= +; 7.7.1 Disable all CS +;========================================================================================= +; Start restriction; Flashless device +#if(DEVICE != MB91461R) +; End restriction + LDI #0x0680, R3 ; chip select enable register CSER + LDI #(0x00), R2 ; load disable settings +smd_cs: + ANDB R2, @R3 ; set register +#endif + +;========================================================================================= +; 7.7.2 Clear TCR Register +;========================================================================================= + LDI #0x0683, R1 ; Pin/Timing Control Register TCR + BORH #0x6,@R1 ; load timing settings + +;========================================================================================= +; 7.7.3 Set CS0 +;========================================================================================= +#if CS0 + LDI #0x0640, R1 ; area select reg ASR0, ACR0 + LDI #(AREASEL0<<16)+CONFIGCS0, R0 ; load settings + ST R0, @R1 ; set registers + + LDI #0x660, R1 ; area wait register awr0 + LDI #WAITREG0, R2 ; wait settings + STH R2, @R1 ; set register +#endif + +;========================================================================================= +; 7.7.4 Set CS1 +;========================================================================================= +#if CS1 + LDI #0x0644, R1 ; area select reg ASR1, ACR1 + LDI #(AREASEL1<<16)+CONFIGCS1, R0 ; load settings + ST R0, @R1 ; set registers + + LDI #0x662, R1 ; area wait register awr1 + LDI #WAITREG1, R2 ; wait settings + STH R2, @R1 ; set register +#endif +smd_cs_mb91461r: +;========================================================================================= +; 7.7.5 Set CS2 +;========================================================================================= +#if CS2 + LDI #0x0648, R1 ; area select reg ASR2, ACR2 + LDI #(AREASEL2<<16)+CONFIGCS2, R0 ; load settings + ST R0, @R1 ; set registers + LDI #0x664, R1 ; area wait register awr2 + LDI #WAITREG2, R2 ; wait settings + STH R2, @R1 ; set register +#endif +;========================================================================================= +; 7.7.6 Set CS3 +;========================================================================================= +#if CS3 + LDI #0x064C, R1 ; area select reg ASR3, ACR3 + LDI #(AREASEL3<<16)+CONFIGCS3, R0 ; load settings + ST R0, @R1 ; set registers + LDI #0x666, R1 ; area wait register awr3 + LDI #WAITREG3, R2 ; wait settings + STH R2, @R1 ; set register +#endif +;========================================================================================= +; 7.7.7 Set CS4 +;========================================================================================= +#if CS4 + LDI #0x0650, R1 ; area select reg ASR4, ACR4 + LDI #(AREASEL4<<16)+CONFIGCS4, R0 ; load settings + ST R0, @R1 ; set registers + LDI #0x668, R1 ; area wait register awr4 + LDI #WAITREG4, R2 ; wait settings + STH R2, @R1 ; set register +#endif +;========================================================================================= +; 7.7.8 Set CS5 +;========================================================================================= +#if CS5 + LDI #0x0654, R1 ; area select reg ASR5, ACR5 + LDI #(AREASEL5<<16)+CONFIGCS5, R0 ; load settings + ST R0, @R1 ; set registers + LDI #0x66A, R1 ; area wait register awr5 + LDI #WAITREG5, R2 ; wait settings + STH R2, @R1 ; set register +#endif +;========================================================================================= +; 7.7.9 Set CS6 +;========================================================================================= +#if (CS6) + LDI #0x0658, R1 ; area select reg ASR6, ACR6 + LDI #(AREASEL6<<16)+CONFIGCS6, R0 ; load settings + ST R0, @R1 ; set registers + LDI #0x66C, R1 ; area wait register awr6 + LDI #WAITREG6, R2 ; wait settings + STH R2, @R1 ; set register +#endif +;========================================================================================= +; 7.7.10 Set CS7 +;========================================================================================= +#if CS7 + LDI #0x065C, R1 ; area select reg ASR7, ACR7 + LDI #(AREASEL7<<16)+CONFIGCS7, R0 ; load settings + ST R0, @R1 ; set registers + LDI #0x66E, R1 ; area wait register awr7 + LDI #WAITREG7, R2 ; wait settings + STH R2, @R1 ; set register +#endif +;========================================================================================= +; 7.7.11 Set special SDRAM config register +;========================================================================================= +#if (SDRAM) + LDI #0x670, R1 ; SDRAM memory config register + LDI #MEMCON, R2 ; wait settings + STB R2, @R1 ; set register +#endif + +;========================================================================================= +; 7.7.12 set Port Function Register +;========================================================================================= +;========================================================================================= +; 7.7.12.1 set PFR00 Register. External bus mode (D[24-31]) or General purpose port +;========================================================================================= + LDI #0x0D80, R1 ; Port Function Register 0, (PFR00) + LDI #PFUNC0, R0 ; load port settings + STB R0, @R1 ; set register +;========================================================================================= +; 7.7.12.2 set PFR01 Register. External bus mode (D[16-23]) or General purpose port +;========================================================================================= + LDI #0x0D81, R1 ; Port Function Register 1, (PFR01) + LDI #PFUNC1, R0 ; load port settings + STB R0, @R1 ; set register +;========================================================================================= +; 7.7.12.3 set PFR02 Register. External bus mode (D[8-15]) or General purpose port +;========================================================================================= + LDI #0x0D82, R1 ; Port Function Register 2, (PFR02) + LDI #PFUNC2, R0 ; load port settings + STB R0, @R1 ; set register +;========================================================================================= +; 7.7.12.4 set PFR03 Register. External bus mode (D[0-7]) or General purpose port +;========================================================================================= + LDI #0x0D83, R1 ; Port Function Register 3, (PFR03) + LDI #PFUNC3, R0 ; load port settings + STB R0, @R1 ; set register +;========================================================================================= +; 7.7.12.5 set PFR04 Register. External bus mode (Adr[24-31]) or General purpose port +;========================================================================================= + LDI #0x0D84, R1 ; Port Function Register 4, (PFR04) + LDI #PFUNC4, R0 ; load port settings + STB R0, @R1 ; set register +;========================================================================================= +; 7.7.12.6 set PFR05 Register. External bus mode (Adr[16-23]) or General purpose port +;========================================================================================= + LDI #0x0D85, R1 ; Port Function Register 5, (PFR05) + LDI #PFUNC5, R0 ; load port settings + STB R0, @R1 ; set register +;========================================================================================= +; 7.7.12.7 set PFR06 Register. External bus mode (Adr[8-15]) or General purpose port +;========================================================================================= + LDI #0x0D86, R1 ; Port Function Register 6, (PFR06) + LDI #PFUNC6, R0 ; load port settings + STB R0, @R1 ; set register +;========================================================================================= +; 7.7.12.8 set PFR07 Register. External bus mode (Adr[0-7]) or General purpose port +;========================================================================================= + LDI #0x0D87, R1 ; Port Function Register 7, (PFR07) + LDI #PFUNC7, R0 ; load port settings + STB R0, @R1 ; set register +;========================================================================================= +; 7.7.12.9 set PFR08 Register. External bus mode (Control Signals) or GIO port +;========================================================================================= + LDI #0x0D88, R1 ; Port Function Register 8, (PFR08) + LDI #PFUNC8, R0 ; load port settings + STB R0, @R1 ; set register +;========================================================================================= +; 7.7.12.10 set PFR09 Register. External bus mode (Control Signals) or GIO port +;========================================================================================= + LDI #0x0D89, R1 ; Port Function Register 9, (PFR09) + LDI #PFUNC9, R0 ; load port settings + STB R0, @R1 ; set register +;========================================================================================= +; 7.7.12.11 set PFR10 Register. External bus mode (Control Signals) or GIO port +;========================================================================================= + LDI #0x0D8A, R1 ; Port Function Register 10, (PFR10) + LDI #PFUNC10, R0 ; load port settings + STB R0, @R1 ; set register +;========================================================================================= +; 7.7.12.12 set EPFR10 Register. External bus mode (Control Signals) or GIO port +;========================================================================================= + LDI #0x0DCA, R1 ; Extended PFR 10, (EPFR10) + LDI #EPFUNC10, R0 ; load port settings + STB R0, @R1 ; set register +;========================================================================================= +; 7.7.13 Set TCR Register +;========================================================================================= + LDI #0x0683, R1 ; Pin/Timing Control Register TCR + LDI #TIMECONTR, R0 ; load timing settings + STB R0, @R1 ; set register +;========================================================================================= +; 7.7.14 Enable CACHE for selected CS +;========================================================================================= + LDI #0x0681, R3 ; chip select enable register CSER + LDI #CHEENA, R2 + ORB R2, @R3 +;========================================================================================= +; 7.7.15 set SDRAM Referesh Control Register +;========================================================================================= +#if (SDRAM) + LDI #0x0684, R1 ; Refresh Control Register RCR + LDI #REFRESH, R0 ; load refresh settings + STH R0, @R1 ; set register + LDI #0x0008, R2 + OR R2, R0 ; Set PON bit to 1 + STH R0, @R1 ; set register +#endif +;========================================================================================= +; 7.7.16 Enable used CS +;========================================================================================= + LDI #0x0680, R3 ; chip select enable register CSER + LDI #ENACSX, R2 +; Start restriction; Flashless device +#if (DEVICE == MB91461R) +; End restriction +emu_sram_cs_mb91461r: + ANDB R2, @R3 ; set register +#else + ORB R2, @R3 +#endif +;========================================================================================= +; 7.7.17 I-cache on/off +;========================================================================================= +; Start restriction; No cache +#if (DEVICE == MB91461R) || (DEVICE == MB91469G) || (DEVICE == others) +; End restriction + #if CACHE + #if CACHE_SIZE == C1024 + LDI #0x03C7, R1 ; Cache size register ISIZE + LDI #0x00, R2 + STB R2, @R1 + LDI #0x03E7, R1 ; Cache control reg ICHCR + LDI #0x07, R2 ; Release entry locks, flush and enable + STB R2, @R1 ; cache + #elif CACHE_SIZE == C2048 + LDI #0x03C7, R1 ; Cache size register ISIZE + LDI #0x01, R2 + STB R2, @R1 + LDI #0x03E7, R1 ; Cache control reg ICHCR + LDI #0x07, R2 ; Release entry locks, flush and enable + STB R2, @R1 ; cache + #elif CACHE_SIZE == C4096 + LDI #0x03C7, R1 ; Cache size register ISIZE + LDI #0x02, R2 + STB R2, @R1 + LDI #0x03E7, R1 ; Cache control reg ICHCR + LDI #0x07, R2 ; Release entry locks, flush and enable + STB R2, @R1 ; cache + #else + #error: Wrong Cache size selected! + #endif + #else + LDI #0x03E7, R1 ; Cache control reg ICHCR + LDI #0x06, R2 ; Release entry locks, flush and disable + STB R2, @R1 ; cache + #endif +#endif +#elif (EXTBUS == OFF) +;========================================================================================= +; 7.7.18 set Port Function Register to general as I/O-Port +;========================================================================================= +;========================================================================================= +; 7.7.18.1 set PFR00 Register. External bus mode as General purpose port +;========================================================================================= + LDI #0x0D80, R1 ; Port Function Register 0, (PFR00) + LDI #0x00, R0 ; load port settings + STB R0, @R1 ; set register +;========================================================================================= +; 7.7.18.2 set PFR01 Register. External bus mode as General purpose port +;========================================================================================= + LDI #0x0D81, R1 ; Port Function Register 1, (PFR01) + LDI #0x00, R0 ; load port settings + STB R0, @R1 ; set register +;========================================================================================= +; 7.7.18.3 set PFR02 Register. External bus mode as General purpose port +;========================================================================================= + LDI #0x0D82, R1 ; Port Function Register 2, (PFR02) + LDI #0x00, R0 ; load port settings + STB R0, @R1 ; set register +;========================================================================================= +; 7.7.18.4 set PFR03 Register. External bus mode as General purpose port +;========================================================================================= + LDI #0x0D83, R1 ; Port Function Register 3, (PFR03) + LDI #0x00, R0 ; load port settings + STB R0, @R1 ; set register +;========================================================================================= +; 7.7.18.5 set PFR04 Register. External bus mode as General purpose port +;========================================================================================= + LDI #0x0D84, R1 ; Port Function Register 4, (PFR04) + LDI #0x00, R0 ; load port settings + STB R0, @R1 ; set register +;========================================================================================= +; 7.7.18.6 set PFR05 Register. External bus mode as General purpose port +;========================================================================================= + LDI #0x0D85, R1 ; Port Function Register 5, (PFR05) + LDI #0x00, R0 ; load port settings + STB R0, @R1 ; set register +;========================================================================================= +; 7.7.18.7 set PFR06 Register. External bus mode as General purpose port +;========================================================================================= + LDI #0x0D86, R1 ; Port Function Register 6, (PFR06) + LDI #0x00, R0 ; load port settings + STB R0, @R1 ; set register +;========================================================================================= +; 7.7.18.8 set PFR07 Register. External bus mode as General purpose port +;========================================================================================= + LDI #0x0D87, R1 ; Port Function Register 7, (PFR07) + LDI #0x00, R0 ; load port settings + STB R0, @R1 ; set register +;========================================================================================= +; 7.7.18.9 set PFR08 Register. External bus mode as General purpose port +;========================================================================================= + LDI #0x0D88, R1 ; Port Function Register 8, (PFR08) + LDI #0x00, R0 ; load port settings + STB R0, @R1 ; set register +;========================================================================================= +; 7.7.18.10 set PFR09 Register. External bus mode as General purpose port +;========================================================================================= + LDI #0x0D89, R1 ; Port Function Register 9, (PFR09) + LDI #0x00, R0 ; load port settings + STB R0, @R1 ; set register +;========================================================================================= +; 7.7.18.11 set PFR10 Register. External bus mode as General purpose port +;========================================================================================= + LDI #0x0D8A, R1 ; Port Function Register 10, (PFR10) + LDI #0x00, R0 ; load port settings + STB R0, @R1 ; set register +;========================================================================================= +; 7.7.18.12 set EPFR10 Register. External bus mode as General purpose port +;========================================================================================= + LDI #0x0DCA, R1 ; Extended PFR10, (EPFR10) + LDI #0x00, R0 ; load port settings + STB R0, @R1 ; set register +;========================================================================================= + +#elif (EXTBUS == DEFAULT) + NOP +smd_cs_mb91461r: +emu_sram_cs_mb91461r: +smd_cs: +#endif ; #endif (EXTBUS) +#endif ; #endif (excl. devices) + ClearRCwatchdog + +;========================================================================================= +; 7.8 Copy code from Flash to I-RAM +;========================================================================================= +#if I_RAM == ON + LDI #_RAM_IRAM, R0 + LDI #_ROM_IRAM, R1 + LDI #sizeof(IRAM), R13 + CMP #0, R13 + BEQ copy_iram_end +copy_iram1: + ADD #-1, R13 + LDUB @(R13, R1), R12 + BNE:D copy_iram1 + STB R12, @(R13, R0) +copy_iram_end: + ClearRCwatchdog +#endif + +;========================================================================================= +; 7.9 Fill stacks +;========================================================================================= +#if STACK_FILL == ON + LDI #STACK_PATTERN, R0 + LDI #SSTACK, R1 + LDI #sizeof(SSTACK), R2 + CMP #0, R2 + BEQ:D fill_sstack_end + MOV R2, R13 + LDI #3, R12 + AND R2, R12 + BEQ:D fill_sstack2 + MOV R2, R3 + SUB R12, R3 + LDI #0x3, R4 + SUB R12, R4 + LSL #0x3, R4 + LDI #STACK_PATTERN, R5 + LSR R4, R5 + LDI #0x8, R4 +fill_sstack1: + ADD #-1, R13 + LSR R4, R5 + CMP R3, R13 + BHI:D fill_sstack1 + STB R5, @(R13, R1) + CMP #0, R3 + BEQ:D fill_sstack_end +fill_sstack2: + ADD #-4, R13 + BGT:D fill_sstack2 + ST R0, @(R13, R1) +fill_sstack_end: + + LDI #STACK_PATTERN, R0 + LDI #USTACK, R1 + LDI #sizeof(USTACK), R2 + CMP #0, R2 + BEQ:D fill_ustack_end + MOV R2, R13 + LDI #3, R12 + AND R2, R12 + BEQ:D fill_ustack2 + MOV R2, R3 + SUB R12, R3 + LDI #0x3, R4 + SUB R12, R4 + LSL #0x3, R4 + LDI #STACK_PATTERN, R5 + LSR R4, R5 + LDI #0x8, R4 +fill_ustack1: + ADD #-1, R13 + LSR R4, R5 + CMP R3, R13 + BHI:D fill_ustack1 + STB R5, @(R13, R1) + CMP #0, R3 + BEQ:D fill_ustack_end +fill_ustack2: + ADD #-4, R13 + BGT:D fill_ustack2 + ST R0, @(R13, R1) +fill_ustack_end: + ClearRCwatchdog +#endif + +;========================================================================================= +; Standard C startup +;========================================================================================= +;========================================================================================= +; 7.10 Clear data +;========================================================================================= +; clear DATA section +; According to ANSI, the DATA section must be cleared during start-up + LDI:8 #0, R0 + LDI #sizeof DATA &~0x3, R1 + LDI #DATA, R13 + CMP #0, R1 + BEQ data_clr1 +data_clr0: + ADD2 #-4, R1 + BNE:D data_clr0 + ST R0, @(R13, R1) +data_clr1: + LDI:8 #sizeof DATA & 0x3, R1 + LDI #DATA + (sizeof DATA & ~0x3), R13 + + CMP #0, R1 + BEQ data_clr_end +data_clr2: + ADD2 #-1, R1 + BNE:D data_clr2 + STB R0, @(R13, R1) +data_clr_end: + ClearRCwatchdog + +;========================================================================================= +; 7.11 Copy Init section from ROM to RAM +;========================================================================================= +; copy rom +; All initialised data's (e.g. int i=1) must be stored in ROM/FLASH area. +; (start value) +; The Application must copy the Section (Init) into the RAM area. + LDI #_RAM_INIT, R0 + LDI #_ROM_INIT, R1 + LDI #sizeof(INIT), R2 + CMP #0, R2 + BEQ:D copy_rom_end + LDI #3, R12 + AND R2, R12 + BEQ:D copy_rom2 + MOV R2, R13 + MOV R2, R3 + SUB R12, R3 +copy_rom1: + ADD #-1, R13 + LDUB @(R13, R1), R12 + CMP R3, R13 + BHI:D copy_rom1 + STB R12, @(R13, R0) + CMP #0, R3 + BEQ:D copy_rom_end +copy_rom2: + ADD #-4, R13 + LD @(R13, R1), R12 + BGT:D copy_rom2 + ST R12, @(R13, R0) +copy_rom_end: + ClearRCwatchdog + +;========================================================================================= +; 7.12 C library initialization +;========================================================================================= +#if CLIBINIT == ON + CALL32 __stream_init, r12 ; initialise library +#endif +;========================================================================================= +; 7.13 call C++ constructors +;========================================================================================= +#if CPLUSPLUS == ON + LDI #___call_dtors, r4 + CALL32 _atexit, r12 + + LDI #EXT_CTOR_DTOR, r8 + LDI #EXT_CTOR_DTOR + sizeof(EXT_CTOR_DTOR), r9 + CMP r9, r8 + BEQ L1 +L0: + LD @r8, r10 + CALL:D @r10 + ADD #4, r8 + CMP r9, r8 + BC L0 +L1: +#endif + +start_main: +;========================================================================================= +; 7.14 call main routine +;========================================================================================= + ClearRCwatchdog ; clear harware watchdog + LDI:8 #0, r4 ; Set the 1st parameter for main to 0. + CALL32:d _main, r12 + LDI:8 #0, r5 ; Set the 2nd parameter for main to 0. +#if CLIBINIT == ON + CALL32 _exit, r12 + __exit: +#endif + +#if CPLUSPLUS == ON + __abort: +#endif + +;========================================================================================= +; 7.15 Return from main function +;========================================================================================= +end: + BRA end + .end __start + diff --git a/20080212/Demo/MB91460_Softune/SRC/main.c b/20080212/Demo/MB91460_Softune/SRC/main.c new file mode 100644 index 000000000..0128f0b4e --- /dev/null +++ b/20080212/Demo/MB91460_Softune/SRC/main.c @@ -0,0 +1,596 @@ +/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ +/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ +/* ELIGIBILITY FOR ANY PURPOSES. */ +/* (C) Fujitsu Microelectronics Europe GmbH */ +/*------------------------------------------------------------------------ + MAIN.C + - description + - See README.TXT for project description and disclaimer. +-------------------------------------------------------------------------*/ + + +/* + * Creates all the demo application tasks, then starts the scheduler. The WEB + * documentation provides more details of the demo application tasks. + * + * Main.c also creates a task called "Check". This only executes every three + * seconds but has the highest priority so is guaranteed to get processor time. + * Its main function is to check that all the other tasks are still operational. + * Each task (other than the "flash" tasks) maintains a unique count that is + * incremented each time the task successfully completes its function. Should + * any error occur within such a task the count is permanently halted. The + * check task inspects the count of each task to ensure it has changed since + * the last time the check task executed. If all the count variables have + * changed all the tasks are still executing error free, and the check task + * toggles the onboard LED. Should any task contain an error at any time + * the LED toggle rate will change from 3 seconds to 500ms. + * + */ + + +/* Hardware specific includes. */ +#include "mb91467d.h" +#include "vectors.h" +#include "watchdog.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo app includes. */ +#include "flash.h" +#include "integer.h" +#include "comtest2.h" +#include "PollQ.h" +#include "semtest.h" +#include "BlockQ.h" +#include "dynamic.h" +#include "flop.h" +#include "GenQTest.h" +#include "QPeek.h" +#include "BlockTim.h" +#include "death.h" +#include "taskutility.h" +#include "partest.h" + +/* Demo task priorities. */ +#define mainWATCHDOG_TASK_PRIORITY ( tskIDLE_PRIORITY + 5 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) +#define mainUTILITY_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_BLOCK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainDEATH_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainGENERIC_QUEUE_PRIORITY ( tskIDLE_PRIORITY ) + +/* Baud rate used by the COM test tasks. */ +#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 19200 ) + +/* The frequency at which the 'Check' tasks executes. See the comments at the +top of the page. When the system is operating error free the 'Check' task +toggles an LED every three seconds. If an error is discovered in any task the +rate is increased to 500 milliseconds. [in this case the '*' characters on the +LCD represent LED's]*/ +#define mainNO_ERROR_CHECK_DELAY ( ( portTickType ) 3000 / portTICK_RATE_MS ) +#define mainERROR_CHECK_DELAY ( ( portTickType ) 500 / portTICK_RATE_MS ) + +/* The total number of LEDs available. */ +#define mainNO_CO_ROUTINE_LEDs ( 8 ) + +/* The first LED used by the comtest tasks. */ +#define mainCOM_TEST_LED ( 0x05 ) + +/* The LED used by the check task. */ +#define mainCHECK_TEST_LED ( 0x07 ) + +/* The number of interrupt levels to use. */ +#define mainINTERRUPT_LEVELS ( 31 ) + +/*---------------------------------------------------------------------------*/ + +/* + * The function that implements the Check task. See the comments at the head + * of the page for implementation details. + */ +static void vErrorChecks( void *pvParameters ); + +/* + * Called by the Check task. Returns pdPASS if all the other tasks are found + * to be operating without error - otherwise returns pdFAIL. + */ +static portSHORT prvCheckOtherTasksAreStillRunning( void ); + +/* + * Setup the microcontroller as used by this demo. + */ +static void prvSetupHardware( void ); + +/* + * Tasks that test the context switch mechanism by filling the CPU registers + * with known values then checking that each register contains the value + * expected. Each of the two tasks use different values, and as low priority + * tasks, get swapped in and out regularly. + */ +static void vFirstRegisterTestTask( void *pvParameters ); +static void vSecondRegisterTestTask( void *pvParameters ); + +/*---------------------------------------------------------------------------*/ + +/* The variable that is set to true should an error be found in one of the +register test tasks. */ +unsigned portLONG ulRegTestError = pdFALSE; + +/* Variables used to ensure the register check tasks are still executing. */ +static volatile unsigned portLONG ulRegTest1Counter = 0UL, ulRegTest2Counter = 0UL; + +/*---------------------------------------------------------------------------*/ + +/* Start all the demo application tasks, then start the scheduler. */ +void main(void) +{ + /* Initialise the hardware ready for the demo. */ + prvSetupHardware(); + + /* Start the standard demo application tasks. */ + vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED - 1 ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartBlockingQueueTasks ( mainQUEUE_BLOCK_PRIORITY ); + vStartDynamicPriorityTasks(); + vStartMathTasks( tskIDLE_PRIORITY ); + vStartGenericQueueTasks( mainGENERIC_QUEUE_PRIORITY ); + vStartQueuePeekTasks(); + vCreateBlockTimeTasks(); + + /* Start the 'Check' task which is defined in this file. */ + xTaskCreate( vErrorChecks, ( signed portCHAR * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + xTaskCreate( vFirstRegisterTestTask, ( signed portCHAR * ) "Reg1", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vSecondRegisterTestTask, ( signed portCHAR * ) "Reg2", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + + /* Start the task that write trace information to the UART. */ + vUtilityStartTraceTask( mainUTILITY_TASK_PRIORITY ); + + /* If we are going to service the watchdog from within a task, then create + the task here. */ + #if WATCHDOG == WTC_IN_TASK + vStartWatchdogTask( mainWATCHDOG_TASK_PRIORITY ); + #endif + + /* The suicide tasks must be started last as they record the number of other + tasks that exist within the system. The value is then used to ensure at run + time the number of tasks that exists is within expected bounds. */ + vCreateSuicidalTasks( mainDEATH_PRIORITY ); + + /* Now start the scheduler. Following this call the created tasks should + be executing. */ + vTaskStartScheduler( ); + + /* vTaskStartScheduler() will only return if an error occurs while the + idle task is being created. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void vErrorChecks( void *pvParameters ) +{ +portTickType xDelayPeriod = mainNO_ERROR_CHECK_DELAY, xLastExecutionTime; + + /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() + works correctly. */ + xLastExecutionTime = xTaskGetTickCount(); + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. */ + for( ;; ) + { + /* Wait until it is time to check again. The time we wait here depends + on whether an error has been detected or not. When an error is + detected the time is shortened resulting in a faster LED flash rate. */ + /* Perform this check every mainCHECK_DELAY milliseconds. */ + vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod ); + + /* See if the other tasks are all ok. */ + if( prvCheckOtherTasksAreStillRunning() != pdPASS ) + { + /* An error occurred in one of the tasks so shorten the delay + period - which has the effect of increasing the frequency of the + LED toggle. */ + xDelayPeriod = mainERROR_CHECK_DELAY; + } + + /* Flash! */ + vParTestToggleLED( mainCHECK_TEST_LED ); + } +} +/*-----------------------------------------------------------*/ + +static portSHORT prvCheckOtherTasksAreStillRunning( void ) +{ +portBASE_TYPE lReturn = pdPASS; +static unsigned portLONG ulLastRegTest1Counter = 0UL, ulLastRegTest2Counter = 0UL; + + /* The demo tasks maintain a count that increments every cycle of the task + provided that the task has never encountered an error. This function + checks the counts maintained by the tasks to ensure they are still being + incremented. A count remaining at the same value between calls therefore + indicates that an error has been detected. */ + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xAreMathsTaskStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xIsCreateTaskStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if ( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if ( xAreQueuePeekTasksStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + /* Have the register test tasks found any errors? */ + if( ulRegTestError != pdFALSE ) + { + lReturn = pdFAIL; + } + + /* Are the register test tasks still running? */ + if( ulLastRegTest1Counter == ulRegTest1Counter ) + { + lReturn = pdFAIL; + } + + if( ulLastRegTest2Counter == ulRegTest2Counter ) + { + lReturn = pdFAIL; + } + + ulLastRegTest1Counter = ulRegTest1Counter; + ulLastRegTest2Counter = ulRegTest2Counter; + + return lReturn; +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Allow all interrupt levels. */ + __set_il( mainINTERRUPT_LEVELS ); + + /* Initialise interrupts. */ + InitIrqLevels(); + + /* Initialise the ports used by the LEDs. */ + vParTestInitialise(); + + /* If we are going to use the watchdog, then initialise it now. */ + #if WATCHDOG != WTC_NONE + InitWatchdog(); + #endif +} +/*-----------------------------------------------------------*/ + +/* The below callback function is called from Delayed ISR if configUSE_IDLE_HOOK +is configured as 1. */ +#if configUSE_IDLE_HOOK == 1 + void vApplicationIdleHook( void ) + { + /* Are we using the idle task to kick the watchdog? */ + #if WATCHDOG == WTC_IN_IDLE + Kick_Watchdog(); + #endif + + #if configUSE_CO_ROUTINES == 1 + vCoRoutineSchedule(); + #endif + } +#endif +/*-----------------------------------------------------------*/ + +/* +The below callback function is called from Tick ISR if configUSE_TICK_HOOK +is configured as 1. */ +#if configUSE_TICK_HOOK == 1 + void vApplicationTickHook( void ) + { + #if WATCHDOG == WTC_IN_TICK + Kick_Watchdog(); + #endif + } +#endif +/*-----------------------------------------------------------*/ + +static void vFirstRegisterTestTask( void *pvParameters ) +{ +extern volatile unsigned portLONG ulCriticalNesting; + + /* Fills the registers with known values (different to the values + used in vSecondRegisterTestTask()), then checks that the registers still + all contain the expected value. This is done to test the context save + and restore mechanism as this task is swapped onto and off of the CPU. + + The critical nesting depth is also saved as part of the context so also + check this maintains an expected value. */ + ulCriticalNesting = 0x12345678; + + for( ;; ) + { + #pragma asm + ;Load known values into each register. + LDI #0x11111111, R0 + LDI #0x22222222, R1 + LDI #0x33333333, R2 + LDI #0x44444444, R3 + LDI #0x55555555, R4 + LDI #0x66666666, R5 + LDI #0x77777777, R6 + LDI #0x88888888, R7 + LDI #0x99999999, R8 + LDI #0xaaaaaaaa, R9 + LDI #0xbbbbbbbb, R10 + LDI #0xcccccccc, R11 + LDI #0xdddddddd, R12 + + ;Check each register still contains the expected value. + LDI #0x11111111, R13 + CMP R13, R0 + BNE First_Set_Error + NOP + + LDI #0x22222222, R13 + CMP R13, R1 + BNE First_Set_Error + NOP + + LDI #0x33333333, R13 + CMP R13, R2 + BNE First_Set_Error + NOP + + LDI #0x44444444, R13 + CMP R13, R3 + BNE First_Set_Error + NOP + + LDI #0x55555555, R13 + CMP R13, R4 + BNE First_Set_Error + NOP + + LDI #0x66666666, R13 + CMP R13, R5 + BNE First_Set_Error + NOP + + LDI #0x77777777, R13 + CMP R13, R6 + BNE First_Set_Error + NOP + + LDI #0x88888888, R13 + CMP R13, R7 + BNE First_Set_Error + NOP + + LDI #0x99999999, R13 + CMP R13, R8 + BNE First_Set_Error + NOP + + LDI #0xaaaaaaaa, R13 + CMP R13, R9 + BNE First_Set_Error + NOP + + LDI #0xbbbbbbbb, R13 + CMP R13, R10 + BNE First_Set_Error + NOP + + LDI #0xcccccccc, R13 + CMP R13, R11 + BNE First_Set_Error + NOP + + LDI #0xdddddddd, R13 + CMP R13, R12 + BNE First_Set_Error + NOP + + BRA First_Start_Next_Loop + NOP + + First_Set_Error: + + ; Latch that an error has occurred. + LDI #_ulRegTestError, R0 + LDI #0x00000001, R1 + ST R1, @R0 + + + First_Start_Next_Loop: + + + #pragma endasm + + ulRegTest1Counter++; + + if( ulCriticalNesting != 0x12345678 ) + { + ulRegTestError = pdTRUE; + } + } +} +/*-----------------------------------------------------------*/ + +static void vSecondRegisterTestTask( void *pvParameters ) +{ +extern volatile unsigned portLONG ulCriticalNesting; + + /* Fills the registers with known values (different to the values + used in vFirstRegisterTestTask()), then checks that the registers still + all contain the expected value. This is done to test the context save + and restore mechanism as this task is swapped onto and off of the CPU. + + The critical nesting depth is also saved as part of the context so also + check this maintains an expected value. */ + ulCriticalNesting = 0x87654321; + + for( ;; ) + { + #pragma asm + ;Load known values into each register. + LDI #0x11111111, R1 + LDI #0x22222222, R2 + LDI #0x33333333, R3 + LDI #0x44444444, R4 + LDI #0x55555555, R5 + LDI #0x66666666, R6 + LDI #0x77777777, R7 + LDI #0x88888888, R8 + LDI #0x99999999, R9 + LDI #0xaaaaaaaa, R10 + LDI #0xbbbbbbbb, R11 + LDI #0xcccccccc, R12 + LDI #0xdddddddd, R0 + + ;Check each register still contains the expected value. + LDI #0x11111111, R13 + CMP R13, R1 + BNE Second_Set_Error + NOP + + LDI #0x22222222, R13 + CMP R13, R2 + BNE Second_Set_Error + NOP + + LDI #0x33333333, R13 + CMP R13, R3 + BNE Second_Set_Error + NOP + + LDI #0x44444444, R13 + CMP R13, R4 + BNE Second_Set_Error + NOP + + LDI #0x55555555, R13 + CMP R13, R5 + BNE Second_Set_Error + NOP + + LDI #0x66666666, R13 + CMP R13, R6 + BNE Second_Set_Error + NOP + + LDI #0x77777777, R13 + CMP R13, R7 + BNE Second_Set_Error + NOP + + LDI #0x88888888, R13 + CMP R13, R8 + BNE Second_Set_Error + NOP + + LDI #0x99999999, R13 + CMP R13, R9 + BNE Second_Set_Error + NOP + + LDI #0xaaaaaaaa, R13 + CMP R13, R10 + BNE Second_Set_Error + NOP + + LDI #0xbbbbbbbb, R13 + CMP R13, R11 + BNE Second_Set_Error + NOP + + LDI #0xcccccccc, R13 + CMP R13, R12 + BNE Second_Set_Error + NOP + + LDI #0xdddddddd, R13 + CMP R13, R0 + BNE Second_Set_Error + NOP + + BRA Second_Start_Next_Loop + NOP + + Second_Set_Error: + + ; Latch that an error has occurred. + LDI #_ulRegTestError, R0 + LDI #0x00000001, R1 + ST R1, @R0 + + + Second_Start_Next_Loop: + + + #pragma endasm + + ulRegTest2Counter++; + + if( ulCriticalNesting != 0x87654321 ) + { + ulRegTestError = pdTRUE; + } + } +} +/*-----------------------------------------------------------*/ + + diff --git a/20080212/Demo/MB91460_Softune/SRC/mb91467d.asm b/20080212/Demo/MB91460_Softune/SRC/mb91467d.asm new file mode 100644 index 000000000..e7eb07a7b --- /dev/null +++ b/20080212/Demo/MB91460_Softune/SRC/mb91467d.asm @@ -0,0 +1,14 @@ +/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ +/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ +/* ELIGIBILITY FOR ANY PURPOSES. */ +/* (C) Fujitsu Microelectronics Europe GmbH */ +/*--------------------------------------------------------------------------- + mb91467d.asm + + + 1.00 UMa Initial Version +-----------------------------------------------------------------------------*/ + + +#define __IO_DEFINE +#include "mb91467d.h" diff --git a/20080212/Demo/MB91460_Softune/SRC/mb91467d.h b/20080212/Demo/MB91460_Softune/SRC/mb91467d.h new file mode 100644 index 000000000..7b2661f3b --- /dev/null +++ b/20080212/Demo/MB91460_Softune/SRC/mb91467d.h @@ -0,0 +1,24806 @@ +/* FR IO-MAP HEADER FILE */ +/* ===================== */ +/* CREATED BY IO-WIZARD V2.27 */ +/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ +/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ +/* ELIGIBILITY FOR ANY PURPOSES. */ +/* (C) Fujitsu Microelectronics Europe GmbH */ +/* */ +/* ************************************************************************* */ +/* Fujitsu Microelectronics Europe GmbH */ +/* http://emea.fujitsu.com/microelectronics */ +/* */ +/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ +/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ +/* ELIGIBILITY FOR ANY PURPOSES */ +/* (C) Fujitsu Microelectronics Europe GmbH */ +/* ************************************************************************* */ +/* ---------------------------------------------------------------------- */ +/* $Id: mb91467D.h,v 1.13 2007/08/08 10:56:26 mwilla Exp $ */ +/* ---------------------------------------------------------------------- */ +/* */ +/* Id: mb91467D.iow,v 1.1 2005/10/14 11:25:42 umarke Exp */ +/* - Initial Version based on mb91V460A, v1.1 */ +/* Id: mb91467D.iow,v 1.2 2005/10/14 09:47:18 umarke Exp */ +/* - Littel Endian IFxDTA_SWP_yz added */ +/* Id: mb91467D.iow,v 1.3 2005/11/18 06:55:29 umarke Exp */ +/* - No. of port register reduced to the no. of registers in MB91467D */ +/* - Registers added: FMWT2, FMCR */ +/* - Addapted Bit Names of Register FMCS */ +/* Id: mb91467D.iow,v 1.4 2005/11/18 06:55:29 umarke Exp */ +/* - OCS01 and OCS23 added */ +/* Id: mb91467D.iow,v 1.6 2006/01/13 08:58:51 umarke Exp */ +/* - Bitnames of CLKR changed */ +/* Id: mb91467D.iow,v 1.7 2006/01/26 15:42:05 umarke Exp */ +/* - REGSEL, BRPERx added */ +/* - REGCTR added */ +/* - LVSEL added */ +/* - Old Bitname of CLKR added */ +/* Id: mb91467D.iow,v 1.8 2006/02/27 10:31:28 umarke Exp */ +/* - BGR10x und BGR00x added */ +/* - PCNx, ITBAx, ITMKx, IDARx_D7 added */ +/* - SGCRH, SGCRL added */ +/* - Bit ACSR_MD added */ +/* - Bit CSCFG_PLLLOCK and CSCFG_RCSEL */ +/* - CUCR: Bits shifted to correct position */ +/* - CUTR1 & CUTR2 bits renamed to TDR14 instead of TR14 */ +/* - CMCR_RUN renamed to CMCR_FMODRUN and shifted */ +/* - Bitnames of OSCCx and OSCRx added */ +/* - FSVx, BSVx and FSCRx added */ +/* - RBSYNC, CBSYNCx */ +/* Id: mb91467D.iow,v 1.9 2006/02/27 11:56:23 umarke Exp */ +/* - changed Adress of REGSEL */ +/* $Id: mb91467D.h,v 1.13 2007/08/08 10:56:26 mwilla Exp $ */ +/* - Grouped CANPRE_CPCKS */ +/* - Bitdescription of HLRC added */ + +/* ASSEMBLER DEFINITIONS : */ + +#ifdef __IO_DEFINE +#define __IO_EXTERN +#else +#define __IO_EXTERN extern volatile +#endif +#ifdef __IO_DEFINE +#pragma asm + .GLOBAL _pdr00, _pdr01, _pdr02, _pdr03, _pdr04, _pdr05 + .GLOBAL _pdr06, _pdr07, _pdr08, _pdr09, _pdr10, _pdr13 + .GLOBAL _pdr14, _pdr15, _pdr16, _pdr17, _pdr18, _pdr19 + .GLOBAL _pdr20, _pdr22, _pdr23, _pdr24, _pdr25, _pdr26 + .GLOBAL _pdr27, _pdr29, _eirr0, _enir0, _elvr0, _eirr1 + .GLOBAL _enir1, _elvr1, _dicr, _hrcl, _rbsync, _scr02 + .GLOBAL _smr02, _ssr02, _rdr02, _tdr02, _escr02, _eccr02 + .GLOBAL _scr04, _smr04, _ssr04, _rdr04, _tdr04, _escr04 + .GLOBAL _eccr04, _fsr04, _fcr04, _scr05, _smr05, _ssr05 + .GLOBAL _rdr05, _tdr05, _escr05, _eccr05, _fsr05, _fcr05 + .GLOBAL _scr06, _smr06, _ssr06, _rdr06, _tdr06, _escr06 + .GLOBAL _eccr06, _fsr06, _fcr06, _scr07, _smr07, _ssr07 + .GLOBAL _rdr07, _tdr07, _escr07, _eccr07, _fsr07, _fcr07 + .GLOBAL _bgr02, _bgr102, _bgr002, _bgr04, _bgr104, _bgr004 + .GLOBAL _bgr05, _bgr105, _bgr005, _bgr06, _bgr106, _bgr006 + .GLOBAL _bgr07, _bgr107, _bgr007, _pwc20, _pwc10, _pws20 + .GLOBAL _pws10, _pwc21, _pwc11, _pws21, _pws11, _pwc22 + .GLOBAL _pwc12, _pws22, _pws12, _pwc23, _pwc13, _pws23 + .GLOBAL _pws13, _pwc24, _pwc14, _pws24, _pws14, _pwc25 + .GLOBAL _pwc15, _pws25, _pws15, _pwc0, _pwc1, _pwc2 + .GLOBAL _pwc3, _pwc4, _pwc5, _ibcr0, _ibsr0, _itba0 + .GLOBAL _itbah0, _itbal0, _itmk0, _itmkh0, _itmkl0, _ismk0 + .GLOBAL _isba0, _idar0, _iccr0, _gcn11, _gcn21, _gcn12 + .GLOBAL _gcn22, _ptmr04, _pcsr04, _pdut04, _pcn04, _pcnh04 + .GLOBAL _pcnl04, _ptmr05, _pcsr05, _pdut05, _pcn05, _pcnh05 + .GLOBAL _pcnl05, _ptmr06, _pcsr06, _pdut06, _pcn06, _pcnh06 + .GLOBAL _pcnl06, _ptmr07, _pcsr07, _pdut07, _pcn07, _pcnh07 + .GLOBAL _pcnl07, _ptmr08, _pcsr08, _pdut08, _pcn08, _pcnh08 + .GLOBAL _pcnl08, _ptmr09, _pcsr09, _pdut09, _pcn09, _pcnh09 + .GLOBAL _pcnl09, _ptmr10, _pcsr10, _pdut10, _pcn10, _pcnh10 + .GLOBAL _pcnl10, _ptmr11, _pcsr11, _pdut11, _pcn11, _pcnh11 + .GLOBAL _pcnl11, _p0tmcsr, _p0tmcsrh, _p0tmcsrl, _p1tmcsr, _p1tmcsrh + .GLOBAL _p1tmcsrl, _p0tmrlr, _p0tmr, _p1tmrlr, _p1tmr, _ics01 + .GLOBAL _ics23, _ipcp0, _ipcp1, _ipcp2, _ipcp3, _ocs01 + .GLOBAL _ocs23, _occp0, _occp1, _occp2, _occp3, _sgcr + .GLOBAL _sgcrh, _sgcrl, _sgfr, _sgar, _sgtr, _sgdr + .GLOBAL _aderh, _aderl, _ader, _adcs1, _adcs0, _adcs + .GLOBAL _adcr1, _adcr0, _adcr, _adct1, _adct0, _adct + .GLOBAL _adsch, _adech, _acsr0, _tmrlr0, _tmr0, _tmcsr0 + .GLOBAL _tmcsrh0, _tmcsrl0, _tmrlr1, _tmr1, _tmcsr1, _tmcsrh1 + .GLOBAL _tmcsrl1, _tmrlr2, _tmr2, _tmcsr2, _tmcsrh2, _tmcsrl2 + .GLOBAL _tmrlr3, _tmr3, _tmcsr3, _tmcsrh3, _tmcsrl3, _tmrlr4 + .GLOBAL _tmr4, _tmcsr4, _tmcsrh4, _tmcsrl4, _tmrlr5, _tmr5 + .GLOBAL _tmcsr5, _tmcsrh5, _tmcsrl5, _tmrlr6, _tmr6, _tmcsr6 + .GLOBAL _tmcsrh6, _tmcsrl6, _tmrlr7, _tmr7, _tmcsr7, _tmcsrh7 + .GLOBAL _tmcsrl7, _tcdt0, _tccs0, _tcdt1, _tccs1, _tcdt2 + .GLOBAL _tccs2, _tcdt3, _tccs3, _dmaca0, _dmacb0, _dmaca1 + .GLOBAL _dmacb1, _dmaca2, _dmacb2, _dmaca3, _dmacb3, _dmaca4 + .GLOBAL _dmacb4, _dmacr, _ics45, _ics67, _ipcp4, _ipcp5 + .GLOBAL _ipcp6, _ipcp7, _tcdt4, _tccs4, _tcdt5, _tccs5 + .GLOBAL _tcdt6, _tccs6, _tcdt7, _tccs7, _udrc10, _udrc1 + .GLOBAL _udrc0, _udcr10, _udcr1, _udcr0, _udcc0, _udcch0 + .GLOBAL _udccl0, _udcs0, _udcc1, _udcch1, _udccl1, _udcs1 + .GLOBAL _udrc32, _udrc3, _udrc2, _udcr32, _udcr3, _udcr2 + .GLOBAL _udcc2, _udcch2, _udccl2, _udcs2, _udcc3, _udcch3 + .GLOBAL _udccl3, _udcs3, _gcn13, _gcn23, _ptmr12, _pcsr12 + .GLOBAL _pdut12, _pcn12, _pcnh12, _pcnl12, _ptmr13, _pcsr13 + .GLOBAL _pdut13, _pcn13, _pcnh13, _pcnl13, _ptmr14, _pcsr14 + .GLOBAL _pdut14, _pcn14, _pcnh14, _pcnl14, _ptmr15, _pcsr15 + .GLOBAL _pdut15, _pcn15, _pcnh15, _pcnl15, _ibcr2, _ibsr2 + .GLOBAL _itba2, _itbah2, _itbal2, _itmk2, _itmkh2, _itmkl2 + .GLOBAL _ismk2, _isba2, _idar2, _iccr2, _ibcr3, _ibsr3 + .GLOBAL _itba3, _itbah3, _itbal3, _itmk3, _itmkh3, _itmkl3 + .GLOBAL _ismk3, _isba3, _idar3, _iccr3, _roms, _bsd0 + .GLOBAL _bsd1, _bsdc, _bsrr, _icr00, _icr01, _icr02 + .GLOBAL _icr03, _icr04, _icr05, _icr06, _icr07, _icr08 + .GLOBAL _icr09, _icr10, _icr11, _icr12, _icr13, _icr14 + .GLOBAL _icr15, _icr16, _icr17, _icr18, _icr19, _icr20 + .GLOBAL _icr21, _icr22, _icr23, _icr24, _icr25, _icr26 + .GLOBAL _icr27, _icr28, _icr29, _icr30, _icr31, _icr32 + .GLOBAL _icr33, _icr34, _icr35, _icr36, _icr37, _icr38 + .GLOBAL _icr39, _icr40, _icr41, _icr42, _icr43, _icr44 + .GLOBAL _icr45, _icr46, _icr47, _icr48, _icr49, _icr50 + .GLOBAL _icr51, _icr52, _icr53, _icr54, _icr55, _icr56 + .GLOBAL _icr57, _icr58, _icr59, _icr60, _icr61, _icr62 + .GLOBAL _icr63, _rsrr, _stcr, _tbcr, _ctbr, _clkr + .GLOBAL _wpr, _divr0, _divr1, _plldivm, _plldivn, _plldivg + .GLOBAL _pllmulg, _pllctrl, _oscc1, _oscs1, _oscc2, _oscs2 + .GLOBAL _porten, _wtcer, _wtcr, _wtbr, _wthr, _wtmr + .GLOBAL _wtsr, _csvtr, _csvcr, _cscfg, _cmcfg, _cucr + .GLOBAL _cutd, _cutr1, _cutr2, _cmpr, _cmcr, _cmt1 + .GLOBAL _cmt2, _canpre, _canckd, _lvsel, _lvdet, _hwwde + .GLOBAL _hwwd, _oscrh, _oscrl, _wpcrh, _wpcrl, _osccr + .GLOBAL _regsel, _regctr, _asr0, _acr0, _asr1, _acr1 + .GLOBAL _asr2, _acr2, _asr3, _acr3, _asr4, _acr4 + .GLOBAL _asr5, _acr5, _asr6, _acr6, _asr7, _acr7 + .GLOBAL _awr0, _awr1, _awr2, _awr3, _awr4, _awr5 + .GLOBAL _awr6, _awr7, _mcra, _mcrb, _iowr0, _iowr1 + .GLOBAL _iowr2, _iowr3, _cser, _cher, _tcr, _rcr + .GLOBAL _modr, _pdrd00, _pdrd01, _pdrd02, _pdrd03, _pdrd04 + .GLOBAL _pdrd05, _pdrd06, _pdrd07, _pdrd08, _pdrd09, _pdrd10 + .GLOBAL _pdrd13, _pdrd14, _pdrd15, _pdrd16, _pdrd17, _pdrd18 + .GLOBAL _pdrd19, _pdrd20, _pdrd22, _pdrd23, _pdrd24, _pdrd25 + .GLOBAL _pdrd26, _pdrd27, _pdrd29, _ddr00, _ddr01, _ddr02 + .GLOBAL _ddr03, _ddr04, _ddr05, _ddr06, _ddr07, _ddr08 + .GLOBAL _ddr09, _ddr10, _ddr13, _ddr14, _ddr15, _ddr16 + .GLOBAL _ddr17, _ddr18, _ddr19, _ddr20, _ddr22, _ddr23 + .GLOBAL _ddr24, _ddr25, _ddr26, _ddr27, _ddr29, _pfr00 + .GLOBAL _pfr01, _pfr02, _pfr03, _pfr04, _pfr05, _pfr06 + .GLOBAL _pfr07, _pfr08, _pfr09, _pfr10, _pfr13, _pfr14 + .GLOBAL _pfr15, _pfr16, _pfr17, _pfr18, _pfr19, _pfr20 + .GLOBAL _pfr22, _pfr23, _pfr24, _pfr25, _pfr26, _pfr27 + .GLOBAL _pfr29, _epfr10, _epfr13, _epfr14, _epfr15, _epfr16 + .GLOBAL _epfr18, _epfr19, _epfr20, _epfr26, _epfr27, _podr00 + .GLOBAL _podr01, _podr02, _podr03, _podr04, _podr05, _podr06 + .GLOBAL _podr07, _podr08, _podr09, _podr10, _podr13, _podr14 + .GLOBAL _podr15, _podr16, _podr17, _podr18, _podr19, _podr20 + .GLOBAL _podr22, _podr23, _podr24, _podr25, _podr26, _podr27 + .GLOBAL _podr29, _pilr00, _pilr01, _pilr02, _pilr03, _pilr04 + .GLOBAL _pilr05, _pilr06, _pilr07, _pilr08, _pilr09, _pilr10 + .GLOBAL _pilr13, _pilr14, _pilr15, _pilr16, _pilr17, _pilr18 + .GLOBAL _pilr19, _pilr20, _pilr22, _pilr23, _pilr24, _pilr25 + .GLOBAL _pilr26, _pilr27, _pilr29, _epilr00, _epilr01, _epilr02 + .GLOBAL _epilr03, _epilr04, _epilr05, _epilr06, _epilr07, _epilr08 + .GLOBAL _epilr09, _epilr10, _epilr13, _epilr14, _epilr15, _epilr16 + .GLOBAL _epilr17, _epilr18, _epilr19, _epilr20, _epilr22, _epilr23 + .GLOBAL _epilr24, _epilr25, _epilr26, _epilr27, _epilr29, _pper00 + .GLOBAL _pper01, _pper02, _pper03, _pper04, _pper05, _pper06 + .GLOBAL _pper07, _pper08, _pper09, _pper10, _pper13, _pper14 + .GLOBAL _pper15, _pper16, _pper17, _pper18, _pper19, _pper20 + .GLOBAL _pper22, _pper23, _pper24, _pper25, _pper26, _pper27 + .GLOBAL _pper29, _ppcr00, _ppcr01, _ppcr02, _ppcr03, _ppcr04 + .GLOBAL _ppcr05, _ppcr06, _ppcr07, _ppcr08, _ppcr09, _ppcr10 + .GLOBAL _ppcr13, _ppcr14, _ppcr15, _ppcr16, _ppcr17, _ppcr18 + .GLOBAL _ppcr19, _ppcr20, _ppcr22, _ppcr23, _ppcr24, _ppcr25 + .GLOBAL _ppcr26, _ppcr27, _ppcr29, _dmasa0, _dmada0, _dmasa1 + .GLOBAL _dmada1, _dmasa2, _dmada2, _dmasa3, _dmada3, _dmasa4 + .GLOBAL _dmada4, _fmcs, _fmcr, _fchcr, _fmwt, _fmwt2 + .GLOBAL _fmps, _fmac, _fcha0, _fcha1, _fscr0, _fscr1 + .GLOBAL _ctrlr0, _statr0, _errcnt0, _btr0, _intr0, _testr0 + .GLOBAL _brper0, _brpe0, _cbsync0, _if1creq0, _if1cmsk0, _if1msk120 + .GLOBAL _if1msk20, _if1msk10, _if1arb120, _if1arb20, _if1arb10, _if1mctr0 + .GLOBAL _if1dta120, _if1dta10, _if1dta20, _if1dtb120, _if1dtb10, _if1dtb20 + .GLOBAL _if1dta_swp120, _if1dta_swp20, _if1dta_swp10, _if1dtb_swp120, _if1dtb_swp20, _if1dtb_swp10 + .GLOBAL _if2creq0, _if2cmsk0, _if2msk120, _if2msk20, _if2msk10, _if2arb120 + .GLOBAL _if2arb20, _if2arb10, _if2mctr0, _if2dta120, _if2dta10, _if2dta20 + .GLOBAL _if2dtb120, _if2dtb10, _if2dtb20, _if2dta_swp120, _if2dta_swp20, _if2dta_swp10 + .GLOBAL _if2dtb_swp120, _if2dtb_swp20, _if2dtb_swp10, _treqr120, _treqr20, _treqr10 + .GLOBAL _newdt120, _newdt20, _newdt10, _intpnd120, _intpnd20, _intpnd10 + .GLOBAL _msgval120, _msgval20, _msgval10, _msgval340, _ctrlr1, _statr1 + .GLOBAL _errcnt1, _btr1, _intr1, _testr1, _brper1, _brpe1 + .GLOBAL _cbsync1, _if1creq1, _if1cmsk1, _if1msk121, _if1msk21, _if1msk11 + .GLOBAL _if1arb121, _if1arb21, _if1arb11, _if1mctr1, _if1dta121, _if1dta11 + .GLOBAL _if1dta21, _if1dtb121, _if1dtb11, _if1dtb21, _if1dta_swp121, _if1dta_swp21 + .GLOBAL _if1dta_swp11, _if1dtb_swp121, _if1dtb_swp21, _if1dtb_swp11, _if2creq1, _if2cmsk1 + .GLOBAL _if2msk121, _if2msk21, _if2msk11, _if2arb121, _if2arb21, _if2arb11 + .GLOBAL _if2mctr1, _if2dta121, _if2dta11, _if2dta21, _if2dtb121, _if2dtb11 + .GLOBAL _if2dtb21, _if2dta_swp121, _if2dta_swp21, _if2dta_swp11, _if2dtb_swp121, _if2dtb_swp21 + .GLOBAL _if2dtb_swp11, _treqr121, _treqr21, _treqr11, _newdt121, _newdt21 + .GLOBAL _newdt11, _intpnd121, _intpnd21, _intpnd11, _msgval121, _msgval21 + .GLOBAL _msgval11, _ctrlr2, _statr2, _errcnt2, _btr2, _intr2 + .GLOBAL _testr2, _brper2, _brpe2, _cbsync2, _if1creq2, _if1cmsk2 + .GLOBAL _if1msk122, _if1msk22, _if1msk12, _if1arb122, _if1arb22, _if1arb12 + .GLOBAL _if1mctr2, _if1dta122, _if1dta12, _if1dta22, _if1dtb122, _if1dtb12 + .GLOBAL _if1dtb22, _if1dta_swp122, _if1dta_swp22, _if1dta_swp12, _if1dtb_swp122, _if1dtb_swp22 + .GLOBAL _if1dtb_swp12, _if2creq2, _if2cmsk2, _if2msk122, _if2msk22, _if2msk12 + .GLOBAL _if2arb122, _if2arb22, _if2arb12, _if2mctr2, _if2dta122, _if2dta12 + .GLOBAL _if2dta22, _if2dtb122, _if2dtb12, _if2dtb22, _if2dta_swp122, _if2dta_swp22 + .GLOBAL _if2dta_swp12, _if2dtb_swp122, _if2dtb_swp22, _if2dtb_swp12, _treqr122, _treqr22 + .GLOBAL _treqr12, _newdt122, _newdt22, _newdt12, _intpnd122, _intpnd22 + .GLOBAL _intpnd12, _msgval122, _msgval22, _msgval12, _bctrl, _bstat + .GLOBAL _biac, _boac, _birq, _bcr0, _bcr1, _bcr2 + .GLOBAL _bcr3, _bcr4, _bcr5, _bcr6, _bcr7, _bad0 + .GLOBAL _bad1, _bad2, _bad3, _bad4, _bad5, _bad6 + .GLOBAL _bad7, _bad8, _bad9, _bad10, _bad11, _bad12 + .GLOBAL _bad13, _bad14, _bad15, _fsv1, _bsv1, _fsv2 + .GLOBAL _bsv2 + +_pdr00 .EQU 0x000000 +PDR00 .EQU 0x000000 /* Port Data Register */ +_pdr01 .EQU 0x000001 +PDR01 .EQU 0x000001 +_pdr02 .EQU 0x000002 +PDR02 .EQU 0x000002 +_pdr03 .EQU 0x000003 +PDR03 .EQU 0x000003 +_pdr04 .EQU 0x000004 +PDR04 .EQU 0x000004 +_pdr05 .EQU 0x000005 +PDR05 .EQU 0x000005 +_pdr06 .EQU 0x000006 +PDR06 .EQU 0x000006 +_pdr07 .EQU 0x000007 +PDR07 .EQU 0x000007 +_pdr08 .EQU 0x000008 +PDR08 .EQU 0x000008 +_pdr09 .EQU 0x000009 +PDR09 .EQU 0x000009 +_pdr10 .EQU 0x00000A +PDR10 .EQU 0x00000A +_pdr13 .EQU 0x00000D +PDR13 .EQU 0x00000D +_pdr14 .EQU 0x00000E +PDR14 .EQU 0x00000E +_pdr15 .EQU 0x00000F +PDR15 .EQU 0x00000F +_pdr16 .EQU 0x000010 +PDR16 .EQU 0x000010 +_pdr17 .EQU 0x000011 +PDR17 .EQU 0x000011 +_pdr18 .EQU 0x000012 +PDR18 .EQU 0x000012 +_pdr19 .EQU 0x000013 +PDR19 .EQU 0x000013 +_pdr20 .EQU 0x000014 +PDR20 .EQU 0x000014 +_pdr22 .EQU 0x000016 +PDR22 .EQU 0x000016 +_pdr23 .EQU 0x000017 +PDR23 .EQU 0x000017 +_pdr24 .EQU 0x000018 +PDR24 .EQU 0x000018 +_pdr25 .EQU 0x000019 +PDR25 .EQU 0x000019 +_pdr26 .EQU 0x00001A +PDR26 .EQU 0x00001A +_pdr27 .EQU 0x00001B +PDR27 .EQU 0x00001B +_pdr29 .EQU 0x00001D +PDR29 .EQU 0x00001D +_eirr0 .EQU 0x000030 +EIRR0 .EQU 0x000030 /* External Interrupt 0-7 */ +_enir0 .EQU 0x000031 +ENIR0 .EQU 0x000031 +_elvr0 .EQU 0x000032 +ELVR0 .EQU 0x000032 +_eirr1 .EQU 0x000034 +EIRR1 .EQU 0x000034 /* External Interrupt 8-15 */ +_enir1 .EQU 0x000035 +ENIR1 .EQU 0x000035 +_elvr1 .EQU 0x000036 +ELVR1 .EQU 0x000036 +_dicr .EQU 0x000038 +DICR .EQU 0x000038 /* DLYI/I-unit */ +_hrcl .EQU 0x000039 +HRCL .EQU 0x000039 +_rbsync .EQU 0x00003A +RBSYNC .EQU 0x00003A /* R-Bus Sync */ +_scr02 .EQU 0x000050 +SCR02 .EQU 0x000050 /* USART (LIN) 2 */ +_smr02 .EQU 0x000051 +SMR02 .EQU 0x000051 +_ssr02 .EQU 0x000052 +SSR02 .EQU 0x000052 +_rdr02 .EQU 0x000053 +RDR02 .EQU 0x000053 +_tdr02 .EQU 0x000053 +TDR02 .EQU 0x000053 +_escr02 .EQU 0x000054 +ESCR02 .EQU 0x000054 +_eccr02 .EQU 0x000055 +ECCR02 .EQU 0x000055 +_scr04 .EQU 0x000060 +SCR04 .EQU 0x000060 /* USART (LIN) 4 with FIFO */ +_smr04 .EQU 0x000061 +SMR04 .EQU 0x000061 +_ssr04 .EQU 0x000062 +SSR04 .EQU 0x000062 +_rdr04 .EQU 0x000063 +RDR04 .EQU 0x000063 +_tdr04 .EQU 0x000063 +TDR04 .EQU 0x000063 +_escr04 .EQU 0x000064 +ESCR04 .EQU 0x000064 +_eccr04 .EQU 0x000065 +ECCR04 .EQU 0x000065 +_fsr04 .EQU 0x000066 +FSR04 .EQU 0x000066 +_fcr04 .EQU 0x000067 +FCR04 .EQU 0x000067 +_scr05 .EQU 0x000068 +SCR05 .EQU 0x000068 /* USART (LIN) 5 with FIFO */ +_smr05 .EQU 0x000069 +SMR05 .EQU 0x000069 +_ssr05 .EQU 0x00006A +SSR05 .EQU 0x00006A +_rdr05 .EQU 0x00006B +RDR05 .EQU 0x00006B +_tdr05 .EQU 0x00006B +TDR05 .EQU 0x00006B +_escr05 .EQU 0x00006C +ESCR05 .EQU 0x00006C +_eccr05 .EQU 0x00006D +ECCR05 .EQU 0x00006D +_fsr05 .EQU 0x00006E +FSR05 .EQU 0x00006E +_fcr05 .EQU 0x00006F +FCR05 .EQU 0x00006F +_scr06 .EQU 0x000070 +SCR06 .EQU 0x000070 /* USART (LIN) 6 with FIFO */ +_smr06 .EQU 0x000071 +SMR06 .EQU 0x000071 +_ssr06 .EQU 0x000072 +SSR06 .EQU 0x000072 +_rdr06 .EQU 0x000073 +RDR06 .EQU 0x000073 +_tdr06 .EQU 0x000073 +TDR06 .EQU 0x000073 +_escr06 .EQU 0x000074 +ESCR06 .EQU 0x000074 +_eccr06 .EQU 0x000075 +ECCR06 .EQU 0x000075 +_fsr06 .EQU 0x000076 +FSR06 .EQU 0x000076 +_fcr06 .EQU 0x000077 +FCR06 .EQU 0x000077 +_scr07 .EQU 0x000078 +SCR07 .EQU 0x000078 /* USART (LIN) 7 with FIFO */ +_smr07 .EQU 0x000079 +SMR07 .EQU 0x000079 +_ssr07 .EQU 0x00007A +SSR07 .EQU 0x00007A +_rdr07 .EQU 0x00007B +RDR07 .EQU 0x00007B +_tdr07 .EQU 0x00007B +TDR07 .EQU 0x00007B +_escr07 .EQU 0x00007C +ESCR07 .EQU 0x00007C +_eccr07 .EQU 0x00007D +ECCR07 .EQU 0x00007D +_fsr07 .EQU 0x00007E +FSR07 .EQU 0x00007E +_fcr07 .EQU 0x00007F +FCR07 .EQU 0x00007F +_bgr02 .EQU 0x000084 +BGR02 .EQU 0x000084 /* Bauderate Generator USART (LIN) 2,4-7 */ +_bgr102 .EQU 0x000084 +BGR102 .EQU 0x000084 +_bgr002 .EQU 0x000085 +BGR002 .EQU 0x000085 +_bgr04 .EQU 0x000088 +BGR04 .EQU 0x000088 +_bgr104 .EQU 0x000088 +BGR104 .EQU 0x000088 +_bgr004 .EQU 0x000089 +BGR004 .EQU 0x000089 +_bgr05 .EQU 0x00008A +BGR05 .EQU 0x00008A +_bgr105 .EQU 0x00008A +BGR105 .EQU 0x00008A +_bgr005 .EQU 0x00008B +BGR005 .EQU 0x00008B +_bgr06 .EQU 0x00008C +BGR06 .EQU 0x00008C +_bgr106 .EQU 0x00008C +BGR106 .EQU 0x00008C +_bgr006 .EQU 0x00008D +BGR006 .EQU 0x00008D +_bgr07 .EQU 0x00008E +BGR07 .EQU 0x00008E +_bgr107 .EQU 0x00008E +BGR107 .EQU 0x00008E +_bgr007 .EQU 0x00008F +BGR007 .EQU 0x00008F +_pwc20 .EQU 0x000090 +PWC20 .EQU 0x000090 /* Stepper Motor 0 */ +_pwc10 .EQU 0x000092 +PWC10 .EQU 0x000092 +_pws20 .EQU 0x000096 +PWS20 .EQU 0x000096 +_pws10 .EQU 0x000097 +PWS10 .EQU 0x000097 +_pwc21 .EQU 0x000098 +PWC21 .EQU 0x000098 /* Stepper Motor 1 */ +_pwc11 .EQU 0x00009A +PWC11 .EQU 0x00009A +_pws21 .EQU 0x00009E +PWS21 .EQU 0x00009E +_pws11 .EQU 0x00009F +PWS11 .EQU 0x00009F +_pwc22 .EQU 0x0000A0 +PWC22 .EQU 0x0000A0 /* Stepper Motor 2 */ +_pwc12 .EQU 0x0000A2 +PWC12 .EQU 0x0000A2 +_pws22 .EQU 0x0000A6 +PWS22 .EQU 0x0000A6 +_pws12 .EQU 0x0000A7 +PWS12 .EQU 0x0000A7 +_pwc23 .EQU 0x0000A8 +PWC23 .EQU 0x0000A8 /* Stepper Motor 3 */ +_pwc13 .EQU 0x0000AA +PWC13 .EQU 0x0000AA +_pws23 .EQU 0x0000AE +PWS23 .EQU 0x0000AE +_pws13 .EQU 0x0000AF +PWS13 .EQU 0x0000AF +_pwc24 .EQU 0x0000B0 +PWC24 .EQU 0x0000B0 /* Stepper Motor 4 */ +_pwc14 .EQU 0x0000B2 +PWC14 .EQU 0x0000B2 +_pws24 .EQU 0x0000B6 +PWS24 .EQU 0x0000B6 +_pws14 .EQU 0x0000B7 +PWS14 .EQU 0x0000B7 +_pwc25 .EQU 0x0000B8 +PWC25 .EQU 0x0000B8 /* Stepper Motor 5 */ +_pwc15 .EQU 0x0000BA +PWC15 .EQU 0x0000BA +_pws25 .EQU 0x0000BE +PWS25 .EQU 0x0000BE +_pws15 .EQU 0x0000BF +PWS15 .EQU 0x0000BF +_pwc0 .EQU 0x0000C1 +PWC0 .EQU 0x0000C1 /* Stepper Motor Control 0-5 */ +_pwc1 .EQU 0x0000C3 +PWC1 .EQU 0x0000C3 +_pwc2 .EQU 0x0000C5 +PWC2 .EQU 0x0000C5 +_pwc3 .EQU 0x0000C7 +PWC3 .EQU 0x0000C7 +_pwc4 .EQU 0x0000C9 +PWC4 .EQU 0x0000C9 +_pwc5 .EQU 0x0000CB +PWC5 .EQU 0x0000CB +_ibcr0 .EQU 0x0000D0 +IBCR0 .EQU 0x0000D0 /* I2C 0 */ +_ibsr0 .EQU 0x0000D1 +IBSR0 .EQU 0x0000D1 +_itba0 .EQU 0x0000D2 +ITBA0 .EQU 0x0000D2 +_itbah0 .EQU 0x0000D2 +ITBAH0 .EQU 0x0000D2 +_itbal0 .EQU 0x0000D3 +ITBAL0 .EQU 0x0000D3 +_itmk0 .EQU 0x0000D4 +ITMK0 .EQU 0x0000D4 +_itmkh0 .EQU 0x0000D4 +ITMKH0 .EQU 0x0000D4 +_itmkl0 .EQU 0x0000D5 +ITMKL0 .EQU 0x0000D5 +_ismk0 .EQU 0x0000D6 +ISMK0 .EQU 0x0000D6 +_isba0 .EQU 0x0000D7 +ISBA0 .EQU 0x0000D7 +_idar0 .EQU 0x0000D9 +IDAR0 .EQU 0x0000D9 +_iccr0 .EQU 0x0000DA +ICCR0 .EQU 0x0000DA +_gcn11 .EQU 0x000104 +GCN11 .EQU 0x000104 /* PPG Control 4-7 */ +_gcn21 .EQU 0x000107 +GCN21 .EQU 0x000107 +_gcn12 .EQU 0x000108 +GCN12 .EQU 0x000108 /* PPG Control 8-11 */ +_gcn22 .EQU 0x00010B +GCN22 .EQU 0x00010B +_ptmr04 .EQU 0x000130 +PTMR04 .EQU 0x000130 /* PPG 4 */ +_pcsr04 .EQU 0x000132 +PCSR04 .EQU 0x000132 +_pdut04 .EQU 0x000134 +PDUT04 .EQU 0x000134 +_pcn04 .EQU 0x000136 +PCN04 .EQU 0x000136 +_pcnh04 .EQU 0x000136 +PCNH04 .EQU 0x000136 +_pcnl04 .EQU 0x000137 +PCNL04 .EQU 0x000137 +_ptmr05 .EQU 0x000138 +PTMR05 .EQU 0x000138 /* PPG 5 */ +_pcsr05 .EQU 0x00013A +PCSR05 .EQU 0x00013A +_pdut05 .EQU 0x00013C +PDUT05 .EQU 0x00013C +_pcn05 .EQU 0x00013E +PCN05 .EQU 0x00013E +_pcnh05 .EQU 0x00013E +PCNH05 .EQU 0x00013E +_pcnl05 .EQU 0x00013F +PCNL05 .EQU 0x00013F +_ptmr06 .EQU 0x000140 +PTMR06 .EQU 0x000140 /* PPG 6 */ +_pcsr06 .EQU 0x000142 +PCSR06 .EQU 0x000142 +_pdut06 .EQU 0x000144 +PDUT06 .EQU 0x000144 +_pcn06 .EQU 0x000146 +PCN06 .EQU 0x000146 +_pcnh06 .EQU 0x000146 +PCNH06 .EQU 0x000146 +_pcnl06 .EQU 0x000147 +PCNL06 .EQU 0x000147 +_ptmr07 .EQU 0x000148 +PTMR07 .EQU 0x000148 /* PPG 7 */ +_pcsr07 .EQU 0x00014A +PCSR07 .EQU 0x00014A +_pdut07 .EQU 0x00014C +PDUT07 .EQU 0x00014C +_pcn07 .EQU 0x00014E +PCN07 .EQU 0x00014E +_pcnh07 .EQU 0x00014E +PCNH07 .EQU 0x00014E +_pcnl07 .EQU 0x00014F +PCNL07 .EQU 0x00014F +_ptmr08 .EQU 0x000150 +PTMR08 .EQU 0x000150 /* PPG 8 */ +_pcsr08 .EQU 0x000152 +PCSR08 .EQU 0x000152 +_pdut08 .EQU 0x000154 +PDUT08 .EQU 0x000154 +_pcn08 .EQU 0x000156 +PCN08 .EQU 0x000156 +_pcnh08 .EQU 0x000156 +PCNH08 .EQU 0x000156 +_pcnl08 .EQU 0x000157 +PCNL08 .EQU 0x000157 +_ptmr09 .EQU 0x000158 +PTMR09 .EQU 0x000158 /* PPG 9 */ +_pcsr09 .EQU 0x00015A +PCSR09 .EQU 0x00015A +_pdut09 .EQU 0x00015C +PDUT09 .EQU 0x00015C +_pcn09 .EQU 0x00015E +PCN09 .EQU 0x00015E +_pcnh09 .EQU 0x00015E +PCNH09 .EQU 0x00015E +_pcnl09 .EQU 0x00015F +PCNL09 .EQU 0x00015F +_ptmr10 .EQU 0x000160 +PTMR10 .EQU 0x000160 /* PPG 10 */ +_pcsr10 .EQU 0x000162 +PCSR10 .EQU 0x000162 +_pdut10 .EQU 0x000164 +PDUT10 .EQU 0x000164 +_pcn10 .EQU 0x000166 +PCN10 .EQU 0x000166 +_pcnh10 .EQU 0x000166 +PCNH10 .EQU 0x000166 +_pcnl10 .EQU 0x000167 +PCNL10 .EQU 0x000167 +_ptmr11 .EQU 0x000168 +PTMR11 .EQU 0x000168 /* PPG 11 */ +_pcsr11 .EQU 0x00016A +PCSR11 .EQU 0x00016A +_pdut11 .EQU 0x00016C +PDUT11 .EQU 0x00016C +_pcn11 .EQU 0x00016E +PCN11 .EQU 0x00016E +_pcnh11 .EQU 0x00016E +PCNH11 .EQU 0x00016E +_pcnl11 .EQU 0x00016F +PCNL11 .EQU 0x00016F +_p0tmcsr .EQU 0x000170 +P0TMCSR .EQU 0x000170 /* Pulse Frequency Modulator (PFM) */ +_p0tmcsrh .EQU 0x000170 +P0TMCSRH .EQU 0x000170 +_p0tmcsrl .EQU 0x000171 +P0TMCSRL .EQU 0x000171 +_p1tmcsr .EQU 0x000172 +P1TMCSR .EQU 0x000172 +_p1tmcsrh .EQU 0x000172 +P1TMCSRH .EQU 0x000172 +_p1tmcsrl .EQU 0x000173 +P1TMCSRL .EQU 0x000173 +_p0tmrlr .EQU 0x000174 +P0TMRLR .EQU 0x000174 +_p0tmr .EQU 0x000176 +P0TMR .EQU 0x000176 +_p1tmrlr .EQU 0x000178 +P1TMRLR .EQU 0x000178 +_p1tmr .EQU 0x00017A +P1TMR .EQU 0x00017A +_ics01 .EQU 0x000181 +ICS01 .EQU 0x000181 /* Input Capture 0-3 */ +_ics23 .EQU 0x000183 +ICS23 .EQU 0x000183 +_ipcp0 .EQU 0x000184 +IPCP0 .EQU 0x000184 +_ipcp1 .EQU 0x000186 +IPCP1 .EQU 0x000186 +_ipcp2 .EQU 0x000188 +IPCP2 .EQU 0x000188 +_ipcp3 .EQU 0x00018A +IPCP3 .EQU 0x00018A +_ocs01 .EQU 0x00018C +OCS01 .EQU 0x00018C /* Output Compare 0-3 */ +_ocs23 .EQU 0x00018E +OCS23 .EQU 0x00018E +_occp0 .EQU 0x000190 +OCCP0 .EQU 0x000190 +_occp1 .EQU 0x000192 +OCCP1 .EQU 0x000192 +_occp2 .EQU 0x000194 +OCCP2 .EQU 0x000194 +_occp3 .EQU 0x000196 +OCCP3 .EQU 0x000196 +_sgcr .EQU 0x000198 +SGCR .EQU 0x000198 /* Sound Generator */ +_sgcrh .EQU 0x000198 +SGCRH .EQU 0x000198 +_sgcrl .EQU 0x000199 +SGCRL .EQU 0x000199 +_sgfr .EQU 0x00019A +SGFR .EQU 0x00019A +_sgar .EQU 0x00019C +SGAR .EQU 0x00019C +_sgtr .EQU 0x00019E +SGTR .EQU 0x00019E +_sgdr .EQU 0x00019F +SGDR .EQU 0x00019F +_aderh .EQU 0x0001A0 +ADERH .EQU 0x0001A0 /* ADC */ +_aderl .EQU 0x0001A2 +ADERL .EQU 0x0001A2 +_ader .EQU 0x0001A0 +ADER .EQU 0x0001A0 +_adcs1 .EQU 0x0001A4 +ADCS1 .EQU 0x0001A4 +_adcs0 .EQU 0x0001A5 +ADCS0 .EQU 0x0001A5 +_adcs .EQU 0x0001A4 +ADCS .EQU 0x0001A4 +_adcr1 .EQU 0x0001A6 +ADCR1 .EQU 0x0001A6 +_adcr0 .EQU 0x0001A7 +ADCR0 .EQU 0x0001A7 +_adcr .EQU 0x0001A6 +ADCR .EQU 0x0001A6 +_adct1 .EQU 0x0001A8 +ADCT1 .EQU 0x0001A8 +_adct0 .EQU 0x0001A9 +ADCT0 .EQU 0x0001A9 +_adct .EQU 0x0001A8 +ADCT .EQU 0x0001A8 +_adsch .EQU 0x0001AA +ADSCH .EQU 0x0001AA +_adech .EQU 0x0001AB +ADECH .EQU 0x0001AB +_acsr0 .EQU 0x0001AD +ACSR0 .EQU 0x0001AD /* Alarm Comparator 0-1 */ +_tmrlr0 .EQU 0x0001B0 +TMRLR0 .EQU 0x0001B0 /* Reload Timer 0 */ +_tmr0 .EQU 0x0001B2 +TMR0 .EQU 0x0001B2 +_tmcsr0 .EQU 0x0001B6 +TMCSR0 .EQU 0x0001B6 +_tmcsrh0 .EQU 0x0001B6 +TMCSRH0 .EQU 0x0001B6 +_tmcsrl0 .EQU 0x0001B7 +TMCSRL0 .EQU 0x0001B7 +_tmrlr1 .EQU 0x0001B8 +TMRLR1 .EQU 0x0001B8 /* Reload Timer 1 */ +_tmr1 .EQU 0x0001BA +TMR1 .EQU 0x0001BA +_tmcsr1 .EQU 0x0001BE +TMCSR1 .EQU 0x0001BE +_tmcsrh1 .EQU 0x0001BE +TMCSRH1 .EQU 0x0001BE +_tmcsrl1 .EQU 0x0001BF +TMCSRL1 .EQU 0x0001BF +_tmrlr2 .EQU 0x0001C0 +TMRLR2 .EQU 0x0001C0 /* Reload Timer 2 */ +_tmr2 .EQU 0x0001C2 +TMR2 .EQU 0x0001C2 +_tmcsr2 .EQU 0x0001C6 +TMCSR2 .EQU 0x0001C6 +_tmcsrh2 .EQU 0x0001C6 +TMCSRH2 .EQU 0x0001C6 +_tmcsrl2 .EQU 0x0001C7 +TMCSRL2 .EQU 0x0001C7 +_tmrlr3 .EQU 0x0001C8 +TMRLR3 .EQU 0x0001C8 /* Reload Timer 3 */ +_tmr3 .EQU 0x0001CA +TMR3 .EQU 0x0001CA +_tmcsr3 .EQU 0x0001CE +TMCSR3 .EQU 0x0001CE +_tmcsrh3 .EQU 0x0001CE +TMCSRH3 .EQU 0x0001CE +_tmcsrl3 .EQU 0x0001CF +TMCSRL3 .EQU 0x0001CF +_tmrlr4 .EQU 0x0001D0 +TMRLR4 .EQU 0x0001D0 /* Reload Timer 4 */ +_tmr4 .EQU 0x0001D2 +TMR4 .EQU 0x0001D2 +_tmcsr4 .EQU 0x0001D6 +TMCSR4 .EQU 0x0001D6 +_tmcsrh4 .EQU 0x0001D6 +TMCSRH4 .EQU 0x0001D6 +_tmcsrl4 .EQU 0x0001D7 +TMCSRL4 .EQU 0x0001D7 +_tmrlr5 .EQU 0x0001D8 +TMRLR5 .EQU 0x0001D8 /* Reload Timer 5 */ +_tmr5 .EQU 0x0001DA +TMR5 .EQU 0x0001DA +_tmcsr5 .EQU 0x0001DE +TMCSR5 .EQU 0x0001DE +_tmcsrh5 .EQU 0x0001DE +TMCSRH5 .EQU 0x0001DE +_tmcsrl5 .EQU 0x0001DF +TMCSRL5 .EQU 0x0001DF +_tmrlr6 .EQU 0x0001E0 +TMRLR6 .EQU 0x0001E0 /* Reload Timer 6 */ +_tmr6 .EQU 0x0001E2 +TMR6 .EQU 0x0001E2 +_tmcsr6 .EQU 0x0001E6 +TMCSR6 .EQU 0x0001E6 +_tmcsrh6 .EQU 0x0001E6 +TMCSRH6 .EQU 0x0001E6 +_tmcsrl6 .EQU 0x0001E7 +TMCSRL6 .EQU 0x0001E7 +_tmrlr7 .EQU 0x0001E8 +TMRLR7 .EQU 0x0001E8 /* Reload Timer 7 */ +_tmr7 .EQU 0x0001EA +TMR7 .EQU 0x0001EA +_tmcsr7 .EQU 0x0001EE +TMCSR7 .EQU 0x0001EE +_tmcsrh7 .EQU 0x0001EE +TMCSRH7 .EQU 0x0001EE +_tmcsrl7 .EQU 0x0001EF +TMCSRL7 .EQU 0x0001EF +_tcdt0 .EQU 0x0001F0 +TCDT0 .EQU 0x0001F0 /* Free Running Timer0 */ +_tccs0 .EQU 0x0001F3 +TCCS0 .EQU 0x0001F3 +_tcdt1 .EQU 0x0001F4 +TCDT1 .EQU 0x0001F4 /* Free Running Timer1 */ +_tccs1 .EQU 0x0001F7 +TCCS1 .EQU 0x0001F7 +_tcdt2 .EQU 0x0001F8 +TCDT2 .EQU 0x0001F8 /* Free Running Timer2 */ +_tccs2 .EQU 0x0001FB +TCCS2 .EQU 0x0001FB +_tcdt3 .EQU 0x0001FC +TCDT3 .EQU 0x0001FC /* Free Running Timer3 */ +_tccs3 .EQU 0x0001FF +TCCS3 .EQU 0x0001FF +_dmaca0 .EQU 0x000200 +DMACA0 .EQU 0x000200 /* DMAC */ +_dmacb0 .EQU 0x000204 +DMACB0 .EQU 0x000204 +_dmaca1 .EQU 0x000208 +DMACA1 .EQU 0x000208 +_dmacb1 .EQU 0x00020C +DMACB1 .EQU 0x00020C +_dmaca2 .EQU 0x000210 +DMACA2 .EQU 0x000210 +_dmacb2 .EQU 0x000214 +DMACB2 .EQU 0x000214 +_dmaca3 .EQU 0x000218 +DMACA3 .EQU 0x000218 +_dmacb3 .EQU 0x00021C +DMACB3 .EQU 0x00021C +_dmaca4 .EQU 0x000220 +DMACA4 .EQU 0x000220 +_dmacb4 .EQU 0x000224 +DMACB4 .EQU 0x000224 +_dmacr .EQU 0x000240 +DMACR .EQU 0x000240 +_ics45 .EQU 0x0002D1 +ICS45 .EQU 0x0002D1 /* Input Capture 4-7 */ +_ics67 .EQU 0x0002D3 +ICS67 .EQU 0x0002D3 +_ipcp4 .EQU 0x0002D4 +IPCP4 .EQU 0x0002D4 +_ipcp5 .EQU 0x0002D6 +IPCP5 .EQU 0x0002D6 +_ipcp6 .EQU 0x0002D8 +IPCP6 .EQU 0x0002D8 +_ipcp7 .EQU 0x0002DA +IPCP7 .EQU 0x0002DA +_tcdt4 .EQU 0x0002F0 +TCDT4 .EQU 0x0002F0 /* Free Running Timer4 */ +_tccs4 .EQU 0x0002F3 +TCCS4 .EQU 0x0002F3 +_tcdt5 .EQU 0x0002F4 +TCDT5 .EQU 0x0002F4 /* Free Running Timer5 */ +_tccs5 .EQU 0x0002F7 +TCCS5 .EQU 0x0002F7 +_tcdt6 .EQU 0x0002F8 +TCDT6 .EQU 0x0002F8 /* Free Running Timer6 */ +_tccs6 .EQU 0x0002FB +TCCS6 .EQU 0x0002FB +_tcdt7 .EQU 0x0002FC +TCDT7 .EQU 0x0002FC /* Free Running Timer7 */ +_tccs7 .EQU 0x0002FF +TCCS7 .EQU 0x0002FF +_udrc10 .EQU 0x000300 +UDRC10 .EQU 0x000300 /* Up/Down Counter 0-1 */ +_udrc1 .EQU 0x000300 +UDRC1 .EQU 0x000300 +_udrc0 .EQU 0x000301 +UDRC0 .EQU 0x000301 +_udcr10 .EQU 0x000302 +UDCR10 .EQU 0x000302 +_udcr1 .EQU 0x000302 +UDCR1 .EQU 0x000302 +_udcr0 .EQU 0x000303 +UDCR0 .EQU 0x000303 +_udcc0 .EQU 0x000304 +UDCC0 .EQU 0x000304 +_udcch0 .EQU 0x000304 +UDCCH0 .EQU 0x000304 +_udccl0 .EQU 0x000305 +UDCCL0 .EQU 0x000305 +_udcs0 .EQU 0x000307 +UDCS0 .EQU 0x000307 +_udcc1 .EQU 0x000308 +UDCC1 .EQU 0x000308 +_udcch1 .EQU 0x000308 +UDCCH1 .EQU 0x000308 +_udccl1 .EQU 0x000309 +UDCCL1 .EQU 0x000309 +_udcs1 .EQU 0x00030B +UDCS1 .EQU 0x00030B +_udrc32 .EQU 0x000310 +UDRC32 .EQU 0x000310 /* Up/Down Counter 2-3 */ +_udrc3 .EQU 0x000310 +UDRC3 .EQU 0x000310 +_udrc2 .EQU 0x000311 +UDRC2 .EQU 0x000311 +_udcr32 .EQU 0x000312 +UDCR32 .EQU 0x000312 +_udcr3 .EQU 0x000312 +UDCR3 .EQU 0x000312 +_udcr2 .EQU 0x000313 +UDCR2 .EQU 0x000313 +_udcc2 .EQU 0x000314 +UDCC2 .EQU 0x000314 +_udcch2 .EQU 0x000314 +UDCCH2 .EQU 0x000314 +_udccl2 .EQU 0x000315 +UDCCL2 .EQU 0x000315 +_udcs2 .EQU 0x000317 +UDCS2 .EQU 0x000317 +_udcc3 .EQU 0x000318 +UDCC3 .EQU 0x000318 +_udcch3 .EQU 0x000318 +UDCCH3 .EQU 0x000318 +_udccl3 .EQU 0x000319 +UDCCL3 .EQU 0x000319 +_udcs3 .EQU 0x00031B +UDCS3 .EQU 0x00031B +_gcn13 .EQU 0x000320 +GCN13 .EQU 0x000320 /* PPG Control 12-15 */ +_gcn23 .EQU 0x000323 +GCN23 .EQU 0x000323 +_ptmr12 .EQU 0x000330 +PTMR12 .EQU 0x000330 /* PPG 12 */ +_pcsr12 .EQU 0x000332 +PCSR12 .EQU 0x000332 +_pdut12 .EQU 0x000334 +PDUT12 .EQU 0x000334 +_pcn12 .EQU 0x000336 +PCN12 .EQU 0x000336 +_pcnh12 .EQU 0x000336 +PCNH12 .EQU 0x000336 +_pcnl12 .EQU 0x000337 +PCNL12 .EQU 0x000337 +_ptmr13 .EQU 0x000338 +PTMR13 .EQU 0x000338 /* PPG 13 */ +_pcsr13 .EQU 0x00033A +PCSR13 .EQU 0x00033A +_pdut13 .EQU 0x00033C +PDUT13 .EQU 0x00033C +_pcn13 .EQU 0x00033E +PCN13 .EQU 0x00033E +_pcnh13 .EQU 0x00033E +PCNH13 .EQU 0x00033E +_pcnl13 .EQU 0x00033F +PCNL13 .EQU 0x00033F +_ptmr14 .EQU 0x000340 +PTMR14 .EQU 0x000340 /* PPG 14 */ +_pcsr14 .EQU 0x000342 +PCSR14 .EQU 0x000342 +_pdut14 .EQU 0x000344 +PDUT14 .EQU 0x000344 +_pcn14 .EQU 0x000346 +PCN14 .EQU 0x000346 +_pcnh14 .EQU 0x000346 +PCNH14 .EQU 0x000346 +_pcnl14 .EQU 0x000347 +PCNL14 .EQU 0x000347 +_ptmr15 .EQU 0x000348 +PTMR15 .EQU 0x000348 /* PPG 15 */ +_pcsr15 .EQU 0x00034A +PCSR15 .EQU 0x00034A +_pdut15 .EQU 0x00034C +PDUT15 .EQU 0x00034C +_pcn15 .EQU 0x00034E +PCN15 .EQU 0x00034E +_pcnh15 .EQU 0x00034E +PCNH15 .EQU 0x00034E +_pcnl15 .EQU 0x00034F +PCNL15 .EQU 0x00034F +_ibcr2 .EQU 0x000368 +IBCR2 .EQU 0x000368 /* I2C 2 */ +_ibsr2 .EQU 0x000369 +IBSR2 .EQU 0x000369 +_itba2 .EQU 0x00036A +ITBA2 .EQU 0x00036A +_itbah2 .EQU 0x00036A +ITBAH2 .EQU 0x00036A +_itbal2 .EQU 0x00036B +ITBAL2 .EQU 0x00036B +_itmk2 .EQU 0x00036C +ITMK2 .EQU 0x00036C +_itmkh2 .EQU 0x00036C +ITMKH2 .EQU 0x00036C +_itmkl2 .EQU 0x00036D +ITMKL2 .EQU 0x00036D +_ismk2 .EQU 0x00036E +ISMK2 .EQU 0x00036E +_isba2 .EQU 0x00036F +ISBA2 .EQU 0x00036F +_idar2 .EQU 0x000371 +IDAR2 .EQU 0x000371 +_iccr2 .EQU 0x000372 +ICCR2 .EQU 0x000372 +_ibcr3 .EQU 0x000374 +IBCR3 .EQU 0x000374 /* I2C 3 */ +_ibsr3 .EQU 0x000375 +IBSR3 .EQU 0x000375 +_itba3 .EQU 0x000376 +ITBA3 .EQU 0x000376 +_itbah3 .EQU 0x000376 +ITBAH3 .EQU 0x000376 +_itbal3 .EQU 0x000377 +ITBAL3 .EQU 0x000377 +_itmk3 .EQU 0x000378 +ITMK3 .EQU 0x000378 +_itmkh3 .EQU 0x000378 +ITMKH3 .EQU 0x000378 +_itmkl3 .EQU 0x000379 +ITMKL3 .EQU 0x000379 +_ismk3 .EQU 0x00037A +ISMK3 .EQU 0x00037A +_isba3 .EQU 0x00037B +ISBA3 .EQU 0x00037B +_idar3 .EQU 0x00037D +IDAR3 .EQU 0x00037D +_iccr3 .EQU 0x00037E +ICCR3 .EQU 0x00037E +_roms .EQU 0x000390 +ROMS .EQU 0x000390 /* ROM Select Register */ +_bsd0 .EQU 0x0003F0 +BSD0 .EQU 0x0003F0 /* Bit Search Module */ +_bsd1 .EQU 0x0003F4 +BSD1 .EQU 0x0003F4 +_bsdc .EQU 0x0003F8 +BSDC .EQU 0x0003F8 +_bsrr .EQU 0x0003FC +BSRR .EQU 0x0003FC +_icr00 .EQU 0x000440 +ICR00 .EQU 0x000440 /* Interrupt Control Unit */ +_icr01 .EQU 0x000441 +ICR01 .EQU 0x000441 +_icr02 .EQU 0x000442 +ICR02 .EQU 0x000442 +_icr03 .EQU 0x000443 +ICR03 .EQU 0x000443 +_icr04 .EQU 0x000444 +ICR04 .EQU 0x000444 +_icr05 .EQU 0x000445 +ICR05 .EQU 0x000445 +_icr06 .EQU 0x000446 +ICR06 .EQU 0x000446 +_icr07 .EQU 0x000447 +ICR07 .EQU 0x000447 +_icr08 .EQU 0x000448 +ICR08 .EQU 0x000448 +_icr09 .EQU 0x000449 +ICR09 .EQU 0x000449 +_icr10 .EQU 0x00044A +ICR10 .EQU 0x00044A +_icr11 .EQU 0x00044B +ICR11 .EQU 0x00044B +_icr12 .EQU 0x00044C +ICR12 .EQU 0x00044C +_icr13 .EQU 0x00044D +ICR13 .EQU 0x00044D +_icr14 .EQU 0x00044E +ICR14 .EQU 0x00044E +_icr15 .EQU 0x00044F +ICR15 .EQU 0x00044F +_icr16 .EQU 0x000450 +ICR16 .EQU 0x000450 +_icr17 .EQU 0x000451 +ICR17 .EQU 0x000451 +_icr18 .EQU 0x000452 +ICR18 .EQU 0x000452 +_icr19 .EQU 0x000453 +ICR19 .EQU 0x000453 +_icr20 .EQU 0x000454 +ICR20 .EQU 0x000454 +_icr21 .EQU 0x000455 +ICR21 .EQU 0x000455 +_icr22 .EQU 0x000456 +ICR22 .EQU 0x000456 +_icr23 .EQU 0x000457 +ICR23 .EQU 0x000457 +_icr24 .EQU 0x000458 +ICR24 .EQU 0x000458 +_icr25 .EQU 0x000459 +ICR25 .EQU 0x000459 +_icr26 .EQU 0x00045A +ICR26 .EQU 0x00045A +_icr27 .EQU 0x00045B +ICR27 .EQU 0x00045B +_icr28 .EQU 0x00045C +ICR28 .EQU 0x00045C +_icr29 .EQU 0x00045D +ICR29 .EQU 0x00045D +_icr30 .EQU 0x00045E +ICR30 .EQU 0x00045E +_icr31 .EQU 0x00045F +ICR31 .EQU 0x00045F +_icr32 .EQU 0x000460 +ICR32 .EQU 0x000460 +_icr33 .EQU 0x000461 +ICR33 .EQU 0x000461 +_icr34 .EQU 0x000462 +ICR34 .EQU 0x000462 +_icr35 .EQU 0x000463 +ICR35 .EQU 0x000463 +_icr36 .EQU 0x000464 +ICR36 .EQU 0x000464 +_icr37 .EQU 0x000465 +ICR37 .EQU 0x000465 +_icr38 .EQU 0x000466 +ICR38 .EQU 0x000466 +_icr39 .EQU 0x000467 +ICR39 .EQU 0x000467 +_icr40 .EQU 0x000468 +ICR40 .EQU 0x000468 +_icr41 .EQU 0x000469 +ICR41 .EQU 0x000469 +_icr42 .EQU 0x00046A +ICR42 .EQU 0x00046A +_icr43 .EQU 0x00046B +ICR43 .EQU 0x00046B +_icr44 .EQU 0x00046C +ICR44 .EQU 0x00046C +_icr45 .EQU 0x00046D +ICR45 .EQU 0x00046D +_icr46 .EQU 0x00046E +ICR46 .EQU 0x00046E +_icr47 .EQU 0x00046F +ICR47 .EQU 0x00046F +_icr48 .EQU 0x000470 +ICR48 .EQU 0x000470 +_icr49 .EQU 0x000471 +ICR49 .EQU 0x000471 +_icr50 .EQU 0x000472 +ICR50 .EQU 0x000472 +_icr51 .EQU 0x000473 +ICR51 .EQU 0x000473 +_icr52 .EQU 0x000474 +ICR52 .EQU 0x000474 +_icr53 .EQU 0x000475 +ICR53 .EQU 0x000475 +_icr54 .EQU 0x000476 +ICR54 .EQU 0x000476 +_icr55 .EQU 0x000477 +ICR55 .EQU 0x000477 +_icr56 .EQU 0x000478 +ICR56 .EQU 0x000478 +_icr57 .EQU 0x000479 +ICR57 .EQU 0x000479 +_icr58 .EQU 0x00047A +ICR58 .EQU 0x00047A +_icr59 .EQU 0x00047B +ICR59 .EQU 0x00047B +_icr60 .EQU 0x00047C +ICR60 .EQU 0x00047C +_icr61 .EQU 0x00047D +ICR61 .EQU 0x00047D +_icr62 .EQU 0x00047E +ICR62 .EQU 0x00047E +_icr63 .EQU 0x00047F +ICR63 .EQU 0x00047F +_rsrr .EQU 0x000480 +RSRR .EQU 0x000480 /* Clock Control Unit */ +_stcr .EQU 0x000481 +STCR .EQU 0x000481 +_tbcr .EQU 0x000482 +TBCR .EQU 0x000482 +_ctbr .EQU 0x000483 +CTBR .EQU 0x000483 +_clkr .EQU 0x000484 +CLKR .EQU 0x000484 +_wpr .EQU 0x000485 +WPR .EQU 0x000485 +_divr0 .EQU 0x000486 +DIVR0 .EQU 0x000486 +_divr1 .EQU 0x000487 +DIVR1 .EQU 0x000487 +_plldivm .EQU 0x00048C +PLLDIVM .EQU 0x00048C /* PLL - Clock Gear Unit: */ +_plldivn .EQU 0x00048D +PLLDIVN .EQU 0x00048D +_plldivg .EQU 0x00048E +PLLDIVG .EQU 0x00048E +_pllmulg .EQU 0x00048F +PLLMULG .EQU 0x00048F +_pllctrl .EQU 0x000490 +PLLCTRL .EQU 0x000490 +_oscc1 .EQU 0x000494 +OSCC1 .EQU 0x000494 /* Main/Sub Oscillator Control */ +_oscs1 .EQU 0x000495 +OSCS1 .EQU 0x000495 +_oscc2 .EQU 0x000496 +OSCC2 .EQU 0x000496 +_oscs2 .EQU 0x000497 +OSCS2 .EQU 0x000497 +_porten .EQU 0x000498 +PORTEN .EQU 0x000498 /* Port Input Enable Control */ +_wtcer .EQU 0x0004A1 +WTCER .EQU 0x0004A1 /* Real Time Clock (Watch Timer) */ +_wtcr .EQU 0x0004A2 +WTCR .EQU 0x0004A2 +_wtbr .EQU 0x0004A4 +WTBR .EQU 0x0004A4 +_wthr .EQU 0x0004A8 +WTHR .EQU 0x0004A8 +_wtmr .EQU 0x0004A9 +WTMR .EQU 0x0004A9 +_wtsr .EQU 0x0004AA +WTSR .EQU 0x0004AA +_csvtr .EQU 0x0004AC +CSVTR .EQU 0x0004AC /* Clock-Supervisor / Selecor / Monitor */ +_csvcr .EQU 0x0004AD +CSVCR .EQU 0x0004AD +_cscfg .EQU 0x0004AE +CSCFG .EQU 0x0004AE +_cmcfg .EQU 0x0004AF +CMCFG .EQU 0x0004AF +_cucr .EQU 0x0004B0 +CUCR .EQU 0x0004B0 /* Calibration Unit of Sub Oszillation */ +_cutd .EQU 0x0004B2 +CUTD .EQU 0x0004B2 +_cutr1 .EQU 0x0004B4 +CUTR1 .EQU 0x0004B4 +_cutr2 .EQU 0x0004B6 +CUTR2 .EQU 0x0004B6 +_cmpr .EQU 0x0004B8 +CMPR .EQU 0x0004B8 /* Clock Modulator */ +_cmcr .EQU 0x0004BB +CMCR .EQU 0x0004BB +_cmt1 .EQU 0x0004BC +CMT1 .EQU 0x0004BC +_cmt2 .EQU 0x0004BE +CMT2 .EQU 0x0004BE +_canpre .EQU 0x0004C0 +CANPRE .EQU 0x0004C0 /* CAN clock control */ +_canckd .EQU 0x0004C1 +CANCKD .EQU 0x0004C1 +_lvsel .EQU 0x0004C4 +LVSEL .EQU 0x0004C4 /* LV Detection / Hardware-Watchdog */ +_lvdet .EQU 0x0004C5 +LVDET .EQU 0x0004C5 +_hwwde .EQU 0x0004C6 +HWWDE .EQU 0x0004C6 +_hwwd .EQU 0x0004C7 +HWWD .EQU 0x0004C7 +_oscrh .EQU 0x0004C8 +OSCRH .EQU 0x0004C8 /* Main-/Sub-Oscillatio Stabilization Timer */ +_oscrl .EQU 0x0004C9 +OSCRL .EQU 0x0004C9 +_wpcrh .EQU 0x0004CA +WPCRH .EQU 0x0004CA +_wpcrl .EQU 0x0004CB +WPCRL .EQU 0x0004CB +_osccr .EQU 0x0004CC +OSCCR .EQU 0x0004CC /* Main-/Sub-Oscillatio Standby Control */ +_regsel .EQU 0x0004CE +REGSEL .EQU 0x0004CE +_regctr .EQU 0x0004CF +REGCTR .EQU 0x0004CF +_asr0 .EQU 0x000640 +ASR0 .EQU 0x000640 /* External Bus/Chip Select Registers */ +_acr0 .EQU 0x000642 +ACR0 .EQU 0x000642 +_asr1 .EQU 0x000644 +ASR1 .EQU 0x000644 +_acr1 .EQU 0x000646 +ACR1 .EQU 0x000646 +_asr2 .EQU 0x000648 +ASR2 .EQU 0x000648 +_acr2 .EQU 0x00064A +ACR2 .EQU 0x00064A +_asr3 .EQU 0x00064C +ASR3 .EQU 0x00064C +_acr3 .EQU 0x00064E +ACR3 .EQU 0x00064E +_asr4 .EQU 0x000650 +ASR4 .EQU 0x000650 +_acr4 .EQU 0x000652 +ACR4 .EQU 0x000652 +_asr5 .EQU 0x000654 +ASR5 .EQU 0x000654 +_acr5 .EQU 0x000656 +ACR5 .EQU 0x000656 +_asr6 .EQU 0x000658 +ASR6 .EQU 0x000658 +_acr6 .EQU 0x00065A +ACR6 .EQU 0x00065A +_asr7 .EQU 0x00065C +ASR7 .EQU 0x00065C +_acr7 .EQU 0x00065E +ACR7 .EQU 0x00065E +_awr0 .EQU 0x000660 +AWR0 .EQU 0x000660 +_awr1 .EQU 0x000662 +AWR1 .EQU 0x000662 +_awr2 .EQU 0x000664 +AWR2 .EQU 0x000664 +_awr3 .EQU 0x000666 +AWR3 .EQU 0x000666 +_awr4 .EQU 0x000668 +AWR4 .EQU 0x000668 +_awr5 .EQU 0x00066A +AWR5 .EQU 0x00066A +_awr6 .EQU 0x00066C +AWR6 .EQU 0x00066C +_awr7 .EQU 0x00066E +AWR7 .EQU 0x00066E +_mcra .EQU 0x000670 +MCRA .EQU 0x000670 +_mcrb .EQU 0x000671 +MCRB .EQU 0x000671 +_iowr0 .EQU 0x000678 +IOWR0 .EQU 0x000678 +_iowr1 .EQU 0x000679 +IOWR1 .EQU 0x000679 +_iowr2 .EQU 0x00067A +IOWR2 .EQU 0x00067A +_iowr3 .EQU 0x00067B +IOWR3 .EQU 0x00067B +_cser .EQU 0x000680 +CSER .EQU 0x000680 +_cher .EQU 0x000681 +CHER .EQU 0x000681 +_tcr .EQU 0x000683 +TCR .EQU 0x000683 +_rcr .EQU 0x000684 +RCR .EQU 0x000684 +_modr .EQU 0x0007FD +MODR .EQU 0x0007FD /* Mode Register */ +_pdrd00 .EQU 0x000D00 +PDRD00 .EQU 0x000D00 /* R-bus Port Data Direct Read Register */ +_pdrd01 .EQU 0x000D01 +PDRD01 .EQU 0x000D01 +_pdrd02 .EQU 0x000D02 +PDRD02 .EQU 0x000D02 +_pdrd03 .EQU 0x000D03 +PDRD03 .EQU 0x000D03 +_pdrd04 .EQU 0x000D04 +PDRD04 .EQU 0x000D04 +_pdrd05 .EQU 0x000D05 +PDRD05 .EQU 0x000D05 +_pdrd06 .EQU 0x000D06 +PDRD06 .EQU 0x000D06 +_pdrd07 .EQU 0x000D07 +PDRD07 .EQU 0x000D07 +_pdrd08 .EQU 0x000D08 +PDRD08 .EQU 0x000D08 +_pdrd09 .EQU 0x000D09 +PDRD09 .EQU 0x000D09 +_pdrd10 .EQU 0x000D0A +PDRD10 .EQU 0x000D0A +_pdrd13 .EQU 0x000D0D +PDRD13 .EQU 0x000D0D +_pdrd14 .EQU 0x000D0E +PDRD14 .EQU 0x000D0E +_pdrd15 .EQU 0x000D0F +PDRD15 .EQU 0x000D0F +_pdrd16 .EQU 0x000D10 +PDRD16 .EQU 0x000D10 +_pdrd17 .EQU 0x000D11 +PDRD17 .EQU 0x000D11 +_pdrd18 .EQU 0x000D12 +PDRD18 .EQU 0x000D12 +_pdrd19 .EQU 0x000D13 +PDRD19 .EQU 0x000D13 +_pdrd20 .EQU 0x000D14 +PDRD20 .EQU 0x000D14 +_pdrd22 .EQU 0x000D16 +PDRD22 .EQU 0x000D16 +_pdrd23 .EQU 0x000D17 +PDRD23 .EQU 0x000D17 +_pdrd24 .EQU 0x000D18 +PDRD24 .EQU 0x000D18 +_pdrd25 .EQU 0x000D19 +PDRD25 .EQU 0x000D19 +_pdrd26 .EQU 0x000D1A +PDRD26 .EQU 0x000D1A +_pdrd27 .EQU 0x000D1B +PDRD27 .EQU 0x000D1B +_pdrd29 .EQU 0x000D1D +PDRD29 .EQU 0x000D1D +_ddr00 .EQU 0x000D40 +DDR00 .EQU 0x000D40 /* R-bus Port Direction Register */ +_ddr01 .EQU 0x000D41 +DDR01 .EQU 0x000D41 +_ddr02 .EQU 0x000D42 +DDR02 .EQU 0x000D42 +_ddr03 .EQU 0x000D43 +DDR03 .EQU 0x000D43 +_ddr04 .EQU 0x000D44 +DDR04 .EQU 0x000D44 +_ddr05 .EQU 0x000D45 +DDR05 .EQU 0x000D45 +_ddr06 .EQU 0x000D46 +DDR06 .EQU 0x000D46 +_ddr07 .EQU 0x000D47 +DDR07 .EQU 0x000D47 +_ddr08 .EQU 0x000D48 +DDR08 .EQU 0x000D48 +_ddr09 .EQU 0x000D49 +DDR09 .EQU 0x000D49 +_ddr10 .EQU 0x000D4A +DDR10 .EQU 0x000D4A +_ddr13 .EQU 0x000D4D +DDR13 .EQU 0x000D4D +_ddr14 .EQU 0x000D4E +DDR14 .EQU 0x000D4E +_ddr15 .EQU 0x000D4F +DDR15 .EQU 0x000D4F +_ddr16 .EQU 0x000D50 +DDR16 .EQU 0x000D50 +_ddr17 .EQU 0x000D51 +DDR17 .EQU 0x000D51 +_ddr18 .EQU 0x000D52 +DDR18 .EQU 0x000D52 +_ddr19 .EQU 0x000D53 +DDR19 .EQU 0x000D53 +_ddr20 .EQU 0x000D54 +DDR20 .EQU 0x000D54 +_ddr22 .EQU 0x000D56 +DDR22 .EQU 0x000D56 +_ddr23 .EQU 0x000D57 +DDR23 .EQU 0x000D57 +_ddr24 .EQU 0x000D58 +DDR24 .EQU 0x000D58 +_ddr25 .EQU 0x000D59 +DDR25 .EQU 0x000D59 +_ddr26 .EQU 0x000D5A +DDR26 .EQU 0x000D5A +_ddr27 .EQU 0x000D5B +DDR27 .EQU 0x000D5B +_ddr29 .EQU 0x000D5D +DDR29 .EQU 0x000D5D +_pfr00 .EQU 0x000D80 +PFR00 .EQU 0x000D80 /* R-bus Port Function Register */ +_pfr01 .EQU 0x000D81 +PFR01 .EQU 0x000D81 +_pfr02 .EQU 0x000D82 +PFR02 .EQU 0x000D82 +_pfr03 .EQU 0x000D83 +PFR03 .EQU 0x000D83 +_pfr04 .EQU 0x000D84 +PFR04 .EQU 0x000D84 +_pfr05 .EQU 0x000D85 +PFR05 .EQU 0x000D85 +_pfr06 .EQU 0x000D86 +PFR06 .EQU 0x000D86 +_pfr07 .EQU 0x000D87 +PFR07 .EQU 0x000D87 +_pfr08 .EQU 0x000D88 +PFR08 .EQU 0x000D88 +_pfr09 .EQU 0x000D89 +PFR09 .EQU 0x000D89 +_pfr10 .EQU 0x000D8A +PFR10 .EQU 0x000D8A +_pfr13 .EQU 0x000D8D +PFR13 .EQU 0x000D8D +_pfr14 .EQU 0x000D8E +PFR14 .EQU 0x000D8E +_pfr15 .EQU 0x000D8F +PFR15 .EQU 0x000D8F +_pfr16 .EQU 0x000D90 +PFR16 .EQU 0x000D90 +_pfr17 .EQU 0x000D91 +PFR17 .EQU 0x000D91 +_pfr18 .EQU 0x000D92 +PFR18 .EQU 0x000D92 +_pfr19 .EQU 0x000D93 +PFR19 .EQU 0x000D93 +_pfr20 .EQU 0x000D94 +PFR20 .EQU 0x000D94 +_pfr22 .EQU 0x000D96 +PFR22 .EQU 0x000D96 +_pfr23 .EQU 0x000D97 +PFR23 .EQU 0x000D97 +_pfr24 .EQU 0x000D98 +PFR24 .EQU 0x000D98 +_pfr25 .EQU 0x000D99 +PFR25 .EQU 0x000D99 +_pfr26 .EQU 0x000D9A +PFR26 .EQU 0x000D9A +_pfr27 .EQU 0x000D9B +PFR27 .EQU 0x000D9B +_pfr29 .EQU 0x000D9D +PFR29 .EQU 0x000D9D +_epfr10 .EQU 0x000DCA +EPFR10 .EQU 0x000DCA /* R-bus Port Extra Function Register */ +_epfr13 .EQU 0x000DCD +EPFR13 .EQU 0x000DCD +_epfr14 .EQU 0x000DCE +EPFR14 .EQU 0x000DCE +_epfr15 .EQU 0x000DCF +EPFR15 .EQU 0x000DCF +_epfr16 .EQU 0x000DD0 +EPFR16 .EQU 0x000DD0 +_epfr18 .EQU 0x000DD2 +EPFR18 .EQU 0x000DD2 +_epfr19 .EQU 0x000DD3 +EPFR19 .EQU 0x000DD3 +_epfr20 .EQU 0x000DD4 +EPFR20 .EQU 0x000DD4 +_epfr26 .EQU 0x000DDA +EPFR26 .EQU 0x000DDA +_epfr27 .EQU 0x000DDB +EPFR27 .EQU 0x000DDB +_podr00 .EQU 0x000E00 +PODR00 .EQU 0x000E00 /* R-bus Port Output Drive Select Register */ +_podr01 .EQU 0x000E01 +PODR01 .EQU 0x000E01 +_podr02 .EQU 0x000E02 +PODR02 .EQU 0x000E02 +_podr03 .EQU 0x000E03 +PODR03 .EQU 0x000E03 +_podr04 .EQU 0x000E04 +PODR04 .EQU 0x000E04 +_podr05 .EQU 0x000E05 +PODR05 .EQU 0x000E05 +_podr06 .EQU 0x000E06 +PODR06 .EQU 0x000E06 +_podr07 .EQU 0x000E07 +PODR07 .EQU 0x000E07 +_podr08 .EQU 0x000E08 +PODR08 .EQU 0x000E08 +_podr09 .EQU 0x000E09 +PODR09 .EQU 0x000E09 +_podr10 .EQU 0x000E0A +PODR10 .EQU 0x000E0A +_podr13 .EQU 0x000E0D +PODR13 .EQU 0x000E0D +_podr14 .EQU 0x000E0E +PODR14 .EQU 0x000E0E +_podr15 .EQU 0x000E0F +PODR15 .EQU 0x000E0F +_podr16 .EQU 0x000E10 +PODR16 .EQU 0x000E10 +_podr17 .EQU 0x000E11 +PODR17 .EQU 0x000E11 +_podr18 .EQU 0x000E12 +PODR18 .EQU 0x000E12 +_podr19 .EQU 0x000E13 +PODR19 .EQU 0x000E13 +_podr20 .EQU 0x000E14 +PODR20 .EQU 0x000E14 +_podr22 .EQU 0x000E16 +PODR22 .EQU 0x000E16 +_podr23 .EQU 0x000E17 +PODR23 .EQU 0x000E17 +_podr24 .EQU 0x000E18 +PODR24 .EQU 0x000E18 +_podr25 .EQU 0x000E19 +PODR25 .EQU 0x000E19 +_podr26 .EQU 0x000E1A +PODR26 .EQU 0x000E1A +_podr27 .EQU 0x000E1B +PODR27 .EQU 0x000E1B +_podr29 .EQU 0x000E1D +PODR29 .EQU 0x000E1D +_pilr00 .EQU 0x000E40 +PILR00 .EQU 0x000E40 /* R-bus Port Input Level Select Register */ +_pilr01 .EQU 0x000E41 +PILR01 .EQU 0x000E41 +_pilr02 .EQU 0x000E42 +PILR02 .EQU 0x000E42 +_pilr03 .EQU 0x000E43 +PILR03 .EQU 0x000E43 +_pilr04 .EQU 0x000E44 +PILR04 .EQU 0x000E44 +_pilr05 .EQU 0x000E45 +PILR05 .EQU 0x000E45 +_pilr06 .EQU 0x000E46 +PILR06 .EQU 0x000E46 +_pilr07 .EQU 0x000E47 +PILR07 .EQU 0x000E47 +_pilr08 .EQU 0x000E48 +PILR08 .EQU 0x000E48 +_pilr09 .EQU 0x000E49 +PILR09 .EQU 0x000E49 +_pilr10 .EQU 0x000E4A +PILR10 .EQU 0x000E4A +_pilr13 .EQU 0x000E4D +PILR13 .EQU 0x000E4D +_pilr14 .EQU 0x000E4E +PILR14 .EQU 0x000E4E +_pilr15 .EQU 0x000E4F +PILR15 .EQU 0x000E4F +_pilr16 .EQU 0x000E50 +PILR16 .EQU 0x000E50 +_pilr17 .EQU 0x000E51 +PILR17 .EQU 0x000E51 +_pilr18 .EQU 0x000E52 +PILR18 .EQU 0x000E52 +_pilr19 .EQU 0x000E53 +PILR19 .EQU 0x000E53 +_pilr20 .EQU 0x000E54 +PILR20 .EQU 0x000E54 +_pilr22 .EQU 0x000E56 +PILR22 .EQU 0x000E56 +_pilr23 .EQU 0x000E57 +PILR23 .EQU 0x000E57 +_pilr24 .EQU 0x000E58 +PILR24 .EQU 0x000E58 +_pilr25 .EQU 0x000E59 +PILR25 .EQU 0x000E59 +_pilr26 .EQU 0x000E5A +PILR26 .EQU 0x000E5A +_pilr27 .EQU 0x000E5B +PILR27 .EQU 0x000E5B +_pilr29 .EQU 0x000E5D +PILR29 .EQU 0x000E5D +_epilr00 .EQU 0x000E80 +EPILR00 .EQU 0x000E80 /* R-bus Port Extra Input Level Select Register */ +_epilr01 .EQU 0x000E81 +EPILR01 .EQU 0x000E81 +_epilr02 .EQU 0x000E82 +EPILR02 .EQU 0x000E82 +_epilr03 .EQU 0x000E83 +EPILR03 .EQU 0x000E83 +_epilr04 .EQU 0x000E84 +EPILR04 .EQU 0x000E84 +_epilr05 .EQU 0x000E85 +EPILR05 .EQU 0x000E85 +_epilr06 .EQU 0x000E86 +EPILR06 .EQU 0x000E86 +_epilr07 .EQU 0x000E87 +EPILR07 .EQU 0x000E87 +_epilr08 .EQU 0x000E88 +EPILR08 .EQU 0x000E88 +_epilr09 .EQU 0x000E89 +EPILR09 .EQU 0x000E89 +_epilr10 .EQU 0x000E8A +EPILR10 .EQU 0x000E8A +_epilr13 .EQU 0x000E8D +EPILR13 .EQU 0x000E8D +_epilr14 .EQU 0x000E8E +EPILR14 .EQU 0x000E8E +_epilr15 .EQU 0x000E8F +EPILR15 .EQU 0x000E8F +_epilr16 .EQU 0x000E80 +EPILR16 .EQU 0x000E80 +_epilr17 .EQU 0x000E81 +EPILR17 .EQU 0x000E81 +_epilr18 .EQU 0x000E82 +EPILR18 .EQU 0x000E82 +_epilr19 .EQU 0x000E83 +EPILR19 .EQU 0x000E83 +_epilr20 .EQU 0x000E84 +EPILR20 .EQU 0x000E84 +_epilr22 .EQU 0x000E86 +EPILR22 .EQU 0x000E86 +_epilr23 .EQU 0x000E87 +EPILR23 .EQU 0x000E87 +_epilr24 .EQU 0x000E88 +EPILR24 .EQU 0x000E88 +_epilr25 .EQU 0x000E89 +EPILR25 .EQU 0x000E89 +_epilr26 .EQU 0x000E8A +EPILR26 .EQU 0x000E8A +_epilr27 .EQU 0x000E8B +EPILR27 .EQU 0x000E8B +_epilr29 .EQU 0x000E8D +EPILR29 .EQU 0x000E8D +_pper00 .EQU 0x000EC0 +PPER00 .EQU 0x000EC0 /* R-bus Port Pull-Up/Down Enable Register */ +_pper01 .EQU 0x000EC1 +PPER01 .EQU 0x000EC1 +_pper02 .EQU 0x000EC2 +PPER02 .EQU 0x000EC2 +_pper03 .EQU 0x000EC3 +PPER03 .EQU 0x000EC3 +_pper04 .EQU 0x000EC4 +PPER04 .EQU 0x000EC4 +_pper05 .EQU 0x000EC5 +PPER05 .EQU 0x000EC5 +_pper06 .EQU 0x000EC6 +PPER06 .EQU 0x000EC6 +_pper07 .EQU 0x000EC7 +PPER07 .EQU 0x000EC7 +_pper08 .EQU 0x000EC8 +PPER08 .EQU 0x000EC8 +_pper09 .EQU 0x000EC9 +PPER09 .EQU 0x000EC9 +_pper10 .EQU 0x000ECA +PPER10 .EQU 0x000ECA +_pper13 .EQU 0x000ECD +PPER13 .EQU 0x000ECD +_pper14 .EQU 0x000ECE +PPER14 .EQU 0x000ECE +_pper15 .EQU 0x000ECF +PPER15 .EQU 0x000ECF +_pper16 .EQU 0x000ED0 +PPER16 .EQU 0x000ED0 +_pper17 .EQU 0x000ED1 +PPER17 .EQU 0x000ED1 +_pper18 .EQU 0x000ED2 +PPER18 .EQU 0x000ED2 +_pper19 .EQU 0x000ED3 +PPER19 .EQU 0x000ED3 +_pper20 .EQU 0x000ED4 +PPER20 .EQU 0x000ED4 +_pper22 .EQU 0x000ED6 +PPER22 .EQU 0x000ED6 +_pper23 .EQU 0x000ED7 +PPER23 .EQU 0x000ED7 +_pper24 .EQU 0x000ED8 +PPER24 .EQU 0x000ED8 +_pper25 .EQU 0x000ED9 +PPER25 .EQU 0x000ED9 +_pper26 .EQU 0x000EDA +PPER26 .EQU 0x000EDA +_pper27 .EQU 0x000EDB +PPER27 .EQU 0x000EDB +_pper29 .EQU 0x000EDD +PPER29 .EQU 0x000EDD +_ppcr00 .EQU 0x000F00 +PPCR00 .EQU 0x000F00 /* R-bus Port Pull-Up/Down Control Register */ +_ppcr01 .EQU 0x000F01 +PPCR01 .EQU 0x000F01 +_ppcr02 .EQU 0x000F02 +PPCR02 .EQU 0x000F02 +_ppcr03 .EQU 0x000F03 +PPCR03 .EQU 0x000F03 +_ppcr04 .EQU 0x000F04 +PPCR04 .EQU 0x000F04 +_ppcr05 .EQU 0x000F05 +PPCR05 .EQU 0x000F05 +_ppcr06 .EQU 0x000F06 +PPCR06 .EQU 0x000F06 +_ppcr07 .EQU 0x000F07 +PPCR07 .EQU 0x000F07 +_ppcr08 .EQU 0x000F08 +PPCR08 .EQU 0x000F08 +_ppcr09 .EQU 0x000F09 +PPCR09 .EQU 0x000F09 +_ppcr10 .EQU 0x000F0A +PPCR10 .EQU 0x000F0A +_ppcr13 .EQU 0x000F0D +PPCR13 .EQU 0x000F0D +_ppcr14 .EQU 0x000F0E +PPCR14 .EQU 0x000F0E +_ppcr15 .EQU 0x000F0F +PPCR15 .EQU 0x000F0F +_ppcr16 .EQU 0x000F10 +PPCR16 .EQU 0x000F10 +_ppcr17 .EQU 0x000F11 +PPCR17 .EQU 0x000F11 +_ppcr18 .EQU 0x000F12 +PPCR18 .EQU 0x000F12 +_ppcr19 .EQU 0x000F13 +PPCR19 .EQU 0x000F13 +_ppcr20 .EQU 0x000F14 +PPCR20 .EQU 0x000F14 +_ppcr22 .EQU 0x000F16 +PPCR22 .EQU 0x000F16 +_ppcr23 .EQU 0x000F17 +PPCR23 .EQU 0x000F17 +_ppcr24 .EQU 0x000F18 +PPCR24 .EQU 0x000F18 +_ppcr25 .EQU 0x000F19 +PPCR25 .EQU 0x000F19 +_ppcr26 .EQU 0x000F1A +PPCR26 .EQU 0x000F1A +_ppcr27 .EQU 0x000F1B +PPCR27 .EQU 0x000F1B +_ppcr29 .EQU 0x000F1D +PPCR29 .EQU 0x000F1D +_dmasa0 .EQU 0x001000 +DMASA0 .EQU 0x001000 /* DMAC */ +_dmada0 .EQU 0x001004 +DMADA0 .EQU 0x001004 +_dmasa1 .EQU 0x001008 +DMASA1 .EQU 0x001008 +_dmada1 .EQU 0x00100C +DMADA1 .EQU 0x00100C +_dmasa2 .EQU 0x001010 +DMASA2 .EQU 0x001010 +_dmada2 .EQU 0x001014 +DMADA2 .EQU 0x001014 +_dmasa3 .EQU 0x001018 +DMASA3 .EQU 0x001018 +_dmada3 .EQU 0x00101C +DMADA3 .EQU 0x00101C +_dmasa4 .EQU 0x001020 +DMASA4 .EQU 0x001020 +_dmada4 .EQU 0x001024 +DMADA4 .EQU 0x001024 +_fmcs .EQU 0x007000 +FMCS .EQU 0x007000 /* Flash Memory/I-Cache Control Register */ +_fmcr .EQU 0x007001 +FMCR .EQU 0x007001 +_fchcr .EQU 0x007002 +FCHCR .EQU 0x007002 +_fmwt .EQU 0x007004 +FMWT .EQU 0x007004 +_fmwt2 .EQU 0x007006 +FMWT2 .EQU 0x007006 +_fmps .EQU 0x007007 +FMPS .EQU 0x007007 +_fmac .EQU 0x007008 +FMAC .EQU 0x007008 +_fcha0 .EQU 0x00700C +FCHA0 .EQU 0x00700C /* I_Cache Nonchachable area settings Register */ +_fcha1 .EQU 0x007010 +FCHA1 .EQU 0x007010 +_fscr0 .EQU 0x007100 +FSCR0 .EQU 0x007100 /* Flash Security Control Register */ +_fscr1 .EQU 0x007104 +FSCR1 .EQU 0x007104 +_ctrlr0 .EQU 0x00C000 +CTRLR0 .EQU 0x00C000 /* CAN 0 Control Register */ +_statr0 .EQU 0x00C002 +STATR0 .EQU 0x00C002 +_errcnt0 .EQU 0x00C004 +ERRCNT0 .EQU 0x00C004 +_btr0 .EQU 0x00C006 +BTR0 .EQU 0x00C006 +_intr0 .EQU 0x00C008 +INTR0 .EQU 0x00C008 +_testr0 .EQU 0x00C00A +TESTR0 .EQU 0x00C00A +_brper0 .EQU 0x00C00C +BRPER0 .EQU 0x00C00C +_brpe0 .EQU 0x00C00C +BRPE0 .EQU 0x00C00C +_cbsync0 .EQU 0x00C00E +CBSYNC0 .EQU 0x00C00E +_if1creq0 .EQU 0x00C010 +IF1CREQ0 .EQU 0x00C010 /* CAN 0 IF 1 */ +_if1cmsk0 .EQU 0x00C012 +IF1CMSK0 .EQU 0x00C012 +_if1msk120 .EQU 0x00C014 +IF1MSK120 .EQU 0x00C014 +_if1msk20 .EQU 0x00C014 +IF1MSK20 .EQU 0x00C014 +_if1msk10 .EQU 0x00C016 +IF1MSK10 .EQU 0x00C016 +_if1arb120 .EQU 0x00C018 +IF1ARB120 .EQU 0x00C018 +_if1arb20 .EQU 0x00C018 +IF1ARB20 .EQU 0x00C018 +_if1arb10 .EQU 0x00C01A +IF1ARB10 .EQU 0x00C01A +_if1mctr0 .EQU 0x00C01C +IF1MCTR0 .EQU 0x00C01C +_if1dta120 .EQU 0x00C020 +IF1DTA120 .EQU 0x00C020 +_if1dta10 .EQU 0x00C020 +IF1DTA10 .EQU 0x00C020 +_if1dta20 .EQU 0x00C022 +IF1DTA20 .EQU 0x00C022 +_if1dtb120 .EQU 0x00C024 +IF1DTB120 .EQU 0x00C024 +_if1dtb10 .EQU 0x00C024 +IF1DTB10 .EQU 0x00C024 +_if1dtb20 .EQU 0x00C026 +IF1DTB20 .EQU 0x00C026 +_if1dta_swp120 .EQU 0x00C030 +IF1DTA_SWP120 .EQU 0x00C030 +_if1dta_swp20 .EQU 0x00C030 +IF1DTA_SWP20 .EQU 0x00C030 +_if1dta_swp10 .EQU 0x00C032 +IF1DTA_SWP10 .EQU 0x00C032 +_if1dtb_swp120 .EQU 0x00C034 +IF1DTB_SWP120 .EQU 0x00C034 +_if1dtb_swp20 .EQU 0x00C034 +IF1DTB_SWP20 .EQU 0x00C034 +_if1dtb_swp10 .EQU 0x00C036 +IF1DTB_SWP10 .EQU 0x00C036 +_if2creq0 .EQU 0x00C040 +IF2CREQ0 .EQU 0x00C040 /* CAN 0 IF 2 */ +_if2cmsk0 .EQU 0x00C042 +IF2CMSK0 .EQU 0x00C042 +_if2msk120 .EQU 0x00C044 +IF2MSK120 .EQU 0x00C044 +_if2msk20 .EQU 0x00C044 +IF2MSK20 .EQU 0x00C044 +_if2msk10 .EQU 0x00C046 +IF2MSK10 .EQU 0x00C046 +_if2arb120 .EQU 0x00C048 +IF2ARB120 .EQU 0x00C048 +_if2arb20 .EQU 0x00C048 +IF2ARB20 .EQU 0x00C048 +_if2arb10 .EQU 0x00C04A +IF2ARB10 .EQU 0x00C04A +_if2mctr0 .EQU 0x00C04C +IF2MCTR0 .EQU 0x00C04C +_if2dta120 .EQU 0x00C050 +IF2DTA120 .EQU 0x00C050 +_if2dta10 .EQU 0x00C050 +IF2DTA10 .EQU 0x00C050 +_if2dta20 .EQU 0x00C052 +IF2DTA20 .EQU 0x00C052 +_if2dtb120 .EQU 0x00C054 +IF2DTB120 .EQU 0x00C054 +_if2dtb10 .EQU 0x00C054 +IF2DTB10 .EQU 0x00C054 +_if2dtb20 .EQU 0x00C056 +IF2DTB20 .EQU 0x00C056 +_if2dta_swp120 .EQU 0x00C060 +IF2DTA_SWP120 .EQU 0x00C060 +_if2dta_swp20 .EQU 0x00C060 +IF2DTA_SWP20 .EQU 0x00C060 +_if2dta_swp10 .EQU 0x00C062 +IF2DTA_SWP10 .EQU 0x00C062 +_if2dtb_swp120 .EQU 0x00C064 +IF2DTB_SWP120 .EQU 0x00C064 +_if2dtb_swp20 .EQU 0x00C064 +IF2DTB_SWP20 .EQU 0x00C064 +_if2dtb_swp10 .EQU 0x00C066 +IF2DTB_SWP10 .EQU 0x00C066 +_treqr120 .EQU 0x00C080 +TREQR120 .EQU 0x00C080 /* CAN 0 Status Flags */ +_treqr20 .EQU 0x00C080 +TREQR20 .EQU 0x00C080 +_treqr10 .EQU 0x00C082 +TREQR10 .EQU 0x00C082 +_newdt120 .EQU 0x00C090 +NEWDT120 .EQU 0x00C090 +_newdt20 .EQU 0x00C090 +NEWDT20 .EQU 0x00C090 +_newdt10 .EQU 0x00C092 +NEWDT10 .EQU 0x00C092 +_intpnd120 .EQU 0x00C0A0 +INTPND120 .EQU 0x00C0A0 +_intpnd20 .EQU 0x00C0A0 +INTPND20 .EQU 0x00C0A0 +_intpnd10 .EQU 0x00C0A2 +INTPND10 .EQU 0x00C0A2 +_msgval120 .EQU 0x00C0B0 +MSGVAL120 .EQU 0x00C0B0 +_msgval20 .EQU 0x00C0B0 +MSGVAL20 .EQU 0x00C0B0 +_msgval10 .EQU 0x00C0B2 +MSGVAL10 .EQU 0x00C0B2 +_msgval340 .EQU 0x00C0B4 +MSGVAL340 .EQU 0x00C0B4 +_ctrlr1 .EQU 0x00C100 +CTRLR1 .EQU 0x00C100 /* CAN 1 Control Register */ +_statr1 .EQU 0x00C102 +STATR1 .EQU 0x00C102 +_errcnt1 .EQU 0x00C104 +ERRCNT1 .EQU 0x00C104 +_btr1 .EQU 0x00C106 +BTR1 .EQU 0x00C106 +_intr1 .EQU 0x00C108 +INTR1 .EQU 0x00C108 +_testr1 .EQU 0x00C10A +TESTR1 .EQU 0x00C10A +_brper1 .EQU 0x00C10C +BRPER1 .EQU 0x00C10C +_brpe1 .EQU 0x00C10C +BRPE1 .EQU 0x00C10C +_cbsync1 .EQU 0x00C10E +CBSYNC1 .EQU 0x00C10E +_if1creq1 .EQU 0x00C110 +IF1CREQ1 .EQU 0x00C110 /* CAN 1 IF 1 */ +_if1cmsk1 .EQU 0x00C112 +IF1CMSK1 .EQU 0x00C112 +_if1msk121 .EQU 0x00C114 +IF1MSK121 .EQU 0x00C114 +_if1msk21 .EQU 0x00C114 +IF1MSK21 .EQU 0x00C114 +_if1msk11 .EQU 0x00C116 +IF1MSK11 .EQU 0x00C116 +_if1arb121 .EQU 0x00C118 +IF1ARB121 .EQU 0x00C118 +_if1arb21 .EQU 0x00C118 +IF1ARB21 .EQU 0x00C118 +_if1arb11 .EQU 0x00C11A +IF1ARB11 .EQU 0x00C11A +_if1mctr1 .EQU 0x00C11C +IF1MCTR1 .EQU 0x00C11C +_if1dta121 .EQU 0x00C120 +IF1DTA121 .EQU 0x00C120 +_if1dta11 .EQU 0x00C120 +IF1DTA11 .EQU 0x00C120 +_if1dta21 .EQU 0x00C122 +IF1DTA21 .EQU 0x00C122 +_if1dtb121 .EQU 0x00C124 +IF1DTB121 .EQU 0x00C124 +_if1dtb11 .EQU 0x00C124 +IF1DTB11 .EQU 0x00C124 +_if1dtb21 .EQU 0x00C126 +IF1DTB21 .EQU 0x00C126 +_if1dta_swp121 .EQU 0x00C130 +IF1DTA_SWP121 .EQU 0x00C130 +_if1dta_swp21 .EQU 0x00C130 +IF1DTA_SWP21 .EQU 0x00C130 +_if1dta_swp11 .EQU 0x00C132 +IF1DTA_SWP11 .EQU 0x00C132 +_if1dtb_swp121 .EQU 0x00C134 +IF1DTB_SWP121 .EQU 0x00C134 +_if1dtb_swp21 .EQU 0x00C134 +IF1DTB_SWP21 .EQU 0x00C134 +_if1dtb_swp11 .EQU 0x00C136 +IF1DTB_SWP11 .EQU 0x00C136 +_if2creq1 .EQU 0x00C140 +IF2CREQ1 .EQU 0x00C140 /* CAN 1 IF 2 */ +_if2cmsk1 .EQU 0x00C142 +IF2CMSK1 .EQU 0x00C142 +_if2msk121 .EQU 0x00C144 +IF2MSK121 .EQU 0x00C144 +_if2msk21 .EQU 0x00C144 +IF2MSK21 .EQU 0x00C144 +_if2msk11 .EQU 0x00C146 +IF2MSK11 .EQU 0x00C146 +_if2arb121 .EQU 0x00C148 +IF2ARB121 .EQU 0x00C148 +_if2arb21 .EQU 0x00C148 +IF2ARB21 .EQU 0x00C148 +_if2arb11 .EQU 0x00C14A +IF2ARB11 .EQU 0x00C14A +_if2mctr1 .EQU 0x00C14C +IF2MCTR1 .EQU 0x00C14C +_if2dta121 .EQU 0x00C150 +IF2DTA121 .EQU 0x00C150 +_if2dta11 .EQU 0x00C150 +IF2DTA11 .EQU 0x00C150 +_if2dta21 .EQU 0x00C152 +IF2DTA21 .EQU 0x00C152 +_if2dtb121 .EQU 0x00C154 +IF2DTB121 .EQU 0x00C154 +_if2dtb11 .EQU 0x00C154 +IF2DTB11 .EQU 0x00C154 +_if2dtb21 .EQU 0x00C156 +IF2DTB21 .EQU 0x00C156 +_if2dta_swp121 .EQU 0x00C160 +IF2DTA_SWP121 .EQU 0x00C160 +_if2dta_swp21 .EQU 0x00C160 +IF2DTA_SWP21 .EQU 0x00C160 +_if2dta_swp11 .EQU 0x00C162 +IF2DTA_SWP11 .EQU 0x00C162 +_if2dtb_swp121 .EQU 0x00C164 +IF2DTB_SWP121 .EQU 0x00C164 +_if2dtb_swp21 .EQU 0x00C164 +IF2DTB_SWP21 .EQU 0x00C164 +_if2dtb_swp11 .EQU 0x00C166 +IF2DTB_SWP11 .EQU 0x00C166 +_treqr121 .EQU 0x00C180 +TREQR121 .EQU 0x00C180 /* CAN 1 Status Flags */ +_treqr21 .EQU 0x00C180 +TREQR21 .EQU 0x00C180 +_treqr11 .EQU 0x00C182 +TREQR11 .EQU 0x00C182 +_newdt121 .EQU 0x00C190 +NEWDT121 .EQU 0x00C190 +_newdt21 .EQU 0x00C190 +NEWDT21 .EQU 0x00C190 +_newdt11 .EQU 0x00C192 +NEWDT11 .EQU 0x00C192 +_intpnd121 .EQU 0x00C1A0 +INTPND121 .EQU 0x00C1A0 +_intpnd21 .EQU 0x00C1A0 +INTPND21 .EQU 0x00C1A0 +_intpnd11 .EQU 0x00C1A2 +INTPND11 .EQU 0x00C1A2 +_msgval121 .EQU 0x00C1B0 +MSGVAL121 .EQU 0x00C1B0 +_msgval21 .EQU 0x00C1B0 +MSGVAL21 .EQU 0x00C1B0 +_msgval11 .EQU 0x00C1B2 +MSGVAL11 .EQU 0x00C1B2 +_ctrlr2 .EQU 0x00C200 +CTRLR2 .EQU 0x00C200 /* CAN 2 Control Register */ +_statr2 .EQU 0x00C202 +STATR2 .EQU 0x00C202 +_errcnt2 .EQU 0x00C204 +ERRCNT2 .EQU 0x00C204 +_btr2 .EQU 0x00C206 +BTR2 .EQU 0x00C206 +_intr2 .EQU 0x00C208 +INTR2 .EQU 0x00C208 +_testr2 .EQU 0x00C20A +TESTR2 .EQU 0x00C20A +_brper2 .EQU 0x00C20C +BRPER2 .EQU 0x00C20C +_brpe2 .EQU 0x00C20C +BRPE2 .EQU 0x00C20C +_cbsync2 .EQU 0x00C20E +CBSYNC2 .EQU 0x00C20E +_if1creq2 .EQU 0x00C210 +IF1CREQ2 .EQU 0x00C210 /* CAN 2 IF 1 */ +_if1cmsk2 .EQU 0x00C212 +IF1CMSK2 .EQU 0x00C212 +_if1msk122 .EQU 0x00C214 +IF1MSK122 .EQU 0x00C214 +_if1msk22 .EQU 0x00C214 +IF1MSK22 .EQU 0x00C214 +_if1msk12 .EQU 0x00C216 +IF1MSK12 .EQU 0x00C216 +_if1arb122 .EQU 0x00C218 +IF1ARB122 .EQU 0x00C218 +_if1arb22 .EQU 0x00C218 +IF1ARB22 .EQU 0x00C218 +_if1arb12 .EQU 0x00C21A +IF1ARB12 .EQU 0x00C21A +_if1mctr2 .EQU 0x00C21C +IF1MCTR2 .EQU 0x00C21C +_if1dta122 .EQU 0x00C220 +IF1DTA122 .EQU 0x00C220 +_if1dta12 .EQU 0x00C220 +IF1DTA12 .EQU 0x00C220 +_if1dta22 .EQU 0x00C222 +IF1DTA22 .EQU 0x00C222 +_if1dtb122 .EQU 0x00C224 +IF1DTB122 .EQU 0x00C224 +_if1dtb12 .EQU 0x00C224 +IF1DTB12 .EQU 0x00C224 +_if1dtb22 .EQU 0x00C226 +IF1DTB22 .EQU 0x00C226 +_if1dta_swp122 .EQU 0x00C230 +IF1DTA_SWP122 .EQU 0x00C230 +_if1dta_swp22 .EQU 0x00C230 +IF1DTA_SWP22 .EQU 0x00C230 +_if1dta_swp12 .EQU 0x00C232 +IF1DTA_SWP12 .EQU 0x00C232 +_if1dtb_swp122 .EQU 0x00C234 +IF1DTB_SWP122 .EQU 0x00C234 +_if1dtb_swp22 .EQU 0x00C234 +IF1DTB_SWP22 .EQU 0x00C234 +_if1dtb_swp12 .EQU 0x00C236 +IF1DTB_SWP12 .EQU 0x00C236 +_if2creq2 .EQU 0x00C240 +IF2CREQ2 .EQU 0x00C240 /* CAN 2 IF 2 */ +_if2cmsk2 .EQU 0x00C242 +IF2CMSK2 .EQU 0x00C242 +_if2msk122 .EQU 0x00C244 +IF2MSK122 .EQU 0x00C244 +_if2msk22 .EQU 0x00C244 +IF2MSK22 .EQU 0x00C244 +_if2msk12 .EQU 0x00C246 +IF2MSK12 .EQU 0x00C246 +_if2arb122 .EQU 0x00C248 +IF2ARB122 .EQU 0x00C248 +_if2arb22 .EQU 0x00C248 +IF2ARB22 .EQU 0x00C248 +_if2arb12 .EQU 0x00C24A +IF2ARB12 .EQU 0x00C24A +_if2mctr2 .EQU 0x00C24C +IF2MCTR2 .EQU 0x00C24C +_if2dta122 .EQU 0x00C250 +IF2DTA122 .EQU 0x00C250 +_if2dta12 .EQU 0x00C250 +IF2DTA12 .EQU 0x00C250 +_if2dta22 .EQU 0x00C252 +IF2DTA22 .EQU 0x00C252 +_if2dtb122 .EQU 0x00C254 +IF2DTB122 .EQU 0x00C254 +_if2dtb12 .EQU 0x00C254 +IF2DTB12 .EQU 0x00C254 +_if2dtb22 .EQU 0x00C256 +IF2DTB22 .EQU 0x00C256 +_if2dta_swp122 .EQU 0x00C260 +IF2DTA_SWP122 .EQU 0x00C260 +_if2dta_swp22 .EQU 0x00C260 +IF2DTA_SWP22 .EQU 0x00C260 +_if2dta_swp12 .EQU 0x00C262 +IF2DTA_SWP12 .EQU 0x00C262 +_if2dtb_swp122 .EQU 0x00C264 +IF2DTB_SWP122 .EQU 0x00C264 +_if2dtb_swp22 .EQU 0x00C264 +IF2DTB_SWP22 .EQU 0x00C264 +_if2dtb_swp12 .EQU 0x00C266 +IF2DTB_SWP12 .EQU 0x00C266 +_treqr122 .EQU 0x00C280 +TREQR122 .EQU 0x00C280 /* CAN 2 Status Flags */ +_treqr22 .EQU 0x00C280 +TREQR22 .EQU 0x00C280 +_treqr12 .EQU 0x00C282 +TREQR12 .EQU 0x00C282 +_newdt122 .EQU 0x00C290 +NEWDT122 .EQU 0x00C290 +_newdt22 .EQU 0x00C290 +NEWDT22 .EQU 0x00C290 +_newdt12 .EQU 0x00C292 +NEWDT12 .EQU 0x00C292 +_intpnd122 .EQU 0x00C2A0 +INTPND122 .EQU 0x00C2A0 +_intpnd22 .EQU 0x00C2A0 +INTPND22 .EQU 0x00C2A0 +_intpnd12 .EQU 0x00C2A2 +INTPND12 .EQU 0x00C2A2 +_msgval122 .EQU 0x00C2B0 +MSGVAL122 .EQU 0x00C2B0 +_msgval22 .EQU 0x00C2B0 +MSGVAL22 .EQU 0x00C2B0 +_msgval12 .EQU 0x00C2B2 +MSGVAL12 .EQU 0x00C2B2 +_bctrl .EQU 0x00F000 +BCTRL .EQU 0x00F000 /* EDSU/MPU Registers */ +_bstat .EQU 0x00F004 +BSTAT .EQU 0x00F004 +_biac .EQU 0x00F008 +BIAC .EQU 0x00F008 +_boac .EQU 0x00F00C +BOAC .EQU 0x00F00C +_birq .EQU 0x00F010 +BIRQ .EQU 0x00F010 +_bcr0 .EQU 0x00F020 +BCR0 .EQU 0x00F020 +_bcr1 .EQU 0x00F024 +BCR1 .EQU 0x00F024 +_bcr2 .EQU 0x00F028 +BCR2 .EQU 0x00F028 +_bcr3 .EQU 0x00F02C +BCR3 .EQU 0x00F02C +_bcr4 .EQU 0x00F030 +BCR4 .EQU 0x00F030 +_bcr5 .EQU 0x00F034 +BCR5 .EQU 0x00F034 +_bcr6 .EQU 0x00F038 +BCR6 .EQU 0x00F038 +_bcr7 .EQU 0x00F03C +BCR7 .EQU 0x00F03C +_bad0 .EQU 0x00F080 +BAD0 .EQU 0x00F080 +_bad1 .EQU 0x00F084 +BAD1 .EQU 0x00F084 +_bad2 .EQU 0x00F088 +BAD2 .EQU 0x00F088 +_bad3 .EQU 0x00F08C +BAD3 .EQU 0x00F08C +_bad4 .EQU 0x00F090 +BAD4 .EQU 0x00F090 +_bad5 .EQU 0x00F094 +BAD5 .EQU 0x00F094 +_bad6 .EQU 0x00F098 +BAD6 .EQU 0x00F098 +_bad7 .EQU 0x00F09C +BAD7 .EQU 0x00F09C +_bad8 .EQU 0x00F0A0 +BAD8 .EQU 0x00F0A0 +_bad9 .EQU 0x00F0A4 +BAD9 .EQU 0x00F0A4 +_bad10 .EQU 0x00F0A8 +BAD10 .EQU 0x00F0A8 +_bad11 .EQU 0x00F0AC +BAD11 .EQU 0x00F0AC +_bad12 .EQU 0x00F0B0 +BAD12 .EQU 0x00F0B0 +_bad13 .EQU 0x00F0B4 +BAD13 .EQU 0x00F0B4 +_bad14 .EQU 0x00F0B8 +BAD14 .EQU 0x00F0B8 +_bad15 .EQU 0x00F0BC +BAD15 .EQU 0x00F0BC +_fsv1 .EQU 0x148000 +FSV1 .EQU 0x148000 /* FSV & BSV Registers */ +_bsv1 .EQU 0x148004 +BSV1 .EQU 0x148004 +_fsv2 .EQU 0x148008 +FSV2 .EQU 0x148008 +_bsv2 .EQU 0x14800C +BSV2 .EQU 0x14800C +#pragma endasm +#else + +#ifndef _MB91XXX_H +#define _MB91XXX_H + +#ifdef __FASM__ +#pragma asm + .IMPORT _pdr00, _pdr01, _pdr02, _pdr03, _pdr04, _pdr05 + .IMPORT _pdr06, _pdr07, _pdr08, _pdr09, _pdr10, _pdr13 + .IMPORT _pdr14, _pdr15, _pdr16, _pdr17, _pdr18, _pdr19 + .IMPORT _pdr20, _pdr22, _pdr23, _pdr24, _pdr25, _pdr26 + .IMPORT _pdr27, _pdr29, _eirr0, _enir0, _elvr0, _eirr1 + .IMPORT _enir1, _elvr1, _dicr, _hrcl, _rbsync, _scr02 + .IMPORT _smr02, _ssr02, _rdr02, _tdr02, _escr02, _eccr02 + .IMPORT _scr04, _smr04, _ssr04, _rdr04, _tdr04, _escr04 + .IMPORT _eccr04, _fsr04, _fcr04, _scr05, _smr05, _ssr05 + .IMPORT _rdr05, _tdr05, _escr05, _eccr05, _fsr05, _fcr05 + .IMPORT _scr06, _smr06, _ssr06, _rdr06, _tdr06, _escr06 + .IMPORT _eccr06, _fsr06, _fcr06, _scr07, _smr07, _ssr07 + .IMPORT _rdr07, _tdr07, _escr07, _eccr07, _fsr07, _fcr07 + .IMPORT _bgr02, _bgr102, _bgr002, _bgr04, _bgr104, _bgr004 + .IMPORT _bgr05, _bgr105, _bgr005, _bgr06, _bgr106, _bgr006 + .IMPORT _bgr07, _bgr107, _bgr007, _pwc20, _pwc10, _pws20 + .IMPORT _pws10, _pwc21, _pwc11, _pws21, _pws11, _pwc22 + .IMPORT _pwc12, _pws22, _pws12, _pwc23, _pwc13, _pws23 + .IMPORT _pws13, _pwc24, _pwc14, _pws24, _pws14, _pwc25 + .IMPORT _pwc15, _pws25, _pws15, _pwc0, _pwc1, _pwc2 + .IMPORT _pwc3, _pwc4, _pwc5, _ibcr0, _ibsr0, _itba0 + .IMPORT _itbah0, _itbal0, _itmk0, _itmkh0, _itmkl0, _ismk0 + .IMPORT _isba0, _idar0, _iccr0, _gcn11, _gcn21, _gcn12 + .IMPORT _gcn22, _ptmr04, _pcsr04, _pdut04, _pcn04, _pcnh04 + .IMPORT _pcnl04, _ptmr05, _pcsr05, _pdut05, _pcn05, _pcnh05 + .IMPORT _pcnl05, _ptmr06, _pcsr06, _pdut06, _pcn06, _pcnh06 + .IMPORT _pcnl06, _ptmr07, _pcsr07, _pdut07, _pcn07, _pcnh07 + .IMPORT _pcnl07, _ptmr08, _pcsr08, _pdut08, _pcn08, _pcnh08 + .IMPORT _pcnl08, _ptmr09, _pcsr09, _pdut09, _pcn09, _pcnh09 + .IMPORT _pcnl09, _ptmr10, _pcsr10, _pdut10, _pcn10, _pcnh10 + .IMPORT _pcnl10, _ptmr11, _pcsr11, _pdut11, _pcn11, _pcnh11 + .IMPORT _pcnl11, _p0tmcsr, _p0tmcsrh, _p0tmcsrl, _p1tmcsr, _p1tmcsrh + .IMPORT _p1tmcsrl, _p0tmrlr, _p0tmr, _p1tmrlr, _p1tmr, _ics01 + .IMPORT _ics23, _ipcp0, _ipcp1, _ipcp2, _ipcp3, _ocs01 + .IMPORT _ocs23, _occp0, _occp1, _occp2, _occp3, _sgcr + .IMPORT _sgcrh, _sgcrl, _sgfr, _sgar, _sgtr, _sgdr + .IMPORT _aderh, _aderl, _ader, _adcs1, _adcs0, _adcs + .IMPORT _adcr1, _adcr0, _adcr, _adct1, _adct0, _adct + .IMPORT _adsch, _adech, _acsr0, _tmrlr0, _tmr0, _tmcsr0 + .IMPORT _tmcsrh0, _tmcsrl0, _tmrlr1, _tmr1, _tmcsr1, _tmcsrh1 + .IMPORT _tmcsrl1, _tmrlr2, _tmr2, _tmcsr2, _tmcsrh2, _tmcsrl2 + .IMPORT _tmrlr3, _tmr3, _tmcsr3, _tmcsrh3, _tmcsrl3, _tmrlr4 + .IMPORT _tmr4, _tmcsr4, _tmcsrh4, _tmcsrl4, _tmrlr5, _tmr5 + .IMPORT _tmcsr5, _tmcsrh5, _tmcsrl5, _tmrlr6, _tmr6, _tmcsr6 + .IMPORT _tmcsrh6, _tmcsrl6, _tmrlr7, _tmr7, _tmcsr7, _tmcsrh7 + .IMPORT _tmcsrl7, _tcdt0, _tccs0, _tcdt1, _tccs1, _tcdt2 + .IMPORT _tccs2, _tcdt3, _tccs3, _dmaca0, _dmacb0, _dmaca1 + .IMPORT _dmacb1, _dmaca2, _dmacb2, _dmaca3, _dmacb3, _dmaca4 + .IMPORT _dmacb4, _dmacr, _ics45, _ics67, _ipcp4, _ipcp5 + .IMPORT _ipcp6, _ipcp7, _tcdt4, _tccs4, _tcdt5, _tccs5 + .IMPORT _tcdt6, _tccs6, _tcdt7, _tccs7, _udrc10, _udrc1 + .IMPORT _udrc0, _udcr10, _udcr1, _udcr0, _udcc0, _udcch0 + .IMPORT _udccl0, _udcs0, _udcc1, _udcch1, _udccl1, _udcs1 + .IMPORT _udrc32, _udrc3, _udrc2, _udcr32, _udcr3, _udcr2 + .IMPORT _udcc2, _udcch2, _udccl2, _udcs2, _udcc3, _udcch3 + .IMPORT _udccl3, _udcs3, _gcn13, _gcn23, _ptmr12, _pcsr12 + .IMPORT _pdut12, _pcn12, _pcnh12, _pcnl12, _ptmr13, _pcsr13 + .IMPORT _pdut13, _pcn13, _pcnh13, _pcnl13, _ptmr14, _pcsr14 + .IMPORT _pdut14, _pcn14, _pcnh14, _pcnl14, _ptmr15, _pcsr15 + .IMPORT _pdut15, _pcn15, _pcnh15, _pcnl15, _ibcr2, _ibsr2 + .IMPORT _itba2, _itbah2, _itbal2, _itmk2, _itmkh2, _itmkl2 + .IMPORT _ismk2, _isba2, _idar2, _iccr2, _ibcr3, _ibsr3 + .IMPORT _itba3, _itbah3, _itbal3, _itmk3, _itmkh3, _itmkl3 + .IMPORT _ismk3, _isba3, _idar3, _iccr3, _roms, _bsd0 + .IMPORT _bsd1, _bsdc, _bsrr, _icr00, _icr01, _icr02 + .IMPORT _icr03, _icr04, _icr05, _icr06, _icr07, _icr08 + .IMPORT _icr09, _icr10, _icr11, _icr12, _icr13, _icr14 + .IMPORT _icr15, _icr16, _icr17, _icr18, _icr19, _icr20 + .IMPORT _icr21, _icr22, _icr23, _icr24, _icr25, _icr26 + .IMPORT _icr27, _icr28, _icr29, _icr30, _icr31, _icr32 + .IMPORT _icr33, _icr34, _icr35, _icr36, _icr37, _icr38 + .IMPORT _icr39, _icr40, _icr41, _icr42, _icr43, _icr44 + .IMPORT _icr45, _icr46, _icr47, _icr48, _icr49, _icr50 + .IMPORT _icr51, _icr52, _icr53, _icr54, _icr55, _icr56 + .IMPORT _icr57, _icr58, _icr59, _icr60, _icr61, _icr62 + .IMPORT _icr63, _rsrr, _stcr, _tbcr, _ctbr, _clkr + .IMPORT _wpr, _divr0, _divr1, _plldivm, _plldivn, _plldivg + .IMPORT _pllmulg, _pllctrl, _oscc1, _oscs1, _oscc2, _oscs2 + .IMPORT _porten, _wtcer, _wtcr, _wtbr, _wthr, _wtmr + .IMPORT _wtsr, _csvtr, _csvcr, _cscfg, _cmcfg, _cucr + .IMPORT _cutd, _cutr1, _cutr2, _cmpr, _cmcr, _cmt1 + .IMPORT _cmt2, _canpre, _canckd, _lvsel, _lvdet, _hwwde + .IMPORT _hwwd, _oscrh, _oscrl, _wpcrh, _wpcrl, _osccr + .IMPORT _regsel, _regctr, _asr0, _acr0, _asr1, _acr1 + .IMPORT _asr2, _acr2, _asr3, _acr3, _asr4, _acr4 + .IMPORT _asr5, _acr5, _asr6, _acr6, _asr7, _acr7 + .IMPORT _awr0, _awr1, _awr2, _awr3, _awr4, _awr5 + .IMPORT _awr6, _awr7, _mcra, _mcrb, _iowr0, _iowr1 + .IMPORT _iowr2, _iowr3, _cser, _cher, _tcr, _rcr + .IMPORT _modr, _pdrd00, _pdrd01, _pdrd02, _pdrd03, _pdrd04 + .IMPORT _pdrd05, _pdrd06, _pdrd07, _pdrd08, _pdrd09, _pdrd10 + .IMPORT _pdrd13, _pdrd14, _pdrd15, _pdrd16, _pdrd17, _pdrd18 + .IMPORT _pdrd19, _pdrd20, _pdrd22, _pdrd23, _pdrd24, _pdrd25 + .IMPORT _pdrd26, _pdrd27, _pdrd29, _ddr00, _ddr01, _ddr02 + .IMPORT _ddr03, _ddr04, _ddr05, _ddr06, _ddr07, _ddr08 + .IMPORT _ddr09, _ddr10, _ddr13, _ddr14, _ddr15, _ddr16 + .IMPORT _ddr17, _ddr18, _ddr19, _ddr20, _ddr22, _ddr23 + .IMPORT _ddr24, _ddr25, _ddr26, _ddr27, _ddr29, _pfr00 + .IMPORT _pfr01, _pfr02, _pfr03, _pfr04, _pfr05, _pfr06 + .IMPORT _pfr07, _pfr08, _pfr09, _pfr10, _pfr13, _pfr14 + .IMPORT _pfr15, _pfr16, _pfr17, _pfr18, _pfr19, _pfr20 + .IMPORT _pfr22, _pfr23, _pfr24, _pfr25, _pfr26, _pfr27 + .IMPORT _pfr29, _epfr10, _epfr13, _epfr14, _epfr15, _epfr16 + .IMPORT _epfr18, _epfr19, _epfr20, _epfr26, _epfr27, _podr00 + .IMPORT _podr01, _podr02, _podr03, _podr04, _podr05, _podr06 + .IMPORT _podr07, _podr08, _podr09, _podr10, _podr13, _podr14 + .IMPORT _podr15, _podr16, _podr17, _podr18, _podr19, _podr20 + .IMPORT _podr22, _podr23, _podr24, _podr25, _podr26, _podr27 + .IMPORT _podr29, _pilr00, _pilr01, _pilr02, _pilr03, _pilr04 + .IMPORT _pilr05, _pilr06, _pilr07, _pilr08, _pilr09, _pilr10 + .IMPORT _pilr13, _pilr14, _pilr15, _pilr16, _pilr17, _pilr18 + .IMPORT _pilr19, _pilr20, _pilr22, _pilr23, _pilr24, _pilr25 + .IMPORT _pilr26, _pilr27, _pilr29, _epilr00, _epilr01, _epilr02 + .IMPORT _epilr03, _epilr04, _epilr05, _epilr06, _epilr07, _epilr08 + .IMPORT _epilr09, _epilr10, _epilr13, _epilr14, _epilr15, _epilr16 + .IMPORT _epilr17, _epilr18, _epilr19, _epilr20, _epilr22, _epilr23 + .IMPORT _epilr24, _epilr25, _epilr26, _epilr27, _epilr29, _pper00 + .IMPORT _pper01, _pper02, _pper03, _pper04, _pper05, _pper06 + .IMPORT _pper07, _pper08, _pper09, _pper10, _pper13, _pper14 + .IMPORT _pper15, _pper16, _pper17, _pper18, _pper19, _pper20 + .IMPORT _pper22, _pper23, _pper24, _pper25, _pper26, _pper27 + .IMPORT _pper29, _ppcr00, _ppcr01, _ppcr02, _ppcr03, _ppcr04 + .IMPORT _ppcr05, _ppcr06, _ppcr07, _ppcr08, _ppcr09, _ppcr10 + .IMPORT _ppcr13, _ppcr14, _ppcr15, _ppcr16, _ppcr17, _ppcr18 + .IMPORT _ppcr19, _ppcr20, _ppcr22, _ppcr23, _ppcr24, _ppcr25 + .IMPORT _ppcr26, _ppcr27, _ppcr29, _dmasa0, _dmada0, _dmasa1 + .IMPORT _dmada1, _dmasa2, _dmada2, _dmasa3, _dmada3, _dmasa4 + .IMPORT _dmada4, _fmcs, _fmcr, _fchcr, _fmwt, _fmwt2 + .IMPORT _fmps, _fmac, _fcha0, _fcha1, _fscr0, _fscr1 + .IMPORT _ctrlr0, _statr0, _errcnt0, _btr0, _intr0, _testr0 + .IMPORT _brper0, _brpe0, _cbsync0, _if1creq0, _if1cmsk0, _if1msk120 + .IMPORT _if1msk20, _if1msk10, _if1arb120, _if1arb20, _if1arb10, _if1mctr0 + .IMPORT _if1dta120, _if1dta10, _if1dta20, _if1dtb120, _if1dtb10, _if1dtb20 + .IMPORT _if1dta_swp120, _if1dta_swp20, _if1dta_swp10, _if1dtb_swp120, _if1dtb_swp20, _if1dtb_swp10 + .IMPORT _if2creq0, _if2cmsk0, _if2msk120, _if2msk20, _if2msk10, _if2arb120 + .IMPORT _if2arb20, _if2arb10, _if2mctr0, _if2dta120, _if2dta10, _if2dta20 + .IMPORT _if2dtb120, _if2dtb10, _if2dtb20, _if2dta_swp120, _if2dta_swp20, _if2dta_swp10 + .IMPORT _if2dtb_swp120, _if2dtb_swp20, _if2dtb_swp10, _treqr120, _treqr20, _treqr10 + .IMPORT _newdt120, _newdt20, _newdt10, _intpnd120, _intpnd20, _intpnd10 + .IMPORT _msgval120, _msgval20, _msgval10, _msgval340, _ctrlr1, _statr1 + .IMPORT _errcnt1, _btr1, _intr1, _testr1, _brper1, _brpe1 + .IMPORT _cbsync1, _if1creq1, _if1cmsk1, _if1msk121, _if1msk21, _if1msk11 + .IMPORT _if1arb121, _if1arb21, _if1arb11, _if1mctr1, _if1dta121, _if1dta11 + .IMPORT _if1dta21, _if1dtb121, _if1dtb11, _if1dtb21, _if1dta_swp121, _if1dta_swp21 + .IMPORT _if1dta_swp11, _if1dtb_swp121, _if1dtb_swp21, _if1dtb_swp11, _if2creq1, _if2cmsk1 + .IMPORT _if2msk121, _if2msk21, _if2msk11, _if2arb121, _if2arb21, _if2arb11 + .IMPORT _if2mctr1, _if2dta121, _if2dta11, _if2dta21, _if2dtb121, _if2dtb11 + .IMPORT _if2dtb21, _if2dta_swp121, _if2dta_swp21, _if2dta_swp11, _if2dtb_swp121, _if2dtb_swp21 + .IMPORT _if2dtb_swp11, _treqr121, _treqr21, _treqr11, _newdt121, _newdt21 + .IMPORT _newdt11, _intpnd121, _intpnd21, _intpnd11, _msgval121, _msgval21 + .IMPORT _msgval11, _ctrlr2, _statr2, _errcnt2, _btr2, _intr2 + .IMPORT _testr2, _brper2, _brpe2, _cbsync2, _if1creq2, _if1cmsk2 + .IMPORT _if1msk122, _if1msk22, _if1msk12, _if1arb122, _if1arb22, _if1arb12 + .IMPORT _if1mctr2, _if1dta122, _if1dta12, _if1dta22, _if1dtb122, _if1dtb12 + .IMPORT _if1dtb22, _if1dta_swp122, _if1dta_swp22, _if1dta_swp12, _if1dtb_swp122, _if1dtb_swp22 + .IMPORT _if1dtb_swp12, _if2creq2, _if2cmsk2, _if2msk122, _if2msk22, _if2msk12 + .IMPORT _if2arb122, _if2arb22, _if2arb12, _if2mctr2, _if2dta122, _if2dta12 + .IMPORT _if2dta22, _if2dtb122, _if2dtb12, _if2dtb22, _if2dta_swp122, _if2dta_swp22 + .IMPORT _if2dta_swp12, _if2dtb_swp122, _if2dtb_swp22, _if2dtb_swp12, _treqr122, _treqr22 + .IMPORT _treqr12, _newdt122, _newdt22, _newdt12, _intpnd122, _intpnd22 + .IMPORT _intpnd12, _msgval122, _msgval22, _msgval12, _bctrl, _bstat + .IMPORT _biac, _boac, _birq, _bcr0, _bcr1, _bcr2 + .IMPORT _bcr3, _bcr4, _bcr5, _bcr6, _bcr7, _bad0 + .IMPORT _bad1, _bad2, _bad3, _bad4, _bad5, _bad6 + .IMPORT _bad7, _bad8, _bad9, _bad10, _bad11, _bad12 + .IMPORT _bad13, _bad14, _bad15, _fsv1, _bsv1, _fsv2 + .IMPORT _bsv2 +#pragma endasm +#else /* __FASM__ */ +/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ +/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ +/* ELIGIBILITY FOR ANY PURPOSES. */ +/* (C) Fujitsu Microelectronics Europe GmbH */ +/* */ +/* ************************************************************************* */ +/* Fujitsu Microelectronics Europe GmbH */ +/* http://emea.fujitsu.com/microelectronics */ +/* */ +/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ +/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ +/* ELIGIBILITY FOR ANY PURPOSES */ +/* (C) Fujitsu Microelectronics Europe GmbH */ +/* ************************************************************************* */ +/* ---------------------------------------------------------------------- */ +/* $Id: mb91467D.h,v 1.13 2007/08/08 10:56:26 mwilla Exp $ */ +/* ---------------------------------------------------------------------- */ +/* */ +/* Id: mb91467D.iow,v 1.1 2005/10/14 11:25:42 umarke Exp */ +/* - Initial Version based on mb91V460A, v1.1 */ +/* Id: mb91467D.iow,v 1.2 2005/10/14 09:47:18 umarke Exp */ +/* - Littel Endian IFxDTA_SWP_yz added */ +/* Id: mb91467D.iow,v 1.3 2005/11/18 06:55:29 umarke Exp */ +/* - No. of port register reduced to the no. of registers in MB91467D */ +/* - Registers added: FMWT2, FMCR */ +/* - Addapted Bit Names of Register FMCS */ +/* Id: mb91467D.iow,v 1.4 2005/11/18 06:55:29 umarke Exp */ +/* - OCS01 and OCS23 added */ +/* Id: mb91467D.iow,v 1.6 2006/01/13 08:58:51 umarke Exp */ +/* - Bitnames of CLKR changed */ +/* Id: mb91467D.iow,v 1.7 2006/01/26 15:42:05 umarke Exp */ +/* - REGSEL, BRPERx added */ +/* - REGCTR added */ +/* - LVSEL added */ +/* - Old Bitname of CLKR added */ +/* Id: mb91467D.iow,v 1.8 2006/02/27 10:31:28 umarke Exp */ +/* - BGR10x und BGR00x added */ +/* - PCNx, ITBAx, ITMKx, IDARx_D7 added */ +/* - SGCRH, SGCRL added */ +/* - Bit ACSR_MD added */ +/* - Bit CSCFG_PLLLOCK and CSCFG_RCSEL */ +/* - CUCR: Bits shifted to correct position */ +/* - CUTR1 & CUTR2 bits renamed to TDR14 instead of TR14 */ +/* - CMCR_RUN renamed to CMCR_FMODRUN and shifted */ +/* - Bitnames of OSCCx and OSCRx added */ +/* - FSVx, BSVx and FSCRx added */ +/* - RBSYNC, CBSYNCx */ +/* Id: mb91467D.iow,v 1.9 2006/02/27 11:56:23 umarke Exp */ +/* - changed Adress of REGSEL */ +/* $Id: mb91467D.h,v 1.13 2007/08/08 10:56:26 mwilla Exp $ */ +/* - Grouped CANPRE_CPCKS */ +/* - Bitdescription of HLRC added */ +/* BIT-STRUCTURE-DEFINITIONS */ + +typedef unsigned char IO_BYTE; +typedef unsigned short IO_WORD; +typedef unsigned long IO_LWORD; +typedef const unsigned short IO_WORD_READ; + +typedef union{ /* Port Data Register */ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDR00STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDR01STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDR02STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDR03STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDR04STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDR05STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDR06STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDR07STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDR08STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDR09STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE :1; + }bit; + }PDR10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDR13STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDR14STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDR15STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDR16STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }PDR17STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDR18STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDR19STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDR20STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE :1; + IO_BYTE _D0 :1; + }bit; + }PDR22STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDR23STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDR24STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDR25STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDR26STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDR27STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDR29STR; +typedef union{ /* External Interrupt 0-7 */ + IO_BYTE byte; + struct{ + IO_BYTE _ER7 :1; + IO_BYTE _ER6 :1; + IO_BYTE _ER5 :1; + IO_BYTE _ER4 :1; + IO_BYTE _ER3 :1; + IO_BYTE _ER2 :1; + IO_BYTE _ER1 :1; + IO_BYTE _ER0 :1; + }bit; + }EIRR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EN7 :1; + IO_BYTE _EN6 :1; + IO_BYTE _EN5 :1; + IO_BYTE _EN4 :1; + IO_BYTE _EN3 :1; + IO_BYTE _EN2 :1; + IO_BYTE _EN1 :1; + IO_BYTE _EN0 :1; + }bit; + }ENIR0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _LB7 :1; + IO_WORD _LA7 :1; + IO_WORD _LB6 :1; + IO_WORD _LA6 :1; + IO_WORD _LB5 :1; + IO_WORD _LA5 :1; + IO_WORD _LB4 :1; + IO_WORD _LA4 :1; + IO_WORD _LB3 :1; + IO_WORD _LA3 :1; + IO_WORD _LB2 :1; + IO_WORD _LA2 :1; + IO_WORD _LB1 :1; + IO_WORD _LA1 :1; + IO_WORD _LB0 :1; + IO_WORD _LA0 :1; + }bit; + }ELVR0STR; +typedef union{ /* External Interrupt 8-15 */ + IO_BYTE byte; + struct{ + IO_BYTE _ER15 :1; + IO_BYTE _ER14 :1; + IO_BYTE _ER13 :1; + IO_BYTE _ER12 :1; + IO_BYTE _ER11 :1; + IO_BYTE _ER10 :1; + IO_BYTE _ER9 :1; + IO_BYTE _ER8 :1; + }bit; + }EIRR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EN15 :1; + IO_BYTE _EN14 :1; + IO_BYTE _EN13 :1; + IO_BYTE _EN12 :1; + IO_BYTE _EN11 :1; + IO_BYTE _EN10 :1; + IO_BYTE _EN9 :1; + IO_BYTE _EN8 :1; + }bit; + }ENIR1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _LB15 :1; + IO_WORD _LA15 :1; + IO_WORD _LB14 :1; + IO_WORD _LA14 :1; + IO_WORD _LB13 :1; + IO_WORD _LA13 :1; + IO_WORD _LB12 :1; + IO_WORD _LA12 :1; + IO_WORD _LB11 :1; + IO_WORD _LA11 :1; + IO_WORD _LB10 :1; + IO_WORD _LA10 :1; + IO_WORD _LB9 :1; + IO_WORD _LA9 :1; + IO_WORD _LB8 :1; + IO_WORD _LA8 :1; + }bit; + }ELVR1STR; +typedef union{ /* DLYI/I-unit */ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _DLYI :1; + }bit; + }DICRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MHALTI :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _LVL4 :1; + IO_BYTE _LVL3 :1; + IO_BYTE _LVL2 :1; + IO_BYTE _LVL1 :1; + IO_BYTE _LVL0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _LVL :5; + }bitc; + }HRCLSTR; +typedef union{ /* USART (LIN) 2 */ + IO_BYTE byte; + struct{ + IO_BYTE _PEN :1; + IO_BYTE _P :1; + IO_BYTE _SBL :1; + IO_BYTE _CL :1; + IO_BYTE _AD :1; + IO_BYTE _CRE :1; + IO_BYTE _RXE :1; + IO_BYTE _TXE :1; + }bit; + }SCR02STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MD1 :1; + IO_BYTE _MD0 :1; + IO_BYTE _OTO :1; + IO_BYTE _EXT :1; + IO_BYTE _REST :1; + IO_BYTE _UPCL :1; + IO_BYTE _SCKE :1; + IO_BYTE _SOE :1; + }bit; + struct{ + IO_BYTE _MD :2; + }bitc; + }SMR02STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PE :1; + IO_BYTE _ORE :1; + IO_BYTE _FRE :1; + IO_BYTE _RDRF :1; + IO_BYTE _TDRE :1; + IO_BYTE _BDS :1; + IO_BYTE _RIE :1; + IO_BYTE _TIE :1; + }bit; + }SSR02STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _LBIE :1; + IO_BYTE _LBD :1; + IO_BYTE _LBL1 :1; + IO_BYTE _LBL0 :1; + IO_BYTE _SOPE :1; + IO_BYTE _SIOP :1; + IO_BYTE _CCO :1; + IO_BYTE _SCES :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _LBL :2; + }bitc; + }ESCR02STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INV :1; + IO_BYTE _LBR :1; + IO_BYTE _MS :1; + IO_BYTE _SCDE :1; + IO_BYTE _SSM :1; + IO_BYTE _BIE :1; + IO_BYTE _RBI :1; + IO_BYTE _TBI :1; + }bit; + }ECCR02STR; +typedef union{ /* USART (LIN) 4 with FIFO */ + IO_BYTE byte; + struct{ + IO_BYTE _PEN :1; + IO_BYTE _P :1; + IO_BYTE _SBL :1; + IO_BYTE _CL :1; + IO_BYTE _AD :1; + IO_BYTE _CRE :1; + IO_BYTE _RXE :1; + IO_BYTE _TXE :1; + }bit; + }SCR04STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MD1 :1; + IO_BYTE _MD0 :1; + IO_BYTE _OTO :1; + IO_BYTE _EXT :1; + IO_BYTE _REST :1; + IO_BYTE _UPCL :1; + IO_BYTE _SCKE :1; + IO_BYTE _SOE :1; + }bit; + struct{ + IO_BYTE _MD :2; + }bitc; + }SMR04STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PE :1; + IO_BYTE _ORE :1; + IO_BYTE _FRE :1; + IO_BYTE _RDRF :1; + IO_BYTE _TDRE :1; + IO_BYTE _BDS :1; + IO_BYTE _RIE :1; + IO_BYTE _TIE :1; + }bit; + }SSR04STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _LBIE :1; + IO_BYTE _LBD :1; + IO_BYTE _LBL1 :1; + IO_BYTE _LBL0 :1; + IO_BYTE _SOPE :1; + IO_BYTE _SIOP :1; + IO_BYTE _CCO :1; + IO_BYTE _SCES :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _LBL :2; + }bitc; + }ESCR04STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INV :1; + IO_BYTE _LBR :1; + IO_BYTE _MS :1; + IO_BYTE _SCDE :1; + IO_BYTE _SSM :1; + IO_BYTE _BIE :1; + IO_BYTE _RBI :1; + IO_BYTE _TBI :1; + }bit; + }ECCR04STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _RXL3 :1; + IO_BYTE _RXL2 :1; + IO_BYTE _RXL1 :1; + IO_BYTE _RXL0 :1; + IO_BYTE :1; + IO_BYTE _ERX :1; + IO_BYTE _ETX :1; + IO_BYTE _SVD :1; + }bit; + struct{ + IO_BYTE _RXL :4; + }bitc; + }FCR04STR; +typedef union{ /* USART (LIN) 5 with FIFO */ + IO_BYTE byte; + struct{ + IO_BYTE _PEN :1; + IO_BYTE _P :1; + IO_BYTE _SBL :1; + IO_BYTE _CL :1; + IO_BYTE _AD :1; + IO_BYTE _CRE :1; + IO_BYTE _RXE :1; + IO_BYTE _TXE :1; + }bit; + }SCR05STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MD1 :1; + IO_BYTE _MD0 :1; + IO_BYTE _OTO :1; + IO_BYTE _EXT :1; + IO_BYTE _REST :1; + IO_BYTE _UPCL :1; + IO_BYTE _SCKE :1; + IO_BYTE _SOE :1; + }bit; + struct{ + IO_BYTE _MD :2; + }bitc; + }SMR05STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PE :1; + IO_BYTE _ORE :1; + IO_BYTE _FRE :1; + IO_BYTE _RDRF :1; + IO_BYTE _TDRE :1; + IO_BYTE _BDS :1; + IO_BYTE _RIE :1; + IO_BYTE _TIE :1; + }bit; + }SSR05STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _LBIE :1; + IO_BYTE _LBD :1; + IO_BYTE _LBL1 :1; + IO_BYTE _LBL0 :1; + IO_BYTE _SOPE :1; + IO_BYTE _SIOP :1; + IO_BYTE _CCO :1; + IO_BYTE _SCES :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _LBL :2; + }bitc; + }ESCR05STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INV :1; + IO_BYTE _LBR :1; + IO_BYTE _MS :1; + IO_BYTE _SCDE :1; + IO_BYTE _SSM :1; + IO_BYTE _BIE :1; + IO_BYTE _RBI :1; + IO_BYTE _TBI :1; + }bit; + }ECCR05STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _RXL3 :1; + IO_BYTE _RXL2 :1; + IO_BYTE _RXL1 :1; + IO_BYTE _RXL0 :1; + IO_BYTE :1; + IO_BYTE _ERX :1; + IO_BYTE _ETX :1; + IO_BYTE _SVD :1; + }bit; + struct{ + IO_BYTE _RXL :4; + }bitc; + }FCR05STR; +typedef union{ /* USART (LIN) 6 with FIFO */ + IO_BYTE byte; + struct{ + IO_BYTE _PEN :1; + IO_BYTE _P :1; + IO_BYTE _SBL :1; + IO_BYTE _CL :1; + IO_BYTE _AD :1; + IO_BYTE _CRE :1; + IO_BYTE _RXE :1; + IO_BYTE _TXE :1; + }bit; + }SCR06STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MD1 :1; + IO_BYTE _MD0 :1; + IO_BYTE _OTO :1; + IO_BYTE _EXT :1; + IO_BYTE _REST :1; + IO_BYTE _UPCL :1; + IO_BYTE _SCKE :1; + IO_BYTE _SOE :1; + }bit; + struct{ + IO_BYTE _MD :2; + }bitc; + }SMR06STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PE :1; + IO_BYTE _ORE :1; + IO_BYTE _FRE :1; + IO_BYTE _RDRF :1; + IO_BYTE _TDRE :1; + IO_BYTE _BDS :1; + IO_BYTE _RIE :1; + IO_BYTE _TIE :1; + }bit; + }SSR06STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _LBIE :1; + IO_BYTE _LBD :1; + IO_BYTE _LBL1 :1; + IO_BYTE _LBL0 :1; + IO_BYTE _SOPE :1; + IO_BYTE _SIOP :1; + IO_BYTE _CCO :1; + IO_BYTE _SCES :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _LBL :2; + }bitc; + }ESCR06STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INV :1; + IO_BYTE _LBR :1; + IO_BYTE _MS :1; + IO_BYTE _SCDE :1; + IO_BYTE _SSM :1; + IO_BYTE _BIE :1; + IO_BYTE _RBI :1; + IO_BYTE _TBI :1; + }bit; + }ECCR06STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _RXL3 :1; + IO_BYTE _RXL2 :1; + IO_BYTE _RXL1 :1; + IO_BYTE _RXL0 :1; + IO_BYTE :1; + IO_BYTE _ERX :1; + IO_BYTE _ETX :1; + IO_BYTE _SVD :1; + }bit; + struct{ + IO_BYTE _RXL :4; + }bitc; + }FCR06STR; +typedef union{ /* USART (LIN) 7 with FIFO */ + IO_BYTE byte; + struct{ + IO_BYTE _PEN :1; + IO_BYTE _P :1; + IO_BYTE _SBL :1; + IO_BYTE _CL :1; + IO_BYTE _AD :1; + IO_BYTE _CRE :1; + IO_BYTE _RXE :1; + IO_BYTE _TXE :1; + }bit; + }SCR07STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MD1 :1; + IO_BYTE _MD0 :1; + IO_BYTE _OTO :1; + IO_BYTE _EXT :1; + IO_BYTE _REST :1; + IO_BYTE _UPCL :1; + IO_BYTE _SCKE :1; + IO_BYTE _SOE :1; + }bit; + struct{ + IO_BYTE _MD :2; + }bitc; + }SMR07STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PE :1; + IO_BYTE _ORE :1; + IO_BYTE _FRE :1; + IO_BYTE _RDRF :1; + IO_BYTE _TDRE :1; + IO_BYTE _BDS :1; + IO_BYTE _RIE :1; + IO_BYTE _TIE :1; + }bit; + }SSR07STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _LBIE :1; + IO_BYTE _LBD :1; + IO_BYTE _LBL1 :1; + IO_BYTE _LBL0 :1; + IO_BYTE _SOPE :1; + IO_BYTE _SIOP :1; + IO_BYTE _CCO :1; + IO_BYTE _SCES :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _LBL :2; + }bitc; + }ESCR07STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INV :1; + IO_BYTE _LBR :1; + IO_BYTE _MS :1; + IO_BYTE _SCDE :1; + IO_BYTE _SSM :1; + IO_BYTE _BIE :1; + IO_BYTE _RBI :1; + IO_BYTE _TBI :1; + }bit; + }ECCR07STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _RXL3 :1; + IO_BYTE _RXL2 :1; + IO_BYTE _RXL1 :1; + IO_BYTE _RXL0 :1; + IO_BYTE :1; + IO_BYTE _ERX :1; + IO_BYTE _ETX :1; + IO_BYTE _SVD :1; + }bit; + struct{ + IO_BYTE _RXL :4; + }bitc; + }FCR07STR; +typedef union{ /* Stepper Motor 0 */ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }PWC20STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }PWC10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _BS :1; + IO_BYTE _P2 :1; + IO_BYTE _P1 :1; + IO_BYTE _P0 :1; + IO_BYTE _M2 :1; + IO_BYTE _M1 :1; + IO_BYTE _M0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _P :3; + IO_BYTE _M :3; + }bitc; + }PWS20STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _P2 :1; + IO_BYTE _P1 :1; + IO_BYTE _P0 :1; + IO_BYTE _M2 :1; + IO_BYTE _M1 :1; + IO_BYTE _M0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _P :3; + IO_BYTE _M :3; + }bitc; + }PWS10STR; +typedef union{ /* Stepper Motor 1 */ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }PWC21STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }PWC11STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _BS :1; + IO_BYTE _P2 :1; + IO_BYTE _P1 :1; + IO_BYTE _P0 :1; + IO_BYTE _M2 :1; + IO_BYTE _M1 :1; + IO_BYTE _M0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _P :3; + IO_BYTE _M :3; + }bitc; + }PWS21STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _P2 :1; + IO_BYTE _P1 :1; + IO_BYTE _P0 :1; + IO_BYTE _M2 :1; + IO_BYTE _M1 :1; + IO_BYTE _M0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _P :3; + IO_BYTE _M :3; + }bitc; + }PWS11STR; +typedef union{ /* Stepper Motor 2 */ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }PWC22STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }PWC12STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _BS :1; + IO_BYTE _P2 :1; + IO_BYTE _P1 :1; + IO_BYTE _P0 :1; + IO_BYTE _M2 :1; + IO_BYTE _M1 :1; + IO_BYTE _M0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _P :3; + IO_BYTE _M :3; + }bitc; + }PWS22STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _P2 :1; + IO_BYTE _P1 :1; + IO_BYTE _P0 :1; + IO_BYTE _M2 :1; + IO_BYTE _M1 :1; + IO_BYTE _M0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _P :3; + IO_BYTE _M :3; + }bitc; + }PWS12STR; +typedef union{ /* Stepper Motor 3 */ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }PWC23STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }PWC13STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _BS :1; + IO_BYTE _P2 :1; + IO_BYTE _P1 :1; + IO_BYTE _P0 :1; + IO_BYTE _M2 :1; + IO_BYTE _M1 :1; + IO_BYTE _M0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _P :3; + IO_BYTE _M :3; + }bitc; + }PWS23STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _P2 :1; + IO_BYTE _P1 :1; + IO_BYTE _P0 :1; + IO_BYTE _M2 :1; + IO_BYTE _M1 :1; + IO_BYTE _M0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _P :3; + IO_BYTE _M :3; + }bitc; + }PWS13STR; +typedef union{ /* Stepper Motor 4 */ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }PWC24STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }PWC14STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _BS :1; + IO_BYTE _P2 :1; + IO_BYTE _P1 :1; + IO_BYTE _P0 :1; + IO_BYTE _M2 :1; + IO_BYTE _M1 :1; + IO_BYTE _M0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _P :3; + IO_BYTE _M :3; + }bitc; + }PWS24STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _P2 :1; + IO_BYTE _P1 :1; + IO_BYTE _P0 :1; + IO_BYTE _M2 :1; + IO_BYTE _M1 :1; + IO_BYTE _M0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _P :3; + IO_BYTE _M :3; + }bitc; + }PWS14STR; +typedef union{ /* Stepper Motor 5 */ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }PWC25STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }PWC15STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _BS :1; + IO_BYTE _P2 :1; + IO_BYTE _P1 :1; + IO_BYTE _P0 :1; + IO_BYTE _M2 :1; + IO_BYTE _M1 :1; + IO_BYTE _M0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _P :3; + IO_BYTE _M :3; + }bitc; + }PWS25STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _P2 :1; + IO_BYTE _P1 :1; + IO_BYTE _P0 :1; + IO_BYTE _M2 :1; + IO_BYTE _M1 :1; + IO_BYTE _M0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _P :3; + IO_BYTE _M :3; + }bitc; + }PWS15STR; +typedef union{ /* Stepper Motor Control 0-5 */ + IO_BYTE byte; + struct{ + IO_BYTE _S2 :1; + IO_BYTE _P2 :1; + IO_BYTE _P1 :1; + IO_BYTE _P0 :1; + IO_BYTE _CE :1; + IO_BYTE _SC :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE _P :3; + }bitc; + }PWC0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _S2 :1; + IO_BYTE _P2 :1; + IO_BYTE _P1 :1; + IO_BYTE _P0 :1; + IO_BYTE _CE :1; + IO_BYTE _SC :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE _P :3; + }bitc; + }PWC1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _S2 :1; + IO_BYTE _P2 :1; + IO_BYTE _P1 :1; + IO_BYTE _P0 :1; + IO_BYTE _CE :1; + IO_BYTE _SC :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE _P :3; + }bitc; + }PWC2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _S2 :1; + IO_BYTE _P2 :1; + IO_BYTE _P1 :1; + IO_BYTE _P0 :1; + IO_BYTE _CE :1; + IO_BYTE _SC :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE _P :3; + }bitc; + }PWC3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _S2 :1; + IO_BYTE _P2 :1; + IO_BYTE _P1 :1; + IO_BYTE _P0 :1; + IO_BYTE _CE :1; + IO_BYTE _SC :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE _P :3; + }bitc; + }PWC4STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _S2 :1; + IO_BYTE _P2 :1; + IO_BYTE _P1 :1; + IO_BYTE _P0 :1; + IO_BYTE _CE :1; + IO_BYTE _SC :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE _P :3; + }bitc; + }PWC5STR; +typedef union{ /* I2C 0 */ + IO_BYTE byte; + struct{ + IO_BYTE _BER :1; + IO_BYTE _BEIE :1; + IO_BYTE _SCC :1; + IO_BYTE _MSS :1; + IO_BYTE _ACK :1; + IO_BYTE _GCAA :1; + IO_BYTE _INTE :1; + IO_BYTE _INT :1; + }bit; + }IBCR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _BB :1; + IO_BYTE _RSC :1; + IO_BYTE _AL :1; + IO_BYTE _LRB :1; + IO_BYTE _TRX :1; + IO_BYTE _AAS :1; + IO_BYTE _GCA :1; + IO_BYTE _ADT :1; + }bit; + }IBSR0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _TA9 :1; + IO_WORD _TA8 :1; + IO_WORD _TA7 :1; + IO_WORD _TA6 :1; + IO_WORD _TA5 :1; + IO_WORD _TA4 :1; + IO_WORD _TA3 :1; + IO_WORD _TA2 :1; + IO_WORD _TA1 :1; + IO_WORD _TA0 :1; + }bit; + }ITBA0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _TA9 :1; + IO_BYTE _TA8 :1; + }bit; + }ITBAH0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TA7 :1; + IO_BYTE _TA6 :1; + IO_BYTE _TA5 :1; + IO_BYTE _TA4 :1; + IO_BYTE _TA3 :1; + IO_BYTE _TA2 :1; + IO_BYTE _TA1 :1; + IO_BYTE _TA0 :1; + }bit; + }ITBAL0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _ENTB :1; + IO_WORD _RAL :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _TM9 :1; + IO_WORD _TM8 :1; + IO_WORD _TM7 :1; + IO_WORD _TM6 :1; + IO_WORD _TM5 :1; + IO_WORD _TM4 :1; + IO_WORD _TM3 :1; + IO_WORD _TM2 :1; + IO_WORD _TM1 :1; + IO_WORD _TM0 :1; + }bit; + }ITMK0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ENTB :1; + IO_BYTE _RAL :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _TM9 :1; + IO_BYTE _TM8 :1; + }bit; + }ITMKH0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TM7 :1; + IO_BYTE _TM6 :1; + IO_BYTE _TM5 :1; + IO_BYTE _TM4 :1; + IO_BYTE _TM3 :1; + IO_BYTE _TM2 :1; + IO_BYTE _TM1 :1; + IO_BYTE _TM0 :1; + }bit; + }ITMKL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ENSB :1; + IO_BYTE _SM6 :1; + IO_BYTE _SM5 :1; + IO_BYTE _SM4 :1; + IO_BYTE _SM3 :1; + IO_BYTE _SM2 :1; + IO_BYTE _SM1 :1; + IO_BYTE _SM0 :1; + }bit; + }ISMK0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _SA6 :1; + IO_BYTE _SA5 :1; + IO_BYTE _SA4 :1; + IO_BYTE _SA3 :1; + IO_BYTE _SA2 :1; + IO_BYTE _SA1 :1; + IO_BYTE _SA0 :1; + }bit; + }ISBA0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }IDAR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _NSF :1; + IO_BYTE _EN :1; + IO_BYTE _CS4 :1; + IO_BYTE _CS3 :1; + IO_BYTE _CS2 :1; + IO_BYTE _CS1 :1; + IO_BYTE _CS0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CS :5; + }bitc; + }ICCR0STR; +typedef union{ /* PPG Control 4-7 */ + IO_WORD word; + struct{ + IO_WORD _TSEL33 :1; + IO_WORD _TSEL32 :1; + IO_WORD _TSEL31 :1; + IO_WORD _TSEL30 :1; + IO_WORD _TSEL23 :1; + IO_WORD _TSEL22 :1; + IO_WORD _TSEL21 :1; + IO_WORD _TSEL20 :1; + IO_WORD _TSEL13 :1; + IO_WORD _TSEL12 :1; + IO_WORD _TSEL11 :1; + IO_WORD _TSEL10 :1; + IO_WORD _TSEL03 :1; + IO_WORD _TSEL02 :1; + IO_WORD _TSEL01 :1; + IO_WORD _TSEL00 :1; + }bit; + }GCN11STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _EN3 :1; + IO_BYTE _EN2 :1; + IO_BYTE _EN1 :1; + IO_BYTE _EN0 :1; + }bit; + }GCN21STR; +typedef union{ /* PPG Control 8-11 */ + IO_WORD word; + struct{ + IO_WORD _TSEL33 :1; + IO_WORD _TSEL32 :1; + IO_WORD _TSEL31 :1; + IO_WORD _TSEL30 :1; + IO_WORD _TSEL23 :1; + IO_WORD _TSEL22 :1; + IO_WORD _TSEL21 :1; + IO_WORD _TSEL20 :1; + IO_WORD _TSEL13 :1; + IO_WORD _TSEL12 :1; + IO_WORD _TSEL11 :1; + IO_WORD _TSEL10 :1; + IO_WORD _TSEL03 :1; + IO_WORD _TSEL02 :1; + IO_WORD _TSEL01 :1; + IO_WORD _TSEL00 :1; + }bit; + }GCN12STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _EN3 :1; + IO_BYTE _EN2 :1; + IO_BYTE _EN1 :1; + IO_BYTE _EN0 :1; + }bit; + }GCN22STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CNTE :1; + IO_WORD _STGR :1; + IO_WORD _MDSE :1; + IO_WORD _RTRG :1; + IO_WORD _CKS1 :1; + IO_WORD _CKS0 :1; + IO_WORD _PGMS :1; + IO_WORD :1; + IO_WORD _EGS1 :1; + IO_WORD _EGS0 :1; + IO_WORD _IREN :1; + IO_WORD _IRQF :1; + IO_WORD _IRS1 :1; + IO_WORD _IRS0 :1; + IO_WORD :1; + IO_WORD _OSEL :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CKS :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD _EGS :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD _IRS :2; + }bitc; + }PCN04STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CNTE :1; + IO_BYTE _STGR :1; + IO_BYTE _MDSE :1; + IO_BYTE _RTRG :1; + IO_BYTE _CKS1 :1; + IO_BYTE _CKS0 :1; + IO_BYTE _PGMS :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CKS :2; + }bitc; + }PCNH04STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EGS1 :1; + IO_BYTE _EGS0 :1; + IO_BYTE _IREN :1; + IO_BYTE _IRQF :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRS0 :1; + IO_BYTE :1; + IO_BYTE _OSEL :1; + }bit; + struct{ + IO_BYTE _EGS :2; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _IRS :2; + }bitc; + }PCNL04STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CNTE :1; + IO_WORD _STGR :1; + IO_WORD _MDSE :1; + IO_WORD _RTRG :1; + IO_WORD _CKS1 :1; + IO_WORD _CKS0 :1; + IO_WORD _PGMS :1; + IO_WORD :1; + IO_WORD _EGS1 :1; + IO_WORD _EGS0 :1; + IO_WORD _IREN :1; + IO_WORD _IRQF :1; + IO_WORD _IRS1 :1; + IO_WORD _IRS0 :1; + IO_WORD :1; + IO_WORD _OSEL :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CKS :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD _EGS :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD _IRS :2; + }bitc; + }PCN05STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CNTE :1; + IO_BYTE _STGR :1; + IO_BYTE _MDSE :1; + IO_BYTE _RTRG :1; + IO_BYTE _CKS1 :1; + IO_BYTE _CKS0 :1; + IO_BYTE _PGMS :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CKS :2; + }bitc; + }PCNH05STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EGS1 :1; + IO_BYTE _EGS0 :1; + IO_BYTE _IREN :1; + IO_BYTE _IRQF :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRS0 :1; + IO_BYTE :1; + IO_BYTE _OSEL :1; + }bit; + struct{ + IO_BYTE _EGS :2; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _IRS :2; + }bitc; + }PCNL05STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CNTE :1; + IO_WORD _STGR :1; + IO_WORD _MDSE :1; + IO_WORD _RTRG :1; + IO_WORD _CKS1 :1; + IO_WORD _CKS0 :1; + IO_WORD _PGMS :1; + IO_WORD :1; + IO_WORD _EGS1 :1; + IO_WORD _EGS0 :1; + IO_WORD _IREN :1; + IO_WORD _IRQF :1; + IO_WORD _IRS1 :1; + IO_WORD _IRS0 :1; + IO_WORD :1; + IO_WORD _OSEL :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CKS :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD _EGS :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD _IRS :2; + }bitc; + }PCN06STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CNTE :1; + IO_BYTE _STGR :1; + IO_BYTE _MDSE :1; + IO_BYTE _RTRG :1; + IO_BYTE _CKS1 :1; + IO_BYTE _CKS0 :1; + IO_BYTE _PGMS :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CKS :2; + }bitc; + }PCNH06STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EGS1 :1; + IO_BYTE _EGS0 :1; + IO_BYTE _IREN :1; + IO_BYTE _IRQF :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRS0 :1; + IO_BYTE :1; + IO_BYTE _OSEL :1; + }bit; + struct{ + IO_BYTE _EGS :2; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _IRS :2; + }bitc; + }PCNL06STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CNTE :1; + IO_WORD _STGR :1; + IO_WORD _MDSE :1; + IO_WORD _RTRG :1; + IO_WORD _CKS1 :1; + IO_WORD _CKS0 :1; + IO_WORD _PGMS :1; + IO_WORD :1; + IO_WORD _EGS1 :1; + IO_WORD _EGS0 :1; + IO_WORD _IREN :1; + IO_WORD _IRQF :1; + IO_WORD _IRS1 :1; + IO_WORD _IRS0 :1; + IO_WORD :1; + IO_WORD _OSEL :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CKS :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD _EGS :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD _IRS :2; + }bitc; + }PCN07STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CNTE :1; + IO_BYTE _STGR :1; + IO_BYTE _MDSE :1; + IO_BYTE _RTRG :1; + IO_BYTE _CKS1 :1; + IO_BYTE _CKS0 :1; + IO_BYTE _PGMS :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CKS :2; + }bitc; + }PCNH07STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EGS1 :1; + IO_BYTE _EGS0 :1; + IO_BYTE _IREN :1; + IO_BYTE _IRQF :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRS0 :1; + IO_BYTE :1; + IO_BYTE _OSEL :1; + }bit; + struct{ + IO_BYTE _EGS :2; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _IRS :2; + }bitc; + }PCNL07STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CNTE :1; + IO_WORD _STGR :1; + IO_WORD _MDSE :1; + IO_WORD _RTRG :1; + IO_WORD _CKS1 :1; + IO_WORD _CKS0 :1; + IO_WORD _PGMS :1; + IO_WORD :1; + IO_WORD _EGS1 :1; + IO_WORD _EGS0 :1; + IO_WORD _IREN :1; + IO_WORD _IRQF :1; + IO_WORD _IRS1 :1; + IO_WORD _IRS0 :1; + IO_WORD :1; + IO_WORD _OSEL :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CKS :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD _EGS :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD _IRS :2; + }bitc; + }PCN08STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CNTE :1; + IO_BYTE _STGR :1; + IO_BYTE _MDSE :1; + IO_BYTE _RTRG :1; + IO_BYTE _CKS1 :1; + IO_BYTE _CKS0 :1; + IO_BYTE _PGMS :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CKS :2; + }bitc; + }PCNH08STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EGS1 :1; + IO_BYTE _EGS0 :1; + IO_BYTE _IREN :1; + IO_BYTE _IRQF :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRS0 :1; + IO_BYTE :1; + IO_BYTE _OSEL :1; + }bit; + struct{ + IO_BYTE _EGS :2; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _IRS :2; + }bitc; + }PCNL08STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CNTE :1; + IO_WORD _STGR :1; + IO_WORD _MDSE :1; + IO_WORD _RTRG :1; + IO_WORD _CKS1 :1; + IO_WORD _CKS0 :1; + IO_WORD _PGMS :1; + IO_WORD :1; + IO_WORD _EGS1 :1; + IO_WORD _EGS0 :1; + IO_WORD _IREN :1; + IO_WORD _IRQF :1; + IO_WORD _IRS1 :1; + IO_WORD _IRS0 :1; + IO_WORD :1; + IO_WORD _OSEL :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CKS :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD _EGS :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD _IRS :2; + }bitc; + }PCN09STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CNTE :1; + IO_BYTE _STGR :1; + IO_BYTE _MDSE :1; + IO_BYTE _RTRG :1; + IO_BYTE _CKS1 :1; + IO_BYTE _CKS0 :1; + IO_BYTE _PGMS :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CKS :2; + }bitc; + }PCNH09STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EGS1 :1; + IO_BYTE _EGS0 :1; + IO_BYTE _IREN :1; + IO_BYTE _IRQF :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRS0 :1; + IO_BYTE :1; + IO_BYTE _OSEL :1; + }bit; + struct{ + IO_BYTE _EGS :2; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _IRS :2; + }bitc; + }PCNL09STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CNTE :1; + IO_WORD _STGR :1; + IO_WORD _MDSE :1; + IO_WORD _RTRG :1; + IO_WORD _CKS1 :1; + IO_WORD _CKS0 :1; + IO_WORD _PGMS :1; + IO_WORD :1; + IO_WORD _EGS1 :1; + IO_WORD _EGS0 :1; + IO_WORD _IREN :1; + IO_WORD _IRQF :1; + IO_WORD _IRS1 :1; + IO_WORD _IRS0 :1; + IO_WORD :1; + IO_WORD _OSEL :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CKS :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD _EGS :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD _IRS :2; + }bitc; + }PCN10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CNTE :1; + IO_BYTE _STGR :1; + IO_BYTE _MDSE :1; + IO_BYTE _RTRG :1; + IO_BYTE _CKS1 :1; + IO_BYTE _CKS0 :1; + IO_BYTE _PGMS :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CKS :2; + }bitc; + }PCNH10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EGS1 :1; + IO_BYTE _EGS0 :1; + IO_BYTE _IREN :1; + IO_BYTE _IRQF :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRS0 :1; + IO_BYTE :1; + IO_BYTE _OSEL :1; + }bit; + struct{ + IO_BYTE _EGS :2; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _IRS :2; + }bitc; + }PCNL10STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CNTE :1; + IO_WORD _STGR :1; + IO_WORD _MDSE :1; + IO_WORD _RTRG :1; + IO_WORD _CKS1 :1; + IO_WORD _CKS0 :1; + IO_WORD _PGMS :1; + IO_WORD :1; + IO_WORD _EGS1 :1; + IO_WORD _EGS0 :1; + IO_WORD _IREN :1; + IO_WORD _IRQF :1; + IO_WORD _IRS1 :1; + IO_WORD _IRS0 :1; + IO_WORD :1; + IO_WORD _OSEL :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CKS :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD _EGS :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD _IRS :2; + }bitc; + }PCN11STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CNTE :1; + IO_BYTE _STGR :1; + IO_BYTE _MDSE :1; + IO_BYTE _RTRG :1; + IO_BYTE _CKS1 :1; + IO_BYTE _CKS0 :1; + IO_BYTE _PGMS :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CKS :2; + }bitc; + }PCNH11STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EGS1 :1; + IO_BYTE _EGS0 :1; + IO_BYTE _IREN :1; + IO_BYTE _IRQF :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRS0 :1; + IO_BYTE :1; + IO_BYTE _OSEL :1; + }bit; + struct{ + IO_BYTE _EGS :2; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _IRS :2; + }bitc; + }PCNL11STR; +typedef union{ /* Pulse Frequency Modulator (PFM) */ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD _INV :1; + IO_WORD :1; + IO_WORD _CSL2 :1; + IO_WORD _CSL1 :1; + IO_WORD _CSL0 :1; + IO_WORD :1; + IO_WORD _MOD1 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _RELD :1; + IO_WORD _INTE :1; + IO_WORD _UF :1; + IO_WORD _CNTE :1; + IO_WORD _TRG :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CSL :3; + }bitc; + }P0TMCSRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _INV :1; + IO_BYTE :1; + IO_BYTE _CSL2 :1; + IO_BYTE _CSL1 :1; + IO_BYTE _CSL0 :1; + IO_BYTE :1; + IO_BYTE _MOD1 :1; + }bit; + struct{ + IO_BYTE :3; + IO_BYTE _CSL :3; + }bitc; + }P0TMCSRHSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _RELD :1; + IO_BYTE _INTE :1; + IO_BYTE _UF :1; + IO_BYTE _CNTE :1; + IO_BYTE _TRG :1; + }bit; + }P0TMCSRLSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD _INV :1; + IO_WORD :1; + IO_WORD _CSL2 :1; + IO_WORD _CSL1 :1; + IO_WORD _CSL0 :1; + IO_WORD :1; + IO_WORD _MOD1 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _RELD :1; + IO_WORD _INTE :1; + IO_WORD _UF :1; + IO_WORD _CNTE :1; + IO_WORD _TRG :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CSL :3; + }bitc; + }P1TMCSRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _INV :1; + IO_BYTE :1; + IO_BYTE _CSL2 :1; + IO_BYTE _CSL1 :1; + IO_BYTE _CSL0 :1; + IO_BYTE :1; + IO_BYTE _MOD1 :1; + }bit; + struct{ + IO_BYTE :3; + IO_BYTE _CSL :3; + }bitc; + }P1TMCSRHSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _RELD :1; + IO_BYTE _INTE :1; + IO_BYTE _UF :1; + IO_BYTE _CNTE :1; + IO_BYTE _TRG :1; + }bit; + }P1TMCSRLSTR; +typedef union{ /* Input Capture 0-3 */ + IO_BYTE byte; + struct{ + IO_BYTE _ICP1 :1; + IO_BYTE _ICP0 :1; + IO_BYTE _ICE1 :1; + IO_BYTE _ICE0 :1; + IO_BYTE _EG11 :1; + IO_BYTE _EG10 :1; + IO_BYTE _EG01 :1; + IO_BYTE _EG00 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _EG1 :2; + IO_BYTE _EG0 :2; + }bitc; + }ICS01STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ICP3 :1; + IO_BYTE _ICP2 :1; + IO_BYTE _ICE3 :1; + IO_BYTE _ICE2 :1; + IO_BYTE _EG31 :1; + IO_BYTE _EG30 :1; + IO_BYTE _EG21 :1; + IO_BYTE _EG20 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _EG3 :2; + IO_BYTE _EG2 :2; + }bitc; + }ICS23STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CP15 :1; + IO_WORD _CP14 :1; + IO_WORD _CP13 :1; + IO_WORD _CP12 :1; + IO_WORD _CP11 :1; + IO_WORD _CP10 :1; + IO_WORD _CP9 :1; + IO_WORD _CP8 :1; + IO_WORD _CP7 :1; + IO_WORD _CP6 :1; + IO_WORD _CP5 :1; + IO_WORD _CP4 :1; + IO_WORD _CP3 :1; + IO_WORD _CP2 :1; + IO_WORD _CP1 :1; + IO_WORD _CP0 :1; + }bit; + }IPCP0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CP15 :1; + IO_WORD _CP14 :1; + IO_WORD _CP13 :1; + IO_WORD _CP12 :1; + IO_WORD _CP11 :1; + IO_WORD _CP10 :1; + IO_WORD _CP9 :1; + IO_WORD _CP8 :1; + IO_WORD _CP7 :1; + IO_WORD _CP6 :1; + IO_WORD _CP5 :1; + IO_WORD _CP4 :1; + IO_WORD _CP3 :1; + IO_WORD _CP2 :1; + IO_WORD _CP1 :1; + IO_WORD _CP0 :1; + }bit; + }IPCP1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CP15 :1; + IO_WORD _CP14 :1; + IO_WORD _CP13 :1; + IO_WORD _CP12 :1; + IO_WORD _CP11 :1; + IO_WORD _CP10 :1; + IO_WORD _CP9 :1; + IO_WORD _CP8 :1; + IO_WORD _CP7 :1; + IO_WORD _CP6 :1; + IO_WORD _CP5 :1; + IO_WORD _CP4 :1; + IO_WORD _CP3 :1; + IO_WORD _CP2 :1; + IO_WORD _CP1 :1; + IO_WORD _CP0 :1; + }bit; + }IPCP2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CP15 :1; + IO_WORD _CP14 :1; + IO_WORD _CP13 :1; + IO_WORD _CP12 :1; + IO_WORD _CP11 :1; + IO_WORD _CP10 :1; + IO_WORD _CP9 :1; + IO_WORD _CP8 :1; + IO_WORD _CP7 :1; + IO_WORD _CP6 :1; + IO_WORD _CP5 :1; + IO_WORD _CP4 :1; + IO_WORD _CP3 :1; + IO_WORD _CP2 :1; + IO_WORD _CP1 :1; + IO_WORD _CP0 :1; + }bit; + }IPCP3STR; +typedef union{ /* Output Compare 0-3 */ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CMOD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _OTD1 :1; + IO_WORD _OTD0 :1; + IO_WORD _ICP1 :1; + IO_WORD _ICP0 :1; + IO_WORD _ICE1 :1; + IO_WORD _ICE0 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CST1 :1; + IO_WORD _CST0 :1; + }bit; + }OCS01STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CMOD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _OTD3 :1; + IO_WORD _OTD2 :1; + IO_WORD _ICP3 :1; + IO_WORD _ICP2 :1; + IO_WORD _ICE3 :1; + IO_WORD _ICE2 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CST3 :1; + IO_WORD _CST2 :1; + }bit; + }OCS23STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _C15 :1; + IO_WORD _C14 :1; + IO_WORD _C13 :1; + IO_WORD _C12 :1; + IO_WORD _C11 :1; + IO_WORD _C10 :1; + IO_WORD _C9 :1; + IO_WORD _C8 :1; + IO_WORD _C7 :1; + IO_WORD _C6 :1; + IO_WORD _C5 :1; + IO_WORD _C4 :1; + IO_WORD _C3 :1; + IO_WORD _C2 :1; + IO_WORD _C1 :1; + IO_WORD _C0 :1; + }bit; + }OCCP0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _C15 :1; + IO_WORD _C14 :1; + IO_WORD _C13 :1; + IO_WORD _C12 :1; + IO_WORD _C11 :1; + IO_WORD _C10 :1; + IO_WORD _C9 :1; + IO_WORD _C8 :1; + IO_WORD _C7 :1; + IO_WORD _C6 :1; + IO_WORD _C5 :1; + IO_WORD _C4 :1; + IO_WORD _C3 :1; + IO_WORD _C2 :1; + IO_WORD _C1 :1; + IO_WORD _C0 :1; + }bit; + }OCCP1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _C15 :1; + IO_WORD _C14 :1; + IO_WORD _C13 :1; + IO_WORD _C12 :1; + IO_WORD _C11 :1; + IO_WORD _C10 :1; + IO_WORD _C9 :1; + IO_WORD _C8 :1; + IO_WORD _C7 :1; + IO_WORD _C6 :1; + IO_WORD _C5 :1; + IO_WORD _C4 :1; + IO_WORD _C3 :1; + IO_WORD _C2 :1; + IO_WORD _C1 :1; + IO_WORD _C0 :1; + }bit; + }OCCP2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _C15 :1; + IO_WORD _C14 :1; + IO_WORD _C13 :1; + IO_WORD _C12 :1; + IO_WORD _C11 :1; + IO_WORD _C10 :1; + IO_WORD _C9 :1; + IO_WORD _C8 :1; + IO_WORD _C7 :1; + IO_WORD _C6 :1; + IO_WORD _C5 :1; + IO_WORD _C4 :1; + IO_WORD _C3 :1; + IO_WORD _C2 :1; + IO_WORD _C1 :1; + IO_WORD _C0 :1; + }bit; + }OCCP3STR; +typedef union{ /* Sound Generator */ + IO_WORD word; + struct{ + IO_WORD _TST :1; + IO_WORD _S2 :1; + IO_WORD _S1 :1; + IO_WORD _S0 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _BUSY :1; + IO_WORD _DEC :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _TONE :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _INTE :1; + IO_WORD _INT :1; + IO_WORD _ST :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD _S :3; + }bitc; + }SGCRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TST :1; + IO_BYTE _S2 :1; + IO_BYTE _S1 :1; + IO_BYTE _S0 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _BUSY :1; + IO_BYTE _DEC :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE _S :3; + }bitc; + }SGCRHSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _TONE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _INTE :1; + IO_BYTE _INT :1; + IO_BYTE _ST :1; + }bit; + }SGCRLSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D15 :1; + IO_WORD _D14 :1; + IO_WORD _D13 :1; + IO_WORD _D12 :1; + IO_WORD _D11 :1; + IO_WORD _D10 :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }SGFRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }SGARSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }SGTRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }SGDRSTR; +typedef union{ /* ADC */ + IO_WORD word; + struct{ + IO_WORD _ADE31 :1; + IO_WORD _ADE30 :1; + IO_WORD _ADE29 :1; + IO_WORD _ADE28 :1; + IO_WORD _ADE27 :1; + IO_WORD _ADE26 :1; + IO_WORD _ADE25 :1; + IO_WORD _ADE24 :1; + IO_WORD _ADE23 :1; + IO_WORD _ADE22 :1; + IO_WORD _ADE21 :1; + IO_WORD _ADE20 :1; + IO_WORD _ADE19 :1; + IO_WORD _ADE18 :1; + IO_WORD _ADE17 :1; + IO_WORD _ADE16 :1; + }bit; + }ADERHSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _ADE15 :1; + IO_WORD _ADE14 :1; + IO_WORD _ADE13 :1; + IO_WORD _ADE12 :1; + IO_WORD _ADE11 :1; + IO_WORD _ADE10 :1; + IO_WORD _ADE9 :1; + IO_WORD _ADE8 :1; + IO_WORD _ADE7 :1; + IO_WORD _ADE6 :1; + IO_WORD _ADE5 :1; + IO_WORD _ADE4 :1; + IO_WORD _ADE3 :1; + IO_WORD _ADE2 :1; + IO_WORD _ADE1 :1; + IO_WORD _ADE0 :1; + }bit; + }ADERLSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _BUSY :1; + IO_BYTE _INT :1; + IO_BYTE _INTE :1; + IO_BYTE _PAUS :1; + IO_BYTE _STS1 :1; + IO_BYTE _STS0 :1; + IO_BYTE _STRT :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _STS :2; + }bitc; + }ADCS1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MD1 :1; + IO_BYTE _MD0 :1; + IO_BYTE _S10 :1; + IO_BYTE _ACH4 :1; + IO_BYTE _ACH3 :1; + IO_BYTE _ACH2 :1; + IO_BYTE _ACH1 :1; + IO_BYTE _ACH0 :1; + }bit; + struct{ + IO_BYTE _MD :2; + IO_BYTE :1; + IO_BYTE _ACH :5; + }bitc; + }ADCS0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D9 :1; + IO_BYTE _D8 :1; + }bit; + }ADCR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }ADCR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CT5 :1; + IO_BYTE _CT4 :1; + IO_BYTE _CT3 :1; + IO_BYTE _CT2 :1; + IO_BYTE _CT1 :1; + IO_BYTE _CT0 :1; + IO_BYTE _ST9 :1; + IO_BYTE _ST8 :1; + }bit; + }ADCT1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ST7 :1; + IO_BYTE _ST6 :1; + IO_BYTE _ST5 :1; + IO_BYTE _ST4 :1; + IO_BYTE _ST3 :1; + IO_BYTE _ST2 :1; + IO_BYTE _ST1 :1; + IO_BYTE _ST0 :1; + }bit; + }ADCT0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ANS4 :1; + IO_BYTE _ANS3 :1; + IO_BYTE _ANS2 :1; + IO_BYTE _ANS1 :1; + IO_BYTE _ASN0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ANS :5; + }bitc; + }ADSCHSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ANE4 :1; + IO_BYTE _ANE3 :1; + IO_BYTE _ANE2 :1; + IO_BYTE _ANE1 :1; + IO_BYTE _ANE0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ANE :5; + }bitc; + }ADECHSTR; +typedef union{ /* Alarm Comparator 0-1 */ + IO_BYTE byte; + struct{ + IO_BYTE _MD :1; + IO_BYTE _OV_EN :1; + IO_BYTE _UV_EN :1; + IO_BYTE _OUT2 :1; + IO_BYTE _OUT1 :1; + IO_BYTE _IRQ :1; + IO_BYTE _IEN :1; + IO_BYTE _PD :1; + }bit; + }ACSR0STR; +typedef union{ /* Reload Timer 0 */ + IO_WORD word; + struct{ + IO_WORD _D15 :1; + IO_WORD _D14 :1; + IO_WORD _D13 :1; + IO_WORD _D12 :1; + IO_WORD _D11 :1; + IO_WORD _D10 :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }TMRLR0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D15 :1; + IO_WORD _D14 :1; + IO_WORD _D13 :1; + IO_WORD _D12 :1; + IO_WORD _D11 :1; + IO_WORD _D10 :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }TMR0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CSL2 :1; + IO_WORD _CSL1 :1; + IO_WORD _CSL0 :1; + IO_WORD _MOD2 :1; + IO_WORD _MOD1 :1; + IO_WORD _MOD0 :1; + IO_WORD :1; + IO_WORD _OUTL :1; + IO_WORD _RELD :1; + IO_WORD _INTE :1; + IO_WORD _UF :1; + IO_WORD _CNTE :1; + IO_WORD _TRG :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CSL :3; + IO_WORD _MOD :3; + }bitc; + }TMCSR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CSL2 :1; + IO_BYTE _CSL1 :1; + IO_BYTE _CSL0 :1; + IO_BYTE _MOD2 :1; + IO_BYTE _MOD1 :1; + }bit; + struct{ + IO_BYTE :3; + IO_BYTE _CSL :3; + }bitc; + }TMCSRH0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MOD0 :1; + IO_BYTE :1; + IO_BYTE _OUTL :1; + IO_BYTE _RELD :1; + IO_BYTE _INTE :1; + IO_BYTE _UF :1; + IO_BYTE _CNTE :1; + IO_BYTE _TRG :1; + }bit; + }TMCSRL0STR; +typedef union{ /* Reload Timer 1 */ + IO_WORD word; + struct{ + IO_WORD _D15 :1; + IO_WORD _D14 :1; + IO_WORD _D13 :1; + IO_WORD _D12 :1; + IO_WORD _D11 :1; + IO_WORD _D10 :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }TMRLR1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D15 :1; + IO_WORD _D14 :1; + IO_WORD _D13 :1; + IO_WORD _D12 :1; + IO_WORD _D11 :1; + IO_WORD _D10 :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }TMR1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CSL2 :1; + IO_WORD _CSL1 :1; + IO_WORD _CSL0 :1; + IO_WORD _MOD2 :1; + IO_WORD _MOD1 :1; + IO_WORD _MOD0 :1; + IO_WORD :1; + IO_WORD _OUTL :1; + IO_WORD _RELD :1; + IO_WORD _INTE :1; + IO_WORD _UF :1; + IO_WORD _CNTE :1; + IO_WORD _TRG :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CSL :3; + IO_WORD _MOD :3; + }bitc; + }TMCSR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CSL2 :1; + IO_BYTE _CSL1 :1; + IO_BYTE _CSL0 :1; + IO_BYTE _MOD2 :1; + IO_BYTE _MOD1 :1; + }bit; + struct{ + IO_BYTE :3; + IO_BYTE _CSL :3; + }bitc; + }TMCSRH1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MOD0 :1; + IO_BYTE :1; + IO_BYTE _OUTL :1; + IO_BYTE _RELD :1; + IO_BYTE _INTE :1; + IO_BYTE _UF :1; + IO_BYTE _CNTE :1; + IO_BYTE _TRG :1; + }bit; + }TMCSRL1STR; +typedef union{ /* Reload Timer 2 */ + IO_WORD word; + struct{ + IO_WORD _D15 :1; + IO_WORD _D14 :1; + IO_WORD _D13 :1; + IO_WORD _D12 :1; + IO_WORD _D11 :1; + IO_WORD _D10 :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }TMRLR2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D15 :1; + IO_WORD _D14 :1; + IO_WORD _D13 :1; + IO_WORD _D12 :1; + IO_WORD _D11 :1; + IO_WORD _D10 :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }TMR2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CSL2 :1; + IO_WORD _CSL1 :1; + IO_WORD _CSL0 :1; + IO_WORD _MOD2 :1; + IO_WORD _MOD1 :1; + IO_WORD _MOD0 :1; + IO_WORD :1; + IO_WORD _OUTL :1; + IO_WORD _RELD :1; + IO_WORD _INTE :1; + IO_WORD _UF :1; + IO_WORD _CNTE :1; + IO_WORD _TRG :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CSL :3; + IO_WORD _MOD :3; + }bitc; + }TMCSR2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CSL2 :1; + IO_BYTE _CSL1 :1; + IO_BYTE _CSL0 :1; + IO_BYTE _MOD2 :1; + IO_BYTE _MOD1 :1; + }bit; + struct{ + IO_BYTE :3; + IO_BYTE _CSL :3; + }bitc; + }TMCSRH2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MOD0 :1; + IO_BYTE :1; + IO_BYTE _OUTL :1; + IO_BYTE _RELD :1; + IO_BYTE _INTE :1; + IO_BYTE _UF :1; + IO_BYTE _CNTE :1; + IO_BYTE _TRG :1; + }bit; + }TMCSRL2STR; +typedef union{ /* Reload Timer 3 */ + IO_WORD word; + struct{ + IO_WORD _D15 :1; + IO_WORD _D14 :1; + IO_WORD _D13 :1; + IO_WORD _D12 :1; + IO_WORD _D11 :1; + IO_WORD _D10 :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }TMRLR3STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D15 :1; + IO_WORD _D14 :1; + IO_WORD _D13 :1; + IO_WORD _D12 :1; + IO_WORD _D11 :1; + IO_WORD _D10 :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }TMR3STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CSL2 :1; + IO_WORD _CSL1 :1; + IO_WORD _CSL0 :1; + IO_WORD _MOD2 :1; + IO_WORD _MOD1 :1; + IO_WORD _MOD0 :1; + IO_WORD :1; + IO_WORD _OUTL :1; + IO_WORD _RELD :1; + IO_WORD _INTE :1; + IO_WORD _UF :1; + IO_WORD _CNTE :1; + IO_WORD _TRG :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CSL :3; + IO_WORD _MOD :3; + }bitc; + }TMCSR3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CSL2 :1; + IO_BYTE _CSL1 :1; + IO_BYTE _CSL0 :1; + IO_BYTE _MOD2 :1; + IO_BYTE _MOD1 :1; + }bit; + struct{ + IO_BYTE :3; + IO_BYTE _CSL :3; + }bitc; + }TMCSRH3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MOD0 :1; + IO_BYTE :1; + IO_BYTE _OUTL :1; + IO_BYTE _RELD :1; + IO_BYTE _INTE :1; + IO_BYTE _UF :1; + IO_BYTE _CNTE :1; + IO_BYTE _TRG :1; + }bit; + }TMCSRL3STR; +typedef union{ /* Reload Timer 4 */ + IO_WORD word; + struct{ + IO_WORD _D15 :1; + IO_WORD _D14 :1; + IO_WORD _D13 :1; + IO_WORD _D12 :1; + IO_WORD _D11 :1; + IO_WORD _D10 :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }TMRLR4STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D15 :1; + IO_WORD _D14 :1; + IO_WORD _D13 :1; + IO_WORD _D12 :1; + IO_WORD _D11 :1; + IO_WORD _D10 :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }TMR4STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CSL2 :1; + IO_WORD _CSL1 :1; + IO_WORD _CSL0 :1; + IO_WORD _MOD2 :1; + IO_WORD _MOD1 :1; + IO_WORD _MOD0 :1; + IO_WORD :1; + IO_WORD _OUTL :1; + IO_WORD _RELD :1; + IO_WORD _INTE :1; + IO_WORD _UF :1; + IO_WORD _CNTE :1; + IO_WORD _TRG :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CSL :3; + IO_WORD _MOD :3; + }bitc; + }TMCSR4STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CSL2 :1; + IO_BYTE _CSL1 :1; + IO_BYTE _CSL0 :1; + IO_BYTE _MOD2 :1; + IO_BYTE _MOD1 :1; + }bit; + struct{ + IO_BYTE :3; + IO_BYTE _CSL :3; + }bitc; + }TMCSRH4STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MOD0 :1; + IO_BYTE :1; + IO_BYTE _OUTL :1; + IO_BYTE _RELD :1; + IO_BYTE _INTE :1; + IO_BYTE _UF :1; + IO_BYTE _CNTE :1; + IO_BYTE _TRG :1; + }bit; + }TMCSRL4STR; +typedef union{ /* Reload Timer 5 */ + IO_WORD word; + struct{ + IO_WORD _D15 :1; + IO_WORD _D14 :1; + IO_WORD _D13 :1; + IO_WORD _D12 :1; + IO_WORD _D11 :1; + IO_WORD _D10 :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }TMRLR5STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D15 :1; + IO_WORD _D14 :1; + IO_WORD _D13 :1; + IO_WORD _D12 :1; + IO_WORD _D11 :1; + IO_WORD _D10 :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }TMR5STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CSL2 :1; + IO_WORD _CSL1 :1; + IO_WORD _CSL0 :1; + IO_WORD _MOD2 :1; + IO_WORD _MOD1 :1; + IO_WORD _MOD0 :1; + IO_WORD :1; + IO_WORD _OUTL :1; + IO_WORD _RELD :1; + IO_WORD _INTE :1; + IO_WORD _UF :1; + IO_WORD _CNTE :1; + IO_WORD _TRG :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CSL :3; + IO_WORD _MOD :3; + }bitc; + }TMCSR5STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CSL2 :1; + IO_BYTE _CSL1 :1; + IO_BYTE _CSL0 :1; + IO_BYTE _MOD2 :1; + IO_BYTE _MOD1 :1; + }bit; + struct{ + IO_BYTE :3; + IO_BYTE _CSL :3; + }bitc; + }TMCSRH5STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MOD0 :1; + IO_BYTE :1; + IO_BYTE _OUTL :1; + IO_BYTE _RELD :1; + IO_BYTE _INTE :1; + IO_BYTE _UF :1; + IO_BYTE _CNTE :1; + IO_BYTE _TRG :1; + }bit; + }TMCSRL5STR; +typedef union{ /* Reload Timer 6 */ + IO_WORD word; + struct{ + IO_WORD _D15 :1; + IO_WORD _D14 :1; + IO_WORD _D13 :1; + IO_WORD _D12 :1; + IO_WORD _D11 :1; + IO_WORD _D10 :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }TMRLR6STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D15 :1; + IO_WORD _D14 :1; + IO_WORD _D13 :1; + IO_WORD _D12 :1; + IO_WORD _D11 :1; + IO_WORD _D10 :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }TMR6STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CSL2 :1; + IO_WORD _CSL1 :1; + IO_WORD _CSL0 :1; + IO_WORD _MOD2 :1; + IO_WORD _MOD1 :1; + IO_WORD _MOD0 :1; + IO_WORD :1; + IO_WORD _OUTL :1; + IO_WORD _RELD :1; + IO_WORD _INTE :1; + IO_WORD _UF :1; + IO_WORD _CNTE :1; + IO_WORD _TRG :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CSL :3; + IO_WORD _MOD :3; + }bitc; + }TMCSR6STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CSL2 :1; + IO_BYTE _CSL1 :1; + IO_BYTE _CSL0 :1; + IO_BYTE _MOD2 :1; + IO_BYTE _MOD1 :1; + }bit; + struct{ + IO_BYTE :3; + IO_BYTE _CSL :3; + }bitc; + }TMCSRH6STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MOD0 :1; + IO_BYTE :1; + IO_BYTE _OUTL :1; + IO_BYTE _RELD :1; + IO_BYTE _INTE :1; + IO_BYTE _UF :1; + IO_BYTE _CNTE :1; + IO_BYTE _TRG :1; + }bit; + }TMCSRL6STR; +typedef union{ /* Reload Timer 7 */ + IO_WORD word; + struct{ + IO_WORD _D15 :1; + IO_WORD _D14 :1; + IO_WORD _D13 :1; + IO_WORD _D12 :1; + IO_WORD _D11 :1; + IO_WORD _D10 :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }TMRLR7STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D15 :1; + IO_WORD _D14 :1; + IO_WORD _D13 :1; + IO_WORD _D12 :1; + IO_WORD _D11 :1; + IO_WORD _D10 :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }TMR7STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CSL2 :1; + IO_WORD _CSL1 :1; + IO_WORD _CSL0 :1; + IO_WORD _MOD2 :1; + IO_WORD _MOD1 :1; + IO_WORD _MOD0 :1; + IO_WORD :1; + IO_WORD _OUTL :1; + IO_WORD _RELD :1; + IO_WORD _INTE :1; + IO_WORD _UF :1; + IO_WORD _CNTE :1; + IO_WORD _TRG :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CSL :3; + IO_WORD _MOD :3; + }bitc; + }TMCSR7STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CSL2 :1; + IO_BYTE _CSL1 :1; + IO_BYTE _CSL0 :1; + IO_BYTE _MOD2 :1; + IO_BYTE _MOD1 :1; + }bit; + struct{ + IO_BYTE :3; + IO_BYTE _CSL :3; + }bitc; + }TMCSRH7STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MOD0 :1; + IO_BYTE :1; + IO_BYTE _OUTL :1; + IO_BYTE _RELD :1; + IO_BYTE _INTE :1; + IO_BYTE _UF :1; + IO_BYTE _CNTE :1; + IO_BYTE _TRG :1; + }bit; + }TMCSRL7STR; +typedef union{ /* Free Running Timer0 */ + IO_WORD word; + struct{ + IO_WORD _T15 :1; + IO_WORD _T14 :1; + IO_WORD _T13 :1; + IO_WORD _T12 :1; + IO_WORD _T11 :1; + IO_WORD _T10 :1; + IO_WORD _T9 :1; + IO_WORD _T8 :1; + IO_WORD _T7 :1; + IO_WORD _T6 :1; + IO_WORD _T5 :1; + IO_WORD _T4 :1; + IO_WORD _T3 :1; + IO_WORD _T2 :1; + IO_WORD _T1 :1; + IO_WORD _T0 :1; + }bit; + }TCDT0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ECLK :1; + IO_BYTE _IVF :1; + IO_BYTE _IVFE :1; + IO_BYTE _STOP :1; + IO_BYTE _MODE :1; + IO_BYTE _CLR :1; + IO_BYTE _CLK1 :1; + IO_BYTE _CLK0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CLK :2; + }bitc; + }TCCS0STR; +typedef union{ /* Free Running Timer1 */ + IO_WORD word; + struct{ + IO_WORD _T15 :1; + IO_WORD _T14 :1; + IO_WORD _T13 :1; + IO_WORD _T12 :1; + IO_WORD _T11 :1; + IO_WORD _T10 :1; + IO_WORD _T9 :1; + IO_WORD _T8 :1; + IO_WORD _T7 :1; + IO_WORD _T6 :1; + IO_WORD _T5 :1; + IO_WORD _T4 :1; + IO_WORD _T3 :1; + IO_WORD _T2 :1; + IO_WORD _T1 :1; + IO_WORD _T0 :1; + }bit; + }TCDT1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ECLK :1; + IO_BYTE _IVF :1; + IO_BYTE _IVFE :1; + IO_BYTE _STOP :1; + IO_BYTE _MODE :1; + IO_BYTE _CLR :1; + IO_BYTE _CLK1 :1; + IO_BYTE _CLK0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CLK :2; + }bitc; + }TCCS1STR; +typedef union{ /* Free Running Timer2 */ + IO_WORD word; + struct{ + IO_WORD _T15 :1; + IO_WORD _T14 :1; + IO_WORD _T13 :1; + IO_WORD _T12 :1; + IO_WORD _T11 :1; + IO_WORD _T10 :1; + IO_WORD _T9 :1; + IO_WORD _T8 :1; + IO_WORD _T7 :1; + IO_WORD _T6 :1; + IO_WORD _T5 :1; + IO_WORD _T4 :1; + IO_WORD _T3 :1; + IO_WORD _T2 :1; + IO_WORD _T1 :1; + IO_WORD _T0 :1; + }bit; + }TCDT2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ECLK :1; + IO_BYTE _IVF :1; + IO_BYTE _IVFE :1; + IO_BYTE _STOP :1; + IO_BYTE _MODE :1; + IO_BYTE _CLR :1; + IO_BYTE _CLK1 :1; + IO_BYTE _CLK0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CLK :2; + }bitc; + }TCCS2STR; +typedef union{ /* Free Running Timer3 */ + IO_WORD word; + struct{ + IO_WORD _T15 :1; + IO_WORD _T14 :1; + IO_WORD _T13 :1; + IO_WORD _T12 :1; + IO_WORD _T11 :1; + IO_WORD _T10 :1; + IO_WORD _T9 :1; + IO_WORD _T8 :1; + IO_WORD _T7 :1; + IO_WORD _T6 :1; + IO_WORD _T5 :1; + IO_WORD _T4 :1; + IO_WORD _T3 :1; + IO_WORD _T2 :1; + IO_WORD _T1 :1; + IO_WORD _T0 :1; + }bit; + }TCDT3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ECLK :1; + IO_BYTE _IVF :1; + IO_BYTE _IVFE :1; + IO_BYTE _STOP :1; + IO_BYTE _MODE :1; + IO_BYTE _CLR :1; + IO_BYTE _CLK1 :1; + IO_BYTE _CLK0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CLK :2; + }bitc; + }TCCS3STR; +typedef union{ /* DMAC */ + IO_LWORD lword; + struct{ + IO_LWORD _DENB :1; + IO_LWORD _PAUS :1; + IO_LWORD _STRG :1; + IO_LWORD _IS4 :1; + IO_LWORD _IS3 :1; + IO_LWORD _IS2 :1; + IO_LWORD _IS1 :1; + IO_LWORD _IS0 :1; + IO_LWORD _EIS3 :1; + IO_LWORD _EIS2 :1; + IO_LWORD _EIS1 :1; + IO_LWORD _EIS0 :1; + IO_LWORD _BLK3 :1; + IO_LWORD _BLK2 :1; + IO_LWORD _BLK1 :1; + IO_LWORD _BLK0 :1; + IO_LWORD _DTCF :1; + IO_LWORD _DTCE :1; + IO_LWORD _DTCD :1; + IO_LWORD _DTCC :1; + IO_LWORD _DTCB :1; + IO_LWORD _DTCA :1; + IO_LWORD _DTC9 :1; + IO_LWORD _DTC8 :1; + IO_LWORD _DTC7 :1; + IO_LWORD _DTC6 :1; + IO_LWORD _DTC5 :1; + IO_LWORD _DTC4 :1; + IO_LWORD _DTC3 :1; + IO_LWORD _DTC2 :1; + IO_LWORD _DTC1 :1; + IO_LWORD _DTC0 :1; + }bit; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _IS :5; + IO_LWORD _EIS :4; + IO_LWORD _BLK :4; + IO_LWORD _DTC :16; + }bitc; + }DMACA0STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _TYPE1 :1; + IO_LWORD _TYPE0 :1; + IO_LWORD _MOD1 :1; + IO_LWORD _MOD0 :1; + IO_LWORD _WS1 :1; + IO_LWORD _WS0 :1; + IO_LWORD _SADM :1; + IO_LWORD _DADM :1; + IO_LWORD _DTCR :1; + IO_LWORD _SADR :1; + IO_LWORD _DADR :1; + IO_LWORD _ERIE :1; + IO_LWORD _EDIE :1; + IO_LWORD _DSS2 :1; + IO_LWORD _DSS1 :1; + IO_LWORD _DSS0 :1; + IO_LWORD _SASZ7 :1; + IO_LWORD _SASZ6 :1; + IO_LWORD _SASZ5 :1; + IO_LWORD _SASZ4 :1; + IO_LWORD _SASZ3 :1; + IO_LWORD _SASZ2 :1; + IO_LWORD _SASZ1 :1; + IO_LWORD _SASZ0 :1; + IO_LWORD _DASZ7 :1; + IO_LWORD _DASZ6 :1; + IO_LWORD _DASZ5 :1; + IO_LWORD _DASZ4 :1; + IO_LWORD _DASZ3 :1; + IO_LWORD _DASZ2 :1; + IO_LWORD _DASZ1 :1; + IO_LWORD _DASZ0 :1; + }bit; + struct{ + IO_LWORD _TYPE :2; + IO_LWORD _MOD :2; + IO_LWORD _WS :2; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _DSS :3; + IO_LWORD _SASZ :8; + IO_LWORD _DASZ :8; + }bitc; + }DMACB0STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _DENB :1; + IO_LWORD _PAUS :1; + IO_LWORD _STRG :1; + IO_LWORD _IS4 :1; + IO_LWORD _IS3 :1; + IO_LWORD _IS2 :1; + IO_LWORD _IS1 :1; + IO_LWORD _IS0 :1; + IO_LWORD _EIS3 :1; + IO_LWORD _EIS2 :1; + IO_LWORD _EIS1 :1; + IO_LWORD _EIS0 :1; + IO_LWORD _BLK3 :1; + IO_LWORD _BLK2 :1; + IO_LWORD _BLK1 :1; + IO_LWORD _BLK0 :1; + IO_LWORD _DTCF :1; + IO_LWORD _DTCE :1; + IO_LWORD _DTCD :1; + IO_LWORD _DTCC :1; + IO_LWORD _DTCB :1; + IO_LWORD _DTCA :1; + IO_LWORD _DTC9 :1; + IO_LWORD _DTC8 :1; + IO_LWORD _DTC7 :1; + IO_LWORD _DTC6 :1; + IO_LWORD _DTC5 :1; + IO_LWORD _DTC4 :1; + IO_LWORD _DTC3 :1; + IO_LWORD _DTC2 :1; + IO_LWORD _DTC1 :1; + IO_LWORD _DTC0 :1; + }bit; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _IS :5; + IO_LWORD _EIS :4; + IO_LWORD _BLK :4; + IO_LWORD _DTC :16; + }bitc; + }DMACA1STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _TYPE1 :1; + IO_LWORD _TYPE0 :1; + IO_LWORD _MOD1 :1; + IO_LWORD _MOD0 :1; + IO_LWORD _WS1 :1; + IO_LWORD _WS0 :1; + IO_LWORD _SADM :1; + IO_LWORD _DADM :1; + IO_LWORD _DTCR :1; + IO_LWORD _SADR :1; + IO_LWORD _DADR :1; + IO_LWORD _ERIE :1; + IO_LWORD _EDIE :1; + IO_LWORD _DSS2 :1; + IO_LWORD _DSS1 :1; + IO_LWORD _DSS0 :1; + IO_LWORD _SASZ7 :1; + IO_LWORD _SASZ6 :1; + IO_LWORD _SASZ5 :1; + IO_LWORD _SASZ4 :1; + IO_LWORD _SASZ3 :1; + IO_LWORD _SASZ2 :1; + IO_LWORD _SASZ1 :1; + IO_LWORD _SASZ0 :1; + IO_LWORD _DASZ7 :1; + IO_LWORD _DASZ6 :1; + IO_LWORD _DASZ5 :1; + IO_LWORD _DASZ4 :1; + IO_LWORD _DASZ3 :1; + IO_LWORD _DASZ2 :1; + IO_LWORD _DASZ1 :1; + IO_LWORD _DASZ0 :1; + }bit; + struct{ + IO_LWORD _TYPE :2; + IO_LWORD _MOD :2; + IO_LWORD _WS :2; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _DSS :3; + IO_LWORD _SASZ :8; + IO_LWORD _DASZ :8; + }bitc; + }DMACB1STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _DENB :1; + IO_LWORD _PAUS :1; + IO_LWORD _STRG :1; + IO_LWORD _IS4 :1; + IO_LWORD _IS3 :1; + IO_LWORD _IS2 :1; + IO_LWORD _IS1 :1; + IO_LWORD _IS0 :1; + IO_LWORD _EIS3 :1; + IO_LWORD _EIS2 :1; + IO_LWORD _EIS1 :1; + IO_LWORD _EIS0 :1; + IO_LWORD _BLK3 :1; + IO_LWORD _BLK2 :1; + IO_LWORD _BLK1 :1; + IO_LWORD _BLK0 :1; + IO_LWORD _DTCF :1; + IO_LWORD _DTCE :1; + IO_LWORD _DTCD :1; + IO_LWORD _DTCC :1; + IO_LWORD _DTCB :1; + IO_LWORD _DTCA :1; + IO_LWORD _DTC9 :1; + IO_LWORD _DTC8 :1; + IO_LWORD _DTC7 :1; + IO_LWORD _DTC6 :1; + IO_LWORD _DTC5 :1; + IO_LWORD _DTC4 :1; + IO_LWORD _DTC3 :1; + IO_LWORD _DTC2 :1; + IO_LWORD _DTC1 :1; + IO_LWORD _DTC0 :1; + }bit; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _IS :5; + IO_LWORD _EIS :4; + IO_LWORD _BLK :4; + IO_LWORD _DTC :16; + }bitc; + }DMACA2STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _TYPE1 :1; + IO_LWORD _TYPE0 :1; + IO_LWORD _MOD1 :1; + IO_LWORD _MOD0 :1; + IO_LWORD _WS1 :1; + IO_LWORD _WS0 :1; + IO_LWORD _SADM :1; + IO_LWORD _DADM :1; + IO_LWORD _DTCR :1; + IO_LWORD _SADR :1; + IO_LWORD _DADR :1; + IO_LWORD _ERIE :1; + IO_LWORD _EDIE :1; + IO_LWORD _DSS2 :1; + IO_LWORD _DSS1 :1; + IO_LWORD _DSS0 :1; + IO_LWORD _SASZ7 :1; + IO_LWORD _SASZ6 :1; + IO_LWORD _SASZ5 :1; + IO_LWORD _SASZ4 :1; + IO_LWORD _SASZ3 :1; + IO_LWORD _SASZ2 :1; + IO_LWORD _SASZ1 :1; + IO_LWORD _SASZ0 :1; + IO_LWORD _DASZ7 :1; + IO_LWORD _DASZ6 :1; + IO_LWORD _DASZ5 :1; + IO_LWORD _DASZ4 :1; + IO_LWORD _DASZ3 :1; + IO_LWORD _DASZ2 :1; + IO_LWORD _DASZ1 :1; + IO_LWORD _DASZ0 :1; + }bit; + struct{ + IO_LWORD _TYPE :2; + IO_LWORD _MOD :2; + IO_LWORD _WS :2; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _DSS :3; + IO_LWORD _SASZ :8; + IO_LWORD _DASZ :8; + }bitc; + }DMACB2STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _DENB :1; + IO_LWORD _PAUS :1; + IO_LWORD _STRG :1; + IO_LWORD _IS4 :1; + IO_LWORD _IS3 :1; + IO_LWORD _IS2 :1; + IO_LWORD _IS1 :1; + IO_LWORD _IS0 :1; + IO_LWORD _EIS3 :1; + IO_LWORD _EIS2 :1; + IO_LWORD _EIS1 :1; + IO_LWORD _EIS0 :1; + IO_LWORD _BLK3 :1; + IO_LWORD _BLK2 :1; + IO_LWORD _BLK1 :1; + IO_LWORD _BLK0 :1; + IO_LWORD _DTCF :1; + IO_LWORD _DTCE :1; + IO_LWORD _DTCD :1; + IO_LWORD _DTCC :1; + IO_LWORD _DTCB :1; + IO_LWORD _DTCA :1; + IO_LWORD _DTC9 :1; + IO_LWORD _DTC8 :1; + IO_LWORD _DTC7 :1; + IO_LWORD _DTC6 :1; + IO_LWORD _DTC5 :1; + IO_LWORD _DTC4 :1; + IO_LWORD _DTC3 :1; + IO_LWORD _DTC2 :1; + IO_LWORD _DTC1 :1; + IO_LWORD _DTC0 :1; + }bit; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _IS :5; + IO_LWORD _EIS :4; + IO_LWORD _BLK :4; + IO_LWORD _DTC :16; + }bitc; + }DMACA3STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _TYPE1 :1; + IO_LWORD _TYPE0 :1; + IO_LWORD _MOD1 :1; + IO_LWORD _MOD0 :1; + IO_LWORD _WS1 :1; + IO_LWORD _WS0 :1; + IO_LWORD _SADM :1; + IO_LWORD _DADM :1; + IO_LWORD _DTCR :1; + IO_LWORD _SADR :1; + IO_LWORD _DADR :1; + IO_LWORD _ERIE :1; + IO_LWORD _EDIE :1; + IO_LWORD _DSS2 :1; + IO_LWORD _DSS1 :1; + IO_LWORD _DSS0 :1; + IO_LWORD _SASZ7 :1; + IO_LWORD _SASZ6 :1; + IO_LWORD _SASZ5 :1; + IO_LWORD _SASZ4 :1; + IO_LWORD _SASZ3 :1; + IO_LWORD _SASZ2 :1; + IO_LWORD _SASZ1 :1; + IO_LWORD _SASZ0 :1; + IO_LWORD _DASZ7 :1; + IO_LWORD _DASZ6 :1; + IO_LWORD _DASZ5 :1; + IO_LWORD _DASZ4 :1; + IO_LWORD _DASZ3 :1; + IO_LWORD _DASZ2 :1; + IO_LWORD _DASZ1 :1; + IO_LWORD _DASZ0 :1; + }bit; + struct{ + IO_LWORD _TYPE :2; + IO_LWORD _MOD :2; + IO_LWORD _WS :2; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _DSS :3; + IO_LWORD _SASZ :8; + IO_LWORD _DASZ :8; + }bitc; + }DMACB3STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _DENB :1; + IO_LWORD _PAUS :1; + IO_LWORD _STRG :1; + IO_LWORD _IS4 :1; + IO_LWORD _IS3 :1; + IO_LWORD _IS2 :1; + IO_LWORD _IS1 :1; + IO_LWORD _IS0 :1; + IO_LWORD _EIS3 :1; + IO_LWORD _EIS2 :1; + IO_LWORD _EIS1 :1; + IO_LWORD _EIS0 :1; + IO_LWORD _BLK3 :1; + IO_LWORD _BLK2 :1; + IO_LWORD _BLK1 :1; + IO_LWORD _BLK0 :1; + IO_LWORD _DTCF :1; + IO_LWORD _DTCE :1; + IO_LWORD _DTCD :1; + IO_LWORD _DTCC :1; + IO_LWORD _DTCB :1; + IO_LWORD _DTCA :1; + IO_LWORD _DTC9 :1; + IO_LWORD _DTC8 :1; + IO_LWORD _DTC7 :1; + IO_LWORD _DTC6 :1; + IO_LWORD _DTC5 :1; + IO_LWORD _DTC4 :1; + IO_LWORD _DTC3 :1; + IO_LWORD _DTC2 :1; + IO_LWORD _DTC1 :1; + IO_LWORD _DTC0 :1; + }bit; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _IS :5; + IO_LWORD _EIS :4; + IO_LWORD _BLK :4; + IO_LWORD _DTC :16; + }bitc; + }DMACA4STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _TYPE1 :1; + IO_LWORD _TYPE0 :1; + IO_LWORD _MOD1 :1; + IO_LWORD _MOD0 :1; + IO_LWORD _WS1 :1; + IO_LWORD _WS0 :1; + IO_LWORD _SADM :1; + IO_LWORD _DADM :1; + IO_LWORD _DTCR :1; + IO_LWORD _SADR :1; + IO_LWORD _DADR :1; + IO_LWORD _ERIE :1; + IO_LWORD _EDIE :1; + IO_LWORD _DSS2 :1; + IO_LWORD _DSS1 :1; + IO_LWORD _DSS0 :1; + IO_LWORD _SASZ7 :1; + IO_LWORD _SASZ6 :1; + IO_LWORD _SASZ5 :1; + IO_LWORD _SASZ4 :1; + IO_LWORD _SASZ3 :1; + IO_LWORD _SASZ2 :1; + IO_LWORD _SASZ1 :1; + IO_LWORD _SASZ0 :1; + IO_LWORD _DASZ7 :1; + IO_LWORD _DASZ6 :1; + IO_LWORD _DASZ5 :1; + IO_LWORD _DASZ4 :1; + IO_LWORD _DASZ3 :1; + IO_LWORD _DASZ2 :1; + IO_LWORD _DASZ1 :1; + IO_LWORD _DASZ0 :1; + }bit; + struct{ + IO_LWORD _TYPE :2; + IO_LWORD _MOD :2; + IO_LWORD _WS :2; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _DSS :3; + IO_LWORD _SASZ :8; + IO_LWORD _DASZ :8; + }bitc; + }DMACB4STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _DMAE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _PM01 :1; + IO_BYTE _DMAH3 :1; + IO_BYTE _DMAH2 :1; + IO_BYTE _DMAH1 :1; + IO_BYTE _DMAH0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _DMAH :4; + }bitc; + }DMACRSTR; +typedef union{ /* Input Capture 4-7 */ + IO_BYTE byte; + struct{ + IO_BYTE _ICP5 :1; + IO_BYTE _ICP4 :1; + IO_BYTE _ICE5 :1; + IO_BYTE _ICE4 :1; + IO_BYTE _EG51 :1; + IO_BYTE _EG50 :1; + IO_BYTE _EG41 :1; + IO_BYTE _EG40 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _EG5 :2; + IO_BYTE _EG4 :2; + }bitc; + }ICS45STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ICP7 :1; + IO_BYTE _ICP6 :1; + IO_BYTE _ICE7 :1; + IO_BYTE _ICE6 :1; + IO_BYTE _EG71 :1; + IO_BYTE _EG70 :1; + IO_BYTE _EG61 :1; + IO_BYTE _EG60 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _EG7 :2; + IO_BYTE _EG6 :2; + }bitc; + }ICS67STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CP15 :1; + IO_WORD _CP14 :1; + IO_WORD _CP13 :1; + IO_WORD _CP12 :1; + IO_WORD _CP11 :1; + IO_WORD _CP10 :1; + IO_WORD _CP9 :1; + IO_WORD _CP8 :1; + IO_WORD _CP7 :1; + IO_WORD _CP6 :1; + IO_WORD _CP5 :1; + IO_WORD _CP4 :1; + IO_WORD _CP3 :1; + IO_WORD _CP2 :1; + IO_WORD _CP1 :1; + IO_WORD _CP0 :1; + }bit; + }IPCP4STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CP15 :1; + IO_WORD _CP14 :1; + IO_WORD _CP13 :1; + IO_WORD _CP12 :1; + IO_WORD _CP11 :1; + IO_WORD _CP10 :1; + IO_WORD _CP9 :1; + IO_WORD _CP8 :1; + IO_WORD _CP7 :1; + IO_WORD _CP6 :1; + IO_WORD _CP5 :1; + IO_WORD _CP4 :1; + IO_WORD _CP3 :1; + IO_WORD _CP2 :1; + IO_WORD _CP1 :1; + IO_WORD _CP0 :1; + }bit; + }IPCP5STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CP15 :1; + IO_WORD _CP14 :1; + IO_WORD _CP13 :1; + IO_WORD _CP12 :1; + IO_WORD _CP11 :1; + IO_WORD _CP10 :1; + IO_WORD _CP9 :1; + IO_WORD _CP8 :1; + IO_WORD _CP7 :1; + IO_WORD _CP6 :1; + IO_WORD _CP5 :1; + IO_WORD _CP4 :1; + IO_WORD _CP3 :1; + IO_WORD _CP2 :1; + IO_WORD _CP1 :1; + IO_WORD _CP0 :1; + }bit; + }IPCP6STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CP15 :1; + IO_WORD _CP14 :1; + IO_WORD _CP13 :1; + IO_WORD _CP12 :1; + IO_WORD _CP11 :1; + IO_WORD _CP10 :1; + IO_WORD _CP9 :1; + IO_WORD _CP8 :1; + IO_WORD _CP7 :1; + IO_WORD _CP6 :1; + IO_WORD _CP5 :1; + IO_WORD _CP4 :1; + IO_WORD _CP3 :1; + IO_WORD _CP2 :1; + IO_WORD _CP1 :1; + IO_WORD _CP0 :1; + }bit; + }IPCP7STR; +typedef union{ /* Free Running Timer4 */ + IO_WORD word; + struct{ + IO_WORD _T15 :1; + IO_WORD _T14 :1; + IO_WORD _T13 :1; + IO_WORD _T12 :1; + IO_WORD _T11 :1; + IO_WORD _T10 :1; + IO_WORD _T9 :1; + IO_WORD _T8 :1; + IO_WORD _T7 :1; + IO_WORD _T6 :1; + IO_WORD _T5 :1; + IO_WORD _T4 :1; + IO_WORD _T3 :1; + IO_WORD _T2 :1; + IO_WORD _T1 :1; + IO_WORD _T0 :1; + }bit; + }TCDT4STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ECLK :1; + IO_BYTE _IVF :1; + IO_BYTE _IVFE :1; + IO_BYTE _STOP :1; + IO_BYTE _MODE :1; + IO_BYTE _CLR :1; + IO_BYTE _CLK1 :1; + IO_BYTE _CLK0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CLK :2; + }bitc; + }TCCS4STR; +typedef union{ /* Free Running Timer5 */ + IO_WORD word; + struct{ + IO_WORD _T15 :1; + IO_WORD _T14 :1; + IO_WORD _T13 :1; + IO_WORD _T12 :1; + IO_WORD _T11 :1; + IO_WORD _T10 :1; + IO_WORD _T9 :1; + IO_WORD _T8 :1; + IO_WORD _T7 :1; + IO_WORD _T6 :1; + IO_WORD _T5 :1; + IO_WORD _T4 :1; + IO_WORD _T3 :1; + IO_WORD _T2 :1; + IO_WORD _T1 :1; + IO_WORD _T0 :1; + }bit; + }TCDT5STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ECLK :1; + IO_BYTE _IVF :1; + IO_BYTE _IVFE :1; + IO_BYTE _STOP :1; + IO_BYTE _MODE :1; + IO_BYTE _CLR :1; + IO_BYTE _CLK1 :1; + IO_BYTE _CLK0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CLK :2; + }bitc; + }TCCS5STR; +typedef union{ /* Free Running Timer6 */ + IO_WORD word; + struct{ + IO_WORD _T15 :1; + IO_WORD _T14 :1; + IO_WORD _T13 :1; + IO_WORD _T12 :1; + IO_WORD _T11 :1; + IO_WORD _T10 :1; + IO_WORD _T9 :1; + IO_WORD _T8 :1; + IO_WORD _T7 :1; + IO_WORD _T6 :1; + IO_WORD _T5 :1; + IO_WORD _T4 :1; + IO_WORD _T3 :1; + IO_WORD _T2 :1; + IO_WORD _T1 :1; + IO_WORD _T0 :1; + }bit; + }TCDT6STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ECLK :1; + IO_BYTE _IVF :1; + IO_BYTE _IVFE :1; + IO_BYTE _STOP :1; + IO_BYTE _MODE :1; + IO_BYTE _CLR :1; + IO_BYTE _CLK1 :1; + IO_BYTE _CLK0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CLK :2; + }bitc; + }TCCS6STR; +typedef union{ /* Free Running Timer7 */ + IO_WORD word; + struct{ + IO_WORD _T15 :1; + IO_WORD _T14 :1; + IO_WORD _T13 :1; + IO_WORD _T12 :1; + IO_WORD _T11 :1; + IO_WORD _T10 :1; + IO_WORD _T9 :1; + IO_WORD _T8 :1; + IO_WORD _T7 :1; + IO_WORD _T6 :1; + IO_WORD _T5 :1; + IO_WORD _T4 :1; + IO_WORD _T3 :1; + IO_WORD _T2 :1; + IO_WORD _T1 :1; + IO_WORD _T0 :1; + }bit; + }TCDT7STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ECLK :1; + IO_BYTE _IVF :1; + IO_BYTE _IVFE :1; + IO_BYTE _STOP :1; + IO_BYTE _MODE :1; + IO_BYTE _CLR :1; + IO_BYTE _CLK1 :1; + IO_BYTE _CLK0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CLK :2; + }bitc; + }TCCS7STR; +typedef union{ /* Up/Down Counter 0-1 */ + IO_WORD word; + struct{ + IO_WORD _D15 :1; + IO_WORD _D14 :1; + IO_WORD _D13 :1; + IO_WORD _D12 :1; + IO_WORD _D11 :1; + IO_WORD _D10 :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }UDRC10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }UDRC1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }UDRC0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D15 :1; + IO_WORD _D14 :1; + IO_WORD _D13 :1; + IO_WORD _D12 :1; + IO_WORD _D11 :1; + IO_WORD _D10 :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }UDCR10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }UDCR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }UDCR0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _M16E :1; + IO_WORD _CDCF :1; + IO_WORD _CFIE :1; + IO_WORD _CLKS :1; + IO_WORD _CMS1 :1; + IO_WORD _CMS0 :1; + IO_WORD _CES1 :1; + IO_WORD _CES0 :1; + IO_WORD :1; + IO_WORD _CTUT :1; + IO_WORD _UCRE :1; + IO_WORD _RLDE :1; + IO_WORD _UDCLR :1; + IO_WORD _CGSC :1; + IO_WORD _CGE1 :1; + IO_WORD _CGE0 :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CMS :2; + IO_WORD _CES :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CGE :2; + }bitc; + }UDCC0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _M16E :1; + IO_BYTE _CDCF :1; + IO_BYTE _CFIE :1; + IO_BYTE _CLKS :1; + IO_BYTE _CMS1 :1; + IO_BYTE _CMS0 :1; + IO_BYTE _CES1 :1; + IO_BYTE _CES0 :1; + }bit; + struct{ + IO_BYTE :4; + IO_BYTE _CMS :2; + IO_BYTE _CES :2; + }bitc; + }UDCCH0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _CTUT :1; + IO_BYTE _UCRE :1; + IO_BYTE _RLDE :1; + IO_BYTE _UDCLR :1; + IO_BYTE _CGSC :1; + IO_BYTE _CGE1 :1; + IO_BYTE _CGE0 :1; + }bit; + struct{ + IO_BYTE :6; + IO_BYTE _CGE :2; + }bitc; + }UDCCL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CSTR :1; + IO_BYTE _CITE :1; + IO_BYTE _UDIE :1; + IO_BYTE _CMPF :1; + IO_BYTE _OVFF :1; + IO_BYTE _UDFF :1; + IO_BYTE _UDF1 :1; + IO_BYTE _UDF0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _UDF :2; + }bitc; + }UDCS0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _RESV15 :1; + IO_WORD _CDCF :1; + IO_WORD _CFIE :1; + IO_WORD _CLKS :1; + IO_WORD _CMS1 :1; + IO_WORD _CMS0 :1; + IO_WORD _CES1 :1; + IO_WORD _CES0 :1; + IO_WORD :1; + IO_WORD _CTUT :1; + IO_WORD _UCRE :1; + IO_WORD _RLDE :1; + IO_WORD _UDCLR :1; + IO_WORD _CGSC :1; + IO_WORD _CGE1 :1; + IO_WORD _CGE0 :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CMS :2; + IO_WORD _CES :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CGE :2; + }bitc; + }UDCC1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _RESV15 :1; + IO_BYTE _CDCF :1; + IO_BYTE _CFIE :1; + IO_BYTE _CLKS :1; + IO_BYTE _CMS1 :1; + IO_BYTE _CMS0 :1; + IO_BYTE _CES1 :1; + IO_BYTE _CES0 :1; + }bit; + struct{ + IO_BYTE :4; + IO_BYTE _CMS :2; + IO_BYTE _CES :2; + }bitc; + }UDCCH1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _CTUT :1; + IO_BYTE _UCRE :1; + IO_BYTE _RLDE :1; + IO_BYTE _UDCLR :1; + IO_BYTE _CGSC :1; + IO_BYTE _CGE1 :1; + IO_BYTE _CGE0 :1; + }bit; + struct{ + IO_BYTE :6; + IO_BYTE _CGE :2; + }bitc; + }UDCCL1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CSTR :1; + IO_BYTE _CITE :1; + IO_BYTE _UDIE :1; + IO_BYTE _CMPF :1; + IO_BYTE _OVFF :1; + IO_BYTE _UDFF :1; + IO_BYTE _UDF1 :1; + IO_BYTE _UDF0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _UDF :2; + }bitc; + }UDCS1STR; +typedef union{ /* Up/Down Counter 2-3 */ + IO_WORD word; + struct{ + IO_WORD _D15 :1; + IO_WORD _D14 :1; + IO_WORD _D13 :1; + IO_WORD _D12 :1; + IO_WORD _D11 :1; + IO_WORD _D10 :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }UDRC32STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }UDRC3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }UDRC2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D15 :1; + IO_WORD _D14 :1; + IO_WORD _D13 :1; + IO_WORD _D12 :1; + IO_WORD _D11 :1; + IO_WORD _D10 :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }UDCR32STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }UDCR3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }UDCR2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _M16E :1; + IO_WORD _CDCF :1; + IO_WORD _CFIE :1; + IO_WORD _CLKS :1; + IO_WORD _CMS1 :1; + IO_WORD _CMS0 :1; + IO_WORD _CES1 :1; + IO_WORD _CES0 :1; + IO_WORD :1; + IO_WORD _CTUT :1; + IO_WORD _UCRE :1; + IO_WORD _RLDE :1; + IO_WORD _UDCLR :1; + IO_WORD _CGSC :1; + IO_WORD _CGE1 :1; + IO_WORD _CGE0 :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CMS :2; + IO_WORD _CES :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CGE :2; + }bitc; + }UDCC2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _M16E :1; + IO_BYTE _CDCF :1; + IO_BYTE _CFIE :1; + IO_BYTE _CLKS :1; + IO_BYTE _CMS1 :1; + IO_BYTE _CMS0 :1; + IO_BYTE _CES1 :1; + IO_BYTE _CES0 :1; + }bit; + struct{ + IO_BYTE :4; + IO_BYTE _CMS :2; + IO_BYTE _CES :2; + }bitc; + }UDCCH2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _CTUT :1; + IO_BYTE _UCRE :1; + IO_BYTE _RLDE :1; + IO_BYTE _UDCLR :1; + IO_BYTE _CGSC :1; + IO_BYTE _CGE1 :1; + IO_BYTE _CGE0 :1; + }bit; + struct{ + IO_BYTE :6; + IO_BYTE _CGE :2; + }bitc; + }UDCCL2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CSTR :1; + IO_BYTE _CITE :1; + IO_BYTE _UDIE :1; + IO_BYTE _CMPF :1; + IO_BYTE _OVFF :1; + IO_BYTE _UDFF :1; + IO_BYTE _UDF1 :1; + IO_BYTE _UDF0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _UDF :2; + }bitc; + }UDCS2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _RESV15 :1; + IO_WORD _CDCF :1; + IO_WORD _CFIE :1; + IO_WORD _CLKS :1; + IO_WORD _CMS1 :1; + IO_WORD _CMS0 :1; + IO_WORD _CES1 :1; + IO_WORD _CES0 :1; + IO_WORD :1; + IO_WORD _CTUT :1; + IO_WORD _UCRE :1; + IO_WORD _RLDE :1; + IO_WORD _UDCLR :1; + IO_WORD _CGSC :1; + IO_WORD _CGE1 :1; + IO_WORD _CGE0 :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CMS :2; + IO_WORD _CES :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CGE :2; + }bitc; + }UDCC3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _RESV15 :1; + IO_BYTE _CDCF :1; + IO_BYTE _CFIE :1; + IO_BYTE _CLKS :1; + IO_BYTE _CMS1 :1; + IO_BYTE _CMS0 :1; + IO_BYTE _CES1 :1; + IO_BYTE _CES0 :1; + }bit; + struct{ + IO_BYTE :4; + IO_BYTE _CMS :2; + IO_BYTE _CES :2; + }bitc; + }UDCCH3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _CTUT :1; + IO_BYTE _UCRE :1; + IO_BYTE _RLDE :1; + IO_BYTE _UDCLR :1; + IO_BYTE _CGSC :1; + IO_BYTE _CGE1 :1; + IO_BYTE _CGE0 :1; + }bit; + struct{ + IO_BYTE :6; + IO_BYTE _CGE :2; + }bitc; + }UDCCL3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CSTR :1; + IO_BYTE _CITE :1; + IO_BYTE _UDIE :1; + IO_BYTE _CMPF :1; + IO_BYTE _OVFF :1; + IO_BYTE _UDFF :1; + IO_BYTE _UDF1 :1; + IO_BYTE _UDF0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _UDF :2; + }bitc; + }UDCS3STR; +typedef union{ /* PPG Control 12-15 */ + IO_WORD word; + struct{ + IO_WORD _TSEL33 :1; + IO_WORD _TSEL32 :1; + IO_WORD _TSEL31 :1; + IO_WORD _TSEL30 :1; + IO_WORD _TSEL23 :1; + IO_WORD _TSEL22 :1; + IO_WORD _TSEL21 :1; + IO_WORD _TSEL20 :1; + IO_WORD _TSEL13 :1; + IO_WORD _TSEL12 :1; + IO_WORD _TSEL11 :1; + IO_WORD _TSEL10 :1; + IO_WORD _TSEL03 :1; + IO_WORD _TSEL02 :1; + IO_WORD _TSEL01 :1; + IO_WORD _TSEL00 :1; + }bit; + }GCN13STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _EN3 :1; + IO_BYTE _EN2 :1; + IO_BYTE _EN1 :1; + IO_BYTE _EN0 :1; + }bit; + }GCN23STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CNTE :1; + IO_WORD _STGR :1; + IO_WORD _MDSE :1; + IO_WORD _RTRG :1; + IO_WORD _CKS1 :1; + IO_WORD _CKS0 :1; + IO_WORD _PGMS :1; + IO_WORD :1; + IO_WORD _EGS1 :1; + IO_WORD _EGS0 :1; + IO_WORD _IREN :1; + IO_WORD _IRQF :1; + IO_WORD _IRS1 :1; + IO_WORD _IRS0 :1; + IO_WORD :1; + IO_WORD _OSEL :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CKS :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD _EGS :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD _IRS :2; + }bitc; + }PCN12STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CNTE :1; + IO_BYTE _STGR :1; + IO_BYTE _MDSE :1; + IO_BYTE _RTRG :1; + IO_BYTE _CKS1 :1; + IO_BYTE _CKS0 :1; + IO_BYTE _PGMS :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CKS :2; + }bitc; + }PCNH12STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EGS1 :1; + IO_BYTE _EGS0 :1; + IO_BYTE _IREN :1; + IO_BYTE _IRQF :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRS0 :1; + IO_BYTE :1; + IO_BYTE _OSEL :1; + }bit; + struct{ + IO_BYTE _EGS :2; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _IRS :2; + }bitc; + }PCNL12STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CNTE :1; + IO_WORD _STGR :1; + IO_WORD _MDSE :1; + IO_WORD _RTRG :1; + IO_WORD _CKS1 :1; + IO_WORD _CKS0 :1; + IO_WORD _PGMS :1; + IO_WORD :1; + IO_WORD _EGS1 :1; + IO_WORD _EGS0 :1; + IO_WORD _IREN :1; + IO_WORD _IRQF :1; + IO_WORD _IRS1 :1; + IO_WORD _IRS0 :1; + IO_WORD :1; + IO_WORD _OSEL :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CKS :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD _EGS :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD _IRS :2; + }bitc; + }PCN13STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CNTE :1; + IO_BYTE _STGR :1; + IO_BYTE _MDSE :1; + IO_BYTE _RTRG :1; + IO_BYTE _CKS1 :1; + IO_BYTE _CKS0 :1; + IO_BYTE _PGMS :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CKS :2; + }bitc; + }PCNH13STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EGS1 :1; + IO_BYTE _EGS0 :1; + IO_BYTE _IREN :1; + IO_BYTE _IRQF :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRS0 :1; + IO_BYTE :1; + IO_BYTE _OSEL :1; + }bit; + struct{ + IO_BYTE _EGS :2; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _IRS :2; + }bitc; + }PCNL13STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CNTE :1; + IO_WORD _STGR :1; + IO_WORD _MDSE :1; + IO_WORD _RTRG :1; + IO_WORD _CKS1 :1; + IO_WORD _CKS0 :1; + IO_WORD _PGMS :1; + IO_WORD :1; + IO_WORD _EGS1 :1; + IO_WORD _EGS0 :1; + IO_WORD _IREN :1; + IO_WORD _IRQF :1; + IO_WORD _IRS1 :1; + IO_WORD _IRS0 :1; + IO_WORD :1; + IO_WORD _OSEL :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CKS :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD _EGS :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD _IRS :2; + }bitc; + }PCN14STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CNTE :1; + IO_BYTE _STGR :1; + IO_BYTE _MDSE :1; + IO_BYTE _RTRG :1; + IO_BYTE _CKS1 :1; + IO_BYTE _CKS0 :1; + IO_BYTE _PGMS :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CKS :2; + }bitc; + }PCNH14STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EGS1 :1; + IO_BYTE _EGS0 :1; + IO_BYTE _IREN :1; + IO_BYTE _IRQF :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRS0 :1; + IO_BYTE :1; + IO_BYTE _OSEL :1; + }bit; + struct{ + IO_BYTE _EGS :2; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _IRS :2; + }bitc; + }PCNL14STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CNTE :1; + IO_WORD _STGR :1; + IO_WORD _MDSE :1; + IO_WORD _RTRG :1; + IO_WORD _CKS1 :1; + IO_WORD _CKS0 :1; + IO_WORD _PGMS :1; + IO_WORD :1; + IO_WORD _EGS1 :1; + IO_WORD _EGS0 :1; + IO_WORD _IREN :1; + IO_WORD _IRQF :1; + IO_WORD _IRS1 :1; + IO_WORD _IRS0 :1; + IO_WORD :1; + IO_WORD _OSEL :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CKS :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD _EGS :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD _IRS :2; + }bitc; + }PCN15STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CNTE :1; + IO_BYTE _STGR :1; + IO_BYTE _MDSE :1; + IO_BYTE _RTRG :1; + IO_BYTE _CKS1 :1; + IO_BYTE _CKS0 :1; + IO_BYTE _PGMS :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CKS :2; + }bitc; + }PCNH15STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EGS1 :1; + IO_BYTE _EGS0 :1; + IO_BYTE _IREN :1; + IO_BYTE _IRQF :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRS0 :1; + IO_BYTE :1; + IO_BYTE _OSEL :1; + }bit; + struct{ + IO_BYTE _EGS :2; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _IRS :2; + }bitc; + }PCNL15STR; +typedef union{ /* I2C 2 */ + IO_BYTE byte; + struct{ + IO_BYTE _BER :1; + IO_BYTE _BEIE :1; + IO_BYTE _SCC :1; + IO_BYTE _MSS :1; + IO_BYTE _ACK :1; + IO_BYTE _GCAA :1; + IO_BYTE _INTE :1; + IO_BYTE _INT :1; + }bit; + }IBCR2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _BB :1; + IO_BYTE _RSC :1; + IO_BYTE _AL :1; + IO_BYTE _LRB :1; + IO_BYTE _TRX :1; + IO_BYTE _AAS :1; + IO_BYTE _GCA :1; + IO_BYTE _ADT :1; + }bit; + }IBSR2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _TA9 :1; + IO_WORD _TA8 :1; + IO_WORD _TA7 :1; + IO_WORD _TA6 :1; + IO_WORD _TA5 :1; + IO_WORD _TA4 :1; + IO_WORD _TA3 :1; + IO_WORD _TA2 :1; + IO_WORD _TA1 :1; + IO_WORD _TA0 :1; + }bit; + }ITBA2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _TA9 :1; + IO_BYTE _TA8 :1; + }bit; + }ITBAH2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TA7 :1; + IO_BYTE _TA6 :1; + IO_BYTE _TA5 :1; + IO_BYTE _TA4 :1; + IO_BYTE _TA3 :1; + IO_BYTE _TA2 :1; + IO_BYTE _TA1 :1; + IO_BYTE _TA0 :1; + }bit; + }ITBAL2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _ENTB :1; + IO_WORD _RAL :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _TM9 :1; + IO_WORD _TM8 :1; + IO_WORD _TM7 :1; + IO_WORD _TM6 :1; + IO_WORD _TM5 :1; + IO_WORD _TM4 :1; + IO_WORD _TM3 :1; + IO_WORD _TM2 :1; + IO_WORD _TM1 :1; + IO_WORD _TM0 :1; + }bit; + }ITMK2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ENTB :1; + IO_BYTE _RAL :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _TM9 :1; + IO_BYTE _TM8 :1; + }bit; + }ITMKH2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TM7 :1; + IO_BYTE _TM6 :1; + IO_BYTE _TM5 :1; + IO_BYTE _TM4 :1; + IO_BYTE _TM3 :1; + IO_BYTE _TM2 :1; + IO_BYTE _TM1 :1; + IO_BYTE _TM0 :1; + }bit; + }ITMKL2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ENSB :1; + IO_BYTE _SM6 :1; + IO_BYTE _SM5 :1; + IO_BYTE _SM4 :1; + IO_BYTE _SM3 :1; + IO_BYTE _SM2 :1; + IO_BYTE _SM1 :1; + IO_BYTE _SM0 :1; + }bit; + }ISMK2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _SA6 :1; + IO_BYTE _SA5 :1; + IO_BYTE _SA4 :1; + IO_BYTE _SA3 :1; + IO_BYTE _SA2 :1; + IO_BYTE _SA1 :1; + IO_BYTE _SA0 :1; + }bit; + }ISBA2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }IDAR2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _NSF :1; + IO_BYTE _EN :1; + IO_BYTE _CS4 :1; + IO_BYTE _CS3 :1; + IO_BYTE _CS2 :1; + IO_BYTE _CS1 :1; + IO_BYTE _CS0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CS :5; + }bitc; + }ICCR2STR; +typedef union{ /* I2C 3 */ + IO_BYTE byte; + struct{ + IO_BYTE _BER :1; + IO_BYTE _BEIE :1; + IO_BYTE _SCC :1; + IO_BYTE _MSS :1; + IO_BYTE _ACK :1; + IO_BYTE _GCAA :1; + IO_BYTE _INTE :1; + IO_BYTE _INT :1; + }bit; + }IBCR3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _BB :1; + IO_BYTE _RSC :1; + IO_BYTE _AL :1; + IO_BYTE _LRB :1; + IO_BYTE _TRX :1; + IO_BYTE _AAS :1; + IO_BYTE _GCA :1; + IO_BYTE _ADT :1; + }bit; + }IBSR3STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _TA9 :1; + IO_WORD _TA8 :1; + IO_WORD _TA7 :1; + IO_WORD _TA6 :1; + IO_WORD _TA5 :1; + IO_WORD _TA4 :1; + IO_WORD _TA3 :1; + IO_WORD _TA2 :1; + IO_WORD _TA1 :1; + IO_WORD _TA0 :1; + }bit; + }ITBA3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _TA9 :1; + IO_BYTE _TA8 :1; + }bit; + }ITBAH3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TA7 :1; + IO_BYTE _TA6 :1; + IO_BYTE _TA5 :1; + IO_BYTE _TA4 :1; + IO_BYTE _TA3 :1; + IO_BYTE _TA2 :1; + IO_BYTE _TA1 :1; + IO_BYTE _TA0 :1; + }bit; + }ITBAL3STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _ENTB :1; + IO_WORD _RAL :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _TM9 :1; + IO_WORD _TM8 :1; + IO_WORD _TM7 :1; + IO_WORD _TM6 :1; + IO_WORD _TM5 :1; + IO_WORD _TM4 :1; + IO_WORD _TM3 :1; + IO_WORD _TM2 :1; + IO_WORD _TM1 :1; + IO_WORD _TM0 :1; + }bit; + }ITMK3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ENTB :1; + IO_BYTE _RAL :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _TM9 :1; + IO_BYTE _TM8 :1; + }bit; + }ITMKH3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TM7 :1; + IO_BYTE _TM6 :1; + IO_BYTE _TM5 :1; + IO_BYTE _TM4 :1; + IO_BYTE _TM3 :1; + IO_BYTE _TM2 :1; + IO_BYTE _TM1 :1; + IO_BYTE _TM0 :1; + }bit; + }ITMKL3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ENSB :1; + IO_BYTE _SM6 :1; + IO_BYTE _SM5 :1; + IO_BYTE _SM4 :1; + IO_BYTE _SM3 :1; + IO_BYTE _SM2 :1; + IO_BYTE _SM1 :1; + IO_BYTE _SM0 :1; + }bit; + }ISMK3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _SA6 :1; + IO_BYTE _SA5 :1; + IO_BYTE _SA4 :1; + IO_BYTE _SA3 :1; + IO_BYTE _SA2 :1; + IO_BYTE _SA1 :1; + IO_BYTE _SA0 :1; + }bit; + }ISBA3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }IDAR3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _NSF :1; + IO_BYTE _EN :1; + IO_BYTE _CS4 :1; + IO_BYTE _CS3 :1; + IO_BYTE _CS2 :1; + IO_BYTE _CS1 :1; + IO_BYTE _CS0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CS :5; + }bitc; + }ICCR3STR; +typedef union{ /* ROM Select Register */ + IO_WORD word; + struct{ + IO_WORD _D15 :1; + IO_WORD _D14 :1; + IO_WORD _D13 :1; + IO_WORD _D12 :1; + IO_WORD _D11 :1; + IO_WORD _D10 :1; + IO_WORD _D9 :1; + IO_WORD _D8 :1; + IO_WORD _D7 :1; + IO_WORD _D6 :1; + IO_WORD _D5 :1; + IO_WORD _D4 :1; + IO_WORD _D3 :1; + IO_WORD _D2 :1; + IO_WORD _D1 :1; + IO_WORD _D0 :1; + }bit; + }ROMSSTR; +typedef union{ /* Interrupt Control Unit */ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR00STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR01STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR02STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR03STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR04STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR05STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR06STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR07STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR08STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR09STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR11STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR12STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR13STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR14STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR15STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR16STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR17STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR18STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR19STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR20STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR21STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR22STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR23STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR24STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR25STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR26STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR27STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR28STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR29STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR30STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR31STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR32STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR33STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR34STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR35STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR36STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR37STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR38STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR39STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR40STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR41STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR42STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR43STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR44STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR45STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR46STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR47STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR48STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR49STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR50STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR51STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR52STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR53STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR54STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR55STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR56STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR57STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR58STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR59STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR60STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR61STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR62STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICR4 :1; + IO_BYTE _ICR3 :1; + IO_BYTE _ICR2 :1; + IO_BYTE _ICR1 :1; + IO_BYTE _ICR0 :1; + }bit; + }ICR63STR; +typedef union{ /* Clock Control Unit */ + IO_BYTE byte; + struct{ + IO_BYTE _INIT :1; + IO_BYTE _HSTB :1; + IO_BYTE _WDOG :1; + IO_BYTE _ERST :1; + IO_BYTE _SRST :1; + IO_BYTE _LINIT :1; + IO_BYTE _WT1 :1; + IO_BYTE _WT0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _WT :2; + }bitc; + }RSRRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _STOP :1; + IO_BYTE _SLEEP :1; + IO_BYTE _HIZ :1; + IO_BYTE _SRST :1; + IO_BYTE _OS1 :1; + IO_BYTE _OS0 :1; + IO_BYTE _OSCD2 :1; + IO_BYTE _OSCD1 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _OS :2; + IO_BYTE _OSCD :2; + }bitc; + }STCRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TBIF :1; + IO_BYTE _TBIE :1; + IO_BYTE _TBC2 :1; + IO_BYTE _TBC1 :1; + IO_BYTE _TBC0 :1; + IO_BYTE :1; + IO_BYTE _SYNCR :1; + IO_BYTE _SYNCS :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _TBC :3; + }bitc; + }TBCRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }CTBRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _SCKEN :1; + IO_BYTE _PLL1EN :1; + IO_BYTE _CLKS1 :1; + IO_BYTE _CLKS0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CLKS :2; + }bitc; + }CLKRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }WPRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _B3 :1; + IO_BYTE _B2 :1; + IO_BYTE _B1 :1; + IO_BYTE _B0 :1; + IO_BYTE _P3 :1; + IO_BYTE _P2 :1; + IO_BYTE _P1 :1; + IO_BYTE _P0 :1; + }bit; + struct{ + IO_BYTE _B :4; + IO_BYTE _P :4; + }bitc; + }DIVR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _T3 :1; + IO_BYTE _T2 :1; + IO_BYTE _T1 :1; + IO_BYTE _T0 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _T :4; + }bitc; + }DIVR1STR; +typedef union{ /* PLL - Clock Gear Unit: */ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _DVM3 :1; + IO_BYTE _DVM2 :1; + IO_BYTE _DVM1 :1; + IO_BYTE _DVM0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _DVM :4; + }bitc; + }PLLDIVMSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _DVN5 :1; + IO_BYTE _DVN4 :1; + IO_BYTE _DVN3 :1; + IO_BYTE _DVN2 :1; + IO_BYTE _DVN1 :1; + IO_BYTE _DVN0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _DVN :6; + }bitc; + }PLLDIVNSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _DVG3 :1; + IO_BYTE _DVG2 :1; + IO_BYTE _DVG1 :1; + IO_BYTE _DVG0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _DVG :4; + }bitc; + }PLLDIVGSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MLG7 :1; + IO_BYTE _MLG6 :1; + IO_BYTE _MLG5 :1; + IO_BYTE _MLG4 :1; + IO_BYTE _MLG3 :1; + IO_BYTE _MLG2 :1; + IO_BYTE _MLG1 :1; + IO_BYTE _MLG0 :1; + }bit; + struct{ + IO_BYTE _MLG :8; + }bitc; + }PLLMULGSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _IEDN :1; + IO_BYTE _GRDN :1; + IO_BYTE _IEUP :1; + IO_BYTE _GRUP :1; + }bit; + }PLLCTRLSTR; +typedef union{ /* Main/Sub Oscillator Control */ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _FCI :1; + IO_BYTE _RFBEN :1; + IO_BYTE _OSCR :1; + }bit; + }OSCC1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OSCS7 :1; + IO_BYTE _OSCS6 :1; + IO_BYTE _OSCS5 :1; + IO_BYTE _OSCS4 :1; + IO_BYTE _OSCS3 :1; + IO_BYTE _OSCS2 :1; + IO_BYTE _OSCS1 :1; + IO_BYTE _OSCS0 :1; + }bit; + }OSCS1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _FCI :1; + IO_BYTE _RFBEN :1; + IO_BYTE _OSCR :1; + }bit; + }OSCC2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OSCS7 :1; + IO_BYTE _OSCS6 :1; + IO_BYTE _OSCS5 :1; + IO_BYTE _OSCS4 :1; + IO_BYTE _OSCS3 :1; + IO_BYTE _OSCS2 :1; + IO_BYTE _OSCS1 :1; + IO_BYTE _OSCS0 :1; + }bit; + }OSCS2STR; +typedef union{ /* Port Input Enable Control */ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CPORTEN :1; + IO_BYTE _GPORTEN :1; + }bit; + }PORTENSTR; +typedef union{ /* Real Time Clock (Watch Timer) */ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _INTE4 :1; + IO_BYTE _INT4 :1; + }bit; + }WTCERSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _INTE3 :1; + IO_WORD _INT3 :1; + IO_WORD _INTE2 :1; + IO_WORD _INT2 :1; + IO_WORD _INTE1 :1; + IO_WORD _INT1 :1; + IO_WORD _INTE0 :1; + IO_WORD _INT0 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _RUN :1; + IO_WORD _UPDT :1; + IO_WORD :1; + IO_WORD _ST :1; + }bit; + }WTCRSTR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _D20 :1; + IO_LWORD _D19 :1; + IO_LWORD _D18 :1; + IO_LWORD _D17 :1; + IO_LWORD _D16 :1; + IO_LWORD _D15 :1; + IO_LWORD _D14 :1; + IO_LWORD _D13 :1; + IO_LWORD _D12 :1; + IO_LWORD _D11 :1; + IO_LWORD _D10 :1; + IO_LWORD _D9 :1; + IO_LWORD _D8 :1; + IO_LWORD _D7 :1; + IO_LWORD _D6 :1; + IO_LWORD _D5 :1; + IO_LWORD _D4 :1; + IO_LWORD _D3 :1; + IO_LWORD _D2 :1; + IO_LWORD _D1 :1; + IO_LWORD _D0 :1; + }bit; + }WTBRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _H4 :1; + IO_BYTE _H3 :1; + IO_BYTE _H2 :1; + IO_BYTE _H1 :1; + IO_BYTE _H0 :1; + }bit; + }WTHRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _M5 :1; + IO_BYTE _M4 :1; + IO_BYTE _M3 :1; + IO_BYTE _M2 :1; + IO_BYTE _M1 :1; + IO_BYTE _M0 :1; + }bit; + }WTMRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _S5 :1; + IO_BYTE _S4 :1; + IO_BYTE _S3 :1; + IO_BYTE _S2 :1; + IO_BYTE _S1 :1; + IO_BYTE _S0 :1; + }bit; + }WTSRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SCKS :1; + IO_BYTE _MM :1; + IO_BYTE _SM :1; + IO_BYTE _RCE :1; + IO_BYTE _MSVE :1; + IO_BYTE _SSVE :1; + IO_BYTE _SRST :1; + IO_BYTE _OUTE :1; + }bit; + }CSVCRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EDSUEN :1; + IO_BYTE _PLLLOCK :1; + IO_BYTE _RCSEL :1; + IO_BYTE _MONCKI :1; + IO_BYTE _CSC3 :1; + IO_BYTE _CSC2 :1; + IO_BYTE _CSC1 :1; + IO_BYTE _CSC0 :1; + }bit; + struct{ + IO_BYTE :4; + IO_BYTE _CSC :4; + }bitc; + }CSCFGSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CMPRE3 :1; + IO_BYTE _CMPRE2 :1; + IO_BYTE _CMPRE1 :1; + IO_BYTE _CMPRE0 :1; + IO_BYTE _CMSEL3 :1; + IO_BYTE _CMSEL2 :1; + IO_BYTE _CMSEL1 :1; + IO_BYTE _CMSEL0 :1; + }bit; + struct{ + IO_BYTE _CMPRE :4; + IO_BYTE _CMSEL :4; + }bitc; + }CMCFGSTR; +typedef union{ /* Calibration Unit of Sub Oszillation */ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _STRT :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _INT :1; + IO_WORD _INTEN :1; + }bit; + }CUCRSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _TDD15 :1; + IO_WORD _TDD14 :1; + IO_WORD _TDD13 :1; + IO_WORD _TDD12 :1; + IO_WORD _TDD11 :1; + IO_WORD _TDD10 :1; + IO_WORD _TDD9 :1; + IO_WORD _TDD8 :1; + IO_WORD _TDD7 :1; + IO_WORD _TDD6 :1; + IO_WORD _TDD5 :1; + IO_WORD _TDD4 :1; + IO_WORD _TDD3 :1; + IO_WORD _TDD2 :1; + IO_WORD _TDD1 :1; + IO_WORD _TDD0 :1; + }bit; + }CUTDSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _TDR23 :1; + IO_WORD _TDR22 :1; + IO_WORD _TDR21 :1; + IO_WORD _TDR20 :1; + IO_WORD _TDR19 :1; + IO_WORD _TDR18 :1; + IO_WORD _TDR17 :1; + IO_WORD _TDR16 :1; + }bit; + }CUTR1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _TDR15 :1; + IO_WORD _TDR14 :1; + IO_WORD _TDR13 :1; + IO_WORD _TDR12 :1; + IO_WORD _TDR11 :1; + IO_WORD _TDR10 :1; + IO_WORD _TDR9 :1; + IO_WORD _TDR8 :1; + IO_WORD _TDR7 :1; + IO_WORD _TDR6 :1; + IO_WORD _TDR5 :1; + IO_WORD _TDR4 :1; + IO_WORD _TDR3 :1; + IO_WORD _TDR2 :1; + IO_WORD _TDR1 :1; + IO_WORD _TDR0 :1; + }bit; + }CUTR2STR; +typedef union{ /* Clock Modulator */ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD _MP13 :1; + IO_WORD _MP12 :1; + IO_WORD _MP11 :1; + IO_WORD _MP10 :1; + IO_WORD _MP9 :1; + IO_WORD _MP8 :1; + IO_WORD _MP7 :1; + IO_WORD _MP6 :1; + IO_WORD _MP5 :1; + IO_WORD _MP4 :1; + IO_WORD _MP3 :1; + IO_WORD _MP2 :1; + IO_WORD _MP1 :1; + IO_WORD _MP0 :1; + }bit; + }CMPRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _FMODRUN :1; + IO_BYTE :1; + IO_BYTE _FMOD :1; + IO_BYTE _PDX :1; + }bit; + }CMCRSTR; +typedef union{ /* CAN clock control */ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CPCKS1 :1; + IO_BYTE _CPCKS0 :1; + IO_BYTE _DVC3 :1; + IO_BYTE _DVC2 :1; + IO_BYTE _DVC1 :1; + IO_BYTE _DVC0 :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _CPCKS :2; + IO_BYTE _DVC :4; + }bitc; + }CANPRESTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CANCKD5 :1; + IO_BYTE _CANCKD4 :1; + IO_BYTE _CANCKD3 :1; + IO_BYTE _CANCKD2 :1; + IO_BYTE _CANCKD1 :1; + IO_BYTE _CANCKD0 :1; + }bit; + }CANCKDSTR; +typedef union{ /* LV Detection / Hardware-Watchdog */ + IO_BYTE byte; + struct{ + IO_BYTE _LVESEL3 :1; + IO_BYTE _LVESEL2 :1; + IO_BYTE _LVESEL1 :1; + IO_BYTE _LVESEL0 :1; + IO_BYTE _LVISEL3 :1; + IO_BYTE _LVISEL2 :1; + IO_BYTE _LVISEL1 :1; + IO_BYTE _LVISEL0 :1; + }bit; + struct{ + IO_BYTE _LVESEL :4; + IO_BYTE _LVISEL :4; + }bitc; + }LVSELSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _LVSEL :1; + IO_BYTE _LVEPD :1; + IO_BYTE _LVIPD :1; + IO_BYTE _LVREN :1; + IO_BYTE :1; + IO_BYTE _LVIEN :1; + IO_BYTE _LVIRQ :1; + }bit; + }LVDETSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ED1 :1; + IO_BYTE _ED0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ED :2; + }bitc; + }HWWDESTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CL :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CPUF :1; + }bit; + }HWWDSTR; +typedef union{ /* Main-/Sub-Oscillatio Stabilization Timer */ + IO_BYTE byte; + struct{ + IO_BYTE _WIF :1; + IO_BYTE _WIE :1; + IO_BYTE _WEN :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _WS1 :1; + IO_BYTE _WS0 :1; + IO_BYTE _WCL :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _WS :2; + }bitc; + }OSCRHSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _WIF :1; + IO_BYTE _WIE :1; + IO_BYTE _WEN :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _WS1 :1; + IO_BYTE _WS0 :1; + IO_BYTE _WCL :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _WS :2; + }bitc; + }WPCRHSTR; +typedef union{ /* Main-/Sub-Oscillatio Standby Control */ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _OSCDS1 :1; + }bit; + }OSCCRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _FLASHSEL :1; + IO_BYTE _MAINSEL :1; + IO_BYTE _SUBSEL3 :1; + IO_BYTE _SUBSEL2 :1; + IO_BYTE _SUBSEL1 :1; + IO_BYTE _SUBSEL0 :1; + }bit; + struct{ + IO_BYTE :4; + IO_BYTE _SUBSEL :4; + }bitc; + }REGSELSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _MSTBO :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _MAINKPEN :1; + IO_BYTE _MAINDSBL :1; + }bit; + }REGCTRSTR; +typedef union{ /* External Bus/Chip Select Registers */ + IO_WORD word; + struct{ + IO_WORD _A31 :1; + IO_WORD _A30 :1; + IO_WORD _A29 :1; + IO_WORD _A28 :1; + IO_WORD _A27 :1; + IO_WORD _A26 :1; + IO_WORD _A25 :1; + IO_WORD _A24 :1; + IO_WORD _A23 :1; + IO_WORD _A22 :1; + IO_WORD _A21 :1; + IO_WORD _A20 :1; + IO_WORD _A19 :1; + IO_WORD _A18 :1; + IO_WORD _A17 :1; + IO_WORD _A16 :1; + }bit; + }ASR0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _ASZ3 :1; + IO_WORD _ASZ2 :1; + IO_WORD _ASZ1 :1; + IO_WORD _ASZ0 :1; + IO_WORD _DBW1 :1; + IO_WORD _DBW0 :1; + IO_WORD _BST1 :1; + IO_WORD _BST0 :1; + IO_WORD _SREN :1; + IO_WORD _PFEN :1; + IO_WORD _WREN :1; + IO_WORD :1; + IO_WORD _TYP3 :1; + IO_WORD _TYP2 :1; + IO_WORD _TYP1 :1; + IO_WORD _TYP0 :1; + }bit; + struct{ + IO_WORD _ASZ :4; + IO_WORD _DBW :2; + IO_WORD _BST :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _TYP :4; + }bitc; + }ACR0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _A31 :1; + IO_WORD _A30 :1; + IO_WORD _A29 :1; + IO_WORD _A28 :1; + IO_WORD _A27 :1; + IO_WORD _A26 :1; + IO_WORD _A25 :1; + IO_WORD _A24 :1; + IO_WORD _A23 :1; + IO_WORD _A22 :1; + IO_WORD _A21 :1; + IO_WORD _A20 :1; + IO_WORD _A19 :1; + IO_WORD _A18 :1; + IO_WORD _A17 :1; + IO_WORD _A16 :1; + }bit; + }ASR1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _ASZ3 :1; + IO_WORD _ASZ2 :1; + IO_WORD _ASZ1 :1; + IO_WORD _ASZ0 :1; + IO_WORD _DBW1 :1; + IO_WORD _DBW0 :1; + IO_WORD _BST1 :1; + IO_WORD _BST0 :1; + IO_WORD _SREN :1; + IO_WORD _PFEN :1; + IO_WORD _WREN :1; + IO_WORD _LEND :1; + IO_WORD _TYP3 :1; + IO_WORD _TYP2 :1; + IO_WORD _TYP1 :1; + IO_WORD _TYP0 :1; + }bit; + struct{ + IO_WORD _ASZ :4; + IO_WORD _DBW :2; + IO_WORD _BST :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _TYP :4; + }bitc; + }ACR1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _A31 :1; + IO_WORD _A30 :1; + IO_WORD _A29 :1; + IO_WORD _A28 :1; + IO_WORD _A27 :1; + IO_WORD _A26 :1; + IO_WORD _A25 :1; + IO_WORD _A24 :1; + IO_WORD _A23 :1; + IO_WORD _A22 :1; + IO_WORD _A21 :1; + IO_WORD _A20 :1; + IO_WORD _A19 :1; + IO_WORD _A18 :1; + IO_WORD _A17 :1; + IO_WORD _A16 :1; + }bit; + }ASR2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _ASZ3 :1; + IO_WORD _ASZ2 :1; + IO_WORD _ASZ1 :1; + IO_WORD _ASZ0 :1; + IO_WORD _DBW1 :1; + IO_WORD _DBW0 :1; + IO_WORD _BST1 :1; + IO_WORD _BST0 :1; + IO_WORD _SREN :1; + IO_WORD _PFEN :1; + IO_WORD _WREN :1; + IO_WORD _LEND :1; + IO_WORD _TYP3 :1; + IO_WORD _TYP2 :1; + IO_WORD _TYP1 :1; + IO_WORD _TYP0 :1; + }bit; + struct{ + IO_WORD _ASZ :4; + IO_WORD _DBW :2; + IO_WORD _BST :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _TYP :4; + }bitc; + }ACR2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _A31 :1; + IO_WORD _A30 :1; + IO_WORD _A29 :1; + IO_WORD _A28 :1; + IO_WORD _A27 :1; + IO_WORD _A26 :1; + IO_WORD _A25 :1; + IO_WORD _A24 :1; + IO_WORD _A23 :1; + IO_WORD _A22 :1; + IO_WORD _A21 :1; + IO_WORD _A20 :1; + IO_WORD _A19 :1; + IO_WORD _A18 :1; + IO_WORD _A17 :1; + IO_WORD _A16 :1; + }bit; + }ASR3STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _ASZ3 :1; + IO_WORD _ASZ2 :1; + IO_WORD _ASZ1 :1; + IO_WORD _ASZ0 :1; + IO_WORD _DBW1 :1; + IO_WORD _DBW0 :1; + IO_WORD _BST1 :1; + IO_WORD _BST0 :1; + IO_WORD _SREN :1; + IO_WORD _PFEN :1; + IO_WORD _WREN :1; + IO_WORD _LEND :1; + IO_WORD _TYP3 :1; + IO_WORD _TYP2 :1; + IO_WORD _TYP1 :1; + IO_WORD _TYP0 :1; + }bit; + struct{ + IO_WORD _ASZ :4; + IO_WORD _DBW :2; + IO_WORD _BST :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _TYP :4; + }bitc; + }ACR3STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _A31 :1; + IO_WORD _A30 :1; + IO_WORD _A29 :1; + IO_WORD _A28 :1; + IO_WORD _A27 :1; + IO_WORD _A26 :1; + IO_WORD _A25 :1; + IO_WORD _A24 :1; + IO_WORD _A23 :1; + IO_WORD _A22 :1; + IO_WORD _A21 :1; + IO_WORD _A20 :1; + IO_WORD _A19 :1; + IO_WORD _A18 :1; + IO_WORD _A17 :1; + IO_WORD _A16 :1; + }bit; + }ASR4STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _ASZ3 :1; + IO_WORD _ASZ2 :1; + IO_WORD _ASZ1 :1; + IO_WORD _ASZ0 :1; + IO_WORD _DBW1 :1; + IO_WORD _DBW0 :1; + IO_WORD _BST1 :1; + IO_WORD _BST0 :1; + IO_WORD _SREN :1; + IO_WORD _PFEN :1; + IO_WORD _WREN :1; + IO_WORD _LEND :1; + IO_WORD _TYP3 :1; + IO_WORD _TYP2 :1; + IO_WORD _TYP1 :1; + IO_WORD _TYP0 :1; + }bit; + struct{ + IO_WORD _ASZ :4; + IO_WORD _DBW :2; + IO_WORD _BST :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _TYP :4; + }bitc; + }ACR4STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _A31 :1; + IO_WORD _A30 :1; + IO_WORD _A29 :1; + IO_WORD _A28 :1; + IO_WORD _A27 :1; + IO_WORD _A26 :1; + IO_WORD _A25 :1; + IO_WORD _A24 :1; + IO_WORD _A23 :1; + IO_WORD _A22 :1; + IO_WORD _A21 :1; + IO_WORD _A20 :1; + IO_WORD _A19 :1; + IO_WORD _A18 :1; + IO_WORD _A17 :1; + IO_WORD _A16 :1; + }bit; + }ASR5STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _ASZ3 :1; + IO_WORD _ASZ2 :1; + IO_WORD _ASZ1 :1; + IO_WORD _ASZ0 :1; + IO_WORD _DBW1 :1; + IO_WORD _DBW0 :1; + IO_WORD _BST1 :1; + IO_WORD _BST0 :1; + IO_WORD _SREN :1; + IO_WORD _PFEN :1; + IO_WORD _WREN :1; + IO_WORD _LEND :1; + IO_WORD _TYP3 :1; + IO_WORD _TYP2 :1; + IO_WORD _TYP1 :1; + IO_WORD _TYP0 :1; + }bit; + struct{ + IO_WORD _ASZ :4; + IO_WORD _DBW :2; + IO_WORD _BST :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _TYP :4; + }bitc; + }ACR5STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _A31 :1; + IO_WORD _A30 :1; + IO_WORD _A29 :1; + IO_WORD _A28 :1; + IO_WORD _A27 :1; + IO_WORD _A26 :1; + IO_WORD _A25 :1; + IO_WORD _A24 :1; + IO_WORD _A23 :1; + IO_WORD _A22 :1; + IO_WORD _A21 :1; + IO_WORD _A20 :1; + IO_WORD _A19 :1; + IO_WORD _A18 :1; + IO_WORD _A17 :1; + IO_WORD _A16 :1; + }bit; + }ASR6STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _ASZ3 :1; + IO_WORD _ASZ2 :1; + IO_WORD _ASZ1 :1; + IO_WORD _ASZ0 :1; + IO_WORD _DBW1 :1; + IO_WORD _DBW0 :1; + IO_WORD _BST1 :1; + IO_WORD _BST0 :1; + IO_WORD _SREN :1; + IO_WORD _PFEN :1; + IO_WORD _WREN :1; + IO_WORD _LEND :1; + IO_WORD _TYP3 :1; + IO_WORD _TYP2 :1; + IO_WORD _TYP1 :1; + IO_WORD _TYP0 :1; + }bit; + struct{ + IO_WORD _ASZ :4; + IO_WORD _DBW :2; + IO_WORD _BST :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _TYP :4; + }bitc; + }ACR6STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _A31 :1; + IO_WORD _A30 :1; + IO_WORD _A29 :1; + IO_WORD _A28 :1; + IO_WORD _A27 :1; + IO_WORD _A26 :1; + IO_WORD _A25 :1; + IO_WORD _A24 :1; + IO_WORD _A23 :1; + IO_WORD _A22 :1; + IO_WORD _A21 :1; + IO_WORD _A20 :1; + IO_WORD _A19 :1; + IO_WORD _A18 :1; + IO_WORD _A17 :1; + IO_WORD _A16 :1; + }bit; + }ASR7STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _ASZ3 :1; + IO_WORD _ASZ2 :1; + IO_WORD _ASZ1 :1; + IO_WORD _ASZ0 :1; + IO_WORD _DBW1 :1; + IO_WORD _DBW0 :1; + IO_WORD _BST1 :1; + IO_WORD _BST0 :1; + IO_WORD _SREN :1; + IO_WORD _PFEN :1; + IO_WORD _WREN :1; + IO_WORD _LEND :1; + IO_WORD _TYP3 :1; + IO_WORD _TYP2 :1; + IO_WORD _TYP1 :1; + IO_WORD _TYP0 :1; + }bit; + struct{ + IO_WORD _ASZ :4; + IO_WORD _DBW :2; + IO_WORD _BST :2; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _TYP :4; + }bitc; + }ACR7STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _W15 :1; + IO_WORD _W14 :1; + IO_WORD _W13 :1; + IO_WORD _W12 :1; + IO_WORD _W11 :1; + IO_WORD _W10 :1; + IO_WORD _W9 :1; + IO_WORD _W8 :1; + IO_WORD _W7 :1; + IO_WORD _W6 :1; + IO_WORD _W5 :1; + IO_WORD _W4 :1; + IO_WORD _W3 :1; + IO_WORD _W2 :1; + IO_WORD _W1 :1; + IO_WORD _W0 :1; + }bit; + }AWR0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _W15 :1; + IO_WORD _W14 :1; + IO_WORD _W13 :1; + IO_WORD _W12 :1; + IO_WORD _W11 :1; + IO_WORD _W10 :1; + IO_WORD _W9 :1; + IO_WORD _W8 :1; + IO_WORD _W7 :1; + IO_WORD _W6 :1; + IO_WORD _W5 :1; + IO_WORD _W4 :1; + IO_WORD _W3 :1; + IO_WORD _W2 :1; + IO_WORD _W1 :1; + IO_WORD _W0 :1; + }bit; + }AWR1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _W15 :1; + IO_WORD _W14 :1; + IO_WORD _W13 :1; + IO_WORD _W12 :1; + IO_WORD _W11 :1; + IO_WORD _W10 :1; + IO_WORD _W9 :1; + IO_WORD _W8 :1; + IO_WORD _W7 :1; + IO_WORD _W6 :1; + IO_WORD _W5 :1; + IO_WORD _W4 :1; + IO_WORD _W3 :1; + IO_WORD _W2 :1; + IO_WORD _W1 :1; + IO_WORD _W0 :1; + }bit; + }AWR2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _W15 :1; + IO_WORD _W14 :1; + IO_WORD _W13 :1; + IO_WORD _W12 :1; + IO_WORD _W11 :1; + IO_WORD _W10 :1; + IO_WORD _W9 :1; + IO_WORD _W8 :1; + IO_WORD _W7 :1; + IO_WORD _W6 :1; + IO_WORD _W5 :1; + IO_WORD _W4 :1; + IO_WORD _W3 :1; + IO_WORD _W2 :1; + IO_WORD _W1 :1; + IO_WORD _W0 :1; + }bit; + }AWR3STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _W15 :1; + IO_WORD _W14 :1; + IO_WORD _W13 :1; + IO_WORD _W12 :1; + IO_WORD _W11 :1; + IO_WORD _W10 :1; + IO_WORD _W9 :1; + IO_WORD _W8 :1; + IO_WORD _W7 :1; + IO_WORD _W6 :1; + IO_WORD _W5 :1; + IO_WORD _W4 :1; + IO_WORD _W3 :1; + IO_WORD _W2 :1; + IO_WORD _W1 :1; + IO_WORD _W0 :1; + }bit; + }AWR4STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _W15 :1; + IO_WORD _W14 :1; + IO_WORD _W13 :1; + IO_WORD _W12 :1; + IO_WORD _W11 :1; + IO_WORD _W10 :1; + IO_WORD _W9 :1; + IO_WORD _W8 :1; + IO_WORD _W7 :1; + IO_WORD _W6 :1; + IO_WORD _W5 :1; + IO_WORD _W4 :1; + IO_WORD _W3 :1; + IO_WORD _W2 :1; + IO_WORD _W1 :1; + IO_WORD _W0 :1; + }bit; + }AWR5STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _W15 :1; + IO_WORD _W14 :1; + IO_WORD _W13 :1; + IO_WORD _W12 :1; + IO_WORD _W11 :1; + IO_WORD _W10 :1; + IO_WORD _W9 :1; + IO_WORD _W8 :1; + IO_WORD _W7 :1; + IO_WORD _W6 :1; + IO_WORD _W5 :1; + IO_WORD _W4 :1; + IO_WORD _W3 :1; + IO_WORD _W2 :1; + IO_WORD _W1 :1; + IO_WORD _W0 :1; + }bit; + }AWR6STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _W15 :1; + IO_WORD _W14 :1; + IO_WORD _W13 :1; + IO_WORD _W12 :1; + IO_WORD _W11 :1; + IO_WORD _W10 :1; + IO_WORD _W9 :1; + IO_WORD _W8 :1; + IO_WORD _W7 :1; + IO_WORD _W6 :1; + IO_WORD _W5 :1; + IO_WORD _W4 :1; + IO_WORD _W3 :1; + IO_WORD _W2 :1; + IO_WORD _W1 :1; + IO_WORD _W0 :1; + }bit; + }AWR7STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _PSZ2 :1; + IO_BYTE _PSZ1 :1; + IO_BYTE _PSZ0 :1; + IO_BYTE _WBST :1; + IO_BYTE _BANK :1; + IO_BYTE _ABS1 :1; + IO_BYTE _ABS0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE _PSZ :3; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ABS :2; + }bitc; + }MCRASTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _PSZ2 :1; + IO_BYTE _PSZ1 :1; + IO_BYTE _PSZ0 :1; + IO_BYTE _WBST :1; + IO_BYTE _BANK :1; + IO_BYTE _ABS1 :1; + IO_BYTE _ABS0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE _PSZ :3; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ABS :2; + }bitc; + }MCRBSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _RYE0 :1; + IO_BYTE _HLD0 :1; + IO_BYTE _WR01 :1; + IO_BYTE _WR00 :1; + IO_BYTE _IW03 :1; + IO_BYTE _IW02 :1; + IO_BYTE _IW01 :1; + IO_BYTE _IW00 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _WR0 :2; + IO_BYTE _IW0 :4; + }bitc; + }IOWR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _RYE1 :1; + IO_BYTE _HLD1 :1; + IO_BYTE _WR11 :1; + IO_BYTE _WR10 :1; + IO_BYTE _IW13 :1; + IO_BYTE _IW12 :1; + IO_BYTE _IW11 :1; + IO_BYTE _IW10 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _WR1 :2; + IO_BYTE _IW1 :4; + }bitc; + }IOWR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _RYE2 :1; + IO_BYTE _HLD2 :1; + IO_BYTE _WR21 :1; + IO_BYTE _WR20 :1; + IO_BYTE _IW23 :1; + IO_BYTE _IW22 :1; + IO_BYTE _IW21 :1; + IO_BYTE _IW20 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _WR2 :2; + IO_BYTE _IW2 :4; + }bitc; + }IOWR2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _RYE3 :1; + IO_BYTE _HLD3 :1; + IO_BYTE _WR31 :1; + IO_BYTE _WR30 :1; + IO_BYTE _IW33 :1; + IO_BYTE _IW32 :1; + IO_BYTE _IW31 :1; + IO_BYTE _IW30 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _WR3 :2; + IO_BYTE _IW3 :4; + }bitc; + }IOWR3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CSE7 :1; + IO_BYTE _CSE6 :1; + IO_BYTE _CSE5 :1; + IO_BYTE _CSE4 :1; + IO_BYTE _CSE3 :1; + IO_BYTE _CSE2 :1; + IO_BYTE _CSE1 :1; + IO_BYTE _CSE0 :1; + }bit; + }CSERSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CHE7 :1; + IO_BYTE _CHE6 :1; + IO_BYTE _CHE5 :1; + IO_BYTE _CHE4 :1; + IO_BYTE _CHE3 :1; + IO_BYTE _CHE2 :1; + IO_BYTE _CHE1 :1; + IO_BYTE _CHE0 :1; + }bit; + }CHERSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _BREN :1; + IO_BYTE _PSUS :1; + IO_BYTE _PCLR :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _RDW1 :1; + IO_BYTE _RDW0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _RDW :2; + }bitc; + }TCRSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _SELF :1; + IO_WORD _RRLD :1; + IO_WORD _RFINT5 :1; + IO_WORD _RFINT4 :1; + IO_WORD _RDINT3 :1; + IO_WORD _RFINT2 :1; + IO_WORD _RFINT1 :1; + IO_WORD _RFINT0 :1; + IO_WORD _BRST :1; + IO_WORD _RFC2 :1; + IO_WORD _RFC1 :1; + IO_WORD _RFC0 :1; + IO_WORD _PON :1; + IO_WORD _TRC2 :1; + IO_WORD _TRC1 :1; + IO_WORD _TRC0 :1; + }bit; + struct{ + IO_WORD :2; + IO_WORD _RFINT :6; + IO_WORD :1; + IO_WORD _RFC :3; + IO_WORD :1; + IO_WORD _TRC :3; + }bitc; + }RCRSTR; +typedef union{ /* Mode Register */ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ROMA :1; + IO_BYTE _WTH1 :1; + IO_BYTE _WTH0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _WTH :2; + }bitc; + }MODRSTR; +typedef union{ /* R-bus Port Data Direct Read Register */ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDRD00STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDRD01STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDRD02STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDRD03STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDRD04STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDRD05STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDRD06STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDRD07STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDRD08STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDRD09STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE :1; + }bit; + }PDRD10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDRD13STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDRD14STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDRD15STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDRD16STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }PDRD17STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDRD18STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDRD19STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDRD20STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE :1; + IO_BYTE _D0 :1; + }bit; + }PDRD22STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDRD23STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDRD24STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDRD25STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDRD26STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDRD27STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PDRD29STR; +typedef union{ /* R-bus Port Direction Register */ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }DDR00STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }DDR01STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }DDR02STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }DDR03STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }DDR04STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }DDR05STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }DDR06STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }DDR07STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }DDR08STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }DDR09STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE :1; + }bit; + }DDR10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }DDR13STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }DDR14STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }DDR15STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }DDR16STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }DDR17STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }DDR18STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }DDR19STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }DDR20STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE :1; + IO_BYTE _D0 :1; + }bit; + }DDR22STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }DDR23STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }DDR24STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }DDR25STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }DDR26STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }DDR27STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }DDR29STR; +typedef union{ /* R-bus Port Function Register */ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PFR00STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PFR01STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PFR02STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PFR03STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PFR04STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PFR05STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PFR06STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PFR07STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PFR08STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PFR09STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE :1; + }bit; + }PFR10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PFR13STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PFR14STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PFR15STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PFR16STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }PFR17STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PFR18STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PFR19STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PFR20STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE :1; + IO_BYTE _D0 :1; + }bit; + }PFR22STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PFR23STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PFR24STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PFR25STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PFR26STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PFR27STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PFR29STR; +typedef union{ /* R-bus Port Extra Function Register */ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }EPFR10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }EPFR13STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }EPFR14STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }EPFR15STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }EPFR16STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }EPFR18STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }EPFR19STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }EPFR20STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }EPFR26STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }EPFR27STR; +typedef union{ /* R-bus Port Output Drive Select Register */ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PODR00STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PODR01STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PODR02STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PODR03STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PODR04STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PODR05STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PODR06STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PODR07STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PODR08STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PODR09STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE :1; + }bit; + }PODR10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PODR13STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PODR14STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PODR15STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PODR16STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }PODR17STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PODR18STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PODR19STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PODR20STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE :1; + IO_BYTE _D0 :1; + }bit; + }PODR22STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PODR23STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PODR24STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PODR25STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PODR26STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PODR27STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PODR29STR; +typedef union{ /* R-bus Port Input Level Select Register */ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PILR00STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PILR01STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PILR02STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PILR03STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PILR04STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PILR05STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PILR06STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PILR07STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PILR08STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PILR09STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE :1; + }bit; + }PILR10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PILR13STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PILR14STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PILR15STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PILR16STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }PILR17STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PILR18STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PILR19STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PILR20STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE :1; + IO_BYTE _D0 :1; + }bit; + }PILR22STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PILR23STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PILR24STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PILR25STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PILR26STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PILR27STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PILR29STR; +typedef union{ /* R-bus Port Extra Input Level Select Register */ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }EPILR00STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }EPILR01STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }EPILR02STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }EPILR03STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }EPILR04STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }EPILR05STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }EPILR06STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }EPILR07STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }EPILR08STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }EPILR09STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE :1; + }bit; + }EPILR10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }EPILR13STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }EPILR14STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }EPILR15STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }EPILR16STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }EPILR17STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }EPILR18STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }EPILR19STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }EPILR20STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE :1; + IO_BYTE _D0 :1; + }bit; + }EPILR22STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }EPILR23STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }EPILR24STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }EPILR25STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }EPILR26STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }EPILR27STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }EPILR29STR; +typedef union{ /* R-bus Port Pull-Up/Down Enable Register */ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPER00STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPER01STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPER02STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPER03STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPER04STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPER05STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPER06STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPER07STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPER08STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPER09STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE :1; + }bit; + }PPER10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPER13STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPER14STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPER15STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPER16STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }PPER17STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPER18STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPER19STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPER20STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE :1; + IO_BYTE _D0 :1; + }bit; + }PPER22STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPER23STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPER24STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPER25STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPER26STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPER27STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPER29STR; +typedef union{ /* R-bus Port Pull-Up/Down Control Register */ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPCR00STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPCR01STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPCR02STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPCR03STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPCR04STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPCR05STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPCR06STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPCR07STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPCR08STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPCR09STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE :1; + }bit; + }PPCR10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPCR13STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPCR14STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPCR15STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPCR16STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }PPCR17STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPCR18STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPCR19STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPCR20STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE :1; + IO_BYTE _D2 :1; + IO_BYTE :1; + IO_BYTE _D0 :1; + }bit; + }PPCR22STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPCR23STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPCR24STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPCR25STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPCR26STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPCR27STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D7 :1; + IO_BYTE _D6 :1; + IO_BYTE _D5 :1; + IO_BYTE _D4 :1; + IO_BYTE _D3 :1; + IO_BYTE _D2 :1; + IO_BYTE _D1 :1; + IO_BYTE _D0 :1; + }bit; + }PPCR29STR; +typedef union{ /* Flash Memory/I-Cache Control Register */ + IO_BYTE byte; + struct{ + IO_BYTE _ASYNC :1; + IO_BYTE _FIXE :1; + IO_BYTE _BIRE :1; + IO_BYTE _RDYEG :1; + IO_BYTE _RDY :1; + IO_BYTE _RDYI :1; + IO_BYTE _RW16 :1; + IO_BYTE _LPM :1; + }bit; + }FMCSSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _LOCK :1; + IO_BYTE _PHASE :1; + IO_BYTE _PF2I :1; + IO_BYTE _RD64 :1; + }bit; + }FMCRSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _REN :1; + IO_WORD _TAGE :1; + IO_WORD _FLUSH :1; + IO_WORD _DBEN :1; + IO_WORD _PFEN :1; + IO_WORD _PFMC :1; + IO_WORD _LOCK :1; + IO_WORD _ENAB :1; + IO_WORD _SIZE1 :1; + IO_WORD _SIZE0 :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _SIZE :2; + }bitc; + }FCHCRSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _WTP1 :1; + IO_WORD _WTP0 :1; + IO_WORD _WEXH1 :1; + IO_WORD _WEXH0 :1; + IO_WORD _WTC3 :1; + IO_WORD _WTC2 :1; + IO_WORD _WTC1 :1; + IO_WORD _WTC0 :1; + IO_WORD _FRAM :1; + IO_WORD _ATD2 :1; + IO_WORD _ATD1 :1; + IO_WORD _ATD0 :1; + IO_WORD _EQ3 :1; + IO_WORD _EQ2 :1; + IO_WORD _EQ1 :1; + IO_WORD _EQ0 :1; + }bit; + struct{ + IO_WORD _WTP :2; + IO_WORD _WEXH :2; + IO_WORD _WTC :4; + IO_WORD :1; + IO_WORD _ATD :3; + IO_WORD _EQ :4; + }bitc; + }FMWTSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _ALEH2 :1; + IO_BYTE _ALEH1 :1; + IO_BYTE _ALEH0 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE _ALEH :3; + }bitc; + }FMWT2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _PS2 :1; + IO_BYTE _PS1 :1; + IO_BYTE _PS0 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _PS :3; + }bitc; + }FMPSSTR; +typedef union{ /* Flash Security Control Register */ + IO_LWORD lword; + struct{ + IO_LWORD _CRC31 :1; + IO_LWORD _CRC30 :1; + IO_LWORD _CRC29 :1; + IO_LWORD _CRC28 :1; + IO_LWORD _CRC27 :1; + IO_LWORD _CRC26 :1; + IO_LWORD _CRC25 :1; + IO_LWORD _CRC24 :1; + IO_LWORD _CRC23 :1; + IO_LWORD _CRC22 :1; + IO_LWORD _CRC21 :1; + IO_LWORD _CRC20 :1; + IO_LWORD _CRC19 :1; + IO_LWORD _CRC18 :1; + IO_LWORD _CRC17 :1; + IO_LWORD _CRC16 :1; + IO_LWORD _CRC15 :1; + IO_LWORD _CRC14 :1; + IO_LWORD _CRC13 :1; + IO_LWORD _CRC12 :1; + IO_LWORD _CRC11 :1; + IO_LWORD _CRC10 :1; + IO_LWORD _CRC9 :1; + IO_LWORD _CRC8 :1; + IO_LWORD _CRC7 :1; + IO_LWORD _CRC6 :1; + IO_LWORD _CRC5 :1; + IO_LWORD _CRC4 :1; + IO_LWORD _CRC3 :1; + IO_LWORD _CRC2 :1; + IO_LWORD _CRC1 :1; + IO_LWORD _CRC0 :1; + }bit; + }FSCR0STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _RDY :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _CSZ3 :1; + IO_LWORD _CSZ2 :1; + IO_LWORD _CSZ1 :1; + IO_LWORD _CSZ0 :1; + IO_LWORD _CSA15 :1; + IO_LWORD _CSA14 :1; + IO_LWORD _CSA13 :1; + IO_LWORD _CSA12 :1; + IO_LWORD _CSA11 :1; + IO_LWORD _CSA10 :1; + IO_LWORD _CSA9 :1; + IO_LWORD _CSA8 :1; + IO_LWORD _CSA7 :1; + IO_LWORD _CSA6 :1; + IO_LWORD _CSA5 :1; + IO_LWORD _CSA4 :1; + IO_LWORD _CSA3 :1; + IO_LWORD _CSA2 :1; + IO_LWORD _CSA1 :1; + IO_LWORD _CSA0 :1; + }bit; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _CSZ :4; + }bitc; + }FSCR1STR; +typedef union{ /* CAN 0 Control Register */ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _Test :1; + IO_WORD _CCE :1; + IO_WORD _DAR :1; + IO_WORD :1; + IO_WORD _EIE :1; + IO_WORD _SIE :1; + IO_WORD _IE :1; + IO_WORD _Init :1; + }bit; + }CTRLR0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _BOff :1; + IO_WORD _EWarn :1; + IO_WORD _EPass :1; + IO_WORD _RxOK :1; + IO_WORD _TxOK :1; + IO_WORD _LEC2 :1; + IO_WORD _LEC1 :1; + IO_WORD _LEC0 :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _LEC :3; + }bitc; + }STATR0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _RP :1; + IO_WORD _REC6 :1; + IO_WORD _REC5 :1; + IO_WORD _REC4 :1; + IO_WORD _REC3 :1; + IO_WORD _REC2 :1; + IO_WORD _REC1 :1; + IO_WORD _REC0 :1; + IO_WORD _TEC7 :1; + IO_WORD _TEC6 :1; + IO_WORD _TEC5 :1; + IO_WORD _TEC4 :1; + IO_WORD _TEC3 :1; + IO_WORD _TEC2 :1; + IO_WORD _TEC1 :1; + IO_WORD _TEC0 :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD _REC :7; + IO_WORD _TEC :8; + }bitc; + }ERRCNT0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD _Tseg22 :1; + IO_WORD _Tseg21 :1; + IO_WORD _Tseg20 :1; + IO_WORD _Tseg13 :1; + IO_WORD _Tseg12 :1; + IO_WORD _Tseg11 :1; + IO_WORD _Tseg10 :1; + IO_WORD _SJW1 :1; + IO_WORD _SJW0 :1; + IO_WORD _BRP5 :1; + IO_WORD _BRP4 :1; + IO_WORD _BRP3 :1; + IO_WORD _BRP2 :1; + IO_WORD _BRP1 :1; + IO_WORD _BRP0 :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD _Tseg2 :3; + IO_WORD _Tseg1 :4; + IO_WORD _SJW :2; + IO_WORD _BRP :6; + }bitc; + }BTR0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _Rx :1; + IO_WORD _Tx1 :1; + IO_WORD _Tx0 :1; + IO_WORD _LBack :1; + IO_WORD _Silent :1; + IO_WORD _Basic :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _Tx :2; + }bitc; + }TESTR0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _BRPE3 :1; + IO_WORD _BRPE2 :1; + IO_WORD _BRPE1 :1; + IO_WORD _BRPE0 :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _BRPE :4; + }bitc; + }BRPER0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }BRPE0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }CBSYNC0STR; +typedef union{ /* CAN 0 IF 1 */ + IO_WORD word; + struct{ + IO_WORD _Busy :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _MN5 :1; + IO_WORD _MN4 :1; + IO_WORD _MN3 :1; + IO_WORD _MN2 :1; + IO_WORD _MN1 :1; + IO_WORD _MN0 :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _MN :6; + }bitc; + }IF1CREQ0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _WR :1; + IO_WORD _Mask :1; + IO_WORD _Arb :1; + IO_WORD _Control :1; + IO_WORD _CIP :1; + IO_WORD _TxReq :1; + IO_WORD _DataA :1; + IO_WORD _DataB :1; + }bit; + }IF1CMSK0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _MXtd :1; + IO_WORD _MDir :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF1MSK20STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _MsgVal :1; + IO_WORD _Xtd :1; + IO_WORD _DIR :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF1ARB20STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _NewDat :1; + IO_WORD _MsgLst :1; + IO_WORD _IntPnd :1; + IO_WORD _UMask :1; + IO_WORD _TxIE :1; + IO_WORD _RxIE :1; + IO_WORD _RmtEn :1; + IO_WORD _TxRqst :1; + IO_WORD _EoB :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _DLC3 :1; + IO_WORD _DLC2 :1; + IO_WORD _DLC1 :1; + IO_WORD _DLC0 :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _DLC :4; + }bitc; + }IF1MCTR0STR; +typedef union{ /* CAN 0 IF 2 */ + IO_WORD word; + struct{ + IO_WORD _Busy :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _MN5 :1; + IO_WORD _MN4 :1; + IO_WORD _MN3 :1; + IO_WORD _MN2 :1; + IO_WORD _MN1 :1; + IO_WORD _MN0 :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _MN :6; + }bitc; + }IF2CREQ0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _WR :1; + IO_WORD _Mask :1; + IO_WORD _Arb :1; + IO_WORD _Control :1; + IO_WORD _CIP :1; + IO_WORD _TxReq :1; + IO_WORD _DataA :1; + IO_WORD _DataB :1; + }bit; + }IF2CMSK0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _MXtd :1; + IO_WORD _MDir :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF2MSK20STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _MsgVal :1; + IO_WORD _Xtd :1; + IO_WORD _DIR :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF2ARB20STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _NewDat :1; + IO_WORD _MsgLst :1; + IO_WORD _IntPnd :1; + IO_WORD _UMask :1; + IO_WORD _TxIE :1; + IO_WORD _RxIE :1; + IO_WORD _RmtEn :1; + IO_WORD _TxRqst :1; + IO_WORD _EoB :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _DLC3 :1; + IO_WORD _DLC2 :1; + IO_WORD _DLC1 :1; + IO_WORD _DLC0 :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _DLC :4; + }bitc; + }IF2MCTR0STR; +typedef union{ /* CAN 1 Control Register */ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _Test :1; + IO_WORD _CCE :1; + IO_WORD _DAR :1; + IO_WORD :1; + IO_WORD _EIE :1; + IO_WORD _SIE :1; + IO_WORD _IE :1; + IO_WORD _Init :1; + }bit; + }CTRLR1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _BOff :1; + IO_WORD _EWarn :1; + IO_WORD _EPass :1; + IO_WORD _RxOK :1; + IO_WORD _TxOK :1; + IO_WORD _LEC2 :1; + IO_WORD _LEC1 :1; + IO_WORD _LEC0 :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _LEC :3; + }bitc; + }STATR1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _RP :1; + IO_WORD _REC6 :1; + IO_WORD _REC5 :1; + IO_WORD _REC4 :1; + IO_WORD _REC3 :1; + IO_WORD _REC2 :1; + IO_WORD _REC1 :1; + IO_WORD _REC0 :1; + IO_WORD _TEC7 :1; + IO_WORD _TEC6 :1; + IO_WORD _TEC5 :1; + IO_WORD _TEC4 :1; + IO_WORD _TEC3 :1; + IO_WORD _TEC2 :1; + IO_WORD _TEC1 :1; + IO_WORD _TEC0 :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD _REC :7; + IO_WORD _TEC :8; + }bitc; + }ERRCNT1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD _Tseg22 :1; + IO_WORD _Tseg21 :1; + IO_WORD _Tseg20 :1; + IO_WORD _Tseg13 :1; + IO_WORD _Tseg12 :1; + IO_WORD _Tseg11 :1; + IO_WORD _Tseg10 :1; + IO_WORD _SJW1 :1; + IO_WORD _SJW0 :1; + IO_WORD _BRP5 :1; + IO_WORD _BRP4 :1; + IO_WORD _BRP3 :1; + IO_WORD _BRP2 :1; + IO_WORD _BRP1 :1; + IO_WORD _BRP0 :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD _Tseg2 :3; + IO_WORD _Tseg1 :4; + IO_WORD _SJW :2; + IO_WORD _BRP :6; + }bitc; + }BTR1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _Rx :1; + IO_WORD _Tx1 :1; + IO_WORD _Tx0 :1; + IO_WORD _LBack :1; + IO_WORD _Silent :1; + IO_WORD _Basic :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _Tx :2; + }bitc; + }TESTR1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _BRPE3 :1; + IO_WORD _BRPE2 :1; + IO_WORD _BRPE1 :1; + IO_WORD _BRPE0 :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _BRPE :4; + }bitc; + }BRPER1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }BRPE1STR; +typedef union{ /* CAN 1 IF 1 */ + IO_WORD word; + struct{ + IO_WORD _Busy :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _MN5 :1; + IO_WORD _MN4 :1; + IO_WORD _MN3 :1; + IO_WORD _MN2 :1; + IO_WORD _MN1 :1; + IO_WORD _MN0 :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _MN :6; + }bitc; + }IF1CREQ1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _WR :1; + IO_WORD _Mask :1; + IO_WORD _Arb :1; + IO_WORD _Control :1; + IO_WORD _CIP :1; + IO_WORD _TxReq :1; + IO_WORD _DataA :1; + IO_WORD _DataB :1; + }bit; + }IF1CMSK1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _MXtd :1; + IO_WORD _MDir :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF1MSK21STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _MsgVal :1; + IO_WORD _Xtd :1; + IO_WORD _DIR :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF1ARB21STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _NewDat :1; + IO_WORD _MsgLst :1; + IO_WORD _IntPnd :1; + IO_WORD _UMask :1; + IO_WORD _TxIE :1; + IO_WORD _RxIE :1; + IO_WORD _RmtEn :1; + IO_WORD _TxRqst :1; + IO_WORD _EoB :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _DLC3 :1; + IO_WORD _DLC2 :1; + IO_WORD _DLC1 :1; + IO_WORD _DLC0 :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _DLC :4; + }bitc; + }IF1MCTR1STR; +typedef union{ /* CAN 1 IF 2 */ + IO_WORD word; + struct{ + IO_WORD _Busy :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _MN5 :1; + IO_WORD _MN4 :1; + IO_WORD _MN3 :1; + IO_WORD _MN2 :1; + IO_WORD _MN1 :1; + IO_WORD _MN0 :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _MN :6; + }bitc; + }IF2CREQ1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _WR :1; + IO_WORD _Mask :1; + IO_WORD _Arb :1; + IO_WORD _Control :1; + IO_WORD _CIP :1; + IO_WORD _TxReq :1; + IO_WORD _DataA :1; + IO_WORD _DataB :1; + }bit; + }IF2CMSK1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _MXtd :1; + IO_WORD _MDir :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF2MSK21STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _MsgVal :1; + IO_WORD _Xtd :1; + IO_WORD _DIR :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF2ARB21STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _NewDat :1; + IO_WORD _MsgLst :1; + IO_WORD _IntPnd :1; + IO_WORD _UMask :1; + IO_WORD _TxIE :1; + IO_WORD _RxIE :1; + IO_WORD _RmtEn :1; + IO_WORD _TxRqst :1; + IO_WORD _EoB :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _DLC3 :1; + IO_WORD _DLC2 :1; + IO_WORD _DLC1 :1; + IO_WORD _DLC0 :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _DLC :4; + }bitc; + }IF2MCTR1STR; +typedef union{ /* CAN 2 Control Register */ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _Test :1; + IO_WORD _CCE :1; + IO_WORD _DAR :1; + IO_WORD :1; + IO_WORD _EIE :1; + IO_WORD _SIE :1; + IO_WORD _IE :1; + IO_WORD _Init :1; + }bit; + }CTRLR2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _BOff :1; + IO_WORD _EWarn :1; + IO_WORD _EPass :1; + IO_WORD _RxOK :1; + IO_WORD _TxOK :1; + IO_WORD _LEC2 :1; + IO_WORD _LEC1 :1; + IO_WORD _LEC0 :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _LEC :3; + }bitc; + }STATR2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _RP :1; + IO_WORD _REC6 :1; + IO_WORD _REC5 :1; + IO_WORD _REC4 :1; + IO_WORD _REC3 :1; + IO_WORD _REC2 :1; + IO_WORD _REC1 :1; + IO_WORD _REC0 :1; + IO_WORD _TEC7 :1; + IO_WORD _TEC6 :1; + IO_WORD _TEC5 :1; + IO_WORD _TEC4 :1; + IO_WORD _TEC3 :1; + IO_WORD _TEC2 :1; + IO_WORD _TEC1 :1; + IO_WORD _TEC0 :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD _REC :7; + IO_WORD _TEC :8; + }bitc; + }ERRCNT2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD _Tseg22 :1; + IO_WORD _Tseg21 :1; + IO_WORD _Tseg20 :1; + IO_WORD _Tseg13 :1; + IO_WORD _Tseg12 :1; + IO_WORD _Tseg11 :1; + IO_WORD _Tseg10 :1; + IO_WORD _SJW1 :1; + IO_WORD _SJW0 :1; + IO_WORD _BRP5 :1; + IO_WORD _BRP4 :1; + IO_WORD _BRP3 :1; + IO_WORD _BRP2 :1; + IO_WORD _BRP1 :1; + IO_WORD _BRP0 :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD _Tseg2 :3; + IO_WORD _Tseg1 :4; + IO_WORD _SJW :2; + IO_WORD _BRP :6; + }bitc; + }BTR2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _Rx :1; + IO_WORD _Tx1 :1; + IO_WORD _Tx0 :1; + IO_WORD _LBack :1; + IO_WORD _Silent :1; + IO_WORD _Basic :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _Tx :2; + }bitc; + }TESTR2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _BRPE3 :1; + IO_WORD _BRPE2 :1; + IO_WORD _BRPE1 :1; + IO_WORD _BRPE0 :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _BRPE :4; + }bitc; + }BRPER2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }BRPE2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }CBSYNC2STR; +typedef union{ /* CAN 2 IF 1 */ + IO_WORD word; + struct{ + IO_WORD _Busy :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _MN5 :1; + IO_WORD _MN4 :1; + IO_WORD _MN3 :1; + IO_WORD _MN2 :1; + IO_WORD _MN1 :1; + IO_WORD _MN0 :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _MN :6; + }bitc; + }IF1CREQ2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _WR :1; + IO_WORD _Mask :1; + IO_WORD _Arb :1; + IO_WORD _Control :1; + IO_WORD _CIP :1; + IO_WORD _TxReq :1; + IO_WORD _DataA :1; + IO_WORD _DataB :1; + }bit; + }IF1CMSK2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _MXtd :1; + IO_WORD _MDir :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF1MSK22STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _MsgVal :1; + IO_WORD _Xtd :1; + IO_WORD _DIR :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF1ARB22STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _NewDat :1; + IO_WORD _MsgLst :1; + IO_WORD _IntPnd :1; + IO_WORD _UMask :1; + IO_WORD _TxIE :1; + IO_WORD _RxIE :1; + IO_WORD _RmtEn :1; + IO_WORD _TxRqst :1; + IO_WORD _EoB :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _DLC3 :1; + IO_WORD _DLC2 :1; + IO_WORD _DLC1 :1; + IO_WORD _DLC0 :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _DLC :4; + }bitc; + }IF1MCTR2STR; +typedef union{ /* CAN 2 IF 2 */ + IO_WORD word; + struct{ + IO_WORD _Busy :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _MN5 :1; + IO_WORD _MN4 :1; + IO_WORD _MN3 :1; + IO_WORD _MN2 :1; + IO_WORD _MN1 :1; + IO_WORD _MN0 :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _MN :6; + }bitc; + }IF2CREQ2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _WR :1; + IO_WORD _Mask :1; + IO_WORD _Arb :1; + IO_WORD _Control :1; + IO_WORD _CIP :1; + IO_WORD _TxReq :1; + IO_WORD _DataA :1; + IO_WORD _DataB :1; + }bit; + }IF2CMSK2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _MXtd :1; + IO_WORD _MDir :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF2MSK22STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _MsgVal :1; + IO_WORD _Xtd :1; + IO_WORD _DIR :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF2ARB22STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _NewDat :1; + IO_WORD _MsgLst :1; + IO_WORD _IntPnd :1; + IO_WORD _UMask :1; + IO_WORD _TxIE :1; + IO_WORD _RxIE :1; + IO_WORD _RmtEn :1; + IO_WORD _TxRqst :1; + IO_WORD _EoB :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _DLC3 :1; + IO_WORD _DLC2 :1; + IO_WORD _DLC1 :1; + IO_WORD _DLC0 :1; + }bit; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _DLC :4; + }bitc; + }IF2MCTR2STR; +typedef union{ /* EDSU/MPU Registers */ + IO_LWORD lword; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _SR :1; + IO_LWORD _SW :1; + IO_LWORD _SX :1; + IO_LWORD _UR :1; + IO_LWORD _UW :1; + IO_LWORD _UX :1; + IO_LWORD _FCPU :1; + IO_LWORD _FDMA :1; + IO_LWORD _EEMM :1; + IO_LWORD _PFD :1; + IO_LWORD _SINT1 :1; + IO_LWORD _SINT0 :1; + IO_LWORD _EINT1 :1; + IO_LWORD _EINT0 :1; + IO_LWORD _EINTT :1; + IO_LWORD _EINTR :1; + }bit; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _SINT :2; + IO_LWORD _EINT :2; + }bitc; + }BCTRLSTR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _IDX4 :1; + IO_LWORD _IDX3 :1; + IO_LWORD _IDX2 :1; + IO_LWORD _IDX1 :1; + IO_LWORD _IDX0 :1; + IO_LWORD _CDMA :1; + IO_LWORD _CSZ1 :1; + IO_LWORD _CSZ0 :1; + IO_LWORD _CRW1 :1; + IO_LWORD _CRW0 :1; + IO_LWORD _PV :1; + IO_LWORD _RST :1; + IO_LWORD _INT1 :1; + IO_LWORD _INT0 :1; + IO_LWORD _INTT :1; + IO_LWORD _INTR :1; + }bit; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _IDX :5; + IO_LWORD :1; + IO_LWORD _CSZ :2; + IO_LWORD _CRW :2; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _INT :2; + }bitc; + }BSTATSTR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _BD31 :1; + IO_LWORD _BD30 :1; + IO_LWORD _BD29 :1; + IO_LWORD _BD28 :1; + IO_LWORD _BD27 :1; + IO_LWORD _BD26 :1; + IO_LWORD _BD25 :1; + IO_LWORD _BD24 :1; + IO_LWORD _BD23 :1; + IO_LWORD _BD22 :1; + IO_LWORD _BD21 :1; + IO_LWORD _BD20 :1; + IO_LWORD _BD19 :1; + IO_LWORD _BD18 :1; + IO_LWORD _BD17 :1; + IO_LWORD _BD16 :1; + IO_LWORD _BD15 :1; + IO_LWORD _BD14 :1; + IO_LWORD _BD13 :1; + IO_LWORD _BD12 :1; + IO_LWORD _BD11 :1; + IO_LWORD _BD10 :1; + IO_LWORD _BD9 :1; + IO_LWORD _BD8 :1; + IO_LWORD _BD7 :1; + IO_LWORD _BD6 :1; + IO_LWORD _BD5 :1; + IO_LWORD _BD4 :1; + IO_LWORD _BD3 :1; + IO_LWORD _BD2 :1; + IO_LWORD _BD1 :1; + IO_LWORD _BD0 :1; + }bit; + }BIRQSTR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _SRX1 :1; + IO_LWORD _SW1 :1; + IO_LWORD _SRX0 :1; + IO_LWORD _SW0 :1; + IO_LWORD _URX1 :1; + IO_LWORD _UW1 :1; + IO_LWORD _URX0 :1; + IO_LWORD _UW0 :1; + IO_LWORD _MPE :1; + IO_LWORD _COMB :1; + IO_LWORD _CTC1 :1; + IO_LWORD _CTC0 :1; + IO_LWORD _OBS1 :1; + IO_LWORD _OBS0 :1; + IO_LWORD _OBT1 :1; + IO_LWORD _OBT0 :1; + IO_LWORD _EP3 :1; + IO_LWORD _EP2 :1; + IO_LWORD _EP1 :1; + IO_LWORD _EP0 :1; + IO_LWORD _EM1 :1; + IO_LWORD _EM0 :1; + IO_LWORD _ER1 :1; + IO_LWORD _ER0 :1; + }bit; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _CTC :2; + IO_LWORD _OBS :2; + IO_LWORD _OBT :2; + IO_LWORD _EP :4; + IO_LWORD _EM :2; + IO_LWORD _ER :2; + }bitc; + }BCR0STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _SRX1 :1; + IO_LWORD _SW1 :1; + IO_LWORD _SRX0 :1; + IO_LWORD _SW0 :1; + IO_LWORD _URX1 :1; + IO_LWORD _UW1 :1; + IO_LWORD _URX0 :1; + IO_LWORD _UW0 :1; + IO_LWORD _MPE :1; + IO_LWORD _COMB :1; + IO_LWORD _CTC1 :1; + IO_LWORD _CTC0 :1; + IO_LWORD _OBS1 :1; + IO_LWORD _OBS0 :1; + IO_LWORD _OBT1 :1; + IO_LWORD _OBT0 :1; + IO_LWORD _EP3 :1; + IO_LWORD _EP2 :1; + IO_LWORD _EP1 :1; + IO_LWORD _EP0 :1; + IO_LWORD _EM1 :1; + IO_LWORD _EM0 :1; + IO_LWORD _ER1 :1; + IO_LWORD _ER0 :1; + }bit; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _CTC :2; + IO_LWORD _OBS :2; + IO_LWORD _OBT :2; + IO_LWORD _EP :4; + IO_LWORD _EM :2; + IO_LWORD _ER :2; + }bitc; + }BCR1STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _SRX1 :1; + IO_LWORD _SW1 :1; + IO_LWORD _SRX0 :1; + IO_LWORD _SW0 :1; + IO_LWORD _URX1 :1; + IO_LWORD _UW1 :1; + IO_LWORD _URX0 :1; + IO_LWORD _UW0 :1; + IO_LWORD _MPE :1; + IO_LWORD _COMB :1; + IO_LWORD _CTC1 :1; + IO_LWORD _CTC0 :1; + IO_LWORD _OBS1 :1; + IO_LWORD _OBS0 :1; + IO_LWORD _OBT1 :1; + IO_LWORD _OBT0 :1; + IO_LWORD _EP3 :1; + IO_LWORD _EP2 :1; + IO_LWORD _EP1 :1; + IO_LWORD _EP0 :1; + IO_LWORD _EM1 :1; + IO_LWORD _EM0 :1; + IO_LWORD _ER1 :1; + IO_LWORD _ER0 :1; + }bit; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _CTC :2; + IO_LWORD _OBS :2; + IO_LWORD _OBT :2; + IO_LWORD _EP :4; + IO_LWORD _EM :2; + IO_LWORD _ER :2; + }bitc; + }BCR2STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _SRX1 :1; + IO_LWORD _SW1 :1; + IO_LWORD _SRX0 :1; + IO_LWORD _SW0 :1; + IO_LWORD _URX1 :1; + IO_LWORD _UW1 :1; + IO_LWORD _URX0 :1; + IO_LWORD _UW0 :1; + IO_LWORD _MPE :1; + IO_LWORD _COMB :1; + IO_LWORD _CTC1 :1; + IO_LWORD _CTC0 :1; + IO_LWORD _OBS1 :1; + IO_LWORD _OBS0 :1; + IO_LWORD _OBT1 :1; + IO_LWORD _OBT0 :1; + IO_LWORD _EP3 :1; + IO_LWORD _EP2 :1; + IO_LWORD _EP1 :1; + IO_LWORD _EP0 :1; + IO_LWORD _EM1 :1; + IO_LWORD _EM0 :1; + IO_LWORD _ER1 :1; + IO_LWORD _ER0 :1; + }bit; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _CTC :2; + IO_LWORD _OBS :2; + IO_LWORD _OBT :2; + IO_LWORD _EP :4; + IO_LWORD _EM :2; + IO_LWORD _ER :2; + }bitc; + }BCR3STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _SRX1 :1; + IO_LWORD _SW1 :1; + IO_LWORD _SRX0 :1; + IO_LWORD _SW0 :1; + IO_LWORD _URX1 :1; + IO_LWORD _UW1 :1; + IO_LWORD _URX0 :1; + IO_LWORD _UW0 :1; + IO_LWORD _MPE :1; + IO_LWORD _COMB :1; + IO_LWORD _CTC1 :1; + IO_LWORD _CTC0 :1; + IO_LWORD _OBS1 :1; + IO_LWORD _OBS0 :1; + IO_LWORD _OBT1 :1; + IO_LWORD _OBT0 :1; + IO_LWORD _EP3 :1; + IO_LWORD _EP2 :1; + IO_LWORD _EP1 :1; + IO_LWORD _EP0 :1; + IO_LWORD _EM1 :1; + IO_LWORD _EM0 :1; + IO_LWORD _ER1 :1; + IO_LWORD _ER0 :1; + }bit; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _CTC :2; + IO_LWORD _OBS :2; + IO_LWORD _OBT :2; + IO_LWORD _EP :4; + IO_LWORD _EM :2; + IO_LWORD _ER :2; + }bitc; + }BCR4STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _SRX1 :1; + IO_LWORD _SW1 :1; + IO_LWORD _SRX0 :1; + IO_LWORD _SW0 :1; + IO_LWORD _URX1 :1; + IO_LWORD _UW1 :1; + IO_LWORD _URX0 :1; + IO_LWORD _UW0 :1; + IO_LWORD _MPE :1; + IO_LWORD _COMB :1; + IO_LWORD _CTC1 :1; + IO_LWORD _CTC0 :1; + IO_LWORD _OBS1 :1; + IO_LWORD _OBS0 :1; + IO_LWORD _OBT1 :1; + IO_LWORD _OBT0 :1; + IO_LWORD _EP3 :1; + IO_LWORD _EP2 :1; + IO_LWORD _EP1 :1; + IO_LWORD _EP0 :1; + IO_LWORD _EM1 :1; + IO_LWORD _EM0 :1; + IO_LWORD _ER1 :1; + IO_LWORD _ER0 :1; + }bit; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _CTC :2; + IO_LWORD _OBS :2; + IO_LWORD _OBT :2; + IO_LWORD _EP :4; + IO_LWORD _EM :2; + IO_LWORD _ER :2; + }bitc; + }BCR5STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _SRX1 :1; + IO_LWORD _SW1 :1; + IO_LWORD _SRX0 :1; + IO_LWORD _SW0 :1; + IO_LWORD _URX1 :1; + IO_LWORD _UW1 :1; + IO_LWORD _URX0 :1; + IO_LWORD _UW0 :1; + IO_LWORD _MPE :1; + IO_LWORD _COMB :1; + IO_LWORD _CTC1 :1; + IO_LWORD _CTC0 :1; + IO_LWORD _OBS1 :1; + IO_LWORD _OBS0 :1; + IO_LWORD _OBT1 :1; + IO_LWORD _OBT0 :1; + IO_LWORD _EP3 :1; + IO_LWORD _EP2 :1; + IO_LWORD _EP1 :1; + IO_LWORD _EP0 :1; + IO_LWORD _EM1 :1; + IO_LWORD _EM0 :1; + IO_LWORD _ER1 :1; + IO_LWORD _ER0 :1; + }bit; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _CTC :2; + IO_LWORD _OBS :2; + IO_LWORD _OBT :2; + IO_LWORD _EP :4; + IO_LWORD _EM :2; + IO_LWORD _ER :2; + }bitc; + }BCR6STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _SRX1 :1; + IO_LWORD _SW1 :1; + IO_LWORD _SRX0 :1; + IO_LWORD _SW0 :1; + IO_LWORD _URX1 :1; + IO_LWORD _UW1 :1; + IO_LWORD _URX0 :1; + IO_LWORD _UW0 :1; + IO_LWORD _MPE :1; + IO_LWORD _COMB :1; + IO_LWORD _CTC1 :1; + IO_LWORD _CTC0 :1; + IO_LWORD _OBS1 :1; + IO_LWORD _OBS0 :1; + IO_LWORD _OBT1 :1; + IO_LWORD _OBT0 :1; + IO_LWORD _EP3 :1; + IO_LWORD _EP2 :1; + IO_LWORD _EP1 :1; + IO_LWORD _EP0 :1; + IO_LWORD _EM1 :1; + IO_LWORD _EM0 :1; + IO_LWORD _ER1 :1; + IO_LWORD _ER0 :1; + }bit; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD _CTC :2; + IO_LWORD _OBS :2; + IO_LWORD _OBT :2; + IO_LWORD _EP :4; + IO_LWORD _EM :2; + IO_LWORD _ER :2; + }bitc; + }BCR7STR; + +/* C-DECLARATIONS */ + +__IO_EXTERN __io PDR00STR pdr00; /* Port Data Register */ +#define PDR00 pdr00.byte +#define PDR00_D7 pdr00.bit._D7 +#define PDR00_D6 pdr00.bit._D6 +#define PDR00_D5 pdr00.bit._D5 +#define PDR00_D4 pdr00.bit._D4 +#define PDR00_D3 pdr00.bit._D3 +#define PDR00_D2 pdr00.bit._D2 +#define PDR00_D1 pdr00.bit._D1 +#define PDR00_D0 pdr00.bit._D0 +__IO_EXTERN __io PDR01STR pdr01; +#define PDR01 pdr01.byte +#define PDR01_D7 pdr01.bit._D7 +#define PDR01_D6 pdr01.bit._D6 +#define PDR01_D5 pdr01.bit._D5 +#define PDR01_D4 pdr01.bit._D4 +#define PDR01_D3 pdr01.bit._D3 +#define PDR01_D2 pdr01.bit._D2 +#define PDR01_D1 pdr01.bit._D1 +#define PDR01_D0 pdr01.bit._D0 +__IO_EXTERN __io PDR02STR pdr02; +#define PDR02 pdr02.byte +#define PDR02_D7 pdr02.bit._D7 +#define PDR02_D6 pdr02.bit._D6 +#define PDR02_D5 pdr02.bit._D5 +#define PDR02_D4 pdr02.bit._D4 +#define PDR02_D3 pdr02.bit._D3 +#define PDR02_D2 pdr02.bit._D2 +#define PDR02_D1 pdr02.bit._D1 +#define PDR02_D0 pdr02.bit._D0 +__IO_EXTERN __io PDR03STR pdr03; +#define PDR03 pdr03.byte +#define PDR03_D7 pdr03.bit._D7 +#define PDR03_D6 pdr03.bit._D6 +#define PDR03_D5 pdr03.bit._D5 +#define PDR03_D4 pdr03.bit._D4 +#define PDR03_D3 pdr03.bit._D3 +#define PDR03_D2 pdr03.bit._D2 +#define PDR03_D1 pdr03.bit._D1 +#define PDR03_D0 pdr03.bit._D0 +__IO_EXTERN __io PDR04STR pdr04; +#define PDR04 pdr04.byte +#define PDR04_D1 pdr04.bit._D1 +#define PDR04_D0 pdr04.bit._D0 +__IO_EXTERN __io PDR05STR pdr05; +#define PDR05 pdr05.byte +#define PDR05_D7 pdr05.bit._D7 +#define PDR05_D6 pdr05.bit._D6 +#define PDR05_D5 pdr05.bit._D5 +#define PDR05_D4 pdr05.bit._D4 +#define PDR05_D3 pdr05.bit._D3 +#define PDR05_D2 pdr05.bit._D2 +#define PDR05_D1 pdr05.bit._D1 +#define PDR05_D0 pdr05.bit._D0 +__IO_EXTERN __io PDR06STR pdr06; +#define PDR06 pdr06.byte +#define PDR06_D7 pdr06.bit._D7 +#define PDR06_D6 pdr06.bit._D6 +#define PDR06_D5 pdr06.bit._D5 +#define PDR06_D4 pdr06.bit._D4 +#define PDR06_D3 pdr06.bit._D3 +#define PDR06_D2 pdr06.bit._D2 +#define PDR06_D1 pdr06.bit._D1 +#define PDR06_D0 pdr06.bit._D0 +__IO_EXTERN __io PDR07STR pdr07; +#define PDR07 pdr07.byte +#define PDR07_D7 pdr07.bit._D7 +#define PDR07_D6 pdr07.bit._D6 +#define PDR07_D5 pdr07.bit._D5 +#define PDR07_D4 pdr07.bit._D4 +#define PDR07_D3 pdr07.bit._D3 +#define PDR07_D2 pdr07.bit._D2 +#define PDR07_D1 pdr07.bit._D1 +#define PDR07_D0 pdr07.bit._D0 +__IO_EXTERN __io PDR08STR pdr08; +#define PDR08 pdr08.byte +#define PDR08_D7 pdr08.bit._D7 +#define PDR08_D6 pdr08.bit._D6 +#define PDR08_D5 pdr08.bit._D5 +#define PDR08_D4 pdr08.bit._D4 +#define PDR08_D3 pdr08.bit._D3 +#define PDR08_D2 pdr08.bit._D2 +#define PDR08_D1 pdr08.bit._D1 +#define PDR08_D0 pdr08.bit._D0 +__IO_EXTERN __io PDR09STR pdr09; +#define PDR09 pdr09.byte +#define PDR09_D7 pdr09.bit._D7 +#define PDR09_D6 pdr09.bit._D6 +#define PDR09_D3 pdr09.bit._D3 +#define PDR09_D2 pdr09.bit._D2 +#define PDR09_D1 pdr09.bit._D1 +#define PDR09_D0 pdr09.bit._D0 +__IO_EXTERN __io PDR10STR pdr10; +#define PDR10 pdr10.byte +#define PDR10_D6 pdr10.bit._D6 +#define PDR10_D5 pdr10.bit._D5 +#define PDR10_D4 pdr10.bit._D4 +#define PDR10_D3 pdr10.bit._D3 +#define PDR10_D2 pdr10.bit._D2 +#define PDR10_D1 pdr10.bit._D1 +__IO_EXTERN __io PDR13STR pdr13; +#define PDR13 pdr13.byte +#define PDR13_D2 pdr13.bit._D2 +#define PDR13_D1 pdr13.bit._D1 +#define PDR13_D0 pdr13.bit._D0 +__IO_EXTERN __io PDR14STR pdr14; +#define PDR14 pdr14.byte +#define PDR14_D7 pdr14.bit._D7 +#define PDR14_D6 pdr14.bit._D6 +#define PDR14_D5 pdr14.bit._D5 +#define PDR14_D4 pdr14.bit._D4 +#define PDR14_D3 pdr14.bit._D3 +#define PDR14_D2 pdr14.bit._D2 +#define PDR14_D1 pdr14.bit._D1 +#define PDR14_D0 pdr14.bit._D0 +__IO_EXTERN __io PDR15STR pdr15; +#define PDR15 pdr15.byte +#define PDR15_D3 pdr15.bit._D3 +#define PDR15_D2 pdr15.bit._D2 +#define PDR15_D1 pdr15.bit._D1 +#define PDR15_D0 pdr15.bit._D0 +__IO_EXTERN __io PDR16STR pdr16; +#define PDR16 pdr16.byte +#define PDR16_D7 pdr16.bit._D7 +#define PDR16_D6 pdr16.bit._D6 +#define PDR16_D5 pdr16.bit._D5 +#define PDR16_D4 pdr16.bit._D4 +#define PDR16_D3 pdr16.bit._D3 +#define PDR16_D2 pdr16.bit._D2 +#define PDR16_D1 pdr16.bit._D1 +#define PDR16_D0 pdr16.bit._D0 +__IO_EXTERN __io PDR17STR pdr17; +#define PDR17 pdr17.byte +#define PDR17_D7 pdr17.bit._D7 +#define PDR17_D6 pdr17.bit._D6 +#define PDR17_D5 pdr17.bit._D5 +#define PDR17_D4 pdr17.bit._D4 +__IO_EXTERN __io PDR18STR pdr18; +#define PDR18 pdr18.byte +#define PDR18_D6 pdr18.bit._D6 +#define PDR18_D5 pdr18.bit._D5 +#define PDR18_D4 pdr18.bit._D4 +#define PDR18_D2 pdr18.bit._D2 +#define PDR18_D1 pdr18.bit._D1 +#define PDR18_D0 pdr18.bit._D0 +__IO_EXTERN __io PDR19STR pdr19; +#define PDR19 pdr19.byte +#define PDR19_D6 pdr19.bit._D6 +#define PDR19_D5 pdr19.bit._D5 +#define PDR19_D4 pdr19.bit._D4 +#define PDR19_D2 pdr19.bit._D2 +#define PDR19_D1 pdr19.bit._D1 +#define PDR19_D0 pdr19.bit._D0 +__IO_EXTERN __io PDR20STR pdr20; +#define PDR20 pdr20.byte +#define PDR20_D2 pdr20.bit._D2 +#define PDR20_D1 pdr20.bit._D1 +#define PDR20_D0 pdr20.bit._D0 +__IO_EXTERN __io PDR22STR pdr22; +#define PDR22 pdr22.byte +#define PDR22_D5 pdr22.bit._D5 +#define PDR22_D4 pdr22.bit._D4 +#define PDR22_D2 pdr22.bit._D2 +#define PDR22_D0 pdr22.bit._D0 +__IO_EXTERN __io PDR23STR pdr23; +#define PDR23 pdr23.byte +#define PDR23_D5 pdr23.bit._D5 +#define PDR23_D4 pdr23.bit._D4 +#define PDR23_D3 pdr23.bit._D3 +#define PDR23_D2 pdr23.bit._D2 +#define PDR23_D1 pdr23.bit._D1 +#define PDR23_D0 pdr23.bit._D0 +__IO_EXTERN __io PDR24STR pdr24; +#define PDR24 pdr24.byte +#define PDR24_D7 pdr24.bit._D7 +#define PDR24_D6 pdr24.bit._D6 +#define PDR24_D5 pdr24.bit._D5 +#define PDR24_D4 pdr24.bit._D4 +#define PDR24_D3 pdr24.bit._D3 +#define PDR24_D2 pdr24.bit._D2 +#define PDR24_D1 pdr24.bit._D1 +#define PDR24_D0 pdr24.bit._D0 +__IO_EXTERN __io PDR25STR pdr25; +#define PDR25 pdr25.byte +#define PDR25_D7 pdr25.bit._D7 +#define PDR25_D6 pdr25.bit._D6 +#define PDR25_D5 pdr25.bit._D5 +#define PDR25_D4 pdr25.bit._D4 +#define PDR25_D3 pdr25.bit._D3 +#define PDR25_D2 pdr25.bit._D2 +#define PDR25_D1 pdr25.bit._D1 +#define PDR25_D0 pdr25.bit._D0 +__IO_EXTERN __io PDR26STR pdr26; +#define PDR26 pdr26.byte +#define PDR26_D7 pdr26.bit._D7 +#define PDR26_D6 pdr26.bit._D6 +#define PDR26_D5 pdr26.bit._D5 +#define PDR26_D4 pdr26.bit._D4 +#define PDR26_D3 pdr26.bit._D3 +#define PDR26_D2 pdr26.bit._D2 +#define PDR26_D1 pdr26.bit._D1 +#define PDR26_D0 pdr26.bit._D0 +__IO_EXTERN __io PDR27STR pdr27; +#define PDR27 pdr27.byte +#define PDR27_D7 pdr27.bit._D7 +#define PDR27_D6 pdr27.bit._D6 +#define PDR27_D5 pdr27.bit._D5 +#define PDR27_D4 pdr27.bit._D4 +#define PDR27_D3 pdr27.bit._D3 +#define PDR27_D2 pdr27.bit._D2 +#define PDR27_D1 pdr27.bit._D1 +#define PDR27_D0 pdr27.bit._D0 +__IO_EXTERN __io PDR29STR pdr29; +#define PDR29 pdr29.byte +#define PDR29_D7 pdr29.bit._D7 +#define PDR29_D6 pdr29.bit._D6 +#define PDR29_D5 pdr29.bit._D5 +#define PDR29_D4 pdr29.bit._D4 +#define PDR29_D3 pdr29.bit._D3 +#define PDR29_D2 pdr29.bit._D2 +#define PDR29_D1 pdr29.bit._D1 +#define PDR29_D0 pdr29.bit._D0 +__IO_EXTERN __io EIRR0STR eirr0; /* External Interrupt 0-7 */ +#define EIRR0 eirr0.byte +#define EIRR0_ER7 eirr0.bit._ER7 +#define EIRR0_ER6 eirr0.bit._ER6 +#define EIRR0_ER5 eirr0.bit._ER5 +#define EIRR0_ER4 eirr0.bit._ER4 +#define EIRR0_ER3 eirr0.bit._ER3 +#define EIRR0_ER2 eirr0.bit._ER2 +#define EIRR0_ER1 eirr0.bit._ER1 +#define EIRR0_ER0 eirr0.bit._ER0 +__IO_EXTERN __io ENIR0STR enir0; +#define ENIR0 enir0.byte +#define ENIR0_EN7 enir0.bit._EN7 +#define ENIR0_EN6 enir0.bit._EN6 +#define ENIR0_EN5 enir0.bit._EN5 +#define ENIR0_EN4 enir0.bit._EN4 +#define ENIR0_EN3 enir0.bit._EN3 +#define ENIR0_EN2 enir0.bit._EN2 +#define ENIR0_EN1 enir0.bit._EN1 +#define ENIR0_EN0 enir0.bit._EN0 +__IO_EXTERN __io ELVR0STR elvr0; +#define ELVR0 elvr0.word +#define ELVR0_LB7 elvr0.bit._LB7 +#define ELVR0_LA7 elvr0.bit._LA7 +#define ELVR0_LB6 elvr0.bit._LB6 +#define ELVR0_LA6 elvr0.bit._LA6 +#define ELVR0_LB5 elvr0.bit._LB5 +#define ELVR0_LA5 elvr0.bit._LA5 +#define ELVR0_LB4 elvr0.bit._LB4 +#define ELVR0_LA4 elvr0.bit._LA4 +#define ELVR0_LB3 elvr0.bit._LB3 +#define ELVR0_LA3 elvr0.bit._LA3 +#define ELVR0_LB2 elvr0.bit._LB2 +#define ELVR0_LA2 elvr0.bit._LA2 +#define ELVR0_LB1 elvr0.bit._LB1 +#define ELVR0_LA1 elvr0.bit._LA1 +#define ELVR0_LB0 elvr0.bit._LB0 +#define ELVR0_LA0 elvr0.bit._LA0 +__IO_EXTERN __io EIRR1STR eirr1; /* External Interrupt 8-15 */ +#define EIRR1 eirr1.byte +#define EIRR1_ER15 eirr1.bit._ER15 +#define EIRR1_ER14 eirr1.bit._ER14 +#define EIRR1_ER13 eirr1.bit._ER13 +#define EIRR1_ER12 eirr1.bit._ER12 +#define EIRR1_ER11 eirr1.bit._ER11 +#define EIRR1_ER10 eirr1.bit._ER10 +#define EIRR1_ER9 eirr1.bit._ER9 +#define EIRR1_ER8 eirr1.bit._ER8 +__IO_EXTERN __io ENIR1STR enir1; +#define ENIR1 enir1.byte +#define ENIR1_EN15 enir1.bit._EN15 +#define ENIR1_EN14 enir1.bit._EN14 +#define ENIR1_EN13 enir1.bit._EN13 +#define ENIR1_EN12 enir1.bit._EN12 +#define ENIR1_EN11 enir1.bit._EN11 +#define ENIR1_EN10 enir1.bit._EN10 +#define ENIR1_EN9 enir1.bit._EN9 +#define ENIR1_EN8 enir1.bit._EN8 +__IO_EXTERN __io ELVR1STR elvr1; +#define ELVR1 elvr1.word +#define ELVR1_LB15 elvr1.bit._LB15 +#define ELVR1_LA15 elvr1.bit._LA15 +#define ELVR1_LB14 elvr1.bit._LB14 +#define ELVR1_LA14 elvr1.bit._LA14 +#define ELVR1_LB13 elvr1.bit._LB13 +#define ELVR1_LA13 elvr1.bit._LA13 +#define ELVR1_LB12 elvr1.bit._LB12 +#define ELVR1_LA12 elvr1.bit._LA12 +#define ELVR1_LB11 elvr1.bit._LB11 +#define ELVR1_LA11 elvr1.bit._LA11 +#define ELVR1_LB10 elvr1.bit._LB10 +#define ELVR1_LA10 elvr1.bit._LA10 +#define ELVR1_LB9 elvr1.bit._LB9 +#define ELVR1_LA9 elvr1.bit._LA9 +#define ELVR1_LB8 elvr1.bit._LB8 +#define ELVR1_LA8 elvr1.bit._LA8 +__IO_EXTERN __io DICRSTR dicr; /* DLYI/I-unit */ +#define DICR dicr.byte +#define DICR_DLYI dicr.bit._DLYI +__IO_EXTERN __io HRCLSTR hrcl; +#define HRCL hrcl.byte +#define HRCL_MHALTI hrcl.bit._MHALTI +#define HRCL_LVL4 hrcl.bit._LVL4 +#define HRCL_LVL3 hrcl.bit._LVL3 +#define HRCL_LVL2 hrcl.bit._LVL2 +#define HRCL_LVL1 hrcl.bit._LVL1 +#define HRCL_LVL0 hrcl.bit._LVL0 +#define HRCL_LVL hrcl.bitc._LVL +__IO_EXTERN __io IO_WORD rbsync; /* R-Bus Sync */ +#define RBSYNC rbsync +__IO_EXTERN __io SCR02STR scr02; /* USART (LIN) 2 */ +#define SCR02 scr02.byte +#define SCR02_PEN scr02.bit._PEN +#define SCR02_P scr02.bit._P +#define SCR02_SBL scr02.bit._SBL +#define SCR02_CL scr02.bit._CL +#define SCR02_AD scr02.bit._AD +#define SCR02_CRE scr02.bit._CRE +#define SCR02_RXE scr02.bit._RXE +#define SCR02_TXE scr02.bit._TXE +__IO_EXTERN __io SMR02STR smr02; +#define SMR02 smr02.byte +#define SMR02_MD1 smr02.bit._MD1 +#define SMR02_MD0 smr02.bit._MD0 +#define SMR02_OTO smr02.bit._OTO +#define SMR02_EXT smr02.bit._EXT +#define SMR02_REST smr02.bit._REST +#define SMR02_UPCL smr02.bit._UPCL +#define SMR02_SCKE smr02.bit._SCKE +#define SMR02_SOE smr02.bit._SOE +#define SMR02_MD smr02.bitc._MD +__IO_EXTERN __io SSR02STR ssr02; +#define SSR02 ssr02.byte +#define SSR02_PE ssr02.bit._PE +#define SSR02_ORE ssr02.bit._ORE +#define SSR02_FRE ssr02.bit._FRE +#define SSR02_RDRF ssr02.bit._RDRF +#define SSR02_TDRE ssr02.bit._TDRE +#define SSR02_BDS ssr02.bit._BDS +#define SSR02_RIE ssr02.bit._RIE +#define SSR02_TIE ssr02.bit._TIE +__IO_EXTERN __io IO_BYTE rdr02; +#define RDR02 rdr02 +__IO_EXTERN __io IO_BYTE tdr02; +#define TDR02 tdr02 +__IO_EXTERN __io ESCR02STR escr02; +#define ESCR02 escr02.byte +#define ESCR02_LBIE escr02.bit._LBIE +#define ESCR02_LBD escr02.bit._LBD +#define ESCR02_LBL1 escr02.bit._LBL1 +#define ESCR02_LBL0 escr02.bit._LBL0 +#define ESCR02_SOPE escr02.bit._SOPE +#define ESCR02_SIOP escr02.bit._SIOP +#define ESCR02_CCO escr02.bit._CCO +#define ESCR02_SCES escr02.bit._SCES +#define ESCR02_LBL escr02.bitc._LBL +__IO_EXTERN __io ECCR02STR eccr02; +#define ECCR02 eccr02.byte +#define ECCR02_INV eccr02.bit._INV +#define ECCR02_LBR eccr02.bit._LBR +#define ECCR02_MS eccr02.bit._MS +#define ECCR02_SCDE eccr02.bit._SCDE +#define ECCR02_SSM eccr02.bit._SSM +#define ECCR02_BIE eccr02.bit._BIE +#define ECCR02_RBI eccr02.bit._RBI +#define ECCR02_TBI eccr02.bit._TBI +__IO_EXTERN __io SCR04STR scr04; /* USART (LIN) 4 with FIFO */ +#define SCR04 scr04.byte +#define SCR04_PEN scr04.bit._PEN +#define SCR04_P scr04.bit._P +#define SCR04_SBL scr04.bit._SBL +#define SCR04_CL scr04.bit._CL +#define SCR04_AD scr04.bit._AD +#define SCR04_CRE scr04.bit._CRE +#define SCR04_RXE scr04.bit._RXE +#define SCR04_TXE scr04.bit._TXE +__IO_EXTERN __io SMR04STR smr04; +#define SMR04 smr04.byte +#define SMR04_MD1 smr04.bit._MD1 +#define SMR04_MD0 smr04.bit._MD0 +#define SMR04_OTO smr04.bit._OTO +#define SMR04_EXT smr04.bit._EXT +#define SMR04_REST smr04.bit._REST +#define SMR04_UPCL smr04.bit._UPCL +#define SMR04_SCKE smr04.bit._SCKE +#define SMR04_SOE smr04.bit._SOE +#define SMR04_MD smr04.bitc._MD +__IO_EXTERN __io SSR04STR ssr04; +#define SSR04 ssr04.byte +#define SSR04_PE ssr04.bit._PE +#define SSR04_ORE ssr04.bit._ORE +#define SSR04_FRE ssr04.bit._FRE +#define SSR04_RDRF ssr04.bit._RDRF +#define SSR04_TDRE ssr04.bit._TDRE +#define SSR04_BDS ssr04.bit._BDS +#define SSR04_RIE ssr04.bit._RIE +#define SSR04_TIE ssr04.bit._TIE +__IO_EXTERN __io IO_BYTE rdr04; +#define RDR04 rdr04 +__IO_EXTERN __io IO_BYTE tdr04; +#define TDR04 tdr04 +__IO_EXTERN __io ESCR04STR escr04; +#define ESCR04 escr04.byte +#define ESCR04_LBIE escr04.bit._LBIE +#define ESCR04_LBD escr04.bit._LBD +#define ESCR04_LBL1 escr04.bit._LBL1 +#define ESCR04_LBL0 escr04.bit._LBL0 +#define ESCR04_SOPE escr04.bit._SOPE +#define ESCR04_SIOP escr04.bit._SIOP +#define ESCR04_CCO escr04.bit._CCO +#define ESCR04_SCES escr04.bit._SCES +#define ESCR04_LBL escr04.bitc._LBL +__IO_EXTERN __io ECCR04STR eccr04; +#define ECCR04 eccr04.byte +#define ECCR04_INV eccr04.bit._INV +#define ECCR04_LBR eccr04.bit._LBR +#define ECCR04_MS eccr04.bit._MS +#define ECCR04_SCDE eccr04.bit._SCDE +#define ECCR04_SSM eccr04.bit._SSM +#define ECCR04_BIE eccr04.bit._BIE +#define ECCR04_RBI eccr04.bit._RBI +#define ECCR04_TBI eccr04.bit._TBI +__IO_EXTERN __io IO_BYTE fsr04; +#define FSR04 fsr04 +__IO_EXTERN __io FCR04STR fcr04; +#define FCR04 fcr04.byte +#define FCR04_RXL3 fcr04.bit._RXL3 +#define FCR04_RXL2 fcr04.bit._RXL2 +#define FCR04_RXL1 fcr04.bit._RXL1 +#define FCR04_RXL0 fcr04.bit._RXL0 +#define FCR04_ERX fcr04.bit._ERX +#define FCR04_ETX fcr04.bit._ETX +#define FCR04_SVD fcr04.bit._SVD +#define FCR04_RXL fcr04.bitc._RXL +__IO_EXTERN __io SCR05STR scr05; /* USART (LIN) 5 with FIFO */ +#define SCR05 scr05.byte +#define SCR05_PEN scr05.bit._PEN +#define SCR05_P scr05.bit._P +#define SCR05_SBL scr05.bit._SBL +#define SCR05_CL scr05.bit._CL +#define SCR05_AD scr05.bit._AD +#define SCR05_CRE scr05.bit._CRE +#define SCR05_RXE scr05.bit._RXE +#define SCR05_TXE scr05.bit._TXE +__IO_EXTERN __io SMR05STR smr05; +#define SMR05 smr05.byte +#define SMR05_MD1 smr05.bit._MD1 +#define SMR05_MD0 smr05.bit._MD0 +#define SMR05_OTO smr05.bit._OTO +#define SMR05_EXT smr05.bit._EXT +#define SMR05_REST smr05.bit._REST +#define SMR05_UPCL smr05.bit._UPCL +#define SMR05_SCKE smr05.bit._SCKE +#define SMR05_SOE smr05.bit._SOE +#define SMR05_MD smr05.bitc._MD +__IO_EXTERN __io SSR05STR ssr05; +#define SSR05 ssr05.byte +#define SSR05_PE ssr05.bit._PE +#define SSR05_ORE ssr05.bit._ORE +#define SSR05_FRE ssr05.bit._FRE +#define SSR05_RDRF ssr05.bit._RDRF +#define SSR05_TDRE ssr05.bit._TDRE +#define SSR05_BDS ssr05.bit._BDS +#define SSR05_RIE ssr05.bit._RIE +#define SSR05_TIE ssr05.bit._TIE +__IO_EXTERN __io IO_BYTE rdr05; +#define RDR05 rdr05 +__IO_EXTERN __io IO_BYTE tdr05; +#define TDR05 tdr05 +__IO_EXTERN __io ESCR05STR escr05; +#define ESCR05 escr05.byte +#define ESCR05_LBIE escr05.bit._LBIE +#define ESCR05_LBD escr05.bit._LBD +#define ESCR05_LBL1 escr05.bit._LBL1 +#define ESCR05_LBL0 escr05.bit._LBL0 +#define ESCR05_SOPE escr05.bit._SOPE +#define ESCR05_SIOP escr05.bit._SIOP +#define ESCR05_CCO escr05.bit._CCO +#define ESCR05_SCES escr05.bit._SCES +#define ESCR05_LBL escr05.bitc._LBL +__IO_EXTERN __io ECCR05STR eccr05; +#define ECCR05 eccr05.byte +#define ECCR05_INV eccr05.bit._INV +#define ECCR05_LBR eccr05.bit._LBR +#define ECCR05_MS eccr05.bit._MS +#define ECCR05_SCDE eccr05.bit._SCDE +#define ECCR05_SSM eccr05.bit._SSM +#define ECCR05_BIE eccr05.bit._BIE +#define ECCR05_RBI eccr05.bit._RBI +#define ECCR05_TBI eccr05.bit._TBI +__IO_EXTERN __io IO_BYTE fsr05; +#define FSR05 fsr05 +__IO_EXTERN __io FCR05STR fcr05; +#define FCR05 fcr05.byte +#define FCR05_RXL3 fcr05.bit._RXL3 +#define FCR05_RXL2 fcr05.bit._RXL2 +#define FCR05_RXL1 fcr05.bit._RXL1 +#define FCR05_RXL0 fcr05.bit._RXL0 +#define FCR05_ERX fcr05.bit._ERX +#define FCR05_ETX fcr05.bit._ETX +#define FCR05_SVD fcr05.bit._SVD +#define FCR05_RXL fcr05.bitc._RXL +__IO_EXTERN __io SCR06STR scr06; /* USART (LIN) 6 with FIFO */ +#define SCR06 scr06.byte +#define SCR06_PEN scr06.bit._PEN +#define SCR06_P scr06.bit._P +#define SCR06_SBL scr06.bit._SBL +#define SCR06_CL scr06.bit._CL +#define SCR06_AD scr06.bit._AD +#define SCR06_CRE scr06.bit._CRE +#define SCR06_RXE scr06.bit._RXE +#define SCR06_TXE scr06.bit._TXE +__IO_EXTERN __io SMR06STR smr06; +#define SMR06 smr06.byte +#define SMR06_MD1 smr06.bit._MD1 +#define SMR06_MD0 smr06.bit._MD0 +#define SMR06_OTO smr06.bit._OTO +#define SMR06_EXT smr06.bit._EXT +#define SMR06_REST smr06.bit._REST +#define SMR06_UPCL smr06.bit._UPCL +#define SMR06_SCKE smr06.bit._SCKE +#define SMR06_SOE smr06.bit._SOE +#define SMR06_MD smr06.bitc._MD +__IO_EXTERN __io SSR06STR ssr06; +#define SSR06 ssr06.byte +#define SSR06_PE ssr06.bit._PE +#define SSR06_ORE ssr06.bit._ORE +#define SSR06_FRE ssr06.bit._FRE +#define SSR06_RDRF ssr06.bit._RDRF +#define SSR06_TDRE ssr06.bit._TDRE +#define SSR06_BDS ssr06.bit._BDS +#define SSR06_RIE ssr06.bit._RIE +#define SSR06_TIE ssr06.bit._TIE +__IO_EXTERN __io IO_BYTE rdr06; +#define RDR06 rdr06 +__IO_EXTERN __io IO_BYTE tdr06; +#define TDR06 tdr06 +__IO_EXTERN __io ESCR06STR escr06; +#define ESCR06 escr06.byte +#define ESCR06_LBIE escr06.bit._LBIE +#define ESCR06_LBD escr06.bit._LBD +#define ESCR06_LBL1 escr06.bit._LBL1 +#define ESCR06_LBL0 escr06.bit._LBL0 +#define ESCR06_SOPE escr06.bit._SOPE +#define ESCR06_SIOP escr06.bit._SIOP +#define ESCR06_CCO escr06.bit._CCO +#define ESCR06_SCES escr06.bit._SCES +#define ESCR06_LBL escr06.bitc._LBL +__IO_EXTERN __io ECCR06STR eccr06; +#define ECCR06 eccr06.byte +#define ECCR06_INV eccr06.bit._INV +#define ECCR06_LBR eccr06.bit._LBR +#define ECCR06_MS eccr06.bit._MS +#define ECCR06_SCDE eccr06.bit._SCDE +#define ECCR06_SSM eccr06.bit._SSM +#define ECCR06_BIE eccr06.bit._BIE +#define ECCR06_RBI eccr06.bit._RBI +#define ECCR06_TBI eccr06.bit._TBI +__IO_EXTERN __io IO_BYTE fsr06; +#define FSR06 fsr06 +__IO_EXTERN __io FCR06STR fcr06; +#define FCR06 fcr06.byte +#define FCR06_RXL3 fcr06.bit._RXL3 +#define FCR06_RXL2 fcr06.bit._RXL2 +#define FCR06_RXL1 fcr06.bit._RXL1 +#define FCR06_RXL0 fcr06.bit._RXL0 +#define FCR06_ERX fcr06.bit._ERX +#define FCR06_ETX fcr06.bit._ETX +#define FCR06_SVD fcr06.bit._SVD +#define FCR06_RXL fcr06.bitc._RXL +__IO_EXTERN __io SCR07STR scr07; /* USART (LIN) 7 with FIFO */ +#define SCR07 scr07.byte +#define SCR07_PEN scr07.bit._PEN +#define SCR07_P scr07.bit._P +#define SCR07_SBL scr07.bit._SBL +#define SCR07_CL scr07.bit._CL +#define SCR07_AD scr07.bit._AD +#define SCR07_CRE scr07.bit._CRE +#define SCR07_RXE scr07.bit._RXE +#define SCR07_TXE scr07.bit._TXE +__IO_EXTERN __io SMR07STR smr07; +#define SMR07 smr07.byte +#define SMR07_MD1 smr07.bit._MD1 +#define SMR07_MD0 smr07.bit._MD0 +#define SMR07_OTO smr07.bit._OTO +#define SMR07_EXT smr07.bit._EXT +#define SMR07_REST smr07.bit._REST +#define SMR07_UPCL smr07.bit._UPCL +#define SMR07_SCKE smr07.bit._SCKE +#define SMR07_SOE smr07.bit._SOE +#define SMR07_MD smr07.bitc._MD +__IO_EXTERN __io SSR07STR ssr07; +#define SSR07 ssr07.byte +#define SSR07_PE ssr07.bit._PE +#define SSR07_ORE ssr07.bit._ORE +#define SSR07_FRE ssr07.bit._FRE +#define SSR07_RDRF ssr07.bit._RDRF +#define SSR07_TDRE ssr07.bit._TDRE +#define SSR07_BDS ssr07.bit._BDS +#define SSR07_RIE ssr07.bit._RIE +#define SSR07_TIE ssr07.bit._TIE +__IO_EXTERN __io IO_BYTE rdr07; +#define RDR07 rdr07 +__IO_EXTERN __io IO_BYTE tdr07; +#define TDR07 tdr07 +__IO_EXTERN __io ESCR07STR escr07; +#define ESCR07 escr07.byte +#define ESCR07_LBIE escr07.bit._LBIE +#define ESCR07_LBD escr07.bit._LBD +#define ESCR07_LBL1 escr07.bit._LBL1 +#define ESCR07_LBL0 escr07.bit._LBL0 +#define ESCR07_SOPE escr07.bit._SOPE +#define ESCR07_SIOP escr07.bit._SIOP +#define ESCR07_CCO escr07.bit._CCO +#define ESCR07_SCES escr07.bit._SCES +#define ESCR07_LBL escr07.bitc._LBL +__IO_EXTERN __io ECCR07STR eccr07; +#define ECCR07 eccr07.byte +#define ECCR07_INV eccr07.bit._INV +#define ECCR07_LBR eccr07.bit._LBR +#define ECCR07_MS eccr07.bit._MS +#define ECCR07_SCDE eccr07.bit._SCDE +#define ECCR07_SSM eccr07.bit._SSM +#define ECCR07_BIE eccr07.bit._BIE +#define ECCR07_RBI eccr07.bit._RBI +#define ECCR07_TBI eccr07.bit._TBI +__IO_EXTERN __io IO_BYTE fsr07; +#define FSR07 fsr07 +__IO_EXTERN __io FCR07STR fcr07; +#define FCR07 fcr07.byte +#define FCR07_RXL3 fcr07.bit._RXL3 +#define FCR07_RXL2 fcr07.bit._RXL2 +#define FCR07_RXL1 fcr07.bit._RXL1 +#define FCR07_RXL0 fcr07.bit._RXL0 +#define FCR07_ERX fcr07.bit._ERX +#define FCR07_ETX fcr07.bit._ETX +#define FCR07_SVD fcr07.bit._SVD +#define FCR07_RXL fcr07.bitc._RXL +__IO_EXTERN __io IO_WORD bgr02; /* Bauderate Generator USART (LIN) 2,4-7 */ +#define BGR02 bgr02 +__IO_EXTERN __io IO_BYTE bgr102; +#define BGR102 bgr102 +__IO_EXTERN __io IO_BYTE bgr002; +#define BGR002 bgr002 +__IO_EXTERN __io IO_WORD bgr04; +#define BGR04 bgr04 +__IO_EXTERN __io IO_BYTE bgr104; +#define BGR104 bgr104 +__IO_EXTERN __io IO_BYTE bgr004; +#define BGR004 bgr004 +__IO_EXTERN __io IO_WORD bgr05; +#define BGR05 bgr05 +__IO_EXTERN __io IO_BYTE bgr105; +#define BGR105 bgr105 +__IO_EXTERN __io IO_BYTE bgr005; +#define BGR005 bgr005 +__IO_EXTERN __io IO_WORD bgr06; +#define BGR06 bgr06 +__IO_EXTERN __io IO_BYTE bgr106; +#define BGR106 bgr106 +__IO_EXTERN __io IO_BYTE bgr006; +#define BGR006 bgr006 +__IO_EXTERN __io IO_WORD bgr07; +#define BGR07 bgr07 +__IO_EXTERN __io IO_BYTE bgr107; +#define BGR107 bgr107 +__IO_EXTERN __io IO_BYTE bgr007; +#define BGR007 bgr007 +__IO_EXTERN __io PWC20STR pwc20; /* Stepper Motor 0 */ +#define PWC20 pwc20.word +#define PWC20_D9 pwc20.bit._D9 +#define PWC20_D8 pwc20.bit._D8 +#define PWC20_D7 pwc20.bit._D7 +#define PWC20_D6 pwc20.bit._D6 +#define PWC20_D5 pwc20.bit._D5 +#define PWC20_D4 pwc20.bit._D4 +#define PWC20_D3 pwc20.bit._D3 +#define PWC20_D2 pwc20.bit._D2 +#define PWC20_D1 pwc20.bit._D1 +#define PWC20_D0 pwc20.bit._D0 +__IO_EXTERN __io PWC10STR pwc10; +#define PWC10 pwc10.word +#define PWC10_D9 pwc10.bit._D9 +#define PWC10_D8 pwc10.bit._D8 +#define PWC10_D7 pwc10.bit._D7 +#define PWC10_D6 pwc10.bit._D6 +#define PWC10_D5 pwc10.bit._D5 +#define PWC10_D4 pwc10.bit._D4 +#define PWC10_D3 pwc10.bit._D3 +#define PWC10_D2 pwc10.bit._D2 +#define PWC10_D1 pwc10.bit._D1 +#define PWC10_D0 pwc10.bit._D0 +__IO_EXTERN __io PWS20STR pws20; +#define PWS20 pws20.byte +#define PWS20_BS pws20.bit._BS +#define PWS20_P2 pws20.bit._P2 +#define PWS20_P1 pws20.bit._P1 +#define PWS20_P0 pws20.bit._P0 +#define PWS20_M2 pws20.bit._M2 +#define PWS20_M1 pws20.bit._M1 +#define PWS20_M0 pws20.bit._M0 +#define PWS20_P pws20.bitc._P +#define PWS20_M pws20.bitc._M +__IO_EXTERN __io PWS10STR pws10; +#define PWS10 pws10.byte +#define PWS10_P2 pws10.bit._P2 +#define PWS10_P1 pws10.bit._P1 +#define PWS10_P0 pws10.bit._P0 +#define PWS10_M2 pws10.bit._M2 +#define PWS10_M1 pws10.bit._M1 +#define PWS10_M0 pws10.bit._M0 +#define PWS10_P pws10.bitc._P +#define PWS10_M pws10.bitc._M +__IO_EXTERN __io PWC21STR pwc21; /* Stepper Motor 1 */ +#define PWC21 pwc21.word +#define PWC21_D9 pwc21.bit._D9 +#define PWC21_D8 pwc21.bit._D8 +#define PWC21_D7 pwc21.bit._D7 +#define PWC21_D6 pwc21.bit._D6 +#define PWC21_D5 pwc21.bit._D5 +#define PWC21_D4 pwc21.bit._D4 +#define PWC21_D3 pwc21.bit._D3 +#define PWC21_D2 pwc21.bit._D2 +#define PWC21_D1 pwc21.bit._D1 +#define PWC21_D0 pwc21.bit._D0 +__IO_EXTERN __io PWC11STR pwc11; +#define PWC11 pwc11.word +#define PWC11_D9 pwc11.bit._D9 +#define PWC11_D8 pwc11.bit._D8 +#define PWC11_D7 pwc11.bit._D7 +#define PWC11_D6 pwc11.bit._D6 +#define PWC11_D5 pwc11.bit._D5 +#define PWC11_D4 pwc11.bit._D4 +#define PWC11_D3 pwc11.bit._D3 +#define PWC11_D2 pwc11.bit._D2 +#define PWC11_D1 pwc11.bit._D1 +#define PWC11_D0 pwc11.bit._D0 +__IO_EXTERN __io PWS21STR pws21; +#define PWS21 pws21.byte +#define PWS21_BS pws21.bit._BS +#define PWS21_P2 pws21.bit._P2 +#define PWS21_P1 pws21.bit._P1 +#define PWS21_P0 pws21.bit._P0 +#define PWS21_M2 pws21.bit._M2 +#define PWS21_M1 pws21.bit._M1 +#define PWS21_M0 pws21.bit._M0 +#define PWS21_P pws21.bitc._P +#define PWS21_M pws21.bitc._M +__IO_EXTERN __io PWS11STR pws11; +#define PWS11 pws11.byte +#define PWS11_P2 pws11.bit._P2 +#define PWS11_P1 pws11.bit._P1 +#define PWS11_P0 pws11.bit._P0 +#define PWS11_M2 pws11.bit._M2 +#define PWS11_M1 pws11.bit._M1 +#define PWS11_M0 pws11.bit._M0 +#define PWS11_P pws11.bitc._P +#define PWS11_M pws11.bitc._M +__IO_EXTERN __io PWC22STR pwc22; /* Stepper Motor 2 */ +#define PWC22 pwc22.word +#define PWC22_D9 pwc22.bit._D9 +#define PWC22_D8 pwc22.bit._D8 +#define PWC22_D7 pwc22.bit._D7 +#define PWC22_D6 pwc22.bit._D6 +#define PWC22_D5 pwc22.bit._D5 +#define PWC22_D4 pwc22.bit._D4 +#define PWC22_D3 pwc22.bit._D3 +#define PWC22_D2 pwc22.bit._D2 +#define PWC22_D1 pwc22.bit._D1 +#define PWC22_D0 pwc22.bit._D0 +__IO_EXTERN __io PWC12STR pwc12; +#define PWC12 pwc12.word +#define PWC12_D9 pwc12.bit._D9 +#define PWC12_D8 pwc12.bit._D8 +#define PWC12_D7 pwc12.bit._D7 +#define PWC12_D6 pwc12.bit._D6 +#define PWC12_D5 pwc12.bit._D5 +#define PWC12_D4 pwc12.bit._D4 +#define PWC12_D3 pwc12.bit._D3 +#define PWC12_D2 pwc12.bit._D2 +#define PWC12_D1 pwc12.bit._D1 +#define PWC12_D0 pwc12.bit._D0 +__IO_EXTERN __io PWS22STR pws22; +#define PWS22 pws22.byte +#define PWS22_BS pws22.bit._BS +#define PWS22_P2 pws22.bit._P2 +#define PWS22_P1 pws22.bit._P1 +#define PWS22_P0 pws22.bit._P0 +#define PWS22_M2 pws22.bit._M2 +#define PWS22_M1 pws22.bit._M1 +#define PWS22_M0 pws22.bit._M0 +#define PWS22_P pws22.bitc._P +#define PWS22_M pws22.bitc._M +__IO_EXTERN __io PWS12STR pws12; +#define PWS12 pws12.byte +#define PWS12_P2 pws12.bit._P2 +#define PWS12_P1 pws12.bit._P1 +#define PWS12_P0 pws12.bit._P0 +#define PWS12_M2 pws12.bit._M2 +#define PWS12_M1 pws12.bit._M1 +#define PWS12_M0 pws12.bit._M0 +#define PWS12_P pws12.bitc._P +#define PWS12_M pws12.bitc._M +__IO_EXTERN __io PWC23STR pwc23; /* Stepper Motor 3 */ +#define PWC23 pwc23.word +#define PWC23_D9 pwc23.bit._D9 +#define PWC23_D8 pwc23.bit._D8 +#define PWC23_D7 pwc23.bit._D7 +#define PWC23_D6 pwc23.bit._D6 +#define PWC23_D5 pwc23.bit._D5 +#define PWC23_D4 pwc23.bit._D4 +#define PWC23_D3 pwc23.bit._D3 +#define PWC23_D2 pwc23.bit._D2 +#define PWC23_D1 pwc23.bit._D1 +#define PWC23_D0 pwc23.bit._D0 +__IO_EXTERN __io PWC13STR pwc13; +#define PWC13 pwc13.word +#define PWC13_D9 pwc13.bit._D9 +#define PWC13_D8 pwc13.bit._D8 +#define PWC13_D7 pwc13.bit._D7 +#define PWC13_D6 pwc13.bit._D6 +#define PWC13_D5 pwc13.bit._D5 +#define PWC13_D4 pwc13.bit._D4 +#define PWC13_D3 pwc13.bit._D3 +#define PWC13_D2 pwc13.bit._D2 +#define PWC13_D1 pwc13.bit._D1 +#define PWC13_D0 pwc13.bit._D0 +__IO_EXTERN __io PWS23STR pws23; +#define PWS23 pws23.byte +#define PWS23_BS pws23.bit._BS +#define PWS23_P2 pws23.bit._P2 +#define PWS23_P1 pws23.bit._P1 +#define PWS23_P0 pws23.bit._P0 +#define PWS23_M2 pws23.bit._M2 +#define PWS23_M1 pws23.bit._M1 +#define PWS23_M0 pws23.bit._M0 +#define PWS23_P pws23.bitc._P +#define PWS23_M pws23.bitc._M +__IO_EXTERN __io PWS13STR pws13; +#define PWS13 pws13.byte +#define PWS13_P2 pws13.bit._P2 +#define PWS13_P1 pws13.bit._P1 +#define PWS13_P0 pws13.bit._P0 +#define PWS13_M2 pws13.bit._M2 +#define PWS13_M1 pws13.bit._M1 +#define PWS13_M0 pws13.bit._M0 +#define PWS13_P pws13.bitc._P +#define PWS13_M pws13.bitc._M +__IO_EXTERN __io PWC24STR pwc24; /* Stepper Motor 4 */ +#define PWC24 pwc24.word +#define PWC24_D9 pwc24.bit._D9 +#define PWC24_D8 pwc24.bit._D8 +#define PWC24_D7 pwc24.bit._D7 +#define PWC24_D6 pwc24.bit._D6 +#define PWC24_D5 pwc24.bit._D5 +#define PWC24_D4 pwc24.bit._D4 +#define PWC24_D3 pwc24.bit._D3 +#define PWC24_D2 pwc24.bit._D2 +#define PWC24_D1 pwc24.bit._D1 +#define PWC24_D0 pwc24.bit._D0 +__IO_EXTERN __io PWC14STR pwc14; +#define PWC14 pwc14.word +#define PWC14_D9 pwc14.bit._D9 +#define PWC14_D8 pwc14.bit._D8 +#define PWC14_D7 pwc14.bit._D7 +#define PWC14_D6 pwc14.bit._D6 +#define PWC14_D5 pwc14.bit._D5 +#define PWC14_D4 pwc14.bit._D4 +#define PWC14_D3 pwc14.bit._D3 +#define PWC14_D2 pwc14.bit._D2 +#define PWC14_D1 pwc14.bit._D1 +#define PWC14_D0 pwc14.bit._D0 +__IO_EXTERN __io PWS24STR pws24; +#define PWS24 pws24.byte +#define PWS24_BS pws24.bit._BS +#define PWS24_P2 pws24.bit._P2 +#define PWS24_P1 pws24.bit._P1 +#define PWS24_P0 pws24.bit._P0 +#define PWS24_M2 pws24.bit._M2 +#define PWS24_M1 pws24.bit._M1 +#define PWS24_M0 pws24.bit._M0 +#define PWS24_P pws24.bitc._P +#define PWS24_M pws24.bitc._M +__IO_EXTERN __io PWS14STR pws14; +#define PWS14 pws14.byte +#define PWS14_P2 pws14.bit._P2 +#define PWS14_P1 pws14.bit._P1 +#define PWS14_P0 pws14.bit._P0 +#define PWS14_M2 pws14.bit._M2 +#define PWS14_M1 pws14.bit._M1 +#define PWS14_M0 pws14.bit._M0 +#define PWS14_P pws14.bitc._P +#define PWS14_M pws14.bitc._M +__IO_EXTERN __io PWC25STR pwc25; /* Stepper Motor 5 */ +#define PWC25 pwc25.word +#define PWC25_D9 pwc25.bit._D9 +#define PWC25_D8 pwc25.bit._D8 +#define PWC25_D7 pwc25.bit._D7 +#define PWC25_D6 pwc25.bit._D6 +#define PWC25_D5 pwc25.bit._D5 +#define PWC25_D4 pwc25.bit._D4 +#define PWC25_D3 pwc25.bit._D3 +#define PWC25_D2 pwc25.bit._D2 +#define PWC25_D1 pwc25.bit._D1 +#define PWC25_D0 pwc25.bit._D0 +__IO_EXTERN __io PWC15STR pwc15; +#define PWC15 pwc15.word +#define PWC15_D9 pwc15.bit._D9 +#define PWC15_D8 pwc15.bit._D8 +#define PWC15_D7 pwc15.bit._D7 +#define PWC15_D6 pwc15.bit._D6 +#define PWC15_D5 pwc15.bit._D5 +#define PWC15_D4 pwc15.bit._D4 +#define PWC15_D3 pwc15.bit._D3 +#define PWC15_D2 pwc15.bit._D2 +#define PWC15_D1 pwc15.bit._D1 +#define PWC15_D0 pwc15.bit._D0 +__IO_EXTERN __io PWS25STR pws25; +#define PWS25 pws25.byte +#define PWS25_BS pws25.bit._BS +#define PWS25_P2 pws25.bit._P2 +#define PWS25_P1 pws25.bit._P1 +#define PWS25_P0 pws25.bit._P0 +#define PWS25_M2 pws25.bit._M2 +#define PWS25_M1 pws25.bit._M1 +#define PWS25_M0 pws25.bit._M0 +#define PWS25_P pws25.bitc._P +#define PWS25_M pws25.bitc._M +__IO_EXTERN __io PWS15STR pws15; +#define PWS15 pws15.byte +#define PWS15_P2 pws15.bit._P2 +#define PWS15_P1 pws15.bit._P1 +#define PWS15_P0 pws15.bit._P0 +#define PWS15_M2 pws15.bit._M2 +#define PWS15_M1 pws15.bit._M1 +#define PWS15_M0 pws15.bit._M0 +#define PWS15_P pws15.bitc._P +#define PWS15_M pws15.bitc._M +__IO_EXTERN __io PWC0STR pwc0; /* Stepper Motor Control 0-5 */ +#define PWC0 pwc0.byte +#define PWC0_S2 pwc0.bit._S2 +#define PWC0_P2 pwc0.bit._P2 +#define PWC0_P1 pwc0.bit._P1 +#define PWC0_P0 pwc0.bit._P0 +#define PWC0_CE pwc0.bit._CE +#define PWC0_SC pwc0.bit._SC +#define PWC0_P pwc0.bitc._P +__IO_EXTERN __io PWC1STR pwc1; +#define PWC1 pwc1.byte +#define PWC1_S2 pwc1.bit._S2 +#define PWC1_P2 pwc1.bit._P2 +#define PWC1_P1 pwc1.bit._P1 +#define PWC1_P0 pwc1.bit._P0 +#define PWC1_CE pwc1.bit._CE +#define PWC1_SC pwc1.bit._SC +#define PWC1_P pwc1.bitc._P +__IO_EXTERN __io PWC2STR pwc2; +#define PWC2 pwc2.byte +#define PWC2_S2 pwc2.bit._S2 +#define PWC2_P2 pwc2.bit._P2 +#define PWC2_P1 pwc2.bit._P1 +#define PWC2_P0 pwc2.bit._P0 +#define PWC2_CE pwc2.bit._CE +#define PWC2_SC pwc2.bit._SC +#define PWC2_P pwc2.bitc._P +__IO_EXTERN __io PWC3STR pwc3; +#define PWC3 pwc3.byte +#define PWC3_S2 pwc3.bit._S2 +#define PWC3_P2 pwc3.bit._P2 +#define PWC3_P1 pwc3.bit._P1 +#define PWC3_P0 pwc3.bit._P0 +#define PWC3_CE pwc3.bit._CE +#define PWC3_SC pwc3.bit._SC +#define PWC3_P pwc3.bitc._P +__IO_EXTERN __io PWC4STR pwc4; +#define PWC4 pwc4.byte +#define PWC4_S2 pwc4.bit._S2 +#define PWC4_P2 pwc4.bit._P2 +#define PWC4_P1 pwc4.bit._P1 +#define PWC4_P0 pwc4.bit._P0 +#define PWC4_CE pwc4.bit._CE +#define PWC4_SC pwc4.bit._SC +#define PWC4_P pwc4.bitc._P +__IO_EXTERN __io PWC5STR pwc5; +#define PWC5 pwc5.byte +#define PWC5_S2 pwc5.bit._S2 +#define PWC5_P2 pwc5.bit._P2 +#define PWC5_P1 pwc5.bit._P1 +#define PWC5_P0 pwc5.bit._P0 +#define PWC5_CE pwc5.bit._CE +#define PWC5_SC pwc5.bit._SC +#define PWC5_P pwc5.bitc._P +__IO_EXTERN __io IBCR0STR ibcr0; /* I2C 0 */ +#define IBCR0 ibcr0.byte +#define IBCR0_BER ibcr0.bit._BER +#define IBCR0_BEIE ibcr0.bit._BEIE +#define IBCR0_SCC ibcr0.bit._SCC +#define IBCR0_MSS ibcr0.bit._MSS +#define IBCR0_ACK ibcr0.bit._ACK +#define IBCR0_GCAA ibcr0.bit._GCAA +#define IBCR0_INTE ibcr0.bit._INTE +#define IBCR0_INT ibcr0.bit._INT +__IO_EXTERN __io IBSR0STR ibsr0; +#define IBSR0 ibsr0.byte +#define IBSR0_BB ibsr0.bit._BB +#define IBSR0_RSC ibsr0.bit._RSC +#define IBSR0_AL ibsr0.bit._AL +#define IBSR0_LRB ibsr0.bit._LRB +#define IBSR0_TRX ibsr0.bit._TRX +#define IBSR0_AAS ibsr0.bit._AAS +#define IBSR0_GCA ibsr0.bit._GCA +#define IBSR0_ADT ibsr0.bit._ADT +__IO_EXTERN __io ITBA0STR itba0; +#define ITBA0 itba0.word +#define ITBA0_TA9 itba0.bit._TA9 +#define ITBA0_TA8 itba0.bit._TA8 +#define ITBA0_TA7 itba0.bit._TA7 +#define ITBA0_TA6 itba0.bit._TA6 +#define ITBA0_TA5 itba0.bit._TA5 +#define ITBA0_TA4 itba0.bit._TA4 +#define ITBA0_TA3 itba0.bit._TA3 +#define ITBA0_TA2 itba0.bit._TA2 +#define ITBA0_TA1 itba0.bit._TA1 +#define ITBA0_TA0 itba0.bit._TA0 +__IO_EXTERN __io ITBAH0STR itbah0; +#define ITBAH0 itbah0.byte +#define ITBAH0_TA9 itbah0.bit._TA9 +#define ITBAH0_TA8 itbah0.bit._TA8 +__IO_EXTERN __io ITBAL0STR itbal0; +#define ITBAL0 itbal0.byte +#define ITBAL0_TA7 itbal0.bit._TA7 +#define ITBAL0_TA6 itbal0.bit._TA6 +#define ITBAL0_TA5 itbal0.bit._TA5 +#define ITBAL0_TA4 itbal0.bit._TA4 +#define ITBAL0_TA3 itbal0.bit._TA3 +#define ITBAL0_TA2 itbal0.bit._TA2 +#define ITBAL0_TA1 itbal0.bit._TA1 +#define ITBAL0_TA0 itbal0.bit._TA0 +__IO_EXTERN __io ITMK0STR itmk0; +#define ITMK0 itmk0.word +#define ITMK0_ENTB itmk0.bit._ENTB +#define ITMK0_RAL itmk0.bit._RAL +#define ITMK0_TM9 itmk0.bit._TM9 +#define ITMK0_TM8 itmk0.bit._TM8 +#define ITMK0_TM7 itmk0.bit._TM7 +#define ITMK0_TM6 itmk0.bit._TM6 +#define ITMK0_TM5 itmk0.bit._TM5 +#define ITMK0_TM4 itmk0.bit._TM4 +#define ITMK0_TM3 itmk0.bit._TM3 +#define ITMK0_TM2 itmk0.bit._TM2 +#define ITMK0_TM1 itmk0.bit._TM1 +#define ITMK0_TM0 itmk0.bit._TM0 +__IO_EXTERN __io ITMKH0STR itmkh0; +#define ITMKH0 itmkh0.byte +#define ITMKH0_ENTB itmkh0.bit._ENTB +#define ITMKH0_RAL itmkh0.bit._RAL +#define ITMKH0_TM9 itmkh0.bit._TM9 +#define ITMKH0_TM8 itmkh0.bit._TM8 +__IO_EXTERN __io ITMKL0STR itmkl0; +#define ITMKL0 itmkl0.byte +#define ITMKL0_TM7 itmkl0.bit._TM7 +#define ITMKL0_TM6 itmkl0.bit._TM6 +#define ITMKL0_TM5 itmkl0.bit._TM5 +#define ITMKL0_TM4 itmkl0.bit._TM4 +#define ITMKL0_TM3 itmkl0.bit._TM3 +#define ITMKL0_TM2 itmkl0.bit._TM2 +#define ITMKL0_TM1 itmkl0.bit._TM1 +#define ITMKL0_TM0 itmkl0.bit._TM0 +__IO_EXTERN __io ISMK0STR ismk0; +#define ISMK0 ismk0.byte +#define ISMK0_ENSB ismk0.bit._ENSB +#define ISMK0_SM6 ismk0.bit._SM6 +#define ISMK0_SM5 ismk0.bit._SM5 +#define ISMK0_SM4 ismk0.bit._SM4 +#define ISMK0_SM3 ismk0.bit._SM3 +#define ISMK0_SM2 ismk0.bit._SM2 +#define ISMK0_SM1 ismk0.bit._SM1 +#define ISMK0_SM0 ismk0.bit._SM0 +__IO_EXTERN __io ISBA0STR isba0; +#define ISBA0 isba0.byte +#define ISBA0_SA6 isba0.bit._SA6 +#define ISBA0_SA5 isba0.bit._SA5 +#define ISBA0_SA4 isba0.bit._SA4 +#define ISBA0_SA3 isba0.bit._SA3 +#define ISBA0_SA2 isba0.bit._SA2 +#define ISBA0_SA1 isba0.bit._SA1 +#define ISBA0_SA0 isba0.bit._SA0 +__IO_EXTERN __io IDAR0STR idar0; +#define IDAR0 idar0.byte +#define IDAR0_D7 idar0.bit._D7 +#define IDAR0_D6 idar0.bit._D6 +#define IDAR0_D5 idar0.bit._D5 +#define IDAR0_D4 idar0.bit._D4 +#define IDAR0_D3 idar0.bit._D3 +#define IDAR0_D2 idar0.bit._D2 +#define IDAR0_D1 idar0.bit._D1 +#define IDAR0_D0 idar0.bit._D0 +__IO_EXTERN __io ICCR0STR iccr0; +#define ICCR0 iccr0.byte +#define ICCR0_NSF iccr0.bit._NSF +#define ICCR0_EN iccr0.bit._EN +#define ICCR0_CS4 iccr0.bit._CS4 +#define ICCR0_CS3 iccr0.bit._CS3 +#define ICCR0_CS2 iccr0.bit._CS2 +#define ICCR0_CS1 iccr0.bit._CS1 +#define ICCR0_CS0 iccr0.bit._CS0 +#define ICCR0_CS iccr0.bitc._CS +__IO_EXTERN GCN11STR gcn11; /* PPG Control 4-7 */ +#define GCN11 gcn11.word +#define GCN11_TSEL33 gcn11.bit._TSEL33 +#define GCN11_TSEL32 gcn11.bit._TSEL32 +#define GCN11_TSEL31 gcn11.bit._TSEL31 +#define GCN11_TSEL30 gcn11.bit._TSEL30 +#define GCN11_TSEL23 gcn11.bit._TSEL23 +#define GCN11_TSEL22 gcn11.bit._TSEL22 +#define GCN11_TSEL21 gcn11.bit._TSEL21 +#define GCN11_TSEL20 gcn11.bit._TSEL20 +#define GCN11_TSEL13 gcn11.bit._TSEL13 +#define GCN11_TSEL12 gcn11.bit._TSEL12 +#define GCN11_TSEL11 gcn11.bit._TSEL11 +#define GCN11_TSEL10 gcn11.bit._TSEL10 +#define GCN11_TSEL03 gcn11.bit._TSEL03 +#define GCN11_TSEL02 gcn11.bit._TSEL02 +#define GCN11_TSEL01 gcn11.bit._TSEL01 +#define GCN11_TSEL00 gcn11.bit._TSEL00 +__IO_EXTERN GCN21STR gcn21; +#define GCN21 gcn21.byte +#define GCN21_EN3 gcn21.bit._EN3 +#define GCN21_EN2 gcn21.bit._EN2 +#define GCN21_EN1 gcn21.bit._EN1 +#define GCN21_EN0 gcn21.bit._EN0 +__IO_EXTERN GCN12STR gcn12; /* PPG Control 8-11 */ +#define GCN12 gcn12.word +#define GCN12_TSEL33 gcn12.bit._TSEL33 +#define GCN12_TSEL32 gcn12.bit._TSEL32 +#define GCN12_TSEL31 gcn12.bit._TSEL31 +#define GCN12_TSEL30 gcn12.bit._TSEL30 +#define GCN12_TSEL23 gcn12.bit._TSEL23 +#define GCN12_TSEL22 gcn12.bit._TSEL22 +#define GCN12_TSEL21 gcn12.bit._TSEL21 +#define GCN12_TSEL20 gcn12.bit._TSEL20 +#define GCN12_TSEL13 gcn12.bit._TSEL13 +#define GCN12_TSEL12 gcn12.bit._TSEL12 +#define GCN12_TSEL11 gcn12.bit._TSEL11 +#define GCN12_TSEL10 gcn12.bit._TSEL10 +#define GCN12_TSEL03 gcn12.bit._TSEL03 +#define GCN12_TSEL02 gcn12.bit._TSEL02 +#define GCN12_TSEL01 gcn12.bit._TSEL01 +#define GCN12_TSEL00 gcn12.bit._TSEL00 +__IO_EXTERN GCN22STR gcn22; +#define GCN22 gcn22.byte +#define GCN22_EN3 gcn22.bit._EN3 +#define GCN22_EN2 gcn22.bit._EN2 +#define GCN22_EN1 gcn22.bit._EN1 +#define GCN22_EN0 gcn22.bit._EN0 +__IO_EXTERN IO_WORD ptmr04; /* PPG 4 */ +#define PTMR04 ptmr04 +__IO_EXTERN IO_WORD pcsr04; +#define PCSR04 pcsr04 +__IO_EXTERN IO_WORD pdut04; +#define PDUT04 pdut04 +__IO_EXTERN PCN04STR pcn04; +#define PCN04 pcn04.word +#define PCN04_CNTE pcn04.bit._CNTE +#define PCN04_STGR pcn04.bit._STGR +#define PCN04_MDSE pcn04.bit._MDSE +#define PCN04_RTRG pcn04.bit._RTRG +#define PCN04_CKS1 pcn04.bit._CKS1 +#define PCN04_CKS0 pcn04.bit._CKS0 +#define PCN04_PGMS pcn04.bit._PGMS +#define PCN04_EGS1 pcn04.bit._EGS1 +#define PCN04_EGS0 pcn04.bit._EGS0 +#define PCN04_IREN pcn04.bit._IREN +#define PCN04_IRQF pcn04.bit._IRQF +#define PCN04_IRS1 pcn04.bit._IRS1 +#define PCN04_IRS0 pcn04.bit._IRS0 +#define PCN04_OSEL pcn04.bit._OSEL +#define PCN04_CKS pcn04.bitc._CKS +#define PCN04_EGS pcn04.bitc._EGS +#define PCN04_IRS pcn04.bitc._IRS +__IO_EXTERN PCNH04STR pcnh04; +#define PCNH04 pcnh04.byte +#define PCNH04_CNTE pcnh04.bit._CNTE +#define PCNH04_STGR pcnh04.bit._STGR +#define PCNH04_MDSE pcnh04.bit._MDSE +#define PCNH04_RTRG pcnh04.bit._RTRG +#define PCNH04_CKS1 pcnh04.bit._CKS1 +#define PCNH04_CKS0 pcnh04.bit._CKS0 +#define PCNH04_PGMS pcnh04.bit._PGMS +#define PCNH04_CKS pcnh04.bitc._CKS +__IO_EXTERN PCNL04STR pcnl04; +#define PCNL04 pcnl04.byte +#define PCNL04_EGS1 pcnl04.bit._EGS1 +#define PCNL04_EGS0 pcnl04.bit._EGS0 +#define PCNL04_IREN pcnl04.bit._IREN +#define PCNL04_IRQF pcnl04.bit._IRQF +#define PCNL04_IRS1 pcnl04.bit._IRS1 +#define PCNL04_IRS0 pcnl04.bit._IRS0 +#define PCNL04_OSEL pcnl04.bit._OSEL +#define PCNL04_EGS pcnl04.bitc._EGS +#define PCNL04_IRS pcnl04.bitc._IRS +__IO_EXTERN IO_WORD ptmr05; /* PPG 5 */ +#define PTMR05 ptmr05 +__IO_EXTERN IO_WORD pcsr05; +#define PCSR05 pcsr05 +__IO_EXTERN IO_WORD pdut05; +#define PDUT05 pdut05 +__IO_EXTERN PCN05STR pcn05; +#define PCN05 pcn05.word +#define PCN05_CNTE pcn05.bit._CNTE +#define PCN05_STGR pcn05.bit._STGR +#define PCN05_MDSE pcn05.bit._MDSE +#define PCN05_RTRG pcn05.bit._RTRG +#define PCN05_CKS1 pcn05.bit._CKS1 +#define PCN05_CKS0 pcn05.bit._CKS0 +#define PCN05_PGMS pcn05.bit._PGMS +#define PCN05_EGS1 pcn05.bit._EGS1 +#define PCN05_EGS0 pcn05.bit._EGS0 +#define PCN05_IREN pcn05.bit._IREN +#define PCN05_IRQF pcn05.bit._IRQF +#define PCN05_IRS1 pcn05.bit._IRS1 +#define PCN05_IRS0 pcn05.bit._IRS0 +#define PCN05_OSEL pcn05.bit._OSEL +#define PCN05_CKS pcn05.bitc._CKS +#define PCN05_EGS pcn05.bitc._EGS +#define PCN05_IRS pcn05.bitc._IRS +__IO_EXTERN PCNH05STR pcnh05; +#define PCNH05 pcnh05.byte +#define PCNH05_CNTE pcnh05.bit._CNTE +#define PCNH05_STGR pcnh05.bit._STGR +#define PCNH05_MDSE pcnh05.bit._MDSE +#define PCNH05_RTRG pcnh05.bit._RTRG +#define PCNH05_CKS1 pcnh05.bit._CKS1 +#define PCNH05_CKS0 pcnh05.bit._CKS0 +#define PCNH05_PGMS pcnh05.bit._PGMS +#define PCNH05_CKS pcnh05.bitc._CKS +__IO_EXTERN PCNL05STR pcnl05; +#define PCNL05 pcnl05.byte +#define PCNL05_EGS1 pcnl05.bit._EGS1 +#define PCNL05_EGS0 pcnl05.bit._EGS0 +#define PCNL05_IREN pcnl05.bit._IREN +#define PCNL05_IRQF pcnl05.bit._IRQF +#define PCNL05_IRS1 pcnl05.bit._IRS1 +#define PCNL05_IRS0 pcnl05.bit._IRS0 +#define PCNL05_OSEL pcnl05.bit._OSEL +#define PCNL05_EGS pcnl05.bitc._EGS +#define PCNL05_IRS pcnl05.bitc._IRS +__IO_EXTERN IO_WORD ptmr06; /* PPG 6 */ +#define PTMR06 ptmr06 +__IO_EXTERN IO_WORD pcsr06; +#define PCSR06 pcsr06 +__IO_EXTERN IO_WORD pdut06; +#define PDUT06 pdut06 +__IO_EXTERN PCN06STR pcn06; +#define PCN06 pcn06.word +#define PCN06_CNTE pcn06.bit._CNTE +#define PCN06_STGR pcn06.bit._STGR +#define PCN06_MDSE pcn06.bit._MDSE +#define PCN06_RTRG pcn06.bit._RTRG +#define PCN06_CKS1 pcn06.bit._CKS1 +#define PCN06_CKS0 pcn06.bit._CKS0 +#define PCN06_PGMS pcn06.bit._PGMS +#define PCN06_EGS1 pcn06.bit._EGS1 +#define PCN06_EGS0 pcn06.bit._EGS0 +#define PCN06_IREN pcn06.bit._IREN +#define PCN06_IRQF pcn06.bit._IRQF +#define PCN06_IRS1 pcn06.bit._IRS1 +#define PCN06_IRS0 pcn06.bit._IRS0 +#define PCN06_OSEL pcn06.bit._OSEL +#define PCN06_CKS pcn06.bitc._CKS +#define PCN06_EGS pcn06.bitc._EGS +#define PCN06_IRS pcn06.bitc._IRS +__IO_EXTERN PCNH06STR pcnh06; +#define PCNH06 pcnh06.byte +#define PCNH06_CNTE pcnh06.bit._CNTE +#define PCNH06_STGR pcnh06.bit._STGR +#define PCNH06_MDSE pcnh06.bit._MDSE +#define PCNH06_RTRG pcnh06.bit._RTRG +#define PCNH06_CKS1 pcnh06.bit._CKS1 +#define PCNH06_CKS0 pcnh06.bit._CKS0 +#define PCNH06_PGMS pcnh06.bit._PGMS +#define PCNH06_CKS pcnh06.bitc._CKS +__IO_EXTERN PCNL06STR pcnl06; +#define PCNL06 pcnl06.byte +#define PCNL06_EGS1 pcnl06.bit._EGS1 +#define PCNL06_EGS0 pcnl06.bit._EGS0 +#define PCNL06_IREN pcnl06.bit._IREN +#define PCNL06_IRQF pcnl06.bit._IRQF +#define PCNL06_IRS1 pcnl06.bit._IRS1 +#define PCNL06_IRS0 pcnl06.bit._IRS0 +#define PCNL06_OSEL pcnl06.bit._OSEL +#define PCNL06_EGS pcnl06.bitc._EGS +#define PCNL06_IRS pcnl06.bitc._IRS +__IO_EXTERN IO_WORD ptmr07; /* PPG 7 */ +#define PTMR07 ptmr07 +__IO_EXTERN IO_WORD pcsr07; +#define PCSR07 pcsr07 +__IO_EXTERN IO_WORD pdut07; +#define PDUT07 pdut07 +__IO_EXTERN PCN07STR pcn07; +#define PCN07 pcn07.word +#define PCN07_CNTE pcn07.bit._CNTE +#define PCN07_STGR pcn07.bit._STGR +#define PCN07_MDSE pcn07.bit._MDSE +#define PCN07_RTRG pcn07.bit._RTRG +#define PCN07_CKS1 pcn07.bit._CKS1 +#define PCN07_CKS0 pcn07.bit._CKS0 +#define PCN07_PGMS pcn07.bit._PGMS +#define PCN07_EGS1 pcn07.bit._EGS1 +#define PCN07_EGS0 pcn07.bit._EGS0 +#define PCN07_IREN pcn07.bit._IREN +#define PCN07_IRQF pcn07.bit._IRQF +#define PCN07_IRS1 pcn07.bit._IRS1 +#define PCN07_IRS0 pcn07.bit._IRS0 +#define PCN07_OSEL pcn07.bit._OSEL +#define PCN07_CKS pcn07.bitc._CKS +#define PCN07_EGS pcn07.bitc._EGS +#define PCN07_IRS pcn07.bitc._IRS +__IO_EXTERN PCNH07STR pcnh07; +#define PCNH07 pcnh07.byte +#define PCNH07_CNTE pcnh07.bit._CNTE +#define PCNH07_STGR pcnh07.bit._STGR +#define PCNH07_MDSE pcnh07.bit._MDSE +#define PCNH07_RTRG pcnh07.bit._RTRG +#define PCNH07_CKS1 pcnh07.bit._CKS1 +#define PCNH07_CKS0 pcnh07.bit._CKS0 +#define PCNH07_PGMS pcnh07.bit._PGMS +#define PCNH07_CKS pcnh07.bitc._CKS +__IO_EXTERN PCNL07STR pcnl07; +#define PCNL07 pcnl07.byte +#define PCNL07_EGS1 pcnl07.bit._EGS1 +#define PCNL07_EGS0 pcnl07.bit._EGS0 +#define PCNL07_IREN pcnl07.bit._IREN +#define PCNL07_IRQF pcnl07.bit._IRQF +#define PCNL07_IRS1 pcnl07.bit._IRS1 +#define PCNL07_IRS0 pcnl07.bit._IRS0 +#define PCNL07_OSEL pcnl07.bit._OSEL +#define PCNL07_EGS pcnl07.bitc._EGS +#define PCNL07_IRS pcnl07.bitc._IRS +__IO_EXTERN IO_WORD ptmr08; /* PPG 8 */ +#define PTMR08 ptmr08 +__IO_EXTERN IO_WORD pcsr08; +#define PCSR08 pcsr08 +__IO_EXTERN IO_WORD pdut08; +#define PDUT08 pdut08 +__IO_EXTERN PCN08STR pcn08; +#define PCN08 pcn08.word +#define PCN08_CNTE pcn08.bit._CNTE +#define PCN08_STGR pcn08.bit._STGR +#define PCN08_MDSE pcn08.bit._MDSE +#define PCN08_RTRG pcn08.bit._RTRG +#define PCN08_CKS1 pcn08.bit._CKS1 +#define PCN08_CKS0 pcn08.bit._CKS0 +#define PCN08_PGMS pcn08.bit._PGMS +#define PCN08_EGS1 pcn08.bit._EGS1 +#define PCN08_EGS0 pcn08.bit._EGS0 +#define PCN08_IREN pcn08.bit._IREN +#define PCN08_IRQF pcn08.bit._IRQF +#define PCN08_IRS1 pcn08.bit._IRS1 +#define PCN08_IRS0 pcn08.bit._IRS0 +#define PCN08_OSEL pcn08.bit._OSEL +#define PCN08_CKS pcn08.bitc._CKS +#define PCN08_EGS pcn08.bitc._EGS +#define PCN08_IRS pcn08.bitc._IRS +__IO_EXTERN PCNH08STR pcnh08; +#define PCNH08 pcnh08.byte +#define PCNH08_CNTE pcnh08.bit._CNTE +#define PCNH08_STGR pcnh08.bit._STGR +#define PCNH08_MDSE pcnh08.bit._MDSE +#define PCNH08_RTRG pcnh08.bit._RTRG +#define PCNH08_CKS1 pcnh08.bit._CKS1 +#define PCNH08_CKS0 pcnh08.bit._CKS0 +#define PCNH08_PGMS pcnh08.bit._PGMS +#define PCNH08_CKS pcnh08.bitc._CKS +__IO_EXTERN PCNL08STR pcnl08; +#define PCNL08 pcnl08.byte +#define PCNL08_EGS1 pcnl08.bit._EGS1 +#define PCNL08_EGS0 pcnl08.bit._EGS0 +#define PCNL08_IREN pcnl08.bit._IREN +#define PCNL08_IRQF pcnl08.bit._IRQF +#define PCNL08_IRS1 pcnl08.bit._IRS1 +#define PCNL08_IRS0 pcnl08.bit._IRS0 +#define PCNL08_OSEL pcnl08.bit._OSEL +#define PCNL08_EGS pcnl08.bitc._EGS +#define PCNL08_IRS pcnl08.bitc._IRS +__IO_EXTERN IO_WORD ptmr09; /* PPG 9 */ +#define PTMR09 ptmr09 +__IO_EXTERN IO_WORD pcsr09; +#define PCSR09 pcsr09 +__IO_EXTERN IO_WORD pdut09; +#define PDUT09 pdut09 +__IO_EXTERN PCN09STR pcn09; +#define PCN09 pcn09.word +#define PCN09_CNTE pcn09.bit._CNTE +#define PCN09_STGR pcn09.bit._STGR +#define PCN09_MDSE pcn09.bit._MDSE +#define PCN09_RTRG pcn09.bit._RTRG +#define PCN09_CKS1 pcn09.bit._CKS1 +#define PCN09_CKS0 pcn09.bit._CKS0 +#define PCN09_PGMS pcn09.bit._PGMS +#define PCN09_EGS1 pcn09.bit._EGS1 +#define PCN09_EGS0 pcn09.bit._EGS0 +#define PCN09_IREN pcn09.bit._IREN +#define PCN09_IRQF pcn09.bit._IRQF +#define PCN09_IRS1 pcn09.bit._IRS1 +#define PCN09_IRS0 pcn09.bit._IRS0 +#define PCN09_OSEL pcn09.bit._OSEL +#define PCN09_CKS pcn09.bitc._CKS +#define PCN09_EGS pcn09.bitc._EGS +#define PCN09_IRS pcn09.bitc._IRS +__IO_EXTERN PCNH09STR pcnh09; +#define PCNH09 pcnh09.byte +#define PCNH09_CNTE pcnh09.bit._CNTE +#define PCNH09_STGR pcnh09.bit._STGR +#define PCNH09_MDSE pcnh09.bit._MDSE +#define PCNH09_RTRG pcnh09.bit._RTRG +#define PCNH09_CKS1 pcnh09.bit._CKS1 +#define PCNH09_CKS0 pcnh09.bit._CKS0 +#define PCNH09_PGMS pcnh09.bit._PGMS +#define PCNH09_CKS pcnh09.bitc._CKS +__IO_EXTERN PCNL09STR pcnl09; +#define PCNL09 pcnl09.byte +#define PCNL09_EGS1 pcnl09.bit._EGS1 +#define PCNL09_EGS0 pcnl09.bit._EGS0 +#define PCNL09_IREN pcnl09.bit._IREN +#define PCNL09_IRQF pcnl09.bit._IRQF +#define PCNL09_IRS1 pcnl09.bit._IRS1 +#define PCNL09_IRS0 pcnl09.bit._IRS0 +#define PCNL09_OSEL pcnl09.bit._OSEL +#define PCNL09_EGS pcnl09.bitc._EGS +#define PCNL09_IRS pcnl09.bitc._IRS +__IO_EXTERN IO_WORD ptmr10; /* PPG 10 */ +#define PTMR10 ptmr10 +__IO_EXTERN IO_WORD pcsr10; +#define PCSR10 pcsr10 +__IO_EXTERN IO_WORD pdut10; +#define PDUT10 pdut10 +__IO_EXTERN PCN10STR pcn10; +#define PCN10 pcn10.word +#define PCN10_CNTE pcn10.bit._CNTE +#define PCN10_STGR pcn10.bit._STGR +#define PCN10_MDSE pcn10.bit._MDSE +#define PCN10_RTRG pcn10.bit._RTRG +#define PCN10_CKS1 pcn10.bit._CKS1 +#define PCN10_CKS0 pcn10.bit._CKS0 +#define PCN10_PGMS pcn10.bit._PGMS +#define PCN10_EGS1 pcn10.bit._EGS1 +#define PCN10_EGS0 pcn10.bit._EGS0 +#define PCN10_IREN pcn10.bit._IREN +#define PCN10_IRQF pcn10.bit._IRQF +#define PCN10_IRS1 pcn10.bit._IRS1 +#define PCN10_IRS0 pcn10.bit._IRS0 +#define PCN10_OSEL pcn10.bit._OSEL +#define PCN10_CKS pcn10.bitc._CKS +#define PCN10_EGS pcn10.bitc._EGS +#define PCN10_IRS pcn10.bitc._IRS +__IO_EXTERN PCNH10STR pcnh10; +#define PCNH10 pcnh10.byte +#define PCNH10_CNTE pcnh10.bit._CNTE +#define PCNH10_STGR pcnh10.bit._STGR +#define PCNH10_MDSE pcnh10.bit._MDSE +#define PCNH10_RTRG pcnh10.bit._RTRG +#define PCNH10_CKS1 pcnh10.bit._CKS1 +#define PCNH10_CKS0 pcnh10.bit._CKS0 +#define PCNH10_PGMS pcnh10.bit._PGMS +#define PCNH10_CKS pcnh10.bitc._CKS +__IO_EXTERN PCNL10STR pcnl10; +#define PCNL10 pcnl10.byte +#define PCNL10_EGS1 pcnl10.bit._EGS1 +#define PCNL10_EGS0 pcnl10.bit._EGS0 +#define PCNL10_IREN pcnl10.bit._IREN +#define PCNL10_IRQF pcnl10.bit._IRQF +#define PCNL10_IRS1 pcnl10.bit._IRS1 +#define PCNL10_IRS0 pcnl10.bit._IRS0 +#define PCNL10_OSEL pcnl10.bit._OSEL +#define PCNL10_EGS pcnl10.bitc._EGS +#define PCNL10_IRS pcnl10.bitc._IRS +__IO_EXTERN IO_WORD ptmr11; /* PPG 11 */ +#define PTMR11 ptmr11 +__IO_EXTERN IO_WORD pcsr11; +#define PCSR11 pcsr11 +__IO_EXTERN IO_WORD pdut11; +#define PDUT11 pdut11 +__IO_EXTERN PCN11STR pcn11; +#define PCN11 pcn11.word +#define PCN11_CNTE pcn11.bit._CNTE +#define PCN11_STGR pcn11.bit._STGR +#define PCN11_MDSE pcn11.bit._MDSE +#define PCN11_RTRG pcn11.bit._RTRG +#define PCN11_CKS1 pcn11.bit._CKS1 +#define PCN11_CKS0 pcn11.bit._CKS0 +#define PCN11_PGMS pcn11.bit._PGMS +#define PCN11_EGS1 pcn11.bit._EGS1 +#define PCN11_EGS0 pcn11.bit._EGS0 +#define PCN11_IREN pcn11.bit._IREN +#define PCN11_IRQF pcn11.bit._IRQF +#define PCN11_IRS1 pcn11.bit._IRS1 +#define PCN11_IRS0 pcn11.bit._IRS0 +#define PCN11_OSEL pcn11.bit._OSEL +#define PCN11_CKS pcn11.bitc._CKS +#define PCN11_EGS pcn11.bitc._EGS +#define PCN11_IRS pcn11.bitc._IRS +__IO_EXTERN PCNH11STR pcnh11; +#define PCNH11 pcnh11.byte +#define PCNH11_CNTE pcnh11.bit._CNTE +#define PCNH11_STGR pcnh11.bit._STGR +#define PCNH11_MDSE pcnh11.bit._MDSE +#define PCNH11_RTRG pcnh11.bit._RTRG +#define PCNH11_CKS1 pcnh11.bit._CKS1 +#define PCNH11_CKS0 pcnh11.bit._CKS0 +#define PCNH11_PGMS pcnh11.bit._PGMS +#define PCNH11_CKS pcnh11.bitc._CKS +__IO_EXTERN PCNL11STR pcnl11; +#define PCNL11 pcnl11.byte +#define PCNL11_EGS1 pcnl11.bit._EGS1 +#define PCNL11_EGS0 pcnl11.bit._EGS0 +#define PCNL11_IREN pcnl11.bit._IREN +#define PCNL11_IRQF pcnl11.bit._IRQF +#define PCNL11_IRS1 pcnl11.bit._IRS1 +#define PCNL11_IRS0 pcnl11.bit._IRS0 +#define PCNL11_OSEL pcnl11.bit._OSEL +#define PCNL11_EGS pcnl11.bitc._EGS +#define PCNL11_IRS pcnl11.bitc._IRS +__IO_EXTERN P0TMCSRSTR p0tmcsr; /* Pulse Frequency Modulator (PFM) */ +#define P0TMCSR p0tmcsr.word +#define P0TMCSR_INV p0tmcsr.bit._INV +#define P0TMCSR_CSL2 p0tmcsr.bit._CSL2 +#define P0TMCSR_CSL1 p0tmcsr.bit._CSL1 +#define P0TMCSR_CSL0 p0tmcsr.bit._CSL0 +#define P0TMCSR_MOD1 p0tmcsr.bit._MOD1 +#define P0TMCSR_RELD p0tmcsr.bit._RELD +#define P0TMCSR_INTE p0tmcsr.bit._INTE +#define P0TMCSR_UF p0tmcsr.bit._UF +#define P0TMCSR_CNTE p0tmcsr.bit._CNTE +#define P0TMCSR_TRG p0tmcsr.bit._TRG +#define P0TMCSR_CSL p0tmcsr.bitc._CSL +__IO_EXTERN P0TMCSRHSTR p0tmcsrh; +#define P0TMCSRH p0tmcsrh.byte +#define P0TMCSRH_INV p0tmcsrh.bit._INV +#define P0TMCSRH_CSL2 p0tmcsrh.bit._CSL2 +#define P0TMCSRH_CSL1 p0tmcsrh.bit._CSL1 +#define P0TMCSRH_CSL0 p0tmcsrh.bit._CSL0 +#define P0TMCSRH_MOD1 p0tmcsrh.bit._MOD1 +#define P0TMCSRH_CSL p0tmcsrh.bitc._CSL +__IO_EXTERN P0TMCSRLSTR p0tmcsrl; +#define P0TMCSRL p0tmcsrl.byte +#define P0TMCSRL_RELD p0tmcsrl.bit._RELD +#define P0TMCSRL_INTE p0tmcsrl.bit._INTE +#define P0TMCSRL_UF p0tmcsrl.bit._UF +#define P0TMCSRL_CNTE p0tmcsrl.bit._CNTE +#define P0TMCSRL_TRG p0tmcsrl.bit._TRG +__IO_EXTERN P1TMCSRSTR p1tmcsr; +#define P1TMCSR p1tmcsr.word +#define P1TMCSR_INV p1tmcsr.bit._INV +#define P1TMCSR_CSL2 p1tmcsr.bit._CSL2 +#define P1TMCSR_CSL1 p1tmcsr.bit._CSL1 +#define P1TMCSR_CSL0 p1tmcsr.bit._CSL0 +#define P1TMCSR_MOD1 p1tmcsr.bit._MOD1 +#define P1TMCSR_RELD p1tmcsr.bit._RELD +#define P1TMCSR_INTE p1tmcsr.bit._INTE +#define P1TMCSR_UF p1tmcsr.bit._UF +#define P1TMCSR_CNTE p1tmcsr.bit._CNTE +#define P1TMCSR_TRG p1tmcsr.bit._TRG +#define P1TMCSR_CSL p1tmcsr.bitc._CSL +__IO_EXTERN P1TMCSRHSTR p1tmcsrh; +#define P1TMCSRH p1tmcsrh.byte +#define P1TMCSRH_INV p1tmcsrh.bit._INV +#define P1TMCSRH_CSL2 p1tmcsrh.bit._CSL2 +#define P1TMCSRH_CSL1 p1tmcsrh.bit._CSL1 +#define P1TMCSRH_CSL0 p1tmcsrh.bit._CSL0 +#define P1TMCSRH_MOD1 p1tmcsrh.bit._MOD1 +#define P1TMCSRH_CSL p1tmcsrh.bitc._CSL +__IO_EXTERN P1TMCSRLSTR p1tmcsrl; +#define P1TMCSRL p1tmcsrl.byte +#define P1TMCSRL_RELD p1tmcsrl.bit._RELD +#define P1TMCSRL_INTE p1tmcsrl.bit._INTE +#define P1TMCSRL_UF p1tmcsrl.bit._UF +#define P1TMCSRL_CNTE p1tmcsrl.bit._CNTE +#define P1TMCSRL_TRG p1tmcsrl.bit._TRG +__IO_EXTERN IO_WORD p0tmrlr; +#define P0TMRLR p0tmrlr +__IO_EXTERN IO_WORD p0tmr; +#define P0TMR p0tmr +__IO_EXTERN IO_WORD p1tmrlr; +#define P1TMRLR p1tmrlr +__IO_EXTERN IO_WORD p1tmr; +#define P1TMR p1tmr +__IO_EXTERN ICS01STR ics01; /* Input Capture 0-3 */ +#define ICS01 ics01.byte +#define ICS01_ICP1 ics01.bit._ICP1 +#define ICS01_ICP0 ics01.bit._ICP0 +#define ICS01_ICE1 ics01.bit._ICE1 +#define ICS01_ICE0 ics01.bit._ICE0 +#define ICS01_EG11 ics01.bit._EG11 +#define ICS01_EG10 ics01.bit._EG10 +#define ICS01_EG01 ics01.bit._EG01 +#define ICS01_EG00 ics01.bit._EG00 +#define ICS01_EG1 ics01.bitc._EG1 +#define ICS01_EG0 ics01.bitc._EG0 +__IO_EXTERN ICS23STR ics23; +#define ICS23 ics23.byte +#define ICS23_ICP3 ics23.bit._ICP3 +#define ICS23_ICP2 ics23.bit._ICP2 +#define ICS23_ICE3 ics23.bit._ICE3 +#define ICS23_ICE2 ics23.bit._ICE2 +#define ICS23_EG31 ics23.bit._EG31 +#define ICS23_EG30 ics23.bit._EG30 +#define ICS23_EG21 ics23.bit._EG21 +#define ICS23_EG20 ics23.bit._EG20 +#define ICS23_EG3 ics23.bitc._EG3 +#define ICS23_EG2 ics23.bitc._EG2 +__IO_EXTERN IPCP0STR ipcp0; +#define IPCP0 ipcp0.word +#define IPCP0_CP15 ipcp0.bit._CP15 +#define IPCP0_CP14 ipcp0.bit._CP14 +#define IPCP0_CP13 ipcp0.bit._CP13 +#define IPCP0_CP12 ipcp0.bit._CP12 +#define IPCP0_CP11 ipcp0.bit._CP11 +#define IPCP0_CP10 ipcp0.bit._CP10 +#define IPCP0_CP9 ipcp0.bit._CP9 +#define IPCP0_CP8 ipcp0.bit._CP8 +#define IPCP0_CP7 ipcp0.bit._CP7 +#define IPCP0_CP6 ipcp0.bit._CP6 +#define IPCP0_CP5 ipcp0.bit._CP5 +#define IPCP0_CP4 ipcp0.bit._CP4 +#define IPCP0_CP3 ipcp0.bit._CP3 +#define IPCP0_CP2 ipcp0.bit._CP2 +#define IPCP0_CP1 ipcp0.bit._CP1 +#define IPCP0_CP0 ipcp0.bit._CP0 +__IO_EXTERN IPCP1STR ipcp1; +#define IPCP1 ipcp1.word +#define IPCP1_CP15 ipcp1.bit._CP15 +#define IPCP1_CP14 ipcp1.bit._CP14 +#define IPCP1_CP13 ipcp1.bit._CP13 +#define IPCP1_CP12 ipcp1.bit._CP12 +#define IPCP1_CP11 ipcp1.bit._CP11 +#define IPCP1_CP10 ipcp1.bit._CP10 +#define IPCP1_CP9 ipcp1.bit._CP9 +#define IPCP1_CP8 ipcp1.bit._CP8 +#define IPCP1_CP7 ipcp1.bit._CP7 +#define IPCP1_CP6 ipcp1.bit._CP6 +#define IPCP1_CP5 ipcp1.bit._CP5 +#define IPCP1_CP4 ipcp1.bit._CP4 +#define IPCP1_CP3 ipcp1.bit._CP3 +#define IPCP1_CP2 ipcp1.bit._CP2 +#define IPCP1_CP1 ipcp1.bit._CP1 +#define IPCP1_CP0 ipcp1.bit._CP0 +__IO_EXTERN IPCP2STR ipcp2; +#define IPCP2 ipcp2.word +#define IPCP2_CP15 ipcp2.bit._CP15 +#define IPCP2_CP14 ipcp2.bit._CP14 +#define IPCP2_CP13 ipcp2.bit._CP13 +#define IPCP2_CP12 ipcp2.bit._CP12 +#define IPCP2_CP11 ipcp2.bit._CP11 +#define IPCP2_CP10 ipcp2.bit._CP10 +#define IPCP2_CP9 ipcp2.bit._CP9 +#define IPCP2_CP8 ipcp2.bit._CP8 +#define IPCP2_CP7 ipcp2.bit._CP7 +#define IPCP2_CP6 ipcp2.bit._CP6 +#define IPCP2_CP5 ipcp2.bit._CP5 +#define IPCP2_CP4 ipcp2.bit._CP4 +#define IPCP2_CP3 ipcp2.bit._CP3 +#define IPCP2_CP2 ipcp2.bit._CP2 +#define IPCP2_CP1 ipcp2.bit._CP1 +#define IPCP2_CP0 ipcp2.bit._CP0 +__IO_EXTERN IPCP3STR ipcp3; +#define IPCP3 ipcp3.word +#define IPCP3_CP15 ipcp3.bit._CP15 +#define IPCP3_CP14 ipcp3.bit._CP14 +#define IPCP3_CP13 ipcp3.bit._CP13 +#define IPCP3_CP12 ipcp3.bit._CP12 +#define IPCP3_CP11 ipcp3.bit._CP11 +#define IPCP3_CP10 ipcp3.bit._CP10 +#define IPCP3_CP9 ipcp3.bit._CP9 +#define IPCP3_CP8 ipcp3.bit._CP8 +#define IPCP3_CP7 ipcp3.bit._CP7 +#define IPCP3_CP6 ipcp3.bit._CP6 +#define IPCP3_CP5 ipcp3.bit._CP5 +#define IPCP3_CP4 ipcp3.bit._CP4 +#define IPCP3_CP3 ipcp3.bit._CP3 +#define IPCP3_CP2 ipcp3.bit._CP2 +#define IPCP3_CP1 ipcp3.bit._CP1 +#define IPCP3_CP0 ipcp3.bit._CP0 +__IO_EXTERN OCS01STR ocs01; /* Output Compare 0-3 */ +#define OCS01 ocs01.word +#define OCS01_CMOD ocs01.bit._CMOD +#define OCS01_OTD1 ocs01.bit._OTD1 +#define OCS01_OTD0 ocs01.bit._OTD0 +#define OCS01_ICP1 ocs01.bit._ICP1 +#define OCS01_ICP0 ocs01.bit._ICP0 +#define OCS01_ICE1 ocs01.bit._ICE1 +#define OCS01_ICE0 ocs01.bit._ICE0 +#define OCS01_CST1 ocs01.bit._CST1 +#define OCS01_CST0 ocs01.bit._CST0 +__IO_EXTERN OCS23STR ocs23; +#define OCS23 ocs23.word +#define OCS23_CMOD ocs23.bit._CMOD +#define OCS23_OTD3 ocs23.bit._OTD3 +#define OCS23_OTD2 ocs23.bit._OTD2 +#define OCS23_ICP3 ocs23.bit._ICP3 +#define OCS23_ICP2 ocs23.bit._ICP2 +#define OCS23_ICE3 ocs23.bit._ICE3 +#define OCS23_ICE2 ocs23.bit._ICE2 +#define OCS23_CST3 ocs23.bit._CST3 +#define OCS23_CST2 ocs23.bit._CST2 +__IO_EXTERN OCCP0STR occp0; +#define OCCP0 occp0.word +#define OCCP0_C15 occp0.bit._C15 +#define OCCP0_C14 occp0.bit._C14 +#define OCCP0_C13 occp0.bit._C13 +#define OCCP0_C12 occp0.bit._C12 +#define OCCP0_C11 occp0.bit._C11 +#define OCCP0_C10 occp0.bit._C10 +#define OCCP0_C9 occp0.bit._C9 +#define OCCP0_C8 occp0.bit._C8 +#define OCCP0_C7 occp0.bit._C7 +#define OCCP0_C6 occp0.bit._C6 +#define OCCP0_C5 occp0.bit._C5 +#define OCCP0_C4 occp0.bit._C4 +#define OCCP0_C3 occp0.bit._C3 +#define OCCP0_C2 occp0.bit._C2 +#define OCCP0_C1 occp0.bit._C1 +#define OCCP0_C0 occp0.bit._C0 +__IO_EXTERN OCCP1STR occp1; +#define OCCP1 occp1.word +#define OCCP1_C15 occp1.bit._C15 +#define OCCP1_C14 occp1.bit._C14 +#define OCCP1_C13 occp1.bit._C13 +#define OCCP1_C12 occp1.bit._C12 +#define OCCP1_C11 occp1.bit._C11 +#define OCCP1_C10 occp1.bit._C10 +#define OCCP1_C9 occp1.bit._C9 +#define OCCP1_C8 occp1.bit._C8 +#define OCCP1_C7 occp1.bit._C7 +#define OCCP1_C6 occp1.bit._C6 +#define OCCP1_C5 occp1.bit._C5 +#define OCCP1_C4 occp1.bit._C4 +#define OCCP1_C3 occp1.bit._C3 +#define OCCP1_C2 occp1.bit._C2 +#define OCCP1_C1 occp1.bit._C1 +#define OCCP1_C0 occp1.bit._C0 +__IO_EXTERN OCCP2STR occp2; +#define OCCP2 occp2.word +#define OCCP2_C15 occp2.bit._C15 +#define OCCP2_C14 occp2.bit._C14 +#define OCCP2_C13 occp2.bit._C13 +#define OCCP2_C12 occp2.bit._C12 +#define OCCP2_C11 occp2.bit._C11 +#define OCCP2_C10 occp2.bit._C10 +#define OCCP2_C9 occp2.bit._C9 +#define OCCP2_C8 occp2.bit._C8 +#define OCCP2_C7 occp2.bit._C7 +#define OCCP2_C6 occp2.bit._C6 +#define OCCP2_C5 occp2.bit._C5 +#define OCCP2_C4 occp2.bit._C4 +#define OCCP2_C3 occp2.bit._C3 +#define OCCP2_C2 occp2.bit._C2 +#define OCCP2_C1 occp2.bit._C1 +#define OCCP2_C0 occp2.bit._C0 +__IO_EXTERN OCCP3STR occp3; +#define OCCP3 occp3.word +#define OCCP3_C15 occp3.bit._C15 +#define OCCP3_C14 occp3.bit._C14 +#define OCCP3_C13 occp3.bit._C13 +#define OCCP3_C12 occp3.bit._C12 +#define OCCP3_C11 occp3.bit._C11 +#define OCCP3_C10 occp3.bit._C10 +#define OCCP3_C9 occp3.bit._C9 +#define OCCP3_C8 occp3.bit._C8 +#define OCCP3_C7 occp3.bit._C7 +#define OCCP3_C6 occp3.bit._C6 +#define OCCP3_C5 occp3.bit._C5 +#define OCCP3_C4 occp3.bit._C4 +#define OCCP3_C3 occp3.bit._C3 +#define OCCP3_C2 occp3.bit._C2 +#define OCCP3_C1 occp3.bit._C1 +#define OCCP3_C0 occp3.bit._C0 +__IO_EXTERN SGCRSTR sgcr; /* Sound Generator */ +#define SGCR sgcr.word +#define SGCR_TST sgcr.bit._TST +#define SGCR_S2 sgcr.bit._S2 +#define SGCR_S1 sgcr.bit._S1 +#define SGCR_S0 sgcr.bit._S0 +#define SGCR_BUSY sgcr.bit._BUSY +#define SGCR_DEC sgcr.bit._DEC +#define SGCR_TONE sgcr.bit._TONE +#define SGCR_INTE sgcr.bit._INTE +#define SGCR_INT sgcr.bit._INT +#define SGCR_ST sgcr.bit._ST +#define SGCR_S sgcr.bitc._S +__IO_EXTERN SGCRHSTR sgcrh; +#define SGCRH sgcrh.byte +#define SGCRH_TST sgcrh.bit._TST +#define SGCRH_S2 sgcrh.bit._S2 +#define SGCRH_S1 sgcrh.bit._S1 +#define SGCRH_S0 sgcrh.bit._S0 +#define SGCRH_BUSY sgcrh.bit._BUSY +#define SGCRH_DEC sgcrh.bit._DEC +#define SGCRH_S sgcrh.bitc._S +__IO_EXTERN SGCRLSTR sgcrl; +#define SGCRL sgcrl.byte +#define SGCRL_TONE sgcrl.bit._TONE +#define SGCRL_INTE sgcrl.bit._INTE +#define SGCRL_INT sgcrl.bit._INT +#define SGCRL_ST sgcrl.bit._ST +__IO_EXTERN SGFRSTR sgfr; +#define SGFR sgfr.word +#define SGFR_D15 sgfr.bit._D15 +#define SGFR_D14 sgfr.bit._D14 +#define SGFR_D13 sgfr.bit._D13 +#define SGFR_D12 sgfr.bit._D12 +#define SGFR_D11 sgfr.bit._D11 +#define SGFR_D10 sgfr.bit._D10 +#define SGFR_D9 sgfr.bit._D9 +#define SGFR_D8 sgfr.bit._D8 +#define SGFR_D7 sgfr.bit._D7 +#define SGFR_D6 sgfr.bit._D6 +#define SGFR_D5 sgfr.bit._D5 +#define SGFR_D4 sgfr.bit._D4 +#define SGFR_D3 sgfr.bit._D3 +#define SGFR_D2 sgfr.bit._D2 +#define SGFR_D1 sgfr.bit._D1 +#define SGFR_D0 sgfr.bit._D0 +__IO_EXTERN SGARSTR sgar; +#define SGAR sgar.byte +#define SGAR_D7 sgar.bit._D7 +#define SGAR_D6 sgar.bit._D6 +#define SGAR_D5 sgar.bit._D5 +#define SGAR_D4 sgar.bit._D4 +#define SGAR_D3 sgar.bit._D3 +#define SGAR_D2 sgar.bit._D2 +#define SGAR_D1 sgar.bit._D1 +#define SGAR_D0 sgar.bit._D0 +__IO_EXTERN SGTRSTR sgtr; +#define SGTR sgtr.byte +#define SGTR_D7 sgtr.bit._D7 +#define SGTR_D6 sgtr.bit._D6 +#define SGTR_D5 sgtr.bit._D5 +#define SGTR_D4 sgtr.bit._D4 +#define SGTR_D3 sgtr.bit._D3 +#define SGTR_D2 sgtr.bit._D2 +#define SGTR_D1 sgtr.bit._D1 +#define SGTR_D0 sgtr.bit._D0 +__IO_EXTERN SGDRSTR sgdr; +#define SGDR sgdr.byte +#define SGDR_D7 sgdr.bit._D7 +#define SGDR_D6 sgdr.bit._D6 +#define SGDR_D5 sgdr.bit._D5 +#define SGDR_D4 sgdr.bit._D4 +#define SGDR_D3 sgdr.bit._D3 +#define SGDR_D2 sgdr.bit._D2 +#define SGDR_D1 sgdr.bit._D1 +#define SGDR_D0 sgdr.bit._D0 +__IO_EXTERN ADERHSTR aderh; /* ADC */ +#define ADERH aderh.word +#define ADERH_ADE31 aderh.bit._ADE31 +#define ADERH_ADE30 aderh.bit._ADE30 +#define ADERH_ADE29 aderh.bit._ADE29 +#define ADERH_ADE28 aderh.bit._ADE28 +#define ADERH_ADE27 aderh.bit._ADE27 +#define ADERH_ADE26 aderh.bit._ADE26 +#define ADERH_ADE25 aderh.bit._ADE25 +#define ADERH_ADE24 aderh.bit._ADE24 +#define ADERH_ADE23 aderh.bit._ADE23 +#define ADERH_ADE22 aderh.bit._ADE22 +#define ADERH_ADE21 aderh.bit._ADE21 +#define ADERH_ADE20 aderh.bit._ADE20 +#define ADERH_ADE19 aderh.bit._ADE19 +#define ADERH_ADE18 aderh.bit._ADE18 +#define ADERH_ADE17 aderh.bit._ADE17 +#define ADERH_ADE16 aderh.bit._ADE16 +__IO_EXTERN ADERLSTR aderl; +#define ADERL aderl.word +#define ADERL_ADE15 aderl.bit._ADE15 +#define ADERL_ADE14 aderl.bit._ADE14 +#define ADERL_ADE13 aderl.bit._ADE13 +#define ADERL_ADE12 aderl.bit._ADE12 +#define ADERL_ADE11 aderl.bit._ADE11 +#define ADERL_ADE10 aderl.bit._ADE10 +#define ADERL_ADE9 aderl.bit._ADE9 +#define ADERL_ADE8 aderl.bit._ADE8 +#define ADERL_ADE7 aderl.bit._ADE7 +#define ADERL_ADE6 aderl.bit._ADE6 +#define ADERL_ADE5 aderl.bit._ADE5 +#define ADERL_ADE4 aderl.bit._ADE4 +#define ADERL_ADE3 aderl.bit._ADE3 +#define ADERL_ADE2 aderl.bit._ADE2 +#define ADERL_ADE1 aderl.bit._ADE1 +#define ADERL_ADE0 aderl.bit._ADE0 +__IO_EXTERN IO_LWORD ader; +#define ADER ader +__IO_EXTERN ADCS1STR adcs1; +#define ADCS1 adcs1.byte +#define ADCS1_BUSY adcs1.bit._BUSY +#define ADCS1_INT adcs1.bit._INT +#define ADCS1_INTE adcs1.bit._INTE +#define ADCS1_PAUS adcs1.bit._PAUS +#define ADCS1_STS1 adcs1.bit._STS1 +#define ADCS1_STS0 adcs1.bit._STS0 +#define ADCS1_STRT adcs1.bit._STRT +#define ADCS1_STS adcs1.bitc._STS +__IO_EXTERN ADCS0STR adcs0; +#define ADCS0 adcs0.byte +#define ADCS0_MD1 adcs0.bit._MD1 +#define ADCS0_MD0 adcs0.bit._MD0 +#define ADCS0_S10 adcs0.bit._S10 +#define ADCS0_ACH4 adcs0.bit._ACH4 +#define ADCS0_ACH3 adcs0.bit._ACH3 +#define ADCS0_ACH2 adcs0.bit._ACH2 +#define ADCS0_ACH1 adcs0.bit._ACH1 +#define ADCS0_ACH0 adcs0.bit._ACH0 +#define ADCS0_MD adcs0.bitc._MD +#define ADCS0_ACH adcs0.bitc._ACH +__IO_EXTERN IO_WORD adcs; +#define ADCS adcs +__IO_EXTERN ADCR1STR adcr1; +#define ADCR1 adcr1.byte +#define ADCR1_D9 adcr1.bit._D9 +#define ADCR1_D8 adcr1.bit._D8 +__IO_EXTERN ADCR0STR adcr0; +#define ADCR0 adcr0.byte +#define ADCR0_D7 adcr0.bit._D7 +#define ADCR0_D6 adcr0.bit._D6 +#define ADCR0_D5 adcr0.bit._D5 +#define ADCR0_D4 adcr0.bit._D4 +#define ADCR0_D3 adcr0.bit._D3 +#define ADCR0_D2 adcr0.bit._D2 +#define ADCR0_D1 adcr0.bit._D1 +#define ADCR0_D0 adcr0.bit._D0 +__IO_EXTERN IO_WORD adcr; +#define ADCR adcr +__IO_EXTERN ADCT1STR adct1; +#define ADCT1 adct1.byte +#define ADCT1_CT5 adct1.bit._CT5 +#define ADCT1_CT4 adct1.bit._CT4 +#define ADCT1_CT3 adct1.bit._CT3 +#define ADCT1_CT2 adct1.bit._CT2 +#define ADCT1_CT1 adct1.bit._CT1 +#define ADCT1_CT0 adct1.bit._CT0 +#define ADCT1_ST9 adct1.bit._ST9 +#define ADCT1_ST8 adct1.bit._ST8 +__IO_EXTERN ADCT0STR adct0; +#define ADCT0 adct0.byte +#define ADCT0_ST7 adct0.bit._ST7 +#define ADCT0_ST6 adct0.bit._ST6 +#define ADCT0_ST5 adct0.bit._ST5 +#define ADCT0_ST4 adct0.bit._ST4 +#define ADCT0_ST3 adct0.bit._ST3 +#define ADCT0_ST2 adct0.bit._ST2 +#define ADCT0_ST1 adct0.bit._ST1 +#define ADCT0_ST0 adct0.bit._ST0 +__IO_EXTERN IO_WORD adct; +#define ADCT adct +__IO_EXTERN ADSCHSTR adsch; +#define ADSCH adsch.byte +#define ADSCH_ANS4 adsch.bit._ANS4 +#define ADSCH_ANS3 adsch.bit._ANS3 +#define ADSCH_ANS2 adsch.bit._ANS2 +#define ADSCH_ANS1 adsch.bit._ANS1 +#define ADSCH_ASN0 adsch.bit._ASN0 +#define ADSCH_ANS adsch.bitc._ANS +__IO_EXTERN ADECHSTR adech; +#define ADECH adech.byte +#define ADECH_ANE4 adech.bit._ANE4 +#define ADECH_ANE3 adech.bit._ANE3 +#define ADECH_ANE2 adech.bit._ANE2 +#define ADECH_ANE1 adech.bit._ANE1 +#define ADECH_ANE0 adech.bit._ANE0 +#define ADECH_ANE adech.bitc._ANE +__IO_EXTERN ACSR0STR acsr0; /* Alarm Comparator 0-1 */ +#define ACSR0 acsr0.byte +#define ACSR0_MD acsr0.bit._MD +#define ACSR0_OV_EN acsr0.bit._OV_EN +#define ACSR0_UV_EN acsr0.bit._UV_EN +#define ACSR0_OUT2 acsr0.bit._OUT2 +#define ACSR0_OUT1 acsr0.bit._OUT1 +#define ACSR0_IRQ acsr0.bit._IRQ +#define ACSR0_IEN acsr0.bit._IEN +#define ACSR0_PD acsr0.bit._PD +__IO_EXTERN TMRLR0STR tmrlr0; /* Reload Timer 0 */ +#define TMRLR0 tmrlr0.word +#define TMRLR0_D15 tmrlr0.bit._D15 +#define TMRLR0_D14 tmrlr0.bit._D14 +#define TMRLR0_D13 tmrlr0.bit._D13 +#define TMRLR0_D12 tmrlr0.bit._D12 +#define TMRLR0_D11 tmrlr0.bit._D11 +#define TMRLR0_D10 tmrlr0.bit._D10 +#define TMRLR0_D9 tmrlr0.bit._D9 +#define TMRLR0_D8 tmrlr0.bit._D8 +#define TMRLR0_D7 tmrlr0.bit._D7 +#define TMRLR0_D6 tmrlr0.bit._D6 +#define TMRLR0_D5 tmrlr0.bit._D5 +#define TMRLR0_D4 tmrlr0.bit._D4 +#define TMRLR0_D3 tmrlr0.bit._D3 +#define TMRLR0_D2 tmrlr0.bit._D2 +#define TMRLR0_D1 tmrlr0.bit._D1 +#define TMRLR0_D0 tmrlr0.bit._D0 +__IO_EXTERN TMR0STR tmr0; +#define TMR0 tmr0.word +#define TMR0_D15 tmr0.bit._D15 +#define TMR0_D14 tmr0.bit._D14 +#define TMR0_D13 tmr0.bit._D13 +#define TMR0_D12 tmr0.bit._D12 +#define TMR0_D11 tmr0.bit._D11 +#define TMR0_D10 tmr0.bit._D10 +#define TMR0_D9 tmr0.bit._D9 +#define TMR0_D8 tmr0.bit._D8 +#define TMR0_D7 tmr0.bit._D7 +#define TMR0_D6 tmr0.bit._D6 +#define TMR0_D5 tmr0.bit._D5 +#define TMR0_D4 tmr0.bit._D4 +#define TMR0_D3 tmr0.bit._D3 +#define TMR0_D2 tmr0.bit._D2 +#define TMR0_D1 tmr0.bit._D1 +#define TMR0_D0 tmr0.bit._D0 +__IO_EXTERN TMCSR0STR tmcsr0; +#define TMCSR0 tmcsr0.word +#define TMCSR0_CSL2 tmcsr0.bit._CSL2 +#define TMCSR0_CSL1 tmcsr0.bit._CSL1 +#define TMCSR0_CSL0 tmcsr0.bit._CSL0 +#define TMCSR0_MOD2 tmcsr0.bit._MOD2 +#define TMCSR0_MOD1 tmcsr0.bit._MOD1 +#define TMCSR0_MOD0 tmcsr0.bit._MOD0 +#define TMCSR0_OUTL tmcsr0.bit._OUTL +#define TMCSR0_RELD tmcsr0.bit._RELD +#define TMCSR0_INTE tmcsr0.bit._INTE +#define TMCSR0_UF tmcsr0.bit._UF +#define TMCSR0_CNTE tmcsr0.bit._CNTE +#define TMCSR0_TRG tmcsr0.bit._TRG +#define TMCSR0_CSL tmcsr0.bitc._CSL +#define TMCSR0_MOD tmcsr0.bitc._MOD +__IO_EXTERN TMCSRH0STR tmcsrh0; +#define TMCSRH0 tmcsrh0.byte +#define TMCSRH0_CSL2 tmcsrh0.bit._CSL2 +#define TMCSRH0_CSL1 tmcsrh0.bit._CSL1 +#define TMCSRH0_CSL0 tmcsrh0.bit._CSL0 +#define TMCSRH0_MOD2 tmcsrh0.bit._MOD2 +#define TMCSRH0_MOD1 tmcsrh0.bit._MOD1 +#define TMCSRH0_CSL tmcsrh0.bitc._CSL +__IO_EXTERN TMCSRL0STR tmcsrl0; +#define TMCSRL0 tmcsrl0.byte +#define TMCSRL0_MOD0 tmcsrl0.bit._MOD0 +#define TMCSRL0_OUTL tmcsrl0.bit._OUTL +#define TMCSRL0_RELD tmcsrl0.bit._RELD +#define TMCSRL0_INTE tmcsrl0.bit._INTE +#define TMCSRL0_UF tmcsrl0.bit._UF +#define TMCSRL0_CNTE tmcsrl0.bit._CNTE +#define TMCSRL0_TRG tmcsrl0.bit._TRG +__IO_EXTERN TMRLR1STR tmrlr1; /* Reload Timer 1 */ +#define TMRLR1 tmrlr1.word +#define TMRLR1_D15 tmrlr1.bit._D15 +#define TMRLR1_D14 tmrlr1.bit._D14 +#define TMRLR1_D13 tmrlr1.bit._D13 +#define TMRLR1_D12 tmrlr1.bit._D12 +#define TMRLR1_D11 tmrlr1.bit._D11 +#define TMRLR1_D10 tmrlr1.bit._D10 +#define TMRLR1_D9 tmrlr1.bit._D9 +#define TMRLR1_D8 tmrlr1.bit._D8 +#define TMRLR1_D7 tmrlr1.bit._D7 +#define TMRLR1_D6 tmrlr1.bit._D6 +#define TMRLR1_D5 tmrlr1.bit._D5 +#define TMRLR1_D4 tmrlr1.bit._D4 +#define TMRLR1_D3 tmrlr1.bit._D3 +#define TMRLR1_D2 tmrlr1.bit._D2 +#define TMRLR1_D1 tmrlr1.bit._D1 +#define TMRLR1_D0 tmrlr1.bit._D0 +__IO_EXTERN TMR1STR tmr1; +#define TMR1 tmr1.word +#define TMR1_D15 tmr1.bit._D15 +#define TMR1_D14 tmr1.bit._D14 +#define TMR1_D13 tmr1.bit._D13 +#define TMR1_D12 tmr1.bit._D12 +#define TMR1_D11 tmr1.bit._D11 +#define TMR1_D10 tmr1.bit._D10 +#define TMR1_D9 tmr1.bit._D9 +#define TMR1_D8 tmr1.bit._D8 +#define TMR1_D7 tmr1.bit._D7 +#define TMR1_D6 tmr1.bit._D6 +#define TMR1_D5 tmr1.bit._D5 +#define TMR1_D4 tmr1.bit._D4 +#define TMR1_D3 tmr1.bit._D3 +#define TMR1_D2 tmr1.bit._D2 +#define TMR1_D1 tmr1.bit._D1 +#define TMR1_D0 tmr1.bit._D0 +__IO_EXTERN TMCSR1STR tmcsr1; +#define TMCSR1 tmcsr1.word +#define TMCSR1_CSL2 tmcsr1.bit._CSL2 +#define TMCSR1_CSL1 tmcsr1.bit._CSL1 +#define TMCSR1_CSL0 tmcsr1.bit._CSL0 +#define TMCSR1_MOD2 tmcsr1.bit._MOD2 +#define TMCSR1_MOD1 tmcsr1.bit._MOD1 +#define TMCSR1_MOD0 tmcsr1.bit._MOD0 +#define TMCSR1_OUTL tmcsr1.bit._OUTL +#define TMCSR1_RELD tmcsr1.bit._RELD +#define TMCSR1_INTE tmcsr1.bit._INTE +#define TMCSR1_UF tmcsr1.bit._UF +#define TMCSR1_CNTE tmcsr1.bit._CNTE +#define TMCSR1_TRG tmcsr1.bit._TRG +#define TMCSR1_CSL tmcsr1.bitc._CSL +#define TMCSR1_MOD tmcsr1.bitc._MOD +__IO_EXTERN TMCSRH1STR tmcsrh1; +#define TMCSRH1 tmcsrh1.byte +#define TMCSRH1_CSL2 tmcsrh1.bit._CSL2 +#define TMCSRH1_CSL1 tmcsrh1.bit._CSL1 +#define TMCSRH1_CSL0 tmcsrh1.bit._CSL0 +#define TMCSRH1_MOD2 tmcsrh1.bit._MOD2 +#define TMCSRH1_MOD1 tmcsrh1.bit._MOD1 +#define TMCSRH1_CSL tmcsrh1.bitc._CSL +__IO_EXTERN TMCSRL1STR tmcsrl1; +#define TMCSRL1 tmcsrl1.byte +#define TMCSRL1_MOD0 tmcsrl1.bit._MOD0 +#define TMCSRL1_OUTL tmcsrl1.bit._OUTL +#define TMCSRL1_RELD tmcsrl1.bit._RELD +#define TMCSRL1_INTE tmcsrl1.bit._INTE +#define TMCSRL1_UF tmcsrl1.bit._UF +#define TMCSRL1_CNTE tmcsrl1.bit._CNTE +#define TMCSRL1_TRG tmcsrl1.bit._TRG +__IO_EXTERN TMRLR2STR tmrlr2; /* Reload Timer 2 */ +#define TMRLR2 tmrlr2.word +#define TMRLR2_D15 tmrlr2.bit._D15 +#define TMRLR2_D14 tmrlr2.bit._D14 +#define TMRLR2_D13 tmrlr2.bit._D13 +#define TMRLR2_D12 tmrlr2.bit._D12 +#define TMRLR2_D11 tmrlr2.bit._D11 +#define TMRLR2_D10 tmrlr2.bit._D10 +#define TMRLR2_D9 tmrlr2.bit._D9 +#define TMRLR2_D8 tmrlr2.bit._D8 +#define TMRLR2_D7 tmrlr2.bit._D7 +#define TMRLR2_D6 tmrlr2.bit._D6 +#define TMRLR2_D5 tmrlr2.bit._D5 +#define TMRLR2_D4 tmrlr2.bit._D4 +#define TMRLR2_D3 tmrlr2.bit._D3 +#define TMRLR2_D2 tmrlr2.bit._D2 +#define TMRLR2_D1 tmrlr2.bit._D1 +#define TMRLR2_D0 tmrlr2.bit._D0 +__IO_EXTERN TMR2STR tmr2; +#define TMR2 tmr2.word +#define TMR2_D15 tmr2.bit._D15 +#define TMR2_D14 tmr2.bit._D14 +#define TMR2_D13 tmr2.bit._D13 +#define TMR2_D12 tmr2.bit._D12 +#define TMR2_D11 tmr2.bit._D11 +#define TMR2_D10 tmr2.bit._D10 +#define TMR2_D9 tmr2.bit._D9 +#define TMR2_D8 tmr2.bit._D8 +#define TMR2_D7 tmr2.bit._D7 +#define TMR2_D6 tmr2.bit._D6 +#define TMR2_D5 tmr2.bit._D5 +#define TMR2_D4 tmr2.bit._D4 +#define TMR2_D3 tmr2.bit._D3 +#define TMR2_D2 tmr2.bit._D2 +#define TMR2_D1 tmr2.bit._D1 +#define TMR2_D0 tmr2.bit._D0 +__IO_EXTERN TMCSR2STR tmcsr2; +#define TMCSR2 tmcsr2.word +#define TMCSR2_CSL2 tmcsr2.bit._CSL2 +#define TMCSR2_CSL1 tmcsr2.bit._CSL1 +#define TMCSR2_CSL0 tmcsr2.bit._CSL0 +#define TMCSR2_MOD2 tmcsr2.bit._MOD2 +#define TMCSR2_MOD1 tmcsr2.bit._MOD1 +#define TMCSR2_MOD0 tmcsr2.bit._MOD0 +#define TMCSR2_OUTL tmcsr2.bit._OUTL +#define TMCSR2_RELD tmcsr2.bit._RELD +#define TMCSR2_INTE tmcsr2.bit._INTE +#define TMCSR2_UF tmcsr2.bit._UF +#define TMCSR2_CNTE tmcsr2.bit._CNTE +#define TMCSR2_TRG tmcsr2.bit._TRG +#define TMCSR2_CSL tmcsr2.bitc._CSL +#define TMCSR2_MOD tmcsr2.bitc._MOD +__IO_EXTERN TMCSRH2STR tmcsrh2; +#define TMCSRH2 tmcsrh2.byte +#define TMCSRH2_CSL2 tmcsrh2.bit._CSL2 +#define TMCSRH2_CSL1 tmcsrh2.bit._CSL1 +#define TMCSRH2_CSL0 tmcsrh2.bit._CSL0 +#define TMCSRH2_MOD2 tmcsrh2.bit._MOD2 +#define TMCSRH2_MOD1 tmcsrh2.bit._MOD1 +#define TMCSRH2_CSL tmcsrh2.bitc._CSL +__IO_EXTERN TMCSRL2STR tmcsrl2; +#define TMCSRL2 tmcsrl2.byte +#define TMCSRL2_MOD0 tmcsrl2.bit._MOD0 +#define TMCSRL2_OUTL tmcsrl2.bit._OUTL +#define TMCSRL2_RELD tmcsrl2.bit._RELD +#define TMCSRL2_INTE tmcsrl2.bit._INTE +#define TMCSRL2_UF tmcsrl2.bit._UF +#define TMCSRL2_CNTE tmcsrl2.bit._CNTE +#define TMCSRL2_TRG tmcsrl2.bit._TRG +__IO_EXTERN TMRLR3STR tmrlr3; /* Reload Timer 3 */ +#define TMRLR3 tmrlr3.word +#define TMRLR3_D15 tmrlr3.bit._D15 +#define TMRLR3_D14 tmrlr3.bit._D14 +#define TMRLR3_D13 tmrlr3.bit._D13 +#define TMRLR3_D12 tmrlr3.bit._D12 +#define TMRLR3_D11 tmrlr3.bit._D11 +#define TMRLR3_D10 tmrlr3.bit._D10 +#define TMRLR3_D9 tmrlr3.bit._D9 +#define TMRLR3_D8 tmrlr3.bit._D8 +#define TMRLR3_D7 tmrlr3.bit._D7 +#define TMRLR3_D6 tmrlr3.bit._D6 +#define TMRLR3_D5 tmrlr3.bit._D5 +#define TMRLR3_D4 tmrlr3.bit._D4 +#define TMRLR3_D3 tmrlr3.bit._D3 +#define TMRLR3_D2 tmrlr3.bit._D2 +#define TMRLR3_D1 tmrlr3.bit._D1 +#define TMRLR3_D0 tmrlr3.bit._D0 +__IO_EXTERN TMR3STR tmr3; +#define TMR3 tmr3.word +#define TMR3_D15 tmr3.bit._D15 +#define TMR3_D14 tmr3.bit._D14 +#define TMR3_D13 tmr3.bit._D13 +#define TMR3_D12 tmr3.bit._D12 +#define TMR3_D11 tmr3.bit._D11 +#define TMR3_D10 tmr3.bit._D10 +#define TMR3_D9 tmr3.bit._D9 +#define TMR3_D8 tmr3.bit._D8 +#define TMR3_D7 tmr3.bit._D7 +#define TMR3_D6 tmr3.bit._D6 +#define TMR3_D5 tmr3.bit._D5 +#define TMR3_D4 tmr3.bit._D4 +#define TMR3_D3 tmr3.bit._D3 +#define TMR3_D2 tmr3.bit._D2 +#define TMR3_D1 tmr3.bit._D1 +#define TMR3_D0 tmr3.bit._D0 +__IO_EXTERN TMCSR3STR tmcsr3; +#define TMCSR3 tmcsr3.word +#define TMCSR3_CSL2 tmcsr3.bit._CSL2 +#define TMCSR3_CSL1 tmcsr3.bit._CSL1 +#define TMCSR3_CSL0 tmcsr3.bit._CSL0 +#define TMCSR3_MOD2 tmcsr3.bit._MOD2 +#define TMCSR3_MOD1 tmcsr3.bit._MOD1 +#define TMCSR3_MOD0 tmcsr3.bit._MOD0 +#define TMCSR3_OUTL tmcsr3.bit._OUTL +#define TMCSR3_RELD tmcsr3.bit._RELD +#define TMCSR3_INTE tmcsr3.bit._INTE +#define TMCSR3_UF tmcsr3.bit._UF +#define TMCSR3_CNTE tmcsr3.bit._CNTE +#define TMCSR3_TRG tmcsr3.bit._TRG +#define TMCSR3_CSL tmcsr3.bitc._CSL +#define TMCSR3_MOD tmcsr3.bitc._MOD +__IO_EXTERN TMCSRH3STR tmcsrh3; +#define TMCSRH3 tmcsrh3.byte +#define TMCSRH3_CSL2 tmcsrh3.bit._CSL2 +#define TMCSRH3_CSL1 tmcsrh3.bit._CSL1 +#define TMCSRH3_CSL0 tmcsrh3.bit._CSL0 +#define TMCSRH3_MOD2 tmcsrh3.bit._MOD2 +#define TMCSRH3_MOD1 tmcsrh3.bit._MOD1 +#define TMCSRH3_CSL tmcsrh3.bitc._CSL +__IO_EXTERN TMCSRL3STR tmcsrl3; +#define TMCSRL3 tmcsrl3.byte +#define TMCSRL3_MOD0 tmcsrl3.bit._MOD0 +#define TMCSRL3_OUTL tmcsrl3.bit._OUTL +#define TMCSRL3_RELD tmcsrl3.bit._RELD +#define TMCSRL3_INTE tmcsrl3.bit._INTE +#define TMCSRL3_UF tmcsrl3.bit._UF +#define TMCSRL3_CNTE tmcsrl3.bit._CNTE +#define TMCSRL3_TRG tmcsrl3.bit._TRG +__IO_EXTERN TMRLR4STR tmrlr4; /* Reload Timer 4 */ +#define TMRLR4 tmrlr4.word +#define TMRLR4_D15 tmrlr4.bit._D15 +#define TMRLR4_D14 tmrlr4.bit._D14 +#define TMRLR4_D13 tmrlr4.bit._D13 +#define TMRLR4_D12 tmrlr4.bit._D12 +#define TMRLR4_D11 tmrlr4.bit._D11 +#define TMRLR4_D10 tmrlr4.bit._D10 +#define TMRLR4_D9 tmrlr4.bit._D9 +#define TMRLR4_D8 tmrlr4.bit._D8 +#define TMRLR4_D7 tmrlr4.bit._D7 +#define TMRLR4_D6 tmrlr4.bit._D6 +#define TMRLR4_D5 tmrlr4.bit._D5 +#define TMRLR4_D4 tmrlr4.bit._D4 +#define TMRLR4_D3 tmrlr4.bit._D3 +#define TMRLR4_D2 tmrlr4.bit._D2 +#define TMRLR4_D1 tmrlr4.bit._D1 +#define TMRLR4_D0 tmrlr4.bit._D0 +__IO_EXTERN TMR4STR tmr4; +#define TMR4 tmr4.word +#define TMR4_D15 tmr4.bit._D15 +#define TMR4_D14 tmr4.bit._D14 +#define TMR4_D13 tmr4.bit._D13 +#define TMR4_D12 tmr4.bit._D12 +#define TMR4_D11 tmr4.bit._D11 +#define TMR4_D10 tmr4.bit._D10 +#define TMR4_D9 tmr4.bit._D9 +#define TMR4_D8 tmr4.bit._D8 +#define TMR4_D7 tmr4.bit._D7 +#define TMR4_D6 tmr4.bit._D6 +#define TMR4_D5 tmr4.bit._D5 +#define TMR4_D4 tmr4.bit._D4 +#define TMR4_D3 tmr4.bit._D3 +#define TMR4_D2 tmr4.bit._D2 +#define TMR4_D1 tmr4.bit._D1 +#define TMR4_D0 tmr4.bit._D0 +__IO_EXTERN TMCSR4STR tmcsr4; +#define TMCSR4 tmcsr4.word +#define TMCSR4_CSL2 tmcsr4.bit._CSL2 +#define TMCSR4_CSL1 tmcsr4.bit._CSL1 +#define TMCSR4_CSL0 tmcsr4.bit._CSL0 +#define TMCSR4_MOD2 tmcsr4.bit._MOD2 +#define TMCSR4_MOD1 tmcsr4.bit._MOD1 +#define TMCSR4_MOD0 tmcsr4.bit._MOD0 +#define TMCSR4_OUTL tmcsr4.bit._OUTL +#define TMCSR4_RELD tmcsr4.bit._RELD +#define TMCSR4_INTE tmcsr4.bit._INTE +#define TMCSR4_UF tmcsr4.bit._UF +#define TMCSR4_CNTE tmcsr4.bit._CNTE +#define TMCSR4_TRG tmcsr4.bit._TRG +#define TMCSR4_CSL tmcsr4.bitc._CSL +#define TMCSR4_MOD tmcsr4.bitc._MOD +__IO_EXTERN TMCSRH4STR tmcsrh4; +#define TMCSRH4 tmcsrh4.byte +#define TMCSRH4_CSL2 tmcsrh4.bit._CSL2 +#define TMCSRH4_CSL1 tmcsrh4.bit._CSL1 +#define TMCSRH4_CSL0 tmcsrh4.bit._CSL0 +#define TMCSRH4_MOD2 tmcsrh4.bit._MOD2 +#define TMCSRH4_MOD1 tmcsrh4.bit._MOD1 +#define TMCSRH4_CSL tmcsrh4.bitc._CSL +__IO_EXTERN TMCSRL4STR tmcsrl4; +#define TMCSRL4 tmcsrl4.byte +#define TMCSRL4_MOD0 tmcsrl4.bit._MOD0 +#define TMCSRL4_OUTL tmcsrl4.bit._OUTL +#define TMCSRL4_RELD tmcsrl4.bit._RELD +#define TMCSRL4_INTE tmcsrl4.bit._INTE +#define TMCSRL4_UF tmcsrl4.bit._UF +#define TMCSRL4_CNTE tmcsrl4.bit._CNTE +#define TMCSRL4_TRG tmcsrl4.bit._TRG +__IO_EXTERN TMRLR5STR tmrlr5; /* Reload Timer 5 */ +#define TMRLR5 tmrlr5.word +#define TMRLR5_D15 tmrlr5.bit._D15 +#define TMRLR5_D14 tmrlr5.bit._D14 +#define TMRLR5_D13 tmrlr5.bit._D13 +#define TMRLR5_D12 tmrlr5.bit._D12 +#define TMRLR5_D11 tmrlr5.bit._D11 +#define TMRLR5_D10 tmrlr5.bit._D10 +#define TMRLR5_D9 tmrlr5.bit._D9 +#define TMRLR5_D8 tmrlr5.bit._D8 +#define TMRLR5_D7 tmrlr5.bit._D7 +#define TMRLR5_D6 tmrlr5.bit._D6 +#define TMRLR5_D5 tmrlr5.bit._D5 +#define TMRLR5_D4 tmrlr5.bit._D4 +#define TMRLR5_D3 tmrlr5.bit._D3 +#define TMRLR5_D2 tmrlr5.bit._D2 +#define TMRLR5_D1 tmrlr5.bit._D1 +#define TMRLR5_D0 tmrlr5.bit._D0 +__IO_EXTERN TMR5STR tmr5; +#define TMR5 tmr5.word +#define TMR5_D15 tmr5.bit._D15 +#define TMR5_D14 tmr5.bit._D14 +#define TMR5_D13 tmr5.bit._D13 +#define TMR5_D12 tmr5.bit._D12 +#define TMR5_D11 tmr5.bit._D11 +#define TMR5_D10 tmr5.bit._D10 +#define TMR5_D9 tmr5.bit._D9 +#define TMR5_D8 tmr5.bit._D8 +#define TMR5_D7 tmr5.bit._D7 +#define TMR5_D6 tmr5.bit._D6 +#define TMR5_D5 tmr5.bit._D5 +#define TMR5_D4 tmr5.bit._D4 +#define TMR5_D3 tmr5.bit._D3 +#define TMR5_D2 tmr5.bit._D2 +#define TMR5_D1 tmr5.bit._D1 +#define TMR5_D0 tmr5.bit._D0 +__IO_EXTERN TMCSR5STR tmcsr5; +#define TMCSR5 tmcsr5.word +#define TMCSR5_CSL2 tmcsr5.bit._CSL2 +#define TMCSR5_CSL1 tmcsr5.bit._CSL1 +#define TMCSR5_CSL0 tmcsr5.bit._CSL0 +#define TMCSR5_MOD2 tmcsr5.bit._MOD2 +#define TMCSR5_MOD1 tmcsr5.bit._MOD1 +#define TMCSR5_MOD0 tmcsr5.bit._MOD0 +#define TMCSR5_OUTL tmcsr5.bit._OUTL +#define TMCSR5_RELD tmcsr5.bit._RELD +#define TMCSR5_INTE tmcsr5.bit._INTE +#define TMCSR5_UF tmcsr5.bit._UF +#define TMCSR5_CNTE tmcsr5.bit._CNTE +#define TMCSR5_TRG tmcsr5.bit._TRG +#define TMCSR5_CSL tmcsr5.bitc._CSL +#define TMCSR5_MOD tmcsr5.bitc._MOD +__IO_EXTERN TMCSRH5STR tmcsrh5; +#define TMCSRH5 tmcsrh5.byte +#define TMCSRH5_CSL2 tmcsrh5.bit._CSL2 +#define TMCSRH5_CSL1 tmcsrh5.bit._CSL1 +#define TMCSRH5_CSL0 tmcsrh5.bit._CSL0 +#define TMCSRH5_MOD2 tmcsrh5.bit._MOD2 +#define TMCSRH5_MOD1 tmcsrh5.bit._MOD1 +#define TMCSRH5_CSL tmcsrh5.bitc._CSL +__IO_EXTERN TMCSRL5STR tmcsrl5; +#define TMCSRL5 tmcsrl5.byte +#define TMCSRL5_MOD0 tmcsrl5.bit._MOD0 +#define TMCSRL5_OUTL tmcsrl5.bit._OUTL +#define TMCSRL5_RELD tmcsrl5.bit._RELD +#define TMCSRL5_INTE tmcsrl5.bit._INTE +#define TMCSRL5_UF tmcsrl5.bit._UF +#define TMCSRL5_CNTE tmcsrl5.bit._CNTE +#define TMCSRL5_TRG tmcsrl5.bit._TRG +__IO_EXTERN TMRLR6STR tmrlr6; /* Reload Timer 6 */ +#define TMRLR6 tmrlr6.word +#define TMRLR6_D15 tmrlr6.bit._D15 +#define TMRLR6_D14 tmrlr6.bit._D14 +#define TMRLR6_D13 tmrlr6.bit._D13 +#define TMRLR6_D12 tmrlr6.bit._D12 +#define TMRLR6_D11 tmrlr6.bit._D11 +#define TMRLR6_D10 tmrlr6.bit._D10 +#define TMRLR6_D9 tmrlr6.bit._D9 +#define TMRLR6_D8 tmrlr6.bit._D8 +#define TMRLR6_D7 tmrlr6.bit._D7 +#define TMRLR6_D6 tmrlr6.bit._D6 +#define TMRLR6_D5 tmrlr6.bit._D5 +#define TMRLR6_D4 tmrlr6.bit._D4 +#define TMRLR6_D3 tmrlr6.bit._D3 +#define TMRLR6_D2 tmrlr6.bit._D2 +#define TMRLR6_D1 tmrlr6.bit._D1 +#define TMRLR6_D0 tmrlr6.bit._D0 +__IO_EXTERN TMR6STR tmr6; +#define TMR6 tmr6.word +#define TMR6_D15 tmr6.bit._D15 +#define TMR6_D14 tmr6.bit._D14 +#define TMR6_D13 tmr6.bit._D13 +#define TMR6_D12 tmr6.bit._D12 +#define TMR6_D11 tmr6.bit._D11 +#define TMR6_D10 tmr6.bit._D10 +#define TMR6_D9 tmr6.bit._D9 +#define TMR6_D8 tmr6.bit._D8 +#define TMR6_D7 tmr6.bit._D7 +#define TMR6_D6 tmr6.bit._D6 +#define TMR6_D5 tmr6.bit._D5 +#define TMR6_D4 tmr6.bit._D4 +#define TMR6_D3 tmr6.bit._D3 +#define TMR6_D2 tmr6.bit._D2 +#define TMR6_D1 tmr6.bit._D1 +#define TMR6_D0 tmr6.bit._D0 +__IO_EXTERN TMCSR6STR tmcsr6; +#define TMCSR6 tmcsr6.word +#define TMCSR6_CSL2 tmcsr6.bit._CSL2 +#define TMCSR6_CSL1 tmcsr6.bit._CSL1 +#define TMCSR6_CSL0 tmcsr6.bit._CSL0 +#define TMCSR6_MOD2 tmcsr6.bit._MOD2 +#define TMCSR6_MOD1 tmcsr6.bit._MOD1 +#define TMCSR6_MOD0 tmcsr6.bit._MOD0 +#define TMCSR6_OUTL tmcsr6.bit._OUTL +#define TMCSR6_RELD tmcsr6.bit._RELD +#define TMCSR6_INTE tmcsr6.bit._INTE +#define TMCSR6_UF tmcsr6.bit._UF +#define TMCSR6_CNTE tmcsr6.bit._CNTE +#define TMCSR6_TRG tmcsr6.bit._TRG +#define TMCSR6_CSL tmcsr6.bitc._CSL +#define TMCSR6_MOD tmcsr6.bitc._MOD +__IO_EXTERN TMCSRH6STR tmcsrh6; +#define TMCSRH6 tmcsrh6.byte +#define TMCSRH6_CSL2 tmcsrh6.bit._CSL2 +#define TMCSRH6_CSL1 tmcsrh6.bit._CSL1 +#define TMCSRH6_CSL0 tmcsrh6.bit._CSL0 +#define TMCSRH6_MOD2 tmcsrh6.bit._MOD2 +#define TMCSRH6_MOD1 tmcsrh6.bit._MOD1 +#define TMCSRH6_CSL tmcsrh6.bitc._CSL +__IO_EXTERN TMCSRL6STR tmcsrl6; +#define TMCSRL6 tmcsrl6.byte +#define TMCSRL6_MOD0 tmcsrl6.bit._MOD0 +#define TMCSRL6_OUTL tmcsrl6.bit._OUTL +#define TMCSRL6_RELD tmcsrl6.bit._RELD +#define TMCSRL6_INTE tmcsrl6.bit._INTE +#define TMCSRL6_UF tmcsrl6.bit._UF +#define TMCSRL6_CNTE tmcsrl6.bit._CNTE +#define TMCSRL6_TRG tmcsrl6.bit._TRG +__IO_EXTERN TMRLR7STR tmrlr7; /* Reload Timer 7 */ +#define TMRLR7 tmrlr7.word +#define TMRLR7_D15 tmrlr7.bit._D15 +#define TMRLR7_D14 tmrlr7.bit._D14 +#define TMRLR7_D13 tmrlr7.bit._D13 +#define TMRLR7_D12 tmrlr7.bit._D12 +#define TMRLR7_D11 tmrlr7.bit._D11 +#define TMRLR7_D10 tmrlr7.bit._D10 +#define TMRLR7_D9 tmrlr7.bit._D9 +#define TMRLR7_D8 tmrlr7.bit._D8 +#define TMRLR7_D7 tmrlr7.bit._D7 +#define TMRLR7_D6 tmrlr7.bit._D6 +#define TMRLR7_D5 tmrlr7.bit._D5 +#define TMRLR7_D4 tmrlr7.bit._D4 +#define TMRLR7_D3 tmrlr7.bit._D3 +#define TMRLR7_D2 tmrlr7.bit._D2 +#define TMRLR7_D1 tmrlr7.bit._D1 +#define TMRLR7_D0 tmrlr7.bit._D0 +__IO_EXTERN TMR7STR tmr7; +#define TMR7 tmr7.word +#define TMR7_D15 tmr7.bit._D15 +#define TMR7_D14 tmr7.bit._D14 +#define TMR7_D13 tmr7.bit._D13 +#define TMR7_D12 tmr7.bit._D12 +#define TMR7_D11 tmr7.bit._D11 +#define TMR7_D10 tmr7.bit._D10 +#define TMR7_D9 tmr7.bit._D9 +#define TMR7_D8 tmr7.bit._D8 +#define TMR7_D7 tmr7.bit._D7 +#define TMR7_D6 tmr7.bit._D6 +#define TMR7_D5 tmr7.bit._D5 +#define TMR7_D4 tmr7.bit._D4 +#define TMR7_D3 tmr7.bit._D3 +#define TMR7_D2 tmr7.bit._D2 +#define TMR7_D1 tmr7.bit._D1 +#define TMR7_D0 tmr7.bit._D0 +__IO_EXTERN TMCSR7STR tmcsr7; +#define TMCSR7 tmcsr7.word +#define TMCSR7_CSL2 tmcsr7.bit._CSL2 +#define TMCSR7_CSL1 tmcsr7.bit._CSL1 +#define TMCSR7_CSL0 tmcsr7.bit._CSL0 +#define TMCSR7_MOD2 tmcsr7.bit._MOD2 +#define TMCSR7_MOD1 tmcsr7.bit._MOD1 +#define TMCSR7_MOD0 tmcsr7.bit._MOD0 +#define TMCSR7_OUTL tmcsr7.bit._OUTL +#define TMCSR7_RELD tmcsr7.bit._RELD +#define TMCSR7_INTE tmcsr7.bit._INTE +#define TMCSR7_UF tmcsr7.bit._UF +#define TMCSR7_CNTE tmcsr7.bit._CNTE +#define TMCSR7_TRG tmcsr7.bit._TRG +#define TMCSR7_CSL tmcsr7.bitc._CSL +#define TMCSR7_MOD tmcsr7.bitc._MOD +__IO_EXTERN TMCSRH7STR tmcsrh7; +#define TMCSRH7 tmcsrh7.byte +#define TMCSRH7_CSL2 tmcsrh7.bit._CSL2 +#define TMCSRH7_CSL1 tmcsrh7.bit._CSL1 +#define TMCSRH7_CSL0 tmcsrh7.bit._CSL0 +#define TMCSRH7_MOD2 tmcsrh7.bit._MOD2 +#define TMCSRH7_MOD1 tmcsrh7.bit._MOD1 +#define TMCSRH7_CSL tmcsrh7.bitc._CSL +__IO_EXTERN TMCSRL7STR tmcsrl7; +#define TMCSRL7 tmcsrl7.byte +#define TMCSRL7_MOD0 tmcsrl7.bit._MOD0 +#define TMCSRL7_OUTL tmcsrl7.bit._OUTL +#define TMCSRL7_RELD tmcsrl7.bit._RELD +#define TMCSRL7_INTE tmcsrl7.bit._INTE +#define TMCSRL7_UF tmcsrl7.bit._UF +#define TMCSRL7_CNTE tmcsrl7.bit._CNTE +#define TMCSRL7_TRG tmcsrl7.bit._TRG +__IO_EXTERN TCDT0STR tcdt0; /* Free Running Timer0 */ +#define TCDT0 tcdt0.word +#define TCDT0_T15 tcdt0.bit._T15 +#define TCDT0_T14 tcdt0.bit._T14 +#define TCDT0_T13 tcdt0.bit._T13 +#define TCDT0_T12 tcdt0.bit._T12 +#define TCDT0_T11 tcdt0.bit._T11 +#define TCDT0_T10 tcdt0.bit._T10 +#define TCDT0_T9 tcdt0.bit._T9 +#define TCDT0_T8 tcdt0.bit._T8 +#define TCDT0_T7 tcdt0.bit._T7 +#define TCDT0_T6 tcdt0.bit._T6 +#define TCDT0_T5 tcdt0.bit._T5 +#define TCDT0_T4 tcdt0.bit._T4 +#define TCDT0_T3 tcdt0.bit._T3 +#define TCDT0_T2 tcdt0.bit._T2 +#define TCDT0_T1 tcdt0.bit._T1 +#define TCDT0_T0 tcdt0.bit._T0 +__IO_EXTERN TCCS0STR tccs0; +#define TCCS0 tccs0.byte +#define TCCS0_ECLK tccs0.bit._ECLK +#define TCCS0_IVF tccs0.bit._IVF +#define TCCS0_IVFE tccs0.bit._IVFE +#define TCCS0_STOP tccs0.bit._STOP +#define TCCS0_MODE tccs0.bit._MODE +#define TCCS0_CLR tccs0.bit._CLR +#define TCCS0_CLK1 tccs0.bit._CLK1 +#define TCCS0_CLK0 tccs0.bit._CLK0 +#define TCCS0_CLK tccs0.bitc._CLK +__IO_EXTERN TCDT1STR tcdt1; /* Free Running Timer1 */ +#define TCDT1 tcdt1.word +#define TCDT1_T15 tcdt1.bit._T15 +#define TCDT1_T14 tcdt1.bit._T14 +#define TCDT1_T13 tcdt1.bit._T13 +#define TCDT1_T12 tcdt1.bit._T12 +#define TCDT1_T11 tcdt1.bit._T11 +#define TCDT1_T10 tcdt1.bit._T10 +#define TCDT1_T9 tcdt1.bit._T9 +#define TCDT1_T8 tcdt1.bit._T8 +#define TCDT1_T7 tcdt1.bit._T7 +#define TCDT1_T6 tcdt1.bit._T6 +#define TCDT1_T5 tcdt1.bit._T5 +#define TCDT1_T4 tcdt1.bit._T4 +#define TCDT1_T3 tcdt1.bit._T3 +#define TCDT1_T2 tcdt1.bit._T2 +#define TCDT1_T1 tcdt1.bit._T1 +#define TCDT1_T0 tcdt1.bit._T0 +__IO_EXTERN TCCS1STR tccs1; +#define TCCS1 tccs1.byte +#define TCCS1_ECLK tccs1.bit._ECLK +#define TCCS1_IVF tccs1.bit._IVF +#define TCCS1_IVFE tccs1.bit._IVFE +#define TCCS1_STOP tccs1.bit._STOP +#define TCCS1_MODE tccs1.bit._MODE +#define TCCS1_CLR tccs1.bit._CLR +#define TCCS1_CLK1 tccs1.bit._CLK1 +#define TCCS1_CLK0 tccs1.bit._CLK0 +#define TCCS1_CLK tccs1.bitc._CLK +__IO_EXTERN TCDT2STR tcdt2; /* Free Running Timer2 */ +#define TCDT2 tcdt2.word +#define TCDT2_T15 tcdt2.bit._T15 +#define TCDT2_T14 tcdt2.bit._T14 +#define TCDT2_T13 tcdt2.bit._T13 +#define TCDT2_T12 tcdt2.bit._T12 +#define TCDT2_T11 tcdt2.bit._T11 +#define TCDT2_T10 tcdt2.bit._T10 +#define TCDT2_T9 tcdt2.bit._T9 +#define TCDT2_T8 tcdt2.bit._T8 +#define TCDT2_T7 tcdt2.bit._T7 +#define TCDT2_T6 tcdt2.bit._T6 +#define TCDT2_T5 tcdt2.bit._T5 +#define TCDT2_T4 tcdt2.bit._T4 +#define TCDT2_T3 tcdt2.bit._T3 +#define TCDT2_T2 tcdt2.bit._T2 +#define TCDT2_T1 tcdt2.bit._T1 +#define TCDT2_T0 tcdt2.bit._T0 +__IO_EXTERN TCCS2STR tccs2; +#define TCCS2 tccs2.byte +#define TCCS2_ECLK tccs2.bit._ECLK +#define TCCS2_IVF tccs2.bit._IVF +#define TCCS2_IVFE tccs2.bit._IVFE +#define TCCS2_STOP tccs2.bit._STOP +#define TCCS2_MODE tccs2.bit._MODE +#define TCCS2_CLR tccs2.bit._CLR +#define TCCS2_CLK1 tccs2.bit._CLK1 +#define TCCS2_CLK0 tccs2.bit._CLK0 +#define TCCS2_CLK tccs2.bitc._CLK +__IO_EXTERN TCDT3STR tcdt3; /* Free Running Timer3 */ +#define TCDT3 tcdt3.word +#define TCDT3_T15 tcdt3.bit._T15 +#define TCDT3_T14 tcdt3.bit._T14 +#define TCDT3_T13 tcdt3.bit._T13 +#define TCDT3_T12 tcdt3.bit._T12 +#define TCDT3_T11 tcdt3.bit._T11 +#define TCDT3_T10 tcdt3.bit._T10 +#define TCDT3_T9 tcdt3.bit._T9 +#define TCDT3_T8 tcdt3.bit._T8 +#define TCDT3_T7 tcdt3.bit._T7 +#define TCDT3_T6 tcdt3.bit._T6 +#define TCDT3_T5 tcdt3.bit._T5 +#define TCDT3_T4 tcdt3.bit._T4 +#define TCDT3_T3 tcdt3.bit._T3 +#define TCDT3_T2 tcdt3.bit._T2 +#define TCDT3_T1 tcdt3.bit._T1 +#define TCDT3_T0 tcdt3.bit._T0 +__IO_EXTERN TCCS3STR tccs3; +#define TCCS3 tccs3.byte +#define TCCS3_ECLK tccs3.bit._ECLK +#define TCCS3_IVF tccs3.bit._IVF +#define TCCS3_IVFE tccs3.bit._IVFE +#define TCCS3_STOP tccs3.bit._STOP +#define TCCS3_MODE tccs3.bit._MODE +#define TCCS3_CLR tccs3.bit._CLR +#define TCCS3_CLK1 tccs3.bit._CLK1 +#define TCCS3_CLK0 tccs3.bit._CLK0 +#define TCCS3_CLK tccs3.bitc._CLK +__IO_EXTERN DMACA0STR dmaca0; /* DMAC */ +#define DMACA0 dmaca0.lword +#define DMACA0_DENB dmaca0.bit._DENB +#define DMACA0_PAUS dmaca0.bit._PAUS +#define DMACA0_STRG dmaca0.bit._STRG +#define DMACA0_IS4 dmaca0.bit._IS4 +#define DMACA0_IS3 dmaca0.bit._IS3 +#define DMACA0_IS2 dmaca0.bit._IS2 +#define DMACA0_IS1 dmaca0.bit._IS1 +#define DMACA0_IS0 dmaca0.bit._IS0 +#define DMACA0_EIS3 dmaca0.bit._EIS3 +#define DMACA0_EIS2 dmaca0.bit._EIS2 +#define DMACA0_EIS1 dmaca0.bit._EIS1 +#define DMACA0_EIS0 dmaca0.bit._EIS0 +#define DMACA0_BLK3 dmaca0.bit._BLK3 +#define DMACA0_BLK2 dmaca0.bit._BLK2 +#define DMACA0_BLK1 dmaca0.bit._BLK1 +#define DMACA0_BLK0 dmaca0.bit._BLK0 +#define DMACA0_DTCF dmaca0.bit._DTCF +#define DMACA0_DTCE dmaca0.bit._DTCE +#define DMACA0_DTCD dmaca0.bit._DTCD +#define DMACA0_DTCC dmaca0.bit._DTCC +#define DMACA0_DTCB dmaca0.bit._DTCB +#define DMACA0_DTCA dmaca0.bit._DTCA +#define DMACA0_DTC9 dmaca0.bit._DTC9 +#define DMACA0_DTC8 dmaca0.bit._DTC8 +#define DMACA0_DTC7 dmaca0.bit._DTC7 +#define DMACA0_DTC6 dmaca0.bit._DTC6 +#define DMACA0_DTC5 dmaca0.bit._DTC5 +#define DMACA0_DTC4 dmaca0.bit._DTC4 +#define DMACA0_DTC3 dmaca0.bit._DTC3 +#define DMACA0_DTC2 dmaca0.bit._DTC2 +#define DMACA0_DTC1 dmaca0.bit._DTC1 +#define DMACA0_DTC0 dmaca0.bit._DTC0 +#define DMACA0_IS dmaca0.bitc._IS +#define DMACA0_EIS dmaca0.bitc._EIS +#define DMACA0_BLK dmaca0.bitc._BLK +#define DMACA0_DTC dmaca0.bitc._DTC +__IO_EXTERN DMACB0STR dmacb0; +#define DMACB0 dmacb0.lword +#define DMACB0_TYPE1 dmacb0.bit._TYPE1 +#define DMACB0_TYPE0 dmacb0.bit._TYPE0 +#define DMACB0_MOD1 dmacb0.bit._MOD1 +#define DMACB0_MOD0 dmacb0.bit._MOD0 +#define DMACB0_WS1 dmacb0.bit._WS1 +#define DMACB0_WS0 dmacb0.bit._WS0 +#define DMACB0_SADM dmacb0.bit._SADM +#define DMACB0_DADM dmacb0.bit._DADM +#define DMACB0_DTCR dmacb0.bit._DTCR +#define DMACB0_SADR dmacb0.bit._SADR +#define DMACB0_DADR dmacb0.bit._DADR +#define DMACB0_ERIE dmacb0.bit._ERIE +#define DMACB0_EDIE dmacb0.bit._EDIE +#define DMACB0_DSS2 dmacb0.bit._DSS2 +#define DMACB0_DSS1 dmacb0.bit._DSS1 +#define DMACB0_DSS0 dmacb0.bit._DSS0 +#define DMACB0_SASZ7 dmacb0.bit._SASZ7 +#define DMACB0_SASZ6 dmacb0.bit._SASZ6 +#define DMACB0_SASZ5 dmacb0.bit._SASZ5 +#define DMACB0_SASZ4 dmacb0.bit._SASZ4 +#define DMACB0_SASZ3 dmacb0.bit._SASZ3 +#define DMACB0_SASZ2 dmacb0.bit._SASZ2 +#define DMACB0_SASZ1 dmacb0.bit._SASZ1 +#define DMACB0_SASZ0 dmacb0.bit._SASZ0 +#define DMACB0_DASZ7 dmacb0.bit._DASZ7 +#define DMACB0_DASZ6 dmacb0.bit._DASZ6 +#define DMACB0_DASZ5 dmacb0.bit._DASZ5 +#define DMACB0_DASZ4 dmacb0.bit._DASZ4 +#define DMACB0_DASZ3 dmacb0.bit._DASZ3 +#define DMACB0_DASZ2 dmacb0.bit._DASZ2 +#define DMACB0_DASZ1 dmacb0.bit._DASZ1 +#define DMACB0_DASZ0 dmacb0.bit._DASZ0 +#define DMACB0_TYPE dmacb0.bitc._TYPE +#define DMACB0_MOD dmacb0.bitc._MOD +#define DMACB0_WS dmacb0.bitc._WS +#define DMACB0_DSS dmacb0.bitc._DSS +#define DMACB0_SASZ dmacb0.bitc._SASZ +#define DMACB0_DASZ dmacb0.bitc._DASZ +__IO_EXTERN DMACA1STR dmaca1; +#define DMACA1 dmaca1.lword +#define DMACA1_DENB dmaca1.bit._DENB +#define DMACA1_PAUS dmaca1.bit._PAUS +#define DMACA1_STRG dmaca1.bit._STRG +#define DMACA1_IS4 dmaca1.bit._IS4 +#define DMACA1_IS3 dmaca1.bit._IS3 +#define DMACA1_IS2 dmaca1.bit._IS2 +#define DMACA1_IS1 dmaca1.bit._IS1 +#define DMACA1_IS0 dmaca1.bit._IS0 +#define DMACA1_EIS3 dmaca1.bit._EIS3 +#define DMACA1_EIS2 dmaca1.bit._EIS2 +#define DMACA1_EIS1 dmaca1.bit._EIS1 +#define DMACA1_EIS0 dmaca1.bit._EIS0 +#define DMACA1_BLK3 dmaca1.bit._BLK3 +#define DMACA1_BLK2 dmaca1.bit._BLK2 +#define DMACA1_BLK1 dmaca1.bit._BLK1 +#define DMACA1_BLK0 dmaca1.bit._BLK0 +#define DMACA1_DTCF dmaca1.bit._DTCF +#define DMACA1_DTCE dmaca1.bit._DTCE +#define DMACA1_DTCD dmaca1.bit._DTCD +#define DMACA1_DTCC dmaca1.bit._DTCC +#define DMACA1_DTCB dmaca1.bit._DTCB +#define DMACA1_DTCA dmaca1.bit._DTCA +#define DMACA1_DTC9 dmaca1.bit._DTC9 +#define DMACA1_DTC8 dmaca1.bit._DTC8 +#define DMACA1_DTC7 dmaca1.bit._DTC7 +#define DMACA1_DTC6 dmaca1.bit._DTC6 +#define DMACA1_DTC5 dmaca1.bit._DTC5 +#define DMACA1_DTC4 dmaca1.bit._DTC4 +#define DMACA1_DTC3 dmaca1.bit._DTC3 +#define DMACA1_DTC2 dmaca1.bit._DTC2 +#define DMACA1_DTC1 dmaca1.bit._DTC1 +#define DMACA1_DTC0 dmaca1.bit._DTC0 +#define DMACA1_IS dmaca1.bitc._IS +#define DMACA1_EIS dmaca1.bitc._EIS +#define DMACA1_BLK dmaca1.bitc._BLK +#define DMACA1_DTC dmaca1.bitc._DTC +__IO_EXTERN DMACB1STR dmacb1; +#define DMACB1 dmacb1.lword +#define DMACB1_TYPE1 dmacb1.bit._TYPE1 +#define DMACB1_TYPE0 dmacb1.bit._TYPE0 +#define DMACB1_MOD1 dmacb1.bit._MOD1 +#define DMACB1_MOD0 dmacb1.bit._MOD0 +#define DMACB1_WS1 dmacb1.bit._WS1 +#define DMACB1_WS0 dmacb1.bit._WS0 +#define DMACB1_SADM dmacb1.bit._SADM +#define DMACB1_DADM dmacb1.bit._DADM +#define DMACB1_DTCR dmacb1.bit._DTCR +#define DMACB1_SADR dmacb1.bit._SADR +#define DMACB1_DADR dmacb1.bit._DADR +#define DMACB1_ERIE dmacb1.bit._ERIE +#define DMACB1_EDIE dmacb1.bit._EDIE +#define DMACB1_DSS2 dmacb1.bit._DSS2 +#define DMACB1_DSS1 dmacb1.bit._DSS1 +#define DMACB1_DSS0 dmacb1.bit._DSS0 +#define DMACB1_SASZ7 dmacb1.bit._SASZ7 +#define DMACB1_SASZ6 dmacb1.bit._SASZ6 +#define DMACB1_SASZ5 dmacb1.bit._SASZ5 +#define DMACB1_SASZ4 dmacb1.bit._SASZ4 +#define DMACB1_SASZ3 dmacb1.bit._SASZ3 +#define DMACB1_SASZ2 dmacb1.bit._SASZ2 +#define DMACB1_SASZ1 dmacb1.bit._SASZ1 +#define DMACB1_SASZ0 dmacb1.bit._SASZ0 +#define DMACB1_DASZ7 dmacb1.bit._DASZ7 +#define DMACB1_DASZ6 dmacb1.bit._DASZ6 +#define DMACB1_DASZ5 dmacb1.bit._DASZ5 +#define DMACB1_DASZ4 dmacb1.bit._DASZ4 +#define DMACB1_DASZ3 dmacb1.bit._DASZ3 +#define DMACB1_DASZ2 dmacb1.bit._DASZ2 +#define DMACB1_DASZ1 dmacb1.bit._DASZ1 +#define DMACB1_DASZ0 dmacb1.bit._DASZ0 +#define DMACB1_TYPE dmacb1.bitc._TYPE +#define DMACB1_MOD dmacb1.bitc._MOD +#define DMACB1_WS dmacb1.bitc._WS +#define DMACB1_DSS dmacb1.bitc._DSS +#define DMACB1_SASZ dmacb1.bitc._SASZ +#define DMACB1_DASZ dmacb1.bitc._DASZ +__IO_EXTERN DMACA2STR dmaca2; +#define DMACA2 dmaca2.lword +#define DMACA2_DENB dmaca2.bit._DENB +#define DMACA2_PAUS dmaca2.bit._PAUS +#define DMACA2_STRG dmaca2.bit._STRG +#define DMACA2_IS4 dmaca2.bit._IS4 +#define DMACA2_IS3 dmaca2.bit._IS3 +#define DMACA2_IS2 dmaca2.bit._IS2 +#define DMACA2_IS1 dmaca2.bit._IS1 +#define DMACA2_IS0 dmaca2.bit._IS0 +#define DMACA2_EIS3 dmaca2.bit._EIS3 +#define DMACA2_EIS2 dmaca2.bit._EIS2 +#define DMACA2_EIS1 dmaca2.bit._EIS1 +#define DMACA2_EIS0 dmaca2.bit._EIS0 +#define DMACA2_BLK3 dmaca2.bit._BLK3 +#define DMACA2_BLK2 dmaca2.bit._BLK2 +#define DMACA2_BLK1 dmaca2.bit._BLK1 +#define DMACA2_BLK0 dmaca2.bit._BLK0 +#define DMACA2_DTCF dmaca2.bit._DTCF +#define DMACA2_DTCE dmaca2.bit._DTCE +#define DMACA2_DTCD dmaca2.bit._DTCD +#define DMACA2_DTCC dmaca2.bit._DTCC +#define DMACA2_DTCB dmaca2.bit._DTCB +#define DMACA2_DTCA dmaca2.bit._DTCA +#define DMACA2_DTC9 dmaca2.bit._DTC9 +#define DMACA2_DTC8 dmaca2.bit._DTC8 +#define DMACA2_DTC7 dmaca2.bit._DTC7 +#define DMACA2_DTC6 dmaca2.bit._DTC6 +#define DMACA2_DTC5 dmaca2.bit._DTC5 +#define DMACA2_DTC4 dmaca2.bit._DTC4 +#define DMACA2_DTC3 dmaca2.bit._DTC3 +#define DMACA2_DTC2 dmaca2.bit._DTC2 +#define DMACA2_DTC1 dmaca2.bit._DTC1 +#define DMACA2_DTC0 dmaca2.bit._DTC0 +#define DMACA2_IS dmaca2.bitc._IS +#define DMACA2_EIS dmaca2.bitc._EIS +#define DMACA2_BLK dmaca2.bitc._BLK +#define DMACA2_DTC dmaca2.bitc._DTC +__IO_EXTERN DMACB2STR dmacb2; +#define DMACB2 dmacb2.lword +#define DMACB2_TYPE1 dmacb2.bit._TYPE1 +#define DMACB2_TYPE0 dmacb2.bit._TYPE0 +#define DMACB2_MOD1 dmacb2.bit._MOD1 +#define DMACB2_MOD0 dmacb2.bit._MOD0 +#define DMACB2_WS1 dmacb2.bit._WS1 +#define DMACB2_WS0 dmacb2.bit._WS0 +#define DMACB2_SADM dmacb2.bit._SADM +#define DMACB2_DADM dmacb2.bit._DADM +#define DMACB2_DTCR dmacb2.bit._DTCR +#define DMACB2_SADR dmacb2.bit._SADR +#define DMACB2_DADR dmacb2.bit._DADR +#define DMACB2_ERIE dmacb2.bit._ERIE +#define DMACB2_EDIE dmacb2.bit._EDIE +#define DMACB2_DSS2 dmacb2.bit._DSS2 +#define DMACB2_DSS1 dmacb2.bit._DSS1 +#define DMACB2_DSS0 dmacb2.bit._DSS0 +#define DMACB2_SASZ7 dmacb2.bit._SASZ7 +#define DMACB2_SASZ6 dmacb2.bit._SASZ6 +#define DMACB2_SASZ5 dmacb2.bit._SASZ5 +#define DMACB2_SASZ4 dmacb2.bit._SASZ4 +#define DMACB2_SASZ3 dmacb2.bit._SASZ3 +#define DMACB2_SASZ2 dmacb2.bit._SASZ2 +#define DMACB2_SASZ1 dmacb2.bit._SASZ1 +#define DMACB2_SASZ0 dmacb2.bit._SASZ0 +#define DMACB2_DASZ7 dmacb2.bit._DASZ7 +#define DMACB2_DASZ6 dmacb2.bit._DASZ6 +#define DMACB2_DASZ5 dmacb2.bit._DASZ5 +#define DMACB2_DASZ4 dmacb2.bit._DASZ4 +#define DMACB2_DASZ3 dmacb2.bit._DASZ3 +#define DMACB2_DASZ2 dmacb2.bit._DASZ2 +#define DMACB2_DASZ1 dmacb2.bit._DASZ1 +#define DMACB2_DASZ0 dmacb2.bit._DASZ0 +#define DMACB2_TYPE dmacb2.bitc._TYPE +#define DMACB2_MOD dmacb2.bitc._MOD +#define DMACB2_WS dmacb2.bitc._WS +#define DMACB2_DSS dmacb2.bitc._DSS +#define DMACB2_SASZ dmacb2.bitc._SASZ +#define DMACB2_DASZ dmacb2.bitc._DASZ +__IO_EXTERN DMACA3STR dmaca3; +#define DMACA3 dmaca3.lword +#define DMACA3_DENB dmaca3.bit._DENB +#define DMACA3_PAUS dmaca3.bit._PAUS +#define DMACA3_STRG dmaca3.bit._STRG +#define DMACA3_IS4 dmaca3.bit._IS4 +#define DMACA3_IS3 dmaca3.bit._IS3 +#define DMACA3_IS2 dmaca3.bit._IS2 +#define DMACA3_IS1 dmaca3.bit._IS1 +#define DMACA3_IS0 dmaca3.bit._IS0 +#define DMACA3_EIS3 dmaca3.bit._EIS3 +#define DMACA3_EIS2 dmaca3.bit._EIS2 +#define DMACA3_EIS1 dmaca3.bit._EIS1 +#define DMACA3_EIS0 dmaca3.bit._EIS0 +#define DMACA3_BLK3 dmaca3.bit._BLK3 +#define DMACA3_BLK2 dmaca3.bit._BLK2 +#define DMACA3_BLK1 dmaca3.bit._BLK1 +#define DMACA3_BLK0 dmaca3.bit._BLK0 +#define DMACA3_DTCF dmaca3.bit._DTCF +#define DMACA3_DTCE dmaca3.bit._DTCE +#define DMACA3_DTCD dmaca3.bit._DTCD +#define DMACA3_DTCC dmaca3.bit._DTCC +#define DMACA3_DTCB dmaca3.bit._DTCB +#define DMACA3_DTCA dmaca3.bit._DTCA +#define DMACA3_DTC9 dmaca3.bit._DTC9 +#define DMACA3_DTC8 dmaca3.bit._DTC8 +#define DMACA3_DTC7 dmaca3.bit._DTC7 +#define DMACA3_DTC6 dmaca3.bit._DTC6 +#define DMACA3_DTC5 dmaca3.bit._DTC5 +#define DMACA3_DTC4 dmaca3.bit._DTC4 +#define DMACA3_DTC3 dmaca3.bit._DTC3 +#define DMACA3_DTC2 dmaca3.bit._DTC2 +#define DMACA3_DTC1 dmaca3.bit._DTC1 +#define DMACA3_DTC0 dmaca3.bit._DTC0 +#define DMACA3_IS dmaca3.bitc._IS +#define DMACA3_EIS dmaca3.bitc._EIS +#define DMACA3_BLK dmaca3.bitc._BLK +#define DMACA3_DTC dmaca3.bitc._DTC +__IO_EXTERN DMACB3STR dmacb3; +#define DMACB3 dmacb3.lword +#define DMACB3_TYPE1 dmacb3.bit._TYPE1 +#define DMACB3_TYPE0 dmacb3.bit._TYPE0 +#define DMACB3_MOD1 dmacb3.bit._MOD1 +#define DMACB3_MOD0 dmacb3.bit._MOD0 +#define DMACB3_WS1 dmacb3.bit._WS1 +#define DMACB3_WS0 dmacb3.bit._WS0 +#define DMACB3_SADM dmacb3.bit._SADM +#define DMACB3_DADM dmacb3.bit._DADM +#define DMACB3_DTCR dmacb3.bit._DTCR +#define DMACB3_SADR dmacb3.bit._SADR +#define DMACB3_DADR dmacb3.bit._DADR +#define DMACB3_ERIE dmacb3.bit._ERIE +#define DMACB3_EDIE dmacb3.bit._EDIE +#define DMACB3_DSS2 dmacb3.bit._DSS2 +#define DMACB3_DSS1 dmacb3.bit._DSS1 +#define DMACB3_DSS0 dmacb3.bit._DSS0 +#define DMACB3_SASZ7 dmacb3.bit._SASZ7 +#define DMACB3_SASZ6 dmacb3.bit._SASZ6 +#define DMACB3_SASZ5 dmacb3.bit._SASZ5 +#define DMACB3_SASZ4 dmacb3.bit._SASZ4 +#define DMACB3_SASZ3 dmacb3.bit._SASZ3 +#define DMACB3_SASZ2 dmacb3.bit._SASZ2 +#define DMACB3_SASZ1 dmacb3.bit._SASZ1 +#define DMACB3_SASZ0 dmacb3.bit._SASZ0 +#define DMACB3_DASZ7 dmacb3.bit._DASZ7 +#define DMACB3_DASZ6 dmacb3.bit._DASZ6 +#define DMACB3_DASZ5 dmacb3.bit._DASZ5 +#define DMACB3_DASZ4 dmacb3.bit._DASZ4 +#define DMACB3_DASZ3 dmacb3.bit._DASZ3 +#define DMACB3_DASZ2 dmacb3.bit._DASZ2 +#define DMACB3_DASZ1 dmacb3.bit._DASZ1 +#define DMACB3_DASZ0 dmacb3.bit._DASZ0 +#define DMACB3_TYPE dmacb3.bitc._TYPE +#define DMACB3_MOD dmacb3.bitc._MOD +#define DMACB3_WS dmacb3.bitc._WS +#define DMACB3_DSS dmacb3.bitc._DSS +#define DMACB3_SASZ dmacb3.bitc._SASZ +#define DMACB3_DASZ dmacb3.bitc._DASZ +__IO_EXTERN DMACA4STR dmaca4; +#define DMACA4 dmaca4.lword +#define DMACA4_DENB dmaca4.bit._DENB +#define DMACA4_PAUS dmaca4.bit._PAUS +#define DMACA4_STRG dmaca4.bit._STRG +#define DMACA4_IS4 dmaca4.bit._IS4 +#define DMACA4_IS3 dmaca4.bit._IS3 +#define DMACA4_IS2 dmaca4.bit._IS2 +#define DMACA4_IS1 dmaca4.bit._IS1 +#define DMACA4_IS0 dmaca4.bit._IS0 +#define DMACA4_EIS3 dmaca4.bit._EIS3 +#define DMACA4_EIS2 dmaca4.bit._EIS2 +#define DMACA4_EIS1 dmaca4.bit._EIS1 +#define DMACA4_EIS0 dmaca4.bit._EIS0 +#define DMACA4_BLK3 dmaca4.bit._BLK3 +#define DMACA4_BLK2 dmaca4.bit._BLK2 +#define DMACA4_BLK1 dmaca4.bit._BLK1 +#define DMACA4_BLK0 dmaca4.bit._BLK0 +#define DMACA4_DTCF dmaca4.bit._DTCF +#define DMACA4_DTCE dmaca4.bit._DTCE +#define DMACA4_DTCD dmaca4.bit._DTCD +#define DMACA4_DTCC dmaca4.bit._DTCC +#define DMACA4_DTCB dmaca4.bit._DTCB +#define DMACA4_DTCA dmaca4.bit._DTCA +#define DMACA4_DTC9 dmaca4.bit._DTC9 +#define DMACA4_DTC8 dmaca4.bit._DTC8 +#define DMACA4_DTC7 dmaca4.bit._DTC7 +#define DMACA4_DTC6 dmaca4.bit._DTC6 +#define DMACA4_DTC5 dmaca4.bit._DTC5 +#define DMACA4_DTC4 dmaca4.bit._DTC4 +#define DMACA4_DTC3 dmaca4.bit._DTC3 +#define DMACA4_DTC2 dmaca4.bit._DTC2 +#define DMACA4_DTC1 dmaca4.bit._DTC1 +#define DMACA4_DTC0 dmaca4.bit._DTC0 +#define DMACA4_IS dmaca4.bitc._IS +#define DMACA4_EIS dmaca4.bitc._EIS +#define DMACA4_BLK dmaca4.bitc._BLK +#define DMACA4_DTC dmaca4.bitc._DTC +__IO_EXTERN DMACB4STR dmacb4; +#define DMACB4 dmacb4.lword +#define DMACB4_TYPE1 dmacb4.bit._TYPE1 +#define DMACB4_TYPE0 dmacb4.bit._TYPE0 +#define DMACB4_MOD1 dmacb4.bit._MOD1 +#define DMACB4_MOD0 dmacb4.bit._MOD0 +#define DMACB4_WS1 dmacb4.bit._WS1 +#define DMACB4_WS0 dmacb4.bit._WS0 +#define DMACB4_SADM dmacb4.bit._SADM +#define DMACB4_DADM dmacb4.bit._DADM +#define DMACB4_DTCR dmacb4.bit._DTCR +#define DMACB4_SADR dmacb4.bit._SADR +#define DMACB4_DADR dmacb4.bit._DADR +#define DMACB4_ERIE dmacb4.bit._ERIE +#define DMACB4_EDIE dmacb4.bit._EDIE +#define DMACB4_DSS2 dmacb4.bit._DSS2 +#define DMACB4_DSS1 dmacb4.bit._DSS1 +#define DMACB4_DSS0 dmacb4.bit._DSS0 +#define DMACB4_SASZ7 dmacb4.bit._SASZ7 +#define DMACB4_SASZ6 dmacb4.bit._SASZ6 +#define DMACB4_SASZ5 dmacb4.bit._SASZ5 +#define DMACB4_SASZ4 dmacb4.bit._SASZ4 +#define DMACB4_SASZ3 dmacb4.bit._SASZ3 +#define DMACB4_SASZ2 dmacb4.bit._SASZ2 +#define DMACB4_SASZ1 dmacb4.bit._SASZ1 +#define DMACB4_SASZ0 dmacb4.bit._SASZ0 +#define DMACB4_DASZ7 dmacb4.bit._DASZ7 +#define DMACB4_DASZ6 dmacb4.bit._DASZ6 +#define DMACB4_DASZ5 dmacb4.bit._DASZ5 +#define DMACB4_DASZ4 dmacb4.bit._DASZ4 +#define DMACB4_DASZ3 dmacb4.bit._DASZ3 +#define DMACB4_DASZ2 dmacb4.bit._DASZ2 +#define DMACB4_DASZ1 dmacb4.bit._DASZ1 +#define DMACB4_DASZ0 dmacb4.bit._DASZ0 +#define DMACB4_TYPE dmacb4.bitc._TYPE +#define DMACB4_MOD dmacb4.bitc._MOD +#define DMACB4_WS dmacb4.bitc._WS +#define DMACB4_DSS dmacb4.bitc._DSS +#define DMACB4_SASZ dmacb4.bitc._SASZ +#define DMACB4_DASZ dmacb4.bitc._DASZ +__IO_EXTERN DMACRSTR dmacr; +#define DMACR dmacr.byte +#define DMACR_DMAE dmacr.bit._DMAE +#define DMACR_PM01 dmacr.bit._PM01 +#define DMACR_DMAH3 dmacr.bit._DMAH3 +#define DMACR_DMAH2 dmacr.bit._DMAH2 +#define DMACR_DMAH1 dmacr.bit._DMAH1 +#define DMACR_DMAH0 dmacr.bit._DMAH0 +#define DMACR_DMAH dmacr.bitc._DMAH +/* include : INC460_DMAC.INC */ +/*-------------------------------------------------------------------*/ +/* INC460.DMAC : Old bit name of DMACx */ + +/* alias macro definition for DMACx */ +#define DMACB0_MD dmacb0.bitc._MOD +#define DMACB0_MD1 dmacb0.bit._MOD1 +#define DMACB0_MD0 dmacb0.bit._MOD0 +#define DMACB1_MD dmacb1.bitc._MOD +#define DMACB1_MD1 dmacb1.bit._MOD1 +#define DMACB1_MD0 dmacb1.bit._MOD0 +#define DMACB2_MD dmacb2.bitc._MOD +#define DMACB2_MD1 dmacb2.bit._MOD1 +#define DMACB2_MD0 dmacb2.bit._MOD0 +#define DMACB3_MD dmacb3.bitc._MOD +#define DMACB3_MD1 dmacb3.bit._MOD1 +#define DMACB3_MD0 dmacb3.bit._MOD0 +#define DMACB4_MD dmacb4.bitc._MOD +#define DMACB4_MD1 dmacb4.bit._MOD1 +#define DMACB4_MD0 dmacb4.bit._MOD0 +/*-------------------------------------------------------------------*/ +__IO_EXTERN ICS45STR ics45; /* Input Capture 4-7 */ +#define ICS45 ics45.byte +#define ICS45_ICP5 ics45.bit._ICP5 +#define ICS45_ICP4 ics45.bit._ICP4 +#define ICS45_ICE5 ics45.bit._ICE5 +#define ICS45_ICE4 ics45.bit._ICE4 +#define ICS45_EG51 ics45.bit._EG51 +#define ICS45_EG50 ics45.bit._EG50 +#define ICS45_EG41 ics45.bit._EG41 +#define ICS45_EG40 ics45.bit._EG40 +#define ICS45_EG5 ics45.bitc._EG5 +#define ICS45_EG4 ics45.bitc._EG4 +__IO_EXTERN ICS67STR ics67; +#define ICS67 ics67.byte +#define ICS67_ICP7 ics67.bit._ICP7 +#define ICS67_ICP6 ics67.bit._ICP6 +#define ICS67_ICE7 ics67.bit._ICE7 +#define ICS67_ICE6 ics67.bit._ICE6 +#define ICS67_EG71 ics67.bit._EG71 +#define ICS67_EG70 ics67.bit._EG70 +#define ICS67_EG61 ics67.bit._EG61 +#define ICS67_EG60 ics67.bit._EG60 +#define ICS67_EG7 ics67.bitc._EG7 +#define ICS67_EG6 ics67.bitc._EG6 +__IO_EXTERN IPCP4STR ipcp4; +#define IPCP4 ipcp4.word +#define IPCP4_CP15 ipcp4.bit._CP15 +#define IPCP4_CP14 ipcp4.bit._CP14 +#define IPCP4_CP13 ipcp4.bit._CP13 +#define IPCP4_CP12 ipcp4.bit._CP12 +#define IPCP4_CP11 ipcp4.bit._CP11 +#define IPCP4_CP10 ipcp4.bit._CP10 +#define IPCP4_CP9 ipcp4.bit._CP9 +#define IPCP4_CP8 ipcp4.bit._CP8 +#define IPCP4_CP7 ipcp4.bit._CP7 +#define IPCP4_CP6 ipcp4.bit._CP6 +#define IPCP4_CP5 ipcp4.bit._CP5 +#define IPCP4_CP4 ipcp4.bit._CP4 +#define IPCP4_CP3 ipcp4.bit._CP3 +#define IPCP4_CP2 ipcp4.bit._CP2 +#define IPCP4_CP1 ipcp4.bit._CP1 +#define IPCP4_CP0 ipcp4.bit._CP0 +__IO_EXTERN IPCP5STR ipcp5; +#define IPCP5 ipcp5.word +#define IPCP5_CP15 ipcp5.bit._CP15 +#define IPCP5_CP14 ipcp5.bit._CP14 +#define IPCP5_CP13 ipcp5.bit._CP13 +#define IPCP5_CP12 ipcp5.bit._CP12 +#define IPCP5_CP11 ipcp5.bit._CP11 +#define IPCP5_CP10 ipcp5.bit._CP10 +#define IPCP5_CP9 ipcp5.bit._CP9 +#define IPCP5_CP8 ipcp5.bit._CP8 +#define IPCP5_CP7 ipcp5.bit._CP7 +#define IPCP5_CP6 ipcp5.bit._CP6 +#define IPCP5_CP5 ipcp5.bit._CP5 +#define IPCP5_CP4 ipcp5.bit._CP4 +#define IPCP5_CP3 ipcp5.bit._CP3 +#define IPCP5_CP2 ipcp5.bit._CP2 +#define IPCP5_CP1 ipcp5.bit._CP1 +#define IPCP5_CP0 ipcp5.bit._CP0 +__IO_EXTERN IPCP6STR ipcp6; +#define IPCP6 ipcp6.word +#define IPCP6_CP15 ipcp6.bit._CP15 +#define IPCP6_CP14 ipcp6.bit._CP14 +#define IPCP6_CP13 ipcp6.bit._CP13 +#define IPCP6_CP12 ipcp6.bit._CP12 +#define IPCP6_CP11 ipcp6.bit._CP11 +#define IPCP6_CP10 ipcp6.bit._CP10 +#define IPCP6_CP9 ipcp6.bit._CP9 +#define IPCP6_CP8 ipcp6.bit._CP8 +#define IPCP6_CP7 ipcp6.bit._CP7 +#define IPCP6_CP6 ipcp6.bit._CP6 +#define IPCP6_CP5 ipcp6.bit._CP5 +#define IPCP6_CP4 ipcp6.bit._CP4 +#define IPCP6_CP3 ipcp6.bit._CP3 +#define IPCP6_CP2 ipcp6.bit._CP2 +#define IPCP6_CP1 ipcp6.bit._CP1 +#define IPCP6_CP0 ipcp6.bit._CP0 +__IO_EXTERN IPCP7STR ipcp7; +#define IPCP7 ipcp7.word +#define IPCP7_CP15 ipcp7.bit._CP15 +#define IPCP7_CP14 ipcp7.bit._CP14 +#define IPCP7_CP13 ipcp7.bit._CP13 +#define IPCP7_CP12 ipcp7.bit._CP12 +#define IPCP7_CP11 ipcp7.bit._CP11 +#define IPCP7_CP10 ipcp7.bit._CP10 +#define IPCP7_CP9 ipcp7.bit._CP9 +#define IPCP7_CP8 ipcp7.bit._CP8 +#define IPCP7_CP7 ipcp7.bit._CP7 +#define IPCP7_CP6 ipcp7.bit._CP6 +#define IPCP7_CP5 ipcp7.bit._CP5 +#define IPCP7_CP4 ipcp7.bit._CP4 +#define IPCP7_CP3 ipcp7.bit._CP3 +#define IPCP7_CP2 ipcp7.bit._CP2 +#define IPCP7_CP1 ipcp7.bit._CP1 +#define IPCP7_CP0 ipcp7.bit._CP0 +__IO_EXTERN TCDT4STR tcdt4; /* Free Running Timer4 */ +#define TCDT4 tcdt4.word +#define TCDT4_T15 tcdt4.bit._T15 +#define TCDT4_T14 tcdt4.bit._T14 +#define TCDT4_T13 tcdt4.bit._T13 +#define TCDT4_T12 tcdt4.bit._T12 +#define TCDT4_T11 tcdt4.bit._T11 +#define TCDT4_T10 tcdt4.bit._T10 +#define TCDT4_T9 tcdt4.bit._T9 +#define TCDT4_T8 tcdt4.bit._T8 +#define TCDT4_T7 tcdt4.bit._T7 +#define TCDT4_T6 tcdt4.bit._T6 +#define TCDT4_T5 tcdt4.bit._T5 +#define TCDT4_T4 tcdt4.bit._T4 +#define TCDT4_T3 tcdt4.bit._T3 +#define TCDT4_T2 tcdt4.bit._T2 +#define TCDT4_T1 tcdt4.bit._T1 +#define TCDT4_T0 tcdt4.bit._T0 +__IO_EXTERN TCCS4STR tccs4; +#define TCCS4 tccs4.byte +#define TCCS4_ECLK tccs4.bit._ECLK +#define TCCS4_IVF tccs4.bit._IVF +#define TCCS4_IVFE tccs4.bit._IVFE +#define TCCS4_STOP tccs4.bit._STOP +#define TCCS4_MODE tccs4.bit._MODE +#define TCCS4_CLR tccs4.bit._CLR +#define TCCS4_CLK1 tccs4.bit._CLK1 +#define TCCS4_CLK0 tccs4.bit._CLK0 +#define TCCS4_CLK tccs4.bitc._CLK +__IO_EXTERN TCDT5STR tcdt5; /* Free Running Timer5 */ +#define TCDT5 tcdt5.word +#define TCDT5_T15 tcdt5.bit._T15 +#define TCDT5_T14 tcdt5.bit._T14 +#define TCDT5_T13 tcdt5.bit._T13 +#define TCDT5_T12 tcdt5.bit._T12 +#define TCDT5_T11 tcdt5.bit._T11 +#define TCDT5_T10 tcdt5.bit._T10 +#define TCDT5_T9 tcdt5.bit._T9 +#define TCDT5_T8 tcdt5.bit._T8 +#define TCDT5_T7 tcdt5.bit._T7 +#define TCDT5_T6 tcdt5.bit._T6 +#define TCDT5_T5 tcdt5.bit._T5 +#define TCDT5_T4 tcdt5.bit._T4 +#define TCDT5_T3 tcdt5.bit._T3 +#define TCDT5_T2 tcdt5.bit._T2 +#define TCDT5_T1 tcdt5.bit._T1 +#define TCDT5_T0 tcdt5.bit._T0 +__IO_EXTERN TCCS5STR tccs5; +#define TCCS5 tccs5.byte +#define TCCS5_ECLK tccs5.bit._ECLK +#define TCCS5_IVF tccs5.bit._IVF +#define TCCS5_IVFE tccs5.bit._IVFE +#define TCCS5_STOP tccs5.bit._STOP +#define TCCS5_MODE tccs5.bit._MODE +#define TCCS5_CLR tccs5.bit._CLR +#define TCCS5_CLK1 tccs5.bit._CLK1 +#define TCCS5_CLK0 tccs5.bit._CLK0 +#define TCCS5_CLK tccs5.bitc._CLK +__IO_EXTERN TCDT6STR tcdt6; /* Free Running Timer6 */ +#define TCDT6 tcdt6.word +#define TCDT6_T15 tcdt6.bit._T15 +#define TCDT6_T14 tcdt6.bit._T14 +#define TCDT6_T13 tcdt6.bit._T13 +#define TCDT6_T12 tcdt6.bit._T12 +#define TCDT6_T11 tcdt6.bit._T11 +#define TCDT6_T10 tcdt6.bit._T10 +#define TCDT6_T9 tcdt6.bit._T9 +#define TCDT6_T8 tcdt6.bit._T8 +#define TCDT6_T7 tcdt6.bit._T7 +#define TCDT6_T6 tcdt6.bit._T6 +#define TCDT6_T5 tcdt6.bit._T5 +#define TCDT6_T4 tcdt6.bit._T4 +#define TCDT6_T3 tcdt6.bit._T3 +#define TCDT6_T2 tcdt6.bit._T2 +#define TCDT6_T1 tcdt6.bit._T1 +#define TCDT6_T0 tcdt6.bit._T0 +__IO_EXTERN TCCS6STR tccs6; +#define TCCS6 tccs6.byte +#define TCCS6_ECLK tccs6.bit._ECLK +#define TCCS6_IVF tccs6.bit._IVF +#define TCCS6_IVFE tccs6.bit._IVFE +#define TCCS6_STOP tccs6.bit._STOP +#define TCCS6_MODE tccs6.bit._MODE +#define TCCS6_CLR tccs6.bit._CLR +#define TCCS6_CLK1 tccs6.bit._CLK1 +#define TCCS6_CLK0 tccs6.bit._CLK0 +#define TCCS6_CLK tccs6.bitc._CLK +__IO_EXTERN TCDT7STR tcdt7; /* Free Running Timer7 */ +#define TCDT7 tcdt7.word +#define TCDT7_T15 tcdt7.bit._T15 +#define TCDT7_T14 tcdt7.bit._T14 +#define TCDT7_T13 tcdt7.bit._T13 +#define TCDT7_T12 tcdt7.bit._T12 +#define TCDT7_T11 tcdt7.bit._T11 +#define TCDT7_T10 tcdt7.bit._T10 +#define TCDT7_T9 tcdt7.bit._T9 +#define TCDT7_T8 tcdt7.bit._T8 +#define TCDT7_T7 tcdt7.bit._T7 +#define TCDT7_T6 tcdt7.bit._T6 +#define TCDT7_T5 tcdt7.bit._T5 +#define TCDT7_T4 tcdt7.bit._T4 +#define TCDT7_T3 tcdt7.bit._T3 +#define TCDT7_T2 tcdt7.bit._T2 +#define TCDT7_T1 tcdt7.bit._T1 +#define TCDT7_T0 tcdt7.bit._T0 +__IO_EXTERN TCCS7STR tccs7; +#define TCCS7 tccs7.byte +#define TCCS7_ECLK tccs7.bit._ECLK +#define TCCS7_IVF tccs7.bit._IVF +#define TCCS7_IVFE tccs7.bit._IVFE +#define TCCS7_STOP tccs7.bit._STOP +#define TCCS7_MODE tccs7.bit._MODE +#define TCCS7_CLR tccs7.bit._CLR +#define TCCS7_CLK1 tccs7.bit._CLK1 +#define TCCS7_CLK0 tccs7.bit._CLK0 +#define TCCS7_CLK tccs7.bitc._CLK +__IO_EXTERN UDRC10STR udrc10; /* Up/Down Counter 0-1 */ +#define UDRC10 udrc10.word +#define UDRC10_D15 udrc10.bit._D15 +#define UDRC10_D14 udrc10.bit._D14 +#define UDRC10_D13 udrc10.bit._D13 +#define UDRC10_D12 udrc10.bit._D12 +#define UDRC10_D11 udrc10.bit._D11 +#define UDRC10_D10 udrc10.bit._D10 +#define UDRC10_D9 udrc10.bit._D9 +#define UDRC10_D8 udrc10.bit._D8 +#define UDRC10_D7 udrc10.bit._D7 +#define UDRC10_D6 udrc10.bit._D6 +#define UDRC10_D5 udrc10.bit._D5 +#define UDRC10_D4 udrc10.bit._D4 +#define UDRC10_D3 udrc10.bit._D3 +#define UDRC10_D2 udrc10.bit._D2 +#define UDRC10_D1 udrc10.bit._D1 +#define UDRC10_D0 udrc10.bit._D0 +__IO_EXTERN UDRC1STR udrc1; +#define UDRC1 udrc1.byte +#define UDRC1_D7 udrc1.bit._D7 +#define UDRC1_D6 udrc1.bit._D6 +#define UDRC1_D5 udrc1.bit._D5 +#define UDRC1_D4 udrc1.bit._D4 +#define UDRC1_D3 udrc1.bit._D3 +#define UDRC1_D2 udrc1.bit._D2 +#define UDRC1_D1 udrc1.bit._D1 +#define UDRC1_D0 udrc1.bit._D0 +__IO_EXTERN UDRC0STR udrc0; +#define UDRC0 udrc0.byte +#define UDRC0_D7 udrc0.bit._D7 +#define UDRC0_D6 udrc0.bit._D6 +#define UDRC0_D5 udrc0.bit._D5 +#define UDRC0_D4 udrc0.bit._D4 +#define UDRC0_D3 udrc0.bit._D3 +#define UDRC0_D2 udrc0.bit._D2 +#define UDRC0_D1 udrc0.bit._D1 +#define UDRC0_D0 udrc0.bit._D0 +__IO_EXTERN UDCR10STR udcr10; +#define UDCR10 udcr10.word +#define UDCR10_D15 udcr10.bit._D15 +#define UDCR10_D14 udcr10.bit._D14 +#define UDCR10_D13 udcr10.bit._D13 +#define UDCR10_D12 udcr10.bit._D12 +#define UDCR10_D11 udcr10.bit._D11 +#define UDCR10_D10 udcr10.bit._D10 +#define UDCR10_D9 udcr10.bit._D9 +#define UDCR10_D8 udcr10.bit._D8 +#define UDCR10_D7 udcr10.bit._D7 +#define UDCR10_D6 udcr10.bit._D6 +#define UDCR10_D5 udcr10.bit._D5 +#define UDCR10_D4 udcr10.bit._D4 +#define UDCR10_D3 udcr10.bit._D3 +#define UDCR10_D2 udcr10.bit._D2 +#define UDCR10_D1 udcr10.bit._D1 +#define UDCR10_D0 udcr10.bit._D0 +__IO_EXTERN UDCR1STR udcr1; +#define UDCR1 udcr1.byte +#define UDCR1_D7 udcr1.bit._D7 +#define UDCR1_D6 udcr1.bit._D6 +#define UDCR1_D5 udcr1.bit._D5 +#define UDCR1_D4 udcr1.bit._D4 +#define UDCR1_D3 udcr1.bit._D3 +#define UDCR1_D2 udcr1.bit._D2 +#define UDCR1_D1 udcr1.bit._D1 +#define UDCR1_D0 udcr1.bit._D0 +__IO_EXTERN UDCR0STR udcr0; +#define UDCR0 udcr0.byte +#define UDCR0_D7 udcr0.bit._D7 +#define UDCR0_D6 udcr0.bit._D6 +#define UDCR0_D5 udcr0.bit._D5 +#define UDCR0_D4 udcr0.bit._D4 +#define UDCR0_D3 udcr0.bit._D3 +#define UDCR0_D2 udcr0.bit._D2 +#define UDCR0_D1 udcr0.bit._D1 +#define UDCR0_D0 udcr0.bit._D0 +__IO_EXTERN UDCC0STR udcc0; +#define UDCC0 udcc0.word +#define UDCC0_M16E udcc0.bit._M16E +#define UDCC0_CDCF udcc0.bit._CDCF +#define UDCC0_CFIE udcc0.bit._CFIE +#define UDCC0_CLKS udcc0.bit._CLKS +#define UDCC0_CMS1 udcc0.bit._CMS1 +#define UDCC0_CMS0 udcc0.bit._CMS0 +#define UDCC0_CES1 udcc0.bit._CES1 +#define UDCC0_CES0 udcc0.bit._CES0 +#define UDCC0_CTUT udcc0.bit._CTUT +#define UDCC0_UCRE udcc0.bit._UCRE +#define UDCC0_RLDE udcc0.bit._RLDE +#define UDCC0_UDCLR udcc0.bit._UDCLR +#define UDCC0_CGSC udcc0.bit._CGSC +#define UDCC0_CGE1 udcc0.bit._CGE1 +#define UDCC0_CGE0 udcc0.bit._CGE0 +#define UDCC0_CMS udcc0.bitc._CMS +#define UDCC0_CES udcc0.bitc._CES +#define UDCC0_CGE udcc0.bitc._CGE +__IO_EXTERN UDCCH0STR udcch0; +#define UDCCH0 udcch0.byte +#define UDCCH0_M16E udcch0.bit._M16E +#define UDCCH0_CDCF udcch0.bit._CDCF +#define UDCCH0_CFIE udcch0.bit._CFIE +#define UDCCH0_CLKS udcch0.bit._CLKS +#define UDCCH0_CMS1 udcch0.bit._CMS1 +#define UDCCH0_CMS0 udcch0.bit._CMS0 +#define UDCCH0_CES1 udcch0.bit._CES1 +#define UDCCH0_CES0 udcch0.bit._CES0 +#define UDCCH0_CMS udcch0.bitc._CMS +#define UDCCH0_CES udcch0.bitc._CES +__IO_EXTERN UDCCL0STR udccl0; +#define UDCCL0 udccl0.byte +#define UDCCL0_CTUT udccl0.bit._CTUT +#define UDCCL0_UCRE udccl0.bit._UCRE +#define UDCCL0_RLDE udccl0.bit._RLDE +#define UDCCL0_UDCLR udccl0.bit._UDCLR +#define UDCCL0_CGSC udccl0.bit._CGSC +#define UDCCL0_CGE1 udccl0.bit._CGE1 +#define UDCCL0_CGE0 udccl0.bit._CGE0 +#define UDCCL0_CGE udccl0.bitc._CGE +__IO_EXTERN UDCS0STR udcs0; +#define UDCS0 udcs0.byte +#define UDCS0_CSTR udcs0.bit._CSTR +#define UDCS0_CITE udcs0.bit._CITE +#define UDCS0_UDIE udcs0.bit._UDIE +#define UDCS0_CMPF udcs0.bit._CMPF +#define UDCS0_OVFF udcs0.bit._OVFF +#define UDCS0_UDFF udcs0.bit._UDFF +#define UDCS0_UDF1 udcs0.bit._UDF1 +#define UDCS0_UDF0 udcs0.bit._UDF0 +#define UDCS0_UDF udcs0.bitc._UDF +__IO_EXTERN UDCC1STR udcc1; +#define UDCC1 udcc1.word +#define UDCC1_RESV15 udcc1.bit._RESV15 +#define UDCC1_CDCF udcc1.bit._CDCF +#define UDCC1_CFIE udcc1.bit._CFIE +#define UDCC1_CLKS udcc1.bit._CLKS +#define UDCC1_CMS1 udcc1.bit._CMS1 +#define UDCC1_CMS0 udcc1.bit._CMS0 +#define UDCC1_CES1 udcc1.bit._CES1 +#define UDCC1_CES0 udcc1.bit._CES0 +#define UDCC1_CTUT udcc1.bit._CTUT +#define UDCC1_UCRE udcc1.bit._UCRE +#define UDCC1_RLDE udcc1.bit._RLDE +#define UDCC1_UDCLR udcc1.bit._UDCLR +#define UDCC1_CGSC udcc1.bit._CGSC +#define UDCC1_CGE1 udcc1.bit._CGE1 +#define UDCC1_CGE0 udcc1.bit._CGE0 +#define UDCC1_CMS udcc1.bitc._CMS +#define UDCC1_CES udcc1.bitc._CES +#define UDCC1_CGE udcc1.bitc._CGE +__IO_EXTERN UDCCH1STR udcch1; +#define UDCCH1 udcch1.byte +#define UDCCH1_RESV15 udcch1.bit._RESV15 +#define UDCCH1_CDCF udcch1.bit._CDCF +#define UDCCH1_CFIE udcch1.bit._CFIE +#define UDCCH1_CLKS udcch1.bit._CLKS +#define UDCCH1_CMS1 udcch1.bit._CMS1 +#define UDCCH1_CMS0 udcch1.bit._CMS0 +#define UDCCH1_CES1 udcch1.bit._CES1 +#define UDCCH1_CES0 udcch1.bit._CES0 +#define UDCCH1_CMS udcch1.bitc._CMS +#define UDCCH1_CES udcch1.bitc._CES +__IO_EXTERN UDCCL1STR udccl1; +#define UDCCL1 udccl1.byte +#define UDCCL1_CTUT udccl1.bit._CTUT +#define UDCCL1_UCRE udccl1.bit._UCRE +#define UDCCL1_RLDE udccl1.bit._RLDE +#define UDCCL1_UDCLR udccl1.bit._UDCLR +#define UDCCL1_CGSC udccl1.bit._CGSC +#define UDCCL1_CGE1 udccl1.bit._CGE1 +#define UDCCL1_CGE0 udccl1.bit._CGE0 +#define UDCCL1_CGE udccl1.bitc._CGE +__IO_EXTERN UDCS1STR udcs1; +#define UDCS1 udcs1.byte +#define UDCS1_CSTR udcs1.bit._CSTR +#define UDCS1_CITE udcs1.bit._CITE +#define UDCS1_UDIE udcs1.bit._UDIE +#define UDCS1_CMPF udcs1.bit._CMPF +#define UDCS1_OVFF udcs1.bit._OVFF +#define UDCS1_UDFF udcs1.bit._UDFF +#define UDCS1_UDF1 udcs1.bit._UDF1 +#define UDCS1_UDF0 udcs1.bit._UDF0 +#define UDCS1_UDF udcs1.bitc._UDF +__IO_EXTERN UDRC32STR udrc32; /* Up/Down Counter 2-3 */ +#define UDRC32 udrc32.word +#define UDRC32_D15 udrc32.bit._D15 +#define UDRC32_D14 udrc32.bit._D14 +#define UDRC32_D13 udrc32.bit._D13 +#define UDRC32_D12 udrc32.bit._D12 +#define UDRC32_D11 udrc32.bit._D11 +#define UDRC32_D10 udrc32.bit._D10 +#define UDRC32_D9 udrc32.bit._D9 +#define UDRC32_D8 udrc32.bit._D8 +#define UDRC32_D7 udrc32.bit._D7 +#define UDRC32_D6 udrc32.bit._D6 +#define UDRC32_D5 udrc32.bit._D5 +#define UDRC32_D4 udrc32.bit._D4 +#define UDRC32_D3 udrc32.bit._D3 +#define UDRC32_D2 udrc32.bit._D2 +#define UDRC32_D1 udrc32.bit._D1 +#define UDRC32_D0 udrc32.bit._D0 +__IO_EXTERN UDRC3STR udrc3; +#define UDRC3 udrc3.byte +#define UDRC3_D7 udrc3.bit._D7 +#define UDRC3_D6 udrc3.bit._D6 +#define UDRC3_D5 udrc3.bit._D5 +#define UDRC3_D4 udrc3.bit._D4 +#define UDRC3_D3 udrc3.bit._D3 +#define UDRC3_D2 udrc3.bit._D2 +#define UDRC3_D1 udrc3.bit._D1 +#define UDRC3_D0 udrc3.bit._D0 +__IO_EXTERN UDRC2STR udrc2; +#define UDRC2 udrc2.byte +#define UDRC2_D7 udrc2.bit._D7 +#define UDRC2_D6 udrc2.bit._D6 +#define UDRC2_D5 udrc2.bit._D5 +#define UDRC2_D4 udrc2.bit._D4 +#define UDRC2_D3 udrc2.bit._D3 +#define UDRC2_D2 udrc2.bit._D2 +#define UDRC2_D1 udrc2.bit._D1 +#define UDRC2_D0 udrc2.bit._D0 +__IO_EXTERN UDCR32STR udcr32; +#define UDCR32 udcr32.word +#define UDCR32_D15 udcr32.bit._D15 +#define UDCR32_D14 udcr32.bit._D14 +#define UDCR32_D13 udcr32.bit._D13 +#define UDCR32_D12 udcr32.bit._D12 +#define UDCR32_D11 udcr32.bit._D11 +#define UDCR32_D10 udcr32.bit._D10 +#define UDCR32_D9 udcr32.bit._D9 +#define UDCR32_D8 udcr32.bit._D8 +#define UDCR32_D7 udcr32.bit._D7 +#define UDCR32_D6 udcr32.bit._D6 +#define UDCR32_D5 udcr32.bit._D5 +#define UDCR32_D4 udcr32.bit._D4 +#define UDCR32_D3 udcr32.bit._D3 +#define UDCR32_D2 udcr32.bit._D2 +#define UDCR32_D1 udcr32.bit._D1 +#define UDCR32_D0 udcr32.bit._D0 +__IO_EXTERN UDCR3STR udcr3; +#define UDCR3 udcr3.byte +#define UDCR3_D7 udcr3.bit._D7 +#define UDCR3_D6 udcr3.bit._D6 +#define UDCR3_D5 udcr3.bit._D5 +#define UDCR3_D4 udcr3.bit._D4 +#define UDCR3_D3 udcr3.bit._D3 +#define UDCR3_D2 udcr3.bit._D2 +#define UDCR3_D1 udcr3.bit._D1 +#define UDCR3_D0 udcr3.bit._D0 +__IO_EXTERN UDCR2STR udcr2; +#define UDCR2 udcr2.byte +#define UDCR2_D7 udcr2.bit._D7 +#define UDCR2_D6 udcr2.bit._D6 +#define UDCR2_D5 udcr2.bit._D5 +#define UDCR2_D4 udcr2.bit._D4 +#define UDCR2_D3 udcr2.bit._D3 +#define UDCR2_D2 udcr2.bit._D2 +#define UDCR2_D1 udcr2.bit._D1 +#define UDCR2_D0 udcr2.bit._D0 +__IO_EXTERN UDCC2STR udcc2; +#define UDCC2 udcc2.word +#define UDCC2_M16E udcc2.bit._M16E +#define UDCC2_CDCF udcc2.bit._CDCF +#define UDCC2_CFIE udcc2.bit._CFIE +#define UDCC2_CLKS udcc2.bit._CLKS +#define UDCC2_CMS1 udcc2.bit._CMS1 +#define UDCC2_CMS0 udcc2.bit._CMS0 +#define UDCC2_CES1 udcc2.bit._CES1 +#define UDCC2_CES0 udcc2.bit._CES0 +#define UDCC2_CTUT udcc2.bit._CTUT +#define UDCC2_UCRE udcc2.bit._UCRE +#define UDCC2_RLDE udcc2.bit._RLDE +#define UDCC2_UDCLR udcc2.bit._UDCLR +#define UDCC2_CGSC udcc2.bit._CGSC +#define UDCC2_CGE1 udcc2.bit._CGE1 +#define UDCC2_CGE0 udcc2.bit._CGE0 +#define UDCC2_CMS udcc2.bitc._CMS +#define UDCC2_CES udcc2.bitc._CES +#define UDCC2_CGE udcc2.bitc._CGE +__IO_EXTERN UDCCH2STR udcch2; +#define UDCCH2 udcch2.byte +#define UDCCH2_M16E udcch2.bit._M16E +#define UDCCH2_CDCF udcch2.bit._CDCF +#define UDCCH2_CFIE udcch2.bit._CFIE +#define UDCCH2_CLKS udcch2.bit._CLKS +#define UDCCH2_CMS1 udcch2.bit._CMS1 +#define UDCCH2_CMS0 udcch2.bit._CMS0 +#define UDCCH2_CES1 udcch2.bit._CES1 +#define UDCCH2_CES0 udcch2.bit._CES0 +#define UDCCH2_CMS udcch2.bitc._CMS +#define UDCCH2_CES udcch2.bitc._CES +__IO_EXTERN UDCCL2STR udccl2; +#define UDCCL2 udccl2.byte +#define UDCCL2_CTUT udccl2.bit._CTUT +#define UDCCL2_UCRE udccl2.bit._UCRE +#define UDCCL2_RLDE udccl2.bit._RLDE +#define UDCCL2_UDCLR udccl2.bit._UDCLR +#define UDCCL2_CGSC udccl2.bit._CGSC +#define UDCCL2_CGE1 udccl2.bit._CGE1 +#define UDCCL2_CGE0 udccl2.bit._CGE0 +#define UDCCL2_CGE udccl2.bitc._CGE +__IO_EXTERN UDCS2STR udcs2; +#define UDCS2 udcs2.byte +#define UDCS2_CSTR udcs2.bit._CSTR +#define UDCS2_CITE udcs2.bit._CITE +#define UDCS2_UDIE udcs2.bit._UDIE +#define UDCS2_CMPF udcs2.bit._CMPF +#define UDCS2_OVFF udcs2.bit._OVFF +#define UDCS2_UDFF udcs2.bit._UDFF +#define UDCS2_UDF1 udcs2.bit._UDF1 +#define UDCS2_UDF0 udcs2.bit._UDF0 +#define UDCS2_UDF udcs2.bitc._UDF +__IO_EXTERN UDCC3STR udcc3; +#define UDCC3 udcc3.word +#define UDCC3_RESV15 udcc3.bit._RESV15 +#define UDCC3_CDCF udcc3.bit._CDCF +#define UDCC3_CFIE udcc3.bit._CFIE +#define UDCC3_CLKS udcc3.bit._CLKS +#define UDCC3_CMS1 udcc3.bit._CMS1 +#define UDCC3_CMS0 udcc3.bit._CMS0 +#define UDCC3_CES1 udcc3.bit._CES1 +#define UDCC3_CES0 udcc3.bit._CES0 +#define UDCC3_CTUT udcc3.bit._CTUT +#define UDCC3_UCRE udcc3.bit._UCRE +#define UDCC3_RLDE udcc3.bit._RLDE +#define UDCC3_UDCLR udcc3.bit._UDCLR +#define UDCC3_CGSC udcc3.bit._CGSC +#define UDCC3_CGE1 udcc3.bit._CGE1 +#define UDCC3_CGE0 udcc3.bit._CGE0 +#define UDCC3_CMS udcc3.bitc._CMS +#define UDCC3_CES udcc3.bitc._CES +#define UDCC3_CGE udcc3.bitc._CGE +__IO_EXTERN UDCCH3STR udcch3; +#define UDCCH3 udcch3.byte +#define UDCCH3_RESV15 udcch3.bit._RESV15 +#define UDCCH3_CDCF udcch3.bit._CDCF +#define UDCCH3_CFIE udcch3.bit._CFIE +#define UDCCH3_CLKS udcch3.bit._CLKS +#define UDCCH3_CMS1 udcch3.bit._CMS1 +#define UDCCH3_CMS0 udcch3.bit._CMS0 +#define UDCCH3_CES1 udcch3.bit._CES1 +#define UDCCH3_CES0 udcch3.bit._CES0 +#define UDCCH3_CMS udcch3.bitc._CMS +#define UDCCH3_CES udcch3.bitc._CES +__IO_EXTERN UDCCL3STR udccl3; +#define UDCCL3 udccl3.byte +#define UDCCL3_CTUT udccl3.bit._CTUT +#define UDCCL3_UCRE udccl3.bit._UCRE +#define UDCCL3_RLDE udccl3.bit._RLDE +#define UDCCL3_UDCLR udccl3.bit._UDCLR +#define UDCCL3_CGSC udccl3.bit._CGSC +#define UDCCL3_CGE1 udccl3.bit._CGE1 +#define UDCCL3_CGE0 udccl3.bit._CGE0 +#define UDCCL3_CGE udccl3.bitc._CGE +__IO_EXTERN UDCS3STR udcs3; +#define UDCS3 udcs3.byte +#define UDCS3_CSTR udcs3.bit._CSTR +#define UDCS3_CITE udcs3.bit._CITE +#define UDCS3_UDIE udcs3.bit._UDIE +#define UDCS3_CMPF udcs3.bit._CMPF +#define UDCS3_OVFF udcs3.bit._OVFF +#define UDCS3_UDFF udcs3.bit._UDFF +#define UDCS3_UDF1 udcs3.bit._UDF1 +#define UDCS3_UDF0 udcs3.bit._UDF0 +#define UDCS3_UDF udcs3.bitc._UDF +__IO_EXTERN GCN13STR gcn13; /* PPG Control 12-15 */ +#define GCN13 gcn13.word +#define GCN13_TSEL33 gcn13.bit._TSEL33 +#define GCN13_TSEL32 gcn13.bit._TSEL32 +#define GCN13_TSEL31 gcn13.bit._TSEL31 +#define GCN13_TSEL30 gcn13.bit._TSEL30 +#define GCN13_TSEL23 gcn13.bit._TSEL23 +#define GCN13_TSEL22 gcn13.bit._TSEL22 +#define GCN13_TSEL21 gcn13.bit._TSEL21 +#define GCN13_TSEL20 gcn13.bit._TSEL20 +#define GCN13_TSEL13 gcn13.bit._TSEL13 +#define GCN13_TSEL12 gcn13.bit._TSEL12 +#define GCN13_TSEL11 gcn13.bit._TSEL11 +#define GCN13_TSEL10 gcn13.bit._TSEL10 +#define GCN13_TSEL03 gcn13.bit._TSEL03 +#define GCN13_TSEL02 gcn13.bit._TSEL02 +#define GCN13_TSEL01 gcn13.bit._TSEL01 +#define GCN13_TSEL00 gcn13.bit._TSEL00 +__IO_EXTERN GCN23STR gcn23; +#define GCN23 gcn23.byte +#define GCN23_EN3 gcn23.bit._EN3 +#define GCN23_EN2 gcn23.bit._EN2 +#define GCN23_EN1 gcn23.bit._EN1 +#define GCN23_EN0 gcn23.bit._EN0 +__IO_EXTERN IO_WORD ptmr12; /* PPG 12 */ +#define PTMR12 ptmr12 +__IO_EXTERN IO_WORD pcsr12; +#define PCSR12 pcsr12 +__IO_EXTERN IO_WORD pdut12; +#define PDUT12 pdut12 +__IO_EXTERN PCN12STR pcn12; +#define PCN12 pcn12.word +#define PCN12_CNTE pcn12.bit._CNTE +#define PCN12_STGR pcn12.bit._STGR +#define PCN12_MDSE pcn12.bit._MDSE +#define PCN12_RTRG pcn12.bit._RTRG +#define PCN12_CKS1 pcn12.bit._CKS1 +#define PCN12_CKS0 pcn12.bit._CKS0 +#define PCN12_PGMS pcn12.bit._PGMS +#define PCN12_EGS1 pcn12.bit._EGS1 +#define PCN12_EGS0 pcn12.bit._EGS0 +#define PCN12_IREN pcn12.bit._IREN +#define PCN12_IRQF pcn12.bit._IRQF +#define PCN12_IRS1 pcn12.bit._IRS1 +#define PCN12_IRS0 pcn12.bit._IRS0 +#define PCN12_OSEL pcn12.bit._OSEL +#define PCN12_CKS pcn12.bitc._CKS +#define PCN12_EGS pcn12.bitc._EGS +#define PCN12_IRS pcn12.bitc._IRS +__IO_EXTERN PCNH12STR pcnh12; +#define PCNH12 pcnh12.byte +#define PCNH12_CNTE pcnh12.bit._CNTE +#define PCNH12_STGR pcnh12.bit._STGR +#define PCNH12_MDSE pcnh12.bit._MDSE +#define PCNH12_RTRG pcnh12.bit._RTRG +#define PCNH12_CKS1 pcnh12.bit._CKS1 +#define PCNH12_CKS0 pcnh12.bit._CKS0 +#define PCNH12_PGMS pcnh12.bit._PGMS +#define PCNH12_CKS pcnh12.bitc._CKS +__IO_EXTERN PCNL12STR pcnl12; +#define PCNL12 pcnl12.byte +#define PCNL12_EGS1 pcnl12.bit._EGS1 +#define PCNL12_EGS0 pcnl12.bit._EGS0 +#define PCNL12_IREN pcnl12.bit._IREN +#define PCNL12_IRQF pcnl12.bit._IRQF +#define PCNL12_IRS1 pcnl12.bit._IRS1 +#define PCNL12_IRS0 pcnl12.bit._IRS0 +#define PCNL12_OSEL pcnl12.bit._OSEL +#define PCNL12_EGS pcnl12.bitc._EGS +#define PCNL12_IRS pcnl12.bitc._IRS +__IO_EXTERN IO_WORD ptmr13; /* PPG 13 */ +#define PTMR13 ptmr13 +__IO_EXTERN IO_WORD pcsr13; +#define PCSR13 pcsr13 +__IO_EXTERN IO_WORD pdut13; +#define PDUT13 pdut13 +__IO_EXTERN PCN13STR pcn13; +#define PCN13 pcn13.word +#define PCN13_CNTE pcn13.bit._CNTE +#define PCN13_STGR pcn13.bit._STGR +#define PCN13_MDSE pcn13.bit._MDSE +#define PCN13_RTRG pcn13.bit._RTRG +#define PCN13_CKS1 pcn13.bit._CKS1 +#define PCN13_CKS0 pcn13.bit._CKS0 +#define PCN13_PGMS pcn13.bit._PGMS +#define PCN13_EGS1 pcn13.bit._EGS1 +#define PCN13_EGS0 pcn13.bit._EGS0 +#define PCN13_IREN pcn13.bit._IREN +#define PCN13_IRQF pcn13.bit._IRQF +#define PCN13_IRS1 pcn13.bit._IRS1 +#define PCN13_IRS0 pcn13.bit._IRS0 +#define PCN13_OSEL pcn13.bit._OSEL +#define PCN13_CKS pcn13.bitc._CKS +#define PCN13_EGS pcn13.bitc._EGS +#define PCN13_IRS pcn13.bitc._IRS +__IO_EXTERN PCNH13STR pcnh13; +#define PCNH13 pcnh13.byte +#define PCNH13_CNTE pcnh13.bit._CNTE +#define PCNH13_STGR pcnh13.bit._STGR +#define PCNH13_MDSE pcnh13.bit._MDSE +#define PCNH13_RTRG pcnh13.bit._RTRG +#define PCNH13_CKS1 pcnh13.bit._CKS1 +#define PCNH13_CKS0 pcnh13.bit._CKS0 +#define PCNH13_PGMS pcnh13.bit._PGMS +#define PCNH13_CKS pcnh13.bitc._CKS +__IO_EXTERN PCNL13STR pcnl13; +#define PCNL13 pcnl13.byte +#define PCNL13_EGS1 pcnl13.bit._EGS1 +#define PCNL13_EGS0 pcnl13.bit._EGS0 +#define PCNL13_IREN pcnl13.bit._IREN +#define PCNL13_IRQF pcnl13.bit._IRQF +#define PCNL13_IRS1 pcnl13.bit._IRS1 +#define PCNL13_IRS0 pcnl13.bit._IRS0 +#define PCNL13_OSEL pcnl13.bit._OSEL +#define PCNL13_EGS pcnl13.bitc._EGS +#define PCNL13_IRS pcnl13.bitc._IRS +__IO_EXTERN IO_WORD ptmr14; /* PPG 14 */ +#define PTMR14 ptmr14 +__IO_EXTERN IO_WORD pcsr14; +#define PCSR14 pcsr14 +__IO_EXTERN IO_WORD pdut14; +#define PDUT14 pdut14 +__IO_EXTERN PCN14STR pcn14; +#define PCN14 pcn14.word +#define PCN14_CNTE pcn14.bit._CNTE +#define PCN14_STGR pcn14.bit._STGR +#define PCN14_MDSE pcn14.bit._MDSE +#define PCN14_RTRG pcn14.bit._RTRG +#define PCN14_CKS1 pcn14.bit._CKS1 +#define PCN14_CKS0 pcn14.bit._CKS0 +#define PCN14_PGMS pcn14.bit._PGMS +#define PCN14_EGS1 pcn14.bit._EGS1 +#define PCN14_EGS0 pcn14.bit._EGS0 +#define PCN14_IREN pcn14.bit._IREN +#define PCN14_IRQF pcn14.bit._IRQF +#define PCN14_IRS1 pcn14.bit._IRS1 +#define PCN14_IRS0 pcn14.bit._IRS0 +#define PCN14_OSEL pcn14.bit._OSEL +#define PCN14_CKS pcn14.bitc._CKS +#define PCN14_EGS pcn14.bitc._EGS +#define PCN14_IRS pcn14.bitc._IRS +__IO_EXTERN PCNH14STR pcnh14; +#define PCNH14 pcnh14.byte +#define PCNH14_CNTE pcnh14.bit._CNTE +#define PCNH14_STGR pcnh14.bit._STGR +#define PCNH14_MDSE pcnh14.bit._MDSE +#define PCNH14_RTRG pcnh14.bit._RTRG +#define PCNH14_CKS1 pcnh14.bit._CKS1 +#define PCNH14_CKS0 pcnh14.bit._CKS0 +#define PCNH14_PGMS pcnh14.bit._PGMS +#define PCNH14_CKS pcnh14.bitc._CKS +__IO_EXTERN PCNL14STR pcnl14; +#define PCNL14 pcnl14.byte +#define PCNL14_EGS1 pcnl14.bit._EGS1 +#define PCNL14_EGS0 pcnl14.bit._EGS0 +#define PCNL14_IREN pcnl14.bit._IREN +#define PCNL14_IRQF pcnl14.bit._IRQF +#define PCNL14_IRS1 pcnl14.bit._IRS1 +#define PCNL14_IRS0 pcnl14.bit._IRS0 +#define PCNL14_OSEL pcnl14.bit._OSEL +#define PCNL14_EGS pcnl14.bitc._EGS +#define PCNL14_IRS pcnl14.bitc._IRS +__IO_EXTERN IO_WORD ptmr15; /* PPG 15 */ +#define PTMR15 ptmr15 +__IO_EXTERN IO_WORD pcsr15; +#define PCSR15 pcsr15 +__IO_EXTERN IO_WORD pdut15; +#define PDUT15 pdut15 +__IO_EXTERN PCN15STR pcn15; +#define PCN15 pcn15.word +#define PCN15_CNTE pcn15.bit._CNTE +#define PCN15_STGR pcn15.bit._STGR +#define PCN15_MDSE pcn15.bit._MDSE +#define PCN15_RTRG pcn15.bit._RTRG +#define PCN15_CKS1 pcn15.bit._CKS1 +#define PCN15_CKS0 pcn15.bit._CKS0 +#define PCN15_PGMS pcn15.bit._PGMS +#define PCN15_EGS1 pcn15.bit._EGS1 +#define PCN15_EGS0 pcn15.bit._EGS0 +#define PCN15_IREN pcn15.bit._IREN +#define PCN15_IRQF pcn15.bit._IRQF +#define PCN15_IRS1 pcn15.bit._IRS1 +#define PCN15_IRS0 pcn15.bit._IRS0 +#define PCN15_OSEL pcn15.bit._OSEL +#define PCN15_CKS pcn15.bitc._CKS +#define PCN15_EGS pcn15.bitc._EGS +#define PCN15_IRS pcn15.bitc._IRS +__IO_EXTERN PCNH15STR pcnh15; +#define PCNH15 pcnh15.byte +#define PCNH15_CNTE pcnh15.bit._CNTE +#define PCNH15_STGR pcnh15.bit._STGR +#define PCNH15_MDSE pcnh15.bit._MDSE +#define PCNH15_RTRG pcnh15.bit._RTRG +#define PCNH15_CKS1 pcnh15.bit._CKS1 +#define PCNH15_CKS0 pcnh15.bit._CKS0 +#define PCNH15_PGMS pcnh15.bit._PGMS +#define PCNH15_CKS pcnh15.bitc._CKS +__IO_EXTERN PCNL15STR pcnl15; +#define PCNL15 pcnl15.byte +#define PCNL15_EGS1 pcnl15.bit._EGS1 +#define PCNL15_EGS0 pcnl15.bit._EGS0 +#define PCNL15_IREN pcnl15.bit._IREN +#define PCNL15_IRQF pcnl15.bit._IRQF +#define PCNL15_IRS1 pcnl15.bit._IRS1 +#define PCNL15_IRS0 pcnl15.bit._IRS0 +#define PCNL15_OSEL pcnl15.bit._OSEL +#define PCNL15_EGS pcnl15.bitc._EGS +#define PCNL15_IRS pcnl15.bitc._IRS +__IO_EXTERN IBCR2STR ibcr2; /* I2C 2 */ +#define IBCR2 ibcr2.byte +#define IBCR2_BER ibcr2.bit._BER +#define IBCR2_BEIE ibcr2.bit._BEIE +#define IBCR2_SCC ibcr2.bit._SCC +#define IBCR2_MSS ibcr2.bit._MSS +#define IBCR2_ACK ibcr2.bit._ACK +#define IBCR2_GCAA ibcr2.bit._GCAA +#define IBCR2_INTE ibcr2.bit._INTE +#define IBCR2_INT ibcr2.bit._INT +__IO_EXTERN IBSR2STR ibsr2; +#define IBSR2 ibsr2.byte +#define IBSR2_BB ibsr2.bit._BB +#define IBSR2_RSC ibsr2.bit._RSC +#define IBSR2_AL ibsr2.bit._AL +#define IBSR2_LRB ibsr2.bit._LRB +#define IBSR2_TRX ibsr2.bit._TRX +#define IBSR2_AAS ibsr2.bit._AAS +#define IBSR2_GCA ibsr2.bit._GCA +#define IBSR2_ADT ibsr2.bit._ADT +__IO_EXTERN ITBA2STR itba2; +#define ITBA2 itba2.word +#define ITBA2_TA9 itba2.bit._TA9 +#define ITBA2_TA8 itba2.bit._TA8 +#define ITBA2_TA7 itba2.bit._TA7 +#define ITBA2_TA6 itba2.bit._TA6 +#define ITBA2_TA5 itba2.bit._TA5 +#define ITBA2_TA4 itba2.bit._TA4 +#define ITBA2_TA3 itba2.bit._TA3 +#define ITBA2_TA2 itba2.bit._TA2 +#define ITBA2_TA1 itba2.bit._TA1 +#define ITBA2_TA0 itba2.bit._TA0 +__IO_EXTERN ITBAH2STR itbah2; +#define ITBAH2 itbah2.byte +#define ITBAH2_TA9 itbah2.bit._TA9 +#define ITBAH2_TA8 itbah2.bit._TA8 +__IO_EXTERN ITBAL2STR itbal2; +#define ITBAL2 itbal2.byte +#define ITBAL2_TA7 itbal2.bit._TA7 +#define ITBAL2_TA6 itbal2.bit._TA6 +#define ITBAL2_TA5 itbal2.bit._TA5 +#define ITBAL2_TA4 itbal2.bit._TA4 +#define ITBAL2_TA3 itbal2.bit._TA3 +#define ITBAL2_TA2 itbal2.bit._TA2 +#define ITBAL2_TA1 itbal2.bit._TA1 +#define ITBAL2_TA0 itbal2.bit._TA0 +__IO_EXTERN ITMK2STR itmk2; +#define ITMK2 itmk2.word +#define ITMK2_ENTB itmk2.bit._ENTB +#define ITMK2_RAL itmk2.bit._RAL +#define ITMK2_TM9 itmk2.bit._TM9 +#define ITMK2_TM8 itmk2.bit._TM8 +#define ITMK2_TM7 itmk2.bit._TM7 +#define ITMK2_TM6 itmk2.bit._TM6 +#define ITMK2_TM5 itmk2.bit._TM5 +#define ITMK2_TM4 itmk2.bit._TM4 +#define ITMK2_TM3 itmk2.bit._TM3 +#define ITMK2_TM2 itmk2.bit._TM2 +#define ITMK2_TM1 itmk2.bit._TM1 +#define ITMK2_TM0 itmk2.bit._TM0 +__IO_EXTERN ITMKH2STR itmkh2; +#define ITMKH2 itmkh2.byte +#define ITMKH2_ENTB itmkh2.bit._ENTB +#define ITMKH2_RAL itmkh2.bit._RAL +#define ITMKH2_TM9 itmkh2.bit._TM9 +#define ITMKH2_TM8 itmkh2.bit._TM8 +__IO_EXTERN ITMKL2STR itmkl2; +#define ITMKL2 itmkl2.byte +#define ITMKL2_TM7 itmkl2.bit._TM7 +#define ITMKL2_TM6 itmkl2.bit._TM6 +#define ITMKL2_TM5 itmkl2.bit._TM5 +#define ITMKL2_TM4 itmkl2.bit._TM4 +#define ITMKL2_TM3 itmkl2.bit._TM3 +#define ITMKL2_TM2 itmkl2.bit._TM2 +#define ITMKL2_TM1 itmkl2.bit._TM1 +#define ITMKL2_TM0 itmkl2.bit._TM0 +__IO_EXTERN ISMK2STR ismk2; +#define ISMK2 ismk2.byte +#define ISMK2_ENSB ismk2.bit._ENSB +#define ISMK2_SM6 ismk2.bit._SM6 +#define ISMK2_SM5 ismk2.bit._SM5 +#define ISMK2_SM4 ismk2.bit._SM4 +#define ISMK2_SM3 ismk2.bit._SM3 +#define ISMK2_SM2 ismk2.bit._SM2 +#define ISMK2_SM1 ismk2.bit._SM1 +#define ISMK2_SM0 ismk2.bit._SM0 +__IO_EXTERN ISBA2STR isba2; +#define ISBA2 isba2.byte +#define ISBA2_SA6 isba2.bit._SA6 +#define ISBA2_SA5 isba2.bit._SA5 +#define ISBA2_SA4 isba2.bit._SA4 +#define ISBA2_SA3 isba2.bit._SA3 +#define ISBA2_SA2 isba2.bit._SA2 +#define ISBA2_SA1 isba2.bit._SA1 +#define ISBA2_SA0 isba2.bit._SA0 +__IO_EXTERN IDAR2STR idar2; +#define IDAR2 idar2.byte +#define IDAR2_D7 idar2.bit._D7 +#define IDAR2_D6 idar2.bit._D6 +#define IDAR2_D5 idar2.bit._D5 +#define IDAR2_D4 idar2.bit._D4 +#define IDAR2_D3 idar2.bit._D3 +#define IDAR2_D2 idar2.bit._D2 +#define IDAR2_D1 idar2.bit._D1 +#define IDAR2_D0 idar2.bit._D0 +__IO_EXTERN ICCR2STR iccr2; +#define ICCR2 iccr2.byte +#define ICCR2_NSF iccr2.bit._NSF +#define ICCR2_EN iccr2.bit._EN +#define ICCR2_CS4 iccr2.bit._CS4 +#define ICCR2_CS3 iccr2.bit._CS3 +#define ICCR2_CS2 iccr2.bit._CS2 +#define ICCR2_CS1 iccr2.bit._CS1 +#define ICCR2_CS0 iccr2.bit._CS0 +#define ICCR2_CS iccr2.bitc._CS +__IO_EXTERN IBCR3STR ibcr3; /* I2C 3 */ +#define IBCR3 ibcr3.byte +#define IBCR3_BER ibcr3.bit._BER +#define IBCR3_BEIE ibcr3.bit._BEIE +#define IBCR3_SCC ibcr3.bit._SCC +#define IBCR3_MSS ibcr3.bit._MSS +#define IBCR3_ACK ibcr3.bit._ACK +#define IBCR3_GCAA ibcr3.bit._GCAA +#define IBCR3_INTE ibcr3.bit._INTE +#define IBCR3_INT ibcr3.bit._INT +__IO_EXTERN IBSR3STR ibsr3; +#define IBSR3 ibsr3.byte +#define IBSR3_BB ibsr3.bit._BB +#define IBSR3_RSC ibsr3.bit._RSC +#define IBSR3_AL ibsr3.bit._AL +#define IBSR3_LRB ibsr3.bit._LRB +#define IBSR3_TRX ibsr3.bit._TRX +#define IBSR3_AAS ibsr3.bit._AAS +#define IBSR3_GCA ibsr3.bit._GCA +#define IBSR3_ADT ibsr3.bit._ADT +__IO_EXTERN ITBA3STR itba3; +#define ITBA3 itba3.word +#define ITBA3_TA9 itba3.bit._TA9 +#define ITBA3_TA8 itba3.bit._TA8 +#define ITBA3_TA7 itba3.bit._TA7 +#define ITBA3_TA6 itba3.bit._TA6 +#define ITBA3_TA5 itba3.bit._TA5 +#define ITBA3_TA4 itba3.bit._TA4 +#define ITBA3_TA3 itba3.bit._TA3 +#define ITBA3_TA2 itba3.bit._TA2 +#define ITBA3_TA1 itba3.bit._TA1 +#define ITBA3_TA0 itba3.bit._TA0 +__IO_EXTERN ITBAH3STR itbah3; +#define ITBAH3 itbah3.byte +#define ITBAH3_TA9 itbah3.bit._TA9 +#define ITBAH3_TA8 itbah3.bit._TA8 +__IO_EXTERN ITBAL3STR itbal3; +#define ITBAL3 itbal3.byte +#define ITBAL3_TA7 itbal3.bit._TA7 +#define ITBAL3_TA6 itbal3.bit._TA6 +#define ITBAL3_TA5 itbal3.bit._TA5 +#define ITBAL3_TA4 itbal3.bit._TA4 +#define ITBAL3_TA3 itbal3.bit._TA3 +#define ITBAL3_TA2 itbal3.bit._TA2 +#define ITBAL3_TA1 itbal3.bit._TA1 +#define ITBAL3_TA0 itbal3.bit._TA0 +__IO_EXTERN ITMK3STR itmk3; +#define ITMK3 itmk3.word +#define ITMK3_ENTB itmk3.bit._ENTB +#define ITMK3_RAL itmk3.bit._RAL +#define ITMK3_TM9 itmk3.bit._TM9 +#define ITMK3_TM8 itmk3.bit._TM8 +#define ITMK3_TM7 itmk3.bit._TM7 +#define ITMK3_TM6 itmk3.bit._TM6 +#define ITMK3_TM5 itmk3.bit._TM5 +#define ITMK3_TM4 itmk3.bit._TM4 +#define ITMK3_TM3 itmk3.bit._TM3 +#define ITMK3_TM2 itmk3.bit._TM2 +#define ITMK3_TM1 itmk3.bit._TM1 +#define ITMK3_TM0 itmk3.bit._TM0 +__IO_EXTERN ITMKH3STR itmkh3; +#define ITMKH3 itmkh3.byte +#define ITMKH3_ENTB itmkh3.bit._ENTB +#define ITMKH3_RAL itmkh3.bit._RAL +#define ITMKH3_TM9 itmkh3.bit._TM9 +#define ITMKH3_TM8 itmkh3.bit._TM8 +__IO_EXTERN ITMKL3STR itmkl3; +#define ITMKL3 itmkl3.byte +#define ITMKL3_TM7 itmkl3.bit._TM7 +#define ITMKL3_TM6 itmkl3.bit._TM6 +#define ITMKL3_TM5 itmkl3.bit._TM5 +#define ITMKL3_TM4 itmkl3.bit._TM4 +#define ITMKL3_TM3 itmkl3.bit._TM3 +#define ITMKL3_TM2 itmkl3.bit._TM2 +#define ITMKL3_TM1 itmkl3.bit._TM1 +#define ITMKL3_TM0 itmkl3.bit._TM0 +__IO_EXTERN ISMK3STR ismk3; +#define ISMK3 ismk3.byte +#define ISMK3_ENSB ismk3.bit._ENSB +#define ISMK3_SM6 ismk3.bit._SM6 +#define ISMK3_SM5 ismk3.bit._SM5 +#define ISMK3_SM4 ismk3.bit._SM4 +#define ISMK3_SM3 ismk3.bit._SM3 +#define ISMK3_SM2 ismk3.bit._SM2 +#define ISMK3_SM1 ismk3.bit._SM1 +#define ISMK3_SM0 ismk3.bit._SM0 +__IO_EXTERN ISBA3STR isba3; +#define ISBA3 isba3.byte +#define ISBA3_SA6 isba3.bit._SA6 +#define ISBA3_SA5 isba3.bit._SA5 +#define ISBA3_SA4 isba3.bit._SA4 +#define ISBA3_SA3 isba3.bit._SA3 +#define ISBA3_SA2 isba3.bit._SA2 +#define ISBA3_SA1 isba3.bit._SA1 +#define ISBA3_SA0 isba3.bit._SA0 +__IO_EXTERN IDAR3STR idar3; +#define IDAR3 idar3.byte +#define IDAR3_D7 idar3.bit._D7 +#define IDAR3_D6 idar3.bit._D6 +#define IDAR3_D5 idar3.bit._D5 +#define IDAR3_D4 idar3.bit._D4 +#define IDAR3_D3 idar3.bit._D3 +#define IDAR3_D2 idar3.bit._D2 +#define IDAR3_D1 idar3.bit._D1 +#define IDAR3_D0 idar3.bit._D0 +__IO_EXTERN ICCR3STR iccr3; +#define ICCR3 iccr3.byte +#define ICCR3_NSF iccr3.bit._NSF +#define ICCR3_EN iccr3.bit._EN +#define ICCR3_CS4 iccr3.bit._CS4 +#define ICCR3_CS3 iccr3.bit._CS3 +#define ICCR3_CS2 iccr3.bit._CS2 +#define ICCR3_CS1 iccr3.bit._CS1 +#define ICCR3_CS0 iccr3.bit._CS0 +#define ICCR3_CS iccr3.bitc._CS +__IO_EXTERN ROMSSTR roms; /* ROM Select Register */ +#define ROMS roms.word +#define ROMS_D15 roms.bit._D15 +#define ROMS_D14 roms.bit._D14 +#define ROMS_D13 roms.bit._D13 +#define ROMS_D12 roms.bit._D12 +#define ROMS_D11 roms.bit._D11 +#define ROMS_D10 roms.bit._D10 +#define ROMS_D9 roms.bit._D9 +#define ROMS_D8 roms.bit._D8 +#define ROMS_D7 roms.bit._D7 +#define ROMS_D6 roms.bit._D6 +#define ROMS_D5 roms.bit._D5 +#define ROMS_D4 roms.bit._D4 +#define ROMS_D3 roms.bit._D3 +#define ROMS_D2 roms.bit._D2 +#define ROMS_D1 roms.bit._D1 +#define ROMS_D0 roms.bit._D0 +__IO_EXTERN IO_LWORD bsd0; /* Bit Search Module */ +#define BSD0 bsd0 +__IO_EXTERN IO_LWORD bsd1; +#define BSD1 bsd1 +__IO_EXTERN IO_LWORD bsdc; +#define BSDC bsdc +__IO_EXTERN IO_LWORD bsrr; +#define BSRR bsrr +__IO_EXTERN ICR00STR icr00; /* Interrupt Control Unit */ +#define ICR00 icr00.byte +#define ICR00_ICR4 icr00.bit._ICR4 +#define ICR00_ICR3 icr00.bit._ICR3 +#define ICR00_ICR2 icr00.bit._ICR2 +#define ICR00_ICR1 icr00.bit._ICR1 +#define ICR00_ICR0 icr00.bit._ICR0 +__IO_EXTERN ICR01STR icr01; +#define ICR01 icr01.byte +#define ICR01_ICR4 icr01.bit._ICR4 +#define ICR01_ICR3 icr01.bit._ICR3 +#define ICR01_ICR2 icr01.bit._ICR2 +#define ICR01_ICR1 icr01.bit._ICR1 +#define ICR01_ICR0 icr01.bit._ICR0 +__IO_EXTERN ICR02STR icr02; +#define ICR02 icr02.byte +#define ICR02_ICR4 icr02.bit._ICR4 +#define ICR02_ICR3 icr02.bit._ICR3 +#define ICR02_ICR2 icr02.bit._ICR2 +#define ICR02_ICR1 icr02.bit._ICR1 +#define ICR02_ICR0 icr02.bit._ICR0 +__IO_EXTERN ICR03STR icr03; +#define ICR03 icr03.byte +#define ICR03_ICR4 icr03.bit._ICR4 +#define ICR03_ICR3 icr03.bit._ICR3 +#define ICR03_ICR2 icr03.bit._ICR2 +#define ICR03_ICR1 icr03.bit._ICR1 +#define ICR03_ICR0 icr03.bit._ICR0 +__IO_EXTERN ICR04STR icr04; +#define ICR04 icr04.byte +#define ICR04_ICR4 icr04.bit._ICR4 +#define ICR04_ICR3 icr04.bit._ICR3 +#define ICR04_ICR2 icr04.bit._ICR2 +#define ICR04_ICR1 icr04.bit._ICR1 +#define ICR04_ICR0 icr04.bit._ICR0 +__IO_EXTERN ICR05STR icr05; +#define ICR05 icr05.byte +#define ICR05_ICR4 icr05.bit._ICR4 +#define ICR05_ICR3 icr05.bit._ICR3 +#define ICR05_ICR2 icr05.bit._ICR2 +#define ICR05_ICR1 icr05.bit._ICR1 +#define ICR05_ICR0 icr05.bit._ICR0 +__IO_EXTERN ICR06STR icr06; +#define ICR06 icr06.byte +#define ICR06_ICR4 icr06.bit._ICR4 +#define ICR06_ICR3 icr06.bit._ICR3 +#define ICR06_ICR2 icr06.bit._ICR2 +#define ICR06_ICR1 icr06.bit._ICR1 +#define ICR06_ICR0 icr06.bit._ICR0 +__IO_EXTERN ICR07STR icr07; +#define ICR07 icr07.byte +#define ICR07_ICR4 icr07.bit._ICR4 +#define ICR07_ICR3 icr07.bit._ICR3 +#define ICR07_ICR2 icr07.bit._ICR2 +#define ICR07_ICR1 icr07.bit._ICR1 +#define ICR07_ICR0 icr07.bit._ICR0 +__IO_EXTERN ICR08STR icr08; +#define ICR08 icr08.byte +#define ICR08_ICR4 icr08.bit._ICR4 +#define ICR08_ICR3 icr08.bit._ICR3 +#define ICR08_ICR2 icr08.bit._ICR2 +#define ICR08_ICR1 icr08.bit._ICR1 +#define ICR08_ICR0 icr08.bit._ICR0 +__IO_EXTERN ICR09STR icr09; +#define ICR09 icr09.byte +#define ICR09_ICR4 icr09.bit._ICR4 +#define ICR09_ICR3 icr09.bit._ICR3 +#define ICR09_ICR2 icr09.bit._ICR2 +#define ICR09_ICR1 icr09.bit._ICR1 +#define ICR09_ICR0 icr09.bit._ICR0 +__IO_EXTERN ICR10STR icr10; +#define ICR10 icr10.byte +#define ICR10_ICR4 icr10.bit._ICR4 +#define ICR10_ICR3 icr10.bit._ICR3 +#define ICR10_ICR2 icr10.bit._ICR2 +#define ICR10_ICR1 icr10.bit._ICR1 +#define ICR10_ICR0 icr10.bit._ICR0 +__IO_EXTERN ICR11STR icr11; +#define ICR11 icr11.byte +#define ICR11_ICR4 icr11.bit._ICR4 +#define ICR11_ICR3 icr11.bit._ICR3 +#define ICR11_ICR2 icr11.bit._ICR2 +#define ICR11_ICR1 icr11.bit._ICR1 +#define ICR11_ICR0 icr11.bit._ICR0 +__IO_EXTERN ICR12STR icr12; +#define ICR12 icr12.byte +#define ICR12_ICR4 icr12.bit._ICR4 +#define ICR12_ICR3 icr12.bit._ICR3 +#define ICR12_ICR2 icr12.bit._ICR2 +#define ICR12_ICR1 icr12.bit._ICR1 +#define ICR12_ICR0 icr12.bit._ICR0 +__IO_EXTERN ICR13STR icr13; +#define ICR13 icr13.byte +#define ICR13_ICR4 icr13.bit._ICR4 +#define ICR13_ICR3 icr13.bit._ICR3 +#define ICR13_ICR2 icr13.bit._ICR2 +#define ICR13_ICR1 icr13.bit._ICR1 +#define ICR13_ICR0 icr13.bit._ICR0 +__IO_EXTERN ICR14STR icr14; +#define ICR14 icr14.byte +#define ICR14_ICR4 icr14.bit._ICR4 +#define ICR14_ICR3 icr14.bit._ICR3 +#define ICR14_ICR2 icr14.bit._ICR2 +#define ICR14_ICR1 icr14.bit._ICR1 +#define ICR14_ICR0 icr14.bit._ICR0 +__IO_EXTERN ICR15STR icr15; +#define ICR15 icr15.byte +#define ICR15_ICR4 icr15.bit._ICR4 +#define ICR15_ICR3 icr15.bit._ICR3 +#define ICR15_ICR2 icr15.bit._ICR2 +#define ICR15_ICR1 icr15.bit._ICR1 +#define ICR15_ICR0 icr15.bit._ICR0 +__IO_EXTERN ICR16STR icr16; +#define ICR16 icr16.byte +#define ICR16_ICR4 icr16.bit._ICR4 +#define ICR16_ICR3 icr16.bit._ICR3 +#define ICR16_ICR2 icr16.bit._ICR2 +#define ICR16_ICR1 icr16.bit._ICR1 +#define ICR16_ICR0 icr16.bit._ICR0 +__IO_EXTERN ICR17STR icr17; +#define ICR17 icr17.byte +#define ICR17_ICR4 icr17.bit._ICR4 +#define ICR17_ICR3 icr17.bit._ICR3 +#define ICR17_ICR2 icr17.bit._ICR2 +#define ICR17_ICR1 icr17.bit._ICR1 +#define ICR17_ICR0 icr17.bit._ICR0 +__IO_EXTERN ICR18STR icr18; +#define ICR18 icr18.byte +#define ICR18_ICR4 icr18.bit._ICR4 +#define ICR18_ICR3 icr18.bit._ICR3 +#define ICR18_ICR2 icr18.bit._ICR2 +#define ICR18_ICR1 icr18.bit._ICR1 +#define ICR18_ICR0 icr18.bit._ICR0 +__IO_EXTERN ICR19STR icr19; +#define ICR19 icr19.byte +#define ICR19_ICR4 icr19.bit._ICR4 +#define ICR19_ICR3 icr19.bit._ICR3 +#define ICR19_ICR2 icr19.bit._ICR2 +#define ICR19_ICR1 icr19.bit._ICR1 +#define ICR19_ICR0 icr19.bit._ICR0 +__IO_EXTERN ICR20STR icr20; +#define ICR20 icr20.byte +#define ICR20_ICR4 icr20.bit._ICR4 +#define ICR20_ICR3 icr20.bit._ICR3 +#define ICR20_ICR2 icr20.bit._ICR2 +#define ICR20_ICR1 icr20.bit._ICR1 +#define ICR20_ICR0 icr20.bit._ICR0 +__IO_EXTERN ICR21STR icr21; +#define ICR21 icr21.byte +#define ICR21_ICR4 icr21.bit._ICR4 +#define ICR21_ICR3 icr21.bit._ICR3 +#define ICR21_ICR2 icr21.bit._ICR2 +#define ICR21_ICR1 icr21.bit._ICR1 +#define ICR21_ICR0 icr21.bit._ICR0 +__IO_EXTERN ICR22STR icr22; +#define ICR22 icr22.byte +#define ICR22_ICR4 icr22.bit._ICR4 +#define ICR22_ICR3 icr22.bit._ICR3 +#define ICR22_ICR2 icr22.bit._ICR2 +#define ICR22_ICR1 icr22.bit._ICR1 +#define ICR22_ICR0 icr22.bit._ICR0 +__IO_EXTERN ICR23STR icr23; +#define ICR23 icr23.byte +#define ICR23_ICR4 icr23.bit._ICR4 +#define ICR23_ICR3 icr23.bit._ICR3 +#define ICR23_ICR2 icr23.bit._ICR2 +#define ICR23_ICR1 icr23.bit._ICR1 +#define ICR23_ICR0 icr23.bit._ICR0 +__IO_EXTERN ICR24STR icr24; +#define ICR24 icr24.byte +#define ICR24_ICR4 icr24.bit._ICR4 +#define ICR24_ICR3 icr24.bit._ICR3 +#define ICR24_ICR2 icr24.bit._ICR2 +#define ICR24_ICR1 icr24.bit._ICR1 +#define ICR24_ICR0 icr24.bit._ICR0 +__IO_EXTERN ICR25STR icr25; +#define ICR25 icr25.byte +#define ICR25_ICR4 icr25.bit._ICR4 +#define ICR25_ICR3 icr25.bit._ICR3 +#define ICR25_ICR2 icr25.bit._ICR2 +#define ICR25_ICR1 icr25.bit._ICR1 +#define ICR25_ICR0 icr25.bit._ICR0 +__IO_EXTERN ICR26STR icr26; +#define ICR26 icr26.byte +#define ICR26_ICR4 icr26.bit._ICR4 +#define ICR26_ICR3 icr26.bit._ICR3 +#define ICR26_ICR2 icr26.bit._ICR2 +#define ICR26_ICR1 icr26.bit._ICR1 +#define ICR26_ICR0 icr26.bit._ICR0 +__IO_EXTERN ICR27STR icr27; +#define ICR27 icr27.byte +#define ICR27_ICR4 icr27.bit._ICR4 +#define ICR27_ICR3 icr27.bit._ICR3 +#define ICR27_ICR2 icr27.bit._ICR2 +#define ICR27_ICR1 icr27.bit._ICR1 +#define ICR27_ICR0 icr27.bit._ICR0 +__IO_EXTERN ICR28STR icr28; +#define ICR28 icr28.byte +#define ICR28_ICR4 icr28.bit._ICR4 +#define ICR28_ICR3 icr28.bit._ICR3 +#define ICR28_ICR2 icr28.bit._ICR2 +#define ICR28_ICR1 icr28.bit._ICR1 +#define ICR28_ICR0 icr28.bit._ICR0 +__IO_EXTERN ICR29STR icr29; +#define ICR29 icr29.byte +#define ICR29_ICR4 icr29.bit._ICR4 +#define ICR29_ICR3 icr29.bit._ICR3 +#define ICR29_ICR2 icr29.bit._ICR2 +#define ICR29_ICR1 icr29.bit._ICR1 +#define ICR29_ICR0 icr29.bit._ICR0 +__IO_EXTERN ICR30STR icr30; +#define ICR30 icr30.byte +#define ICR30_ICR4 icr30.bit._ICR4 +#define ICR30_ICR3 icr30.bit._ICR3 +#define ICR30_ICR2 icr30.bit._ICR2 +#define ICR30_ICR1 icr30.bit._ICR1 +#define ICR30_ICR0 icr30.bit._ICR0 +__IO_EXTERN ICR31STR icr31; +#define ICR31 icr31.byte +#define ICR31_ICR4 icr31.bit._ICR4 +#define ICR31_ICR3 icr31.bit._ICR3 +#define ICR31_ICR2 icr31.bit._ICR2 +#define ICR31_ICR1 icr31.bit._ICR1 +#define ICR31_ICR0 icr31.bit._ICR0 +__IO_EXTERN ICR32STR icr32; +#define ICR32 icr32.byte +#define ICR32_ICR4 icr32.bit._ICR4 +#define ICR32_ICR3 icr32.bit._ICR3 +#define ICR32_ICR2 icr32.bit._ICR2 +#define ICR32_ICR1 icr32.bit._ICR1 +#define ICR32_ICR0 icr32.bit._ICR0 +__IO_EXTERN ICR33STR icr33; +#define ICR33 icr33.byte +#define ICR33_ICR4 icr33.bit._ICR4 +#define ICR33_ICR3 icr33.bit._ICR3 +#define ICR33_ICR2 icr33.bit._ICR2 +#define ICR33_ICR1 icr33.bit._ICR1 +#define ICR33_ICR0 icr33.bit._ICR0 +__IO_EXTERN ICR34STR icr34; +#define ICR34 icr34.byte +#define ICR34_ICR4 icr34.bit._ICR4 +#define ICR34_ICR3 icr34.bit._ICR3 +#define ICR34_ICR2 icr34.bit._ICR2 +#define ICR34_ICR1 icr34.bit._ICR1 +#define ICR34_ICR0 icr34.bit._ICR0 +__IO_EXTERN ICR35STR icr35; +#define ICR35 icr35.byte +#define ICR35_ICR4 icr35.bit._ICR4 +#define ICR35_ICR3 icr35.bit._ICR3 +#define ICR35_ICR2 icr35.bit._ICR2 +#define ICR35_ICR1 icr35.bit._ICR1 +#define ICR35_ICR0 icr35.bit._ICR0 +__IO_EXTERN ICR36STR icr36; +#define ICR36 icr36.byte +#define ICR36_ICR4 icr36.bit._ICR4 +#define ICR36_ICR3 icr36.bit._ICR3 +#define ICR36_ICR2 icr36.bit._ICR2 +#define ICR36_ICR1 icr36.bit._ICR1 +#define ICR36_ICR0 icr36.bit._ICR0 +__IO_EXTERN ICR37STR icr37; +#define ICR37 icr37.byte +#define ICR37_ICR4 icr37.bit._ICR4 +#define ICR37_ICR3 icr37.bit._ICR3 +#define ICR37_ICR2 icr37.bit._ICR2 +#define ICR37_ICR1 icr37.bit._ICR1 +#define ICR37_ICR0 icr37.bit._ICR0 +__IO_EXTERN ICR38STR icr38; +#define ICR38 icr38.byte +#define ICR38_ICR4 icr38.bit._ICR4 +#define ICR38_ICR3 icr38.bit._ICR3 +#define ICR38_ICR2 icr38.bit._ICR2 +#define ICR38_ICR1 icr38.bit._ICR1 +#define ICR38_ICR0 icr38.bit._ICR0 +__IO_EXTERN ICR39STR icr39; +#define ICR39 icr39.byte +#define ICR39_ICR4 icr39.bit._ICR4 +#define ICR39_ICR3 icr39.bit._ICR3 +#define ICR39_ICR2 icr39.bit._ICR2 +#define ICR39_ICR1 icr39.bit._ICR1 +#define ICR39_ICR0 icr39.bit._ICR0 +__IO_EXTERN ICR40STR icr40; +#define ICR40 icr40.byte +#define ICR40_ICR4 icr40.bit._ICR4 +#define ICR40_ICR3 icr40.bit._ICR3 +#define ICR40_ICR2 icr40.bit._ICR2 +#define ICR40_ICR1 icr40.bit._ICR1 +#define ICR40_ICR0 icr40.bit._ICR0 +__IO_EXTERN ICR41STR icr41; +#define ICR41 icr41.byte +#define ICR41_ICR4 icr41.bit._ICR4 +#define ICR41_ICR3 icr41.bit._ICR3 +#define ICR41_ICR2 icr41.bit._ICR2 +#define ICR41_ICR1 icr41.bit._ICR1 +#define ICR41_ICR0 icr41.bit._ICR0 +__IO_EXTERN ICR42STR icr42; +#define ICR42 icr42.byte +#define ICR42_ICR4 icr42.bit._ICR4 +#define ICR42_ICR3 icr42.bit._ICR3 +#define ICR42_ICR2 icr42.bit._ICR2 +#define ICR42_ICR1 icr42.bit._ICR1 +#define ICR42_ICR0 icr42.bit._ICR0 +__IO_EXTERN ICR43STR icr43; +#define ICR43 icr43.byte +#define ICR43_ICR4 icr43.bit._ICR4 +#define ICR43_ICR3 icr43.bit._ICR3 +#define ICR43_ICR2 icr43.bit._ICR2 +#define ICR43_ICR1 icr43.bit._ICR1 +#define ICR43_ICR0 icr43.bit._ICR0 +__IO_EXTERN ICR44STR icr44; +#define ICR44 icr44.byte +#define ICR44_ICR4 icr44.bit._ICR4 +#define ICR44_ICR3 icr44.bit._ICR3 +#define ICR44_ICR2 icr44.bit._ICR2 +#define ICR44_ICR1 icr44.bit._ICR1 +#define ICR44_ICR0 icr44.bit._ICR0 +__IO_EXTERN ICR45STR icr45; +#define ICR45 icr45.byte +#define ICR45_ICR4 icr45.bit._ICR4 +#define ICR45_ICR3 icr45.bit._ICR3 +#define ICR45_ICR2 icr45.bit._ICR2 +#define ICR45_ICR1 icr45.bit._ICR1 +#define ICR45_ICR0 icr45.bit._ICR0 +__IO_EXTERN ICR46STR icr46; +#define ICR46 icr46.byte +#define ICR46_ICR4 icr46.bit._ICR4 +#define ICR46_ICR3 icr46.bit._ICR3 +#define ICR46_ICR2 icr46.bit._ICR2 +#define ICR46_ICR1 icr46.bit._ICR1 +#define ICR46_ICR0 icr46.bit._ICR0 +__IO_EXTERN ICR47STR icr47; +#define ICR47 icr47.byte +#define ICR47_ICR4 icr47.bit._ICR4 +#define ICR47_ICR3 icr47.bit._ICR3 +#define ICR47_ICR2 icr47.bit._ICR2 +#define ICR47_ICR1 icr47.bit._ICR1 +#define ICR47_ICR0 icr47.bit._ICR0 +__IO_EXTERN ICR48STR icr48; +#define ICR48 icr48.byte +#define ICR48_ICR4 icr48.bit._ICR4 +#define ICR48_ICR3 icr48.bit._ICR3 +#define ICR48_ICR2 icr48.bit._ICR2 +#define ICR48_ICR1 icr48.bit._ICR1 +#define ICR48_ICR0 icr48.bit._ICR0 +__IO_EXTERN ICR49STR icr49; +#define ICR49 icr49.byte +#define ICR49_ICR4 icr49.bit._ICR4 +#define ICR49_ICR3 icr49.bit._ICR3 +#define ICR49_ICR2 icr49.bit._ICR2 +#define ICR49_ICR1 icr49.bit._ICR1 +#define ICR49_ICR0 icr49.bit._ICR0 +__IO_EXTERN ICR50STR icr50; +#define ICR50 icr50.byte +#define ICR50_ICR4 icr50.bit._ICR4 +#define ICR50_ICR3 icr50.bit._ICR3 +#define ICR50_ICR2 icr50.bit._ICR2 +#define ICR50_ICR1 icr50.bit._ICR1 +#define ICR50_ICR0 icr50.bit._ICR0 +__IO_EXTERN ICR51STR icr51; +#define ICR51 icr51.byte +#define ICR51_ICR4 icr51.bit._ICR4 +#define ICR51_ICR3 icr51.bit._ICR3 +#define ICR51_ICR2 icr51.bit._ICR2 +#define ICR51_ICR1 icr51.bit._ICR1 +#define ICR51_ICR0 icr51.bit._ICR0 +__IO_EXTERN ICR52STR icr52; +#define ICR52 icr52.byte +#define ICR52_ICR4 icr52.bit._ICR4 +#define ICR52_ICR3 icr52.bit._ICR3 +#define ICR52_ICR2 icr52.bit._ICR2 +#define ICR52_ICR1 icr52.bit._ICR1 +#define ICR52_ICR0 icr52.bit._ICR0 +__IO_EXTERN ICR53STR icr53; +#define ICR53 icr53.byte +#define ICR53_ICR4 icr53.bit._ICR4 +#define ICR53_ICR3 icr53.bit._ICR3 +#define ICR53_ICR2 icr53.bit._ICR2 +#define ICR53_ICR1 icr53.bit._ICR1 +#define ICR53_ICR0 icr53.bit._ICR0 +__IO_EXTERN ICR54STR icr54; +#define ICR54 icr54.byte +#define ICR54_ICR4 icr54.bit._ICR4 +#define ICR54_ICR3 icr54.bit._ICR3 +#define ICR54_ICR2 icr54.bit._ICR2 +#define ICR54_ICR1 icr54.bit._ICR1 +#define ICR54_ICR0 icr54.bit._ICR0 +__IO_EXTERN ICR55STR icr55; +#define ICR55 icr55.byte +#define ICR55_ICR4 icr55.bit._ICR4 +#define ICR55_ICR3 icr55.bit._ICR3 +#define ICR55_ICR2 icr55.bit._ICR2 +#define ICR55_ICR1 icr55.bit._ICR1 +#define ICR55_ICR0 icr55.bit._ICR0 +__IO_EXTERN ICR56STR icr56; +#define ICR56 icr56.byte +#define ICR56_ICR4 icr56.bit._ICR4 +#define ICR56_ICR3 icr56.bit._ICR3 +#define ICR56_ICR2 icr56.bit._ICR2 +#define ICR56_ICR1 icr56.bit._ICR1 +#define ICR56_ICR0 icr56.bit._ICR0 +__IO_EXTERN ICR57STR icr57; +#define ICR57 icr57.byte +#define ICR57_ICR4 icr57.bit._ICR4 +#define ICR57_ICR3 icr57.bit._ICR3 +#define ICR57_ICR2 icr57.bit._ICR2 +#define ICR57_ICR1 icr57.bit._ICR1 +#define ICR57_ICR0 icr57.bit._ICR0 +__IO_EXTERN ICR58STR icr58; +#define ICR58 icr58.byte +#define ICR58_ICR4 icr58.bit._ICR4 +#define ICR58_ICR3 icr58.bit._ICR3 +#define ICR58_ICR2 icr58.bit._ICR2 +#define ICR58_ICR1 icr58.bit._ICR1 +#define ICR58_ICR0 icr58.bit._ICR0 +__IO_EXTERN ICR59STR icr59; +#define ICR59 icr59.byte +#define ICR59_ICR4 icr59.bit._ICR4 +#define ICR59_ICR3 icr59.bit._ICR3 +#define ICR59_ICR2 icr59.bit._ICR2 +#define ICR59_ICR1 icr59.bit._ICR1 +#define ICR59_ICR0 icr59.bit._ICR0 +__IO_EXTERN ICR60STR icr60; +#define ICR60 icr60.byte +#define ICR60_ICR4 icr60.bit._ICR4 +#define ICR60_ICR3 icr60.bit._ICR3 +#define ICR60_ICR2 icr60.bit._ICR2 +#define ICR60_ICR1 icr60.bit._ICR1 +#define ICR60_ICR0 icr60.bit._ICR0 +__IO_EXTERN ICR61STR icr61; +#define ICR61 icr61.byte +#define ICR61_ICR4 icr61.bit._ICR4 +#define ICR61_ICR3 icr61.bit._ICR3 +#define ICR61_ICR2 icr61.bit._ICR2 +#define ICR61_ICR1 icr61.bit._ICR1 +#define ICR61_ICR0 icr61.bit._ICR0 +__IO_EXTERN ICR62STR icr62; +#define ICR62 icr62.byte +#define ICR62_ICR4 icr62.bit._ICR4 +#define ICR62_ICR3 icr62.bit._ICR3 +#define ICR62_ICR2 icr62.bit._ICR2 +#define ICR62_ICR1 icr62.bit._ICR1 +#define ICR62_ICR0 icr62.bit._ICR0 +__IO_EXTERN ICR63STR icr63; +#define ICR63 icr63.byte +#define ICR63_ICR4 icr63.bit._ICR4 +#define ICR63_ICR3 icr63.bit._ICR3 +#define ICR63_ICR2 icr63.bit._ICR2 +#define ICR63_ICR1 icr63.bit._ICR1 +#define ICR63_ICR0 icr63.bit._ICR0 +__IO_EXTERN RSRRSTR rsrr; /* Clock Control Unit */ +#define RSRR rsrr.byte +#define RSRR_INIT rsrr.bit._INIT +#define RSRR_HSTB rsrr.bit._HSTB +#define RSRR_WDOG rsrr.bit._WDOG +#define RSRR_ERST rsrr.bit._ERST +#define RSRR_SRST rsrr.bit._SRST +#define RSRR_LINIT rsrr.bit._LINIT +#define RSRR_WT1 rsrr.bit._WT1 +#define RSRR_WT0 rsrr.bit._WT0 +#define RSRR_WT rsrr.bitc._WT +__IO_EXTERN STCRSTR stcr; +#define STCR stcr.byte +#define STCR_STOP stcr.bit._STOP +#define STCR_SLEEP stcr.bit._SLEEP +#define STCR_HIZ stcr.bit._HIZ +#define STCR_SRST stcr.bit._SRST +#define STCR_OS1 stcr.bit._OS1 +#define STCR_OS0 stcr.bit._OS0 +#define STCR_OSCD2 stcr.bit._OSCD2 +#define STCR_OSCD1 stcr.bit._OSCD1 +#define STCR_OS stcr.bitc._OS +#define STCR_OSCD stcr.bitc._OSCD +__IO_EXTERN TBCRSTR tbcr; +#define TBCR tbcr.byte +#define TBCR_TBIF tbcr.bit._TBIF +#define TBCR_TBIE tbcr.bit._TBIE +#define TBCR_TBC2 tbcr.bit._TBC2 +#define TBCR_TBC1 tbcr.bit._TBC1 +#define TBCR_TBC0 tbcr.bit._TBC0 +#define TBCR_SYNCR tbcr.bit._SYNCR +#define TBCR_SYNCS tbcr.bit._SYNCS +#define TBCR_TBC tbcr.bitc._TBC +__IO_EXTERN CTBRSTR ctbr; +#define CTBR ctbr.byte +#define CTBR_D7 ctbr.bit._D7 +#define CTBR_D6 ctbr.bit._D6 +#define CTBR_D5 ctbr.bit._D5 +#define CTBR_D4 ctbr.bit._D4 +#define CTBR_D3 ctbr.bit._D3 +#define CTBR_D2 ctbr.bit._D2 +#define CTBR_D1 ctbr.bit._D1 +#define CTBR_D0 ctbr.bit._D0 +__IO_EXTERN CLKRSTR clkr; +#define CLKR clkr.byte +#define CLKR_SCKEN clkr.bit._SCKEN +#define CLKR_PLL1EN clkr.bit._PLL1EN +#define CLKR_CLKS1 clkr.bit._CLKS1 +#define CLKR_CLKS0 clkr.bit._CLKS0 +#define CLKR_CLKS clkr.bitc._CLKS +/* include : INC460_CLKR.INC */ +/*-------------------------------------------------------------------*/ +/* INC460.INC : Old bit name of CLKR */ + +/* alias macro definition for CLKR*/ +#define CLKR_PLL2EN clkr.bit._SCKEN +/*-------------------------------------------------------------------*/ +__IO_EXTERN WPRSTR wpr; +#define WPR wpr.byte +#define WPR_D7 wpr.bit._D7 +#define WPR_D6 wpr.bit._D6 +#define WPR_D5 wpr.bit._D5 +#define WPR_D4 wpr.bit._D4 +#define WPR_D3 wpr.bit._D3 +#define WPR_D2 wpr.bit._D2 +#define WPR_D1 wpr.bit._D1 +#define WPR_D0 wpr.bit._D0 +__IO_EXTERN DIVR0STR divr0; +#define DIVR0 divr0.byte +#define DIVR0_B3 divr0.bit._B3 +#define DIVR0_B2 divr0.bit._B2 +#define DIVR0_B1 divr0.bit._B1 +#define DIVR0_B0 divr0.bit._B0 +#define DIVR0_P3 divr0.bit._P3 +#define DIVR0_P2 divr0.bit._P2 +#define DIVR0_P1 divr0.bit._P1 +#define DIVR0_P0 divr0.bit._P0 +#define DIVR0_B divr0.bitc._B +#define DIVR0_P divr0.bitc._P +__IO_EXTERN DIVR1STR divr1; +#define DIVR1 divr1.byte +#define DIVR1_T3 divr1.bit._T3 +#define DIVR1_T2 divr1.bit._T2 +#define DIVR1_T1 divr1.bit._T1 +#define DIVR1_T0 divr1.bit._T0 +#define DIVR1_T divr1.bitc._T +__IO_EXTERN PLLDIVMSTR plldivm; /* PLL - Clock Gear Unit: */ +#define PLLDIVM plldivm.byte +#define PLLDIVM_DVM3 plldivm.bit._DVM3 +#define PLLDIVM_DVM2 plldivm.bit._DVM2 +#define PLLDIVM_DVM1 plldivm.bit._DVM1 +#define PLLDIVM_DVM0 plldivm.bit._DVM0 +#define PLLDIVM_DVM plldivm.bitc._DVM +__IO_EXTERN PLLDIVNSTR plldivn; +#define PLLDIVN plldivn.byte +#define PLLDIVN_DVN5 plldivn.bit._DVN5 +#define PLLDIVN_DVN4 plldivn.bit._DVN4 +#define PLLDIVN_DVN3 plldivn.bit._DVN3 +#define PLLDIVN_DVN2 plldivn.bit._DVN2 +#define PLLDIVN_DVN1 plldivn.bit._DVN1 +#define PLLDIVN_DVN0 plldivn.bit._DVN0 +#define PLLDIVN_DVN plldivn.bitc._DVN +__IO_EXTERN PLLDIVGSTR plldivg; +#define PLLDIVG plldivg.byte +#define PLLDIVG_DVG3 plldivg.bit._DVG3 +#define PLLDIVG_DVG2 plldivg.bit._DVG2 +#define PLLDIVG_DVG1 plldivg.bit._DVG1 +#define PLLDIVG_DVG0 plldivg.bit._DVG0 +#define PLLDIVG_DVG plldivg.bitc._DVG +__IO_EXTERN PLLMULGSTR pllmulg; +#define PLLMULG pllmulg.byte +#define PLLMULG_MLG7 pllmulg.bit._MLG7 +#define PLLMULG_MLG6 pllmulg.bit._MLG6 +#define PLLMULG_MLG5 pllmulg.bit._MLG5 +#define PLLMULG_MLG4 pllmulg.bit._MLG4 +#define PLLMULG_MLG3 pllmulg.bit._MLG3 +#define PLLMULG_MLG2 pllmulg.bit._MLG2 +#define PLLMULG_MLG1 pllmulg.bit._MLG1 +#define PLLMULG_MLG0 pllmulg.bit._MLG0 +#define PLLMULG_MLG pllmulg.bitc._MLG +__IO_EXTERN PLLCTRLSTR pllctrl; +#define PLLCTRL pllctrl.byte +#define PLLCTRL_IEDN pllctrl.bit._IEDN +#define PLLCTRL_GRDN pllctrl.bit._GRDN +#define PLLCTRL_IEUP pllctrl.bit._IEUP +#define PLLCTRL_GRUP pllctrl.bit._GRUP +__IO_EXTERN OSCC1STR oscc1; /* Main/Sub Oscillator Control */ +#define OSCC1 oscc1.byte +#define OSCC1_FCI oscc1.bit._FCI +#define OSCC1_RFBEN oscc1.bit._RFBEN +#define OSCC1_OSCR oscc1.bit._OSCR +__IO_EXTERN OSCS1STR oscs1; +#define OSCS1 oscs1.byte +#define OSCS1_OSCS7 oscs1.bit._OSCS7 +#define OSCS1_OSCS6 oscs1.bit._OSCS6 +#define OSCS1_OSCS5 oscs1.bit._OSCS5 +#define OSCS1_OSCS4 oscs1.bit._OSCS4 +#define OSCS1_OSCS3 oscs1.bit._OSCS3 +#define OSCS1_OSCS2 oscs1.bit._OSCS2 +#define OSCS1_OSCS1 oscs1.bit._OSCS1 +#define OSCS1_OSCS0 oscs1.bit._OSCS0 +__IO_EXTERN OSCC2STR oscc2; +#define OSCC2 oscc2.byte +#define OSCC2_FCI oscc2.bit._FCI +#define OSCC2_RFBEN oscc2.bit._RFBEN +#define OSCC2_OSCR oscc2.bit._OSCR +__IO_EXTERN OSCS2STR oscs2; +#define OSCS2 oscs2.byte +#define OSCS2_OSCS7 oscs2.bit._OSCS7 +#define OSCS2_OSCS6 oscs2.bit._OSCS6 +#define OSCS2_OSCS5 oscs2.bit._OSCS5 +#define OSCS2_OSCS4 oscs2.bit._OSCS4 +#define OSCS2_OSCS3 oscs2.bit._OSCS3 +#define OSCS2_OSCS2 oscs2.bit._OSCS2 +#define OSCS2_OSCS1 oscs2.bit._OSCS1 +#define OSCS2_OSCS0 oscs2.bit._OSCS0 +__IO_EXTERN PORTENSTR porten; /* Port Input Enable Control */ +#define PORTEN porten.byte +#define PORTEN_CPORTEN porten.bit._CPORTEN +#define PORTEN_GPORTEN porten.bit._GPORTEN +__IO_EXTERN WTCERSTR wtcer; /* Real Time Clock (Watch Timer) */ +#define WTCER wtcer.byte +#define WTCER_INTE4 wtcer.bit._INTE4 +#define WTCER_INT4 wtcer.bit._INT4 +__IO_EXTERN WTCRSTR wtcr; +#define WTCR wtcr.word +#define WTCR_INTE3 wtcr.bit._INTE3 +#define WTCR_INT3 wtcr.bit._INT3 +#define WTCR_INTE2 wtcr.bit._INTE2 +#define WTCR_INT2 wtcr.bit._INT2 +#define WTCR_INTE1 wtcr.bit._INTE1 +#define WTCR_INT1 wtcr.bit._INT1 +#define WTCR_INTE0 wtcr.bit._INTE0 +#define WTCR_INT0 wtcr.bit._INT0 +#define WTCR_RUN wtcr.bit._RUN +#define WTCR_UPDT wtcr.bit._UPDT +#define WTCR_ST wtcr.bit._ST +__IO_EXTERN WTBRSTR wtbr; +#define WTBR wtbr.lword +#define WTBR_D20 wtbr.bit._D20 +#define WTBR_D19 wtbr.bit._D19 +#define WTBR_D18 wtbr.bit._D18 +#define WTBR_D17 wtbr.bit._D17 +#define WTBR_D16 wtbr.bit._D16 +#define WTBR_D15 wtbr.bit._D15 +#define WTBR_D14 wtbr.bit._D14 +#define WTBR_D13 wtbr.bit._D13 +#define WTBR_D12 wtbr.bit._D12 +#define WTBR_D11 wtbr.bit._D11 +#define WTBR_D10 wtbr.bit._D10 +#define WTBR_D9 wtbr.bit._D9 +#define WTBR_D8 wtbr.bit._D8 +#define WTBR_D7 wtbr.bit._D7 +#define WTBR_D6 wtbr.bit._D6 +#define WTBR_D5 wtbr.bit._D5 +#define WTBR_D4 wtbr.bit._D4 +#define WTBR_D3 wtbr.bit._D3 +#define WTBR_D2 wtbr.bit._D2 +#define WTBR_D1 wtbr.bit._D1 +#define WTBR_D0 wtbr.bit._D0 +__IO_EXTERN WTHRSTR wthr; +#define WTHR wthr.byte +#define WTHR_H4 wthr.bit._H4 +#define WTHR_H3 wthr.bit._H3 +#define WTHR_H2 wthr.bit._H2 +#define WTHR_H1 wthr.bit._H1 +#define WTHR_H0 wthr.bit._H0 +__IO_EXTERN WTMRSTR wtmr; +#define WTMR wtmr.byte +#define WTMR_M5 wtmr.bit._M5 +#define WTMR_M4 wtmr.bit._M4 +#define WTMR_M3 wtmr.bit._M3 +#define WTMR_M2 wtmr.bit._M2 +#define WTMR_M1 wtmr.bit._M1 +#define WTMR_M0 wtmr.bit._M0 +__IO_EXTERN WTSRSTR wtsr; +#define WTSR wtsr.byte +#define WTSR_S5 wtsr.bit._S5 +#define WTSR_S4 wtsr.bit._S4 +#define WTSR_S3 wtsr.bit._S3 +#define WTSR_S2 wtsr.bit._S2 +#define WTSR_S1 wtsr.bit._S1 +#define WTSR_S0 wtsr.bit._S0 +__IO_EXTERN IO_BYTE csvtr; /* Clock-Supervisor / Selecor / Monitor */ +#define CSVTR csvtr +__IO_EXTERN CSVCRSTR csvcr; +#define CSVCR csvcr.byte +#define CSVCR_SCKS csvcr.bit._SCKS +#define CSVCR_MM csvcr.bit._MM +#define CSVCR_SM csvcr.bit._SM +#define CSVCR_RCE csvcr.bit._RCE +#define CSVCR_MSVE csvcr.bit._MSVE +#define CSVCR_SSVE csvcr.bit._SSVE +#define CSVCR_SRST csvcr.bit._SRST +#define CSVCR_OUTE csvcr.bit._OUTE +__IO_EXTERN CSCFGSTR cscfg; +#define CSCFG cscfg.byte +#define CSCFG_EDSUEN cscfg.bit._EDSUEN +#define CSCFG_PLLLOCK cscfg.bit._PLLLOCK +#define CSCFG_RCSEL cscfg.bit._RCSEL +#define CSCFG_MONCKI cscfg.bit._MONCKI +#define CSCFG_CSC3 cscfg.bit._CSC3 +#define CSCFG_CSC2 cscfg.bit._CSC2 +#define CSCFG_CSC1 cscfg.bit._CSC1 +#define CSCFG_CSC0 cscfg.bit._CSC0 +#define CSCFG_CSC cscfg.bitc._CSC +__IO_EXTERN CMCFGSTR cmcfg; +#define CMCFG cmcfg.byte +#define CMCFG_CMPRE3 cmcfg.bit._CMPRE3 +#define CMCFG_CMPRE2 cmcfg.bit._CMPRE2 +#define CMCFG_CMPRE1 cmcfg.bit._CMPRE1 +#define CMCFG_CMPRE0 cmcfg.bit._CMPRE0 +#define CMCFG_CMSEL3 cmcfg.bit._CMSEL3 +#define CMCFG_CMSEL2 cmcfg.bit._CMSEL2 +#define CMCFG_CMSEL1 cmcfg.bit._CMSEL1 +#define CMCFG_CMSEL0 cmcfg.bit._CMSEL0 +#define CMCFG_CMPRE cmcfg.bitc._CMPRE +#define CMCFG_CMSEL cmcfg.bitc._CMSEL +/* include : INC460_CSV.INC */ +/*-------------------------------------------------------------------*/ +/* INC460.DMAC : Old bit name of CSV */ + +/* alias macro definition for CSV */ +#define CSVCR_MS csvcr.bit._SM +#define CSVCR_REC csvcr.bit._RCE +/*-------------------------------------------------------------------*/ +__IO_EXTERN CUCRSTR cucr; /* Calibration Unit of Sub Oszillation */ +#define CUCR cucr.word +#define CUCR_STRT cucr.bit._STRT +#define CUCR_INT cucr.bit._INT +#define CUCR_INTEN cucr.bit._INTEN +__IO_EXTERN CUTDSTR cutd; +#define CUTD cutd.word +#define CUTD_TDD15 cutd.bit._TDD15 +#define CUTD_TDD14 cutd.bit._TDD14 +#define CUTD_TDD13 cutd.bit._TDD13 +#define CUTD_TDD12 cutd.bit._TDD12 +#define CUTD_TDD11 cutd.bit._TDD11 +#define CUTD_TDD10 cutd.bit._TDD10 +#define CUTD_TDD9 cutd.bit._TDD9 +#define CUTD_TDD8 cutd.bit._TDD8 +#define CUTD_TDD7 cutd.bit._TDD7 +#define CUTD_TDD6 cutd.bit._TDD6 +#define CUTD_TDD5 cutd.bit._TDD5 +#define CUTD_TDD4 cutd.bit._TDD4 +#define CUTD_TDD3 cutd.bit._TDD3 +#define CUTD_TDD2 cutd.bit._TDD2 +#define CUTD_TDD1 cutd.bit._TDD1 +#define CUTD_TDD0 cutd.bit._TDD0 +__IO_EXTERN CUTR1STR cutr1; +#define CUTR1 cutr1.word +#define CUTR1_TDR23 cutr1.bit._TDR23 +#define CUTR1_TDR22 cutr1.bit._TDR22 +#define CUTR1_TDR21 cutr1.bit._TDR21 +#define CUTR1_TDR20 cutr1.bit._TDR20 +#define CUTR1_TDR19 cutr1.bit._TDR19 +#define CUTR1_TDR18 cutr1.bit._TDR18 +#define CUTR1_TDR17 cutr1.bit._TDR17 +#define CUTR1_TDR16 cutr1.bit._TDR16 +__IO_EXTERN CUTR2STR cutr2; +#define CUTR2 cutr2.word +#define CUTR2_TDR15 cutr2.bit._TDR15 +#define CUTR2_TDR14 cutr2.bit._TDR14 +#define CUTR2_TDR13 cutr2.bit._TDR13 +#define CUTR2_TDR12 cutr2.bit._TDR12 +#define CUTR2_TDR11 cutr2.bit._TDR11 +#define CUTR2_TDR10 cutr2.bit._TDR10 +#define CUTR2_TDR9 cutr2.bit._TDR9 +#define CUTR2_TDR8 cutr2.bit._TDR8 +#define CUTR2_TDR7 cutr2.bit._TDR7 +#define CUTR2_TDR6 cutr2.bit._TDR6 +#define CUTR2_TDR5 cutr2.bit._TDR5 +#define CUTR2_TDR4 cutr2.bit._TDR4 +#define CUTR2_TDR3 cutr2.bit._TDR3 +#define CUTR2_TDR2 cutr2.bit._TDR2 +#define CUTR2_TDR1 cutr2.bit._TDR1 +#define CUTR2_TDR0 cutr2.bit._TDR0 +__IO_EXTERN CMPRSTR cmpr; /* Clock Modulator */ +#define CMPR cmpr.word +#define CMPR_MP13 cmpr.bit._MP13 +#define CMPR_MP12 cmpr.bit._MP12 +#define CMPR_MP11 cmpr.bit._MP11 +#define CMPR_MP10 cmpr.bit._MP10 +#define CMPR_MP9 cmpr.bit._MP9 +#define CMPR_MP8 cmpr.bit._MP8 +#define CMPR_MP7 cmpr.bit._MP7 +#define CMPR_MP6 cmpr.bit._MP6 +#define CMPR_MP5 cmpr.bit._MP5 +#define CMPR_MP4 cmpr.bit._MP4 +#define CMPR_MP3 cmpr.bit._MP3 +#define CMPR_MP2 cmpr.bit._MP2 +#define CMPR_MP1 cmpr.bit._MP1 +#define CMPR_MP0 cmpr.bit._MP0 +__IO_EXTERN CMCRSTR cmcr; +#define CMCR cmcr.byte +#define CMCR_FMODRUN cmcr.bit._FMODRUN +#define CMCR_FMOD cmcr.bit._FMOD +#define CMCR_PDX cmcr.bit._PDX +__IO_EXTERN IO_WORD cmt1; +#define CMT1 cmt1 +__IO_EXTERN IO_WORD cmt2; +#define CMT2 cmt2 +__IO_EXTERN CANPRESTR canpre; /* CAN clock control */ +#define CANPRE canpre.byte +#define CANPRE_CPCKS1 canpre.bit._CPCKS1 +#define CANPRE_CPCKS0 canpre.bit._CPCKS0 +#define CANPRE_DVC3 canpre.bit._DVC3 +#define CANPRE_DVC2 canpre.bit._DVC2 +#define CANPRE_DVC1 canpre.bit._DVC1 +#define CANPRE_DVC0 canpre.bit._DVC0 +#define CANPRE_CPCKS canpre.bitc._CPCKS +#define CANPRE_DVC canpre.bitc._DVC +__IO_EXTERN CANCKDSTR canckd; +#define CANCKD canckd.byte +#define CANCKD_CANCKD5 canckd.bit._CANCKD5 +#define CANCKD_CANCKD4 canckd.bit._CANCKD4 +#define CANCKD_CANCKD3 canckd.bit._CANCKD3 +#define CANCKD_CANCKD2 canckd.bit._CANCKD2 +#define CANCKD_CANCKD1 canckd.bit._CANCKD1 +#define CANCKD_CANCKD0 canckd.bit._CANCKD0 +__IO_EXTERN LVSELSTR lvsel; /* LV Detection / Hardware-Watchdog */ +#define LVSEL lvsel.byte +#define LVSEL_LVESEL3 lvsel.bit._LVESEL3 +#define LVSEL_LVESEL2 lvsel.bit._LVESEL2 +#define LVSEL_LVESEL1 lvsel.bit._LVESEL1 +#define LVSEL_LVESEL0 lvsel.bit._LVESEL0 +#define LVSEL_LVISEL3 lvsel.bit._LVISEL3 +#define LVSEL_LVISEL2 lvsel.bit._LVISEL2 +#define LVSEL_LVISEL1 lvsel.bit._LVISEL1 +#define LVSEL_LVISEL0 lvsel.bit._LVISEL0 +#define LVSEL_LVESEL lvsel.bitc._LVESEL +#define LVSEL_LVISEL lvsel.bitc._LVISEL +__IO_EXTERN LVDETSTR lvdet; +#define LVDET lvdet.byte +#define LVDET_LVSEL lvdet.bit._LVSEL +#define LVDET_LVEPD lvdet.bit._LVEPD +#define LVDET_LVIPD lvdet.bit._LVIPD +#define LVDET_LVREN lvdet.bit._LVREN +#define LVDET_LVIEN lvdet.bit._LVIEN +#define LVDET_LVIRQ lvdet.bit._LVIRQ +__IO_EXTERN HWWDESTR hwwde; +#define HWWDE hwwde.byte +#define HWWDE_ED1 hwwde.bit._ED1 +#define HWWDE_ED0 hwwde.bit._ED0 +#define HWWDE_ED hwwde.bitc._ED +__IO_EXTERN HWWDSTR hwwd; +#define HWWD hwwd.byte +#define HWWD_CL hwwd.bit._CL +#define HWWD_CPUF hwwd.bit._CPUF +__IO_EXTERN OSCRHSTR oscrh; /* Main-/Sub-Oscillatio Stabilization Timer */ +#define OSCRH oscrh.byte +#define OSCRH_WIF oscrh.bit._WIF +#define OSCRH_WIE oscrh.bit._WIE +#define OSCRH_WEN oscrh.bit._WEN +#define OSCRH_WS1 oscrh.bit._WS1 +#define OSCRH_WS0 oscrh.bit._WS0 +#define OSCRH_WCL oscrh.bit._WCL +#define OSCRH_WS oscrh.bitc._WS +__IO_EXTERN IO_BYTE oscrl; +#define OSCRL oscrl +__IO_EXTERN WPCRHSTR wpcrh; +#define WPCRH wpcrh.byte +#define WPCRH_WIF wpcrh.bit._WIF +#define WPCRH_WIE wpcrh.bit._WIE +#define WPCRH_WEN wpcrh.bit._WEN +#define WPCRH_WS1 wpcrh.bit._WS1 +#define WPCRH_WS0 wpcrh.bit._WS0 +#define WPCRH_WCL wpcrh.bit._WCL +#define WPCRH_WS wpcrh.bitc._WS +__IO_EXTERN IO_BYTE wpcrl; +#define WPCRL wpcrl +__IO_EXTERN OSCCRSTR osccr; /* Main-/Sub-Oscillatio Standby Control */ +#define OSCCR osccr.byte +#define OSCCR_OSCDS1 osccr.bit._OSCDS1 +__IO_EXTERN REGSELSTR regsel; +#define REGSEL regsel.byte +#define REGSEL_FLASHSEL regsel.bit._FLASHSEL +#define REGSEL_MAINSEL regsel.bit._MAINSEL +#define REGSEL_SUBSEL3 regsel.bit._SUBSEL3 +#define REGSEL_SUBSEL2 regsel.bit._SUBSEL2 +#define REGSEL_SUBSEL1 regsel.bit._SUBSEL1 +#define REGSEL_SUBSEL0 regsel.bit._SUBSEL0 +#define REGSEL_SUBSEL regsel.bitc._SUBSEL +__IO_EXTERN REGCTRSTR regctr; +#define REGCTR regctr.byte +#define REGCTR_MSTBO regctr.bit._MSTBO +#define REGCTR_MAINKPEN regctr.bit._MAINKPEN +#define REGCTR_MAINDSBL regctr.bit._MAINDSBL +__IO_EXTERN ASR0STR asr0; /* External Bus/Chip Select Registers */ +#define ASR0 asr0.word +#define ASR0_A31 asr0.bit._A31 +#define ASR0_A30 asr0.bit._A30 +#define ASR0_A29 asr0.bit._A29 +#define ASR0_A28 asr0.bit._A28 +#define ASR0_A27 asr0.bit._A27 +#define ASR0_A26 asr0.bit._A26 +#define ASR0_A25 asr0.bit._A25 +#define ASR0_A24 asr0.bit._A24 +#define ASR0_A23 asr0.bit._A23 +#define ASR0_A22 asr0.bit._A22 +#define ASR0_A21 asr0.bit._A21 +#define ASR0_A20 asr0.bit._A20 +#define ASR0_A19 asr0.bit._A19 +#define ASR0_A18 asr0.bit._A18 +#define ASR0_A17 asr0.bit._A17 +#define ASR0_A16 asr0.bit._A16 +__IO_EXTERN ACR0STR acr0; +#define ACR0 acr0.word +#define ACR0_ASZ3 acr0.bit._ASZ3 +#define ACR0_ASZ2 acr0.bit._ASZ2 +#define ACR0_ASZ1 acr0.bit._ASZ1 +#define ACR0_ASZ0 acr0.bit._ASZ0 +#define ACR0_DBW1 acr0.bit._DBW1 +#define ACR0_DBW0 acr0.bit._DBW0 +#define ACR0_BST1 acr0.bit._BST1 +#define ACR0_BST0 acr0.bit._BST0 +#define ACR0_SREN acr0.bit._SREN +#define ACR0_PFEN acr0.bit._PFEN +#define ACR0_WREN acr0.bit._WREN +#define ACR0_TYP3 acr0.bit._TYP3 +#define ACR0_TYP2 acr0.bit._TYP2 +#define ACR0_TYP1 acr0.bit._TYP1 +#define ACR0_TYP0 acr0.bit._TYP0 +#define ACR0_ASZ acr0.bitc._ASZ +#define ACR0_DBW acr0.bitc._DBW +#define ACR0_BST acr0.bitc._BST +#define ACR0_TYP acr0.bitc._TYP +__IO_EXTERN ASR1STR asr1; +#define ASR1 asr1.word +#define ASR1_A31 asr1.bit._A31 +#define ASR1_A30 asr1.bit._A30 +#define ASR1_A29 asr1.bit._A29 +#define ASR1_A28 asr1.bit._A28 +#define ASR1_A27 asr1.bit._A27 +#define ASR1_A26 asr1.bit._A26 +#define ASR1_A25 asr1.bit._A25 +#define ASR1_A24 asr1.bit._A24 +#define ASR1_A23 asr1.bit._A23 +#define ASR1_A22 asr1.bit._A22 +#define ASR1_A21 asr1.bit._A21 +#define ASR1_A20 asr1.bit._A20 +#define ASR1_A19 asr1.bit._A19 +#define ASR1_A18 asr1.bit._A18 +#define ASR1_A17 asr1.bit._A17 +#define ASR1_A16 asr1.bit._A16 +__IO_EXTERN ACR1STR acr1; +#define ACR1 acr1.word +#define ACR1_ASZ3 acr1.bit._ASZ3 +#define ACR1_ASZ2 acr1.bit._ASZ2 +#define ACR1_ASZ1 acr1.bit._ASZ1 +#define ACR1_ASZ0 acr1.bit._ASZ0 +#define ACR1_DBW1 acr1.bit._DBW1 +#define ACR1_DBW0 acr1.bit._DBW0 +#define ACR1_BST1 acr1.bit._BST1 +#define ACR1_BST0 acr1.bit._BST0 +#define ACR1_SREN acr1.bit._SREN +#define ACR1_PFEN acr1.bit._PFEN +#define ACR1_WREN acr1.bit._WREN +#define ACR1_LEND acr1.bit._LEND +#define ACR1_TYP3 acr1.bit._TYP3 +#define ACR1_TYP2 acr1.bit._TYP2 +#define ACR1_TYP1 acr1.bit._TYP1 +#define ACR1_TYP0 acr1.bit._TYP0 +#define ACR1_ASZ acr1.bitc._ASZ +#define ACR1_DBW acr1.bitc._DBW +#define ACR1_BST acr1.bitc._BST +#define ACR1_TYP acr1.bitc._TYP +__IO_EXTERN ASR2STR asr2; +#define ASR2 asr2.word +#define ASR2_A31 asr2.bit._A31 +#define ASR2_A30 asr2.bit._A30 +#define ASR2_A29 asr2.bit._A29 +#define ASR2_A28 asr2.bit._A28 +#define ASR2_A27 asr2.bit._A27 +#define ASR2_A26 asr2.bit._A26 +#define ASR2_A25 asr2.bit._A25 +#define ASR2_A24 asr2.bit._A24 +#define ASR2_A23 asr2.bit._A23 +#define ASR2_A22 asr2.bit._A22 +#define ASR2_A21 asr2.bit._A21 +#define ASR2_A20 asr2.bit._A20 +#define ASR2_A19 asr2.bit._A19 +#define ASR2_A18 asr2.bit._A18 +#define ASR2_A17 asr2.bit._A17 +#define ASR2_A16 asr2.bit._A16 +__IO_EXTERN ACR2STR acr2; +#define ACR2 acr2.word +#define ACR2_ASZ3 acr2.bit._ASZ3 +#define ACR2_ASZ2 acr2.bit._ASZ2 +#define ACR2_ASZ1 acr2.bit._ASZ1 +#define ACR2_ASZ0 acr2.bit._ASZ0 +#define ACR2_DBW1 acr2.bit._DBW1 +#define ACR2_DBW0 acr2.bit._DBW0 +#define ACR2_BST1 acr2.bit._BST1 +#define ACR2_BST0 acr2.bit._BST0 +#define ACR2_SREN acr2.bit._SREN +#define ACR2_PFEN acr2.bit._PFEN +#define ACR2_WREN acr2.bit._WREN +#define ACR2_LEND acr2.bit._LEND +#define ACR2_TYP3 acr2.bit._TYP3 +#define ACR2_TYP2 acr2.bit._TYP2 +#define ACR2_TYP1 acr2.bit._TYP1 +#define ACR2_TYP0 acr2.bit._TYP0 +#define ACR2_ASZ acr2.bitc._ASZ +#define ACR2_DBW acr2.bitc._DBW +#define ACR2_BST acr2.bitc._BST +#define ACR2_TYP acr2.bitc._TYP +__IO_EXTERN ASR3STR asr3; +#define ASR3 asr3.word +#define ASR3_A31 asr3.bit._A31 +#define ASR3_A30 asr3.bit._A30 +#define ASR3_A29 asr3.bit._A29 +#define ASR3_A28 asr3.bit._A28 +#define ASR3_A27 asr3.bit._A27 +#define ASR3_A26 asr3.bit._A26 +#define ASR3_A25 asr3.bit._A25 +#define ASR3_A24 asr3.bit._A24 +#define ASR3_A23 asr3.bit._A23 +#define ASR3_A22 asr3.bit._A22 +#define ASR3_A21 asr3.bit._A21 +#define ASR3_A20 asr3.bit._A20 +#define ASR3_A19 asr3.bit._A19 +#define ASR3_A18 asr3.bit._A18 +#define ASR3_A17 asr3.bit._A17 +#define ASR3_A16 asr3.bit._A16 +__IO_EXTERN ACR3STR acr3; +#define ACR3 acr3.word +#define ACR3_ASZ3 acr3.bit._ASZ3 +#define ACR3_ASZ2 acr3.bit._ASZ2 +#define ACR3_ASZ1 acr3.bit._ASZ1 +#define ACR3_ASZ0 acr3.bit._ASZ0 +#define ACR3_DBW1 acr3.bit._DBW1 +#define ACR3_DBW0 acr3.bit._DBW0 +#define ACR3_BST1 acr3.bit._BST1 +#define ACR3_BST0 acr3.bit._BST0 +#define ACR3_SREN acr3.bit._SREN +#define ACR3_PFEN acr3.bit._PFEN +#define ACR3_WREN acr3.bit._WREN +#define ACR3_LEND acr3.bit._LEND +#define ACR3_TYP3 acr3.bit._TYP3 +#define ACR3_TYP2 acr3.bit._TYP2 +#define ACR3_TYP1 acr3.bit._TYP1 +#define ACR3_TYP0 acr3.bit._TYP0 +#define ACR3_ASZ acr3.bitc._ASZ +#define ACR3_DBW acr3.bitc._DBW +#define ACR3_BST acr3.bitc._BST +#define ACR3_TYP acr3.bitc._TYP +__IO_EXTERN ASR4STR asr4; +#define ASR4 asr4.word +#define ASR4_A31 asr4.bit._A31 +#define ASR4_A30 asr4.bit._A30 +#define ASR4_A29 asr4.bit._A29 +#define ASR4_A28 asr4.bit._A28 +#define ASR4_A27 asr4.bit._A27 +#define ASR4_A26 asr4.bit._A26 +#define ASR4_A25 asr4.bit._A25 +#define ASR4_A24 asr4.bit._A24 +#define ASR4_A23 asr4.bit._A23 +#define ASR4_A22 asr4.bit._A22 +#define ASR4_A21 asr4.bit._A21 +#define ASR4_A20 asr4.bit._A20 +#define ASR4_A19 asr4.bit._A19 +#define ASR4_A18 asr4.bit._A18 +#define ASR4_A17 asr4.bit._A17 +#define ASR4_A16 asr4.bit._A16 +__IO_EXTERN ACR4STR acr4; +#define ACR4 acr4.word +#define ACR4_ASZ3 acr4.bit._ASZ3 +#define ACR4_ASZ2 acr4.bit._ASZ2 +#define ACR4_ASZ1 acr4.bit._ASZ1 +#define ACR4_ASZ0 acr4.bit._ASZ0 +#define ACR4_DBW1 acr4.bit._DBW1 +#define ACR4_DBW0 acr4.bit._DBW0 +#define ACR4_BST1 acr4.bit._BST1 +#define ACR4_BST0 acr4.bit._BST0 +#define ACR4_SREN acr4.bit._SREN +#define ACR4_PFEN acr4.bit._PFEN +#define ACR4_WREN acr4.bit._WREN +#define ACR4_LEND acr4.bit._LEND +#define ACR4_TYP3 acr4.bit._TYP3 +#define ACR4_TYP2 acr4.bit._TYP2 +#define ACR4_TYP1 acr4.bit._TYP1 +#define ACR4_TYP0 acr4.bit._TYP0 +#define ACR4_ASZ acr4.bitc._ASZ +#define ACR4_DBW acr4.bitc._DBW +#define ACR4_BST acr4.bitc._BST +#define ACR4_TYP acr4.bitc._TYP +__IO_EXTERN ASR5STR asr5; +#define ASR5 asr5.word +#define ASR5_A31 asr5.bit._A31 +#define ASR5_A30 asr5.bit._A30 +#define ASR5_A29 asr5.bit._A29 +#define ASR5_A28 asr5.bit._A28 +#define ASR5_A27 asr5.bit._A27 +#define ASR5_A26 asr5.bit._A26 +#define ASR5_A25 asr5.bit._A25 +#define ASR5_A24 asr5.bit._A24 +#define ASR5_A23 asr5.bit._A23 +#define ASR5_A22 asr5.bit._A22 +#define ASR5_A21 asr5.bit._A21 +#define ASR5_A20 asr5.bit._A20 +#define ASR5_A19 asr5.bit._A19 +#define ASR5_A18 asr5.bit._A18 +#define ASR5_A17 asr5.bit._A17 +#define ASR5_A16 asr5.bit._A16 +__IO_EXTERN ACR5STR acr5; +#define ACR5 acr5.word +#define ACR5_ASZ3 acr5.bit._ASZ3 +#define ACR5_ASZ2 acr5.bit._ASZ2 +#define ACR5_ASZ1 acr5.bit._ASZ1 +#define ACR5_ASZ0 acr5.bit._ASZ0 +#define ACR5_DBW1 acr5.bit._DBW1 +#define ACR5_DBW0 acr5.bit._DBW0 +#define ACR5_BST1 acr5.bit._BST1 +#define ACR5_BST0 acr5.bit._BST0 +#define ACR5_SREN acr5.bit._SREN +#define ACR5_PFEN acr5.bit._PFEN +#define ACR5_WREN acr5.bit._WREN +#define ACR5_LEND acr5.bit._LEND +#define ACR5_TYP3 acr5.bit._TYP3 +#define ACR5_TYP2 acr5.bit._TYP2 +#define ACR5_TYP1 acr5.bit._TYP1 +#define ACR5_TYP0 acr5.bit._TYP0 +#define ACR5_ASZ acr5.bitc._ASZ +#define ACR5_DBW acr5.bitc._DBW +#define ACR5_BST acr5.bitc._BST +#define ACR5_TYP acr5.bitc._TYP +__IO_EXTERN ASR6STR asr6; +#define ASR6 asr6.word +#define ASR6_A31 asr6.bit._A31 +#define ASR6_A30 asr6.bit._A30 +#define ASR6_A29 asr6.bit._A29 +#define ASR6_A28 asr6.bit._A28 +#define ASR6_A27 asr6.bit._A27 +#define ASR6_A26 asr6.bit._A26 +#define ASR6_A25 asr6.bit._A25 +#define ASR6_A24 asr6.bit._A24 +#define ASR6_A23 asr6.bit._A23 +#define ASR6_A22 asr6.bit._A22 +#define ASR6_A21 asr6.bit._A21 +#define ASR6_A20 asr6.bit._A20 +#define ASR6_A19 asr6.bit._A19 +#define ASR6_A18 asr6.bit._A18 +#define ASR6_A17 asr6.bit._A17 +#define ASR6_A16 asr6.bit._A16 +__IO_EXTERN ACR6STR acr6; +#define ACR6 acr6.word +#define ACR6_ASZ3 acr6.bit._ASZ3 +#define ACR6_ASZ2 acr6.bit._ASZ2 +#define ACR6_ASZ1 acr6.bit._ASZ1 +#define ACR6_ASZ0 acr6.bit._ASZ0 +#define ACR6_DBW1 acr6.bit._DBW1 +#define ACR6_DBW0 acr6.bit._DBW0 +#define ACR6_BST1 acr6.bit._BST1 +#define ACR6_BST0 acr6.bit._BST0 +#define ACR6_SREN acr6.bit._SREN +#define ACR6_PFEN acr6.bit._PFEN +#define ACR6_WREN acr6.bit._WREN +#define ACR6_LEND acr6.bit._LEND +#define ACR6_TYP3 acr6.bit._TYP3 +#define ACR6_TYP2 acr6.bit._TYP2 +#define ACR6_TYP1 acr6.bit._TYP1 +#define ACR6_TYP0 acr6.bit._TYP0 +#define ACR6_ASZ acr6.bitc._ASZ +#define ACR6_DBW acr6.bitc._DBW +#define ACR6_BST acr6.bitc._BST +#define ACR6_TYP acr6.bitc._TYP +__IO_EXTERN ASR7STR asr7; +#define ASR7 asr7.word +#define ASR7_A31 asr7.bit._A31 +#define ASR7_A30 asr7.bit._A30 +#define ASR7_A29 asr7.bit._A29 +#define ASR7_A28 asr7.bit._A28 +#define ASR7_A27 asr7.bit._A27 +#define ASR7_A26 asr7.bit._A26 +#define ASR7_A25 asr7.bit._A25 +#define ASR7_A24 asr7.bit._A24 +#define ASR7_A23 asr7.bit._A23 +#define ASR7_A22 asr7.bit._A22 +#define ASR7_A21 asr7.bit._A21 +#define ASR7_A20 asr7.bit._A20 +#define ASR7_A19 asr7.bit._A19 +#define ASR7_A18 asr7.bit._A18 +#define ASR7_A17 asr7.bit._A17 +#define ASR7_A16 asr7.bit._A16 +__IO_EXTERN ACR7STR acr7; +#define ACR7 acr7.word +#define ACR7_ASZ3 acr7.bit._ASZ3 +#define ACR7_ASZ2 acr7.bit._ASZ2 +#define ACR7_ASZ1 acr7.bit._ASZ1 +#define ACR7_ASZ0 acr7.bit._ASZ0 +#define ACR7_DBW1 acr7.bit._DBW1 +#define ACR7_DBW0 acr7.bit._DBW0 +#define ACR7_BST1 acr7.bit._BST1 +#define ACR7_BST0 acr7.bit._BST0 +#define ACR7_SREN acr7.bit._SREN +#define ACR7_PFEN acr7.bit._PFEN +#define ACR7_WREN acr7.bit._WREN +#define ACR7_LEND acr7.bit._LEND +#define ACR7_TYP3 acr7.bit._TYP3 +#define ACR7_TYP2 acr7.bit._TYP2 +#define ACR7_TYP1 acr7.bit._TYP1 +#define ACR7_TYP0 acr7.bit._TYP0 +#define ACR7_ASZ acr7.bitc._ASZ +#define ACR7_DBW acr7.bitc._DBW +#define ACR7_BST acr7.bitc._BST +#define ACR7_TYP acr7.bitc._TYP +__IO_EXTERN AWR0STR awr0; +#define AWR0 awr0.word +#define AWR0_W15 awr0.bit._W15 +#define AWR0_W14 awr0.bit._W14 +#define AWR0_W13 awr0.bit._W13 +#define AWR0_W12 awr0.bit._W12 +#define AWR0_W11 awr0.bit._W11 +#define AWR0_W10 awr0.bit._W10 +#define AWR0_W9 awr0.bit._W9 +#define AWR0_W8 awr0.bit._W8 +#define AWR0_W7 awr0.bit._W7 +#define AWR0_W6 awr0.bit._W6 +#define AWR0_W5 awr0.bit._W5 +#define AWR0_W4 awr0.bit._W4 +#define AWR0_W3 awr0.bit._W3 +#define AWR0_W2 awr0.bit._W2 +#define AWR0_W1 awr0.bit._W1 +#define AWR0_W0 awr0.bit._W0 +__IO_EXTERN AWR1STR awr1; +#define AWR1 awr1.word +#define AWR1_W15 awr1.bit._W15 +#define AWR1_W14 awr1.bit._W14 +#define AWR1_W13 awr1.bit._W13 +#define AWR1_W12 awr1.bit._W12 +#define AWR1_W11 awr1.bit._W11 +#define AWR1_W10 awr1.bit._W10 +#define AWR1_W9 awr1.bit._W9 +#define AWR1_W8 awr1.bit._W8 +#define AWR1_W7 awr1.bit._W7 +#define AWR1_W6 awr1.bit._W6 +#define AWR1_W5 awr1.bit._W5 +#define AWR1_W4 awr1.bit._W4 +#define AWR1_W3 awr1.bit._W3 +#define AWR1_W2 awr1.bit._W2 +#define AWR1_W1 awr1.bit._W1 +#define AWR1_W0 awr1.bit._W0 +__IO_EXTERN AWR2STR awr2; +#define AWR2 awr2.word +#define AWR2_W15 awr2.bit._W15 +#define AWR2_W14 awr2.bit._W14 +#define AWR2_W13 awr2.bit._W13 +#define AWR2_W12 awr2.bit._W12 +#define AWR2_W11 awr2.bit._W11 +#define AWR2_W10 awr2.bit._W10 +#define AWR2_W9 awr2.bit._W9 +#define AWR2_W8 awr2.bit._W8 +#define AWR2_W7 awr2.bit._W7 +#define AWR2_W6 awr2.bit._W6 +#define AWR2_W5 awr2.bit._W5 +#define AWR2_W4 awr2.bit._W4 +#define AWR2_W3 awr2.bit._W3 +#define AWR2_W2 awr2.bit._W2 +#define AWR2_W1 awr2.bit._W1 +#define AWR2_W0 awr2.bit._W0 +__IO_EXTERN AWR3STR awr3; +#define AWR3 awr3.word +#define AWR3_W15 awr3.bit._W15 +#define AWR3_W14 awr3.bit._W14 +#define AWR3_W13 awr3.bit._W13 +#define AWR3_W12 awr3.bit._W12 +#define AWR3_W11 awr3.bit._W11 +#define AWR3_W10 awr3.bit._W10 +#define AWR3_W9 awr3.bit._W9 +#define AWR3_W8 awr3.bit._W8 +#define AWR3_W7 awr3.bit._W7 +#define AWR3_W6 awr3.bit._W6 +#define AWR3_W5 awr3.bit._W5 +#define AWR3_W4 awr3.bit._W4 +#define AWR3_W3 awr3.bit._W3 +#define AWR3_W2 awr3.bit._W2 +#define AWR3_W1 awr3.bit._W1 +#define AWR3_W0 awr3.bit._W0 +__IO_EXTERN AWR4STR awr4; +#define AWR4 awr4.word +#define AWR4_W15 awr4.bit._W15 +#define AWR4_W14 awr4.bit._W14 +#define AWR4_W13 awr4.bit._W13 +#define AWR4_W12 awr4.bit._W12 +#define AWR4_W11 awr4.bit._W11 +#define AWR4_W10 awr4.bit._W10 +#define AWR4_W9 awr4.bit._W9 +#define AWR4_W8 awr4.bit._W8 +#define AWR4_W7 awr4.bit._W7 +#define AWR4_W6 awr4.bit._W6 +#define AWR4_W5 awr4.bit._W5 +#define AWR4_W4 awr4.bit._W4 +#define AWR4_W3 awr4.bit._W3 +#define AWR4_W2 awr4.bit._W2 +#define AWR4_W1 awr4.bit._W1 +#define AWR4_W0 awr4.bit._W0 +__IO_EXTERN AWR5STR awr5; +#define AWR5 awr5.word +#define AWR5_W15 awr5.bit._W15 +#define AWR5_W14 awr5.bit._W14 +#define AWR5_W13 awr5.bit._W13 +#define AWR5_W12 awr5.bit._W12 +#define AWR5_W11 awr5.bit._W11 +#define AWR5_W10 awr5.bit._W10 +#define AWR5_W9 awr5.bit._W9 +#define AWR5_W8 awr5.bit._W8 +#define AWR5_W7 awr5.bit._W7 +#define AWR5_W6 awr5.bit._W6 +#define AWR5_W5 awr5.bit._W5 +#define AWR5_W4 awr5.bit._W4 +#define AWR5_W3 awr5.bit._W3 +#define AWR5_W2 awr5.bit._W2 +#define AWR5_W1 awr5.bit._W1 +#define AWR5_W0 awr5.bit._W0 +__IO_EXTERN AWR6STR awr6; +#define AWR6 awr6.word +#define AWR6_W15 awr6.bit._W15 +#define AWR6_W14 awr6.bit._W14 +#define AWR6_W13 awr6.bit._W13 +#define AWR6_W12 awr6.bit._W12 +#define AWR6_W11 awr6.bit._W11 +#define AWR6_W10 awr6.bit._W10 +#define AWR6_W9 awr6.bit._W9 +#define AWR6_W8 awr6.bit._W8 +#define AWR6_W7 awr6.bit._W7 +#define AWR6_W6 awr6.bit._W6 +#define AWR6_W5 awr6.bit._W5 +#define AWR6_W4 awr6.bit._W4 +#define AWR6_W3 awr6.bit._W3 +#define AWR6_W2 awr6.bit._W2 +#define AWR6_W1 awr6.bit._W1 +#define AWR6_W0 awr6.bit._W0 +__IO_EXTERN AWR7STR awr7; +#define AWR7 awr7.word +#define AWR7_W15 awr7.bit._W15 +#define AWR7_W14 awr7.bit._W14 +#define AWR7_W13 awr7.bit._W13 +#define AWR7_W12 awr7.bit._W12 +#define AWR7_W11 awr7.bit._W11 +#define AWR7_W10 awr7.bit._W10 +#define AWR7_W9 awr7.bit._W9 +#define AWR7_W8 awr7.bit._W8 +#define AWR7_W7 awr7.bit._W7 +#define AWR7_W6 awr7.bit._W6 +#define AWR7_W5 awr7.bit._W5 +#define AWR7_W4 awr7.bit._W4 +#define AWR7_W3 awr7.bit._W3 +#define AWR7_W2 awr7.bit._W2 +#define AWR7_W1 awr7.bit._W1 +#define AWR7_W0 awr7.bit._W0 +__IO_EXTERN MCRASTR mcra; +#define MCRA mcra.byte +#define MCRA_PSZ2 mcra.bit._PSZ2 +#define MCRA_PSZ1 mcra.bit._PSZ1 +#define MCRA_PSZ0 mcra.bit._PSZ0 +#define MCRA_WBST mcra.bit._WBST +#define MCRA_BANK mcra.bit._BANK +#define MCRA_ABS1 mcra.bit._ABS1 +#define MCRA_ABS0 mcra.bit._ABS0 +#define MCRA_PSZ mcra.bitc._PSZ +#define MCRA_ABS mcra.bitc._ABS +__IO_EXTERN MCRBSTR mcrb; +#define MCRB mcrb.byte +#define MCRB_PSZ2 mcrb.bit._PSZ2 +#define MCRB_PSZ1 mcrb.bit._PSZ1 +#define MCRB_PSZ0 mcrb.bit._PSZ0 +#define MCRB_WBST mcrb.bit._WBST +#define MCRB_BANK mcrb.bit._BANK +#define MCRB_ABS1 mcrb.bit._ABS1 +#define MCRB_ABS0 mcrb.bit._ABS0 +#define MCRB_PSZ mcrb.bitc._PSZ +#define MCRB_ABS mcrb.bitc._ABS +__IO_EXTERN IOWR0STR iowr0; +#define IOWR0 iowr0.byte +#define IOWR0_RYE0 iowr0.bit._RYE0 +#define IOWR0_HLD0 iowr0.bit._HLD0 +#define IOWR0_WR01 iowr0.bit._WR01 +#define IOWR0_WR00 iowr0.bit._WR00 +#define IOWR0_IW03 iowr0.bit._IW03 +#define IOWR0_IW02 iowr0.bit._IW02 +#define IOWR0_IW01 iowr0.bit._IW01 +#define IOWR0_IW00 iowr0.bit._IW00 +#define IOWR0_WR0 iowr0.bitc._WR0 +#define IOWR0_IW0 iowr0.bitc._IW0 +__IO_EXTERN IOWR1STR iowr1; +#define IOWR1 iowr1.byte +#define IOWR1_RYE1 iowr1.bit._RYE1 +#define IOWR1_HLD1 iowr1.bit._HLD1 +#define IOWR1_WR11 iowr1.bit._WR11 +#define IOWR1_WR10 iowr1.bit._WR10 +#define IOWR1_IW13 iowr1.bit._IW13 +#define IOWR1_IW12 iowr1.bit._IW12 +#define IOWR1_IW11 iowr1.bit._IW11 +#define IOWR1_IW10 iowr1.bit._IW10 +#define IOWR1_WR1 iowr1.bitc._WR1 +#define IOWR1_IW1 iowr1.bitc._IW1 +__IO_EXTERN IOWR2STR iowr2; +#define IOWR2 iowr2.byte +#define IOWR2_RYE2 iowr2.bit._RYE2 +#define IOWR2_HLD2 iowr2.bit._HLD2 +#define IOWR2_WR21 iowr2.bit._WR21 +#define IOWR2_WR20 iowr2.bit._WR20 +#define IOWR2_IW23 iowr2.bit._IW23 +#define IOWR2_IW22 iowr2.bit._IW22 +#define IOWR2_IW21 iowr2.bit._IW21 +#define IOWR2_IW20 iowr2.bit._IW20 +#define IOWR2_WR2 iowr2.bitc._WR2 +#define IOWR2_IW2 iowr2.bitc._IW2 +__IO_EXTERN IOWR3STR iowr3; +#define IOWR3 iowr3.byte +#define IOWR3_RYE3 iowr3.bit._RYE3 +#define IOWR3_HLD3 iowr3.bit._HLD3 +#define IOWR3_WR31 iowr3.bit._WR31 +#define IOWR3_WR30 iowr3.bit._WR30 +#define IOWR3_IW33 iowr3.bit._IW33 +#define IOWR3_IW32 iowr3.bit._IW32 +#define IOWR3_IW31 iowr3.bit._IW31 +#define IOWR3_IW30 iowr3.bit._IW30 +#define IOWR3_WR3 iowr3.bitc._WR3 +#define IOWR3_IW3 iowr3.bitc._IW3 +__IO_EXTERN CSERSTR cser; +#define CSER cser.byte +#define CSER_CSE7 cser.bit._CSE7 +#define CSER_CSE6 cser.bit._CSE6 +#define CSER_CSE5 cser.bit._CSE5 +#define CSER_CSE4 cser.bit._CSE4 +#define CSER_CSE3 cser.bit._CSE3 +#define CSER_CSE2 cser.bit._CSE2 +#define CSER_CSE1 cser.bit._CSE1 +#define CSER_CSE0 cser.bit._CSE0 +__IO_EXTERN CHERSTR cher; +#define CHER cher.byte +#define CHER_CHE7 cher.bit._CHE7 +#define CHER_CHE6 cher.bit._CHE6 +#define CHER_CHE5 cher.bit._CHE5 +#define CHER_CHE4 cher.bit._CHE4 +#define CHER_CHE3 cher.bit._CHE3 +#define CHER_CHE2 cher.bit._CHE2 +#define CHER_CHE1 cher.bit._CHE1 +#define CHER_CHE0 cher.bit._CHE0 +__IO_EXTERN TCRSTR tcr; +#define TCR tcr.byte +#define TCR_BREN tcr.bit._BREN +#define TCR_PSUS tcr.bit._PSUS +#define TCR_PCLR tcr.bit._PCLR +#define TCR_RDW1 tcr.bit._RDW1 +#define TCR_RDW0 tcr.bit._RDW0 +#define TCR_RDW tcr.bitc._RDW +__IO_EXTERN RCRSTR rcr; +#define RCR rcr.word +#define RCR_SELF rcr.bit._SELF +#define RCR_RRLD rcr.bit._RRLD +#define RCR_RFINT5 rcr.bit._RFINT5 +#define RCR_RFINT4 rcr.bit._RFINT4 +#define RCR_RDINT3 rcr.bit._RDINT3 +#define RCR_RFINT2 rcr.bit._RFINT2 +#define RCR_RFINT1 rcr.bit._RFINT1 +#define RCR_RFINT0 rcr.bit._RFINT0 +#define RCR_BRST rcr.bit._BRST +#define RCR_RFC2 rcr.bit._RFC2 +#define RCR_RFC1 rcr.bit._RFC1 +#define RCR_RFC0 rcr.bit._RFC0 +#define RCR_PON rcr.bit._PON +#define RCR_TRC2 rcr.bit._TRC2 +#define RCR_TRC1 rcr.bit._TRC1 +#define RCR_TRC0 rcr.bit._TRC0 +#define RCR_RFINT rcr.bitc._RFINT +#define RCR_RFC rcr.bitc._RFC +#define RCR_TRC rcr.bitc._TRC +__IO_EXTERN MODRSTR modr; /* Mode Register */ +#define MODR modr.byte +#define MODR_ROMA modr.bit._ROMA +#define MODR_WTH1 modr.bit._WTH1 +#define MODR_WTH0 modr.bit._WTH0 +#define MODR_WTH modr.bitc._WTH +__IO_EXTERN PDRD00STR pdrd00; /* R-bus Port Data Direct Read Register */ +#define PDRD00 pdrd00.byte +#define PDRD00_D7 pdrd00.bit._D7 +#define PDRD00_D6 pdrd00.bit._D6 +#define PDRD00_D5 pdrd00.bit._D5 +#define PDRD00_D4 pdrd00.bit._D4 +#define PDRD00_D3 pdrd00.bit._D3 +#define PDRD00_D2 pdrd00.bit._D2 +#define PDRD00_D1 pdrd00.bit._D1 +#define PDRD00_D0 pdrd00.bit._D0 +__IO_EXTERN PDRD01STR pdrd01; +#define PDRD01 pdrd01.byte +#define PDRD01_D7 pdrd01.bit._D7 +#define PDRD01_D6 pdrd01.bit._D6 +#define PDRD01_D5 pdrd01.bit._D5 +#define PDRD01_D4 pdrd01.bit._D4 +#define PDRD01_D3 pdrd01.bit._D3 +#define PDRD01_D2 pdrd01.bit._D2 +#define PDRD01_D1 pdrd01.bit._D1 +#define PDRD01_D0 pdrd01.bit._D0 +__IO_EXTERN PDRD02STR pdrd02; +#define PDRD02 pdrd02.byte +#define PDRD02_D7 pdrd02.bit._D7 +#define PDRD02_D6 pdrd02.bit._D6 +#define PDRD02_D5 pdrd02.bit._D5 +#define PDRD02_D4 pdrd02.bit._D4 +#define PDRD02_D3 pdrd02.bit._D3 +#define PDRD02_D2 pdrd02.bit._D2 +#define PDRD02_D1 pdrd02.bit._D1 +#define PDRD02_D0 pdrd02.bit._D0 +__IO_EXTERN PDRD03STR pdrd03; +#define PDRD03 pdrd03.byte +#define PDRD03_D7 pdrd03.bit._D7 +#define PDRD03_D6 pdrd03.bit._D6 +#define PDRD03_D5 pdrd03.bit._D5 +#define PDRD03_D4 pdrd03.bit._D4 +#define PDRD03_D3 pdrd03.bit._D3 +#define PDRD03_D2 pdrd03.bit._D2 +#define PDRD03_D1 pdrd03.bit._D1 +#define PDRD03_D0 pdrd03.bit._D0 +__IO_EXTERN PDRD04STR pdrd04; +#define PDRD04 pdrd04.byte +#define PDRD04_D1 pdrd04.bit._D1 +#define PDRD04_D0 pdrd04.bit._D0 +__IO_EXTERN PDRD05STR pdrd05; +#define PDRD05 pdrd05.byte +#define PDRD05_D7 pdrd05.bit._D7 +#define PDRD05_D6 pdrd05.bit._D6 +#define PDRD05_D5 pdrd05.bit._D5 +#define PDRD05_D4 pdrd05.bit._D4 +#define PDRD05_D3 pdrd05.bit._D3 +#define PDRD05_D2 pdrd05.bit._D2 +#define PDRD05_D1 pdrd05.bit._D1 +#define PDRD05_D0 pdrd05.bit._D0 +__IO_EXTERN PDRD06STR pdrd06; +#define PDRD06 pdrd06.byte +#define PDRD06_D7 pdrd06.bit._D7 +#define PDRD06_D6 pdrd06.bit._D6 +#define PDRD06_D5 pdrd06.bit._D5 +#define PDRD06_D4 pdrd06.bit._D4 +#define PDRD06_D3 pdrd06.bit._D3 +#define PDRD06_D2 pdrd06.bit._D2 +#define PDRD06_D1 pdrd06.bit._D1 +#define PDRD06_D0 pdrd06.bit._D0 +__IO_EXTERN PDRD07STR pdrd07; +#define PDRD07 pdrd07.byte +#define PDRD07_D7 pdrd07.bit._D7 +#define PDRD07_D6 pdrd07.bit._D6 +#define PDRD07_D5 pdrd07.bit._D5 +#define PDRD07_D4 pdrd07.bit._D4 +#define PDRD07_D3 pdrd07.bit._D3 +#define PDRD07_D2 pdrd07.bit._D2 +#define PDRD07_D1 pdrd07.bit._D1 +#define PDRD07_D0 pdrd07.bit._D0 +__IO_EXTERN PDRD08STR pdrd08; +#define PDRD08 pdrd08.byte +#define PDRD08_D7 pdrd08.bit._D7 +#define PDRD08_D6 pdrd08.bit._D6 +#define PDRD08_D5 pdrd08.bit._D5 +#define PDRD08_D4 pdrd08.bit._D4 +#define PDRD08_D3 pdrd08.bit._D3 +#define PDRD08_D2 pdrd08.bit._D2 +#define PDRD08_D1 pdrd08.bit._D1 +#define PDRD08_D0 pdrd08.bit._D0 +__IO_EXTERN PDRD09STR pdrd09; +#define PDRD09 pdrd09.byte +#define PDRD09_D7 pdrd09.bit._D7 +#define PDRD09_D6 pdrd09.bit._D6 +#define PDRD09_D3 pdrd09.bit._D3 +#define PDRD09_D2 pdrd09.bit._D2 +#define PDRD09_D1 pdrd09.bit._D1 +#define PDRD09_D0 pdrd09.bit._D0 +__IO_EXTERN PDRD10STR pdrd10; +#define PDRD10 pdrd10.byte +#define PDRD10_D6 pdrd10.bit._D6 +#define PDRD10_D5 pdrd10.bit._D5 +#define PDRD10_D4 pdrd10.bit._D4 +#define PDRD10_D3 pdrd10.bit._D3 +#define PDRD10_D2 pdrd10.bit._D2 +#define PDRD10_D1 pdrd10.bit._D1 +__IO_EXTERN PDRD13STR pdrd13; +#define PDRD13 pdrd13.byte +#define PDRD13_D2 pdrd13.bit._D2 +#define PDRD13_D1 pdrd13.bit._D1 +#define PDRD13_D0 pdrd13.bit._D0 +__IO_EXTERN PDRD14STR pdrd14; +#define PDRD14 pdrd14.byte +#define PDRD14_D7 pdrd14.bit._D7 +#define PDRD14_D6 pdrd14.bit._D6 +#define PDRD14_D5 pdrd14.bit._D5 +#define PDRD14_D4 pdrd14.bit._D4 +#define PDRD14_D3 pdrd14.bit._D3 +#define PDRD14_D2 pdrd14.bit._D2 +#define PDRD14_D1 pdrd14.bit._D1 +#define PDRD14_D0 pdrd14.bit._D0 +__IO_EXTERN PDRD15STR pdrd15; +#define PDRD15 pdrd15.byte +#define PDRD15_D3 pdrd15.bit._D3 +#define PDRD15_D2 pdrd15.bit._D2 +#define PDRD15_D1 pdrd15.bit._D1 +#define PDRD15_D0 pdrd15.bit._D0 +__IO_EXTERN PDRD16STR pdrd16; +#define PDRD16 pdrd16.byte +#define PDRD16_D7 pdrd16.bit._D7 +#define PDRD16_D6 pdrd16.bit._D6 +#define PDRD16_D5 pdrd16.bit._D5 +#define PDRD16_D4 pdrd16.bit._D4 +#define PDRD16_D3 pdrd16.bit._D3 +#define PDRD16_D2 pdrd16.bit._D2 +#define PDRD16_D1 pdrd16.bit._D1 +#define PDRD16_D0 pdrd16.bit._D0 +__IO_EXTERN PDRD17STR pdrd17; +#define PDRD17 pdrd17.byte +#define PDRD17_D7 pdrd17.bit._D7 +#define PDRD17_D6 pdrd17.bit._D6 +#define PDRD17_D5 pdrd17.bit._D5 +#define PDRD17_D4 pdrd17.bit._D4 +__IO_EXTERN PDRD18STR pdrd18; +#define PDRD18 pdrd18.byte +#define PDRD18_D6 pdrd18.bit._D6 +#define PDRD18_D5 pdrd18.bit._D5 +#define PDRD18_D4 pdrd18.bit._D4 +#define PDRD18_D2 pdrd18.bit._D2 +#define PDRD18_D1 pdrd18.bit._D1 +#define PDRD18_D0 pdrd18.bit._D0 +__IO_EXTERN PDRD19STR pdrd19; +#define PDRD19 pdrd19.byte +#define PDRD19_D6 pdrd19.bit._D6 +#define PDRD19_D5 pdrd19.bit._D5 +#define PDRD19_D4 pdrd19.bit._D4 +#define PDRD19_D2 pdrd19.bit._D2 +#define PDRD19_D1 pdrd19.bit._D1 +#define PDRD19_D0 pdrd19.bit._D0 +__IO_EXTERN PDRD20STR pdrd20; +#define PDRD20 pdrd20.byte +#define PDRD20_D2 pdrd20.bit._D2 +#define PDRD20_D1 pdrd20.bit._D1 +#define PDRD20_D0 pdrd20.bit._D0 +__IO_EXTERN PDRD22STR pdrd22; +#define PDRD22 pdrd22.byte +#define PDRD22_D5 pdrd22.bit._D5 +#define PDRD22_D4 pdrd22.bit._D4 +#define PDRD22_D2 pdrd22.bit._D2 +#define PDRD22_D0 pdrd22.bit._D0 +__IO_EXTERN PDRD23STR pdrd23; +#define PDRD23 pdrd23.byte +#define PDRD23_D5 pdrd23.bit._D5 +#define PDRD23_D4 pdrd23.bit._D4 +#define PDRD23_D3 pdrd23.bit._D3 +#define PDRD23_D2 pdrd23.bit._D2 +#define PDRD23_D1 pdrd23.bit._D1 +#define PDRD23_D0 pdrd23.bit._D0 +__IO_EXTERN PDRD24STR pdrd24; +#define PDRD24 pdrd24.byte +#define PDRD24_D7 pdrd24.bit._D7 +#define PDRD24_D6 pdrd24.bit._D6 +#define PDRD24_D5 pdrd24.bit._D5 +#define PDRD24_D4 pdrd24.bit._D4 +#define PDRD24_D3 pdrd24.bit._D3 +#define PDRD24_D2 pdrd24.bit._D2 +#define PDRD24_D1 pdrd24.bit._D1 +#define PDRD24_D0 pdrd24.bit._D0 +__IO_EXTERN PDRD25STR pdrd25; +#define PDRD25 pdrd25.byte +#define PDRD25_D7 pdrd25.bit._D7 +#define PDRD25_D6 pdrd25.bit._D6 +#define PDRD25_D5 pdrd25.bit._D5 +#define PDRD25_D4 pdrd25.bit._D4 +#define PDRD25_D3 pdrd25.bit._D3 +#define PDRD25_D2 pdrd25.bit._D2 +#define PDRD25_D1 pdrd25.bit._D1 +#define PDRD25_D0 pdrd25.bit._D0 +__IO_EXTERN PDRD26STR pdrd26; +#define PDRD26 pdrd26.byte +#define PDRD26_D7 pdrd26.bit._D7 +#define PDRD26_D6 pdrd26.bit._D6 +#define PDRD26_D5 pdrd26.bit._D5 +#define PDRD26_D4 pdrd26.bit._D4 +#define PDRD26_D3 pdrd26.bit._D3 +#define PDRD26_D2 pdrd26.bit._D2 +#define PDRD26_D1 pdrd26.bit._D1 +#define PDRD26_D0 pdrd26.bit._D0 +__IO_EXTERN PDRD27STR pdrd27; +#define PDRD27 pdrd27.byte +#define PDRD27_D7 pdrd27.bit._D7 +#define PDRD27_D6 pdrd27.bit._D6 +#define PDRD27_D5 pdrd27.bit._D5 +#define PDRD27_D4 pdrd27.bit._D4 +#define PDRD27_D3 pdrd27.bit._D3 +#define PDRD27_D2 pdrd27.bit._D2 +#define PDRD27_D1 pdrd27.bit._D1 +#define PDRD27_D0 pdrd27.bit._D0 +__IO_EXTERN PDRD29STR pdrd29; +#define PDRD29 pdrd29.byte +#define PDRD29_D7 pdrd29.bit._D7 +#define PDRD29_D6 pdrd29.bit._D6 +#define PDRD29_D5 pdrd29.bit._D5 +#define PDRD29_D4 pdrd29.bit._D4 +#define PDRD29_D3 pdrd29.bit._D3 +#define PDRD29_D2 pdrd29.bit._D2 +#define PDRD29_D1 pdrd29.bit._D1 +#define PDRD29_D0 pdrd29.bit._D0 +__IO_EXTERN DDR00STR ddr00; /* R-bus Port Direction Register */ +#define DDR00 ddr00.byte +#define DDR00_D7 ddr00.bit._D7 +#define DDR00_D6 ddr00.bit._D6 +#define DDR00_D5 ddr00.bit._D5 +#define DDR00_D4 ddr00.bit._D4 +#define DDR00_D3 ddr00.bit._D3 +#define DDR00_D2 ddr00.bit._D2 +#define DDR00_D1 ddr00.bit._D1 +#define DDR00_D0 ddr00.bit._D0 +__IO_EXTERN DDR01STR ddr01; +#define DDR01 ddr01.byte +#define DDR01_D7 ddr01.bit._D7 +#define DDR01_D6 ddr01.bit._D6 +#define DDR01_D5 ddr01.bit._D5 +#define DDR01_D4 ddr01.bit._D4 +#define DDR01_D3 ddr01.bit._D3 +#define DDR01_D2 ddr01.bit._D2 +#define DDR01_D1 ddr01.bit._D1 +#define DDR01_D0 ddr01.bit._D0 +__IO_EXTERN DDR02STR ddr02; +#define DDR02 ddr02.byte +#define DDR02_D7 ddr02.bit._D7 +#define DDR02_D6 ddr02.bit._D6 +#define DDR02_D5 ddr02.bit._D5 +#define DDR02_D4 ddr02.bit._D4 +#define DDR02_D3 ddr02.bit._D3 +#define DDR02_D2 ddr02.bit._D2 +#define DDR02_D1 ddr02.bit._D1 +#define DDR02_D0 ddr02.bit._D0 +__IO_EXTERN DDR03STR ddr03; +#define DDR03 ddr03.byte +#define DDR03_D7 ddr03.bit._D7 +#define DDR03_D6 ddr03.bit._D6 +#define DDR03_D5 ddr03.bit._D5 +#define DDR03_D4 ddr03.bit._D4 +#define DDR03_D3 ddr03.bit._D3 +#define DDR03_D2 ddr03.bit._D2 +#define DDR03_D1 ddr03.bit._D1 +#define DDR03_D0 ddr03.bit._D0 +__IO_EXTERN DDR04STR ddr04; +#define DDR04 ddr04.byte +#define DDR04_D1 ddr04.bit._D1 +#define DDR04_D0 ddr04.bit._D0 +__IO_EXTERN DDR05STR ddr05; +#define DDR05 ddr05.byte +#define DDR05_D7 ddr05.bit._D7 +#define DDR05_D6 ddr05.bit._D6 +#define DDR05_D5 ddr05.bit._D5 +#define DDR05_D4 ddr05.bit._D4 +#define DDR05_D3 ddr05.bit._D3 +#define DDR05_D2 ddr05.bit._D2 +#define DDR05_D1 ddr05.bit._D1 +#define DDR05_D0 ddr05.bit._D0 +__IO_EXTERN DDR06STR ddr06; +#define DDR06 ddr06.byte +#define DDR06_D7 ddr06.bit._D7 +#define DDR06_D6 ddr06.bit._D6 +#define DDR06_D5 ddr06.bit._D5 +#define DDR06_D4 ddr06.bit._D4 +#define DDR06_D3 ddr06.bit._D3 +#define DDR06_D2 ddr06.bit._D2 +#define DDR06_D1 ddr06.bit._D1 +#define DDR06_D0 ddr06.bit._D0 +__IO_EXTERN DDR07STR ddr07; +#define DDR07 ddr07.byte +#define DDR07_D7 ddr07.bit._D7 +#define DDR07_D6 ddr07.bit._D6 +#define DDR07_D5 ddr07.bit._D5 +#define DDR07_D4 ddr07.bit._D4 +#define DDR07_D3 ddr07.bit._D3 +#define DDR07_D2 ddr07.bit._D2 +#define DDR07_D1 ddr07.bit._D1 +#define DDR07_D0 ddr07.bit._D0 +__IO_EXTERN DDR08STR ddr08; +#define DDR08 ddr08.byte +#define DDR08_D7 ddr08.bit._D7 +#define DDR08_D6 ddr08.bit._D6 +#define DDR08_D5 ddr08.bit._D5 +#define DDR08_D4 ddr08.bit._D4 +#define DDR08_D3 ddr08.bit._D3 +#define DDR08_D2 ddr08.bit._D2 +#define DDR08_D1 ddr08.bit._D1 +#define DDR08_D0 ddr08.bit._D0 +__IO_EXTERN DDR09STR ddr09; +#define DDR09 ddr09.byte +#define DDR09_D7 ddr09.bit._D7 +#define DDR09_D6 ddr09.bit._D6 +#define DDR09_D3 ddr09.bit._D3 +#define DDR09_D2 ddr09.bit._D2 +#define DDR09_D1 ddr09.bit._D1 +#define DDR09_D0 ddr09.bit._D0 +__IO_EXTERN DDR10STR ddr10; +#define DDR10 ddr10.byte +#define DDR10_D6 ddr10.bit._D6 +#define DDR10_D5 ddr10.bit._D5 +#define DDR10_D4 ddr10.bit._D4 +#define DDR10_D3 ddr10.bit._D3 +#define DDR10_D2 ddr10.bit._D2 +#define DDR10_D1 ddr10.bit._D1 +__IO_EXTERN DDR13STR ddr13; +#define DDR13 ddr13.byte +#define DDR13_D2 ddr13.bit._D2 +#define DDR13_D1 ddr13.bit._D1 +#define DDR13_D0 ddr13.bit._D0 +__IO_EXTERN DDR14STR ddr14; +#define DDR14 ddr14.byte +#define DDR14_D7 ddr14.bit._D7 +#define DDR14_D6 ddr14.bit._D6 +#define DDR14_D5 ddr14.bit._D5 +#define DDR14_D4 ddr14.bit._D4 +#define DDR14_D3 ddr14.bit._D3 +#define DDR14_D2 ddr14.bit._D2 +#define DDR14_D1 ddr14.bit._D1 +#define DDR14_D0 ddr14.bit._D0 +__IO_EXTERN DDR15STR ddr15; +#define DDR15 ddr15.byte +#define DDR15_D3 ddr15.bit._D3 +#define DDR15_D2 ddr15.bit._D2 +#define DDR15_D1 ddr15.bit._D1 +#define DDR15_D0 ddr15.bit._D0 +__IO_EXTERN DDR16STR ddr16; +#define DDR16 ddr16.byte +#define DDR16_D7 ddr16.bit._D7 +#define DDR16_D6 ddr16.bit._D6 +#define DDR16_D5 ddr16.bit._D5 +#define DDR16_D4 ddr16.bit._D4 +#define DDR16_D3 ddr16.bit._D3 +#define DDR16_D2 ddr16.bit._D2 +#define DDR16_D1 ddr16.bit._D1 +#define DDR16_D0 ddr16.bit._D0 +__IO_EXTERN DDR17STR ddr17; +#define DDR17 ddr17.byte +#define DDR17_D7 ddr17.bit._D7 +#define DDR17_D6 ddr17.bit._D6 +#define DDR17_D5 ddr17.bit._D5 +#define DDR17_D4 ddr17.bit._D4 +__IO_EXTERN DDR18STR ddr18; +#define DDR18 ddr18.byte +#define DDR18_D6 ddr18.bit._D6 +#define DDR18_D5 ddr18.bit._D5 +#define DDR18_D4 ddr18.bit._D4 +#define DDR18_D2 ddr18.bit._D2 +#define DDR18_D1 ddr18.bit._D1 +#define DDR18_D0 ddr18.bit._D0 +__IO_EXTERN DDR19STR ddr19; +#define DDR19 ddr19.byte +#define DDR19_D6 ddr19.bit._D6 +#define DDR19_D5 ddr19.bit._D5 +#define DDR19_D4 ddr19.bit._D4 +#define DDR19_D2 ddr19.bit._D2 +#define DDR19_D1 ddr19.bit._D1 +#define DDR19_D0 ddr19.bit._D0 +__IO_EXTERN DDR20STR ddr20; +#define DDR20 ddr20.byte +#define DDR20_D2 ddr20.bit._D2 +#define DDR20_D1 ddr20.bit._D1 +#define DDR20_D0 ddr20.bit._D0 +__IO_EXTERN DDR22STR ddr22; +#define DDR22 ddr22.byte +#define DDR22_D5 ddr22.bit._D5 +#define DDR22_D4 ddr22.bit._D4 +#define DDR22_D2 ddr22.bit._D2 +#define DDR22_D0 ddr22.bit._D0 +__IO_EXTERN DDR23STR ddr23; +#define DDR23 ddr23.byte +#define DDR23_D5 ddr23.bit._D5 +#define DDR23_D4 ddr23.bit._D4 +#define DDR23_D3 ddr23.bit._D3 +#define DDR23_D2 ddr23.bit._D2 +#define DDR23_D1 ddr23.bit._D1 +#define DDR23_D0 ddr23.bit._D0 +__IO_EXTERN DDR24STR ddr24; +#define DDR24 ddr24.byte +#define DDR24_D7 ddr24.bit._D7 +#define DDR24_D6 ddr24.bit._D6 +#define DDR24_D5 ddr24.bit._D5 +#define DDR24_D4 ddr24.bit._D4 +#define DDR24_D3 ddr24.bit._D3 +#define DDR24_D2 ddr24.bit._D2 +#define DDR24_D1 ddr24.bit._D1 +#define DDR24_D0 ddr24.bit._D0 +__IO_EXTERN DDR25STR ddr25; +#define DDR25 ddr25.byte +#define DDR25_D7 ddr25.bit._D7 +#define DDR25_D6 ddr25.bit._D6 +#define DDR25_D5 ddr25.bit._D5 +#define DDR25_D4 ddr25.bit._D4 +#define DDR25_D3 ddr25.bit._D3 +#define DDR25_D2 ddr25.bit._D2 +#define DDR25_D1 ddr25.bit._D1 +#define DDR25_D0 ddr25.bit._D0 +__IO_EXTERN DDR26STR ddr26; +#define DDR26 ddr26.byte +#define DDR26_D7 ddr26.bit._D7 +#define DDR26_D6 ddr26.bit._D6 +#define DDR26_D5 ddr26.bit._D5 +#define DDR26_D4 ddr26.bit._D4 +#define DDR26_D3 ddr26.bit._D3 +#define DDR26_D2 ddr26.bit._D2 +#define DDR26_D1 ddr26.bit._D1 +#define DDR26_D0 ddr26.bit._D0 +__IO_EXTERN DDR27STR ddr27; +#define DDR27 ddr27.byte +#define DDR27_D7 ddr27.bit._D7 +#define DDR27_D6 ddr27.bit._D6 +#define DDR27_D5 ddr27.bit._D5 +#define DDR27_D4 ddr27.bit._D4 +#define DDR27_D3 ddr27.bit._D3 +#define DDR27_D2 ddr27.bit._D2 +#define DDR27_D1 ddr27.bit._D1 +#define DDR27_D0 ddr27.bit._D0 +__IO_EXTERN DDR29STR ddr29; +#define DDR29 ddr29.byte +#define DDR29_D7 ddr29.bit._D7 +#define DDR29_D6 ddr29.bit._D6 +#define DDR29_D5 ddr29.bit._D5 +#define DDR29_D4 ddr29.bit._D4 +#define DDR29_D3 ddr29.bit._D3 +#define DDR29_D2 ddr29.bit._D2 +#define DDR29_D1 ddr29.bit._D1 +#define DDR29_D0 ddr29.bit._D0 +__IO_EXTERN PFR00STR pfr00; /* R-bus Port Function Register */ +#define PFR00 pfr00.byte +#define PFR00_D7 pfr00.bit._D7 +#define PFR00_D6 pfr00.bit._D6 +#define PFR00_D5 pfr00.bit._D5 +#define PFR00_D4 pfr00.bit._D4 +#define PFR00_D3 pfr00.bit._D3 +#define PFR00_D2 pfr00.bit._D2 +#define PFR00_D1 pfr00.bit._D1 +#define PFR00_D0 pfr00.bit._D0 +__IO_EXTERN PFR01STR pfr01; +#define PFR01 pfr01.byte +#define PFR01_D7 pfr01.bit._D7 +#define PFR01_D6 pfr01.bit._D6 +#define PFR01_D5 pfr01.bit._D5 +#define PFR01_D4 pfr01.bit._D4 +#define PFR01_D3 pfr01.bit._D3 +#define PFR01_D2 pfr01.bit._D2 +#define PFR01_D1 pfr01.bit._D1 +#define PFR01_D0 pfr01.bit._D0 +__IO_EXTERN PFR02STR pfr02; +#define PFR02 pfr02.byte +#define PFR02_D7 pfr02.bit._D7 +#define PFR02_D6 pfr02.bit._D6 +#define PFR02_D5 pfr02.bit._D5 +#define PFR02_D4 pfr02.bit._D4 +#define PFR02_D3 pfr02.bit._D3 +#define PFR02_D2 pfr02.bit._D2 +#define PFR02_D1 pfr02.bit._D1 +#define PFR02_D0 pfr02.bit._D0 +__IO_EXTERN PFR03STR pfr03; +#define PFR03 pfr03.byte +#define PFR03_D7 pfr03.bit._D7 +#define PFR03_D6 pfr03.bit._D6 +#define PFR03_D5 pfr03.bit._D5 +#define PFR03_D4 pfr03.bit._D4 +#define PFR03_D3 pfr03.bit._D3 +#define PFR03_D2 pfr03.bit._D2 +#define PFR03_D1 pfr03.bit._D1 +#define PFR03_D0 pfr03.bit._D0 +__IO_EXTERN PFR04STR pfr04; +#define PFR04 pfr04.byte +#define PFR04_D1 pfr04.bit._D1 +#define PFR04_D0 pfr04.bit._D0 +__IO_EXTERN PFR05STR pfr05; +#define PFR05 pfr05.byte +#define PFR05_D7 pfr05.bit._D7 +#define PFR05_D6 pfr05.bit._D6 +#define PFR05_D5 pfr05.bit._D5 +#define PFR05_D4 pfr05.bit._D4 +#define PFR05_D3 pfr05.bit._D3 +#define PFR05_D2 pfr05.bit._D2 +#define PFR05_D1 pfr05.bit._D1 +#define PFR05_D0 pfr05.bit._D0 +__IO_EXTERN PFR06STR pfr06; +#define PFR06 pfr06.byte +#define PFR06_D7 pfr06.bit._D7 +#define PFR06_D6 pfr06.bit._D6 +#define PFR06_D5 pfr06.bit._D5 +#define PFR06_D4 pfr06.bit._D4 +#define PFR06_D3 pfr06.bit._D3 +#define PFR06_D2 pfr06.bit._D2 +#define PFR06_D1 pfr06.bit._D1 +#define PFR06_D0 pfr06.bit._D0 +__IO_EXTERN PFR07STR pfr07; +#define PFR07 pfr07.byte +#define PFR07_D7 pfr07.bit._D7 +#define PFR07_D6 pfr07.bit._D6 +#define PFR07_D5 pfr07.bit._D5 +#define PFR07_D4 pfr07.bit._D4 +#define PFR07_D3 pfr07.bit._D3 +#define PFR07_D2 pfr07.bit._D2 +#define PFR07_D1 pfr07.bit._D1 +#define PFR07_D0 pfr07.bit._D0 +__IO_EXTERN PFR08STR pfr08; +#define PFR08 pfr08.byte +#define PFR08_D7 pfr08.bit._D7 +#define PFR08_D6 pfr08.bit._D6 +#define PFR08_D5 pfr08.bit._D5 +#define PFR08_D4 pfr08.bit._D4 +#define PFR08_D3 pfr08.bit._D3 +#define PFR08_D2 pfr08.bit._D2 +#define PFR08_D1 pfr08.bit._D1 +#define PFR08_D0 pfr08.bit._D0 +__IO_EXTERN PFR09STR pfr09; +#define PFR09 pfr09.byte +#define PFR09_D7 pfr09.bit._D7 +#define PFR09_D6 pfr09.bit._D6 +#define PFR09_D3 pfr09.bit._D3 +#define PFR09_D2 pfr09.bit._D2 +#define PFR09_D1 pfr09.bit._D1 +#define PFR09_D0 pfr09.bit._D0 +__IO_EXTERN PFR10STR pfr10; +#define PFR10 pfr10.byte +#define PFR10_D6 pfr10.bit._D6 +#define PFR10_D5 pfr10.bit._D5 +#define PFR10_D4 pfr10.bit._D4 +#define PFR10_D3 pfr10.bit._D3 +#define PFR10_D2 pfr10.bit._D2 +#define PFR10_D1 pfr10.bit._D1 +__IO_EXTERN PFR13STR pfr13; +#define PFR13 pfr13.byte +#define PFR13_D2 pfr13.bit._D2 +#define PFR13_D1 pfr13.bit._D1 +#define PFR13_D0 pfr13.bit._D0 +__IO_EXTERN PFR14STR pfr14; +#define PFR14 pfr14.byte +#define PFR14_D7 pfr14.bit._D7 +#define PFR14_D6 pfr14.bit._D6 +#define PFR14_D5 pfr14.bit._D5 +#define PFR14_D4 pfr14.bit._D4 +#define PFR14_D3 pfr14.bit._D3 +#define PFR14_D2 pfr14.bit._D2 +#define PFR14_D1 pfr14.bit._D1 +#define PFR14_D0 pfr14.bit._D0 +__IO_EXTERN PFR15STR pfr15; +#define PFR15 pfr15.byte +#define PFR15_D3 pfr15.bit._D3 +#define PFR15_D2 pfr15.bit._D2 +#define PFR15_D1 pfr15.bit._D1 +#define PFR15_D0 pfr15.bit._D0 +__IO_EXTERN PFR16STR pfr16; +#define PFR16 pfr16.byte +#define PFR16_D7 pfr16.bit._D7 +#define PFR16_D6 pfr16.bit._D6 +#define PFR16_D5 pfr16.bit._D5 +#define PFR16_D4 pfr16.bit._D4 +#define PFR16_D3 pfr16.bit._D3 +#define PFR16_D2 pfr16.bit._D2 +#define PFR16_D1 pfr16.bit._D1 +#define PFR16_D0 pfr16.bit._D0 +__IO_EXTERN PFR17STR pfr17; +#define PFR17 pfr17.byte +#define PFR17_D7 pfr17.bit._D7 +#define PFR17_D6 pfr17.bit._D6 +#define PFR17_D5 pfr17.bit._D5 +#define PFR17_D4 pfr17.bit._D4 +__IO_EXTERN PFR18STR pfr18; +#define PFR18 pfr18.byte +#define PFR18_D6 pfr18.bit._D6 +#define PFR18_D5 pfr18.bit._D5 +#define PFR18_D4 pfr18.bit._D4 +#define PFR18_D2 pfr18.bit._D2 +#define PFR18_D1 pfr18.bit._D1 +#define PFR18_D0 pfr18.bit._D0 +__IO_EXTERN PFR19STR pfr19; +#define PFR19 pfr19.byte +#define PFR19_D6 pfr19.bit._D6 +#define PFR19_D5 pfr19.bit._D5 +#define PFR19_D4 pfr19.bit._D4 +#define PFR19_D2 pfr19.bit._D2 +#define PFR19_D1 pfr19.bit._D1 +#define PFR19_D0 pfr19.bit._D0 +__IO_EXTERN PFR20STR pfr20; +#define PFR20 pfr20.byte +#define PFR20_D2 pfr20.bit._D2 +#define PFR20_D1 pfr20.bit._D1 +#define PFR20_D0 pfr20.bit._D0 +__IO_EXTERN PFR22STR pfr22; +#define PFR22 pfr22.byte +#define PFR22_D5 pfr22.bit._D5 +#define PFR22_D4 pfr22.bit._D4 +#define PFR22_D2 pfr22.bit._D2 +#define PFR22_D0 pfr22.bit._D0 +__IO_EXTERN PFR23STR pfr23; +#define PFR23 pfr23.byte +#define PFR23_D5 pfr23.bit._D5 +#define PFR23_D4 pfr23.bit._D4 +#define PFR23_D3 pfr23.bit._D3 +#define PFR23_D2 pfr23.bit._D2 +#define PFR23_D1 pfr23.bit._D1 +#define PFR23_D0 pfr23.bit._D0 +__IO_EXTERN PFR24STR pfr24; +#define PFR24 pfr24.byte +#define PFR24_D7 pfr24.bit._D7 +#define PFR24_D6 pfr24.bit._D6 +#define PFR24_D5 pfr24.bit._D5 +#define PFR24_D4 pfr24.bit._D4 +#define PFR24_D3 pfr24.bit._D3 +#define PFR24_D2 pfr24.bit._D2 +#define PFR24_D1 pfr24.bit._D1 +#define PFR24_D0 pfr24.bit._D0 +__IO_EXTERN PFR25STR pfr25; +#define PFR25 pfr25.byte +#define PFR25_D7 pfr25.bit._D7 +#define PFR25_D6 pfr25.bit._D6 +#define PFR25_D5 pfr25.bit._D5 +#define PFR25_D4 pfr25.bit._D4 +#define PFR25_D3 pfr25.bit._D3 +#define PFR25_D2 pfr25.bit._D2 +#define PFR25_D1 pfr25.bit._D1 +#define PFR25_D0 pfr25.bit._D0 +__IO_EXTERN PFR26STR pfr26; +#define PFR26 pfr26.byte +#define PFR26_D7 pfr26.bit._D7 +#define PFR26_D6 pfr26.bit._D6 +#define PFR26_D5 pfr26.bit._D5 +#define PFR26_D4 pfr26.bit._D4 +#define PFR26_D3 pfr26.bit._D3 +#define PFR26_D2 pfr26.bit._D2 +#define PFR26_D1 pfr26.bit._D1 +#define PFR26_D0 pfr26.bit._D0 +__IO_EXTERN PFR27STR pfr27; +#define PFR27 pfr27.byte +#define PFR27_D7 pfr27.bit._D7 +#define PFR27_D6 pfr27.bit._D6 +#define PFR27_D5 pfr27.bit._D5 +#define PFR27_D4 pfr27.bit._D4 +#define PFR27_D3 pfr27.bit._D3 +#define PFR27_D2 pfr27.bit._D2 +#define PFR27_D1 pfr27.bit._D1 +#define PFR27_D0 pfr27.bit._D0 +__IO_EXTERN PFR29STR pfr29; +#define PFR29 pfr29.byte +#define PFR29_D7 pfr29.bit._D7 +#define PFR29_D6 pfr29.bit._D6 +#define PFR29_D5 pfr29.bit._D5 +#define PFR29_D4 pfr29.bit._D4 +#define PFR29_D3 pfr29.bit._D3 +#define PFR29_D2 pfr29.bit._D2 +#define PFR29_D1 pfr29.bit._D1 +#define PFR29_D0 pfr29.bit._D0 +__IO_EXTERN EPFR10STR epfr10; /* R-bus Port Extra Function Register */ +#define EPFR10 epfr10.byte +#define EPFR10_D5 epfr10.bit._D5 +#define EPFR10_D4 epfr10.bit._D4 +__IO_EXTERN EPFR13STR epfr13; +#define EPFR13 epfr13.byte +#define EPFR13_D2 epfr13.bit._D2 +__IO_EXTERN EPFR14STR epfr14; +#define EPFR14 epfr14.byte +#define EPFR14_D7 epfr14.bit._D7 +#define EPFR14_D6 epfr14.bit._D6 +#define EPFR14_D5 epfr14.bit._D5 +#define EPFR14_D4 epfr14.bit._D4 +#define EPFR14_D3 epfr14.bit._D3 +#define EPFR14_D2 epfr14.bit._D2 +#define EPFR14_D1 epfr14.bit._D1 +#define EPFR14_D0 epfr14.bit._D0 +__IO_EXTERN EPFR15STR epfr15; +#define EPFR15 epfr15.byte +#define EPFR15_D3 epfr15.bit._D3 +#define EPFR15_D2 epfr15.bit._D2 +#define EPFR15_D1 epfr15.bit._D1 +#define EPFR15_D0 epfr15.bit._D0 +__IO_EXTERN EPFR16STR epfr16; +#define EPFR16 epfr16.byte +#define EPFR16_D7 epfr16.bit._D7 +#define EPFR16_D6 epfr16.bit._D6 +#define EPFR16_D5 epfr16.bit._D5 +#define EPFR16_D4 epfr16.bit._D4 +__IO_EXTERN EPFR18STR epfr18; +#define EPFR18 epfr18.byte +#define EPFR18_D6 epfr18.bit._D6 +#define EPFR18_D5 epfr18.bit._D5 +#define EPFR18_D4 epfr18.bit._D4 +#define EPFR18_D2 epfr18.bit._D2 +#define EPFR18_D1 epfr18.bit._D1 +#define EPFR18_D0 epfr18.bit._D0 +__IO_EXTERN EPFR19STR epfr19; +#define EPFR19 epfr19.byte +#define EPFR19_D6 epfr19.bit._D6 +#define EPFR19_D2 epfr19.bit._D2 +__IO_EXTERN EPFR20STR epfr20; +#define EPFR20 epfr20.byte +#define EPFR20_D2 epfr20.bit._D2 +#define EPFR20_D1 epfr20.bit._D1 +#define EPFR20_D0 epfr20.bit._D0 +__IO_EXTERN EPFR26STR epfr26; +#define EPFR26 epfr26.byte +#define EPFR26_D7 epfr26.bit._D7 +#define EPFR26_D6 epfr26.bit._D6 +#define EPFR26_D5 epfr26.bit._D5 +#define EPFR26_D4 epfr26.bit._D4 +#define EPFR26_D3 epfr26.bit._D3 +#define EPFR26_D2 epfr26.bit._D2 +#define EPFR26_D1 epfr26.bit._D1 +#define EPFR26_D0 epfr26.bit._D0 +__IO_EXTERN EPFR27STR epfr27; +#define EPFR27 epfr27.byte +#define EPFR27_D7 epfr27.bit._D7 +#define EPFR27_D6 epfr27.bit._D6 +#define EPFR27_D5 epfr27.bit._D5 +#define EPFR27_D4 epfr27.bit._D4 +#define EPFR27_D3 epfr27.bit._D3 +#define EPFR27_D2 epfr27.bit._D2 +#define EPFR27_D1 epfr27.bit._D1 +#define EPFR27_D0 epfr27.bit._D0 +__IO_EXTERN PODR00STR podr00; /* R-bus Port Output Drive Select Register */ +#define PODR00 podr00.byte +#define PODR00_D7 podr00.bit._D7 +#define PODR00_D6 podr00.bit._D6 +#define PODR00_D5 podr00.bit._D5 +#define PODR00_D4 podr00.bit._D4 +#define PODR00_D3 podr00.bit._D3 +#define PODR00_D2 podr00.bit._D2 +#define PODR00_D1 podr00.bit._D1 +#define PODR00_D0 podr00.bit._D0 +__IO_EXTERN PODR01STR podr01; +#define PODR01 podr01.byte +#define PODR01_D7 podr01.bit._D7 +#define PODR01_D6 podr01.bit._D6 +#define PODR01_D5 podr01.bit._D5 +#define PODR01_D4 podr01.bit._D4 +#define PODR01_D3 podr01.bit._D3 +#define PODR01_D2 podr01.bit._D2 +#define PODR01_D1 podr01.bit._D1 +#define PODR01_D0 podr01.bit._D0 +__IO_EXTERN PODR02STR podr02; +#define PODR02 podr02.byte +#define PODR02_D7 podr02.bit._D7 +#define PODR02_D6 podr02.bit._D6 +#define PODR02_D5 podr02.bit._D5 +#define PODR02_D4 podr02.bit._D4 +#define PODR02_D3 podr02.bit._D3 +#define PODR02_D2 podr02.bit._D2 +#define PODR02_D1 podr02.bit._D1 +#define PODR02_D0 podr02.bit._D0 +__IO_EXTERN PODR03STR podr03; +#define PODR03 podr03.byte +#define PODR03_D7 podr03.bit._D7 +#define PODR03_D6 podr03.bit._D6 +#define PODR03_D5 podr03.bit._D5 +#define PODR03_D4 podr03.bit._D4 +#define PODR03_D3 podr03.bit._D3 +#define PODR03_D2 podr03.bit._D2 +#define PODR03_D1 podr03.bit._D1 +#define PODR03_D0 podr03.bit._D0 +__IO_EXTERN PODR04STR podr04; +#define PODR04 podr04.byte +#define PODR04_D1 podr04.bit._D1 +#define PODR04_D0 podr04.bit._D0 +__IO_EXTERN PODR05STR podr05; +#define PODR05 podr05.byte +#define PODR05_D7 podr05.bit._D7 +#define PODR05_D6 podr05.bit._D6 +#define PODR05_D5 podr05.bit._D5 +#define PODR05_D4 podr05.bit._D4 +#define PODR05_D3 podr05.bit._D3 +#define PODR05_D2 podr05.bit._D2 +#define PODR05_D1 podr05.bit._D1 +#define PODR05_D0 podr05.bit._D0 +__IO_EXTERN PODR06STR podr06; +#define PODR06 podr06.byte +#define PODR06_D7 podr06.bit._D7 +#define PODR06_D6 podr06.bit._D6 +#define PODR06_D5 podr06.bit._D5 +#define PODR06_D4 podr06.bit._D4 +#define PODR06_D3 podr06.bit._D3 +#define PODR06_D2 podr06.bit._D2 +#define PODR06_D1 podr06.bit._D1 +#define PODR06_D0 podr06.bit._D0 +__IO_EXTERN PODR07STR podr07; +#define PODR07 podr07.byte +#define PODR07_D7 podr07.bit._D7 +#define PODR07_D6 podr07.bit._D6 +#define PODR07_D5 podr07.bit._D5 +#define PODR07_D4 podr07.bit._D4 +#define PODR07_D3 podr07.bit._D3 +#define PODR07_D2 podr07.bit._D2 +#define PODR07_D1 podr07.bit._D1 +#define PODR07_D0 podr07.bit._D0 +__IO_EXTERN PODR08STR podr08; +#define PODR08 podr08.byte +#define PODR08_D7 podr08.bit._D7 +#define PODR08_D6 podr08.bit._D6 +#define PODR08_D5 podr08.bit._D5 +#define PODR08_D4 podr08.bit._D4 +#define PODR08_D3 podr08.bit._D3 +#define PODR08_D2 podr08.bit._D2 +#define PODR08_D1 podr08.bit._D1 +#define PODR08_D0 podr08.bit._D0 +__IO_EXTERN PODR09STR podr09; +#define PODR09 podr09.byte +#define PODR09_D7 podr09.bit._D7 +#define PODR09_D6 podr09.bit._D6 +#define PODR09_D3 podr09.bit._D3 +#define PODR09_D2 podr09.bit._D2 +#define PODR09_D1 podr09.bit._D1 +#define PODR09_D0 podr09.bit._D0 +__IO_EXTERN PODR10STR podr10; +#define PODR10 podr10.byte +#define PODR10_D6 podr10.bit._D6 +#define PODR10_D5 podr10.bit._D5 +#define PODR10_D4 podr10.bit._D4 +#define PODR10_D3 podr10.bit._D3 +#define PODR10_D2 podr10.bit._D2 +#define PODR10_D1 podr10.bit._D1 +__IO_EXTERN PODR13STR podr13; +#define PODR13 podr13.byte +#define PODR13_D2 podr13.bit._D2 +#define PODR13_D1 podr13.bit._D1 +#define PODR13_D0 podr13.bit._D0 +__IO_EXTERN PODR14STR podr14; +#define PODR14 podr14.byte +#define PODR14_D7 podr14.bit._D7 +#define PODR14_D6 podr14.bit._D6 +#define PODR14_D5 podr14.bit._D5 +#define PODR14_D4 podr14.bit._D4 +#define PODR14_D3 podr14.bit._D3 +#define PODR14_D2 podr14.bit._D2 +#define PODR14_D1 podr14.bit._D1 +#define PODR14_D0 podr14.bit._D0 +__IO_EXTERN PODR15STR podr15; +#define PODR15 podr15.byte +#define PODR15_D3 podr15.bit._D3 +#define PODR15_D2 podr15.bit._D2 +#define PODR15_D1 podr15.bit._D1 +#define PODR15_D0 podr15.bit._D0 +__IO_EXTERN PODR16STR podr16; +#define PODR16 podr16.byte +#define PODR16_D7 podr16.bit._D7 +#define PODR16_D6 podr16.bit._D6 +#define PODR16_D5 podr16.bit._D5 +#define PODR16_D4 podr16.bit._D4 +#define PODR16_D3 podr16.bit._D3 +#define PODR16_D2 podr16.bit._D2 +#define PODR16_D1 podr16.bit._D1 +#define PODR16_D0 podr16.bit._D0 +__IO_EXTERN PODR17STR podr17; +#define PODR17 podr17.byte +#define PODR17_D7 podr17.bit._D7 +#define PODR17_D6 podr17.bit._D6 +#define PODR17_D5 podr17.bit._D5 +#define PODR17_D4 podr17.bit._D4 +__IO_EXTERN PODR18STR podr18; +#define PODR18 podr18.byte +#define PODR18_D6 podr18.bit._D6 +#define PODR18_D5 podr18.bit._D5 +#define PODR18_D4 podr18.bit._D4 +#define PODR18_D2 podr18.bit._D2 +#define PODR18_D1 podr18.bit._D1 +#define PODR18_D0 podr18.bit._D0 +__IO_EXTERN PODR19STR podr19; +#define PODR19 podr19.byte +#define PODR19_D6 podr19.bit._D6 +#define PODR19_D5 podr19.bit._D5 +#define PODR19_D4 podr19.bit._D4 +#define PODR19_D2 podr19.bit._D2 +#define PODR19_D1 podr19.bit._D1 +#define PODR19_D0 podr19.bit._D0 +__IO_EXTERN PODR20STR podr20; +#define PODR20 podr20.byte +#define PODR20_D2 podr20.bit._D2 +#define PODR20_D1 podr20.bit._D1 +#define PODR20_D0 podr20.bit._D0 +__IO_EXTERN PODR22STR podr22; +#define PODR22 podr22.byte +#define PODR22_D5 podr22.bit._D5 +#define PODR22_D4 podr22.bit._D4 +#define PODR22_D2 podr22.bit._D2 +#define PODR22_D0 podr22.bit._D0 +__IO_EXTERN PODR23STR podr23; +#define PODR23 podr23.byte +#define PODR23_D5 podr23.bit._D5 +#define PODR23_D4 podr23.bit._D4 +#define PODR23_D3 podr23.bit._D3 +#define PODR23_D2 podr23.bit._D2 +#define PODR23_D1 podr23.bit._D1 +#define PODR23_D0 podr23.bit._D0 +__IO_EXTERN PODR24STR podr24; +#define PODR24 podr24.byte +#define PODR24_D7 podr24.bit._D7 +#define PODR24_D6 podr24.bit._D6 +#define PODR24_D5 podr24.bit._D5 +#define PODR24_D4 podr24.bit._D4 +#define PODR24_D3 podr24.bit._D3 +#define PODR24_D2 podr24.bit._D2 +#define PODR24_D1 podr24.bit._D1 +#define PODR24_D0 podr24.bit._D0 +__IO_EXTERN PODR25STR podr25; +#define PODR25 podr25.byte +#define PODR25_D7 podr25.bit._D7 +#define PODR25_D6 podr25.bit._D6 +#define PODR25_D5 podr25.bit._D5 +#define PODR25_D4 podr25.bit._D4 +#define PODR25_D3 podr25.bit._D3 +#define PODR25_D2 podr25.bit._D2 +#define PODR25_D1 podr25.bit._D1 +#define PODR25_D0 podr25.bit._D0 +__IO_EXTERN PODR26STR podr26; +#define PODR26 podr26.byte +#define PODR26_D7 podr26.bit._D7 +#define PODR26_D6 podr26.bit._D6 +#define PODR26_D5 podr26.bit._D5 +#define PODR26_D4 podr26.bit._D4 +#define PODR26_D3 podr26.bit._D3 +#define PODR26_D2 podr26.bit._D2 +#define PODR26_D1 podr26.bit._D1 +#define PODR26_D0 podr26.bit._D0 +__IO_EXTERN PODR27STR podr27; +#define PODR27 podr27.byte +#define PODR27_D7 podr27.bit._D7 +#define PODR27_D6 podr27.bit._D6 +#define PODR27_D5 podr27.bit._D5 +#define PODR27_D4 podr27.bit._D4 +#define PODR27_D3 podr27.bit._D3 +#define PODR27_D2 podr27.bit._D2 +#define PODR27_D1 podr27.bit._D1 +#define PODR27_D0 podr27.bit._D0 +__IO_EXTERN PODR29STR podr29; +#define PODR29 podr29.byte +#define PODR29_D7 podr29.bit._D7 +#define PODR29_D6 podr29.bit._D6 +#define PODR29_D5 podr29.bit._D5 +#define PODR29_D4 podr29.bit._D4 +#define PODR29_D3 podr29.bit._D3 +#define PODR29_D2 podr29.bit._D2 +#define PODR29_D1 podr29.bit._D1 +#define PODR29_D0 podr29.bit._D0 +__IO_EXTERN PILR00STR pilr00; /* R-bus Port Input Level Select Register */ +#define PILR00 pilr00.byte +#define PILR00_D7 pilr00.bit._D7 +#define PILR00_D6 pilr00.bit._D6 +#define PILR00_D5 pilr00.bit._D5 +#define PILR00_D4 pilr00.bit._D4 +#define PILR00_D3 pilr00.bit._D3 +#define PILR00_D2 pilr00.bit._D2 +#define PILR00_D1 pilr00.bit._D1 +#define PILR00_D0 pilr00.bit._D0 +__IO_EXTERN PILR01STR pilr01; +#define PILR01 pilr01.byte +#define PILR01_D7 pilr01.bit._D7 +#define PILR01_D6 pilr01.bit._D6 +#define PILR01_D5 pilr01.bit._D5 +#define PILR01_D4 pilr01.bit._D4 +#define PILR01_D3 pilr01.bit._D3 +#define PILR01_D2 pilr01.bit._D2 +#define PILR01_D1 pilr01.bit._D1 +#define PILR01_D0 pilr01.bit._D0 +__IO_EXTERN PILR02STR pilr02; +#define PILR02 pilr02.byte +#define PILR02_D7 pilr02.bit._D7 +#define PILR02_D6 pilr02.bit._D6 +#define PILR02_D5 pilr02.bit._D5 +#define PILR02_D4 pilr02.bit._D4 +#define PILR02_D3 pilr02.bit._D3 +#define PILR02_D2 pilr02.bit._D2 +#define PILR02_D1 pilr02.bit._D1 +#define PILR02_D0 pilr02.bit._D0 +__IO_EXTERN PILR03STR pilr03; +#define PILR03 pilr03.byte +#define PILR03_D7 pilr03.bit._D7 +#define PILR03_D6 pilr03.bit._D6 +#define PILR03_D5 pilr03.bit._D5 +#define PILR03_D4 pilr03.bit._D4 +#define PILR03_D3 pilr03.bit._D3 +#define PILR03_D2 pilr03.bit._D2 +#define PILR03_D1 pilr03.bit._D1 +#define PILR03_D0 pilr03.bit._D0 +__IO_EXTERN PILR04STR pilr04; +#define PILR04 pilr04.byte +#define PILR04_D1 pilr04.bit._D1 +#define PILR04_D0 pilr04.bit._D0 +__IO_EXTERN PILR05STR pilr05; +#define PILR05 pilr05.byte +#define PILR05_D7 pilr05.bit._D7 +#define PILR05_D6 pilr05.bit._D6 +#define PILR05_D5 pilr05.bit._D5 +#define PILR05_D4 pilr05.bit._D4 +#define PILR05_D3 pilr05.bit._D3 +#define PILR05_D2 pilr05.bit._D2 +#define PILR05_D1 pilr05.bit._D1 +#define PILR05_D0 pilr05.bit._D0 +__IO_EXTERN PILR06STR pilr06; +#define PILR06 pilr06.byte +#define PILR06_D7 pilr06.bit._D7 +#define PILR06_D6 pilr06.bit._D6 +#define PILR06_D5 pilr06.bit._D5 +#define PILR06_D4 pilr06.bit._D4 +#define PILR06_D3 pilr06.bit._D3 +#define PILR06_D2 pilr06.bit._D2 +#define PILR06_D1 pilr06.bit._D1 +#define PILR06_D0 pilr06.bit._D0 +__IO_EXTERN PILR07STR pilr07; +#define PILR07 pilr07.byte +#define PILR07_D7 pilr07.bit._D7 +#define PILR07_D6 pilr07.bit._D6 +#define PILR07_D5 pilr07.bit._D5 +#define PILR07_D4 pilr07.bit._D4 +#define PILR07_D3 pilr07.bit._D3 +#define PILR07_D2 pilr07.bit._D2 +#define PILR07_D1 pilr07.bit._D1 +#define PILR07_D0 pilr07.bit._D0 +__IO_EXTERN PILR08STR pilr08; +#define PILR08 pilr08.byte +#define PILR08_D7 pilr08.bit._D7 +#define PILR08_D6 pilr08.bit._D6 +#define PILR08_D5 pilr08.bit._D5 +#define PILR08_D4 pilr08.bit._D4 +#define PILR08_D3 pilr08.bit._D3 +#define PILR08_D2 pilr08.bit._D2 +#define PILR08_D1 pilr08.bit._D1 +#define PILR08_D0 pilr08.bit._D0 +__IO_EXTERN PILR09STR pilr09; +#define PILR09 pilr09.byte +#define PILR09_D7 pilr09.bit._D7 +#define PILR09_D6 pilr09.bit._D6 +#define PILR09_D3 pilr09.bit._D3 +#define PILR09_D2 pilr09.bit._D2 +#define PILR09_D1 pilr09.bit._D1 +#define PILR09_D0 pilr09.bit._D0 +__IO_EXTERN PILR10STR pilr10; +#define PILR10 pilr10.byte +#define PILR10_D6 pilr10.bit._D6 +#define PILR10_D5 pilr10.bit._D5 +#define PILR10_D4 pilr10.bit._D4 +#define PILR10_D3 pilr10.bit._D3 +#define PILR10_D2 pilr10.bit._D2 +#define PILR10_D1 pilr10.bit._D1 +__IO_EXTERN PILR13STR pilr13; +#define PILR13 pilr13.byte +#define PILR13_D2 pilr13.bit._D2 +#define PILR13_D1 pilr13.bit._D1 +#define PILR13_D0 pilr13.bit._D0 +__IO_EXTERN PILR14STR pilr14; +#define PILR14 pilr14.byte +#define PILR14_D7 pilr14.bit._D7 +#define PILR14_D6 pilr14.bit._D6 +#define PILR14_D5 pilr14.bit._D5 +#define PILR14_D4 pilr14.bit._D4 +#define PILR14_D3 pilr14.bit._D3 +#define PILR14_D2 pilr14.bit._D2 +#define PILR14_D1 pilr14.bit._D1 +#define PILR14_D0 pilr14.bit._D0 +__IO_EXTERN PILR15STR pilr15; +#define PILR15 pilr15.byte +#define PILR15_D3 pilr15.bit._D3 +#define PILR15_D2 pilr15.bit._D2 +#define PILR15_D1 pilr15.bit._D1 +#define PILR15_D0 pilr15.bit._D0 +__IO_EXTERN PILR16STR pilr16; +#define PILR16 pilr16.byte +#define PILR16_D7 pilr16.bit._D7 +#define PILR16_D6 pilr16.bit._D6 +#define PILR16_D5 pilr16.bit._D5 +#define PILR16_D4 pilr16.bit._D4 +#define PILR16_D3 pilr16.bit._D3 +#define PILR16_D2 pilr16.bit._D2 +#define PILR16_D1 pilr16.bit._D1 +#define PILR16_D0 pilr16.bit._D0 +__IO_EXTERN PILR17STR pilr17; +#define PILR17 pilr17.byte +#define PILR17_D7 pilr17.bit._D7 +#define PILR17_D6 pilr17.bit._D6 +#define PILR17_D5 pilr17.bit._D5 +#define PILR17_D4 pilr17.bit._D4 +__IO_EXTERN PILR18STR pilr18; +#define PILR18 pilr18.byte +#define PILR18_D6 pilr18.bit._D6 +#define PILR18_D5 pilr18.bit._D5 +#define PILR18_D4 pilr18.bit._D4 +#define PILR18_D2 pilr18.bit._D2 +#define PILR18_D1 pilr18.bit._D1 +#define PILR18_D0 pilr18.bit._D0 +__IO_EXTERN PILR19STR pilr19; +#define PILR19 pilr19.byte +#define PILR19_D6 pilr19.bit._D6 +#define PILR19_D5 pilr19.bit._D5 +#define PILR19_D4 pilr19.bit._D4 +#define PILR19_D2 pilr19.bit._D2 +#define PILR19_D1 pilr19.bit._D1 +#define PILR19_D0 pilr19.bit._D0 +__IO_EXTERN PILR20STR pilr20; +#define PILR20 pilr20.byte +#define PILR20_D2 pilr20.bit._D2 +#define PILR20_D1 pilr20.bit._D1 +#define PILR20_D0 pilr20.bit._D0 +__IO_EXTERN PILR22STR pilr22; +#define PILR22 pilr22.byte +#define PILR22_D5 pilr22.bit._D5 +#define PILR22_D4 pilr22.bit._D4 +#define PILR22_D2 pilr22.bit._D2 +#define PILR22_D0 pilr22.bit._D0 +__IO_EXTERN PILR23STR pilr23; +#define PILR23 pilr23.byte +#define PILR23_D5 pilr23.bit._D5 +#define PILR23_D4 pilr23.bit._D4 +#define PILR23_D3 pilr23.bit._D3 +#define PILR23_D2 pilr23.bit._D2 +#define PILR23_D1 pilr23.bit._D1 +#define PILR23_D0 pilr23.bit._D0 +__IO_EXTERN PILR24STR pilr24; +#define PILR24 pilr24.byte +#define PILR24_D7 pilr24.bit._D7 +#define PILR24_D6 pilr24.bit._D6 +#define PILR24_D5 pilr24.bit._D5 +#define PILR24_D4 pilr24.bit._D4 +#define PILR24_D3 pilr24.bit._D3 +#define PILR24_D2 pilr24.bit._D2 +#define PILR24_D1 pilr24.bit._D1 +#define PILR24_D0 pilr24.bit._D0 +__IO_EXTERN PILR25STR pilr25; +#define PILR25 pilr25.byte +#define PILR25_D7 pilr25.bit._D7 +#define PILR25_D6 pilr25.bit._D6 +#define PILR25_D5 pilr25.bit._D5 +#define PILR25_D4 pilr25.bit._D4 +#define PILR25_D3 pilr25.bit._D3 +#define PILR25_D2 pilr25.bit._D2 +#define PILR25_D1 pilr25.bit._D1 +#define PILR25_D0 pilr25.bit._D0 +__IO_EXTERN PILR26STR pilr26; +#define PILR26 pilr26.byte +#define PILR26_D7 pilr26.bit._D7 +#define PILR26_D6 pilr26.bit._D6 +#define PILR26_D5 pilr26.bit._D5 +#define PILR26_D4 pilr26.bit._D4 +#define PILR26_D3 pilr26.bit._D3 +#define PILR26_D2 pilr26.bit._D2 +#define PILR26_D1 pilr26.bit._D1 +#define PILR26_D0 pilr26.bit._D0 +__IO_EXTERN PILR27STR pilr27; +#define PILR27 pilr27.byte +#define PILR27_D7 pilr27.bit._D7 +#define PILR27_D6 pilr27.bit._D6 +#define PILR27_D5 pilr27.bit._D5 +#define PILR27_D4 pilr27.bit._D4 +#define PILR27_D3 pilr27.bit._D3 +#define PILR27_D2 pilr27.bit._D2 +#define PILR27_D1 pilr27.bit._D1 +#define PILR27_D0 pilr27.bit._D0 +__IO_EXTERN PILR29STR pilr29; +#define PILR29 pilr29.byte +#define PILR29_D7 pilr29.bit._D7 +#define PILR29_D6 pilr29.bit._D6 +#define PILR29_D5 pilr29.bit._D5 +#define PILR29_D4 pilr29.bit._D4 +#define PILR29_D3 pilr29.bit._D3 +#define PILR29_D2 pilr29.bit._D2 +#define PILR29_D1 pilr29.bit._D1 +#define PILR29_D0 pilr29.bit._D0 +__IO_EXTERN EPILR00STR epilr00; /* R-bus Port Extra Input Level Select Register */ +#define EPILR00 epilr00.byte +#define EPILR00_D7 epilr00.bit._D7 +#define EPILR00_D6 epilr00.bit._D6 +#define EPILR00_D5 epilr00.bit._D5 +#define EPILR00_D4 epilr00.bit._D4 +#define EPILR00_D3 epilr00.bit._D3 +#define EPILR00_D2 epilr00.bit._D2 +#define EPILR00_D1 epilr00.bit._D1 +#define EPILR00_D0 epilr00.bit._D0 +__IO_EXTERN EPILR01STR epilr01; +#define EPILR01 epilr01.byte +#define EPILR01_D7 epilr01.bit._D7 +#define EPILR01_D6 epilr01.bit._D6 +#define EPILR01_D5 epilr01.bit._D5 +#define EPILR01_D4 epilr01.bit._D4 +#define EPILR01_D3 epilr01.bit._D3 +#define EPILR01_D2 epilr01.bit._D2 +#define EPILR01_D1 epilr01.bit._D1 +#define EPILR01_D0 epilr01.bit._D0 +__IO_EXTERN EPILR02STR epilr02; +#define EPILR02 epilr02.byte +#define EPILR02_D7 epilr02.bit._D7 +#define EPILR02_D6 epilr02.bit._D6 +#define EPILR02_D5 epilr02.bit._D5 +#define EPILR02_D4 epilr02.bit._D4 +#define EPILR02_D3 epilr02.bit._D3 +#define EPILR02_D2 epilr02.bit._D2 +#define EPILR02_D1 epilr02.bit._D1 +#define EPILR02_D0 epilr02.bit._D0 +__IO_EXTERN EPILR03STR epilr03; +#define EPILR03 epilr03.byte +#define EPILR03_D7 epilr03.bit._D7 +#define EPILR03_D6 epilr03.bit._D6 +#define EPILR03_D5 epilr03.bit._D5 +#define EPILR03_D4 epilr03.bit._D4 +#define EPILR03_D3 epilr03.bit._D3 +#define EPILR03_D2 epilr03.bit._D2 +#define EPILR03_D1 epilr03.bit._D1 +#define EPILR03_D0 epilr03.bit._D0 +__IO_EXTERN EPILR04STR epilr04; +#define EPILR04 epilr04.byte +#define EPILR04_D1 epilr04.bit._D1 +#define EPILR04_D0 epilr04.bit._D0 +__IO_EXTERN EPILR05STR epilr05; +#define EPILR05 epilr05.byte +#define EPILR05_D7 epilr05.bit._D7 +#define EPILR05_D6 epilr05.bit._D6 +#define EPILR05_D5 epilr05.bit._D5 +#define EPILR05_D4 epilr05.bit._D4 +#define EPILR05_D3 epilr05.bit._D3 +#define EPILR05_D2 epilr05.bit._D2 +#define EPILR05_D1 epilr05.bit._D1 +#define EPILR05_D0 epilr05.bit._D0 +__IO_EXTERN EPILR06STR epilr06; +#define EPILR06 epilr06.byte +#define EPILR06_D7 epilr06.bit._D7 +#define EPILR06_D6 epilr06.bit._D6 +#define EPILR06_D5 epilr06.bit._D5 +#define EPILR06_D4 epilr06.bit._D4 +#define EPILR06_D3 epilr06.bit._D3 +#define EPILR06_D2 epilr06.bit._D2 +#define EPILR06_D1 epilr06.bit._D1 +#define EPILR06_D0 epilr06.bit._D0 +__IO_EXTERN EPILR07STR epilr07; +#define EPILR07 epilr07.byte +#define EPILR07_D7 epilr07.bit._D7 +#define EPILR07_D6 epilr07.bit._D6 +#define EPILR07_D5 epilr07.bit._D5 +#define EPILR07_D4 epilr07.bit._D4 +#define EPILR07_D3 epilr07.bit._D3 +#define EPILR07_D2 epilr07.bit._D2 +#define EPILR07_D1 epilr07.bit._D1 +#define EPILR07_D0 epilr07.bit._D0 +__IO_EXTERN EPILR08STR epilr08; +#define EPILR08 epilr08.byte +#define EPILR08_D7 epilr08.bit._D7 +#define EPILR08_D6 epilr08.bit._D6 +#define EPILR08_D5 epilr08.bit._D5 +#define EPILR08_D4 epilr08.bit._D4 +#define EPILR08_D3 epilr08.bit._D3 +#define EPILR08_D2 epilr08.bit._D2 +#define EPILR08_D1 epilr08.bit._D1 +#define EPILR08_D0 epilr08.bit._D0 +__IO_EXTERN EPILR09STR epilr09; +#define EPILR09 epilr09.byte +#define EPILR09_D7 epilr09.bit._D7 +#define EPILR09_D6 epilr09.bit._D6 +#define EPILR09_D3 epilr09.bit._D3 +#define EPILR09_D2 epilr09.bit._D2 +#define EPILR09_D1 epilr09.bit._D1 +#define EPILR09_D0 epilr09.bit._D0 +__IO_EXTERN EPILR10STR epilr10; +#define EPILR10 epilr10.byte +#define EPILR10_D6 epilr10.bit._D6 +#define EPILR10_D5 epilr10.bit._D5 +#define EPILR10_D4 epilr10.bit._D4 +#define EPILR10_D3 epilr10.bit._D3 +#define EPILR10_D2 epilr10.bit._D2 +#define EPILR10_D1 epilr10.bit._D1 +__IO_EXTERN EPILR13STR epilr13; +#define EPILR13 epilr13.byte +#define EPILR13_D2 epilr13.bit._D2 +#define EPILR13_D1 epilr13.bit._D1 +#define EPILR13_D0 epilr13.bit._D0 +__IO_EXTERN EPILR14STR epilr14; +#define EPILR14 epilr14.byte +#define EPILR14_D7 epilr14.bit._D7 +#define EPILR14_D6 epilr14.bit._D6 +#define EPILR14_D5 epilr14.bit._D5 +#define EPILR14_D4 epilr14.bit._D4 +#define EPILR14_D3 epilr14.bit._D3 +#define EPILR14_D2 epilr14.bit._D2 +#define EPILR14_D1 epilr14.bit._D1 +#define EPILR14_D0 epilr14.bit._D0 +__IO_EXTERN EPILR15STR epilr15; +#define EPILR15 epilr15.byte +#define EPILR15_D3 epilr15.bit._D3 +#define EPILR15_D2 epilr15.bit._D2 +#define EPILR15_D1 epilr15.bit._D1 +#define EPILR15_D0 epilr15.bit._D0 +__IO_EXTERN EPILR16STR epilr16; +#define EPILR16 epilr16.byte +#define EPILR16_D7 epilr16.bit._D7 +#define EPILR16_D6 epilr16.bit._D6 +#define EPILR16_D5 epilr16.bit._D5 +#define EPILR16_D4 epilr16.bit._D4 +#define EPILR16_D3 epilr16.bit._D3 +#define EPILR16_D2 epilr16.bit._D2 +#define EPILR16_D1 epilr16.bit._D1 +#define EPILR16_D0 epilr16.bit._D0 +__IO_EXTERN EPILR17STR epilr17; +#define EPILR17 epilr17.byte +#define EPILR17_D7 epilr17.bit._D7 +#define EPILR17_D6 epilr17.bit._D6 +#define EPILR17_D5 epilr17.bit._D5 +#define EPILR17_D4 epilr17.bit._D4 +__IO_EXTERN EPILR18STR epilr18; +#define EPILR18 epilr18.byte +#define EPILR18_D6 epilr18.bit._D6 +#define EPILR18_D5 epilr18.bit._D5 +#define EPILR18_D4 epilr18.bit._D4 +#define EPILR18_D2 epilr18.bit._D2 +#define EPILR18_D1 epilr18.bit._D1 +#define EPILR18_D0 epilr18.bit._D0 +__IO_EXTERN EPILR19STR epilr19; +#define EPILR19 epilr19.byte +#define EPILR19_D6 epilr19.bit._D6 +#define EPILR19_D5 epilr19.bit._D5 +#define EPILR19_D4 epilr19.bit._D4 +#define EPILR19_D2 epilr19.bit._D2 +#define EPILR19_D1 epilr19.bit._D1 +#define EPILR19_D0 epilr19.bit._D0 +__IO_EXTERN EPILR20STR epilr20; +#define EPILR20 epilr20.byte +#define EPILR20_D2 epilr20.bit._D2 +#define EPILR20_D1 epilr20.bit._D1 +#define EPILR20_D0 epilr20.bit._D0 +__IO_EXTERN EPILR22STR epilr22; +#define EPILR22 epilr22.byte +#define EPILR22_D5 epilr22.bit._D5 +#define EPILR22_D4 epilr22.bit._D4 +#define EPILR22_D2 epilr22.bit._D2 +#define EPILR22_D0 epilr22.bit._D0 +__IO_EXTERN EPILR23STR epilr23; +#define EPILR23 epilr23.byte +#define EPILR23_D5 epilr23.bit._D5 +#define EPILR23_D4 epilr23.bit._D4 +#define EPILR23_D3 epilr23.bit._D3 +#define EPILR23_D2 epilr23.bit._D2 +#define EPILR23_D1 epilr23.bit._D1 +#define EPILR23_D0 epilr23.bit._D0 +__IO_EXTERN EPILR24STR epilr24; +#define EPILR24 epilr24.byte +#define EPILR24_D7 epilr24.bit._D7 +#define EPILR24_D6 epilr24.bit._D6 +#define EPILR24_D5 epilr24.bit._D5 +#define EPILR24_D4 epilr24.bit._D4 +#define EPILR24_D3 epilr24.bit._D3 +#define EPILR24_D2 epilr24.bit._D2 +#define EPILR24_D1 epilr24.bit._D1 +#define EPILR24_D0 epilr24.bit._D0 +__IO_EXTERN EPILR25STR epilr25; +#define EPILR25 epilr25.byte +#define EPILR25_D7 epilr25.bit._D7 +#define EPILR25_D6 epilr25.bit._D6 +#define EPILR25_D5 epilr25.bit._D5 +#define EPILR25_D4 epilr25.bit._D4 +#define EPILR25_D3 epilr25.bit._D3 +#define EPILR25_D2 epilr25.bit._D2 +#define EPILR25_D1 epilr25.bit._D1 +#define EPILR25_D0 epilr25.bit._D0 +__IO_EXTERN EPILR26STR epilr26; +#define EPILR26 epilr26.byte +#define EPILR26_D7 epilr26.bit._D7 +#define EPILR26_D6 epilr26.bit._D6 +#define EPILR26_D5 epilr26.bit._D5 +#define EPILR26_D4 epilr26.bit._D4 +#define EPILR26_D3 epilr26.bit._D3 +#define EPILR26_D2 epilr26.bit._D2 +#define EPILR26_D1 epilr26.bit._D1 +#define EPILR26_D0 epilr26.bit._D0 +__IO_EXTERN EPILR27STR epilr27; +#define EPILR27 epilr27.byte +#define EPILR27_D7 epilr27.bit._D7 +#define EPILR27_D6 epilr27.bit._D6 +#define EPILR27_D5 epilr27.bit._D5 +#define EPILR27_D4 epilr27.bit._D4 +#define EPILR27_D3 epilr27.bit._D3 +#define EPILR27_D2 epilr27.bit._D2 +#define EPILR27_D1 epilr27.bit._D1 +#define EPILR27_D0 epilr27.bit._D0 +__IO_EXTERN EPILR29STR epilr29; +#define EPILR29 epilr29.byte +#define EPILR29_D7 epilr29.bit._D7 +#define EPILR29_D6 epilr29.bit._D6 +#define EPILR29_D5 epilr29.bit._D5 +#define EPILR29_D4 epilr29.bit._D4 +#define EPILR29_D3 epilr29.bit._D3 +#define EPILR29_D2 epilr29.bit._D2 +#define EPILR29_D1 epilr29.bit._D1 +#define EPILR29_D0 epilr29.bit._D0 +__IO_EXTERN PPER00STR pper00; /* R-bus Port Pull-Up/Down Enable Register */ +#define PPER00 pper00.byte +#define PPER00_D7 pper00.bit._D7 +#define PPER00_D6 pper00.bit._D6 +#define PPER00_D5 pper00.bit._D5 +#define PPER00_D4 pper00.bit._D4 +#define PPER00_D3 pper00.bit._D3 +#define PPER00_D2 pper00.bit._D2 +#define PPER00_D1 pper00.bit._D1 +#define PPER00_D0 pper00.bit._D0 +__IO_EXTERN PPER01STR pper01; +#define PPER01 pper01.byte +#define PPER01_D7 pper01.bit._D7 +#define PPER01_D6 pper01.bit._D6 +#define PPER01_D5 pper01.bit._D5 +#define PPER01_D4 pper01.bit._D4 +#define PPER01_D3 pper01.bit._D3 +#define PPER01_D2 pper01.bit._D2 +#define PPER01_D1 pper01.bit._D1 +#define PPER01_D0 pper01.bit._D0 +__IO_EXTERN PPER02STR pper02; +#define PPER02 pper02.byte +#define PPER02_D7 pper02.bit._D7 +#define PPER02_D6 pper02.bit._D6 +#define PPER02_D5 pper02.bit._D5 +#define PPER02_D4 pper02.bit._D4 +#define PPER02_D3 pper02.bit._D3 +#define PPER02_D2 pper02.bit._D2 +#define PPER02_D1 pper02.bit._D1 +#define PPER02_D0 pper02.bit._D0 +__IO_EXTERN PPER03STR pper03; +#define PPER03 pper03.byte +#define PPER03_D7 pper03.bit._D7 +#define PPER03_D6 pper03.bit._D6 +#define PPER03_D5 pper03.bit._D5 +#define PPER03_D4 pper03.bit._D4 +#define PPER03_D3 pper03.bit._D3 +#define PPER03_D2 pper03.bit._D2 +#define PPER03_D1 pper03.bit._D1 +#define PPER03_D0 pper03.bit._D0 +__IO_EXTERN PPER04STR pper04; +#define PPER04 pper04.byte +#define PPER04_D1 pper04.bit._D1 +#define PPER04_D0 pper04.bit._D0 +__IO_EXTERN PPER05STR pper05; +#define PPER05 pper05.byte +#define PPER05_D7 pper05.bit._D7 +#define PPER05_D6 pper05.bit._D6 +#define PPER05_D5 pper05.bit._D5 +#define PPER05_D4 pper05.bit._D4 +#define PPER05_D3 pper05.bit._D3 +#define PPER05_D2 pper05.bit._D2 +#define PPER05_D1 pper05.bit._D1 +#define PPER05_D0 pper05.bit._D0 +__IO_EXTERN PPER06STR pper06; +#define PPER06 pper06.byte +#define PPER06_D7 pper06.bit._D7 +#define PPER06_D6 pper06.bit._D6 +#define PPER06_D5 pper06.bit._D5 +#define PPER06_D4 pper06.bit._D4 +#define PPER06_D3 pper06.bit._D3 +#define PPER06_D2 pper06.bit._D2 +#define PPER06_D1 pper06.bit._D1 +#define PPER06_D0 pper06.bit._D0 +__IO_EXTERN PPER07STR pper07; +#define PPER07 pper07.byte +#define PPER07_D7 pper07.bit._D7 +#define PPER07_D6 pper07.bit._D6 +#define PPER07_D5 pper07.bit._D5 +#define PPER07_D4 pper07.bit._D4 +#define PPER07_D3 pper07.bit._D3 +#define PPER07_D2 pper07.bit._D2 +#define PPER07_D1 pper07.bit._D1 +#define PPER07_D0 pper07.bit._D0 +__IO_EXTERN PPER08STR pper08; +#define PPER08 pper08.byte +#define PPER08_D7 pper08.bit._D7 +#define PPER08_D6 pper08.bit._D6 +#define PPER08_D5 pper08.bit._D5 +#define PPER08_D4 pper08.bit._D4 +#define PPER08_D3 pper08.bit._D3 +#define PPER08_D2 pper08.bit._D2 +#define PPER08_D1 pper08.bit._D1 +#define PPER08_D0 pper08.bit._D0 +__IO_EXTERN PPER09STR pper09; +#define PPER09 pper09.byte +#define PPER09_D7 pper09.bit._D7 +#define PPER09_D6 pper09.bit._D6 +#define PPER09_D3 pper09.bit._D3 +#define PPER09_D2 pper09.bit._D2 +#define PPER09_D1 pper09.bit._D1 +#define PPER09_D0 pper09.bit._D0 +__IO_EXTERN PPER10STR pper10; +#define PPER10 pper10.byte +#define PPER10_D6 pper10.bit._D6 +#define PPER10_D5 pper10.bit._D5 +#define PPER10_D4 pper10.bit._D4 +#define PPER10_D3 pper10.bit._D3 +#define PPER10_D2 pper10.bit._D2 +#define PPER10_D1 pper10.bit._D1 +__IO_EXTERN PPER13STR pper13; +#define PPER13 pper13.byte +#define PPER13_D2 pper13.bit._D2 +#define PPER13_D1 pper13.bit._D1 +#define PPER13_D0 pper13.bit._D0 +__IO_EXTERN PPER14STR pper14; +#define PPER14 pper14.byte +#define PPER14_D7 pper14.bit._D7 +#define PPER14_D6 pper14.bit._D6 +#define PPER14_D5 pper14.bit._D5 +#define PPER14_D4 pper14.bit._D4 +#define PPER14_D3 pper14.bit._D3 +#define PPER14_D2 pper14.bit._D2 +#define PPER14_D1 pper14.bit._D1 +#define PPER14_D0 pper14.bit._D0 +__IO_EXTERN PPER15STR pper15; +#define PPER15 pper15.byte +#define PPER15_D3 pper15.bit._D3 +#define PPER15_D2 pper15.bit._D2 +#define PPER15_D1 pper15.bit._D1 +#define PPER15_D0 pper15.bit._D0 +__IO_EXTERN PPER16STR pper16; +#define PPER16 pper16.byte +#define PPER16_D7 pper16.bit._D7 +#define PPER16_D6 pper16.bit._D6 +#define PPER16_D5 pper16.bit._D5 +#define PPER16_D4 pper16.bit._D4 +#define PPER16_D3 pper16.bit._D3 +#define PPER16_D2 pper16.bit._D2 +#define PPER16_D1 pper16.bit._D1 +#define PPER16_D0 pper16.bit._D0 +__IO_EXTERN PPER17STR pper17; +#define PPER17 pper17.byte +#define PPER17_D7 pper17.bit._D7 +#define PPER17_D6 pper17.bit._D6 +#define PPER17_D5 pper17.bit._D5 +#define PPER17_D4 pper17.bit._D4 +__IO_EXTERN PPER18STR pper18; +#define PPER18 pper18.byte +#define PPER18_D6 pper18.bit._D6 +#define PPER18_D5 pper18.bit._D5 +#define PPER18_D4 pper18.bit._D4 +#define PPER18_D2 pper18.bit._D2 +#define PPER18_D1 pper18.bit._D1 +#define PPER18_D0 pper18.bit._D0 +__IO_EXTERN PPER19STR pper19; +#define PPER19 pper19.byte +#define PPER19_D6 pper19.bit._D6 +#define PPER19_D5 pper19.bit._D5 +#define PPER19_D4 pper19.bit._D4 +#define PPER19_D2 pper19.bit._D2 +#define PPER19_D1 pper19.bit._D1 +#define PPER19_D0 pper19.bit._D0 +__IO_EXTERN PPER20STR pper20; +#define PPER20 pper20.byte +#define PPER20_D2 pper20.bit._D2 +#define PPER20_D1 pper20.bit._D1 +#define PPER20_D0 pper20.bit._D0 +__IO_EXTERN PPER22STR pper22; +#define PPER22 pper22.byte +#define PPER22_D5 pper22.bit._D5 +#define PPER22_D4 pper22.bit._D4 +#define PPER22_D2 pper22.bit._D2 +#define PPER22_D0 pper22.bit._D0 +__IO_EXTERN PPER23STR pper23; +#define PPER23 pper23.byte +#define PPER23_D5 pper23.bit._D5 +#define PPER23_D4 pper23.bit._D4 +#define PPER23_D3 pper23.bit._D3 +#define PPER23_D2 pper23.bit._D2 +#define PPER23_D1 pper23.bit._D1 +#define PPER23_D0 pper23.bit._D0 +__IO_EXTERN PPER24STR pper24; +#define PPER24 pper24.byte +#define PPER24_D7 pper24.bit._D7 +#define PPER24_D6 pper24.bit._D6 +#define PPER24_D5 pper24.bit._D5 +#define PPER24_D4 pper24.bit._D4 +#define PPER24_D3 pper24.bit._D3 +#define PPER24_D2 pper24.bit._D2 +#define PPER24_D1 pper24.bit._D1 +#define PPER24_D0 pper24.bit._D0 +__IO_EXTERN PPER25STR pper25; +#define PPER25 pper25.byte +#define PPER25_D7 pper25.bit._D7 +#define PPER25_D6 pper25.bit._D6 +#define PPER25_D5 pper25.bit._D5 +#define PPER25_D4 pper25.bit._D4 +#define PPER25_D3 pper25.bit._D3 +#define PPER25_D2 pper25.bit._D2 +#define PPER25_D1 pper25.bit._D1 +#define PPER25_D0 pper25.bit._D0 +__IO_EXTERN PPER26STR pper26; +#define PPER26 pper26.byte +#define PPER26_D7 pper26.bit._D7 +#define PPER26_D6 pper26.bit._D6 +#define PPER26_D5 pper26.bit._D5 +#define PPER26_D4 pper26.bit._D4 +#define PPER26_D3 pper26.bit._D3 +#define PPER26_D2 pper26.bit._D2 +#define PPER26_D1 pper26.bit._D1 +#define PPER26_D0 pper26.bit._D0 +__IO_EXTERN PPER27STR pper27; +#define PPER27 pper27.byte +#define PPER27_D7 pper27.bit._D7 +#define PPER27_D6 pper27.bit._D6 +#define PPER27_D5 pper27.bit._D5 +#define PPER27_D4 pper27.bit._D4 +#define PPER27_D3 pper27.bit._D3 +#define PPER27_D2 pper27.bit._D2 +#define PPER27_D1 pper27.bit._D1 +#define PPER27_D0 pper27.bit._D0 +__IO_EXTERN PPER29STR pper29; +#define PPER29 pper29.byte +#define PPER29_D7 pper29.bit._D7 +#define PPER29_D6 pper29.bit._D6 +#define PPER29_D5 pper29.bit._D5 +#define PPER29_D4 pper29.bit._D4 +#define PPER29_D3 pper29.bit._D3 +#define PPER29_D2 pper29.bit._D2 +#define PPER29_D1 pper29.bit._D1 +#define PPER29_D0 pper29.bit._D0 +__IO_EXTERN PPCR00STR ppcr00; /* R-bus Port Pull-Up/Down Control Register */ +#define PPCR00 ppcr00.byte +#define PPCR00_D7 ppcr00.bit._D7 +#define PPCR00_D6 ppcr00.bit._D6 +#define PPCR00_D5 ppcr00.bit._D5 +#define PPCR00_D4 ppcr00.bit._D4 +#define PPCR00_D3 ppcr00.bit._D3 +#define PPCR00_D2 ppcr00.bit._D2 +#define PPCR00_D1 ppcr00.bit._D1 +#define PPCR00_D0 ppcr00.bit._D0 +__IO_EXTERN PPCR01STR ppcr01; +#define PPCR01 ppcr01.byte +#define PPCR01_D7 ppcr01.bit._D7 +#define PPCR01_D6 ppcr01.bit._D6 +#define PPCR01_D5 ppcr01.bit._D5 +#define PPCR01_D4 ppcr01.bit._D4 +#define PPCR01_D3 ppcr01.bit._D3 +#define PPCR01_D2 ppcr01.bit._D2 +#define PPCR01_D1 ppcr01.bit._D1 +#define PPCR01_D0 ppcr01.bit._D0 +__IO_EXTERN PPCR02STR ppcr02; +#define PPCR02 ppcr02.byte +#define PPCR02_D7 ppcr02.bit._D7 +#define PPCR02_D6 ppcr02.bit._D6 +#define PPCR02_D5 ppcr02.bit._D5 +#define PPCR02_D4 ppcr02.bit._D4 +#define PPCR02_D3 ppcr02.bit._D3 +#define PPCR02_D2 ppcr02.bit._D2 +#define PPCR02_D1 ppcr02.bit._D1 +#define PPCR02_D0 ppcr02.bit._D0 +__IO_EXTERN PPCR03STR ppcr03; +#define PPCR03 ppcr03.byte +#define PPCR03_D7 ppcr03.bit._D7 +#define PPCR03_D6 ppcr03.bit._D6 +#define PPCR03_D5 ppcr03.bit._D5 +#define PPCR03_D4 ppcr03.bit._D4 +#define PPCR03_D3 ppcr03.bit._D3 +#define PPCR03_D2 ppcr03.bit._D2 +#define PPCR03_D1 ppcr03.bit._D1 +#define PPCR03_D0 ppcr03.bit._D0 +__IO_EXTERN PPCR04STR ppcr04; +#define PPCR04 ppcr04.byte +#define PPCR04_D1 ppcr04.bit._D1 +#define PPCR04_D0 ppcr04.bit._D0 +__IO_EXTERN PPCR05STR ppcr05; +#define PPCR05 ppcr05.byte +#define PPCR05_D7 ppcr05.bit._D7 +#define PPCR05_D6 ppcr05.bit._D6 +#define PPCR05_D5 ppcr05.bit._D5 +#define PPCR05_D4 ppcr05.bit._D4 +#define PPCR05_D3 ppcr05.bit._D3 +#define PPCR05_D2 ppcr05.bit._D2 +#define PPCR05_D1 ppcr05.bit._D1 +#define PPCR05_D0 ppcr05.bit._D0 +__IO_EXTERN PPCR06STR ppcr06; +#define PPCR06 ppcr06.byte +#define PPCR06_D7 ppcr06.bit._D7 +#define PPCR06_D6 ppcr06.bit._D6 +#define PPCR06_D5 ppcr06.bit._D5 +#define PPCR06_D4 ppcr06.bit._D4 +#define PPCR06_D3 ppcr06.bit._D3 +#define PPCR06_D2 ppcr06.bit._D2 +#define PPCR06_D1 ppcr06.bit._D1 +#define PPCR06_D0 ppcr06.bit._D0 +__IO_EXTERN PPCR07STR ppcr07; +#define PPCR07 ppcr07.byte +#define PPCR07_D7 ppcr07.bit._D7 +#define PPCR07_D6 ppcr07.bit._D6 +#define PPCR07_D5 ppcr07.bit._D5 +#define PPCR07_D4 ppcr07.bit._D4 +#define PPCR07_D3 ppcr07.bit._D3 +#define PPCR07_D2 ppcr07.bit._D2 +#define PPCR07_D1 ppcr07.bit._D1 +#define PPCR07_D0 ppcr07.bit._D0 +__IO_EXTERN PPCR08STR ppcr08; +#define PPCR08 ppcr08.byte +#define PPCR08_D7 ppcr08.bit._D7 +#define PPCR08_D6 ppcr08.bit._D6 +#define PPCR08_D5 ppcr08.bit._D5 +#define PPCR08_D4 ppcr08.bit._D4 +#define PPCR08_D3 ppcr08.bit._D3 +#define PPCR08_D2 ppcr08.bit._D2 +#define PPCR08_D1 ppcr08.bit._D1 +#define PPCR08_D0 ppcr08.bit._D0 +__IO_EXTERN PPCR09STR ppcr09; +#define PPCR09 ppcr09.byte +#define PPCR09_D7 ppcr09.bit._D7 +#define PPCR09_D6 ppcr09.bit._D6 +#define PPCR09_D3 ppcr09.bit._D3 +#define PPCR09_D2 ppcr09.bit._D2 +#define PPCR09_D1 ppcr09.bit._D1 +#define PPCR09_D0 ppcr09.bit._D0 +__IO_EXTERN PPCR10STR ppcr10; +#define PPCR10 ppcr10.byte +#define PPCR10_D6 ppcr10.bit._D6 +#define PPCR10_D5 ppcr10.bit._D5 +#define PPCR10_D4 ppcr10.bit._D4 +#define PPCR10_D3 ppcr10.bit._D3 +#define PPCR10_D2 ppcr10.bit._D2 +#define PPCR10_D1 ppcr10.bit._D1 +__IO_EXTERN PPCR13STR ppcr13; +#define PPCR13 ppcr13.byte +#define PPCR13_D2 ppcr13.bit._D2 +#define PPCR13_D1 ppcr13.bit._D1 +#define PPCR13_D0 ppcr13.bit._D0 +__IO_EXTERN PPCR14STR ppcr14; +#define PPCR14 ppcr14.byte +#define PPCR14_D7 ppcr14.bit._D7 +#define PPCR14_D6 ppcr14.bit._D6 +#define PPCR14_D5 ppcr14.bit._D5 +#define PPCR14_D4 ppcr14.bit._D4 +#define PPCR14_D3 ppcr14.bit._D3 +#define PPCR14_D2 ppcr14.bit._D2 +#define PPCR14_D1 ppcr14.bit._D1 +#define PPCR14_D0 ppcr14.bit._D0 +__IO_EXTERN PPCR15STR ppcr15; +#define PPCR15 ppcr15.byte +#define PPCR15_D3 ppcr15.bit._D3 +#define PPCR15_D2 ppcr15.bit._D2 +#define PPCR15_D1 ppcr15.bit._D1 +#define PPCR15_D0 ppcr15.bit._D0 +__IO_EXTERN PPCR16STR ppcr16; +#define PPCR16 ppcr16.byte +#define PPCR16_D7 ppcr16.bit._D7 +#define PPCR16_D6 ppcr16.bit._D6 +#define PPCR16_D5 ppcr16.bit._D5 +#define PPCR16_D4 ppcr16.bit._D4 +#define PPCR16_D3 ppcr16.bit._D3 +#define PPCR16_D2 ppcr16.bit._D2 +#define PPCR16_D1 ppcr16.bit._D1 +#define PPCR16_D0 ppcr16.bit._D0 +__IO_EXTERN PPCR17STR ppcr17; +#define PPCR17 ppcr17.byte +#define PPCR17_D7 ppcr17.bit._D7 +#define PPCR17_D6 ppcr17.bit._D6 +#define PPCR17_D5 ppcr17.bit._D5 +#define PPCR17_D4 ppcr17.bit._D4 +__IO_EXTERN PPCR18STR ppcr18; +#define PPCR18 ppcr18.byte +#define PPCR18_D6 ppcr18.bit._D6 +#define PPCR18_D5 ppcr18.bit._D5 +#define PPCR18_D4 ppcr18.bit._D4 +#define PPCR18_D2 ppcr18.bit._D2 +#define PPCR18_D1 ppcr18.bit._D1 +#define PPCR18_D0 ppcr18.bit._D0 +__IO_EXTERN PPCR19STR ppcr19; +#define PPCR19 ppcr19.byte +#define PPCR19_D6 ppcr19.bit._D6 +#define PPCR19_D5 ppcr19.bit._D5 +#define PPCR19_D4 ppcr19.bit._D4 +#define PPCR19_D2 ppcr19.bit._D2 +#define PPCR19_D1 ppcr19.bit._D1 +#define PPCR19_D0 ppcr19.bit._D0 +__IO_EXTERN PPCR20STR ppcr20; +#define PPCR20 ppcr20.byte +#define PPCR20_D2 ppcr20.bit._D2 +#define PPCR20_D1 ppcr20.bit._D1 +#define PPCR20_D0 ppcr20.bit._D0 +__IO_EXTERN PPCR22STR ppcr22; +#define PPCR22 ppcr22.byte +#define PPCR22_D5 ppcr22.bit._D5 +#define PPCR22_D4 ppcr22.bit._D4 +#define PPCR22_D2 ppcr22.bit._D2 +#define PPCR22_D0 ppcr22.bit._D0 +__IO_EXTERN PPCR23STR ppcr23; +#define PPCR23 ppcr23.byte +#define PPCR23_D5 ppcr23.bit._D5 +#define PPCR23_D4 ppcr23.bit._D4 +#define PPCR23_D3 ppcr23.bit._D3 +#define PPCR23_D2 ppcr23.bit._D2 +#define PPCR23_D1 ppcr23.bit._D1 +#define PPCR23_D0 ppcr23.bit._D0 +__IO_EXTERN PPCR24STR ppcr24; +#define PPCR24 ppcr24.byte +#define PPCR24_D7 ppcr24.bit._D7 +#define PPCR24_D6 ppcr24.bit._D6 +#define PPCR24_D5 ppcr24.bit._D5 +#define PPCR24_D4 ppcr24.bit._D4 +#define PPCR24_D3 ppcr24.bit._D3 +#define PPCR24_D2 ppcr24.bit._D2 +#define PPCR24_D1 ppcr24.bit._D1 +#define PPCR24_D0 ppcr24.bit._D0 +__IO_EXTERN PPCR25STR ppcr25; +#define PPCR25 ppcr25.byte +#define PPCR25_D7 ppcr25.bit._D7 +#define PPCR25_D6 ppcr25.bit._D6 +#define PPCR25_D5 ppcr25.bit._D5 +#define PPCR25_D4 ppcr25.bit._D4 +#define PPCR25_D3 ppcr25.bit._D3 +#define PPCR25_D2 ppcr25.bit._D2 +#define PPCR25_D1 ppcr25.bit._D1 +#define PPCR25_D0 ppcr25.bit._D0 +__IO_EXTERN PPCR26STR ppcr26; +#define PPCR26 ppcr26.byte +#define PPCR26_D7 ppcr26.bit._D7 +#define PPCR26_D6 ppcr26.bit._D6 +#define PPCR26_D5 ppcr26.bit._D5 +#define PPCR26_D4 ppcr26.bit._D4 +#define PPCR26_D3 ppcr26.bit._D3 +#define PPCR26_D2 ppcr26.bit._D2 +#define PPCR26_D1 ppcr26.bit._D1 +#define PPCR26_D0 ppcr26.bit._D0 +__IO_EXTERN PPCR27STR ppcr27; +#define PPCR27 ppcr27.byte +#define PPCR27_D7 ppcr27.bit._D7 +#define PPCR27_D6 ppcr27.bit._D6 +#define PPCR27_D5 ppcr27.bit._D5 +#define PPCR27_D4 ppcr27.bit._D4 +#define PPCR27_D3 ppcr27.bit._D3 +#define PPCR27_D2 ppcr27.bit._D2 +#define PPCR27_D1 ppcr27.bit._D1 +#define PPCR27_D0 ppcr27.bit._D0 +__IO_EXTERN PPCR29STR ppcr29; +#define PPCR29 ppcr29.byte +#define PPCR29_D7 ppcr29.bit._D7 +#define PPCR29_D6 ppcr29.bit._D6 +#define PPCR29_D5 ppcr29.bit._D5 +#define PPCR29_D4 ppcr29.bit._D4 +#define PPCR29_D3 ppcr29.bit._D3 +#define PPCR29_D2 ppcr29.bit._D2 +#define PPCR29_D1 ppcr29.bit._D1 +#define PPCR29_D0 ppcr29.bit._D0 +__IO_EXTERN IO_LWORD dmasa0; /* DMAC */ +#define DMASA0 dmasa0 +__IO_EXTERN IO_LWORD dmada0; +#define DMADA0 dmada0 +__IO_EXTERN IO_LWORD dmasa1; +#define DMASA1 dmasa1 +__IO_EXTERN IO_LWORD dmada1; +#define DMADA1 dmada1 +__IO_EXTERN IO_LWORD dmasa2; +#define DMASA2 dmasa2 +__IO_EXTERN IO_LWORD dmada2; +#define DMADA2 dmada2 +__IO_EXTERN IO_LWORD dmasa3; +#define DMASA3 dmasa3 +__IO_EXTERN IO_LWORD dmada3; +#define DMADA3 dmada3 +__IO_EXTERN IO_LWORD dmasa4; +#define DMASA4 dmasa4 +__IO_EXTERN IO_LWORD dmada4; +#define DMADA4 dmada4 +__IO_EXTERN FMCSSTR fmcs; /* Flash Memory/I-Cache Control Register */ +#define FMCS fmcs.byte +#define FMCS_ASYNC fmcs.bit._ASYNC +#define FMCS_FIXE fmcs.bit._FIXE +#define FMCS_BIRE fmcs.bit._BIRE +#define FMCS_RDYEG fmcs.bit._RDYEG +#define FMCS_RDY fmcs.bit._RDY +#define FMCS_RDYI fmcs.bit._RDYI +#define FMCS_RW16 fmcs.bit._RW16 +#define FMCS_LPM fmcs.bit._LPM +__IO_EXTERN FMCRSTR fmcr; +#define FMCR fmcr.byte +#define FMCR_LOCK fmcr.bit._LOCK +#define FMCR_PHASE fmcr.bit._PHASE +#define FMCR_PF2I fmcr.bit._PF2I +#define FMCR_RD64 fmcr.bit._RD64 +__IO_EXTERN FCHCRSTR fchcr; +#define FCHCR fchcr.word +#define FCHCR_REN fchcr.bit._REN +#define FCHCR_TAGE fchcr.bit._TAGE +#define FCHCR_FLUSH fchcr.bit._FLUSH +#define FCHCR_DBEN fchcr.bit._DBEN +#define FCHCR_PFEN fchcr.bit._PFEN +#define FCHCR_PFMC fchcr.bit._PFMC +#define FCHCR_LOCK fchcr.bit._LOCK +#define FCHCR_ENAB fchcr.bit._ENAB +#define FCHCR_SIZE1 fchcr.bit._SIZE1 +#define FCHCR_SIZE0 fchcr.bit._SIZE0 +#define FCHCR_SIZE fchcr.bitc._SIZE +__IO_EXTERN FMWTSTR fmwt; +#define FMWT fmwt.word +#define FMWT_WTP1 fmwt.bit._WTP1 +#define FMWT_WTP0 fmwt.bit._WTP0 +#define FMWT_WEXH1 fmwt.bit._WEXH1 +#define FMWT_WEXH0 fmwt.bit._WEXH0 +#define FMWT_WTC3 fmwt.bit._WTC3 +#define FMWT_WTC2 fmwt.bit._WTC2 +#define FMWT_WTC1 fmwt.bit._WTC1 +#define FMWT_WTC0 fmwt.bit._WTC0 +#define FMWT_FRAM fmwt.bit._FRAM +#define FMWT_ATD2 fmwt.bit._ATD2 +#define FMWT_ATD1 fmwt.bit._ATD1 +#define FMWT_ATD0 fmwt.bit._ATD0 +#define FMWT_EQ3 fmwt.bit._EQ3 +#define FMWT_EQ2 fmwt.bit._EQ2 +#define FMWT_EQ1 fmwt.bit._EQ1 +#define FMWT_EQ0 fmwt.bit._EQ0 +#define FMWT_WTP fmwt.bitc._WTP +#define FMWT_WEXH fmwt.bitc._WEXH +#define FMWT_WTC fmwt.bitc._WTC +#define FMWT_ATD fmwt.bitc._ATD +#define FMWT_EQ fmwt.bitc._EQ +__IO_EXTERN FMWT2STR fmwt2; +#define FMWT2 fmwt2.byte +#define FMWT2_ALEH2 fmwt2.bit._ALEH2 +#define FMWT2_ALEH1 fmwt2.bit._ALEH1 +#define FMWT2_ALEH0 fmwt2.bit._ALEH0 +#define FMWT2_ALEH fmwt2.bitc._ALEH +__IO_EXTERN FMPSSTR fmps; +#define FMPS fmps.byte +#define FMPS_PS2 fmps.bit._PS2 +#define FMPS_PS1 fmps.bit._PS1 +#define FMPS_PS0 fmps.bit._PS0 +#define FMPS_PS fmps.bitc._PS +__IO_EXTERN IO_LWORD fmac; +#define FMAC fmac +__IO_EXTERN IO_LWORD fcha0; /* I_Cache Nonchachable area settings Register */ +#define FCHA0 fcha0 +__IO_EXTERN IO_LWORD fcha1; +#define FCHA1 fcha1 +__IO_EXTERN FSCR0STR fscr0; /* Flash Security Control Register */ +#define FSCR0 fscr0.lword +#define FSCR0_CRC31 fscr0.bit._CRC31 +#define FSCR0_CRC30 fscr0.bit._CRC30 +#define FSCR0_CRC29 fscr0.bit._CRC29 +#define FSCR0_CRC28 fscr0.bit._CRC28 +#define FSCR0_CRC27 fscr0.bit._CRC27 +#define FSCR0_CRC26 fscr0.bit._CRC26 +#define FSCR0_CRC25 fscr0.bit._CRC25 +#define FSCR0_CRC24 fscr0.bit._CRC24 +#define FSCR0_CRC23 fscr0.bit._CRC23 +#define FSCR0_CRC22 fscr0.bit._CRC22 +#define FSCR0_CRC21 fscr0.bit._CRC21 +#define FSCR0_CRC20 fscr0.bit._CRC20 +#define FSCR0_CRC19 fscr0.bit._CRC19 +#define FSCR0_CRC18 fscr0.bit._CRC18 +#define FSCR0_CRC17 fscr0.bit._CRC17 +#define FSCR0_CRC16 fscr0.bit._CRC16 +#define FSCR0_CRC15 fscr0.bit._CRC15 +#define FSCR0_CRC14 fscr0.bit._CRC14 +#define FSCR0_CRC13 fscr0.bit._CRC13 +#define FSCR0_CRC12 fscr0.bit._CRC12 +#define FSCR0_CRC11 fscr0.bit._CRC11 +#define FSCR0_CRC10 fscr0.bit._CRC10 +#define FSCR0_CRC9 fscr0.bit._CRC9 +#define FSCR0_CRC8 fscr0.bit._CRC8 +#define FSCR0_CRC7 fscr0.bit._CRC7 +#define FSCR0_CRC6 fscr0.bit._CRC6 +#define FSCR0_CRC5 fscr0.bit._CRC5 +#define FSCR0_CRC4 fscr0.bit._CRC4 +#define FSCR0_CRC3 fscr0.bit._CRC3 +#define FSCR0_CRC2 fscr0.bit._CRC2 +#define FSCR0_CRC1 fscr0.bit._CRC1 +#define FSCR0_CRC0 fscr0.bit._CRC0 +__IO_EXTERN FSCR1STR fscr1; +#define FSCR1 fscr1.lword +#define FSCR1_RDY fscr1.bit._RDY +#define FSCR1_CSZ3 fscr1.bit._CSZ3 +#define FSCR1_CSZ2 fscr1.bit._CSZ2 +#define FSCR1_CSZ1 fscr1.bit._CSZ1 +#define FSCR1_CSZ0 fscr1.bit._CSZ0 +#define FSCR1_CSA15 fscr1.bit._CSA15 +#define FSCR1_CSA14 fscr1.bit._CSA14 +#define FSCR1_CSA13 fscr1.bit._CSA13 +#define FSCR1_CSA12 fscr1.bit._CSA12 +#define FSCR1_CSA11 fscr1.bit._CSA11 +#define FSCR1_CSA10 fscr1.bit._CSA10 +#define FSCR1_CSA9 fscr1.bit._CSA9 +#define FSCR1_CSA8 fscr1.bit._CSA8 +#define FSCR1_CSA7 fscr1.bit._CSA7 +#define FSCR1_CSA6 fscr1.bit._CSA6 +#define FSCR1_CSA5 fscr1.bit._CSA5 +#define FSCR1_CSA4 fscr1.bit._CSA4 +#define FSCR1_CSA3 fscr1.bit._CSA3 +#define FSCR1_CSA2 fscr1.bit._CSA2 +#define FSCR1_CSA1 fscr1.bit._CSA1 +#define FSCR1_CSA0 fscr1.bit._CSA0 +#define FSCR1_CSZ fscr1.bitc._CSZ +__IO_EXTERN CTRLR0STR ctrlr0; /* CAN 0 Control Register */ +#define CTRLR0 ctrlr0.word +#define CTRLR0_Test ctrlr0.bit._Test +#define CTRLR0_CCE ctrlr0.bit._CCE +#define CTRLR0_DAR ctrlr0.bit._DAR +#define CTRLR0_EIE ctrlr0.bit._EIE +#define CTRLR0_SIE ctrlr0.bit._SIE +#define CTRLR0_IE ctrlr0.bit._IE +#define CTRLR0_Init ctrlr0.bit._Init +__IO_EXTERN STATR0STR statr0; +#define STATR0 statr0.word +#define STATR0_BOff statr0.bit._BOff +#define STATR0_EWarn statr0.bit._EWarn +#define STATR0_EPass statr0.bit._EPass +#define STATR0_RxOK statr0.bit._RxOK +#define STATR0_TxOK statr0.bit._TxOK +#define STATR0_LEC2 statr0.bit._LEC2 +#define STATR0_LEC1 statr0.bit._LEC1 +#define STATR0_LEC0 statr0.bit._LEC0 +#define STATR0_LEC statr0.bitc._LEC +__IO_EXTERN ERRCNT0STR errcnt0; +#define ERRCNT0 errcnt0.word +#define ERRCNT0_RP errcnt0.bit._RP +#define ERRCNT0_REC6 errcnt0.bit._REC6 +#define ERRCNT0_REC5 errcnt0.bit._REC5 +#define ERRCNT0_REC4 errcnt0.bit._REC4 +#define ERRCNT0_REC3 errcnt0.bit._REC3 +#define ERRCNT0_REC2 errcnt0.bit._REC2 +#define ERRCNT0_REC1 errcnt0.bit._REC1 +#define ERRCNT0_REC0 errcnt0.bit._REC0 +#define ERRCNT0_TEC7 errcnt0.bit._TEC7 +#define ERRCNT0_TEC6 errcnt0.bit._TEC6 +#define ERRCNT0_TEC5 errcnt0.bit._TEC5 +#define ERRCNT0_TEC4 errcnt0.bit._TEC4 +#define ERRCNT0_TEC3 errcnt0.bit._TEC3 +#define ERRCNT0_TEC2 errcnt0.bit._TEC2 +#define ERRCNT0_TEC1 errcnt0.bit._TEC1 +#define ERRCNT0_TEC0 errcnt0.bit._TEC0 +#define ERRCNT0_REC errcnt0.bitc._REC +#define ERRCNT0_TEC errcnt0.bitc._TEC +__IO_EXTERN BTR0STR btr0; +#define BTR0 btr0.word +#define BTR0_Tseg22 btr0.bit._Tseg22 +#define BTR0_Tseg21 btr0.bit._Tseg21 +#define BTR0_Tseg20 btr0.bit._Tseg20 +#define BTR0_Tseg13 btr0.bit._Tseg13 +#define BTR0_Tseg12 btr0.bit._Tseg12 +#define BTR0_Tseg11 btr0.bit._Tseg11 +#define BTR0_Tseg10 btr0.bit._Tseg10 +#define BTR0_SJW1 btr0.bit._SJW1 +#define BTR0_SJW0 btr0.bit._SJW0 +#define BTR0_BRP5 btr0.bit._BRP5 +#define BTR0_BRP4 btr0.bit._BRP4 +#define BTR0_BRP3 btr0.bit._BRP3 +#define BTR0_BRP2 btr0.bit._BRP2 +#define BTR0_BRP1 btr0.bit._BRP1 +#define BTR0_BRP0 btr0.bit._BRP0 +#define BTR0_Tseg2 btr0.bitc._Tseg2 +#define BTR0_Tseg1 btr0.bitc._Tseg1 +#define BTR0_SJW btr0.bitc._SJW +#define BTR0_BRP btr0.bitc._BRP +__IO_EXTERN IO_WORD intr0; +#define INTR0 intr0 +__IO_EXTERN TESTR0STR testr0; +#define TESTR0 testr0.word +#define TESTR0_Rx testr0.bit._Rx +#define TESTR0_Tx1 testr0.bit._Tx1 +#define TESTR0_Tx0 testr0.bit._Tx0 +#define TESTR0_LBack testr0.bit._LBack +#define TESTR0_Silent testr0.bit._Silent +#define TESTR0_Basic testr0.bit._Basic +#define TESTR0_Tx testr0.bitc._Tx +__IO_EXTERN BRPER0STR brper0; +#define BRPER0 brper0.word +#define BRPER0_BRPE3 brper0.bit._BRPE3 +#define BRPER0_BRPE2 brper0.bit._BRPE2 +#define BRPER0_BRPE1 brper0.bit._BRPE1 +#define BRPER0_BRPE0 brper0.bit._BRPE0 +#define BRPER0_BRPE brper0.bitc._BRPE +__IO_EXTERN BRPE0STR brpe0; +#define BRPE0 brpe0.word +__IO_EXTERN CBSYNC0STR cbsync0; +#define CBSYNC0 cbsync0.word +__IO_EXTERN IF1CREQ0STR if1creq0; /* CAN 0 IF 1 */ +#define IF1CREQ0 if1creq0.word +#define IF1CREQ0_Busy if1creq0.bit._Busy +#define IF1CREQ0_MN5 if1creq0.bit._MN5 +#define IF1CREQ0_MN4 if1creq0.bit._MN4 +#define IF1CREQ0_MN3 if1creq0.bit._MN3 +#define IF1CREQ0_MN2 if1creq0.bit._MN2 +#define IF1CREQ0_MN1 if1creq0.bit._MN1 +#define IF1CREQ0_MN0 if1creq0.bit._MN0 +#define IF1CREQ0_MN if1creq0.bitc._MN +__IO_EXTERN IF1CMSK0STR if1cmsk0; +#define IF1CMSK0 if1cmsk0.word +#define IF1CMSK0_WR if1cmsk0.bit._WR +#define IF1CMSK0_Mask if1cmsk0.bit._Mask +#define IF1CMSK0_Arb if1cmsk0.bit._Arb +#define IF1CMSK0_Control if1cmsk0.bit._Control +#define IF1CMSK0_CIP if1cmsk0.bit._CIP +#define IF1CMSK0_TxReq if1cmsk0.bit._TxReq +#define IF1CMSK0_DataA if1cmsk0.bit._DataA +#define IF1CMSK0_DataB if1cmsk0.bit._DataB +__IO_EXTERN IO_LWORD if1msk120; +#define IF1MSK120 if1msk120 +__IO_EXTERN IF1MSK20STR if1msk20; +#define IF1MSK20 if1msk20.word +#define IF1MSK20_MXtd if1msk20.bit._MXtd +#define IF1MSK20_MDir if1msk20.bit._MDir +__IO_EXTERN IO_WORD if1msk10; +#define IF1MSK10 if1msk10 +__IO_EXTERN IO_LWORD if1arb120; +#define IF1ARB120 if1arb120 +__IO_EXTERN IF1ARB20STR if1arb20; +#define IF1ARB20 if1arb20.word +#define IF1ARB20_MsgVal if1arb20.bit._MsgVal +#define IF1ARB20_Xtd if1arb20.bit._Xtd +#define IF1ARB20_DIR if1arb20.bit._DIR +__IO_EXTERN IO_WORD if1arb10; +#define IF1ARB10 if1arb10 +__IO_EXTERN IF1MCTR0STR if1mctr0; +#define IF1MCTR0 if1mctr0.word +#define IF1MCTR0_NewDat if1mctr0.bit._NewDat +#define IF1MCTR0_MsgLst if1mctr0.bit._MsgLst +#define IF1MCTR0_IntPnd if1mctr0.bit._IntPnd +#define IF1MCTR0_UMask if1mctr0.bit._UMask +#define IF1MCTR0_TxIE if1mctr0.bit._TxIE +#define IF1MCTR0_RxIE if1mctr0.bit._RxIE +#define IF1MCTR0_RmtEn if1mctr0.bit._RmtEn +#define IF1MCTR0_TxRqst if1mctr0.bit._TxRqst +#define IF1MCTR0_EoB if1mctr0.bit._EoB +#define IF1MCTR0_DLC3 if1mctr0.bit._DLC3 +#define IF1MCTR0_DLC2 if1mctr0.bit._DLC2 +#define IF1MCTR0_DLC1 if1mctr0.bit._DLC1 +#define IF1MCTR0_DLC0 if1mctr0.bit._DLC0 +#define IF1MCTR0_DLC if1mctr0.bitc._DLC +__IO_EXTERN IO_LWORD if1dta120; +#define IF1DTA120 if1dta120 +__IO_EXTERN IO_WORD if1dta10; +#define IF1DTA10 if1dta10 +__IO_EXTERN IO_WORD if1dta20; +#define IF1DTA20 if1dta20 +__IO_EXTERN IO_LWORD if1dtb120; +#define IF1DTB120 if1dtb120 +__IO_EXTERN IO_WORD if1dtb10; +#define IF1DTB10 if1dtb10 +__IO_EXTERN IO_WORD if1dtb20; +#define IF1DTB20 if1dtb20 +__IO_EXTERN IO_LWORD if1dta_swp120; +#define IF1DTA_SWP120 if1dta_swp120 +__IO_EXTERN IO_WORD if1dta_swp20; +#define IF1DTA_SWP20 if1dta_swp20 +__IO_EXTERN IO_WORD if1dta_swp10; +#define IF1DTA_SWP10 if1dta_swp10 +__IO_EXTERN IO_LWORD if1dtb_swp120; +#define IF1DTB_SWP120 if1dtb_swp120 +__IO_EXTERN IO_WORD if1dtb_swp20; +#define IF1DTB_SWP20 if1dtb_swp20 +__IO_EXTERN IO_WORD if1dtb_swp10; +#define IF1DTB_SWP10 if1dtb_swp10 +__IO_EXTERN IF2CREQ0STR if2creq0; /* CAN 0 IF 2 */ +#define IF2CREQ0 if2creq0.word +#define IF2CREQ0_Busy if2creq0.bit._Busy +#define IF2CREQ0_MN5 if2creq0.bit._MN5 +#define IF2CREQ0_MN4 if2creq0.bit._MN4 +#define IF2CREQ0_MN3 if2creq0.bit._MN3 +#define IF2CREQ0_MN2 if2creq0.bit._MN2 +#define IF2CREQ0_MN1 if2creq0.bit._MN1 +#define IF2CREQ0_MN0 if2creq0.bit._MN0 +#define IF2CREQ0_MN if2creq0.bitc._MN +__IO_EXTERN IF2CMSK0STR if2cmsk0; +#define IF2CMSK0 if2cmsk0.word +#define IF2CMSK0_WR if2cmsk0.bit._WR +#define IF2CMSK0_Mask if2cmsk0.bit._Mask +#define IF2CMSK0_Arb if2cmsk0.bit._Arb +#define IF2CMSK0_Control if2cmsk0.bit._Control +#define IF2CMSK0_CIP if2cmsk0.bit._CIP +#define IF2CMSK0_TxReq if2cmsk0.bit._TxReq +#define IF2CMSK0_DataA if2cmsk0.bit._DataA +#define IF2CMSK0_DataB if2cmsk0.bit._DataB +__IO_EXTERN IO_LWORD if2msk120; +#define IF2MSK120 if2msk120 +__IO_EXTERN IF2MSK20STR if2msk20; +#define IF2MSK20 if2msk20.word +#define IF2MSK20_MXtd if2msk20.bit._MXtd +#define IF2MSK20_MDir if2msk20.bit._MDir +__IO_EXTERN IO_WORD if2msk10; +#define IF2MSK10 if2msk10 +__IO_EXTERN IO_LWORD if2arb120; +#define IF2ARB120 if2arb120 +__IO_EXTERN IF2ARB20STR if2arb20; +#define IF2ARB20 if2arb20.word +#define IF2ARB20_MsgVal if2arb20.bit._MsgVal +#define IF2ARB20_Xtd if2arb20.bit._Xtd +#define IF2ARB20_DIR if2arb20.bit._DIR +__IO_EXTERN IO_WORD if2arb10; +#define IF2ARB10 if2arb10 +__IO_EXTERN IF2MCTR0STR if2mctr0; +#define IF2MCTR0 if2mctr0.word +#define IF2MCTR0_NewDat if2mctr0.bit._NewDat +#define IF2MCTR0_MsgLst if2mctr0.bit._MsgLst +#define IF2MCTR0_IntPnd if2mctr0.bit._IntPnd +#define IF2MCTR0_UMask if2mctr0.bit._UMask +#define IF2MCTR0_TxIE if2mctr0.bit._TxIE +#define IF2MCTR0_RxIE if2mctr0.bit._RxIE +#define IF2MCTR0_RmtEn if2mctr0.bit._RmtEn +#define IF2MCTR0_TxRqst if2mctr0.bit._TxRqst +#define IF2MCTR0_EoB if2mctr0.bit._EoB +#define IF2MCTR0_DLC3 if2mctr0.bit._DLC3 +#define IF2MCTR0_DLC2 if2mctr0.bit._DLC2 +#define IF2MCTR0_DLC1 if2mctr0.bit._DLC1 +#define IF2MCTR0_DLC0 if2mctr0.bit._DLC0 +#define IF2MCTR0_DLC if2mctr0.bitc._DLC +__IO_EXTERN IO_LWORD if2dta120; +#define IF2DTA120 if2dta120 +__IO_EXTERN IO_WORD if2dta10; +#define IF2DTA10 if2dta10 +__IO_EXTERN IO_WORD if2dta20; +#define IF2DTA20 if2dta20 +__IO_EXTERN IO_LWORD if2dtb120; +#define IF2DTB120 if2dtb120 +__IO_EXTERN IO_WORD if2dtb10; +#define IF2DTB10 if2dtb10 +__IO_EXTERN IO_WORD if2dtb20; +#define IF2DTB20 if2dtb20 +__IO_EXTERN IO_LWORD if2dta_swp120; +#define IF2DTA_SWP120 if2dta_swp120 +__IO_EXTERN IO_WORD if2dta_swp20; +#define IF2DTA_SWP20 if2dta_swp20 +__IO_EXTERN IO_WORD if2dta_swp10; +#define IF2DTA_SWP10 if2dta_swp10 +__IO_EXTERN IO_LWORD if2dtb_swp120; +#define IF2DTB_SWP120 if2dtb_swp120 +__IO_EXTERN IO_WORD if2dtb_swp20; +#define IF2DTB_SWP20 if2dtb_swp20 +__IO_EXTERN IO_WORD if2dtb_swp10; +#define IF2DTB_SWP10 if2dtb_swp10 +__IO_EXTERN IO_LWORD treqr120; /* CAN 0 Status Flags */ +#define TREQR120 treqr120 +__IO_EXTERN IO_WORD treqr20; +#define TREQR20 treqr20 +__IO_EXTERN IO_WORD treqr10; +#define TREQR10 treqr10 +__IO_EXTERN IO_LWORD newdt120; +#define NEWDT120 newdt120 +__IO_EXTERN IO_WORD newdt20; +#define NEWDT20 newdt20 +__IO_EXTERN IO_WORD newdt10; +#define NEWDT10 newdt10 +__IO_EXTERN IO_LWORD intpnd120; +#define INTPND120 intpnd120 +__IO_EXTERN IO_WORD intpnd20; +#define INTPND20 intpnd20 +__IO_EXTERN IO_WORD intpnd10; +#define INTPND10 intpnd10 +__IO_EXTERN IO_LWORD msgval120; +#define MSGVAL120 msgval120 +__IO_EXTERN IO_WORD msgval20; +#define MSGVAL20 msgval20 +__IO_EXTERN IO_WORD msgval10; +#define MSGVAL10 msgval10 +__IO_EXTERN IO_LWORD msgval340; +#define MSGVAL340 msgval340 +__IO_EXTERN CTRLR1STR ctrlr1; /* CAN 1 Control Register */ +#define CTRLR1 ctrlr1.word +#define CTRLR1_Test ctrlr1.bit._Test +#define CTRLR1_CCE ctrlr1.bit._CCE +#define CTRLR1_DAR ctrlr1.bit._DAR +#define CTRLR1_EIE ctrlr1.bit._EIE +#define CTRLR1_SIE ctrlr1.bit._SIE +#define CTRLR1_IE ctrlr1.bit._IE +#define CTRLR1_Init ctrlr1.bit._Init +__IO_EXTERN STATR1STR statr1; +#define STATR1 statr1.word +#define STATR1_BOff statr1.bit._BOff +#define STATR1_EWarn statr1.bit._EWarn +#define STATR1_EPass statr1.bit._EPass +#define STATR1_RxOK statr1.bit._RxOK +#define STATR1_TxOK statr1.bit._TxOK +#define STATR1_LEC2 statr1.bit._LEC2 +#define STATR1_LEC1 statr1.bit._LEC1 +#define STATR1_LEC0 statr1.bit._LEC0 +#define STATR1_LEC statr1.bitc._LEC +__IO_EXTERN ERRCNT1STR errcnt1; +#define ERRCNT1 errcnt1.word +#define ERRCNT1_RP errcnt1.bit._RP +#define ERRCNT1_REC6 errcnt1.bit._REC6 +#define ERRCNT1_REC5 errcnt1.bit._REC5 +#define ERRCNT1_REC4 errcnt1.bit._REC4 +#define ERRCNT1_REC3 errcnt1.bit._REC3 +#define ERRCNT1_REC2 errcnt1.bit._REC2 +#define ERRCNT1_REC1 errcnt1.bit._REC1 +#define ERRCNT1_REC0 errcnt1.bit._REC0 +#define ERRCNT1_TEC7 errcnt1.bit._TEC7 +#define ERRCNT1_TEC6 errcnt1.bit._TEC6 +#define ERRCNT1_TEC5 errcnt1.bit._TEC5 +#define ERRCNT1_TEC4 errcnt1.bit._TEC4 +#define ERRCNT1_TEC3 errcnt1.bit._TEC3 +#define ERRCNT1_TEC2 errcnt1.bit._TEC2 +#define ERRCNT1_TEC1 errcnt1.bit._TEC1 +#define ERRCNT1_TEC0 errcnt1.bit._TEC0 +#define ERRCNT1_REC errcnt1.bitc._REC +#define ERRCNT1_TEC errcnt1.bitc._TEC +__IO_EXTERN BTR1STR btr1; +#define BTR1 btr1.word +#define BTR1_Tseg22 btr1.bit._Tseg22 +#define BTR1_Tseg21 btr1.bit._Tseg21 +#define BTR1_Tseg20 btr1.bit._Tseg20 +#define BTR1_Tseg13 btr1.bit._Tseg13 +#define BTR1_Tseg12 btr1.bit._Tseg12 +#define BTR1_Tseg11 btr1.bit._Tseg11 +#define BTR1_Tseg10 btr1.bit._Tseg10 +#define BTR1_SJW1 btr1.bit._SJW1 +#define BTR1_SJW0 btr1.bit._SJW0 +#define BTR1_BRP5 btr1.bit._BRP5 +#define BTR1_BRP4 btr1.bit._BRP4 +#define BTR1_BRP3 btr1.bit._BRP3 +#define BTR1_BRP2 btr1.bit._BRP2 +#define BTR1_BRP1 btr1.bit._BRP1 +#define BTR1_BRP0 btr1.bit._BRP0 +#define BTR1_Tseg2 btr1.bitc._Tseg2 +#define BTR1_Tseg1 btr1.bitc._Tseg1 +#define BTR1_SJW btr1.bitc._SJW +#define BTR1_BRP btr1.bitc._BRP +__IO_EXTERN IO_WORD intr1; +#define INTR1 intr1 +__IO_EXTERN TESTR1STR testr1; +#define TESTR1 testr1.word +#define TESTR1_Rx testr1.bit._Rx +#define TESTR1_Tx1 testr1.bit._Tx1 +#define TESTR1_Tx0 testr1.bit._Tx0 +#define TESTR1_LBack testr1.bit._LBack +#define TESTR1_Silent testr1.bit._Silent +#define TESTR1_Basic testr1.bit._Basic +#define TESTR1_Tx testr1.bitc._Tx +__IO_EXTERN BRPER1STR brper1; +#define BRPER1 brper1.word +#define BRPER1_BRPE3 brper1.bit._BRPE3 +#define BRPER1_BRPE2 brper1.bit._BRPE2 +#define BRPER1_BRPE1 brper1.bit._BRPE1 +#define BRPER1_BRPE0 brper1.bit._BRPE0 +#define BRPER1_BRPE brper1.bitc._BRPE +__IO_EXTERN BRPE1STR brpe1; +#define BRPE1 brpe1.word +__IO_EXTERN IO_WORD cbsync1; +#define CBSYNC1 cbsync1 +__IO_EXTERN IF1CREQ1STR if1creq1; /* CAN 1 IF 1 */ +#define IF1CREQ1 if1creq1.word +#define IF1CREQ1_Busy if1creq1.bit._Busy +#define IF1CREQ1_MN5 if1creq1.bit._MN5 +#define IF1CREQ1_MN4 if1creq1.bit._MN4 +#define IF1CREQ1_MN3 if1creq1.bit._MN3 +#define IF1CREQ1_MN2 if1creq1.bit._MN2 +#define IF1CREQ1_MN1 if1creq1.bit._MN1 +#define IF1CREQ1_MN0 if1creq1.bit._MN0 +#define IF1CREQ1_MN if1creq1.bitc._MN +__IO_EXTERN IF1CMSK1STR if1cmsk1; +#define IF1CMSK1 if1cmsk1.word +#define IF1CMSK1_WR if1cmsk1.bit._WR +#define IF1CMSK1_Mask if1cmsk1.bit._Mask +#define IF1CMSK1_Arb if1cmsk1.bit._Arb +#define IF1CMSK1_Control if1cmsk1.bit._Control +#define IF1CMSK1_CIP if1cmsk1.bit._CIP +#define IF1CMSK1_TxReq if1cmsk1.bit._TxReq +#define IF1CMSK1_DataA if1cmsk1.bit._DataA +#define IF1CMSK1_DataB if1cmsk1.bit._DataB +__IO_EXTERN IO_LWORD if1msk121; +#define IF1MSK121 if1msk121 +__IO_EXTERN IF1MSK21STR if1msk21; +#define IF1MSK21 if1msk21.word +#define IF1MSK21_MXtd if1msk21.bit._MXtd +#define IF1MSK21_MDir if1msk21.bit._MDir +__IO_EXTERN IO_WORD if1msk11; +#define IF1MSK11 if1msk11 +__IO_EXTERN IO_LWORD if1arb121; +#define IF1ARB121 if1arb121 +__IO_EXTERN IF1ARB21STR if1arb21; +#define IF1ARB21 if1arb21.word +#define IF1ARB21_MsgVal if1arb21.bit._MsgVal +#define IF1ARB21_Xtd if1arb21.bit._Xtd +#define IF1ARB21_DIR if1arb21.bit._DIR +__IO_EXTERN IO_WORD if1arb11; +#define IF1ARB11 if1arb11 +__IO_EXTERN IF1MCTR1STR if1mctr1; +#define IF1MCTR1 if1mctr1.word +#define IF1MCTR1_NewDat if1mctr1.bit._NewDat +#define IF1MCTR1_MsgLst if1mctr1.bit._MsgLst +#define IF1MCTR1_IntPnd if1mctr1.bit._IntPnd +#define IF1MCTR1_UMask if1mctr1.bit._UMask +#define IF1MCTR1_TxIE if1mctr1.bit._TxIE +#define IF1MCTR1_RxIE if1mctr1.bit._RxIE +#define IF1MCTR1_RmtEn if1mctr1.bit._RmtEn +#define IF1MCTR1_TxRqst if1mctr1.bit._TxRqst +#define IF1MCTR1_EoB if1mctr1.bit._EoB +#define IF1MCTR1_DLC3 if1mctr1.bit._DLC3 +#define IF1MCTR1_DLC2 if1mctr1.bit._DLC2 +#define IF1MCTR1_DLC1 if1mctr1.bit._DLC1 +#define IF1MCTR1_DLC0 if1mctr1.bit._DLC0 +#define IF1MCTR1_DLC if1mctr1.bitc._DLC +__IO_EXTERN IO_LWORD if1dta121; +#define IF1DTA121 if1dta121 +__IO_EXTERN IO_WORD if1dta11; +#define IF1DTA11 if1dta11 +__IO_EXTERN IO_WORD if1dta21; +#define IF1DTA21 if1dta21 +__IO_EXTERN IO_LWORD if1dtb121; +#define IF1DTB121 if1dtb121 +__IO_EXTERN IO_WORD if1dtb11; +#define IF1DTB11 if1dtb11 +__IO_EXTERN IO_WORD if1dtb21; +#define IF1DTB21 if1dtb21 +__IO_EXTERN IO_LWORD if1dta_swp121; +#define IF1DTA_SWP121 if1dta_swp121 +__IO_EXTERN IO_WORD if1dta_swp21; +#define IF1DTA_SWP21 if1dta_swp21 +__IO_EXTERN IO_WORD if1dta_swp11; +#define IF1DTA_SWP11 if1dta_swp11 +__IO_EXTERN IO_LWORD if1dtb_swp121; +#define IF1DTB_SWP121 if1dtb_swp121 +__IO_EXTERN IO_WORD if1dtb_swp21; +#define IF1DTB_SWP21 if1dtb_swp21 +__IO_EXTERN IO_WORD if1dtb_swp11; +#define IF1DTB_SWP11 if1dtb_swp11 +__IO_EXTERN IF2CREQ1STR if2creq1; /* CAN 1 IF 2 */ +#define IF2CREQ1 if2creq1.word +#define IF2CREQ1_Busy if2creq1.bit._Busy +#define IF2CREQ1_MN5 if2creq1.bit._MN5 +#define IF2CREQ1_MN4 if2creq1.bit._MN4 +#define IF2CREQ1_MN3 if2creq1.bit._MN3 +#define IF2CREQ1_MN2 if2creq1.bit._MN2 +#define IF2CREQ1_MN1 if2creq1.bit._MN1 +#define IF2CREQ1_MN0 if2creq1.bit._MN0 +#define IF2CREQ1_MN if2creq1.bitc._MN +__IO_EXTERN IF2CMSK1STR if2cmsk1; +#define IF2CMSK1 if2cmsk1.word +#define IF2CMSK1_WR if2cmsk1.bit._WR +#define IF2CMSK1_Mask if2cmsk1.bit._Mask +#define IF2CMSK1_Arb if2cmsk1.bit._Arb +#define IF2CMSK1_Control if2cmsk1.bit._Control +#define IF2CMSK1_CIP if2cmsk1.bit._CIP +#define IF2CMSK1_TxReq if2cmsk1.bit._TxReq +#define IF2CMSK1_DataA if2cmsk1.bit._DataA +#define IF2CMSK1_DataB if2cmsk1.bit._DataB +__IO_EXTERN IO_LWORD if2msk121; +#define IF2MSK121 if2msk121 +__IO_EXTERN IF2MSK21STR if2msk21; +#define IF2MSK21 if2msk21.word +#define IF2MSK21_MXtd if2msk21.bit._MXtd +#define IF2MSK21_MDir if2msk21.bit._MDir +__IO_EXTERN IO_WORD if2msk11; +#define IF2MSK11 if2msk11 +__IO_EXTERN IO_LWORD if2arb121; +#define IF2ARB121 if2arb121 +__IO_EXTERN IF2ARB21STR if2arb21; +#define IF2ARB21 if2arb21.word +#define IF2ARB21_MsgVal if2arb21.bit._MsgVal +#define IF2ARB21_Xtd if2arb21.bit._Xtd +#define IF2ARB21_DIR if2arb21.bit._DIR +__IO_EXTERN IO_WORD if2arb11; +#define IF2ARB11 if2arb11 +__IO_EXTERN IF2MCTR1STR if2mctr1; +#define IF2MCTR1 if2mctr1.word +#define IF2MCTR1_NewDat if2mctr1.bit._NewDat +#define IF2MCTR1_MsgLst if2mctr1.bit._MsgLst +#define IF2MCTR1_IntPnd if2mctr1.bit._IntPnd +#define IF2MCTR1_UMask if2mctr1.bit._UMask +#define IF2MCTR1_TxIE if2mctr1.bit._TxIE +#define IF2MCTR1_RxIE if2mctr1.bit._RxIE +#define IF2MCTR1_RmtEn if2mctr1.bit._RmtEn +#define IF2MCTR1_TxRqst if2mctr1.bit._TxRqst +#define IF2MCTR1_EoB if2mctr1.bit._EoB +#define IF2MCTR1_DLC3 if2mctr1.bit._DLC3 +#define IF2MCTR1_DLC2 if2mctr1.bit._DLC2 +#define IF2MCTR1_DLC1 if2mctr1.bit._DLC1 +#define IF2MCTR1_DLC0 if2mctr1.bit._DLC0 +#define IF2MCTR1_DLC if2mctr1.bitc._DLC +__IO_EXTERN IO_LWORD if2dta121; +#define IF2DTA121 if2dta121 +__IO_EXTERN IO_WORD if2dta11; +#define IF2DTA11 if2dta11 +__IO_EXTERN IO_WORD if2dta21; +#define IF2DTA21 if2dta21 +__IO_EXTERN IO_LWORD if2dtb121; +#define IF2DTB121 if2dtb121 +__IO_EXTERN IO_WORD if2dtb11; +#define IF2DTB11 if2dtb11 +__IO_EXTERN IO_WORD if2dtb21; +#define IF2DTB21 if2dtb21 +__IO_EXTERN IO_LWORD if2dta_swp121; +#define IF2DTA_SWP121 if2dta_swp121 +__IO_EXTERN IO_WORD if2dta_swp21; +#define IF2DTA_SWP21 if2dta_swp21 +__IO_EXTERN IO_WORD if2dta_swp11; +#define IF2DTA_SWP11 if2dta_swp11 +__IO_EXTERN IO_LWORD if2dtb_swp121; +#define IF2DTB_SWP121 if2dtb_swp121 +__IO_EXTERN IO_WORD if2dtb_swp21; +#define IF2DTB_SWP21 if2dtb_swp21 +__IO_EXTERN IO_WORD if2dtb_swp11; +#define IF2DTB_SWP11 if2dtb_swp11 +__IO_EXTERN IO_LWORD treqr121; /* CAN 1 Status Flags */ +#define TREQR121 treqr121 +__IO_EXTERN IO_WORD treqr21; +#define TREQR21 treqr21 +__IO_EXTERN IO_WORD treqr11; +#define TREQR11 treqr11 +__IO_EXTERN IO_LWORD newdt121; +#define NEWDT121 newdt121 +__IO_EXTERN IO_WORD newdt21; +#define NEWDT21 newdt21 +__IO_EXTERN IO_WORD newdt11; +#define NEWDT11 newdt11 +__IO_EXTERN IO_LWORD intpnd121; +#define INTPND121 intpnd121 +__IO_EXTERN IO_WORD intpnd21; +#define INTPND21 intpnd21 +__IO_EXTERN IO_WORD intpnd11; +#define INTPND11 intpnd11 +__IO_EXTERN IO_LWORD msgval121; +#define MSGVAL121 msgval121 +__IO_EXTERN IO_WORD msgval21; +#define MSGVAL21 msgval21 +__IO_EXTERN IO_WORD msgval11; +#define MSGVAL11 msgval11 +__IO_EXTERN CTRLR2STR ctrlr2; /* CAN 2 Control Register */ +#define CTRLR2 ctrlr2.word +#define CTRLR2_Test ctrlr2.bit._Test +#define CTRLR2_CCE ctrlr2.bit._CCE +#define CTRLR2_DAR ctrlr2.bit._DAR +#define CTRLR2_EIE ctrlr2.bit._EIE +#define CTRLR2_SIE ctrlr2.bit._SIE +#define CTRLR2_IE ctrlr2.bit._IE +#define CTRLR2_Init ctrlr2.bit._Init +__IO_EXTERN STATR2STR statr2; +#define STATR2 statr2.word +#define STATR2_BOff statr2.bit._BOff +#define STATR2_EWarn statr2.bit._EWarn +#define STATR2_EPass statr2.bit._EPass +#define STATR2_RxOK statr2.bit._RxOK +#define STATR2_TxOK statr2.bit._TxOK +#define STATR2_LEC2 statr2.bit._LEC2 +#define STATR2_LEC1 statr2.bit._LEC1 +#define STATR2_LEC0 statr2.bit._LEC0 +#define STATR2_LEC statr2.bitc._LEC +__IO_EXTERN ERRCNT2STR errcnt2; +#define ERRCNT2 errcnt2.word +#define ERRCNT2_RP errcnt2.bit._RP +#define ERRCNT2_REC6 errcnt2.bit._REC6 +#define ERRCNT2_REC5 errcnt2.bit._REC5 +#define ERRCNT2_REC4 errcnt2.bit._REC4 +#define ERRCNT2_REC3 errcnt2.bit._REC3 +#define ERRCNT2_REC2 errcnt2.bit._REC2 +#define ERRCNT2_REC1 errcnt2.bit._REC1 +#define ERRCNT2_REC0 errcnt2.bit._REC0 +#define ERRCNT2_TEC7 errcnt2.bit._TEC7 +#define ERRCNT2_TEC6 errcnt2.bit._TEC6 +#define ERRCNT2_TEC5 errcnt2.bit._TEC5 +#define ERRCNT2_TEC4 errcnt2.bit._TEC4 +#define ERRCNT2_TEC3 errcnt2.bit._TEC3 +#define ERRCNT2_TEC2 errcnt2.bit._TEC2 +#define ERRCNT2_TEC1 errcnt2.bit._TEC1 +#define ERRCNT2_TEC0 errcnt2.bit._TEC0 +#define ERRCNT2_REC errcnt2.bitc._REC +#define ERRCNT2_TEC errcnt2.bitc._TEC +__IO_EXTERN BTR2STR btr2; +#define BTR2 btr2.word +#define BTR2_Tseg22 btr2.bit._Tseg22 +#define BTR2_Tseg21 btr2.bit._Tseg21 +#define BTR2_Tseg20 btr2.bit._Tseg20 +#define BTR2_Tseg13 btr2.bit._Tseg13 +#define BTR2_Tseg12 btr2.bit._Tseg12 +#define BTR2_Tseg11 btr2.bit._Tseg11 +#define BTR2_Tseg10 btr2.bit._Tseg10 +#define BTR2_SJW1 btr2.bit._SJW1 +#define BTR2_SJW0 btr2.bit._SJW0 +#define BTR2_BRP5 btr2.bit._BRP5 +#define BTR2_BRP4 btr2.bit._BRP4 +#define BTR2_BRP3 btr2.bit._BRP3 +#define BTR2_BRP2 btr2.bit._BRP2 +#define BTR2_BRP1 btr2.bit._BRP1 +#define BTR2_BRP0 btr2.bit._BRP0 +#define BTR2_Tseg2 btr2.bitc._Tseg2 +#define BTR2_Tseg1 btr2.bitc._Tseg1 +#define BTR2_SJW btr2.bitc._SJW +#define BTR2_BRP btr2.bitc._BRP +__IO_EXTERN IO_WORD intr2; +#define INTR2 intr2 +__IO_EXTERN TESTR2STR testr2; +#define TESTR2 testr2.word +#define TESTR2_Rx testr2.bit._Rx +#define TESTR2_Tx1 testr2.bit._Tx1 +#define TESTR2_Tx0 testr2.bit._Tx0 +#define TESTR2_LBack testr2.bit._LBack +#define TESTR2_Silent testr2.bit._Silent +#define TESTR2_Basic testr2.bit._Basic +#define TESTR2_Tx testr2.bitc._Tx +__IO_EXTERN BRPER2STR brper2; +#define BRPER2 brper2.word +#define BRPER2_BRPE3 brper2.bit._BRPE3 +#define BRPER2_BRPE2 brper2.bit._BRPE2 +#define BRPER2_BRPE1 brper2.bit._BRPE1 +#define BRPER2_BRPE0 brper2.bit._BRPE0 +#define BRPER2_BRPE brper2.bitc._BRPE +__IO_EXTERN BRPE2STR brpe2; +#define BRPE2 brpe2.word +__IO_EXTERN CBSYNC2STR cbsync2; +#define CBSYNC2 cbsync2.word +__IO_EXTERN IF1CREQ2STR if1creq2; /* CAN 2 IF 1 */ +#define IF1CREQ2 if1creq2.word +#define IF1CREQ2_Busy if1creq2.bit._Busy +#define IF1CREQ2_MN5 if1creq2.bit._MN5 +#define IF1CREQ2_MN4 if1creq2.bit._MN4 +#define IF1CREQ2_MN3 if1creq2.bit._MN3 +#define IF1CREQ2_MN2 if1creq2.bit._MN2 +#define IF1CREQ2_MN1 if1creq2.bit._MN1 +#define IF1CREQ2_MN0 if1creq2.bit._MN0 +#define IF1CREQ2_MN if1creq2.bitc._MN +__IO_EXTERN IF1CMSK2STR if1cmsk2; +#define IF1CMSK2 if1cmsk2.word +#define IF1CMSK2_WR if1cmsk2.bit._WR +#define IF1CMSK2_Mask if1cmsk2.bit._Mask +#define IF1CMSK2_Arb if1cmsk2.bit._Arb +#define IF1CMSK2_Control if1cmsk2.bit._Control +#define IF1CMSK2_CIP if1cmsk2.bit._CIP +#define IF1CMSK2_TxReq if1cmsk2.bit._TxReq +#define IF1CMSK2_DataA if1cmsk2.bit._DataA +#define IF1CMSK2_DataB if1cmsk2.bit._DataB +__IO_EXTERN IO_LWORD if1msk122; +#define IF1MSK122 if1msk122 +__IO_EXTERN IF1MSK22STR if1msk22; +#define IF1MSK22 if1msk22.word +#define IF1MSK22_MXtd if1msk22.bit._MXtd +#define IF1MSK22_MDir if1msk22.bit._MDir +__IO_EXTERN IO_WORD if1msk12; +#define IF1MSK12 if1msk12 +__IO_EXTERN IO_LWORD if1arb122; +#define IF1ARB122 if1arb122 +__IO_EXTERN IF1ARB22STR if1arb22; +#define IF1ARB22 if1arb22.word +#define IF1ARB22_MsgVal if1arb22.bit._MsgVal +#define IF1ARB22_Xtd if1arb22.bit._Xtd +#define IF1ARB22_DIR if1arb22.bit._DIR +__IO_EXTERN IO_WORD if1arb12; +#define IF1ARB12 if1arb12 +__IO_EXTERN IF1MCTR2STR if1mctr2; +#define IF1MCTR2 if1mctr2.word +#define IF1MCTR2_NewDat if1mctr2.bit._NewDat +#define IF1MCTR2_MsgLst if1mctr2.bit._MsgLst +#define IF1MCTR2_IntPnd if1mctr2.bit._IntPnd +#define IF1MCTR2_UMask if1mctr2.bit._UMask +#define IF1MCTR2_TxIE if1mctr2.bit._TxIE +#define IF1MCTR2_RxIE if1mctr2.bit._RxIE +#define IF1MCTR2_RmtEn if1mctr2.bit._RmtEn +#define IF1MCTR2_TxRqst if1mctr2.bit._TxRqst +#define IF1MCTR2_EoB if1mctr2.bit._EoB +#define IF1MCTR2_DLC3 if1mctr2.bit._DLC3 +#define IF1MCTR2_DLC2 if1mctr2.bit._DLC2 +#define IF1MCTR2_DLC1 if1mctr2.bit._DLC1 +#define IF1MCTR2_DLC0 if1mctr2.bit._DLC0 +#define IF1MCTR2_DLC if1mctr2.bitc._DLC +__IO_EXTERN IO_LWORD if1dta122; +#define IF1DTA122 if1dta122 +__IO_EXTERN IO_WORD if1dta12; +#define IF1DTA12 if1dta12 +__IO_EXTERN IO_WORD if1dta22; +#define IF1DTA22 if1dta22 +__IO_EXTERN IO_LWORD if1dtb122; +#define IF1DTB122 if1dtb122 +__IO_EXTERN IO_WORD if1dtb12; +#define IF1DTB12 if1dtb12 +__IO_EXTERN IO_WORD if1dtb22; +#define IF1DTB22 if1dtb22 +__IO_EXTERN IO_LWORD if1dta_swp122; +#define IF1DTA_SWP122 if1dta_swp122 +__IO_EXTERN IO_WORD if1dta_swp22; +#define IF1DTA_SWP22 if1dta_swp22 +__IO_EXTERN IO_WORD if1dta_swp12; +#define IF1DTA_SWP12 if1dta_swp12 +__IO_EXTERN IO_LWORD if1dtb_swp122; +#define IF1DTB_SWP122 if1dtb_swp122 +__IO_EXTERN IO_WORD if1dtb_swp22; +#define IF1DTB_SWP22 if1dtb_swp22 +__IO_EXTERN IO_WORD if1dtb_swp12; +#define IF1DTB_SWP12 if1dtb_swp12 +__IO_EXTERN IF2CREQ2STR if2creq2; /* CAN 2 IF 2 */ +#define IF2CREQ2 if2creq2.word +#define IF2CREQ2_Busy if2creq2.bit._Busy +#define IF2CREQ2_MN5 if2creq2.bit._MN5 +#define IF2CREQ2_MN4 if2creq2.bit._MN4 +#define IF2CREQ2_MN3 if2creq2.bit._MN3 +#define IF2CREQ2_MN2 if2creq2.bit._MN2 +#define IF2CREQ2_MN1 if2creq2.bit._MN1 +#define IF2CREQ2_MN0 if2creq2.bit._MN0 +#define IF2CREQ2_MN if2creq2.bitc._MN +__IO_EXTERN IF2CMSK2STR if2cmsk2; +#define IF2CMSK2 if2cmsk2.word +#define IF2CMSK2_WR if2cmsk2.bit._WR +#define IF2CMSK2_Mask if2cmsk2.bit._Mask +#define IF2CMSK2_Arb if2cmsk2.bit._Arb +#define IF2CMSK2_Control if2cmsk2.bit._Control +#define IF2CMSK2_CIP if2cmsk2.bit._CIP +#define IF2CMSK2_TxReq if2cmsk2.bit._TxReq +#define IF2CMSK2_DataA if2cmsk2.bit._DataA +#define IF2CMSK2_DataB if2cmsk2.bit._DataB +__IO_EXTERN IO_LWORD if2msk122; +#define IF2MSK122 if2msk122 +__IO_EXTERN IF2MSK22STR if2msk22; +#define IF2MSK22 if2msk22.word +#define IF2MSK22_MXtd if2msk22.bit._MXtd +#define IF2MSK22_MDir if2msk22.bit._MDir +__IO_EXTERN IO_WORD if2msk12; +#define IF2MSK12 if2msk12 +__IO_EXTERN IO_LWORD if2arb122; +#define IF2ARB122 if2arb122 +__IO_EXTERN IF2ARB22STR if2arb22; +#define IF2ARB22 if2arb22.word +#define IF2ARB22_MsgVal if2arb22.bit._MsgVal +#define IF2ARB22_Xtd if2arb22.bit._Xtd +#define IF2ARB22_DIR if2arb22.bit._DIR +__IO_EXTERN IO_WORD if2arb12; +#define IF2ARB12 if2arb12 +__IO_EXTERN IF2MCTR2STR if2mctr2; +#define IF2MCTR2 if2mctr2.word +#define IF2MCTR2_NewDat if2mctr2.bit._NewDat +#define IF2MCTR2_MsgLst if2mctr2.bit._MsgLst +#define IF2MCTR2_IntPnd if2mctr2.bit._IntPnd +#define IF2MCTR2_UMask if2mctr2.bit._UMask +#define IF2MCTR2_TxIE if2mctr2.bit._TxIE +#define IF2MCTR2_RxIE if2mctr2.bit._RxIE +#define IF2MCTR2_RmtEn if2mctr2.bit._RmtEn +#define IF2MCTR2_TxRqst if2mctr2.bit._TxRqst +#define IF2MCTR2_EoB if2mctr2.bit._EoB +#define IF2MCTR2_DLC3 if2mctr2.bit._DLC3 +#define IF2MCTR2_DLC2 if2mctr2.bit._DLC2 +#define IF2MCTR2_DLC1 if2mctr2.bit._DLC1 +#define IF2MCTR2_DLC0 if2mctr2.bit._DLC0 +#define IF2MCTR2_DLC if2mctr2.bitc._DLC +__IO_EXTERN IO_LWORD if2dta122; +#define IF2DTA122 if2dta122 +__IO_EXTERN IO_WORD if2dta12; +#define IF2DTA12 if2dta12 +__IO_EXTERN IO_WORD if2dta22; +#define IF2DTA22 if2dta22 +__IO_EXTERN IO_LWORD if2dtb122; +#define IF2DTB122 if2dtb122 +__IO_EXTERN IO_WORD if2dtb12; +#define IF2DTB12 if2dtb12 +__IO_EXTERN IO_WORD if2dtb22; +#define IF2DTB22 if2dtb22 +__IO_EXTERN IO_LWORD if2dta_swp122; +#define IF2DTA_SWP122 if2dta_swp122 +__IO_EXTERN IO_WORD if2dta_swp22; +#define IF2DTA_SWP22 if2dta_swp22 +__IO_EXTERN IO_WORD if2dta_swp12; +#define IF2DTA_SWP12 if2dta_swp12 +__IO_EXTERN IO_LWORD if2dtb_swp122; +#define IF2DTB_SWP122 if2dtb_swp122 +__IO_EXTERN IO_WORD if2dtb_swp22; +#define IF2DTB_SWP22 if2dtb_swp22 +__IO_EXTERN IO_WORD if2dtb_swp12; +#define IF2DTB_SWP12 if2dtb_swp12 +__IO_EXTERN IO_LWORD treqr122; /* CAN 2 Status Flags */ +#define TREQR122 treqr122 +__IO_EXTERN IO_WORD treqr22; +#define TREQR22 treqr22 +__IO_EXTERN IO_WORD treqr12; +#define TREQR12 treqr12 +__IO_EXTERN IO_LWORD newdt122; +#define NEWDT122 newdt122 +__IO_EXTERN IO_WORD newdt22; +#define NEWDT22 newdt22 +__IO_EXTERN IO_WORD newdt12; +#define NEWDT12 newdt12 +__IO_EXTERN IO_LWORD intpnd122; +#define INTPND122 intpnd122 +__IO_EXTERN IO_WORD intpnd22; +#define INTPND22 intpnd22 +__IO_EXTERN IO_WORD intpnd12; +#define INTPND12 intpnd12 +__IO_EXTERN IO_LWORD msgval122; +#define MSGVAL122 msgval122 +__IO_EXTERN IO_WORD msgval22; +#define MSGVAL22 msgval22 +__IO_EXTERN IO_WORD msgval12; +#define MSGVAL12 msgval12 +/* include : INC467_CAN.INC */ +/*-------------------------------------------------------------------*/ +/* INC467.CAN : Old bit name of CAN Registers */ + +/* alias macro definition for CAN Bits */ +#define BTR0_Tsg22 btr0.bit._Tseg22 +#define BTR0_Tsg21 btr0.bit._Tseg21 +#define BTR0_Tsg20 btr0.bit._Tseg20 +#define BTR0_Tsg2 btr0.bitc._Tseg2 +#define BTR0_Tsg13 btr0.bit._Tseg13 +#define BTR0_Tsg12 btr0.bit._Tseg12 +#define BTR0_Tsg11 btr0.bit._Tseg11 +#define BTR0_Tsg10 btr0.bit._Tseg10 +#define BTR0_Tsg1 btr0.bitc._Tseg1 +#define IF1CMSK0_Contr if1cmsk0.bit._Control +#define IF2CMSK0_Contr if2cmsk0.bit._Control + +#define BTR1_Tsg22 btr1.bit._Tseg22 +#define BTR1_Tsg21 btr1.bit._Tseg21 +#define BTR1_Tsg20 btr1.bit._Tseg20 +#define BTR1_Tsg2 btr1.bitc._Tseg2 +#define BTR1_Tsg13 btr1.bit._Tseg13 +#define BTR1_Tsg12 btr1.bit._Tseg12 +#define BTR1_Tsg11 btr1.bit._Tseg11 +#define BTR1_Tsg10 btr1.bit._Tseg10 +#define BTR1_Tsg1 btr1.bitc._Tseg1 +#define IF1CMSK1_Contr if1cmsk1.bit._Control +#define IF2CMSK1_Contr if2cmsk1.bit._Control + +#define BTR2_Tsg22 btr2.bit._Tseg22 +#define BTR2_Tsg21 btr2.bit._Tseg21 +#define BTR2_Tsg20 btr2.bit._Tseg20 +#define BTR2_Tsg2 btr2.bitc._Tseg2 +#define BTR2_Tsg13 btr2.bit._Tseg13 +#define BTR2_Tsg12 btr2.bit._Tseg12 +#define BTR2_Tsg11 btr2.bit._Tseg11 +#define BTR2_Tsg10 btr2.bit._Tseg10 +#define BTR2_Tsg1 btr2.bitc._Tseg1 +#define IF1CMSK2_Contr if1cmsk2.bit._Control +#define IF2CMSK2_Contr if2cmsk2.bit._Control +/*-------------------------------------------------------------------*/ +__IO_EXTERN BCTRLSTR bctrl; /* EDSU/MPU Registers */ +#define BCTRL bctrl.lword +#define BCTRL_SR bctrl.bit._SR +#define BCTRL_SW bctrl.bit._SW +#define BCTRL_SX bctrl.bit._SX +#define BCTRL_UR bctrl.bit._UR +#define BCTRL_UW bctrl.bit._UW +#define BCTRL_UX bctrl.bit._UX +#define BCTRL_FCPU bctrl.bit._FCPU +#define BCTRL_FDMA bctrl.bit._FDMA +#define BCTRL_EEMM bctrl.bit._EEMM +#define BCTRL_PFD bctrl.bit._PFD +#define BCTRL_SINT1 bctrl.bit._SINT1 +#define BCTRL_SINT0 bctrl.bit._SINT0 +#define BCTRL_EINT1 bctrl.bit._EINT1 +#define BCTRL_EINT0 bctrl.bit._EINT0 +#define BCTRL_EINTT bctrl.bit._EINTT +#define BCTRL_EINTR bctrl.bit._EINTR +#define BCTRL_SINT bctrl.bitc._SINT +#define BCTRL_EINT bctrl.bitc._EINT +__IO_EXTERN BSTATSTR bstat; +#define BSTAT bstat.lword +#define BSTAT_IDX4 bstat.bit._IDX4 +#define BSTAT_IDX3 bstat.bit._IDX3 +#define BSTAT_IDX2 bstat.bit._IDX2 +#define BSTAT_IDX1 bstat.bit._IDX1 +#define BSTAT_IDX0 bstat.bit._IDX0 +#define BSTAT_CDMA bstat.bit._CDMA +#define BSTAT_CSZ1 bstat.bit._CSZ1 +#define BSTAT_CSZ0 bstat.bit._CSZ0 +#define BSTAT_CRW1 bstat.bit._CRW1 +#define BSTAT_CRW0 bstat.bit._CRW0 +#define BSTAT_PV bstat.bit._PV +#define BSTAT_RST bstat.bit._RST +#define BSTAT_INT1 bstat.bit._INT1 +#define BSTAT_INT0 bstat.bit._INT0 +#define BSTAT_INTT bstat.bit._INTT +#define BSTAT_INTR bstat.bit._INTR +#define BSTAT_IDX bstat.bitc._IDX +#define BSTAT_CSZ bstat.bitc._CSZ +#define BSTAT_CRW bstat.bitc._CRW +#define BSTAT_INT bstat.bitc._INT +__IO_EXTERN IO_LWORD biac; +#define BIAC biac +__IO_EXTERN IO_LWORD boac; +#define BOAC boac +__IO_EXTERN BIRQSTR birq; +#define BIRQ birq.lword +#define BIRQ_BD31 birq.bit._BD31 +#define BIRQ_BD30 birq.bit._BD30 +#define BIRQ_BD29 birq.bit._BD29 +#define BIRQ_BD28 birq.bit._BD28 +#define BIRQ_BD27 birq.bit._BD27 +#define BIRQ_BD26 birq.bit._BD26 +#define BIRQ_BD25 birq.bit._BD25 +#define BIRQ_BD24 birq.bit._BD24 +#define BIRQ_BD23 birq.bit._BD23 +#define BIRQ_BD22 birq.bit._BD22 +#define BIRQ_BD21 birq.bit._BD21 +#define BIRQ_BD20 birq.bit._BD20 +#define BIRQ_BD19 birq.bit._BD19 +#define BIRQ_BD18 birq.bit._BD18 +#define BIRQ_BD17 birq.bit._BD17 +#define BIRQ_BD16 birq.bit._BD16 +#define BIRQ_BD15 birq.bit._BD15 +#define BIRQ_BD14 birq.bit._BD14 +#define BIRQ_BD13 birq.bit._BD13 +#define BIRQ_BD12 birq.bit._BD12 +#define BIRQ_BD11 birq.bit._BD11 +#define BIRQ_BD10 birq.bit._BD10 +#define BIRQ_BD9 birq.bit._BD9 +#define BIRQ_BD8 birq.bit._BD8 +#define BIRQ_BD7 birq.bit._BD7 +#define BIRQ_BD6 birq.bit._BD6 +#define BIRQ_BD5 birq.bit._BD5 +#define BIRQ_BD4 birq.bit._BD4 +#define BIRQ_BD3 birq.bit._BD3 +#define BIRQ_BD2 birq.bit._BD2 +#define BIRQ_BD1 birq.bit._BD1 +#define BIRQ_BD0 birq.bit._BD0 +__IO_EXTERN BCR0STR bcr0; +#define BCR0 bcr0.lword +#define BCR0_SRX1 bcr0.bit._SRX1 +#define BCR0_SW1 bcr0.bit._SW1 +#define BCR0_SRX0 bcr0.bit._SRX0 +#define BCR0_SW0 bcr0.bit._SW0 +#define BCR0_URX1 bcr0.bit._URX1 +#define BCR0_UW1 bcr0.bit._UW1 +#define BCR0_URX0 bcr0.bit._URX0 +#define BCR0_UW0 bcr0.bit._UW0 +#define BCR0_MPE bcr0.bit._MPE +#define BCR0_COMB bcr0.bit._COMB +#define BCR0_CTC1 bcr0.bit._CTC1 +#define BCR0_CTC0 bcr0.bit._CTC0 +#define BCR0_OBS1 bcr0.bit._OBS1 +#define BCR0_OBS0 bcr0.bit._OBS0 +#define BCR0_OBT1 bcr0.bit._OBT1 +#define BCR0_OBT0 bcr0.bit._OBT0 +#define BCR0_EP3 bcr0.bit._EP3 +#define BCR0_EP2 bcr0.bit._EP2 +#define BCR0_EP1 bcr0.bit._EP1 +#define BCR0_EP0 bcr0.bit._EP0 +#define BCR0_EM1 bcr0.bit._EM1 +#define BCR0_EM0 bcr0.bit._EM0 +#define BCR0_ER1 bcr0.bit._ER1 +#define BCR0_ER0 bcr0.bit._ER0 +#define BCR0_CTC bcr0.bitc._CTC +#define BCR0_OBS bcr0.bitc._OBS +#define BCR0_OBT bcr0.bitc._OBT +#define BCR0_EP bcr0.bitc._EP +#define BCR0_EM bcr0.bitc._EM +#define BCR0_ER bcr0.bitc._ER +__IO_EXTERN BCR1STR bcr1; +#define BCR1 bcr1.lword +#define BCR1_SRX1 bcr1.bit._SRX1 +#define BCR1_SW1 bcr1.bit._SW1 +#define BCR1_SRX0 bcr1.bit._SRX0 +#define BCR1_SW0 bcr1.bit._SW0 +#define BCR1_URX1 bcr1.bit._URX1 +#define BCR1_UW1 bcr1.bit._UW1 +#define BCR1_URX0 bcr1.bit._URX0 +#define BCR1_UW0 bcr1.bit._UW0 +#define BCR1_MPE bcr1.bit._MPE +#define BCR1_COMB bcr1.bit._COMB +#define BCR1_CTC1 bcr1.bit._CTC1 +#define BCR1_CTC0 bcr1.bit._CTC0 +#define BCR1_OBS1 bcr1.bit._OBS1 +#define BCR1_OBS0 bcr1.bit._OBS0 +#define BCR1_OBT1 bcr1.bit._OBT1 +#define BCR1_OBT0 bcr1.bit._OBT0 +#define BCR1_EP3 bcr1.bit._EP3 +#define BCR1_EP2 bcr1.bit._EP2 +#define BCR1_EP1 bcr1.bit._EP1 +#define BCR1_EP0 bcr1.bit._EP0 +#define BCR1_EM1 bcr1.bit._EM1 +#define BCR1_EM0 bcr1.bit._EM0 +#define BCR1_ER1 bcr1.bit._ER1 +#define BCR1_ER0 bcr1.bit._ER0 +#define BCR1_CTC bcr1.bitc._CTC +#define BCR1_OBS bcr1.bitc._OBS +#define BCR1_OBT bcr1.bitc._OBT +#define BCR1_EP bcr1.bitc._EP +#define BCR1_EM bcr1.bitc._EM +#define BCR1_ER bcr1.bitc._ER +__IO_EXTERN BCR2STR bcr2; +#define BCR2 bcr2.lword +#define BCR2_SRX1 bcr2.bit._SRX1 +#define BCR2_SW1 bcr2.bit._SW1 +#define BCR2_SRX0 bcr2.bit._SRX0 +#define BCR2_SW0 bcr2.bit._SW0 +#define BCR2_URX1 bcr2.bit._URX1 +#define BCR2_UW1 bcr2.bit._UW1 +#define BCR2_URX0 bcr2.bit._URX0 +#define BCR2_UW0 bcr2.bit._UW0 +#define BCR2_MPE bcr2.bit._MPE +#define BCR2_COMB bcr2.bit._COMB +#define BCR2_CTC1 bcr2.bit._CTC1 +#define BCR2_CTC0 bcr2.bit._CTC0 +#define BCR2_OBS1 bcr2.bit._OBS1 +#define BCR2_OBS0 bcr2.bit._OBS0 +#define BCR2_OBT1 bcr2.bit._OBT1 +#define BCR2_OBT0 bcr2.bit._OBT0 +#define BCR2_EP3 bcr2.bit._EP3 +#define BCR2_EP2 bcr2.bit._EP2 +#define BCR2_EP1 bcr2.bit._EP1 +#define BCR2_EP0 bcr2.bit._EP0 +#define BCR2_EM1 bcr2.bit._EM1 +#define BCR2_EM0 bcr2.bit._EM0 +#define BCR2_ER1 bcr2.bit._ER1 +#define BCR2_ER0 bcr2.bit._ER0 +#define BCR2_CTC bcr2.bitc._CTC +#define BCR2_OBS bcr2.bitc._OBS +#define BCR2_OBT bcr2.bitc._OBT +#define BCR2_EP bcr2.bitc._EP +#define BCR2_EM bcr2.bitc._EM +#define BCR2_ER bcr2.bitc._ER +__IO_EXTERN BCR3STR bcr3; +#define BCR3 bcr3.lword +#define BCR3_SRX1 bcr3.bit._SRX1 +#define BCR3_SW1 bcr3.bit._SW1 +#define BCR3_SRX0 bcr3.bit._SRX0 +#define BCR3_SW0 bcr3.bit._SW0 +#define BCR3_URX1 bcr3.bit._URX1 +#define BCR3_UW1 bcr3.bit._UW1 +#define BCR3_URX0 bcr3.bit._URX0 +#define BCR3_UW0 bcr3.bit._UW0 +#define BCR3_MPE bcr3.bit._MPE +#define BCR3_COMB bcr3.bit._COMB +#define BCR3_CTC1 bcr3.bit._CTC1 +#define BCR3_CTC0 bcr3.bit._CTC0 +#define BCR3_OBS1 bcr3.bit._OBS1 +#define BCR3_OBS0 bcr3.bit._OBS0 +#define BCR3_OBT1 bcr3.bit._OBT1 +#define BCR3_OBT0 bcr3.bit._OBT0 +#define BCR3_EP3 bcr3.bit._EP3 +#define BCR3_EP2 bcr3.bit._EP2 +#define BCR3_EP1 bcr3.bit._EP1 +#define BCR3_EP0 bcr3.bit._EP0 +#define BCR3_EM1 bcr3.bit._EM1 +#define BCR3_EM0 bcr3.bit._EM0 +#define BCR3_ER1 bcr3.bit._ER1 +#define BCR3_ER0 bcr3.bit._ER0 +#define BCR3_CTC bcr3.bitc._CTC +#define BCR3_OBS bcr3.bitc._OBS +#define BCR3_OBT bcr3.bitc._OBT +#define BCR3_EP bcr3.bitc._EP +#define BCR3_EM bcr3.bitc._EM +#define BCR3_ER bcr3.bitc._ER +__IO_EXTERN BCR4STR bcr4; +#define BCR4 bcr4.lword +#define BCR4_SRX1 bcr4.bit._SRX1 +#define BCR4_SW1 bcr4.bit._SW1 +#define BCR4_SRX0 bcr4.bit._SRX0 +#define BCR4_SW0 bcr4.bit._SW0 +#define BCR4_URX1 bcr4.bit._URX1 +#define BCR4_UW1 bcr4.bit._UW1 +#define BCR4_URX0 bcr4.bit._URX0 +#define BCR4_UW0 bcr4.bit._UW0 +#define BCR4_MPE bcr4.bit._MPE +#define BCR4_COMB bcr4.bit._COMB +#define BCR4_CTC1 bcr4.bit._CTC1 +#define BCR4_CTC0 bcr4.bit._CTC0 +#define BCR4_OBS1 bcr4.bit._OBS1 +#define BCR4_OBS0 bcr4.bit._OBS0 +#define BCR4_OBT1 bcr4.bit._OBT1 +#define BCR4_OBT0 bcr4.bit._OBT0 +#define BCR4_EP3 bcr4.bit._EP3 +#define BCR4_EP2 bcr4.bit._EP2 +#define BCR4_EP1 bcr4.bit._EP1 +#define BCR4_EP0 bcr4.bit._EP0 +#define BCR4_EM1 bcr4.bit._EM1 +#define BCR4_EM0 bcr4.bit._EM0 +#define BCR4_ER1 bcr4.bit._ER1 +#define BCR4_ER0 bcr4.bit._ER0 +#define BCR4_CTC bcr4.bitc._CTC +#define BCR4_OBS bcr4.bitc._OBS +#define BCR4_OBT bcr4.bitc._OBT +#define BCR4_EP bcr4.bitc._EP +#define BCR4_EM bcr4.bitc._EM +#define BCR4_ER bcr4.bitc._ER +__IO_EXTERN BCR5STR bcr5; +#define BCR5 bcr5.lword +#define BCR5_SRX1 bcr5.bit._SRX1 +#define BCR5_SW1 bcr5.bit._SW1 +#define BCR5_SRX0 bcr5.bit._SRX0 +#define BCR5_SW0 bcr5.bit._SW0 +#define BCR5_URX1 bcr5.bit._URX1 +#define BCR5_UW1 bcr5.bit._UW1 +#define BCR5_URX0 bcr5.bit._URX0 +#define BCR5_UW0 bcr5.bit._UW0 +#define BCR5_MPE bcr5.bit._MPE +#define BCR5_COMB bcr5.bit._COMB +#define BCR5_CTC1 bcr5.bit._CTC1 +#define BCR5_CTC0 bcr5.bit._CTC0 +#define BCR5_OBS1 bcr5.bit._OBS1 +#define BCR5_OBS0 bcr5.bit._OBS0 +#define BCR5_OBT1 bcr5.bit._OBT1 +#define BCR5_OBT0 bcr5.bit._OBT0 +#define BCR5_EP3 bcr5.bit._EP3 +#define BCR5_EP2 bcr5.bit._EP2 +#define BCR5_EP1 bcr5.bit._EP1 +#define BCR5_EP0 bcr5.bit._EP0 +#define BCR5_EM1 bcr5.bit._EM1 +#define BCR5_EM0 bcr5.bit._EM0 +#define BCR5_ER1 bcr5.bit._ER1 +#define BCR5_ER0 bcr5.bit._ER0 +#define BCR5_CTC bcr5.bitc._CTC +#define BCR5_OBS bcr5.bitc._OBS +#define BCR5_OBT bcr5.bitc._OBT +#define BCR5_EP bcr5.bitc._EP +#define BCR5_EM bcr5.bitc._EM +#define BCR5_ER bcr5.bitc._ER +__IO_EXTERN BCR6STR bcr6; +#define BCR6 bcr6.lword +#define BCR6_SRX1 bcr6.bit._SRX1 +#define BCR6_SW1 bcr6.bit._SW1 +#define BCR6_SRX0 bcr6.bit._SRX0 +#define BCR6_SW0 bcr6.bit._SW0 +#define BCR6_URX1 bcr6.bit._URX1 +#define BCR6_UW1 bcr6.bit._UW1 +#define BCR6_URX0 bcr6.bit._URX0 +#define BCR6_UW0 bcr6.bit._UW0 +#define BCR6_MPE bcr6.bit._MPE +#define BCR6_COMB bcr6.bit._COMB +#define BCR6_CTC1 bcr6.bit._CTC1 +#define BCR6_CTC0 bcr6.bit._CTC0 +#define BCR6_OBS1 bcr6.bit._OBS1 +#define BCR6_OBS0 bcr6.bit._OBS0 +#define BCR6_OBT1 bcr6.bit._OBT1 +#define BCR6_OBT0 bcr6.bit._OBT0 +#define BCR6_EP3 bcr6.bit._EP3 +#define BCR6_EP2 bcr6.bit._EP2 +#define BCR6_EP1 bcr6.bit._EP1 +#define BCR6_EP0 bcr6.bit._EP0 +#define BCR6_EM1 bcr6.bit._EM1 +#define BCR6_EM0 bcr6.bit._EM0 +#define BCR6_ER1 bcr6.bit._ER1 +#define BCR6_ER0 bcr6.bit._ER0 +#define BCR6_CTC bcr6.bitc._CTC +#define BCR6_OBS bcr6.bitc._OBS +#define BCR6_OBT bcr6.bitc._OBT +#define BCR6_EP bcr6.bitc._EP +#define BCR6_EM bcr6.bitc._EM +#define BCR6_ER bcr6.bitc._ER +__IO_EXTERN BCR7STR bcr7; +#define BCR7 bcr7.lword +#define BCR7_SRX1 bcr7.bit._SRX1 +#define BCR7_SW1 bcr7.bit._SW1 +#define BCR7_SRX0 bcr7.bit._SRX0 +#define BCR7_SW0 bcr7.bit._SW0 +#define BCR7_URX1 bcr7.bit._URX1 +#define BCR7_UW1 bcr7.bit._UW1 +#define BCR7_URX0 bcr7.bit._URX0 +#define BCR7_UW0 bcr7.bit._UW0 +#define BCR7_MPE bcr7.bit._MPE +#define BCR7_COMB bcr7.bit._COMB +#define BCR7_CTC1 bcr7.bit._CTC1 +#define BCR7_CTC0 bcr7.bit._CTC0 +#define BCR7_OBS1 bcr7.bit._OBS1 +#define BCR7_OBS0 bcr7.bit._OBS0 +#define BCR7_OBT1 bcr7.bit._OBT1 +#define BCR7_OBT0 bcr7.bit._OBT0 +#define BCR7_EP3 bcr7.bit._EP3 +#define BCR7_EP2 bcr7.bit._EP2 +#define BCR7_EP1 bcr7.bit._EP1 +#define BCR7_EP0 bcr7.bit._EP0 +#define BCR7_EM1 bcr7.bit._EM1 +#define BCR7_EM0 bcr7.bit._EM0 +#define BCR7_ER1 bcr7.bit._ER1 +#define BCR7_ER0 bcr7.bit._ER0 +#define BCR7_CTC bcr7.bitc._CTC +#define BCR7_OBS bcr7.bitc._OBS +#define BCR7_OBT bcr7.bitc._OBT +#define BCR7_EP bcr7.bitc._EP +#define BCR7_EM bcr7.bitc._EM +#define BCR7_ER bcr7.bitc._ER +__IO_EXTERN IO_LWORD bad0; +#define BAD0 bad0 +__IO_EXTERN IO_LWORD bad1; +#define BAD1 bad1 +__IO_EXTERN IO_LWORD bad2; +#define BAD2 bad2 +__IO_EXTERN IO_LWORD bad3; +#define BAD3 bad3 +__IO_EXTERN IO_LWORD bad4; +#define BAD4 bad4 +__IO_EXTERN IO_LWORD bad5; +#define BAD5 bad5 +__IO_EXTERN IO_LWORD bad6; +#define BAD6 bad6 +__IO_EXTERN IO_LWORD bad7; +#define BAD7 bad7 +__IO_EXTERN IO_LWORD bad8; +#define BAD8 bad8 +__IO_EXTERN IO_LWORD bad9; +#define BAD9 bad9 +__IO_EXTERN IO_LWORD bad10; +#define BAD10 bad10 +__IO_EXTERN IO_LWORD bad11; +#define BAD11 bad11 +__IO_EXTERN IO_LWORD bad12; +#define BAD12 bad12 +__IO_EXTERN IO_LWORD bad13; +#define BAD13 bad13 +__IO_EXTERN IO_LWORD bad14; +#define BAD14 bad14 +__IO_EXTERN IO_LWORD bad15; +#define BAD15 bad15 +__IO_EXTERN IO_LWORD fsv1; /* FSV & BSV Registers */ +#define FSV1 fsv1 +__IO_EXTERN IO_LWORD bsv1; +#define BSV1 bsv1 +__IO_EXTERN IO_LWORD fsv2; +#define FSV2 fsv2 +__IO_EXTERN IO_LWORD bsv2; +#define BSV2 bsv2 +/* include : INC467_BSYNC.INC */ +/*-------------------------------------------------------------------*/ +/* INC467.BSYNC : Macros Bus Sync*/ + +#define RB_SYNC if(RBSYNC) +#define CB_SYNC0 if(CBSYNC0) +#define CB_SYNC1 if(CBSYNC1) +#define CB_SYNC2 if(CBSYNC2) +/*-------------------------------------------------------------------*/ +#endif /* __FASM__ */ +#endif /* __MB91XXX_H */ +#endif /* __IO_DEFINE */ diff --git a/20080212/Demo/MB91460_Softune/SRC/partest/partest.c b/20080212/Demo/MB91460_Softune/SRC/partest/partest.c new file mode 100644 index 000000000..4e7c1900b --- /dev/null +++ b/20080212/Demo/MB91460_Softune/SRC/partest/partest.c @@ -0,0 +1,81 @@ +/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ +/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ +/* ELIGIBILITY FOR ANY PURPOSES. */ +/* (C) Fujitsu Microelectronics Europe GmbH */ +/*------------------------------------------------------------------------ + MAIN.C + - description + - See README.TXT for project description and disclaimer. +-------------------------------------------------------------------------*/ +/*************************@INCLUDE_START************************/ + + + +/* Hardware specific includes. */ +#include "mb91467d.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#define partstNUM_LEDs 8 + +static unsigned portSHORT sState[ partstNUM_LEDs ] = { pdFALSE }; + +/*-----------------------------------------------------------*/ +void vParTestInitialise( void ) +{ + /* Set port for LED outputs. */ + DDR16 = 0xFF; + + /* Start with LEDs off. */ + PDR25 = 0x00; +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ + if( uxLED < partstNUM_LEDs ) + { + taskENTER_CRITICAL(); + + /* Toggle the state of the single genuine on board LED. */ + if( sState[ uxLED ]) + { + PDR25 |= ( 1 << uxLED ); + } + else + { + PDR25 &= ~( 1 << uxLED ); + } + + sState[ uxLED ] = !( sState[ uxLED ] ); + + taskEXIT_CRITICAL(); + } +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ + /* Set or clear the output [in this case show or hide the '*' character. */ + if( uxLED < partstNUM_LEDs ) + { + taskENTER_CRITICAL(); + { + if( xValue ) + { + PDR25 |= ( 1 << uxLED ); + sState[ uxLED ] = 1; + } + else + { + PDR25 &= ~( 1 << uxLED ); + sState[ uxLED ] = 0; + } + } + taskEXIT_CRITICAL(); + } +} +/*-----------------------------------------------------------*/ + diff --git a/20080212/Demo/MB91460_Softune/SRC/serial/serial.c b/20080212/Demo/MB91460_Softune/SRC/serial/serial.c new file mode 100644 index 000000000..090d79935 --- /dev/null +++ b/20080212/Demo/MB91460_Softune/SRC/serial/serial.c @@ -0,0 +1,207 @@ +/* + FreeRTOS.org V4.7.0 - Copyright (C) 2003-2007 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + + Also see http://www.SafeRTOS.com a version that has been certified for use + in safety critical systems, plus commercial licensing, development and + support options. + *************************************************************************** +*/ + + +/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER. + * + * This file only supports UART 2 + */ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "queue.h" +#include "task.h" + +/* Demo application includes. */ +#include "serial.h" + +/* The queue used to hold received characters. */ +static xQueueHandle xRxedChars; + +/* The queue used to hold characters waiting transmission. */ +static xQueueHandle xCharsForTx; + +static volatile portSHORT sTHREEmpty; + +/*-----------------------------------------------------------*/ + +xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) +{ +//unsigned portLONG ulBaudRateCount; + + portENTER_CRITICAL(); + { + /* Create the queues used by the com test task. */ + xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + + /* Initialize UART asynchronous mode */ + BGR02 = configPER_CLOCK_HZ / ulWantedBaud; + + SCR02 = 0x17; /* 8N1 */ + SMR02 = 0x0d; /* enable SOT3, Reset, normal mode */ + SSR02 = 0x02; /* LSB first, enable receive interrupts */ + + PFR20_D0 = 1; // enable UART + PFR20_D1 = 1; // enable UART + + EPFR20_D1 = 0; // enable UART + } + portEXIT_CRITICAL(); + + /* Unlike other ports, this serial code does not allow for more than one + com port. We therefore don't return a pointer to a port structure and can + instead just return NULL. */ + return NULL; +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) +{ + /* Get the next character from the buffer. Return false if no characters + are available, or arrive before xBlockTime expires. */ + if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) + { + return pdTRUE; + } + else + { + return pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) +{ +signed portBASE_TYPE xReturn; + + /* Transmit a character. */ + portENTER_CRITICAL(); + { + if( sTHREEmpty == pdTRUE ) + { + /* If sTHREEmpty is true then the UART Tx ISR has indicated that + there are no characters queued to be transmitted - so we can + write the character directly to the shift Tx register. */ + sTHREEmpty = pdFALSE; + TDR02 = cOutChar; + xReturn = pdPASS; + } + else + { + /* sTHREEmpty is false, so there are still characters waiting to be + transmitted. We have to queue this character so it gets + transmitted in turn. */ + + /* Return false if after the block time there is no room on the Tx + queue. It is ok to block inside a critical section as each task + maintains it's own critical section status. */ + if (xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) == pdTRUE) + { + xReturn = pdPASS; + } + else + { + xReturn = pdFAIL; + } + } + + if (pdPASS == xReturn) + { + /* Turn on the Tx interrupt so the ISR will remove the character from the + queue and send it. This does not need to be in a critical section as + if the interrupt has already removed the character the next interrupt + will simply turn off the Tx interrupt again. */ + SSR02_TIE = 1; + } + + } + portEXIT_CRITICAL(); + + return pdPASS; +} +/*-----------------------------------------------------------*/ + +/* + * UART RX interrupt service routine. + */ + __interrupt void UART2_RxISR (void) +{ + signed portCHAR cChar; + + /* Get the character from the UART and post it on the queue of Rxed + characters. */ + cChar = RDR02; + + if( xQueueSendFromISR( xRxedChars, &cChar, pdFALSE ) ) + { + /*If the post causes a task to wake force a context switch + as the woken task may have a higher priority than the task we have + interrupted. */ + portYIELD_FROM_ISR(); + } +} + +/*-----------------------------------------------------------*/ + +/* + * UART Tx interrupt service routine. + */ +__interrupt void UART2_TxISR (void) +{ + signed portCHAR cChar; + signed portBASE_TYPE xTaskWoken; + + /* The previous character has been transmitted. See if there are any + further characters waiting transmission. */ + if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWoken ) == pdTRUE ) + { + /* There was another character queued - transmit it now. */ + TDR02 = cChar; + } + else + { + /* There were no other characters to transmit. */ + sTHREEmpty = pdTRUE; + + /* Disable transmit interrupts */ + SSR02_TIE = 0; + } +} + diff --git a/20080212/Demo/MB91460_Softune/SRC/utility/taskutility.c b/20080212/Demo/MB91460_Softune/SRC/utility/taskutility.c new file mode 100644 index 000000000..b23f633f2 --- /dev/null +++ b/20080212/Demo/MB91460_Softune/SRC/utility/taskutility.c @@ -0,0 +1,215 @@ +/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ +/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ +/* ELIGIBILITY FOR ANY PURPOSES. */ +/* (C) Fujitsu Microelectronics Europe GmbH */ +/*------------------------------------------------------------------------ + taskutility.C + - +-------------------------------------------------------------------------*/ +#include "mb91467d.h" +#include "vectors.h" +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +static void vUART5Task( void *pvParameters ); + +const char ASCII[] = "0123456789ABCDEF"; + +void vInitUart5( void ); + +xSemaphoreHandle xSemaphore; + +void vInitUart5( void ) +{ + //Initialize UART asynchronous mode + BGR05 = 1666; // 9600 Baud @ 16MHz + SCR05 = 0x17; // 7N2 + SMR05 = 0x0d; // enable SOT3, Reset, normal mode + SSR05 = 0x00; // LSB first + PFR19_D4 = 1; // enable UART + PFR19_D5 = 1; // enable UART + + //EPFR19 = 0x00; // enable UART + SSR05_RIE = 1; +} + +void Putch5( char ch ) /* sends a char */ +{ + while( SSR05_TDRE == 0 ); + + /* wait for transmit buffer empty */ + TDR05 = ch; /* put ch into buffer */ +} + +char Getch5( void ) /* waits for and returns incomming char */ +{ + volatile unsigned ch; + + while( SSR05_RDRF == 0 ); + + /* wait for data received */ + if( SSR05_ORE ) /* overrun error */ + { + ch = RDR05; /* reset error flags */ + return ( char ) ( -1 ); + } + else + { + return( RDR05 ); /* return char */ + } +} + +void Puts5( const char *Name5 ) /* Puts a String to UART */ +{ + volatile portSHORT i, len; + len = strlen( Name5 ); + + for( i = 0; i < strlen(Name5); i++ ) /* go through string */ + { + if( Name5[i] == 10 ) + { + Putch5( 13 ); + } + + Putch5( Name5[i] ); /* send it out */ + } +} + +void Puthex5( unsigned long n, unsigned char digits ) +{ + unsigned portCHAR digit = 0, div = 0, i; + + div = ( 4 * (digits - 1) ); /* init shift divisor */ + for( i = 0; i < digits; i++ ) + { + digit = ( (n >> div) & 0xF ); /* get hex-digit value */ + Putch5( digit + ((digit < 0xA) ? '0' : 'A' - 0xA) ); + div -= 4; /* next digit shift */ + } +} + +void Putdec5( unsigned long x, int digits ) +{ + portSHORT i; + portCHAR buf[10], sign = 1; + + if( digits < 0 ) + { /* should be print of zero? */ + digits *= ( -1 ); + sign = 1; + } + + buf[digits] = '\0'; /* end sign of string */ + + for( i = digits; i > 0; i-- ) + { + buf[i - 1] = ASCII[x % 10]; + x = x / 10; + } + + if( sign ) + { + for( i = 0; buf[i] == '0'; i++ ) + { /* no print of zero */ + if( i < digits - 1 ) + { + buf[i] = ' '; + } + } + } + + Puts5( buf ); /* send string */ +} + +void vUtilityStartTraceTask( unsigned portBASE_TYPE uxPriority ) +{ + portENTER_CRITICAL(); + vInitUart5(); + portENTER_CRITICAL(); + + vSemaphoreCreateBinary( xSemaphore ); + + if( xSemaphore != NULL ) + { + xTaskCreate( vUART5Task, (signed portCHAR *) "UART4", ( unsigned portSHORT ) 2048, ( void * ) NULL, uxPriority, NULL ); + } +} + +static void vUART5Task( void *pvParameters ) +{ + portCHAR tasklist_buff[512], trace_buff[512]; + unsigned portLONG trace_len, j; + + unsigned portCHAR ch; + + Puts5( "\n -------------MB91467D FreeRTOS DEMO Task List and Trace Utility----------- \n" ); + + for( ;; ) + { + Puts5( "\n\rPress any of the following keys for the corresponding functionality: " ); + + Puts5( "\n\r1: To call vTaskList() and display current task status " ); + + Puts5( "\n\r2: To call vTaskStartTrace() and to display trace results once the trace ends" ); + + SSR05_RIE = 1; + + /* Block on the semaphore. The UART interrupt will use the semaphore to + wake this task when required. */ + xSemaphoreTake( xSemaphore, portMAX_DELAY ); + + ch = Getch5(); + + switch( ch ) + { + case '1': + vTaskList( (signed char *) tasklist_buff ); + Puts5( "\n\rThe current task list is as follows...." ); + Puts5( "\n\r----------------------------------------------" ); + Puts5( "\n\rName State Priority Stack Number" ); + Puts5( "\n\r----------------------------------------------" ); + Puts5( tasklist_buff ); + Puts5( "\r----------------------------------------------" ); + break; + + case '2': + vTaskStartTrace( (signed char *) trace_buff, 512 ); + Puts5( "\n\rThe trace started!!" ); + vTaskDelay( (portTickType) 450 ); + trace_len = ulTaskEndTrace(); + Puts5( "\n\rThe trace ended!!" ); + Puts5( "\n\rThe trace is as follows...." ); + Puts5( "\n\r--------------------------------------------------------" ); + Puts5( "\n\r Tick | Task Number | Tick | Task Number |" ); + Puts5( "\n\r--------------------------------------------------------\n\r" ); + for( j = 0; j < trace_len; j++ ) + { + Puthex5( trace_buff[j], 2 ); + if( j % 4 == 3 ) + { + Puts5( " | " ); + } + + if( j % 16 == 15 ) + { + Puts5( "\n" ); + } + } + + Puts5( "\r--------------------------------------------------------" ); + break; + + default: + break; + } + + Puts5( "\n" ); + } +} + +__interrupt void UART5_RxISR( void ) +{ + SSR05_RIE = 0; + xSemaphoreGiveFromISR( xSemaphore, pdFALSE ); +} diff --git a/20080212/Demo/MB91460_Softune/SRC/vectors.c b/20080212/Demo/MB91460_Softune/SRC/vectors.c new file mode 100644 index 000000000..c99e1490b --- /dev/null +++ b/20080212/Demo/MB91460_Softune/SRC/vectors.c @@ -0,0 +1,354 @@ +/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ +/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ +/* ELIGIBILITY FOR ANY PURPOSES. */ +/* (C) Fujitsu Microelectronics Europe GmbH */ +/*------------------------------------------------------------------------ + VECTORS.C + - Interrupt level (priority) setting + - Interrupt vector definition + + 31.04.05 1.00 UMa Initial Version + 08.11.05 1.01 MSt SWB Mondeb switch for ICR00 Register added + 27.02.06 1.02 UMa added comment in DefaultIRQHandler + 17.03.06 1.03 UMa comment out ICR01 + 28.07.06 1.04 UMa changed comment + 06.10.06 1.05 UMa changed DefaultIRQHandler +-------------------------------------------------------------------------*/ + +#include "mb91467d.h" +#include "watchdog.h" + +/*------------------------------------------------------------------------ + InitIrqLevels() + + This function pre-sets all interrupt control registers. It can be used + to set all interrupt priorities in static applications. If this file + contains assignments to dedicated resources, verify that the + appropriate controller is used. Not all devices of the MB91460 Series + offer all recources. + + NOTE: value 31 disables the interrupt and value 16 sets highest priority. +-------------------------------------------------------------------------*/ +void InitIrqLevels(void) +{ + /* ICRxx */ + /* Softune Workbench Monitor Debugger is using ext int0 for abort function */ + /* ICR00 = 31; *//* External Interrupt 0 */ + /* External Interrupt 1 */ + ICR01 = 31; /* External Interrupt 2 */ + /* External Interrupt 3 */ + ICR02 = 31; /* External Interrupt 4 */ + /* External Interrupt 5 */ + ICR03 = 31; /* External Interrupt 6 */ + /* External Interrupt 7 */ + ICR04 = 31; /* External Interrupt 8 */ + /* External Interrupt 9 */ + ICR05 = 31; /* External Interrupt 10 */ + /* External Interrupt 11 */ + ICR06 = 31; /* External Interrupt 12 */ + /* External Interrupt 13 */ + ICR07 = 31; /* External Interrupt 14 */ + /* External Interrupt 15 */ + ICR08 = 30; /* Reload Timer 0 */ + /* Reload Timer 1 */ + ICR09 = 31; /* Reload Timer 2 */ + /* Reload Timer 3 */ + ICR10 = 31; /* Reload Timer 4 */ + /* Reload Timer 5 */ + ICR11 = 31; /* Reload Timer 6 */ + /* Reload Timer 7 */ + ICR12 = 31; /* Free Run Timer 0 */ + /* Free Run Timer 1 */ + ICR13 = 31; /* Free Run Timer 2 */ + /* Free Run Timer 3 */ + ICR14 = 31; /* Free Run Timer 4 */ + /* Free Run Timer 5 */ + ICR15 = 31; /* Free Run Timer 6 */ + /* Free Run Timer 7 */ + ICR16 = 31; /* CAN 0 */ + /* CAN 1 */ + ICR17 = 31; /* CAN 2 */ + /* CAN 3 */ + ICR18 = 31; /* CAN 4 */ + /* CAN 5 */ + ICR19 = 31; /* USART (LIN) 0 RX */ + /* USART (LIN) 0 TX */ + ICR20 = 31; /* USART (LIN) 1 RX */ + /* USART (LIN) 1 TX */ + ICR21 = 30; /* USART (LIN) 2 RX */ + /* USART (LIN) 2 TX */ + ICR22 = 31; /* USART (LIN) 3 RX */ + /* USART (LIN) 3 TX */ + ICR23 = 30; /* System Reserved */ + /* Delayed Interrupt */ + ICR24 = 31; /* System Reserved */ + /* System Reserved */ + ICR25 = 31; /* USART (LIN, FIFO) 4 RX */ + /* USART (LIN, FIFO) 4 TX */ + ICR26 = 30; /* USART (LIN, FIFO) 5 RX */ + /* USART (LIN, FIFO) 5 TX */ + ICR27 = 31; /* USART (LIN, FIFO) 6 RX */ + /* USART (LIN, FIFO) 6 TX */ + ICR28 = 31; /* USART (LIN, FIFO) 7 RX */ + /* USART (LIN, FIFO) 7 TX */ + ICR29 = 31; /* I2C 0 / I2C 2 */ + /* I2C 1 / I2C 3 */ + ICR30 = 31; /* USART (LIN, FIFO) 8 RX */ + /* USART (LIN, FIFO) 8 TX */ + ICR31 = 31; /* USART (LIN, FIFO) 9 RX */ + /* USART (LIN, FIFO) 9 TX */ + ICR32 = 31; /* USART (LIN, FIFO) 10 RX */ + /* USART (LIN, FIFO) 10 TX */ + ICR33 = 31; /* USART (LIN, FIFO) 11 RX */ + /* USART (LIN, FIFO) 11 TX */ + ICR34 = 31; /* USART (LIN, FIFO) 12 RX */ + /* USART (LIN, FIFO) 12 TX */ + ICR35 = 31; /* USART (LIN, FIFO) 13 RX */ + /* USART (LIN, FIFO) 13 TX */ + ICR36 = 31; /* USART (LIN, FIFO) 14 RX */ + /* USART (LIN, FIFO) 14 TX */ + ICR37 = 31; /* USART (LIN, FIFO) 15 RX */ + /* USART (LIN, FIFO) 15 TX */ + ICR38 = 31; /* Input Capture 0 */ + /* Input Capture 1 */ + ICR39 = 31; /* Input Capture 2 */ + /* Input Capture 3 */ + ICR40 = 31; /* Input Capture 4 */ + /* Input Capture 5 */ + ICR41 = 31; /* Input Capture 6 */ + /* Input Capture 7 */ + ICR42 = 31; /* Output Compare 0 */ + /* Output Compare 1 */ + ICR43 = 31; /* Output Compare 2 */ + /* Output Compare 3 */ + ICR44 = 31; /* Output Compare 4 */ + /* Output Compare 5 */ + ICR45 = 31; /* Output Compare 6 */ + /* Output Compare 7 */ + ICR46 = 31; /* Sound Generator */ + /* Phase Frequ. Modulator */ + ICR47 = 31; /* System Reserved */ + /* System Reserved */ + ICR48 = 31; /* Prog. Pulse Gen. 0 */ + /* Prog. Pulse Gen. 1 */ + ICR49 = 31; /* Prog. Pulse Gen. 2 */ + /* Prog. Pulse Gen. 3 */ + ICR50 = 31; /* Prog. Pulse Gen. 4 */ + /* Prog. Pulse Gen. 5 */ + ICR51 = 31; /* Prog. Pulse Gen. 6 */ + /* Prog. Pulse Gen. 7 */ + ICR52 = 31; /* Prog. Pulse Gen. 8 */ + /* Prog. Pulse Gen. 9 */ + ICR53 = 31; /* Prog. Pulse Gen. 10 */ + /* Prog. Pulse Gen. 11 */ + ICR54 = 31; /* Prog. Pulse Gen. 12 */ + /* Prog. Pulse Gen. 13 */ + ICR55 = 31; /* Prog. Pulse Gen. 14 */ + /* Prog. Pulse Gen. 15 */ + ICR56 = 31; /* Up/Down Counter 0 */ + /* Up/Down Counter 1 */ + ICR57 = 31; /* Up/Down Counter 2 */ + /* Up/Down Counter 3 */ + ICR58 = 31; /* Real Time Clock */ + /* Calibration Unit */ + ICR59 = 31; /* A/D Converter 0 */ + /* - */ + ICR60 = 31; /* Alarm Comperator 0 */ + /* Alarm Comperator 1 */ + ICR61 = 31; /* Low Volage Detector */ + /* SMC Zero Point 0-5 */ + ICR62 = 31; /* Timebase Overflow */ + /* PLL Clock Gear */ + ICR63 = 31; /* DMA Controller */ + /* Main/Sub OSC stability wait */ +} + + +/*------------------------------------------------------------------------ + Prototypes + + Add your own prototypes here. Each vector definition needs is proto- + type. Either do it here or include a header file containing them. +-------------------------------------------------------------------------*/ +__interrupt void DefaultIRQHandler (void); +extern __interrupt void ReloadTimer0_IRQHandler ( void ); +extern __interrupt void vPortYield ( void ); +extern __interrupt void vPortYieldDelayed (void); + +extern __interrupt void UART2_RxISR(void); +extern __interrupt void UART2_TxISR(void); +extern __interrupt void UART5_RxISR(void); + +/*------------------------------------------------------------------------ + Vector definiton + + Use following statements to define vectors. All resource related + vectors are predefined. Remaining software interrupts can be added here + as well. +------------------------------------------------------------------------*/ +#pragma intvect 0xBFF8 0 /* (fixed) reset vector */ +#pragma intvect 0x06000000 1 /* (fixed) Mode Byte */ + +#pragma intvect DefaultIRQHandler 15 /* Non Maskable Interrupt */ +#pragma intvect DefaultIRQHandler 16 /* External Interrupt 0 */ +#pragma intvect DefaultIRQHandler 17 /* External Interrupt 1 */ + +#pragma intvect DefaultIRQHandler 18 /* External Interrupt 2 */ + +#pragma intvect DefaultIRQHandler 19 /* External Interrupt 3 */ +#pragma intvect DefaultIRQHandler 20 /* External Interrupt 4 */ +#pragma intvect DefaultIRQHandler 21 /* External Interrupt 5 */ +#pragma intvect DefaultIRQHandler 22 /* External Interrupt 6 */ +#pragma intvect DefaultIRQHandler 23 /* External Interrupt 7 */ +#pragma intvect DefaultIRQHandler 24 /* External Interrupt 8 */ +#pragma intvect DefaultIRQHandler 25 /* External Interrupt 9 */ +#pragma intvect DefaultIRQHandler 26 /* External Interrupt 10 */ +#pragma intvect DefaultIRQHandler 27 /* External Interrupt 11 */ +#pragma intvect DefaultIRQHandler 28 /* External Interrupt 12 */ +#pragma intvect DefaultIRQHandler 29 /* External Interrupt 13 */ +#pragma intvect DefaultIRQHandler 30 /* External Interrupt 14 */ +#pragma intvect DefaultIRQHandler 31 /* External Interrupt 15 */ + +#pragma intvect ReloadTimer0_IRQHandler 32 /* Reload Timer 0 */ + +#pragma intvect DefaultIRQHandler 33 /* Reload Timer 1 */ +#pragma intvect DefaultIRQHandler 34 /* Reload Timer 2 */ +#pragma intvect DefaultIRQHandler 35 /* Reload Timer 3 */ +#pragma intvect DefaultIRQHandler 36 /* Reload Timer 4 */ +#pragma intvect DefaultIRQHandler 37 /* Reload Timer 5 */ +#pragma intvect DefaultIRQHandler 38 /* Reload Timer 6 */ +#pragma intvect DefaultIRQHandler 39 /* Reload Timer 7 */ +#pragma intvect DefaultIRQHandler 40 /* Free Run Timer 0 */ +#pragma intvect DefaultIRQHandler 41 /* Free Run Timer 1 */ +#pragma intvect DefaultIRQHandler 42 /* Free Run Timer 2 */ +#pragma intvect DefaultIRQHandler 43 /* Free Run Timer 3 */ +#pragma intvect DefaultIRQHandler 44 /* Free Run Timer 4 */ +#pragma intvect DefaultIRQHandler 45 /* Free Run Timer 5 */ +#pragma intvect DefaultIRQHandler 46 /* Free Run Timer 6 */ +#pragma intvect DefaultIRQHandler 47 /* Free Run Timer 7 */ +#pragma intvect DefaultIRQHandler 48 /* CAN 0 */ +#pragma intvect DefaultIRQHandler 49 /* CAN 1 */ +#pragma intvect DefaultIRQHandler 50 /* CAN 2 */ +#pragma intvect DefaultIRQHandler 51 /* CAN 3 */ +#pragma intvect DefaultIRQHandler 52 /* CAN 4 */ +#pragma intvect DefaultIRQHandler 53 /* CAN 5 */ +#pragma intvect DefaultIRQHandler 54 /* USART (LIN) 0 RX */ +#pragma intvect DefaultIRQHandler 55 /* USART (LIN) 0 TX */ +#pragma intvect DefaultIRQHandler 56 /* USART (LIN) 1 RX */ +#pragma intvect DefaultIRQHandler 57 /* USART (LIN) 1 TX */ + +#pragma intvect UART2_RxISR 58 /* USART (LIN) 2 RX */ +#pragma intvect UART2_TxISR 59 /* USART (LIN) 2 TX */ + +#pragma intvect DefaultIRQHandler 60 /* USART (LIN) 3 RX */ +#pragma intvect DefaultIRQHandler 61 /* USART (LIN) 3 TX */ +#pragma intvect DefaultIRQHandler 62 /* System Reserved */ + +#pragma intvect vPortYieldDelayed 63 /* Delayed Interrupt */ + +#pragma intvect vPortYield 64 /* INT 64 */ + +#pragma intvect DefaultIRQHandler 65 /* System Reserved */ +#pragma intvect DefaultIRQHandler 66 /* USART (LIN, FIFO) 4 RX */ +#pragma intvect DefaultIRQHandler 67 /* USART (LIN, FIFO) 4 TX */ + +#pragma intvect UART5_RxISR 68 /* USART (LIN, FIFO) 5 RX */ + +#pragma intvect DefaultIRQHandler 69 /* USART (LIN, FIFO) 5 TX */ +#pragma intvect DefaultIRQHandler 70 /* USART (LIN, FIFO) 6 RX */ +#pragma intvect DefaultIRQHandler 71 /* USART (LIN, FIFO) 6 TX */ +#pragma intvect DefaultIRQHandler 72 /* USART (LIN, FIFO) 7 RX */ +#pragma intvect DefaultIRQHandler 73 /* USART (LIN, FIFO) 7 TX */ +#pragma intvect DefaultIRQHandler 74 /* I2C 0 / I2C 2 */ +#pragma intvect DefaultIRQHandler 75 /* I2C 1 / I2C 3 */ +#pragma intvect DefaultIRQHandler 76 /* USART (LIN, FIFO) 8 RX */ +#pragma intvect DefaultIRQHandler 77 /* USART (LIN, FIFO) 8 TX */ +#pragma intvect DefaultIRQHandler 78 /* USART (LIN, FIFO) 9 RX */ +#pragma intvect DefaultIRQHandler 79 /* USART (LIN, FIFO) 9 TX */ +#pragma intvect DefaultIRQHandler 80 /* USART (LIN, FIFO) 10 RX */ +#pragma intvect DefaultIRQHandler 81 /* USART (LIN, FIFO) 10 TX */ +#pragma intvect DefaultIRQHandler 82 /* USART (LIN, FIFO) 11 RX */ +#pragma intvect DefaultIRQHandler 83 /* USART (LIN, FIFO) 11 TX */ +#pragma intvect DefaultIRQHandler 84 /* USART (LIN, FIFO) 12 RX */ +#pragma intvect DefaultIRQHandler 85 /* USART (LIN, FIFO) 12 TX */ +#pragma intvect DefaultIRQHandler 86 /* USART (LIN, FIFO) 13 RX */ +#pragma intvect DefaultIRQHandler 87 /* USART (LIN, FIFO) 13 TX */ +#pragma intvect DefaultIRQHandler 88 /* USART (LIN, FIFO) 14 RX */ +#pragma intvect DefaultIRQHandler 89 /* USART (LIN, FIFO) 14 TX */ +#pragma intvect DefaultIRQHandler 90 /* USART (LIN, FIFO) 15 RX */ +#pragma intvect DefaultIRQHandler 91 /* USART (LIN, FIFO) 15 TX */ +#pragma intvect DefaultIRQHandler 92 /* Input Capture 0 */ +#pragma intvect DefaultIRQHandler 93 /* Input Capture 1 */ +#pragma intvect DefaultIRQHandler 94 /* Input Capture 2 */ +#pragma intvect DefaultIRQHandler 95 /* Input Capture 3 */ +#pragma intvect DefaultIRQHandler 96 /* Input Capture 4 */ +#pragma intvect DefaultIRQHandler 97 /* Input Capture 5 */ +#pragma intvect DefaultIRQHandler 98 /* Input Capture 6 */ +#pragma intvect DefaultIRQHandler 99 /* Input Capture 7 */ +#pragma intvect DefaultIRQHandler 100 /* Output Compare 0 */ +#pragma intvect DefaultIRQHandler 101 /* Output Compare 1 */ +#pragma intvect DefaultIRQHandler 102 /* Output Compare 2 */ +#pragma intvect DefaultIRQHandler 103 /* Output Compare 3 */ +#pragma intvect DefaultIRQHandler 104 /* Output Compare 4 */ +#pragma intvect DefaultIRQHandler 105 /* Output Compare 5 */ +#pragma intvect DefaultIRQHandler 106 /* Output Compare 6 */ +#pragma intvect DefaultIRQHandler 107 /* Output Compare 7 */ +#pragma intvect DefaultIRQHandler 108 /* Sound Generator */ +#pragma intvect DefaultIRQHandler 109 /* Phase Frequ. Modulator */ +#pragma intvect DefaultIRQHandler 110 /* System Reserved */ +#pragma intvect DefaultIRQHandler 111 /* System Reserved */ +#pragma intvect DefaultIRQHandler 112 /* Prog. Pulse Gen. 0 */ +#pragma intvect DefaultIRQHandler 113 /* Prog. Pulse Gen. 1 */ +#pragma intvect DefaultIRQHandler 114 /* Prog. Pulse Gen. 2 */ +#pragma intvect DefaultIRQHandler 115 /* Prog. Pulse Gen. 3 */ +#pragma intvect DefaultIRQHandler 116 /* Prog. Pulse Gen. 4 */ +#pragma intvect DefaultIRQHandler 117 /* Prog. Pulse Gen. 5 */ +#pragma intvect DefaultIRQHandler 118 /* Prog. Pulse Gen. 6 */ +#pragma intvect DefaultIRQHandler 119 /* Prog. Pulse Gen. 7 */ +#pragma intvect DefaultIRQHandler 120 /* Prog. Pulse Gen. 8 */ +#pragma intvect DefaultIRQHandler 121 /* Prog. Pulse Gen. 9 */ +#pragma intvect DefaultIRQHandler 122 /* Prog. Pulse Gen. 10 */ +#pragma intvect DefaultIRQHandler 123 /* Prog. Pulse Gen. 11 */ +#pragma intvect DefaultIRQHandler 124 /* Prog. Pulse Gen. 12 */ +#pragma intvect DefaultIRQHandler 125 /* Prog. Pulse Gen. 13 */ +#pragma intvect DefaultIRQHandler 126 /* Prog. Pulse Gen. 14 */ +#pragma intvect DefaultIRQHandler 127 /* Prog. Pulse Gen. 15 */ +#pragma intvect DefaultIRQHandler 128 /* Up/Down Counter 0 */ +#pragma intvect DefaultIRQHandler 129 /* Up/Down Counter 1 */ +#pragma intvect DefaultIRQHandler 130 /* Up/Down Counter 2 */ +#pragma intvect DefaultIRQHandler 131 /* Up/Down Counter 3 */ +#pragma intvect DefaultIRQHandler 132 /* Real Time Clock */ +#pragma intvect DefaultIRQHandler 133 /* Calibration Unit */ +#pragma intvect DefaultIRQHandler 134 /* A/D Converter 0 */ +#pragma intvect DefaultIRQHandler 135 /* - */ +#pragma intvect DefaultIRQHandler 136 /* Alarm Comperator 0 */ +#pragma intvect DefaultIRQHandler 137 /* Alarm Comperator 1 */ +#pragma intvect DefaultIRQHandler 138 /* Low Volage Detector */ +#pragma intvect DefaultIRQHandler 139 /* SMC Zero Point 0-5 */ +#pragma intvect DefaultIRQHandler 140 /* Timebase Overflow */ +#pragma intvect DefaultIRQHandler 141 /* PLL Clock Gear */ +#pragma intvect DefaultIRQHandler 142 /* DMA Controller */ +#pragma intvect DefaultIRQHandler 143 /* Main/Sub OSC stability wait */ +#pragma intvect 0xFFFFFFFF 144 /* Boot Sec. Vector (MB91V460A) */ + +/*------------------------------------------------------------------------ + DefaultIRQHandler() + + This function is a placeholder for all vector definitions. Either use + your own placeholder or add necessary code here. +-------------------------------------------------------------------------*/ +__interrupt +void DefaultIRQHandler (void) +{ + /* RB_SYNC; */ /* Synchronisation with R-Bus */ + /* May be required, if there is */ + /* no R-Bus access after the */ + /* reset of the interrupt flag */ + + __DI(); /* disable interrupts */ + while(1) + { + Kick_Watchdog(); /* feed hardware watchdog */ + } + /* halt system */ +} diff --git a/20080212/Demo/MB91460_Softune/SRC/vectors.h b/20080212/Demo/MB91460_Softune/SRC/vectors.h new file mode 100644 index 000000000..058e0002a --- /dev/null +++ b/20080212/Demo/MB91460_Softune/SRC/vectors.h @@ -0,0 +1,13 @@ +/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ +/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ +/* ELIGIBILITY FOR ANY PURPOSES. */ +/* (C) Fujitsu Microelectronics Europe GmbH */ +/*---------------------------------------------------------------------------- + VECTORS.h + + + 06.10.06 1.00 UMa Initial Version +-----------------------------------------------------------------------------*/ + + +void InitIrqLevels(void); diff --git a/20080212/Demo/MB91460_Softune/SRC/watchdog/watchdog.c b/20080212/Demo/MB91460_Softune/SRC/watchdog/watchdog.c new file mode 100644 index 000000000..e75d80bf8 --- /dev/null +++ b/20080212/Demo/MB91460_Softune/SRC/watchdog/watchdog.c @@ -0,0 +1,56 @@ +/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ +/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ +/* ELIGIBILITY FOR ANY PURPOSES. */ +/* (C) Fujitsu Microelectronics Europe GmbH */ +/*------------------------------------------------------------------------ + watchdog.c + - This file contains the function deefinition for hardware watchdog. +-------------------------------------------------------------------------*/ + +#include "mb91467d.h" +#include "FreeRTOS.h" +#include "task.h" +#include "watchdog.h" + +/*--------------------------------------------------------------------------- + * Setup Watchdog + *---------------------------------------------------------------------------*/ +#if WATCHDOG != WTC_NONE +void InitWatchdog(void) +{ + HWWDE_ED = WTC_PER_2_16; /* Set the watchdog period as 655.36 ms */ +} +#endif + +/*--------------------------------------------------------------------------- + * The below task clears the watchdog and blocks itself for WTC_CLR_PER ticks. + *---------------------------------------------------------------------------*/ +#if WATCHDOG == WTC_IN_TASK +static void prvWatchdogTask ( void *pvParameters ) +{ + const portTickType xFrequency = WTC_CLR_PER; + portTickType xLastWakeTime; + + /* Get currrent tick count */ + xLastWakeTime = xTaskGetTickCount(); + + for( ; ; ) + { + Kick_Watchdog(); + + /* Block the task for WTC_CLR_PER ticks (300 ms) at watchdog overflow + period of WTC_PER_2_16 CLKRC cycles (655.36 ms) */ + vTaskDelayUntil( &xLastWakeTime, xFrequency ); + } +} +#endif + +/*--------------------------------------------------------------------------- + * The below function creates hardware watchdog task. + *---------------------------------------------------------------------------*/ +#if WATCHDOG == WTC_IN_TASK +void vStartWatchdogTask( unsigned portSHORT uxPriority ) +{ + xTaskCreate( prvWatchdogTask , ( signed portCHAR * ) "KickWTC", portMINIMAL_STACK_SIZE, ( void * ) NULL, uxPriority, ( xTaskHandle * ) NULL ); +} +#endif diff --git a/20080212/Demo/MB91460_Softune/SRC/watchdog/watchdog.h b/20080212/Demo/MB91460_Softune/SRC/watchdog/watchdog.h new file mode 100644 index 000000000..9f95d24ff --- /dev/null +++ b/20080212/Demo/MB91460_Softune/SRC/watchdog/watchdog.h @@ -0,0 +1,46 @@ +/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ +/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ +/* ELIGIBILITY FOR ANY PURPOSES. */ +/* (C) Fujitsu Microelectronics Europe GmbH */ +/*------------------------------------------------------------------------ + watchdog.h + - This file contains the defines and function declaration for hardware watchdog. +-------------------------------------------------------------------------*/ +/* + * Clear watchdog defines + */ +#define WTC_NONE 0 /* Don't initialize and clear watchdog */ +#define WTC_IN_TASK 1 /* Clear Watchdog in dedicated task */ +#define WTC_IN_TICK 2 /* Clear Watchdog in TICK Hook */ +#define WTC_IN_IDLE 3 /* Clear Watchdog in Idle Hook */ + +#define WATCHDOG WTC_IN_TASK /* Clear Watchdog in vWatchdogTask() */ +/*------------------------------------------------------------------------*/ +/* + * Watchdog period defines + */ +#define WTC_PER_2_16 0 /* The watchdog period is 2^16 CLKRC cycles */ +#define WTC_PER_2_17 1 /* The watchdog period is 2^17 CLKRC cycles */ +#define WTC_PER_2_18 2 /* The watchdog period is 2^18 CLKRC cycles */ +#define WTC_PER_2_19 3 /* The watchdog period is 2^19 CLKRC cycles */ +/*------------------------------------------------------------------------*/ +/* + * After every WTC_CLR_PER ticks the watchdog would be cleared in the prvWatchdogTask(). + * This period needs to be chosen in accordance with the current CLKRC (100KHz or 2MHz) + * and the above setting WTC_PER_2_XX. + */ +#define WTC_CLR_PER 30 /* The watchdog clear period in RTOS ticks */ +/*------------------------------------------------------------------------*/ +/* + * Kick_watchdog Macro to clear watchdog + */ +#define Kick_Watchdog() \ + { HWWD = 0x10; \ + } +/*------------------------------------------------------------------------*/ +/* + * Watchdog function declarations + */ +void InitWatchdog (void); +void vStartWatchdogTask(unsigned portSHORT); + diff --git a/20080212/Demo/MB91460_Softune/STANDALONE/MB2198-01-COM1.sup b/20080212/Demo/MB91460_Softune/STANDALONE/MB2198-01-COM1.sup new file mode 100644 index 000000000..0745dbf14 --- /dev/null +++ b/20080212/Demo/MB91460_Softune/STANDALONE/MB2198-01-COM1.sup @@ -0,0 +1,227 @@ +[Information] +DebChangeFlag=0 +MCUChangeFlag=0 +[Version] +Version=1 +Level=1 +Revision=0 +[Debug Type] +Type=0 +Virtual CPU File=wv911e2.dll +Monitor Load=1 +Monitor Load Condition=Enable +Mode=FFFF +Monitor Combination Version=10100 +Mcu Name=MB91F467D +Monitor Select Count=1 +Monitor Connect Condition0=4 +Monitor Combination0=8/1/2:RealTimeMemory:,8/9/10:RAM Checker:C:48&1 +Core ID=0 +ChangeFlag=Disable +[Device] +Communication=RS COM1 115200 +ProductID=0 +Protocol=3 +[Target] +AutoLoad=Enable +Before Batch File=PRC\set_ROMS.prc +After Batch File=PRC\set_RESET.prc +Non AutoMap=Enable +Load DebInfo Only=Disable +Ondemand Load Condition=Disable +[Start] +Batch File= +[Window] +Flag=Enable +AssemblySize=458 4 878 244 +AssemblyState=0 +AssemblyFGColor=0 0 255 +RegisterSize=745 0 891 555 +RegisterState=0 +MemorySize=569 -3 836 574 +MemoryState=0 +Assembly Address=H'0000BFF8 +Memory Address=H'00000390 +Memory Mode=H'00000002 +Memory Ascii=H'00000001 +Memory SplitRow=0 +RMemory Address=H'00000000 +RMemory Mode=H'FFFFFFFF +RMemory Ascii=H'00000001 +RMemory SplitRow=0 +Trace ViewMode=FFFFFFFF +Command Max History=H'00000032 +Source Display Mode=Enable +Source Multi Mode=Enable +Source Ask Mode=Enable +Source Active Mode=Enable +Source PC Color=255 255 0 +Source Scope Color=255 0 255 +Source Back Trace=255 0 255 +Register Change Color=255 0 0 +Perfomance Mode=H'00000001 +Perfomance Scale=1 0 0.000000 0.000000 +RMemory Change Color=255 0 0 +RMemory Invalid Color=128 128 128 +CommandSize=3 299 423 470 +CommandState=0 +WatchSize=0 0 420 112 +WatchState=0 +Abs Sort Mode=H'00000001 +Register Select0=H'00000000 +Register Select1=H'00000001 +Register Select2=H'00000002 +Register Select3=H'00000003 +Register Select4=H'00000004 +Register Select5=H'00000005 +Register Select6=H'00000006 +Register Select7=H'00000007 +Register Select8=H'00000008 +Register Select9=H'00000009 +Register Select10=H'0000000A +Register Select11=H'0000000B +Register Select12=H'0000000C +Register Select13=H'0000000D +Register Select14=H'0000000E +Register Select15=H'0000000F +Register Select16=H'00000010 +Register Select17=H'00000011 +Register Select18=H'00000012 +Register Select19=H'00000013 +Register Select20=H'00000014 +Register Select21=H'00000015 +Register Select22=H'00000016 +Register Select23=H'00000017 +Register Select24=H'00000018 +Register Select25=H'00000019 +Register Select26=H'0000001A +Register Select27=H'0000001B +Register Select28=H'0000001C +Register Select29=H'0000001D +Register Select30=H'0000001E +Register Select31=H'0000001F +Register Select32=H'00000020 +Register Select33=H'00000021 +Register Select34=H'00000022 +Register Select35=H'00000027 +Layer0=2000,SRC\Start91460.asm +Layer1=1002, +Layer2=1007, +Source0Name=SRC\Start91460.asm +Source0Size=0 0 420 240 +Source0State=0 +Source0Line=698 +Source0Mode=2 +SymbolSize=0 0 420 128 +SymbolState=0 +Memory Line Byte=H'00000000 +Memory Change Color=255 0 0 +Memory Mark Color0=192 192 192 +Memory Mark Color1=192 0 0 +Memory Mark Color2=255 255 0 +Memory Mark Color3=0 255 0 +Memory Mark Color4=0 255 255 +Memory Mark Color5=0 128 192 +Memory Mark Color6=255 128 64 +Watch2Size=0 0 420 112 +Watch2State=0 +Watch3Size=0 0 420 112 +Watch3State=0 +[Path Environment] +Flag=Enable +Source= +[Map] +Flag=Enable +[Radix Environment] +Flag=Enable +Mode=10 +Source=1 +[Watch Environment] +Flag=Enable +Size=0 +Mode=0 +MBuf=0 +Check=1 +CSiz=100 +[Exec Environment] +Flag=Enable +GoIntMask=0 +StepUnit=3 +StepIntMask=0 +StepIntpCtrl=4 +GoTrcCtrl=2 +OnTheFlyBreakAdmit=1 +[Break Environment] +Flag=Enable +EventCodeMode=0 +EventDataMode=0 +[Emulation Environment] +Flag=Enable +Verify=0 +TRIG Input=0 +RunMode=3 +ICache Auto Control=0 +DefaultBreak=1 +TraceLostBreak=0 +AlignmentErrorBreak=0 +RFCR Auto Control=On +RFCR Execute=6810 +RFCR Break=F98 +Frequency=64 +AutoWait=3 +Limit Volt=6.6 2.0 +WatchDog=1 +Resource=1 +EventMode=0 +[Monitor Environment] +Flag=Enable +MemoryWindow=0 +WatchWindow=0 +ObjectWindow=0 +ElapseTime=3E8 +Unit=1 +Mode=0 +RealtimeMemoryWindow=0 +[Error] +Flag=Enable +GuiErrorOutput=2 +CommandErrorOutput=1 +BatchErrorOutput=1 +ErrorOutputLevel=0 +[Color] +Flag=Enable +[Tab Environment] +TabSize=8 +[Communication] +Send=4000 +Receive=4000 +[Trace Environment] +Trace Break=0 +Trace Status=0 +[CS Memory] +Flag=Disable +Area=0 +Write Enable=Disable +[IceMonitor Environment] +[FLASH Environment] +File Specified Area=00000001 00000000 00000000 +Environment Area=00000001 00000000 00000000 +MCU Number=MB91F464A +EnvSectorInfo1=0 00000000 00000000 +EnvSectorInfo2=0 00000000 00000000 +EnvSectorInfo3=0 00000000 00000000 +EnvSectorInfo4=0 00000000 00000000 +EnvSectorInfo5=0 00000000 00000000 +EnvSectorInfo6=0 00000000 00000000 +EnvSectorInfo7=0 00000000 00000000 +EnvSectorInfo8=0 00000000 00000000 +EnvSectorSelectMode=0 +FileSectorInfo1=0 00000000 00000000 +FileSectorInfo2=0 00000000 00000000 +FileSectorInfo3=0 00000000 00000000 +FileSectorInfo4=0 00000000 00000000 +FileSectorInfo5=0 00000000 00000000 +FileSectorInfo6=0 00000000 00000000 +FileSectorInfo7=0 00000000 00000000 +FileSectorInfo8=0 00000000 00000000 +FileSectorSelectMode=0 diff --git a/20080212/Demo/MB91460_Softune/STANDALONE/MB2198-01-LAN.sup b/20080212/Demo/MB91460_Softune/STANDALONE/MB2198-01-LAN.sup new file mode 100644 index 000000000..ee2b9864d --- /dev/null +++ b/20080212/Demo/MB91460_Softune/STANDALONE/MB2198-01-LAN.sup @@ -0,0 +1,226 @@ +[Information] +DebChangeFlag=0 +MCUChangeFlag=0 +[Version] +Version=1 +Level=1 +Revision=0 +[Debug Type] +Type=0 +Virtual CPU File=wv911e2.dll +Monitor Load=1 +Monitor Load Condition=Enable +Mode=FFFF +Monitor Combination Version=10100 +Mcu Name=MB91F467D +Monitor Select Count=1 +Monitor Connect Condition0=4 +Monitor Combination0=8/1/2:RealTimeMemory:,8/9/10:RAM Checker:C:48&1 +Core ID=0 +[Device] +Communication=LAN emu32_lan +ProductID=0 +Protocol=3 +[Target] +AutoLoad=Enable +Before Batch File=PRC\set_ROMS.prc +After Batch File=PRC\set_RESET.prc +Non AutoMap=Enable +Load DebInfo Only=Disable +Ondemand Load Condition=Disable +[Start] +Batch File= +[Window] +Flag=Enable +AssemblySize=458 4 878 244 +AssemblyState=0 +AssemblyFGColor=0 0 255 +RegisterSize=745 0 891 555 +RegisterState=0 +MemorySize=569 -3 836 574 +MemoryState=0 +Assembly Address=H'0000BFF8 +Memory Address=H'00000390 +Memory Mode=H'00000002 +Memory Ascii=H'00000001 +Memory SplitRow=0 +RMemory Address=H'00000000 +RMemory Mode=H'FFFFFFFF +RMemory Ascii=H'00000001 +RMemory SplitRow=0 +Trace ViewMode=FFFFFFFF +Command Max History=H'00000032 +Source Display Mode=Enable +Source Multi Mode=Enable +Source Ask Mode=Enable +Source Active Mode=Enable +Source PC Color=255 255 0 +Source Scope Color=255 0 255 +Source Back Trace=255 0 255 +Register Change Color=255 0 0 +Perfomance Mode=H'00000001 +Perfomance Scale=1 0 0.000000 0.000000 +RMemory Change Color=255 0 0 +RMemory Invalid Color=128 128 128 +CommandSize=3 299 423 470 +CommandState=0 +WatchSize=0 0 420 112 +WatchState=0 +Abs Sort Mode=H'00000001 +Register Select0=H'00000000 +Register Select1=H'00000001 +Register Select2=H'00000002 +Register Select3=H'00000003 +Register Select4=H'00000004 +Register Select5=H'00000005 +Register Select6=H'00000006 +Register Select7=H'00000007 +Register Select8=H'00000008 +Register Select9=H'00000009 +Register Select10=H'0000000A +Register Select11=H'0000000B +Register Select12=H'0000000C +Register Select13=H'0000000D +Register Select14=H'0000000E +Register Select15=H'0000000F +Register Select16=H'00000010 +Register Select17=H'00000011 +Register Select18=H'00000012 +Register Select19=H'00000013 +Register Select20=H'00000014 +Register Select21=H'00000015 +Register Select22=H'00000016 +Register Select23=H'00000017 +Register Select24=H'00000018 +Register Select25=H'00000019 +Register Select26=H'0000001A +Register Select27=H'0000001B +Register Select28=H'0000001C +Register Select29=H'0000001D +Register Select30=H'0000001E +Register Select31=H'0000001F +Register Select32=H'00000020 +Register Select33=H'00000021 +Register Select34=H'00000022 +Register Select35=H'00000027 +Layer0=2000,SRC\Start91460.asm +Layer1=1002, +Layer2=1007, +Source0Name=SRC\Start91460.asm +Source0Size=0 0 420 240 +Source0State=0 +Source0Line=698 +Source0Mode=2 +SymbolSize=0 0 420 128 +SymbolState=0 +Memory Line Byte=H'00000000 +Memory Change Color=255 0 0 +Memory Mark Color0=192 192 192 +Memory Mark Color1=192 0 0 +Memory Mark Color2=255 255 0 +Memory Mark Color3=0 255 0 +Memory Mark Color4=0 255 255 +Memory Mark Color5=0 128 192 +Memory Mark Color6=255 128 64 +Watch2Size=0 0 420 112 +Watch2State=0 +Watch3Size=0 0 420 112 +Watch3State=0 +[Path Environment] +Flag=Enable +Source= +[Map] +Flag=Enable +[Radix Environment] +Flag=Enable +Mode=10 +Source=1 +[Watch Environment] +Flag=Enable +Size=0 +Mode=0 +MBuf=0 +Check=1 +CSiz=100 +[Exec Environment] +Flag=Enable +GoIntMask=0 +StepUnit=3 +StepIntMask=0 +StepIntpCtrl=4 +GoTrcCtrl=2 +OnTheFlyBreakAdmit=1 +[Break Environment] +Flag=Enable +EventCodeMode=0 +EventDataMode=0 +[Emulation Environment] +Flag=Enable +Verify=0 +TRIG Input=0 +RunMode=3 +ICache Auto Control=0 +DefaultBreak=1 +TraceLostBreak=0 +AlignmentErrorBreak=0 +RFCR Auto Control=On +RFCR Execute=6780 +RFCR Break=F98 +Frequency=64 +AutoWait=3 +Limit Volt=6.6 2.0 +WatchDog=1 +Resource=1 +EventMode=0 +[Monitor Environment] +Flag=Enable +MemoryWindow=0 +WatchWindow=0 +ObjectWindow=0 +ElapseTime=3E8 +Unit=1 +Mode=0 +RealtimeMemoryWindow=0 +[Error] +Flag=Enable +GuiErrorOutput=2 +CommandErrorOutput=1 +BatchErrorOutput=1 +ErrorOutputLevel=0 +[Color] +Flag=Enable +[Tab Environment] +TabSize=8 +[Communication] +Send=60000 +Receive=32000 +[Trace Environment] +Trace Break=0 +Trace Status=0 +[CS Memory] +Flag=Disable +Area=0 +Write Enable=Disable +[IceMonitor Environment] +[FLASH Environment] +File Specified Area=00000001 00000000 00000000 +Environment Area=00000001 00000000 00000000 +MCU Number=MB91F464A +EnvSectorInfo1=0 00000000 00000000 +EnvSectorInfo2=0 00000000 00000000 +EnvSectorInfo3=0 00000000 00000000 +EnvSectorInfo4=0 00000000 00000000 +EnvSectorInfo5=0 00000000 00000000 +EnvSectorInfo6=0 00000000 00000000 +EnvSectorInfo7=0 00000000 00000000 +EnvSectorInfo8=0 00000000 00000000 +EnvSectorSelectMode=0 +FileSectorInfo1=0 00000000 00000000 +FileSectorInfo2=0 00000000 00000000 +FileSectorInfo3=0 00000000 00000000 +FileSectorInfo4=0 00000000 00000000 +FileSectorInfo5=0 00000000 00000000 +FileSectorInfo6=0 00000000 00000000 +FileSectorInfo7=0 00000000 00000000 +FileSectorInfo8=0 00000000 00000000 +FileSectorSelectMode=0 diff --git a/20080212/Demo/MB91460_Softune/STANDALONE/MB2198-01-USB.sup b/20080212/Demo/MB91460_Softune/STANDALONE/MB2198-01-USB.sup new file mode 100644 index 000000000..c8b74ad95 --- /dev/null +++ b/20080212/Demo/MB91460_Softune/STANDALONE/MB2198-01-USB.sup @@ -0,0 +1,327 @@ +[Information] +DebChangeFlag=0 +MCUChangeFlag=0 +[Version] +Version=1 +Level=1 +Revision=0 +[Debug Type] +Type=0 +Virtual CPU File=wv911e2.dll +Monitor Load=1 +Monitor Load Condition=Enable +Mode=FFFF +Monitor Combination Version=10100 +Mcu Name=MB91F467D +Monitor Select Count=1 +Monitor Connect Condition0=4 +Monitor Combination0=8/1/2:RealTimeMemory:,8/9/10:RAM Checker:C:48&1 +Core ID=0 +[Device] +Communication=USB +ProductID=2002 +Protocol=3 +[Target] +AutoLoad=Enable +Before Batch File=PRC\set_ROMS.prc +After Batch File=PRC\set_RESET.prc +Non AutoMap=Enable +Load DebInfo Only=Disable +Ondemand Load Condition=Disable +[Start] +Batch File= +[Window] +Flag=Enable +AssemblySize=0 435 256 580 +AssemblyState=2 +AssemblyFGColor=0 0 255 +RegisterSize=0 0 512 300 +RegisterState=0 +MemorySize=0 0 512 300 +MemoryState=0 +Assembly Address=H'0000BFF8 +Memory Address=H'00045858 +Memory Mode=H'00000003 +Memory Ascii=H'00000000 +Memory SplitRow=0 +RMemory Address=H'00000000 +RMemory Mode=H'FFFFFFFF +RMemory Ascii=H'00000001 +RMemory SplitRow=0 +Trace ViewMode=1 +Command Max History=H'00000032 +Source Display Mode=Enable +Source Multi Mode=Enable +Source Ask Mode=Enable +Source Active Mode=Enable +Source PC Color=255 255 0 +Source Scope Color=255 0 255 +Source Back Trace=255 0 255 +Register Change Color=255 0 0 +Perfomance Mode=H'00000001 +Perfomance Scale=1 0 0.000000 0.000000 +RMemory Change Color=255 0 0 +RMemory Invalid Color=128 128 128 +CommandSize=256 0 615 171 +CommandState=0 +WatchSize=512 0 1024 200 +WatchState=0 +Abs Sort Mode=H'00000001 +Register Select0=H'00000000 +Register Select1=H'00000001 +Register Select2=H'00000002 +Register Select3=H'00000003 +Register Select4=H'00000004 +Register Select5=H'00000005 +Register Select6=H'00000006 +Register Select7=H'00000007 +Register Select8=H'00000008 +Register Select9=H'00000009 +Register Select10=H'0000000A +Register Select11=H'0000000B +Register Select12=H'0000000C +Register Select13=H'0000000D +Register Select14=H'0000000E +Register Select15=H'0000000F +Register Select16=H'00000010 +Register Select17=H'00000011 +Register Select18=H'00000012 +Register Select19=H'00000013 +Register Select20=H'00000014 +Register Select21=H'00000015 +Register Select22=H'00000016 +Register Select23=H'00000017 +Register Select24=H'00000018 +Register Select25=H'00000019 +Register Select26=H'0000001A +Register Select27=H'0000001B +Register Select28=H'0000001C +Register Select29=H'0000001D +Register Select30=H'0000001E +Register Select31=H'0000001F +Register Select32=H'00000020 +Register Select33=H'00000021 +Register Select34=H'00000022 +Register Select35=H'00000027 +SymbolSize=0 0 450 475 +SymbolState=0 +Memory Line Byte=H'00000000 +Memory Change Color=255 0 0 +Memory Mark Color0=192 192 192 +Memory Mark Color1=192 0 0 +Memory Mark Color2=255 255 0 +Memory Mark Color3=0 255 0 +Memory Mark Color4=0 255 255 +Memory Mark Color5=0 128 192 +Memory Mark Color6=255 128 64 +Watch2Size=0 0 420 112 +Watch2State=0 +Watch3Size=0 0 420 112 +Watch3State=0 +TraceSize=492 0 738 145 +TraceState=0 +Layer0=1004, +Layer1=1005, +Layer2=1006, +Source0Name=SRC\Minimal\blocktim.c +Source0Size=512 400 1024 600 +Source0State=0 +Source0Line=195 +Source0Mode=2 +LocalSize=0 300 512 600 +LocalState=0 +Watch Variable0=[xTickCount],82030000,1,-1 -1 +Watch Variable1=[uxTopReadyPriority],80030000,1,-1 -1 +Watch Variable2=[tasks\uxCurrentNumberOfTasks],80030000,1,-1 -1 +Watch Variable3=[tasks\pxCurrentTCB],82040000,1,-1 -1 +Watch Variable4=[xTaskCheck],10010000,1,-1 -1 +Watch Variable5=[sCheckVariables],10010000,1,-1 -1 +Watch Variable6=[xSemaphoreParameters],10080000,1,-1 -1 +Watch Variable7=[sNextCheckVariable],92030000,1,-1 -1 +Command History0=cmd send +Command History1=cmd send=60000 +Command History2=cmd send +Command History3=cmd send=50000 +Command History4=cmd help +Command History5=cmd send +Command History6=cmd send +Command History7=cmd send +Command History8=cmd send +Command History9=cmd help +Command History10=cmd +Command History11=cmd send +Command History12=cmd send +Command History13=cmd send=60000 +Command History14=cmd send +Command History15=cmd send = 60000 +Command History16=cmd send +Command History17=send +Command History18=cmd send=50000 +Command History19=cmd send +Command History20=cmd send +Command History21=cmd send=60000 +Command History22=cmd send +Command History23=cmd send=500 +Command History24=cmd send +Command History25=load c:\CYGWIN\usr\cross\bin\test.mhx +Command History26=load c:\CYGWIN\usr\cross\bin\test.mhx +Command History27=load c:\CYGWIN\usr\cross\bin\test.mhx +Layer3=2000,SRC\Minimal\blocktim.c +Layer4=2000,SRC\Minimal\comtest.c +Layer5=2000,SRC\taskutility.c +Source1Name=SRC\MAIN.c +Source1Size=512 200 1024 400 +Source1State=0 +Source1Line=9F +Source1Mode=2 +Layer6=2000,SRC\FreeRTOSConfig.h +Layer7=2000,SRC\os\queue.c +Source2Name=SRC\FreeRTOSConfig.h +Source2Size=110 110 936 513 +Source2State=0 +Source2Line=22 +Source2Mode=2 +Source3Name=SRC\Minimal\comtest.c +Source3Size=154 154 984 561 +Source3State=0 +Source3Line=100 +Source3Mode=2 +Source4Name=SRC\Start91460.asm +Source4Size=198 198 1028 605 +Source4State=0 +Source4Line=627 +Source4Mode=2 +Source5Name=SRC\taskutility.c +Source5Size=0 0 830 407 +Source5State=0 +Source5Line=76 +Source5Mode=2 +Layer8=2000,SRC\Start91460.asm +Layer9=1007, +Layer10=2000,SRC\MAIN.c +Layer11=1002, +Watch Variable8=[xStart],10080000,1,-1 -1 +Watch Variable9=[xEnd],10080000,1,-1 -1 +Source6Name=SRC\os\queue.c +Source6Size=154 154 1006 564 +Source6State=0 +Source6Line=322 +Source6Mode=2 +Watch Variable10=[xPrimaryCycles],90030000,1,-1 -1 +Watch Variable11=[xSecondaryCycles],80030000,1,-1 -1 +Command History28=load c:\CYGWIN\usr\cross\bin\test.mhx +Command History29=load c:\CYGWIN\usr\cross\bin\test.mhx +Command History30=load c:\CYGWIN\usr\cross\bin\test.mhx +Command History31=load c:\CYGWIN\usr\cross\bin\test.mhx +Command History32=load c:\CYGWIN\usr\cross\bin\test.mhx +Command History33=load c:\CYGWIN\usr\cross\bin\test.mhx +[Path Environment] +Flag=Enable +Source= +[Map] +Flag=Enable +[Radix Environment] +Flag=Enable +Mode=10 +Source=1 +[Watch Environment] +Flag=Enable +Size=0 +Mode=0 +MBuf=0 +Check=1 +CSiz=100 +[Exec Environment] +Flag=Enable +GoIntMask=0 +StepUnit=3 +StepIntMask=0 +StepIntpCtrl=4 +GoTrcCtrl=2 +OnTheFlyBreakAdmit=1 +[Break Environment] +Flag=Enable +EventCodeMode=0 +EventDataMode=0 +Code0=00040302 1 1 1 0 0 MAIN.c$162 +Debug File=C:\Fujitsu\FreeRTOS\FreeRTOS_Port_FR\91467d_FreeRTOS\STANDALONE\ABS\91467d_FreeRTOS.abs +[Emulation Environment] +Flag=Enable +Verify=0 +TRIG Input=0 +RunMode=3 +ICache Auto Control=0 +DefaultBreak=1 +TraceLostBreak=0 +AlignmentErrorBreak=1 +RFCR Auto Control=On +RFCR Execute=5B50 +RFCR Break=F98 +Frequency=50 +AutoWait=3 +Limit Volt=6.6 2.0 +WatchDog=0 +Resource=1 +EventMode=0 +[Monitor Environment] +Flag=Enable +MemoryWindow=1 +WatchWindow=1 +ObjectWindow=0 +ElapseTime=3E8 +Unit=1 +Mode=0 +RealtimeMemoryWindow=0 +[Error] +Flag=Enable +GuiErrorOutput=2 +CommandErrorOutput=1 +BatchErrorOutput=1 +ErrorOutputLevel=0 +[Color] +Flag=Enable +[Tab Environment] +TabSize=8 +[Communication] +Send=60000 +Receive=32000 +[Trace Environment] +Trace Break=0 +Trace Status=0 +[CS Memory] +Flag=Disable +Area=0 +Write Enable=Disable +[IceMonitor Environment] +Mode=FFFFFFFF +[FLASH Environment] +File Specified Area=00000001 00000000 00000000 +Environment Area=00000001 00000000 00000000 +MCU Number=MB91F467D +EnvSectorInfo1=0 00000000 00000000 +EnvSectorInfo2=0 00000000 00000000 +EnvSectorInfo3=0 00000000 00000000 +EnvSectorInfo4=0 00000000 00000000 +EnvSectorInfo5=0 00000000 00000000 +EnvSectorInfo6=0 00000000 00000000 +EnvSectorInfo7=0 00000000 00000000 +EnvSectorInfo8=0 00000000 00000000 +EnvSectorSelectMode=0 +FileSectorInfo1=0 00000000 00000000 +FileSectorInfo2=0 00000000 00000000 +FileSectorInfo3=0 00000000 00000000 +FileSectorInfo4=0 00000000 00000000 +FileSectorInfo5=0 00000000 00000000 +FileSectorInfo6=0 00000000 00000000 +FileSectorInfo7=0 00000000 00000000 +FileSectorInfo8=0 00000000 00000000 +FileSectorSelectMode=0 +[Book Mark] +BookMarkMem0=SystemStack,,6,H'00028000,H'000280FB +BookMarkMem1=H'00028228,,1,H'00028228,H'0002837B +BookMarkMem2=H'0002837C,,3,H'0002837C,H'000284CF +BookMarkMem3=H'000284D0,,1,H'000284D0,H'00028623 +BookMarkMem4=(tasks\pxCurrentTCB)->pxTopOfStack,,6,H'00028624,H'00028627 +BookMarkMem5=*((tasks\pxCurrentTCB)->pxTopOfStack),,2,H'00028838,H'0002883B +BookMarkMem6=\pxCurrentTCB,,7,H'0002892C,H'0002892F +BookMarkMem7=UserStack,,4,H'0002894C,H'00028D47 diff --git a/20080212/Demo/MB91460_Softune/STANDALONE/Mondeb_57K6_com1.sup b/20080212/Demo/MB91460_Softune/STANDALONE/Mondeb_57K6_com1.sup new file mode 100644 index 000000000..9af36c8af --- /dev/null +++ b/20080212/Demo/MB91460_Softune/STANDALONE/Mondeb_57K6_com1.sup @@ -0,0 +1,214 @@ +[Information] +DebChangeFlag=0 +MCUChangeFlag=0 +[Version] +Version=1 +Level=1 +Revision=0 +[Debug Type] +Type=2 +Virtual CPU File=wv911r1.dll +Monitor Load=0 +Monitor Load Condition=Disable +[Device] +Communication=RS COM1 57600 +ProductID=0 +Protocol=0 +[Target] +AutoLoad=Enable +Before Batch File= +After Batch File=PRC\set_MONITOR.prc +Non AutoMap=Enable +Load DebInfo Only=Disable +Ondemand Load Condition=Disable +[Start] +Batch File= +[Window] +Flag=Enable +AssemblySize=325 90 1151 598 +AssemblyState=0 +AssemblyFGColor=0 0 255 +CommandSize=132 138 958 562 +CommandState=0 +Assembly Address=H'00042412 +Memory Address=H'0002F038 +Memory Mode=H'00000003 +Memory Ascii=H'00000001 +Memory SplitRow=0 +RMemory Address=H'00000000 +RMemory Mode=H'FFFFFFFF +RMemory Ascii=H'00000001 +RMemory SplitRow=0 +Trace ViewMode=FFFFFFFF +Command Max History=H'00000032 +Source Display Mode=Enable +Source Multi Mode=Enable +Source Ask Mode=Enable +Source Active Mode=Enable +Source PC Color=255 255 0 +Source Scope Color=255 0 255 +Source Back Trace=255 0 255 +Register Change Color=255 0 0 +Abs Sort Mode=H'00000001 +Perfomance Mode=H'00000001 +Perfomance Scale=1 0 0.000000 0.000000 +RMemory Change Color=255 0 0 +RMemory Invalid Color=128 128 128 +Command History0=step +Command History1=go ,main +RegisterSize=218 423 1044 847 +RegisterState=0 +Register Select0=H'00000000 +Register Select1=H'00000001 +Register Select2=H'00000002 +Register Select3=H'00000003 +Register Select4=H'00000004 +Register Select5=H'00000005 +Register Select6=H'00000006 +Register Select7=H'00000007 +Register Select8=H'00000008 +Register Select9=H'00000009 +Register Select10=H'0000000A +Register Select11=H'0000000B +Register Select12=H'0000000C +Register Select13=H'0000000D +Register Select14=H'0000000E +Register Select15=H'0000000F +Register Select16=H'00000010 +Register Select17=H'00000011 +Register Select18=H'00000012 +Register Select19=H'00000013 +Register Select20=H'00000014 +Register Select21=H'00000015 +Register Select22=H'00000016 +Register Select23=H'00000017 +Register Select24=H'00000018 +Register Select25=H'00000019 +Register Select26=H'0000001A +Register Select27=H'0000001B +Register Select28=H'0000001C +Register Select29=H'0000001D +Register Select30=H'0000001E +Register Select31=H'0000001F +Register Select32=H'00000020 +Register Select33=H'00000021 +Register Select34=H'00000022 +Register Select35=H'00000027 +MemorySize=66 69 892 493 +MemoryState=0 +Layer0=1005, +Layer1=1004, +Layer2=2000,..\..\Source\tasks.c +Source0Name=..\..\Source\tasks.c +Source0Size=204 103 1030 527 +Source0State=0 +Source0Line=46C +Source0Mode=2 +Source1Name=..\..\Source\portable\Softune\MB91460\port.c +Source1Size=310 3 1136 427 +Source1State=0 +Source1Line=DB +Source1Mode=2 +SymbolSize=0 0 0 0 +SymbolState=0 +Memory Line Byte=H'00000000 +Memory Change Color=255 0 0 +Memory Mark Color0=192 192 192 +Memory Mark Color1=192 0 0 +Memory Mark Color2=255 255 0 +Memory Mark Color3=0 255 0 +Memory Mark Color4=0 255 255 +Memory Mark Color5=0 128 192 +Memory Mark Color6=255 128 64 +Layer3=1006, +Layer4=1003, +Layer5=2000,..\..\Source\portable\Softune\MB91460\port.c +Layer6=2000,SRC\watchdog\watchdog.c +Layer7=1002, +LocalSize=44 46 870 470 +LocalState=0 +WatchSize=0 0 826 424 +WatchState=0 +Source2Name=SRC\main.c +Source2Size=66 69 1074 448 +Source2State=0 +Source2Line=124 +Source2Mode=2 +Source3Name=SRC\watchdog\watchdog.c +Source3Size=44 46 998 421 +Source3State=0 +Source3Line=1C +Source3Mode=2 +Layer8=2000,SRC\Start91460.asm +Watch Variable0=[ulCriticalNesting],82030000,1,-1 -1 +Layer9=1007, +Layer10=2000,SRC\main.c +Source4Name=SRC\Start91460.asm +Source4Size=198 207 1086 679 +Source4State=0 +Source4Line=913 +Source4Mode=2 +Layer11=2000,SRC\vectors.c +Source5Name=SRC\vectors.c +Source5Size=22 23 859 518 +Source5State=2 +Source5Line=49 +Source5Mode=2 +[Path Environment] +Flag=Enable +Source= +[Map] +Flag=Enable +[Radix Environment] +Flag=Enable +Mode=10 +Source=1 +[Watch Environment] +Flag=Enable +Size=0 +Mode=0 +MBuf=0 +Check=1 +CSiz=100 +[Exec Environment] +Flag=Enable +GoIntMask=0 +StepUnit=3 +StepIntMask=0 +StepIntpCtrl=4 +GoTrcCtrl=2 +OnTheFlyBreakAdmit=0 +[Break Environment] +Flag=Enable +[Emulation Environment] +Flag=Disable +[Monitor Environment] +Flag=Enable +MemoryWindow=0 +WatchWindow=0 +ObjectWindow=0 +ElapseTime=3E8 +Unit=1 +Mode=0 +RealtimeMemoryWindow=0 +[Error] +Flag=Enable +GuiErrorOutput=2 +CommandErrorOutput=1 +BatchErrorOutput=1 +ErrorOutputLevel=0 +[Color] +Flag=Enable +[Tab Environment] +TabSize=8 +[Communication] +Send=250 +Receive=250 +[CS Memory] +Flag=Disable +Area=0 +Write Enable=Disable +[FLASH Environment] +File Specified Area=00000001 00000000 00000000 +Environment Area=00000001 00000000 00000000 +MCU Number=MB91F467D diff --git a/20080212/Demo/MB91460_Softune/STANDALONE/Mondeb_57K6_com2.sup b/20080212/Demo/MB91460_Softune/STANDALONE/Mondeb_57K6_com2.sup new file mode 100644 index 000000000..c989e99ab --- /dev/null +++ b/20080212/Demo/MB91460_Softune/STANDALONE/Mondeb_57K6_com2.sup @@ -0,0 +1,197 @@ +[Information] +DebChangeFlag=0 +MCUChangeFlag=0 +[Version] +Version=1 +Level=1 +Revision=0 +[Debug Type] +Type=2 +Virtual CPU File=wv911r1.dll +Monitor Load=0 +Monitor Load Condition=Disable +[Device] +Communication=RS COM2 57600 +ProductID=0 +Protocol=0 +[Target] +AutoLoad=Enable +Before Batch File= +After Batch File=PRC\set_MONITOR.prc +Non AutoMap=Enable +Load DebInfo Only=Disable +Ondemand Load Condition=Disable +[Start] +Batch File= +[Window] +Flag=Enable +AssemblySize=0 0 420 240 +AssemblyState=0 +AssemblyFGColor=0 0 255 +CommandSize=0 0 420 320 +CommandState=0 +Layer0=2000,..\Common\Minimal\flop.c +Layer1=2000,..\Common\Minimal\dynamic.c +Layer2=2000,..\Common\Minimal\integer.c +Layer3=2000,..\Common\Minimal\semtest.c +Layer4=2000,..\..\Source\portable\Softune\MB91460\port.c +Assembly Address=H'00040DFC +Memory Address=H'00000000 +Memory Mode=H'FFFFFFFF +Memory Ascii=H'00000001 +Memory Line Byte=H'00000000 +Memory SplitRow=0 +RMemory Address=H'00000000 +RMemory Mode=H'FFFFFFFF +RMemory Ascii=H'00000001 +RMemory SplitRow=0 +Trace ViewMode=FFFFFFFF +Command Max History=H'00000032 +Source Display Mode=Enable +Source Multi Mode=Enable +Source Ask Mode=Enable +Source Active Mode=Enable +Source PC Color=255 255 0 +Source Scope Color=255 0 255 +Source Back Trace=255 0 255 +Register Change Color=255 0 0 +Memory Change Color=255 0 0 +Memory Mark Color0=192 192 192 +Memory Mark Color1=192 0 0 +Memory Mark Color2=255 255 0 +Memory Mark Color3=0 255 0 +Memory Mark Color4=0 255 255 +Memory Mark Color5=0 128 192 +Memory Mark Color6=255 128 64 +Abs Sort Mode=H'00000001 +Source0Name=SRC\Start91460.asm +Source0Size=0 0 715 313 +Source0State=0 +Source0Line=916 +Source0Mode=2 +Source1Name=SRC\MAIN.c +Source1Size=88 88 825 404 +Source1State=0 +Source1Line=9C +Source1Mode=2 +Source2Name=..\Common\Minimal\flop.c +Source2Size=132 132 873 452 +Source2State=0 +Source2Line=115 +Source2Mode=1 +Perfomance Mode=H'00000001 +Perfomance Scale=1 0 0.000000 0.000000 +RMemory Change Color=255 0 0 +RMemory Invalid Color=128 128 128 +Layer5=2000,..\..\Source\portable\MemMang\heap_1.c +Layer6=2000,..\..\Source\portable\MemMang\heap_3.c +Layer7=2000,..\..\Source\tasks.c +Source3Name=..\Common\Minimal\integer.c +Source3Size=0 0 737 316 +Source3State=0 +Source3Line=7C +Source3Mode=2 +Source4Name=..\..\Source\tasks.c +Source4Size=22 22 759 338 +Source4State=0 +Source4Line=46F +Source4Mode=2 +Source5Name=..\Common\Minimal\dynamic.c +Source5Size=44 44 781 360 +Source5State=0 +Source5Line=159 +Source5Mode=2 +Layer8=2000,..\..\Source\portable\MemMang\heap_2.c +Source6Name=..\Common\Minimal\semtest.c +Source6Size=110 110 976 426 +Source6State=0 +Source6Line=8B +Source6Mode=2 +Layer9=1002, +Source7Name=..\..\Source\portable\Softune\MB91460\port.c +Source7Size=132 132 998 448 +Source7State=0 +Source7Line=BE +Source7Mode=2 +Layer10=2000,SRC\Start91460.asm +Layer11=1007, +Layer12=2000,SRC\MAIN.c +Layer13=2000,..\..\Source\queue.c +Source8Name=..\..\Source\portable\MemMang\heap_2.c +Source8Size=66 66 936 386 +Source8State=0 +Source8Line=3F +Source8Mode=2 +Source9Name=..\..\Source\portable\MemMang\heap_1.c +Source9Size=88 88 958 408 +Source9State=0 +Source9Line=31 +Source9Mode=2 +Source10Name=..\..\Source\portable\MemMang\heap_3.c +Source10Size=110 110 980 411 +Source10State=0 +Source10Line=31 +Source10Mode=2 +Source11Name=..\..\Source\queue.c +Source11Size=0 0 866 297 +Source11State=0 +Source11Line=328 +Source11Mode=2 +[Path Environment] +Flag=Enable +Source= +[Map] +Flag=Enable +[Radix Environment] +Flag=Enable +Mode=10 +Source=1 +[Watch Environment] +Flag=Enable +Size=0 +Mode=0 +MBuf=0 +Check=1 +CSiz=100 +[Exec Environment] +Flag=Enable +GoIntMask=0 +StepUnit=3 +StepIntMask=0 +StepIntpCtrl=4 +GoTrcCtrl=2 +OnTheFlyBreakAdmit=0 +[Break Environment] +Flag=Enable +Code0=00042682 1 0 1 MAIN.c$160 +Code1=0004268A 1 0 1 MAIN.c$162 +Debug File=E:\FreeRTOS\FR\91467d_FreeRTOS\91467d_FreeRTOS\Demo\MB91460_Softune\STANDALONE\ABS\91467d_FreeRTOS.abs +Code2=00042690 1 0 1 MAIN.c$167 +[Emulation Environment] +Flag=Disable +[Monitor Environment] +Flag=Enable +MemoryWindow=0 +WatchWindow=0 +ObjectWindow=0 +ElapseTime=3E8 +Unit=1 +Mode=0 +RealtimeMemoryWindow=0 +[Error] +Flag=Enable +GuiErrorOutput=2 +CommandErrorOutput=1 +BatchErrorOutput=1 +ErrorOutputLevel=0 +[Color] +Flag=Enable +[Tab Environment] +TabSize=8 +[Communication] +Send=250 +Receive=250 +[CS Memory] +Flag=Disable +Area=0 +Write Enable=Disable diff --git a/20080212/Demo/MB91460_Softune/STANDALONE/Simulator.sup b/20080212/Demo/MB91460_Softune/STANDALONE/Simulator.sup new file mode 100644 index 000000000..f4196e591 --- /dev/null +++ b/20080212/Demo/MB91460_Softune/STANDALONE/Simulator.sup @@ -0,0 +1,291 @@ +[Information] +DebChangeFlag=0 +MCUChangeFlag=0 +[Version] +Version=1 +Level=1 +Revision=0 +[Debug Type] +Type=1 +Virtual CPU File=wv911s1.dll +Monitor Load=0 +Monitor Load Condition=Disable +[Device] +Communication=LAN +ProductID=0 +Protocol=0 +[Target] +AutoLoad=Enable +Before Batch File= +After Batch File=C:PRC\set_SIMULATE.prc +Non AutoMap=Disable +Load DebInfo Only=Disable +Ondemand Load Condition=Disable +[Start] +Batch File= +[Window] +Flag=Enable +Assembly Address=H'000F4000 +Memory Address=H'00005742 +Memory Mode=H'00000001 +Memory Ascii=H'00000001 +Memory SplitRow=0 +RMemory Address=H'00000000 +RMemory Mode=H'FFFFFFFF +RMemory Ascii=H'00000001 +RMemory SplitRow=0 +Trace ViewMode=FFFFFFFF +Command Max History=H'00000032 +Source Display Mode=Enable +Source Multi Mode=Enable +Source Ask Mode=Enable +Source Active Mode=Enable +Source PC Color=255 255 0 +Source Scope Color=255 0 255 +Source Back Trace=255 0 255 +Register Change Color=255 0 0 +Perfomance Mode=H'00000001 +Perfomance Scale=1 0 0.000000 0.000000 +RMemory Change Color=255 0 0 +RMemory Invalid Color=128 128 128 +RegisterSize=703 3 997 211 +RegisterState=0 +Register Select0=H'00000000 +Register Select1=H'00000001 +Register Select2=H'00000002 +Register Select3=H'00000003 +Register Select4=H'00000004 +Register Select5=H'00000005 +Register Select6=H'00000006 +Register Select7=H'00000007 +Register Select8=H'00000008 +Register Select9=H'00000009 +Register Select10=H'0000000A +Register Select11=H'0000000B +Register Select12=H'0000000C +Register Select13=H'0000000D +Register Select14=H'0000000E +Register Select15=H'0000000F +Register Select16=H'00000010 +Register Select17=H'00000011 +Register Select18=H'00000012 +Register Select19=H'00000013 +Register Select20=H'00000014 +Register Select21=H'00000015 +Register Select22=H'00000016 +Register Select23=H'00000017 +Register Select24=H'00000018 +Register Select25=H'00000019 +Register Select26=H'0000001A +Register Select27=H'0000001B +Register Select28=H'0000001C +Register Select29=H'0000001D +Register Select30=H'0000001E +Register Select31=H'0000001F +Register Select32=H'00000020 +Register Select33=H'00000021 +Register Select34=H'00000022 +Register Select35=H'00000027 +MemorySize=521 35 939 404 +MemoryState=0 +AssemblySize=0 0 420 240 +AssemblyState=0 +AssemblyFGColor=0 0 255 +WatchSize=51 443 471 555 +WatchState=0 +CommandSize=-2 380 418 551 +CommandState=0 +Command History0=load c:\CYGWIN\usr\cross\bin\test.mhx +Command History1=load c:\CYGWIN\usr\cross\bin\test.mhx +Command History2=load c:\CYGWIN\usr\cross\bin\test.mhx +Command History3=load c:\CYGWIN\usr\cross\bin\test.mhx +Command History4=load c:\CYGWIN\usr\cross\bin\test.mhx +Command History5=load c:\CYGWIN\usr\cross\bin\test.mhx +Command History6=load c:\CYGWIN\usr\cross\bin\test.mhx +Abs Sort Mode=H'00000001 +SymbolSize=0 0 0 0 +SymbolState=0 +Command History7=load c:\CYGWIN\usr\cross\bin\test.mhx +Memory Line Byte=H'00000000 +Memory Change Color=255 0 0 +Memory Mark Color0=192 192 192 +Memory Mark Color1=192 0 0 +Memory Mark Color2=255 255 0 +Memory Mark Color3=0 255 0 +Memory Mark Color4=0 255 255 +Memory Mark Color5=0 128 192 +Memory Mark Color6=255 128 64 +Command History8=load c:\CYGWIN\usr\cross\bin\test.mhx +Command History9=load c:\CYGWIN\usr\cross\bin\test.mhx +Command History10=load c:\CYGWIN\usr\cross\bin\test.mhx +Command History11=load c:\CYGWIN\usr\cross\bin\test.mhx +Command History12=load c:\CYGWIN\usr\cross\bin\test.mhx +Command History13=load c:\CYGWIN\usr\cross\bin\test.mhx +Command History14=load c:\CYGWIN\usr\cross\bin\test.mhx +Command History15=load c:\CYGWIN\usr\cross\bin\test.mhx +Layer0=1004, +TraceSize=0 0 0 0 +TraceState=0 +Watch2Size=0 0 420 112 +Watch2State=0 +Layer1=1002, +Source0Name=SRC\Start91460.asm +Source0Size=0 0 868 429 +Source0State=0 +Source0Line=627 +Source0Mode=1 +Layer2=2000,SRC\FreeRTOS.h +Layer3=2000,SRC\tasks.c +Layer4=2000,SRC\portmacro.h +Layer5=1007, +Source1Name=SRC\MAIN.c +Source1Size=132 132 1000 579 +Source1State=2 +Source1Line=E1 +Source1Mode=1 +Source2Name=SRC\tasks.c +Source2Size=154 154 1022 601 +Source2State=0 +Source2Line=59E +Source2Mode=1 +Source3Name=SRC\port.c +Source3Size=176 176 1044 623 +Source3State=0 +Source3Line=EC +Source3Mode=2 +Layer6=2000,SRC\Start91460.asm +Command History16=load c:\CYGWIN\usr\cross\bin\test.mhx +Command History17=load c:\CYGWIN\usr\cross\bin\test.mhx +Command History18=load c:\CYGWIN\usr\cross\bin\test.mhx +Command History19=load c:\CYGWIN\usr\cross\bin\test.out +Command History20=load c:\CYGWIN\usr\cross\bin\test.out +Command History21=load c:\CYGWIN\usr\cross\bin\test.out +Command History22=load c:\c:\CYGWIN\usr\cross\bin\test.out +Command History23=load +Command History24=open +Command History25=go ,main +Command History26=go noClockStartup,Start91460\smd_cs +Command History27=go ,noClockStartup +Command History28=go ,noClockStartup +Command History29=go noClockStartup,Start91460\smd_cs +Command History30=go ,noClockStartup +Command History31=go noClockStartup,Start91460\smd_cs +Command History32=go ,Start91460\smd_tbr +Command History33=FLASHREADT +Command History34=SET MEMORY/WORD 0xFFFFC=__start +Command History35=SET MEMORY/WORD 0xFFFFC=__start +Command History36=SET MEMORY/WORD 0xFFFFC=__start +Command History37=_start +Command History38=_start +Command History39=_start +Command History40=SET MEMORY/WORD 0xFFFFC=_start +Layer7=2000,SRC\port.c +Layer8=2000,SRC\FreeRTOSConfig.h +Layer9=2000,SRC\MAIN.c +Source4Name=SRC\portmacro.h +Source4Size=176 176 969 598 +Source4State=0 +Source4Line=25 +Source4Mode=2 +Source5Name=SRC\FreeRTOS.h +Source5Size=0 0 793 422 +Source5State=0 +Source5Line=52 +Source5Mode=2 +Source6Name=SRC\FreeRTOSConfig.h +Source6Size=22 22 815 444 +Source6State=0 +Source6Line=28 +Source6Mode=2 +[Path Environment] +Flag=Enable +Source= +[Map] +Flag=Enable +Area0=00000000 00020401 3 0 0 +Area2=00028000 0002C9DB 3 0 0 +Area4=0002D000 0002D411 3 0 0 +Area6=00030000 0003FFFF 7 0 0 +Area7=00040000 00044E91 5 0 0 +Area9=000F4000 000F42A7 5 0 0 +Area11=000F5000 000F549D 5 0 0 +Area13=000FFC00 000FFFFF 5 0 0 +Area15=00148000 0014800F 5 0 0 +[Radix Environment] +Flag=Enable +Mode=10 +Source=1 +[Watch Environment] +Flag=Enable +Size=0 +Mode=0 +MBuf=0 +Check=1 +CSiz=100 +[Exec Environment] +Flag=Enable +GoIntMask=0 +StepUnit=3 +StepIntMask=0 +StepIntpCtrl=4 +GoTrcCtrl=2 +OnTheFlyBreakAdmit=0 +[Break Environment] +Flag=Enable +Code0=000413F8 1 0 1 tasks.c$628 +Debug File=C:\Fujitsu\FreeRTOS\FreeRTOS Port FR\91467d_FreeRTOS-v11\STANDALONE\ABS\91467d_FreeRTOS.abs +[Emulation Environment] +Flag=Disable +[Monitor Environment] +Flag=Enable +MemoryWindow=0 +WatchWindow=0 +ObjectWindow=0 +ElapseTime=3E8 +Unit=1 +Mode=0 +RealtimeMemoryWindow=0 +[Error] +Flag=Enable +GuiErrorOutput=2 +CommandErrorOutput=1 +BatchErrorOutput=1 +ErrorOutputLevel=0 +[Color] +Flag=Enable +[Tab Environment] +TabSize=8 +[Communication] +Send=1000 +Receive=64 +[Trace Environment] +Trace Break=0 +Trace Status=1 +[CS Memory] +Flag=Disable +Area=0 +Write Enable=Disable +[FLASH Environment] +File Specified Area=00000001 00000000 00000000 +Environment Area=00000001 00000000 00000000 +MCU Number=MB91F467D +EnvSectorInfo1=0 00000000 00000000 +EnvSectorInfo2=0 00000000 00000000 +EnvSectorInfo3=0 00000000 00000000 +EnvSectorInfo4=0 00000000 00000000 +EnvSectorInfo5=0 00000000 00000000 +EnvSectorInfo6=0 00000000 00000000 +EnvSectorInfo7=0 00000000 00000000 +EnvSectorInfo8=0 00000000 00000000 +EnvSectorSelectMode=0 +FileSectorInfo1=0 00000000 00000000 +FileSectorInfo2=0 00000000 00000000 +FileSectorInfo3=0 00000000 00000000 +FileSectorInfo4=0 00000000 00000000 +FileSectorInfo5=0 00000000 00000000 +FileSectorInfo6=0 00000000 00000000 +FileSectorInfo7=0 00000000 00000000 +FileSectorInfo8=0 00000000 00000000 +FileSectorSelectMode=0 +[Simulation Environment] +Interrupt0=0 1 1 diff --git a/20080212/Demo/MB91460_Softune/readme.txt b/20080212/Demo/MB91460_Softune/readme.txt new file mode 100644 index 000000000..d74bd01a2 --- /dev/null +++ b/20080212/Demo/MB91460_Softune/readme.txt @@ -0,0 +1,114 @@ + +========================================================================== + Template Project for MB91F467D +========================================================================== + Fujitsu Microelectronics Europe GmbH + http://emea.fujitsu.com/microelectronics + +The following software is for demonstration purposes only. It is not +fully tested, nor validated in order to fullfill its task under all +circumstances. Therefore, this software or any part of it must only be +used in an evaluation laboratory environment. +This software is subject to the rules of our standard DISCLAIMER, that is +delivered with our SW-tools on the Fujitsu Microcontrollers CD /DVD +(V3.4 or higher "\START.HTM"). +========================================================================== + +History +Date Ver Author Softune Description +2007-11-12 1.0 MPi V60L06 original version +2007-11-12 1.1 MPi V60L06 Changed the version for consistency + with SVN +2007-11-23 1.2 MPi V60L06 Seperated Watchdog functionality + added watchdog.c and watchdog.h +2007-12-13 1.3 MPi V60L06 Tested with the FreeRTOS version 4.6.1. +2007-12-13 1.4 MPi V60L06 Tested with the FreeRTOS version 4.7.0. +2007-01-07 1.5 MPi V60L06 Removed watchdog.c, watchdog.h, port.c + and portmacro.h from directory + \FreeRTOS_Port_FR\91467d_FreeRTOS\SRC +2007-01-18 1.6 MPi V60L06 Tested with monitor debugger +========================================================================== +1.0. +This is a project is to test the FreeRTOS port for FR (91467D) and the demo +application which runs on SK-91F467-Felxray V1.1. + +1.1. +This FreeRTOS port uses the Task Stack pointed by User Stack pointer (USP) for +tasks and the system stack pointed by System Stack pointer (SSP) for everything +else. + +1.2. +In this port, the functionality is added to initialize and clear the watchdog in +the dedicated task, Tick Hook or the Idle Hook. The place exactly where the +watchdog can be cleared can be configured. Though Idle Hook is not an approproiate +place to clear the watchdog, its done here for demonstration purpose only. + +Also from Main function vTaskStartScheduler() function is called instead of +xPortStartScheduler(). After doing this change now no more IDLE task is required +to be added seperately as vTaskStartScheduler() adds prvIdleTask() on its own. + +The System Stack required by each of the RLT0 and Delayed Interrupt ISR is around 100 +bytes. This is considering no interrupts has higher priority than the RLT0 and Delayed +interrupt (23). If an application has interrupt whose priority is higher than these +interrupts, which is very likely, then for each such interrupt the user has to increase +the stack size at least by 50 bytes, though this is not an optimum figure and very well +depends upon the application. +Hence though the STACK_SYS_SIZE is defined as 2000, its optimum value would be very well +dependent on the application where the port would be used. + +1.3. +Tested with the FreeRTOS version 4.6.1. + +Changed portBYTE_ALIGNMENT to 4 from 1. + +Added portYIELDFromISR() which uses delayed interrupt. This macro needs to be used from the +application ISRs in order to force a context switch from them if required. It should be noted +that the interrupt priority of such application ISRs MUST be always higher than the dealyed +interrupt (currently 23) in order to perform the context switch correctly. + +It should be also noted that the RLT0 and Delayed Interrupt priority MUST be always same in order +to assure correct working of this port. + +Now portYIELD() used software interrupt INT #40H instead of delayed interrupt. + +Now all the queue functions works ok. + +Tested with the heap_1.c, heap_2.c and heap_3.c. + +Added the __STD_LIB_sbrk.c file in order to define the *sbrk() function. This is required while using +heap_3.c file which uses the dynamic memory allocation. + +Made changes to the demo application files crflash.c and crhook.c. Please refer those file +and grep for "Added by MPi" to find the changes. + +Added taskutility.c file. This file contains vUART4Task() which calls vTaskList() and vTaskStartTrace() +functions. + +If vCreateBlockTimeTasks() is not called then the LED at PDR25_D7 blinks at normal rate (3s). + +1.4. +Tested with the FreeRTOS version 4.6.1. + +At one time, either of heap_1.c or heap_2.c or heap_3.c needs to be used. Hence the files those are not +required to be used should be removed from the target of the build. + +1.5. +Removed watchdog.c, watchdog.h, port.c and portmacro.h from directory \FreeRTOS_Port_FR\91467d_FreeRTOS\SRC, +since they are moved to folders watchdog and port respectively. + +1.6. +It should be noted that the readme, appnote and SVN tag version numbers may be different for the same release. + +Used relative path to include files instead of absolute. + +Created config, MemMang, serial and utility subdirectories and moved corresponding functionlaity there. + +Updated taskuitlity.c, vectors.c in oredr to use UART 5 instead of UART 4 + +Updated flash.c to increase LEDs to 4 from 3. + +Clock settings: +--------------- +Crystal: 4 MHz +CPU: 64 MHz +CLKP: 16 MHz diff --git a/20080212/Demo/MB96340_Softune/96340_FreeRTOS_96348hs.wsp b/20080212/Demo/MB96340_Softune/96340_FreeRTOS_96348hs.wsp new file mode 100644 index 000000000..dbd380940 --- /dev/null +++ b/20080212/Demo/MB96340_Softune/96340_FreeRTOS_96348hs.wsp @@ -0,0 +1,27 @@ +[CPUTYPE] +CpuSerise=907 + +[PrjFile] +Count=2 +FILE-0=FreeRTOS_96348hs_FLASHCAN100P340\FreeRTOS_96348hs_FLASHCAN100P340.prj +FILE-1=FreeRTOS_96348hs_SK16FX100PMC\FreeRTOS_96348hs_SK16FX100PMC.prj +ActivePrj=FreeRTOS_96348hs_SK16FX100PMC.prj + +[SubPrj-FreeRTOS_96348hs_FLASHCAN100P340.prj] +Count=0 + +[SubPrj-FreeRTOS_96348hs_SK16FX100PMC.prj] +Count=0 + +[DebState] +AutoSave=1 +Exec=0 +AutoLoad=1 + +[DirInfo] +WSP=C:\E\Dev\FreeRTOS\WorkingCopy2\Demo\MB96340_Softune\ + +[EditState] +STATE-1=freertos_96348hs_sk16fx100pmc\src\serial\serial.c:192 +Count=1 + diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Config_1/MB2198-01_COM1.sup b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Config_1/MB2198-01_COM1.sup new file mode 100644 index 000000000..548c5e1f2 --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Config_1/MB2198-01_COM1.sup @@ -0,0 +1,146 @@ +[Information] +DebChangeFlag=0 +MCUChangeFlag=1 +[Version] +Version=1 +Level=1 +Revision=0 +[Debug Type] +Type=0 +Virtual CPU File=wv907e4.dll +Core ID=0 +Monitor Load=1 +Monitor Load Condition=Enable +Mode=FFFFFFFF +[Device] +Communication=RS COM1 115200 +ProductID=0 +Protocol=3 +[Target] +AutoLoad=Enable +Before Batch File= +After Batch File= +Non AutoMap=Disable +Load DebInfo Only=Disable +Ondemand Load Condition=Disable +[Start] +Batch File= +[Window] +Flag=Enable +AssemblySize=0 0 0 0 +AssemblyState=0 +AssemblyFGColor=0 0 255 +RegisterSize=0 0 0 0 +RegisterState=0 +MemorySize=0 0 0 0 +MemoryState=0 +CommandSize=0 0 0 0 +CommandState=0 +Assembly Address=H'000000 +Memory Address=H'000000 +Memory Mode=H'FFFFFFFF +Memory Ascii=H'00000001 +Memory SplitRow=0 +RMemory Address=H'000000 +RMemory Mode=H'FFFFFFFF +RMemory Ascii=H'00000001 +RMemory SplitRow=0 +Trace ViewMode=FFFFFFFF +Command Max History=H'00000032 +Source Display Mode=Enable +Source Multi Mode=Enable +Source Ask Mode=Enable +Source Active Mode=Enable +Source PC Color=255 255 0 +Source Scope Color=255 0 255 +Source Back Trace=255 0 255 +Register Change Color=255 0 0 +Perfomance Mode=H'00000001 +Perfomance Scale=1 0 0.000000 0.000000 +Coverage Address=H'000000 +Coverage Type=H'00000000 +Coverage SplitRow=0 +RMemory Change Color=255 0 0 +RMemory Invalid Color=128 128 128 +[Path Environment] +Flag=Enable +Source= +[Map] +Flag=Enable +Undef=On +Inrom Access=Off +Inrom=Off +Inrom Image=On +Area0=00000180 0000037F 7 1 0 +Area1=00002240 00007FFF 7 1 0 +Area2=00000000 000000EF 3 1 0 +Area3=00000100 0000017F 3 1 0 +Area4=00000380 00000BFF 3 1 0 +[Radix Environment] +Flag=Enable +Mode=10 +Source=1 +[Watch Environment] +Flag=Enable +Size=0 +Mode=0 +MBuf=0 +Check=1 +CSiz=100 +[Exec Environment] +Flag=Enable +GoIntMask=0 +StepUnit=3 +StepIntMask=0 +StepIntpCtrl=4 +GoTrcCtrl=2 +OnTheFlyBreakAdmit=0 +[Break Environment] +Flag=Enable +[Emulation Environment] +Flag=Enable +RunMode=0 +Verify=1 +EventMode=0 +Limit Volt MB2198=5.75 2.5 +WatchDoc=0 +Resource=0 +External Pin=0 +DefaultBreak=0 +DebugArea1=105 34A066E 49356 1234724 0 +DebugArea2=0 326508 13702376 1237400 0 +ParallelPort=-1 0 +Performance Break=2 +Coverage Status=0 +Frequency=40 +[Monitor Environment] +Flag=Enable +MemoryWindow=0 +WatchWindow=0 +ObjectWindow=0 +ElapseTime=3E8 +Unit=1 +Mode=0 +RealtimeMemoryWindow=0 +[Error] +Flag=Enable +GuiErrorOutput=2 +CommandErrorOutput=1 +BatchErrorOutput=1 +ErrorOutputLevel=0 +[Color] +Flag=Enable +[Tab Environment] +TabSize=8 +[Communication] +Send=1000 +Receive=800 +[Trace Environment] +Trace Break=0 +Trace Status=1 +Trace StartPosition=1 +Trace BufferfulStop=0 +Trace Instruction=1 +Trace Verbose=0 +Trace DataArea1=1 00000000 FFFFFFFF 7 +Trace DataArea2=2 00000000 FFFFFFFF 0 diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Config_1/MB2198-01_COM2.sup b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Config_1/MB2198-01_COM2.sup new file mode 100644 index 000000000..851fec7ca --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Config_1/MB2198-01_COM2.sup @@ -0,0 +1,146 @@ +[Information] +DebChangeFlag=0 +MCUChangeFlag=1 +[Version] +Version=1 +Level=1 +Revision=0 +[Debug Type] +Type=0 +Virtual CPU File=wv907e4.dll +Core ID=0 +Monitor Load=1 +Monitor Load Condition=Enable +Mode=FFFFFFFF +[Device] +Communication=RS COM2 115200 +ProductID=2002 +Protocol=3 +[Target] +AutoLoad=Enable +Before Batch File= +After Batch File= +Non AutoMap=Disable +Load DebInfo Only=Disable +Ondemand Load Condition=Disable +[Start] +Batch File= +[Window] +Flag=Enable +AssemblySize=0 0 0 0 +AssemblyState=0 +AssemblyFGColor=0 0 255 +RegisterSize=0 0 0 0 +RegisterState=0 +MemorySize=0 0 0 0 +MemoryState=0 +CommandSize=0 0 0 0 +CommandState=0 +Assembly Address=H'000000 +Memory Address=H'000000 +Memory Mode=H'FFFFFFFF +Memory Ascii=H'00000001 +Memory SplitRow=0 +RMemory Address=H'000000 +RMemory Mode=H'FFFFFFFF +RMemory Ascii=H'00000001 +RMemory SplitRow=0 +Trace ViewMode=FFFFFFFF +Command Max History=H'00000032 +Source Display Mode=Enable +Source Multi Mode=Enable +Source Ask Mode=Enable +Source Active Mode=Enable +Source PC Color=255 255 0 +Source Scope Color=255 0 255 +Source Back Trace=255 0 255 +Register Change Color=255 0 0 +Perfomance Mode=H'00000001 +Perfomance Scale=1 0 0.000000 0.000000 +Coverage Address=H'000000 +Coverage Type=H'00000000 +Coverage SplitRow=0 +RMemory Change Color=255 0 0 +RMemory Invalid Color=128 128 128 +[Path Environment] +Flag=Enable +Source= +[Map] +Flag=Enable +Undef=On +Inrom Access=Off +Inrom=Off +Inrom Image=On +Area0=00000180 0000037F 7 1 0 +Area1=00002240 00007FFF 7 1 0 +Area2=00000000 000000EF 3 1 0 +Area3=00000100 0000017F 3 1 0 +Area4=00000380 00000BFF 3 1 0 +[Radix Environment] +Flag=Enable +Mode=10 +Source=1 +[Watch Environment] +Flag=Enable +Size=0 +Mode=0 +MBuf=0 +Check=1 +CSiz=100 +[Exec Environment] +Flag=Enable +GoIntMask=0 +StepUnit=3 +StepIntMask=0 +StepIntpCtrl=4 +GoTrcCtrl=2 +OnTheFlyBreakAdmit=0 +[Break Environment] +Flag=Enable +[Emulation Environment] +Flag=Enable +RunMode=0 +Verify=1 +EventMode=0 +Limit Volt MB2198=5.75 2.5 +WatchDoc=0 +Resource=0 +External Pin=0 +DefaultBreak=0 +DebugArea1=105 34A0671 49356 1234724 0 +DebugArea2=0 326358 13702376 1237400 0 +ParallelPort=-1 0 +Performance Break=2 +Coverage Status=0 +Frequency=40 +[Monitor Environment] +Flag=Enable +MemoryWindow=0 +WatchWindow=0 +ObjectWindow=0 +ElapseTime=3E8 +Unit=1 +Mode=0 +RealtimeMemoryWindow=0 +[Error] +Flag=Enable +GuiErrorOutput=2 +CommandErrorOutput=1 +BatchErrorOutput=1 +ErrorOutputLevel=0 +[Color] +Flag=Enable +[Tab Environment] +TabSize=8 +[Communication] +Send=1000 +Receive=800 +[Trace Environment] +Trace Break=0 +Trace Status=1 +Trace StartPosition=1 +Trace BufferfulStop=0 +Trace Instruction=1 +Trace Verbose=0 +Trace DataArea1=1 00000000 FFFFFFFF 7 +Trace DataArea2=2 00000000 FFFFFFFF 0 diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Config_1/MB2198-01_LAN.sup b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Config_1/MB2198-01_LAN.sup new file mode 100644 index 000000000..683b5bf20 --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Config_1/MB2198-01_LAN.sup @@ -0,0 +1,45 @@ +[Information] +DebChangeFlag=1 +MCUChangeFlag=1 +[Version] +Version=1 +Level=1 +Revision=0 +[Debug Type] +Type=0 +Virtual CPU File=wv907e4.dll +Core ID=0 +Monitor Load=1 +Monitor Load Condition=Enable +[Device] +Communication=LAN 127.0.0.1 +ProductID=0 +Protocol=3 +[Target] +AutoLoad=Enable +Before Batch File= +After Batch File= +[Start] +Batch File= +[Window] +Flag=Enable +[Path Environment] +Flag=Enable +[Map] +Flag=Enable +[Radix Environment] +Flag=Enable +[Watch Environment] +Flag=Enable +[Exec Environment] +Flag=Enable +[Break Environment] +Flag=Enable +[Emulation Environment] +Flag=Enable +[Monitor Environment] +Flag=Enable +[Error] +Flag=Enable +[Color] +Flag=Enable diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Config_1/MB2198-01_USB.sup b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Config_1/MB2198-01_USB.sup new file mode 100644 index 000000000..b951324d8 --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Config_1/MB2198-01_USB.sup @@ -0,0 +1,265 @@ +[Information] +DebChangeFlag=0 +MCUChangeFlag=0 +[Version] +Version=1 +Level=1 +Revision=0 +[Debug Type] +Type=0 +Virtual CPU File=wv907e4.dll +Core ID=0 +Monitor Load=1 +Monitor Load Condition=Enable +Mode=FFFF +[Device] +Communication=USB +ProductID=2002 +Protocol=3 +[Target] +AutoLoad=Enable +Before Batch File= +After Batch File= +Non AutoMap=Disable +Load DebInfo Only=Disable +Ondemand Load Condition=Disable +[Start] +Batch File= +[Window] +Flag=Enable +AssemblySize=0 392 493 588 +AssemblyState=2 +AssemblyFGColor=0 0 255 +RegisterSize=491 191 982 382 +RegisterState=0 +MemorySize=491 382 982 573 +MemoryState=0 +CommandSize=0 0 0 0 +CommandState=0 +Assembly Address=H'F852E9 +Memory Address=H'F80198 +Memory Mode=H'00000001 +Memory Ascii=H'00000001 +Memory SplitRow=0 +RMemory Address=H'000000 +RMemory Mode=H'FFFFFFFF +RMemory Ascii=H'00000001 +RMemory SplitRow=0 +Trace ViewMode=1 +Command Max History=H'00000032 +Source Display Mode=Enable +Source Multi Mode=Enable +Source Ask Mode=Enable +Source Active Mode=Enable +Source PC Color=255 255 0 +Source Scope Color=255 0 255 +Source Back Trace=255 0 255 +Register Change Color=255 0 0 +Perfomance Mode=H'00000001 +Perfomance Scale=1 0 0.000000 0.000000 +Coverage Address=H'000000 +Coverage Type=H'00000000 +Coverage SplitRow=0 +RMemory Change Color=255 0 0 +RMemory Invalid Color=128 128 128 +LocalSize=491 0 982 191 +LocalState=0 +WatchSize=0 287 491 574 +WatchState=0 +Layer0=1004, +Layer1=1006, +Layer2=1003, +Layer3=1005, +Layer4=2000,src\os\tasks.c +Register Select0=H'00000000 +Register Select1=H'00000003 +Register Select2=H'00000004 +Register Select3=H'00000005 +Register Select4=H'00000006 +Register Select5=H'00000007 +Register Select6=H'00000008 +Register Select7=H'00000010 +Register Select8=H'00000011 +Register Select9=H'00000012 +Register Select10=H'00000013 +Register Select11=H'00000014 +Register Select12=H'00000015 +Register Select13=H'00000016 +Register Select14=H'00000017 +Register Select15=H'00000018 +Register Select16=H'00000022 +Register Select17=H'00000023 +Register Select18=H'00000024 +Register Select19=H'00000025 +Register Select20=H'00000026 +Register Select21=H'00000027 +Register Select22=H'00000028 +Register Select23=H'00000029 +Register Select24=H'00000035 +Source0Name=Src\Main.c +Source0Size=0 0 491 287 +Source0State=0 +Source0Line=DA +Source0Mode=2 +Source1Name=Src\port\port.c +Source1Size=22 22 828 421 +Source1State=0 +Source1Line=2E +Source1Mode=2 +Watch Variable0=[usCriticalNesting],00080000,1,-1 -1 +Watch Variable1=[pxCurrentTCB],92040000,1,-1 -1 +Watch Variable2=[pxNewTCB],00080000,1,-1 -1 +TraceSize=244 196 977 510 +TraceState=0 +Watch Variable3=[maindata],10080000,1,-1 -1 +Watch Variable4=[pxReadyTasksLists],10010000,1,-1 -1 +Layer5=2000,Src\watchdog\watchdog.c +Watch Variable5=[queueFail],91030000,1,-1 -1 +Watch Variable6=[xRxedChars],92040000,1,-1 -1 +Watch Variable7=[xCharsForTx],92040000,1,-1 -1 +Watch Variable8=[xBigQueue],10080000,1,-1 -1 +Watch Variable9=[SSR0],A0070000,1,-1 -1 +Watch Variable10=[TMCSR0],A0070000,1,-1 -1 +SymbolSize=0 0 420 128 +SymbolState=0 +Watch Variable11=[cChar],10080000,1,-1 -1 +Watch Variable12=[xTaskCheck],10010000,1,-1 -1 +Watch Variable13=[xPolledQueue],10080000,1,-1 -1 +Watch Variable14=[BGR2],A0070000,1,-1 -1 +Layer6=2000,Src\watchdog\watchdog.h +Layer7=2000,Src\port\portmacro.h +Layer8=2000,Src\vectors.c +Layer9=2000,Src\port\port.c +Layer10=2000,Src\Main.c +Layer11=2000,Src\Start.asm +Layer12=1002, +Source2Name=src\os\tasks.c +Source2Size=66 66 872 465 +Source2State=0 +Source2Line=480 +Source2Mode=2 +Source3Name=Src\Start.asm +Source3Size=88 88 894 487 +Source3State=0 +Source3Line=40F +Source3Mode=2 +Source4Name=Src\watchdog\watchdog.h +Source4Size=132 132 938 531 +Source4State=0 +Source4Line=2E +Source4Mode=2 +Source5Name=Src\watchdog\watchdog.c +Source5Size=154 154 960 553 +Source5State=0 +Source5Line=1 +Source5Mode=2 +Source6Name=Src\port\portmacro.h +Source6Size=22 22 832 425 +Source6State=0 +Source6Line=46 +Source6Mode=2 +Source7Name=Src\vectors.c +Source7Size=44 44 854 447 +Source7State=0 +Source7Line=1 +Source7Mode=2 +Watch Variable15=[sState],90030000,1,-1 -1 +[Path Environment] +Flag=Enable +Source= +[Map] +Flag=Enable +Undef=On +Inrom Access=Off +Inrom=Off +Inrom Image=On +Area0=00000180 0000037F 7 1 0 +Area1=00002240 00007FFF 7 1 0 +Area2=00000000 000000EF 3 1 0 +Area3=00000100 0000017F 3 1 0 +Area4=00000380 00000BFF 3 1 0 +GuardArea0=00010000 000FDFFF 7 +[Radix Environment] +Flag=Enable +Mode=10 +Source=1 +[Watch Environment] +Flag=Enable +Size=0 +Mode=0 +MBuf=0 +Check=1 +CSiz=100 +[Exec Environment] +Flag=Enable +GoIntMask=0 +StepUnit=3 +StepIntMask=0 +StepIntpCtrl=4 +GoTrcCtrl=2 +OnTheFlyBreakAdmit=0 +[Break Environment] +Flag=Enable +Data MB21981=0000247C 00FFFFFF 0 2 1 1 1 1 000000DE 0000FFFF +DataBreakFlag1=Enable +Data MB21982=00002538 00FFFFFF 0 2 1 1 1 1 000000DE 0000FFFF +DataBreakFlag2=Enable +Code MB21986=00DE2616 00FFFFFF 1 0 1 flash.c$98 +CodeBreakFlag6=Enable +Code MB21987=00DE261E 00FFFFFF 1 0 1 flash.c$110 +CodeBreakFlag7=Enable +Code MB21988=00DE2633 00FFFFFF 1 0 1 flash.c$125 +CodeBreakFlag8=Enable +Code MB21989=00DE2650 00FFFFFF 1 0 1 flash.c$138 +CodeBreakFlag9=Enable +Code MB21981=00F8016E 00FFFFFF 1 0 1 main.c$223 +CodeBreakFlag1=Enable +Code MB21983=00F801A8 00FFFFFF 1 0 1 \vParTestSetLED +CodeBreakFlag3=Enable +[Emulation Environment] +Flag=Enable +RunMode=0 +Verify=1 +EventMode=0 +Limit Volt MB2198=5.75 2.5 +WatchDoc=0 +Resource=0 +External Pin=0 +DefaultBreak=0 +DebugArea1=1CCD60 1CCD68 28629 1234724 0 +DebugArea2=0 1DF3D38 11156792 1237400 0 +ParallelPort=-1 0 +Performance Break=2 +Coverage Status=0 +Frequency=40 +[Monitor Environment] +Flag=Enable +MemoryWindow=0 +WatchWindow=1 +ObjectWindow=0 +ElapseTime=3E8 +Unit=1 +Mode=0 +RealtimeMemoryWindow=0 +[Error] +Flag=Enable +GuiErrorOutput=2 +CommandErrorOutput=1 +BatchErrorOutput=1 +ErrorOutputLevel=0 +[Color] +Flag=Enable +[Tab Environment] +TabSize=8 +[Communication] +Send=63992 +Receive=32000 +[Trace Environment] +Trace Break=0 +Trace Status=1 +Trace StartPosition=1 +Trace BufferfulStop=0 +Trace Instruction=1 +Trace Verbose=0 +Trace DataArea1=1 00000000 00FFFFFF 7 +Trace DataArea2=2 00000000 FFFFFFFF 0 diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Config_2/MB2198-01_COM1.sup b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Config_2/MB2198-01_COM1.sup new file mode 100644 index 000000000..548c5e1f2 --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Config_2/MB2198-01_COM1.sup @@ -0,0 +1,146 @@ +[Information] +DebChangeFlag=0 +MCUChangeFlag=1 +[Version] +Version=1 +Level=1 +Revision=0 +[Debug Type] +Type=0 +Virtual CPU File=wv907e4.dll +Core ID=0 +Monitor Load=1 +Monitor Load Condition=Enable +Mode=FFFFFFFF +[Device] +Communication=RS COM1 115200 +ProductID=0 +Protocol=3 +[Target] +AutoLoad=Enable +Before Batch File= +After Batch File= +Non AutoMap=Disable +Load DebInfo Only=Disable +Ondemand Load Condition=Disable +[Start] +Batch File= +[Window] +Flag=Enable +AssemblySize=0 0 0 0 +AssemblyState=0 +AssemblyFGColor=0 0 255 +RegisterSize=0 0 0 0 +RegisterState=0 +MemorySize=0 0 0 0 +MemoryState=0 +CommandSize=0 0 0 0 +CommandState=0 +Assembly Address=H'000000 +Memory Address=H'000000 +Memory Mode=H'FFFFFFFF +Memory Ascii=H'00000001 +Memory SplitRow=0 +RMemory Address=H'000000 +RMemory Mode=H'FFFFFFFF +RMemory Ascii=H'00000001 +RMemory SplitRow=0 +Trace ViewMode=FFFFFFFF +Command Max History=H'00000032 +Source Display Mode=Enable +Source Multi Mode=Enable +Source Ask Mode=Enable +Source Active Mode=Enable +Source PC Color=255 255 0 +Source Scope Color=255 0 255 +Source Back Trace=255 0 255 +Register Change Color=255 0 0 +Perfomance Mode=H'00000001 +Perfomance Scale=1 0 0.000000 0.000000 +Coverage Address=H'000000 +Coverage Type=H'00000000 +Coverage SplitRow=0 +RMemory Change Color=255 0 0 +RMemory Invalid Color=128 128 128 +[Path Environment] +Flag=Enable +Source= +[Map] +Flag=Enable +Undef=On +Inrom Access=Off +Inrom=Off +Inrom Image=On +Area0=00000180 0000037F 7 1 0 +Area1=00002240 00007FFF 7 1 0 +Area2=00000000 000000EF 3 1 0 +Area3=00000100 0000017F 3 1 0 +Area4=00000380 00000BFF 3 1 0 +[Radix Environment] +Flag=Enable +Mode=10 +Source=1 +[Watch Environment] +Flag=Enable +Size=0 +Mode=0 +MBuf=0 +Check=1 +CSiz=100 +[Exec Environment] +Flag=Enable +GoIntMask=0 +StepUnit=3 +StepIntMask=0 +StepIntpCtrl=4 +GoTrcCtrl=2 +OnTheFlyBreakAdmit=0 +[Break Environment] +Flag=Enable +[Emulation Environment] +Flag=Enable +RunMode=0 +Verify=1 +EventMode=0 +Limit Volt MB2198=5.75 2.5 +WatchDoc=0 +Resource=0 +External Pin=0 +DefaultBreak=0 +DebugArea1=105 34A066E 49356 1234724 0 +DebugArea2=0 326508 13702376 1237400 0 +ParallelPort=-1 0 +Performance Break=2 +Coverage Status=0 +Frequency=40 +[Monitor Environment] +Flag=Enable +MemoryWindow=0 +WatchWindow=0 +ObjectWindow=0 +ElapseTime=3E8 +Unit=1 +Mode=0 +RealtimeMemoryWindow=0 +[Error] +Flag=Enable +GuiErrorOutput=2 +CommandErrorOutput=1 +BatchErrorOutput=1 +ErrorOutputLevel=0 +[Color] +Flag=Enable +[Tab Environment] +TabSize=8 +[Communication] +Send=1000 +Receive=800 +[Trace Environment] +Trace Break=0 +Trace Status=1 +Trace StartPosition=1 +Trace BufferfulStop=0 +Trace Instruction=1 +Trace Verbose=0 +Trace DataArea1=1 00000000 FFFFFFFF 7 +Trace DataArea2=2 00000000 FFFFFFFF 0 diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Config_2/MB2198-01_COM2.sup b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Config_2/MB2198-01_COM2.sup new file mode 100644 index 000000000..851fec7ca --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Config_2/MB2198-01_COM2.sup @@ -0,0 +1,146 @@ +[Information] +DebChangeFlag=0 +MCUChangeFlag=1 +[Version] +Version=1 +Level=1 +Revision=0 +[Debug Type] +Type=0 +Virtual CPU File=wv907e4.dll +Core ID=0 +Monitor Load=1 +Monitor Load Condition=Enable +Mode=FFFFFFFF +[Device] +Communication=RS COM2 115200 +ProductID=2002 +Protocol=3 +[Target] +AutoLoad=Enable +Before Batch File= +After Batch File= +Non AutoMap=Disable +Load DebInfo Only=Disable +Ondemand Load Condition=Disable +[Start] +Batch File= +[Window] +Flag=Enable +AssemblySize=0 0 0 0 +AssemblyState=0 +AssemblyFGColor=0 0 255 +RegisterSize=0 0 0 0 +RegisterState=0 +MemorySize=0 0 0 0 +MemoryState=0 +CommandSize=0 0 0 0 +CommandState=0 +Assembly Address=H'000000 +Memory Address=H'000000 +Memory Mode=H'FFFFFFFF +Memory Ascii=H'00000001 +Memory SplitRow=0 +RMemory Address=H'000000 +RMemory Mode=H'FFFFFFFF +RMemory Ascii=H'00000001 +RMemory SplitRow=0 +Trace ViewMode=FFFFFFFF +Command Max History=H'00000032 +Source Display Mode=Enable +Source Multi Mode=Enable +Source Ask Mode=Enable +Source Active Mode=Enable +Source PC Color=255 255 0 +Source Scope Color=255 0 255 +Source Back Trace=255 0 255 +Register Change Color=255 0 0 +Perfomance Mode=H'00000001 +Perfomance Scale=1 0 0.000000 0.000000 +Coverage Address=H'000000 +Coverage Type=H'00000000 +Coverage SplitRow=0 +RMemory Change Color=255 0 0 +RMemory Invalid Color=128 128 128 +[Path Environment] +Flag=Enable +Source= +[Map] +Flag=Enable +Undef=On +Inrom Access=Off +Inrom=Off +Inrom Image=On +Area0=00000180 0000037F 7 1 0 +Area1=00002240 00007FFF 7 1 0 +Area2=00000000 000000EF 3 1 0 +Area3=00000100 0000017F 3 1 0 +Area4=00000380 00000BFF 3 1 0 +[Radix Environment] +Flag=Enable +Mode=10 +Source=1 +[Watch Environment] +Flag=Enable +Size=0 +Mode=0 +MBuf=0 +Check=1 +CSiz=100 +[Exec Environment] +Flag=Enable +GoIntMask=0 +StepUnit=3 +StepIntMask=0 +StepIntpCtrl=4 +GoTrcCtrl=2 +OnTheFlyBreakAdmit=0 +[Break Environment] +Flag=Enable +[Emulation Environment] +Flag=Enable +RunMode=0 +Verify=1 +EventMode=0 +Limit Volt MB2198=5.75 2.5 +WatchDoc=0 +Resource=0 +External Pin=0 +DefaultBreak=0 +DebugArea1=105 34A0671 49356 1234724 0 +DebugArea2=0 326358 13702376 1237400 0 +ParallelPort=-1 0 +Performance Break=2 +Coverage Status=0 +Frequency=40 +[Monitor Environment] +Flag=Enable +MemoryWindow=0 +WatchWindow=0 +ObjectWindow=0 +ElapseTime=3E8 +Unit=1 +Mode=0 +RealtimeMemoryWindow=0 +[Error] +Flag=Enable +GuiErrorOutput=2 +CommandErrorOutput=1 +BatchErrorOutput=1 +ErrorOutputLevel=0 +[Color] +Flag=Enable +[Tab Environment] +TabSize=8 +[Communication] +Send=1000 +Receive=800 +[Trace Environment] +Trace Break=0 +Trace Status=1 +Trace StartPosition=1 +Trace BufferfulStop=0 +Trace Instruction=1 +Trace Verbose=0 +Trace DataArea1=1 00000000 FFFFFFFF 7 +Trace DataArea2=2 00000000 FFFFFFFF 0 diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Config_2/MB2198-01_LAN.sup b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Config_2/MB2198-01_LAN.sup new file mode 100644 index 000000000..683b5bf20 --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Config_2/MB2198-01_LAN.sup @@ -0,0 +1,45 @@ +[Information] +DebChangeFlag=1 +MCUChangeFlag=1 +[Version] +Version=1 +Level=1 +Revision=0 +[Debug Type] +Type=0 +Virtual CPU File=wv907e4.dll +Core ID=0 +Monitor Load=1 +Monitor Load Condition=Enable +[Device] +Communication=LAN 127.0.0.1 +ProductID=0 +Protocol=3 +[Target] +AutoLoad=Enable +Before Batch File= +After Batch File= +[Start] +Batch File= +[Window] +Flag=Enable +[Path Environment] +Flag=Enable +[Map] +Flag=Enable +[Radix Environment] +Flag=Enable +[Watch Environment] +Flag=Enable +[Exec Environment] +Flag=Enable +[Break Environment] +Flag=Enable +[Emulation Environment] +Flag=Enable +[Monitor Environment] +Flag=Enable +[Error] +Flag=Enable +[Color] +Flag=Enable diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Config_2/MB2198-01_USB.sup b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Config_2/MB2198-01_USB.sup new file mode 100644 index 000000000..2e1391a01 --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Config_2/MB2198-01_USB.sup @@ -0,0 +1,286 @@ +[Information] +DebChangeFlag=0 +MCUChangeFlag=0 +[Version] +Version=1 +Level=1 +Revision=0 +[Debug Type] +Type=0 +Virtual CPU File=wv907e4.dll +Core ID=0 +Monitor Load=1 +Monitor Load Condition=Enable +Mode=FFFF +[Device] +Communication=USB +ProductID=2002 +Protocol=3 +[Target] +AutoLoad=Enable +Before Batch File= +After Batch File= +Non AutoMap=Disable +Load DebInfo Only=Disable +Ondemand Load Condition=Disable +[Start] +Batch File= +[Window] +Flag=Enable +AssemblySize=0 392 493 588 +AssemblyState=2 +AssemblyFGColor=0 0 255 +RegisterSize=491 191 982 382 +RegisterState=0 +MemorySize=491 382 982 573 +MemoryState=0 +CommandSize=0 0 0 0 +CommandState=0 +Assembly Address=H'F852F5 +Memory Address=H'F80198 +Memory Mode=H'00000001 +Memory Ascii=H'00000001 +Memory SplitRow=0 +RMemory Address=H'000000 +RMemory Mode=H'FFFFFFFF +RMemory Ascii=H'00000001 +RMemory SplitRow=0 +Trace ViewMode=1 +Command Max History=H'00000032 +Source Display Mode=Enable +Source Multi Mode=Enable +Source Ask Mode=Enable +Source Active Mode=Enable +Source PC Color=255 255 0 +Source Scope Color=255 0 255 +Source Back Trace=255 0 255 +Register Change Color=255 0 0 +Perfomance Mode=H'00000001 +Perfomance Scale=1 0 0.000000 0.000000 +Coverage Address=H'000000 +Coverage Type=H'00000000 +Coverage SplitRow=0 +RMemory Change Color=255 0 0 +RMemory Invalid Color=128 128 128 +LocalSize=491 0 982 191 +LocalState=0 +WatchSize=0 287 491 574 +WatchState=0 +Layer0=1004, +Layer1=1006, +Layer2=1003, +Layer3=1005, +Layer4=2000,Src\taskutility.c +Register Select0=H'00000000 +Register Select1=H'00000003 +Register Select2=H'00000004 +Register Select3=H'00000005 +Register Select4=H'00000006 +Register Select5=H'00000007 +Register Select6=H'00000008 +Register Select7=H'00000010 +Register Select8=H'00000011 +Register Select9=H'00000012 +Register Select10=H'00000013 +Register Select11=H'00000014 +Register Select12=H'00000015 +Register Select13=H'00000016 +Register Select14=H'00000017 +Register Select15=H'00000018 +Register Select16=H'00000022 +Register Select17=H'00000023 +Register Select18=H'00000024 +Register Select19=H'00000025 +Register Select20=H'00000026 +Register Select21=H'00000027 +Register Select22=H'00000028 +Register Select23=H'00000029 +Register Select24=H'00000035 +Source0Name=Src\Main.c +Source0Size=0 0 491 287 +Source0State=0 +Source0Line=DA +Source0Mode=2 +Source1Name=Src\port\port.c +Source1Size=22 22 828 421 +Source1State=0 +Source1Line=2E +Source1Mode=2 +Watch Variable0=[usCriticalNesting],00080000,1,-1 -1 +Watch Variable1=[pxCurrentTCB],92040000,1,-1 -1 +Watch Variable2=[pxNewTCB],00080000,1,-1 -1 +TraceSize=244 196 977 510 +TraceState=0 +Watch Variable3=[maindata],10080000,1,-1 -1 +Watch Variable4=[pxReadyTasksLists],10010000,1,-1 -1 +Layer5=2000,src\os\tasks.c +Watch Variable5=[queueFail],91030000,1,-1 -1 +Watch Variable6=[xRxedChars],92040000,1,-1 -1 +Watch Variable7=[xCharsForTx],92040000,1,-1 -1 +Watch Variable8=[xBigQueue],10080000,1,-1 -1 +Watch Variable9=[SSR0],A0070000,1,-1 -1 +Watch Variable10=[TMCSR0],A0070000,1,-1 -1 +SymbolSize=0 0 420 128 +SymbolState=0 +Watch Variable11=[cChar],10080000,1,-1 -1 +Watch Variable12=[xTaskCheck],10010000,1,-1 -1 +Watch Variable13=[xPolledQueue],10080000,1,-1 -1 +Watch Variable14=[BGR2],A0070000,1,-1 -1 +Layer6=2000,Src\watchdog\watchdog.c +Layer7=2000,Src\watchdog\watchdog.h +Layer8=2000,Src\port\portmacro.h +Layer9=2000,Src\vectors.c +Layer10=2000,Src\__STD_LIB_sbrk.c +Layer11=2000,Src\FreeRTOSConfig.h +Layer12=2000,Src\port\port.c +Layer13=2000,Src\Start.asm +Layer14=2000,Src\Main.c +Source2Name=src\os\tasks.c +Source2Size=66 66 872 465 +Source2State=0 +Source2Line=480 +Source2Mode=2 +Source3Name=Src\Start.asm +Source3Size=88 88 894 487 +Source3State=0 +Source3Line=40F +Source3Mode=2 +Source4Name=Src\watchdog\watchdog.h +Source4Size=132 132 938 531 +Source4State=0 +Source4Line=2E +Source4Mode=2 +Source5Name=Src\watchdog\watchdog.c +Source5Size=154 154 960 553 +Source5State=0 +Source5Line=1 +Source5Mode=2 +Source6Name=Src\taskutility.c +Source6Size=176 176 986 579 +Source6State=0 +Source6Line=64 +Source6Mode=2 +Source7Name=Src\port\portmacro.h +Source7Size=22 22 832 425 +Source7State=0 +Source7Line=46 +Source7Mode=2 +Source8Name=Src\vectors.c +Source8Size=44 44 854 447 +Source8State=0 +Source8Line=1 +Source8Mode=2 +Source9Name=Src\__STD_LIB_sbrk.c +Source9Size=66 66 876 469 +Source9State=0 +Source9Line=1 +Source9Mode=2 +Layer15=1002, +Source10Name=Src\FreeRTOSConfig.h +Source10Size=110 110 920 513 +Source10State=0 +Source10Line=22 +Source10Mode=2 +Watch Variable15=[sState],90030000,1,-1 -1 +[Path Environment] +Flag=Enable +Source= +[Map] +Flag=Enable +Undef=On +Inrom Access=Off +Inrom=Off +Inrom Image=On +Area0=00000180 0000037F 7 1 0 +Area1=00002240 00007FFF 7 1 0 +Area2=00000000 000000EF 3 1 0 +Area3=00000100 0000017F 3 1 0 +Area4=00000380 00000BFF 3 1 0 +GuardArea0=00010000 000FDFFF 7 +[Radix Environment] +Flag=Enable +Mode=10 +Source=1 +[Watch Environment] +Flag=Enable +Size=0 +Mode=0 +MBuf=0 +Check=1 +CSiz=100 +[Exec Environment] +Flag=Enable +GoIntMask=0 +StepUnit=3 +StepIntMask=0 +StepIntpCtrl=4 +GoTrcCtrl=2 +OnTheFlyBreakAdmit=0 +[Break Environment] +Flag=Enable +Data MB21981=0000247C 00FFFFFF 0 2 1 1 1 1 000000DE 0000FFFF +DataBreakFlag1=Enable +Data MB21982=00002538 00FFFFFF 0 2 1 1 1 1 000000DE 0000FFFF +DataBreakFlag2=Enable +Code MB21986=00DE2616 00FFFFFF 1 0 1 flash.c$98 +CodeBreakFlag6=Enable +Code MB21987=00DE261E 00FFFFFF 1 0 1 flash.c$110 +CodeBreakFlag7=Enable +Code MB21988=00DE2633 00FFFFFF 1 0 1 flash.c$125 +CodeBreakFlag8=Enable +Code MB21989=00DE2650 00FFFFFF 1 0 1 flash.c$138 +CodeBreakFlag9=Enable +Code MB21980=00DE00D4 00FFFFFF 1 0 1 +CodeBreakFlag0=Enable +Debug File=C:\Fujitsu\FreeRTOS\FreeRTOS Port 16FX\96340_FreeRTOS_96348hs\96340_FreeRTOS_96348hs\ABS\96340_FreeRTOS_96348hs.abs +Code MB21981=00F8016E 00FFFFFF 1 0 1 main.c$223 +CodeBreakFlag1=Enable +Code MB21983=00F801A8 00FFFFFF 1 0 1 \vParTestSetLED +CodeBreakFlag3=Enable +[Emulation Environment] +Flag=Enable +RunMode=0 +Verify=1 +EventMode=0 +Limit Volt MB2198=5.75 2.5 +WatchDoc=0 +Resource=0 +External Pin=0 +DefaultBreak=0 +DebugArea1=12D714 2AB11CC 27874 1234724 0 +DebugArea2=0 B65720 11154784 1237400 0 +ParallelPort=-1 0 +Performance Break=2 +Coverage Status=0 +Frequency=40 +[Monitor Environment] +Flag=Enable +MemoryWindow=0 +WatchWindow=1 +ObjectWindow=0 +ElapseTime=3E8 +Unit=1 +Mode=0 +RealtimeMemoryWindow=0 +[Error] +Flag=Enable +GuiErrorOutput=2 +CommandErrorOutput=1 +BatchErrorOutput=1 +ErrorOutputLevel=0 +[Color] +Flag=Enable +[Tab Environment] +TabSize=8 +[Communication] +Send=63992 +Receive=32000 +[Trace Environment] +Trace Break=0 +Trace Status=1 +Trace StartPosition=1 +Trace BufferfulStop=0 +Trace Instruction=1 +Trace Verbose=0 +Trace DataArea1=1 00000000 00FFFFFF 7 +Trace DataArea2=2 00000000 FFFFFFFF 0 diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Config_3/MB2198-01_COM1.sup b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Config_3/MB2198-01_COM1.sup new file mode 100644 index 000000000..548c5e1f2 --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Config_3/MB2198-01_COM1.sup @@ -0,0 +1,146 @@ +[Information] +DebChangeFlag=0 +MCUChangeFlag=1 +[Version] +Version=1 +Level=1 +Revision=0 +[Debug Type] +Type=0 +Virtual CPU File=wv907e4.dll +Core ID=0 +Monitor Load=1 +Monitor Load Condition=Enable +Mode=FFFFFFFF +[Device] +Communication=RS COM1 115200 +ProductID=0 +Protocol=3 +[Target] +AutoLoad=Enable +Before Batch File= +After Batch File= +Non AutoMap=Disable +Load DebInfo Only=Disable +Ondemand Load Condition=Disable +[Start] +Batch File= +[Window] +Flag=Enable +AssemblySize=0 0 0 0 +AssemblyState=0 +AssemblyFGColor=0 0 255 +RegisterSize=0 0 0 0 +RegisterState=0 +MemorySize=0 0 0 0 +MemoryState=0 +CommandSize=0 0 0 0 +CommandState=0 +Assembly Address=H'000000 +Memory Address=H'000000 +Memory Mode=H'FFFFFFFF +Memory Ascii=H'00000001 +Memory SplitRow=0 +RMemory Address=H'000000 +RMemory Mode=H'FFFFFFFF +RMemory Ascii=H'00000001 +RMemory SplitRow=0 +Trace ViewMode=FFFFFFFF +Command Max History=H'00000032 +Source Display Mode=Enable +Source Multi Mode=Enable +Source Ask Mode=Enable +Source Active Mode=Enable +Source PC Color=255 255 0 +Source Scope Color=255 0 255 +Source Back Trace=255 0 255 +Register Change Color=255 0 0 +Perfomance Mode=H'00000001 +Perfomance Scale=1 0 0.000000 0.000000 +Coverage Address=H'000000 +Coverage Type=H'00000000 +Coverage SplitRow=0 +RMemory Change Color=255 0 0 +RMemory Invalid Color=128 128 128 +[Path Environment] +Flag=Enable +Source= +[Map] +Flag=Enable +Undef=On +Inrom Access=Off +Inrom=Off +Inrom Image=On +Area0=00000180 0000037F 7 1 0 +Area1=00002240 00007FFF 7 1 0 +Area2=00000000 000000EF 3 1 0 +Area3=00000100 0000017F 3 1 0 +Area4=00000380 00000BFF 3 1 0 +[Radix Environment] +Flag=Enable +Mode=10 +Source=1 +[Watch Environment] +Flag=Enable +Size=0 +Mode=0 +MBuf=0 +Check=1 +CSiz=100 +[Exec Environment] +Flag=Enable +GoIntMask=0 +StepUnit=3 +StepIntMask=0 +StepIntpCtrl=4 +GoTrcCtrl=2 +OnTheFlyBreakAdmit=0 +[Break Environment] +Flag=Enable +[Emulation Environment] +Flag=Enable +RunMode=0 +Verify=1 +EventMode=0 +Limit Volt MB2198=5.75 2.5 +WatchDoc=0 +Resource=0 +External Pin=0 +DefaultBreak=0 +DebugArea1=105 34A066E 49356 1234724 0 +DebugArea2=0 326508 13702376 1237400 0 +ParallelPort=-1 0 +Performance Break=2 +Coverage Status=0 +Frequency=40 +[Monitor Environment] +Flag=Enable +MemoryWindow=0 +WatchWindow=0 +ObjectWindow=0 +ElapseTime=3E8 +Unit=1 +Mode=0 +RealtimeMemoryWindow=0 +[Error] +Flag=Enable +GuiErrorOutput=2 +CommandErrorOutput=1 +BatchErrorOutput=1 +ErrorOutputLevel=0 +[Color] +Flag=Enable +[Tab Environment] +TabSize=8 +[Communication] +Send=1000 +Receive=800 +[Trace Environment] +Trace Break=0 +Trace Status=1 +Trace StartPosition=1 +Trace BufferfulStop=0 +Trace Instruction=1 +Trace Verbose=0 +Trace DataArea1=1 00000000 FFFFFFFF 7 +Trace DataArea2=2 00000000 FFFFFFFF 0 diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Config_3/MB2198-01_COM2.sup b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Config_3/MB2198-01_COM2.sup new file mode 100644 index 000000000..851fec7ca --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Config_3/MB2198-01_COM2.sup @@ -0,0 +1,146 @@ +[Information] +DebChangeFlag=0 +MCUChangeFlag=1 +[Version] +Version=1 +Level=1 +Revision=0 +[Debug Type] +Type=0 +Virtual CPU File=wv907e4.dll +Core ID=0 +Monitor Load=1 +Monitor Load Condition=Enable +Mode=FFFFFFFF +[Device] +Communication=RS COM2 115200 +ProductID=2002 +Protocol=3 +[Target] +AutoLoad=Enable +Before Batch File= +After Batch File= +Non AutoMap=Disable +Load DebInfo Only=Disable +Ondemand Load Condition=Disable +[Start] +Batch File= +[Window] +Flag=Enable +AssemblySize=0 0 0 0 +AssemblyState=0 +AssemblyFGColor=0 0 255 +RegisterSize=0 0 0 0 +RegisterState=0 +MemorySize=0 0 0 0 +MemoryState=0 +CommandSize=0 0 0 0 +CommandState=0 +Assembly Address=H'000000 +Memory Address=H'000000 +Memory Mode=H'FFFFFFFF +Memory Ascii=H'00000001 +Memory SplitRow=0 +RMemory Address=H'000000 +RMemory Mode=H'FFFFFFFF +RMemory Ascii=H'00000001 +RMemory SplitRow=0 +Trace ViewMode=FFFFFFFF +Command Max History=H'00000032 +Source Display Mode=Enable +Source Multi Mode=Enable +Source Ask Mode=Enable +Source Active Mode=Enable +Source PC Color=255 255 0 +Source Scope Color=255 0 255 +Source Back Trace=255 0 255 +Register Change Color=255 0 0 +Perfomance Mode=H'00000001 +Perfomance Scale=1 0 0.000000 0.000000 +Coverage Address=H'000000 +Coverage Type=H'00000000 +Coverage SplitRow=0 +RMemory Change Color=255 0 0 +RMemory Invalid Color=128 128 128 +[Path Environment] +Flag=Enable +Source= +[Map] +Flag=Enable +Undef=On +Inrom Access=Off +Inrom=Off +Inrom Image=On +Area0=00000180 0000037F 7 1 0 +Area1=00002240 00007FFF 7 1 0 +Area2=00000000 000000EF 3 1 0 +Area3=00000100 0000017F 3 1 0 +Area4=00000380 00000BFF 3 1 0 +[Radix Environment] +Flag=Enable +Mode=10 +Source=1 +[Watch Environment] +Flag=Enable +Size=0 +Mode=0 +MBuf=0 +Check=1 +CSiz=100 +[Exec Environment] +Flag=Enable +GoIntMask=0 +StepUnit=3 +StepIntMask=0 +StepIntpCtrl=4 +GoTrcCtrl=2 +OnTheFlyBreakAdmit=0 +[Break Environment] +Flag=Enable +[Emulation Environment] +Flag=Enable +RunMode=0 +Verify=1 +EventMode=0 +Limit Volt MB2198=5.75 2.5 +WatchDoc=0 +Resource=0 +External Pin=0 +DefaultBreak=0 +DebugArea1=105 34A0671 49356 1234724 0 +DebugArea2=0 326358 13702376 1237400 0 +ParallelPort=-1 0 +Performance Break=2 +Coverage Status=0 +Frequency=40 +[Monitor Environment] +Flag=Enable +MemoryWindow=0 +WatchWindow=0 +ObjectWindow=0 +ElapseTime=3E8 +Unit=1 +Mode=0 +RealtimeMemoryWindow=0 +[Error] +Flag=Enable +GuiErrorOutput=2 +CommandErrorOutput=1 +BatchErrorOutput=1 +ErrorOutputLevel=0 +[Color] +Flag=Enable +[Tab Environment] +TabSize=8 +[Communication] +Send=1000 +Receive=800 +[Trace Environment] +Trace Break=0 +Trace Status=1 +Trace StartPosition=1 +Trace BufferfulStop=0 +Trace Instruction=1 +Trace Verbose=0 +Trace DataArea1=1 00000000 FFFFFFFF 7 +Trace DataArea2=2 00000000 FFFFFFFF 0 diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Config_3/MB2198-01_LAN.sup b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Config_3/MB2198-01_LAN.sup new file mode 100644 index 000000000..683b5bf20 --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Config_3/MB2198-01_LAN.sup @@ -0,0 +1,45 @@ +[Information] +DebChangeFlag=1 +MCUChangeFlag=1 +[Version] +Version=1 +Level=1 +Revision=0 +[Debug Type] +Type=0 +Virtual CPU File=wv907e4.dll +Core ID=0 +Monitor Load=1 +Monitor Load Condition=Enable +[Device] +Communication=LAN 127.0.0.1 +ProductID=0 +Protocol=3 +[Target] +AutoLoad=Enable +Before Batch File= +After Batch File= +[Start] +Batch File= +[Window] +Flag=Enable +[Path Environment] +Flag=Enable +[Map] +Flag=Enable +[Radix Environment] +Flag=Enable +[Watch Environment] +Flag=Enable +[Exec Environment] +Flag=Enable +[Break Environment] +Flag=Enable +[Emulation Environment] +Flag=Enable +[Monitor Environment] +Flag=Enable +[Error] +Flag=Enable +[Color] +Flag=Enable diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Config_3/MB2198-01_USB.sup b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Config_3/MB2198-01_USB.sup new file mode 100644 index 000000000..2e1391a01 --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Config_3/MB2198-01_USB.sup @@ -0,0 +1,286 @@ +[Information] +DebChangeFlag=0 +MCUChangeFlag=0 +[Version] +Version=1 +Level=1 +Revision=0 +[Debug Type] +Type=0 +Virtual CPU File=wv907e4.dll +Core ID=0 +Monitor Load=1 +Monitor Load Condition=Enable +Mode=FFFF +[Device] +Communication=USB +ProductID=2002 +Protocol=3 +[Target] +AutoLoad=Enable +Before Batch File= +After Batch File= +Non AutoMap=Disable +Load DebInfo Only=Disable +Ondemand Load Condition=Disable +[Start] +Batch File= +[Window] +Flag=Enable +AssemblySize=0 392 493 588 +AssemblyState=2 +AssemblyFGColor=0 0 255 +RegisterSize=491 191 982 382 +RegisterState=0 +MemorySize=491 382 982 573 +MemoryState=0 +CommandSize=0 0 0 0 +CommandState=0 +Assembly Address=H'F852F5 +Memory Address=H'F80198 +Memory Mode=H'00000001 +Memory Ascii=H'00000001 +Memory SplitRow=0 +RMemory Address=H'000000 +RMemory Mode=H'FFFFFFFF +RMemory Ascii=H'00000001 +RMemory SplitRow=0 +Trace ViewMode=1 +Command Max History=H'00000032 +Source Display Mode=Enable +Source Multi Mode=Enable +Source Ask Mode=Enable +Source Active Mode=Enable +Source PC Color=255 255 0 +Source Scope Color=255 0 255 +Source Back Trace=255 0 255 +Register Change Color=255 0 0 +Perfomance Mode=H'00000001 +Perfomance Scale=1 0 0.000000 0.000000 +Coverage Address=H'000000 +Coverage Type=H'00000000 +Coverage SplitRow=0 +RMemory Change Color=255 0 0 +RMemory Invalid Color=128 128 128 +LocalSize=491 0 982 191 +LocalState=0 +WatchSize=0 287 491 574 +WatchState=0 +Layer0=1004, +Layer1=1006, +Layer2=1003, +Layer3=1005, +Layer4=2000,Src\taskutility.c +Register Select0=H'00000000 +Register Select1=H'00000003 +Register Select2=H'00000004 +Register Select3=H'00000005 +Register Select4=H'00000006 +Register Select5=H'00000007 +Register Select6=H'00000008 +Register Select7=H'00000010 +Register Select8=H'00000011 +Register Select9=H'00000012 +Register Select10=H'00000013 +Register Select11=H'00000014 +Register Select12=H'00000015 +Register Select13=H'00000016 +Register Select14=H'00000017 +Register Select15=H'00000018 +Register Select16=H'00000022 +Register Select17=H'00000023 +Register Select18=H'00000024 +Register Select19=H'00000025 +Register Select20=H'00000026 +Register Select21=H'00000027 +Register Select22=H'00000028 +Register Select23=H'00000029 +Register Select24=H'00000035 +Source0Name=Src\Main.c +Source0Size=0 0 491 287 +Source0State=0 +Source0Line=DA +Source0Mode=2 +Source1Name=Src\port\port.c +Source1Size=22 22 828 421 +Source1State=0 +Source1Line=2E +Source1Mode=2 +Watch Variable0=[usCriticalNesting],00080000,1,-1 -1 +Watch Variable1=[pxCurrentTCB],92040000,1,-1 -1 +Watch Variable2=[pxNewTCB],00080000,1,-1 -1 +TraceSize=244 196 977 510 +TraceState=0 +Watch Variable3=[maindata],10080000,1,-1 -1 +Watch Variable4=[pxReadyTasksLists],10010000,1,-1 -1 +Layer5=2000,src\os\tasks.c +Watch Variable5=[queueFail],91030000,1,-1 -1 +Watch Variable6=[xRxedChars],92040000,1,-1 -1 +Watch Variable7=[xCharsForTx],92040000,1,-1 -1 +Watch Variable8=[xBigQueue],10080000,1,-1 -1 +Watch Variable9=[SSR0],A0070000,1,-1 -1 +Watch Variable10=[TMCSR0],A0070000,1,-1 -1 +SymbolSize=0 0 420 128 +SymbolState=0 +Watch Variable11=[cChar],10080000,1,-1 -1 +Watch Variable12=[xTaskCheck],10010000,1,-1 -1 +Watch Variable13=[xPolledQueue],10080000,1,-1 -1 +Watch Variable14=[BGR2],A0070000,1,-1 -1 +Layer6=2000,Src\watchdog\watchdog.c +Layer7=2000,Src\watchdog\watchdog.h +Layer8=2000,Src\port\portmacro.h +Layer9=2000,Src\vectors.c +Layer10=2000,Src\__STD_LIB_sbrk.c +Layer11=2000,Src\FreeRTOSConfig.h +Layer12=2000,Src\port\port.c +Layer13=2000,Src\Start.asm +Layer14=2000,Src\Main.c +Source2Name=src\os\tasks.c +Source2Size=66 66 872 465 +Source2State=0 +Source2Line=480 +Source2Mode=2 +Source3Name=Src\Start.asm +Source3Size=88 88 894 487 +Source3State=0 +Source3Line=40F +Source3Mode=2 +Source4Name=Src\watchdog\watchdog.h +Source4Size=132 132 938 531 +Source4State=0 +Source4Line=2E +Source4Mode=2 +Source5Name=Src\watchdog\watchdog.c +Source5Size=154 154 960 553 +Source5State=0 +Source5Line=1 +Source5Mode=2 +Source6Name=Src\taskutility.c +Source6Size=176 176 986 579 +Source6State=0 +Source6Line=64 +Source6Mode=2 +Source7Name=Src\port\portmacro.h +Source7Size=22 22 832 425 +Source7State=0 +Source7Line=46 +Source7Mode=2 +Source8Name=Src\vectors.c +Source8Size=44 44 854 447 +Source8State=0 +Source8Line=1 +Source8Mode=2 +Source9Name=Src\__STD_LIB_sbrk.c +Source9Size=66 66 876 469 +Source9State=0 +Source9Line=1 +Source9Mode=2 +Layer15=1002, +Source10Name=Src\FreeRTOSConfig.h +Source10Size=110 110 920 513 +Source10State=0 +Source10Line=22 +Source10Mode=2 +Watch Variable15=[sState],90030000,1,-1 -1 +[Path Environment] +Flag=Enable +Source= +[Map] +Flag=Enable +Undef=On +Inrom Access=Off +Inrom=Off +Inrom Image=On +Area0=00000180 0000037F 7 1 0 +Area1=00002240 00007FFF 7 1 0 +Area2=00000000 000000EF 3 1 0 +Area3=00000100 0000017F 3 1 0 +Area4=00000380 00000BFF 3 1 0 +GuardArea0=00010000 000FDFFF 7 +[Radix Environment] +Flag=Enable +Mode=10 +Source=1 +[Watch Environment] +Flag=Enable +Size=0 +Mode=0 +MBuf=0 +Check=1 +CSiz=100 +[Exec Environment] +Flag=Enable +GoIntMask=0 +StepUnit=3 +StepIntMask=0 +StepIntpCtrl=4 +GoTrcCtrl=2 +OnTheFlyBreakAdmit=0 +[Break Environment] +Flag=Enable +Data MB21981=0000247C 00FFFFFF 0 2 1 1 1 1 000000DE 0000FFFF +DataBreakFlag1=Enable +Data MB21982=00002538 00FFFFFF 0 2 1 1 1 1 000000DE 0000FFFF +DataBreakFlag2=Enable +Code MB21986=00DE2616 00FFFFFF 1 0 1 flash.c$98 +CodeBreakFlag6=Enable +Code MB21987=00DE261E 00FFFFFF 1 0 1 flash.c$110 +CodeBreakFlag7=Enable +Code MB21988=00DE2633 00FFFFFF 1 0 1 flash.c$125 +CodeBreakFlag8=Enable +Code MB21989=00DE2650 00FFFFFF 1 0 1 flash.c$138 +CodeBreakFlag9=Enable +Code MB21980=00DE00D4 00FFFFFF 1 0 1 +CodeBreakFlag0=Enable +Debug File=C:\Fujitsu\FreeRTOS\FreeRTOS Port 16FX\96340_FreeRTOS_96348hs\96340_FreeRTOS_96348hs\ABS\96340_FreeRTOS_96348hs.abs +Code MB21981=00F8016E 00FFFFFF 1 0 1 main.c$223 +CodeBreakFlag1=Enable +Code MB21983=00F801A8 00FFFFFF 1 0 1 \vParTestSetLED +CodeBreakFlag3=Enable +[Emulation Environment] +Flag=Enable +RunMode=0 +Verify=1 +EventMode=0 +Limit Volt MB2198=5.75 2.5 +WatchDoc=0 +Resource=0 +External Pin=0 +DefaultBreak=0 +DebugArea1=12D714 2AB11CC 27874 1234724 0 +DebugArea2=0 B65720 11154784 1237400 0 +ParallelPort=-1 0 +Performance Break=2 +Coverage Status=0 +Frequency=40 +[Monitor Environment] +Flag=Enable +MemoryWindow=0 +WatchWindow=1 +ObjectWindow=0 +ElapseTime=3E8 +Unit=1 +Mode=0 +RealtimeMemoryWindow=0 +[Error] +Flag=Enable +GuiErrorOutput=2 +CommandErrorOutput=1 +BatchErrorOutput=1 +ErrorOutputLevel=0 +[Color] +Flag=Enable +[Tab Environment] +TabSize=8 +[Communication] +Send=63992 +Receive=32000 +[Trace Environment] +Trace Break=0 +Trace Status=1 +Trace StartPosition=1 +Trace BufferfulStop=0 +Trace Instruction=1 +Trace Verbose=0 +Trace DataArea1=1 00000000 00FFFFFF 7 +Trace DataArea2=2 00000000 FFFFFFFF 0 diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Config_4/MB2198-01_COM1.sup b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Config_4/MB2198-01_COM1.sup new file mode 100644 index 000000000..548c5e1f2 --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Config_4/MB2198-01_COM1.sup @@ -0,0 +1,146 @@ +[Information] +DebChangeFlag=0 +MCUChangeFlag=1 +[Version] +Version=1 +Level=1 +Revision=0 +[Debug Type] +Type=0 +Virtual CPU File=wv907e4.dll +Core ID=0 +Monitor Load=1 +Monitor Load Condition=Enable +Mode=FFFFFFFF +[Device] +Communication=RS COM1 115200 +ProductID=0 +Protocol=3 +[Target] +AutoLoad=Enable +Before Batch File= +After Batch File= +Non AutoMap=Disable +Load DebInfo Only=Disable +Ondemand Load Condition=Disable +[Start] +Batch File= +[Window] +Flag=Enable +AssemblySize=0 0 0 0 +AssemblyState=0 +AssemblyFGColor=0 0 255 +RegisterSize=0 0 0 0 +RegisterState=0 +MemorySize=0 0 0 0 +MemoryState=0 +CommandSize=0 0 0 0 +CommandState=0 +Assembly Address=H'000000 +Memory Address=H'000000 +Memory Mode=H'FFFFFFFF +Memory Ascii=H'00000001 +Memory SplitRow=0 +RMemory Address=H'000000 +RMemory Mode=H'FFFFFFFF +RMemory Ascii=H'00000001 +RMemory SplitRow=0 +Trace ViewMode=FFFFFFFF +Command Max History=H'00000032 +Source Display Mode=Enable +Source Multi Mode=Enable +Source Ask Mode=Enable +Source Active Mode=Enable +Source PC Color=255 255 0 +Source Scope Color=255 0 255 +Source Back Trace=255 0 255 +Register Change Color=255 0 0 +Perfomance Mode=H'00000001 +Perfomance Scale=1 0 0.000000 0.000000 +Coverage Address=H'000000 +Coverage Type=H'00000000 +Coverage SplitRow=0 +RMemory Change Color=255 0 0 +RMemory Invalid Color=128 128 128 +[Path Environment] +Flag=Enable +Source= +[Map] +Flag=Enable +Undef=On +Inrom Access=Off +Inrom=Off +Inrom Image=On +Area0=00000180 0000037F 7 1 0 +Area1=00002240 00007FFF 7 1 0 +Area2=00000000 000000EF 3 1 0 +Area3=00000100 0000017F 3 1 0 +Area4=00000380 00000BFF 3 1 0 +[Radix Environment] +Flag=Enable +Mode=10 +Source=1 +[Watch Environment] +Flag=Enable +Size=0 +Mode=0 +MBuf=0 +Check=1 +CSiz=100 +[Exec Environment] +Flag=Enable +GoIntMask=0 +StepUnit=3 +StepIntMask=0 +StepIntpCtrl=4 +GoTrcCtrl=2 +OnTheFlyBreakAdmit=0 +[Break Environment] +Flag=Enable +[Emulation Environment] +Flag=Enable +RunMode=0 +Verify=1 +EventMode=0 +Limit Volt MB2198=5.75 2.5 +WatchDoc=0 +Resource=0 +External Pin=0 +DefaultBreak=0 +DebugArea1=105 34A066E 49356 1234724 0 +DebugArea2=0 326508 13702376 1237400 0 +ParallelPort=-1 0 +Performance Break=2 +Coverage Status=0 +Frequency=40 +[Monitor Environment] +Flag=Enable +MemoryWindow=0 +WatchWindow=0 +ObjectWindow=0 +ElapseTime=3E8 +Unit=1 +Mode=0 +RealtimeMemoryWindow=0 +[Error] +Flag=Enable +GuiErrorOutput=2 +CommandErrorOutput=1 +BatchErrorOutput=1 +ErrorOutputLevel=0 +[Color] +Flag=Enable +[Tab Environment] +TabSize=8 +[Communication] +Send=1000 +Receive=800 +[Trace Environment] +Trace Break=0 +Trace Status=1 +Trace StartPosition=1 +Trace BufferfulStop=0 +Trace Instruction=1 +Trace Verbose=0 +Trace DataArea1=1 00000000 FFFFFFFF 7 +Trace DataArea2=2 00000000 FFFFFFFF 0 diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Config_4/MB2198-01_COM2.sup b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Config_4/MB2198-01_COM2.sup new file mode 100644 index 000000000..851fec7ca --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Config_4/MB2198-01_COM2.sup @@ -0,0 +1,146 @@ +[Information] +DebChangeFlag=0 +MCUChangeFlag=1 +[Version] +Version=1 +Level=1 +Revision=0 +[Debug Type] +Type=0 +Virtual CPU File=wv907e4.dll +Core ID=0 +Monitor Load=1 +Monitor Load Condition=Enable +Mode=FFFFFFFF +[Device] +Communication=RS COM2 115200 +ProductID=2002 +Protocol=3 +[Target] +AutoLoad=Enable +Before Batch File= +After Batch File= +Non AutoMap=Disable +Load DebInfo Only=Disable +Ondemand Load Condition=Disable +[Start] +Batch File= +[Window] +Flag=Enable +AssemblySize=0 0 0 0 +AssemblyState=0 +AssemblyFGColor=0 0 255 +RegisterSize=0 0 0 0 +RegisterState=0 +MemorySize=0 0 0 0 +MemoryState=0 +CommandSize=0 0 0 0 +CommandState=0 +Assembly Address=H'000000 +Memory Address=H'000000 +Memory Mode=H'FFFFFFFF +Memory Ascii=H'00000001 +Memory SplitRow=0 +RMemory Address=H'000000 +RMemory Mode=H'FFFFFFFF +RMemory Ascii=H'00000001 +RMemory SplitRow=0 +Trace ViewMode=FFFFFFFF +Command Max History=H'00000032 +Source Display Mode=Enable +Source Multi Mode=Enable +Source Ask Mode=Enable +Source Active Mode=Enable +Source PC Color=255 255 0 +Source Scope Color=255 0 255 +Source Back Trace=255 0 255 +Register Change Color=255 0 0 +Perfomance Mode=H'00000001 +Perfomance Scale=1 0 0.000000 0.000000 +Coverage Address=H'000000 +Coverage Type=H'00000000 +Coverage SplitRow=0 +RMemory Change Color=255 0 0 +RMemory Invalid Color=128 128 128 +[Path Environment] +Flag=Enable +Source= +[Map] +Flag=Enable +Undef=On +Inrom Access=Off +Inrom=Off +Inrom Image=On +Area0=00000180 0000037F 7 1 0 +Area1=00002240 00007FFF 7 1 0 +Area2=00000000 000000EF 3 1 0 +Area3=00000100 0000017F 3 1 0 +Area4=00000380 00000BFF 3 1 0 +[Radix Environment] +Flag=Enable +Mode=10 +Source=1 +[Watch Environment] +Flag=Enable +Size=0 +Mode=0 +MBuf=0 +Check=1 +CSiz=100 +[Exec Environment] +Flag=Enable +GoIntMask=0 +StepUnit=3 +StepIntMask=0 +StepIntpCtrl=4 +GoTrcCtrl=2 +OnTheFlyBreakAdmit=0 +[Break Environment] +Flag=Enable +[Emulation Environment] +Flag=Enable +RunMode=0 +Verify=1 +EventMode=0 +Limit Volt MB2198=5.75 2.5 +WatchDoc=0 +Resource=0 +External Pin=0 +DefaultBreak=0 +DebugArea1=105 34A0671 49356 1234724 0 +DebugArea2=0 326358 13702376 1237400 0 +ParallelPort=-1 0 +Performance Break=2 +Coverage Status=0 +Frequency=40 +[Monitor Environment] +Flag=Enable +MemoryWindow=0 +WatchWindow=0 +ObjectWindow=0 +ElapseTime=3E8 +Unit=1 +Mode=0 +RealtimeMemoryWindow=0 +[Error] +Flag=Enable +GuiErrorOutput=2 +CommandErrorOutput=1 +BatchErrorOutput=1 +ErrorOutputLevel=0 +[Color] +Flag=Enable +[Tab Environment] +TabSize=8 +[Communication] +Send=1000 +Receive=800 +[Trace Environment] +Trace Break=0 +Trace Status=1 +Trace StartPosition=1 +Trace BufferfulStop=0 +Trace Instruction=1 +Trace Verbose=0 +Trace DataArea1=1 00000000 FFFFFFFF 7 +Trace DataArea2=2 00000000 FFFFFFFF 0 diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Config_4/MB2198-01_LAN.sup b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Config_4/MB2198-01_LAN.sup new file mode 100644 index 000000000..683b5bf20 --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Config_4/MB2198-01_LAN.sup @@ -0,0 +1,45 @@ +[Information] +DebChangeFlag=1 +MCUChangeFlag=1 +[Version] +Version=1 +Level=1 +Revision=0 +[Debug Type] +Type=0 +Virtual CPU File=wv907e4.dll +Core ID=0 +Monitor Load=1 +Monitor Load Condition=Enable +[Device] +Communication=LAN 127.0.0.1 +ProductID=0 +Protocol=3 +[Target] +AutoLoad=Enable +Before Batch File= +After Batch File= +[Start] +Batch File= +[Window] +Flag=Enable +[Path Environment] +Flag=Enable +[Map] +Flag=Enable +[Radix Environment] +Flag=Enable +[Watch Environment] +Flag=Enable +[Exec Environment] +Flag=Enable +[Break Environment] +Flag=Enable +[Emulation Environment] +Flag=Enable +[Monitor Environment] +Flag=Enable +[Error] +Flag=Enable +[Color] +Flag=Enable diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Config_4/MB2198-01_USB.sup b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Config_4/MB2198-01_USB.sup new file mode 100644 index 000000000..2e1391a01 --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Config_4/MB2198-01_USB.sup @@ -0,0 +1,286 @@ +[Information] +DebChangeFlag=0 +MCUChangeFlag=0 +[Version] +Version=1 +Level=1 +Revision=0 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..\..\..\..\..\..\..\SoftuneV3_16bit_REV300019-R03\LIB\907\INCLUDE\stdlib.h +F14-5=- ..\..\..\..\..\..\..\SoftuneV3_16bit_REV300019-R03\LIB\907\INCLUDE\string.h +F14-6=- ..\..\..\Source\include\FreeRTOS.h +F14-7=- ..\..\..\Source\include\projdefs.h +F14-8=- Src\config\FreeRTOSConfig.h +F14-9=- ..\..\..\Source\include\portable.h +F14-10=- ..\..\..\Source\portable\Softune\MB96340\portmacro.h +F14-11=- src\mb96348hs.h +F14-12=- ..\..\..\Source\include\task.h +F14-13=- ..\..\..\Source\include\list.h +F15=12 c 0 ..\..\Common\Minimal\AltBlckQ.c +F15-1=- ..\..\..\..\..\..\..\SoftuneV3_16bit_REV300019-R03\LIB\907\INCLUDE\stdlib.h +F15-2=- ..\..\..\..\..\..\..\SoftuneV3_16bit_REV300019-R03\LIB\907\INCLUDE\stddef.h +F15-3=- ..\..\..\Source\include\FreeRTOS.h +F15-4=- ..\..\..\Source\include\projdefs.h +F15-5=- Src\config\FreeRTOSConfig.h +F15-6=- ..\..\..\Source\include\portable.h +F15-7=- ..\..\..\Source\portable\Softune\MB96340\portmacro.h +F15-8=- src\mb96348hs.h +F15-9=- ..\..\..\Source\include\task.h +F15-10=- ..\..\..\Source\include\list.h +F15-11=- ..\..\..\Source\include\queue.h +F15-12=- ..\..\Common\include\AltBlckQ.h +F16=11 c 0 ..\..\Common\Minimal\AltBlock.c +F16-1=- ..\..\..\Source\include\FreeRTOS.h +F16-2=- ..\..\..\..\..\..\..\SoftuneV3_16bit_REV300019-R03\LIB\907\INCLUDE\stddef.h +F16-3=- ..\..\..\Source\include\projdefs.h +F16-4=- Src\config\FreeRTOSConfig.h +F16-5=- ..\..\..\Source\include\portable.h +F16-6=- ..\..\..\Source\portable\Softune\MB96340\portmacro.h +F16-7=- src\mb96348hs.h +F16-8=- ..\..\..\Source\include\task.h +F16-9=- ..\..\..\Source\include\list.h +F16-10=- ..\..\..\Source\include\queue.h +F16-11=- ..\..\Common\include\AltBlock.h +F17=12 c 0 ..\..\Common\Minimal\AltPollQ.c +F17-1=- ..\..\..\..\..\..\..\SoftuneV3_16bit_REV300019-R03\LIB\907\INCLUDE\stdlib.h +F17-2=- ..\..\..\..\..\..\..\SoftuneV3_16bit_REV300019-R03\LIB\907\INCLUDE\stddef.h +F17-3=- ..\..\..\Source\include\FreeRTOS.h +F17-4=- ..\..\..\Source\include\projdefs.h +F17-5=- Src\config\FreeRTOSConfig.h +F17-6=- ..\..\..\Source\include\portable.h +F17-7=- ..\..\..\Source\portable\Softune\MB96340\portmacro.h +F17-8=- src\mb96348hs.h +F17-9=- ..\..\..\Source\include\task.h +F17-10=- ..\..\..\Source\include\list.h +F17-11=- ..\..\..\Source\include\queue.h +F17-12=- ..\..\Common\include\AltPollQ.h +F18=13 c 0 ..\..\Common\Minimal\AltQTest.c +F18-1=- ..\..\..\..\..\..\..\SoftuneV3_16bit_REV300019-R03\LIB\907\INCLUDE\stdlib.h +F18-2=- ..\..\..\..\..\..\..\SoftuneV3_16bit_REV300019-R03\LIB\907\INCLUDE\stddef.h +F18-3=- ..\..\..\Source\include\FreeRTOS.h +F18-4=- ..\..\..\Source\include\projdefs.h +F18-5=- Src\config\FreeRTOSConfig.h +F18-6=- ..\..\..\Source\include\portable.h +F18-7=- ..\..\..\Source\portable\Softune\MB96340\portmacro.h +F18-8=- src\mb96348hs.h +F18-9=- ..\..\..\Source\include\task.h +F18-10=- ..\..\..\Source\include\list.h +F18-11=- ..\..\..\Source\include\queue.h +F18-12=- ..\..\..\Source\include\semphr.h +F18-13=- ..\..\Common\include\AltQTest.h +F19=12 c 1 ..\..\Common\Minimal\BlockQ.c +F19-1=- ..\..\..\..\..\..\..\SoftuneV3_16bit_REV300019-R03\LIB\907\INCLUDE\stdlib.h +F19-2=- ..\..\..\..\..\..\..\SoftuneV3_16bit_REV300019-R03\LIB\907\INCLUDE\stddef.h +F19-3=- ..\..\..\Source\include\FreeRTOS.h +F19-4=- ..\..\..\Source\include\projdefs.h +F19-5=- Src\config\FreeRTOSConfig.h +F19-6=- ..\..\..\Source\include\portable.h +F19-7=- ..\..\..\Source\portable\Softune\MB96340\portmacro.h +F19-8=- src\mb96348hs.h +F19-9=- ..\..\..\Source\include\task.h +F19-10=- ..\..\..\Source\include\list.h +F19-11=- ..\..\..\Source\include\queue.h +F19-12=- ..\..\Common\include\BlockQ.h +F20=11 c 1 ..\..\Common\Minimal\blocktim.c +F20-1=- ..\..\..\Source\include\FreeRTOS.h +F20-2=- ..\..\..\..\..\..\..\SoftuneV3_16bit_REV300019-R03\LIB\907\INCLUDE\stddef.h +F20-3=- ..\..\..\Source\include\projdefs.h +F20-4=- Src\config\FreeRTOSConfig.h +F20-5=- ..\..\..\Source\include\portable.h +F20-6=- ..\..\..\Source\portable\Softune\MB96340\portmacro.h +F20-7=- src\mb96348hs.h +F20-8=- ..\..\..\Source\include\task.h +F20-9=- ..\..\..\Source\include\list.h +F20-10=- ..\..\..\Source\include\queue.h +F20-11=- ..\..\Common\include\blocktim.h +F21=13 c 1 ..\..\Common\Minimal\comtest.c +F21-1=- ..\..\..\..\..\..\..\SoftuneV3_16bit_REV300019-R03\LIB\907\INCLUDE\stdlib.h +F21-2=- ..\..\..\..\..\..\..\SoftuneV3_16bit_REV300019-R03\LIB\907\INCLUDE\stddef.h +F21-3=- ..\..\..\Source\include\FreeRTOS.h +F21-4=- ..\..\..\Source\include\projdefs.h +F21-5=- Src\config\FreeRTOSConfig.h +F21-6=- ..\..\..\Source\include\portable.h +F21-7=- ..\..\..\Source\portable\Softune\MB96340\portmacro.h +F21-8=- src\mb96348hs.h +F21-9=- ..\..\..\Source\include\task.h +F21-10=- ..\..\..\Source\include\list.h +F21-11=- ..\..\Common\include\serial.h +F21-12=- ..\..\Common\include\comtest.h +F21-13=- ..\..\Common\include\partest.h +F22=12 c 0 ..\..\Common\Minimal\countsem.c +F22-1=- ..\..\..\Source\include\FreeRTOS.h +F22-2=- ..\..\..\..\..\..\..\SoftuneV3_16bit_REV300019-R03\LIB\907\INCLUDE\stddef.h +F22-3=- ..\..\..\Source\include\projdefs.h +F22-4=- Src\config\FreeRTOSConfig.h +F22-5=- ..\..\..\Source\include\portable.h +F22-6=- ..\..\..\Source\portable\Softune\MB96340\portmacro.h +F22-7=- src\mb96348hs.h +F22-8=- ..\..\..\Source\include\task.h +F22-9=- ..\..\..\Source\include\list.h +F22-10=- ..\..\..\Source\include\semphr.h +F22-11=- ..\..\..\Source\include\queue.h +F22-12=- ..\..\Common\include\countsem.h +F23=12 c 1 ..\..\Common\Minimal\crflash.c +F23-1=- ..\..\..\Source\include\FreeRTOS.h +F23-2=- ..\..\..\..\..\..\..\SoftuneV3_16bit_REV300019-R03\LIB\907\INCLUDE\stddef.h +F23-3=- ..\..\..\Source\include\projdefs.h +F23-4=- Src\config\FreeRTOSConfig.h +F23-5=- ..\..\..\Source\include\portable.h +F23-6=- ..\..\..\Source\portable\Softune\MB96340\portmacro.h +F23-7=- src\mb96348hs.h +F23-8=- ..\..\..\Source\include\croutine.h +F23-9=- ..\..\..\Source\include\list.h +F23-10=- ..\..\..\Source\include\queue.h +F23-11=- ..\..\Common\include\partest.h +F23-12=- ..\..\Common\include\crflash.h +F24=11 c 1 ..\..\Common\Minimal\crhook.c +F24-1=- ..\..\..\Source\include\FreeRTOS.h +F24-2=- ..\..\..\..\..\..\..\SoftuneV3_16bit_REV300019-R03\LIB\907\INCLUDE\stddef.h +F24-3=- ..\..\..\Source\include\projdefs.h +F24-4=- Src\config\FreeRTOSConfig.h +F24-5=- ..\..\..\Source\include\portable.h +F24-6=- ..\..\..\Source\portable\Softune\MB96340\portmacro.h +F24-7=- src\mb96348hs.h +F24-8=- ..\..\..\Source\include\croutine.h +F24-9=- ..\..\..\Source\include\list.h +F24-10=- ..\..\..\Source\include\queue.h +F24-11=- ..\..\Common\include\crhook.h +F25=11 c 1 ..\..\Common\Minimal\death.c +F25-1=- ..\..\..\..\..\..\..\SoftuneV3_16bit_REV300019-R03\LIB\907\INCLUDE\stdlib.h +F25-2=- ..\..\..\..\..\..\..\SoftuneV3_16bit_REV300019-R03\LIB\907\INCLUDE\stddef.h +F25-3=- ..\..\..\Source\include\FreeRTOS.h +F25-4=- ..\..\..\Source\include\projdefs.h +F25-5=- Src\config\FreeRTOSConfig.h +F25-6=- ..\..\..\Source\include\portable.h +F25-7=- ..\..\..\Source\portable\Softune\MB96340\portmacro.h +F25-8=- src\mb96348hs.h +F25-9=- ..\..\..\Source\include\task.h +F25-10=- ..\..\..\Source\include\list.h +F25-11=- ..\..\Common\include\death.h +F26=13 c 1 ..\..\Common\Minimal\dynamic.c +F26-1=- ..\..\..\..\..\..\..\SoftuneV3_16bit_REV300019-R03\LIB\907\INCLUDE\stdlib.h +F26-2=- ..\..\..\..\..\..\..\SoftuneV3_16bit_REV300019-R03\LIB\907\INCLUDE\stddef.h +F26-3=- ..\..\..\Source\include\FreeRTOS.h +F26-4=- ..\..\..\Source\include\projdefs.h +F26-5=- Src\config\FreeRTOSConfig.h +F26-6=- ..\..\..\Source\include\portable.h +F26-7=- ..\..\..\Source\portable\Softune\MB96340\portmacro.h +F26-8=- src\mb96348hs.h +F26-9=- ..\..\..\Source\include\task.h +F26-10=- ..\..\..\Source\include\list.h +F26-11=- ..\..\..\Source\include\semphr.h +F26-12=- ..\..\..\Source\include\queue.h +F26-13=- ..\..\Common\include\dynamic.h +F27=12 c 1 ..\..\Common\Minimal\flash.c +F27-1=- ..\..\..\..\..\..\..\SoftuneV3_16bit_REV300019-R03\LIB\907\INCLUDE\stdlib.h +F27-2=- ..\..\..\..\..\..\..\SoftuneV3_16bit_REV300019-R03\LIB\907\INCLUDE\stddef.h +F27-3=- ..\..\..\Source\include\FreeRTOS.h +F27-4=- ..\..\..\Source\include\projdefs.h +F27-5=- Src\config\FreeRTOSConfig.h +F27-6=- ..\..\..\Source\include\portable.h +F27-7=- ..\..\..\Source\portable\Softune\MB96340\portmacro.h +F27-8=- src\mb96348hs.h +F27-9=- ..\..\..\Source\include\task.h +F27-10=- ..\..\..\Source\include\list.h +F27-11=- ..\..\Common\include\partest.h +F27-12=- ..\..\Common\include\flash.h +F28=13 c 1 ..\..\Common\Minimal\flop.c +F28-1=- ..\..\..\..\..\..\..\SoftuneV3_16bit_REV300019-R03\LIB\907\INCLUDE\stdlib.h +F28-2=- ..\..\..\..\..\..\..\SoftuneV3_16bit_REV300019-R03\LIB\907\INCLUDE\stddef.h +F28-3=- ..\..\..\..\..\..\..\SoftuneV3_16bit_REV300019-R03\LIB\907\INCLUDE\math.h +F28-4=- ..\..\..\..\..\..\..\SoftuneV3_16bit_REV300019-R03\LIB\907\INCLUDE\errno.h +F28-5=- ..\..\..\Source\include\FreeRTOS.h +F28-6=- ..\..\..\Source\include\projdefs.h +F28-7=- Src\config\FreeRTOSConfig.h +F28-8=- ..\..\..\Source\include\portable.h +F28-9=- ..\..\..\Source\portable\Softune\MB96340\portmacro.h +F28-10=- src\mb96348hs.h +F28-11=- ..\..\..\Source\include\task.h +F28-12=- ..\..\..\Source\include\list.h +F28-13=- ..\..\Common\include\flop.h +F29=13 c 1 ..\..\Common\Minimal\GenQTest.c +F29-1=- ..\..\..\..\..\..\..\SoftuneV3_16bit_REV300019-R03\LIB\907\INCLUDE\stdlib.h +F29-2=- ..\..\..\..\..\..\..\SoftuneV3_16bit_REV300019-R03\LIB\907\INCLUDE\stddef.h +F29-3=- ..\..\..\Source\include\FreeRTOS.h +F29-4=- ..\..\..\Source\include\projdefs.h +F29-5=- Src\config\FreeRTOSConfig.h +F29-6=- ..\..\..\Source\include\portable.h +F29-7=- ..\..\..\Source\portable\Softune\MB96340\portmacro.h +F29-8=- src\mb96348hs.h +F29-9=- ..\..\..\Source\include\task.h +F29-10=- ..\..\..\Source\include\list.h +F29-11=- ..\..\..\Source\include\queue.h +F29-12=- ..\..\..\Source\include\semphr.h +F29-13=- ..\..\Common\include\GenQTest.h +F30=11 c 1 ..\..\Common\Minimal\integer.c +F30-1=- ..\..\..\..\..\..\..\SoftuneV3_16bit_REV300019-R03\LIB\907\INCLUDE\stdlib.h +F30-2=- ..\..\..\..\..\..\..\SoftuneV3_16bit_REV300019-R03\LIB\907\INCLUDE\stddef.h +F30-3=- ..\..\..\Source\include\FreeRTOS.h +F30-4=- ..\..\..\Source\include\projdefs.h +F30-5=- Src\config\FreeRTOSConfig.h +F30-6=- ..\..\..\Source\include\portable.h +F30-7=- ..\..\..\Source\portable\Softune\MB96340\portmacro.h +F30-8=- src\mb96348hs.h +F30-9=- ..\..\..\Source\include\task.h +F30-10=- ..\..\..\Source\include\list.h +F30-11=- ..\..\Common\include\integer.h +F31=12 c 1 ..\..\Common\Minimal\PollQ.c +F31-1=- ..\..\..\..\..\..\..\SoftuneV3_16bit_REV300019-R03\LIB\907\INCLUDE\stdlib.h +F31-2=- ..\..\..\..\..\..\..\SoftuneV3_16bit_REV300019-R03\LIB\907\INCLUDE\stddef.h +F31-3=- ..\..\..\Source\include\FreeRTOS.h +F31-4=- ..\..\..\Source\include\projdefs.h +F31-5=- Src\config\FreeRTOSConfig.h +F31-6=- ..\..\..\Source\include\portable.h +F31-7=- ..\..\..\Source\portable\Softune\MB96340\portmacro.h +F31-8=- src\mb96348hs.h +F31-9=- ..\..\..\Source\include\task.h +F31-10=- ..\..\..\Source\include\list.h +F31-11=- ..\..\..\Source\include\queue.h +F31-12=- ..\..\Common\include\PollQ.h +F32=13 c 1 ..\..\Common\Minimal\QPeek.c +F32-1=- ..\..\..\..\..\..\..\SoftuneV3_16bit_REV300019-R03\LIB\907\INCLUDE\stdlib.h +F32-2=- ..\..\..\..\..\..\..\SoftuneV3_16bit_REV300019-R03\LIB\907\INCLUDE\stddef.h +F32-3=- ..\..\..\Source\include\FreeRTOS.h +F32-4=- ..\..\..\Source\include\projdefs.h +F32-5=- Src\config\FreeRTOSConfig.h +F32-6=- ..\..\..\Source\include\portable.h +F32-7=- ..\..\..\Source\portable\Softune\MB96340\portmacro.h +F32-8=- src\mb96348hs.h +F32-9=- ..\..\..\Source\include\task.h +F32-10=- ..\..\..\Source\include\list.h +F32-11=- ..\..\..\Source\include\queue.h +F32-12=- ..\..\..\Source\include\semphr.h +F32-13=- ..\..\Common\include\QPeek.h +F33=13 c 1 ..\..\Common\Minimal\semtest.c +F33-1=- ..\..\..\..\..\..\..\SoftuneV3_16bit_REV300019-R03\LIB\907\INCLUDE\stdlib.h +F33-2=- ..\..\..\..\..\..\..\SoftuneV3_16bit_REV300019-R03\LIB\907\INCLUDE\stddef.h +F33-3=- ..\..\..\Source\include\FreeRTOS.h +F33-4=- ..\..\..\Source\include\projdefs.h +F33-5=- Src\config\FreeRTOSConfig.h +F33-6=- ..\..\..\Source\include\portable.h +F33-7=- ..\..\..\Source\portable\Softune\MB96340\portmacro.h +F33-8=- src\mb96348hs.h +F33-9=- ..\..\..\Source\include\task.h +F33-10=- ..\..\..\Source\include\list.h +F33-11=- ..\..\..\Source\include\semphr.h +F33-12=- ..\..\..\Source\include\queue.h +F33-13=- ..\..\Common\include\semtest.h +F34=10 c 0 ..\..\..\Source\portable\MemMang\heap_1.c +F34-1=- ..\..\..\..\..\..\..\SoftuneV3_16bit_REV300019-R03\LIB\907\INCLUDE\stdlib.h +F34-2=- ..\..\..\..\..\..\..\SoftuneV3_16bit_REV300019-R03\LIB\907\INCLUDE\stddef.h +F34-3=- ..\..\..\Source\include\FreeRTOS.h +F34-4=- ..\..\..\Source\include\projdefs.h +F34-5=- Src\config\FreeRTOSConfig.h +F34-6=- ..\..\..\Source\include\portable.h +F34-7=- ..\..\..\Source\portable\Softune\MB96340\portmacro.h +F34-8=- src\mb96348hs.h +F34-9=- ..\..\..\Source\include\task.h +F34-10=- ..\..\..\Source\include\list.h +F35=10 c 0 ..\..\..\Source\portable\MemMang\heap_2.c +F35-1=- ..\..\..\..\..\..\..\SoftuneV3_16bit_REV300019-R03\LIB\907\INCLUDE\stdlib.h +F35-2=- ..\..\..\..\..\..\..\SoftuneV3_16bit_REV300019-R03\LIB\907\INCLUDE\stddef.h +F35-3=- ..\..\..\Source\include\FreeRTOS.h +F35-4=- ..\..\..\Source\include\projdefs.h +F35-5=- Src\config\FreeRTOSConfig.h +F35-6=- ..\..\..\Source\include\portable.h +F35-7=- ..\..\..\Source\portable\Softune\MB96340\portmacro.h +F35-8=- src\mb96348hs.h +F35-9=- ..\..\..\Source\include\task.h +F35-10=- ..\..\..\Source\include\list.h +F36=10 c 1 ..\..\..\Source\portable\MemMang\heap_3.c +F36-1=- ..\..\..\..\..\..\..\SoftuneV3_16bit_REV300019-R03\LIB\907\INCLUDE\stdlib.h +F36-2=- ..\..\..\..\..\..\..\SoftuneV3_16bit_REV300019-R03\LIB\907\INCLUDE\stddef.h +F36-3=- ..\..\..\Source\include\FreeRTOS.h +F36-4=- ..\..\..\Source\include\projdefs.h +F36-5=- Src\config\FreeRTOSConfig.h +F36-6=- ..\..\..\Source\include\portable.h +F36-7=- ..\..\..\Source\portable\Softune\MB96340\portmacro.h +F36-8=- src\mb96348hs.h +F36-9=- ..\..\..\Source\include\task.h +F36-10=- ..\..\..\Source\include\list.h + +[BUILDMODE-Config_4] +kernel=1 +ABI=0 + +[RUNSET-Config_4] +CONVERT=1 +CONVERTKIND=0 + +[DebState-Config_4] +SupCount=5 +Supfile-0=Config_4\MB2198-01_COM1.sup +Supfile-1=Config_4\MB2198-01_COM2.sup +Supfile-2=Config_4\MB2198-01_LAN.sup +Supfile-3=Config_4\MB2198-01_USB.sup +Supfile-4=Config_4\Simulator.sup +Current=MB2198-01_USB.sup +AliasFile= +CPURunMode=16,16,16,16,0,1,0x0:0x0,,0,0xFF + +[AsmBefore] +Count=0 + +[AsmAfter] +Count=0 + +[CcBefore] +Count=0 + +[CcAfter] +Count=0 + +[LnkBefore] +Count=0 + +[LnkAfter] +Count=0 + +[LibBefore] +Count=0 + +[LibAfter] +Count=0 + +[CnvBefore] +Count=0 + +[CnvAfter] +Count=0 + +[ConfigBefore] +Count=0 + +[ConfigAfter] +Count=0 + diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Prc/romconst.prc b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Prc/romconst.prc new file mode 100644 index 000000000..d56d47ef8 --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Prc/romconst.prc @@ -0,0 +1,325 @@ +# Simulator only: +# Copy ROM-mirror area to bank 0x00 + +if %EVAL(ROMM_CONFIG & 0x01) == 0x01 + +set variable ROMM_BANK = %EVAL(ROMM_CONFIG >> 4) +set variable ROMM_SIZE = %EVAL((ROMM_CONFIG >> 1) & 0x03) + +print "\n\n>Set ROM-mirror memory map...\n" + + +if %ROMM_SIZE == 0 +set map /read H'00E000..H'00FFFF + +if %ROMM_BANK == 0x00 +show map +move H'f0e000..H'F0FFFF,H'e000 + +elseif %ROMM_BANK == 0x01 +show map +move H'f1e000..H'F1FFFF,H'e000 + +elseif %ROMM_BANK == 0x02 +show map +move H'f2e000..H'F2FFFF,H'e000 + +elseif %ROMM_BANK == 0x03 +show map +move H'f3e000..H'F3FFFF,H'e000 + +elseif %ROMM_BANK == 0x04 +show map +move H'f4e000..H'F4FFFF,H'e000 + +elseif %ROMM_BANK == 0x05 +show map +move H'f5e000..H'F5FFFF,H'e000 + +elseif %ROMM_BANK == 0x06 +show map +move H'f6e000..H'F6FFFF,H'e000 + +elseif %ROMM_BANK == 0x07 +show map +move H'f7e000..H'F7FFFF,H'e000 + +elseif %ROMM_BANK == 0x08 +show map +move H'f8e000..H'F8FFFF,H'e000 + +elseif %ROMM_BANK == 0x09 +show map +move H'f9e000..H'F9FFFF,H'e000 + +elseif %ROMM_BANK == 0x0A +show map +move H'fAe000..H'FAFFFF,H'e000 + +elseif %ROMM_BANK == 0x0B +show map +move H'fBe000..H'FBFFFF,H'e000 + +elseif %ROMM_BANK == 0x0B +show map +move H'fBe000..H'FBFFFF,H'e000 + +elseif %ROMM_BANK == 0x0C +show map +move H'fCe000..H'FCFFFF,H'e000 + +elseif %ROMM_BANK == 0x0D +show map +move H'fde000..H'FDFFFF,H'e000 + +elseif %ROMM_BANK == 0x0E +show map +move H'fee000..H'FEFFFF,H'e000 + +elseif %ROMM_BANK == 0x0F +show map +move H'ffe000..H'FFFFFF,H'e000 + +endif # ROMM_BANK selection + +elseif %ROMM_SIZE == 1 +set map /read H'00C000..H'00FFFF + +if %ROMM_BANK == 0x00 +show map +move H'f0c000..H'F0FFFF,H'c000 + +elseif %ROMM_BANK == 0x01 +show map +move H'f1c000..H'F1FFFF,H'c000 + +elseif %ROMM_BANK == 0x02 +show map +move H'f2c000..H'F2FFFF,H'c000 + +elseif %ROMM_BANK == 0x03 +show map +move H'f3c000..H'F3FFFF,H'c000 + +elseif %ROMM_BANK == 0x04 +show map +move H'f4c000..H'F4FFFF,H'c000 + +elseif %ROMM_BANK == 0x05 +show map +move H'f5c000..H'F5FFFF,H'c000 + +elseif %ROMM_BANK == 0x06 +show map +move H'f6c000..H'F6FFFF,H'c000 + +elseif %ROMM_BANK == 0x07 +show map +move H'f7c000..H'F7FFFF,H'c000 + +elseif %ROMM_BANK == 0x08 +show map +move H'f8c000..H'F8FFFF,H'c000 + +elseif %ROMM_BANK == 0x09 +show map +move H'f9c000..H'F9FFFF,H'c000 + +elseif %ROMM_BANK == 0x0A +show map +move H'fAc000..H'FAFFFF,H'c000 + +elseif %ROMM_BANK == 0x0B +show map +move H'fBc000..H'FBFFFF,H'c000 + +elseif %ROMM_BANK == 0x0B +show map +move H'fBc000..H'FBFFFF,H'c000 + +elseif %ROMM_BANK == 0x0C +show map +move H'fCc000..H'FCFFFF,H'c000 + +elseif %ROMM_BANK == 0x0D +show map +move H'fdc000..H'FDFFFF,H'c000 + +elseif %ROMM_BANK == 0x0E +show map +move H'fec000..H'FEFFFF,H'c000 + +elseif %ROMM_BANK == 0x0F +show map +move H'ffc000..H'FFFFFF,H'c000 + +endif # ROMM_BANK selection + +elseif %ROMM_SIZE == 2 +set map /read H'00A000..H'00FFFF + +if %ROMM_BANK == 0x00 +show map +move H'f0a000..H'F0FFFF,H'a000 + +elseif %ROMM_BANK == 0x01 +show map +move H'f1a000..H'F1FFFF,H'a000 + +elseif %ROMM_BANK == 0x02 +show map +move H'f2a000..H'F2FFFF,H'a000 + +elseif %ROMM_BANK == 0x03 +show map +move H'f3a000..H'F3FFFF,H'a000 + +elseif %ROMM_BANK == 0x04 +show map +move H'f4a000..H'F4FFFF,H'a000 + +elseif %ROMM_BANK == 0x05 +show map +move H'f5a000..H'F5FFFF,H'a000 + +elseif %ROMM_BANK == 0x06 +show map +move H'f6a000..H'F6FFFF,H'a000 + +elseif %ROMM_BANK == 0x07 +show map +move H'f7a000..H'F7FFFF,H'a000 + +elseif %ROMM_BANK == 0x08 +show map +move H'f8a000..H'F8FFFF,H'a000 + +elseif %ROMM_BANK == 0x09 +show map +move H'f9a000..H'F9FFFF,H'a000 + +elseif %ROMM_BANK == 0x0A +show map +move H'fAa000..H'FAFFFF,H'a000 + +elseif %ROMM_BANK == 0x0B +show map +move H'fBa000..H'FBFFFF,H'a000 + +elseif %ROMM_BANK == 0x0B +show map +move H'fBa000..H'FBFFFF,H'a000 + +elseif %ROMM_BANK == 0x0C +show map +move H'fCa000..H'FCFFFF,H'a000 + +elseif %ROMM_BANK == 0x0D +show map +move H'fda000..H'FDFFFF,H'a000 + +elseif %ROMM_BANK == 0x0E +show map +move H'fea000..H'FEFFFF,H'a000 + +elseif %ROMM_BANK == 0x0F +show map +move H'ffa000..H'FFFFFF,H'a000 + +endif # ROMM_BANK selection + +elseif %ROMM_SIZE == 3 +set map /read H'008000..H'00FFFF + +if %ROMM_BANK == 0x00 +show map +move H'f08000..H'F0FFFF,H'8000 + +elseif %ROMM_BANK == 0x01 +show map +move H'f18000..H'F1FFFF,H'8000 + +elseif %ROMM_BANK == 0x02 +show map +move H'f28000..H'F2FFFF,H'8000 + +elseif %ROMM_BANK == 0x03 +show map +move H'f38000..H'F3FFFF,H'8000 + +elseif %ROMM_BANK == 0x04 +show map +move H'f48000..H'F4FFFF,H'8000 + +elseif %ROMM_BANK == 0x05 +show map +move H'f58000..H'F5FFFF,H'8000 + +elseif %ROMM_BANK == 0x06 +show map +move H'f68000..H'F6FFFF,H'8000 + +elseif %ROMM_BANK == 0x07 +show map +move H'f78000..H'F7FFFF,H'8000 + +elseif %ROMM_BANK == 0x08 +show map +move H'f88000..H'F8FFFF,H'8000 + +elseif %ROMM_BANK == 0x09 +show map +move H'f98000..H'F9FFFF,H'8000 + +elseif %ROMM_BANK == 0x0A +show map +move H'fA8000..H'FAFFFF,H'8000 + +elseif %ROMM_BANK == 0x0B +show map +move H'fB8000..H'FBFFFF,H'8000 + +elseif %ROMM_BANK == 0x0B +show map +move H'fB8000..H'FBFFFF,H'8000 + +elseif %ROMM_BANK == 0x0C +show map +move H'fC8000..H'FCFFFF,H'8000 + +elseif %ROMM_BANK == 0x0D +show map +move H'fd8000..H'FDFFFF,H'8000 + +elseif %ROMM_BANK == 0x0E +show map +move H'fe8000..H'FEFFFF,H'8000 + +elseif %ROMM_BANK == 0x0F +show map +move H'ff8000..H'FFFFFF,H'8000 + +endif # ROMM_BANK selection + +endif # ROMM_SIZE selection + +print ">Copy ROMCONST for simulation..." +print "OK" + +print "\n-----------------------------------------------------------" +print "\nUse command \"batch prc\\romconst.prc\" after each download" +print "\n-----------------------------------------------------------" + +else + +print "\n----------------------" +print "\nROM Mirror disabled!!!" +print "\n----------------------" + +endif + +print "\n-------------------------------------------------------------------" +print "\nSetting CKMR to 0xF0 to allow for the Clock Wait in that start.asm." +print "\n-------------------------------------------------------------------" + +set MEM /byte 0x0403 = 0xF0 diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Simulator.sup b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Simulator.sup new file mode 100644 index 000000000..6e44211ea --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Simulator.sup @@ -0,0 +1,210 @@ +[Information] +DebChangeFlag=0 +MCUChangeFlag=0 + +[Version] +Version=1 +Level=1 +Revision=0 + +[Debug Type] +Type=1 +Virtual CPU File=wv907f1.dll +Monitor Load=1 +Monitor Load Condition=Disable +Core ID=0 + +[Device] +Communication=LAN 141.187.6.53 +ProductID=0 +Protocol=3 + +[Target] +AutoLoad=Enable +Before Batch File= +After Batch File=Prc\romconst.prc +Non AutoMap=Disable +Load DebInfo Only=Disable +Ondemand Load Condition=Disable + +[Start] +Batch File= + +[Window] +Flag=Enable +AssemblySize=0 0 0 0 +AssemblyState=0 +AssemblyFGColor=0 0 255 +Assembly Address=H'000000 +Memory Address=H'004241 +Memory Mode=H'00000001 +Memory Ascii=H'00000001 +Memory SplitRow=0 +RMemory Address=H'000000 +RMemory Mode=H'FFFFFFFF +RMemory Ascii=H'00000001 +RMemory SplitRow=0 +Trace ViewMode=1 +Command Max History=H'00000032 +Source Display Mode=Enable +Source Multi Mode=Enable +Source Ask Mode=Enable +Source Active Mode=Enable +Source PC Color=255 255 0 +Source Scope Color=255 0 255 +Source Back Trace=255 0 255 +Register Change Color=255 0 0 +Perfomance Mode=H'00000001 +Perfomance Scale=1 0 0.000000 0.000000 +Coverage Address=H'000000 +Coverage Type=H'00000000 +RMemory Change Color=255 0 0 +RMemory Invalid Color=128 128 128 +CommandSize=0 534 359 712 +CommandState=0 +MemorySize=487 476 974 714 +MemoryState=0 +Layer0=1003, +Coverage SplitRow=0 +Layer1=1006, +Layer2=1004, +Source0Name=Src\Main.c +Source0Size=487 238 974 476 +Source0State=2 +Source0Line=21 +Source0Mode=1 +Source1Name=Src\Start.asm +Source1Size=154 154 912 653 +Source1State=0 +Source1Line=40C +Source1Mode=2 +RegisterSize=487 0 974 238 +RegisterState=0 +Layer3=2000,Src\Start.asm +Register Select0=H'00000000 +Register Select1=H'00000003 +Register Select2=H'00000004 +Register Select3=H'00000005 +Register Select4=H'00000006 +Register Select5=H'00000007 +Register Select6=H'00000008 +Register Select7=H'00000010 +Register Select8=H'00000011 +Register Select9=H'00000012 +Register Select10=H'00000013 +Register Select11=H'00000014 +Register Select12=H'00000015 +Register Select13=H'00000016 +Register Select14=H'00000017 +Register Select15=H'00000018 +Register Select16=H'00000022 +Register Select17=H'00000023 +Register Select18=H'00000024 +Register Select19=H'00000025 +Register Select20=H'00000026 +Register Select21=H'00000027 +Register Select22=H'00000028 +Register Select23=H'00000029 +Register Select24=H'00000035 +WatchSize=0 357 487 714 +WatchState=0 +Watch Variable0=[pxCurrentTCB],92040000,1,-1 -1 +Watch Variable1=[pxTCB],10080000,1,-1 -1 +Watch Variable2=[usCriticalNesting],91030000,1,-1 -1 +LocalSize=388 0 582 161 +LocalState=0 +Layer4=1007, +Layer5=2000,Src\Main.c +TraceSize=243 178 486 356 +TraceState=0 +Watch Variable3=[*ptr],90080000,1,-1 -1 + +[Path Environment] +Flag=Enable +Source= + +[Map] +Flag=Enable +Area0=00000000 000000EF 3 0 0 +Area2=00000100 0000017F 3 0 0 +Area3=00000180 0000018F 7 0 0 +Area4=00000190 00000369 3 0 0 +Area5=0000036A 0000037F 7 0 0 +Area6=00000380 00000BFF 3 0 0 +Area8=00002240 0000470F 3 0 0 +Area9=00004710 00007FFF 7 0 0 +Area10=00008000 0000FFFF 1 0 0 +Area12=000F0000 000F0FFF 3 0 0 +Area14=000FE000 000FFFFF 5 0 0 +Area16=00DE0000 00DE7FFF 5 0 0 +Area18=00DF0000 00DF7FFF 5 0 0 +Area20=00F80000 00FFFFFF 5 0 0 +Inrom Image=Off + +[Radix Environment] +Flag=Enable +Mode=10 +Source=1 + +[Watch Environment] +Flag=Enable +Size=0 +Mode=0 +MBuf=0 +Check=1 +CSiz=100 + +[Exec Environment] +Flag=Enable +GoIntMask=0 +StepUnit=3 +StepIntMask=0 +StepIntpCtrl=4 +GoTrcCtrl=2 +OnTheFlyBreakAdmit=0 + +[Break Environment] +Flag=Enable +Code0=00DE00F1 1 0 1 +CodeBreakFlag0=Enable +Code1=00DE012F 1 0 1 main.c$103 +CodeBreakFlag1=Enable +Debug File=C:\Fujitsu\FreeRTOS\FreeRTOS Port 16FX\96340_FreeRTOS_96348hs-v17\96340_FreeRTOS_96348hs-v17\ABS\96340_FreeRTOS_96348hs.abs +Code2=00DE013E 1 0 1 +CodeBreakFlag2=Enable +Code3=00DE1B64 1 0 1 \prvRLT0_TICKISR +CodeBreakFlag3=Enable + +[Emulation Environment] +Flag=Disable + +[Monitor Environment] +Flag=Enable +MemoryWindow=1 +WatchWindow=0 +ObjectWindow=0 +ElapseTime=3E8 +Unit=1 +Mode=0 +RealtimeMemoryWindow=0 + +[Error] +Flag=Enable +GuiErrorOutput=2 +CommandErrorOutput=1 +BatchErrorOutput=1 +ErrorOutputLevel=0 + +[Color] +Flag=Enable + +[Tab Environment] +TabSize=8 + +[Communication] +Send=1000 +Receive=64 + +[Trace Environment] +Trace Break=0 +Trace Status=1 diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Src/MAIN.C b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Src/MAIN.C new file mode 100644 index 000000000..c5e03a5d1 --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Src/MAIN.C @@ -0,0 +1,397 @@ +/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ +/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ +/* ELIGIBILITY FOR ANY PURPOSES. */ +/* (C) Fujitsu Microelectronics Europe GmbH */ +/*--------------------------------------------------------------------------- + MAIN.C + - description + - See README.TXT for project description and disclaimer. + +/*---------------------------------------------------------------------------*/ + +/* 16FX includes */ +#include "mb96348hs.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" +#include +#include + +/*---------------------------------------------------------------------------*/ + +/* Demo task priorities. */ +#define WTC_TASK_PRIORITY ( tskIDLE_PRIORITY + 5 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) +#define TASK_UTILITY_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_BLOCK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainDEATH_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainGENERIC_QUEUE_PRIORITY ( tskIDLE_PRIORITY ) + +/* Baud rate used by the COM test tasks. */ +#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 19200 ) + +/* The frequency at which the 'Check' tasks executes. See the comments at the +top of the page. When the system is operating error free the 'Check' task +toggles an LED every three seconds. If an error is discovered in any task the +rate is increased to 500 milliseconds. [in this case the '*' characters on the +LCD represent LED's]*/ +#define mainNO_ERROR_CHECK_DELAY ( ( portTickType ) 3000 / portTICK_RATE_MS ) +#define mainERROR_CHECK_DELAY ( ( portTickType ) 500 / portTICK_RATE_MS ) + +/*---------------------------------------------------------------------------*/ +#define ledNUMBER_OF_LEDS 8 +#define mainCOM_TEST_LED 0x05 +#define mainCHECK_TEST_LED 0x07 +/*---------------------------------------------------------------------------*/ +/* + * The function that implements the Check task. See the comments at the head + * of the page for implementation details. + */ +static void vErrorChecks( void *pvParameters ); + +/* + * Called by the Check task. Returns pdPASS if all the other tasks are found + * to be operating without error - otherwise returns pdFAIL. + */ +static portSHORT prvCheckOtherTasksAreStillRunning( void ); + +/*---------------------------------------------------------------------------*/ + +static unsigned portCHAR sState = 0x00; +/*--------------------------------------------------------------------------- + * The below callback function is called from Tick ISR if configUSE_TICK_HOOK + * is configured as 1. + *---------------------------------------------------------------------------*/ +/*void vApplicationTickHook ( void ) +{ +#if WATCHDOG == WTC_IN_TICK + Kick_Watchdog(); +#endif +}*/ + +/*--------------------------------------------------------------------------- + * The below callback function is called from Delayed ISR if configUSE_IDLE_HOOK + * is configured as 1. + *---------------------------------------------------------------------------*/ +void vApplicationIdleHook ( void ) +{ +#if WATCHDOG == WTC_IN_IDLE + Kick_Watchdog(); +#endif + +#if ( INCLUDE_StartFlashCoRoutines == 1 || INCLUDE_StartHookCoRoutines == 1 ) + vCoRoutineSchedule(); +#endif +} +/*--------------------------------------------------------------------------- + * Initialize Port 00 + *---------------------------------------------------------------------------*/ +static void prvInitPort00( void ) +{ + DDR00 = 0xFF; + PDR00 = 0x00; +} +/*--------------------------------------------------------------------------- + * Setup the hardware + *---------------------------------------------------------------------------*/ +static void prvSetupHardware( void ) +{ + prvInitPort00(); + +#if WATCHDOG != WTC_NONE + InitWatchdog(); +#endif +} + +/*--------------------------------------------------------------------------- + * main() + *---------------------------------------------------------------------------*/ +void main(void) +{ + InitIrqLevels(); /* Initialize interrupts */ + __set_il(7); /* Allow all levels */ + + prvSetupHardware(); + +#if WATCHDOG == WTC_IN_TASK + vStartWatchdogTask( WTC_TASK_PRIORITY ); +#endif + + /* Start the standard demo application tasks. */ + +#if ( INCLUDE_StartLEDFlashTasks == 1 ) + vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); +#endif + +#if ( INCLUDE_StartIntegerMathTasks == 1 ) + vStartIntegerMathTasks( tskIDLE_PRIORITY ); +#endif + +#if ( INCLUDE_AltStartComTestTasks == 1 ) + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED - 1 ); +#endif + +#if ( INCLUDE_StartPolledQueueTasks == 1 ) + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); +#endif + +#if ( INCLUDE_StartSemaphoreTasks == 1 ) + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); +#endif + +#if ( INCLUDE_StartBlockingQueueTasks == 1 ) + vStartBlockingQueueTasks ( mainQUEUE_BLOCK_PRIORITY ); +#endif + +#if ( INCLUDE_StartDynamicPriorityTasks == 1 ) + vStartDynamicPriorityTasks(); +#endif + +#if ( INCLUDE_StartMathTasks == 1 ) + vStartMathTasks( tskIDLE_PRIORITY ); +#endif + +#if ( INCLUDE_StartFlashCoRoutines == 1 ) + vStartFlashCoRoutines( ledNUMBER_OF_LEDS-1 ); +#endif + +#if ( INCLUDE_StartHookCoRoutines == 1 ) + vStartHookCoRoutines(); +#endif + +#if ( INCLUDE_StartGenericQueueTasks == 1 ) + vStartGenericQueueTasks( mainGENERIC_QUEUE_PRIORITY ); +#endif + +#if ( INCLUDE_StartQueuePeekTasks == 1 ) + vStartQueuePeekTasks(); +#endif + +#if ( INCLUDE_CreateBlockTimeTasks == 1 ) + vCreateBlockTimeTasks(); +#endif + +#if ( INCLUDE_CreateSuicidalTasks == 1 ) + vCreateSuicidalTasks( mainDEATH_PRIORITY ); +#endif + +#if ( INCLUDE_TraceListTasks == 1 ) + vTraceListTasks( TASK_UTILITY_PRIORITY ); +#endif + + /* Start the 'Check' task which is defined in this file. */ + xTaskCreate( vErrorChecks, ( signed portCHAR * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + vTaskStartScheduler(); + + /* Should not reach here */ + while (1) + { + __asm(" NOP "); // + } +} + +/*-----------------------------------------------------------*/ +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ + if (uxLED < ledNUMBER_OF_LEDS) + { + vTaskSuspendAll(); + + /* Toggle the state of the single genuine on board LED. */ + if( (sState & ((portCHAR)(1 << uxLED))) == 0) + { + PDR00 |= (1 << uxLED); + sState |= (1 << uxLED); + } + else + { + PDR00 &= ~(1 << uxLED); + sState &= ~(1 << uxLED); + } + + xTaskResumeAll(); + } +} +/*-----------------------------------------------------------*/ +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ + /* Set or clear the output [in this case show or hide the '*' character. */ + if( uxLED < ledNUMBER_OF_LEDS ) + { + vTaskSuspendAll(); + { + if( xValue ) + { + PDR00 |= (1 << uxLED); + sState |= (1 << uxLED); + } + else + { + PDR00 &= ~(1 << uxLED); + sState &= ~(1 << uxLED); + } + } + xTaskResumeAll(); + } +} +/*-----------------------------------------------------------*/ + +static void vErrorChecks( void *pvParameters ) +{ +static volatile unsigned portLONG ulDummyVariable = 3UL; +portTickType xDelayPeriod = mainNO_ERROR_CHECK_DELAY; + + ( void ) pvParameters; + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. */ + for( ;; ) + { + /* Wait until it is time to check again. The time we wait here depends + on whether an error has been detected or not. When an error is + detected the time is shortened resulting in a faster LED flash rate. */ + vTaskDelay( xDelayPeriod ); + + /* Perform a bit of 32bit maths to ensure the registers used by the + integer tasks get some exercise outside of the integer tasks + themselves. The result here is not important we are just deliberately + changing registers used by other tasks to ensure that their context + switch is operating as required. - see the demo application + documentation for more info. */ + ulDummyVariable *= 3UL; + + /* See if the other tasks are all ok. */ + if( prvCheckOtherTasksAreStillRunning() != pdPASS ) + { + /* An error occurred in one of the tasks so shorten the delay + period - which has the effect of increasing the frequency of the + LED toggle. */ + xDelayPeriod = mainERROR_CHECK_DELAY; + } + + /* Flash! */ + vParTestToggleLED(mainCHECK_TEST_LED); + } +} + +/*-----------------------------------------------------------*/ + +static portSHORT prvCheckOtherTasksAreStillRunning( void ) +{ +static portSHORT sNoErrorFound = pdTRUE; + + /* The demo tasks maintain a count that increments every cycle of the task + provided that the task has never encountered an error. This function + checks the counts maintained by the tasks to ensure they are still being + incremented. A count remaining at the same value between calls therefore + indicates that an error has been detected. Only tasks that do not flash + an LED are checked. */ + +#if ( INCLUDE_StartIntegerMathTasks == 1 ) + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + sNoErrorFound = pdFALSE; + } +#endif + + +#if ( INCLUDE_AltStartComTestTasks == 1 ) + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + sNoErrorFound = pdFALSE; + } +#endif + + +#if ( INCLUDE_StartPolledQueueTasks == 1 ) + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + sNoErrorFound = pdFALSE; + } +#endif + + +#if ( INCLUDE_StartSemaphoreTasks == 1 ) + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + sNoErrorFound = pdFALSE; + } +#endif + + +#if ( INCLUDE_StartBlockingQueueTasks == 1 ) + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + sNoErrorFound = pdFALSE; + } +#endif + + +#if ( INCLUDE_StartDynamicPriorityTasks == 1 ) + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + sNoErrorFound = pdFALSE; + } +#endif + + +#if ( INCLUDE_StartMathTasks == 1 ) + if( xAreMathsTaskStillRunning() != pdTRUE ) + { + sNoErrorFound = pdFALSE; + } +#endif + + +#if ( INCLUDE_StartFlashCoRoutines == 1 ) + if( xAreFlashCoRoutinesStillRunning() != pdTRUE ) + { + sNoErrorFound = pdFALSE; + } +#endif + +#if ( INCLUDE_StartHookCoRoutines == 1 ) + if( xAreHookCoRoutinesStillRunning() != pdTRUE ) + { + sNoErrorFound = pdFALSE; + } +#endif + +#if ( INCLUDE_StartGenericQueueTasks == 1 ) + if ( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + sNoErrorFound = pdFALSE; + } +#endif + +#if ( INCLUDE_StartQueuePeekTasks == 1 ) + if ( xAreQueuePeekTasksStillRunning() != pdTRUE ) + { + sNoErrorFound = pdFALSE; + } +#endif + +#if ( INCLUDE_CreateBlockTimeTasks == 1 ) + if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + sNoErrorFound = pdFALSE; + } +#endif + +#if ( INCLUDE_CreateSuicidalTasks == 1 ) + if( xIsCreateTaskStillRunning() != pdTRUE ) + { + sNoErrorFound = pdFALSE; + } +#endif + + return sNoErrorFound; +} + +/*---------------------------------------------------------------------------*/ \ No newline at end of file diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Src/START.ASM b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Src/START.ASM new file mode 100644 index 000000000..edf4db626 --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Src/START.ASM @@ -0,0 +1,1785 @@ +;==================================================================== +; THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. +; FUJITSU MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY +; FOR ANY ERRORS OR ELIGIBILITY FOR ANY PURPOSES. +; +; Startup file for memory and basic controller initialisation +; +; MB96300 Family C Compiler +; +; (C) FUJITSU MICROELECTRONICS EUROPE 1998-2008 +;==================================================================== + + .PROGRAM STARTUP + .TITLE "STARTUP FILE FOR MEMORY INITIALISATION" + +;==================================================================== +; 1 Contents +;==================================================================== +; 1 Contents +; 2 Disclaimer +; 3 History +; +; 4 SETTINGS (USER INTERFACE) +; 4.1 Controller Series +; 4.2 C-language Memory model +; 4.3 Function-Call Interface +; 4.4 Constant Data Handling +; 4.5 Stack Type and Stack Size +; 4.6 General Register Bank +; 4.7 Low-Level Library Interface +; 4.8 Clock Selection +; 4.9 Clock Stabilization Time +; 4.10 External Bus Interface +; 4.11 ROM Mirror configuration +; 4.12 Flash Security +; 4.13 Flash Write Protection +; 4.14 Boot Vector +; 4.15 UART scanning +; 4.16 Enable RAMCODE Copying +; 4.17 Enable information stamp in ROM +; 4.18 Enable Background Debugging Mode +; +; 5 Section and Data Declaration +; 5.1 Several fixed addresses (fixed for MB963xx controllers) +; 5.2 Declaration of __near addressed data sections +; 5.3 Declaration of RAMCODE section and labels +; 5.4 Declaration of sections containing other sections description +; 5.5 Stack area and stack top definition/declaration +; 5.6 Direct page register dummy label definition +; +; 6 Start-Up Code +; 6.1 Import external symbols +; 6.2 Program start (the boot vector should point here) +; 6.3 "NOT RESET YET" WARNING +; 6.4 Initialisation of processor status +; 6.5 Set clock ratio (ignore subclock) +; 6.6 Set external bus configuration +; 6.7 Prepare stacks and set the active stack type +; 6.8 Copy initial values to data areas +; 6.9 Clear uninitialised data areas to zero +; 6.10 Set Data Bank Register (DTB) and Direct Page Register (DPR) +; 6.11 Wait for PLL to stabilise +; 6.12 Initialise Low-Level Library Interface +; 6.13 Call C-language main function +; 6.14 Shut down library +; 6.15 Program end loop +; 6.16 Set Flash Security +; 6.17 Set Flash write protection +; 6.18 Debug address specification +; +;==================================================================== +; 2 Disclaimer +;==================================================================== +; FUJITSU MICROELECTRONICS EUROPE GMBH +; Pittlerstrasse 47, 63225 Langen, Germany +; Tel.:++49 6103 690-0, Fax -122 +; +; The following software is for demonstration purposes only. +; It is not fully tested, nor validated in order to fulfil +; its task under all circumstances. Therefore, this software +; or any part of it must only be used in an evaluation +; laboratory environment. +; This software is subject to the rules of our standard +; DISCLAIMER, that is delivered with our SW-tools on the +; Fujitsu Microcontrollers CD (V3.4 or higher "\START.HTM") or +; on our Internet Pages: +; http://www.fme.gsdc.de/gsdc.htm +; http://emea.fujitsu.com/microelectronics +; +;==================================================================== +; 3 History +;==================================================================== +; $Id: START.ASM,v 1.25 2007/09/28 07:33:18 mcuae Exp $ + +#define VERSION "1.25" +/* +$Log: START.ASM,v $ +Revision 1.25 2007/09/28 07:33:18 mcuae +Bug in BDM baudrate calculation corrected + +Revision 1.24 2007/09/26 14:03:08 mcuae +- Device list for MB96340 series updated and expanded + +Revision 1.23 2007/08/06 14:48:16 mcuae +- BDM section always reserved, filled with 0xFF, if not configured + +Revision 1.22 2007/08/02 08:34:03 mcuae +- communication mode bits of BDM configuration grouped + +Revision 1.21 2007/07/13 08:23:05 mwilla +device selection for BDM baud rate improved + +Revision 1.20 2007/06/12 10:43:57 mwilla +- BDM-Baud-Rate calculation includes crystal frequency + +Revision 1.19 2007/06/06 07:46:55 mwilla +- add Background Debugging Configuration +- Stack initialization moved before variable initialization +- values of cystal frequency and device macros changed + +Revision 1.18 2007/04/16 07:56:02 phuene +- update clock settings when crystal is 8 MHz so that the CLKVCO is low + +Revision 1.17 2007/04/10 11:30:43 phuene +- add MB96320 Series +- Clock settings optimized for CPU_8MHZ_CLKP2_8MHZ, CPU_12MHZ_CLKP2_12MHZ, CPU_16MHZ_CLKP2_16MHZ, CPU_24MHZ_CLKP2_24MHZ, CPU_32MHZ_CLKP2_32MHZ +- make the selection for the individual devices also consider the selected Series +- support 8 MHz crystal +- add clock setting CPU_32MHZ_CLKP1_16MHZ_CLKP2_16MHZ +- prohibit CPU_32MHZ_CLKP2_16MHZ, CPU_CLKP1_16MHZ_CLKP2_16MHZ for MB96F348H and MB96F348T according to functional limitation 16FXFL0014 + +Revision 1.16 2007/02/07 12:38:10 phuene +- support disabling the UART scanning in Internal Vector Mode +- distinguish between Reset Vector and Boot Vector: the Boot Vector points to the start of the user application + +Revision 1.15 2007/02/07 09:00:19 phuene +- add .SKIP instructions to occupy the whole ROM configuration block area + +Revision 1.14 2007/01/29 13:15:06 phuene +- fix CPU_4MHZ_MAIN_CLKP2_4MHZ clock setting + +Revision 1.13 2007/01/03 10:40:14 phuene +- change clock setting CPU_24MHZ_CLKP2_16MHZ to CPU_24MHZ_CLKP2_12MHZ; this allows for better performance of MB96F348H/T +- use additional preprocessor statements to avoid checking for PLL ready twice in some cases + +Revision 1.12 2007/01/02 10:16:20 phuene +- correct CLKP2 (CAN) clock for CPU_32MHZ and MB96F348H/T +- correct CLKP2 (CAN) clock for CPU_24MHZ for all other devices than MB96F348H/T + +Revision 1.11 2006/12/28 10:49:52 phuene +- corrected PLL setting for CPU_16MHZ for MB96348H, MB96348T + +Revision 1.10 2006/12/28 08:41:57 phuene +- correct revision number at new location + +Revision 1.1 2006/12/28 07:20:01 phuene +- new location in CVS + +Revision 1.9 2006/12/27 13:00:45 phuene +- add support for ROM Mirror when using the Simulator +- add support for 16FXFL0022, 16FXFL0023 + +Revision 1.8 2006/12/11 16:43:37 phuene +- fix typo + +Revision 1.7 2006/12/11 16:35:08 phuene +- add setting for Clock Stabilization Times +- modify clock settings: + - CLKP2 < 28 MHz + - remove clock settings using more wait cycles than absolutely required + +Revision 1.6 2006/11/03 13:38:45 phuene +- modify clock settings to also set the Flash Memory Timing +- add support for both parameter passing models + +Revision 1.5 2006/08/07 14:01:44 phuene +- change default clock setting to PLLx4 for CLKS1, CLKS2 +- correct clock setting +- disable Flash Security by default for Main Flash, Satellite Flash +- disable availability of Satellite Flash by default + +Revision 0.1 2006/01/25 15:37:46 phu +- initial version based on start.asm for MB90340 Series, version 3.8 +Revision 0.2 2006/07/14 15:37:46 phu +- include PIER settings for External Bus operation +Revision 0.3 2006/07/14 15:37:46 phu +- add MB96350 Series +- correct PIER settings for HRQ and RDY signals +Revision 0.4 2006/08/07 15:35:35 phu +- change default clock setting to PLLx4 for CLKS1, CLKS2 +- correct clock setting +- disable Flash Security by default for Main Flash, Satellite Flash +- disable availability of Satellite Flash by default +*/ +;==================================================================== + +;==================================================================== +; 4 Settings +;==================================================================== +; +; CHECK ALL OPTIONS WHETHER THEY FIT TO THE APPLICATION +; +; Configure this startup file in the "Settings" section. Search for +; comments with leading "; <<<". This points to the items to be set. +;==================================================================== +#set OFF 0 +#set ON 1 + +;==================================================================== +; 4.1 Controller Series, Device +;==================================================================== + +#set MB96320 0 +#set MB96340 1 +#set MB96350 2 +#set MB96360 3 +#set MB96380 4 + +#set SERIES MB96340 ; <<< select Series + + +; Only if SERIES = MB96340 was selected, please specify the device +; according to the following selection +; Note: Do not change order because of device number dependency in +; 6.5 Clock settings and 6.18 Debug address specification! +#set MB96348HA 1 +#set MB96348TA 2 +#set MB96346RA 3 +#set MB96346YA 4 +#set MB96346AA 5 +#set MB96347RA 6 +#set MB96347YA 7 +#set MB96347AA 8 +#set MB96348RA 9 +#set MB96348YA 10 +#set MB96348AA 11 +#set MB96346RB 12 +#set MB96346AB 13 +#set MB96346YB 14 +#set MB96347RB 15 +#set MB96347AB 16 +#set MB96347YB 17 +#set MB96348CA 18 +#set MB96348HB 19 +#set MB96348TB 20 +#set MB96348RB 21 +#set MB96348AB 22 +#set MB96348YB 23 +#set MB96348CC 24 +#set MB96348HC 25 +#set MB96348TC 26 + +#set DEVICE MB96348HB ; <<< select device if Series = MB96340 + +;==================================================================== +; 4.2 C-language Memory model +;==================================================================== + + ; data code +#set SMALL 0 ; 16 Bit 16 Bit +#set MEDIUM 1 ; 16 Bit 24 Bit +#set COMPACT 2 ; 24 Bit 16 Bit +#set LARGE 3 ; 24 Bit 24 Bit +#set AUTOMODEL 4 ; works always, might occupy two + ; additional bytes + + +#set MEMMODEL AUTOMODEL ; <<< C-memory model + +; The selected memory model should be set in order to fit to the +; model selected for the compiler. +; Note, in this startup version AUTOMODEL will work for all +; C-models. However, if the compiler is configured for SMALL or +; COMPACT, two additional bytes on stack are occupied. If this is not +; acceptable, the above setting should be set to the correct model. + +;==================================================================== +; 4.3 Function-Call Interface +;==================================================================== + #if __REG_PASS__ + .REG_PASS + #endif + +; Above statement informs Assembler on compatibility of start-up code +; to Function Call Interface as selected for the application. There +; is nothing to configure. +; The Function-Call Interface specifies the method of passing parame- +; ter from function caller to callee. The standard method of FCC907S +; compiler uses "stack argument passing". Alternatively, language +; tools can be configured for "register argument passing". +; For details see the compiler manual. +; This start-up file is compatible to both interfaces. + +;==================================================================== +; 4.4 Constant Data Handling +;==================================================================== + +#set ROMCONST 0 ; works only with compiler ROMCONST +#set RAMCONST 1 ; works with BOTH compiler settings +#set AUTOCONST RAMCONST ; works with BOTH compiler settings + +#set CONSTDATA AUTOCONST ; <<< set RAM/ROM/AUTOCONST + +; - AUTOCONST (default) is the same as RAMCONST +; - RAMCONST/AUTOCONST should always work, even if compiler is set to +; ROMCONST. If compiler is set to ROMCONST and this startup file is +; set to RAMCONST or AUTOCONST, this startup file will generate an +; empty section CINIT in RAM. However, the code, which copies from +; CONST to CINIT will not have any effect, because size of section is 0. +; - It is highly recommended to set the compiler to ROMCONST for +; single-chip mode or internal ROM+ext bus. The start-up file +; should be set to AUTOCONST. +; - ROMCONST setting on systems with full external bus requires exter- +; nal address mapping. +; Single-chip can be emulated by the emulator debugger. +; ROM mirror can also be used with simulator. +; +; see also ROM MIRROR options + +;==================================================================== +; 4.5 Stack Type and Stack Size +;==================================================================== + +#set USRSTACK 0 ; user stack: for main program +#set SYSSTACK 1 ; system stack: for main program and interrupts + +#set STACKUSE SYSSTACK ; <<< set active stack + +#set STACK_RESERVE ON ; <<< reserve stack area in this module +#set STACK_SYS_SIZE 1500 ; <<< byte size of System stack +#set STACK_USR_SIZE 2 ; <<< byte size of User stack + +#set STACK_FILL ON ; <<< fills the stack area with pattern +#set STACK_PATTERN 0x55AA ; <<< the pattern to write to stack + +; - If the active stack is set to SYSSTACK, it is used for main program +; and interrupts. In this case, the user stack can be set to a dummy +; size. +; If the active stack is set to user stack, it is used for the main +; program but the system stack is automatically activated, if an inter- +; rupt is serviced. Both stack areas must have a reasonable size. +; - If STACK_RESERVE is ON, the sections USTACK and SSTACK are reserved +; in this module. Otherwise, they have to be reserved in other modules. +; If STACK_RESERVE is OFF, the size definitions STACK_SYS_SIZE and +; STACK_USR_SIZE have no meaning. +; - Even if they are reserved in other modules, they are still initialised +; in this start-up file. +; - Filling the stack with a pattern allows to dynamically check the stack +; area, which had already been used. +; +; - If only system stack is used and SSB is linked to a different bank +; than USB, make sure that all C-modules (which generate far pointers +; to stack data) have "#pragma SSB". Applies only to exclusive confi- +; gurations. +; - Note, several library functions require quite a big stack (due to +; ANSI). Check the stack information files (*.stk) in the LIB\907 +; directory. + +;==================================================================== +; 4.6 General Register Bank +;==================================================================== + +#set REGBANK 0 ; <<< set default register bank + +; set the General Register Bank that is to be used after startup. +; Usually, this is bank 0, which applies to address H'180..H'18F. Set +; in the range from 0 to 31. +; Note: All used register banks have to be reserved (linker options). + +#if REGBANK > 31 || REGBANK < 0 +# error REGBANK setting out of range +#endif + +;==================================================================== +; 4.7 Low-Level Library Interface +;==================================================================== + +#set CLIBINIT OFF ; <<< select extended library usage + +; This option has only to be set, if stream-IO/standard-IO function of +; the C-library have to be used (printf(), fopen()...). This also +; requires low-level functions to be defined by the application +; software. +; For other library functions (like e.g. sprintf()) all this is not +; necessary. However, several functions consume a large amount of stack. + +;==================================================================== +; 4.8 Clock Selection +;==================================================================== + +; The clock selection requires that a 4 MHz external clock is provided +; as the Main Clock. If a different frequency is used, the Flash Memory +; Timing settings must be checked! + +#set CLOCKWAIT ON ; <<< wait for stabilized clock, if + ; Main Clock or PLL is used + +; The clock is set quite early. However, if CLOCKWAIT is ON, polling +; for machine clock to be switched to Main Clock or PLL is done at +; the end of this file. Therefore, the stabilization time is not +; wasted. Main() will finally start at correct speed. Resources can +; be used immediately. +; Note: Some frequency settings (below) necessarily need a stabilized +; PLL for final settings. In these cases, the CLOCKWAIT setting above +; does not have any effect. +; +; This startup file version does not support subclock. + +#set FREQ_4MHZ D'4000000L +#set FREQ_8MHZ D'8000000L + +#set CRYSTAL FREQ_4MHZ ; <<< select external crystal frequency + +#set CPU_4MHZ_MAIN_CLKP2_4MHZ 0x0004 +#set CPU_4MHZ_PLL_CLKP2_4MHZ 0x0104 +#set CPU_8MHZ_CLKP2_8MHZ 0x0108 +#set CPU_12MHZ_CLKP2_12MHZ 0x010C +#set CPU_16MHZ_CLKP2_16MHZ 0x0110 +#set CPU_24MHZ_CLKP2_12MHZ 0x0118 +#set CPU_32MHZ_CLKP2_16MHZ 0x0120 +#set CPU_32MHZ_CLKP1_16MHZ_CLKP2_16MHZ 0x0220 +#set CPU_48MHZ_CLKP2_16MHZ 0x0130 +#set CPU_56MHZ_CLKP2_14MHZ 0x0138 + +#set CLOCK_SPEED CPU_56MHZ_CLKP2_14MHZ ; <<< set clock speeds + +; The peripheral clock CLKP1 is set to the same frequency than the CPU. +; The peripheral clock CLKP2 has its setting. This is because it +; feeds only the CAN controllers and Sound Generators. These do not +; need high frequency clocks. + +;==================================================================== +; 4.9 Clock Stabilization Time +;==================================================================== + +#set MC_2_10_CYCLES 0 +#set MC_2_12_CYCLES 1 +#set MC_2_13_CYCLES 2 +#set MC_2_14_CYCLES 3 +#set MC_2_15_CYCLES 4 +#set MC_2_16_CYCLES 5 +#set MC_2_17_CYCLES 6 +#set MC_2_18_CYCLES 7 + +#set MC_STAB_TIME MC_2_15_CYCLES ; <<< select Main Clock Stabilization Time + +;==================================================================== +; 4.10 External Bus Interface +;==================================================================== + +#set SINGLE_CHIP 0 ; all internal +#set INTROM_EXTBUS 1 ; mask ROM or FLASH memory used +#set EXTROM_EXTBUS 2 ; full external bus (INROM not used) + +#set BUSMODE SINGLE_CHIP ; <<< set bus mode (see mode pins) + +#set MULTIPLEXED 0 ; +#set NON_MULTIPLEXED 1 ; only if supported by the device + +#set ADDRESSMODE MULTIPLEXED ; <<< set address-mode + +; Some devices support multiplexed and/or non-multiplexed Bus mode +; please refer to the related datasheet/hardwaremanual + + +; If BUSMODE is "SINGLE_CHIP", ignore remaining bus settings. + +; Select the used Chip Select areas +#set CHIP_SELECT0 OFF ; <<< enable chip select area +#set CHIP_SELECT1 OFF ; <<< enable chip select area +#set CHIP_SELECT2 OFF ; <<< enable chip select area +#set CHIP_SELECT3 OFF ; <<< enable chip select area +#set CHIP_SELECT4 OFF ; <<< enable chip select area +#set CHIP_SELECT5 OFF ; <<< enable chip select area + +#set HOLD_REQ OFF ; <<< select Hold function +#set EXT_READY OFF ; <<< select external Ready function +#set EXT_CLOCK_ENABLE OFF ; <<< select external bus clock output +#set EXT_CLOCK_INVERT OFF ; <<< select clock inversion +#set EXT_CLOCK_SUSPEND OFF ; <<< select if external clock is suspended when no transfer in progress + +; The external bus clock is derived from core clock CLKB. Select the divider for the external bus clock. + +#set EXT_CLOCK_DIV1 0 +#set EXT_CLOCK_DIV2 1 +#set EXT_CLOCK_DIV4 2 +#set EXT_CLOCK_DIV8 3 +#set EXT_CLOCK_DIV16 4 +#set EXT_CLOCK_DIV32 5 +#set EXT_CLOCK_DIV64 6 +#set EXT_CLOCK_DIV128 7 + +#set EXT_CLOCK_DIVISION EXT_CLOCK_DIV1 ; <<< select clock divider + +#set ADDR_PINS_23_16 B'00000000 ; <<< select used address lines + ; A23..A16 to be output. +#set ADDR_PINS_15_8 B'00000000 ; <<< select used address lines + ; A15..A8 to be output. +#set ADDR_PINS_7_0 B'00000000 ; <<< select used address lines + ; A7..A0 to be output. + +#set LOW_BYTE_SIGNAL OFF ; select low byte signal LBX +#set HIGH_BYTE_SIGNAL OFF ; select high byte signal UBX +#set LOW_WRITE_STROBE OFF ; select write strobe signal WRLX/WRX +#set HIGH_WRITE_STROBE OFF ; select write strobe signal WRHX +#set READ_STROBE OFF ; select read strobe signal RDX +#set ADDRESS_STROBE OFF ; select address strobe signal ALE/ASX +#set ADDRESS_STROBE_LVL OFF ; select address strobe function: OFF - active low; ON - active high + + +#set CS0_CONFIG B'0000000000000000 ; <<< select Chip Select Area 0 configuration +; |||||||||||||+++-- Automatic wait cycles (0: 0, 1: 1, 2: 2, 3: 3, 4: 4, 5: 8, 6: 16, 7: 32) +; ||||||||||||+----- Address Cycle Extension (0: not extended, 1: extension by 1 cycle) +; |||||||||||+------ Strobe timing (0: scheme 0, 1: scheme 1) +; ||||||||||+------- Write strobe function (0: WRLX strobe, 1: WRX strobe) +; |||||||||+-------- Endianess (0: little endian, 1: big endian) +; ||||||||+--------- Bus width (0: 16bit, 1: 8bit) +; |||||+++---------- ignored +; ||||+------------- Chip Select output enable (0: CS disabled, 1: CS enabled) +; |||+-------------- Chip Select level (0: low active, 1: high active) +; ||+--------------- Access type limitation (0: code and data, 1: data only) +; ++---------------- ignored + +#set CS1_CONFIG B'0000000000000000 ; <<< select Chip Select Area 1 configuration +; |||||||||||||+++-- Automatic wait cycles (0: 0, 1: 1, 2: 2, 3: 3, 4: 4, 5: 8, 6: 16, 7: 32) +; ||||||||||||+----- Address Cycle Extension (0: not extended, 1: extension by 1 cycle) +; |||||||||||+------ Strobe timing (0: scheme 0, 1: scheme 1) +; ||||||||||+------- Write strobe function (0: WRLX strobe, 1: WRX strobe) +; |||||||||+-------- Endianess (0: little endian, 1: big endian) +; ||||||||+--------- Bus width (0: 16bit, 1: 8bit) +; |||||+++---------- ignored +; ||||+------------- Chip Select output enable (0: CS disabled, 1: CS enabled) +; |||+-------------- Chip Select level (0: low active, 1: high active) +; ||+--------------- Access type limitation (0: code and data, 1: data only) +; ++---------------- ignored + +#set CS2_CONFIG B'0000011000000000 ; <<< select Chip Select Area 2 configuration +; |||||||||||||+++-- Automatic wait cycles (0: 0, 1: 1, 2: 2, 3: 3, 4: 4, 5: 8, 6: 16, 7: 32) +; ||||||||||||+----- Address Cycle Extension (0: not extended, 1: extension by 1 cycle) +; |||||||||||+------ Strobe timing (0: scheme 0, 1: scheme 1) +; ||||||||||+------- Write strobe function (0: WRLX strobe, 1: WRX strobe) +; |||||||||+-------- Endianess (0: little endian, 1: big endian) +; ||||||||+--------- Bus width (0: 16bit, 1: 8bit) +; |||||+++---------- External area size (0: 64kB, 1: 128kB, 2: 256kB, 3: 512kB, 4: 1MB, 5: 2MB, 6: 4MB, 7: 8MB) +; ||||+------------- Chip Select output enable (0: CS disabled, 1: CS enabled) +; |||+-------------- Chip Select level (0: low active, 1: high active) +; ||+--------------- Access type limitation (0: code and data, 1: data only) +; ++---------------- ignored + +#set CS3_CONFIG B'0000011000000000 ; <<< select Chip Select Area 3 configuration +; |||||||||||||+++-- Automatic wait cycles (0: 0, 1: 1, 2: 2, 3: 3, 4: 4, 5: 8, 6: 16, 7: 32) +; ||||||||||||+----- Address Cycle Extension (0: not extended, 1: extension by 1 cycle) +; |||||||||||+------ Strobe timing (0: scheme 0, 1: scheme 1) +; ||||||||||+------- Write strobe function (0: WRLX strobe, 1: WRX strobe) +; |||||||||+-------- Endianess (0: little endian, 1: big endian) +; ||||||||+--------- Bus width (0: 16bit, 1: 8bit) +; |||||+++---------- External area size (0: 64kB, 1: 128kB, 2: 256kB, 3: 512kB, 4: 1MB, 5: 2MB, 6: 4MB, 7: 8MB) +; ||||+------------- Chip Select output enable (0: CS disabled, 1: CS enabled) +; |||+-------------- Chip Select level (0: low active, 1: high active) +; ||+--------------- Access type limitation (0: code and data, 1: data only) +; ++---------------- ignored + +#set CS4_CONFIG B'0000011000000000 ; <<< select Chip Select Area 4 configuration +; |||||||||||||+++-- Automatic wait cycles (0: 0, 1: 1, 2: 2, 3: 3, 4: 4, 5: 8, 6: 16, 7: 32) +; ||||||||||||+----- Address Cycle Extension (0: not extended, 1: extension by 1 cycle) +; |||||||||||+------ Strobe timing (0: scheme 0, 1: scheme 1) +; ||||||||||+------- Write strobe function (0: WRLX strobe, 1: WRX strobe) +; |||||||||+-------- Endianess (0: little endian, 1: big endian) +; ||||||||+--------- Bus width (0: 16bit, 1: 8bit) +; |||||+++---------- External area size (0: 64kB, 1: 128kB, 2: 256kB, 3: 512kB, 4: 1MB, 5: 2MB, 6: 4MB, 7: 8MB) +; ||||+------------- Chip Select output enable (0: CS disabled, 1: CS enabled) +; |||+-------------- Chip Select level (0: low active, 1: high active) +; ||+--------------- Access type limitation (0: code and data, 1: data only) +; ++---------------- ignored + +#set CS5_CONFIG B'0000011000000000 ; <<< select Chip Select Area 5 configuration +; |||||||||||||+++-- Automatic wait cycles (0: 0, 1: 1, 2: 2, 3: 3, 4: 4, 5: 8, 6: 16, 7: 32) +; ||||||||||||+----- Address Cycle Extension (0: not extended, 1: extension by 1 cycle) +; |||||||||||+------ Strobe timing (0: scheme 0, 1: scheme 1) +; ||||||||||+------- Write strobe function (0: WRLX strobe, 1: WRX strobe) +; |||||||||+-------- Endianess (0: little endian, 1: big endian) +; ||||||||+--------- Bus width (0: 16bit, 1: 8bit) +; |||||+++---------- External area size (0: 64kB, 1: 128kB, 2: 256kB, 3: 512kB, 4: 1MB, 5: 2MB, 6: 4MB, 7: 8MB) +; ||||+------------- Chip Select output enable (0: CS disabled, 1: CS enabled) +; |||+-------------- Chip Select level (0: low active, 1: high active) +; ||+--------------- Access type limitation (0: code and data, 1: data only) +; ++---------------- ignored + + +#set CS2_START 0x00 ; select start bank of chip select area; valid values: 0x00..0xFF +#set CS3_START 0x40 ; select start bank of chip select area; valid values: 0x00..0xFF +#set CS4_START 0x80 ; select start bank of chip select area; valid values: 0x00..0xFF +#set CS5_START 0xC0 ; select start bank of chip select area; valid values: 0x00..0xFF + + +;==================================================================== +; 4.11 ROM Mirror configuration +;==================================================================== + +#set MIRROR_8KB 0 +#set MIRROR_16KB 1 +#set MIRROR_24KB 2 +#set MIRROR_32KB 3 + +#set ROMMIRROR ON ; <<< ROM mirror function ON/OFF +#set MIRROR_BANK 0xF ; <<< ROM Mirror bank, allowed entries: 0x0..0xF for the banks 0xF0..0xFF +#set MIRROR_SIZE MIRROR_32KB ; <<< ROM Mirror size + +; One can select which ROM area to mirror into the upper half of bank 00. +; If ROMMIRROR = OFF is selected, the address range 0x008000..0x00FFFF +; shows the contents of the respective area of bank 1: 0x018000..0x01FFFF. +; If ROMMIRROR = ON is selected, the memory bank to mirror can be selected. +; Available banks are 0xF0 to 0xFF. Furthermore, the ROM Mirror area size can +; be selected. 4 sizes are available: 8 kB, 16 kB, 24 kB, or 32 kB. The ROM Mirror +; from the highest address of the selected bank downwards, e.g. if bank 0xFF and +; mirror size 24 kB is selected, the memory range 0xFFA000..0xFFFFFF is mirrored +; to address range 0x00A000..0x00FFFF. The memory area not selected for +; ROM Mirror is still mirrored from bank 0x01. +; This is necessary to get the compiler ROMCONST option working. This is intended +; to increase performance, if a lot of dynamic data have to be accessed. +; In SMALL and MEDIUM model these data can be accessed within bank 0, +; which allows to use near addressing. Please make sure to have the linker +; setting adjusted accordingly! + + +;==================================================================== +; 4.12 Flash Security +;==================================================================== + +#set MAIN_SECURITY_ENABLE OFF ; <<< enable Flash Security for Main Flash +#set SATELLITE_FLASH OFF ; <<< select if Satellite Flash is available +#set SATELLITE_SECURITY_ENABLE OFF ; <<< enable Flash Security for Satellite Flash + +; set the Flash Security unlock key (16 bytes) +; all 0: unlock not possible +#set MAIN_UNLOCK_0 0x00 +#set MAIN_UNLOCK_1 0x00 +#set MAIN_UNLOCK_2 0x00 +#set MAIN_UNLOCK_3 0x00 +#set MAIN_UNLOCK_4 0x00 +#set MAIN_UNLOCK_5 0x00 +#set MAIN_UNLOCK_6 0x00 +#set MAIN_UNLOCK_7 0x00 +#set MAIN_UNLOCK_8 0x00 +#set MAIN_UNLOCK_9 0x00 +#set MAIN_UNLOCK_10 0x00 +#set MAIN_UNLOCK_11 0x00 +#set MAIN_UNLOCK_12 0x00 +#set MAIN_UNLOCK_13 0x00 +#set MAIN_UNLOCK_14 0x00 +#set MAIN_UNLOCK_15 0x00 + +#set SATELLITE_UNLOCK_0 0x00 +#set SATELLITE_UNLOCK_1 0x00 +#set SATELLITE_UNLOCK_2 0x00 +#set SATELLITE_UNLOCK_3 0x00 +#set SATELLITE_UNLOCK_4 0x00 +#set SATELLITE_UNLOCK_5 0x00 +#set SATELLITE_UNLOCK_6 0x00 +#set SATELLITE_UNLOCK_7 0x00 +#set SATELLITE_UNLOCK_8 0x00 +#set SATELLITE_UNLOCK_9 0x00 +#set SATELLITE_UNLOCK_10 0x00 +#set SATELLITE_UNLOCK_11 0x00 +#set SATELLITE_UNLOCK_12 0x00 +#set SATELLITE_UNLOCK_13 0x00 +#set SATELLITE_UNLOCK_14 0x00 +#set SATELLITE_UNLOCK_15 0x00 + + +;==================================================================== +; 4.13 Flash Write Protection +;==================================================================== + +#set MAIN_FLASH_WRITE_PROTECT OFF ; <<< select Flash write protection +#set PROTECT_SECTOR_SA0 OFF ; <<< select individual sector to protect +#set PROTECT_SECTOR_SA1 OFF ; <<< select individual sector to protect +#set PROTECT_SECTOR_SA2 OFF ; <<< select individual sector to protect +#set PROTECT_SECTOR_SA3 OFF ; <<< select individual sector to protect +#set PROTECT_SECTOR_SA32 OFF ; <<< select individual sector to protect +#set PROTECT_SECTOR_SA33 OFF ; <<< select individual sector to protect +#set PROTECT_SECTOR_SA34 OFF ; <<< select individual sector to protect +#set PROTECT_SECTOR_SA35 OFF ; <<< select individual sector to protect +#set PROTECT_SECTOR_SA36 OFF ; <<< select individual sector to protect +#set PROTECT_SECTOR_SA37 OFF ; <<< select individual sector to protect +#set PROTECT_SECTOR_SA38 OFF ; <<< select individual sector to protect +#set PROTECT_SECTOR_SA39 OFF ; <<< select individual sector to protect + +#set SATELLITE_FLASH_WRITE_PROTECT OFF ; <<< select Flash write protection +#set PROTECT_SECTOR_SB0 OFF ; <<< select individual sector to protect +#set PROTECT_SECTOR_SB1 OFF ; <<< select individual sector to protect +#set PROTECT_SECTOR_SB2 OFF ; <<< select individual sector to protect +#set PROTECT_SECTOR_SB3 OFF ; <<< select individual sector to protect + + +;==================================================================== +; 4.14 Boot Vector +;==================================================================== + +#set BOOT_VECTOR_TABLE 1 ; enable boot vector +#set BOOT_VECTOR_FIXED 2 ; enable boot vector + +#set BOOT_VECTOR BOOT_VECTOR_TABLE ; <<< select type of boot vector + +; If boot vector generation is enabled (BOOT_VECTOR_TABLE, BOOT_VECTOR_FIXED), +; appropriate code is generated. If it is disabled (OFF), start-up file does +; not care about. +; +; BOOT_VECTOR_TABLE: - Create table entry at address oxFFFFDC. +; - Any start address can be set and start-up file will +; set address of this start code. +; BOOT_VECTOR_FIXED: - Instead of table entry, a special marker is set in +; ROM Configuration Block, which enables the fixed +; start address 0xDF0080. This is prefered setting +; for user boot loaders. +; OFF: - Do not set table entry and marker. This might be used +; for application to be loaded by boot loader. +; +; Note +; BOOT_VECTOR_TABLE setting can also be used, if all other interrupt vectors +; are specified via "pragma intvect". Only if interrupts 0..7 are specified +; via "pragma intvect", these will conflict with the vector in this module. +; The reason is the INTVECT section, which includes the whole area from the +; lowest to the highest specified vector. + +#if BOOT_VECTOR == BOOT_VECTOR_TABLE + .SECTION RESVECT, CONST, LOCATE=H'FFFFDC + .DATA.E _start + .SECTION BOOT_SELECT, CONST, LOCATE=H'DF0030 + .DATA.L 0xFFFFFFFF + +#else +# if BOOT_VECTOR == BOOT_VECTOR_FIXED + .SECTION BOOT_SELECT, CONST, LOCATE=H'DF0030 + .DATA.L 0x292D3A7B ; Magic Word +# else + .SECTION BOOT_SELECT, CONST, LOCATE=H'DF0030 + .SKIP 4 +# endif +#endif + +;==================================================================== +; 4.15 UART scanning +;==================================================================== + +#set UART_SCANNING OFF ; <<< enable UART scanning in + ; Internal Vector Mode +; +; By default, the MCU scans in Internal Vector Mode for a UART +; communication after reset. This enables to establish a serial +; communication without switching to Serial Communication Mode. +; For the final aplpication, sset this switch to OFF to achieve the +; fastest start-up time. + +#if UART_SCANNING == ON + .SECTION UART_SCAN_SELECT, CONST, LOCATE=H'DF0034 + .DATA.L 0xFFFFFFFF +#else + .SECTION UART_SCAN_SELECT, CONST, LOCATE=H'DF0034 + .DATA.L 0x292D3A7B +#endif + .SKIP 0x08 + + +;==================================================================== +; 4.16 Enable RAMCODE Copying +;==================================================================== + +#set COPY_RAMCODE OFF ; <<< enable RAMCODE section to + ; be copied from ROM to RAM + +; To get this option properly working the code to be executed has to +; be linked to section RAMCODE (e.g. by #pragma section). The section +; RAMCODE has be located in RAM and the section @RAMCODE has to be +; located at a fixed address in ROM by linker settings. + +;==================================================================== +; 4.17 Enable information stamp in ROM +;==================================================================== + +#set VERSION_STAMP OFF ; <<< enable version number in + ; separated section + + +#if VERSION_STAMP == ON + .SECTION VERSIONS, CONST ; change name, if necessary + .SDATA "Start ", VERSION, "\n\0" +#endif + +;==================================================================== +; 4.18 Enable Background Debugging Mode +;==================================================================== + +#set BACKGROUND_DEBUGGING OFF ; <<< enable Background Debugging + ; mode + +#set BDM_CONFIGURATION B'0000000000010000 ; <<< set BDM configuration +; ||||||||++--- BdmUART +; |||||||| (0: A, 1: B, 2: C, 3: D) +; ||||||++----- BdmSynchMode +; |||||| (0: Async., 1: Sync. +; |||||| 2: BdmKLine, 3: res.) +; |||||+------- BdmAutoStart +; ||||+-------- BdmExtBreakpointCfg +; |||+--------- BdmKeepRClock +; ||+---------- BdmCaliRClock +; |+----------- BdmKeepBCD +; +------------ BdmUserKernel + +#set BDM_BAUDRATE 115200 ; <<< set Baudrate in Bits/s for BDM + +#set BDM_EXT_CONFIG 0xFFFFFF ; <<< set external Config/Kernel + +#set BDM_WD_PATTERN 0x00 ; <<< set watchdog pattern + +#set BDM_PFCS0 0x0000 ; <<< set default breakpoint +#set BDM_PFCS1 0x0000 ; configurations +#set BDM_PFCS2 0x0000 +#set BDM_PFCS3 0x0000 + +#set BDM_PFA0 0xFFFFFF ; <<< set address +#set BDM_PFA1 0xFFFFFF ; configurations +#set BDM_PFA2 0xFFFFFF +#set BDM_PFA3 0xFFFFFF +#set BDM_PFA4 0xFFFFFF +#set BDM_PFA5 0xFFFFFF +#set BDM_PFA6 0xFFFFFF +#set BDM_PFA7 0xFFFFFF + +#set BDM_PFD0 0xFFFFFF ; <<< set patch data +#set BDM_PFD1 0xFFFFFF ; configurations +#set BDM_PFD2 0xFFFFFF +#set BDM_PFD3 0xFFFFFF +#set BDM_PFD4 0xFFFFFF +#set BDM_PFD5 0xFFFFFF +#set BDM_PFD6 0xFFFFFF +#set BDM_PFD7 0xFFFFFF + + +; <<< END OF SETTINGS >>> + +;==================================================================== +; 5 Section and Data Declaration +;==================================================================== + +;==================================================================== +; 5.1 Several fixed addresses (fixed for MB963xx controllers) +;==================================================================== + +MFMCS .EQU 0x03F1 ; Main Flash Memory configuration register +MFMTC .EQU 0x03F2 ; Main Flash Memory timing register +SFMCS .EQU 0x03F5 ; Satellite Flash Memory configuration register +SFMTC .EQU 0x03F6 ; Satellite Flash Memory timing register +ROMM .EQU 0x03AE ; ROM mirror control register +CKSR .EQU 0x0401 ; Clock select control register +CKSSR .EQU 0x0402 ; Clock stabilization select register +CKMR .EQU 0x0403 ; Clock monitor register +CKFCR .EQU 0x0404 ; Clock frequency control register +PLLCR .EQU 0x0406 ; PLL control register +VRCR .EQU 0x042C ; Voltage Regulator Control register +#if BUSMODE != SINGLE_CHIP ; only for devices with external bus +PIER00 .EQU 0x0444 +PIER01 .EQU 0x0445 +PIER02 .EQU 0x0446 +PIER03 .EQU 0x0447 +PIER12 .EQU 0x0450 +EACL0 .EQU 0x06E0 +EACH0 .EQU 0x06E1 +EACL1 .EQU 0x06E2 +EACH1 .EQU 0x06E3 +EACL2 .EQU 0x06E4 +EACH2 .EQU 0x06E5 +EACL3 .EQU 0x06E6 +EACH3 .EQU 0x06E7 +EACL4 .EQU 0x06E8 +EACH4 .EQU 0x06E9 +EACL5 .EQU 0x06EA +EACH5 .EQU 0x06EB +EAS2 .EQU 0x06EC +EAS3 .EQU 0x06ED +EAS4 .EQU 0x06EE +EAS5 .EQU 0x06EF +EBM .EQU 0x06F0 +EBCF .EQU 0x06F1 +EBAE0 .EQU 0x06F2 +EBAE1 .EQU 0x06F3 +EBAE2 .EQU 0x06F4 +EBCS .EQU 0x06F5 +#endif ; BUSMODE != SINGLE_CHIP + +;==================================================================== +; 5.2 Declaration of __near addressed data sections +;==================================================================== + +; sections to be cleared + .SECTION DATA, DATA, ALIGN=2 ; zero clear area + .SECTION DATA2, DATA, ALIGN=2 ; zero clear area + .SECTION DIRDATA, DIR, ALIGN=2 ; zero clear direct + .SECTION LIBDATA, DATA, ALIGN=2 ; zero clear lib area + +; sections to be initialised with start-up values + .SECTION INIT, DATA, ALIGN=2 ; initialised area + .SECTION INIT2, DATA, ALIGN=2 ; initialised area + .SECTION DIRINIT, DIR, ALIGN=2 ; initialised dir + .SECTION LIBINIT, DATA, ALIGN=2 ; initialised lib area +#if CONSTDATA == RAMCONST + .SECTION CINIT, DATA, ALIGN=2 ; initialised const + .SECTION CINIT2, DATA, ALIGN=2 ; initialised const +#endif + +; sections containing start-up values for initialised sections above + .SECTION DCONST, CONST, ALIGN=2 ; DINIT initialisers + .SECTION DIRCONST, DIRCONST,ALIGN=2 ; DIRINIT initialisers + .SECTION LIBDCONST, CONST, ALIGN=2 ; LIBDCONST init val + + ; following section is either copied to CINIT (RAMCONST) or + ; mapped by ROM-mirror function (ROMCONST) + .SECTION CONST, CONST, ALIGN=2 ; CINIT initialisers + .SECTION CONST2, CONST, ALIGN=2 ; CINIT initialisers + +;==================================================================== +; 5.3 Declaration of RAMCODE section and labels +;==================================================================== + +#if COPY_RAMCODE == ON + .SECTION RAMCODE, CODE, ALIGN=1 + .IMPORT _RAM_RAMCODE ; provided by linker + .IMPORT _ROM_RAMCODE ; provided by linker +#endif + + +;==================================================================== +; 5.4 Declaration of sections containing other sections description +;==================================================================== + +; DCLEAR contains start address and size of all sections to be cleared +; DTRANS contains source and destination address and size of all +; sections to be initialised with start-up values +; The compiler automatically adds a descriptor for each __far addressed +; data section to DCLEAR or DTRANS. These __far sections are separated +; for each C-module. + +; In addition the start-up file adds the descriptors of the previously +; declared __near section here. This way the same code in the start-up +; file can be used for initialising all sections. + + .SECTION DCLEAR, CONST, ALIGN=2 ; zero clear table + ; Address Bank Size + .DATA.H DATA, BNKSEC DATA, SIZEOF(DATA ) + .DATA.H DIRDATA, BNKSEC DIRDATA, SIZEOF(DIRDATA) + .DATA.H LIBDATA, BNKSEC LIBDATA, SIZEOF(LIBDATA) + + .SECTION DTRANS, CONST, ALIGN=2 ; copy table + ; Address Bank Address Bank Size + .DATA.H DCONST, BNKSEC DCONST, INIT, BNKSEC INIT, SIZEOF INIT + .DATA.H DIRCONST, BNKSEC DIRCONST, DIRINIT,BNKSEC DIRINIT,SIZEOF DIRINIT + .DATA.H LIBDCONST,BNKSEC LIBDCONST,LIBINIT,BNKSEC LIBINIT,SIZEOF LIBINIT + +#if CONSTDATA == RAMCONST + .DATA.H CONST, BNKSEC CONST, CINIT, BNKSEC CINIT, SIZEOF CINIT + .DATA.H CONST2, BNKSEC CONST, CINIT2, BNKSEC CINIT2, SIZEOF CINIT2 +#endif + +#if COPY_RAMCODE == ON + .DATA.L _ROM_RAMCODE, _RAM_RAMCODE + .DATA.H SIZEOF RAMCODE +#endif + +;==================================================================== +; 5.5 Stack area and stack top definition/declaration +;==================================================================== +#if STACK_RESERVE == ON + .SECTION SSTACK, STACK, ALIGN=2 + + .EXPORT __systemstack, __systemstack_top +__systemstack: + .RES.B (STACK_SYS_SIZE + 1) & 0xFFFE +__systemstack_top: +SSTACK_TOP: + + .SECTION USTACK, STACK, ALIGN=2 + + .EXPORT __userstack, __userstack_top +__userstack: + .RES.B (STACK_USR_SIZE + 1) & 0xFFFE +__userstack_top: +USTACK_TOP: + +#else + .SECTION SSTACK, STACK, ALIGN=2 + .SECTION USTACK, STACK, ALIGN=2 + + .IMPORT __systemstack, __systemstack_top + .IMPORT __userstack, __userstack_top +#endif + +;==================================================================== +; 5.6 Direct page register dummy label definition +;==================================================================== + + .SECTION DIRDATA ; zero clear direct +DIRDATA_S: ; label for DPR init + +; This label is used to get the page of the __direct data. +; Depending on the linkage order of this startup file the label is +; placed anywhere within the __direct data page. However, the +; statement "PAGE (DIRDATA_S)" is processed. Therefore, the lower +; 8 Bit of the address of DIRDATA_S are not relevant and this feature +; becomes linkage order independent. +; Note, the linker settings have to make sure that all __direct +; data are located within the same physical page (256 Byte block). + +;==================================================================== +; 6 Start-Up Code +;==================================================================== + +;==================================================================== +; 6.1 Import external symbols +;==================================================================== + + .IMPORT _main ; user code entrance +#if CLIBINIT == ON + .IMPORT __stream_init + .IMPORT _exit + .EXPORT __exit +#endif + .EXPORT _start + +;==================================================================== +; ___ _____ __ ___ _____ +; / | / \ | \ | +; \___ | | | |___/ | +; \ | |----| | \ | +; ___/ | | | | \ | Begin of actual code section +;==================================================================== + .SECTION CODE_START, CODE, ALIGN=1 + +;==================================================================== +; 6.2 Program start (the reset vector should point here) +;==================================================================== +_start: + NOP ; This NOP is only for debugging. On debugger the IP + ; (instruction pointer) should point here after reset + +;==================================================================== +; 6.3 "NOT RESET YET" WARNING +;==================================================================== +notresetyet: + NOP ; read hint below!!!!!!! +; If the debugger stays at this NOP after download, the controller has +; not been reset yet. In order to reset all hardware registers it is +; highly recommended to reset the controller. +; However, if no reset vector has been defined on purpose, this start +; address can also be used. +; This mechanism is using the .END instruction at the end of this mo- +; dule. It is not necessary for controller operation but improves +; security during debugging (mainly emulator debugger). +; If the debugger stays here after a single step from label "_start" +; to label "notresetyet", this note can be ignored. + +;==================================================================== +; 6.4 Initialisation of processor status +;==================================================================== + AND CCR, #0x80 ; disable interrupts + MOV ILM,#7 ; set interrupt level mask to ALL + MOV RP,#REGBANK ; set register bank pointer + +;==================================================================== +; 6.5 Set clock ratio (ignore subclock) +;==================================================================== + MOVN A, #0 ; set bank 0 in DTB for the case that + MOV DTB, A ; start-up code was not jumped by reset + + MOV CKSSR, #(0xF8 | MC_STAB_TIME) ; set clock stabilization time + +#if (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_4MHZ_MAIN_CLKP2_4MHZ) + MOV CKSR, #0xB5 +#endif ; (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_4MHZ_MAIN_CLKP2_4MHZ) + +#if (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_4MHZ_MAIN_CLKP2_4MHZ) + CLRB MFMCS:4 + CLRB MFMCS:5 + CLRB SFMCS:4 + CLRB SFMCS:5 + MOVW CKFCR, #0x1111 + MOV CKSR, #0xB5 +#endif ; (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_4MHZ_MAIN_CLKP2_4MHZ) + +#if (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_4MHZ_PLL_CLKP2_4MHZ) +# if ((SERIES == MB96340) && (DEVICE < 3)) + MOVW PLLCR, #0x00E0 + MOV CKSR, #0xFA +# else + MOVW PLLCR, #0x00A1 + MOVW CKFCR, #0x1111 + MOVW MFMTC, #0x2128 +# if SATELLITE_FLASH == ON + MOVW SFMTC, #0x2128 +# endif ; SATELLITE_FLASH == ON + MOV CKSR, #0xFA +# endif ; ((SERIES == MB96340) && (DEVICE < 3)) +#endif ; (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_4MHZ_PLL_CLKP2_4MHZ) + +#if (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_4MHZ_PLL_CLKP2_4MHZ) +# if ((SERIES == MB96340) && (DEVICE < 3)) + MOVW PLLCR, #0x0060 + CLRB MFMCS:4 + CLRB MFMCS:5 + CLRB SFMCS:4 + CLRB SFMCS:5 + MOVW CKFCR, #0x1111 + MOV CKSR, #0xFA +# else + MOVW PLLCR, #0x0060 + MOVW CKFCR, #0x1111 + MOVW MFMTC, #0x2128 +# if SATELLITE_FLASH == ON + MOVW SFMTC, #0x2128 +# endif ; SATELLITE_FLASH == ON + MOV CKSR, #0xFA +# endif ; ((SERIES == MB96340) && (DEVICE < 3)) +#endif ; (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_4MHZ_PLL_CLKP2_4MHZ) + +#if (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_8MHZ_CLKP2_8MHZ) +# if ((SERIES == MB96340) && (DEVICE < 3)) + MOVW PLLCR, #0x00A1 + MOV CKSR, #0xFA +# else + MOVW PLLCR, #0x0043 + MOVW CKFCR, #0x1111 + MOVW MFMTC, #0x2128 +# if SATELLITE_FLASH == ON + MOVW SFMTC, #0x2128 +# endif ; SATELLITE_FLASH == ON + MOV CKSR, #0xFA +# endif ; ((SERIES == MB96340) && (DEVICE < 3)) +#endif ; (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_8MHZ_CLKP2_8MHZ) + +#if (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_8MHZ_CLKP2_8MHZ) +# if ((SERIES == MB96340) && (DEVICE < 3)) + MOVW PLLCR, #0x0060 + MOV CKSR, #0xFA +# else + MOVW PLLCR, #0x0081 + MOVW CKFCR, #0x1111 + MOVW MFMTC, #0x2128 +# if SATELLITE_FLASH == ON + MOVW SFMTC, #0x2128 +# endif ; SATELLITE_FLASH == ON + MOV CKSR, #0xFA +# endif ; ((SERIES == MB96340) && (DEVICE < 3)) +#endif ; (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_8MHZ_CLKP2_8MHZ) + +#if (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_12MHZ_CLKP2_12MHZ) +# if ((SERIES == MB96340) && (DEVICE < 3)) + MOVW PLLCR, #0x0062 + MOV CKSR, #0xFA +# else + MOVW PLLCR, #0x0025 + MOVW CKFCR, #0x1111 + MOVW MFMTC, #0x2128 +# if SATELLITE_FLASH == ON + MOVW SFMTC, #0x2128 +# endif ; SATELLITE_FLASH == ON + MOV CKSR, #0xFA +# endif ; ((SERIES == MB96340) && (DEVICE < 3)) +#endif ; (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_12MHZ_CLKP2_12MHZ) + +#if (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_12MHZ_CLKP2_12MHZ) +# if ((SERIES == MB96340) && (DEVICE < 3)) + MOVW PLLCR, #0x0082 + CLRB MFMCS:4 + CLRB MFMCS:5 + CLRB SFMCS:4 + CLRB SFMCS:5 + MOVW CKFCR, #0x1111 + MOV CKSR, #0xFA +# else + MOVW PLLCR, #0x0082 + MOVW CKFCR, #0x1111 + MOVW MFMTC, #0x2128 +# if SATELLITE_FLASH == ON + MOVW SFMTC, #0x2128 +# endif ; SATELLITE_FLASH == ON + MOV CKSR, #0xFA +# endif ; ((SERIES == MB96340) && (DEVICE < 3)) +#endif ; (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_12MHZ_CLKP2_12MHZ) + +#if (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_16MHZ_CLKP2_16MHZ) +# if ((SERIES == MB96340) && (DEVICE < 3)) + MOVW PLLCR, #0x0043 + MOV CKSR, #0xFA +# else + MOVW PLLCR, #0x0027 + MOVW CKFCR, #0x1111 + MOVW MFMTC, #0x2279 +# if SATELLITE_FLASH == ON + MOVW SFMTC, #0x2279 +# endif ; SATELLITE_FLASH == ON + MOV CKSR, #0xFA +# endif ; ((SERIES == MB96340) && (DEVICE < 3)) +#endif ; (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_16MHZ_CLKP2_16MHZ) + +#if (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_16MHZ_CLKP2_16MHZ) +# if ((SERIES == MB96340) && (DEVICE < 3)) + MOVW PLLCR, #0x0081 + MOV CKSR, #0xFA +# else + MOVW PLLCR, #0x0003 + MOVW CKFCR, #0x1111 + MOVW MFMTC, #0x2279 +# if SATELLITE_FLASH == ON + MOVW SFMTC, #0x2279 +# endif ; SATELLITE_FLASH == ON + MOV CKSR, #0xFA +# endif ; ((SERIES == MB96340) && (DEVICE < 3)) +#endif ; (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_16MHZ_CLKP2_16MHZ) + +#if (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_24MHZ_CLKP2_12MHZ) +# if ((SERIES == MB96340) && (DEVICE < 3)) + MOVW PLLCR, #0x0025 + MOVW CKFCR, #0x1001 + MOV CKSR, #0xFA +# else + MOVW PLLCR, #0x000B + MOVW CKFCR, #0x3111 + MOVW MFMTC, #0x4C09 +# if SATELLITE_FLASH == ON + MOVW SFMTC, #0x4C09 +# endif ; SATELLITE_FLASH == ON + MOV CKSR, #0xFA +# endif ; ((SERIES == MB96340) && (DEVICE < 3)) +#endif ; (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_24MHZ_CLKP2_12MHZ) + +#if (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_24MHZ_CLKP2_12MHZ) +# if ((SERIES == MB96340) && (DEVICE < 3)) + MOVW PLLCR, #0x0082 + MOVW CKFCR, #0x1001 + MOV CKSR, #0xFA +# else + MOVW PLLCR, #0x0005 + MOVW CKFCR, #0x3111 + MOVW MFMTC, #0x4C09 +# if SATELLITE_FLASH == ON + MOVW SFMTC, #0x4C09 +# endif ; SATELLITE_FLASH == ON + MOV CKSR, #0xFA +# endif ; ((SERIES == MB96340) && (DEVICE < 3)) +#endif ; (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_24MHZ_CLKP2_12MHZ) + +#if (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_32MHZ_CLKP2_16MHZ) +# if ((SERIES == MB96340) && (DEVICE < 3)) +# error Setting prohibited due to 16FXFL0014 +# else + MOVW PLLCR, #0x000F + MOVW CKFCR, #0x3111 + MOVW MFMTC, #0x4C09 +# if SATELLITE_FLASH == ON + MOVW SFMTC, #0x4C09 +# endif ; SATELLITE_FLASH == ON + MOV CKSR, #0xFA +# endif ; ((SERIES == MB96340) && (DEVICE < 3)) +#endif ; (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_32MHZ_CLKP2_16MHZ) + +#if (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_32MHZ_CLKP2_16MHZ) +# if ((SERIES == MB96340) && (DEVICE < 3)) +# error Setting prohibited due to 16FXFL0014 +# else + MOVW PLLCR, #0x0007 + MOVW CKFCR, #0x3111 + MOVW MFMTC, #0x4C09 +# if SATELLITE_FLASH == ON + MOVW SFMTC, #0x4C09 +# endif ; SATELLITE_FLASH == ON + MOV CKSR, #0xFA +# endif ; ((SERIES == MB96340) && (DEVICE < 3)) +#endif ; (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_32MHZ_CLKP2_16MHZ) + +#if (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_32MHZ_CLKP1_16MHZ_CLKP2_16MHZ) +# if ((SERIES == MB96340) && (DEVICE < 3)) +# error Setting prohibited due to 16FXFL0014 +# else + MOVW PLLCR, #0x000F + MOVW CKFCR, #0x3311 + MOVW MFMTC, #0x4C09 +# if SATELLITE_FLASH == ON + MOVW SFMTC, #0x4C09 +# endif ; SATELLITE_FLASH == ON + MOV CKSR, #0xFA +# endif ; ((SERIES == MB96340) && (DEVICE < 3)) +#endif ; (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_32MHZ_CLKP1_16MHZ_CLKP2_16MHZ) + +#if (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_32MHZ_CLKP1_16MHZ_CLKP2_16MHZ) +# if ((SERIES == MB96340) && (DEVICE < 3)) +# error Setting prohibited due to 16FXFL0014 +# else + MOVW PLLCR, #0x0007 + MOVW CKFCR, #0x3311 + MOVW MFMTC, #0x4C09 +# if SATELLITE_FLASH == ON + MOVW SFMTC, #0x4C09 +# endif ; SATELLITE_FLASH == ON + MOV CKSR, #0xFA +# endif ; ((SERIES == MB96340) && (DEVICE < 3)) +#endif ; (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_32MHZ_CLKP1_16MHZ_CLKP2_16MHZ) + +#if (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_48MHZ_CLKP2_16MHZ) + MOVW PLLCR, #0x000B + MOVW CKFCR, #0x2001 + MOVW MFMTC, #0x223A +# if SATELLITE_FLASH == ON + MOVW SFMTC, #0x223A +# endif ; SATELLITE_FLASH == ON + MOV CKSR, #0xFA +#endif ; (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_48MHZ_CLKP2_16MHZ) + +#if (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_48MHZ_CLKP2_16MHZ) + MOVW PLLCR, #0x0005 + MOVW CKFCR, #0x2001 + MOVW MFMTC, #0x223A +# if SATELLITE_FLASH == ON + MOVW SFMTC, #0x223A +# endif ; SATELLITE_FLASH == ON + MOV CKSR, #0xFA +#endif ; (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_48MHZ_CLKP2_16MHZ) + +#if (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_56MHZ_CLKP2_14MHZ) + MOVW PLLCR, #0x000D + MOVW CKFCR, #0x3001 + MOVW MFMTC, #0x4B3B +# if SATELLITE_FLASH == ON + MOVW SFMTC, #0x4B3B +# endif ; SATELLITE_FLASH == ON + MOV CKSR, #0xFA +#endif ; (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_56MHZ_CLKP2_14MHZ) + +#if (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_56MHZ_CLKP2_14MHZ) + MOVW PLLCR, #0x0006 + MOVW CKFCR, #0x3001 + MOVW MFMTC, #0x4B3B + MOV MFMCS, #0x70 +# if SATELLITE_FLASH == ON + MOVW SFMTC, #0x4B3B + MOV SFMCS, #0x70 +# endif ; SATELLITE_FLASH == ON + MOV VRCR, #0xF6 + MOV CKSR, #0xFA +#endif ; (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_56MHZ_CLKP2_14MHZ) + + +;==================================================================== +; 6.6 Set external bus configuaration +;==================================================================== + +#if BUSMODE != SINGLE_CHIP ; ext bus used + MOV EBCF, #((HOLD_REQ << 7) | (EXT_READY << 6) | (EXT_CLOCK_ENABLE << 5) | (EXT_CLOCK_INVERT << 4) | (EXT_CLOCK_SUSPEND << 3) | EXT_CLOCK_DIVISION) + MOV EBAE0,#ADDR_PINS_7_0 + MOV EBAE1,#ADDR_PINS_15_8 + MOV EBAE2,#ADDR_PINS_23_16 + MOV EBCS, #((ADDRESS_STROBE_LVL << 6) | (ADDRESS_STROBE << 5) | (READ_STROBE << 4) | (HIGH_WRITE_STROBE << 3) | (LOW_WRITE_STROBE << 2) | (HIGH_BYTE_SIGNAL << 1) | LOW_BYTE_SIGNAL) + MOVW EACL0,#CS0_CONFIG + MOVW EACL1,#CS1_CONFIG + MOVW EACL2,#CS2_CONFIG + MOVW EACL3,#CS3_CONFIG + MOVW EACL4,#CS4_CONFIG + MOVW EACL5,#CS5_CONFIG + MOV EAS2, #CS2_START + MOV EAS3, #CS3_START + MOV EAS4, #CS4_START + MOV EAS5, #CS5_START + MOV EBM, #((ADDRESSMODE << 7) | ((BUSMODE-1) << 6) | (CHIP_SELECT5 << 5) | (CHIP_SELECT4 << 4) | (CHIP_SELECT3 << 3) | (CHIP_SELECT2 << 2) | (CHIP_SELECT1 << 1) | CHIP_SELECT0) ; set address mode, ROM access + +# if SERIES == MB96320 || SERIES == MB96340 || SERIES == MB96350 + MOV PIER00,#0xFF +# if (CS0_CONFIG & 0x0080) == 0 || (CS1_CONFIG & 0x0080) == 0 || (CS2_CONFIG & 0x0080) == 0 || (CS3_CONFIG & 0x0080) == 0 || (CS4_CONFIG & 0x0080) == 0 || (CS5_CONFIG & 0x0080) == 0 + MOV PIER01,#0xFF +# endif +# if HOLD_REQ == ON + SETB PIER03:4 +# endif +# if EXT_READY == ON + SETB PIER03:6 +# endif +# else if SERIES == MB96380 + MOV PIER01,#0xFF +# if (CS0_CONFIG & 0x0080) == 0 || (CS1_CONFIG & 0x0080) == 0 || (CS2_CONFIG & 0x0080) == 0 || (CS3_CONFIG & 0x0080) == 0 || (CS4_CONFIG & 0x0080) == 0 || (CS5_CONFIG & 0x0080) == 0 + MOV PIER02,#0xFF +# endif +# if HOLD_REQ == ON + SETB PIER12:7 +# endif +# if EXT_READY == ON + SETB PIER00:2 +# endif +# endif + +#endif + +#if BUSMODE == INTROM_EXTBUS ; EXTBUS and INTROM/EXTROM +# if ROMMIRROR == OFF && CONSTDATA == ROMCONST +# error Mirror function must be ON to mirror internal ROM +# endif +#endif + +ROMM_CONFIG .EQU ((MIRROR_BANK << 4) | (MIRROR_SIZE << 1) | (ROMMIRROR)) + MOV ROMM, #ROMM_CONFIG + + +;==================================================================== +; 6.7 Prepare stacks and set the default stack type +;==================================================================== + + AND CCR,#H'DF ; clear system stack flag + MOVL A, #(__userstack_top) & ~1 + MOVW SP,A ; load offset of stack top to pointer + SWAPW ; swap higher word to AL + MOV USB, A ; set bank + +#if STACK_FILL == ON ; preset the stack + MOV ADB, A + MOVW A, #USTACK ; load start stack address to AL + MOVW A, #STACK_PATTERN ; AL -> AH, pattern in AL + MOVW RW0, #SIZEOF(USTACK) / 2 ; get byte count + FILSWI ADB ; write pattern to stack +#endif + + OR CCR,#H'20 ; set System stack flag + MOVL A, #(__systemstack_top) & ~1 + MOVW SP,A ; load offset of stack top to pointer + SWAPW ; swap higher word to AL + MOV SSB, A ; set bank + +#if STACK_FILL == ON ; preset the stack + MOV ADB, A + MOVW A, #SSTACK ; load start stack address to AL + MOVW A, #STACK_PATTERN ; AL -> AH, pattern in AL + MOVW RW0, #SIZEOF(SSTACK) / 2; get byte count + FILSWI ADB ; write pattern to stack +#endif + +#if STACKUSE == USRSTACK + AND CCR,#H'DF ; clear system stack flag +#endif + + +; The following macro is needed because of the AUTOMODEL option. If the +; model is not known while assembling the module, one has to expect +; completion of streaminit() by RET or RETP. Because RET removes 2 bytes +; from stack and RETP removes 4 bytes from stack, SP is reloaded. + +# macro RELOAD_SP + +#if STACKUSE == USRSTACK + MOVW A, #(__userstack_top) & ~1 +#else + MOVW A, #(__systemstack_top) & ~1 +#endif + MOVW SP,A +# endm + + +;==================================================================== +; 6.8 Copy initial values to data areas. +;==================================================================== +; +; Each C-module has its own __far INIT section. The names are generic. +; DCONST_module contains the initialisers for the far data of the one +; module. INIT_module reserves the RAM area, which has to be loaded +; with the data from DCONST_module. ("module" is the name of the *.c +; file) +; All separated DCONST_module/INIT_module areas are described in +; DTRANS section by start addresses and length of each far section. +; 0000 1. source address (ROM) +; 0004 1. destination address (RAM) +; 0008 length of sections 1 +; 000A 2. source address (ROM) +; 000E 2. destination address (RAM) +; 0012 length of sections 2 +; 0014 3. source address ... +; In addition the start-up file adds the descriptors of the __near +; sections to this table. The order of the descriptors in this table +; depends on the linkage order. +;==================================================================== + MOV A, #BNKSEC DTRANS ; get bank of table + MOV DTB, A ; store bank in DTB + MOVW RW1, #DTRANS ; get start offset of table + OR CCR, #H'20 ; System stack flag set (SSB used) + BRA LABEL2 ; branch to loop condition +LABEL1: + MOVW A, @RW1+6 ; get bank of destination + MOV SSB, A ; save dest bank in SSB + MOVW A, @RW1+2 ; get source bank + MOV ADB, A ; save source bank in ADB + MOVW A, @RW1+4 ; move destination addr in AL + MOVW A, @RW1 ; AL -> AH, src addr -> AL + MOVW RW0, @RW1+8 ; number of bytes to copy -> RW0 + MOVSI SPB, ADB ; copy data + MOVN A, #10 ; length of one table entry is 10 + ADDW RW1, A ; set pointer to next table entry +LABEL2: + MOVW A, RW1 ; get address of next block + SUBW A, #DTRANS ; sub address of first block + CMPW A, #SIZEOF (DTRANS) ; all blocks processed ? + BNE LABEL1 ; if not, branch + + +;==================================================================== +; 6.9 Clear uninitialised data areas to zero +;==================================================================== +; +; Each C-module has its own __far DATA section. The names are generic. +; DATA_module contains the reserved area (RAM) to be cleared. +; ("module" is the name of the *.c file) +; All separated DATA_module areas are described in DCLEAR section by +; start addresses and length of all far section. +; 0000 1. section address (RAM) +; 0004 length of section 1 +; 0006 2. section address (RAM) +; 000A length of section 2 +; 000C 3. section address (RAM) +; 0010 length of section 3 ... +; In addition the start-up file adds the descriptors of the __near +; sections to this table. The order of the descriptors in this table +; depends on the linkage order. +;==================================================================== + MOV A, #BNKSEC DCLEAR ; get bank of table + MOV DTB, A ; store bank in DTB + MOVW RW1, #DCLEAR ; get start offset of table + BRA LABEL4 ; branch to loop condition +LABEL3: + MOV A, @RW1+2 ; get section bank + MOV ADB, A ; save section bank in ADB + MOVW RW0, @RW1+4 ; number of bytes to copy -> RW0 + MOVW A, @RW1 ; move section addr in AL + MOVN A, #0 ; AL -> AH, init value -> AL + FILSI ADB ; write 0 to section + MOVN A, #6 ; length of one table entry is 6 + ADDW RW1, A ; set pointer to next table entry +LABEL4: + MOVW A, RW1 ; get address of next block + SUBW A, #DCLEAR ; sub address of first block + CMPW A, #SIZEOF (DCLEAR) ; all blocks processed ? + BNE LABEL3 ; if not, branch + + + +;==================================================================== +; 6.10 Set Data Bank Register (DTB) and Direct Page Register (DPR) +;==================================================================== + MOV A,#BNKSEC DATA ; User data bank offset + MOV DTB,A + + MOV A,#PAGE DIRDATA_S ; User direct page + MOV DPR,A + +;==================================================================== +; 6.11 Wait for clocks to stabilise +;==================================================================== + +#if (CLOCK_SPEED == CPU_4MHZ_MAIN_CLKP2_4MHZ) && (CLOCKWAIT == ON) +no_MC_yet: + BBC CKMR:5,no_MC_yet ; check MCM and wait for + ; Main Clock to stabilize +#endif ; wait for Main Clock + +#if (((CRYSTAL == FREQ_4MHZ) ||(CRYSTAL == FREQ_8MHZ)) && \ + ((CLOCK_SPEED == CPU_12MHZ_CLKP2_12MHZ) || \ + (CLOCK_SPEED == CPU_16MHZ_CLKP2_16MHZ) || \ + (CLOCK_SPEED == CPU_24MHZ_CLKP2_12MHZ))) +no_PLL_0WS: + BBC CKMR:6, no_PLL_0WS + +# if ! ((SERIES == MB96340) && (DEVICE < 3)) + MOVW MFMTC, #0x2208 +# if SATELLITE_FLASH == ON + MOVW SFMTC, #0x2208 +# endif ; SATELLITE_FLASH == ON +# endif ; ! ((SERIES == MB96340) && (DEVICE < 3)) +#endif + +#if ((CRYSTAL == FREQ_4MHZ) || (CRYSTAL == FREQ_8MHZ)) && \ + ((CLOCK_SPEED == CPU_32MHZ_CLKP2_16MHZ) || \ + (CLOCK_SPEED == CPU_32MHZ_CLKP1_16MHZ_CLKP2_16MHZ)) && \ + ! ((SERIES == MB96340) && (DEVICE < 3)) +no_PLL_1WS: + BBC CKMR:6, no_PLL_1WS + + MOVW MFMTC, #0x6B09 +# if SATELLITE_FLASH == ON + MOVW SFMTC, #0x6B09 +# endif ; SATELLITE_FLASH == ON +#endif + +#if (CLOCKWAIT == ON) && \ + ((CLOCK_SPEED == CPU_4MHZ_PLL_CLKP2_4MHZ) || \ + (CLOCK_SPEED == CPU_8MHZ_CLKP2_8MHZ) || \ + (CLOCK_SPEED == CPU_48MHZ_CLKP2_16MHZ) || \ + (CLOCK_SPEED == CPU_56MHZ_CLKP2_14MHZ)) +no_PLL_yet: + BBC CKMR:6,no_PLL_yet ; check PCM and wait for + ; PLL to stabilize +#endif ; wait for PLL + +;==================================================================== +; 6.12 Initialise Low-Level Library Interface +;==================================================================== +; +; Call lib init function and reload stack afterwards, if AUTOMODEL +;==================================================================== +#if CLIBINIT == ON +# if MEMMODEL == SMALL || MEMMODEL == COMPACT + CALL __stream_init ; initialise library IO +# else ; MEDIUM, LARGE, AUTOMODEL + CALLP __stream_init ; initialise library IO +# if MEMMODEL == AUTOMODEL + RELOAD_SP ; reload stack since stream_init was + ; possibly left by RET (not RETP) +# endif ; AUTOMODEL +# endif ; MEDIUM, LARGE, AUTOMODEL +#endif ; LIBINI + +;==================================================================== +; 6.13 Call C-language main function +;==================================================================== +#if MEMMODEL == SMALL || MEMMODEL == COMPACT + CALL _main ; Start main function +#else ; MEDIUM, LARGE, AUTOMODEL + CALLP _main ; Start main function + ; ignore remaining word on stack, + ; if main was completed by RET +#endif +;==================================================================== +; 6.14 Shut down library +;==================================================================== +#if CLIBINIT == ON +# if MEMMODEL == SMALL || MEMMODEL == COMPACT + CALL _exit +# else ; MEDIUM, LARGE, AUTOMODEL + CALLP _exit ; ignore remaining word on stack, + ; if main was completed by RET +# endif +__exit: +#endif + +;==================================================================== +; 6.15 Program end loop +;==================================================================== + +end: BRA end ; Loop + + +;==================================================================== +; 6.16 Set Flash Security +;==================================================================== + + .SECTION MAIN_SECURITY, CONST, LOCATE=H'DF0000 +#if MAIN_SECURITY_ENABLE == 0 + .DATA.W 0xFFFF ; Security DISABLED + .SKIP 16 +#else MAIN_SECURITY_ENABLE == 1 + .DATA.W 0x0099 ; Security ENABLED + .DATA.W ((MAIN_UNLOCK_1 << 8) | MAIN_UNLOCK_0) + .DATA.W ((MAIN_UNLOCK_3 << 8) | MAIN_UNLOCK_2) + .DATA.W ((MAIN_UNLOCK_5 << 8) | MAIN_UNLOCK_4) + .DATA.W ((MAIN_UNLOCK_7 << 8) | MAIN_UNLOCK_6) + .DATA.W ((MAIN_UNLOCK_9 << 8) | MAIN_UNLOCK_8) + .DATA.W ((MAIN_UNLOCK_11 << 8) | MAIN_UNLOCK_10) + .DATA.W ((MAIN_UNLOCK_13 << 8) | MAIN_UNLOCK_12) + .DATA.W ((MAIN_UNLOCK_15 << 8) | MAIN_UNLOCK_14) +#endif + .SKIP 4 + .SKIP 6 + +#if SATELLITE_FLASH == ON + .SECTION SATELLITE_SECURITY, CONST, LOCATE=H'DE0000 +# if SATELLITE_SECURITY_ENABLE == 0 + .DATA.W 0xFFFF ; Security DISABLED + .SKIP 16 +# else SATELLITE_SECURITY_ENABLE == 1 + .DATA.W 0x0099 ; Security ENABLED + .DATA.W ((SATELLITE_UNLOCK_1 << 8) | SATELLITE_UNLOCK_0) + .DATA.W ((SATELLITE_UNLOCK_3 << 8) | SATELLITE_UNLOCK_2) + .DATA.W ((SATELLITE_UNLOCK_5 << 8) | SATELLITE_UNLOCK_4) + .DATA.W ((SATELLITE_UNLOCK_7 << 8) | SATELLITE_UNLOCK_6) + .DATA.W ((SATELLITE_UNLOCK_9 << 8) | SATELLITE_UNLOCK_8) + .DATA.W ((SATELLITE_UNLOCK_11 << 8) | SATELLITE_UNLOCK_10) + .DATA.W ((SATELLITE_UNLOCK_13 << 8) | SATELLITE_UNLOCK_12) + .DATA.W ((SATELLITE_UNLOCK_15 << 8) | SATELLITE_UNLOCK_14) +# endif + .SKIP 4 + .SKIP 6 +#endif ; SATELLITE_FLASH == ON + + +;==================================================================== +; 6.17 Set Flash write protection +;==================================================================== + + .SECTION MAIN_PROTECT, CONST, LOCATE=H'DF001C +#if MAIN_FLASH_WRITE_PROTECT == ON + .DATA.L 0x292D3A7B + .DATA.B ~((PROTECT_SECTOR_SA3 << 3) | (PROTECT_SECTOR_SA2 << 2) | (PROTECT_SECTOR_SA1 << 1) | PROTECT_SECTOR_SA0) + .DATA.E 0xFFFFFF + .DATA.B ~((PROTECT_SECTOR_SA39 << 7) | (PROTECT_SECTOR_SA38 << 6) | (PROTECT_SECTOR_SA37 << 5) | (PROTECT_SECTOR_SA36 << 4) | (PROTECT_SECTOR_SA35 << 3) | (PROTECT_SECTOR_SA34 << 2) | (PROTECT_SECTOR_SA33 << 1) | PROTECT_SECTOR_SA32) + .SKIP 3 +#else + .DATA.L 0xFFFFFFFF + .SKIP 8 +#endif ; MAIN_FLASH_WRITE_PROTECT + .SKIP 8 + +#if SATELLITE_FLASH == ON + .SECTION SATELLITE_PROTECT, CONST, LOCATE=H'DE001C +# if SATELLITE_FLASH_WRITE_PROTECT == ON + .DATA.L 0x292D3A7B + .DATA.B ~((PROTECT_SECTOR_SB3 << 3) | (PROTECT_SECTOR_SB2 << 2) | (PROTECT_SECTOR_SB1 << 1) | PROTECT_SECTOR_SB0) + .SKIP 7 +# else + .DATA.L 0xFFFFFFFF + .SKIP 8 +# endif ; SATELLITE_FLASH_WRITE_PROTECT + .SKIP 8 +#endif ; SATELLITE_FLASH == ON + + +;==================================================================== +; 6.18 Debug address specification +;==================================================================== +; +; BDM configuration section should always be defined for later +; configuration by e.g. debugger tool or (special) programmer tool. + + .SECTION BDM_CONFIG, CONST, LOCATE=H'DF0040 + +#if BACKGROUND_DEBUGGING == ON + + .DATA.L 0x292D3A7B + + .ORG H'DF0044 + .DATA.W BDM_CONFIGURATION + + .ORG H'DF0046 +# if (SERIES == MB96340 && DEVICE < 3) +# error Device does not support background debugging +# endif ; (SERIES == MB96340 && DEVICE < 3) + +# if (SERIES == MB96340 && DEVICE < 12) + .DATA.W (D'16 * CRYSTAL + BDM_BAUDRATE) / BDM_BAUDRATE +# else + .DATA.W (D'32 * CRYSTAL + BDM_BAUDRATE) / BDM_BAUDRATE +# endif ; (SERIES == MB96340 && if DEVICE < 12) + + .ORG H'DF0048 + .DATA.E BDM_EXT_CONFIG + + .ORG H'DF004B + .DATA.B BDM_WD_PATTERN + + .ORG H'DF0050 + .DATA.W BDM_PFCS0 + .DATA.W BDM_PFCS1 + .DATA.W BDM_PFCS2 + .DATA.W BDM_PFCS3 + + .DATA.E BDM_PFA0, BDM_PFA1 + .DATA.E BDM_PFA2, BDM_PFA3 + .DATA.E BDM_PFA4, BDM_PFA5 + .DATA.E BDM_PFA6, BDM_PFA7 + + .DATA.W BDM_PFD0, BDM_PFD1 + .DATA.W BDM_PFD2, BDM_PFD3 + .DATA.W BDM_PFD4, BDM_PFD5 + .DATA.W BDM_PFD6, BDM_PFD7 +#else + .DATAB.B 64, 0xFF ; fill section with 0xFF + +#endif ; BACKGROUND_DEBUGGING == ON + + .ORG 0xDF0080 + .END notresetyet ; define debugger start address + + +;==================================================================== +; ----------------------- End of Start-up file --------------------- +;==================================================================== diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Src/config/FreeRTOSConfig.h b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Src/config/FreeRTOSConfig.h new file mode 100644 index 000000000..16fe7a61e --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Src/config/FreeRTOSConfig.h @@ -0,0 +1,84 @@ +/* + FreeRTOS.org V4.5.0 - Copyright (C) 2003-2007 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + + Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along + with commercial development and support options. + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 1 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 56000000 ) /* Clock setup from start.asm in the demo application. */ +#define configCLKP1_CLOCK_HZ ( ( unsigned portLONG ) 56000000 ) /* Clock setup from start.asm in the demo application. */ +#define configTICK_RATE_HZ ( ( portTickType ) 100 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 6 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 176 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 21504 ) ) +#define configMAX_TASK_NAME_LEN ( 20 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 1 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 1 +#define configMAX_CO_ROUTINE_PRIORITIES ( 4 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vResumeFromISR 1 +//#define INCLUDE_xTaskResumeFromISR 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Src/config/config.h b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Src/config/config.h new file mode 100644 index 000000000..8847e6607 --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Src/config/config.h @@ -0,0 +1,73 @@ +/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ +/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ +/* ELIGIBILITY FOR ANY PURPOSES. */ +/* (C) Fujitsu Microelectronics Europe GmbH */ +/*--------------------------------------------------------------------------- + config.h + - This file contains the defines to include or exclude a certain demo + application function. +/*---------------------------------------------------------------------------*/ +/* The below are the defines that includes the corresponding function (those create related + * tasks) if they are defined aand vice a versa. + */ + +#define INCLUDE_StartIntegerMathTasks 1 + +#define INCLUDE_StartPolledQueueTasks 1 +#define INCLUDE_StartSemaphoreTasks 1 +#define INCLUDE_StartBlockingQueueTasks 1 +#define INCLUDE_StartDynamicPriorityTasks 1 + +#define INCLUDE_StartHookCoRoutines 1 +#define INCLUDE_StartGenericQueueTasks 1 +#define INCLUDE_StartQueuePeekTasks 1 + +#define INCLUDE_CreateSuicidalTasks 1 + +/*---------------------------------------------------------------------------*/ + +#if __CONFIG__ == 1 + #define INCLUDE_StartLEDFlashTasks 1 + #define INCLUDE_AltStartComTestTasks 1 + #define INCLUDE_StartMathTasks 0 + #define INCLUDE_StartFlashCoRoutines 0 + #define INCLUDE_CreateBlockTimeTasks 0 + #define INCLUDE_TraceListTasks 1 +#elif __CONFIG__ == 2 + #define INCLUDE_StartLEDFlashTasks 0 + #define INCLUDE_AltStartComTestTasks 0 + #define INCLUDE_StartMathTasks 0 + #define INCLUDE_StartFlashCoRoutines 1 + #define INCLUDE_CreateBlockTimeTasks 1 + #define INCLUDE_TraceListTasks 1 +#elif __CONFIG__ == 3 + #define INCLUDE_StartLEDFlashTasks 1 + #define INCLUDE_AltStartComTestTasks 1 + #define INCLUDE_StartMathTasks 1 + #define INCLUDE_StartFlashCoRoutines 0 + #define INCLUDE_CreateBlockTimeTasks 1 + #define INCLUDE_TraceListTasks 0 +#elif __CONFIG__ == 4 + #define INCLUDE_StartLEDFlashTasks 0 + #define INCLUDE_AltStartComTestTasks 0 + #define INCLUDE_StartMathTasks 1 + #define INCLUDE_StartFlashCoRoutines 1 + #define INCLUDE_CreateBlockTimeTasks 0 + #define INCLUDE_TraceListTasks 1 +#else + #error __CONFIG__ should be defined and it should have value between 1 to 4 +#endif + +/* vStartFlashCoRoutines() can only be used (by defining INCLUDE_StartFlashCoRoutines as 1) + * if vStartLEDFlashTasks() and vAltStartComTestTasks() functions are not used (by defining + * INCLUDE_StartLEDFlashTasks and INCLUDE_AltStartComTestTasks both as 0) and vice a versa. + * This is because tasks created by these functions shares the LEDs connected to Port 00. The + * corresponding code from the function prvCheckOtherTasksAreStillRunning() should also be + * commented. + */ + +/* In order to have vTraceListTasks() the below define INCLUDE_TraceListTasks should be defined + * as 1. While doing so one have to compromise on some of the other tasks as vTraceListTasks() + * requires high amount of memory. It should be noted that if all the task are tried to be inclued + * then the compiler would give memory overflow error. + */ \ No newline at end of file diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Src/mb96348hs.asm b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Src/mb96348hs.asm new file mode 100644 index 000000000..d6613c658 --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Src/mb96348hs.asm @@ -0,0 +1,2090 @@ +/* FFMC-16 IO-MAP HEADER FILE */ +/* ========================== */ +/* SOFTUNE WORKBENCH FORMAT */ +/* C-DEFINITIONS FOR IO-SYMBOLS */ +/* CREATED BY IO-WIZARD V2.27 */ +/* $Id: mb96348hs.asm,v 1.7 2007/09/20 14:23:20 mwilla Exp $ */ +/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ +/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ +/* ELIGIBILITY FOR ANY PURPOSES. */ +/* (C) Fujitsu Microelectronics Europe GmbH */ +/* ************************************************************************* */ +/* FUJITSU MICROELECTRONICS EUROPE GMBH */ +/* Pittlerstrasse 47, 63225 Langen, Germany */ +/* Tel.:++49/6103/690-0,Fax - 122 */ +/* */ +/* The following software is for demonstration purposes only. */ +/* It is not fully tested, nor validated in order to fullfill */ +/* its task under all circumstances. Therefore, this software */ +/* or any part of it must only be used in an evaluation */ +/* laboratory environment. */ +/* This software is subject to the rules of our standard */ +/* DISCLAIMER, that is delivered with our SW-tools on the CD or DVD */ +/* "Micros Documentation & Software" (V3.4 or later) or */ +/* see our Internet Page - */ +/* http://emea.fujitsu.com/microelectronics */ +/* ************************************************************************* */ +/* */ +/* NOTE: */ +/* */ +/* This header-file covers all features of the chip MB96F348HS. */ +/* */ +/* */ +/* ---------------------------------------------------------------------- */ +/* History: */ +/* Date Version Author Description */ +/* 22.12.2006 1.0 PHu Initial Release: derived from headerfile of */ +/* MB96348RS and added Satellite Flash, removed */ +/* RTC, Clock Calibration, LIN-USART7-9 */ +/* 16.01.2007 1.1 PHu Add 32-bit access names for CAN where */ +/* appropriate */ +/* 09.02.2007 1.3 PHu skip version 1.2 to be in line with CVS */ +/* numbering */ +/* correct addresses of LIN-UART3 registers */ +/* allow only 16 bit access for the ADSR */ +/* 12.04.2007 1.4 Mef Added Voltage Regulator Control Register */ +/* Added RD19V bit in Flash Memory Control */ +/* Status Register */ +/* 03.05.2007 1.5 Mef Added LIN USART 7,8,9 */ +/* 15.05.2007 1.6 Mef Added RTC */ +/* 20.09.2007 1.7 MWi Completely revised version */ + + .PROGRAM MB96348HS + .TITLE MB96348HS + +;------------------------ +; IO-AREA DEFINITIONS : +;------------------------ + + + + .section IOBASE, IO, locate=0x0 ; + .GLOBAL __pdr00, __pdr01, __pdr02, __pdr03, __pdr04, __pdr05 + .GLOBAL __pdr06, __pdr07, __pdr08, __pdr09, __pdr10, __adcs + .GLOBAL __adcsl, __adcsh, __adcr, __adcrl, __adcrh, __adsr + .GLOBAL __adecr, __tcdt0, __tccs0, __tccsl0, __tccsh0, __tcdt1 + .GLOBAL __tccs1, __tccsl1, __tccsh1, __ocs0, __ocs1, __occp0 + .GLOBAL __occp1, __ocs2, __ocs3, __occp2, __occp3, __ocs4 + .GLOBAL __ocs5, __occp4, __occp5, __ocs6, __ocs7, __occp6 + .GLOBAL __occp7, __ics01, __ice01, __ipcp0, __ipcpl0, __ipcph0 + .GLOBAL __ipcp1, __ipcpl1, __ipcph1, __ics23, __ice23, __ipcp2 + .GLOBAL __ipcpl2, __ipcph2, __ipcp3, __ipcpl3, __ipcph3, __ics45 + .GLOBAL __ice45, __ipcp4, __ipcpl4, __ipcph4, __ipcp5, __ipcpl5 + .GLOBAL __ipcph5, __ics67, __ice67, __ipcp6, __ipcpl6, __ipcph6 + .GLOBAL __ipcp7, __ipcpl7, __ipcph7, __enir0, __eirr0, __elvr0 + .GLOBAL __elvrl0, __elvrh0, __enir1, __eirr1, __elvr1, __elvrl1 + .GLOBAL __elvrh1, __tmcsr0, __tmcsrl0, __tmcsrh0, __tmrlr0, __tmr0 + .GLOBAL __tmcsr1, __tmcsrl1, __tmcsrh1, __tmrlr1, __tmr1, __tmcsr2 + .GLOBAL __tmcsrl2, __tmcsrh2, __tmrlr2, __tmr2, __tmcsr3, __tmcsrl3 + .GLOBAL __tmcsrh3, __tmrlr3, __tmr3, __tmcsr6, __tmcsrl6, __tmcsrh6 + .GLOBAL __tmrlr6, __tmr6, __gcn10, __gcn1l0, __gcn1h0, __gcn20 + .GLOBAL __gcn2l0, __gcn2h0, __ptmr0, __pcsr0, __pdut0, __pcn0 + .GLOBAL __pcnl0, __pcnh0, __ptmr1, __pcsr1, __pdut1, __pcn1 + .GLOBAL __pcnl1, __pcnh1, __ptmr2, __pcsr2, __pdut2, __pcn2 + .GLOBAL __pcnl2, __pcnh2, __ptmr3, __pcsr3, __pdut3, __pcn3 + .GLOBAL __pcnl3, __pcnh3, __gcn11, __gcn1l1, __gcn1h1, __gcn21 + .GLOBAL __gcn2l1, __gcn2h1, __ptmr4, __pcsr4, __pdut4, __pcn4 + .GLOBAL __pcnl4, __pcnh4, __ptmr5, __pcsr5, __pdut5, __pcn5 + .GLOBAL __pcnl5, __pcnh5, __ibsr0, __ibcr0, __itba0, __itbal0 + .GLOBAL __itbah0, __itmk0, __itmkl0, __itmkh0, __isba0, __ismk0 + .GLOBAL __idar0, __iccr0, __ibsr1, __ibcr1, __itba1, __itbal1 + .GLOBAL __itbah1, __itmk1, __itmkl1, __itmkh1, __isba1, __ismk1 + .GLOBAL __idar1, __iccr1, __smr0, __scr0, __tdr0, __rdr0 + .GLOBAL __ssr0, __eccr0, __escr0, __bgr0, __bgrl0, __bgrh0 + .GLOBAL __esir0, __smr1, __scr1, __tdr1, __rdr1, __ssr1 + .GLOBAL __eccr1, __escr1, __bgr1, __bgrl1, __bgrh1, __esir1 + .GLOBAL __smr2, __scr2, __tdr2, __rdr2, __ssr2, __eccr2 + .GLOBAL __escr2, __bgr2, __bgrl2, __bgrh2, __esir2, __smr3 + .GLOBAL __scr3, __tdr3, __rdr3, __ssr3, __eccr3, __escr3 + .GLOBAL __bgr3, __bgrl3, __bgrh3, __esir3 + +__pdr00 .res.b 1 ;000000 +PDR00 .equ 0x0000 +__pdr01 .res.b 1 ;000001 +PDR01 .equ 0x0001 +__pdr02 .res.b 1 ;000002 +PDR02 .equ 0x0002 +__pdr03 .res.b 1 ;000003 +PDR03 .equ 0x0003 +__pdr04 .res.b 1 ;000004 +PDR04 .equ 0x0004 +__pdr05 .res.b 1 ;000005 +PDR05 .equ 0x0005 +__pdr06 .res.b 1 ;000006 +PDR06 .equ 0x0006 +__pdr07 .res.b 1 ;000007 +PDR07 .equ 0x0007 +__pdr08 .res.b 1 ;000008 +PDR08 .equ 0x0008 +__pdr09 .res.b 1 ;000009 +PDR09 .equ 0x0009 +__pdr10 .res.b 1 ;00000A +PDR10 .equ 0x000A + .org 0x000018 +__adcs ; overlay symbol ;000018 +ADCS .equ 0x0018 +__adcsl .res.b 1 ;000018 +ADCSL .equ 0x0018 +__adcsh .res.b 1 ;000019 +ADCSH .equ 0x0019 +__adcr ; overlay symbol ;00001A +ADCR .equ 0x001A +__adcrl .res.b 1 ;00001A +ADCRL .equ 0x001A +__adcrh .res.b 1 ;00001B +ADCRH .equ 0x001B +__adsr .res.b 2 ;00001C +ADSR .equ 0x001C +__adecr .res.b 1 ;00001E +ADECR .equ 0x001E + .org 0x000020 +__tcdt0 .res.b 2 ;000020 +TCDT0 .equ 0x0020 +__tccs0 ; overlay symbol ;000022 +TCCS0 .equ 0x0022 +__tccsl0 .res.b 1 ;000022 +TCCSL0 .equ 0x0022 +__tccsh0 .res.b 1 ;000023 +TCCSH0 .equ 0x0023 +__tcdt1 .res.b 2 ;000024 +TCDT1 .equ 0x0024 +__tccs1 ; overlay symbol ;000026 +TCCS1 .equ 0x0026 +__tccsl1 .res.b 1 ;000026 +TCCSL1 .equ 0x0026 +__tccsh1 .res.b 1 ;000027 +TCCSH1 .equ 0x0027 +__ocs0 .res.b 1 ;000028 +OCS0 .equ 0x0028 +__ocs1 .res.b 1 ;000029 +OCS1 .equ 0x0029 +__occp0 .res.b 2 ;00002A +OCCP0 .equ 0x002A +__occp1 .res.b 2 ;00002C +OCCP1 .equ 0x002C +__ocs2 .res.b 1 ;00002E +OCS2 .equ 0x002E +__ocs3 .res.b 1 ;00002F +OCS3 .equ 0x002F +__occp2 .res.b 2 ;000030 +OCCP2 .equ 0x0030 +__occp3 .res.b 2 ;000032 +OCCP3 .equ 0x0032 +__ocs4 .res.b 1 ;000034 +OCS4 .equ 0x0034 +__ocs5 .res.b 1 ;000035 +OCS5 .equ 0x0035 +__occp4 .res.b 2 ;000036 +OCCP4 .equ 0x0036 +__occp5 .res.b 2 ;000038 +OCCP5 .equ 0x0038 +__ocs6 .res.b 1 ;00003A +OCS6 .equ 0x003A +__ocs7 .res.b 1 ;00003B +OCS7 .equ 0x003B +__occp6 .res.b 2 ;00003C +OCCP6 .equ 0x003C +__occp7 .res.b 2 ;00003E +OCCP7 .equ 0x003E +__ics01 .res.b 1 ;000040 +ICS01 .equ 0x0040 +__ice01 .res.b 1 ;000041 +ICE01 .equ 0x0041 +__ipcp0 ; overlay symbol ;000042 +IPCP0 .equ 0x0042 +__ipcpl0 .res.b 1 ;000042 +IPCPL0 .equ 0x0042 +__ipcph0 .res.b 1 ;000043 +IPCPH0 .equ 0x0043 +__ipcp1 ; overlay symbol ;000044 +IPCP1 .equ 0x0044 +__ipcpl1 .res.b 1 ;000044 +IPCPL1 .equ 0x0044 +__ipcph1 .res.b 1 ;000045 +IPCPH1 .equ 0x0045 +__ics23 .res.b 1 ;000046 +ICS23 .equ 0x0046 +__ice23 .res.b 1 ;000047 +ICE23 .equ 0x0047 +__ipcp2 ; overlay symbol ;000048 +IPCP2 .equ 0x0048 +__ipcpl2 .res.b 1 ;000048 +IPCPL2 .equ 0x0048 +__ipcph2 .res.b 1 ;000049 +IPCPH2 .equ 0x0049 +__ipcp3 ; overlay symbol ;00004A +IPCP3 .equ 0x004A +__ipcpl3 .res.b 1 ;00004A +IPCPL3 .equ 0x004A +__ipcph3 .res.b 1 ;00004B +IPCPH3 .equ 0x004B +__ics45 .res.b 1 ;00004C +ICS45 .equ 0x004C +__ice45 .res.b 1 ;00004D +ICE45 .equ 0x004D +__ipcp4 ; overlay symbol ;00004E +IPCP4 .equ 0x004E +__ipcpl4 .res.b 1 ;00004E +IPCPL4 .equ 0x004E +__ipcph4 .res.b 1 ;00004F +IPCPH4 .equ 0x004F +__ipcp5 ; overlay symbol ;000050 +IPCP5 .equ 0x0050 +__ipcpl5 .res.b 1 ;000050 +IPCPL5 .equ 0x0050 +__ipcph5 .res.b 1 ;000051 +IPCPH5 .equ 0x0051 +__ics67 .res.b 1 ;000052 +ICS67 .equ 0x0052 +__ice67 .res.b 1 ;000053 +ICE67 .equ 0x0053 +__ipcp6 ; overlay symbol ;000054 +IPCP6 .equ 0x0054 +__ipcpl6 .res.b 1 ;000054 +IPCPL6 .equ 0x0054 +__ipcph6 .res.b 1 ;000055 +IPCPH6 .equ 0x0055 +__ipcp7 ; overlay symbol ;000056 +IPCP7 .equ 0x0056 +__ipcpl7 .res.b 1 ;000056 +IPCPL7 .equ 0x0056 +__ipcph7 .res.b 1 ;000057 +IPCPH7 .equ 0x0057 +__enir0 .res.b 1 ;000058 +ENIR0 .equ 0x0058 +__eirr0 .res.b 1 ;000059 +EIRR0 .equ 0x0059 +__elvr0 ; overlay symbol ;00005A +ELVR0 .equ 0x005A +__elvrl0 .res.b 1 ;00005A +ELVRL0 .equ 0x005A +__elvrh0 .res.b 1 ;00005B +ELVRH0 .equ 0x005B +__enir1 .res.b 1 ;00005C +ENIR1 .equ 0x005C +__eirr1 .res.b 1 ;00005D +EIRR1 .equ 0x005D +__elvr1 ; overlay symbol ;00005E +ELVR1 .equ 0x005E +__elvrl1 .res.b 1 ;00005E +ELVRL1 .equ 0x005E +__elvrh1 .res.b 1 ;00005F +ELVRH1 .equ 0x005F +__tmcsr0 ; overlay symbol ;000060 +TMCSR0 .equ 0x0060 +__tmcsrl0 .res.b 1 ;000060 +TMCSRL0 .equ 0x0060 +__tmcsrh0 .res.b 1 ;000061 +TMCSRH0 .equ 0x0061 +__tmrlr0 ; overlay symbol ;000062 +TMRLR0 .equ 0x0062 +__tmr0 .res.b 2 ;000062 +TMR0 .equ 0x0062 +__tmcsr1 ; overlay symbol ;000064 +TMCSR1 .equ 0x0064 +__tmcsrl1 .res.b 1 ;000064 +TMCSRL1 .equ 0x0064 +__tmcsrh1 .res.b 1 ;000065 +TMCSRH1 .equ 0x0065 +__tmrlr1 ; overlay symbol ;000066 +TMRLR1 .equ 0x0066 +__tmr1 .res.b 2 ;000066 +TMR1 .equ 0x0066 +__tmcsr2 ; overlay symbol ;000068 +TMCSR2 .equ 0x0068 +__tmcsrl2 .res.b 1 ;000068 +TMCSRL2 .equ 0x0068 +__tmcsrh2 .res.b 1 ;000069 +TMCSRH2 .equ 0x0069 +__tmrlr2 ; overlay symbol ;00006A +TMRLR2 .equ 0x006A +__tmr2 .res.b 2 ;00006A +TMR2 .equ 0x006A +__tmcsr3 ; overlay symbol ;00006C +TMCSR3 .equ 0x006C +__tmcsrl3 .res.b 1 ;00006C +TMCSRL3 .equ 0x006C +__tmcsrh3 .res.b 1 ;00006D +TMCSRH3 .equ 0x006D +__tmrlr3 ; overlay symbol ;00006E +TMRLR3 .equ 0x006E +__tmr3 .res.b 2 ;00006E +TMR3 .equ 0x006E +__tmcsr6 ; overlay symbol ;000070 +TMCSR6 .equ 0x0070 +__tmcsrl6 .res.b 1 ;000070 +TMCSRL6 .equ 0x0070 +__tmcsrh6 .res.b 1 ;000071 +TMCSRH6 .equ 0x0071 +__tmrlr6 ; overlay symbol ;000072 +TMRLR6 .equ 0x0072 +__tmr6 .res.b 2 ;000072 +TMR6 .equ 0x0072 +__gcn10 ; overlay symbol ;000074 +GCN10 .equ 0x0074 +__gcn1l0 .res.b 1 ;000074 +GCN1L0 .equ 0x0074 +__gcn1h0 .res.b 1 ;000075 +GCN1H0 .equ 0x0075 +__gcn20 ; overlay symbol ;000076 +GCN20 .equ 0x0076 +__gcn2l0 .res.b 1 ;000076 +GCN2L0 .equ 0x0076 +__gcn2h0 .res.b 1 ;000077 +GCN2H0 .equ 0x0077 +__ptmr0 .res.b 2 ;000078 +PTMR0 .equ 0x0078 +__pcsr0 .res.b 2 ;00007A +PCSR0 .equ 0x007A +__pdut0 .res.b 2 ;00007C +PDUT0 .equ 0x007C +__pcn0 ; overlay symbol ;00007E +PCN0 .equ 0x007E +__pcnl0 .res.b 1 ;00007E +PCNL0 .equ 0x007E +__pcnh0 .res.b 1 ;00007F +PCNH0 .equ 0x007F +__ptmr1 .res.b 2 ;000080 +PTMR1 .equ 0x0080 +__pcsr1 .res.b 2 ;000082 +PCSR1 .equ 0x0082 +__pdut1 .res.b 2 ;000084 +PDUT1 .equ 0x0084 +__pcn1 ; overlay symbol ;000086 +PCN1 .equ 0x0086 +__pcnl1 .res.b 1 ;000086 +PCNL1 .equ 0x0086 +__pcnh1 .res.b 1 ;000087 +PCNH1 .equ 0x0087 +__ptmr2 .res.b 2 ;000088 +PTMR2 .equ 0x0088 +__pcsr2 .res.b 2 ;00008A +PCSR2 .equ 0x008A +__pdut2 .res.b 2 ;00008C +PDUT2 .equ 0x008C +__pcn2 ; overlay symbol ;00008E +PCN2 .equ 0x008E +__pcnl2 .res.b 1 ;00008E +PCNL2 .equ 0x008E +__pcnh2 .res.b 1 ;00008F +PCNH2 .equ 0x008F +__ptmr3 .res.b 2 ;000090 +PTMR3 .equ 0x0090 +__pcsr3 .res.b 2 ;000092 +PCSR3 .equ 0x0092 +__pdut3 .res.b 2 ;000094 +PDUT3 .equ 0x0094 +__pcn3 ; overlay symbol ;000096 +PCN3 .equ 0x0096 +__pcnl3 .res.b 1 ;000096 +PCNL3 .equ 0x0096 +__pcnh3 .res.b 1 ;000097 +PCNH3 .equ 0x0097 +__gcn11 ; overlay symbol ;000098 +GCN11 .equ 0x0098 +__gcn1l1 .res.b 1 ;000098 +GCN1L1 .equ 0x0098 +__gcn1h1 .res.b 1 ;000099 +GCN1H1 .equ 0x0099 +__gcn21 ; overlay symbol ;00009A +GCN21 .equ 0x009A +__gcn2l1 .res.b 1 ;00009A +GCN2L1 .equ 0x009A +__gcn2h1 .res.b 1 ;00009B +GCN2H1 .equ 0x009B +__ptmr4 .res.b 2 ;00009C +PTMR4 .equ 0x009C +__pcsr4 .res.b 2 ;00009E +PCSR4 .equ 0x009E +__pdut4 .res.b 2 ;0000A0 +PDUT4 .equ 0x00A0 +__pcn4 ; overlay symbol ;0000A2 +PCN4 .equ 0x00A2 +__pcnl4 .res.b 1 ;0000A2 +PCNL4 .equ 0x00A2 +__pcnh4 .res.b 1 ;0000A3 +PCNH4 .equ 0x00A3 +__ptmr5 .res.b 2 ;0000A4 +PTMR5 .equ 0x00A4 +__pcsr5 .res.b 2 ;0000A6 +PCSR5 .equ 0x00A6 +__pdut5 .res.b 2 ;0000A8 +PDUT5 .equ 0x00A8 +__pcn5 ; overlay symbol ;0000AA +PCN5 .equ 0x00AA +__pcnl5 .res.b 1 ;0000AA +PCNL5 .equ 0x00AA +__pcnh5 .res.b 1 ;0000AB +PCNH5 .equ 0x00AB +__ibsr0 .res.b 1 ;0000AC +IBSR0 .equ 0x00AC +__ibcr0 .res.b 1 ;0000AD +IBCR0 .equ 0x00AD +__itba0 ; overlay symbol ;0000AE +ITBA0 .equ 0x00AE +__itbal0 .res.b 1 ;0000AE +ITBAL0 .equ 0x00AE +__itbah0 .res.b 1 ;0000AF +ITBAH0 .equ 0x00AF +__itmk0 ; overlay symbol ;0000B0 +ITMK0 .equ 0x00B0 +__itmkl0 .res.b 1 ;0000B0 +ITMKL0 .equ 0x00B0 +__itmkh0 .res.b 1 ;0000B1 +ITMKH0 .equ 0x00B1 +__isba0 .res.b 1 ;0000B2 +ISBA0 .equ 0x00B2 +__ismk0 .res.b 1 ;0000B3 +ISMK0 .equ 0x00B3 +__idar0 .res.b 1 ;0000B4 +IDAR0 .equ 0x00B4 +__iccr0 .res.b 1 ;0000B5 +ICCR0 .equ 0x00B5 +__ibsr1 .res.b 1 ;0000B6 +IBSR1 .equ 0x00B6 +__ibcr1 .res.b 1 ;0000B7 +IBCR1 .equ 0x00B7 +__itba1 ; overlay symbol ;0000B8 +ITBA1 .equ 0x00B8 +__itbal1 .res.b 1 ;0000B8 +ITBAL1 .equ 0x00B8 +__itbah1 .res.b 1 ;0000B9 +ITBAH1 .equ 0x00B9 +__itmk1 ; overlay symbol ;0000BA +ITMK1 .equ 0x00BA +__itmkl1 .res.b 1 ;0000BA +ITMKL1 .equ 0x00BA +__itmkh1 .res.b 1 ;0000BB +ITMKH1 .equ 0x00BB +__isba1 .res.b 1 ;0000BC +ISBA1 .equ 0x00BC +__ismk1 .res.b 1 ;0000BD +ISMK1 .equ 0x00BD +__idar1 .res.b 1 ;0000BE +IDAR1 .equ 0x00BE +__iccr1 .res.b 1 ;0000BF +ICCR1 .equ 0x00BF +__smr0 .res.b 1 ;0000C0 +SMR0 .equ 0x00C0 +__scr0 .res.b 1 ;0000C1 +SCR0 .equ 0x00C1 +__tdr0 ; overlay symbol ;0000C2 +TDR0 .equ 0x00C2 +__rdr0 .res.b 1 ;0000C2 +RDR0 .equ 0x00C2 +__ssr0 .res.b 1 ;0000C3 +SSR0 .equ 0x00C3 +__eccr0 .res.b 1 ;0000C4 +ECCR0 .equ 0x00C4 +__escr0 .res.b 1 ;0000C5 +ESCR0 .equ 0x00C5 +__bgr0 ; overlay symbol ;0000C6 +BGR0 .equ 0x00C6 +__bgrl0 .res.b 1 ;0000C6 +BGRL0 .equ 0x00C6 +__bgrh0 .res.b 1 ;0000C7 +BGRH0 .equ 0x00C7 +__esir0 .res.b 1 ;0000C8 +ESIR0 .equ 0x00C8 + .org 0x0000cA +__smr1 .res.b 1 ;0000CA +SMR1 .equ 0x00CA +__scr1 .res.b 1 ;0000CB +SCR1 .equ 0x00CB +__tdr1 ; overlay symbol ;0000CC +TDR1 .equ 0x00CC +__rdr1 .res.b 1 ;0000CC +RDR1 .equ 0x00CC +__ssr1 .res.b 1 ;0000CD +SSR1 .equ 0x00CD +__eccr1 .res.b 1 ;0000CE +ECCR1 .equ 0x00CE +__escr1 .res.b 1 ;0000CF +ESCR1 .equ 0x00CF +__bgr1 ; overlay symbol ;0000D0 +BGR1 .equ 0x00D0 +__bgrl1 .res.b 1 ;0000D0 +BGRL1 .equ 0x00D0 +__bgrh1 .res.b 1 ;0000D1 +BGRH1 .equ 0x00D1 +__esir1 .res.b 1 ;0000D2 +ESIR1 .equ 0x00D2 + .org 0x0000d4 +__smr2 .res.b 1 ;0000D4 +SMR2 .equ 0x00D4 +__scr2 .res.b 1 ;0000D5 +SCR2 .equ 0x00D5 +__tdr2 ; overlay symbol ;0000D6 +TDR2 .equ 0x00D6 +__rdr2 .res.b 1 ;0000D6 +RDR2 .equ 0x00D6 +__ssr2 .res.b 1 ;0000D7 +SSR2 .equ 0x00D7 +__eccr2 .res.b 1 ;0000D8 +ECCR2 .equ 0x00D8 +__escr2 .res.b 1 ;0000D9 +ESCR2 .equ 0x00D9 +__bgr2 ; overlay symbol ;0000DA +BGR2 .equ 0x00DA +__bgrl2 .res.b 1 ;0000DA +BGRL2 .equ 0x00DA +__bgrh2 .res.b 1 ;0000DB +BGRH2 .equ 0x00DB +__esir2 .res.b 1 ;0000DC +ESIR2 .equ 0x00DC + .org 0x0000de +__smr3 .res.b 1 ;0000DE +SMR3 .equ 0x00DE +__scr3 .res.b 1 ;0000DF +SCR3 .equ 0x00DF +__tdr3 ; overlay symbol ;0000E0 +TDR3 .equ 0x00E0 +__rdr3 .res.b 1 ;0000E0 +RDR3 .equ 0x00E0 +__ssr3 .res.b 1 ;0000E1 +SSR3 .equ 0x00E1 +__eccr3 .res.b 1 ;0000E2 +ECCR3 .equ 0x00E2 +__escr3 .res.b 1 ;0000E3 +ESCR3 .equ 0x00E3 +__bgr3 ; overlay symbol ;0000E4 +BGR3 .equ 0x00E4 +__bgrl3 .res.b 1 ;0000E4 +BGRL3 .equ 0x00E4 +__bgrh3 .res.b 1 ;0000E5 +BGRH3 .equ 0x00E5 +__esir3 .res.b 1 ;0000E6 +ESIR3 .equ 0x00E6 + + .section DMADESCRIPTOR, DATA, locate=0x100 ; + .GLOBAL __bapl0, __bapm0, __baph0, __dmacs0, __ioa0, __ioal0 + .GLOBAL __ioah0, __dct0, __dctl0, __dcth0, __bapl1, __bapm1 + .GLOBAL __baph1, __dmacs1, __ioa1, __ioal1, __ioah1, __dct1 + .GLOBAL __dctl1, __dcth1, __bapl2, __bapm2, __baph2, __dmacs2 + .GLOBAL __ioa2, __ioal2, __ioah2, __dct2, __dctl2, __dcth2 + .GLOBAL __bapl3, __bapm3, __baph3, __dmacs3, __ioa3, __ioal3 + .GLOBAL __ioah3, __dct3, __dctl3, __dcth3, __bapl4, __bapm4 + .GLOBAL __baph4, __dmacs4, __ioa4, __ioal4, __ioah4, __dct4 + .GLOBAL __dctl4, __dcth4, __bapl5, __bapm5, __baph5, __dmacs5 + .GLOBAL __ioa5, __ioal5, __ioah5, __dct5, __dctl5, __dcth5 + +__bapl0 .res.b 1 ;000100 +BAPL0 .equ 0x0100 +__bapm0 .res.b 1 ;000101 +BAPM0 .equ 0x0101 +__baph0 .res.b 1 ;000102 +BAPH0 .equ 0x0102 +__dmacs0 .res.b 1 ;000103 +DMACS0 .equ 0x0103 +__ioa0 ; overlay symbol ;000104 +IOA0 .equ 0x0104 +__ioal0 .res.b 1 ;000104 +IOAL0 .equ 0x0104 +__ioah0 .res.b 1 ;000105 +IOAH0 .equ 0x0105 +__dct0 ; overlay symbol ;000106 +DCT0 .equ 0x0106 +__dctl0 .res.b 1 ;000106 +DCTL0 .equ 0x0106 +__dcth0 .res.b 1 ;000107 +DCTH0 .equ 0x0107 +__bapl1 .res.b 1 ;000108 +BAPL1 .equ 0x0108 +__bapm1 .res.b 1 ;000109 +BAPM1 .equ 0x0109 +__baph1 .res.b 1 ;00010A +BAPH1 .equ 0x010A +__dmacs1 .res.b 1 ;00010B +DMACS1 .equ 0x010B +__ioa1 ; overlay symbol ;00010C +IOA1 .equ 0x010C +__ioal1 .res.b 1 ;00010C +IOAL1 .equ 0x010C +__ioah1 .res.b 1 ;00010D +IOAH1 .equ 0x010D +__dct1 ; overlay symbol ;00010E +DCT1 .equ 0x010E +__dctl1 .res.b 1 ;00010E +DCTL1 .equ 0x010E +__dcth1 .res.b 1 ;00010F +DCTH1 .equ 0x010F +__bapl2 .res.b 1 ;000110 +BAPL2 .equ 0x0110 +__bapm2 .res.b 1 ;000111 +BAPM2 .equ 0x0111 +__baph2 .res.b 1 ;000112 +BAPH2 .equ 0x0112 +__dmacs2 .res.b 1 ;000113 +DMACS2 .equ 0x0113 +__ioa2 ; overlay symbol ;000114 +IOA2 .equ 0x0114 +__ioal2 .res.b 1 ;000114 +IOAL2 .equ 0x0114 +__ioah2 .res.b 1 ;000115 +IOAH2 .equ 0x0115 +__dct2 ; overlay symbol ;000116 +DCT2 .equ 0x0116 +__dctl2 .res.b 1 ;000116 +DCTL2 .equ 0x0116 +__dcth2 .res.b 1 ;000117 +DCTH2 .equ 0x0117 +__bapl3 .res.b 1 ;000118 +BAPL3 .equ 0x0118 +__bapm3 .res.b 1 ;000119 +BAPM3 .equ 0x0119 +__baph3 .res.b 1 ;00011A +BAPH3 .equ 0x011A +__dmacs3 .res.b 1 ;00011B +DMACS3 .equ 0x011B +__ioa3 ; overlay symbol ;00011C +IOA3 .equ 0x011C +__ioal3 .res.b 1 ;00011C +IOAL3 .equ 0x011C +__ioah3 .res.b 1 ;00011D +IOAH3 .equ 0x011D +__dct3 ; overlay symbol ;00011E +DCT3 .equ 0x011E +__dctl3 .res.b 1 ;00011E +DCTL3 .equ 0x011E +__dcth3 .res.b 1 ;00011F +DCTH3 .equ 0x011F +__bapl4 .res.b 1 ;000120 +BAPL4 .equ 0x0120 +__bapm4 .res.b 1 ;000121 +BAPM4 .equ 0x0121 +__baph4 .res.b 1 ;000122 +BAPH4 .equ 0x0122 +__dmacs4 .res.b 1 ;000123 +DMACS4 .equ 0x0123 +__ioa4 ; overlay symbol ;000124 +IOA4 .equ 0x0124 +__ioal4 .res.b 1 ;000124 +IOAL4 .equ 0x0124 +__ioah4 .res.b 1 ;000125 +IOAH4 .equ 0x0125 +__dct4 ; overlay symbol ;000126 +DCT4 .equ 0x0126 +__dctl4 .res.b 1 ;000126 +DCTL4 .equ 0x0126 +__dcth4 .res.b 1 ;000127 +DCTH4 .equ 0x0127 +__bapl5 .res.b 1 ;000128 +BAPL5 .equ 0x0128 +__bapm5 .res.b 1 ;000129 +BAPM5 .equ 0x0129 +__baph5 .res.b 1 ;00012A +BAPH5 .equ 0x012A +__dmacs5 .res.b 1 ;00012B +DMACS5 .equ 0x012B +__ioa5 ; overlay symbol ;00012C +IOA5 .equ 0x012C +__ioal5 .res.b 1 ;00012C +IOAL5 .equ 0x012C +__ioah5 .res.b 1 ;00012D +IOAH5 .equ 0x012D +__dct5 ; overlay symbol ;00012E +DCT5 .equ 0x012E +__dctl5 .res.b 1 ;00012E +DCTL5 .equ 0x012E +__dcth5 .res.b 1 ;00012F +DCTH5 .equ 0x012F + + .section IOXTND, DATA, locate=0x380 ; + .GLOBAL __disel0, __disel1, __disel2, __disel3, __disel4, __disel5 + .GLOBAL __dsr, __dsrl, __dsrh, __dssr, __dssrl, __dssrh + .GLOBAL __der, __derl, __derh, __icr, __ilr, __idx + .GLOBAL __tbr, __tbrl, __tbrh, __dirr, __nmi, __edsu2 + .GLOBAL __romm, __edsu, __pfcs0, __pfcs1, __pfcs2, __pfcs3 + .GLOBAL __pfal0, __pfam0, __pfah0, __pfal1, __pfam1, __pfah1 + .GLOBAL __pfal2, __pfam2, __pfah2, __pfal3, __pfam3, __pfah3 + .GLOBAL __pfal4, __pfam4, __pfah4, __pfal5, __pfam5, __pfah5 + .GLOBAL __pfal6, __pfam6, __pfah6, __pfal7, __pfam7, __pfah7 + .GLOBAL __pfd0, __pfdl0, __pfdh0, __pfd1, __pfdl1, __pfdh1 + .GLOBAL __pfd2, __pfdl2, __pfdh2, __pfd3, __pfdl3, __pfdh3 + .GLOBAL __pfd4, __pfdl4, __pfdh4, __pfd5, __pfdl5, __pfdh5 + .GLOBAL __pfd6, __pfdl6, __pfdh6, __pfd7, __pfdl7, __pfdh7 + .GLOBAL __mfmcs, __mfmtc, __mfmtcl, __mfmtch, __sfmcs, __sfmtc + .GLOBAL __sfmtcl, __sfmtch, __fmwc0, __fmwc1, __fmwc2, __fmwc3 + .GLOBAL __fmwc4, __fmwc5, __smcr, __cksr, __ckssr, __ckmr + .GLOBAL __ckfcr, __ckfcrl, __ckfcrh, __pllcr, __pllcrl, __pllcrh + .GLOBAL __rctcr, __mctcr, __rccsrc, __rcr, __rccsr, __wdtc + .GLOBAL __wdtcp, __coar, __cocr0, __cocr1, __cmcr, __cmpr + .GLOBAL __cmprl, __cmprh, __vrcr, __ddr00, __ddr01, __ddr02 + .GLOBAL __ddr03, __ddr04, __ddr05, __ddr06, __ddr07, __ddr08 + .GLOBAL __ddr09, __ddr10, __pier00, __pier01, __pier02, __pier03 + .GLOBAL __pier04, __pier05, __pier06, __pier07, __pier08, __pier09 + .GLOBAL __pier10, __pilr00, __pilr01, __pilr02, __pilr03, __pilr04 + .GLOBAL __pilr05, __pilr06, __pilr07, __pilr08, __pilr09, __pilr10 + .GLOBAL __epilr00, __epilr01, __epilr02, __epilr03, __epilr04, __epilr05 + .GLOBAL __epilr06, __epilr07, __epilr08, __epilr09, __epilr10, __podr00 + .GLOBAL __podr01, __podr02, __podr03, __podr04, __podr05, __podr06 + .GLOBAL __podr07, __podr08, __podr09, __podr10, __phdr08, __phdr09 + .GLOBAL __phdr10, __pucr00, __pucr01, __pucr02, __pucr03, __pucr04 + .GLOBAL __pucr05, __pucr06, __pucr07, __pucr08, __pucr09, __pucr10 + .GLOBAL __epsr00, __epsr01, __epsr02, __epsr03, __epsr04, __epsr05 + .GLOBAL __epsr06, __epsr07, __epsr08, __epsr09, __epsr10, __ader0 + .GLOBAL __ader1, __ader2, __prrr0, __prrr1, __prrr2, __prrr3 + .GLOBAL __prrr4, __prrr5, __prrr6, __prrr7, __prrr8, __prrr9 + .GLOBAL __wtbr0, __wtbrl0, __wtbrh0, __wtbr1, __wtsr, __wtmr + .GLOBAL __wthr, __wtcer, __wtcksr, __wtcr, __wtcrl, __wtcrh + .GLOBAL __cucr, __cutd, __cutdl, __cutdh, __cutr, __cutr2 + .GLOBAL __cutr2l, __cutr2h, __cutr1, __cutr1l, __cutr1h, __tmisr + .GLOBAL __smr7, __scr7, __tdr7, __rdr7, __ssr7, __eccr7 + .GLOBAL __escr7, __bgr7, __bgrl7, __bgrh7, __esir7, __smr8 + .GLOBAL __scr8, __tdr8, __rdr8, __ssr8, __eccr8, __escr8 + .GLOBAL __bgr8, __bgrl8, __bgrh8, __esir8, __smr9, __scr9 + .GLOBAL __tdr9, __rdr9, __ssr9, __eccr9, __escr9, __bgr9 + .GLOBAL __bgrl9, __bgrh9, __esir9, __acsr0, __aecsr0, __acsr1 + .GLOBAL __aecsr1, __ptmr6, __pcsr6, __pdut6, __pcn6, __pcnl6 + .GLOBAL __pcnh6, __ptmr7, __pcsr7, __pdut7, __pcn7, __pcnl7 + .GLOBAL __pcnh7, __gcn12, __gcn1l2, __gcn1h2, __gcn22, __gcn2l2 + .GLOBAL __gcn2h2, __ptmr8, __pcsr8, __pdut8, __pcn8, __pcnl8 + .GLOBAL __pcnh8, __ptmr9, __pcsr9, __pdut9, __pcn9, __pcnl9 + .GLOBAL __pcnh9, __ptmr10, __pcsr10, __pdut10, __pcn10, __pcnl10 + .GLOBAL __pcnh10, __ptmr11, __pcsr11, __pdut11, __pcn11, __pcnl11 + .GLOBAL __pcnh11, __gcn13, __gcn1l3, __gcn1h3, __gcn23, __gcn2l3 + .GLOBAL __gcn2h3, __ptmr12, __pcsr12, __pdut12, __pcn12, __pcnl12 + .GLOBAL __pcnh12, __ptmr13, __pcsr13, __pdut13, __pcn13, __pcnl13 + .GLOBAL __pcnh13, __ptmr14, __pcsr14, __pdut14, __pcn14, __pcnl14 + .GLOBAL __pcnh14, __ptmr15, __pcsr15, __pdut15, __pcn15, __pcnl15 + .GLOBAL __pcnh15, __prrr10, __prrr11, __prrr12, __prrr13, __eac0 + .GLOBAL __eacl0, __each0, __eac1, __eacl1, __each1, __eac2 + .GLOBAL __eacl2, __each2, __eac3, __eacl3, __each3, __eac4 + .GLOBAL __eacl4, __each4, __eac5, __eacl5, __each5, __eas2 + .GLOBAL __eas3, __eas4, __eas5, __ebm, __ebcf, __ebae0 + .GLOBAL __ebae1, __ebae2, __ebcs, __ctrlr0, __ctrlrl0, __ctrlrh0 + .GLOBAL __statr0, __statrl0, __statrh0, __errcnt0, __errcntl0, __errcnth0 + .GLOBAL __btr0, __btrl0, __btrh0, __intr0, __intrl0, __intrh0 + .GLOBAL __testr0, __testrl0, __testrh0, __brper0, __brperl0, __brperh0 + .GLOBAL __if1creq0, __if1creql0, __if1creqh0, __if1cmsk0, __if1cmskl0, __if1cmskh0 + .GLOBAL __if1msk0, __if1msk10, __if1msk1l0, __if1msk1h0, __if1msk20, __if1msk2l0 + .GLOBAL __if1msk2h0, __if1arb0, __if1arb10, __if1arb1l0, __if1arb1h0, __if1arb20 + .GLOBAL __if1arb2l0, __if1arb2h0, __if1mctr0, __if1mctrl0, __if1mctrh0, __if1dta0 + .GLOBAL __if1dta10, __if1dta1l0, __if1dta1h0, __if1dta20, __if1dta2l0, __if1dta2h0 + .GLOBAL __if1dtb0, __if1dtb10, __if1dtb1l0, __if1dtb1h0, __if1dtb20, __if1dtb2l0 + .GLOBAL __if1dtb2h0, __if2creq0, __if2creql0, __if2creqh0, __if2cmsk0, __if2cmskl0 + .GLOBAL __if2cmskh0, __if2msk0, __if2msk10, __if2msk1l0, __if2msk1h0, __if2msk20 + .GLOBAL __if2msk2l0, __if2msk2h0, __if2arb0, __if2arb10, __if2arb1l0, __if2arb1h0 + .GLOBAL __if2arb20, __if2arb2l0, __if2arb2h0, __if2mctr0, __if2mctrl0, __if2mctrh0 + .GLOBAL __if2dta0, __if2dta10, __if2dta1l0, __if2dta1h0, __if2dta20, __if2dta2l0 + .GLOBAL __if2dta2h0, __if2dtb0, __if2dtb10, __if2dtb1l0, __if2dtb1h0, __if2dtb20 + .GLOBAL __if2dtb2l0, __if2dtb2h0, __treqr0, __treqr10, __treqr1l0, __treqr1h0 + .GLOBAL __treqr20, __treqr2l0, __treqr2h0, __newdt0, __newdt10, __newdt1l0 + .GLOBAL __newdt1h0, __newdt20, __newdt2l0, __newdt2h0, __intpnd0, __intpnd10 + .GLOBAL __intpnd1l0, __intpnd1h0, __intpnd20, __intpnd2l0, __intpnd2h0, __msgval0 + .GLOBAL __msgval10, __msgval1l0, __msgval1h0, __msgval20, __msgval2l0, __msgval2h0 + .GLOBAL __coer0, __ctrlr1, __ctrlrl1, __ctrlrh1, __statr1, __statrl1 + .GLOBAL __statrh1, __errcnt1, __errcntl1, __errcnth1, __btr1, __btrl1 + .GLOBAL __btrh1, __intr1, __intrl1, __intrh1, __testr1, __testrl1 + .GLOBAL __testrh1, __brper1, __brperl1, __brperh1, __if1creq1, __if1creql1 + .GLOBAL __if1creqh1, __if1cmsk1, __if1cmskl1, __if1cmskh1, __if1msk1, __if1msk11 + .GLOBAL __if1msk1l1, __if1msk1h1, __if1msk21, __if1msk2l1, __if1msk2h1, __if1arb1 + .GLOBAL __if1arb11, __if1arb1l1, __if1arb1h1, __if1arb21, __if1arb2l1, __if1arb2h1 + .GLOBAL __if1mctr1, __if1mctrl1, __if1mctrh1, __if1dta1, __if1dta11, __if1dta1l1 + .GLOBAL __if1dta1h1, __if1dta21, __if1dta2l1, __if1dta2h1, __if1dtb1, __if1dtb11 + .GLOBAL __if1dtb1l1, __if1dtb1h1, __if1dtb21, __if1dtb2l1, __if1dtb2h1, __if2creq1 + .GLOBAL __if2creql1, __if2creqh1, __if2cmsk1, __if2cmskl1, __if2cmskh1, __if2msk1 + .GLOBAL __if2msk11, __if2msk1l1, __if2msk1h1, __if2msk21, __if2msk2l1, __if2msk2h1 + .GLOBAL __if2arb1, __if2arb11, __if2arb1l1, __if2arb1h1, __if2arb21, __if2arb2l1 + .GLOBAL __if2arb2h1, __if2mctr1, __if2mctrl1, __if2mctrh1, __if2dta1, __if2dta11 + .GLOBAL __if2dta1l1, __if2dta1h1, __if2dta21, __if2dta2l1, __if2dta2h1, __if2dtb1 + .GLOBAL __if2dtb11, __if2dtb1l1, __if2dtb1h1, __if2dtb21, __if2dtb2l1, __if2dtb2h1 + .GLOBAL __treqr1, __treqr11, __treqr1l1, __treqr1h1, __treqr21, __treqr2l1 + .GLOBAL __treqr2h1, __newdt1, __newdt11, __newdt1l1, __newdt1h1, __newdt21 + .GLOBAL __newdt2l1, __newdt2h1, __intpnd1, __intpnd11, __intpnd1l1, __intpnd1h1 + .GLOBAL __intpnd21, __intpnd2l1, __intpnd2h1, __msgval1, __msgval11, __msgval1l1 + .GLOBAL __msgval1h1, __msgval21, __msgval2l1, __msgval2h1, __coer1 + +__disel0 .res.b 1 ;000380 +DISEL0 .equ 0x0380 +__disel1 .res.b 1 ;000381 +DISEL1 .equ 0x0381 +__disel2 .res.b 1 ;000382 +DISEL2 .equ 0x0382 +__disel3 .res.b 1 ;000383 +DISEL3 .equ 0x0383 +__disel4 .res.b 1 ;000384 +DISEL4 .equ 0x0384 +__disel5 .res.b 1 ;000385 +DISEL5 .equ 0x0385 + .org 0x000390 +__dsr ; overlay symbol ;000390 +DSR .equ 0x0390 +__dsrl .res.b 1 ;000390 +DSRL .equ 0x0390 +__dsrh .res.b 1 ;000391 +DSRH .equ 0x0391 +__dssr ; overlay symbol ;000392 +DSSR .equ 0x0392 +__dssrl .res.b 1 ;000392 +DSSRL .equ 0x0392 +__dssrh .res.b 1 ;000393 +DSSRH .equ 0x0393 +__der ; overlay symbol ;000394 +DER .equ 0x0394 +__derl .res.b 1 ;000394 +DERL .equ 0x0394 +__derh .res.b 1 ;000395 +DERH .equ 0x0395 + .org 0x0003a0 +__icr ; overlay symbol ;0003A0 +ICR .equ 0x03A0 +__ilr .res.b 1 ;0003A0 +ILR .equ 0x03A0 +__idx .res.b 1 ;0003A1 +IDX .equ 0x03A1 +__tbr ; overlay symbol ;0003A2 +TBR .equ 0x03A2 +__tbrl .res.b 1 ;0003A2 +TBRL .equ 0x03A2 +__tbrh .res.b 1 ;0003A3 +TBRH .equ 0x03A3 +__dirr .res.b 1 ;0003A4 +DIRR .equ 0x03A4 +__nmi .res.b 1 ;0003A5 +NMI .equ 0x03A5 + .org 0x0003ac +__edsu2 .res.b 2 ;0003AC +EDSU2 .equ 0x03AC +__romm .res.b 1 ;0003AE +ROMM .equ 0x03AE +__edsu .res.b 1 ;0003AF +EDSU .equ 0x03AF +__pfcs0 .res.b 2 ;0003B0 +PFCS0 .equ 0x03B0 +__pfcs1 .res.b 2 ;0003B2 +PFCS1 .equ 0x03B2 +__pfcs2 .res.b 2 ;0003B4 +PFCS2 .equ 0x03B4 +__pfcs3 .res.b 2 ;0003B6 +PFCS3 .equ 0x03B6 +__pfal0 .res.b 1 ;0003B8 +PFAL0 .equ 0x03B8 +__pfam0 .res.b 1 ;0003B9 +PFAM0 .equ 0x03B9 +__pfah0 .res.b 1 ;0003BA +PFAH0 .equ 0x03BA +__pfal1 .res.b 1 ;0003BB +PFAL1 .equ 0x03BB +__pfam1 .res.b 1 ;0003BC +PFAM1 .equ 0x03BC +__pfah1 .res.b 1 ;0003BD +PFAH1 .equ 0x03BD +__pfal2 .res.b 1 ;0003BE +PFAL2 .equ 0x03BE +__pfam2 .res.b 1 ;0003BF +PFAM2 .equ 0x03BF +__pfah2 .res.b 1 ;0003C0 +PFAH2 .equ 0x03C0 +__pfal3 .res.b 1 ;0003C1 +PFAL3 .equ 0x03C1 +__pfam3 .res.b 1 ;0003C2 +PFAM3 .equ 0x03C2 +__pfah3 .res.b 1 ;0003C3 +PFAH3 .equ 0x03C3 +__pfal4 .res.b 1 ;0003C4 +PFAL4 .equ 0x03C4 +__pfam4 .res.b 1 ;0003C5 +PFAM4 .equ 0x03C5 +__pfah4 .res.b 1 ;0003C6 +PFAH4 .equ 0x03C6 +__pfal5 .res.b 1 ;0003C7 +PFAL5 .equ 0x03C7 +__pfam5 .res.b 1 ;0003C8 +PFAM5 .equ 0x03C8 +__pfah5 .res.b 1 ;0003C9 +PFAH5 .equ 0x03C9 +__pfal6 .res.b 1 ;0003CA +PFAL6 .equ 0x03CA +__pfam6 .res.b 1 ;0003CB +PFAM6 .equ 0x03CB +__pfah6 .res.b 1 ;0003CC +PFAH6 .equ 0x03CC +__pfal7 .res.b 1 ;0003CD +PFAL7 .equ 0x03CD +__pfam7 .res.b 1 ;0003CE +PFAM7 .equ 0x03CE +__pfah7 .res.b 1 ;0003CF +PFAH7 .equ 0x03CF +__pfd0 ; overlay symbol ;0003D0 +PFD0 .equ 0x03D0 +__pfdl0 .res.b 1 ;0003D0 +PFDL0 .equ 0x03D0 +__pfdh0 .res.b 1 ;0003D1 +PFDH0 .equ 0x03D1 +__pfd1 ; overlay symbol ;0003D2 +PFD1 .equ 0x03D2 +__pfdl1 .res.b 1 ;0003D2 +PFDL1 .equ 0x03D2 +__pfdh1 .res.b 1 ;0003D3 +PFDH1 .equ 0x03D3 +__pfd2 ; overlay symbol ;0003D4 +PFD2 .equ 0x03D4 +__pfdl2 .res.b 1 ;0003D4 +PFDL2 .equ 0x03D4 +__pfdh2 .res.b 1 ;0003D5 +PFDH2 .equ 0x03D5 +__pfd3 ; overlay symbol ;0003D6 +PFD3 .equ 0x03D6 +__pfdl3 .res.b 1 ;0003D6 +PFDL3 .equ 0x03D6 +__pfdh3 .res.b 1 ;0003D7 +PFDH3 .equ 0x03D7 +__pfd4 ; overlay symbol ;0003D8 +PFD4 .equ 0x03D8 +__pfdl4 .res.b 1 ;0003D8 +PFDL4 .equ 0x03D8 +__pfdh4 .res.b 1 ;0003D9 +PFDH4 .equ 0x03D9 +__pfd5 ; overlay symbol ;0003DA +PFD5 .equ 0x03DA +__pfdl5 .res.b 1 ;0003DA +PFDL5 .equ 0x03DA +__pfdh5 .res.b 1 ;0003DB +PFDH5 .equ 0x03DB +__pfd6 ; overlay symbol ;0003DC +PFD6 .equ 0x03DC +__pfdl6 .res.b 1 ;0003DC +PFDL6 .equ 0x03DC +__pfdh6 .res.b 1 ;0003DD +PFDH6 .equ 0x03DD +__pfd7 ; overlay symbol ;0003DE +PFD7 .equ 0x03DE +__pfdl7 .res.b 1 ;0003DE +PFDL7 .equ 0x03DE +__pfdh7 .res.b 1 ;0003DF +PFDH7 .equ 0x03DF + .org 0x0003f1 +__mfmcs .res.b 1 ;0003F1 +MFMCS .equ 0x03F1 +__mfmtc ; overlay symbol ;0003F2 +MFMTC .equ 0x03F2 +__mfmtcl .res.b 1 ;0003F2 +MFMTCL .equ 0x03F2 +__mfmtch .res.b 1 ;0003F3 +MFMTCH .equ 0x03F3 + .org 0x0003f5 +__sfmcs .res.b 1 ;0003F5 +SFMCS .equ 0x03F5 +__sfmtc ; overlay symbol ;0003F6 +SFMTC .equ 0x03F6 +__sfmtcl .res.b 1 ;0003F6 +SFMTCL .equ 0x03F6 +__sfmtch .res.b 1 ;0003F7 +SFMTCH .equ 0x03F7 +__fmwc0 .res.b 1 ;0003F8 +FMWC0 .equ 0x03F8 +__fmwc1 .res.b 1 ;0003F9 +FMWC1 .equ 0x03F9 +__fmwc2 .res.b 1 ;0003FA +FMWC2 .equ 0x03FA +__fmwc3 .res.b 1 ;0003FB +FMWC3 .equ 0x03FB +__fmwc4 .res.b 1 ;0003FC +FMWC4 .equ 0x03FC +__fmwc5 .res.b 1 ;0003FD +FMWC5 .equ 0x03FD + .org 0x000400 +__smcr .res.b 1 ;000400 +SMCR .equ 0x0400 +__cksr .res.b 1 ;000401 +CKSR .equ 0x0401 +__ckssr .res.b 1 ;000402 +CKSSR .equ 0x0402 +__ckmr .res.b 1 ;000403 +CKMR .equ 0x0403 +__ckfcr ; overlay symbol ;000404 +CKFCR .equ 0x0404 +__ckfcrl .res.b 1 ;000404 +CKFCRL .equ 0x0404 +__ckfcrh .res.b 1 ;000405 +CKFCRH .equ 0x0405 +__pllcr ; overlay symbol ;000406 +PLLCR .equ 0x0406 +__pllcrl .res.b 1 ;000406 +PLLCRL .equ 0x0406 +__pllcrh .res.b 1 ;000407 +PLLCRH .equ 0x0407 +__rctcr .res.b 1 ;000408 +RCTCR .equ 0x0408 +__mctcr .res.b 1 ;000409 +MCTCR .equ 0x0409 + .org 0x00040b +__rccsrc .res.b 1 ;00040B +RCCSRC .equ 0x040B +__rcr .res.b 1 ;00040C +RCR .equ 0x040C +__rccsr .res.b 1 ;00040D +RCCSR .equ 0x040D +__wdtc .res.b 1 ;00040E +WDTC .equ 0x040E +__wdtcp .res.b 1 ;00040F +WDTCP .equ 0x040F + .org 0x000415 +__coar .res.b 1 ;000415 +COAR .equ 0x0415 +__cocr0 .res.b 1 ;000416 +COCR0 .equ 0x0416 +__cocr1 .res.b 1 ;000417 +COCR1 .equ 0x0417 +__cmcr .res.b 1 ;000418 +CMCR .equ 0x0418 + .org 0x00041a +__cmpr ; overlay symbol ;00041A +CMPR .equ 0x041A +__cmprl .res.b 1 ;00041A +CMPRL .equ 0x041A +__cmprh .res.b 1 ;00041B +CMPRH .equ 0x041B + .org 0x00042c +__vrcr .res.b 1 ;00042C +VRCR .equ 0x042C + .org 0x000430 +__ddr00 .res.b 1 ;000430 +DDR00 .equ 0x0430 +__ddr01 .res.b 1 ;000431 +DDR01 .equ 0x0431 +__ddr02 .res.b 1 ;000432 +DDR02 .equ 0x0432 +__ddr03 .res.b 1 ;000433 +DDR03 .equ 0x0433 +__ddr04 .res.b 1 ;000434 +DDR04 .equ 0x0434 +__ddr05 .res.b 1 ;000435 +DDR05 .equ 0x0435 +__ddr06 .res.b 1 ;000436 +DDR06 .equ 0x0436 +__ddr07 .res.b 1 ;000437 +DDR07 .equ 0x0437 +__ddr08 .res.b 1 ;000438 +DDR08 .equ 0x0438 +__ddr09 .res.b 1 ;000439 +DDR09 .equ 0x0439 +__ddr10 .res.b 1 ;00043A +DDR10 .equ 0x043A + .org 0x000444 +__pier00 .res.b 1 ;000444 +PIER00 .equ 0x0444 +__pier01 .res.b 1 ;000445 +PIER01 .equ 0x0445 +__pier02 .res.b 1 ;000446 +PIER02 .equ 0x0446 +__pier03 .res.b 1 ;000447 +PIER03 .equ 0x0447 +__pier04 .res.b 1 ;000448 +PIER04 .equ 0x0448 +__pier05 .res.b 1 ;000449 +PIER05 .equ 0x0449 +__pier06 .res.b 1 ;00044A +PIER06 .equ 0x044A +__pier07 .res.b 1 ;00044B +PIER07 .equ 0x044B +__pier08 .res.b 1 ;00044C +PIER08 .equ 0x044C +__pier09 .res.b 1 ;00044D +PIER09 .equ 0x044D +__pier10 .res.b 1 ;00044E +PIER10 .equ 0x044E + .org 0x000458 +__pilr00 .res.b 1 ;000458 +PILR00 .equ 0x0458 +__pilr01 .res.b 1 ;000459 +PILR01 .equ 0x0459 +__pilr02 .res.b 1 ;00045A +PILR02 .equ 0x045A +__pilr03 .res.b 1 ;00045B +PILR03 .equ 0x045B +__pilr04 .res.b 1 ;00045C +PILR04 .equ 0x045C +__pilr05 .res.b 1 ;00045D +PILR05 .equ 0x045D +__pilr06 .res.b 1 ;00045E +PILR06 .equ 0x045E +__pilr07 .res.b 1 ;00045F +PILR07 .equ 0x045F +__pilr08 .res.b 1 ;000460 +PILR08 .equ 0x0460 +__pilr09 .res.b 1 ;000461 +PILR09 .equ 0x0461 +__pilr10 .res.b 1 ;000462 +PILR10 .equ 0x0462 + .org 0x00046C +__epilr00 .res.b 1 ;00046C +EPILR00 .equ 0x046C +__epilr01 .res.b 1 ;00046D +EPILR01 .equ 0x046D +__epilr02 .res.b 1 ;00046E +EPILR02 .equ 0x046E +__epilr03 .res.b 1 ;00046F +EPILR03 .equ 0x046F +__epilr04 .res.b 1 ;000470 +EPILR04 .equ 0x0470 +__epilr05 .res.b 1 ;000471 +EPILR05 .equ 0x0471 +__epilr06 .res.b 1 ;000472 +EPILR06 .equ 0x0472 +__epilr07 .res.b 1 ;000473 +EPILR07 .equ 0x0473 +__epilr08 .res.b 1 ;000474 +EPILR08 .equ 0x0474 +__epilr09 .res.b 1 ;000475 +EPILR09 .equ 0x0475 +__epilr10 .res.b 1 ;000476 +EPILR10 .equ 0x0476 + .org 0x000480 +__podr00 .res.b 1 ;000480 +PODR00 .equ 0x0480 +__podr01 .res.b 1 ;000481 +PODR01 .equ 0x0481 +__podr02 .res.b 1 ;000482 +PODR02 .equ 0x0482 +__podr03 .res.b 1 ;000483 +PODR03 .equ 0x0483 +__podr04 .res.b 1 ;000484 +PODR04 .equ 0x0484 +__podr05 .res.b 1 ;000485 +PODR05 .equ 0x0485 +__podr06 .res.b 1 ;000486 +PODR06 .equ 0x0486 +__podr07 .res.b 1 ;000487 +PODR07 .equ 0x0487 +__podr08 .res.b 1 ;000488 +PODR08 .equ 0x0488 +__podr09 .res.b 1 ;000489 +PODR09 .equ 0x0489 +__podr10 .res.b 1 ;00048A +PODR10 .equ 0x048A + .org 0x00049C +__phdr08 .res.b 1 ;00049C +PHDR08 .equ 0x049C +__phdr09 .res.b 1 ;00049D +PHDR09 .equ 0x049D +__phdr10 .res.b 1 ;00049E +PHDR10 .equ 0x049E + .org 0x0004A8 +__pucr00 .res.b 1 ;0004A8 +PUCR00 .equ 0x04A8 +__pucr01 .res.b 1 ;0004A9 +PUCR01 .equ 0x04A9 +__pucr02 .res.b 1 ;0004AA +PUCR02 .equ 0x04AA +__pucr03 .res.b 1 ;0004AB +PUCR03 .equ 0x04AB +__pucr04 .res.b 1 ;0004AC +PUCR04 .equ 0x04AC +__pucr05 .res.b 1 ;0004AD +PUCR05 .equ 0x04AD +__pucr06 .res.b 1 ;0004AE +PUCR06 .equ 0x04AE +__pucr07 .res.b 1 ;0004AF +PUCR07 .equ 0x04AF +__pucr08 .res.b 1 ;0004B0 +PUCR08 .equ 0x04B0 +__pucr09 .res.b 1 ;0004B1 +PUCR09 .equ 0x04B1 +__pucr10 .res.b 1 ;0004B2 +PUCR10 .equ 0x04B2 + .org 0x0004BC +__epsr00 .res.b 1 ;0004BC +EPSR00 .equ 0x04BC +__epsr01 .res.b 1 ;0004BD +EPSR01 .equ 0x04BD +__epsr02 .res.b 1 ;0004BE +EPSR02 .equ 0x04BE +__epsr03 .res.b 1 ;0004BF +EPSR03 .equ 0x04BF +__epsr04 .res.b 1 ;0004C0 +EPSR04 .equ 0x04C0 +__epsr05 .res.b 1 ;0004C1 +EPSR05 .equ 0x04C1 +__epsr06 .res.b 1 ;0004C2 +EPSR06 .equ 0x04C2 +__epsr07 .res.b 1 ;0004C3 +EPSR07 .equ 0x04C3 +__epsr08 .res.b 1 ;0004C4 +EPSR08 .equ 0x04C4 +__epsr09 .res.b 1 ;0004C5 +EPSR09 .equ 0x04C5 +__epsr10 .res.b 1 ;0004C6 +EPSR10 .equ 0x04C6 + .org 0x0004d0 +__ader0 .res.b 1 ;0004D0 +ADER0 .equ 0x04D0 +__ader1 .res.b 1 ;0004D1 +ADER1 .equ 0x04D1 +__ader2 .res.b 1 ;0004D2 +ADER2 .equ 0x04D2 + .org 0x0004d6 +__prrr0 .res.b 1 ;0004D6 +PRRR0 .equ 0x04D6 +__prrr1 .res.b 1 ;0004D7 +PRRR1 .equ 0x04D7 +__prrr2 .res.b 1 ;0004D8 +PRRR2 .equ 0x04D8 +__prrr3 .res.b 1 ;0004D9 +PRRR3 .equ 0x04D9 +__prrr4 .res.b 1 ;0004DA +PRRR4 .equ 0x04DA +__prrr5 .res.b 1 ;0004DB +PRRR5 .equ 0x04DB +__prrr6 .res.b 1 ;0004DC +PRRR6 .equ 0x04DC +__prrr7 .res.b 1 ;0004DD +PRRR7 .equ 0x04DD +__prrr8 .res.b 1 ;0004DE +PRRR8 .equ 0x04DE +__prrr9 .res.b 1 ;0004DF +PRRR9 .equ 0x04DF +__wtbr0 ; overlay symbol ;0004E0 +WTBR0 .equ 0x04E0 +__wtbrl0 .res.b 1 ;0004E0 +WTBRL0 .equ 0x04E0 +__wtbrh0 .res.b 1 ;0004E1 +WTBRH0 .equ 0x04E1 +__wtbr1 .res.b 1 ;0004E2 +WTBR1 .equ 0x04E2 +__wtsr .res.b 1 ;0004E3 +WTSR .equ 0x04E3 +__wtmr .res.b 1 ;0004E4 +WTMR .equ 0x04E4 +__wthr .res.b 1 ;0004E5 +WTHR .equ 0x04E5 +__wtcer .res.b 1 ;0004E6 +WTCER .equ 0x04E6 +__wtcksr .res.b 1 ;0004E7 +WTCKSR .equ 0x04E7 +__wtcr ; overlay symbol ;0004E8 +WTCR .equ 0x04E8 +__wtcrl .res.b 1 ;0004E8 +WTCRL .equ 0x04E8 +__wtcrh .res.b 1 ;0004E9 +WTCRH .equ 0x04E9 +__cucr .res.b 1 ;0004EA +CUCR .equ 0x04EA + .org 0x0004ec +__cutd ; overlay symbol ;0004EC +CUTD .equ 0x04EC +__cutdl .res.b 1 ;0004EC +CUTDL .equ 0x04EC +__cutdh .res.b 1 ;0004ED +CUTDH .equ 0x04ED +__cutr ; overlay symbol ;0004EE +CUTR .equ 0x04EE +__cutr2 ; overlay symbol ;0004EE +CUTR2 .equ 0x04EE +__cutr2l .res.b 1 ;0004EE +CUTR2L .equ 0x04EE +__cutr2h .res.b 1 ;0004EF +CUTR2H .equ 0x04EF +__cutr1 ; overlay symbol ;0004F0 +CUTR1 .equ 0x04F0 +__cutr1l .res.b 1 ;0004F0 +CUTR1L .equ 0x04F0 +__cutr1h .res.b 1 ;0004F1 +CUTR1H .equ 0x04F1 + .org 0x0004fa +__tmisr .res.b 1 ;0004FA +TMISR .equ 0x04FA + .org 0x00053e +__smr7 .res.b 1 ;00053E +SMR7 .equ 0x053E +__scr7 .res.b 1 ;00053F +SCR7 .equ 0x053F +__tdr7 ; overlay symbol ;000540 +TDR7 .equ 0x0540 +__rdr7 .res.b 1 ;000540 +RDR7 .equ 0x0540 +__ssr7 .res.b 1 ;000541 +SSR7 .equ 0x0541 +__eccr7 .res.b 1 ;000542 +ECCR7 .equ 0x0542 +__escr7 .res.b 1 ;000543 +ESCR7 .equ 0x0543 +__bgr7 ; overlay symbol ;000544 +BGR7 .equ 0x0544 +__bgrl7 .res.b 1 ;000544 +BGRL7 .equ 0x0544 +__bgrh7 .res.b 1 ;000545 +BGRH7 .equ 0x0545 +__esir7 .res.b 1 ;000546 +ESIR7 .equ 0x0546 + .org 0x000548 +__smr8 .res.b 1 ;000548 +SMR8 .equ 0x0548 +__scr8 .res.b 1 ;000549 +SCR8 .equ 0x0549 +__tdr8 ; overlay symbol ;00054A +TDR8 .equ 0x054A +__rdr8 .res.b 1 ;00054A +RDR8 .equ 0x054A +__ssr8 .res.b 1 ;00054B +SSR8 .equ 0x054B +__eccr8 .res.b 1 ;00054C +ECCR8 .equ 0x054C +__escr8 .res.b 1 ;00054D +ESCR8 .equ 0x054D +__bgr8 ; overlay symbol ;00054E +BGR8 .equ 0x054E +__bgrl8 .res.b 1 ;00054E +BGRL8 .equ 0x054E +__bgrh8 .res.b 1 ;00054F +BGRH8 .equ 0x054F +__esir8 .res.b 1 ;000550 +ESIR8 .equ 0x0550 + .org 0x000552 +__smr9 .res.b 1 ;000552 +SMR9 .equ 0x0552 +__scr9 .res.b 1 ;000553 +SCR9 .equ 0x0553 +__tdr9 ; overlay symbol ;000554 +TDR9 .equ 0x0554 +__rdr9 .res.b 1 ;000554 +RDR9 .equ 0x0554 +__ssr9 .res.b 1 ;000555 +SSR9 .equ 0x0555 +__eccr9 .res.b 1 ;000556 +ECCR9 .equ 0x0556 +__escr9 .res.b 1 ;000557 +ESCR9 .equ 0x0557 +__bgr9 ; overlay symbol ;000558 +BGR9 .equ 0x0558 +__bgrl9 .res.b 1 ;000558 +BGRL9 .equ 0x0558 +__bgrh9 .res.b 1 ;000559 +BGRH9 .equ 0x0559 +__esir9 .res.b 1 ;00055A +ESIR9 .equ 0x055A + .org 0x000560 +__acsr0 .res.b 1 ;000560 +ACSR0 .equ 0x0560 +__aecsr0 .res.b 1 ;000561 +AECSR0 .equ 0x0561 +__acsr1 .res.b 1 ;000562 +ACSR1 .equ 0x0562 +__aecsr1 .res.b 1 ;000563 +AECSR1 .equ 0x0563 +__ptmr6 .res.b 2 ;000564 +PTMR6 .equ 0x0564 +__pcsr6 .res.b 2 ;000566 +PCSR6 .equ 0x0566 +__pdut6 .res.b 2 ;000568 +PDUT6 .equ 0x0568 +__pcn6 ; overlay symbol ;00056A +PCN6 .equ 0x056A +__pcnl6 .res.b 1 ;00056A +PCNL6 .equ 0x056A +__pcnh6 .res.b 1 ;00056B +PCNH6 .equ 0x056B +__ptmr7 .res.b 2 ;00056C +PTMR7 .equ 0x056C +__pcsr7 .res.b 2 ;00056E +PCSR7 .equ 0x056E +__pdut7 .res.b 2 ;000570 +PDUT7 .equ 0x0570 +__pcn7 ; overlay symbol ;000572 +PCN7 .equ 0x0572 +__pcnl7 .res.b 1 ;000572 +PCNL7 .equ 0x0572 +__pcnh7 .res.b 1 ;000573 +PCNH7 .equ 0x0573 +__gcn12 ; overlay symbol ;000574 +GCN12 .equ 0x0574 +__gcn1l2 .res.b 1 ;000574 +GCN1L2 .equ 0x0574 +__gcn1h2 .res.b 1 ;000575 +GCN1H2 .equ 0x0575 +__gcn22 ; overlay symbol ;000576 +GCN22 .equ 0x0576 +__gcn2l2 .res.b 1 ;000576 +GCN2L2 .equ 0x0576 +__gcn2h2 .res.b 1 ;000577 +GCN2H2 .equ 0x0577 +__ptmr8 .res.b 2 ;000578 +PTMR8 .equ 0x0578 +__pcsr8 .res.b 2 ;00057A +PCSR8 .equ 0x057A +__pdut8 .res.b 2 ;00057C +PDUT8 .equ 0x057C +__pcn8 ; overlay symbol ;00057E +PCN8 .equ 0x057E +__pcnl8 .res.b 1 ;00057E +PCNL8 .equ 0x057E +__pcnh8 .res.b 1 ;00057F +PCNH8 .equ 0x057F +__ptmr9 .res.b 2 ;000580 +PTMR9 .equ 0x0580 +__pcsr9 .res.b 2 ;000582 +PCSR9 .equ 0x0582 +__pdut9 .res.b 2 ;000584 +PDUT9 .equ 0x0584 +__pcn9 ; overlay symbol ;000586 +PCN9 .equ 0x0586 +__pcnl9 .res.b 1 ;000586 +PCNL9 .equ 0x0586 +__pcnh9 .res.b 1 ;000587 +PCNH9 .equ 0x0587 +__ptmr10 .res.b 2 ;000588 +PTMR10 .equ 0x0588 +__pcsr10 .res.b 2 ;00058A +PCSR10 .equ 0x058A +__pdut10 .res.b 2 ;00058C +PDUT10 .equ 0x058C +__pcn10 ; overlay symbol ;00058E +PCN10 .equ 0x058E +__pcnl10 .res.b 1 ;00058E +PCNL10 .equ 0x058E +__pcnh10 .res.b 1 ;00058F +PCNH10 .equ 0x058F +__ptmr11 .res.b 2 ;000590 +PTMR11 .equ 0x0590 +__pcsr11 .res.b 2 ;000592 +PCSR11 .equ 0x0592 +__pdut11 .res.b 2 ;000594 +PDUT11 .equ 0x0594 +__pcn11 ; overlay symbol ;000596 +PCN11 .equ 0x0596 +__pcnl11 .res.b 1 ;000596 +PCNL11 .equ 0x0596 +__pcnh11 .res.b 1 ;000597 +PCNH11 .equ 0x0597 +__gcn13 ; overlay symbol ;000598 +GCN13 .equ 0x0598 +__gcn1l3 .res.b 1 ;000598 +GCN1L3 .equ 0x0598 +__gcn1h3 .res.b 1 ;000599 +GCN1H3 .equ 0x0599 +__gcn23 ; overlay symbol ;00059A +GCN23 .equ 0x059A +__gcn2l3 .res.b 1 ;00059A +GCN2L3 .equ 0x059A +__gcn2h3 .res.b 1 ;00059B +GCN2H3 .equ 0x059B +__ptmr12 .res.b 2 ;00059C +PTMR12 .equ 0x059C +__pcsr12 .res.b 2 ;00059E +PCSR12 .equ 0x059E +__pdut12 .res.b 2 ;0005A0 +PDUT12 .equ 0x05A0 +__pcn12 ; overlay symbol ;0005A2 +PCN12 .equ 0x05A2 +__pcnl12 .res.b 1 ;0005A2 +PCNL12 .equ 0x05A2 +__pcnh12 .res.b 1 ;0005A3 +PCNH12 .equ 0x05A3 +__ptmr13 .res.b 2 ;0005A4 +PTMR13 .equ 0x05A4 +__pcsr13 .res.b 2 ;0005A6 +PCSR13 .equ 0x05A6 +__pdut13 .res.b 2 ;0005A8 +PDUT13 .equ 0x05A8 +__pcn13 ; overlay symbol ;0005AA +PCN13 .equ 0x05AA +__pcnl13 .res.b 1 ;0005AA +PCNL13 .equ 0x05AA +__pcnh13 .res.b 1 ;0005AB +PCNH13 .equ 0x05AB +__ptmr14 .res.b 2 ;0005AC +PTMR14 .equ 0x05AC +__pcsr14 .res.b 2 ;0005AE +PCSR14 .equ 0x05AE +__pdut14 .res.b 2 ;0005B0 +PDUT14 .equ 0x05B0 +__pcn14 ; overlay symbol ;0005B2 +PCN14 .equ 0x05B2 +__pcnl14 .res.b 1 ;0005B2 +PCNL14 .equ 0x05B2 +__pcnh14 .res.b 1 ;0005B3 +PCNH14 .equ 0x05B3 +__ptmr15 .res.b 2 ;0005B4 +PTMR15 .equ 0x05B4 +__pcsr15 .res.b 2 ;0005B6 +PCSR15 .equ 0x05B6 +__pdut15 .res.b 2 ;0005B8 +PDUT15 .equ 0x05B8 +__pcn15 ; overlay symbol ;0005BA +PCN15 .equ 0x05BA +__pcnl15 .res.b 1 ;0005BA +PCNL15 .equ 0x05BA +__pcnh15 .res.b 1 ;0005BB +PCNH15 .equ 0x05BB + .org 0x000660 +__prrr10 .res.b 1 ;000660 +PRRR10 .equ 0x0660 +__prrr11 .res.b 1 ;000661 +PRRR11 .equ 0x0661 +__prrr12 .res.b 1 ;000662 +PRRR12 .equ 0x0662 +__prrr13 .res.b 1 ;000663 +PRRR13 .equ 0x0663 + .org 0x0006e0 +__eac0 ; overlay symbol ;0006E0 +EAC0 .equ 0x06E0 +__eacl0 .res.b 1 ;0006E0 +EACL0 .equ 0x06E0 +__each0 .res.b 1 ;0006E1 +EACH0 .equ 0x06E1 +__eac1 ; overlay symbol ;0006E2 +EAC1 .equ 0x06E2 +__eacl1 .res.b 1 ;0006E2 +EACL1 .equ 0x06E2 +__each1 .res.b 1 ;0006E3 +EACH1 .equ 0x06E3 +__eac2 ; overlay symbol ;0006E4 +EAC2 .equ 0x06E4 +__eacl2 .res.b 1 ;0006E4 +EACL2 .equ 0x06E4 +__each2 .res.b 1 ;0006E5 +EACH2 .equ 0x06E5 +__eac3 ; overlay symbol ;0006E6 +EAC3 .equ 0x06E6 +__eacl3 .res.b 1 ;0006E6 +EACL3 .equ 0x06E6 +__each3 .res.b 1 ;0006E7 +EACH3 .equ 0x06E7 +__eac4 ; overlay symbol ;0006E8 +EAC4 .equ 0x06E8 +__eacl4 .res.b 1 ;0006E8 +EACL4 .equ 0x06E8 +__each4 .res.b 1 ;0006E9 +EACH4 .equ 0x06E9 +__eac5 ; overlay symbol ;0006EA +EAC5 .equ 0x06EA +__eacl5 .res.b 1 ;0006EA +EACL5 .equ 0x06EA +__each5 .res.b 1 ;0006EB +EACH5 .equ 0x06EB +__eas2 .res.b 1 ;0006EC +EAS2 .equ 0x06EC +__eas3 .res.b 1 ;0006ED +EAS3 .equ 0x06ED +__eas4 .res.b 1 ;0006EE +EAS4 .equ 0x06EE +__eas5 .res.b 1 ;0006EF +EAS5 .equ 0x06EF +__ebm .res.b 1 ;0006F0 +EBM .equ 0x06F0 +__ebcf .res.b 1 ;0006F1 +EBCF .equ 0x06F1 +__ebae0 .res.b 1 ;0006F2 +EBAE0 .equ 0x06F2 +__ebae1 .res.b 1 ;0006F3 +EBAE1 .equ 0x06F3 +__ebae2 .res.b 1 ;0006F4 +EBAE2 .equ 0x06F4 +__ebcs .res.b 1 ;0006F5 +EBCS .equ 0x06F5 + .org 0x000700 +__ctrlr0 ; overlay symbol ;000700 +CTRLR0 .equ 0x0700 +__ctrlrl0 .res.b 1 ;000700 +CTRLRL0 .equ 0x0700 +__ctrlrh0 .res.b 1 ;000701 +CTRLRH0 .equ 0x0701 +__statr0 ; overlay symbol ;000702 +STATR0 .equ 0x0702 +__statrl0 .res.b 1 ;000702 +STATRL0 .equ 0x0702 +__statrh0 .res.b 1 ;000703 +STATRH0 .equ 0x0703 +__errcnt0 ; overlay symbol ;000704 +ERRCNT0 .equ 0x0704 +__errcntl0 .res.b 1 ;000704 +ERRCNTL0 .equ 0x0704 +__errcnth0 .res.b 1 ;000705 +ERRCNTH0 .equ 0x0705 +__btr0 ; overlay symbol ;000706 +BTR0 .equ 0x0706 +__btrl0 .res.b 1 ;000706 +BTRL0 .equ 0x0706 +__btrh0 .res.b 1 ;000707 +BTRH0 .equ 0x0707 +__intr0 ; overlay symbol ;000708 +INTR0 .equ 0x0708 +__intrl0 .res.b 1 ;000708 +INTRL0 .equ 0x0708 +__intrh0 .res.b 1 ;000709 +INTRH0 .equ 0x0709 +__testr0 ; overlay symbol ;00070A +TESTR0 .equ 0x070A +__testrl0 .res.b 1 ;00070A +TESTRL0 .equ 0x070A +__testrh0 .res.b 1 ;00070B +TESTRH0 .equ 0x070B +__brper0 ; overlay symbol ;00070C +BRPER0 .equ 0x070C +__brperl0 .res.b 1 ;00070C +BRPERL0 .equ 0x070C +__brperh0 .res.b 1 ;00070D +BRPERH0 .equ 0x070D + .org 0x000710 +__if1creq0 ; overlay symbol ;000710 +IF1CREQ0 .equ 0x0710 +__if1creql0 .res.b 1 ;000710 +IF1CREQL0 .equ 0x0710 +__if1creqh0 .res.b 1 ;000711 +IF1CREQH0 .equ 0x0711 +__if1cmsk0 ; overlay symbol ;000712 +IF1CMSK0 .equ 0x0712 +__if1cmskl0 .res.b 1 ;000712 +IF1CMSKL0 .equ 0x0712 +__if1cmskh0 .res.b 1 ;000713 +IF1CMSKH0 .equ 0x0713 +__if1msk0 ; overlay symbol ;000714 +IF1MSK0 .equ 0x0714 +__if1msk10 ; overlay symbol ;000714 +IF1MSK10 .equ 0x0714 +__if1msk1l0 .res.b 1 ;000714 +IF1MSK1L0 .equ 0x0714 +__if1msk1h0 .res.b 1 ;000715 +IF1MSK1H0 .equ 0x0715 +__if1msk20 ; overlay symbol ;000716 +IF1MSK20 .equ 0x0716 +__if1msk2l0 .res.b 1 ;000716 +IF1MSK2L0 .equ 0x0716 +__if1msk2h0 .res.b 1 ;000717 +IF1MSK2H0 .equ 0x0717 +__if1arb0 ; overlay symbol ;000718 +IF1ARB0 .equ 0x0718 +__if1arb10 ; overlay symbol ;000718 +IF1ARB10 .equ 0x0718 +__if1arb1l0 .res.b 1 ;000718 +IF1ARB1L0 .equ 0x0718 +__if1arb1h0 .res.b 1 ;000719 +IF1ARB1H0 .equ 0x0719 +__if1arb20 ; overlay symbol ;00071A +IF1ARB20 .equ 0x071A +__if1arb2l0 .res.b 1 ;00071A +IF1ARB2L0 .equ 0x071A +__if1arb2h0 .res.b 1 ;00071B +IF1ARB2H0 .equ 0x071B +__if1mctr0 ; overlay symbol ;00071C +IF1MCTR0 .equ 0x071C +__if1mctrl0 .res.b 1 ;00071C +IF1MCTRL0 .equ 0x071C +__if1mctrh0 .res.b 1 ;00071D +IF1MCTRH0 .equ 0x071D +__if1dta0 ; overlay symbol ;00071E +IF1DTA0 .equ 0x071E +__if1dta10 ; overlay symbol ;00071E +IF1DTA10 .equ 0x071E +__if1dta1l0 .res.b 1 ;00071E +IF1DTA1L0 .equ 0x071E +__if1dta1h0 .res.b 1 ;00071F +IF1DTA1H0 .equ 0x071F +__if1dta20 ; overlay symbol ;000720 +IF1DTA20 .equ 0x0720 +__if1dta2l0 .res.b 1 ;000720 +IF1DTA2L0 .equ 0x0720 +__if1dta2h0 .res.b 1 ;000721 +IF1DTA2H0 .equ 0x0721 +__if1dtb0 ; overlay symbol ;000722 +IF1DTB0 .equ 0x0722 +__if1dtb10 ; overlay symbol ;000722 +IF1DTB10 .equ 0x0722 +__if1dtb1l0 .res.b 1 ;000722 +IF1DTB1L0 .equ 0x0722 +__if1dtb1h0 .res.b 1 ;000723 +IF1DTB1H0 .equ 0x0723 +__if1dtb20 ; overlay symbol ;000724 +IF1DTB20 .equ 0x0724 +__if1dtb2l0 .res.b 1 ;000724 +IF1DTB2L0 .equ 0x0724 +__if1dtb2h0 .res.b 1 ;000725 +IF1DTB2H0 .equ 0x0725 + .org 0x000740 +__if2creq0 ; overlay symbol ;000740 +IF2CREQ0 .equ 0x0740 +__if2creql0 .res.b 1 ;000740 +IF2CREQL0 .equ 0x0740 +__if2creqh0 .res.b 1 ;000741 +IF2CREQH0 .equ 0x0741 +__if2cmsk0 ; overlay symbol ;000742 +IF2CMSK0 .equ 0x0742 +__if2cmskl0 .res.b 1 ;000742 +IF2CMSKL0 .equ 0x0742 +__if2cmskh0 .res.b 1 ;000743 +IF2CMSKH0 .equ 0x0743 +__if2msk0 ; overlay symbol ;000744 +IF2MSK0 .equ 0x0744 +__if2msk10 ; overlay symbol ;000744 +IF2MSK10 .equ 0x0744 +__if2msk1l0 .res.b 1 ;000744 +IF2MSK1L0 .equ 0x0744 +__if2msk1h0 .res.b 1 ;000745 +IF2MSK1H0 .equ 0x0745 +__if2msk20 ; overlay symbol ;000746 +IF2MSK20 .equ 0x0746 +__if2msk2l0 .res.b 1 ;000746 +IF2MSK2L0 .equ 0x0746 +__if2msk2h0 .res.b 1 ;000747 +IF2MSK2H0 .equ 0x0747 +__if2arb0 ; overlay symbol ;000748 +IF2ARB0 .equ 0x0748 +__if2arb10 ; overlay symbol ;000748 +IF2ARB10 .equ 0x0748 +__if2arb1l0 .res.b 1 ;000748 +IF2ARB1L0 .equ 0x0748 +__if2arb1h0 .res.b 1 ;000749 +IF2ARB1H0 .equ 0x0749 +__if2arb20 ; overlay symbol ;00074A +IF2ARB20 .equ 0x074A +__if2arb2l0 .res.b 1 ;00074A +IF2ARB2L0 .equ 0x074A +__if2arb2h0 .res.b 1 ;00074B +IF2ARB2H0 .equ 0x074B +__if2mctr0 ; overlay symbol ;00074C +IF2MCTR0 .equ 0x074C +__if2mctrl0 .res.b 1 ;00074C +IF2MCTRL0 .equ 0x074C +__if2mctrh0 .res.b 1 ;00074D +IF2MCTRH0 .equ 0x074D +__if2dta0 ; overlay symbol ;00074E +IF2DTA0 .equ 0x074E +__if2dta10 ; overlay symbol ;00074E +IF2DTA10 .equ 0x074E +__if2dta1l0 .res.b 1 ;00074E +IF2DTA1L0 .equ 0x074E +__if2dta1h0 .res.b 1 ;00074F +IF2DTA1H0 .equ 0x074F +__if2dta20 ; overlay symbol ;000750 +IF2DTA20 .equ 0x0750 +__if2dta2l0 .res.b 1 ;000750 +IF2DTA2L0 .equ 0x0750 +__if2dta2h0 .res.b 1 ;000751 +IF2DTA2H0 .equ 0x0751 +__if2dtb0 ; overlay symbol ;000752 +IF2DTB0 .equ 0x0752 +__if2dtb10 ; overlay symbol ;000752 +IF2DTB10 .equ 0x0752 +__if2dtb1l0 .res.b 1 ;000752 +IF2DTB1L0 .equ 0x0752 +__if2dtb1h0 .res.b 1 ;000753 +IF2DTB1H0 .equ 0x0753 +__if2dtb20 ; overlay symbol ;000754 +IF2DTB20 .equ 0x0754 +__if2dtb2l0 .res.b 1 ;000754 +IF2DTB2L0 .equ 0x0754 +__if2dtb2h0 .res.b 1 ;000755 +IF2DTB2H0 .equ 0x0755 + .org 0x000780 +__treqr0 ; overlay symbol ;000780 +TREQR0 .equ 0x0780 +__treqr10 ; overlay symbol ;000780 +TREQR10 .equ 0x0780 +__treqr1l0 .res.b 1 ;000780 +TREQR1L0 .equ 0x0780 +__treqr1h0 .res.b 1 ;000781 +TREQR1H0 .equ 0x0781 +__treqr20 ; overlay symbol ;000782 +TREQR20 .equ 0x0782 +__treqr2l0 .res.b 1 ;000782 +TREQR2L0 .equ 0x0782 +__treqr2h0 .res.b 1 ;000783 +TREQR2H0 .equ 0x0783 + .org 0x000790 +__newdt0 ; overlay symbol ;000790 +NEWDT0 .equ 0x0790 +__newdt10 ; overlay symbol ;000790 +NEWDT10 .equ 0x0790 +__newdt1l0 .res.b 1 ;000790 +NEWDT1L0 .equ 0x0790 +__newdt1h0 .res.b 1 ;000791 +NEWDT1H0 .equ 0x0791 +__newdt20 ; overlay symbol ;000792 +NEWDT20 .equ 0x0792 +__newdt2l0 .res.b 1 ;000792 +NEWDT2L0 .equ 0x0792 +__newdt2h0 .res.b 1 ;000793 +NEWDT2H0 .equ 0x0793 + .org 0x0007A0 +__intpnd0 ; overlay symbol ;0007A0 +INTPND0 .equ 0x07A0 +__intpnd10 ; overlay symbol ;0007A0 +INTPND10 .equ 0x07A0 +__intpnd1l0 .res.b 1 ;0007A0 +INTPND1L0 .equ 0x07A0 +__intpnd1h0 .res.b 1 ;0007A1 +INTPND1H0 .equ 0x07A1 +__intpnd20 ; overlay symbol ;0007A2 +INTPND20 .equ 0x07A2 +__intpnd2l0 .res.b 1 ;0007A2 +INTPND2L0 .equ 0x07A2 +__intpnd2h0 .res.b 1 ;0007A3 +INTPND2H0 .equ 0x07A3 + .org 0x0007B0 +__msgval0 ; overlay symbol ;0007B0 +MSGVAL0 .equ 0x07B0 +__msgval10 ; overlay symbol ;0007B0 +MSGVAL10 .equ 0x07B0 +__msgval1l0 .res.b 1 ;0007B0 +MSGVAL1L0 .equ 0x07B0 +__msgval1h0 .res.b 1 ;0007B1 +MSGVAL1H0 .equ 0x07B1 +__msgval20 ; overlay symbol ;0007B2 +MSGVAL20 .equ 0x07B2 +__msgval2l0 .res.b 1 ;0007B2 +MSGVAL2L0 .equ 0x07B2 +__msgval2h0 .res.b 1 ;0007B3 +MSGVAL2H0 .equ 0x07B3 + .org 0x0007CE +__coer0 .res.b 1 ;0007CE +COER0 .equ 0x07CE + .org 0x000800 +__ctrlr1 ; overlay symbol ;000800 +CTRLR1 .equ 0x0800 +__ctrlrl1 .res.b 1 ;000800 +CTRLRL1 .equ 0x0800 +__ctrlrh1 .res.b 1 ;000801 +CTRLRH1 .equ 0x0801 +__statr1 ; overlay symbol ;000802 +STATR1 .equ 0x0802 +__statrl1 .res.b 1 ;000802 +STATRL1 .equ 0x0802 +__statrh1 .res.b 1 ;000803 +STATRH1 .equ 0x0803 +__errcnt1 ; overlay symbol ;000804 +ERRCNT1 .equ 0x0804 +__errcntl1 .res.b 1 ;000804 +ERRCNTL1 .equ 0x0804 +__errcnth1 .res.b 1 ;000805 +ERRCNTH1 .equ 0x0805 +__btr1 ; overlay symbol ;000806 +BTR1 .equ 0x0806 +__btrl1 .res.b 1 ;000806 +BTRL1 .equ 0x0806 +__btrh1 .res.b 1 ;000807 +BTRH1 .equ 0x0807 +__intr1 ; overlay symbol ;000808 +INTR1 .equ 0x0808 +__intrl1 .res.b 1 ;000808 +INTRL1 .equ 0x0808 +__intrh1 .res.b 1 ;000809 +INTRH1 .equ 0x0809 +__testr1 ; overlay symbol ;00080A +TESTR1 .equ 0x080A +__testrl1 .res.b 1 ;00080A +TESTRL1 .equ 0x080A +__testrh1 .res.b 1 ;00080B +TESTRH1 .equ 0x080B +__brper1 ; overlay symbol ;00080C +BRPER1 .equ 0x080C +__brperl1 .res.b 1 ;00080C +BRPERL1 .equ 0x080C +__brperh1 .res.b 1 ;00080D +BRPERH1 .equ 0x080D + .org 0x000810 +__if1creq1 ; overlay symbol ;000810 +IF1CREQ1 .equ 0x0810 +__if1creql1 .res.b 1 ;000810 +IF1CREQL1 .equ 0x0810 +__if1creqh1 .res.b 1 ;000811 +IF1CREQH1 .equ 0x0811 +__if1cmsk1 ; overlay symbol ;000812 +IF1CMSK1 .equ 0x0812 +__if1cmskl1 .res.b 1 ;000812 +IF1CMSKL1 .equ 0x0812 +__if1cmskh1 .res.b 1 ;000813 +IF1CMSKH1 .equ 0x0813 +__if1msk1 ; overlay symbol ;000814 +IF1MSK1 .equ 0x0814 +__if1msk11 ; overlay symbol ;000814 +IF1MSK11 .equ 0x0814 +__if1msk1l1 .res.b 1 ;000814 +IF1MSK1L1 .equ 0x0814 +__if1msk1h1 .res.b 1 ;000815 +IF1MSK1H1 .equ 0x0815 +__if1msk21 ; overlay symbol ;000816 +IF1MSK21 .equ 0x0816 +__if1msk2l1 .res.b 1 ;000816 +IF1MSK2L1 .equ 0x0816 +__if1msk2h1 .res.b 1 ;000817 +IF1MSK2H1 .equ 0x0817 +__if1arb1 ; overlay symbol ;000818 +IF1ARB1 .equ 0x0818 +__if1arb11 ; overlay symbol ;000818 +IF1ARB11 .equ 0x0818 +__if1arb1l1 .res.b 1 ;000818 +IF1ARB1L1 .equ 0x0818 +__if1arb1h1 .res.b 1 ;000819 +IF1ARB1H1 .equ 0x0819 +__if1arb21 ; overlay symbol ;00081A +IF1ARB21 .equ 0x081A +__if1arb2l1 .res.b 1 ;00081A +IF1ARB2L1 .equ 0x081A +__if1arb2h1 .res.b 1 ;00081B +IF1ARB2H1 .equ 0x081B +__if1mctr1 ; overlay symbol ;00081C +IF1MCTR1 .equ 0x081C +__if1mctrl1 .res.b 1 ;00081C +IF1MCTRL1 .equ 0x081C +__if1mctrh1 .res.b 1 ;00081D +IF1MCTRH1 .equ 0x081D +__if1dta1 ; overlay symbol ;00081E +IF1DTA1 .equ 0x081E +__if1dta11 ; overlay symbol ;00081E +IF1DTA11 .equ 0x081E +__if1dta1l1 .res.b 1 ;00081E +IF1DTA1L1 .equ 0x081E +__if1dta1h1 .res.b 1 ;00081F +IF1DTA1H1 .equ 0x081F +__if1dta21 ; overlay symbol ;000820 +IF1DTA21 .equ 0x0820 +__if1dta2l1 .res.b 1 ;000820 +IF1DTA2L1 .equ 0x0820 +__if1dta2h1 .res.b 1 ;000821 +IF1DTA2H1 .equ 0x0821 +__if1dtb1 ; overlay symbol ;000822 +IF1DTB1 .equ 0x0822 +__if1dtb11 ; overlay symbol ;000822 +IF1DTB11 .equ 0x0822 +__if1dtb1l1 .res.b 1 ;000822 +IF1DTB1L1 .equ 0x0822 +__if1dtb1h1 .res.b 1 ;000823 +IF1DTB1H1 .equ 0x0823 +__if1dtb21 ; overlay symbol ;000824 +IF1DTB21 .equ 0x0824 +__if1dtb2l1 .res.b 1 ;000824 +IF1DTB2L1 .equ 0x0824 +__if1dtb2h1 .res.b 1 ;000825 +IF1DTB2H1 .equ 0x0825 + .org 0x000840 +__if2creq1 ; overlay symbol ;000840 +IF2CREQ1 .equ 0x0840 +__if2creql1 .res.b 1 ;000840 +IF2CREQL1 .equ 0x0840 +__if2creqh1 .res.b 1 ;000841 +IF2CREQH1 .equ 0x0841 +__if2cmsk1 ; overlay symbol ;000842 +IF2CMSK1 .equ 0x0842 +__if2cmskl1 .res.b 1 ;000842 +IF2CMSKL1 .equ 0x0842 +__if2cmskh1 .res.b 1 ;000843 +IF2CMSKH1 .equ 0x0843 +__if2msk1 ; overlay symbol ;000844 +IF2MSK1 .equ 0x0844 +__if2msk11 ; overlay symbol ;000844 +IF2MSK11 .equ 0x0844 +__if2msk1l1 .res.b 1 ;000844 +IF2MSK1L1 .equ 0x0844 +__if2msk1h1 .res.b 1 ;000845 +IF2MSK1H1 .equ 0x0845 +__if2msk21 ; overlay symbol ;000846 +IF2MSK21 .equ 0x0846 +__if2msk2l1 .res.b 1 ;000846 +IF2MSK2L1 .equ 0x0846 +__if2msk2h1 .res.b 1 ;000847 +IF2MSK2H1 .equ 0x0847 +__if2arb1 ; overlay symbol ;000848 +IF2ARB1 .equ 0x0848 +__if2arb11 ; overlay symbol ;000848 +IF2ARB11 .equ 0x0848 +__if2arb1l1 .res.b 1 ;000848 +IF2ARB1L1 .equ 0x0848 +__if2arb1h1 .res.b 1 ;000849 +IF2ARB1H1 .equ 0x0849 +__if2arb21 ; overlay symbol ;00084A +IF2ARB21 .equ 0x084A +__if2arb2l1 .res.b 1 ;00084A +IF2ARB2L1 .equ 0x084A +__if2arb2h1 .res.b 1 ;00084B +IF2ARB2H1 .equ 0x084B +__if2mctr1 ; overlay symbol ;00084C +IF2MCTR1 .equ 0x084C +__if2mctrl1 .res.b 1 ;00084C +IF2MCTRL1 .equ 0x084C +__if2mctrh1 .res.b 1 ;00084D +IF2MCTRH1 .equ 0x084D +__if2dta1 ; overlay symbol ;00084E +IF2DTA1 .equ 0x084E +__if2dta11 ; overlay symbol ;00084E +IF2DTA11 .equ 0x084E +__if2dta1l1 .res.b 1 ;00084E +IF2DTA1L1 .equ 0x084E +__if2dta1h1 .res.b 1 ;00084F +IF2DTA1H1 .equ 0x084F +__if2dta21 ; overlay symbol ;000850 +IF2DTA21 .equ 0x0850 +__if2dta2l1 .res.b 1 ;000850 +IF2DTA2L1 .equ 0x0850 +__if2dta2h1 .res.b 1 ;000851 +IF2DTA2H1 .equ 0x0851 +__if2dtb1 ; overlay symbol ;000852 +IF2DTB1 .equ 0x0852 +__if2dtb11 ; overlay symbol ;000852 +IF2DTB11 .equ 0x0852 +__if2dtb1l1 .res.b 1 ;000852 +IF2DTB1L1 .equ 0x0852 +__if2dtb1h1 .res.b 1 ;000853 +IF2DTB1H1 .equ 0x0853 +__if2dtb21 ; overlay symbol ;000854 +IF2DTB21 .equ 0x0854 +__if2dtb2l1 .res.b 1 ;000854 +IF2DTB2L1 .equ 0x0854 +__if2dtb2h1 .res.b 1 ;000855 +IF2DTB2H1 .equ 0x0855 + .org 0x000880 +__treqr1 ; overlay symbol ;000880 +TREQR1 .equ 0x0880 +__treqr11 ; overlay symbol ;000880 +TREQR11 .equ 0x0880 +__treqr1l1 .res.b 1 ;000880 +TREQR1L1 .equ 0x0880 +__treqr1h1 .res.b 1 ;000881 +TREQR1H1 .equ 0x0881 +__treqr21 ; overlay symbol ;000882 +TREQR21 .equ 0x0882 +__treqr2l1 .res.b 1 ;000882 +TREQR2L1 .equ 0x0882 +__treqr2h1 .res.b 1 ;000883 +TREQR2H1 .equ 0x0883 + .org 0x000890 +__newdt1 ; overlay symbol ;000890 +NEWDT1 .equ 0x0890 +__newdt11 ; overlay symbol ;000890 +NEWDT11 .equ 0x0890 +__newdt1l1 .res.b 1 ;000890 +NEWDT1L1 .equ 0x0890 +__newdt1h1 .res.b 1 ;000891 +NEWDT1H1 .equ 0x0891 +__newdt21 ; overlay symbol ;000892 +NEWDT21 .equ 0x0892 +__newdt2l1 .res.b 1 ;000892 +NEWDT2L1 .equ 0x0892 +__newdt2h1 .res.b 1 ;000893 +NEWDT2H1 .equ 0x0893 + .org 0x0008A0 +__intpnd1 ; overlay symbol ;0008A0 +INTPND1 .equ 0x08A0 +__intpnd11 ; overlay symbol ;0008A0 +INTPND11 .equ 0x08A0 +__intpnd1l1 .res.b 1 ;0008A0 +INTPND1L1 .equ 0x08A0 +__intpnd1h1 .res.b 1 ;0008A1 +INTPND1H1 .equ 0x08A1 +__intpnd21 ; overlay symbol ;0008A2 +INTPND21 .equ 0x08A2 +__intpnd2l1 .res.b 1 ;0008A2 +INTPND2L1 .equ 0x08A2 +__intpnd2h1 .res.b 1 ;0008A3 +INTPND2H1 .equ 0x08A3 + .org 0x0008B0 +__msgval1 ; overlay symbol ;0008B0 +MSGVAL1 .equ 0x08B0 +__msgval11 ; overlay symbol ;0008B0 +MSGVAL11 .equ 0x08B0 +__msgval1l1 .res.b 1 ;0008B0 +MSGVAL1L1 .equ 0x08B0 +__msgval1h1 .res.b 1 ;0008B1 +MSGVAL1H1 .equ 0x08B1 +__msgval21 ; overlay symbol ;0008B2 +MSGVAL21 .equ 0x08B2 +__msgval2l1 .res.b 1 ;0008B2 +MSGVAL2L1 .equ 0x08B2 +__msgval2h1 .res.b 1 ;0008B3 +MSGVAL2H1 .equ 0x08B3 + .org 0x0008CE +__coer1 .res.b 1 ;0008CE +COER1 .equ 0x08CE + + + .end diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Src/mb96348hs.h b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Src/mb96348hs.h new file mode 100644 index 000000000..8803c2337 --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Src/mb96348hs.h @@ -0,0 +1,23746 @@ +/* FFMC-16 IO-MAP HEADER FILE */ +/* ========================== */ +/* SOFTUNE WORKBENCH FORMAT */ +/* C-DEFINITIONS FOR IO-SYMBOLS */ +/* CREATED BY IO-WIZARD V2.27 */ +/* $Id: mb96348hs.h,v 1.7 2007/09/20 14:23:33 mwilla Exp $ */ +/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ +/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ +/* ELIGIBILITY FOR ANY PURPOSES. */ +/* (C) Fujitsu Microelectronics Europe GmbH */ +/* ************************************************************************* */ +/* FUJITSU MICROELECTRONICS EUROPE GMBH */ +/* Pittlerstrasse 47, 63225 Langen, Germany */ +/* Tel.:++49/6103/690-0,Fax - 122 */ +/* */ +/* The following software is for demonstration purposes only. */ +/* It is not fully tested, nor validated in order to fullfill */ +/* its task under all circumstances. Therefore, this software */ +/* or any part of it must only be used in an evaluation */ +/* laboratory environment. */ +/* This software is subject to the rules of our standard */ +/* DISCLAIMER, that is delivered with our SW-tools on the CD or DVD */ +/* "Micros Documentation & Software" (V3.4 or later) or */ +/* see our Internet Page - */ +/* http://emea.fujitsu.com/microelectronics */ +/* ************************************************************************* */ +/* */ +/* NOTE: */ +/* */ +/* This header-file covers all features of the chip MB96F348HS. */ +/* */ +/* */ +/* ---------------------------------------------------------------------- */ +/* History: */ +/* Date Version Author Description */ +/* 22.12.2006 1.0 PHu Initial Release: derived from headerfile of */ +/* MB96348RS and added Satellite Flash, removed */ +/* RTC, Clock Calibration, LIN-USART7-9 */ +/* 16.01.2007 1.1 PHu Add 32-bit access names for CAN where */ +/* appropriate */ +/* 09.02.2007 1.3 PHu skip version 1.2 to be in line with CVS */ +/* numbering */ +/* correct addresses of LIN-UART3 registers */ +/* allow only 16 bit access for the ADSR */ +/* 12.04.2007 1.4 Mef Added Voltage Regulator Control Register */ +/* Added RD19V bit in Flash Memory Control */ +/* Status Register */ +/* 03.05.2007 1.5 Mef Added LIN USART 7,8,9 */ +/* 15.05.2007 1.6 Mef Added RTC */ +/* 20.09.2007 1.7 MWi Completely revised version */ + + +#ifndef __MB96XXX_H +# define __MB96XXX_H +/* +- Please define __IO_NEAR in LARGE and COMPACT memory model, if the default + data bank (DTB) is 00. This will result in better performance in these + models. +- Please define __IO_FAR in SMALL and MEDIUM memory model, if the default + data bank (DTB) is other than 00. This might be the case in systems with + external RAM, which are not using internal RAM as default data area. +- Please define neither __IO_NEAR nor __IO_FAR in all other cases. This + will work with almost all configurations. +*/ + +# ifdef __IO_NEAR +# ifdef __IO_FAR +# error __IO_NEAR and __IO_FAR must not be defined at the same time +# else +# define ___IOWIDTH __near +# endif +# else +# ifdef __IO_FAR +# define ___IOWIDTH __far +# else /* specified by memory model */ +# define ___IOWIDTH +# endif +# endif +# ifdef __IO_DEFINE +# define __IO_EXTERN +# define __IO_EXTENDED volatile ___IOWIDTH +# else +# define __IO_EXTERN extern /* for data, which can have __io */ +# define __IO_EXTENDED extern volatile ___IOWIDTH +# endif + +typedef unsigned char IO_BYTE; +typedef unsigned short IO_WORD; +typedef unsigned long IO_LWORD; +typedef const unsigned short IO_WORD_READ; + +/* REGISTER BIT STRUCTURES */ + +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _P0 :1; + IO_BYTE _P1 :1; + IO_BYTE _P2 :1; + IO_BYTE _P3 :1; + IO_BYTE _P4 :1; + IO_BYTE _P5 :1; + IO_BYTE _P6 :1; + IO_BYTE _P7 :1; + }bit; + }PDR00STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _P0 :1; + IO_BYTE _P1 :1; + IO_BYTE _P2 :1; + IO_BYTE _P3 :1; + IO_BYTE _P4 :1; + IO_BYTE _P5 :1; + IO_BYTE _P6 :1; + IO_BYTE _P7 :1; + }bit; + }PDR01STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _P0 :1; + IO_BYTE _P1 :1; + IO_BYTE _P2 :1; + IO_BYTE _P3 :1; + IO_BYTE _P4 :1; + IO_BYTE _P5 :1; + IO_BYTE _P6 :1; + IO_BYTE _P7 :1; + }bit; + }PDR02STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _P0 :1; + IO_BYTE _P1 :1; + IO_BYTE _P2 :1; + IO_BYTE _P3 :1; + IO_BYTE _P4 :1; + IO_BYTE _P5 :1; + IO_BYTE _P6 :1; + IO_BYTE _P7 :1; + }bit; + }PDR03STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _P0 :1; + IO_BYTE _P1 :1; + IO_BYTE _P2 :1; + IO_BYTE _P3 :1; + IO_BYTE _P4 :1; + IO_BYTE _P5 :1; + IO_BYTE _P6 :1; + IO_BYTE _P7 :1; + }bit; + }PDR04STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _P0 :1; + IO_BYTE _P1 :1; + IO_BYTE _P2 :1; + IO_BYTE _P3 :1; + IO_BYTE _P4 :1; + IO_BYTE _P5 :1; + IO_BYTE _P6 :1; + IO_BYTE _P7 :1; + }bit; + }PDR05STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _P0 :1; + IO_BYTE _P1 :1; + IO_BYTE _P2 :1; + IO_BYTE _P3 :1; + IO_BYTE _P4 :1; + IO_BYTE _P5 :1; + IO_BYTE _P6 :1; + IO_BYTE _P7 :1; + }bit; + }PDR06STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _P0 :1; + IO_BYTE _P1 :1; + IO_BYTE _P2 :1; + IO_BYTE _P3 :1; + IO_BYTE _P4 :1; + IO_BYTE _P5 :1; + IO_BYTE _P6 :1; + IO_BYTE _P7 :1; + }bit; + }PDR07STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _P0 :1; + IO_BYTE _P1 :1; + IO_BYTE _P2 :1; + IO_BYTE _P3 :1; + IO_BYTE _P4 :1; + IO_BYTE _P5 :1; + IO_BYTE _P6 :1; + IO_BYTE _P7 :1; + }bit; + }PDR08STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _P0 :1; + IO_BYTE _P1 :1; + IO_BYTE _P2 :1; + IO_BYTE _P3 :1; + IO_BYTE _P4 :1; + IO_BYTE _P5 :1; + IO_BYTE _P6 :1; + IO_BYTE _P7 :1; + }bit; + }PDR09STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _P0 :1; + IO_BYTE _P1 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }PDR10STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _resv :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _S10 :1; + IO_WORD _MD0 :1; + IO_WORD _MD1 :1; + IO_WORD :1; + IO_WORD _STRT :1; + IO_WORD _STS0 :1; + IO_WORD _STS1 :1; + IO_WORD _PAUS :1; + IO_WORD _INTE :1; + IO_WORD _INT :1; + IO_WORD _BUSY :1; + }bit; + struct{ + IO_WORD :6; + IO_WORD _MD :2; + IO_WORD :2; + IO_WORD _STS :2; + }bitc; + }ADCSSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _resv :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _S10 :1; + IO_BYTE _MD0 :1; + IO_BYTE _MD1 :1; + }bit; + struct{ + IO_BYTE :6; + IO_BYTE _MD :2; + }bitc; + }ADCSLSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _STRT :1; + IO_BYTE _STS0 :1; + IO_BYTE _STS1 :1; + IO_BYTE _PAUS :1; + IO_BYTE _INTE :1; + IO_BYTE _INT :1; + IO_BYTE _BUSY :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _STS :2; + }bitc; + }ADCSHSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD _D :10; + }bitc; + }ADCRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D0 :1; + IO_BYTE _D1 :1; + IO_BYTE _D2 :1; + IO_BYTE _D3 :1; + IO_BYTE _D4 :1; + IO_BYTE _D5 :1; + IO_BYTE _D6 :1; + IO_BYTE _D7 :1; + }bit; + }ADCRLSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D8 :1; + IO_BYTE _D9 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }ADCRHSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _ANE0 :1; + IO_WORD _ANE1 :1; + IO_WORD _ANE2 :1; + IO_WORD _ANE3 :1; + IO_WORD _ANE4 :1; + IO_WORD _ANS0 :1; + IO_WORD _ANS1 :1; + IO_WORD _ANS2 :1; + IO_WORD _ANS3 :1; + IO_WORD _ANS4 :1; + IO_WORD _CT0 :1; + IO_WORD _CT1 :1; + IO_WORD _CT2 :1; + IO_WORD _ST0 :1; + IO_WORD _ST1 :1; + IO_WORD _ST2 :1; + }bit; + }ADSRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ADSEL :1; + IO_BYTE _HSEL :1; + IO_BYTE _LSEL :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }ADECRSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _T0 :1; + IO_WORD _T1 :1; + IO_WORD _T2 :1; + IO_WORD _T3 :1; + IO_WORD _T4 :1; + IO_WORD _T5 :1; + IO_WORD _T6 :1; + IO_WORD _T7 :1; + IO_WORD _T8 :1; + IO_WORD _T9 :1; + IO_WORD _T10 :1; + IO_WORD _T11 :1; + IO_WORD _T12 :1; + IO_WORD _T13 :1; + IO_WORD _T14 :1; + IO_WORD _T15 :1; + }bit; + struct{ + IO_WORD _T :16; + }bitc; + }TCDT0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CLK0 :1; + IO_WORD _CLK1 :1; + IO_WORD _CLK2 :1; + IO_WORD _CLR :1; + IO_WORD _MODE :1; + IO_WORD _STOP :1; + IO_WORD _IVFE :1; + IO_WORD _IVF :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _FSEL :1; + IO_WORD _ECKE :1; + }bit; + struct{ + IO_WORD _CLK :3; + }bitc; + }TCCS0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CLK0 :1; + IO_BYTE _CLK1 :1; + IO_BYTE _CLK2 :1; + IO_BYTE _CLR :1; + IO_BYTE _MODE :1; + IO_BYTE _STOP :1; + IO_BYTE _IVFE :1; + IO_BYTE _IVF :1; + }bit; + struct{ + IO_BYTE _CLK :3; + }bitc; + }TCCSL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _FSEL :1; + IO_BYTE _ECKE :1; + }bit; + }TCCSH0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _T0 :1; + IO_WORD _T1 :1; + IO_WORD _T2 :1; + IO_WORD _T3 :1; + IO_WORD _T4 :1; + IO_WORD _T5 :1; + IO_WORD _T6 :1; + IO_WORD _T7 :1; + IO_WORD _T8 :1; + IO_WORD _T9 :1; + IO_WORD _T10 :1; + IO_WORD _T11 :1; + IO_WORD _T12 :1; + IO_WORD _T13 :1; + IO_WORD _T14 :1; + IO_WORD _T15 :1; + }bit; + struct{ + IO_WORD _T :16; + }bitc; + }TCDT1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CLK0 :1; + IO_WORD _CLK1 :1; + IO_WORD _CLK2 :1; + IO_WORD _CLR :1; + IO_WORD _MODE :1; + IO_WORD _STOP :1; + IO_WORD _IVFE :1; + IO_WORD _IVF :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _FSEL :1; + IO_WORD _ECKE :1; + }bit; + struct{ + IO_WORD _CLK :3; + }bitc; + }TCCS1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CLK0 :1; + IO_BYTE _CLK1 :1; + IO_BYTE _CLK2 :1; + IO_BYTE _CLR :1; + IO_BYTE _MODE :1; + IO_BYTE _STOP :1; + IO_BYTE _IVFE :1; + IO_BYTE _IVF :1; + }bit; + struct{ + IO_BYTE _CLK :3; + }bitc; + }TCCSL1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _FSEL :1; + IO_BYTE _ECKE :1; + }bit; + }TCCSH1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CST0 :1; + IO_BYTE _CST1 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICE0 :1; + IO_BYTE _ICE1 :1; + IO_BYTE _ICP0 :1; + IO_BYTE _ICP1 :1; + }bit; + }OCS0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OTD0 :1; + IO_BYTE _OTD1 :1; + IO_BYTE _OTE0 :1; + IO_BYTE _OTE1 :1; + IO_BYTE _CMOD0 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CMOD1 :1; + }bit; + }OCS1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _C00 :1; + IO_WORD _C01 :1; + IO_WORD _C02 :1; + IO_WORD _C03 :1; + IO_WORD _C04 :1; + IO_WORD _C05 :1; + IO_WORD _C06 :1; + IO_WORD _C07 :1; + IO_WORD _C08 :1; + IO_WORD _C09 :1; + IO_WORD _C10 :1; + IO_WORD _C11 :1; + IO_WORD _C12 :1; + IO_WORD _C13 :1; + IO_WORD _C14 :1; + IO_WORD _C15 :1; + }bit; + struct{ + IO_WORD _C0 :16; + }bitc; + }OCCP0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _C00 :1; + IO_WORD _C01 :1; + IO_WORD _C02 :1; + IO_WORD _C03 :1; + IO_WORD _C04 :1; + IO_WORD _C05 :1; + IO_WORD _C06 :1; + IO_WORD _C07 :1; + IO_WORD _C08 :1; + IO_WORD _C09 :1; + IO_WORD _C10 :1; + IO_WORD _C11 :1; + IO_WORD _C12 :1; + IO_WORD _C13 :1; + IO_WORD _C14 :1; + IO_WORD _C15 :1; + }bit; + struct{ + IO_WORD _C0 :16; + }bitc; + }OCCP1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CST2 :1; + IO_BYTE _CST3 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICE2 :1; + IO_BYTE _ICE3 :1; + IO_BYTE _ICP2 :1; + IO_BYTE _ICP3 :1; + }bit; + }OCS2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OTD2 :1; + IO_BYTE _OTD3 :1; + IO_BYTE _OTE2 :1; + IO_BYTE _OTE3 :1; + IO_BYTE _CMOD0 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CMOD1 :1; + }bit; + }OCS3STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _C00 :1; + IO_WORD _C01 :1; + IO_WORD _C02 :1; + IO_WORD _C03 :1; + IO_WORD _C04 :1; + IO_WORD _C05 :1; + IO_WORD _C06 :1; + IO_WORD _C07 :1; + IO_WORD _C08 :1; + IO_WORD _C09 :1; + IO_WORD _C10 :1; + IO_WORD _C11 :1; + IO_WORD _C12 :1; + IO_WORD _C13 :1; + IO_WORD _C14 :1; + IO_WORD _C15 :1; + }bit; + struct{ + IO_WORD _C0 :16; + }bitc; + }OCCP2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _C00 :1; + IO_WORD _C01 :1; + IO_WORD _C02 :1; + IO_WORD _C03 :1; + IO_WORD _C04 :1; + IO_WORD _C05 :1; + IO_WORD _C06 :1; + IO_WORD _C07 :1; + IO_WORD _C08 :1; + IO_WORD _C09 :1; + IO_WORD _C10 :1; + IO_WORD _C11 :1; + IO_WORD _C12 :1; + IO_WORD _C13 :1; + IO_WORD _C14 :1; + IO_WORD _C15 :1; + }bit; + struct{ + IO_WORD _C0 :16; + }bitc; + }OCCP3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CST4 :1; + IO_BYTE _CST5 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICE4 :1; + IO_BYTE _ICE5 :1; + IO_BYTE _ICP4 :1; + IO_BYTE _ICP5 :1; + }bit; + }OCS4STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OTD4 :1; + IO_BYTE _OTD5 :1; + IO_BYTE _OTE4 :1; + IO_BYTE _OTE5 :1; + IO_BYTE _CMOD0 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CMOD1 :1; + }bit; + }OCS5STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _C00 :1; + IO_WORD _C01 :1; + IO_WORD _C02 :1; + IO_WORD _C03 :1; + IO_WORD _C04 :1; + IO_WORD _C05 :1; + IO_WORD _C06 :1; + IO_WORD _C07 :1; + IO_WORD _C08 :1; + IO_WORD _C09 :1; + IO_WORD _C10 :1; + IO_WORD _C11 :1; + IO_WORD _C12 :1; + IO_WORD _C13 :1; + IO_WORD _C14 :1; + IO_WORD _C15 :1; + }bit; + struct{ + IO_WORD _C0 :16; + }bitc; + }OCCP4STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _C00 :1; + IO_WORD _C01 :1; + IO_WORD _C02 :1; + IO_WORD _C03 :1; + IO_WORD _C04 :1; + IO_WORD _C05 :1; + IO_WORD _C06 :1; + IO_WORD _C07 :1; + IO_WORD _C08 :1; + IO_WORD _C09 :1; + IO_WORD _C10 :1; + IO_WORD _C11 :1; + IO_WORD _C12 :1; + IO_WORD _C13 :1; + IO_WORD _C14 :1; + IO_WORD _C15 :1; + }bit; + struct{ + IO_WORD _C0 :16; + }bitc; + }OCCP5STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CST6 :1; + IO_BYTE _CST7 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICE6 :1; + IO_BYTE _ICE7 :1; + IO_BYTE _ICP6 :1; + IO_BYTE _ICP7 :1; + }bit; + }OCS6STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OTD6 :1; + IO_BYTE _OTD7 :1; + IO_BYTE _OTE6 :1; + IO_BYTE _OTE7 :1; + IO_BYTE _CMOD0 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CMOD1 :1; + }bit; + }OCS7STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _C00 :1; + IO_WORD _C01 :1; + IO_WORD _C02 :1; + IO_WORD _C03 :1; + IO_WORD _C04 :1; + IO_WORD _C05 :1; + IO_WORD _C06 :1; + IO_WORD _C07 :1; + IO_WORD _C08 :1; + IO_WORD _C09 :1; + IO_WORD _C10 :1; + IO_WORD _C11 :1; + IO_WORD _C12 :1; + IO_WORD _C13 :1; + IO_WORD _C14 :1; + IO_WORD _C15 :1; + }bit; + struct{ + IO_WORD _C0 :16; + }bitc; + }OCCP6STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _C00 :1; + IO_WORD _C01 :1; + IO_WORD _C02 :1; + IO_WORD _C03 :1; + IO_WORD _C04 :1; + IO_WORD _C05 :1; + IO_WORD _C06 :1; + IO_WORD _C07 :1; + IO_WORD _C08 :1; + IO_WORD _C09 :1; + IO_WORD _C10 :1; + IO_WORD _C11 :1; + IO_WORD _C12 :1; + IO_WORD _C13 :1; + IO_WORD _C14 :1; + IO_WORD _C15 :1; + }bit; + struct{ + IO_WORD _C0 :16; + }bitc; + }OCCP7STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EG00 :1; + IO_BYTE _EG01 :1; + IO_BYTE _EG10 :1; + IO_BYTE _EG11 :1; + IO_BYTE _ICE0 :1; + IO_BYTE _ICE1 :1; + IO_BYTE _ICP0 :1; + IO_BYTE _ICP1 :1; + }bit; + struct{ + IO_BYTE _EG0 :2; + IO_BYTE _EG1 :2; + }bitc; + }ICS01STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IEI0 :1; + IO_BYTE _IEI1 :1; + IO_BYTE _ICUS0 :1; + IO_BYTE :1; + IO_BYTE _ICUS1 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }ICE01STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CP00 :1; + IO_WORD _CP01 :1; + IO_WORD _CP02 :1; + IO_WORD _CP03 :1; + IO_WORD _CP04 :1; + IO_WORD _CP05 :1; + IO_WORD _CP06 :1; + IO_WORD _CP07 :1; + IO_WORD _CP08 :1; + IO_WORD _CP09 :1; + IO_WORD _CP10 :1; + IO_WORD _CP11 :1; + IO_WORD _CP12 :1; + IO_WORD _CP13 :1; + IO_WORD _CP14 :1; + IO_WORD _CP15 :1; + }bit; + struct{ + IO_WORD _CP0 :16; + }bitc; + }IPCP0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CP00 :1; + IO_BYTE _CP01 :1; + IO_BYTE _CP02 :1; + IO_BYTE _CP03 :1; + IO_BYTE _CP04 :1; + IO_BYTE _CP05 :1; + IO_BYTE _CP06 :1; + IO_BYTE _CP07 :1; + }bit; + }IPCPL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CP08 :1; + IO_BYTE _CP09 :1; + IO_BYTE _CP10 :1; + IO_BYTE _CP11 :1; + IO_BYTE _CP12 :1; + IO_BYTE _CP13 :1; + IO_BYTE _CP14 :1; + IO_BYTE _CP15 :1; + }bit; + }IPCPH0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CP00 :1; + IO_WORD _CP01 :1; + IO_WORD _CP02 :1; + IO_WORD _CP03 :1; + IO_WORD _CP04 :1; + IO_WORD _CP05 :1; + IO_WORD _CP06 :1; + IO_WORD _CP07 :1; + IO_WORD _CP08 :1; + IO_WORD _CP09 :1; + IO_WORD _CP10 :1; + IO_WORD _CP11 :1; + IO_WORD _CP12 :1; + IO_WORD _CP13 :1; + IO_WORD _CP14 :1; + IO_WORD _CP15 :1; + }bit; + struct{ + IO_WORD _CP0 :16; + }bitc; + }IPCP1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CP00 :1; + IO_BYTE _CP01 :1; + IO_BYTE _CP02 :1; + IO_BYTE _CP03 :1; + IO_BYTE _CP04 :1; + IO_BYTE _CP05 :1; + IO_BYTE _CP06 :1; + IO_BYTE _CP07 :1; + }bit; + }IPCPL1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CP08 :1; + IO_BYTE _CP09 :1; + IO_BYTE _CP10 :1; + IO_BYTE _CP11 :1; + IO_BYTE _CP12 :1; + IO_BYTE _CP13 :1; + IO_BYTE _CP14 :1; + IO_BYTE _CP15 :1; + }bit; + }IPCPH1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EG20 :1; + IO_BYTE _EG21 :1; + IO_BYTE _EG30 :1; + IO_BYTE _EG31 :1; + IO_BYTE _ICE2 :1; + IO_BYTE _ICE3 :1; + IO_BYTE _ICP2 :1; + IO_BYTE _ICP3 :1; + }bit; + struct{ + IO_BYTE _EG2 :2; + IO_BYTE _EG3 :2; + }bitc; + }ICS23STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IEI2 :1; + IO_BYTE _IEI3 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }ICE23STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CP00 :1; + IO_WORD _CP01 :1; + IO_WORD _CP02 :1; + IO_WORD _CP03 :1; + IO_WORD _CP04 :1; + IO_WORD _CP05 :1; + IO_WORD _CP06 :1; + IO_WORD _CP07 :1; + IO_WORD _CP08 :1; + IO_WORD _CP09 :1; + IO_WORD _CP10 :1; + IO_WORD _CP11 :1; + IO_WORD _CP12 :1; + IO_WORD _CP13 :1; + IO_WORD _CP14 :1; + IO_WORD _CP15 :1; + }bit; + struct{ + IO_WORD _CP0 :16; + }bitc; + }IPCP2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CP00 :1; + IO_BYTE _CP01 :1; + IO_BYTE _CP02 :1; + IO_BYTE _CP03 :1; + IO_BYTE _CP04 :1; + IO_BYTE _CP05 :1; + IO_BYTE _CP06 :1; + IO_BYTE _CP07 :1; + }bit; + }IPCPL2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CP08 :1; + IO_BYTE _CP09 :1; + IO_BYTE _CP10 :1; + IO_BYTE _CP11 :1; + IO_BYTE _CP12 :1; + IO_BYTE _CP13 :1; + IO_BYTE _CP14 :1; + IO_BYTE _CP15 :1; + }bit; + }IPCPH2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CP00 :1; + IO_WORD _CP01 :1; + IO_WORD _CP02 :1; + IO_WORD _CP03 :1; + IO_WORD _CP04 :1; + IO_WORD _CP05 :1; + IO_WORD _CP06 :1; + IO_WORD _CP07 :1; + IO_WORD _CP08 :1; + IO_WORD _CP09 :1; + IO_WORD _CP10 :1; + IO_WORD _CP11 :1; + IO_WORD _CP12 :1; + IO_WORD _CP13 :1; + IO_WORD _CP14 :1; + IO_WORD _CP15 :1; + }bit; + struct{ + IO_WORD _CP0 :16; + }bitc; + }IPCP3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CP00 :1; + IO_BYTE _CP01 :1; + IO_BYTE _CP02 :1; + IO_BYTE _CP03 :1; + IO_BYTE _CP04 :1; + IO_BYTE _CP05 :1; + IO_BYTE _CP06 :1; + IO_BYTE _CP07 :1; + }bit; + }IPCPL3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CP08 :1; + IO_BYTE _CP09 :1; + IO_BYTE _CP10 :1; + IO_BYTE _CP11 :1; + IO_BYTE _CP12 :1; + IO_BYTE _CP13 :1; + IO_BYTE _CP14 :1; + IO_BYTE _CP15 :1; + }bit; + }IPCPH3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EG40 :1; + IO_BYTE _EG41 :1; + IO_BYTE _EG50 :1; + IO_BYTE _EG51 :1; + IO_BYTE _ICE4 :1; + IO_BYTE _ICE5 :1; + IO_BYTE _ICP4 :1; + IO_BYTE _ICP5 :1; + }bit; + struct{ + IO_BYTE _EG4 :2; + IO_BYTE _EG5 :2; + }bitc; + }ICS45STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IEI4 :1; + IO_BYTE _IEI5 :1; + IO_BYTE _ICUS4 :1; + IO_BYTE :1; + IO_BYTE _ICUS5 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }ICE45STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CP00 :1; + IO_WORD _CP01 :1; + IO_WORD _CP02 :1; + IO_WORD _CP03 :1; + IO_WORD _CP04 :1; + IO_WORD _CP05 :1; + IO_WORD _CP06 :1; + IO_WORD _CP07 :1; + IO_WORD _CP08 :1; + IO_WORD _CP09 :1; + IO_WORD _CP10 :1; + IO_WORD _CP11 :1; + IO_WORD _CP12 :1; + IO_WORD _CP13 :1; + IO_WORD _CP14 :1; + IO_WORD _CP15 :1; + }bit; + struct{ + IO_WORD _CP0 :16; + }bitc; + }IPCP4STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CP00 :1; + IO_BYTE _CP01 :1; + IO_BYTE _CP02 :1; + IO_BYTE _CP03 :1; + IO_BYTE _CP04 :1; + IO_BYTE _CP05 :1; + IO_BYTE _CP06 :1; + IO_BYTE _CP07 :1; + }bit; + }IPCPL4STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CP08 :1; + IO_BYTE _CP09 :1; + IO_BYTE _CP10 :1; + IO_BYTE _CP11 :1; + IO_BYTE _CP12 :1; + IO_BYTE _CP13 :1; + IO_BYTE _CP14 :1; + IO_BYTE _CP15 :1; + }bit; + }IPCPH4STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CP00 :1; + IO_WORD _CP01 :1; + IO_WORD _CP02 :1; + IO_WORD _CP03 :1; + IO_WORD _CP04 :1; + IO_WORD _CP05 :1; + IO_WORD _CP06 :1; + IO_WORD _CP07 :1; + IO_WORD _CP08 :1; + IO_WORD _CP09 :1; + IO_WORD _CP10 :1; + IO_WORD _CP11 :1; + IO_WORD _CP12 :1; + IO_WORD _CP13 :1; + IO_WORD _CP14 :1; + IO_WORD _CP15 :1; + }bit; + struct{ + IO_WORD _CP0 :16; + }bitc; + }IPCP5STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CP00 :1; + IO_BYTE _CP01 :1; + IO_BYTE _CP02 :1; + IO_BYTE _CP03 :1; + IO_BYTE _CP04 :1; + IO_BYTE _CP05 :1; + IO_BYTE _CP06 :1; + IO_BYTE _CP07 :1; + }bit; + }IPCPL5STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CP08 :1; + IO_BYTE _CP09 :1; + IO_BYTE _CP10 :1; + IO_BYTE _CP11 :1; + IO_BYTE _CP12 :1; + IO_BYTE _CP13 :1; + IO_BYTE _CP14 :1; + IO_BYTE _CP15 :1; + }bit; + }IPCPH5STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EG60 :1; + IO_BYTE _EG61 :1; + IO_BYTE _EG70 :1; + IO_BYTE _EG71 :1; + IO_BYTE _ICE6 :1; + IO_BYTE _ICE7 :1; + IO_BYTE _ICP6 :1; + IO_BYTE _ICP7 :1; + }bit; + struct{ + IO_BYTE _EG6 :2; + IO_BYTE _EG7 :2; + }bitc; + }ICS67STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IEI6 :1; + IO_BYTE _IEI7 :1; + IO_BYTE _ICUS6 :1; + IO_BYTE :1; + IO_BYTE _ICUS7 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }ICE67STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CP00 :1; + IO_WORD _CP01 :1; + IO_WORD _CP02 :1; + IO_WORD _CP03 :1; + IO_WORD _CP04 :1; + IO_WORD _CP05 :1; + IO_WORD _CP06 :1; + IO_WORD _CP07 :1; + IO_WORD _CP08 :1; + IO_WORD _CP09 :1; + IO_WORD _CP10 :1; + IO_WORD _CP11 :1; + IO_WORD _CP12 :1; + IO_WORD _CP13 :1; + IO_WORD _CP14 :1; + IO_WORD _CP15 :1; + }bit; + struct{ + IO_WORD _CP0 :16; + }bitc; + }IPCP6STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CP00 :1; + IO_BYTE _CP01 :1; + IO_BYTE _CP02 :1; + IO_BYTE _CP03 :1; + IO_BYTE _CP04 :1; + IO_BYTE _CP05 :1; + IO_BYTE _CP06 :1; + IO_BYTE _CP07 :1; + }bit; + }IPCPL6STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CP08 :1; + IO_BYTE _CP09 :1; + IO_BYTE _CP10 :1; + IO_BYTE _CP11 :1; + IO_BYTE _CP12 :1; + IO_BYTE _CP13 :1; + IO_BYTE _CP14 :1; + IO_BYTE _CP15 :1; + }bit; + }IPCPH6STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CP00 :1; + IO_WORD _CP01 :1; + IO_WORD _CP02 :1; + IO_WORD _CP03 :1; + IO_WORD _CP04 :1; + IO_WORD _CP05 :1; + IO_WORD _CP06 :1; + IO_WORD _CP07 :1; + IO_WORD _CP08 :1; + IO_WORD _CP09 :1; + IO_WORD _CP10 :1; + IO_WORD _CP11 :1; + IO_WORD _CP12 :1; + IO_WORD _CP13 :1; + IO_WORD _CP14 :1; + IO_WORD _CP15 :1; + }bit; + struct{ + IO_WORD _CP0 :16; + }bitc; + }IPCP7STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CP00 :1; + IO_BYTE _CP01 :1; + IO_BYTE _CP02 :1; + IO_BYTE _CP03 :1; + IO_BYTE _CP04 :1; + IO_BYTE _CP05 :1; + IO_BYTE _CP06 :1; + IO_BYTE _CP07 :1; + }bit; + }IPCPL7STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CP08 :1; + IO_BYTE _CP09 :1; + IO_BYTE _CP10 :1; + IO_BYTE _CP11 :1; + IO_BYTE _CP12 :1; + IO_BYTE _CP13 :1; + IO_BYTE _CP14 :1; + IO_BYTE _CP15 :1; + }bit; + }IPCPH7STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EN0 :1; + IO_BYTE _EN1 :1; + IO_BYTE _EN2 :1; + IO_BYTE _EN3 :1; + IO_BYTE _EN4 :1; + IO_BYTE _EN5 :1; + IO_BYTE _EN6 :1; + IO_BYTE _EN7 :1; + }bit; + }ENIR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ER0 :1; + IO_BYTE _ER1 :1; + IO_BYTE _ER2 :1; + IO_BYTE _ER3 :1; + IO_BYTE _ER4 :1; + IO_BYTE _ER5 :1; + IO_BYTE _ER6 :1; + IO_BYTE _ER7 :1; + }bit; + }EIRR0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _LA0 :1; + IO_WORD _LB0 :1; + IO_WORD _LA1 :1; + IO_WORD _LB1 :1; + IO_WORD _LA2 :1; + IO_WORD _LB2 :1; + IO_WORD _LA3 :1; + IO_WORD _LB3 :1; + IO_WORD _LA4 :1; + IO_WORD _LB4 :1; + IO_WORD _LA5 :1; + IO_WORD _LB5 :1; + IO_WORD _LA6 :1; + IO_WORD _LB6 :1; + IO_WORD _LA7 :1; + IO_WORD _LB7 :1; + }bit; + }ELVR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _LA0 :1; + IO_BYTE _LB0 :1; + IO_BYTE _LA1 :1; + IO_BYTE _LB1 :1; + IO_BYTE _LA2 :1; + IO_BYTE _LB2 :1; + IO_BYTE _LA3 :1; + IO_BYTE _LB3 :1; + }bit; + }ELVRL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _LA4 :1; + IO_BYTE _LB4 :1; + IO_BYTE _LA5 :1; + IO_BYTE _LB5 :1; + IO_BYTE _LA6 :1; + IO_BYTE _LB6 :1; + IO_BYTE _LA7 :1; + IO_BYTE _LB7 :1; + }bit; + }ELVRH0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EN8 :1; + IO_BYTE _EN9 :1; + IO_BYTE _EN10 :1; + IO_BYTE _EN11 :1; + IO_BYTE _EN12 :1; + IO_BYTE _EN13 :1; + IO_BYTE _EN14 :1; + IO_BYTE _EN15 :1; + }bit; + }ENIR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ER8 :1; + IO_BYTE _ER9 :1; + IO_BYTE _ER10 :1; + IO_BYTE _ER11 :1; + IO_BYTE _ER12 :1; + IO_BYTE _ER13 :1; + IO_BYTE _ER14 :1; + IO_BYTE _ER15 :1; + }bit; + }EIRR1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _LA8 :1; + IO_WORD _LB8 :1; + IO_WORD _LA9 :1; + IO_WORD _LB9 :1; + IO_WORD _LA10 :1; + IO_WORD _LB10 :1; + IO_WORD _LA11 :1; + IO_WORD _LB11 :1; + IO_WORD _LA12 :1; + IO_WORD _LB12 :1; + IO_WORD _LA13 :1; + IO_WORD _LB13 :1; + IO_WORD _LA14 :1; + IO_WORD _LB14 :1; + IO_WORD _LA15 :1; + IO_WORD _LB15 :1; + }bit; + }ELVR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _LA8 :1; + IO_BYTE _LB8 :1; + IO_BYTE _LA9 :1; + IO_BYTE _LB9 :1; + IO_BYTE _LA10 :1; + IO_BYTE _LB10 :1; + IO_BYTE _LA11 :1; + IO_BYTE _LB11 :1; + }bit; + }ELVRL1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _LA12 :1; + IO_BYTE _LB12 :1; + IO_BYTE _LA13 :1; + IO_BYTE _LB13 :1; + IO_BYTE _LA14 :1; + IO_BYTE _LB14 :1; + IO_BYTE _LA15 :1; + IO_BYTE _LB15 :1; + }bit; + }ELVRH1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _TRG :1; + IO_WORD _CNTE :1; + IO_WORD _UF :1; + IO_WORD _INTE :1; + IO_WORD _RELD :1; + IO_WORD _OUTL :1; + IO_WORD _OUTE :1; + IO_WORD _MOD0 :1; + IO_WORD _MOD1 :1; + IO_WORD _MOD2 :1; + IO_WORD _CSL0 :1; + IO_WORD _CSL1 :1; + IO_WORD _FSEL :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD :10; + IO_WORD _CSL :2; + }bitc; + }TMCSR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TRG :1; + IO_BYTE _CNTE :1; + IO_BYTE _UF :1; + IO_BYTE _INTE :1; + IO_BYTE _RELD :1; + IO_BYTE _OUTL :1; + IO_BYTE _OUTE :1; + IO_BYTE _MOD0 :1; + }bit; + }TMCSRL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MOD1 :1; + IO_BYTE _MOD2 :1; + IO_BYTE _CSL0 :1; + IO_BYTE _CSL1 :1; + IO_BYTE _FSEL :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _CSL :2; + }bitc; + }TMCSRH0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _TRG :1; + IO_WORD _CNTE :1; + IO_WORD _UF :1; + IO_WORD _INTE :1; + IO_WORD _RELD :1; + IO_WORD _OUTL :1; + IO_WORD _OUTE :1; + IO_WORD _MOD0 :1; + IO_WORD _MOD1 :1; + IO_WORD _MOD2 :1; + IO_WORD _CSL0 :1; + IO_WORD _CSL1 :1; + IO_WORD _FSEL :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD :10; + IO_WORD _CSL :2; + }bitc; + }TMCSR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TRG :1; + IO_BYTE _CNTE :1; + IO_BYTE _UF :1; + IO_BYTE _INTE :1; + IO_BYTE _RELD :1; + IO_BYTE _OUTL :1; + IO_BYTE _OUTE :1; + IO_BYTE _MOD0 :1; + }bit; + }TMCSRL1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MOD1 :1; + IO_BYTE _MOD2 :1; + IO_BYTE _CSL0 :1; + IO_BYTE _CSL1 :1; + IO_BYTE _FSEL :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _CSL :2; + }bitc; + }TMCSRH1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _TRG :1; + IO_WORD _CNTE :1; + IO_WORD _UF :1; + IO_WORD _INTE :1; + IO_WORD _RELD :1; + IO_WORD _OUTL :1; + IO_WORD _OUTE :1; + IO_WORD _MOD0 :1; + IO_WORD _MOD1 :1; + IO_WORD _MOD2 :1; + IO_WORD _CSL0 :1; + IO_WORD _CSL1 :1; + IO_WORD _FSEL :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD :10; + IO_WORD _CSL :2; + }bitc; + }TMCSR2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TRG :1; + IO_BYTE _CNTE :1; + IO_BYTE _UF :1; + IO_BYTE _INTE :1; + IO_BYTE _RELD :1; + IO_BYTE _OUTL :1; + IO_BYTE _OUTE :1; + IO_BYTE _MOD0 :1; + }bit; + }TMCSRL2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MOD1 :1; + IO_BYTE _MOD2 :1; + IO_BYTE _CSL0 :1; + IO_BYTE _CSL1 :1; + IO_BYTE _FSEL :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _CSL :2; + }bitc; + }TMCSRH2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _TRG :1; + IO_WORD _CNTE :1; + IO_WORD _UF :1; + IO_WORD _INTE :1; + IO_WORD _RELD :1; + IO_WORD _OUTL :1; + IO_WORD _OUTE :1; + IO_WORD _MOD0 :1; + IO_WORD _MOD1 :1; + IO_WORD _MOD2 :1; + IO_WORD _CSL0 :1; + IO_WORD _CSL1 :1; + IO_WORD _FSEL :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD :10; + IO_WORD _CSL :2; + }bitc; + }TMCSR3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TRG :1; + IO_BYTE _CNTE :1; + IO_BYTE _UF :1; + IO_BYTE _INTE :1; + IO_BYTE _RELD :1; + IO_BYTE _OUTL :1; + IO_BYTE _OUTE :1; + IO_BYTE _MOD0 :1; + }bit; + }TMCSRL3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MOD1 :1; + IO_BYTE _MOD2 :1; + IO_BYTE _CSL0 :1; + IO_BYTE _CSL1 :1; + IO_BYTE _FSEL :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _CSL :2; + }bitc; + }TMCSRH3STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _TRG :1; + IO_WORD _CNTE :1; + IO_WORD _UF :1; + IO_WORD _INTE :1; + IO_WORD _RELD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _MOD0 :1; + IO_WORD _MOD1 :1; + IO_WORD _MOD2 :1; + IO_WORD _CSL0 :1; + IO_WORD _CSL1 :1; + IO_WORD _FSEL :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD :10; + IO_WORD _CSL :2; + }bitc; + }TMCSR6STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TRG :1; + IO_BYTE _CNTE :1; + IO_BYTE _UF :1; + IO_BYTE _INTE :1; + IO_BYTE _RELD :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _MOD0 :1; + }bit; + }TMCSRL6STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MOD1 :1; + IO_BYTE _MOD2 :1; + IO_BYTE _CSL0 :1; + IO_BYTE _CSL1 :1; + IO_BYTE _FSEL :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _CSL :2; + }bitc; + }TMCSRH6STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _TSEL00 :1; + IO_WORD _TSEL01 :1; + IO_WORD _TSEL02 :1; + IO_WORD _TSEL03 :1; + IO_WORD _TSEL10 :1; + IO_WORD _TSEL11 :1; + IO_WORD _TSEL12 :1; + IO_WORD _TSEL13 :1; + IO_WORD _TSEL20 :1; + IO_WORD _TSEL21 :1; + IO_WORD _TSEL22 :1; + IO_WORD _TSEL23 :1; + IO_WORD _TSEL30 :1; + IO_WORD _TSEL31 :1; + IO_WORD _TSEL32 :1; + IO_WORD _TSEL33 :1; + }bit; + struct{ + IO_WORD _TSEL0 :4; + IO_WORD _TSEL1 :4; + IO_WORD _TSEL2 :4; + IO_WORD _TSEL3 :4; + }bitc; + }GCN10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TSEL00 :1; + IO_BYTE _TSEL01 :1; + IO_BYTE _TSEL02 :1; + IO_BYTE _TSEL03 :1; + IO_BYTE _TSEL10 :1; + IO_BYTE _TSEL11 :1; + IO_BYTE _TSEL12 :1; + IO_BYTE _TSEL13 :1; + }bit; + struct{ + IO_BYTE _TSEL0 :4; + IO_BYTE _TSEL1 :4; + }bitc; + }GCN1L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TSEL20 :1; + IO_BYTE _TSEL21 :1; + IO_BYTE _TSEL22 :1; + IO_BYTE _TSEL23 :1; + IO_BYTE _TSEL30 :1; + IO_BYTE _TSEL31 :1; + IO_BYTE _TSEL32 :1; + IO_BYTE _TSEL33 :1; + }bit; + struct{ + IO_BYTE _TSEL2 :4; + IO_BYTE _TSEL3 :4; + }bitc; + }GCN1H0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _EN0 :1; + IO_WORD _EN1 :1; + IO_WORD _EN2 :1; + IO_WORD _EN3 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CKSEL0 :1; + IO_WORD _CKSEL1 :1; + IO_WORD _CKSEL2 :1; + IO_WORD _CKSEL3 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD _EN :4; + IO_WORD :4; + IO_WORD _CKSEL :4; + }bitc; + }GCN20STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EN0 :1; + IO_BYTE _EN1 :1; + IO_BYTE _EN2 :1; + IO_BYTE _EN3 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _EN :4; + }bitc; + }GCN2L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CKSEL0 :1; + IO_BYTE _CKSEL1 :1; + IO_BYTE _CKSEL2 :1; + IO_BYTE _CKSEL3 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _CKSEL :4; + }bitc; + }GCN2H0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PTMR0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PCSR0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PDUT0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _OSEL :1; + IO_WORD _OE :1; + IO_WORD _IRS0 :1; + IO_WORD _IRS1 :1; + IO_WORD _IRQF :1; + IO_WORD _IREN :1; + IO_WORD _EGS0 :1; + IO_WORD _EGS1 :1; + IO_WORD :1; + IO_WORD _PGMS :1; + IO_WORD _CKS0 :1; + IO_WORD _CKS1 :1; + IO_WORD _RTRG :1; + IO_WORD _MDSE :1; + IO_WORD _STGR :1; + IO_WORD _CNTE :1; + }bit; + struct{ + IO_WORD :2; + IO_WORD _IRS :2; + IO_WORD :2; + IO_WORD _EGS :2; + IO_WORD :2; + IO_WORD _CKS :2; + }bitc; + }PCN0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OSEL :1; + IO_BYTE _OE :1; + IO_BYTE _IRS0 :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRQF :1; + IO_BYTE _IREN :1; + IO_BYTE _EGS0 :1; + IO_BYTE _EGS1 :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _IRS :2; + IO_BYTE :2; + IO_BYTE _EGS :2; + }bitc; + }PCNL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _PGMS :1; + IO_BYTE _CKS0 :1; + IO_BYTE _CKS1 :1; + IO_BYTE _RTRG :1; + IO_BYTE _MDSE :1; + IO_BYTE _STGR :1; + IO_BYTE _CNTE :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _CKS :2; + }bitc; + }PCNH0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PTMR1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PCSR1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PDUT1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _OSEL :1; + IO_WORD _OE :1; + IO_WORD _IRS0 :1; + IO_WORD _IRS1 :1; + IO_WORD _IRQF :1; + IO_WORD _IREN :1; + IO_WORD _EGS0 :1; + IO_WORD _EGS1 :1; + IO_WORD :1; + IO_WORD _PGMS :1; + IO_WORD _CKS0 :1; + IO_WORD _CKS1 :1; + IO_WORD _RTRG :1; + IO_WORD _MDSE :1; + IO_WORD _STGR :1; + IO_WORD _CNTE :1; + }bit; + struct{ + IO_WORD :2; + IO_WORD _IRS :2; + IO_WORD :2; + IO_WORD _EGS :2; + IO_WORD :2; + IO_WORD _CKS :2; + }bitc; + }PCN1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OSEL :1; + IO_BYTE _OE :1; + IO_BYTE _IRS0 :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRQF :1; + IO_BYTE _IREN :1; + IO_BYTE _EGS0 :1; + IO_BYTE _EGS1 :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _IRS :2; + IO_BYTE :2; + IO_BYTE _EGS :2; + }bitc; + }PCNL1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _PGMS :1; + IO_BYTE _CKS0 :1; + IO_BYTE _CKS1 :1; + IO_BYTE _RTRG :1; + IO_BYTE _MDSE :1; + IO_BYTE _STGR :1; + IO_BYTE _CNTE :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _CKS :2; + }bitc; + }PCNH1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PTMR2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PCSR2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PDUT2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _OSEL :1; + IO_WORD _OE :1; + IO_WORD _IRS0 :1; + IO_WORD _IRS1 :1; + IO_WORD _IRQF :1; + IO_WORD _IREN :1; + IO_WORD _EGS0 :1; + IO_WORD _EGS1 :1; + IO_WORD :1; + IO_WORD _PGMS :1; + IO_WORD _CKS0 :1; + IO_WORD _CKS1 :1; + IO_WORD _RTRG :1; + IO_WORD _MDSE :1; + IO_WORD _STGR :1; + IO_WORD _CNTE :1; + }bit; + struct{ + IO_WORD :2; + IO_WORD _IRS :2; + IO_WORD :2; + IO_WORD _EGS :2; + IO_WORD :2; + IO_WORD _CKS :2; + }bitc; + }PCN2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OSEL :1; + IO_BYTE _OE :1; + IO_BYTE _IRS0 :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRQF :1; + IO_BYTE _IREN :1; + IO_BYTE _EGS0 :1; + IO_BYTE _EGS1 :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _IRS :2; + IO_BYTE :2; + IO_BYTE _EGS :2; + }bitc; + }PCNL2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _PGMS :1; + IO_BYTE _CKS0 :1; + IO_BYTE _CKS1 :1; + IO_BYTE _RTRG :1; + IO_BYTE _MDSE :1; + IO_BYTE _STGR :1; + IO_BYTE _CNTE :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _CKS :2; + }bitc; + }PCNH2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PTMR3STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PCSR3STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PDUT3STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _OSEL :1; + IO_WORD _OE :1; + IO_WORD _IRS0 :1; + IO_WORD _IRS1 :1; + IO_WORD _IRQF :1; + IO_WORD _IREN :1; + IO_WORD _EGS0 :1; + IO_WORD _EGS1 :1; + IO_WORD :1; + IO_WORD _PGMS :1; + IO_WORD _CKS0 :1; + IO_WORD _CKS1 :1; + IO_WORD _RTRG :1; + IO_WORD _MDSE :1; + IO_WORD _STGR :1; + IO_WORD _CNTE :1; + }bit; + struct{ + IO_WORD :2; + IO_WORD _IRS :2; + IO_WORD :2; + IO_WORD _EGS :2; + IO_WORD :2; + IO_WORD _CKS :2; + }bitc; + }PCN3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OSEL :1; + IO_BYTE _OE :1; + IO_BYTE _IRS0 :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRQF :1; + IO_BYTE _IREN :1; + IO_BYTE _EGS0 :1; + IO_BYTE _EGS1 :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _IRS :2; + IO_BYTE :2; + IO_BYTE _EGS :2; + }bitc; + }PCNL3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _PGMS :1; + IO_BYTE _CKS0 :1; + IO_BYTE _CKS1 :1; + IO_BYTE _RTRG :1; + IO_BYTE _MDSE :1; + IO_BYTE _STGR :1; + IO_BYTE _CNTE :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _CKS :2; + }bitc; + }PCNH3STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _TSEL00 :1; + IO_WORD _TSEL01 :1; + IO_WORD _TSEL02 :1; + IO_WORD _TSEL03 :1; + IO_WORD _TSEL10 :1; + IO_WORD _TSEL11 :1; + IO_WORD _TSEL12 :1; + IO_WORD _TSEL13 :1; + IO_WORD _TSEL20 :1; + IO_WORD _TSEL21 :1; + IO_WORD _TSEL22 :1; + IO_WORD _TSEL23 :1; + IO_WORD _TSEL30 :1; + IO_WORD _TSEL31 :1; + IO_WORD _TSEL32 :1; + IO_WORD _TSEL33 :1; + }bit; + struct{ + IO_WORD _TSEL0 :4; + IO_WORD _TSEL1 :4; + IO_WORD _TSEL2 :4; + IO_WORD _TSEL3 :4; + }bitc; + }GCN11STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TSEL00 :1; + IO_BYTE _TSEL01 :1; + IO_BYTE _TSEL02 :1; + IO_BYTE _TSEL03 :1; + IO_BYTE _TSEL10 :1; + IO_BYTE _TSEL11 :1; + IO_BYTE _TSEL12 :1; + IO_BYTE _TSEL13 :1; + }bit; + struct{ + IO_BYTE _TSEL0 :4; + IO_BYTE _TSEL1 :4; + }bitc; + }GCN1L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TSEL20 :1; + IO_BYTE _TSEL21 :1; + IO_BYTE _TSEL22 :1; + IO_BYTE _TSEL23 :1; + IO_BYTE _TSEL30 :1; + IO_BYTE _TSEL31 :1; + IO_BYTE _TSEL32 :1; + IO_BYTE _TSEL33 :1; + }bit; + struct{ + IO_BYTE _TSEL2 :4; + IO_BYTE _TSEL3 :4; + }bitc; + }GCN1H1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _EN0 :1; + IO_WORD _EN1 :1; + IO_WORD _EN2 :1; + IO_WORD _EN3 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CKSEL0 :1; + IO_WORD _CKSEL1 :1; + IO_WORD _CKSEL2 :1; + IO_WORD _CKSEL3 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD :8; + IO_WORD _CKSEL :4; + }bitc; + }GCN21STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EN0 :1; + IO_BYTE _EN1 :1; + IO_BYTE _EN2 :1; + IO_BYTE _EN3 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }GCN2L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CKSEL0 :1; + IO_BYTE _CKSEL1 :1; + IO_BYTE _CKSEL2 :1; + IO_BYTE _CKSEL3 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _CKSEL :4; + }bitc; + }GCN2H1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PTMR4STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PCSR4STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PDUT4STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _OSEL :1; + IO_WORD _OE :1; + IO_WORD _IRS0 :1; + IO_WORD _IRS1 :1; + IO_WORD _IRQF :1; + IO_WORD _IREN :1; + IO_WORD _EGS0 :1; + IO_WORD _EGS1 :1; + IO_WORD :1; + IO_WORD _PGMS :1; + IO_WORD _CKS0 :1; + IO_WORD _CKS1 :1; + IO_WORD _RTRG :1; + IO_WORD _MDSE :1; + IO_WORD _STGR :1; + IO_WORD _CNTE :1; + }bit; + struct{ + IO_WORD :2; + IO_WORD _IRS :2; + IO_WORD :2; + IO_WORD _EGS :2; + IO_WORD :2; + IO_WORD _CKS :2; + }bitc; + }PCN4STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OSEL :1; + IO_BYTE _OE :1; + IO_BYTE _IRS0 :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRQF :1; + IO_BYTE _IREN :1; + IO_BYTE _EGS0 :1; + IO_BYTE _EGS1 :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _IRS :2; + IO_BYTE :2; + IO_BYTE _EGS :2; + }bitc; + }PCNL4STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _PGMS :1; + IO_BYTE _CKS0 :1; + IO_BYTE _CKS1 :1; + IO_BYTE _RTRG :1; + IO_BYTE _MDSE :1; + IO_BYTE _STGR :1; + IO_BYTE _CNTE :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _CKS :2; + }bitc; + }PCNH4STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PTMR5STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PCSR5STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PDUT5STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _OSEL :1; + IO_WORD _OE :1; + IO_WORD _IRS0 :1; + IO_WORD _IRS1 :1; + IO_WORD _IRQF :1; + IO_WORD _IREN :1; + IO_WORD _EGS0 :1; + IO_WORD _EGS1 :1; + IO_WORD :1; + IO_WORD _PGMS :1; + IO_WORD _CKS0 :1; + IO_WORD _CKS1 :1; + IO_WORD _RTRG :1; + IO_WORD _MDSE :1; + IO_WORD _STGR :1; + IO_WORD _CNTE :1; + }bit; + struct{ + IO_WORD :2; + IO_WORD _IRS :2; + IO_WORD :2; + IO_WORD _EGS :2; + IO_WORD :2; + IO_WORD _CKS :2; + }bitc; + }PCN5STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OSEL :1; + IO_BYTE _OE :1; + IO_BYTE _IRS0 :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRQF :1; + IO_BYTE _IREN :1; + IO_BYTE _EGS0 :1; + IO_BYTE _EGS1 :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _IRS :2; + IO_BYTE :2; + IO_BYTE _EGS :2; + }bitc; + }PCNL5STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _PGMS :1; + IO_BYTE _CKS0 :1; + IO_BYTE _CKS1 :1; + IO_BYTE _RTRG :1; + IO_BYTE _MDSE :1; + IO_BYTE _STGR :1; + IO_BYTE _CNTE :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _CKS :2; + }bitc; + }PCNH5STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ADT :1; + IO_BYTE _GCA :1; + IO_BYTE _AAS :1; + IO_BYTE _TRX :1; + IO_BYTE _LRB :1; + IO_BYTE _AL :1; + IO_BYTE _RSC :1; + IO_BYTE _BB :1; + }bit; + }IBSR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INT :1; + IO_BYTE _INTE :1; + IO_BYTE _GCAA :1; + IO_BYTE _ACK :1; + IO_BYTE _MSS :1; + IO_BYTE _SCC :1; + IO_BYTE _BEIE :1; + IO_BYTE _BER :1; + }bit; + }IBCR0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _TA0 :1; + IO_WORD _TA1 :1; + IO_WORD _TA2 :1; + IO_WORD _TA3 :1; + IO_WORD _TA4 :1; + IO_WORD _TA5 :1; + IO_WORD _TA6 :1; + IO_WORD _TA7 :1; + IO_WORD _TA8 :1; + IO_WORD _TA9 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD _TA :10; + }bitc; + }ITBA0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TA0 :1; + IO_BYTE _TA1 :1; + IO_BYTE _TA2 :1; + IO_BYTE _TA3 :1; + IO_BYTE _TA4 :1; + IO_BYTE _TA5 :1; + IO_BYTE _TA6 :1; + IO_BYTE _TA7 :1; + }bit; + }ITBAL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TA8 :1; + IO_BYTE _TA9 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }ITBAH0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _TM0 :1; + IO_WORD _TM1 :1; + IO_WORD _TM2 :1; + IO_WORD _TM3 :1; + IO_WORD _TM4 :1; + IO_WORD _TM5 :1; + IO_WORD _TM6 :1; + IO_WORD _TM7 :1; + IO_WORD _TM8 :1; + IO_WORD _TM9 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _RAL :1; + IO_WORD _ENTB :1; + }bit; + struct{ + IO_WORD _TM :10; + }bitc; + }ITMK0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TM0 :1; + IO_BYTE _TM1 :1; + IO_BYTE _TM2 :1; + IO_BYTE _TM3 :1; + IO_BYTE _TM4 :1; + IO_BYTE _TM5 :1; + IO_BYTE _TM6 :1; + IO_BYTE _TM7 :1; + }bit; + }ITMKL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TM8 :1; + IO_BYTE _TM9 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _RAL :1; + IO_BYTE _ENTB :1; + }bit; + }ITMKH0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SA0 :1; + IO_BYTE _SA1 :1; + IO_BYTE _SA2 :1; + IO_BYTE _SA3 :1; + IO_BYTE _SA4 :1; + IO_BYTE _SA5 :1; + IO_BYTE _SA6 :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _SA :7; + }bitc; + }ISBA0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SM0 :1; + IO_BYTE _SM1 :1; + IO_BYTE _SM2 :1; + IO_BYTE _SM3 :1; + IO_BYTE _SM4 :1; + IO_BYTE _SM5 :1; + IO_BYTE _SM6 :1; + IO_BYTE _ENSB :1; + }bit; + struct{ + IO_BYTE _SM :7; + }bitc; + }ISMK0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D0 :1; + IO_BYTE _D1 :1; + IO_BYTE _D2 :1; + IO_BYTE _D3 :1; + IO_BYTE _D4 :1; + IO_BYTE _D5 :1; + IO_BYTE _D6 :1; + IO_BYTE _D7 :1; + }bit; + }IDAR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CS0 :1; + IO_BYTE _CS1 :1; + IO_BYTE _CS2 :1; + IO_BYTE _CS3 :1; + IO_BYTE _CS4 :1; + IO_BYTE _EN :1; + IO_BYTE _NSF :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _CS :5; + }bitc; + }ICCR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ADT :1; + IO_BYTE _GCA :1; + IO_BYTE _AAS :1; + IO_BYTE _TRX :1; + IO_BYTE _LRB :1; + IO_BYTE _AL :1; + IO_BYTE _RSC :1; + IO_BYTE _BB :1; + }bit; + }IBSR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INT :1; + IO_BYTE _INTE :1; + IO_BYTE _GCAA :1; + IO_BYTE _ACK :1; + IO_BYTE _MSS :1; + IO_BYTE _SCC :1; + IO_BYTE _BEIE :1; + IO_BYTE _BER :1; + }bit; + }IBCR1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _TA0 :1; + IO_WORD _TA1 :1; + IO_WORD _TA2 :1; + IO_WORD _TA3 :1; + IO_WORD _TA4 :1; + IO_WORD _TA5 :1; + IO_WORD _TA6 :1; + IO_WORD _TA7 :1; + IO_WORD _TA8 :1; + IO_WORD _TA9 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD _TA :10; + }bitc; + }ITBA1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TA0 :1; + IO_BYTE _TA1 :1; + IO_BYTE _TA2 :1; + IO_BYTE _TA3 :1; + IO_BYTE _TA4 :1; + IO_BYTE _TA5 :1; + IO_BYTE _TA6 :1; + IO_BYTE _TA7 :1; + }bit; + }ITBAL1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TA8 :1; + IO_BYTE _TA9 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }ITBAH1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _TM0 :1; + IO_WORD _TM1 :1; + IO_WORD _TM2 :1; + IO_WORD _TM3 :1; + IO_WORD _TM4 :1; + IO_WORD _TM5 :1; + IO_WORD _TM6 :1; + IO_WORD _TM7 :1; + IO_WORD _TM8 :1; + IO_WORD _TM9 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _RAL :1; + IO_WORD _ENTB :1; + }bit; + struct{ + IO_WORD _TM :10; + }bitc; + }ITMK1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TM0 :1; + IO_BYTE _TM1 :1; + IO_BYTE _TM2 :1; + IO_BYTE _TM3 :1; + IO_BYTE _TM4 :1; + IO_BYTE _TM5 :1; + IO_BYTE _TM6 :1; + IO_BYTE _TM7 :1; + }bit; + }ITMKL1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TM8 :1; + IO_BYTE _TM9 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _RAL :1; + IO_BYTE _ENTB :1; + }bit; + }ITMKH1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SA0 :1; + IO_BYTE _SA1 :1; + IO_BYTE _SA2 :1; + IO_BYTE _SA3 :1; + IO_BYTE _SA4 :1; + IO_BYTE _SA5 :1; + IO_BYTE _SA6 :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _SA :7; + }bitc; + }ISBA1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SM0 :1; + IO_BYTE _SM1 :1; + IO_BYTE _SM2 :1; + IO_BYTE _SM3 :1; + IO_BYTE _SM4 :1; + IO_BYTE _SM5 :1; + IO_BYTE _SM6 :1; + IO_BYTE _ENSB :1; + }bit; + struct{ + IO_BYTE _SM :7; + }bitc; + }ISMK1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D0 :1; + IO_BYTE _D1 :1; + IO_BYTE _D2 :1; + IO_BYTE _D3 :1; + IO_BYTE _D4 :1; + IO_BYTE _D5 :1; + IO_BYTE _D6 :1; + IO_BYTE _D7 :1; + }bit; + }IDAR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CS0 :1; + IO_BYTE _CS1 :1; + IO_BYTE _CS2 :1; + IO_BYTE _CS3 :1; + IO_BYTE _CS4 :1; + IO_BYTE _EN :1; + IO_BYTE _NSF :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _CS :5; + }bitc; + }ICCR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SOE :1; + IO_BYTE _SCKE :1; + IO_BYTE _UPCL :1; + IO_BYTE _REST :1; + IO_BYTE _EXT :1; + IO_BYTE _OTO :1; + IO_BYTE _MD0 :1; + IO_BYTE _MD1 :1; + }bit; + struct{ + IO_BYTE :6; + IO_BYTE _MD :2; + }bitc; + }SMR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TXE :1; + IO_BYTE _RXE :1; + IO_BYTE _CRE :1; + IO_BYTE _AD :1; + IO_BYTE _CL :1; + IO_BYTE _SBL :1; + IO_BYTE _P :1; + IO_BYTE _PEN :1; + }bit; + }SCR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TIE :1; + IO_BYTE _RIE :1; + IO_BYTE _BDS :1; + IO_BYTE _TDRE :1; + IO_BYTE _RDRF :1; + IO_BYTE _FRE :1; + IO_BYTE _ORE :1; + IO_BYTE _PE :1; + }bit; + }SSR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TBI :1; + IO_BYTE _RBI :1; + IO_BYTE _BIE :1; + IO_BYTE _SSM :1; + IO_BYTE _SCDE :1; + IO_BYTE _MS :1; + IO_BYTE _LBR :1; + IO_BYTE _INV :1; + }bit; + }ECCR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SCES :1; + IO_BYTE _CCO :1; + IO_BYTE _SIOP :1; + IO_BYTE _SOPE :1; + IO_BYTE _LBL0 :1; + IO_BYTE _LBL1 :1; + IO_BYTE _LBD :1; + IO_BYTE _LBIE :1; + }bit; + struct{ + IO_BYTE :4; + IO_BYTE _LBL :2; + }bitc; + }ESCR0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _BGR0 :1; + IO_WORD _BGR1 :1; + IO_WORD _BGR2 :1; + IO_WORD _BGR3 :1; + IO_WORD _BGR4 :1; + IO_WORD _BGR5 :1; + IO_WORD _BGR6 :1; + IO_WORD _BGR7 :1; + IO_WORD _BGR8 :1; + IO_WORD _BGR9 :1; + IO_WORD _BGR10 :1; + IO_WORD _BGR11 :1; + IO_WORD _BGR12 :1; + IO_WORD _BGR13 :1; + IO_WORD _BGR14 :1; + IO_WORD _BGR15 :1; + }bit; + struct{ + IO_WORD _BGR :16; + }bitc; + }BGR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _BGR0 :1; + IO_BYTE _BGR1 :1; + IO_BYTE _BGR2 :1; + IO_BYTE _BGR3 :1; + IO_BYTE _BGR4 :1; + IO_BYTE _BGR5 :1; + IO_BYTE _BGR6 :1; + IO_BYTE _BGR7 :1; + }bit; + }BGRL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _BGR8 :1; + IO_BYTE _BGR9 :1; + IO_BYTE _BGR10 :1; + IO_BYTE _BGR11 :1; + IO_BYTE _BGR12 :1; + IO_BYTE _BGR13 :1; + IO_BYTE _BGR14 :1; + IO_BYTE _BGR15 :1; + }bit; + }BGRH0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _AICD :1; + IO_BYTE _RBI :1; + IO_BYTE _RDRF :1; + IO_BYTE _TDRE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }ESIR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SOE :1; + IO_BYTE _SCKE :1; + IO_BYTE _UPCL :1; + IO_BYTE _REST :1; + IO_BYTE _EXT :1; + IO_BYTE _OTO :1; + IO_BYTE _MD0 :1; + IO_BYTE _MD1 :1; + }bit; + struct{ + IO_BYTE :6; + IO_BYTE _MD :2; + }bitc; + }SMR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TXE :1; + IO_BYTE _RXE :1; + IO_BYTE _CRE :1; + IO_BYTE _AD :1; + IO_BYTE _CL :1; + IO_BYTE _SBL :1; + IO_BYTE _P :1; + IO_BYTE _PEN :1; + }bit; + }SCR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TIE :1; + IO_BYTE _RIE :1; + IO_BYTE _BDS :1; + IO_BYTE _TDRE :1; + IO_BYTE _RDRF :1; + IO_BYTE _FRE :1; + IO_BYTE _ORE :1; + IO_BYTE _PE :1; + }bit; + }SSR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TBI :1; + IO_BYTE _RBI :1; + IO_BYTE _BIE :1; + IO_BYTE _SSM :1; + IO_BYTE _SCDE :1; + IO_BYTE _MS :1; + IO_BYTE _LBR :1; + IO_BYTE _INV :1; + }bit; + }ECCR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SCES :1; + IO_BYTE _CCO :1; + IO_BYTE _SIOP :1; + IO_BYTE _SOPE :1; + IO_BYTE _LBL0 :1; + IO_BYTE _LBL1 :1; + IO_BYTE _LBD :1; + IO_BYTE _LBIE :1; + }bit; + struct{ + IO_BYTE :4; + IO_BYTE _LBL :2; + }bitc; + }ESCR1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _BGR0 :1; + IO_WORD _BGR1 :1; + IO_WORD _BGR2 :1; + IO_WORD _BGR3 :1; + IO_WORD _BGR4 :1; + IO_WORD _BGR5 :1; + IO_WORD _BGR6 :1; + IO_WORD _BGR7 :1; + IO_WORD _BGR8 :1; + IO_WORD _BGR9 :1; + IO_WORD _BGR10 :1; + IO_WORD _BGR11 :1; + IO_WORD _BGR12 :1; + IO_WORD _BGR13 :1; + IO_WORD _BGR14 :1; + IO_WORD _BGR15 :1; + }bit; + struct{ + IO_WORD _BGR :16; + }bitc; + }BGR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _BGR0 :1; + IO_BYTE _BGR1 :1; + IO_BYTE _BGR2 :1; + IO_BYTE _BGR3 :1; + IO_BYTE _BGR4 :1; + IO_BYTE _BGR5 :1; + IO_BYTE _BGR6 :1; + IO_BYTE _BGR7 :1; + }bit; + }BGRL1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _BGR8 :1; + IO_BYTE _BGR9 :1; + IO_BYTE _BGR10 :1; + IO_BYTE _BGR11 :1; + IO_BYTE _BGR12 :1; + IO_BYTE _BGR13 :1; + IO_BYTE _BGR14 :1; + IO_BYTE _BGR15 :1; + }bit; + }BGRH1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _AICD :1; + IO_BYTE _RBI :1; + IO_BYTE _RDRF :1; + IO_BYTE _TDRE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }ESIR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SOE :1; + IO_BYTE _SCKE :1; + IO_BYTE _UPCL :1; + IO_BYTE _REST :1; + IO_BYTE _EXT :1; + IO_BYTE _OTO :1; + IO_BYTE _MD0 :1; + IO_BYTE _MD1 :1; + }bit; + struct{ + IO_BYTE :6; + IO_BYTE _MD :2; + }bitc; + }SMR2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TXE :1; + IO_BYTE _RXE :1; + IO_BYTE _CRE :1; + IO_BYTE _AD :1; + IO_BYTE _CL :1; + IO_BYTE _SBL :1; + IO_BYTE _P :1; + IO_BYTE _PEN :1; + }bit; + }SCR2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TIE :1; + IO_BYTE _RIE :1; + IO_BYTE _BDS :1; + IO_BYTE _TDRE :1; + IO_BYTE _RDRF :1; + IO_BYTE _FRE :1; + IO_BYTE _ORE :1; + IO_BYTE _PE :1; + }bit; + }SSR2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TBI :1; + IO_BYTE _RBI :1; + IO_BYTE _BIE :1; + IO_BYTE _SSM :1; + IO_BYTE _SCDE :1; + IO_BYTE _MS :1; + IO_BYTE _LBR :1; + IO_BYTE _INV :1; + }bit; + }ECCR2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SCES :1; + IO_BYTE _CCO :1; + IO_BYTE _SIOP :1; + IO_BYTE _SOPE :1; + IO_BYTE _LBL0 :1; + IO_BYTE _LBL1 :1; + IO_BYTE _LBD :1; + IO_BYTE _LBIE :1; + }bit; + struct{ + IO_BYTE :4; + IO_BYTE _LBL :2; + }bitc; + }ESCR2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _BGR0 :1; + IO_WORD _BGR1 :1; + IO_WORD _BGR2 :1; + IO_WORD _BGR3 :1; + IO_WORD _BGR4 :1; + IO_WORD _BGR5 :1; + IO_WORD _BGR6 :1; + IO_WORD _BGR7 :1; + IO_WORD _BGR8 :1; + IO_WORD _BGR9 :1; + IO_WORD _BGR10 :1; + IO_WORD _BGR11 :1; + IO_WORD _BGR12 :1; + IO_WORD _BGR13 :1; + IO_WORD _BGR14 :1; + IO_WORD _BGR15 :1; + }bit; + struct{ + IO_WORD _BGR :16; + }bitc; + }BGR2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _BGR0 :1; + IO_BYTE _BGR1 :1; + IO_BYTE _BGR2 :1; + IO_BYTE _BGR3 :1; + IO_BYTE _BGR4 :1; + IO_BYTE _BGR5 :1; + IO_BYTE _BGR6 :1; + IO_BYTE _BGR7 :1; + }bit; + }BGRL2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _BGR8 :1; + IO_BYTE _BGR9 :1; + IO_BYTE _BGR10 :1; + IO_BYTE _BGR11 :1; + IO_BYTE _BGR12 :1; + IO_BYTE _BGR13 :1; + IO_BYTE _BGR14 :1; + IO_BYTE _BGR15 :1; + }bit; + }BGRH2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _AICD :1; + IO_BYTE _RBI :1; + IO_BYTE _RDRF :1; + IO_BYTE _TDRE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }ESIR2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SOE :1; + IO_BYTE _SCKE :1; + IO_BYTE _UPCL :1; + IO_BYTE _REST :1; + IO_BYTE _EXT :1; + IO_BYTE _OTO :1; + IO_BYTE _MD0 :1; + IO_BYTE _MD1 :1; + }bit; + struct{ + IO_BYTE :6; + IO_BYTE _MD :2; + }bitc; + }SMR3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TXE :1; + IO_BYTE _RXE :1; + IO_BYTE _CRE :1; + IO_BYTE _AD :1; + IO_BYTE _CL :1; + IO_BYTE _SBL :1; + IO_BYTE _P :1; + IO_BYTE _PEN :1; + }bit; + }SCR3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TIE :1; + IO_BYTE _RIE :1; + IO_BYTE _BDS :1; + IO_BYTE _TDRE :1; + IO_BYTE _RDRF :1; + IO_BYTE _FRE :1; + IO_BYTE _ORE :1; + IO_BYTE _PE :1; + }bit; + }SSR3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TBI :1; + IO_BYTE _RBI :1; + IO_BYTE _BIE :1; + IO_BYTE _SSM :1; + IO_BYTE _SCDE :1; + IO_BYTE _MS :1; + IO_BYTE _LBR :1; + IO_BYTE _INV :1; + }bit; + }ECCR3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SCES :1; + IO_BYTE _CCO :1; + IO_BYTE _SIOP :1; + IO_BYTE _SOPE :1; + IO_BYTE _LBL0 :1; + IO_BYTE _LBL1 :1; + IO_BYTE _LBD :1; + IO_BYTE _LBIE :1; + }bit; + struct{ + IO_BYTE :4; + IO_BYTE _LBL :2; + }bitc; + }ESCR3STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _BGR0 :1; + IO_WORD _BGR1 :1; + IO_WORD _BGR2 :1; + IO_WORD _BGR3 :1; + IO_WORD _BGR4 :1; + IO_WORD _BGR5 :1; + IO_WORD _BGR6 :1; + IO_WORD _BGR7 :1; + IO_WORD _BGR8 :1; + IO_WORD _BGR9 :1; + IO_WORD _BGR10 :1; + IO_WORD _BGR11 :1; + IO_WORD _BGR12 :1; + IO_WORD _BGR13 :1; + IO_WORD _BGR14 :1; + IO_WORD _BGR15 :1; + }bit; + struct{ + IO_WORD _BGR :16; + }bitc; + }BGR3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _BGR0 :1; + IO_BYTE _BGR1 :1; + IO_BYTE _BGR2 :1; + IO_BYTE _BGR3 :1; + IO_BYTE _BGR4 :1; + IO_BYTE _BGR5 :1; + IO_BYTE _BGR6 :1; + IO_BYTE _BGR7 :1; + }bit; + }BGRL3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _BGR8 :1; + IO_BYTE _BGR9 :1; + IO_BYTE _BGR10 :1; + IO_BYTE _BGR11 :1; + IO_BYTE _BGR12 :1; + IO_BYTE _BGR13 :1; + IO_BYTE _BGR14 :1; + IO_BYTE _BGR15 :1; + }bit; + }BGRH3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _AICD :1; + IO_BYTE _RBI :1; + IO_BYTE _RDRF :1; + IO_BYTE _TDRE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }ESIR3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SE :1; + IO_BYTE _DIR :1; + IO_BYTE _BF :1; + IO_BYTE _BW :1; + IO_BYTE _IF :1; + IO_BYTE _BPD :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }DMACS0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SE :1; + IO_BYTE _DIR :1; + IO_BYTE _BF :1; + IO_BYTE _BW :1; + IO_BYTE _IF :1; + IO_BYTE _BPD :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }DMACS1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SE :1; + IO_BYTE _DIR :1; + IO_BYTE _BF :1; + IO_BYTE _BW :1; + IO_BYTE _IF :1; + IO_BYTE _BPD :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }DMACS2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SE :1; + IO_BYTE _DIR :1; + IO_BYTE _BF :1; + IO_BYTE _BW :1; + IO_BYTE _IF :1; + IO_BYTE _BPD :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }DMACS3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SE :1; + IO_BYTE _DIR :1; + IO_BYTE _BF :1; + IO_BYTE _BW :1; + IO_BYTE _IF :1; + IO_BYTE _BPD :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }DMACS4STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SE :1; + IO_BYTE _DIR :1; + IO_BYTE _BF :1; + IO_BYTE _BW :1; + IO_BYTE _IF :1; + IO_BYTE _BPD :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }DMACS5STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _DTE0 :1; + IO_WORD _DTE1 :1; + IO_WORD _DTE2 :1; + IO_WORD _DTE3 :1; + IO_WORD _DTE4 :1; + IO_WORD _DTE5 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }DSRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _DTE0 :1; + IO_BYTE _DTE1 :1; + IO_BYTE _DTE2 :1; + IO_BYTE _DTE3 :1; + IO_BYTE _DTE4 :1; + IO_BYTE _DTE5 :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }DSRLSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _STP0 :1; + IO_WORD _STP1 :1; + IO_WORD _STP2 :1; + IO_WORD _STP3 :1; + IO_WORD _STP4 :1; + IO_WORD _STP5 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }DSSRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _STP0 :1; + IO_BYTE _STP1 :1; + IO_BYTE _STP2 :1; + IO_BYTE _STP3 :1; + IO_BYTE _STP4 :1; + IO_BYTE _STP5 :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }DSSRLSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _EN0 :1; + IO_WORD _EN1 :1; + IO_WORD _EN2 :1; + IO_WORD _EN3 :1; + IO_WORD _EN4 :1; + IO_WORD _EN5 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }DERSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EN0 :1; + IO_BYTE _EN1 :1; + IO_BYTE _EN2 :1; + IO_BYTE _EN3 :1; + IO_BYTE _EN4 :1; + IO_BYTE _EN5 :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }DERLSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _IL0 :1; + IO_WORD _IL1 :1; + IO_WORD _IL2 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _IX0 :1; + IO_WORD _IX1 :1; + IO_WORD _IX2 :1; + IO_WORD _IX3 :1; + IO_WORD _IX4 :1; + IO_WORD _IX5 :1; + IO_WORD _IX6 :1; + IO_WORD _IX7 :1; + }bit; + struct{ + IO_WORD _IL :3; + IO_WORD :5; + IO_WORD _IX :8; + }bitc; + }ICRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IL0 :1; + IO_BYTE _IL1 :1; + IO_BYTE _IL2 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _IL :3; + }bitc; + }ILRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IX0 :1; + IO_BYTE _IX1 :1; + IO_BYTE _IX2 :1; + IO_BYTE _IX3 :1; + IO_BYTE _IX4 :1; + IO_BYTE _IX5 :1; + IO_BYTE _IX6 :1; + IO_BYTE _IX7 :1; + }bit; + struct{ + IO_BYTE _IX :8; + }bitc; + }IDXSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD _TB10 :1; + IO_WORD _TB11 :1; + IO_WORD _TB12 :1; + IO_WORD _TB13 :1; + IO_WORD _TB14 :1; + IO_WORD _TB15 :1; + IO_WORD _TB16 :1; + IO_WORD _TB17 :1; + IO_WORD _TB18 :1; + IO_WORD _TB19 :1; + IO_WORD _TB20 :1; + IO_WORD _TB21 :1; + IO_WORD _TB22 :1; + IO_WORD _TB23 :1; + }bit; + }TBRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _TB10 :1; + IO_BYTE _TB11 :1; + IO_BYTE _TB12 :1; + IO_BYTE _TB13 :1; + IO_BYTE _TB14 :1; + IO_BYTE _TB15 :1; + }bit; + }TBRLSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TB16 :1; + IO_BYTE _TB17 :1; + IO_BYTE _TB18 :1; + IO_BYTE _TB19 :1; + IO_BYTE _TB20 :1; + IO_BYTE _TB21 :1; + IO_BYTE _TB22 :1; + IO_BYTE _TB23 :1; + }bit; + }TBRHSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _R0 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }DIRRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _FLAG :1; + IO_BYTE _EN :1; + IO_BYTE _LEV :1; + IO_BYTE _INT9FIX :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }NMISTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _RSEL0 :1; + IO_WORD _RSEL1 :1; + IO_WORD _RSEL2 :1; + IO_WORD _RSEL3 :1; + IO_WORD _RSEL4 :1; + IO_WORD _RSEL5 :1; + IO_WORD _RSEL6 :1; + IO_WORD _RSEL7 :1; + IO_WORD _TSEL0 :1; + IO_WORD _TSEL1 :1; + IO_WORD _TSEL2 :1; + IO_WORD _TSEL3 :1; + IO_WORD _TSEL4 :1; + IO_WORD _TSEL5 :1; + IO_WORD _TSEL6 :1; + IO_WORD _TSEL7 :1; + }bit; + struct{ + IO_WORD _RSEL :8; + IO_WORD _TSEL :8; + }bitc; + }EDSU2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MI :1; + IO_BYTE _SZ0 :1; + IO_BYTE _SZ1 :1; + IO_BYTE :1; + IO_BYTE _BS0 :1; + IO_BYTE _BS1 :1; + IO_BYTE _BS2 :1; + IO_BYTE _BS3 :1; + }bit; + }ROMMSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _RINT :1; + IO_BYTE _RIE :1; + IO_BYTE _SEL0 :1; + IO_BYTE _SEL1 :1; + IO_BYTE _TINT :1; + IO_BYTE _TIE :1; + IO_BYTE :1; + IO_BYTE _EN :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _SEL :2; + }bitc; + }EDSUSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _I0 :1; + IO_WORD _I1 :1; + IO_WORD _IE0 :1; + IO_WORD _IE1 :1; + IO_WORD _PE0 :1; + IO_WORD _PE1 :1; + IO_WORD _AR :1; + IO_WORD _AM :1; + IO_WORD _DMA :1; + IO_WORD _CPU :1; + IO_WORD _DATA :1; + IO_WORD _CODE :1; + IO_WORD _WORD :1; + IO_WORD _BYTE :1; + IO_WORD _WRITE :1; + IO_WORD _READ :1; + }bit; + }PFCS0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _I0 :1; + IO_WORD _I1 :1; + IO_WORD _IE0 :1; + IO_WORD _IE1 :1; + IO_WORD _PE0 :1; + IO_WORD _PE1 :1; + IO_WORD _AR :1; + IO_WORD _AM :1; + IO_WORD _DMA :1; + IO_WORD _CPU :1; + IO_WORD _DATA :1; + IO_WORD _CODE :1; + IO_WORD _WORD :1; + IO_WORD _BYTE :1; + IO_WORD _WRITE :1; + IO_WORD _READ :1; + }bit; + }PFCS1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _I0 :1; + IO_WORD _I1 :1; + IO_WORD _IE0 :1; + IO_WORD _IE1 :1; + IO_WORD _PE0 :1; + IO_WORD _PE1 :1; + IO_WORD _AR :1; + IO_WORD _AM :1; + IO_WORD _DMA :1; + IO_WORD _CPU :1; + IO_WORD _DATA :1; + IO_WORD _CODE :1; + IO_WORD _WORD :1; + IO_WORD _BYTE :1; + IO_WORD _WRITE :1; + IO_WORD _READ :1; + }bit; + }PFCS2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _I0 :1; + IO_WORD _I1 :1; + IO_WORD _IE0 :1; + IO_WORD _IE1 :1; + IO_WORD _PE0 :1; + IO_WORD _PE1 :1; + IO_WORD _AR :1; + IO_WORD _AM :1; + IO_WORD _DMA :1; + IO_WORD _CPU :1; + IO_WORD _DATA :1; + IO_WORD _CODE :1; + IO_WORD _WORD :1; + IO_WORD _BYTE :1; + IO_WORD _WRITE :1; + IO_WORD _READ :1; + }bit; + }PFCS3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFA0 :1; + IO_BYTE _PFA1 :1; + IO_BYTE _PFA2 :1; + IO_BYTE _PFA3 :1; + IO_BYTE _PFA4 :1; + IO_BYTE _PFA5 :1; + IO_BYTE _PFA6 :1; + IO_BYTE _PFA7 :1; + }bit; + }PFAL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFA8 :1; + IO_BYTE _PFA9 :1; + IO_BYTE _PFA10 :1; + IO_BYTE _PFA11 :1; + IO_BYTE _PFA12 :1; + IO_BYTE _PFA13 :1; + IO_BYTE _PFA14 :1; + IO_BYTE _PFA15 :1; + }bit; + }PFAM0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFA16 :1; + IO_BYTE _PFA17 :1; + IO_BYTE _PFA18 :1; + IO_BYTE _PFA19 :1; + IO_BYTE _PFA20 :1; + IO_BYTE _PFA21 :1; + IO_BYTE _PFA22 :1; + IO_BYTE _PFA23 :1; + }bit; + }PFAH0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFA0 :1; + IO_BYTE _PFA1 :1; + IO_BYTE _PFA2 :1; + IO_BYTE _PFA3 :1; + IO_BYTE _PFA4 :1; + IO_BYTE _PFA5 :1; + IO_BYTE _PFA6 :1; + IO_BYTE _PFA7 :1; + }bit; + }PFAL1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFA8 :1; + IO_BYTE _PFA9 :1; + IO_BYTE _PFA10 :1; + IO_BYTE _PFA11 :1; + IO_BYTE _PFA12 :1; + IO_BYTE _PFA13 :1; + IO_BYTE _PFA14 :1; + IO_BYTE _PFA15 :1; + }bit; + }PFAM1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFA16 :1; + IO_BYTE _PFA17 :1; + IO_BYTE _PFA18 :1; + IO_BYTE _PFA19 :1; + IO_BYTE _PFA20 :1; + IO_BYTE _PFA21 :1; + IO_BYTE _PFA22 :1; + IO_BYTE _PFA23 :1; + }bit; + }PFAH1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFA0 :1; + IO_BYTE _PFA1 :1; + IO_BYTE _PFA2 :1; + IO_BYTE _PFA3 :1; + IO_BYTE _PFA4 :1; + IO_BYTE _PFA5 :1; + IO_BYTE _PFA6 :1; + IO_BYTE _PFA7 :1; + }bit; + }PFAL2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFA8 :1; + IO_BYTE _PFA9 :1; + IO_BYTE _PFA10 :1; + IO_BYTE _PFA11 :1; + IO_BYTE _PFA12 :1; + IO_BYTE _PFA13 :1; + IO_BYTE _PFA14 :1; + IO_BYTE _PFA15 :1; + }bit; + }PFAM2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFA16 :1; + IO_BYTE _PFA17 :1; + IO_BYTE _PFA18 :1; + IO_BYTE _PFA19 :1; + IO_BYTE _PFA20 :1; + IO_BYTE _PFA21 :1; + IO_BYTE _PFA22 :1; + IO_BYTE _PFA23 :1; + }bit; + }PFAH2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFA0 :1; + IO_BYTE _PFA1 :1; + IO_BYTE _PFA2 :1; + IO_BYTE _PFA3 :1; + IO_BYTE _PFA4 :1; + IO_BYTE _PFA5 :1; + IO_BYTE _PFA6 :1; + IO_BYTE _PFA7 :1; + }bit; + }PFAL3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFA8 :1; + IO_BYTE _PFA9 :1; + IO_BYTE _PFA10 :1; + IO_BYTE _PFA11 :1; + IO_BYTE _PFA12 :1; + IO_BYTE _PFA13 :1; + IO_BYTE _PFA14 :1; + IO_BYTE _PFA15 :1; + }bit; + }PFAM3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFA16 :1; + IO_BYTE _PFA17 :1; + IO_BYTE _PFA18 :1; + IO_BYTE _PFA19 :1; + IO_BYTE _PFA20 :1; + IO_BYTE _PFA21 :1; + IO_BYTE _PFA22 :1; + IO_BYTE _PFA23 :1; + }bit; + }PFAH3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFA0 :1; + IO_BYTE _PFA1 :1; + IO_BYTE _PFA2 :1; + IO_BYTE _PFA3 :1; + IO_BYTE _PFA4 :1; + IO_BYTE _PFA5 :1; + IO_BYTE _PFA6 :1; + IO_BYTE _PFA7 :1; + }bit; + }PFAL4STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFA8 :1; + IO_BYTE _PFA9 :1; + IO_BYTE _PFA10 :1; + IO_BYTE _PFA11 :1; + IO_BYTE _PFA12 :1; + IO_BYTE _PFA13 :1; + IO_BYTE _PFA14 :1; + IO_BYTE _PFA15 :1; + }bit; + }PFAM4STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFA16 :1; + IO_BYTE _PFA17 :1; + IO_BYTE _PFA18 :1; + IO_BYTE _PFA19 :1; + IO_BYTE _PFA20 :1; + IO_BYTE _PFA21 :1; + IO_BYTE _PFA22 :1; + IO_BYTE _PFA23 :1; + }bit; + }PFAH4STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFA0 :1; + IO_BYTE _PFA1 :1; + IO_BYTE _PFA2 :1; + IO_BYTE _PFA3 :1; + IO_BYTE _PFA4 :1; + IO_BYTE _PFA5 :1; + IO_BYTE _PFA6 :1; + IO_BYTE _PFA7 :1; + }bit; + }PFAL5STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFA8 :1; + IO_BYTE _PFA9 :1; + IO_BYTE _PFA10 :1; + IO_BYTE _PFA11 :1; + IO_BYTE _PFA12 :1; + IO_BYTE _PFA13 :1; + IO_BYTE _PFA14 :1; + IO_BYTE _PFA15 :1; + }bit; + }PFAM5STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFA16 :1; + IO_BYTE _PFA17 :1; + IO_BYTE _PFA18 :1; + IO_BYTE _PFA19 :1; + IO_BYTE _PFA20 :1; + IO_BYTE _PFA21 :1; + IO_BYTE _PFA22 :1; + IO_BYTE _PFA23 :1; + }bit; + }PFAH5STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFA0 :1; + IO_BYTE _PFA1 :1; + IO_BYTE _PFA2 :1; + IO_BYTE _PFA3 :1; + IO_BYTE _PFA4 :1; + IO_BYTE _PFA5 :1; + IO_BYTE _PFA6 :1; + IO_BYTE _PFA7 :1; + }bit; + }PFAL6STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFA8 :1; + IO_BYTE _PFA9 :1; + IO_BYTE _PFA10 :1; + IO_BYTE _PFA11 :1; + IO_BYTE _PFA12 :1; + IO_BYTE _PFA13 :1; + IO_BYTE _PFA14 :1; + IO_BYTE _PFA15 :1; + }bit; + }PFAM6STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFA16 :1; + IO_BYTE _PFA17 :1; + IO_BYTE _PFA18 :1; + IO_BYTE _PFA19 :1; + IO_BYTE _PFA20 :1; + IO_BYTE _PFA21 :1; + IO_BYTE _PFA22 :1; + IO_BYTE _PFA23 :1; + }bit; + }PFAH6STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFA0 :1; + IO_BYTE _PFA1 :1; + IO_BYTE _PFA2 :1; + IO_BYTE _PFA3 :1; + IO_BYTE _PFA4 :1; + IO_BYTE _PFA5 :1; + IO_BYTE _PFA6 :1; + IO_BYTE _PFA7 :1; + }bit; + }PFAL7STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFA8 :1; + IO_BYTE _PFA9 :1; + IO_BYTE _PFA10 :1; + IO_BYTE _PFA11 :1; + IO_BYTE _PFA12 :1; + IO_BYTE _PFA13 :1; + IO_BYTE _PFA14 :1; + IO_BYTE _PFA15 :1; + }bit; + }PFAM7STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFA16 :1; + IO_BYTE _PFA17 :1; + IO_BYTE _PFA18 :1; + IO_BYTE _PFA19 :1; + IO_BYTE _PFA20 :1; + IO_BYTE _PFA21 :1; + IO_BYTE _PFA22 :1; + IO_BYTE _PFA23 :1; + }bit; + }PFAH7STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _PFD0 :1; + IO_WORD _PFD1 :1; + IO_WORD _PFD2 :1; + IO_WORD _PFD3 :1; + IO_WORD _PFD4 :1; + IO_WORD _PFD5 :1; + IO_WORD _PFD6 :1; + IO_WORD _PFD7 :1; + IO_WORD _PFD8 :1; + IO_WORD _PFD9 :1; + IO_WORD _PFD10 :1; + IO_WORD _PFD11 :1; + IO_WORD _PFD12 :1; + IO_WORD _PFD13 :1; + IO_WORD _PFD14 :1; + IO_WORD _PFD15 :1; + }bit; + struct{ + IO_WORD _PFD :16; + }bitc; + }PFD0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFD0 :1; + IO_BYTE _PFD1 :1; + IO_BYTE _PFD2 :1; + IO_BYTE _PFD3 :1; + IO_BYTE _PFD4 :1; + IO_BYTE _PFD5 :1; + IO_BYTE _PFD6 :1; + IO_BYTE _PFD7 :1; + }bit; + }PFDL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFD8 :1; + IO_BYTE _PFD9 :1; + IO_BYTE _PFD10 :1; + IO_BYTE _PFD11 :1; + IO_BYTE _PFD12 :1; + IO_BYTE _PFD13 :1; + IO_BYTE _PFD14 :1; + IO_BYTE _PFD15 :1; + }bit; + }PFDH0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _PFD0 :1; + IO_WORD _PFD1 :1; + IO_WORD _PFD2 :1; + IO_WORD _PFD3 :1; + IO_WORD _PFD4 :1; + IO_WORD _PFD5 :1; + IO_WORD _PFD6 :1; + IO_WORD _PFD7 :1; + IO_WORD _PFD8 :1; + IO_WORD _PFD9 :1; + IO_WORD _PFD10 :1; + IO_WORD _PFD11 :1; + IO_WORD _PFD12 :1; + IO_WORD _PFD13 :1; + IO_WORD _PFD14 :1; + IO_WORD _PFD15 :1; + }bit; + struct{ + IO_WORD _PFD :16; + }bitc; + }PFD1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFD0 :1; + IO_BYTE _PFD1 :1; + IO_BYTE _PFD2 :1; + IO_BYTE _PFD3 :1; + IO_BYTE _PFD4 :1; + IO_BYTE _PFD5 :1; + IO_BYTE _PFD6 :1; + IO_BYTE _PFD7 :1; + }bit; + }PFDL1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFD8 :1; + IO_BYTE _PFD9 :1; + IO_BYTE _PFD10 :1; + IO_BYTE _PFD11 :1; + IO_BYTE _PFD12 :1; + IO_BYTE _PFD13 :1; + IO_BYTE _PFD14 :1; + IO_BYTE _PFD15 :1; + }bit; + }PFDH1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _PFD0 :1; + IO_WORD _PFD1 :1; + IO_WORD _PFD2 :1; + IO_WORD _PFD3 :1; + IO_WORD _PFD4 :1; + IO_WORD _PFD5 :1; + IO_WORD _PFD6 :1; + IO_WORD _PFD7 :1; + IO_WORD _PFD8 :1; + IO_WORD _PFD9 :1; + IO_WORD _PFD10 :1; + IO_WORD _PFD11 :1; + IO_WORD _PFD12 :1; + IO_WORD _PFD13 :1; + IO_WORD _PFD14 :1; + IO_WORD _PFD15 :1; + }bit; + struct{ + IO_WORD _PFD :16; + }bitc; + }PFD2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFD0 :1; + IO_BYTE _PFD1 :1; + IO_BYTE _PFD2 :1; + IO_BYTE _PFD3 :1; + IO_BYTE _PFD4 :1; + IO_BYTE _PFD5 :1; + IO_BYTE _PFD6 :1; + IO_BYTE _PFD7 :1; + }bit; + }PFDL2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFD8 :1; + IO_BYTE _PFD9 :1; + IO_BYTE _PFD10 :1; + IO_BYTE _PFD11 :1; + IO_BYTE _PFD12 :1; + IO_BYTE _PFD13 :1; + IO_BYTE _PFD14 :1; + IO_BYTE _PFD15 :1; + }bit; + }PFDH2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _PFD0 :1; + IO_WORD _PFD1 :1; + IO_WORD _PFD2 :1; + IO_WORD _PFD3 :1; + IO_WORD _PFD4 :1; + IO_WORD _PFD5 :1; + IO_WORD _PFD6 :1; + IO_WORD _PFD7 :1; + IO_WORD _PFD8 :1; + IO_WORD _PFD9 :1; + IO_WORD _PFD10 :1; + IO_WORD _PFD11 :1; + IO_WORD _PFD12 :1; + IO_WORD _PFD13 :1; + IO_WORD _PFD14 :1; + IO_WORD _PFD15 :1; + }bit; + struct{ + IO_WORD _PFD :16; + }bitc; + }PFD3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFD0 :1; + IO_BYTE _PFD1 :1; + IO_BYTE _PFD2 :1; + IO_BYTE _PFD3 :1; + IO_BYTE _PFD4 :1; + IO_BYTE _PFD5 :1; + IO_BYTE _PFD6 :1; + IO_BYTE _PFD7 :1; + }bit; + }PFDL3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFD8 :1; + IO_BYTE _PFD9 :1; + IO_BYTE _PFD10 :1; + IO_BYTE _PFD11 :1; + IO_BYTE _PFD12 :1; + IO_BYTE _PFD13 :1; + IO_BYTE _PFD14 :1; + IO_BYTE _PFD15 :1; + }bit; + }PFDH3STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _PFD0 :1; + IO_WORD _PFD1 :1; + IO_WORD _PFD2 :1; + IO_WORD _PFD3 :1; + IO_WORD _PFD4 :1; + IO_WORD _PFD5 :1; + IO_WORD _PFD6 :1; + IO_WORD _PFD7 :1; + IO_WORD _PFD8 :1; + IO_WORD _PFD9 :1; + IO_WORD _PFD10 :1; + IO_WORD _PFD11 :1; + IO_WORD _PFD12 :1; + IO_WORD _PFD13 :1; + IO_WORD _PFD14 :1; + IO_WORD _PFD15 :1; + }bit; + struct{ + IO_WORD _PFD :16; + }bitc; + }PFD4STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFD0 :1; + IO_BYTE _PFD1 :1; + IO_BYTE _PFD2 :1; + IO_BYTE _PFD3 :1; + IO_BYTE _PFD4 :1; + IO_BYTE _PFD5 :1; + IO_BYTE _PFD6 :1; + IO_BYTE _PFD7 :1; + }bit; + }PFDL4STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFD8 :1; + IO_BYTE _PFD9 :1; + IO_BYTE _PFD10 :1; + IO_BYTE _PFD11 :1; + IO_BYTE _PFD12 :1; + IO_BYTE _PFD13 :1; + IO_BYTE _PFD14 :1; + IO_BYTE _PFD15 :1; + }bit; + }PFDH4STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _PFD0 :1; + IO_WORD _PFD1 :1; + IO_WORD _PFD2 :1; + IO_WORD _PFD3 :1; + IO_WORD _PFD4 :1; + IO_WORD _PFD5 :1; + IO_WORD _PFD6 :1; + IO_WORD _PFD7 :1; + IO_WORD _PFD8 :1; + IO_WORD _PFD9 :1; + IO_WORD _PFD10 :1; + IO_WORD _PFD11 :1; + IO_WORD _PFD12 :1; + IO_WORD _PFD13 :1; + IO_WORD _PFD14 :1; + IO_WORD _PFD15 :1; + }bit; + struct{ + IO_WORD _PFD :16; + }bitc; + }PFD5STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFD0 :1; + IO_BYTE _PFD1 :1; + IO_BYTE _PFD2 :1; + IO_BYTE _PFD3 :1; + IO_BYTE _PFD4 :1; + IO_BYTE _PFD5 :1; + IO_BYTE _PFD6 :1; + IO_BYTE _PFD7 :1; + }bit; + }PFDL5STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFD8 :1; + IO_BYTE _PFD9 :1; + IO_BYTE _PFD10 :1; + IO_BYTE _PFD11 :1; + IO_BYTE _PFD12 :1; + IO_BYTE _PFD13 :1; + IO_BYTE _PFD14 :1; + IO_BYTE _PFD15 :1; + }bit; + }PFDH5STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _PFD0 :1; + IO_WORD _PFD1 :1; + IO_WORD _PFD2 :1; + IO_WORD _PFD3 :1; + IO_WORD _PFD4 :1; + IO_WORD _PFD5 :1; + IO_WORD _PFD6 :1; + IO_WORD _PFD7 :1; + IO_WORD _PFD8 :1; + IO_WORD _PFD9 :1; + IO_WORD _PFD10 :1; + IO_WORD _PFD11 :1; + IO_WORD _PFD12 :1; + IO_WORD _PFD13 :1; + IO_WORD _PFD14 :1; + IO_WORD _PFD15 :1; + }bit; + struct{ + IO_WORD _PFD :16; + }bitc; + }PFD6STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFD0 :1; + IO_BYTE _PFD1 :1; + IO_BYTE _PFD2 :1; + IO_BYTE _PFD3 :1; + IO_BYTE _PFD4 :1; + IO_BYTE _PFD5 :1; + IO_BYTE _PFD6 :1; + IO_BYTE _PFD7 :1; + }bit; + }PFDL6STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFD8 :1; + IO_BYTE _PFD9 :1; + IO_BYTE _PFD10 :1; + IO_BYTE _PFD11 :1; + IO_BYTE _PFD12 :1; + IO_BYTE _PFD13 :1; + IO_BYTE _PFD14 :1; + IO_BYTE _PFD15 :1; + }bit; + }PFDH6STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _PFD0 :1; + IO_WORD _PFD1 :1; + IO_WORD _PFD2 :1; + IO_WORD _PFD3 :1; + IO_WORD _PFD4 :1; + IO_WORD _PFD5 :1; + IO_WORD _PFD6 :1; + IO_WORD _PFD7 :1; + IO_WORD _PFD8 :1; + IO_WORD _PFD9 :1; + IO_WORD _PFD10 :1; + IO_WORD _PFD11 :1; + IO_WORD _PFD12 :1; + IO_WORD _PFD13 :1; + IO_WORD _PFD14 :1; + IO_WORD _PFD15 :1; + }bit; + struct{ + IO_WORD _PFD :16; + }bitc; + }PFD7STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFD0 :1; + IO_BYTE _PFD1 :1; + IO_BYTE _PFD2 :1; + IO_BYTE _PFD3 :1; + IO_BYTE _PFD4 :1; + IO_BYTE _PFD5 :1; + IO_BYTE _PFD6 :1; + IO_BYTE _PFD7 :1; + }bit; + }PFDL7STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFD8 :1; + IO_BYTE _PFD9 :1; + IO_BYTE _PFD10 :1; + IO_BYTE _PFD11 :1; + IO_BYTE _PFD12 :1; + IO_BYTE _PFD13 :1; + IO_BYTE _PFD14 :1; + IO_BYTE _PFD15 :1; + }bit; + }PFDH7STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _RDY :1; + IO_BYTE _RDYINT :1; + IO_BYTE _INTE :1; + IO_BYTE _WE :1; + IO_BYTE _CRBE :1; + IO_BYTE _DRBE :1; + IO_BYTE _RD19V :1; + IO_BYTE :1; + }bit; + }MFMCSSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _FAWC0 :1; + IO_WORD _FAWC1 :1; + IO_WORD _FAWC2 :1; + IO_WORD _SYNC :1; + IO_WORD _ADS :1; + IO_WORD _CLKBW :1; + IO_WORD _WEXL :1; + IO_WORD :1; + IO_WORD _ATDINIT :1; + IO_WORD _ATDL0 :1; + IO_WORD _ATDL1 :1; + IO_WORD _ATDEQD0 :1; + IO_WORD _ATDEQD1 :1; + IO_WORD _EQL0 :1; + IO_WORD _EQL1 :1; + IO_WORD _EQL2 :1; + }bit; + struct{ + IO_WORD _FAWC :3; + IO_WORD :6; + IO_WORD _ATDL :2; + IO_WORD _ATDEQD :2; + IO_WORD _EQL :3; + }bitc; + }MFMTCSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _FAWC0 :1; + IO_BYTE _FAWC1 :1; + IO_BYTE _FAWC2 :1; + IO_BYTE _SYNC :1; + IO_BYTE _ADS :1; + IO_BYTE _CLKBW :1; + IO_BYTE _WEXL :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _FAWC :3; + }bitc; + }MFMTCLSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ATDINIT :1; + IO_BYTE _ATDL0 :1; + IO_BYTE _ATDL1 :1; + IO_BYTE _ATDEQD0 :1; + IO_BYTE _ATDEQD1 :1; + IO_BYTE _EQL0 :1; + IO_BYTE _EQL1 :1; + IO_BYTE _EQL2 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE _ATDL :2; + IO_BYTE _ATDEQD :2; + IO_BYTE _EQL :3; + }bitc; + }MFMTCHSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _RDY :1; + IO_BYTE _RDYINT :1; + IO_BYTE _INTE :1; + IO_BYTE _WE :1; + IO_BYTE _CRBE :1; + IO_BYTE _DRBE :1; + IO_BYTE _RD19V :1; + IO_BYTE :1; + }bit; + }SFMCSSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _FAWC0 :1; + IO_WORD _FAWC1 :1; + IO_WORD _FAWC2 :1; + IO_WORD _SYNC :1; + IO_WORD _ADS :1; + IO_WORD _CLKBW :1; + IO_WORD _WEXL :1; + IO_WORD :1; + IO_WORD _ATDINIT :1; + IO_WORD _ATDL0 :1; + IO_WORD _ATDL1 :1; + IO_WORD _ATDEQD0 :1; + IO_WORD _ATDEQD1 :1; + IO_WORD _EQL0 :1; + IO_WORD _EQL1 :1; + IO_WORD _EQL2 :1; + }bit; + struct{ + IO_WORD _FAWC :3; + IO_WORD :6; + IO_WORD _ATDL :2; + IO_WORD _ATDEQD :2; + IO_WORD _EQL :3; + }bitc; + }SFMTCSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _FAWC0 :1; + IO_BYTE _FAWC1 :1; + IO_BYTE _FAWC2 :1; + IO_BYTE _SYNC :1; + IO_BYTE _ADS :1; + IO_BYTE _CLKBW :1; + IO_BYTE _WEXL :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _FAWC :3; + }bitc; + }SFMTCLSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ATDINIT :1; + IO_BYTE _ATDL0 :1; + IO_BYTE _ATDL1 :1; + IO_BYTE _ATDEQD0 :1; + IO_BYTE _ATDEQD1 :1; + IO_BYTE _EQL0 :1; + IO_BYTE _EQL1 :1; + IO_BYTE _EQL2 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE _ATDL :2; + IO_BYTE _ATDEQD :2; + IO_BYTE _EQL :3; + }bitc; + }SFMTCHSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _WCB0 :1; + IO_BYTE _WCB1 :1; + IO_BYTE _WCB2 :1; + IO_BYTE _WCB3 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _WCB :4; + }bitc; + }FMWC0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _WCA0 :1; + IO_BYTE _WCA1 :1; + IO_BYTE _WCA2 :1; + IO_BYTE _WCA3 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _WCA :4; + }bitc; + }FMWC1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _WC32 :1; + IO_BYTE _WC33 :1; + IO_BYTE _WC34 :1; + IO_BYTE _WC35 :1; + IO_BYTE _WC36 :1; + IO_BYTE _WC37 :1; + IO_BYTE _WC38 :1; + IO_BYTE _WC39 :1; + }bit; + struct{ + IO_BYTE _WC3 :8; + }bitc; + }FMWC5STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SMS0 :1; + IO_BYTE _SMS1 :1; + IO_BYTE _SPL :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _SMS :2; + }bitc; + }SMCRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SC1S0 :1; + IO_BYTE _SC1S1 :1; + IO_BYTE _SC2S0 :1; + IO_BYTE _SC2S1 :1; + IO_BYTE _RCE :1; + IO_BYTE _MCE :1; + IO_BYTE _PCE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _SC1S :2; + IO_BYTE _SC2S :2; + }bitc; + }CKSRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MCST0 :1; + IO_BYTE _MCST1 :1; + IO_BYTE _MCST2 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _PCST :1; + IO_BYTE _MRFBE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _MCST :3; + }bitc; + }CKSSRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SC1M0 :1; + IO_BYTE _SC1M1 :1; + IO_BYTE _SC2M0 :1; + IO_BYTE _SC2M1 :1; + IO_BYTE _RCM :1; + IO_BYTE _MCM :1; + IO_BYTE _PCM :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _SC1M :2; + IO_BYTE _SC2M :2; + }bitc; + }CKMRSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _RCFS :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _BCD0 :1; + IO_WORD _BCD1 :1; + IO_WORD _BCD2 :1; + IO_WORD _BCD3 :1; + IO_WORD _PC1D0 :1; + IO_WORD _PC1D1 :1; + IO_WORD _PC1D2 :1; + IO_WORD _PC1D3 :1; + IO_WORD _PC2D0 :1; + IO_WORD _PC2D1 :1; + IO_WORD _PC2D2 :1; + IO_WORD _PC2D3 :1; + }bit; + struct{ + IO_WORD :4; + IO_WORD _BCD :4; + IO_WORD _PC1D :4; + IO_WORD _PC2D :4; + }bitc; + }CKFCRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _RCFS :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _BCD0 :1; + IO_BYTE _BCD1 :1; + IO_BYTE _BCD2 :1; + IO_BYTE _BCD3 :1; + }bit; + struct{ + IO_BYTE :4; + IO_BYTE _BCD :4; + }bitc; + }CKFCRLSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PC1D0 :1; + IO_BYTE _PC1D1 :1; + IO_BYTE _PC1D2 :1; + IO_BYTE _PC1D3 :1; + IO_BYTE _PC2D0 :1; + IO_BYTE _PC2D1 :1; + IO_BYTE _PC2D2 :1; + IO_BYTE _PC2D3 :1; + }bit; + struct{ + IO_BYTE _PC1D :4; + IO_BYTE _PC2D :4; + }bitc; + }CKFCRHSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _PMS0 :1; + IO_WORD _PMS1 :1; + IO_WORD _PMS2 :1; + IO_WORD _PMS3 :1; + IO_WORD _PMS4 :1; + IO_WORD _VMS0 :1; + IO_WORD _VMS1 :1; + IO_WORD _VMS2 :1; + IO_WORD _PC3D0 :1; + IO_WORD _PC3D1 :1; + IO_WORD _PC3D2 :1; + IO_WORD _PC3D3 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD _PMS :5; + IO_WORD _VMS :3; + IO_WORD _PC3D :4; + }bitc; + }PLLCRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PMS0 :1; + IO_BYTE _PMS1 :1; + IO_BYTE _PMS2 :1; + IO_BYTE _PMS3 :1; + IO_BYTE _PMS4 :1; + IO_BYTE _VMS0 :1; + IO_BYTE _VMS1 :1; + IO_BYTE _VMS2 :1; + }bit; + struct{ + IO_BYTE _PMS :5; + IO_BYTE _VMS :3; + }bitc; + }PLLCRLSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PC3D0 :1; + IO_BYTE _PC3D1 :1; + IO_BYTE _PC3D2 :1; + IO_BYTE _PC3D3 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _PC3D :4; + }bitc; + }PLLCRHSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _RCTI0 :1; + IO_BYTE _RCTI1 :1; + IO_BYTE _RCTI2 :1; + IO_BYTE _RCTI3 :1; + IO_BYTE _RCTR :1; + IO_BYTE _RCTIF :1; + IO_BYTE _RCTIE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _RCTI :4; + }bitc; + }RCTCRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MCTI0 :1; + IO_BYTE _MCTI1 :1; + IO_BYTE _MCTI2 :1; + IO_BYTE _MCTI3 :1; + IO_BYTE _MCTR :1; + IO_BYTE _MCTIF :1; + IO_BYTE _MCTIE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _MCTI :4; + }bitc; + }MCTCRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PRST :1; + IO_BYTE _ERST :1; + IO_BYTE _MCRST :1; + IO_BYTE :1; + IO_BYTE _SRST :1; + IO_BYTE _WRST :1; + IO_BYTE _MCMF :1; + IO_BYTE :1; + }bit; + }RCCSRCSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SRSTG :1; + IO_BYTE _LVRE :1; + IO_BYTE _LVDE :1; + IO_BYTE _CSDRE :1; + IO_BYTE _MCSDI :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }RCRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PRST :1; + IO_BYTE _ERST :1; + IO_BYTE _MCRST :1; + IO_BYTE :1; + IO_BYTE _SRST :1; + IO_BYTE _WRST :1; + IO_BYTE _MCMF :1; + IO_BYTE :1; + }bit; + }RCCSRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _WTI0 :1; + IO_BYTE _WTI1 :1; + IO_BYTE _WTI2 :1; + IO_BYTE _WTI3 :1; + IO_BYTE _WTCS0 :1; + IO_BYTE _WTCS1 :1; + IO_BYTE _RSTP :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _WTI :4; + IO_BYTE _WTCS :2; + }bitc; + }WDTCSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _WCP0 :1; + IO_BYTE _WCP1 :1; + IO_BYTE _WCP2 :1; + IO_BYTE _WCP3 :1; + IO_BYTE _WCP4 :1; + IO_BYTE _WCP5 :1; + IO_BYTE _WCP6 :1; + IO_BYTE _WCP7 :1; + }bit; + struct{ + IO_BYTE _WCP :8; + }bitc; + }WDTCPSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CKOE0 :1; + IO_BYTE _CKOXE0 :1; + IO_BYTE _RUNC0 :1; + IO_BYTE _RUNM0 :1; + IO_BYTE _CKOE1 :1; + IO_BYTE _CKOXE1 :1; + IO_BYTE _RUNC1 :1; + IO_BYTE _RUNM1 :1; + }bit; + }COARSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SEL0 :1; + IO_BYTE _SEL1 :1; + IO_BYTE _SEL2 :1; + IO_BYTE _SEL3 :1; + IO_BYTE _DIV0 :1; + IO_BYTE _DIV1 :1; + IO_BYTE _DIV2 :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _SEL :4; + IO_BYTE _DIV :3; + }bitc; + }COCR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SEL0 :1; + IO_BYTE _SEL1 :1; + IO_BYTE _SEL2 :1; + IO_BYTE _SEL3 :1; + IO_BYTE _DIV0 :1; + IO_BYTE _DIV1 :1; + IO_BYTE _DIV2 :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _SEL :4; + IO_BYTE _DIV :3; + }bitc; + }COCR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PDX :1; + IO_BYTE _MODEN :1; + IO_BYTE _MODRUN :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }CMCRSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _C0 :1; + IO_WORD _C1 :1; + IO_WORD _C2 :1; + IO_WORD _C3 :1; + IO_WORD _C4 :1; + IO_WORD _N0 :1; + IO_WORD _N1 :1; + IO_WORD _N2 :1; + IO_WORD _N3 :1; + IO_WORD _K0 :1; + IO_WORD _K1 :1; + IO_WORD _K2 :1; + IO_WORD _K3 :1; + IO_WORD _K4 :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD _C :5; + IO_WORD _N :3; + IO_WORD :1; + IO_WORD _K :5; + }bitc; + }CMPRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _C0 :1; + IO_BYTE _C1 :1; + IO_BYTE _C2 :1; + IO_BYTE _C3 :1; + IO_BYTE _C4 :1; + IO_BYTE _N0 :1; + IO_BYTE _N1 :1; + IO_BYTE _N2 :1; + }bit; + struct{ + IO_BYTE _C :5; + IO_BYTE _N :3; + }bitc; + }CMPRLSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _N3 :1; + IO_BYTE _K0 :1; + IO_BYTE _K1 :1; + IO_BYTE _K2 :1; + IO_BYTE _K3 :1; + IO_BYTE _K4 :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE _K :5; + }bitc; + }CMPRHSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _LPBM0 :1; + IO_BYTE _LPBM1 :1; + IO_BYTE _LPMB2 :1; + IO_BYTE _LPMA0 :1; + IO_BYTE _LPMA1 :1; + IO_BYTE _LPMA2 :1; + IO_BYTE _HPM0 :1; + IO_BYTE _HPM1 :1; + }bit; + struct{ + IO_BYTE _LPBM :3; + IO_BYTE _LPMA :3; + IO_BYTE _HPM :2; + }bitc; + }VRCRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D0 :1; + IO_BYTE _D1 :1; + IO_BYTE _D2 :1; + IO_BYTE _D3 :1; + IO_BYTE _D4 :1; + IO_BYTE _D5 :1; + IO_BYTE _D6 :1; + IO_BYTE _D7 :1; + }bit; + }DDR00STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D0 :1; + IO_BYTE _D1 :1; + IO_BYTE _D2 :1; + IO_BYTE _D3 :1; + IO_BYTE _D4 :1; + IO_BYTE _D5 :1; + IO_BYTE _D6 :1; + IO_BYTE _D7 :1; + }bit; + }DDR01STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D0 :1; + IO_BYTE _D1 :1; + IO_BYTE _D2 :1; + IO_BYTE _D3 :1; + IO_BYTE _D4 :1; + IO_BYTE _D5 :1; + IO_BYTE _D6 :1; + IO_BYTE _D7 :1; + }bit; + }DDR02STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D0 :1; + IO_BYTE _D1 :1; + IO_BYTE _D2 :1; + IO_BYTE _D3 :1; + IO_BYTE _D4 :1; + IO_BYTE _D5 :1; + IO_BYTE _D6 :1; + IO_BYTE _D7 :1; + }bit; + }DDR03STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D0 :1; + IO_BYTE _D1 :1; + IO_BYTE _D2 :1; + IO_BYTE _D3 :1; + IO_BYTE _D4 :1; + IO_BYTE _D5 :1; + IO_BYTE _D6 :1; + IO_BYTE _D7 :1; + }bit; + }DDR04STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D0 :1; + IO_BYTE _D1 :1; + IO_BYTE _D2 :1; + IO_BYTE _D3 :1; + IO_BYTE _D4 :1; + IO_BYTE _D5 :1; + IO_BYTE _D6 :1; + IO_BYTE _D7 :1; + }bit; + }DDR05STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D0 :1; + IO_BYTE _D1 :1; + IO_BYTE _D2 :1; + IO_BYTE _D3 :1; + IO_BYTE _D4 :1; + IO_BYTE _D5 :1; + IO_BYTE _D6 :1; + IO_BYTE _D7 :1; + }bit; + }DDR06STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D0 :1; + IO_BYTE _D1 :1; + IO_BYTE _D2 :1; + IO_BYTE _D3 :1; + IO_BYTE _D4 :1; + IO_BYTE _D5 :1; + IO_BYTE _D6 :1; + IO_BYTE _D7 :1; + }bit; + }DDR07STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D0 :1; + IO_BYTE _D1 :1; + IO_BYTE _D2 :1; + IO_BYTE _D3 :1; + IO_BYTE _D4 :1; + IO_BYTE _D5 :1; + IO_BYTE _D6 :1; + IO_BYTE _D7 :1; + }bit; + }DDR08STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D0 :1; + IO_BYTE _D1 :1; + IO_BYTE _D2 :1; + IO_BYTE _D3 :1; + IO_BYTE _D4 :1; + IO_BYTE _D5 :1; + IO_BYTE _D6 :1; + IO_BYTE _D7 :1; + }bit; + }DDR09STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D0 :1; + IO_BYTE _D1 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }DDR10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IE0 :1; + IO_BYTE _IE1 :1; + IO_BYTE _IE2 :1; + IO_BYTE _IE3 :1; + IO_BYTE _IE4 :1; + IO_BYTE _IE5 :1; + IO_BYTE _IE6 :1; + IO_BYTE _IE7 :1; + }bit; + }PIER00STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IE0 :1; + IO_BYTE _IE1 :1; + IO_BYTE _IE2 :1; + IO_BYTE _IE3 :1; + IO_BYTE _IE4 :1; + IO_BYTE _IE5 :1; + IO_BYTE _IE6 :1; + IO_BYTE _IE7 :1; + }bit; + }PIER01STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IE0 :1; + IO_BYTE _IE1 :1; + IO_BYTE _IE2 :1; + IO_BYTE _IE3 :1; + IO_BYTE _IE4 :1; + IO_BYTE _IE5 :1; + IO_BYTE _IE6 :1; + IO_BYTE _IE7 :1; + }bit; + }PIER02STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IE0 :1; + IO_BYTE _IE1 :1; + IO_BYTE _IE2 :1; + IO_BYTE _IE3 :1; + IO_BYTE _IE4 :1; + IO_BYTE _IE5 :1; + IO_BYTE _IE6 :1; + IO_BYTE _IE7 :1; + }bit; + }PIER03STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IE0 :1; + IO_BYTE _IE1 :1; + IO_BYTE _IE2 :1; + IO_BYTE _IE3 :1; + IO_BYTE _IE4 :1; + IO_BYTE _IE5 :1; + IO_BYTE _IE6 :1; + IO_BYTE _IE7 :1; + }bit; + }PIER04STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IE0 :1; + IO_BYTE _IE1 :1; + IO_BYTE _IE2 :1; + IO_BYTE _IE3 :1; + IO_BYTE _IE4 :1; + IO_BYTE _IE5 :1; + IO_BYTE _IE6 :1; + IO_BYTE _IE7 :1; + }bit; + }PIER05STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IE0 :1; + IO_BYTE _IE1 :1; + IO_BYTE _IE2 :1; + IO_BYTE _IE3 :1; + IO_BYTE _IE4 :1; + IO_BYTE _IE5 :1; + IO_BYTE _IE6 :1; + IO_BYTE _IE7 :1; + }bit; + }PIER06STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IE0 :1; + IO_BYTE _IE1 :1; + IO_BYTE _IE2 :1; + IO_BYTE _IE3 :1; + IO_BYTE _IE4 :1; + IO_BYTE _IE5 :1; + IO_BYTE _IE6 :1; + IO_BYTE _IE7 :1; + }bit; + }PIER07STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IE0 :1; + IO_BYTE _IE1 :1; + IO_BYTE _IE2 :1; + IO_BYTE _IE3 :1; + IO_BYTE _IE4 :1; + IO_BYTE _IE5 :1; + IO_BYTE _IE6 :1; + IO_BYTE _IE7 :1; + }bit; + }PIER08STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IE0 :1; + IO_BYTE _IE1 :1; + IO_BYTE _IE2 :1; + IO_BYTE _IE3 :1; + IO_BYTE _IE4 :1; + IO_BYTE _IE5 :1; + IO_BYTE _IE6 :1; + IO_BYTE _IE7 :1; + }bit; + }PIER09STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IE0 :1; + IO_BYTE _IE1 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }PIER10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IL0 :1; + IO_BYTE _IL1 :1; + IO_BYTE _IL2 :1; + IO_BYTE _IL3 :1; + IO_BYTE _IL4 :1; + IO_BYTE _IL5 :1; + IO_BYTE _IL6 :1; + IO_BYTE _IL7 :1; + }bit; + }PILR00STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IL0 :1; + IO_BYTE _IL1 :1; + IO_BYTE _IL2 :1; + IO_BYTE _IL3 :1; + IO_BYTE _IL4 :1; + IO_BYTE _IL5 :1; + IO_BYTE _IL6 :1; + IO_BYTE _IL7 :1; + }bit; + }PILR01STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IL0 :1; + IO_BYTE _IL1 :1; + IO_BYTE _IL2 :1; + IO_BYTE _IL3 :1; + IO_BYTE _IL4 :1; + IO_BYTE _IL5 :1; + IO_BYTE _IL6 :1; + IO_BYTE _IL7 :1; + }bit; + }PILR02STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IL0 :1; + IO_BYTE _IL1 :1; + IO_BYTE _IL2 :1; + IO_BYTE _IL3 :1; + IO_BYTE _IL4 :1; + IO_BYTE _IL5 :1; + IO_BYTE _IL6 :1; + IO_BYTE _IL7 :1; + }bit; + }PILR03STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IL0 :1; + IO_BYTE _IL1 :1; + IO_BYTE _IL2 :1; + IO_BYTE _IL3 :1; + IO_BYTE _IL4 :1; + IO_BYTE _IL5 :1; + IO_BYTE _IL6 :1; + IO_BYTE _IL7 :1; + }bit; + }PILR04STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IL0 :1; + IO_BYTE _IL1 :1; + IO_BYTE _IL2 :1; + IO_BYTE _IL3 :1; + IO_BYTE _IL4 :1; + IO_BYTE _IL5 :1; + IO_BYTE _IL6 :1; + IO_BYTE _IL7 :1; + }bit; + }PILR05STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IL0 :1; + IO_BYTE _IL1 :1; + IO_BYTE _IL2 :1; + IO_BYTE _IL3 :1; + IO_BYTE _IL4 :1; + IO_BYTE _IL5 :1; + IO_BYTE _IL6 :1; + IO_BYTE _IL7 :1; + }bit; + }PILR06STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IL0 :1; + IO_BYTE _IL1 :1; + IO_BYTE _IL2 :1; + IO_BYTE _IL3 :1; + IO_BYTE _IL4 :1; + IO_BYTE _IL5 :1; + IO_BYTE _IL6 :1; + IO_BYTE _IL7 :1; + }bit; + }PILR07STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IL0 :1; + IO_BYTE _IL1 :1; + IO_BYTE _IL2 :1; + IO_BYTE _IL3 :1; + IO_BYTE _IL4 :1; + IO_BYTE _IL5 :1; + IO_BYTE _IL6 :1; + IO_BYTE _IL7 :1; + }bit; + }PILR08STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IL0 :1; + IO_BYTE _IL1 :1; + IO_BYTE _IL2 :1; + IO_BYTE _IL3 :1; + IO_BYTE _IL4 :1; + IO_BYTE _IL5 :1; + IO_BYTE _IL6 :1; + IO_BYTE _IL7 :1; + }bit; + }PILR09STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IL0 :1; + IO_BYTE _IL1 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }PILR10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EIL0 :1; + IO_BYTE _EIL1 :1; + IO_BYTE _EIL2 :1; + IO_BYTE _EIL3 :1; + IO_BYTE _EIL4 :1; + IO_BYTE _EIL5 :1; + IO_BYTE _EIL6 :1; + IO_BYTE _EIL7 :1; + }bit; + }EPILR00STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EIL0 :1; + IO_BYTE _EIL1 :1; + IO_BYTE _EIL2 :1; + IO_BYTE _EIL3 :1; + IO_BYTE _EIL4 :1; + IO_BYTE _EIL5 :1; + IO_BYTE _EIL6 :1; + IO_BYTE _EIL7 :1; + }bit; + }EPILR01STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EIL0 :1; + IO_BYTE _EIL1 :1; + IO_BYTE _EIL2 :1; + IO_BYTE _EIL3 :1; + IO_BYTE _EIL4 :1; + IO_BYTE _EIL5 :1; + IO_BYTE _EIL6 :1; + IO_BYTE _EIL7 :1; + }bit; + }EPILR02STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EIL0 :1; + IO_BYTE _EIL1 :1; + IO_BYTE _EIL2 :1; + IO_BYTE _EIL3 :1; + IO_BYTE _EIL4 :1; + IO_BYTE _EIL5 :1; + IO_BYTE _EIL6 :1; + IO_BYTE _EIL7 :1; + }bit; + }EPILR03STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EIL0 :1; + IO_BYTE _EIL1 :1; + IO_BYTE _EIL2 :1; + IO_BYTE _EIL3 :1; + IO_BYTE _EIL4 :1; + IO_BYTE _EIL5 :1; + IO_BYTE _EIL6 :1; + IO_BYTE _EIL7 :1; + }bit; + }EPILR04STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EIL0 :1; + IO_BYTE _EIL1 :1; + IO_BYTE _EIL2 :1; + IO_BYTE _EIL3 :1; + IO_BYTE _EIL4 :1; + IO_BYTE _EIL5 :1; + IO_BYTE _EIL6 :1; + IO_BYTE _EIL7 :1; + }bit; + }EPILR05STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EIL0 :1; + IO_BYTE _EIL1 :1; + IO_BYTE _EIL2 :1; + IO_BYTE _EIL3 :1; + IO_BYTE _EIL4 :1; + IO_BYTE _EIL5 :1; + IO_BYTE _EIL6 :1; + IO_BYTE _EIL7 :1; + }bit; + }EPILR06STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EIL0 :1; + IO_BYTE _EIL1 :1; + IO_BYTE _EIL2 :1; + IO_BYTE _EIL3 :1; + IO_BYTE _EIL4 :1; + IO_BYTE _EIL5 :1; + IO_BYTE _EIL6 :1; + IO_BYTE _EIL7 :1; + }bit; + }EPILR07STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EIL0 :1; + IO_BYTE _EIL1 :1; + IO_BYTE _EIL2 :1; + IO_BYTE _EIL3 :1; + IO_BYTE _EIL4 :1; + IO_BYTE _EIL5 :1; + IO_BYTE _EIL6 :1; + IO_BYTE _EIL7 :1; + }bit; + }EPILR08STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EIL0 :1; + IO_BYTE _EIL1 :1; + IO_BYTE _EIL2 :1; + IO_BYTE _EIL3 :1; + IO_BYTE _EIL4 :1; + IO_BYTE _EIL5 :1; + IO_BYTE _EIL6 :1; + IO_BYTE _EIL7 :1; + }bit; + }EPILR09STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EIL0 :1; + IO_BYTE _EIL1 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }EPILR10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OD0 :1; + IO_BYTE _OD1 :1; + IO_BYTE _OD2 :1; + IO_BYTE _OD3 :1; + IO_BYTE _OD4 :1; + IO_BYTE _OD5 :1; + IO_BYTE _OD6 :1; + IO_BYTE _OD7 :1; + }bit; + }PODR00STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OD0 :1; + IO_BYTE _OD1 :1; + IO_BYTE _OD2 :1; + IO_BYTE _OD3 :1; + IO_BYTE _OD4 :1; + IO_BYTE _OD5 :1; + IO_BYTE _OD6 :1; + IO_BYTE _OD7 :1; + }bit; + }PODR01STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OD0 :1; + IO_BYTE _OD1 :1; + IO_BYTE _OD2 :1; + IO_BYTE _OD3 :1; + IO_BYTE _OD4 :1; + IO_BYTE _OD5 :1; + IO_BYTE _OD6 :1; + IO_BYTE _OD7 :1; + }bit; + }PODR02STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OD0 :1; + IO_BYTE _OD1 :1; + IO_BYTE _OD2 :1; + IO_BYTE _OD3 :1; + IO_BYTE _OD4 :1; + IO_BYTE _OD5 :1; + IO_BYTE _OD6 :1; + IO_BYTE _OD7 :1; + }bit; + }PODR03STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OD0 :1; + IO_BYTE _OD1 :1; + IO_BYTE _OD2 :1; + IO_BYTE _OD3 :1; + IO_BYTE _OD4 :1; + IO_BYTE _OD5 :1; + IO_BYTE _OD6 :1; + IO_BYTE _OD7 :1; + }bit; + }PODR04STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OD0 :1; + IO_BYTE _OD1 :1; + IO_BYTE _OD2 :1; + IO_BYTE _OD3 :1; + IO_BYTE _OD4 :1; + IO_BYTE _OD5 :1; + IO_BYTE _OD6 :1; + IO_BYTE _OD7 :1; + }bit; + }PODR05STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OD0 :1; + IO_BYTE _OD1 :1; + IO_BYTE _OD2 :1; + IO_BYTE _OD3 :1; + IO_BYTE _OD4 :1; + IO_BYTE _OD5 :1; + IO_BYTE _OD6 :1; + IO_BYTE _OD7 :1; + }bit; + }PODR06STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OD0 :1; + IO_BYTE _OD1 :1; + IO_BYTE _OD2 :1; + IO_BYTE _OD3 :1; + IO_BYTE _OD4 :1; + IO_BYTE _OD5 :1; + IO_BYTE _OD6 :1; + IO_BYTE _OD7 :1; + }bit; + }PODR07STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OD0 :1; + IO_BYTE _OD1 :1; + IO_BYTE _OD2 :1; + IO_BYTE _OD3 :1; + IO_BYTE _OD4 :1; + IO_BYTE _OD5 :1; + IO_BYTE _OD6 :1; + IO_BYTE _OD7 :1; + }bit; + }PODR08STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OD0 :1; + IO_BYTE _OD1 :1; + IO_BYTE _OD2 :1; + IO_BYTE _OD3 :1; + IO_BYTE _OD4 :1; + IO_BYTE _OD5 :1; + IO_BYTE _OD6 :1; + IO_BYTE _OD7 :1; + }bit; + }PODR09STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OD0 :1; + IO_BYTE _OD1 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }PODR10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _HD0 :1; + IO_BYTE _HD1 :1; + IO_BYTE _HD2 :1; + IO_BYTE _HD3 :1; + IO_BYTE _HD4 :1; + IO_BYTE _HD5 :1; + IO_BYTE _HD6 :1; + IO_BYTE _HD7 :1; + }bit; + }PHDR08STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _HD0 :1; + IO_BYTE _HD1 :1; + IO_BYTE _HD2 :1; + IO_BYTE _HD3 :1; + IO_BYTE _HD4 :1; + IO_BYTE _HD5 :1; + IO_BYTE _HD6 :1; + IO_BYTE _HD7 :1; + }bit; + }PHDR09STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _HD0 :1; + IO_BYTE _HD1 :1; + IO_BYTE _HD2 :1; + IO_BYTE _HD3 :1; + IO_BYTE _HD4 :1; + IO_BYTE _HD5 :1; + IO_BYTE _HD6 :1; + IO_BYTE _HD7 :1; + }bit; + }PHDR10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PU0 :1; + IO_BYTE _PU1 :1; + IO_BYTE _PU2 :1; + IO_BYTE _PU3 :1; + IO_BYTE _PU4 :1; + IO_BYTE _PU5 :1; + IO_BYTE _PU6 :1; + IO_BYTE _PU7 :1; + }bit; + }PUCR00STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PU0 :1; + IO_BYTE _PU1 :1; + IO_BYTE _PU2 :1; + IO_BYTE _PU3 :1; + IO_BYTE _PU4 :1; + IO_BYTE _PU5 :1; + IO_BYTE _PU6 :1; + IO_BYTE _PU7 :1; + }bit; + }PUCR01STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PU0 :1; + IO_BYTE _PU1 :1; + IO_BYTE _PU2 :1; + IO_BYTE _PU3 :1; + IO_BYTE _PU4 :1; + IO_BYTE _PU5 :1; + IO_BYTE _PU6 :1; + IO_BYTE _PU7 :1; + }bit; + }PUCR02STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PU0 :1; + IO_BYTE _PU1 :1; + IO_BYTE _PU2 :1; + IO_BYTE _PU3 :1; + IO_BYTE _PU4 :1; + IO_BYTE _PU5 :1; + IO_BYTE _PU6 :1; + IO_BYTE _PU7 :1; + }bit; + }PUCR03STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PU0 :1; + IO_BYTE _PU1 :1; + IO_BYTE _PU2 :1; + IO_BYTE _PU3 :1; + IO_BYTE _PU4 :1; + IO_BYTE _PU5 :1; + IO_BYTE _PU6 :1; + IO_BYTE _PU7 :1; + }bit; + }PUCR04STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PU0 :1; + IO_BYTE _PU1 :1; + IO_BYTE _PU2 :1; + IO_BYTE _PU3 :1; + IO_BYTE _PU4 :1; + IO_BYTE _PU5 :1; + IO_BYTE _PU6 :1; + IO_BYTE _PU7 :1; + }bit; + }PUCR05STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PU0 :1; + IO_BYTE _PU1 :1; + IO_BYTE _PU2 :1; + IO_BYTE _PU3 :1; + IO_BYTE _PU4 :1; + IO_BYTE _PU5 :1; + IO_BYTE _PU6 :1; + IO_BYTE _PU7 :1; + }bit; + }PUCR06STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PU0 :1; + IO_BYTE _PU1 :1; + IO_BYTE _PU2 :1; + IO_BYTE _PU3 :1; + IO_BYTE _PU4 :1; + IO_BYTE _PU5 :1; + IO_BYTE _PU6 :1; + IO_BYTE _PU7 :1; + }bit; + }PUCR07STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PU0 :1; + IO_BYTE _PU1 :1; + IO_BYTE _PU2 :1; + IO_BYTE _PU3 :1; + IO_BYTE _PU4 :1; + IO_BYTE _PU5 :1; + IO_BYTE _PU6 :1; + IO_BYTE _PU7 :1; + }bit; + }PUCR08STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PU0 :1; + IO_BYTE _PU1 :1; + IO_BYTE _PU2 :1; + IO_BYTE _PU3 :1; + IO_BYTE _PU4 :1; + IO_BYTE _PU5 :1; + IO_BYTE _PU6 :1; + IO_BYTE _PU7 :1; + }bit; + }PUCR09STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PU0 :1; + IO_BYTE _PU1 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }PUCR10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PS0 :1; + IO_BYTE _PS1 :1; + IO_BYTE _PS2 :1; + IO_BYTE _PS3 :1; + IO_BYTE _PS4 :1; + IO_BYTE _PS5 :1; + IO_BYTE _PS6 :1; + IO_BYTE _PS7 :1; + }bit; + }EPSR00STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PS0 :1; + IO_BYTE _PS1 :1; + IO_BYTE _PS2 :1; + IO_BYTE _PS3 :1; + IO_BYTE _PS4 :1; + IO_BYTE _PS5 :1; + IO_BYTE _PS6 :1; + IO_BYTE _PS7 :1; + }bit; + }EPSR01STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PS0 :1; + IO_BYTE _PS1 :1; + IO_BYTE _PS2 :1; + IO_BYTE _PS3 :1; + IO_BYTE _PS4 :1; + IO_BYTE _PS5 :1; + IO_BYTE _PS6 :1; + IO_BYTE _PS7 :1; + }bit; + }EPSR02STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PS0 :1; + IO_BYTE _PS1 :1; + IO_BYTE _PS2 :1; + IO_BYTE _PS3 :1; + IO_BYTE _PS4 :1; + IO_BYTE _PS5 :1; + IO_BYTE _PS6 :1; + IO_BYTE _PS7 :1; + }bit; + }EPSR03STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PS0 :1; + IO_BYTE _PS1 :1; + IO_BYTE _PS2 :1; + IO_BYTE _PS3 :1; + IO_BYTE _PS4 :1; + IO_BYTE _PS5 :1; + IO_BYTE _PS6 :1; + IO_BYTE _PS7 :1; + }bit; + }EPSR04STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PS0 :1; + IO_BYTE _PS1 :1; + IO_BYTE _PS2 :1; + IO_BYTE _PS3 :1; + IO_BYTE _PS4 :1; + IO_BYTE _PS5 :1; + IO_BYTE _PS6 :1; + IO_BYTE _PS7 :1; + }bit; + }EPSR05STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PS0 :1; + IO_BYTE _PS1 :1; + IO_BYTE _PS2 :1; + IO_BYTE _PS3 :1; + IO_BYTE _PS4 :1; + IO_BYTE _PS5 :1; + IO_BYTE _PS6 :1; + IO_BYTE _PS7 :1; + }bit; + }EPSR06STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PS0 :1; + IO_BYTE _PS1 :1; + IO_BYTE _PS2 :1; + IO_BYTE _PS3 :1; + IO_BYTE _PS4 :1; + IO_BYTE _PS5 :1; + IO_BYTE _PS6 :1; + IO_BYTE _PS7 :1; + }bit; + }EPSR07STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PS0 :1; + IO_BYTE _PS1 :1; + IO_BYTE _PS2 :1; + IO_BYTE _PS3 :1; + IO_BYTE _PS4 :1; + IO_BYTE _PS5 :1; + IO_BYTE _PS6 :1; + IO_BYTE _PS7 :1; + }bit; + }EPSR08STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PS0 :1; + IO_BYTE _PS1 :1; + IO_BYTE _PS2 :1; + IO_BYTE _PS3 :1; + IO_BYTE _PS4 :1; + IO_BYTE _PS5 :1; + IO_BYTE _PS6 :1; + IO_BYTE _PS7 :1; + }bit; + }EPSR09STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PS0 :1; + IO_BYTE _PS1 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }EPSR10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ADE0 :1; + IO_BYTE _ADE1 :1; + IO_BYTE _ADE2 :1; + IO_BYTE _ADE3 :1; + IO_BYTE _ADE4 :1; + IO_BYTE _ADE5 :1; + IO_BYTE _ADE6 :1; + IO_BYTE _ADE7 :1; + }bit; + }ADER0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ADE8 :1; + IO_BYTE _ADE9 :1; + IO_BYTE _ADE10 :1; + IO_BYTE _ADE11 :1; + IO_BYTE _ADE12 :1; + IO_BYTE _ADE13 :1; + IO_BYTE _ADE14 :1; + IO_BYTE _ADE15 :1; + }bit; + }ADER1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ADE16 :1; + IO_BYTE _ADE17 :1; + IO_BYTE _ADE18 :1; + IO_BYTE _ADE19 :1; + IO_BYTE _ADE20 :1; + IO_BYTE _ADE21 :1; + IO_BYTE _ADE22 :1; + IO_BYTE _ADE23 :1; + }bit; + }ADER2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INT0_R :1; + IO_BYTE _INT1_R :1; + IO_BYTE _INT2_R :1; + IO_BYTE _INT3_R :1; + IO_BYTE _INT4_R :1; + IO_BYTE _INT5_R :1; + IO_BYTE _INT6_R :1; + IO_BYTE _INT7_R :1; + }bit; + }PRRR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INT8_R :1; + IO_BYTE _INT9_R :1; + IO_BYTE _INT10_R :1; + IO_BYTE _INT11_R :1; + IO_BYTE _INT12_R :1; + IO_BYTE _INT13_R :1; + IO_BYTE _INT14_R :1; + IO_BYTE _INT15_R :1; + }bit; + }PRRR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PPG0_R :1; + IO_BYTE _PPG1_R :1; + IO_BYTE _PPG2_R :1; + IO_BYTE _PPG3_R :1; + IO_BYTE _PPG4_R :1; + IO_BYTE _PPG5_R :1; + IO_BYTE _PPG6_R :1; + IO_BYTE _PPG7_R :1; + }bit; + }PRRR2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TIN0_R :1; + IO_BYTE _TOT0_R :1; + IO_BYTE _TIN1_R :1; + IO_BYTE _TOT1_R :1; + IO_BYTE _TIN2_R :1; + IO_BYTE _TOT2_R :1; + IO_BYTE _TIN3_R :1; + IO_BYTE _TOT3_R :1; + }bit; + }PRRR3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IN0_R :1; + IO_BYTE _IN1_R :1; + IO_BYTE _IN2_R :1; + IO_BYTE _IN3_R :1; + IO_BYTE _IN4_R :1; + IO_BYTE _IN5_R :1; + IO_BYTE _IN6_R :1; + IO_BYTE _IN7_R :1; + }bit; + }PRRR4STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OUT0_R :1; + IO_BYTE _OUT1_R :1; + IO_BYTE _OUT2_R :1; + IO_BYTE _OUT3_R :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _OUT6_R :1; + IO_BYTE _OUT7_R :1; + }bit; + }PRRR5STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SGO0_R :1; + IO_BYTE _SGA0_R :1; + IO_BYTE _FRCK0_R :1; + IO_BYTE _SIN2_R :1; + IO_BYTE _SOT2_R :1; + IO_BYTE _SCK2_R :1; + IO_BYTE _CKOT1_R :1; + IO_BYTE _CKOTX1_R :1; + }bit; + }PRRR6STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ADTG_R :1; + IO_BYTE _NMI_R :1; + IO_BYTE _CS3_R :1; + IO_BYTE _INT3_R1 :1; + IO_BYTE _INT4_R1 :1; + IO_BYTE _INT5_R1 :1; + IO_BYTE _RX2_R :1; + IO_BYTE _TX2_R :1; + }bit; + }PRRR7STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SIN7_R :1; + IO_BYTE _SOT7_R :1; + IO_BYTE _SCK7_R :1; + IO_BYTE _SIN8_R :1; + IO_BYTE _SOT8_R :1; + IO_BYTE _SCK8_R :1; + IO_BYTE _SIN9_R :1; + IO_BYTE _SOT9_R :1; + }bit; + }PRRR8STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SCK9_R :1; + IO_BYTE _SGO1_R :1; + IO_BYTE _SGA1_R :1; + IO_BYTE _FRCK2_R :1; + IO_BYTE _OUT10_R :1; + IO_BYTE _CKOT0_R :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }PRRR9STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }WTBR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D0 :1; + IO_BYTE _D1 :1; + IO_BYTE _D2 :1; + IO_BYTE _D3 :1; + IO_BYTE _D4 :1; + IO_BYTE _D5 :1; + IO_BYTE _D6 :1; + IO_BYTE _D7 :1; + }bit; + }WTBRL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D8 :1; + IO_BYTE _D9 :1; + IO_BYTE _D10 :1; + IO_BYTE _D11 :1; + IO_BYTE _D12 :1; + IO_BYTE _D13 :1; + IO_BYTE _D14 :1; + IO_BYTE _D15 :1; + }bit; + }WTBRH0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D16 :1; + IO_BYTE _D17 :1; + IO_BYTE _D18 :1; + IO_BYTE _D19 :1; + IO_BYTE _D20 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _D1 :5; + }bitc; + }WTBR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _S0 :1; + IO_BYTE _S1 :1; + IO_BYTE _S2 :1; + IO_BYTE _S3 :1; + IO_BYTE _S4 :1; + IO_BYTE _S5 :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _S :6; + }bitc; + }WTSRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _M0 :1; + IO_BYTE _M1 :1; + IO_BYTE _M2 :1; + IO_BYTE _M3 :1; + IO_BYTE _M4 :1; + IO_BYTE _M5 :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _M :6; + }bitc; + }WTMRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _H0 :1; + IO_BYTE _H1 :1; + IO_BYTE _H2 :1; + IO_BYTE _H3 :1; + IO_BYTE _H4 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _H :5; + }bitc; + }WTHRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INT4 :1; + IO_BYTE _INTE4 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }WTCERSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CKSEL0 :1; + IO_BYTE _CKSEL1 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _CKSEL :2; + }bitc; + }WTCKSRSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _ST :1; + IO_WORD _OE :1; + IO_WORD _UPDT :1; + IO_WORD _RUN :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _INT0 :1; + IO_WORD _INTE0 :1; + IO_WORD _INT1 :1; + IO_WORD _INTE1 :1; + IO_WORD _INT2 :1; + IO_WORD _INTE2 :1; + IO_WORD _INT3 :1; + IO_WORD _INTE3 :1; + }bit; + }WTCRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ST :1; + IO_BYTE _OE :1; + IO_BYTE _UPDT :1; + IO_BYTE _RUN :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }WTCRLSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INT0 :1; + IO_BYTE _INTE0 :1; + IO_BYTE _INT1 :1; + IO_BYTE _INTE1 :1; + IO_BYTE _INT2 :1; + IO_BYTE _INTE2 :1; + IO_BYTE _INT3 :1; + IO_BYTE _INTE3 :1; + }bit; + }WTCRHSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INTEN :1; + IO_BYTE _INT :1; + IO_BYTE _CKSEL :1; + IO_BYTE :1; + IO_BYTE _STRT :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _RESV :1; + }bit; + }CUCRSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _TDD0 :1; + IO_WORD _TDD1 :1; + IO_WORD _TDD2 :1; + IO_WORD _TDD3 :1; + IO_WORD _TDD4 :1; + IO_WORD _TDD5 :1; + IO_WORD _TDD6 :1; + IO_WORD _TDD7 :1; + IO_WORD _TDD8 :1; + IO_WORD _TDD9 :1; + IO_WORD _TDD10 :1; + IO_WORD _TDD11 :1; + IO_WORD _TDD12 :1; + IO_WORD _TDD13 :1; + IO_WORD _TDD14 :1; + IO_WORD _TDD15 :1; + }bit; + struct{ + IO_WORD _TDD :16; + }bitc; + }CUTDSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TDD0 :1; + IO_BYTE _TDD1 :1; + IO_BYTE _TDD2 :1; + IO_BYTE _TDD3 :1; + IO_BYTE _TDD4 :1; + IO_BYTE _TDD5 :1; + IO_BYTE _TDD6 :1; + IO_BYTE _TDD7 :1; + }bit; + }CUTDLSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TDD8 :1; + IO_BYTE _TDD9 :1; + IO_BYTE _TDD10 :1; + IO_BYTE _TDD11 :1; + IO_BYTE _TDD12 :1; + IO_BYTE _TDD13 :1; + IO_BYTE _TDD14 :1; + IO_BYTE _TDD15 :1; + }bit; + }CUTDHSTR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _TDR0 :1; + IO_LWORD _TDR1 :1; + IO_LWORD _TDR2 :1; + IO_LWORD _TDR3 :1; + IO_LWORD _TDR4 :1; + IO_LWORD _TDR5 :1; + IO_LWORD _TDR6 :1; + IO_LWORD _TDR7 :1; + IO_LWORD _TDR8 :1; + IO_LWORD _TDR9 :1; + IO_LWORD _TDR10 :1; + IO_LWORD _TDR11 :1; + IO_LWORD _TDR12 :1; + IO_LWORD _TDR13 :1; + IO_LWORD _TDR14 :1; + IO_LWORD _TDR15 :1; + IO_LWORD _TDR16 :1; + IO_LWORD _TDR17 :1; + IO_LWORD _TDR18 :1; + IO_LWORD _TDR19 :1; + IO_LWORD _TDR20 :1; + IO_LWORD _TDR21 :1; + IO_LWORD _TDR22 :1; + IO_LWORD _TDR23 :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + }bit; + }CUTRSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _TDR0 :1; + IO_WORD _TDR1 :1; + IO_WORD _TDR2 :1; + IO_WORD _TDR3 :1; + IO_WORD _TDR4 :1; + IO_WORD _TDR5 :1; + IO_WORD _TDR6 :1; + IO_WORD _TDR7 :1; + IO_WORD _TDR8 :1; + IO_WORD _TDR9 :1; + IO_WORD _TDR10 :1; + IO_WORD _TDR11 :1; + IO_WORD _TDR12 :1; + IO_WORD _TDR13 :1; + IO_WORD _TDR14 :1; + IO_WORD _TDR15 :1; + }bit; + }CUTR2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TDR0 :1; + IO_BYTE _TDR1 :1; + IO_BYTE _TDR2 :1; + IO_BYTE _TDR3 :1; + IO_BYTE _TDR4 :1; + IO_BYTE _TDR5 :1; + IO_BYTE _TDR6 :1; + IO_BYTE _TDR7 :1; + }bit; + }CUTR2LSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TDR8 :1; + IO_BYTE _TDR9 :1; + IO_BYTE _TDR10 :1; + IO_BYTE _TDR11 :1; + IO_BYTE _TDR12 :1; + IO_BYTE _TDR13 :1; + IO_BYTE _TDR14 :1; + IO_BYTE _TDR15 :1; + }bit; + }CUTR2HSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _TDR16 :1; + IO_WORD _TDR17 :1; + IO_WORD _TDR18 :1; + IO_WORD _TDR19 :1; + IO_WORD _TDR20 :1; + IO_WORD _TDR21 :1; + IO_WORD _TDR22 :1; + IO_WORD _TDR23 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }CUTR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TDR16 :1; + IO_BYTE _TDR17 :1; + IO_BYTE _TDR18 :1; + IO_BYTE _TDR19 :1; + IO_BYTE _TDR20 :1; + IO_BYTE _TDR21 :1; + IO_BYTE _TDR22 :1; + IO_BYTE _TDR23 :1; + }bit; + }CUTR1LSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }CUTR1HSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TMIS0 :1; + IO_BYTE _TMIS1 :1; + IO_BYTE _TMIS2 :1; + IO_BYTE _TMIS3 :1; + IO_BYTE _TMIS4 :1; + IO_BYTE _TMIS5 :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }TMISRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SOE :1; + IO_BYTE _SCKE :1; + IO_BYTE _UPCL :1; + IO_BYTE _REST :1; + IO_BYTE _EXT :1; + IO_BYTE _OTO :1; + IO_BYTE _MD0 :1; + IO_BYTE _MD1 :1; + }bit; + struct{ + IO_BYTE :6; + IO_BYTE _MD :2; + }bitc; + }SMR7STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TXE :1; + IO_BYTE _RXE :1; + IO_BYTE _CRE :1; + IO_BYTE _AD :1; + IO_BYTE _CL :1; + IO_BYTE _SBL :1; + IO_BYTE _P :1; + IO_BYTE _PEN :1; + }bit; + }SCR7STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TIE :1; + IO_BYTE _RIE :1; + IO_BYTE _BDS :1; + IO_BYTE _TDRE :1; + IO_BYTE _RDRF :1; + IO_BYTE _FRE :1; + IO_BYTE _ORE :1; + IO_BYTE _PE :1; + }bit; + }SSR7STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TBI :1; + IO_BYTE _RBI :1; + IO_BYTE _BIE :1; + IO_BYTE _SSM :1; + IO_BYTE _SCDE :1; + IO_BYTE _MS :1; + IO_BYTE _LBR :1; + IO_BYTE _INV :1; + }bit; + }ECCR7STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SCES :1; + IO_BYTE _CCO :1; + IO_BYTE _SIOP :1; + IO_BYTE _SOPE :1; + IO_BYTE _LBL0 :1; + IO_BYTE _LBL1 :1; + IO_BYTE _LBD :1; + IO_BYTE _LBIE :1; + }bit; + struct{ + IO_BYTE :4; + IO_BYTE _LBL :2; + }bitc; + }ESCR7STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _BGR0 :1; + IO_WORD _BGR1 :1; + IO_WORD _BGR2 :1; + IO_WORD _BGR3 :1; + IO_WORD _BGR4 :1; + IO_WORD _BGR5 :1; + IO_WORD _BGR6 :1; + IO_WORD _BGR7 :1; + IO_WORD _BGR8 :1; + IO_WORD _BGR9 :1; + IO_WORD _BGR10 :1; + IO_WORD _BGR11 :1; + IO_WORD _BGR12 :1; + IO_WORD _BGR13 :1; + IO_WORD _BGR14 :1; + IO_WORD _BGR15 :1; + }bit; + struct{ + IO_WORD _BGR :16; + }bitc; + }BGR7STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _BGR0 :1; + IO_BYTE _BGR1 :1; + IO_BYTE _BGR2 :1; + IO_BYTE _BGR3 :1; + IO_BYTE _BGR4 :1; + IO_BYTE _BGR5 :1; + IO_BYTE _BGR6 :1; + IO_BYTE _BGR7 :1; + }bit; + }BGRL7STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _BGR8 :1; + IO_BYTE _BGR9 :1; + IO_BYTE _BGR10 :1; + IO_BYTE _BGR11 :1; + IO_BYTE _BGR12 :1; + IO_BYTE _BGR13 :1; + IO_BYTE _BGR14 :1; + IO_BYTE _BGR15 :1; + }bit; + }BGRH7STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _AICD :1; + IO_BYTE _RBI :1; + IO_BYTE _RDRF :1; + IO_BYTE _TDRE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }ESIR7STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SOE :1; + IO_BYTE _SCKE :1; + IO_BYTE _UPCL :1; + IO_BYTE _REST :1; + IO_BYTE _EXT :1; + IO_BYTE _OTO :1; + IO_BYTE _MD0 :1; + IO_BYTE _MD1 :1; + }bit; + struct{ + IO_BYTE :6; + IO_BYTE _MD :2; + }bitc; + }SMR8STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TXE :1; + IO_BYTE _RXE :1; + IO_BYTE _CRE :1; + IO_BYTE _AD :1; + IO_BYTE _CL :1; + IO_BYTE _SBL :1; + IO_BYTE _P :1; + IO_BYTE _PEN :1; + }bit; + }SCR8STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TIE :1; + IO_BYTE _RIE :1; + IO_BYTE _BDS :1; + IO_BYTE _TDRE :1; + IO_BYTE _RDRF :1; + IO_BYTE _FRE :1; + IO_BYTE _ORE :1; + IO_BYTE _PE :1; + }bit; + }SSR8STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TBI :1; + IO_BYTE _RBI :1; + IO_BYTE _BIE :1; + IO_BYTE _SSM :1; + IO_BYTE _SCDE :1; + IO_BYTE _MS :1; + IO_BYTE _LBR :1; + IO_BYTE _INV :1; + }bit; + }ECCR8STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SCES :1; + IO_BYTE _CCO :1; + IO_BYTE _SIOP :1; + IO_BYTE _SOPE :1; + IO_BYTE _LBL0 :1; + IO_BYTE _LBL1 :1; + IO_BYTE _LBD :1; + IO_BYTE _LBIE :1; + }bit; + struct{ + IO_BYTE :4; + IO_BYTE _LBL :2; + }bitc; + }ESCR8STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _BGR0 :1; + IO_WORD _BGR1 :1; + IO_WORD _BGR2 :1; + IO_WORD _BGR3 :1; + IO_WORD _BGR4 :1; + IO_WORD _BGR5 :1; + IO_WORD _BGR6 :1; + IO_WORD _BGR7 :1; + IO_WORD _BGR8 :1; + IO_WORD _BGR9 :1; + IO_WORD _BGR10 :1; + IO_WORD _BGR11 :1; + IO_WORD _BGR12 :1; + IO_WORD _BGR13 :1; + IO_WORD _BGR14 :1; + IO_WORD _BGR15 :1; + }bit; + struct{ + IO_WORD _BGR :16; + }bitc; + }BGR8STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _BGR0 :1; + IO_BYTE _BGR1 :1; + IO_BYTE _BGR2 :1; + IO_BYTE _BGR3 :1; + IO_BYTE _BGR4 :1; + IO_BYTE _BGR5 :1; + IO_BYTE _BGR6 :1; + IO_BYTE _BGR7 :1; + }bit; + }BGRL8STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _BGR8 :1; + IO_BYTE _BGR9 :1; + IO_BYTE _BGR10 :1; + IO_BYTE _BGR11 :1; + IO_BYTE _BGR12 :1; + IO_BYTE _BGR13 :1; + IO_BYTE _BGR14 :1; + IO_BYTE _BGR15 :1; + }bit; + }BGRH8STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _AICD :1; + IO_BYTE _RBI :1; + IO_BYTE _RDRF :1; + IO_BYTE _TDRE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }ESIR8STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SOE :1; + IO_BYTE _SCKE :1; + IO_BYTE _UPCL :1; + IO_BYTE _REST :1; + IO_BYTE _EXT :1; + IO_BYTE _OTO :1; + IO_BYTE _MD0 :1; + IO_BYTE _MD1 :1; + }bit; + struct{ + IO_BYTE :6; + IO_BYTE _MD :2; + }bitc; + }SMR9STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TXE :1; + IO_BYTE _RXE :1; + IO_BYTE _CRE :1; + IO_BYTE _AD :1; + IO_BYTE _CL :1; + IO_BYTE _SBL :1; + IO_BYTE _P :1; + IO_BYTE _PEN :1; + }bit; + }SCR9STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TIE :1; + IO_BYTE _RIE :1; + IO_BYTE _BDS :1; + IO_BYTE _TDRE :1; + IO_BYTE _RDRF :1; + IO_BYTE _FRE :1; + IO_BYTE _ORE :1; + IO_BYTE _PE :1; + }bit; + }SSR9STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TBI :1; + IO_BYTE _RBI :1; + IO_BYTE _BIE :1; + IO_BYTE _SSM :1; + IO_BYTE _SCDE :1; + IO_BYTE _MS :1; + IO_BYTE _LBR :1; + IO_BYTE _INV :1; + }bit; + }ECCR9STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SCES :1; + IO_BYTE _CCO :1; + IO_BYTE _SIOP :1; + IO_BYTE _SOPE :1; + IO_BYTE _LBL0 :1; + IO_BYTE _LBL1 :1; + IO_BYTE _LBD :1; + IO_BYTE _LBIE :1; + }bit; + struct{ + IO_BYTE :4; + IO_BYTE _LBL :2; + }bitc; + }ESCR9STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _BGR0 :1; + IO_WORD _BGR1 :1; + IO_WORD _BGR2 :1; + IO_WORD _BGR3 :1; + IO_WORD _BGR4 :1; + IO_WORD _BGR5 :1; + IO_WORD _BGR6 :1; + IO_WORD _BGR7 :1; + IO_WORD _BGR8 :1; + IO_WORD _BGR9 :1; + IO_WORD _BGR10 :1; + IO_WORD _BGR11 :1; + IO_WORD _BGR12 :1; + IO_WORD _BGR13 :1; + IO_WORD _BGR14 :1; + IO_WORD _BGR15 :1; + }bit; + struct{ + IO_WORD _BGR :16; + }bitc; + }BGR9STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _BGR0 :1; + IO_BYTE _BGR1 :1; + IO_BYTE _BGR2 :1; + IO_BYTE _BGR3 :1; + IO_BYTE _BGR4 :1; + IO_BYTE _BGR5 :1; + IO_BYTE _BGR6 :1; + IO_BYTE _BGR7 :1; + }bit; + }BGRL9STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _BGR8 :1; + IO_BYTE _BGR9 :1; + IO_BYTE _BGR10 :1; + IO_BYTE _BGR11 :1; + IO_BYTE _BGR12 :1; + IO_BYTE _BGR13 :1; + IO_BYTE _BGR14 :1; + IO_BYTE _BGR15 :1; + }bit; + }BGRH9STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _AICD :1; + IO_BYTE _RBI :1; + IO_BYTE _RDRF :1; + IO_BYTE _TDRE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }ESIR9STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PD :1; + IO_BYTE _IEN :1; + IO_BYTE _IRQ :1; + IO_BYTE _OUT1 :1; + IO_BYTE _OUT2 :1; + IO_BYTE _UVEN :1; + IO_BYTE _OVEN :1; + IO_BYTE _CMD :1; + }bit; + }ACSR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INTREF :1; + IO_BYTE :1; + IO_BYTE _ACE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }AECSR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PD :1; + IO_BYTE _IEN :1; + IO_BYTE _IRQ :1; + IO_BYTE _OUT1 :1; + IO_BYTE _OUT2 :1; + IO_BYTE _UVEN :1; + IO_BYTE _OVEN :1; + IO_BYTE _CMD :1; + }bit; + }ACSR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INTREF :1; + IO_BYTE :1; + IO_BYTE _ACE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }AECSR1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PTMR6STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PCSR6STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PDUT6STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _OSEL :1; + IO_WORD _OE :1; + IO_WORD _IRS0 :1; + IO_WORD _IRS1 :1; + IO_WORD _IRQF :1; + IO_WORD _IREN :1; + IO_WORD _EGS0 :1; + IO_WORD _EGS1 :1; + IO_WORD :1; + IO_WORD _PGMS :1; + IO_WORD _CKS0 :1; + IO_WORD _CKS1 :1; + IO_WORD _RTRG :1; + IO_WORD _MDSE :1; + IO_WORD _STGR :1; + IO_WORD _CNTE :1; + }bit; + struct{ + IO_WORD :2; + IO_WORD _IRS :2; + IO_WORD :2; + IO_WORD _EGS :2; + IO_WORD :2; + IO_WORD _CKS :2; + }bitc; + }PCN6STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OSEL :1; + IO_BYTE _OE :1; + IO_BYTE _IRS0 :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRQF :1; + IO_BYTE _IREN :1; + IO_BYTE _EGS0 :1; + IO_BYTE _EGS1 :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _IRS :2; + IO_BYTE :2; + IO_BYTE _EGS :2; + }bitc; + }PCNL6STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _PGMS :1; + IO_BYTE _CKS0 :1; + IO_BYTE _CKS1 :1; + IO_BYTE _RTRG :1; + IO_BYTE _MDSE :1; + IO_BYTE _STGR :1; + IO_BYTE _CNTE :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _CKS :2; + }bitc; + }PCNH6STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PTMR7STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PCSR7STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PDUT7STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _OSEL :1; + IO_WORD _OE :1; + IO_WORD _IRS0 :1; + IO_WORD _IRS1 :1; + IO_WORD _IRQF :1; + IO_WORD _IREN :1; + IO_WORD _EGS0 :1; + IO_WORD _EGS1 :1; + IO_WORD :1; + IO_WORD _PGMS :1; + IO_WORD _CKS0 :1; + IO_WORD _CKS1 :1; + IO_WORD _RTRG :1; + IO_WORD _MDSE :1; + IO_WORD _STGR :1; + IO_WORD _CNTE :1; + }bit; + struct{ + IO_WORD :2; + IO_WORD _IRS :2; + IO_WORD :2; + IO_WORD _EGS :2; + IO_WORD :2; + IO_WORD _CKS :2; + }bitc; + }PCN7STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OSEL :1; + IO_BYTE _OE :1; + IO_BYTE _IRS0 :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRQF :1; + IO_BYTE _IREN :1; + IO_BYTE _EGS0 :1; + IO_BYTE _EGS1 :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _IRS :2; + IO_BYTE :2; + IO_BYTE _EGS :2; + }bitc; + }PCNL7STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _PGMS :1; + IO_BYTE _CKS0 :1; + IO_BYTE _CKS1 :1; + IO_BYTE _RTRG :1; + IO_BYTE _MDSE :1; + IO_BYTE _STGR :1; + IO_BYTE _CNTE :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _CKS :2; + }bitc; + }PCNH7STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _TSEL00 :1; + IO_WORD _TSEL01 :1; + IO_WORD _TSEL02 :1; + IO_WORD _TSEL03 :1; + IO_WORD _TSEL10 :1; + IO_WORD _TSEL11 :1; + IO_WORD _TSEL12 :1; + IO_WORD _TSEL13 :1; + IO_WORD _TSEL20 :1; + IO_WORD _TSEL21 :1; + IO_WORD _TSEL22 :1; + IO_WORD _TSEL23 :1; + IO_WORD _TSEL30 :1; + IO_WORD _TSEL31 :1; + IO_WORD _TSEL32 :1; + IO_WORD _TSEL33 :1; + }bit; + struct{ + IO_WORD _TSEL0 :4; + IO_WORD _TSEL1 :4; + IO_WORD _TSEL2 :4; + IO_WORD _TSEL3 :4; + }bitc; + }GCN12STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TSEL00 :1; + IO_BYTE _TSEL01 :1; + IO_BYTE _TSEL02 :1; + IO_BYTE _TSEL03 :1; + IO_BYTE _TSEL10 :1; + IO_BYTE _TSEL11 :1; + IO_BYTE _TSEL12 :1; + IO_BYTE _TSEL13 :1; + }bit; + struct{ + IO_BYTE _TSEL0 :4; + IO_BYTE _TSEL1 :4; + }bitc; + }GCN1L2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TSEL20 :1; + IO_BYTE _TSEL21 :1; + IO_BYTE _TSEL22 :1; + IO_BYTE _TSEL23 :1; + IO_BYTE _TSEL30 :1; + IO_BYTE _TSEL31 :1; + IO_BYTE _TSEL32 :1; + IO_BYTE _TSEL33 :1; + }bit; + struct{ + IO_BYTE _TSEL2 :4; + IO_BYTE _TSEL3 :4; + }bitc; + }GCN1H2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _EN0 :1; + IO_WORD _EN1 :1; + IO_WORD _EN2 :1; + IO_WORD _EN3 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CKSEL0 :1; + IO_WORD _CKSEL1 :1; + IO_WORD _CKSEL2 :1; + IO_WORD _CKSEL3 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD _EN :4; + IO_WORD :4; + IO_WORD _CKSEL :4; + }bitc; + }GCN22STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EN0 :1; + IO_BYTE _EN1 :1; + IO_BYTE _EN2 :1; + IO_BYTE _EN3 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _EN :4; + }bitc; + }GCN2L2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CKSEL0 :1; + IO_BYTE _CKSEL1 :1; + IO_BYTE _CKSEL2 :1; + IO_BYTE _CKSEL3 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _CKSEL :4; + }bitc; + }GCN2H2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PTMR8STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PCSR8STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PDUT8STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _OSEL :1; + IO_WORD _OE :1; + IO_WORD _IRS0 :1; + IO_WORD _IRS1 :1; + IO_WORD _IRQF :1; + IO_WORD _IREN :1; + IO_WORD _EGS0 :1; + IO_WORD _EGS1 :1; + IO_WORD :1; + IO_WORD _PGMS :1; + IO_WORD _CKS0 :1; + IO_WORD _CKS1 :1; + IO_WORD _RTRG :1; + IO_WORD _MDSE :1; + IO_WORD _STGR :1; + IO_WORD _CNTE :1; + }bit; + struct{ + IO_WORD :2; + IO_WORD _IRS :2; + IO_WORD :2; + IO_WORD _EGS :2; + IO_WORD :2; + IO_WORD _CKS :2; + }bitc; + }PCN8STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OSEL :1; + IO_BYTE _OE :1; + IO_BYTE _IRS0 :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRQF :1; + IO_BYTE _IREN :1; + IO_BYTE _EGS0 :1; + IO_BYTE _EGS1 :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _IRS :2; + IO_BYTE :2; + IO_BYTE _EGS :2; + }bitc; + }PCNL8STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _PGMS :1; + IO_BYTE _CKS0 :1; + IO_BYTE _CKS1 :1; + IO_BYTE _RTRG :1; + IO_BYTE _MDSE :1; + IO_BYTE _STGR :1; + IO_BYTE _CNTE :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _CKS :2; + }bitc; + }PCNH8STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PTMR9STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PCSR9STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PDUT9STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _OSEL :1; + IO_WORD _OE :1; + IO_WORD _IRS0 :1; + IO_WORD _IRS1 :1; + IO_WORD _IRQF :1; + IO_WORD _IREN :1; + IO_WORD _EGS0 :1; + IO_WORD _EGS1 :1; + IO_WORD :1; + IO_WORD _PGMS :1; + IO_WORD _CKS0 :1; + IO_WORD _CKS1 :1; + IO_WORD _RTRG :1; + IO_WORD _MDSE :1; + IO_WORD _STGR :1; + IO_WORD _CNTE :1; + }bit; + struct{ + IO_WORD :2; + IO_WORD _IRS :2; + IO_WORD :2; + IO_WORD _EGS :2; + IO_WORD :2; + IO_WORD _CKS :2; + }bitc; + }PCN9STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OSEL :1; + IO_BYTE _OE :1; + IO_BYTE _IRS0 :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRQF :1; + IO_BYTE _IREN :1; + IO_BYTE _EGS0 :1; + IO_BYTE _EGS1 :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _IRS :2; + IO_BYTE :2; + IO_BYTE _EGS :2; + }bitc; + }PCNL9STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _PGMS :1; + IO_BYTE _CKS0 :1; + IO_BYTE _CKS1 :1; + IO_BYTE _RTRG :1; + IO_BYTE _MDSE :1; + IO_BYTE _STGR :1; + IO_BYTE _CNTE :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _CKS :2; + }bitc; + }PCNH9STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PTMR10STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PCSR10STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PDUT10STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _OSEL :1; + IO_WORD _OE :1; + IO_WORD _IRS0 :1; + IO_WORD _IRS1 :1; + IO_WORD _IRQF :1; + IO_WORD _IREN :1; + IO_WORD _EGS0 :1; + IO_WORD _EGS1 :1; + IO_WORD :1; + IO_WORD _PGMS :1; + IO_WORD _CKS0 :1; + IO_WORD _CKS1 :1; + IO_WORD _RTRG :1; + IO_WORD _MDSE :1; + IO_WORD _STGR :1; + IO_WORD _CNTE :1; + }bit; + struct{ + IO_WORD :2; + IO_WORD _IRS :2; + IO_WORD :2; + IO_WORD _EGS :2; + IO_WORD :2; + IO_WORD _CKS :2; + }bitc; + }PCN10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OSEL :1; + IO_BYTE _OE :1; + IO_BYTE _IRS0 :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRQF :1; + IO_BYTE _IREN :1; + IO_BYTE _EGS0 :1; + IO_BYTE _EGS1 :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _IRS :2; + IO_BYTE :2; + IO_BYTE _EGS :2; + }bitc; + }PCNL10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _PGMS :1; + IO_BYTE _CKS0 :1; + IO_BYTE _CKS1 :1; + IO_BYTE _RTRG :1; + IO_BYTE _MDSE :1; + IO_BYTE _STGR :1; + IO_BYTE _CNTE :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _CKS :2; + }bitc; + }PCNH10STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PTMR11STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PCSR11STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PDUT11STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _OSEL :1; + IO_WORD _OE :1; + IO_WORD _IRS0 :1; + IO_WORD _IRS1 :1; + IO_WORD _IRQF :1; + IO_WORD _IREN :1; + IO_WORD _EGS0 :1; + IO_WORD _EGS1 :1; + IO_WORD :1; + IO_WORD _PGMS :1; + IO_WORD _CKS0 :1; + IO_WORD _CKS1 :1; + IO_WORD _RTRG :1; + IO_WORD _MDSE :1; + IO_WORD _STGR :1; + IO_WORD _CNTE :1; + }bit; + struct{ + IO_WORD :2; + IO_WORD _IRS :2; + IO_WORD :2; + IO_WORD _EGS :2; + IO_WORD :2; + IO_WORD _CKS :2; + }bitc; + }PCN11STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OSEL :1; + IO_BYTE _OE :1; + IO_BYTE _IRS0 :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRQF :1; + IO_BYTE _IREN :1; + IO_BYTE _EGS0 :1; + IO_BYTE _EGS1 :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _IRS :2; + IO_BYTE :2; + IO_BYTE _EGS :2; + }bitc; + }PCNL11STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _PGMS :1; + IO_BYTE _CKS0 :1; + IO_BYTE _CKS1 :1; + IO_BYTE _RTRG :1; + IO_BYTE _MDSE :1; + IO_BYTE _STGR :1; + IO_BYTE _CNTE :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _CKS :2; + }bitc; + }PCNH11STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _TSEL00 :1; + IO_WORD _TSEL01 :1; + IO_WORD _TSEL02 :1; + IO_WORD _TSEL03 :1; + IO_WORD _TSEL10 :1; + IO_WORD _TSEL11 :1; + IO_WORD _TSEL12 :1; + IO_WORD _TSEL13 :1; + IO_WORD _TSEL20 :1; + IO_WORD _TSEL21 :1; + IO_WORD _TSEL22 :1; + IO_WORD _TSEL23 :1; + IO_WORD _TSEL30 :1; + IO_WORD _TSEL31 :1; + IO_WORD _TSEL32 :1; + IO_WORD _TSEL33 :1; + }bit; + struct{ + IO_WORD _TSEL0 :4; + IO_WORD _TSEL1 :4; + IO_WORD _TSEL2 :4; + IO_WORD _TSEL3 :4; + }bitc; + }GCN13STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TSEL00 :1; + IO_BYTE _TSEL01 :1; + IO_BYTE _TSEL02 :1; + IO_BYTE _TSEL03 :1; + IO_BYTE _TSEL10 :1; + IO_BYTE _TSEL11 :1; + IO_BYTE _TSEL12 :1; + IO_BYTE _TSEL13 :1; + }bit; + struct{ + IO_BYTE _TSEL0 :4; + IO_BYTE _TSEL1 :4; + }bitc; + }GCN1L3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TSEL20 :1; + IO_BYTE _TSEL21 :1; + IO_BYTE _TSEL22 :1; + IO_BYTE _TSEL23 :1; + IO_BYTE _TSEL30 :1; + IO_BYTE _TSEL31 :1; + IO_BYTE _TSEL32 :1; + IO_BYTE _TSEL33 :1; + }bit; + struct{ + IO_BYTE _TSEL2 :4; + IO_BYTE _TSEL3 :4; + }bitc; + }GCN1H3STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _EN0 :1; + IO_WORD _EN1 :1; + IO_WORD _EN2 :1; + IO_WORD _EN3 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CKSEL0 :1; + IO_WORD _CKSEL1 :1; + IO_WORD _CKSEL2 :1; + IO_WORD _CKSEL3 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD _EN :4; + IO_WORD :4; + IO_WORD _CKSEL :4; + }bitc; + }GCN23STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EN0 :1; + IO_BYTE _EN1 :1; + IO_BYTE _EN2 :1; + IO_BYTE _EN3 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _EN :4; + }bitc; + }GCN2L3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CKSEL0 :1; + IO_BYTE _CKSEL1 :1; + IO_BYTE _CKSEL2 :1; + IO_BYTE _CKSEL3 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _CKSEL :4; + }bitc; + }GCN2H3STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PTMR12STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PCSR12STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PDUT12STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _OSEL :1; + IO_WORD _OE :1; + IO_WORD _IRS0 :1; + IO_WORD _IRS1 :1; + IO_WORD _IRQF :1; + IO_WORD _IREN :1; + IO_WORD _EGS0 :1; + IO_WORD _EGS1 :1; + IO_WORD :1; + IO_WORD _PGMS :1; + IO_WORD _CKS0 :1; + IO_WORD _CKS1 :1; + IO_WORD _RTRG :1; + IO_WORD _MDSE :1; + IO_WORD _STGR :1; + IO_WORD _CNTE :1; + }bit; + struct{ + IO_WORD :2; + IO_WORD _IRS :2; + IO_WORD :2; + IO_WORD _EGS :2; + IO_WORD :2; + IO_WORD _CKS :2; + }bitc; + }PCN12STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OSEL :1; + IO_BYTE _OE :1; + IO_BYTE _IRS0 :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRQF :1; + IO_BYTE _IREN :1; + IO_BYTE _EGS0 :1; + IO_BYTE _EGS1 :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _IRS :2; + IO_BYTE :2; + IO_BYTE _EGS :2; + }bitc; + }PCNL12STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _PGMS :1; + IO_BYTE _CKS0 :1; + IO_BYTE _CKS1 :1; + IO_BYTE _RTRG :1; + IO_BYTE _MDSE :1; + IO_BYTE _STGR :1; + IO_BYTE _CNTE :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _CKS :2; + }bitc; + }PCNH12STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PTMR13STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PCSR13STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PDUT13STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _OSEL :1; + IO_WORD _OE :1; + IO_WORD _IRS0 :1; + IO_WORD _IRS1 :1; + IO_WORD _IRQF :1; + IO_WORD _IREN :1; + IO_WORD _EGS0 :1; + IO_WORD _EGS1 :1; + IO_WORD :1; + IO_WORD _PGMS :1; + IO_WORD _CKS0 :1; + IO_WORD _CKS1 :1; + IO_WORD _RTRG :1; + IO_WORD _MDSE :1; + IO_WORD _STGR :1; + IO_WORD _CNTE :1; + }bit; + struct{ + IO_WORD :2; + IO_WORD _IRS :2; + IO_WORD :2; + IO_WORD _EGS :2; + IO_WORD :2; + IO_WORD _CKS :2; + }bitc; + }PCN13STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OSEL :1; + IO_BYTE _OE :1; + IO_BYTE _IRS0 :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRQF :1; + IO_BYTE _IREN :1; + IO_BYTE _EGS0 :1; + IO_BYTE _EGS1 :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _IRS :2; + IO_BYTE :2; + IO_BYTE _EGS :2; + }bitc; + }PCNL13STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _PGMS :1; + IO_BYTE _CKS0 :1; + IO_BYTE _CKS1 :1; + IO_BYTE _RTRG :1; + IO_BYTE _MDSE :1; + IO_BYTE _STGR :1; + IO_BYTE _CNTE :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _CKS :2; + }bitc; + }PCNH13STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PTMR14STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PCSR14STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PDUT14STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _OSEL :1; + IO_WORD _OE :1; + IO_WORD _IRS0 :1; + IO_WORD _IRS1 :1; + IO_WORD _IRQF :1; + IO_WORD _IREN :1; + IO_WORD _EGS0 :1; + IO_WORD _EGS1 :1; + IO_WORD :1; + IO_WORD _PGMS :1; + IO_WORD _CKS0 :1; + IO_WORD _CKS1 :1; + IO_WORD _RTRG :1; + IO_WORD _MDSE :1; + IO_WORD _STGR :1; + IO_WORD _CNTE :1; + }bit; + struct{ + IO_WORD :2; + IO_WORD _IRS :2; + IO_WORD :2; + IO_WORD _EGS :2; + IO_WORD :2; + IO_WORD _CKS :2; + }bitc; + }PCN14STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OSEL :1; + IO_BYTE _OE :1; + IO_BYTE _IRS0 :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRQF :1; + IO_BYTE _IREN :1; + IO_BYTE _EGS0 :1; + IO_BYTE _EGS1 :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _IRS :2; + IO_BYTE :2; + IO_BYTE _EGS :2; + }bitc; + }PCNL14STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _PGMS :1; + IO_BYTE _CKS0 :1; + IO_BYTE _CKS1 :1; + IO_BYTE _RTRG :1; + IO_BYTE _MDSE :1; + IO_BYTE _STGR :1; + IO_BYTE _CNTE :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _CKS :2; + }bitc; + }PCNH14STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PTMR15STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PCSR15STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PDUT15STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _OSEL :1; + IO_WORD _OE :1; + IO_WORD _IRS0 :1; + IO_WORD _IRS1 :1; + IO_WORD _IRQF :1; + IO_WORD _IREN :1; + IO_WORD _EGS0 :1; + IO_WORD _EGS1 :1; + IO_WORD :1; + IO_WORD _PGMS :1; + IO_WORD _CKS0 :1; + IO_WORD _CKS1 :1; + IO_WORD _RTRG :1; + IO_WORD _MDSE :1; + IO_WORD _STGR :1; + IO_WORD _CNTE :1; + }bit; + struct{ + IO_WORD :2; + IO_WORD _IRS :2; + IO_WORD :2; + IO_WORD _EGS :2; + IO_WORD :2; + IO_WORD _CKS :2; + }bitc; + }PCN15STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OSEL :1; + IO_BYTE _OE :1; + IO_BYTE _IRS0 :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRQF :1; + IO_BYTE _IREN :1; + IO_BYTE _EGS0 :1; + IO_BYTE _EGS1 :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _IRS :2; + IO_BYTE :2; + IO_BYTE _EGS :2; + }bitc; + }PCNL15STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _PGMS :1; + IO_BYTE _CKS0 :1; + IO_BYTE _CKS1 :1; + IO_BYTE _RTRG :1; + IO_BYTE _MDSE :1; + IO_BYTE _STGR :1; + IO_BYTE _CNTE :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _CKS :2; + }bitc; + }PCNH15STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PPG8_R :1; + IO_BYTE _PPG9_R :1; + IO_BYTE _PPG10_R :1; + IO_BYTE _PPG11_R :1; + IO_BYTE _TTG8_R :1; + IO_BYTE _TTG9_R :1; + IO_BYTE _TTG10_R :1; + IO_BYTE _TTG11_R :1; + }bit; + }PRRR10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PPG16_R :1; + IO_BYTE _PPG17_R :1; + IO_BYTE _PPG18_R :1; + IO_BYTE _PPG19_R :1; + IO_BYTE _TTG16_R :1; + IO_BYTE _TTG17_R :1; + IO_BYTE _TTG18_R :1; + IO_BYTE _TTG19_R :1; + }bit; + }PRRR11STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CS0_R :1; + IO_BYTE _CS1_R :1; + IO_BYTE _CS2_R :1; + IO_BYTE _CS4_R :1; + IO_BYTE _CS5_R :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }PRRR12STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }PRRR13STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _R0 :1; + IO_WORD _R1 :1; + IO_WORD _R2 :1; + IO_WORD _ACE :1; + IO_WORD _STS :1; + IO_WORD _WSF :1; + IO_WORD _ES :1; + IO_WORD _BW :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CSE :1; + IO_WORD _CSL :1; + IO_WORD _ATL :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD _R :3; + }bitc; + }EAC0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _R0 :1; + IO_BYTE _R1 :1; + IO_BYTE _R2 :1; + IO_BYTE _ACE :1; + IO_BYTE _STS :1; + IO_BYTE _WSF :1; + IO_BYTE _ES :1; + IO_BYTE _BW :1; + }bit; + struct{ + IO_BYTE _R :3; + }bitc; + }EACL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CSE :1; + IO_BYTE _CSL :1; + IO_BYTE _ATL :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }EACH0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _R0 :1; + IO_WORD _R1 :1; + IO_WORD _R2 :1; + IO_WORD _ACE :1; + IO_WORD _STS :1; + IO_WORD _WSF :1; + IO_WORD _ES :1; + IO_WORD _BW :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CSE :1; + IO_WORD _CSL :1; + IO_WORD _ATL :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD _R :3; + }bitc; + }EAC1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _R0 :1; + IO_BYTE _R1 :1; + IO_BYTE _R2 :1; + IO_BYTE _ACE :1; + IO_BYTE _STS :1; + IO_BYTE _WSF :1; + IO_BYTE _ES :1; + IO_BYTE _BW :1; + }bit; + struct{ + IO_BYTE _R :3; + }bitc; + }EACL1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CSE :1; + IO_BYTE _CSL :1; + IO_BYTE _ATL :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }EACH1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _R0 :1; + IO_WORD _R1 :1; + IO_WORD _R2 :1; + IO_WORD _ACE :1; + IO_WORD _STS :1; + IO_WORD _WSF :1; + IO_WORD _ES :1; + IO_WORD _BW :1; + IO_WORD _EASZ0 :1; + IO_WORD _EASZ1 :1; + IO_WORD _EASZ2 :1; + IO_WORD _CSE :1; + IO_WORD _CSL :1; + IO_WORD _ATL :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD _R :3; + IO_WORD :5; + IO_WORD _EASZ :3; + }bitc; + }EAC2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _R0 :1; + IO_BYTE _R1 :1; + IO_BYTE _R2 :1; + IO_BYTE _ACE :1; + IO_BYTE _STS :1; + IO_BYTE _WSF :1; + IO_BYTE _ES :1; + IO_BYTE _BW :1; + }bit; + struct{ + IO_BYTE _R :3; + }bitc; + }EACL2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EASZ0 :1; + IO_BYTE _EASZ1 :1; + IO_BYTE _EASZ2 :1; + IO_BYTE _CSE :1; + IO_BYTE _CSL :1; + IO_BYTE _ATL :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _EASZ :3; + }bitc; + }EACH2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _R0 :1; + IO_WORD _R1 :1; + IO_WORD _R2 :1; + IO_WORD _ACE :1; + IO_WORD _STS :1; + IO_WORD _WSF :1; + IO_WORD _ES :1; + IO_WORD _BW :1; + IO_WORD _EASZ0 :1; + IO_WORD _EASZ1 :1; + IO_WORD _EASZ2 :1; + IO_WORD _CSE :1; + IO_WORD _CSL :1; + IO_WORD _ATL :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD _R :3; + IO_WORD :5; + IO_WORD _EASZ :3; + }bitc; + }EAC3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _R0 :1; + IO_BYTE _R1 :1; + IO_BYTE _R2 :1; + IO_BYTE _ACE :1; + IO_BYTE _STS :1; + IO_BYTE _WSF :1; + IO_BYTE _ES :1; + IO_BYTE _BW :1; + }bit; + struct{ + IO_BYTE _R :3; + }bitc; + }EACL3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EASZ0 :1; + IO_BYTE _EASZ1 :1; + IO_BYTE _EASZ2 :1; + IO_BYTE _CSE :1; + IO_BYTE _CSL :1; + IO_BYTE _ATL :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _EASZ :3; + }bitc; + }EACH3STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _R0 :1; + IO_WORD _R1 :1; + IO_WORD _R2 :1; + IO_WORD _ACE :1; + IO_WORD _STS :1; + IO_WORD _WSF :1; + IO_WORD _ES :1; + IO_WORD _BW :1; + IO_WORD _EASZ0 :1; + IO_WORD _EASZ1 :1; + IO_WORD _EASZ2 :1; + IO_WORD _CSE :1; + IO_WORD _CSL :1; + IO_WORD _ATL :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD _R :3; + IO_WORD :5; + IO_WORD _EASZ :3; + }bitc; + }EAC4STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _R0 :1; + IO_BYTE _R1 :1; + IO_BYTE _R2 :1; + IO_BYTE _ACE :1; + IO_BYTE _STS :1; + IO_BYTE _WSF :1; + IO_BYTE _ES :1; + IO_BYTE _BW :1; + }bit; + struct{ + IO_BYTE _R :3; + }bitc; + }EACL4STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EASZ0 :1; + IO_BYTE _EASZ1 :1; + IO_BYTE _EASZ2 :1; + IO_BYTE _CSE :1; + IO_BYTE _CSL :1; + IO_BYTE _ATL :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _EASZ :3; + }bitc; + }EACH4STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _R0 :1; + IO_WORD _R1 :1; + IO_WORD _R2 :1; + IO_WORD _ACE :1; + IO_WORD _STS :1; + IO_WORD _WSF :1; + IO_WORD _ES :1; + IO_WORD _BW :1; + IO_WORD _EASZ0 :1; + IO_WORD _EASZ1 :1; + IO_WORD _EASZ2 :1; + IO_WORD _CSE :1; + IO_WORD _CSL :1; + IO_WORD _ATL :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD _R :3; + IO_WORD :5; + IO_WORD _EASZ :3; + }bitc; + }EAC5STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _R0 :1; + IO_BYTE _R1 :1; + IO_BYTE _R2 :1; + IO_BYTE _ACE :1; + IO_BYTE _STS :1; + IO_BYTE _WSF :1; + IO_BYTE _ES :1; + IO_BYTE _BW :1; + }bit; + struct{ + IO_BYTE _R :3; + }bitc; + }EACL5STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EASZ0 :1; + IO_BYTE _EASZ1 :1; + IO_BYTE _EASZ2 :1; + IO_BYTE _CSE :1; + IO_BYTE _CSL :1; + IO_BYTE _ATL :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _EASZ :3; + }bitc; + }EACH5STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _A0 :1; + IO_BYTE _A1 :1; + IO_BYTE _A2 :1; + IO_BYTE _A3 :1; + IO_BYTE _A4 :1; + IO_BYTE _A5 :1; + IO_BYTE _A6 :1; + IO_BYTE _A7 :1; + }bit; + struct{ + IO_BYTE _A :8; + }bitc; + }EAS2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _A0 :1; + IO_BYTE _A1 :1; + IO_BYTE _A2 :1; + IO_BYTE _A3 :1; + IO_BYTE _A4 :1; + IO_BYTE _A5 :1; + IO_BYTE _A6 :1; + IO_BYTE _A7 :1; + }bit; + struct{ + IO_BYTE _A :8; + }bitc; + }EAS3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _A0 :1; + IO_BYTE _A1 :1; + IO_BYTE _A2 :1; + IO_BYTE _A3 :1; + IO_BYTE _A4 :1; + IO_BYTE _A5 :1; + IO_BYTE _A6 :1; + IO_BYTE _A7 :1; + }bit; + struct{ + IO_BYTE _A :8; + }bitc; + }EAS4STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _A0 :1; + IO_BYTE _A1 :1; + IO_BYTE _A2 :1; + IO_BYTE _A3 :1; + IO_BYTE _A4 :1; + IO_BYTE _A5 :1; + IO_BYTE _A6 :1; + IO_BYTE _A7 :1; + }bit; + }EAS5STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EAE0 :1; + IO_BYTE _EAE1 :1; + IO_BYTE _EAE2 :1; + IO_BYTE _EAE3 :1; + IO_BYTE _EAE4 :1; + IO_BYTE _EAE5 :1; + IO_BYTE _ERE :1; + IO_BYTE _NMS :1; + }bit; + struct{ + IO_BYTE _EAE :6; + }bitc; + }EBMSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _DIV0 :1; + IO_BYTE _DIV1 :1; + IO_BYTE _DIV2 :1; + IO_BYTE _CSM :1; + IO_BYTE _CKI :1; + IO_BYTE _CKE :1; + IO_BYTE _RYE :1; + IO_BYTE _HDE :1; + }bit; + struct{ + IO_BYTE _DIV :3; + }bitc; + }EBCFSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _A00 :1; + IO_BYTE _A01 :1; + IO_BYTE _A02 :1; + IO_BYTE _A03 :1; + IO_BYTE _A04 :1; + IO_BYTE _A05 :1; + IO_BYTE _A06 :1; + IO_BYTE _A07 :1; + }bit; + }EBAE0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _A08 :1; + IO_BYTE _A09 :1; + IO_BYTE _A10 :1; + IO_BYTE _A11 :1; + IO_BYTE _A12 :1; + IO_BYTE _A13 :1; + IO_BYTE _A14 :1; + IO_BYTE _A15 :1; + }bit; + }EBAE1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _A16 :1; + IO_BYTE _A17 :1; + IO_BYTE _A18 :1; + IO_BYTE _A19 :1; + IO_BYTE _A20 :1; + IO_BYTE _A21 :1; + IO_BYTE _A22 :1; + IO_BYTE _A23 :1; + }bit; + }EBAE2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _LBE :1; + IO_BYTE _UBE :1; + IO_BYTE _WRLE :1; + IO_BYTE _WRHE :1; + IO_BYTE _RDE :1; + IO_BYTE _ASE :1; + IO_BYTE _ASL :1; + IO_BYTE :1; + }bit; + }EBCSSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _INIT :1; + IO_WORD _IE :1; + IO_WORD _SIE :1; + IO_WORD _EIE :1; + IO_WORD :1; + IO_WORD _DAR :1; + IO_WORD _CCE :1; + IO_WORD _TEST :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }CTRLR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INIT :1; + IO_BYTE _IE :1; + IO_BYTE _SIE :1; + IO_BYTE _EIE :1; + IO_BYTE :1; + IO_BYTE _DAR :1; + IO_BYTE _CCE :1; + IO_BYTE _TEST :1; + }bit; + }CTRLRL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }CTRLRH0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _LEC0 :1; + IO_WORD _LEC1 :1; + IO_WORD _LEC2 :1; + IO_WORD _TXOK :1; + IO_WORD _RXOK :1; + IO_WORD _EPASS :1; + IO_WORD _EWARN :1; + IO_WORD _BOFF :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD _LEC :3; + }bitc; + }STATR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _LEC0 :1; + IO_BYTE _LEC1 :1; + IO_BYTE _LEC2 :1; + IO_BYTE _TXOK :1; + IO_BYTE _RXOK :1; + IO_BYTE _EPASS :1; + IO_BYTE _EWARN :1; + IO_BYTE _BOFF :1; + }bit; + struct{ + IO_BYTE _LEC :3; + }bitc; + }STATRL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }STATRH0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _TEC0 :1; + IO_WORD _TEC1 :1; + IO_WORD _TEC2 :1; + IO_WORD _TEC3 :1; + IO_WORD _TEC4 :1; + IO_WORD _TEC5 :1; + IO_WORD _TEC6 :1; + IO_WORD _TEC7 :1; + IO_WORD _REC0 :1; + IO_WORD _REC1 :1; + IO_WORD _REC2 :1; + IO_WORD _REC3 :1; + IO_WORD _REC4 :1; + IO_WORD _REC5 :1; + IO_WORD _REC6 :1; + IO_WORD _RP :1; + }bit; + struct{ + IO_WORD _TEC :8; + IO_WORD _REC :7; + }bitc; + }ERRCNT0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TEC0 :1; + IO_BYTE _TEC1 :1; + IO_BYTE _TEC2 :1; + IO_BYTE _TEC3 :1; + IO_BYTE _TEC4 :1; + IO_BYTE _TEC5 :1; + IO_BYTE _TEC6 :1; + IO_BYTE _TEC7 :1; + }bit; + struct{ + IO_BYTE _TEC :8; + }bitc; + }ERRCNTL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _REC0 :1; + IO_BYTE _REC1 :1; + IO_BYTE _REC2 :1; + IO_BYTE _REC3 :1; + IO_BYTE _REC4 :1; + IO_BYTE _REC5 :1; + IO_BYTE _REC6 :1; + IO_BYTE _RP :1; + }bit; + struct{ + IO_BYTE _REC :7; + }bitc; + }ERRCNTH0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _BRP0 :1; + IO_WORD _BRP1 :1; + IO_WORD _BRP2 :1; + IO_WORD _BRP3 :1; + IO_WORD _BRP4 :1; + IO_WORD _BRP5 :1; + IO_WORD _SJW0 :1; + IO_WORD _SJW1 :1; + IO_WORD _TSEG10 :1; + IO_WORD _TSEG11 :1; + IO_WORD _TSEG12 :1; + IO_WORD _TSEG13 :1; + IO_WORD _TSEG20 :1; + IO_WORD _TSEG21 :1; + IO_WORD _TSEG22 :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD _BRP :6; + IO_WORD _SJW :2; + IO_WORD _TSEG1 :4; + IO_WORD _TSEG2 :3; + }bitc; + }BTR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _BRP0 :1; + IO_BYTE _BRP1 :1; + IO_BYTE _BRP2 :1; + IO_BYTE _BRP3 :1; + IO_BYTE _BRP4 :1; + IO_BYTE _BRP5 :1; + IO_BYTE _SJW0 :1; + IO_BYTE _SJW1 :1; + }bit; + struct{ + IO_BYTE _BRP :6; + IO_BYTE _SJW :2; + }bitc; + }BTRL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TSEG10 :1; + IO_BYTE _TSEG11 :1; + IO_BYTE _TSEG12 :1; + IO_BYTE _TSEG13 :1; + IO_BYTE _TSEG20 :1; + IO_BYTE _TSEG21 :1; + IO_BYTE _TSEG22 :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _TSEG1 :4; + IO_BYTE _TSEG2 :3; + }bitc; + }BTRH0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _INTID0 :1; + IO_WORD _INTID1 :1; + IO_WORD _INTID2 :1; + IO_WORD _INTID3 :1; + IO_WORD _INTID4 :1; + IO_WORD _INTID5 :1; + IO_WORD _INTID6 :1; + IO_WORD _INTID7 :1; + IO_WORD _INTID8 :1; + IO_WORD _INTID9 :1; + IO_WORD _INTID10 :1; + IO_WORD _INTID11 :1; + IO_WORD _INTID12 :1; + IO_WORD _INTID13 :1; + IO_WORD _INTID14 :1; + IO_WORD _INTID15 :1; + }bit; + struct{ + IO_WORD _INTID :16; + }bitc; + }INTR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INTID0 :1; + IO_BYTE _INTID1 :1; + IO_BYTE _INTID2 :1; + IO_BYTE _INTID3 :1; + IO_BYTE _INTID4 :1; + IO_BYTE _INTID5 :1; + IO_BYTE _INTID6 :1; + IO_BYTE _INTID7 :1; + }bit; + }INTRL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INTID8 :1; + IO_BYTE _INTID9 :1; + IO_BYTE _INTID10 :1; + IO_BYTE _INTID11 :1; + IO_BYTE _INTID12 :1; + IO_BYTE _INTID13 :1; + IO_BYTE _INTID14 :1; + IO_BYTE _INTID15 :1; + }bit; + }INTRH0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD _BASIC :1; + IO_WORD _SILENT :1; + IO_WORD _LBACK :1; + IO_WORD _TX0 :1; + IO_WORD _TX1 :1; + IO_WORD _RX :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }TESTR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _BASIC :1; + IO_BYTE _SILENT :1; + IO_BYTE _LBACK :1; + IO_BYTE _TX0 :1; + IO_BYTE _TX1 :1; + IO_BYTE _RX :1; + }bit; + }TESTRL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }TESTRH0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _BRPE0 :1; + IO_WORD _BRPE1 :1; + IO_WORD _BRPE2 :1; + IO_WORD _BRPE3 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD _BRPE :4; + }bitc; + }BRPER0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _BRPE0 :1; + IO_BYTE _BRPE1 :1; + IO_BYTE _BRPE2 :1; + IO_BYTE _BRPE3 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _BRPE :4; + }bitc; + }BRPERL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }BRPERH0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _MSGN0 :1; + IO_WORD _MSGN1 :1; + IO_WORD _MSGN2 :1; + IO_WORD _MSGN3 :1; + IO_WORD _MSGN4 :1; + IO_WORD _MSGN5 :1; + IO_WORD _MSGN6 :1; + IO_WORD _MSGN7 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _BUSY :1; + }bit; + }IF1CREQ0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSGN0 :1; + IO_BYTE _MSGN1 :1; + IO_BYTE _MSGN2 :1; + IO_BYTE _MSGN3 :1; + IO_BYTE _MSGN4 :1; + IO_BYTE _MSGN5 :1; + IO_BYTE _MSGN6 :1; + IO_BYTE _MSGN7 :1; + }bit; + }IF1CREQL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _BUSY :1; + }bit; + }IF1CREQH0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _DATAB :1; + IO_WORD _DATAA :1; + IO_WORD _TXREQ :1; + IO_WORD _CIP :1; + IO_WORD _CONTROL :1; + IO_WORD _ARB :1; + IO_WORD _MASK :1; + IO_WORD _WRRD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF1CMSK0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _DATAB :1; + IO_BYTE _DATAA :1; + IO_BYTE _TXREQ :1; + IO_BYTE _CIP :1; + IO_BYTE _CONTROL :1; + IO_BYTE _ARB :1; + IO_BYTE _MASK :1; + IO_BYTE _WRRD :1; + }bit; + }IF1CMSKL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF1CMSKH0STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _MSK0 :1; + IO_LWORD _MSK1 :1; + IO_LWORD _MSK2 :1; + IO_LWORD _MSK3 :1; + IO_LWORD _MSK4 :1; + IO_LWORD _MSK5 :1; + IO_LWORD _MSK6 :1; + IO_LWORD _MSK7 :1; + IO_LWORD _MSK8 :1; + IO_LWORD _MSK9 :1; + IO_LWORD _MSK10 :1; + IO_LWORD _MSK11 :1; + IO_LWORD _MSK12 :1; + IO_LWORD _MSK13 :1; + IO_LWORD _MSK14 :1; + IO_LWORD _MSK15 :1; + IO_LWORD _MSK16 :1; + IO_LWORD _MSK17 :1; + IO_LWORD _MSK18 :1; + IO_LWORD _MSK19 :1; + IO_LWORD _MSK20 :1; + IO_LWORD _MSK21 :1; + IO_LWORD _MSK22 :1; + IO_LWORD _MSK23 :1; + IO_LWORD _MSK24 :1; + IO_LWORD _MSK25 :1; + IO_LWORD _MSK26 :1; + IO_LWORD _MSK27 :1; + IO_LWORD _MSK28 :1; + IO_LWORD :1; + IO_LWORD _MDIR :1; + IO_LWORD _MXTD :1; + }bit; + struct{ + IO_LWORD _MSK :29; + }bitc; + }IF1MSK0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _MSK0 :1; + IO_WORD _MSK1 :1; + IO_WORD _MSK2 :1; + IO_WORD _MSK3 :1; + IO_WORD _MSK4 :1; + IO_WORD _MSK5 :1; + IO_WORD _MSK6 :1; + IO_WORD _MSK7 :1; + IO_WORD _MSK8 :1; + IO_WORD _MSK9 :1; + IO_WORD _MSK10 :1; + IO_WORD _MSK11 :1; + IO_WORD _MSK12 :1; + IO_WORD _MSK13 :1; + IO_WORD _MSK14 :1; + IO_WORD _MSK15 :1; + }bit; + }IF1MSK10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSK0 :1; + IO_BYTE _MSK1 :1; + IO_BYTE _MSK2 :1; + IO_BYTE _MSK3 :1; + IO_BYTE _MSK4 :1; + IO_BYTE _MSK5 :1; + IO_BYTE _MSK6 :1; + IO_BYTE _MSK7 :1; + }bit; + }IF1MSK1L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSK8 :1; + IO_BYTE _MSK9 :1; + IO_BYTE _MSK10 :1; + IO_BYTE _MSK11 :1; + IO_BYTE _MSK12 :1; + IO_BYTE _MSK13 :1; + IO_BYTE _MSK14 :1; + IO_BYTE _MSK15 :1; + }bit; + }IF1MSK1H0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _MSK16 :1; + IO_WORD _MSK17 :1; + IO_WORD _MSK18 :1; + IO_WORD _MSK19 :1; + IO_WORD _MSK20 :1; + IO_WORD _MSK21 :1; + IO_WORD _MSK22 :1; + IO_WORD _MSK23 :1; + IO_WORD _MSK24 :1; + IO_WORD _MSK25 :1; + IO_WORD _MSK26 :1; + IO_WORD _MSK27 :1; + IO_WORD _MSK28 :1; + IO_WORD :1; + IO_WORD _MDIR :1; + IO_WORD _MXTD :1; + }bit; + }IF1MSK20STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSK16 :1; + IO_BYTE _MSK17 :1; + IO_BYTE _MSK18 :1; + IO_BYTE _MSK19 :1; + IO_BYTE _MSK20 :1; + IO_BYTE _MSK21 :1; + IO_BYTE _MSK22 :1; + IO_BYTE _MSK23 :1; + }bit; + }IF1MSK2L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSK24 :1; + IO_BYTE _MSK25 :1; + IO_BYTE _MSK26 :1; + IO_BYTE _MSK27 :1; + IO_BYTE _MSK28 :1; + IO_BYTE :1; + IO_BYTE _MDIR :1; + IO_BYTE _MXTD :1; + }bit; + }IF1MSK2H0STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _ID0 :1; + IO_LWORD _ID1 :1; + IO_LWORD _ID2 :1; + IO_LWORD _ID3 :1; + IO_LWORD _ID4 :1; + IO_LWORD _ID5 :1; + IO_LWORD _ID6 :1; + IO_LWORD _ID7 :1; + IO_LWORD _ID8 :1; + IO_LWORD _ID9 :1; + IO_LWORD _ID10 :1; + IO_LWORD _ID11 :1; + IO_LWORD _ID12 :1; + IO_LWORD _ID13 :1; + IO_LWORD _ID14 :1; + IO_LWORD _ID15 :1; + IO_LWORD _ID16 :1; + IO_LWORD _ID17 :1; + IO_LWORD _ID18 :1; + IO_LWORD _ID19 :1; + IO_LWORD _ID20 :1; + IO_LWORD _ID21 :1; + IO_LWORD _ID22 :1; + IO_LWORD _ID23 :1; + IO_LWORD _ID24 :1; + IO_LWORD _ID25 :1; + IO_LWORD _ID26 :1; + IO_LWORD _ID27 :1; + IO_LWORD _ID28 :1; + IO_LWORD _DIR :1; + IO_LWORD _XTD :1; + IO_LWORD _MSGVAL :1; + }bit; + struct{ + IO_LWORD _ID :29; + }bitc; + }IF1ARB0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _ID0 :1; + IO_WORD _ID1 :1; + IO_WORD _ID2 :1; + IO_WORD _ID3 :1; + IO_WORD _ID4 :1; + IO_WORD _ID5 :1; + IO_WORD _ID6 :1; + IO_WORD _ID7 :1; + IO_WORD _ID8 :1; + IO_WORD _ID9 :1; + IO_WORD _ID10 :1; + IO_WORD _ID11 :1; + IO_WORD _ID12 :1; + IO_WORD _ID13 :1; + IO_WORD _ID14 :1; + IO_WORD _ID15 :1; + }bit; + }IF1ARB10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ID0 :1; + IO_BYTE _ID1 :1; + IO_BYTE _ID2 :1; + IO_BYTE _ID3 :1; + IO_BYTE _ID4 :1; + IO_BYTE _ID5 :1; + IO_BYTE _ID6 :1; + IO_BYTE _ID7 :1; + }bit; + }IF1ARB1L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ID8 :1; + IO_BYTE _ID9 :1; + IO_BYTE _ID10 :1; + IO_BYTE _ID11 :1; + IO_BYTE _ID12 :1; + IO_BYTE _ID13 :1; + IO_BYTE _ID14 :1; + IO_BYTE _ID15 :1; + }bit; + }IF1ARB1H0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _ID16 :1; + IO_WORD _ID17 :1; + IO_WORD _ID18 :1; + IO_WORD _ID19 :1; + IO_WORD _ID20 :1; + IO_WORD _ID21 :1; + IO_WORD _ID22 :1; + IO_WORD _ID23 :1; + IO_WORD _ID24 :1; + IO_WORD _ID25 :1; + IO_WORD _ID26 :1; + IO_WORD _ID27 :1; + IO_WORD _ID28 :1; + IO_WORD _DIR :1; + IO_WORD _XTD :1; + IO_WORD _MSGVAL :1; + }bit; + }IF1ARB20STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ID16 :1; + IO_BYTE _ID17 :1; + IO_BYTE _ID18 :1; + IO_BYTE _ID19 :1; + IO_BYTE _ID20 :1; + IO_BYTE _ID21 :1; + IO_BYTE _ID22 :1; + IO_BYTE _ID23 :1; + }bit; + }IF1ARB2L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ID24 :1; + IO_BYTE _ID25 :1; + IO_BYTE _ID26 :1; + IO_BYTE _ID27 :1; + IO_BYTE _ID28 :1; + IO_BYTE _DIR :1; + IO_BYTE _XTD :1; + IO_BYTE _MSGVAL :1; + }bit; + }IF1ARB2H0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _DLC0 :1; + IO_WORD _DLC1 :1; + IO_WORD _DLC2 :1; + IO_WORD _DLC3 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _EOB :1; + IO_WORD _TXRQST :1; + IO_WORD _RMTEN :1; + IO_WORD _RXIE :1; + IO_WORD _TXIE :1; + IO_WORD _UMASK :1; + IO_WORD _INTPND :1; + IO_WORD _MSGLST :1; + IO_WORD _NEWDAT :1; + }bit; + struct{ + IO_WORD _DLC :4; + }bitc; + }IF1MCTR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _DLC0 :1; + IO_BYTE _DLC1 :1; + IO_BYTE _DLC2 :1; + IO_BYTE _DLC3 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _EOB :1; + }bit; + struct{ + IO_BYTE _DLC :4; + }bitc; + }IF1MCTRL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TXRQST :1; + IO_BYTE _RMTEN :1; + IO_BYTE _RXIE :1; + IO_BYTE _TXIE :1; + IO_BYTE _UMASK :1; + IO_BYTE _INTPND :1; + IO_BYTE _MSGLST :1; + IO_BYTE _NEWDAT :1; + }bit; + }IF1MCTRH0STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + }bit; + }IF1DTA0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF1DTA10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF1DTA1L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF1DTA1H0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF1DTA20STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF1DTA2L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF1DTA2H0STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + }bit; + }IF1DTB0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF1DTB10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF1DTB1L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF1DTB1H0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF1DTB20STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF1DTB2L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF1DTB2H0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _MSGN0 :1; + IO_WORD _MSGN1 :1; + IO_WORD _MSGN2 :1; + IO_WORD _MSGN3 :1; + IO_WORD _MSGN4 :1; + IO_WORD _MSGN5 :1; + IO_WORD _MSGN6 :1; + IO_WORD _MSGN7 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _BUSY :1; + }bit; + }IF2CREQ0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSGN0 :1; + IO_BYTE _MSGN1 :1; + IO_BYTE _MSGN2 :1; + IO_BYTE _MSGN3 :1; + IO_BYTE _MSGN4 :1; + IO_BYTE _MSGN5 :1; + IO_BYTE _MSGN6 :1; + IO_BYTE _MSGN7 :1; + }bit; + }IF2CREQL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _BUSY :1; + }bit; + }IF2CREQH0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _DATAB :1; + IO_WORD _DATAA :1; + IO_WORD _TXREQ :1; + IO_WORD _CIP :1; + IO_WORD _CONTROL :1; + IO_WORD _ARB :1; + IO_WORD _MASK :1; + IO_WORD _WRRD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF2CMSK0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _DATAB :1; + IO_BYTE _DATAA :1; + IO_BYTE _TXREQ :1; + IO_BYTE _CIP :1; + IO_BYTE _CONTROL :1; + IO_BYTE _ARB :1; + IO_BYTE _MASK :1; + IO_BYTE _WRRD :1; + }bit; + }IF2CMSKL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF2CMSKH0STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _MSK0 :1; + IO_LWORD _MSK1 :1; + IO_LWORD _MSK2 :1; + IO_LWORD _MSK3 :1; + IO_LWORD _MSK4 :1; + IO_LWORD _MSK5 :1; + IO_LWORD _MSK6 :1; + IO_LWORD _MSK7 :1; + IO_LWORD _MSK8 :1; + IO_LWORD _MSK9 :1; + IO_LWORD _MSK10 :1; + IO_LWORD _MSK11 :1; + IO_LWORD _MSK12 :1; + IO_LWORD _MSK13 :1; + IO_LWORD _MSK14 :1; + IO_LWORD _MSK15 :1; + IO_LWORD _MSK16 :1; + IO_LWORD _MSK17 :1; + IO_LWORD _MSK18 :1; + IO_LWORD _MSK19 :1; + IO_LWORD _MSK20 :1; + IO_LWORD _MSK21 :1; + IO_LWORD _MSK22 :1; + IO_LWORD _MSK23 :1; + IO_LWORD _MSK24 :1; + IO_LWORD _MSK25 :1; + IO_LWORD _MSK26 :1; + IO_LWORD _MSK27 :1; + IO_LWORD _MSK28 :1; + IO_LWORD :1; + IO_LWORD _MDIR :1; + IO_LWORD _MXTD :1; + }bit; + struct{ + IO_LWORD _MSK :29; + }bitc; + }IF2MSK0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _MSK0 :1; + IO_WORD _MSK1 :1; + IO_WORD _MSK2 :1; + IO_WORD _MSK3 :1; + IO_WORD _MSK4 :1; + IO_WORD _MSK5 :1; + IO_WORD _MSK6 :1; + IO_WORD _MSK7 :1; + IO_WORD _MSK8 :1; + IO_WORD _MSK9 :1; + IO_WORD _MSK10 :1; + IO_WORD _MSK11 :1; + IO_WORD _MSK12 :1; + IO_WORD _MSK13 :1; + IO_WORD _MSK14 :1; + IO_WORD _MSK15 :1; + }bit; + }IF2MSK10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSK0 :1; + IO_BYTE _MSK1 :1; + IO_BYTE _MSK2 :1; + IO_BYTE _MSK3 :1; + IO_BYTE _MSK4 :1; + IO_BYTE _MSK5 :1; + IO_BYTE _MSK6 :1; + IO_BYTE _MSK7 :1; + }bit; + }IF2MSK1L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSK8 :1; + IO_BYTE _MSK9 :1; + IO_BYTE _MSK10 :1; + IO_BYTE _MSK11 :1; + IO_BYTE _MSK12 :1; + IO_BYTE _MSK13 :1; + IO_BYTE _MSK14 :1; + IO_BYTE _MSK15 :1; + }bit; + }IF2MSK1H0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _MSK16 :1; + IO_WORD _MSK17 :1; + IO_WORD _MSK18 :1; + IO_WORD _MSK19 :1; + IO_WORD _MSK20 :1; + IO_WORD _MSK21 :1; + IO_WORD _MSK22 :1; + IO_WORD _MSK23 :1; + IO_WORD _MSK24 :1; + IO_WORD _MSK25 :1; + IO_WORD _MSK26 :1; + IO_WORD _MSK27 :1; + IO_WORD _MSK28 :1; + IO_WORD :1; + IO_WORD _MDIR :1; + IO_WORD _MXTD :1; + }bit; + }IF2MSK20STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSK16 :1; + IO_BYTE _MSK17 :1; + IO_BYTE _MSK18 :1; + IO_BYTE _MSK19 :1; + IO_BYTE _MSK20 :1; + IO_BYTE _MSK21 :1; + IO_BYTE _MSK22 :1; + IO_BYTE _MSK23 :1; + }bit; + }IF2MSK2L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSK24 :1; + IO_BYTE _MSK25 :1; + IO_BYTE _MSK26 :1; + IO_BYTE _MSK27 :1; + IO_BYTE _MSK28 :1; + IO_BYTE :1; + IO_BYTE _MDIR :1; + IO_BYTE _MXTD :1; + }bit; + }IF2MSK2H0STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _ID0 :1; + IO_LWORD _ID1 :1; + IO_LWORD _ID2 :1; + IO_LWORD _ID3 :1; + IO_LWORD _ID4 :1; + IO_LWORD _ID5 :1; + IO_LWORD _ID6 :1; + IO_LWORD _ID7 :1; + IO_LWORD _ID8 :1; + IO_LWORD _ID9 :1; + IO_LWORD _ID10 :1; + IO_LWORD _ID11 :1; + IO_LWORD _ID12 :1; + IO_LWORD _ID13 :1; + IO_LWORD _ID14 :1; + IO_LWORD _ID15 :1; + IO_LWORD _ID16 :1; + IO_LWORD _ID17 :1; + IO_LWORD _ID18 :1; + IO_LWORD _ID19 :1; + IO_LWORD _ID20 :1; + IO_LWORD _ID21 :1; + IO_LWORD _ID22 :1; + IO_LWORD _ID23 :1; + IO_LWORD _ID24 :1; + IO_LWORD _ID25 :1; + IO_LWORD _ID26 :1; + IO_LWORD _ID27 :1; + IO_LWORD _ID28 :1; + IO_LWORD _DIR :1; + IO_LWORD _XTD :1; + IO_LWORD _MSGVAL :1; + }bit; + struct{ + IO_LWORD _ID :29; + }bitc; + }IF2ARB0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _ID0 :1; + IO_WORD _ID1 :1; + IO_WORD _ID2 :1; + IO_WORD _ID3 :1; + IO_WORD _ID4 :1; + IO_WORD _ID5 :1; + IO_WORD _ID6 :1; + IO_WORD _ID7 :1; + IO_WORD _ID8 :1; + IO_WORD _ID9 :1; + IO_WORD _ID10 :1; + IO_WORD _ID11 :1; + IO_WORD _ID12 :1; + IO_WORD _ID13 :1; + IO_WORD _ID14 :1; + IO_WORD _ID15 :1; + }bit; + }IF2ARB10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ID0 :1; + IO_BYTE _ID1 :1; + IO_BYTE _ID2 :1; + IO_BYTE _ID3 :1; + IO_BYTE _ID4 :1; + IO_BYTE _ID5 :1; + IO_BYTE _ID6 :1; + IO_BYTE _ID7 :1; + }bit; + }IF2ARB1L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ID8 :1; + IO_BYTE _ID9 :1; + IO_BYTE _ID10 :1; + IO_BYTE _ID11 :1; + IO_BYTE _ID12 :1; + IO_BYTE _ID13 :1; + IO_BYTE _ID14 :1; + IO_BYTE _ID15 :1; + }bit; + }IF2ARB1H0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _ID16 :1; + IO_WORD _ID17 :1; + IO_WORD _ID18 :1; + IO_WORD _ID19 :1; + IO_WORD _ID20 :1; + IO_WORD _ID21 :1; + IO_WORD _ID22 :1; + IO_WORD _ID23 :1; + IO_WORD _ID24 :1; + IO_WORD _ID25 :1; + IO_WORD _ID26 :1; + IO_WORD _ID27 :1; + IO_WORD _ID28 :1; + IO_WORD _DIR :1; + IO_WORD _XTD :1; + IO_WORD _MSGVAL :1; + }bit; + }IF2ARB20STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ID16 :1; + IO_BYTE _ID17 :1; + IO_BYTE _ID18 :1; + IO_BYTE _ID19 :1; + IO_BYTE _ID20 :1; + IO_BYTE _ID21 :1; + IO_BYTE _ID22 :1; + IO_BYTE _ID23 :1; + }bit; + }IF2ARB2L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ID24 :1; + IO_BYTE _ID25 :1; + IO_BYTE _ID26 :1; + IO_BYTE _ID27 :1; + IO_BYTE _ID28 :1; + IO_BYTE _DIR :1; + IO_BYTE _XTD :1; + IO_BYTE _MSGVAL :1; + }bit; + }IF2ARB2H0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _DLC0 :1; + IO_WORD _DLC1 :1; + IO_WORD _DLC2 :1; + IO_WORD _DLC3 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _EOB :1; + IO_WORD _TXRQST :1; + IO_WORD _RMTEN :1; + IO_WORD _RXIE :1; + IO_WORD _TXIE :1; + IO_WORD _UMASK :1; + IO_WORD _INTPND :1; + IO_WORD _MSGLST :1; + IO_WORD _NEWDAT :1; + }bit; + struct{ + IO_WORD _DLC :4; + }bitc; + }IF2MCTR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _DLC0 :1; + IO_BYTE _DLC1 :1; + IO_BYTE _DLC2 :1; + IO_BYTE _DLC3 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _EOB :1; + }bit; + struct{ + IO_BYTE _DLC :4; + }bitc; + }IF2MCTRL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TXRQST :1; + IO_BYTE _RMTEN :1; + IO_BYTE _RXIE :1; + IO_BYTE _TXIE :1; + IO_BYTE _UMASK :1; + IO_BYTE _INTPND :1; + IO_BYTE _MSGLST :1; + IO_BYTE _NEWDAT :1; + }bit; + }IF2MCTRH0STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + }bit; + }IF2DTA0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF2DTA10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF2DTA1L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF2DTA1H0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF2DTA20STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF2DTA2L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF2DTA2H0STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + }bit; + }IF2DTB0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF2DTB10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF2DTB1L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF2DTB1H0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF2DTB20STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF2DTB2L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF2DTB2H0STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _TXRQST1 :1; + IO_LWORD _TXRQST2 :1; + IO_LWORD _TXRQST3 :1; + IO_LWORD _TXRQST4 :1; + IO_LWORD _TXRQST5 :1; + IO_LWORD _TXRQST6 :1; + IO_LWORD _TXRQST7 :1; + IO_LWORD _TXRQST8 :1; + IO_LWORD _TXRQST9 :1; + IO_LWORD _TXRQST10 :1; + IO_LWORD _TXRQST11 :1; + IO_LWORD _TXRQST12 :1; + IO_LWORD _TXRQST13 :1; + IO_LWORD _TXRQST14 :1; + IO_LWORD _TXRQST15 :1; + IO_LWORD _TXRQST16 :1; + IO_LWORD _TXRQST17 :1; + IO_LWORD _TXRQST18 :1; + IO_LWORD _TXRQST19 :1; + IO_LWORD _TXRQST20 :1; + IO_LWORD _TXRQST21 :1; + IO_LWORD _TXRQST22 :1; + IO_LWORD _TXRQST23 :1; + IO_LWORD _TXRQST24 :1; + IO_LWORD _TXRQST25 :1; + IO_LWORD _TXRQST26 :1; + IO_LWORD _TXRQST27 :1; + IO_LWORD _TXRQST28 :1; + IO_LWORD _TXRQST29 :1; + IO_LWORD _TXRQST30 :1; + IO_LWORD _TXRQST31 :1; + IO_LWORD _TXRQST32 :1; + }bit; + struct{ + IO_LWORD _TXRQST :32; + }bitc; + }TREQR0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _TXRQST1 :1; + IO_WORD _TXRQST2 :1; + IO_WORD _TXRQST3 :1; + IO_WORD _TXRQST4 :1; + IO_WORD _TXRQST5 :1; + IO_WORD _TXRQST6 :1; + IO_WORD _TXRQST7 :1; + IO_WORD _TXRQST8 :1; + IO_WORD _TXRQST9 :1; + IO_WORD _TXRQST10 :1; + IO_WORD _TXRQST11 :1; + IO_WORD _TXRQST12 :1; + IO_WORD _TXRQST13 :1; + IO_WORD _TXRQST14 :1; + IO_WORD _TXRQST15 :1; + IO_WORD _TXRQST16 :1; + }bit; + }TREQR10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TXRQST1 :1; + IO_BYTE _TXRQST2 :1; + IO_BYTE _TXRQST3 :1; + IO_BYTE _TXRQST4 :1; + IO_BYTE _TXRQST5 :1; + IO_BYTE _TXRQST6 :1; + IO_BYTE _TXRQST7 :1; + IO_BYTE _TXRQST8 :1; + }bit; + }TREQR1L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TXRQST9 :1; + IO_BYTE _TXRQST10 :1; + IO_BYTE _TXRQST11 :1; + IO_BYTE _TXRQST12 :1; + IO_BYTE _TXRQST13 :1; + IO_BYTE _TXRQST14 :1; + IO_BYTE _TXRQST15 :1; + IO_BYTE _TXRQST16 :1; + }bit; + }TREQR1H0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _TXRQST17 :1; + IO_WORD _TXRQST18 :1; + IO_WORD _TXRQST19 :1; + IO_WORD _TXRQST20 :1; + IO_WORD _TXRQST21 :1; + IO_WORD _TXRQST22 :1; + IO_WORD _TXRQST23 :1; + IO_WORD _TXRQST24 :1; + IO_WORD _TXRQST25 :1; + IO_WORD _TXRQST26 :1; + IO_WORD _TXRQST27 :1; + IO_WORD _TXRQST28 :1; + IO_WORD _TXRQST29 :1; + IO_WORD _TXRQST30 :1; + IO_WORD _TXRQST31 :1; + IO_WORD _TXRQST32 :1; + }bit; + }TREQR20STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TXRQST17 :1; + IO_BYTE _TXRQST18 :1; + IO_BYTE _TXRQST19 :1; + IO_BYTE _TXRQST20 :1; + IO_BYTE _TXRQST21 :1; + IO_BYTE _TXRQST22 :1; + IO_BYTE _TXRQST23 :1; + IO_BYTE _TXRQST24 :1; + }bit; + }TREQR2L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TXRQST25 :1; + IO_BYTE _TXRQST26 :1; + IO_BYTE _TXRQST27 :1; + IO_BYTE _TXRQST28 :1; + IO_BYTE _TXRQST29 :1; + IO_BYTE _TXRQST30 :1; + IO_BYTE _TXRQST31 :1; + IO_BYTE _TXRQST32 :1; + }bit; + }TREQR2H0STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _NEWDAT1 :1; + IO_LWORD _NEWDAT2 :1; + IO_LWORD _NEWDAT3 :1; + IO_LWORD _NEWDAT4 :1; + IO_LWORD _NEWDAT5 :1; + IO_LWORD _NEWDAT6 :1; + IO_LWORD _NEWDAT7 :1; + IO_LWORD _NEWDAT8 :1; + IO_LWORD _NEWDAT9 :1; + IO_LWORD _NEWDAT10 :1; + IO_LWORD _NEWDAT11 :1; + IO_LWORD _NEWDAT12 :1; + IO_LWORD _NEWDAT13 :1; + IO_LWORD _NEWDAT14 :1; + IO_LWORD _NEWDAT15 :1; + IO_LWORD _NEWDAT16 :1; + IO_LWORD _NEWDAT17 :1; + IO_LWORD _NEWDAT18 :1; + IO_LWORD _NEWDAT19 :1; + IO_LWORD _NEWDAT20 :1; + IO_LWORD _NEWDAT21 :1; + IO_LWORD _NEWDAT22 :1; + IO_LWORD _NEWDAT23 :1; + IO_LWORD _NEWDAT24 :1; + IO_LWORD _NEWDAT25 :1; + IO_LWORD _NEWDAT26 :1; + IO_LWORD _NEWDAT27 :1; + IO_LWORD _NEWDAT28 :1; + IO_LWORD _NEWDAT29 :1; + IO_LWORD _NEWDAT30 :1; + IO_LWORD _NEWDAT31 :1; + IO_LWORD _NEWDAT32 :1; + }bit; + struct{ + IO_LWORD _NEWDAT :32; + }bitc; + }NEWDT0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _NEWDAT1 :1; + IO_WORD _NEWDAT2 :1; + IO_WORD _NEWDAT3 :1; + IO_WORD _NEWDAT4 :1; + IO_WORD _NEWDAT5 :1; + IO_WORD _NEWDAT6 :1; + IO_WORD _NEWDAT7 :1; + IO_WORD _NEWDAT8 :1; + IO_WORD _NEWDAT9 :1; + IO_WORD _NEWDAT10 :1; + IO_WORD _NEWDAT11 :1; + IO_WORD _NEWDAT12 :1; + IO_WORD _NEWDAT13 :1; + IO_WORD _NEWDAT14 :1; + IO_WORD _NEWDAT15 :1; + IO_WORD _NEWDAT16 :1; + }bit; + }NEWDT10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _NEWDAT1 :1; + IO_BYTE _NEWDAT2 :1; + IO_BYTE _NEWDAT3 :1; + IO_BYTE _NEWDAT4 :1; + IO_BYTE _NEWDAT5 :1; + IO_BYTE _NEWDAT6 :1; + IO_BYTE _NEWDAT7 :1; + IO_BYTE _NEWDAT8 :1; + }bit; + }NEWDT1L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _NEWDAT9 :1; + IO_BYTE _NEWDAT10 :1; + IO_BYTE _NEWDAT11 :1; + IO_BYTE _NEWDAT12 :1; + IO_BYTE _NEWDAT13 :1; + IO_BYTE _NEWDAT14 :1; + IO_BYTE _NEWDAT15 :1; + IO_BYTE _NEWDAT16 :1; + }bit; + }NEWDT1H0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _NEWDAT17 :1; + IO_WORD _NEWDAT18 :1; + IO_WORD _NEWDAT19 :1; + IO_WORD _NEWDAT20 :1; + IO_WORD _NEWDAT21 :1; + IO_WORD _NEWDAT22 :1; + IO_WORD _NEWDAT23 :1; + IO_WORD _NEWDAT24 :1; + IO_WORD _NEWDAT25 :1; + IO_WORD _NEWDAT26 :1; + IO_WORD _NEWDAT27 :1; + IO_WORD _NEWDAT28 :1; + IO_WORD _NEWDAT29 :1; + IO_WORD _NEWDAT30 :1; + IO_WORD _NEWDAT31 :1; + IO_WORD _NEWDAT32 :1; + }bit; + }NEWDT20STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _NEWDAT17 :1; + IO_BYTE _NEWDAT18 :1; + IO_BYTE _NEWDAT19 :1; + IO_BYTE _NEWDAT20 :1; + IO_BYTE _NEWDAT21 :1; + IO_BYTE _NEWDAT22 :1; + IO_BYTE _NEWDAT23 :1; + IO_BYTE _NEWDAT24 :1; + }bit; + }NEWDT2L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _NEWDAT25 :1; + IO_BYTE _NEWDAT26 :1; + IO_BYTE _NEWDAT27 :1; + IO_BYTE _NEWDAT28 :1; + IO_BYTE _NEWDAT29 :1; + IO_BYTE _NEWDAT30 :1; + IO_BYTE _NEWDAT31 :1; + IO_BYTE _NEWDAT32 :1; + }bit; + }NEWDT2H0STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _INTPND1 :1; + IO_LWORD _INTPND2 :1; + IO_LWORD _INTPND3 :1; + IO_LWORD _INTPND4 :1; + IO_LWORD _INTPND5 :1; + IO_LWORD _INTPND6 :1; + IO_LWORD _INTPND7 :1; + IO_LWORD _INTPND8 :1; + IO_LWORD _INTPND9 :1; + IO_LWORD _INTPND10 :1; + IO_LWORD _INTPND11 :1; + IO_LWORD _INTPND12 :1; + IO_LWORD _INTPND13 :1; + IO_LWORD _INTPND14 :1; + IO_LWORD _INTPND15 :1; + IO_LWORD _INTPND16 :1; + IO_LWORD _INTPND17 :1; + IO_LWORD _INTPND18 :1; + IO_LWORD _INTPND19 :1; + IO_LWORD _INTPND20 :1; + IO_LWORD _INTPND21 :1; + IO_LWORD _INTPND22 :1; + IO_LWORD _INTPND23 :1; + IO_LWORD _INTPND24 :1; + IO_LWORD _INTPND25 :1; + IO_LWORD _INTPND26 :1; + IO_LWORD _INTPND27 :1; + IO_LWORD _INTPND28 :1; + IO_LWORD _INTPND29 :1; + IO_LWORD _INTPND30 :1; + IO_LWORD _INTPND31 :1; + IO_LWORD _INTPND32 :1; + }bit; + struct{ + IO_LWORD _INTPND :32; + }bitc; + }INTPND0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _INTPND1 :1; + IO_WORD _INTPND2 :1; + IO_WORD _INTPND3 :1; + IO_WORD _INTPND4 :1; + IO_WORD _INTPND5 :1; + IO_WORD _INTPND6 :1; + IO_WORD _INTPND7 :1; + IO_WORD _INTPND8 :1; + IO_WORD _INTPND9 :1; + IO_WORD _INTPND10 :1; + IO_WORD _INTPND11 :1; + IO_WORD _INTPND12 :1; + IO_WORD _INTPND13 :1; + IO_WORD _INTPND14 :1; + IO_WORD _INTPND15 :1; + IO_WORD _INTPND16 :1; + }bit; + }INTPND10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INTPND1 :1; + IO_BYTE _INTPND2 :1; + IO_BYTE _INTPND3 :1; + IO_BYTE _INTPND4 :1; + IO_BYTE _INTPND5 :1; + IO_BYTE _INTPND6 :1; + IO_BYTE _INTPND7 :1; + IO_BYTE _INTPND8 :1; + }bit; + }INTPND1L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INTPND9 :1; + IO_BYTE _INTPND10 :1; + IO_BYTE _INTPND11 :1; + IO_BYTE _INTPND12 :1; + IO_BYTE _INTPND13 :1; + IO_BYTE _INTPND14 :1; + IO_BYTE _INTPND15 :1; + IO_BYTE _INTPND16 :1; + }bit; + }INTPND1H0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _INTPND17 :1; + IO_WORD _INTPND18 :1; + IO_WORD _INTPND19 :1; + IO_WORD _INTPND20 :1; + IO_WORD _INTPND21 :1; + IO_WORD _INTPND22 :1; + IO_WORD _INTPND23 :1; + IO_WORD _INTPND24 :1; + IO_WORD _INTPND25 :1; + IO_WORD _INTPND26 :1; + IO_WORD _INTPND27 :1; + IO_WORD _INTPND28 :1; + IO_WORD _INTPND29 :1; + IO_WORD _INTPND30 :1; + IO_WORD _INTPND31 :1; + IO_WORD _INTPND32 :1; + }bit; + }INTPND20STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INTPND17 :1; + IO_BYTE _INTPND18 :1; + IO_BYTE _INTPND19 :1; + IO_BYTE _INTPND20 :1; + IO_BYTE _INTPND21 :1; + IO_BYTE _INTPND22 :1; + IO_BYTE _INTPND23 :1; + IO_BYTE _INTPND24 :1; + }bit; + }INTPND2L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INTPND25 :1; + IO_BYTE _INTPND26 :1; + IO_BYTE _INTPND27 :1; + IO_BYTE _INTPND28 :1; + IO_BYTE _INTPND29 :1; + IO_BYTE _INTPND30 :1; + IO_BYTE _INTPND31 :1; + IO_BYTE _INTPND32 :1; + }bit; + }INTPND2H0STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _MSGVAL1 :1; + IO_LWORD _MSGVAL2 :1; + IO_LWORD _MSGVAL3 :1; + IO_LWORD _MSGVAL4 :1; + IO_LWORD _MSGVAL5 :1; + IO_LWORD _MSGVAL6 :1; + IO_LWORD _MSGVAL7 :1; + IO_LWORD _MSGVAL8 :1; + IO_LWORD _MSGVAL9 :1; + IO_LWORD _MSGVAL10 :1; + IO_LWORD _MSGVAL11 :1; + IO_LWORD _MSGVAL12 :1; + IO_LWORD _MSGVAL13 :1; + IO_LWORD _MSGVAL14 :1; + IO_LWORD _MSGVAL15 :1; + IO_LWORD _MSGVAL16 :1; + IO_LWORD _MSGVAL17 :1; + IO_LWORD _MSGVAL18 :1; + IO_LWORD _MSGVAL19 :1; + IO_LWORD _MSGVAL20 :1; + IO_LWORD _MSGVAL21 :1; + IO_LWORD _MSGVAL22 :1; + IO_LWORD _MSGVAL23 :1; + IO_LWORD _MSGVAL24 :1; + IO_LWORD _MSGVAL25 :1; + IO_LWORD _MSGVAL26 :1; + IO_LWORD _MSGVAL27 :1; + IO_LWORD _MSGVAL28 :1; + IO_LWORD _MSGVAL29 :1; + IO_LWORD _MSGVAL30 :1; + IO_LWORD _MSGVAL31 :1; + IO_LWORD _MSGVAL32 :1; + }bit; + struct{ + IO_LWORD _MSGVAL :32; + }bitc; + }MSGVAL0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _MSGVAL1 :1; + IO_WORD _MSGVAL2 :1; + IO_WORD _MSGVAL3 :1; + IO_WORD _MSGVAL4 :1; + IO_WORD _MSGVAL5 :1; + IO_WORD _MSGVAL6 :1; + IO_WORD _MSGVAL7 :1; + IO_WORD _MSGVAL8 :1; + IO_WORD _MSGVAL9 :1; + IO_WORD _MSGVAL10 :1; + IO_WORD _MSGVAL11 :1; + IO_WORD _MSGVAL12 :1; + IO_WORD _MSGVAL13 :1; + IO_WORD _MSGVAL14 :1; + IO_WORD _MSGVAL15 :1; + IO_WORD _MSGVAL16 :1; + }bit; + }MSGVAL10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSGVAL1 :1; + IO_BYTE _MSGVAL2 :1; + IO_BYTE _MSGVAL3 :1; + IO_BYTE _MSGVAL4 :1; + IO_BYTE _MSGVAL5 :1; + IO_BYTE _MSGVAL6 :1; + IO_BYTE _MSGVAL7 :1; + IO_BYTE _MSGVAL8 :1; + }bit; + }MSGVAL1L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSGVAL9 :1; + IO_BYTE _MSGVAL10 :1; + IO_BYTE _MSGVAL11 :1; + IO_BYTE _MSGVAL12 :1; + IO_BYTE _MSGVAL13 :1; + IO_BYTE _MSGVAL14 :1; + IO_BYTE _MSGVAL15 :1; + IO_BYTE _MSGVAL16 :1; + }bit; + }MSGVAL1H0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _MSGVAL17 :1; + IO_WORD _MSGVAL18 :1; + IO_WORD _MSGVAL19 :1; + IO_WORD _MSGVAL20 :1; + IO_WORD _MSGVAL21 :1; + IO_WORD _MSGVAL22 :1; + IO_WORD _MSGVAL23 :1; + IO_WORD _MSGVAL24 :1; + IO_WORD _MSGVAL25 :1; + IO_WORD _MSGVAL26 :1; + IO_WORD _MSGVAL27 :1; + IO_WORD _MSGVAL28 :1; + IO_WORD _MSGVAL29 :1; + IO_WORD _MSGVAL30 :1; + IO_WORD _MSGVAL31 :1; + IO_WORD _MSGVAL32 :1; + }bit; + }MSGVAL20STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSGVAL17 :1; + IO_BYTE _MSGVAL18 :1; + IO_BYTE _MSGVAL19 :1; + IO_BYTE _MSGVAL20 :1; + IO_BYTE _MSGVAL21 :1; + IO_BYTE _MSGVAL22 :1; + IO_BYTE _MSGVAL23 :1; + IO_BYTE _MSGVAL24 :1; + }bit; + }MSGVAL2L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSGVAL25 :1; + IO_BYTE _MSGVAL26 :1; + IO_BYTE _MSGVAL27 :1; + IO_BYTE _MSGVAL28 :1; + IO_BYTE _MSGVAL29 :1; + IO_BYTE _MSGVAL30 :1; + IO_BYTE _MSGVAL31 :1; + IO_BYTE _MSGVAL32 :1; + }bit; + }MSGVAL2H0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }COER0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _INIT :1; + IO_WORD _IE :1; + IO_WORD _SIE :1; + IO_WORD _EIE :1; + IO_WORD :1; + IO_WORD _DAR :1; + IO_WORD _CCE :1; + IO_WORD _TEST :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }CTRLR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INIT :1; + IO_BYTE _IE :1; + IO_BYTE _SIE :1; + IO_BYTE _EIE :1; + IO_BYTE :1; + IO_BYTE _DAR :1; + IO_BYTE _CCE :1; + IO_BYTE _TEST :1; + }bit; + }CTRLRL1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }CTRLRH1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _LEC0 :1; + IO_WORD _LEC1 :1; + IO_WORD _LEC2 :1; + IO_WORD _TXOK :1; + IO_WORD _RXOK :1; + IO_WORD _EPASS :1; + IO_WORD _EWARN :1; + IO_WORD _BOFF :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD _LEC :3; + }bitc; + }STATR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _LEC0 :1; + IO_BYTE _LEC1 :1; + IO_BYTE _LEC2 :1; + IO_BYTE _TXOK :1; + IO_BYTE _RXOK :1; + IO_BYTE _EPASS :1; + IO_BYTE _EWARN :1; + IO_BYTE _BOFF :1; + }bit; + struct{ + IO_BYTE _LEC :3; + }bitc; + }STATRL1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }STATRH1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _TEC0 :1; + IO_WORD _TEC1 :1; + IO_WORD _TEC2 :1; + IO_WORD _TEC3 :1; + IO_WORD _TEC4 :1; + IO_WORD _TEC5 :1; + IO_WORD _TEC6 :1; + IO_WORD _TEC7 :1; + IO_WORD _REC0 :1; + IO_WORD _REC1 :1; + IO_WORD _REC2 :1; + IO_WORD _REC3 :1; + IO_WORD _REC4 :1; + IO_WORD _REC5 :1; + IO_WORD _REC6 :1; + IO_WORD _RP :1; + }bit; + struct{ + IO_WORD _TEC :8; + IO_WORD _REC :7; + }bitc; + }ERRCNT1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TEC0 :1; + IO_BYTE _TEC1 :1; + IO_BYTE _TEC2 :1; + IO_BYTE _TEC3 :1; + IO_BYTE _TEC4 :1; + IO_BYTE _TEC5 :1; + IO_BYTE _TEC6 :1; + IO_BYTE _TEC7 :1; + }bit; + struct{ + IO_BYTE _TEC :8; + }bitc; + }ERRCNTL1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _REC0 :1; + IO_BYTE _REC1 :1; + IO_BYTE _REC2 :1; + IO_BYTE _REC3 :1; + IO_BYTE _REC4 :1; + IO_BYTE _REC5 :1; + IO_BYTE _REC6 :1; + IO_BYTE _RP :1; + }bit; + struct{ + IO_BYTE _REC :7; + }bitc; + }ERRCNTH1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _BRP0 :1; + IO_WORD _BRP1 :1; + IO_WORD _BRP2 :1; + IO_WORD _BRP3 :1; + IO_WORD _BRP4 :1; + IO_WORD _BRP5 :1; + IO_WORD _SJW0 :1; + IO_WORD _SJW1 :1; + IO_WORD _TSEG10 :1; + IO_WORD _TSEG11 :1; + IO_WORD _TSEG12 :1; + IO_WORD _TSEG13 :1; + IO_WORD _TSEG20 :1; + IO_WORD _TSEG21 :1; + IO_WORD _TSEG22 :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD _BRP :6; + IO_WORD _SJW :2; + IO_WORD _TSEG1 :4; + IO_WORD _TSEG2 :3; + }bitc; + }BTR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _BRP0 :1; + IO_BYTE _BRP1 :1; + IO_BYTE _BRP2 :1; + IO_BYTE _BRP3 :1; + IO_BYTE _BRP4 :1; + IO_BYTE _BRP5 :1; + IO_BYTE _SJW0 :1; + IO_BYTE _SJW1 :1; + }bit; + struct{ + IO_BYTE _BRP :6; + IO_BYTE _SJW :2; + }bitc; + }BTRL1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TSEG10 :1; + IO_BYTE _TSEG11 :1; + IO_BYTE _TSEG12 :1; + IO_BYTE _TSEG13 :1; + IO_BYTE _TSEG20 :1; + IO_BYTE _TSEG21 :1; + IO_BYTE _TSEG22 :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _TSEG1 :4; + IO_BYTE _TSEG2 :3; + }bitc; + }BTRH1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _INTID0 :1; + IO_WORD _INTID1 :1; + IO_WORD _INTID2 :1; + IO_WORD _INTID3 :1; + IO_WORD _INTID4 :1; + IO_WORD _INTID5 :1; + IO_WORD _INTID6 :1; + IO_WORD _INTID7 :1; + IO_WORD _INTID8 :1; + IO_WORD _INTID9 :1; + IO_WORD _INTID10 :1; + IO_WORD _INTID11 :1; + IO_WORD _INTID12 :1; + IO_WORD _INTID13 :1; + IO_WORD _INTID14 :1; + IO_WORD _INTID15 :1; + }bit; + struct{ + IO_WORD _INTID :16; + }bitc; + }INTR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INTID0 :1; + IO_BYTE _INTID1 :1; + IO_BYTE _INTID2 :1; + IO_BYTE _INTID3 :1; + IO_BYTE _INTID4 :1; + IO_BYTE _INTID5 :1; + IO_BYTE _INTID6 :1; + IO_BYTE _INTID7 :1; + }bit; + }INTRL1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INTID8 :1; + IO_BYTE _INTID9 :1; + IO_BYTE _INTID10 :1; + IO_BYTE _INTID11 :1; + IO_BYTE _INTID12 :1; + IO_BYTE _INTID13 :1; + IO_BYTE _INTID14 :1; + IO_BYTE _INTID15 :1; + }bit; + }INTRH1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD _BASIC :1; + IO_WORD _SILENT :1; + IO_WORD _LBACK :1; + IO_WORD _TX0 :1; + IO_WORD _TX1 :1; + IO_WORD _RX :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }TESTR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _BASIC :1; + IO_BYTE _SILENT :1; + IO_BYTE _LBACK :1; + IO_BYTE _TX0 :1; + IO_BYTE _TX1 :1; + IO_BYTE _RX :1; + }bit; + }TESTRL1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }TESTRH1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _BRPE0 :1; + IO_WORD _BRPE1 :1; + IO_WORD _BRPE2 :1; + IO_WORD _BRPE3 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD _BRPE :4; + }bitc; + }BRPER1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _BRPE0 :1; + IO_BYTE _BRPE1 :1; + IO_BYTE _BRPE2 :1; + IO_BYTE _BRPE3 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _BRPE :4; + }bitc; + }BRPERL1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }BRPERH1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _MSGN0 :1; + IO_WORD _MSGN1 :1; + IO_WORD _MSGN2 :1; + IO_WORD _MSGN3 :1; + IO_WORD _MSGN4 :1; + IO_WORD _MSGN5 :1; + IO_WORD _MSGN6 :1; + IO_WORD _MSGN7 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _BUSY :1; + }bit; + }IF1CREQ1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSGN0 :1; + IO_BYTE _MSGN1 :1; + IO_BYTE _MSGN2 :1; + IO_BYTE _MSGN3 :1; + IO_BYTE _MSGN4 :1; + IO_BYTE _MSGN5 :1; + IO_BYTE _MSGN6 :1; + IO_BYTE _MSGN7 :1; + }bit; + }IF1CREQL1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _BUSY :1; + }bit; + }IF1CREQH1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _DATAB :1; + IO_WORD _DATAA :1; + IO_WORD _TXREQ :1; + IO_WORD _CIP :1; + IO_WORD _CONTROL :1; + IO_WORD _ARB :1; + IO_WORD _MASK :1; + IO_WORD _WRRD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF1CMSK1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _DATAB :1; + IO_BYTE _DATAA :1; + IO_BYTE _TXREQ :1; + IO_BYTE _CIP :1; + IO_BYTE _CONTROL :1; + IO_BYTE _ARB :1; + IO_BYTE _MASK :1; + IO_BYTE _WRRD :1; + }bit; + }IF1CMSKL1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF1CMSKH1STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _MSK0 :1; + IO_LWORD _MSK1 :1; + IO_LWORD _MSK2 :1; + IO_LWORD _MSK3 :1; + IO_LWORD _MSK4 :1; + IO_LWORD _MSK5 :1; + IO_LWORD _MSK6 :1; + IO_LWORD _MSK7 :1; + IO_LWORD _MSK8 :1; + IO_LWORD _MSK9 :1; + IO_LWORD _MSK10 :1; + IO_LWORD _MSK11 :1; + IO_LWORD _MSK12 :1; + IO_LWORD _MSK13 :1; + IO_LWORD _MSK14 :1; + IO_LWORD _MSK15 :1; + IO_LWORD _MSK16 :1; + IO_LWORD _MSK17 :1; + IO_LWORD _MSK18 :1; + IO_LWORD _MSK19 :1; + IO_LWORD _MSK20 :1; + IO_LWORD _MSK21 :1; + IO_LWORD _MSK22 :1; + IO_LWORD _MSK23 :1; + IO_LWORD _MSK24 :1; + IO_LWORD _MSK25 :1; + IO_LWORD _MSK26 :1; + IO_LWORD _MSK27 :1; + IO_LWORD _MSK28 :1; + IO_LWORD :1; + IO_LWORD _MDIR :1; + IO_LWORD _MXTD :1; + }bit; + struct{ + IO_LWORD _MSK :29; + }bitc; + }IF1MSK1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _MSK0 :1; + IO_WORD _MSK1 :1; + IO_WORD _MSK2 :1; + IO_WORD _MSK3 :1; + IO_WORD _MSK4 :1; + IO_WORD _MSK5 :1; + IO_WORD _MSK6 :1; + IO_WORD _MSK7 :1; + IO_WORD _MSK8 :1; + IO_WORD _MSK9 :1; + IO_WORD _MSK10 :1; + IO_WORD _MSK11 :1; + IO_WORD _MSK12 :1; + IO_WORD _MSK13 :1; + IO_WORD _MSK14 :1; + IO_WORD _MSK15 :1; + }bit; + }IF1MSK11STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSK0 :1; + IO_BYTE _MSK1 :1; + IO_BYTE _MSK2 :1; + IO_BYTE _MSK3 :1; + IO_BYTE _MSK4 :1; + IO_BYTE _MSK5 :1; + IO_BYTE _MSK6 :1; + IO_BYTE _MSK7 :1; + }bit; + }IF1MSK1L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSK8 :1; + IO_BYTE _MSK9 :1; + IO_BYTE _MSK10 :1; + IO_BYTE _MSK11 :1; + IO_BYTE _MSK12 :1; + IO_BYTE _MSK13 :1; + IO_BYTE _MSK14 :1; + IO_BYTE _MSK15 :1; + }bit; + }IF1MSK1H1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _MSK16 :1; + IO_WORD _MSK17 :1; + IO_WORD _MSK18 :1; + IO_WORD _MSK19 :1; + IO_WORD _MSK20 :1; + IO_WORD _MSK21 :1; + IO_WORD _MSK22 :1; + IO_WORD _MSK23 :1; + IO_WORD _MSK24 :1; + IO_WORD _MSK25 :1; + IO_WORD _MSK26 :1; + IO_WORD _MSK27 :1; + IO_WORD _MSK28 :1; + IO_WORD :1; + IO_WORD _MDIR :1; + IO_WORD _MXTD :1; + }bit; + }IF1MSK21STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSK16 :1; + IO_BYTE _MSK17 :1; + IO_BYTE _MSK18 :1; + IO_BYTE _MSK19 :1; + IO_BYTE _MSK20 :1; + IO_BYTE _MSK21 :1; + IO_BYTE _MSK22 :1; + IO_BYTE _MSK23 :1; + }bit; + }IF1MSK2L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSK24 :1; + IO_BYTE _MSK25 :1; + IO_BYTE _MSK26 :1; + IO_BYTE _MSK27 :1; + IO_BYTE _MSK28 :1; + IO_BYTE :1; + IO_BYTE _MDIR :1; + IO_BYTE _MXTD :1; + }bit; + }IF1MSK2H1STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _ID0 :1; + IO_LWORD _ID1 :1; + IO_LWORD _ID2 :1; + IO_LWORD _ID3 :1; + IO_LWORD _ID4 :1; + IO_LWORD _ID5 :1; + IO_LWORD _ID6 :1; + IO_LWORD _ID7 :1; + IO_LWORD _ID8 :1; + IO_LWORD _ID9 :1; + IO_LWORD _ID10 :1; + IO_LWORD _ID11 :1; + IO_LWORD _ID12 :1; + IO_LWORD _ID13 :1; + IO_LWORD _ID14 :1; + IO_LWORD _ID15 :1; + IO_LWORD _ID16 :1; + IO_LWORD _ID17 :1; + IO_LWORD _ID18 :1; + IO_LWORD _ID19 :1; + IO_LWORD _ID20 :1; + IO_LWORD _ID21 :1; + IO_LWORD _ID22 :1; + IO_LWORD _ID23 :1; + IO_LWORD _ID24 :1; + IO_LWORD _ID25 :1; + IO_LWORD _ID26 :1; + IO_LWORD _ID27 :1; + IO_LWORD _ID28 :1; + IO_LWORD _DIR :1; + IO_LWORD _XTD :1; + IO_LWORD _MSGVAL :1; + }bit; + struct{ + IO_LWORD _ID :29; + }bitc; + }IF1ARB1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _ID0 :1; + IO_WORD _ID1 :1; + IO_WORD _ID2 :1; + IO_WORD _ID3 :1; + IO_WORD _ID4 :1; + IO_WORD _ID5 :1; + IO_WORD _ID6 :1; + IO_WORD _ID7 :1; + IO_WORD _ID8 :1; + IO_WORD _ID9 :1; + IO_WORD _ID10 :1; + IO_WORD _ID11 :1; + IO_WORD _ID12 :1; + IO_WORD _ID13 :1; + IO_WORD _ID14 :1; + IO_WORD _ID15 :1; + }bit; + }IF1ARB11STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ID0 :1; + IO_BYTE _ID1 :1; + IO_BYTE _ID2 :1; + IO_BYTE _ID3 :1; + IO_BYTE _ID4 :1; + IO_BYTE _ID5 :1; + IO_BYTE _ID6 :1; + IO_BYTE _ID7 :1; + }bit; + }IF1ARB1L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ID8 :1; + IO_BYTE _ID9 :1; + IO_BYTE _ID10 :1; + IO_BYTE _ID11 :1; + IO_BYTE _ID12 :1; + IO_BYTE _ID13 :1; + IO_BYTE _ID14 :1; + IO_BYTE _ID15 :1; + }bit; + }IF1ARB1H1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _ID16 :1; + IO_WORD _ID17 :1; + IO_WORD _ID18 :1; + IO_WORD _ID19 :1; + IO_WORD _ID20 :1; + IO_WORD _ID21 :1; + IO_WORD _ID22 :1; + IO_WORD _ID23 :1; + IO_WORD _ID24 :1; + IO_WORD _ID25 :1; + IO_WORD _ID26 :1; + IO_WORD _ID27 :1; + IO_WORD _ID28 :1; + IO_WORD _DIR :1; + IO_WORD _XTD :1; + IO_WORD _MSGVAL :1; + }bit; + }IF1ARB21STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ID16 :1; + IO_BYTE _ID17 :1; + IO_BYTE _ID18 :1; + IO_BYTE _ID19 :1; + IO_BYTE _ID20 :1; + IO_BYTE _ID21 :1; + IO_BYTE _ID22 :1; + IO_BYTE _ID23 :1; + }bit; + }IF1ARB2L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ID24 :1; + IO_BYTE _ID25 :1; + IO_BYTE _ID26 :1; + IO_BYTE _ID27 :1; + IO_BYTE _ID28 :1; + IO_BYTE _DIR :1; + IO_BYTE _XTD :1; + IO_BYTE _MSGVAL :1; + }bit; + }IF1ARB2H1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _DLC0 :1; + IO_WORD _DLC1 :1; + IO_WORD _DLC2 :1; + IO_WORD _DLC3 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _EOB :1; + IO_WORD _TXRQST :1; + IO_WORD _RMTEN :1; + IO_WORD _RXIE :1; + IO_WORD _TXIE :1; + IO_WORD _UMASK :1; + IO_WORD _INTPND :1; + IO_WORD _MSGLST :1; + IO_WORD _NEWDAT :1; + }bit; + struct{ + IO_WORD _DLC :4; + }bitc; + }IF1MCTR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _DLC0 :1; + IO_BYTE _DLC1 :1; + IO_BYTE _DLC2 :1; + IO_BYTE _DLC3 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _EOB :1; + }bit; + struct{ + IO_BYTE _DLC :4; + }bitc; + }IF1MCTRL1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TXRQST :1; + IO_BYTE _RMTEN :1; + IO_BYTE _RXIE :1; + IO_BYTE _TXIE :1; + IO_BYTE _UMASK :1; + IO_BYTE _INTPND :1; + IO_BYTE _MSGLST :1; + IO_BYTE _NEWDAT :1; + }bit; + }IF1MCTRH1STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + }bit; + }IF1DTA1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF1DTA11STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF1DTA1L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF1DTA1H1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF1DTA21STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF1DTA2L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF1DTA2H1STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + }bit; + }IF1DTB1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF1DTB11STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF1DTB1L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF1DTB1H1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF1DTB21STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF1DTB2L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF1DTB2H1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _MSGN0 :1; + IO_WORD _MSGN1 :1; + IO_WORD _MSGN2 :1; + IO_WORD _MSGN3 :1; + IO_WORD _MSGN4 :1; + IO_WORD _MSGN5 :1; + IO_WORD _MSGN6 :1; + IO_WORD _MSGN7 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _BUSY :1; + }bit; + }IF2CREQ1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSGN0 :1; + IO_BYTE _MSGN1 :1; + IO_BYTE _MSGN2 :1; + IO_BYTE _MSGN3 :1; + IO_BYTE _MSGN4 :1; + IO_BYTE _MSGN5 :1; + IO_BYTE _MSGN6 :1; + IO_BYTE _MSGN7 :1; + }bit; + }IF2CREQL1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _BUSY :1; + }bit; + }IF2CREQH1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _DATAB :1; + IO_WORD _DATAA :1; + IO_WORD _TXREQ :1; + IO_WORD _CIP :1; + IO_WORD _CONTROL :1; + IO_WORD _ARB :1; + IO_WORD _MASK :1; + IO_WORD _WRRD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF2CMSK1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _DATAB :1; + IO_BYTE _DATAA :1; + IO_BYTE _TXREQ :1; + IO_BYTE _CIP :1; + IO_BYTE _CONTROL :1; + IO_BYTE _ARB :1; + IO_BYTE _MASK :1; + IO_BYTE _WRRD :1; + }bit; + }IF2CMSKL1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF2CMSKH1STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _MSK0 :1; + IO_LWORD _MSK1 :1; + IO_LWORD _MSK2 :1; + IO_LWORD _MSK3 :1; + IO_LWORD _MSK4 :1; + IO_LWORD _MSK5 :1; + IO_LWORD _MSK6 :1; + IO_LWORD _MSK7 :1; + IO_LWORD _MSK8 :1; + IO_LWORD _MSK9 :1; + IO_LWORD _MSK10 :1; + IO_LWORD _MSK11 :1; + IO_LWORD _MSK12 :1; + IO_LWORD _MSK13 :1; + IO_LWORD _MSK14 :1; + IO_LWORD _MSK15 :1; + IO_LWORD _MSK16 :1; + IO_LWORD _MSK17 :1; + IO_LWORD _MSK18 :1; + IO_LWORD _MSK19 :1; + IO_LWORD _MSK20 :1; + IO_LWORD _MSK21 :1; + IO_LWORD _MSK22 :1; + IO_LWORD _MSK23 :1; + IO_LWORD _MSK24 :1; + IO_LWORD _MSK25 :1; + IO_LWORD _MSK26 :1; + IO_LWORD _MSK27 :1; + IO_LWORD _MSK28 :1; + IO_LWORD :1; + IO_LWORD _MDIR :1; + IO_LWORD _MXTD :1; + }bit; + struct{ + IO_LWORD _MSK :29; + }bitc; + }IF2MSK1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _MSK0 :1; + IO_WORD _MSK1 :1; + IO_WORD _MSK2 :1; + IO_WORD _MSK3 :1; + IO_WORD _MSK4 :1; + IO_WORD _MSK5 :1; + IO_WORD _MSK6 :1; + IO_WORD _MSK7 :1; + IO_WORD _MSK8 :1; + IO_WORD _MSK9 :1; + IO_WORD _MSK10 :1; + IO_WORD _MSK11 :1; + IO_WORD _MSK12 :1; + IO_WORD _MSK13 :1; + IO_WORD _MSK14 :1; + IO_WORD _MSK15 :1; + }bit; + }IF2MSK11STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSK0 :1; + IO_BYTE _MSK1 :1; + IO_BYTE _MSK2 :1; + IO_BYTE _MSK3 :1; + IO_BYTE _MSK4 :1; + IO_BYTE _MSK5 :1; + IO_BYTE _MSK6 :1; + IO_BYTE _MSK7 :1; + }bit; + }IF2MSK1L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSK8 :1; + IO_BYTE _MSK9 :1; + IO_BYTE _MSK10 :1; + IO_BYTE _MSK11 :1; + IO_BYTE _MSK12 :1; + IO_BYTE _MSK13 :1; + IO_BYTE _MSK14 :1; + IO_BYTE _MSK15 :1; + }bit; + }IF2MSK1H1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _MSK16 :1; + IO_WORD _MSK17 :1; + IO_WORD _MSK18 :1; + IO_WORD _MSK19 :1; + IO_WORD _MSK20 :1; + IO_WORD _MSK21 :1; + IO_WORD _MSK22 :1; + IO_WORD _MSK23 :1; + IO_WORD _MSK24 :1; + IO_WORD _MSK25 :1; + IO_WORD _MSK26 :1; + IO_WORD _MSK27 :1; + IO_WORD _MSK28 :1; + IO_WORD :1; + IO_WORD _MDIR :1; + IO_WORD _MXTD :1; + }bit; + }IF2MSK21STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSK16 :1; + IO_BYTE _MSK17 :1; + IO_BYTE _MSK18 :1; + IO_BYTE _MSK19 :1; + IO_BYTE _MSK20 :1; + IO_BYTE _MSK21 :1; + IO_BYTE _MSK22 :1; + IO_BYTE _MSK23 :1; + }bit; + }IF2MSK2L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSK24 :1; + IO_BYTE _MSK25 :1; + IO_BYTE _MSK26 :1; + IO_BYTE _MSK27 :1; + IO_BYTE _MSK28 :1; + IO_BYTE :1; + IO_BYTE _MDIR :1; + IO_BYTE _MXTD :1; + }bit; + }IF2MSK2H1STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _ID0 :1; + IO_LWORD _ID1 :1; + IO_LWORD _ID2 :1; + IO_LWORD _ID3 :1; + IO_LWORD _ID4 :1; + IO_LWORD _ID5 :1; + IO_LWORD _ID6 :1; + IO_LWORD _ID7 :1; + IO_LWORD _ID8 :1; + IO_LWORD _ID9 :1; + IO_LWORD _ID10 :1; + IO_LWORD _ID11 :1; + IO_LWORD _ID12 :1; + IO_LWORD _ID13 :1; + IO_LWORD _ID14 :1; + IO_LWORD _ID15 :1; + IO_LWORD _ID16 :1; + IO_LWORD _ID17 :1; + IO_LWORD _ID18 :1; + IO_LWORD _ID19 :1; + IO_LWORD _ID20 :1; + IO_LWORD _ID21 :1; + IO_LWORD _ID22 :1; + IO_LWORD _ID23 :1; + IO_LWORD _ID24 :1; + IO_LWORD _ID25 :1; + IO_LWORD _ID26 :1; + IO_LWORD _ID27 :1; + IO_LWORD _ID28 :1; + IO_LWORD _DIR :1; + IO_LWORD _XTD :1; + IO_LWORD _MSGVAL :1; + }bit; + struct{ + IO_LWORD _ID :29; + }bitc; + }IF2ARB1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _ID0 :1; + IO_WORD _ID1 :1; + IO_WORD _ID2 :1; + IO_WORD _ID3 :1; + IO_WORD _ID4 :1; + IO_WORD _ID5 :1; + IO_WORD _ID6 :1; + IO_WORD _ID7 :1; + IO_WORD _ID8 :1; + IO_WORD _ID9 :1; + IO_WORD _ID10 :1; + IO_WORD _ID11 :1; + IO_WORD _ID12 :1; + IO_WORD _ID13 :1; + IO_WORD _ID14 :1; + IO_WORD _ID15 :1; + }bit; + }IF2ARB11STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ID0 :1; + IO_BYTE _ID1 :1; + IO_BYTE _ID2 :1; + IO_BYTE _ID3 :1; + IO_BYTE _ID4 :1; + IO_BYTE _ID5 :1; + IO_BYTE _ID6 :1; + IO_BYTE _ID7 :1; + }bit; + }IF2ARB1L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ID8 :1; + IO_BYTE _ID9 :1; + IO_BYTE _ID10 :1; + IO_BYTE _ID11 :1; + IO_BYTE _ID12 :1; + IO_BYTE _ID13 :1; + IO_BYTE _ID14 :1; + IO_BYTE _ID15 :1; + }bit; + }IF2ARB1H1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _ID16 :1; + IO_WORD _ID17 :1; + IO_WORD _ID18 :1; + IO_WORD _ID19 :1; + IO_WORD _ID20 :1; + IO_WORD _ID21 :1; + IO_WORD _ID22 :1; + IO_WORD _ID23 :1; + IO_WORD _ID24 :1; + IO_WORD _ID25 :1; + IO_WORD _ID26 :1; + IO_WORD _ID27 :1; + IO_WORD _ID28 :1; + IO_WORD _DIR :1; + IO_WORD _XTD :1; + IO_WORD _MSGVAL :1; + }bit; + }IF2ARB21STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ID16 :1; + IO_BYTE _ID17 :1; + IO_BYTE _ID18 :1; + IO_BYTE _ID19 :1; + IO_BYTE _ID20 :1; + IO_BYTE _ID21 :1; + IO_BYTE _ID22 :1; + IO_BYTE _ID23 :1; + }bit; + }IF2ARB2L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ID24 :1; + IO_BYTE _ID25 :1; + IO_BYTE _ID26 :1; + IO_BYTE _ID27 :1; + IO_BYTE _ID28 :1; + IO_BYTE _DIR :1; + IO_BYTE _XTD :1; + IO_BYTE _MSGVAL :1; + }bit; + }IF2ARB2H1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _DLC0 :1; + IO_WORD _DLC1 :1; + IO_WORD _DLC2 :1; + IO_WORD _DLC3 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _EOB :1; + IO_WORD _TXRQST :1; + IO_WORD _RMTEN :1; + IO_WORD _RXIE :1; + IO_WORD _TXIE :1; + IO_WORD _UMASK :1; + IO_WORD _INTPND :1; + IO_WORD _MSGLST :1; + IO_WORD _NEWDAT :1; + }bit; + struct{ + IO_WORD _DLC :4; + }bitc; + }IF2MCTR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _DLC0 :1; + IO_BYTE _DLC1 :1; + IO_BYTE _DLC2 :1; + IO_BYTE _DLC3 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _EOB :1; + }bit; + struct{ + IO_BYTE _DLC :4; + }bitc; + }IF2MCTRL1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TXRQST :1; + IO_BYTE _RMTEN :1; + IO_BYTE _RXIE :1; + IO_BYTE _TXIE :1; + IO_BYTE _UMASK :1; + IO_BYTE _INTPND :1; + IO_BYTE _MSGLST :1; + IO_BYTE _NEWDAT :1; + }bit; + }IF2MCTRH1STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + }bit; + }IF2DTA1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF2DTA11STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF2DTA1L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF2DTA1H1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF2DTA21STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF2DTA2L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF2DTA2H1STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + }bit; + }IF2DTB1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF2DTB11STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF2DTB1L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF2DTB1H1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF2DTB21STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF2DTB2L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF2DTB2H1STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _TXRQST1 :1; + IO_LWORD _TXRQST2 :1; + IO_LWORD _TXRQST3 :1; + IO_LWORD _TXRQST4 :1; + IO_LWORD _TXRQST5 :1; + IO_LWORD _TXRQST6 :1; + IO_LWORD _TXRQST7 :1; + IO_LWORD _TXRQST8 :1; + IO_LWORD _TXRQST9 :1; + IO_LWORD _TXRQST10 :1; + IO_LWORD _TXRQST11 :1; + IO_LWORD _TXRQST12 :1; + IO_LWORD _TXRQST13 :1; + IO_LWORD _TXRQST14 :1; + IO_LWORD _TXRQST15 :1; + IO_LWORD _TXRQST16 :1; + IO_LWORD _TXRQST17 :1; + IO_LWORD _TXRQST18 :1; + IO_LWORD _TXRQST19 :1; + IO_LWORD _TXRQST20 :1; + IO_LWORD _TXRQST21 :1; + IO_LWORD _TXRQST22 :1; + IO_LWORD _TXRQST23 :1; + IO_LWORD _TXRQST24 :1; + IO_LWORD _TXRQST25 :1; + IO_LWORD _TXRQST26 :1; + IO_LWORD _TXRQST27 :1; + IO_LWORD _TXRQST28 :1; + IO_LWORD _TXRQST29 :1; + IO_LWORD _TXRQST30 :1; + IO_LWORD _TXRQST31 :1; + IO_LWORD _TXRQST32 :1; + }bit; + struct{ + IO_LWORD _TXRQST :32; + }bitc; + }TREQR1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _TXRQST1 :1; + IO_WORD _TXRQST2 :1; + IO_WORD _TXRQST3 :1; + IO_WORD _TXRQST4 :1; + IO_WORD _TXRQST5 :1; + IO_WORD _TXRQST6 :1; + IO_WORD _TXRQST7 :1; + IO_WORD _TXRQST8 :1; + IO_WORD _TXRQST9 :1; + IO_WORD _TXRQST10 :1; + IO_WORD _TXRQST11 :1; + IO_WORD _TXRQST12 :1; + IO_WORD _TXRQST13 :1; + IO_WORD _TXRQST14 :1; + IO_WORD _TXRQST15 :1; + IO_WORD _TXRQST16 :1; + }bit; + }TREQR11STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TXRQST1 :1; + IO_BYTE _TXRQST2 :1; + IO_BYTE _TXRQST3 :1; + IO_BYTE _TXRQST4 :1; + IO_BYTE _TXRQST5 :1; + IO_BYTE _TXRQST6 :1; + IO_BYTE _TXRQST7 :1; + IO_BYTE _TXRQST8 :1; + }bit; + }TREQR1L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TXRQST9 :1; + IO_BYTE _TXRQST10 :1; + IO_BYTE _TXRQST11 :1; + IO_BYTE _TXRQST12 :1; + IO_BYTE _TXRQST13 :1; + IO_BYTE _TXRQST14 :1; + IO_BYTE _TXRQST15 :1; + IO_BYTE _TXRQST16 :1; + }bit; + }TREQR1H1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _TXRQST17 :1; + IO_WORD _TXRQST18 :1; + IO_WORD _TXRQST19 :1; + IO_WORD _TXRQST20 :1; + IO_WORD _TXRQST21 :1; + IO_WORD _TXRQST22 :1; + IO_WORD _TXRQST23 :1; + IO_WORD _TXRQST24 :1; + IO_WORD _TXRQST25 :1; + IO_WORD _TXRQST26 :1; + IO_WORD _TXRQST27 :1; + IO_WORD _TXRQST28 :1; + IO_WORD _TXRQST29 :1; + IO_WORD _TXRQST30 :1; + IO_WORD _TXRQST31 :1; + IO_WORD _TXRQST32 :1; + }bit; + }TREQR21STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TXRQST17 :1; + IO_BYTE _TXRQST18 :1; + IO_BYTE _TXRQST19 :1; + IO_BYTE _TXRQST20 :1; + IO_BYTE _TXRQST21 :1; + IO_BYTE _TXRQST22 :1; + IO_BYTE _TXRQST23 :1; + IO_BYTE _TXRQST24 :1; + }bit; + }TREQR2L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TXRQST25 :1; + IO_BYTE _TXRQST26 :1; + IO_BYTE _TXRQST27 :1; + IO_BYTE _TXRQST28 :1; + IO_BYTE _TXRQST29 :1; + IO_BYTE _TXRQST30 :1; + IO_BYTE _TXRQST31 :1; + IO_BYTE _TXRQST32 :1; + }bit; + }TREQR2H1STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _NEWDAT1 :1; + IO_LWORD _NEWDAT2 :1; + IO_LWORD _NEWDAT3 :1; + IO_LWORD _NEWDAT4 :1; + IO_LWORD _NEWDAT5 :1; + IO_LWORD _NEWDAT6 :1; + IO_LWORD _NEWDAT7 :1; + IO_LWORD _NEWDAT8 :1; + IO_LWORD _NEWDAT9 :1; + IO_LWORD _NEWDAT10 :1; + IO_LWORD _NEWDAT11 :1; + IO_LWORD _NEWDAT12 :1; + IO_LWORD _NEWDAT13 :1; + IO_LWORD _NEWDAT14 :1; + IO_LWORD _NEWDAT15 :1; + IO_LWORD _NEWDAT16 :1; + IO_LWORD _NEWDAT17 :1; + IO_LWORD _NEWDAT18 :1; + IO_LWORD _NEWDAT19 :1; + IO_LWORD _NEWDAT20 :1; + IO_LWORD _NEWDAT21 :1; + IO_LWORD _NEWDAT22 :1; + IO_LWORD _NEWDAT23 :1; + IO_LWORD _NEWDAT24 :1; + IO_LWORD _NEWDAT25 :1; + IO_LWORD _NEWDAT26 :1; + IO_LWORD _NEWDAT27 :1; + IO_LWORD _NEWDAT28 :1; + IO_LWORD _NEWDAT29 :1; + IO_LWORD _NEWDAT30 :1; + IO_LWORD _NEWDAT31 :1; + IO_LWORD _NEWDAT32 :1; + }bit; + struct{ + IO_LWORD _NEWDAT :32; + }bitc; + }NEWDT1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _NEWDAT1 :1; + IO_WORD _NEWDAT2 :1; + IO_WORD _NEWDAT3 :1; + IO_WORD _NEWDAT4 :1; + IO_WORD _NEWDAT5 :1; + IO_WORD _NEWDAT6 :1; + IO_WORD _NEWDAT7 :1; + IO_WORD _NEWDAT8 :1; + IO_WORD _NEWDAT9 :1; + IO_WORD _NEWDAT10 :1; + IO_WORD _NEWDAT11 :1; + IO_WORD _NEWDAT12 :1; + IO_WORD _NEWDAT13 :1; + IO_WORD _NEWDAT14 :1; + IO_WORD _NEWDAT15 :1; + IO_WORD _NEWDAT16 :1; + }bit; + }NEWDT11STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _NEWDAT1 :1; + IO_BYTE _NEWDAT2 :1; + IO_BYTE _NEWDAT3 :1; + IO_BYTE _NEWDAT4 :1; + IO_BYTE _NEWDAT5 :1; + IO_BYTE _NEWDAT6 :1; + IO_BYTE _NEWDAT7 :1; + IO_BYTE _NEWDAT8 :1; + }bit; + }NEWDT1L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _NEWDAT9 :1; + IO_BYTE _NEWDAT10 :1; + IO_BYTE _NEWDAT11 :1; + IO_BYTE _NEWDAT12 :1; + IO_BYTE _NEWDAT13 :1; + IO_BYTE _NEWDAT14 :1; + IO_BYTE _NEWDAT15 :1; + IO_BYTE _NEWDAT16 :1; + }bit; + }NEWDT1H1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _NEWDAT17 :1; + IO_WORD _NEWDAT18 :1; + IO_WORD _NEWDAT19 :1; + IO_WORD _NEWDAT20 :1; + IO_WORD _NEWDAT21 :1; + IO_WORD _NEWDAT22 :1; + IO_WORD _NEWDAT23 :1; + IO_WORD _NEWDAT24 :1; + IO_WORD _NEWDAT25 :1; + IO_WORD _NEWDAT26 :1; + IO_WORD _NEWDAT27 :1; + IO_WORD _NEWDAT28 :1; + IO_WORD _NEWDAT29 :1; + IO_WORD _NEWDAT30 :1; + IO_WORD _NEWDAT31 :1; + IO_WORD _NEWDAT32 :1; + }bit; + }NEWDT21STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _NEWDAT17 :1; + IO_BYTE _NEWDAT18 :1; + IO_BYTE _NEWDAT19 :1; + IO_BYTE _NEWDAT20 :1; + IO_BYTE _NEWDAT21 :1; + IO_BYTE _NEWDAT22 :1; + IO_BYTE _NEWDAT23 :1; + IO_BYTE _NEWDAT24 :1; + }bit; + }NEWDT2L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _NEWDAT25 :1; + IO_BYTE _NEWDAT26 :1; + IO_BYTE _NEWDAT27 :1; + IO_BYTE _NEWDAT28 :1; + IO_BYTE _NEWDAT29 :1; + IO_BYTE _NEWDAT30 :1; + IO_BYTE _NEWDAT31 :1; + IO_BYTE _NEWDAT32 :1; + }bit; + }NEWDT2H1STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _INTPND1 :1; + IO_LWORD _INTPND2 :1; + IO_LWORD _INTPND3 :1; + IO_LWORD _INTPND4 :1; + IO_LWORD _INTPND5 :1; + IO_LWORD _INTPND6 :1; + IO_LWORD _INTPND7 :1; + IO_LWORD _INTPND8 :1; + IO_LWORD _INTPND9 :1; + IO_LWORD _INTPND10 :1; + IO_LWORD _INTPND11 :1; + IO_LWORD _INTPND12 :1; + IO_LWORD _INTPND13 :1; + IO_LWORD _INTPND14 :1; + IO_LWORD _INTPND15 :1; + IO_LWORD _INTPND16 :1; + IO_LWORD _INTPND17 :1; + IO_LWORD _INTPND18 :1; + IO_LWORD _INTPND19 :1; + IO_LWORD _INTPND20 :1; + IO_LWORD _INTPND21 :1; + IO_LWORD _INTPND22 :1; + IO_LWORD _INTPND23 :1; + IO_LWORD _INTPND24 :1; + IO_LWORD _INTPND25 :1; + IO_LWORD _INTPND26 :1; + IO_LWORD _INTPND27 :1; + IO_LWORD _INTPND28 :1; + IO_LWORD _INTPND29 :1; + IO_LWORD _INTPND30 :1; + IO_LWORD _INTPND31 :1; + IO_LWORD _INTPND32 :1; + }bit; + struct{ + IO_LWORD _INTPND :32; + }bitc; + }INTPND1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _INTPND1 :1; + IO_WORD _INTPND2 :1; + IO_WORD _INTPND3 :1; + IO_WORD _INTPND4 :1; + IO_WORD _INTPND5 :1; + IO_WORD _INTPND6 :1; + IO_WORD _INTPND7 :1; + IO_WORD _INTPND8 :1; + IO_WORD _INTPND9 :1; + IO_WORD _INTPND10 :1; + IO_WORD _INTPND11 :1; + IO_WORD _INTPND12 :1; + IO_WORD _INTPND13 :1; + IO_WORD _INTPND14 :1; + IO_WORD _INTPND15 :1; + IO_WORD _INTPND16 :1; + }bit; + }INTPND11STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INTPND1 :1; + IO_BYTE _INTPND2 :1; + IO_BYTE _INTPND3 :1; + IO_BYTE _INTPND4 :1; + IO_BYTE _INTPND5 :1; + IO_BYTE _INTPND6 :1; + IO_BYTE _INTPND7 :1; + IO_BYTE _INTPND8 :1; + }bit; + }INTPND1L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INTPND9 :1; + IO_BYTE _INTPND10 :1; + IO_BYTE _INTPND11 :1; + IO_BYTE _INTPND12 :1; + IO_BYTE _INTPND13 :1; + IO_BYTE _INTPND14 :1; + IO_BYTE _INTPND15 :1; + IO_BYTE _INTPND16 :1; + }bit; + }INTPND1H1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _INTPND17 :1; + IO_WORD _INTPND18 :1; + IO_WORD _INTPND19 :1; + IO_WORD _INTPND20 :1; + IO_WORD _INTPND21 :1; + IO_WORD _INTPND22 :1; + IO_WORD _INTPND23 :1; + IO_WORD _INTPND24 :1; + IO_WORD _INTPND25 :1; + IO_WORD _INTPND26 :1; + IO_WORD _INTPND27 :1; + IO_WORD _INTPND28 :1; + IO_WORD _INTPND29 :1; + IO_WORD _INTPND30 :1; + IO_WORD _INTPND31 :1; + IO_WORD _INTPND32 :1; + }bit; + }INTPND21STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INTPND17 :1; + IO_BYTE _INTPND18 :1; + IO_BYTE _INTPND19 :1; + IO_BYTE _INTPND20 :1; + IO_BYTE _INTPND21 :1; + IO_BYTE _INTPND22 :1; + IO_BYTE _INTPND23 :1; + IO_BYTE _INTPND24 :1; + }bit; + }INTPND2L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INTPND25 :1; + IO_BYTE _INTPND26 :1; + IO_BYTE _INTPND27 :1; + IO_BYTE _INTPND28 :1; + IO_BYTE _INTPND29 :1; + IO_BYTE _INTPND30 :1; + IO_BYTE _INTPND31 :1; + IO_BYTE _INTPND32 :1; + }bit; + }INTPND2H1STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _MSGVAL1 :1; + IO_LWORD _MSGVAL2 :1; + IO_LWORD _MSGVAL3 :1; + IO_LWORD _MSGVAL4 :1; + IO_LWORD _MSGVAL5 :1; + IO_LWORD _MSGVAL6 :1; + IO_LWORD _MSGVAL7 :1; + IO_LWORD _MSGVAL8 :1; + IO_LWORD _MSGVAL9 :1; + IO_LWORD _MSGVAL10 :1; + IO_LWORD _MSGVAL11 :1; + IO_LWORD _MSGVAL12 :1; + IO_LWORD _MSGVAL13 :1; + IO_LWORD _MSGVAL14 :1; + IO_LWORD _MSGVAL15 :1; + IO_LWORD _MSGVAL16 :1; + IO_LWORD _MSGVAL17 :1; + IO_LWORD _MSGVAL18 :1; + IO_LWORD _MSGVAL19 :1; + IO_LWORD _MSGVAL20 :1; + IO_LWORD _MSGVAL21 :1; + IO_LWORD _MSGVAL22 :1; + IO_LWORD _MSGVAL23 :1; + IO_LWORD _MSGVAL24 :1; + IO_LWORD _MSGVAL25 :1; + IO_LWORD _MSGVAL26 :1; + IO_LWORD _MSGVAL27 :1; + IO_LWORD _MSGVAL28 :1; + IO_LWORD _MSGVAL29 :1; + IO_LWORD _MSGVAL30 :1; + IO_LWORD _MSGVAL31 :1; + IO_LWORD _MSGVAL32 :1; + }bit; + struct{ + IO_LWORD _MSGVAL :32; + }bitc; + }MSGVAL1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _MSGVAL1 :1; + IO_WORD _MSGVAL2 :1; + IO_WORD _MSGVAL3 :1; + IO_WORD _MSGVAL4 :1; + IO_WORD _MSGVAL5 :1; + IO_WORD _MSGVAL6 :1; + IO_WORD _MSGVAL7 :1; + IO_WORD _MSGVAL8 :1; + IO_WORD _MSGVAL9 :1; + IO_WORD _MSGVAL10 :1; + IO_WORD _MSGVAL11 :1; + IO_WORD _MSGVAL12 :1; + IO_WORD _MSGVAL13 :1; + IO_WORD _MSGVAL14 :1; + IO_WORD _MSGVAL15 :1; + IO_WORD _MSGVAL16 :1; + }bit; + }MSGVAL11STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSGVAL1 :1; + IO_BYTE _MSGVAL2 :1; + IO_BYTE _MSGVAL3 :1; + IO_BYTE _MSGVAL4 :1; + IO_BYTE _MSGVAL5 :1; + IO_BYTE _MSGVAL6 :1; + IO_BYTE _MSGVAL7 :1; + IO_BYTE _MSGVAL8 :1; + }bit; + }MSGVAL1L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSGVAL9 :1; + IO_BYTE _MSGVAL10 :1; + IO_BYTE _MSGVAL11 :1; + IO_BYTE _MSGVAL12 :1; + IO_BYTE _MSGVAL13 :1; + IO_BYTE _MSGVAL14 :1; + IO_BYTE _MSGVAL15 :1; + IO_BYTE _MSGVAL16 :1; + }bit; + }MSGVAL1H1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _MSGVAL17 :1; + IO_WORD _MSGVAL18 :1; + IO_WORD _MSGVAL19 :1; + IO_WORD _MSGVAL20 :1; + IO_WORD _MSGVAL21 :1; + IO_WORD _MSGVAL22 :1; + IO_WORD _MSGVAL23 :1; + IO_WORD _MSGVAL24 :1; + IO_WORD _MSGVAL25 :1; + IO_WORD _MSGVAL26 :1; + IO_WORD _MSGVAL27 :1; + IO_WORD _MSGVAL28 :1; + IO_WORD _MSGVAL29 :1; + IO_WORD _MSGVAL30 :1; + IO_WORD _MSGVAL31 :1; + IO_WORD _MSGVAL32 :1; + }bit; + }MSGVAL21STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSGVAL17 :1; + IO_BYTE _MSGVAL18 :1; + IO_BYTE _MSGVAL19 :1; + IO_BYTE _MSGVAL20 :1; + IO_BYTE _MSGVAL21 :1; + IO_BYTE _MSGVAL22 :1; + IO_BYTE _MSGVAL23 :1; + IO_BYTE _MSGVAL24 :1; + }bit; + }MSGVAL2L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSGVAL25 :1; + IO_BYTE _MSGVAL26 :1; + IO_BYTE _MSGVAL27 :1; + IO_BYTE _MSGVAL28 :1; + IO_BYTE _MSGVAL29 :1; + IO_BYTE _MSGVAL30 :1; + IO_BYTE _MSGVAL31 :1; + IO_BYTE _MSGVAL32 :1; + }bit; + }MSGVAL2H1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }COER1STR; + +/* C-DECLARATIONS */ + +__IO_EXTERN __io PDR00STR _pdr00; +#define PDR00 _pdr00.byte +#define PDR00_P0 _pdr00.bit._P0 +#define PDR00_P1 _pdr00.bit._P1 +#define PDR00_P2 _pdr00.bit._P2 +#define PDR00_P3 _pdr00.bit._P3 +#define PDR00_P4 _pdr00.bit._P4 +#define PDR00_P5 _pdr00.bit._P5 +#define PDR00_P6 _pdr00.bit._P6 +#define PDR00_P7 _pdr00.bit._P7 +__IO_EXTERN __io PDR01STR _pdr01; +#define PDR01 _pdr01.byte +#define PDR01_P0 _pdr01.bit._P0 +#define PDR01_P1 _pdr01.bit._P1 +#define PDR01_P2 _pdr01.bit._P2 +#define PDR01_P3 _pdr01.bit._P3 +#define PDR01_P4 _pdr01.bit._P4 +#define PDR01_P5 _pdr01.bit._P5 +#define PDR01_P6 _pdr01.bit._P6 +#define PDR01_P7 _pdr01.bit._P7 +__IO_EXTERN __io PDR02STR _pdr02; +#define PDR02 _pdr02.byte +#define PDR02_P0 _pdr02.bit._P0 +#define PDR02_P1 _pdr02.bit._P1 +#define PDR02_P2 _pdr02.bit._P2 +#define PDR02_P3 _pdr02.bit._P3 +#define PDR02_P4 _pdr02.bit._P4 +#define PDR02_P5 _pdr02.bit._P5 +#define PDR02_P6 _pdr02.bit._P6 +#define PDR02_P7 _pdr02.bit._P7 +__IO_EXTERN __io PDR03STR _pdr03; +#define PDR03 _pdr03.byte +#define PDR03_P0 _pdr03.bit._P0 +#define PDR03_P1 _pdr03.bit._P1 +#define PDR03_P2 _pdr03.bit._P2 +#define PDR03_P3 _pdr03.bit._P3 +#define PDR03_P4 _pdr03.bit._P4 +#define PDR03_P5 _pdr03.bit._P5 +#define PDR03_P6 _pdr03.bit._P6 +#define PDR03_P7 _pdr03.bit._P7 +__IO_EXTERN __io PDR04STR _pdr04; +#define PDR04 _pdr04.byte +#define PDR04_P0 _pdr04.bit._P0 +#define PDR04_P1 _pdr04.bit._P1 +#define PDR04_P2 _pdr04.bit._P2 +#define PDR04_P3 _pdr04.bit._P3 +#define PDR04_P4 _pdr04.bit._P4 +#define PDR04_P5 _pdr04.bit._P5 +#define PDR04_P6 _pdr04.bit._P6 +#define PDR04_P7 _pdr04.bit._P7 +__IO_EXTERN __io PDR05STR _pdr05; +#define PDR05 _pdr05.byte +#define PDR05_P0 _pdr05.bit._P0 +#define PDR05_P1 _pdr05.bit._P1 +#define PDR05_P2 _pdr05.bit._P2 +#define PDR05_P3 _pdr05.bit._P3 +#define PDR05_P4 _pdr05.bit._P4 +#define PDR05_P5 _pdr05.bit._P5 +#define PDR05_P6 _pdr05.bit._P6 +#define PDR05_P7 _pdr05.bit._P7 +__IO_EXTERN __io PDR06STR _pdr06; +#define PDR06 _pdr06.byte +#define PDR06_P0 _pdr06.bit._P0 +#define PDR06_P1 _pdr06.bit._P1 +#define PDR06_P2 _pdr06.bit._P2 +#define PDR06_P3 _pdr06.bit._P3 +#define PDR06_P4 _pdr06.bit._P4 +#define PDR06_P5 _pdr06.bit._P5 +#define PDR06_P6 _pdr06.bit._P6 +#define PDR06_P7 _pdr06.bit._P7 +__IO_EXTERN __io PDR07STR _pdr07; +#define PDR07 _pdr07.byte +#define PDR07_P0 _pdr07.bit._P0 +#define PDR07_P1 _pdr07.bit._P1 +#define PDR07_P2 _pdr07.bit._P2 +#define PDR07_P3 _pdr07.bit._P3 +#define PDR07_P4 _pdr07.bit._P4 +#define PDR07_P5 _pdr07.bit._P5 +#define PDR07_P6 _pdr07.bit._P6 +#define PDR07_P7 _pdr07.bit._P7 +__IO_EXTERN __io PDR08STR _pdr08; +#define PDR08 _pdr08.byte +#define PDR08_P0 _pdr08.bit._P0 +#define PDR08_P1 _pdr08.bit._P1 +#define PDR08_P2 _pdr08.bit._P2 +#define PDR08_P3 _pdr08.bit._P3 +#define PDR08_P4 _pdr08.bit._P4 +#define PDR08_P5 _pdr08.bit._P5 +#define PDR08_P6 _pdr08.bit._P6 +#define PDR08_P7 _pdr08.bit._P7 +__IO_EXTERN __io PDR09STR _pdr09; +#define PDR09 _pdr09.byte +#define PDR09_P0 _pdr09.bit._P0 +#define PDR09_P1 _pdr09.bit._P1 +#define PDR09_P2 _pdr09.bit._P2 +#define PDR09_P3 _pdr09.bit._P3 +#define PDR09_P4 _pdr09.bit._P4 +#define PDR09_P5 _pdr09.bit._P5 +#define PDR09_P6 _pdr09.bit._P6 +#define PDR09_P7 _pdr09.bit._P7 +__IO_EXTERN __io PDR10STR _pdr10; +#define PDR10 _pdr10.byte +#define PDR10_P0 _pdr10.bit._P0 +#define PDR10_P1 _pdr10.bit._P1 +__IO_EXTERN __io ADCSSTR _adcs; +#define ADCS _adcs.word +#define ADCS_resv _adcs.bit._resv +#define ADCS_S10 _adcs.bit._S10 +#define ADCS_MD0 _adcs.bit._MD0 +#define ADCS_MD1 _adcs.bit._MD1 +#define ADCS_STRT _adcs.bit._STRT +#define ADCS_STS0 _adcs.bit._STS0 +#define ADCS_STS1 _adcs.bit._STS1 +#define ADCS_PAUS _adcs.bit._PAUS +#define ADCS_INTE _adcs.bit._INTE +#define ADCS_INT _adcs.bit._INT +#define ADCS_BUSY _adcs.bit._BUSY +#define ADCS_MD _adcs.bitc._MD +#define ADCS_STS _adcs.bitc._STS +__IO_EXTERN __io ADCSLSTR _adcsl; +#define ADCSL _adcsl.byte +#define ADCSL_resv _adcsl.bit._resv +#define ADCSL_S10 _adcsl.bit._S10 +#define ADCSL_MD0 _adcsl.bit._MD0 +#define ADCSL_MD1 _adcsl.bit._MD1 +#define ADCSL_MD _adcsl.bitc._MD +__IO_EXTERN __io ADCSHSTR _adcsh; +#define ADCSH _adcsh.byte +#define ADCSH_STRT _adcsh.bit._STRT +#define ADCSH_STS0 _adcsh.bit._STS0 +#define ADCSH_STS1 _adcsh.bit._STS1 +#define ADCSH_PAUS _adcsh.bit._PAUS +#define ADCSH_INTE _adcsh.bit._INTE +#define ADCSH_INT _adcsh.bit._INT +#define ADCSH_BUSY _adcsh.bit._BUSY +#define ADCSH_STS _adcsh.bitc._STS +__IO_EXTERN __io ADCRSTR _adcr; +#define ADCR _adcr.word +#define ADCR_D0 _adcr.bit._D0 +#define ADCR_D1 _adcr.bit._D1 +#define ADCR_D2 _adcr.bit._D2 +#define ADCR_D3 _adcr.bit._D3 +#define ADCR_D4 _adcr.bit._D4 +#define ADCR_D5 _adcr.bit._D5 +#define ADCR_D6 _adcr.bit._D6 +#define ADCR_D7 _adcr.bit._D7 +#define ADCR_D8 _adcr.bit._D8 +#define ADCR_D9 _adcr.bit._D9 +#define ADCR_D _adcr.bitc._D +__IO_EXTERN __io ADCRLSTR _adcrl; +#define ADCRL _adcrl.byte +#define ADCRL_D0 _adcrl.bit._D0 +#define ADCRL_D1 _adcrl.bit._D1 +#define ADCRL_D2 _adcrl.bit._D2 +#define ADCRL_D3 _adcrl.bit._D3 +#define ADCRL_D4 _adcrl.bit._D4 +#define ADCRL_D5 _adcrl.bit._D5 +#define ADCRL_D6 _adcrl.bit._D6 +#define ADCRL_D7 _adcrl.bit._D7 +__IO_EXTERN __io ADCRHSTR _adcrh; +#define ADCRH _adcrh.byte +#define ADCRH_D8 _adcrh.bit._D8 +#define ADCRH_D9 _adcrh.bit._D9 +__IO_EXTERN __io ADSRSTR _adsr; +#define ADSR _adsr.word +#define ADSR_ANE0 _adsr.bit._ANE0 +#define ADSR_ANE1 _adsr.bit._ANE1 +#define ADSR_ANE2 _adsr.bit._ANE2 +#define ADSR_ANE3 _adsr.bit._ANE3 +#define ADSR_ANE4 _adsr.bit._ANE4 +#define ADSR_ANS0 _adsr.bit._ANS0 +#define ADSR_ANS1 _adsr.bit._ANS1 +#define ADSR_ANS2 _adsr.bit._ANS2 +#define ADSR_ANS3 _adsr.bit._ANS3 +#define ADSR_ANS4 _adsr.bit._ANS4 +#define ADSR_CT0 _adsr.bit._CT0 +#define ADSR_CT1 _adsr.bit._CT1 +#define ADSR_CT2 _adsr.bit._CT2 +#define ADSR_ST0 _adsr.bit._ST0 +#define ADSR_ST1 _adsr.bit._ST1 +#define ADSR_ST2 _adsr.bit._ST2 +__IO_EXTERN __io ADECRSTR _adecr; +#define ADECR _adecr.byte +#define ADECR_ADSEL _adecr.bit._ADSEL +#define ADECR_HSEL _adecr.bit._HSEL +#define ADECR_LSEL _adecr.bit._LSEL +__IO_EXTERN __io TCDT0STR _tcdt0; +#define TCDT0 _tcdt0.word +#define TCDT0_T0 _tcdt0.bit._T0 +#define TCDT0_T1 _tcdt0.bit._T1 +#define TCDT0_T2 _tcdt0.bit._T2 +#define TCDT0_T3 _tcdt0.bit._T3 +#define TCDT0_T4 _tcdt0.bit._T4 +#define TCDT0_T5 _tcdt0.bit._T5 +#define TCDT0_T6 _tcdt0.bit._T6 +#define TCDT0_T7 _tcdt0.bit._T7 +#define TCDT0_T8 _tcdt0.bit._T8 +#define TCDT0_T9 _tcdt0.bit._T9 +#define TCDT0_T10 _tcdt0.bit._T10 +#define TCDT0_T11 _tcdt0.bit._T11 +#define TCDT0_T12 _tcdt0.bit._T12 +#define TCDT0_T13 _tcdt0.bit._T13 +#define TCDT0_T14 _tcdt0.bit._T14 +#define TCDT0_T15 _tcdt0.bit._T15 +#define TCDT0_T _tcdt0.bitc._T +__IO_EXTERN __io TCCS0STR _tccs0; +#define TCCS0 _tccs0.word +#define TCCS0_CLK0 _tccs0.bit._CLK0 +#define TCCS0_CLK1 _tccs0.bit._CLK1 +#define TCCS0_CLK2 _tccs0.bit._CLK2 +#define TCCS0_CLR _tccs0.bit._CLR +#define TCCS0_MODE _tccs0.bit._MODE +#define TCCS0_STOP _tccs0.bit._STOP +#define TCCS0_IVFE _tccs0.bit._IVFE +#define TCCS0_IVF _tccs0.bit._IVF +#define TCCS0_FSEL _tccs0.bit._FSEL +#define TCCS0_ECKE _tccs0.bit._ECKE +#define TCCS0_CLK _tccs0.bitc._CLK +__IO_EXTERN __io TCCSL0STR _tccsl0; +#define TCCSL0 _tccsl0.byte +#define TCCSL0_CLK0 _tccsl0.bit._CLK0 +#define TCCSL0_CLK1 _tccsl0.bit._CLK1 +#define TCCSL0_CLK2 _tccsl0.bit._CLK2 +#define TCCSL0_CLR _tccsl0.bit._CLR +#define TCCSL0_MODE _tccsl0.bit._MODE +#define TCCSL0_STOP _tccsl0.bit._STOP +#define TCCSL0_IVFE _tccsl0.bit._IVFE +#define TCCSL0_IVF _tccsl0.bit._IVF +#define TCCSL0_CLK _tccsl0.bitc._CLK +__IO_EXTERN __io TCCSH0STR _tccsh0; +#define TCCSH0 _tccsh0.byte +#define TCCSH0_FSEL _tccsh0.bit._FSEL +#define TCCSH0_ECKE _tccsh0.bit._ECKE +__IO_EXTERN __io TCDT1STR _tcdt1; +#define TCDT1 _tcdt1.word +#define TCDT1_T0 _tcdt1.bit._T0 +#define TCDT1_T1 _tcdt1.bit._T1 +#define TCDT1_T2 _tcdt1.bit._T2 +#define TCDT1_T3 _tcdt1.bit._T3 +#define TCDT1_T4 _tcdt1.bit._T4 +#define TCDT1_T5 _tcdt1.bit._T5 +#define TCDT1_T6 _tcdt1.bit._T6 +#define TCDT1_T7 _tcdt1.bit._T7 +#define TCDT1_T8 _tcdt1.bit._T8 +#define TCDT1_T9 _tcdt1.bit._T9 +#define TCDT1_T10 _tcdt1.bit._T10 +#define TCDT1_T11 _tcdt1.bit._T11 +#define TCDT1_T12 _tcdt1.bit._T12 +#define TCDT1_T13 _tcdt1.bit._T13 +#define TCDT1_T14 _tcdt1.bit._T14 +#define TCDT1_T15 _tcdt1.bit._T15 +#define TCDT1_T _tcdt1.bitc._T +__IO_EXTERN __io TCCS1STR _tccs1; +#define TCCS1 _tccs1.word +#define TCCS1_CLK0 _tccs1.bit._CLK0 +#define TCCS1_CLK1 _tccs1.bit._CLK1 +#define TCCS1_CLK2 _tccs1.bit._CLK2 +#define TCCS1_CLR _tccs1.bit._CLR +#define TCCS1_MODE _tccs1.bit._MODE +#define TCCS1_STOP _tccs1.bit._STOP +#define TCCS1_IVFE _tccs1.bit._IVFE +#define TCCS1_IVF _tccs1.bit._IVF +#define TCCS1_FSEL _tccs1.bit._FSEL +#define TCCS1_ECKE _tccs1.bit._ECKE +#define TCCS1_CLK _tccs1.bitc._CLK +__IO_EXTERN __io TCCSL1STR _tccsl1; +#define TCCSL1 _tccsl1.byte +#define TCCSL1_CLK0 _tccsl1.bit._CLK0 +#define TCCSL1_CLK1 _tccsl1.bit._CLK1 +#define TCCSL1_CLK2 _tccsl1.bit._CLK2 +#define TCCSL1_CLR _tccsl1.bit._CLR +#define TCCSL1_MODE _tccsl1.bit._MODE +#define TCCSL1_STOP _tccsl1.bit._STOP +#define TCCSL1_IVFE _tccsl1.bit._IVFE +#define TCCSL1_IVF _tccsl1.bit._IVF +#define TCCSL1_CLK _tccsl1.bitc._CLK +__IO_EXTERN __io TCCSH1STR _tccsh1; +#define TCCSH1 _tccsh1.byte +#define TCCSH1_FSEL _tccsh1.bit._FSEL +#define TCCSH1_ECKE _tccsh1.bit._ECKE +__IO_EXTERN __io OCS0STR _ocs0; +#define OCS0 _ocs0.byte +#define OCS0_CST0 _ocs0.bit._CST0 +#define OCS0_CST1 _ocs0.bit._CST1 +#define OCS0_ICE0 _ocs0.bit._ICE0 +#define OCS0_ICE1 _ocs0.bit._ICE1 +#define OCS0_ICP0 _ocs0.bit._ICP0 +#define OCS0_ICP1 _ocs0.bit._ICP1 +__IO_EXTERN __io OCS1STR _ocs1; +#define OCS1 _ocs1.byte +#define OCS1_OTD0 _ocs1.bit._OTD0 +#define OCS1_OTD1 _ocs1.bit._OTD1 +#define OCS1_OTE0 _ocs1.bit._OTE0 +#define OCS1_OTE1 _ocs1.bit._OTE1 +#define OCS1_CMOD0 _ocs1.bit._CMOD0 +#define OCS1_CMOD1 _ocs1.bit._CMOD1 +__IO_EXTERN __io OCCP0STR _occp0; +#define OCCP0 _occp0.word +#define OCCP0_C00 _occp0.bit._C00 +#define OCCP0_C01 _occp0.bit._C01 +#define OCCP0_C02 _occp0.bit._C02 +#define OCCP0_C03 _occp0.bit._C03 +#define OCCP0_C04 _occp0.bit._C04 +#define OCCP0_C05 _occp0.bit._C05 +#define OCCP0_C06 _occp0.bit._C06 +#define OCCP0_C07 _occp0.bit._C07 +#define OCCP0_C08 _occp0.bit._C08 +#define OCCP0_C09 _occp0.bit._C09 +#define OCCP0_C10 _occp0.bit._C10 +#define OCCP0_C11 _occp0.bit._C11 +#define OCCP0_C12 _occp0.bit._C12 +#define OCCP0_C13 _occp0.bit._C13 +#define OCCP0_C14 _occp0.bit._C14 +#define OCCP0_C15 _occp0.bit._C15 +#define OCCP0_C0 _occp0.bitc._C0 +__IO_EXTERN __io OCCP1STR _occp1; +#define OCCP1 _occp1.word +#define OCCP1_C00 _occp1.bit._C00 +#define OCCP1_C01 _occp1.bit._C01 +#define OCCP1_C02 _occp1.bit._C02 +#define OCCP1_C03 _occp1.bit._C03 +#define OCCP1_C04 _occp1.bit._C04 +#define OCCP1_C05 _occp1.bit._C05 +#define OCCP1_C06 _occp1.bit._C06 +#define OCCP1_C07 _occp1.bit._C07 +#define OCCP1_C08 _occp1.bit._C08 +#define OCCP1_C09 _occp1.bit._C09 +#define OCCP1_C10 _occp1.bit._C10 +#define OCCP1_C11 _occp1.bit._C11 +#define OCCP1_C12 _occp1.bit._C12 +#define OCCP1_C13 _occp1.bit._C13 +#define OCCP1_C14 _occp1.bit._C14 +#define OCCP1_C15 _occp1.bit._C15 +#define OCCP1_C0 _occp1.bitc._C0 +__IO_EXTERN __io OCS2STR _ocs2; +#define OCS2 _ocs2.byte +#define OCS2_CST2 _ocs2.bit._CST2 +#define OCS2_CST3 _ocs2.bit._CST3 +#define OCS2_ICE2 _ocs2.bit._ICE2 +#define OCS2_ICE3 _ocs2.bit._ICE3 +#define OCS2_ICP2 _ocs2.bit._ICP2 +#define OCS2_ICP3 _ocs2.bit._ICP3 +__IO_EXTERN __io OCS3STR _ocs3; +#define OCS3 _ocs3.byte +#define OCS3_OTD2 _ocs3.bit._OTD2 +#define OCS3_OTD3 _ocs3.bit._OTD3 +#define OCS3_OTE2 _ocs3.bit._OTE2 +#define OCS3_OTE3 _ocs3.bit._OTE3 +#define OCS3_CMOD0 _ocs3.bit._CMOD0 +#define OCS3_CMOD1 _ocs3.bit._CMOD1 +__IO_EXTERN __io OCCP2STR _occp2; +#define OCCP2 _occp2.word +#define OCCP2_C00 _occp2.bit._C00 +#define OCCP2_C01 _occp2.bit._C01 +#define OCCP2_C02 _occp2.bit._C02 +#define OCCP2_C03 _occp2.bit._C03 +#define OCCP2_C04 _occp2.bit._C04 +#define OCCP2_C05 _occp2.bit._C05 +#define OCCP2_C06 _occp2.bit._C06 +#define OCCP2_C07 _occp2.bit._C07 +#define OCCP2_C08 _occp2.bit._C08 +#define OCCP2_C09 _occp2.bit._C09 +#define OCCP2_C10 _occp2.bit._C10 +#define OCCP2_C11 _occp2.bit._C11 +#define OCCP2_C12 _occp2.bit._C12 +#define OCCP2_C13 _occp2.bit._C13 +#define OCCP2_C14 _occp2.bit._C14 +#define OCCP2_C15 _occp2.bit._C15 +#define OCCP2_C0 _occp2.bitc._C0 +__IO_EXTERN __io OCCP3STR _occp3; +#define OCCP3 _occp3.word +#define OCCP3_C00 _occp3.bit._C00 +#define OCCP3_C01 _occp3.bit._C01 +#define OCCP3_C02 _occp3.bit._C02 +#define OCCP3_C03 _occp3.bit._C03 +#define OCCP3_C04 _occp3.bit._C04 +#define OCCP3_C05 _occp3.bit._C05 +#define OCCP3_C06 _occp3.bit._C06 +#define OCCP3_C07 _occp3.bit._C07 +#define OCCP3_C08 _occp3.bit._C08 +#define OCCP3_C09 _occp3.bit._C09 +#define OCCP3_C10 _occp3.bit._C10 +#define OCCP3_C11 _occp3.bit._C11 +#define OCCP3_C12 _occp3.bit._C12 +#define OCCP3_C13 _occp3.bit._C13 +#define OCCP3_C14 _occp3.bit._C14 +#define OCCP3_C15 _occp3.bit._C15 +#define OCCP3_C0 _occp3.bitc._C0 +__IO_EXTERN __io OCS4STR _ocs4; +#define OCS4 _ocs4.byte +#define OCS4_CST4 _ocs4.bit._CST4 +#define OCS4_CST5 _ocs4.bit._CST5 +#define OCS4_ICE4 _ocs4.bit._ICE4 +#define OCS4_ICE5 _ocs4.bit._ICE5 +#define OCS4_ICP4 _ocs4.bit._ICP4 +#define OCS4_ICP5 _ocs4.bit._ICP5 +__IO_EXTERN __io OCS5STR _ocs5; +#define OCS5 _ocs5.byte +#define OCS5_OTD4 _ocs5.bit._OTD4 +#define OCS5_OTD5 _ocs5.bit._OTD5 +#define OCS5_OTE4 _ocs5.bit._OTE4 +#define OCS5_OTE5 _ocs5.bit._OTE5 +#define OCS5_CMOD0 _ocs5.bit._CMOD0 +#define OCS5_CMOD1 _ocs5.bit._CMOD1 +__IO_EXTERN __io OCCP4STR _occp4; +#define OCCP4 _occp4.word +#define OCCP4_C00 _occp4.bit._C00 +#define OCCP4_C01 _occp4.bit._C01 +#define OCCP4_C02 _occp4.bit._C02 +#define OCCP4_C03 _occp4.bit._C03 +#define OCCP4_C04 _occp4.bit._C04 +#define OCCP4_C05 _occp4.bit._C05 +#define OCCP4_C06 _occp4.bit._C06 +#define OCCP4_C07 _occp4.bit._C07 +#define OCCP4_C08 _occp4.bit._C08 +#define OCCP4_C09 _occp4.bit._C09 +#define OCCP4_C10 _occp4.bit._C10 +#define OCCP4_C11 _occp4.bit._C11 +#define OCCP4_C12 _occp4.bit._C12 +#define OCCP4_C13 _occp4.bit._C13 +#define OCCP4_C14 _occp4.bit._C14 +#define OCCP4_C15 _occp4.bit._C15 +#define OCCP4_C0 _occp4.bitc._C0 +__IO_EXTERN __io OCCP5STR _occp5; +#define OCCP5 _occp5.word +#define OCCP5_C00 _occp5.bit._C00 +#define OCCP5_C01 _occp5.bit._C01 +#define OCCP5_C02 _occp5.bit._C02 +#define OCCP5_C03 _occp5.bit._C03 +#define OCCP5_C04 _occp5.bit._C04 +#define OCCP5_C05 _occp5.bit._C05 +#define OCCP5_C06 _occp5.bit._C06 +#define OCCP5_C07 _occp5.bit._C07 +#define OCCP5_C08 _occp5.bit._C08 +#define OCCP5_C09 _occp5.bit._C09 +#define OCCP5_C10 _occp5.bit._C10 +#define OCCP5_C11 _occp5.bit._C11 +#define OCCP5_C12 _occp5.bit._C12 +#define OCCP5_C13 _occp5.bit._C13 +#define OCCP5_C14 _occp5.bit._C14 +#define OCCP5_C15 _occp5.bit._C15 +#define OCCP5_C0 _occp5.bitc._C0 +__IO_EXTERN __io OCS6STR _ocs6; +#define OCS6 _ocs6.byte +#define OCS6_CST6 _ocs6.bit._CST6 +#define OCS6_CST7 _ocs6.bit._CST7 +#define OCS6_ICE6 _ocs6.bit._ICE6 +#define OCS6_ICE7 _ocs6.bit._ICE7 +#define OCS6_ICP6 _ocs6.bit._ICP6 +#define OCS6_ICP7 _ocs6.bit._ICP7 +__IO_EXTERN __io OCS7STR _ocs7; +#define OCS7 _ocs7.byte +#define OCS7_OTD6 _ocs7.bit._OTD6 +#define OCS7_OTD7 _ocs7.bit._OTD7 +#define OCS7_OTE6 _ocs7.bit._OTE6 +#define OCS7_OTE7 _ocs7.bit._OTE7 +#define OCS7_CMOD0 _ocs7.bit._CMOD0 +#define OCS7_CMOD1 _ocs7.bit._CMOD1 +__IO_EXTERN __io OCCP6STR _occp6; +#define OCCP6 _occp6.word +#define OCCP6_C00 _occp6.bit._C00 +#define OCCP6_C01 _occp6.bit._C01 +#define OCCP6_C02 _occp6.bit._C02 +#define OCCP6_C03 _occp6.bit._C03 +#define OCCP6_C04 _occp6.bit._C04 +#define OCCP6_C05 _occp6.bit._C05 +#define OCCP6_C06 _occp6.bit._C06 +#define OCCP6_C07 _occp6.bit._C07 +#define OCCP6_C08 _occp6.bit._C08 +#define OCCP6_C09 _occp6.bit._C09 +#define OCCP6_C10 _occp6.bit._C10 +#define OCCP6_C11 _occp6.bit._C11 +#define OCCP6_C12 _occp6.bit._C12 +#define OCCP6_C13 _occp6.bit._C13 +#define OCCP6_C14 _occp6.bit._C14 +#define OCCP6_C15 _occp6.bit._C15 +#define OCCP6_C0 _occp6.bitc._C0 +__IO_EXTERN __io OCCP7STR _occp7; +#define OCCP7 _occp7.word +#define OCCP7_C00 _occp7.bit._C00 +#define OCCP7_C01 _occp7.bit._C01 +#define OCCP7_C02 _occp7.bit._C02 +#define OCCP7_C03 _occp7.bit._C03 +#define OCCP7_C04 _occp7.bit._C04 +#define OCCP7_C05 _occp7.bit._C05 +#define OCCP7_C06 _occp7.bit._C06 +#define OCCP7_C07 _occp7.bit._C07 +#define OCCP7_C08 _occp7.bit._C08 +#define OCCP7_C09 _occp7.bit._C09 +#define OCCP7_C10 _occp7.bit._C10 +#define OCCP7_C11 _occp7.bit._C11 +#define OCCP7_C12 _occp7.bit._C12 +#define OCCP7_C13 _occp7.bit._C13 +#define OCCP7_C14 _occp7.bit._C14 +#define OCCP7_C15 _occp7.bit._C15 +#define OCCP7_C0 _occp7.bitc._C0 +__IO_EXTERN __io ICS01STR _ics01; +#define ICS01 _ics01.byte +#define ICS01_EG00 _ics01.bit._EG00 +#define ICS01_EG01 _ics01.bit._EG01 +#define ICS01_EG10 _ics01.bit._EG10 +#define ICS01_EG11 _ics01.bit._EG11 +#define ICS01_ICE0 _ics01.bit._ICE0 +#define ICS01_ICE1 _ics01.bit._ICE1 +#define ICS01_ICP0 _ics01.bit._ICP0 +#define ICS01_ICP1 _ics01.bit._ICP1 +#define ICS01_EG0 _ics01.bitc._EG0 +#define ICS01_EG1 _ics01.bitc._EG1 +__IO_EXTERN __io ICE01STR _ice01; +#define ICE01 _ice01.byte +#define ICE01_IEI0 _ice01.bit._IEI0 +#define ICE01_IEI1 _ice01.bit._IEI1 +#define ICE01_ICUS0 _ice01.bit._ICUS0 +#define ICE01_ICUS1 _ice01.bit._ICUS1 +__IO_EXTERN __io IPCP0STR _ipcp0; +#define IPCP0 _ipcp0.word +#define IPCP0_CP00 _ipcp0.bit._CP00 +#define IPCP0_CP01 _ipcp0.bit._CP01 +#define IPCP0_CP02 _ipcp0.bit._CP02 +#define IPCP0_CP03 _ipcp0.bit._CP03 +#define IPCP0_CP04 _ipcp0.bit._CP04 +#define IPCP0_CP05 _ipcp0.bit._CP05 +#define IPCP0_CP06 _ipcp0.bit._CP06 +#define IPCP0_CP07 _ipcp0.bit._CP07 +#define IPCP0_CP08 _ipcp0.bit._CP08 +#define IPCP0_CP09 _ipcp0.bit._CP09 +#define IPCP0_CP10 _ipcp0.bit._CP10 +#define IPCP0_CP11 _ipcp0.bit._CP11 +#define IPCP0_CP12 _ipcp0.bit._CP12 +#define IPCP0_CP13 _ipcp0.bit._CP13 +#define IPCP0_CP14 _ipcp0.bit._CP14 +#define IPCP0_CP15 _ipcp0.bit._CP15 +#define IPCP0_CP0 _ipcp0.bitc._CP0 +__IO_EXTERN __io IPCPL0STR _ipcpl0; +#define IPCPL0 _ipcpl0.byte +#define IPCPL0_CP00 _ipcpl0.bit._CP00 +#define IPCPL0_CP01 _ipcpl0.bit._CP01 +#define IPCPL0_CP02 _ipcpl0.bit._CP02 +#define IPCPL0_CP03 _ipcpl0.bit._CP03 +#define IPCPL0_CP04 _ipcpl0.bit._CP04 +#define IPCPL0_CP05 _ipcpl0.bit._CP05 +#define IPCPL0_CP06 _ipcpl0.bit._CP06 +#define IPCPL0_CP07 _ipcpl0.bit._CP07 +__IO_EXTERN __io IPCPH0STR _ipcph0; +#define IPCPH0 _ipcph0.byte +#define IPCPH0_CP08 _ipcph0.bit._CP08 +#define IPCPH0_CP09 _ipcph0.bit._CP09 +#define IPCPH0_CP10 _ipcph0.bit._CP10 +#define IPCPH0_CP11 _ipcph0.bit._CP11 +#define IPCPH0_CP12 _ipcph0.bit._CP12 +#define IPCPH0_CP13 _ipcph0.bit._CP13 +#define IPCPH0_CP14 _ipcph0.bit._CP14 +#define IPCPH0_CP15 _ipcph0.bit._CP15 +__IO_EXTERN __io IPCP1STR _ipcp1; +#define IPCP1 _ipcp1.word +#define IPCP1_CP00 _ipcp1.bit._CP00 +#define IPCP1_CP01 _ipcp1.bit._CP01 +#define IPCP1_CP02 _ipcp1.bit._CP02 +#define IPCP1_CP03 _ipcp1.bit._CP03 +#define IPCP1_CP04 _ipcp1.bit._CP04 +#define IPCP1_CP05 _ipcp1.bit._CP05 +#define IPCP1_CP06 _ipcp1.bit._CP06 +#define IPCP1_CP07 _ipcp1.bit._CP07 +#define IPCP1_CP08 _ipcp1.bit._CP08 +#define IPCP1_CP09 _ipcp1.bit._CP09 +#define IPCP1_CP10 _ipcp1.bit._CP10 +#define IPCP1_CP11 _ipcp1.bit._CP11 +#define IPCP1_CP12 _ipcp1.bit._CP12 +#define IPCP1_CP13 _ipcp1.bit._CP13 +#define IPCP1_CP14 _ipcp1.bit._CP14 +#define IPCP1_CP15 _ipcp1.bit._CP15 +#define IPCP1_CP0 _ipcp1.bitc._CP0 +__IO_EXTERN __io IPCPL1STR _ipcpl1; +#define IPCPL1 _ipcpl1.byte +#define IPCPL1_CP00 _ipcpl1.bit._CP00 +#define IPCPL1_CP01 _ipcpl1.bit._CP01 +#define IPCPL1_CP02 _ipcpl1.bit._CP02 +#define IPCPL1_CP03 _ipcpl1.bit._CP03 +#define IPCPL1_CP04 _ipcpl1.bit._CP04 +#define IPCPL1_CP05 _ipcpl1.bit._CP05 +#define IPCPL1_CP06 _ipcpl1.bit._CP06 +#define IPCPL1_CP07 _ipcpl1.bit._CP07 +__IO_EXTERN __io IPCPH1STR _ipcph1; +#define IPCPH1 _ipcph1.byte +#define IPCPH1_CP08 _ipcph1.bit._CP08 +#define IPCPH1_CP09 _ipcph1.bit._CP09 +#define IPCPH1_CP10 _ipcph1.bit._CP10 +#define IPCPH1_CP11 _ipcph1.bit._CP11 +#define IPCPH1_CP12 _ipcph1.bit._CP12 +#define IPCPH1_CP13 _ipcph1.bit._CP13 +#define IPCPH1_CP14 _ipcph1.bit._CP14 +#define IPCPH1_CP15 _ipcph1.bit._CP15 +__IO_EXTERN __io ICS23STR _ics23; +#define ICS23 _ics23.byte +#define ICS23_EG20 _ics23.bit._EG20 +#define ICS23_EG21 _ics23.bit._EG21 +#define ICS23_EG30 _ics23.bit._EG30 +#define ICS23_EG31 _ics23.bit._EG31 +#define ICS23_ICE2 _ics23.bit._ICE2 +#define ICS23_ICE3 _ics23.bit._ICE3 +#define ICS23_ICP2 _ics23.bit._ICP2 +#define ICS23_ICP3 _ics23.bit._ICP3 +#define ICS23_EG2 _ics23.bitc._EG2 +#define ICS23_EG3 _ics23.bitc._EG3 +__IO_EXTERN __io ICE23STR _ice23; +#define ICE23 _ice23.byte +#define ICE23_IEI2 _ice23.bit._IEI2 +#define ICE23_IEI3 _ice23.bit._IEI3 +__IO_EXTERN __io IPCP2STR _ipcp2; +#define IPCP2 _ipcp2.word +#define IPCP2_CP00 _ipcp2.bit._CP00 +#define IPCP2_CP01 _ipcp2.bit._CP01 +#define IPCP2_CP02 _ipcp2.bit._CP02 +#define IPCP2_CP03 _ipcp2.bit._CP03 +#define IPCP2_CP04 _ipcp2.bit._CP04 +#define IPCP2_CP05 _ipcp2.bit._CP05 +#define IPCP2_CP06 _ipcp2.bit._CP06 +#define IPCP2_CP07 _ipcp2.bit._CP07 +#define IPCP2_CP08 _ipcp2.bit._CP08 +#define IPCP2_CP09 _ipcp2.bit._CP09 +#define IPCP2_CP10 _ipcp2.bit._CP10 +#define IPCP2_CP11 _ipcp2.bit._CP11 +#define IPCP2_CP12 _ipcp2.bit._CP12 +#define IPCP2_CP13 _ipcp2.bit._CP13 +#define IPCP2_CP14 _ipcp2.bit._CP14 +#define IPCP2_CP15 _ipcp2.bit._CP15 +#define IPCP2_CP0 _ipcp2.bitc._CP0 +__IO_EXTERN __io IPCPL2STR _ipcpl2; +#define IPCPL2 _ipcpl2.byte +#define IPCPL2_CP00 _ipcpl2.bit._CP00 +#define IPCPL2_CP01 _ipcpl2.bit._CP01 +#define IPCPL2_CP02 _ipcpl2.bit._CP02 +#define IPCPL2_CP03 _ipcpl2.bit._CP03 +#define IPCPL2_CP04 _ipcpl2.bit._CP04 +#define IPCPL2_CP05 _ipcpl2.bit._CP05 +#define IPCPL2_CP06 _ipcpl2.bit._CP06 +#define IPCPL2_CP07 _ipcpl2.bit._CP07 +__IO_EXTERN __io IPCPH2STR _ipcph2; +#define IPCPH2 _ipcph2.byte +#define IPCPH2_CP08 _ipcph2.bit._CP08 +#define IPCPH2_CP09 _ipcph2.bit._CP09 +#define IPCPH2_CP10 _ipcph2.bit._CP10 +#define IPCPH2_CP11 _ipcph2.bit._CP11 +#define IPCPH2_CP12 _ipcph2.bit._CP12 +#define IPCPH2_CP13 _ipcph2.bit._CP13 +#define IPCPH2_CP14 _ipcph2.bit._CP14 +#define IPCPH2_CP15 _ipcph2.bit._CP15 +__IO_EXTERN __io IPCP3STR _ipcp3; +#define IPCP3 _ipcp3.word +#define IPCP3_CP00 _ipcp3.bit._CP00 +#define IPCP3_CP01 _ipcp3.bit._CP01 +#define IPCP3_CP02 _ipcp3.bit._CP02 +#define IPCP3_CP03 _ipcp3.bit._CP03 +#define IPCP3_CP04 _ipcp3.bit._CP04 +#define IPCP3_CP05 _ipcp3.bit._CP05 +#define IPCP3_CP06 _ipcp3.bit._CP06 +#define IPCP3_CP07 _ipcp3.bit._CP07 +#define IPCP3_CP08 _ipcp3.bit._CP08 +#define IPCP3_CP09 _ipcp3.bit._CP09 +#define IPCP3_CP10 _ipcp3.bit._CP10 +#define IPCP3_CP11 _ipcp3.bit._CP11 +#define IPCP3_CP12 _ipcp3.bit._CP12 +#define IPCP3_CP13 _ipcp3.bit._CP13 +#define IPCP3_CP14 _ipcp3.bit._CP14 +#define IPCP3_CP15 _ipcp3.bit._CP15 +#define IPCP3_CP0 _ipcp3.bitc._CP0 +__IO_EXTERN __io IPCPL3STR _ipcpl3; +#define IPCPL3 _ipcpl3.byte +#define IPCPL3_CP00 _ipcpl3.bit._CP00 +#define IPCPL3_CP01 _ipcpl3.bit._CP01 +#define IPCPL3_CP02 _ipcpl3.bit._CP02 +#define IPCPL3_CP03 _ipcpl3.bit._CP03 +#define IPCPL3_CP04 _ipcpl3.bit._CP04 +#define IPCPL3_CP05 _ipcpl3.bit._CP05 +#define IPCPL3_CP06 _ipcpl3.bit._CP06 +#define IPCPL3_CP07 _ipcpl3.bit._CP07 +__IO_EXTERN __io IPCPH3STR _ipcph3; +#define IPCPH3 _ipcph3.byte +#define IPCPH3_CP08 _ipcph3.bit._CP08 +#define IPCPH3_CP09 _ipcph3.bit._CP09 +#define IPCPH3_CP10 _ipcph3.bit._CP10 +#define IPCPH3_CP11 _ipcph3.bit._CP11 +#define IPCPH3_CP12 _ipcph3.bit._CP12 +#define IPCPH3_CP13 _ipcph3.bit._CP13 +#define IPCPH3_CP14 _ipcph3.bit._CP14 +#define IPCPH3_CP15 _ipcph3.bit._CP15 +__IO_EXTERN __io ICS45STR _ics45; +#define ICS45 _ics45.byte +#define ICS45_EG40 _ics45.bit._EG40 +#define ICS45_EG41 _ics45.bit._EG41 +#define ICS45_EG50 _ics45.bit._EG50 +#define ICS45_EG51 _ics45.bit._EG51 +#define ICS45_ICE4 _ics45.bit._ICE4 +#define ICS45_ICE5 _ics45.bit._ICE5 +#define ICS45_ICP4 _ics45.bit._ICP4 +#define ICS45_ICP5 _ics45.bit._ICP5 +#define ICS45_EG4 _ics45.bitc._EG4 +#define ICS45_EG5 _ics45.bitc._EG5 +__IO_EXTERN __io ICE45STR _ice45; +#define ICE45 _ice45.byte +#define ICE45_IEI4 _ice45.bit._IEI4 +#define ICE45_IEI5 _ice45.bit._IEI5 +#define ICE45_ICUS4 _ice45.bit._ICUS4 +#define ICE45_ICUS5 _ice45.bit._ICUS5 +__IO_EXTERN __io IPCP4STR _ipcp4; +#define IPCP4 _ipcp4.word +#define IPCP4_CP00 _ipcp4.bit._CP00 +#define IPCP4_CP01 _ipcp4.bit._CP01 +#define IPCP4_CP02 _ipcp4.bit._CP02 +#define IPCP4_CP03 _ipcp4.bit._CP03 +#define IPCP4_CP04 _ipcp4.bit._CP04 +#define IPCP4_CP05 _ipcp4.bit._CP05 +#define IPCP4_CP06 _ipcp4.bit._CP06 +#define IPCP4_CP07 _ipcp4.bit._CP07 +#define IPCP4_CP08 _ipcp4.bit._CP08 +#define IPCP4_CP09 _ipcp4.bit._CP09 +#define IPCP4_CP10 _ipcp4.bit._CP10 +#define IPCP4_CP11 _ipcp4.bit._CP11 +#define IPCP4_CP12 _ipcp4.bit._CP12 +#define IPCP4_CP13 _ipcp4.bit._CP13 +#define IPCP4_CP14 _ipcp4.bit._CP14 +#define IPCP4_CP15 _ipcp4.bit._CP15 +#define IPCP4_CP0 _ipcp4.bitc._CP0 +__IO_EXTERN __io IPCPL4STR _ipcpl4; +#define IPCPL4 _ipcpl4.byte +#define IPCPL4_CP00 _ipcpl4.bit._CP00 +#define IPCPL4_CP01 _ipcpl4.bit._CP01 +#define IPCPL4_CP02 _ipcpl4.bit._CP02 +#define IPCPL4_CP03 _ipcpl4.bit._CP03 +#define IPCPL4_CP04 _ipcpl4.bit._CP04 +#define IPCPL4_CP05 _ipcpl4.bit._CP05 +#define IPCPL4_CP06 _ipcpl4.bit._CP06 +#define IPCPL4_CP07 _ipcpl4.bit._CP07 +__IO_EXTERN __io IPCPH4STR _ipcph4; +#define IPCPH4 _ipcph4.byte +#define IPCPH4_CP08 _ipcph4.bit._CP08 +#define IPCPH4_CP09 _ipcph4.bit._CP09 +#define IPCPH4_CP10 _ipcph4.bit._CP10 +#define IPCPH4_CP11 _ipcph4.bit._CP11 +#define IPCPH4_CP12 _ipcph4.bit._CP12 +#define IPCPH4_CP13 _ipcph4.bit._CP13 +#define IPCPH4_CP14 _ipcph4.bit._CP14 +#define IPCPH4_CP15 _ipcph4.bit._CP15 +__IO_EXTERN __io IPCP5STR _ipcp5; +#define IPCP5 _ipcp5.word +#define IPCP5_CP00 _ipcp5.bit._CP00 +#define IPCP5_CP01 _ipcp5.bit._CP01 +#define IPCP5_CP02 _ipcp5.bit._CP02 +#define IPCP5_CP03 _ipcp5.bit._CP03 +#define IPCP5_CP04 _ipcp5.bit._CP04 +#define IPCP5_CP05 _ipcp5.bit._CP05 +#define IPCP5_CP06 _ipcp5.bit._CP06 +#define IPCP5_CP07 _ipcp5.bit._CP07 +#define IPCP5_CP08 _ipcp5.bit._CP08 +#define IPCP5_CP09 _ipcp5.bit._CP09 +#define IPCP5_CP10 _ipcp5.bit._CP10 +#define IPCP5_CP11 _ipcp5.bit._CP11 +#define IPCP5_CP12 _ipcp5.bit._CP12 +#define IPCP5_CP13 _ipcp5.bit._CP13 +#define IPCP5_CP14 _ipcp5.bit._CP14 +#define IPCP5_CP15 _ipcp5.bit._CP15 +#define IPCP5_CP0 _ipcp5.bitc._CP0 +__IO_EXTERN __io IPCPL5STR _ipcpl5; +#define IPCPL5 _ipcpl5.byte +#define IPCPL5_CP00 _ipcpl5.bit._CP00 +#define IPCPL5_CP01 _ipcpl5.bit._CP01 +#define IPCPL5_CP02 _ipcpl5.bit._CP02 +#define IPCPL5_CP03 _ipcpl5.bit._CP03 +#define IPCPL5_CP04 _ipcpl5.bit._CP04 +#define IPCPL5_CP05 _ipcpl5.bit._CP05 +#define IPCPL5_CP06 _ipcpl5.bit._CP06 +#define IPCPL5_CP07 _ipcpl5.bit._CP07 +__IO_EXTERN __io IPCPH5STR _ipcph5; +#define IPCPH5 _ipcph5.byte +#define IPCPH5_CP08 _ipcph5.bit._CP08 +#define IPCPH5_CP09 _ipcph5.bit._CP09 +#define IPCPH5_CP10 _ipcph5.bit._CP10 +#define IPCPH5_CP11 _ipcph5.bit._CP11 +#define IPCPH5_CP12 _ipcph5.bit._CP12 +#define IPCPH5_CP13 _ipcph5.bit._CP13 +#define IPCPH5_CP14 _ipcph5.bit._CP14 +#define IPCPH5_CP15 _ipcph5.bit._CP15 +__IO_EXTERN __io ICS67STR _ics67; +#define ICS67 _ics67.byte +#define ICS67_EG60 _ics67.bit._EG60 +#define ICS67_EG61 _ics67.bit._EG61 +#define ICS67_EG70 _ics67.bit._EG70 +#define ICS67_EG71 _ics67.bit._EG71 +#define ICS67_ICE6 _ics67.bit._ICE6 +#define ICS67_ICE7 _ics67.bit._ICE7 +#define ICS67_ICP6 _ics67.bit._ICP6 +#define ICS67_ICP7 _ics67.bit._ICP7 +#define ICS67_EG6 _ics67.bitc._EG6 +#define ICS67_EG7 _ics67.bitc._EG7 +__IO_EXTERN __io ICE67STR _ice67; +#define ICE67 _ice67.byte +#define ICE67_IEI6 _ice67.bit._IEI6 +#define ICE67_IEI7 _ice67.bit._IEI7 +#define ICE67_ICUS6 _ice67.bit._ICUS6 +#define ICE67_ICUS7 _ice67.bit._ICUS7 +__IO_EXTERN __io IPCP6STR _ipcp6; +#define IPCP6 _ipcp6.word +#define IPCP6_CP00 _ipcp6.bit._CP00 +#define IPCP6_CP01 _ipcp6.bit._CP01 +#define IPCP6_CP02 _ipcp6.bit._CP02 +#define IPCP6_CP03 _ipcp6.bit._CP03 +#define IPCP6_CP04 _ipcp6.bit._CP04 +#define IPCP6_CP05 _ipcp6.bit._CP05 +#define IPCP6_CP06 _ipcp6.bit._CP06 +#define IPCP6_CP07 _ipcp6.bit._CP07 +#define IPCP6_CP08 _ipcp6.bit._CP08 +#define IPCP6_CP09 _ipcp6.bit._CP09 +#define IPCP6_CP10 _ipcp6.bit._CP10 +#define IPCP6_CP11 _ipcp6.bit._CP11 +#define IPCP6_CP12 _ipcp6.bit._CP12 +#define IPCP6_CP13 _ipcp6.bit._CP13 +#define IPCP6_CP14 _ipcp6.bit._CP14 +#define IPCP6_CP15 _ipcp6.bit._CP15 +#define IPCP6_CP0 _ipcp6.bitc._CP0 +__IO_EXTERN __io IPCPL6STR _ipcpl6; +#define IPCPL6 _ipcpl6.byte +#define IPCPL6_CP00 _ipcpl6.bit._CP00 +#define IPCPL6_CP01 _ipcpl6.bit._CP01 +#define IPCPL6_CP02 _ipcpl6.bit._CP02 +#define IPCPL6_CP03 _ipcpl6.bit._CP03 +#define IPCPL6_CP04 _ipcpl6.bit._CP04 +#define IPCPL6_CP05 _ipcpl6.bit._CP05 +#define IPCPL6_CP06 _ipcpl6.bit._CP06 +#define IPCPL6_CP07 _ipcpl6.bit._CP07 +__IO_EXTERN __io IPCPH6STR _ipcph6; +#define IPCPH6 _ipcph6.byte +#define IPCPH6_CP08 _ipcph6.bit._CP08 +#define IPCPH6_CP09 _ipcph6.bit._CP09 +#define IPCPH6_CP10 _ipcph6.bit._CP10 +#define IPCPH6_CP11 _ipcph6.bit._CP11 +#define IPCPH6_CP12 _ipcph6.bit._CP12 +#define IPCPH6_CP13 _ipcph6.bit._CP13 +#define IPCPH6_CP14 _ipcph6.bit._CP14 +#define IPCPH6_CP15 _ipcph6.bit._CP15 +__IO_EXTERN __io IPCP7STR _ipcp7; +#define IPCP7 _ipcp7.word +#define IPCP7_CP00 _ipcp7.bit._CP00 +#define IPCP7_CP01 _ipcp7.bit._CP01 +#define IPCP7_CP02 _ipcp7.bit._CP02 +#define IPCP7_CP03 _ipcp7.bit._CP03 +#define IPCP7_CP04 _ipcp7.bit._CP04 +#define IPCP7_CP05 _ipcp7.bit._CP05 +#define IPCP7_CP06 _ipcp7.bit._CP06 +#define IPCP7_CP07 _ipcp7.bit._CP07 +#define IPCP7_CP08 _ipcp7.bit._CP08 +#define IPCP7_CP09 _ipcp7.bit._CP09 +#define IPCP7_CP10 _ipcp7.bit._CP10 +#define IPCP7_CP11 _ipcp7.bit._CP11 +#define IPCP7_CP12 _ipcp7.bit._CP12 +#define IPCP7_CP13 _ipcp7.bit._CP13 +#define IPCP7_CP14 _ipcp7.bit._CP14 +#define IPCP7_CP15 _ipcp7.bit._CP15 +#define IPCP7_CP0 _ipcp7.bitc._CP0 +__IO_EXTERN __io IPCPL7STR _ipcpl7; +#define IPCPL7 _ipcpl7.byte +#define IPCPL7_CP00 _ipcpl7.bit._CP00 +#define IPCPL7_CP01 _ipcpl7.bit._CP01 +#define IPCPL7_CP02 _ipcpl7.bit._CP02 +#define IPCPL7_CP03 _ipcpl7.bit._CP03 +#define IPCPL7_CP04 _ipcpl7.bit._CP04 +#define IPCPL7_CP05 _ipcpl7.bit._CP05 +#define IPCPL7_CP06 _ipcpl7.bit._CP06 +#define IPCPL7_CP07 _ipcpl7.bit._CP07 +__IO_EXTERN __io IPCPH7STR _ipcph7; +#define IPCPH7 _ipcph7.byte +#define IPCPH7_CP08 _ipcph7.bit._CP08 +#define IPCPH7_CP09 _ipcph7.bit._CP09 +#define IPCPH7_CP10 _ipcph7.bit._CP10 +#define IPCPH7_CP11 _ipcph7.bit._CP11 +#define IPCPH7_CP12 _ipcph7.bit._CP12 +#define IPCPH7_CP13 _ipcph7.bit._CP13 +#define IPCPH7_CP14 _ipcph7.bit._CP14 +#define IPCPH7_CP15 _ipcph7.bit._CP15 +__IO_EXTERN __io ENIR0STR _enir0; +#define ENIR0 _enir0.byte +#define ENIR0_EN0 _enir0.bit._EN0 +#define ENIR0_EN1 _enir0.bit._EN1 +#define ENIR0_EN2 _enir0.bit._EN2 +#define ENIR0_EN3 _enir0.bit._EN3 +#define ENIR0_EN4 _enir0.bit._EN4 +#define ENIR0_EN5 _enir0.bit._EN5 +#define ENIR0_EN6 _enir0.bit._EN6 +#define ENIR0_EN7 _enir0.bit._EN7 +__IO_EXTERN __io EIRR0STR _eirr0; +#define EIRR0 _eirr0.byte +#define EIRR0_ER0 _eirr0.bit._ER0 +#define EIRR0_ER1 _eirr0.bit._ER1 +#define EIRR0_ER2 _eirr0.bit._ER2 +#define EIRR0_ER3 _eirr0.bit._ER3 +#define EIRR0_ER4 _eirr0.bit._ER4 +#define EIRR0_ER5 _eirr0.bit._ER5 +#define EIRR0_ER6 _eirr0.bit._ER6 +#define EIRR0_ER7 _eirr0.bit._ER7 +__IO_EXTERN __io ELVR0STR _elvr0; +#define ELVR0 _elvr0.word +#define ELVR0_LA0 _elvr0.bit._LA0 +#define ELVR0_LB0 _elvr0.bit._LB0 +#define ELVR0_LA1 _elvr0.bit._LA1 +#define ELVR0_LB1 _elvr0.bit._LB1 +#define ELVR0_LA2 _elvr0.bit._LA2 +#define ELVR0_LB2 _elvr0.bit._LB2 +#define ELVR0_LA3 _elvr0.bit._LA3 +#define ELVR0_LB3 _elvr0.bit._LB3 +#define ELVR0_LA4 _elvr0.bit._LA4 +#define ELVR0_LB4 _elvr0.bit._LB4 +#define ELVR0_LA5 _elvr0.bit._LA5 +#define ELVR0_LB5 _elvr0.bit._LB5 +#define ELVR0_LA6 _elvr0.bit._LA6 +#define ELVR0_LB6 _elvr0.bit._LB6 +#define ELVR0_LA7 _elvr0.bit._LA7 +#define ELVR0_LB7 _elvr0.bit._LB7 +__IO_EXTERN __io ELVRL0STR _elvrl0; +#define ELVRL0 _elvrl0.byte +#define ELVRL0_LA0 _elvrl0.bit._LA0 +#define ELVRL0_LB0 _elvrl0.bit._LB0 +#define ELVRL0_LA1 _elvrl0.bit._LA1 +#define ELVRL0_LB1 _elvrl0.bit._LB1 +#define ELVRL0_LA2 _elvrl0.bit._LA2 +#define ELVRL0_LB2 _elvrl0.bit._LB2 +#define ELVRL0_LA3 _elvrl0.bit._LA3 +#define ELVRL0_LB3 _elvrl0.bit._LB3 +__IO_EXTERN __io ELVRH0STR _elvrh0; +#define ELVRH0 _elvrh0.byte +#define ELVRH0_LA4 _elvrh0.bit._LA4 +#define ELVRH0_LB4 _elvrh0.bit._LB4 +#define ELVRH0_LA5 _elvrh0.bit._LA5 +#define ELVRH0_LB5 _elvrh0.bit._LB5 +#define ELVRH0_LA6 _elvrh0.bit._LA6 +#define ELVRH0_LB6 _elvrh0.bit._LB6 +#define ELVRH0_LA7 _elvrh0.bit._LA7 +#define ELVRH0_LB7 _elvrh0.bit._LB7 +__IO_EXTERN __io ENIR1STR _enir1; +#define ENIR1 _enir1.byte +#define ENIR1_EN8 _enir1.bit._EN8 +#define ENIR1_EN9 _enir1.bit._EN9 +#define ENIR1_EN10 _enir1.bit._EN10 +#define ENIR1_EN11 _enir1.bit._EN11 +#define ENIR1_EN12 _enir1.bit._EN12 +#define ENIR1_EN13 _enir1.bit._EN13 +#define ENIR1_EN14 _enir1.bit._EN14 +#define ENIR1_EN15 _enir1.bit._EN15 +__IO_EXTERN __io EIRR1STR _eirr1; +#define EIRR1 _eirr1.byte +#define EIRR1_ER8 _eirr1.bit._ER8 +#define EIRR1_ER9 _eirr1.bit._ER9 +#define EIRR1_ER10 _eirr1.bit._ER10 +#define EIRR1_ER11 _eirr1.bit._ER11 +#define EIRR1_ER12 _eirr1.bit._ER12 +#define EIRR1_ER13 _eirr1.bit._ER13 +#define EIRR1_ER14 _eirr1.bit._ER14 +#define EIRR1_ER15 _eirr1.bit._ER15 +__IO_EXTERN __io ELVR1STR _elvr1; +#define ELVR1 _elvr1.word +#define ELVR1_LA8 _elvr1.bit._LA8 +#define ELVR1_LB8 _elvr1.bit._LB8 +#define ELVR1_LA9 _elvr1.bit._LA9 +#define ELVR1_LB9 _elvr1.bit._LB9 +#define ELVR1_LA10 _elvr1.bit._LA10 +#define ELVR1_LB10 _elvr1.bit._LB10 +#define ELVR1_LA11 _elvr1.bit._LA11 +#define ELVR1_LB11 _elvr1.bit._LB11 +#define ELVR1_LA12 _elvr1.bit._LA12 +#define ELVR1_LB12 _elvr1.bit._LB12 +#define ELVR1_LA13 _elvr1.bit._LA13 +#define ELVR1_LB13 _elvr1.bit._LB13 +#define ELVR1_LA14 _elvr1.bit._LA14 +#define ELVR1_LB14 _elvr1.bit._LB14 +#define ELVR1_LA15 _elvr1.bit._LA15 +#define ELVR1_LB15 _elvr1.bit._LB15 +__IO_EXTERN __io ELVRL1STR _elvrl1; +#define ELVRL1 _elvrl1.byte +#define ELVRL1_LA8 _elvrl1.bit._LA8 +#define ELVRL1_LB8 _elvrl1.bit._LB8 +#define ELVRL1_LA9 _elvrl1.bit._LA9 +#define ELVRL1_LB9 _elvrl1.bit._LB9 +#define ELVRL1_LA10 _elvrl1.bit._LA10 +#define ELVRL1_LB10 _elvrl1.bit._LB10 +#define ELVRL1_LA11 _elvrl1.bit._LA11 +#define ELVRL1_LB11 _elvrl1.bit._LB11 +__IO_EXTERN __io ELVRH1STR _elvrh1; +#define ELVRH1 _elvrh1.byte +#define ELVRH1_LA12 _elvrh1.bit._LA12 +#define ELVRH1_LB12 _elvrh1.bit._LB12 +#define ELVRH1_LA13 _elvrh1.bit._LA13 +#define ELVRH1_LB13 _elvrh1.bit._LB13 +#define ELVRH1_LA14 _elvrh1.bit._LA14 +#define ELVRH1_LB14 _elvrh1.bit._LB14 +#define ELVRH1_LA15 _elvrh1.bit._LA15 +#define ELVRH1_LB15 _elvrh1.bit._LB15 +__IO_EXTERN __io TMCSR0STR _tmcsr0; +#define TMCSR0 _tmcsr0.word +#define TMCSR0_TRG _tmcsr0.bit._TRG +#define TMCSR0_CNTE _tmcsr0.bit._CNTE +#define TMCSR0_UF _tmcsr0.bit._UF +#define TMCSR0_INTE _tmcsr0.bit._INTE +#define TMCSR0_RELD _tmcsr0.bit._RELD +#define TMCSR0_OUTL _tmcsr0.bit._OUTL +#define TMCSR0_OUTE _tmcsr0.bit._OUTE +#define TMCSR0_MOD0 _tmcsr0.bit._MOD0 +#define TMCSR0_MOD1 _tmcsr0.bit._MOD1 +#define TMCSR0_MOD2 _tmcsr0.bit._MOD2 +#define TMCSR0_CSL0 _tmcsr0.bit._CSL0 +#define TMCSR0_CSL1 _tmcsr0.bit._CSL1 +#define TMCSR0_FSEL _tmcsr0.bit._FSEL +#define TMCSR0_CSL _tmcsr0.bitc._CSL +__IO_EXTERN __io TMCSRL0STR _tmcsrl0; +#define TMCSRL0 _tmcsrl0.byte +#define TMCSRL0_TRG _tmcsrl0.bit._TRG +#define TMCSRL0_CNTE _tmcsrl0.bit._CNTE +#define TMCSRL0_UF _tmcsrl0.bit._UF +#define TMCSRL0_INTE _tmcsrl0.bit._INTE +#define TMCSRL0_RELD _tmcsrl0.bit._RELD +#define TMCSRL0_OUTL _tmcsrl0.bit._OUTL +#define TMCSRL0_OUTE _tmcsrl0.bit._OUTE +#define TMCSRL0_MOD0 _tmcsrl0.bit._MOD0 +__IO_EXTERN __io TMCSRH0STR _tmcsrh0; +#define TMCSRH0 _tmcsrh0.byte +#define TMCSRH0_MOD1 _tmcsrh0.bit._MOD1 +#define TMCSRH0_MOD2 _tmcsrh0.bit._MOD2 +#define TMCSRH0_CSL0 _tmcsrh0.bit._CSL0 +#define TMCSRH0_CSL1 _tmcsrh0.bit._CSL1 +#define TMCSRH0_FSEL _tmcsrh0.bit._FSEL +#define TMCSRH0_CSL _tmcsrh0.bitc._CSL +__IO_EXTERN __io IO_WORD _tmrlr0; +#define TMRLR0 _tmrlr0 +__IO_EXTERN __io IO_WORD _tmr0; +#define TMR0 _tmr0 +__IO_EXTERN __io TMCSR1STR _tmcsr1; +#define TMCSR1 _tmcsr1.word +#define TMCSR1_TRG _tmcsr1.bit._TRG +#define TMCSR1_CNTE _tmcsr1.bit._CNTE +#define TMCSR1_UF _tmcsr1.bit._UF +#define TMCSR1_INTE _tmcsr1.bit._INTE +#define TMCSR1_RELD _tmcsr1.bit._RELD +#define TMCSR1_OUTL _tmcsr1.bit._OUTL +#define TMCSR1_OUTE _tmcsr1.bit._OUTE +#define TMCSR1_MOD0 _tmcsr1.bit._MOD0 +#define TMCSR1_MOD1 _tmcsr1.bit._MOD1 +#define TMCSR1_MOD2 _tmcsr1.bit._MOD2 +#define TMCSR1_CSL0 _tmcsr1.bit._CSL0 +#define TMCSR1_CSL1 _tmcsr1.bit._CSL1 +#define TMCSR1_FSEL _tmcsr1.bit._FSEL +#define TMCSR1_CSL _tmcsr1.bitc._CSL +__IO_EXTERN __io TMCSRL1STR _tmcsrl1; +#define TMCSRL1 _tmcsrl1.byte +#define TMCSRL1_TRG _tmcsrl1.bit._TRG +#define TMCSRL1_CNTE _tmcsrl1.bit._CNTE +#define TMCSRL1_UF _tmcsrl1.bit._UF +#define TMCSRL1_INTE _tmcsrl1.bit._INTE +#define TMCSRL1_RELD _tmcsrl1.bit._RELD +#define TMCSRL1_OUTL _tmcsrl1.bit._OUTL +#define TMCSRL1_OUTE _tmcsrl1.bit._OUTE +#define TMCSRL1_MOD0 _tmcsrl1.bit._MOD0 +__IO_EXTERN __io TMCSRH1STR _tmcsrh1; +#define TMCSRH1 _tmcsrh1.byte +#define TMCSRH1_MOD1 _tmcsrh1.bit._MOD1 +#define TMCSRH1_MOD2 _tmcsrh1.bit._MOD2 +#define TMCSRH1_CSL0 _tmcsrh1.bit._CSL0 +#define TMCSRH1_CSL1 _tmcsrh1.bit._CSL1 +#define TMCSRH1_FSEL _tmcsrh1.bit._FSEL +#define TMCSRH1_CSL _tmcsrh1.bitc._CSL +__IO_EXTERN __io IO_WORD _tmrlr1; +#define TMRLR1 _tmrlr1 +__IO_EXTERN __io IO_WORD _tmr1; +#define TMR1 _tmr1 +__IO_EXTERN __io TMCSR2STR _tmcsr2; +#define TMCSR2 _tmcsr2.word +#define TMCSR2_TRG _tmcsr2.bit._TRG +#define TMCSR2_CNTE _tmcsr2.bit._CNTE +#define TMCSR2_UF _tmcsr2.bit._UF +#define TMCSR2_INTE _tmcsr2.bit._INTE +#define TMCSR2_RELD _tmcsr2.bit._RELD +#define TMCSR2_OUTL _tmcsr2.bit._OUTL +#define TMCSR2_OUTE _tmcsr2.bit._OUTE +#define TMCSR2_MOD0 _tmcsr2.bit._MOD0 +#define TMCSR2_MOD1 _tmcsr2.bit._MOD1 +#define TMCSR2_MOD2 _tmcsr2.bit._MOD2 +#define TMCSR2_CSL0 _tmcsr2.bit._CSL0 +#define TMCSR2_CSL1 _tmcsr2.bit._CSL1 +#define TMCSR2_FSEL _tmcsr2.bit._FSEL +#define TMCSR2_CSL _tmcsr2.bitc._CSL +__IO_EXTERN __io TMCSRL2STR _tmcsrl2; +#define TMCSRL2 _tmcsrl2.byte +#define TMCSRL2_TRG _tmcsrl2.bit._TRG +#define TMCSRL2_CNTE _tmcsrl2.bit._CNTE +#define TMCSRL2_UF _tmcsrl2.bit._UF +#define TMCSRL2_INTE _tmcsrl2.bit._INTE +#define TMCSRL2_RELD _tmcsrl2.bit._RELD +#define TMCSRL2_OUTL _tmcsrl2.bit._OUTL +#define TMCSRL2_OUTE _tmcsrl2.bit._OUTE +#define TMCSRL2_MOD0 _tmcsrl2.bit._MOD0 +__IO_EXTERN __io TMCSRH2STR _tmcsrh2; +#define TMCSRH2 _tmcsrh2.byte +#define TMCSRH2_MOD1 _tmcsrh2.bit._MOD1 +#define TMCSRH2_MOD2 _tmcsrh2.bit._MOD2 +#define TMCSRH2_CSL0 _tmcsrh2.bit._CSL0 +#define TMCSRH2_CSL1 _tmcsrh2.bit._CSL1 +#define TMCSRH2_FSEL _tmcsrh2.bit._FSEL +#define TMCSRH2_CSL _tmcsrh2.bitc._CSL +__IO_EXTERN __io IO_WORD _tmrlr2; +#define TMRLR2 _tmrlr2 +__IO_EXTERN __io IO_WORD _tmr2; +#define TMR2 _tmr2 +__IO_EXTERN __io TMCSR3STR _tmcsr3; +#define TMCSR3 _tmcsr3.word +#define TMCSR3_TRG _tmcsr3.bit._TRG +#define TMCSR3_CNTE _tmcsr3.bit._CNTE +#define TMCSR3_UF _tmcsr3.bit._UF +#define TMCSR3_INTE _tmcsr3.bit._INTE +#define TMCSR3_RELD _tmcsr3.bit._RELD +#define TMCSR3_OUTL _tmcsr3.bit._OUTL +#define TMCSR3_OUTE _tmcsr3.bit._OUTE +#define TMCSR3_MOD0 _tmcsr3.bit._MOD0 +#define TMCSR3_MOD1 _tmcsr3.bit._MOD1 +#define TMCSR3_MOD2 _tmcsr3.bit._MOD2 +#define TMCSR3_CSL0 _tmcsr3.bit._CSL0 +#define TMCSR3_CSL1 _tmcsr3.bit._CSL1 +#define TMCSR3_FSEL _tmcsr3.bit._FSEL +#define TMCSR3_CSL _tmcsr3.bitc._CSL +__IO_EXTERN __io TMCSRL3STR _tmcsrl3; +#define TMCSRL3 _tmcsrl3.byte +#define TMCSRL3_TRG _tmcsrl3.bit._TRG +#define TMCSRL3_CNTE _tmcsrl3.bit._CNTE +#define TMCSRL3_UF _tmcsrl3.bit._UF +#define TMCSRL3_INTE _tmcsrl3.bit._INTE +#define TMCSRL3_RELD _tmcsrl3.bit._RELD +#define TMCSRL3_OUTL _tmcsrl3.bit._OUTL +#define TMCSRL3_OUTE _tmcsrl3.bit._OUTE +#define TMCSRL3_MOD0 _tmcsrl3.bit._MOD0 +__IO_EXTERN __io TMCSRH3STR _tmcsrh3; +#define TMCSRH3 _tmcsrh3.byte +#define TMCSRH3_MOD1 _tmcsrh3.bit._MOD1 +#define TMCSRH3_MOD2 _tmcsrh3.bit._MOD2 +#define TMCSRH3_CSL0 _tmcsrh3.bit._CSL0 +#define TMCSRH3_CSL1 _tmcsrh3.bit._CSL1 +#define TMCSRH3_FSEL _tmcsrh3.bit._FSEL +#define TMCSRH3_CSL _tmcsrh3.bitc._CSL +__IO_EXTERN __io IO_WORD _tmrlr3; +#define TMRLR3 _tmrlr3 +__IO_EXTERN __io IO_WORD _tmr3; +#define TMR3 _tmr3 +__IO_EXTERN __io TMCSR6STR _tmcsr6; +#define TMCSR6 _tmcsr6.word +#define TMCSR6_TRG _tmcsr6.bit._TRG +#define TMCSR6_CNTE _tmcsr6.bit._CNTE +#define TMCSR6_UF _tmcsr6.bit._UF +#define TMCSR6_INTE _tmcsr6.bit._INTE +#define TMCSR6_RELD _tmcsr6.bit._RELD +#define TMCSR6_MOD0 _tmcsr6.bit._MOD0 +#define TMCSR6_MOD1 _tmcsr6.bit._MOD1 +#define TMCSR6_MOD2 _tmcsr6.bit._MOD2 +#define TMCSR6_CSL0 _tmcsr6.bit._CSL0 +#define TMCSR6_CSL1 _tmcsr6.bit._CSL1 +#define TMCSR6_FSEL _tmcsr6.bit._FSEL +#define TMCSR6_CSL _tmcsr6.bitc._CSL +__IO_EXTERN __io TMCSRL6STR _tmcsrl6; +#define TMCSRL6 _tmcsrl6.byte +#define TMCSRL6_TRG _tmcsrl6.bit._TRG +#define TMCSRL6_CNTE _tmcsrl6.bit._CNTE +#define TMCSRL6_UF _tmcsrl6.bit._UF +#define TMCSRL6_INTE _tmcsrl6.bit._INTE +#define TMCSRL6_RELD _tmcsrl6.bit._RELD +#define TMCSRL6_MOD0 _tmcsrl6.bit._MOD0 +__IO_EXTERN __io TMCSRH6STR _tmcsrh6; +#define TMCSRH6 _tmcsrh6.byte +#define TMCSRH6_MOD1 _tmcsrh6.bit._MOD1 +#define TMCSRH6_MOD2 _tmcsrh6.bit._MOD2 +#define TMCSRH6_CSL0 _tmcsrh6.bit._CSL0 +#define TMCSRH6_CSL1 _tmcsrh6.bit._CSL1 +#define TMCSRH6_FSEL _tmcsrh6.bit._FSEL +#define TMCSRH6_CSL _tmcsrh6.bitc._CSL +__IO_EXTERN __io IO_WORD _tmrlr6; +#define TMRLR6 _tmrlr6 +__IO_EXTERN __io IO_WORD _tmr6; +#define TMR6 _tmr6 +__IO_EXTERN __io GCN10STR _gcn10; +#define GCN10 _gcn10.word +#define GCN10_TSEL00 _gcn10.bit._TSEL00 +#define GCN10_TSEL01 _gcn10.bit._TSEL01 +#define GCN10_TSEL02 _gcn10.bit._TSEL02 +#define GCN10_TSEL03 _gcn10.bit._TSEL03 +#define GCN10_TSEL10 _gcn10.bit._TSEL10 +#define GCN10_TSEL11 _gcn10.bit._TSEL11 +#define GCN10_TSEL12 _gcn10.bit._TSEL12 +#define GCN10_TSEL13 _gcn10.bit._TSEL13 +#define GCN10_TSEL20 _gcn10.bit._TSEL20 +#define GCN10_TSEL21 _gcn10.bit._TSEL21 +#define GCN10_TSEL22 _gcn10.bit._TSEL22 +#define GCN10_TSEL23 _gcn10.bit._TSEL23 +#define GCN10_TSEL30 _gcn10.bit._TSEL30 +#define GCN10_TSEL31 _gcn10.bit._TSEL31 +#define GCN10_TSEL32 _gcn10.bit._TSEL32 +#define GCN10_TSEL33 _gcn10.bit._TSEL33 +#define GCN10_TSEL0 _gcn10.bitc._TSEL0 +#define GCN10_TSEL1 _gcn10.bitc._TSEL1 +#define GCN10_TSEL2 _gcn10.bitc._TSEL2 +#define GCN10_TSEL3 _gcn10.bitc._TSEL3 +__IO_EXTERN __io GCN1L0STR _gcn1l0; +#define GCN1L0 _gcn1l0.byte +#define GCN1L0_TSEL00 _gcn1l0.bit._TSEL00 +#define GCN1L0_TSEL01 _gcn1l0.bit._TSEL01 +#define GCN1L0_TSEL02 _gcn1l0.bit._TSEL02 +#define GCN1L0_TSEL03 _gcn1l0.bit._TSEL03 +#define GCN1L0_TSEL10 _gcn1l0.bit._TSEL10 +#define GCN1L0_TSEL11 _gcn1l0.bit._TSEL11 +#define GCN1L0_TSEL12 _gcn1l0.bit._TSEL12 +#define GCN1L0_TSEL13 _gcn1l0.bit._TSEL13 +#define GCN1L0_TSEL0 _gcn1l0.bitc._TSEL0 +#define GCN1L0_TSEL1 _gcn1l0.bitc._TSEL1 +__IO_EXTERN __io GCN1H0STR _gcn1h0; +#define GCN1H0 _gcn1h0.byte +#define GCN1H0_TSEL20 _gcn1h0.bit._TSEL20 +#define GCN1H0_TSEL21 _gcn1h0.bit._TSEL21 +#define GCN1H0_TSEL22 _gcn1h0.bit._TSEL22 +#define GCN1H0_TSEL23 _gcn1h0.bit._TSEL23 +#define GCN1H0_TSEL30 _gcn1h0.bit._TSEL30 +#define GCN1H0_TSEL31 _gcn1h0.bit._TSEL31 +#define GCN1H0_TSEL32 _gcn1h0.bit._TSEL32 +#define GCN1H0_TSEL33 _gcn1h0.bit._TSEL33 +#define GCN1H0_TSEL2 _gcn1h0.bitc._TSEL2 +#define GCN1H0_TSEL3 _gcn1h0.bitc._TSEL3 +__IO_EXTERN __io GCN20STR _gcn20; +#define GCN20 _gcn20.word +#define GCN20_EN0 _gcn20.bit._EN0 +#define GCN20_EN1 _gcn20.bit._EN1 +#define GCN20_EN2 _gcn20.bit._EN2 +#define GCN20_EN3 _gcn20.bit._EN3 +#define GCN20_CKSEL0 _gcn20.bit._CKSEL0 +#define GCN20_CKSEL1 _gcn20.bit._CKSEL1 +#define GCN20_CKSEL2 _gcn20.bit._CKSEL2 +#define GCN20_CKSEL3 _gcn20.bit._CKSEL3 +#define GCN20_EN _gcn20.bitc._EN +#define GCN20_CKSEL _gcn20.bitc._CKSEL +__IO_EXTERN __io GCN2L0STR _gcn2l0; +#define GCN2L0 _gcn2l0.byte +#define GCN2L0_EN0 _gcn2l0.bit._EN0 +#define GCN2L0_EN1 _gcn2l0.bit._EN1 +#define GCN2L0_EN2 _gcn2l0.bit._EN2 +#define GCN2L0_EN3 _gcn2l0.bit._EN3 +#define GCN2L0_EN _gcn2l0.bitc._EN +__IO_EXTERN __io GCN2H0STR _gcn2h0; +#define GCN2H0 _gcn2h0.byte +#define GCN2H0_CKSEL0 _gcn2h0.bit._CKSEL0 +#define GCN2H0_CKSEL1 _gcn2h0.bit._CKSEL1 +#define GCN2H0_CKSEL2 _gcn2h0.bit._CKSEL2 +#define GCN2H0_CKSEL3 _gcn2h0.bit._CKSEL3 +#define GCN2H0_CKSEL _gcn2h0.bitc._CKSEL +__IO_EXTERN __io PTMR0STR _ptmr0; +#define PTMR0 _ptmr0.word +#define PTMR0_D0 _ptmr0.bit._D0 +#define PTMR0_D1 _ptmr0.bit._D1 +#define PTMR0_D2 _ptmr0.bit._D2 +#define PTMR0_D3 _ptmr0.bit._D3 +#define PTMR0_D4 _ptmr0.bit._D4 +#define PTMR0_D5 _ptmr0.bit._D5 +#define PTMR0_D6 _ptmr0.bit._D6 +#define PTMR0_D7 _ptmr0.bit._D7 +#define PTMR0_D8 _ptmr0.bit._D8 +#define PTMR0_D9 _ptmr0.bit._D9 +#define PTMR0_D10 _ptmr0.bit._D10 +#define PTMR0_D11 _ptmr0.bit._D11 +#define PTMR0_D12 _ptmr0.bit._D12 +#define PTMR0_D13 _ptmr0.bit._D13 +#define PTMR0_D14 _ptmr0.bit._D14 +#define PTMR0_D15 _ptmr0.bit._D15 +#define PTMR0_D _ptmr0.bitc._D +__IO_EXTERN __io PCSR0STR _pcsr0; +#define PCSR0 _pcsr0.word +#define PCSR0_D0 _pcsr0.bit._D0 +#define PCSR0_D1 _pcsr0.bit._D1 +#define PCSR0_D2 _pcsr0.bit._D2 +#define PCSR0_D3 _pcsr0.bit._D3 +#define PCSR0_D4 _pcsr0.bit._D4 +#define PCSR0_D5 _pcsr0.bit._D5 +#define PCSR0_D6 _pcsr0.bit._D6 +#define PCSR0_D7 _pcsr0.bit._D7 +#define PCSR0_D8 _pcsr0.bit._D8 +#define PCSR0_D9 _pcsr0.bit._D9 +#define PCSR0_D10 _pcsr0.bit._D10 +#define PCSR0_D11 _pcsr0.bit._D11 +#define PCSR0_D12 _pcsr0.bit._D12 +#define PCSR0_D13 _pcsr0.bit._D13 +#define PCSR0_D14 _pcsr0.bit._D14 +#define PCSR0_D15 _pcsr0.bit._D15 +#define PCSR0_D _pcsr0.bitc._D +__IO_EXTERN __io PDUT0STR _pdut0; +#define PDUT0 _pdut0.word +#define PDUT0_D0 _pdut0.bit._D0 +#define PDUT0_D1 _pdut0.bit._D1 +#define PDUT0_D2 _pdut0.bit._D2 +#define PDUT0_D3 _pdut0.bit._D3 +#define PDUT0_D4 _pdut0.bit._D4 +#define PDUT0_D5 _pdut0.bit._D5 +#define PDUT0_D6 _pdut0.bit._D6 +#define PDUT0_D7 _pdut0.bit._D7 +#define PDUT0_D8 _pdut0.bit._D8 +#define PDUT0_D9 _pdut0.bit._D9 +#define PDUT0_D10 _pdut0.bit._D10 +#define PDUT0_D11 _pdut0.bit._D11 +#define PDUT0_D12 _pdut0.bit._D12 +#define PDUT0_D13 _pdut0.bit._D13 +#define PDUT0_D14 _pdut0.bit._D14 +#define PDUT0_D15 _pdut0.bit._D15 +#define PDUT0_D _pdut0.bitc._D +__IO_EXTERN __io PCN0STR _pcn0; +#define PCN0 _pcn0.word +#define PCN0_OSEL _pcn0.bit._OSEL +#define PCN0_OE _pcn0.bit._OE +#define PCN0_IRS0 _pcn0.bit._IRS0 +#define PCN0_IRS1 _pcn0.bit._IRS1 +#define PCN0_IRQF _pcn0.bit._IRQF +#define PCN0_IREN _pcn0.bit._IREN +#define PCN0_EGS0 _pcn0.bit._EGS0 +#define PCN0_EGS1 _pcn0.bit._EGS1 +#define PCN0_PGMS _pcn0.bit._PGMS +#define PCN0_CKS0 _pcn0.bit._CKS0 +#define PCN0_CKS1 _pcn0.bit._CKS1 +#define PCN0_RTRG _pcn0.bit._RTRG +#define PCN0_MDSE _pcn0.bit._MDSE +#define PCN0_STGR _pcn0.bit._STGR +#define PCN0_CNTE _pcn0.bit._CNTE +#define PCN0_IRS _pcn0.bitc._IRS +#define PCN0_EGS _pcn0.bitc._EGS +#define PCN0_CKS _pcn0.bitc._CKS +__IO_EXTERN __io PCNL0STR _pcnl0; +#define PCNL0 _pcnl0.byte +#define PCNL0_OSEL _pcnl0.bit._OSEL +#define PCNL0_OE _pcnl0.bit._OE +#define PCNL0_IRS0 _pcnl0.bit._IRS0 +#define PCNL0_IRS1 _pcnl0.bit._IRS1 +#define PCNL0_IRQF _pcnl0.bit._IRQF +#define PCNL0_IREN _pcnl0.bit._IREN +#define PCNL0_EGS0 _pcnl0.bit._EGS0 +#define PCNL0_EGS1 _pcnl0.bit._EGS1 +#define PCNL0_IRS _pcnl0.bitc._IRS +#define PCNL0_EGS _pcnl0.bitc._EGS +__IO_EXTERN __io PCNH0STR _pcnh0; +#define PCNH0 _pcnh0.byte +#define PCNH0_PGMS _pcnh0.bit._PGMS +#define PCNH0_CKS0 _pcnh0.bit._CKS0 +#define PCNH0_CKS1 _pcnh0.bit._CKS1 +#define PCNH0_RTRG _pcnh0.bit._RTRG +#define PCNH0_MDSE _pcnh0.bit._MDSE +#define PCNH0_STGR _pcnh0.bit._STGR +#define PCNH0_CNTE _pcnh0.bit._CNTE +#define PCNH0_CKS _pcnh0.bitc._CKS +__IO_EXTERN __io PTMR1STR _ptmr1; +#define PTMR1 _ptmr1.word +#define PTMR1_D0 _ptmr1.bit._D0 +#define PTMR1_D1 _ptmr1.bit._D1 +#define PTMR1_D2 _ptmr1.bit._D2 +#define PTMR1_D3 _ptmr1.bit._D3 +#define PTMR1_D4 _ptmr1.bit._D4 +#define PTMR1_D5 _ptmr1.bit._D5 +#define PTMR1_D6 _ptmr1.bit._D6 +#define PTMR1_D7 _ptmr1.bit._D7 +#define PTMR1_D8 _ptmr1.bit._D8 +#define PTMR1_D9 _ptmr1.bit._D9 +#define PTMR1_D10 _ptmr1.bit._D10 +#define PTMR1_D11 _ptmr1.bit._D11 +#define PTMR1_D12 _ptmr1.bit._D12 +#define PTMR1_D13 _ptmr1.bit._D13 +#define PTMR1_D14 _ptmr1.bit._D14 +#define PTMR1_D15 _ptmr1.bit._D15 +#define PTMR1_D _ptmr1.bitc._D +__IO_EXTERN __io PCSR1STR _pcsr1; +#define PCSR1 _pcsr1.word +#define PCSR1_D0 _pcsr1.bit._D0 +#define PCSR1_D1 _pcsr1.bit._D1 +#define PCSR1_D2 _pcsr1.bit._D2 +#define PCSR1_D3 _pcsr1.bit._D3 +#define PCSR1_D4 _pcsr1.bit._D4 +#define PCSR1_D5 _pcsr1.bit._D5 +#define PCSR1_D6 _pcsr1.bit._D6 +#define PCSR1_D7 _pcsr1.bit._D7 +#define PCSR1_D8 _pcsr1.bit._D8 +#define PCSR1_D9 _pcsr1.bit._D9 +#define PCSR1_D10 _pcsr1.bit._D10 +#define PCSR1_D11 _pcsr1.bit._D11 +#define PCSR1_D12 _pcsr1.bit._D12 +#define PCSR1_D13 _pcsr1.bit._D13 +#define PCSR1_D14 _pcsr1.bit._D14 +#define PCSR1_D15 _pcsr1.bit._D15 +#define PCSR1_D _pcsr1.bitc._D +__IO_EXTERN __io PDUT1STR _pdut1; +#define PDUT1 _pdut1.word +#define PDUT1_D0 _pdut1.bit._D0 +#define PDUT1_D1 _pdut1.bit._D1 +#define PDUT1_D2 _pdut1.bit._D2 +#define PDUT1_D3 _pdut1.bit._D3 +#define PDUT1_D4 _pdut1.bit._D4 +#define PDUT1_D5 _pdut1.bit._D5 +#define PDUT1_D6 _pdut1.bit._D6 +#define PDUT1_D7 _pdut1.bit._D7 +#define PDUT1_D8 _pdut1.bit._D8 +#define PDUT1_D9 _pdut1.bit._D9 +#define PDUT1_D10 _pdut1.bit._D10 +#define PDUT1_D11 _pdut1.bit._D11 +#define PDUT1_D12 _pdut1.bit._D12 +#define PDUT1_D13 _pdut1.bit._D13 +#define PDUT1_D14 _pdut1.bit._D14 +#define PDUT1_D15 _pdut1.bit._D15 +#define PDUT1_D _pdut1.bitc._D +__IO_EXTERN __io PCN1STR _pcn1; +#define PCN1 _pcn1.word +#define PCN1_OSEL _pcn1.bit._OSEL +#define PCN1_OE _pcn1.bit._OE +#define PCN1_IRS0 _pcn1.bit._IRS0 +#define PCN1_IRS1 _pcn1.bit._IRS1 +#define PCN1_IRQF _pcn1.bit._IRQF +#define PCN1_IREN _pcn1.bit._IREN +#define PCN1_EGS0 _pcn1.bit._EGS0 +#define PCN1_EGS1 _pcn1.bit._EGS1 +#define PCN1_PGMS _pcn1.bit._PGMS +#define PCN1_CKS0 _pcn1.bit._CKS0 +#define PCN1_CKS1 _pcn1.bit._CKS1 +#define PCN1_RTRG _pcn1.bit._RTRG +#define PCN1_MDSE _pcn1.bit._MDSE +#define PCN1_STGR _pcn1.bit._STGR +#define PCN1_CNTE _pcn1.bit._CNTE +#define PCN1_IRS _pcn1.bitc._IRS +#define PCN1_EGS _pcn1.bitc._EGS +#define PCN1_CKS _pcn1.bitc._CKS +__IO_EXTERN __io PCNL1STR _pcnl1; +#define PCNL1 _pcnl1.byte +#define PCNL1_OSEL _pcnl1.bit._OSEL +#define PCNL1_OE _pcnl1.bit._OE +#define PCNL1_IRS0 _pcnl1.bit._IRS0 +#define PCNL1_IRS1 _pcnl1.bit._IRS1 +#define PCNL1_IRQF _pcnl1.bit._IRQF +#define PCNL1_IREN _pcnl1.bit._IREN +#define PCNL1_EGS0 _pcnl1.bit._EGS0 +#define PCNL1_EGS1 _pcnl1.bit._EGS1 +#define PCNL1_IRS _pcnl1.bitc._IRS +#define PCNL1_EGS _pcnl1.bitc._EGS +__IO_EXTERN __io PCNH1STR _pcnh1; +#define PCNH1 _pcnh1.byte +#define PCNH1_PGMS _pcnh1.bit._PGMS +#define PCNH1_CKS0 _pcnh1.bit._CKS0 +#define PCNH1_CKS1 _pcnh1.bit._CKS1 +#define PCNH1_RTRG _pcnh1.bit._RTRG +#define PCNH1_MDSE _pcnh1.bit._MDSE +#define PCNH1_STGR _pcnh1.bit._STGR +#define PCNH1_CNTE _pcnh1.bit._CNTE +#define PCNH1_CKS _pcnh1.bitc._CKS +__IO_EXTERN __io PTMR2STR _ptmr2; +#define PTMR2 _ptmr2.word +#define PTMR2_D0 _ptmr2.bit._D0 +#define PTMR2_D1 _ptmr2.bit._D1 +#define PTMR2_D2 _ptmr2.bit._D2 +#define PTMR2_D3 _ptmr2.bit._D3 +#define PTMR2_D4 _ptmr2.bit._D4 +#define PTMR2_D5 _ptmr2.bit._D5 +#define PTMR2_D6 _ptmr2.bit._D6 +#define PTMR2_D7 _ptmr2.bit._D7 +#define PTMR2_D8 _ptmr2.bit._D8 +#define PTMR2_D9 _ptmr2.bit._D9 +#define PTMR2_D10 _ptmr2.bit._D10 +#define PTMR2_D11 _ptmr2.bit._D11 +#define PTMR2_D12 _ptmr2.bit._D12 +#define PTMR2_D13 _ptmr2.bit._D13 +#define PTMR2_D14 _ptmr2.bit._D14 +#define PTMR2_D15 _ptmr2.bit._D15 +#define PTMR2_D _ptmr2.bitc._D +__IO_EXTERN __io PCSR2STR _pcsr2; +#define PCSR2 _pcsr2.word +#define PCSR2_D0 _pcsr2.bit._D0 +#define PCSR2_D1 _pcsr2.bit._D1 +#define PCSR2_D2 _pcsr2.bit._D2 +#define PCSR2_D3 _pcsr2.bit._D3 +#define PCSR2_D4 _pcsr2.bit._D4 +#define PCSR2_D5 _pcsr2.bit._D5 +#define PCSR2_D6 _pcsr2.bit._D6 +#define PCSR2_D7 _pcsr2.bit._D7 +#define PCSR2_D8 _pcsr2.bit._D8 +#define PCSR2_D9 _pcsr2.bit._D9 +#define PCSR2_D10 _pcsr2.bit._D10 +#define PCSR2_D11 _pcsr2.bit._D11 +#define PCSR2_D12 _pcsr2.bit._D12 +#define PCSR2_D13 _pcsr2.bit._D13 +#define PCSR2_D14 _pcsr2.bit._D14 +#define PCSR2_D15 _pcsr2.bit._D15 +#define PCSR2_D _pcsr2.bitc._D +__IO_EXTERN __io PDUT2STR _pdut2; +#define PDUT2 _pdut2.word +#define PDUT2_D0 _pdut2.bit._D0 +#define PDUT2_D1 _pdut2.bit._D1 +#define PDUT2_D2 _pdut2.bit._D2 +#define PDUT2_D3 _pdut2.bit._D3 +#define PDUT2_D4 _pdut2.bit._D4 +#define PDUT2_D5 _pdut2.bit._D5 +#define PDUT2_D6 _pdut2.bit._D6 +#define PDUT2_D7 _pdut2.bit._D7 +#define PDUT2_D8 _pdut2.bit._D8 +#define PDUT2_D9 _pdut2.bit._D9 +#define PDUT2_D10 _pdut2.bit._D10 +#define PDUT2_D11 _pdut2.bit._D11 +#define PDUT2_D12 _pdut2.bit._D12 +#define PDUT2_D13 _pdut2.bit._D13 +#define PDUT2_D14 _pdut2.bit._D14 +#define PDUT2_D15 _pdut2.bit._D15 +#define PDUT2_D _pdut2.bitc._D +__IO_EXTERN __io PCN2STR _pcn2; +#define PCN2 _pcn2.word +#define PCN2_OSEL _pcn2.bit._OSEL +#define PCN2_OE _pcn2.bit._OE +#define PCN2_IRS0 _pcn2.bit._IRS0 +#define PCN2_IRS1 _pcn2.bit._IRS1 +#define PCN2_IRQF _pcn2.bit._IRQF +#define PCN2_IREN _pcn2.bit._IREN +#define PCN2_EGS0 _pcn2.bit._EGS0 +#define PCN2_EGS1 _pcn2.bit._EGS1 +#define PCN2_PGMS _pcn2.bit._PGMS +#define PCN2_CKS0 _pcn2.bit._CKS0 +#define PCN2_CKS1 _pcn2.bit._CKS1 +#define PCN2_RTRG _pcn2.bit._RTRG +#define PCN2_MDSE _pcn2.bit._MDSE +#define PCN2_STGR _pcn2.bit._STGR +#define PCN2_CNTE _pcn2.bit._CNTE +#define PCN2_IRS _pcn2.bitc._IRS +#define PCN2_EGS _pcn2.bitc._EGS +#define PCN2_CKS _pcn2.bitc._CKS +__IO_EXTERN __io PCNL2STR _pcnl2; +#define PCNL2 _pcnl2.byte +#define PCNL2_OSEL _pcnl2.bit._OSEL +#define PCNL2_OE _pcnl2.bit._OE +#define PCNL2_IRS0 _pcnl2.bit._IRS0 +#define PCNL2_IRS1 _pcnl2.bit._IRS1 +#define PCNL2_IRQF _pcnl2.bit._IRQF +#define PCNL2_IREN _pcnl2.bit._IREN +#define PCNL2_EGS0 _pcnl2.bit._EGS0 +#define PCNL2_EGS1 _pcnl2.bit._EGS1 +#define PCNL2_IRS _pcnl2.bitc._IRS +#define PCNL2_EGS _pcnl2.bitc._EGS +__IO_EXTERN __io PCNH2STR _pcnh2; +#define PCNH2 _pcnh2.byte +#define PCNH2_PGMS _pcnh2.bit._PGMS +#define PCNH2_CKS0 _pcnh2.bit._CKS0 +#define PCNH2_CKS1 _pcnh2.bit._CKS1 +#define PCNH2_RTRG _pcnh2.bit._RTRG +#define PCNH2_MDSE _pcnh2.bit._MDSE +#define PCNH2_STGR _pcnh2.bit._STGR +#define PCNH2_CNTE _pcnh2.bit._CNTE +#define PCNH2_CKS _pcnh2.bitc._CKS +__IO_EXTERN __io PTMR3STR _ptmr3; +#define PTMR3 _ptmr3.word +#define PTMR3_D0 _ptmr3.bit._D0 +#define PTMR3_D1 _ptmr3.bit._D1 +#define PTMR3_D2 _ptmr3.bit._D2 +#define PTMR3_D3 _ptmr3.bit._D3 +#define PTMR3_D4 _ptmr3.bit._D4 +#define PTMR3_D5 _ptmr3.bit._D5 +#define PTMR3_D6 _ptmr3.bit._D6 +#define PTMR3_D7 _ptmr3.bit._D7 +#define PTMR3_D8 _ptmr3.bit._D8 +#define PTMR3_D9 _ptmr3.bit._D9 +#define PTMR3_D10 _ptmr3.bit._D10 +#define PTMR3_D11 _ptmr3.bit._D11 +#define PTMR3_D12 _ptmr3.bit._D12 +#define PTMR3_D13 _ptmr3.bit._D13 +#define PTMR3_D14 _ptmr3.bit._D14 +#define PTMR3_D15 _ptmr3.bit._D15 +#define PTMR3_D _ptmr3.bitc._D +__IO_EXTERN __io PCSR3STR _pcsr3; +#define PCSR3 _pcsr3.word +#define PCSR3_D0 _pcsr3.bit._D0 +#define PCSR3_D1 _pcsr3.bit._D1 +#define PCSR3_D2 _pcsr3.bit._D2 +#define PCSR3_D3 _pcsr3.bit._D3 +#define PCSR3_D4 _pcsr3.bit._D4 +#define PCSR3_D5 _pcsr3.bit._D5 +#define PCSR3_D6 _pcsr3.bit._D6 +#define PCSR3_D7 _pcsr3.bit._D7 +#define PCSR3_D8 _pcsr3.bit._D8 +#define PCSR3_D9 _pcsr3.bit._D9 +#define PCSR3_D10 _pcsr3.bit._D10 +#define PCSR3_D11 _pcsr3.bit._D11 +#define PCSR3_D12 _pcsr3.bit._D12 +#define PCSR3_D13 _pcsr3.bit._D13 +#define PCSR3_D14 _pcsr3.bit._D14 +#define PCSR3_D15 _pcsr3.bit._D15 +#define PCSR3_D _pcsr3.bitc._D +__IO_EXTERN __io PDUT3STR _pdut3; +#define PDUT3 _pdut3.word +#define PDUT3_D0 _pdut3.bit._D0 +#define PDUT3_D1 _pdut3.bit._D1 +#define PDUT3_D2 _pdut3.bit._D2 +#define PDUT3_D3 _pdut3.bit._D3 +#define PDUT3_D4 _pdut3.bit._D4 +#define PDUT3_D5 _pdut3.bit._D5 +#define PDUT3_D6 _pdut3.bit._D6 +#define PDUT3_D7 _pdut3.bit._D7 +#define PDUT3_D8 _pdut3.bit._D8 +#define PDUT3_D9 _pdut3.bit._D9 +#define PDUT3_D10 _pdut3.bit._D10 +#define PDUT3_D11 _pdut3.bit._D11 +#define PDUT3_D12 _pdut3.bit._D12 +#define PDUT3_D13 _pdut3.bit._D13 +#define PDUT3_D14 _pdut3.bit._D14 +#define PDUT3_D15 _pdut3.bit._D15 +#define PDUT3_D _pdut3.bitc._D +__IO_EXTERN __io PCN3STR _pcn3; +#define PCN3 _pcn3.word +#define PCN3_OSEL _pcn3.bit._OSEL +#define PCN3_OE _pcn3.bit._OE +#define PCN3_IRS0 _pcn3.bit._IRS0 +#define PCN3_IRS1 _pcn3.bit._IRS1 +#define PCN3_IRQF _pcn3.bit._IRQF +#define PCN3_IREN _pcn3.bit._IREN +#define PCN3_EGS0 _pcn3.bit._EGS0 +#define PCN3_EGS1 _pcn3.bit._EGS1 +#define PCN3_PGMS _pcn3.bit._PGMS +#define PCN3_CKS0 _pcn3.bit._CKS0 +#define PCN3_CKS1 _pcn3.bit._CKS1 +#define PCN3_RTRG _pcn3.bit._RTRG +#define PCN3_MDSE _pcn3.bit._MDSE +#define PCN3_STGR _pcn3.bit._STGR +#define PCN3_CNTE _pcn3.bit._CNTE +#define PCN3_IRS _pcn3.bitc._IRS +#define PCN3_EGS _pcn3.bitc._EGS +#define PCN3_CKS _pcn3.bitc._CKS +__IO_EXTERN __io PCNL3STR _pcnl3; +#define PCNL3 _pcnl3.byte +#define PCNL3_OSEL _pcnl3.bit._OSEL +#define PCNL3_OE _pcnl3.bit._OE +#define PCNL3_IRS0 _pcnl3.bit._IRS0 +#define PCNL3_IRS1 _pcnl3.bit._IRS1 +#define PCNL3_IRQF _pcnl3.bit._IRQF +#define PCNL3_IREN _pcnl3.bit._IREN +#define PCNL3_EGS0 _pcnl3.bit._EGS0 +#define PCNL3_EGS1 _pcnl3.bit._EGS1 +#define PCNL3_IRS _pcnl3.bitc._IRS +#define PCNL3_EGS _pcnl3.bitc._EGS +__IO_EXTERN __io PCNH3STR _pcnh3; +#define PCNH3 _pcnh3.byte +#define PCNH3_PGMS _pcnh3.bit._PGMS +#define PCNH3_CKS0 _pcnh3.bit._CKS0 +#define PCNH3_CKS1 _pcnh3.bit._CKS1 +#define PCNH3_RTRG _pcnh3.bit._RTRG +#define PCNH3_MDSE _pcnh3.bit._MDSE +#define PCNH3_STGR _pcnh3.bit._STGR +#define PCNH3_CNTE _pcnh3.bit._CNTE +#define PCNH3_CKS _pcnh3.bitc._CKS +__IO_EXTERN __io GCN11STR _gcn11; +#define GCN11 _gcn11.word +#define GCN11_TSEL00 _gcn11.bit._TSEL00 +#define GCN11_TSEL01 _gcn11.bit._TSEL01 +#define GCN11_TSEL02 _gcn11.bit._TSEL02 +#define GCN11_TSEL03 _gcn11.bit._TSEL03 +#define GCN11_TSEL10 _gcn11.bit._TSEL10 +#define GCN11_TSEL11 _gcn11.bit._TSEL11 +#define GCN11_TSEL12 _gcn11.bit._TSEL12 +#define GCN11_TSEL13 _gcn11.bit._TSEL13 +#define GCN11_TSEL20 _gcn11.bit._TSEL20 +#define GCN11_TSEL21 _gcn11.bit._TSEL21 +#define GCN11_TSEL22 _gcn11.bit._TSEL22 +#define GCN11_TSEL23 _gcn11.bit._TSEL23 +#define GCN11_TSEL30 _gcn11.bit._TSEL30 +#define GCN11_TSEL31 _gcn11.bit._TSEL31 +#define GCN11_TSEL32 _gcn11.bit._TSEL32 +#define GCN11_TSEL33 _gcn11.bit._TSEL33 +#define GCN11_TSEL0 _gcn11.bitc._TSEL0 +#define GCN11_TSEL1 _gcn11.bitc._TSEL1 +#define GCN11_TSEL2 _gcn11.bitc._TSEL2 +#define GCN11_TSEL3 _gcn11.bitc._TSEL3 +__IO_EXTERN __io GCN1L1STR _gcn1l1; +#define GCN1L1 _gcn1l1.byte +#define GCN1L1_TSEL00 _gcn1l1.bit._TSEL00 +#define GCN1L1_TSEL01 _gcn1l1.bit._TSEL01 +#define GCN1L1_TSEL02 _gcn1l1.bit._TSEL02 +#define GCN1L1_TSEL03 _gcn1l1.bit._TSEL03 +#define GCN1L1_TSEL10 _gcn1l1.bit._TSEL10 +#define GCN1L1_TSEL11 _gcn1l1.bit._TSEL11 +#define GCN1L1_TSEL12 _gcn1l1.bit._TSEL12 +#define GCN1L1_TSEL13 _gcn1l1.bit._TSEL13 +#define GCN1L1_TSEL0 _gcn1l1.bitc._TSEL0 +#define GCN1L1_TSEL1 _gcn1l1.bitc._TSEL1 +__IO_EXTERN __io GCN1H1STR _gcn1h1; +#define GCN1H1 _gcn1h1.byte +#define GCN1H1_TSEL20 _gcn1h1.bit._TSEL20 +#define GCN1H1_TSEL21 _gcn1h1.bit._TSEL21 +#define GCN1H1_TSEL22 _gcn1h1.bit._TSEL22 +#define GCN1H1_TSEL23 _gcn1h1.bit._TSEL23 +#define GCN1H1_TSEL30 _gcn1h1.bit._TSEL30 +#define GCN1H1_TSEL31 _gcn1h1.bit._TSEL31 +#define GCN1H1_TSEL32 _gcn1h1.bit._TSEL32 +#define GCN1H1_TSEL33 _gcn1h1.bit._TSEL33 +#define GCN1H1_TSEL2 _gcn1h1.bitc._TSEL2 +#define GCN1H1_TSEL3 _gcn1h1.bitc._TSEL3 +__IO_EXTERN __io GCN21STR _gcn21; +#define GCN21 _gcn21.word +#define GCN21_EN0 _gcn21.bit._EN0 +#define GCN21_EN1 _gcn21.bit._EN1 +#define GCN21_EN2 _gcn21.bit._EN2 +#define GCN21_EN3 _gcn21.bit._EN3 +#define GCN21_CKSEL0 _gcn21.bit._CKSEL0 +#define GCN21_CKSEL1 _gcn21.bit._CKSEL1 +#define GCN21_CKSEL2 _gcn21.bit._CKSEL2 +#define GCN21_CKSEL3 _gcn21.bit._CKSEL3 +#define GCN21_CKSEL _gcn21.bitc._CKSEL +__IO_EXTERN __io GCN2L1STR _gcn2l1; +#define GCN2L1 _gcn2l1.byte +#define GCN2L1_EN0 _gcn2l1.bit._EN0 +#define GCN2L1_EN1 _gcn2l1.bit._EN1 +#define GCN2L1_EN2 _gcn2l1.bit._EN2 +#define GCN2L1_EN3 _gcn2l1.bit._EN3 +__IO_EXTERN __io GCN2H1STR _gcn2h1; +#define GCN2H1 _gcn2h1.byte +#define GCN2H1_CKSEL0 _gcn2h1.bit._CKSEL0 +#define GCN2H1_CKSEL1 _gcn2h1.bit._CKSEL1 +#define GCN2H1_CKSEL2 _gcn2h1.bit._CKSEL2 +#define GCN2H1_CKSEL3 _gcn2h1.bit._CKSEL3 +#define GCN2H1_CKSEL _gcn2h1.bitc._CKSEL +__IO_EXTERN __io PTMR4STR _ptmr4; +#define PTMR4 _ptmr4.word +#define PTMR4_D0 _ptmr4.bit._D0 +#define PTMR4_D1 _ptmr4.bit._D1 +#define PTMR4_D2 _ptmr4.bit._D2 +#define PTMR4_D3 _ptmr4.bit._D3 +#define PTMR4_D4 _ptmr4.bit._D4 +#define PTMR4_D5 _ptmr4.bit._D5 +#define PTMR4_D6 _ptmr4.bit._D6 +#define PTMR4_D7 _ptmr4.bit._D7 +#define PTMR4_D8 _ptmr4.bit._D8 +#define PTMR4_D9 _ptmr4.bit._D9 +#define PTMR4_D10 _ptmr4.bit._D10 +#define PTMR4_D11 _ptmr4.bit._D11 +#define PTMR4_D12 _ptmr4.bit._D12 +#define PTMR4_D13 _ptmr4.bit._D13 +#define PTMR4_D14 _ptmr4.bit._D14 +#define PTMR4_D15 _ptmr4.bit._D15 +#define PTMR4_D _ptmr4.bitc._D +__IO_EXTERN __io PCSR4STR _pcsr4; +#define PCSR4 _pcsr4.word +#define PCSR4_D0 _pcsr4.bit._D0 +#define PCSR4_D1 _pcsr4.bit._D1 +#define PCSR4_D2 _pcsr4.bit._D2 +#define PCSR4_D3 _pcsr4.bit._D3 +#define PCSR4_D4 _pcsr4.bit._D4 +#define PCSR4_D5 _pcsr4.bit._D5 +#define PCSR4_D6 _pcsr4.bit._D6 +#define PCSR4_D7 _pcsr4.bit._D7 +#define PCSR4_D8 _pcsr4.bit._D8 +#define PCSR4_D9 _pcsr4.bit._D9 +#define PCSR4_D10 _pcsr4.bit._D10 +#define PCSR4_D11 _pcsr4.bit._D11 +#define PCSR4_D12 _pcsr4.bit._D12 +#define PCSR4_D13 _pcsr4.bit._D13 +#define PCSR4_D14 _pcsr4.bit._D14 +#define PCSR4_D15 _pcsr4.bit._D15 +#define PCSR4_D _pcsr4.bitc._D +__IO_EXTERN __io PDUT4STR _pdut4; +#define PDUT4 _pdut4.word +#define PDUT4_D0 _pdut4.bit._D0 +#define PDUT4_D1 _pdut4.bit._D1 +#define PDUT4_D2 _pdut4.bit._D2 +#define PDUT4_D3 _pdut4.bit._D3 +#define PDUT4_D4 _pdut4.bit._D4 +#define PDUT4_D5 _pdut4.bit._D5 +#define PDUT4_D6 _pdut4.bit._D6 +#define PDUT4_D7 _pdut4.bit._D7 +#define PDUT4_D8 _pdut4.bit._D8 +#define PDUT4_D9 _pdut4.bit._D9 +#define PDUT4_D10 _pdut4.bit._D10 +#define PDUT4_D11 _pdut4.bit._D11 +#define PDUT4_D12 _pdut4.bit._D12 +#define PDUT4_D13 _pdut4.bit._D13 +#define PDUT4_D14 _pdut4.bit._D14 +#define PDUT4_D15 _pdut4.bit._D15 +#define PDUT4_D _pdut4.bitc._D +__IO_EXTERN __io PCN4STR _pcn4; +#define PCN4 _pcn4.word +#define PCN4_OSEL _pcn4.bit._OSEL +#define PCN4_OE _pcn4.bit._OE +#define PCN4_IRS0 _pcn4.bit._IRS0 +#define PCN4_IRS1 _pcn4.bit._IRS1 +#define PCN4_IRQF _pcn4.bit._IRQF +#define PCN4_IREN _pcn4.bit._IREN +#define PCN4_EGS0 _pcn4.bit._EGS0 +#define PCN4_EGS1 _pcn4.bit._EGS1 +#define PCN4_PGMS _pcn4.bit._PGMS +#define PCN4_CKS0 _pcn4.bit._CKS0 +#define PCN4_CKS1 _pcn4.bit._CKS1 +#define PCN4_RTRG _pcn4.bit._RTRG +#define PCN4_MDSE _pcn4.bit._MDSE +#define PCN4_STGR _pcn4.bit._STGR +#define PCN4_CNTE _pcn4.bit._CNTE +#define PCN4_IRS _pcn4.bitc._IRS +#define PCN4_EGS _pcn4.bitc._EGS +#define PCN4_CKS _pcn4.bitc._CKS +__IO_EXTERN __io PCNL4STR _pcnl4; +#define PCNL4 _pcnl4.byte +#define PCNL4_OSEL _pcnl4.bit._OSEL +#define PCNL4_OE _pcnl4.bit._OE +#define PCNL4_IRS0 _pcnl4.bit._IRS0 +#define PCNL4_IRS1 _pcnl4.bit._IRS1 +#define PCNL4_IRQF _pcnl4.bit._IRQF +#define PCNL4_IREN _pcnl4.bit._IREN +#define PCNL4_EGS0 _pcnl4.bit._EGS0 +#define PCNL4_EGS1 _pcnl4.bit._EGS1 +#define PCNL4_IRS _pcnl4.bitc._IRS +#define PCNL4_EGS _pcnl4.bitc._EGS +__IO_EXTERN __io PCNH4STR _pcnh4; +#define PCNH4 _pcnh4.byte +#define PCNH4_PGMS _pcnh4.bit._PGMS +#define PCNH4_CKS0 _pcnh4.bit._CKS0 +#define PCNH4_CKS1 _pcnh4.bit._CKS1 +#define PCNH4_RTRG _pcnh4.bit._RTRG +#define PCNH4_MDSE _pcnh4.bit._MDSE +#define PCNH4_STGR _pcnh4.bit._STGR +#define PCNH4_CNTE _pcnh4.bit._CNTE +#define PCNH4_CKS _pcnh4.bitc._CKS +__IO_EXTERN __io PTMR5STR _ptmr5; +#define PTMR5 _ptmr5.word +#define PTMR5_D0 _ptmr5.bit._D0 +#define PTMR5_D1 _ptmr5.bit._D1 +#define PTMR5_D2 _ptmr5.bit._D2 +#define PTMR5_D3 _ptmr5.bit._D3 +#define PTMR5_D4 _ptmr5.bit._D4 +#define PTMR5_D5 _ptmr5.bit._D5 +#define PTMR5_D6 _ptmr5.bit._D6 +#define PTMR5_D7 _ptmr5.bit._D7 +#define PTMR5_D8 _ptmr5.bit._D8 +#define PTMR5_D9 _ptmr5.bit._D9 +#define PTMR5_D10 _ptmr5.bit._D10 +#define PTMR5_D11 _ptmr5.bit._D11 +#define PTMR5_D12 _ptmr5.bit._D12 +#define PTMR5_D13 _ptmr5.bit._D13 +#define PTMR5_D14 _ptmr5.bit._D14 +#define PTMR5_D15 _ptmr5.bit._D15 +#define PTMR5_D _ptmr5.bitc._D +__IO_EXTERN __io PCSR5STR _pcsr5; +#define PCSR5 _pcsr5.word +#define PCSR5_D0 _pcsr5.bit._D0 +#define PCSR5_D1 _pcsr5.bit._D1 +#define PCSR5_D2 _pcsr5.bit._D2 +#define PCSR5_D3 _pcsr5.bit._D3 +#define PCSR5_D4 _pcsr5.bit._D4 +#define PCSR5_D5 _pcsr5.bit._D5 +#define PCSR5_D6 _pcsr5.bit._D6 +#define PCSR5_D7 _pcsr5.bit._D7 +#define PCSR5_D8 _pcsr5.bit._D8 +#define PCSR5_D9 _pcsr5.bit._D9 +#define PCSR5_D10 _pcsr5.bit._D10 +#define PCSR5_D11 _pcsr5.bit._D11 +#define PCSR5_D12 _pcsr5.bit._D12 +#define PCSR5_D13 _pcsr5.bit._D13 +#define PCSR5_D14 _pcsr5.bit._D14 +#define PCSR5_D15 _pcsr5.bit._D15 +#define PCSR5_D _pcsr5.bitc._D +__IO_EXTERN __io PDUT5STR _pdut5; +#define PDUT5 _pdut5.word +#define PDUT5_D0 _pdut5.bit._D0 +#define PDUT5_D1 _pdut5.bit._D1 +#define PDUT5_D2 _pdut5.bit._D2 +#define PDUT5_D3 _pdut5.bit._D3 +#define PDUT5_D4 _pdut5.bit._D4 +#define PDUT5_D5 _pdut5.bit._D5 +#define PDUT5_D6 _pdut5.bit._D6 +#define PDUT5_D7 _pdut5.bit._D7 +#define PDUT5_D8 _pdut5.bit._D8 +#define PDUT5_D9 _pdut5.bit._D9 +#define PDUT5_D10 _pdut5.bit._D10 +#define PDUT5_D11 _pdut5.bit._D11 +#define PDUT5_D12 _pdut5.bit._D12 +#define PDUT5_D13 _pdut5.bit._D13 +#define PDUT5_D14 _pdut5.bit._D14 +#define PDUT5_D15 _pdut5.bit._D15 +#define PDUT5_D _pdut5.bitc._D +__IO_EXTERN __io PCN5STR _pcn5; +#define PCN5 _pcn5.word +#define PCN5_OSEL _pcn5.bit._OSEL +#define PCN5_OE _pcn5.bit._OE +#define PCN5_IRS0 _pcn5.bit._IRS0 +#define PCN5_IRS1 _pcn5.bit._IRS1 +#define PCN5_IRQF _pcn5.bit._IRQF +#define PCN5_IREN _pcn5.bit._IREN +#define PCN5_EGS0 _pcn5.bit._EGS0 +#define PCN5_EGS1 _pcn5.bit._EGS1 +#define PCN5_PGMS _pcn5.bit._PGMS +#define PCN5_CKS0 _pcn5.bit._CKS0 +#define PCN5_CKS1 _pcn5.bit._CKS1 +#define PCN5_RTRG _pcn5.bit._RTRG +#define PCN5_MDSE _pcn5.bit._MDSE +#define PCN5_STGR _pcn5.bit._STGR +#define PCN5_CNTE _pcn5.bit._CNTE +#define PCN5_IRS _pcn5.bitc._IRS +#define PCN5_EGS _pcn5.bitc._EGS +#define PCN5_CKS _pcn5.bitc._CKS +__IO_EXTERN __io PCNL5STR _pcnl5; +#define PCNL5 _pcnl5.byte +#define PCNL5_OSEL _pcnl5.bit._OSEL +#define PCNL5_OE _pcnl5.bit._OE +#define PCNL5_IRS0 _pcnl5.bit._IRS0 +#define PCNL5_IRS1 _pcnl5.bit._IRS1 +#define PCNL5_IRQF _pcnl5.bit._IRQF +#define PCNL5_IREN _pcnl5.bit._IREN +#define PCNL5_EGS0 _pcnl5.bit._EGS0 +#define PCNL5_EGS1 _pcnl5.bit._EGS1 +#define PCNL5_IRS _pcnl5.bitc._IRS +#define PCNL5_EGS _pcnl5.bitc._EGS +__IO_EXTERN __io PCNH5STR _pcnh5; +#define PCNH5 _pcnh5.byte +#define PCNH5_PGMS _pcnh5.bit._PGMS +#define PCNH5_CKS0 _pcnh5.bit._CKS0 +#define PCNH5_CKS1 _pcnh5.bit._CKS1 +#define PCNH5_RTRG _pcnh5.bit._RTRG +#define PCNH5_MDSE _pcnh5.bit._MDSE +#define PCNH5_STGR _pcnh5.bit._STGR +#define PCNH5_CNTE _pcnh5.bit._CNTE +#define PCNH5_CKS _pcnh5.bitc._CKS +__IO_EXTERN __io IBSR0STR _ibsr0; +#define IBSR0 _ibsr0.byte +#define IBSR0_ADT _ibsr0.bit._ADT +#define IBSR0_GCA _ibsr0.bit._GCA +#define IBSR0_AAS _ibsr0.bit._AAS +#define IBSR0_TRX _ibsr0.bit._TRX +#define IBSR0_LRB _ibsr0.bit._LRB +#define IBSR0_AL _ibsr0.bit._AL +#define IBSR0_RSC _ibsr0.bit._RSC +#define IBSR0_BB _ibsr0.bit._BB +__IO_EXTERN __io IBCR0STR _ibcr0; +#define IBCR0 _ibcr0.byte +#define IBCR0_INT _ibcr0.bit._INT +#define IBCR0_INTE _ibcr0.bit._INTE +#define IBCR0_GCAA _ibcr0.bit._GCAA +#define IBCR0_ACK _ibcr0.bit._ACK +#define IBCR0_MSS _ibcr0.bit._MSS +#define IBCR0_SCC _ibcr0.bit._SCC +#define IBCR0_BEIE _ibcr0.bit._BEIE +#define IBCR0_BER _ibcr0.bit._BER +__IO_EXTERN __io ITBA0STR _itba0; +#define ITBA0 _itba0.word +#define ITBA0_TA0 _itba0.bit._TA0 +#define ITBA0_TA1 _itba0.bit._TA1 +#define ITBA0_TA2 _itba0.bit._TA2 +#define ITBA0_TA3 _itba0.bit._TA3 +#define ITBA0_TA4 _itba0.bit._TA4 +#define ITBA0_TA5 _itba0.bit._TA5 +#define ITBA0_TA6 _itba0.bit._TA6 +#define ITBA0_TA7 _itba0.bit._TA7 +#define ITBA0_TA8 _itba0.bit._TA8 +#define ITBA0_TA9 _itba0.bit._TA9 +#define ITBA0_TA _itba0.bitc._TA +__IO_EXTERN __io ITBAL0STR _itbal0; +#define ITBAL0 _itbal0.byte +#define ITBAL0_TA0 _itbal0.bit._TA0 +#define ITBAL0_TA1 _itbal0.bit._TA1 +#define ITBAL0_TA2 _itbal0.bit._TA2 +#define ITBAL0_TA3 _itbal0.bit._TA3 +#define ITBAL0_TA4 _itbal0.bit._TA4 +#define ITBAL0_TA5 _itbal0.bit._TA5 +#define ITBAL0_TA6 _itbal0.bit._TA6 +#define ITBAL0_TA7 _itbal0.bit._TA7 +__IO_EXTERN __io ITBAH0STR _itbah0; +#define ITBAH0 _itbah0.byte +#define ITBAH0_TA8 _itbah0.bit._TA8 +#define ITBAH0_TA9 _itbah0.bit._TA9 +__IO_EXTERN __io ITMK0STR _itmk0; +#define ITMK0 _itmk0.word +#define ITMK0_TM0 _itmk0.bit._TM0 +#define ITMK0_TM1 _itmk0.bit._TM1 +#define ITMK0_TM2 _itmk0.bit._TM2 +#define ITMK0_TM3 _itmk0.bit._TM3 +#define ITMK0_TM4 _itmk0.bit._TM4 +#define ITMK0_TM5 _itmk0.bit._TM5 +#define ITMK0_TM6 _itmk0.bit._TM6 +#define ITMK0_TM7 _itmk0.bit._TM7 +#define ITMK0_TM8 _itmk0.bit._TM8 +#define ITMK0_TM9 _itmk0.bit._TM9 +#define ITMK0_RAL _itmk0.bit._RAL +#define ITMK0_ENTB _itmk0.bit._ENTB +#define ITMK0_TM _itmk0.bitc._TM +__IO_EXTERN __io ITMKL0STR _itmkl0; +#define ITMKL0 _itmkl0.byte +#define ITMKL0_TM0 _itmkl0.bit._TM0 +#define ITMKL0_TM1 _itmkl0.bit._TM1 +#define ITMKL0_TM2 _itmkl0.bit._TM2 +#define ITMKL0_TM3 _itmkl0.bit._TM3 +#define ITMKL0_TM4 _itmkl0.bit._TM4 +#define ITMKL0_TM5 _itmkl0.bit._TM5 +#define ITMKL0_TM6 _itmkl0.bit._TM6 +#define ITMKL0_TM7 _itmkl0.bit._TM7 +__IO_EXTERN __io ITMKH0STR _itmkh0; +#define ITMKH0 _itmkh0.byte +#define ITMKH0_TM8 _itmkh0.bit._TM8 +#define ITMKH0_TM9 _itmkh0.bit._TM9 +#define ITMKH0_RAL _itmkh0.bit._RAL +#define ITMKH0_ENTB _itmkh0.bit._ENTB +__IO_EXTERN __io ISBA0STR _isba0; +#define ISBA0 _isba0.byte +#define ISBA0_SA0 _isba0.bit._SA0 +#define ISBA0_SA1 _isba0.bit._SA1 +#define ISBA0_SA2 _isba0.bit._SA2 +#define ISBA0_SA3 _isba0.bit._SA3 +#define ISBA0_SA4 _isba0.bit._SA4 +#define ISBA0_SA5 _isba0.bit._SA5 +#define ISBA0_SA6 _isba0.bit._SA6 +#define ISBA0_SA _isba0.bitc._SA +__IO_EXTERN __io ISMK0STR _ismk0; +#define ISMK0 _ismk0.byte +#define ISMK0_SM0 _ismk0.bit._SM0 +#define ISMK0_SM1 _ismk0.bit._SM1 +#define ISMK0_SM2 _ismk0.bit._SM2 +#define ISMK0_SM3 _ismk0.bit._SM3 +#define ISMK0_SM4 _ismk0.bit._SM4 +#define ISMK0_SM5 _ismk0.bit._SM5 +#define ISMK0_SM6 _ismk0.bit._SM6 +#define ISMK0_ENSB _ismk0.bit._ENSB +#define ISMK0_SM _ismk0.bitc._SM +__IO_EXTERN __io IDAR0STR _idar0; +#define IDAR0 _idar0.byte +#define IDAR0_D0 _idar0.bit._D0 +#define IDAR0_D1 _idar0.bit._D1 +#define IDAR0_D2 _idar0.bit._D2 +#define IDAR0_D3 _idar0.bit._D3 +#define IDAR0_D4 _idar0.bit._D4 +#define IDAR0_D5 _idar0.bit._D5 +#define IDAR0_D6 _idar0.bit._D6 +#define IDAR0_D7 _idar0.bit._D7 +__IO_EXTERN __io ICCR0STR _iccr0; +#define ICCR0 _iccr0.byte +#define ICCR0_CS0 _iccr0.bit._CS0 +#define ICCR0_CS1 _iccr0.bit._CS1 +#define ICCR0_CS2 _iccr0.bit._CS2 +#define ICCR0_CS3 _iccr0.bit._CS3 +#define ICCR0_CS4 _iccr0.bit._CS4 +#define ICCR0_EN _iccr0.bit._EN +#define ICCR0_NSF _iccr0.bit._NSF +#define ICCR0_CS _iccr0.bitc._CS +__IO_EXTERN __io IBSR1STR _ibsr1; +#define IBSR1 _ibsr1.byte +#define IBSR1_ADT _ibsr1.bit._ADT +#define IBSR1_GCA _ibsr1.bit._GCA +#define IBSR1_AAS _ibsr1.bit._AAS +#define IBSR1_TRX _ibsr1.bit._TRX +#define IBSR1_LRB _ibsr1.bit._LRB +#define IBSR1_AL _ibsr1.bit._AL +#define IBSR1_RSC _ibsr1.bit._RSC +#define IBSR1_BB _ibsr1.bit._BB +__IO_EXTERN __io IBCR1STR _ibcr1; +#define IBCR1 _ibcr1.byte +#define IBCR1_INT _ibcr1.bit._INT +#define IBCR1_INTE _ibcr1.bit._INTE +#define IBCR1_GCAA _ibcr1.bit._GCAA +#define IBCR1_ACK _ibcr1.bit._ACK +#define IBCR1_MSS _ibcr1.bit._MSS +#define IBCR1_SCC _ibcr1.bit._SCC +#define IBCR1_BEIE _ibcr1.bit._BEIE +#define IBCR1_BER _ibcr1.bit._BER +__IO_EXTERN __io ITBA1STR _itba1; +#define ITBA1 _itba1.word +#define ITBA1_TA0 _itba1.bit._TA0 +#define ITBA1_TA1 _itba1.bit._TA1 +#define ITBA1_TA2 _itba1.bit._TA2 +#define ITBA1_TA3 _itba1.bit._TA3 +#define ITBA1_TA4 _itba1.bit._TA4 +#define ITBA1_TA5 _itba1.bit._TA5 +#define ITBA1_TA6 _itba1.bit._TA6 +#define ITBA1_TA7 _itba1.bit._TA7 +#define ITBA1_TA8 _itba1.bit._TA8 +#define ITBA1_TA9 _itba1.bit._TA9 +#define ITBA1_TA _itba1.bitc._TA +__IO_EXTERN __io ITBAL1STR _itbal1; +#define ITBAL1 _itbal1.byte +#define ITBAL1_TA0 _itbal1.bit._TA0 +#define ITBAL1_TA1 _itbal1.bit._TA1 +#define ITBAL1_TA2 _itbal1.bit._TA2 +#define ITBAL1_TA3 _itbal1.bit._TA3 +#define ITBAL1_TA4 _itbal1.bit._TA4 +#define ITBAL1_TA5 _itbal1.bit._TA5 +#define ITBAL1_TA6 _itbal1.bit._TA6 +#define ITBAL1_TA7 _itbal1.bit._TA7 +__IO_EXTERN __io ITBAH1STR _itbah1; +#define ITBAH1 _itbah1.byte +#define ITBAH1_TA8 _itbah1.bit._TA8 +#define ITBAH1_TA9 _itbah1.bit._TA9 +__IO_EXTERN __io ITMK1STR _itmk1; +#define ITMK1 _itmk1.word +#define ITMK1_TM0 _itmk1.bit._TM0 +#define ITMK1_TM1 _itmk1.bit._TM1 +#define ITMK1_TM2 _itmk1.bit._TM2 +#define ITMK1_TM3 _itmk1.bit._TM3 +#define ITMK1_TM4 _itmk1.bit._TM4 +#define ITMK1_TM5 _itmk1.bit._TM5 +#define ITMK1_TM6 _itmk1.bit._TM6 +#define ITMK1_TM7 _itmk1.bit._TM7 +#define ITMK1_TM8 _itmk1.bit._TM8 +#define ITMK1_TM9 _itmk1.bit._TM9 +#define ITMK1_RAL _itmk1.bit._RAL +#define ITMK1_ENTB _itmk1.bit._ENTB +#define ITMK1_TM _itmk1.bitc._TM +__IO_EXTERN __io ITMKL1STR _itmkl1; +#define ITMKL1 _itmkl1.byte +#define ITMKL1_TM0 _itmkl1.bit._TM0 +#define ITMKL1_TM1 _itmkl1.bit._TM1 +#define ITMKL1_TM2 _itmkl1.bit._TM2 +#define ITMKL1_TM3 _itmkl1.bit._TM3 +#define ITMKL1_TM4 _itmkl1.bit._TM4 +#define ITMKL1_TM5 _itmkl1.bit._TM5 +#define ITMKL1_TM6 _itmkl1.bit._TM6 +#define ITMKL1_TM7 _itmkl1.bit._TM7 +__IO_EXTERN __io ITMKH1STR _itmkh1; +#define ITMKH1 _itmkh1.byte +#define ITMKH1_TM8 _itmkh1.bit._TM8 +#define ITMKH1_TM9 _itmkh1.bit._TM9 +#define ITMKH1_RAL _itmkh1.bit._RAL +#define ITMKH1_ENTB _itmkh1.bit._ENTB +__IO_EXTERN __io ISBA1STR _isba1; +#define ISBA1 _isba1.byte +#define ISBA1_SA0 _isba1.bit._SA0 +#define ISBA1_SA1 _isba1.bit._SA1 +#define ISBA1_SA2 _isba1.bit._SA2 +#define ISBA1_SA3 _isba1.bit._SA3 +#define ISBA1_SA4 _isba1.bit._SA4 +#define ISBA1_SA5 _isba1.bit._SA5 +#define ISBA1_SA6 _isba1.bit._SA6 +#define ISBA1_SA _isba1.bitc._SA +__IO_EXTERN __io ISMK1STR _ismk1; +#define ISMK1 _ismk1.byte +#define ISMK1_SM0 _ismk1.bit._SM0 +#define ISMK1_SM1 _ismk1.bit._SM1 +#define ISMK1_SM2 _ismk1.bit._SM2 +#define ISMK1_SM3 _ismk1.bit._SM3 +#define ISMK1_SM4 _ismk1.bit._SM4 +#define ISMK1_SM5 _ismk1.bit._SM5 +#define ISMK1_SM6 _ismk1.bit._SM6 +#define ISMK1_ENSB _ismk1.bit._ENSB +#define ISMK1_SM _ismk1.bitc._SM +__IO_EXTERN __io IDAR1STR _idar1; +#define IDAR1 _idar1.byte +#define IDAR1_D0 _idar1.bit._D0 +#define IDAR1_D1 _idar1.bit._D1 +#define IDAR1_D2 _idar1.bit._D2 +#define IDAR1_D3 _idar1.bit._D3 +#define IDAR1_D4 _idar1.bit._D4 +#define IDAR1_D5 _idar1.bit._D5 +#define IDAR1_D6 _idar1.bit._D6 +#define IDAR1_D7 _idar1.bit._D7 +__IO_EXTERN __io ICCR1STR _iccr1; +#define ICCR1 _iccr1.byte +#define ICCR1_CS0 _iccr1.bit._CS0 +#define ICCR1_CS1 _iccr1.bit._CS1 +#define ICCR1_CS2 _iccr1.bit._CS2 +#define ICCR1_CS3 _iccr1.bit._CS3 +#define ICCR1_CS4 _iccr1.bit._CS4 +#define ICCR1_EN _iccr1.bit._EN +#define ICCR1_NSF _iccr1.bit._NSF +#define ICCR1_CS _iccr1.bitc._CS +__IO_EXTERN __io SMR0STR _smr0; +#define SMR0 _smr0.byte +#define SMR0_SOE _smr0.bit._SOE +#define SMR0_SCKE _smr0.bit._SCKE +#define SMR0_UPCL _smr0.bit._UPCL +#define SMR0_REST _smr0.bit._REST +#define SMR0_EXT _smr0.bit._EXT +#define SMR0_OTO _smr0.bit._OTO +#define SMR0_MD0 _smr0.bit._MD0 +#define SMR0_MD1 _smr0.bit._MD1 +#define SMR0_MD _smr0.bitc._MD +__IO_EXTERN __io SCR0STR _scr0; +#define SCR0 _scr0.byte +#define SCR0_TXE _scr0.bit._TXE +#define SCR0_RXE _scr0.bit._RXE +#define SCR0_CRE _scr0.bit._CRE +#define SCR0_AD _scr0.bit._AD +#define SCR0_CL _scr0.bit._CL +#define SCR0_SBL _scr0.bit._SBL +#define SCR0_P _scr0.bit._P +#define SCR0_PEN _scr0.bit._PEN +__IO_EXTERN __io IO_BYTE _tdr0; +#define TDR0 _tdr0 +__IO_EXTERN __io IO_BYTE _rdr0; +#define RDR0 _rdr0 +__IO_EXTERN __io SSR0STR _ssr0; +#define SSR0 _ssr0.byte +#define SSR0_TIE _ssr0.bit._TIE +#define SSR0_RIE _ssr0.bit._RIE +#define SSR0_BDS _ssr0.bit._BDS +#define SSR0_TDRE _ssr0.bit._TDRE +#define SSR0_RDRF _ssr0.bit._RDRF +#define SSR0_FRE _ssr0.bit._FRE +#define SSR0_ORE _ssr0.bit._ORE +#define SSR0_PE _ssr0.bit._PE +__IO_EXTERN __io ECCR0STR _eccr0; +#define ECCR0 _eccr0.byte +#define ECCR0_TBI _eccr0.bit._TBI +#define ECCR0_RBI _eccr0.bit._RBI +#define ECCR0_BIE _eccr0.bit._BIE +#define ECCR0_SSM _eccr0.bit._SSM +#define ECCR0_SCDE _eccr0.bit._SCDE +#define ECCR0_MS _eccr0.bit._MS +#define ECCR0_LBR _eccr0.bit._LBR +#define ECCR0_INV _eccr0.bit._INV +__IO_EXTERN __io ESCR0STR _escr0; +#define ESCR0 _escr0.byte +#define ESCR0_SCES _escr0.bit._SCES +#define ESCR0_CCO _escr0.bit._CCO +#define ESCR0_SIOP _escr0.bit._SIOP +#define ESCR0_SOPE _escr0.bit._SOPE +#define ESCR0_LBL0 _escr0.bit._LBL0 +#define ESCR0_LBL1 _escr0.bit._LBL1 +#define ESCR0_LBD _escr0.bit._LBD +#define ESCR0_LBIE _escr0.bit._LBIE +#define ESCR0_LBL _escr0.bitc._LBL +__IO_EXTERN __io BGR0STR _bgr0; +#define BGR0 _bgr0.word +#define BGR0_BGR0 _bgr0.bit._BGR0 +#define BGR0_BGR1 _bgr0.bit._BGR1 +#define BGR0_BGR2 _bgr0.bit._BGR2 +#define BGR0_BGR3 _bgr0.bit._BGR3 +#define BGR0_BGR4 _bgr0.bit._BGR4 +#define BGR0_BGR5 _bgr0.bit._BGR5 +#define BGR0_BGR6 _bgr0.bit._BGR6 +#define BGR0_BGR7 _bgr0.bit._BGR7 +#define BGR0_BGR8 _bgr0.bit._BGR8 +#define BGR0_BGR9 _bgr0.bit._BGR9 +#define BGR0_BGR10 _bgr0.bit._BGR10 +#define BGR0_BGR11 _bgr0.bit._BGR11 +#define BGR0_BGR12 _bgr0.bit._BGR12 +#define BGR0_BGR13 _bgr0.bit._BGR13 +#define BGR0_BGR14 _bgr0.bit._BGR14 +#define BGR0_BGR15 _bgr0.bit._BGR15 +#define BGR0_BGR _bgr0.bitc._BGR +__IO_EXTERN __io BGRL0STR _bgrl0; +#define BGRL0 _bgrl0.byte +#define BGRL0_BGR0 _bgrl0.bit._BGR0 +#define BGRL0_BGR1 _bgrl0.bit._BGR1 +#define BGRL0_BGR2 _bgrl0.bit._BGR2 +#define BGRL0_BGR3 _bgrl0.bit._BGR3 +#define BGRL0_BGR4 _bgrl0.bit._BGR4 +#define BGRL0_BGR5 _bgrl0.bit._BGR5 +#define BGRL0_BGR6 _bgrl0.bit._BGR6 +#define BGRL0_BGR7 _bgrl0.bit._BGR7 +__IO_EXTERN __io BGRH0STR _bgrh0; +#define BGRH0 _bgrh0.byte +#define BGRH0_BGR8 _bgrh0.bit._BGR8 +#define BGRH0_BGR9 _bgrh0.bit._BGR9 +#define BGRH0_BGR10 _bgrh0.bit._BGR10 +#define BGRH0_BGR11 _bgrh0.bit._BGR11 +#define BGRH0_BGR12 _bgrh0.bit._BGR12 +#define BGRH0_BGR13 _bgrh0.bit._BGR13 +#define BGRH0_BGR14 _bgrh0.bit._BGR14 +#define BGRH0_BGR15 _bgrh0.bit._BGR15 +__IO_EXTERN __io ESIR0STR _esir0; +#define ESIR0 _esir0.byte +#define ESIR0_AICD _esir0.bit._AICD +#define ESIR0_RBI _esir0.bit._RBI +#define ESIR0_RDRF _esir0.bit._RDRF +#define ESIR0_TDRE _esir0.bit._TDRE +__IO_EXTERN __io SMR1STR _smr1; +#define SMR1 _smr1.byte +#define SMR1_SOE _smr1.bit._SOE +#define SMR1_SCKE _smr1.bit._SCKE +#define SMR1_UPCL _smr1.bit._UPCL +#define SMR1_REST _smr1.bit._REST +#define SMR1_EXT _smr1.bit._EXT +#define SMR1_OTO _smr1.bit._OTO +#define SMR1_MD0 _smr1.bit._MD0 +#define SMR1_MD1 _smr1.bit._MD1 +#define SMR1_MD _smr1.bitc._MD +__IO_EXTERN __io SCR1STR _scr1; +#define SCR1 _scr1.byte +#define SCR1_TXE _scr1.bit._TXE +#define SCR1_RXE _scr1.bit._RXE +#define SCR1_CRE _scr1.bit._CRE +#define SCR1_AD _scr1.bit._AD +#define SCR1_CL _scr1.bit._CL +#define SCR1_SBL _scr1.bit._SBL +#define SCR1_P _scr1.bit._P +#define SCR1_PEN _scr1.bit._PEN +__IO_EXTERN __io IO_BYTE _tdr1; +#define TDR1 _tdr1 +__IO_EXTERN __io IO_BYTE _rdr1; +#define RDR1 _rdr1 +__IO_EXTERN __io SSR1STR _ssr1; +#define SSR1 _ssr1.byte +#define SSR1_TIE _ssr1.bit._TIE +#define SSR1_RIE _ssr1.bit._RIE +#define SSR1_BDS _ssr1.bit._BDS +#define SSR1_TDRE _ssr1.bit._TDRE +#define SSR1_RDRF _ssr1.bit._RDRF +#define SSR1_FRE _ssr1.bit._FRE +#define SSR1_ORE _ssr1.bit._ORE +#define SSR1_PE _ssr1.bit._PE +__IO_EXTERN __io ECCR1STR _eccr1; +#define ECCR1 _eccr1.byte +#define ECCR1_TBI _eccr1.bit._TBI +#define ECCR1_RBI _eccr1.bit._RBI +#define ECCR1_BIE _eccr1.bit._BIE +#define ECCR1_SSM _eccr1.bit._SSM +#define ECCR1_SCDE _eccr1.bit._SCDE +#define ECCR1_MS _eccr1.bit._MS +#define ECCR1_LBR _eccr1.bit._LBR +#define ECCR1_INV _eccr1.bit._INV +__IO_EXTERN __io ESCR1STR _escr1; +#define ESCR1 _escr1.byte +#define ESCR1_SCES _escr1.bit._SCES +#define ESCR1_CCO _escr1.bit._CCO +#define ESCR1_SIOP _escr1.bit._SIOP +#define ESCR1_SOPE _escr1.bit._SOPE +#define ESCR1_LBL0 _escr1.bit._LBL0 +#define ESCR1_LBL1 _escr1.bit._LBL1 +#define ESCR1_LBD _escr1.bit._LBD +#define ESCR1_LBIE _escr1.bit._LBIE +#define ESCR1_LBL _escr1.bitc._LBL +__IO_EXTERN __io BGR1STR _bgr1; +#define BGR1 _bgr1.word +#define BGR1_BGR0 _bgr1.bit._BGR0 +#define BGR1_BGR1 _bgr1.bit._BGR1 +#define BGR1_BGR2 _bgr1.bit._BGR2 +#define BGR1_BGR3 _bgr1.bit._BGR3 +#define BGR1_BGR4 _bgr1.bit._BGR4 +#define BGR1_BGR5 _bgr1.bit._BGR5 +#define BGR1_BGR6 _bgr1.bit._BGR6 +#define BGR1_BGR7 _bgr1.bit._BGR7 +#define BGR1_BGR8 _bgr1.bit._BGR8 +#define BGR1_BGR9 _bgr1.bit._BGR9 +#define BGR1_BGR10 _bgr1.bit._BGR10 +#define BGR1_BGR11 _bgr1.bit._BGR11 +#define BGR1_BGR12 _bgr1.bit._BGR12 +#define BGR1_BGR13 _bgr1.bit._BGR13 +#define BGR1_BGR14 _bgr1.bit._BGR14 +#define BGR1_BGR15 _bgr1.bit._BGR15 +#define BGR1_BGR _bgr1.bitc._BGR +__IO_EXTERN __io BGRL1STR _bgrl1; +#define BGRL1 _bgrl1.byte +#define BGRL1_BGR0 _bgrl1.bit._BGR0 +#define BGRL1_BGR1 _bgrl1.bit._BGR1 +#define BGRL1_BGR2 _bgrl1.bit._BGR2 +#define BGRL1_BGR3 _bgrl1.bit._BGR3 +#define BGRL1_BGR4 _bgrl1.bit._BGR4 +#define BGRL1_BGR5 _bgrl1.bit._BGR5 +#define BGRL1_BGR6 _bgrl1.bit._BGR6 +#define BGRL1_BGR7 _bgrl1.bit._BGR7 +__IO_EXTERN __io BGRH1STR _bgrh1; +#define BGRH1 _bgrh1.byte +#define BGRH1_BGR8 _bgrh1.bit._BGR8 +#define BGRH1_BGR9 _bgrh1.bit._BGR9 +#define BGRH1_BGR10 _bgrh1.bit._BGR10 +#define BGRH1_BGR11 _bgrh1.bit._BGR11 +#define BGRH1_BGR12 _bgrh1.bit._BGR12 +#define BGRH1_BGR13 _bgrh1.bit._BGR13 +#define BGRH1_BGR14 _bgrh1.bit._BGR14 +#define BGRH1_BGR15 _bgrh1.bit._BGR15 +__IO_EXTERN __io ESIR1STR _esir1; +#define ESIR1 _esir1.byte +#define ESIR1_AICD _esir1.bit._AICD +#define ESIR1_RBI _esir1.bit._RBI +#define ESIR1_RDRF _esir1.bit._RDRF +#define ESIR1_TDRE _esir1.bit._TDRE +__IO_EXTERN __io SMR2STR _smr2; +#define SMR2 _smr2.byte +#define SMR2_SOE _smr2.bit._SOE +#define SMR2_SCKE _smr2.bit._SCKE +#define SMR2_UPCL _smr2.bit._UPCL +#define SMR2_REST _smr2.bit._REST +#define SMR2_EXT _smr2.bit._EXT +#define SMR2_OTO _smr2.bit._OTO +#define SMR2_MD0 _smr2.bit._MD0 +#define SMR2_MD1 _smr2.bit._MD1 +#define SMR2_MD _smr2.bitc._MD +__IO_EXTERN __io SCR2STR _scr2; +#define SCR2 _scr2.byte +#define SCR2_TXE _scr2.bit._TXE +#define SCR2_RXE _scr2.bit._RXE +#define SCR2_CRE _scr2.bit._CRE +#define SCR2_AD _scr2.bit._AD +#define SCR2_CL _scr2.bit._CL +#define SCR2_SBL _scr2.bit._SBL +#define SCR2_P _scr2.bit._P +#define SCR2_PEN _scr2.bit._PEN +__IO_EXTERN __io IO_BYTE _tdr2; +#define TDR2 _tdr2 +__IO_EXTERN __io IO_BYTE _rdr2; +#define RDR2 _rdr2 +__IO_EXTERN __io SSR2STR _ssr2; +#define SSR2 _ssr2.byte +#define SSR2_TIE _ssr2.bit._TIE +#define SSR2_RIE _ssr2.bit._RIE +#define SSR2_BDS _ssr2.bit._BDS +#define SSR2_TDRE _ssr2.bit._TDRE +#define SSR2_RDRF _ssr2.bit._RDRF +#define SSR2_FRE _ssr2.bit._FRE +#define SSR2_ORE _ssr2.bit._ORE +#define SSR2_PE _ssr2.bit._PE +__IO_EXTERN __io ECCR2STR _eccr2; +#define ECCR2 _eccr2.byte +#define ECCR2_TBI _eccr2.bit._TBI +#define ECCR2_RBI _eccr2.bit._RBI +#define ECCR2_BIE _eccr2.bit._BIE +#define ECCR2_SSM _eccr2.bit._SSM +#define ECCR2_SCDE _eccr2.bit._SCDE +#define ECCR2_MS _eccr2.bit._MS +#define ECCR2_LBR _eccr2.bit._LBR +#define ECCR2_INV _eccr2.bit._INV +__IO_EXTERN __io ESCR2STR _escr2; +#define ESCR2 _escr2.byte +#define ESCR2_SCES _escr2.bit._SCES +#define ESCR2_CCO _escr2.bit._CCO +#define ESCR2_SIOP _escr2.bit._SIOP +#define ESCR2_SOPE _escr2.bit._SOPE +#define ESCR2_LBL0 _escr2.bit._LBL0 +#define ESCR2_LBL1 _escr2.bit._LBL1 +#define ESCR2_LBD _escr2.bit._LBD +#define ESCR2_LBIE _escr2.bit._LBIE +#define ESCR2_LBL _escr2.bitc._LBL +__IO_EXTERN __io BGR2STR _bgr2; +#define BGR2 _bgr2.word +#define BGR2_BGR0 _bgr2.bit._BGR0 +#define BGR2_BGR1 _bgr2.bit._BGR1 +#define BGR2_BGR2 _bgr2.bit._BGR2 +#define BGR2_BGR3 _bgr2.bit._BGR3 +#define BGR2_BGR4 _bgr2.bit._BGR4 +#define BGR2_BGR5 _bgr2.bit._BGR5 +#define BGR2_BGR6 _bgr2.bit._BGR6 +#define BGR2_BGR7 _bgr2.bit._BGR7 +#define BGR2_BGR8 _bgr2.bit._BGR8 +#define BGR2_BGR9 _bgr2.bit._BGR9 +#define BGR2_BGR10 _bgr2.bit._BGR10 +#define BGR2_BGR11 _bgr2.bit._BGR11 +#define BGR2_BGR12 _bgr2.bit._BGR12 +#define BGR2_BGR13 _bgr2.bit._BGR13 +#define BGR2_BGR14 _bgr2.bit._BGR14 +#define BGR2_BGR15 _bgr2.bit._BGR15 +#define BGR2_BGR _bgr2.bitc._BGR +__IO_EXTERN __io BGRL2STR _bgrl2; +#define BGRL2 _bgrl2.byte +#define BGRL2_BGR0 _bgrl2.bit._BGR0 +#define BGRL2_BGR1 _bgrl2.bit._BGR1 +#define BGRL2_BGR2 _bgrl2.bit._BGR2 +#define BGRL2_BGR3 _bgrl2.bit._BGR3 +#define BGRL2_BGR4 _bgrl2.bit._BGR4 +#define BGRL2_BGR5 _bgrl2.bit._BGR5 +#define BGRL2_BGR6 _bgrl2.bit._BGR6 +#define BGRL2_BGR7 _bgrl2.bit._BGR7 +__IO_EXTERN __io BGRH2STR _bgrh2; +#define BGRH2 _bgrh2.byte +#define BGRH2_BGR8 _bgrh2.bit._BGR8 +#define BGRH2_BGR9 _bgrh2.bit._BGR9 +#define BGRH2_BGR10 _bgrh2.bit._BGR10 +#define BGRH2_BGR11 _bgrh2.bit._BGR11 +#define BGRH2_BGR12 _bgrh2.bit._BGR12 +#define BGRH2_BGR13 _bgrh2.bit._BGR13 +#define BGRH2_BGR14 _bgrh2.bit._BGR14 +#define BGRH2_BGR15 _bgrh2.bit._BGR15 +__IO_EXTERN __io ESIR2STR _esir2; +#define ESIR2 _esir2.byte +#define ESIR2_AICD _esir2.bit._AICD +#define ESIR2_RBI _esir2.bit._RBI +#define ESIR2_RDRF _esir2.bit._RDRF +#define ESIR2_TDRE _esir2.bit._TDRE +__IO_EXTERN __io SMR3STR _smr3; +#define SMR3 _smr3.byte +#define SMR3_SOE _smr3.bit._SOE +#define SMR3_SCKE _smr3.bit._SCKE +#define SMR3_UPCL _smr3.bit._UPCL +#define SMR3_REST _smr3.bit._REST +#define SMR3_EXT _smr3.bit._EXT +#define SMR3_OTO _smr3.bit._OTO +#define SMR3_MD0 _smr3.bit._MD0 +#define SMR3_MD1 _smr3.bit._MD1 +#define SMR3_MD _smr3.bitc._MD +__IO_EXTERN __io SCR3STR _scr3; +#define SCR3 _scr3.byte +#define SCR3_TXE _scr3.bit._TXE +#define SCR3_RXE _scr3.bit._RXE +#define SCR3_CRE _scr3.bit._CRE +#define SCR3_AD _scr3.bit._AD +#define SCR3_CL _scr3.bit._CL +#define SCR3_SBL _scr3.bit._SBL +#define SCR3_P _scr3.bit._P +#define SCR3_PEN _scr3.bit._PEN +__IO_EXTERN __io IO_BYTE _tdr3; +#define TDR3 _tdr3 +__IO_EXTERN __io IO_BYTE _rdr3; +#define RDR3 _rdr3 +__IO_EXTERN __io SSR3STR _ssr3; +#define SSR3 _ssr3.byte +#define SSR3_TIE _ssr3.bit._TIE +#define SSR3_RIE _ssr3.bit._RIE +#define SSR3_BDS _ssr3.bit._BDS +#define SSR3_TDRE _ssr3.bit._TDRE +#define SSR3_RDRF _ssr3.bit._RDRF +#define SSR3_FRE _ssr3.bit._FRE +#define SSR3_ORE _ssr3.bit._ORE +#define SSR3_PE _ssr3.bit._PE +__IO_EXTERN __io ECCR3STR _eccr3; +#define ECCR3 _eccr3.byte +#define ECCR3_TBI _eccr3.bit._TBI +#define ECCR3_RBI _eccr3.bit._RBI +#define ECCR3_BIE _eccr3.bit._BIE +#define ECCR3_SSM _eccr3.bit._SSM +#define ECCR3_SCDE _eccr3.bit._SCDE +#define ECCR3_MS _eccr3.bit._MS +#define ECCR3_LBR _eccr3.bit._LBR +#define ECCR3_INV _eccr3.bit._INV +__IO_EXTERN __io ESCR3STR _escr3; +#define ESCR3 _escr3.byte +#define ESCR3_SCES _escr3.bit._SCES +#define ESCR3_CCO _escr3.bit._CCO +#define ESCR3_SIOP _escr3.bit._SIOP +#define ESCR3_SOPE _escr3.bit._SOPE +#define ESCR3_LBL0 _escr3.bit._LBL0 +#define ESCR3_LBL1 _escr3.bit._LBL1 +#define ESCR3_LBD _escr3.bit._LBD +#define ESCR3_LBIE _escr3.bit._LBIE +#define ESCR3_LBL _escr3.bitc._LBL +__IO_EXTERN __io BGR3STR _bgr3; +#define BGR3 _bgr3.word +#define BGR3_BGR0 _bgr3.bit._BGR0 +#define BGR3_BGR1 _bgr3.bit._BGR1 +#define BGR3_BGR2 _bgr3.bit._BGR2 +#define BGR3_BGR3 _bgr3.bit._BGR3 +#define BGR3_BGR4 _bgr3.bit._BGR4 +#define BGR3_BGR5 _bgr3.bit._BGR5 +#define BGR3_BGR6 _bgr3.bit._BGR6 +#define BGR3_BGR7 _bgr3.bit._BGR7 +#define BGR3_BGR8 _bgr3.bit._BGR8 +#define BGR3_BGR9 _bgr3.bit._BGR9 +#define BGR3_BGR10 _bgr3.bit._BGR10 +#define BGR3_BGR11 _bgr3.bit._BGR11 +#define BGR3_BGR12 _bgr3.bit._BGR12 +#define BGR3_BGR13 _bgr3.bit._BGR13 +#define BGR3_BGR14 _bgr3.bit._BGR14 +#define BGR3_BGR15 _bgr3.bit._BGR15 +#define BGR3_BGR _bgr3.bitc._BGR +__IO_EXTERN __io BGRL3STR _bgrl3; +#define BGRL3 _bgrl3.byte +#define BGRL3_BGR0 _bgrl3.bit._BGR0 +#define BGRL3_BGR1 _bgrl3.bit._BGR1 +#define BGRL3_BGR2 _bgrl3.bit._BGR2 +#define BGRL3_BGR3 _bgrl3.bit._BGR3 +#define BGRL3_BGR4 _bgrl3.bit._BGR4 +#define BGRL3_BGR5 _bgrl3.bit._BGR5 +#define BGRL3_BGR6 _bgrl3.bit._BGR6 +#define BGRL3_BGR7 _bgrl3.bit._BGR7 +__IO_EXTERN __io BGRH3STR _bgrh3; +#define BGRH3 _bgrh3.byte +#define BGRH3_BGR8 _bgrh3.bit._BGR8 +#define BGRH3_BGR9 _bgrh3.bit._BGR9 +#define BGRH3_BGR10 _bgrh3.bit._BGR10 +#define BGRH3_BGR11 _bgrh3.bit._BGR11 +#define BGRH3_BGR12 _bgrh3.bit._BGR12 +#define BGRH3_BGR13 _bgrh3.bit._BGR13 +#define BGRH3_BGR14 _bgrh3.bit._BGR14 +#define BGRH3_BGR15 _bgrh3.bit._BGR15 +__IO_EXTERN __io ESIR3STR _esir3; +#define ESIR3 _esir3.byte +#define ESIR3_AICD _esir3.bit._AICD +#define ESIR3_RBI _esir3.bit._RBI +#define ESIR3_RDRF _esir3.bit._RDRF +#define ESIR3_TDRE _esir3.bit._TDRE +__IO_EXTENDED IO_BYTE _bapl0; +#define BAPL0 _bapl0 +__IO_EXTENDED IO_BYTE _bapm0; +#define BAPM0 _bapm0 +__IO_EXTENDED IO_BYTE _baph0; +#define BAPH0 _baph0 +__IO_EXTENDED DMACS0STR _dmacs0; +#define DMACS0 _dmacs0.byte +#define DMACS0_SE _dmacs0.bit._SE +#define DMACS0_DIR _dmacs0.bit._DIR +#define DMACS0_BF _dmacs0.bit._BF +#define DMACS0_BW _dmacs0.bit._BW +#define DMACS0_IF _dmacs0.bit._IF +#define DMACS0_BPD _dmacs0.bit._BPD +__IO_EXTENDED IO_WORD _ioa0; +#define IOA0 _ioa0 +__IO_EXTENDED IO_BYTE _ioal0; +#define IOAL0 _ioal0 +__IO_EXTENDED IO_BYTE _ioah0; +#define IOAH0 _ioah0 +__IO_EXTENDED IO_WORD _dct0; +#define DCT0 _dct0 +__IO_EXTENDED IO_BYTE _dctl0; +#define DCTL0 _dctl0 +__IO_EXTENDED IO_BYTE _dcth0; +#define DCTH0 _dcth0 +__IO_EXTENDED IO_BYTE _bapl1; +#define BAPL1 _bapl1 +__IO_EXTENDED IO_BYTE _bapm1; +#define BAPM1 _bapm1 +__IO_EXTENDED IO_BYTE _baph1; +#define BAPH1 _baph1 +__IO_EXTENDED DMACS1STR _dmacs1; +#define DMACS1 _dmacs1.byte +#define DMACS1_SE _dmacs1.bit._SE +#define DMACS1_DIR _dmacs1.bit._DIR +#define DMACS1_BF _dmacs1.bit._BF +#define DMACS1_BW _dmacs1.bit._BW +#define DMACS1_IF _dmacs1.bit._IF +#define DMACS1_BPD _dmacs1.bit._BPD +__IO_EXTENDED IO_WORD _ioa1; +#define IOA1 _ioa1 +__IO_EXTENDED IO_BYTE _ioal1; +#define IOAL1 _ioal1 +__IO_EXTENDED IO_BYTE _ioah1; +#define IOAH1 _ioah1 +__IO_EXTENDED IO_WORD _dct1; +#define DCT1 _dct1 +__IO_EXTENDED IO_BYTE _dctl1; +#define DCTL1 _dctl1 +__IO_EXTENDED IO_BYTE _dcth1; +#define DCTH1 _dcth1 +__IO_EXTENDED IO_BYTE _bapl2; +#define BAPL2 _bapl2 +__IO_EXTENDED IO_BYTE _bapm2; +#define BAPM2 _bapm2 +__IO_EXTENDED IO_BYTE _baph2; +#define BAPH2 _baph2 +__IO_EXTENDED DMACS2STR _dmacs2; +#define DMACS2 _dmacs2.byte +#define DMACS2_SE _dmacs2.bit._SE +#define DMACS2_DIR _dmacs2.bit._DIR +#define DMACS2_BF _dmacs2.bit._BF +#define DMACS2_BW _dmacs2.bit._BW +#define DMACS2_IF _dmacs2.bit._IF +#define DMACS2_BPD _dmacs2.bit._BPD +__IO_EXTENDED IO_WORD _ioa2; +#define IOA2 _ioa2 +__IO_EXTENDED IO_BYTE _ioal2; +#define IOAL2 _ioal2 +__IO_EXTENDED IO_BYTE _ioah2; +#define IOAH2 _ioah2 +__IO_EXTENDED IO_WORD _dct2; +#define DCT2 _dct2 +__IO_EXTENDED IO_BYTE _dctl2; +#define DCTL2 _dctl2 +__IO_EXTENDED IO_BYTE _dcth2; +#define DCTH2 _dcth2 +__IO_EXTENDED IO_BYTE _bapl3; +#define BAPL3 _bapl3 +__IO_EXTENDED IO_BYTE _bapm3; +#define BAPM3 _bapm3 +__IO_EXTENDED IO_BYTE _baph3; +#define BAPH3 _baph3 +__IO_EXTENDED DMACS3STR _dmacs3; +#define DMACS3 _dmacs3.byte +#define DMACS3_SE _dmacs3.bit._SE +#define DMACS3_DIR _dmacs3.bit._DIR +#define DMACS3_BF _dmacs3.bit._BF +#define DMACS3_BW _dmacs3.bit._BW +#define DMACS3_IF _dmacs3.bit._IF +#define DMACS3_BPD _dmacs3.bit._BPD +__IO_EXTENDED IO_WORD _ioa3; +#define IOA3 _ioa3 +__IO_EXTENDED IO_BYTE _ioal3; +#define IOAL3 _ioal3 +__IO_EXTENDED IO_BYTE _ioah3; +#define IOAH3 _ioah3 +__IO_EXTENDED IO_WORD _dct3; +#define DCT3 _dct3 +__IO_EXTENDED IO_BYTE _dctl3; +#define DCTL3 _dctl3 +__IO_EXTENDED IO_BYTE _dcth3; +#define DCTH3 _dcth3 +__IO_EXTENDED IO_BYTE _bapl4; +#define BAPL4 _bapl4 +__IO_EXTENDED IO_BYTE _bapm4; +#define BAPM4 _bapm4 +__IO_EXTENDED IO_BYTE _baph4; +#define BAPH4 _baph4 +__IO_EXTENDED DMACS4STR _dmacs4; +#define DMACS4 _dmacs4.byte +#define DMACS4_SE _dmacs4.bit._SE +#define DMACS4_DIR _dmacs4.bit._DIR +#define DMACS4_BF _dmacs4.bit._BF +#define DMACS4_BW _dmacs4.bit._BW +#define DMACS4_IF _dmacs4.bit._IF +#define DMACS4_BPD _dmacs4.bit._BPD +__IO_EXTENDED IO_WORD _ioa4; +#define IOA4 _ioa4 +__IO_EXTENDED IO_BYTE _ioal4; +#define IOAL4 _ioal4 +__IO_EXTENDED IO_BYTE _ioah4; +#define IOAH4 _ioah4 +__IO_EXTENDED IO_WORD _dct4; +#define DCT4 _dct4 +__IO_EXTENDED IO_BYTE _dctl4; +#define DCTL4 _dctl4 +__IO_EXTENDED IO_BYTE _dcth4; +#define DCTH4 _dcth4 +__IO_EXTENDED IO_BYTE _bapl5; +#define BAPL5 _bapl5 +__IO_EXTENDED IO_BYTE _bapm5; +#define BAPM5 _bapm5 +__IO_EXTENDED IO_BYTE _baph5; +#define BAPH5 _baph5 +__IO_EXTENDED DMACS5STR _dmacs5; +#define DMACS5 _dmacs5.byte +#define DMACS5_SE _dmacs5.bit._SE +#define DMACS5_DIR _dmacs5.bit._DIR +#define DMACS5_BF _dmacs5.bit._BF +#define DMACS5_BW _dmacs5.bit._BW +#define DMACS5_IF _dmacs5.bit._IF +#define DMACS5_BPD _dmacs5.bit._BPD +__IO_EXTENDED IO_WORD _ioa5; +#define IOA5 _ioa5 +__IO_EXTENDED IO_BYTE _ioal5; +#define IOAL5 _ioal5 +__IO_EXTENDED IO_BYTE _ioah5; +#define IOAH5 _ioah5 +__IO_EXTENDED IO_WORD _dct5; +#define DCT5 _dct5 +__IO_EXTENDED IO_BYTE _dctl5; +#define DCTL5 _dctl5 +__IO_EXTENDED IO_BYTE _dcth5; +#define DCTH5 _dcth5 +__IO_EXTENDED IO_BYTE _disel0; +#define DISEL0 _disel0 +__IO_EXTENDED IO_BYTE _disel1; +#define DISEL1 _disel1 +__IO_EXTENDED IO_BYTE _disel2; +#define DISEL2 _disel2 +__IO_EXTENDED IO_BYTE _disel3; +#define DISEL3 _disel3 +__IO_EXTENDED IO_BYTE _disel4; +#define DISEL4 _disel4 +__IO_EXTENDED IO_BYTE _disel5; +#define DISEL5 _disel5 +__IO_EXTENDED DSRSTR _dsr; +#define DSR _dsr.word +#define DSR_DTE0 _dsr.bit._DTE0 +#define DSR_DTE1 _dsr.bit._DTE1 +#define DSR_DTE2 _dsr.bit._DTE2 +#define DSR_DTE3 _dsr.bit._DTE3 +#define DSR_DTE4 _dsr.bit._DTE4 +#define DSR_DTE5 _dsr.bit._DTE5 +__IO_EXTENDED DSRLSTR _dsrl; +#define DSRL _dsrl.byte +#define DSRL_DTE0 _dsrl.bit._DTE0 +#define DSRL_DTE1 _dsrl.bit._DTE1 +#define DSRL_DTE2 _dsrl.bit._DTE2 +#define DSRL_DTE3 _dsrl.bit._DTE3 +#define DSRL_DTE4 _dsrl.bit._DTE4 +#define DSRL_DTE5 _dsrl.bit._DTE5 +__IO_EXTENDED IO_BYTE _dsrh; +#define DSRH _dsrh +__IO_EXTENDED DSSRSTR _dssr; +#define DSSR _dssr.word +#define DSSR_STP0 _dssr.bit._STP0 +#define DSSR_STP1 _dssr.bit._STP1 +#define DSSR_STP2 _dssr.bit._STP2 +#define DSSR_STP3 _dssr.bit._STP3 +#define DSSR_STP4 _dssr.bit._STP4 +#define DSSR_STP5 _dssr.bit._STP5 +__IO_EXTENDED DSSRLSTR _dssrl; +#define DSSRL _dssrl.byte +#define DSSRL_STP0 _dssrl.bit._STP0 +#define DSSRL_STP1 _dssrl.bit._STP1 +#define DSSRL_STP2 _dssrl.bit._STP2 +#define DSSRL_STP3 _dssrl.bit._STP3 +#define DSSRL_STP4 _dssrl.bit._STP4 +#define DSSRL_STP5 _dssrl.bit._STP5 +__IO_EXTENDED IO_BYTE _dssrh; +#define DSSRH _dssrh +__IO_EXTENDED DERSTR _der; +#define DER _der.word +#define DER_EN0 _der.bit._EN0 +#define DER_EN1 _der.bit._EN1 +#define DER_EN2 _der.bit._EN2 +#define DER_EN3 _der.bit._EN3 +#define DER_EN4 _der.bit._EN4 +#define DER_EN5 _der.bit._EN5 +__IO_EXTENDED DERLSTR _derl; +#define DERL _derl.byte +#define DERL_EN0 _derl.bit._EN0 +#define DERL_EN1 _derl.bit._EN1 +#define DERL_EN2 _derl.bit._EN2 +#define DERL_EN3 _derl.bit._EN3 +#define DERL_EN4 _derl.bit._EN4 +#define DERL_EN5 _derl.bit._EN5 +__IO_EXTENDED IO_BYTE _derh; +#define DERH _derh +__IO_EXTENDED ICRSTR _icr; +#define ICR _icr.word +#define ICR_IL0 _icr.bit._IL0 +#define ICR_IL1 _icr.bit._IL1 +#define ICR_IL2 _icr.bit._IL2 +#define ICR_IX0 _icr.bit._IX0 +#define ICR_IX1 _icr.bit._IX1 +#define ICR_IX2 _icr.bit._IX2 +#define ICR_IX3 _icr.bit._IX3 +#define ICR_IX4 _icr.bit._IX4 +#define ICR_IX5 _icr.bit._IX5 +#define ICR_IX6 _icr.bit._IX6 +#define ICR_IX7 _icr.bit._IX7 +#define ICR_IL _icr.bitc._IL +#define ICR_IX _icr.bitc._IX +__IO_EXTENDED ILRSTR _ilr; +#define ILR _ilr.byte +#define ILR_IL0 _ilr.bit._IL0 +#define ILR_IL1 _ilr.bit._IL1 +#define ILR_IL2 _ilr.bit._IL2 +#define ILR_IL _ilr.bitc._IL +__IO_EXTENDED IDXSTR _idx; +#define IDX _idx.byte +#define IDX_IX0 _idx.bit._IX0 +#define IDX_IX1 _idx.bit._IX1 +#define IDX_IX2 _idx.bit._IX2 +#define IDX_IX3 _idx.bit._IX3 +#define IDX_IX4 _idx.bit._IX4 +#define IDX_IX5 _idx.bit._IX5 +#define IDX_IX6 _idx.bit._IX6 +#define IDX_IX7 _idx.bit._IX7 +#define IDX_IX _idx.bitc._IX +__IO_EXTENDED TBRSTR _tbr; +#define TBR _tbr.word +#define TBR_TB10 _tbr.bit._TB10 +#define TBR_TB11 _tbr.bit._TB11 +#define TBR_TB12 _tbr.bit._TB12 +#define TBR_TB13 _tbr.bit._TB13 +#define TBR_TB14 _tbr.bit._TB14 +#define TBR_TB15 _tbr.bit._TB15 +#define TBR_TB16 _tbr.bit._TB16 +#define TBR_TB17 _tbr.bit._TB17 +#define TBR_TB18 _tbr.bit._TB18 +#define TBR_TB19 _tbr.bit._TB19 +#define TBR_TB20 _tbr.bit._TB20 +#define TBR_TB21 _tbr.bit._TB21 +#define TBR_TB22 _tbr.bit._TB22 +#define TBR_TB23 _tbr.bit._TB23 +__IO_EXTENDED TBRLSTR _tbrl; +#define TBRL _tbrl.byte +#define TBRL_TB10 _tbrl.bit._TB10 +#define TBRL_TB11 _tbrl.bit._TB11 +#define TBRL_TB12 _tbrl.bit._TB12 +#define TBRL_TB13 _tbrl.bit._TB13 +#define TBRL_TB14 _tbrl.bit._TB14 +#define TBRL_TB15 _tbrl.bit._TB15 +__IO_EXTENDED TBRHSTR _tbrh; +#define TBRH _tbrh.byte +#define TBRH_TB16 _tbrh.bit._TB16 +#define TBRH_TB17 _tbrh.bit._TB17 +#define TBRH_TB18 _tbrh.bit._TB18 +#define TBRH_TB19 _tbrh.bit._TB19 +#define TBRH_TB20 _tbrh.bit._TB20 +#define TBRH_TB21 _tbrh.bit._TB21 +#define TBRH_TB22 _tbrh.bit._TB22 +#define TBRH_TB23 _tbrh.bit._TB23 +__IO_EXTENDED DIRRSTR _dirr; +#define DIRR _dirr.byte +#define DIRR_R0 _dirr.bit._R0 +__IO_EXTENDED NMISTR _nmi; +#define NMI _nmi.byte +#define NMI_FLAG _nmi.bit._FLAG +#define NMI_EN _nmi.bit._EN +#define NMI_LEV _nmi.bit._LEV +#define NMI_INT9FIX _nmi.bit._INT9FIX +__IO_EXTENDED EDSU2STR _edsu2; +#define EDSU2 _edsu2.word +#define EDSU2_RSEL0 _edsu2.bit._RSEL0 +#define EDSU2_RSEL1 _edsu2.bit._RSEL1 +#define EDSU2_RSEL2 _edsu2.bit._RSEL2 +#define EDSU2_RSEL3 _edsu2.bit._RSEL3 +#define EDSU2_RSEL4 _edsu2.bit._RSEL4 +#define EDSU2_RSEL5 _edsu2.bit._RSEL5 +#define EDSU2_RSEL6 _edsu2.bit._RSEL6 +#define EDSU2_RSEL7 _edsu2.bit._RSEL7 +#define EDSU2_TSEL0 _edsu2.bit._TSEL0 +#define EDSU2_TSEL1 _edsu2.bit._TSEL1 +#define EDSU2_TSEL2 _edsu2.bit._TSEL2 +#define EDSU2_TSEL3 _edsu2.bit._TSEL3 +#define EDSU2_TSEL4 _edsu2.bit._TSEL4 +#define EDSU2_TSEL5 _edsu2.bit._TSEL5 +#define EDSU2_TSEL6 _edsu2.bit._TSEL6 +#define EDSU2_TSEL7 _edsu2.bit._TSEL7 +#define EDSU2_RSEL _edsu2.bitc._RSEL +#define EDSU2_TSEL _edsu2.bitc._TSEL +__IO_EXTENDED ROMMSTR _romm; +#define ROMM _romm.byte +#define ROMM_MI _romm.bit._MI +#define ROMM_SZ0 _romm.bit._SZ0 +#define ROMM_SZ1 _romm.bit._SZ1 +#define ROMM_BS0 _romm.bit._BS0 +#define ROMM_BS1 _romm.bit._BS1 +#define ROMM_BS2 _romm.bit._BS2 +#define ROMM_BS3 _romm.bit._BS3 +__IO_EXTENDED EDSUSTR _edsu; +#define EDSU _edsu.byte +#define EDSU_RINT _edsu.bit._RINT +#define EDSU_RIE _edsu.bit._RIE +#define EDSU_SEL0 _edsu.bit._SEL0 +#define EDSU_SEL1 _edsu.bit._SEL1 +#define EDSU_TINT _edsu.bit._TINT +#define EDSU_TIE _edsu.bit._TIE +#define EDSU_EN _edsu.bit._EN +#define EDSU_SEL _edsu.bitc._SEL +__IO_EXTENDED PFCS0STR _pfcs0; +#define PFCS0 _pfcs0.word +#define PFCS0_I0 _pfcs0.bit._I0 +#define PFCS0_I1 _pfcs0.bit._I1 +#define PFCS0_IE0 _pfcs0.bit._IE0 +#define PFCS0_IE1 _pfcs0.bit._IE1 +#define PFCS0_PE0 _pfcs0.bit._PE0 +#define PFCS0_PE1 _pfcs0.bit._PE1 +#define PFCS0_AR _pfcs0.bit._AR +#define PFCS0_AM _pfcs0.bit._AM +#define PFCS0_DMA _pfcs0.bit._DMA +#define PFCS0_CPU _pfcs0.bit._CPU +#define PFCS0_DATA _pfcs0.bit._DATA +#define PFCS0_CODE _pfcs0.bit._CODE +#define PFCS0_WORD _pfcs0.bit._WORD +#define PFCS0_BYTE _pfcs0.bit._BYTE +#define PFCS0_WRITE _pfcs0.bit._WRITE +#define PFCS0_READ _pfcs0.bit._READ +__IO_EXTENDED PFCS1STR _pfcs1; +#define PFCS1 _pfcs1.word +#define PFCS1_I0 _pfcs1.bit._I0 +#define PFCS1_I1 _pfcs1.bit._I1 +#define PFCS1_IE0 _pfcs1.bit._IE0 +#define PFCS1_IE1 _pfcs1.bit._IE1 +#define PFCS1_PE0 _pfcs1.bit._PE0 +#define PFCS1_PE1 _pfcs1.bit._PE1 +#define PFCS1_AR _pfcs1.bit._AR +#define PFCS1_AM _pfcs1.bit._AM +#define PFCS1_DMA _pfcs1.bit._DMA +#define PFCS1_CPU _pfcs1.bit._CPU +#define PFCS1_DATA _pfcs1.bit._DATA +#define PFCS1_CODE _pfcs1.bit._CODE +#define PFCS1_WORD _pfcs1.bit._WORD +#define PFCS1_BYTE _pfcs1.bit._BYTE +#define PFCS1_WRITE _pfcs1.bit._WRITE +#define PFCS1_READ _pfcs1.bit._READ +__IO_EXTENDED PFCS2STR _pfcs2; +#define PFCS2 _pfcs2.word +#define PFCS2_I0 _pfcs2.bit._I0 +#define PFCS2_I1 _pfcs2.bit._I1 +#define PFCS2_IE0 _pfcs2.bit._IE0 +#define PFCS2_IE1 _pfcs2.bit._IE1 +#define PFCS2_PE0 _pfcs2.bit._PE0 +#define PFCS2_PE1 _pfcs2.bit._PE1 +#define PFCS2_AR _pfcs2.bit._AR +#define PFCS2_AM _pfcs2.bit._AM +#define PFCS2_DMA _pfcs2.bit._DMA +#define PFCS2_CPU _pfcs2.bit._CPU +#define PFCS2_DATA _pfcs2.bit._DATA +#define PFCS2_CODE _pfcs2.bit._CODE +#define PFCS2_WORD _pfcs2.bit._WORD +#define PFCS2_BYTE _pfcs2.bit._BYTE +#define PFCS2_WRITE _pfcs2.bit._WRITE +#define PFCS2_READ _pfcs2.bit._READ +__IO_EXTENDED PFCS3STR _pfcs3; +#define PFCS3 _pfcs3.word +#define PFCS3_I0 _pfcs3.bit._I0 +#define PFCS3_I1 _pfcs3.bit._I1 +#define PFCS3_IE0 _pfcs3.bit._IE0 +#define PFCS3_IE1 _pfcs3.bit._IE1 +#define PFCS3_PE0 _pfcs3.bit._PE0 +#define PFCS3_PE1 _pfcs3.bit._PE1 +#define PFCS3_AR _pfcs3.bit._AR +#define PFCS3_AM _pfcs3.bit._AM +#define PFCS3_DMA _pfcs3.bit._DMA +#define PFCS3_CPU _pfcs3.bit._CPU +#define PFCS3_DATA _pfcs3.bit._DATA +#define PFCS3_CODE _pfcs3.bit._CODE +#define PFCS3_WORD _pfcs3.bit._WORD +#define PFCS3_BYTE _pfcs3.bit._BYTE +#define PFCS3_WRITE _pfcs3.bit._WRITE +#define PFCS3_READ _pfcs3.bit._READ +__IO_EXTENDED PFAL0STR _pfal0; +#define PFAL0 _pfal0.byte +#define PFAL0_PFA0 _pfal0.bit._PFA0 +#define PFAL0_PFA1 _pfal0.bit._PFA1 +#define PFAL0_PFA2 _pfal0.bit._PFA2 +#define PFAL0_PFA3 _pfal0.bit._PFA3 +#define PFAL0_PFA4 _pfal0.bit._PFA4 +#define PFAL0_PFA5 _pfal0.bit._PFA5 +#define PFAL0_PFA6 _pfal0.bit._PFA6 +#define PFAL0_PFA7 _pfal0.bit._PFA7 +__IO_EXTENDED PFAM0STR _pfam0; +#define PFAM0 _pfam0.byte +#define PFAM0_PFA8 _pfam0.bit._PFA8 +#define PFAM0_PFA9 _pfam0.bit._PFA9 +#define PFAM0_PFA10 _pfam0.bit._PFA10 +#define PFAM0_PFA11 _pfam0.bit._PFA11 +#define PFAM0_PFA12 _pfam0.bit._PFA12 +#define PFAM0_PFA13 _pfam0.bit._PFA13 +#define PFAM0_PFA14 _pfam0.bit._PFA14 +#define PFAM0_PFA15 _pfam0.bit._PFA15 +__IO_EXTENDED PFAH0STR _pfah0; +#define PFAH0 _pfah0.byte +#define PFAH0_PFA16 _pfah0.bit._PFA16 +#define PFAH0_PFA17 _pfah0.bit._PFA17 +#define PFAH0_PFA18 _pfah0.bit._PFA18 +#define PFAH0_PFA19 _pfah0.bit._PFA19 +#define PFAH0_PFA20 _pfah0.bit._PFA20 +#define PFAH0_PFA21 _pfah0.bit._PFA21 +#define PFAH0_PFA22 _pfah0.bit._PFA22 +#define PFAH0_PFA23 _pfah0.bit._PFA23 +__IO_EXTENDED PFAL1STR _pfal1; +#define PFAL1 _pfal1.byte +#define PFAL1_PFA0 _pfal1.bit._PFA0 +#define PFAL1_PFA1 _pfal1.bit._PFA1 +#define PFAL1_PFA2 _pfal1.bit._PFA2 +#define PFAL1_PFA3 _pfal1.bit._PFA3 +#define PFAL1_PFA4 _pfal1.bit._PFA4 +#define PFAL1_PFA5 _pfal1.bit._PFA5 +#define PFAL1_PFA6 _pfal1.bit._PFA6 +#define PFAL1_PFA7 _pfal1.bit._PFA7 +__IO_EXTENDED PFAM1STR _pfam1; +#define PFAM1 _pfam1.byte +#define PFAM1_PFA8 _pfam1.bit._PFA8 +#define PFAM1_PFA9 _pfam1.bit._PFA9 +#define PFAM1_PFA10 _pfam1.bit._PFA10 +#define PFAM1_PFA11 _pfam1.bit._PFA11 +#define PFAM1_PFA12 _pfam1.bit._PFA12 +#define PFAM1_PFA13 _pfam1.bit._PFA13 +#define PFAM1_PFA14 _pfam1.bit._PFA14 +#define PFAM1_PFA15 _pfam1.bit._PFA15 +__IO_EXTENDED PFAH1STR _pfah1; +#define PFAH1 _pfah1.byte +#define PFAH1_PFA16 _pfah1.bit._PFA16 +#define PFAH1_PFA17 _pfah1.bit._PFA17 +#define PFAH1_PFA18 _pfah1.bit._PFA18 +#define PFAH1_PFA19 _pfah1.bit._PFA19 +#define PFAH1_PFA20 _pfah1.bit._PFA20 +#define PFAH1_PFA21 _pfah1.bit._PFA21 +#define PFAH1_PFA22 _pfah1.bit._PFA22 +#define PFAH1_PFA23 _pfah1.bit._PFA23 +__IO_EXTENDED PFAL2STR _pfal2; +#define PFAL2 _pfal2.byte +#define PFAL2_PFA0 _pfal2.bit._PFA0 +#define PFAL2_PFA1 _pfal2.bit._PFA1 +#define PFAL2_PFA2 _pfal2.bit._PFA2 +#define PFAL2_PFA3 _pfal2.bit._PFA3 +#define PFAL2_PFA4 _pfal2.bit._PFA4 +#define PFAL2_PFA5 _pfal2.bit._PFA5 +#define PFAL2_PFA6 _pfal2.bit._PFA6 +#define PFAL2_PFA7 _pfal2.bit._PFA7 +__IO_EXTENDED PFAM2STR _pfam2; +#define PFAM2 _pfam2.byte +#define PFAM2_PFA8 _pfam2.bit._PFA8 +#define PFAM2_PFA9 _pfam2.bit._PFA9 +#define PFAM2_PFA10 _pfam2.bit._PFA10 +#define PFAM2_PFA11 _pfam2.bit._PFA11 +#define PFAM2_PFA12 _pfam2.bit._PFA12 +#define PFAM2_PFA13 _pfam2.bit._PFA13 +#define PFAM2_PFA14 _pfam2.bit._PFA14 +#define PFAM2_PFA15 _pfam2.bit._PFA15 +__IO_EXTENDED PFAH2STR _pfah2; +#define PFAH2 _pfah2.byte +#define PFAH2_PFA16 _pfah2.bit._PFA16 +#define PFAH2_PFA17 _pfah2.bit._PFA17 +#define PFAH2_PFA18 _pfah2.bit._PFA18 +#define PFAH2_PFA19 _pfah2.bit._PFA19 +#define PFAH2_PFA20 _pfah2.bit._PFA20 +#define PFAH2_PFA21 _pfah2.bit._PFA21 +#define PFAH2_PFA22 _pfah2.bit._PFA22 +#define PFAH2_PFA23 _pfah2.bit._PFA23 +__IO_EXTENDED PFAL3STR _pfal3; +#define PFAL3 _pfal3.byte +#define PFAL3_PFA0 _pfal3.bit._PFA0 +#define PFAL3_PFA1 _pfal3.bit._PFA1 +#define PFAL3_PFA2 _pfal3.bit._PFA2 +#define PFAL3_PFA3 _pfal3.bit._PFA3 +#define PFAL3_PFA4 _pfal3.bit._PFA4 +#define PFAL3_PFA5 _pfal3.bit._PFA5 +#define PFAL3_PFA6 _pfal3.bit._PFA6 +#define PFAL3_PFA7 _pfal3.bit._PFA7 +__IO_EXTENDED PFAM3STR _pfam3; +#define PFAM3 _pfam3.byte +#define PFAM3_PFA8 _pfam3.bit._PFA8 +#define PFAM3_PFA9 _pfam3.bit._PFA9 +#define PFAM3_PFA10 _pfam3.bit._PFA10 +#define PFAM3_PFA11 _pfam3.bit._PFA11 +#define PFAM3_PFA12 _pfam3.bit._PFA12 +#define PFAM3_PFA13 _pfam3.bit._PFA13 +#define PFAM3_PFA14 _pfam3.bit._PFA14 +#define PFAM3_PFA15 _pfam3.bit._PFA15 +__IO_EXTENDED PFAH3STR _pfah3; +#define PFAH3 _pfah3.byte +#define PFAH3_PFA16 _pfah3.bit._PFA16 +#define PFAH3_PFA17 _pfah3.bit._PFA17 +#define PFAH3_PFA18 _pfah3.bit._PFA18 +#define PFAH3_PFA19 _pfah3.bit._PFA19 +#define PFAH3_PFA20 _pfah3.bit._PFA20 +#define PFAH3_PFA21 _pfah3.bit._PFA21 +#define PFAH3_PFA22 _pfah3.bit._PFA22 +#define PFAH3_PFA23 _pfah3.bit._PFA23 +__IO_EXTENDED PFAL4STR _pfal4; +#define PFAL4 _pfal4.byte +#define PFAL4_PFA0 _pfal4.bit._PFA0 +#define PFAL4_PFA1 _pfal4.bit._PFA1 +#define PFAL4_PFA2 _pfal4.bit._PFA2 +#define PFAL4_PFA3 _pfal4.bit._PFA3 +#define PFAL4_PFA4 _pfal4.bit._PFA4 +#define PFAL4_PFA5 _pfal4.bit._PFA5 +#define PFAL4_PFA6 _pfal4.bit._PFA6 +#define PFAL4_PFA7 _pfal4.bit._PFA7 +__IO_EXTENDED PFAM4STR _pfam4; +#define PFAM4 _pfam4.byte +#define PFAM4_PFA8 _pfam4.bit._PFA8 +#define PFAM4_PFA9 _pfam4.bit._PFA9 +#define PFAM4_PFA10 _pfam4.bit._PFA10 +#define PFAM4_PFA11 _pfam4.bit._PFA11 +#define PFAM4_PFA12 _pfam4.bit._PFA12 +#define PFAM4_PFA13 _pfam4.bit._PFA13 +#define PFAM4_PFA14 _pfam4.bit._PFA14 +#define PFAM4_PFA15 _pfam4.bit._PFA15 +__IO_EXTENDED PFAH4STR _pfah4; +#define PFAH4 _pfah4.byte +#define PFAH4_PFA16 _pfah4.bit._PFA16 +#define PFAH4_PFA17 _pfah4.bit._PFA17 +#define PFAH4_PFA18 _pfah4.bit._PFA18 +#define PFAH4_PFA19 _pfah4.bit._PFA19 +#define PFAH4_PFA20 _pfah4.bit._PFA20 +#define PFAH4_PFA21 _pfah4.bit._PFA21 +#define PFAH4_PFA22 _pfah4.bit._PFA22 +#define PFAH4_PFA23 _pfah4.bit._PFA23 +__IO_EXTENDED PFAL5STR _pfal5; +#define PFAL5 _pfal5.byte +#define PFAL5_PFA0 _pfal5.bit._PFA0 +#define PFAL5_PFA1 _pfal5.bit._PFA1 +#define PFAL5_PFA2 _pfal5.bit._PFA2 +#define PFAL5_PFA3 _pfal5.bit._PFA3 +#define PFAL5_PFA4 _pfal5.bit._PFA4 +#define PFAL5_PFA5 _pfal5.bit._PFA5 +#define PFAL5_PFA6 _pfal5.bit._PFA6 +#define PFAL5_PFA7 _pfal5.bit._PFA7 +__IO_EXTENDED PFAM5STR _pfam5; +#define PFAM5 _pfam5.byte +#define PFAM5_PFA8 _pfam5.bit._PFA8 +#define PFAM5_PFA9 _pfam5.bit._PFA9 +#define PFAM5_PFA10 _pfam5.bit._PFA10 +#define PFAM5_PFA11 _pfam5.bit._PFA11 +#define PFAM5_PFA12 _pfam5.bit._PFA12 +#define PFAM5_PFA13 _pfam5.bit._PFA13 +#define PFAM5_PFA14 _pfam5.bit._PFA14 +#define PFAM5_PFA15 _pfam5.bit._PFA15 +__IO_EXTENDED PFAH5STR _pfah5; +#define PFAH5 _pfah5.byte +#define PFAH5_PFA16 _pfah5.bit._PFA16 +#define PFAH5_PFA17 _pfah5.bit._PFA17 +#define PFAH5_PFA18 _pfah5.bit._PFA18 +#define PFAH5_PFA19 _pfah5.bit._PFA19 +#define PFAH5_PFA20 _pfah5.bit._PFA20 +#define PFAH5_PFA21 _pfah5.bit._PFA21 +#define PFAH5_PFA22 _pfah5.bit._PFA22 +#define PFAH5_PFA23 _pfah5.bit._PFA23 +__IO_EXTENDED PFAL6STR _pfal6; +#define PFAL6 _pfal6.byte +#define PFAL6_PFA0 _pfal6.bit._PFA0 +#define PFAL6_PFA1 _pfal6.bit._PFA1 +#define PFAL6_PFA2 _pfal6.bit._PFA2 +#define PFAL6_PFA3 _pfal6.bit._PFA3 +#define PFAL6_PFA4 _pfal6.bit._PFA4 +#define PFAL6_PFA5 _pfal6.bit._PFA5 +#define PFAL6_PFA6 _pfal6.bit._PFA6 +#define PFAL6_PFA7 _pfal6.bit._PFA7 +__IO_EXTENDED PFAM6STR _pfam6; +#define PFAM6 _pfam6.byte +#define PFAM6_PFA8 _pfam6.bit._PFA8 +#define PFAM6_PFA9 _pfam6.bit._PFA9 +#define PFAM6_PFA10 _pfam6.bit._PFA10 +#define PFAM6_PFA11 _pfam6.bit._PFA11 +#define PFAM6_PFA12 _pfam6.bit._PFA12 +#define PFAM6_PFA13 _pfam6.bit._PFA13 +#define PFAM6_PFA14 _pfam6.bit._PFA14 +#define PFAM6_PFA15 _pfam6.bit._PFA15 +__IO_EXTENDED PFAH6STR _pfah6; +#define PFAH6 _pfah6.byte +#define PFAH6_PFA16 _pfah6.bit._PFA16 +#define PFAH6_PFA17 _pfah6.bit._PFA17 +#define PFAH6_PFA18 _pfah6.bit._PFA18 +#define PFAH6_PFA19 _pfah6.bit._PFA19 +#define PFAH6_PFA20 _pfah6.bit._PFA20 +#define PFAH6_PFA21 _pfah6.bit._PFA21 +#define PFAH6_PFA22 _pfah6.bit._PFA22 +#define PFAH6_PFA23 _pfah6.bit._PFA23 +__IO_EXTENDED PFAL7STR _pfal7; +#define PFAL7 _pfal7.byte +#define PFAL7_PFA0 _pfal7.bit._PFA0 +#define PFAL7_PFA1 _pfal7.bit._PFA1 +#define PFAL7_PFA2 _pfal7.bit._PFA2 +#define PFAL7_PFA3 _pfal7.bit._PFA3 +#define PFAL7_PFA4 _pfal7.bit._PFA4 +#define PFAL7_PFA5 _pfal7.bit._PFA5 +#define PFAL7_PFA6 _pfal7.bit._PFA6 +#define PFAL7_PFA7 _pfal7.bit._PFA7 +__IO_EXTENDED PFAM7STR _pfam7; +#define PFAM7 _pfam7.byte +#define PFAM7_PFA8 _pfam7.bit._PFA8 +#define PFAM7_PFA9 _pfam7.bit._PFA9 +#define PFAM7_PFA10 _pfam7.bit._PFA10 +#define PFAM7_PFA11 _pfam7.bit._PFA11 +#define PFAM7_PFA12 _pfam7.bit._PFA12 +#define PFAM7_PFA13 _pfam7.bit._PFA13 +#define PFAM7_PFA14 _pfam7.bit._PFA14 +#define PFAM7_PFA15 _pfam7.bit._PFA15 +__IO_EXTENDED PFAH7STR _pfah7; +#define PFAH7 _pfah7.byte +#define PFAH7_PFA16 _pfah7.bit._PFA16 +#define PFAH7_PFA17 _pfah7.bit._PFA17 +#define PFAH7_PFA18 _pfah7.bit._PFA18 +#define PFAH7_PFA19 _pfah7.bit._PFA19 +#define PFAH7_PFA20 _pfah7.bit._PFA20 +#define PFAH7_PFA21 _pfah7.bit._PFA21 +#define PFAH7_PFA22 _pfah7.bit._PFA22 +#define PFAH7_PFA23 _pfah7.bit._PFA23 +__IO_EXTENDED PFD0STR _pfd0; +#define PFD0 _pfd0.word +#define PFD0_PFD0 _pfd0.bit._PFD0 +#define PFD0_PFD1 _pfd0.bit._PFD1 +#define PFD0_PFD2 _pfd0.bit._PFD2 +#define PFD0_PFD3 _pfd0.bit._PFD3 +#define PFD0_PFD4 _pfd0.bit._PFD4 +#define PFD0_PFD5 _pfd0.bit._PFD5 +#define PFD0_PFD6 _pfd0.bit._PFD6 +#define PFD0_PFD7 _pfd0.bit._PFD7 +#define PFD0_PFD8 _pfd0.bit._PFD8 +#define PFD0_PFD9 _pfd0.bit._PFD9 +#define PFD0_PFD10 _pfd0.bit._PFD10 +#define PFD0_PFD11 _pfd0.bit._PFD11 +#define PFD0_PFD12 _pfd0.bit._PFD12 +#define PFD0_PFD13 _pfd0.bit._PFD13 +#define PFD0_PFD14 _pfd0.bit._PFD14 +#define PFD0_PFD15 _pfd0.bit._PFD15 +#define PFD0_PFD _pfd0.bitc._PFD +__IO_EXTENDED PFDL0STR _pfdl0; +#define PFDL0 _pfdl0.byte +#define PFDL0_PFD0 _pfdl0.bit._PFD0 +#define PFDL0_PFD1 _pfdl0.bit._PFD1 +#define PFDL0_PFD2 _pfdl0.bit._PFD2 +#define PFDL0_PFD3 _pfdl0.bit._PFD3 +#define PFDL0_PFD4 _pfdl0.bit._PFD4 +#define PFDL0_PFD5 _pfdl0.bit._PFD5 +#define PFDL0_PFD6 _pfdl0.bit._PFD6 +#define PFDL0_PFD7 _pfdl0.bit._PFD7 +__IO_EXTENDED PFDH0STR _pfdh0; +#define PFDH0 _pfdh0.byte +#define PFDH0_PFD8 _pfdh0.bit._PFD8 +#define PFDH0_PFD9 _pfdh0.bit._PFD9 +#define PFDH0_PFD10 _pfdh0.bit._PFD10 +#define PFDH0_PFD11 _pfdh0.bit._PFD11 +#define PFDH0_PFD12 _pfdh0.bit._PFD12 +#define PFDH0_PFD13 _pfdh0.bit._PFD13 +#define PFDH0_PFD14 _pfdh0.bit._PFD14 +#define PFDH0_PFD15 _pfdh0.bit._PFD15 +__IO_EXTENDED PFD1STR _pfd1; +#define PFD1 _pfd1.word +#define PFD1_PFD0 _pfd1.bit._PFD0 +#define PFD1_PFD1 _pfd1.bit._PFD1 +#define PFD1_PFD2 _pfd1.bit._PFD2 +#define PFD1_PFD3 _pfd1.bit._PFD3 +#define PFD1_PFD4 _pfd1.bit._PFD4 +#define PFD1_PFD5 _pfd1.bit._PFD5 +#define PFD1_PFD6 _pfd1.bit._PFD6 +#define PFD1_PFD7 _pfd1.bit._PFD7 +#define PFD1_PFD8 _pfd1.bit._PFD8 +#define PFD1_PFD9 _pfd1.bit._PFD9 +#define PFD1_PFD10 _pfd1.bit._PFD10 +#define PFD1_PFD11 _pfd1.bit._PFD11 +#define PFD1_PFD12 _pfd1.bit._PFD12 +#define PFD1_PFD13 _pfd1.bit._PFD13 +#define PFD1_PFD14 _pfd1.bit._PFD14 +#define PFD1_PFD15 _pfd1.bit._PFD15 +#define PFD1_PFD _pfd1.bitc._PFD +__IO_EXTENDED PFDL1STR _pfdl1; +#define PFDL1 _pfdl1.byte +#define PFDL1_PFD0 _pfdl1.bit._PFD0 +#define PFDL1_PFD1 _pfdl1.bit._PFD1 +#define PFDL1_PFD2 _pfdl1.bit._PFD2 +#define PFDL1_PFD3 _pfdl1.bit._PFD3 +#define PFDL1_PFD4 _pfdl1.bit._PFD4 +#define PFDL1_PFD5 _pfdl1.bit._PFD5 +#define PFDL1_PFD6 _pfdl1.bit._PFD6 +#define PFDL1_PFD7 _pfdl1.bit._PFD7 +__IO_EXTENDED PFDH1STR _pfdh1; +#define PFDH1 _pfdh1.byte +#define PFDH1_PFD8 _pfdh1.bit._PFD8 +#define PFDH1_PFD9 _pfdh1.bit._PFD9 +#define PFDH1_PFD10 _pfdh1.bit._PFD10 +#define PFDH1_PFD11 _pfdh1.bit._PFD11 +#define PFDH1_PFD12 _pfdh1.bit._PFD12 +#define PFDH1_PFD13 _pfdh1.bit._PFD13 +#define PFDH1_PFD14 _pfdh1.bit._PFD14 +#define PFDH1_PFD15 _pfdh1.bit._PFD15 +__IO_EXTENDED PFD2STR _pfd2; +#define PFD2 _pfd2.word +#define PFD2_PFD0 _pfd2.bit._PFD0 +#define PFD2_PFD1 _pfd2.bit._PFD1 +#define PFD2_PFD2 _pfd2.bit._PFD2 +#define PFD2_PFD3 _pfd2.bit._PFD3 +#define PFD2_PFD4 _pfd2.bit._PFD4 +#define PFD2_PFD5 _pfd2.bit._PFD5 +#define PFD2_PFD6 _pfd2.bit._PFD6 +#define PFD2_PFD7 _pfd2.bit._PFD7 +#define PFD2_PFD8 _pfd2.bit._PFD8 +#define PFD2_PFD9 _pfd2.bit._PFD9 +#define PFD2_PFD10 _pfd2.bit._PFD10 +#define PFD2_PFD11 _pfd2.bit._PFD11 +#define PFD2_PFD12 _pfd2.bit._PFD12 +#define PFD2_PFD13 _pfd2.bit._PFD13 +#define PFD2_PFD14 _pfd2.bit._PFD14 +#define PFD2_PFD15 _pfd2.bit._PFD15 +#define PFD2_PFD _pfd2.bitc._PFD +__IO_EXTENDED PFDL2STR _pfdl2; +#define PFDL2 _pfdl2.byte +#define PFDL2_PFD0 _pfdl2.bit._PFD0 +#define PFDL2_PFD1 _pfdl2.bit._PFD1 +#define PFDL2_PFD2 _pfdl2.bit._PFD2 +#define PFDL2_PFD3 _pfdl2.bit._PFD3 +#define PFDL2_PFD4 _pfdl2.bit._PFD4 +#define PFDL2_PFD5 _pfdl2.bit._PFD5 +#define PFDL2_PFD6 _pfdl2.bit._PFD6 +#define PFDL2_PFD7 _pfdl2.bit._PFD7 +__IO_EXTENDED PFDH2STR _pfdh2; +#define PFDH2 _pfdh2.byte +#define PFDH2_PFD8 _pfdh2.bit._PFD8 +#define PFDH2_PFD9 _pfdh2.bit._PFD9 +#define PFDH2_PFD10 _pfdh2.bit._PFD10 +#define PFDH2_PFD11 _pfdh2.bit._PFD11 +#define PFDH2_PFD12 _pfdh2.bit._PFD12 +#define PFDH2_PFD13 _pfdh2.bit._PFD13 +#define PFDH2_PFD14 _pfdh2.bit._PFD14 +#define PFDH2_PFD15 _pfdh2.bit._PFD15 +__IO_EXTENDED PFD3STR _pfd3; +#define PFD3 _pfd3.word +#define PFD3_PFD0 _pfd3.bit._PFD0 +#define PFD3_PFD1 _pfd3.bit._PFD1 +#define PFD3_PFD2 _pfd3.bit._PFD2 +#define PFD3_PFD3 _pfd3.bit._PFD3 +#define PFD3_PFD4 _pfd3.bit._PFD4 +#define PFD3_PFD5 _pfd3.bit._PFD5 +#define PFD3_PFD6 _pfd3.bit._PFD6 +#define PFD3_PFD7 _pfd3.bit._PFD7 +#define PFD3_PFD8 _pfd3.bit._PFD8 +#define PFD3_PFD9 _pfd3.bit._PFD9 +#define PFD3_PFD10 _pfd3.bit._PFD10 +#define PFD3_PFD11 _pfd3.bit._PFD11 +#define PFD3_PFD12 _pfd3.bit._PFD12 +#define PFD3_PFD13 _pfd3.bit._PFD13 +#define PFD3_PFD14 _pfd3.bit._PFD14 +#define PFD3_PFD15 _pfd3.bit._PFD15 +#define PFD3_PFD _pfd3.bitc._PFD +__IO_EXTENDED PFDL3STR _pfdl3; +#define PFDL3 _pfdl3.byte +#define PFDL3_PFD0 _pfdl3.bit._PFD0 +#define PFDL3_PFD1 _pfdl3.bit._PFD1 +#define PFDL3_PFD2 _pfdl3.bit._PFD2 +#define PFDL3_PFD3 _pfdl3.bit._PFD3 +#define PFDL3_PFD4 _pfdl3.bit._PFD4 +#define PFDL3_PFD5 _pfdl3.bit._PFD5 +#define PFDL3_PFD6 _pfdl3.bit._PFD6 +#define PFDL3_PFD7 _pfdl3.bit._PFD7 +__IO_EXTENDED PFDH3STR _pfdh3; +#define PFDH3 _pfdh3.byte +#define PFDH3_PFD8 _pfdh3.bit._PFD8 +#define PFDH3_PFD9 _pfdh3.bit._PFD9 +#define PFDH3_PFD10 _pfdh3.bit._PFD10 +#define PFDH3_PFD11 _pfdh3.bit._PFD11 +#define PFDH3_PFD12 _pfdh3.bit._PFD12 +#define PFDH3_PFD13 _pfdh3.bit._PFD13 +#define PFDH3_PFD14 _pfdh3.bit._PFD14 +#define PFDH3_PFD15 _pfdh3.bit._PFD15 +__IO_EXTENDED PFD4STR _pfd4; +#define PFD4 _pfd4.word +#define PFD4_PFD0 _pfd4.bit._PFD0 +#define PFD4_PFD1 _pfd4.bit._PFD1 +#define PFD4_PFD2 _pfd4.bit._PFD2 +#define PFD4_PFD3 _pfd4.bit._PFD3 +#define PFD4_PFD4 _pfd4.bit._PFD4 +#define PFD4_PFD5 _pfd4.bit._PFD5 +#define PFD4_PFD6 _pfd4.bit._PFD6 +#define PFD4_PFD7 _pfd4.bit._PFD7 +#define PFD4_PFD8 _pfd4.bit._PFD8 +#define PFD4_PFD9 _pfd4.bit._PFD9 +#define PFD4_PFD10 _pfd4.bit._PFD10 +#define PFD4_PFD11 _pfd4.bit._PFD11 +#define PFD4_PFD12 _pfd4.bit._PFD12 +#define PFD4_PFD13 _pfd4.bit._PFD13 +#define PFD4_PFD14 _pfd4.bit._PFD14 +#define PFD4_PFD15 _pfd4.bit._PFD15 +#define PFD4_PFD _pfd4.bitc._PFD +__IO_EXTENDED PFDL4STR _pfdl4; +#define PFDL4 _pfdl4.byte +#define PFDL4_PFD0 _pfdl4.bit._PFD0 +#define PFDL4_PFD1 _pfdl4.bit._PFD1 +#define PFDL4_PFD2 _pfdl4.bit._PFD2 +#define PFDL4_PFD3 _pfdl4.bit._PFD3 +#define PFDL4_PFD4 _pfdl4.bit._PFD4 +#define PFDL4_PFD5 _pfdl4.bit._PFD5 +#define PFDL4_PFD6 _pfdl4.bit._PFD6 +#define PFDL4_PFD7 _pfdl4.bit._PFD7 +__IO_EXTENDED PFDH4STR _pfdh4; +#define PFDH4 _pfdh4.byte +#define PFDH4_PFD8 _pfdh4.bit._PFD8 +#define PFDH4_PFD9 _pfdh4.bit._PFD9 +#define PFDH4_PFD10 _pfdh4.bit._PFD10 +#define PFDH4_PFD11 _pfdh4.bit._PFD11 +#define PFDH4_PFD12 _pfdh4.bit._PFD12 +#define PFDH4_PFD13 _pfdh4.bit._PFD13 +#define PFDH4_PFD14 _pfdh4.bit._PFD14 +#define PFDH4_PFD15 _pfdh4.bit._PFD15 +__IO_EXTENDED PFD5STR _pfd5; +#define PFD5 _pfd5.word +#define PFD5_PFD0 _pfd5.bit._PFD0 +#define PFD5_PFD1 _pfd5.bit._PFD1 +#define PFD5_PFD2 _pfd5.bit._PFD2 +#define PFD5_PFD3 _pfd5.bit._PFD3 +#define PFD5_PFD4 _pfd5.bit._PFD4 +#define PFD5_PFD5 _pfd5.bit._PFD5 +#define PFD5_PFD6 _pfd5.bit._PFD6 +#define PFD5_PFD7 _pfd5.bit._PFD7 +#define PFD5_PFD8 _pfd5.bit._PFD8 +#define PFD5_PFD9 _pfd5.bit._PFD9 +#define PFD5_PFD10 _pfd5.bit._PFD10 +#define PFD5_PFD11 _pfd5.bit._PFD11 +#define PFD5_PFD12 _pfd5.bit._PFD12 +#define PFD5_PFD13 _pfd5.bit._PFD13 +#define PFD5_PFD14 _pfd5.bit._PFD14 +#define PFD5_PFD15 _pfd5.bit._PFD15 +#define PFD5_PFD _pfd5.bitc._PFD +__IO_EXTENDED PFDL5STR _pfdl5; +#define PFDL5 _pfdl5.byte +#define PFDL5_PFD0 _pfdl5.bit._PFD0 +#define PFDL5_PFD1 _pfdl5.bit._PFD1 +#define PFDL5_PFD2 _pfdl5.bit._PFD2 +#define PFDL5_PFD3 _pfdl5.bit._PFD3 +#define PFDL5_PFD4 _pfdl5.bit._PFD4 +#define PFDL5_PFD5 _pfdl5.bit._PFD5 +#define PFDL5_PFD6 _pfdl5.bit._PFD6 +#define PFDL5_PFD7 _pfdl5.bit._PFD7 +__IO_EXTENDED PFDH5STR _pfdh5; +#define PFDH5 _pfdh5.byte +#define PFDH5_PFD8 _pfdh5.bit._PFD8 +#define PFDH5_PFD9 _pfdh5.bit._PFD9 +#define PFDH5_PFD10 _pfdh5.bit._PFD10 +#define PFDH5_PFD11 _pfdh5.bit._PFD11 +#define PFDH5_PFD12 _pfdh5.bit._PFD12 +#define PFDH5_PFD13 _pfdh5.bit._PFD13 +#define PFDH5_PFD14 _pfdh5.bit._PFD14 +#define PFDH5_PFD15 _pfdh5.bit._PFD15 +__IO_EXTENDED PFD6STR _pfd6; +#define PFD6 _pfd6.word +#define PFD6_PFD0 _pfd6.bit._PFD0 +#define PFD6_PFD1 _pfd6.bit._PFD1 +#define PFD6_PFD2 _pfd6.bit._PFD2 +#define PFD6_PFD3 _pfd6.bit._PFD3 +#define PFD6_PFD4 _pfd6.bit._PFD4 +#define PFD6_PFD5 _pfd6.bit._PFD5 +#define PFD6_PFD6 _pfd6.bit._PFD6 +#define PFD6_PFD7 _pfd6.bit._PFD7 +#define PFD6_PFD8 _pfd6.bit._PFD8 +#define PFD6_PFD9 _pfd6.bit._PFD9 +#define PFD6_PFD10 _pfd6.bit._PFD10 +#define PFD6_PFD11 _pfd6.bit._PFD11 +#define PFD6_PFD12 _pfd6.bit._PFD12 +#define PFD6_PFD13 _pfd6.bit._PFD13 +#define PFD6_PFD14 _pfd6.bit._PFD14 +#define PFD6_PFD15 _pfd6.bit._PFD15 +#define PFD6_PFD _pfd6.bitc._PFD +__IO_EXTENDED PFDL6STR _pfdl6; +#define PFDL6 _pfdl6.byte +#define PFDL6_PFD0 _pfdl6.bit._PFD0 +#define PFDL6_PFD1 _pfdl6.bit._PFD1 +#define PFDL6_PFD2 _pfdl6.bit._PFD2 +#define PFDL6_PFD3 _pfdl6.bit._PFD3 +#define PFDL6_PFD4 _pfdl6.bit._PFD4 +#define PFDL6_PFD5 _pfdl6.bit._PFD5 +#define PFDL6_PFD6 _pfdl6.bit._PFD6 +#define PFDL6_PFD7 _pfdl6.bit._PFD7 +__IO_EXTENDED PFDH6STR _pfdh6; +#define PFDH6 _pfdh6.byte +#define PFDH6_PFD8 _pfdh6.bit._PFD8 +#define PFDH6_PFD9 _pfdh6.bit._PFD9 +#define PFDH6_PFD10 _pfdh6.bit._PFD10 +#define PFDH6_PFD11 _pfdh6.bit._PFD11 +#define PFDH6_PFD12 _pfdh6.bit._PFD12 +#define PFDH6_PFD13 _pfdh6.bit._PFD13 +#define PFDH6_PFD14 _pfdh6.bit._PFD14 +#define PFDH6_PFD15 _pfdh6.bit._PFD15 +__IO_EXTENDED PFD7STR _pfd7; +#define PFD7 _pfd7.word +#define PFD7_PFD0 _pfd7.bit._PFD0 +#define PFD7_PFD1 _pfd7.bit._PFD1 +#define PFD7_PFD2 _pfd7.bit._PFD2 +#define PFD7_PFD3 _pfd7.bit._PFD3 +#define PFD7_PFD4 _pfd7.bit._PFD4 +#define PFD7_PFD5 _pfd7.bit._PFD5 +#define PFD7_PFD6 _pfd7.bit._PFD6 +#define PFD7_PFD7 _pfd7.bit._PFD7 +#define PFD7_PFD8 _pfd7.bit._PFD8 +#define PFD7_PFD9 _pfd7.bit._PFD9 +#define PFD7_PFD10 _pfd7.bit._PFD10 +#define PFD7_PFD11 _pfd7.bit._PFD11 +#define PFD7_PFD12 _pfd7.bit._PFD12 +#define PFD7_PFD13 _pfd7.bit._PFD13 +#define PFD7_PFD14 _pfd7.bit._PFD14 +#define PFD7_PFD15 _pfd7.bit._PFD15 +#define PFD7_PFD _pfd7.bitc._PFD +__IO_EXTENDED PFDL7STR _pfdl7; +#define PFDL7 _pfdl7.byte +#define PFDL7_PFD0 _pfdl7.bit._PFD0 +#define PFDL7_PFD1 _pfdl7.bit._PFD1 +#define PFDL7_PFD2 _pfdl7.bit._PFD2 +#define PFDL7_PFD3 _pfdl7.bit._PFD3 +#define PFDL7_PFD4 _pfdl7.bit._PFD4 +#define PFDL7_PFD5 _pfdl7.bit._PFD5 +#define PFDL7_PFD6 _pfdl7.bit._PFD6 +#define PFDL7_PFD7 _pfdl7.bit._PFD7 +__IO_EXTENDED PFDH7STR _pfdh7; +#define PFDH7 _pfdh7.byte +#define PFDH7_PFD8 _pfdh7.bit._PFD8 +#define PFDH7_PFD9 _pfdh7.bit._PFD9 +#define PFDH7_PFD10 _pfdh7.bit._PFD10 +#define PFDH7_PFD11 _pfdh7.bit._PFD11 +#define PFDH7_PFD12 _pfdh7.bit._PFD12 +#define PFDH7_PFD13 _pfdh7.bit._PFD13 +#define PFDH7_PFD14 _pfdh7.bit._PFD14 +#define PFDH7_PFD15 _pfdh7.bit._PFD15 +__IO_EXTENDED MFMCSSTR _mfmcs; +#define MFMCS _mfmcs.byte +#define MFMCS_RDY _mfmcs.bit._RDY +#define MFMCS_RDYINT _mfmcs.bit._RDYINT +#define MFMCS_INTE _mfmcs.bit._INTE +#define MFMCS_WE _mfmcs.bit._WE +#define MFMCS_CRBE _mfmcs.bit._CRBE +#define MFMCS_DRBE _mfmcs.bit._DRBE +#define MFMCS_RD19V _mfmcs.bit._RD19V +__IO_EXTENDED MFMTCSTR _mfmtc; +#define MFMTC _mfmtc.word +#define MFMTC_FAWC0 _mfmtc.bit._FAWC0 +#define MFMTC_FAWC1 _mfmtc.bit._FAWC1 +#define MFMTC_FAWC2 _mfmtc.bit._FAWC2 +#define MFMTC_SYNC _mfmtc.bit._SYNC +#define MFMTC_ADS _mfmtc.bit._ADS +#define MFMTC_CLKBW _mfmtc.bit._CLKBW +#define MFMTC_WEXL _mfmtc.bit._WEXL +#define MFMTC_ATDINIT _mfmtc.bit._ATDINIT +#define MFMTC_ATDL0 _mfmtc.bit._ATDL0 +#define MFMTC_ATDL1 _mfmtc.bit._ATDL1 +#define MFMTC_ATDEQD0 _mfmtc.bit._ATDEQD0 +#define MFMTC_ATDEQD1 _mfmtc.bit._ATDEQD1 +#define MFMTC_EQL0 _mfmtc.bit._EQL0 +#define MFMTC_EQL1 _mfmtc.bit._EQL1 +#define MFMTC_EQL2 _mfmtc.bit._EQL2 +#define MFMTC_FAWC _mfmtc.bitc._FAWC +#define MFMTC_ATDL _mfmtc.bitc._ATDL +#define MFMTC_ATDEQD _mfmtc.bitc._ATDEQD +#define MFMTC_EQL _mfmtc.bitc._EQL +__IO_EXTENDED MFMTCLSTR _mfmtcl; +#define MFMTCL _mfmtcl.byte +#define MFMTCL_FAWC0 _mfmtcl.bit._FAWC0 +#define MFMTCL_FAWC1 _mfmtcl.bit._FAWC1 +#define MFMTCL_FAWC2 _mfmtcl.bit._FAWC2 +#define MFMTCL_SYNC _mfmtcl.bit._SYNC +#define MFMTCL_ADS _mfmtcl.bit._ADS +#define MFMTCL_CLKBW _mfmtcl.bit._CLKBW +#define MFMTCL_WEXL _mfmtcl.bit._WEXL +#define MFMTCL_FAWC _mfmtcl.bitc._FAWC +__IO_EXTENDED MFMTCHSTR _mfmtch; +#define MFMTCH _mfmtch.byte +#define MFMTCH_ATDINIT _mfmtch.bit._ATDINIT +#define MFMTCH_ATDL0 _mfmtch.bit._ATDL0 +#define MFMTCH_ATDL1 _mfmtch.bit._ATDL1 +#define MFMTCH_ATDEQD0 _mfmtch.bit._ATDEQD0 +#define MFMTCH_ATDEQD1 _mfmtch.bit._ATDEQD1 +#define MFMTCH_EQL0 _mfmtch.bit._EQL0 +#define MFMTCH_EQL1 _mfmtch.bit._EQL1 +#define MFMTCH_EQL2 _mfmtch.bit._EQL2 +#define MFMTCH_ATDL _mfmtch.bitc._ATDL +#define MFMTCH_ATDEQD _mfmtch.bitc._ATDEQD +#define MFMTCH_EQL _mfmtch.bitc._EQL +__IO_EXTENDED SFMCSSTR _sfmcs; +#define SFMCS _sfmcs.byte +#define SFMCS_RDY _sfmcs.bit._RDY +#define SFMCS_RDYINT _sfmcs.bit._RDYINT +#define SFMCS_INTE _sfmcs.bit._INTE +#define SFMCS_WE _sfmcs.bit._WE +#define SFMCS_CRBE _sfmcs.bit._CRBE +#define SFMCS_DRBE _sfmcs.bit._DRBE +#define SFMCS_RD19V _sfmcs.bit._RD19V +__IO_EXTENDED SFMTCSTR _sfmtc; +#define SFMTC _sfmtc.word +#define SFMTC_FAWC0 _sfmtc.bit._FAWC0 +#define SFMTC_FAWC1 _sfmtc.bit._FAWC1 +#define SFMTC_FAWC2 _sfmtc.bit._FAWC2 +#define SFMTC_SYNC _sfmtc.bit._SYNC +#define SFMTC_ADS _sfmtc.bit._ADS +#define SFMTC_CLKBW _sfmtc.bit._CLKBW +#define SFMTC_WEXL _sfmtc.bit._WEXL +#define SFMTC_ATDINIT _sfmtc.bit._ATDINIT +#define SFMTC_ATDL0 _sfmtc.bit._ATDL0 +#define SFMTC_ATDL1 _sfmtc.bit._ATDL1 +#define SFMTC_ATDEQD0 _sfmtc.bit._ATDEQD0 +#define SFMTC_ATDEQD1 _sfmtc.bit._ATDEQD1 +#define SFMTC_EQL0 _sfmtc.bit._EQL0 +#define SFMTC_EQL1 _sfmtc.bit._EQL1 +#define SFMTC_EQL2 _sfmtc.bit._EQL2 +#define SFMTC_FAWC _sfmtc.bitc._FAWC +#define SFMTC_ATDL _sfmtc.bitc._ATDL +#define SFMTC_ATDEQD _sfmtc.bitc._ATDEQD +#define SFMTC_EQL _sfmtc.bitc._EQL +__IO_EXTENDED SFMTCLSTR _sfmtcl; +#define SFMTCL _sfmtcl.byte +#define SFMTCL_FAWC0 _sfmtcl.bit._FAWC0 +#define SFMTCL_FAWC1 _sfmtcl.bit._FAWC1 +#define SFMTCL_FAWC2 _sfmtcl.bit._FAWC2 +#define SFMTCL_SYNC _sfmtcl.bit._SYNC +#define SFMTCL_ADS _sfmtcl.bit._ADS +#define SFMTCL_CLKBW _sfmtcl.bit._CLKBW +#define SFMTCL_WEXL _sfmtcl.bit._WEXL +#define SFMTCL_FAWC _sfmtcl.bitc._FAWC +__IO_EXTENDED SFMTCHSTR _sfmtch; +#define SFMTCH _sfmtch.byte +#define SFMTCH_ATDINIT _sfmtch.bit._ATDINIT +#define SFMTCH_ATDL0 _sfmtch.bit._ATDL0 +#define SFMTCH_ATDL1 _sfmtch.bit._ATDL1 +#define SFMTCH_ATDEQD0 _sfmtch.bit._ATDEQD0 +#define SFMTCH_ATDEQD1 _sfmtch.bit._ATDEQD1 +#define SFMTCH_EQL0 _sfmtch.bit._EQL0 +#define SFMTCH_EQL1 _sfmtch.bit._EQL1 +#define SFMTCH_EQL2 _sfmtch.bit._EQL2 +#define SFMTCH_ATDL _sfmtch.bitc._ATDL +#define SFMTCH_ATDEQD _sfmtch.bitc._ATDEQD +#define SFMTCH_EQL _sfmtch.bitc._EQL +__IO_EXTENDED FMWC0STR _fmwc0; +#define FMWC0 _fmwc0.byte +#define FMWC0_WCB0 _fmwc0.bit._WCB0 +#define FMWC0_WCB1 _fmwc0.bit._WCB1 +#define FMWC0_WCB2 _fmwc0.bit._WCB2 +#define FMWC0_WCB3 _fmwc0.bit._WCB3 +#define FMWC0_WCB _fmwc0.bitc._WCB +__IO_EXTENDED FMWC1STR _fmwc1; +#define FMWC1 _fmwc1.byte +#define FMWC1_WCA0 _fmwc1.bit._WCA0 +#define FMWC1_WCA1 _fmwc1.bit._WCA1 +#define FMWC1_WCA2 _fmwc1.bit._WCA2 +#define FMWC1_WCA3 _fmwc1.bit._WCA3 +#define FMWC1_WCA _fmwc1.bitc._WCA +__IO_EXTENDED IO_BYTE _fmwc2; +#define FMWC2 _fmwc2 +__IO_EXTENDED IO_BYTE _fmwc3; +#define FMWC3 _fmwc3 +__IO_EXTENDED IO_BYTE _fmwc4; +#define FMWC4 _fmwc4 +__IO_EXTENDED FMWC5STR _fmwc5; +#define FMWC5 _fmwc5.byte +#define FMWC5_WC32 _fmwc5.bit._WC32 +#define FMWC5_WC33 _fmwc5.bit._WC33 +#define FMWC5_WC34 _fmwc5.bit._WC34 +#define FMWC5_WC35 _fmwc5.bit._WC35 +#define FMWC5_WC36 _fmwc5.bit._WC36 +#define FMWC5_WC37 _fmwc5.bit._WC37 +#define FMWC5_WC38 _fmwc5.bit._WC38 +#define FMWC5_WC39 _fmwc5.bit._WC39 +#define FMWC5_WC3 _fmwc5.bitc._WC3 +__IO_EXTENDED SMCRSTR _smcr; +#define SMCR _smcr.byte +#define SMCR_SMS0 _smcr.bit._SMS0 +#define SMCR_SMS1 _smcr.bit._SMS1 +#define SMCR_SPL _smcr.bit._SPL +#define SMCR_SMS _smcr.bitc._SMS +__IO_EXTENDED CKSRSTR _cksr; +#define CKSR _cksr.byte +#define CKSR_SC1S0 _cksr.bit._SC1S0 +#define CKSR_SC1S1 _cksr.bit._SC1S1 +#define CKSR_SC2S0 _cksr.bit._SC2S0 +#define CKSR_SC2S1 _cksr.bit._SC2S1 +#define CKSR_RCE _cksr.bit._RCE +#define CKSR_MCE _cksr.bit._MCE +#define CKSR_PCE _cksr.bit._PCE +#define CKSR_SC1S _cksr.bitc._SC1S +#define CKSR_SC2S _cksr.bitc._SC2S +__IO_EXTENDED CKSSRSTR _ckssr; +#define CKSSR _ckssr.byte +#define CKSSR_MCST0 _ckssr.bit._MCST0 +#define CKSSR_MCST1 _ckssr.bit._MCST1 +#define CKSSR_MCST2 _ckssr.bit._MCST2 +#define CKSSR_PCST _ckssr.bit._PCST +#define CKSSR_MRFBE _ckssr.bit._MRFBE +#define CKSSR_MCST _ckssr.bitc._MCST +__IO_EXTENDED CKMRSTR _ckmr; +#define CKMR _ckmr.byte +#define CKMR_SC1M0 _ckmr.bit._SC1M0 +#define CKMR_SC1M1 _ckmr.bit._SC1M1 +#define CKMR_SC2M0 _ckmr.bit._SC2M0 +#define CKMR_SC2M1 _ckmr.bit._SC2M1 +#define CKMR_RCM _ckmr.bit._RCM +#define CKMR_MCM _ckmr.bit._MCM +#define CKMR_PCM _ckmr.bit._PCM +#define CKMR_SC1M _ckmr.bitc._SC1M +#define CKMR_SC2M _ckmr.bitc._SC2M +__IO_EXTENDED CKFCRSTR _ckfcr; +#define CKFCR _ckfcr.word +#define CKFCR_RCFS _ckfcr.bit._RCFS +#define CKFCR_BCD0 _ckfcr.bit._BCD0 +#define CKFCR_BCD1 _ckfcr.bit._BCD1 +#define CKFCR_BCD2 _ckfcr.bit._BCD2 +#define CKFCR_BCD3 _ckfcr.bit._BCD3 +#define CKFCR_PC1D0 _ckfcr.bit._PC1D0 +#define CKFCR_PC1D1 _ckfcr.bit._PC1D1 +#define CKFCR_PC1D2 _ckfcr.bit._PC1D2 +#define CKFCR_PC1D3 _ckfcr.bit._PC1D3 +#define CKFCR_PC2D0 _ckfcr.bit._PC2D0 +#define CKFCR_PC2D1 _ckfcr.bit._PC2D1 +#define CKFCR_PC2D2 _ckfcr.bit._PC2D2 +#define CKFCR_PC2D3 _ckfcr.bit._PC2D3 +#define CKFCR_BCD _ckfcr.bitc._BCD +#define CKFCR_PC1D _ckfcr.bitc._PC1D +#define CKFCR_PC2D _ckfcr.bitc._PC2D +__IO_EXTENDED CKFCRLSTR _ckfcrl; +#define CKFCRL _ckfcrl.byte +#define CKFCRL_RCFS _ckfcrl.bit._RCFS +#define CKFCRL_BCD0 _ckfcrl.bit._BCD0 +#define CKFCRL_BCD1 _ckfcrl.bit._BCD1 +#define CKFCRL_BCD2 _ckfcrl.bit._BCD2 +#define CKFCRL_BCD3 _ckfcrl.bit._BCD3 +#define CKFCRL_BCD _ckfcrl.bitc._BCD +__IO_EXTENDED CKFCRHSTR _ckfcrh; +#define CKFCRH _ckfcrh.byte +#define CKFCRH_PC1D0 _ckfcrh.bit._PC1D0 +#define CKFCRH_PC1D1 _ckfcrh.bit._PC1D1 +#define CKFCRH_PC1D2 _ckfcrh.bit._PC1D2 +#define CKFCRH_PC1D3 _ckfcrh.bit._PC1D3 +#define CKFCRH_PC2D0 _ckfcrh.bit._PC2D0 +#define CKFCRH_PC2D1 _ckfcrh.bit._PC2D1 +#define CKFCRH_PC2D2 _ckfcrh.bit._PC2D2 +#define CKFCRH_PC2D3 _ckfcrh.bit._PC2D3 +#define CKFCRH_PC1D _ckfcrh.bitc._PC1D +#define CKFCRH_PC2D _ckfcrh.bitc._PC2D +__IO_EXTENDED PLLCRSTR _pllcr; +#define PLLCR _pllcr.word +#define PLLCR_PMS0 _pllcr.bit._PMS0 +#define PLLCR_PMS1 _pllcr.bit._PMS1 +#define PLLCR_PMS2 _pllcr.bit._PMS2 +#define PLLCR_PMS3 _pllcr.bit._PMS3 +#define PLLCR_PMS4 _pllcr.bit._PMS4 +#define PLLCR_VMS0 _pllcr.bit._VMS0 +#define PLLCR_VMS1 _pllcr.bit._VMS1 +#define PLLCR_VMS2 _pllcr.bit._VMS2 +#define PLLCR_PC3D0 _pllcr.bit._PC3D0 +#define PLLCR_PC3D1 _pllcr.bit._PC3D1 +#define PLLCR_PC3D2 _pllcr.bit._PC3D2 +#define PLLCR_PC3D3 _pllcr.bit._PC3D3 +#define PLLCR_PMS _pllcr.bitc._PMS +#define PLLCR_VMS _pllcr.bitc._VMS +#define PLLCR_PC3D _pllcr.bitc._PC3D +__IO_EXTENDED PLLCRLSTR _pllcrl; +#define PLLCRL _pllcrl.byte +#define PLLCRL_PMS0 _pllcrl.bit._PMS0 +#define PLLCRL_PMS1 _pllcrl.bit._PMS1 +#define PLLCRL_PMS2 _pllcrl.bit._PMS2 +#define PLLCRL_PMS3 _pllcrl.bit._PMS3 +#define PLLCRL_PMS4 _pllcrl.bit._PMS4 +#define PLLCRL_VMS0 _pllcrl.bit._VMS0 +#define PLLCRL_VMS1 _pllcrl.bit._VMS1 +#define PLLCRL_VMS2 _pllcrl.bit._VMS2 +#define PLLCRL_PMS _pllcrl.bitc._PMS +#define PLLCRL_VMS _pllcrl.bitc._VMS +__IO_EXTENDED PLLCRHSTR _pllcrh; +#define PLLCRH _pllcrh.byte +#define PLLCRH_PC3D0 _pllcrh.bit._PC3D0 +#define PLLCRH_PC3D1 _pllcrh.bit._PC3D1 +#define PLLCRH_PC3D2 _pllcrh.bit._PC3D2 +#define PLLCRH_PC3D3 _pllcrh.bit._PC3D3 +#define PLLCRH_PC3D _pllcrh.bitc._PC3D +__IO_EXTENDED RCTCRSTR _rctcr; +#define RCTCR _rctcr.byte +#define RCTCR_RCTI0 _rctcr.bit._RCTI0 +#define RCTCR_RCTI1 _rctcr.bit._RCTI1 +#define RCTCR_RCTI2 _rctcr.bit._RCTI2 +#define RCTCR_RCTI3 _rctcr.bit._RCTI3 +#define RCTCR_RCTR _rctcr.bit._RCTR +#define RCTCR_RCTIF _rctcr.bit._RCTIF +#define RCTCR_RCTIE _rctcr.bit._RCTIE +#define RCTCR_RCTI _rctcr.bitc._RCTI +__IO_EXTENDED MCTCRSTR _mctcr; +#define MCTCR _mctcr.byte +#define MCTCR_MCTI0 _mctcr.bit._MCTI0 +#define MCTCR_MCTI1 _mctcr.bit._MCTI1 +#define MCTCR_MCTI2 _mctcr.bit._MCTI2 +#define MCTCR_MCTI3 _mctcr.bit._MCTI3 +#define MCTCR_MCTR _mctcr.bit._MCTR +#define MCTCR_MCTIF _mctcr.bit._MCTIF +#define MCTCR_MCTIE _mctcr.bit._MCTIE +#define MCTCR_MCTI _mctcr.bitc._MCTI +__IO_EXTENDED RCCSRCSTR _rccsrc; +#define RCCSRC _rccsrc.byte +#define RCCSRC_PRST _rccsrc.bit._PRST +#define RCCSRC_ERST _rccsrc.bit._ERST +#define RCCSRC_MCRST _rccsrc.bit._MCRST +#define RCCSRC_SRST _rccsrc.bit._SRST +#define RCCSRC_WRST _rccsrc.bit._WRST +#define RCCSRC_MCMF _rccsrc.bit._MCMF +__IO_EXTENDED RCRSTR _rcr; +#define RCR _rcr.byte +#define RCR_SRSTG _rcr.bit._SRSTG +#define RCR_LVRE _rcr.bit._LVRE +#define RCR_LVDE _rcr.bit._LVDE +#define RCR_CSDRE _rcr.bit._CSDRE +#define RCR_MCSDI _rcr.bit._MCSDI +__IO_EXTENDED RCCSRSTR _rccsr; +#define RCCSR _rccsr.byte +#define RCCSR_PRST _rccsr.bit._PRST +#define RCCSR_ERST _rccsr.bit._ERST +#define RCCSR_MCRST _rccsr.bit._MCRST +#define RCCSR_SRST _rccsr.bit._SRST +#define RCCSR_WRST _rccsr.bit._WRST +#define RCCSR_MCMF _rccsr.bit._MCMF +__IO_EXTENDED WDTCSTR _wdtc; +#define WDTC _wdtc.byte +#define WDTC_WTI0 _wdtc.bit._WTI0 +#define WDTC_WTI1 _wdtc.bit._WTI1 +#define WDTC_WTI2 _wdtc.bit._WTI2 +#define WDTC_WTI3 _wdtc.bit._WTI3 +#define WDTC_WTCS0 _wdtc.bit._WTCS0 +#define WDTC_WTCS1 _wdtc.bit._WTCS1 +#define WDTC_RSTP _wdtc.bit._RSTP +#define WDTC_WTI _wdtc.bitc._WTI +#define WDTC_WTCS _wdtc.bitc._WTCS +__IO_EXTENDED WDTCPSTR _wdtcp; +#define WDTCP _wdtcp.byte +#define WDTCP_WCP0 _wdtcp.bit._WCP0 +#define WDTCP_WCP1 _wdtcp.bit._WCP1 +#define WDTCP_WCP2 _wdtcp.bit._WCP2 +#define WDTCP_WCP3 _wdtcp.bit._WCP3 +#define WDTCP_WCP4 _wdtcp.bit._WCP4 +#define WDTCP_WCP5 _wdtcp.bit._WCP5 +#define WDTCP_WCP6 _wdtcp.bit._WCP6 +#define WDTCP_WCP7 _wdtcp.bit._WCP7 +#define WDTCP_WCP _wdtcp.bitc._WCP +__IO_EXTENDED COARSTR _coar; +#define COAR _coar.byte +#define COAR_CKOE0 _coar.bit._CKOE0 +#define COAR_CKOXE0 _coar.bit._CKOXE0 +#define COAR_RUNC0 _coar.bit._RUNC0 +#define COAR_RUNM0 _coar.bit._RUNM0 +#define COAR_CKOE1 _coar.bit._CKOE1 +#define COAR_CKOXE1 _coar.bit._CKOXE1 +#define COAR_RUNC1 _coar.bit._RUNC1 +#define COAR_RUNM1 _coar.bit._RUNM1 +__IO_EXTENDED COCR0STR _cocr0; +#define COCR0 _cocr0.byte +#define COCR0_SEL0 _cocr0.bit._SEL0 +#define COCR0_SEL1 _cocr0.bit._SEL1 +#define COCR0_SEL2 _cocr0.bit._SEL2 +#define COCR0_SEL3 _cocr0.bit._SEL3 +#define COCR0_DIV0 _cocr0.bit._DIV0 +#define COCR0_DIV1 _cocr0.bit._DIV1 +#define COCR0_DIV2 _cocr0.bit._DIV2 +#define COCR0_SEL _cocr0.bitc._SEL +#define COCR0_DIV _cocr0.bitc._DIV +__IO_EXTENDED COCR1STR _cocr1; +#define COCR1 _cocr1.byte +#define COCR1_SEL0 _cocr1.bit._SEL0 +#define COCR1_SEL1 _cocr1.bit._SEL1 +#define COCR1_SEL2 _cocr1.bit._SEL2 +#define COCR1_SEL3 _cocr1.bit._SEL3 +#define COCR1_DIV0 _cocr1.bit._DIV0 +#define COCR1_DIV1 _cocr1.bit._DIV1 +#define COCR1_DIV2 _cocr1.bit._DIV2 +#define COCR1_SEL _cocr1.bitc._SEL +#define COCR1_DIV _cocr1.bitc._DIV +__IO_EXTENDED CMCRSTR _cmcr; +#define CMCR _cmcr.byte +#define CMCR_PDX _cmcr.bit._PDX +#define CMCR_MODEN _cmcr.bit._MODEN +#define CMCR_MODRUN _cmcr.bit._MODRUN +__IO_EXTENDED CMPRSTR _cmpr; +#define CMPR _cmpr.word +#define CMPR_C0 _cmpr.bit._C0 +#define CMPR_C1 _cmpr.bit._C1 +#define CMPR_C2 _cmpr.bit._C2 +#define CMPR_C3 _cmpr.bit._C3 +#define CMPR_C4 _cmpr.bit._C4 +#define CMPR_N0 _cmpr.bit._N0 +#define CMPR_N1 _cmpr.bit._N1 +#define CMPR_N2 _cmpr.bit._N2 +#define CMPR_N3 _cmpr.bit._N3 +#define CMPR_K0 _cmpr.bit._K0 +#define CMPR_K1 _cmpr.bit._K1 +#define CMPR_K2 _cmpr.bit._K2 +#define CMPR_K3 _cmpr.bit._K3 +#define CMPR_K4 _cmpr.bit._K4 +#define CMPR_C _cmpr.bitc._C +#define CMPR_N _cmpr.bitc._N +#define CMPR_K _cmpr.bitc._K +__IO_EXTENDED CMPRLSTR _cmprl; +#define CMPRL _cmprl.byte +#define CMPRL_C0 _cmprl.bit._C0 +#define CMPRL_C1 _cmprl.bit._C1 +#define CMPRL_C2 _cmprl.bit._C2 +#define CMPRL_C3 _cmprl.bit._C3 +#define CMPRL_C4 _cmprl.bit._C4 +#define CMPRL_N0 _cmprl.bit._N0 +#define CMPRL_N1 _cmprl.bit._N1 +#define CMPRL_N2 _cmprl.bit._N2 +#define CMPRL_C _cmprl.bitc._C +#define CMPRL_N _cmprl.bitc._N +__IO_EXTENDED CMPRHSTR _cmprh; +#define CMPRH _cmprh.byte +#define CMPRH_N3 _cmprh.bit._N3 +#define CMPRH_K0 _cmprh.bit._K0 +#define CMPRH_K1 _cmprh.bit._K1 +#define CMPRH_K2 _cmprh.bit._K2 +#define CMPRH_K3 _cmprh.bit._K3 +#define CMPRH_K4 _cmprh.bit._K4 +#define CMPRH_K _cmprh.bitc._K +__IO_EXTENDED VRCRSTR _vrcr; +#define VRCR _vrcr.byte +#define VRCR_LPBM0 _vrcr.bit._LPBM0 +#define VRCR_LPBM1 _vrcr.bit._LPBM1 +#define VRCR_LPMB2 _vrcr.bit._LPMB2 +#define VRCR_LPMA0 _vrcr.bit._LPMA0 +#define VRCR_LPMA1 _vrcr.bit._LPMA1 +#define VRCR_LPMA2 _vrcr.bit._LPMA2 +#define VRCR_HPM0 _vrcr.bit._HPM0 +#define VRCR_HPM1 _vrcr.bit._HPM1 +#define VRCR_LPBM _vrcr.bitc._LPBM +#define VRCR_LPMA _vrcr.bitc._LPMA +#define VRCR_HPM _vrcr.bitc._HPM +__IO_EXTENDED DDR00STR _ddr00; +#define DDR00 _ddr00.byte +#define DDR00_D0 _ddr00.bit._D0 +#define DDR00_D1 _ddr00.bit._D1 +#define DDR00_D2 _ddr00.bit._D2 +#define DDR00_D3 _ddr00.bit._D3 +#define DDR00_D4 _ddr00.bit._D4 +#define DDR00_D5 _ddr00.bit._D5 +#define DDR00_D6 _ddr00.bit._D6 +#define DDR00_D7 _ddr00.bit._D7 +__IO_EXTENDED DDR01STR _ddr01; +#define DDR01 _ddr01.byte +#define DDR01_D0 _ddr01.bit._D0 +#define DDR01_D1 _ddr01.bit._D1 +#define DDR01_D2 _ddr01.bit._D2 +#define DDR01_D3 _ddr01.bit._D3 +#define DDR01_D4 _ddr01.bit._D4 +#define DDR01_D5 _ddr01.bit._D5 +#define DDR01_D6 _ddr01.bit._D6 +#define DDR01_D7 _ddr01.bit._D7 +__IO_EXTENDED DDR02STR _ddr02; +#define DDR02 _ddr02.byte +#define DDR02_D0 _ddr02.bit._D0 +#define DDR02_D1 _ddr02.bit._D1 +#define DDR02_D2 _ddr02.bit._D2 +#define DDR02_D3 _ddr02.bit._D3 +#define DDR02_D4 _ddr02.bit._D4 +#define DDR02_D5 _ddr02.bit._D5 +#define DDR02_D6 _ddr02.bit._D6 +#define DDR02_D7 _ddr02.bit._D7 +__IO_EXTENDED DDR03STR _ddr03; +#define DDR03 _ddr03.byte +#define DDR03_D0 _ddr03.bit._D0 +#define DDR03_D1 _ddr03.bit._D1 +#define DDR03_D2 _ddr03.bit._D2 +#define DDR03_D3 _ddr03.bit._D3 +#define DDR03_D4 _ddr03.bit._D4 +#define DDR03_D5 _ddr03.bit._D5 +#define DDR03_D6 _ddr03.bit._D6 +#define DDR03_D7 _ddr03.bit._D7 +__IO_EXTENDED DDR04STR _ddr04; +#define DDR04 _ddr04.byte +#define DDR04_D0 _ddr04.bit._D0 +#define DDR04_D1 _ddr04.bit._D1 +#define DDR04_D2 _ddr04.bit._D2 +#define DDR04_D3 _ddr04.bit._D3 +#define DDR04_D4 _ddr04.bit._D4 +#define DDR04_D5 _ddr04.bit._D5 +#define DDR04_D6 _ddr04.bit._D6 +#define DDR04_D7 _ddr04.bit._D7 +__IO_EXTENDED DDR05STR _ddr05; +#define DDR05 _ddr05.byte +#define DDR05_D0 _ddr05.bit._D0 +#define DDR05_D1 _ddr05.bit._D1 +#define DDR05_D2 _ddr05.bit._D2 +#define DDR05_D3 _ddr05.bit._D3 +#define DDR05_D4 _ddr05.bit._D4 +#define DDR05_D5 _ddr05.bit._D5 +#define DDR05_D6 _ddr05.bit._D6 +#define DDR05_D7 _ddr05.bit._D7 +__IO_EXTENDED DDR06STR _ddr06; +#define DDR06 _ddr06.byte +#define DDR06_D0 _ddr06.bit._D0 +#define DDR06_D1 _ddr06.bit._D1 +#define DDR06_D2 _ddr06.bit._D2 +#define DDR06_D3 _ddr06.bit._D3 +#define DDR06_D4 _ddr06.bit._D4 +#define DDR06_D5 _ddr06.bit._D5 +#define DDR06_D6 _ddr06.bit._D6 +#define DDR06_D7 _ddr06.bit._D7 +__IO_EXTENDED DDR07STR _ddr07; +#define DDR07 _ddr07.byte +#define DDR07_D0 _ddr07.bit._D0 +#define DDR07_D1 _ddr07.bit._D1 +#define DDR07_D2 _ddr07.bit._D2 +#define DDR07_D3 _ddr07.bit._D3 +#define DDR07_D4 _ddr07.bit._D4 +#define DDR07_D5 _ddr07.bit._D5 +#define DDR07_D6 _ddr07.bit._D6 +#define DDR07_D7 _ddr07.bit._D7 +__IO_EXTENDED DDR08STR _ddr08; +#define DDR08 _ddr08.byte +#define DDR08_D0 _ddr08.bit._D0 +#define DDR08_D1 _ddr08.bit._D1 +#define DDR08_D2 _ddr08.bit._D2 +#define DDR08_D3 _ddr08.bit._D3 +#define DDR08_D4 _ddr08.bit._D4 +#define DDR08_D5 _ddr08.bit._D5 +#define DDR08_D6 _ddr08.bit._D6 +#define DDR08_D7 _ddr08.bit._D7 +__IO_EXTENDED DDR09STR _ddr09; +#define DDR09 _ddr09.byte +#define DDR09_D0 _ddr09.bit._D0 +#define DDR09_D1 _ddr09.bit._D1 +#define DDR09_D2 _ddr09.bit._D2 +#define DDR09_D3 _ddr09.bit._D3 +#define DDR09_D4 _ddr09.bit._D4 +#define DDR09_D5 _ddr09.bit._D5 +#define DDR09_D6 _ddr09.bit._D6 +#define DDR09_D7 _ddr09.bit._D7 +__IO_EXTENDED DDR10STR _ddr10; +#define DDR10 _ddr10.byte +#define DDR10_D0 _ddr10.bit._D0 +#define DDR10_D1 _ddr10.bit._D1 +__IO_EXTENDED PIER00STR _pier00; +#define PIER00 _pier00.byte +#define PIER00_IE0 _pier00.bit._IE0 +#define PIER00_IE1 _pier00.bit._IE1 +#define PIER00_IE2 _pier00.bit._IE2 +#define PIER00_IE3 _pier00.bit._IE3 +#define PIER00_IE4 _pier00.bit._IE4 +#define PIER00_IE5 _pier00.bit._IE5 +#define PIER00_IE6 _pier00.bit._IE6 +#define PIER00_IE7 _pier00.bit._IE7 +__IO_EXTENDED PIER01STR _pier01; +#define PIER01 _pier01.byte +#define PIER01_IE0 _pier01.bit._IE0 +#define PIER01_IE1 _pier01.bit._IE1 +#define PIER01_IE2 _pier01.bit._IE2 +#define PIER01_IE3 _pier01.bit._IE3 +#define PIER01_IE4 _pier01.bit._IE4 +#define PIER01_IE5 _pier01.bit._IE5 +#define PIER01_IE6 _pier01.bit._IE6 +#define PIER01_IE7 _pier01.bit._IE7 +__IO_EXTENDED PIER02STR _pier02; +#define PIER02 _pier02.byte +#define PIER02_IE0 _pier02.bit._IE0 +#define PIER02_IE1 _pier02.bit._IE1 +#define PIER02_IE2 _pier02.bit._IE2 +#define PIER02_IE3 _pier02.bit._IE3 +#define PIER02_IE4 _pier02.bit._IE4 +#define PIER02_IE5 _pier02.bit._IE5 +#define PIER02_IE6 _pier02.bit._IE6 +#define PIER02_IE7 _pier02.bit._IE7 +__IO_EXTENDED PIER03STR _pier03; +#define PIER03 _pier03.byte +#define PIER03_IE0 _pier03.bit._IE0 +#define PIER03_IE1 _pier03.bit._IE1 +#define PIER03_IE2 _pier03.bit._IE2 +#define PIER03_IE3 _pier03.bit._IE3 +#define PIER03_IE4 _pier03.bit._IE4 +#define PIER03_IE5 _pier03.bit._IE5 +#define PIER03_IE6 _pier03.bit._IE6 +#define PIER03_IE7 _pier03.bit._IE7 +__IO_EXTENDED PIER04STR _pier04; +#define PIER04 _pier04.byte +#define PIER04_IE0 _pier04.bit._IE0 +#define PIER04_IE1 _pier04.bit._IE1 +#define PIER04_IE2 _pier04.bit._IE2 +#define PIER04_IE3 _pier04.bit._IE3 +#define PIER04_IE4 _pier04.bit._IE4 +#define PIER04_IE5 _pier04.bit._IE5 +#define PIER04_IE6 _pier04.bit._IE6 +#define PIER04_IE7 _pier04.bit._IE7 +__IO_EXTENDED PIER05STR _pier05; +#define PIER05 _pier05.byte +#define PIER05_IE0 _pier05.bit._IE0 +#define PIER05_IE1 _pier05.bit._IE1 +#define PIER05_IE2 _pier05.bit._IE2 +#define PIER05_IE3 _pier05.bit._IE3 +#define PIER05_IE4 _pier05.bit._IE4 +#define PIER05_IE5 _pier05.bit._IE5 +#define PIER05_IE6 _pier05.bit._IE6 +#define PIER05_IE7 _pier05.bit._IE7 +__IO_EXTENDED PIER06STR _pier06; +#define PIER06 _pier06.byte +#define PIER06_IE0 _pier06.bit._IE0 +#define PIER06_IE1 _pier06.bit._IE1 +#define PIER06_IE2 _pier06.bit._IE2 +#define PIER06_IE3 _pier06.bit._IE3 +#define PIER06_IE4 _pier06.bit._IE4 +#define PIER06_IE5 _pier06.bit._IE5 +#define PIER06_IE6 _pier06.bit._IE6 +#define PIER06_IE7 _pier06.bit._IE7 +__IO_EXTENDED PIER07STR _pier07; +#define PIER07 _pier07.byte +#define PIER07_IE0 _pier07.bit._IE0 +#define PIER07_IE1 _pier07.bit._IE1 +#define PIER07_IE2 _pier07.bit._IE2 +#define PIER07_IE3 _pier07.bit._IE3 +#define PIER07_IE4 _pier07.bit._IE4 +#define PIER07_IE5 _pier07.bit._IE5 +#define PIER07_IE6 _pier07.bit._IE6 +#define PIER07_IE7 _pier07.bit._IE7 +__IO_EXTENDED PIER08STR _pier08; +#define PIER08 _pier08.byte +#define PIER08_IE0 _pier08.bit._IE0 +#define PIER08_IE1 _pier08.bit._IE1 +#define PIER08_IE2 _pier08.bit._IE2 +#define PIER08_IE3 _pier08.bit._IE3 +#define PIER08_IE4 _pier08.bit._IE4 +#define PIER08_IE5 _pier08.bit._IE5 +#define PIER08_IE6 _pier08.bit._IE6 +#define PIER08_IE7 _pier08.bit._IE7 +__IO_EXTENDED PIER09STR _pier09; +#define PIER09 _pier09.byte +#define PIER09_IE0 _pier09.bit._IE0 +#define PIER09_IE1 _pier09.bit._IE1 +#define PIER09_IE2 _pier09.bit._IE2 +#define PIER09_IE3 _pier09.bit._IE3 +#define PIER09_IE4 _pier09.bit._IE4 +#define PIER09_IE5 _pier09.bit._IE5 +#define PIER09_IE6 _pier09.bit._IE6 +#define PIER09_IE7 _pier09.bit._IE7 +__IO_EXTENDED PIER10STR _pier10; +#define PIER10 _pier10.byte +#define PIER10_IE0 _pier10.bit._IE0 +#define PIER10_IE1 _pier10.bit._IE1 +__IO_EXTENDED PILR00STR _pilr00; +#define PILR00 _pilr00.byte +#define PILR00_IL0 _pilr00.bit._IL0 +#define PILR00_IL1 _pilr00.bit._IL1 +#define PILR00_IL2 _pilr00.bit._IL2 +#define PILR00_IL3 _pilr00.bit._IL3 +#define PILR00_IL4 _pilr00.bit._IL4 +#define PILR00_IL5 _pilr00.bit._IL5 +#define PILR00_IL6 _pilr00.bit._IL6 +#define PILR00_IL7 _pilr00.bit._IL7 +__IO_EXTENDED PILR01STR _pilr01; +#define PILR01 _pilr01.byte +#define PILR01_IL0 _pilr01.bit._IL0 +#define PILR01_IL1 _pilr01.bit._IL1 +#define PILR01_IL2 _pilr01.bit._IL2 +#define PILR01_IL3 _pilr01.bit._IL3 +#define PILR01_IL4 _pilr01.bit._IL4 +#define PILR01_IL5 _pilr01.bit._IL5 +#define PILR01_IL6 _pilr01.bit._IL6 +#define PILR01_IL7 _pilr01.bit._IL7 +__IO_EXTENDED PILR02STR _pilr02; +#define PILR02 _pilr02.byte +#define PILR02_IL0 _pilr02.bit._IL0 +#define PILR02_IL1 _pilr02.bit._IL1 +#define PILR02_IL2 _pilr02.bit._IL2 +#define PILR02_IL3 _pilr02.bit._IL3 +#define PILR02_IL4 _pilr02.bit._IL4 +#define PILR02_IL5 _pilr02.bit._IL5 +#define PILR02_IL6 _pilr02.bit._IL6 +#define PILR02_IL7 _pilr02.bit._IL7 +__IO_EXTENDED PILR03STR _pilr03; +#define PILR03 _pilr03.byte +#define PILR03_IL0 _pilr03.bit._IL0 +#define PILR03_IL1 _pilr03.bit._IL1 +#define PILR03_IL2 _pilr03.bit._IL2 +#define PILR03_IL3 _pilr03.bit._IL3 +#define PILR03_IL4 _pilr03.bit._IL4 +#define PILR03_IL5 _pilr03.bit._IL5 +#define PILR03_IL6 _pilr03.bit._IL6 +#define PILR03_IL7 _pilr03.bit._IL7 +__IO_EXTENDED PILR04STR _pilr04; +#define PILR04 _pilr04.byte +#define PILR04_IL0 _pilr04.bit._IL0 +#define PILR04_IL1 _pilr04.bit._IL1 +#define PILR04_IL2 _pilr04.bit._IL2 +#define PILR04_IL3 _pilr04.bit._IL3 +#define PILR04_IL4 _pilr04.bit._IL4 +#define PILR04_IL5 _pilr04.bit._IL5 +#define PILR04_IL6 _pilr04.bit._IL6 +#define PILR04_IL7 _pilr04.bit._IL7 +__IO_EXTENDED PILR05STR _pilr05; +#define PILR05 _pilr05.byte +#define PILR05_IL0 _pilr05.bit._IL0 +#define PILR05_IL1 _pilr05.bit._IL1 +#define PILR05_IL2 _pilr05.bit._IL2 +#define PILR05_IL3 _pilr05.bit._IL3 +#define PILR05_IL4 _pilr05.bit._IL4 +#define PILR05_IL5 _pilr05.bit._IL5 +#define PILR05_IL6 _pilr05.bit._IL6 +#define PILR05_IL7 _pilr05.bit._IL7 +__IO_EXTENDED PILR06STR _pilr06; +#define PILR06 _pilr06.byte +#define PILR06_IL0 _pilr06.bit._IL0 +#define PILR06_IL1 _pilr06.bit._IL1 +#define PILR06_IL2 _pilr06.bit._IL2 +#define PILR06_IL3 _pilr06.bit._IL3 +#define PILR06_IL4 _pilr06.bit._IL4 +#define PILR06_IL5 _pilr06.bit._IL5 +#define PILR06_IL6 _pilr06.bit._IL6 +#define PILR06_IL7 _pilr06.bit._IL7 +__IO_EXTENDED PILR07STR _pilr07; +#define PILR07 _pilr07.byte +#define PILR07_IL0 _pilr07.bit._IL0 +#define PILR07_IL1 _pilr07.bit._IL1 +#define PILR07_IL2 _pilr07.bit._IL2 +#define PILR07_IL3 _pilr07.bit._IL3 +#define PILR07_IL4 _pilr07.bit._IL4 +#define PILR07_IL5 _pilr07.bit._IL5 +#define PILR07_IL6 _pilr07.bit._IL6 +#define PILR07_IL7 _pilr07.bit._IL7 +__IO_EXTENDED PILR08STR _pilr08; +#define PILR08 _pilr08.byte +#define PILR08_IL0 _pilr08.bit._IL0 +#define PILR08_IL1 _pilr08.bit._IL1 +#define PILR08_IL2 _pilr08.bit._IL2 +#define PILR08_IL3 _pilr08.bit._IL3 +#define PILR08_IL4 _pilr08.bit._IL4 +#define PILR08_IL5 _pilr08.bit._IL5 +#define PILR08_IL6 _pilr08.bit._IL6 +#define PILR08_IL7 _pilr08.bit._IL7 +__IO_EXTENDED PILR09STR _pilr09; +#define PILR09 _pilr09.byte +#define PILR09_IL0 _pilr09.bit._IL0 +#define PILR09_IL1 _pilr09.bit._IL1 +#define PILR09_IL2 _pilr09.bit._IL2 +#define PILR09_IL3 _pilr09.bit._IL3 +#define PILR09_IL4 _pilr09.bit._IL4 +#define PILR09_IL5 _pilr09.bit._IL5 +#define PILR09_IL6 _pilr09.bit._IL6 +#define PILR09_IL7 _pilr09.bit._IL7 +__IO_EXTENDED PILR10STR _pilr10; +#define PILR10 _pilr10.byte +#define PILR10_IL0 _pilr10.bit._IL0 +#define PILR10_IL1 _pilr10.bit._IL1 +__IO_EXTENDED EPILR00STR _epilr00; +#define EPILR00 _epilr00.byte +#define EPILR00_EIL0 _epilr00.bit._EIL0 +#define EPILR00_EIL1 _epilr00.bit._EIL1 +#define EPILR00_EIL2 _epilr00.bit._EIL2 +#define EPILR00_EIL3 _epilr00.bit._EIL3 +#define EPILR00_EIL4 _epilr00.bit._EIL4 +#define EPILR00_EIL5 _epilr00.bit._EIL5 +#define EPILR00_EIL6 _epilr00.bit._EIL6 +#define EPILR00_EIL7 _epilr00.bit._EIL7 +__IO_EXTENDED EPILR01STR _epilr01; +#define EPILR01 _epilr01.byte +#define EPILR01_EIL0 _epilr01.bit._EIL0 +#define EPILR01_EIL1 _epilr01.bit._EIL1 +#define EPILR01_EIL2 _epilr01.bit._EIL2 +#define EPILR01_EIL3 _epilr01.bit._EIL3 +#define EPILR01_EIL4 _epilr01.bit._EIL4 +#define EPILR01_EIL5 _epilr01.bit._EIL5 +#define EPILR01_EIL6 _epilr01.bit._EIL6 +#define EPILR01_EIL7 _epilr01.bit._EIL7 +__IO_EXTENDED EPILR02STR _epilr02; +#define EPILR02 _epilr02.byte +#define EPILR02_EIL0 _epilr02.bit._EIL0 +#define EPILR02_EIL1 _epilr02.bit._EIL1 +#define EPILR02_EIL2 _epilr02.bit._EIL2 +#define EPILR02_EIL3 _epilr02.bit._EIL3 +#define EPILR02_EIL4 _epilr02.bit._EIL4 +#define EPILR02_EIL5 _epilr02.bit._EIL5 +#define EPILR02_EIL6 _epilr02.bit._EIL6 +#define EPILR02_EIL7 _epilr02.bit._EIL7 +__IO_EXTENDED EPILR03STR _epilr03; +#define EPILR03 _epilr03.byte +#define EPILR03_EIL0 _epilr03.bit._EIL0 +#define EPILR03_EIL1 _epilr03.bit._EIL1 +#define EPILR03_EIL2 _epilr03.bit._EIL2 +#define EPILR03_EIL3 _epilr03.bit._EIL3 +#define EPILR03_EIL4 _epilr03.bit._EIL4 +#define EPILR03_EIL5 _epilr03.bit._EIL5 +#define EPILR03_EIL6 _epilr03.bit._EIL6 +#define EPILR03_EIL7 _epilr03.bit._EIL7 +__IO_EXTENDED EPILR04STR _epilr04; +#define EPILR04 _epilr04.byte +#define EPILR04_EIL0 _epilr04.bit._EIL0 +#define EPILR04_EIL1 _epilr04.bit._EIL1 +#define EPILR04_EIL2 _epilr04.bit._EIL2 +#define EPILR04_EIL3 _epilr04.bit._EIL3 +#define EPILR04_EIL4 _epilr04.bit._EIL4 +#define EPILR04_EIL5 _epilr04.bit._EIL5 +#define EPILR04_EIL6 _epilr04.bit._EIL6 +#define EPILR04_EIL7 _epilr04.bit._EIL7 +__IO_EXTENDED EPILR05STR _epilr05; +#define EPILR05 _epilr05.byte +#define EPILR05_EIL0 _epilr05.bit._EIL0 +#define EPILR05_EIL1 _epilr05.bit._EIL1 +#define EPILR05_EIL2 _epilr05.bit._EIL2 +#define EPILR05_EIL3 _epilr05.bit._EIL3 +#define EPILR05_EIL4 _epilr05.bit._EIL4 +#define EPILR05_EIL5 _epilr05.bit._EIL5 +#define EPILR05_EIL6 _epilr05.bit._EIL6 +#define EPILR05_EIL7 _epilr05.bit._EIL7 +__IO_EXTENDED EPILR06STR _epilr06; +#define EPILR06 _epilr06.byte +#define EPILR06_EIL0 _epilr06.bit._EIL0 +#define EPILR06_EIL1 _epilr06.bit._EIL1 +#define EPILR06_EIL2 _epilr06.bit._EIL2 +#define EPILR06_EIL3 _epilr06.bit._EIL3 +#define EPILR06_EIL4 _epilr06.bit._EIL4 +#define EPILR06_EIL5 _epilr06.bit._EIL5 +#define EPILR06_EIL6 _epilr06.bit._EIL6 +#define EPILR06_EIL7 _epilr06.bit._EIL7 +__IO_EXTENDED EPILR07STR _epilr07; +#define EPILR07 _epilr07.byte +#define EPILR07_EIL0 _epilr07.bit._EIL0 +#define EPILR07_EIL1 _epilr07.bit._EIL1 +#define EPILR07_EIL2 _epilr07.bit._EIL2 +#define EPILR07_EIL3 _epilr07.bit._EIL3 +#define EPILR07_EIL4 _epilr07.bit._EIL4 +#define EPILR07_EIL5 _epilr07.bit._EIL5 +#define EPILR07_EIL6 _epilr07.bit._EIL6 +#define EPILR07_EIL7 _epilr07.bit._EIL7 +__IO_EXTENDED EPILR08STR _epilr08; +#define EPILR08 _epilr08.byte +#define EPILR08_EIL0 _epilr08.bit._EIL0 +#define EPILR08_EIL1 _epilr08.bit._EIL1 +#define EPILR08_EIL2 _epilr08.bit._EIL2 +#define EPILR08_EIL3 _epilr08.bit._EIL3 +#define EPILR08_EIL4 _epilr08.bit._EIL4 +#define EPILR08_EIL5 _epilr08.bit._EIL5 +#define EPILR08_EIL6 _epilr08.bit._EIL6 +#define EPILR08_EIL7 _epilr08.bit._EIL7 +__IO_EXTENDED EPILR09STR _epilr09; +#define EPILR09 _epilr09.byte +#define EPILR09_EIL0 _epilr09.bit._EIL0 +#define EPILR09_EIL1 _epilr09.bit._EIL1 +#define EPILR09_EIL2 _epilr09.bit._EIL2 +#define EPILR09_EIL3 _epilr09.bit._EIL3 +#define EPILR09_EIL4 _epilr09.bit._EIL4 +#define EPILR09_EIL5 _epilr09.bit._EIL5 +#define EPILR09_EIL6 _epilr09.bit._EIL6 +#define EPILR09_EIL7 _epilr09.bit._EIL7 +__IO_EXTENDED EPILR10STR _epilr10; +#define EPILR10 _epilr10.byte +#define EPILR10_EIL0 _epilr10.bit._EIL0 +#define EPILR10_EIL1 _epilr10.bit._EIL1 +__IO_EXTENDED PODR00STR _podr00; +#define PODR00 _podr00.byte +#define PODR00_OD0 _podr00.bit._OD0 +#define PODR00_OD1 _podr00.bit._OD1 +#define PODR00_OD2 _podr00.bit._OD2 +#define PODR00_OD3 _podr00.bit._OD3 +#define PODR00_OD4 _podr00.bit._OD4 +#define PODR00_OD5 _podr00.bit._OD5 +#define PODR00_OD6 _podr00.bit._OD6 +#define PODR00_OD7 _podr00.bit._OD7 +__IO_EXTENDED PODR01STR _podr01; +#define PODR01 _podr01.byte +#define PODR01_OD0 _podr01.bit._OD0 +#define PODR01_OD1 _podr01.bit._OD1 +#define PODR01_OD2 _podr01.bit._OD2 +#define PODR01_OD3 _podr01.bit._OD3 +#define PODR01_OD4 _podr01.bit._OD4 +#define PODR01_OD5 _podr01.bit._OD5 +#define PODR01_OD6 _podr01.bit._OD6 +#define PODR01_OD7 _podr01.bit._OD7 +__IO_EXTENDED PODR02STR _podr02; +#define PODR02 _podr02.byte +#define PODR02_OD0 _podr02.bit._OD0 +#define PODR02_OD1 _podr02.bit._OD1 +#define PODR02_OD2 _podr02.bit._OD2 +#define PODR02_OD3 _podr02.bit._OD3 +#define PODR02_OD4 _podr02.bit._OD4 +#define PODR02_OD5 _podr02.bit._OD5 +#define PODR02_OD6 _podr02.bit._OD6 +#define PODR02_OD7 _podr02.bit._OD7 +__IO_EXTENDED PODR03STR _podr03; +#define PODR03 _podr03.byte +#define PODR03_OD0 _podr03.bit._OD0 +#define PODR03_OD1 _podr03.bit._OD1 +#define PODR03_OD2 _podr03.bit._OD2 +#define PODR03_OD3 _podr03.bit._OD3 +#define PODR03_OD4 _podr03.bit._OD4 +#define PODR03_OD5 _podr03.bit._OD5 +#define PODR03_OD6 _podr03.bit._OD6 +#define PODR03_OD7 _podr03.bit._OD7 +__IO_EXTENDED PODR04STR _podr04; +#define PODR04 _podr04.byte +#define PODR04_OD0 _podr04.bit._OD0 +#define PODR04_OD1 _podr04.bit._OD1 +#define PODR04_OD2 _podr04.bit._OD2 +#define PODR04_OD3 _podr04.bit._OD3 +#define PODR04_OD4 _podr04.bit._OD4 +#define PODR04_OD5 _podr04.bit._OD5 +#define PODR04_OD6 _podr04.bit._OD6 +#define PODR04_OD7 _podr04.bit._OD7 +__IO_EXTENDED PODR05STR _podr05; +#define PODR05 _podr05.byte +#define PODR05_OD0 _podr05.bit._OD0 +#define PODR05_OD1 _podr05.bit._OD1 +#define PODR05_OD2 _podr05.bit._OD2 +#define PODR05_OD3 _podr05.bit._OD3 +#define PODR05_OD4 _podr05.bit._OD4 +#define PODR05_OD5 _podr05.bit._OD5 +#define PODR05_OD6 _podr05.bit._OD6 +#define PODR05_OD7 _podr05.bit._OD7 +__IO_EXTENDED PODR06STR _podr06; +#define PODR06 _podr06.byte +#define PODR06_OD0 _podr06.bit._OD0 +#define PODR06_OD1 _podr06.bit._OD1 +#define PODR06_OD2 _podr06.bit._OD2 +#define PODR06_OD3 _podr06.bit._OD3 +#define PODR06_OD4 _podr06.bit._OD4 +#define PODR06_OD5 _podr06.bit._OD5 +#define PODR06_OD6 _podr06.bit._OD6 +#define PODR06_OD7 _podr06.bit._OD7 +__IO_EXTENDED PODR07STR _podr07; +#define PODR07 _podr07.byte +#define PODR07_OD0 _podr07.bit._OD0 +#define PODR07_OD1 _podr07.bit._OD1 +#define PODR07_OD2 _podr07.bit._OD2 +#define PODR07_OD3 _podr07.bit._OD3 +#define PODR07_OD4 _podr07.bit._OD4 +#define PODR07_OD5 _podr07.bit._OD5 +#define PODR07_OD6 _podr07.bit._OD6 +#define PODR07_OD7 _podr07.bit._OD7 +__IO_EXTENDED PODR08STR _podr08; +#define PODR08 _podr08.byte +#define PODR08_OD0 _podr08.bit._OD0 +#define PODR08_OD1 _podr08.bit._OD1 +#define PODR08_OD2 _podr08.bit._OD2 +#define PODR08_OD3 _podr08.bit._OD3 +#define PODR08_OD4 _podr08.bit._OD4 +#define PODR08_OD5 _podr08.bit._OD5 +#define PODR08_OD6 _podr08.bit._OD6 +#define PODR08_OD7 _podr08.bit._OD7 +__IO_EXTENDED PODR09STR _podr09; +#define PODR09 _podr09.byte +#define PODR09_OD0 _podr09.bit._OD0 +#define PODR09_OD1 _podr09.bit._OD1 +#define PODR09_OD2 _podr09.bit._OD2 +#define PODR09_OD3 _podr09.bit._OD3 +#define PODR09_OD4 _podr09.bit._OD4 +#define PODR09_OD5 _podr09.bit._OD5 +#define PODR09_OD6 _podr09.bit._OD6 +#define PODR09_OD7 _podr09.bit._OD7 +__IO_EXTENDED PODR10STR _podr10; +#define PODR10 _podr10.byte +#define PODR10_OD0 _podr10.bit._OD0 +#define PODR10_OD1 _podr10.bit._OD1 +__IO_EXTENDED PHDR08STR _phdr08; +#define PHDR08 _phdr08.byte +#define PHDR08_HD0 _phdr08.bit._HD0 +#define PHDR08_HD1 _phdr08.bit._HD1 +#define PHDR08_HD2 _phdr08.bit._HD2 +#define PHDR08_HD3 _phdr08.bit._HD3 +#define PHDR08_HD4 _phdr08.bit._HD4 +#define PHDR08_HD5 _phdr08.bit._HD5 +#define PHDR08_HD6 _phdr08.bit._HD6 +#define PHDR08_HD7 _phdr08.bit._HD7 +__IO_EXTENDED PHDR09STR _phdr09; +#define PHDR09 _phdr09.byte +#define PHDR09_HD0 _phdr09.bit._HD0 +#define PHDR09_HD1 _phdr09.bit._HD1 +#define PHDR09_HD2 _phdr09.bit._HD2 +#define PHDR09_HD3 _phdr09.bit._HD3 +#define PHDR09_HD4 _phdr09.bit._HD4 +#define PHDR09_HD5 _phdr09.bit._HD5 +#define PHDR09_HD6 _phdr09.bit._HD6 +#define PHDR09_HD7 _phdr09.bit._HD7 +__IO_EXTENDED PHDR10STR _phdr10; +#define PHDR10 _phdr10.byte +#define PHDR10_HD0 _phdr10.bit._HD0 +#define PHDR10_HD1 _phdr10.bit._HD1 +#define PHDR10_HD2 _phdr10.bit._HD2 +#define PHDR10_HD3 _phdr10.bit._HD3 +#define PHDR10_HD4 _phdr10.bit._HD4 +#define PHDR10_HD5 _phdr10.bit._HD5 +#define PHDR10_HD6 _phdr10.bit._HD6 +#define PHDR10_HD7 _phdr10.bit._HD7 +__IO_EXTENDED PUCR00STR _pucr00; +#define PUCR00 _pucr00.byte +#define PUCR00_PU0 _pucr00.bit._PU0 +#define PUCR00_PU1 _pucr00.bit._PU1 +#define PUCR00_PU2 _pucr00.bit._PU2 +#define PUCR00_PU3 _pucr00.bit._PU3 +#define PUCR00_PU4 _pucr00.bit._PU4 +#define PUCR00_PU5 _pucr00.bit._PU5 +#define PUCR00_PU6 _pucr00.bit._PU6 +#define PUCR00_PU7 _pucr00.bit._PU7 +__IO_EXTENDED PUCR01STR _pucr01; +#define PUCR01 _pucr01.byte +#define PUCR01_PU0 _pucr01.bit._PU0 +#define PUCR01_PU1 _pucr01.bit._PU1 +#define PUCR01_PU2 _pucr01.bit._PU2 +#define PUCR01_PU3 _pucr01.bit._PU3 +#define PUCR01_PU4 _pucr01.bit._PU4 +#define PUCR01_PU5 _pucr01.bit._PU5 +#define PUCR01_PU6 _pucr01.bit._PU6 +#define PUCR01_PU7 _pucr01.bit._PU7 +__IO_EXTENDED PUCR02STR _pucr02; +#define PUCR02 _pucr02.byte +#define PUCR02_PU0 _pucr02.bit._PU0 +#define PUCR02_PU1 _pucr02.bit._PU1 +#define PUCR02_PU2 _pucr02.bit._PU2 +#define PUCR02_PU3 _pucr02.bit._PU3 +#define PUCR02_PU4 _pucr02.bit._PU4 +#define PUCR02_PU5 _pucr02.bit._PU5 +#define PUCR02_PU6 _pucr02.bit._PU6 +#define PUCR02_PU7 _pucr02.bit._PU7 +__IO_EXTENDED PUCR03STR _pucr03; +#define PUCR03 _pucr03.byte +#define PUCR03_PU0 _pucr03.bit._PU0 +#define PUCR03_PU1 _pucr03.bit._PU1 +#define PUCR03_PU2 _pucr03.bit._PU2 +#define PUCR03_PU3 _pucr03.bit._PU3 +#define PUCR03_PU4 _pucr03.bit._PU4 +#define PUCR03_PU5 _pucr03.bit._PU5 +#define PUCR03_PU6 _pucr03.bit._PU6 +#define PUCR03_PU7 _pucr03.bit._PU7 +__IO_EXTENDED PUCR04STR _pucr04; +#define PUCR04 _pucr04.byte +#define PUCR04_PU0 _pucr04.bit._PU0 +#define PUCR04_PU1 _pucr04.bit._PU1 +#define PUCR04_PU2 _pucr04.bit._PU2 +#define PUCR04_PU3 _pucr04.bit._PU3 +#define PUCR04_PU4 _pucr04.bit._PU4 +#define PUCR04_PU5 _pucr04.bit._PU5 +#define PUCR04_PU6 _pucr04.bit._PU6 +#define PUCR04_PU7 _pucr04.bit._PU7 +__IO_EXTENDED PUCR05STR _pucr05; +#define PUCR05 _pucr05.byte +#define PUCR05_PU0 _pucr05.bit._PU0 +#define PUCR05_PU1 _pucr05.bit._PU1 +#define PUCR05_PU2 _pucr05.bit._PU2 +#define PUCR05_PU3 _pucr05.bit._PU3 +#define PUCR05_PU4 _pucr05.bit._PU4 +#define PUCR05_PU5 _pucr05.bit._PU5 +#define PUCR05_PU6 _pucr05.bit._PU6 +#define PUCR05_PU7 _pucr05.bit._PU7 +__IO_EXTENDED PUCR06STR _pucr06; +#define PUCR06 _pucr06.byte +#define PUCR06_PU0 _pucr06.bit._PU0 +#define PUCR06_PU1 _pucr06.bit._PU1 +#define PUCR06_PU2 _pucr06.bit._PU2 +#define PUCR06_PU3 _pucr06.bit._PU3 +#define PUCR06_PU4 _pucr06.bit._PU4 +#define PUCR06_PU5 _pucr06.bit._PU5 +#define PUCR06_PU6 _pucr06.bit._PU6 +#define PUCR06_PU7 _pucr06.bit._PU7 +__IO_EXTENDED PUCR07STR _pucr07; +#define PUCR07 _pucr07.byte +#define PUCR07_PU0 _pucr07.bit._PU0 +#define PUCR07_PU1 _pucr07.bit._PU1 +#define PUCR07_PU2 _pucr07.bit._PU2 +#define PUCR07_PU3 _pucr07.bit._PU3 +#define PUCR07_PU4 _pucr07.bit._PU4 +#define PUCR07_PU5 _pucr07.bit._PU5 +#define PUCR07_PU6 _pucr07.bit._PU6 +#define PUCR07_PU7 _pucr07.bit._PU7 +__IO_EXTENDED PUCR08STR _pucr08; +#define PUCR08 _pucr08.byte +#define PUCR08_PU0 _pucr08.bit._PU0 +#define PUCR08_PU1 _pucr08.bit._PU1 +#define PUCR08_PU2 _pucr08.bit._PU2 +#define PUCR08_PU3 _pucr08.bit._PU3 +#define PUCR08_PU4 _pucr08.bit._PU4 +#define PUCR08_PU5 _pucr08.bit._PU5 +#define PUCR08_PU6 _pucr08.bit._PU6 +#define PUCR08_PU7 _pucr08.bit._PU7 +__IO_EXTENDED PUCR09STR _pucr09; +#define PUCR09 _pucr09.byte +#define PUCR09_PU0 _pucr09.bit._PU0 +#define PUCR09_PU1 _pucr09.bit._PU1 +#define PUCR09_PU2 _pucr09.bit._PU2 +#define PUCR09_PU3 _pucr09.bit._PU3 +#define PUCR09_PU4 _pucr09.bit._PU4 +#define PUCR09_PU5 _pucr09.bit._PU5 +#define PUCR09_PU6 _pucr09.bit._PU6 +#define PUCR09_PU7 _pucr09.bit._PU7 +__IO_EXTENDED PUCR10STR _pucr10; +#define PUCR10 _pucr10.byte +#define PUCR10_PU0 _pucr10.bit._PU0 +#define PUCR10_PU1 _pucr10.bit._PU1 +__IO_EXTENDED EPSR00STR _epsr00; +#define EPSR00 _epsr00.byte +#define EPSR00_PS0 _epsr00.bit._PS0 +#define EPSR00_PS1 _epsr00.bit._PS1 +#define EPSR00_PS2 _epsr00.bit._PS2 +#define EPSR00_PS3 _epsr00.bit._PS3 +#define EPSR00_PS4 _epsr00.bit._PS4 +#define EPSR00_PS5 _epsr00.bit._PS5 +#define EPSR00_PS6 _epsr00.bit._PS6 +#define EPSR00_PS7 _epsr00.bit._PS7 +__IO_EXTENDED EPSR01STR _epsr01; +#define EPSR01 _epsr01.byte +#define EPSR01_PS0 _epsr01.bit._PS0 +#define EPSR01_PS1 _epsr01.bit._PS1 +#define EPSR01_PS2 _epsr01.bit._PS2 +#define EPSR01_PS3 _epsr01.bit._PS3 +#define EPSR01_PS4 _epsr01.bit._PS4 +#define EPSR01_PS5 _epsr01.bit._PS5 +#define EPSR01_PS6 _epsr01.bit._PS6 +#define EPSR01_PS7 _epsr01.bit._PS7 +__IO_EXTENDED EPSR02STR _epsr02; +#define EPSR02 _epsr02.byte +#define EPSR02_PS0 _epsr02.bit._PS0 +#define EPSR02_PS1 _epsr02.bit._PS1 +#define EPSR02_PS2 _epsr02.bit._PS2 +#define EPSR02_PS3 _epsr02.bit._PS3 +#define EPSR02_PS4 _epsr02.bit._PS4 +#define EPSR02_PS5 _epsr02.bit._PS5 +#define EPSR02_PS6 _epsr02.bit._PS6 +#define EPSR02_PS7 _epsr02.bit._PS7 +__IO_EXTENDED EPSR03STR _epsr03; +#define EPSR03 _epsr03.byte +#define EPSR03_PS0 _epsr03.bit._PS0 +#define EPSR03_PS1 _epsr03.bit._PS1 +#define EPSR03_PS2 _epsr03.bit._PS2 +#define EPSR03_PS3 _epsr03.bit._PS3 +#define EPSR03_PS4 _epsr03.bit._PS4 +#define EPSR03_PS5 _epsr03.bit._PS5 +#define EPSR03_PS6 _epsr03.bit._PS6 +#define EPSR03_PS7 _epsr03.bit._PS7 +__IO_EXTENDED EPSR04STR _epsr04; +#define EPSR04 _epsr04.byte +#define EPSR04_PS0 _epsr04.bit._PS0 +#define EPSR04_PS1 _epsr04.bit._PS1 +#define EPSR04_PS2 _epsr04.bit._PS2 +#define EPSR04_PS3 _epsr04.bit._PS3 +#define EPSR04_PS4 _epsr04.bit._PS4 +#define EPSR04_PS5 _epsr04.bit._PS5 +#define EPSR04_PS6 _epsr04.bit._PS6 +#define EPSR04_PS7 _epsr04.bit._PS7 +__IO_EXTENDED EPSR05STR _epsr05; +#define EPSR05 _epsr05.byte +#define EPSR05_PS0 _epsr05.bit._PS0 +#define EPSR05_PS1 _epsr05.bit._PS1 +#define EPSR05_PS2 _epsr05.bit._PS2 +#define EPSR05_PS3 _epsr05.bit._PS3 +#define EPSR05_PS4 _epsr05.bit._PS4 +#define EPSR05_PS5 _epsr05.bit._PS5 +#define EPSR05_PS6 _epsr05.bit._PS6 +#define EPSR05_PS7 _epsr05.bit._PS7 +__IO_EXTENDED EPSR06STR _epsr06; +#define EPSR06 _epsr06.byte +#define EPSR06_PS0 _epsr06.bit._PS0 +#define EPSR06_PS1 _epsr06.bit._PS1 +#define EPSR06_PS2 _epsr06.bit._PS2 +#define EPSR06_PS3 _epsr06.bit._PS3 +#define EPSR06_PS4 _epsr06.bit._PS4 +#define EPSR06_PS5 _epsr06.bit._PS5 +#define EPSR06_PS6 _epsr06.bit._PS6 +#define EPSR06_PS7 _epsr06.bit._PS7 +__IO_EXTENDED EPSR07STR _epsr07; +#define EPSR07 _epsr07.byte +#define EPSR07_PS0 _epsr07.bit._PS0 +#define EPSR07_PS1 _epsr07.bit._PS1 +#define EPSR07_PS2 _epsr07.bit._PS2 +#define EPSR07_PS3 _epsr07.bit._PS3 +#define EPSR07_PS4 _epsr07.bit._PS4 +#define EPSR07_PS5 _epsr07.bit._PS5 +#define EPSR07_PS6 _epsr07.bit._PS6 +#define EPSR07_PS7 _epsr07.bit._PS7 +__IO_EXTENDED EPSR08STR _epsr08; +#define EPSR08 _epsr08.byte +#define EPSR08_PS0 _epsr08.bit._PS0 +#define EPSR08_PS1 _epsr08.bit._PS1 +#define EPSR08_PS2 _epsr08.bit._PS2 +#define EPSR08_PS3 _epsr08.bit._PS3 +#define EPSR08_PS4 _epsr08.bit._PS4 +#define EPSR08_PS5 _epsr08.bit._PS5 +#define EPSR08_PS6 _epsr08.bit._PS6 +#define EPSR08_PS7 _epsr08.bit._PS7 +__IO_EXTENDED EPSR09STR _epsr09; +#define EPSR09 _epsr09.byte +#define EPSR09_PS0 _epsr09.bit._PS0 +#define EPSR09_PS1 _epsr09.bit._PS1 +#define EPSR09_PS2 _epsr09.bit._PS2 +#define EPSR09_PS3 _epsr09.bit._PS3 +#define EPSR09_PS4 _epsr09.bit._PS4 +#define EPSR09_PS5 _epsr09.bit._PS5 +#define EPSR09_PS6 _epsr09.bit._PS6 +#define EPSR09_PS7 _epsr09.bit._PS7 +__IO_EXTENDED EPSR10STR _epsr10; +#define EPSR10 _epsr10.byte +#define EPSR10_PS0 _epsr10.bit._PS0 +#define EPSR10_PS1 _epsr10.bit._PS1 +__IO_EXTENDED ADER0STR _ader0; +#define ADER0 _ader0.byte +#define ADER0_ADE0 _ader0.bit._ADE0 +#define ADER0_ADE1 _ader0.bit._ADE1 +#define ADER0_ADE2 _ader0.bit._ADE2 +#define ADER0_ADE3 _ader0.bit._ADE3 +#define ADER0_ADE4 _ader0.bit._ADE4 +#define ADER0_ADE5 _ader0.bit._ADE5 +#define ADER0_ADE6 _ader0.bit._ADE6 +#define ADER0_ADE7 _ader0.bit._ADE7 +__IO_EXTENDED ADER1STR _ader1; +#define ADER1 _ader1.byte +#define ADER1_ADE8 _ader1.bit._ADE8 +#define ADER1_ADE9 _ader1.bit._ADE9 +#define ADER1_ADE10 _ader1.bit._ADE10 +#define ADER1_ADE11 _ader1.bit._ADE11 +#define ADER1_ADE12 _ader1.bit._ADE12 +#define ADER1_ADE13 _ader1.bit._ADE13 +#define ADER1_ADE14 _ader1.bit._ADE14 +#define ADER1_ADE15 _ader1.bit._ADE15 +__IO_EXTENDED ADER2STR _ader2; +#define ADER2 _ader2.byte +#define ADER2_ADE16 _ader2.bit._ADE16 +#define ADER2_ADE17 _ader2.bit._ADE17 +#define ADER2_ADE18 _ader2.bit._ADE18 +#define ADER2_ADE19 _ader2.bit._ADE19 +#define ADER2_ADE20 _ader2.bit._ADE20 +#define ADER2_ADE21 _ader2.bit._ADE21 +#define ADER2_ADE22 _ader2.bit._ADE22 +#define ADER2_ADE23 _ader2.bit._ADE23 +__IO_EXTENDED PRRR0STR _prrr0; +#define PRRR0 _prrr0.byte +#define PRRR0_INT0_R _prrr0.bit._INT0_R +#define PRRR0_INT1_R _prrr0.bit._INT1_R +#define PRRR0_INT2_R _prrr0.bit._INT2_R +#define PRRR0_INT3_R _prrr0.bit._INT3_R +#define PRRR0_INT4_R _prrr0.bit._INT4_R +#define PRRR0_INT5_R _prrr0.bit._INT5_R +#define PRRR0_INT6_R _prrr0.bit._INT6_R +#define PRRR0_INT7_R _prrr0.bit._INT7_R +__IO_EXTENDED PRRR1STR _prrr1; +#define PRRR1 _prrr1.byte +#define PRRR1_INT8_R _prrr1.bit._INT8_R +#define PRRR1_INT9_R _prrr1.bit._INT9_R +#define PRRR1_INT10_R _prrr1.bit._INT10_R +#define PRRR1_INT11_R _prrr1.bit._INT11_R +#define PRRR1_INT12_R _prrr1.bit._INT12_R +#define PRRR1_INT13_R _prrr1.bit._INT13_R +#define PRRR1_INT14_R _prrr1.bit._INT14_R +#define PRRR1_INT15_R _prrr1.bit._INT15_R +__IO_EXTENDED PRRR2STR _prrr2; +#define PRRR2 _prrr2.byte +#define PRRR2_PPG0_R _prrr2.bit._PPG0_R +#define PRRR2_PPG1_R _prrr2.bit._PPG1_R +#define PRRR2_PPG2_R _prrr2.bit._PPG2_R +#define PRRR2_PPG3_R _prrr2.bit._PPG3_R +#define PRRR2_PPG4_R _prrr2.bit._PPG4_R +#define PRRR2_PPG5_R _prrr2.bit._PPG5_R +#define PRRR2_PPG6_R _prrr2.bit._PPG6_R +#define PRRR2_PPG7_R _prrr2.bit._PPG7_R +__IO_EXTENDED PRRR3STR _prrr3; +#define PRRR3 _prrr3.byte +#define PRRR3_TIN0_R _prrr3.bit._TIN0_R +#define PRRR3_TOT0_R _prrr3.bit._TOT0_R +#define PRRR3_TIN1_R _prrr3.bit._TIN1_R +#define PRRR3_TOT1_R _prrr3.bit._TOT1_R +#define PRRR3_TIN2_R _prrr3.bit._TIN2_R +#define PRRR3_TOT2_R _prrr3.bit._TOT2_R +#define PRRR3_TIN3_R _prrr3.bit._TIN3_R +#define PRRR3_TOT3_R _prrr3.bit._TOT3_R +__IO_EXTENDED PRRR4STR _prrr4; +#define PRRR4 _prrr4.byte +#define PRRR4_IN0_R _prrr4.bit._IN0_R +#define PRRR4_IN1_R _prrr4.bit._IN1_R +#define PRRR4_IN2_R _prrr4.bit._IN2_R +#define PRRR4_IN3_R _prrr4.bit._IN3_R +#define PRRR4_IN4_R _prrr4.bit._IN4_R +#define PRRR4_IN5_R _prrr4.bit._IN5_R +#define PRRR4_IN6_R _prrr4.bit._IN6_R +#define PRRR4_IN7_R _prrr4.bit._IN7_R +__IO_EXTENDED PRRR5STR _prrr5; +#define PRRR5 _prrr5.byte +#define PRRR5_OUT0_R _prrr5.bit._OUT0_R +#define PRRR5_OUT1_R _prrr5.bit._OUT1_R +#define PRRR5_OUT2_R _prrr5.bit._OUT2_R +#define PRRR5_OUT3_R _prrr5.bit._OUT3_R +#define PRRR5_OUT6_R _prrr5.bit._OUT6_R +#define PRRR5_OUT7_R _prrr5.bit._OUT7_R +__IO_EXTENDED PRRR6STR _prrr6; +#define PRRR6 _prrr6.byte +#define PRRR6_SGO0_R _prrr6.bit._SGO0_R +#define PRRR6_SGA0_R _prrr6.bit._SGA0_R +#define PRRR6_FRCK0_R _prrr6.bit._FRCK0_R +#define PRRR6_SIN2_R _prrr6.bit._SIN2_R +#define PRRR6_SOT2_R _prrr6.bit._SOT2_R +#define PRRR6_SCK2_R _prrr6.bit._SCK2_R +#define PRRR6_CKOT1_R _prrr6.bit._CKOT1_R +#define PRRR6_CKOTX1_R _prrr6.bit._CKOTX1_R +__IO_EXTENDED PRRR7STR _prrr7; +#define PRRR7 _prrr7.byte +#define PRRR7_ADTG_R _prrr7.bit._ADTG_R +#define PRRR7_NMI_R _prrr7.bit._NMI_R +#define PRRR7_CS3_R _prrr7.bit._CS3_R +#define PRRR7_INT3_R1 _prrr7.bit._INT3_R1 +#define PRRR7_INT4_R1 _prrr7.bit._INT4_R1 +#define PRRR7_INT5_R1 _prrr7.bit._INT5_R1 +#define PRRR7_RX2_R _prrr7.bit._RX2_R +#define PRRR7_TX2_R _prrr7.bit._TX2_R +__IO_EXTENDED PRRR8STR _prrr8; +#define PRRR8 _prrr8.byte +#define PRRR8_SIN7_R _prrr8.bit._SIN7_R +#define PRRR8_SOT7_R _prrr8.bit._SOT7_R +#define PRRR8_SCK7_R _prrr8.bit._SCK7_R +#define PRRR8_SIN8_R _prrr8.bit._SIN8_R +#define PRRR8_SOT8_R _prrr8.bit._SOT8_R +#define PRRR8_SCK8_R _prrr8.bit._SCK8_R +#define PRRR8_SIN9_R _prrr8.bit._SIN9_R +#define PRRR8_SOT9_R _prrr8.bit._SOT9_R +__IO_EXTENDED PRRR9STR _prrr9; +#define PRRR9 _prrr9.byte +#define PRRR9_SCK9_R _prrr9.bit._SCK9_R +#define PRRR9_SGO1_R _prrr9.bit._SGO1_R +#define PRRR9_SGA1_R _prrr9.bit._SGA1_R +#define PRRR9_FRCK2_R _prrr9.bit._FRCK2_R +#define PRRR9_OUT10_R _prrr9.bit._OUT10_R +#define PRRR9_CKOT0_R _prrr9.bit._CKOT0_R +__IO_EXTENDED WTBR0STR _wtbr0; +#define WTBR0 _wtbr0.word +#define WTBR0_D0 _wtbr0.bit._D0 +#define WTBR0_D1 _wtbr0.bit._D1 +#define WTBR0_D2 _wtbr0.bit._D2 +#define WTBR0_D3 _wtbr0.bit._D3 +#define WTBR0_D4 _wtbr0.bit._D4 +#define WTBR0_D5 _wtbr0.bit._D5 +#define WTBR0_D6 _wtbr0.bit._D6 +#define WTBR0_D7 _wtbr0.bit._D7 +#define WTBR0_D8 _wtbr0.bit._D8 +#define WTBR0_D9 _wtbr0.bit._D9 +#define WTBR0_D10 _wtbr0.bit._D10 +#define WTBR0_D11 _wtbr0.bit._D11 +#define WTBR0_D12 _wtbr0.bit._D12 +#define WTBR0_D13 _wtbr0.bit._D13 +#define WTBR0_D14 _wtbr0.bit._D14 +#define WTBR0_D15 _wtbr0.bit._D15 +#define WTBR0_D _wtbr0.bitc._D +__IO_EXTENDED WTBRL0STR _wtbrl0; +#define WTBRL0 _wtbrl0.byte +#define WTBRL0_D0 _wtbrl0.bit._D0 +#define WTBRL0_D1 _wtbrl0.bit._D1 +#define WTBRL0_D2 _wtbrl0.bit._D2 +#define WTBRL0_D3 _wtbrl0.bit._D3 +#define WTBRL0_D4 _wtbrl0.bit._D4 +#define WTBRL0_D5 _wtbrl0.bit._D5 +#define WTBRL0_D6 _wtbrl0.bit._D6 +#define WTBRL0_D7 _wtbrl0.bit._D7 +__IO_EXTENDED WTBRH0STR _wtbrh0; +#define WTBRH0 _wtbrh0.byte +#define WTBRH0_D8 _wtbrh0.bit._D8 +#define WTBRH0_D9 _wtbrh0.bit._D9 +#define WTBRH0_D10 _wtbrh0.bit._D10 +#define WTBRH0_D11 _wtbrh0.bit._D11 +#define WTBRH0_D12 _wtbrh0.bit._D12 +#define WTBRH0_D13 _wtbrh0.bit._D13 +#define WTBRH0_D14 _wtbrh0.bit._D14 +#define WTBRH0_D15 _wtbrh0.bit._D15 +__IO_EXTENDED WTBR1STR _wtbr1; +#define WTBR1 _wtbr1.byte +#define WTBR1_D16 _wtbr1.bit._D16 +#define WTBR1_D17 _wtbr1.bit._D17 +#define WTBR1_D18 _wtbr1.bit._D18 +#define WTBR1_D19 _wtbr1.bit._D19 +#define WTBR1_D20 _wtbr1.bit._D20 +#define WTBR1_D1 _wtbr1.bitc._D1 +__IO_EXTENDED WTSRSTR _wtsr; +#define WTSR _wtsr.byte +#define WTSR_S0 _wtsr.bit._S0 +#define WTSR_S1 _wtsr.bit._S1 +#define WTSR_S2 _wtsr.bit._S2 +#define WTSR_S3 _wtsr.bit._S3 +#define WTSR_S4 _wtsr.bit._S4 +#define WTSR_S5 _wtsr.bit._S5 +#define WTSR_S _wtsr.bitc._S +__IO_EXTENDED WTMRSTR _wtmr; +#define WTMR _wtmr.byte +#define WTMR_M0 _wtmr.bit._M0 +#define WTMR_M1 _wtmr.bit._M1 +#define WTMR_M2 _wtmr.bit._M2 +#define WTMR_M3 _wtmr.bit._M3 +#define WTMR_M4 _wtmr.bit._M4 +#define WTMR_M5 _wtmr.bit._M5 +#define WTMR_M _wtmr.bitc._M +__IO_EXTENDED WTHRSTR _wthr; +#define WTHR _wthr.byte +#define WTHR_H0 _wthr.bit._H0 +#define WTHR_H1 _wthr.bit._H1 +#define WTHR_H2 _wthr.bit._H2 +#define WTHR_H3 _wthr.bit._H3 +#define WTHR_H4 _wthr.bit._H4 +#define WTHR_H _wthr.bitc._H +__IO_EXTENDED WTCERSTR _wtcer; +#define WTCER _wtcer.byte +#define WTCER_INT4 _wtcer.bit._INT4 +#define WTCER_INTE4 _wtcer.bit._INTE4 +__IO_EXTENDED WTCKSRSTR _wtcksr; +#define WTCKSR _wtcksr.byte +#define WTCKSR_CKSEL0 _wtcksr.bit._CKSEL0 +#define WTCKSR_CKSEL1 _wtcksr.bit._CKSEL1 +#define WTCKSR_CKSEL _wtcksr.bitc._CKSEL +__IO_EXTENDED WTCRSTR _wtcr; +#define WTCR _wtcr.word +#define WTCR_ST _wtcr.bit._ST +#define WTCR_OE _wtcr.bit._OE +#define WTCR_UPDT _wtcr.bit._UPDT +#define WTCR_RUN _wtcr.bit._RUN +#define WTCR_INT0 _wtcr.bit._INT0 +#define WTCR_INTE0 _wtcr.bit._INTE0 +#define WTCR_INT1 _wtcr.bit._INT1 +#define WTCR_INTE1 _wtcr.bit._INTE1 +#define WTCR_INT2 _wtcr.bit._INT2 +#define WTCR_INTE2 _wtcr.bit._INTE2 +#define WTCR_INT3 _wtcr.bit._INT3 +#define WTCR_INTE3 _wtcr.bit._INTE3 +__IO_EXTENDED WTCRLSTR _wtcrl; +#define WTCRL _wtcrl.byte +#define WTCRL_ST _wtcrl.bit._ST +#define WTCRL_OE _wtcrl.bit._OE +#define WTCRL_UPDT _wtcrl.bit._UPDT +#define WTCRL_RUN _wtcrl.bit._RUN +__IO_EXTENDED WTCRHSTR _wtcrh; +#define WTCRH _wtcrh.byte +#define WTCRH_INT0 _wtcrh.bit._INT0 +#define WTCRH_INTE0 _wtcrh.bit._INTE0 +#define WTCRH_INT1 _wtcrh.bit._INT1 +#define WTCRH_INTE1 _wtcrh.bit._INTE1 +#define WTCRH_INT2 _wtcrh.bit._INT2 +#define WTCRH_INTE2 _wtcrh.bit._INTE2 +#define WTCRH_INT3 _wtcrh.bit._INT3 +#define WTCRH_INTE3 _wtcrh.bit._INTE3 +__IO_EXTENDED CUCRSTR _cucr; +#define CUCR _cucr.byte +#define CUCR_INTEN _cucr.bit._INTEN +#define CUCR_INT _cucr.bit._INT +#define CUCR_CKSEL _cucr.bit._CKSEL +#define CUCR_STRT _cucr.bit._STRT +#define CUCR_RESV _cucr.bit._RESV +__IO_EXTENDED CUTDSTR _cutd; +#define CUTD _cutd.word +#define CUTD_TDD0 _cutd.bit._TDD0 +#define CUTD_TDD1 _cutd.bit._TDD1 +#define CUTD_TDD2 _cutd.bit._TDD2 +#define CUTD_TDD3 _cutd.bit._TDD3 +#define CUTD_TDD4 _cutd.bit._TDD4 +#define CUTD_TDD5 _cutd.bit._TDD5 +#define CUTD_TDD6 _cutd.bit._TDD6 +#define CUTD_TDD7 _cutd.bit._TDD7 +#define CUTD_TDD8 _cutd.bit._TDD8 +#define CUTD_TDD9 _cutd.bit._TDD9 +#define CUTD_TDD10 _cutd.bit._TDD10 +#define CUTD_TDD11 _cutd.bit._TDD11 +#define CUTD_TDD12 _cutd.bit._TDD12 +#define CUTD_TDD13 _cutd.bit._TDD13 +#define CUTD_TDD14 _cutd.bit._TDD14 +#define CUTD_TDD15 _cutd.bit._TDD15 +#define CUTD_TDD _cutd.bitc._TDD +__IO_EXTENDED CUTDLSTR _cutdl; +#define CUTDL _cutdl.byte +#define CUTDL_TDD0 _cutdl.bit._TDD0 +#define CUTDL_TDD1 _cutdl.bit._TDD1 +#define CUTDL_TDD2 _cutdl.bit._TDD2 +#define CUTDL_TDD3 _cutdl.bit._TDD3 +#define CUTDL_TDD4 _cutdl.bit._TDD4 +#define CUTDL_TDD5 _cutdl.bit._TDD5 +#define CUTDL_TDD6 _cutdl.bit._TDD6 +#define CUTDL_TDD7 _cutdl.bit._TDD7 +__IO_EXTENDED CUTDHSTR _cutdh; +#define CUTDH _cutdh.byte +#define CUTDH_TDD8 _cutdh.bit._TDD8 +#define CUTDH_TDD9 _cutdh.bit._TDD9 +#define CUTDH_TDD10 _cutdh.bit._TDD10 +#define CUTDH_TDD11 _cutdh.bit._TDD11 +#define CUTDH_TDD12 _cutdh.bit._TDD12 +#define CUTDH_TDD13 _cutdh.bit._TDD13 +#define CUTDH_TDD14 _cutdh.bit._TDD14 +#define CUTDH_TDD15 _cutdh.bit._TDD15 +__IO_EXTENDED CUTRSTR _cutr; +#define CUTR _cutr.lword +#define CUTR_TDR0 _cutr.bit._TDR0 +#define CUTR_TDR1 _cutr.bit._TDR1 +#define CUTR_TDR2 _cutr.bit._TDR2 +#define CUTR_TDR3 _cutr.bit._TDR3 +#define CUTR_TDR4 _cutr.bit._TDR4 +#define CUTR_TDR5 _cutr.bit._TDR5 +#define CUTR_TDR6 _cutr.bit._TDR6 +#define CUTR_TDR7 _cutr.bit._TDR7 +#define CUTR_TDR8 _cutr.bit._TDR8 +#define CUTR_TDR9 _cutr.bit._TDR9 +#define CUTR_TDR10 _cutr.bit._TDR10 +#define CUTR_TDR11 _cutr.bit._TDR11 +#define CUTR_TDR12 _cutr.bit._TDR12 +#define CUTR_TDR13 _cutr.bit._TDR13 +#define CUTR_TDR14 _cutr.bit._TDR14 +#define CUTR_TDR15 _cutr.bit._TDR15 +#define CUTR_TDR16 _cutr.bit._TDR16 +#define CUTR_TDR17 _cutr.bit._TDR17 +#define CUTR_TDR18 _cutr.bit._TDR18 +#define CUTR_TDR19 _cutr.bit._TDR19 +#define CUTR_TDR20 _cutr.bit._TDR20 +#define CUTR_TDR21 _cutr.bit._TDR21 +#define CUTR_TDR22 _cutr.bit._TDR22 +#define CUTR_TDR23 _cutr.bit._TDR23 +__IO_EXTENDED CUTR2STR _cutr2; +#define CUTR2 _cutr2.word +#define CUTR2_TDR0 _cutr2.bit._TDR0 +#define CUTR2_TDR1 _cutr2.bit._TDR1 +#define CUTR2_TDR2 _cutr2.bit._TDR2 +#define CUTR2_TDR3 _cutr2.bit._TDR3 +#define CUTR2_TDR4 _cutr2.bit._TDR4 +#define CUTR2_TDR5 _cutr2.bit._TDR5 +#define CUTR2_TDR6 _cutr2.bit._TDR6 +#define CUTR2_TDR7 _cutr2.bit._TDR7 +#define CUTR2_TDR8 _cutr2.bit._TDR8 +#define CUTR2_TDR9 _cutr2.bit._TDR9 +#define CUTR2_TDR10 _cutr2.bit._TDR10 +#define CUTR2_TDR11 _cutr2.bit._TDR11 +#define CUTR2_TDR12 _cutr2.bit._TDR12 +#define CUTR2_TDR13 _cutr2.bit._TDR13 +#define CUTR2_TDR14 _cutr2.bit._TDR14 +#define CUTR2_TDR15 _cutr2.bit._TDR15 +__IO_EXTENDED CUTR2LSTR _cutr2l; +#define CUTR2L _cutr2l.byte +#define CUTR2L_TDR0 _cutr2l.bit._TDR0 +#define CUTR2L_TDR1 _cutr2l.bit._TDR1 +#define CUTR2L_TDR2 _cutr2l.bit._TDR2 +#define CUTR2L_TDR3 _cutr2l.bit._TDR3 +#define CUTR2L_TDR4 _cutr2l.bit._TDR4 +#define CUTR2L_TDR5 _cutr2l.bit._TDR5 +#define CUTR2L_TDR6 _cutr2l.bit._TDR6 +#define CUTR2L_TDR7 _cutr2l.bit._TDR7 +__IO_EXTENDED CUTR2HSTR _cutr2h; +#define CUTR2H _cutr2h.byte +#define CUTR2H_TDR8 _cutr2h.bit._TDR8 +#define CUTR2H_TDR9 _cutr2h.bit._TDR9 +#define CUTR2H_TDR10 _cutr2h.bit._TDR10 +#define CUTR2H_TDR11 _cutr2h.bit._TDR11 +#define CUTR2H_TDR12 _cutr2h.bit._TDR12 +#define CUTR2H_TDR13 _cutr2h.bit._TDR13 +#define CUTR2H_TDR14 _cutr2h.bit._TDR14 +#define CUTR2H_TDR15 _cutr2h.bit._TDR15 +__IO_EXTENDED CUTR1STR _cutr1; +#define CUTR1 _cutr1.word +#define CUTR1_TDR16 _cutr1.bit._TDR16 +#define CUTR1_TDR17 _cutr1.bit._TDR17 +#define CUTR1_TDR18 _cutr1.bit._TDR18 +#define CUTR1_TDR19 _cutr1.bit._TDR19 +#define CUTR1_TDR20 _cutr1.bit._TDR20 +#define CUTR1_TDR21 _cutr1.bit._TDR21 +#define CUTR1_TDR22 _cutr1.bit._TDR22 +#define CUTR1_TDR23 _cutr1.bit._TDR23 +__IO_EXTENDED CUTR1LSTR _cutr1l; +#define CUTR1L _cutr1l.byte +#define CUTR1L_TDR16 _cutr1l.bit._TDR16 +#define CUTR1L_TDR17 _cutr1l.bit._TDR17 +#define CUTR1L_TDR18 _cutr1l.bit._TDR18 +#define CUTR1L_TDR19 _cutr1l.bit._TDR19 +#define CUTR1L_TDR20 _cutr1l.bit._TDR20 +#define CUTR1L_TDR21 _cutr1l.bit._TDR21 +#define CUTR1L_TDR22 _cutr1l.bit._TDR22 +#define CUTR1L_TDR23 _cutr1l.bit._TDR23 +__IO_EXTENDED CUTR1HSTR _cutr1h; +#define CUTR1H _cutr1h.byte +__IO_EXTENDED TMISRSTR _tmisr; +#define TMISR _tmisr.byte +#define TMISR_TMIS0 _tmisr.bit._TMIS0 +#define TMISR_TMIS1 _tmisr.bit._TMIS1 +#define TMISR_TMIS2 _tmisr.bit._TMIS2 +#define TMISR_TMIS3 _tmisr.bit._TMIS3 +#define TMISR_TMIS4 _tmisr.bit._TMIS4 +#define TMISR_TMIS5 _tmisr.bit._TMIS5 +__IO_EXTENDED SMR7STR _smr7; +#define SMR7 _smr7.byte +#define SMR7_SOE _smr7.bit._SOE +#define SMR7_SCKE _smr7.bit._SCKE +#define SMR7_UPCL _smr7.bit._UPCL +#define SMR7_REST _smr7.bit._REST +#define SMR7_EXT _smr7.bit._EXT +#define SMR7_OTO _smr7.bit._OTO +#define SMR7_MD0 _smr7.bit._MD0 +#define SMR7_MD1 _smr7.bit._MD1 +#define SMR7_MD _smr7.bitc._MD +__IO_EXTENDED SCR7STR _scr7; +#define SCR7 _scr7.byte +#define SCR7_TXE _scr7.bit._TXE +#define SCR7_RXE _scr7.bit._RXE +#define SCR7_CRE _scr7.bit._CRE +#define SCR7_AD _scr7.bit._AD +#define SCR7_CL _scr7.bit._CL +#define SCR7_SBL _scr7.bit._SBL +#define SCR7_P _scr7.bit._P +#define SCR7_PEN _scr7.bit._PEN +__IO_EXTENDED IO_BYTE _tdr7; +#define TDR7 _tdr7 +__IO_EXTENDED IO_BYTE _rdr7; +#define RDR7 _rdr7 +__IO_EXTENDED SSR7STR _ssr7; +#define SSR7 _ssr7.byte +#define SSR7_TIE _ssr7.bit._TIE +#define SSR7_RIE _ssr7.bit._RIE +#define SSR7_BDS _ssr7.bit._BDS +#define SSR7_TDRE _ssr7.bit._TDRE +#define SSR7_RDRF _ssr7.bit._RDRF +#define SSR7_FRE _ssr7.bit._FRE +#define SSR7_ORE _ssr7.bit._ORE +#define SSR7_PE _ssr7.bit._PE +__IO_EXTENDED ECCR7STR _eccr7; +#define ECCR7 _eccr7.byte +#define ECCR7_TBI _eccr7.bit._TBI +#define ECCR7_RBI _eccr7.bit._RBI +#define ECCR7_BIE _eccr7.bit._BIE +#define ECCR7_SSM _eccr7.bit._SSM +#define ECCR7_SCDE _eccr7.bit._SCDE +#define ECCR7_MS _eccr7.bit._MS +#define ECCR7_LBR _eccr7.bit._LBR +#define ECCR7_INV _eccr7.bit._INV +__IO_EXTENDED ESCR7STR _escr7; +#define ESCR7 _escr7.byte +#define ESCR7_SCES _escr7.bit._SCES +#define ESCR7_CCO _escr7.bit._CCO +#define ESCR7_SIOP _escr7.bit._SIOP +#define ESCR7_SOPE _escr7.bit._SOPE +#define ESCR7_LBL0 _escr7.bit._LBL0 +#define ESCR7_LBL1 _escr7.bit._LBL1 +#define ESCR7_LBD _escr7.bit._LBD +#define ESCR7_LBIE _escr7.bit._LBIE +#define ESCR7_LBL _escr7.bitc._LBL +__IO_EXTENDED BGR7STR _bgr7; +#define BGR7 _bgr7.word +#define BGR7_BGR0 _bgr7.bit._BGR0 +#define BGR7_BGR1 _bgr7.bit._BGR1 +#define BGR7_BGR2 _bgr7.bit._BGR2 +#define BGR7_BGR3 _bgr7.bit._BGR3 +#define BGR7_BGR4 _bgr7.bit._BGR4 +#define BGR7_BGR5 _bgr7.bit._BGR5 +#define BGR7_BGR6 _bgr7.bit._BGR6 +#define BGR7_BGR7 _bgr7.bit._BGR7 +#define BGR7_BGR8 _bgr7.bit._BGR8 +#define BGR7_BGR9 _bgr7.bit._BGR9 +#define BGR7_BGR10 _bgr7.bit._BGR10 +#define BGR7_BGR11 _bgr7.bit._BGR11 +#define BGR7_BGR12 _bgr7.bit._BGR12 +#define BGR7_BGR13 _bgr7.bit._BGR13 +#define BGR7_BGR14 _bgr7.bit._BGR14 +#define BGR7_BGR15 _bgr7.bit._BGR15 +#define BGR7_BGR _bgr7.bitc._BGR +__IO_EXTENDED BGRL7STR _bgrl7; +#define BGRL7 _bgrl7.byte +#define BGRL7_BGR0 _bgrl7.bit._BGR0 +#define BGRL7_BGR1 _bgrl7.bit._BGR1 +#define BGRL7_BGR2 _bgrl7.bit._BGR2 +#define BGRL7_BGR3 _bgrl7.bit._BGR3 +#define BGRL7_BGR4 _bgrl7.bit._BGR4 +#define BGRL7_BGR5 _bgrl7.bit._BGR5 +#define BGRL7_BGR6 _bgrl7.bit._BGR6 +#define BGRL7_BGR7 _bgrl7.bit._BGR7 +__IO_EXTENDED BGRH7STR _bgrh7; +#define BGRH7 _bgrh7.byte +#define BGRH7_BGR8 _bgrh7.bit._BGR8 +#define BGRH7_BGR9 _bgrh7.bit._BGR9 +#define BGRH7_BGR10 _bgrh7.bit._BGR10 +#define BGRH7_BGR11 _bgrh7.bit._BGR11 +#define BGRH7_BGR12 _bgrh7.bit._BGR12 +#define BGRH7_BGR13 _bgrh7.bit._BGR13 +#define BGRH7_BGR14 _bgrh7.bit._BGR14 +#define BGRH7_BGR15 _bgrh7.bit._BGR15 +__IO_EXTENDED ESIR7STR _esir7; +#define ESIR7 _esir7.byte +#define ESIR7_AICD _esir7.bit._AICD +#define ESIR7_RBI _esir7.bit._RBI +#define ESIR7_RDRF _esir7.bit._RDRF +#define ESIR7_TDRE _esir7.bit._TDRE +__IO_EXTENDED SMR8STR _smr8; +#define SMR8 _smr8.byte +#define SMR8_SOE _smr8.bit._SOE +#define SMR8_SCKE _smr8.bit._SCKE +#define SMR8_UPCL _smr8.bit._UPCL +#define SMR8_REST _smr8.bit._REST +#define SMR8_EXT _smr8.bit._EXT +#define SMR8_OTO _smr8.bit._OTO +#define SMR8_MD0 _smr8.bit._MD0 +#define SMR8_MD1 _smr8.bit._MD1 +#define SMR8_MD _smr8.bitc._MD +__IO_EXTENDED SCR8STR _scr8; +#define SCR8 _scr8.byte +#define SCR8_TXE _scr8.bit._TXE +#define SCR8_RXE _scr8.bit._RXE +#define SCR8_CRE _scr8.bit._CRE +#define SCR8_AD _scr8.bit._AD +#define SCR8_CL _scr8.bit._CL +#define SCR8_SBL _scr8.bit._SBL +#define SCR8_P _scr8.bit._P +#define SCR8_PEN _scr8.bit._PEN +__IO_EXTENDED IO_BYTE _tdr8; +#define TDR8 _tdr8 +__IO_EXTENDED IO_BYTE _rdr8; +#define RDR8 _rdr8 +__IO_EXTENDED SSR8STR _ssr8; +#define SSR8 _ssr8.byte +#define SSR8_TIE _ssr8.bit._TIE +#define SSR8_RIE _ssr8.bit._RIE +#define SSR8_BDS _ssr8.bit._BDS +#define SSR8_TDRE _ssr8.bit._TDRE +#define SSR8_RDRF _ssr8.bit._RDRF +#define SSR8_FRE _ssr8.bit._FRE +#define SSR8_ORE _ssr8.bit._ORE +#define SSR8_PE _ssr8.bit._PE +__IO_EXTENDED ECCR8STR _eccr8; +#define ECCR8 _eccr8.byte +#define ECCR8_TBI _eccr8.bit._TBI +#define ECCR8_RBI _eccr8.bit._RBI +#define ECCR8_BIE _eccr8.bit._BIE +#define ECCR8_SSM _eccr8.bit._SSM +#define ECCR8_SCDE _eccr8.bit._SCDE +#define ECCR8_MS _eccr8.bit._MS +#define ECCR8_LBR _eccr8.bit._LBR +#define ECCR8_INV _eccr8.bit._INV +__IO_EXTENDED ESCR8STR _escr8; +#define ESCR8 _escr8.byte +#define ESCR8_SCES _escr8.bit._SCES +#define ESCR8_CCO _escr8.bit._CCO +#define ESCR8_SIOP _escr8.bit._SIOP +#define ESCR8_SOPE _escr8.bit._SOPE +#define ESCR8_LBL0 _escr8.bit._LBL0 +#define ESCR8_LBL1 _escr8.bit._LBL1 +#define ESCR8_LBD _escr8.bit._LBD +#define ESCR8_LBIE _escr8.bit._LBIE +#define ESCR8_LBL _escr8.bitc._LBL +__IO_EXTENDED BGR8STR _bgr8; +#define BGR8 _bgr8.word +#define BGR8_BGR0 _bgr8.bit._BGR0 +#define BGR8_BGR1 _bgr8.bit._BGR1 +#define BGR8_BGR2 _bgr8.bit._BGR2 +#define BGR8_BGR3 _bgr8.bit._BGR3 +#define BGR8_BGR4 _bgr8.bit._BGR4 +#define BGR8_BGR5 _bgr8.bit._BGR5 +#define BGR8_BGR6 _bgr8.bit._BGR6 +#define BGR8_BGR7 _bgr8.bit._BGR7 +#define BGR8_BGR8 _bgr8.bit._BGR8 +#define BGR8_BGR9 _bgr8.bit._BGR9 +#define BGR8_BGR10 _bgr8.bit._BGR10 +#define BGR8_BGR11 _bgr8.bit._BGR11 +#define BGR8_BGR12 _bgr8.bit._BGR12 +#define BGR8_BGR13 _bgr8.bit._BGR13 +#define BGR8_BGR14 _bgr8.bit._BGR14 +#define BGR8_BGR15 _bgr8.bit._BGR15 +#define BGR8_BGR _bgr8.bitc._BGR +__IO_EXTENDED BGRL8STR _bgrl8; +#define BGRL8 _bgrl8.byte +#define BGRL8_BGR0 _bgrl8.bit._BGR0 +#define BGRL8_BGR1 _bgrl8.bit._BGR1 +#define BGRL8_BGR2 _bgrl8.bit._BGR2 +#define BGRL8_BGR3 _bgrl8.bit._BGR3 +#define BGRL8_BGR4 _bgrl8.bit._BGR4 +#define BGRL8_BGR5 _bgrl8.bit._BGR5 +#define BGRL8_BGR6 _bgrl8.bit._BGR6 +#define BGRL8_BGR7 _bgrl8.bit._BGR7 +__IO_EXTENDED BGRH8STR _bgrh8; +#define BGRH8 _bgrh8.byte +#define BGRH8_BGR8 _bgrh8.bit._BGR8 +#define BGRH8_BGR9 _bgrh8.bit._BGR9 +#define BGRH8_BGR10 _bgrh8.bit._BGR10 +#define BGRH8_BGR11 _bgrh8.bit._BGR11 +#define BGRH8_BGR12 _bgrh8.bit._BGR12 +#define BGRH8_BGR13 _bgrh8.bit._BGR13 +#define BGRH8_BGR14 _bgrh8.bit._BGR14 +#define BGRH8_BGR15 _bgrh8.bit._BGR15 +__IO_EXTENDED ESIR8STR _esir8; +#define ESIR8 _esir8.byte +#define ESIR8_AICD _esir8.bit._AICD +#define ESIR8_RBI _esir8.bit._RBI +#define ESIR8_RDRF _esir8.bit._RDRF +#define ESIR8_TDRE _esir8.bit._TDRE +__IO_EXTENDED SMR9STR _smr9; +#define SMR9 _smr9.byte +#define SMR9_SOE _smr9.bit._SOE +#define SMR9_SCKE _smr9.bit._SCKE +#define SMR9_UPCL _smr9.bit._UPCL +#define SMR9_REST _smr9.bit._REST +#define SMR9_EXT _smr9.bit._EXT +#define SMR9_OTO _smr9.bit._OTO +#define SMR9_MD0 _smr9.bit._MD0 +#define SMR9_MD1 _smr9.bit._MD1 +#define SMR9_MD _smr9.bitc._MD +__IO_EXTENDED SCR9STR _scr9; +#define SCR9 _scr9.byte +#define SCR9_TXE _scr9.bit._TXE +#define SCR9_RXE _scr9.bit._RXE +#define SCR9_CRE _scr9.bit._CRE +#define SCR9_AD _scr9.bit._AD +#define SCR9_CL _scr9.bit._CL +#define SCR9_SBL _scr9.bit._SBL +#define SCR9_P _scr9.bit._P +#define SCR9_PEN _scr9.bit._PEN +__IO_EXTENDED IO_BYTE _tdr9; +#define TDR9 _tdr9 +__IO_EXTENDED IO_BYTE _rdr9; +#define RDR9 _rdr9 +__IO_EXTENDED SSR9STR _ssr9; +#define SSR9 _ssr9.byte +#define SSR9_TIE _ssr9.bit._TIE +#define SSR9_RIE _ssr9.bit._RIE +#define SSR9_BDS _ssr9.bit._BDS +#define SSR9_TDRE _ssr9.bit._TDRE +#define SSR9_RDRF _ssr9.bit._RDRF +#define SSR9_FRE _ssr9.bit._FRE +#define SSR9_ORE _ssr9.bit._ORE +#define SSR9_PE _ssr9.bit._PE +__IO_EXTENDED ECCR9STR _eccr9; +#define ECCR9 _eccr9.byte +#define ECCR9_TBI _eccr9.bit._TBI +#define ECCR9_RBI _eccr9.bit._RBI +#define ECCR9_BIE _eccr9.bit._BIE +#define ECCR9_SSM _eccr9.bit._SSM +#define ECCR9_SCDE _eccr9.bit._SCDE +#define ECCR9_MS _eccr9.bit._MS +#define ECCR9_LBR _eccr9.bit._LBR +#define ECCR9_INV _eccr9.bit._INV +__IO_EXTENDED ESCR9STR _escr9; +#define ESCR9 _escr9.byte +#define ESCR9_SCES _escr9.bit._SCES +#define ESCR9_CCO _escr9.bit._CCO +#define ESCR9_SIOP _escr9.bit._SIOP +#define ESCR9_SOPE _escr9.bit._SOPE +#define ESCR9_LBL0 _escr9.bit._LBL0 +#define ESCR9_LBL1 _escr9.bit._LBL1 +#define ESCR9_LBD _escr9.bit._LBD +#define ESCR9_LBIE _escr9.bit._LBIE +#define ESCR9_LBL _escr9.bitc._LBL +__IO_EXTENDED BGR9STR _bgr9; +#define BGR9 _bgr9.word +#define BGR9_BGR0 _bgr9.bit._BGR0 +#define BGR9_BGR1 _bgr9.bit._BGR1 +#define BGR9_BGR2 _bgr9.bit._BGR2 +#define BGR9_BGR3 _bgr9.bit._BGR3 +#define BGR9_BGR4 _bgr9.bit._BGR4 +#define BGR9_BGR5 _bgr9.bit._BGR5 +#define BGR9_BGR6 _bgr9.bit._BGR6 +#define BGR9_BGR7 _bgr9.bit._BGR7 +#define BGR9_BGR8 _bgr9.bit._BGR8 +#define BGR9_BGR9 _bgr9.bit._BGR9 +#define BGR9_BGR10 _bgr9.bit._BGR10 +#define BGR9_BGR11 _bgr9.bit._BGR11 +#define BGR9_BGR12 _bgr9.bit._BGR12 +#define BGR9_BGR13 _bgr9.bit._BGR13 +#define BGR9_BGR14 _bgr9.bit._BGR14 +#define BGR9_BGR15 _bgr9.bit._BGR15 +#define BGR9_BGR _bgr9.bitc._BGR +__IO_EXTENDED BGRL9STR _bgrl9; +#define BGRL9 _bgrl9.byte +#define BGRL9_BGR0 _bgrl9.bit._BGR0 +#define BGRL9_BGR1 _bgrl9.bit._BGR1 +#define BGRL9_BGR2 _bgrl9.bit._BGR2 +#define BGRL9_BGR3 _bgrl9.bit._BGR3 +#define BGRL9_BGR4 _bgrl9.bit._BGR4 +#define BGRL9_BGR5 _bgrl9.bit._BGR5 +#define BGRL9_BGR6 _bgrl9.bit._BGR6 +#define BGRL9_BGR7 _bgrl9.bit._BGR7 +__IO_EXTENDED BGRH9STR _bgrh9; +#define BGRH9 _bgrh9.byte +#define BGRH9_BGR8 _bgrh9.bit._BGR8 +#define BGRH9_BGR9 _bgrh9.bit._BGR9 +#define BGRH9_BGR10 _bgrh9.bit._BGR10 +#define BGRH9_BGR11 _bgrh9.bit._BGR11 +#define BGRH9_BGR12 _bgrh9.bit._BGR12 +#define BGRH9_BGR13 _bgrh9.bit._BGR13 +#define BGRH9_BGR14 _bgrh9.bit._BGR14 +#define BGRH9_BGR15 _bgrh9.bit._BGR15 +__IO_EXTENDED ESIR9STR _esir9; +#define ESIR9 _esir9.byte +#define ESIR9_AICD _esir9.bit._AICD +#define ESIR9_RBI _esir9.bit._RBI +#define ESIR9_RDRF _esir9.bit._RDRF +#define ESIR9_TDRE _esir9.bit._TDRE +__IO_EXTENDED ACSR0STR _acsr0; +#define ACSR0 _acsr0.byte +#define ACSR0_PD _acsr0.bit._PD +#define ACSR0_IEN _acsr0.bit._IEN +#define ACSR0_IRQ _acsr0.bit._IRQ +#define ACSR0_OUT1 _acsr0.bit._OUT1 +#define ACSR0_OUT2 _acsr0.bit._OUT2 +#define ACSR0_UVEN _acsr0.bit._UVEN +#define ACSR0_OVEN _acsr0.bit._OVEN +#define ACSR0_CMD _acsr0.bit._CMD +__IO_EXTENDED AECSR0STR _aecsr0; +#define AECSR0 _aecsr0.byte +#define AECSR0_INTREF _aecsr0.bit._INTREF +#define AECSR0_ACE _aecsr0.bit._ACE +__IO_EXTENDED ACSR1STR _acsr1; +#define ACSR1 _acsr1.byte +#define ACSR1_PD _acsr1.bit._PD +#define ACSR1_IEN _acsr1.bit._IEN +#define ACSR1_IRQ _acsr1.bit._IRQ +#define ACSR1_OUT1 _acsr1.bit._OUT1 +#define ACSR1_OUT2 _acsr1.bit._OUT2 +#define ACSR1_UVEN _acsr1.bit._UVEN +#define ACSR1_OVEN _acsr1.bit._OVEN +#define ACSR1_CMD _acsr1.bit._CMD +__IO_EXTENDED AECSR1STR _aecsr1; +#define AECSR1 _aecsr1.byte +#define AECSR1_INTREF _aecsr1.bit._INTREF +#define AECSR1_ACE _aecsr1.bit._ACE +__IO_EXTENDED PTMR6STR _ptmr6; +#define PTMR6 _ptmr6.word +#define PTMR6_D0 _ptmr6.bit._D0 +#define PTMR6_D1 _ptmr6.bit._D1 +#define PTMR6_D2 _ptmr6.bit._D2 +#define PTMR6_D3 _ptmr6.bit._D3 +#define PTMR6_D4 _ptmr6.bit._D4 +#define PTMR6_D5 _ptmr6.bit._D5 +#define PTMR6_D6 _ptmr6.bit._D6 +#define PTMR6_D7 _ptmr6.bit._D7 +#define PTMR6_D8 _ptmr6.bit._D8 +#define PTMR6_D9 _ptmr6.bit._D9 +#define PTMR6_D10 _ptmr6.bit._D10 +#define PTMR6_D11 _ptmr6.bit._D11 +#define PTMR6_D12 _ptmr6.bit._D12 +#define PTMR6_D13 _ptmr6.bit._D13 +#define PTMR6_D14 _ptmr6.bit._D14 +#define PTMR6_D15 _ptmr6.bit._D15 +#define PTMR6_D _ptmr6.bitc._D +__IO_EXTENDED PCSR6STR _pcsr6; +#define PCSR6 _pcsr6.word +#define PCSR6_D0 _pcsr6.bit._D0 +#define PCSR6_D1 _pcsr6.bit._D1 +#define PCSR6_D2 _pcsr6.bit._D2 +#define PCSR6_D3 _pcsr6.bit._D3 +#define PCSR6_D4 _pcsr6.bit._D4 +#define PCSR6_D5 _pcsr6.bit._D5 +#define PCSR6_D6 _pcsr6.bit._D6 +#define PCSR6_D7 _pcsr6.bit._D7 +#define PCSR6_D8 _pcsr6.bit._D8 +#define PCSR6_D9 _pcsr6.bit._D9 +#define PCSR6_D10 _pcsr6.bit._D10 +#define PCSR6_D11 _pcsr6.bit._D11 +#define PCSR6_D12 _pcsr6.bit._D12 +#define PCSR6_D13 _pcsr6.bit._D13 +#define PCSR6_D14 _pcsr6.bit._D14 +#define PCSR6_D15 _pcsr6.bit._D15 +#define PCSR6_D _pcsr6.bitc._D +__IO_EXTENDED PDUT6STR _pdut6; +#define PDUT6 _pdut6.word +#define PDUT6_D0 _pdut6.bit._D0 +#define PDUT6_D1 _pdut6.bit._D1 +#define PDUT6_D2 _pdut6.bit._D2 +#define PDUT6_D3 _pdut6.bit._D3 +#define PDUT6_D4 _pdut6.bit._D4 +#define PDUT6_D5 _pdut6.bit._D5 +#define PDUT6_D6 _pdut6.bit._D6 +#define PDUT6_D7 _pdut6.bit._D7 +#define PDUT6_D8 _pdut6.bit._D8 +#define PDUT6_D9 _pdut6.bit._D9 +#define PDUT6_D10 _pdut6.bit._D10 +#define PDUT6_D11 _pdut6.bit._D11 +#define PDUT6_D12 _pdut6.bit._D12 +#define PDUT6_D13 _pdut6.bit._D13 +#define PDUT6_D14 _pdut6.bit._D14 +#define PDUT6_D15 _pdut6.bit._D15 +#define PDUT6_D _pdut6.bitc._D +__IO_EXTENDED PCN6STR _pcn6; +#define PCN6 _pcn6.word +#define PCN6_OSEL _pcn6.bit._OSEL +#define PCN6_OE _pcn6.bit._OE +#define PCN6_IRS0 _pcn6.bit._IRS0 +#define PCN6_IRS1 _pcn6.bit._IRS1 +#define PCN6_IRQF _pcn6.bit._IRQF +#define PCN6_IREN _pcn6.bit._IREN +#define PCN6_EGS0 _pcn6.bit._EGS0 +#define PCN6_EGS1 _pcn6.bit._EGS1 +#define PCN6_PGMS _pcn6.bit._PGMS +#define PCN6_CKS0 _pcn6.bit._CKS0 +#define PCN6_CKS1 _pcn6.bit._CKS1 +#define PCN6_RTRG _pcn6.bit._RTRG +#define PCN6_MDSE _pcn6.bit._MDSE +#define PCN6_STGR _pcn6.bit._STGR +#define PCN6_CNTE _pcn6.bit._CNTE +#define PCN6_IRS _pcn6.bitc._IRS +#define PCN6_EGS _pcn6.bitc._EGS +#define PCN6_CKS _pcn6.bitc._CKS +__IO_EXTENDED PCNL6STR _pcnl6; +#define PCNL6 _pcnl6.byte +#define PCNL6_OSEL _pcnl6.bit._OSEL +#define PCNL6_OE _pcnl6.bit._OE +#define PCNL6_IRS0 _pcnl6.bit._IRS0 +#define PCNL6_IRS1 _pcnl6.bit._IRS1 +#define PCNL6_IRQF _pcnl6.bit._IRQF +#define PCNL6_IREN _pcnl6.bit._IREN +#define PCNL6_EGS0 _pcnl6.bit._EGS0 +#define PCNL6_EGS1 _pcnl6.bit._EGS1 +#define PCNL6_IRS _pcnl6.bitc._IRS +#define PCNL6_EGS _pcnl6.bitc._EGS +__IO_EXTENDED PCNH6STR _pcnh6; +#define PCNH6 _pcnh6.byte +#define PCNH6_PGMS _pcnh6.bit._PGMS +#define PCNH6_CKS0 _pcnh6.bit._CKS0 +#define PCNH6_CKS1 _pcnh6.bit._CKS1 +#define PCNH6_RTRG _pcnh6.bit._RTRG +#define PCNH6_MDSE _pcnh6.bit._MDSE +#define PCNH6_STGR _pcnh6.bit._STGR +#define PCNH6_CNTE _pcnh6.bit._CNTE +#define PCNH6_CKS _pcnh6.bitc._CKS +__IO_EXTENDED PTMR7STR _ptmr7; +#define PTMR7 _ptmr7.word +#define PTMR7_D0 _ptmr7.bit._D0 +#define PTMR7_D1 _ptmr7.bit._D1 +#define PTMR7_D2 _ptmr7.bit._D2 +#define PTMR7_D3 _ptmr7.bit._D3 +#define PTMR7_D4 _ptmr7.bit._D4 +#define PTMR7_D5 _ptmr7.bit._D5 +#define PTMR7_D6 _ptmr7.bit._D6 +#define PTMR7_D7 _ptmr7.bit._D7 +#define PTMR7_D8 _ptmr7.bit._D8 +#define PTMR7_D9 _ptmr7.bit._D9 +#define PTMR7_D10 _ptmr7.bit._D10 +#define PTMR7_D11 _ptmr7.bit._D11 +#define PTMR7_D12 _ptmr7.bit._D12 +#define PTMR7_D13 _ptmr7.bit._D13 +#define PTMR7_D14 _ptmr7.bit._D14 +#define PTMR7_D15 _ptmr7.bit._D15 +#define PTMR7_D _ptmr7.bitc._D +__IO_EXTENDED PCSR7STR _pcsr7; +#define PCSR7 _pcsr7.word +#define PCSR7_D0 _pcsr7.bit._D0 +#define PCSR7_D1 _pcsr7.bit._D1 +#define PCSR7_D2 _pcsr7.bit._D2 +#define PCSR7_D3 _pcsr7.bit._D3 +#define PCSR7_D4 _pcsr7.bit._D4 +#define PCSR7_D5 _pcsr7.bit._D5 +#define PCSR7_D6 _pcsr7.bit._D6 +#define PCSR7_D7 _pcsr7.bit._D7 +#define PCSR7_D8 _pcsr7.bit._D8 +#define PCSR7_D9 _pcsr7.bit._D9 +#define PCSR7_D10 _pcsr7.bit._D10 +#define PCSR7_D11 _pcsr7.bit._D11 +#define PCSR7_D12 _pcsr7.bit._D12 +#define PCSR7_D13 _pcsr7.bit._D13 +#define PCSR7_D14 _pcsr7.bit._D14 +#define PCSR7_D15 _pcsr7.bit._D15 +#define PCSR7_D _pcsr7.bitc._D +__IO_EXTENDED PDUT7STR _pdut7; +#define PDUT7 _pdut7.word +#define PDUT7_D0 _pdut7.bit._D0 +#define PDUT7_D1 _pdut7.bit._D1 +#define PDUT7_D2 _pdut7.bit._D2 +#define PDUT7_D3 _pdut7.bit._D3 +#define PDUT7_D4 _pdut7.bit._D4 +#define PDUT7_D5 _pdut7.bit._D5 +#define PDUT7_D6 _pdut7.bit._D6 +#define PDUT7_D7 _pdut7.bit._D7 +#define PDUT7_D8 _pdut7.bit._D8 +#define PDUT7_D9 _pdut7.bit._D9 +#define PDUT7_D10 _pdut7.bit._D10 +#define PDUT7_D11 _pdut7.bit._D11 +#define PDUT7_D12 _pdut7.bit._D12 +#define PDUT7_D13 _pdut7.bit._D13 +#define PDUT7_D14 _pdut7.bit._D14 +#define PDUT7_D15 _pdut7.bit._D15 +#define PDUT7_D _pdut7.bitc._D +__IO_EXTENDED PCN7STR _pcn7; +#define PCN7 _pcn7.word +#define PCN7_OSEL _pcn7.bit._OSEL +#define PCN7_OE _pcn7.bit._OE +#define PCN7_IRS0 _pcn7.bit._IRS0 +#define PCN7_IRS1 _pcn7.bit._IRS1 +#define PCN7_IRQF _pcn7.bit._IRQF +#define PCN7_IREN _pcn7.bit._IREN +#define PCN7_EGS0 _pcn7.bit._EGS0 +#define PCN7_EGS1 _pcn7.bit._EGS1 +#define PCN7_PGMS _pcn7.bit._PGMS +#define PCN7_CKS0 _pcn7.bit._CKS0 +#define PCN7_CKS1 _pcn7.bit._CKS1 +#define PCN7_RTRG _pcn7.bit._RTRG +#define PCN7_MDSE _pcn7.bit._MDSE +#define PCN7_STGR _pcn7.bit._STGR +#define PCN7_CNTE _pcn7.bit._CNTE +#define PCN7_IRS _pcn7.bitc._IRS +#define PCN7_EGS _pcn7.bitc._EGS +#define PCN7_CKS _pcn7.bitc._CKS +__IO_EXTENDED PCNL7STR _pcnl7; +#define PCNL7 _pcnl7.byte +#define PCNL7_OSEL _pcnl7.bit._OSEL +#define PCNL7_OE _pcnl7.bit._OE +#define PCNL7_IRS0 _pcnl7.bit._IRS0 +#define PCNL7_IRS1 _pcnl7.bit._IRS1 +#define PCNL7_IRQF _pcnl7.bit._IRQF +#define PCNL7_IREN _pcnl7.bit._IREN +#define PCNL7_EGS0 _pcnl7.bit._EGS0 +#define PCNL7_EGS1 _pcnl7.bit._EGS1 +#define PCNL7_IRS _pcnl7.bitc._IRS +#define PCNL7_EGS _pcnl7.bitc._EGS +__IO_EXTENDED PCNH7STR _pcnh7; +#define PCNH7 _pcnh7.byte +#define PCNH7_PGMS _pcnh7.bit._PGMS +#define PCNH7_CKS0 _pcnh7.bit._CKS0 +#define PCNH7_CKS1 _pcnh7.bit._CKS1 +#define PCNH7_RTRG _pcnh7.bit._RTRG +#define PCNH7_MDSE _pcnh7.bit._MDSE +#define PCNH7_STGR _pcnh7.bit._STGR +#define PCNH7_CNTE _pcnh7.bit._CNTE +#define PCNH7_CKS _pcnh7.bitc._CKS +__IO_EXTENDED GCN12STR _gcn12; +#define GCN12 _gcn12.word +#define GCN12_TSEL00 _gcn12.bit._TSEL00 +#define GCN12_TSEL01 _gcn12.bit._TSEL01 +#define GCN12_TSEL02 _gcn12.bit._TSEL02 +#define GCN12_TSEL03 _gcn12.bit._TSEL03 +#define GCN12_TSEL10 _gcn12.bit._TSEL10 +#define GCN12_TSEL11 _gcn12.bit._TSEL11 +#define GCN12_TSEL12 _gcn12.bit._TSEL12 +#define GCN12_TSEL13 _gcn12.bit._TSEL13 +#define GCN12_TSEL20 _gcn12.bit._TSEL20 +#define GCN12_TSEL21 _gcn12.bit._TSEL21 +#define GCN12_TSEL22 _gcn12.bit._TSEL22 +#define GCN12_TSEL23 _gcn12.bit._TSEL23 +#define GCN12_TSEL30 _gcn12.bit._TSEL30 +#define GCN12_TSEL31 _gcn12.bit._TSEL31 +#define GCN12_TSEL32 _gcn12.bit._TSEL32 +#define GCN12_TSEL33 _gcn12.bit._TSEL33 +#define GCN12_TSEL0 _gcn12.bitc._TSEL0 +#define GCN12_TSEL1 _gcn12.bitc._TSEL1 +#define GCN12_TSEL2 _gcn12.bitc._TSEL2 +#define GCN12_TSEL3 _gcn12.bitc._TSEL3 +__IO_EXTENDED GCN1L2STR _gcn1l2; +#define GCN1L2 _gcn1l2.byte +#define GCN1L2_TSEL00 _gcn1l2.bit._TSEL00 +#define GCN1L2_TSEL01 _gcn1l2.bit._TSEL01 +#define GCN1L2_TSEL02 _gcn1l2.bit._TSEL02 +#define GCN1L2_TSEL03 _gcn1l2.bit._TSEL03 +#define GCN1L2_TSEL10 _gcn1l2.bit._TSEL10 +#define GCN1L2_TSEL11 _gcn1l2.bit._TSEL11 +#define GCN1L2_TSEL12 _gcn1l2.bit._TSEL12 +#define GCN1L2_TSEL13 _gcn1l2.bit._TSEL13 +#define GCN1L2_TSEL0 _gcn1l2.bitc._TSEL0 +#define GCN1L2_TSEL1 _gcn1l2.bitc._TSEL1 +__IO_EXTENDED GCN1H2STR _gcn1h2; +#define GCN1H2 _gcn1h2.byte +#define GCN1H2_TSEL20 _gcn1h2.bit._TSEL20 +#define GCN1H2_TSEL21 _gcn1h2.bit._TSEL21 +#define GCN1H2_TSEL22 _gcn1h2.bit._TSEL22 +#define GCN1H2_TSEL23 _gcn1h2.bit._TSEL23 +#define GCN1H2_TSEL30 _gcn1h2.bit._TSEL30 +#define GCN1H2_TSEL31 _gcn1h2.bit._TSEL31 +#define GCN1H2_TSEL32 _gcn1h2.bit._TSEL32 +#define GCN1H2_TSEL33 _gcn1h2.bit._TSEL33 +#define GCN1H2_TSEL2 _gcn1h2.bitc._TSEL2 +#define GCN1H2_TSEL3 _gcn1h2.bitc._TSEL3 +__IO_EXTENDED GCN22STR _gcn22; +#define GCN22 _gcn22.word +#define GCN22_EN0 _gcn22.bit._EN0 +#define GCN22_EN1 _gcn22.bit._EN1 +#define GCN22_EN2 _gcn22.bit._EN2 +#define GCN22_EN3 _gcn22.bit._EN3 +#define GCN22_CKSEL0 _gcn22.bit._CKSEL0 +#define GCN22_CKSEL1 _gcn22.bit._CKSEL1 +#define GCN22_CKSEL2 _gcn22.bit._CKSEL2 +#define GCN22_CKSEL3 _gcn22.bit._CKSEL3 +#define GCN22_EN _gcn22.bitc._EN +#define GCN22_CKSEL _gcn22.bitc._CKSEL +__IO_EXTENDED GCN2L2STR _gcn2l2; +#define GCN2L2 _gcn2l2.byte +#define GCN2L2_EN0 _gcn2l2.bit._EN0 +#define GCN2L2_EN1 _gcn2l2.bit._EN1 +#define GCN2L2_EN2 _gcn2l2.bit._EN2 +#define GCN2L2_EN3 _gcn2l2.bit._EN3 +#define GCN2L2_EN _gcn2l2.bitc._EN +__IO_EXTENDED GCN2H2STR _gcn2h2; +#define GCN2H2 _gcn2h2.byte +#define GCN2H2_CKSEL0 _gcn2h2.bit._CKSEL0 +#define GCN2H2_CKSEL1 _gcn2h2.bit._CKSEL1 +#define GCN2H2_CKSEL2 _gcn2h2.bit._CKSEL2 +#define GCN2H2_CKSEL3 _gcn2h2.bit._CKSEL3 +#define GCN2H2_CKSEL _gcn2h2.bitc._CKSEL +__IO_EXTENDED PTMR8STR _ptmr8; +#define PTMR8 _ptmr8.word +#define PTMR8_D0 _ptmr8.bit._D0 +#define PTMR8_D1 _ptmr8.bit._D1 +#define PTMR8_D2 _ptmr8.bit._D2 +#define PTMR8_D3 _ptmr8.bit._D3 +#define PTMR8_D4 _ptmr8.bit._D4 +#define PTMR8_D5 _ptmr8.bit._D5 +#define PTMR8_D6 _ptmr8.bit._D6 +#define PTMR8_D7 _ptmr8.bit._D7 +#define PTMR8_D8 _ptmr8.bit._D8 +#define PTMR8_D9 _ptmr8.bit._D9 +#define PTMR8_D10 _ptmr8.bit._D10 +#define PTMR8_D11 _ptmr8.bit._D11 +#define PTMR8_D12 _ptmr8.bit._D12 +#define PTMR8_D13 _ptmr8.bit._D13 +#define PTMR8_D14 _ptmr8.bit._D14 +#define PTMR8_D15 _ptmr8.bit._D15 +#define PTMR8_D _ptmr8.bitc._D +__IO_EXTENDED PCSR8STR _pcsr8; +#define PCSR8 _pcsr8.word +#define PCSR8_D0 _pcsr8.bit._D0 +#define PCSR8_D1 _pcsr8.bit._D1 +#define PCSR8_D2 _pcsr8.bit._D2 +#define PCSR8_D3 _pcsr8.bit._D3 +#define PCSR8_D4 _pcsr8.bit._D4 +#define PCSR8_D5 _pcsr8.bit._D5 +#define PCSR8_D6 _pcsr8.bit._D6 +#define PCSR8_D7 _pcsr8.bit._D7 +#define PCSR8_D8 _pcsr8.bit._D8 +#define PCSR8_D9 _pcsr8.bit._D9 +#define PCSR8_D10 _pcsr8.bit._D10 +#define PCSR8_D11 _pcsr8.bit._D11 +#define PCSR8_D12 _pcsr8.bit._D12 +#define PCSR8_D13 _pcsr8.bit._D13 +#define PCSR8_D14 _pcsr8.bit._D14 +#define PCSR8_D15 _pcsr8.bit._D15 +#define PCSR8_D _pcsr8.bitc._D +__IO_EXTENDED PDUT8STR _pdut8; +#define PDUT8 _pdut8.word +#define PDUT8_D0 _pdut8.bit._D0 +#define PDUT8_D1 _pdut8.bit._D1 +#define PDUT8_D2 _pdut8.bit._D2 +#define PDUT8_D3 _pdut8.bit._D3 +#define PDUT8_D4 _pdut8.bit._D4 +#define PDUT8_D5 _pdut8.bit._D5 +#define PDUT8_D6 _pdut8.bit._D6 +#define PDUT8_D7 _pdut8.bit._D7 +#define PDUT8_D8 _pdut8.bit._D8 +#define PDUT8_D9 _pdut8.bit._D9 +#define PDUT8_D10 _pdut8.bit._D10 +#define PDUT8_D11 _pdut8.bit._D11 +#define PDUT8_D12 _pdut8.bit._D12 +#define PDUT8_D13 _pdut8.bit._D13 +#define PDUT8_D14 _pdut8.bit._D14 +#define PDUT8_D15 _pdut8.bit._D15 +#define PDUT8_D _pdut8.bitc._D +__IO_EXTENDED PCN8STR _pcn8; +#define PCN8 _pcn8.word +#define PCN8_OSEL _pcn8.bit._OSEL +#define PCN8_OE _pcn8.bit._OE +#define PCN8_IRS0 _pcn8.bit._IRS0 +#define PCN8_IRS1 _pcn8.bit._IRS1 +#define PCN8_IRQF _pcn8.bit._IRQF +#define PCN8_IREN _pcn8.bit._IREN +#define PCN8_EGS0 _pcn8.bit._EGS0 +#define PCN8_EGS1 _pcn8.bit._EGS1 +#define PCN8_PGMS _pcn8.bit._PGMS +#define PCN8_CKS0 _pcn8.bit._CKS0 +#define PCN8_CKS1 _pcn8.bit._CKS1 +#define PCN8_RTRG _pcn8.bit._RTRG +#define PCN8_MDSE _pcn8.bit._MDSE +#define PCN8_STGR _pcn8.bit._STGR +#define PCN8_CNTE _pcn8.bit._CNTE +#define PCN8_IRS _pcn8.bitc._IRS +#define PCN8_EGS _pcn8.bitc._EGS +#define PCN8_CKS _pcn8.bitc._CKS +__IO_EXTENDED PCNL8STR _pcnl8; +#define PCNL8 _pcnl8.byte +#define PCNL8_OSEL _pcnl8.bit._OSEL +#define PCNL8_OE _pcnl8.bit._OE +#define PCNL8_IRS0 _pcnl8.bit._IRS0 +#define PCNL8_IRS1 _pcnl8.bit._IRS1 +#define PCNL8_IRQF _pcnl8.bit._IRQF +#define PCNL8_IREN _pcnl8.bit._IREN +#define PCNL8_EGS0 _pcnl8.bit._EGS0 +#define PCNL8_EGS1 _pcnl8.bit._EGS1 +#define PCNL8_IRS _pcnl8.bitc._IRS +#define PCNL8_EGS _pcnl8.bitc._EGS +__IO_EXTENDED PCNH8STR _pcnh8; +#define PCNH8 _pcnh8.byte +#define PCNH8_PGMS _pcnh8.bit._PGMS +#define PCNH8_CKS0 _pcnh8.bit._CKS0 +#define PCNH8_CKS1 _pcnh8.bit._CKS1 +#define PCNH8_RTRG _pcnh8.bit._RTRG +#define PCNH8_MDSE _pcnh8.bit._MDSE +#define PCNH8_STGR _pcnh8.bit._STGR +#define PCNH8_CNTE _pcnh8.bit._CNTE +#define PCNH8_CKS _pcnh8.bitc._CKS +__IO_EXTENDED PTMR9STR _ptmr9; +#define PTMR9 _ptmr9.word +#define PTMR9_D0 _ptmr9.bit._D0 +#define PTMR9_D1 _ptmr9.bit._D1 +#define PTMR9_D2 _ptmr9.bit._D2 +#define PTMR9_D3 _ptmr9.bit._D3 +#define PTMR9_D4 _ptmr9.bit._D4 +#define PTMR9_D5 _ptmr9.bit._D5 +#define PTMR9_D6 _ptmr9.bit._D6 +#define PTMR9_D7 _ptmr9.bit._D7 +#define PTMR9_D8 _ptmr9.bit._D8 +#define PTMR9_D9 _ptmr9.bit._D9 +#define PTMR9_D10 _ptmr9.bit._D10 +#define PTMR9_D11 _ptmr9.bit._D11 +#define PTMR9_D12 _ptmr9.bit._D12 +#define PTMR9_D13 _ptmr9.bit._D13 +#define PTMR9_D14 _ptmr9.bit._D14 +#define PTMR9_D15 _ptmr9.bit._D15 +#define PTMR9_D _ptmr9.bitc._D +__IO_EXTENDED PCSR9STR _pcsr9; +#define PCSR9 _pcsr9.word +#define PCSR9_D0 _pcsr9.bit._D0 +#define PCSR9_D1 _pcsr9.bit._D1 +#define PCSR9_D2 _pcsr9.bit._D2 +#define PCSR9_D3 _pcsr9.bit._D3 +#define PCSR9_D4 _pcsr9.bit._D4 +#define PCSR9_D5 _pcsr9.bit._D5 +#define PCSR9_D6 _pcsr9.bit._D6 +#define PCSR9_D7 _pcsr9.bit._D7 +#define PCSR9_D8 _pcsr9.bit._D8 +#define PCSR9_D9 _pcsr9.bit._D9 +#define PCSR9_D10 _pcsr9.bit._D10 +#define PCSR9_D11 _pcsr9.bit._D11 +#define PCSR9_D12 _pcsr9.bit._D12 +#define PCSR9_D13 _pcsr9.bit._D13 +#define PCSR9_D14 _pcsr9.bit._D14 +#define PCSR9_D15 _pcsr9.bit._D15 +#define PCSR9_D _pcsr9.bitc._D +__IO_EXTENDED PDUT9STR _pdut9; +#define PDUT9 _pdut9.word +#define PDUT9_D0 _pdut9.bit._D0 +#define PDUT9_D1 _pdut9.bit._D1 +#define PDUT9_D2 _pdut9.bit._D2 +#define PDUT9_D3 _pdut9.bit._D3 +#define PDUT9_D4 _pdut9.bit._D4 +#define PDUT9_D5 _pdut9.bit._D5 +#define PDUT9_D6 _pdut9.bit._D6 +#define PDUT9_D7 _pdut9.bit._D7 +#define PDUT9_D8 _pdut9.bit._D8 +#define PDUT9_D9 _pdut9.bit._D9 +#define PDUT9_D10 _pdut9.bit._D10 +#define PDUT9_D11 _pdut9.bit._D11 +#define PDUT9_D12 _pdut9.bit._D12 +#define PDUT9_D13 _pdut9.bit._D13 +#define PDUT9_D14 _pdut9.bit._D14 +#define PDUT9_D15 _pdut9.bit._D15 +#define PDUT9_D _pdut9.bitc._D +__IO_EXTENDED PCN9STR _pcn9; +#define PCN9 _pcn9.word +#define PCN9_OSEL _pcn9.bit._OSEL +#define PCN9_OE _pcn9.bit._OE +#define PCN9_IRS0 _pcn9.bit._IRS0 +#define PCN9_IRS1 _pcn9.bit._IRS1 +#define PCN9_IRQF _pcn9.bit._IRQF +#define PCN9_IREN _pcn9.bit._IREN +#define PCN9_EGS0 _pcn9.bit._EGS0 +#define PCN9_EGS1 _pcn9.bit._EGS1 +#define PCN9_PGMS _pcn9.bit._PGMS +#define PCN9_CKS0 _pcn9.bit._CKS0 +#define PCN9_CKS1 _pcn9.bit._CKS1 +#define PCN9_RTRG _pcn9.bit._RTRG +#define PCN9_MDSE _pcn9.bit._MDSE +#define PCN9_STGR _pcn9.bit._STGR +#define PCN9_CNTE _pcn9.bit._CNTE +#define PCN9_IRS _pcn9.bitc._IRS +#define PCN9_EGS _pcn9.bitc._EGS +#define PCN9_CKS _pcn9.bitc._CKS +__IO_EXTENDED PCNL9STR _pcnl9; +#define PCNL9 _pcnl9.byte +#define PCNL9_OSEL _pcnl9.bit._OSEL +#define PCNL9_OE _pcnl9.bit._OE +#define PCNL9_IRS0 _pcnl9.bit._IRS0 +#define PCNL9_IRS1 _pcnl9.bit._IRS1 +#define PCNL9_IRQF _pcnl9.bit._IRQF +#define PCNL9_IREN _pcnl9.bit._IREN +#define PCNL9_EGS0 _pcnl9.bit._EGS0 +#define PCNL9_EGS1 _pcnl9.bit._EGS1 +#define PCNL9_IRS _pcnl9.bitc._IRS +#define PCNL9_EGS _pcnl9.bitc._EGS +__IO_EXTENDED PCNH9STR _pcnh9; +#define PCNH9 _pcnh9.byte +#define PCNH9_PGMS _pcnh9.bit._PGMS +#define PCNH9_CKS0 _pcnh9.bit._CKS0 +#define PCNH9_CKS1 _pcnh9.bit._CKS1 +#define PCNH9_RTRG _pcnh9.bit._RTRG +#define PCNH9_MDSE _pcnh9.bit._MDSE +#define PCNH9_STGR _pcnh9.bit._STGR +#define PCNH9_CNTE _pcnh9.bit._CNTE +#define PCNH9_CKS _pcnh9.bitc._CKS +__IO_EXTENDED PTMR10STR _ptmr10; +#define PTMR10 _ptmr10.word +#define PTMR10_D0 _ptmr10.bit._D0 +#define PTMR10_D1 _ptmr10.bit._D1 +#define PTMR10_D2 _ptmr10.bit._D2 +#define PTMR10_D3 _ptmr10.bit._D3 +#define PTMR10_D4 _ptmr10.bit._D4 +#define PTMR10_D5 _ptmr10.bit._D5 +#define PTMR10_D6 _ptmr10.bit._D6 +#define PTMR10_D7 _ptmr10.bit._D7 +#define PTMR10_D8 _ptmr10.bit._D8 +#define PTMR10_D9 _ptmr10.bit._D9 +#define PTMR10_D10 _ptmr10.bit._D10 +#define PTMR10_D11 _ptmr10.bit._D11 +#define PTMR10_D12 _ptmr10.bit._D12 +#define PTMR10_D13 _ptmr10.bit._D13 +#define PTMR10_D14 _ptmr10.bit._D14 +#define PTMR10_D15 _ptmr10.bit._D15 +#define PTMR10_D _ptmr10.bitc._D +__IO_EXTENDED PCSR10STR _pcsr10; +#define PCSR10 _pcsr10.word +#define PCSR10_D0 _pcsr10.bit._D0 +#define PCSR10_D1 _pcsr10.bit._D1 +#define PCSR10_D2 _pcsr10.bit._D2 +#define PCSR10_D3 _pcsr10.bit._D3 +#define PCSR10_D4 _pcsr10.bit._D4 +#define PCSR10_D5 _pcsr10.bit._D5 +#define PCSR10_D6 _pcsr10.bit._D6 +#define PCSR10_D7 _pcsr10.bit._D7 +#define PCSR10_D8 _pcsr10.bit._D8 +#define PCSR10_D9 _pcsr10.bit._D9 +#define PCSR10_D10 _pcsr10.bit._D10 +#define PCSR10_D11 _pcsr10.bit._D11 +#define PCSR10_D12 _pcsr10.bit._D12 +#define PCSR10_D13 _pcsr10.bit._D13 +#define PCSR10_D14 _pcsr10.bit._D14 +#define PCSR10_D15 _pcsr10.bit._D15 +#define PCSR10_D _pcsr10.bitc._D +__IO_EXTENDED PDUT10STR _pdut10; +#define PDUT10 _pdut10.word +#define PDUT10_D0 _pdut10.bit._D0 +#define PDUT10_D1 _pdut10.bit._D1 +#define PDUT10_D2 _pdut10.bit._D2 +#define PDUT10_D3 _pdut10.bit._D3 +#define PDUT10_D4 _pdut10.bit._D4 +#define PDUT10_D5 _pdut10.bit._D5 +#define PDUT10_D6 _pdut10.bit._D6 +#define PDUT10_D7 _pdut10.bit._D7 +#define PDUT10_D8 _pdut10.bit._D8 +#define PDUT10_D9 _pdut10.bit._D9 +#define PDUT10_D10 _pdut10.bit._D10 +#define PDUT10_D11 _pdut10.bit._D11 +#define PDUT10_D12 _pdut10.bit._D12 +#define PDUT10_D13 _pdut10.bit._D13 +#define PDUT10_D14 _pdut10.bit._D14 +#define PDUT10_D15 _pdut10.bit._D15 +#define PDUT10_D _pdut10.bitc._D +__IO_EXTENDED PCN10STR _pcn10; +#define PCN10 _pcn10.word +#define PCN10_OSEL _pcn10.bit._OSEL +#define PCN10_OE _pcn10.bit._OE +#define PCN10_IRS0 _pcn10.bit._IRS0 +#define PCN10_IRS1 _pcn10.bit._IRS1 +#define PCN10_IRQF _pcn10.bit._IRQF +#define PCN10_IREN _pcn10.bit._IREN +#define PCN10_EGS0 _pcn10.bit._EGS0 +#define PCN10_EGS1 _pcn10.bit._EGS1 +#define PCN10_PGMS _pcn10.bit._PGMS +#define PCN10_CKS0 _pcn10.bit._CKS0 +#define PCN10_CKS1 _pcn10.bit._CKS1 +#define PCN10_RTRG _pcn10.bit._RTRG +#define PCN10_MDSE _pcn10.bit._MDSE +#define PCN10_STGR _pcn10.bit._STGR +#define PCN10_CNTE _pcn10.bit._CNTE +#define PCN10_IRS _pcn10.bitc._IRS +#define PCN10_EGS _pcn10.bitc._EGS +#define PCN10_CKS _pcn10.bitc._CKS +__IO_EXTENDED PCNL10STR _pcnl10; +#define PCNL10 _pcnl10.byte +#define PCNL10_OSEL _pcnl10.bit._OSEL +#define PCNL10_OE _pcnl10.bit._OE +#define PCNL10_IRS0 _pcnl10.bit._IRS0 +#define PCNL10_IRS1 _pcnl10.bit._IRS1 +#define PCNL10_IRQF _pcnl10.bit._IRQF +#define PCNL10_IREN _pcnl10.bit._IREN +#define PCNL10_EGS0 _pcnl10.bit._EGS0 +#define PCNL10_EGS1 _pcnl10.bit._EGS1 +#define PCNL10_IRS _pcnl10.bitc._IRS +#define PCNL10_EGS _pcnl10.bitc._EGS +__IO_EXTENDED PCNH10STR _pcnh10; +#define PCNH10 _pcnh10.byte +#define PCNH10_PGMS _pcnh10.bit._PGMS +#define PCNH10_CKS0 _pcnh10.bit._CKS0 +#define PCNH10_CKS1 _pcnh10.bit._CKS1 +#define PCNH10_RTRG _pcnh10.bit._RTRG +#define PCNH10_MDSE _pcnh10.bit._MDSE +#define PCNH10_STGR _pcnh10.bit._STGR +#define PCNH10_CNTE _pcnh10.bit._CNTE +#define PCNH10_CKS _pcnh10.bitc._CKS +__IO_EXTENDED PTMR11STR _ptmr11; +#define PTMR11 _ptmr11.word +#define PTMR11_D0 _ptmr11.bit._D0 +#define PTMR11_D1 _ptmr11.bit._D1 +#define PTMR11_D2 _ptmr11.bit._D2 +#define PTMR11_D3 _ptmr11.bit._D3 +#define PTMR11_D4 _ptmr11.bit._D4 +#define PTMR11_D5 _ptmr11.bit._D5 +#define PTMR11_D6 _ptmr11.bit._D6 +#define PTMR11_D7 _ptmr11.bit._D7 +#define PTMR11_D8 _ptmr11.bit._D8 +#define PTMR11_D9 _ptmr11.bit._D9 +#define PTMR11_D10 _ptmr11.bit._D10 +#define PTMR11_D11 _ptmr11.bit._D11 +#define PTMR11_D12 _ptmr11.bit._D12 +#define PTMR11_D13 _ptmr11.bit._D13 +#define PTMR11_D14 _ptmr11.bit._D14 +#define PTMR11_D15 _ptmr11.bit._D15 +#define PTMR11_D _ptmr11.bitc._D +__IO_EXTENDED PCSR11STR _pcsr11; +#define PCSR11 _pcsr11.word +#define PCSR11_D0 _pcsr11.bit._D0 +#define PCSR11_D1 _pcsr11.bit._D1 +#define PCSR11_D2 _pcsr11.bit._D2 +#define PCSR11_D3 _pcsr11.bit._D3 +#define PCSR11_D4 _pcsr11.bit._D4 +#define PCSR11_D5 _pcsr11.bit._D5 +#define PCSR11_D6 _pcsr11.bit._D6 +#define PCSR11_D7 _pcsr11.bit._D7 +#define PCSR11_D8 _pcsr11.bit._D8 +#define PCSR11_D9 _pcsr11.bit._D9 +#define PCSR11_D10 _pcsr11.bit._D10 +#define PCSR11_D11 _pcsr11.bit._D11 +#define PCSR11_D12 _pcsr11.bit._D12 +#define PCSR11_D13 _pcsr11.bit._D13 +#define PCSR11_D14 _pcsr11.bit._D14 +#define PCSR11_D15 _pcsr11.bit._D15 +#define PCSR11_D _pcsr11.bitc._D +__IO_EXTENDED PDUT11STR _pdut11; +#define PDUT11 _pdut11.word +#define PDUT11_D0 _pdut11.bit._D0 +#define PDUT11_D1 _pdut11.bit._D1 +#define PDUT11_D2 _pdut11.bit._D2 +#define PDUT11_D3 _pdut11.bit._D3 +#define PDUT11_D4 _pdut11.bit._D4 +#define PDUT11_D5 _pdut11.bit._D5 +#define PDUT11_D6 _pdut11.bit._D6 +#define PDUT11_D7 _pdut11.bit._D7 +#define PDUT11_D8 _pdut11.bit._D8 +#define PDUT11_D9 _pdut11.bit._D9 +#define PDUT11_D10 _pdut11.bit._D10 +#define PDUT11_D11 _pdut11.bit._D11 +#define PDUT11_D12 _pdut11.bit._D12 +#define PDUT11_D13 _pdut11.bit._D13 +#define PDUT11_D14 _pdut11.bit._D14 +#define PDUT11_D15 _pdut11.bit._D15 +#define PDUT11_D _pdut11.bitc._D +__IO_EXTENDED PCN11STR _pcn11; +#define PCN11 _pcn11.word +#define PCN11_OSEL _pcn11.bit._OSEL +#define PCN11_OE _pcn11.bit._OE +#define PCN11_IRS0 _pcn11.bit._IRS0 +#define PCN11_IRS1 _pcn11.bit._IRS1 +#define PCN11_IRQF _pcn11.bit._IRQF +#define PCN11_IREN _pcn11.bit._IREN +#define PCN11_EGS0 _pcn11.bit._EGS0 +#define PCN11_EGS1 _pcn11.bit._EGS1 +#define PCN11_PGMS _pcn11.bit._PGMS +#define PCN11_CKS0 _pcn11.bit._CKS0 +#define PCN11_CKS1 _pcn11.bit._CKS1 +#define PCN11_RTRG _pcn11.bit._RTRG +#define PCN11_MDSE _pcn11.bit._MDSE +#define PCN11_STGR _pcn11.bit._STGR +#define PCN11_CNTE _pcn11.bit._CNTE +#define PCN11_IRS _pcn11.bitc._IRS +#define PCN11_EGS _pcn11.bitc._EGS +#define PCN11_CKS _pcn11.bitc._CKS +__IO_EXTENDED PCNL11STR _pcnl11; +#define PCNL11 _pcnl11.byte +#define PCNL11_OSEL _pcnl11.bit._OSEL +#define PCNL11_OE _pcnl11.bit._OE +#define PCNL11_IRS0 _pcnl11.bit._IRS0 +#define PCNL11_IRS1 _pcnl11.bit._IRS1 +#define PCNL11_IRQF _pcnl11.bit._IRQF +#define PCNL11_IREN _pcnl11.bit._IREN +#define PCNL11_EGS0 _pcnl11.bit._EGS0 +#define PCNL11_EGS1 _pcnl11.bit._EGS1 +#define PCNL11_IRS _pcnl11.bitc._IRS +#define PCNL11_EGS _pcnl11.bitc._EGS +__IO_EXTENDED PCNH11STR _pcnh11; +#define PCNH11 _pcnh11.byte +#define PCNH11_PGMS _pcnh11.bit._PGMS +#define PCNH11_CKS0 _pcnh11.bit._CKS0 +#define PCNH11_CKS1 _pcnh11.bit._CKS1 +#define PCNH11_RTRG _pcnh11.bit._RTRG +#define PCNH11_MDSE _pcnh11.bit._MDSE +#define PCNH11_STGR _pcnh11.bit._STGR +#define PCNH11_CNTE _pcnh11.bit._CNTE +#define PCNH11_CKS _pcnh11.bitc._CKS +__IO_EXTENDED GCN13STR _gcn13; +#define GCN13 _gcn13.word +#define GCN13_TSEL00 _gcn13.bit._TSEL00 +#define GCN13_TSEL01 _gcn13.bit._TSEL01 +#define GCN13_TSEL02 _gcn13.bit._TSEL02 +#define GCN13_TSEL03 _gcn13.bit._TSEL03 +#define GCN13_TSEL10 _gcn13.bit._TSEL10 +#define GCN13_TSEL11 _gcn13.bit._TSEL11 +#define GCN13_TSEL12 _gcn13.bit._TSEL12 +#define GCN13_TSEL13 _gcn13.bit._TSEL13 +#define GCN13_TSEL20 _gcn13.bit._TSEL20 +#define GCN13_TSEL21 _gcn13.bit._TSEL21 +#define GCN13_TSEL22 _gcn13.bit._TSEL22 +#define GCN13_TSEL23 _gcn13.bit._TSEL23 +#define GCN13_TSEL30 _gcn13.bit._TSEL30 +#define GCN13_TSEL31 _gcn13.bit._TSEL31 +#define GCN13_TSEL32 _gcn13.bit._TSEL32 +#define GCN13_TSEL33 _gcn13.bit._TSEL33 +#define GCN13_TSEL0 _gcn13.bitc._TSEL0 +#define GCN13_TSEL1 _gcn13.bitc._TSEL1 +#define GCN13_TSEL2 _gcn13.bitc._TSEL2 +#define GCN13_TSEL3 _gcn13.bitc._TSEL3 +__IO_EXTENDED GCN1L3STR _gcn1l3; +#define GCN1L3 _gcn1l3.byte +#define GCN1L3_TSEL00 _gcn1l3.bit._TSEL00 +#define GCN1L3_TSEL01 _gcn1l3.bit._TSEL01 +#define GCN1L3_TSEL02 _gcn1l3.bit._TSEL02 +#define GCN1L3_TSEL03 _gcn1l3.bit._TSEL03 +#define GCN1L3_TSEL10 _gcn1l3.bit._TSEL10 +#define GCN1L3_TSEL11 _gcn1l3.bit._TSEL11 +#define GCN1L3_TSEL12 _gcn1l3.bit._TSEL12 +#define GCN1L3_TSEL13 _gcn1l3.bit._TSEL13 +#define GCN1L3_TSEL0 _gcn1l3.bitc._TSEL0 +#define GCN1L3_TSEL1 _gcn1l3.bitc._TSEL1 +__IO_EXTENDED GCN1H3STR _gcn1h3; +#define GCN1H3 _gcn1h3.byte +#define GCN1H3_TSEL20 _gcn1h3.bit._TSEL20 +#define GCN1H3_TSEL21 _gcn1h3.bit._TSEL21 +#define GCN1H3_TSEL22 _gcn1h3.bit._TSEL22 +#define GCN1H3_TSEL23 _gcn1h3.bit._TSEL23 +#define GCN1H3_TSEL30 _gcn1h3.bit._TSEL30 +#define GCN1H3_TSEL31 _gcn1h3.bit._TSEL31 +#define GCN1H3_TSEL32 _gcn1h3.bit._TSEL32 +#define GCN1H3_TSEL33 _gcn1h3.bit._TSEL33 +#define GCN1H3_TSEL2 _gcn1h3.bitc._TSEL2 +#define GCN1H3_TSEL3 _gcn1h3.bitc._TSEL3 +__IO_EXTENDED GCN23STR _gcn23; +#define GCN23 _gcn23.word +#define GCN23_EN0 _gcn23.bit._EN0 +#define GCN23_EN1 _gcn23.bit._EN1 +#define GCN23_EN2 _gcn23.bit._EN2 +#define GCN23_EN3 _gcn23.bit._EN3 +#define GCN23_CKSEL0 _gcn23.bit._CKSEL0 +#define GCN23_CKSEL1 _gcn23.bit._CKSEL1 +#define GCN23_CKSEL2 _gcn23.bit._CKSEL2 +#define GCN23_CKSEL3 _gcn23.bit._CKSEL3 +#define GCN23_EN _gcn23.bitc._EN +#define GCN23_CKSEL _gcn23.bitc._CKSEL +__IO_EXTENDED GCN2L3STR _gcn2l3; +#define GCN2L3 _gcn2l3.byte +#define GCN2L3_EN0 _gcn2l3.bit._EN0 +#define GCN2L3_EN1 _gcn2l3.bit._EN1 +#define GCN2L3_EN2 _gcn2l3.bit._EN2 +#define GCN2L3_EN3 _gcn2l3.bit._EN3 +#define GCN2L3_EN _gcn2l3.bitc._EN +__IO_EXTENDED GCN2H3STR _gcn2h3; +#define GCN2H3 _gcn2h3.byte +#define GCN2H3_CKSEL0 _gcn2h3.bit._CKSEL0 +#define GCN2H3_CKSEL1 _gcn2h3.bit._CKSEL1 +#define GCN2H3_CKSEL2 _gcn2h3.bit._CKSEL2 +#define GCN2H3_CKSEL3 _gcn2h3.bit._CKSEL3 +#define GCN2H3_CKSEL _gcn2h3.bitc._CKSEL +__IO_EXTENDED PTMR12STR _ptmr12; +#define PTMR12 _ptmr12.word +#define PTMR12_D0 _ptmr12.bit._D0 +#define PTMR12_D1 _ptmr12.bit._D1 +#define PTMR12_D2 _ptmr12.bit._D2 +#define PTMR12_D3 _ptmr12.bit._D3 +#define PTMR12_D4 _ptmr12.bit._D4 +#define PTMR12_D5 _ptmr12.bit._D5 +#define PTMR12_D6 _ptmr12.bit._D6 +#define PTMR12_D7 _ptmr12.bit._D7 +#define PTMR12_D8 _ptmr12.bit._D8 +#define PTMR12_D9 _ptmr12.bit._D9 +#define PTMR12_D10 _ptmr12.bit._D10 +#define PTMR12_D11 _ptmr12.bit._D11 +#define PTMR12_D12 _ptmr12.bit._D12 +#define PTMR12_D13 _ptmr12.bit._D13 +#define PTMR12_D14 _ptmr12.bit._D14 +#define PTMR12_D15 _ptmr12.bit._D15 +#define PTMR12_D _ptmr12.bitc._D +__IO_EXTENDED PCSR12STR _pcsr12; +#define PCSR12 _pcsr12.word +#define PCSR12_D0 _pcsr12.bit._D0 +#define PCSR12_D1 _pcsr12.bit._D1 +#define PCSR12_D2 _pcsr12.bit._D2 +#define PCSR12_D3 _pcsr12.bit._D3 +#define PCSR12_D4 _pcsr12.bit._D4 +#define PCSR12_D5 _pcsr12.bit._D5 +#define PCSR12_D6 _pcsr12.bit._D6 +#define PCSR12_D7 _pcsr12.bit._D7 +#define PCSR12_D8 _pcsr12.bit._D8 +#define PCSR12_D9 _pcsr12.bit._D9 +#define PCSR12_D10 _pcsr12.bit._D10 +#define PCSR12_D11 _pcsr12.bit._D11 +#define PCSR12_D12 _pcsr12.bit._D12 +#define PCSR12_D13 _pcsr12.bit._D13 +#define PCSR12_D14 _pcsr12.bit._D14 +#define PCSR12_D15 _pcsr12.bit._D15 +#define PCSR12_D _pcsr12.bitc._D +__IO_EXTENDED PDUT12STR _pdut12; +#define PDUT12 _pdut12.word +#define PDUT12_D0 _pdut12.bit._D0 +#define PDUT12_D1 _pdut12.bit._D1 +#define PDUT12_D2 _pdut12.bit._D2 +#define PDUT12_D3 _pdut12.bit._D3 +#define PDUT12_D4 _pdut12.bit._D4 +#define PDUT12_D5 _pdut12.bit._D5 +#define PDUT12_D6 _pdut12.bit._D6 +#define PDUT12_D7 _pdut12.bit._D7 +#define PDUT12_D8 _pdut12.bit._D8 +#define PDUT12_D9 _pdut12.bit._D9 +#define PDUT12_D10 _pdut12.bit._D10 +#define PDUT12_D11 _pdut12.bit._D11 +#define PDUT12_D12 _pdut12.bit._D12 +#define PDUT12_D13 _pdut12.bit._D13 +#define PDUT12_D14 _pdut12.bit._D14 +#define PDUT12_D15 _pdut12.bit._D15 +#define PDUT12_D _pdut12.bitc._D +__IO_EXTENDED PCN12STR _pcn12; +#define PCN12 _pcn12.word +#define PCN12_OSEL _pcn12.bit._OSEL +#define PCN12_OE _pcn12.bit._OE +#define PCN12_IRS0 _pcn12.bit._IRS0 +#define PCN12_IRS1 _pcn12.bit._IRS1 +#define PCN12_IRQF _pcn12.bit._IRQF +#define PCN12_IREN _pcn12.bit._IREN +#define PCN12_EGS0 _pcn12.bit._EGS0 +#define PCN12_EGS1 _pcn12.bit._EGS1 +#define PCN12_PGMS _pcn12.bit._PGMS +#define PCN12_CKS0 _pcn12.bit._CKS0 +#define PCN12_CKS1 _pcn12.bit._CKS1 +#define PCN12_RTRG _pcn12.bit._RTRG +#define PCN12_MDSE _pcn12.bit._MDSE +#define PCN12_STGR _pcn12.bit._STGR +#define PCN12_CNTE _pcn12.bit._CNTE +#define PCN12_IRS _pcn12.bitc._IRS +#define PCN12_EGS _pcn12.bitc._EGS +#define PCN12_CKS _pcn12.bitc._CKS +__IO_EXTENDED PCNL12STR _pcnl12; +#define PCNL12 _pcnl12.byte +#define PCNL12_OSEL _pcnl12.bit._OSEL +#define PCNL12_OE _pcnl12.bit._OE +#define PCNL12_IRS0 _pcnl12.bit._IRS0 +#define PCNL12_IRS1 _pcnl12.bit._IRS1 +#define PCNL12_IRQF _pcnl12.bit._IRQF +#define PCNL12_IREN _pcnl12.bit._IREN +#define PCNL12_EGS0 _pcnl12.bit._EGS0 +#define PCNL12_EGS1 _pcnl12.bit._EGS1 +#define PCNL12_IRS _pcnl12.bitc._IRS +#define PCNL12_EGS _pcnl12.bitc._EGS +__IO_EXTENDED PCNH12STR _pcnh12; +#define PCNH12 _pcnh12.byte +#define PCNH12_PGMS _pcnh12.bit._PGMS +#define PCNH12_CKS0 _pcnh12.bit._CKS0 +#define PCNH12_CKS1 _pcnh12.bit._CKS1 +#define PCNH12_RTRG _pcnh12.bit._RTRG +#define PCNH12_MDSE _pcnh12.bit._MDSE +#define PCNH12_STGR _pcnh12.bit._STGR +#define PCNH12_CNTE _pcnh12.bit._CNTE +#define PCNH12_CKS _pcnh12.bitc._CKS +__IO_EXTENDED PTMR13STR _ptmr13; +#define PTMR13 _ptmr13.word +#define PTMR13_D0 _ptmr13.bit._D0 +#define PTMR13_D1 _ptmr13.bit._D1 +#define PTMR13_D2 _ptmr13.bit._D2 +#define PTMR13_D3 _ptmr13.bit._D3 +#define PTMR13_D4 _ptmr13.bit._D4 +#define PTMR13_D5 _ptmr13.bit._D5 +#define PTMR13_D6 _ptmr13.bit._D6 +#define PTMR13_D7 _ptmr13.bit._D7 +#define PTMR13_D8 _ptmr13.bit._D8 +#define PTMR13_D9 _ptmr13.bit._D9 +#define PTMR13_D10 _ptmr13.bit._D10 +#define PTMR13_D11 _ptmr13.bit._D11 +#define PTMR13_D12 _ptmr13.bit._D12 +#define PTMR13_D13 _ptmr13.bit._D13 +#define PTMR13_D14 _ptmr13.bit._D14 +#define PTMR13_D15 _ptmr13.bit._D15 +#define PTMR13_D _ptmr13.bitc._D +__IO_EXTENDED PCSR13STR _pcsr13; +#define PCSR13 _pcsr13.word +#define PCSR13_D0 _pcsr13.bit._D0 +#define PCSR13_D1 _pcsr13.bit._D1 +#define PCSR13_D2 _pcsr13.bit._D2 +#define PCSR13_D3 _pcsr13.bit._D3 +#define PCSR13_D4 _pcsr13.bit._D4 +#define PCSR13_D5 _pcsr13.bit._D5 +#define PCSR13_D6 _pcsr13.bit._D6 +#define PCSR13_D7 _pcsr13.bit._D7 +#define PCSR13_D8 _pcsr13.bit._D8 +#define PCSR13_D9 _pcsr13.bit._D9 +#define PCSR13_D10 _pcsr13.bit._D10 +#define PCSR13_D11 _pcsr13.bit._D11 +#define PCSR13_D12 _pcsr13.bit._D12 +#define PCSR13_D13 _pcsr13.bit._D13 +#define PCSR13_D14 _pcsr13.bit._D14 +#define PCSR13_D15 _pcsr13.bit._D15 +#define PCSR13_D _pcsr13.bitc._D +__IO_EXTENDED PDUT13STR _pdut13; +#define PDUT13 _pdut13.word +#define PDUT13_D0 _pdut13.bit._D0 +#define PDUT13_D1 _pdut13.bit._D1 +#define PDUT13_D2 _pdut13.bit._D2 +#define PDUT13_D3 _pdut13.bit._D3 +#define PDUT13_D4 _pdut13.bit._D4 +#define PDUT13_D5 _pdut13.bit._D5 +#define PDUT13_D6 _pdut13.bit._D6 +#define PDUT13_D7 _pdut13.bit._D7 +#define PDUT13_D8 _pdut13.bit._D8 +#define PDUT13_D9 _pdut13.bit._D9 +#define PDUT13_D10 _pdut13.bit._D10 +#define PDUT13_D11 _pdut13.bit._D11 +#define PDUT13_D12 _pdut13.bit._D12 +#define PDUT13_D13 _pdut13.bit._D13 +#define PDUT13_D14 _pdut13.bit._D14 +#define PDUT13_D15 _pdut13.bit._D15 +#define PDUT13_D _pdut13.bitc._D +__IO_EXTENDED PCN13STR _pcn13; +#define PCN13 _pcn13.word +#define PCN13_OSEL _pcn13.bit._OSEL +#define PCN13_OE _pcn13.bit._OE +#define PCN13_IRS0 _pcn13.bit._IRS0 +#define PCN13_IRS1 _pcn13.bit._IRS1 +#define PCN13_IRQF _pcn13.bit._IRQF +#define PCN13_IREN _pcn13.bit._IREN +#define PCN13_EGS0 _pcn13.bit._EGS0 +#define PCN13_EGS1 _pcn13.bit._EGS1 +#define PCN13_PGMS _pcn13.bit._PGMS +#define PCN13_CKS0 _pcn13.bit._CKS0 +#define PCN13_CKS1 _pcn13.bit._CKS1 +#define PCN13_RTRG _pcn13.bit._RTRG +#define PCN13_MDSE _pcn13.bit._MDSE +#define PCN13_STGR _pcn13.bit._STGR +#define PCN13_CNTE _pcn13.bit._CNTE +#define PCN13_IRS _pcn13.bitc._IRS +#define PCN13_EGS _pcn13.bitc._EGS +#define PCN13_CKS _pcn13.bitc._CKS +__IO_EXTENDED PCNL13STR _pcnl13; +#define PCNL13 _pcnl13.byte +#define PCNL13_OSEL _pcnl13.bit._OSEL +#define PCNL13_OE _pcnl13.bit._OE +#define PCNL13_IRS0 _pcnl13.bit._IRS0 +#define PCNL13_IRS1 _pcnl13.bit._IRS1 +#define PCNL13_IRQF _pcnl13.bit._IRQF +#define PCNL13_IREN _pcnl13.bit._IREN +#define PCNL13_EGS0 _pcnl13.bit._EGS0 +#define PCNL13_EGS1 _pcnl13.bit._EGS1 +#define PCNL13_IRS _pcnl13.bitc._IRS +#define PCNL13_EGS _pcnl13.bitc._EGS +__IO_EXTENDED PCNH13STR _pcnh13; +#define PCNH13 _pcnh13.byte +#define PCNH13_PGMS _pcnh13.bit._PGMS +#define PCNH13_CKS0 _pcnh13.bit._CKS0 +#define PCNH13_CKS1 _pcnh13.bit._CKS1 +#define PCNH13_RTRG _pcnh13.bit._RTRG +#define PCNH13_MDSE _pcnh13.bit._MDSE +#define PCNH13_STGR _pcnh13.bit._STGR +#define PCNH13_CNTE _pcnh13.bit._CNTE +#define PCNH13_CKS _pcnh13.bitc._CKS +__IO_EXTENDED PTMR14STR _ptmr14; +#define PTMR14 _ptmr14.word +#define PTMR14_D0 _ptmr14.bit._D0 +#define PTMR14_D1 _ptmr14.bit._D1 +#define PTMR14_D2 _ptmr14.bit._D2 +#define PTMR14_D3 _ptmr14.bit._D3 +#define PTMR14_D4 _ptmr14.bit._D4 +#define PTMR14_D5 _ptmr14.bit._D5 +#define PTMR14_D6 _ptmr14.bit._D6 +#define PTMR14_D7 _ptmr14.bit._D7 +#define PTMR14_D8 _ptmr14.bit._D8 +#define PTMR14_D9 _ptmr14.bit._D9 +#define PTMR14_D10 _ptmr14.bit._D10 +#define PTMR14_D11 _ptmr14.bit._D11 +#define PTMR14_D12 _ptmr14.bit._D12 +#define PTMR14_D13 _ptmr14.bit._D13 +#define PTMR14_D14 _ptmr14.bit._D14 +#define PTMR14_D15 _ptmr14.bit._D15 +#define PTMR14_D _ptmr14.bitc._D +__IO_EXTENDED PCSR14STR _pcsr14; +#define PCSR14 _pcsr14.word +#define PCSR14_D0 _pcsr14.bit._D0 +#define PCSR14_D1 _pcsr14.bit._D1 +#define PCSR14_D2 _pcsr14.bit._D2 +#define PCSR14_D3 _pcsr14.bit._D3 +#define PCSR14_D4 _pcsr14.bit._D4 +#define PCSR14_D5 _pcsr14.bit._D5 +#define PCSR14_D6 _pcsr14.bit._D6 +#define PCSR14_D7 _pcsr14.bit._D7 +#define PCSR14_D8 _pcsr14.bit._D8 +#define PCSR14_D9 _pcsr14.bit._D9 +#define PCSR14_D10 _pcsr14.bit._D10 +#define PCSR14_D11 _pcsr14.bit._D11 +#define PCSR14_D12 _pcsr14.bit._D12 +#define PCSR14_D13 _pcsr14.bit._D13 +#define PCSR14_D14 _pcsr14.bit._D14 +#define PCSR14_D15 _pcsr14.bit._D15 +#define PCSR14_D _pcsr14.bitc._D +__IO_EXTENDED PDUT14STR _pdut14; +#define PDUT14 _pdut14.word +#define PDUT14_D0 _pdut14.bit._D0 +#define PDUT14_D1 _pdut14.bit._D1 +#define PDUT14_D2 _pdut14.bit._D2 +#define PDUT14_D3 _pdut14.bit._D3 +#define PDUT14_D4 _pdut14.bit._D4 +#define PDUT14_D5 _pdut14.bit._D5 +#define PDUT14_D6 _pdut14.bit._D6 +#define PDUT14_D7 _pdut14.bit._D7 +#define PDUT14_D8 _pdut14.bit._D8 +#define PDUT14_D9 _pdut14.bit._D9 +#define PDUT14_D10 _pdut14.bit._D10 +#define PDUT14_D11 _pdut14.bit._D11 +#define PDUT14_D12 _pdut14.bit._D12 +#define PDUT14_D13 _pdut14.bit._D13 +#define PDUT14_D14 _pdut14.bit._D14 +#define PDUT14_D15 _pdut14.bit._D15 +#define PDUT14_D _pdut14.bitc._D +__IO_EXTENDED PCN14STR _pcn14; +#define PCN14 _pcn14.word +#define PCN14_OSEL _pcn14.bit._OSEL +#define PCN14_OE _pcn14.bit._OE +#define PCN14_IRS0 _pcn14.bit._IRS0 +#define PCN14_IRS1 _pcn14.bit._IRS1 +#define PCN14_IRQF _pcn14.bit._IRQF +#define PCN14_IREN _pcn14.bit._IREN +#define PCN14_EGS0 _pcn14.bit._EGS0 +#define PCN14_EGS1 _pcn14.bit._EGS1 +#define PCN14_PGMS _pcn14.bit._PGMS +#define PCN14_CKS0 _pcn14.bit._CKS0 +#define PCN14_CKS1 _pcn14.bit._CKS1 +#define PCN14_RTRG _pcn14.bit._RTRG +#define PCN14_MDSE _pcn14.bit._MDSE +#define PCN14_STGR _pcn14.bit._STGR +#define PCN14_CNTE _pcn14.bit._CNTE +#define PCN14_IRS _pcn14.bitc._IRS +#define PCN14_EGS _pcn14.bitc._EGS +#define PCN14_CKS _pcn14.bitc._CKS +__IO_EXTENDED PCNL14STR _pcnl14; +#define PCNL14 _pcnl14.byte +#define PCNL14_OSEL _pcnl14.bit._OSEL +#define PCNL14_OE _pcnl14.bit._OE +#define PCNL14_IRS0 _pcnl14.bit._IRS0 +#define PCNL14_IRS1 _pcnl14.bit._IRS1 +#define PCNL14_IRQF _pcnl14.bit._IRQF +#define PCNL14_IREN _pcnl14.bit._IREN +#define PCNL14_EGS0 _pcnl14.bit._EGS0 +#define PCNL14_EGS1 _pcnl14.bit._EGS1 +#define PCNL14_IRS _pcnl14.bitc._IRS +#define PCNL14_EGS _pcnl14.bitc._EGS +__IO_EXTENDED PCNH14STR _pcnh14; +#define PCNH14 _pcnh14.byte +#define PCNH14_PGMS _pcnh14.bit._PGMS +#define PCNH14_CKS0 _pcnh14.bit._CKS0 +#define PCNH14_CKS1 _pcnh14.bit._CKS1 +#define PCNH14_RTRG _pcnh14.bit._RTRG +#define PCNH14_MDSE _pcnh14.bit._MDSE +#define PCNH14_STGR _pcnh14.bit._STGR +#define PCNH14_CNTE _pcnh14.bit._CNTE +#define PCNH14_CKS _pcnh14.bitc._CKS +__IO_EXTENDED PTMR15STR _ptmr15; +#define PTMR15 _ptmr15.word +#define PTMR15_D0 _ptmr15.bit._D0 +#define PTMR15_D1 _ptmr15.bit._D1 +#define PTMR15_D2 _ptmr15.bit._D2 +#define PTMR15_D3 _ptmr15.bit._D3 +#define PTMR15_D4 _ptmr15.bit._D4 +#define PTMR15_D5 _ptmr15.bit._D5 +#define PTMR15_D6 _ptmr15.bit._D6 +#define PTMR15_D7 _ptmr15.bit._D7 +#define PTMR15_D8 _ptmr15.bit._D8 +#define PTMR15_D9 _ptmr15.bit._D9 +#define PTMR15_D10 _ptmr15.bit._D10 +#define PTMR15_D11 _ptmr15.bit._D11 +#define PTMR15_D12 _ptmr15.bit._D12 +#define PTMR15_D13 _ptmr15.bit._D13 +#define PTMR15_D14 _ptmr15.bit._D14 +#define PTMR15_D15 _ptmr15.bit._D15 +#define PTMR15_D _ptmr15.bitc._D +__IO_EXTENDED PCSR15STR _pcsr15; +#define PCSR15 _pcsr15.word +#define PCSR15_D0 _pcsr15.bit._D0 +#define PCSR15_D1 _pcsr15.bit._D1 +#define PCSR15_D2 _pcsr15.bit._D2 +#define PCSR15_D3 _pcsr15.bit._D3 +#define PCSR15_D4 _pcsr15.bit._D4 +#define PCSR15_D5 _pcsr15.bit._D5 +#define PCSR15_D6 _pcsr15.bit._D6 +#define PCSR15_D7 _pcsr15.bit._D7 +#define PCSR15_D8 _pcsr15.bit._D8 +#define PCSR15_D9 _pcsr15.bit._D9 +#define PCSR15_D10 _pcsr15.bit._D10 +#define PCSR15_D11 _pcsr15.bit._D11 +#define PCSR15_D12 _pcsr15.bit._D12 +#define PCSR15_D13 _pcsr15.bit._D13 +#define PCSR15_D14 _pcsr15.bit._D14 +#define PCSR15_D15 _pcsr15.bit._D15 +#define PCSR15_D _pcsr15.bitc._D +__IO_EXTENDED PDUT15STR _pdut15; +#define PDUT15 _pdut15.word +#define PDUT15_D0 _pdut15.bit._D0 +#define PDUT15_D1 _pdut15.bit._D1 +#define PDUT15_D2 _pdut15.bit._D2 +#define PDUT15_D3 _pdut15.bit._D3 +#define PDUT15_D4 _pdut15.bit._D4 +#define PDUT15_D5 _pdut15.bit._D5 +#define PDUT15_D6 _pdut15.bit._D6 +#define PDUT15_D7 _pdut15.bit._D7 +#define PDUT15_D8 _pdut15.bit._D8 +#define PDUT15_D9 _pdut15.bit._D9 +#define PDUT15_D10 _pdut15.bit._D10 +#define PDUT15_D11 _pdut15.bit._D11 +#define PDUT15_D12 _pdut15.bit._D12 +#define PDUT15_D13 _pdut15.bit._D13 +#define PDUT15_D14 _pdut15.bit._D14 +#define PDUT15_D15 _pdut15.bit._D15 +#define PDUT15_D _pdut15.bitc._D +__IO_EXTENDED PCN15STR _pcn15; +#define PCN15 _pcn15.word +#define PCN15_OSEL _pcn15.bit._OSEL +#define PCN15_OE _pcn15.bit._OE +#define PCN15_IRS0 _pcn15.bit._IRS0 +#define PCN15_IRS1 _pcn15.bit._IRS1 +#define PCN15_IRQF _pcn15.bit._IRQF +#define PCN15_IREN _pcn15.bit._IREN +#define PCN15_EGS0 _pcn15.bit._EGS0 +#define PCN15_EGS1 _pcn15.bit._EGS1 +#define PCN15_PGMS _pcn15.bit._PGMS +#define PCN15_CKS0 _pcn15.bit._CKS0 +#define PCN15_CKS1 _pcn15.bit._CKS1 +#define PCN15_RTRG _pcn15.bit._RTRG +#define PCN15_MDSE _pcn15.bit._MDSE +#define PCN15_STGR _pcn15.bit._STGR +#define PCN15_CNTE _pcn15.bit._CNTE +#define PCN15_IRS _pcn15.bitc._IRS +#define PCN15_EGS _pcn15.bitc._EGS +#define PCN15_CKS _pcn15.bitc._CKS +__IO_EXTENDED PCNL15STR _pcnl15; +#define PCNL15 _pcnl15.byte +#define PCNL15_OSEL _pcnl15.bit._OSEL +#define PCNL15_OE _pcnl15.bit._OE +#define PCNL15_IRS0 _pcnl15.bit._IRS0 +#define PCNL15_IRS1 _pcnl15.bit._IRS1 +#define PCNL15_IRQF _pcnl15.bit._IRQF +#define PCNL15_IREN _pcnl15.bit._IREN +#define PCNL15_EGS0 _pcnl15.bit._EGS0 +#define PCNL15_EGS1 _pcnl15.bit._EGS1 +#define PCNL15_IRS _pcnl15.bitc._IRS +#define PCNL15_EGS _pcnl15.bitc._EGS +__IO_EXTENDED PCNH15STR _pcnh15; +#define PCNH15 _pcnh15.byte +#define PCNH15_PGMS _pcnh15.bit._PGMS +#define PCNH15_CKS0 _pcnh15.bit._CKS0 +#define PCNH15_CKS1 _pcnh15.bit._CKS1 +#define PCNH15_RTRG _pcnh15.bit._RTRG +#define PCNH15_MDSE _pcnh15.bit._MDSE +#define PCNH15_STGR _pcnh15.bit._STGR +#define PCNH15_CNTE _pcnh15.bit._CNTE +#define PCNH15_CKS _pcnh15.bitc._CKS +__IO_EXTENDED PRRR10STR _prrr10; +#define PRRR10 _prrr10.byte +#define PRRR10_PPG8_R _prrr10.bit._PPG8_R +#define PRRR10_PPG9_R _prrr10.bit._PPG9_R +#define PRRR10_PPG10_R _prrr10.bit._PPG10_R +#define PRRR10_PPG11_R _prrr10.bit._PPG11_R +#define PRRR10_TTG8_R _prrr10.bit._TTG8_R +#define PRRR10_TTG9_R _prrr10.bit._TTG9_R +#define PRRR10_TTG10_R _prrr10.bit._TTG10_R +#define PRRR10_TTG11_R _prrr10.bit._TTG11_R +__IO_EXTENDED PRRR11STR _prrr11; +#define PRRR11 _prrr11.byte +#define PRRR11_PPG16_R _prrr11.bit._PPG16_R +#define PRRR11_PPG17_R _prrr11.bit._PPG17_R +#define PRRR11_PPG18_R _prrr11.bit._PPG18_R +#define PRRR11_PPG19_R _prrr11.bit._PPG19_R +#define PRRR11_TTG16_R _prrr11.bit._TTG16_R +#define PRRR11_TTG17_R _prrr11.bit._TTG17_R +#define PRRR11_TTG18_R _prrr11.bit._TTG18_R +#define PRRR11_TTG19_R _prrr11.bit._TTG19_R +__IO_EXTENDED PRRR12STR _prrr12; +#define PRRR12 _prrr12.byte +#define PRRR12_CS0_R _prrr12.bit._CS0_R +#define PRRR12_CS1_R _prrr12.bit._CS1_R +#define PRRR12_CS2_R _prrr12.bit._CS2_R +#define PRRR12_CS4_R _prrr12.bit._CS4_R +#define PRRR12_CS5_R _prrr12.bit._CS5_R +__IO_EXTENDED PRRR13STR _prrr13; +#define PRRR13 _prrr13.byte +__IO_EXTENDED EAC0STR _eac0; +#define EAC0 _eac0.word +#define EAC0_R0 _eac0.bit._R0 +#define EAC0_R1 _eac0.bit._R1 +#define EAC0_R2 _eac0.bit._R2 +#define EAC0_ACE _eac0.bit._ACE +#define EAC0_STS _eac0.bit._STS +#define EAC0_WSF _eac0.bit._WSF +#define EAC0_ES _eac0.bit._ES +#define EAC0_BW _eac0.bit._BW +#define EAC0_CSE _eac0.bit._CSE +#define EAC0_CSL _eac0.bit._CSL +#define EAC0_ATL _eac0.bit._ATL +#define EAC0_R _eac0.bitc._R +__IO_EXTENDED EACL0STR _eacl0; +#define EACL0 _eacl0.byte +#define EACL0_R0 _eacl0.bit._R0 +#define EACL0_R1 _eacl0.bit._R1 +#define EACL0_R2 _eacl0.bit._R2 +#define EACL0_ACE _eacl0.bit._ACE +#define EACL0_STS _eacl0.bit._STS +#define EACL0_WSF _eacl0.bit._WSF +#define EACL0_ES _eacl0.bit._ES +#define EACL0_BW _eacl0.bit._BW +#define EACL0_R _eacl0.bitc._R +__IO_EXTENDED EACH0STR _each0; +#define EACH0 _each0.byte +#define EACH0_CSE _each0.bit._CSE +#define EACH0_CSL _each0.bit._CSL +#define EACH0_ATL _each0.bit._ATL +__IO_EXTENDED EAC1STR _eac1; +#define EAC1 _eac1.word +#define EAC1_R0 _eac1.bit._R0 +#define EAC1_R1 _eac1.bit._R1 +#define EAC1_R2 _eac1.bit._R2 +#define EAC1_ACE _eac1.bit._ACE +#define EAC1_STS _eac1.bit._STS +#define EAC1_WSF _eac1.bit._WSF +#define EAC1_ES _eac1.bit._ES +#define EAC1_BW _eac1.bit._BW +#define EAC1_CSE _eac1.bit._CSE +#define EAC1_CSL _eac1.bit._CSL +#define EAC1_ATL _eac1.bit._ATL +#define EAC1_R _eac1.bitc._R +__IO_EXTENDED EACL1STR _eacl1; +#define EACL1 _eacl1.byte +#define EACL1_R0 _eacl1.bit._R0 +#define EACL1_R1 _eacl1.bit._R1 +#define EACL1_R2 _eacl1.bit._R2 +#define EACL1_ACE _eacl1.bit._ACE +#define EACL1_STS _eacl1.bit._STS +#define EACL1_WSF _eacl1.bit._WSF +#define EACL1_ES _eacl1.bit._ES +#define EACL1_BW _eacl1.bit._BW +#define EACL1_R _eacl1.bitc._R +__IO_EXTENDED EACH1STR _each1; +#define EACH1 _each1.byte +#define EACH1_CSE _each1.bit._CSE +#define EACH1_CSL _each1.bit._CSL +#define EACH1_ATL _each1.bit._ATL +__IO_EXTENDED EAC2STR _eac2; +#define EAC2 _eac2.word +#define EAC2_R0 _eac2.bit._R0 +#define EAC2_R1 _eac2.bit._R1 +#define EAC2_R2 _eac2.bit._R2 +#define EAC2_ACE _eac2.bit._ACE +#define EAC2_STS _eac2.bit._STS +#define EAC2_WSF _eac2.bit._WSF +#define EAC2_ES _eac2.bit._ES +#define EAC2_BW _eac2.bit._BW +#define EAC2_EASZ0 _eac2.bit._EASZ0 +#define EAC2_EASZ1 _eac2.bit._EASZ1 +#define EAC2_EASZ2 _eac2.bit._EASZ2 +#define EAC2_CSE _eac2.bit._CSE +#define EAC2_CSL _eac2.bit._CSL +#define EAC2_ATL _eac2.bit._ATL +#define EAC2_R _eac2.bitc._R +#define EAC2_EASZ _eac2.bitc._EASZ +__IO_EXTENDED EACL2STR _eacl2; +#define EACL2 _eacl2.byte +#define EACL2_R0 _eacl2.bit._R0 +#define EACL2_R1 _eacl2.bit._R1 +#define EACL2_R2 _eacl2.bit._R2 +#define EACL2_ACE _eacl2.bit._ACE +#define EACL2_STS _eacl2.bit._STS +#define EACL2_WSF _eacl2.bit._WSF +#define EACL2_ES _eacl2.bit._ES +#define EACL2_BW _eacl2.bit._BW +#define EACL2_R _eacl2.bitc._R +__IO_EXTENDED EACH2STR _each2; +#define EACH2 _each2.byte +#define EACH2_EASZ0 _each2.bit._EASZ0 +#define EACH2_EASZ1 _each2.bit._EASZ1 +#define EACH2_EASZ2 _each2.bit._EASZ2 +#define EACH2_CSE _each2.bit._CSE +#define EACH2_CSL _each2.bit._CSL +#define EACH2_ATL _each2.bit._ATL +#define EACH2_EASZ _each2.bitc._EASZ +__IO_EXTENDED EAC3STR _eac3; +#define EAC3 _eac3.word +#define EAC3_R0 _eac3.bit._R0 +#define EAC3_R1 _eac3.bit._R1 +#define EAC3_R2 _eac3.bit._R2 +#define EAC3_ACE _eac3.bit._ACE +#define EAC3_STS _eac3.bit._STS +#define EAC3_WSF _eac3.bit._WSF +#define EAC3_ES _eac3.bit._ES +#define EAC3_BW _eac3.bit._BW +#define EAC3_EASZ0 _eac3.bit._EASZ0 +#define EAC3_EASZ1 _eac3.bit._EASZ1 +#define EAC3_EASZ2 _eac3.bit._EASZ2 +#define EAC3_CSE _eac3.bit._CSE +#define EAC3_CSL _eac3.bit._CSL +#define EAC3_ATL _eac3.bit._ATL +#define EAC3_R _eac3.bitc._R +#define EAC3_EASZ _eac3.bitc._EASZ +__IO_EXTENDED EACL3STR _eacl3; +#define EACL3 _eacl3.byte +#define EACL3_R0 _eacl3.bit._R0 +#define EACL3_R1 _eacl3.bit._R1 +#define EACL3_R2 _eacl3.bit._R2 +#define EACL3_ACE _eacl3.bit._ACE +#define EACL3_STS _eacl3.bit._STS +#define EACL3_WSF _eacl3.bit._WSF +#define EACL3_ES _eacl3.bit._ES +#define EACL3_BW _eacl3.bit._BW +#define EACL3_R _eacl3.bitc._R +__IO_EXTENDED EACH3STR _each3; +#define EACH3 _each3.byte +#define EACH3_EASZ0 _each3.bit._EASZ0 +#define EACH3_EASZ1 _each3.bit._EASZ1 +#define EACH3_EASZ2 _each3.bit._EASZ2 +#define EACH3_CSE _each3.bit._CSE +#define EACH3_CSL _each3.bit._CSL +#define EACH3_ATL _each3.bit._ATL +#define EACH3_EASZ _each3.bitc._EASZ +__IO_EXTENDED EAC4STR _eac4; +#define EAC4 _eac4.word +#define EAC4_R0 _eac4.bit._R0 +#define EAC4_R1 _eac4.bit._R1 +#define EAC4_R2 _eac4.bit._R2 +#define EAC4_ACE _eac4.bit._ACE +#define EAC4_STS _eac4.bit._STS +#define EAC4_WSF _eac4.bit._WSF +#define EAC4_ES _eac4.bit._ES +#define EAC4_BW _eac4.bit._BW +#define EAC4_EASZ0 _eac4.bit._EASZ0 +#define EAC4_EASZ1 _eac4.bit._EASZ1 +#define EAC4_EASZ2 _eac4.bit._EASZ2 +#define EAC4_CSE _eac4.bit._CSE +#define EAC4_CSL _eac4.bit._CSL +#define EAC4_ATL _eac4.bit._ATL +#define EAC4_R _eac4.bitc._R +#define EAC4_EASZ _eac4.bitc._EASZ +__IO_EXTENDED EACL4STR _eacl4; +#define EACL4 _eacl4.byte +#define EACL4_R0 _eacl4.bit._R0 +#define EACL4_R1 _eacl4.bit._R1 +#define EACL4_R2 _eacl4.bit._R2 +#define EACL4_ACE _eacl4.bit._ACE +#define EACL4_STS _eacl4.bit._STS +#define EACL4_WSF _eacl4.bit._WSF +#define EACL4_ES _eacl4.bit._ES +#define EACL4_BW _eacl4.bit._BW +#define EACL4_R _eacl4.bitc._R +__IO_EXTENDED EACH4STR _each4; +#define EACH4 _each4.byte +#define EACH4_EASZ0 _each4.bit._EASZ0 +#define EACH4_EASZ1 _each4.bit._EASZ1 +#define EACH4_EASZ2 _each4.bit._EASZ2 +#define EACH4_CSE _each4.bit._CSE +#define EACH4_CSL _each4.bit._CSL +#define EACH4_ATL _each4.bit._ATL +#define EACH4_EASZ _each4.bitc._EASZ +__IO_EXTENDED EAC5STR _eac5; +#define EAC5 _eac5.word +#define EAC5_R0 _eac5.bit._R0 +#define EAC5_R1 _eac5.bit._R1 +#define EAC5_R2 _eac5.bit._R2 +#define EAC5_ACE _eac5.bit._ACE +#define EAC5_STS _eac5.bit._STS +#define EAC5_WSF _eac5.bit._WSF +#define EAC5_ES _eac5.bit._ES +#define EAC5_BW _eac5.bit._BW +#define EAC5_EASZ0 _eac5.bit._EASZ0 +#define EAC5_EASZ1 _eac5.bit._EASZ1 +#define EAC5_EASZ2 _eac5.bit._EASZ2 +#define EAC5_CSE _eac5.bit._CSE +#define EAC5_CSL _eac5.bit._CSL +#define EAC5_ATL _eac5.bit._ATL +#define EAC5_R _eac5.bitc._R +#define EAC5_EASZ _eac5.bitc._EASZ +__IO_EXTENDED EACL5STR _eacl5; +#define EACL5 _eacl5.byte +#define EACL5_R0 _eacl5.bit._R0 +#define EACL5_R1 _eacl5.bit._R1 +#define EACL5_R2 _eacl5.bit._R2 +#define EACL5_ACE _eacl5.bit._ACE +#define EACL5_STS _eacl5.bit._STS +#define EACL5_WSF _eacl5.bit._WSF +#define EACL5_ES _eacl5.bit._ES +#define EACL5_BW _eacl5.bit._BW +#define EACL5_R _eacl5.bitc._R +__IO_EXTENDED EACH5STR _each5; +#define EACH5 _each5.byte +#define EACH5_EASZ0 _each5.bit._EASZ0 +#define EACH5_EASZ1 _each5.bit._EASZ1 +#define EACH5_EASZ2 _each5.bit._EASZ2 +#define EACH5_CSE _each5.bit._CSE +#define EACH5_CSL _each5.bit._CSL +#define EACH5_ATL _each5.bit._ATL +#define EACH5_EASZ _each5.bitc._EASZ +__IO_EXTENDED EAS2STR _eas2; +#define EAS2 _eas2.byte +#define EAS2_A0 _eas2.bit._A0 +#define EAS2_A1 _eas2.bit._A1 +#define EAS2_A2 _eas2.bit._A2 +#define EAS2_A3 _eas2.bit._A3 +#define EAS2_A4 _eas2.bit._A4 +#define EAS2_A5 _eas2.bit._A5 +#define EAS2_A6 _eas2.bit._A6 +#define EAS2_A7 _eas2.bit._A7 +#define EAS2_A _eas2.bitc._A +__IO_EXTENDED EAS3STR _eas3; +#define EAS3 _eas3.byte +#define EAS3_A0 _eas3.bit._A0 +#define EAS3_A1 _eas3.bit._A1 +#define EAS3_A2 _eas3.bit._A2 +#define EAS3_A3 _eas3.bit._A3 +#define EAS3_A4 _eas3.bit._A4 +#define EAS3_A5 _eas3.bit._A5 +#define EAS3_A6 _eas3.bit._A6 +#define EAS3_A7 _eas3.bit._A7 +#define EAS3_A _eas3.bitc._A +__IO_EXTENDED EAS4STR _eas4; +#define EAS4 _eas4.byte +#define EAS4_A0 _eas4.bit._A0 +#define EAS4_A1 _eas4.bit._A1 +#define EAS4_A2 _eas4.bit._A2 +#define EAS4_A3 _eas4.bit._A3 +#define EAS4_A4 _eas4.bit._A4 +#define EAS4_A5 _eas4.bit._A5 +#define EAS4_A6 _eas4.bit._A6 +#define EAS4_A7 _eas4.bit._A7 +#define EAS4_A _eas4.bitc._A +__IO_EXTENDED EAS5STR _eas5; +#define EAS5 _eas5.byte +#define EAS5_A0 _eas5.bit._A0 +#define EAS5_A1 _eas5.bit._A1 +#define EAS5_A2 _eas5.bit._A2 +#define EAS5_A3 _eas5.bit._A3 +#define EAS5_A4 _eas5.bit._A4 +#define EAS5_A5 _eas5.bit._A5 +#define EAS5_A6 _eas5.bit._A6 +#define EAS5_A7 _eas5.bit._A7 +__IO_EXTENDED EBMSTR _ebm; +#define EBM _ebm.byte +#define EBM_EAE0 _ebm.bit._EAE0 +#define EBM_EAE1 _ebm.bit._EAE1 +#define EBM_EAE2 _ebm.bit._EAE2 +#define EBM_EAE3 _ebm.bit._EAE3 +#define EBM_EAE4 _ebm.bit._EAE4 +#define EBM_EAE5 _ebm.bit._EAE5 +#define EBM_ERE _ebm.bit._ERE +#define EBM_NMS _ebm.bit._NMS +#define EBM_EAE _ebm.bitc._EAE +__IO_EXTENDED EBCFSTR _ebcf; +#define EBCF _ebcf.byte +#define EBCF_DIV0 _ebcf.bit._DIV0 +#define EBCF_DIV1 _ebcf.bit._DIV1 +#define EBCF_DIV2 _ebcf.bit._DIV2 +#define EBCF_CSM _ebcf.bit._CSM +#define EBCF_CKI _ebcf.bit._CKI +#define EBCF_CKE _ebcf.bit._CKE +#define EBCF_RYE _ebcf.bit._RYE +#define EBCF_HDE _ebcf.bit._HDE +#define EBCF_DIV _ebcf.bitc._DIV +__IO_EXTENDED EBAE0STR _ebae0; +#define EBAE0 _ebae0.byte +#define EBAE0_A00 _ebae0.bit._A00 +#define EBAE0_A01 _ebae0.bit._A01 +#define EBAE0_A02 _ebae0.bit._A02 +#define EBAE0_A03 _ebae0.bit._A03 +#define EBAE0_A04 _ebae0.bit._A04 +#define EBAE0_A05 _ebae0.bit._A05 +#define EBAE0_A06 _ebae0.bit._A06 +#define EBAE0_A07 _ebae0.bit._A07 +__IO_EXTENDED EBAE1STR _ebae1; +#define EBAE1 _ebae1.byte +#define EBAE1_A08 _ebae1.bit._A08 +#define EBAE1_A09 _ebae1.bit._A09 +#define EBAE1_A10 _ebae1.bit._A10 +#define EBAE1_A11 _ebae1.bit._A11 +#define EBAE1_A12 _ebae1.bit._A12 +#define EBAE1_A13 _ebae1.bit._A13 +#define EBAE1_A14 _ebae1.bit._A14 +#define EBAE1_A15 _ebae1.bit._A15 +__IO_EXTENDED EBAE2STR _ebae2; +#define EBAE2 _ebae2.byte +#define EBAE2_A16 _ebae2.bit._A16 +#define EBAE2_A17 _ebae2.bit._A17 +#define EBAE2_A18 _ebae2.bit._A18 +#define EBAE2_A19 _ebae2.bit._A19 +#define EBAE2_A20 _ebae2.bit._A20 +#define EBAE2_A21 _ebae2.bit._A21 +#define EBAE2_A22 _ebae2.bit._A22 +#define EBAE2_A23 _ebae2.bit._A23 +__IO_EXTENDED EBCSSTR _ebcs; +#define EBCS _ebcs.byte +#define EBCS_LBE _ebcs.bit._LBE +#define EBCS_UBE _ebcs.bit._UBE +#define EBCS_WRLE _ebcs.bit._WRLE +#define EBCS_WRHE _ebcs.bit._WRHE +#define EBCS_RDE _ebcs.bit._RDE +#define EBCS_ASE _ebcs.bit._ASE +#define EBCS_ASL _ebcs.bit._ASL +__IO_EXTENDED CTRLR0STR _ctrlr0; +#define CTRLR0 _ctrlr0.word +#define CTRLR0_INIT _ctrlr0.bit._INIT +#define CTRLR0_IE _ctrlr0.bit._IE +#define CTRLR0_SIE _ctrlr0.bit._SIE +#define CTRLR0_EIE _ctrlr0.bit._EIE +#define CTRLR0_DAR _ctrlr0.bit._DAR +#define CTRLR0_CCE _ctrlr0.bit._CCE +#define CTRLR0_TEST _ctrlr0.bit._TEST +__IO_EXTENDED CTRLRL0STR _ctrlrl0; +#define CTRLRL0 _ctrlrl0.byte +#define CTRLRL0_INIT _ctrlrl0.bit._INIT +#define CTRLRL0_IE _ctrlrl0.bit._IE +#define CTRLRL0_SIE _ctrlrl0.bit._SIE +#define CTRLRL0_EIE _ctrlrl0.bit._EIE +#define CTRLRL0_DAR _ctrlrl0.bit._DAR +#define CTRLRL0_CCE _ctrlrl0.bit._CCE +#define CTRLRL0_TEST _ctrlrl0.bit._TEST +__IO_EXTENDED CTRLRH0STR _ctrlrh0; +#define CTRLRH0 _ctrlrh0.byte +__IO_EXTENDED STATR0STR _statr0; +#define STATR0 _statr0.word +#define STATR0_LEC0 _statr0.bit._LEC0 +#define STATR0_LEC1 _statr0.bit._LEC1 +#define STATR0_LEC2 _statr0.bit._LEC2 +#define STATR0_TXOK _statr0.bit._TXOK +#define STATR0_RXOK _statr0.bit._RXOK +#define STATR0_EPASS _statr0.bit._EPASS +#define STATR0_EWARN _statr0.bit._EWARN +#define STATR0_BOFF _statr0.bit._BOFF +#define STATR0_LEC _statr0.bitc._LEC +__IO_EXTENDED STATRL0STR _statrl0; +#define STATRL0 _statrl0.byte +#define STATRL0_LEC0 _statrl0.bit._LEC0 +#define STATRL0_LEC1 _statrl0.bit._LEC1 +#define STATRL0_LEC2 _statrl0.bit._LEC2 +#define STATRL0_TXOK _statrl0.bit._TXOK +#define STATRL0_RXOK _statrl0.bit._RXOK +#define STATRL0_EPASS _statrl0.bit._EPASS +#define STATRL0_EWARN _statrl0.bit._EWARN +#define STATRL0_BOFF _statrl0.bit._BOFF +#define STATRL0_LEC _statrl0.bitc._LEC +__IO_EXTENDED STATRH0STR _statrh0; +#define STATRH0 _statrh0.byte +__IO_EXTENDED ERRCNT0STR _errcnt0; +#define ERRCNT0 _errcnt0.word +#define ERRCNT0_TEC0 _errcnt0.bit._TEC0 +#define ERRCNT0_TEC1 _errcnt0.bit._TEC1 +#define ERRCNT0_TEC2 _errcnt0.bit._TEC2 +#define ERRCNT0_TEC3 _errcnt0.bit._TEC3 +#define ERRCNT0_TEC4 _errcnt0.bit._TEC4 +#define ERRCNT0_TEC5 _errcnt0.bit._TEC5 +#define ERRCNT0_TEC6 _errcnt0.bit._TEC6 +#define ERRCNT0_TEC7 _errcnt0.bit._TEC7 +#define ERRCNT0_REC0 _errcnt0.bit._REC0 +#define ERRCNT0_REC1 _errcnt0.bit._REC1 +#define ERRCNT0_REC2 _errcnt0.bit._REC2 +#define ERRCNT0_REC3 _errcnt0.bit._REC3 +#define ERRCNT0_REC4 _errcnt0.bit._REC4 +#define ERRCNT0_REC5 _errcnt0.bit._REC5 +#define ERRCNT0_REC6 _errcnt0.bit._REC6 +#define ERRCNT0_RP _errcnt0.bit._RP +#define ERRCNT0_TEC _errcnt0.bitc._TEC +#define ERRCNT0_REC _errcnt0.bitc._REC +__IO_EXTENDED ERRCNTL0STR _errcntl0; +#define ERRCNTL0 _errcntl0.byte +#define ERRCNTL0_TEC0 _errcntl0.bit._TEC0 +#define ERRCNTL0_TEC1 _errcntl0.bit._TEC1 +#define ERRCNTL0_TEC2 _errcntl0.bit._TEC2 +#define ERRCNTL0_TEC3 _errcntl0.bit._TEC3 +#define ERRCNTL0_TEC4 _errcntl0.bit._TEC4 +#define ERRCNTL0_TEC5 _errcntl0.bit._TEC5 +#define ERRCNTL0_TEC6 _errcntl0.bit._TEC6 +#define ERRCNTL0_TEC7 _errcntl0.bit._TEC7 +#define ERRCNTL0_TEC _errcntl0.bitc._TEC +__IO_EXTENDED ERRCNTH0STR _errcnth0; +#define ERRCNTH0 _errcnth0.byte +#define ERRCNTH0_REC0 _errcnth0.bit._REC0 +#define ERRCNTH0_REC1 _errcnth0.bit._REC1 +#define ERRCNTH0_REC2 _errcnth0.bit._REC2 +#define ERRCNTH0_REC3 _errcnth0.bit._REC3 +#define ERRCNTH0_REC4 _errcnth0.bit._REC4 +#define ERRCNTH0_REC5 _errcnth0.bit._REC5 +#define ERRCNTH0_REC6 _errcnth0.bit._REC6 +#define ERRCNTH0_RP _errcnth0.bit._RP +#define ERRCNTH0_REC _errcnth0.bitc._REC +__IO_EXTENDED BTR0STR _btr0; +#define BTR0 _btr0.word +#define BTR0_BRP0 _btr0.bit._BRP0 +#define BTR0_BRP1 _btr0.bit._BRP1 +#define BTR0_BRP2 _btr0.bit._BRP2 +#define BTR0_BRP3 _btr0.bit._BRP3 +#define BTR0_BRP4 _btr0.bit._BRP4 +#define BTR0_BRP5 _btr0.bit._BRP5 +#define BTR0_SJW0 _btr0.bit._SJW0 +#define BTR0_SJW1 _btr0.bit._SJW1 +#define BTR0_TSEG10 _btr0.bit._TSEG10 +#define BTR0_TSEG11 _btr0.bit._TSEG11 +#define BTR0_TSEG12 _btr0.bit._TSEG12 +#define BTR0_TSEG13 _btr0.bit._TSEG13 +#define BTR0_TSEG20 _btr0.bit._TSEG20 +#define BTR0_TSEG21 _btr0.bit._TSEG21 +#define BTR0_TSEG22 _btr0.bit._TSEG22 +#define BTR0_BRP _btr0.bitc._BRP +#define BTR0_SJW _btr0.bitc._SJW +#define BTR0_TSEG1 _btr0.bitc._TSEG1 +#define BTR0_TSEG2 _btr0.bitc._TSEG2 +__IO_EXTENDED BTRL0STR _btrl0; +#define BTRL0 _btrl0.byte +#define BTRL0_BRP0 _btrl0.bit._BRP0 +#define BTRL0_BRP1 _btrl0.bit._BRP1 +#define BTRL0_BRP2 _btrl0.bit._BRP2 +#define BTRL0_BRP3 _btrl0.bit._BRP3 +#define BTRL0_BRP4 _btrl0.bit._BRP4 +#define BTRL0_BRP5 _btrl0.bit._BRP5 +#define BTRL0_SJW0 _btrl0.bit._SJW0 +#define BTRL0_SJW1 _btrl0.bit._SJW1 +#define BTRL0_BRP _btrl0.bitc._BRP +#define BTRL0_SJW _btrl0.bitc._SJW +__IO_EXTENDED BTRH0STR _btrh0; +#define BTRH0 _btrh0.byte +#define BTRH0_TSEG10 _btrh0.bit._TSEG10 +#define BTRH0_TSEG11 _btrh0.bit._TSEG11 +#define BTRH0_TSEG12 _btrh0.bit._TSEG12 +#define BTRH0_TSEG13 _btrh0.bit._TSEG13 +#define BTRH0_TSEG20 _btrh0.bit._TSEG20 +#define BTRH0_TSEG21 _btrh0.bit._TSEG21 +#define BTRH0_TSEG22 _btrh0.bit._TSEG22 +#define BTRH0_TSEG1 _btrh0.bitc._TSEG1 +#define BTRH0_TSEG2 _btrh0.bitc._TSEG2 +__IO_EXTENDED INTR0STR _intr0; +#define INTR0 _intr0.word +#define INTR0_INTID0 _intr0.bit._INTID0 +#define INTR0_INTID1 _intr0.bit._INTID1 +#define INTR0_INTID2 _intr0.bit._INTID2 +#define INTR0_INTID3 _intr0.bit._INTID3 +#define INTR0_INTID4 _intr0.bit._INTID4 +#define INTR0_INTID5 _intr0.bit._INTID5 +#define INTR0_INTID6 _intr0.bit._INTID6 +#define INTR0_INTID7 _intr0.bit._INTID7 +#define INTR0_INTID8 _intr0.bit._INTID8 +#define INTR0_INTID9 _intr0.bit._INTID9 +#define INTR0_INTID10 _intr0.bit._INTID10 +#define INTR0_INTID11 _intr0.bit._INTID11 +#define INTR0_INTID12 _intr0.bit._INTID12 +#define INTR0_INTID13 _intr0.bit._INTID13 +#define INTR0_INTID14 _intr0.bit._INTID14 +#define INTR0_INTID15 _intr0.bit._INTID15 +#define INTR0_INTID _intr0.bitc._INTID +__IO_EXTENDED INTRL0STR _intrl0; +#define INTRL0 _intrl0.byte +#define INTRL0_INTID0 _intrl0.bit._INTID0 +#define INTRL0_INTID1 _intrl0.bit._INTID1 +#define INTRL0_INTID2 _intrl0.bit._INTID2 +#define INTRL0_INTID3 _intrl0.bit._INTID3 +#define INTRL0_INTID4 _intrl0.bit._INTID4 +#define INTRL0_INTID5 _intrl0.bit._INTID5 +#define INTRL0_INTID6 _intrl0.bit._INTID6 +#define INTRL0_INTID7 _intrl0.bit._INTID7 +__IO_EXTENDED INTRH0STR _intrh0; +#define INTRH0 _intrh0.byte +#define INTRH0_INTID8 _intrh0.bit._INTID8 +#define INTRH0_INTID9 _intrh0.bit._INTID9 +#define INTRH0_INTID10 _intrh0.bit._INTID10 +#define INTRH0_INTID11 _intrh0.bit._INTID11 +#define INTRH0_INTID12 _intrh0.bit._INTID12 +#define INTRH0_INTID13 _intrh0.bit._INTID13 +#define INTRH0_INTID14 _intrh0.bit._INTID14 +#define INTRH0_INTID15 _intrh0.bit._INTID15 +__IO_EXTENDED TESTR0STR _testr0; +#define TESTR0 _testr0.word +#define TESTR0_BASIC _testr0.bit._BASIC +#define TESTR0_SILENT _testr0.bit._SILENT +#define TESTR0_LBACK _testr0.bit._LBACK +#define TESTR0_TX0 _testr0.bit._TX0 +#define TESTR0_TX1 _testr0.bit._TX1 +#define TESTR0_RX _testr0.bit._RX +__IO_EXTENDED TESTRL0STR _testrl0; +#define TESTRL0 _testrl0.byte +#define TESTRL0_BASIC _testrl0.bit._BASIC +#define TESTRL0_SILENT _testrl0.bit._SILENT +#define TESTRL0_LBACK _testrl0.bit._LBACK +#define TESTRL0_TX0 _testrl0.bit._TX0 +#define TESTRL0_TX1 _testrl0.bit._TX1 +#define TESTRL0_RX _testrl0.bit._RX +__IO_EXTENDED TESTRH0STR _testrh0; +#define TESTRH0 _testrh0.byte +__IO_EXTENDED BRPER0STR _brper0; +#define BRPER0 _brper0.word +#define BRPER0_BRPE0 _brper0.bit._BRPE0 +#define BRPER0_BRPE1 _brper0.bit._BRPE1 +#define BRPER0_BRPE2 _brper0.bit._BRPE2 +#define BRPER0_BRPE3 _brper0.bit._BRPE3 +#define BRPER0_BRPE _brper0.bitc._BRPE +__IO_EXTENDED BRPERL0STR _brperl0; +#define BRPERL0 _brperl0.byte +#define BRPERL0_BRPE0 _brperl0.bit._BRPE0 +#define BRPERL0_BRPE1 _brperl0.bit._BRPE1 +#define BRPERL0_BRPE2 _brperl0.bit._BRPE2 +#define BRPERL0_BRPE3 _brperl0.bit._BRPE3 +#define BRPERL0_BRPE _brperl0.bitc._BRPE +__IO_EXTENDED BRPERH0STR _brperh0; +#define BRPERH0 _brperh0.byte +__IO_EXTENDED IF1CREQ0STR _if1creq0; +#define IF1CREQ0 _if1creq0.word +#define IF1CREQ0_MSGN0 _if1creq0.bit._MSGN0 +#define IF1CREQ0_MSGN1 _if1creq0.bit._MSGN1 +#define IF1CREQ0_MSGN2 _if1creq0.bit._MSGN2 +#define IF1CREQ0_MSGN3 _if1creq0.bit._MSGN3 +#define IF1CREQ0_MSGN4 _if1creq0.bit._MSGN4 +#define IF1CREQ0_MSGN5 _if1creq0.bit._MSGN5 +#define IF1CREQ0_MSGN6 _if1creq0.bit._MSGN6 +#define IF1CREQ0_MSGN7 _if1creq0.bit._MSGN7 +#define IF1CREQ0_BUSY _if1creq0.bit._BUSY +__IO_EXTENDED IF1CREQL0STR _if1creql0; +#define IF1CREQL0 _if1creql0.byte +#define IF1CREQL0_MSGN0 _if1creql0.bit._MSGN0 +#define IF1CREQL0_MSGN1 _if1creql0.bit._MSGN1 +#define IF1CREQL0_MSGN2 _if1creql0.bit._MSGN2 +#define IF1CREQL0_MSGN3 _if1creql0.bit._MSGN3 +#define IF1CREQL0_MSGN4 _if1creql0.bit._MSGN4 +#define IF1CREQL0_MSGN5 _if1creql0.bit._MSGN5 +#define IF1CREQL0_MSGN6 _if1creql0.bit._MSGN6 +#define IF1CREQL0_MSGN7 _if1creql0.bit._MSGN7 +__IO_EXTENDED IF1CREQH0STR _if1creqh0; +#define IF1CREQH0 _if1creqh0.byte +#define IF1CREQH0_BUSY _if1creqh0.bit._BUSY +__IO_EXTENDED IF1CMSK0STR _if1cmsk0; +#define IF1CMSK0 _if1cmsk0.word +#define IF1CMSK0_DATAB _if1cmsk0.bit._DATAB +#define IF1CMSK0_DATAA _if1cmsk0.bit._DATAA +#define IF1CMSK0_TXREQ _if1cmsk0.bit._TXREQ +#define IF1CMSK0_CIP _if1cmsk0.bit._CIP +#define IF1CMSK0_CONTROL _if1cmsk0.bit._CONTROL +#define IF1CMSK0_ARB _if1cmsk0.bit._ARB +#define IF1CMSK0_MASK _if1cmsk0.bit._MASK +#define IF1CMSK0_WRRD _if1cmsk0.bit._WRRD +__IO_EXTENDED IF1CMSKL0STR _if1cmskl0; +#define IF1CMSKL0 _if1cmskl0.byte +#define IF1CMSKL0_DATAB _if1cmskl0.bit._DATAB +#define IF1CMSKL0_DATAA _if1cmskl0.bit._DATAA +#define IF1CMSKL0_TXREQ _if1cmskl0.bit._TXREQ +#define IF1CMSKL0_CIP _if1cmskl0.bit._CIP +#define IF1CMSKL0_CONTROL _if1cmskl0.bit._CONTROL +#define IF1CMSKL0_ARB _if1cmskl0.bit._ARB +#define IF1CMSKL0_MASK _if1cmskl0.bit._MASK +#define IF1CMSKL0_WRRD _if1cmskl0.bit._WRRD +__IO_EXTENDED IF1CMSKH0STR _if1cmskh0; +#define IF1CMSKH0 _if1cmskh0.byte +__IO_EXTENDED IF1MSK0STR _if1msk0; +#define IF1MSK0 _if1msk0.lword +#define IF1MSK0_MSK0 _if1msk0.bit._MSK0 +#define IF1MSK0_MSK1 _if1msk0.bit._MSK1 +#define IF1MSK0_MSK2 _if1msk0.bit._MSK2 +#define IF1MSK0_MSK3 _if1msk0.bit._MSK3 +#define IF1MSK0_MSK4 _if1msk0.bit._MSK4 +#define IF1MSK0_MSK5 _if1msk0.bit._MSK5 +#define IF1MSK0_MSK6 _if1msk0.bit._MSK6 +#define IF1MSK0_MSK7 _if1msk0.bit._MSK7 +#define IF1MSK0_MSK8 _if1msk0.bit._MSK8 +#define IF1MSK0_MSK9 _if1msk0.bit._MSK9 +#define IF1MSK0_MSK10 _if1msk0.bit._MSK10 +#define IF1MSK0_MSK11 _if1msk0.bit._MSK11 +#define IF1MSK0_MSK12 _if1msk0.bit._MSK12 +#define IF1MSK0_MSK13 _if1msk0.bit._MSK13 +#define IF1MSK0_MSK14 _if1msk0.bit._MSK14 +#define IF1MSK0_MSK15 _if1msk0.bit._MSK15 +#define IF1MSK0_MSK16 _if1msk0.bit._MSK16 +#define IF1MSK0_MSK17 _if1msk0.bit._MSK17 +#define IF1MSK0_MSK18 _if1msk0.bit._MSK18 +#define IF1MSK0_MSK19 _if1msk0.bit._MSK19 +#define IF1MSK0_MSK20 _if1msk0.bit._MSK20 +#define IF1MSK0_MSK21 _if1msk0.bit._MSK21 +#define IF1MSK0_MSK22 _if1msk0.bit._MSK22 +#define IF1MSK0_MSK23 _if1msk0.bit._MSK23 +#define IF1MSK0_MSK24 _if1msk0.bit._MSK24 +#define IF1MSK0_MSK25 _if1msk0.bit._MSK25 +#define IF1MSK0_MSK26 _if1msk0.bit._MSK26 +#define IF1MSK0_MSK27 _if1msk0.bit._MSK27 +#define IF1MSK0_MSK28 _if1msk0.bit._MSK28 +#define IF1MSK0_MDIR _if1msk0.bit._MDIR +#define IF1MSK0_MXTD _if1msk0.bit._MXTD +#define IF1MSK0_MSK _if1msk0.bitc._MSK +__IO_EXTENDED IF1MSK10STR _if1msk10; +#define IF1MSK10 _if1msk10.word +#define IF1MSK10_MSK0 _if1msk10.bit._MSK0 +#define IF1MSK10_MSK1 _if1msk10.bit._MSK1 +#define IF1MSK10_MSK2 _if1msk10.bit._MSK2 +#define IF1MSK10_MSK3 _if1msk10.bit._MSK3 +#define IF1MSK10_MSK4 _if1msk10.bit._MSK4 +#define IF1MSK10_MSK5 _if1msk10.bit._MSK5 +#define IF1MSK10_MSK6 _if1msk10.bit._MSK6 +#define IF1MSK10_MSK7 _if1msk10.bit._MSK7 +#define IF1MSK10_MSK8 _if1msk10.bit._MSK8 +#define IF1MSK10_MSK9 _if1msk10.bit._MSK9 +#define IF1MSK10_MSK10 _if1msk10.bit._MSK10 +#define IF1MSK10_MSK11 _if1msk10.bit._MSK11 +#define IF1MSK10_MSK12 _if1msk10.bit._MSK12 +#define IF1MSK10_MSK13 _if1msk10.bit._MSK13 +#define IF1MSK10_MSK14 _if1msk10.bit._MSK14 +#define IF1MSK10_MSK15 _if1msk10.bit._MSK15 +__IO_EXTENDED IF1MSK1L0STR _if1msk1l0; +#define IF1MSK1L0 _if1msk1l0.byte +#define IF1MSK1L0_MSK0 _if1msk1l0.bit._MSK0 +#define IF1MSK1L0_MSK1 _if1msk1l0.bit._MSK1 +#define IF1MSK1L0_MSK2 _if1msk1l0.bit._MSK2 +#define IF1MSK1L0_MSK3 _if1msk1l0.bit._MSK3 +#define IF1MSK1L0_MSK4 _if1msk1l0.bit._MSK4 +#define IF1MSK1L0_MSK5 _if1msk1l0.bit._MSK5 +#define IF1MSK1L0_MSK6 _if1msk1l0.bit._MSK6 +#define IF1MSK1L0_MSK7 _if1msk1l0.bit._MSK7 +__IO_EXTENDED IF1MSK1H0STR _if1msk1h0; +#define IF1MSK1H0 _if1msk1h0.byte +#define IF1MSK1H0_MSK8 _if1msk1h0.bit._MSK8 +#define IF1MSK1H0_MSK9 _if1msk1h0.bit._MSK9 +#define IF1MSK1H0_MSK10 _if1msk1h0.bit._MSK10 +#define IF1MSK1H0_MSK11 _if1msk1h0.bit._MSK11 +#define IF1MSK1H0_MSK12 _if1msk1h0.bit._MSK12 +#define IF1MSK1H0_MSK13 _if1msk1h0.bit._MSK13 +#define IF1MSK1H0_MSK14 _if1msk1h0.bit._MSK14 +#define IF1MSK1H0_MSK15 _if1msk1h0.bit._MSK15 +__IO_EXTENDED IF1MSK20STR _if1msk20; +#define IF1MSK20 _if1msk20.word +#define IF1MSK20_MSK16 _if1msk20.bit._MSK16 +#define IF1MSK20_MSK17 _if1msk20.bit._MSK17 +#define IF1MSK20_MSK18 _if1msk20.bit._MSK18 +#define IF1MSK20_MSK19 _if1msk20.bit._MSK19 +#define IF1MSK20_MSK20 _if1msk20.bit._MSK20 +#define IF1MSK20_MSK21 _if1msk20.bit._MSK21 +#define IF1MSK20_MSK22 _if1msk20.bit._MSK22 +#define IF1MSK20_MSK23 _if1msk20.bit._MSK23 +#define IF1MSK20_MSK24 _if1msk20.bit._MSK24 +#define IF1MSK20_MSK25 _if1msk20.bit._MSK25 +#define IF1MSK20_MSK26 _if1msk20.bit._MSK26 +#define IF1MSK20_MSK27 _if1msk20.bit._MSK27 +#define IF1MSK20_MSK28 _if1msk20.bit._MSK28 +#define IF1MSK20_MDIR _if1msk20.bit._MDIR +#define IF1MSK20_MXTD _if1msk20.bit._MXTD +__IO_EXTENDED IF1MSK2L0STR _if1msk2l0; +#define IF1MSK2L0 _if1msk2l0.byte +#define IF1MSK2L0_MSK16 _if1msk2l0.bit._MSK16 +#define IF1MSK2L0_MSK17 _if1msk2l0.bit._MSK17 +#define IF1MSK2L0_MSK18 _if1msk2l0.bit._MSK18 +#define IF1MSK2L0_MSK19 _if1msk2l0.bit._MSK19 +#define IF1MSK2L0_MSK20 _if1msk2l0.bit._MSK20 +#define IF1MSK2L0_MSK21 _if1msk2l0.bit._MSK21 +#define IF1MSK2L0_MSK22 _if1msk2l0.bit._MSK22 +#define IF1MSK2L0_MSK23 _if1msk2l0.bit._MSK23 +__IO_EXTENDED IF1MSK2H0STR _if1msk2h0; +#define IF1MSK2H0 _if1msk2h0.byte +#define IF1MSK2H0_MSK24 _if1msk2h0.bit._MSK24 +#define IF1MSK2H0_MSK25 _if1msk2h0.bit._MSK25 +#define IF1MSK2H0_MSK26 _if1msk2h0.bit._MSK26 +#define IF1MSK2H0_MSK27 _if1msk2h0.bit._MSK27 +#define IF1MSK2H0_MSK28 _if1msk2h0.bit._MSK28 +#define IF1MSK2H0_MDIR _if1msk2h0.bit._MDIR +#define IF1MSK2H0_MXTD _if1msk2h0.bit._MXTD +__IO_EXTENDED IF1ARB0STR _if1arb0; +#define IF1ARB0 _if1arb0.lword +#define IF1ARB0_ID0 _if1arb0.bit._ID0 +#define IF1ARB0_ID1 _if1arb0.bit._ID1 +#define IF1ARB0_ID2 _if1arb0.bit._ID2 +#define IF1ARB0_ID3 _if1arb0.bit._ID3 +#define IF1ARB0_ID4 _if1arb0.bit._ID4 +#define IF1ARB0_ID5 _if1arb0.bit._ID5 +#define IF1ARB0_ID6 _if1arb0.bit._ID6 +#define IF1ARB0_ID7 _if1arb0.bit._ID7 +#define IF1ARB0_ID8 _if1arb0.bit._ID8 +#define IF1ARB0_ID9 _if1arb0.bit._ID9 +#define IF1ARB0_ID10 _if1arb0.bit._ID10 +#define IF1ARB0_ID11 _if1arb0.bit._ID11 +#define IF1ARB0_ID12 _if1arb0.bit._ID12 +#define IF1ARB0_ID13 _if1arb0.bit._ID13 +#define IF1ARB0_ID14 _if1arb0.bit._ID14 +#define IF1ARB0_ID15 _if1arb0.bit._ID15 +#define IF1ARB0_ID16 _if1arb0.bit._ID16 +#define IF1ARB0_ID17 _if1arb0.bit._ID17 +#define IF1ARB0_ID18 _if1arb0.bit._ID18 +#define IF1ARB0_ID19 _if1arb0.bit._ID19 +#define IF1ARB0_ID20 _if1arb0.bit._ID20 +#define IF1ARB0_ID21 _if1arb0.bit._ID21 +#define IF1ARB0_ID22 _if1arb0.bit._ID22 +#define IF1ARB0_ID23 _if1arb0.bit._ID23 +#define IF1ARB0_ID24 _if1arb0.bit._ID24 +#define IF1ARB0_ID25 _if1arb0.bit._ID25 +#define IF1ARB0_ID26 _if1arb0.bit._ID26 +#define IF1ARB0_ID27 _if1arb0.bit._ID27 +#define IF1ARB0_ID28 _if1arb0.bit._ID28 +#define IF1ARB0_DIR _if1arb0.bit._DIR +#define IF1ARB0_XTD _if1arb0.bit._XTD +#define IF1ARB0_MSGVAL _if1arb0.bit._MSGVAL +#define IF1ARB0_ID _if1arb0.bitc._ID +__IO_EXTENDED IF1ARB10STR _if1arb10; +#define IF1ARB10 _if1arb10.word +#define IF1ARB10_ID0 _if1arb10.bit._ID0 +#define IF1ARB10_ID1 _if1arb10.bit._ID1 +#define IF1ARB10_ID2 _if1arb10.bit._ID2 +#define IF1ARB10_ID3 _if1arb10.bit._ID3 +#define IF1ARB10_ID4 _if1arb10.bit._ID4 +#define IF1ARB10_ID5 _if1arb10.bit._ID5 +#define IF1ARB10_ID6 _if1arb10.bit._ID6 +#define IF1ARB10_ID7 _if1arb10.bit._ID7 +#define IF1ARB10_ID8 _if1arb10.bit._ID8 +#define IF1ARB10_ID9 _if1arb10.bit._ID9 +#define IF1ARB10_ID10 _if1arb10.bit._ID10 +#define IF1ARB10_ID11 _if1arb10.bit._ID11 +#define IF1ARB10_ID12 _if1arb10.bit._ID12 +#define IF1ARB10_ID13 _if1arb10.bit._ID13 +#define IF1ARB10_ID14 _if1arb10.bit._ID14 +#define IF1ARB10_ID15 _if1arb10.bit._ID15 +__IO_EXTENDED IF1ARB1L0STR _if1arb1l0; +#define IF1ARB1L0 _if1arb1l0.byte +#define IF1ARB1L0_ID0 _if1arb1l0.bit._ID0 +#define IF1ARB1L0_ID1 _if1arb1l0.bit._ID1 +#define IF1ARB1L0_ID2 _if1arb1l0.bit._ID2 +#define IF1ARB1L0_ID3 _if1arb1l0.bit._ID3 +#define IF1ARB1L0_ID4 _if1arb1l0.bit._ID4 +#define IF1ARB1L0_ID5 _if1arb1l0.bit._ID5 +#define IF1ARB1L0_ID6 _if1arb1l0.bit._ID6 +#define IF1ARB1L0_ID7 _if1arb1l0.bit._ID7 +__IO_EXTENDED IF1ARB1H0STR _if1arb1h0; +#define IF1ARB1H0 _if1arb1h0.byte +#define IF1ARB1H0_ID8 _if1arb1h0.bit._ID8 +#define IF1ARB1H0_ID9 _if1arb1h0.bit._ID9 +#define IF1ARB1H0_ID10 _if1arb1h0.bit._ID10 +#define IF1ARB1H0_ID11 _if1arb1h0.bit._ID11 +#define IF1ARB1H0_ID12 _if1arb1h0.bit._ID12 +#define IF1ARB1H0_ID13 _if1arb1h0.bit._ID13 +#define IF1ARB1H0_ID14 _if1arb1h0.bit._ID14 +#define IF1ARB1H0_ID15 _if1arb1h0.bit._ID15 +__IO_EXTENDED IF1ARB20STR _if1arb20; +#define IF1ARB20 _if1arb20.word +#define IF1ARB20_ID16 _if1arb20.bit._ID16 +#define IF1ARB20_ID17 _if1arb20.bit._ID17 +#define IF1ARB20_ID18 _if1arb20.bit._ID18 +#define IF1ARB20_ID19 _if1arb20.bit._ID19 +#define IF1ARB20_ID20 _if1arb20.bit._ID20 +#define IF1ARB20_ID21 _if1arb20.bit._ID21 +#define IF1ARB20_ID22 _if1arb20.bit._ID22 +#define IF1ARB20_ID23 _if1arb20.bit._ID23 +#define IF1ARB20_ID24 _if1arb20.bit._ID24 +#define IF1ARB20_ID25 _if1arb20.bit._ID25 +#define IF1ARB20_ID26 _if1arb20.bit._ID26 +#define IF1ARB20_ID27 _if1arb20.bit._ID27 +#define IF1ARB20_ID28 _if1arb20.bit._ID28 +#define IF1ARB20_DIR _if1arb20.bit._DIR +#define IF1ARB20_XTD _if1arb20.bit._XTD +#define IF1ARB20_MSGVAL _if1arb20.bit._MSGVAL +__IO_EXTENDED IF1ARB2L0STR _if1arb2l0; +#define IF1ARB2L0 _if1arb2l0.byte +#define IF1ARB2L0_ID16 _if1arb2l0.bit._ID16 +#define IF1ARB2L0_ID17 _if1arb2l0.bit._ID17 +#define IF1ARB2L0_ID18 _if1arb2l0.bit._ID18 +#define IF1ARB2L0_ID19 _if1arb2l0.bit._ID19 +#define IF1ARB2L0_ID20 _if1arb2l0.bit._ID20 +#define IF1ARB2L0_ID21 _if1arb2l0.bit._ID21 +#define IF1ARB2L0_ID22 _if1arb2l0.bit._ID22 +#define IF1ARB2L0_ID23 _if1arb2l0.bit._ID23 +__IO_EXTENDED IF1ARB2H0STR _if1arb2h0; +#define IF1ARB2H0 _if1arb2h0.byte +#define IF1ARB2H0_ID24 _if1arb2h0.bit._ID24 +#define IF1ARB2H0_ID25 _if1arb2h0.bit._ID25 +#define IF1ARB2H0_ID26 _if1arb2h0.bit._ID26 +#define IF1ARB2H0_ID27 _if1arb2h0.bit._ID27 +#define IF1ARB2H0_ID28 _if1arb2h0.bit._ID28 +#define IF1ARB2H0_DIR _if1arb2h0.bit._DIR +#define IF1ARB2H0_XTD _if1arb2h0.bit._XTD +#define IF1ARB2H0_MSGVAL _if1arb2h0.bit._MSGVAL +__IO_EXTENDED IF1MCTR0STR _if1mctr0; +#define IF1MCTR0 _if1mctr0.word +#define IF1MCTR0_DLC0 _if1mctr0.bit._DLC0 +#define IF1MCTR0_DLC1 _if1mctr0.bit._DLC1 +#define IF1MCTR0_DLC2 _if1mctr0.bit._DLC2 +#define IF1MCTR0_DLC3 _if1mctr0.bit._DLC3 +#define IF1MCTR0_EOB _if1mctr0.bit._EOB +#define IF1MCTR0_TXRQST _if1mctr0.bit._TXRQST +#define IF1MCTR0_RMTEN _if1mctr0.bit._RMTEN +#define IF1MCTR0_RXIE _if1mctr0.bit._RXIE +#define IF1MCTR0_TXIE _if1mctr0.bit._TXIE +#define IF1MCTR0_UMASK _if1mctr0.bit._UMASK +#define IF1MCTR0_INTPND _if1mctr0.bit._INTPND +#define IF1MCTR0_MSGLST _if1mctr0.bit._MSGLST +#define IF1MCTR0_NEWDAT _if1mctr0.bit._NEWDAT +#define IF1MCTR0_DLC _if1mctr0.bitc._DLC +__IO_EXTENDED IF1MCTRL0STR _if1mctrl0; +#define IF1MCTRL0 _if1mctrl0.byte +#define IF1MCTRL0_DLC0 _if1mctrl0.bit._DLC0 +#define IF1MCTRL0_DLC1 _if1mctrl0.bit._DLC1 +#define IF1MCTRL0_DLC2 _if1mctrl0.bit._DLC2 +#define IF1MCTRL0_DLC3 _if1mctrl0.bit._DLC3 +#define IF1MCTRL0_EOB _if1mctrl0.bit._EOB +#define IF1MCTRL0_DLC _if1mctrl0.bitc._DLC +__IO_EXTENDED IF1MCTRH0STR _if1mctrh0; +#define IF1MCTRH0 _if1mctrh0.byte +#define IF1MCTRH0_TXRQST _if1mctrh0.bit._TXRQST +#define IF1MCTRH0_RMTEN _if1mctrh0.bit._RMTEN +#define IF1MCTRH0_RXIE _if1mctrh0.bit._RXIE +#define IF1MCTRH0_TXIE _if1mctrh0.bit._TXIE +#define IF1MCTRH0_UMASK _if1mctrh0.bit._UMASK +#define IF1MCTRH0_INTPND _if1mctrh0.bit._INTPND +#define IF1MCTRH0_MSGLST _if1mctrh0.bit._MSGLST +#define IF1MCTRH0_NEWDAT _if1mctrh0.bit._NEWDAT +__IO_EXTENDED IF1DTA0STR _if1dta0; +#define IF1DTA0 _if1dta0.lword +__IO_EXTENDED IF1DTA10STR _if1dta10; +#define IF1DTA10 _if1dta10.word +__IO_EXTENDED IF1DTA1L0STR _if1dta1l0; +#define IF1DTA1L0 _if1dta1l0.byte +__IO_EXTENDED IF1DTA1H0STR _if1dta1h0; +#define IF1DTA1H0 _if1dta1h0.byte +__IO_EXTENDED IF1DTA20STR _if1dta20; +#define IF1DTA20 _if1dta20.word +__IO_EXTENDED IF1DTA2L0STR _if1dta2l0; +#define IF1DTA2L0 _if1dta2l0.byte +__IO_EXTENDED IF1DTA2H0STR _if1dta2h0; +#define IF1DTA2H0 _if1dta2h0.byte +__IO_EXTENDED IF1DTB0STR _if1dtb0; +#define IF1DTB0 _if1dtb0.lword +__IO_EXTENDED IF1DTB10STR _if1dtb10; +#define IF1DTB10 _if1dtb10.word +__IO_EXTENDED IF1DTB1L0STR _if1dtb1l0; +#define IF1DTB1L0 _if1dtb1l0.byte +__IO_EXTENDED IF1DTB1H0STR _if1dtb1h0; +#define IF1DTB1H0 _if1dtb1h0.byte +__IO_EXTENDED IF1DTB20STR _if1dtb20; +#define IF1DTB20 _if1dtb20.word +__IO_EXTENDED IF1DTB2L0STR _if1dtb2l0; +#define IF1DTB2L0 _if1dtb2l0.byte +__IO_EXTENDED IF1DTB2H0STR _if1dtb2h0; +#define IF1DTB2H0 _if1dtb2h0.byte +__IO_EXTENDED IF2CREQ0STR _if2creq0; +#define IF2CREQ0 _if2creq0.word +#define IF2CREQ0_MSGN0 _if2creq0.bit._MSGN0 +#define IF2CREQ0_MSGN1 _if2creq0.bit._MSGN1 +#define IF2CREQ0_MSGN2 _if2creq0.bit._MSGN2 +#define IF2CREQ0_MSGN3 _if2creq0.bit._MSGN3 +#define IF2CREQ0_MSGN4 _if2creq0.bit._MSGN4 +#define IF2CREQ0_MSGN5 _if2creq0.bit._MSGN5 +#define IF2CREQ0_MSGN6 _if2creq0.bit._MSGN6 +#define IF2CREQ0_MSGN7 _if2creq0.bit._MSGN7 +#define IF2CREQ0_BUSY _if2creq0.bit._BUSY +__IO_EXTENDED IF2CREQL0STR _if2creql0; +#define IF2CREQL0 _if2creql0.byte +#define IF2CREQL0_MSGN0 _if2creql0.bit._MSGN0 +#define IF2CREQL0_MSGN1 _if2creql0.bit._MSGN1 +#define IF2CREQL0_MSGN2 _if2creql0.bit._MSGN2 +#define IF2CREQL0_MSGN3 _if2creql0.bit._MSGN3 +#define IF2CREQL0_MSGN4 _if2creql0.bit._MSGN4 +#define IF2CREQL0_MSGN5 _if2creql0.bit._MSGN5 +#define IF2CREQL0_MSGN6 _if2creql0.bit._MSGN6 +#define IF2CREQL0_MSGN7 _if2creql0.bit._MSGN7 +__IO_EXTENDED IF2CREQH0STR _if2creqh0; +#define IF2CREQH0 _if2creqh0.byte +#define IF2CREQH0_BUSY _if2creqh0.bit._BUSY +__IO_EXTENDED IF2CMSK0STR _if2cmsk0; +#define IF2CMSK0 _if2cmsk0.word +#define IF2CMSK0_DATAB _if2cmsk0.bit._DATAB +#define IF2CMSK0_DATAA _if2cmsk0.bit._DATAA +#define IF2CMSK0_TXREQ _if2cmsk0.bit._TXREQ +#define IF2CMSK0_CIP _if2cmsk0.bit._CIP +#define IF2CMSK0_CONTROL _if2cmsk0.bit._CONTROL +#define IF2CMSK0_ARB _if2cmsk0.bit._ARB +#define IF2CMSK0_MASK _if2cmsk0.bit._MASK +#define IF2CMSK0_WRRD _if2cmsk0.bit._WRRD +__IO_EXTENDED IF2CMSKL0STR _if2cmskl0; +#define IF2CMSKL0 _if2cmskl0.byte +#define IF2CMSKL0_DATAB _if2cmskl0.bit._DATAB +#define IF2CMSKL0_DATAA _if2cmskl0.bit._DATAA +#define IF2CMSKL0_TXREQ _if2cmskl0.bit._TXREQ +#define IF2CMSKL0_CIP _if2cmskl0.bit._CIP +#define IF2CMSKL0_CONTROL _if2cmskl0.bit._CONTROL +#define IF2CMSKL0_ARB _if2cmskl0.bit._ARB +#define IF2CMSKL0_MASK _if2cmskl0.bit._MASK +#define IF2CMSKL0_WRRD _if2cmskl0.bit._WRRD +__IO_EXTENDED IF2CMSKH0STR _if2cmskh0; +#define IF2CMSKH0 _if2cmskh0.byte +__IO_EXTENDED IF2MSK0STR _if2msk0; +#define IF2MSK0 _if2msk0.lword +#define IF2MSK0_MSK0 _if2msk0.bit._MSK0 +#define IF2MSK0_MSK1 _if2msk0.bit._MSK1 +#define IF2MSK0_MSK2 _if2msk0.bit._MSK2 +#define IF2MSK0_MSK3 _if2msk0.bit._MSK3 +#define IF2MSK0_MSK4 _if2msk0.bit._MSK4 +#define IF2MSK0_MSK5 _if2msk0.bit._MSK5 +#define IF2MSK0_MSK6 _if2msk0.bit._MSK6 +#define IF2MSK0_MSK7 _if2msk0.bit._MSK7 +#define IF2MSK0_MSK8 _if2msk0.bit._MSK8 +#define IF2MSK0_MSK9 _if2msk0.bit._MSK9 +#define IF2MSK0_MSK10 _if2msk0.bit._MSK10 +#define IF2MSK0_MSK11 _if2msk0.bit._MSK11 +#define IF2MSK0_MSK12 _if2msk0.bit._MSK12 +#define IF2MSK0_MSK13 _if2msk0.bit._MSK13 +#define IF2MSK0_MSK14 _if2msk0.bit._MSK14 +#define IF2MSK0_MSK15 _if2msk0.bit._MSK15 +#define IF2MSK0_MSK16 _if2msk0.bit._MSK16 +#define IF2MSK0_MSK17 _if2msk0.bit._MSK17 +#define IF2MSK0_MSK18 _if2msk0.bit._MSK18 +#define IF2MSK0_MSK19 _if2msk0.bit._MSK19 +#define IF2MSK0_MSK20 _if2msk0.bit._MSK20 +#define IF2MSK0_MSK21 _if2msk0.bit._MSK21 +#define IF2MSK0_MSK22 _if2msk0.bit._MSK22 +#define IF2MSK0_MSK23 _if2msk0.bit._MSK23 +#define IF2MSK0_MSK24 _if2msk0.bit._MSK24 +#define IF2MSK0_MSK25 _if2msk0.bit._MSK25 +#define IF2MSK0_MSK26 _if2msk0.bit._MSK26 +#define IF2MSK0_MSK27 _if2msk0.bit._MSK27 +#define IF2MSK0_MSK28 _if2msk0.bit._MSK28 +#define IF2MSK0_MDIR _if2msk0.bit._MDIR +#define IF2MSK0_MXTD _if2msk0.bit._MXTD +#define IF2MSK0_MSK _if2msk0.bitc._MSK +__IO_EXTENDED IF2MSK10STR _if2msk10; +#define IF2MSK10 _if2msk10.word +#define IF2MSK10_MSK0 _if2msk10.bit._MSK0 +#define IF2MSK10_MSK1 _if2msk10.bit._MSK1 +#define IF2MSK10_MSK2 _if2msk10.bit._MSK2 +#define IF2MSK10_MSK3 _if2msk10.bit._MSK3 +#define IF2MSK10_MSK4 _if2msk10.bit._MSK4 +#define IF2MSK10_MSK5 _if2msk10.bit._MSK5 +#define IF2MSK10_MSK6 _if2msk10.bit._MSK6 +#define IF2MSK10_MSK7 _if2msk10.bit._MSK7 +#define IF2MSK10_MSK8 _if2msk10.bit._MSK8 +#define IF2MSK10_MSK9 _if2msk10.bit._MSK9 +#define IF2MSK10_MSK10 _if2msk10.bit._MSK10 +#define IF2MSK10_MSK11 _if2msk10.bit._MSK11 +#define IF2MSK10_MSK12 _if2msk10.bit._MSK12 +#define IF2MSK10_MSK13 _if2msk10.bit._MSK13 +#define IF2MSK10_MSK14 _if2msk10.bit._MSK14 +#define IF2MSK10_MSK15 _if2msk10.bit._MSK15 +__IO_EXTENDED IF2MSK1L0STR _if2msk1l0; +#define IF2MSK1L0 _if2msk1l0.byte +#define IF2MSK1L0_MSK0 _if2msk1l0.bit._MSK0 +#define IF2MSK1L0_MSK1 _if2msk1l0.bit._MSK1 +#define IF2MSK1L0_MSK2 _if2msk1l0.bit._MSK2 +#define IF2MSK1L0_MSK3 _if2msk1l0.bit._MSK3 +#define IF2MSK1L0_MSK4 _if2msk1l0.bit._MSK4 +#define IF2MSK1L0_MSK5 _if2msk1l0.bit._MSK5 +#define IF2MSK1L0_MSK6 _if2msk1l0.bit._MSK6 +#define IF2MSK1L0_MSK7 _if2msk1l0.bit._MSK7 +__IO_EXTENDED IF2MSK1H0STR _if2msk1h0; +#define IF2MSK1H0 _if2msk1h0.byte +#define IF2MSK1H0_MSK8 _if2msk1h0.bit._MSK8 +#define IF2MSK1H0_MSK9 _if2msk1h0.bit._MSK9 +#define IF2MSK1H0_MSK10 _if2msk1h0.bit._MSK10 +#define IF2MSK1H0_MSK11 _if2msk1h0.bit._MSK11 +#define IF2MSK1H0_MSK12 _if2msk1h0.bit._MSK12 +#define IF2MSK1H0_MSK13 _if2msk1h0.bit._MSK13 +#define IF2MSK1H0_MSK14 _if2msk1h0.bit._MSK14 +#define IF2MSK1H0_MSK15 _if2msk1h0.bit._MSK15 +__IO_EXTENDED IF2MSK20STR _if2msk20; +#define IF2MSK20 _if2msk20.word +#define IF2MSK20_MSK16 _if2msk20.bit._MSK16 +#define IF2MSK20_MSK17 _if2msk20.bit._MSK17 +#define IF2MSK20_MSK18 _if2msk20.bit._MSK18 +#define IF2MSK20_MSK19 _if2msk20.bit._MSK19 +#define IF2MSK20_MSK20 _if2msk20.bit._MSK20 +#define IF2MSK20_MSK21 _if2msk20.bit._MSK21 +#define IF2MSK20_MSK22 _if2msk20.bit._MSK22 +#define IF2MSK20_MSK23 _if2msk20.bit._MSK23 +#define IF2MSK20_MSK24 _if2msk20.bit._MSK24 +#define IF2MSK20_MSK25 _if2msk20.bit._MSK25 +#define IF2MSK20_MSK26 _if2msk20.bit._MSK26 +#define IF2MSK20_MSK27 _if2msk20.bit._MSK27 +#define IF2MSK20_MSK28 _if2msk20.bit._MSK28 +#define IF2MSK20_MDIR _if2msk20.bit._MDIR +#define IF2MSK20_MXTD _if2msk20.bit._MXTD +__IO_EXTENDED IF2MSK2L0STR _if2msk2l0; +#define IF2MSK2L0 _if2msk2l0.byte +#define IF2MSK2L0_MSK16 _if2msk2l0.bit._MSK16 +#define IF2MSK2L0_MSK17 _if2msk2l0.bit._MSK17 +#define IF2MSK2L0_MSK18 _if2msk2l0.bit._MSK18 +#define IF2MSK2L0_MSK19 _if2msk2l0.bit._MSK19 +#define IF2MSK2L0_MSK20 _if2msk2l0.bit._MSK20 +#define IF2MSK2L0_MSK21 _if2msk2l0.bit._MSK21 +#define IF2MSK2L0_MSK22 _if2msk2l0.bit._MSK22 +#define IF2MSK2L0_MSK23 _if2msk2l0.bit._MSK23 +__IO_EXTENDED IF2MSK2H0STR _if2msk2h0; +#define IF2MSK2H0 _if2msk2h0.byte +#define IF2MSK2H0_MSK24 _if2msk2h0.bit._MSK24 +#define IF2MSK2H0_MSK25 _if2msk2h0.bit._MSK25 +#define IF2MSK2H0_MSK26 _if2msk2h0.bit._MSK26 +#define IF2MSK2H0_MSK27 _if2msk2h0.bit._MSK27 +#define IF2MSK2H0_MSK28 _if2msk2h0.bit._MSK28 +#define IF2MSK2H0_MDIR _if2msk2h0.bit._MDIR +#define IF2MSK2H0_MXTD _if2msk2h0.bit._MXTD +__IO_EXTENDED IF2ARB0STR _if2arb0; +#define IF2ARB0 _if2arb0.lword +#define IF2ARB0_ID0 _if2arb0.bit._ID0 +#define IF2ARB0_ID1 _if2arb0.bit._ID1 +#define IF2ARB0_ID2 _if2arb0.bit._ID2 +#define IF2ARB0_ID3 _if2arb0.bit._ID3 +#define IF2ARB0_ID4 _if2arb0.bit._ID4 +#define IF2ARB0_ID5 _if2arb0.bit._ID5 +#define IF2ARB0_ID6 _if2arb0.bit._ID6 +#define IF2ARB0_ID7 _if2arb0.bit._ID7 +#define IF2ARB0_ID8 _if2arb0.bit._ID8 +#define IF2ARB0_ID9 _if2arb0.bit._ID9 +#define IF2ARB0_ID10 _if2arb0.bit._ID10 +#define IF2ARB0_ID11 _if2arb0.bit._ID11 +#define IF2ARB0_ID12 _if2arb0.bit._ID12 +#define IF2ARB0_ID13 _if2arb0.bit._ID13 +#define IF2ARB0_ID14 _if2arb0.bit._ID14 +#define IF2ARB0_ID15 _if2arb0.bit._ID15 +#define IF2ARB0_ID16 _if2arb0.bit._ID16 +#define IF2ARB0_ID17 _if2arb0.bit._ID17 +#define IF2ARB0_ID18 _if2arb0.bit._ID18 +#define IF2ARB0_ID19 _if2arb0.bit._ID19 +#define IF2ARB0_ID20 _if2arb0.bit._ID20 +#define IF2ARB0_ID21 _if2arb0.bit._ID21 +#define IF2ARB0_ID22 _if2arb0.bit._ID22 +#define IF2ARB0_ID23 _if2arb0.bit._ID23 +#define IF2ARB0_ID24 _if2arb0.bit._ID24 +#define IF2ARB0_ID25 _if2arb0.bit._ID25 +#define IF2ARB0_ID26 _if2arb0.bit._ID26 +#define IF2ARB0_ID27 _if2arb0.bit._ID27 +#define IF2ARB0_ID28 _if2arb0.bit._ID28 +#define IF2ARB0_DIR _if2arb0.bit._DIR +#define IF2ARB0_XTD _if2arb0.bit._XTD +#define IF2ARB0_MSGVAL _if2arb0.bit._MSGVAL +#define IF2ARB0_ID _if2arb0.bitc._ID +__IO_EXTENDED IF2ARB10STR _if2arb10; +#define IF2ARB10 _if2arb10.word +#define IF2ARB10_ID0 _if2arb10.bit._ID0 +#define IF2ARB10_ID1 _if2arb10.bit._ID1 +#define IF2ARB10_ID2 _if2arb10.bit._ID2 +#define IF2ARB10_ID3 _if2arb10.bit._ID3 +#define IF2ARB10_ID4 _if2arb10.bit._ID4 +#define IF2ARB10_ID5 _if2arb10.bit._ID5 +#define IF2ARB10_ID6 _if2arb10.bit._ID6 +#define IF2ARB10_ID7 _if2arb10.bit._ID7 +#define IF2ARB10_ID8 _if2arb10.bit._ID8 +#define IF2ARB10_ID9 _if2arb10.bit._ID9 +#define IF2ARB10_ID10 _if2arb10.bit._ID10 +#define IF2ARB10_ID11 _if2arb10.bit._ID11 +#define IF2ARB10_ID12 _if2arb10.bit._ID12 +#define IF2ARB10_ID13 _if2arb10.bit._ID13 +#define IF2ARB10_ID14 _if2arb10.bit._ID14 +#define IF2ARB10_ID15 _if2arb10.bit._ID15 +__IO_EXTENDED IF2ARB1L0STR _if2arb1l0; +#define IF2ARB1L0 _if2arb1l0.byte +#define IF2ARB1L0_ID0 _if2arb1l0.bit._ID0 +#define IF2ARB1L0_ID1 _if2arb1l0.bit._ID1 +#define IF2ARB1L0_ID2 _if2arb1l0.bit._ID2 +#define IF2ARB1L0_ID3 _if2arb1l0.bit._ID3 +#define IF2ARB1L0_ID4 _if2arb1l0.bit._ID4 +#define IF2ARB1L0_ID5 _if2arb1l0.bit._ID5 +#define IF2ARB1L0_ID6 _if2arb1l0.bit._ID6 +#define IF2ARB1L0_ID7 _if2arb1l0.bit._ID7 +__IO_EXTENDED IF2ARB1H0STR _if2arb1h0; +#define IF2ARB1H0 _if2arb1h0.byte +#define IF2ARB1H0_ID8 _if2arb1h0.bit._ID8 +#define IF2ARB1H0_ID9 _if2arb1h0.bit._ID9 +#define IF2ARB1H0_ID10 _if2arb1h0.bit._ID10 +#define IF2ARB1H0_ID11 _if2arb1h0.bit._ID11 +#define IF2ARB1H0_ID12 _if2arb1h0.bit._ID12 +#define IF2ARB1H0_ID13 _if2arb1h0.bit._ID13 +#define IF2ARB1H0_ID14 _if2arb1h0.bit._ID14 +#define IF2ARB1H0_ID15 _if2arb1h0.bit._ID15 +__IO_EXTENDED IF2ARB20STR _if2arb20; +#define IF2ARB20 _if2arb20.word +#define IF2ARB20_ID16 _if2arb20.bit._ID16 +#define IF2ARB20_ID17 _if2arb20.bit._ID17 +#define IF2ARB20_ID18 _if2arb20.bit._ID18 +#define IF2ARB20_ID19 _if2arb20.bit._ID19 +#define IF2ARB20_ID20 _if2arb20.bit._ID20 +#define IF2ARB20_ID21 _if2arb20.bit._ID21 +#define IF2ARB20_ID22 _if2arb20.bit._ID22 +#define IF2ARB20_ID23 _if2arb20.bit._ID23 +#define IF2ARB20_ID24 _if2arb20.bit._ID24 +#define IF2ARB20_ID25 _if2arb20.bit._ID25 +#define IF2ARB20_ID26 _if2arb20.bit._ID26 +#define IF2ARB20_ID27 _if2arb20.bit._ID27 +#define IF2ARB20_ID28 _if2arb20.bit._ID28 +#define IF2ARB20_DIR _if2arb20.bit._DIR +#define IF2ARB20_XTD _if2arb20.bit._XTD +#define IF2ARB20_MSGVAL _if2arb20.bit._MSGVAL +__IO_EXTENDED IF2ARB2L0STR _if2arb2l0; +#define IF2ARB2L0 _if2arb2l0.byte +#define IF2ARB2L0_ID16 _if2arb2l0.bit._ID16 +#define IF2ARB2L0_ID17 _if2arb2l0.bit._ID17 +#define IF2ARB2L0_ID18 _if2arb2l0.bit._ID18 +#define IF2ARB2L0_ID19 _if2arb2l0.bit._ID19 +#define IF2ARB2L0_ID20 _if2arb2l0.bit._ID20 +#define IF2ARB2L0_ID21 _if2arb2l0.bit._ID21 +#define IF2ARB2L0_ID22 _if2arb2l0.bit._ID22 +#define IF2ARB2L0_ID23 _if2arb2l0.bit._ID23 +__IO_EXTENDED IF2ARB2H0STR _if2arb2h0; +#define IF2ARB2H0 _if2arb2h0.byte +#define IF2ARB2H0_ID24 _if2arb2h0.bit._ID24 +#define IF2ARB2H0_ID25 _if2arb2h0.bit._ID25 +#define IF2ARB2H0_ID26 _if2arb2h0.bit._ID26 +#define IF2ARB2H0_ID27 _if2arb2h0.bit._ID27 +#define IF2ARB2H0_ID28 _if2arb2h0.bit._ID28 +#define IF2ARB2H0_DIR _if2arb2h0.bit._DIR +#define IF2ARB2H0_XTD _if2arb2h0.bit._XTD +#define IF2ARB2H0_MSGVAL _if2arb2h0.bit._MSGVAL +__IO_EXTENDED IF2MCTR0STR _if2mctr0; +#define IF2MCTR0 _if2mctr0.word +#define IF2MCTR0_DLC0 _if2mctr0.bit._DLC0 +#define IF2MCTR0_DLC1 _if2mctr0.bit._DLC1 +#define IF2MCTR0_DLC2 _if2mctr0.bit._DLC2 +#define IF2MCTR0_DLC3 _if2mctr0.bit._DLC3 +#define IF2MCTR0_EOB _if2mctr0.bit._EOB +#define IF2MCTR0_TXRQST _if2mctr0.bit._TXRQST +#define IF2MCTR0_RMTEN _if2mctr0.bit._RMTEN +#define IF2MCTR0_RXIE _if2mctr0.bit._RXIE +#define IF2MCTR0_TXIE _if2mctr0.bit._TXIE +#define IF2MCTR0_UMASK _if2mctr0.bit._UMASK +#define IF2MCTR0_INTPND _if2mctr0.bit._INTPND +#define IF2MCTR0_MSGLST _if2mctr0.bit._MSGLST +#define IF2MCTR0_NEWDAT _if2mctr0.bit._NEWDAT +#define IF2MCTR0_DLC _if2mctr0.bitc._DLC +__IO_EXTENDED IF2MCTRL0STR _if2mctrl0; +#define IF2MCTRL0 _if2mctrl0.byte +#define IF2MCTRL0_DLC0 _if2mctrl0.bit._DLC0 +#define IF2MCTRL0_DLC1 _if2mctrl0.bit._DLC1 +#define IF2MCTRL0_DLC2 _if2mctrl0.bit._DLC2 +#define IF2MCTRL0_DLC3 _if2mctrl0.bit._DLC3 +#define IF2MCTRL0_EOB _if2mctrl0.bit._EOB +#define IF2MCTRL0_DLC _if2mctrl0.bitc._DLC +__IO_EXTENDED IF2MCTRH0STR _if2mctrh0; +#define IF2MCTRH0 _if2mctrh0.byte +#define IF2MCTRH0_TXRQST _if2mctrh0.bit._TXRQST +#define IF2MCTRH0_RMTEN _if2mctrh0.bit._RMTEN +#define IF2MCTRH0_RXIE _if2mctrh0.bit._RXIE +#define IF2MCTRH0_TXIE _if2mctrh0.bit._TXIE +#define IF2MCTRH0_UMASK _if2mctrh0.bit._UMASK +#define IF2MCTRH0_INTPND _if2mctrh0.bit._INTPND +#define IF2MCTRH0_MSGLST _if2mctrh0.bit._MSGLST +#define IF2MCTRH0_NEWDAT _if2mctrh0.bit._NEWDAT +__IO_EXTENDED IF2DTA0STR _if2dta0; +#define IF2DTA0 _if2dta0.lword +__IO_EXTENDED IF2DTA10STR _if2dta10; +#define IF2DTA10 _if2dta10.word +__IO_EXTENDED IF2DTA1L0STR _if2dta1l0; +#define IF2DTA1L0 _if2dta1l0.byte +__IO_EXTENDED IF2DTA1H0STR _if2dta1h0; +#define IF2DTA1H0 _if2dta1h0.byte +__IO_EXTENDED IF2DTA20STR _if2dta20; +#define IF2DTA20 _if2dta20.word +__IO_EXTENDED IF2DTA2L0STR _if2dta2l0; +#define IF2DTA2L0 _if2dta2l0.byte +__IO_EXTENDED IF2DTA2H0STR _if2dta2h0; +#define IF2DTA2H0 _if2dta2h0.byte +__IO_EXTENDED IF2DTB0STR _if2dtb0; +#define IF2DTB0 _if2dtb0.lword +__IO_EXTENDED IF2DTB10STR _if2dtb10; +#define IF2DTB10 _if2dtb10.word +__IO_EXTENDED IF2DTB1L0STR _if2dtb1l0; +#define IF2DTB1L0 _if2dtb1l0.byte +__IO_EXTENDED IF2DTB1H0STR _if2dtb1h0; +#define IF2DTB1H0 _if2dtb1h0.byte +__IO_EXTENDED IF2DTB20STR _if2dtb20; +#define IF2DTB20 _if2dtb20.word +__IO_EXTENDED IF2DTB2L0STR _if2dtb2l0; +#define IF2DTB2L0 _if2dtb2l0.byte +__IO_EXTENDED IF2DTB2H0STR _if2dtb2h0; +#define IF2DTB2H0 _if2dtb2h0.byte +__IO_EXTENDED TREQR0STR _treqr0; +#define TREQR0 _treqr0.lword +#define TREQR0_TXRQST1 _treqr0.bit._TXRQST1 +#define TREQR0_TXRQST2 _treqr0.bit._TXRQST2 +#define TREQR0_TXRQST3 _treqr0.bit._TXRQST3 +#define TREQR0_TXRQST4 _treqr0.bit._TXRQST4 +#define TREQR0_TXRQST5 _treqr0.bit._TXRQST5 +#define TREQR0_TXRQST6 _treqr0.bit._TXRQST6 +#define TREQR0_TXRQST7 _treqr0.bit._TXRQST7 +#define TREQR0_TXRQST8 _treqr0.bit._TXRQST8 +#define TREQR0_TXRQST9 _treqr0.bit._TXRQST9 +#define TREQR0_TXRQST10 _treqr0.bit._TXRQST10 +#define TREQR0_TXRQST11 _treqr0.bit._TXRQST11 +#define TREQR0_TXRQST12 _treqr0.bit._TXRQST12 +#define TREQR0_TXRQST13 _treqr0.bit._TXRQST13 +#define TREQR0_TXRQST14 _treqr0.bit._TXRQST14 +#define TREQR0_TXRQST15 _treqr0.bit._TXRQST15 +#define TREQR0_TXRQST16 _treqr0.bit._TXRQST16 +#define TREQR0_TXRQST17 _treqr0.bit._TXRQST17 +#define TREQR0_TXRQST18 _treqr0.bit._TXRQST18 +#define TREQR0_TXRQST19 _treqr0.bit._TXRQST19 +#define TREQR0_TXRQST20 _treqr0.bit._TXRQST20 +#define TREQR0_TXRQST21 _treqr0.bit._TXRQST21 +#define TREQR0_TXRQST22 _treqr0.bit._TXRQST22 +#define TREQR0_TXRQST23 _treqr0.bit._TXRQST23 +#define TREQR0_TXRQST24 _treqr0.bit._TXRQST24 +#define TREQR0_TXRQST25 _treqr0.bit._TXRQST25 +#define TREQR0_TXRQST26 _treqr0.bit._TXRQST26 +#define TREQR0_TXRQST27 _treqr0.bit._TXRQST27 +#define TREQR0_TXRQST28 _treqr0.bit._TXRQST28 +#define TREQR0_TXRQST29 _treqr0.bit._TXRQST29 +#define TREQR0_TXRQST30 _treqr0.bit._TXRQST30 +#define TREQR0_TXRQST31 _treqr0.bit._TXRQST31 +#define TREQR0_TXRQST32 _treqr0.bit._TXRQST32 +#define TREQR0_TXRQST _treqr0.bitc._TXRQST +__IO_EXTENDED TREQR10STR _treqr10; +#define TREQR10 _treqr10.word +#define TREQR10_TXRQST1 _treqr10.bit._TXRQST1 +#define TREQR10_TXRQST2 _treqr10.bit._TXRQST2 +#define TREQR10_TXRQST3 _treqr10.bit._TXRQST3 +#define TREQR10_TXRQST4 _treqr10.bit._TXRQST4 +#define TREQR10_TXRQST5 _treqr10.bit._TXRQST5 +#define TREQR10_TXRQST6 _treqr10.bit._TXRQST6 +#define TREQR10_TXRQST7 _treqr10.bit._TXRQST7 +#define TREQR10_TXRQST8 _treqr10.bit._TXRQST8 +#define TREQR10_TXRQST9 _treqr10.bit._TXRQST9 +#define TREQR10_TXRQST10 _treqr10.bit._TXRQST10 +#define TREQR10_TXRQST11 _treqr10.bit._TXRQST11 +#define TREQR10_TXRQST12 _treqr10.bit._TXRQST12 +#define TREQR10_TXRQST13 _treqr10.bit._TXRQST13 +#define TREQR10_TXRQST14 _treqr10.bit._TXRQST14 +#define TREQR10_TXRQST15 _treqr10.bit._TXRQST15 +#define TREQR10_TXRQST16 _treqr10.bit._TXRQST16 +__IO_EXTENDED TREQR1L0STR _treqr1l0; +#define TREQR1L0 _treqr1l0.byte +#define TREQR1L0_TXRQST1 _treqr1l0.bit._TXRQST1 +#define TREQR1L0_TXRQST2 _treqr1l0.bit._TXRQST2 +#define TREQR1L0_TXRQST3 _treqr1l0.bit._TXRQST3 +#define TREQR1L0_TXRQST4 _treqr1l0.bit._TXRQST4 +#define TREQR1L0_TXRQST5 _treqr1l0.bit._TXRQST5 +#define TREQR1L0_TXRQST6 _treqr1l0.bit._TXRQST6 +#define TREQR1L0_TXRQST7 _treqr1l0.bit._TXRQST7 +#define TREQR1L0_TXRQST8 _treqr1l0.bit._TXRQST8 +__IO_EXTENDED TREQR1H0STR _treqr1h0; +#define TREQR1H0 _treqr1h0.byte +#define TREQR1H0_TXRQST9 _treqr1h0.bit._TXRQST9 +#define TREQR1H0_TXRQST10 _treqr1h0.bit._TXRQST10 +#define TREQR1H0_TXRQST11 _treqr1h0.bit._TXRQST11 +#define TREQR1H0_TXRQST12 _treqr1h0.bit._TXRQST12 +#define TREQR1H0_TXRQST13 _treqr1h0.bit._TXRQST13 +#define TREQR1H0_TXRQST14 _treqr1h0.bit._TXRQST14 +#define TREQR1H0_TXRQST15 _treqr1h0.bit._TXRQST15 +#define TREQR1H0_TXRQST16 _treqr1h0.bit._TXRQST16 +__IO_EXTENDED TREQR20STR _treqr20; +#define TREQR20 _treqr20.word +#define TREQR20_TXRQST17 _treqr20.bit._TXRQST17 +#define TREQR20_TXRQST18 _treqr20.bit._TXRQST18 +#define TREQR20_TXRQST19 _treqr20.bit._TXRQST19 +#define TREQR20_TXRQST20 _treqr20.bit._TXRQST20 +#define TREQR20_TXRQST21 _treqr20.bit._TXRQST21 +#define TREQR20_TXRQST22 _treqr20.bit._TXRQST22 +#define TREQR20_TXRQST23 _treqr20.bit._TXRQST23 +#define TREQR20_TXRQST24 _treqr20.bit._TXRQST24 +#define TREQR20_TXRQST25 _treqr20.bit._TXRQST25 +#define TREQR20_TXRQST26 _treqr20.bit._TXRQST26 +#define TREQR20_TXRQST27 _treqr20.bit._TXRQST27 +#define TREQR20_TXRQST28 _treqr20.bit._TXRQST28 +#define TREQR20_TXRQST29 _treqr20.bit._TXRQST29 +#define TREQR20_TXRQST30 _treqr20.bit._TXRQST30 +#define TREQR20_TXRQST31 _treqr20.bit._TXRQST31 +#define TREQR20_TXRQST32 _treqr20.bit._TXRQST32 +__IO_EXTENDED TREQR2L0STR _treqr2l0; +#define TREQR2L0 _treqr2l0.byte +#define TREQR2L0_TXRQST17 _treqr2l0.bit._TXRQST17 +#define TREQR2L0_TXRQST18 _treqr2l0.bit._TXRQST18 +#define TREQR2L0_TXRQST19 _treqr2l0.bit._TXRQST19 +#define TREQR2L0_TXRQST20 _treqr2l0.bit._TXRQST20 +#define TREQR2L0_TXRQST21 _treqr2l0.bit._TXRQST21 +#define TREQR2L0_TXRQST22 _treqr2l0.bit._TXRQST22 +#define TREQR2L0_TXRQST23 _treqr2l0.bit._TXRQST23 +#define TREQR2L0_TXRQST24 _treqr2l0.bit._TXRQST24 +__IO_EXTENDED TREQR2H0STR _treqr2h0; +#define TREQR2H0 _treqr2h0.byte +#define TREQR2H0_TXRQST25 _treqr2h0.bit._TXRQST25 +#define TREQR2H0_TXRQST26 _treqr2h0.bit._TXRQST26 +#define TREQR2H0_TXRQST27 _treqr2h0.bit._TXRQST27 +#define TREQR2H0_TXRQST28 _treqr2h0.bit._TXRQST28 +#define TREQR2H0_TXRQST29 _treqr2h0.bit._TXRQST29 +#define TREQR2H0_TXRQST30 _treqr2h0.bit._TXRQST30 +#define TREQR2H0_TXRQST31 _treqr2h0.bit._TXRQST31 +#define TREQR2H0_TXRQST32 _treqr2h0.bit._TXRQST32 +__IO_EXTENDED NEWDT0STR _newdt0; +#define NEWDT0 _newdt0.lword +#define NEWDT0_NEWDAT1 _newdt0.bit._NEWDAT1 +#define NEWDT0_NEWDAT2 _newdt0.bit._NEWDAT2 +#define NEWDT0_NEWDAT3 _newdt0.bit._NEWDAT3 +#define NEWDT0_NEWDAT4 _newdt0.bit._NEWDAT4 +#define NEWDT0_NEWDAT5 _newdt0.bit._NEWDAT5 +#define NEWDT0_NEWDAT6 _newdt0.bit._NEWDAT6 +#define NEWDT0_NEWDAT7 _newdt0.bit._NEWDAT7 +#define NEWDT0_NEWDAT8 _newdt0.bit._NEWDAT8 +#define NEWDT0_NEWDAT9 _newdt0.bit._NEWDAT9 +#define NEWDT0_NEWDAT10 _newdt0.bit._NEWDAT10 +#define NEWDT0_NEWDAT11 _newdt0.bit._NEWDAT11 +#define NEWDT0_NEWDAT12 _newdt0.bit._NEWDAT12 +#define NEWDT0_NEWDAT13 _newdt0.bit._NEWDAT13 +#define NEWDT0_NEWDAT14 _newdt0.bit._NEWDAT14 +#define NEWDT0_NEWDAT15 _newdt0.bit._NEWDAT15 +#define NEWDT0_NEWDAT16 _newdt0.bit._NEWDAT16 +#define NEWDT0_NEWDAT17 _newdt0.bit._NEWDAT17 +#define NEWDT0_NEWDAT18 _newdt0.bit._NEWDAT18 +#define NEWDT0_NEWDAT19 _newdt0.bit._NEWDAT19 +#define NEWDT0_NEWDAT20 _newdt0.bit._NEWDAT20 +#define NEWDT0_NEWDAT21 _newdt0.bit._NEWDAT21 +#define NEWDT0_NEWDAT22 _newdt0.bit._NEWDAT22 +#define NEWDT0_NEWDAT23 _newdt0.bit._NEWDAT23 +#define NEWDT0_NEWDAT24 _newdt0.bit._NEWDAT24 +#define NEWDT0_NEWDAT25 _newdt0.bit._NEWDAT25 +#define NEWDT0_NEWDAT26 _newdt0.bit._NEWDAT26 +#define NEWDT0_NEWDAT27 _newdt0.bit._NEWDAT27 +#define NEWDT0_NEWDAT28 _newdt0.bit._NEWDAT28 +#define NEWDT0_NEWDAT29 _newdt0.bit._NEWDAT29 +#define NEWDT0_NEWDAT30 _newdt0.bit._NEWDAT30 +#define NEWDT0_NEWDAT31 _newdt0.bit._NEWDAT31 +#define NEWDT0_NEWDAT32 _newdt0.bit._NEWDAT32 +#define NEWDT0_NEWDAT _newdt0.bitc._NEWDAT +__IO_EXTENDED NEWDT10STR _newdt10; +#define NEWDT10 _newdt10.word +#define NEWDT10_NEWDAT1 _newdt10.bit._NEWDAT1 +#define NEWDT10_NEWDAT2 _newdt10.bit._NEWDAT2 +#define NEWDT10_NEWDAT3 _newdt10.bit._NEWDAT3 +#define NEWDT10_NEWDAT4 _newdt10.bit._NEWDAT4 +#define NEWDT10_NEWDAT5 _newdt10.bit._NEWDAT5 +#define NEWDT10_NEWDAT6 _newdt10.bit._NEWDAT6 +#define NEWDT10_NEWDAT7 _newdt10.bit._NEWDAT7 +#define NEWDT10_NEWDAT8 _newdt10.bit._NEWDAT8 +#define NEWDT10_NEWDAT9 _newdt10.bit._NEWDAT9 +#define NEWDT10_NEWDAT10 _newdt10.bit._NEWDAT10 +#define NEWDT10_NEWDAT11 _newdt10.bit._NEWDAT11 +#define NEWDT10_NEWDAT12 _newdt10.bit._NEWDAT12 +#define NEWDT10_NEWDAT13 _newdt10.bit._NEWDAT13 +#define NEWDT10_NEWDAT14 _newdt10.bit._NEWDAT14 +#define NEWDT10_NEWDAT15 _newdt10.bit._NEWDAT15 +#define NEWDT10_NEWDAT16 _newdt10.bit._NEWDAT16 +__IO_EXTENDED NEWDT1L0STR _newdt1l0; +#define NEWDT1L0 _newdt1l0.byte +#define NEWDT1L0_NEWDAT1 _newdt1l0.bit._NEWDAT1 +#define NEWDT1L0_NEWDAT2 _newdt1l0.bit._NEWDAT2 +#define NEWDT1L0_NEWDAT3 _newdt1l0.bit._NEWDAT3 +#define NEWDT1L0_NEWDAT4 _newdt1l0.bit._NEWDAT4 +#define NEWDT1L0_NEWDAT5 _newdt1l0.bit._NEWDAT5 +#define NEWDT1L0_NEWDAT6 _newdt1l0.bit._NEWDAT6 +#define NEWDT1L0_NEWDAT7 _newdt1l0.bit._NEWDAT7 +#define NEWDT1L0_NEWDAT8 _newdt1l0.bit._NEWDAT8 +__IO_EXTENDED NEWDT1H0STR _newdt1h0; +#define NEWDT1H0 _newdt1h0.byte +#define NEWDT1H0_NEWDAT9 _newdt1h0.bit._NEWDAT9 +#define NEWDT1H0_NEWDAT10 _newdt1h0.bit._NEWDAT10 +#define NEWDT1H0_NEWDAT11 _newdt1h0.bit._NEWDAT11 +#define NEWDT1H0_NEWDAT12 _newdt1h0.bit._NEWDAT12 +#define NEWDT1H0_NEWDAT13 _newdt1h0.bit._NEWDAT13 +#define NEWDT1H0_NEWDAT14 _newdt1h0.bit._NEWDAT14 +#define NEWDT1H0_NEWDAT15 _newdt1h0.bit._NEWDAT15 +#define NEWDT1H0_NEWDAT16 _newdt1h0.bit._NEWDAT16 +__IO_EXTENDED NEWDT20STR _newdt20; +#define NEWDT20 _newdt20.word +#define NEWDT20_NEWDAT17 _newdt20.bit._NEWDAT17 +#define NEWDT20_NEWDAT18 _newdt20.bit._NEWDAT18 +#define NEWDT20_NEWDAT19 _newdt20.bit._NEWDAT19 +#define NEWDT20_NEWDAT20 _newdt20.bit._NEWDAT20 +#define NEWDT20_NEWDAT21 _newdt20.bit._NEWDAT21 +#define NEWDT20_NEWDAT22 _newdt20.bit._NEWDAT22 +#define NEWDT20_NEWDAT23 _newdt20.bit._NEWDAT23 +#define NEWDT20_NEWDAT24 _newdt20.bit._NEWDAT24 +#define NEWDT20_NEWDAT25 _newdt20.bit._NEWDAT25 +#define NEWDT20_NEWDAT26 _newdt20.bit._NEWDAT26 +#define NEWDT20_NEWDAT27 _newdt20.bit._NEWDAT27 +#define NEWDT20_NEWDAT28 _newdt20.bit._NEWDAT28 +#define NEWDT20_NEWDAT29 _newdt20.bit._NEWDAT29 +#define NEWDT20_NEWDAT30 _newdt20.bit._NEWDAT30 +#define NEWDT20_NEWDAT31 _newdt20.bit._NEWDAT31 +#define NEWDT20_NEWDAT32 _newdt20.bit._NEWDAT32 +__IO_EXTENDED NEWDT2L0STR _newdt2l0; +#define NEWDT2L0 _newdt2l0.byte +#define NEWDT2L0_NEWDAT17 _newdt2l0.bit._NEWDAT17 +#define NEWDT2L0_NEWDAT18 _newdt2l0.bit._NEWDAT18 +#define NEWDT2L0_NEWDAT19 _newdt2l0.bit._NEWDAT19 +#define NEWDT2L0_NEWDAT20 _newdt2l0.bit._NEWDAT20 +#define NEWDT2L0_NEWDAT21 _newdt2l0.bit._NEWDAT21 +#define NEWDT2L0_NEWDAT22 _newdt2l0.bit._NEWDAT22 +#define NEWDT2L0_NEWDAT23 _newdt2l0.bit._NEWDAT23 +#define NEWDT2L0_NEWDAT24 _newdt2l0.bit._NEWDAT24 +__IO_EXTENDED NEWDT2H0STR _newdt2h0; +#define NEWDT2H0 _newdt2h0.byte +#define NEWDT2H0_NEWDAT25 _newdt2h0.bit._NEWDAT25 +#define NEWDT2H0_NEWDAT26 _newdt2h0.bit._NEWDAT26 +#define NEWDT2H0_NEWDAT27 _newdt2h0.bit._NEWDAT27 +#define NEWDT2H0_NEWDAT28 _newdt2h0.bit._NEWDAT28 +#define NEWDT2H0_NEWDAT29 _newdt2h0.bit._NEWDAT29 +#define NEWDT2H0_NEWDAT30 _newdt2h0.bit._NEWDAT30 +#define NEWDT2H0_NEWDAT31 _newdt2h0.bit._NEWDAT31 +#define NEWDT2H0_NEWDAT32 _newdt2h0.bit._NEWDAT32 +__IO_EXTENDED INTPND0STR _intpnd0; +#define INTPND0 _intpnd0.lword +#define INTPND0_INTPND1 _intpnd0.bit._INTPND1 +#define INTPND0_INTPND2 _intpnd0.bit._INTPND2 +#define INTPND0_INTPND3 _intpnd0.bit._INTPND3 +#define INTPND0_INTPND4 _intpnd0.bit._INTPND4 +#define INTPND0_INTPND5 _intpnd0.bit._INTPND5 +#define INTPND0_INTPND6 _intpnd0.bit._INTPND6 +#define INTPND0_INTPND7 _intpnd0.bit._INTPND7 +#define INTPND0_INTPND8 _intpnd0.bit._INTPND8 +#define INTPND0_INTPND9 _intpnd0.bit._INTPND9 +#define INTPND0_INTPND10 _intpnd0.bit._INTPND10 +#define INTPND0_INTPND11 _intpnd0.bit._INTPND11 +#define INTPND0_INTPND12 _intpnd0.bit._INTPND12 +#define INTPND0_INTPND13 _intpnd0.bit._INTPND13 +#define INTPND0_INTPND14 _intpnd0.bit._INTPND14 +#define INTPND0_INTPND15 _intpnd0.bit._INTPND15 +#define INTPND0_INTPND16 _intpnd0.bit._INTPND16 +#define INTPND0_INTPND17 _intpnd0.bit._INTPND17 +#define INTPND0_INTPND18 _intpnd0.bit._INTPND18 +#define INTPND0_INTPND19 _intpnd0.bit._INTPND19 +#define INTPND0_INTPND20 _intpnd0.bit._INTPND20 +#define INTPND0_INTPND21 _intpnd0.bit._INTPND21 +#define INTPND0_INTPND22 _intpnd0.bit._INTPND22 +#define INTPND0_INTPND23 _intpnd0.bit._INTPND23 +#define INTPND0_INTPND24 _intpnd0.bit._INTPND24 +#define INTPND0_INTPND25 _intpnd0.bit._INTPND25 +#define INTPND0_INTPND26 _intpnd0.bit._INTPND26 +#define INTPND0_INTPND27 _intpnd0.bit._INTPND27 +#define INTPND0_INTPND28 _intpnd0.bit._INTPND28 +#define INTPND0_INTPND29 _intpnd0.bit._INTPND29 +#define INTPND0_INTPND30 _intpnd0.bit._INTPND30 +#define INTPND0_INTPND31 _intpnd0.bit._INTPND31 +#define INTPND0_INTPND32 _intpnd0.bit._INTPND32 +#define INTPND0_INTPND _intpnd0.bitc._INTPND +__IO_EXTENDED INTPND10STR _intpnd10; +#define INTPND10 _intpnd10.word +#define INTPND10_INTPND1 _intpnd10.bit._INTPND1 +#define INTPND10_INTPND2 _intpnd10.bit._INTPND2 +#define INTPND10_INTPND3 _intpnd10.bit._INTPND3 +#define INTPND10_INTPND4 _intpnd10.bit._INTPND4 +#define INTPND10_INTPND5 _intpnd10.bit._INTPND5 +#define INTPND10_INTPND6 _intpnd10.bit._INTPND6 +#define INTPND10_INTPND7 _intpnd10.bit._INTPND7 +#define INTPND10_INTPND8 _intpnd10.bit._INTPND8 +#define INTPND10_INTPND9 _intpnd10.bit._INTPND9 +#define INTPND10_INTPND10 _intpnd10.bit._INTPND10 +#define INTPND10_INTPND11 _intpnd10.bit._INTPND11 +#define INTPND10_INTPND12 _intpnd10.bit._INTPND12 +#define INTPND10_INTPND13 _intpnd10.bit._INTPND13 +#define INTPND10_INTPND14 _intpnd10.bit._INTPND14 +#define INTPND10_INTPND15 _intpnd10.bit._INTPND15 +#define INTPND10_INTPND16 _intpnd10.bit._INTPND16 +__IO_EXTENDED INTPND1L0STR _intpnd1l0; +#define INTPND1L0 _intpnd1l0.byte +#define INTPND1L0_INTPND1 _intpnd1l0.bit._INTPND1 +#define INTPND1L0_INTPND2 _intpnd1l0.bit._INTPND2 +#define INTPND1L0_INTPND3 _intpnd1l0.bit._INTPND3 +#define INTPND1L0_INTPND4 _intpnd1l0.bit._INTPND4 +#define INTPND1L0_INTPND5 _intpnd1l0.bit._INTPND5 +#define INTPND1L0_INTPND6 _intpnd1l0.bit._INTPND6 +#define INTPND1L0_INTPND7 _intpnd1l0.bit._INTPND7 +#define INTPND1L0_INTPND8 _intpnd1l0.bit._INTPND8 +__IO_EXTENDED INTPND1H0STR _intpnd1h0; +#define INTPND1H0 _intpnd1h0.byte +#define INTPND1H0_INTPND9 _intpnd1h0.bit._INTPND9 +#define INTPND1H0_INTPND10 _intpnd1h0.bit._INTPND10 +#define INTPND1H0_INTPND11 _intpnd1h0.bit._INTPND11 +#define INTPND1H0_INTPND12 _intpnd1h0.bit._INTPND12 +#define INTPND1H0_INTPND13 _intpnd1h0.bit._INTPND13 +#define INTPND1H0_INTPND14 _intpnd1h0.bit._INTPND14 +#define INTPND1H0_INTPND15 _intpnd1h0.bit._INTPND15 +#define INTPND1H0_INTPND16 _intpnd1h0.bit._INTPND16 +__IO_EXTENDED INTPND20STR _intpnd20; +#define INTPND20 _intpnd20.word +#define INTPND20_INTPND17 _intpnd20.bit._INTPND17 +#define INTPND20_INTPND18 _intpnd20.bit._INTPND18 +#define INTPND20_INTPND19 _intpnd20.bit._INTPND19 +#define INTPND20_INTPND20 _intpnd20.bit._INTPND20 +#define INTPND20_INTPND21 _intpnd20.bit._INTPND21 +#define INTPND20_INTPND22 _intpnd20.bit._INTPND22 +#define INTPND20_INTPND23 _intpnd20.bit._INTPND23 +#define INTPND20_INTPND24 _intpnd20.bit._INTPND24 +#define INTPND20_INTPND25 _intpnd20.bit._INTPND25 +#define INTPND20_INTPND26 _intpnd20.bit._INTPND26 +#define INTPND20_INTPND27 _intpnd20.bit._INTPND27 +#define INTPND20_INTPND28 _intpnd20.bit._INTPND28 +#define INTPND20_INTPND29 _intpnd20.bit._INTPND29 +#define INTPND20_INTPND30 _intpnd20.bit._INTPND30 +#define INTPND20_INTPND31 _intpnd20.bit._INTPND31 +#define INTPND20_INTPND32 _intpnd20.bit._INTPND32 +__IO_EXTENDED INTPND2L0STR _intpnd2l0; +#define INTPND2L0 _intpnd2l0.byte +#define INTPND2L0_INTPND17 _intpnd2l0.bit._INTPND17 +#define INTPND2L0_INTPND18 _intpnd2l0.bit._INTPND18 +#define INTPND2L0_INTPND19 _intpnd2l0.bit._INTPND19 +#define INTPND2L0_INTPND20 _intpnd2l0.bit._INTPND20 +#define INTPND2L0_INTPND21 _intpnd2l0.bit._INTPND21 +#define INTPND2L0_INTPND22 _intpnd2l0.bit._INTPND22 +#define INTPND2L0_INTPND23 _intpnd2l0.bit._INTPND23 +#define INTPND2L0_INTPND24 _intpnd2l0.bit._INTPND24 +__IO_EXTENDED INTPND2H0STR _intpnd2h0; +#define INTPND2H0 _intpnd2h0.byte +#define INTPND2H0_INTPND25 _intpnd2h0.bit._INTPND25 +#define INTPND2H0_INTPND26 _intpnd2h0.bit._INTPND26 +#define INTPND2H0_INTPND27 _intpnd2h0.bit._INTPND27 +#define INTPND2H0_INTPND28 _intpnd2h0.bit._INTPND28 +#define INTPND2H0_INTPND29 _intpnd2h0.bit._INTPND29 +#define INTPND2H0_INTPND30 _intpnd2h0.bit._INTPND30 +#define INTPND2H0_INTPND31 _intpnd2h0.bit._INTPND31 +#define INTPND2H0_INTPND32 _intpnd2h0.bit._INTPND32 +__IO_EXTENDED MSGVAL0STR _msgval0; +#define MSGVAL0 _msgval0.lword +#define MSGVAL0_MSGVAL1 _msgval0.bit._MSGVAL1 +#define MSGVAL0_MSGVAL2 _msgval0.bit._MSGVAL2 +#define MSGVAL0_MSGVAL3 _msgval0.bit._MSGVAL3 +#define MSGVAL0_MSGVAL4 _msgval0.bit._MSGVAL4 +#define MSGVAL0_MSGVAL5 _msgval0.bit._MSGVAL5 +#define MSGVAL0_MSGVAL6 _msgval0.bit._MSGVAL6 +#define MSGVAL0_MSGVAL7 _msgval0.bit._MSGVAL7 +#define MSGVAL0_MSGVAL8 _msgval0.bit._MSGVAL8 +#define MSGVAL0_MSGVAL9 _msgval0.bit._MSGVAL9 +#define MSGVAL0_MSGVAL10 _msgval0.bit._MSGVAL10 +#define MSGVAL0_MSGVAL11 _msgval0.bit._MSGVAL11 +#define MSGVAL0_MSGVAL12 _msgval0.bit._MSGVAL12 +#define MSGVAL0_MSGVAL13 _msgval0.bit._MSGVAL13 +#define MSGVAL0_MSGVAL14 _msgval0.bit._MSGVAL14 +#define MSGVAL0_MSGVAL15 _msgval0.bit._MSGVAL15 +#define MSGVAL0_MSGVAL16 _msgval0.bit._MSGVAL16 +#define MSGVAL0_MSGVAL17 _msgval0.bit._MSGVAL17 +#define MSGVAL0_MSGVAL18 _msgval0.bit._MSGVAL18 +#define MSGVAL0_MSGVAL19 _msgval0.bit._MSGVAL19 +#define MSGVAL0_MSGVAL20 _msgval0.bit._MSGVAL20 +#define MSGVAL0_MSGVAL21 _msgval0.bit._MSGVAL21 +#define MSGVAL0_MSGVAL22 _msgval0.bit._MSGVAL22 +#define MSGVAL0_MSGVAL23 _msgval0.bit._MSGVAL23 +#define MSGVAL0_MSGVAL24 _msgval0.bit._MSGVAL24 +#define MSGVAL0_MSGVAL25 _msgval0.bit._MSGVAL25 +#define MSGVAL0_MSGVAL26 _msgval0.bit._MSGVAL26 +#define MSGVAL0_MSGVAL27 _msgval0.bit._MSGVAL27 +#define MSGVAL0_MSGVAL28 _msgval0.bit._MSGVAL28 +#define MSGVAL0_MSGVAL29 _msgval0.bit._MSGVAL29 +#define MSGVAL0_MSGVAL30 _msgval0.bit._MSGVAL30 +#define MSGVAL0_MSGVAL31 _msgval0.bit._MSGVAL31 +#define MSGVAL0_MSGVAL32 _msgval0.bit._MSGVAL32 +#define MSGVAL0_MSGVAL _msgval0.bitc._MSGVAL +__IO_EXTENDED MSGVAL10STR _msgval10; +#define MSGVAL10 _msgval10.word +#define MSGVAL10_MSGVAL1 _msgval10.bit._MSGVAL1 +#define MSGVAL10_MSGVAL2 _msgval10.bit._MSGVAL2 +#define MSGVAL10_MSGVAL3 _msgval10.bit._MSGVAL3 +#define MSGVAL10_MSGVAL4 _msgval10.bit._MSGVAL4 +#define MSGVAL10_MSGVAL5 _msgval10.bit._MSGVAL5 +#define MSGVAL10_MSGVAL6 _msgval10.bit._MSGVAL6 +#define MSGVAL10_MSGVAL7 _msgval10.bit._MSGVAL7 +#define MSGVAL10_MSGVAL8 _msgval10.bit._MSGVAL8 +#define MSGVAL10_MSGVAL9 _msgval10.bit._MSGVAL9 +#define MSGVAL10_MSGVAL10 _msgval10.bit._MSGVAL10 +#define MSGVAL10_MSGVAL11 _msgval10.bit._MSGVAL11 +#define MSGVAL10_MSGVAL12 _msgval10.bit._MSGVAL12 +#define MSGVAL10_MSGVAL13 _msgval10.bit._MSGVAL13 +#define MSGVAL10_MSGVAL14 _msgval10.bit._MSGVAL14 +#define MSGVAL10_MSGVAL15 _msgval10.bit._MSGVAL15 +#define MSGVAL10_MSGVAL16 _msgval10.bit._MSGVAL16 +__IO_EXTENDED MSGVAL1L0STR _msgval1l0; +#define MSGVAL1L0 _msgval1l0.byte +#define MSGVAL1L0_MSGVAL1 _msgval1l0.bit._MSGVAL1 +#define MSGVAL1L0_MSGVAL2 _msgval1l0.bit._MSGVAL2 +#define MSGVAL1L0_MSGVAL3 _msgval1l0.bit._MSGVAL3 +#define MSGVAL1L0_MSGVAL4 _msgval1l0.bit._MSGVAL4 +#define MSGVAL1L0_MSGVAL5 _msgval1l0.bit._MSGVAL5 +#define MSGVAL1L0_MSGVAL6 _msgval1l0.bit._MSGVAL6 +#define MSGVAL1L0_MSGVAL7 _msgval1l0.bit._MSGVAL7 +#define MSGVAL1L0_MSGVAL8 _msgval1l0.bit._MSGVAL8 +__IO_EXTENDED MSGVAL1H0STR _msgval1h0; +#define MSGVAL1H0 _msgval1h0.byte +#define MSGVAL1H0_MSGVAL9 _msgval1h0.bit._MSGVAL9 +#define MSGVAL1H0_MSGVAL10 _msgval1h0.bit._MSGVAL10 +#define MSGVAL1H0_MSGVAL11 _msgval1h0.bit._MSGVAL11 +#define MSGVAL1H0_MSGVAL12 _msgval1h0.bit._MSGVAL12 +#define MSGVAL1H0_MSGVAL13 _msgval1h0.bit._MSGVAL13 +#define MSGVAL1H0_MSGVAL14 _msgval1h0.bit._MSGVAL14 +#define MSGVAL1H0_MSGVAL15 _msgval1h0.bit._MSGVAL15 +#define MSGVAL1H0_MSGVAL16 _msgval1h0.bit._MSGVAL16 +__IO_EXTENDED MSGVAL20STR _msgval20; +#define MSGVAL20 _msgval20.word +#define MSGVAL20_MSGVAL17 _msgval20.bit._MSGVAL17 +#define MSGVAL20_MSGVAL18 _msgval20.bit._MSGVAL18 +#define MSGVAL20_MSGVAL19 _msgval20.bit._MSGVAL19 +#define MSGVAL20_MSGVAL20 _msgval20.bit._MSGVAL20 +#define MSGVAL20_MSGVAL21 _msgval20.bit._MSGVAL21 +#define MSGVAL20_MSGVAL22 _msgval20.bit._MSGVAL22 +#define MSGVAL20_MSGVAL23 _msgval20.bit._MSGVAL23 +#define MSGVAL20_MSGVAL24 _msgval20.bit._MSGVAL24 +#define MSGVAL20_MSGVAL25 _msgval20.bit._MSGVAL25 +#define MSGVAL20_MSGVAL26 _msgval20.bit._MSGVAL26 +#define MSGVAL20_MSGVAL27 _msgval20.bit._MSGVAL27 +#define MSGVAL20_MSGVAL28 _msgval20.bit._MSGVAL28 +#define MSGVAL20_MSGVAL29 _msgval20.bit._MSGVAL29 +#define MSGVAL20_MSGVAL30 _msgval20.bit._MSGVAL30 +#define MSGVAL20_MSGVAL31 _msgval20.bit._MSGVAL31 +#define MSGVAL20_MSGVAL32 _msgval20.bit._MSGVAL32 +__IO_EXTENDED MSGVAL2L0STR _msgval2l0; +#define MSGVAL2L0 _msgval2l0.byte +#define MSGVAL2L0_MSGVAL17 _msgval2l0.bit._MSGVAL17 +#define MSGVAL2L0_MSGVAL18 _msgval2l0.bit._MSGVAL18 +#define MSGVAL2L0_MSGVAL19 _msgval2l0.bit._MSGVAL19 +#define MSGVAL2L0_MSGVAL20 _msgval2l0.bit._MSGVAL20 +#define MSGVAL2L0_MSGVAL21 _msgval2l0.bit._MSGVAL21 +#define MSGVAL2L0_MSGVAL22 _msgval2l0.bit._MSGVAL22 +#define MSGVAL2L0_MSGVAL23 _msgval2l0.bit._MSGVAL23 +#define MSGVAL2L0_MSGVAL24 _msgval2l0.bit._MSGVAL24 +__IO_EXTENDED MSGVAL2H0STR _msgval2h0; +#define MSGVAL2H0 _msgval2h0.byte +#define MSGVAL2H0_MSGVAL25 _msgval2h0.bit._MSGVAL25 +#define MSGVAL2H0_MSGVAL26 _msgval2h0.bit._MSGVAL26 +#define MSGVAL2H0_MSGVAL27 _msgval2h0.bit._MSGVAL27 +#define MSGVAL2H0_MSGVAL28 _msgval2h0.bit._MSGVAL28 +#define MSGVAL2H0_MSGVAL29 _msgval2h0.bit._MSGVAL29 +#define MSGVAL2H0_MSGVAL30 _msgval2h0.bit._MSGVAL30 +#define MSGVAL2H0_MSGVAL31 _msgval2h0.bit._MSGVAL31 +#define MSGVAL2H0_MSGVAL32 _msgval2h0.bit._MSGVAL32 +__IO_EXTENDED COER0STR _coer0; +#define COER0 _coer0.byte +#define COER0_OE _coer0.bit._OE +__IO_EXTENDED CTRLR1STR _ctrlr1; +#define CTRLR1 _ctrlr1.word +#define CTRLR1_INIT _ctrlr1.bit._INIT +#define CTRLR1_IE _ctrlr1.bit._IE +#define CTRLR1_SIE _ctrlr1.bit._SIE +#define CTRLR1_EIE _ctrlr1.bit._EIE +#define CTRLR1_DAR _ctrlr1.bit._DAR +#define CTRLR1_CCE _ctrlr1.bit._CCE +#define CTRLR1_TEST _ctrlr1.bit._TEST +__IO_EXTENDED CTRLRL1STR _ctrlrl1; +#define CTRLRL1 _ctrlrl1.byte +#define CTRLRL1_INIT _ctrlrl1.bit._INIT +#define CTRLRL1_IE _ctrlrl1.bit._IE +#define CTRLRL1_SIE _ctrlrl1.bit._SIE +#define CTRLRL1_EIE _ctrlrl1.bit._EIE +#define CTRLRL1_DAR _ctrlrl1.bit._DAR +#define CTRLRL1_CCE _ctrlrl1.bit._CCE +#define CTRLRL1_TEST _ctrlrl1.bit._TEST +__IO_EXTENDED CTRLRH1STR _ctrlrh1; +#define CTRLRH1 _ctrlrh1.byte +__IO_EXTENDED STATR1STR _statr1; +#define STATR1 _statr1.word +#define STATR1_LEC0 _statr1.bit._LEC0 +#define STATR1_LEC1 _statr1.bit._LEC1 +#define STATR1_LEC2 _statr1.bit._LEC2 +#define STATR1_TXOK _statr1.bit._TXOK +#define STATR1_RXOK _statr1.bit._RXOK +#define STATR1_EPASS _statr1.bit._EPASS +#define STATR1_EWARN _statr1.bit._EWARN +#define STATR1_BOFF _statr1.bit._BOFF +#define STATR1_LEC _statr1.bitc._LEC +__IO_EXTENDED STATRL1STR _statrl1; +#define STATRL1 _statrl1.byte +#define STATRL1_LEC0 _statrl1.bit._LEC0 +#define STATRL1_LEC1 _statrl1.bit._LEC1 +#define STATRL1_LEC2 _statrl1.bit._LEC2 +#define STATRL1_TXOK _statrl1.bit._TXOK +#define STATRL1_RXOK _statrl1.bit._RXOK +#define STATRL1_EPASS _statrl1.bit._EPASS +#define STATRL1_EWARN _statrl1.bit._EWARN +#define STATRL1_BOFF _statrl1.bit._BOFF +#define STATRL1_LEC _statrl1.bitc._LEC +__IO_EXTENDED STATRH1STR _statrh1; +#define STATRH1 _statrh1.byte +__IO_EXTENDED ERRCNT1STR _errcnt1; +#define ERRCNT1 _errcnt1.word +#define ERRCNT1_TEC0 _errcnt1.bit._TEC0 +#define ERRCNT1_TEC1 _errcnt1.bit._TEC1 +#define ERRCNT1_TEC2 _errcnt1.bit._TEC2 +#define ERRCNT1_TEC3 _errcnt1.bit._TEC3 +#define ERRCNT1_TEC4 _errcnt1.bit._TEC4 +#define ERRCNT1_TEC5 _errcnt1.bit._TEC5 +#define ERRCNT1_TEC6 _errcnt1.bit._TEC6 +#define ERRCNT1_TEC7 _errcnt1.bit._TEC7 +#define ERRCNT1_REC0 _errcnt1.bit._REC0 +#define ERRCNT1_REC1 _errcnt1.bit._REC1 +#define ERRCNT1_REC2 _errcnt1.bit._REC2 +#define ERRCNT1_REC3 _errcnt1.bit._REC3 +#define ERRCNT1_REC4 _errcnt1.bit._REC4 +#define ERRCNT1_REC5 _errcnt1.bit._REC5 +#define ERRCNT1_REC6 _errcnt1.bit._REC6 +#define ERRCNT1_RP _errcnt1.bit._RP +#define ERRCNT1_TEC _errcnt1.bitc._TEC +#define ERRCNT1_REC _errcnt1.bitc._REC +__IO_EXTENDED ERRCNTL1STR _errcntl1; +#define ERRCNTL1 _errcntl1.byte +#define ERRCNTL1_TEC0 _errcntl1.bit._TEC0 +#define ERRCNTL1_TEC1 _errcntl1.bit._TEC1 +#define ERRCNTL1_TEC2 _errcntl1.bit._TEC2 +#define ERRCNTL1_TEC3 _errcntl1.bit._TEC3 +#define ERRCNTL1_TEC4 _errcntl1.bit._TEC4 +#define ERRCNTL1_TEC5 _errcntl1.bit._TEC5 +#define ERRCNTL1_TEC6 _errcntl1.bit._TEC6 +#define ERRCNTL1_TEC7 _errcntl1.bit._TEC7 +#define ERRCNTL1_TEC _errcntl1.bitc._TEC +__IO_EXTENDED ERRCNTH1STR _errcnth1; +#define ERRCNTH1 _errcnth1.byte +#define ERRCNTH1_REC0 _errcnth1.bit._REC0 +#define ERRCNTH1_REC1 _errcnth1.bit._REC1 +#define ERRCNTH1_REC2 _errcnth1.bit._REC2 +#define ERRCNTH1_REC3 _errcnth1.bit._REC3 +#define ERRCNTH1_REC4 _errcnth1.bit._REC4 +#define ERRCNTH1_REC5 _errcnth1.bit._REC5 +#define ERRCNTH1_REC6 _errcnth1.bit._REC6 +#define ERRCNTH1_RP _errcnth1.bit._RP +#define ERRCNTH1_REC _errcnth1.bitc._REC +__IO_EXTENDED BTR1STR _btr1; +#define BTR1 _btr1.word +#define BTR1_BRP0 _btr1.bit._BRP0 +#define BTR1_BRP1 _btr1.bit._BRP1 +#define BTR1_BRP2 _btr1.bit._BRP2 +#define BTR1_BRP3 _btr1.bit._BRP3 +#define BTR1_BRP4 _btr1.bit._BRP4 +#define BTR1_BRP5 _btr1.bit._BRP5 +#define BTR1_SJW0 _btr1.bit._SJW0 +#define BTR1_SJW1 _btr1.bit._SJW1 +#define BTR1_TSEG10 _btr1.bit._TSEG10 +#define BTR1_TSEG11 _btr1.bit._TSEG11 +#define BTR1_TSEG12 _btr1.bit._TSEG12 +#define BTR1_TSEG13 _btr1.bit._TSEG13 +#define BTR1_TSEG20 _btr1.bit._TSEG20 +#define BTR1_TSEG21 _btr1.bit._TSEG21 +#define BTR1_TSEG22 _btr1.bit._TSEG22 +#define BTR1_BRP _btr1.bitc._BRP +#define BTR1_SJW _btr1.bitc._SJW +#define BTR1_TSEG1 _btr1.bitc._TSEG1 +#define BTR1_TSEG2 _btr1.bitc._TSEG2 +__IO_EXTENDED BTRL1STR _btrl1; +#define BTRL1 _btrl1.byte +#define BTRL1_BRP0 _btrl1.bit._BRP0 +#define BTRL1_BRP1 _btrl1.bit._BRP1 +#define BTRL1_BRP2 _btrl1.bit._BRP2 +#define BTRL1_BRP3 _btrl1.bit._BRP3 +#define BTRL1_BRP4 _btrl1.bit._BRP4 +#define BTRL1_BRP5 _btrl1.bit._BRP5 +#define BTRL1_SJW0 _btrl1.bit._SJW0 +#define BTRL1_SJW1 _btrl1.bit._SJW1 +#define BTRL1_BRP _btrl1.bitc._BRP +#define BTRL1_SJW _btrl1.bitc._SJW +__IO_EXTENDED BTRH1STR _btrh1; +#define BTRH1 _btrh1.byte +#define BTRH1_TSEG10 _btrh1.bit._TSEG10 +#define BTRH1_TSEG11 _btrh1.bit._TSEG11 +#define BTRH1_TSEG12 _btrh1.bit._TSEG12 +#define BTRH1_TSEG13 _btrh1.bit._TSEG13 +#define BTRH1_TSEG20 _btrh1.bit._TSEG20 +#define BTRH1_TSEG21 _btrh1.bit._TSEG21 +#define BTRH1_TSEG22 _btrh1.bit._TSEG22 +#define BTRH1_TSEG1 _btrh1.bitc._TSEG1 +#define BTRH1_TSEG2 _btrh1.bitc._TSEG2 +__IO_EXTENDED INTR1STR _intr1; +#define INTR1 _intr1.word +#define INTR1_INTID0 _intr1.bit._INTID0 +#define INTR1_INTID1 _intr1.bit._INTID1 +#define INTR1_INTID2 _intr1.bit._INTID2 +#define INTR1_INTID3 _intr1.bit._INTID3 +#define INTR1_INTID4 _intr1.bit._INTID4 +#define INTR1_INTID5 _intr1.bit._INTID5 +#define INTR1_INTID6 _intr1.bit._INTID6 +#define INTR1_INTID7 _intr1.bit._INTID7 +#define INTR1_INTID8 _intr1.bit._INTID8 +#define INTR1_INTID9 _intr1.bit._INTID9 +#define INTR1_INTID10 _intr1.bit._INTID10 +#define INTR1_INTID11 _intr1.bit._INTID11 +#define INTR1_INTID12 _intr1.bit._INTID12 +#define INTR1_INTID13 _intr1.bit._INTID13 +#define INTR1_INTID14 _intr1.bit._INTID14 +#define INTR1_INTID15 _intr1.bit._INTID15 +#define INTR1_INTID _intr1.bitc._INTID +__IO_EXTENDED INTRL1STR _intrl1; +#define INTRL1 _intrl1.byte +#define INTRL1_INTID0 _intrl1.bit._INTID0 +#define INTRL1_INTID1 _intrl1.bit._INTID1 +#define INTRL1_INTID2 _intrl1.bit._INTID2 +#define INTRL1_INTID3 _intrl1.bit._INTID3 +#define INTRL1_INTID4 _intrl1.bit._INTID4 +#define INTRL1_INTID5 _intrl1.bit._INTID5 +#define INTRL1_INTID6 _intrl1.bit._INTID6 +#define INTRL1_INTID7 _intrl1.bit._INTID7 +__IO_EXTENDED INTRH1STR _intrh1; +#define INTRH1 _intrh1.byte +#define INTRH1_INTID8 _intrh1.bit._INTID8 +#define INTRH1_INTID9 _intrh1.bit._INTID9 +#define INTRH1_INTID10 _intrh1.bit._INTID10 +#define INTRH1_INTID11 _intrh1.bit._INTID11 +#define INTRH1_INTID12 _intrh1.bit._INTID12 +#define INTRH1_INTID13 _intrh1.bit._INTID13 +#define INTRH1_INTID14 _intrh1.bit._INTID14 +#define INTRH1_INTID15 _intrh1.bit._INTID15 +__IO_EXTENDED TESTR1STR _testr1; +#define TESTR1 _testr1.word +#define TESTR1_BASIC _testr1.bit._BASIC +#define TESTR1_SILENT _testr1.bit._SILENT +#define TESTR1_LBACK _testr1.bit._LBACK +#define TESTR1_TX0 _testr1.bit._TX0 +#define TESTR1_TX1 _testr1.bit._TX1 +#define TESTR1_RX _testr1.bit._RX +__IO_EXTENDED TESTRL1STR _testrl1; +#define TESTRL1 _testrl1.byte +#define TESTRL1_BASIC _testrl1.bit._BASIC +#define TESTRL1_SILENT _testrl1.bit._SILENT +#define TESTRL1_LBACK _testrl1.bit._LBACK +#define TESTRL1_TX0 _testrl1.bit._TX0 +#define TESTRL1_TX1 _testrl1.bit._TX1 +#define TESTRL1_RX _testrl1.bit._RX +__IO_EXTENDED TESTRH1STR _testrh1; +#define TESTRH1 _testrh1.byte +__IO_EXTENDED BRPER1STR _brper1; +#define BRPER1 _brper1.word +#define BRPER1_BRPE0 _brper1.bit._BRPE0 +#define BRPER1_BRPE1 _brper1.bit._BRPE1 +#define BRPER1_BRPE2 _brper1.bit._BRPE2 +#define BRPER1_BRPE3 _brper1.bit._BRPE3 +#define BRPER1_BRPE _brper1.bitc._BRPE +__IO_EXTENDED BRPERL1STR _brperl1; +#define BRPERL1 _brperl1.byte +#define BRPERL1_BRPE0 _brperl1.bit._BRPE0 +#define BRPERL1_BRPE1 _brperl1.bit._BRPE1 +#define BRPERL1_BRPE2 _brperl1.bit._BRPE2 +#define BRPERL1_BRPE3 _brperl1.bit._BRPE3 +#define BRPERL1_BRPE _brperl1.bitc._BRPE +__IO_EXTENDED BRPERH1STR _brperh1; +#define BRPERH1 _brperh1.byte +__IO_EXTENDED IF1CREQ1STR _if1creq1; +#define IF1CREQ1 _if1creq1.word +#define IF1CREQ1_MSGN0 _if1creq1.bit._MSGN0 +#define IF1CREQ1_MSGN1 _if1creq1.bit._MSGN1 +#define IF1CREQ1_MSGN2 _if1creq1.bit._MSGN2 +#define IF1CREQ1_MSGN3 _if1creq1.bit._MSGN3 +#define IF1CREQ1_MSGN4 _if1creq1.bit._MSGN4 +#define IF1CREQ1_MSGN5 _if1creq1.bit._MSGN5 +#define IF1CREQ1_MSGN6 _if1creq1.bit._MSGN6 +#define IF1CREQ1_MSGN7 _if1creq1.bit._MSGN7 +#define IF1CREQ1_BUSY _if1creq1.bit._BUSY +__IO_EXTENDED IF1CREQL1STR _if1creql1; +#define IF1CREQL1 _if1creql1.byte +#define IF1CREQL1_MSGN0 _if1creql1.bit._MSGN0 +#define IF1CREQL1_MSGN1 _if1creql1.bit._MSGN1 +#define IF1CREQL1_MSGN2 _if1creql1.bit._MSGN2 +#define IF1CREQL1_MSGN3 _if1creql1.bit._MSGN3 +#define IF1CREQL1_MSGN4 _if1creql1.bit._MSGN4 +#define IF1CREQL1_MSGN5 _if1creql1.bit._MSGN5 +#define IF1CREQL1_MSGN6 _if1creql1.bit._MSGN6 +#define IF1CREQL1_MSGN7 _if1creql1.bit._MSGN7 +__IO_EXTENDED IF1CREQH1STR _if1creqh1; +#define IF1CREQH1 _if1creqh1.byte +#define IF1CREQH1_BUSY _if1creqh1.bit._BUSY +__IO_EXTENDED IF1CMSK1STR _if1cmsk1; +#define IF1CMSK1 _if1cmsk1.word +#define IF1CMSK1_DATAB _if1cmsk1.bit._DATAB +#define IF1CMSK1_DATAA _if1cmsk1.bit._DATAA +#define IF1CMSK1_TXREQ _if1cmsk1.bit._TXREQ +#define IF1CMSK1_CIP _if1cmsk1.bit._CIP +#define IF1CMSK1_CONTROL _if1cmsk1.bit._CONTROL +#define IF1CMSK1_ARB _if1cmsk1.bit._ARB +#define IF1CMSK1_MASK _if1cmsk1.bit._MASK +#define IF1CMSK1_WRRD _if1cmsk1.bit._WRRD +__IO_EXTENDED IF1CMSKL1STR _if1cmskl1; +#define IF1CMSKL1 _if1cmskl1.byte +#define IF1CMSKL1_DATAB _if1cmskl1.bit._DATAB +#define IF1CMSKL1_DATAA _if1cmskl1.bit._DATAA +#define IF1CMSKL1_TXREQ _if1cmskl1.bit._TXREQ +#define IF1CMSKL1_CIP _if1cmskl1.bit._CIP +#define IF1CMSKL1_CONTROL _if1cmskl1.bit._CONTROL +#define IF1CMSKL1_ARB _if1cmskl1.bit._ARB +#define IF1CMSKL1_MASK _if1cmskl1.bit._MASK +#define IF1CMSKL1_WRRD _if1cmskl1.bit._WRRD +__IO_EXTENDED IF1CMSKH1STR _if1cmskh1; +#define IF1CMSKH1 _if1cmskh1.byte +__IO_EXTENDED IF1MSK1STR _if1msk1; +#define IF1MSK1 _if1msk1.lword +#define IF1MSK1_MSK0 _if1msk1.bit._MSK0 +#define IF1MSK1_MSK1 _if1msk1.bit._MSK1 +#define IF1MSK1_MSK2 _if1msk1.bit._MSK2 +#define IF1MSK1_MSK3 _if1msk1.bit._MSK3 +#define IF1MSK1_MSK4 _if1msk1.bit._MSK4 +#define IF1MSK1_MSK5 _if1msk1.bit._MSK5 +#define IF1MSK1_MSK6 _if1msk1.bit._MSK6 +#define IF1MSK1_MSK7 _if1msk1.bit._MSK7 +#define IF1MSK1_MSK8 _if1msk1.bit._MSK8 +#define IF1MSK1_MSK9 _if1msk1.bit._MSK9 +#define IF1MSK1_MSK10 _if1msk1.bit._MSK10 +#define IF1MSK1_MSK11 _if1msk1.bit._MSK11 +#define IF1MSK1_MSK12 _if1msk1.bit._MSK12 +#define IF1MSK1_MSK13 _if1msk1.bit._MSK13 +#define IF1MSK1_MSK14 _if1msk1.bit._MSK14 +#define IF1MSK1_MSK15 _if1msk1.bit._MSK15 +#define IF1MSK1_MSK16 _if1msk1.bit._MSK16 +#define IF1MSK1_MSK17 _if1msk1.bit._MSK17 +#define IF1MSK1_MSK18 _if1msk1.bit._MSK18 +#define IF1MSK1_MSK19 _if1msk1.bit._MSK19 +#define IF1MSK1_MSK20 _if1msk1.bit._MSK20 +#define IF1MSK1_MSK21 _if1msk1.bit._MSK21 +#define IF1MSK1_MSK22 _if1msk1.bit._MSK22 +#define IF1MSK1_MSK23 _if1msk1.bit._MSK23 +#define IF1MSK1_MSK24 _if1msk1.bit._MSK24 +#define IF1MSK1_MSK25 _if1msk1.bit._MSK25 +#define IF1MSK1_MSK26 _if1msk1.bit._MSK26 +#define IF1MSK1_MSK27 _if1msk1.bit._MSK27 +#define IF1MSK1_MSK28 _if1msk1.bit._MSK28 +#define IF1MSK1_MDIR _if1msk1.bit._MDIR +#define IF1MSK1_MXTD _if1msk1.bit._MXTD +#define IF1MSK1_MSK _if1msk1.bitc._MSK +__IO_EXTENDED IF1MSK11STR _if1msk11; +#define IF1MSK11 _if1msk11.word +#define IF1MSK11_MSK0 _if1msk11.bit._MSK0 +#define IF1MSK11_MSK1 _if1msk11.bit._MSK1 +#define IF1MSK11_MSK2 _if1msk11.bit._MSK2 +#define IF1MSK11_MSK3 _if1msk11.bit._MSK3 +#define IF1MSK11_MSK4 _if1msk11.bit._MSK4 +#define IF1MSK11_MSK5 _if1msk11.bit._MSK5 +#define IF1MSK11_MSK6 _if1msk11.bit._MSK6 +#define IF1MSK11_MSK7 _if1msk11.bit._MSK7 +#define IF1MSK11_MSK8 _if1msk11.bit._MSK8 +#define IF1MSK11_MSK9 _if1msk11.bit._MSK9 +#define IF1MSK11_MSK10 _if1msk11.bit._MSK10 +#define IF1MSK11_MSK11 _if1msk11.bit._MSK11 +#define IF1MSK11_MSK12 _if1msk11.bit._MSK12 +#define IF1MSK11_MSK13 _if1msk11.bit._MSK13 +#define IF1MSK11_MSK14 _if1msk11.bit._MSK14 +#define IF1MSK11_MSK15 _if1msk11.bit._MSK15 +__IO_EXTENDED IF1MSK1L1STR _if1msk1l1; +#define IF1MSK1L1 _if1msk1l1.byte +#define IF1MSK1L1_MSK0 _if1msk1l1.bit._MSK0 +#define IF1MSK1L1_MSK1 _if1msk1l1.bit._MSK1 +#define IF1MSK1L1_MSK2 _if1msk1l1.bit._MSK2 +#define IF1MSK1L1_MSK3 _if1msk1l1.bit._MSK3 +#define IF1MSK1L1_MSK4 _if1msk1l1.bit._MSK4 +#define IF1MSK1L1_MSK5 _if1msk1l1.bit._MSK5 +#define IF1MSK1L1_MSK6 _if1msk1l1.bit._MSK6 +#define IF1MSK1L1_MSK7 _if1msk1l1.bit._MSK7 +__IO_EXTENDED IF1MSK1H1STR _if1msk1h1; +#define IF1MSK1H1 _if1msk1h1.byte +#define IF1MSK1H1_MSK8 _if1msk1h1.bit._MSK8 +#define IF1MSK1H1_MSK9 _if1msk1h1.bit._MSK9 +#define IF1MSK1H1_MSK10 _if1msk1h1.bit._MSK10 +#define IF1MSK1H1_MSK11 _if1msk1h1.bit._MSK11 +#define IF1MSK1H1_MSK12 _if1msk1h1.bit._MSK12 +#define IF1MSK1H1_MSK13 _if1msk1h1.bit._MSK13 +#define IF1MSK1H1_MSK14 _if1msk1h1.bit._MSK14 +#define IF1MSK1H1_MSK15 _if1msk1h1.bit._MSK15 +__IO_EXTENDED IF1MSK21STR _if1msk21; +#define IF1MSK21 _if1msk21.word +#define IF1MSK21_MSK16 _if1msk21.bit._MSK16 +#define IF1MSK21_MSK17 _if1msk21.bit._MSK17 +#define IF1MSK21_MSK18 _if1msk21.bit._MSK18 +#define IF1MSK21_MSK19 _if1msk21.bit._MSK19 +#define IF1MSK21_MSK20 _if1msk21.bit._MSK20 +#define IF1MSK21_MSK21 _if1msk21.bit._MSK21 +#define IF1MSK21_MSK22 _if1msk21.bit._MSK22 +#define IF1MSK21_MSK23 _if1msk21.bit._MSK23 +#define IF1MSK21_MSK24 _if1msk21.bit._MSK24 +#define IF1MSK21_MSK25 _if1msk21.bit._MSK25 +#define IF1MSK21_MSK26 _if1msk21.bit._MSK26 +#define IF1MSK21_MSK27 _if1msk21.bit._MSK27 +#define IF1MSK21_MSK28 _if1msk21.bit._MSK28 +#define IF1MSK21_MDIR _if1msk21.bit._MDIR +#define IF1MSK21_MXTD _if1msk21.bit._MXTD +__IO_EXTENDED IF1MSK2L1STR _if1msk2l1; +#define IF1MSK2L1 _if1msk2l1.byte +#define IF1MSK2L1_MSK16 _if1msk2l1.bit._MSK16 +#define IF1MSK2L1_MSK17 _if1msk2l1.bit._MSK17 +#define IF1MSK2L1_MSK18 _if1msk2l1.bit._MSK18 +#define IF1MSK2L1_MSK19 _if1msk2l1.bit._MSK19 +#define IF1MSK2L1_MSK20 _if1msk2l1.bit._MSK20 +#define IF1MSK2L1_MSK21 _if1msk2l1.bit._MSK21 +#define IF1MSK2L1_MSK22 _if1msk2l1.bit._MSK22 +#define IF1MSK2L1_MSK23 _if1msk2l1.bit._MSK23 +__IO_EXTENDED IF1MSK2H1STR _if1msk2h1; +#define IF1MSK2H1 _if1msk2h1.byte +#define IF1MSK2H1_MSK24 _if1msk2h1.bit._MSK24 +#define IF1MSK2H1_MSK25 _if1msk2h1.bit._MSK25 +#define IF1MSK2H1_MSK26 _if1msk2h1.bit._MSK26 +#define IF1MSK2H1_MSK27 _if1msk2h1.bit._MSK27 +#define IF1MSK2H1_MSK28 _if1msk2h1.bit._MSK28 +#define IF1MSK2H1_MDIR _if1msk2h1.bit._MDIR +#define IF1MSK2H1_MXTD _if1msk2h1.bit._MXTD +__IO_EXTENDED IF1ARB1STR _if1arb1; +#define IF1ARB1 _if1arb1.lword +#define IF1ARB1_ID0 _if1arb1.bit._ID0 +#define IF1ARB1_ID1 _if1arb1.bit._ID1 +#define IF1ARB1_ID2 _if1arb1.bit._ID2 +#define IF1ARB1_ID3 _if1arb1.bit._ID3 +#define IF1ARB1_ID4 _if1arb1.bit._ID4 +#define IF1ARB1_ID5 _if1arb1.bit._ID5 +#define IF1ARB1_ID6 _if1arb1.bit._ID6 +#define IF1ARB1_ID7 _if1arb1.bit._ID7 +#define IF1ARB1_ID8 _if1arb1.bit._ID8 +#define IF1ARB1_ID9 _if1arb1.bit._ID9 +#define IF1ARB1_ID10 _if1arb1.bit._ID10 +#define IF1ARB1_ID11 _if1arb1.bit._ID11 +#define IF1ARB1_ID12 _if1arb1.bit._ID12 +#define IF1ARB1_ID13 _if1arb1.bit._ID13 +#define IF1ARB1_ID14 _if1arb1.bit._ID14 +#define IF1ARB1_ID15 _if1arb1.bit._ID15 +#define IF1ARB1_ID16 _if1arb1.bit._ID16 +#define IF1ARB1_ID17 _if1arb1.bit._ID17 +#define IF1ARB1_ID18 _if1arb1.bit._ID18 +#define IF1ARB1_ID19 _if1arb1.bit._ID19 +#define IF1ARB1_ID20 _if1arb1.bit._ID20 +#define IF1ARB1_ID21 _if1arb1.bit._ID21 +#define IF1ARB1_ID22 _if1arb1.bit._ID22 +#define IF1ARB1_ID23 _if1arb1.bit._ID23 +#define IF1ARB1_ID24 _if1arb1.bit._ID24 +#define IF1ARB1_ID25 _if1arb1.bit._ID25 +#define IF1ARB1_ID26 _if1arb1.bit._ID26 +#define IF1ARB1_ID27 _if1arb1.bit._ID27 +#define IF1ARB1_ID28 _if1arb1.bit._ID28 +#define IF1ARB1_DIR _if1arb1.bit._DIR +#define IF1ARB1_XTD _if1arb1.bit._XTD +#define IF1ARB1_MSGVAL _if1arb1.bit._MSGVAL +#define IF1ARB1_ID _if1arb1.bitc._ID +__IO_EXTENDED IF1ARB11STR _if1arb11; +#define IF1ARB11 _if1arb11.word +#define IF1ARB11_ID0 _if1arb11.bit._ID0 +#define IF1ARB11_ID1 _if1arb11.bit._ID1 +#define IF1ARB11_ID2 _if1arb11.bit._ID2 +#define IF1ARB11_ID3 _if1arb11.bit._ID3 +#define IF1ARB11_ID4 _if1arb11.bit._ID4 +#define IF1ARB11_ID5 _if1arb11.bit._ID5 +#define IF1ARB11_ID6 _if1arb11.bit._ID6 +#define IF1ARB11_ID7 _if1arb11.bit._ID7 +#define IF1ARB11_ID8 _if1arb11.bit._ID8 +#define IF1ARB11_ID9 _if1arb11.bit._ID9 +#define IF1ARB11_ID10 _if1arb11.bit._ID10 +#define IF1ARB11_ID11 _if1arb11.bit._ID11 +#define IF1ARB11_ID12 _if1arb11.bit._ID12 +#define IF1ARB11_ID13 _if1arb11.bit._ID13 +#define IF1ARB11_ID14 _if1arb11.bit._ID14 +#define IF1ARB11_ID15 _if1arb11.bit._ID15 +__IO_EXTENDED IF1ARB1L1STR _if1arb1l1; +#define IF1ARB1L1 _if1arb1l1.byte +#define IF1ARB1L1_ID0 _if1arb1l1.bit._ID0 +#define IF1ARB1L1_ID1 _if1arb1l1.bit._ID1 +#define IF1ARB1L1_ID2 _if1arb1l1.bit._ID2 +#define IF1ARB1L1_ID3 _if1arb1l1.bit._ID3 +#define IF1ARB1L1_ID4 _if1arb1l1.bit._ID4 +#define IF1ARB1L1_ID5 _if1arb1l1.bit._ID5 +#define IF1ARB1L1_ID6 _if1arb1l1.bit._ID6 +#define IF1ARB1L1_ID7 _if1arb1l1.bit._ID7 +__IO_EXTENDED IF1ARB1H1STR _if1arb1h1; +#define IF1ARB1H1 _if1arb1h1.byte +#define IF1ARB1H1_ID8 _if1arb1h1.bit._ID8 +#define IF1ARB1H1_ID9 _if1arb1h1.bit._ID9 +#define IF1ARB1H1_ID10 _if1arb1h1.bit._ID10 +#define IF1ARB1H1_ID11 _if1arb1h1.bit._ID11 +#define IF1ARB1H1_ID12 _if1arb1h1.bit._ID12 +#define IF1ARB1H1_ID13 _if1arb1h1.bit._ID13 +#define IF1ARB1H1_ID14 _if1arb1h1.bit._ID14 +#define IF1ARB1H1_ID15 _if1arb1h1.bit._ID15 +__IO_EXTENDED IF1ARB21STR _if1arb21; +#define IF1ARB21 _if1arb21.word +#define IF1ARB21_ID16 _if1arb21.bit._ID16 +#define IF1ARB21_ID17 _if1arb21.bit._ID17 +#define IF1ARB21_ID18 _if1arb21.bit._ID18 +#define IF1ARB21_ID19 _if1arb21.bit._ID19 +#define IF1ARB21_ID20 _if1arb21.bit._ID20 +#define IF1ARB21_ID21 _if1arb21.bit._ID21 +#define IF1ARB21_ID22 _if1arb21.bit._ID22 +#define IF1ARB21_ID23 _if1arb21.bit._ID23 +#define IF1ARB21_ID24 _if1arb21.bit._ID24 +#define IF1ARB21_ID25 _if1arb21.bit._ID25 +#define IF1ARB21_ID26 _if1arb21.bit._ID26 +#define IF1ARB21_ID27 _if1arb21.bit._ID27 +#define IF1ARB21_ID28 _if1arb21.bit._ID28 +#define IF1ARB21_DIR _if1arb21.bit._DIR +#define IF1ARB21_XTD _if1arb21.bit._XTD +#define IF1ARB21_MSGVAL _if1arb21.bit._MSGVAL +__IO_EXTENDED IF1ARB2L1STR _if1arb2l1; +#define IF1ARB2L1 _if1arb2l1.byte +#define IF1ARB2L1_ID16 _if1arb2l1.bit._ID16 +#define IF1ARB2L1_ID17 _if1arb2l1.bit._ID17 +#define IF1ARB2L1_ID18 _if1arb2l1.bit._ID18 +#define IF1ARB2L1_ID19 _if1arb2l1.bit._ID19 +#define IF1ARB2L1_ID20 _if1arb2l1.bit._ID20 +#define IF1ARB2L1_ID21 _if1arb2l1.bit._ID21 +#define IF1ARB2L1_ID22 _if1arb2l1.bit._ID22 +#define IF1ARB2L1_ID23 _if1arb2l1.bit._ID23 +__IO_EXTENDED IF1ARB2H1STR _if1arb2h1; +#define IF1ARB2H1 _if1arb2h1.byte +#define IF1ARB2H1_ID24 _if1arb2h1.bit._ID24 +#define IF1ARB2H1_ID25 _if1arb2h1.bit._ID25 +#define IF1ARB2H1_ID26 _if1arb2h1.bit._ID26 +#define IF1ARB2H1_ID27 _if1arb2h1.bit._ID27 +#define IF1ARB2H1_ID28 _if1arb2h1.bit._ID28 +#define IF1ARB2H1_DIR _if1arb2h1.bit._DIR +#define IF1ARB2H1_XTD _if1arb2h1.bit._XTD +#define IF1ARB2H1_MSGVAL _if1arb2h1.bit._MSGVAL +__IO_EXTENDED IF1MCTR1STR _if1mctr1; +#define IF1MCTR1 _if1mctr1.word +#define IF1MCTR1_DLC0 _if1mctr1.bit._DLC0 +#define IF1MCTR1_DLC1 _if1mctr1.bit._DLC1 +#define IF1MCTR1_DLC2 _if1mctr1.bit._DLC2 +#define IF1MCTR1_DLC3 _if1mctr1.bit._DLC3 +#define IF1MCTR1_EOB _if1mctr1.bit._EOB +#define IF1MCTR1_TXRQST _if1mctr1.bit._TXRQST +#define IF1MCTR1_RMTEN _if1mctr1.bit._RMTEN +#define IF1MCTR1_RXIE _if1mctr1.bit._RXIE +#define IF1MCTR1_TXIE _if1mctr1.bit._TXIE +#define IF1MCTR1_UMASK _if1mctr1.bit._UMASK +#define IF1MCTR1_INTPND _if1mctr1.bit._INTPND +#define IF1MCTR1_MSGLST _if1mctr1.bit._MSGLST +#define IF1MCTR1_NEWDAT _if1mctr1.bit._NEWDAT +#define IF1MCTR1_DLC _if1mctr1.bitc._DLC +__IO_EXTENDED IF1MCTRL1STR _if1mctrl1; +#define IF1MCTRL1 _if1mctrl1.byte +#define IF1MCTRL1_DLC0 _if1mctrl1.bit._DLC0 +#define IF1MCTRL1_DLC1 _if1mctrl1.bit._DLC1 +#define IF1MCTRL1_DLC2 _if1mctrl1.bit._DLC2 +#define IF1MCTRL1_DLC3 _if1mctrl1.bit._DLC3 +#define IF1MCTRL1_EOB _if1mctrl1.bit._EOB +#define IF1MCTRL1_DLC _if1mctrl1.bitc._DLC +__IO_EXTENDED IF1MCTRH1STR _if1mctrh1; +#define IF1MCTRH1 _if1mctrh1.byte +#define IF1MCTRH1_TXRQST _if1mctrh1.bit._TXRQST +#define IF1MCTRH1_RMTEN _if1mctrh1.bit._RMTEN +#define IF1MCTRH1_RXIE _if1mctrh1.bit._RXIE +#define IF1MCTRH1_TXIE _if1mctrh1.bit._TXIE +#define IF1MCTRH1_UMASK _if1mctrh1.bit._UMASK +#define IF1MCTRH1_INTPND _if1mctrh1.bit._INTPND +#define IF1MCTRH1_MSGLST _if1mctrh1.bit._MSGLST +#define IF1MCTRH1_NEWDAT _if1mctrh1.bit._NEWDAT +__IO_EXTENDED IF1DTA1STR _if1dta1; +#define IF1DTA1 _if1dta1.lword +__IO_EXTENDED IF1DTA11STR _if1dta11; +#define IF1DTA11 _if1dta11.word +__IO_EXTENDED IF1DTA1L1STR _if1dta1l1; +#define IF1DTA1L1 _if1dta1l1.byte +__IO_EXTENDED IF1DTA1H1STR _if1dta1h1; +#define IF1DTA1H1 _if1dta1h1.byte +__IO_EXTENDED IF1DTA21STR _if1dta21; +#define IF1DTA21 _if1dta21.word +__IO_EXTENDED IF1DTA2L1STR _if1dta2l1; +#define IF1DTA2L1 _if1dta2l1.byte +__IO_EXTENDED IF1DTA2H1STR _if1dta2h1; +#define IF1DTA2H1 _if1dta2h1.byte +__IO_EXTENDED IF1DTB1STR _if1dtb1; +#define IF1DTB1 _if1dtb1.lword +__IO_EXTENDED IF1DTB11STR _if1dtb11; +#define IF1DTB11 _if1dtb11.word +__IO_EXTENDED IF1DTB1L1STR _if1dtb1l1; +#define IF1DTB1L1 _if1dtb1l1.byte +__IO_EXTENDED IF1DTB1H1STR _if1dtb1h1; +#define IF1DTB1H1 _if1dtb1h1.byte +__IO_EXTENDED IF1DTB21STR _if1dtb21; +#define IF1DTB21 _if1dtb21.word +__IO_EXTENDED IF1DTB2L1STR _if1dtb2l1; +#define IF1DTB2L1 _if1dtb2l1.byte +__IO_EXTENDED IF1DTB2H1STR _if1dtb2h1; +#define IF1DTB2H1 _if1dtb2h1.byte +__IO_EXTENDED IF2CREQ1STR _if2creq1; +#define IF2CREQ1 _if2creq1.word +#define IF2CREQ1_MSGN0 _if2creq1.bit._MSGN0 +#define IF2CREQ1_MSGN1 _if2creq1.bit._MSGN1 +#define IF2CREQ1_MSGN2 _if2creq1.bit._MSGN2 +#define IF2CREQ1_MSGN3 _if2creq1.bit._MSGN3 +#define IF2CREQ1_MSGN4 _if2creq1.bit._MSGN4 +#define IF2CREQ1_MSGN5 _if2creq1.bit._MSGN5 +#define IF2CREQ1_MSGN6 _if2creq1.bit._MSGN6 +#define IF2CREQ1_MSGN7 _if2creq1.bit._MSGN7 +#define IF2CREQ1_BUSY _if2creq1.bit._BUSY +__IO_EXTENDED IF2CREQL1STR _if2creql1; +#define IF2CREQL1 _if2creql1.byte +#define IF2CREQL1_MSGN0 _if2creql1.bit._MSGN0 +#define IF2CREQL1_MSGN1 _if2creql1.bit._MSGN1 +#define IF2CREQL1_MSGN2 _if2creql1.bit._MSGN2 +#define IF2CREQL1_MSGN3 _if2creql1.bit._MSGN3 +#define IF2CREQL1_MSGN4 _if2creql1.bit._MSGN4 +#define IF2CREQL1_MSGN5 _if2creql1.bit._MSGN5 +#define IF2CREQL1_MSGN6 _if2creql1.bit._MSGN6 +#define IF2CREQL1_MSGN7 _if2creql1.bit._MSGN7 +__IO_EXTENDED IF2CREQH1STR _if2creqh1; +#define IF2CREQH1 _if2creqh1.byte +#define IF2CREQH1_BUSY _if2creqh1.bit._BUSY +__IO_EXTENDED IF2CMSK1STR _if2cmsk1; +#define IF2CMSK1 _if2cmsk1.word +#define IF2CMSK1_DATAB _if2cmsk1.bit._DATAB +#define IF2CMSK1_DATAA _if2cmsk1.bit._DATAA +#define IF2CMSK1_TXREQ _if2cmsk1.bit._TXREQ +#define IF2CMSK1_CIP _if2cmsk1.bit._CIP +#define IF2CMSK1_CONTROL _if2cmsk1.bit._CONTROL +#define IF2CMSK1_ARB _if2cmsk1.bit._ARB +#define IF2CMSK1_MASK _if2cmsk1.bit._MASK +#define IF2CMSK1_WRRD _if2cmsk1.bit._WRRD +__IO_EXTENDED IF2CMSKL1STR _if2cmskl1; +#define IF2CMSKL1 _if2cmskl1.byte +#define IF2CMSKL1_DATAB _if2cmskl1.bit._DATAB +#define IF2CMSKL1_DATAA _if2cmskl1.bit._DATAA +#define IF2CMSKL1_TXREQ _if2cmskl1.bit._TXREQ +#define IF2CMSKL1_CIP _if2cmskl1.bit._CIP +#define IF2CMSKL1_CONTROL _if2cmskl1.bit._CONTROL +#define IF2CMSKL1_ARB _if2cmskl1.bit._ARB +#define IF2CMSKL1_MASK _if2cmskl1.bit._MASK +#define IF2CMSKL1_WRRD _if2cmskl1.bit._WRRD +__IO_EXTENDED IF2CMSKH1STR _if2cmskh1; +#define IF2CMSKH1 _if2cmskh1.byte +__IO_EXTENDED IF2MSK1STR _if2msk1; +#define IF2MSK1 _if2msk1.lword +#define IF2MSK1_MSK0 _if2msk1.bit._MSK0 +#define IF2MSK1_MSK1 _if2msk1.bit._MSK1 +#define IF2MSK1_MSK2 _if2msk1.bit._MSK2 +#define IF2MSK1_MSK3 _if2msk1.bit._MSK3 +#define IF2MSK1_MSK4 _if2msk1.bit._MSK4 +#define IF2MSK1_MSK5 _if2msk1.bit._MSK5 +#define IF2MSK1_MSK6 _if2msk1.bit._MSK6 +#define IF2MSK1_MSK7 _if2msk1.bit._MSK7 +#define IF2MSK1_MSK8 _if2msk1.bit._MSK8 +#define IF2MSK1_MSK9 _if2msk1.bit._MSK9 +#define IF2MSK1_MSK10 _if2msk1.bit._MSK10 +#define IF2MSK1_MSK11 _if2msk1.bit._MSK11 +#define IF2MSK1_MSK12 _if2msk1.bit._MSK12 +#define IF2MSK1_MSK13 _if2msk1.bit._MSK13 +#define IF2MSK1_MSK14 _if2msk1.bit._MSK14 +#define IF2MSK1_MSK15 _if2msk1.bit._MSK15 +#define IF2MSK1_MSK16 _if2msk1.bit._MSK16 +#define IF2MSK1_MSK17 _if2msk1.bit._MSK17 +#define IF2MSK1_MSK18 _if2msk1.bit._MSK18 +#define IF2MSK1_MSK19 _if2msk1.bit._MSK19 +#define IF2MSK1_MSK20 _if2msk1.bit._MSK20 +#define IF2MSK1_MSK21 _if2msk1.bit._MSK21 +#define IF2MSK1_MSK22 _if2msk1.bit._MSK22 +#define IF2MSK1_MSK23 _if2msk1.bit._MSK23 +#define IF2MSK1_MSK24 _if2msk1.bit._MSK24 +#define IF2MSK1_MSK25 _if2msk1.bit._MSK25 +#define IF2MSK1_MSK26 _if2msk1.bit._MSK26 +#define IF2MSK1_MSK27 _if2msk1.bit._MSK27 +#define IF2MSK1_MSK28 _if2msk1.bit._MSK28 +#define IF2MSK1_MDIR _if2msk1.bit._MDIR +#define IF2MSK1_MXTD _if2msk1.bit._MXTD +#define IF2MSK1_MSK _if2msk1.bitc._MSK +__IO_EXTENDED IF2MSK11STR _if2msk11; +#define IF2MSK11 _if2msk11.word +#define IF2MSK11_MSK0 _if2msk11.bit._MSK0 +#define IF2MSK11_MSK1 _if2msk11.bit._MSK1 +#define IF2MSK11_MSK2 _if2msk11.bit._MSK2 +#define IF2MSK11_MSK3 _if2msk11.bit._MSK3 +#define IF2MSK11_MSK4 _if2msk11.bit._MSK4 +#define IF2MSK11_MSK5 _if2msk11.bit._MSK5 +#define IF2MSK11_MSK6 _if2msk11.bit._MSK6 +#define IF2MSK11_MSK7 _if2msk11.bit._MSK7 +#define IF2MSK11_MSK8 _if2msk11.bit._MSK8 +#define IF2MSK11_MSK9 _if2msk11.bit._MSK9 +#define IF2MSK11_MSK10 _if2msk11.bit._MSK10 +#define IF2MSK11_MSK11 _if2msk11.bit._MSK11 +#define IF2MSK11_MSK12 _if2msk11.bit._MSK12 +#define IF2MSK11_MSK13 _if2msk11.bit._MSK13 +#define IF2MSK11_MSK14 _if2msk11.bit._MSK14 +#define IF2MSK11_MSK15 _if2msk11.bit._MSK15 +__IO_EXTENDED IF2MSK1L1STR _if2msk1l1; +#define IF2MSK1L1 _if2msk1l1.byte +#define IF2MSK1L1_MSK0 _if2msk1l1.bit._MSK0 +#define IF2MSK1L1_MSK1 _if2msk1l1.bit._MSK1 +#define IF2MSK1L1_MSK2 _if2msk1l1.bit._MSK2 +#define IF2MSK1L1_MSK3 _if2msk1l1.bit._MSK3 +#define IF2MSK1L1_MSK4 _if2msk1l1.bit._MSK4 +#define IF2MSK1L1_MSK5 _if2msk1l1.bit._MSK5 +#define IF2MSK1L1_MSK6 _if2msk1l1.bit._MSK6 +#define IF2MSK1L1_MSK7 _if2msk1l1.bit._MSK7 +__IO_EXTENDED IF2MSK1H1STR _if2msk1h1; +#define IF2MSK1H1 _if2msk1h1.byte +#define IF2MSK1H1_MSK8 _if2msk1h1.bit._MSK8 +#define IF2MSK1H1_MSK9 _if2msk1h1.bit._MSK9 +#define IF2MSK1H1_MSK10 _if2msk1h1.bit._MSK10 +#define IF2MSK1H1_MSK11 _if2msk1h1.bit._MSK11 +#define IF2MSK1H1_MSK12 _if2msk1h1.bit._MSK12 +#define IF2MSK1H1_MSK13 _if2msk1h1.bit._MSK13 +#define IF2MSK1H1_MSK14 _if2msk1h1.bit._MSK14 +#define IF2MSK1H1_MSK15 _if2msk1h1.bit._MSK15 +__IO_EXTENDED IF2MSK21STR _if2msk21; +#define IF2MSK21 _if2msk21.word +#define IF2MSK21_MSK16 _if2msk21.bit._MSK16 +#define IF2MSK21_MSK17 _if2msk21.bit._MSK17 +#define IF2MSK21_MSK18 _if2msk21.bit._MSK18 +#define IF2MSK21_MSK19 _if2msk21.bit._MSK19 +#define IF2MSK21_MSK20 _if2msk21.bit._MSK20 +#define IF2MSK21_MSK21 _if2msk21.bit._MSK21 +#define IF2MSK21_MSK22 _if2msk21.bit._MSK22 +#define IF2MSK21_MSK23 _if2msk21.bit._MSK23 +#define IF2MSK21_MSK24 _if2msk21.bit._MSK24 +#define IF2MSK21_MSK25 _if2msk21.bit._MSK25 +#define IF2MSK21_MSK26 _if2msk21.bit._MSK26 +#define IF2MSK21_MSK27 _if2msk21.bit._MSK27 +#define IF2MSK21_MSK28 _if2msk21.bit._MSK28 +#define IF2MSK21_MDIR _if2msk21.bit._MDIR +#define IF2MSK21_MXTD _if2msk21.bit._MXTD +__IO_EXTENDED IF2MSK2L1STR _if2msk2l1; +#define IF2MSK2L1 _if2msk2l1.byte +#define IF2MSK2L1_MSK16 _if2msk2l1.bit._MSK16 +#define IF2MSK2L1_MSK17 _if2msk2l1.bit._MSK17 +#define IF2MSK2L1_MSK18 _if2msk2l1.bit._MSK18 +#define IF2MSK2L1_MSK19 _if2msk2l1.bit._MSK19 +#define IF2MSK2L1_MSK20 _if2msk2l1.bit._MSK20 +#define IF2MSK2L1_MSK21 _if2msk2l1.bit._MSK21 +#define IF2MSK2L1_MSK22 _if2msk2l1.bit._MSK22 +#define IF2MSK2L1_MSK23 _if2msk2l1.bit._MSK23 +__IO_EXTENDED IF2MSK2H1STR _if2msk2h1; +#define IF2MSK2H1 _if2msk2h1.byte +#define IF2MSK2H1_MSK24 _if2msk2h1.bit._MSK24 +#define IF2MSK2H1_MSK25 _if2msk2h1.bit._MSK25 +#define IF2MSK2H1_MSK26 _if2msk2h1.bit._MSK26 +#define IF2MSK2H1_MSK27 _if2msk2h1.bit._MSK27 +#define IF2MSK2H1_MSK28 _if2msk2h1.bit._MSK28 +#define IF2MSK2H1_MDIR _if2msk2h1.bit._MDIR +#define IF2MSK2H1_MXTD _if2msk2h1.bit._MXTD +__IO_EXTENDED IF2ARB1STR _if2arb1; +#define IF2ARB1 _if2arb1.lword +#define IF2ARB1_ID0 _if2arb1.bit._ID0 +#define IF2ARB1_ID1 _if2arb1.bit._ID1 +#define IF2ARB1_ID2 _if2arb1.bit._ID2 +#define IF2ARB1_ID3 _if2arb1.bit._ID3 +#define IF2ARB1_ID4 _if2arb1.bit._ID4 +#define IF2ARB1_ID5 _if2arb1.bit._ID5 +#define IF2ARB1_ID6 _if2arb1.bit._ID6 +#define IF2ARB1_ID7 _if2arb1.bit._ID7 +#define IF2ARB1_ID8 _if2arb1.bit._ID8 +#define IF2ARB1_ID9 _if2arb1.bit._ID9 +#define IF2ARB1_ID10 _if2arb1.bit._ID10 +#define IF2ARB1_ID11 _if2arb1.bit._ID11 +#define IF2ARB1_ID12 _if2arb1.bit._ID12 +#define IF2ARB1_ID13 _if2arb1.bit._ID13 +#define IF2ARB1_ID14 _if2arb1.bit._ID14 +#define IF2ARB1_ID15 _if2arb1.bit._ID15 +#define IF2ARB1_ID16 _if2arb1.bit._ID16 +#define IF2ARB1_ID17 _if2arb1.bit._ID17 +#define IF2ARB1_ID18 _if2arb1.bit._ID18 +#define IF2ARB1_ID19 _if2arb1.bit._ID19 +#define IF2ARB1_ID20 _if2arb1.bit._ID20 +#define IF2ARB1_ID21 _if2arb1.bit._ID21 +#define IF2ARB1_ID22 _if2arb1.bit._ID22 +#define IF2ARB1_ID23 _if2arb1.bit._ID23 +#define IF2ARB1_ID24 _if2arb1.bit._ID24 +#define IF2ARB1_ID25 _if2arb1.bit._ID25 +#define IF2ARB1_ID26 _if2arb1.bit._ID26 +#define IF2ARB1_ID27 _if2arb1.bit._ID27 +#define IF2ARB1_ID28 _if2arb1.bit._ID28 +#define IF2ARB1_DIR _if2arb1.bit._DIR +#define IF2ARB1_XTD _if2arb1.bit._XTD +#define IF2ARB1_MSGVAL _if2arb1.bit._MSGVAL +#define IF2ARB1_ID _if2arb1.bitc._ID +__IO_EXTENDED IF2ARB11STR _if2arb11; +#define IF2ARB11 _if2arb11.word +#define IF2ARB11_ID0 _if2arb11.bit._ID0 +#define IF2ARB11_ID1 _if2arb11.bit._ID1 +#define IF2ARB11_ID2 _if2arb11.bit._ID2 +#define IF2ARB11_ID3 _if2arb11.bit._ID3 +#define IF2ARB11_ID4 _if2arb11.bit._ID4 +#define IF2ARB11_ID5 _if2arb11.bit._ID5 +#define IF2ARB11_ID6 _if2arb11.bit._ID6 +#define IF2ARB11_ID7 _if2arb11.bit._ID7 +#define IF2ARB11_ID8 _if2arb11.bit._ID8 +#define IF2ARB11_ID9 _if2arb11.bit._ID9 +#define IF2ARB11_ID10 _if2arb11.bit._ID10 +#define IF2ARB11_ID11 _if2arb11.bit._ID11 +#define IF2ARB11_ID12 _if2arb11.bit._ID12 +#define IF2ARB11_ID13 _if2arb11.bit._ID13 +#define IF2ARB11_ID14 _if2arb11.bit._ID14 +#define IF2ARB11_ID15 _if2arb11.bit._ID15 +__IO_EXTENDED IF2ARB1L1STR _if2arb1l1; +#define IF2ARB1L1 _if2arb1l1.byte +#define IF2ARB1L1_ID0 _if2arb1l1.bit._ID0 +#define IF2ARB1L1_ID1 _if2arb1l1.bit._ID1 +#define IF2ARB1L1_ID2 _if2arb1l1.bit._ID2 +#define IF2ARB1L1_ID3 _if2arb1l1.bit._ID3 +#define IF2ARB1L1_ID4 _if2arb1l1.bit._ID4 +#define IF2ARB1L1_ID5 _if2arb1l1.bit._ID5 +#define IF2ARB1L1_ID6 _if2arb1l1.bit._ID6 +#define IF2ARB1L1_ID7 _if2arb1l1.bit._ID7 +__IO_EXTENDED IF2ARB1H1STR _if2arb1h1; +#define IF2ARB1H1 _if2arb1h1.byte +#define IF2ARB1H1_ID8 _if2arb1h1.bit._ID8 +#define IF2ARB1H1_ID9 _if2arb1h1.bit._ID9 +#define IF2ARB1H1_ID10 _if2arb1h1.bit._ID10 +#define IF2ARB1H1_ID11 _if2arb1h1.bit._ID11 +#define IF2ARB1H1_ID12 _if2arb1h1.bit._ID12 +#define IF2ARB1H1_ID13 _if2arb1h1.bit._ID13 +#define IF2ARB1H1_ID14 _if2arb1h1.bit._ID14 +#define IF2ARB1H1_ID15 _if2arb1h1.bit._ID15 +__IO_EXTENDED IF2ARB21STR _if2arb21; +#define IF2ARB21 _if2arb21.word +#define IF2ARB21_ID16 _if2arb21.bit._ID16 +#define IF2ARB21_ID17 _if2arb21.bit._ID17 +#define IF2ARB21_ID18 _if2arb21.bit._ID18 +#define IF2ARB21_ID19 _if2arb21.bit._ID19 +#define IF2ARB21_ID20 _if2arb21.bit._ID20 +#define IF2ARB21_ID21 _if2arb21.bit._ID21 +#define IF2ARB21_ID22 _if2arb21.bit._ID22 +#define IF2ARB21_ID23 _if2arb21.bit._ID23 +#define IF2ARB21_ID24 _if2arb21.bit._ID24 +#define IF2ARB21_ID25 _if2arb21.bit._ID25 +#define IF2ARB21_ID26 _if2arb21.bit._ID26 +#define IF2ARB21_ID27 _if2arb21.bit._ID27 +#define IF2ARB21_ID28 _if2arb21.bit._ID28 +#define IF2ARB21_DIR _if2arb21.bit._DIR +#define IF2ARB21_XTD _if2arb21.bit._XTD +#define IF2ARB21_MSGVAL _if2arb21.bit._MSGVAL +__IO_EXTENDED IF2ARB2L1STR _if2arb2l1; +#define IF2ARB2L1 _if2arb2l1.byte +#define IF2ARB2L1_ID16 _if2arb2l1.bit._ID16 +#define IF2ARB2L1_ID17 _if2arb2l1.bit._ID17 +#define IF2ARB2L1_ID18 _if2arb2l1.bit._ID18 +#define IF2ARB2L1_ID19 _if2arb2l1.bit._ID19 +#define IF2ARB2L1_ID20 _if2arb2l1.bit._ID20 +#define IF2ARB2L1_ID21 _if2arb2l1.bit._ID21 +#define IF2ARB2L1_ID22 _if2arb2l1.bit._ID22 +#define IF2ARB2L1_ID23 _if2arb2l1.bit._ID23 +__IO_EXTENDED IF2ARB2H1STR _if2arb2h1; +#define IF2ARB2H1 _if2arb2h1.byte +#define IF2ARB2H1_ID24 _if2arb2h1.bit._ID24 +#define IF2ARB2H1_ID25 _if2arb2h1.bit._ID25 +#define IF2ARB2H1_ID26 _if2arb2h1.bit._ID26 +#define IF2ARB2H1_ID27 _if2arb2h1.bit._ID27 +#define IF2ARB2H1_ID28 _if2arb2h1.bit._ID28 +#define IF2ARB2H1_DIR _if2arb2h1.bit._DIR +#define IF2ARB2H1_XTD _if2arb2h1.bit._XTD +#define IF2ARB2H1_MSGVAL _if2arb2h1.bit._MSGVAL +__IO_EXTENDED IF2MCTR1STR _if2mctr1; +#define IF2MCTR1 _if2mctr1.word +#define IF2MCTR1_DLC0 _if2mctr1.bit._DLC0 +#define IF2MCTR1_DLC1 _if2mctr1.bit._DLC1 +#define IF2MCTR1_DLC2 _if2mctr1.bit._DLC2 +#define IF2MCTR1_DLC3 _if2mctr1.bit._DLC3 +#define IF2MCTR1_EOB _if2mctr1.bit._EOB +#define IF2MCTR1_TXRQST _if2mctr1.bit._TXRQST +#define IF2MCTR1_RMTEN _if2mctr1.bit._RMTEN +#define IF2MCTR1_RXIE _if2mctr1.bit._RXIE +#define IF2MCTR1_TXIE _if2mctr1.bit._TXIE +#define IF2MCTR1_UMASK _if2mctr1.bit._UMASK +#define IF2MCTR1_INTPND _if2mctr1.bit._INTPND +#define IF2MCTR1_MSGLST _if2mctr1.bit._MSGLST +#define IF2MCTR1_NEWDAT _if2mctr1.bit._NEWDAT +#define IF2MCTR1_DLC _if2mctr1.bitc._DLC +__IO_EXTENDED IF2MCTRL1STR _if2mctrl1; +#define IF2MCTRL1 _if2mctrl1.byte +#define IF2MCTRL1_DLC0 _if2mctrl1.bit._DLC0 +#define IF2MCTRL1_DLC1 _if2mctrl1.bit._DLC1 +#define IF2MCTRL1_DLC2 _if2mctrl1.bit._DLC2 +#define IF2MCTRL1_DLC3 _if2mctrl1.bit._DLC3 +#define IF2MCTRL1_EOB _if2mctrl1.bit._EOB +#define IF2MCTRL1_DLC _if2mctrl1.bitc._DLC +__IO_EXTENDED IF2MCTRH1STR _if2mctrh1; +#define IF2MCTRH1 _if2mctrh1.byte +#define IF2MCTRH1_TXRQST _if2mctrh1.bit._TXRQST +#define IF2MCTRH1_RMTEN _if2mctrh1.bit._RMTEN +#define IF2MCTRH1_RXIE _if2mctrh1.bit._RXIE +#define IF2MCTRH1_TXIE _if2mctrh1.bit._TXIE +#define IF2MCTRH1_UMASK _if2mctrh1.bit._UMASK +#define IF2MCTRH1_INTPND _if2mctrh1.bit._INTPND +#define IF2MCTRH1_MSGLST _if2mctrh1.bit._MSGLST +#define IF2MCTRH1_NEWDAT _if2mctrh1.bit._NEWDAT +__IO_EXTENDED IF2DTA1STR _if2dta1; +#define IF2DTA1 _if2dta1.lword +__IO_EXTENDED IF2DTA11STR _if2dta11; +#define IF2DTA11 _if2dta11.word +__IO_EXTENDED IF2DTA1L1STR _if2dta1l1; +#define IF2DTA1L1 _if2dta1l1.byte +__IO_EXTENDED IF2DTA1H1STR _if2dta1h1; +#define IF2DTA1H1 _if2dta1h1.byte +__IO_EXTENDED IF2DTA21STR _if2dta21; +#define IF2DTA21 _if2dta21.word +__IO_EXTENDED IF2DTA2L1STR _if2dta2l1; +#define IF2DTA2L1 _if2dta2l1.byte +__IO_EXTENDED IF2DTA2H1STR _if2dta2h1; +#define IF2DTA2H1 _if2dta2h1.byte +__IO_EXTENDED IF2DTB1STR _if2dtb1; +#define IF2DTB1 _if2dtb1.lword +__IO_EXTENDED IF2DTB11STR _if2dtb11; +#define IF2DTB11 _if2dtb11.word +__IO_EXTENDED IF2DTB1L1STR _if2dtb1l1; +#define IF2DTB1L1 _if2dtb1l1.byte +__IO_EXTENDED IF2DTB1H1STR _if2dtb1h1; +#define IF2DTB1H1 _if2dtb1h1.byte +__IO_EXTENDED IF2DTB21STR _if2dtb21; +#define IF2DTB21 _if2dtb21.word +__IO_EXTENDED IF2DTB2L1STR _if2dtb2l1; +#define IF2DTB2L1 _if2dtb2l1.byte +__IO_EXTENDED IF2DTB2H1STR _if2dtb2h1; +#define IF2DTB2H1 _if2dtb2h1.byte +__IO_EXTENDED TREQR1STR _treqr1; +#define TREQR1 _treqr1.lword +#define TREQR1_TXRQST1 _treqr1.bit._TXRQST1 +#define TREQR1_TXRQST2 _treqr1.bit._TXRQST2 +#define TREQR1_TXRQST3 _treqr1.bit._TXRQST3 +#define TREQR1_TXRQST4 _treqr1.bit._TXRQST4 +#define TREQR1_TXRQST5 _treqr1.bit._TXRQST5 +#define TREQR1_TXRQST6 _treqr1.bit._TXRQST6 +#define TREQR1_TXRQST7 _treqr1.bit._TXRQST7 +#define TREQR1_TXRQST8 _treqr1.bit._TXRQST8 +#define TREQR1_TXRQST9 _treqr1.bit._TXRQST9 +#define TREQR1_TXRQST10 _treqr1.bit._TXRQST10 +#define TREQR1_TXRQST11 _treqr1.bit._TXRQST11 +#define TREQR1_TXRQST12 _treqr1.bit._TXRQST12 +#define TREQR1_TXRQST13 _treqr1.bit._TXRQST13 +#define TREQR1_TXRQST14 _treqr1.bit._TXRQST14 +#define TREQR1_TXRQST15 _treqr1.bit._TXRQST15 +#define TREQR1_TXRQST16 _treqr1.bit._TXRQST16 +#define TREQR1_TXRQST17 _treqr1.bit._TXRQST17 +#define TREQR1_TXRQST18 _treqr1.bit._TXRQST18 +#define TREQR1_TXRQST19 _treqr1.bit._TXRQST19 +#define TREQR1_TXRQST20 _treqr1.bit._TXRQST20 +#define TREQR1_TXRQST21 _treqr1.bit._TXRQST21 +#define TREQR1_TXRQST22 _treqr1.bit._TXRQST22 +#define TREQR1_TXRQST23 _treqr1.bit._TXRQST23 +#define TREQR1_TXRQST24 _treqr1.bit._TXRQST24 +#define TREQR1_TXRQST25 _treqr1.bit._TXRQST25 +#define TREQR1_TXRQST26 _treqr1.bit._TXRQST26 +#define TREQR1_TXRQST27 _treqr1.bit._TXRQST27 +#define TREQR1_TXRQST28 _treqr1.bit._TXRQST28 +#define TREQR1_TXRQST29 _treqr1.bit._TXRQST29 +#define TREQR1_TXRQST30 _treqr1.bit._TXRQST30 +#define TREQR1_TXRQST31 _treqr1.bit._TXRQST31 +#define TREQR1_TXRQST32 _treqr1.bit._TXRQST32 +#define TREQR1_TXRQST _treqr1.bitc._TXRQST +__IO_EXTENDED TREQR11STR _treqr11; +#define TREQR11 _treqr11.word +#define TREQR11_TXRQST1 _treqr11.bit._TXRQST1 +#define TREQR11_TXRQST2 _treqr11.bit._TXRQST2 +#define TREQR11_TXRQST3 _treqr11.bit._TXRQST3 +#define TREQR11_TXRQST4 _treqr11.bit._TXRQST4 +#define TREQR11_TXRQST5 _treqr11.bit._TXRQST5 +#define TREQR11_TXRQST6 _treqr11.bit._TXRQST6 +#define TREQR11_TXRQST7 _treqr11.bit._TXRQST7 +#define TREQR11_TXRQST8 _treqr11.bit._TXRQST8 +#define TREQR11_TXRQST9 _treqr11.bit._TXRQST9 +#define TREQR11_TXRQST10 _treqr11.bit._TXRQST10 +#define TREQR11_TXRQST11 _treqr11.bit._TXRQST11 +#define TREQR11_TXRQST12 _treqr11.bit._TXRQST12 +#define TREQR11_TXRQST13 _treqr11.bit._TXRQST13 +#define TREQR11_TXRQST14 _treqr11.bit._TXRQST14 +#define TREQR11_TXRQST15 _treqr11.bit._TXRQST15 +#define TREQR11_TXRQST16 _treqr11.bit._TXRQST16 +__IO_EXTENDED TREQR1L1STR _treqr1l1; +#define TREQR1L1 _treqr1l1.byte +#define TREQR1L1_TXRQST1 _treqr1l1.bit._TXRQST1 +#define TREQR1L1_TXRQST2 _treqr1l1.bit._TXRQST2 +#define TREQR1L1_TXRQST3 _treqr1l1.bit._TXRQST3 +#define TREQR1L1_TXRQST4 _treqr1l1.bit._TXRQST4 +#define TREQR1L1_TXRQST5 _treqr1l1.bit._TXRQST5 +#define TREQR1L1_TXRQST6 _treqr1l1.bit._TXRQST6 +#define TREQR1L1_TXRQST7 _treqr1l1.bit._TXRQST7 +#define TREQR1L1_TXRQST8 _treqr1l1.bit._TXRQST8 +__IO_EXTENDED TREQR1H1STR _treqr1h1; +#define TREQR1H1 _treqr1h1.byte +#define TREQR1H1_TXRQST9 _treqr1h1.bit._TXRQST9 +#define TREQR1H1_TXRQST10 _treqr1h1.bit._TXRQST10 +#define TREQR1H1_TXRQST11 _treqr1h1.bit._TXRQST11 +#define TREQR1H1_TXRQST12 _treqr1h1.bit._TXRQST12 +#define TREQR1H1_TXRQST13 _treqr1h1.bit._TXRQST13 +#define TREQR1H1_TXRQST14 _treqr1h1.bit._TXRQST14 +#define TREQR1H1_TXRQST15 _treqr1h1.bit._TXRQST15 +#define TREQR1H1_TXRQST16 _treqr1h1.bit._TXRQST16 +__IO_EXTENDED TREQR21STR _treqr21; +#define TREQR21 _treqr21.word +#define TREQR21_TXRQST17 _treqr21.bit._TXRQST17 +#define TREQR21_TXRQST18 _treqr21.bit._TXRQST18 +#define TREQR21_TXRQST19 _treqr21.bit._TXRQST19 +#define TREQR21_TXRQST20 _treqr21.bit._TXRQST20 +#define TREQR21_TXRQST21 _treqr21.bit._TXRQST21 +#define TREQR21_TXRQST22 _treqr21.bit._TXRQST22 +#define TREQR21_TXRQST23 _treqr21.bit._TXRQST23 +#define TREQR21_TXRQST24 _treqr21.bit._TXRQST24 +#define TREQR21_TXRQST25 _treqr21.bit._TXRQST25 +#define TREQR21_TXRQST26 _treqr21.bit._TXRQST26 +#define TREQR21_TXRQST27 _treqr21.bit._TXRQST27 +#define TREQR21_TXRQST28 _treqr21.bit._TXRQST28 +#define TREQR21_TXRQST29 _treqr21.bit._TXRQST29 +#define TREQR21_TXRQST30 _treqr21.bit._TXRQST30 +#define TREQR21_TXRQST31 _treqr21.bit._TXRQST31 +#define TREQR21_TXRQST32 _treqr21.bit._TXRQST32 +__IO_EXTENDED TREQR2L1STR _treqr2l1; +#define TREQR2L1 _treqr2l1.byte +#define TREQR2L1_TXRQST17 _treqr2l1.bit._TXRQST17 +#define TREQR2L1_TXRQST18 _treqr2l1.bit._TXRQST18 +#define TREQR2L1_TXRQST19 _treqr2l1.bit._TXRQST19 +#define TREQR2L1_TXRQST20 _treqr2l1.bit._TXRQST20 +#define TREQR2L1_TXRQST21 _treqr2l1.bit._TXRQST21 +#define TREQR2L1_TXRQST22 _treqr2l1.bit._TXRQST22 +#define TREQR2L1_TXRQST23 _treqr2l1.bit._TXRQST23 +#define TREQR2L1_TXRQST24 _treqr2l1.bit._TXRQST24 +__IO_EXTENDED TREQR2H1STR _treqr2h1; +#define TREQR2H1 _treqr2h1.byte +#define TREQR2H1_TXRQST25 _treqr2h1.bit._TXRQST25 +#define TREQR2H1_TXRQST26 _treqr2h1.bit._TXRQST26 +#define TREQR2H1_TXRQST27 _treqr2h1.bit._TXRQST27 +#define TREQR2H1_TXRQST28 _treqr2h1.bit._TXRQST28 +#define TREQR2H1_TXRQST29 _treqr2h1.bit._TXRQST29 +#define TREQR2H1_TXRQST30 _treqr2h1.bit._TXRQST30 +#define TREQR2H1_TXRQST31 _treqr2h1.bit._TXRQST31 +#define TREQR2H1_TXRQST32 _treqr2h1.bit._TXRQST32 +__IO_EXTENDED NEWDT1STR _newdt1; +#define NEWDT1 _newdt1.lword +#define NEWDT1_NEWDAT1 _newdt1.bit._NEWDAT1 +#define NEWDT1_NEWDAT2 _newdt1.bit._NEWDAT2 +#define NEWDT1_NEWDAT3 _newdt1.bit._NEWDAT3 +#define NEWDT1_NEWDAT4 _newdt1.bit._NEWDAT4 +#define NEWDT1_NEWDAT5 _newdt1.bit._NEWDAT5 +#define NEWDT1_NEWDAT6 _newdt1.bit._NEWDAT6 +#define NEWDT1_NEWDAT7 _newdt1.bit._NEWDAT7 +#define NEWDT1_NEWDAT8 _newdt1.bit._NEWDAT8 +#define NEWDT1_NEWDAT9 _newdt1.bit._NEWDAT9 +#define NEWDT1_NEWDAT10 _newdt1.bit._NEWDAT10 +#define NEWDT1_NEWDAT11 _newdt1.bit._NEWDAT11 +#define NEWDT1_NEWDAT12 _newdt1.bit._NEWDAT12 +#define NEWDT1_NEWDAT13 _newdt1.bit._NEWDAT13 +#define NEWDT1_NEWDAT14 _newdt1.bit._NEWDAT14 +#define NEWDT1_NEWDAT15 _newdt1.bit._NEWDAT15 +#define NEWDT1_NEWDAT16 _newdt1.bit._NEWDAT16 +#define NEWDT1_NEWDAT17 _newdt1.bit._NEWDAT17 +#define NEWDT1_NEWDAT18 _newdt1.bit._NEWDAT18 +#define NEWDT1_NEWDAT19 _newdt1.bit._NEWDAT19 +#define NEWDT1_NEWDAT20 _newdt1.bit._NEWDAT20 +#define NEWDT1_NEWDAT21 _newdt1.bit._NEWDAT21 +#define NEWDT1_NEWDAT22 _newdt1.bit._NEWDAT22 +#define NEWDT1_NEWDAT23 _newdt1.bit._NEWDAT23 +#define NEWDT1_NEWDAT24 _newdt1.bit._NEWDAT24 +#define NEWDT1_NEWDAT25 _newdt1.bit._NEWDAT25 +#define NEWDT1_NEWDAT26 _newdt1.bit._NEWDAT26 +#define NEWDT1_NEWDAT27 _newdt1.bit._NEWDAT27 +#define NEWDT1_NEWDAT28 _newdt1.bit._NEWDAT28 +#define NEWDT1_NEWDAT29 _newdt1.bit._NEWDAT29 +#define NEWDT1_NEWDAT30 _newdt1.bit._NEWDAT30 +#define NEWDT1_NEWDAT31 _newdt1.bit._NEWDAT31 +#define NEWDT1_NEWDAT32 _newdt1.bit._NEWDAT32 +#define NEWDT1_NEWDAT _newdt1.bitc._NEWDAT +__IO_EXTENDED NEWDT11STR _newdt11; +#define NEWDT11 _newdt11.word +#define NEWDT11_NEWDAT1 _newdt11.bit._NEWDAT1 +#define NEWDT11_NEWDAT2 _newdt11.bit._NEWDAT2 +#define NEWDT11_NEWDAT3 _newdt11.bit._NEWDAT3 +#define NEWDT11_NEWDAT4 _newdt11.bit._NEWDAT4 +#define NEWDT11_NEWDAT5 _newdt11.bit._NEWDAT5 +#define NEWDT11_NEWDAT6 _newdt11.bit._NEWDAT6 +#define NEWDT11_NEWDAT7 _newdt11.bit._NEWDAT7 +#define NEWDT11_NEWDAT8 _newdt11.bit._NEWDAT8 +#define NEWDT11_NEWDAT9 _newdt11.bit._NEWDAT9 +#define NEWDT11_NEWDAT10 _newdt11.bit._NEWDAT10 +#define NEWDT11_NEWDAT11 _newdt11.bit._NEWDAT11 +#define NEWDT11_NEWDAT12 _newdt11.bit._NEWDAT12 +#define NEWDT11_NEWDAT13 _newdt11.bit._NEWDAT13 +#define NEWDT11_NEWDAT14 _newdt11.bit._NEWDAT14 +#define NEWDT11_NEWDAT15 _newdt11.bit._NEWDAT15 +#define NEWDT11_NEWDAT16 _newdt11.bit._NEWDAT16 +__IO_EXTENDED NEWDT1L1STR _newdt1l1; +#define NEWDT1L1 _newdt1l1.byte +#define NEWDT1L1_NEWDAT1 _newdt1l1.bit._NEWDAT1 +#define NEWDT1L1_NEWDAT2 _newdt1l1.bit._NEWDAT2 +#define NEWDT1L1_NEWDAT3 _newdt1l1.bit._NEWDAT3 +#define NEWDT1L1_NEWDAT4 _newdt1l1.bit._NEWDAT4 +#define NEWDT1L1_NEWDAT5 _newdt1l1.bit._NEWDAT5 +#define NEWDT1L1_NEWDAT6 _newdt1l1.bit._NEWDAT6 +#define NEWDT1L1_NEWDAT7 _newdt1l1.bit._NEWDAT7 +#define NEWDT1L1_NEWDAT8 _newdt1l1.bit._NEWDAT8 +__IO_EXTENDED NEWDT1H1STR _newdt1h1; +#define NEWDT1H1 _newdt1h1.byte +#define NEWDT1H1_NEWDAT9 _newdt1h1.bit._NEWDAT9 +#define NEWDT1H1_NEWDAT10 _newdt1h1.bit._NEWDAT10 +#define NEWDT1H1_NEWDAT11 _newdt1h1.bit._NEWDAT11 +#define NEWDT1H1_NEWDAT12 _newdt1h1.bit._NEWDAT12 +#define NEWDT1H1_NEWDAT13 _newdt1h1.bit._NEWDAT13 +#define NEWDT1H1_NEWDAT14 _newdt1h1.bit._NEWDAT14 +#define NEWDT1H1_NEWDAT15 _newdt1h1.bit._NEWDAT15 +#define NEWDT1H1_NEWDAT16 _newdt1h1.bit._NEWDAT16 +__IO_EXTENDED NEWDT21STR _newdt21; +#define NEWDT21 _newdt21.word +#define NEWDT21_NEWDAT17 _newdt21.bit._NEWDAT17 +#define NEWDT21_NEWDAT18 _newdt21.bit._NEWDAT18 +#define NEWDT21_NEWDAT19 _newdt21.bit._NEWDAT19 +#define NEWDT21_NEWDAT20 _newdt21.bit._NEWDAT20 +#define NEWDT21_NEWDAT21 _newdt21.bit._NEWDAT21 +#define NEWDT21_NEWDAT22 _newdt21.bit._NEWDAT22 +#define NEWDT21_NEWDAT23 _newdt21.bit._NEWDAT23 +#define NEWDT21_NEWDAT24 _newdt21.bit._NEWDAT24 +#define NEWDT21_NEWDAT25 _newdt21.bit._NEWDAT25 +#define NEWDT21_NEWDAT26 _newdt21.bit._NEWDAT26 +#define NEWDT21_NEWDAT27 _newdt21.bit._NEWDAT27 +#define NEWDT21_NEWDAT28 _newdt21.bit._NEWDAT28 +#define NEWDT21_NEWDAT29 _newdt21.bit._NEWDAT29 +#define NEWDT21_NEWDAT30 _newdt21.bit._NEWDAT30 +#define NEWDT21_NEWDAT31 _newdt21.bit._NEWDAT31 +#define NEWDT21_NEWDAT32 _newdt21.bit._NEWDAT32 +__IO_EXTENDED NEWDT2L1STR _newdt2l1; +#define NEWDT2L1 _newdt2l1.byte +#define NEWDT2L1_NEWDAT17 _newdt2l1.bit._NEWDAT17 +#define NEWDT2L1_NEWDAT18 _newdt2l1.bit._NEWDAT18 +#define NEWDT2L1_NEWDAT19 _newdt2l1.bit._NEWDAT19 +#define NEWDT2L1_NEWDAT20 _newdt2l1.bit._NEWDAT20 +#define NEWDT2L1_NEWDAT21 _newdt2l1.bit._NEWDAT21 +#define NEWDT2L1_NEWDAT22 _newdt2l1.bit._NEWDAT22 +#define NEWDT2L1_NEWDAT23 _newdt2l1.bit._NEWDAT23 +#define NEWDT2L1_NEWDAT24 _newdt2l1.bit._NEWDAT24 +__IO_EXTENDED NEWDT2H1STR _newdt2h1; +#define NEWDT2H1 _newdt2h1.byte +#define NEWDT2H1_NEWDAT25 _newdt2h1.bit._NEWDAT25 +#define NEWDT2H1_NEWDAT26 _newdt2h1.bit._NEWDAT26 +#define NEWDT2H1_NEWDAT27 _newdt2h1.bit._NEWDAT27 +#define NEWDT2H1_NEWDAT28 _newdt2h1.bit._NEWDAT28 +#define NEWDT2H1_NEWDAT29 _newdt2h1.bit._NEWDAT29 +#define NEWDT2H1_NEWDAT30 _newdt2h1.bit._NEWDAT30 +#define NEWDT2H1_NEWDAT31 _newdt2h1.bit._NEWDAT31 +#define NEWDT2H1_NEWDAT32 _newdt2h1.bit._NEWDAT32 +__IO_EXTENDED INTPND1STR _intpnd1; +#define INTPND1 _intpnd1.lword +#define INTPND1_INTPND1 _intpnd1.bit._INTPND1 +#define INTPND1_INTPND2 _intpnd1.bit._INTPND2 +#define INTPND1_INTPND3 _intpnd1.bit._INTPND3 +#define INTPND1_INTPND4 _intpnd1.bit._INTPND4 +#define INTPND1_INTPND5 _intpnd1.bit._INTPND5 +#define INTPND1_INTPND6 _intpnd1.bit._INTPND6 +#define INTPND1_INTPND7 _intpnd1.bit._INTPND7 +#define INTPND1_INTPND8 _intpnd1.bit._INTPND8 +#define INTPND1_INTPND9 _intpnd1.bit._INTPND9 +#define INTPND1_INTPND10 _intpnd1.bit._INTPND10 +#define INTPND1_INTPND11 _intpnd1.bit._INTPND11 +#define INTPND1_INTPND12 _intpnd1.bit._INTPND12 +#define INTPND1_INTPND13 _intpnd1.bit._INTPND13 +#define INTPND1_INTPND14 _intpnd1.bit._INTPND14 +#define INTPND1_INTPND15 _intpnd1.bit._INTPND15 +#define INTPND1_INTPND16 _intpnd1.bit._INTPND16 +#define INTPND1_INTPND17 _intpnd1.bit._INTPND17 +#define INTPND1_INTPND18 _intpnd1.bit._INTPND18 +#define INTPND1_INTPND19 _intpnd1.bit._INTPND19 +#define INTPND1_INTPND20 _intpnd1.bit._INTPND20 +#define INTPND1_INTPND21 _intpnd1.bit._INTPND21 +#define INTPND1_INTPND22 _intpnd1.bit._INTPND22 +#define INTPND1_INTPND23 _intpnd1.bit._INTPND23 +#define INTPND1_INTPND24 _intpnd1.bit._INTPND24 +#define INTPND1_INTPND25 _intpnd1.bit._INTPND25 +#define INTPND1_INTPND26 _intpnd1.bit._INTPND26 +#define INTPND1_INTPND27 _intpnd1.bit._INTPND27 +#define INTPND1_INTPND28 _intpnd1.bit._INTPND28 +#define INTPND1_INTPND29 _intpnd1.bit._INTPND29 +#define INTPND1_INTPND30 _intpnd1.bit._INTPND30 +#define INTPND1_INTPND31 _intpnd1.bit._INTPND31 +#define INTPND1_INTPND32 _intpnd1.bit._INTPND32 +#define INTPND1_INTPND _intpnd1.bitc._INTPND +__IO_EXTENDED INTPND11STR _intpnd11; +#define INTPND11 _intpnd11.word +#define INTPND11_INTPND1 _intpnd11.bit._INTPND1 +#define INTPND11_INTPND2 _intpnd11.bit._INTPND2 +#define INTPND11_INTPND3 _intpnd11.bit._INTPND3 +#define INTPND11_INTPND4 _intpnd11.bit._INTPND4 +#define INTPND11_INTPND5 _intpnd11.bit._INTPND5 +#define INTPND11_INTPND6 _intpnd11.bit._INTPND6 +#define INTPND11_INTPND7 _intpnd11.bit._INTPND7 +#define INTPND11_INTPND8 _intpnd11.bit._INTPND8 +#define INTPND11_INTPND9 _intpnd11.bit._INTPND9 +#define INTPND11_INTPND10 _intpnd11.bit._INTPND10 +#define INTPND11_INTPND11 _intpnd11.bit._INTPND11 +#define INTPND11_INTPND12 _intpnd11.bit._INTPND12 +#define INTPND11_INTPND13 _intpnd11.bit._INTPND13 +#define INTPND11_INTPND14 _intpnd11.bit._INTPND14 +#define INTPND11_INTPND15 _intpnd11.bit._INTPND15 +#define INTPND11_INTPND16 _intpnd11.bit._INTPND16 +__IO_EXTENDED INTPND1L1STR _intpnd1l1; +#define INTPND1L1 _intpnd1l1.byte +#define INTPND1L1_INTPND1 _intpnd1l1.bit._INTPND1 +#define INTPND1L1_INTPND2 _intpnd1l1.bit._INTPND2 +#define INTPND1L1_INTPND3 _intpnd1l1.bit._INTPND3 +#define INTPND1L1_INTPND4 _intpnd1l1.bit._INTPND4 +#define INTPND1L1_INTPND5 _intpnd1l1.bit._INTPND5 +#define INTPND1L1_INTPND6 _intpnd1l1.bit._INTPND6 +#define INTPND1L1_INTPND7 _intpnd1l1.bit._INTPND7 +#define INTPND1L1_INTPND8 _intpnd1l1.bit._INTPND8 +__IO_EXTENDED INTPND1H1STR _intpnd1h1; +#define INTPND1H1 _intpnd1h1.byte +#define INTPND1H1_INTPND9 _intpnd1h1.bit._INTPND9 +#define INTPND1H1_INTPND10 _intpnd1h1.bit._INTPND10 +#define INTPND1H1_INTPND11 _intpnd1h1.bit._INTPND11 +#define INTPND1H1_INTPND12 _intpnd1h1.bit._INTPND12 +#define INTPND1H1_INTPND13 _intpnd1h1.bit._INTPND13 +#define INTPND1H1_INTPND14 _intpnd1h1.bit._INTPND14 +#define INTPND1H1_INTPND15 _intpnd1h1.bit._INTPND15 +#define INTPND1H1_INTPND16 _intpnd1h1.bit._INTPND16 +__IO_EXTENDED INTPND21STR _intpnd21; +#define INTPND21 _intpnd21.word +#define INTPND21_INTPND17 _intpnd21.bit._INTPND17 +#define INTPND21_INTPND18 _intpnd21.bit._INTPND18 +#define INTPND21_INTPND19 _intpnd21.bit._INTPND19 +#define INTPND21_INTPND20 _intpnd21.bit._INTPND20 +#define INTPND21_INTPND21 _intpnd21.bit._INTPND21 +#define INTPND21_INTPND22 _intpnd21.bit._INTPND22 +#define INTPND21_INTPND23 _intpnd21.bit._INTPND23 +#define INTPND21_INTPND24 _intpnd21.bit._INTPND24 +#define INTPND21_INTPND25 _intpnd21.bit._INTPND25 +#define INTPND21_INTPND26 _intpnd21.bit._INTPND26 +#define INTPND21_INTPND27 _intpnd21.bit._INTPND27 +#define INTPND21_INTPND28 _intpnd21.bit._INTPND28 +#define INTPND21_INTPND29 _intpnd21.bit._INTPND29 +#define INTPND21_INTPND30 _intpnd21.bit._INTPND30 +#define INTPND21_INTPND31 _intpnd21.bit._INTPND31 +#define INTPND21_INTPND32 _intpnd21.bit._INTPND32 +__IO_EXTENDED INTPND2L1STR _intpnd2l1; +#define INTPND2L1 _intpnd2l1.byte +#define INTPND2L1_INTPND17 _intpnd2l1.bit._INTPND17 +#define INTPND2L1_INTPND18 _intpnd2l1.bit._INTPND18 +#define INTPND2L1_INTPND19 _intpnd2l1.bit._INTPND19 +#define INTPND2L1_INTPND20 _intpnd2l1.bit._INTPND20 +#define INTPND2L1_INTPND21 _intpnd2l1.bit._INTPND21 +#define INTPND2L1_INTPND22 _intpnd2l1.bit._INTPND22 +#define INTPND2L1_INTPND23 _intpnd2l1.bit._INTPND23 +#define INTPND2L1_INTPND24 _intpnd2l1.bit._INTPND24 +__IO_EXTENDED INTPND2H1STR _intpnd2h1; +#define INTPND2H1 _intpnd2h1.byte +#define INTPND2H1_INTPND25 _intpnd2h1.bit._INTPND25 +#define INTPND2H1_INTPND26 _intpnd2h1.bit._INTPND26 +#define INTPND2H1_INTPND27 _intpnd2h1.bit._INTPND27 +#define INTPND2H1_INTPND28 _intpnd2h1.bit._INTPND28 +#define INTPND2H1_INTPND29 _intpnd2h1.bit._INTPND29 +#define INTPND2H1_INTPND30 _intpnd2h1.bit._INTPND30 +#define INTPND2H1_INTPND31 _intpnd2h1.bit._INTPND31 +#define INTPND2H1_INTPND32 _intpnd2h1.bit._INTPND32 +__IO_EXTENDED MSGVAL1STR _msgval1; +#define MSGVAL1 _msgval1.lword +#define MSGVAL1_MSGVAL1 _msgval1.bit._MSGVAL1 +#define MSGVAL1_MSGVAL2 _msgval1.bit._MSGVAL2 +#define MSGVAL1_MSGVAL3 _msgval1.bit._MSGVAL3 +#define MSGVAL1_MSGVAL4 _msgval1.bit._MSGVAL4 +#define MSGVAL1_MSGVAL5 _msgval1.bit._MSGVAL5 +#define MSGVAL1_MSGVAL6 _msgval1.bit._MSGVAL6 +#define MSGVAL1_MSGVAL7 _msgval1.bit._MSGVAL7 +#define MSGVAL1_MSGVAL8 _msgval1.bit._MSGVAL8 +#define MSGVAL1_MSGVAL9 _msgval1.bit._MSGVAL9 +#define MSGVAL1_MSGVAL10 _msgval1.bit._MSGVAL10 +#define MSGVAL1_MSGVAL11 _msgval1.bit._MSGVAL11 +#define MSGVAL1_MSGVAL12 _msgval1.bit._MSGVAL12 +#define MSGVAL1_MSGVAL13 _msgval1.bit._MSGVAL13 +#define MSGVAL1_MSGVAL14 _msgval1.bit._MSGVAL14 +#define MSGVAL1_MSGVAL15 _msgval1.bit._MSGVAL15 +#define MSGVAL1_MSGVAL16 _msgval1.bit._MSGVAL16 +#define MSGVAL1_MSGVAL17 _msgval1.bit._MSGVAL17 +#define MSGVAL1_MSGVAL18 _msgval1.bit._MSGVAL18 +#define MSGVAL1_MSGVAL19 _msgval1.bit._MSGVAL19 +#define MSGVAL1_MSGVAL20 _msgval1.bit._MSGVAL20 +#define MSGVAL1_MSGVAL21 _msgval1.bit._MSGVAL21 +#define MSGVAL1_MSGVAL22 _msgval1.bit._MSGVAL22 +#define MSGVAL1_MSGVAL23 _msgval1.bit._MSGVAL23 +#define MSGVAL1_MSGVAL24 _msgval1.bit._MSGVAL24 +#define MSGVAL1_MSGVAL25 _msgval1.bit._MSGVAL25 +#define MSGVAL1_MSGVAL26 _msgval1.bit._MSGVAL26 +#define MSGVAL1_MSGVAL27 _msgval1.bit._MSGVAL27 +#define MSGVAL1_MSGVAL28 _msgval1.bit._MSGVAL28 +#define MSGVAL1_MSGVAL29 _msgval1.bit._MSGVAL29 +#define MSGVAL1_MSGVAL30 _msgval1.bit._MSGVAL30 +#define MSGVAL1_MSGVAL31 _msgval1.bit._MSGVAL31 +#define MSGVAL1_MSGVAL32 _msgval1.bit._MSGVAL32 +#define MSGVAL1_MSGVAL _msgval1.bitc._MSGVAL +__IO_EXTENDED MSGVAL11STR _msgval11; +#define MSGVAL11 _msgval11.word +#define MSGVAL11_MSGVAL1 _msgval11.bit._MSGVAL1 +#define MSGVAL11_MSGVAL2 _msgval11.bit._MSGVAL2 +#define MSGVAL11_MSGVAL3 _msgval11.bit._MSGVAL3 +#define MSGVAL11_MSGVAL4 _msgval11.bit._MSGVAL4 +#define MSGVAL11_MSGVAL5 _msgval11.bit._MSGVAL5 +#define MSGVAL11_MSGVAL6 _msgval11.bit._MSGVAL6 +#define MSGVAL11_MSGVAL7 _msgval11.bit._MSGVAL7 +#define MSGVAL11_MSGVAL8 _msgval11.bit._MSGVAL8 +#define MSGVAL11_MSGVAL9 _msgval11.bit._MSGVAL9 +#define MSGVAL11_MSGVAL10 _msgval11.bit._MSGVAL10 +#define MSGVAL11_MSGVAL11 _msgval11.bit._MSGVAL11 +#define MSGVAL11_MSGVAL12 _msgval11.bit._MSGVAL12 +#define MSGVAL11_MSGVAL13 _msgval11.bit._MSGVAL13 +#define MSGVAL11_MSGVAL14 _msgval11.bit._MSGVAL14 +#define MSGVAL11_MSGVAL15 _msgval11.bit._MSGVAL15 +#define MSGVAL11_MSGVAL16 _msgval11.bit._MSGVAL16 +__IO_EXTENDED MSGVAL1L1STR _msgval1l1; +#define MSGVAL1L1 _msgval1l1.byte +#define MSGVAL1L1_MSGVAL1 _msgval1l1.bit._MSGVAL1 +#define MSGVAL1L1_MSGVAL2 _msgval1l1.bit._MSGVAL2 +#define MSGVAL1L1_MSGVAL3 _msgval1l1.bit._MSGVAL3 +#define MSGVAL1L1_MSGVAL4 _msgval1l1.bit._MSGVAL4 +#define MSGVAL1L1_MSGVAL5 _msgval1l1.bit._MSGVAL5 +#define MSGVAL1L1_MSGVAL6 _msgval1l1.bit._MSGVAL6 +#define MSGVAL1L1_MSGVAL7 _msgval1l1.bit._MSGVAL7 +#define MSGVAL1L1_MSGVAL8 _msgval1l1.bit._MSGVAL8 +__IO_EXTENDED MSGVAL1H1STR _msgval1h1; +#define MSGVAL1H1 _msgval1h1.byte +#define MSGVAL1H1_MSGVAL9 _msgval1h1.bit._MSGVAL9 +#define MSGVAL1H1_MSGVAL10 _msgval1h1.bit._MSGVAL10 +#define MSGVAL1H1_MSGVAL11 _msgval1h1.bit._MSGVAL11 +#define MSGVAL1H1_MSGVAL12 _msgval1h1.bit._MSGVAL12 +#define MSGVAL1H1_MSGVAL13 _msgval1h1.bit._MSGVAL13 +#define MSGVAL1H1_MSGVAL14 _msgval1h1.bit._MSGVAL14 +#define MSGVAL1H1_MSGVAL15 _msgval1h1.bit._MSGVAL15 +#define MSGVAL1H1_MSGVAL16 _msgval1h1.bit._MSGVAL16 +__IO_EXTENDED MSGVAL21STR _msgval21; +#define MSGVAL21 _msgval21.word +#define MSGVAL21_MSGVAL17 _msgval21.bit._MSGVAL17 +#define MSGVAL21_MSGVAL18 _msgval21.bit._MSGVAL18 +#define MSGVAL21_MSGVAL19 _msgval21.bit._MSGVAL19 +#define MSGVAL21_MSGVAL20 _msgval21.bit._MSGVAL20 +#define MSGVAL21_MSGVAL21 _msgval21.bit._MSGVAL21 +#define MSGVAL21_MSGVAL22 _msgval21.bit._MSGVAL22 +#define MSGVAL21_MSGVAL23 _msgval21.bit._MSGVAL23 +#define MSGVAL21_MSGVAL24 _msgval21.bit._MSGVAL24 +#define MSGVAL21_MSGVAL25 _msgval21.bit._MSGVAL25 +#define MSGVAL21_MSGVAL26 _msgval21.bit._MSGVAL26 +#define MSGVAL21_MSGVAL27 _msgval21.bit._MSGVAL27 +#define MSGVAL21_MSGVAL28 _msgval21.bit._MSGVAL28 +#define MSGVAL21_MSGVAL29 _msgval21.bit._MSGVAL29 +#define MSGVAL21_MSGVAL30 _msgval21.bit._MSGVAL30 +#define MSGVAL21_MSGVAL31 _msgval21.bit._MSGVAL31 +#define MSGVAL21_MSGVAL32 _msgval21.bit._MSGVAL32 +__IO_EXTENDED MSGVAL2L1STR _msgval2l1; +#define MSGVAL2L1 _msgval2l1.byte +#define MSGVAL2L1_MSGVAL17 _msgval2l1.bit._MSGVAL17 +#define MSGVAL2L1_MSGVAL18 _msgval2l1.bit._MSGVAL18 +#define MSGVAL2L1_MSGVAL19 _msgval2l1.bit._MSGVAL19 +#define MSGVAL2L1_MSGVAL20 _msgval2l1.bit._MSGVAL20 +#define MSGVAL2L1_MSGVAL21 _msgval2l1.bit._MSGVAL21 +#define MSGVAL2L1_MSGVAL22 _msgval2l1.bit._MSGVAL22 +#define MSGVAL2L1_MSGVAL23 _msgval2l1.bit._MSGVAL23 +#define MSGVAL2L1_MSGVAL24 _msgval2l1.bit._MSGVAL24 +__IO_EXTENDED MSGVAL2H1STR _msgval2h1; +#define MSGVAL2H1 _msgval2h1.byte +#define MSGVAL2H1_MSGVAL25 _msgval2h1.bit._MSGVAL25 +#define MSGVAL2H1_MSGVAL26 _msgval2h1.bit._MSGVAL26 +#define MSGVAL2H1_MSGVAL27 _msgval2h1.bit._MSGVAL27 +#define MSGVAL2H1_MSGVAL28 _msgval2h1.bit._MSGVAL28 +#define MSGVAL2H1_MSGVAL29 _msgval2h1.bit._MSGVAL29 +#define MSGVAL2H1_MSGVAL30 _msgval2h1.bit._MSGVAL30 +#define MSGVAL2H1_MSGVAL31 _msgval2h1.bit._MSGVAL31 +#define MSGVAL2H1_MSGVAL32 _msgval2h1.bit._MSGVAL32 +__IO_EXTENDED COER1STR _coer1; +#define COER1 _coer1.byte +#define COER1_OE _coer1.bit._OE +# undef ___IOWIDTH +#endif /* __MB90XXX_H */ diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Src/serial/serial.c b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Src/serial/serial.c new file mode 100644 index 000000000..1d26f676e --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Src/serial/serial.c @@ -0,0 +1,218 @@ +/* + FreeRTOS.org V4.6.1 - Copyright (C) 2003-2007 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + + Also see http://www.SafeRTOS.com a version that has been certified for use + in safety critical systems, plus commercial licensing, development and + support options. + *************************************************************************** +*/ + + +/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER. + * + * This file only supports UART 1 + */ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "queue.h" +#include "task.h" + +/* Demo application includes. */ +#include "serial.h" + +/* The queue used to hold received characters. */ +static xQueueHandle xRxedChars; + +/* The queue used to hold characters waiting transmission. */ +static xQueueHandle xCharsForTx; + +static volatile portSHORT sTHREEmpty; + +static volatile portSHORT queueFail = pdFALSE; + +/*-----------------------------------------------------------*/ + +xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) +{ + + /* Initialise the hardware. */ + portENTER_CRITICAL(); + { + /* Create the queues used by the com test task. */ + xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + + if ( xRxedChars == 0) + { + queueFail = pdTRUE; + } + + if ( xCharsForTx == 0) + { + queueFail = pdTRUE; + } + + /* Initialize UART asynchronous mode */ + BGR0 = configCLKP1_CLOCK_HZ / ulWantedBaud; + + SCR0 = 0x17; /* 8N1 */ + SMR0 = 0x0d; /* enable SOT3, Reset, normal mode */ + SSR0 = 0x02; /* LSB first, enable receive interrupts */ + + PIER08_IE2 = 1; /* enable input */ + DDR08_D2 = 0; /* switch P08_2 to input */ + DDR08_D3 = 1; /* switch P08_3 to output */ + } + portEXIT_CRITICAL(); + + /* Unlike other ports, this serial code does not allow for more than one + com port. We therefore don't return a pointer to a port structure and can + instead just return NULL. */ + return NULL; +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) +{ + /* Get the next character from the buffer. Return false if no characters + are available, or arrive before xBlockTime expires. */ + if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) + { + return pdTRUE; + } + else + { + return pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) +{ +signed portBASE_TYPE xReturn; + + /* Transmit a character. */ + portENTER_CRITICAL(); + { + if( sTHREEmpty == pdTRUE ) + { + /* If sTHREEmpty is true then the UART Tx ISR has indicated that + there are no characters queued to be transmitted - so we can + write the character directly to the shift Tx register. */ + sTHREEmpty = pdFALSE; + TDR0 = cOutChar; + xReturn = pdPASS; + } + else + { + /* sTHREEmpty is false, so there are still characters waiting to be + transmitted. We have to queue this character so it gets + transmitted in turn. */ + + /* Return false if after the block time there is no room on the Tx + queue. It is ok to block inside a critical section as each task + maintains it's own critical section status. */ + if (xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) == pdTRUE) + { + xReturn = pdPASS; + } + else + { + xReturn = pdFAIL; + } + } + + if (pdPASS == xReturn) + { + /* Turn on the Tx interrupt so the ISR will remove the character from the + queue and send it. This does not need to be in a critical section as + if the interrupt has already removed the character the next interrupt + will simply turn off the Tx interrupt again. */ + SSR0_TIE = 1; + } + + } + portEXIT_CRITICAL(); + + return pdPASS; +} +/*-----------------------------------------------------------*/ + +/* + * UART RX interrupt service routine. + */ + __interrupt void UART0_RxISR (void) +{ + volatile signed portCHAR cChar; + + /* Get the character from the UART and post it on the queue of Rxed + characters. */ + cChar = RDR0; + + if( xQueueGenericSendFromISR( xRxedChars, (const void * const) &cChar, (signed portBASE_TYPE) pdFALSE, (portBASE_TYPE) 0 ) ) + { + /*If the post causes a task to wake force a context switch + as the woken task may have a higher priority than the task we have + interrupted. */ + portYIELDFromISR(); + } +} + +/*-----------------------------------------------------------*/ + +/* + * UART Tx interrupt service routine. + */ +__interrupt void UART0_TxISR (void) +{ + signed portCHAR cChar; + signed portBASE_TYPE xTaskWoken; + + /* The previous character has been transmitted. See if there are any + further characters waiting transmission. */ + if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWoken ) == pdTRUE ) + { + /* There was another character queued - transmit it now. */ + TDR0 = cChar; + } + else + { + /* There were no other characters to transmit. */ + sTHREEmpty = pdTRUE; + + /* Disable transmit interrupts */ + SSR0_TIE = 0; + } +} + diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Src/utility/taskutility.c b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Src/utility/taskutility.c new file mode 100644 index 000000000..85db50ecc --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Src/utility/taskutility.c @@ -0,0 +1,199 @@ +/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ +/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ +/* ELIGIBILITY FOR ANY PURPOSES. */ +/* (C) Fujitsu Microelectronics Europe GmbH */ +/*------------------------------------------------------------------------ + taskutility.C + - +-------------------------------------------------------------------------*/ + + +/*************************@INCLUDE_START************************/ +#include "mb96348hs.h" +#include "FreeRTOS.h" +#include "task.h" + + +static void vUART2Task( void *pvParameters ); + +/**************************@INCLUDE_END*************************/ +/*********************@GLOBAL_VARIABLES_START*******************/ +const char ASCII[] = "0123456789ABCDEF"; + +xTaskHandle UART_TaskHandle; + +void InitUart2(void) +{ + /* Initialize UART asynchronous mode */ + BGR2 = configCLKP1_CLOCK_HZ / 9600; /* 9600 Baud @ CLKP1 - 56 MHz */ + + SCR2 = 0x17; /* 8N1 */ + SMR2 = 0x0d; /* enable SOT3, Reset, normal mode */ + SSR2 = 0x02; /* LSB first, enable receive interrupts */ + + PIER05_IE0 = 1; /* enable input */ + DDR05_D0 = 0; /* switch P05_0 to input */ + DDR05_D1 = 1; /* switch P05_1 to output */ + +} + +void Putch2(char ch) /* sends a char */ +{ + while (SSR2_TDRE == 0); /* wait for transmit buffer empty */ + TDR2 = ch; /* put ch into buffer */ +} + +char Getch2(void) /* waits for and returns incomming char */ +{ + volatile unsigned ch; + + while(SSR2_RDRF == 0); /* wait for data received */ + if (SSR2_ORE) /* overrun error */ + { + ch = RDR2; /* reset error flags */ + return (char)(-1); + } + else + return (RDR2); /* return char */ +} + +void Puts2(const char *Name2) /* Puts a String to UART */ +{ + volatile portSHORT i,len; + len = strlen(Name2); + + for (i=0; i> div)&0xF); /* get hex-digit value */ + Putch2(digit + ((digit < 0xA) ? '0' : 'A' - 0xA)); + div-=4; /* next digit shift */ + } +} + +void Putdec2(unsigned long x, int digits) +{ + portSHORT i; + portCHAR buf[10],sign=1; + + if (digits < 0) { /* should be print of zero? */ + digits *= (-1); + sign =1; + } + buf[digits]='\0'; /* end sign of string */ + + for (i=digits; i>0; i--) { + buf[i-1] = ASCII[x % 10]; + x = x/10; + } + + if ( sign ) + { + for (i=0; buf[i]=='0'; i++) { /* no print of zero */ + if ( i= i ; j-- ) + { + Puthex2(trace_buff[j],2); + } + Puts2(" | "); + l++; + if ( l == 4) + { + Puts2("\n"); + l = 0; + } + } + Puts2("\r--------------------------------------------------------"); + break; + + default: + break; + } + Puts2("\n"); + } +} + +__interrupt void UART2_RxISR ( void ) +{ + SSR2_RIE=0; + vTaskResume( UART_TaskHandle ); +} diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Src/vectors.c b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Src/vectors.c new file mode 100644 index 000000000..5e605ac52 --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Src/vectors.c @@ -0,0 +1,179 @@ +/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ +/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ +/* ELIGIBILITY FOR ANY PURPOSES. */ +/* (C) Fujitsu Microelectronics Europe GmbH */ +/*--------------------------------------------------------------------------- + VECTORS.C + - Interrupt level (priority) setting + - Interrupt vector definition +-----------------------------------------------------------------------------*/ + +#include "mb96348hs.h" + +/*--------------------------------------------------------------------------- + InitIrqLevels() + This function pre-sets all interrupt control registers. It can be used + to set all interrupt priorities in static applications. If this file + contains assignments to dedicated resources, verify that the + appropriate controller is used. + NOTE: value 7 disables the interrupt and value 0 sets highest priority. +-----------------------------------------------------------------------------*/ + +#define MIN_ICR 12 +#define MAX_ICR 96 + +#define DEFAULT_ILM_MASK 7 + +void InitIrqLevels(void) +{ + volatile int irq; + + for (irq = MIN_ICR; irq <= MAX_ICR; irq++) + { + ICR = (irq << 8) | DEFAULT_ILM_MASK; + } + + ICR = ((51 & 0xFF) << 8) | 6; /* Reload Timer 0 of MB9634x Series */ + ICR = ((12 & 0xFF) << 8) | 6; /* Delayed interrupt of 16FX Family */ + ICR = (79 << 8) | 5; /* UART 0 Rx of MB9634x Series*/ + ICR = (80 << 8) | 5; /* UART 0 Tx of MB9634x Series*/ + ICR = (83 << 8) | 5; /* UART 2 Rx of MB9634x Series*/ +} + +/*--------------------------------------------------------------------------- + Prototypes + Add your own prototypes here. Each vector definition needs is proto- + type. Either do it here or include a header file containing them. +-----------------------------------------------------------------------------*/ + +__interrupt void DefaultIRQHandler (void); + +extern __interrupt void prvRLT0_TICKISR (void); +extern __interrupt void UART0_RxISR (void); +extern __interrupt void UART0_TxISR (void); +extern __interrupt void vPortYield (void); +extern __interrupt void vPortYieldDelayed (void); + +extern __interrupt void UART2_RxISR (void); + +/*--------------------------------------------------------------------------- + Vector definiton for MB9634x + Use following statements to define vectors. All resource related + vectors are predefined. Remaining software interrupts can be added here + as well. + NOTE: If software interrupts 0 to 7 are defined here, this might + conflict with the reset vector in the start-up file. +-----------------------------------------------------------------------------*/ + +#pragma intvect DefaultIRQHandler 11 /* Non-maskable Interrupt */ + +#pragma intvect vPortYieldDelayed 12 /* Delayed Interrupt */ + +#pragma intvect DefaultIRQHandler 13 /* RC Timer */ +#pragma intvect DefaultIRQHandler 14 /* Main Clock Timer */ +#pragma intvect DefaultIRQHandler 15 /* Sub Clock Timer */ +#pragma intvect DefaultIRQHandler 16 /* Reserved */ +#pragma intvect DefaultIRQHandler 17 /* EXT0 */ +#pragma intvect DefaultIRQHandler 18 /* EXT1 */ +#pragma intvect DefaultIRQHandler 19 /* EXT2 */ +#pragma intvect DefaultIRQHandler 20 /* EXT3 */ +#pragma intvect DefaultIRQHandler 21 /* EXT4 */ +#pragma intvect DefaultIRQHandler 22 /* EXT5 */ +#pragma intvect DefaultIRQHandler 23 /* EXT6 */ +#pragma intvect DefaultIRQHandler 24 /* EXT7 */ +#pragma intvect DefaultIRQHandler 25 /* EXT8 */ +#pragma intvect DefaultIRQHandler 26 /* EXT9 */ +#pragma intvect DefaultIRQHandler 27 /* EXT10 */ +#pragma intvect DefaultIRQHandler 28 /* EXT11 */ +#pragma intvect DefaultIRQHandler 29 /* EXT12 */ +#pragma intvect DefaultIRQHandler 30 /* EXT13 */ +#pragma intvect DefaultIRQHandler 31 /* EXT14 */ +#pragma intvect DefaultIRQHandler 32 /* EXT15 */ +#pragma intvect DefaultIRQHandler 33 /* CAN0 */ +#pragma intvect DefaultIRQHandler 34 /* CAN1 */ +#pragma intvect DefaultIRQHandler 35 /* PPG0 */ +#pragma intvect DefaultIRQHandler 36 /* PPG1 */ +#pragma intvect DefaultIRQHandler 37 /* PPG2 */ +#pragma intvect DefaultIRQHandler 38 /* PPG3 */ +#pragma intvect DefaultIRQHandler 39 /* PPG4 */ +#pragma intvect DefaultIRQHandler 40 /* PPG5 */ +#pragma intvect DefaultIRQHandler 41 /* PPG6 */ +#pragma intvect DefaultIRQHandler 42 /* PPG7 */ +#pragma intvect DefaultIRQHandler 43 /* PPG8 */ +#pragma intvect DefaultIRQHandler 44 /* PPG9 */ +#pragma intvect DefaultIRQHandler 45 /* PPG10 */ +#pragma intvect DefaultIRQHandler 46 /* PPG11 */ +#pragma intvect DefaultIRQHandler 47 /* PPG12 */ +#pragma intvect DefaultIRQHandler 48 /* PPG13 */ +#pragma intvect DefaultIRQHandler 49 /* PPG14 */ +#pragma intvect DefaultIRQHandler 50 /* PPG15 */ + +#pragma intvect prvRLT0_TICKISR 51 /* RLT0 */ + +#pragma intvect DefaultIRQHandler 52 /* RLT1 */ +#pragma intvect DefaultIRQHandler 53 /* RLT2 */ +#pragma intvect DefaultIRQHandler 54 /* RLT3 */ +#pragma intvect DefaultIRQHandler 55 /* PPGRLT - RLT6 */ +#pragma intvect DefaultIRQHandler 56 /* ICU0 */ +#pragma intvect DefaultIRQHandler 57 /* ICU1 */ +#pragma intvect DefaultIRQHandler 58 /* ICU2 */ +#pragma intvect DefaultIRQHandler 59 /* ICU3 */ +#pragma intvect DefaultIRQHandler 60 /* ICU4 */ +#pragma intvect DefaultIRQHandler 61 /* ICU5 */ +#pragma intvect DefaultIRQHandler 62 /* ICU6 */ +#pragma intvect DefaultIRQHandler 63 /* ICU7 */ +#pragma intvect DefaultIRQHandler 64 /* OCU0 */ +#pragma intvect DefaultIRQHandler 65 /* OCU1 */ +#pragma intvect DefaultIRQHandler 66 /* OCU2 */ +#pragma intvect DefaultIRQHandler 67 /* OCU3 */ +#pragma intvect DefaultIRQHandler 68 /* OCU4 */ +#pragma intvect DefaultIRQHandler 69 /* OCU5 */ +#pragma intvect DefaultIRQHandler 70 /* OCU6 */ +#pragma intvect DefaultIRQHandler 71 /* OCU7 */ +#pragma intvect DefaultIRQHandler 72 /* FRT0 */ +#pragma intvect DefaultIRQHandler 73 /* FRT1 */ +#pragma intvect DefaultIRQHandler 74 /* I2C0 */ +#pragma intvect DefaultIRQHandler 75 /* I2C1 */ +#pragma intvect DefaultIRQHandler 76 /* ADC */ +#pragma intvect DefaultIRQHandler 77 /* ALARM0 */ +#pragma intvect DefaultIRQHandler 78 /* ALARM1 */ + +#pragma intvect UART0_RxISR 79 /* LIN-UART 0 RX */ +#pragma intvect UART0_TxISR 80 /* LIN-UART 0 TX */ + +#pragma intvect DefaultIRQHandler 81 /* LIN-UART 1 RX */ +#pragma intvect DefaultIRQHandler 82 /* LIN-UART 1 TX */ + +#pragma intvect UART2_RxISR 83 /* LIN-UART 2 RX */ + +#pragma intvect DefaultIRQHandler 84 /* LIN-UART 2 TX */ +#pragma intvect DefaultIRQHandler 85 /* LIN-UART 3 RX */ +#pragma intvect DefaultIRQHandler 86 /* LIN-UART 3 TX */ +#pragma intvect DefaultIRQHandler 87 /* MAIN FLASH IRQ */ +#pragma intvect DefaultIRQHandler 88 /* SATELLITE FLASH IRQ (not on all devices) */ +#pragma intvect DefaultIRQHandler 89 /* LIN-UART 7 RX (not on all devices) */ +#pragma intvect DefaultIRQHandler 90 /* LIN-UART 7 TX (not on all devices) */ +#pragma intvect DefaultIRQHandler 91 /* LIN-UART 8 RX (not on all devices) */ +#pragma intvect DefaultIRQHandler 92 /* LIN-UART 8 TX (not on all devices) */ +#pragma intvect DefaultIRQHandler 93 /* LIN-UART 9 RX (not on all devices) */ +#pragma intvect DefaultIRQHandler 94 /* LIN-UART 9 TX (not on all devices) */ +#pragma intvect DefaultIRQHandler 95 /* RTC (not on all devices) */ +#pragma intvect DefaultIRQHandler 96 /* CAL (not on all devices) */ + +#pragma intvect vPortYield 122 /* INT #122 */ + +/*--------------------------------------------------------------------------- + DefaultIRQHandler() + This function is a placeholder for all vector definitions. Either use + your own placeholder or add necessary code here. +-----------------------------------------------------------------------------*/ + +__interrupt +void DefaultIRQHandler (void) +{ + __DI(); /* disable interrupts */ + while(1) + { + __wait_nop(); /* halt system */ + } +} \ No newline at end of file diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Src/watchdog/watchdog.c b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Src/watchdog/watchdog.c new file mode 100644 index 000000000..273414254 --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Src/watchdog/watchdog.c @@ -0,0 +1,62 @@ +/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ +/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ +/* ELIGIBILITY FOR ANY PURPOSES. */ +/* (C) Fujitsu Microelectronics Europe GmbH */ +/*------------------------------------------------------------------------ + watchdog.c + - This file contains the function deefinition for hardware watchdog. +-------------------------------------------------------------------------*/ + +#include "mb96348hs.h" +#include "FreeRTOS.h" +#include "task.h" +#include "watchdog.h" + +/*--------------------------------------------------------------------------- + * Setup Watchdog + *---------------------------------------------------------------------------*/ +#if WATCHDOG != WTC_NONE +void InitWatchdog(void) +{ + WDTC_WTI = WTC_PER_2_23; /* 2^23/CLKWT */ + WDTC_WTCS = WTC_CLKMC; /* CLKWT=CLKMC, Watchdog expiration delay = 2.097s @ 4MHZ CLKMC*/ + WDTCP = 0x00; /* Activate Watchdog, Clear Pattern 0x00 */ +} +#endif + +/*--------------------------------------------------------------------------- + * The below task clears the watchdog and blocks itself for WTC_CLR_PER ticks. + *---------------------------------------------------------------------------*/ +#if WATCHDOG == WTC_IN_TASK +static void prvWatchdogTask ( void *pvParameters ) +{ + const portTickType xFrequency = WTC_CLR_PER; + portTickType xLastWakeTime; + + ( void ) pvParameters; + + /* Get currrent tick count */ + xLastWakeTime = xTaskGetTickCount(); + + for( ; ; ) + { + /* Get currrent tick count */ + xLastWakeTime = xTaskGetTickCount(); + + Kick_Watchdog(); + + /* Block the task for WTC_CLR_PER ticks (1 s) at watchdog overflow period of WTC_PER_2_24 CLKMC cycles */ + vTaskDelayUntil( &xLastWakeTime, xFrequency ); + } +} +#endif + +/*--------------------------------------------------------------------------- + * The below function creates hardware watchdog task. + *---------------------------------------------------------------------------*/ +#if WATCHDOG == WTC_IN_TASK +void vStartWatchdogTask( unsigned portBASE_TYPE uxPriority ) +{ + xTaskCreate( prvWatchdogTask , ( signed portCHAR * ) "KickWTC", portMINIMAL_STACK_SIZE, ( void * ) NULL, uxPriority, ( xTaskHandle * ) NULL ); +} +#endif diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Src/watchdog/watchdog.h b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Src/watchdog/watchdog.h new file mode 100644 index 000000000..057c6af86 --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/Src/watchdog/watchdog.h @@ -0,0 +1,73 @@ +/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ +/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ +/* ELIGIBILITY FOR ANY PURPOSES. */ +/* (C) Fujitsu Microelectronics Europe GmbH */ +/*------------------------------------------------------------------------ + watchdog.h + - This file contains the defines and function declaration for hardware watchdog. +-------------------------------------------------------------------------*/ +/* + * Clear watchdog defines + */ +#define WTC_NONE 0 /* Don't initialize and clear watchdog */ +#define WTC_IN_TASK 1 /* Clear Watchdog in dedicated task */ +#define WTC_IN_TICK 2 /* Clear Watchdog in TICK Hook */ +#define WTC_IN_IDLE 3 /* Clear Watchdog in Idle Hook */ + +#define WATCHDOG WTC_IN_TASK /* Clear Watchdog in vWatchdogTask() */ +/*------------------------------------------------------------------------*/ +/* + * Watchdog period defines + */ +#define WTC_PER_2_9 0 /* The watchdog period is 2^9/CLKWT */ +#define WTC_PER_2_10 1 /* The watchdog period is 2^10/CLKWT */ +#define WTC_PER_2_11 2 /* The watchdog period is 2^11/CLKWT */ +#define WTC_PER_2_12 3 /* The watchdog period is 2^12/CLKWT */ +#define WTC_PER_2_13 4 /* The watchdog period is 2^13/CLKWT */ +#define WTC_PER_2_14 5 /* The watchdog period is 2^14/CLKWT */ +#define WTC_PER_2_15 6 /* The watchdog period is 2^15/CLKWT */ +#define WTC_PER_2_16 7 /* The watchdog period is 2^16/CLKWT */ +#define WTC_PER_2_17 8 /* The watchdog period is 2^17/CLKWT */ +#define WTC_PER_2_18 9 /* The watchdog period is 2^18/CLKWT */ +#define WTC_PER_2_19 10 /* The watchdog period is 2^19/CLKWT */ +#define WTC_PER_2_20 11 /* The watchdog period is 2^20/CLKWT */ +#define WTC_PER_2_21 12 /* The watchdog period is 2^21/CLKWT */ +#define WTC_PER_2_22 13 /* The watchdog period is 2^22/CLKWT */ +#define WTC_PER_2_23 14 /* The watchdog period is 2^23/CLKWT */ +#define WTC_PER_2_24 15 /* The watchdog period is 2^24/CLKWT */ +/*------------------------------------------------------------------------*/ +/* + * Watchdog Clock source defines + */ +#define WTC_CLKRC0 0 /* The watchdog clock is CLKRC */ +#define WTC_CLKRC1 1 /* The watchdog clock is CLKRC, + changing RC clock while watchdog opeation causes reset */ +#define WTC_CLKMC 2 /* The watchdog clock is CLKMC */ +#define WTC_CLKSC 3 /* The watchdog clock is CLKSC */ +/*------------------------------------------------------------------------*/ +/* + * Watchdog Reset at transition to Stop mode defines + */ +#define WTC_RSTP_0 0 /* No watchdog reset at transition to Stop mode */ +#define WTC_RSTP_1 1 /* watchdog reset at transition to Stop mode */ +/*------------------------------------------------------------------------*/ +/* + * After every WTC_CLR_PER ticks the watchdog would be cleared in the prvWatchdogTask(). + * This period needs to be chosed in accordance with the current CLKWT and the above + * setting WTC_PER_2_XX. + */ +#define WTC_CLR_PER 100 /* The watchdog clear period in RTOS ticks */ +/*------------------------------------------------------------------------*/ +/* + * Kick_watchdog Macro to clear watchdog + */ +#define Kick_Watchdog() \ + { WDTCP = 0x00; \ + } +/*------------------------------------------------------------------------*/ +/* + * Watchdog function declarations + */ +void InitWatchdog (void); +void vStartWatchdogTask(unsigned portBASE_TYPE uxPriority); + diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/options.dat b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/options.dat new file mode 100644 index 000000000..c9b577be9 --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/options.dat @@ -0,0 +1,386 @@ +$CPUSERIES-907 +$Prj-Config_1 +$0 +-g +-w 3 +-INF LIST +-D __CONFIG__=1 +-I ".\Src" +-I ".\Src\config" +-I ".\Src\watchdog" +-I "..\..\Common\include" +-I "..\..\..\Source\include" +-I "..\..\..\Source\portable\Softune\MB96340" +-O 4 +-K SPEED +-model MEDIUM +-B +-Xdof +-xauto 127 +-x vTaskSwitchContext,vTaskIncrementTick +-K EOPT +-K LIB +-K UNROLL +$other +-INF srcin +-D __96340 +$time +1202809404 +$end +$1 +-g +-w 2 +-D __CONFIG__=1 +-I "C:\Fujitsu\FreeRTOS\FreeRTOS Port 16FX\96340_FreeRTOS_96348hs-v17\96340_FreeRTOS_96348hs-v17\Src\os" +-I "C:\Fujitsu\FreeRTOS\FreeRTOS Port 16FX\96340_FreeRTOS_96348hs-v17\96340_FreeRTOS_96348hs-v17\Src\port" +-linf ON +-lsrc ON +-lsec ON +-lcros OFF +-linc ON +-lexp OBJ +-pl 60 +-pw 100 +-tab 8 +-lf +-Xdof +$other +$time +1200396895 +$end +$2 +-g +-AL 2 +-ra _INRAM01=0x000180/0x00037F +-ra _INRAM02=0x002240/0x007FFF +-ro _INROM03=0xF80000/0xFFFFFF +-ro _INROM01=0xDE0000/0xDE7FFF +-ro _INROM02=0xDF0000/0xDF7FFF +-sc CONST/Data/BYTE=0xFF8000 +-check_rora +-check_locate +-rg 0 +-m +-pl 60 +-pw 132 +-Xals +-Xalr +-na +-w 2 +-Xdof +$other +-Xset_rora +$time +1201865507 +$end +$3 +-dt s,d,r,a +-pl 60 +-pw 132 +-g +-Xdof +$other +$time +1201865507 +$end +$4 +-Xdof +$other +$time +1200395885 +$end +$5 +$other +$time +1200395885 +$end +$Prjend +$Prj-Config_2 +$0 +-g +-w 3 +-INF LIST +-D __CONFIG__=2 +-I ".\Src" +-I ".\Src\config" +-I ".\Src\watchdog" +-I "..\..\Common\include" +-I "..\..\..\Source\include" +-I "..\..\..\Source\portable\Softune\MB96340" +-O 4 +-K SPEED +-model MEDIUM +-B +-Xdof +-xauto 127 +-x vTaskSwitchContext,vTaskIncrementTick +-K EOPT +-K LIB +-K UNROLL +$other +-INF srcin +-D __96340 +$time +1202809404 +$end +$1 +-g +-w 2 +-D __CONFIG__=2 +-I "C:\Fujitsu\FreeRTOS\FreeRTOS Port 16FX\96340_FreeRTOS_96348hs-v17\96340_FreeRTOS_96348hs-v17\Src\os" +-I "C:\Fujitsu\FreeRTOS\FreeRTOS Port 16FX\96340_FreeRTOS_96348hs-v17\96340_FreeRTOS_96348hs-v17\Src\port" +-linf ON +-lsrc ON +-lsec ON +-lcros OFF +-linc ON +-lexp OBJ +-pl 60 +-pw 100 +-tab 8 +-lf +-Xdof +$other +$time +1200396910 +$end +$2 +-g +-AL 2 +-ra _INRAM01=0x000180/0x00037F +-ra _INRAM02=0x002240/0x007FFF +-ro _INROM03=0xF80000/0xFFFFFF +-ro _INROM01=0xDE0000/0xDE7FFF +-ro _INROM02=0xDF0000/0xDF7FFF +-sc CONST/Data/BYTE=0xFF8000 +-check_rora +-check_locate +-rg 0 +-m +-pl 60 +-pw 132 +-Xals +-Xalr +-na +-w 2 +-Xdof +$other +-Xset_rora +$time +1201865507 +$end +$3 +-dt s,d,r,a +-pl 60 +-pw 132 +-g +-Xdof +$other +$time +1201865507 +$end +$4 +-Xdof +$other +$time +1200396397 +$end +$5 +$other +$time +1200396397 +$end +$Prjend +$Prj-Config_3 +$0 +-g +-w 3 +-INF LIST +-D __CONFIG__=3 +-I ".\Src" +-I ".\Src\config" +-I ".\Src\watchdog" +-I "..\..\Common\include" +-I "..\..\..\Source\include" +-I "..\..\..\Source\portable\Softune\MB96340" +-O 4 +-K SPEED +-model MEDIUM +-B +-Xdof +-xauto 127 +-x vTaskSwitchContext,vTaskIncrementTick +-K EOPT +-K LIB +-K UNROLL +$other +-INF srcin +-D __96340 +$time +1202809404 +$end +$1 +-g +-w 2 +-D __CONFIG__=3 +-I "C:\Fujitsu\FreeRTOS\FreeRTOS Port 16FX\96340_FreeRTOS_96348hs-v17\96340_FreeRTOS_96348hs-v17\Src\os" +-I "C:\Fujitsu\FreeRTOS\FreeRTOS Port 16FX\96340_FreeRTOS_96348hs-v17\96340_FreeRTOS_96348hs-v17\Src\port" +-linf ON +-lsrc ON +-lsec ON +-lcros OFF +-linc ON +-lexp OBJ +-pl 60 +-pw 100 +-tab 8 +-lf +-Xdof +$other +$time +1200396949 +$end +$2 +-g +-AL 2 +-ra _INRAM01=0x000180/0x00037F +-ra _INRAM02=0x002240/0x007FFF +-ro _INROM03=0xF80000/0xFFFFFF +-ro _INROM01=0xDE0000/0xDE7FFF +-ro _INROM02=0xDF0000/0xDF7FFF +-sc CONST/Data/BYTE=0xFF8000 +-check_rora +-check_locate +-rg 0 +-m +-pl 60 +-pw 132 +-Xals +-Xalr +-na +-w 2 +-Xdof +$other +-Xset_rora +$time +1201865507 +$end +$3 +-dt s,d,r,a +-pl 60 +-pw 132 +-g +-Xdof +$other +$time +1201865507 +$end +$4 +-Xdof +$other +$time +1200396397 +$end +$5 +$other +$time +1200396397 +$end +$Prjend +$Prj-Config_4 +$0 +-g +-w 3 +-INF LIST +-D __CONFIG__=4 +-I ".\Src" +-I ".\Src\config" +-I ".\Src\watchdog" +-I "..\..\Common\include" +-I "..\..\..\Source\include" +-I "..\..\..\Source\portable\Softune\MB96340" +-O 4 +-K SPEED +-model MEDIUM +-B +-Xdof +-xauto 127 +-x vTaskSwitchContext,vTaskIncrementTick +-K EOPT +-K LIB +-K UNROLL +$other +-INF srcin +-D __96340 +$time +1202809404 +$end +$1 +-g +-w 2 +-D __CONFIG__=4 +-I "C:\Fujitsu\FreeRTOS\FreeRTOS Port 16FX\96340_FreeRTOS_96348hs-v17\96340_FreeRTOS_96348hs-v17\Src\os" +-I "C:\Fujitsu\FreeRTOS\FreeRTOS Port 16FX\96340_FreeRTOS_96348hs-v17\96340_FreeRTOS_96348hs-v17\Src\port" +-linf ON +-lsrc ON +-lsec ON +-lcros OFF +-linc ON +-lexp OBJ +-pl 60 +-pw 100 +-tab 8 +-lf +-Xdof +$other +$time +1200396961 +$end +$2 +-g +-AL 2 +-ra _INRAM01=0x000180/0x00037F +-ra _INRAM02=0x002240/0x007FFF +-ro _INROM03=0xF80000/0xFFFFFF +-ro _INROM01=0xDE0000/0xDE7FFF +-ro _INROM02=0xDF0000/0xDF7FFF +-sc CONST/Data/BYTE=0xFF8000 +-check_rora +-check_locate +-rg 0 +-m +-pl 60 +-pw 132 +-Xals +-Xalr +-na +-w 2 +-Xdof +$other +-Xset_rora +$time +1201865507 +$end +$3 +-dt s,d,r,a +-pl 60 +-pw 132 +-g +-Xdof +$other +$time +1201865507 +$end +$4 +-Xdof +$other +$time +1200396397 +$end +$5 +$other +$time +1200396397 +$end +$Prjend +$CPUSERIESEND diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/readme.txt b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/readme.txt new file mode 100644 index 000000000..742c57257 --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_FLASHCAN100P340/readme.txt @@ -0,0 +1,133 @@ +========================================================================== + Template Project for MB96348HS Series +========================================================================== + Fujitsu Microelectronics Europe GmbH + + The following software is for demonstration purposes only. It is not + fully tested, nor validated in order to fullfill its task under all + circumstances. Therefore, this software or any part of it must only be + used in an evaluation laboratory environment. + This software is subject to the rules of our standard DISCLAIMER, that is + delivered with our SW-tools on the Fujitsu Microcontrollers DVD + (V5.0 or higher "\START.HTM"). +========================================================================== + +History +Date Ver Author Softune Description +2007-10-29 1.0 MPi V30L33R11 original version +2007-11-02 1.1 MPi V30L33R11 Added the watchdog functionality + Used vTaskStartScheduler() instead + of xPortStartScheduler() +2007-11-12 1.2 MPi V30L33R11 Updated FreeRTOS 4.6.1 and tested +2007-11-23 1.3 MPi V30L33R11 Seperated watchdog functionality in watchdog.c + and watchdog.h +2008-01-03 1.4 MPi V30L33R11 Added portYIELDFromISR() and now all the + demo application functions are working. +2008-01-04 1.5 MPi V30L33R11 Updated FreeRTOS 4.7.0 and tested +2008-01-10 1.6 MPi V30L33R11 Replaced INT9 with INT #122 in macro portYIELD() +2008-01-15 1.7 MPi V30L33R11 Integrated SVN releases 1.5 and 1.6. +========================================================================== +1.0. +This is a project is to test the FreeRTOS port for 16FX and the demo application +which runs on FLASH-CAN-100P-240. + +This FreeRTOS port uses the Task Stack pointed by User Stack pointer (USB:USP) for +tasks and the system stack pointed by System Stack pointer (SSB:SSP) for everything +else. + +This port is tested with MEDIUM and LARGE memory model and seems to be working fine. +The define MEMMODEL has to be configured in order to use the corresponding memory +model. + +This port doesnt use any register banking and always uses bank 0. It also consider that +the parameters to the tasks is passed via stack and not via registers. + +In this port the implemetation of portENTER_CRITICAL() and portEXIT_CRITICAL() macros +is changed in order to make them more efficient. Now usCriticalNesting variable is not +used to keep track of global interrupt enable. Rather the current PS is stored on to +the stack and interrupts are disabled for portENTER_CRITICAL(). And for portEXIT_CRITICAL() +simply the PS is restored from stack. + +1.1. +In this port, the functionality is added to initialize and clear the watchdog in the +dedicated task, Tick Hook or the Idle Hook. The place exactly where the wtachdog can be +cleared can be configured. Though Idle Hook is not an approproiate place to clear the +watchdog, its done here for demonstration purpose only. + +Also from Main function vTaskStartScheduler() function is called instead of xPortStartScheduler(). +After doing this change now no more IDLE task is required to be added seperately as +vTaskStartScheduler() adds prvIdleTask() on its own. + +1.2. +Updated the FreeRTOS version to 4.6.1 and tested with the same. + +1.3. +Moved the watchdog functionality to watchdog.c and watchdog.h. + +1.4. +Added portYIELDFromISR() which uses delayed interrupt. This macro needs to be used from the +application ISRs in order to force a context switch from them if required. It should be noted +that the interrupt priority of such application ISRs MUST be always higher than the dealyed +interrupt (currently 23) in order to perform the context switch correctly. + +It should be also noted that the RLT0 and Delayed Interrupt priority MUST be always same in order +to assure correct working of this port. + +Now portYIELD() used software interrupt INT9 instead of delayed interrupt. + +Now all the queue functions works ok. + +Tested with the heap_1.c, heap_2.c and heap_3.c. + +At one time, either of heap_1.c or heap_2.c or heap_3.c needs to be used. Hence the files those are not +required to be used should be removed from the target of the build. + +Added the __STD_LIB_sbrk.c file in order to define the *sbrk() function. This is required while using +heap_3.c file which uses the dynamic memory allocation. + +Made changes to the demo application files crhook.c. Please refer the file and grep for "Added by MPi" +to find the changes. It should be noted that if INCLUDE_StartHookCoRoutines is defined as 0 (i.e. if +vStartHookCoRoutines() functionality is NOT required) then crhook.c file should be removed from target +build and uncomment the vApplicationTickHook() function from main.c should be uncommnented. + +Added taskutility.c file. This file contains vUART2Task() which calls vTaskList() and vTaskStartTrace() +functions. + +If vCreateBlockTimeTasks() is not called then the LED at PDR00_P7 blinks at normal rate (3s). + +This port is tested with MEDIUM and LARGE memory model and working fine. + +configMINIMAL_STACK_SIZE value changed to 172 from 70 in order to make the port work. + +1.5. +Updated the FreeRTOS version to 4.7.0 and tested with the same. Tested for pre-emptive as well as +co-operative approach. + +1.6. +portYIELD() macro now uses INT #122 instead of INT9. + +Optimized functions vParTestToggleLED() and vParTestSetLED() in main.c. + +Now watchdog uses 2^23 as clock prescaler instead of 2^24. Also updated the WTC_CLR_PER in watchdog.h. + +1.7. +It should be noted that the readme, appnote and SVN tag version numbers may be different for the same release. + +This readme is specific to project FreeRTOS_96348hs_FLASHCAN100P340. And this project specifically works +on board FLASH-CAN-100P-240 V1.0 along with MB2198-01 emulator+Softune Workbench. + +Created 4 different configuration Config_1 to Config_4. Each config includes certain demo application function. +More details specific to each configuration can be found in the appnote. + +Used relative path to include files instead of absolute. + +Created config, MemMang, serial and utility subdirectories and moved corresponding functionlaity there. + +Updated config.h, main.c and start.asm in order to have configuration specific build. + +Clock settings: +--------------- +Crystal: 4 MHz +CLKB: 56 MHz +CLKP1: 56 MHz +CLKP2: 56 MHz diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Config_1/MB2198-01_COM1.sup b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Config_1/MB2198-01_COM1.sup new file mode 100644 index 000000000..1355cbb2d --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Config_1/MB2198-01_COM1.sup @@ -0,0 +1,45 @@ +[Information] +DebChangeFlag=1 +MCUChangeFlag=1 +[Version] +Version=1 +Level=1 +Revision=0 +[Debug Type] +Type=0 +Virtual CPU File=wv907e4.dll +Core ID=0 +Monitor Load=1 +Monitor Load Condition=Enable +[Device] +Communication=RS COM1 115200 +ProductID=0 +Protocol=3 +[Target] +AutoLoad=Disable +Before Batch File= +After Batch File= +[Start] +Batch File= +[Window] +Flag=Enable +[Path Environment] +Flag=Enable +[Map] +Flag=Enable +[Radix Environment] +Flag=Enable +[Watch Environment] +Flag=Enable +[Exec Environment] +Flag=Enable +[Break Environment] +Flag=Enable +[Emulation Environment] +Flag=Enable +[Monitor Environment] +Flag=Enable +[Error] +Flag=Enable +[Color] +Flag=Enable diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Config_1/MB2198-01_COM2.sup b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Config_1/MB2198-01_COM2.sup new file mode 100644 index 000000000..c0373eb00 --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Config_1/MB2198-01_COM2.sup @@ -0,0 +1,46 @@ +[Information] +DebChangeFlag=1 +MCUChangeFlag=1 +[Version] +Version=1 +Level=1 +Revision=0 +[Debug Type] +Type=0 +Virtual CPU File=wv907e4.dll +Core ID=0 +Monitor Load=1 +Monitor Load Condition=Enable +ChangeFlag=Disable +[Device] +Communication=RS COM2 115200 +ProductID=0 +Protocol=3 +[Target] +AutoLoad=Disable +Before Batch File= +After Batch File= +[Start] +Batch File= +[Window] +Flag=Enable +[Path Environment] +Flag=Enable +[Map] +Flag=Enable +[Radix Environment] +Flag=Enable +[Watch Environment] +Flag=Enable +[Exec Environment] +Flag=Enable +[Break Environment] +Flag=Enable +[Emulation Environment] +Flag=Enable +[Monitor Environment] +Flag=Enable +[Error] +Flag=Enable +[Color] +Flag=Enable diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Config_1/MB2198-01_LAN.sup b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Config_1/MB2198-01_LAN.sup new file mode 100644 index 000000000..2d593b5a1 --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Config_1/MB2198-01_LAN.sup @@ -0,0 +1,46 @@ +[Information] +DebChangeFlag=1 +MCUChangeFlag=1 +[Version] +Version=1 +Level=1 +Revision=0 +[Debug Type] +Type=0 +Virtual CPU File=wv907e4.dll +Core ID=0 +Monitor Load=1 +Monitor Load Condition=Enable +ChangeFlag=Disable +[Device] +Communication=LAN 127.0.0.1 +ProductID=0 +Protocol=3 +[Target] +AutoLoad=Enable +Before Batch File= +After Batch File= +[Start] +Batch File= +[Window] +Flag=Enable +[Path Environment] +Flag=Enable +[Map] +Flag=Enable +[Radix Environment] +Flag=Enable +[Watch Environment] +Flag=Enable +[Exec Environment] +Flag=Enable +[Break Environment] +Flag=Enable +[Emulation Environment] +Flag=Enable +[Monitor Environment] +Flag=Enable +[Error] +Flag=Enable +[Color] +Flag=Enable diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Config_1/MB2198-01_USB.sup b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Config_1/MB2198-01_USB.sup new file mode 100644 index 000000000..7f30ac5ac --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Config_1/MB2198-01_USB.sup @@ -0,0 +1,45 @@ +[Information] +DebChangeFlag=1 +MCUChangeFlag=1 +[Version] +Version=1 +Level=1 +Revision=0 +[Debug Type] +Type=0 +Virtual CPU File=wv907e4.dll +Core ID=0 +Monitor Load=1 +Monitor Load Condition=Enable +[Device] +Communication=USB +ProductID=0 +Protocol=3 +[Target] +AutoLoad=Enable +Before Batch File= +After Batch File= +[Start] +Batch File= +[Window] +Flag=Enable +[Path Environment] +Flag=Enable +[Map] +Flag=Enable +[Radix Environment] +Flag=Enable +[Watch Environment] +Flag=Enable +[Exec Environment] +Flag=Enable +[Break Environment] +Flag=Enable +[Emulation Environment] +Flag=Enable +[Monitor Environment] +Flag=Enable +[Error] +Flag=Enable +[Color] +Flag=Enable diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Config_1/Simulator.sup b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Config_1/Simulator.sup new file mode 100644 index 000000000..cc6ec9e23 --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Config_1/Simulator.sup @@ -0,0 +1,46 @@ +[Information] +DebChangeFlag=1 +MCUChangeFlag=1 +[Version] +Version=1 +Level=1 +Revision=0 +[Debug Type] +Type=1 +Virtual CPU File=wv907f1.dll +Core ID=0 +Monitor Load=1 +Monitor Load Condition=Disable +ChangeFlag=Disable +[Device] +Communication=USB +ProductID=0 +Protocol=3 +[Target] +AutoLoad=Enable +Before Batch File= +After Batch File= +[Start] +Batch File= +[Window] +Flag=Enable +[Path Environment] +Flag=Enable +[Map] +Flag=Enable +[Radix Environment] +Flag=Enable +[Watch Environment] +Flag=Enable +[Exec Environment] +Flag=Enable +[Break Environment] +Flag=Enable +[Emulation Environment] +Flag=Enable +[Monitor Environment] +Flag=Enable +[Error] +Flag=Enable +[Color] +Flag=Enable diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Config_2/MB2198-01_COM1.sup b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Config_2/MB2198-01_COM1.sup new file mode 100644 index 000000000..ca33b5b5c --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Config_2/MB2198-01_COM1.sup @@ -0,0 +1,46 @@ +[Information] +DebChangeFlag=1 +MCUChangeFlag=1 +[Version] +Version=1 +Level=1 +Revision=0 +[Debug Type] +Type=0 +Virtual CPU File=wv907e4.dll +Core ID=0 +Monitor Load=1 +Monitor Load Condition=Enable +ChangeFlag=Disable +[Device] +Communication=RS COM1 115200 +ProductID=0 +Protocol=3 +[Target] +AutoLoad=Disable +Before Batch File= +After Batch File= +[Start] +Batch File= +[Window] +Flag=Enable +[Path Environment] +Flag=Enable +[Map] +Flag=Enable +[Radix Environment] +Flag=Enable +[Watch Environment] +Flag=Enable +[Exec Environment] +Flag=Enable +[Break Environment] +Flag=Enable +[Emulation Environment] +Flag=Enable +[Monitor Environment] +Flag=Enable +[Error] +Flag=Enable +[Color] +Flag=Enable diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Config_2/MB2198-01_COM2.sup b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Config_2/MB2198-01_COM2.sup new file mode 100644 index 000000000..c0373eb00 --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Config_2/MB2198-01_COM2.sup @@ -0,0 +1,46 @@ +[Information] +DebChangeFlag=1 +MCUChangeFlag=1 +[Version] +Version=1 +Level=1 +Revision=0 +[Debug Type] +Type=0 +Virtual CPU File=wv907e4.dll +Core ID=0 +Monitor Load=1 +Monitor Load Condition=Enable +ChangeFlag=Disable +[Device] +Communication=RS COM2 115200 +ProductID=0 +Protocol=3 +[Target] +AutoLoad=Disable +Before Batch File= +After Batch File= +[Start] +Batch File= +[Window] +Flag=Enable +[Path Environment] +Flag=Enable +[Map] +Flag=Enable +[Radix Environment] +Flag=Enable +[Watch Environment] +Flag=Enable +[Exec Environment] +Flag=Enable +[Break Environment] +Flag=Enable +[Emulation Environment] +Flag=Enable +[Monitor Environment] +Flag=Enable +[Error] +Flag=Enable +[Color] +Flag=Enable diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Config_2/MB2198-01_LAN.sup b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Config_2/MB2198-01_LAN.sup new file mode 100644 index 000000000..2d593b5a1 --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Config_2/MB2198-01_LAN.sup @@ -0,0 +1,46 @@ +[Information] +DebChangeFlag=1 +MCUChangeFlag=1 +[Version] +Version=1 +Level=1 +Revision=0 +[Debug Type] +Type=0 +Virtual CPU File=wv907e4.dll +Core ID=0 +Monitor Load=1 +Monitor Load Condition=Enable +ChangeFlag=Disable +[Device] +Communication=LAN 127.0.0.1 +ProductID=0 +Protocol=3 +[Target] +AutoLoad=Enable +Before Batch File= +After Batch File= +[Start] +Batch File= +[Window] +Flag=Enable +[Path Environment] +Flag=Enable +[Map] +Flag=Enable +[Radix Environment] +Flag=Enable +[Watch Environment] +Flag=Enable +[Exec Environment] +Flag=Enable +[Break Environment] +Flag=Enable +[Emulation Environment] +Flag=Enable +[Monitor Environment] +Flag=Enable +[Error] +Flag=Enable +[Color] +Flag=Enable diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Config_2/MB2198-01_USB.sup b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Config_2/MB2198-01_USB.sup new file mode 100644 index 000000000..64314f965 --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Config_2/MB2198-01_USB.sup @@ -0,0 +1,46 @@ +[Information] +DebChangeFlag=1 +MCUChangeFlag=1 +[Version] +Version=1 +Level=1 +Revision=0 +[Debug Type] +Type=0 +Virtual CPU File=wv907e4.dll +Core ID=0 +Monitor Load=1 +Monitor Load Condition=Enable +ChangeFlag=Enable +[Device] +Communication=USB +ProductID=0 +Protocol=3 +[Target] +AutoLoad=Enable +Before Batch File= +After Batch File= +[Start] +Batch File= +[Window] +Flag=Enable +[Path Environment] +Flag=Enable +[Map] +Flag=Enable +[Radix Environment] +Flag=Enable +[Watch Environment] +Flag=Enable +[Exec Environment] +Flag=Enable +[Break Environment] +Flag=Enable +[Emulation Environment] +Flag=Enable +[Monitor Environment] +Flag=Enable +[Error] +Flag=Enable +[Color] +Flag=Enable diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Config_2/Simulator.sup b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Config_2/Simulator.sup new file mode 100644 index 000000000..cc6ec9e23 --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Config_2/Simulator.sup @@ -0,0 +1,46 @@ +[Information] +DebChangeFlag=1 +MCUChangeFlag=1 +[Version] +Version=1 +Level=1 +Revision=0 +[Debug Type] +Type=1 +Virtual CPU File=wv907f1.dll +Core ID=0 +Monitor Load=1 +Monitor Load Condition=Disable +ChangeFlag=Disable +[Device] +Communication=USB +ProductID=0 +Protocol=3 +[Target] +AutoLoad=Enable +Before Batch File= +After Batch File= +[Start] +Batch File= +[Window] +Flag=Enable +[Path Environment] +Flag=Enable +[Map] +Flag=Enable +[Radix Environment] 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..\..\..\..\..\..\..\devtools\Softune\LIB\907\INCLUDE\stddef.h +F11-11=- ..\..\..\..\..\..\..\devtools\Softune\LIB\907\INCLUDE\stdarg.h +F11-12=- ..\..\..\..\..\..\..\devtools\Softune\LIB\907\INCLUDE\stdlib.h +F11-13=- ..\..\..\..\..\..\..\devtools\Softune\LIB\907\INCLUDE\string.h +F12=0 c 0 ..\..\Common\Minimal\AltBlckQ.c +F13=0 c 0 ..\..\Common\Minimal\AltBlock.c +F14=0 c 0 ..\..\Common\Minimal\AltPollQ.c +F15=0 c 0 ..\..\Common\Minimal\AltQTest.c +F16=12 c 1 ..\..\Common\Minimal\BlockQ.c +F16-1=- ..\..\..\Source\include\FreeRTOS.h +F16-2=- ..\..\..\Source\include\projdefs.h +F16-3=- Src\config\FreeRTOSConfig.h +F16-4=- ..\..\..\Source\include\portable.h +F16-5=- ..\..\..\Source\portable\Softune\MB96340\portmacro.h +F16-6=- src\mb96348hs.h +F16-7=- ..\..\..\Source\include\task.h +F16-8=- ..\..\..\Source\include\list.h +F16-9=- ..\..\..\Source\include\queue.h +F16-10=- ..\..\Common\include\BlockQ.h +F16-11=- ..\..\..\..\..\..\..\devtools\Softune\LIB\907\INCLUDE\stdlib.h +F16-12=- ..\..\..\..\..\..\..\devtools\Softune\LIB\907\INCLUDE\stddef.h +F17=11 c 1 ..\..\Common\Minimal\blocktim.c +F17-1=- ..\..\..\Source\include\FreeRTOS.h +F17-2=- ..\..\..\Source\include\projdefs.h +F17-3=- Src\config\FreeRTOSConfig.h +F17-4=- ..\..\..\Source\include\portable.h +F17-5=- ..\..\..\Source\portable\Softune\MB96340\portmacro.h +F17-6=- src\mb96348hs.h +F17-7=- ..\..\..\Source\include\task.h +F17-8=- ..\..\..\Source\include\list.h +F17-9=- ..\..\..\Source\include\queue.h +F17-10=- ..\..\Common\include\blocktim.h +F17-11=- ..\..\..\..\..\..\..\devtools\Softune\LIB\907\INCLUDE\stddef.h +F18=13 c 1 ..\..\Common\Minimal\comtest.c +F18-1=- ..\..\..\Source\include\FreeRTOS.h +F18-2=- ..\..\..\Source\include\projdefs.h +F18-3=- Src\config\FreeRTOSConfig.h +F18-4=- ..\..\..\Source\include\portable.h +F18-5=- ..\..\..\Source\portable\Softune\MB96340\portmacro.h +F18-6=- src\mb96348hs.h +F18-7=- ..\..\..\Source\include\task.h +F18-8=- ..\..\..\Source\include\list.h +F18-9=- ..\..\Common\include\serial.h +F18-10=- ..\..\Common\include\comtest.h +F18-11=- ..\..\Common\include\partest.h +F18-12=- ..\..\..\..\..\..\..\devtools\Softune\LIB\907\INCLUDE\stdlib.h +F18-13=- ..\..\..\..\..\..\..\devtools\Softune\LIB\907\INCLUDE\stddef.h +F19=0 c 0 ..\..\Common\Minimal\countsem.c +F20=11 c 1 ..\..\Common\Minimal\crhook.c +F20-1=- ..\..\..\Source\include\FreeRTOS.h +F20-2=- ..\..\..\Source\include\projdefs.h +F20-3=- Src\config\FreeRTOSConfig.h +F20-4=- ..\..\..\Source\include\portable.h +F20-5=- ..\..\..\Source\portable\Softune\MB96340\portmacro.h +F20-6=- src\mb96348hs.h +F20-7=- ..\..\..\Source\include\croutine.h +F20-8=- ..\..\..\Source\include\list.h +F20-9=- ..\..\..\Source\include\queue.h +F20-10=- ..\..\Common\include\crhook.h +F20-11=- ..\..\..\..\..\..\..\devtools\Softune\LIB\907\INCLUDE\stddef.h +F21=11 c 1 ..\..\Common\Minimal\death.c +F21-1=- ..\..\..\Source\include\FreeRTOS.h +F21-2=- ..\..\..\Source\include\projdefs.h +F21-3=- Src\config\FreeRTOSConfig.h +F21-4=- ..\..\..\Source\include\portable.h +F21-5=- ..\..\..\Source\portable\Softune\MB96340\portmacro.h +F21-6=- src\mb96348hs.h +F21-7=- ..\..\..\Source\include\task.h +F21-8=- ..\..\..\Source\include\list.h +F21-9=- ..\..\Common\include\death.h +F21-10=- ..\..\..\..\..\..\..\devtools\Softune\LIB\907\INCLUDE\stdlib.h +F21-11=- ..\..\..\..\..\..\..\devtools\Softune\LIB\907\INCLUDE\stddef.h +F22=13 c 1 ..\..\Common\Minimal\dynamic.c +F22-1=- ..\..\..\Source\include\FreeRTOS.h +F22-2=- ..\..\..\Source\include\projdefs.h +F22-3=- Src\config\FreeRTOSConfig.h +F22-4=- ..\..\..\Source\include\portable.h +F22-5=- ..\..\..\Source\portable\Softune\MB96340\portmacro.h +F22-6=- src\mb96348hs.h +F22-7=- ..\..\..\Source\include\task.h +F22-8=- ..\..\..\Source\include\list.h +F22-9=- ..\..\..\Source\include\semphr.h +F22-10=- ..\..\..\Source\include\queue.h +F22-11=- ..\..\Common\include\dynamic.h +F22-12=- ..\..\..\..\..\..\..\devtools\Softune\LIB\907\INCLUDE\stdlib.h +F22-13=- ..\..\..\..\..\..\..\devtools\Softune\LIB\907\INCLUDE\stddef.h +F23=12 c 1 ..\..\Common\Minimal\flash.c +F23-1=- ..\..\..\Source\include\FreeRTOS.h +F23-2=- ..\..\..\Source\include\projdefs.h +F23-3=- Src\config\FreeRTOSConfig.h +F23-4=- ..\..\..\Source\include\portable.h +F23-5=- ..\..\..\Source\portable\Softune\MB96340\portmacro.h +F23-6=- src\mb96348hs.h +F23-7=- ..\..\..\Source\include\task.h +F23-8=- ..\..\..\Source\include\list.h +F23-9=- ..\..\Common\include\partest.h +F23-10=- ..\..\Common\include\flash.h +F23-11=- ..\..\..\..\..\..\..\devtools\Softune\LIB\907\INCLUDE\stdlib.h +F23-12=- ..\..\..\..\..\..\..\devtools\Softune\LIB\907\INCLUDE\stddef.h +F24=13 c 1 ..\..\Common\Minimal\flop.c +F24-1=- ..\..\..\Source\include\FreeRTOS.h +F24-2=- ..\..\..\Source\include\projdefs.h +F24-3=- Src\config\FreeRTOSConfig.h +F24-4=- ..\..\..\Source\include\portable.h +F24-5=- ..\..\..\Source\portable\Softune\MB96340\portmacro.h +F24-6=- src\mb96348hs.h +F24-7=- ..\..\..\Source\include\task.h +F24-8=- ..\..\..\Source\include\list.h +F24-9=- ..\..\Common\include\flop.h +F24-10=- ..\..\..\..\..\..\..\devtools\Softune\LIB\907\INCLUDE\stdlib.h +F24-11=- ..\..\..\..\..\..\..\devtools\Softune\LIB\907\INCLUDE\stddef.h +F24-12=- ..\..\..\..\..\..\..\devtools\Softune\LIB\907\INCLUDE\math.h +F24-13=- ..\..\..\..\..\..\..\devtools\Softune\LIB\907\INCLUDE\errno.h +F25=13 c 1 ..\..\Common\Minimal\GenQTest.c +F25-1=- ..\..\..\Source\include\FreeRTOS.h +F25-2=- ..\..\..\Source\include\projdefs.h +F25-3=- Src\config\FreeRTOSConfig.h +F25-4=- ..\..\..\Source\include\portable.h +F25-5=- ..\..\..\Source\portable\Softune\MB96340\portmacro.h +F25-6=- src\mb96348hs.h +F25-7=- ..\..\..\Source\include\task.h +F25-8=- ..\..\..\Source\include\list.h +F25-9=- ..\..\..\Source\include\queue.h +F25-10=- ..\..\..\Source\include\semphr.h +F25-11=- ..\..\Common\include\GenQTest.h +F25-12=- ..\..\..\..\..\..\..\devtools\Softune\LIB\907\INCLUDE\stdlib.h +F25-13=- ..\..\..\..\..\..\..\devtools\Softune\LIB\907\INCLUDE\stddef.h +F26=11 c 1 ..\..\Common\Minimal\integer.c +F26-1=- ..\..\..\Source\include\FreeRTOS.h +F26-2=- ..\..\..\Source\include\projdefs.h +F26-3=- Src\config\FreeRTOSConfig.h +F26-4=- ..\..\..\Source\include\portable.h +F26-5=- ..\..\..\Source\portable\Softune\MB96340\portmacro.h +F26-6=- src\mb96348hs.h +F26-7=- ..\..\..\Source\include\task.h +F26-8=- ..\..\..\Source\include\list.h +F26-9=- ..\..\Common\include\integer.h +F26-10=- ..\..\..\..\..\..\..\devtools\Softune\LIB\907\INCLUDE\stdlib.h +F26-11=- ..\..\..\..\..\..\..\devtools\Softune\LIB\907\INCLUDE\stddef.h +F27=12 c 1 ..\..\Common\Minimal\PollQ.c +F27-1=- ..\..\..\Source\include\FreeRTOS.h +F27-2=- ..\..\..\Source\include\projdefs.h +F27-3=- Src\config\FreeRTOSConfig.h +F27-4=- ..\..\..\Source\include\portable.h +F27-5=- ..\..\..\Source\portable\Softune\MB96340\portmacro.h +F27-6=- src\mb96348hs.h +F27-7=- ..\..\..\Source\include\task.h +F27-8=- ..\..\..\Source\include\list.h +F27-9=- ..\..\..\Source\include\queue.h +F27-10=- ..\..\Common\include\PollQ.h +F27-11=- ..\..\..\..\..\..\..\devtools\Softune\LIB\907\INCLUDE\stdlib.h +F27-12=- ..\..\..\..\..\..\..\devtools\Softune\LIB\907\INCLUDE\stddef.h +F28=13 c 1 ..\..\Common\Minimal\QPeek.c +F28-1=- ..\..\..\Source\include\FreeRTOS.h +F28-2=- ..\..\..\Source\include\projdefs.h +F28-3=- Src\config\FreeRTOSConfig.h +F28-4=- ..\..\..\Source\include\portable.h +F28-5=- ..\..\..\Source\portable\Softune\MB96340\portmacro.h +F28-6=- src\mb96348hs.h +F28-7=- ..\..\..\Source\include\task.h +F28-8=- ..\..\..\Source\include\list.h +F28-9=- ..\..\..\Source\include\queue.h +F28-10=- ..\..\..\Source\include\semphr.h +F28-11=- ..\..\Common\include\QPeek.h +F28-12=- ..\..\..\..\..\..\..\devtools\Softune\LIB\907\INCLUDE\stdlib.h +F28-13=- ..\..\..\..\..\..\..\devtools\Softune\LIB\907\INCLUDE\stddef.h +F29=13 c 1 ..\..\Common\Minimal\semtest.c +F29-1=- ..\..\..\Source\include\FreeRTOS.h +F29-2=- ..\..\..\Source\include\projdefs.h +F29-3=- Src\config\FreeRTOSConfig.h +F29-4=- ..\..\..\Source\include\portable.h +F29-5=- ..\..\..\Source\portable\Softune\MB96340\portmacro.h +F29-6=- src\mb96348hs.h +F29-7=- ..\..\..\Source\include\task.h +F29-8=- ..\..\..\Source\include\list.h +F29-9=- ..\..\..\Source\include\semphr.h +F29-10=- ..\..\..\Source\include\queue.h +F29-11=- ..\..\Common\include\semtest.h +F29-12=- ..\..\..\..\..\..\..\devtools\Softune\LIB\907\INCLUDE\stdlib.h +F29-13=- ..\..\..\..\..\..\..\devtools\Softune\LIB\907\INCLUDE\stddef.h +F30=0 c 0 ..\..\..\Source\portable\MemMang\heap_1.c +F31=0 c 0 ..\..\..\Source\portable\MemMang\heap_2.c +F32=10 c 1 ..\..\..\Source\portable\MemMang\heap_3.c +F32-1=- ..\..\..\Source\include\FreeRTOS.h +F32-2=- ..\..\..\Source\include\projdefs.h +F32-3=- Src\config\FreeRTOSConfig.h +F32-4=- ..\..\..\Source\include\portable.h +F32-5=- ..\..\..\Source\portable\Softune\MB96340\portmacro.h +F32-6=- src\mb96348hs.h +F32-7=- ..\..\..\Source\include\task.h +F32-8=- ..\..\..\Source\include\list.h +F32-9=- ..\..\..\..\..\..\..\devtools\Softune\LIB\907\INCLUDE\stdlib.h +F32-10=- ..\..\..\..\..\..\..\devtools\Softune\LIB\907\INCLUDE\stddef.h +F33=12 c 1 Src\serial\serial.c +F33-1=- ..\..\..\Source\include\FreeRTOS.h +F33-2=- ..\..\..\Source\include\projdefs.h +F33-3=- Src\config\FreeRTOSConfig.h +F33-4=- ..\..\..\Source\include\portable.h +F33-5=- ..\..\..\Source\portable\Softune\MB96340\portmacro.h +F33-6=- src\mb96348hs.h +F33-7=- ..\..\..\Source\include\queue.h +F33-8=- ..\..\..\Source\include\task.h +F33-9=- ..\..\..\Source\include\list.h +F33-10=- ..\..\Common\include\serial.h +F33-11=- ..\..\..\..\..\..\..\devtools\Softune\LIB\907\INCLUDE\stdlib.h +F33-12=- ..\..\..\..\..\..\..\devtools\Softune\LIB\907\INCLUDE\stddef.h +F34=10 c 1 Src\watchdog\watchdog.c +F34-1=- src\mb96348hs.h +F34-2=- ..\..\..\Source\include\FreeRTOS.h +F34-3=- ..\..\..\Source\include\projdefs.h +F34-4=- Src\config\FreeRTOSConfig.h +F34-5=- ..\..\..\Source\include\portable.h +F34-6=- ..\..\..\Source\portable\Softune\MB96340\portmacro.h +F34-7=- ..\..\..\Source\include\task.h +F34-8=- ..\..\..\Source\include\list.h +F34-9=- Src\watchdog\watchdog.h +F34-10=- ..\..\..\..\..\..\..\devtools\Softune\LIB\907\INCLUDE\stddef.h +F35=9 c 1 Src\utility\taskutility.c +F35-1=- src\mb96348hs.h +F35-2=- ..\..\..\Source\include\FreeRTOS.h +F35-3=- ..\..\..\Source\include\projdefs.h +F35-4=- Src\config\FreeRTOSConfig.h +F35-5=- ..\..\..\Source\include\portable.h +F35-6=- ..\..\..\Source\portable\Softune\MB96340\portmacro.h +F35-7=- ..\..\..\Source\include\task.h +F35-8=- ..\..\..\Source\include\list.h +F35-9=- ..\..\..\..\..\..\..\devtools\Softune\LIB\907\INCLUDE\stddef.h +F36=12 c 1 Src\crflash_sk16fx100mpc.c +F36-1=- ..\..\..\Source\include\FreeRTOS.h +F36-2=- ..\..\..\..\..\..\..\devtools\Softune\LIB\907\INCLUDE\stddef.h +F36-3=- ..\..\..\Source\include\projdefs.h +F36-4=- Src\config\FreeRTOSConfig.h +F36-5=- ..\..\..\Source\include\portable.h +F36-6=- ..\..\..\Source\portable\Softune\MB96340\portmacro.h +F36-7=- src\mb96348hs.h +F36-8=- ..\..\..\Source\include\croutine.h +F36-9=- ..\..\..\Source\include\list.h +F36-10=- ..\..\..\Source\include\queue.h +F36-11=- ..\..\Common\include\partest.h +F36-12=- ..\..\Common\include\crflash.h + +[BUILDMODE-Config_4] +kernel=1 +ABI=0 + +[RUNSET-Config_4] +CONVERT=1 +CONVERTKIND=0 + +[DebState-Config_4] +SupCount=5 +Supfile-0=Config_4\MB2198-01_COM1.sup +Supfile-1=Config_4\MB2198-01_COM2.sup +Supfile-2=Config_4\MB2198-01_LAN.sup +Supfile-3=Config_4\MB2198-01_USB.sup +Supfile-4=Config_4\Simulator.sup +Current=MB2198-01_USB.sup +AliasFile= +CPURunMode=16,16,16,16,0,1,0x0:0x0,,0,0xFF + +[AsmBefore] +Count=0 + +[AsmAfter] +Count=0 + +[CcBefore] +Count=0 + +[CcAfter] +Count=0 + +[LnkBefore] +Count=0 + +[LnkAfter] +Count=0 + +[LibBefore] +Count=0 + +[LibAfter] +Count=0 + +[CnvBefore] +Count=0 + +[CnvAfter] +Count=0 + +[ConfigBefore] +Count=0 + +[ConfigAfter] +Count=0 + diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Prc/romconst.prc b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Prc/romconst.prc new file mode 100644 index 000000000..d56d47ef8 --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Prc/romconst.prc @@ -0,0 +1,325 @@ +# Simulator only: +# Copy ROM-mirror area to bank 0x00 + +if %EVAL(ROMM_CONFIG & 0x01) == 0x01 + +set variable ROMM_BANK = %EVAL(ROMM_CONFIG >> 4) +set variable ROMM_SIZE = %EVAL((ROMM_CONFIG >> 1) & 0x03) + +print "\n\n>Set ROM-mirror memory map...\n" + + +if %ROMM_SIZE == 0 +set map /read H'00E000..H'00FFFF + +if %ROMM_BANK == 0x00 +show map +move H'f0e000..H'F0FFFF,H'e000 + +elseif %ROMM_BANK == 0x01 +show map +move H'f1e000..H'F1FFFF,H'e000 + +elseif %ROMM_BANK == 0x02 +show map +move H'f2e000..H'F2FFFF,H'e000 + +elseif %ROMM_BANK == 0x03 +show map +move H'f3e000..H'F3FFFF,H'e000 + +elseif %ROMM_BANK == 0x04 +show map +move H'f4e000..H'F4FFFF,H'e000 + +elseif %ROMM_BANK == 0x05 +show map +move H'f5e000..H'F5FFFF,H'e000 + +elseif %ROMM_BANK == 0x06 +show map +move H'f6e000..H'F6FFFF,H'e000 + +elseif %ROMM_BANK == 0x07 +show map +move H'f7e000..H'F7FFFF,H'e000 + +elseif %ROMM_BANK == 0x08 +show map +move H'f8e000..H'F8FFFF,H'e000 + +elseif %ROMM_BANK == 0x09 +show map +move H'f9e000..H'F9FFFF,H'e000 + +elseif %ROMM_BANK == 0x0A +show map +move H'fAe000..H'FAFFFF,H'e000 + +elseif %ROMM_BANK == 0x0B +show map +move H'fBe000..H'FBFFFF,H'e000 + +elseif %ROMM_BANK == 0x0B +show map +move H'fBe000..H'FBFFFF,H'e000 + +elseif %ROMM_BANK == 0x0C +show map +move H'fCe000..H'FCFFFF,H'e000 + +elseif %ROMM_BANK == 0x0D +show map +move H'fde000..H'FDFFFF,H'e000 + +elseif %ROMM_BANK == 0x0E +show map +move H'fee000..H'FEFFFF,H'e000 + +elseif %ROMM_BANK == 0x0F +show map +move H'ffe000..H'FFFFFF,H'e000 + +endif # ROMM_BANK selection + +elseif %ROMM_SIZE == 1 +set map /read H'00C000..H'00FFFF + +if %ROMM_BANK == 0x00 +show map +move H'f0c000..H'F0FFFF,H'c000 + +elseif %ROMM_BANK == 0x01 +show map +move H'f1c000..H'F1FFFF,H'c000 + +elseif %ROMM_BANK == 0x02 +show map +move H'f2c000..H'F2FFFF,H'c000 + +elseif %ROMM_BANK == 0x03 +show map +move H'f3c000..H'F3FFFF,H'c000 + +elseif %ROMM_BANK == 0x04 +show map +move H'f4c000..H'F4FFFF,H'c000 + +elseif %ROMM_BANK == 0x05 +show map +move H'f5c000..H'F5FFFF,H'c000 + +elseif %ROMM_BANK == 0x06 +show map +move H'f6c000..H'F6FFFF,H'c000 + +elseif %ROMM_BANK == 0x07 +show map +move H'f7c000..H'F7FFFF,H'c000 + +elseif %ROMM_BANK == 0x08 +show map +move H'f8c000..H'F8FFFF,H'c000 + +elseif %ROMM_BANK == 0x09 +show map +move H'f9c000..H'F9FFFF,H'c000 + +elseif %ROMM_BANK == 0x0A +show map +move H'fAc000..H'FAFFFF,H'c000 + +elseif %ROMM_BANK == 0x0B +show map +move H'fBc000..H'FBFFFF,H'c000 + +elseif %ROMM_BANK == 0x0B +show map +move H'fBc000..H'FBFFFF,H'c000 + +elseif %ROMM_BANK == 0x0C +show map +move H'fCc000..H'FCFFFF,H'c000 + +elseif %ROMM_BANK == 0x0D +show map +move H'fdc000..H'FDFFFF,H'c000 + +elseif %ROMM_BANK == 0x0E +show map +move H'fec000..H'FEFFFF,H'c000 + +elseif %ROMM_BANK == 0x0F +show map +move H'ffc000..H'FFFFFF,H'c000 + +endif # ROMM_BANK selection + +elseif %ROMM_SIZE == 2 +set map /read H'00A000..H'00FFFF + +if %ROMM_BANK == 0x00 +show map +move H'f0a000..H'F0FFFF,H'a000 + +elseif %ROMM_BANK == 0x01 +show map +move H'f1a000..H'F1FFFF,H'a000 + +elseif %ROMM_BANK == 0x02 +show map +move H'f2a000..H'F2FFFF,H'a000 + +elseif %ROMM_BANK == 0x03 +show map +move H'f3a000..H'F3FFFF,H'a000 + +elseif %ROMM_BANK == 0x04 +show map +move H'f4a000..H'F4FFFF,H'a000 + +elseif %ROMM_BANK == 0x05 +show map +move H'f5a000..H'F5FFFF,H'a000 + +elseif %ROMM_BANK == 0x06 +show map +move H'f6a000..H'F6FFFF,H'a000 + +elseif %ROMM_BANK == 0x07 +show map +move H'f7a000..H'F7FFFF,H'a000 + +elseif %ROMM_BANK == 0x08 +show map +move H'f8a000..H'F8FFFF,H'a000 + +elseif %ROMM_BANK == 0x09 +show map +move H'f9a000..H'F9FFFF,H'a000 + +elseif %ROMM_BANK == 0x0A +show map +move H'fAa000..H'FAFFFF,H'a000 + +elseif %ROMM_BANK == 0x0B +show map +move H'fBa000..H'FBFFFF,H'a000 + +elseif %ROMM_BANK == 0x0B +show map +move H'fBa000..H'FBFFFF,H'a000 + +elseif %ROMM_BANK == 0x0C +show map +move H'fCa000..H'FCFFFF,H'a000 + +elseif %ROMM_BANK == 0x0D +show map +move H'fda000..H'FDFFFF,H'a000 + +elseif %ROMM_BANK == 0x0E +show map +move H'fea000..H'FEFFFF,H'a000 + +elseif %ROMM_BANK == 0x0F +show map +move H'ffa000..H'FFFFFF,H'a000 + +endif # ROMM_BANK selection + +elseif %ROMM_SIZE == 3 +set map /read H'008000..H'00FFFF + +if %ROMM_BANK == 0x00 +show map +move H'f08000..H'F0FFFF,H'8000 + +elseif %ROMM_BANK == 0x01 +show map +move H'f18000..H'F1FFFF,H'8000 + +elseif %ROMM_BANK == 0x02 +show map +move H'f28000..H'F2FFFF,H'8000 + +elseif %ROMM_BANK == 0x03 +show map +move H'f38000..H'F3FFFF,H'8000 + +elseif %ROMM_BANK == 0x04 +show map +move H'f48000..H'F4FFFF,H'8000 + +elseif %ROMM_BANK == 0x05 +show map +move H'f58000..H'F5FFFF,H'8000 + +elseif %ROMM_BANK == 0x06 +show map +move H'f68000..H'F6FFFF,H'8000 + +elseif %ROMM_BANK == 0x07 +show map +move H'f78000..H'F7FFFF,H'8000 + +elseif %ROMM_BANK == 0x08 +show map +move H'f88000..H'F8FFFF,H'8000 + +elseif %ROMM_BANK == 0x09 +show map +move H'f98000..H'F9FFFF,H'8000 + +elseif %ROMM_BANK == 0x0A +show map +move H'fA8000..H'FAFFFF,H'8000 + +elseif %ROMM_BANK == 0x0B +show map +move H'fB8000..H'FBFFFF,H'8000 + +elseif %ROMM_BANK == 0x0B +show map +move H'fB8000..H'FBFFFF,H'8000 + +elseif %ROMM_BANK == 0x0C +show map +move H'fC8000..H'FCFFFF,H'8000 + +elseif %ROMM_BANK == 0x0D +show map +move H'fd8000..H'FDFFFF,H'8000 + +elseif %ROMM_BANK == 0x0E +show map +move H'fe8000..H'FEFFFF,H'8000 + +elseif %ROMM_BANK == 0x0F +show map +move H'ff8000..H'FFFFFF,H'8000 + +endif # ROMM_BANK selection + +endif # ROMM_SIZE selection + +print ">Copy ROMCONST for simulation..." +print "OK" + +print "\n-----------------------------------------------------------" +print "\nUse command \"batch prc\\romconst.prc\" after each download" +print "\n-----------------------------------------------------------" + +else + +print "\n----------------------" +print "\nROM Mirror disabled!!!" +print "\n----------------------" + +endif + +print "\n-------------------------------------------------------------------" +print "\nSetting CKMR to 0xF0 to allow for the Clock Wait in that start.asm." +print "\n-------------------------------------------------------------------" + +set MEM /byte 0x0403 = 0xF0 diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Simulator.sup b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Simulator.sup new file mode 100644 index 000000000..6e44211ea --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Simulator.sup @@ -0,0 +1,210 @@ +[Information] +DebChangeFlag=0 +MCUChangeFlag=0 + +[Version] +Version=1 +Level=1 +Revision=0 + +[Debug Type] +Type=1 +Virtual CPU File=wv907f1.dll +Monitor Load=1 +Monitor Load Condition=Disable +Core ID=0 + +[Device] +Communication=LAN 141.187.6.53 +ProductID=0 +Protocol=3 + +[Target] +AutoLoad=Enable +Before Batch File= +After Batch File=Prc\romconst.prc +Non AutoMap=Disable +Load DebInfo Only=Disable +Ondemand Load Condition=Disable + +[Start] +Batch File= + +[Window] +Flag=Enable +AssemblySize=0 0 0 0 +AssemblyState=0 +AssemblyFGColor=0 0 255 +Assembly Address=H'000000 +Memory Address=H'004241 +Memory Mode=H'00000001 +Memory Ascii=H'00000001 +Memory SplitRow=0 +RMemory Address=H'000000 +RMemory Mode=H'FFFFFFFF +RMemory Ascii=H'00000001 +RMemory SplitRow=0 +Trace ViewMode=1 +Command Max History=H'00000032 +Source Display Mode=Enable +Source Multi Mode=Enable +Source Ask Mode=Enable +Source Active Mode=Enable +Source PC Color=255 255 0 +Source Scope Color=255 0 255 +Source Back Trace=255 0 255 +Register Change Color=255 0 0 +Perfomance Mode=H'00000001 +Perfomance Scale=1 0 0.000000 0.000000 +Coverage Address=H'000000 +Coverage Type=H'00000000 +RMemory Change Color=255 0 0 +RMemory Invalid Color=128 128 128 +CommandSize=0 534 359 712 +CommandState=0 +MemorySize=487 476 974 714 +MemoryState=0 +Layer0=1003, +Coverage SplitRow=0 +Layer1=1006, +Layer2=1004, +Source0Name=Src\Main.c +Source0Size=487 238 974 476 +Source0State=2 +Source0Line=21 +Source0Mode=1 +Source1Name=Src\Start.asm +Source1Size=154 154 912 653 +Source1State=0 +Source1Line=40C +Source1Mode=2 +RegisterSize=487 0 974 238 +RegisterState=0 +Layer3=2000,Src\Start.asm +Register Select0=H'00000000 +Register Select1=H'00000003 +Register Select2=H'00000004 +Register Select3=H'00000005 +Register Select4=H'00000006 +Register Select5=H'00000007 +Register Select6=H'00000008 +Register Select7=H'00000010 +Register Select8=H'00000011 +Register Select9=H'00000012 +Register Select10=H'00000013 +Register Select11=H'00000014 +Register Select12=H'00000015 +Register Select13=H'00000016 +Register Select14=H'00000017 +Register Select15=H'00000018 +Register Select16=H'00000022 +Register Select17=H'00000023 +Register Select18=H'00000024 +Register Select19=H'00000025 +Register Select20=H'00000026 +Register Select21=H'00000027 +Register Select22=H'00000028 +Register Select23=H'00000029 +Register Select24=H'00000035 +WatchSize=0 357 487 714 +WatchState=0 +Watch Variable0=[pxCurrentTCB],92040000,1,-1 -1 +Watch Variable1=[pxTCB],10080000,1,-1 -1 +Watch Variable2=[usCriticalNesting],91030000,1,-1 -1 +LocalSize=388 0 582 161 +LocalState=0 +Layer4=1007, +Layer5=2000,Src\Main.c +TraceSize=243 178 486 356 +TraceState=0 +Watch Variable3=[*ptr],90080000,1,-1 -1 + +[Path Environment] +Flag=Enable +Source= + +[Map] +Flag=Enable +Area0=00000000 000000EF 3 0 0 +Area2=00000100 0000017F 3 0 0 +Area3=00000180 0000018F 7 0 0 +Area4=00000190 00000369 3 0 0 +Area5=0000036A 0000037F 7 0 0 +Area6=00000380 00000BFF 3 0 0 +Area8=00002240 0000470F 3 0 0 +Area9=00004710 00007FFF 7 0 0 +Area10=00008000 0000FFFF 1 0 0 +Area12=000F0000 000F0FFF 3 0 0 +Area14=000FE000 000FFFFF 5 0 0 +Area16=00DE0000 00DE7FFF 5 0 0 +Area18=00DF0000 00DF7FFF 5 0 0 +Area20=00F80000 00FFFFFF 5 0 0 +Inrom Image=Off + +[Radix Environment] +Flag=Enable +Mode=10 +Source=1 + +[Watch Environment] +Flag=Enable +Size=0 +Mode=0 +MBuf=0 +Check=1 +CSiz=100 + +[Exec Environment] +Flag=Enable +GoIntMask=0 +StepUnit=3 +StepIntMask=0 +StepIntpCtrl=4 +GoTrcCtrl=2 +OnTheFlyBreakAdmit=0 + +[Break Environment] +Flag=Enable +Code0=00DE00F1 1 0 1 +CodeBreakFlag0=Enable +Code1=00DE012F 1 0 1 main.c$103 +CodeBreakFlag1=Enable +Debug File=C:\Fujitsu\FreeRTOS\FreeRTOS Port 16FX\96340_FreeRTOS_96348hs-v17\96340_FreeRTOS_96348hs-v17\ABS\96340_FreeRTOS_96348hs.abs +Code2=00DE013E 1 0 1 +CodeBreakFlag2=Enable +Code3=00DE1B64 1 0 1 \prvRLT0_TICKISR +CodeBreakFlag3=Enable + +[Emulation Environment] +Flag=Disable + +[Monitor Environment] +Flag=Enable +MemoryWindow=1 +WatchWindow=0 +ObjectWindow=0 +ElapseTime=3E8 +Unit=1 +Mode=0 +RealtimeMemoryWindow=0 + +[Error] +Flag=Enable +GuiErrorOutput=2 +CommandErrorOutput=1 +BatchErrorOutput=1 +ErrorOutputLevel=0 + +[Color] +Flag=Enable + +[Tab Environment] +TabSize=8 + +[Communication] +Send=1000 +Receive=64 + +[Trace Environment] +Trace Break=0 +Trace Status=1 diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/START.ASM b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/START.ASM new file mode 100644 index 000000000..711f6606d --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/START.ASM @@ -0,0 +1,1835 @@ +;==================================================================== +; THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. +; FUJITSU MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY +; FOR ANY ERRORS OR ELIGIBILITY FOR ANY PURPOSES. +; +; Startup file for memory and basic controller initialisation +; +; MB96300 Family C Compiler +; +; (C) FUJITSU MICROELECTRONICS EUROPE 1998-2008 +;==================================================================== + + .PROGRAM STARTUP + .TITLE "STARTUP FILE FOR MEMORY INITIALISATION" + +;==================================================================== +; 1 Contents +;==================================================================== +; 1 Contents +; 2 Disclaimer +; 3 History +; +; 4 SETTINGS (USER INTERFACE) +; 4.1 Controller Series +; 4.2 C-language Memory model +; 4.3 Function-Call Interface +; 4.4 Constant Data Handling +; 4.5 Stack Type and Stack Size +; 4.6 General Register Bank +; 4.7 Low-Level Library Interface +; 4.8 Clock Selection +; 4.9 Clock Stabilization Time +; 4.10 External Bus Interface +; 4.11 ROM Mirror configuration +; 4.12 Flash Security +; 4.13 Flash Write Protection +; 4.14 Boot Vector +; 4.15 UART scanning +; 4.16 Enable RAMCODE Copying +; 4.17 Enable information stamp in ROM +; 4.18 Enable Background Debugging Mode +; +; 5 Section and Data Declaration +; 5.1 Several fixed addresses (fixed for MB963xx controllers) +; 5.2 Declaration of __near addressed data sections +; 5.3 Declaration of RAMCODE section and labels +; 5.4 Declaration of sections containing other sections description +; 5.5 Stack area and stack top definition/declaration +; 5.6 Direct page register dummy label definition +; +; 6 Start-Up Code +; 6.1 Import external symbols +; 6.2 Program start (the boot vector should point here) +; 6.3 "NOT RESET YET" WARNING +; 6.4 Initialisation of processor status +; 6.5 Set clock ratio (ignore subclock) +; 6.6 Set external bus configuration +; 6.7 Prepare stacks and set the active stack type +; 6.8 Copy initial values to data areas +; 6.9 Clear uninitialised data areas to zero +; 6.10 Set Data Bank Register (DTB) and Direct Page Register (DPR) +; 6.11 Wait for PLL to stabilise +; 6.12 Initialise Low-Level Library Interface +; 6.13 Call C-language main function +; 6.14 Shut down library +; 6.15 Program end loop +; 6.16 Set Flash Security +; 6.17 Set Flash write protection +; 6.18 Debug address specification +; +;==================================================================== +; 2 Disclaimer +;==================================================================== +; FUJITSU MICROELECTRONICS EUROPE GMBH +; Pittlerstrasse 47, 63225 Langen, Germany +; Tel.:++49 6103 690-0, Fax -122 +; +; The following software is for demonstration purposes only. +; It is not fully tested, nor validated in order to fulfil +; its task under all circumstances. Therefore, this software +; or any part of it must only be used in an evaluation +; laboratory environment. +; This software is subject to the rules of our standard +; DISCLAIMER, that is delivered with our SW-tools on the +; Fujitsu Microcontrollers CD (V3.4 or higher "\START.HTM") or +; on our Internet Pages: +; http://www.fme.gsdc.de/gsdc.htm +; http://emea.fujitsu.com/microelectronics +; +;==================================================================== +; 3 History +;==================================================================== +; $Id: START.ASM,v 1.25 2007/09/28 07:33:18 mcuae Exp $ + + +#define VERSION "1.25" +/* +$Log: START.ASM,v $ +Revision 1.25 2007/09/28 07:33:18 mcuae +Bug in BDM baudrate calculation corrected + +Revision 1.24 2007/09/26 14:03:08 mcuae +- Device list for MB96340 series updated and expanded + +Revision 1.23 2007/08/06 14:48:16 mcuae +- BDM section always reserved, filled with 0xFF, if not configured + +Revision 1.22 2007/08/02 08:34:03 mcuae +- communication mode bits of BDM configuration grouped + +Revision 1.21 2007/07/13 08:23:05 mwilla +device selection for BDM baud rate improved + +Revision 1.20 2007/06/12 10:43:57 mwilla +- BDM-Baud-Rate calculation includes crystal frequency + +Revision 1.19 2007/06/06 07:46:55 mwilla +- add Background Debugging Configuration +- Stack initialization moved before variable initialization +- values of cystal frequency and device macros changed + +Revision 1.18 2007/04/16 07:56:02 phuene +- update clock settings when crystal is 8 MHz so that the CLKVCO is low + +Revision 1.17 2007/04/10 11:30:43 phuene +- add MB96320 Series +- Clock settings optimized for CPU_8MHZ_CLKP2_8MHZ, CPU_12MHZ_CLKP2_12MHZ, CPU_16MHZ_CLKP2_16MHZ, CPU_24MHZ_CLKP2_24MHZ, CPU_32MHZ_CLKP2_32MHZ +- make the selection for the individual devices also consider the selected Series +- support 8 MHz crystal +- add clock setting CPU_32MHZ_CLKP1_16MHZ_CLKP2_16MHZ +- prohibit CPU_32MHZ_CLKP2_16MHZ, CPU_CLKP1_16MHZ_CLKP2_16MHZ for MB96F348H and MB96F348T according to functional limitation 16FXFL0014 + +Revision 1.16 2007/02/07 12:38:10 phuene +- support disabling the UART scanning in Internal Vector Mode +- distinguish between Reset Vector and Boot Vector: the Boot Vector points to the start of the user application + +Revision 1.15 2007/02/07 09:00:19 phuene +- add .SKIP instructions to occupy the whole ROM configuration block area + +Revision 1.14 2007/01/29 13:15:06 phuene +- fix CPU_4MHZ_MAIN_CLKP2_4MHZ clock setting + +Revision 1.13 2007/01/03 10:40:14 phuene +- change clock setting CPU_24MHZ_CLKP2_16MHZ to CPU_24MHZ_CLKP2_12MHZ; this allows for better performance of MB96F348H/T +- use additional preprocessor statements to avoid checking for PLL ready twice in some cases + +Revision 1.12 2007/01/02 10:16:20 phuene +- correct CLKP2 (CAN) clock for CPU_32MHZ and MB96F348H/T +- correct CLKP2 (CAN) clock for CPU_24MHZ for all other devices than MB96F348H/T + +Revision 1.11 2006/12/28 10:49:52 phuene +- corrected PLL setting for CPU_16MHZ for MB96348H, MB96348T + +Revision 1.10 2006/12/28 08:41:57 phuene +- correct revision number at new location + +Revision 1.1 2006/12/28 07:20:01 phuene +- new location in CVS + +Revision 1.9 2006/12/27 13:00:45 phuene +- add support for ROM Mirror when using the Simulator +- add support for 16FXFL0022, 16FXFL0023 + +Revision 1.8 2006/12/11 16:43:37 phuene +- fix typo + +Revision 1.7 2006/12/11 16:35:08 phuene +- add setting for Clock Stabilization Times +- modify clock settings: + - CLKP2 < 28 MHz + - remove clock settings using more wait cycles than absolutely required + +Revision 1.6 2006/11/03 13:38:45 phuene +- modify clock settings to also set the Flash Memory Timing +- add support for both parameter passing models + +Revision 1.5 2006/08/07 14:01:44 phuene +- change default clock setting to PLLx4 for CLKS1, CLKS2 +- correct clock setting +- disable Flash Security by default for Main Flash, Satellite Flash +- disable availability of Satellite Flash by default + +Revision 0.1 2006/01/25 15:37:46 phu +- initial version based on start.asm for MB90340 Series, version 3.8 +Revision 0.2 2006/07/14 15:37:46 phu +- include PIER settings for External Bus operation +Revision 0.3 2006/07/14 15:37:46 phu +- add MB96350 Series +- correct PIER settings for HRQ and RDY signals +Revision 0.4 2006/08/07 15:35:35 phu +- change default clock setting to PLLx4 for CLKS1, CLKS2 +- correct clock setting +- disable Flash Security by default for Main Flash, Satellite Flash +- disable availability of Satellite Flash by default +*/ +;==================================================================== + +;==================================================================== +; 4 Settings +;==================================================================== +; +; CHECK ALL OPTIONS WHETHER THEY FIT TO THE APPLICATION +; +; Configure this startup file in the "Settings" section. Search for +; comments with leading "; <<<". This points to the items to be set. +;==================================================================== +#set OFF 0 +#set ON 1 + +;==================================================================== +; 4.1 Controller Series, Device +;==================================================================== + +#set MB96320 0 +#set MB96340 1 +#set MB96350 2 +#set MB96360 3 +#set MB96380 4 + +#set SERIES MB96340 ; <<< select Series + + +; Only if SERIES = MB96340 was selected, please specify the device +; according to the following selection +; Note: Do not change order because of device number dependency in +; 6.5 Clock settings and 6.18 Debug address specification! +#set MB96348HA 1 +#set MB96348TA 2 +#set MB96346RA 3 +#set MB96346YA 4 +#set MB96346AA 5 +#set MB96347RA 6 +#set MB96347YA 7 +#set MB96347AA 8 +#set MB96348RA 9 +#set MB96348YA 10 +#set MB96348AA 11 +#set MB96346RB 12 +#set MB96346AB 13 +#set MB96346YB 14 +#set MB96347RB 15 +#set MB96347AB 16 +#set MB96347YB 17 +#set MB96348CA 18 +#set MB96348HB 19 +#set MB96348TB 20 +#set MB96348RB 21 +#set MB96348AB 22 +#set MB96348YB 23 +#set MB96348CC 24 +#set MB96348HC 25 +#set MB96348TC 26 + +#set DEVICE MB96348HB ; <<< select device if Series = MB96340 + +;==================================================================== +; 4.2 C-language Memory model +;==================================================================== + + ; data code +#set SMALL 0 ; 16 Bit 16 Bit +#set MEDIUM 1 ; 16 Bit 24 Bit +#set COMPACT 2 ; 24 Bit 16 Bit +#set LARGE 3 ; 24 Bit 24 Bit +#set AUTOMODEL 4 ; works always, might occupy two + ; additional bytes + + +#set MEMMODEL AUTOMODEL ; <<< C-memory model + +; The selected memory model should be set in order to fit to the +; model selected for the compiler. +; Note, in this startup version AUTOMODEL will work for all +; C-models. However, if the compiler is configured for SMALL or +; COMPACT, two additional bytes on stack are occupied. If this is not +; acceptable, the above setting should be set to the correct model. + +;==================================================================== +; 4.3 Function-Call Interface +;==================================================================== + #if __REG_PASS__ + .REG_PASS + #endif + +; Above statement informs Assembler on compatibility of start-up code +; to Function Call Interface as selected for the application. There +; is nothing to configure. +; The Function-Call Interface specifies the method of passing parame- +; ter from function caller to callee. The standard method of FCC907S +; compiler uses "stack argument passing". Alternatively, language +; tools can be configured for "register argument passing". +; For details see the compiler manual. +; This start-up file is compatible to both interfaces. + +;==================================================================== +; 4.4 Constant Data Handling +;==================================================================== + +#set ROMCONST 0 ; works only with compiler ROMCONST +#set RAMCONST 1 ; works with BOTH compiler settings +#set AUTOCONST RAMCONST ; works with BOTH compiler settings + +#set CONSTDATA AUTOCONST ; <<< set RAM/ROM/AUTOCONST + +; - AUTOCONST (default) is the same as RAMCONST +; - RAMCONST/AUTOCONST should always work, even if compiler is set to +; ROMCONST. If compiler is set to ROMCONST and this startup file is +; set to RAMCONST or AUTOCONST, this startup file will generate an +; empty section CINIT in RAM. However, the code, which copies from +; CONST to CINIT will not have any effect, because size of section is 0. +; - It is highly recommended to set the compiler to ROMCONST for +; single-chip mode or internal ROM+ext bus. The start-up file +; should be set to AUTOCONST. +; - ROMCONST setting on systems with full external bus requires exter- +; nal address mapping. +; Single-chip can be emulated by the emulator debugger. +; ROM mirror can also be used with simulator. +; +; see also ROM MIRROR options + +;==================================================================== +; 4.5 Stack Type and Stack Size +;==================================================================== + +#set USRSTACK 0 ; user stack: for main program +#set SYSSTACK 1 ; system stack: for main program and interrupts + +#set STACKUSE SYSSTACK ; <<< set active stack + +#set STACK_RESERVE ON ; <<< reserve stack area in this module +#set STACK_SYS_SIZE 1500 ; <<< byte size of System stack +#set STACK_USR_SIZE 2 ; <<< byte size of User stack + +#set STACK_FILL ON ; <<< fills the stack area with pattern +#set STACK_PATTERN 0x55AA ; <<< the pattern to write to stack + +; - If the active stack is set to SYSSTACK, it is used for main program +; and interrupts. In this case, the user stack can be set to a dummy +; size. +; If the active stack is set to user stack, it is used for the main +; program but the system stack is automatically activated, if an inter- +; rupt is serviced. Both stack areas must have a reasonable size. +; - If STACK_RESERVE is ON, the sections USTACK and SSTACK are reserved +; in this module. Otherwise, they have to be reserved in other modules. +; If STACK_RESERVE is OFF, the size definitions STACK_SYS_SIZE and +; STACK_USR_SIZE have no meaning. +; - Even if they are reserved in other modules, they are still initialised +; in this start-up file. +; - Filling the stack with a pattern allows to dynamically check the stack +; area, which had already been used. +; +; - If only system stack is used and SSB is linked to a different bank +; than USB, make sure that all C-modules (which generate far pointers +; to stack data) have "#pragma SSB". Applies only to exclusive confi- +; gurations. +; - Note, several library functions require quite a big stack (due to +; ANSI). Check the stack information files (*.stk) in the LIB\907 +; directory. + +;==================================================================== +; 4.6 General Register Bank +;==================================================================== + +#set REGBANK 0 ; <<< set default register bank + +; set the General Register Bank that is to be used after startup. +; Usually, this is bank 0, which applies to address H'180..H'18F. Set +; in the range from 0 to 31. +; Note: All used register banks have to be reserved (linker options). + +#if REGBANK > 31 || REGBANK < 0 +# error REGBANK setting out of range +#endif + +;==================================================================== +; 4.7 Low-Level Library Interface +;==================================================================== + +#set CLIBINIT OFF ; <<< select extended library usage + +; This option has only to be set, if stream-IO/standard-IO function of +; the C-library have to be used (printf(), fopen()...). This also +; requires low-level functions to be defined by the application +; software. +; For other library functions (like e.g. sprintf()) all this is not +; necessary. However, several functions consume a large amount of stack. + +;==================================================================== +; 4.8 Clock Selection +;==================================================================== + +; The clock selection requires that a 4 MHz external clock is provided +; as the Main Clock. If a different frequency is used, the Flash Memory +; Timing settings must be checked! + +#set CLOCKWAIT ON ; <<< wait for stabilized clock, if + ; Main Clock or PLL is used + +; The clock is set quite early. However, if CLOCKWAIT is ON, polling +; for machine clock to be switched to Main Clock or PLL is done at +; the end of this file. Therefore, the stabilization time is not +; wasted. Main() will finally start at correct speed. Resources can +; be used immediately. +; Note: Some frequency settings (below) necessarily need a stabilized +; PLL for final settings. In these cases, the CLOCKWAIT setting above +; does not have any effect. +; +; This startup file version does not support subclock. + +#set FREQ_4MHZ D'4000000L +#set FREQ_8MHZ D'8000000L + +#set CRYSTAL FREQ_4MHZ ; <<< select external crystal frequency + +#set CPU_4MHZ_MAIN_CLKP2_4MHZ 0x0004 +#set CPU_4MHZ_PLL_CLKP2_4MHZ 0x0104 +#set CPU_8MHZ_CLKP2_8MHZ 0x0108 +#set CPU_12MHZ_CLKP2_12MHZ 0x010C +#set CPU_16MHZ_CLKP2_16MHZ 0x0110 +#set CPU_24MHZ_CLKP2_12MHZ 0x0118 +#set CPU_32MHZ_CLKP2_16MHZ 0x0120 +#set CPU_32MHZ_CLKP1_16MHZ_CLKP2_16MHZ 0x0220 +#set CPU_48MHZ_CLKP2_16MHZ 0x0130 +#set CPU_56MHZ_CLKP2_14MHZ 0x0138 + +#set CLOCK_SPEED CPU_56MHZ_CLKP2_14MHZ ; <<< set clock speeds + +; The peripheral clock CLKP1 is set to the same frequency than the CPU. +; The peripheral clock CLKP2 has its setting. This is because it +; feeds only the CAN controllers and Sound Generators. These do not +; need high frequency clocks. + +;==================================================================== +; 4.9 Clock Stabilization Time +;==================================================================== + +#set MC_2_10_CYCLES 0 +#set MC_2_12_CYCLES 1 +#set MC_2_13_CYCLES 2 +#set MC_2_14_CYCLES 3 +#set MC_2_15_CYCLES 4 +#set MC_2_16_CYCLES 5 +#set MC_2_17_CYCLES 6 +#set MC_2_18_CYCLES 7 + +#set MC_STAB_TIME MC_2_15_CYCLES ; <<< select Main Clock Stabilization Time + +;==================================================================== +; 4.10 External Bus Interface +;==================================================================== + +#set SINGLE_CHIP 0 ; all internal +#set INTROM_EXTBUS 1 ; mask ROM or FLASH memory used +#set EXTROM_EXTBUS 2 ; full external bus (INROM not used) + +#set BUSMODE SINGLE_CHIP ; <<< set bus mode (see mode pins) + +#set MULTIPLEXED 0 ; +#set NON_MULTIPLEXED 1 ; only if supported by the device + +#set ADDRESSMODE MULTIPLEXED ; <<< set address-mode + +; Some devices support multiplexed and/or non-multiplexed Bus mode +; please refer to the related datasheet/hardwaremanual + + +; If BUSMODE is "SINGLE_CHIP", ignore remaining bus settings. + +; Select the used Chip Select areas +#set CHIP_SELECT0 OFF ; <<< enable chip select area +#set CHIP_SELECT1 OFF ; <<< enable chip select area +#set CHIP_SELECT2 OFF ; <<< enable chip select area +#set CHIP_SELECT3 OFF ; <<< enable chip select area +#set CHIP_SELECT4 OFF ; <<< enable chip select area +#set CHIP_SELECT5 OFF ; <<< enable chip select area + +#set HOLD_REQ OFF ; <<< select Hold function +#set EXT_READY OFF ; <<< select external Ready function +#set EXT_CLOCK_ENABLE OFF ; <<< select external bus clock output +#set EXT_CLOCK_INVERT OFF ; <<< select clock inversion +#set EXT_CLOCK_SUSPEND OFF ; <<< select if external clock is suspended when no transfer in progress + +; The external bus clock is derived from core clock CLKB. Select the divider for the external bus clock. + +#set EXT_CLOCK_DIV1 0 +#set EXT_CLOCK_DIV2 1 +#set EXT_CLOCK_DIV4 2 +#set EXT_CLOCK_DIV8 3 +#set EXT_CLOCK_DIV16 4 +#set EXT_CLOCK_DIV32 5 +#set EXT_CLOCK_DIV64 6 +#set EXT_CLOCK_DIV128 7 + +#set EXT_CLOCK_DIVISION EXT_CLOCK_DIV1 ; <<< select clock divider + +#set ADDR_PINS_23_16 B'00000000 ; <<< select used address lines + ; A23..A16 to be output. +#set ADDR_PINS_15_8 B'00000000 ; <<< select used address lines + ; A15..A8 to be output. +#set ADDR_PINS_7_0 B'00000000 ; <<< select used address lines + ; A7..A0 to be output. + +#set LOW_BYTE_SIGNAL OFF ; select low byte signal LBX +#set HIGH_BYTE_SIGNAL OFF ; select high byte signal UBX +#set LOW_WRITE_STROBE OFF ; select write strobe signal WRLX/WRX +#set HIGH_WRITE_STROBE OFF ; select write strobe signal WRHX +#set READ_STROBE OFF ; select read strobe signal RDX +#set ADDRESS_STROBE OFF ; select address strobe signal ALE/ASX +#set ADDRESS_STROBE_LVL OFF ; select address strobe function: OFF - active low; ON - active high + + +#set CS0_CONFIG B'0000000000000000 ; <<< select Chip Select Area 0 configuration +; |||||||||||||+++-- Automatic wait cycles (0: 0, 1: 1, 2: 2, 3: 3, 4: 4, 5: 8, 6: 16, 7: 32) +; ||||||||||||+----- Address Cycle Extension (0: not extended, 1: extension by 1 cycle) +; |||||||||||+------ Strobe timing (0: scheme 0, 1: scheme 1) +; ||||||||||+------- Write strobe function (0: WRLX strobe, 1: WRX strobe) +; |||||||||+-------- Endianess (0: little endian, 1: big endian) +; ||||||||+--------- Bus width (0: 16bit, 1: 8bit) +; |||||+++---------- ignored +; ||||+------------- Chip Select output enable (0: CS disabled, 1: CS enabled) +; |||+-------------- Chip Select level (0: low active, 1: high active) +; ||+--------------- Access type limitation (0: code and data, 1: data only) +; ++---------------- ignored + +#set CS1_CONFIG B'0000000000000000 ; <<< select Chip Select Area 1 configuration +; |||||||||||||+++-- Automatic wait cycles (0: 0, 1: 1, 2: 2, 3: 3, 4: 4, 5: 8, 6: 16, 7: 32) +; ||||||||||||+----- Address Cycle Extension (0: not extended, 1: extension by 1 cycle) +; |||||||||||+------ Strobe timing (0: scheme 0, 1: scheme 1) +; ||||||||||+------- Write strobe function (0: WRLX strobe, 1: WRX strobe) +; |||||||||+-------- Endianess (0: little endian, 1: big endian) +; ||||||||+--------- Bus width (0: 16bit, 1: 8bit) +; |||||+++---------- ignored +; ||||+------------- Chip Select output enable (0: CS disabled, 1: CS enabled) +; |||+-------------- Chip Select level (0: low active, 1: high active) +; ||+--------------- Access type limitation (0: code and data, 1: data only) +; ++---------------- ignored + +#set CS2_CONFIG B'0000011000000000 ; <<< select Chip Select Area 2 configuration +; |||||||||||||+++-- Automatic wait cycles (0: 0, 1: 1, 2: 2, 3: 3, 4: 4, 5: 8, 6: 16, 7: 32) +; ||||||||||||+----- Address Cycle Extension (0: not extended, 1: extension by 1 cycle) +; |||||||||||+------ Strobe timing (0: scheme 0, 1: scheme 1) +; ||||||||||+------- Write strobe function (0: WRLX strobe, 1: WRX strobe) +; |||||||||+-------- Endianess (0: little endian, 1: big endian) +; ||||||||+--------- Bus width (0: 16bit, 1: 8bit) +; |||||+++---------- External area size (0: 64kB, 1: 128kB, 2: 256kB, 3: 512kB, 4: 1MB, 5: 2MB, 6: 4MB, 7: 8MB) +; ||||+------------- Chip Select output enable (0: CS disabled, 1: CS enabled) +; |||+-------------- Chip Select level (0: low active, 1: high active) +; ||+--------------- Access type limitation (0: code and data, 1: data only) +; ++---------------- ignored + +#set CS3_CONFIG B'0000011000000000 ; <<< select Chip Select Area 3 configuration +; |||||||||||||+++-- Automatic wait cycles (0: 0, 1: 1, 2: 2, 3: 3, 4: 4, 5: 8, 6: 16, 7: 32) +; ||||||||||||+----- Address Cycle Extension (0: not extended, 1: extension by 1 cycle) +; |||||||||||+------ Strobe timing (0: scheme 0, 1: scheme 1) +; ||||||||||+------- Write strobe function (0: WRLX strobe, 1: WRX strobe) +; |||||||||+-------- Endianess (0: little endian, 1: big endian) +; ||||||||+--------- Bus width (0: 16bit, 1: 8bit) +; |||||+++---------- External area size (0: 64kB, 1: 128kB, 2: 256kB, 3: 512kB, 4: 1MB, 5: 2MB, 6: 4MB, 7: 8MB) +; ||||+------------- Chip Select output enable (0: CS disabled, 1: CS enabled) +; |||+-------------- Chip Select level (0: low active, 1: high active) +; ||+--------------- Access type limitation (0: code and data, 1: data only) +; ++---------------- ignored + +#set CS4_CONFIG B'0000011000000000 ; <<< select Chip Select Area 4 configuration +; |||||||||||||+++-- Automatic wait cycles (0: 0, 1: 1, 2: 2, 3: 3, 4: 4, 5: 8, 6: 16, 7: 32) +; ||||||||||||+----- Address Cycle Extension (0: not extended, 1: extension by 1 cycle) +; |||||||||||+------ Strobe timing (0: scheme 0, 1: scheme 1) +; ||||||||||+------- Write strobe function (0: WRLX strobe, 1: WRX strobe) +; |||||||||+-------- Endianess (0: little endian, 1: big endian) +; ||||||||+--------- Bus width (0: 16bit, 1: 8bit) +; |||||+++---------- External area size (0: 64kB, 1: 128kB, 2: 256kB, 3: 512kB, 4: 1MB, 5: 2MB, 6: 4MB, 7: 8MB) +; ||||+------------- Chip Select output enable (0: CS disabled, 1: CS enabled) +; |||+-------------- Chip Select level (0: low active, 1: high active) +; ||+--------------- Access type limitation (0: code and data, 1: data only) +; ++---------------- ignored + +#set CS5_CONFIG B'0000011000000000 ; <<< select Chip Select Area 5 configuration +; |||||||||||||+++-- Automatic wait cycles (0: 0, 1: 1, 2: 2, 3: 3, 4: 4, 5: 8, 6: 16, 7: 32) +; ||||||||||||+----- Address Cycle Extension (0: not extended, 1: extension by 1 cycle) +; |||||||||||+------ Strobe timing (0: scheme 0, 1: scheme 1) +; ||||||||||+------- Write strobe function (0: WRLX strobe, 1: WRX strobe) +; |||||||||+-------- Endianess (0: little endian, 1: big endian) +; ||||||||+--------- Bus width (0: 16bit, 1: 8bit) +; |||||+++---------- External area size (0: 64kB, 1: 128kB, 2: 256kB, 3: 512kB, 4: 1MB, 5: 2MB, 6: 4MB, 7: 8MB) +; ||||+------------- Chip Select output enable (0: CS disabled, 1: CS enabled) +; |||+-------------- Chip Select level (0: low active, 1: high active) +; ||+--------------- Access type limitation (0: code and data, 1: data only) +; ++---------------- ignored + + +#set CS2_START 0x00 ; select start bank of chip select area; valid values: 0x00..0xFF +#set CS3_START 0x40 ; select start bank of chip select area; valid values: 0x00..0xFF +#set CS4_START 0x80 ; select start bank of chip select area; valid values: 0x00..0xFF +#set CS5_START 0xC0 ; select start bank of chip select area; valid values: 0x00..0xFF + + +;==================================================================== +; 4.11 ROM Mirror configuration +;==================================================================== + +#set MIRROR_8KB 0 +#set MIRROR_16KB 1 +#set MIRROR_24KB 2 +#set MIRROR_32KB 3 + +#set ROMMIRROR ON ; <<< ROM mirror function ON/OFF +#set MIRROR_BANK 0xF ; <<< ROM Mirror bank, allowed entries: 0x0..0xF for the banks 0xF0..0xFF +#set MIRROR_SIZE MIRROR_32KB ; <<< ROM Mirror size + +; One can select which ROM area to mirror into the upper half of bank 00. +; If ROMMIRROR = OFF is selected, the address range 0x008000..0x00FFFF +; shows the contents of the respective area of bank 1: 0x018000..0x01FFFF. +; If ROMMIRROR = ON is selected, the memory bank to mirror can be selected. +; Available banks are 0xF0 to 0xFF. Furthermore, the ROM Mirror area size can +; be selected. 4 sizes are available: 8 kB, 16 kB, 24 kB, or 32 kB. The ROM Mirror +; from the highest address of the selected bank downwards, e.g. if bank 0xFF and +; mirror size 24 kB is selected, the memory range 0xFFA000..0xFFFFFF is mirrored +; to address range 0x00A000..0x00FFFF. The memory area not selected for +; ROM Mirror is still mirrored from bank 0x01. +; This is necessary to get the compiler ROMCONST option working. This is intended +; to increase performance, if a lot of dynamic data have to be accessed. +; In SMALL and MEDIUM model these data can be accessed within bank 0, +; which allows to use near addressing. Please make sure to have the linker +; setting adjusted accordingly! + + +;==================================================================== +; 4.12 Flash Security +;==================================================================== + +#set MAIN_SECURITY_ENABLE OFF ; <<< enable Flash Security for Main Flash +#set SATELLITE_FLASH OFF ; <<< select if Satellite Flash is available +#set SATELLITE_SECURITY_ENABLE OFF ; <<< enable Flash Security for Satellite Flash + +; set the Flash Security unlock key (16 bytes) +; all 0: unlock not possible +#set MAIN_UNLOCK_0 0x00 +#set MAIN_UNLOCK_1 0x00 +#set MAIN_UNLOCK_2 0x00 +#set MAIN_UNLOCK_3 0x00 +#set MAIN_UNLOCK_4 0x00 +#set MAIN_UNLOCK_5 0x00 +#set MAIN_UNLOCK_6 0x00 +#set MAIN_UNLOCK_7 0x00 +#set MAIN_UNLOCK_8 0x00 +#set MAIN_UNLOCK_9 0x00 +#set MAIN_UNLOCK_10 0x00 +#set MAIN_UNLOCK_11 0x00 +#set MAIN_UNLOCK_12 0x00 +#set MAIN_UNLOCK_13 0x00 +#set MAIN_UNLOCK_14 0x00 +#set MAIN_UNLOCK_15 0x00 + +#set SATELLITE_UNLOCK_0 0x00 +#set SATELLITE_UNLOCK_1 0x00 +#set SATELLITE_UNLOCK_2 0x00 +#set SATELLITE_UNLOCK_3 0x00 +#set SATELLITE_UNLOCK_4 0x00 +#set SATELLITE_UNLOCK_5 0x00 +#set SATELLITE_UNLOCK_6 0x00 +#set SATELLITE_UNLOCK_7 0x00 +#set SATELLITE_UNLOCK_8 0x00 +#set SATELLITE_UNLOCK_9 0x00 +#set SATELLITE_UNLOCK_10 0x00 +#set SATELLITE_UNLOCK_11 0x00 +#set SATELLITE_UNLOCK_12 0x00 +#set SATELLITE_UNLOCK_13 0x00 +#set SATELLITE_UNLOCK_14 0x00 +#set SATELLITE_UNLOCK_15 0x00 + + +;==================================================================== +; 4.13 Flash Write Protection +;==================================================================== + +#set MAIN_FLASH_WRITE_PROTECT OFF ; <<< select Flash write protection +#set PROTECT_SECTOR_SA0 OFF ; <<< select individual sector to protect +#set PROTECT_SECTOR_SA1 OFF ; <<< select individual sector to protect +#set PROTECT_SECTOR_SA2 OFF ; <<< select individual sector to protect +#set PROTECT_SECTOR_SA3 OFF ; <<< select individual sector to protect +#set PROTECT_SECTOR_SA32 OFF ; <<< select individual sector to protect +#set PROTECT_SECTOR_SA33 OFF ; <<< select individual sector to protect +#set PROTECT_SECTOR_SA34 OFF ; <<< select individual sector to protect +#set PROTECT_SECTOR_SA35 OFF ; <<< select individual sector to protect +#set PROTECT_SECTOR_SA36 OFF ; <<< select individual sector to protect +#set PROTECT_SECTOR_SA37 OFF ; <<< select individual sector to protect +#set PROTECT_SECTOR_SA38 OFF ; <<< select individual sector to protect +#set PROTECT_SECTOR_SA39 OFF ; <<< select individual sector to protect + +#set SATELLITE_FLASH_WRITE_PROTECT OFF ; <<< select Flash write protection +#set PROTECT_SECTOR_SB0 OFF ; <<< select individual sector to protect +#set PROTECT_SECTOR_SB1 OFF ; <<< select individual sector to protect +#set PROTECT_SECTOR_SB2 OFF ; <<< select individual sector to protect +#set PROTECT_SECTOR_SB3 OFF ; <<< select individual sector to protect + + +;==================================================================== +; 4.14 Boot Vector +;==================================================================== + +#set BOOT_VECTOR_TABLE 1 ; enable boot vector +#set BOOT_VECTOR_FIXED 2 ; enable boot vector + +#set BOOT_VECTOR BOOT_VECTOR_TABLE ; <<< select type of boot vector + +; If boot vector generation is enabled (BOOT_VECTOR_TABLE, BOOT_VECTOR_FIXED), +; appropriate code is generated. If it is disabled (OFF), start-up file does +; not care about. +; +; BOOT_VECTOR_TABLE: - Create table entry at address oxFFFFDC. +; - Any start address can be set and start-up file will +; set address of this start code. +; BOOT_VECTOR_FIXED: - Instead of table entry, a special marker is set in +; ROM Configuration Block, which enables the fixed +; start address 0xDF0080. This is prefered setting +; for user boot loaders. +; OFF: - Do not set table entry and marker. This might be used +; for application to be loaded by boot loader. +; +; Note +; BOOT_VECTOR_TABLE setting can also be used, if all other interrupt vectors +; are specified via "pragma intvect". Only if interrupts 0..7 are specified +; via "pragma intvect", these will conflict with the vector in this module. +; The reason is the INTVECT section, which includes the whole area from the +; lowest to the highest specified vector. + +#if BOOT_VECTOR == BOOT_VECTOR_TABLE + .SECTION RESVECT, CONST, LOCATE=H'FFFFDC + .DATA.E _start + .SECTION BOOT_SELECT, CONST, LOCATE=H'DF0030 + .DATA.L 0xFFFFFFFF + +#else +# if BOOT_VECTOR == BOOT_VECTOR_FIXED + .SECTION BOOT_SELECT, CONST, LOCATE=H'DF0030 + .DATA.L 0x292D3A7B ; Magic Word +# else + .SECTION BOOT_SELECT, CONST, LOCATE=H'DF0030 + .SKIP 4 +# endif +#endif + +;==================================================================== +; 4.15 UART scanning +;==================================================================== + +#set UART_SCANNING OFF ; <<< enable UART scanning in + ; Internal Vector Mode +; +; By default, the MCU scans in Internal Vector Mode for a UART +; communication after reset. This enables to establish a serial +; communication without switching to Serial Communication Mode. +; For the final aplpication, sset this switch to OFF to achieve the +; fastest start-up time. + +#if UART_SCANNING == ON + .SECTION UART_SCAN_SELECT, CONST, LOCATE=H'DF0034 + .DATA.L 0xFFFFFFFF +#else + .SECTION UART_SCAN_SELECT, CONST, LOCATE=H'DF0034 + .DATA.L 0x292D3A7B +#endif + .SKIP 0x08 + + +;==================================================================== +; 4.16 Enable RAMCODE Copying +;==================================================================== + +#set COPY_RAMCODE OFF ; <<< enable RAMCODE section to + ; be copied from ROM to RAM + +; To get this option properly working the code to be executed has to +; be linked to section RAMCODE (e.g. by #pragma section). The section +; RAMCODE has be located in RAM and the section @RAMCODE has to be +; located at a fixed address in ROM by linker settings. + +;==================================================================== +; 4.17 Enable information stamp in ROM +;==================================================================== + +#set VERSION_STAMP OFF ; <<< enable version number in + ; separated section + + +#if VERSION_STAMP == ON + .SECTION VERSIONS, CONST ; change name, if necessary + .SDATA "Start ", VERSION, "\n\0" +#endif + +;==================================================================== +; 4.18 Enable Background Debugging Mode +;==================================================================== + +#set BACKGROUND_DEBUGGING ON ; <<< enable Background Debugging + ; mode + +#if __CONFIG__ == 1 + #set BDM_CONFIGURATION B'0000000000010001 ; <<< set BDM configuration + ; ||||||||++--- BdmUART + ; |||||||| (0: A, 1: B, 2: C, 3: D) + ; ||||||++----- BdmSynchMode + ; |||||| (0: Async., 1: Sync. + ; |||||| 2: BdmKLine, 3: res.) + ; |||||+------- BdmAutoStart + ; ||||+-------- BdmExtBreakpointCfg + ; |||+--------- BdmKeepRClock + ; ||+---------- BdmCaliRClock + ; |+----------- BdmKeepBCD + ; +------------ BdmUserKernel + +#elif __CONFIG__ == 2 + #set BDM_CONFIGURATION B'0000000000010000 ; <<< set BDM configuration + ; ||||||||++--- BdmUART + ; |||||||| (0: A, 1: B, 2: C, 3: D) + ; ||||||++----- BdmSynchMode + ; |||||| (0: Async., 1: Sync. + ; |||||| 2: BdmKLine, 3: res.) + ; |||||+------- BdmAutoStart + ; ||||+-------- BdmExtBreakpointCfg + ; |||+--------- BdmKeepRClock + ; ||+---------- BdmCaliRClock + ; |+----------- BdmKeepBCD + ; +------------ BdmUserKernel + +#elif __CONFIG__ == 3 + #set BDM_CONFIGURATION B'0000000000010001 ; <<< set BDM configuration + ; ||||||||++--- BdmUART + ; |||||||| (0: A, 1: B, 2: C, 3: D) + ; ||||||++----- BdmSynchMode + ; |||||| (0: Async., 1: Sync. + ; |||||| 2: BdmKLine, 3: res.) + ; |||||+------- BdmAutoStart + ; ||||+-------- BdmExtBreakpointCfg + ; |||+--------- BdmKeepRClock + ; ||+---------- BdmCaliRClock + ; |+----------- BdmKeepBCD + ; +------------ BdmUserKernel + +#elif __CONFIG__ == 4 + #set BDM_CONFIGURATION B'0000000000010000 ; <<< set BDM configuration + ; ||||||||++--- BdmUART + ; |||||||| (0: A, 1: B, 2: C, 3: D) + ; ||||||++----- BdmSynchMode + ; |||||| (0: Async., 1: Sync. + ; |||||| 2: BdmKLine, 3: res.) + ; |||||+------- BdmAutoStart + ; ||||+-------- BdmExtBreakpointCfg + ; |||+--------- BdmKeepRClock + ; ||+---------- BdmCaliRClock + ; |+----------- BdmKeepBCD + ; +------------ BdmUserKernel + +#else + #error Either of the __USE_COMTEST__ and __USE_TASKLIST__ should be defined + +#endif + + +#set BDM_BAUDRATE 115200 ; <<< set Baudrate in Bits/s for BDM + +#set BDM_EXT_CONFIG 0xFFFFFF ; <<< set external Config/Kernel + +#set BDM_WD_PATTERN 0x00 ; <<< set watchdog pattern + +#set BDM_PFCS0 0x0000 ; <<< set default breakpoint +#set BDM_PFCS1 0x0000 ; configurations +#set BDM_PFCS2 0x0000 +#set BDM_PFCS3 0x0000 + +#set BDM_PFA0 0xFFFFFF ; <<< set address +#set BDM_PFA1 0xFFFFFF ; configurations +#set BDM_PFA2 0xFFFFFF +#set BDM_PFA3 0xFFFFFF +#set BDM_PFA4 0xFFFFFF +#set BDM_PFA5 0xFFFFFF +#set BDM_PFA6 0xFFFFFF +#set BDM_PFA7 0xFFFFFF + +#set BDM_PFD0 0xFFFFFF ; <<< set patch data +#set BDM_PFD1 0xFFFFFF ; configurations +#set BDM_PFD2 0xFFFFFF +#set BDM_PFD3 0xFFFFFF +#set BDM_PFD4 0xFFFFFF +#set BDM_PFD5 0xFFFFFF +#set BDM_PFD6 0xFFFFFF +#set BDM_PFD7 0xFFFFFF + + +; <<< END OF SETTINGS >>> + +;==================================================================== +; 5 Section and Data Declaration +;==================================================================== + +;==================================================================== +; 5.1 Several fixed addresses (fixed for MB963xx controllers) +;==================================================================== + +MFMCS .EQU 0x03F1 ; Main Flash Memory configuration register +MFMTC .EQU 0x03F2 ; Main Flash Memory timing register +SFMCS .EQU 0x03F5 ; Satellite Flash Memory configuration register +SFMTC .EQU 0x03F6 ; Satellite Flash Memory timing register +ROMM .EQU 0x03AE ; ROM mirror control register +CKSR .EQU 0x0401 ; Clock select control register +CKSSR .EQU 0x0402 ; Clock stabilization select register +CKMR .EQU 0x0403 ; Clock monitor register +CKFCR .EQU 0x0404 ; Clock frequency control register +PLLCR .EQU 0x0406 ; PLL control register +VRCR .EQU 0x042C ; Voltage Regulator Control register +#if BUSMODE != SINGLE_CHIP ; only for devices with external bus +PIER00 .EQU 0x0444 +PIER01 .EQU 0x0445 +PIER02 .EQU 0x0446 +PIER03 .EQU 0x0447 +PIER12 .EQU 0x0450 +EACL0 .EQU 0x06E0 +EACH0 .EQU 0x06E1 +EACL1 .EQU 0x06E2 +EACH1 .EQU 0x06E3 +EACL2 .EQU 0x06E4 +EACH2 .EQU 0x06E5 +EACL3 .EQU 0x06E6 +EACH3 .EQU 0x06E7 +EACL4 .EQU 0x06E8 +EACH4 .EQU 0x06E9 +EACL5 .EQU 0x06EA +EACH5 .EQU 0x06EB +EAS2 .EQU 0x06EC +EAS3 .EQU 0x06ED +EAS4 .EQU 0x06EE +EAS5 .EQU 0x06EF +EBM .EQU 0x06F0 +EBCF .EQU 0x06F1 +EBAE0 .EQU 0x06F2 +EBAE1 .EQU 0x06F3 +EBAE2 .EQU 0x06F4 +EBCS .EQU 0x06F5 +#endif ; BUSMODE != SINGLE_CHIP + +;==================================================================== +; 5.2 Declaration of __near addressed data sections +;==================================================================== + +; sections to be cleared + .SECTION DATA, DATA, ALIGN=2 ; zero clear area + .SECTION DATA2, DATA, ALIGN=2 ; zero clear area + .SECTION DIRDATA, DIR, ALIGN=2 ; zero clear direct + .SECTION LIBDATA, DATA, ALIGN=2 ; zero clear lib area + +; sections to be initialised with start-up values + .SECTION INIT, DATA, ALIGN=2 ; initialised area + .SECTION INIT2, DATA, ALIGN=2 ; initialised area + .SECTION DIRINIT, DIR, ALIGN=2 ; initialised dir + .SECTION LIBINIT, DATA, ALIGN=2 ; initialised lib area +#if CONSTDATA == RAMCONST + .SECTION CINIT, DATA, ALIGN=2 ; initialised const + .SECTION CINIT2, DATA, ALIGN=2 ; initialised const +#endif + +; sections containing start-up values for initialised sections above + .SECTION DCONST, CONST, ALIGN=2 ; DINIT initialisers + .SECTION DIRCONST, DIRCONST,ALIGN=2 ; DIRINIT initialisers + .SECTION LIBDCONST, CONST, ALIGN=2 ; LIBDCONST init val + + ; following section is either copied to CINIT (RAMCONST) or + ; mapped by ROM-mirror function (ROMCONST) + .SECTION CONST, CONST, ALIGN=2 ; CINIT initialisers + .SECTION CONST2, CONST, ALIGN=2 ; CINIT initialisers + +;==================================================================== +; 5.3 Declaration of RAMCODE section and labels +;==================================================================== + +#if COPY_RAMCODE == ON + .SECTION RAMCODE, CODE, ALIGN=1 + .IMPORT _RAM_RAMCODE ; provided by linker + .IMPORT _ROM_RAMCODE ; provided by linker +#endif + + +;==================================================================== +; 5.4 Declaration of sections containing other sections description +;==================================================================== + +; DCLEAR contains start address and size of all sections to be cleared +; DTRANS contains source and destination address and size of all +; sections to be initialised with start-up values +; The compiler automatically adds a descriptor for each __far addressed +; data section to DCLEAR or DTRANS. These __far sections are separated +; for each C-module. + +; In addition the start-up file adds the descriptors of the previously +; declared __near section here. This way the same code in the start-up +; file can be used for initialising all sections. + + .SECTION DCLEAR, CONST, ALIGN=2 ; zero clear table + ; Address Bank Size + .DATA.H DATA, BNKSEC DATA, SIZEOF(DATA ) + .DATA.H DIRDATA, BNKSEC DIRDATA, SIZEOF(DIRDATA) + .DATA.H LIBDATA, BNKSEC LIBDATA, SIZEOF(LIBDATA) + + .SECTION DTRANS, CONST, ALIGN=2 ; copy table + ; Address Bank Address Bank Size + .DATA.H DCONST, BNKSEC DCONST, INIT, BNKSEC INIT, SIZEOF INIT + .DATA.H DIRCONST, BNKSEC DIRCONST, DIRINIT,BNKSEC DIRINIT,SIZEOF DIRINIT + .DATA.H LIBDCONST,BNKSEC LIBDCONST,LIBINIT,BNKSEC LIBINIT,SIZEOF LIBINIT + +#if CONSTDATA == RAMCONST + .DATA.H CONST, BNKSEC CONST, CINIT, BNKSEC CINIT, SIZEOF CINIT + .DATA.H CONST2, BNKSEC CONST, CINIT2, BNKSEC CINIT2, SIZEOF CINIT2 +#endif + +#if COPY_RAMCODE == ON + .DATA.L _ROM_RAMCODE, _RAM_RAMCODE + .DATA.H SIZEOF RAMCODE +#endif + +;==================================================================== +; 5.5 Stack area and stack top definition/declaration +;==================================================================== +#if STACK_RESERVE == ON + .SECTION SSTACK, STACK, ALIGN=2 + + .EXPORT __systemstack, __systemstack_top +__systemstack: + .RES.B (STACK_SYS_SIZE + 1) & 0xFFFE +__systemstack_top: +SSTACK_TOP: + + .SECTION USTACK, STACK, ALIGN=2 + + .EXPORT __userstack, __userstack_top +__userstack: + .RES.B (STACK_USR_SIZE + 1) & 0xFFFE +__userstack_top: +USTACK_TOP: + +#else + .SECTION SSTACK, STACK, ALIGN=2 + .SECTION USTACK, STACK, ALIGN=2 + + .IMPORT __systemstack, __systemstack_top + .IMPORT __userstack, __userstack_top +#endif + +;==================================================================== +; 5.6 Direct page register dummy label definition +;==================================================================== + + .SECTION DIRDATA ; zero clear direct +DIRDATA_S: ; label for DPR init + +; This label is used to get the page of the __direct data. +; Depending on the linkage order of this startup file the label is +; placed anywhere within the __direct data page. However, the +; statement "PAGE (DIRDATA_S)" is processed. Therefore, the lower +; 8 Bit of the address of DIRDATA_S are not relevant and this feature +; becomes linkage order independent. +; Note, the linker settings have to make sure that all __direct +; data are located within the same physical page (256 Byte block). + +;==================================================================== +; 6 Start-Up Code +;==================================================================== + +;==================================================================== +; 6.1 Import external symbols +;==================================================================== + + .IMPORT _main ; user code entrance +#if CLIBINIT == ON + .IMPORT __stream_init + .IMPORT _exit + .EXPORT __exit +#endif + .EXPORT _start + +;==================================================================== +; ___ _____ __ ___ _____ +; / | / \ | \ | +; \___ | | | |___/ | +; \ | |----| | \ | +; ___/ | | | | \ | Begin of actual code section +;==================================================================== + .SECTION CODE_START, CODE, ALIGN=1 + +;==================================================================== +; 6.2 Program start (the reset vector should point here) +;==================================================================== +_start: + NOP ; This NOP is only for debugging. On debugger the IP + ; (instruction pointer) should point here after reset + +;==================================================================== +; 6.3 "NOT RESET YET" WARNING +;==================================================================== +notresetyet: + NOP ; read hint below!!!!!!! +; If the debugger stays at this NOP after download, the controller has +; not been reset yet. In order to reset all hardware registers it is +; highly recommended to reset the controller. +; However, if no reset vector has been defined on purpose, this start +; address can also be used. +; This mechanism is using the .END instruction at the end of this mo- +; dule. It is not necessary for controller operation but improves +; security during debugging (mainly emulator debugger). +; If the debugger stays here after a single step from label "_start" +; to label "notresetyet", this note can be ignored. + +;==================================================================== +; 6.4 Initialisation of processor status +;==================================================================== + AND CCR, #0x80 ; disable interrupts + MOV ILM,#7 ; set interrupt level mask to ALL + MOV RP,#REGBANK ; set register bank pointer + +;==================================================================== +; 6.5 Set clock ratio (ignore subclock) +;==================================================================== + MOVN A, #0 ; set bank 0 in DTB for the case that + MOV DTB, A ; start-up code was not jumped by reset + + MOV CKSSR, #(0xF8 | MC_STAB_TIME) ; set clock stabilization time + +#if (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_4MHZ_MAIN_CLKP2_4MHZ) + MOV CKSR, #0xB5 +#endif ; (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_4MHZ_MAIN_CLKP2_4MHZ) + +#if (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_4MHZ_MAIN_CLKP2_4MHZ) + CLRB MFMCS:4 + CLRB MFMCS:5 + CLRB SFMCS:4 + CLRB SFMCS:5 + MOVW CKFCR, #0x1111 + MOV CKSR, #0xB5 +#endif ; (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_4MHZ_MAIN_CLKP2_4MHZ) + +#if (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_4MHZ_PLL_CLKP2_4MHZ) +# if ((SERIES == MB96340) && (DEVICE < 3)) + MOVW PLLCR, #0x00E0 + MOV CKSR, #0xFA +# else + MOVW PLLCR, #0x00A1 + MOVW CKFCR, #0x1111 + MOVW MFMTC, #0x2128 +# if SATELLITE_FLASH == ON + MOVW SFMTC, #0x2128 +# endif ; SATELLITE_FLASH == ON + MOV CKSR, #0xFA +# endif ; ((SERIES == MB96340) && (DEVICE < 3)) +#endif ; (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_4MHZ_PLL_CLKP2_4MHZ) + +#if (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_4MHZ_PLL_CLKP2_4MHZ) +# if ((SERIES == MB96340) && (DEVICE < 3)) + MOVW PLLCR, #0x0060 + CLRB MFMCS:4 + CLRB MFMCS:5 + CLRB SFMCS:4 + CLRB SFMCS:5 + MOVW CKFCR, #0x1111 + MOV CKSR, #0xFA +# else + MOVW PLLCR, #0x0060 + MOVW CKFCR, #0x1111 + MOVW MFMTC, #0x2128 +# if SATELLITE_FLASH == ON + MOVW SFMTC, #0x2128 +# endif ; SATELLITE_FLASH == ON + MOV CKSR, #0xFA +# endif ; ((SERIES == MB96340) && (DEVICE < 3)) +#endif ; (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_4MHZ_PLL_CLKP2_4MHZ) + +#if (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_8MHZ_CLKP2_8MHZ) +# if ((SERIES == MB96340) && (DEVICE < 3)) + MOVW PLLCR, #0x00A1 + MOV CKSR, #0xFA +# else + MOVW PLLCR, #0x0043 + MOVW CKFCR, #0x1111 + MOVW MFMTC, #0x2128 +# if SATELLITE_FLASH == ON + MOVW SFMTC, #0x2128 +# endif ; SATELLITE_FLASH == ON + MOV CKSR, #0xFA +# endif ; ((SERIES == MB96340) && (DEVICE < 3)) +#endif ; (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_8MHZ_CLKP2_8MHZ) + +#if (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_8MHZ_CLKP2_8MHZ) +# if ((SERIES == MB96340) && (DEVICE < 3)) + MOVW PLLCR, #0x0060 + MOV CKSR, #0xFA +# else + MOVW PLLCR, #0x0081 + MOVW CKFCR, #0x1111 + MOVW MFMTC, #0x2128 +# if SATELLITE_FLASH == ON + MOVW SFMTC, #0x2128 +# endif ; SATELLITE_FLASH == ON + MOV CKSR, #0xFA +# endif ; ((SERIES == MB96340) && (DEVICE < 3)) +#endif ; (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_8MHZ_CLKP2_8MHZ) + +#if (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_12MHZ_CLKP2_12MHZ) +# if ((SERIES == MB96340) && (DEVICE < 3)) + MOVW PLLCR, #0x0062 + MOV CKSR, #0xFA +# else + MOVW PLLCR, #0x0025 + MOVW CKFCR, #0x1111 + MOVW MFMTC, #0x2128 +# if SATELLITE_FLASH == ON + MOVW SFMTC, #0x2128 +# endif ; SATELLITE_FLASH == ON + MOV CKSR, #0xFA +# endif ; ((SERIES == MB96340) && (DEVICE < 3)) +#endif ; (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_12MHZ_CLKP2_12MHZ) + +#if (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_12MHZ_CLKP2_12MHZ) +# if ((SERIES == MB96340) && (DEVICE < 3)) + MOVW PLLCR, #0x0082 + CLRB MFMCS:4 + CLRB MFMCS:5 + CLRB SFMCS:4 + CLRB SFMCS:5 + MOVW CKFCR, #0x1111 + MOV CKSR, #0xFA +# else + MOVW PLLCR, #0x0082 + MOVW CKFCR, #0x1111 + MOVW MFMTC, #0x2128 +# if SATELLITE_FLASH == ON + MOVW SFMTC, #0x2128 +# endif ; SATELLITE_FLASH == ON + MOV CKSR, #0xFA +# endif ; ((SERIES == MB96340) && (DEVICE < 3)) +#endif ; (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_12MHZ_CLKP2_12MHZ) + +#if (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_16MHZ_CLKP2_16MHZ) +# if ((SERIES == MB96340) && (DEVICE < 3)) + MOVW PLLCR, #0x0043 + MOV CKSR, #0xFA +# else + MOVW PLLCR, #0x0027 + MOVW CKFCR, #0x1111 + MOVW MFMTC, #0x2279 +# if SATELLITE_FLASH == ON + MOVW SFMTC, #0x2279 +# endif ; SATELLITE_FLASH == ON + MOV CKSR, #0xFA +# endif ; ((SERIES == MB96340) && (DEVICE < 3)) +#endif ; (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_16MHZ_CLKP2_16MHZ) + +#if (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_16MHZ_CLKP2_16MHZ) +# if ((SERIES == MB96340) && (DEVICE < 3)) + MOVW PLLCR, #0x0081 + MOV CKSR, #0xFA +# else + MOVW PLLCR, #0x0003 + MOVW CKFCR, #0x1111 + MOVW MFMTC, #0x2279 +# if SATELLITE_FLASH == ON + MOVW SFMTC, #0x2279 +# endif ; SATELLITE_FLASH == ON + MOV CKSR, #0xFA +# endif ; ((SERIES == MB96340) && (DEVICE < 3)) +#endif ; (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_16MHZ_CLKP2_16MHZ) + +#if (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_24MHZ_CLKP2_12MHZ) +# if ((SERIES == MB96340) && (DEVICE < 3)) + MOVW PLLCR, #0x0025 + MOVW CKFCR, #0x1001 + MOV CKSR, #0xFA +# else + MOVW PLLCR, #0x000B + MOVW CKFCR, #0x3111 + MOVW MFMTC, #0x4C09 +# if SATELLITE_FLASH == ON + MOVW SFMTC, #0x4C09 +# endif ; SATELLITE_FLASH == ON + MOV CKSR, #0xFA +# endif ; ((SERIES == MB96340) && (DEVICE < 3)) +#endif ; (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_24MHZ_CLKP2_12MHZ) + +#if (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_24MHZ_CLKP2_12MHZ) +# if ((SERIES == MB96340) && (DEVICE < 3)) + MOVW PLLCR, #0x0082 + MOVW CKFCR, #0x1001 + MOV CKSR, #0xFA +# else + MOVW PLLCR, #0x0005 + MOVW CKFCR, #0x3111 + MOVW MFMTC, #0x4C09 +# if SATELLITE_FLASH == ON + MOVW SFMTC, #0x4C09 +# endif ; SATELLITE_FLASH == ON + MOV CKSR, #0xFA +# endif ; ((SERIES == MB96340) && (DEVICE < 3)) +#endif ; (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_24MHZ_CLKP2_12MHZ) + +#if (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_32MHZ_CLKP2_16MHZ) +# if ((SERIES == MB96340) && (DEVICE < 3)) +# error Setting prohibited due to 16FXFL0014 +# else + MOVW PLLCR, #0x000F + MOVW CKFCR, #0x3111 + MOVW MFMTC, #0x4C09 +# if SATELLITE_FLASH == ON + MOVW SFMTC, #0x4C09 +# endif ; SATELLITE_FLASH == ON + MOV CKSR, #0xFA +# endif ; ((SERIES == MB96340) && (DEVICE < 3)) +#endif ; (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_32MHZ_CLKP2_16MHZ) + +#if (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_32MHZ_CLKP2_16MHZ) +# if ((SERIES == MB96340) && (DEVICE < 3)) +# error Setting prohibited due to 16FXFL0014 +# else + MOVW PLLCR, #0x0007 + MOVW CKFCR, #0x3111 + MOVW MFMTC, #0x4C09 +# if SATELLITE_FLASH == ON + MOVW SFMTC, #0x4C09 +# endif ; SATELLITE_FLASH == ON + MOV CKSR, #0xFA +# endif ; ((SERIES == MB96340) && (DEVICE < 3)) +#endif ; (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_32MHZ_CLKP2_16MHZ) + +#if (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_32MHZ_CLKP1_16MHZ_CLKP2_16MHZ) +# if ((SERIES == MB96340) && (DEVICE < 3)) +# error Setting prohibited due to 16FXFL0014 +# else + MOVW PLLCR, #0x000F + MOVW CKFCR, #0x3311 + MOVW MFMTC, #0x4C09 +# if SATELLITE_FLASH == ON + MOVW SFMTC, #0x4C09 +# endif ; SATELLITE_FLASH == ON + MOV CKSR, #0xFA +# endif ; ((SERIES == MB96340) && (DEVICE < 3)) +#endif ; (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_32MHZ_CLKP1_16MHZ_CLKP2_16MHZ) + +#if (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_32MHZ_CLKP1_16MHZ_CLKP2_16MHZ) +# if ((SERIES == MB96340) && (DEVICE < 3)) +# error Setting prohibited due to 16FXFL0014 +# else + MOVW PLLCR, #0x0007 + MOVW CKFCR, #0x3311 + MOVW MFMTC, #0x4C09 +# if SATELLITE_FLASH == ON + MOVW SFMTC, #0x4C09 +# endif ; SATELLITE_FLASH == ON + MOV CKSR, #0xFA +# endif ; ((SERIES == MB96340) && (DEVICE < 3)) +#endif ; (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_32MHZ_CLKP1_16MHZ_CLKP2_16MHZ) + +#if (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_48MHZ_CLKP2_16MHZ) + MOVW PLLCR, #0x000B + MOVW CKFCR, #0x2001 + MOVW MFMTC, #0x223A +# if SATELLITE_FLASH == ON + MOVW SFMTC, #0x223A +# endif ; SATELLITE_FLASH == ON + MOV CKSR, #0xFA +#endif ; (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_48MHZ_CLKP2_16MHZ) + +#if (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_48MHZ_CLKP2_16MHZ) + MOVW PLLCR, #0x0005 + MOVW CKFCR, #0x2001 + MOVW MFMTC, #0x223A +# if SATELLITE_FLASH == ON + MOVW SFMTC, #0x223A +# endif ; SATELLITE_FLASH == ON + MOV CKSR, #0xFA +#endif ; (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_48MHZ_CLKP2_16MHZ) + +#if (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_56MHZ_CLKP2_14MHZ) + MOVW PLLCR, #0x000D + MOVW CKFCR, #0x3001 + MOVW MFMTC, #0x4B3B +# if SATELLITE_FLASH == ON + MOVW SFMTC, #0x4B3B +# endif ; SATELLITE_FLASH == ON + MOV CKSR, #0xFA +#endif ; (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_56MHZ_CLKP2_14MHZ) + +#if (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_56MHZ_CLKP2_14MHZ) + MOVW PLLCR, #0x0006 + MOVW CKFCR, #0x3001 + MOVW MFMTC, #0x4B3B + MOV MFMCS, #0x70 +# if SATELLITE_FLASH == ON + MOVW SFMTC, #0x4B3B + MOV SFMCS, #0x70 +# endif ; SATELLITE_FLASH == ON + MOV VRCR, #0xF6 + MOV CKSR, #0xFA +#endif ; (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_56MHZ_CLKP2_14MHZ) + + +;==================================================================== +; 6.6 Set external bus configuaration +;==================================================================== + +#if BUSMODE != SINGLE_CHIP ; ext bus used + MOV EBCF, #((HOLD_REQ << 7) | (EXT_READY << 6) | (EXT_CLOCK_ENABLE << 5) | (EXT_CLOCK_INVERT << 4) | (EXT_CLOCK_SUSPEND << 3) | EXT_CLOCK_DIVISION) + MOV EBAE0,#ADDR_PINS_7_0 + MOV EBAE1,#ADDR_PINS_15_8 + MOV EBAE2,#ADDR_PINS_23_16 + MOV EBCS, #((ADDRESS_STROBE_LVL << 6) | (ADDRESS_STROBE << 5) | (READ_STROBE << 4) | (HIGH_WRITE_STROBE << 3) | (LOW_WRITE_STROBE << 2) | (HIGH_BYTE_SIGNAL << 1) | LOW_BYTE_SIGNAL) + MOVW EACL0,#CS0_CONFIG + MOVW EACL1,#CS1_CONFIG + MOVW EACL2,#CS2_CONFIG + MOVW EACL3,#CS3_CONFIG + MOVW EACL4,#CS4_CONFIG + MOVW EACL5,#CS5_CONFIG + MOV EAS2, #CS2_START + MOV EAS3, #CS3_START + MOV EAS4, #CS4_START + MOV EAS5, #CS5_START + MOV EBM, #((ADDRESSMODE << 7) | ((BUSMODE-1) << 6) | (CHIP_SELECT5 << 5) | (CHIP_SELECT4 << 4) | (CHIP_SELECT3 << 3) | (CHIP_SELECT2 << 2) | (CHIP_SELECT1 << 1) | CHIP_SELECT0) ; set address mode, ROM access + +# if SERIES == MB96320 || SERIES == MB96340 || SERIES == MB96350 + MOV PIER00,#0xFF +# if (CS0_CONFIG & 0x0080) == 0 || (CS1_CONFIG & 0x0080) == 0 || (CS2_CONFIG & 0x0080) == 0 || (CS3_CONFIG & 0x0080) == 0 || (CS4_CONFIG & 0x0080) == 0 || (CS5_CONFIG & 0x0080) == 0 + MOV PIER01,#0xFF +# endif +# if HOLD_REQ == ON + SETB PIER03:4 +# endif +# if EXT_READY == ON + SETB PIER03:6 +# endif +# else if SERIES == MB96380 + MOV PIER01,#0xFF +# if (CS0_CONFIG & 0x0080) == 0 || (CS1_CONFIG & 0x0080) == 0 || (CS2_CONFIG & 0x0080) == 0 || (CS3_CONFIG & 0x0080) == 0 || (CS4_CONFIG & 0x0080) == 0 || (CS5_CONFIG & 0x0080) == 0 + MOV PIER02,#0xFF +# endif +# if HOLD_REQ == ON + SETB PIER12:7 +# endif +# if EXT_READY == ON + SETB PIER00:2 +# endif +# endif + +#endif + +#if BUSMODE == INTROM_EXTBUS ; EXTBUS and INTROM/EXTROM +# if ROMMIRROR == OFF && CONSTDATA == ROMCONST +# error Mirror function must be ON to mirror internal ROM +# endif +#endif + +ROMM_CONFIG .EQU ((MIRROR_BANK << 4) | (MIRROR_SIZE << 1) | (ROMMIRROR)) + MOV ROMM, #ROMM_CONFIG + + +;==================================================================== +; 6.7 Prepare stacks and set the default stack type +;==================================================================== + + AND CCR,#H'DF ; clear system stack flag + MOVL A, #(__userstack_top) & ~1 + MOVW SP,A ; load offset of stack top to pointer + SWAPW ; swap higher word to AL + MOV USB, A ; set bank + +#if STACK_FILL == ON ; preset the stack + MOV ADB, A + MOVW A, #USTACK ; load start stack address to AL + MOVW A, #STACK_PATTERN ; AL -> AH, pattern in AL + MOVW RW0, #SIZEOF(USTACK) / 2 ; get byte count + FILSWI ADB ; write pattern to stack +#endif + + OR CCR,#H'20 ; set System stack flag + MOVL A, #(__systemstack_top) & ~1 + MOVW SP,A ; load offset of stack top to pointer + SWAPW ; swap higher word to AL + MOV SSB, A ; set bank + +#if STACK_FILL == ON ; preset the stack + MOV ADB, A + MOVW A, #SSTACK ; load start stack address to AL + MOVW A, #STACK_PATTERN ; AL -> AH, pattern in AL + MOVW RW0, #SIZEOF(SSTACK) / 2; get byte count + FILSWI ADB ; write pattern to stack +#endif + +#if STACKUSE == USRSTACK + AND CCR,#H'DF ; clear system stack flag +#endif + + +; The following macro is needed because of the AUTOMODEL option. If the +; model is not known while assembling the module, one has to expect +; completion of streaminit() by RET or RETP. Because RET removes 2 bytes +; from stack and RETP removes 4 bytes from stack, SP is reloaded. + +# macro RELOAD_SP + +#if STACKUSE == USRSTACK + MOVW A, #(__userstack_top) & ~1 +#else + MOVW A, #(__systemstack_top) & ~1 +#endif + MOVW SP,A +# endm + + +;==================================================================== +; 6.8 Copy initial values to data areas. +;==================================================================== +; +; Each C-module has its own __far INIT section. The names are generic. +; DCONST_module contains the initialisers for the far data of the one +; module. INIT_module reserves the RAM area, which has to be loaded +; with the data from DCONST_module. ("module" is the name of the *.c +; file) +; All separated DCONST_module/INIT_module areas are described in +; DTRANS section by start addresses and length of each far section. +; 0000 1. source address (ROM) +; 0004 1. destination address (RAM) +; 0008 length of sections 1 +; 000A 2. source address (ROM) +; 000E 2. destination address (RAM) +; 0012 length of sections 2 +; 0014 3. source address ... +; In addition the start-up file adds the descriptors of the __near +; sections to this table. The order of the descriptors in this table +; depends on the linkage order. +;==================================================================== + MOV A, #BNKSEC DTRANS ; get bank of table + MOV DTB, A ; store bank in DTB + MOVW RW1, #DTRANS ; get start offset of table + OR CCR, #H'20 ; System stack flag set (SSB used) + BRA LABEL2 ; branch to loop condition +LABEL1: + MOVW A, @RW1+6 ; get bank of destination + MOV SSB, A ; save dest bank in SSB + MOVW A, @RW1+2 ; get source bank + MOV ADB, A ; save source bank in ADB + MOVW A, @RW1+4 ; move destination addr in AL + MOVW A, @RW1 ; AL -> AH, src addr -> AL + MOVW RW0, @RW1+8 ; number of bytes to copy -> RW0 + MOVSI SPB, ADB ; copy data + MOVN A, #10 ; length of one table entry is 10 + ADDW RW1, A ; set pointer to next table entry +LABEL2: + MOVW A, RW1 ; get address of next block + SUBW A, #DTRANS ; sub address of first block + CMPW A, #SIZEOF (DTRANS) ; all blocks processed ? + BNE LABEL1 ; if not, branch + + +;==================================================================== +; 6.9 Clear uninitialised data areas to zero +;==================================================================== +; +; Each C-module has its own __far DATA section. The names are generic. +; DATA_module contains the reserved area (RAM) to be cleared. +; ("module" is the name of the *.c file) +; All separated DATA_module areas are described in DCLEAR section by +; start addresses and length of all far section. +; 0000 1. section address (RAM) +; 0004 length of section 1 +; 0006 2. section address (RAM) +; 000A length of section 2 +; 000C 3. section address (RAM) +; 0010 length of section 3 ... +; In addition the start-up file adds the descriptors of the __near +; sections to this table. The order of the descriptors in this table +; depends on the linkage order. +;==================================================================== + MOV A, #BNKSEC DCLEAR ; get bank of table + MOV DTB, A ; store bank in DTB + MOVW RW1, #DCLEAR ; get start offset of table + BRA LABEL4 ; branch to loop condition +LABEL3: + MOV A, @RW1+2 ; get section bank + MOV ADB, A ; save section bank in ADB + MOVW RW0, @RW1+4 ; number of bytes to copy -> RW0 + MOVW A, @RW1 ; move section addr in AL + MOVN A, #0 ; AL -> AH, init value -> AL + FILSI ADB ; write 0 to section + MOVN A, #6 ; length of one table entry is 6 + ADDW RW1, A ; set pointer to next table entry +LABEL4: + MOVW A, RW1 ; get address of next block + SUBW A, #DCLEAR ; sub address of first block + CMPW A, #SIZEOF (DCLEAR) ; all blocks processed ? + BNE LABEL3 ; if not, branch + + + +;==================================================================== +; 6.10 Set Data Bank Register (DTB) and Direct Page Register (DPR) +;==================================================================== + MOV A,#BNKSEC DATA ; User data bank offset + MOV DTB,A + + MOV A,#PAGE DIRDATA_S ; User direct page + MOV DPR,A + +;==================================================================== +; 6.11 Wait for clocks to stabilise +;==================================================================== + +#if (CLOCK_SPEED == CPU_4MHZ_MAIN_CLKP2_4MHZ) && (CLOCKWAIT == ON) +no_MC_yet: + BBC CKMR:5,no_MC_yet ; check MCM and wait for + ; Main Clock to stabilize +#endif ; wait for Main Clock + +#if (((CRYSTAL == FREQ_4MHZ) ||(CRYSTAL == FREQ_8MHZ)) && \ + ((CLOCK_SPEED == CPU_12MHZ_CLKP2_12MHZ) || \ + (CLOCK_SPEED == CPU_16MHZ_CLKP2_16MHZ) || \ + (CLOCK_SPEED == CPU_24MHZ_CLKP2_12MHZ))) +no_PLL_0WS: + BBC CKMR:6, no_PLL_0WS + +# if ! ((SERIES == MB96340) && (DEVICE < 3)) + MOVW MFMTC, #0x2208 +# if SATELLITE_FLASH == ON + MOVW SFMTC, #0x2208 +# endif ; SATELLITE_FLASH == ON +# endif ; ! ((SERIES == MB96340) && (DEVICE < 3)) +#endif + +#if ((CRYSTAL == FREQ_4MHZ) || (CRYSTAL == FREQ_8MHZ)) && \ + ((CLOCK_SPEED == CPU_32MHZ_CLKP2_16MHZ) || \ + (CLOCK_SPEED == CPU_32MHZ_CLKP1_16MHZ_CLKP2_16MHZ)) && \ + ! ((SERIES == MB96340) && (DEVICE < 3)) +no_PLL_1WS: + BBC CKMR:6, no_PLL_1WS + + MOVW MFMTC, #0x6B09 +# if SATELLITE_FLASH == ON + MOVW SFMTC, #0x6B09 +# endif ; SATELLITE_FLASH == ON +#endif + +#if (CLOCKWAIT == ON) && \ + ((CLOCK_SPEED == CPU_4MHZ_PLL_CLKP2_4MHZ) || \ + (CLOCK_SPEED == CPU_8MHZ_CLKP2_8MHZ) || \ + (CLOCK_SPEED == CPU_48MHZ_CLKP2_16MHZ) || \ + (CLOCK_SPEED == CPU_56MHZ_CLKP2_14MHZ)) +no_PLL_yet: + BBC CKMR:6,no_PLL_yet ; check PCM and wait for + ; PLL to stabilize +#endif ; wait for PLL + +;==================================================================== +; 6.12 Initialise Low-Level Library Interface +;==================================================================== +; +; Call lib init function and reload stack afterwards, if AUTOMODEL +;==================================================================== +#if CLIBINIT == ON +# if MEMMODEL == SMALL || MEMMODEL == COMPACT + CALL __stream_init ; initialise library IO +# else ; MEDIUM, LARGE, AUTOMODEL + CALLP __stream_init ; initialise library IO +# if MEMMODEL == AUTOMODEL + RELOAD_SP ; reload stack since stream_init was + ; possibly left by RET (not RETP) +# endif ; AUTOMODEL +# endif ; MEDIUM, LARGE, AUTOMODEL +#endif ; LIBINI + +;==================================================================== +; 6.13 Call C-language main function +;==================================================================== +#if MEMMODEL == SMALL || MEMMODEL == COMPACT + CALL _main ; Start main function +#else ; MEDIUM, LARGE, AUTOMODEL + CALLP _main ; Start main function + ; ignore remaining word on stack, + ; if main was completed by RET +#endif +;==================================================================== +; 6.14 Shut down library +;==================================================================== +#if CLIBINIT == ON +# if MEMMODEL == SMALL || MEMMODEL == COMPACT + CALL _exit +# else ; MEDIUM, LARGE, AUTOMODEL + CALLP _exit ; ignore remaining word on stack, + ; if main was completed by RET +# endif +__exit: +#endif + +;==================================================================== +; 6.15 Program end loop +;==================================================================== + +end: BRA end ; Loop + + +;==================================================================== +; 6.16 Set Flash Security +;==================================================================== + + .SECTION MAIN_SECURITY, CONST, LOCATE=H'DF0000 +#if MAIN_SECURITY_ENABLE == 0 + .DATA.W 0xFFFF ; Security DISABLED + .SKIP 16 +#else MAIN_SECURITY_ENABLE == 1 + .DATA.W 0x0099 ; Security ENABLED + .DATA.W ((MAIN_UNLOCK_1 << 8) | MAIN_UNLOCK_0) + .DATA.W ((MAIN_UNLOCK_3 << 8) | MAIN_UNLOCK_2) + .DATA.W ((MAIN_UNLOCK_5 << 8) | MAIN_UNLOCK_4) + .DATA.W ((MAIN_UNLOCK_7 << 8) | MAIN_UNLOCK_6) + .DATA.W ((MAIN_UNLOCK_9 << 8) | MAIN_UNLOCK_8) + .DATA.W ((MAIN_UNLOCK_11 << 8) | MAIN_UNLOCK_10) + .DATA.W ((MAIN_UNLOCK_13 << 8) | MAIN_UNLOCK_12) + .DATA.W ((MAIN_UNLOCK_15 << 8) | MAIN_UNLOCK_14) +#endif + .SKIP 4 + .SKIP 6 + +#if SATELLITE_FLASH == ON + .SECTION SATELLITE_SECURITY, CONST, LOCATE=H'DE0000 +# if SATELLITE_SECURITY_ENABLE == 0 + .DATA.W 0xFFFF ; Security DISABLED + .SKIP 16 +# else SATELLITE_SECURITY_ENABLE == 1 + .DATA.W 0x0099 ; Security ENABLED + .DATA.W ((SATELLITE_UNLOCK_1 << 8) | SATELLITE_UNLOCK_0) + .DATA.W ((SATELLITE_UNLOCK_3 << 8) | SATELLITE_UNLOCK_2) + .DATA.W ((SATELLITE_UNLOCK_5 << 8) | SATELLITE_UNLOCK_4) + .DATA.W ((SATELLITE_UNLOCK_7 << 8) | SATELLITE_UNLOCK_6) + .DATA.W ((SATELLITE_UNLOCK_9 << 8) | SATELLITE_UNLOCK_8) + .DATA.W ((SATELLITE_UNLOCK_11 << 8) | SATELLITE_UNLOCK_10) + .DATA.W ((SATELLITE_UNLOCK_13 << 8) | SATELLITE_UNLOCK_12) + .DATA.W ((SATELLITE_UNLOCK_15 << 8) | SATELLITE_UNLOCK_14) +# endif + .SKIP 4 + .SKIP 6 +#endif ; SATELLITE_FLASH == ON + + +;==================================================================== +; 6.17 Set Flash write protection +;==================================================================== + + .SECTION MAIN_PROTECT, CONST, LOCATE=H'DF001C +#if MAIN_FLASH_WRITE_PROTECT == ON + .DATA.L 0x292D3A7B + .DATA.B ~((PROTECT_SECTOR_SA3 << 3) | (PROTECT_SECTOR_SA2 << 2) | (PROTECT_SECTOR_SA1 << 1) | PROTECT_SECTOR_SA0) + .DATA.E 0xFFFFFF + .DATA.B ~((PROTECT_SECTOR_SA39 << 7) | (PROTECT_SECTOR_SA38 << 6) | (PROTECT_SECTOR_SA37 << 5) | (PROTECT_SECTOR_SA36 << 4) | (PROTECT_SECTOR_SA35 << 3) | (PROTECT_SECTOR_SA34 << 2) | (PROTECT_SECTOR_SA33 << 1) | PROTECT_SECTOR_SA32) + .SKIP 3 +#else + .DATA.L 0xFFFFFFFF + .SKIP 8 +#endif ; MAIN_FLASH_WRITE_PROTECT + .SKIP 8 + +#if SATELLITE_FLASH == ON + .SECTION SATELLITE_PROTECT, CONST, LOCATE=H'DE001C +# if SATELLITE_FLASH_WRITE_PROTECT == ON + .DATA.L 0x292D3A7B + .DATA.B ~((PROTECT_SECTOR_SB3 << 3) | (PROTECT_SECTOR_SB2 << 2) | (PROTECT_SECTOR_SB1 << 1) | PROTECT_SECTOR_SB0) + .SKIP 7 +# else + .DATA.L 0xFFFFFFFF + .SKIP 8 +# endif ; SATELLITE_FLASH_WRITE_PROTECT + .SKIP 8 +#endif ; SATELLITE_FLASH == ON + + +;==================================================================== +; 6.18 Debug address specification +;==================================================================== +; +; BDM configuration section should always be defined for later +; configuration by e.g. debugger tool or (special) programmer tool. + + .SECTION BDM_CONFIG, CONST, LOCATE=H'DF0040 + +#if BACKGROUND_DEBUGGING == ON + + .DATA.L 0x292D3A7B + + .ORG H'DF0044 + .DATA.W BDM_CONFIGURATION + + .ORG H'DF0046 +# if (SERIES == MB96340 && DEVICE < 3) +# error Device does not support background debugging +# endif ; (SERIES == MB96340 && DEVICE < 3) + +# if (SERIES == MB96340 && DEVICE < 12) + .DATA.W (D'16 * CRYSTAL + BDM_BAUDRATE) / BDM_BAUDRATE +# else + .DATA.W (D'32 * CRYSTAL + BDM_BAUDRATE) / BDM_BAUDRATE +# endif ; (SERIES == MB96340 && if DEVICE < 12) + + .ORG H'DF0048 + .DATA.E BDM_EXT_CONFIG + + .ORG H'DF004B + .DATA.B BDM_WD_PATTERN + + .ORG H'DF0050 + .DATA.W BDM_PFCS0 + .DATA.W BDM_PFCS1 + .DATA.W BDM_PFCS2 + .DATA.W BDM_PFCS3 + + .DATA.E BDM_PFA0, BDM_PFA1 + .DATA.E BDM_PFA2, BDM_PFA3 + .DATA.E BDM_PFA4, BDM_PFA5 + .DATA.E BDM_PFA6, BDM_PFA7 + + .DATA.W BDM_PFD0, BDM_PFD1 + .DATA.W BDM_PFD2, BDM_PFD3 + .DATA.W BDM_PFD4, BDM_PFD5 + .DATA.W BDM_PFD6, BDM_PFD7 +#else + .DATAB.B 64, 0xFF ; fill section with 0xFF + +#endif ; BACKGROUND_DEBUGGING == ON + + .ORG 0xDF0080 + .END notresetyet ; define debugger start address + + +;==================================================================== +; ----------------------- End of Start-up file --------------------- +;==================================================================== diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/config/FreeRTOSConfig.h b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/config/FreeRTOSConfig.h new file mode 100644 index 000000000..8885329e2 --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/config/FreeRTOSConfig.h @@ -0,0 +1,100 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/* + * The below define should be same as the option selected by the Memory + * Model (Project->Setup Project->C Compiler->Catagory->Target Depend ) + * + * Valid settings here include: + * portSMALL 16 Bit 16 Bit + * portMEDIUM 16 Bit 24 Bit + * portCOMPACT 24 Bit 16 Bit + * portLARGE 24 Bit 24 Bit + */ +#define configMEMMODEL portMEDIUM + + + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 1 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 56000000 ) /* Clock setup from start.asm in the demo application. */ +#define configCLKP1_CLOCK_HZ ( ( unsigned portLONG ) 56000000 ) /* Clock setup from start.asm in the demo application. */ +#define configTICK_RATE_HZ ( (portTickType) 100 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 6 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 176 ) +#define configTOTAL_HEAP_SIZE ( (size_t) (21504) ) +#define configMAX_TASK_NAME_LEN ( 20 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 1 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 1 +#define configMAX_CO_ROUTINE_PRIORITIES ( 4 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vResumeFromISR 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/config/config.h b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/config/config.h new file mode 100644 index 000000000..78403f071 --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/config/config.h @@ -0,0 +1,63 @@ +/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ + +/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ + +/* ELIGIBILITY FOR ANY PURPOSES. */ + +/* (C) Fujitsu Microelectronics Europe GmbH */ + +/*--------------------------------------------------------------------------- + config.h + - This file contains the defines to include or exclude a certain demo + application function. +/*---------------------------------------------------------------------------*/ + +/* The below are the defines that includes the corresponding function (those create related + * tasks) if they are defined and vice a versa. + */ +#define INCLUDE_StartLEDFlashTasks 1 +#define INCLUDE_StartIntegerMathTasks 1 + +#define INCLUDE_StartPolledQueueTasks 1 +#define INCLUDE_StartSemaphoreTasks 1 +#define INCLUDE_StartBlockingQueueTasks 1 +#define INCLUDE_StartDynamicPriorityTasks 1 + +#define INCLUDE_StartFlashCoRoutines 1 +#define INCLUDE_StartHookCoRoutines 1 +#define INCLUDE_StartGenericQueueTasks 1 +#define INCLUDE_StartQueuePeekTasks 1 +#define INCLUDE_CreateSuicidalTasks 1 + +/* In order to have vTraceListTasks() the below define INCLUDE_TraceListTasks should be defined + * as 1. While doing so one have to compromise on some of the other tasks as vTraceListTasks() + * requires high amount of memory. It should be noted that if all the task are tried to be inclued + * then the compiler would give memory overflow error. + */ +#if __CONFIG__ == 1 + #define INCLUDE_AltStartComTestTasks 1 + #define INCLUDE_StartMathTasks 0 + #define INCLUDE_CreateBlockTimeTasks 0 + #define INCLUDE_TraceListTasks 0 +#elif __CONFIG__ == 2 + #define INCLUDE_AltStartComTestTasks 0 + #define INCLUDE_StartMathTasks 0 + #define INCLUDE_CreateBlockTimeTasks 0 + #define INCLUDE_TraceListTasks 1 +#elif __CONFIG__ == 3 + #define INCLUDE_AltStartComTestTasks 0 + #define INCLUDE_StartMathTasks 0 + #define INCLUDE_CreateBlockTimeTasks 0 + #define INCLUDE_TraceListTasks 0 +#elif __CONFIG__ == 4 + #define INCLUDE_AltStartComTestTasks 0 + #define INCLUDE_StartMathTasks 0 + #define INCLUDE_CreateBlockTimeTasks 1 + #define INCLUDE_TraceListTasks 1 +#else + #define INCLUDE_AltStartComTestTasks 0 + #define INCLUDE_StartMathTasks 0 + #define INCLUDE_CreateBlockTimeTasks 0 + #define INCLUDE_TraceListTasks 0 + #error __CONFIG__ should be defined and it should have value between 1 to 4 +#endif diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/crflash_sk16fx100mpc.c b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/crflash_sk16fx100mpc.c new file mode 100644 index 000000000..8a714bd71 --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/crflash_sk16fx100mpc.c @@ -0,0 +1,224 @@ +/* + FreeRTOS.org V4.7.0 - Copyright (C) 2003-2007 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + + Also see http://www.SafeRTOS.com a version that has been certified for use + in safety critical systems, plus commercial licensing, development and + support options. + *************************************************************************** +*/ + +/* + * This demo application file demonstrates the use of queues to pass data + * between co-routines. + * + * N represents the number of 'fixed delay' co-routines that are created and + * is set during initialisation. + * + * N 'fixed delay' co-routines are created that just block for a fixed + * period then post the number of an LED onto a queue. Each such co-routine + * uses a different block period. A single 'flash' co-routine is also created + * that blocks on the same queue, waiting for the number of the next LED it + * should flash. Upon receiving a number it simply toggle the instructed LED + * then blocks on the queue once more. In this manner each LED from LED 0 to + * LED N-1 is caused to flash at a different rate. + * + * The 'fixed delay' co-routines are created with co-routine priority 0. The + * flash co-routine is created with co-routine priority 1. This means that + * the queue should never contain more than a single item. This is because + * posting to the queue will unblock the 'flash' co-routine, and as this has + * a priority greater than the tasks posting to the queue it is guaranteed to + * have emptied the queue and blocked once again before the queue can contain + * any more date. An error is indicated if an attempt to post data to the + * queue fails - indicating that the queue is already full. + * + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "croutine.h" +#include "queue.h" + +/* Demo application includes. */ +#include "partest.h" +#include "crflash.h" + +/* The queue should only need to be of length 1. See the description at the +top of the file. */ +#define crfQUEUE_LENGTH 1 + +#define crfFIXED_DELAY_PRIORITY 0 +#define crfFLASH_PRIORITY 1 + +/* Only one flash co-routine is created so the index is not significant. */ +#define crfFLASH_INDEX 0 + +/* Don't allow more than crfMAX_FLASH_TASKS 'fixed delay' co-routines to be +created. */ +#define crfMAX_FLASH_TASKS 8 + +/* We don't want to block when posting to the queue. */ +#define crfPOSTING_BLOCK_TIME 0 + +/* Added by MPi, this define is added in order to make the vParTestToggleLED() +work. This basically differentiates the PDR09 from PDR00. 7-seg display LEDs connected +to PDR09 (SEG1) are used by the prvFlashCoRoutine() and PDR00 (SEG2) are used by tasks. */ +#define PDR00_Offset 8 + +/* + * The 'fixed delay' co-routine as described at the top of the file. + */ +static void prvFixedDelayCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + +/* + * The 'flash' co-routine as described at the top of the file. + */ +static void prvFlashCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); + +/* The queue used to pass data between the 'fixed delay' co-routines and the +'flash' co-routine. */ +static xQueueHandle xFlashQueue; + +/* This will be set to pdFALSE if we detect an error. */ +static unsigned portBASE_TYPE uxCoRoutineFlashStatus = pdPASS; + +/*-----------------------------------------------------------*/ + +/* + * See the header file for details. + */ +void vStartFlashCoRoutines( unsigned portBASE_TYPE uxNumberToCreate ) +{ +unsigned portBASE_TYPE uxIndex; + + if( uxNumberToCreate > crfMAX_FLASH_TASKS ) + { + uxNumberToCreate = crfMAX_FLASH_TASKS; + } + + /* Create the queue used to pass data between the co-routines. */ + xFlashQueue = xQueueCreate( crfQUEUE_LENGTH, sizeof( unsigned portBASE_TYPE ) ); + + if( xFlashQueue ) + { + /* Create uxNumberToCreate 'fixed delay' co-routines. */ + for( uxIndex = 0; uxIndex < uxNumberToCreate; uxIndex++ ) + { + xCoRoutineCreate( prvFixedDelayCoRoutine, crfFIXED_DELAY_PRIORITY, uxIndex ); + } + + /* Create the 'flash' co-routine. */ + xCoRoutineCreate( prvFlashCoRoutine, crfFLASH_PRIORITY, crfFLASH_INDEX ); + } +} +/*-----------------------------------------------------------*/ + +static void prvFixedDelayCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +/* Even though this is a co-routine the xResult variable does not need to be +static as we do not need it to maintain its state between blocks. */ +signed portBASE_TYPE xResult; +/* The uxIndex parameter of the co-routine function is used as an index into +the xFlashRates array to obtain the delay period to use. */ +static const portTickType xFlashRates[ crfMAX_FLASH_TASKS ] = { 150 / portTICK_RATE_MS, + 200 / portTICK_RATE_MS, + 250 / portTICK_RATE_MS, + 300 / portTICK_RATE_MS, + 350 / portTICK_RATE_MS, + 400 / portTICK_RATE_MS, + 450 / portTICK_RATE_MS, + 500 / portTICK_RATE_MS }; + + /* Co-routines MUST start with a call to crSTART. */ + crSTART( xHandle ); + + for( ;; ) + { + /* Post our uxIndex value onto the queue. This is used as the LED to + flash. */ + crQUEUE_SEND( xHandle, xFlashQueue, ( void * ) &uxIndex, crfPOSTING_BLOCK_TIME, &xResult ); + + if( xResult != pdPASS ) + { + /* For the reasons stated at the top of the file we should always + find that we can post to the queue. If we could not then an error + has occurred. */ + uxCoRoutineFlashStatus = pdFAIL; + } + + crDELAY( xHandle, xFlashRates[ uxIndex ] ); + } + + /* Co-routines MUST end with a call to crEND. */ + crEND(); +} +/*-----------------------------------------------------------*/ + +static void prvFlashCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) +{ +/* Even though this is a co-routine the variable do not need to be +static as we do not need it to maintain their state between blocks. */ +signed portBASE_TYPE xResult; +unsigned portBASE_TYPE uxLEDToFlash; + + /* Co-routines MUST start with a call to crSTART. */ + crSTART( xHandle ); + ( void ) uxIndex; + + for( ;; ) + { + /* Block to wait for the number of the LED to flash. */ + crQUEUE_RECEIVE( xHandle, xFlashQueue, &uxLEDToFlash, portMAX_DELAY, &xResult ); + + if( xResult != pdPASS ) + { + /* We would not expect to wake unless we received something. */ + uxCoRoutineFlashStatus = pdFAIL; + } + else + { + /* We received the number of an LED to flash - flash it! */ + /* Added by MPi, PDR00_Offset is added in order to make the + vParTestToggleLED() work. */ + vParTestToggleLED( uxLEDToFlash + PDR00_Offset ); + } + } + + /* Co-routines MUST end with a call to crEND. */ + crEND(); +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xAreFlashCoRoutinesStillRunning( void ) +{ + /* Return pdPASS or pdFAIL depending on whether an error has been detected + or not. */ + return uxCoRoutineFlashStatus; +} + diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/main.c b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/main.c new file mode 100644 index 000000000..9e03536ce --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/main.c @@ -0,0 +1,470 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/*--------------------------------------------------------------------------- + MAIN.C + - description + - See README.TXT for project description and disclaimer. + +/*---------------------------------------------------------------------------*/ + +/* 16FX includes */ +#include "mb96348hs.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" +#include +#include + +/*---------------------------------------------------------------------------*/ + +/* Demo task priorities. */ +#define WTC_TASK_PRIORITY ( tskIDLE_PRIORITY + 5 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) +#define TASK_UTILITY_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_BLOCK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainDEATH_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainGENERIC_QUEUE_PRIORITY ( tskIDLE_PRIORITY ) + +/* Baud rate used by the COM test tasks. */ +#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 19200 ) + +/* The frequency at which the 'Check' tasks executes. See the comments at the +top of the page. When the system is operating error free the 'Check' task +toggles an LED every three seconds. If an error is discovered in any task the +rate is increased to 500 milliseconds. [in this case the '*' characters on the +LCD represent LED's]*/ +#define mainNO_ERROR_CHECK_DELAY ( (portTickType) 3000 / portTICK_RATE_MS ) +#define mainERROR_CHECK_DELAY ( (portTickType) 500 / portTICK_RATE_MS ) + +/*---------------------------------------------------------------------------*/ +#define ledNUMBER_OF_LEDS 8 +#define mainCOM_TEST_LED 0x05 +#define mainCHECK_TEST_LED 0x07 + +/*---------------------------------------------------------------------------*/ + +/* + * The function that implements the Check task. See the comments at the head + * of the page for implementation details. + */ +static void vErrorChecks( void *pvParameters ); + +/* + * Called by the Check task. Returns pdPASS if all the other tasks are found + * to be operating without error - otherwise returns pdFAIL. + */ +static portSHORT prvCheckOtherTasksAreStillRunning( void ); + +/*---------------------------------------------------------------------------*/ +static unsigned portCHAR sState[2] = { 0xFF, 0xFF }; + +/*--------------------------------------------------------------------------- + * The below callback function is called from Tick ISR if configUSE_TICK_HOOK + * is configured as 1. + *---------------------------------------------------------------------------*/ + +/*void vApplicationTickHook ( void ) +{ +#if WATCHDOG == WTC_IN_TICK + Kick_Watchdog(); +#endif +}*/ + +/*--------------------------------------------------------------------------- + * The below callback function is called from Delayed ISR if configUSE_IDLE_HOOK + * is configured as 1. + *---------------------------------------------------------------------------*/ +void vApplicationIdleHook( void ) +{ + #if WATCHDOG == WTC_IN_IDLE + Kick_Watchdog(); + #endif + #if ( INCLUDE_StartFlashCoRoutines == 1 || INCLUDE_StartHookCoRoutines == 1 ) + vCoRoutineSchedule(); + #endif +} + +/*--------------------------------------------------------------------------- + * Initialize Port 00 + *---------------------------------------------------------------------------*/ +static void prvInitPort00( void ) +{ + DDR00 = 0xFF; + PDR00 = 0xFF; + DDR09 = 0xFF; + PDR09 = 0xFF; +} + +/*--------------------------------------------------------------------------- + * Setup the hardware + *---------------------------------------------------------------------------*/ +static void prvSetupHardware( void ) +{ + prvInitPort00(); + + #if WATCHDOG != WTC_NONE + InitWatchdog(); + #endif +} + +/*--------------------------------------------------------------------------- + * main() + *---------------------------------------------------------------------------*/ +void main( void ) +{ + InitIrqLevels(); /* Initialize interrupts */ + __set_il( 7 ); /* Allow all levels */ + + prvSetupHardware(); + + #if WATCHDOG == WTC_IN_TASK + vStartWatchdogTask( WTC_TASK_PRIORITY ); + #endif + + /* Start the standard demo application tasks. */ + #if ( INCLUDE_StartLEDFlashTasks == 1 ) + vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); + #endif + + #if ( INCLUDE_StartIntegerMathTasks == 1 ) + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + #endif + + #if ( INCLUDE_AltStartComTestTasks == 1 ) + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED - 1 ); + #endif + + #if ( INCLUDE_StartPolledQueueTasks == 1 ) + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + #endif + + #if ( INCLUDE_StartSemaphoreTasks == 1 ) + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + #endif + + #if ( INCLUDE_StartBlockingQueueTasks == 1 ) + vStartBlockingQueueTasks( mainQUEUE_BLOCK_PRIORITY ); + #endif + + #if ( INCLUDE_StartDynamicPriorityTasks == 1 ) + vStartDynamicPriorityTasks(); + #endif + + #if ( INCLUDE_StartMathTasks == 1 ) + vStartMathTasks( tskIDLE_PRIORITY ); + #endif + + #if ( INCLUDE_StartFlashCoRoutines == 1 ) + vStartFlashCoRoutines( ledNUMBER_OF_LEDS ); + #endif + + #if ( INCLUDE_StartHookCoRoutines == 1 ) + vStartHookCoRoutines(); + #endif + + #if ( INCLUDE_StartGenericQueueTasks == 1 ) + vStartGenericQueueTasks( mainGENERIC_QUEUE_PRIORITY ); + #endif + + #if ( INCLUDE_StartQueuePeekTasks == 1 ) + vStartQueuePeekTasks(); + #endif + + #if ( INCLUDE_CreateBlockTimeTasks == 1 ) + vCreateBlockTimeTasks(); + #endif + + #if ( INCLUDE_CreateSuicidalTasks == 1 ) + vCreateSuicidalTasks( mainDEATH_PRIORITY ); + #endif + + #if ( INCLUDE_TraceListTasks == 1 ) + vTraceListTasks( TASK_UTILITY_PRIORITY ); + #endif + + /* Start the 'Check' task which is defined in this file. */ + xTaskCreate( vErrorChecks, (signed portCHAR *) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + vTaskStartScheduler(); + + /* Should not reach here */ + while( 1 ) + { + __asm( " NOP " ); /* // */ + } +} + +/*-----------------------------------------------------------*/ +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ + if( uxLED < ledNUMBER_OF_LEDS ) + { + vTaskSuspendAll(); + + /* Toggle the state of the single genuine on board LED. */ + if( (sState[0] & ((portCHAR) (1 << uxLED))) == 0 ) + { + PDR09 |= ( 1 << uxLED ); + sState[0] |= ( 1 << uxLED ); + } + else + { + PDR09 &= ~( 1 << uxLED ); + sState[0] &= ~( 1 << uxLED ); + } + + xTaskResumeAll(); + } + else + { + vTaskSuspendAll(); + + uxLED -= ledNUMBER_OF_LEDS; + + if( (sState[1] & ((portCHAR) (1 << uxLED))) == 0 ) + { + PDR00 |= ( 1 << uxLED ); + sState[1] |= ( 1 << uxLED ); + } + else + { + PDR00 &= ~( 1 << uxLED ); + sState[1] &= ~( 1 << uxLED ); + } + + xTaskResumeAll(); + } +} + +/*-----------------------------------------------------------*/ +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ + /* Set or clear the output [in this case show or hide the '*' character. */ + if( uxLED < ledNUMBER_OF_LEDS ) + { + vTaskSuspendAll(); + { + if( xValue ) + { + PDR09 &= ~( 1 << uxLED ); + sState[0] &= ~( 1 << uxLED ); + } + else + { + PDR09 |= ( 1 << uxLED ); + sState[0] |= ( 1 << uxLED ); + } + } + + xTaskResumeAll(); + } + else + { + vTaskSuspendAll(); + { + if( xValue ) + { + PDR00 &= ~( 1 << uxLED ); + sState[1] &= ~( 1 << uxLED ); + } + else + { + PDR00 |= ( 1 << uxLED ); + sState[1] |= ( 1 << uxLED ); + } + } + + xTaskResumeAll(); + } +} + +/*-----------------------------------------------------------*/ +static void vErrorChecks( void *pvParameters ) +{ + static volatile unsigned portLONG ulDummyVariable = 3UL; + portTickType xDelayPeriod = mainNO_ERROR_CHECK_DELAY; + ( void ) pvParameters; + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. */ + for( ;; ) + { + /* Wait until it is time to check again. The time we wait here depends + on whether an error has been detected or not. When an error is + detected the time is shortened resulting in a faster LED flash rate. */ + vTaskDelay( xDelayPeriod ); + + /* Perform a bit of 32bit maths to ensure the registers used by the + integer tasks get some exercise outside of the integer tasks + themselves. The result here is not important we are just deliberately + changing registers used by other tasks to ensure that their context + switch is operating as required. - see the demo application + documentation for more info. */ + ulDummyVariable *= 3UL; + + /* See if the other tasks are all ok. */ + if( prvCheckOtherTasksAreStillRunning() != pdPASS ) + { + /* An error occurred in one of the tasks so shorten the delay + period - which has the effect of increasing the frequency of the + LED toggle. */ + xDelayPeriod = mainERROR_CHECK_DELAY; + } + + /* Flash! */ + vParTestToggleLED( mainCHECK_TEST_LED ); + } +} + +/*-----------------------------------------------------------*/ +static portSHORT prvCheckOtherTasksAreStillRunning( void ) +{ + static portSHORT sNoErrorFound = pdTRUE; + + /* The demo tasks maintain a count that increments every cycle of the task + provided that the task has never encountered an error. This function + checks the counts maintained by the tasks to ensure they are still being + incremented. A count remaining at the same value between calls therefore + indicates that an error has been detected. Only tasks that do not flash + an LED are checked. */ + #if ( INCLUDE_StartIntegerMathTasks == 1 ) + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + sNoErrorFound = pdFALSE; + } + + #endif + #if ( INCLUDE_AltStartComTestTasks == 1 ) + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + sNoErrorFound = pdFALSE; + } + + #endif + #if ( INCLUDE_StartPolledQueueTasks == 1 ) + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + sNoErrorFound = pdFALSE; + } + + #endif + #if ( INCLUDE_StartSemaphoreTasks == 1 ) + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + sNoErrorFound = pdFALSE; + } + + #endif + #if ( INCLUDE_StartBlockingQueueTasks == 1 ) + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + sNoErrorFound = pdFALSE; + } + + #endif + #if ( INCLUDE_StartDynamicPriorityTasks == 1 ) + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + sNoErrorFound = pdFALSE; + } + + #endif + #if ( INCLUDE_StartMathTasks == 1 ) + if( xAreMathsTaskStillRunning() != pdTRUE ) + { + sNoErrorFound = pdFALSE; + } + + #endif + #if ( INCLUDE_StartFlashCoRoutines == 1 ) + if( xAreFlashCoRoutinesStillRunning() != pdTRUE ) + { + sNoErrorFound = pdFALSE; + } + + #endif + #if ( INCLUDE_StartHookCoRoutines == 1 ) + if( xAreHookCoRoutinesStillRunning() != pdTRUE ) + { + sNoErrorFound = pdFALSE; + } + + #endif + #if ( INCLUDE_StartGenericQueueTasks == 1 ) + if( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + sNoErrorFound = pdFALSE; + } + + #endif + #if ( INCLUDE_StartQueuePeekTasks == 1 ) + if( xAreQueuePeekTasksStillRunning() != pdTRUE ) + { + sNoErrorFound = pdFALSE; + } + + #endif + #if ( INCLUDE_CreateBlockTimeTasks == 1 ) + if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + sNoErrorFound = pdFALSE; + } + + #endif + #if ( INCLUDE_CreateSuicidalTasks == 1 ) + if( xIsCreateTaskStillRunning() != pdTRUE ) + { + sNoErrorFound = pdFALSE; + } + + #endif + return sNoErrorFound; +} + +/*---------------------------------------------------------------------------*/ diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/mb96348hs.asm b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/mb96348hs.asm new file mode 100644 index 000000000..d6613c658 --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/mb96348hs.asm @@ -0,0 +1,2090 @@ +/* FFMC-16 IO-MAP HEADER FILE */ +/* ========================== */ +/* SOFTUNE WORKBENCH FORMAT */ +/* C-DEFINITIONS FOR IO-SYMBOLS */ +/* CREATED BY IO-WIZARD V2.27 */ +/* $Id: mb96348hs.asm,v 1.7 2007/09/20 14:23:20 mwilla Exp $ */ +/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ +/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ +/* ELIGIBILITY FOR ANY PURPOSES. */ +/* (C) Fujitsu Microelectronics Europe GmbH */ +/* ************************************************************************* */ +/* FUJITSU MICROELECTRONICS EUROPE GMBH */ +/* Pittlerstrasse 47, 63225 Langen, Germany */ +/* Tel.:++49/6103/690-0,Fax - 122 */ +/* */ +/* The following software is for demonstration purposes only. */ +/* It is not fully tested, nor validated in order to fullfill */ +/* its task under all circumstances. Therefore, this software */ +/* or any part of it must only be used in an evaluation */ +/* laboratory environment. */ +/* This software is subject to the rules of our standard */ +/* DISCLAIMER, that is delivered with our SW-tools on the CD or DVD */ +/* "Micros Documentation & Software" (V3.4 or later) or */ +/* see our Internet Page - */ +/* http://emea.fujitsu.com/microelectronics */ +/* ************************************************************************* */ +/* */ +/* NOTE: */ +/* */ +/* This header-file covers all features of the chip MB96F348HS. */ +/* */ +/* */ +/* ---------------------------------------------------------------------- */ +/* History: */ +/* Date Version Author Description */ +/* 22.12.2006 1.0 PHu Initial Release: derived from headerfile of */ +/* MB96348RS and added Satellite Flash, removed */ +/* RTC, Clock Calibration, LIN-USART7-9 */ +/* 16.01.2007 1.1 PHu Add 32-bit access names for CAN where */ +/* appropriate */ +/* 09.02.2007 1.3 PHu skip version 1.2 to be in line with CVS */ +/* numbering */ +/* correct addresses of LIN-UART3 registers */ +/* allow only 16 bit access for the ADSR */ +/* 12.04.2007 1.4 Mef Added Voltage Regulator Control Register */ +/* Added RD19V bit in Flash Memory Control */ +/* Status Register */ +/* 03.05.2007 1.5 Mef Added LIN USART 7,8,9 */ +/* 15.05.2007 1.6 Mef Added RTC */ +/* 20.09.2007 1.7 MWi Completely revised version */ + + .PROGRAM MB96348HS + .TITLE MB96348HS + +;------------------------ +; IO-AREA DEFINITIONS : +;------------------------ + + + + .section IOBASE, IO, locate=0x0 ; + .GLOBAL __pdr00, __pdr01, __pdr02, __pdr03, __pdr04, __pdr05 + .GLOBAL __pdr06, __pdr07, __pdr08, __pdr09, __pdr10, __adcs + .GLOBAL __adcsl, __adcsh, __adcr, __adcrl, __adcrh, __adsr + .GLOBAL __adecr, __tcdt0, __tccs0, __tccsl0, __tccsh0, __tcdt1 + .GLOBAL __tccs1, __tccsl1, __tccsh1, __ocs0, __ocs1, __occp0 + .GLOBAL __occp1, __ocs2, __ocs3, __occp2, __occp3, __ocs4 + .GLOBAL __ocs5, __occp4, __occp5, __ocs6, __ocs7, __occp6 + .GLOBAL __occp7, __ics01, __ice01, __ipcp0, __ipcpl0, __ipcph0 + .GLOBAL __ipcp1, __ipcpl1, __ipcph1, __ics23, __ice23, __ipcp2 + .GLOBAL __ipcpl2, __ipcph2, __ipcp3, __ipcpl3, __ipcph3, __ics45 + .GLOBAL __ice45, __ipcp4, __ipcpl4, __ipcph4, __ipcp5, __ipcpl5 + .GLOBAL __ipcph5, __ics67, __ice67, __ipcp6, __ipcpl6, __ipcph6 + .GLOBAL __ipcp7, __ipcpl7, __ipcph7, __enir0, __eirr0, __elvr0 + .GLOBAL __elvrl0, __elvrh0, __enir1, __eirr1, __elvr1, __elvrl1 + .GLOBAL __elvrh1, __tmcsr0, __tmcsrl0, __tmcsrh0, __tmrlr0, __tmr0 + .GLOBAL __tmcsr1, __tmcsrl1, __tmcsrh1, __tmrlr1, __tmr1, __tmcsr2 + .GLOBAL __tmcsrl2, __tmcsrh2, __tmrlr2, __tmr2, __tmcsr3, __tmcsrl3 + .GLOBAL __tmcsrh3, __tmrlr3, __tmr3, __tmcsr6, __tmcsrl6, __tmcsrh6 + .GLOBAL __tmrlr6, __tmr6, __gcn10, __gcn1l0, __gcn1h0, __gcn20 + .GLOBAL __gcn2l0, __gcn2h0, __ptmr0, __pcsr0, __pdut0, __pcn0 + .GLOBAL __pcnl0, __pcnh0, __ptmr1, __pcsr1, __pdut1, __pcn1 + .GLOBAL __pcnl1, __pcnh1, __ptmr2, __pcsr2, __pdut2, __pcn2 + .GLOBAL __pcnl2, __pcnh2, __ptmr3, __pcsr3, __pdut3, __pcn3 + .GLOBAL __pcnl3, __pcnh3, __gcn11, __gcn1l1, __gcn1h1, __gcn21 + .GLOBAL __gcn2l1, __gcn2h1, __ptmr4, __pcsr4, __pdut4, __pcn4 + .GLOBAL __pcnl4, __pcnh4, __ptmr5, __pcsr5, __pdut5, __pcn5 + .GLOBAL __pcnl5, __pcnh5, __ibsr0, __ibcr0, __itba0, __itbal0 + .GLOBAL __itbah0, __itmk0, __itmkl0, __itmkh0, __isba0, __ismk0 + .GLOBAL __idar0, __iccr0, __ibsr1, __ibcr1, __itba1, __itbal1 + .GLOBAL __itbah1, __itmk1, __itmkl1, __itmkh1, __isba1, __ismk1 + .GLOBAL __idar1, __iccr1, __smr0, __scr0, __tdr0, __rdr0 + .GLOBAL __ssr0, __eccr0, __escr0, __bgr0, __bgrl0, __bgrh0 + .GLOBAL __esir0, __smr1, __scr1, __tdr1, __rdr1, __ssr1 + .GLOBAL __eccr1, __escr1, __bgr1, __bgrl1, __bgrh1, __esir1 + .GLOBAL __smr2, __scr2, __tdr2, __rdr2, __ssr2, __eccr2 + .GLOBAL __escr2, __bgr2, __bgrl2, __bgrh2, __esir2, __smr3 + .GLOBAL __scr3, __tdr3, __rdr3, __ssr3, __eccr3, __escr3 + .GLOBAL __bgr3, __bgrl3, __bgrh3, __esir3 + +__pdr00 .res.b 1 ;000000 +PDR00 .equ 0x0000 +__pdr01 .res.b 1 ;000001 +PDR01 .equ 0x0001 +__pdr02 .res.b 1 ;000002 +PDR02 .equ 0x0002 +__pdr03 .res.b 1 ;000003 +PDR03 .equ 0x0003 +__pdr04 .res.b 1 ;000004 +PDR04 .equ 0x0004 +__pdr05 .res.b 1 ;000005 +PDR05 .equ 0x0005 +__pdr06 .res.b 1 ;000006 +PDR06 .equ 0x0006 +__pdr07 .res.b 1 ;000007 +PDR07 .equ 0x0007 +__pdr08 .res.b 1 ;000008 +PDR08 .equ 0x0008 +__pdr09 .res.b 1 ;000009 +PDR09 .equ 0x0009 +__pdr10 .res.b 1 ;00000A +PDR10 .equ 0x000A + .org 0x000018 +__adcs ; overlay symbol ;000018 +ADCS .equ 0x0018 +__adcsl .res.b 1 ;000018 +ADCSL .equ 0x0018 +__adcsh .res.b 1 ;000019 +ADCSH .equ 0x0019 +__adcr ; overlay symbol ;00001A +ADCR .equ 0x001A +__adcrl .res.b 1 ;00001A +ADCRL .equ 0x001A +__adcrh .res.b 1 ;00001B +ADCRH .equ 0x001B +__adsr .res.b 2 ;00001C +ADSR .equ 0x001C +__adecr .res.b 1 ;00001E +ADECR .equ 0x001E + .org 0x000020 +__tcdt0 .res.b 2 ;000020 +TCDT0 .equ 0x0020 +__tccs0 ; overlay symbol ;000022 +TCCS0 .equ 0x0022 +__tccsl0 .res.b 1 ;000022 +TCCSL0 .equ 0x0022 +__tccsh0 .res.b 1 ;000023 +TCCSH0 .equ 0x0023 +__tcdt1 .res.b 2 ;000024 +TCDT1 .equ 0x0024 +__tccs1 ; overlay symbol ;000026 +TCCS1 .equ 0x0026 +__tccsl1 .res.b 1 ;000026 +TCCSL1 .equ 0x0026 +__tccsh1 .res.b 1 ;000027 +TCCSH1 .equ 0x0027 +__ocs0 .res.b 1 ;000028 +OCS0 .equ 0x0028 +__ocs1 .res.b 1 ;000029 +OCS1 .equ 0x0029 +__occp0 .res.b 2 ;00002A +OCCP0 .equ 0x002A +__occp1 .res.b 2 ;00002C +OCCP1 .equ 0x002C +__ocs2 .res.b 1 ;00002E +OCS2 .equ 0x002E +__ocs3 .res.b 1 ;00002F +OCS3 .equ 0x002F +__occp2 .res.b 2 ;000030 +OCCP2 .equ 0x0030 +__occp3 .res.b 2 ;000032 +OCCP3 .equ 0x0032 +__ocs4 .res.b 1 ;000034 +OCS4 .equ 0x0034 +__ocs5 .res.b 1 ;000035 +OCS5 .equ 0x0035 +__occp4 .res.b 2 ;000036 +OCCP4 .equ 0x0036 +__occp5 .res.b 2 ;000038 +OCCP5 .equ 0x0038 +__ocs6 .res.b 1 ;00003A +OCS6 .equ 0x003A +__ocs7 .res.b 1 ;00003B +OCS7 .equ 0x003B +__occp6 .res.b 2 ;00003C +OCCP6 .equ 0x003C +__occp7 .res.b 2 ;00003E +OCCP7 .equ 0x003E +__ics01 .res.b 1 ;000040 +ICS01 .equ 0x0040 +__ice01 .res.b 1 ;000041 +ICE01 .equ 0x0041 +__ipcp0 ; overlay symbol ;000042 +IPCP0 .equ 0x0042 +__ipcpl0 .res.b 1 ;000042 +IPCPL0 .equ 0x0042 +__ipcph0 .res.b 1 ;000043 +IPCPH0 .equ 0x0043 +__ipcp1 ; overlay symbol ;000044 +IPCP1 .equ 0x0044 +__ipcpl1 .res.b 1 ;000044 +IPCPL1 .equ 0x0044 +__ipcph1 .res.b 1 ;000045 +IPCPH1 .equ 0x0045 +__ics23 .res.b 1 ;000046 +ICS23 .equ 0x0046 +__ice23 .res.b 1 ;000047 +ICE23 .equ 0x0047 +__ipcp2 ; overlay symbol ;000048 +IPCP2 .equ 0x0048 +__ipcpl2 .res.b 1 ;000048 +IPCPL2 .equ 0x0048 +__ipcph2 .res.b 1 ;000049 +IPCPH2 .equ 0x0049 +__ipcp3 ; overlay symbol ;00004A +IPCP3 .equ 0x004A +__ipcpl3 .res.b 1 ;00004A +IPCPL3 .equ 0x004A +__ipcph3 .res.b 1 ;00004B +IPCPH3 .equ 0x004B +__ics45 .res.b 1 ;00004C +ICS45 .equ 0x004C +__ice45 .res.b 1 ;00004D +ICE45 .equ 0x004D +__ipcp4 ; overlay symbol ;00004E +IPCP4 .equ 0x004E +__ipcpl4 .res.b 1 ;00004E +IPCPL4 .equ 0x004E +__ipcph4 .res.b 1 ;00004F +IPCPH4 .equ 0x004F +__ipcp5 ; overlay symbol ;000050 +IPCP5 .equ 0x0050 +__ipcpl5 .res.b 1 ;000050 +IPCPL5 .equ 0x0050 +__ipcph5 .res.b 1 ;000051 +IPCPH5 .equ 0x0051 +__ics67 .res.b 1 ;000052 +ICS67 .equ 0x0052 +__ice67 .res.b 1 ;000053 +ICE67 .equ 0x0053 +__ipcp6 ; overlay symbol ;000054 +IPCP6 .equ 0x0054 +__ipcpl6 .res.b 1 ;000054 +IPCPL6 .equ 0x0054 +__ipcph6 .res.b 1 ;000055 +IPCPH6 .equ 0x0055 +__ipcp7 ; overlay symbol ;000056 +IPCP7 .equ 0x0056 +__ipcpl7 .res.b 1 ;000056 +IPCPL7 .equ 0x0056 +__ipcph7 .res.b 1 ;000057 +IPCPH7 .equ 0x0057 +__enir0 .res.b 1 ;000058 +ENIR0 .equ 0x0058 +__eirr0 .res.b 1 ;000059 +EIRR0 .equ 0x0059 +__elvr0 ; overlay symbol ;00005A +ELVR0 .equ 0x005A +__elvrl0 .res.b 1 ;00005A +ELVRL0 .equ 0x005A +__elvrh0 .res.b 1 ;00005B +ELVRH0 .equ 0x005B +__enir1 .res.b 1 ;00005C +ENIR1 .equ 0x005C +__eirr1 .res.b 1 ;00005D +EIRR1 .equ 0x005D +__elvr1 ; overlay symbol ;00005E +ELVR1 .equ 0x005E +__elvrl1 .res.b 1 ;00005E +ELVRL1 .equ 0x005E +__elvrh1 .res.b 1 ;00005F +ELVRH1 .equ 0x005F +__tmcsr0 ; overlay symbol ;000060 +TMCSR0 .equ 0x0060 +__tmcsrl0 .res.b 1 ;000060 +TMCSRL0 .equ 0x0060 +__tmcsrh0 .res.b 1 ;000061 +TMCSRH0 .equ 0x0061 +__tmrlr0 ; overlay symbol ;000062 +TMRLR0 .equ 0x0062 +__tmr0 .res.b 2 ;000062 +TMR0 .equ 0x0062 +__tmcsr1 ; overlay symbol ;000064 +TMCSR1 .equ 0x0064 +__tmcsrl1 .res.b 1 ;000064 +TMCSRL1 .equ 0x0064 +__tmcsrh1 .res.b 1 ;000065 +TMCSRH1 .equ 0x0065 +__tmrlr1 ; overlay symbol ;000066 +TMRLR1 .equ 0x0066 +__tmr1 .res.b 2 ;000066 +TMR1 .equ 0x0066 +__tmcsr2 ; overlay symbol ;000068 +TMCSR2 .equ 0x0068 +__tmcsrl2 .res.b 1 ;000068 +TMCSRL2 .equ 0x0068 +__tmcsrh2 .res.b 1 ;000069 +TMCSRH2 .equ 0x0069 +__tmrlr2 ; overlay symbol ;00006A +TMRLR2 .equ 0x006A +__tmr2 .res.b 2 ;00006A +TMR2 .equ 0x006A +__tmcsr3 ; overlay symbol ;00006C +TMCSR3 .equ 0x006C +__tmcsrl3 .res.b 1 ;00006C +TMCSRL3 .equ 0x006C +__tmcsrh3 .res.b 1 ;00006D +TMCSRH3 .equ 0x006D +__tmrlr3 ; overlay symbol ;00006E +TMRLR3 .equ 0x006E +__tmr3 .res.b 2 ;00006E +TMR3 .equ 0x006E +__tmcsr6 ; overlay symbol ;000070 +TMCSR6 .equ 0x0070 +__tmcsrl6 .res.b 1 ;000070 +TMCSRL6 .equ 0x0070 +__tmcsrh6 .res.b 1 ;000071 +TMCSRH6 .equ 0x0071 +__tmrlr6 ; overlay symbol ;000072 +TMRLR6 .equ 0x0072 +__tmr6 .res.b 2 ;000072 +TMR6 .equ 0x0072 +__gcn10 ; overlay symbol ;000074 +GCN10 .equ 0x0074 +__gcn1l0 .res.b 1 ;000074 +GCN1L0 .equ 0x0074 +__gcn1h0 .res.b 1 ;000075 +GCN1H0 .equ 0x0075 +__gcn20 ; overlay symbol ;000076 +GCN20 .equ 0x0076 +__gcn2l0 .res.b 1 ;000076 +GCN2L0 .equ 0x0076 +__gcn2h0 .res.b 1 ;000077 +GCN2H0 .equ 0x0077 +__ptmr0 .res.b 2 ;000078 +PTMR0 .equ 0x0078 +__pcsr0 .res.b 2 ;00007A +PCSR0 .equ 0x007A +__pdut0 .res.b 2 ;00007C +PDUT0 .equ 0x007C +__pcn0 ; overlay symbol ;00007E +PCN0 .equ 0x007E +__pcnl0 .res.b 1 ;00007E +PCNL0 .equ 0x007E +__pcnh0 .res.b 1 ;00007F +PCNH0 .equ 0x007F +__ptmr1 .res.b 2 ;000080 +PTMR1 .equ 0x0080 +__pcsr1 .res.b 2 ;000082 +PCSR1 .equ 0x0082 +__pdut1 .res.b 2 ;000084 +PDUT1 .equ 0x0084 +__pcn1 ; overlay symbol ;000086 +PCN1 .equ 0x0086 +__pcnl1 .res.b 1 ;000086 +PCNL1 .equ 0x0086 +__pcnh1 .res.b 1 ;000087 +PCNH1 .equ 0x0087 +__ptmr2 .res.b 2 ;000088 +PTMR2 .equ 0x0088 +__pcsr2 .res.b 2 ;00008A +PCSR2 .equ 0x008A +__pdut2 .res.b 2 ;00008C +PDUT2 .equ 0x008C +__pcn2 ; overlay symbol ;00008E +PCN2 .equ 0x008E +__pcnl2 .res.b 1 ;00008E +PCNL2 .equ 0x008E +__pcnh2 .res.b 1 ;00008F +PCNH2 .equ 0x008F +__ptmr3 .res.b 2 ;000090 +PTMR3 .equ 0x0090 +__pcsr3 .res.b 2 ;000092 +PCSR3 .equ 0x0092 +__pdut3 .res.b 2 ;000094 +PDUT3 .equ 0x0094 +__pcn3 ; overlay symbol ;000096 +PCN3 .equ 0x0096 +__pcnl3 .res.b 1 ;000096 +PCNL3 .equ 0x0096 +__pcnh3 .res.b 1 ;000097 +PCNH3 .equ 0x0097 +__gcn11 ; overlay symbol ;000098 +GCN11 .equ 0x0098 +__gcn1l1 .res.b 1 ;000098 +GCN1L1 .equ 0x0098 +__gcn1h1 .res.b 1 ;000099 +GCN1H1 .equ 0x0099 +__gcn21 ; overlay symbol ;00009A +GCN21 .equ 0x009A +__gcn2l1 .res.b 1 ;00009A +GCN2L1 .equ 0x009A +__gcn2h1 .res.b 1 ;00009B +GCN2H1 .equ 0x009B +__ptmr4 .res.b 2 ;00009C +PTMR4 .equ 0x009C +__pcsr4 .res.b 2 ;00009E +PCSR4 .equ 0x009E +__pdut4 .res.b 2 ;0000A0 +PDUT4 .equ 0x00A0 +__pcn4 ; overlay symbol ;0000A2 +PCN4 .equ 0x00A2 +__pcnl4 .res.b 1 ;0000A2 +PCNL4 .equ 0x00A2 +__pcnh4 .res.b 1 ;0000A3 +PCNH4 .equ 0x00A3 +__ptmr5 .res.b 2 ;0000A4 +PTMR5 .equ 0x00A4 +__pcsr5 .res.b 2 ;0000A6 +PCSR5 .equ 0x00A6 +__pdut5 .res.b 2 ;0000A8 +PDUT5 .equ 0x00A8 +__pcn5 ; overlay symbol ;0000AA +PCN5 .equ 0x00AA +__pcnl5 .res.b 1 ;0000AA +PCNL5 .equ 0x00AA +__pcnh5 .res.b 1 ;0000AB +PCNH5 .equ 0x00AB +__ibsr0 .res.b 1 ;0000AC +IBSR0 .equ 0x00AC +__ibcr0 .res.b 1 ;0000AD +IBCR0 .equ 0x00AD +__itba0 ; overlay symbol ;0000AE +ITBA0 .equ 0x00AE +__itbal0 .res.b 1 ;0000AE +ITBAL0 .equ 0x00AE +__itbah0 .res.b 1 ;0000AF +ITBAH0 .equ 0x00AF +__itmk0 ; overlay symbol ;0000B0 +ITMK0 .equ 0x00B0 +__itmkl0 .res.b 1 ;0000B0 +ITMKL0 .equ 0x00B0 +__itmkh0 .res.b 1 ;0000B1 +ITMKH0 .equ 0x00B1 +__isba0 .res.b 1 ;0000B2 +ISBA0 .equ 0x00B2 +__ismk0 .res.b 1 ;0000B3 +ISMK0 .equ 0x00B3 +__idar0 .res.b 1 ;0000B4 +IDAR0 .equ 0x00B4 +__iccr0 .res.b 1 ;0000B5 +ICCR0 .equ 0x00B5 +__ibsr1 .res.b 1 ;0000B6 +IBSR1 .equ 0x00B6 +__ibcr1 .res.b 1 ;0000B7 +IBCR1 .equ 0x00B7 +__itba1 ; overlay symbol ;0000B8 +ITBA1 .equ 0x00B8 +__itbal1 .res.b 1 ;0000B8 +ITBAL1 .equ 0x00B8 +__itbah1 .res.b 1 ;0000B9 +ITBAH1 .equ 0x00B9 +__itmk1 ; overlay symbol ;0000BA +ITMK1 .equ 0x00BA +__itmkl1 .res.b 1 ;0000BA +ITMKL1 .equ 0x00BA +__itmkh1 .res.b 1 ;0000BB +ITMKH1 .equ 0x00BB +__isba1 .res.b 1 ;0000BC +ISBA1 .equ 0x00BC +__ismk1 .res.b 1 ;0000BD +ISMK1 .equ 0x00BD +__idar1 .res.b 1 ;0000BE +IDAR1 .equ 0x00BE +__iccr1 .res.b 1 ;0000BF +ICCR1 .equ 0x00BF +__smr0 .res.b 1 ;0000C0 +SMR0 .equ 0x00C0 +__scr0 .res.b 1 ;0000C1 +SCR0 .equ 0x00C1 +__tdr0 ; overlay symbol ;0000C2 +TDR0 .equ 0x00C2 +__rdr0 .res.b 1 ;0000C2 +RDR0 .equ 0x00C2 +__ssr0 .res.b 1 ;0000C3 +SSR0 .equ 0x00C3 +__eccr0 .res.b 1 ;0000C4 +ECCR0 .equ 0x00C4 +__escr0 .res.b 1 ;0000C5 +ESCR0 .equ 0x00C5 +__bgr0 ; overlay symbol ;0000C6 +BGR0 .equ 0x00C6 +__bgrl0 .res.b 1 ;0000C6 +BGRL0 .equ 0x00C6 +__bgrh0 .res.b 1 ;0000C7 +BGRH0 .equ 0x00C7 +__esir0 .res.b 1 ;0000C8 +ESIR0 .equ 0x00C8 + .org 0x0000cA +__smr1 .res.b 1 ;0000CA +SMR1 .equ 0x00CA +__scr1 .res.b 1 ;0000CB +SCR1 .equ 0x00CB +__tdr1 ; overlay symbol ;0000CC +TDR1 .equ 0x00CC +__rdr1 .res.b 1 ;0000CC +RDR1 .equ 0x00CC +__ssr1 .res.b 1 ;0000CD +SSR1 .equ 0x00CD +__eccr1 .res.b 1 ;0000CE +ECCR1 .equ 0x00CE +__escr1 .res.b 1 ;0000CF +ESCR1 .equ 0x00CF +__bgr1 ; overlay symbol ;0000D0 +BGR1 .equ 0x00D0 +__bgrl1 .res.b 1 ;0000D0 +BGRL1 .equ 0x00D0 +__bgrh1 .res.b 1 ;0000D1 +BGRH1 .equ 0x00D1 +__esir1 .res.b 1 ;0000D2 +ESIR1 .equ 0x00D2 + .org 0x0000d4 +__smr2 .res.b 1 ;0000D4 +SMR2 .equ 0x00D4 +__scr2 .res.b 1 ;0000D5 +SCR2 .equ 0x00D5 +__tdr2 ; overlay symbol ;0000D6 +TDR2 .equ 0x00D6 +__rdr2 .res.b 1 ;0000D6 +RDR2 .equ 0x00D6 +__ssr2 .res.b 1 ;0000D7 +SSR2 .equ 0x00D7 +__eccr2 .res.b 1 ;0000D8 +ECCR2 .equ 0x00D8 +__escr2 .res.b 1 ;0000D9 +ESCR2 .equ 0x00D9 +__bgr2 ; overlay symbol ;0000DA +BGR2 .equ 0x00DA +__bgrl2 .res.b 1 ;0000DA +BGRL2 .equ 0x00DA +__bgrh2 .res.b 1 ;0000DB +BGRH2 .equ 0x00DB +__esir2 .res.b 1 ;0000DC +ESIR2 .equ 0x00DC + .org 0x0000de +__smr3 .res.b 1 ;0000DE +SMR3 .equ 0x00DE +__scr3 .res.b 1 ;0000DF +SCR3 .equ 0x00DF +__tdr3 ; overlay symbol ;0000E0 +TDR3 .equ 0x00E0 +__rdr3 .res.b 1 ;0000E0 +RDR3 .equ 0x00E0 +__ssr3 .res.b 1 ;0000E1 +SSR3 .equ 0x00E1 +__eccr3 .res.b 1 ;0000E2 +ECCR3 .equ 0x00E2 +__escr3 .res.b 1 ;0000E3 +ESCR3 .equ 0x00E3 +__bgr3 ; overlay symbol ;0000E4 +BGR3 .equ 0x00E4 +__bgrl3 .res.b 1 ;0000E4 +BGRL3 .equ 0x00E4 +__bgrh3 .res.b 1 ;0000E5 +BGRH3 .equ 0x00E5 +__esir3 .res.b 1 ;0000E6 +ESIR3 .equ 0x00E6 + + .section DMADESCRIPTOR, DATA, locate=0x100 ; + .GLOBAL __bapl0, __bapm0, __baph0, __dmacs0, __ioa0, __ioal0 + .GLOBAL __ioah0, __dct0, __dctl0, __dcth0, __bapl1, __bapm1 + .GLOBAL __baph1, __dmacs1, __ioa1, __ioal1, __ioah1, __dct1 + .GLOBAL __dctl1, __dcth1, __bapl2, __bapm2, __baph2, __dmacs2 + .GLOBAL __ioa2, __ioal2, __ioah2, __dct2, __dctl2, __dcth2 + .GLOBAL __bapl3, __bapm3, __baph3, __dmacs3, __ioa3, __ioal3 + .GLOBAL __ioah3, __dct3, __dctl3, __dcth3, __bapl4, __bapm4 + .GLOBAL __baph4, __dmacs4, __ioa4, __ioal4, __ioah4, __dct4 + .GLOBAL __dctl4, __dcth4, __bapl5, __bapm5, __baph5, __dmacs5 + .GLOBAL __ioa5, __ioal5, __ioah5, __dct5, __dctl5, __dcth5 + +__bapl0 .res.b 1 ;000100 +BAPL0 .equ 0x0100 +__bapm0 .res.b 1 ;000101 +BAPM0 .equ 0x0101 +__baph0 .res.b 1 ;000102 +BAPH0 .equ 0x0102 +__dmacs0 .res.b 1 ;000103 +DMACS0 .equ 0x0103 +__ioa0 ; overlay symbol ;000104 +IOA0 .equ 0x0104 +__ioal0 .res.b 1 ;000104 +IOAL0 .equ 0x0104 +__ioah0 .res.b 1 ;000105 +IOAH0 .equ 0x0105 +__dct0 ; overlay symbol ;000106 +DCT0 .equ 0x0106 +__dctl0 .res.b 1 ;000106 +DCTL0 .equ 0x0106 +__dcth0 .res.b 1 ;000107 +DCTH0 .equ 0x0107 +__bapl1 .res.b 1 ;000108 +BAPL1 .equ 0x0108 +__bapm1 .res.b 1 ;000109 +BAPM1 .equ 0x0109 +__baph1 .res.b 1 ;00010A +BAPH1 .equ 0x010A +__dmacs1 .res.b 1 ;00010B +DMACS1 .equ 0x010B +__ioa1 ; overlay symbol ;00010C +IOA1 .equ 0x010C +__ioal1 .res.b 1 ;00010C +IOAL1 .equ 0x010C +__ioah1 .res.b 1 ;00010D +IOAH1 .equ 0x010D +__dct1 ; overlay symbol ;00010E +DCT1 .equ 0x010E +__dctl1 .res.b 1 ;00010E +DCTL1 .equ 0x010E +__dcth1 .res.b 1 ;00010F +DCTH1 .equ 0x010F +__bapl2 .res.b 1 ;000110 +BAPL2 .equ 0x0110 +__bapm2 .res.b 1 ;000111 +BAPM2 .equ 0x0111 +__baph2 .res.b 1 ;000112 +BAPH2 .equ 0x0112 +__dmacs2 .res.b 1 ;000113 +DMACS2 .equ 0x0113 +__ioa2 ; overlay symbol ;000114 +IOA2 .equ 0x0114 +__ioal2 .res.b 1 ;000114 +IOAL2 .equ 0x0114 +__ioah2 .res.b 1 ;000115 +IOAH2 .equ 0x0115 +__dct2 ; overlay symbol ;000116 +DCT2 .equ 0x0116 +__dctl2 .res.b 1 ;000116 +DCTL2 .equ 0x0116 +__dcth2 .res.b 1 ;000117 +DCTH2 .equ 0x0117 +__bapl3 .res.b 1 ;000118 +BAPL3 .equ 0x0118 +__bapm3 .res.b 1 ;000119 +BAPM3 .equ 0x0119 +__baph3 .res.b 1 ;00011A +BAPH3 .equ 0x011A +__dmacs3 .res.b 1 ;00011B +DMACS3 .equ 0x011B +__ioa3 ; overlay symbol ;00011C +IOA3 .equ 0x011C +__ioal3 .res.b 1 ;00011C +IOAL3 .equ 0x011C +__ioah3 .res.b 1 ;00011D +IOAH3 .equ 0x011D +__dct3 ; overlay symbol ;00011E +DCT3 .equ 0x011E +__dctl3 .res.b 1 ;00011E +DCTL3 .equ 0x011E +__dcth3 .res.b 1 ;00011F +DCTH3 .equ 0x011F +__bapl4 .res.b 1 ;000120 +BAPL4 .equ 0x0120 +__bapm4 .res.b 1 ;000121 +BAPM4 .equ 0x0121 +__baph4 .res.b 1 ;000122 +BAPH4 .equ 0x0122 +__dmacs4 .res.b 1 ;000123 +DMACS4 .equ 0x0123 +__ioa4 ; overlay symbol ;000124 +IOA4 .equ 0x0124 +__ioal4 .res.b 1 ;000124 +IOAL4 .equ 0x0124 +__ioah4 .res.b 1 ;000125 +IOAH4 .equ 0x0125 +__dct4 ; overlay symbol ;000126 +DCT4 .equ 0x0126 +__dctl4 .res.b 1 ;000126 +DCTL4 .equ 0x0126 +__dcth4 .res.b 1 ;000127 +DCTH4 .equ 0x0127 +__bapl5 .res.b 1 ;000128 +BAPL5 .equ 0x0128 +__bapm5 .res.b 1 ;000129 +BAPM5 .equ 0x0129 +__baph5 .res.b 1 ;00012A +BAPH5 .equ 0x012A +__dmacs5 .res.b 1 ;00012B +DMACS5 .equ 0x012B +__ioa5 ; overlay symbol ;00012C +IOA5 .equ 0x012C +__ioal5 .res.b 1 ;00012C +IOAL5 .equ 0x012C +__ioah5 .res.b 1 ;00012D +IOAH5 .equ 0x012D +__dct5 ; overlay symbol ;00012E +DCT5 .equ 0x012E +__dctl5 .res.b 1 ;00012E +DCTL5 .equ 0x012E +__dcth5 .res.b 1 ;00012F +DCTH5 .equ 0x012F + + .section IOXTND, DATA, locate=0x380 ; + .GLOBAL __disel0, __disel1, __disel2, __disel3, __disel4, __disel5 + .GLOBAL __dsr, __dsrl, __dsrh, __dssr, __dssrl, __dssrh + .GLOBAL __der, __derl, __derh, __icr, __ilr, __idx + .GLOBAL __tbr, __tbrl, __tbrh, __dirr, __nmi, __edsu2 + .GLOBAL __romm, __edsu, __pfcs0, __pfcs1, __pfcs2, __pfcs3 + .GLOBAL __pfal0, __pfam0, __pfah0, __pfal1, __pfam1, __pfah1 + .GLOBAL __pfal2, __pfam2, __pfah2, __pfal3, __pfam3, __pfah3 + .GLOBAL __pfal4, __pfam4, __pfah4, __pfal5, __pfam5, __pfah5 + .GLOBAL __pfal6, __pfam6, __pfah6, __pfal7, __pfam7, __pfah7 + .GLOBAL __pfd0, __pfdl0, __pfdh0, __pfd1, __pfdl1, __pfdh1 + .GLOBAL __pfd2, __pfdl2, __pfdh2, __pfd3, __pfdl3, __pfdh3 + .GLOBAL __pfd4, __pfdl4, __pfdh4, __pfd5, __pfdl5, __pfdh5 + .GLOBAL __pfd6, __pfdl6, __pfdh6, __pfd7, __pfdl7, __pfdh7 + .GLOBAL __mfmcs, __mfmtc, __mfmtcl, __mfmtch, __sfmcs, __sfmtc + .GLOBAL __sfmtcl, __sfmtch, __fmwc0, __fmwc1, __fmwc2, __fmwc3 + .GLOBAL __fmwc4, __fmwc5, __smcr, __cksr, __ckssr, __ckmr + .GLOBAL __ckfcr, __ckfcrl, __ckfcrh, __pllcr, __pllcrl, __pllcrh + .GLOBAL __rctcr, __mctcr, __rccsrc, __rcr, __rccsr, __wdtc + .GLOBAL __wdtcp, __coar, __cocr0, __cocr1, __cmcr, __cmpr + .GLOBAL __cmprl, __cmprh, __vrcr, __ddr00, __ddr01, __ddr02 + .GLOBAL __ddr03, __ddr04, __ddr05, __ddr06, __ddr07, __ddr08 + .GLOBAL __ddr09, __ddr10, __pier00, __pier01, __pier02, __pier03 + .GLOBAL __pier04, __pier05, __pier06, __pier07, __pier08, __pier09 + .GLOBAL __pier10, __pilr00, __pilr01, __pilr02, __pilr03, __pilr04 + .GLOBAL __pilr05, __pilr06, __pilr07, __pilr08, __pilr09, __pilr10 + .GLOBAL __epilr00, __epilr01, __epilr02, __epilr03, __epilr04, __epilr05 + .GLOBAL __epilr06, __epilr07, __epilr08, __epilr09, __epilr10, __podr00 + .GLOBAL __podr01, __podr02, __podr03, __podr04, __podr05, __podr06 + .GLOBAL __podr07, __podr08, __podr09, __podr10, __phdr08, __phdr09 + .GLOBAL __phdr10, __pucr00, __pucr01, __pucr02, __pucr03, __pucr04 + .GLOBAL __pucr05, __pucr06, __pucr07, __pucr08, __pucr09, __pucr10 + .GLOBAL __epsr00, __epsr01, __epsr02, __epsr03, __epsr04, __epsr05 + .GLOBAL __epsr06, __epsr07, __epsr08, __epsr09, __epsr10, __ader0 + .GLOBAL __ader1, __ader2, __prrr0, __prrr1, __prrr2, __prrr3 + .GLOBAL __prrr4, __prrr5, __prrr6, __prrr7, __prrr8, __prrr9 + .GLOBAL __wtbr0, __wtbrl0, __wtbrh0, __wtbr1, __wtsr, __wtmr + .GLOBAL __wthr, __wtcer, __wtcksr, __wtcr, __wtcrl, __wtcrh + .GLOBAL __cucr, __cutd, __cutdl, __cutdh, __cutr, __cutr2 + .GLOBAL __cutr2l, __cutr2h, __cutr1, __cutr1l, __cutr1h, __tmisr + .GLOBAL __smr7, __scr7, __tdr7, __rdr7, __ssr7, __eccr7 + .GLOBAL __escr7, __bgr7, __bgrl7, __bgrh7, __esir7, __smr8 + .GLOBAL __scr8, __tdr8, __rdr8, __ssr8, __eccr8, __escr8 + .GLOBAL __bgr8, __bgrl8, __bgrh8, __esir8, __smr9, __scr9 + .GLOBAL __tdr9, __rdr9, __ssr9, __eccr9, __escr9, __bgr9 + .GLOBAL __bgrl9, __bgrh9, __esir9, __acsr0, __aecsr0, __acsr1 + .GLOBAL __aecsr1, __ptmr6, __pcsr6, __pdut6, __pcn6, __pcnl6 + .GLOBAL __pcnh6, __ptmr7, __pcsr7, __pdut7, __pcn7, __pcnl7 + .GLOBAL __pcnh7, __gcn12, __gcn1l2, __gcn1h2, __gcn22, __gcn2l2 + .GLOBAL __gcn2h2, __ptmr8, __pcsr8, __pdut8, __pcn8, __pcnl8 + .GLOBAL __pcnh8, __ptmr9, __pcsr9, __pdut9, __pcn9, __pcnl9 + .GLOBAL __pcnh9, __ptmr10, __pcsr10, __pdut10, __pcn10, __pcnl10 + .GLOBAL __pcnh10, __ptmr11, __pcsr11, __pdut11, __pcn11, __pcnl11 + .GLOBAL __pcnh11, __gcn13, __gcn1l3, __gcn1h3, __gcn23, __gcn2l3 + .GLOBAL __gcn2h3, __ptmr12, __pcsr12, __pdut12, __pcn12, __pcnl12 + .GLOBAL __pcnh12, __ptmr13, __pcsr13, __pdut13, __pcn13, __pcnl13 + .GLOBAL __pcnh13, __ptmr14, __pcsr14, __pdut14, __pcn14, __pcnl14 + .GLOBAL __pcnh14, __ptmr15, __pcsr15, __pdut15, __pcn15, __pcnl15 + .GLOBAL __pcnh15, __prrr10, __prrr11, __prrr12, __prrr13, __eac0 + .GLOBAL __eacl0, __each0, __eac1, __eacl1, __each1, __eac2 + .GLOBAL __eacl2, __each2, __eac3, __eacl3, __each3, __eac4 + .GLOBAL __eacl4, __each4, __eac5, __eacl5, __each5, __eas2 + .GLOBAL __eas3, __eas4, __eas5, __ebm, __ebcf, __ebae0 + .GLOBAL __ebae1, __ebae2, __ebcs, __ctrlr0, __ctrlrl0, __ctrlrh0 + .GLOBAL __statr0, __statrl0, __statrh0, __errcnt0, __errcntl0, __errcnth0 + .GLOBAL __btr0, __btrl0, __btrh0, __intr0, __intrl0, __intrh0 + .GLOBAL __testr0, __testrl0, __testrh0, __brper0, __brperl0, __brperh0 + .GLOBAL __if1creq0, __if1creql0, __if1creqh0, __if1cmsk0, __if1cmskl0, __if1cmskh0 + .GLOBAL __if1msk0, __if1msk10, __if1msk1l0, __if1msk1h0, __if1msk20, __if1msk2l0 + .GLOBAL __if1msk2h0, __if1arb0, __if1arb10, __if1arb1l0, __if1arb1h0, __if1arb20 + .GLOBAL __if1arb2l0, __if1arb2h0, __if1mctr0, __if1mctrl0, __if1mctrh0, __if1dta0 + .GLOBAL __if1dta10, __if1dta1l0, __if1dta1h0, __if1dta20, __if1dta2l0, __if1dta2h0 + .GLOBAL __if1dtb0, __if1dtb10, __if1dtb1l0, __if1dtb1h0, __if1dtb20, __if1dtb2l0 + .GLOBAL __if1dtb2h0, __if2creq0, __if2creql0, __if2creqh0, __if2cmsk0, __if2cmskl0 + .GLOBAL __if2cmskh0, __if2msk0, __if2msk10, __if2msk1l0, __if2msk1h0, __if2msk20 + .GLOBAL __if2msk2l0, __if2msk2h0, __if2arb0, __if2arb10, __if2arb1l0, __if2arb1h0 + .GLOBAL __if2arb20, __if2arb2l0, __if2arb2h0, __if2mctr0, __if2mctrl0, __if2mctrh0 + .GLOBAL __if2dta0, __if2dta10, __if2dta1l0, __if2dta1h0, __if2dta20, __if2dta2l0 + .GLOBAL __if2dta2h0, __if2dtb0, __if2dtb10, __if2dtb1l0, __if2dtb1h0, __if2dtb20 + .GLOBAL __if2dtb2l0, __if2dtb2h0, __treqr0, __treqr10, __treqr1l0, __treqr1h0 + .GLOBAL __treqr20, __treqr2l0, __treqr2h0, __newdt0, __newdt10, __newdt1l0 + .GLOBAL __newdt1h0, __newdt20, __newdt2l0, __newdt2h0, __intpnd0, __intpnd10 + .GLOBAL __intpnd1l0, __intpnd1h0, __intpnd20, __intpnd2l0, __intpnd2h0, __msgval0 + .GLOBAL __msgval10, __msgval1l0, __msgval1h0, __msgval20, __msgval2l0, __msgval2h0 + .GLOBAL __coer0, __ctrlr1, __ctrlrl1, __ctrlrh1, __statr1, __statrl1 + .GLOBAL __statrh1, __errcnt1, __errcntl1, __errcnth1, __btr1, __btrl1 + .GLOBAL __btrh1, __intr1, __intrl1, __intrh1, __testr1, __testrl1 + .GLOBAL __testrh1, __brper1, __brperl1, __brperh1, __if1creq1, __if1creql1 + .GLOBAL __if1creqh1, __if1cmsk1, __if1cmskl1, __if1cmskh1, __if1msk1, __if1msk11 + .GLOBAL __if1msk1l1, __if1msk1h1, __if1msk21, __if1msk2l1, __if1msk2h1, __if1arb1 + .GLOBAL __if1arb11, __if1arb1l1, __if1arb1h1, __if1arb21, __if1arb2l1, __if1arb2h1 + .GLOBAL __if1mctr1, __if1mctrl1, __if1mctrh1, __if1dta1, __if1dta11, __if1dta1l1 + .GLOBAL __if1dta1h1, __if1dta21, __if1dta2l1, __if1dta2h1, __if1dtb1, __if1dtb11 + .GLOBAL __if1dtb1l1, __if1dtb1h1, __if1dtb21, __if1dtb2l1, __if1dtb2h1, __if2creq1 + .GLOBAL __if2creql1, __if2creqh1, __if2cmsk1, __if2cmskl1, __if2cmskh1, __if2msk1 + .GLOBAL __if2msk11, __if2msk1l1, __if2msk1h1, __if2msk21, __if2msk2l1, __if2msk2h1 + .GLOBAL __if2arb1, __if2arb11, __if2arb1l1, __if2arb1h1, __if2arb21, __if2arb2l1 + .GLOBAL __if2arb2h1, __if2mctr1, __if2mctrl1, __if2mctrh1, __if2dta1, __if2dta11 + .GLOBAL __if2dta1l1, __if2dta1h1, __if2dta21, __if2dta2l1, __if2dta2h1, __if2dtb1 + .GLOBAL __if2dtb11, __if2dtb1l1, __if2dtb1h1, __if2dtb21, __if2dtb2l1, __if2dtb2h1 + .GLOBAL __treqr1, __treqr11, __treqr1l1, __treqr1h1, __treqr21, __treqr2l1 + .GLOBAL __treqr2h1, __newdt1, __newdt11, __newdt1l1, __newdt1h1, __newdt21 + .GLOBAL __newdt2l1, __newdt2h1, __intpnd1, __intpnd11, __intpnd1l1, __intpnd1h1 + .GLOBAL __intpnd21, __intpnd2l1, __intpnd2h1, __msgval1, __msgval11, __msgval1l1 + .GLOBAL __msgval1h1, __msgval21, __msgval2l1, __msgval2h1, __coer1 + +__disel0 .res.b 1 ;000380 +DISEL0 .equ 0x0380 +__disel1 .res.b 1 ;000381 +DISEL1 .equ 0x0381 +__disel2 .res.b 1 ;000382 +DISEL2 .equ 0x0382 +__disel3 .res.b 1 ;000383 +DISEL3 .equ 0x0383 +__disel4 .res.b 1 ;000384 +DISEL4 .equ 0x0384 +__disel5 .res.b 1 ;000385 +DISEL5 .equ 0x0385 + .org 0x000390 +__dsr ; overlay symbol ;000390 +DSR .equ 0x0390 +__dsrl .res.b 1 ;000390 +DSRL .equ 0x0390 +__dsrh .res.b 1 ;000391 +DSRH .equ 0x0391 +__dssr ; overlay symbol ;000392 +DSSR .equ 0x0392 +__dssrl .res.b 1 ;000392 +DSSRL .equ 0x0392 +__dssrh .res.b 1 ;000393 +DSSRH .equ 0x0393 +__der ; overlay symbol ;000394 +DER .equ 0x0394 +__derl .res.b 1 ;000394 +DERL .equ 0x0394 +__derh .res.b 1 ;000395 +DERH .equ 0x0395 + .org 0x0003a0 +__icr ; overlay symbol ;0003A0 +ICR .equ 0x03A0 +__ilr .res.b 1 ;0003A0 +ILR .equ 0x03A0 +__idx .res.b 1 ;0003A1 +IDX .equ 0x03A1 +__tbr ; overlay symbol ;0003A2 +TBR .equ 0x03A2 +__tbrl .res.b 1 ;0003A2 +TBRL .equ 0x03A2 +__tbrh .res.b 1 ;0003A3 +TBRH .equ 0x03A3 +__dirr .res.b 1 ;0003A4 +DIRR .equ 0x03A4 +__nmi .res.b 1 ;0003A5 +NMI .equ 0x03A5 + .org 0x0003ac +__edsu2 .res.b 2 ;0003AC +EDSU2 .equ 0x03AC +__romm .res.b 1 ;0003AE +ROMM .equ 0x03AE +__edsu .res.b 1 ;0003AF +EDSU .equ 0x03AF +__pfcs0 .res.b 2 ;0003B0 +PFCS0 .equ 0x03B0 +__pfcs1 .res.b 2 ;0003B2 +PFCS1 .equ 0x03B2 +__pfcs2 .res.b 2 ;0003B4 +PFCS2 .equ 0x03B4 +__pfcs3 .res.b 2 ;0003B6 +PFCS3 .equ 0x03B6 +__pfal0 .res.b 1 ;0003B8 +PFAL0 .equ 0x03B8 +__pfam0 .res.b 1 ;0003B9 +PFAM0 .equ 0x03B9 +__pfah0 .res.b 1 ;0003BA +PFAH0 .equ 0x03BA +__pfal1 .res.b 1 ;0003BB +PFAL1 .equ 0x03BB +__pfam1 .res.b 1 ;0003BC +PFAM1 .equ 0x03BC +__pfah1 .res.b 1 ;0003BD +PFAH1 .equ 0x03BD +__pfal2 .res.b 1 ;0003BE +PFAL2 .equ 0x03BE +__pfam2 .res.b 1 ;0003BF +PFAM2 .equ 0x03BF +__pfah2 .res.b 1 ;0003C0 +PFAH2 .equ 0x03C0 +__pfal3 .res.b 1 ;0003C1 +PFAL3 .equ 0x03C1 +__pfam3 .res.b 1 ;0003C2 +PFAM3 .equ 0x03C2 +__pfah3 .res.b 1 ;0003C3 +PFAH3 .equ 0x03C3 +__pfal4 .res.b 1 ;0003C4 +PFAL4 .equ 0x03C4 +__pfam4 .res.b 1 ;0003C5 +PFAM4 .equ 0x03C5 +__pfah4 .res.b 1 ;0003C6 +PFAH4 .equ 0x03C6 +__pfal5 .res.b 1 ;0003C7 +PFAL5 .equ 0x03C7 +__pfam5 .res.b 1 ;0003C8 +PFAM5 .equ 0x03C8 +__pfah5 .res.b 1 ;0003C9 +PFAH5 .equ 0x03C9 +__pfal6 .res.b 1 ;0003CA +PFAL6 .equ 0x03CA +__pfam6 .res.b 1 ;0003CB +PFAM6 .equ 0x03CB +__pfah6 .res.b 1 ;0003CC +PFAH6 .equ 0x03CC +__pfal7 .res.b 1 ;0003CD +PFAL7 .equ 0x03CD +__pfam7 .res.b 1 ;0003CE +PFAM7 .equ 0x03CE +__pfah7 .res.b 1 ;0003CF +PFAH7 .equ 0x03CF +__pfd0 ; overlay symbol ;0003D0 +PFD0 .equ 0x03D0 +__pfdl0 .res.b 1 ;0003D0 +PFDL0 .equ 0x03D0 +__pfdh0 .res.b 1 ;0003D1 +PFDH0 .equ 0x03D1 +__pfd1 ; overlay symbol ;0003D2 +PFD1 .equ 0x03D2 +__pfdl1 .res.b 1 ;0003D2 +PFDL1 .equ 0x03D2 +__pfdh1 .res.b 1 ;0003D3 +PFDH1 .equ 0x03D3 +__pfd2 ; overlay symbol ;0003D4 +PFD2 .equ 0x03D4 +__pfdl2 .res.b 1 ;0003D4 +PFDL2 .equ 0x03D4 +__pfdh2 .res.b 1 ;0003D5 +PFDH2 .equ 0x03D5 +__pfd3 ; overlay symbol ;0003D6 +PFD3 .equ 0x03D6 +__pfdl3 .res.b 1 ;0003D6 +PFDL3 .equ 0x03D6 +__pfdh3 .res.b 1 ;0003D7 +PFDH3 .equ 0x03D7 +__pfd4 ; overlay symbol ;0003D8 +PFD4 .equ 0x03D8 +__pfdl4 .res.b 1 ;0003D8 +PFDL4 .equ 0x03D8 +__pfdh4 .res.b 1 ;0003D9 +PFDH4 .equ 0x03D9 +__pfd5 ; overlay symbol ;0003DA +PFD5 .equ 0x03DA +__pfdl5 .res.b 1 ;0003DA +PFDL5 .equ 0x03DA +__pfdh5 .res.b 1 ;0003DB +PFDH5 .equ 0x03DB +__pfd6 ; overlay symbol ;0003DC +PFD6 .equ 0x03DC +__pfdl6 .res.b 1 ;0003DC +PFDL6 .equ 0x03DC +__pfdh6 .res.b 1 ;0003DD +PFDH6 .equ 0x03DD +__pfd7 ; overlay symbol ;0003DE +PFD7 .equ 0x03DE +__pfdl7 .res.b 1 ;0003DE +PFDL7 .equ 0x03DE +__pfdh7 .res.b 1 ;0003DF +PFDH7 .equ 0x03DF + .org 0x0003f1 +__mfmcs .res.b 1 ;0003F1 +MFMCS .equ 0x03F1 +__mfmtc ; overlay symbol ;0003F2 +MFMTC .equ 0x03F2 +__mfmtcl .res.b 1 ;0003F2 +MFMTCL .equ 0x03F2 +__mfmtch .res.b 1 ;0003F3 +MFMTCH .equ 0x03F3 + .org 0x0003f5 +__sfmcs .res.b 1 ;0003F5 +SFMCS .equ 0x03F5 +__sfmtc ; overlay symbol ;0003F6 +SFMTC .equ 0x03F6 +__sfmtcl .res.b 1 ;0003F6 +SFMTCL .equ 0x03F6 +__sfmtch .res.b 1 ;0003F7 +SFMTCH .equ 0x03F7 +__fmwc0 .res.b 1 ;0003F8 +FMWC0 .equ 0x03F8 +__fmwc1 .res.b 1 ;0003F9 +FMWC1 .equ 0x03F9 +__fmwc2 .res.b 1 ;0003FA +FMWC2 .equ 0x03FA +__fmwc3 .res.b 1 ;0003FB +FMWC3 .equ 0x03FB +__fmwc4 .res.b 1 ;0003FC +FMWC4 .equ 0x03FC +__fmwc5 .res.b 1 ;0003FD +FMWC5 .equ 0x03FD + .org 0x000400 +__smcr .res.b 1 ;000400 +SMCR .equ 0x0400 +__cksr .res.b 1 ;000401 +CKSR .equ 0x0401 +__ckssr .res.b 1 ;000402 +CKSSR .equ 0x0402 +__ckmr .res.b 1 ;000403 +CKMR .equ 0x0403 +__ckfcr ; overlay symbol ;000404 +CKFCR .equ 0x0404 +__ckfcrl .res.b 1 ;000404 +CKFCRL .equ 0x0404 +__ckfcrh .res.b 1 ;000405 +CKFCRH .equ 0x0405 +__pllcr ; overlay symbol ;000406 +PLLCR .equ 0x0406 +__pllcrl .res.b 1 ;000406 +PLLCRL .equ 0x0406 +__pllcrh .res.b 1 ;000407 +PLLCRH .equ 0x0407 +__rctcr .res.b 1 ;000408 +RCTCR .equ 0x0408 +__mctcr .res.b 1 ;000409 +MCTCR .equ 0x0409 + .org 0x00040b +__rccsrc .res.b 1 ;00040B +RCCSRC .equ 0x040B +__rcr .res.b 1 ;00040C +RCR .equ 0x040C +__rccsr .res.b 1 ;00040D +RCCSR .equ 0x040D +__wdtc .res.b 1 ;00040E +WDTC .equ 0x040E +__wdtcp .res.b 1 ;00040F +WDTCP .equ 0x040F + .org 0x000415 +__coar .res.b 1 ;000415 +COAR .equ 0x0415 +__cocr0 .res.b 1 ;000416 +COCR0 .equ 0x0416 +__cocr1 .res.b 1 ;000417 +COCR1 .equ 0x0417 +__cmcr .res.b 1 ;000418 +CMCR .equ 0x0418 + .org 0x00041a +__cmpr ; overlay symbol ;00041A +CMPR .equ 0x041A +__cmprl .res.b 1 ;00041A +CMPRL .equ 0x041A +__cmprh .res.b 1 ;00041B +CMPRH .equ 0x041B + .org 0x00042c +__vrcr .res.b 1 ;00042C +VRCR .equ 0x042C + .org 0x000430 +__ddr00 .res.b 1 ;000430 +DDR00 .equ 0x0430 +__ddr01 .res.b 1 ;000431 +DDR01 .equ 0x0431 +__ddr02 .res.b 1 ;000432 +DDR02 .equ 0x0432 +__ddr03 .res.b 1 ;000433 +DDR03 .equ 0x0433 +__ddr04 .res.b 1 ;000434 +DDR04 .equ 0x0434 +__ddr05 .res.b 1 ;000435 +DDR05 .equ 0x0435 +__ddr06 .res.b 1 ;000436 +DDR06 .equ 0x0436 +__ddr07 .res.b 1 ;000437 +DDR07 .equ 0x0437 +__ddr08 .res.b 1 ;000438 +DDR08 .equ 0x0438 +__ddr09 .res.b 1 ;000439 +DDR09 .equ 0x0439 +__ddr10 .res.b 1 ;00043A +DDR10 .equ 0x043A + .org 0x000444 +__pier00 .res.b 1 ;000444 +PIER00 .equ 0x0444 +__pier01 .res.b 1 ;000445 +PIER01 .equ 0x0445 +__pier02 .res.b 1 ;000446 +PIER02 .equ 0x0446 +__pier03 .res.b 1 ;000447 +PIER03 .equ 0x0447 +__pier04 .res.b 1 ;000448 +PIER04 .equ 0x0448 +__pier05 .res.b 1 ;000449 +PIER05 .equ 0x0449 +__pier06 .res.b 1 ;00044A +PIER06 .equ 0x044A +__pier07 .res.b 1 ;00044B +PIER07 .equ 0x044B +__pier08 .res.b 1 ;00044C +PIER08 .equ 0x044C +__pier09 .res.b 1 ;00044D +PIER09 .equ 0x044D +__pier10 .res.b 1 ;00044E +PIER10 .equ 0x044E + .org 0x000458 +__pilr00 .res.b 1 ;000458 +PILR00 .equ 0x0458 +__pilr01 .res.b 1 ;000459 +PILR01 .equ 0x0459 +__pilr02 .res.b 1 ;00045A +PILR02 .equ 0x045A +__pilr03 .res.b 1 ;00045B +PILR03 .equ 0x045B +__pilr04 .res.b 1 ;00045C +PILR04 .equ 0x045C +__pilr05 .res.b 1 ;00045D +PILR05 .equ 0x045D +__pilr06 .res.b 1 ;00045E +PILR06 .equ 0x045E +__pilr07 .res.b 1 ;00045F +PILR07 .equ 0x045F +__pilr08 .res.b 1 ;000460 +PILR08 .equ 0x0460 +__pilr09 .res.b 1 ;000461 +PILR09 .equ 0x0461 +__pilr10 .res.b 1 ;000462 +PILR10 .equ 0x0462 + .org 0x00046C +__epilr00 .res.b 1 ;00046C +EPILR00 .equ 0x046C +__epilr01 .res.b 1 ;00046D +EPILR01 .equ 0x046D +__epilr02 .res.b 1 ;00046E +EPILR02 .equ 0x046E +__epilr03 .res.b 1 ;00046F +EPILR03 .equ 0x046F +__epilr04 .res.b 1 ;000470 +EPILR04 .equ 0x0470 +__epilr05 .res.b 1 ;000471 +EPILR05 .equ 0x0471 +__epilr06 .res.b 1 ;000472 +EPILR06 .equ 0x0472 +__epilr07 .res.b 1 ;000473 +EPILR07 .equ 0x0473 +__epilr08 .res.b 1 ;000474 +EPILR08 .equ 0x0474 +__epilr09 .res.b 1 ;000475 +EPILR09 .equ 0x0475 +__epilr10 .res.b 1 ;000476 +EPILR10 .equ 0x0476 + .org 0x000480 +__podr00 .res.b 1 ;000480 +PODR00 .equ 0x0480 +__podr01 .res.b 1 ;000481 +PODR01 .equ 0x0481 +__podr02 .res.b 1 ;000482 +PODR02 .equ 0x0482 +__podr03 .res.b 1 ;000483 +PODR03 .equ 0x0483 +__podr04 .res.b 1 ;000484 +PODR04 .equ 0x0484 +__podr05 .res.b 1 ;000485 +PODR05 .equ 0x0485 +__podr06 .res.b 1 ;000486 +PODR06 .equ 0x0486 +__podr07 .res.b 1 ;000487 +PODR07 .equ 0x0487 +__podr08 .res.b 1 ;000488 +PODR08 .equ 0x0488 +__podr09 .res.b 1 ;000489 +PODR09 .equ 0x0489 +__podr10 .res.b 1 ;00048A +PODR10 .equ 0x048A + .org 0x00049C +__phdr08 .res.b 1 ;00049C +PHDR08 .equ 0x049C +__phdr09 .res.b 1 ;00049D +PHDR09 .equ 0x049D +__phdr10 .res.b 1 ;00049E +PHDR10 .equ 0x049E + .org 0x0004A8 +__pucr00 .res.b 1 ;0004A8 +PUCR00 .equ 0x04A8 +__pucr01 .res.b 1 ;0004A9 +PUCR01 .equ 0x04A9 +__pucr02 .res.b 1 ;0004AA +PUCR02 .equ 0x04AA +__pucr03 .res.b 1 ;0004AB +PUCR03 .equ 0x04AB +__pucr04 .res.b 1 ;0004AC +PUCR04 .equ 0x04AC +__pucr05 .res.b 1 ;0004AD +PUCR05 .equ 0x04AD +__pucr06 .res.b 1 ;0004AE +PUCR06 .equ 0x04AE +__pucr07 .res.b 1 ;0004AF +PUCR07 .equ 0x04AF +__pucr08 .res.b 1 ;0004B0 +PUCR08 .equ 0x04B0 +__pucr09 .res.b 1 ;0004B1 +PUCR09 .equ 0x04B1 +__pucr10 .res.b 1 ;0004B2 +PUCR10 .equ 0x04B2 + .org 0x0004BC +__epsr00 .res.b 1 ;0004BC +EPSR00 .equ 0x04BC +__epsr01 .res.b 1 ;0004BD +EPSR01 .equ 0x04BD +__epsr02 .res.b 1 ;0004BE +EPSR02 .equ 0x04BE +__epsr03 .res.b 1 ;0004BF +EPSR03 .equ 0x04BF +__epsr04 .res.b 1 ;0004C0 +EPSR04 .equ 0x04C0 +__epsr05 .res.b 1 ;0004C1 +EPSR05 .equ 0x04C1 +__epsr06 .res.b 1 ;0004C2 +EPSR06 .equ 0x04C2 +__epsr07 .res.b 1 ;0004C3 +EPSR07 .equ 0x04C3 +__epsr08 .res.b 1 ;0004C4 +EPSR08 .equ 0x04C4 +__epsr09 .res.b 1 ;0004C5 +EPSR09 .equ 0x04C5 +__epsr10 .res.b 1 ;0004C6 +EPSR10 .equ 0x04C6 + .org 0x0004d0 +__ader0 .res.b 1 ;0004D0 +ADER0 .equ 0x04D0 +__ader1 .res.b 1 ;0004D1 +ADER1 .equ 0x04D1 +__ader2 .res.b 1 ;0004D2 +ADER2 .equ 0x04D2 + .org 0x0004d6 +__prrr0 .res.b 1 ;0004D6 +PRRR0 .equ 0x04D6 +__prrr1 .res.b 1 ;0004D7 +PRRR1 .equ 0x04D7 +__prrr2 .res.b 1 ;0004D8 +PRRR2 .equ 0x04D8 +__prrr3 .res.b 1 ;0004D9 +PRRR3 .equ 0x04D9 +__prrr4 .res.b 1 ;0004DA +PRRR4 .equ 0x04DA +__prrr5 .res.b 1 ;0004DB +PRRR5 .equ 0x04DB +__prrr6 .res.b 1 ;0004DC +PRRR6 .equ 0x04DC +__prrr7 .res.b 1 ;0004DD +PRRR7 .equ 0x04DD +__prrr8 .res.b 1 ;0004DE +PRRR8 .equ 0x04DE +__prrr9 .res.b 1 ;0004DF +PRRR9 .equ 0x04DF +__wtbr0 ; overlay symbol ;0004E0 +WTBR0 .equ 0x04E0 +__wtbrl0 .res.b 1 ;0004E0 +WTBRL0 .equ 0x04E0 +__wtbrh0 .res.b 1 ;0004E1 +WTBRH0 .equ 0x04E1 +__wtbr1 .res.b 1 ;0004E2 +WTBR1 .equ 0x04E2 +__wtsr .res.b 1 ;0004E3 +WTSR .equ 0x04E3 +__wtmr .res.b 1 ;0004E4 +WTMR .equ 0x04E4 +__wthr .res.b 1 ;0004E5 +WTHR .equ 0x04E5 +__wtcer .res.b 1 ;0004E6 +WTCER .equ 0x04E6 +__wtcksr .res.b 1 ;0004E7 +WTCKSR .equ 0x04E7 +__wtcr ; overlay symbol ;0004E8 +WTCR .equ 0x04E8 +__wtcrl .res.b 1 ;0004E8 +WTCRL .equ 0x04E8 +__wtcrh .res.b 1 ;0004E9 +WTCRH .equ 0x04E9 +__cucr .res.b 1 ;0004EA +CUCR .equ 0x04EA + .org 0x0004ec +__cutd ; overlay symbol ;0004EC +CUTD .equ 0x04EC +__cutdl .res.b 1 ;0004EC +CUTDL .equ 0x04EC +__cutdh .res.b 1 ;0004ED +CUTDH .equ 0x04ED +__cutr ; overlay symbol ;0004EE +CUTR .equ 0x04EE +__cutr2 ; overlay symbol ;0004EE +CUTR2 .equ 0x04EE +__cutr2l .res.b 1 ;0004EE +CUTR2L .equ 0x04EE +__cutr2h .res.b 1 ;0004EF +CUTR2H .equ 0x04EF +__cutr1 ; overlay symbol ;0004F0 +CUTR1 .equ 0x04F0 +__cutr1l .res.b 1 ;0004F0 +CUTR1L .equ 0x04F0 +__cutr1h .res.b 1 ;0004F1 +CUTR1H .equ 0x04F1 + .org 0x0004fa +__tmisr .res.b 1 ;0004FA +TMISR .equ 0x04FA + .org 0x00053e +__smr7 .res.b 1 ;00053E +SMR7 .equ 0x053E +__scr7 .res.b 1 ;00053F +SCR7 .equ 0x053F +__tdr7 ; overlay symbol ;000540 +TDR7 .equ 0x0540 +__rdr7 .res.b 1 ;000540 +RDR7 .equ 0x0540 +__ssr7 .res.b 1 ;000541 +SSR7 .equ 0x0541 +__eccr7 .res.b 1 ;000542 +ECCR7 .equ 0x0542 +__escr7 .res.b 1 ;000543 +ESCR7 .equ 0x0543 +__bgr7 ; overlay symbol ;000544 +BGR7 .equ 0x0544 +__bgrl7 .res.b 1 ;000544 +BGRL7 .equ 0x0544 +__bgrh7 .res.b 1 ;000545 +BGRH7 .equ 0x0545 +__esir7 .res.b 1 ;000546 +ESIR7 .equ 0x0546 + .org 0x000548 +__smr8 .res.b 1 ;000548 +SMR8 .equ 0x0548 +__scr8 .res.b 1 ;000549 +SCR8 .equ 0x0549 +__tdr8 ; overlay symbol ;00054A +TDR8 .equ 0x054A +__rdr8 .res.b 1 ;00054A +RDR8 .equ 0x054A +__ssr8 .res.b 1 ;00054B +SSR8 .equ 0x054B +__eccr8 .res.b 1 ;00054C +ECCR8 .equ 0x054C +__escr8 .res.b 1 ;00054D +ESCR8 .equ 0x054D +__bgr8 ; overlay symbol ;00054E +BGR8 .equ 0x054E +__bgrl8 .res.b 1 ;00054E +BGRL8 .equ 0x054E +__bgrh8 .res.b 1 ;00054F +BGRH8 .equ 0x054F +__esir8 .res.b 1 ;000550 +ESIR8 .equ 0x0550 + .org 0x000552 +__smr9 .res.b 1 ;000552 +SMR9 .equ 0x0552 +__scr9 .res.b 1 ;000553 +SCR9 .equ 0x0553 +__tdr9 ; overlay symbol ;000554 +TDR9 .equ 0x0554 +__rdr9 .res.b 1 ;000554 +RDR9 .equ 0x0554 +__ssr9 .res.b 1 ;000555 +SSR9 .equ 0x0555 +__eccr9 .res.b 1 ;000556 +ECCR9 .equ 0x0556 +__escr9 .res.b 1 ;000557 +ESCR9 .equ 0x0557 +__bgr9 ; overlay symbol ;000558 +BGR9 .equ 0x0558 +__bgrl9 .res.b 1 ;000558 +BGRL9 .equ 0x0558 +__bgrh9 .res.b 1 ;000559 +BGRH9 .equ 0x0559 +__esir9 .res.b 1 ;00055A +ESIR9 .equ 0x055A + .org 0x000560 +__acsr0 .res.b 1 ;000560 +ACSR0 .equ 0x0560 +__aecsr0 .res.b 1 ;000561 +AECSR0 .equ 0x0561 +__acsr1 .res.b 1 ;000562 +ACSR1 .equ 0x0562 +__aecsr1 .res.b 1 ;000563 +AECSR1 .equ 0x0563 +__ptmr6 .res.b 2 ;000564 +PTMR6 .equ 0x0564 +__pcsr6 .res.b 2 ;000566 +PCSR6 .equ 0x0566 +__pdut6 .res.b 2 ;000568 +PDUT6 .equ 0x0568 +__pcn6 ; overlay symbol ;00056A +PCN6 .equ 0x056A +__pcnl6 .res.b 1 ;00056A +PCNL6 .equ 0x056A +__pcnh6 .res.b 1 ;00056B +PCNH6 .equ 0x056B +__ptmr7 .res.b 2 ;00056C +PTMR7 .equ 0x056C +__pcsr7 .res.b 2 ;00056E +PCSR7 .equ 0x056E +__pdut7 .res.b 2 ;000570 +PDUT7 .equ 0x0570 +__pcn7 ; overlay symbol ;000572 +PCN7 .equ 0x0572 +__pcnl7 .res.b 1 ;000572 +PCNL7 .equ 0x0572 +__pcnh7 .res.b 1 ;000573 +PCNH7 .equ 0x0573 +__gcn12 ; overlay symbol ;000574 +GCN12 .equ 0x0574 +__gcn1l2 .res.b 1 ;000574 +GCN1L2 .equ 0x0574 +__gcn1h2 .res.b 1 ;000575 +GCN1H2 .equ 0x0575 +__gcn22 ; overlay symbol ;000576 +GCN22 .equ 0x0576 +__gcn2l2 .res.b 1 ;000576 +GCN2L2 .equ 0x0576 +__gcn2h2 .res.b 1 ;000577 +GCN2H2 .equ 0x0577 +__ptmr8 .res.b 2 ;000578 +PTMR8 .equ 0x0578 +__pcsr8 .res.b 2 ;00057A +PCSR8 .equ 0x057A +__pdut8 .res.b 2 ;00057C +PDUT8 .equ 0x057C +__pcn8 ; overlay symbol ;00057E +PCN8 .equ 0x057E +__pcnl8 .res.b 1 ;00057E +PCNL8 .equ 0x057E +__pcnh8 .res.b 1 ;00057F +PCNH8 .equ 0x057F +__ptmr9 .res.b 2 ;000580 +PTMR9 .equ 0x0580 +__pcsr9 .res.b 2 ;000582 +PCSR9 .equ 0x0582 +__pdut9 .res.b 2 ;000584 +PDUT9 .equ 0x0584 +__pcn9 ; overlay symbol ;000586 +PCN9 .equ 0x0586 +__pcnl9 .res.b 1 ;000586 +PCNL9 .equ 0x0586 +__pcnh9 .res.b 1 ;000587 +PCNH9 .equ 0x0587 +__ptmr10 .res.b 2 ;000588 +PTMR10 .equ 0x0588 +__pcsr10 .res.b 2 ;00058A +PCSR10 .equ 0x058A +__pdut10 .res.b 2 ;00058C +PDUT10 .equ 0x058C +__pcn10 ; overlay symbol ;00058E +PCN10 .equ 0x058E +__pcnl10 .res.b 1 ;00058E +PCNL10 .equ 0x058E +__pcnh10 .res.b 1 ;00058F +PCNH10 .equ 0x058F +__ptmr11 .res.b 2 ;000590 +PTMR11 .equ 0x0590 +__pcsr11 .res.b 2 ;000592 +PCSR11 .equ 0x0592 +__pdut11 .res.b 2 ;000594 +PDUT11 .equ 0x0594 +__pcn11 ; overlay symbol ;000596 +PCN11 .equ 0x0596 +__pcnl11 .res.b 1 ;000596 +PCNL11 .equ 0x0596 +__pcnh11 .res.b 1 ;000597 +PCNH11 .equ 0x0597 +__gcn13 ; overlay symbol ;000598 +GCN13 .equ 0x0598 +__gcn1l3 .res.b 1 ;000598 +GCN1L3 .equ 0x0598 +__gcn1h3 .res.b 1 ;000599 +GCN1H3 .equ 0x0599 +__gcn23 ; overlay symbol ;00059A +GCN23 .equ 0x059A +__gcn2l3 .res.b 1 ;00059A +GCN2L3 .equ 0x059A +__gcn2h3 .res.b 1 ;00059B +GCN2H3 .equ 0x059B +__ptmr12 .res.b 2 ;00059C +PTMR12 .equ 0x059C +__pcsr12 .res.b 2 ;00059E +PCSR12 .equ 0x059E +__pdut12 .res.b 2 ;0005A0 +PDUT12 .equ 0x05A0 +__pcn12 ; overlay symbol ;0005A2 +PCN12 .equ 0x05A2 +__pcnl12 .res.b 1 ;0005A2 +PCNL12 .equ 0x05A2 +__pcnh12 .res.b 1 ;0005A3 +PCNH12 .equ 0x05A3 +__ptmr13 .res.b 2 ;0005A4 +PTMR13 .equ 0x05A4 +__pcsr13 .res.b 2 ;0005A6 +PCSR13 .equ 0x05A6 +__pdut13 .res.b 2 ;0005A8 +PDUT13 .equ 0x05A8 +__pcn13 ; overlay symbol ;0005AA +PCN13 .equ 0x05AA +__pcnl13 .res.b 1 ;0005AA +PCNL13 .equ 0x05AA +__pcnh13 .res.b 1 ;0005AB +PCNH13 .equ 0x05AB +__ptmr14 .res.b 2 ;0005AC +PTMR14 .equ 0x05AC +__pcsr14 .res.b 2 ;0005AE +PCSR14 .equ 0x05AE +__pdut14 .res.b 2 ;0005B0 +PDUT14 .equ 0x05B0 +__pcn14 ; overlay symbol ;0005B2 +PCN14 .equ 0x05B2 +__pcnl14 .res.b 1 ;0005B2 +PCNL14 .equ 0x05B2 +__pcnh14 .res.b 1 ;0005B3 +PCNH14 .equ 0x05B3 +__ptmr15 .res.b 2 ;0005B4 +PTMR15 .equ 0x05B4 +__pcsr15 .res.b 2 ;0005B6 +PCSR15 .equ 0x05B6 +__pdut15 .res.b 2 ;0005B8 +PDUT15 .equ 0x05B8 +__pcn15 ; overlay symbol ;0005BA +PCN15 .equ 0x05BA +__pcnl15 .res.b 1 ;0005BA +PCNL15 .equ 0x05BA +__pcnh15 .res.b 1 ;0005BB +PCNH15 .equ 0x05BB + .org 0x000660 +__prrr10 .res.b 1 ;000660 +PRRR10 .equ 0x0660 +__prrr11 .res.b 1 ;000661 +PRRR11 .equ 0x0661 +__prrr12 .res.b 1 ;000662 +PRRR12 .equ 0x0662 +__prrr13 .res.b 1 ;000663 +PRRR13 .equ 0x0663 + .org 0x0006e0 +__eac0 ; overlay symbol ;0006E0 +EAC0 .equ 0x06E0 +__eacl0 .res.b 1 ;0006E0 +EACL0 .equ 0x06E0 +__each0 .res.b 1 ;0006E1 +EACH0 .equ 0x06E1 +__eac1 ; overlay symbol ;0006E2 +EAC1 .equ 0x06E2 +__eacl1 .res.b 1 ;0006E2 +EACL1 .equ 0x06E2 +__each1 .res.b 1 ;0006E3 +EACH1 .equ 0x06E3 +__eac2 ; overlay symbol ;0006E4 +EAC2 .equ 0x06E4 +__eacl2 .res.b 1 ;0006E4 +EACL2 .equ 0x06E4 +__each2 .res.b 1 ;0006E5 +EACH2 .equ 0x06E5 +__eac3 ; overlay symbol ;0006E6 +EAC3 .equ 0x06E6 +__eacl3 .res.b 1 ;0006E6 +EACL3 .equ 0x06E6 +__each3 .res.b 1 ;0006E7 +EACH3 .equ 0x06E7 +__eac4 ; overlay symbol ;0006E8 +EAC4 .equ 0x06E8 +__eacl4 .res.b 1 ;0006E8 +EACL4 .equ 0x06E8 +__each4 .res.b 1 ;0006E9 +EACH4 .equ 0x06E9 +__eac5 ; overlay symbol ;0006EA +EAC5 .equ 0x06EA +__eacl5 .res.b 1 ;0006EA +EACL5 .equ 0x06EA +__each5 .res.b 1 ;0006EB +EACH5 .equ 0x06EB +__eas2 .res.b 1 ;0006EC +EAS2 .equ 0x06EC +__eas3 .res.b 1 ;0006ED +EAS3 .equ 0x06ED +__eas4 .res.b 1 ;0006EE +EAS4 .equ 0x06EE +__eas5 .res.b 1 ;0006EF +EAS5 .equ 0x06EF +__ebm .res.b 1 ;0006F0 +EBM .equ 0x06F0 +__ebcf .res.b 1 ;0006F1 +EBCF .equ 0x06F1 +__ebae0 .res.b 1 ;0006F2 +EBAE0 .equ 0x06F2 +__ebae1 .res.b 1 ;0006F3 +EBAE1 .equ 0x06F3 +__ebae2 .res.b 1 ;0006F4 +EBAE2 .equ 0x06F4 +__ebcs .res.b 1 ;0006F5 +EBCS .equ 0x06F5 + .org 0x000700 +__ctrlr0 ; overlay symbol ;000700 +CTRLR0 .equ 0x0700 +__ctrlrl0 .res.b 1 ;000700 +CTRLRL0 .equ 0x0700 +__ctrlrh0 .res.b 1 ;000701 +CTRLRH0 .equ 0x0701 +__statr0 ; overlay symbol ;000702 +STATR0 .equ 0x0702 +__statrl0 .res.b 1 ;000702 +STATRL0 .equ 0x0702 +__statrh0 .res.b 1 ;000703 +STATRH0 .equ 0x0703 +__errcnt0 ; overlay symbol ;000704 +ERRCNT0 .equ 0x0704 +__errcntl0 .res.b 1 ;000704 +ERRCNTL0 .equ 0x0704 +__errcnth0 .res.b 1 ;000705 +ERRCNTH0 .equ 0x0705 +__btr0 ; overlay symbol ;000706 +BTR0 .equ 0x0706 +__btrl0 .res.b 1 ;000706 +BTRL0 .equ 0x0706 +__btrh0 .res.b 1 ;000707 +BTRH0 .equ 0x0707 +__intr0 ; overlay symbol ;000708 +INTR0 .equ 0x0708 +__intrl0 .res.b 1 ;000708 +INTRL0 .equ 0x0708 +__intrh0 .res.b 1 ;000709 +INTRH0 .equ 0x0709 +__testr0 ; overlay symbol ;00070A +TESTR0 .equ 0x070A +__testrl0 .res.b 1 ;00070A +TESTRL0 .equ 0x070A +__testrh0 .res.b 1 ;00070B +TESTRH0 .equ 0x070B +__brper0 ; overlay symbol ;00070C +BRPER0 .equ 0x070C +__brperl0 .res.b 1 ;00070C +BRPERL0 .equ 0x070C +__brperh0 .res.b 1 ;00070D +BRPERH0 .equ 0x070D + .org 0x000710 +__if1creq0 ; overlay symbol ;000710 +IF1CREQ0 .equ 0x0710 +__if1creql0 .res.b 1 ;000710 +IF1CREQL0 .equ 0x0710 +__if1creqh0 .res.b 1 ;000711 +IF1CREQH0 .equ 0x0711 +__if1cmsk0 ; overlay symbol ;000712 +IF1CMSK0 .equ 0x0712 +__if1cmskl0 .res.b 1 ;000712 +IF1CMSKL0 .equ 0x0712 +__if1cmskh0 .res.b 1 ;000713 +IF1CMSKH0 .equ 0x0713 +__if1msk0 ; overlay symbol ;000714 +IF1MSK0 .equ 0x0714 +__if1msk10 ; overlay symbol ;000714 +IF1MSK10 .equ 0x0714 +__if1msk1l0 .res.b 1 ;000714 +IF1MSK1L0 .equ 0x0714 +__if1msk1h0 .res.b 1 ;000715 +IF1MSK1H0 .equ 0x0715 +__if1msk20 ; overlay symbol ;000716 +IF1MSK20 .equ 0x0716 +__if1msk2l0 .res.b 1 ;000716 +IF1MSK2L0 .equ 0x0716 +__if1msk2h0 .res.b 1 ;000717 +IF1MSK2H0 .equ 0x0717 +__if1arb0 ; overlay symbol ;000718 +IF1ARB0 .equ 0x0718 +__if1arb10 ; overlay symbol ;000718 +IF1ARB10 .equ 0x0718 +__if1arb1l0 .res.b 1 ;000718 +IF1ARB1L0 .equ 0x0718 +__if1arb1h0 .res.b 1 ;000719 +IF1ARB1H0 .equ 0x0719 +__if1arb20 ; overlay symbol ;00071A +IF1ARB20 .equ 0x071A +__if1arb2l0 .res.b 1 ;00071A +IF1ARB2L0 .equ 0x071A +__if1arb2h0 .res.b 1 ;00071B +IF1ARB2H0 .equ 0x071B +__if1mctr0 ; overlay symbol ;00071C +IF1MCTR0 .equ 0x071C +__if1mctrl0 .res.b 1 ;00071C +IF1MCTRL0 .equ 0x071C +__if1mctrh0 .res.b 1 ;00071D +IF1MCTRH0 .equ 0x071D +__if1dta0 ; overlay symbol ;00071E +IF1DTA0 .equ 0x071E +__if1dta10 ; overlay symbol ;00071E +IF1DTA10 .equ 0x071E +__if1dta1l0 .res.b 1 ;00071E +IF1DTA1L0 .equ 0x071E +__if1dta1h0 .res.b 1 ;00071F +IF1DTA1H0 .equ 0x071F +__if1dta20 ; overlay symbol ;000720 +IF1DTA20 .equ 0x0720 +__if1dta2l0 .res.b 1 ;000720 +IF1DTA2L0 .equ 0x0720 +__if1dta2h0 .res.b 1 ;000721 +IF1DTA2H0 .equ 0x0721 +__if1dtb0 ; overlay symbol ;000722 +IF1DTB0 .equ 0x0722 +__if1dtb10 ; overlay symbol ;000722 +IF1DTB10 .equ 0x0722 +__if1dtb1l0 .res.b 1 ;000722 +IF1DTB1L0 .equ 0x0722 +__if1dtb1h0 .res.b 1 ;000723 +IF1DTB1H0 .equ 0x0723 +__if1dtb20 ; overlay symbol ;000724 +IF1DTB20 .equ 0x0724 +__if1dtb2l0 .res.b 1 ;000724 +IF1DTB2L0 .equ 0x0724 +__if1dtb2h0 .res.b 1 ;000725 +IF1DTB2H0 .equ 0x0725 + .org 0x000740 +__if2creq0 ; overlay symbol ;000740 +IF2CREQ0 .equ 0x0740 +__if2creql0 .res.b 1 ;000740 +IF2CREQL0 .equ 0x0740 +__if2creqh0 .res.b 1 ;000741 +IF2CREQH0 .equ 0x0741 +__if2cmsk0 ; overlay symbol ;000742 +IF2CMSK0 .equ 0x0742 +__if2cmskl0 .res.b 1 ;000742 +IF2CMSKL0 .equ 0x0742 +__if2cmskh0 .res.b 1 ;000743 +IF2CMSKH0 .equ 0x0743 +__if2msk0 ; overlay symbol ;000744 +IF2MSK0 .equ 0x0744 +__if2msk10 ; overlay symbol ;000744 +IF2MSK10 .equ 0x0744 +__if2msk1l0 .res.b 1 ;000744 +IF2MSK1L0 .equ 0x0744 +__if2msk1h0 .res.b 1 ;000745 +IF2MSK1H0 .equ 0x0745 +__if2msk20 ; overlay symbol ;000746 +IF2MSK20 .equ 0x0746 +__if2msk2l0 .res.b 1 ;000746 +IF2MSK2L0 .equ 0x0746 +__if2msk2h0 .res.b 1 ;000747 +IF2MSK2H0 .equ 0x0747 +__if2arb0 ; overlay symbol ;000748 +IF2ARB0 .equ 0x0748 +__if2arb10 ; overlay symbol ;000748 +IF2ARB10 .equ 0x0748 +__if2arb1l0 .res.b 1 ;000748 +IF2ARB1L0 .equ 0x0748 +__if2arb1h0 .res.b 1 ;000749 +IF2ARB1H0 .equ 0x0749 +__if2arb20 ; overlay symbol ;00074A +IF2ARB20 .equ 0x074A +__if2arb2l0 .res.b 1 ;00074A +IF2ARB2L0 .equ 0x074A +__if2arb2h0 .res.b 1 ;00074B +IF2ARB2H0 .equ 0x074B +__if2mctr0 ; overlay symbol ;00074C +IF2MCTR0 .equ 0x074C +__if2mctrl0 .res.b 1 ;00074C +IF2MCTRL0 .equ 0x074C +__if2mctrh0 .res.b 1 ;00074D +IF2MCTRH0 .equ 0x074D +__if2dta0 ; overlay symbol ;00074E +IF2DTA0 .equ 0x074E +__if2dta10 ; overlay symbol ;00074E +IF2DTA10 .equ 0x074E +__if2dta1l0 .res.b 1 ;00074E +IF2DTA1L0 .equ 0x074E +__if2dta1h0 .res.b 1 ;00074F +IF2DTA1H0 .equ 0x074F +__if2dta20 ; overlay symbol ;000750 +IF2DTA20 .equ 0x0750 +__if2dta2l0 .res.b 1 ;000750 +IF2DTA2L0 .equ 0x0750 +__if2dta2h0 .res.b 1 ;000751 +IF2DTA2H0 .equ 0x0751 +__if2dtb0 ; overlay symbol ;000752 +IF2DTB0 .equ 0x0752 +__if2dtb10 ; overlay symbol ;000752 +IF2DTB10 .equ 0x0752 +__if2dtb1l0 .res.b 1 ;000752 +IF2DTB1L0 .equ 0x0752 +__if2dtb1h0 .res.b 1 ;000753 +IF2DTB1H0 .equ 0x0753 +__if2dtb20 ; overlay symbol ;000754 +IF2DTB20 .equ 0x0754 +__if2dtb2l0 .res.b 1 ;000754 +IF2DTB2L0 .equ 0x0754 +__if2dtb2h0 .res.b 1 ;000755 +IF2DTB2H0 .equ 0x0755 + .org 0x000780 +__treqr0 ; overlay symbol ;000780 +TREQR0 .equ 0x0780 +__treqr10 ; overlay symbol ;000780 +TREQR10 .equ 0x0780 +__treqr1l0 .res.b 1 ;000780 +TREQR1L0 .equ 0x0780 +__treqr1h0 .res.b 1 ;000781 +TREQR1H0 .equ 0x0781 +__treqr20 ; overlay symbol ;000782 +TREQR20 .equ 0x0782 +__treqr2l0 .res.b 1 ;000782 +TREQR2L0 .equ 0x0782 +__treqr2h0 .res.b 1 ;000783 +TREQR2H0 .equ 0x0783 + .org 0x000790 +__newdt0 ; overlay symbol ;000790 +NEWDT0 .equ 0x0790 +__newdt10 ; overlay symbol ;000790 +NEWDT10 .equ 0x0790 +__newdt1l0 .res.b 1 ;000790 +NEWDT1L0 .equ 0x0790 +__newdt1h0 .res.b 1 ;000791 +NEWDT1H0 .equ 0x0791 +__newdt20 ; overlay symbol ;000792 +NEWDT20 .equ 0x0792 +__newdt2l0 .res.b 1 ;000792 +NEWDT2L0 .equ 0x0792 +__newdt2h0 .res.b 1 ;000793 +NEWDT2H0 .equ 0x0793 + .org 0x0007A0 +__intpnd0 ; overlay symbol ;0007A0 +INTPND0 .equ 0x07A0 +__intpnd10 ; overlay symbol ;0007A0 +INTPND10 .equ 0x07A0 +__intpnd1l0 .res.b 1 ;0007A0 +INTPND1L0 .equ 0x07A0 +__intpnd1h0 .res.b 1 ;0007A1 +INTPND1H0 .equ 0x07A1 +__intpnd20 ; overlay symbol ;0007A2 +INTPND20 .equ 0x07A2 +__intpnd2l0 .res.b 1 ;0007A2 +INTPND2L0 .equ 0x07A2 +__intpnd2h0 .res.b 1 ;0007A3 +INTPND2H0 .equ 0x07A3 + .org 0x0007B0 +__msgval0 ; overlay symbol ;0007B0 +MSGVAL0 .equ 0x07B0 +__msgval10 ; overlay symbol ;0007B0 +MSGVAL10 .equ 0x07B0 +__msgval1l0 .res.b 1 ;0007B0 +MSGVAL1L0 .equ 0x07B0 +__msgval1h0 .res.b 1 ;0007B1 +MSGVAL1H0 .equ 0x07B1 +__msgval20 ; overlay symbol ;0007B2 +MSGVAL20 .equ 0x07B2 +__msgval2l0 .res.b 1 ;0007B2 +MSGVAL2L0 .equ 0x07B2 +__msgval2h0 .res.b 1 ;0007B3 +MSGVAL2H0 .equ 0x07B3 + .org 0x0007CE +__coer0 .res.b 1 ;0007CE +COER0 .equ 0x07CE + .org 0x000800 +__ctrlr1 ; overlay symbol ;000800 +CTRLR1 .equ 0x0800 +__ctrlrl1 .res.b 1 ;000800 +CTRLRL1 .equ 0x0800 +__ctrlrh1 .res.b 1 ;000801 +CTRLRH1 .equ 0x0801 +__statr1 ; overlay symbol ;000802 +STATR1 .equ 0x0802 +__statrl1 .res.b 1 ;000802 +STATRL1 .equ 0x0802 +__statrh1 .res.b 1 ;000803 +STATRH1 .equ 0x0803 +__errcnt1 ; overlay symbol ;000804 +ERRCNT1 .equ 0x0804 +__errcntl1 .res.b 1 ;000804 +ERRCNTL1 .equ 0x0804 +__errcnth1 .res.b 1 ;000805 +ERRCNTH1 .equ 0x0805 +__btr1 ; overlay symbol ;000806 +BTR1 .equ 0x0806 +__btrl1 .res.b 1 ;000806 +BTRL1 .equ 0x0806 +__btrh1 .res.b 1 ;000807 +BTRH1 .equ 0x0807 +__intr1 ; overlay symbol ;000808 +INTR1 .equ 0x0808 +__intrl1 .res.b 1 ;000808 +INTRL1 .equ 0x0808 +__intrh1 .res.b 1 ;000809 +INTRH1 .equ 0x0809 +__testr1 ; overlay symbol ;00080A +TESTR1 .equ 0x080A +__testrl1 .res.b 1 ;00080A +TESTRL1 .equ 0x080A +__testrh1 .res.b 1 ;00080B +TESTRH1 .equ 0x080B +__brper1 ; overlay symbol ;00080C +BRPER1 .equ 0x080C +__brperl1 .res.b 1 ;00080C +BRPERL1 .equ 0x080C +__brperh1 .res.b 1 ;00080D +BRPERH1 .equ 0x080D + .org 0x000810 +__if1creq1 ; overlay symbol ;000810 +IF1CREQ1 .equ 0x0810 +__if1creql1 .res.b 1 ;000810 +IF1CREQL1 .equ 0x0810 +__if1creqh1 .res.b 1 ;000811 +IF1CREQH1 .equ 0x0811 +__if1cmsk1 ; overlay symbol ;000812 +IF1CMSK1 .equ 0x0812 +__if1cmskl1 .res.b 1 ;000812 +IF1CMSKL1 .equ 0x0812 +__if1cmskh1 .res.b 1 ;000813 +IF1CMSKH1 .equ 0x0813 +__if1msk1 ; overlay symbol ;000814 +IF1MSK1 .equ 0x0814 +__if1msk11 ; overlay symbol ;000814 +IF1MSK11 .equ 0x0814 +__if1msk1l1 .res.b 1 ;000814 +IF1MSK1L1 .equ 0x0814 +__if1msk1h1 .res.b 1 ;000815 +IF1MSK1H1 .equ 0x0815 +__if1msk21 ; overlay symbol ;000816 +IF1MSK21 .equ 0x0816 +__if1msk2l1 .res.b 1 ;000816 +IF1MSK2L1 .equ 0x0816 +__if1msk2h1 .res.b 1 ;000817 +IF1MSK2H1 .equ 0x0817 +__if1arb1 ; overlay symbol ;000818 +IF1ARB1 .equ 0x0818 +__if1arb11 ; overlay symbol ;000818 +IF1ARB11 .equ 0x0818 +__if1arb1l1 .res.b 1 ;000818 +IF1ARB1L1 .equ 0x0818 +__if1arb1h1 .res.b 1 ;000819 +IF1ARB1H1 .equ 0x0819 +__if1arb21 ; overlay symbol ;00081A +IF1ARB21 .equ 0x081A +__if1arb2l1 .res.b 1 ;00081A +IF1ARB2L1 .equ 0x081A +__if1arb2h1 .res.b 1 ;00081B +IF1ARB2H1 .equ 0x081B +__if1mctr1 ; overlay symbol ;00081C +IF1MCTR1 .equ 0x081C +__if1mctrl1 .res.b 1 ;00081C +IF1MCTRL1 .equ 0x081C +__if1mctrh1 .res.b 1 ;00081D +IF1MCTRH1 .equ 0x081D +__if1dta1 ; overlay symbol ;00081E +IF1DTA1 .equ 0x081E +__if1dta11 ; overlay symbol ;00081E +IF1DTA11 .equ 0x081E +__if1dta1l1 .res.b 1 ;00081E +IF1DTA1L1 .equ 0x081E +__if1dta1h1 .res.b 1 ;00081F +IF1DTA1H1 .equ 0x081F +__if1dta21 ; overlay symbol ;000820 +IF1DTA21 .equ 0x0820 +__if1dta2l1 .res.b 1 ;000820 +IF1DTA2L1 .equ 0x0820 +__if1dta2h1 .res.b 1 ;000821 +IF1DTA2H1 .equ 0x0821 +__if1dtb1 ; overlay symbol ;000822 +IF1DTB1 .equ 0x0822 +__if1dtb11 ; overlay symbol ;000822 +IF1DTB11 .equ 0x0822 +__if1dtb1l1 .res.b 1 ;000822 +IF1DTB1L1 .equ 0x0822 +__if1dtb1h1 .res.b 1 ;000823 +IF1DTB1H1 .equ 0x0823 +__if1dtb21 ; overlay symbol ;000824 +IF1DTB21 .equ 0x0824 +__if1dtb2l1 .res.b 1 ;000824 +IF1DTB2L1 .equ 0x0824 +__if1dtb2h1 .res.b 1 ;000825 +IF1DTB2H1 .equ 0x0825 + .org 0x000840 +__if2creq1 ; overlay symbol ;000840 +IF2CREQ1 .equ 0x0840 +__if2creql1 .res.b 1 ;000840 +IF2CREQL1 .equ 0x0840 +__if2creqh1 .res.b 1 ;000841 +IF2CREQH1 .equ 0x0841 +__if2cmsk1 ; overlay symbol ;000842 +IF2CMSK1 .equ 0x0842 +__if2cmskl1 .res.b 1 ;000842 +IF2CMSKL1 .equ 0x0842 +__if2cmskh1 .res.b 1 ;000843 +IF2CMSKH1 .equ 0x0843 +__if2msk1 ; overlay symbol ;000844 +IF2MSK1 .equ 0x0844 +__if2msk11 ; overlay symbol ;000844 +IF2MSK11 .equ 0x0844 +__if2msk1l1 .res.b 1 ;000844 +IF2MSK1L1 .equ 0x0844 +__if2msk1h1 .res.b 1 ;000845 +IF2MSK1H1 .equ 0x0845 +__if2msk21 ; overlay symbol ;000846 +IF2MSK21 .equ 0x0846 +__if2msk2l1 .res.b 1 ;000846 +IF2MSK2L1 .equ 0x0846 +__if2msk2h1 .res.b 1 ;000847 +IF2MSK2H1 .equ 0x0847 +__if2arb1 ; overlay symbol ;000848 +IF2ARB1 .equ 0x0848 +__if2arb11 ; overlay symbol ;000848 +IF2ARB11 .equ 0x0848 +__if2arb1l1 .res.b 1 ;000848 +IF2ARB1L1 .equ 0x0848 +__if2arb1h1 .res.b 1 ;000849 +IF2ARB1H1 .equ 0x0849 +__if2arb21 ; overlay symbol ;00084A +IF2ARB21 .equ 0x084A +__if2arb2l1 .res.b 1 ;00084A +IF2ARB2L1 .equ 0x084A +__if2arb2h1 .res.b 1 ;00084B +IF2ARB2H1 .equ 0x084B +__if2mctr1 ; overlay symbol ;00084C +IF2MCTR1 .equ 0x084C +__if2mctrl1 .res.b 1 ;00084C +IF2MCTRL1 .equ 0x084C +__if2mctrh1 .res.b 1 ;00084D +IF2MCTRH1 .equ 0x084D +__if2dta1 ; overlay symbol ;00084E +IF2DTA1 .equ 0x084E +__if2dta11 ; overlay symbol ;00084E +IF2DTA11 .equ 0x084E +__if2dta1l1 .res.b 1 ;00084E +IF2DTA1L1 .equ 0x084E +__if2dta1h1 .res.b 1 ;00084F +IF2DTA1H1 .equ 0x084F +__if2dta21 ; overlay symbol ;000850 +IF2DTA21 .equ 0x0850 +__if2dta2l1 .res.b 1 ;000850 +IF2DTA2L1 .equ 0x0850 +__if2dta2h1 .res.b 1 ;000851 +IF2DTA2H1 .equ 0x0851 +__if2dtb1 ; overlay symbol ;000852 +IF2DTB1 .equ 0x0852 +__if2dtb11 ; overlay symbol ;000852 +IF2DTB11 .equ 0x0852 +__if2dtb1l1 .res.b 1 ;000852 +IF2DTB1L1 .equ 0x0852 +__if2dtb1h1 .res.b 1 ;000853 +IF2DTB1H1 .equ 0x0853 +__if2dtb21 ; overlay symbol ;000854 +IF2DTB21 .equ 0x0854 +__if2dtb2l1 .res.b 1 ;000854 +IF2DTB2L1 .equ 0x0854 +__if2dtb2h1 .res.b 1 ;000855 +IF2DTB2H1 .equ 0x0855 + .org 0x000880 +__treqr1 ; overlay symbol ;000880 +TREQR1 .equ 0x0880 +__treqr11 ; overlay symbol ;000880 +TREQR11 .equ 0x0880 +__treqr1l1 .res.b 1 ;000880 +TREQR1L1 .equ 0x0880 +__treqr1h1 .res.b 1 ;000881 +TREQR1H1 .equ 0x0881 +__treqr21 ; overlay symbol ;000882 +TREQR21 .equ 0x0882 +__treqr2l1 .res.b 1 ;000882 +TREQR2L1 .equ 0x0882 +__treqr2h1 .res.b 1 ;000883 +TREQR2H1 .equ 0x0883 + .org 0x000890 +__newdt1 ; overlay symbol ;000890 +NEWDT1 .equ 0x0890 +__newdt11 ; overlay symbol ;000890 +NEWDT11 .equ 0x0890 +__newdt1l1 .res.b 1 ;000890 +NEWDT1L1 .equ 0x0890 +__newdt1h1 .res.b 1 ;000891 +NEWDT1H1 .equ 0x0891 +__newdt21 ; overlay symbol ;000892 +NEWDT21 .equ 0x0892 +__newdt2l1 .res.b 1 ;000892 +NEWDT2L1 .equ 0x0892 +__newdt2h1 .res.b 1 ;000893 +NEWDT2H1 .equ 0x0893 + .org 0x0008A0 +__intpnd1 ; overlay symbol ;0008A0 +INTPND1 .equ 0x08A0 +__intpnd11 ; overlay symbol ;0008A0 +INTPND11 .equ 0x08A0 +__intpnd1l1 .res.b 1 ;0008A0 +INTPND1L1 .equ 0x08A0 +__intpnd1h1 .res.b 1 ;0008A1 +INTPND1H1 .equ 0x08A1 +__intpnd21 ; overlay symbol ;0008A2 +INTPND21 .equ 0x08A2 +__intpnd2l1 .res.b 1 ;0008A2 +INTPND2L1 .equ 0x08A2 +__intpnd2h1 .res.b 1 ;0008A3 +INTPND2H1 .equ 0x08A3 + .org 0x0008B0 +__msgval1 ; overlay symbol ;0008B0 +MSGVAL1 .equ 0x08B0 +__msgval11 ; overlay symbol ;0008B0 +MSGVAL11 .equ 0x08B0 +__msgval1l1 .res.b 1 ;0008B0 +MSGVAL1L1 .equ 0x08B0 +__msgval1h1 .res.b 1 ;0008B1 +MSGVAL1H1 .equ 0x08B1 +__msgval21 ; overlay symbol ;0008B2 +MSGVAL21 .equ 0x08B2 +__msgval2l1 .res.b 1 ;0008B2 +MSGVAL2L1 .equ 0x08B2 +__msgval2h1 .res.b 1 ;0008B3 +MSGVAL2H1 .equ 0x08B3 + .org 0x0008CE +__coer1 .res.b 1 ;0008CE +COER1 .equ 0x08CE + + + .end diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/mb96348hs.h b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/mb96348hs.h new file mode 100644 index 000000000..8803c2337 --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/mb96348hs.h @@ -0,0 +1,23746 @@ +/* FFMC-16 IO-MAP HEADER FILE */ +/* ========================== */ +/* SOFTUNE WORKBENCH FORMAT */ +/* C-DEFINITIONS FOR IO-SYMBOLS */ +/* CREATED BY IO-WIZARD V2.27 */ +/* $Id: mb96348hs.h,v 1.7 2007/09/20 14:23:33 mwilla Exp $ */ +/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ +/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ +/* ELIGIBILITY FOR ANY PURPOSES. */ +/* (C) Fujitsu Microelectronics Europe GmbH */ +/* ************************************************************************* */ +/* FUJITSU MICROELECTRONICS EUROPE GMBH */ +/* Pittlerstrasse 47, 63225 Langen, Germany */ +/* Tel.:++49/6103/690-0,Fax - 122 */ +/* */ +/* The following software is for demonstration purposes only. */ +/* It is not fully tested, nor validated in order to fullfill */ +/* its task under all circumstances. Therefore, this software */ +/* or any part of it must only be used in an evaluation */ +/* laboratory environment. */ +/* This software is subject to the rules of our standard */ +/* DISCLAIMER, that is delivered with our SW-tools on the CD or DVD */ +/* "Micros Documentation & Software" (V3.4 or later) or */ +/* see our Internet Page - */ +/* http://emea.fujitsu.com/microelectronics */ +/* ************************************************************************* */ +/* */ +/* NOTE: */ +/* */ +/* This header-file covers all features of the chip MB96F348HS. */ +/* */ +/* */ +/* ---------------------------------------------------------------------- */ +/* History: */ +/* Date Version Author Description */ +/* 22.12.2006 1.0 PHu Initial Release: derived from headerfile of */ +/* MB96348RS and added Satellite Flash, removed */ +/* RTC, Clock Calibration, LIN-USART7-9 */ +/* 16.01.2007 1.1 PHu Add 32-bit access names for CAN where */ +/* appropriate */ +/* 09.02.2007 1.3 PHu skip version 1.2 to be in line with CVS */ +/* numbering */ +/* correct addresses of LIN-UART3 registers */ +/* allow only 16 bit access for the ADSR */ +/* 12.04.2007 1.4 Mef Added Voltage Regulator Control Register */ +/* Added RD19V bit in Flash Memory Control */ +/* Status Register */ +/* 03.05.2007 1.5 Mef Added LIN USART 7,8,9 */ +/* 15.05.2007 1.6 Mef Added RTC */ +/* 20.09.2007 1.7 MWi Completely revised version */ + + +#ifndef __MB96XXX_H +# define __MB96XXX_H +/* +- Please define __IO_NEAR in LARGE and COMPACT memory model, if the default + data bank (DTB) is 00. This will result in better performance in these + models. +- Please define __IO_FAR in SMALL and MEDIUM memory model, if the default + data bank (DTB) is other than 00. This might be the case in systems with + external RAM, which are not using internal RAM as default data area. +- Please define neither __IO_NEAR nor __IO_FAR in all other cases. This + will work with almost all configurations. +*/ + +# ifdef __IO_NEAR +# ifdef __IO_FAR +# error __IO_NEAR and __IO_FAR must not be defined at the same time +# else +# define ___IOWIDTH __near +# endif +# else +# ifdef __IO_FAR +# define ___IOWIDTH __far +# else /* specified by memory model */ +# define ___IOWIDTH +# endif +# endif +# ifdef __IO_DEFINE +# define __IO_EXTERN +# define __IO_EXTENDED volatile ___IOWIDTH +# else +# define __IO_EXTERN extern /* for data, which can have __io */ +# define __IO_EXTENDED extern volatile ___IOWIDTH +# endif + +typedef unsigned char IO_BYTE; +typedef unsigned short IO_WORD; +typedef unsigned long IO_LWORD; +typedef const unsigned short IO_WORD_READ; + +/* REGISTER BIT STRUCTURES */ + +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _P0 :1; + IO_BYTE _P1 :1; + IO_BYTE _P2 :1; + IO_BYTE _P3 :1; + IO_BYTE _P4 :1; + IO_BYTE _P5 :1; + IO_BYTE _P6 :1; + IO_BYTE _P7 :1; + }bit; + }PDR00STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _P0 :1; + IO_BYTE _P1 :1; + IO_BYTE _P2 :1; + IO_BYTE _P3 :1; + IO_BYTE _P4 :1; + IO_BYTE _P5 :1; + IO_BYTE _P6 :1; + IO_BYTE _P7 :1; + }bit; + }PDR01STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _P0 :1; + IO_BYTE _P1 :1; + IO_BYTE _P2 :1; + IO_BYTE _P3 :1; + IO_BYTE _P4 :1; + IO_BYTE _P5 :1; + IO_BYTE _P6 :1; + IO_BYTE _P7 :1; + }bit; + }PDR02STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _P0 :1; + IO_BYTE _P1 :1; + IO_BYTE _P2 :1; + IO_BYTE _P3 :1; + IO_BYTE _P4 :1; + IO_BYTE _P5 :1; + IO_BYTE _P6 :1; + IO_BYTE _P7 :1; + }bit; + }PDR03STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _P0 :1; + IO_BYTE _P1 :1; + IO_BYTE _P2 :1; + IO_BYTE _P3 :1; + IO_BYTE _P4 :1; + IO_BYTE _P5 :1; + IO_BYTE _P6 :1; + IO_BYTE _P7 :1; + }bit; + }PDR04STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _P0 :1; + IO_BYTE _P1 :1; + IO_BYTE _P2 :1; + IO_BYTE _P3 :1; + IO_BYTE _P4 :1; + IO_BYTE _P5 :1; + IO_BYTE _P6 :1; + IO_BYTE _P7 :1; + }bit; + }PDR05STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _P0 :1; + IO_BYTE _P1 :1; + IO_BYTE _P2 :1; + IO_BYTE _P3 :1; + IO_BYTE _P4 :1; + IO_BYTE _P5 :1; + IO_BYTE _P6 :1; + IO_BYTE _P7 :1; + }bit; + }PDR06STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _P0 :1; + IO_BYTE _P1 :1; + IO_BYTE _P2 :1; + IO_BYTE _P3 :1; + IO_BYTE _P4 :1; + IO_BYTE _P5 :1; + IO_BYTE _P6 :1; + IO_BYTE _P7 :1; + }bit; + }PDR07STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _P0 :1; + IO_BYTE _P1 :1; + IO_BYTE _P2 :1; + IO_BYTE _P3 :1; + IO_BYTE _P4 :1; + IO_BYTE _P5 :1; + IO_BYTE _P6 :1; + IO_BYTE _P7 :1; + }bit; + }PDR08STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _P0 :1; + IO_BYTE _P1 :1; + IO_BYTE _P2 :1; + IO_BYTE _P3 :1; + IO_BYTE _P4 :1; + IO_BYTE _P5 :1; + IO_BYTE _P6 :1; + IO_BYTE _P7 :1; + }bit; + }PDR09STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _P0 :1; + IO_BYTE _P1 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }PDR10STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _resv :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _S10 :1; + IO_WORD _MD0 :1; + IO_WORD _MD1 :1; + IO_WORD :1; + IO_WORD _STRT :1; + IO_WORD _STS0 :1; + IO_WORD _STS1 :1; + IO_WORD _PAUS :1; + IO_WORD _INTE :1; + IO_WORD _INT :1; + IO_WORD _BUSY :1; + }bit; + struct{ + IO_WORD :6; + IO_WORD _MD :2; + IO_WORD :2; + IO_WORD _STS :2; + }bitc; + }ADCSSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _resv :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _S10 :1; + IO_BYTE _MD0 :1; + IO_BYTE _MD1 :1; + }bit; + struct{ + IO_BYTE :6; + IO_BYTE _MD :2; + }bitc; + }ADCSLSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _STRT :1; + IO_BYTE _STS0 :1; + IO_BYTE _STS1 :1; + IO_BYTE _PAUS :1; + IO_BYTE _INTE :1; + IO_BYTE _INT :1; + IO_BYTE _BUSY :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _STS :2; + }bitc; + }ADCSHSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD _D :10; + }bitc; + }ADCRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D0 :1; + IO_BYTE _D1 :1; + IO_BYTE _D2 :1; + IO_BYTE _D3 :1; + IO_BYTE _D4 :1; + IO_BYTE _D5 :1; + IO_BYTE _D6 :1; + IO_BYTE _D7 :1; + }bit; + }ADCRLSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D8 :1; + IO_BYTE _D9 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }ADCRHSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _ANE0 :1; + IO_WORD _ANE1 :1; + IO_WORD _ANE2 :1; + IO_WORD _ANE3 :1; + IO_WORD _ANE4 :1; + IO_WORD _ANS0 :1; + IO_WORD _ANS1 :1; + IO_WORD _ANS2 :1; + IO_WORD _ANS3 :1; + IO_WORD _ANS4 :1; + IO_WORD _CT0 :1; + IO_WORD _CT1 :1; + IO_WORD _CT2 :1; + IO_WORD _ST0 :1; + IO_WORD _ST1 :1; + IO_WORD _ST2 :1; + }bit; + }ADSRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ADSEL :1; + IO_BYTE _HSEL :1; + IO_BYTE _LSEL :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }ADECRSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _T0 :1; + IO_WORD _T1 :1; + IO_WORD _T2 :1; + IO_WORD _T3 :1; + IO_WORD _T4 :1; + IO_WORD _T5 :1; + IO_WORD _T6 :1; + IO_WORD _T7 :1; + IO_WORD _T8 :1; + IO_WORD _T9 :1; + IO_WORD _T10 :1; + IO_WORD _T11 :1; + IO_WORD _T12 :1; + IO_WORD _T13 :1; + IO_WORD _T14 :1; + IO_WORD _T15 :1; + }bit; + struct{ + IO_WORD _T :16; + }bitc; + }TCDT0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CLK0 :1; + IO_WORD _CLK1 :1; + IO_WORD _CLK2 :1; + IO_WORD _CLR :1; + IO_WORD _MODE :1; + IO_WORD _STOP :1; + IO_WORD _IVFE :1; + IO_WORD _IVF :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _FSEL :1; + IO_WORD _ECKE :1; + }bit; + struct{ + IO_WORD _CLK :3; + }bitc; + }TCCS0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CLK0 :1; + IO_BYTE _CLK1 :1; + IO_BYTE _CLK2 :1; + IO_BYTE _CLR :1; + IO_BYTE _MODE :1; + IO_BYTE _STOP :1; + IO_BYTE _IVFE :1; + IO_BYTE _IVF :1; + }bit; + struct{ + IO_BYTE _CLK :3; + }bitc; + }TCCSL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _FSEL :1; + IO_BYTE _ECKE :1; + }bit; + }TCCSH0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _T0 :1; + IO_WORD _T1 :1; + IO_WORD _T2 :1; + IO_WORD _T3 :1; + IO_WORD _T4 :1; + IO_WORD _T5 :1; + IO_WORD _T6 :1; + IO_WORD _T7 :1; + IO_WORD _T8 :1; + IO_WORD _T9 :1; + IO_WORD _T10 :1; + IO_WORD _T11 :1; + IO_WORD _T12 :1; + IO_WORD _T13 :1; + IO_WORD _T14 :1; + IO_WORD _T15 :1; + }bit; + struct{ + IO_WORD _T :16; + }bitc; + }TCDT1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CLK0 :1; + IO_WORD _CLK1 :1; + IO_WORD _CLK2 :1; + IO_WORD _CLR :1; + IO_WORD _MODE :1; + IO_WORD _STOP :1; + IO_WORD _IVFE :1; + IO_WORD _IVF :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _FSEL :1; + IO_WORD _ECKE :1; + }bit; + struct{ + IO_WORD _CLK :3; + }bitc; + }TCCS1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CLK0 :1; + IO_BYTE _CLK1 :1; + IO_BYTE _CLK2 :1; + IO_BYTE _CLR :1; + IO_BYTE _MODE :1; + IO_BYTE _STOP :1; + IO_BYTE _IVFE :1; + IO_BYTE _IVF :1; + }bit; + struct{ + IO_BYTE _CLK :3; + }bitc; + }TCCSL1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _FSEL :1; + IO_BYTE _ECKE :1; + }bit; + }TCCSH1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CST0 :1; + IO_BYTE _CST1 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICE0 :1; + IO_BYTE _ICE1 :1; + IO_BYTE _ICP0 :1; + IO_BYTE _ICP1 :1; + }bit; + }OCS0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OTD0 :1; + IO_BYTE _OTD1 :1; + IO_BYTE _OTE0 :1; + IO_BYTE _OTE1 :1; + IO_BYTE _CMOD0 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CMOD1 :1; + }bit; + }OCS1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _C00 :1; + IO_WORD _C01 :1; + IO_WORD _C02 :1; + IO_WORD _C03 :1; + IO_WORD _C04 :1; + IO_WORD _C05 :1; + IO_WORD _C06 :1; + IO_WORD _C07 :1; + IO_WORD _C08 :1; + IO_WORD _C09 :1; + IO_WORD _C10 :1; + IO_WORD _C11 :1; + IO_WORD _C12 :1; + IO_WORD _C13 :1; + IO_WORD _C14 :1; + IO_WORD _C15 :1; + }bit; + struct{ + IO_WORD _C0 :16; + }bitc; + }OCCP0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _C00 :1; + IO_WORD _C01 :1; + IO_WORD _C02 :1; + IO_WORD _C03 :1; + IO_WORD _C04 :1; + IO_WORD _C05 :1; + IO_WORD _C06 :1; + IO_WORD _C07 :1; + IO_WORD _C08 :1; + IO_WORD _C09 :1; + IO_WORD _C10 :1; + IO_WORD _C11 :1; + IO_WORD _C12 :1; + IO_WORD _C13 :1; + IO_WORD _C14 :1; + IO_WORD _C15 :1; + }bit; + struct{ + IO_WORD _C0 :16; + }bitc; + }OCCP1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CST2 :1; + IO_BYTE _CST3 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICE2 :1; + IO_BYTE _ICE3 :1; + IO_BYTE _ICP2 :1; + IO_BYTE _ICP3 :1; + }bit; + }OCS2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OTD2 :1; + IO_BYTE _OTD3 :1; + IO_BYTE _OTE2 :1; + IO_BYTE _OTE3 :1; + IO_BYTE _CMOD0 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CMOD1 :1; + }bit; + }OCS3STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _C00 :1; + IO_WORD _C01 :1; + IO_WORD _C02 :1; + IO_WORD _C03 :1; + IO_WORD _C04 :1; + IO_WORD _C05 :1; + IO_WORD _C06 :1; + IO_WORD _C07 :1; + IO_WORD _C08 :1; + IO_WORD _C09 :1; + IO_WORD _C10 :1; + IO_WORD _C11 :1; + IO_WORD _C12 :1; + IO_WORD _C13 :1; + IO_WORD _C14 :1; + IO_WORD _C15 :1; + }bit; + struct{ + IO_WORD _C0 :16; + }bitc; + }OCCP2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _C00 :1; + IO_WORD _C01 :1; + IO_WORD _C02 :1; + IO_WORD _C03 :1; + IO_WORD _C04 :1; + IO_WORD _C05 :1; + IO_WORD _C06 :1; + IO_WORD _C07 :1; + IO_WORD _C08 :1; + IO_WORD _C09 :1; + IO_WORD _C10 :1; + IO_WORD _C11 :1; + IO_WORD _C12 :1; + IO_WORD _C13 :1; + IO_WORD _C14 :1; + IO_WORD _C15 :1; + }bit; + struct{ + IO_WORD _C0 :16; + }bitc; + }OCCP3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CST4 :1; + IO_BYTE _CST5 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICE4 :1; + IO_BYTE _ICE5 :1; + IO_BYTE _ICP4 :1; + IO_BYTE _ICP5 :1; + }bit; + }OCS4STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OTD4 :1; + IO_BYTE _OTD5 :1; + IO_BYTE _OTE4 :1; + IO_BYTE _OTE5 :1; + IO_BYTE _CMOD0 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CMOD1 :1; + }bit; + }OCS5STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _C00 :1; + IO_WORD _C01 :1; + IO_WORD _C02 :1; + IO_WORD _C03 :1; + IO_WORD _C04 :1; + IO_WORD _C05 :1; + IO_WORD _C06 :1; + IO_WORD _C07 :1; + IO_WORD _C08 :1; + IO_WORD _C09 :1; + IO_WORD _C10 :1; + IO_WORD _C11 :1; + IO_WORD _C12 :1; + IO_WORD _C13 :1; + IO_WORD _C14 :1; + IO_WORD _C15 :1; + }bit; + struct{ + IO_WORD _C0 :16; + }bitc; + }OCCP4STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _C00 :1; + IO_WORD _C01 :1; + IO_WORD _C02 :1; + IO_WORD _C03 :1; + IO_WORD _C04 :1; + IO_WORD _C05 :1; + IO_WORD _C06 :1; + IO_WORD _C07 :1; + IO_WORD _C08 :1; + IO_WORD _C09 :1; + IO_WORD _C10 :1; + IO_WORD _C11 :1; + IO_WORD _C12 :1; + IO_WORD _C13 :1; + IO_WORD _C14 :1; + IO_WORD _C15 :1; + }bit; + struct{ + IO_WORD _C0 :16; + }bitc; + }OCCP5STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CST6 :1; + IO_BYTE _CST7 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _ICE6 :1; + IO_BYTE _ICE7 :1; + IO_BYTE _ICP6 :1; + IO_BYTE _ICP7 :1; + }bit; + }OCS6STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OTD6 :1; + IO_BYTE _OTD7 :1; + IO_BYTE _OTE6 :1; + IO_BYTE _OTE7 :1; + IO_BYTE _CMOD0 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CMOD1 :1; + }bit; + }OCS7STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _C00 :1; + IO_WORD _C01 :1; + IO_WORD _C02 :1; + IO_WORD _C03 :1; + IO_WORD _C04 :1; + IO_WORD _C05 :1; + IO_WORD _C06 :1; + IO_WORD _C07 :1; + IO_WORD _C08 :1; + IO_WORD _C09 :1; + IO_WORD _C10 :1; + IO_WORD _C11 :1; + IO_WORD _C12 :1; + IO_WORD _C13 :1; + IO_WORD _C14 :1; + IO_WORD _C15 :1; + }bit; + struct{ + IO_WORD _C0 :16; + }bitc; + }OCCP6STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _C00 :1; + IO_WORD _C01 :1; + IO_WORD _C02 :1; + IO_WORD _C03 :1; + IO_WORD _C04 :1; + IO_WORD _C05 :1; + IO_WORD _C06 :1; + IO_WORD _C07 :1; + IO_WORD _C08 :1; + IO_WORD _C09 :1; + IO_WORD _C10 :1; + IO_WORD _C11 :1; + IO_WORD _C12 :1; + IO_WORD _C13 :1; + IO_WORD _C14 :1; + IO_WORD _C15 :1; + }bit; + struct{ + IO_WORD _C0 :16; + }bitc; + }OCCP7STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EG00 :1; + IO_BYTE _EG01 :1; + IO_BYTE _EG10 :1; + IO_BYTE _EG11 :1; + IO_BYTE _ICE0 :1; + IO_BYTE _ICE1 :1; + IO_BYTE _ICP0 :1; + IO_BYTE _ICP1 :1; + }bit; + struct{ + IO_BYTE _EG0 :2; + IO_BYTE _EG1 :2; + }bitc; + }ICS01STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IEI0 :1; + IO_BYTE _IEI1 :1; + IO_BYTE _ICUS0 :1; + IO_BYTE :1; + IO_BYTE _ICUS1 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }ICE01STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CP00 :1; + IO_WORD _CP01 :1; + IO_WORD _CP02 :1; + IO_WORD _CP03 :1; + IO_WORD _CP04 :1; + IO_WORD _CP05 :1; + IO_WORD _CP06 :1; + IO_WORD _CP07 :1; + IO_WORD _CP08 :1; + IO_WORD _CP09 :1; + IO_WORD _CP10 :1; + IO_WORD _CP11 :1; + IO_WORD _CP12 :1; + IO_WORD _CP13 :1; + IO_WORD _CP14 :1; + IO_WORD _CP15 :1; + }bit; + struct{ + IO_WORD _CP0 :16; + }bitc; + }IPCP0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CP00 :1; + IO_BYTE _CP01 :1; + IO_BYTE _CP02 :1; + IO_BYTE _CP03 :1; + IO_BYTE _CP04 :1; + IO_BYTE _CP05 :1; + IO_BYTE _CP06 :1; + IO_BYTE _CP07 :1; + }bit; + }IPCPL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CP08 :1; + IO_BYTE _CP09 :1; + IO_BYTE _CP10 :1; + IO_BYTE _CP11 :1; + IO_BYTE _CP12 :1; + IO_BYTE _CP13 :1; + IO_BYTE _CP14 :1; + IO_BYTE _CP15 :1; + }bit; + }IPCPH0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CP00 :1; + IO_WORD _CP01 :1; + IO_WORD _CP02 :1; + IO_WORD _CP03 :1; + IO_WORD _CP04 :1; + IO_WORD _CP05 :1; + IO_WORD _CP06 :1; + IO_WORD _CP07 :1; + IO_WORD _CP08 :1; + IO_WORD _CP09 :1; + IO_WORD _CP10 :1; + IO_WORD _CP11 :1; + IO_WORD _CP12 :1; + IO_WORD _CP13 :1; + IO_WORD _CP14 :1; + IO_WORD _CP15 :1; + }bit; + struct{ + IO_WORD _CP0 :16; + }bitc; + }IPCP1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CP00 :1; + IO_BYTE _CP01 :1; + IO_BYTE _CP02 :1; + IO_BYTE _CP03 :1; + IO_BYTE _CP04 :1; + IO_BYTE _CP05 :1; + IO_BYTE _CP06 :1; + IO_BYTE _CP07 :1; + }bit; + }IPCPL1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CP08 :1; + IO_BYTE _CP09 :1; + IO_BYTE _CP10 :1; + IO_BYTE _CP11 :1; + IO_BYTE _CP12 :1; + IO_BYTE _CP13 :1; + IO_BYTE _CP14 :1; + IO_BYTE _CP15 :1; + }bit; + }IPCPH1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EG20 :1; + IO_BYTE _EG21 :1; + IO_BYTE _EG30 :1; + IO_BYTE _EG31 :1; + IO_BYTE _ICE2 :1; + IO_BYTE _ICE3 :1; + IO_BYTE _ICP2 :1; + IO_BYTE _ICP3 :1; + }bit; + struct{ + IO_BYTE _EG2 :2; + IO_BYTE _EG3 :2; + }bitc; + }ICS23STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IEI2 :1; + IO_BYTE _IEI3 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }ICE23STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CP00 :1; + IO_WORD _CP01 :1; + IO_WORD _CP02 :1; + IO_WORD _CP03 :1; + IO_WORD _CP04 :1; + IO_WORD _CP05 :1; + IO_WORD _CP06 :1; + IO_WORD _CP07 :1; + IO_WORD _CP08 :1; + IO_WORD _CP09 :1; + IO_WORD _CP10 :1; + IO_WORD _CP11 :1; + IO_WORD _CP12 :1; + IO_WORD _CP13 :1; + IO_WORD _CP14 :1; + IO_WORD _CP15 :1; + }bit; + struct{ + IO_WORD _CP0 :16; + }bitc; + }IPCP2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CP00 :1; + IO_BYTE _CP01 :1; + IO_BYTE _CP02 :1; + IO_BYTE _CP03 :1; + IO_BYTE _CP04 :1; + IO_BYTE _CP05 :1; + IO_BYTE _CP06 :1; + IO_BYTE _CP07 :1; + }bit; + }IPCPL2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CP08 :1; + IO_BYTE _CP09 :1; + IO_BYTE _CP10 :1; + IO_BYTE _CP11 :1; + IO_BYTE _CP12 :1; + IO_BYTE _CP13 :1; + IO_BYTE _CP14 :1; + IO_BYTE _CP15 :1; + }bit; + }IPCPH2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CP00 :1; + IO_WORD _CP01 :1; + IO_WORD _CP02 :1; + IO_WORD _CP03 :1; + IO_WORD _CP04 :1; + IO_WORD _CP05 :1; + IO_WORD _CP06 :1; + IO_WORD _CP07 :1; + IO_WORD _CP08 :1; + IO_WORD _CP09 :1; + IO_WORD _CP10 :1; + IO_WORD _CP11 :1; + IO_WORD _CP12 :1; + IO_WORD _CP13 :1; + IO_WORD _CP14 :1; + IO_WORD _CP15 :1; + }bit; + struct{ + IO_WORD _CP0 :16; + }bitc; + }IPCP3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CP00 :1; + IO_BYTE _CP01 :1; + IO_BYTE _CP02 :1; + IO_BYTE _CP03 :1; + IO_BYTE _CP04 :1; + IO_BYTE _CP05 :1; + IO_BYTE _CP06 :1; + IO_BYTE _CP07 :1; + }bit; + }IPCPL3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CP08 :1; + IO_BYTE _CP09 :1; + IO_BYTE _CP10 :1; + IO_BYTE _CP11 :1; + IO_BYTE _CP12 :1; + IO_BYTE _CP13 :1; + IO_BYTE _CP14 :1; + IO_BYTE _CP15 :1; + }bit; + }IPCPH3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EG40 :1; + IO_BYTE _EG41 :1; + IO_BYTE _EG50 :1; + IO_BYTE _EG51 :1; + IO_BYTE _ICE4 :1; + IO_BYTE _ICE5 :1; + IO_BYTE _ICP4 :1; + IO_BYTE _ICP5 :1; + }bit; + struct{ + IO_BYTE _EG4 :2; + IO_BYTE _EG5 :2; + }bitc; + }ICS45STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IEI4 :1; + IO_BYTE _IEI5 :1; + IO_BYTE _ICUS4 :1; + IO_BYTE :1; + IO_BYTE _ICUS5 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }ICE45STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CP00 :1; + IO_WORD _CP01 :1; + IO_WORD _CP02 :1; + IO_WORD _CP03 :1; + IO_WORD _CP04 :1; + IO_WORD _CP05 :1; + IO_WORD _CP06 :1; + IO_WORD _CP07 :1; + IO_WORD _CP08 :1; + IO_WORD _CP09 :1; + IO_WORD _CP10 :1; + IO_WORD _CP11 :1; + IO_WORD _CP12 :1; + IO_WORD _CP13 :1; + IO_WORD _CP14 :1; + IO_WORD _CP15 :1; + }bit; + struct{ + IO_WORD _CP0 :16; + }bitc; + }IPCP4STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CP00 :1; + IO_BYTE _CP01 :1; + IO_BYTE _CP02 :1; + IO_BYTE _CP03 :1; + IO_BYTE _CP04 :1; + IO_BYTE _CP05 :1; + IO_BYTE _CP06 :1; + IO_BYTE _CP07 :1; + }bit; + }IPCPL4STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CP08 :1; + IO_BYTE _CP09 :1; + IO_BYTE _CP10 :1; + IO_BYTE _CP11 :1; + IO_BYTE _CP12 :1; + IO_BYTE _CP13 :1; + IO_BYTE _CP14 :1; + IO_BYTE _CP15 :1; + }bit; + }IPCPH4STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CP00 :1; + IO_WORD _CP01 :1; + IO_WORD _CP02 :1; + IO_WORD _CP03 :1; + IO_WORD _CP04 :1; + IO_WORD _CP05 :1; + IO_WORD _CP06 :1; + IO_WORD _CP07 :1; + IO_WORD _CP08 :1; + IO_WORD _CP09 :1; + IO_WORD _CP10 :1; + IO_WORD _CP11 :1; + IO_WORD _CP12 :1; + IO_WORD _CP13 :1; + IO_WORD _CP14 :1; + IO_WORD _CP15 :1; + }bit; + struct{ + IO_WORD _CP0 :16; + }bitc; + }IPCP5STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CP00 :1; + IO_BYTE _CP01 :1; + IO_BYTE _CP02 :1; + IO_BYTE _CP03 :1; + IO_BYTE _CP04 :1; + IO_BYTE _CP05 :1; + IO_BYTE _CP06 :1; + IO_BYTE _CP07 :1; + }bit; + }IPCPL5STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CP08 :1; + IO_BYTE _CP09 :1; + IO_BYTE _CP10 :1; + IO_BYTE _CP11 :1; + IO_BYTE _CP12 :1; + IO_BYTE _CP13 :1; + IO_BYTE _CP14 :1; + IO_BYTE _CP15 :1; + }bit; + }IPCPH5STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EG60 :1; + IO_BYTE _EG61 :1; + IO_BYTE _EG70 :1; + IO_BYTE _EG71 :1; + IO_BYTE _ICE6 :1; + IO_BYTE _ICE7 :1; + IO_BYTE _ICP6 :1; + IO_BYTE _ICP7 :1; + }bit; + struct{ + IO_BYTE _EG6 :2; + IO_BYTE _EG7 :2; + }bitc; + }ICS67STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IEI6 :1; + IO_BYTE _IEI7 :1; + IO_BYTE _ICUS6 :1; + IO_BYTE :1; + IO_BYTE _ICUS7 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }ICE67STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CP00 :1; + IO_WORD _CP01 :1; + IO_WORD _CP02 :1; + IO_WORD _CP03 :1; + IO_WORD _CP04 :1; + IO_WORD _CP05 :1; + IO_WORD _CP06 :1; + IO_WORD _CP07 :1; + IO_WORD _CP08 :1; + IO_WORD _CP09 :1; + IO_WORD _CP10 :1; + IO_WORD _CP11 :1; + IO_WORD _CP12 :1; + IO_WORD _CP13 :1; + IO_WORD _CP14 :1; + IO_WORD _CP15 :1; + }bit; + struct{ + IO_WORD _CP0 :16; + }bitc; + }IPCP6STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CP00 :1; + IO_BYTE _CP01 :1; + IO_BYTE _CP02 :1; + IO_BYTE _CP03 :1; + IO_BYTE _CP04 :1; + IO_BYTE _CP05 :1; + IO_BYTE _CP06 :1; + IO_BYTE _CP07 :1; + }bit; + }IPCPL6STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CP08 :1; + IO_BYTE _CP09 :1; + IO_BYTE _CP10 :1; + IO_BYTE _CP11 :1; + IO_BYTE _CP12 :1; + IO_BYTE _CP13 :1; + IO_BYTE _CP14 :1; + IO_BYTE _CP15 :1; + }bit; + }IPCPH6STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _CP00 :1; + IO_WORD _CP01 :1; + IO_WORD _CP02 :1; + IO_WORD _CP03 :1; + IO_WORD _CP04 :1; + IO_WORD _CP05 :1; + IO_WORD _CP06 :1; + IO_WORD _CP07 :1; + IO_WORD _CP08 :1; + IO_WORD _CP09 :1; + IO_WORD _CP10 :1; + IO_WORD _CP11 :1; + IO_WORD _CP12 :1; + IO_WORD _CP13 :1; + IO_WORD _CP14 :1; + IO_WORD _CP15 :1; + }bit; + struct{ + IO_WORD _CP0 :16; + }bitc; + }IPCP7STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CP00 :1; + IO_BYTE _CP01 :1; + IO_BYTE _CP02 :1; + IO_BYTE _CP03 :1; + IO_BYTE _CP04 :1; + IO_BYTE _CP05 :1; + IO_BYTE _CP06 :1; + IO_BYTE _CP07 :1; + }bit; + }IPCPL7STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CP08 :1; + IO_BYTE _CP09 :1; + IO_BYTE _CP10 :1; + IO_BYTE _CP11 :1; + IO_BYTE _CP12 :1; + IO_BYTE _CP13 :1; + IO_BYTE _CP14 :1; + IO_BYTE _CP15 :1; + }bit; + }IPCPH7STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EN0 :1; + IO_BYTE _EN1 :1; + IO_BYTE _EN2 :1; + IO_BYTE _EN3 :1; + IO_BYTE _EN4 :1; + IO_BYTE _EN5 :1; + IO_BYTE _EN6 :1; + IO_BYTE _EN7 :1; + }bit; + }ENIR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ER0 :1; + IO_BYTE _ER1 :1; + IO_BYTE _ER2 :1; + IO_BYTE _ER3 :1; + IO_BYTE _ER4 :1; + IO_BYTE _ER5 :1; + IO_BYTE _ER6 :1; + IO_BYTE _ER7 :1; + }bit; + }EIRR0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _LA0 :1; + IO_WORD _LB0 :1; + IO_WORD _LA1 :1; + IO_WORD _LB1 :1; + IO_WORD _LA2 :1; + IO_WORD _LB2 :1; + IO_WORD _LA3 :1; + IO_WORD _LB3 :1; + IO_WORD _LA4 :1; + IO_WORD _LB4 :1; + IO_WORD _LA5 :1; + IO_WORD _LB5 :1; + IO_WORD _LA6 :1; + IO_WORD _LB6 :1; + IO_WORD _LA7 :1; + IO_WORD _LB7 :1; + }bit; + }ELVR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _LA0 :1; + IO_BYTE _LB0 :1; + IO_BYTE _LA1 :1; + IO_BYTE _LB1 :1; + IO_BYTE _LA2 :1; + IO_BYTE _LB2 :1; + IO_BYTE _LA3 :1; + IO_BYTE _LB3 :1; + }bit; + }ELVRL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _LA4 :1; + IO_BYTE _LB4 :1; + IO_BYTE _LA5 :1; + IO_BYTE _LB5 :1; + IO_BYTE _LA6 :1; + IO_BYTE _LB6 :1; + IO_BYTE _LA7 :1; + IO_BYTE _LB7 :1; + }bit; + }ELVRH0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EN8 :1; + IO_BYTE _EN9 :1; + IO_BYTE _EN10 :1; + IO_BYTE _EN11 :1; + IO_BYTE _EN12 :1; + IO_BYTE _EN13 :1; + IO_BYTE _EN14 :1; + IO_BYTE _EN15 :1; + }bit; + }ENIR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ER8 :1; + IO_BYTE _ER9 :1; + IO_BYTE _ER10 :1; + IO_BYTE _ER11 :1; + IO_BYTE _ER12 :1; + IO_BYTE _ER13 :1; + IO_BYTE _ER14 :1; + IO_BYTE _ER15 :1; + }bit; + }EIRR1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _LA8 :1; + IO_WORD _LB8 :1; + IO_WORD _LA9 :1; + IO_WORD _LB9 :1; + IO_WORD _LA10 :1; + IO_WORD _LB10 :1; + IO_WORD _LA11 :1; + IO_WORD _LB11 :1; + IO_WORD _LA12 :1; + IO_WORD _LB12 :1; + IO_WORD _LA13 :1; + IO_WORD _LB13 :1; + IO_WORD _LA14 :1; + IO_WORD _LB14 :1; + IO_WORD _LA15 :1; + IO_WORD _LB15 :1; + }bit; + }ELVR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _LA8 :1; + IO_BYTE _LB8 :1; + IO_BYTE _LA9 :1; + IO_BYTE _LB9 :1; + IO_BYTE _LA10 :1; + IO_BYTE _LB10 :1; + IO_BYTE _LA11 :1; + IO_BYTE _LB11 :1; + }bit; + }ELVRL1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _LA12 :1; + IO_BYTE _LB12 :1; + IO_BYTE _LA13 :1; + IO_BYTE _LB13 :1; + IO_BYTE _LA14 :1; + IO_BYTE _LB14 :1; + IO_BYTE _LA15 :1; + IO_BYTE _LB15 :1; + }bit; + }ELVRH1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _TRG :1; + IO_WORD _CNTE :1; + IO_WORD _UF :1; + IO_WORD _INTE :1; + IO_WORD _RELD :1; + IO_WORD _OUTL :1; + IO_WORD _OUTE :1; + IO_WORD _MOD0 :1; + IO_WORD _MOD1 :1; + IO_WORD _MOD2 :1; + IO_WORD _CSL0 :1; + IO_WORD _CSL1 :1; + IO_WORD _FSEL :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD :10; + IO_WORD _CSL :2; + }bitc; + }TMCSR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TRG :1; + IO_BYTE _CNTE :1; + IO_BYTE _UF :1; + IO_BYTE _INTE :1; + IO_BYTE _RELD :1; + IO_BYTE _OUTL :1; + IO_BYTE _OUTE :1; + IO_BYTE _MOD0 :1; + }bit; + }TMCSRL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MOD1 :1; + IO_BYTE _MOD2 :1; + IO_BYTE _CSL0 :1; + IO_BYTE _CSL1 :1; + IO_BYTE _FSEL :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _CSL :2; + }bitc; + }TMCSRH0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _TRG :1; + IO_WORD _CNTE :1; + IO_WORD _UF :1; + IO_WORD _INTE :1; + IO_WORD _RELD :1; + IO_WORD _OUTL :1; + IO_WORD _OUTE :1; + IO_WORD _MOD0 :1; + IO_WORD _MOD1 :1; + IO_WORD _MOD2 :1; + IO_WORD _CSL0 :1; + IO_WORD _CSL1 :1; + IO_WORD _FSEL :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD :10; + IO_WORD _CSL :2; + }bitc; + }TMCSR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TRG :1; + IO_BYTE _CNTE :1; + IO_BYTE _UF :1; + IO_BYTE _INTE :1; + IO_BYTE _RELD :1; + IO_BYTE _OUTL :1; + IO_BYTE _OUTE :1; + IO_BYTE _MOD0 :1; + }bit; + }TMCSRL1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MOD1 :1; + IO_BYTE _MOD2 :1; + IO_BYTE _CSL0 :1; + IO_BYTE _CSL1 :1; + IO_BYTE _FSEL :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _CSL :2; + }bitc; + }TMCSRH1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _TRG :1; + IO_WORD _CNTE :1; + IO_WORD _UF :1; + IO_WORD _INTE :1; + IO_WORD _RELD :1; + IO_WORD _OUTL :1; + IO_WORD _OUTE :1; + IO_WORD _MOD0 :1; + IO_WORD _MOD1 :1; + IO_WORD _MOD2 :1; + IO_WORD _CSL0 :1; + IO_WORD _CSL1 :1; + IO_WORD _FSEL :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD :10; + IO_WORD _CSL :2; + }bitc; + }TMCSR2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TRG :1; + IO_BYTE _CNTE :1; + IO_BYTE _UF :1; + IO_BYTE _INTE :1; + IO_BYTE _RELD :1; + IO_BYTE _OUTL :1; + IO_BYTE _OUTE :1; + IO_BYTE _MOD0 :1; + }bit; + }TMCSRL2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MOD1 :1; + IO_BYTE _MOD2 :1; + IO_BYTE _CSL0 :1; + IO_BYTE _CSL1 :1; + IO_BYTE _FSEL :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _CSL :2; + }bitc; + }TMCSRH2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _TRG :1; + IO_WORD _CNTE :1; + IO_WORD _UF :1; + IO_WORD _INTE :1; + IO_WORD _RELD :1; + IO_WORD _OUTL :1; + IO_WORD _OUTE :1; + IO_WORD _MOD0 :1; + IO_WORD _MOD1 :1; + IO_WORD _MOD2 :1; + IO_WORD _CSL0 :1; + IO_WORD _CSL1 :1; + IO_WORD _FSEL :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD :10; + IO_WORD _CSL :2; + }bitc; + }TMCSR3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TRG :1; + IO_BYTE _CNTE :1; + IO_BYTE _UF :1; + IO_BYTE _INTE :1; + IO_BYTE _RELD :1; + IO_BYTE _OUTL :1; + IO_BYTE _OUTE :1; + IO_BYTE _MOD0 :1; + }bit; + }TMCSRL3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MOD1 :1; + IO_BYTE _MOD2 :1; + IO_BYTE _CSL0 :1; + IO_BYTE _CSL1 :1; + IO_BYTE _FSEL :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _CSL :2; + }bitc; + }TMCSRH3STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _TRG :1; + IO_WORD _CNTE :1; + IO_WORD _UF :1; + IO_WORD _INTE :1; + IO_WORD _RELD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _MOD0 :1; + IO_WORD _MOD1 :1; + IO_WORD _MOD2 :1; + IO_WORD _CSL0 :1; + IO_WORD _CSL1 :1; + IO_WORD _FSEL :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD :10; + IO_WORD _CSL :2; + }bitc; + }TMCSR6STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TRG :1; + IO_BYTE _CNTE :1; + IO_BYTE _UF :1; + IO_BYTE _INTE :1; + IO_BYTE _RELD :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _MOD0 :1; + }bit; + }TMCSRL6STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MOD1 :1; + IO_BYTE _MOD2 :1; + IO_BYTE _CSL0 :1; + IO_BYTE _CSL1 :1; + IO_BYTE _FSEL :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _CSL :2; + }bitc; + }TMCSRH6STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _TSEL00 :1; + IO_WORD _TSEL01 :1; + IO_WORD _TSEL02 :1; + IO_WORD _TSEL03 :1; + IO_WORD _TSEL10 :1; + IO_WORD _TSEL11 :1; + IO_WORD _TSEL12 :1; + IO_WORD _TSEL13 :1; + IO_WORD _TSEL20 :1; + IO_WORD _TSEL21 :1; + IO_WORD _TSEL22 :1; + IO_WORD _TSEL23 :1; + IO_WORD _TSEL30 :1; + IO_WORD _TSEL31 :1; + IO_WORD _TSEL32 :1; + IO_WORD _TSEL33 :1; + }bit; + struct{ + IO_WORD _TSEL0 :4; + IO_WORD _TSEL1 :4; + IO_WORD _TSEL2 :4; + IO_WORD _TSEL3 :4; + }bitc; + }GCN10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TSEL00 :1; + IO_BYTE _TSEL01 :1; + IO_BYTE _TSEL02 :1; + IO_BYTE _TSEL03 :1; + IO_BYTE _TSEL10 :1; + IO_BYTE _TSEL11 :1; + IO_BYTE _TSEL12 :1; + IO_BYTE _TSEL13 :1; + }bit; + struct{ + IO_BYTE _TSEL0 :4; + IO_BYTE _TSEL1 :4; + }bitc; + }GCN1L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TSEL20 :1; + IO_BYTE _TSEL21 :1; + IO_BYTE _TSEL22 :1; + IO_BYTE _TSEL23 :1; + IO_BYTE _TSEL30 :1; + IO_BYTE _TSEL31 :1; + IO_BYTE _TSEL32 :1; + IO_BYTE _TSEL33 :1; + }bit; + struct{ + IO_BYTE _TSEL2 :4; + IO_BYTE _TSEL3 :4; + }bitc; + }GCN1H0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _EN0 :1; + IO_WORD _EN1 :1; + IO_WORD _EN2 :1; + IO_WORD _EN3 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CKSEL0 :1; + IO_WORD _CKSEL1 :1; + IO_WORD _CKSEL2 :1; + IO_WORD _CKSEL3 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD _EN :4; + IO_WORD :4; + IO_WORD _CKSEL :4; + }bitc; + }GCN20STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EN0 :1; + IO_BYTE _EN1 :1; + IO_BYTE _EN2 :1; + IO_BYTE _EN3 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _EN :4; + }bitc; + }GCN2L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CKSEL0 :1; + IO_BYTE _CKSEL1 :1; + IO_BYTE _CKSEL2 :1; + IO_BYTE _CKSEL3 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _CKSEL :4; + }bitc; + }GCN2H0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PTMR0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PCSR0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PDUT0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _OSEL :1; + IO_WORD _OE :1; + IO_WORD _IRS0 :1; + IO_WORD _IRS1 :1; + IO_WORD _IRQF :1; + IO_WORD _IREN :1; + IO_WORD _EGS0 :1; + IO_WORD _EGS1 :1; + IO_WORD :1; + IO_WORD _PGMS :1; + IO_WORD _CKS0 :1; + IO_WORD _CKS1 :1; + IO_WORD _RTRG :1; + IO_WORD _MDSE :1; + IO_WORD _STGR :1; + IO_WORD _CNTE :1; + }bit; + struct{ + IO_WORD :2; + IO_WORD _IRS :2; + IO_WORD :2; + IO_WORD _EGS :2; + IO_WORD :2; + IO_WORD _CKS :2; + }bitc; + }PCN0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OSEL :1; + IO_BYTE _OE :1; + IO_BYTE _IRS0 :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRQF :1; + IO_BYTE _IREN :1; + IO_BYTE _EGS0 :1; + IO_BYTE _EGS1 :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _IRS :2; + IO_BYTE :2; + IO_BYTE _EGS :2; + }bitc; + }PCNL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _PGMS :1; + IO_BYTE _CKS0 :1; + IO_BYTE _CKS1 :1; + IO_BYTE _RTRG :1; + IO_BYTE _MDSE :1; + IO_BYTE _STGR :1; + IO_BYTE _CNTE :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _CKS :2; + }bitc; + }PCNH0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PTMR1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PCSR1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PDUT1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _OSEL :1; + IO_WORD _OE :1; + IO_WORD _IRS0 :1; + IO_WORD _IRS1 :1; + IO_WORD _IRQF :1; + IO_WORD _IREN :1; + IO_WORD _EGS0 :1; + IO_WORD _EGS1 :1; + IO_WORD :1; + IO_WORD _PGMS :1; + IO_WORD _CKS0 :1; + IO_WORD _CKS1 :1; + IO_WORD _RTRG :1; + IO_WORD _MDSE :1; + IO_WORD _STGR :1; + IO_WORD _CNTE :1; + }bit; + struct{ + IO_WORD :2; + IO_WORD _IRS :2; + IO_WORD :2; + IO_WORD _EGS :2; + IO_WORD :2; + IO_WORD _CKS :2; + }bitc; + }PCN1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OSEL :1; + IO_BYTE _OE :1; + IO_BYTE _IRS0 :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRQF :1; + IO_BYTE _IREN :1; + IO_BYTE _EGS0 :1; + IO_BYTE _EGS1 :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _IRS :2; + IO_BYTE :2; + IO_BYTE _EGS :2; + }bitc; + }PCNL1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _PGMS :1; + IO_BYTE _CKS0 :1; + IO_BYTE _CKS1 :1; + IO_BYTE _RTRG :1; + IO_BYTE _MDSE :1; + IO_BYTE _STGR :1; + IO_BYTE _CNTE :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _CKS :2; + }bitc; + }PCNH1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PTMR2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PCSR2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PDUT2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _OSEL :1; + IO_WORD _OE :1; + IO_WORD _IRS0 :1; + IO_WORD _IRS1 :1; + IO_WORD _IRQF :1; + IO_WORD _IREN :1; + IO_WORD _EGS0 :1; + IO_WORD _EGS1 :1; + IO_WORD :1; + IO_WORD _PGMS :1; + IO_WORD _CKS0 :1; + IO_WORD _CKS1 :1; + IO_WORD _RTRG :1; + IO_WORD _MDSE :1; + IO_WORD _STGR :1; + IO_WORD _CNTE :1; + }bit; + struct{ + IO_WORD :2; + IO_WORD _IRS :2; + IO_WORD :2; + IO_WORD _EGS :2; + IO_WORD :2; + IO_WORD _CKS :2; + }bitc; + }PCN2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OSEL :1; + IO_BYTE _OE :1; + IO_BYTE _IRS0 :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRQF :1; + IO_BYTE _IREN :1; + IO_BYTE _EGS0 :1; + IO_BYTE _EGS1 :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _IRS :2; + IO_BYTE :2; + IO_BYTE _EGS :2; + }bitc; + }PCNL2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _PGMS :1; + IO_BYTE _CKS0 :1; + IO_BYTE _CKS1 :1; + IO_BYTE _RTRG :1; + IO_BYTE _MDSE :1; + IO_BYTE _STGR :1; + IO_BYTE _CNTE :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _CKS :2; + }bitc; + }PCNH2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PTMR3STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PCSR3STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PDUT3STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _OSEL :1; + IO_WORD _OE :1; + IO_WORD _IRS0 :1; + IO_WORD _IRS1 :1; + IO_WORD _IRQF :1; + IO_WORD _IREN :1; + IO_WORD _EGS0 :1; + IO_WORD _EGS1 :1; + IO_WORD :1; + IO_WORD _PGMS :1; + IO_WORD _CKS0 :1; + IO_WORD _CKS1 :1; + IO_WORD _RTRG :1; + IO_WORD _MDSE :1; + IO_WORD _STGR :1; + IO_WORD _CNTE :1; + }bit; + struct{ + IO_WORD :2; + IO_WORD _IRS :2; + IO_WORD :2; + IO_WORD _EGS :2; + IO_WORD :2; + IO_WORD _CKS :2; + }bitc; + }PCN3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OSEL :1; + IO_BYTE _OE :1; + IO_BYTE _IRS0 :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRQF :1; + IO_BYTE _IREN :1; + IO_BYTE _EGS0 :1; + IO_BYTE _EGS1 :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _IRS :2; + IO_BYTE :2; + IO_BYTE _EGS :2; + }bitc; + }PCNL3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _PGMS :1; + IO_BYTE _CKS0 :1; + IO_BYTE _CKS1 :1; + IO_BYTE _RTRG :1; + IO_BYTE _MDSE :1; + IO_BYTE _STGR :1; + IO_BYTE _CNTE :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _CKS :2; + }bitc; + }PCNH3STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _TSEL00 :1; + IO_WORD _TSEL01 :1; + IO_WORD _TSEL02 :1; + IO_WORD _TSEL03 :1; + IO_WORD _TSEL10 :1; + IO_WORD _TSEL11 :1; + IO_WORD _TSEL12 :1; + IO_WORD _TSEL13 :1; + IO_WORD _TSEL20 :1; + IO_WORD _TSEL21 :1; + IO_WORD _TSEL22 :1; + IO_WORD _TSEL23 :1; + IO_WORD _TSEL30 :1; + IO_WORD _TSEL31 :1; + IO_WORD _TSEL32 :1; + IO_WORD _TSEL33 :1; + }bit; + struct{ + IO_WORD _TSEL0 :4; + IO_WORD _TSEL1 :4; + IO_WORD _TSEL2 :4; + IO_WORD _TSEL3 :4; + }bitc; + }GCN11STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TSEL00 :1; + IO_BYTE _TSEL01 :1; + IO_BYTE _TSEL02 :1; + IO_BYTE _TSEL03 :1; + IO_BYTE _TSEL10 :1; + IO_BYTE _TSEL11 :1; + IO_BYTE _TSEL12 :1; + IO_BYTE _TSEL13 :1; + }bit; + struct{ + IO_BYTE _TSEL0 :4; + IO_BYTE _TSEL1 :4; + }bitc; + }GCN1L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TSEL20 :1; + IO_BYTE _TSEL21 :1; + IO_BYTE _TSEL22 :1; + IO_BYTE _TSEL23 :1; + IO_BYTE _TSEL30 :1; + IO_BYTE _TSEL31 :1; + IO_BYTE _TSEL32 :1; + IO_BYTE _TSEL33 :1; + }bit; + struct{ + IO_BYTE _TSEL2 :4; + IO_BYTE _TSEL3 :4; + }bitc; + }GCN1H1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _EN0 :1; + IO_WORD _EN1 :1; + IO_WORD _EN2 :1; + IO_WORD _EN3 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CKSEL0 :1; + IO_WORD _CKSEL1 :1; + IO_WORD _CKSEL2 :1; + IO_WORD _CKSEL3 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD :8; + IO_WORD _CKSEL :4; + }bitc; + }GCN21STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EN0 :1; + IO_BYTE _EN1 :1; + IO_BYTE _EN2 :1; + IO_BYTE _EN3 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }GCN2L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CKSEL0 :1; + IO_BYTE _CKSEL1 :1; + IO_BYTE _CKSEL2 :1; + IO_BYTE _CKSEL3 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _CKSEL :4; + }bitc; + }GCN2H1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PTMR4STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PCSR4STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PDUT4STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _OSEL :1; + IO_WORD _OE :1; + IO_WORD _IRS0 :1; + IO_WORD _IRS1 :1; + IO_WORD _IRQF :1; + IO_WORD _IREN :1; + IO_WORD _EGS0 :1; + IO_WORD _EGS1 :1; + IO_WORD :1; + IO_WORD _PGMS :1; + IO_WORD _CKS0 :1; + IO_WORD _CKS1 :1; + IO_WORD _RTRG :1; + IO_WORD _MDSE :1; + IO_WORD _STGR :1; + IO_WORD _CNTE :1; + }bit; + struct{ + IO_WORD :2; + IO_WORD _IRS :2; + IO_WORD :2; + IO_WORD _EGS :2; + IO_WORD :2; + IO_WORD _CKS :2; + }bitc; + }PCN4STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OSEL :1; + IO_BYTE _OE :1; + IO_BYTE _IRS0 :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRQF :1; + IO_BYTE _IREN :1; + IO_BYTE _EGS0 :1; + IO_BYTE _EGS1 :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _IRS :2; + IO_BYTE :2; + IO_BYTE _EGS :2; + }bitc; + }PCNL4STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _PGMS :1; + IO_BYTE _CKS0 :1; + IO_BYTE _CKS1 :1; + IO_BYTE _RTRG :1; + IO_BYTE _MDSE :1; + IO_BYTE _STGR :1; + IO_BYTE _CNTE :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _CKS :2; + }bitc; + }PCNH4STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PTMR5STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PCSR5STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PDUT5STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _OSEL :1; + IO_WORD _OE :1; + IO_WORD _IRS0 :1; + IO_WORD _IRS1 :1; + IO_WORD _IRQF :1; + IO_WORD _IREN :1; + IO_WORD _EGS0 :1; + IO_WORD _EGS1 :1; + IO_WORD :1; + IO_WORD _PGMS :1; + IO_WORD _CKS0 :1; + IO_WORD _CKS1 :1; + IO_WORD _RTRG :1; + IO_WORD _MDSE :1; + IO_WORD _STGR :1; + IO_WORD _CNTE :1; + }bit; + struct{ + IO_WORD :2; + IO_WORD _IRS :2; + IO_WORD :2; + IO_WORD _EGS :2; + IO_WORD :2; + IO_WORD _CKS :2; + }bitc; + }PCN5STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OSEL :1; + IO_BYTE _OE :1; + IO_BYTE _IRS0 :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRQF :1; + IO_BYTE _IREN :1; + IO_BYTE _EGS0 :1; + IO_BYTE _EGS1 :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _IRS :2; + IO_BYTE :2; + IO_BYTE _EGS :2; + }bitc; + }PCNL5STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _PGMS :1; + IO_BYTE _CKS0 :1; + IO_BYTE _CKS1 :1; + IO_BYTE _RTRG :1; + IO_BYTE _MDSE :1; + IO_BYTE _STGR :1; + IO_BYTE _CNTE :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _CKS :2; + }bitc; + }PCNH5STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ADT :1; + IO_BYTE _GCA :1; + IO_BYTE _AAS :1; + IO_BYTE _TRX :1; + IO_BYTE _LRB :1; + IO_BYTE _AL :1; + IO_BYTE _RSC :1; + IO_BYTE _BB :1; + }bit; + }IBSR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INT :1; + IO_BYTE _INTE :1; + IO_BYTE _GCAA :1; + IO_BYTE _ACK :1; + IO_BYTE _MSS :1; + IO_BYTE _SCC :1; + IO_BYTE _BEIE :1; + IO_BYTE _BER :1; + }bit; + }IBCR0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _TA0 :1; + IO_WORD _TA1 :1; + IO_WORD _TA2 :1; + IO_WORD _TA3 :1; + IO_WORD _TA4 :1; + IO_WORD _TA5 :1; + IO_WORD _TA6 :1; + IO_WORD _TA7 :1; + IO_WORD _TA8 :1; + IO_WORD _TA9 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD _TA :10; + }bitc; + }ITBA0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TA0 :1; + IO_BYTE _TA1 :1; + IO_BYTE _TA2 :1; + IO_BYTE _TA3 :1; + IO_BYTE _TA4 :1; + IO_BYTE _TA5 :1; + IO_BYTE _TA6 :1; + IO_BYTE _TA7 :1; + }bit; + }ITBAL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TA8 :1; + IO_BYTE _TA9 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }ITBAH0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _TM0 :1; + IO_WORD _TM1 :1; + IO_WORD _TM2 :1; + IO_WORD _TM3 :1; + IO_WORD _TM4 :1; + IO_WORD _TM5 :1; + IO_WORD _TM6 :1; + IO_WORD _TM7 :1; + IO_WORD _TM8 :1; + IO_WORD _TM9 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _RAL :1; + IO_WORD _ENTB :1; + }bit; + struct{ + IO_WORD _TM :10; + }bitc; + }ITMK0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TM0 :1; + IO_BYTE _TM1 :1; + IO_BYTE _TM2 :1; + IO_BYTE _TM3 :1; + IO_BYTE _TM4 :1; + IO_BYTE _TM5 :1; + IO_BYTE _TM6 :1; + IO_BYTE _TM7 :1; + }bit; + }ITMKL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TM8 :1; + IO_BYTE _TM9 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _RAL :1; + IO_BYTE _ENTB :1; + }bit; + }ITMKH0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SA0 :1; + IO_BYTE _SA1 :1; + IO_BYTE _SA2 :1; + IO_BYTE _SA3 :1; + IO_BYTE _SA4 :1; + IO_BYTE _SA5 :1; + IO_BYTE _SA6 :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _SA :7; + }bitc; + }ISBA0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SM0 :1; + IO_BYTE _SM1 :1; + IO_BYTE _SM2 :1; + IO_BYTE _SM3 :1; + IO_BYTE _SM4 :1; + IO_BYTE _SM5 :1; + IO_BYTE _SM6 :1; + IO_BYTE _ENSB :1; + }bit; + struct{ + IO_BYTE _SM :7; + }bitc; + }ISMK0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D0 :1; + IO_BYTE _D1 :1; + IO_BYTE _D2 :1; + IO_BYTE _D3 :1; + IO_BYTE _D4 :1; + IO_BYTE _D5 :1; + IO_BYTE _D6 :1; + IO_BYTE _D7 :1; + }bit; + }IDAR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CS0 :1; + IO_BYTE _CS1 :1; + IO_BYTE _CS2 :1; + IO_BYTE _CS3 :1; + IO_BYTE _CS4 :1; + IO_BYTE _EN :1; + IO_BYTE _NSF :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _CS :5; + }bitc; + }ICCR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ADT :1; + IO_BYTE _GCA :1; + IO_BYTE _AAS :1; + IO_BYTE _TRX :1; + IO_BYTE _LRB :1; + IO_BYTE _AL :1; + IO_BYTE _RSC :1; + IO_BYTE _BB :1; + }bit; + }IBSR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INT :1; + IO_BYTE _INTE :1; + IO_BYTE _GCAA :1; + IO_BYTE _ACK :1; + IO_BYTE _MSS :1; + IO_BYTE _SCC :1; + IO_BYTE _BEIE :1; + IO_BYTE _BER :1; + }bit; + }IBCR1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _TA0 :1; + IO_WORD _TA1 :1; + IO_WORD _TA2 :1; + IO_WORD _TA3 :1; + IO_WORD _TA4 :1; + IO_WORD _TA5 :1; + IO_WORD _TA6 :1; + IO_WORD _TA7 :1; + IO_WORD _TA8 :1; + IO_WORD _TA9 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD _TA :10; + }bitc; + }ITBA1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TA0 :1; + IO_BYTE _TA1 :1; + IO_BYTE _TA2 :1; + IO_BYTE _TA3 :1; + IO_BYTE _TA4 :1; + IO_BYTE _TA5 :1; + IO_BYTE _TA6 :1; + IO_BYTE _TA7 :1; + }bit; + }ITBAL1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TA8 :1; + IO_BYTE _TA9 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }ITBAH1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _TM0 :1; + IO_WORD _TM1 :1; + IO_WORD _TM2 :1; + IO_WORD _TM3 :1; + IO_WORD _TM4 :1; + IO_WORD _TM5 :1; + IO_WORD _TM6 :1; + IO_WORD _TM7 :1; + IO_WORD _TM8 :1; + IO_WORD _TM9 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _RAL :1; + IO_WORD _ENTB :1; + }bit; + struct{ + IO_WORD _TM :10; + }bitc; + }ITMK1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TM0 :1; + IO_BYTE _TM1 :1; + IO_BYTE _TM2 :1; + IO_BYTE _TM3 :1; + IO_BYTE _TM4 :1; + IO_BYTE _TM5 :1; + IO_BYTE _TM6 :1; + IO_BYTE _TM7 :1; + }bit; + }ITMKL1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TM8 :1; + IO_BYTE _TM9 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _RAL :1; + IO_BYTE _ENTB :1; + }bit; + }ITMKH1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SA0 :1; + IO_BYTE _SA1 :1; + IO_BYTE _SA2 :1; + IO_BYTE _SA3 :1; + IO_BYTE _SA4 :1; + IO_BYTE _SA5 :1; + IO_BYTE _SA6 :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _SA :7; + }bitc; + }ISBA1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SM0 :1; + IO_BYTE _SM1 :1; + IO_BYTE _SM2 :1; + IO_BYTE _SM3 :1; + IO_BYTE _SM4 :1; + IO_BYTE _SM5 :1; + IO_BYTE _SM6 :1; + IO_BYTE _ENSB :1; + }bit; + struct{ + IO_BYTE _SM :7; + }bitc; + }ISMK1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D0 :1; + IO_BYTE _D1 :1; + IO_BYTE _D2 :1; + IO_BYTE _D3 :1; + IO_BYTE _D4 :1; + IO_BYTE _D5 :1; + IO_BYTE _D6 :1; + IO_BYTE _D7 :1; + }bit; + }IDAR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CS0 :1; + IO_BYTE _CS1 :1; + IO_BYTE _CS2 :1; + IO_BYTE _CS3 :1; + IO_BYTE _CS4 :1; + IO_BYTE _EN :1; + IO_BYTE _NSF :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _CS :5; + }bitc; + }ICCR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SOE :1; + IO_BYTE _SCKE :1; + IO_BYTE _UPCL :1; + IO_BYTE _REST :1; + IO_BYTE _EXT :1; + IO_BYTE _OTO :1; + IO_BYTE _MD0 :1; + IO_BYTE _MD1 :1; + }bit; + struct{ + IO_BYTE :6; + IO_BYTE _MD :2; + }bitc; + }SMR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TXE :1; + IO_BYTE _RXE :1; + IO_BYTE _CRE :1; + IO_BYTE _AD :1; + IO_BYTE _CL :1; + IO_BYTE _SBL :1; + IO_BYTE _P :1; + IO_BYTE _PEN :1; + }bit; + }SCR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TIE :1; + IO_BYTE _RIE :1; + IO_BYTE _BDS :1; + IO_BYTE _TDRE :1; + IO_BYTE _RDRF :1; + IO_BYTE _FRE :1; + IO_BYTE _ORE :1; + IO_BYTE _PE :1; + }bit; + }SSR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TBI :1; + IO_BYTE _RBI :1; + IO_BYTE _BIE :1; + IO_BYTE _SSM :1; + IO_BYTE _SCDE :1; + IO_BYTE _MS :1; + IO_BYTE _LBR :1; + IO_BYTE _INV :1; + }bit; + }ECCR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SCES :1; + IO_BYTE _CCO :1; + IO_BYTE _SIOP :1; + IO_BYTE _SOPE :1; + IO_BYTE _LBL0 :1; + IO_BYTE _LBL1 :1; + IO_BYTE _LBD :1; + IO_BYTE _LBIE :1; + }bit; + struct{ + IO_BYTE :4; + IO_BYTE _LBL :2; + }bitc; + }ESCR0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _BGR0 :1; + IO_WORD _BGR1 :1; + IO_WORD _BGR2 :1; + IO_WORD _BGR3 :1; + IO_WORD _BGR4 :1; + IO_WORD _BGR5 :1; + IO_WORD _BGR6 :1; + IO_WORD _BGR7 :1; + IO_WORD _BGR8 :1; + IO_WORD _BGR9 :1; + IO_WORD _BGR10 :1; + IO_WORD _BGR11 :1; + IO_WORD _BGR12 :1; + IO_WORD _BGR13 :1; + IO_WORD _BGR14 :1; + IO_WORD _BGR15 :1; + }bit; + struct{ + IO_WORD _BGR :16; + }bitc; + }BGR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _BGR0 :1; + IO_BYTE _BGR1 :1; + IO_BYTE _BGR2 :1; + IO_BYTE _BGR3 :1; + IO_BYTE _BGR4 :1; + IO_BYTE _BGR5 :1; + IO_BYTE _BGR6 :1; + IO_BYTE _BGR7 :1; + }bit; + }BGRL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _BGR8 :1; + IO_BYTE _BGR9 :1; + IO_BYTE _BGR10 :1; + IO_BYTE _BGR11 :1; + IO_BYTE _BGR12 :1; + IO_BYTE _BGR13 :1; + IO_BYTE _BGR14 :1; + IO_BYTE _BGR15 :1; + }bit; + }BGRH0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _AICD :1; + IO_BYTE _RBI :1; + IO_BYTE _RDRF :1; + IO_BYTE _TDRE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }ESIR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SOE :1; + IO_BYTE _SCKE :1; + IO_BYTE _UPCL :1; + IO_BYTE _REST :1; + IO_BYTE _EXT :1; + IO_BYTE _OTO :1; + IO_BYTE _MD0 :1; + IO_BYTE _MD1 :1; + }bit; + struct{ + IO_BYTE :6; + IO_BYTE _MD :2; + }bitc; + }SMR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TXE :1; + IO_BYTE _RXE :1; + IO_BYTE _CRE :1; + IO_BYTE _AD :1; + IO_BYTE _CL :1; + IO_BYTE _SBL :1; + IO_BYTE _P :1; + IO_BYTE _PEN :1; + }bit; + }SCR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TIE :1; + IO_BYTE _RIE :1; + IO_BYTE _BDS :1; + IO_BYTE _TDRE :1; + IO_BYTE _RDRF :1; + IO_BYTE _FRE :1; + IO_BYTE _ORE :1; + IO_BYTE _PE :1; + }bit; + }SSR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TBI :1; + IO_BYTE _RBI :1; + IO_BYTE _BIE :1; + IO_BYTE _SSM :1; + IO_BYTE _SCDE :1; + IO_BYTE _MS :1; + IO_BYTE _LBR :1; + IO_BYTE _INV :1; + }bit; + }ECCR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SCES :1; + IO_BYTE _CCO :1; + IO_BYTE _SIOP :1; + IO_BYTE _SOPE :1; + IO_BYTE _LBL0 :1; + IO_BYTE _LBL1 :1; + IO_BYTE _LBD :1; + IO_BYTE _LBIE :1; + }bit; + struct{ + IO_BYTE :4; + IO_BYTE _LBL :2; + }bitc; + }ESCR1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _BGR0 :1; + IO_WORD _BGR1 :1; + IO_WORD _BGR2 :1; + IO_WORD _BGR3 :1; + IO_WORD _BGR4 :1; + IO_WORD _BGR5 :1; + IO_WORD _BGR6 :1; + IO_WORD _BGR7 :1; + IO_WORD _BGR8 :1; + IO_WORD _BGR9 :1; + IO_WORD _BGR10 :1; + IO_WORD _BGR11 :1; + IO_WORD _BGR12 :1; + IO_WORD _BGR13 :1; + IO_WORD _BGR14 :1; + IO_WORD _BGR15 :1; + }bit; + struct{ + IO_WORD _BGR :16; + }bitc; + }BGR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _BGR0 :1; + IO_BYTE _BGR1 :1; + IO_BYTE _BGR2 :1; + IO_BYTE _BGR3 :1; + IO_BYTE _BGR4 :1; + IO_BYTE _BGR5 :1; + IO_BYTE _BGR6 :1; + IO_BYTE _BGR7 :1; + }bit; + }BGRL1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _BGR8 :1; + IO_BYTE _BGR9 :1; + IO_BYTE _BGR10 :1; + IO_BYTE _BGR11 :1; + IO_BYTE _BGR12 :1; + IO_BYTE _BGR13 :1; + IO_BYTE _BGR14 :1; + IO_BYTE _BGR15 :1; + }bit; + }BGRH1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _AICD :1; + IO_BYTE _RBI :1; + IO_BYTE _RDRF :1; + IO_BYTE _TDRE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }ESIR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SOE :1; + IO_BYTE _SCKE :1; + IO_BYTE _UPCL :1; + IO_BYTE _REST :1; + IO_BYTE _EXT :1; + IO_BYTE _OTO :1; + IO_BYTE _MD0 :1; + IO_BYTE _MD1 :1; + }bit; + struct{ + IO_BYTE :6; + IO_BYTE _MD :2; + }bitc; + }SMR2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TXE :1; + IO_BYTE _RXE :1; + IO_BYTE _CRE :1; + IO_BYTE _AD :1; + IO_BYTE _CL :1; + IO_BYTE _SBL :1; + IO_BYTE _P :1; + IO_BYTE _PEN :1; + }bit; + }SCR2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TIE :1; + IO_BYTE _RIE :1; + IO_BYTE _BDS :1; + IO_BYTE _TDRE :1; + IO_BYTE _RDRF :1; + IO_BYTE _FRE :1; + IO_BYTE _ORE :1; + IO_BYTE _PE :1; + }bit; + }SSR2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TBI :1; + IO_BYTE _RBI :1; + IO_BYTE _BIE :1; + IO_BYTE _SSM :1; + IO_BYTE _SCDE :1; + IO_BYTE _MS :1; + IO_BYTE _LBR :1; + IO_BYTE _INV :1; + }bit; + }ECCR2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SCES :1; + IO_BYTE _CCO :1; + IO_BYTE _SIOP :1; + IO_BYTE _SOPE :1; + IO_BYTE _LBL0 :1; + IO_BYTE _LBL1 :1; + IO_BYTE _LBD :1; + IO_BYTE _LBIE :1; + }bit; + struct{ + IO_BYTE :4; + IO_BYTE _LBL :2; + }bitc; + }ESCR2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _BGR0 :1; + IO_WORD _BGR1 :1; + IO_WORD _BGR2 :1; + IO_WORD _BGR3 :1; + IO_WORD _BGR4 :1; + IO_WORD _BGR5 :1; + IO_WORD _BGR6 :1; + IO_WORD _BGR7 :1; + IO_WORD _BGR8 :1; + IO_WORD _BGR9 :1; + IO_WORD _BGR10 :1; + IO_WORD _BGR11 :1; + IO_WORD _BGR12 :1; + IO_WORD _BGR13 :1; + IO_WORD _BGR14 :1; + IO_WORD _BGR15 :1; + }bit; + struct{ + IO_WORD _BGR :16; + }bitc; + }BGR2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _BGR0 :1; + IO_BYTE _BGR1 :1; + IO_BYTE _BGR2 :1; + IO_BYTE _BGR3 :1; + IO_BYTE _BGR4 :1; + IO_BYTE _BGR5 :1; + IO_BYTE _BGR6 :1; + IO_BYTE _BGR7 :1; + }bit; + }BGRL2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _BGR8 :1; + IO_BYTE _BGR9 :1; + IO_BYTE _BGR10 :1; + IO_BYTE _BGR11 :1; + IO_BYTE _BGR12 :1; + IO_BYTE _BGR13 :1; + IO_BYTE _BGR14 :1; + IO_BYTE _BGR15 :1; + }bit; + }BGRH2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _AICD :1; + IO_BYTE _RBI :1; + IO_BYTE _RDRF :1; + IO_BYTE _TDRE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }ESIR2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SOE :1; + IO_BYTE _SCKE :1; + IO_BYTE _UPCL :1; + IO_BYTE _REST :1; + IO_BYTE _EXT :1; + IO_BYTE _OTO :1; + IO_BYTE _MD0 :1; + IO_BYTE _MD1 :1; + }bit; + struct{ + IO_BYTE :6; + IO_BYTE _MD :2; + }bitc; + }SMR3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TXE :1; + IO_BYTE _RXE :1; + IO_BYTE _CRE :1; + IO_BYTE _AD :1; + IO_BYTE _CL :1; + IO_BYTE _SBL :1; + IO_BYTE _P :1; + IO_BYTE _PEN :1; + }bit; + }SCR3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TIE :1; + IO_BYTE _RIE :1; + IO_BYTE _BDS :1; + IO_BYTE _TDRE :1; + IO_BYTE _RDRF :1; + IO_BYTE _FRE :1; + IO_BYTE _ORE :1; + IO_BYTE _PE :1; + }bit; + }SSR3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TBI :1; + IO_BYTE _RBI :1; + IO_BYTE _BIE :1; + IO_BYTE _SSM :1; + IO_BYTE _SCDE :1; + IO_BYTE _MS :1; + IO_BYTE _LBR :1; + IO_BYTE _INV :1; + }bit; + }ECCR3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SCES :1; + IO_BYTE _CCO :1; + IO_BYTE _SIOP :1; + IO_BYTE _SOPE :1; + IO_BYTE _LBL0 :1; + IO_BYTE _LBL1 :1; + IO_BYTE _LBD :1; + IO_BYTE _LBIE :1; + }bit; + struct{ + IO_BYTE :4; + IO_BYTE _LBL :2; + }bitc; + }ESCR3STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _BGR0 :1; + IO_WORD _BGR1 :1; + IO_WORD _BGR2 :1; + IO_WORD _BGR3 :1; + IO_WORD _BGR4 :1; + IO_WORD _BGR5 :1; + IO_WORD _BGR6 :1; + IO_WORD _BGR7 :1; + IO_WORD _BGR8 :1; + IO_WORD _BGR9 :1; + IO_WORD _BGR10 :1; + IO_WORD _BGR11 :1; + IO_WORD _BGR12 :1; + IO_WORD _BGR13 :1; + IO_WORD _BGR14 :1; + IO_WORD _BGR15 :1; + }bit; + struct{ + IO_WORD _BGR :16; + }bitc; + }BGR3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _BGR0 :1; + IO_BYTE _BGR1 :1; + IO_BYTE _BGR2 :1; + IO_BYTE _BGR3 :1; + IO_BYTE _BGR4 :1; + IO_BYTE _BGR5 :1; + IO_BYTE _BGR6 :1; + IO_BYTE _BGR7 :1; + }bit; + }BGRL3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _BGR8 :1; + IO_BYTE _BGR9 :1; + IO_BYTE _BGR10 :1; + IO_BYTE _BGR11 :1; + IO_BYTE _BGR12 :1; + IO_BYTE _BGR13 :1; + IO_BYTE _BGR14 :1; + IO_BYTE _BGR15 :1; + }bit; + }BGRH3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _AICD :1; + IO_BYTE _RBI :1; + IO_BYTE _RDRF :1; + IO_BYTE _TDRE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }ESIR3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SE :1; + IO_BYTE _DIR :1; + IO_BYTE _BF :1; + IO_BYTE _BW :1; + IO_BYTE _IF :1; + IO_BYTE _BPD :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }DMACS0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SE :1; + IO_BYTE _DIR :1; + IO_BYTE _BF :1; + IO_BYTE _BW :1; + IO_BYTE _IF :1; + IO_BYTE _BPD :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }DMACS1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SE :1; + IO_BYTE _DIR :1; + IO_BYTE _BF :1; + IO_BYTE _BW :1; + IO_BYTE _IF :1; + IO_BYTE _BPD :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }DMACS2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SE :1; + IO_BYTE _DIR :1; + IO_BYTE _BF :1; + IO_BYTE _BW :1; + IO_BYTE _IF :1; + IO_BYTE _BPD :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }DMACS3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SE :1; + IO_BYTE _DIR :1; + IO_BYTE _BF :1; + IO_BYTE _BW :1; + IO_BYTE _IF :1; + IO_BYTE _BPD :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }DMACS4STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SE :1; + IO_BYTE _DIR :1; + IO_BYTE _BF :1; + IO_BYTE _BW :1; + IO_BYTE _IF :1; + IO_BYTE _BPD :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }DMACS5STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _DTE0 :1; + IO_WORD _DTE1 :1; + IO_WORD _DTE2 :1; + IO_WORD _DTE3 :1; + IO_WORD _DTE4 :1; + IO_WORD _DTE5 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }DSRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _DTE0 :1; + IO_BYTE _DTE1 :1; + IO_BYTE _DTE2 :1; + IO_BYTE _DTE3 :1; + IO_BYTE _DTE4 :1; + IO_BYTE _DTE5 :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }DSRLSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _STP0 :1; + IO_WORD _STP1 :1; + IO_WORD _STP2 :1; + IO_WORD _STP3 :1; + IO_WORD _STP4 :1; + IO_WORD _STP5 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }DSSRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _STP0 :1; + IO_BYTE _STP1 :1; + IO_BYTE _STP2 :1; + IO_BYTE _STP3 :1; + IO_BYTE _STP4 :1; + IO_BYTE _STP5 :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }DSSRLSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _EN0 :1; + IO_WORD _EN1 :1; + IO_WORD _EN2 :1; + IO_WORD _EN3 :1; + IO_WORD _EN4 :1; + IO_WORD _EN5 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }DERSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EN0 :1; + IO_BYTE _EN1 :1; + IO_BYTE _EN2 :1; + IO_BYTE _EN3 :1; + IO_BYTE _EN4 :1; + IO_BYTE _EN5 :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }DERLSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _IL0 :1; + IO_WORD _IL1 :1; + IO_WORD _IL2 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _IX0 :1; + IO_WORD _IX1 :1; + IO_WORD _IX2 :1; + IO_WORD _IX3 :1; + IO_WORD _IX4 :1; + IO_WORD _IX5 :1; + IO_WORD _IX6 :1; + IO_WORD _IX7 :1; + }bit; + struct{ + IO_WORD _IL :3; + IO_WORD :5; + IO_WORD _IX :8; + }bitc; + }ICRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IL0 :1; + IO_BYTE _IL1 :1; + IO_BYTE _IL2 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _IL :3; + }bitc; + }ILRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IX0 :1; + IO_BYTE _IX1 :1; + IO_BYTE _IX2 :1; + IO_BYTE _IX3 :1; + IO_BYTE _IX4 :1; + IO_BYTE _IX5 :1; + IO_BYTE _IX6 :1; + IO_BYTE _IX7 :1; + }bit; + struct{ + IO_BYTE _IX :8; + }bitc; + }IDXSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD _TB10 :1; + IO_WORD _TB11 :1; + IO_WORD _TB12 :1; + IO_WORD _TB13 :1; + IO_WORD _TB14 :1; + IO_WORD _TB15 :1; + IO_WORD _TB16 :1; + IO_WORD _TB17 :1; + IO_WORD _TB18 :1; + IO_WORD _TB19 :1; + IO_WORD _TB20 :1; + IO_WORD _TB21 :1; + IO_WORD _TB22 :1; + IO_WORD _TB23 :1; + }bit; + }TBRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _TB10 :1; + IO_BYTE _TB11 :1; + IO_BYTE _TB12 :1; + IO_BYTE _TB13 :1; + IO_BYTE _TB14 :1; + IO_BYTE _TB15 :1; + }bit; + }TBRLSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TB16 :1; + IO_BYTE _TB17 :1; + IO_BYTE _TB18 :1; + IO_BYTE _TB19 :1; + IO_BYTE _TB20 :1; + IO_BYTE _TB21 :1; + IO_BYTE _TB22 :1; + IO_BYTE _TB23 :1; + }bit; + }TBRHSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _R0 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }DIRRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _FLAG :1; + IO_BYTE _EN :1; + IO_BYTE _LEV :1; + IO_BYTE _INT9FIX :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }NMISTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _RSEL0 :1; + IO_WORD _RSEL1 :1; + IO_WORD _RSEL2 :1; + IO_WORD _RSEL3 :1; + IO_WORD _RSEL4 :1; + IO_WORD _RSEL5 :1; + IO_WORD _RSEL6 :1; + IO_WORD _RSEL7 :1; + IO_WORD _TSEL0 :1; + IO_WORD _TSEL1 :1; + IO_WORD _TSEL2 :1; + IO_WORD _TSEL3 :1; + IO_WORD _TSEL4 :1; + IO_WORD _TSEL5 :1; + IO_WORD _TSEL6 :1; + IO_WORD _TSEL7 :1; + }bit; + struct{ + IO_WORD _RSEL :8; + IO_WORD _TSEL :8; + }bitc; + }EDSU2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MI :1; + IO_BYTE _SZ0 :1; + IO_BYTE _SZ1 :1; + IO_BYTE :1; + IO_BYTE _BS0 :1; + IO_BYTE _BS1 :1; + IO_BYTE _BS2 :1; + IO_BYTE _BS3 :1; + }bit; + }ROMMSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _RINT :1; + IO_BYTE _RIE :1; + IO_BYTE _SEL0 :1; + IO_BYTE _SEL1 :1; + IO_BYTE _TINT :1; + IO_BYTE _TIE :1; + IO_BYTE :1; + IO_BYTE _EN :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _SEL :2; + }bitc; + }EDSUSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _I0 :1; + IO_WORD _I1 :1; + IO_WORD _IE0 :1; + IO_WORD _IE1 :1; + IO_WORD _PE0 :1; + IO_WORD _PE1 :1; + IO_WORD _AR :1; + IO_WORD _AM :1; + IO_WORD _DMA :1; + IO_WORD _CPU :1; + IO_WORD _DATA :1; + IO_WORD _CODE :1; + IO_WORD _WORD :1; + IO_WORD _BYTE :1; + IO_WORD _WRITE :1; + IO_WORD _READ :1; + }bit; + }PFCS0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _I0 :1; + IO_WORD _I1 :1; + IO_WORD _IE0 :1; + IO_WORD _IE1 :1; + IO_WORD _PE0 :1; + IO_WORD _PE1 :1; + IO_WORD _AR :1; + IO_WORD _AM :1; + IO_WORD _DMA :1; + IO_WORD _CPU :1; + IO_WORD _DATA :1; + IO_WORD _CODE :1; + IO_WORD _WORD :1; + IO_WORD _BYTE :1; + IO_WORD _WRITE :1; + IO_WORD _READ :1; + }bit; + }PFCS1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _I0 :1; + IO_WORD _I1 :1; + IO_WORD _IE0 :1; + IO_WORD _IE1 :1; + IO_WORD _PE0 :1; + IO_WORD _PE1 :1; + IO_WORD _AR :1; + IO_WORD _AM :1; + IO_WORD _DMA :1; + IO_WORD _CPU :1; + IO_WORD _DATA :1; + IO_WORD _CODE :1; + IO_WORD _WORD :1; + IO_WORD _BYTE :1; + IO_WORD _WRITE :1; + IO_WORD _READ :1; + }bit; + }PFCS2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _I0 :1; + IO_WORD _I1 :1; + IO_WORD _IE0 :1; + IO_WORD _IE1 :1; + IO_WORD _PE0 :1; + IO_WORD _PE1 :1; + IO_WORD _AR :1; + IO_WORD _AM :1; + IO_WORD _DMA :1; + IO_WORD _CPU :1; + IO_WORD _DATA :1; + IO_WORD _CODE :1; + IO_WORD _WORD :1; + IO_WORD _BYTE :1; + IO_WORD _WRITE :1; + IO_WORD _READ :1; + }bit; + }PFCS3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFA0 :1; + IO_BYTE _PFA1 :1; + IO_BYTE _PFA2 :1; + IO_BYTE _PFA3 :1; + IO_BYTE _PFA4 :1; + IO_BYTE _PFA5 :1; + IO_BYTE _PFA6 :1; + IO_BYTE _PFA7 :1; + }bit; + }PFAL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFA8 :1; + IO_BYTE _PFA9 :1; + IO_BYTE _PFA10 :1; + IO_BYTE _PFA11 :1; + IO_BYTE _PFA12 :1; + IO_BYTE _PFA13 :1; + IO_BYTE _PFA14 :1; + IO_BYTE _PFA15 :1; + }bit; + }PFAM0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFA16 :1; + IO_BYTE _PFA17 :1; + IO_BYTE _PFA18 :1; + IO_BYTE _PFA19 :1; + IO_BYTE _PFA20 :1; + IO_BYTE _PFA21 :1; + IO_BYTE _PFA22 :1; + IO_BYTE _PFA23 :1; + }bit; + }PFAH0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFA0 :1; + IO_BYTE _PFA1 :1; + IO_BYTE _PFA2 :1; + IO_BYTE _PFA3 :1; + IO_BYTE _PFA4 :1; + IO_BYTE _PFA5 :1; + IO_BYTE _PFA6 :1; + IO_BYTE _PFA7 :1; + }bit; + }PFAL1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFA8 :1; + IO_BYTE _PFA9 :1; + IO_BYTE _PFA10 :1; + IO_BYTE _PFA11 :1; + IO_BYTE _PFA12 :1; + IO_BYTE _PFA13 :1; + IO_BYTE _PFA14 :1; + IO_BYTE _PFA15 :1; + }bit; + }PFAM1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFA16 :1; + IO_BYTE _PFA17 :1; + IO_BYTE _PFA18 :1; + IO_BYTE _PFA19 :1; + IO_BYTE _PFA20 :1; + IO_BYTE _PFA21 :1; + IO_BYTE _PFA22 :1; + IO_BYTE _PFA23 :1; + }bit; + }PFAH1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFA0 :1; + IO_BYTE _PFA1 :1; + IO_BYTE _PFA2 :1; + IO_BYTE _PFA3 :1; + IO_BYTE _PFA4 :1; + IO_BYTE _PFA5 :1; + IO_BYTE _PFA6 :1; + IO_BYTE _PFA7 :1; + }bit; + }PFAL2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFA8 :1; + IO_BYTE _PFA9 :1; + IO_BYTE _PFA10 :1; + IO_BYTE _PFA11 :1; + IO_BYTE _PFA12 :1; + IO_BYTE _PFA13 :1; + IO_BYTE _PFA14 :1; + IO_BYTE _PFA15 :1; + }bit; + }PFAM2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFA16 :1; + IO_BYTE _PFA17 :1; + IO_BYTE _PFA18 :1; + IO_BYTE _PFA19 :1; + IO_BYTE _PFA20 :1; + IO_BYTE _PFA21 :1; + IO_BYTE _PFA22 :1; + IO_BYTE _PFA23 :1; + }bit; + }PFAH2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFA0 :1; + IO_BYTE _PFA1 :1; + IO_BYTE _PFA2 :1; + IO_BYTE _PFA3 :1; + IO_BYTE _PFA4 :1; + IO_BYTE _PFA5 :1; + IO_BYTE _PFA6 :1; + IO_BYTE _PFA7 :1; + }bit; + }PFAL3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFA8 :1; + IO_BYTE _PFA9 :1; + IO_BYTE _PFA10 :1; + IO_BYTE _PFA11 :1; + IO_BYTE _PFA12 :1; + IO_BYTE _PFA13 :1; + IO_BYTE _PFA14 :1; + IO_BYTE _PFA15 :1; + }bit; + }PFAM3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFA16 :1; + IO_BYTE _PFA17 :1; + IO_BYTE _PFA18 :1; + IO_BYTE _PFA19 :1; + IO_BYTE _PFA20 :1; + IO_BYTE _PFA21 :1; + IO_BYTE _PFA22 :1; + IO_BYTE _PFA23 :1; + }bit; + }PFAH3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFA0 :1; + IO_BYTE _PFA1 :1; + IO_BYTE _PFA2 :1; + IO_BYTE _PFA3 :1; + IO_BYTE _PFA4 :1; + IO_BYTE _PFA5 :1; + IO_BYTE _PFA6 :1; + IO_BYTE _PFA7 :1; + }bit; + }PFAL4STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFA8 :1; + IO_BYTE _PFA9 :1; + IO_BYTE _PFA10 :1; + IO_BYTE _PFA11 :1; + IO_BYTE _PFA12 :1; + IO_BYTE _PFA13 :1; + IO_BYTE _PFA14 :1; + IO_BYTE _PFA15 :1; + }bit; + }PFAM4STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFA16 :1; + IO_BYTE _PFA17 :1; + IO_BYTE _PFA18 :1; + IO_BYTE _PFA19 :1; + IO_BYTE _PFA20 :1; + IO_BYTE _PFA21 :1; + IO_BYTE _PFA22 :1; + IO_BYTE _PFA23 :1; + }bit; + }PFAH4STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFA0 :1; + IO_BYTE _PFA1 :1; + IO_BYTE _PFA2 :1; + IO_BYTE _PFA3 :1; + IO_BYTE _PFA4 :1; + IO_BYTE _PFA5 :1; + IO_BYTE _PFA6 :1; + IO_BYTE _PFA7 :1; + }bit; + }PFAL5STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFA8 :1; + IO_BYTE _PFA9 :1; + IO_BYTE _PFA10 :1; + IO_BYTE _PFA11 :1; + IO_BYTE _PFA12 :1; + IO_BYTE _PFA13 :1; + IO_BYTE _PFA14 :1; + IO_BYTE _PFA15 :1; + }bit; + }PFAM5STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFA16 :1; + IO_BYTE _PFA17 :1; + IO_BYTE _PFA18 :1; + IO_BYTE _PFA19 :1; + IO_BYTE _PFA20 :1; + IO_BYTE _PFA21 :1; + IO_BYTE _PFA22 :1; + IO_BYTE _PFA23 :1; + }bit; + }PFAH5STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFA0 :1; + IO_BYTE _PFA1 :1; + IO_BYTE _PFA2 :1; + IO_BYTE _PFA3 :1; + IO_BYTE _PFA4 :1; + IO_BYTE _PFA5 :1; + IO_BYTE _PFA6 :1; + IO_BYTE _PFA7 :1; + }bit; + }PFAL6STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFA8 :1; + IO_BYTE _PFA9 :1; + IO_BYTE _PFA10 :1; + IO_BYTE _PFA11 :1; + IO_BYTE _PFA12 :1; + IO_BYTE _PFA13 :1; + IO_BYTE _PFA14 :1; + IO_BYTE _PFA15 :1; + }bit; + }PFAM6STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFA16 :1; + IO_BYTE _PFA17 :1; + IO_BYTE _PFA18 :1; + IO_BYTE _PFA19 :1; + IO_BYTE _PFA20 :1; + IO_BYTE _PFA21 :1; + IO_BYTE _PFA22 :1; + IO_BYTE _PFA23 :1; + }bit; + }PFAH6STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFA0 :1; + IO_BYTE _PFA1 :1; + IO_BYTE _PFA2 :1; + IO_BYTE _PFA3 :1; + IO_BYTE _PFA4 :1; + IO_BYTE _PFA5 :1; + IO_BYTE _PFA6 :1; + IO_BYTE _PFA7 :1; + }bit; + }PFAL7STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFA8 :1; + IO_BYTE _PFA9 :1; + IO_BYTE _PFA10 :1; + IO_BYTE _PFA11 :1; + IO_BYTE _PFA12 :1; + IO_BYTE _PFA13 :1; + IO_BYTE _PFA14 :1; + IO_BYTE _PFA15 :1; + }bit; + }PFAM7STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFA16 :1; + IO_BYTE _PFA17 :1; + IO_BYTE _PFA18 :1; + IO_BYTE _PFA19 :1; + IO_BYTE _PFA20 :1; + IO_BYTE _PFA21 :1; + IO_BYTE _PFA22 :1; + IO_BYTE _PFA23 :1; + }bit; + }PFAH7STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _PFD0 :1; + IO_WORD _PFD1 :1; + IO_WORD _PFD2 :1; + IO_WORD _PFD3 :1; + IO_WORD _PFD4 :1; + IO_WORD _PFD5 :1; + IO_WORD _PFD6 :1; + IO_WORD _PFD7 :1; + IO_WORD _PFD8 :1; + IO_WORD _PFD9 :1; + IO_WORD _PFD10 :1; + IO_WORD _PFD11 :1; + IO_WORD _PFD12 :1; + IO_WORD _PFD13 :1; + IO_WORD _PFD14 :1; + IO_WORD _PFD15 :1; + }bit; + struct{ + IO_WORD _PFD :16; + }bitc; + }PFD0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFD0 :1; + IO_BYTE _PFD1 :1; + IO_BYTE _PFD2 :1; + IO_BYTE _PFD3 :1; + IO_BYTE _PFD4 :1; + IO_BYTE _PFD5 :1; + IO_BYTE _PFD6 :1; + IO_BYTE _PFD7 :1; + }bit; + }PFDL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFD8 :1; + IO_BYTE _PFD9 :1; + IO_BYTE _PFD10 :1; + IO_BYTE _PFD11 :1; + IO_BYTE _PFD12 :1; + IO_BYTE _PFD13 :1; + IO_BYTE _PFD14 :1; + IO_BYTE _PFD15 :1; + }bit; + }PFDH0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _PFD0 :1; + IO_WORD _PFD1 :1; + IO_WORD _PFD2 :1; + IO_WORD _PFD3 :1; + IO_WORD _PFD4 :1; + IO_WORD _PFD5 :1; + IO_WORD _PFD6 :1; + IO_WORD _PFD7 :1; + IO_WORD _PFD8 :1; + IO_WORD _PFD9 :1; + IO_WORD _PFD10 :1; + IO_WORD _PFD11 :1; + IO_WORD _PFD12 :1; + IO_WORD _PFD13 :1; + IO_WORD _PFD14 :1; + IO_WORD _PFD15 :1; + }bit; + struct{ + IO_WORD _PFD :16; + }bitc; + }PFD1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFD0 :1; + IO_BYTE _PFD1 :1; + IO_BYTE _PFD2 :1; + IO_BYTE _PFD3 :1; + IO_BYTE _PFD4 :1; + IO_BYTE _PFD5 :1; + IO_BYTE _PFD6 :1; + IO_BYTE _PFD7 :1; + }bit; + }PFDL1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFD8 :1; + IO_BYTE _PFD9 :1; + IO_BYTE _PFD10 :1; + IO_BYTE _PFD11 :1; + IO_BYTE _PFD12 :1; + IO_BYTE _PFD13 :1; + IO_BYTE _PFD14 :1; + IO_BYTE _PFD15 :1; + }bit; + }PFDH1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _PFD0 :1; + IO_WORD _PFD1 :1; + IO_WORD _PFD2 :1; + IO_WORD _PFD3 :1; + IO_WORD _PFD4 :1; + IO_WORD _PFD5 :1; + IO_WORD _PFD6 :1; + IO_WORD _PFD7 :1; + IO_WORD _PFD8 :1; + IO_WORD _PFD9 :1; + IO_WORD _PFD10 :1; + IO_WORD _PFD11 :1; + IO_WORD _PFD12 :1; + IO_WORD _PFD13 :1; + IO_WORD _PFD14 :1; + IO_WORD _PFD15 :1; + }bit; + struct{ + IO_WORD _PFD :16; + }bitc; + }PFD2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFD0 :1; + IO_BYTE _PFD1 :1; + IO_BYTE _PFD2 :1; + IO_BYTE _PFD3 :1; + IO_BYTE _PFD4 :1; + IO_BYTE _PFD5 :1; + IO_BYTE _PFD6 :1; + IO_BYTE _PFD7 :1; + }bit; + }PFDL2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFD8 :1; + IO_BYTE _PFD9 :1; + IO_BYTE _PFD10 :1; + IO_BYTE _PFD11 :1; + IO_BYTE _PFD12 :1; + IO_BYTE _PFD13 :1; + IO_BYTE _PFD14 :1; + IO_BYTE _PFD15 :1; + }bit; + }PFDH2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _PFD0 :1; + IO_WORD _PFD1 :1; + IO_WORD _PFD2 :1; + IO_WORD _PFD3 :1; + IO_WORD _PFD4 :1; + IO_WORD _PFD5 :1; + IO_WORD _PFD6 :1; + IO_WORD _PFD7 :1; + IO_WORD _PFD8 :1; + IO_WORD _PFD9 :1; + IO_WORD _PFD10 :1; + IO_WORD _PFD11 :1; + IO_WORD _PFD12 :1; + IO_WORD _PFD13 :1; + IO_WORD _PFD14 :1; + IO_WORD _PFD15 :1; + }bit; + struct{ + IO_WORD _PFD :16; + }bitc; + }PFD3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFD0 :1; + IO_BYTE _PFD1 :1; + IO_BYTE _PFD2 :1; + IO_BYTE _PFD3 :1; + IO_BYTE _PFD4 :1; + IO_BYTE _PFD5 :1; + IO_BYTE _PFD6 :1; + IO_BYTE _PFD7 :1; + }bit; + }PFDL3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFD8 :1; + IO_BYTE _PFD9 :1; + IO_BYTE _PFD10 :1; + IO_BYTE _PFD11 :1; + IO_BYTE _PFD12 :1; + IO_BYTE _PFD13 :1; + IO_BYTE _PFD14 :1; + IO_BYTE _PFD15 :1; + }bit; + }PFDH3STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _PFD0 :1; + IO_WORD _PFD1 :1; + IO_WORD _PFD2 :1; + IO_WORD _PFD3 :1; + IO_WORD _PFD4 :1; + IO_WORD _PFD5 :1; + IO_WORD _PFD6 :1; + IO_WORD _PFD7 :1; + IO_WORD _PFD8 :1; + IO_WORD _PFD9 :1; + IO_WORD _PFD10 :1; + IO_WORD _PFD11 :1; + IO_WORD _PFD12 :1; + IO_WORD _PFD13 :1; + IO_WORD _PFD14 :1; + IO_WORD _PFD15 :1; + }bit; + struct{ + IO_WORD _PFD :16; + }bitc; + }PFD4STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFD0 :1; + IO_BYTE _PFD1 :1; + IO_BYTE _PFD2 :1; + IO_BYTE _PFD3 :1; + IO_BYTE _PFD4 :1; + IO_BYTE _PFD5 :1; + IO_BYTE _PFD6 :1; + IO_BYTE _PFD7 :1; + }bit; + }PFDL4STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFD8 :1; + IO_BYTE _PFD9 :1; + IO_BYTE _PFD10 :1; + IO_BYTE _PFD11 :1; + IO_BYTE _PFD12 :1; + IO_BYTE _PFD13 :1; + IO_BYTE _PFD14 :1; + IO_BYTE _PFD15 :1; + }bit; + }PFDH4STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _PFD0 :1; + IO_WORD _PFD1 :1; + IO_WORD _PFD2 :1; + IO_WORD _PFD3 :1; + IO_WORD _PFD4 :1; + IO_WORD _PFD5 :1; + IO_WORD _PFD6 :1; + IO_WORD _PFD7 :1; + IO_WORD _PFD8 :1; + IO_WORD _PFD9 :1; + IO_WORD _PFD10 :1; + IO_WORD _PFD11 :1; + IO_WORD _PFD12 :1; + IO_WORD _PFD13 :1; + IO_WORD _PFD14 :1; + IO_WORD _PFD15 :1; + }bit; + struct{ + IO_WORD _PFD :16; + }bitc; + }PFD5STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFD0 :1; + IO_BYTE _PFD1 :1; + IO_BYTE _PFD2 :1; + IO_BYTE _PFD3 :1; + IO_BYTE _PFD4 :1; + IO_BYTE _PFD5 :1; + IO_BYTE _PFD6 :1; + IO_BYTE _PFD7 :1; + }bit; + }PFDL5STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFD8 :1; + IO_BYTE _PFD9 :1; + IO_BYTE _PFD10 :1; + IO_BYTE _PFD11 :1; + IO_BYTE _PFD12 :1; + IO_BYTE _PFD13 :1; + IO_BYTE _PFD14 :1; + IO_BYTE _PFD15 :1; + }bit; + }PFDH5STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _PFD0 :1; + IO_WORD _PFD1 :1; + IO_WORD _PFD2 :1; + IO_WORD _PFD3 :1; + IO_WORD _PFD4 :1; + IO_WORD _PFD5 :1; + IO_WORD _PFD6 :1; + IO_WORD _PFD7 :1; + IO_WORD _PFD8 :1; + IO_WORD _PFD9 :1; + IO_WORD _PFD10 :1; + IO_WORD _PFD11 :1; + IO_WORD _PFD12 :1; + IO_WORD _PFD13 :1; + IO_WORD _PFD14 :1; + IO_WORD _PFD15 :1; + }bit; + struct{ + IO_WORD _PFD :16; + }bitc; + }PFD6STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFD0 :1; + IO_BYTE _PFD1 :1; + IO_BYTE _PFD2 :1; + IO_BYTE _PFD3 :1; + IO_BYTE _PFD4 :1; + IO_BYTE _PFD5 :1; + IO_BYTE _PFD6 :1; + IO_BYTE _PFD7 :1; + }bit; + }PFDL6STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFD8 :1; + IO_BYTE _PFD9 :1; + IO_BYTE _PFD10 :1; + IO_BYTE _PFD11 :1; + IO_BYTE _PFD12 :1; + IO_BYTE _PFD13 :1; + IO_BYTE _PFD14 :1; + IO_BYTE _PFD15 :1; + }bit; + }PFDH6STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _PFD0 :1; + IO_WORD _PFD1 :1; + IO_WORD _PFD2 :1; + IO_WORD _PFD3 :1; + IO_WORD _PFD4 :1; + IO_WORD _PFD5 :1; + IO_WORD _PFD6 :1; + IO_WORD _PFD7 :1; + IO_WORD _PFD8 :1; + IO_WORD _PFD9 :1; + IO_WORD _PFD10 :1; + IO_WORD _PFD11 :1; + IO_WORD _PFD12 :1; + IO_WORD _PFD13 :1; + IO_WORD _PFD14 :1; + IO_WORD _PFD15 :1; + }bit; + struct{ + IO_WORD _PFD :16; + }bitc; + }PFD7STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFD0 :1; + IO_BYTE _PFD1 :1; + IO_BYTE _PFD2 :1; + IO_BYTE _PFD3 :1; + IO_BYTE _PFD4 :1; + IO_BYTE _PFD5 :1; + IO_BYTE _PFD6 :1; + IO_BYTE _PFD7 :1; + }bit; + }PFDL7STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PFD8 :1; + IO_BYTE _PFD9 :1; + IO_BYTE _PFD10 :1; + IO_BYTE _PFD11 :1; + IO_BYTE _PFD12 :1; + IO_BYTE _PFD13 :1; + IO_BYTE _PFD14 :1; + IO_BYTE _PFD15 :1; + }bit; + }PFDH7STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _RDY :1; + IO_BYTE _RDYINT :1; + IO_BYTE _INTE :1; + IO_BYTE _WE :1; + IO_BYTE _CRBE :1; + IO_BYTE _DRBE :1; + IO_BYTE _RD19V :1; + IO_BYTE :1; + }bit; + }MFMCSSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _FAWC0 :1; + IO_WORD _FAWC1 :1; + IO_WORD _FAWC2 :1; + IO_WORD _SYNC :1; + IO_WORD _ADS :1; + IO_WORD _CLKBW :1; + IO_WORD _WEXL :1; + IO_WORD :1; + IO_WORD _ATDINIT :1; + IO_WORD _ATDL0 :1; + IO_WORD _ATDL1 :1; + IO_WORD _ATDEQD0 :1; + IO_WORD _ATDEQD1 :1; + IO_WORD _EQL0 :1; + IO_WORD _EQL1 :1; + IO_WORD _EQL2 :1; + }bit; + struct{ + IO_WORD _FAWC :3; + IO_WORD :6; + IO_WORD _ATDL :2; + IO_WORD _ATDEQD :2; + IO_WORD _EQL :3; + }bitc; + }MFMTCSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _FAWC0 :1; + IO_BYTE _FAWC1 :1; + IO_BYTE _FAWC2 :1; + IO_BYTE _SYNC :1; + IO_BYTE _ADS :1; + IO_BYTE _CLKBW :1; + IO_BYTE _WEXL :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _FAWC :3; + }bitc; + }MFMTCLSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ATDINIT :1; + IO_BYTE _ATDL0 :1; + IO_BYTE _ATDL1 :1; + IO_BYTE _ATDEQD0 :1; + IO_BYTE _ATDEQD1 :1; + IO_BYTE _EQL0 :1; + IO_BYTE _EQL1 :1; + IO_BYTE _EQL2 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE _ATDL :2; + IO_BYTE _ATDEQD :2; + IO_BYTE _EQL :3; + }bitc; + }MFMTCHSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _RDY :1; + IO_BYTE _RDYINT :1; + IO_BYTE _INTE :1; + IO_BYTE _WE :1; + IO_BYTE _CRBE :1; + IO_BYTE _DRBE :1; + IO_BYTE _RD19V :1; + IO_BYTE :1; + }bit; + }SFMCSSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _FAWC0 :1; + IO_WORD _FAWC1 :1; + IO_WORD _FAWC2 :1; + IO_WORD _SYNC :1; + IO_WORD _ADS :1; + IO_WORD _CLKBW :1; + IO_WORD _WEXL :1; + IO_WORD :1; + IO_WORD _ATDINIT :1; + IO_WORD _ATDL0 :1; + IO_WORD _ATDL1 :1; + IO_WORD _ATDEQD0 :1; + IO_WORD _ATDEQD1 :1; + IO_WORD _EQL0 :1; + IO_WORD _EQL1 :1; + IO_WORD _EQL2 :1; + }bit; + struct{ + IO_WORD _FAWC :3; + IO_WORD :6; + IO_WORD _ATDL :2; + IO_WORD _ATDEQD :2; + IO_WORD _EQL :3; + }bitc; + }SFMTCSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _FAWC0 :1; + IO_BYTE _FAWC1 :1; + IO_BYTE _FAWC2 :1; + IO_BYTE _SYNC :1; + IO_BYTE _ADS :1; + IO_BYTE _CLKBW :1; + IO_BYTE _WEXL :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _FAWC :3; + }bitc; + }SFMTCLSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ATDINIT :1; + IO_BYTE _ATDL0 :1; + IO_BYTE _ATDL1 :1; + IO_BYTE _ATDEQD0 :1; + IO_BYTE _ATDEQD1 :1; + IO_BYTE _EQL0 :1; + IO_BYTE _EQL1 :1; + IO_BYTE _EQL2 :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE _ATDL :2; + IO_BYTE _ATDEQD :2; + IO_BYTE _EQL :3; + }bitc; + }SFMTCHSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _WCB0 :1; + IO_BYTE _WCB1 :1; + IO_BYTE _WCB2 :1; + IO_BYTE _WCB3 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _WCB :4; + }bitc; + }FMWC0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _WCA0 :1; + IO_BYTE _WCA1 :1; + IO_BYTE _WCA2 :1; + IO_BYTE _WCA3 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _WCA :4; + }bitc; + }FMWC1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _WC32 :1; + IO_BYTE _WC33 :1; + IO_BYTE _WC34 :1; + IO_BYTE _WC35 :1; + IO_BYTE _WC36 :1; + IO_BYTE _WC37 :1; + IO_BYTE _WC38 :1; + IO_BYTE _WC39 :1; + }bit; + struct{ + IO_BYTE _WC3 :8; + }bitc; + }FMWC5STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SMS0 :1; + IO_BYTE _SMS1 :1; + IO_BYTE _SPL :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _SMS :2; + }bitc; + }SMCRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SC1S0 :1; + IO_BYTE _SC1S1 :1; + IO_BYTE _SC2S0 :1; + IO_BYTE _SC2S1 :1; + IO_BYTE _RCE :1; + IO_BYTE _MCE :1; + IO_BYTE _PCE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _SC1S :2; + IO_BYTE _SC2S :2; + }bitc; + }CKSRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MCST0 :1; + IO_BYTE _MCST1 :1; + IO_BYTE _MCST2 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _PCST :1; + IO_BYTE _MRFBE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _MCST :3; + }bitc; + }CKSSRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SC1M0 :1; + IO_BYTE _SC1M1 :1; + IO_BYTE _SC2M0 :1; + IO_BYTE _SC2M1 :1; + IO_BYTE _RCM :1; + IO_BYTE _MCM :1; + IO_BYTE _PCM :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _SC1M :2; + IO_BYTE _SC2M :2; + }bitc; + }CKMRSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _RCFS :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _BCD0 :1; + IO_WORD _BCD1 :1; + IO_WORD _BCD2 :1; + IO_WORD _BCD3 :1; + IO_WORD _PC1D0 :1; + IO_WORD _PC1D1 :1; + IO_WORD _PC1D2 :1; + IO_WORD _PC1D3 :1; + IO_WORD _PC2D0 :1; + IO_WORD _PC2D1 :1; + IO_WORD _PC2D2 :1; + IO_WORD _PC2D3 :1; + }bit; + struct{ + IO_WORD :4; + IO_WORD _BCD :4; + IO_WORD _PC1D :4; + IO_WORD _PC2D :4; + }bitc; + }CKFCRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _RCFS :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _BCD0 :1; + IO_BYTE _BCD1 :1; + IO_BYTE _BCD2 :1; + IO_BYTE _BCD3 :1; + }bit; + struct{ + IO_BYTE :4; + IO_BYTE _BCD :4; + }bitc; + }CKFCRLSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PC1D0 :1; + IO_BYTE _PC1D1 :1; + IO_BYTE _PC1D2 :1; + IO_BYTE _PC1D3 :1; + IO_BYTE _PC2D0 :1; + IO_BYTE _PC2D1 :1; + IO_BYTE _PC2D2 :1; + IO_BYTE _PC2D3 :1; + }bit; + struct{ + IO_BYTE _PC1D :4; + IO_BYTE _PC2D :4; + }bitc; + }CKFCRHSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _PMS0 :1; + IO_WORD _PMS1 :1; + IO_WORD _PMS2 :1; + IO_WORD _PMS3 :1; + IO_WORD _PMS4 :1; + IO_WORD _VMS0 :1; + IO_WORD _VMS1 :1; + IO_WORD _VMS2 :1; + IO_WORD _PC3D0 :1; + IO_WORD _PC3D1 :1; + IO_WORD _PC3D2 :1; + IO_WORD _PC3D3 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD _PMS :5; + IO_WORD _VMS :3; + IO_WORD _PC3D :4; + }bitc; + }PLLCRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PMS0 :1; + IO_BYTE _PMS1 :1; + IO_BYTE _PMS2 :1; + IO_BYTE _PMS3 :1; + IO_BYTE _PMS4 :1; + IO_BYTE _VMS0 :1; + IO_BYTE _VMS1 :1; + IO_BYTE _VMS2 :1; + }bit; + struct{ + IO_BYTE _PMS :5; + IO_BYTE _VMS :3; + }bitc; + }PLLCRLSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PC3D0 :1; + IO_BYTE _PC3D1 :1; + IO_BYTE _PC3D2 :1; + IO_BYTE _PC3D3 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _PC3D :4; + }bitc; + }PLLCRHSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _RCTI0 :1; + IO_BYTE _RCTI1 :1; + IO_BYTE _RCTI2 :1; + IO_BYTE _RCTI3 :1; + IO_BYTE _RCTR :1; + IO_BYTE _RCTIF :1; + IO_BYTE _RCTIE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _RCTI :4; + }bitc; + }RCTCRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MCTI0 :1; + IO_BYTE _MCTI1 :1; + IO_BYTE _MCTI2 :1; + IO_BYTE _MCTI3 :1; + IO_BYTE _MCTR :1; + IO_BYTE _MCTIF :1; + IO_BYTE _MCTIE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _MCTI :4; + }bitc; + }MCTCRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PRST :1; + IO_BYTE _ERST :1; + IO_BYTE _MCRST :1; + IO_BYTE :1; + IO_BYTE _SRST :1; + IO_BYTE _WRST :1; + IO_BYTE _MCMF :1; + IO_BYTE :1; + }bit; + }RCCSRCSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SRSTG :1; + IO_BYTE _LVRE :1; + IO_BYTE _LVDE :1; + IO_BYTE _CSDRE :1; + IO_BYTE _MCSDI :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }RCRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PRST :1; + IO_BYTE _ERST :1; + IO_BYTE _MCRST :1; + IO_BYTE :1; + IO_BYTE _SRST :1; + IO_BYTE _WRST :1; + IO_BYTE _MCMF :1; + IO_BYTE :1; + }bit; + }RCCSRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _WTI0 :1; + IO_BYTE _WTI1 :1; + IO_BYTE _WTI2 :1; + IO_BYTE _WTI3 :1; + IO_BYTE _WTCS0 :1; + IO_BYTE _WTCS1 :1; + IO_BYTE _RSTP :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _WTI :4; + IO_BYTE _WTCS :2; + }bitc; + }WDTCSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _WCP0 :1; + IO_BYTE _WCP1 :1; + IO_BYTE _WCP2 :1; + IO_BYTE _WCP3 :1; + IO_BYTE _WCP4 :1; + IO_BYTE _WCP5 :1; + IO_BYTE _WCP6 :1; + IO_BYTE _WCP7 :1; + }bit; + struct{ + IO_BYTE _WCP :8; + }bitc; + }WDTCPSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CKOE0 :1; + IO_BYTE _CKOXE0 :1; + IO_BYTE _RUNC0 :1; + IO_BYTE _RUNM0 :1; + IO_BYTE _CKOE1 :1; + IO_BYTE _CKOXE1 :1; + IO_BYTE _RUNC1 :1; + IO_BYTE _RUNM1 :1; + }bit; + }COARSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SEL0 :1; + IO_BYTE _SEL1 :1; + IO_BYTE _SEL2 :1; + IO_BYTE _SEL3 :1; + IO_BYTE _DIV0 :1; + IO_BYTE _DIV1 :1; + IO_BYTE _DIV2 :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _SEL :4; + IO_BYTE _DIV :3; + }bitc; + }COCR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SEL0 :1; + IO_BYTE _SEL1 :1; + IO_BYTE _SEL2 :1; + IO_BYTE _SEL3 :1; + IO_BYTE _DIV0 :1; + IO_BYTE _DIV1 :1; + IO_BYTE _DIV2 :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _SEL :4; + IO_BYTE _DIV :3; + }bitc; + }COCR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PDX :1; + IO_BYTE _MODEN :1; + IO_BYTE _MODRUN :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }CMCRSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _C0 :1; + IO_WORD _C1 :1; + IO_WORD _C2 :1; + IO_WORD _C3 :1; + IO_WORD _C4 :1; + IO_WORD _N0 :1; + IO_WORD _N1 :1; + IO_WORD _N2 :1; + IO_WORD _N3 :1; + IO_WORD _K0 :1; + IO_WORD _K1 :1; + IO_WORD _K2 :1; + IO_WORD _K3 :1; + IO_WORD _K4 :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD _C :5; + IO_WORD _N :3; + IO_WORD :1; + IO_WORD _K :5; + }bitc; + }CMPRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _C0 :1; + IO_BYTE _C1 :1; + IO_BYTE _C2 :1; + IO_BYTE _C3 :1; + IO_BYTE _C4 :1; + IO_BYTE _N0 :1; + IO_BYTE _N1 :1; + IO_BYTE _N2 :1; + }bit; + struct{ + IO_BYTE _C :5; + IO_BYTE _N :3; + }bitc; + }CMPRLSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _N3 :1; + IO_BYTE _K0 :1; + IO_BYTE _K1 :1; + IO_BYTE _K2 :1; + IO_BYTE _K3 :1; + IO_BYTE _K4 :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE :1; + IO_BYTE _K :5; + }bitc; + }CMPRHSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _LPBM0 :1; + IO_BYTE _LPBM1 :1; + IO_BYTE _LPMB2 :1; + IO_BYTE _LPMA0 :1; + IO_BYTE _LPMA1 :1; + IO_BYTE _LPMA2 :1; + IO_BYTE _HPM0 :1; + IO_BYTE _HPM1 :1; + }bit; + struct{ + IO_BYTE _LPBM :3; + IO_BYTE _LPMA :3; + IO_BYTE _HPM :2; + }bitc; + }VRCRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D0 :1; + IO_BYTE _D1 :1; + IO_BYTE _D2 :1; + IO_BYTE _D3 :1; + IO_BYTE _D4 :1; + IO_BYTE _D5 :1; + IO_BYTE _D6 :1; + IO_BYTE _D7 :1; + }bit; + }DDR00STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D0 :1; + IO_BYTE _D1 :1; + IO_BYTE _D2 :1; + IO_BYTE _D3 :1; + IO_BYTE _D4 :1; + IO_BYTE _D5 :1; + IO_BYTE _D6 :1; + IO_BYTE _D7 :1; + }bit; + }DDR01STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D0 :1; + IO_BYTE _D1 :1; + IO_BYTE _D2 :1; + IO_BYTE _D3 :1; + IO_BYTE _D4 :1; + IO_BYTE _D5 :1; + IO_BYTE _D6 :1; + IO_BYTE _D7 :1; + }bit; + }DDR02STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D0 :1; + IO_BYTE _D1 :1; + IO_BYTE _D2 :1; + IO_BYTE _D3 :1; + IO_BYTE _D4 :1; + IO_BYTE _D5 :1; + IO_BYTE _D6 :1; + IO_BYTE _D7 :1; + }bit; + }DDR03STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D0 :1; + IO_BYTE _D1 :1; + IO_BYTE _D2 :1; + IO_BYTE _D3 :1; + IO_BYTE _D4 :1; + IO_BYTE _D5 :1; + IO_BYTE _D6 :1; + IO_BYTE _D7 :1; + }bit; + }DDR04STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D0 :1; + IO_BYTE _D1 :1; + IO_BYTE _D2 :1; + IO_BYTE _D3 :1; + IO_BYTE _D4 :1; + IO_BYTE _D5 :1; + IO_BYTE _D6 :1; + IO_BYTE _D7 :1; + }bit; + }DDR05STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D0 :1; + IO_BYTE _D1 :1; + IO_BYTE _D2 :1; + IO_BYTE _D3 :1; + IO_BYTE _D4 :1; + IO_BYTE _D5 :1; + IO_BYTE _D6 :1; + IO_BYTE _D7 :1; + }bit; + }DDR06STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D0 :1; + IO_BYTE _D1 :1; + IO_BYTE _D2 :1; + IO_BYTE _D3 :1; + IO_BYTE _D4 :1; + IO_BYTE _D5 :1; + IO_BYTE _D6 :1; + IO_BYTE _D7 :1; + }bit; + }DDR07STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D0 :1; + IO_BYTE _D1 :1; + IO_BYTE _D2 :1; + IO_BYTE _D3 :1; + IO_BYTE _D4 :1; + IO_BYTE _D5 :1; + IO_BYTE _D6 :1; + IO_BYTE _D7 :1; + }bit; + }DDR08STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D0 :1; + IO_BYTE _D1 :1; + IO_BYTE _D2 :1; + IO_BYTE _D3 :1; + IO_BYTE _D4 :1; + IO_BYTE _D5 :1; + IO_BYTE _D6 :1; + IO_BYTE _D7 :1; + }bit; + }DDR09STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D0 :1; + IO_BYTE _D1 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }DDR10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IE0 :1; + IO_BYTE _IE1 :1; + IO_BYTE _IE2 :1; + IO_BYTE _IE3 :1; + IO_BYTE _IE4 :1; + IO_BYTE _IE5 :1; + IO_BYTE _IE6 :1; + IO_BYTE _IE7 :1; + }bit; + }PIER00STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IE0 :1; + IO_BYTE _IE1 :1; + IO_BYTE _IE2 :1; + IO_BYTE _IE3 :1; + IO_BYTE _IE4 :1; + IO_BYTE _IE5 :1; + IO_BYTE _IE6 :1; + IO_BYTE _IE7 :1; + }bit; + }PIER01STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IE0 :1; + IO_BYTE _IE1 :1; + IO_BYTE _IE2 :1; + IO_BYTE _IE3 :1; + IO_BYTE _IE4 :1; + IO_BYTE _IE5 :1; + IO_BYTE _IE6 :1; + IO_BYTE _IE7 :1; + }bit; + }PIER02STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IE0 :1; + IO_BYTE _IE1 :1; + IO_BYTE _IE2 :1; + IO_BYTE _IE3 :1; + IO_BYTE _IE4 :1; + IO_BYTE _IE5 :1; + IO_BYTE _IE6 :1; + IO_BYTE _IE7 :1; + }bit; + }PIER03STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IE0 :1; + IO_BYTE _IE1 :1; + IO_BYTE _IE2 :1; + IO_BYTE _IE3 :1; + IO_BYTE _IE4 :1; + IO_BYTE _IE5 :1; + IO_BYTE _IE6 :1; + IO_BYTE _IE7 :1; + }bit; + }PIER04STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IE0 :1; + IO_BYTE _IE1 :1; + IO_BYTE _IE2 :1; + IO_BYTE _IE3 :1; + IO_BYTE _IE4 :1; + IO_BYTE _IE5 :1; + IO_BYTE _IE6 :1; + IO_BYTE _IE7 :1; + }bit; + }PIER05STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IE0 :1; + IO_BYTE _IE1 :1; + IO_BYTE _IE2 :1; + IO_BYTE _IE3 :1; + IO_BYTE _IE4 :1; + IO_BYTE _IE5 :1; + IO_BYTE _IE6 :1; + IO_BYTE _IE7 :1; + }bit; + }PIER06STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IE0 :1; + IO_BYTE _IE1 :1; + IO_BYTE _IE2 :1; + IO_BYTE _IE3 :1; + IO_BYTE _IE4 :1; + IO_BYTE _IE5 :1; + IO_BYTE _IE6 :1; + IO_BYTE _IE7 :1; + }bit; + }PIER07STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IE0 :1; + IO_BYTE _IE1 :1; + IO_BYTE _IE2 :1; + IO_BYTE _IE3 :1; + IO_BYTE _IE4 :1; + IO_BYTE _IE5 :1; + IO_BYTE _IE6 :1; + IO_BYTE _IE7 :1; + }bit; + }PIER08STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IE0 :1; + IO_BYTE _IE1 :1; + IO_BYTE _IE2 :1; + IO_BYTE _IE3 :1; + IO_BYTE _IE4 :1; + IO_BYTE _IE5 :1; + IO_BYTE _IE6 :1; + IO_BYTE _IE7 :1; + }bit; + }PIER09STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IE0 :1; + IO_BYTE _IE1 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }PIER10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IL0 :1; + IO_BYTE _IL1 :1; + IO_BYTE _IL2 :1; + IO_BYTE _IL3 :1; + IO_BYTE _IL4 :1; + IO_BYTE _IL5 :1; + IO_BYTE _IL6 :1; + IO_BYTE _IL7 :1; + }bit; + }PILR00STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IL0 :1; + IO_BYTE _IL1 :1; + IO_BYTE _IL2 :1; + IO_BYTE _IL3 :1; + IO_BYTE _IL4 :1; + IO_BYTE _IL5 :1; + IO_BYTE _IL6 :1; + IO_BYTE _IL7 :1; + }bit; + }PILR01STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IL0 :1; + IO_BYTE _IL1 :1; + IO_BYTE _IL2 :1; + IO_BYTE _IL3 :1; + IO_BYTE _IL4 :1; + IO_BYTE _IL5 :1; + IO_BYTE _IL6 :1; + IO_BYTE _IL7 :1; + }bit; + }PILR02STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IL0 :1; + IO_BYTE _IL1 :1; + IO_BYTE _IL2 :1; + IO_BYTE _IL3 :1; + IO_BYTE _IL4 :1; + IO_BYTE _IL5 :1; + IO_BYTE _IL6 :1; + IO_BYTE _IL7 :1; + }bit; + }PILR03STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IL0 :1; + IO_BYTE _IL1 :1; + IO_BYTE _IL2 :1; + IO_BYTE _IL3 :1; + IO_BYTE _IL4 :1; + IO_BYTE _IL5 :1; + IO_BYTE _IL6 :1; + IO_BYTE _IL7 :1; + }bit; + }PILR04STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IL0 :1; + IO_BYTE _IL1 :1; + IO_BYTE _IL2 :1; + IO_BYTE _IL3 :1; + IO_BYTE _IL4 :1; + IO_BYTE _IL5 :1; + IO_BYTE _IL6 :1; + IO_BYTE _IL7 :1; + }bit; + }PILR05STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IL0 :1; + IO_BYTE _IL1 :1; + IO_BYTE _IL2 :1; + IO_BYTE _IL3 :1; + IO_BYTE _IL4 :1; + IO_BYTE _IL5 :1; + IO_BYTE _IL6 :1; + IO_BYTE _IL7 :1; + }bit; + }PILR06STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IL0 :1; + IO_BYTE _IL1 :1; + IO_BYTE _IL2 :1; + IO_BYTE _IL3 :1; + IO_BYTE _IL4 :1; + IO_BYTE _IL5 :1; + IO_BYTE _IL6 :1; + IO_BYTE _IL7 :1; + }bit; + }PILR07STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IL0 :1; + IO_BYTE _IL1 :1; + IO_BYTE _IL2 :1; + IO_BYTE _IL3 :1; + IO_BYTE _IL4 :1; + IO_BYTE _IL5 :1; + IO_BYTE _IL6 :1; + IO_BYTE _IL7 :1; + }bit; + }PILR08STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IL0 :1; + IO_BYTE _IL1 :1; + IO_BYTE _IL2 :1; + IO_BYTE _IL3 :1; + IO_BYTE _IL4 :1; + IO_BYTE _IL5 :1; + IO_BYTE _IL6 :1; + IO_BYTE _IL7 :1; + }bit; + }PILR09STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IL0 :1; + IO_BYTE _IL1 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }PILR10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EIL0 :1; + IO_BYTE _EIL1 :1; + IO_BYTE _EIL2 :1; + IO_BYTE _EIL3 :1; + IO_BYTE _EIL4 :1; + IO_BYTE _EIL5 :1; + IO_BYTE _EIL6 :1; + IO_BYTE _EIL7 :1; + }bit; + }EPILR00STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EIL0 :1; + IO_BYTE _EIL1 :1; + IO_BYTE _EIL2 :1; + IO_BYTE _EIL3 :1; + IO_BYTE _EIL4 :1; + IO_BYTE _EIL5 :1; + IO_BYTE _EIL6 :1; + IO_BYTE _EIL7 :1; + }bit; + }EPILR01STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EIL0 :1; + IO_BYTE _EIL1 :1; + IO_BYTE _EIL2 :1; + IO_BYTE _EIL3 :1; + IO_BYTE _EIL4 :1; + IO_BYTE _EIL5 :1; + IO_BYTE _EIL6 :1; + IO_BYTE _EIL7 :1; + }bit; + }EPILR02STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EIL0 :1; + IO_BYTE _EIL1 :1; + IO_BYTE _EIL2 :1; + IO_BYTE _EIL3 :1; + IO_BYTE _EIL4 :1; + IO_BYTE _EIL5 :1; + IO_BYTE _EIL6 :1; + IO_BYTE _EIL7 :1; + }bit; + }EPILR03STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EIL0 :1; + IO_BYTE _EIL1 :1; + IO_BYTE _EIL2 :1; + IO_BYTE _EIL3 :1; + IO_BYTE _EIL4 :1; + IO_BYTE _EIL5 :1; + IO_BYTE _EIL6 :1; + IO_BYTE _EIL7 :1; + }bit; + }EPILR04STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EIL0 :1; + IO_BYTE _EIL1 :1; + IO_BYTE _EIL2 :1; + IO_BYTE _EIL3 :1; + IO_BYTE _EIL4 :1; + IO_BYTE _EIL5 :1; + IO_BYTE _EIL6 :1; + IO_BYTE _EIL7 :1; + }bit; + }EPILR05STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EIL0 :1; + IO_BYTE _EIL1 :1; + IO_BYTE _EIL2 :1; + IO_BYTE _EIL3 :1; + IO_BYTE _EIL4 :1; + IO_BYTE _EIL5 :1; + IO_BYTE _EIL6 :1; + IO_BYTE _EIL7 :1; + }bit; + }EPILR06STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EIL0 :1; + IO_BYTE _EIL1 :1; + IO_BYTE _EIL2 :1; + IO_BYTE _EIL3 :1; + IO_BYTE _EIL4 :1; + IO_BYTE _EIL5 :1; + IO_BYTE _EIL6 :1; + IO_BYTE _EIL7 :1; + }bit; + }EPILR07STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EIL0 :1; + IO_BYTE _EIL1 :1; + IO_BYTE _EIL2 :1; + IO_BYTE _EIL3 :1; + IO_BYTE _EIL4 :1; + IO_BYTE _EIL5 :1; + IO_BYTE _EIL6 :1; + IO_BYTE _EIL7 :1; + }bit; + }EPILR08STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EIL0 :1; + IO_BYTE _EIL1 :1; + IO_BYTE _EIL2 :1; + IO_BYTE _EIL3 :1; + IO_BYTE _EIL4 :1; + IO_BYTE _EIL5 :1; + IO_BYTE _EIL6 :1; + IO_BYTE _EIL7 :1; + }bit; + }EPILR09STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EIL0 :1; + IO_BYTE _EIL1 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }EPILR10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OD0 :1; + IO_BYTE _OD1 :1; + IO_BYTE _OD2 :1; + IO_BYTE _OD3 :1; + IO_BYTE _OD4 :1; + IO_BYTE _OD5 :1; + IO_BYTE _OD6 :1; + IO_BYTE _OD7 :1; + }bit; + }PODR00STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OD0 :1; + IO_BYTE _OD1 :1; + IO_BYTE _OD2 :1; + IO_BYTE _OD3 :1; + IO_BYTE _OD4 :1; + IO_BYTE _OD5 :1; + IO_BYTE _OD6 :1; + IO_BYTE _OD7 :1; + }bit; + }PODR01STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OD0 :1; + IO_BYTE _OD1 :1; + IO_BYTE _OD2 :1; + IO_BYTE _OD3 :1; + IO_BYTE _OD4 :1; + IO_BYTE _OD5 :1; + IO_BYTE _OD6 :1; + IO_BYTE _OD7 :1; + }bit; + }PODR02STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OD0 :1; + IO_BYTE _OD1 :1; + IO_BYTE _OD2 :1; + IO_BYTE _OD3 :1; + IO_BYTE _OD4 :1; + IO_BYTE _OD5 :1; + IO_BYTE _OD6 :1; + IO_BYTE _OD7 :1; + }bit; + }PODR03STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OD0 :1; + IO_BYTE _OD1 :1; + IO_BYTE _OD2 :1; + IO_BYTE _OD3 :1; + IO_BYTE _OD4 :1; + IO_BYTE _OD5 :1; + IO_BYTE _OD6 :1; + IO_BYTE _OD7 :1; + }bit; + }PODR04STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OD0 :1; + IO_BYTE _OD1 :1; + IO_BYTE _OD2 :1; + IO_BYTE _OD3 :1; + IO_BYTE _OD4 :1; + IO_BYTE _OD5 :1; + IO_BYTE _OD6 :1; + IO_BYTE _OD7 :1; + }bit; + }PODR05STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OD0 :1; + IO_BYTE _OD1 :1; + IO_BYTE _OD2 :1; + IO_BYTE _OD3 :1; + IO_BYTE _OD4 :1; + IO_BYTE _OD5 :1; + IO_BYTE _OD6 :1; + IO_BYTE _OD7 :1; + }bit; + }PODR06STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OD0 :1; + IO_BYTE _OD1 :1; + IO_BYTE _OD2 :1; + IO_BYTE _OD3 :1; + IO_BYTE _OD4 :1; + IO_BYTE _OD5 :1; + IO_BYTE _OD6 :1; + IO_BYTE _OD7 :1; + }bit; + }PODR07STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OD0 :1; + IO_BYTE _OD1 :1; + IO_BYTE _OD2 :1; + IO_BYTE _OD3 :1; + IO_BYTE _OD4 :1; + IO_BYTE _OD5 :1; + IO_BYTE _OD6 :1; + IO_BYTE _OD7 :1; + }bit; + }PODR08STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OD0 :1; + IO_BYTE _OD1 :1; + IO_BYTE _OD2 :1; + IO_BYTE _OD3 :1; + IO_BYTE _OD4 :1; + IO_BYTE _OD5 :1; + IO_BYTE _OD6 :1; + IO_BYTE _OD7 :1; + }bit; + }PODR09STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OD0 :1; + IO_BYTE _OD1 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }PODR10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _HD0 :1; + IO_BYTE _HD1 :1; + IO_BYTE _HD2 :1; + IO_BYTE _HD3 :1; + IO_BYTE _HD4 :1; + IO_BYTE _HD5 :1; + IO_BYTE _HD6 :1; + IO_BYTE _HD7 :1; + }bit; + }PHDR08STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _HD0 :1; + IO_BYTE _HD1 :1; + IO_BYTE _HD2 :1; + IO_BYTE _HD3 :1; + IO_BYTE _HD4 :1; + IO_BYTE _HD5 :1; + IO_BYTE _HD6 :1; + IO_BYTE _HD7 :1; + }bit; + }PHDR09STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _HD0 :1; + IO_BYTE _HD1 :1; + IO_BYTE _HD2 :1; + IO_BYTE _HD3 :1; + IO_BYTE _HD4 :1; + IO_BYTE _HD5 :1; + IO_BYTE _HD6 :1; + IO_BYTE _HD7 :1; + }bit; + }PHDR10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PU0 :1; + IO_BYTE _PU1 :1; + IO_BYTE _PU2 :1; + IO_BYTE _PU3 :1; + IO_BYTE _PU4 :1; + IO_BYTE _PU5 :1; + IO_BYTE _PU6 :1; + IO_BYTE _PU7 :1; + }bit; + }PUCR00STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PU0 :1; + IO_BYTE _PU1 :1; + IO_BYTE _PU2 :1; + IO_BYTE _PU3 :1; + IO_BYTE _PU4 :1; + IO_BYTE _PU5 :1; + IO_BYTE _PU6 :1; + IO_BYTE _PU7 :1; + }bit; + }PUCR01STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PU0 :1; + IO_BYTE _PU1 :1; + IO_BYTE _PU2 :1; + IO_BYTE _PU3 :1; + IO_BYTE _PU4 :1; + IO_BYTE _PU5 :1; + IO_BYTE _PU6 :1; + IO_BYTE _PU7 :1; + }bit; + }PUCR02STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PU0 :1; + IO_BYTE _PU1 :1; + IO_BYTE _PU2 :1; + IO_BYTE _PU3 :1; + IO_BYTE _PU4 :1; + IO_BYTE _PU5 :1; + IO_BYTE _PU6 :1; + IO_BYTE _PU7 :1; + }bit; + }PUCR03STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PU0 :1; + IO_BYTE _PU1 :1; + IO_BYTE _PU2 :1; + IO_BYTE _PU3 :1; + IO_BYTE _PU4 :1; + IO_BYTE _PU5 :1; + IO_BYTE _PU6 :1; + IO_BYTE _PU7 :1; + }bit; + }PUCR04STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PU0 :1; + IO_BYTE _PU1 :1; + IO_BYTE _PU2 :1; + IO_BYTE _PU3 :1; + IO_BYTE _PU4 :1; + IO_BYTE _PU5 :1; + IO_BYTE _PU6 :1; + IO_BYTE _PU7 :1; + }bit; + }PUCR05STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PU0 :1; + IO_BYTE _PU1 :1; + IO_BYTE _PU2 :1; + IO_BYTE _PU3 :1; + IO_BYTE _PU4 :1; + IO_BYTE _PU5 :1; + IO_BYTE _PU6 :1; + IO_BYTE _PU7 :1; + }bit; + }PUCR06STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PU0 :1; + IO_BYTE _PU1 :1; + IO_BYTE _PU2 :1; + IO_BYTE _PU3 :1; + IO_BYTE _PU4 :1; + IO_BYTE _PU5 :1; + IO_BYTE _PU6 :1; + IO_BYTE _PU7 :1; + }bit; + }PUCR07STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PU0 :1; + IO_BYTE _PU1 :1; + IO_BYTE _PU2 :1; + IO_BYTE _PU3 :1; + IO_BYTE _PU4 :1; + IO_BYTE _PU5 :1; + IO_BYTE _PU6 :1; + IO_BYTE _PU7 :1; + }bit; + }PUCR08STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PU0 :1; + IO_BYTE _PU1 :1; + IO_BYTE _PU2 :1; + IO_BYTE _PU3 :1; + IO_BYTE _PU4 :1; + IO_BYTE _PU5 :1; + IO_BYTE _PU6 :1; + IO_BYTE _PU7 :1; + }bit; + }PUCR09STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PU0 :1; + IO_BYTE _PU1 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }PUCR10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PS0 :1; + IO_BYTE _PS1 :1; + IO_BYTE _PS2 :1; + IO_BYTE _PS3 :1; + IO_BYTE _PS4 :1; + IO_BYTE _PS5 :1; + IO_BYTE _PS6 :1; + IO_BYTE _PS7 :1; + }bit; + }EPSR00STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PS0 :1; + IO_BYTE _PS1 :1; + IO_BYTE _PS2 :1; + IO_BYTE _PS3 :1; + IO_BYTE _PS4 :1; + IO_BYTE _PS5 :1; + IO_BYTE _PS6 :1; + IO_BYTE _PS7 :1; + }bit; + }EPSR01STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PS0 :1; + IO_BYTE _PS1 :1; + IO_BYTE _PS2 :1; + IO_BYTE _PS3 :1; + IO_BYTE _PS4 :1; + IO_BYTE _PS5 :1; + IO_BYTE _PS6 :1; + IO_BYTE _PS7 :1; + }bit; + }EPSR02STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PS0 :1; + IO_BYTE _PS1 :1; + IO_BYTE _PS2 :1; + IO_BYTE _PS3 :1; + IO_BYTE _PS4 :1; + IO_BYTE _PS5 :1; + IO_BYTE _PS6 :1; + IO_BYTE _PS7 :1; + }bit; + }EPSR03STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PS0 :1; + IO_BYTE _PS1 :1; + IO_BYTE _PS2 :1; + IO_BYTE _PS3 :1; + IO_BYTE _PS4 :1; + IO_BYTE _PS5 :1; + IO_BYTE _PS6 :1; + IO_BYTE _PS7 :1; + }bit; + }EPSR04STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PS0 :1; + IO_BYTE _PS1 :1; + IO_BYTE _PS2 :1; + IO_BYTE _PS3 :1; + IO_BYTE _PS4 :1; + IO_BYTE _PS5 :1; + IO_BYTE _PS6 :1; + IO_BYTE _PS7 :1; + }bit; + }EPSR05STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PS0 :1; + IO_BYTE _PS1 :1; + IO_BYTE _PS2 :1; + IO_BYTE _PS3 :1; + IO_BYTE _PS4 :1; + IO_BYTE _PS5 :1; + IO_BYTE _PS6 :1; + IO_BYTE _PS7 :1; + }bit; + }EPSR06STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PS0 :1; + IO_BYTE _PS1 :1; + IO_BYTE _PS2 :1; + IO_BYTE _PS3 :1; + IO_BYTE _PS4 :1; + IO_BYTE _PS5 :1; + IO_BYTE _PS6 :1; + IO_BYTE _PS7 :1; + }bit; + }EPSR07STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PS0 :1; + IO_BYTE _PS1 :1; + IO_BYTE _PS2 :1; + IO_BYTE _PS3 :1; + IO_BYTE _PS4 :1; + IO_BYTE _PS5 :1; + IO_BYTE _PS6 :1; + IO_BYTE _PS7 :1; + }bit; + }EPSR08STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PS0 :1; + IO_BYTE _PS1 :1; + IO_BYTE _PS2 :1; + IO_BYTE _PS3 :1; + IO_BYTE _PS4 :1; + IO_BYTE _PS5 :1; + IO_BYTE _PS6 :1; + IO_BYTE _PS7 :1; + }bit; + }EPSR09STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PS0 :1; + IO_BYTE _PS1 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }EPSR10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ADE0 :1; + IO_BYTE _ADE1 :1; + IO_BYTE _ADE2 :1; + IO_BYTE _ADE3 :1; + IO_BYTE _ADE4 :1; + IO_BYTE _ADE5 :1; + IO_BYTE _ADE6 :1; + IO_BYTE _ADE7 :1; + }bit; + }ADER0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ADE8 :1; + IO_BYTE _ADE9 :1; + IO_BYTE _ADE10 :1; + IO_BYTE _ADE11 :1; + IO_BYTE _ADE12 :1; + IO_BYTE _ADE13 :1; + IO_BYTE _ADE14 :1; + IO_BYTE _ADE15 :1; + }bit; + }ADER1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ADE16 :1; + IO_BYTE _ADE17 :1; + IO_BYTE _ADE18 :1; + IO_BYTE _ADE19 :1; + IO_BYTE _ADE20 :1; + IO_BYTE _ADE21 :1; + IO_BYTE _ADE22 :1; + IO_BYTE _ADE23 :1; + }bit; + }ADER2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INT0_R :1; + IO_BYTE _INT1_R :1; + IO_BYTE _INT2_R :1; + IO_BYTE _INT3_R :1; + IO_BYTE _INT4_R :1; + IO_BYTE _INT5_R :1; + IO_BYTE _INT6_R :1; + IO_BYTE _INT7_R :1; + }bit; + }PRRR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INT8_R :1; + IO_BYTE _INT9_R :1; + IO_BYTE _INT10_R :1; + IO_BYTE _INT11_R :1; + IO_BYTE _INT12_R :1; + IO_BYTE _INT13_R :1; + IO_BYTE _INT14_R :1; + IO_BYTE _INT15_R :1; + }bit; + }PRRR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PPG0_R :1; + IO_BYTE _PPG1_R :1; + IO_BYTE _PPG2_R :1; + IO_BYTE _PPG3_R :1; + IO_BYTE _PPG4_R :1; + IO_BYTE _PPG5_R :1; + IO_BYTE _PPG6_R :1; + IO_BYTE _PPG7_R :1; + }bit; + }PRRR2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TIN0_R :1; + IO_BYTE _TOT0_R :1; + IO_BYTE _TIN1_R :1; + IO_BYTE _TOT1_R :1; + IO_BYTE _TIN2_R :1; + IO_BYTE _TOT2_R :1; + IO_BYTE _TIN3_R :1; + IO_BYTE _TOT3_R :1; + }bit; + }PRRR3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _IN0_R :1; + IO_BYTE _IN1_R :1; + IO_BYTE _IN2_R :1; + IO_BYTE _IN3_R :1; + IO_BYTE _IN4_R :1; + IO_BYTE _IN5_R :1; + IO_BYTE _IN6_R :1; + IO_BYTE _IN7_R :1; + }bit; + }PRRR4STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OUT0_R :1; + IO_BYTE _OUT1_R :1; + IO_BYTE _OUT2_R :1; + IO_BYTE _OUT3_R :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _OUT6_R :1; + IO_BYTE _OUT7_R :1; + }bit; + }PRRR5STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SGO0_R :1; + IO_BYTE _SGA0_R :1; + IO_BYTE _FRCK0_R :1; + IO_BYTE _SIN2_R :1; + IO_BYTE _SOT2_R :1; + IO_BYTE _SCK2_R :1; + IO_BYTE _CKOT1_R :1; + IO_BYTE _CKOTX1_R :1; + }bit; + }PRRR6STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ADTG_R :1; + IO_BYTE _NMI_R :1; + IO_BYTE _CS3_R :1; + IO_BYTE _INT3_R1 :1; + IO_BYTE _INT4_R1 :1; + IO_BYTE _INT5_R1 :1; + IO_BYTE _RX2_R :1; + IO_BYTE _TX2_R :1; + }bit; + }PRRR7STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SIN7_R :1; + IO_BYTE _SOT7_R :1; + IO_BYTE _SCK7_R :1; + IO_BYTE _SIN8_R :1; + IO_BYTE _SOT8_R :1; + IO_BYTE _SCK8_R :1; + IO_BYTE _SIN9_R :1; + IO_BYTE _SOT9_R :1; + }bit; + }PRRR8STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SCK9_R :1; + IO_BYTE _SGO1_R :1; + IO_BYTE _SGA1_R :1; + IO_BYTE _FRCK2_R :1; + IO_BYTE _OUT10_R :1; + IO_BYTE _CKOT0_R :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }PRRR9STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }WTBR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D0 :1; + IO_BYTE _D1 :1; + IO_BYTE _D2 :1; + IO_BYTE _D3 :1; + IO_BYTE _D4 :1; + IO_BYTE _D5 :1; + IO_BYTE _D6 :1; + IO_BYTE _D7 :1; + }bit; + }WTBRL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D8 :1; + IO_BYTE _D9 :1; + IO_BYTE _D10 :1; + IO_BYTE _D11 :1; + IO_BYTE _D12 :1; + IO_BYTE _D13 :1; + IO_BYTE _D14 :1; + IO_BYTE _D15 :1; + }bit; + }WTBRH0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _D16 :1; + IO_BYTE _D17 :1; + IO_BYTE _D18 :1; + IO_BYTE _D19 :1; + IO_BYTE _D20 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _D1 :5; + }bitc; + }WTBR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _S0 :1; + IO_BYTE _S1 :1; + IO_BYTE _S2 :1; + IO_BYTE _S3 :1; + IO_BYTE _S4 :1; + IO_BYTE _S5 :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _S :6; + }bitc; + }WTSRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _M0 :1; + IO_BYTE _M1 :1; + IO_BYTE _M2 :1; + IO_BYTE _M3 :1; + IO_BYTE _M4 :1; + IO_BYTE _M5 :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _M :6; + }bitc; + }WTMRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _H0 :1; + IO_BYTE _H1 :1; + IO_BYTE _H2 :1; + IO_BYTE _H3 :1; + IO_BYTE _H4 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _H :5; + }bitc; + }WTHRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INT4 :1; + IO_BYTE _INTE4 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }WTCERSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CKSEL0 :1; + IO_BYTE _CKSEL1 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _CKSEL :2; + }bitc; + }WTCKSRSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _ST :1; + IO_WORD _OE :1; + IO_WORD _UPDT :1; + IO_WORD _RUN :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _INT0 :1; + IO_WORD _INTE0 :1; + IO_WORD _INT1 :1; + IO_WORD _INTE1 :1; + IO_WORD _INT2 :1; + IO_WORD _INTE2 :1; + IO_WORD _INT3 :1; + IO_WORD _INTE3 :1; + }bit; + }WTCRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ST :1; + IO_BYTE _OE :1; + IO_BYTE _UPDT :1; + IO_BYTE _RUN :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }WTCRLSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INT0 :1; + IO_BYTE _INTE0 :1; + IO_BYTE _INT1 :1; + IO_BYTE _INTE1 :1; + IO_BYTE _INT2 :1; + IO_BYTE _INTE2 :1; + IO_BYTE _INT3 :1; + IO_BYTE _INTE3 :1; + }bit; + }WTCRHSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INTEN :1; + IO_BYTE _INT :1; + IO_BYTE _CKSEL :1; + IO_BYTE :1; + IO_BYTE _STRT :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _RESV :1; + }bit; + }CUCRSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _TDD0 :1; + IO_WORD _TDD1 :1; + IO_WORD _TDD2 :1; + IO_WORD _TDD3 :1; + IO_WORD _TDD4 :1; + IO_WORD _TDD5 :1; + IO_WORD _TDD6 :1; + IO_WORD _TDD7 :1; + IO_WORD _TDD8 :1; + IO_WORD _TDD9 :1; + IO_WORD _TDD10 :1; + IO_WORD _TDD11 :1; + IO_WORD _TDD12 :1; + IO_WORD _TDD13 :1; + IO_WORD _TDD14 :1; + IO_WORD _TDD15 :1; + }bit; + struct{ + IO_WORD _TDD :16; + }bitc; + }CUTDSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TDD0 :1; + IO_BYTE _TDD1 :1; + IO_BYTE _TDD2 :1; + IO_BYTE _TDD3 :1; + IO_BYTE _TDD4 :1; + IO_BYTE _TDD5 :1; + IO_BYTE _TDD6 :1; + IO_BYTE _TDD7 :1; + }bit; + }CUTDLSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TDD8 :1; + IO_BYTE _TDD9 :1; + IO_BYTE _TDD10 :1; + IO_BYTE _TDD11 :1; + IO_BYTE _TDD12 :1; + IO_BYTE _TDD13 :1; + IO_BYTE _TDD14 :1; + IO_BYTE _TDD15 :1; + }bit; + }CUTDHSTR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _TDR0 :1; + IO_LWORD _TDR1 :1; + IO_LWORD _TDR2 :1; + IO_LWORD _TDR3 :1; + IO_LWORD _TDR4 :1; + IO_LWORD _TDR5 :1; + IO_LWORD _TDR6 :1; + IO_LWORD _TDR7 :1; + IO_LWORD _TDR8 :1; + IO_LWORD _TDR9 :1; + IO_LWORD _TDR10 :1; + IO_LWORD _TDR11 :1; + IO_LWORD _TDR12 :1; + IO_LWORD _TDR13 :1; + IO_LWORD _TDR14 :1; + IO_LWORD _TDR15 :1; + IO_LWORD _TDR16 :1; + IO_LWORD _TDR17 :1; + IO_LWORD _TDR18 :1; + IO_LWORD _TDR19 :1; + IO_LWORD _TDR20 :1; + IO_LWORD _TDR21 :1; + IO_LWORD _TDR22 :1; + IO_LWORD _TDR23 :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + }bit; + }CUTRSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _TDR0 :1; + IO_WORD _TDR1 :1; + IO_WORD _TDR2 :1; + IO_WORD _TDR3 :1; + IO_WORD _TDR4 :1; + IO_WORD _TDR5 :1; + IO_WORD _TDR6 :1; + IO_WORD _TDR7 :1; + IO_WORD _TDR8 :1; + IO_WORD _TDR9 :1; + IO_WORD _TDR10 :1; + IO_WORD _TDR11 :1; + IO_WORD _TDR12 :1; + IO_WORD _TDR13 :1; + IO_WORD _TDR14 :1; + IO_WORD _TDR15 :1; + }bit; + }CUTR2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TDR0 :1; + IO_BYTE _TDR1 :1; + IO_BYTE _TDR2 :1; + IO_BYTE _TDR3 :1; + IO_BYTE _TDR4 :1; + IO_BYTE _TDR5 :1; + IO_BYTE _TDR6 :1; + IO_BYTE _TDR7 :1; + }bit; + }CUTR2LSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TDR8 :1; + IO_BYTE _TDR9 :1; + IO_BYTE _TDR10 :1; + IO_BYTE _TDR11 :1; + IO_BYTE _TDR12 :1; + IO_BYTE _TDR13 :1; + IO_BYTE _TDR14 :1; + IO_BYTE _TDR15 :1; + }bit; + }CUTR2HSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _TDR16 :1; + IO_WORD _TDR17 :1; + IO_WORD _TDR18 :1; + IO_WORD _TDR19 :1; + IO_WORD _TDR20 :1; + IO_WORD _TDR21 :1; + IO_WORD _TDR22 :1; + IO_WORD _TDR23 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }CUTR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TDR16 :1; + IO_BYTE _TDR17 :1; + IO_BYTE _TDR18 :1; + IO_BYTE _TDR19 :1; + IO_BYTE _TDR20 :1; + IO_BYTE _TDR21 :1; + IO_BYTE _TDR22 :1; + IO_BYTE _TDR23 :1; + }bit; + }CUTR1LSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }CUTR1HSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TMIS0 :1; + IO_BYTE _TMIS1 :1; + IO_BYTE _TMIS2 :1; + IO_BYTE _TMIS3 :1; + IO_BYTE _TMIS4 :1; + IO_BYTE _TMIS5 :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }TMISRSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SOE :1; + IO_BYTE _SCKE :1; + IO_BYTE _UPCL :1; + IO_BYTE _REST :1; + IO_BYTE _EXT :1; + IO_BYTE _OTO :1; + IO_BYTE _MD0 :1; + IO_BYTE _MD1 :1; + }bit; + struct{ + IO_BYTE :6; + IO_BYTE _MD :2; + }bitc; + }SMR7STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TXE :1; + IO_BYTE _RXE :1; + IO_BYTE _CRE :1; + IO_BYTE _AD :1; + IO_BYTE _CL :1; + IO_BYTE _SBL :1; + IO_BYTE _P :1; + IO_BYTE _PEN :1; + }bit; + }SCR7STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TIE :1; + IO_BYTE _RIE :1; + IO_BYTE _BDS :1; + IO_BYTE _TDRE :1; + IO_BYTE _RDRF :1; + IO_BYTE _FRE :1; + IO_BYTE _ORE :1; + IO_BYTE _PE :1; + }bit; + }SSR7STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TBI :1; + IO_BYTE _RBI :1; + IO_BYTE _BIE :1; + IO_BYTE _SSM :1; + IO_BYTE _SCDE :1; + IO_BYTE _MS :1; + IO_BYTE _LBR :1; + IO_BYTE _INV :1; + }bit; + }ECCR7STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SCES :1; + IO_BYTE _CCO :1; + IO_BYTE _SIOP :1; + IO_BYTE _SOPE :1; + IO_BYTE _LBL0 :1; + IO_BYTE _LBL1 :1; + IO_BYTE _LBD :1; + IO_BYTE _LBIE :1; + }bit; + struct{ + IO_BYTE :4; + IO_BYTE _LBL :2; + }bitc; + }ESCR7STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _BGR0 :1; + IO_WORD _BGR1 :1; + IO_WORD _BGR2 :1; + IO_WORD _BGR3 :1; + IO_WORD _BGR4 :1; + IO_WORD _BGR5 :1; + IO_WORD _BGR6 :1; + IO_WORD _BGR7 :1; + IO_WORD _BGR8 :1; + IO_WORD _BGR9 :1; + IO_WORD _BGR10 :1; + IO_WORD _BGR11 :1; + IO_WORD _BGR12 :1; + IO_WORD _BGR13 :1; + IO_WORD _BGR14 :1; + IO_WORD _BGR15 :1; + }bit; + struct{ + IO_WORD _BGR :16; + }bitc; + }BGR7STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _BGR0 :1; + IO_BYTE _BGR1 :1; + IO_BYTE _BGR2 :1; + IO_BYTE _BGR3 :1; + IO_BYTE _BGR4 :1; + IO_BYTE _BGR5 :1; + IO_BYTE _BGR6 :1; + IO_BYTE _BGR7 :1; + }bit; + }BGRL7STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _BGR8 :1; + IO_BYTE _BGR9 :1; + IO_BYTE _BGR10 :1; + IO_BYTE _BGR11 :1; + IO_BYTE _BGR12 :1; + IO_BYTE _BGR13 :1; + IO_BYTE _BGR14 :1; + IO_BYTE _BGR15 :1; + }bit; + }BGRH7STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _AICD :1; + IO_BYTE _RBI :1; + IO_BYTE _RDRF :1; + IO_BYTE _TDRE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }ESIR7STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SOE :1; + IO_BYTE _SCKE :1; + IO_BYTE _UPCL :1; + IO_BYTE _REST :1; + IO_BYTE _EXT :1; + IO_BYTE _OTO :1; + IO_BYTE _MD0 :1; + IO_BYTE _MD1 :1; + }bit; + struct{ + IO_BYTE :6; + IO_BYTE _MD :2; + }bitc; + }SMR8STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TXE :1; + IO_BYTE _RXE :1; + IO_BYTE _CRE :1; + IO_BYTE _AD :1; + IO_BYTE _CL :1; + IO_BYTE _SBL :1; + IO_BYTE _P :1; + IO_BYTE _PEN :1; + }bit; + }SCR8STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TIE :1; + IO_BYTE _RIE :1; + IO_BYTE _BDS :1; + IO_BYTE _TDRE :1; + IO_BYTE _RDRF :1; + IO_BYTE _FRE :1; + IO_BYTE _ORE :1; + IO_BYTE _PE :1; + }bit; + }SSR8STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TBI :1; + IO_BYTE _RBI :1; + IO_BYTE _BIE :1; + IO_BYTE _SSM :1; + IO_BYTE _SCDE :1; + IO_BYTE _MS :1; + IO_BYTE _LBR :1; + IO_BYTE _INV :1; + }bit; + }ECCR8STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SCES :1; + IO_BYTE _CCO :1; + IO_BYTE _SIOP :1; + IO_BYTE _SOPE :1; + IO_BYTE _LBL0 :1; + IO_BYTE _LBL1 :1; + IO_BYTE _LBD :1; + IO_BYTE _LBIE :1; + }bit; + struct{ + IO_BYTE :4; + IO_BYTE _LBL :2; + }bitc; + }ESCR8STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _BGR0 :1; + IO_WORD _BGR1 :1; + IO_WORD _BGR2 :1; + IO_WORD _BGR3 :1; + IO_WORD _BGR4 :1; + IO_WORD _BGR5 :1; + IO_WORD _BGR6 :1; + IO_WORD _BGR7 :1; + IO_WORD _BGR8 :1; + IO_WORD _BGR9 :1; + IO_WORD _BGR10 :1; + IO_WORD _BGR11 :1; + IO_WORD _BGR12 :1; + IO_WORD _BGR13 :1; + IO_WORD _BGR14 :1; + IO_WORD _BGR15 :1; + }bit; + struct{ + IO_WORD _BGR :16; + }bitc; + }BGR8STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _BGR0 :1; + IO_BYTE _BGR1 :1; + IO_BYTE _BGR2 :1; + IO_BYTE _BGR3 :1; + IO_BYTE _BGR4 :1; + IO_BYTE _BGR5 :1; + IO_BYTE _BGR6 :1; + IO_BYTE _BGR7 :1; + }bit; + }BGRL8STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _BGR8 :1; + IO_BYTE _BGR9 :1; + IO_BYTE _BGR10 :1; + IO_BYTE _BGR11 :1; + IO_BYTE _BGR12 :1; + IO_BYTE _BGR13 :1; + IO_BYTE _BGR14 :1; + IO_BYTE _BGR15 :1; + }bit; + }BGRH8STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _AICD :1; + IO_BYTE _RBI :1; + IO_BYTE _RDRF :1; + IO_BYTE _TDRE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }ESIR8STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SOE :1; + IO_BYTE _SCKE :1; + IO_BYTE _UPCL :1; + IO_BYTE _REST :1; + IO_BYTE _EXT :1; + IO_BYTE _OTO :1; + IO_BYTE _MD0 :1; + IO_BYTE _MD1 :1; + }bit; + struct{ + IO_BYTE :6; + IO_BYTE _MD :2; + }bitc; + }SMR9STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TXE :1; + IO_BYTE _RXE :1; + IO_BYTE _CRE :1; + IO_BYTE _AD :1; + IO_BYTE _CL :1; + IO_BYTE _SBL :1; + IO_BYTE _P :1; + IO_BYTE _PEN :1; + }bit; + }SCR9STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TIE :1; + IO_BYTE _RIE :1; + IO_BYTE _BDS :1; + IO_BYTE _TDRE :1; + IO_BYTE _RDRF :1; + IO_BYTE _FRE :1; + IO_BYTE _ORE :1; + IO_BYTE _PE :1; + }bit; + }SSR9STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TBI :1; + IO_BYTE _RBI :1; + IO_BYTE _BIE :1; + IO_BYTE _SSM :1; + IO_BYTE _SCDE :1; + IO_BYTE _MS :1; + IO_BYTE _LBR :1; + IO_BYTE _INV :1; + }bit; + }ECCR9STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _SCES :1; + IO_BYTE _CCO :1; + IO_BYTE _SIOP :1; + IO_BYTE _SOPE :1; + IO_BYTE _LBL0 :1; + IO_BYTE _LBL1 :1; + IO_BYTE _LBD :1; + IO_BYTE _LBIE :1; + }bit; + struct{ + IO_BYTE :4; + IO_BYTE _LBL :2; + }bitc; + }ESCR9STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _BGR0 :1; + IO_WORD _BGR1 :1; + IO_WORD _BGR2 :1; + IO_WORD _BGR3 :1; + IO_WORD _BGR4 :1; + IO_WORD _BGR5 :1; + IO_WORD _BGR6 :1; + IO_WORD _BGR7 :1; + IO_WORD _BGR8 :1; + IO_WORD _BGR9 :1; + IO_WORD _BGR10 :1; + IO_WORD _BGR11 :1; + IO_WORD _BGR12 :1; + IO_WORD _BGR13 :1; + IO_WORD _BGR14 :1; + IO_WORD _BGR15 :1; + }bit; + struct{ + IO_WORD _BGR :16; + }bitc; + }BGR9STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _BGR0 :1; + IO_BYTE _BGR1 :1; + IO_BYTE _BGR2 :1; + IO_BYTE _BGR3 :1; + IO_BYTE _BGR4 :1; + IO_BYTE _BGR5 :1; + IO_BYTE _BGR6 :1; + IO_BYTE _BGR7 :1; + }bit; + }BGRL9STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _BGR8 :1; + IO_BYTE _BGR9 :1; + IO_BYTE _BGR10 :1; + IO_BYTE _BGR11 :1; + IO_BYTE _BGR12 :1; + IO_BYTE _BGR13 :1; + IO_BYTE _BGR14 :1; + IO_BYTE _BGR15 :1; + }bit; + }BGRH9STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _AICD :1; + IO_BYTE _RBI :1; + IO_BYTE _RDRF :1; + IO_BYTE _TDRE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }ESIR9STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PD :1; + IO_BYTE _IEN :1; + IO_BYTE _IRQ :1; + IO_BYTE _OUT1 :1; + IO_BYTE _OUT2 :1; + IO_BYTE _UVEN :1; + IO_BYTE _OVEN :1; + IO_BYTE _CMD :1; + }bit; + }ACSR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INTREF :1; + IO_BYTE :1; + IO_BYTE _ACE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }AECSR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PD :1; + IO_BYTE _IEN :1; + IO_BYTE _IRQ :1; + IO_BYTE _OUT1 :1; + IO_BYTE _OUT2 :1; + IO_BYTE _UVEN :1; + IO_BYTE _OVEN :1; + IO_BYTE _CMD :1; + }bit; + }ACSR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INTREF :1; + IO_BYTE :1; + IO_BYTE _ACE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }AECSR1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PTMR6STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PCSR6STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PDUT6STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _OSEL :1; + IO_WORD _OE :1; + IO_WORD _IRS0 :1; + IO_WORD _IRS1 :1; + IO_WORD _IRQF :1; + IO_WORD _IREN :1; + IO_WORD _EGS0 :1; + IO_WORD _EGS1 :1; + IO_WORD :1; + IO_WORD _PGMS :1; + IO_WORD _CKS0 :1; + IO_WORD _CKS1 :1; + IO_WORD _RTRG :1; + IO_WORD _MDSE :1; + IO_WORD _STGR :1; + IO_WORD _CNTE :1; + }bit; + struct{ + IO_WORD :2; + IO_WORD _IRS :2; + IO_WORD :2; + IO_WORD _EGS :2; + IO_WORD :2; + IO_WORD _CKS :2; + }bitc; + }PCN6STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OSEL :1; + IO_BYTE _OE :1; + IO_BYTE _IRS0 :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRQF :1; + IO_BYTE _IREN :1; + IO_BYTE _EGS0 :1; + IO_BYTE _EGS1 :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _IRS :2; + IO_BYTE :2; + IO_BYTE _EGS :2; + }bitc; + }PCNL6STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _PGMS :1; + IO_BYTE _CKS0 :1; + IO_BYTE _CKS1 :1; + IO_BYTE _RTRG :1; + IO_BYTE _MDSE :1; + IO_BYTE _STGR :1; + IO_BYTE _CNTE :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _CKS :2; + }bitc; + }PCNH6STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PTMR7STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PCSR7STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PDUT7STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _OSEL :1; + IO_WORD _OE :1; + IO_WORD _IRS0 :1; + IO_WORD _IRS1 :1; + IO_WORD _IRQF :1; + IO_WORD _IREN :1; + IO_WORD _EGS0 :1; + IO_WORD _EGS1 :1; + IO_WORD :1; + IO_WORD _PGMS :1; + IO_WORD _CKS0 :1; + IO_WORD _CKS1 :1; + IO_WORD _RTRG :1; + IO_WORD _MDSE :1; + IO_WORD _STGR :1; + IO_WORD _CNTE :1; + }bit; + struct{ + IO_WORD :2; + IO_WORD _IRS :2; + IO_WORD :2; + IO_WORD _EGS :2; + IO_WORD :2; + IO_WORD _CKS :2; + }bitc; + }PCN7STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OSEL :1; + IO_BYTE _OE :1; + IO_BYTE _IRS0 :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRQF :1; + IO_BYTE _IREN :1; + IO_BYTE _EGS0 :1; + IO_BYTE _EGS1 :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _IRS :2; + IO_BYTE :2; + IO_BYTE _EGS :2; + }bitc; + }PCNL7STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _PGMS :1; + IO_BYTE _CKS0 :1; + IO_BYTE _CKS1 :1; + IO_BYTE _RTRG :1; + IO_BYTE _MDSE :1; + IO_BYTE _STGR :1; + IO_BYTE _CNTE :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _CKS :2; + }bitc; + }PCNH7STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _TSEL00 :1; + IO_WORD _TSEL01 :1; + IO_WORD _TSEL02 :1; + IO_WORD _TSEL03 :1; + IO_WORD _TSEL10 :1; + IO_WORD _TSEL11 :1; + IO_WORD _TSEL12 :1; + IO_WORD _TSEL13 :1; + IO_WORD _TSEL20 :1; + IO_WORD _TSEL21 :1; + IO_WORD _TSEL22 :1; + IO_WORD _TSEL23 :1; + IO_WORD _TSEL30 :1; + IO_WORD _TSEL31 :1; + IO_WORD _TSEL32 :1; + IO_WORD _TSEL33 :1; + }bit; + struct{ + IO_WORD _TSEL0 :4; + IO_WORD _TSEL1 :4; + IO_WORD _TSEL2 :4; + IO_WORD _TSEL3 :4; + }bitc; + }GCN12STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TSEL00 :1; + IO_BYTE _TSEL01 :1; + IO_BYTE _TSEL02 :1; + IO_BYTE _TSEL03 :1; + IO_BYTE _TSEL10 :1; + IO_BYTE _TSEL11 :1; + IO_BYTE _TSEL12 :1; + IO_BYTE _TSEL13 :1; + }bit; + struct{ + IO_BYTE _TSEL0 :4; + IO_BYTE _TSEL1 :4; + }bitc; + }GCN1L2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TSEL20 :1; + IO_BYTE _TSEL21 :1; + IO_BYTE _TSEL22 :1; + IO_BYTE _TSEL23 :1; + IO_BYTE _TSEL30 :1; + IO_BYTE _TSEL31 :1; + IO_BYTE _TSEL32 :1; + IO_BYTE _TSEL33 :1; + }bit; + struct{ + IO_BYTE _TSEL2 :4; + IO_BYTE _TSEL3 :4; + }bitc; + }GCN1H2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _EN0 :1; + IO_WORD _EN1 :1; + IO_WORD _EN2 :1; + IO_WORD _EN3 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CKSEL0 :1; + IO_WORD _CKSEL1 :1; + IO_WORD _CKSEL2 :1; + IO_WORD _CKSEL3 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD _EN :4; + IO_WORD :4; + IO_WORD _CKSEL :4; + }bitc; + }GCN22STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EN0 :1; + IO_BYTE _EN1 :1; + IO_BYTE _EN2 :1; + IO_BYTE _EN3 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _EN :4; + }bitc; + }GCN2L2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CKSEL0 :1; + IO_BYTE _CKSEL1 :1; + IO_BYTE _CKSEL2 :1; + IO_BYTE _CKSEL3 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _CKSEL :4; + }bitc; + }GCN2H2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PTMR8STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PCSR8STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PDUT8STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _OSEL :1; + IO_WORD _OE :1; + IO_WORD _IRS0 :1; + IO_WORD _IRS1 :1; + IO_WORD _IRQF :1; + IO_WORD _IREN :1; + IO_WORD _EGS0 :1; + IO_WORD _EGS1 :1; + IO_WORD :1; + IO_WORD _PGMS :1; + IO_WORD _CKS0 :1; + IO_WORD _CKS1 :1; + IO_WORD _RTRG :1; + IO_WORD _MDSE :1; + IO_WORD _STGR :1; + IO_WORD _CNTE :1; + }bit; + struct{ + IO_WORD :2; + IO_WORD _IRS :2; + IO_WORD :2; + IO_WORD _EGS :2; + IO_WORD :2; + IO_WORD _CKS :2; + }bitc; + }PCN8STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OSEL :1; + IO_BYTE _OE :1; + IO_BYTE _IRS0 :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRQF :1; + IO_BYTE _IREN :1; + IO_BYTE _EGS0 :1; + IO_BYTE _EGS1 :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _IRS :2; + IO_BYTE :2; + IO_BYTE _EGS :2; + }bitc; + }PCNL8STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _PGMS :1; + IO_BYTE _CKS0 :1; + IO_BYTE _CKS1 :1; + IO_BYTE _RTRG :1; + IO_BYTE _MDSE :1; + IO_BYTE _STGR :1; + IO_BYTE _CNTE :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _CKS :2; + }bitc; + }PCNH8STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PTMR9STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PCSR9STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PDUT9STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _OSEL :1; + IO_WORD _OE :1; + IO_WORD _IRS0 :1; + IO_WORD _IRS1 :1; + IO_WORD _IRQF :1; + IO_WORD _IREN :1; + IO_WORD _EGS0 :1; + IO_WORD _EGS1 :1; + IO_WORD :1; + IO_WORD _PGMS :1; + IO_WORD _CKS0 :1; + IO_WORD _CKS1 :1; + IO_WORD _RTRG :1; + IO_WORD _MDSE :1; + IO_WORD _STGR :1; + IO_WORD _CNTE :1; + }bit; + struct{ + IO_WORD :2; + IO_WORD _IRS :2; + IO_WORD :2; + IO_WORD _EGS :2; + IO_WORD :2; + IO_WORD _CKS :2; + }bitc; + }PCN9STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OSEL :1; + IO_BYTE _OE :1; + IO_BYTE _IRS0 :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRQF :1; + IO_BYTE _IREN :1; + IO_BYTE _EGS0 :1; + IO_BYTE _EGS1 :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _IRS :2; + IO_BYTE :2; + IO_BYTE _EGS :2; + }bitc; + }PCNL9STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _PGMS :1; + IO_BYTE _CKS0 :1; + IO_BYTE _CKS1 :1; + IO_BYTE _RTRG :1; + IO_BYTE _MDSE :1; + IO_BYTE _STGR :1; + IO_BYTE _CNTE :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _CKS :2; + }bitc; + }PCNH9STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PTMR10STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PCSR10STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PDUT10STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _OSEL :1; + IO_WORD _OE :1; + IO_WORD _IRS0 :1; + IO_WORD _IRS1 :1; + IO_WORD _IRQF :1; + IO_WORD _IREN :1; + IO_WORD _EGS0 :1; + IO_WORD _EGS1 :1; + IO_WORD :1; + IO_WORD _PGMS :1; + IO_WORD _CKS0 :1; + IO_WORD _CKS1 :1; + IO_WORD _RTRG :1; + IO_WORD _MDSE :1; + IO_WORD _STGR :1; + IO_WORD _CNTE :1; + }bit; + struct{ + IO_WORD :2; + IO_WORD _IRS :2; + IO_WORD :2; + IO_WORD _EGS :2; + IO_WORD :2; + IO_WORD _CKS :2; + }bitc; + }PCN10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OSEL :1; + IO_BYTE _OE :1; + IO_BYTE _IRS0 :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRQF :1; + IO_BYTE _IREN :1; + IO_BYTE _EGS0 :1; + IO_BYTE _EGS1 :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _IRS :2; + IO_BYTE :2; + IO_BYTE _EGS :2; + }bitc; + }PCNL10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _PGMS :1; + IO_BYTE _CKS0 :1; + IO_BYTE _CKS1 :1; + IO_BYTE _RTRG :1; + IO_BYTE _MDSE :1; + IO_BYTE _STGR :1; + IO_BYTE _CNTE :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _CKS :2; + }bitc; + }PCNH10STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PTMR11STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PCSR11STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PDUT11STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _OSEL :1; + IO_WORD _OE :1; + IO_WORD _IRS0 :1; + IO_WORD _IRS1 :1; + IO_WORD _IRQF :1; + IO_WORD _IREN :1; + IO_WORD _EGS0 :1; + IO_WORD _EGS1 :1; + IO_WORD :1; + IO_WORD _PGMS :1; + IO_WORD _CKS0 :1; + IO_WORD _CKS1 :1; + IO_WORD _RTRG :1; + IO_WORD _MDSE :1; + IO_WORD _STGR :1; + IO_WORD _CNTE :1; + }bit; + struct{ + IO_WORD :2; + IO_WORD _IRS :2; + IO_WORD :2; + IO_WORD _EGS :2; + IO_WORD :2; + IO_WORD _CKS :2; + }bitc; + }PCN11STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OSEL :1; + IO_BYTE _OE :1; + IO_BYTE _IRS0 :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRQF :1; + IO_BYTE _IREN :1; + IO_BYTE _EGS0 :1; + IO_BYTE _EGS1 :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _IRS :2; + IO_BYTE :2; + IO_BYTE _EGS :2; + }bitc; + }PCNL11STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _PGMS :1; + IO_BYTE _CKS0 :1; + IO_BYTE _CKS1 :1; + IO_BYTE _RTRG :1; + IO_BYTE _MDSE :1; + IO_BYTE _STGR :1; + IO_BYTE _CNTE :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _CKS :2; + }bitc; + }PCNH11STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _TSEL00 :1; + IO_WORD _TSEL01 :1; + IO_WORD _TSEL02 :1; + IO_WORD _TSEL03 :1; + IO_WORD _TSEL10 :1; + IO_WORD _TSEL11 :1; + IO_WORD _TSEL12 :1; + IO_WORD _TSEL13 :1; + IO_WORD _TSEL20 :1; + IO_WORD _TSEL21 :1; + IO_WORD _TSEL22 :1; + IO_WORD _TSEL23 :1; + IO_WORD _TSEL30 :1; + IO_WORD _TSEL31 :1; + IO_WORD _TSEL32 :1; + IO_WORD _TSEL33 :1; + }bit; + struct{ + IO_WORD _TSEL0 :4; + IO_WORD _TSEL1 :4; + IO_WORD _TSEL2 :4; + IO_WORD _TSEL3 :4; + }bitc; + }GCN13STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TSEL00 :1; + IO_BYTE _TSEL01 :1; + IO_BYTE _TSEL02 :1; + IO_BYTE _TSEL03 :1; + IO_BYTE _TSEL10 :1; + IO_BYTE _TSEL11 :1; + IO_BYTE _TSEL12 :1; + IO_BYTE _TSEL13 :1; + }bit; + struct{ + IO_BYTE _TSEL0 :4; + IO_BYTE _TSEL1 :4; + }bitc; + }GCN1L3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TSEL20 :1; + IO_BYTE _TSEL21 :1; + IO_BYTE _TSEL22 :1; + IO_BYTE _TSEL23 :1; + IO_BYTE _TSEL30 :1; + IO_BYTE _TSEL31 :1; + IO_BYTE _TSEL32 :1; + IO_BYTE _TSEL33 :1; + }bit; + struct{ + IO_BYTE _TSEL2 :4; + IO_BYTE _TSEL3 :4; + }bitc; + }GCN1H3STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _EN0 :1; + IO_WORD _EN1 :1; + IO_WORD _EN2 :1; + IO_WORD _EN3 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CKSEL0 :1; + IO_WORD _CKSEL1 :1; + IO_WORD _CKSEL2 :1; + IO_WORD _CKSEL3 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD _EN :4; + IO_WORD :4; + IO_WORD _CKSEL :4; + }bitc; + }GCN23STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EN0 :1; + IO_BYTE _EN1 :1; + IO_BYTE _EN2 :1; + IO_BYTE _EN3 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _EN :4; + }bitc; + }GCN2L3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CKSEL0 :1; + IO_BYTE _CKSEL1 :1; + IO_BYTE _CKSEL2 :1; + IO_BYTE _CKSEL3 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _CKSEL :4; + }bitc; + }GCN2H3STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PTMR12STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PCSR12STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PDUT12STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _OSEL :1; + IO_WORD _OE :1; + IO_WORD _IRS0 :1; + IO_WORD _IRS1 :1; + IO_WORD _IRQF :1; + IO_WORD _IREN :1; + IO_WORD _EGS0 :1; + IO_WORD _EGS1 :1; + IO_WORD :1; + IO_WORD _PGMS :1; + IO_WORD _CKS0 :1; + IO_WORD _CKS1 :1; + IO_WORD _RTRG :1; + IO_WORD _MDSE :1; + IO_WORD _STGR :1; + IO_WORD _CNTE :1; + }bit; + struct{ + IO_WORD :2; + IO_WORD _IRS :2; + IO_WORD :2; + IO_WORD _EGS :2; + IO_WORD :2; + IO_WORD _CKS :2; + }bitc; + }PCN12STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OSEL :1; + IO_BYTE _OE :1; + IO_BYTE _IRS0 :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRQF :1; + IO_BYTE _IREN :1; + IO_BYTE _EGS0 :1; + IO_BYTE _EGS1 :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _IRS :2; + IO_BYTE :2; + IO_BYTE _EGS :2; + }bitc; + }PCNL12STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _PGMS :1; + IO_BYTE _CKS0 :1; + IO_BYTE _CKS1 :1; + IO_BYTE _RTRG :1; + IO_BYTE _MDSE :1; + IO_BYTE _STGR :1; + IO_BYTE _CNTE :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _CKS :2; + }bitc; + }PCNH12STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PTMR13STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PCSR13STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PDUT13STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _OSEL :1; + IO_WORD _OE :1; + IO_WORD _IRS0 :1; + IO_WORD _IRS1 :1; + IO_WORD _IRQF :1; + IO_WORD _IREN :1; + IO_WORD _EGS0 :1; + IO_WORD _EGS1 :1; + IO_WORD :1; + IO_WORD _PGMS :1; + IO_WORD _CKS0 :1; + IO_WORD _CKS1 :1; + IO_WORD _RTRG :1; + IO_WORD _MDSE :1; + IO_WORD _STGR :1; + IO_WORD _CNTE :1; + }bit; + struct{ + IO_WORD :2; + IO_WORD _IRS :2; + IO_WORD :2; + IO_WORD _EGS :2; + IO_WORD :2; + IO_WORD _CKS :2; + }bitc; + }PCN13STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OSEL :1; + IO_BYTE _OE :1; + IO_BYTE _IRS0 :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRQF :1; + IO_BYTE _IREN :1; + IO_BYTE _EGS0 :1; + IO_BYTE _EGS1 :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _IRS :2; + IO_BYTE :2; + IO_BYTE _EGS :2; + }bitc; + }PCNL13STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _PGMS :1; + IO_BYTE _CKS0 :1; + IO_BYTE _CKS1 :1; + IO_BYTE _RTRG :1; + IO_BYTE _MDSE :1; + IO_BYTE _STGR :1; + IO_BYTE _CNTE :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _CKS :2; + }bitc; + }PCNH13STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PTMR14STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PCSR14STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PDUT14STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _OSEL :1; + IO_WORD _OE :1; + IO_WORD _IRS0 :1; + IO_WORD _IRS1 :1; + IO_WORD _IRQF :1; + IO_WORD _IREN :1; + IO_WORD _EGS0 :1; + IO_WORD _EGS1 :1; + IO_WORD :1; + IO_WORD _PGMS :1; + IO_WORD _CKS0 :1; + IO_WORD _CKS1 :1; + IO_WORD _RTRG :1; + IO_WORD _MDSE :1; + IO_WORD _STGR :1; + IO_WORD _CNTE :1; + }bit; + struct{ + IO_WORD :2; + IO_WORD _IRS :2; + IO_WORD :2; + IO_WORD _EGS :2; + IO_WORD :2; + IO_WORD _CKS :2; + }bitc; + }PCN14STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OSEL :1; + IO_BYTE _OE :1; + IO_BYTE _IRS0 :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRQF :1; + IO_BYTE _IREN :1; + IO_BYTE _EGS0 :1; + IO_BYTE _EGS1 :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _IRS :2; + IO_BYTE :2; + IO_BYTE _EGS :2; + }bitc; + }PCNL14STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _PGMS :1; + IO_BYTE _CKS0 :1; + IO_BYTE _CKS1 :1; + IO_BYTE _RTRG :1; + IO_BYTE _MDSE :1; + IO_BYTE _STGR :1; + IO_BYTE _CNTE :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _CKS :2; + }bitc; + }PCNH14STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PTMR15STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PCSR15STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _D0 :1; + IO_WORD _D1 :1; + IO_WORD _D2 :1; + IO_WORD _D3 :1; + IO_WORD _D4 :1; + IO_WORD _D5 :1; + IO_WORD _D6 :1; + IO_WORD _D7 :1; + IO_WORD _D8 :1; + IO_WORD _D9 :1; + IO_WORD _D10 :1; + IO_WORD _D11 :1; + IO_WORD _D12 :1; + IO_WORD _D13 :1; + IO_WORD _D14 :1; + IO_WORD _D15 :1; + }bit; + struct{ + IO_WORD _D :16; + }bitc; + }PDUT15STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _OSEL :1; + IO_WORD _OE :1; + IO_WORD _IRS0 :1; + IO_WORD _IRS1 :1; + IO_WORD _IRQF :1; + IO_WORD _IREN :1; + IO_WORD _EGS0 :1; + IO_WORD _EGS1 :1; + IO_WORD :1; + IO_WORD _PGMS :1; + IO_WORD _CKS0 :1; + IO_WORD _CKS1 :1; + IO_WORD _RTRG :1; + IO_WORD _MDSE :1; + IO_WORD _STGR :1; + IO_WORD _CNTE :1; + }bit; + struct{ + IO_WORD :2; + IO_WORD _IRS :2; + IO_WORD :2; + IO_WORD _EGS :2; + IO_WORD :2; + IO_WORD _CKS :2; + }bitc; + }PCN15STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OSEL :1; + IO_BYTE _OE :1; + IO_BYTE _IRS0 :1; + IO_BYTE _IRS1 :1; + IO_BYTE _IRQF :1; + IO_BYTE _IREN :1; + IO_BYTE _EGS0 :1; + IO_BYTE _EGS1 :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _IRS :2; + IO_BYTE :2; + IO_BYTE _EGS :2; + }bitc; + }PCNL15STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE _PGMS :1; + IO_BYTE _CKS0 :1; + IO_BYTE _CKS1 :1; + IO_BYTE _RTRG :1; + IO_BYTE _MDSE :1; + IO_BYTE _STGR :1; + IO_BYTE _CNTE :1; + }bit; + struct{ + IO_BYTE :2; + IO_BYTE _CKS :2; + }bitc; + }PCNH15STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PPG8_R :1; + IO_BYTE _PPG9_R :1; + IO_BYTE _PPG10_R :1; + IO_BYTE _PPG11_R :1; + IO_BYTE _TTG8_R :1; + IO_BYTE _TTG9_R :1; + IO_BYTE _TTG10_R :1; + IO_BYTE _TTG11_R :1; + }bit; + }PRRR10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _PPG16_R :1; + IO_BYTE _PPG17_R :1; + IO_BYTE _PPG18_R :1; + IO_BYTE _PPG19_R :1; + IO_BYTE _TTG16_R :1; + IO_BYTE _TTG17_R :1; + IO_BYTE _TTG18_R :1; + IO_BYTE _TTG19_R :1; + }bit; + }PRRR11STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _CS0_R :1; + IO_BYTE _CS1_R :1; + IO_BYTE _CS2_R :1; + IO_BYTE _CS4_R :1; + IO_BYTE _CS5_R :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }PRRR12STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }PRRR13STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _R0 :1; + IO_WORD _R1 :1; + IO_WORD _R2 :1; + IO_WORD _ACE :1; + IO_WORD _STS :1; + IO_WORD _WSF :1; + IO_WORD _ES :1; + IO_WORD _BW :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CSE :1; + IO_WORD _CSL :1; + IO_WORD _ATL :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD _R :3; + }bitc; + }EAC0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _R0 :1; + IO_BYTE _R1 :1; + IO_BYTE _R2 :1; + IO_BYTE _ACE :1; + IO_BYTE _STS :1; + IO_BYTE _WSF :1; + IO_BYTE _ES :1; + IO_BYTE _BW :1; + }bit; + struct{ + IO_BYTE _R :3; + }bitc; + }EACL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CSE :1; + IO_BYTE _CSL :1; + IO_BYTE _ATL :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }EACH0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _R0 :1; + IO_WORD _R1 :1; + IO_WORD _R2 :1; + IO_WORD _ACE :1; + IO_WORD _STS :1; + IO_WORD _WSF :1; + IO_WORD _ES :1; + IO_WORD _BW :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _CSE :1; + IO_WORD _CSL :1; + IO_WORD _ATL :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD _R :3; + }bitc; + }EAC1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _R0 :1; + IO_BYTE _R1 :1; + IO_BYTE _R2 :1; + IO_BYTE _ACE :1; + IO_BYTE _STS :1; + IO_BYTE _WSF :1; + IO_BYTE _ES :1; + IO_BYTE _BW :1; + }bit; + struct{ + IO_BYTE _R :3; + }bitc; + }EACL1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _CSE :1; + IO_BYTE _CSL :1; + IO_BYTE _ATL :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }EACH1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _R0 :1; + IO_WORD _R1 :1; + IO_WORD _R2 :1; + IO_WORD _ACE :1; + IO_WORD _STS :1; + IO_WORD _WSF :1; + IO_WORD _ES :1; + IO_WORD _BW :1; + IO_WORD _EASZ0 :1; + IO_WORD _EASZ1 :1; + IO_WORD _EASZ2 :1; + IO_WORD _CSE :1; + IO_WORD _CSL :1; + IO_WORD _ATL :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD _R :3; + IO_WORD :5; + IO_WORD _EASZ :3; + }bitc; + }EAC2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _R0 :1; + IO_BYTE _R1 :1; + IO_BYTE _R2 :1; + IO_BYTE _ACE :1; + IO_BYTE _STS :1; + IO_BYTE _WSF :1; + IO_BYTE _ES :1; + IO_BYTE _BW :1; + }bit; + struct{ + IO_BYTE _R :3; + }bitc; + }EACL2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EASZ0 :1; + IO_BYTE _EASZ1 :1; + IO_BYTE _EASZ2 :1; + IO_BYTE _CSE :1; + IO_BYTE _CSL :1; + IO_BYTE _ATL :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _EASZ :3; + }bitc; + }EACH2STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _R0 :1; + IO_WORD _R1 :1; + IO_WORD _R2 :1; + IO_WORD _ACE :1; + IO_WORD _STS :1; + IO_WORD _WSF :1; + IO_WORD _ES :1; + IO_WORD _BW :1; + IO_WORD _EASZ0 :1; + IO_WORD _EASZ1 :1; + IO_WORD _EASZ2 :1; + IO_WORD _CSE :1; + IO_WORD _CSL :1; + IO_WORD _ATL :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD _R :3; + IO_WORD :5; + IO_WORD _EASZ :3; + }bitc; + }EAC3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _R0 :1; + IO_BYTE _R1 :1; + IO_BYTE _R2 :1; + IO_BYTE _ACE :1; + IO_BYTE _STS :1; + IO_BYTE _WSF :1; + IO_BYTE _ES :1; + IO_BYTE _BW :1; + }bit; + struct{ + IO_BYTE _R :3; + }bitc; + }EACL3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EASZ0 :1; + IO_BYTE _EASZ1 :1; + IO_BYTE _EASZ2 :1; + IO_BYTE _CSE :1; + IO_BYTE _CSL :1; + IO_BYTE _ATL :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _EASZ :3; + }bitc; + }EACH3STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _R0 :1; + IO_WORD _R1 :1; + IO_WORD _R2 :1; + IO_WORD _ACE :1; + IO_WORD _STS :1; + IO_WORD _WSF :1; + IO_WORD _ES :1; + IO_WORD _BW :1; + IO_WORD _EASZ0 :1; + IO_WORD _EASZ1 :1; + IO_WORD _EASZ2 :1; + IO_WORD _CSE :1; + IO_WORD _CSL :1; + IO_WORD _ATL :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD _R :3; + IO_WORD :5; + IO_WORD _EASZ :3; + }bitc; + }EAC4STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _R0 :1; + IO_BYTE _R1 :1; + IO_BYTE _R2 :1; + IO_BYTE _ACE :1; + IO_BYTE _STS :1; + IO_BYTE _WSF :1; + IO_BYTE _ES :1; + IO_BYTE _BW :1; + }bit; + struct{ + IO_BYTE _R :3; + }bitc; + }EACL4STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EASZ0 :1; + IO_BYTE _EASZ1 :1; + IO_BYTE _EASZ2 :1; + IO_BYTE _CSE :1; + IO_BYTE _CSL :1; + IO_BYTE _ATL :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _EASZ :3; + }bitc; + }EACH4STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _R0 :1; + IO_WORD _R1 :1; + IO_WORD _R2 :1; + IO_WORD _ACE :1; + IO_WORD _STS :1; + IO_WORD _WSF :1; + IO_WORD _ES :1; + IO_WORD _BW :1; + IO_WORD _EASZ0 :1; + IO_WORD _EASZ1 :1; + IO_WORD _EASZ2 :1; + IO_WORD _CSE :1; + IO_WORD _CSL :1; + IO_WORD _ATL :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD _R :3; + IO_WORD :5; + IO_WORD _EASZ :3; + }bitc; + }EAC5STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _R0 :1; + IO_BYTE _R1 :1; + IO_BYTE _R2 :1; + IO_BYTE _ACE :1; + IO_BYTE _STS :1; + IO_BYTE _WSF :1; + IO_BYTE _ES :1; + IO_BYTE _BW :1; + }bit; + struct{ + IO_BYTE _R :3; + }bitc; + }EACL5STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EASZ0 :1; + IO_BYTE _EASZ1 :1; + IO_BYTE _EASZ2 :1; + IO_BYTE _CSE :1; + IO_BYTE _CSL :1; + IO_BYTE _ATL :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _EASZ :3; + }bitc; + }EACH5STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _A0 :1; + IO_BYTE _A1 :1; + IO_BYTE _A2 :1; + IO_BYTE _A3 :1; + IO_BYTE _A4 :1; + IO_BYTE _A5 :1; + IO_BYTE _A6 :1; + IO_BYTE _A7 :1; + }bit; + struct{ + IO_BYTE _A :8; + }bitc; + }EAS2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _A0 :1; + IO_BYTE _A1 :1; + IO_BYTE _A2 :1; + IO_BYTE _A3 :1; + IO_BYTE _A4 :1; + IO_BYTE _A5 :1; + IO_BYTE _A6 :1; + IO_BYTE _A7 :1; + }bit; + struct{ + IO_BYTE _A :8; + }bitc; + }EAS3STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _A0 :1; + IO_BYTE _A1 :1; + IO_BYTE _A2 :1; + IO_BYTE _A3 :1; + IO_BYTE _A4 :1; + IO_BYTE _A5 :1; + IO_BYTE _A6 :1; + IO_BYTE _A7 :1; + }bit; + struct{ + IO_BYTE _A :8; + }bitc; + }EAS4STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _A0 :1; + IO_BYTE _A1 :1; + IO_BYTE _A2 :1; + IO_BYTE _A3 :1; + IO_BYTE _A4 :1; + IO_BYTE _A5 :1; + IO_BYTE _A6 :1; + IO_BYTE _A7 :1; + }bit; + }EAS5STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _EAE0 :1; + IO_BYTE _EAE1 :1; + IO_BYTE _EAE2 :1; + IO_BYTE _EAE3 :1; + IO_BYTE _EAE4 :1; + IO_BYTE _EAE5 :1; + IO_BYTE _ERE :1; + IO_BYTE _NMS :1; + }bit; + struct{ + IO_BYTE _EAE :6; + }bitc; + }EBMSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _DIV0 :1; + IO_BYTE _DIV1 :1; + IO_BYTE _DIV2 :1; + IO_BYTE _CSM :1; + IO_BYTE _CKI :1; + IO_BYTE _CKE :1; + IO_BYTE _RYE :1; + IO_BYTE _HDE :1; + }bit; + struct{ + IO_BYTE _DIV :3; + }bitc; + }EBCFSTR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _A00 :1; + IO_BYTE _A01 :1; + IO_BYTE _A02 :1; + IO_BYTE _A03 :1; + IO_BYTE _A04 :1; + IO_BYTE _A05 :1; + IO_BYTE _A06 :1; + IO_BYTE _A07 :1; + }bit; + }EBAE0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _A08 :1; + IO_BYTE _A09 :1; + IO_BYTE _A10 :1; + IO_BYTE _A11 :1; + IO_BYTE _A12 :1; + IO_BYTE _A13 :1; + IO_BYTE _A14 :1; + IO_BYTE _A15 :1; + }bit; + }EBAE1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _A16 :1; + IO_BYTE _A17 :1; + IO_BYTE _A18 :1; + IO_BYTE _A19 :1; + IO_BYTE _A20 :1; + IO_BYTE _A21 :1; + IO_BYTE _A22 :1; + IO_BYTE _A23 :1; + }bit; + }EBAE2STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _LBE :1; + IO_BYTE _UBE :1; + IO_BYTE _WRLE :1; + IO_BYTE _WRHE :1; + IO_BYTE _RDE :1; + IO_BYTE _ASE :1; + IO_BYTE _ASL :1; + IO_BYTE :1; + }bit; + }EBCSSTR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _INIT :1; + IO_WORD _IE :1; + IO_WORD _SIE :1; + IO_WORD _EIE :1; + IO_WORD :1; + IO_WORD _DAR :1; + IO_WORD _CCE :1; + IO_WORD _TEST :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }CTRLR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INIT :1; + IO_BYTE _IE :1; + IO_BYTE _SIE :1; + IO_BYTE _EIE :1; + IO_BYTE :1; + IO_BYTE _DAR :1; + IO_BYTE _CCE :1; + IO_BYTE _TEST :1; + }bit; + }CTRLRL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }CTRLRH0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _LEC0 :1; + IO_WORD _LEC1 :1; + IO_WORD _LEC2 :1; + IO_WORD _TXOK :1; + IO_WORD _RXOK :1; + IO_WORD _EPASS :1; + IO_WORD _EWARN :1; + IO_WORD _BOFF :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD _LEC :3; + }bitc; + }STATR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _LEC0 :1; + IO_BYTE _LEC1 :1; + IO_BYTE _LEC2 :1; + IO_BYTE _TXOK :1; + IO_BYTE _RXOK :1; + IO_BYTE _EPASS :1; + IO_BYTE _EWARN :1; + IO_BYTE _BOFF :1; + }bit; + struct{ + IO_BYTE _LEC :3; + }bitc; + }STATRL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }STATRH0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _TEC0 :1; + IO_WORD _TEC1 :1; + IO_WORD _TEC2 :1; + IO_WORD _TEC3 :1; + IO_WORD _TEC4 :1; + IO_WORD _TEC5 :1; + IO_WORD _TEC6 :1; + IO_WORD _TEC7 :1; + IO_WORD _REC0 :1; + IO_WORD _REC1 :1; + IO_WORD _REC2 :1; + IO_WORD _REC3 :1; + IO_WORD _REC4 :1; + IO_WORD _REC5 :1; + IO_WORD _REC6 :1; + IO_WORD _RP :1; + }bit; + struct{ + IO_WORD _TEC :8; + IO_WORD _REC :7; + }bitc; + }ERRCNT0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TEC0 :1; + IO_BYTE _TEC1 :1; + IO_BYTE _TEC2 :1; + IO_BYTE _TEC3 :1; + IO_BYTE _TEC4 :1; + IO_BYTE _TEC5 :1; + IO_BYTE _TEC6 :1; + IO_BYTE _TEC7 :1; + }bit; + struct{ + IO_BYTE _TEC :8; + }bitc; + }ERRCNTL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _REC0 :1; + IO_BYTE _REC1 :1; + IO_BYTE _REC2 :1; + IO_BYTE _REC3 :1; + IO_BYTE _REC4 :1; + IO_BYTE _REC5 :1; + IO_BYTE _REC6 :1; + IO_BYTE _RP :1; + }bit; + struct{ + IO_BYTE _REC :7; + }bitc; + }ERRCNTH0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _BRP0 :1; + IO_WORD _BRP1 :1; + IO_WORD _BRP2 :1; + IO_WORD _BRP3 :1; + IO_WORD _BRP4 :1; + IO_WORD _BRP5 :1; + IO_WORD _SJW0 :1; + IO_WORD _SJW1 :1; + IO_WORD _TSEG10 :1; + IO_WORD _TSEG11 :1; + IO_WORD _TSEG12 :1; + IO_WORD _TSEG13 :1; + IO_WORD _TSEG20 :1; + IO_WORD _TSEG21 :1; + IO_WORD _TSEG22 :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD _BRP :6; + IO_WORD _SJW :2; + IO_WORD _TSEG1 :4; + IO_WORD _TSEG2 :3; + }bitc; + }BTR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _BRP0 :1; + IO_BYTE _BRP1 :1; + IO_BYTE _BRP2 :1; + IO_BYTE _BRP3 :1; + IO_BYTE _BRP4 :1; + IO_BYTE _BRP5 :1; + IO_BYTE _SJW0 :1; + IO_BYTE _SJW1 :1; + }bit; + struct{ + IO_BYTE _BRP :6; + IO_BYTE _SJW :2; + }bitc; + }BTRL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TSEG10 :1; + IO_BYTE _TSEG11 :1; + IO_BYTE _TSEG12 :1; + IO_BYTE _TSEG13 :1; + IO_BYTE _TSEG20 :1; + IO_BYTE _TSEG21 :1; + IO_BYTE _TSEG22 :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _TSEG1 :4; + IO_BYTE _TSEG2 :3; + }bitc; + }BTRH0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _INTID0 :1; + IO_WORD _INTID1 :1; + IO_WORD _INTID2 :1; + IO_WORD _INTID3 :1; + IO_WORD _INTID4 :1; + IO_WORD _INTID5 :1; + IO_WORD _INTID6 :1; + IO_WORD _INTID7 :1; + IO_WORD _INTID8 :1; + IO_WORD _INTID9 :1; + IO_WORD _INTID10 :1; + IO_WORD _INTID11 :1; + IO_WORD _INTID12 :1; + IO_WORD _INTID13 :1; + IO_WORD _INTID14 :1; + IO_WORD _INTID15 :1; + }bit; + struct{ + IO_WORD _INTID :16; + }bitc; + }INTR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INTID0 :1; + IO_BYTE _INTID1 :1; + IO_BYTE _INTID2 :1; + IO_BYTE _INTID3 :1; + IO_BYTE _INTID4 :1; + IO_BYTE _INTID5 :1; + IO_BYTE _INTID6 :1; + IO_BYTE _INTID7 :1; + }bit; + }INTRL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INTID8 :1; + IO_BYTE _INTID9 :1; + IO_BYTE _INTID10 :1; + IO_BYTE _INTID11 :1; + IO_BYTE _INTID12 :1; + IO_BYTE _INTID13 :1; + IO_BYTE _INTID14 :1; + IO_BYTE _INTID15 :1; + }bit; + }INTRH0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD _BASIC :1; + IO_WORD _SILENT :1; + IO_WORD _LBACK :1; + IO_WORD _TX0 :1; + IO_WORD _TX1 :1; + IO_WORD _RX :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }TESTR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _BASIC :1; + IO_BYTE _SILENT :1; + IO_BYTE _LBACK :1; + IO_BYTE _TX0 :1; + IO_BYTE _TX1 :1; + IO_BYTE _RX :1; + }bit; + }TESTRL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }TESTRH0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _BRPE0 :1; + IO_WORD _BRPE1 :1; + IO_WORD _BRPE2 :1; + IO_WORD _BRPE3 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD _BRPE :4; + }bitc; + }BRPER0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _BRPE0 :1; + IO_BYTE _BRPE1 :1; + IO_BYTE _BRPE2 :1; + IO_BYTE _BRPE3 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _BRPE :4; + }bitc; + }BRPERL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }BRPERH0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _MSGN0 :1; + IO_WORD _MSGN1 :1; + IO_WORD _MSGN2 :1; + IO_WORD _MSGN3 :1; + IO_WORD _MSGN4 :1; + IO_WORD _MSGN5 :1; + IO_WORD _MSGN6 :1; + IO_WORD _MSGN7 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _BUSY :1; + }bit; + }IF1CREQ0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSGN0 :1; + IO_BYTE _MSGN1 :1; + IO_BYTE _MSGN2 :1; + IO_BYTE _MSGN3 :1; + IO_BYTE _MSGN4 :1; + IO_BYTE _MSGN5 :1; + IO_BYTE _MSGN6 :1; + IO_BYTE _MSGN7 :1; + }bit; + }IF1CREQL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _BUSY :1; + }bit; + }IF1CREQH0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _DATAB :1; + IO_WORD _DATAA :1; + IO_WORD _TXREQ :1; + IO_WORD _CIP :1; + IO_WORD _CONTROL :1; + IO_WORD _ARB :1; + IO_WORD _MASK :1; + IO_WORD _WRRD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF1CMSK0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _DATAB :1; + IO_BYTE _DATAA :1; + IO_BYTE _TXREQ :1; + IO_BYTE _CIP :1; + IO_BYTE _CONTROL :1; + IO_BYTE _ARB :1; + IO_BYTE _MASK :1; + IO_BYTE _WRRD :1; + }bit; + }IF1CMSKL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF1CMSKH0STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _MSK0 :1; + IO_LWORD _MSK1 :1; + IO_LWORD _MSK2 :1; + IO_LWORD _MSK3 :1; + IO_LWORD _MSK4 :1; + IO_LWORD _MSK5 :1; + IO_LWORD _MSK6 :1; + IO_LWORD _MSK7 :1; + IO_LWORD _MSK8 :1; + IO_LWORD _MSK9 :1; + IO_LWORD _MSK10 :1; + IO_LWORD _MSK11 :1; + IO_LWORD _MSK12 :1; + IO_LWORD _MSK13 :1; + IO_LWORD _MSK14 :1; + IO_LWORD _MSK15 :1; + IO_LWORD _MSK16 :1; + IO_LWORD _MSK17 :1; + IO_LWORD _MSK18 :1; + IO_LWORD _MSK19 :1; + IO_LWORD _MSK20 :1; + IO_LWORD _MSK21 :1; + IO_LWORD _MSK22 :1; + IO_LWORD _MSK23 :1; + IO_LWORD _MSK24 :1; + IO_LWORD _MSK25 :1; + IO_LWORD _MSK26 :1; + IO_LWORD _MSK27 :1; + IO_LWORD _MSK28 :1; + IO_LWORD :1; + IO_LWORD _MDIR :1; + IO_LWORD _MXTD :1; + }bit; + struct{ + IO_LWORD _MSK :29; + }bitc; + }IF1MSK0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _MSK0 :1; + IO_WORD _MSK1 :1; + IO_WORD _MSK2 :1; + IO_WORD _MSK3 :1; + IO_WORD _MSK4 :1; + IO_WORD _MSK5 :1; + IO_WORD _MSK6 :1; + IO_WORD _MSK7 :1; + IO_WORD _MSK8 :1; + IO_WORD _MSK9 :1; + IO_WORD _MSK10 :1; + IO_WORD _MSK11 :1; + IO_WORD _MSK12 :1; + IO_WORD _MSK13 :1; + IO_WORD _MSK14 :1; + IO_WORD _MSK15 :1; + }bit; + }IF1MSK10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSK0 :1; + IO_BYTE _MSK1 :1; + IO_BYTE _MSK2 :1; + IO_BYTE _MSK3 :1; + IO_BYTE _MSK4 :1; + IO_BYTE _MSK5 :1; + IO_BYTE _MSK6 :1; + IO_BYTE _MSK7 :1; + }bit; + }IF1MSK1L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSK8 :1; + IO_BYTE _MSK9 :1; + IO_BYTE _MSK10 :1; + IO_BYTE _MSK11 :1; + IO_BYTE _MSK12 :1; + IO_BYTE _MSK13 :1; + IO_BYTE _MSK14 :1; + IO_BYTE _MSK15 :1; + }bit; + }IF1MSK1H0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _MSK16 :1; + IO_WORD _MSK17 :1; + IO_WORD _MSK18 :1; + IO_WORD _MSK19 :1; + IO_WORD _MSK20 :1; + IO_WORD _MSK21 :1; + IO_WORD _MSK22 :1; + IO_WORD _MSK23 :1; + IO_WORD _MSK24 :1; + IO_WORD _MSK25 :1; + IO_WORD _MSK26 :1; + IO_WORD _MSK27 :1; + IO_WORD _MSK28 :1; + IO_WORD :1; + IO_WORD _MDIR :1; + IO_WORD _MXTD :1; + }bit; + }IF1MSK20STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSK16 :1; + IO_BYTE _MSK17 :1; + IO_BYTE _MSK18 :1; + IO_BYTE _MSK19 :1; + IO_BYTE _MSK20 :1; + IO_BYTE _MSK21 :1; + IO_BYTE _MSK22 :1; + IO_BYTE _MSK23 :1; + }bit; + }IF1MSK2L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSK24 :1; + IO_BYTE _MSK25 :1; + IO_BYTE _MSK26 :1; + IO_BYTE _MSK27 :1; + IO_BYTE _MSK28 :1; + IO_BYTE :1; + IO_BYTE _MDIR :1; + IO_BYTE _MXTD :1; + }bit; + }IF1MSK2H0STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _ID0 :1; + IO_LWORD _ID1 :1; + IO_LWORD _ID2 :1; + IO_LWORD _ID3 :1; + IO_LWORD _ID4 :1; + IO_LWORD _ID5 :1; + IO_LWORD _ID6 :1; + IO_LWORD _ID7 :1; + IO_LWORD _ID8 :1; + IO_LWORD _ID9 :1; + IO_LWORD _ID10 :1; + IO_LWORD _ID11 :1; + IO_LWORD _ID12 :1; + IO_LWORD _ID13 :1; + IO_LWORD _ID14 :1; + IO_LWORD _ID15 :1; + IO_LWORD _ID16 :1; + IO_LWORD _ID17 :1; + IO_LWORD _ID18 :1; + IO_LWORD _ID19 :1; + IO_LWORD _ID20 :1; + IO_LWORD _ID21 :1; + IO_LWORD _ID22 :1; + IO_LWORD _ID23 :1; + IO_LWORD _ID24 :1; + IO_LWORD _ID25 :1; + IO_LWORD _ID26 :1; + IO_LWORD _ID27 :1; + IO_LWORD _ID28 :1; + IO_LWORD _DIR :1; + IO_LWORD _XTD :1; + IO_LWORD _MSGVAL :1; + }bit; + struct{ + IO_LWORD _ID :29; + }bitc; + }IF1ARB0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _ID0 :1; + IO_WORD _ID1 :1; + IO_WORD _ID2 :1; + IO_WORD _ID3 :1; + IO_WORD _ID4 :1; + IO_WORD _ID5 :1; + IO_WORD _ID6 :1; + IO_WORD _ID7 :1; + IO_WORD _ID8 :1; + IO_WORD _ID9 :1; + IO_WORD _ID10 :1; + IO_WORD _ID11 :1; + IO_WORD _ID12 :1; + IO_WORD _ID13 :1; + IO_WORD _ID14 :1; + IO_WORD _ID15 :1; + }bit; + }IF1ARB10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ID0 :1; + IO_BYTE _ID1 :1; + IO_BYTE _ID2 :1; + IO_BYTE _ID3 :1; + IO_BYTE _ID4 :1; + IO_BYTE _ID5 :1; + IO_BYTE _ID6 :1; + IO_BYTE _ID7 :1; + }bit; + }IF1ARB1L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ID8 :1; + IO_BYTE _ID9 :1; + IO_BYTE _ID10 :1; + IO_BYTE _ID11 :1; + IO_BYTE _ID12 :1; + IO_BYTE _ID13 :1; + IO_BYTE _ID14 :1; + IO_BYTE _ID15 :1; + }bit; + }IF1ARB1H0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _ID16 :1; + IO_WORD _ID17 :1; + IO_WORD _ID18 :1; + IO_WORD _ID19 :1; + IO_WORD _ID20 :1; + IO_WORD _ID21 :1; + IO_WORD _ID22 :1; + IO_WORD _ID23 :1; + IO_WORD _ID24 :1; + IO_WORD _ID25 :1; + IO_WORD _ID26 :1; + IO_WORD _ID27 :1; + IO_WORD _ID28 :1; + IO_WORD _DIR :1; + IO_WORD _XTD :1; + IO_WORD _MSGVAL :1; + }bit; + }IF1ARB20STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ID16 :1; + IO_BYTE _ID17 :1; + IO_BYTE _ID18 :1; + IO_BYTE _ID19 :1; + IO_BYTE _ID20 :1; + IO_BYTE _ID21 :1; + IO_BYTE _ID22 :1; + IO_BYTE _ID23 :1; + }bit; + }IF1ARB2L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ID24 :1; + IO_BYTE _ID25 :1; + IO_BYTE _ID26 :1; + IO_BYTE _ID27 :1; + IO_BYTE _ID28 :1; + IO_BYTE _DIR :1; + IO_BYTE _XTD :1; + IO_BYTE _MSGVAL :1; + }bit; + }IF1ARB2H0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _DLC0 :1; + IO_WORD _DLC1 :1; + IO_WORD _DLC2 :1; + IO_WORD _DLC3 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _EOB :1; + IO_WORD _TXRQST :1; + IO_WORD _RMTEN :1; + IO_WORD _RXIE :1; + IO_WORD _TXIE :1; + IO_WORD _UMASK :1; + IO_WORD _INTPND :1; + IO_WORD _MSGLST :1; + IO_WORD _NEWDAT :1; + }bit; + struct{ + IO_WORD _DLC :4; + }bitc; + }IF1MCTR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _DLC0 :1; + IO_BYTE _DLC1 :1; + IO_BYTE _DLC2 :1; + IO_BYTE _DLC3 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _EOB :1; + }bit; + struct{ + IO_BYTE _DLC :4; + }bitc; + }IF1MCTRL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TXRQST :1; + IO_BYTE _RMTEN :1; + IO_BYTE _RXIE :1; + IO_BYTE _TXIE :1; + IO_BYTE _UMASK :1; + IO_BYTE _INTPND :1; + IO_BYTE _MSGLST :1; + IO_BYTE _NEWDAT :1; + }bit; + }IF1MCTRH0STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + }bit; + }IF1DTA0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF1DTA10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF1DTA1L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF1DTA1H0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF1DTA20STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF1DTA2L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF1DTA2H0STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + }bit; + }IF1DTB0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF1DTB10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF1DTB1L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF1DTB1H0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF1DTB20STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF1DTB2L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF1DTB2H0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _MSGN0 :1; + IO_WORD _MSGN1 :1; + IO_WORD _MSGN2 :1; + IO_WORD _MSGN3 :1; + IO_WORD _MSGN4 :1; + IO_WORD _MSGN5 :1; + IO_WORD _MSGN6 :1; + IO_WORD _MSGN7 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _BUSY :1; + }bit; + }IF2CREQ0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSGN0 :1; + IO_BYTE _MSGN1 :1; + IO_BYTE _MSGN2 :1; + IO_BYTE _MSGN3 :1; + IO_BYTE _MSGN4 :1; + IO_BYTE _MSGN5 :1; + IO_BYTE _MSGN6 :1; + IO_BYTE _MSGN7 :1; + }bit; + }IF2CREQL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _BUSY :1; + }bit; + }IF2CREQH0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _DATAB :1; + IO_WORD _DATAA :1; + IO_WORD _TXREQ :1; + IO_WORD _CIP :1; + IO_WORD _CONTROL :1; + IO_WORD _ARB :1; + IO_WORD _MASK :1; + IO_WORD _WRRD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF2CMSK0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _DATAB :1; + IO_BYTE _DATAA :1; + IO_BYTE _TXREQ :1; + IO_BYTE _CIP :1; + IO_BYTE _CONTROL :1; + IO_BYTE _ARB :1; + IO_BYTE _MASK :1; + IO_BYTE _WRRD :1; + }bit; + }IF2CMSKL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF2CMSKH0STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _MSK0 :1; + IO_LWORD _MSK1 :1; + IO_LWORD _MSK2 :1; + IO_LWORD _MSK3 :1; + IO_LWORD _MSK4 :1; + IO_LWORD _MSK5 :1; + IO_LWORD _MSK6 :1; + IO_LWORD _MSK7 :1; + IO_LWORD _MSK8 :1; + IO_LWORD _MSK9 :1; + IO_LWORD _MSK10 :1; + IO_LWORD _MSK11 :1; + IO_LWORD _MSK12 :1; + IO_LWORD _MSK13 :1; + IO_LWORD _MSK14 :1; + IO_LWORD _MSK15 :1; + IO_LWORD _MSK16 :1; + IO_LWORD _MSK17 :1; + IO_LWORD _MSK18 :1; + IO_LWORD _MSK19 :1; + IO_LWORD _MSK20 :1; + IO_LWORD _MSK21 :1; + IO_LWORD _MSK22 :1; + IO_LWORD _MSK23 :1; + IO_LWORD _MSK24 :1; + IO_LWORD _MSK25 :1; + IO_LWORD _MSK26 :1; + IO_LWORD _MSK27 :1; + IO_LWORD _MSK28 :1; + IO_LWORD :1; + IO_LWORD _MDIR :1; + IO_LWORD _MXTD :1; + }bit; + struct{ + IO_LWORD _MSK :29; + }bitc; + }IF2MSK0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _MSK0 :1; + IO_WORD _MSK1 :1; + IO_WORD _MSK2 :1; + IO_WORD _MSK3 :1; + IO_WORD _MSK4 :1; + IO_WORD _MSK5 :1; + IO_WORD _MSK6 :1; + IO_WORD _MSK7 :1; + IO_WORD _MSK8 :1; + IO_WORD _MSK9 :1; + IO_WORD _MSK10 :1; + IO_WORD _MSK11 :1; + IO_WORD _MSK12 :1; + IO_WORD _MSK13 :1; + IO_WORD _MSK14 :1; + IO_WORD _MSK15 :1; + }bit; + }IF2MSK10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSK0 :1; + IO_BYTE _MSK1 :1; + IO_BYTE _MSK2 :1; + IO_BYTE _MSK3 :1; + IO_BYTE _MSK4 :1; + IO_BYTE _MSK5 :1; + IO_BYTE _MSK6 :1; + IO_BYTE _MSK7 :1; + }bit; + }IF2MSK1L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSK8 :1; + IO_BYTE _MSK9 :1; + IO_BYTE _MSK10 :1; + IO_BYTE _MSK11 :1; + IO_BYTE _MSK12 :1; + IO_BYTE _MSK13 :1; + IO_BYTE _MSK14 :1; + IO_BYTE _MSK15 :1; + }bit; + }IF2MSK1H0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _MSK16 :1; + IO_WORD _MSK17 :1; + IO_WORD _MSK18 :1; + IO_WORD _MSK19 :1; + IO_WORD _MSK20 :1; + IO_WORD _MSK21 :1; + IO_WORD _MSK22 :1; + IO_WORD _MSK23 :1; + IO_WORD _MSK24 :1; + IO_WORD _MSK25 :1; + IO_WORD _MSK26 :1; + IO_WORD _MSK27 :1; + IO_WORD _MSK28 :1; + IO_WORD :1; + IO_WORD _MDIR :1; + IO_WORD _MXTD :1; + }bit; + }IF2MSK20STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSK16 :1; + IO_BYTE _MSK17 :1; + IO_BYTE _MSK18 :1; + IO_BYTE _MSK19 :1; + IO_BYTE _MSK20 :1; + IO_BYTE _MSK21 :1; + IO_BYTE _MSK22 :1; + IO_BYTE _MSK23 :1; + }bit; + }IF2MSK2L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSK24 :1; + IO_BYTE _MSK25 :1; + IO_BYTE _MSK26 :1; + IO_BYTE _MSK27 :1; + IO_BYTE _MSK28 :1; + IO_BYTE :1; + IO_BYTE _MDIR :1; + IO_BYTE _MXTD :1; + }bit; + }IF2MSK2H0STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _ID0 :1; + IO_LWORD _ID1 :1; + IO_LWORD _ID2 :1; + IO_LWORD _ID3 :1; + IO_LWORD _ID4 :1; + IO_LWORD _ID5 :1; + IO_LWORD _ID6 :1; + IO_LWORD _ID7 :1; + IO_LWORD _ID8 :1; + IO_LWORD _ID9 :1; + IO_LWORD _ID10 :1; + IO_LWORD _ID11 :1; + IO_LWORD _ID12 :1; + IO_LWORD _ID13 :1; + IO_LWORD _ID14 :1; + IO_LWORD _ID15 :1; + IO_LWORD _ID16 :1; + IO_LWORD _ID17 :1; + IO_LWORD _ID18 :1; + IO_LWORD _ID19 :1; + IO_LWORD _ID20 :1; + IO_LWORD _ID21 :1; + IO_LWORD _ID22 :1; + IO_LWORD _ID23 :1; + IO_LWORD _ID24 :1; + IO_LWORD _ID25 :1; + IO_LWORD _ID26 :1; + IO_LWORD _ID27 :1; + IO_LWORD _ID28 :1; + IO_LWORD _DIR :1; + IO_LWORD _XTD :1; + IO_LWORD _MSGVAL :1; + }bit; + struct{ + IO_LWORD _ID :29; + }bitc; + }IF2ARB0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _ID0 :1; + IO_WORD _ID1 :1; + IO_WORD _ID2 :1; + IO_WORD _ID3 :1; + IO_WORD _ID4 :1; + IO_WORD _ID5 :1; + IO_WORD _ID6 :1; + IO_WORD _ID7 :1; + IO_WORD _ID8 :1; + IO_WORD _ID9 :1; + IO_WORD _ID10 :1; + IO_WORD _ID11 :1; + IO_WORD _ID12 :1; + IO_WORD _ID13 :1; + IO_WORD _ID14 :1; + IO_WORD _ID15 :1; + }bit; + }IF2ARB10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ID0 :1; + IO_BYTE _ID1 :1; + IO_BYTE _ID2 :1; + IO_BYTE _ID3 :1; + IO_BYTE _ID4 :1; + IO_BYTE _ID5 :1; + IO_BYTE _ID6 :1; + IO_BYTE _ID7 :1; + }bit; + }IF2ARB1L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ID8 :1; + IO_BYTE _ID9 :1; + IO_BYTE _ID10 :1; + IO_BYTE _ID11 :1; + IO_BYTE _ID12 :1; + IO_BYTE _ID13 :1; + IO_BYTE _ID14 :1; + IO_BYTE _ID15 :1; + }bit; + }IF2ARB1H0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _ID16 :1; + IO_WORD _ID17 :1; + IO_WORD _ID18 :1; + IO_WORD _ID19 :1; + IO_WORD _ID20 :1; + IO_WORD _ID21 :1; + IO_WORD _ID22 :1; + IO_WORD _ID23 :1; + IO_WORD _ID24 :1; + IO_WORD _ID25 :1; + IO_WORD _ID26 :1; + IO_WORD _ID27 :1; + IO_WORD _ID28 :1; + IO_WORD _DIR :1; + IO_WORD _XTD :1; + IO_WORD _MSGVAL :1; + }bit; + }IF2ARB20STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ID16 :1; + IO_BYTE _ID17 :1; + IO_BYTE _ID18 :1; + IO_BYTE _ID19 :1; + IO_BYTE _ID20 :1; + IO_BYTE _ID21 :1; + IO_BYTE _ID22 :1; + IO_BYTE _ID23 :1; + }bit; + }IF2ARB2L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ID24 :1; + IO_BYTE _ID25 :1; + IO_BYTE _ID26 :1; + IO_BYTE _ID27 :1; + IO_BYTE _ID28 :1; + IO_BYTE _DIR :1; + IO_BYTE _XTD :1; + IO_BYTE _MSGVAL :1; + }bit; + }IF2ARB2H0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _DLC0 :1; + IO_WORD _DLC1 :1; + IO_WORD _DLC2 :1; + IO_WORD _DLC3 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _EOB :1; + IO_WORD _TXRQST :1; + IO_WORD _RMTEN :1; + IO_WORD _RXIE :1; + IO_WORD _TXIE :1; + IO_WORD _UMASK :1; + IO_WORD _INTPND :1; + IO_WORD _MSGLST :1; + IO_WORD _NEWDAT :1; + }bit; + struct{ + IO_WORD _DLC :4; + }bitc; + }IF2MCTR0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _DLC0 :1; + IO_BYTE _DLC1 :1; + IO_BYTE _DLC2 :1; + IO_BYTE _DLC3 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _EOB :1; + }bit; + struct{ + IO_BYTE _DLC :4; + }bitc; + }IF2MCTRL0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TXRQST :1; + IO_BYTE _RMTEN :1; + IO_BYTE _RXIE :1; + IO_BYTE _TXIE :1; + IO_BYTE _UMASK :1; + IO_BYTE _INTPND :1; + IO_BYTE _MSGLST :1; + IO_BYTE _NEWDAT :1; + }bit; + }IF2MCTRH0STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + }bit; + }IF2DTA0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF2DTA10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF2DTA1L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF2DTA1H0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF2DTA20STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF2DTA2L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF2DTA2H0STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + }bit; + }IF2DTB0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF2DTB10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF2DTB1L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF2DTB1H0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF2DTB20STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF2DTB2L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF2DTB2H0STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _TXRQST1 :1; + IO_LWORD _TXRQST2 :1; + IO_LWORD _TXRQST3 :1; + IO_LWORD _TXRQST4 :1; + IO_LWORD _TXRQST5 :1; + IO_LWORD _TXRQST6 :1; + IO_LWORD _TXRQST7 :1; + IO_LWORD _TXRQST8 :1; + IO_LWORD _TXRQST9 :1; + IO_LWORD _TXRQST10 :1; + IO_LWORD _TXRQST11 :1; + IO_LWORD _TXRQST12 :1; + IO_LWORD _TXRQST13 :1; + IO_LWORD _TXRQST14 :1; + IO_LWORD _TXRQST15 :1; + IO_LWORD _TXRQST16 :1; + IO_LWORD _TXRQST17 :1; + IO_LWORD _TXRQST18 :1; + IO_LWORD _TXRQST19 :1; + IO_LWORD _TXRQST20 :1; + IO_LWORD _TXRQST21 :1; + IO_LWORD _TXRQST22 :1; + IO_LWORD _TXRQST23 :1; + IO_LWORD _TXRQST24 :1; + IO_LWORD _TXRQST25 :1; + IO_LWORD _TXRQST26 :1; + IO_LWORD _TXRQST27 :1; + IO_LWORD _TXRQST28 :1; + IO_LWORD _TXRQST29 :1; + IO_LWORD _TXRQST30 :1; + IO_LWORD _TXRQST31 :1; + IO_LWORD _TXRQST32 :1; + }bit; + struct{ + IO_LWORD _TXRQST :32; + }bitc; + }TREQR0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _TXRQST1 :1; + IO_WORD _TXRQST2 :1; + IO_WORD _TXRQST3 :1; + IO_WORD _TXRQST4 :1; + IO_WORD _TXRQST5 :1; + IO_WORD _TXRQST6 :1; + IO_WORD _TXRQST7 :1; + IO_WORD _TXRQST8 :1; + IO_WORD _TXRQST9 :1; + IO_WORD _TXRQST10 :1; + IO_WORD _TXRQST11 :1; + IO_WORD _TXRQST12 :1; + IO_WORD _TXRQST13 :1; + IO_WORD _TXRQST14 :1; + IO_WORD _TXRQST15 :1; + IO_WORD _TXRQST16 :1; + }bit; + }TREQR10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TXRQST1 :1; + IO_BYTE _TXRQST2 :1; + IO_BYTE _TXRQST3 :1; + IO_BYTE _TXRQST4 :1; + IO_BYTE _TXRQST5 :1; + IO_BYTE _TXRQST6 :1; + IO_BYTE _TXRQST7 :1; + IO_BYTE _TXRQST8 :1; + }bit; + }TREQR1L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TXRQST9 :1; + IO_BYTE _TXRQST10 :1; + IO_BYTE _TXRQST11 :1; + IO_BYTE _TXRQST12 :1; + IO_BYTE _TXRQST13 :1; + IO_BYTE _TXRQST14 :1; + IO_BYTE _TXRQST15 :1; + IO_BYTE _TXRQST16 :1; + }bit; + }TREQR1H0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _TXRQST17 :1; + IO_WORD _TXRQST18 :1; + IO_WORD _TXRQST19 :1; + IO_WORD _TXRQST20 :1; + IO_WORD _TXRQST21 :1; + IO_WORD _TXRQST22 :1; + IO_WORD _TXRQST23 :1; + IO_WORD _TXRQST24 :1; + IO_WORD _TXRQST25 :1; + IO_WORD _TXRQST26 :1; + IO_WORD _TXRQST27 :1; + IO_WORD _TXRQST28 :1; + IO_WORD _TXRQST29 :1; + IO_WORD _TXRQST30 :1; + IO_WORD _TXRQST31 :1; + IO_WORD _TXRQST32 :1; + }bit; + }TREQR20STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TXRQST17 :1; + IO_BYTE _TXRQST18 :1; + IO_BYTE _TXRQST19 :1; + IO_BYTE _TXRQST20 :1; + IO_BYTE _TXRQST21 :1; + IO_BYTE _TXRQST22 :1; + IO_BYTE _TXRQST23 :1; + IO_BYTE _TXRQST24 :1; + }bit; + }TREQR2L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TXRQST25 :1; + IO_BYTE _TXRQST26 :1; + IO_BYTE _TXRQST27 :1; + IO_BYTE _TXRQST28 :1; + IO_BYTE _TXRQST29 :1; + IO_BYTE _TXRQST30 :1; + IO_BYTE _TXRQST31 :1; + IO_BYTE _TXRQST32 :1; + }bit; + }TREQR2H0STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _NEWDAT1 :1; + IO_LWORD _NEWDAT2 :1; + IO_LWORD _NEWDAT3 :1; + IO_LWORD _NEWDAT4 :1; + IO_LWORD _NEWDAT5 :1; + IO_LWORD _NEWDAT6 :1; + IO_LWORD _NEWDAT7 :1; + IO_LWORD _NEWDAT8 :1; + IO_LWORD _NEWDAT9 :1; + IO_LWORD _NEWDAT10 :1; + IO_LWORD _NEWDAT11 :1; + IO_LWORD _NEWDAT12 :1; + IO_LWORD _NEWDAT13 :1; + IO_LWORD _NEWDAT14 :1; + IO_LWORD _NEWDAT15 :1; + IO_LWORD _NEWDAT16 :1; + IO_LWORD _NEWDAT17 :1; + IO_LWORD _NEWDAT18 :1; + IO_LWORD _NEWDAT19 :1; + IO_LWORD _NEWDAT20 :1; + IO_LWORD _NEWDAT21 :1; + IO_LWORD _NEWDAT22 :1; + IO_LWORD _NEWDAT23 :1; + IO_LWORD _NEWDAT24 :1; + IO_LWORD _NEWDAT25 :1; + IO_LWORD _NEWDAT26 :1; + IO_LWORD _NEWDAT27 :1; + IO_LWORD _NEWDAT28 :1; + IO_LWORD _NEWDAT29 :1; + IO_LWORD _NEWDAT30 :1; + IO_LWORD _NEWDAT31 :1; + IO_LWORD _NEWDAT32 :1; + }bit; + struct{ + IO_LWORD _NEWDAT :32; + }bitc; + }NEWDT0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _NEWDAT1 :1; + IO_WORD _NEWDAT2 :1; + IO_WORD _NEWDAT3 :1; + IO_WORD _NEWDAT4 :1; + IO_WORD _NEWDAT5 :1; + IO_WORD _NEWDAT6 :1; + IO_WORD _NEWDAT7 :1; + IO_WORD _NEWDAT8 :1; + IO_WORD _NEWDAT9 :1; + IO_WORD _NEWDAT10 :1; + IO_WORD _NEWDAT11 :1; + IO_WORD _NEWDAT12 :1; + IO_WORD _NEWDAT13 :1; + IO_WORD _NEWDAT14 :1; + IO_WORD _NEWDAT15 :1; + IO_WORD _NEWDAT16 :1; + }bit; + }NEWDT10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _NEWDAT1 :1; + IO_BYTE _NEWDAT2 :1; + IO_BYTE _NEWDAT3 :1; + IO_BYTE _NEWDAT4 :1; + IO_BYTE _NEWDAT5 :1; + IO_BYTE _NEWDAT6 :1; + IO_BYTE _NEWDAT7 :1; + IO_BYTE _NEWDAT8 :1; + }bit; + }NEWDT1L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _NEWDAT9 :1; + IO_BYTE _NEWDAT10 :1; + IO_BYTE _NEWDAT11 :1; + IO_BYTE _NEWDAT12 :1; + IO_BYTE _NEWDAT13 :1; + IO_BYTE _NEWDAT14 :1; + IO_BYTE _NEWDAT15 :1; + IO_BYTE _NEWDAT16 :1; + }bit; + }NEWDT1H0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _NEWDAT17 :1; + IO_WORD _NEWDAT18 :1; + IO_WORD _NEWDAT19 :1; + IO_WORD _NEWDAT20 :1; + IO_WORD _NEWDAT21 :1; + IO_WORD _NEWDAT22 :1; + IO_WORD _NEWDAT23 :1; + IO_WORD _NEWDAT24 :1; + IO_WORD _NEWDAT25 :1; + IO_WORD _NEWDAT26 :1; + IO_WORD _NEWDAT27 :1; + IO_WORD _NEWDAT28 :1; + IO_WORD _NEWDAT29 :1; + IO_WORD _NEWDAT30 :1; + IO_WORD _NEWDAT31 :1; + IO_WORD _NEWDAT32 :1; + }bit; + }NEWDT20STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _NEWDAT17 :1; + IO_BYTE _NEWDAT18 :1; + IO_BYTE _NEWDAT19 :1; + IO_BYTE _NEWDAT20 :1; + IO_BYTE _NEWDAT21 :1; + IO_BYTE _NEWDAT22 :1; + IO_BYTE _NEWDAT23 :1; + IO_BYTE _NEWDAT24 :1; + }bit; + }NEWDT2L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _NEWDAT25 :1; + IO_BYTE _NEWDAT26 :1; + IO_BYTE _NEWDAT27 :1; + IO_BYTE _NEWDAT28 :1; + IO_BYTE _NEWDAT29 :1; + IO_BYTE _NEWDAT30 :1; + IO_BYTE _NEWDAT31 :1; + IO_BYTE _NEWDAT32 :1; + }bit; + }NEWDT2H0STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _INTPND1 :1; + IO_LWORD _INTPND2 :1; + IO_LWORD _INTPND3 :1; + IO_LWORD _INTPND4 :1; + IO_LWORD _INTPND5 :1; + IO_LWORD _INTPND6 :1; + IO_LWORD _INTPND7 :1; + IO_LWORD _INTPND8 :1; + IO_LWORD _INTPND9 :1; + IO_LWORD _INTPND10 :1; + IO_LWORD _INTPND11 :1; + IO_LWORD _INTPND12 :1; + IO_LWORD _INTPND13 :1; + IO_LWORD _INTPND14 :1; + IO_LWORD _INTPND15 :1; + IO_LWORD _INTPND16 :1; + IO_LWORD _INTPND17 :1; + IO_LWORD _INTPND18 :1; + IO_LWORD _INTPND19 :1; + IO_LWORD _INTPND20 :1; + IO_LWORD _INTPND21 :1; + IO_LWORD _INTPND22 :1; + IO_LWORD _INTPND23 :1; + IO_LWORD _INTPND24 :1; + IO_LWORD _INTPND25 :1; + IO_LWORD _INTPND26 :1; + IO_LWORD _INTPND27 :1; + IO_LWORD _INTPND28 :1; + IO_LWORD _INTPND29 :1; + IO_LWORD _INTPND30 :1; + IO_LWORD _INTPND31 :1; + IO_LWORD _INTPND32 :1; + }bit; + struct{ + IO_LWORD _INTPND :32; + }bitc; + }INTPND0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _INTPND1 :1; + IO_WORD _INTPND2 :1; + IO_WORD _INTPND3 :1; + IO_WORD _INTPND4 :1; + IO_WORD _INTPND5 :1; + IO_WORD _INTPND6 :1; + IO_WORD _INTPND7 :1; + IO_WORD _INTPND8 :1; + IO_WORD _INTPND9 :1; + IO_WORD _INTPND10 :1; + IO_WORD _INTPND11 :1; + IO_WORD _INTPND12 :1; + IO_WORD _INTPND13 :1; + IO_WORD _INTPND14 :1; + IO_WORD _INTPND15 :1; + IO_WORD _INTPND16 :1; + }bit; + }INTPND10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INTPND1 :1; + IO_BYTE _INTPND2 :1; + IO_BYTE _INTPND3 :1; + IO_BYTE _INTPND4 :1; + IO_BYTE _INTPND5 :1; + IO_BYTE _INTPND6 :1; + IO_BYTE _INTPND7 :1; + IO_BYTE _INTPND8 :1; + }bit; + }INTPND1L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INTPND9 :1; + IO_BYTE _INTPND10 :1; + IO_BYTE _INTPND11 :1; + IO_BYTE _INTPND12 :1; + IO_BYTE _INTPND13 :1; + IO_BYTE _INTPND14 :1; + IO_BYTE _INTPND15 :1; + IO_BYTE _INTPND16 :1; + }bit; + }INTPND1H0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _INTPND17 :1; + IO_WORD _INTPND18 :1; + IO_WORD _INTPND19 :1; + IO_WORD _INTPND20 :1; + IO_WORD _INTPND21 :1; + IO_WORD _INTPND22 :1; + IO_WORD _INTPND23 :1; + IO_WORD _INTPND24 :1; + IO_WORD _INTPND25 :1; + IO_WORD _INTPND26 :1; + IO_WORD _INTPND27 :1; + IO_WORD _INTPND28 :1; + IO_WORD _INTPND29 :1; + IO_WORD _INTPND30 :1; + IO_WORD _INTPND31 :1; + IO_WORD _INTPND32 :1; + }bit; + }INTPND20STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INTPND17 :1; + IO_BYTE _INTPND18 :1; + IO_BYTE _INTPND19 :1; + IO_BYTE _INTPND20 :1; + IO_BYTE _INTPND21 :1; + IO_BYTE _INTPND22 :1; + IO_BYTE _INTPND23 :1; + IO_BYTE _INTPND24 :1; + }bit; + }INTPND2L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INTPND25 :1; + IO_BYTE _INTPND26 :1; + IO_BYTE _INTPND27 :1; + IO_BYTE _INTPND28 :1; + IO_BYTE _INTPND29 :1; + IO_BYTE _INTPND30 :1; + IO_BYTE _INTPND31 :1; + IO_BYTE _INTPND32 :1; + }bit; + }INTPND2H0STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _MSGVAL1 :1; + IO_LWORD _MSGVAL2 :1; + IO_LWORD _MSGVAL3 :1; + IO_LWORD _MSGVAL4 :1; + IO_LWORD _MSGVAL5 :1; + IO_LWORD _MSGVAL6 :1; + IO_LWORD _MSGVAL7 :1; + IO_LWORD _MSGVAL8 :1; + IO_LWORD _MSGVAL9 :1; + IO_LWORD _MSGVAL10 :1; + IO_LWORD _MSGVAL11 :1; + IO_LWORD _MSGVAL12 :1; + IO_LWORD _MSGVAL13 :1; + IO_LWORD _MSGVAL14 :1; + IO_LWORD _MSGVAL15 :1; + IO_LWORD _MSGVAL16 :1; + IO_LWORD _MSGVAL17 :1; + IO_LWORD _MSGVAL18 :1; + IO_LWORD _MSGVAL19 :1; + IO_LWORD _MSGVAL20 :1; + IO_LWORD _MSGVAL21 :1; + IO_LWORD _MSGVAL22 :1; + IO_LWORD _MSGVAL23 :1; + IO_LWORD _MSGVAL24 :1; + IO_LWORD _MSGVAL25 :1; + IO_LWORD _MSGVAL26 :1; + IO_LWORD _MSGVAL27 :1; + IO_LWORD _MSGVAL28 :1; + IO_LWORD _MSGVAL29 :1; + IO_LWORD _MSGVAL30 :1; + IO_LWORD _MSGVAL31 :1; + IO_LWORD _MSGVAL32 :1; + }bit; + struct{ + IO_LWORD _MSGVAL :32; + }bitc; + }MSGVAL0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _MSGVAL1 :1; + IO_WORD _MSGVAL2 :1; + IO_WORD _MSGVAL3 :1; + IO_WORD _MSGVAL4 :1; + IO_WORD _MSGVAL5 :1; + IO_WORD _MSGVAL6 :1; + IO_WORD _MSGVAL7 :1; + IO_WORD _MSGVAL8 :1; + IO_WORD _MSGVAL9 :1; + IO_WORD _MSGVAL10 :1; + IO_WORD _MSGVAL11 :1; + IO_WORD _MSGVAL12 :1; + IO_WORD _MSGVAL13 :1; + IO_WORD _MSGVAL14 :1; + IO_WORD _MSGVAL15 :1; + IO_WORD _MSGVAL16 :1; + }bit; + }MSGVAL10STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSGVAL1 :1; + IO_BYTE _MSGVAL2 :1; + IO_BYTE _MSGVAL3 :1; + IO_BYTE _MSGVAL4 :1; + IO_BYTE _MSGVAL5 :1; + IO_BYTE _MSGVAL6 :1; + IO_BYTE _MSGVAL7 :1; + IO_BYTE _MSGVAL8 :1; + }bit; + }MSGVAL1L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSGVAL9 :1; + IO_BYTE _MSGVAL10 :1; + IO_BYTE _MSGVAL11 :1; + IO_BYTE _MSGVAL12 :1; + IO_BYTE _MSGVAL13 :1; + IO_BYTE _MSGVAL14 :1; + IO_BYTE _MSGVAL15 :1; + IO_BYTE _MSGVAL16 :1; + }bit; + }MSGVAL1H0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _MSGVAL17 :1; + IO_WORD _MSGVAL18 :1; + IO_WORD _MSGVAL19 :1; + IO_WORD _MSGVAL20 :1; + IO_WORD _MSGVAL21 :1; + IO_WORD _MSGVAL22 :1; + IO_WORD _MSGVAL23 :1; + IO_WORD _MSGVAL24 :1; + IO_WORD _MSGVAL25 :1; + IO_WORD _MSGVAL26 :1; + IO_WORD _MSGVAL27 :1; + IO_WORD _MSGVAL28 :1; + IO_WORD _MSGVAL29 :1; + IO_WORD _MSGVAL30 :1; + IO_WORD _MSGVAL31 :1; + IO_WORD _MSGVAL32 :1; + }bit; + }MSGVAL20STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSGVAL17 :1; + IO_BYTE _MSGVAL18 :1; + IO_BYTE _MSGVAL19 :1; + IO_BYTE _MSGVAL20 :1; + IO_BYTE _MSGVAL21 :1; + IO_BYTE _MSGVAL22 :1; + IO_BYTE _MSGVAL23 :1; + IO_BYTE _MSGVAL24 :1; + }bit; + }MSGVAL2L0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSGVAL25 :1; + IO_BYTE _MSGVAL26 :1; + IO_BYTE _MSGVAL27 :1; + IO_BYTE _MSGVAL28 :1; + IO_BYTE _MSGVAL29 :1; + IO_BYTE _MSGVAL30 :1; + IO_BYTE _MSGVAL31 :1; + IO_BYTE _MSGVAL32 :1; + }bit; + }MSGVAL2H0STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }COER0STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _INIT :1; + IO_WORD _IE :1; + IO_WORD _SIE :1; + IO_WORD _EIE :1; + IO_WORD :1; + IO_WORD _DAR :1; + IO_WORD _CCE :1; + IO_WORD _TEST :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }CTRLR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INIT :1; + IO_BYTE _IE :1; + IO_BYTE _SIE :1; + IO_BYTE _EIE :1; + IO_BYTE :1; + IO_BYTE _DAR :1; + IO_BYTE _CCE :1; + IO_BYTE _TEST :1; + }bit; + }CTRLRL1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }CTRLRH1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _LEC0 :1; + IO_WORD _LEC1 :1; + IO_WORD _LEC2 :1; + IO_WORD _TXOK :1; + IO_WORD _RXOK :1; + IO_WORD _EPASS :1; + IO_WORD _EWARN :1; + IO_WORD _BOFF :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD _LEC :3; + }bitc; + }STATR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _LEC0 :1; + IO_BYTE _LEC1 :1; + IO_BYTE _LEC2 :1; + IO_BYTE _TXOK :1; + IO_BYTE _RXOK :1; + IO_BYTE _EPASS :1; + IO_BYTE _EWARN :1; + IO_BYTE _BOFF :1; + }bit; + struct{ + IO_BYTE _LEC :3; + }bitc; + }STATRL1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }STATRH1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _TEC0 :1; + IO_WORD _TEC1 :1; + IO_WORD _TEC2 :1; + IO_WORD _TEC3 :1; + IO_WORD _TEC4 :1; + IO_WORD _TEC5 :1; + IO_WORD _TEC6 :1; + IO_WORD _TEC7 :1; + IO_WORD _REC0 :1; + IO_WORD _REC1 :1; + IO_WORD _REC2 :1; + IO_WORD _REC3 :1; + IO_WORD _REC4 :1; + IO_WORD _REC5 :1; + IO_WORD _REC6 :1; + IO_WORD _RP :1; + }bit; + struct{ + IO_WORD _TEC :8; + IO_WORD _REC :7; + }bitc; + }ERRCNT1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TEC0 :1; + IO_BYTE _TEC1 :1; + IO_BYTE _TEC2 :1; + IO_BYTE _TEC3 :1; + IO_BYTE _TEC4 :1; + IO_BYTE _TEC5 :1; + IO_BYTE _TEC6 :1; + IO_BYTE _TEC7 :1; + }bit; + struct{ + IO_BYTE _TEC :8; + }bitc; + }ERRCNTL1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _REC0 :1; + IO_BYTE _REC1 :1; + IO_BYTE _REC2 :1; + IO_BYTE _REC3 :1; + IO_BYTE _REC4 :1; + IO_BYTE _REC5 :1; + IO_BYTE _REC6 :1; + IO_BYTE _RP :1; + }bit; + struct{ + IO_BYTE _REC :7; + }bitc; + }ERRCNTH1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _BRP0 :1; + IO_WORD _BRP1 :1; + IO_WORD _BRP2 :1; + IO_WORD _BRP3 :1; + IO_WORD _BRP4 :1; + IO_WORD _BRP5 :1; + IO_WORD _SJW0 :1; + IO_WORD _SJW1 :1; + IO_WORD _TSEG10 :1; + IO_WORD _TSEG11 :1; + IO_WORD _TSEG12 :1; + IO_WORD _TSEG13 :1; + IO_WORD _TSEG20 :1; + IO_WORD _TSEG21 :1; + IO_WORD _TSEG22 :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD _BRP :6; + IO_WORD _SJW :2; + IO_WORD _TSEG1 :4; + IO_WORD _TSEG2 :3; + }bitc; + }BTR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _BRP0 :1; + IO_BYTE _BRP1 :1; + IO_BYTE _BRP2 :1; + IO_BYTE _BRP3 :1; + IO_BYTE _BRP4 :1; + IO_BYTE _BRP5 :1; + IO_BYTE _SJW0 :1; + IO_BYTE _SJW1 :1; + }bit; + struct{ + IO_BYTE _BRP :6; + IO_BYTE _SJW :2; + }bitc; + }BTRL1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TSEG10 :1; + IO_BYTE _TSEG11 :1; + IO_BYTE _TSEG12 :1; + IO_BYTE _TSEG13 :1; + IO_BYTE _TSEG20 :1; + IO_BYTE _TSEG21 :1; + IO_BYTE _TSEG22 :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _TSEG1 :4; + IO_BYTE _TSEG2 :3; + }bitc; + }BTRH1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _INTID0 :1; + IO_WORD _INTID1 :1; + IO_WORD _INTID2 :1; + IO_WORD _INTID3 :1; + IO_WORD _INTID4 :1; + IO_WORD _INTID5 :1; + IO_WORD _INTID6 :1; + IO_WORD _INTID7 :1; + IO_WORD _INTID8 :1; + IO_WORD _INTID9 :1; + IO_WORD _INTID10 :1; + IO_WORD _INTID11 :1; + IO_WORD _INTID12 :1; + IO_WORD _INTID13 :1; + IO_WORD _INTID14 :1; + IO_WORD _INTID15 :1; + }bit; + struct{ + IO_WORD _INTID :16; + }bitc; + }INTR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INTID0 :1; + IO_BYTE _INTID1 :1; + IO_BYTE _INTID2 :1; + IO_BYTE _INTID3 :1; + IO_BYTE _INTID4 :1; + IO_BYTE _INTID5 :1; + IO_BYTE _INTID6 :1; + IO_BYTE _INTID7 :1; + }bit; + }INTRL1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INTID8 :1; + IO_BYTE _INTID9 :1; + IO_BYTE _INTID10 :1; + IO_BYTE _INTID11 :1; + IO_BYTE _INTID12 :1; + IO_BYTE _INTID13 :1; + IO_BYTE _INTID14 :1; + IO_BYTE _INTID15 :1; + }bit; + }INTRH1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD _BASIC :1; + IO_WORD _SILENT :1; + IO_WORD _LBACK :1; + IO_WORD _TX0 :1; + IO_WORD _TX1 :1; + IO_WORD _RX :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }TESTR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _BASIC :1; + IO_BYTE _SILENT :1; + IO_BYTE _LBACK :1; + IO_BYTE _TX0 :1; + IO_BYTE _TX1 :1; + IO_BYTE _RX :1; + }bit; + }TESTRL1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }TESTRH1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _BRPE0 :1; + IO_WORD _BRPE1 :1; + IO_WORD _BRPE2 :1; + IO_WORD _BRPE3 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + struct{ + IO_WORD _BRPE :4; + }bitc; + }BRPER1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _BRPE0 :1; + IO_BYTE _BRPE1 :1; + IO_BYTE _BRPE2 :1; + IO_BYTE _BRPE3 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + struct{ + IO_BYTE _BRPE :4; + }bitc; + }BRPERL1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }BRPERH1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _MSGN0 :1; + IO_WORD _MSGN1 :1; + IO_WORD _MSGN2 :1; + IO_WORD _MSGN3 :1; + IO_WORD _MSGN4 :1; + IO_WORD _MSGN5 :1; + IO_WORD _MSGN6 :1; + IO_WORD _MSGN7 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _BUSY :1; + }bit; + }IF1CREQ1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSGN0 :1; + IO_BYTE _MSGN1 :1; + IO_BYTE _MSGN2 :1; + IO_BYTE _MSGN3 :1; + IO_BYTE _MSGN4 :1; + IO_BYTE _MSGN5 :1; + IO_BYTE _MSGN6 :1; + IO_BYTE _MSGN7 :1; + }bit; + }IF1CREQL1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _BUSY :1; + }bit; + }IF1CREQH1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _DATAB :1; + IO_WORD _DATAA :1; + IO_WORD _TXREQ :1; + IO_WORD _CIP :1; + IO_WORD _CONTROL :1; + IO_WORD _ARB :1; + IO_WORD _MASK :1; + IO_WORD _WRRD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF1CMSK1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _DATAB :1; + IO_BYTE _DATAA :1; + IO_BYTE _TXREQ :1; + IO_BYTE _CIP :1; + IO_BYTE _CONTROL :1; + IO_BYTE _ARB :1; + IO_BYTE _MASK :1; + IO_BYTE _WRRD :1; + }bit; + }IF1CMSKL1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF1CMSKH1STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _MSK0 :1; + IO_LWORD _MSK1 :1; + IO_LWORD _MSK2 :1; + IO_LWORD _MSK3 :1; + IO_LWORD _MSK4 :1; + IO_LWORD _MSK5 :1; + IO_LWORD _MSK6 :1; + IO_LWORD _MSK7 :1; + IO_LWORD _MSK8 :1; + IO_LWORD _MSK9 :1; + IO_LWORD _MSK10 :1; + IO_LWORD _MSK11 :1; + IO_LWORD _MSK12 :1; + IO_LWORD _MSK13 :1; + IO_LWORD _MSK14 :1; + IO_LWORD _MSK15 :1; + IO_LWORD _MSK16 :1; + IO_LWORD _MSK17 :1; + IO_LWORD _MSK18 :1; + IO_LWORD _MSK19 :1; + IO_LWORD _MSK20 :1; + IO_LWORD _MSK21 :1; + IO_LWORD _MSK22 :1; + IO_LWORD _MSK23 :1; + IO_LWORD _MSK24 :1; + IO_LWORD _MSK25 :1; + IO_LWORD _MSK26 :1; + IO_LWORD _MSK27 :1; + IO_LWORD _MSK28 :1; + IO_LWORD :1; + IO_LWORD _MDIR :1; + IO_LWORD _MXTD :1; + }bit; + struct{ + IO_LWORD _MSK :29; + }bitc; + }IF1MSK1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _MSK0 :1; + IO_WORD _MSK1 :1; + IO_WORD _MSK2 :1; + IO_WORD _MSK3 :1; + IO_WORD _MSK4 :1; + IO_WORD _MSK5 :1; + IO_WORD _MSK6 :1; + IO_WORD _MSK7 :1; + IO_WORD _MSK8 :1; + IO_WORD _MSK9 :1; + IO_WORD _MSK10 :1; + IO_WORD _MSK11 :1; + IO_WORD _MSK12 :1; + IO_WORD _MSK13 :1; + IO_WORD _MSK14 :1; + IO_WORD _MSK15 :1; + }bit; + }IF1MSK11STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSK0 :1; + IO_BYTE _MSK1 :1; + IO_BYTE _MSK2 :1; + IO_BYTE _MSK3 :1; + IO_BYTE _MSK4 :1; + IO_BYTE _MSK5 :1; + IO_BYTE _MSK6 :1; + IO_BYTE _MSK7 :1; + }bit; + }IF1MSK1L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSK8 :1; + IO_BYTE _MSK9 :1; + IO_BYTE _MSK10 :1; + IO_BYTE _MSK11 :1; + IO_BYTE _MSK12 :1; + IO_BYTE _MSK13 :1; + IO_BYTE _MSK14 :1; + IO_BYTE _MSK15 :1; + }bit; + }IF1MSK1H1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _MSK16 :1; + IO_WORD _MSK17 :1; + IO_WORD _MSK18 :1; + IO_WORD _MSK19 :1; + IO_WORD _MSK20 :1; + IO_WORD _MSK21 :1; + IO_WORD _MSK22 :1; + IO_WORD _MSK23 :1; + IO_WORD _MSK24 :1; + IO_WORD _MSK25 :1; + IO_WORD _MSK26 :1; + IO_WORD _MSK27 :1; + IO_WORD _MSK28 :1; + IO_WORD :1; + IO_WORD _MDIR :1; + IO_WORD _MXTD :1; + }bit; + }IF1MSK21STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSK16 :1; + IO_BYTE _MSK17 :1; + IO_BYTE _MSK18 :1; + IO_BYTE _MSK19 :1; + IO_BYTE _MSK20 :1; + IO_BYTE _MSK21 :1; + IO_BYTE _MSK22 :1; + IO_BYTE _MSK23 :1; + }bit; + }IF1MSK2L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSK24 :1; + IO_BYTE _MSK25 :1; + IO_BYTE _MSK26 :1; + IO_BYTE _MSK27 :1; + IO_BYTE _MSK28 :1; + IO_BYTE :1; + IO_BYTE _MDIR :1; + IO_BYTE _MXTD :1; + }bit; + }IF1MSK2H1STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _ID0 :1; + IO_LWORD _ID1 :1; + IO_LWORD _ID2 :1; + IO_LWORD _ID3 :1; + IO_LWORD _ID4 :1; + IO_LWORD _ID5 :1; + IO_LWORD _ID6 :1; + IO_LWORD _ID7 :1; + IO_LWORD _ID8 :1; + IO_LWORD _ID9 :1; + IO_LWORD _ID10 :1; + IO_LWORD _ID11 :1; + IO_LWORD _ID12 :1; + IO_LWORD _ID13 :1; + IO_LWORD _ID14 :1; + IO_LWORD _ID15 :1; + IO_LWORD _ID16 :1; + IO_LWORD _ID17 :1; + IO_LWORD _ID18 :1; + IO_LWORD _ID19 :1; + IO_LWORD _ID20 :1; + IO_LWORD _ID21 :1; + IO_LWORD _ID22 :1; + IO_LWORD _ID23 :1; + IO_LWORD _ID24 :1; + IO_LWORD _ID25 :1; + IO_LWORD _ID26 :1; + IO_LWORD _ID27 :1; + IO_LWORD _ID28 :1; + IO_LWORD _DIR :1; + IO_LWORD _XTD :1; + IO_LWORD _MSGVAL :1; + }bit; + struct{ + IO_LWORD _ID :29; + }bitc; + }IF1ARB1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _ID0 :1; + IO_WORD _ID1 :1; + IO_WORD _ID2 :1; + IO_WORD _ID3 :1; + IO_WORD _ID4 :1; + IO_WORD _ID5 :1; + IO_WORD _ID6 :1; + IO_WORD _ID7 :1; + IO_WORD _ID8 :1; + IO_WORD _ID9 :1; + IO_WORD _ID10 :1; + IO_WORD _ID11 :1; + IO_WORD _ID12 :1; + IO_WORD _ID13 :1; + IO_WORD _ID14 :1; + IO_WORD _ID15 :1; + }bit; + }IF1ARB11STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ID0 :1; + IO_BYTE _ID1 :1; + IO_BYTE _ID2 :1; + IO_BYTE _ID3 :1; + IO_BYTE _ID4 :1; + IO_BYTE _ID5 :1; + IO_BYTE _ID6 :1; + IO_BYTE _ID7 :1; + }bit; + }IF1ARB1L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ID8 :1; + IO_BYTE _ID9 :1; + IO_BYTE _ID10 :1; + IO_BYTE _ID11 :1; + IO_BYTE _ID12 :1; + IO_BYTE _ID13 :1; + IO_BYTE _ID14 :1; + IO_BYTE _ID15 :1; + }bit; + }IF1ARB1H1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _ID16 :1; + IO_WORD _ID17 :1; + IO_WORD _ID18 :1; + IO_WORD _ID19 :1; + IO_WORD _ID20 :1; + IO_WORD _ID21 :1; + IO_WORD _ID22 :1; + IO_WORD _ID23 :1; + IO_WORD _ID24 :1; + IO_WORD _ID25 :1; + IO_WORD _ID26 :1; + IO_WORD _ID27 :1; + IO_WORD _ID28 :1; + IO_WORD _DIR :1; + IO_WORD _XTD :1; + IO_WORD _MSGVAL :1; + }bit; + }IF1ARB21STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ID16 :1; + IO_BYTE _ID17 :1; + IO_BYTE _ID18 :1; + IO_BYTE _ID19 :1; + IO_BYTE _ID20 :1; + IO_BYTE _ID21 :1; + IO_BYTE _ID22 :1; + IO_BYTE _ID23 :1; + }bit; + }IF1ARB2L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ID24 :1; + IO_BYTE _ID25 :1; + IO_BYTE _ID26 :1; + IO_BYTE _ID27 :1; + IO_BYTE _ID28 :1; + IO_BYTE _DIR :1; + IO_BYTE _XTD :1; + IO_BYTE _MSGVAL :1; + }bit; + }IF1ARB2H1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _DLC0 :1; + IO_WORD _DLC1 :1; + IO_WORD _DLC2 :1; + IO_WORD _DLC3 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _EOB :1; + IO_WORD _TXRQST :1; + IO_WORD _RMTEN :1; + IO_WORD _RXIE :1; + IO_WORD _TXIE :1; + IO_WORD _UMASK :1; + IO_WORD _INTPND :1; + IO_WORD _MSGLST :1; + IO_WORD _NEWDAT :1; + }bit; + struct{ + IO_WORD _DLC :4; + }bitc; + }IF1MCTR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _DLC0 :1; + IO_BYTE _DLC1 :1; + IO_BYTE _DLC2 :1; + IO_BYTE _DLC3 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _EOB :1; + }bit; + struct{ + IO_BYTE _DLC :4; + }bitc; + }IF1MCTRL1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TXRQST :1; + IO_BYTE _RMTEN :1; + IO_BYTE _RXIE :1; + IO_BYTE _TXIE :1; + IO_BYTE _UMASK :1; + IO_BYTE _INTPND :1; + IO_BYTE _MSGLST :1; + IO_BYTE _NEWDAT :1; + }bit; + }IF1MCTRH1STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + }bit; + }IF1DTA1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF1DTA11STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF1DTA1L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF1DTA1H1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF1DTA21STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF1DTA2L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF1DTA2H1STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + }bit; + }IF1DTB1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF1DTB11STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF1DTB1L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF1DTB1H1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF1DTB21STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF1DTB2L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF1DTB2H1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _MSGN0 :1; + IO_WORD _MSGN1 :1; + IO_WORD _MSGN2 :1; + IO_WORD _MSGN3 :1; + IO_WORD _MSGN4 :1; + IO_WORD _MSGN5 :1; + IO_WORD _MSGN6 :1; + IO_WORD _MSGN7 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _BUSY :1; + }bit; + }IF2CREQ1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSGN0 :1; + IO_BYTE _MSGN1 :1; + IO_BYTE _MSGN2 :1; + IO_BYTE _MSGN3 :1; + IO_BYTE _MSGN4 :1; + IO_BYTE _MSGN5 :1; + IO_BYTE _MSGN6 :1; + IO_BYTE _MSGN7 :1; + }bit; + }IF2CREQL1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _BUSY :1; + }bit; + }IF2CREQH1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _DATAB :1; + IO_WORD _DATAA :1; + IO_WORD _TXREQ :1; + IO_WORD _CIP :1; + IO_WORD _CONTROL :1; + IO_WORD _ARB :1; + IO_WORD _MASK :1; + IO_WORD _WRRD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF2CMSK1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _DATAB :1; + IO_BYTE _DATAA :1; + IO_BYTE _TXREQ :1; + IO_BYTE _CIP :1; + IO_BYTE _CONTROL :1; + IO_BYTE _ARB :1; + IO_BYTE _MASK :1; + IO_BYTE _WRRD :1; + }bit; + }IF2CMSKL1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF2CMSKH1STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _MSK0 :1; + IO_LWORD _MSK1 :1; + IO_LWORD _MSK2 :1; + IO_LWORD _MSK3 :1; + IO_LWORD _MSK4 :1; + IO_LWORD _MSK5 :1; + IO_LWORD _MSK6 :1; + IO_LWORD _MSK7 :1; + IO_LWORD _MSK8 :1; + IO_LWORD _MSK9 :1; + IO_LWORD _MSK10 :1; + IO_LWORD _MSK11 :1; + IO_LWORD _MSK12 :1; + IO_LWORD _MSK13 :1; + IO_LWORD _MSK14 :1; + IO_LWORD _MSK15 :1; + IO_LWORD _MSK16 :1; + IO_LWORD _MSK17 :1; + IO_LWORD _MSK18 :1; + IO_LWORD _MSK19 :1; + IO_LWORD _MSK20 :1; + IO_LWORD _MSK21 :1; + IO_LWORD _MSK22 :1; + IO_LWORD _MSK23 :1; + IO_LWORD _MSK24 :1; + IO_LWORD _MSK25 :1; + IO_LWORD _MSK26 :1; + IO_LWORD _MSK27 :1; + IO_LWORD _MSK28 :1; + IO_LWORD :1; + IO_LWORD _MDIR :1; + IO_LWORD _MXTD :1; + }bit; + struct{ + IO_LWORD _MSK :29; + }bitc; + }IF2MSK1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _MSK0 :1; + IO_WORD _MSK1 :1; + IO_WORD _MSK2 :1; + IO_WORD _MSK3 :1; + IO_WORD _MSK4 :1; + IO_WORD _MSK5 :1; + IO_WORD _MSK6 :1; + IO_WORD _MSK7 :1; + IO_WORD _MSK8 :1; + IO_WORD _MSK9 :1; + IO_WORD _MSK10 :1; + IO_WORD _MSK11 :1; + IO_WORD _MSK12 :1; + IO_WORD _MSK13 :1; + IO_WORD _MSK14 :1; + IO_WORD _MSK15 :1; + }bit; + }IF2MSK11STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSK0 :1; + IO_BYTE _MSK1 :1; + IO_BYTE _MSK2 :1; + IO_BYTE _MSK3 :1; + IO_BYTE _MSK4 :1; + IO_BYTE _MSK5 :1; + IO_BYTE _MSK6 :1; + IO_BYTE _MSK7 :1; + }bit; + }IF2MSK1L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSK8 :1; + IO_BYTE _MSK9 :1; + IO_BYTE _MSK10 :1; + IO_BYTE _MSK11 :1; + IO_BYTE _MSK12 :1; + IO_BYTE _MSK13 :1; + IO_BYTE _MSK14 :1; + IO_BYTE _MSK15 :1; + }bit; + }IF2MSK1H1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _MSK16 :1; + IO_WORD _MSK17 :1; + IO_WORD _MSK18 :1; + IO_WORD _MSK19 :1; + IO_WORD _MSK20 :1; + IO_WORD _MSK21 :1; + IO_WORD _MSK22 :1; + IO_WORD _MSK23 :1; + IO_WORD _MSK24 :1; + IO_WORD _MSK25 :1; + IO_WORD _MSK26 :1; + IO_WORD _MSK27 :1; + IO_WORD _MSK28 :1; + IO_WORD :1; + IO_WORD _MDIR :1; + IO_WORD _MXTD :1; + }bit; + }IF2MSK21STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSK16 :1; + IO_BYTE _MSK17 :1; + IO_BYTE _MSK18 :1; + IO_BYTE _MSK19 :1; + IO_BYTE _MSK20 :1; + IO_BYTE _MSK21 :1; + IO_BYTE _MSK22 :1; + IO_BYTE _MSK23 :1; + }bit; + }IF2MSK2L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSK24 :1; + IO_BYTE _MSK25 :1; + IO_BYTE _MSK26 :1; + IO_BYTE _MSK27 :1; + IO_BYTE _MSK28 :1; + IO_BYTE :1; + IO_BYTE _MDIR :1; + IO_BYTE _MXTD :1; + }bit; + }IF2MSK2H1STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _ID0 :1; + IO_LWORD _ID1 :1; + IO_LWORD _ID2 :1; + IO_LWORD _ID3 :1; + IO_LWORD _ID4 :1; + IO_LWORD _ID5 :1; + IO_LWORD _ID6 :1; + IO_LWORD _ID7 :1; + IO_LWORD _ID8 :1; + IO_LWORD _ID9 :1; + IO_LWORD _ID10 :1; + IO_LWORD _ID11 :1; + IO_LWORD _ID12 :1; + IO_LWORD _ID13 :1; + IO_LWORD _ID14 :1; + IO_LWORD _ID15 :1; + IO_LWORD _ID16 :1; + IO_LWORD _ID17 :1; + IO_LWORD _ID18 :1; + IO_LWORD _ID19 :1; + IO_LWORD _ID20 :1; + IO_LWORD _ID21 :1; + IO_LWORD _ID22 :1; + IO_LWORD _ID23 :1; + IO_LWORD _ID24 :1; + IO_LWORD _ID25 :1; + IO_LWORD _ID26 :1; + IO_LWORD _ID27 :1; + IO_LWORD _ID28 :1; + IO_LWORD _DIR :1; + IO_LWORD _XTD :1; + IO_LWORD _MSGVAL :1; + }bit; + struct{ + IO_LWORD _ID :29; + }bitc; + }IF2ARB1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _ID0 :1; + IO_WORD _ID1 :1; + IO_WORD _ID2 :1; + IO_WORD _ID3 :1; + IO_WORD _ID4 :1; + IO_WORD _ID5 :1; + IO_WORD _ID6 :1; + IO_WORD _ID7 :1; + IO_WORD _ID8 :1; + IO_WORD _ID9 :1; + IO_WORD _ID10 :1; + IO_WORD _ID11 :1; + IO_WORD _ID12 :1; + IO_WORD _ID13 :1; + IO_WORD _ID14 :1; + IO_WORD _ID15 :1; + }bit; + }IF2ARB11STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ID0 :1; + IO_BYTE _ID1 :1; + IO_BYTE _ID2 :1; + IO_BYTE _ID3 :1; + IO_BYTE _ID4 :1; + IO_BYTE _ID5 :1; + IO_BYTE _ID6 :1; + IO_BYTE _ID7 :1; + }bit; + }IF2ARB1L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ID8 :1; + IO_BYTE _ID9 :1; + IO_BYTE _ID10 :1; + IO_BYTE _ID11 :1; + IO_BYTE _ID12 :1; + IO_BYTE _ID13 :1; + IO_BYTE _ID14 :1; + IO_BYTE _ID15 :1; + }bit; + }IF2ARB1H1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _ID16 :1; + IO_WORD _ID17 :1; + IO_WORD _ID18 :1; + IO_WORD _ID19 :1; + IO_WORD _ID20 :1; + IO_WORD _ID21 :1; + IO_WORD _ID22 :1; + IO_WORD _ID23 :1; + IO_WORD _ID24 :1; + IO_WORD _ID25 :1; + IO_WORD _ID26 :1; + IO_WORD _ID27 :1; + IO_WORD _ID28 :1; + IO_WORD _DIR :1; + IO_WORD _XTD :1; + IO_WORD _MSGVAL :1; + }bit; + }IF2ARB21STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ID16 :1; + IO_BYTE _ID17 :1; + IO_BYTE _ID18 :1; + IO_BYTE _ID19 :1; + IO_BYTE _ID20 :1; + IO_BYTE _ID21 :1; + IO_BYTE _ID22 :1; + IO_BYTE _ID23 :1; + }bit; + }IF2ARB2L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _ID24 :1; + IO_BYTE _ID25 :1; + IO_BYTE _ID26 :1; + IO_BYTE _ID27 :1; + IO_BYTE _ID28 :1; + IO_BYTE _DIR :1; + IO_BYTE _XTD :1; + IO_BYTE _MSGVAL :1; + }bit; + }IF2ARB2H1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _DLC0 :1; + IO_WORD _DLC1 :1; + IO_WORD _DLC2 :1; + IO_WORD _DLC3 :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD _EOB :1; + IO_WORD _TXRQST :1; + IO_WORD _RMTEN :1; + IO_WORD _RXIE :1; + IO_WORD _TXIE :1; + IO_WORD _UMASK :1; + IO_WORD _INTPND :1; + IO_WORD _MSGLST :1; + IO_WORD _NEWDAT :1; + }bit; + struct{ + IO_WORD _DLC :4; + }bitc; + }IF2MCTR1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _DLC0 :1; + IO_BYTE _DLC1 :1; + IO_BYTE _DLC2 :1; + IO_BYTE _DLC3 :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE _EOB :1; + }bit; + struct{ + IO_BYTE _DLC :4; + }bitc; + }IF2MCTRL1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TXRQST :1; + IO_BYTE _RMTEN :1; + IO_BYTE _RXIE :1; + IO_BYTE _TXIE :1; + IO_BYTE _UMASK :1; + IO_BYTE _INTPND :1; + IO_BYTE _MSGLST :1; + IO_BYTE _NEWDAT :1; + }bit; + }IF2MCTRH1STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + }bit; + }IF2DTA1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF2DTA11STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF2DTA1L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF2DTA1H1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF2DTA21STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF2DTA2L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF2DTA2H1STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + IO_LWORD :1; + }bit; + }IF2DTB1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF2DTB11STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF2DTB1L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF2DTB1H1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + IO_WORD :1; + }bit; + }IF2DTB21STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF2DTB2L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }IF2DTB2H1STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _TXRQST1 :1; + IO_LWORD _TXRQST2 :1; + IO_LWORD _TXRQST3 :1; + IO_LWORD _TXRQST4 :1; + IO_LWORD _TXRQST5 :1; + IO_LWORD _TXRQST6 :1; + IO_LWORD _TXRQST7 :1; + IO_LWORD _TXRQST8 :1; + IO_LWORD _TXRQST9 :1; + IO_LWORD _TXRQST10 :1; + IO_LWORD _TXRQST11 :1; + IO_LWORD _TXRQST12 :1; + IO_LWORD _TXRQST13 :1; + IO_LWORD _TXRQST14 :1; + IO_LWORD _TXRQST15 :1; + IO_LWORD _TXRQST16 :1; + IO_LWORD _TXRQST17 :1; + IO_LWORD _TXRQST18 :1; + IO_LWORD _TXRQST19 :1; + IO_LWORD _TXRQST20 :1; + IO_LWORD _TXRQST21 :1; + IO_LWORD _TXRQST22 :1; + IO_LWORD _TXRQST23 :1; + IO_LWORD _TXRQST24 :1; + IO_LWORD _TXRQST25 :1; + IO_LWORD _TXRQST26 :1; + IO_LWORD _TXRQST27 :1; + IO_LWORD _TXRQST28 :1; + IO_LWORD _TXRQST29 :1; + IO_LWORD _TXRQST30 :1; + IO_LWORD _TXRQST31 :1; + IO_LWORD _TXRQST32 :1; + }bit; + struct{ + IO_LWORD _TXRQST :32; + }bitc; + }TREQR1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _TXRQST1 :1; + IO_WORD _TXRQST2 :1; + IO_WORD _TXRQST3 :1; + IO_WORD _TXRQST4 :1; + IO_WORD _TXRQST5 :1; + IO_WORD _TXRQST6 :1; + IO_WORD _TXRQST7 :1; + IO_WORD _TXRQST8 :1; + IO_WORD _TXRQST9 :1; + IO_WORD _TXRQST10 :1; + IO_WORD _TXRQST11 :1; + IO_WORD _TXRQST12 :1; + IO_WORD _TXRQST13 :1; + IO_WORD _TXRQST14 :1; + IO_WORD _TXRQST15 :1; + IO_WORD _TXRQST16 :1; + }bit; + }TREQR11STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TXRQST1 :1; + IO_BYTE _TXRQST2 :1; + IO_BYTE _TXRQST3 :1; + IO_BYTE _TXRQST4 :1; + IO_BYTE _TXRQST5 :1; + IO_BYTE _TXRQST6 :1; + IO_BYTE _TXRQST7 :1; + IO_BYTE _TXRQST8 :1; + }bit; + }TREQR1L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TXRQST9 :1; + IO_BYTE _TXRQST10 :1; + IO_BYTE _TXRQST11 :1; + IO_BYTE _TXRQST12 :1; + IO_BYTE _TXRQST13 :1; + IO_BYTE _TXRQST14 :1; + IO_BYTE _TXRQST15 :1; + IO_BYTE _TXRQST16 :1; + }bit; + }TREQR1H1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _TXRQST17 :1; + IO_WORD _TXRQST18 :1; + IO_WORD _TXRQST19 :1; + IO_WORD _TXRQST20 :1; + IO_WORD _TXRQST21 :1; + IO_WORD _TXRQST22 :1; + IO_WORD _TXRQST23 :1; + IO_WORD _TXRQST24 :1; + IO_WORD _TXRQST25 :1; + IO_WORD _TXRQST26 :1; + IO_WORD _TXRQST27 :1; + IO_WORD _TXRQST28 :1; + IO_WORD _TXRQST29 :1; + IO_WORD _TXRQST30 :1; + IO_WORD _TXRQST31 :1; + IO_WORD _TXRQST32 :1; + }bit; + }TREQR21STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TXRQST17 :1; + IO_BYTE _TXRQST18 :1; + IO_BYTE _TXRQST19 :1; + IO_BYTE _TXRQST20 :1; + IO_BYTE _TXRQST21 :1; + IO_BYTE _TXRQST22 :1; + IO_BYTE _TXRQST23 :1; + IO_BYTE _TXRQST24 :1; + }bit; + }TREQR2L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _TXRQST25 :1; + IO_BYTE _TXRQST26 :1; + IO_BYTE _TXRQST27 :1; + IO_BYTE _TXRQST28 :1; + IO_BYTE _TXRQST29 :1; + IO_BYTE _TXRQST30 :1; + IO_BYTE _TXRQST31 :1; + IO_BYTE _TXRQST32 :1; + }bit; + }TREQR2H1STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _NEWDAT1 :1; + IO_LWORD _NEWDAT2 :1; + IO_LWORD _NEWDAT3 :1; + IO_LWORD _NEWDAT4 :1; + IO_LWORD _NEWDAT5 :1; + IO_LWORD _NEWDAT6 :1; + IO_LWORD _NEWDAT7 :1; + IO_LWORD _NEWDAT8 :1; + IO_LWORD _NEWDAT9 :1; + IO_LWORD _NEWDAT10 :1; + IO_LWORD _NEWDAT11 :1; + IO_LWORD _NEWDAT12 :1; + IO_LWORD _NEWDAT13 :1; + IO_LWORD _NEWDAT14 :1; + IO_LWORD _NEWDAT15 :1; + IO_LWORD _NEWDAT16 :1; + IO_LWORD _NEWDAT17 :1; + IO_LWORD _NEWDAT18 :1; + IO_LWORD _NEWDAT19 :1; + IO_LWORD _NEWDAT20 :1; + IO_LWORD _NEWDAT21 :1; + IO_LWORD _NEWDAT22 :1; + IO_LWORD _NEWDAT23 :1; + IO_LWORD _NEWDAT24 :1; + IO_LWORD _NEWDAT25 :1; + IO_LWORD _NEWDAT26 :1; + IO_LWORD _NEWDAT27 :1; + IO_LWORD _NEWDAT28 :1; + IO_LWORD _NEWDAT29 :1; + IO_LWORD _NEWDAT30 :1; + IO_LWORD _NEWDAT31 :1; + IO_LWORD _NEWDAT32 :1; + }bit; + struct{ + IO_LWORD _NEWDAT :32; + }bitc; + }NEWDT1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _NEWDAT1 :1; + IO_WORD _NEWDAT2 :1; + IO_WORD _NEWDAT3 :1; + IO_WORD _NEWDAT4 :1; + IO_WORD _NEWDAT5 :1; + IO_WORD _NEWDAT6 :1; + IO_WORD _NEWDAT7 :1; + IO_WORD _NEWDAT8 :1; + IO_WORD _NEWDAT9 :1; + IO_WORD _NEWDAT10 :1; + IO_WORD _NEWDAT11 :1; + IO_WORD _NEWDAT12 :1; + IO_WORD _NEWDAT13 :1; + IO_WORD _NEWDAT14 :1; + IO_WORD _NEWDAT15 :1; + IO_WORD _NEWDAT16 :1; + }bit; + }NEWDT11STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _NEWDAT1 :1; + IO_BYTE _NEWDAT2 :1; + IO_BYTE _NEWDAT3 :1; + IO_BYTE _NEWDAT4 :1; + IO_BYTE _NEWDAT5 :1; + IO_BYTE _NEWDAT6 :1; + IO_BYTE _NEWDAT7 :1; + IO_BYTE _NEWDAT8 :1; + }bit; + }NEWDT1L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _NEWDAT9 :1; + IO_BYTE _NEWDAT10 :1; + IO_BYTE _NEWDAT11 :1; + IO_BYTE _NEWDAT12 :1; + IO_BYTE _NEWDAT13 :1; + IO_BYTE _NEWDAT14 :1; + IO_BYTE _NEWDAT15 :1; + IO_BYTE _NEWDAT16 :1; + }bit; + }NEWDT1H1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _NEWDAT17 :1; + IO_WORD _NEWDAT18 :1; + IO_WORD _NEWDAT19 :1; + IO_WORD _NEWDAT20 :1; + IO_WORD _NEWDAT21 :1; + IO_WORD _NEWDAT22 :1; + IO_WORD _NEWDAT23 :1; + IO_WORD _NEWDAT24 :1; + IO_WORD _NEWDAT25 :1; + IO_WORD _NEWDAT26 :1; + IO_WORD _NEWDAT27 :1; + IO_WORD _NEWDAT28 :1; + IO_WORD _NEWDAT29 :1; + IO_WORD _NEWDAT30 :1; + IO_WORD _NEWDAT31 :1; + IO_WORD _NEWDAT32 :1; + }bit; + }NEWDT21STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _NEWDAT17 :1; + IO_BYTE _NEWDAT18 :1; + IO_BYTE _NEWDAT19 :1; + IO_BYTE _NEWDAT20 :1; + IO_BYTE _NEWDAT21 :1; + IO_BYTE _NEWDAT22 :1; + IO_BYTE _NEWDAT23 :1; + IO_BYTE _NEWDAT24 :1; + }bit; + }NEWDT2L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _NEWDAT25 :1; + IO_BYTE _NEWDAT26 :1; + IO_BYTE _NEWDAT27 :1; + IO_BYTE _NEWDAT28 :1; + IO_BYTE _NEWDAT29 :1; + IO_BYTE _NEWDAT30 :1; + IO_BYTE _NEWDAT31 :1; + IO_BYTE _NEWDAT32 :1; + }bit; + }NEWDT2H1STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _INTPND1 :1; + IO_LWORD _INTPND2 :1; + IO_LWORD _INTPND3 :1; + IO_LWORD _INTPND4 :1; + IO_LWORD _INTPND5 :1; + IO_LWORD _INTPND6 :1; + IO_LWORD _INTPND7 :1; + IO_LWORD _INTPND8 :1; + IO_LWORD _INTPND9 :1; + IO_LWORD _INTPND10 :1; + IO_LWORD _INTPND11 :1; + IO_LWORD _INTPND12 :1; + IO_LWORD _INTPND13 :1; + IO_LWORD _INTPND14 :1; + IO_LWORD _INTPND15 :1; + IO_LWORD _INTPND16 :1; + IO_LWORD _INTPND17 :1; + IO_LWORD _INTPND18 :1; + IO_LWORD _INTPND19 :1; + IO_LWORD _INTPND20 :1; + IO_LWORD _INTPND21 :1; + IO_LWORD _INTPND22 :1; + IO_LWORD _INTPND23 :1; + IO_LWORD _INTPND24 :1; + IO_LWORD _INTPND25 :1; + IO_LWORD _INTPND26 :1; + IO_LWORD _INTPND27 :1; + IO_LWORD _INTPND28 :1; + IO_LWORD _INTPND29 :1; + IO_LWORD _INTPND30 :1; + IO_LWORD _INTPND31 :1; + IO_LWORD _INTPND32 :1; + }bit; + struct{ + IO_LWORD _INTPND :32; + }bitc; + }INTPND1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _INTPND1 :1; + IO_WORD _INTPND2 :1; + IO_WORD _INTPND3 :1; + IO_WORD _INTPND4 :1; + IO_WORD _INTPND5 :1; + IO_WORD _INTPND6 :1; + IO_WORD _INTPND7 :1; + IO_WORD _INTPND8 :1; + IO_WORD _INTPND9 :1; + IO_WORD _INTPND10 :1; + IO_WORD _INTPND11 :1; + IO_WORD _INTPND12 :1; + IO_WORD _INTPND13 :1; + IO_WORD _INTPND14 :1; + IO_WORD _INTPND15 :1; + IO_WORD _INTPND16 :1; + }bit; + }INTPND11STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INTPND1 :1; + IO_BYTE _INTPND2 :1; + IO_BYTE _INTPND3 :1; + IO_BYTE _INTPND4 :1; + IO_BYTE _INTPND5 :1; + IO_BYTE _INTPND6 :1; + IO_BYTE _INTPND7 :1; + IO_BYTE _INTPND8 :1; + }bit; + }INTPND1L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INTPND9 :1; + IO_BYTE _INTPND10 :1; + IO_BYTE _INTPND11 :1; + IO_BYTE _INTPND12 :1; + IO_BYTE _INTPND13 :1; + IO_BYTE _INTPND14 :1; + IO_BYTE _INTPND15 :1; + IO_BYTE _INTPND16 :1; + }bit; + }INTPND1H1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _INTPND17 :1; + IO_WORD _INTPND18 :1; + IO_WORD _INTPND19 :1; + IO_WORD _INTPND20 :1; + IO_WORD _INTPND21 :1; + IO_WORD _INTPND22 :1; + IO_WORD _INTPND23 :1; + IO_WORD _INTPND24 :1; + IO_WORD _INTPND25 :1; + IO_WORD _INTPND26 :1; + IO_WORD _INTPND27 :1; + IO_WORD _INTPND28 :1; + IO_WORD _INTPND29 :1; + IO_WORD _INTPND30 :1; + IO_WORD _INTPND31 :1; + IO_WORD _INTPND32 :1; + }bit; + }INTPND21STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INTPND17 :1; + IO_BYTE _INTPND18 :1; + IO_BYTE _INTPND19 :1; + IO_BYTE _INTPND20 :1; + IO_BYTE _INTPND21 :1; + IO_BYTE _INTPND22 :1; + IO_BYTE _INTPND23 :1; + IO_BYTE _INTPND24 :1; + }bit; + }INTPND2L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _INTPND25 :1; + IO_BYTE _INTPND26 :1; + IO_BYTE _INTPND27 :1; + IO_BYTE _INTPND28 :1; + IO_BYTE _INTPND29 :1; + IO_BYTE _INTPND30 :1; + IO_BYTE _INTPND31 :1; + IO_BYTE _INTPND32 :1; + }bit; + }INTPND2H1STR; +typedef union{ + IO_LWORD lword; + struct{ + IO_LWORD _MSGVAL1 :1; + IO_LWORD _MSGVAL2 :1; + IO_LWORD _MSGVAL3 :1; + IO_LWORD _MSGVAL4 :1; + IO_LWORD _MSGVAL5 :1; + IO_LWORD _MSGVAL6 :1; + IO_LWORD _MSGVAL7 :1; + IO_LWORD _MSGVAL8 :1; + IO_LWORD _MSGVAL9 :1; + IO_LWORD _MSGVAL10 :1; + IO_LWORD _MSGVAL11 :1; + IO_LWORD _MSGVAL12 :1; + IO_LWORD _MSGVAL13 :1; + IO_LWORD _MSGVAL14 :1; + IO_LWORD _MSGVAL15 :1; + IO_LWORD _MSGVAL16 :1; + IO_LWORD _MSGVAL17 :1; + IO_LWORD _MSGVAL18 :1; + IO_LWORD _MSGVAL19 :1; + IO_LWORD _MSGVAL20 :1; + IO_LWORD _MSGVAL21 :1; + IO_LWORD _MSGVAL22 :1; + IO_LWORD _MSGVAL23 :1; + IO_LWORD _MSGVAL24 :1; + IO_LWORD _MSGVAL25 :1; + IO_LWORD _MSGVAL26 :1; + IO_LWORD _MSGVAL27 :1; + IO_LWORD _MSGVAL28 :1; + IO_LWORD _MSGVAL29 :1; + IO_LWORD _MSGVAL30 :1; + IO_LWORD _MSGVAL31 :1; + IO_LWORD _MSGVAL32 :1; + }bit; + struct{ + IO_LWORD _MSGVAL :32; + }bitc; + }MSGVAL1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _MSGVAL1 :1; + IO_WORD _MSGVAL2 :1; + IO_WORD _MSGVAL3 :1; + IO_WORD _MSGVAL4 :1; + IO_WORD _MSGVAL5 :1; + IO_WORD _MSGVAL6 :1; + IO_WORD _MSGVAL7 :1; + IO_WORD _MSGVAL8 :1; + IO_WORD _MSGVAL9 :1; + IO_WORD _MSGVAL10 :1; + IO_WORD _MSGVAL11 :1; + IO_WORD _MSGVAL12 :1; + IO_WORD _MSGVAL13 :1; + IO_WORD _MSGVAL14 :1; + IO_WORD _MSGVAL15 :1; + IO_WORD _MSGVAL16 :1; + }bit; + }MSGVAL11STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSGVAL1 :1; + IO_BYTE _MSGVAL2 :1; + IO_BYTE _MSGVAL3 :1; + IO_BYTE _MSGVAL4 :1; + IO_BYTE _MSGVAL5 :1; + IO_BYTE _MSGVAL6 :1; + IO_BYTE _MSGVAL7 :1; + IO_BYTE _MSGVAL8 :1; + }bit; + }MSGVAL1L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSGVAL9 :1; + IO_BYTE _MSGVAL10 :1; + IO_BYTE _MSGVAL11 :1; + IO_BYTE _MSGVAL12 :1; + IO_BYTE _MSGVAL13 :1; + IO_BYTE _MSGVAL14 :1; + IO_BYTE _MSGVAL15 :1; + IO_BYTE _MSGVAL16 :1; + }bit; + }MSGVAL1H1STR; +typedef union{ + IO_WORD word; + struct{ + IO_WORD _MSGVAL17 :1; + IO_WORD _MSGVAL18 :1; + IO_WORD _MSGVAL19 :1; + IO_WORD _MSGVAL20 :1; + IO_WORD _MSGVAL21 :1; + IO_WORD _MSGVAL22 :1; + IO_WORD _MSGVAL23 :1; + IO_WORD _MSGVAL24 :1; + IO_WORD _MSGVAL25 :1; + IO_WORD _MSGVAL26 :1; + IO_WORD _MSGVAL27 :1; + IO_WORD _MSGVAL28 :1; + IO_WORD _MSGVAL29 :1; + IO_WORD _MSGVAL30 :1; + IO_WORD _MSGVAL31 :1; + IO_WORD _MSGVAL32 :1; + }bit; + }MSGVAL21STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSGVAL17 :1; + IO_BYTE _MSGVAL18 :1; + IO_BYTE _MSGVAL19 :1; + IO_BYTE _MSGVAL20 :1; + IO_BYTE _MSGVAL21 :1; + IO_BYTE _MSGVAL22 :1; + IO_BYTE _MSGVAL23 :1; + IO_BYTE _MSGVAL24 :1; + }bit; + }MSGVAL2L1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _MSGVAL25 :1; + IO_BYTE _MSGVAL26 :1; + IO_BYTE _MSGVAL27 :1; + IO_BYTE _MSGVAL28 :1; + IO_BYTE _MSGVAL29 :1; + IO_BYTE _MSGVAL30 :1; + IO_BYTE _MSGVAL31 :1; + IO_BYTE _MSGVAL32 :1; + }bit; + }MSGVAL2H1STR; +typedef union{ + IO_BYTE byte; + struct{ + IO_BYTE _OE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + IO_BYTE :1; + }bit; + }COER1STR; + +/* C-DECLARATIONS */ + +__IO_EXTERN __io PDR00STR _pdr00; +#define PDR00 _pdr00.byte +#define PDR00_P0 _pdr00.bit._P0 +#define PDR00_P1 _pdr00.bit._P1 +#define PDR00_P2 _pdr00.bit._P2 +#define PDR00_P3 _pdr00.bit._P3 +#define PDR00_P4 _pdr00.bit._P4 +#define PDR00_P5 _pdr00.bit._P5 +#define PDR00_P6 _pdr00.bit._P6 +#define PDR00_P7 _pdr00.bit._P7 +__IO_EXTERN __io PDR01STR _pdr01; +#define PDR01 _pdr01.byte +#define PDR01_P0 _pdr01.bit._P0 +#define PDR01_P1 _pdr01.bit._P1 +#define PDR01_P2 _pdr01.bit._P2 +#define PDR01_P3 _pdr01.bit._P3 +#define PDR01_P4 _pdr01.bit._P4 +#define PDR01_P5 _pdr01.bit._P5 +#define PDR01_P6 _pdr01.bit._P6 +#define PDR01_P7 _pdr01.bit._P7 +__IO_EXTERN __io PDR02STR _pdr02; +#define PDR02 _pdr02.byte +#define PDR02_P0 _pdr02.bit._P0 +#define PDR02_P1 _pdr02.bit._P1 +#define PDR02_P2 _pdr02.bit._P2 +#define PDR02_P3 _pdr02.bit._P3 +#define PDR02_P4 _pdr02.bit._P4 +#define PDR02_P5 _pdr02.bit._P5 +#define PDR02_P6 _pdr02.bit._P6 +#define PDR02_P7 _pdr02.bit._P7 +__IO_EXTERN __io PDR03STR _pdr03; +#define PDR03 _pdr03.byte +#define PDR03_P0 _pdr03.bit._P0 +#define PDR03_P1 _pdr03.bit._P1 +#define PDR03_P2 _pdr03.bit._P2 +#define PDR03_P3 _pdr03.bit._P3 +#define PDR03_P4 _pdr03.bit._P4 +#define PDR03_P5 _pdr03.bit._P5 +#define PDR03_P6 _pdr03.bit._P6 +#define PDR03_P7 _pdr03.bit._P7 +__IO_EXTERN __io PDR04STR _pdr04; +#define PDR04 _pdr04.byte +#define PDR04_P0 _pdr04.bit._P0 +#define PDR04_P1 _pdr04.bit._P1 +#define PDR04_P2 _pdr04.bit._P2 +#define PDR04_P3 _pdr04.bit._P3 +#define PDR04_P4 _pdr04.bit._P4 +#define PDR04_P5 _pdr04.bit._P5 +#define PDR04_P6 _pdr04.bit._P6 +#define PDR04_P7 _pdr04.bit._P7 +__IO_EXTERN __io PDR05STR _pdr05; +#define PDR05 _pdr05.byte +#define PDR05_P0 _pdr05.bit._P0 +#define PDR05_P1 _pdr05.bit._P1 +#define PDR05_P2 _pdr05.bit._P2 +#define PDR05_P3 _pdr05.bit._P3 +#define PDR05_P4 _pdr05.bit._P4 +#define PDR05_P5 _pdr05.bit._P5 +#define PDR05_P6 _pdr05.bit._P6 +#define PDR05_P7 _pdr05.bit._P7 +__IO_EXTERN __io PDR06STR _pdr06; +#define PDR06 _pdr06.byte +#define PDR06_P0 _pdr06.bit._P0 +#define PDR06_P1 _pdr06.bit._P1 +#define PDR06_P2 _pdr06.bit._P2 +#define PDR06_P3 _pdr06.bit._P3 +#define PDR06_P4 _pdr06.bit._P4 +#define PDR06_P5 _pdr06.bit._P5 +#define PDR06_P6 _pdr06.bit._P6 +#define PDR06_P7 _pdr06.bit._P7 +__IO_EXTERN __io PDR07STR _pdr07; +#define PDR07 _pdr07.byte +#define PDR07_P0 _pdr07.bit._P0 +#define PDR07_P1 _pdr07.bit._P1 +#define PDR07_P2 _pdr07.bit._P2 +#define PDR07_P3 _pdr07.bit._P3 +#define PDR07_P4 _pdr07.bit._P4 +#define PDR07_P5 _pdr07.bit._P5 +#define PDR07_P6 _pdr07.bit._P6 +#define PDR07_P7 _pdr07.bit._P7 +__IO_EXTERN __io PDR08STR _pdr08; +#define PDR08 _pdr08.byte +#define PDR08_P0 _pdr08.bit._P0 +#define PDR08_P1 _pdr08.bit._P1 +#define PDR08_P2 _pdr08.bit._P2 +#define PDR08_P3 _pdr08.bit._P3 +#define PDR08_P4 _pdr08.bit._P4 +#define PDR08_P5 _pdr08.bit._P5 +#define PDR08_P6 _pdr08.bit._P6 +#define PDR08_P7 _pdr08.bit._P7 +__IO_EXTERN __io PDR09STR _pdr09; +#define PDR09 _pdr09.byte +#define PDR09_P0 _pdr09.bit._P0 +#define PDR09_P1 _pdr09.bit._P1 +#define PDR09_P2 _pdr09.bit._P2 +#define PDR09_P3 _pdr09.bit._P3 +#define PDR09_P4 _pdr09.bit._P4 +#define PDR09_P5 _pdr09.bit._P5 +#define PDR09_P6 _pdr09.bit._P6 +#define PDR09_P7 _pdr09.bit._P7 +__IO_EXTERN __io PDR10STR _pdr10; +#define PDR10 _pdr10.byte +#define PDR10_P0 _pdr10.bit._P0 +#define PDR10_P1 _pdr10.bit._P1 +__IO_EXTERN __io ADCSSTR _adcs; +#define ADCS _adcs.word +#define ADCS_resv _adcs.bit._resv +#define ADCS_S10 _adcs.bit._S10 +#define ADCS_MD0 _adcs.bit._MD0 +#define ADCS_MD1 _adcs.bit._MD1 +#define ADCS_STRT _adcs.bit._STRT +#define ADCS_STS0 _adcs.bit._STS0 +#define ADCS_STS1 _adcs.bit._STS1 +#define ADCS_PAUS _adcs.bit._PAUS +#define ADCS_INTE _adcs.bit._INTE +#define ADCS_INT _adcs.bit._INT +#define ADCS_BUSY _adcs.bit._BUSY +#define ADCS_MD _adcs.bitc._MD +#define ADCS_STS _adcs.bitc._STS +__IO_EXTERN __io ADCSLSTR _adcsl; +#define ADCSL _adcsl.byte +#define ADCSL_resv _adcsl.bit._resv +#define ADCSL_S10 _adcsl.bit._S10 +#define ADCSL_MD0 _adcsl.bit._MD0 +#define ADCSL_MD1 _adcsl.bit._MD1 +#define ADCSL_MD _adcsl.bitc._MD +__IO_EXTERN __io ADCSHSTR _adcsh; +#define ADCSH _adcsh.byte +#define ADCSH_STRT _adcsh.bit._STRT +#define ADCSH_STS0 _adcsh.bit._STS0 +#define ADCSH_STS1 _adcsh.bit._STS1 +#define ADCSH_PAUS _adcsh.bit._PAUS +#define ADCSH_INTE _adcsh.bit._INTE +#define ADCSH_INT _adcsh.bit._INT +#define ADCSH_BUSY _adcsh.bit._BUSY +#define ADCSH_STS _adcsh.bitc._STS +__IO_EXTERN __io ADCRSTR _adcr; +#define ADCR _adcr.word +#define ADCR_D0 _adcr.bit._D0 +#define ADCR_D1 _adcr.bit._D1 +#define ADCR_D2 _adcr.bit._D2 +#define ADCR_D3 _adcr.bit._D3 +#define ADCR_D4 _adcr.bit._D4 +#define ADCR_D5 _adcr.bit._D5 +#define ADCR_D6 _adcr.bit._D6 +#define ADCR_D7 _adcr.bit._D7 +#define ADCR_D8 _adcr.bit._D8 +#define ADCR_D9 _adcr.bit._D9 +#define ADCR_D _adcr.bitc._D +__IO_EXTERN __io ADCRLSTR _adcrl; +#define ADCRL _adcrl.byte +#define ADCRL_D0 _adcrl.bit._D0 +#define ADCRL_D1 _adcrl.bit._D1 +#define ADCRL_D2 _adcrl.bit._D2 +#define ADCRL_D3 _adcrl.bit._D3 +#define ADCRL_D4 _adcrl.bit._D4 +#define ADCRL_D5 _adcrl.bit._D5 +#define ADCRL_D6 _adcrl.bit._D6 +#define ADCRL_D7 _adcrl.bit._D7 +__IO_EXTERN __io ADCRHSTR _adcrh; +#define ADCRH _adcrh.byte +#define ADCRH_D8 _adcrh.bit._D8 +#define ADCRH_D9 _adcrh.bit._D9 +__IO_EXTERN __io ADSRSTR _adsr; +#define ADSR _adsr.word +#define ADSR_ANE0 _adsr.bit._ANE0 +#define ADSR_ANE1 _adsr.bit._ANE1 +#define ADSR_ANE2 _adsr.bit._ANE2 +#define ADSR_ANE3 _adsr.bit._ANE3 +#define ADSR_ANE4 _adsr.bit._ANE4 +#define ADSR_ANS0 _adsr.bit._ANS0 +#define ADSR_ANS1 _adsr.bit._ANS1 +#define ADSR_ANS2 _adsr.bit._ANS2 +#define ADSR_ANS3 _adsr.bit._ANS3 +#define ADSR_ANS4 _adsr.bit._ANS4 +#define ADSR_CT0 _adsr.bit._CT0 +#define ADSR_CT1 _adsr.bit._CT1 +#define ADSR_CT2 _adsr.bit._CT2 +#define ADSR_ST0 _adsr.bit._ST0 +#define ADSR_ST1 _adsr.bit._ST1 +#define ADSR_ST2 _adsr.bit._ST2 +__IO_EXTERN __io ADECRSTR _adecr; +#define ADECR _adecr.byte +#define ADECR_ADSEL _adecr.bit._ADSEL +#define ADECR_HSEL _adecr.bit._HSEL +#define ADECR_LSEL _adecr.bit._LSEL +__IO_EXTERN __io TCDT0STR _tcdt0; +#define TCDT0 _tcdt0.word +#define TCDT0_T0 _tcdt0.bit._T0 +#define TCDT0_T1 _tcdt0.bit._T1 +#define TCDT0_T2 _tcdt0.bit._T2 +#define TCDT0_T3 _tcdt0.bit._T3 +#define TCDT0_T4 _tcdt0.bit._T4 +#define TCDT0_T5 _tcdt0.bit._T5 +#define TCDT0_T6 _tcdt0.bit._T6 +#define TCDT0_T7 _tcdt0.bit._T7 +#define TCDT0_T8 _tcdt0.bit._T8 +#define TCDT0_T9 _tcdt0.bit._T9 +#define TCDT0_T10 _tcdt0.bit._T10 +#define TCDT0_T11 _tcdt0.bit._T11 +#define TCDT0_T12 _tcdt0.bit._T12 +#define TCDT0_T13 _tcdt0.bit._T13 +#define TCDT0_T14 _tcdt0.bit._T14 +#define TCDT0_T15 _tcdt0.bit._T15 +#define TCDT0_T _tcdt0.bitc._T +__IO_EXTERN __io TCCS0STR _tccs0; +#define TCCS0 _tccs0.word +#define TCCS0_CLK0 _tccs0.bit._CLK0 +#define TCCS0_CLK1 _tccs0.bit._CLK1 +#define TCCS0_CLK2 _tccs0.bit._CLK2 +#define TCCS0_CLR _tccs0.bit._CLR +#define TCCS0_MODE _tccs0.bit._MODE +#define TCCS0_STOP _tccs0.bit._STOP +#define TCCS0_IVFE _tccs0.bit._IVFE +#define TCCS0_IVF _tccs0.bit._IVF +#define TCCS0_FSEL _tccs0.bit._FSEL +#define TCCS0_ECKE _tccs0.bit._ECKE +#define TCCS0_CLK _tccs0.bitc._CLK +__IO_EXTERN __io TCCSL0STR _tccsl0; +#define TCCSL0 _tccsl0.byte +#define TCCSL0_CLK0 _tccsl0.bit._CLK0 +#define TCCSL0_CLK1 _tccsl0.bit._CLK1 +#define TCCSL0_CLK2 _tccsl0.bit._CLK2 +#define TCCSL0_CLR _tccsl0.bit._CLR +#define TCCSL0_MODE _tccsl0.bit._MODE +#define TCCSL0_STOP _tccsl0.bit._STOP +#define TCCSL0_IVFE _tccsl0.bit._IVFE +#define TCCSL0_IVF _tccsl0.bit._IVF +#define TCCSL0_CLK _tccsl0.bitc._CLK +__IO_EXTERN __io TCCSH0STR _tccsh0; +#define TCCSH0 _tccsh0.byte +#define TCCSH0_FSEL _tccsh0.bit._FSEL +#define TCCSH0_ECKE _tccsh0.bit._ECKE +__IO_EXTERN __io TCDT1STR _tcdt1; +#define TCDT1 _tcdt1.word +#define TCDT1_T0 _tcdt1.bit._T0 +#define TCDT1_T1 _tcdt1.bit._T1 +#define TCDT1_T2 _tcdt1.bit._T2 +#define TCDT1_T3 _tcdt1.bit._T3 +#define TCDT1_T4 _tcdt1.bit._T4 +#define TCDT1_T5 _tcdt1.bit._T5 +#define TCDT1_T6 _tcdt1.bit._T6 +#define TCDT1_T7 _tcdt1.bit._T7 +#define TCDT1_T8 _tcdt1.bit._T8 +#define TCDT1_T9 _tcdt1.bit._T9 +#define TCDT1_T10 _tcdt1.bit._T10 +#define TCDT1_T11 _tcdt1.bit._T11 +#define TCDT1_T12 _tcdt1.bit._T12 +#define TCDT1_T13 _tcdt1.bit._T13 +#define TCDT1_T14 _tcdt1.bit._T14 +#define TCDT1_T15 _tcdt1.bit._T15 +#define TCDT1_T _tcdt1.bitc._T +__IO_EXTERN __io TCCS1STR _tccs1; +#define TCCS1 _tccs1.word +#define TCCS1_CLK0 _tccs1.bit._CLK0 +#define TCCS1_CLK1 _tccs1.bit._CLK1 +#define TCCS1_CLK2 _tccs1.bit._CLK2 +#define TCCS1_CLR _tccs1.bit._CLR +#define TCCS1_MODE _tccs1.bit._MODE +#define TCCS1_STOP _tccs1.bit._STOP +#define TCCS1_IVFE _tccs1.bit._IVFE +#define TCCS1_IVF _tccs1.bit._IVF +#define TCCS1_FSEL _tccs1.bit._FSEL +#define TCCS1_ECKE _tccs1.bit._ECKE +#define TCCS1_CLK _tccs1.bitc._CLK +__IO_EXTERN __io TCCSL1STR _tccsl1; +#define TCCSL1 _tccsl1.byte +#define TCCSL1_CLK0 _tccsl1.bit._CLK0 +#define TCCSL1_CLK1 _tccsl1.bit._CLK1 +#define TCCSL1_CLK2 _tccsl1.bit._CLK2 +#define TCCSL1_CLR _tccsl1.bit._CLR +#define TCCSL1_MODE _tccsl1.bit._MODE +#define TCCSL1_STOP _tccsl1.bit._STOP +#define TCCSL1_IVFE _tccsl1.bit._IVFE +#define TCCSL1_IVF _tccsl1.bit._IVF +#define TCCSL1_CLK _tccsl1.bitc._CLK +__IO_EXTERN __io TCCSH1STR _tccsh1; +#define TCCSH1 _tccsh1.byte +#define TCCSH1_FSEL _tccsh1.bit._FSEL +#define TCCSH1_ECKE _tccsh1.bit._ECKE +__IO_EXTERN __io OCS0STR _ocs0; +#define OCS0 _ocs0.byte +#define OCS0_CST0 _ocs0.bit._CST0 +#define OCS0_CST1 _ocs0.bit._CST1 +#define OCS0_ICE0 _ocs0.bit._ICE0 +#define OCS0_ICE1 _ocs0.bit._ICE1 +#define OCS0_ICP0 _ocs0.bit._ICP0 +#define OCS0_ICP1 _ocs0.bit._ICP1 +__IO_EXTERN __io OCS1STR _ocs1; +#define OCS1 _ocs1.byte +#define OCS1_OTD0 _ocs1.bit._OTD0 +#define OCS1_OTD1 _ocs1.bit._OTD1 +#define OCS1_OTE0 _ocs1.bit._OTE0 +#define OCS1_OTE1 _ocs1.bit._OTE1 +#define OCS1_CMOD0 _ocs1.bit._CMOD0 +#define OCS1_CMOD1 _ocs1.bit._CMOD1 +__IO_EXTERN __io OCCP0STR _occp0; +#define OCCP0 _occp0.word +#define OCCP0_C00 _occp0.bit._C00 +#define OCCP0_C01 _occp0.bit._C01 +#define OCCP0_C02 _occp0.bit._C02 +#define OCCP0_C03 _occp0.bit._C03 +#define OCCP0_C04 _occp0.bit._C04 +#define OCCP0_C05 _occp0.bit._C05 +#define OCCP0_C06 _occp0.bit._C06 +#define OCCP0_C07 _occp0.bit._C07 +#define OCCP0_C08 _occp0.bit._C08 +#define OCCP0_C09 _occp0.bit._C09 +#define OCCP0_C10 _occp0.bit._C10 +#define OCCP0_C11 _occp0.bit._C11 +#define OCCP0_C12 _occp0.bit._C12 +#define OCCP0_C13 _occp0.bit._C13 +#define OCCP0_C14 _occp0.bit._C14 +#define OCCP0_C15 _occp0.bit._C15 +#define OCCP0_C0 _occp0.bitc._C0 +__IO_EXTERN __io OCCP1STR _occp1; +#define OCCP1 _occp1.word +#define OCCP1_C00 _occp1.bit._C00 +#define OCCP1_C01 _occp1.bit._C01 +#define OCCP1_C02 _occp1.bit._C02 +#define OCCP1_C03 _occp1.bit._C03 +#define OCCP1_C04 _occp1.bit._C04 +#define OCCP1_C05 _occp1.bit._C05 +#define OCCP1_C06 _occp1.bit._C06 +#define OCCP1_C07 _occp1.bit._C07 +#define OCCP1_C08 _occp1.bit._C08 +#define OCCP1_C09 _occp1.bit._C09 +#define OCCP1_C10 _occp1.bit._C10 +#define OCCP1_C11 _occp1.bit._C11 +#define OCCP1_C12 _occp1.bit._C12 +#define OCCP1_C13 _occp1.bit._C13 +#define OCCP1_C14 _occp1.bit._C14 +#define OCCP1_C15 _occp1.bit._C15 +#define OCCP1_C0 _occp1.bitc._C0 +__IO_EXTERN __io OCS2STR _ocs2; +#define OCS2 _ocs2.byte +#define OCS2_CST2 _ocs2.bit._CST2 +#define OCS2_CST3 _ocs2.bit._CST3 +#define OCS2_ICE2 _ocs2.bit._ICE2 +#define OCS2_ICE3 _ocs2.bit._ICE3 +#define OCS2_ICP2 _ocs2.bit._ICP2 +#define OCS2_ICP3 _ocs2.bit._ICP3 +__IO_EXTERN __io OCS3STR _ocs3; +#define OCS3 _ocs3.byte +#define OCS3_OTD2 _ocs3.bit._OTD2 +#define OCS3_OTD3 _ocs3.bit._OTD3 +#define OCS3_OTE2 _ocs3.bit._OTE2 +#define OCS3_OTE3 _ocs3.bit._OTE3 +#define OCS3_CMOD0 _ocs3.bit._CMOD0 +#define OCS3_CMOD1 _ocs3.bit._CMOD1 +__IO_EXTERN __io OCCP2STR _occp2; +#define OCCP2 _occp2.word +#define OCCP2_C00 _occp2.bit._C00 +#define OCCP2_C01 _occp2.bit._C01 +#define OCCP2_C02 _occp2.bit._C02 +#define OCCP2_C03 _occp2.bit._C03 +#define OCCP2_C04 _occp2.bit._C04 +#define OCCP2_C05 _occp2.bit._C05 +#define OCCP2_C06 _occp2.bit._C06 +#define OCCP2_C07 _occp2.bit._C07 +#define OCCP2_C08 _occp2.bit._C08 +#define OCCP2_C09 _occp2.bit._C09 +#define OCCP2_C10 _occp2.bit._C10 +#define OCCP2_C11 _occp2.bit._C11 +#define OCCP2_C12 _occp2.bit._C12 +#define OCCP2_C13 _occp2.bit._C13 +#define OCCP2_C14 _occp2.bit._C14 +#define OCCP2_C15 _occp2.bit._C15 +#define OCCP2_C0 _occp2.bitc._C0 +__IO_EXTERN __io OCCP3STR _occp3; +#define OCCP3 _occp3.word +#define OCCP3_C00 _occp3.bit._C00 +#define OCCP3_C01 _occp3.bit._C01 +#define OCCP3_C02 _occp3.bit._C02 +#define OCCP3_C03 _occp3.bit._C03 +#define OCCP3_C04 _occp3.bit._C04 +#define OCCP3_C05 _occp3.bit._C05 +#define OCCP3_C06 _occp3.bit._C06 +#define OCCP3_C07 _occp3.bit._C07 +#define OCCP3_C08 _occp3.bit._C08 +#define OCCP3_C09 _occp3.bit._C09 +#define OCCP3_C10 _occp3.bit._C10 +#define OCCP3_C11 _occp3.bit._C11 +#define OCCP3_C12 _occp3.bit._C12 +#define OCCP3_C13 _occp3.bit._C13 +#define OCCP3_C14 _occp3.bit._C14 +#define OCCP3_C15 _occp3.bit._C15 +#define OCCP3_C0 _occp3.bitc._C0 +__IO_EXTERN __io OCS4STR _ocs4; +#define OCS4 _ocs4.byte +#define OCS4_CST4 _ocs4.bit._CST4 +#define OCS4_CST5 _ocs4.bit._CST5 +#define OCS4_ICE4 _ocs4.bit._ICE4 +#define OCS4_ICE5 _ocs4.bit._ICE5 +#define OCS4_ICP4 _ocs4.bit._ICP4 +#define OCS4_ICP5 _ocs4.bit._ICP5 +__IO_EXTERN __io OCS5STR _ocs5; +#define OCS5 _ocs5.byte +#define OCS5_OTD4 _ocs5.bit._OTD4 +#define OCS5_OTD5 _ocs5.bit._OTD5 +#define OCS5_OTE4 _ocs5.bit._OTE4 +#define OCS5_OTE5 _ocs5.bit._OTE5 +#define OCS5_CMOD0 _ocs5.bit._CMOD0 +#define OCS5_CMOD1 _ocs5.bit._CMOD1 +__IO_EXTERN __io OCCP4STR _occp4; +#define OCCP4 _occp4.word +#define OCCP4_C00 _occp4.bit._C00 +#define OCCP4_C01 _occp4.bit._C01 +#define OCCP4_C02 _occp4.bit._C02 +#define OCCP4_C03 _occp4.bit._C03 +#define OCCP4_C04 _occp4.bit._C04 +#define OCCP4_C05 _occp4.bit._C05 +#define OCCP4_C06 _occp4.bit._C06 +#define OCCP4_C07 _occp4.bit._C07 +#define OCCP4_C08 _occp4.bit._C08 +#define OCCP4_C09 _occp4.bit._C09 +#define OCCP4_C10 _occp4.bit._C10 +#define OCCP4_C11 _occp4.bit._C11 +#define OCCP4_C12 _occp4.bit._C12 +#define OCCP4_C13 _occp4.bit._C13 +#define OCCP4_C14 _occp4.bit._C14 +#define OCCP4_C15 _occp4.bit._C15 +#define OCCP4_C0 _occp4.bitc._C0 +__IO_EXTERN __io OCCP5STR _occp5; +#define OCCP5 _occp5.word +#define OCCP5_C00 _occp5.bit._C00 +#define OCCP5_C01 _occp5.bit._C01 +#define OCCP5_C02 _occp5.bit._C02 +#define OCCP5_C03 _occp5.bit._C03 +#define OCCP5_C04 _occp5.bit._C04 +#define OCCP5_C05 _occp5.bit._C05 +#define OCCP5_C06 _occp5.bit._C06 +#define OCCP5_C07 _occp5.bit._C07 +#define OCCP5_C08 _occp5.bit._C08 +#define OCCP5_C09 _occp5.bit._C09 +#define OCCP5_C10 _occp5.bit._C10 +#define OCCP5_C11 _occp5.bit._C11 +#define OCCP5_C12 _occp5.bit._C12 +#define OCCP5_C13 _occp5.bit._C13 +#define OCCP5_C14 _occp5.bit._C14 +#define OCCP5_C15 _occp5.bit._C15 +#define OCCP5_C0 _occp5.bitc._C0 +__IO_EXTERN __io OCS6STR _ocs6; +#define OCS6 _ocs6.byte +#define OCS6_CST6 _ocs6.bit._CST6 +#define OCS6_CST7 _ocs6.bit._CST7 +#define OCS6_ICE6 _ocs6.bit._ICE6 +#define OCS6_ICE7 _ocs6.bit._ICE7 +#define OCS6_ICP6 _ocs6.bit._ICP6 +#define OCS6_ICP7 _ocs6.bit._ICP7 +__IO_EXTERN __io OCS7STR _ocs7; +#define OCS7 _ocs7.byte +#define OCS7_OTD6 _ocs7.bit._OTD6 +#define OCS7_OTD7 _ocs7.bit._OTD7 +#define OCS7_OTE6 _ocs7.bit._OTE6 +#define OCS7_OTE7 _ocs7.bit._OTE7 +#define OCS7_CMOD0 _ocs7.bit._CMOD0 +#define OCS7_CMOD1 _ocs7.bit._CMOD1 +__IO_EXTERN __io OCCP6STR _occp6; +#define OCCP6 _occp6.word +#define OCCP6_C00 _occp6.bit._C00 +#define OCCP6_C01 _occp6.bit._C01 +#define OCCP6_C02 _occp6.bit._C02 +#define OCCP6_C03 _occp6.bit._C03 +#define OCCP6_C04 _occp6.bit._C04 +#define OCCP6_C05 _occp6.bit._C05 +#define OCCP6_C06 _occp6.bit._C06 +#define OCCP6_C07 _occp6.bit._C07 +#define OCCP6_C08 _occp6.bit._C08 +#define OCCP6_C09 _occp6.bit._C09 +#define OCCP6_C10 _occp6.bit._C10 +#define OCCP6_C11 _occp6.bit._C11 +#define OCCP6_C12 _occp6.bit._C12 +#define OCCP6_C13 _occp6.bit._C13 +#define OCCP6_C14 _occp6.bit._C14 +#define OCCP6_C15 _occp6.bit._C15 +#define OCCP6_C0 _occp6.bitc._C0 +__IO_EXTERN __io OCCP7STR _occp7; +#define OCCP7 _occp7.word +#define OCCP7_C00 _occp7.bit._C00 +#define OCCP7_C01 _occp7.bit._C01 +#define OCCP7_C02 _occp7.bit._C02 +#define OCCP7_C03 _occp7.bit._C03 +#define OCCP7_C04 _occp7.bit._C04 +#define OCCP7_C05 _occp7.bit._C05 +#define OCCP7_C06 _occp7.bit._C06 +#define OCCP7_C07 _occp7.bit._C07 +#define OCCP7_C08 _occp7.bit._C08 +#define OCCP7_C09 _occp7.bit._C09 +#define OCCP7_C10 _occp7.bit._C10 +#define OCCP7_C11 _occp7.bit._C11 +#define OCCP7_C12 _occp7.bit._C12 +#define OCCP7_C13 _occp7.bit._C13 +#define OCCP7_C14 _occp7.bit._C14 +#define OCCP7_C15 _occp7.bit._C15 +#define OCCP7_C0 _occp7.bitc._C0 +__IO_EXTERN __io ICS01STR _ics01; +#define ICS01 _ics01.byte +#define ICS01_EG00 _ics01.bit._EG00 +#define ICS01_EG01 _ics01.bit._EG01 +#define ICS01_EG10 _ics01.bit._EG10 +#define ICS01_EG11 _ics01.bit._EG11 +#define ICS01_ICE0 _ics01.bit._ICE0 +#define ICS01_ICE1 _ics01.bit._ICE1 +#define ICS01_ICP0 _ics01.bit._ICP0 +#define ICS01_ICP1 _ics01.bit._ICP1 +#define ICS01_EG0 _ics01.bitc._EG0 +#define ICS01_EG1 _ics01.bitc._EG1 +__IO_EXTERN __io ICE01STR _ice01; +#define ICE01 _ice01.byte +#define ICE01_IEI0 _ice01.bit._IEI0 +#define ICE01_IEI1 _ice01.bit._IEI1 +#define ICE01_ICUS0 _ice01.bit._ICUS0 +#define ICE01_ICUS1 _ice01.bit._ICUS1 +__IO_EXTERN __io IPCP0STR _ipcp0; +#define IPCP0 _ipcp0.word +#define IPCP0_CP00 _ipcp0.bit._CP00 +#define IPCP0_CP01 _ipcp0.bit._CP01 +#define IPCP0_CP02 _ipcp0.bit._CP02 +#define IPCP0_CP03 _ipcp0.bit._CP03 +#define IPCP0_CP04 _ipcp0.bit._CP04 +#define IPCP0_CP05 _ipcp0.bit._CP05 +#define IPCP0_CP06 _ipcp0.bit._CP06 +#define IPCP0_CP07 _ipcp0.bit._CP07 +#define IPCP0_CP08 _ipcp0.bit._CP08 +#define IPCP0_CP09 _ipcp0.bit._CP09 +#define IPCP0_CP10 _ipcp0.bit._CP10 +#define IPCP0_CP11 _ipcp0.bit._CP11 +#define IPCP0_CP12 _ipcp0.bit._CP12 +#define IPCP0_CP13 _ipcp0.bit._CP13 +#define IPCP0_CP14 _ipcp0.bit._CP14 +#define IPCP0_CP15 _ipcp0.bit._CP15 +#define IPCP0_CP0 _ipcp0.bitc._CP0 +__IO_EXTERN __io IPCPL0STR _ipcpl0; +#define IPCPL0 _ipcpl0.byte +#define IPCPL0_CP00 _ipcpl0.bit._CP00 +#define IPCPL0_CP01 _ipcpl0.bit._CP01 +#define IPCPL0_CP02 _ipcpl0.bit._CP02 +#define IPCPL0_CP03 _ipcpl0.bit._CP03 +#define IPCPL0_CP04 _ipcpl0.bit._CP04 +#define IPCPL0_CP05 _ipcpl0.bit._CP05 +#define IPCPL0_CP06 _ipcpl0.bit._CP06 +#define IPCPL0_CP07 _ipcpl0.bit._CP07 +__IO_EXTERN __io IPCPH0STR _ipcph0; +#define IPCPH0 _ipcph0.byte +#define IPCPH0_CP08 _ipcph0.bit._CP08 +#define IPCPH0_CP09 _ipcph0.bit._CP09 +#define IPCPH0_CP10 _ipcph0.bit._CP10 +#define IPCPH0_CP11 _ipcph0.bit._CP11 +#define IPCPH0_CP12 _ipcph0.bit._CP12 +#define IPCPH0_CP13 _ipcph0.bit._CP13 +#define IPCPH0_CP14 _ipcph0.bit._CP14 +#define IPCPH0_CP15 _ipcph0.bit._CP15 +__IO_EXTERN __io IPCP1STR _ipcp1; +#define IPCP1 _ipcp1.word +#define IPCP1_CP00 _ipcp1.bit._CP00 +#define IPCP1_CP01 _ipcp1.bit._CP01 +#define IPCP1_CP02 _ipcp1.bit._CP02 +#define IPCP1_CP03 _ipcp1.bit._CP03 +#define IPCP1_CP04 _ipcp1.bit._CP04 +#define IPCP1_CP05 _ipcp1.bit._CP05 +#define IPCP1_CP06 _ipcp1.bit._CP06 +#define IPCP1_CP07 _ipcp1.bit._CP07 +#define IPCP1_CP08 _ipcp1.bit._CP08 +#define IPCP1_CP09 _ipcp1.bit._CP09 +#define IPCP1_CP10 _ipcp1.bit._CP10 +#define IPCP1_CP11 _ipcp1.bit._CP11 +#define IPCP1_CP12 _ipcp1.bit._CP12 +#define IPCP1_CP13 _ipcp1.bit._CP13 +#define IPCP1_CP14 _ipcp1.bit._CP14 +#define IPCP1_CP15 _ipcp1.bit._CP15 +#define IPCP1_CP0 _ipcp1.bitc._CP0 +__IO_EXTERN __io IPCPL1STR _ipcpl1; +#define IPCPL1 _ipcpl1.byte +#define IPCPL1_CP00 _ipcpl1.bit._CP00 +#define IPCPL1_CP01 _ipcpl1.bit._CP01 +#define IPCPL1_CP02 _ipcpl1.bit._CP02 +#define IPCPL1_CP03 _ipcpl1.bit._CP03 +#define IPCPL1_CP04 _ipcpl1.bit._CP04 +#define IPCPL1_CP05 _ipcpl1.bit._CP05 +#define IPCPL1_CP06 _ipcpl1.bit._CP06 +#define IPCPL1_CP07 _ipcpl1.bit._CP07 +__IO_EXTERN __io IPCPH1STR _ipcph1; +#define IPCPH1 _ipcph1.byte +#define IPCPH1_CP08 _ipcph1.bit._CP08 +#define IPCPH1_CP09 _ipcph1.bit._CP09 +#define IPCPH1_CP10 _ipcph1.bit._CP10 +#define IPCPH1_CP11 _ipcph1.bit._CP11 +#define IPCPH1_CP12 _ipcph1.bit._CP12 +#define IPCPH1_CP13 _ipcph1.bit._CP13 +#define IPCPH1_CP14 _ipcph1.bit._CP14 +#define IPCPH1_CP15 _ipcph1.bit._CP15 +__IO_EXTERN __io ICS23STR _ics23; +#define ICS23 _ics23.byte +#define ICS23_EG20 _ics23.bit._EG20 +#define ICS23_EG21 _ics23.bit._EG21 +#define ICS23_EG30 _ics23.bit._EG30 +#define ICS23_EG31 _ics23.bit._EG31 +#define ICS23_ICE2 _ics23.bit._ICE2 +#define ICS23_ICE3 _ics23.bit._ICE3 +#define ICS23_ICP2 _ics23.bit._ICP2 +#define ICS23_ICP3 _ics23.bit._ICP3 +#define ICS23_EG2 _ics23.bitc._EG2 +#define ICS23_EG3 _ics23.bitc._EG3 +__IO_EXTERN __io ICE23STR _ice23; +#define ICE23 _ice23.byte +#define ICE23_IEI2 _ice23.bit._IEI2 +#define ICE23_IEI3 _ice23.bit._IEI3 +__IO_EXTERN __io IPCP2STR _ipcp2; +#define IPCP2 _ipcp2.word +#define IPCP2_CP00 _ipcp2.bit._CP00 +#define IPCP2_CP01 _ipcp2.bit._CP01 +#define IPCP2_CP02 _ipcp2.bit._CP02 +#define IPCP2_CP03 _ipcp2.bit._CP03 +#define IPCP2_CP04 _ipcp2.bit._CP04 +#define IPCP2_CP05 _ipcp2.bit._CP05 +#define IPCP2_CP06 _ipcp2.bit._CP06 +#define IPCP2_CP07 _ipcp2.bit._CP07 +#define IPCP2_CP08 _ipcp2.bit._CP08 +#define IPCP2_CP09 _ipcp2.bit._CP09 +#define IPCP2_CP10 _ipcp2.bit._CP10 +#define IPCP2_CP11 _ipcp2.bit._CP11 +#define IPCP2_CP12 _ipcp2.bit._CP12 +#define IPCP2_CP13 _ipcp2.bit._CP13 +#define IPCP2_CP14 _ipcp2.bit._CP14 +#define IPCP2_CP15 _ipcp2.bit._CP15 +#define IPCP2_CP0 _ipcp2.bitc._CP0 +__IO_EXTERN __io IPCPL2STR _ipcpl2; +#define IPCPL2 _ipcpl2.byte +#define IPCPL2_CP00 _ipcpl2.bit._CP00 +#define IPCPL2_CP01 _ipcpl2.bit._CP01 +#define IPCPL2_CP02 _ipcpl2.bit._CP02 +#define IPCPL2_CP03 _ipcpl2.bit._CP03 +#define IPCPL2_CP04 _ipcpl2.bit._CP04 +#define IPCPL2_CP05 _ipcpl2.bit._CP05 +#define IPCPL2_CP06 _ipcpl2.bit._CP06 +#define IPCPL2_CP07 _ipcpl2.bit._CP07 +__IO_EXTERN __io IPCPH2STR _ipcph2; +#define IPCPH2 _ipcph2.byte +#define IPCPH2_CP08 _ipcph2.bit._CP08 +#define IPCPH2_CP09 _ipcph2.bit._CP09 +#define IPCPH2_CP10 _ipcph2.bit._CP10 +#define IPCPH2_CP11 _ipcph2.bit._CP11 +#define IPCPH2_CP12 _ipcph2.bit._CP12 +#define IPCPH2_CP13 _ipcph2.bit._CP13 +#define IPCPH2_CP14 _ipcph2.bit._CP14 +#define IPCPH2_CP15 _ipcph2.bit._CP15 +__IO_EXTERN __io IPCP3STR _ipcp3; +#define IPCP3 _ipcp3.word +#define IPCP3_CP00 _ipcp3.bit._CP00 +#define IPCP3_CP01 _ipcp3.bit._CP01 +#define IPCP3_CP02 _ipcp3.bit._CP02 +#define IPCP3_CP03 _ipcp3.bit._CP03 +#define IPCP3_CP04 _ipcp3.bit._CP04 +#define IPCP3_CP05 _ipcp3.bit._CP05 +#define IPCP3_CP06 _ipcp3.bit._CP06 +#define IPCP3_CP07 _ipcp3.bit._CP07 +#define IPCP3_CP08 _ipcp3.bit._CP08 +#define IPCP3_CP09 _ipcp3.bit._CP09 +#define IPCP3_CP10 _ipcp3.bit._CP10 +#define IPCP3_CP11 _ipcp3.bit._CP11 +#define IPCP3_CP12 _ipcp3.bit._CP12 +#define IPCP3_CP13 _ipcp3.bit._CP13 +#define IPCP3_CP14 _ipcp3.bit._CP14 +#define IPCP3_CP15 _ipcp3.bit._CP15 +#define IPCP3_CP0 _ipcp3.bitc._CP0 +__IO_EXTERN __io IPCPL3STR _ipcpl3; +#define IPCPL3 _ipcpl3.byte +#define IPCPL3_CP00 _ipcpl3.bit._CP00 +#define IPCPL3_CP01 _ipcpl3.bit._CP01 +#define IPCPL3_CP02 _ipcpl3.bit._CP02 +#define IPCPL3_CP03 _ipcpl3.bit._CP03 +#define IPCPL3_CP04 _ipcpl3.bit._CP04 +#define IPCPL3_CP05 _ipcpl3.bit._CP05 +#define IPCPL3_CP06 _ipcpl3.bit._CP06 +#define IPCPL3_CP07 _ipcpl3.bit._CP07 +__IO_EXTERN __io IPCPH3STR _ipcph3; +#define IPCPH3 _ipcph3.byte +#define IPCPH3_CP08 _ipcph3.bit._CP08 +#define IPCPH3_CP09 _ipcph3.bit._CP09 +#define IPCPH3_CP10 _ipcph3.bit._CP10 +#define IPCPH3_CP11 _ipcph3.bit._CP11 +#define IPCPH3_CP12 _ipcph3.bit._CP12 +#define IPCPH3_CP13 _ipcph3.bit._CP13 +#define IPCPH3_CP14 _ipcph3.bit._CP14 +#define IPCPH3_CP15 _ipcph3.bit._CP15 +__IO_EXTERN __io ICS45STR _ics45; +#define ICS45 _ics45.byte +#define ICS45_EG40 _ics45.bit._EG40 +#define ICS45_EG41 _ics45.bit._EG41 +#define ICS45_EG50 _ics45.bit._EG50 +#define ICS45_EG51 _ics45.bit._EG51 +#define ICS45_ICE4 _ics45.bit._ICE4 +#define ICS45_ICE5 _ics45.bit._ICE5 +#define ICS45_ICP4 _ics45.bit._ICP4 +#define ICS45_ICP5 _ics45.bit._ICP5 +#define ICS45_EG4 _ics45.bitc._EG4 +#define ICS45_EG5 _ics45.bitc._EG5 +__IO_EXTERN __io ICE45STR _ice45; +#define ICE45 _ice45.byte +#define ICE45_IEI4 _ice45.bit._IEI4 +#define ICE45_IEI5 _ice45.bit._IEI5 +#define ICE45_ICUS4 _ice45.bit._ICUS4 +#define ICE45_ICUS5 _ice45.bit._ICUS5 +__IO_EXTERN __io IPCP4STR _ipcp4; +#define IPCP4 _ipcp4.word +#define IPCP4_CP00 _ipcp4.bit._CP00 +#define IPCP4_CP01 _ipcp4.bit._CP01 +#define IPCP4_CP02 _ipcp4.bit._CP02 +#define IPCP4_CP03 _ipcp4.bit._CP03 +#define IPCP4_CP04 _ipcp4.bit._CP04 +#define IPCP4_CP05 _ipcp4.bit._CP05 +#define IPCP4_CP06 _ipcp4.bit._CP06 +#define IPCP4_CP07 _ipcp4.bit._CP07 +#define IPCP4_CP08 _ipcp4.bit._CP08 +#define IPCP4_CP09 _ipcp4.bit._CP09 +#define IPCP4_CP10 _ipcp4.bit._CP10 +#define IPCP4_CP11 _ipcp4.bit._CP11 +#define IPCP4_CP12 _ipcp4.bit._CP12 +#define IPCP4_CP13 _ipcp4.bit._CP13 +#define IPCP4_CP14 _ipcp4.bit._CP14 +#define IPCP4_CP15 _ipcp4.bit._CP15 +#define IPCP4_CP0 _ipcp4.bitc._CP0 +__IO_EXTERN __io IPCPL4STR _ipcpl4; +#define IPCPL4 _ipcpl4.byte +#define IPCPL4_CP00 _ipcpl4.bit._CP00 +#define IPCPL4_CP01 _ipcpl4.bit._CP01 +#define IPCPL4_CP02 _ipcpl4.bit._CP02 +#define IPCPL4_CP03 _ipcpl4.bit._CP03 +#define IPCPL4_CP04 _ipcpl4.bit._CP04 +#define IPCPL4_CP05 _ipcpl4.bit._CP05 +#define IPCPL4_CP06 _ipcpl4.bit._CP06 +#define IPCPL4_CP07 _ipcpl4.bit._CP07 +__IO_EXTERN __io IPCPH4STR _ipcph4; +#define IPCPH4 _ipcph4.byte +#define IPCPH4_CP08 _ipcph4.bit._CP08 +#define IPCPH4_CP09 _ipcph4.bit._CP09 +#define IPCPH4_CP10 _ipcph4.bit._CP10 +#define IPCPH4_CP11 _ipcph4.bit._CP11 +#define IPCPH4_CP12 _ipcph4.bit._CP12 +#define IPCPH4_CP13 _ipcph4.bit._CP13 +#define IPCPH4_CP14 _ipcph4.bit._CP14 +#define IPCPH4_CP15 _ipcph4.bit._CP15 +__IO_EXTERN __io IPCP5STR _ipcp5; +#define IPCP5 _ipcp5.word +#define IPCP5_CP00 _ipcp5.bit._CP00 +#define IPCP5_CP01 _ipcp5.bit._CP01 +#define IPCP5_CP02 _ipcp5.bit._CP02 +#define IPCP5_CP03 _ipcp5.bit._CP03 +#define IPCP5_CP04 _ipcp5.bit._CP04 +#define IPCP5_CP05 _ipcp5.bit._CP05 +#define IPCP5_CP06 _ipcp5.bit._CP06 +#define IPCP5_CP07 _ipcp5.bit._CP07 +#define IPCP5_CP08 _ipcp5.bit._CP08 +#define IPCP5_CP09 _ipcp5.bit._CP09 +#define IPCP5_CP10 _ipcp5.bit._CP10 +#define IPCP5_CP11 _ipcp5.bit._CP11 +#define IPCP5_CP12 _ipcp5.bit._CP12 +#define IPCP5_CP13 _ipcp5.bit._CP13 +#define IPCP5_CP14 _ipcp5.bit._CP14 +#define IPCP5_CP15 _ipcp5.bit._CP15 +#define IPCP5_CP0 _ipcp5.bitc._CP0 +__IO_EXTERN __io IPCPL5STR _ipcpl5; +#define IPCPL5 _ipcpl5.byte +#define IPCPL5_CP00 _ipcpl5.bit._CP00 +#define IPCPL5_CP01 _ipcpl5.bit._CP01 +#define IPCPL5_CP02 _ipcpl5.bit._CP02 +#define IPCPL5_CP03 _ipcpl5.bit._CP03 +#define IPCPL5_CP04 _ipcpl5.bit._CP04 +#define IPCPL5_CP05 _ipcpl5.bit._CP05 +#define IPCPL5_CP06 _ipcpl5.bit._CP06 +#define IPCPL5_CP07 _ipcpl5.bit._CP07 +__IO_EXTERN __io IPCPH5STR _ipcph5; +#define IPCPH5 _ipcph5.byte +#define IPCPH5_CP08 _ipcph5.bit._CP08 +#define IPCPH5_CP09 _ipcph5.bit._CP09 +#define IPCPH5_CP10 _ipcph5.bit._CP10 +#define IPCPH5_CP11 _ipcph5.bit._CP11 +#define IPCPH5_CP12 _ipcph5.bit._CP12 +#define IPCPH5_CP13 _ipcph5.bit._CP13 +#define IPCPH5_CP14 _ipcph5.bit._CP14 +#define IPCPH5_CP15 _ipcph5.bit._CP15 +__IO_EXTERN __io ICS67STR _ics67; +#define ICS67 _ics67.byte +#define ICS67_EG60 _ics67.bit._EG60 +#define ICS67_EG61 _ics67.bit._EG61 +#define ICS67_EG70 _ics67.bit._EG70 +#define ICS67_EG71 _ics67.bit._EG71 +#define ICS67_ICE6 _ics67.bit._ICE6 +#define ICS67_ICE7 _ics67.bit._ICE7 +#define ICS67_ICP6 _ics67.bit._ICP6 +#define ICS67_ICP7 _ics67.bit._ICP7 +#define ICS67_EG6 _ics67.bitc._EG6 +#define ICS67_EG7 _ics67.bitc._EG7 +__IO_EXTERN __io ICE67STR _ice67; +#define ICE67 _ice67.byte +#define ICE67_IEI6 _ice67.bit._IEI6 +#define ICE67_IEI7 _ice67.bit._IEI7 +#define ICE67_ICUS6 _ice67.bit._ICUS6 +#define ICE67_ICUS7 _ice67.bit._ICUS7 +__IO_EXTERN __io IPCP6STR _ipcp6; +#define IPCP6 _ipcp6.word +#define IPCP6_CP00 _ipcp6.bit._CP00 +#define IPCP6_CP01 _ipcp6.bit._CP01 +#define IPCP6_CP02 _ipcp6.bit._CP02 +#define IPCP6_CP03 _ipcp6.bit._CP03 +#define IPCP6_CP04 _ipcp6.bit._CP04 +#define IPCP6_CP05 _ipcp6.bit._CP05 +#define IPCP6_CP06 _ipcp6.bit._CP06 +#define IPCP6_CP07 _ipcp6.bit._CP07 +#define IPCP6_CP08 _ipcp6.bit._CP08 +#define IPCP6_CP09 _ipcp6.bit._CP09 +#define IPCP6_CP10 _ipcp6.bit._CP10 +#define IPCP6_CP11 _ipcp6.bit._CP11 +#define IPCP6_CP12 _ipcp6.bit._CP12 +#define IPCP6_CP13 _ipcp6.bit._CP13 +#define IPCP6_CP14 _ipcp6.bit._CP14 +#define IPCP6_CP15 _ipcp6.bit._CP15 +#define IPCP6_CP0 _ipcp6.bitc._CP0 +__IO_EXTERN __io IPCPL6STR _ipcpl6; +#define IPCPL6 _ipcpl6.byte +#define IPCPL6_CP00 _ipcpl6.bit._CP00 +#define IPCPL6_CP01 _ipcpl6.bit._CP01 +#define IPCPL6_CP02 _ipcpl6.bit._CP02 +#define IPCPL6_CP03 _ipcpl6.bit._CP03 +#define IPCPL6_CP04 _ipcpl6.bit._CP04 +#define IPCPL6_CP05 _ipcpl6.bit._CP05 +#define IPCPL6_CP06 _ipcpl6.bit._CP06 +#define IPCPL6_CP07 _ipcpl6.bit._CP07 +__IO_EXTERN __io IPCPH6STR _ipcph6; +#define IPCPH6 _ipcph6.byte +#define IPCPH6_CP08 _ipcph6.bit._CP08 +#define IPCPH6_CP09 _ipcph6.bit._CP09 +#define IPCPH6_CP10 _ipcph6.bit._CP10 +#define IPCPH6_CP11 _ipcph6.bit._CP11 +#define IPCPH6_CP12 _ipcph6.bit._CP12 +#define IPCPH6_CP13 _ipcph6.bit._CP13 +#define IPCPH6_CP14 _ipcph6.bit._CP14 +#define IPCPH6_CP15 _ipcph6.bit._CP15 +__IO_EXTERN __io IPCP7STR _ipcp7; +#define IPCP7 _ipcp7.word +#define IPCP7_CP00 _ipcp7.bit._CP00 +#define IPCP7_CP01 _ipcp7.bit._CP01 +#define IPCP7_CP02 _ipcp7.bit._CP02 +#define IPCP7_CP03 _ipcp7.bit._CP03 +#define IPCP7_CP04 _ipcp7.bit._CP04 +#define IPCP7_CP05 _ipcp7.bit._CP05 +#define IPCP7_CP06 _ipcp7.bit._CP06 +#define IPCP7_CP07 _ipcp7.bit._CP07 +#define IPCP7_CP08 _ipcp7.bit._CP08 +#define IPCP7_CP09 _ipcp7.bit._CP09 +#define IPCP7_CP10 _ipcp7.bit._CP10 +#define IPCP7_CP11 _ipcp7.bit._CP11 +#define IPCP7_CP12 _ipcp7.bit._CP12 +#define IPCP7_CP13 _ipcp7.bit._CP13 +#define IPCP7_CP14 _ipcp7.bit._CP14 +#define IPCP7_CP15 _ipcp7.bit._CP15 +#define IPCP7_CP0 _ipcp7.bitc._CP0 +__IO_EXTERN __io IPCPL7STR _ipcpl7; +#define IPCPL7 _ipcpl7.byte +#define IPCPL7_CP00 _ipcpl7.bit._CP00 +#define IPCPL7_CP01 _ipcpl7.bit._CP01 +#define IPCPL7_CP02 _ipcpl7.bit._CP02 +#define IPCPL7_CP03 _ipcpl7.bit._CP03 +#define IPCPL7_CP04 _ipcpl7.bit._CP04 +#define IPCPL7_CP05 _ipcpl7.bit._CP05 +#define IPCPL7_CP06 _ipcpl7.bit._CP06 +#define IPCPL7_CP07 _ipcpl7.bit._CP07 +__IO_EXTERN __io IPCPH7STR _ipcph7; +#define IPCPH7 _ipcph7.byte +#define IPCPH7_CP08 _ipcph7.bit._CP08 +#define IPCPH7_CP09 _ipcph7.bit._CP09 +#define IPCPH7_CP10 _ipcph7.bit._CP10 +#define IPCPH7_CP11 _ipcph7.bit._CP11 +#define IPCPH7_CP12 _ipcph7.bit._CP12 +#define IPCPH7_CP13 _ipcph7.bit._CP13 +#define IPCPH7_CP14 _ipcph7.bit._CP14 +#define IPCPH7_CP15 _ipcph7.bit._CP15 +__IO_EXTERN __io ENIR0STR _enir0; +#define ENIR0 _enir0.byte +#define ENIR0_EN0 _enir0.bit._EN0 +#define ENIR0_EN1 _enir0.bit._EN1 +#define ENIR0_EN2 _enir0.bit._EN2 +#define ENIR0_EN3 _enir0.bit._EN3 +#define ENIR0_EN4 _enir0.bit._EN4 +#define ENIR0_EN5 _enir0.bit._EN5 +#define ENIR0_EN6 _enir0.bit._EN6 +#define ENIR0_EN7 _enir0.bit._EN7 +__IO_EXTERN __io EIRR0STR _eirr0; +#define EIRR0 _eirr0.byte +#define EIRR0_ER0 _eirr0.bit._ER0 +#define EIRR0_ER1 _eirr0.bit._ER1 +#define EIRR0_ER2 _eirr0.bit._ER2 +#define EIRR0_ER3 _eirr0.bit._ER3 +#define EIRR0_ER4 _eirr0.bit._ER4 +#define EIRR0_ER5 _eirr0.bit._ER5 +#define EIRR0_ER6 _eirr0.bit._ER6 +#define EIRR0_ER7 _eirr0.bit._ER7 +__IO_EXTERN __io ELVR0STR _elvr0; +#define ELVR0 _elvr0.word +#define ELVR0_LA0 _elvr0.bit._LA0 +#define ELVR0_LB0 _elvr0.bit._LB0 +#define ELVR0_LA1 _elvr0.bit._LA1 +#define ELVR0_LB1 _elvr0.bit._LB1 +#define ELVR0_LA2 _elvr0.bit._LA2 +#define ELVR0_LB2 _elvr0.bit._LB2 +#define ELVR0_LA3 _elvr0.bit._LA3 +#define ELVR0_LB3 _elvr0.bit._LB3 +#define ELVR0_LA4 _elvr0.bit._LA4 +#define ELVR0_LB4 _elvr0.bit._LB4 +#define ELVR0_LA5 _elvr0.bit._LA5 +#define ELVR0_LB5 _elvr0.bit._LB5 +#define ELVR0_LA6 _elvr0.bit._LA6 +#define ELVR0_LB6 _elvr0.bit._LB6 +#define ELVR0_LA7 _elvr0.bit._LA7 +#define ELVR0_LB7 _elvr0.bit._LB7 +__IO_EXTERN __io ELVRL0STR _elvrl0; +#define ELVRL0 _elvrl0.byte +#define ELVRL0_LA0 _elvrl0.bit._LA0 +#define ELVRL0_LB0 _elvrl0.bit._LB0 +#define ELVRL0_LA1 _elvrl0.bit._LA1 +#define ELVRL0_LB1 _elvrl0.bit._LB1 +#define ELVRL0_LA2 _elvrl0.bit._LA2 +#define ELVRL0_LB2 _elvrl0.bit._LB2 +#define ELVRL0_LA3 _elvrl0.bit._LA3 +#define ELVRL0_LB3 _elvrl0.bit._LB3 +__IO_EXTERN __io ELVRH0STR _elvrh0; +#define ELVRH0 _elvrh0.byte +#define ELVRH0_LA4 _elvrh0.bit._LA4 +#define ELVRH0_LB4 _elvrh0.bit._LB4 +#define ELVRH0_LA5 _elvrh0.bit._LA5 +#define ELVRH0_LB5 _elvrh0.bit._LB5 +#define ELVRH0_LA6 _elvrh0.bit._LA6 +#define ELVRH0_LB6 _elvrh0.bit._LB6 +#define ELVRH0_LA7 _elvrh0.bit._LA7 +#define ELVRH0_LB7 _elvrh0.bit._LB7 +__IO_EXTERN __io ENIR1STR _enir1; +#define ENIR1 _enir1.byte +#define ENIR1_EN8 _enir1.bit._EN8 +#define ENIR1_EN9 _enir1.bit._EN9 +#define ENIR1_EN10 _enir1.bit._EN10 +#define ENIR1_EN11 _enir1.bit._EN11 +#define ENIR1_EN12 _enir1.bit._EN12 +#define ENIR1_EN13 _enir1.bit._EN13 +#define ENIR1_EN14 _enir1.bit._EN14 +#define ENIR1_EN15 _enir1.bit._EN15 +__IO_EXTERN __io EIRR1STR _eirr1; +#define EIRR1 _eirr1.byte +#define EIRR1_ER8 _eirr1.bit._ER8 +#define EIRR1_ER9 _eirr1.bit._ER9 +#define EIRR1_ER10 _eirr1.bit._ER10 +#define EIRR1_ER11 _eirr1.bit._ER11 +#define EIRR1_ER12 _eirr1.bit._ER12 +#define EIRR1_ER13 _eirr1.bit._ER13 +#define EIRR1_ER14 _eirr1.bit._ER14 +#define EIRR1_ER15 _eirr1.bit._ER15 +__IO_EXTERN __io ELVR1STR _elvr1; +#define ELVR1 _elvr1.word +#define ELVR1_LA8 _elvr1.bit._LA8 +#define ELVR1_LB8 _elvr1.bit._LB8 +#define ELVR1_LA9 _elvr1.bit._LA9 +#define ELVR1_LB9 _elvr1.bit._LB9 +#define ELVR1_LA10 _elvr1.bit._LA10 +#define ELVR1_LB10 _elvr1.bit._LB10 +#define ELVR1_LA11 _elvr1.bit._LA11 +#define ELVR1_LB11 _elvr1.bit._LB11 +#define ELVR1_LA12 _elvr1.bit._LA12 +#define ELVR1_LB12 _elvr1.bit._LB12 +#define ELVR1_LA13 _elvr1.bit._LA13 +#define ELVR1_LB13 _elvr1.bit._LB13 +#define ELVR1_LA14 _elvr1.bit._LA14 +#define ELVR1_LB14 _elvr1.bit._LB14 +#define ELVR1_LA15 _elvr1.bit._LA15 +#define ELVR1_LB15 _elvr1.bit._LB15 +__IO_EXTERN __io ELVRL1STR _elvrl1; +#define ELVRL1 _elvrl1.byte +#define ELVRL1_LA8 _elvrl1.bit._LA8 +#define ELVRL1_LB8 _elvrl1.bit._LB8 +#define ELVRL1_LA9 _elvrl1.bit._LA9 +#define ELVRL1_LB9 _elvrl1.bit._LB9 +#define ELVRL1_LA10 _elvrl1.bit._LA10 +#define ELVRL1_LB10 _elvrl1.bit._LB10 +#define ELVRL1_LA11 _elvrl1.bit._LA11 +#define ELVRL1_LB11 _elvrl1.bit._LB11 +__IO_EXTERN __io ELVRH1STR _elvrh1; +#define ELVRH1 _elvrh1.byte +#define ELVRH1_LA12 _elvrh1.bit._LA12 +#define ELVRH1_LB12 _elvrh1.bit._LB12 +#define ELVRH1_LA13 _elvrh1.bit._LA13 +#define ELVRH1_LB13 _elvrh1.bit._LB13 +#define ELVRH1_LA14 _elvrh1.bit._LA14 +#define ELVRH1_LB14 _elvrh1.bit._LB14 +#define ELVRH1_LA15 _elvrh1.bit._LA15 +#define ELVRH1_LB15 _elvrh1.bit._LB15 +__IO_EXTERN __io TMCSR0STR _tmcsr0; +#define TMCSR0 _tmcsr0.word +#define TMCSR0_TRG _tmcsr0.bit._TRG +#define TMCSR0_CNTE _tmcsr0.bit._CNTE +#define TMCSR0_UF _tmcsr0.bit._UF +#define TMCSR0_INTE _tmcsr0.bit._INTE +#define TMCSR0_RELD _tmcsr0.bit._RELD +#define TMCSR0_OUTL _tmcsr0.bit._OUTL +#define TMCSR0_OUTE _tmcsr0.bit._OUTE +#define TMCSR0_MOD0 _tmcsr0.bit._MOD0 +#define TMCSR0_MOD1 _tmcsr0.bit._MOD1 +#define TMCSR0_MOD2 _tmcsr0.bit._MOD2 +#define TMCSR0_CSL0 _tmcsr0.bit._CSL0 +#define TMCSR0_CSL1 _tmcsr0.bit._CSL1 +#define TMCSR0_FSEL _tmcsr0.bit._FSEL +#define TMCSR0_CSL _tmcsr0.bitc._CSL +__IO_EXTERN __io TMCSRL0STR _tmcsrl0; +#define TMCSRL0 _tmcsrl0.byte +#define TMCSRL0_TRG _tmcsrl0.bit._TRG +#define TMCSRL0_CNTE _tmcsrl0.bit._CNTE +#define TMCSRL0_UF _tmcsrl0.bit._UF +#define TMCSRL0_INTE _tmcsrl0.bit._INTE +#define TMCSRL0_RELD _tmcsrl0.bit._RELD +#define TMCSRL0_OUTL _tmcsrl0.bit._OUTL +#define TMCSRL0_OUTE _tmcsrl0.bit._OUTE +#define TMCSRL0_MOD0 _tmcsrl0.bit._MOD0 +__IO_EXTERN __io TMCSRH0STR _tmcsrh0; +#define TMCSRH0 _tmcsrh0.byte +#define TMCSRH0_MOD1 _tmcsrh0.bit._MOD1 +#define TMCSRH0_MOD2 _tmcsrh0.bit._MOD2 +#define TMCSRH0_CSL0 _tmcsrh0.bit._CSL0 +#define TMCSRH0_CSL1 _tmcsrh0.bit._CSL1 +#define TMCSRH0_FSEL _tmcsrh0.bit._FSEL +#define TMCSRH0_CSL _tmcsrh0.bitc._CSL +__IO_EXTERN __io IO_WORD _tmrlr0; +#define TMRLR0 _tmrlr0 +__IO_EXTERN __io IO_WORD _tmr0; +#define TMR0 _tmr0 +__IO_EXTERN __io TMCSR1STR _tmcsr1; +#define TMCSR1 _tmcsr1.word +#define TMCSR1_TRG _tmcsr1.bit._TRG +#define TMCSR1_CNTE _tmcsr1.bit._CNTE +#define TMCSR1_UF _tmcsr1.bit._UF +#define TMCSR1_INTE _tmcsr1.bit._INTE +#define TMCSR1_RELD _tmcsr1.bit._RELD +#define TMCSR1_OUTL _tmcsr1.bit._OUTL +#define TMCSR1_OUTE _tmcsr1.bit._OUTE +#define TMCSR1_MOD0 _tmcsr1.bit._MOD0 +#define TMCSR1_MOD1 _tmcsr1.bit._MOD1 +#define TMCSR1_MOD2 _tmcsr1.bit._MOD2 +#define TMCSR1_CSL0 _tmcsr1.bit._CSL0 +#define TMCSR1_CSL1 _tmcsr1.bit._CSL1 +#define TMCSR1_FSEL _tmcsr1.bit._FSEL +#define TMCSR1_CSL _tmcsr1.bitc._CSL +__IO_EXTERN __io TMCSRL1STR _tmcsrl1; +#define TMCSRL1 _tmcsrl1.byte +#define TMCSRL1_TRG _tmcsrl1.bit._TRG +#define TMCSRL1_CNTE _tmcsrl1.bit._CNTE +#define TMCSRL1_UF _tmcsrl1.bit._UF +#define TMCSRL1_INTE _tmcsrl1.bit._INTE +#define TMCSRL1_RELD _tmcsrl1.bit._RELD +#define TMCSRL1_OUTL _tmcsrl1.bit._OUTL +#define TMCSRL1_OUTE _tmcsrl1.bit._OUTE +#define TMCSRL1_MOD0 _tmcsrl1.bit._MOD0 +__IO_EXTERN __io TMCSRH1STR _tmcsrh1; +#define TMCSRH1 _tmcsrh1.byte +#define TMCSRH1_MOD1 _tmcsrh1.bit._MOD1 +#define TMCSRH1_MOD2 _tmcsrh1.bit._MOD2 +#define TMCSRH1_CSL0 _tmcsrh1.bit._CSL0 +#define TMCSRH1_CSL1 _tmcsrh1.bit._CSL1 +#define TMCSRH1_FSEL _tmcsrh1.bit._FSEL +#define TMCSRH1_CSL _tmcsrh1.bitc._CSL +__IO_EXTERN __io IO_WORD _tmrlr1; +#define TMRLR1 _tmrlr1 +__IO_EXTERN __io IO_WORD _tmr1; +#define TMR1 _tmr1 +__IO_EXTERN __io TMCSR2STR _tmcsr2; +#define TMCSR2 _tmcsr2.word +#define TMCSR2_TRG _tmcsr2.bit._TRG +#define TMCSR2_CNTE _tmcsr2.bit._CNTE +#define TMCSR2_UF _tmcsr2.bit._UF +#define TMCSR2_INTE _tmcsr2.bit._INTE +#define TMCSR2_RELD _tmcsr2.bit._RELD +#define TMCSR2_OUTL _tmcsr2.bit._OUTL +#define TMCSR2_OUTE _tmcsr2.bit._OUTE +#define TMCSR2_MOD0 _tmcsr2.bit._MOD0 +#define TMCSR2_MOD1 _tmcsr2.bit._MOD1 +#define TMCSR2_MOD2 _tmcsr2.bit._MOD2 +#define TMCSR2_CSL0 _tmcsr2.bit._CSL0 +#define TMCSR2_CSL1 _tmcsr2.bit._CSL1 +#define TMCSR2_FSEL _tmcsr2.bit._FSEL +#define TMCSR2_CSL _tmcsr2.bitc._CSL +__IO_EXTERN __io TMCSRL2STR _tmcsrl2; +#define TMCSRL2 _tmcsrl2.byte +#define TMCSRL2_TRG _tmcsrl2.bit._TRG +#define TMCSRL2_CNTE _tmcsrl2.bit._CNTE +#define TMCSRL2_UF _tmcsrl2.bit._UF +#define TMCSRL2_INTE _tmcsrl2.bit._INTE +#define TMCSRL2_RELD _tmcsrl2.bit._RELD +#define TMCSRL2_OUTL _tmcsrl2.bit._OUTL +#define TMCSRL2_OUTE _tmcsrl2.bit._OUTE +#define TMCSRL2_MOD0 _tmcsrl2.bit._MOD0 +__IO_EXTERN __io TMCSRH2STR _tmcsrh2; +#define TMCSRH2 _tmcsrh2.byte +#define TMCSRH2_MOD1 _tmcsrh2.bit._MOD1 +#define TMCSRH2_MOD2 _tmcsrh2.bit._MOD2 +#define TMCSRH2_CSL0 _tmcsrh2.bit._CSL0 +#define TMCSRH2_CSL1 _tmcsrh2.bit._CSL1 +#define TMCSRH2_FSEL _tmcsrh2.bit._FSEL +#define TMCSRH2_CSL _tmcsrh2.bitc._CSL +__IO_EXTERN __io IO_WORD _tmrlr2; +#define TMRLR2 _tmrlr2 +__IO_EXTERN __io IO_WORD _tmr2; +#define TMR2 _tmr2 +__IO_EXTERN __io TMCSR3STR _tmcsr3; +#define TMCSR3 _tmcsr3.word +#define TMCSR3_TRG _tmcsr3.bit._TRG +#define TMCSR3_CNTE _tmcsr3.bit._CNTE +#define TMCSR3_UF _tmcsr3.bit._UF +#define TMCSR3_INTE _tmcsr3.bit._INTE +#define TMCSR3_RELD _tmcsr3.bit._RELD +#define TMCSR3_OUTL _tmcsr3.bit._OUTL +#define TMCSR3_OUTE _tmcsr3.bit._OUTE +#define TMCSR3_MOD0 _tmcsr3.bit._MOD0 +#define TMCSR3_MOD1 _tmcsr3.bit._MOD1 +#define TMCSR3_MOD2 _tmcsr3.bit._MOD2 +#define TMCSR3_CSL0 _tmcsr3.bit._CSL0 +#define TMCSR3_CSL1 _tmcsr3.bit._CSL1 +#define TMCSR3_FSEL _tmcsr3.bit._FSEL +#define TMCSR3_CSL _tmcsr3.bitc._CSL +__IO_EXTERN __io TMCSRL3STR _tmcsrl3; +#define TMCSRL3 _tmcsrl3.byte +#define TMCSRL3_TRG _tmcsrl3.bit._TRG +#define TMCSRL3_CNTE _tmcsrl3.bit._CNTE +#define TMCSRL3_UF _tmcsrl3.bit._UF +#define TMCSRL3_INTE _tmcsrl3.bit._INTE +#define TMCSRL3_RELD _tmcsrl3.bit._RELD +#define TMCSRL3_OUTL _tmcsrl3.bit._OUTL +#define TMCSRL3_OUTE _tmcsrl3.bit._OUTE +#define TMCSRL3_MOD0 _tmcsrl3.bit._MOD0 +__IO_EXTERN __io TMCSRH3STR _tmcsrh3; +#define TMCSRH3 _tmcsrh3.byte +#define TMCSRH3_MOD1 _tmcsrh3.bit._MOD1 +#define TMCSRH3_MOD2 _tmcsrh3.bit._MOD2 +#define TMCSRH3_CSL0 _tmcsrh3.bit._CSL0 +#define TMCSRH3_CSL1 _tmcsrh3.bit._CSL1 +#define TMCSRH3_FSEL _tmcsrh3.bit._FSEL +#define TMCSRH3_CSL _tmcsrh3.bitc._CSL +__IO_EXTERN __io IO_WORD _tmrlr3; +#define TMRLR3 _tmrlr3 +__IO_EXTERN __io IO_WORD _tmr3; +#define TMR3 _tmr3 +__IO_EXTERN __io TMCSR6STR _tmcsr6; +#define TMCSR6 _tmcsr6.word +#define TMCSR6_TRG _tmcsr6.bit._TRG +#define TMCSR6_CNTE _tmcsr6.bit._CNTE +#define TMCSR6_UF _tmcsr6.bit._UF +#define TMCSR6_INTE _tmcsr6.bit._INTE +#define TMCSR6_RELD _tmcsr6.bit._RELD +#define TMCSR6_MOD0 _tmcsr6.bit._MOD0 +#define TMCSR6_MOD1 _tmcsr6.bit._MOD1 +#define TMCSR6_MOD2 _tmcsr6.bit._MOD2 +#define TMCSR6_CSL0 _tmcsr6.bit._CSL0 +#define TMCSR6_CSL1 _tmcsr6.bit._CSL1 +#define TMCSR6_FSEL _tmcsr6.bit._FSEL +#define TMCSR6_CSL _tmcsr6.bitc._CSL +__IO_EXTERN __io TMCSRL6STR _tmcsrl6; +#define TMCSRL6 _tmcsrl6.byte +#define TMCSRL6_TRG _tmcsrl6.bit._TRG +#define TMCSRL6_CNTE _tmcsrl6.bit._CNTE +#define TMCSRL6_UF _tmcsrl6.bit._UF +#define TMCSRL6_INTE _tmcsrl6.bit._INTE +#define TMCSRL6_RELD _tmcsrl6.bit._RELD +#define TMCSRL6_MOD0 _tmcsrl6.bit._MOD0 +__IO_EXTERN __io TMCSRH6STR _tmcsrh6; +#define TMCSRH6 _tmcsrh6.byte +#define TMCSRH6_MOD1 _tmcsrh6.bit._MOD1 +#define TMCSRH6_MOD2 _tmcsrh6.bit._MOD2 +#define TMCSRH6_CSL0 _tmcsrh6.bit._CSL0 +#define TMCSRH6_CSL1 _tmcsrh6.bit._CSL1 +#define TMCSRH6_FSEL _tmcsrh6.bit._FSEL +#define TMCSRH6_CSL _tmcsrh6.bitc._CSL +__IO_EXTERN __io IO_WORD _tmrlr6; +#define TMRLR6 _tmrlr6 +__IO_EXTERN __io IO_WORD _tmr6; +#define TMR6 _tmr6 +__IO_EXTERN __io GCN10STR _gcn10; +#define GCN10 _gcn10.word +#define GCN10_TSEL00 _gcn10.bit._TSEL00 +#define GCN10_TSEL01 _gcn10.bit._TSEL01 +#define GCN10_TSEL02 _gcn10.bit._TSEL02 +#define GCN10_TSEL03 _gcn10.bit._TSEL03 +#define GCN10_TSEL10 _gcn10.bit._TSEL10 +#define GCN10_TSEL11 _gcn10.bit._TSEL11 +#define GCN10_TSEL12 _gcn10.bit._TSEL12 +#define GCN10_TSEL13 _gcn10.bit._TSEL13 +#define GCN10_TSEL20 _gcn10.bit._TSEL20 +#define GCN10_TSEL21 _gcn10.bit._TSEL21 +#define GCN10_TSEL22 _gcn10.bit._TSEL22 +#define GCN10_TSEL23 _gcn10.bit._TSEL23 +#define GCN10_TSEL30 _gcn10.bit._TSEL30 +#define GCN10_TSEL31 _gcn10.bit._TSEL31 +#define GCN10_TSEL32 _gcn10.bit._TSEL32 +#define GCN10_TSEL33 _gcn10.bit._TSEL33 +#define GCN10_TSEL0 _gcn10.bitc._TSEL0 +#define GCN10_TSEL1 _gcn10.bitc._TSEL1 +#define GCN10_TSEL2 _gcn10.bitc._TSEL2 +#define GCN10_TSEL3 _gcn10.bitc._TSEL3 +__IO_EXTERN __io GCN1L0STR _gcn1l0; +#define GCN1L0 _gcn1l0.byte +#define GCN1L0_TSEL00 _gcn1l0.bit._TSEL00 +#define GCN1L0_TSEL01 _gcn1l0.bit._TSEL01 +#define GCN1L0_TSEL02 _gcn1l0.bit._TSEL02 +#define GCN1L0_TSEL03 _gcn1l0.bit._TSEL03 +#define GCN1L0_TSEL10 _gcn1l0.bit._TSEL10 +#define GCN1L0_TSEL11 _gcn1l0.bit._TSEL11 +#define GCN1L0_TSEL12 _gcn1l0.bit._TSEL12 +#define GCN1L0_TSEL13 _gcn1l0.bit._TSEL13 +#define GCN1L0_TSEL0 _gcn1l0.bitc._TSEL0 +#define GCN1L0_TSEL1 _gcn1l0.bitc._TSEL1 +__IO_EXTERN __io GCN1H0STR _gcn1h0; +#define GCN1H0 _gcn1h0.byte +#define GCN1H0_TSEL20 _gcn1h0.bit._TSEL20 +#define GCN1H0_TSEL21 _gcn1h0.bit._TSEL21 +#define GCN1H0_TSEL22 _gcn1h0.bit._TSEL22 +#define GCN1H0_TSEL23 _gcn1h0.bit._TSEL23 +#define GCN1H0_TSEL30 _gcn1h0.bit._TSEL30 +#define GCN1H0_TSEL31 _gcn1h0.bit._TSEL31 +#define GCN1H0_TSEL32 _gcn1h0.bit._TSEL32 +#define GCN1H0_TSEL33 _gcn1h0.bit._TSEL33 +#define GCN1H0_TSEL2 _gcn1h0.bitc._TSEL2 +#define GCN1H0_TSEL3 _gcn1h0.bitc._TSEL3 +__IO_EXTERN __io GCN20STR _gcn20; +#define GCN20 _gcn20.word +#define GCN20_EN0 _gcn20.bit._EN0 +#define GCN20_EN1 _gcn20.bit._EN1 +#define GCN20_EN2 _gcn20.bit._EN2 +#define GCN20_EN3 _gcn20.bit._EN3 +#define GCN20_CKSEL0 _gcn20.bit._CKSEL0 +#define GCN20_CKSEL1 _gcn20.bit._CKSEL1 +#define GCN20_CKSEL2 _gcn20.bit._CKSEL2 +#define GCN20_CKSEL3 _gcn20.bit._CKSEL3 +#define GCN20_EN _gcn20.bitc._EN +#define GCN20_CKSEL _gcn20.bitc._CKSEL +__IO_EXTERN __io GCN2L0STR _gcn2l0; +#define GCN2L0 _gcn2l0.byte +#define GCN2L0_EN0 _gcn2l0.bit._EN0 +#define GCN2L0_EN1 _gcn2l0.bit._EN1 +#define GCN2L0_EN2 _gcn2l0.bit._EN2 +#define GCN2L0_EN3 _gcn2l0.bit._EN3 +#define GCN2L0_EN _gcn2l0.bitc._EN +__IO_EXTERN __io GCN2H0STR _gcn2h0; +#define GCN2H0 _gcn2h0.byte +#define GCN2H0_CKSEL0 _gcn2h0.bit._CKSEL0 +#define GCN2H0_CKSEL1 _gcn2h0.bit._CKSEL1 +#define GCN2H0_CKSEL2 _gcn2h0.bit._CKSEL2 +#define GCN2H0_CKSEL3 _gcn2h0.bit._CKSEL3 +#define GCN2H0_CKSEL _gcn2h0.bitc._CKSEL +__IO_EXTERN __io PTMR0STR _ptmr0; +#define PTMR0 _ptmr0.word +#define PTMR0_D0 _ptmr0.bit._D0 +#define PTMR0_D1 _ptmr0.bit._D1 +#define PTMR0_D2 _ptmr0.bit._D2 +#define PTMR0_D3 _ptmr0.bit._D3 +#define PTMR0_D4 _ptmr0.bit._D4 +#define PTMR0_D5 _ptmr0.bit._D5 +#define PTMR0_D6 _ptmr0.bit._D6 +#define PTMR0_D7 _ptmr0.bit._D7 +#define PTMR0_D8 _ptmr0.bit._D8 +#define PTMR0_D9 _ptmr0.bit._D9 +#define PTMR0_D10 _ptmr0.bit._D10 +#define PTMR0_D11 _ptmr0.bit._D11 +#define PTMR0_D12 _ptmr0.bit._D12 +#define PTMR0_D13 _ptmr0.bit._D13 +#define PTMR0_D14 _ptmr0.bit._D14 +#define PTMR0_D15 _ptmr0.bit._D15 +#define PTMR0_D _ptmr0.bitc._D +__IO_EXTERN __io PCSR0STR _pcsr0; +#define PCSR0 _pcsr0.word +#define PCSR0_D0 _pcsr0.bit._D0 +#define PCSR0_D1 _pcsr0.bit._D1 +#define PCSR0_D2 _pcsr0.bit._D2 +#define PCSR0_D3 _pcsr0.bit._D3 +#define PCSR0_D4 _pcsr0.bit._D4 +#define PCSR0_D5 _pcsr0.bit._D5 +#define PCSR0_D6 _pcsr0.bit._D6 +#define PCSR0_D7 _pcsr0.bit._D7 +#define PCSR0_D8 _pcsr0.bit._D8 +#define PCSR0_D9 _pcsr0.bit._D9 +#define PCSR0_D10 _pcsr0.bit._D10 +#define PCSR0_D11 _pcsr0.bit._D11 +#define PCSR0_D12 _pcsr0.bit._D12 +#define PCSR0_D13 _pcsr0.bit._D13 +#define PCSR0_D14 _pcsr0.bit._D14 +#define PCSR0_D15 _pcsr0.bit._D15 +#define PCSR0_D _pcsr0.bitc._D +__IO_EXTERN __io PDUT0STR _pdut0; +#define PDUT0 _pdut0.word +#define PDUT0_D0 _pdut0.bit._D0 +#define PDUT0_D1 _pdut0.bit._D1 +#define PDUT0_D2 _pdut0.bit._D2 +#define PDUT0_D3 _pdut0.bit._D3 +#define PDUT0_D4 _pdut0.bit._D4 +#define PDUT0_D5 _pdut0.bit._D5 +#define PDUT0_D6 _pdut0.bit._D6 +#define PDUT0_D7 _pdut0.bit._D7 +#define PDUT0_D8 _pdut0.bit._D8 +#define PDUT0_D9 _pdut0.bit._D9 +#define PDUT0_D10 _pdut0.bit._D10 +#define PDUT0_D11 _pdut0.bit._D11 +#define PDUT0_D12 _pdut0.bit._D12 +#define PDUT0_D13 _pdut0.bit._D13 +#define PDUT0_D14 _pdut0.bit._D14 +#define PDUT0_D15 _pdut0.bit._D15 +#define PDUT0_D _pdut0.bitc._D +__IO_EXTERN __io PCN0STR _pcn0; +#define PCN0 _pcn0.word +#define PCN0_OSEL _pcn0.bit._OSEL +#define PCN0_OE _pcn0.bit._OE +#define PCN0_IRS0 _pcn0.bit._IRS0 +#define PCN0_IRS1 _pcn0.bit._IRS1 +#define PCN0_IRQF _pcn0.bit._IRQF +#define PCN0_IREN _pcn0.bit._IREN +#define PCN0_EGS0 _pcn0.bit._EGS0 +#define PCN0_EGS1 _pcn0.bit._EGS1 +#define PCN0_PGMS _pcn0.bit._PGMS +#define PCN0_CKS0 _pcn0.bit._CKS0 +#define PCN0_CKS1 _pcn0.bit._CKS1 +#define PCN0_RTRG _pcn0.bit._RTRG +#define PCN0_MDSE _pcn0.bit._MDSE +#define PCN0_STGR _pcn0.bit._STGR +#define PCN0_CNTE _pcn0.bit._CNTE +#define PCN0_IRS _pcn0.bitc._IRS +#define PCN0_EGS _pcn0.bitc._EGS +#define PCN0_CKS _pcn0.bitc._CKS +__IO_EXTERN __io PCNL0STR _pcnl0; +#define PCNL0 _pcnl0.byte +#define PCNL0_OSEL _pcnl0.bit._OSEL +#define PCNL0_OE _pcnl0.bit._OE +#define PCNL0_IRS0 _pcnl0.bit._IRS0 +#define PCNL0_IRS1 _pcnl0.bit._IRS1 +#define PCNL0_IRQF _pcnl0.bit._IRQF +#define PCNL0_IREN _pcnl0.bit._IREN +#define PCNL0_EGS0 _pcnl0.bit._EGS0 +#define PCNL0_EGS1 _pcnl0.bit._EGS1 +#define PCNL0_IRS _pcnl0.bitc._IRS +#define PCNL0_EGS _pcnl0.bitc._EGS +__IO_EXTERN __io PCNH0STR _pcnh0; +#define PCNH0 _pcnh0.byte +#define PCNH0_PGMS _pcnh0.bit._PGMS +#define PCNH0_CKS0 _pcnh0.bit._CKS0 +#define PCNH0_CKS1 _pcnh0.bit._CKS1 +#define PCNH0_RTRG _pcnh0.bit._RTRG +#define PCNH0_MDSE _pcnh0.bit._MDSE +#define PCNH0_STGR _pcnh0.bit._STGR +#define PCNH0_CNTE _pcnh0.bit._CNTE +#define PCNH0_CKS _pcnh0.bitc._CKS +__IO_EXTERN __io PTMR1STR _ptmr1; +#define PTMR1 _ptmr1.word +#define PTMR1_D0 _ptmr1.bit._D0 +#define PTMR1_D1 _ptmr1.bit._D1 +#define PTMR1_D2 _ptmr1.bit._D2 +#define PTMR1_D3 _ptmr1.bit._D3 +#define PTMR1_D4 _ptmr1.bit._D4 +#define PTMR1_D5 _ptmr1.bit._D5 +#define PTMR1_D6 _ptmr1.bit._D6 +#define PTMR1_D7 _ptmr1.bit._D7 +#define PTMR1_D8 _ptmr1.bit._D8 +#define PTMR1_D9 _ptmr1.bit._D9 +#define PTMR1_D10 _ptmr1.bit._D10 +#define PTMR1_D11 _ptmr1.bit._D11 +#define PTMR1_D12 _ptmr1.bit._D12 +#define PTMR1_D13 _ptmr1.bit._D13 +#define PTMR1_D14 _ptmr1.bit._D14 +#define PTMR1_D15 _ptmr1.bit._D15 +#define PTMR1_D _ptmr1.bitc._D +__IO_EXTERN __io PCSR1STR _pcsr1; +#define PCSR1 _pcsr1.word +#define PCSR1_D0 _pcsr1.bit._D0 +#define PCSR1_D1 _pcsr1.bit._D1 +#define PCSR1_D2 _pcsr1.bit._D2 +#define PCSR1_D3 _pcsr1.bit._D3 +#define PCSR1_D4 _pcsr1.bit._D4 +#define PCSR1_D5 _pcsr1.bit._D5 +#define PCSR1_D6 _pcsr1.bit._D6 +#define PCSR1_D7 _pcsr1.bit._D7 +#define PCSR1_D8 _pcsr1.bit._D8 +#define PCSR1_D9 _pcsr1.bit._D9 +#define PCSR1_D10 _pcsr1.bit._D10 +#define PCSR1_D11 _pcsr1.bit._D11 +#define PCSR1_D12 _pcsr1.bit._D12 +#define PCSR1_D13 _pcsr1.bit._D13 +#define PCSR1_D14 _pcsr1.bit._D14 +#define PCSR1_D15 _pcsr1.bit._D15 +#define PCSR1_D _pcsr1.bitc._D +__IO_EXTERN __io PDUT1STR _pdut1; +#define PDUT1 _pdut1.word +#define PDUT1_D0 _pdut1.bit._D0 +#define PDUT1_D1 _pdut1.bit._D1 +#define PDUT1_D2 _pdut1.bit._D2 +#define PDUT1_D3 _pdut1.bit._D3 +#define PDUT1_D4 _pdut1.bit._D4 +#define PDUT1_D5 _pdut1.bit._D5 +#define PDUT1_D6 _pdut1.bit._D6 +#define PDUT1_D7 _pdut1.bit._D7 +#define PDUT1_D8 _pdut1.bit._D8 +#define PDUT1_D9 _pdut1.bit._D9 +#define PDUT1_D10 _pdut1.bit._D10 +#define PDUT1_D11 _pdut1.bit._D11 +#define PDUT1_D12 _pdut1.bit._D12 +#define PDUT1_D13 _pdut1.bit._D13 +#define PDUT1_D14 _pdut1.bit._D14 +#define PDUT1_D15 _pdut1.bit._D15 +#define PDUT1_D _pdut1.bitc._D +__IO_EXTERN __io PCN1STR _pcn1; +#define PCN1 _pcn1.word +#define PCN1_OSEL _pcn1.bit._OSEL +#define PCN1_OE _pcn1.bit._OE +#define PCN1_IRS0 _pcn1.bit._IRS0 +#define PCN1_IRS1 _pcn1.bit._IRS1 +#define PCN1_IRQF _pcn1.bit._IRQF +#define PCN1_IREN _pcn1.bit._IREN +#define PCN1_EGS0 _pcn1.bit._EGS0 +#define PCN1_EGS1 _pcn1.bit._EGS1 +#define PCN1_PGMS _pcn1.bit._PGMS +#define PCN1_CKS0 _pcn1.bit._CKS0 +#define PCN1_CKS1 _pcn1.bit._CKS1 +#define PCN1_RTRG _pcn1.bit._RTRG +#define PCN1_MDSE _pcn1.bit._MDSE +#define PCN1_STGR _pcn1.bit._STGR +#define PCN1_CNTE _pcn1.bit._CNTE +#define PCN1_IRS _pcn1.bitc._IRS +#define PCN1_EGS _pcn1.bitc._EGS +#define PCN1_CKS _pcn1.bitc._CKS +__IO_EXTERN __io PCNL1STR _pcnl1; +#define PCNL1 _pcnl1.byte +#define PCNL1_OSEL _pcnl1.bit._OSEL +#define PCNL1_OE _pcnl1.bit._OE +#define PCNL1_IRS0 _pcnl1.bit._IRS0 +#define PCNL1_IRS1 _pcnl1.bit._IRS1 +#define PCNL1_IRQF _pcnl1.bit._IRQF +#define PCNL1_IREN _pcnl1.bit._IREN +#define PCNL1_EGS0 _pcnl1.bit._EGS0 +#define PCNL1_EGS1 _pcnl1.bit._EGS1 +#define PCNL1_IRS _pcnl1.bitc._IRS +#define PCNL1_EGS _pcnl1.bitc._EGS +__IO_EXTERN __io PCNH1STR _pcnh1; +#define PCNH1 _pcnh1.byte +#define PCNH1_PGMS _pcnh1.bit._PGMS +#define PCNH1_CKS0 _pcnh1.bit._CKS0 +#define PCNH1_CKS1 _pcnh1.bit._CKS1 +#define PCNH1_RTRG _pcnh1.bit._RTRG +#define PCNH1_MDSE _pcnh1.bit._MDSE +#define PCNH1_STGR _pcnh1.bit._STGR +#define PCNH1_CNTE _pcnh1.bit._CNTE +#define PCNH1_CKS _pcnh1.bitc._CKS +__IO_EXTERN __io PTMR2STR _ptmr2; +#define PTMR2 _ptmr2.word +#define PTMR2_D0 _ptmr2.bit._D0 +#define PTMR2_D1 _ptmr2.bit._D1 +#define PTMR2_D2 _ptmr2.bit._D2 +#define PTMR2_D3 _ptmr2.bit._D3 +#define PTMR2_D4 _ptmr2.bit._D4 +#define PTMR2_D5 _ptmr2.bit._D5 +#define PTMR2_D6 _ptmr2.bit._D6 +#define PTMR2_D7 _ptmr2.bit._D7 +#define PTMR2_D8 _ptmr2.bit._D8 +#define PTMR2_D9 _ptmr2.bit._D9 +#define PTMR2_D10 _ptmr2.bit._D10 +#define PTMR2_D11 _ptmr2.bit._D11 +#define PTMR2_D12 _ptmr2.bit._D12 +#define PTMR2_D13 _ptmr2.bit._D13 +#define PTMR2_D14 _ptmr2.bit._D14 +#define PTMR2_D15 _ptmr2.bit._D15 +#define PTMR2_D _ptmr2.bitc._D +__IO_EXTERN __io PCSR2STR _pcsr2; +#define PCSR2 _pcsr2.word +#define PCSR2_D0 _pcsr2.bit._D0 +#define PCSR2_D1 _pcsr2.bit._D1 +#define PCSR2_D2 _pcsr2.bit._D2 +#define PCSR2_D3 _pcsr2.bit._D3 +#define PCSR2_D4 _pcsr2.bit._D4 +#define PCSR2_D5 _pcsr2.bit._D5 +#define PCSR2_D6 _pcsr2.bit._D6 +#define PCSR2_D7 _pcsr2.bit._D7 +#define PCSR2_D8 _pcsr2.bit._D8 +#define PCSR2_D9 _pcsr2.bit._D9 +#define PCSR2_D10 _pcsr2.bit._D10 +#define PCSR2_D11 _pcsr2.bit._D11 +#define PCSR2_D12 _pcsr2.bit._D12 +#define PCSR2_D13 _pcsr2.bit._D13 +#define PCSR2_D14 _pcsr2.bit._D14 +#define PCSR2_D15 _pcsr2.bit._D15 +#define PCSR2_D _pcsr2.bitc._D +__IO_EXTERN __io PDUT2STR _pdut2; +#define PDUT2 _pdut2.word +#define PDUT2_D0 _pdut2.bit._D0 +#define PDUT2_D1 _pdut2.bit._D1 +#define PDUT2_D2 _pdut2.bit._D2 +#define PDUT2_D3 _pdut2.bit._D3 +#define PDUT2_D4 _pdut2.bit._D4 +#define PDUT2_D5 _pdut2.bit._D5 +#define PDUT2_D6 _pdut2.bit._D6 +#define PDUT2_D7 _pdut2.bit._D7 +#define PDUT2_D8 _pdut2.bit._D8 +#define PDUT2_D9 _pdut2.bit._D9 +#define PDUT2_D10 _pdut2.bit._D10 +#define PDUT2_D11 _pdut2.bit._D11 +#define PDUT2_D12 _pdut2.bit._D12 +#define PDUT2_D13 _pdut2.bit._D13 +#define PDUT2_D14 _pdut2.bit._D14 +#define PDUT2_D15 _pdut2.bit._D15 +#define PDUT2_D _pdut2.bitc._D +__IO_EXTERN __io PCN2STR _pcn2; +#define PCN2 _pcn2.word +#define PCN2_OSEL _pcn2.bit._OSEL +#define PCN2_OE _pcn2.bit._OE +#define PCN2_IRS0 _pcn2.bit._IRS0 +#define PCN2_IRS1 _pcn2.bit._IRS1 +#define PCN2_IRQF _pcn2.bit._IRQF +#define PCN2_IREN _pcn2.bit._IREN +#define PCN2_EGS0 _pcn2.bit._EGS0 +#define PCN2_EGS1 _pcn2.bit._EGS1 +#define PCN2_PGMS _pcn2.bit._PGMS +#define PCN2_CKS0 _pcn2.bit._CKS0 +#define PCN2_CKS1 _pcn2.bit._CKS1 +#define PCN2_RTRG _pcn2.bit._RTRG +#define PCN2_MDSE _pcn2.bit._MDSE +#define PCN2_STGR _pcn2.bit._STGR +#define PCN2_CNTE _pcn2.bit._CNTE +#define PCN2_IRS _pcn2.bitc._IRS +#define PCN2_EGS _pcn2.bitc._EGS +#define PCN2_CKS _pcn2.bitc._CKS +__IO_EXTERN __io PCNL2STR _pcnl2; +#define PCNL2 _pcnl2.byte +#define PCNL2_OSEL _pcnl2.bit._OSEL +#define PCNL2_OE _pcnl2.bit._OE +#define PCNL2_IRS0 _pcnl2.bit._IRS0 +#define PCNL2_IRS1 _pcnl2.bit._IRS1 +#define PCNL2_IRQF _pcnl2.bit._IRQF +#define PCNL2_IREN _pcnl2.bit._IREN +#define PCNL2_EGS0 _pcnl2.bit._EGS0 +#define PCNL2_EGS1 _pcnl2.bit._EGS1 +#define PCNL2_IRS _pcnl2.bitc._IRS +#define PCNL2_EGS _pcnl2.bitc._EGS +__IO_EXTERN __io PCNH2STR _pcnh2; +#define PCNH2 _pcnh2.byte +#define PCNH2_PGMS _pcnh2.bit._PGMS +#define PCNH2_CKS0 _pcnh2.bit._CKS0 +#define PCNH2_CKS1 _pcnh2.bit._CKS1 +#define PCNH2_RTRG _pcnh2.bit._RTRG +#define PCNH2_MDSE _pcnh2.bit._MDSE +#define PCNH2_STGR _pcnh2.bit._STGR +#define PCNH2_CNTE _pcnh2.bit._CNTE +#define PCNH2_CKS _pcnh2.bitc._CKS +__IO_EXTERN __io PTMR3STR _ptmr3; +#define PTMR3 _ptmr3.word +#define PTMR3_D0 _ptmr3.bit._D0 +#define PTMR3_D1 _ptmr3.bit._D1 +#define PTMR3_D2 _ptmr3.bit._D2 +#define PTMR3_D3 _ptmr3.bit._D3 +#define PTMR3_D4 _ptmr3.bit._D4 +#define PTMR3_D5 _ptmr3.bit._D5 +#define PTMR3_D6 _ptmr3.bit._D6 +#define PTMR3_D7 _ptmr3.bit._D7 +#define PTMR3_D8 _ptmr3.bit._D8 +#define PTMR3_D9 _ptmr3.bit._D9 +#define PTMR3_D10 _ptmr3.bit._D10 +#define PTMR3_D11 _ptmr3.bit._D11 +#define PTMR3_D12 _ptmr3.bit._D12 +#define PTMR3_D13 _ptmr3.bit._D13 +#define PTMR3_D14 _ptmr3.bit._D14 +#define PTMR3_D15 _ptmr3.bit._D15 +#define PTMR3_D _ptmr3.bitc._D +__IO_EXTERN __io PCSR3STR _pcsr3; +#define PCSR3 _pcsr3.word +#define PCSR3_D0 _pcsr3.bit._D0 +#define PCSR3_D1 _pcsr3.bit._D1 +#define PCSR3_D2 _pcsr3.bit._D2 +#define PCSR3_D3 _pcsr3.bit._D3 +#define PCSR3_D4 _pcsr3.bit._D4 +#define PCSR3_D5 _pcsr3.bit._D5 +#define PCSR3_D6 _pcsr3.bit._D6 +#define PCSR3_D7 _pcsr3.bit._D7 +#define PCSR3_D8 _pcsr3.bit._D8 +#define PCSR3_D9 _pcsr3.bit._D9 +#define PCSR3_D10 _pcsr3.bit._D10 +#define PCSR3_D11 _pcsr3.bit._D11 +#define PCSR3_D12 _pcsr3.bit._D12 +#define PCSR3_D13 _pcsr3.bit._D13 +#define PCSR3_D14 _pcsr3.bit._D14 +#define PCSR3_D15 _pcsr3.bit._D15 +#define PCSR3_D _pcsr3.bitc._D +__IO_EXTERN __io PDUT3STR _pdut3; +#define PDUT3 _pdut3.word +#define PDUT3_D0 _pdut3.bit._D0 +#define PDUT3_D1 _pdut3.bit._D1 +#define PDUT3_D2 _pdut3.bit._D2 +#define PDUT3_D3 _pdut3.bit._D3 +#define PDUT3_D4 _pdut3.bit._D4 +#define PDUT3_D5 _pdut3.bit._D5 +#define PDUT3_D6 _pdut3.bit._D6 +#define PDUT3_D7 _pdut3.bit._D7 +#define PDUT3_D8 _pdut3.bit._D8 +#define PDUT3_D9 _pdut3.bit._D9 +#define PDUT3_D10 _pdut3.bit._D10 +#define PDUT3_D11 _pdut3.bit._D11 +#define PDUT3_D12 _pdut3.bit._D12 +#define PDUT3_D13 _pdut3.bit._D13 +#define PDUT3_D14 _pdut3.bit._D14 +#define PDUT3_D15 _pdut3.bit._D15 +#define PDUT3_D _pdut3.bitc._D +__IO_EXTERN __io PCN3STR _pcn3; +#define PCN3 _pcn3.word +#define PCN3_OSEL _pcn3.bit._OSEL +#define PCN3_OE _pcn3.bit._OE +#define PCN3_IRS0 _pcn3.bit._IRS0 +#define PCN3_IRS1 _pcn3.bit._IRS1 +#define PCN3_IRQF _pcn3.bit._IRQF +#define PCN3_IREN _pcn3.bit._IREN +#define PCN3_EGS0 _pcn3.bit._EGS0 +#define PCN3_EGS1 _pcn3.bit._EGS1 +#define PCN3_PGMS _pcn3.bit._PGMS +#define PCN3_CKS0 _pcn3.bit._CKS0 +#define PCN3_CKS1 _pcn3.bit._CKS1 +#define PCN3_RTRG _pcn3.bit._RTRG +#define PCN3_MDSE _pcn3.bit._MDSE +#define PCN3_STGR _pcn3.bit._STGR +#define PCN3_CNTE _pcn3.bit._CNTE +#define PCN3_IRS _pcn3.bitc._IRS +#define PCN3_EGS _pcn3.bitc._EGS +#define PCN3_CKS _pcn3.bitc._CKS +__IO_EXTERN __io PCNL3STR _pcnl3; +#define PCNL3 _pcnl3.byte +#define PCNL3_OSEL _pcnl3.bit._OSEL +#define PCNL3_OE _pcnl3.bit._OE +#define PCNL3_IRS0 _pcnl3.bit._IRS0 +#define PCNL3_IRS1 _pcnl3.bit._IRS1 +#define PCNL3_IRQF _pcnl3.bit._IRQF +#define PCNL3_IREN _pcnl3.bit._IREN +#define PCNL3_EGS0 _pcnl3.bit._EGS0 +#define PCNL3_EGS1 _pcnl3.bit._EGS1 +#define PCNL3_IRS _pcnl3.bitc._IRS +#define PCNL3_EGS _pcnl3.bitc._EGS +__IO_EXTERN __io PCNH3STR _pcnh3; +#define PCNH3 _pcnh3.byte +#define PCNH3_PGMS _pcnh3.bit._PGMS +#define PCNH3_CKS0 _pcnh3.bit._CKS0 +#define PCNH3_CKS1 _pcnh3.bit._CKS1 +#define PCNH3_RTRG _pcnh3.bit._RTRG +#define PCNH3_MDSE _pcnh3.bit._MDSE +#define PCNH3_STGR _pcnh3.bit._STGR +#define PCNH3_CNTE _pcnh3.bit._CNTE +#define PCNH3_CKS _pcnh3.bitc._CKS +__IO_EXTERN __io GCN11STR _gcn11; +#define GCN11 _gcn11.word +#define GCN11_TSEL00 _gcn11.bit._TSEL00 +#define GCN11_TSEL01 _gcn11.bit._TSEL01 +#define GCN11_TSEL02 _gcn11.bit._TSEL02 +#define GCN11_TSEL03 _gcn11.bit._TSEL03 +#define GCN11_TSEL10 _gcn11.bit._TSEL10 +#define GCN11_TSEL11 _gcn11.bit._TSEL11 +#define GCN11_TSEL12 _gcn11.bit._TSEL12 +#define GCN11_TSEL13 _gcn11.bit._TSEL13 +#define GCN11_TSEL20 _gcn11.bit._TSEL20 +#define GCN11_TSEL21 _gcn11.bit._TSEL21 +#define GCN11_TSEL22 _gcn11.bit._TSEL22 +#define GCN11_TSEL23 _gcn11.bit._TSEL23 +#define GCN11_TSEL30 _gcn11.bit._TSEL30 +#define GCN11_TSEL31 _gcn11.bit._TSEL31 +#define GCN11_TSEL32 _gcn11.bit._TSEL32 +#define GCN11_TSEL33 _gcn11.bit._TSEL33 +#define GCN11_TSEL0 _gcn11.bitc._TSEL0 +#define GCN11_TSEL1 _gcn11.bitc._TSEL1 +#define GCN11_TSEL2 _gcn11.bitc._TSEL2 +#define GCN11_TSEL3 _gcn11.bitc._TSEL3 +__IO_EXTERN __io GCN1L1STR _gcn1l1; +#define GCN1L1 _gcn1l1.byte +#define GCN1L1_TSEL00 _gcn1l1.bit._TSEL00 +#define GCN1L1_TSEL01 _gcn1l1.bit._TSEL01 +#define GCN1L1_TSEL02 _gcn1l1.bit._TSEL02 +#define GCN1L1_TSEL03 _gcn1l1.bit._TSEL03 +#define GCN1L1_TSEL10 _gcn1l1.bit._TSEL10 +#define GCN1L1_TSEL11 _gcn1l1.bit._TSEL11 +#define GCN1L1_TSEL12 _gcn1l1.bit._TSEL12 +#define GCN1L1_TSEL13 _gcn1l1.bit._TSEL13 +#define GCN1L1_TSEL0 _gcn1l1.bitc._TSEL0 +#define GCN1L1_TSEL1 _gcn1l1.bitc._TSEL1 +__IO_EXTERN __io GCN1H1STR _gcn1h1; +#define GCN1H1 _gcn1h1.byte +#define GCN1H1_TSEL20 _gcn1h1.bit._TSEL20 +#define GCN1H1_TSEL21 _gcn1h1.bit._TSEL21 +#define GCN1H1_TSEL22 _gcn1h1.bit._TSEL22 +#define GCN1H1_TSEL23 _gcn1h1.bit._TSEL23 +#define GCN1H1_TSEL30 _gcn1h1.bit._TSEL30 +#define GCN1H1_TSEL31 _gcn1h1.bit._TSEL31 +#define GCN1H1_TSEL32 _gcn1h1.bit._TSEL32 +#define GCN1H1_TSEL33 _gcn1h1.bit._TSEL33 +#define GCN1H1_TSEL2 _gcn1h1.bitc._TSEL2 +#define GCN1H1_TSEL3 _gcn1h1.bitc._TSEL3 +__IO_EXTERN __io GCN21STR _gcn21; +#define GCN21 _gcn21.word +#define GCN21_EN0 _gcn21.bit._EN0 +#define GCN21_EN1 _gcn21.bit._EN1 +#define GCN21_EN2 _gcn21.bit._EN2 +#define GCN21_EN3 _gcn21.bit._EN3 +#define GCN21_CKSEL0 _gcn21.bit._CKSEL0 +#define GCN21_CKSEL1 _gcn21.bit._CKSEL1 +#define GCN21_CKSEL2 _gcn21.bit._CKSEL2 +#define GCN21_CKSEL3 _gcn21.bit._CKSEL3 +#define GCN21_CKSEL _gcn21.bitc._CKSEL +__IO_EXTERN __io GCN2L1STR _gcn2l1; +#define GCN2L1 _gcn2l1.byte +#define GCN2L1_EN0 _gcn2l1.bit._EN0 +#define GCN2L1_EN1 _gcn2l1.bit._EN1 +#define GCN2L1_EN2 _gcn2l1.bit._EN2 +#define GCN2L1_EN3 _gcn2l1.bit._EN3 +__IO_EXTERN __io GCN2H1STR _gcn2h1; +#define GCN2H1 _gcn2h1.byte +#define GCN2H1_CKSEL0 _gcn2h1.bit._CKSEL0 +#define GCN2H1_CKSEL1 _gcn2h1.bit._CKSEL1 +#define GCN2H1_CKSEL2 _gcn2h1.bit._CKSEL2 +#define GCN2H1_CKSEL3 _gcn2h1.bit._CKSEL3 +#define GCN2H1_CKSEL _gcn2h1.bitc._CKSEL +__IO_EXTERN __io PTMR4STR _ptmr4; +#define PTMR4 _ptmr4.word +#define PTMR4_D0 _ptmr4.bit._D0 +#define PTMR4_D1 _ptmr4.bit._D1 +#define PTMR4_D2 _ptmr4.bit._D2 +#define PTMR4_D3 _ptmr4.bit._D3 +#define PTMR4_D4 _ptmr4.bit._D4 +#define PTMR4_D5 _ptmr4.bit._D5 +#define PTMR4_D6 _ptmr4.bit._D6 +#define PTMR4_D7 _ptmr4.bit._D7 +#define PTMR4_D8 _ptmr4.bit._D8 +#define PTMR4_D9 _ptmr4.bit._D9 +#define PTMR4_D10 _ptmr4.bit._D10 +#define PTMR4_D11 _ptmr4.bit._D11 +#define PTMR4_D12 _ptmr4.bit._D12 +#define PTMR4_D13 _ptmr4.bit._D13 +#define PTMR4_D14 _ptmr4.bit._D14 +#define PTMR4_D15 _ptmr4.bit._D15 +#define PTMR4_D _ptmr4.bitc._D +__IO_EXTERN __io PCSR4STR _pcsr4; +#define PCSR4 _pcsr4.word +#define PCSR4_D0 _pcsr4.bit._D0 +#define PCSR4_D1 _pcsr4.bit._D1 +#define PCSR4_D2 _pcsr4.bit._D2 +#define PCSR4_D3 _pcsr4.bit._D3 +#define PCSR4_D4 _pcsr4.bit._D4 +#define PCSR4_D5 _pcsr4.bit._D5 +#define PCSR4_D6 _pcsr4.bit._D6 +#define PCSR4_D7 _pcsr4.bit._D7 +#define PCSR4_D8 _pcsr4.bit._D8 +#define PCSR4_D9 _pcsr4.bit._D9 +#define PCSR4_D10 _pcsr4.bit._D10 +#define PCSR4_D11 _pcsr4.bit._D11 +#define PCSR4_D12 _pcsr4.bit._D12 +#define PCSR4_D13 _pcsr4.bit._D13 +#define PCSR4_D14 _pcsr4.bit._D14 +#define PCSR4_D15 _pcsr4.bit._D15 +#define PCSR4_D _pcsr4.bitc._D +__IO_EXTERN __io PDUT4STR _pdut4; +#define PDUT4 _pdut4.word +#define PDUT4_D0 _pdut4.bit._D0 +#define PDUT4_D1 _pdut4.bit._D1 +#define PDUT4_D2 _pdut4.bit._D2 +#define PDUT4_D3 _pdut4.bit._D3 +#define PDUT4_D4 _pdut4.bit._D4 +#define PDUT4_D5 _pdut4.bit._D5 +#define PDUT4_D6 _pdut4.bit._D6 +#define PDUT4_D7 _pdut4.bit._D7 +#define PDUT4_D8 _pdut4.bit._D8 +#define PDUT4_D9 _pdut4.bit._D9 +#define PDUT4_D10 _pdut4.bit._D10 +#define PDUT4_D11 _pdut4.bit._D11 +#define PDUT4_D12 _pdut4.bit._D12 +#define PDUT4_D13 _pdut4.bit._D13 +#define PDUT4_D14 _pdut4.bit._D14 +#define PDUT4_D15 _pdut4.bit._D15 +#define PDUT4_D _pdut4.bitc._D +__IO_EXTERN __io PCN4STR _pcn4; +#define PCN4 _pcn4.word +#define PCN4_OSEL _pcn4.bit._OSEL +#define PCN4_OE _pcn4.bit._OE +#define PCN4_IRS0 _pcn4.bit._IRS0 +#define PCN4_IRS1 _pcn4.bit._IRS1 +#define PCN4_IRQF _pcn4.bit._IRQF +#define PCN4_IREN _pcn4.bit._IREN +#define PCN4_EGS0 _pcn4.bit._EGS0 +#define PCN4_EGS1 _pcn4.bit._EGS1 +#define PCN4_PGMS _pcn4.bit._PGMS +#define PCN4_CKS0 _pcn4.bit._CKS0 +#define PCN4_CKS1 _pcn4.bit._CKS1 +#define PCN4_RTRG _pcn4.bit._RTRG +#define PCN4_MDSE _pcn4.bit._MDSE +#define PCN4_STGR _pcn4.bit._STGR +#define PCN4_CNTE _pcn4.bit._CNTE +#define PCN4_IRS _pcn4.bitc._IRS +#define PCN4_EGS _pcn4.bitc._EGS +#define PCN4_CKS _pcn4.bitc._CKS +__IO_EXTERN __io PCNL4STR _pcnl4; +#define PCNL4 _pcnl4.byte +#define PCNL4_OSEL _pcnl4.bit._OSEL +#define PCNL4_OE _pcnl4.bit._OE +#define PCNL4_IRS0 _pcnl4.bit._IRS0 +#define PCNL4_IRS1 _pcnl4.bit._IRS1 +#define PCNL4_IRQF _pcnl4.bit._IRQF +#define PCNL4_IREN _pcnl4.bit._IREN +#define PCNL4_EGS0 _pcnl4.bit._EGS0 +#define PCNL4_EGS1 _pcnl4.bit._EGS1 +#define PCNL4_IRS _pcnl4.bitc._IRS +#define PCNL4_EGS _pcnl4.bitc._EGS +__IO_EXTERN __io PCNH4STR _pcnh4; +#define PCNH4 _pcnh4.byte +#define PCNH4_PGMS _pcnh4.bit._PGMS +#define PCNH4_CKS0 _pcnh4.bit._CKS0 +#define PCNH4_CKS1 _pcnh4.bit._CKS1 +#define PCNH4_RTRG _pcnh4.bit._RTRG +#define PCNH4_MDSE _pcnh4.bit._MDSE +#define PCNH4_STGR _pcnh4.bit._STGR +#define PCNH4_CNTE _pcnh4.bit._CNTE +#define PCNH4_CKS _pcnh4.bitc._CKS +__IO_EXTERN __io PTMR5STR _ptmr5; +#define PTMR5 _ptmr5.word +#define PTMR5_D0 _ptmr5.bit._D0 +#define PTMR5_D1 _ptmr5.bit._D1 +#define PTMR5_D2 _ptmr5.bit._D2 +#define PTMR5_D3 _ptmr5.bit._D3 +#define PTMR5_D4 _ptmr5.bit._D4 +#define PTMR5_D5 _ptmr5.bit._D5 +#define PTMR5_D6 _ptmr5.bit._D6 +#define PTMR5_D7 _ptmr5.bit._D7 +#define PTMR5_D8 _ptmr5.bit._D8 +#define PTMR5_D9 _ptmr5.bit._D9 +#define PTMR5_D10 _ptmr5.bit._D10 +#define PTMR5_D11 _ptmr5.bit._D11 +#define PTMR5_D12 _ptmr5.bit._D12 +#define PTMR5_D13 _ptmr5.bit._D13 +#define PTMR5_D14 _ptmr5.bit._D14 +#define PTMR5_D15 _ptmr5.bit._D15 +#define PTMR5_D _ptmr5.bitc._D +__IO_EXTERN __io PCSR5STR _pcsr5; +#define PCSR5 _pcsr5.word +#define PCSR5_D0 _pcsr5.bit._D0 +#define PCSR5_D1 _pcsr5.bit._D1 +#define PCSR5_D2 _pcsr5.bit._D2 +#define PCSR5_D3 _pcsr5.bit._D3 +#define PCSR5_D4 _pcsr5.bit._D4 +#define PCSR5_D5 _pcsr5.bit._D5 +#define PCSR5_D6 _pcsr5.bit._D6 +#define PCSR5_D7 _pcsr5.bit._D7 +#define PCSR5_D8 _pcsr5.bit._D8 +#define PCSR5_D9 _pcsr5.bit._D9 +#define PCSR5_D10 _pcsr5.bit._D10 +#define PCSR5_D11 _pcsr5.bit._D11 +#define PCSR5_D12 _pcsr5.bit._D12 +#define PCSR5_D13 _pcsr5.bit._D13 +#define PCSR5_D14 _pcsr5.bit._D14 +#define PCSR5_D15 _pcsr5.bit._D15 +#define PCSR5_D _pcsr5.bitc._D +__IO_EXTERN __io PDUT5STR _pdut5; +#define PDUT5 _pdut5.word +#define PDUT5_D0 _pdut5.bit._D0 +#define PDUT5_D1 _pdut5.bit._D1 +#define PDUT5_D2 _pdut5.bit._D2 +#define PDUT5_D3 _pdut5.bit._D3 +#define PDUT5_D4 _pdut5.bit._D4 +#define PDUT5_D5 _pdut5.bit._D5 +#define PDUT5_D6 _pdut5.bit._D6 +#define PDUT5_D7 _pdut5.bit._D7 +#define PDUT5_D8 _pdut5.bit._D8 +#define PDUT5_D9 _pdut5.bit._D9 +#define PDUT5_D10 _pdut5.bit._D10 +#define PDUT5_D11 _pdut5.bit._D11 +#define PDUT5_D12 _pdut5.bit._D12 +#define PDUT5_D13 _pdut5.bit._D13 +#define PDUT5_D14 _pdut5.bit._D14 +#define PDUT5_D15 _pdut5.bit._D15 +#define PDUT5_D _pdut5.bitc._D +__IO_EXTERN __io PCN5STR _pcn5; +#define PCN5 _pcn5.word +#define PCN5_OSEL _pcn5.bit._OSEL +#define PCN5_OE _pcn5.bit._OE +#define PCN5_IRS0 _pcn5.bit._IRS0 +#define PCN5_IRS1 _pcn5.bit._IRS1 +#define PCN5_IRQF _pcn5.bit._IRQF +#define PCN5_IREN _pcn5.bit._IREN +#define PCN5_EGS0 _pcn5.bit._EGS0 +#define PCN5_EGS1 _pcn5.bit._EGS1 +#define PCN5_PGMS _pcn5.bit._PGMS +#define PCN5_CKS0 _pcn5.bit._CKS0 +#define PCN5_CKS1 _pcn5.bit._CKS1 +#define PCN5_RTRG _pcn5.bit._RTRG +#define PCN5_MDSE _pcn5.bit._MDSE +#define PCN5_STGR _pcn5.bit._STGR +#define PCN5_CNTE _pcn5.bit._CNTE +#define PCN5_IRS _pcn5.bitc._IRS +#define PCN5_EGS _pcn5.bitc._EGS +#define PCN5_CKS _pcn5.bitc._CKS +__IO_EXTERN __io PCNL5STR _pcnl5; +#define PCNL5 _pcnl5.byte +#define PCNL5_OSEL _pcnl5.bit._OSEL +#define PCNL5_OE _pcnl5.bit._OE +#define PCNL5_IRS0 _pcnl5.bit._IRS0 +#define PCNL5_IRS1 _pcnl5.bit._IRS1 +#define PCNL5_IRQF _pcnl5.bit._IRQF +#define PCNL5_IREN _pcnl5.bit._IREN +#define PCNL5_EGS0 _pcnl5.bit._EGS0 +#define PCNL5_EGS1 _pcnl5.bit._EGS1 +#define PCNL5_IRS _pcnl5.bitc._IRS +#define PCNL5_EGS _pcnl5.bitc._EGS +__IO_EXTERN __io PCNH5STR _pcnh5; +#define PCNH5 _pcnh5.byte +#define PCNH5_PGMS _pcnh5.bit._PGMS +#define PCNH5_CKS0 _pcnh5.bit._CKS0 +#define PCNH5_CKS1 _pcnh5.bit._CKS1 +#define PCNH5_RTRG _pcnh5.bit._RTRG +#define PCNH5_MDSE _pcnh5.bit._MDSE +#define PCNH5_STGR _pcnh5.bit._STGR +#define PCNH5_CNTE _pcnh5.bit._CNTE +#define PCNH5_CKS _pcnh5.bitc._CKS +__IO_EXTERN __io IBSR0STR _ibsr0; +#define IBSR0 _ibsr0.byte +#define IBSR0_ADT _ibsr0.bit._ADT +#define IBSR0_GCA _ibsr0.bit._GCA +#define IBSR0_AAS _ibsr0.bit._AAS +#define IBSR0_TRX _ibsr0.bit._TRX +#define IBSR0_LRB _ibsr0.bit._LRB +#define IBSR0_AL _ibsr0.bit._AL +#define IBSR0_RSC _ibsr0.bit._RSC +#define IBSR0_BB _ibsr0.bit._BB +__IO_EXTERN __io IBCR0STR _ibcr0; +#define IBCR0 _ibcr0.byte +#define IBCR0_INT _ibcr0.bit._INT +#define IBCR0_INTE _ibcr0.bit._INTE +#define IBCR0_GCAA _ibcr0.bit._GCAA +#define IBCR0_ACK _ibcr0.bit._ACK +#define IBCR0_MSS _ibcr0.bit._MSS +#define IBCR0_SCC _ibcr0.bit._SCC +#define IBCR0_BEIE _ibcr0.bit._BEIE +#define IBCR0_BER _ibcr0.bit._BER +__IO_EXTERN __io ITBA0STR _itba0; +#define ITBA0 _itba0.word +#define ITBA0_TA0 _itba0.bit._TA0 +#define ITBA0_TA1 _itba0.bit._TA1 +#define ITBA0_TA2 _itba0.bit._TA2 +#define ITBA0_TA3 _itba0.bit._TA3 +#define ITBA0_TA4 _itba0.bit._TA4 +#define ITBA0_TA5 _itba0.bit._TA5 +#define ITBA0_TA6 _itba0.bit._TA6 +#define ITBA0_TA7 _itba0.bit._TA7 +#define ITBA0_TA8 _itba0.bit._TA8 +#define ITBA0_TA9 _itba0.bit._TA9 +#define ITBA0_TA _itba0.bitc._TA +__IO_EXTERN __io ITBAL0STR _itbal0; +#define ITBAL0 _itbal0.byte +#define ITBAL0_TA0 _itbal0.bit._TA0 +#define ITBAL0_TA1 _itbal0.bit._TA1 +#define ITBAL0_TA2 _itbal0.bit._TA2 +#define ITBAL0_TA3 _itbal0.bit._TA3 +#define ITBAL0_TA4 _itbal0.bit._TA4 +#define ITBAL0_TA5 _itbal0.bit._TA5 +#define ITBAL0_TA6 _itbal0.bit._TA6 +#define ITBAL0_TA7 _itbal0.bit._TA7 +__IO_EXTERN __io ITBAH0STR _itbah0; +#define ITBAH0 _itbah0.byte +#define ITBAH0_TA8 _itbah0.bit._TA8 +#define ITBAH0_TA9 _itbah0.bit._TA9 +__IO_EXTERN __io ITMK0STR _itmk0; +#define ITMK0 _itmk0.word +#define ITMK0_TM0 _itmk0.bit._TM0 +#define ITMK0_TM1 _itmk0.bit._TM1 +#define ITMK0_TM2 _itmk0.bit._TM2 +#define ITMK0_TM3 _itmk0.bit._TM3 +#define ITMK0_TM4 _itmk0.bit._TM4 +#define ITMK0_TM5 _itmk0.bit._TM5 +#define ITMK0_TM6 _itmk0.bit._TM6 +#define ITMK0_TM7 _itmk0.bit._TM7 +#define ITMK0_TM8 _itmk0.bit._TM8 +#define ITMK0_TM9 _itmk0.bit._TM9 +#define ITMK0_RAL _itmk0.bit._RAL +#define ITMK0_ENTB _itmk0.bit._ENTB +#define ITMK0_TM _itmk0.bitc._TM +__IO_EXTERN __io ITMKL0STR _itmkl0; +#define ITMKL0 _itmkl0.byte +#define ITMKL0_TM0 _itmkl0.bit._TM0 +#define ITMKL0_TM1 _itmkl0.bit._TM1 +#define ITMKL0_TM2 _itmkl0.bit._TM2 +#define ITMKL0_TM3 _itmkl0.bit._TM3 +#define ITMKL0_TM4 _itmkl0.bit._TM4 +#define ITMKL0_TM5 _itmkl0.bit._TM5 +#define ITMKL0_TM6 _itmkl0.bit._TM6 +#define ITMKL0_TM7 _itmkl0.bit._TM7 +__IO_EXTERN __io ITMKH0STR _itmkh0; +#define ITMKH0 _itmkh0.byte +#define ITMKH0_TM8 _itmkh0.bit._TM8 +#define ITMKH0_TM9 _itmkh0.bit._TM9 +#define ITMKH0_RAL _itmkh0.bit._RAL +#define ITMKH0_ENTB _itmkh0.bit._ENTB +__IO_EXTERN __io ISBA0STR _isba0; +#define ISBA0 _isba0.byte +#define ISBA0_SA0 _isba0.bit._SA0 +#define ISBA0_SA1 _isba0.bit._SA1 +#define ISBA0_SA2 _isba0.bit._SA2 +#define ISBA0_SA3 _isba0.bit._SA3 +#define ISBA0_SA4 _isba0.bit._SA4 +#define ISBA0_SA5 _isba0.bit._SA5 +#define ISBA0_SA6 _isba0.bit._SA6 +#define ISBA0_SA _isba0.bitc._SA +__IO_EXTERN __io ISMK0STR _ismk0; +#define ISMK0 _ismk0.byte +#define ISMK0_SM0 _ismk0.bit._SM0 +#define ISMK0_SM1 _ismk0.bit._SM1 +#define ISMK0_SM2 _ismk0.bit._SM2 +#define ISMK0_SM3 _ismk0.bit._SM3 +#define ISMK0_SM4 _ismk0.bit._SM4 +#define ISMK0_SM5 _ismk0.bit._SM5 +#define ISMK0_SM6 _ismk0.bit._SM6 +#define ISMK0_ENSB _ismk0.bit._ENSB +#define ISMK0_SM _ismk0.bitc._SM +__IO_EXTERN __io IDAR0STR _idar0; +#define IDAR0 _idar0.byte +#define IDAR0_D0 _idar0.bit._D0 +#define IDAR0_D1 _idar0.bit._D1 +#define IDAR0_D2 _idar0.bit._D2 +#define IDAR0_D3 _idar0.bit._D3 +#define IDAR0_D4 _idar0.bit._D4 +#define IDAR0_D5 _idar0.bit._D5 +#define IDAR0_D6 _idar0.bit._D6 +#define IDAR0_D7 _idar0.bit._D7 +__IO_EXTERN __io ICCR0STR _iccr0; +#define ICCR0 _iccr0.byte +#define ICCR0_CS0 _iccr0.bit._CS0 +#define ICCR0_CS1 _iccr0.bit._CS1 +#define ICCR0_CS2 _iccr0.bit._CS2 +#define ICCR0_CS3 _iccr0.bit._CS3 +#define ICCR0_CS4 _iccr0.bit._CS4 +#define ICCR0_EN _iccr0.bit._EN +#define ICCR0_NSF _iccr0.bit._NSF +#define ICCR0_CS _iccr0.bitc._CS +__IO_EXTERN __io IBSR1STR _ibsr1; +#define IBSR1 _ibsr1.byte +#define IBSR1_ADT _ibsr1.bit._ADT +#define IBSR1_GCA _ibsr1.bit._GCA +#define IBSR1_AAS _ibsr1.bit._AAS +#define IBSR1_TRX _ibsr1.bit._TRX +#define IBSR1_LRB _ibsr1.bit._LRB +#define IBSR1_AL _ibsr1.bit._AL +#define IBSR1_RSC _ibsr1.bit._RSC +#define IBSR1_BB _ibsr1.bit._BB +__IO_EXTERN __io IBCR1STR _ibcr1; +#define IBCR1 _ibcr1.byte +#define IBCR1_INT _ibcr1.bit._INT +#define IBCR1_INTE _ibcr1.bit._INTE +#define IBCR1_GCAA _ibcr1.bit._GCAA +#define IBCR1_ACK _ibcr1.bit._ACK +#define IBCR1_MSS _ibcr1.bit._MSS +#define IBCR1_SCC _ibcr1.bit._SCC +#define IBCR1_BEIE _ibcr1.bit._BEIE +#define IBCR1_BER _ibcr1.bit._BER +__IO_EXTERN __io ITBA1STR _itba1; +#define ITBA1 _itba1.word +#define ITBA1_TA0 _itba1.bit._TA0 +#define ITBA1_TA1 _itba1.bit._TA1 +#define ITBA1_TA2 _itba1.bit._TA2 +#define ITBA1_TA3 _itba1.bit._TA3 +#define ITBA1_TA4 _itba1.bit._TA4 +#define ITBA1_TA5 _itba1.bit._TA5 +#define ITBA1_TA6 _itba1.bit._TA6 +#define ITBA1_TA7 _itba1.bit._TA7 +#define ITBA1_TA8 _itba1.bit._TA8 +#define ITBA1_TA9 _itba1.bit._TA9 +#define ITBA1_TA _itba1.bitc._TA +__IO_EXTERN __io ITBAL1STR _itbal1; +#define ITBAL1 _itbal1.byte +#define ITBAL1_TA0 _itbal1.bit._TA0 +#define ITBAL1_TA1 _itbal1.bit._TA1 +#define ITBAL1_TA2 _itbal1.bit._TA2 +#define ITBAL1_TA3 _itbal1.bit._TA3 +#define ITBAL1_TA4 _itbal1.bit._TA4 +#define ITBAL1_TA5 _itbal1.bit._TA5 +#define ITBAL1_TA6 _itbal1.bit._TA6 +#define ITBAL1_TA7 _itbal1.bit._TA7 +__IO_EXTERN __io ITBAH1STR _itbah1; +#define ITBAH1 _itbah1.byte +#define ITBAH1_TA8 _itbah1.bit._TA8 +#define ITBAH1_TA9 _itbah1.bit._TA9 +__IO_EXTERN __io ITMK1STR _itmk1; +#define ITMK1 _itmk1.word +#define ITMK1_TM0 _itmk1.bit._TM0 +#define ITMK1_TM1 _itmk1.bit._TM1 +#define ITMK1_TM2 _itmk1.bit._TM2 +#define ITMK1_TM3 _itmk1.bit._TM3 +#define ITMK1_TM4 _itmk1.bit._TM4 +#define ITMK1_TM5 _itmk1.bit._TM5 +#define ITMK1_TM6 _itmk1.bit._TM6 +#define ITMK1_TM7 _itmk1.bit._TM7 +#define ITMK1_TM8 _itmk1.bit._TM8 +#define ITMK1_TM9 _itmk1.bit._TM9 +#define ITMK1_RAL _itmk1.bit._RAL +#define ITMK1_ENTB _itmk1.bit._ENTB +#define ITMK1_TM _itmk1.bitc._TM +__IO_EXTERN __io ITMKL1STR _itmkl1; +#define ITMKL1 _itmkl1.byte +#define ITMKL1_TM0 _itmkl1.bit._TM0 +#define ITMKL1_TM1 _itmkl1.bit._TM1 +#define ITMKL1_TM2 _itmkl1.bit._TM2 +#define ITMKL1_TM3 _itmkl1.bit._TM3 +#define ITMKL1_TM4 _itmkl1.bit._TM4 +#define ITMKL1_TM5 _itmkl1.bit._TM5 +#define ITMKL1_TM6 _itmkl1.bit._TM6 +#define ITMKL1_TM7 _itmkl1.bit._TM7 +__IO_EXTERN __io ITMKH1STR _itmkh1; +#define ITMKH1 _itmkh1.byte +#define ITMKH1_TM8 _itmkh1.bit._TM8 +#define ITMKH1_TM9 _itmkh1.bit._TM9 +#define ITMKH1_RAL _itmkh1.bit._RAL +#define ITMKH1_ENTB _itmkh1.bit._ENTB +__IO_EXTERN __io ISBA1STR _isba1; +#define ISBA1 _isba1.byte +#define ISBA1_SA0 _isba1.bit._SA0 +#define ISBA1_SA1 _isba1.bit._SA1 +#define ISBA1_SA2 _isba1.bit._SA2 +#define ISBA1_SA3 _isba1.bit._SA3 +#define ISBA1_SA4 _isba1.bit._SA4 +#define ISBA1_SA5 _isba1.bit._SA5 +#define ISBA1_SA6 _isba1.bit._SA6 +#define ISBA1_SA _isba1.bitc._SA +__IO_EXTERN __io ISMK1STR _ismk1; +#define ISMK1 _ismk1.byte +#define ISMK1_SM0 _ismk1.bit._SM0 +#define ISMK1_SM1 _ismk1.bit._SM1 +#define ISMK1_SM2 _ismk1.bit._SM2 +#define ISMK1_SM3 _ismk1.bit._SM3 +#define ISMK1_SM4 _ismk1.bit._SM4 +#define ISMK1_SM5 _ismk1.bit._SM5 +#define ISMK1_SM6 _ismk1.bit._SM6 +#define ISMK1_ENSB _ismk1.bit._ENSB +#define ISMK1_SM _ismk1.bitc._SM +__IO_EXTERN __io IDAR1STR _idar1; +#define IDAR1 _idar1.byte +#define IDAR1_D0 _idar1.bit._D0 +#define IDAR1_D1 _idar1.bit._D1 +#define IDAR1_D2 _idar1.bit._D2 +#define IDAR1_D3 _idar1.bit._D3 +#define IDAR1_D4 _idar1.bit._D4 +#define IDAR1_D5 _idar1.bit._D5 +#define IDAR1_D6 _idar1.bit._D6 +#define IDAR1_D7 _idar1.bit._D7 +__IO_EXTERN __io ICCR1STR _iccr1; +#define ICCR1 _iccr1.byte +#define ICCR1_CS0 _iccr1.bit._CS0 +#define ICCR1_CS1 _iccr1.bit._CS1 +#define ICCR1_CS2 _iccr1.bit._CS2 +#define ICCR1_CS3 _iccr1.bit._CS3 +#define ICCR1_CS4 _iccr1.bit._CS4 +#define ICCR1_EN _iccr1.bit._EN +#define ICCR1_NSF _iccr1.bit._NSF +#define ICCR1_CS _iccr1.bitc._CS +__IO_EXTERN __io SMR0STR _smr0; +#define SMR0 _smr0.byte +#define SMR0_SOE _smr0.bit._SOE +#define SMR0_SCKE _smr0.bit._SCKE +#define SMR0_UPCL _smr0.bit._UPCL +#define SMR0_REST _smr0.bit._REST +#define SMR0_EXT _smr0.bit._EXT +#define SMR0_OTO _smr0.bit._OTO +#define SMR0_MD0 _smr0.bit._MD0 +#define SMR0_MD1 _smr0.bit._MD1 +#define SMR0_MD _smr0.bitc._MD +__IO_EXTERN __io SCR0STR _scr0; +#define SCR0 _scr0.byte +#define SCR0_TXE _scr0.bit._TXE +#define SCR0_RXE _scr0.bit._RXE +#define SCR0_CRE _scr0.bit._CRE +#define SCR0_AD _scr0.bit._AD +#define SCR0_CL _scr0.bit._CL +#define SCR0_SBL _scr0.bit._SBL +#define SCR0_P _scr0.bit._P +#define SCR0_PEN _scr0.bit._PEN +__IO_EXTERN __io IO_BYTE _tdr0; +#define TDR0 _tdr0 +__IO_EXTERN __io IO_BYTE _rdr0; +#define RDR0 _rdr0 +__IO_EXTERN __io SSR0STR _ssr0; +#define SSR0 _ssr0.byte +#define SSR0_TIE _ssr0.bit._TIE +#define SSR0_RIE _ssr0.bit._RIE +#define SSR0_BDS _ssr0.bit._BDS +#define SSR0_TDRE _ssr0.bit._TDRE +#define SSR0_RDRF _ssr0.bit._RDRF +#define SSR0_FRE _ssr0.bit._FRE +#define SSR0_ORE _ssr0.bit._ORE +#define SSR0_PE _ssr0.bit._PE +__IO_EXTERN __io ECCR0STR _eccr0; +#define ECCR0 _eccr0.byte +#define ECCR0_TBI _eccr0.bit._TBI +#define ECCR0_RBI _eccr0.bit._RBI +#define ECCR0_BIE _eccr0.bit._BIE +#define ECCR0_SSM _eccr0.bit._SSM +#define ECCR0_SCDE _eccr0.bit._SCDE +#define ECCR0_MS _eccr0.bit._MS +#define ECCR0_LBR _eccr0.bit._LBR +#define ECCR0_INV _eccr0.bit._INV +__IO_EXTERN __io ESCR0STR _escr0; +#define ESCR0 _escr0.byte +#define ESCR0_SCES _escr0.bit._SCES +#define ESCR0_CCO _escr0.bit._CCO +#define ESCR0_SIOP _escr0.bit._SIOP +#define ESCR0_SOPE _escr0.bit._SOPE +#define ESCR0_LBL0 _escr0.bit._LBL0 +#define ESCR0_LBL1 _escr0.bit._LBL1 +#define ESCR0_LBD _escr0.bit._LBD +#define ESCR0_LBIE _escr0.bit._LBIE +#define ESCR0_LBL _escr0.bitc._LBL +__IO_EXTERN __io BGR0STR _bgr0; +#define BGR0 _bgr0.word +#define BGR0_BGR0 _bgr0.bit._BGR0 +#define BGR0_BGR1 _bgr0.bit._BGR1 +#define BGR0_BGR2 _bgr0.bit._BGR2 +#define BGR0_BGR3 _bgr0.bit._BGR3 +#define BGR0_BGR4 _bgr0.bit._BGR4 +#define BGR0_BGR5 _bgr0.bit._BGR5 +#define BGR0_BGR6 _bgr0.bit._BGR6 +#define BGR0_BGR7 _bgr0.bit._BGR7 +#define BGR0_BGR8 _bgr0.bit._BGR8 +#define BGR0_BGR9 _bgr0.bit._BGR9 +#define BGR0_BGR10 _bgr0.bit._BGR10 +#define BGR0_BGR11 _bgr0.bit._BGR11 +#define BGR0_BGR12 _bgr0.bit._BGR12 +#define BGR0_BGR13 _bgr0.bit._BGR13 +#define BGR0_BGR14 _bgr0.bit._BGR14 +#define BGR0_BGR15 _bgr0.bit._BGR15 +#define BGR0_BGR _bgr0.bitc._BGR +__IO_EXTERN __io BGRL0STR _bgrl0; +#define BGRL0 _bgrl0.byte +#define BGRL0_BGR0 _bgrl0.bit._BGR0 +#define BGRL0_BGR1 _bgrl0.bit._BGR1 +#define BGRL0_BGR2 _bgrl0.bit._BGR2 +#define BGRL0_BGR3 _bgrl0.bit._BGR3 +#define BGRL0_BGR4 _bgrl0.bit._BGR4 +#define BGRL0_BGR5 _bgrl0.bit._BGR5 +#define BGRL0_BGR6 _bgrl0.bit._BGR6 +#define BGRL0_BGR7 _bgrl0.bit._BGR7 +__IO_EXTERN __io BGRH0STR _bgrh0; +#define BGRH0 _bgrh0.byte +#define BGRH0_BGR8 _bgrh0.bit._BGR8 +#define BGRH0_BGR9 _bgrh0.bit._BGR9 +#define BGRH0_BGR10 _bgrh0.bit._BGR10 +#define BGRH0_BGR11 _bgrh0.bit._BGR11 +#define BGRH0_BGR12 _bgrh0.bit._BGR12 +#define BGRH0_BGR13 _bgrh0.bit._BGR13 +#define BGRH0_BGR14 _bgrh0.bit._BGR14 +#define BGRH0_BGR15 _bgrh0.bit._BGR15 +__IO_EXTERN __io ESIR0STR _esir0; +#define ESIR0 _esir0.byte +#define ESIR0_AICD _esir0.bit._AICD +#define ESIR0_RBI _esir0.bit._RBI +#define ESIR0_RDRF _esir0.bit._RDRF +#define ESIR0_TDRE _esir0.bit._TDRE +__IO_EXTERN __io SMR1STR _smr1; +#define SMR1 _smr1.byte +#define SMR1_SOE _smr1.bit._SOE +#define SMR1_SCKE _smr1.bit._SCKE +#define SMR1_UPCL _smr1.bit._UPCL +#define SMR1_REST _smr1.bit._REST +#define SMR1_EXT _smr1.bit._EXT +#define SMR1_OTO _smr1.bit._OTO +#define SMR1_MD0 _smr1.bit._MD0 +#define SMR1_MD1 _smr1.bit._MD1 +#define SMR1_MD _smr1.bitc._MD +__IO_EXTERN __io SCR1STR _scr1; +#define SCR1 _scr1.byte +#define SCR1_TXE _scr1.bit._TXE +#define SCR1_RXE _scr1.bit._RXE +#define SCR1_CRE _scr1.bit._CRE +#define SCR1_AD _scr1.bit._AD +#define SCR1_CL _scr1.bit._CL +#define SCR1_SBL _scr1.bit._SBL +#define SCR1_P _scr1.bit._P +#define SCR1_PEN _scr1.bit._PEN +__IO_EXTERN __io IO_BYTE _tdr1; +#define TDR1 _tdr1 +__IO_EXTERN __io IO_BYTE _rdr1; +#define RDR1 _rdr1 +__IO_EXTERN __io SSR1STR _ssr1; +#define SSR1 _ssr1.byte +#define SSR1_TIE _ssr1.bit._TIE +#define SSR1_RIE _ssr1.bit._RIE +#define SSR1_BDS _ssr1.bit._BDS +#define SSR1_TDRE _ssr1.bit._TDRE +#define SSR1_RDRF _ssr1.bit._RDRF +#define SSR1_FRE _ssr1.bit._FRE +#define SSR1_ORE _ssr1.bit._ORE +#define SSR1_PE _ssr1.bit._PE +__IO_EXTERN __io ECCR1STR _eccr1; +#define ECCR1 _eccr1.byte +#define ECCR1_TBI _eccr1.bit._TBI +#define ECCR1_RBI _eccr1.bit._RBI +#define ECCR1_BIE _eccr1.bit._BIE +#define ECCR1_SSM _eccr1.bit._SSM +#define ECCR1_SCDE _eccr1.bit._SCDE +#define ECCR1_MS _eccr1.bit._MS +#define ECCR1_LBR _eccr1.bit._LBR +#define ECCR1_INV _eccr1.bit._INV +__IO_EXTERN __io ESCR1STR _escr1; +#define ESCR1 _escr1.byte +#define ESCR1_SCES _escr1.bit._SCES +#define ESCR1_CCO _escr1.bit._CCO +#define ESCR1_SIOP _escr1.bit._SIOP +#define ESCR1_SOPE _escr1.bit._SOPE +#define ESCR1_LBL0 _escr1.bit._LBL0 +#define ESCR1_LBL1 _escr1.bit._LBL1 +#define ESCR1_LBD _escr1.bit._LBD +#define ESCR1_LBIE _escr1.bit._LBIE +#define ESCR1_LBL _escr1.bitc._LBL +__IO_EXTERN __io BGR1STR _bgr1; +#define BGR1 _bgr1.word +#define BGR1_BGR0 _bgr1.bit._BGR0 +#define BGR1_BGR1 _bgr1.bit._BGR1 +#define BGR1_BGR2 _bgr1.bit._BGR2 +#define BGR1_BGR3 _bgr1.bit._BGR3 +#define BGR1_BGR4 _bgr1.bit._BGR4 +#define BGR1_BGR5 _bgr1.bit._BGR5 +#define BGR1_BGR6 _bgr1.bit._BGR6 +#define BGR1_BGR7 _bgr1.bit._BGR7 +#define BGR1_BGR8 _bgr1.bit._BGR8 +#define BGR1_BGR9 _bgr1.bit._BGR9 +#define BGR1_BGR10 _bgr1.bit._BGR10 +#define BGR1_BGR11 _bgr1.bit._BGR11 +#define BGR1_BGR12 _bgr1.bit._BGR12 +#define BGR1_BGR13 _bgr1.bit._BGR13 +#define BGR1_BGR14 _bgr1.bit._BGR14 +#define BGR1_BGR15 _bgr1.bit._BGR15 +#define BGR1_BGR _bgr1.bitc._BGR +__IO_EXTERN __io BGRL1STR _bgrl1; +#define BGRL1 _bgrl1.byte +#define BGRL1_BGR0 _bgrl1.bit._BGR0 +#define BGRL1_BGR1 _bgrl1.bit._BGR1 +#define BGRL1_BGR2 _bgrl1.bit._BGR2 +#define BGRL1_BGR3 _bgrl1.bit._BGR3 +#define BGRL1_BGR4 _bgrl1.bit._BGR4 +#define BGRL1_BGR5 _bgrl1.bit._BGR5 +#define BGRL1_BGR6 _bgrl1.bit._BGR6 +#define BGRL1_BGR7 _bgrl1.bit._BGR7 +__IO_EXTERN __io BGRH1STR _bgrh1; +#define BGRH1 _bgrh1.byte +#define BGRH1_BGR8 _bgrh1.bit._BGR8 +#define BGRH1_BGR9 _bgrh1.bit._BGR9 +#define BGRH1_BGR10 _bgrh1.bit._BGR10 +#define BGRH1_BGR11 _bgrh1.bit._BGR11 +#define BGRH1_BGR12 _bgrh1.bit._BGR12 +#define BGRH1_BGR13 _bgrh1.bit._BGR13 +#define BGRH1_BGR14 _bgrh1.bit._BGR14 +#define BGRH1_BGR15 _bgrh1.bit._BGR15 +__IO_EXTERN __io ESIR1STR _esir1; +#define ESIR1 _esir1.byte +#define ESIR1_AICD _esir1.bit._AICD +#define ESIR1_RBI _esir1.bit._RBI +#define ESIR1_RDRF _esir1.bit._RDRF +#define ESIR1_TDRE _esir1.bit._TDRE +__IO_EXTERN __io SMR2STR _smr2; +#define SMR2 _smr2.byte +#define SMR2_SOE _smr2.bit._SOE +#define SMR2_SCKE _smr2.bit._SCKE +#define SMR2_UPCL _smr2.bit._UPCL +#define SMR2_REST _smr2.bit._REST +#define SMR2_EXT _smr2.bit._EXT +#define SMR2_OTO _smr2.bit._OTO +#define SMR2_MD0 _smr2.bit._MD0 +#define SMR2_MD1 _smr2.bit._MD1 +#define SMR2_MD _smr2.bitc._MD +__IO_EXTERN __io SCR2STR _scr2; +#define SCR2 _scr2.byte +#define SCR2_TXE _scr2.bit._TXE +#define SCR2_RXE _scr2.bit._RXE +#define SCR2_CRE _scr2.bit._CRE +#define SCR2_AD _scr2.bit._AD +#define SCR2_CL _scr2.bit._CL +#define SCR2_SBL _scr2.bit._SBL +#define SCR2_P _scr2.bit._P +#define SCR2_PEN _scr2.bit._PEN +__IO_EXTERN __io IO_BYTE _tdr2; +#define TDR2 _tdr2 +__IO_EXTERN __io IO_BYTE _rdr2; +#define RDR2 _rdr2 +__IO_EXTERN __io SSR2STR _ssr2; +#define SSR2 _ssr2.byte +#define SSR2_TIE _ssr2.bit._TIE +#define SSR2_RIE _ssr2.bit._RIE +#define SSR2_BDS _ssr2.bit._BDS +#define SSR2_TDRE _ssr2.bit._TDRE +#define SSR2_RDRF _ssr2.bit._RDRF +#define SSR2_FRE _ssr2.bit._FRE +#define SSR2_ORE _ssr2.bit._ORE +#define SSR2_PE _ssr2.bit._PE +__IO_EXTERN __io ECCR2STR _eccr2; +#define ECCR2 _eccr2.byte +#define ECCR2_TBI _eccr2.bit._TBI +#define ECCR2_RBI _eccr2.bit._RBI +#define ECCR2_BIE _eccr2.bit._BIE +#define ECCR2_SSM _eccr2.bit._SSM +#define ECCR2_SCDE _eccr2.bit._SCDE +#define ECCR2_MS _eccr2.bit._MS +#define ECCR2_LBR _eccr2.bit._LBR +#define ECCR2_INV _eccr2.bit._INV +__IO_EXTERN __io ESCR2STR _escr2; +#define ESCR2 _escr2.byte +#define ESCR2_SCES _escr2.bit._SCES +#define ESCR2_CCO _escr2.bit._CCO +#define ESCR2_SIOP _escr2.bit._SIOP +#define ESCR2_SOPE _escr2.bit._SOPE +#define ESCR2_LBL0 _escr2.bit._LBL0 +#define ESCR2_LBL1 _escr2.bit._LBL1 +#define ESCR2_LBD _escr2.bit._LBD +#define ESCR2_LBIE _escr2.bit._LBIE +#define ESCR2_LBL _escr2.bitc._LBL +__IO_EXTERN __io BGR2STR _bgr2; +#define BGR2 _bgr2.word +#define BGR2_BGR0 _bgr2.bit._BGR0 +#define BGR2_BGR1 _bgr2.bit._BGR1 +#define BGR2_BGR2 _bgr2.bit._BGR2 +#define BGR2_BGR3 _bgr2.bit._BGR3 +#define BGR2_BGR4 _bgr2.bit._BGR4 +#define BGR2_BGR5 _bgr2.bit._BGR5 +#define BGR2_BGR6 _bgr2.bit._BGR6 +#define BGR2_BGR7 _bgr2.bit._BGR7 +#define BGR2_BGR8 _bgr2.bit._BGR8 +#define BGR2_BGR9 _bgr2.bit._BGR9 +#define BGR2_BGR10 _bgr2.bit._BGR10 +#define BGR2_BGR11 _bgr2.bit._BGR11 +#define BGR2_BGR12 _bgr2.bit._BGR12 +#define BGR2_BGR13 _bgr2.bit._BGR13 +#define BGR2_BGR14 _bgr2.bit._BGR14 +#define BGR2_BGR15 _bgr2.bit._BGR15 +#define BGR2_BGR _bgr2.bitc._BGR +__IO_EXTERN __io BGRL2STR _bgrl2; +#define BGRL2 _bgrl2.byte +#define BGRL2_BGR0 _bgrl2.bit._BGR0 +#define BGRL2_BGR1 _bgrl2.bit._BGR1 +#define BGRL2_BGR2 _bgrl2.bit._BGR2 +#define BGRL2_BGR3 _bgrl2.bit._BGR3 +#define BGRL2_BGR4 _bgrl2.bit._BGR4 +#define BGRL2_BGR5 _bgrl2.bit._BGR5 +#define BGRL2_BGR6 _bgrl2.bit._BGR6 +#define BGRL2_BGR7 _bgrl2.bit._BGR7 +__IO_EXTERN __io BGRH2STR _bgrh2; +#define BGRH2 _bgrh2.byte +#define BGRH2_BGR8 _bgrh2.bit._BGR8 +#define BGRH2_BGR9 _bgrh2.bit._BGR9 +#define BGRH2_BGR10 _bgrh2.bit._BGR10 +#define BGRH2_BGR11 _bgrh2.bit._BGR11 +#define BGRH2_BGR12 _bgrh2.bit._BGR12 +#define BGRH2_BGR13 _bgrh2.bit._BGR13 +#define BGRH2_BGR14 _bgrh2.bit._BGR14 +#define BGRH2_BGR15 _bgrh2.bit._BGR15 +__IO_EXTERN __io ESIR2STR _esir2; +#define ESIR2 _esir2.byte +#define ESIR2_AICD _esir2.bit._AICD +#define ESIR2_RBI _esir2.bit._RBI +#define ESIR2_RDRF _esir2.bit._RDRF +#define ESIR2_TDRE _esir2.bit._TDRE +__IO_EXTERN __io SMR3STR _smr3; +#define SMR3 _smr3.byte +#define SMR3_SOE _smr3.bit._SOE +#define SMR3_SCKE _smr3.bit._SCKE +#define SMR3_UPCL _smr3.bit._UPCL +#define SMR3_REST _smr3.bit._REST +#define SMR3_EXT _smr3.bit._EXT +#define SMR3_OTO _smr3.bit._OTO +#define SMR3_MD0 _smr3.bit._MD0 +#define SMR3_MD1 _smr3.bit._MD1 +#define SMR3_MD _smr3.bitc._MD +__IO_EXTERN __io SCR3STR _scr3; +#define SCR3 _scr3.byte +#define SCR3_TXE _scr3.bit._TXE +#define SCR3_RXE _scr3.bit._RXE +#define SCR3_CRE _scr3.bit._CRE +#define SCR3_AD _scr3.bit._AD +#define SCR3_CL _scr3.bit._CL +#define SCR3_SBL _scr3.bit._SBL +#define SCR3_P _scr3.bit._P +#define SCR3_PEN _scr3.bit._PEN +__IO_EXTERN __io IO_BYTE _tdr3; +#define TDR3 _tdr3 +__IO_EXTERN __io IO_BYTE _rdr3; +#define RDR3 _rdr3 +__IO_EXTERN __io SSR3STR _ssr3; +#define SSR3 _ssr3.byte +#define SSR3_TIE _ssr3.bit._TIE +#define SSR3_RIE _ssr3.bit._RIE +#define SSR3_BDS _ssr3.bit._BDS +#define SSR3_TDRE _ssr3.bit._TDRE +#define SSR3_RDRF _ssr3.bit._RDRF +#define SSR3_FRE _ssr3.bit._FRE +#define SSR3_ORE _ssr3.bit._ORE +#define SSR3_PE _ssr3.bit._PE +__IO_EXTERN __io ECCR3STR _eccr3; +#define ECCR3 _eccr3.byte +#define ECCR3_TBI _eccr3.bit._TBI +#define ECCR3_RBI _eccr3.bit._RBI +#define ECCR3_BIE _eccr3.bit._BIE +#define ECCR3_SSM _eccr3.bit._SSM +#define ECCR3_SCDE _eccr3.bit._SCDE +#define ECCR3_MS _eccr3.bit._MS +#define ECCR3_LBR _eccr3.bit._LBR +#define ECCR3_INV _eccr3.bit._INV +__IO_EXTERN __io ESCR3STR _escr3; +#define ESCR3 _escr3.byte +#define ESCR3_SCES _escr3.bit._SCES +#define ESCR3_CCO _escr3.bit._CCO +#define ESCR3_SIOP _escr3.bit._SIOP +#define ESCR3_SOPE _escr3.bit._SOPE +#define ESCR3_LBL0 _escr3.bit._LBL0 +#define ESCR3_LBL1 _escr3.bit._LBL1 +#define ESCR3_LBD _escr3.bit._LBD +#define ESCR3_LBIE _escr3.bit._LBIE +#define ESCR3_LBL _escr3.bitc._LBL +__IO_EXTERN __io BGR3STR _bgr3; +#define BGR3 _bgr3.word +#define BGR3_BGR0 _bgr3.bit._BGR0 +#define BGR3_BGR1 _bgr3.bit._BGR1 +#define BGR3_BGR2 _bgr3.bit._BGR2 +#define BGR3_BGR3 _bgr3.bit._BGR3 +#define BGR3_BGR4 _bgr3.bit._BGR4 +#define BGR3_BGR5 _bgr3.bit._BGR5 +#define BGR3_BGR6 _bgr3.bit._BGR6 +#define BGR3_BGR7 _bgr3.bit._BGR7 +#define BGR3_BGR8 _bgr3.bit._BGR8 +#define BGR3_BGR9 _bgr3.bit._BGR9 +#define BGR3_BGR10 _bgr3.bit._BGR10 +#define BGR3_BGR11 _bgr3.bit._BGR11 +#define BGR3_BGR12 _bgr3.bit._BGR12 +#define BGR3_BGR13 _bgr3.bit._BGR13 +#define BGR3_BGR14 _bgr3.bit._BGR14 +#define BGR3_BGR15 _bgr3.bit._BGR15 +#define BGR3_BGR _bgr3.bitc._BGR +__IO_EXTERN __io BGRL3STR _bgrl3; +#define BGRL3 _bgrl3.byte +#define BGRL3_BGR0 _bgrl3.bit._BGR0 +#define BGRL3_BGR1 _bgrl3.bit._BGR1 +#define BGRL3_BGR2 _bgrl3.bit._BGR2 +#define BGRL3_BGR3 _bgrl3.bit._BGR3 +#define BGRL3_BGR4 _bgrl3.bit._BGR4 +#define BGRL3_BGR5 _bgrl3.bit._BGR5 +#define BGRL3_BGR6 _bgrl3.bit._BGR6 +#define BGRL3_BGR7 _bgrl3.bit._BGR7 +__IO_EXTERN __io BGRH3STR _bgrh3; +#define BGRH3 _bgrh3.byte +#define BGRH3_BGR8 _bgrh3.bit._BGR8 +#define BGRH3_BGR9 _bgrh3.bit._BGR9 +#define BGRH3_BGR10 _bgrh3.bit._BGR10 +#define BGRH3_BGR11 _bgrh3.bit._BGR11 +#define BGRH3_BGR12 _bgrh3.bit._BGR12 +#define BGRH3_BGR13 _bgrh3.bit._BGR13 +#define BGRH3_BGR14 _bgrh3.bit._BGR14 +#define BGRH3_BGR15 _bgrh3.bit._BGR15 +__IO_EXTERN __io ESIR3STR _esir3; +#define ESIR3 _esir3.byte +#define ESIR3_AICD _esir3.bit._AICD +#define ESIR3_RBI _esir3.bit._RBI +#define ESIR3_RDRF _esir3.bit._RDRF +#define ESIR3_TDRE _esir3.bit._TDRE +__IO_EXTENDED IO_BYTE _bapl0; +#define BAPL0 _bapl0 +__IO_EXTENDED IO_BYTE _bapm0; +#define BAPM0 _bapm0 +__IO_EXTENDED IO_BYTE _baph0; +#define BAPH0 _baph0 +__IO_EXTENDED DMACS0STR _dmacs0; +#define DMACS0 _dmacs0.byte +#define DMACS0_SE _dmacs0.bit._SE +#define DMACS0_DIR _dmacs0.bit._DIR +#define DMACS0_BF _dmacs0.bit._BF +#define DMACS0_BW _dmacs0.bit._BW +#define DMACS0_IF _dmacs0.bit._IF +#define DMACS0_BPD _dmacs0.bit._BPD +__IO_EXTENDED IO_WORD _ioa0; +#define IOA0 _ioa0 +__IO_EXTENDED IO_BYTE _ioal0; +#define IOAL0 _ioal0 +__IO_EXTENDED IO_BYTE _ioah0; +#define IOAH0 _ioah0 +__IO_EXTENDED IO_WORD _dct0; +#define DCT0 _dct0 +__IO_EXTENDED IO_BYTE _dctl0; +#define DCTL0 _dctl0 +__IO_EXTENDED IO_BYTE _dcth0; +#define DCTH0 _dcth0 +__IO_EXTENDED IO_BYTE _bapl1; +#define BAPL1 _bapl1 +__IO_EXTENDED IO_BYTE _bapm1; +#define BAPM1 _bapm1 +__IO_EXTENDED IO_BYTE _baph1; +#define BAPH1 _baph1 +__IO_EXTENDED DMACS1STR _dmacs1; +#define DMACS1 _dmacs1.byte +#define DMACS1_SE _dmacs1.bit._SE +#define DMACS1_DIR _dmacs1.bit._DIR +#define DMACS1_BF _dmacs1.bit._BF +#define DMACS1_BW _dmacs1.bit._BW +#define DMACS1_IF _dmacs1.bit._IF +#define DMACS1_BPD _dmacs1.bit._BPD +__IO_EXTENDED IO_WORD _ioa1; +#define IOA1 _ioa1 +__IO_EXTENDED IO_BYTE _ioal1; +#define IOAL1 _ioal1 +__IO_EXTENDED IO_BYTE _ioah1; +#define IOAH1 _ioah1 +__IO_EXTENDED IO_WORD _dct1; +#define DCT1 _dct1 +__IO_EXTENDED IO_BYTE _dctl1; +#define DCTL1 _dctl1 +__IO_EXTENDED IO_BYTE _dcth1; +#define DCTH1 _dcth1 +__IO_EXTENDED IO_BYTE _bapl2; +#define BAPL2 _bapl2 +__IO_EXTENDED IO_BYTE _bapm2; +#define BAPM2 _bapm2 +__IO_EXTENDED IO_BYTE _baph2; +#define BAPH2 _baph2 +__IO_EXTENDED DMACS2STR _dmacs2; +#define DMACS2 _dmacs2.byte +#define DMACS2_SE _dmacs2.bit._SE +#define DMACS2_DIR _dmacs2.bit._DIR +#define DMACS2_BF _dmacs2.bit._BF +#define DMACS2_BW _dmacs2.bit._BW +#define DMACS2_IF _dmacs2.bit._IF +#define DMACS2_BPD _dmacs2.bit._BPD +__IO_EXTENDED IO_WORD _ioa2; +#define IOA2 _ioa2 +__IO_EXTENDED IO_BYTE _ioal2; +#define IOAL2 _ioal2 +__IO_EXTENDED IO_BYTE _ioah2; +#define IOAH2 _ioah2 +__IO_EXTENDED IO_WORD _dct2; +#define DCT2 _dct2 +__IO_EXTENDED IO_BYTE _dctl2; +#define DCTL2 _dctl2 +__IO_EXTENDED IO_BYTE _dcth2; +#define DCTH2 _dcth2 +__IO_EXTENDED IO_BYTE _bapl3; +#define BAPL3 _bapl3 +__IO_EXTENDED IO_BYTE _bapm3; +#define BAPM3 _bapm3 +__IO_EXTENDED IO_BYTE _baph3; +#define BAPH3 _baph3 +__IO_EXTENDED DMACS3STR _dmacs3; +#define DMACS3 _dmacs3.byte +#define DMACS3_SE _dmacs3.bit._SE +#define DMACS3_DIR _dmacs3.bit._DIR +#define DMACS3_BF _dmacs3.bit._BF +#define DMACS3_BW _dmacs3.bit._BW +#define DMACS3_IF _dmacs3.bit._IF +#define DMACS3_BPD _dmacs3.bit._BPD +__IO_EXTENDED IO_WORD _ioa3; +#define IOA3 _ioa3 +__IO_EXTENDED IO_BYTE _ioal3; +#define IOAL3 _ioal3 +__IO_EXTENDED IO_BYTE _ioah3; +#define IOAH3 _ioah3 +__IO_EXTENDED IO_WORD _dct3; +#define DCT3 _dct3 +__IO_EXTENDED IO_BYTE _dctl3; +#define DCTL3 _dctl3 +__IO_EXTENDED IO_BYTE _dcth3; +#define DCTH3 _dcth3 +__IO_EXTENDED IO_BYTE _bapl4; +#define BAPL4 _bapl4 +__IO_EXTENDED IO_BYTE _bapm4; +#define BAPM4 _bapm4 +__IO_EXTENDED IO_BYTE _baph4; +#define BAPH4 _baph4 +__IO_EXTENDED DMACS4STR _dmacs4; +#define DMACS4 _dmacs4.byte +#define DMACS4_SE _dmacs4.bit._SE +#define DMACS4_DIR _dmacs4.bit._DIR +#define DMACS4_BF _dmacs4.bit._BF +#define DMACS4_BW _dmacs4.bit._BW +#define DMACS4_IF _dmacs4.bit._IF +#define DMACS4_BPD _dmacs4.bit._BPD +__IO_EXTENDED IO_WORD _ioa4; +#define IOA4 _ioa4 +__IO_EXTENDED IO_BYTE _ioal4; +#define IOAL4 _ioal4 +__IO_EXTENDED IO_BYTE _ioah4; +#define IOAH4 _ioah4 +__IO_EXTENDED IO_WORD _dct4; +#define DCT4 _dct4 +__IO_EXTENDED IO_BYTE _dctl4; +#define DCTL4 _dctl4 +__IO_EXTENDED IO_BYTE _dcth4; +#define DCTH4 _dcth4 +__IO_EXTENDED IO_BYTE _bapl5; +#define BAPL5 _bapl5 +__IO_EXTENDED IO_BYTE _bapm5; +#define BAPM5 _bapm5 +__IO_EXTENDED IO_BYTE _baph5; +#define BAPH5 _baph5 +__IO_EXTENDED DMACS5STR _dmacs5; +#define DMACS5 _dmacs5.byte +#define DMACS5_SE _dmacs5.bit._SE +#define DMACS5_DIR _dmacs5.bit._DIR +#define DMACS5_BF _dmacs5.bit._BF +#define DMACS5_BW _dmacs5.bit._BW +#define DMACS5_IF _dmacs5.bit._IF +#define DMACS5_BPD _dmacs5.bit._BPD +__IO_EXTENDED IO_WORD _ioa5; +#define IOA5 _ioa5 +__IO_EXTENDED IO_BYTE _ioal5; +#define IOAL5 _ioal5 +__IO_EXTENDED IO_BYTE _ioah5; +#define IOAH5 _ioah5 +__IO_EXTENDED IO_WORD _dct5; +#define DCT5 _dct5 +__IO_EXTENDED IO_BYTE _dctl5; +#define DCTL5 _dctl5 +__IO_EXTENDED IO_BYTE _dcth5; +#define DCTH5 _dcth5 +__IO_EXTENDED IO_BYTE _disel0; +#define DISEL0 _disel0 +__IO_EXTENDED IO_BYTE _disel1; +#define DISEL1 _disel1 +__IO_EXTENDED IO_BYTE _disel2; +#define DISEL2 _disel2 +__IO_EXTENDED IO_BYTE _disel3; +#define DISEL3 _disel3 +__IO_EXTENDED IO_BYTE _disel4; +#define DISEL4 _disel4 +__IO_EXTENDED IO_BYTE _disel5; +#define DISEL5 _disel5 +__IO_EXTENDED DSRSTR _dsr; +#define DSR _dsr.word +#define DSR_DTE0 _dsr.bit._DTE0 +#define DSR_DTE1 _dsr.bit._DTE1 +#define DSR_DTE2 _dsr.bit._DTE2 +#define DSR_DTE3 _dsr.bit._DTE3 +#define DSR_DTE4 _dsr.bit._DTE4 +#define DSR_DTE5 _dsr.bit._DTE5 +__IO_EXTENDED DSRLSTR _dsrl; +#define DSRL _dsrl.byte +#define DSRL_DTE0 _dsrl.bit._DTE0 +#define DSRL_DTE1 _dsrl.bit._DTE1 +#define DSRL_DTE2 _dsrl.bit._DTE2 +#define DSRL_DTE3 _dsrl.bit._DTE3 +#define DSRL_DTE4 _dsrl.bit._DTE4 +#define DSRL_DTE5 _dsrl.bit._DTE5 +__IO_EXTENDED IO_BYTE _dsrh; +#define DSRH _dsrh +__IO_EXTENDED DSSRSTR _dssr; +#define DSSR _dssr.word +#define DSSR_STP0 _dssr.bit._STP0 +#define DSSR_STP1 _dssr.bit._STP1 +#define DSSR_STP2 _dssr.bit._STP2 +#define DSSR_STP3 _dssr.bit._STP3 +#define DSSR_STP4 _dssr.bit._STP4 +#define DSSR_STP5 _dssr.bit._STP5 +__IO_EXTENDED DSSRLSTR _dssrl; +#define DSSRL _dssrl.byte +#define DSSRL_STP0 _dssrl.bit._STP0 +#define DSSRL_STP1 _dssrl.bit._STP1 +#define DSSRL_STP2 _dssrl.bit._STP2 +#define DSSRL_STP3 _dssrl.bit._STP3 +#define DSSRL_STP4 _dssrl.bit._STP4 +#define DSSRL_STP5 _dssrl.bit._STP5 +__IO_EXTENDED IO_BYTE _dssrh; +#define DSSRH _dssrh +__IO_EXTENDED DERSTR _der; +#define DER _der.word +#define DER_EN0 _der.bit._EN0 +#define DER_EN1 _der.bit._EN1 +#define DER_EN2 _der.bit._EN2 +#define DER_EN3 _der.bit._EN3 +#define DER_EN4 _der.bit._EN4 +#define DER_EN5 _der.bit._EN5 +__IO_EXTENDED DERLSTR _derl; +#define DERL _derl.byte +#define DERL_EN0 _derl.bit._EN0 +#define DERL_EN1 _derl.bit._EN1 +#define DERL_EN2 _derl.bit._EN2 +#define DERL_EN3 _derl.bit._EN3 +#define DERL_EN4 _derl.bit._EN4 +#define DERL_EN5 _derl.bit._EN5 +__IO_EXTENDED IO_BYTE _derh; +#define DERH _derh +__IO_EXTENDED ICRSTR _icr; +#define ICR _icr.word +#define ICR_IL0 _icr.bit._IL0 +#define ICR_IL1 _icr.bit._IL1 +#define ICR_IL2 _icr.bit._IL2 +#define ICR_IX0 _icr.bit._IX0 +#define ICR_IX1 _icr.bit._IX1 +#define ICR_IX2 _icr.bit._IX2 +#define ICR_IX3 _icr.bit._IX3 +#define ICR_IX4 _icr.bit._IX4 +#define ICR_IX5 _icr.bit._IX5 +#define ICR_IX6 _icr.bit._IX6 +#define ICR_IX7 _icr.bit._IX7 +#define ICR_IL _icr.bitc._IL +#define ICR_IX _icr.bitc._IX +__IO_EXTENDED ILRSTR _ilr; +#define ILR _ilr.byte +#define ILR_IL0 _ilr.bit._IL0 +#define ILR_IL1 _ilr.bit._IL1 +#define ILR_IL2 _ilr.bit._IL2 +#define ILR_IL _ilr.bitc._IL +__IO_EXTENDED IDXSTR _idx; +#define IDX _idx.byte +#define IDX_IX0 _idx.bit._IX0 +#define IDX_IX1 _idx.bit._IX1 +#define IDX_IX2 _idx.bit._IX2 +#define IDX_IX3 _idx.bit._IX3 +#define IDX_IX4 _idx.bit._IX4 +#define IDX_IX5 _idx.bit._IX5 +#define IDX_IX6 _idx.bit._IX6 +#define IDX_IX7 _idx.bit._IX7 +#define IDX_IX _idx.bitc._IX +__IO_EXTENDED TBRSTR _tbr; +#define TBR _tbr.word +#define TBR_TB10 _tbr.bit._TB10 +#define TBR_TB11 _tbr.bit._TB11 +#define TBR_TB12 _tbr.bit._TB12 +#define TBR_TB13 _tbr.bit._TB13 +#define TBR_TB14 _tbr.bit._TB14 +#define TBR_TB15 _tbr.bit._TB15 +#define TBR_TB16 _tbr.bit._TB16 +#define TBR_TB17 _tbr.bit._TB17 +#define TBR_TB18 _tbr.bit._TB18 +#define TBR_TB19 _tbr.bit._TB19 +#define TBR_TB20 _tbr.bit._TB20 +#define TBR_TB21 _tbr.bit._TB21 +#define TBR_TB22 _tbr.bit._TB22 +#define TBR_TB23 _tbr.bit._TB23 +__IO_EXTENDED TBRLSTR _tbrl; +#define TBRL _tbrl.byte +#define TBRL_TB10 _tbrl.bit._TB10 +#define TBRL_TB11 _tbrl.bit._TB11 +#define TBRL_TB12 _tbrl.bit._TB12 +#define TBRL_TB13 _tbrl.bit._TB13 +#define TBRL_TB14 _tbrl.bit._TB14 +#define TBRL_TB15 _tbrl.bit._TB15 +__IO_EXTENDED TBRHSTR _tbrh; +#define TBRH _tbrh.byte +#define TBRH_TB16 _tbrh.bit._TB16 +#define TBRH_TB17 _tbrh.bit._TB17 +#define TBRH_TB18 _tbrh.bit._TB18 +#define TBRH_TB19 _tbrh.bit._TB19 +#define TBRH_TB20 _tbrh.bit._TB20 +#define TBRH_TB21 _tbrh.bit._TB21 +#define TBRH_TB22 _tbrh.bit._TB22 +#define TBRH_TB23 _tbrh.bit._TB23 +__IO_EXTENDED DIRRSTR _dirr; +#define DIRR _dirr.byte +#define DIRR_R0 _dirr.bit._R0 +__IO_EXTENDED NMISTR _nmi; +#define NMI _nmi.byte +#define NMI_FLAG _nmi.bit._FLAG +#define NMI_EN _nmi.bit._EN +#define NMI_LEV _nmi.bit._LEV +#define NMI_INT9FIX _nmi.bit._INT9FIX +__IO_EXTENDED EDSU2STR _edsu2; +#define EDSU2 _edsu2.word +#define EDSU2_RSEL0 _edsu2.bit._RSEL0 +#define EDSU2_RSEL1 _edsu2.bit._RSEL1 +#define EDSU2_RSEL2 _edsu2.bit._RSEL2 +#define EDSU2_RSEL3 _edsu2.bit._RSEL3 +#define EDSU2_RSEL4 _edsu2.bit._RSEL4 +#define EDSU2_RSEL5 _edsu2.bit._RSEL5 +#define EDSU2_RSEL6 _edsu2.bit._RSEL6 +#define EDSU2_RSEL7 _edsu2.bit._RSEL7 +#define EDSU2_TSEL0 _edsu2.bit._TSEL0 +#define EDSU2_TSEL1 _edsu2.bit._TSEL1 +#define EDSU2_TSEL2 _edsu2.bit._TSEL2 +#define EDSU2_TSEL3 _edsu2.bit._TSEL3 +#define EDSU2_TSEL4 _edsu2.bit._TSEL4 +#define EDSU2_TSEL5 _edsu2.bit._TSEL5 +#define EDSU2_TSEL6 _edsu2.bit._TSEL6 +#define EDSU2_TSEL7 _edsu2.bit._TSEL7 +#define EDSU2_RSEL _edsu2.bitc._RSEL +#define EDSU2_TSEL _edsu2.bitc._TSEL +__IO_EXTENDED ROMMSTR _romm; +#define ROMM _romm.byte +#define ROMM_MI _romm.bit._MI +#define ROMM_SZ0 _romm.bit._SZ0 +#define ROMM_SZ1 _romm.bit._SZ1 +#define ROMM_BS0 _romm.bit._BS0 +#define ROMM_BS1 _romm.bit._BS1 +#define ROMM_BS2 _romm.bit._BS2 +#define ROMM_BS3 _romm.bit._BS3 +__IO_EXTENDED EDSUSTR _edsu; +#define EDSU _edsu.byte +#define EDSU_RINT _edsu.bit._RINT +#define EDSU_RIE _edsu.bit._RIE +#define EDSU_SEL0 _edsu.bit._SEL0 +#define EDSU_SEL1 _edsu.bit._SEL1 +#define EDSU_TINT _edsu.bit._TINT +#define EDSU_TIE _edsu.bit._TIE +#define EDSU_EN _edsu.bit._EN +#define EDSU_SEL _edsu.bitc._SEL +__IO_EXTENDED PFCS0STR _pfcs0; +#define PFCS0 _pfcs0.word +#define PFCS0_I0 _pfcs0.bit._I0 +#define PFCS0_I1 _pfcs0.bit._I1 +#define PFCS0_IE0 _pfcs0.bit._IE0 +#define PFCS0_IE1 _pfcs0.bit._IE1 +#define PFCS0_PE0 _pfcs0.bit._PE0 +#define PFCS0_PE1 _pfcs0.bit._PE1 +#define PFCS0_AR _pfcs0.bit._AR +#define PFCS0_AM _pfcs0.bit._AM +#define PFCS0_DMA _pfcs0.bit._DMA +#define PFCS0_CPU _pfcs0.bit._CPU +#define PFCS0_DATA _pfcs0.bit._DATA +#define PFCS0_CODE _pfcs0.bit._CODE +#define PFCS0_WORD _pfcs0.bit._WORD +#define PFCS0_BYTE _pfcs0.bit._BYTE +#define PFCS0_WRITE _pfcs0.bit._WRITE +#define PFCS0_READ _pfcs0.bit._READ +__IO_EXTENDED PFCS1STR _pfcs1; +#define PFCS1 _pfcs1.word +#define PFCS1_I0 _pfcs1.bit._I0 +#define PFCS1_I1 _pfcs1.bit._I1 +#define PFCS1_IE0 _pfcs1.bit._IE0 +#define PFCS1_IE1 _pfcs1.bit._IE1 +#define PFCS1_PE0 _pfcs1.bit._PE0 +#define PFCS1_PE1 _pfcs1.bit._PE1 +#define PFCS1_AR _pfcs1.bit._AR +#define PFCS1_AM _pfcs1.bit._AM +#define PFCS1_DMA _pfcs1.bit._DMA +#define PFCS1_CPU _pfcs1.bit._CPU +#define PFCS1_DATA _pfcs1.bit._DATA +#define PFCS1_CODE _pfcs1.bit._CODE +#define PFCS1_WORD _pfcs1.bit._WORD +#define PFCS1_BYTE _pfcs1.bit._BYTE +#define PFCS1_WRITE _pfcs1.bit._WRITE +#define PFCS1_READ _pfcs1.bit._READ +__IO_EXTENDED PFCS2STR _pfcs2; +#define PFCS2 _pfcs2.word +#define PFCS2_I0 _pfcs2.bit._I0 +#define PFCS2_I1 _pfcs2.bit._I1 +#define PFCS2_IE0 _pfcs2.bit._IE0 +#define PFCS2_IE1 _pfcs2.bit._IE1 +#define PFCS2_PE0 _pfcs2.bit._PE0 +#define PFCS2_PE1 _pfcs2.bit._PE1 +#define PFCS2_AR _pfcs2.bit._AR +#define PFCS2_AM _pfcs2.bit._AM +#define PFCS2_DMA _pfcs2.bit._DMA +#define PFCS2_CPU _pfcs2.bit._CPU +#define PFCS2_DATA _pfcs2.bit._DATA +#define PFCS2_CODE _pfcs2.bit._CODE +#define PFCS2_WORD _pfcs2.bit._WORD +#define PFCS2_BYTE _pfcs2.bit._BYTE +#define PFCS2_WRITE _pfcs2.bit._WRITE +#define PFCS2_READ _pfcs2.bit._READ +__IO_EXTENDED PFCS3STR _pfcs3; +#define PFCS3 _pfcs3.word +#define PFCS3_I0 _pfcs3.bit._I0 +#define PFCS3_I1 _pfcs3.bit._I1 +#define PFCS3_IE0 _pfcs3.bit._IE0 +#define PFCS3_IE1 _pfcs3.bit._IE1 +#define PFCS3_PE0 _pfcs3.bit._PE0 +#define PFCS3_PE1 _pfcs3.bit._PE1 +#define PFCS3_AR _pfcs3.bit._AR +#define PFCS3_AM _pfcs3.bit._AM +#define PFCS3_DMA _pfcs3.bit._DMA +#define PFCS3_CPU _pfcs3.bit._CPU +#define PFCS3_DATA _pfcs3.bit._DATA +#define PFCS3_CODE _pfcs3.bit._CODE +#define PFCS3_WORD _pfcs3.bit._WORD +#define PFCS3_BYTE _pfcs3.bit._BYTE +#define PFCS3_WRITE _pfcs3.bit._WRITE +#define PFCS3_READ _pfcs3.bit._READ +__IO_EXTENDED PFAL0STR _pfal0; +#define PFAL0 _pfal0.byte +#define PFAL0_PFA0 _pfal0.bit._PFA0 +#define PFAL0_PFA1 _pfal0.bit._PFA1 +#define PFAL0_PFA2 _pfal0.bit._PFA2 +#define PFAL0_PFA3 _pfal0.bit._PFA3 +#define PFAL0_PFA4 _pfal0.bit._PFA4 +#define PFAL0_PFA5 _pfal0.bit._PFA5 +#define PFAL0_PFA6 _pfal0.bit._PFA6 +#define PFAL0_PFA7 _pfal0.bit._PFA7 +__IO_EXTENDED PFAM0STR _pfam0; +#define PFAM0 _pfam0.byte +#define PFAM0_PFA8 _pfam0.bit._PFA8 +#define PFAM0_PFA9 _pfam0.bit._PFA9 +#define PFAM0_PFA10 _pfam0.bit._PFA10 +#define PFAM0_PFA11 _pfam0.bit._PFA11 +#define PFAM0_PFA12 _pfam0.bit._PFA12 +#define PFAM0_PFA13 _pfam0.bit._PFA13 +#define PFAM0_PFA14 _pfam0.bit._PFA14 +#define PFAM0_PFA15 _pfam0.bit._PFA15 +__IO_EXTENDED PFAH0STR _pfah0; +#define PFAH0 _pfah0.byte +#define PFAH0_PFA16 _pfah0.bit._PFA16 +#define PFAH0_PFA17 _pfah0.bit._PFA17 +#define PFAH0_PFA18 _pfah0.bit._PFA18 +#define PFAH0_PFA19 _pfah0.bit._PFA19 +#define PFAH0_PFA20 _pfah0.bit._PFA20 +#define PFAH0_PFA21 _pfah0.bit._PFA21 +#define PFAH0_PFA22 _pfah0.bit._PFA22 +#define PFAH0_PFA23 _pfah0.bit._PFA23 +__IO_EXTENDED PFAL1STR _pfal1; +#define PFAL1 _pfal1.byte +#define PFAL1_PFA0 _pfal1.bit._PFA0 +#define PFAL1_PFA1 _pfal1.bit._PFA1 +#define PFAL1_PFA2 _pfal1.bit._PFA2 +#define PFAL1_PFA3 _pfal1.bit._PFA3 +#define PFAL1_PFA4 _pfal1.bit._PFA4 +#define PFAL1_PFA5 _pfal1.bit._PFA5 +#define PFAL1_PFA6 _pfal1.bit._PFA6 +#define PFAL1_PFA7 _pfal1.bit._PFA7 +__IO_EXTENDED PFAM1STR _pfam1; +#define PFAM1 _pfam1.byte +#define PFAM1_PFA8 _pfam1.bit._PFA8 +#define PFAM1_PFA9 _pfam1.bit._PFA9 +#define PFAM1_PFA10 _pfam1.bit._PFA10 +#define PFAM1_PFA11 _pfam1.bit._PFA11 +#define PFAM1_PFA12 _pfam1.bit._PFA12 +#define PFAM1_PFA13 _pfam1.bit._PFA13 +#define PFAM1_PFA14 _pfam1.bit._PFA14 +#define PFAM1_PFA15 _pfam1.bit._PFA15 +__IO_EXTENDED PFAH1STR _pfah1; +#define PFAH1 _pfah1.byte +#define PFAH1_PFA16 _pfah1.bit._PFA16 +#define PFAH1_PFA17 _pfah1.bit._PFA17 +#define PFAH1_PFA18 _pfah1.bit._PFA18 +#define PFAH1_PFA19 _pfah1.bit._PFA19 +#define PFAH1_PFA20 _pfah1.bit._PFA20 +#define PFAH1_PFA21 _pfah1.bit._PFA21 +#define PFAH1_PFA22 _pfah1.bit._PFA22 +#define PFAH1_PFA23 _pfah1.bit._PFA23 +__IO_EXTENDED PFAL2STR _pfal2; +#define PFAL2 _pfal2.byte +#define PFAL2_PFA0 _pfal2.bit._PFA0 +#define PFAL2_PFA1 _pfal2.bit._PFA1 +#define PFAL2_PFA2 _pfal2.bit._PFA2 +#define PFAL2_PFA3 _pfal2.bit._PFA3 +#define PFAL2_PFA4 _pfal2.bit._PFA4 +#define PFAL2_PFA5 _pfal2.bit._PFA5 +#define PFAL2_PFA6 _pfal2.bit._PFA6 +#define PFAL2_PFA7 _pfal2.bit._PFA7 +__IO_EXTENDED PFAM2STR _pfam2; +#define PFAM2 _pfam2.byte +#define PFAM2_PFA8 _pfam2.bit._PFA8 +#define PFAM2_PFA9 _pfam2.bit._PFA9 +#define PFAM2_PFA10 _pfam2.bit._PFA10 +#define PFAM2_PFA11 _pfam2.bit._PFA11 +#define PFAM2_PFA12 _pfam2.bit._PFA12 +#define PFAM2_PFA13 _pfam2.bit._PFA13 +#define PFAM2_PFA14 _pfam2.bit._PFA14 +#define PFAM2_PFA15 _pfam2.bit._PFA15 +__IO_EXTENDED PFAH2STR _pfah2; +#define PFAH2 _pfah2.byte +#define PFAH2_PFA16 _pfah2.bit._PFA16 +#define PFAH2_PFA17 _pfah2.bit._PFA17 +#define PFAH2_PFA18 _pfah2.bit._PFA18 +#define PFAH2_PFA19 _pfah2.bit._PFA19 +#define PFAH2_PFA20 _pfah2.bit._PFA20 +#define PFAH2_PFA21 _pfah2.bit._PFA21 +#define PFAH2_PFA22 _pfah2.bit._PFA22 +#define PFAH2_PFA23 _pfah2.bit._PFA23 +__IO_EXTENDED PFAL3STR _pfal3; +#define PFAL3 _pfal3.byte +#define PFAL3_PFA0 _pfal3.bit._PFA0 +#define PFAL3_PFA1 _pfal3.bit._PFA1 +#define PFAL3_PFA2 _pfal3.bit._PFA2 +#define PFAL3_PFA3 _pfal3.bit._PFA3 +#define PFAL3_PFA4 _pfal3.bit._PFA4 +#define PFAL3_PFA5 _pfal3.bit._PFA5 +#define PFAL3_PFA6 _pfal3.bit._PFA6 +#define PFAL3_PFA7 _pfal3.bit._PFA7 +__IO_EXTENDED PFAM3STR _pfam3; +#define PFAM3 _pfam3.byte +#define PFAM3_PFA8 _pfam3.bit._PFA8 +#define PFAM3_PFA9 _pfam3.bit._PFA9 +#define PFAM3_PFA10 _pfam3.bit._PFA10 +#define PFAM3_PFA11 _pfam3.bit._PFA11 +#define PFAM3_PFA12 _pfam3.bit._PFA12 +#define PFAM3_PFA13 _pfam3.bit._PFA13 +#define PFAM3_PFA14 _pfam3.bit._PFA14 +#define PFAM3_PFA15 _pfam3.bit._PFA15 +__IO_EXTENDED PFAH3STR _pfah3; +#define PFAH3 _pfah3.byte +#define PFAH3_PFA16 _pfah3.bit._PFA16 +#define PFAH3_PFA17 _pfah3.bit._PFA17 +#define PFAH3_PFA18 _pfah3.bit._PFA18 +#define PFAH3_PFA19 _pfah3.bit._PFA19 +#define PFAH3_PFA20 _pfah3.bit._PFA20 +#define PFAH3_PFA21 _pfah3.bit._PFA21 +#define PFAH3_PFA22 _pfah3.bit._PFA22 +#define PFAH3_PFA23 _pfah3.bit._PFA23 +__IO_EXTENDED PFAL4STR _pfal4; +#define PFAL4 _pfal4.byte +#define PFAL4_PFA0 _pfal4.bit._PFA0 +#define PFAL4_PFA1 _pfal4.bit._PFA1 +#define PFAL4_PFA2 _pfal4.bit._PFA2 +#define PFAL4_PFA3 _pfal4.bit._PFA3 +#define PFAL4_PFA4 _pfal4.bit._PFA4 +#define PFAL4_PFA5 _pfal4.bit._PFA5 +#define PFAL4_PFA6 _pfal4.bit._PFA6 +#define PFAL4_PFA7 _pfal4.bit._PFA7 +__IO_EXTENDED PFAM4STR _pfam4; +#define PFAM4 _pfam4.byte +#define PFAM4_PFA8 _pfam4.bit._PFA8 +#define PFAM4_PFA9 _pfam4.bit._PFA9 +#define PFAM4_PFA10 _pfam4.bit._PFA10 +#define PFAM4_PFA11 _pfam4.bit._PFA11 +#define PFAM4_PFA12 _pfam4.bit._PFA12 +#define PFAM4_PFA13 _pfam4.bit._PFA13 +#define PFAM4_PFA14 _pfam4.bit._PFA14 +#define PFAM4_PFA15 _pfam4.bit._PFA15 +__IO_EXTENDED PFAH4STR _pfah4; +#define PFAH4 _pfah4.byte +#define PFAH4_PFA16 _pfah4.bit._PFA16 +#define PFAH4_PFA17 _pfah4.bit._PFA17 +#define PFAH4_PFA18 _pfah4.bit._PFA18 +#define PFAH4_PFA19 _pfah4.bit._PFA19 +#define PFAH4_PFA20 _pfah4.bit._PFA20 +#define PFAH4_PFA21 _pfah4.bit._PFA21 +#define PFAH4_PFA22 _pfah4.bit._PFA22 +#define PFAH4_PFA23 _pfah4.bit._PFA23 +__IO_EXTENDED PFAL5STR _pfal5; +#define PFAL5 _pfal5.byte +#define PFAL5_PFA0 _pfal5.bit._PFA0 +#define PFAL5_PFA1 _pfal5.bit._PFA1 +#define PFAL5_PFA2 _pfal5.bit._PFA2 +#define PFAL5_PFA3 _pfal5.bit._PFA3 +#define PFAL5_PFA4 _pfal5.bit._PFA4 +#define PFAL5_PFA5 _pfal5.bit._PFA5 +#define PFAL5_PFA6 _pfal5.bit._PFA6 +#define PFAL5_PFA7 _pfal5.bit._PFA7 +__IO_EXTENDED PFAM5STR _pfam5; +#define PFAM5 _pfam5.byte +#define PFAM5_PFA8 _pfam5.bit._PFA8 +#define PFAM5_PFA9 _pfam5.bit._PFA9 +#define PFAM5_PFA10 _pfam5.bit._PFA10 +#define PFAM5_PFA11 _pfam5.bit._PFA11 +#define PFAM5_PFA12 _pfam5.bit._PFA12 +#define PFAM5_PFA13 _pfam5.bit._PFA13 +#define PFAM5_PFA14 _pfam5.bit._PFA14 +#define PFAM5_PFA15 _pfam5.bit._PFA15 +__IO_EXTENDED PFAH5STR _pfah5; +#define PFAH5 _pfah5.byte +#define PFAH5_PFA16 _pfah5.bit._PFA16 +#define PFAH5_PFA17 _pfah5.bit._PFA17 +#define PFAH5_PFA18 _pfah5.bit._PFA18 +#define PFAH5_PFA19 _pfah5.bit._PFA19 +#define PFAH5_PFA20 _pfah5.bit._PFA20 +#define PFAH5_PFA21 _pfah5.bit._PFA21 +#define PFAH5_PFA22 _pfah5.bit._PFA22 +#define PFAH5_PFA23 _pfah5.bit._PFA23 +__IO_EXTENDED PFAL6STR _pfal6; +#define PFAL6 _pfal6.byte +#define PFAL6_PFA0 _pfal6.bit._PFA0 +#define PFAL6_PFA1 _pfal6.bit._PFA1 +#define PFAL6_PFA2 _pfal6.bit._PFA2 +#define PFAL6_PFA3 _pfal6.bit._PFA3 +#define PFAL6_PFA4 _pfal6.bit._PFA4 +#define PFAL6_PFA5 _pfal6.bit._PFA5 +#define PFAL6_PFA6 _pfal6.bit._PFA6 +#define PFAL6_PFA7 _pfal6.bit._PFA7 +__IO_EXTENDED PFAM6STR _pfam6; +#define PFAM6 _pfam6.byte +#define PFAM6_PFA8 _pfam6.bit._PFA8 +#define PFAM6_PFA9 _pfam6.bit._PFA9 +#define PFAM6_PFA10 _pfam6.bit._PFA10 +#define PFAM6_PFA11 _pfam6.bit._PFA11 +#define PFAM6_PFA12 _pfam6.bit._PFA12 +#define PFAM6_PFA13 _pfam6.bit._PFA13 +#define PFAM6_PFA14 _pfam6.bit._PFA14 +#define PFAM6_PFA15 _pfam6.bit._PFA15 +__IO_EXTENDED PFAH6STR _pfah6; +#define PFAH6 _pfah6.byte +#define PFAH6_PFA16 _pfah6.bit._PFA16 +#define PFAH6_PFA17 _pfah6.bit._PFA17 +#define PFAH6_PFA18 _pfah6.bit._PFA18 +#define PFAH6_PFA19 _pfah6.bit._PFA19 +#define PFAH6_PFA20 _pfah6.bit._PFA20 +#define PFAH6_PFA21 _pfah6.bit._PFA21 +#define PFAH6_PFA22 _pfah6.bit._PFA22 +#define PFAH6_PFA23 _pfah6.bit._PFA23 +__IO_EXTENDED PFAL7STR _pfal7; +#define PFAL7 _pfal7.byte +#define PFAL7_PFA0 _pfal7.bit._PFA0 +#define PFAL7_PFA1 _pfal7.bit._PFA1 +#define PFAL7_PFA2 _pfal7.bit._PFA2 +#define PFAL7_PFA3 _pfal7.bit._PFA3 +#define PFAL7_PFA4 _pfal7.bit._PFA4 +#define PFAL7_PFA5 _pfal7.bit._PFA5 +#define PFAL7_PFA6 _pfal7.bit._PFA6 +#define PFAL7_PFA7 _pfal7.bit._PFA7 +__IO_EXTENDED PFAM7STR _pfam7; +#define PFAM7 _pfam7.byte +#define PFAM7_PFA8 _pfam7.bit._PFA8 +#define PFAM7_PFA9 _pfam7.bit._PFA9 +#define PFAM7_PFA10 _pfam7.bit._PFA10 +#define PFAM7_PFA11 _pfam7.bit._PFA11 +#define PFAM7_PFA12 _pfam7.bit._PFA12 +#define PFAM7_PFA13 _pfam7.bit._PFA13 +#define PFAM7_PFA14 _pfam7.bit._PFA14 +#define PFAM7_PFA15 _pfam7.bit._PFA15 +__IO_EXTENDED PFAH7STR _pfah7; +#define PFAH7 _pfah7.byte +#define PFAH7_PFA16 _pfah7.bit._PFA16 +#define PFAH7_PFA17 _pfah7.bit._PFA17 +#define PFAH7_PFA18 _pfah7.bit._PFA18 +#define PFAH7_PFA19 _pfah7.bit._PFA19 +#define PFAH7_PFA20 _pfah7.bit._PFA20 +#define PFAH7_PFA21 _pfah7.bit._PFA21 +#define PFAH7_PFA22 _pfah7.bit._PFA22 +#define PFAH7_PFA23 _pfah7.bit._PFA23 +__IO_EXTENDED PFD0STR _pfd0; +#define PFD0 _pfd0.word +#define PFD0_PFD0 _pfd0.bit._PFD0 +#define PFD0_PFD1 _pfd0.bit._PFD1 +#define PFD0_PFD2 _pfd0.bit._PFD2 +#define PFD0_PFD3 _pfd0.bit._PFD3 +#define PFD0_PFD4 _pfd0.bit._PFD4 +#define PFD0_PFD5 _pfd0.bit._PFD5 +#define PFD0_PFD6 _pfd0.bit._PFD6 +#define PFD0_PFD7 _pfd0.bit._PFD7 +#define PFD0_PFD8 _pfd0.bit._PFD8 +#define PFD0_PFD9 _pfd0.bit._PFD9 +#define PFD0_PFD10 _pfd0.bit._PFD10 +#define PFD0_PFD11 _pfd0.bit._PFD11 +#define PFD0_PFD12 _pfd0.bit._PFD12 +#define PFD0_PFD13 _pfd0.bit._PFD13 +#define PFD0_PFD14 _pfd0.bit._PFD14 +#define PFD0_PFD15 _pfd0.bit._PFD15 +#define PFD0_PFD _pfd0.bitc._PFD +__IO_EXTENDED PFDL0STR _pfdl0; +#define PFDL0 _pfdl0.byte +#define PFDL0_PFD0 _pfdl0.bit._PFD0 +#define PFDL0_PFD1 _pfdl0.bit._PFD1 +#define PFDL0_PFD2 _pfdl0.bit._PFD2 +#define PFDL0_PFD3 _pfdl0.bit._PFD3 +#define PFDL0_PFD4 _pfdl0.bit._PFD4 +#define PFDL0_PFD5 _pfdl0.bit._PFD5 +#define PFDL0_PFD6 _pfdl0.bit._PFD6 +#define PFDL0_PFD7 _pfdl0.bit._PFD7 +__IO_EXTENDED PFDH0STR _pfdh0; +#define PFDH0 _pfdh0.byte +#define PFDH0_PFD8 _pfdh0.bit._PFD8 +#define PFDH0_PFD9 _pfdh0.bit._PFD9 +#define PFDH0_PFD10 _pfdh0.bit._PFD10 +#define PFDH0_PFD11 _pfdh0.bit._PFD11 +#define PFDH0_PFD12 _pfdh0.bit._PFD12 +#define PFDH0_PFD13 _pfdh0.bit._PFD13 +#define PFDH0_PFD14 _pfdh0.bit._PFD14 +#define PFDH0_PFD15 _pfdh0.bit._PFD15 +__IO_EXTENDED PFD1STR _pfd1; +#define PFD1 _pfd1.word +#define PFD1_PFD0 _pfd1.bit._PFD0 +#define PFD1_PFD1 _pfd1.bit._PFD1 +#define PFD1_PFD2 _pfd1.bit._PFD2 +#define PFD1_PFD3 _pfd1.bit._PFD3 +#define PFD1_PFD4 _pfd1.bit._PFD4 +#define PFD1_PFD5 _pfd1.bit._PFD5 +#define PFD1_PFD6 _pfd1.bit._PFD6 +#define PFD1_PFD7 _pfd1.bit._PFD7 +#define PFD1_PFD8 _pfd1.bit._PFD8 +#define PFD1_PFD9 _pfd1.bit._PFD9 +#define PFD1_PFD10 _pfd1.bit._PFD10 +#define PFD1_PFD11 _pfd1.bit._PFD11 +#define PFD1_PFD12 _pfd1.bit._PFD12 +#define PFD1_PFD13 _pfd1.bit._PFD13 +#define PFD1_PFD14 _pfd1.bit._PFD14 +#define PFD1_PFD15 _pfd1.bit._PFD15 +#define PFD1_PFD _pfd1.bitc._PFD +__IO_EXTENDED PFDL1STR _pfdl1; +#define PFDL1 _pfdl1.byte +#define PFDL1_PFD0 _pfdl1.bit._PFD0 +#define PFDL1_PFD1 _pfdl1.bit._PFD1 +#define PFDL1_PFD2 _pfdl1.bit._PFD2 +#define PFDL1_PFD3 _pfdl1.bit._PFD3 +#define PFDL1_PFD4 _pfdl1.bit._PFD4 +#define PFDL1_PFD5 _pfdl1.bit._PFD5 +#define PFDL1_PFD6 _pfdl1.bit._PFD6 +#define PFDL1_PFD7 _pfdl1.bit._PFD7 +__IO_EXTENDED PFDH1STR _pfdh1; +#define PFDH1 _pfdh1.byte +#define PFDH1_PFD8 _pfdh1.bit._PFD8 +#define PFDH1_PFD9 _pfdh1.bit._PFD9 +#define PFDH1_PFD10 _pfdh1.bit._PFD10 +#define PFDH1_PFD11 _pfdh1.bit._PFD11 +#define PFDH1_PFD12 _pfdh1.bit._PFD12 +#define PFDH1_PFD13 _pfdh1.bit._PFD13 +#define PFDH1_PFD14 _pfdh1.bit._PFD14 +#define PFDH1_PFD15 _pfdh1.bit._PFD15 +__IO_EXTENDED PFD2STR _pfd2; +#define PFD2 _pfd2.word +#define PFD2_PFD0 _pfd2.bit._PFD0 +#define PFD2_PFD1 _pfd2.bit._PFD1 +#define PFD2_PFD2 _pfd2.bit._PFD2 +#define PFD2_PFD3 _pfd2.bit._PFD3 +#define PFD2_PFD4 _pfd2.bit._PFD4 +#define PFD2_PFD5 _pfd2.bit._PFD5 +#define PFD2_PFD6 _pfd2.bit._PFD6 +#define PFD2_PFD7 _pfd2.bit._PFD7 +#define PFD2_PFD8 _pfd2.bit._PFD8 +#define PFD2_PFD9 _pfd2.bit._PFD9 +#define PFD2_PFD10 _pfd2.bit._PFD10 +#define PFD2_PFD11 _pfd2.bit._PFD11 +#define PFD2_PFD12 _pfd2.bit._PFD12 +#define PFD2_PFD13 _pfd2.bit._PFD13 +#define PFD2_PFD14 _pfd2.bit._PFD14 +#define PFD2_PFD15 _pfd2.bit._PFD15 +#define PFD2_PFD _pfd2.bitc._PFD +__IO_EXTENDED PFDL2STR _pfdl2; +#define PFDL2 _pfdl2.byte +#define PFDL2_PFD0 _pfdl2.bit._PFD0 +#define PFDL2_PFD1 _pfdl2.bit._PFD1 +#define PFDL2_PFD2 _pfdl2.bit._PFD2 +#define PFDL2_PFD3 _pfdl2.bit._PFD3 +#define PFDL2_PFD4 _pfdl2.bit._PFD4 +#define PFDL2_PFD5 _pfdl2.bit._PFD5 +#define PFDL2_PFD6 _pfdl2.bit._PFD6 +#define PFDL2_PFD7 _pfdl2.bit._PFD7 +__IO_EXTENDED PFDH2STR _pfdh2; +#define PFDH2 _pfdh2.byte +#define PFDH2_PFD8 _pfdh2.bit._PFD8 +#define PFDH2_PFD9 _pfdh2.bit._PFD9 +#define PFDH2_PFD10 _pfdh2.bit._PFD10 +#define PFDH2_PFD11 _pfdh2.bit._PFD11 +#define PFDH2_PFD12 _pfdh2.bit._PFD12 +#define PFDH2_PFD13 _pfdh2.bit._PFD13 +#define PFDH2_PFD14 _pfdh2.bit._PFD14 +#define PFDH2_PFD15 _pfdh2.bit._PFD15 +__IO_EXTENDED PFD3STR _pfd3; +#define PFD3 _pfd3.word +#define PFD3_PFD0 _pfd3.bit._PFD0 +#define PFD3_PFD1 _pfd3.bit._PFD1 +#define PFD3_PFD2 _pfd3.bit._PFD2 +#define PFD3_PFD3 _pfd3.bit._PFD3 +#define PFD3_PFD4 _pfd3.bit._PFD4 +#define PFD3_PFD5 _pfd3.bit._PFD5 +#define PFD3_PFD6 _pfd3.bit._PFD6 +#define PFD3_PFD7 _pfd3.bit._PFD7 +#define PFD3_PFD8 _pfd3.bit._PFD8 +#define PFD3_PFD9 _pfd3.bit._PFD9 +#define PFD3_PFD10 _pfd3.bit._PFD10 +#define PFD3_PFD11 _pfd3.bit._PFD11 +#define PFD3_PFD12 _pfd3.bit._PFD12 +#define PFD3_PFD13 _pfd3.bit._PFD13 +#define PFD3_PFD14 _pfd3.bit._PFD14 +#define PFD3_PFD15 _pfd3.bit._PFD15 +#define PFD3_PFD _pfd3.bitc._PFD +__IO_EXTENDED PFDL3STR _pfdl3; +#define PFDL3 _pfdl3.byte +#define PFDL3_PFD0 _pfdl3.bit._PFD0 +#define PFDL3_PFD1 _pfdl3.bit._PFD1 +#define PFDL3_PFD2 _pfdl3.bit._PFD2 +#define PFDL3_PFD3 _pfdl3.bit._PFD3 +#define PFDL3_PFD4 _pfdl3.bit._PFD4 +#define PFDL3_PFD5 _pfdl3.bit._PFD5 +#define PFDL3_PFD6 _pfdl3.bit._PFD6 +#define PFDL3_PFD7 _pfdl3.bit._PFD7 +__IO_EXTENDED PFDH3STR _pfdh3; +#define PFDH3 _pfdh3.byte +#define PFDH3_PFD8 _pfdh3.bit._PFD8 +#define PFDH3_PFD9 _pfdh3.bit._PFD9 +#define PFDH3_PFD10 _pfdh3.bit._PFD10 +#define PFDH3_PFD11 _pfdh3.bit._PFD11 +#define PFDH3_PFD12 _pfdh3.bit._PFD12 +#define PFDH3_PFD13 _pfdh3.bit._PFD13 +#define PFDH3_PFD14 _pfdh3.bit._PFD14 +#define PFDH3_PFD15 _pfdh3.bit._PFD15 +__IO_EXTENDED PFD4STR _pfd4; +#define PFD4 _pfd4.word +#define PFD4_PFD0 _pfd4.bit._PFD0 +#define PFD4_PFD1 _pfd4.bit._PFD1 +#define PFD4_PFD2 _pfd4.bit._PFD2 +#define PFD4_PFD3 _pfd4.bit._PFD3 +#define PFD4_PFD4 _pfd4.bit._PFD4 +#define PFD4_PFD5 _pfd4.bit._PFD5 +#define PFD4_PFD6 _pfd4.bit._PFD6 +#define PFD4_PFD7 _pfd4.bit._PFD7 +#define PFD4_PFD8 _pfd4.bit._PFD8 +#define PFD4_PFD9 _pfd4.bit._PFD9 +#define PFD4_PFD10 _pfd4.bit._PFD10 +#define PFD4_PFD11 _pfd4.bit._PFD11 +#define PFD4_PFD12 _pfd4.bit._PFD12 +#define PFD4_PFD13 _pfd4.bit._PFD13 +#define PFD4_PFD14 _pfd4.bit._PFD14 +#define PFD4_PFD15 _pfd4.bit._PFD15 +#define PFD4_PFD _pfd4.bitc._PFD +__IO_EXTENDED PFDL4STR _pfdl4; +#define PFDL4 _pfdl4.byte +#define PFDL4_PFD0 _pfdl4.bit._PFD0 +#define PFDL4_PFD1 _pfdl4.bit._PFD1 +#define PFDL4_PFD2 _pfdl4.bit._PFD2 +#define PFDL4_PFD3 _pfdl4.bit._PFD3 +#define PFDL4_PFD4 _pfdl4.bit._PFD4 +#define PFDL4_PFD5 _pfdl4.bit._PFD5 +#define PFDL4_PFD6 _pfdl4.bit._PFD6 +#define PFDL4_PFD7 _pfdl4.bit._PFD7 +__IO_EXTENDED PFDH4STR _pfdh4; +#define PFDH4 _pfdh4.byte +#define PFDH4_PFD8 _pfdh4.bit._PFD8 +#define PFDH4_PFD9 _pfdh4.bit._PFD9 +#define PFDH4_PFD10 _pfdh4.bit._PFD10 +#define PFDH4_PFD11 _pfdh4.bit._PFD11 +#define PFDH4_PFD12 _pfdh4.bit._PFD12 +#define PFDH4_PFD13 _pfdh4.bit._PFD13 +#define PFDH4_PFD14 _pfdh4.bit._PFD14 +#define PFDH4_PFD15 _pfdh4.bit._PFD15 +__IO_EXTENDED PFD5STR _pfd5; +#define PFD5 _pfd5.word +#define PFD5_PFD0 _pfd5.bit._PFD0 +#define PFD5_PFD1 _pfd5.bit._PFD1 +#define PFD5_PFD2 _pfd5.bit._PFD2 +#define PFD5_PFD3 _pfd5.bit._PFD3 +#define PFD5_PFD4 _pfd5.bit._PFD4 +#define PFD5_PFD5 _pfd5.bit._PFD5 +#define PFD5_PFD6 _pfd5.bit._PFD6 +#define PFD5_PFD7 _pfd5.bit._PFD7 +#define PFD5_PFD8 _pfd5.bit._PFD8 +#define PFD5_PFD9 _pfd5.bit._PFD9 +#define PFD5_PFD10 _pfd5.bit._PFD10 +#define PFD5_PFD11 _pfd5.bit._PFD11 +#define PFD5_PFD12 _pfd5.bit._PFD12 +#define PFD5_PFD13 _pfd5.bit._PFD13 +#define PFD5_PFD14 _pfd5.bit._PFD14 +#define PFD5_PFD15 _pfd5.bit._PFD15 +#define PFD5_PFD _pfd5.bitc._PFD +__IO_EXTENDED PFDL5STR _pfdl5; +#define PFDL5 _pfdl5.byte +#define PFDL5_PFD0 _pfdl5.bit._PFD0 +#define PFDL5_PFD1 _pfdl5.bit._PFD1 +#define PFDL5_PFD2 _pfdl5.bit._PFD2 +#define PFDL5_PFD3 _pfdl5.bit._PFD3 +#define PFDL5_PFD4 _pfdl5.bit._PFD4 +#define PFDL5_PFD5 _pfdl5.bit._PFD5 +#define PFDL5_PFD6 _pfdl5.bit._PFD6 +#define PFDL5_PFD7 _pfdl5.bit._PFD7 +__IO_EXTENDED PFDH5STR _pfdh5; +#define PFDH5 _pfdh5.byte +#define PFDH5_PFD8 _pfdh5.bit._PFD8 +#define PFDH5_PFD9 _pfdh5.bit._PFD9 +#define PFDH5_PFD10 _pfdh5.bit._PFD10 +#define PFDH5_PFD11 _pfdh5.bit._PFD11 +#define PFDH5_PFD12 _pfdh5.bit._PFD12 +#define PFDH5_PFD13 _pfdh5.bit._PFD13 +#define PFDH5_PFD14 _pfdh5.bit._PFD14 +#define PFDH5_PFD15 _pfdh5.bit._PFD15 +__IO_EXTENDED PFD6STR _pfd6; +#define PFD6 _pfd6.word +#define PFD6_PFD0 _pfd6.bit._PFD0 +#define PFD6_PFD1 _pfd6.bit._PFD1 +#define PFD6_PFD2 _pfd6.bit._PFD2 +#define PFD6_PFD3 _pfd6.bit._PFD3 +#define PFD6_PFD4 _pfd6.bit._PFD4 +#define PFD6_PFD5 _pfd6.bit._PFD5 +#define PFD6_PFD6 _pfd6.bit._PFD6 +#define PFD6_PFD7 _pfd6.bit._PFD7 +#define PFD6_PFD8 _pfd6.bit._PFD8 +#define PFD6_PFD9 _pfd6.bit._PFD9 +#define PFD6_PFD10 _pfd6.bit._PFD10 +#define PFD6_PFD11 _pfd6.bit._PFD11 +#define PFD6_PFD12 _pfd6.bit._PFD12 +#define PFD6_PFD13 _pfd6.bit._PFD13 +#define PFD6_PFD14 _pfd6.bit._PFD14 +#define PFD6_PFD15 _pfd6.bit._PFD15 +#define PFD6_PFD _pfd6.bitc._PFD +__IO_EXTENDED PFDL6STR _pfdl6; +#define PFDL6 _pfdl6.byte +#define PFDL6_PFD0 _pfdl6.bit._PFD0 +#define PFDL6_PFD1 _pfdl6.bit._PFD1 +#define PFDL6_PFD2 _pfdl6.bit._PFD2 +#define PFDL6_PFD3 _pfdl6.bit._PFD3 +#define PFDL6_PFD4 _pfdl6.bit._PFD4 +#define PFDL6_PFD5 _pfdl6.bit._PFD5 +#define PFDL6_PFD6 _pfdl6.bit._PFD6 +#define PFDL6_PFD7 _pfdl6.bit._PFD7 +__IO_EXTENDED PFDH6STR _pfdh6; +#define PFDH6 _pfdh6.byte +#define PFDH6_PFD8 _pfdh6.bit._PFD8 +#define PFDH6_PFD9 _pfdh6.bit._PFD9 +#define PFDH6_PFD10 _pfdh6.bit._PFD10 +#define PFDH6_PFD11 _pfdh6.bit._PFD11 +#define PFDH6_PFD12 _pfdh6.bit._PFD12 +#define PFDH6_PFD13 _pfdh6.bit._PFD13 +#define PFDH6_PFD14 _pfdh6.bit._PFD14 +#define PFDH6_PFD15 _pfdh6.bit._PFD15 +__IO_EXTENDED PFD7STR _pfd7; +#define PFD7 _pfd7.word +#define PFD7_PFD0 _pfd7.bit._PFD0 +#define PFD7_PFD1 _pfd7.bit._PFD1 +#define PFD7_PFD2 _pfd7.bit._PFD2 +#define PFD7_PFD3 _pfd7.bit._PFD3 +#define PFD7_PFD4 _pfd7.bit._PFD4 +#define PFD7_PFD5 _pfd7.bit._PFD5 +#define PFD7_PFD6 _pfd7.bit._PFD6 +#define PFD7_PFD7 _pfd7.bit._PFD7 +#define PFD7_PFD8 _pfd7.bit._PFD8 +#define PFD7_PFD9 _pfd7.bit._PFD9 +#define PFD7_PFD10 _pfd7.bit._PFD10 +#define PFD7_PFD11 _pfd7.bit._PFD11 +#define PFD7_PFD12 _pfd7.bit._PFD12 +#define PFD7_PFD13 _pfd7.bit._PFD13 +#define PFD7_PFD14 _pfd7.bit._PFD14 +#define PFD7_PFD15 _pfd7.bit._PFD15 +#define PFD7_PFD _pfd7.bitc._PFD +__IO_EXTENDED PFDL7STR _pfdl7; +#define PFDL7 _pfdl7.byte +#define PFDL7_PFD0 _pfdl7.bit._PFD0 +#define PFDL7_PFD1 _pfdl7.bit._PFD1 +#define PFDL7_PFD2 _pfdl7.bit._PFD2 +#define PFDL7_PFD3 _pfdl7.bit._PFD3 +#define PFDL7_PFD4 _pfdl7.bit._PFD4 +#define PFDL7_PFD5 _pfdl7.bit._PFD5 +#define PFDL7_PFD6 _pfdl7.bit._PFD6 +#define PFDL7_PFD7 _pfdl7.bit._PFD7 +__IO_EXTENDED PFDH7STR _pfdh7; +#define PFDH7 _pfdh7.byte +#define PFDH7_PFD8 _pfdh7.bit._PFD8 +#define PFDH7_PFD9 _pfdh7.bit._PFD9 +#define PFDH7_PFD10 _pfdh7.bit._PFD10 +#define PFDH7_PFD11 _pfdh7.bit._PFD11 +#define PFDH7_PFD12 _pfdh7.bit._PFD12 +#define PFDH7_PFD13 _pfdh7.bit._PFD13 +#define PFDH7_PFD14 _pfdh7.bit._PFD14 +#define PFDH7_PFD15 _pfdh7.bit._PFD15 +__IO_EXTENDED MFMCSSTR _mfmcs; +#define MFMCS _mfmcs.byte +#define MFMCS_RDY _mfmcs.bit._RDY +#define MFMCS_RDYINT _mfmcs.bit._RDYINT +#define MFMCS_INTE _mfmcs.bit._INTE +#define MFMCS_WE _mfmcs.bit._WE +#define MFMCS_CRBE _mfmcs.bit._CRBE +#define MFMCS_DRBE _mfmcs.bit._DRBE +#define MFMCS_RD19V _mfmcs.bit._RD19V +__IO_EXTENDED MFMTCSTR _mfmtc; +#define MFMTC _mfmtc.word +#define MFMTC_FAWC0 _mfmtc.bit._FAWC0 +#define MFMTC_FAWC1 _mfmtc.bit._FAWC1 +#define MFMTC_FAWC2 _mfmtc.bit._FAWC2 +#define MFMTC_SYNC _mfmtc.bit._SYNC +#define MFMTC_ADS _mfmtc.bit._ADS +#define MFMTC_CLKBW _mfmtc.bit._CLKBW +#define MFMTC_WEXL _mfmtc.bit._WEXL +#define MFMTC_ATDINIT _mfmtc.bit._ATDINIT +#define MFMTC_ATDL0 _mfmtc.bit._ATDL0 +#define MFMTC_ATDL1 _mfmtc.bit._ATDL1 +#define MFMTC_ATDEQD0 _mfmtc.bit._ATDEQD0 +#define MFMTC_ATDEQD1 _mfmtc.bit._ATDEQD1 +#define MFMTC_EQL0 _mfmtc.bit._EQL0 +#define MFMTC_EQL1 _mfmtc.bit._EQL1 +#define MFMTC_EQL2 _mfmtc.bit._EQL2 +#define MFMTC_FAWC _mfmtc.bitc._FAWC +#define MFMTC_ATDL _mfmtc.bitc._ATDL +#define MFMTC_ATDEQD _mfmtc.bitc._ATDEQD +#define MFMTC_EQL _mfmtc.bitc._EQL +__IO_EXTENDED MFMTCLSTR _mfmtcl; +#define MFMTCL _mfmtcl.byte +#define MFMTCL_FAWC0 _mfmtcl.bit._FAWC0 +#define MFMTCL_FAWC1 _mfmtcl.bit._FAWC1 +#define MFMTCL_FAWC2 _mfmtcl.bit._FAWC2 +#define MFMTCL_SYNC _mfmtcl.bit._SYNC +#define MFMTCL_ADS _mfmtcl.bit._ADS +#define MFMTCL_CLKBW _mfmtcl.bit._CLKBW +#define MFMTCL_WEXL _mfmtcl.bit._WEXL +#define MFMTCL_FAWC _mfmtcl.bitc._FAWC +__IO_EXTENDED MFMTCHSTR _mfmtch; +#define MFMTCH _mfmtch.byte +#define MFMTCH_ATDINIT _mfmtch.bit._ATDINIT +#define MFMTCH_ATDL0 _mfmtch.bit._ATDL0 +#define MFMTCH_ATDL1 _mfmtch.bit._ATDL1 +#define MFMTCH_ATDEQD0 _mfmtch.bit._ATDEQD0 +#define MFMTCH_ATDEQD1 _mfmtch.bit._ATDEQD1 +#define MFMTCH_EQL0 _mfmtch.bit._EQL0 +#define MFMTCH_EQL1 _mfmtch.bit._EQL1 +#define MFMTCH_EQL2 _mfmtch.bit._EQL2 +#define MFMTCH_ATDL _mfmtch.bitc._ATDL +#define MFMTCH_ATDEQD _mfmtch.bitc._ATDEQD +#define MFMTCH_EQL _mfmtch.bitc._EQL +__IO_EXTENDED SFMCSSTR _sfmcs; +#define SFMCS _sfmcs.byte +#define SFMCS_RDY _sfmcs.bit._RDY +#define SFMCS_RDYINT _sfmcs.bit._RDYINT +#define SFMCS_INTE _sfmcs.bit._INTE +#define SFMCS_WE _sfmcs.bit._WE +#define SFMCS_CRBE _sfmcs.bit._CRBE +#define SFMCS_DRBE _sfmcs.bit._DRBE +#define SFMCS_RD19V _sfmcs.bit._RD19V +__IO_EXTENDED SFMTCSTR _sfmtc; +#define SFMTC _sfmtc.word +#define SFMTC_FAWC0 _sfmtc.bit._FAWC0 +#define SFMTC_FAWC1 _sfmtc.bit._FAWC1 +#define SFMTC_FAWC2 _sfmtc.bit._FAWC2 +#define SFMTC_SYNC _sfmtc.bit._SYNC +#define SFMTC_ADS _sfmtc.bit._ADS +#define SFMTC_CLKBW _sfmtc.bit._CLKBW +#define SFMTC_WEXL _sfmtc.bit._WEXL +#define SFMTC_ATDINIT _sfmtc.bit._ATDINIT +#define SFMTC_ATDL0 _sfmtc.bit._ATDL0 +#define SFMTC_ATDL1 _sfmtc.bit._ATDL1 +#define SFMTC_ATDEQD0 _sfmtc.bit._ATDEQD0 +#define SFMTC_ATDEQD1 _sfmtc.bit._ATDEQD1 +#define SFMTC_EQL0 _sfmtc.bit._EQL0 +#define SFMTC_EQL1 _sfmtc.bit._EQL1 +#define SFMTC_EQL2 _sfmtc.bit._EQL2 +#define SFMTC_FAWC _sfmtc.bitc._FAWC +#define SFMTC_ATDL _sfmtc.bitc._ATDL +#define SFMTC_ATDEQD _sfmtc.bitc._ATDEQD +#define SFMTC_EQL _sfmtc.bitc._EQL +__IO_EXTENDED SFMTCLSTR _sfmtcl; +#define SFMTCL _sfmtcl.byte +#define SFMTCL_FAWC0 _sfmtcl.bit._FAWC0 +#define SFMTCL_FAWC1 _sfmtcl.bit._FAWC1 +#define SFMTCL_FAWC2 _sfmtcl.bit._FAWC2 +#define SFMTCL_SYNC _sfmtcl.bit._SYNC +#define SFMTCL_ADS _sfmtcl.bit._ADS +#define SFMTCL_CLKBW _sfmtcl.bit._CLKBW +#define SFMTCL_WEXL _sfmtcl.bit._WEXL +#define SFMTCL_FAWC _sfmtcl.bitc._FAWC +__IO_EXTENDED SFMTCHSTR _sfmtch; +#define SFMTCH _sfmtch.byte +#define SFMTCH_ATDINIT _sfmtch.bit._ATDINIT +#define SFMTCH_ATDL0 _sfmtch.bit._ATDL0 +#define SFMTCH_ATDL1 _sfmtch.bit._ATDL1 +#define SFMTCH_ATDEQD0 _sfmtch.bit._ATDEQD0 +#define SFMTCH_ATDEQD1 _sfmtch.bit._ATDEQD1 +#define SFMTCH_EQL0 _sfmtch.bit._EQL0 +#define SFMTCH_EQL1 _sfmtch.bit._EQL1 +#define SFMTCH_EQL2 _sfmtch.bit._EQL2 +#define SFMTCH_ATDL _sfmtch.bitc._ATDL +#define SFMTCH_ATDEQD _sfmtch.bitc._ATDEQD +#define SFMTCH_EQL _sfmtch.bitc._EQL +__IO_EXTENDED FMWC0STR _fmwc0; +#define FMWC0 _fmwc0.byte +#define FMWC0_WCB0 _fmwc0.bit._WCB0 +#define FMWC0_WCB1 _fmwc0.bit._WCB1 +#define FMWC0_WCB2 _fmwc0.bit._WCB2 +#define FMWC0_WCB3 _fmwc0.bit._WCB3 +#define FMWC0_WCB _fmwc0.bitc._WCB +__IO_EXTENDED FMWC1STR _fmwc1; +#define FMWC1 _fmwc1.byte +#define FMWC1_WCA0 _fmwc1.bit._WCA0 +#define FMWC1_WCA1 _fmwc1.bit._WCA1 +#define FMWC1_WCA2 _fmwc1.bit._WCA2 +#define FMWC1_WCA3 _fmwc1.bit._WCA3 +#define FMWC1_WCA _fmwc1.bitc._WCA +__IO_EXTENDED IO_BYTE _fmwc2; +#define FMWC2 _fmwc2 +__IO_EXTENDED IO_BYTE _fmwc3; +#define FMWC3 _fmwc3 +__IO_EXTENDED IO_BYTE _fmwc4; +#define FMWC4 _fmwc4 +__IO_EXTENDED FMWC5STR _fmwc5; +#define FMWC5 _fmwc5.byte +#define FMWC5_WC32 _fmwc5.bit._WC32 +#define FMWC5_WC33 _fmwc5.bit._WC33 +#define FMWC5_WC34 _fmwc5.bit._WC34 +#define FMWC5_WC35 _fmwc5.bit._WC35 +#define FMWC5_WC36 _fmwc5.bit._WC36 +#define FMWC5_WC37 _fmwc5.bit._WC37 +#define FMWC5_WC38 _fmwc5.bit._WC38 +#define FMWC5_WC39 _fmwc5.bit._WC39 +#define FMWC5_WC3 _fmwc5.bitc._WC3 +__IO_EXTENDED SMCRSTR _smcr; +#define SMCR _smcr.byte +#define SMCR_SMS0 _smcr.bit._SMS0 +#define SMCR_SMS1 _smcr.bit._SMS1 +#define SMCR_SPL _smcr.bit._SPL +#define SMCR_SMS _smcr.bitc._SMS +__IO_EXTENDED CKSRSTR _cksr; +#define CKSR _cksr.byte +#define CKSR_SC1S0 _cksr.bit._SC1S0 +#define CKSR_SC1S1 _cksr.bit._SC1S1 +#define CKSR_SC2S0 _cksr.bit._SC2S0 +#define CKSR_SC2S1 _cksr.bit._SC2S1 +#define CKSR_RCE _cksr.bit._RCE +#define CKSR_MCE _cksr.bit._MCE +#define CKSR_PCE _cksr.bit._PCE +#define CKSR_SC1S _cksr.bitc._SC1S +#define CKSR_SC2S _cksr.bitc._SC2S +__IO_EXTENDED CKSSRSTR _ckssr; +#define CKSSR _ckssr.byte +#define CKSSR_MCST0 _ckssr.bit._MCST0 +#define CKSSR_MCST1 _ckssr.bit._MCST1 +#define CKSSR_MCST2 _ckssr.bit._MCST2 +#define CKSSR_PCST _ckssr.bit._PCST +#define CKSSR_MRFBE _ckssr.bit._MRFBE +#define CKSSR_MCST _ckssr.bitc._MCST +__IO_EXTENDED CKMRSTR _ckmr; +#define CKMR _ckmr.byte +#define CKMR_SC1M0 _ckmr.bit._SC1M0 +#define CKMR_SC1M1 _ckmr.bit._SC1M1 +#define CKMR_SC2M0 _ckmr.bit._SC2M0 +#define CKMR_SC2M1 _ckmr.bit._SC2M1 +#define CKMR_RCM _ckmr.bit._RCM +#define CKMR_MCM _ckmr.bit._MCM +#define CKMR_PCM _ckmr.bit._PCM +#define CKMR_SC1M _ckmr.bitc._SC1M +#define CKMR_SC2M _ckmr.bitc._SC2M +__IO_EXTENDED CKFCRSTR _ckfcr; +#define CKFCR _ckfcr.word +#define CKFCR_RCFS _ckfcr.bit._RCFS +#define CKFCR_BCD0 _ckfcr.bit._BCD0 +#define CKFCR_BCD1 _ckfcr.bit._BCD1 +#define CKFCR_BCD2 _ckfcr.bit._BCD2 +#define CKFCR_BCD3 _ckfcr.bit._BCD3 +#define CKFCR_PC1D0 _ckfcr.bit._PC1D0 +#define CKFCR_PC1D1 _ckfcr.bit._PC1D1 +#define CKFCR_PC1D2 _ckfcr.bit._PC1D2 +#define CKFCR_PC1D3 _ckfcr.bit._PC1D3 +#define CKFCR_PC2D0 _ckfcr.bit._PC2D0 +#define CKFCR_PC2D1 _ckfcr.bit._PC2D1 +#define CKFCR_PC2D2 _ckfcr.bit._PC2D2 +#define CKFCR_PC2D3 _ckfcr.bit._PC2D3 +#define CKFCR_BCD _ckfcr.bitc._BCD +#define CKFCR_PC1D _ckfcr.bitc._PC1D +#define CKFCR_PC2D _ckfcr.bitc._PC2D +__IO_EXTENDED CKFCRLSTR _ckfcrl; +#define CKFCRL _ckfcrl.byte +#define CKFCRL_RCFS _ckfcrl.bit._RCFS +#define CKFCRL_BCD0 _ckfcrl.bit._BCD0 +#define CKFCRL_BCD1 _ckfcrl.bit._BCD1 +#define CKFCRL_BCD2 _ckfcrl.bit._BCD2 +#define CKFCRL_BCD3 _ckfcrl.bit._BCD3 +#define CKFCRL_BCD _ckfcrl.bitc._BCD +__IO_EXTENDED CKFCRHSTR _ckfcrh; +#define CKFCRH _ckfcrh.byte +#define CKFCRH_PC1D0 _ckfcrh.bit._PC1D0 +#define CKFCRH_PC1D1 _ckfcrh.bit._PC1D1 +#define CKFCRH_PC1D2 _ckfcrh.bit._PC1D2 +#define CKFCRH_PC1D3 _ckfcrh.bit._PC1D3 +#define CKFCRH_PC2D0 _ckfcrh.bit._PC2D0 +#define CKFCRH_PC2D1 _ckfcrh.bit._PC2D1 +#define CKFCRH_PC2D2 _ckfcrh.bit._PC2D2 +#define CKFCRH_PC2D3 _ckfcrh.bit._PC2D3 +#define CKFCRH_PC1D _ckfcrh.bitc._PC1D +#define CKFCRH_PC2D _ckfcrh.bitc._PC2D +__IO_EXTENDED PLLCRSTR _pllcr; +#define PLLCR _pllcr.word +#define PLLCR_PMS0 _pllcr.bit._PMS0 +#define PLLCR_PMS1 _pllcr.bit._PMS1 +#define PLLCR_PMS2 _pllcr.bit._PMS2 +#define PLLCR_PMS3 _pllcr.bit._PMS3 +#define PLLCR_PMS4 _pllcr.bit._PMS4 +#define PLLCR_VMS0 _pllcr.bit._VMS0 +#define PLLCR_VMS1 _pllcr.bit._VMS1 +#define PLLCR_VMS2 _pllcr.bit._VMS2 +#define PLLCR_PC3D0 _pllcr.bit._PC3D0 +#define PLLCR_PC3D1 _pllcr.bit._PC3D1 +#define PLLCR_PC3D2 _pllcr.bit._PC3D2 +#define PLLCR_PC3D3 _pllcr.bit._PC3D3 +#define PLLCR_PMS _pllcr.bitc._PMS +#define PLLCR_VMS _pllcr.bitc._VMS +#define PLLCR_PC3D _pllcr.bitc._PC3D +__IO_EXTENDED PLLCRLSTR _pllcrl; +#define PLLCRL _pllcrl.byte +#define PLLCRL_PMS0 _pllcrl.bit._PMS0 +#define PLLCRL_PMS1 _pllcrl.bit._PMS1 +#define PLLCRL_PMS2 _pllcrl.bit._PMS2 +#define PLLCRL_PMS3 _pllcrl.bit._PMS3 +#define PLLCRL_PMS4 _pllcrl.bit._PMS4 +#define PLLCRL_VMS0 _pllcrl.bit._VMS0 +#define PLLCRL_VMS1 _pllcrl.bit._VMS1 +#define PLLCRL_VMS2 _pllcrl.bit._VMS2 +#define PLLCRL_PMS _pllcrl.bitc._PMS +#define PLLCRL_VMS _pllcrl.bitc._VMS +__IO_EXTENDED PLLCRHSTR _pllcrh; +#define PLLCRH _pllcrh.byte +#define PLLCRH_PC3D0 _pllcrh.bit._PC3D0 +#define PLLCRH_PC3D1 _pllcrh.bit._PC3D1 +#define PLLCRH_PC3D2 _pllcrh.bit._PC3D2 +#define PLLCRH_PC3D3 _pllcrh.bit._PC3D3 +#define PLLCRH_PC3D _pllcrh.bitc._PC3D +__IO_EXTENDED RCTCRSTR _rctcr; +#define RCTCR _rctcr.byte +#define RCTCR_RCTI0 _rctcr.bit._RCTI0 +#define RCTCR_RCTI1 _rctcr.bit._RCTI1 +#define RCTCR_RCTI2 _rctcr.bit._RCTI2 +#define RCTCR_RCTI3 _rctcr.bit._RCTI3 +#define RCTCR_RCTR _rctcr.bit._RCTR +#define RCTCR_RCTIF _rctcr.bit._RCTIF +#define RCTCR_RCTIE _rctcr.bit._RCTIE +#define RCTCR_RCTI _rctcr.bitc._RCTI +__IO_EXTENDED MCTCRSTR _mctcr; +#define MCTCR _mctcr.byte +#define MCTCR_MCTI0 _mctcr.bit._MCTI0 +#define MCTCR_MCTI1 _mctcr.bit._MCTI1 +#define MCTCR_MCTI2 _mctcr.bit._MCTI2 +#define MCTCR_MCTI3 _mctcr.bit._MCTI3 +#define MCTCR_MCTR _mctcr.bit._MCTR +#define MCTCR_MCTIF _mctcr.bit._MCTIF +#define MCTCR_MCTIE _mctcr.bit._MCTIE +#define MCTCR_MCTI _mctcr.bitc._MCTI +__IO_EXTENDED RCCSRCSTR _rccsrc; +#define RCCSRC _rccsrc.byte +#define RCCSRC_PRST _rccsrc.bit._PRST +#define RCCSRC_ERST _rccsrc.bit._ERST +#define RCCSRC_MCRST _rccsrc.bit._MCRST +#define RCCSRC_SRST _rccsrc.bit._SRST +#define RCCSRC_WRST _rccsrc.bit._WRST +#define RCCSRC_MCMF _rccsrc.bit._MCMF +__IO_EXTENDED RCRSTR _rcr; +#define RCR _rcr.byte +#define RCR_SRSTG _rcr.bit._SRSTG +#define RCR_LVRE _rcr.bit._LVRE +#define RCR_LVDE _rcr.bit._LVDE +#define RCR_CSDRE _rcr.bit._CSDRE +#define RCR_MCSDI _rcr.bit._MCSDI +__IO_EXTENDED RCCSRSTR _rccsr; +#define RCCSR _rccsr.byte +#define RCCSR_PRST _rccsr.bit._PRST +#define RCCSR_ERST _rccsr.bit._ERST +#define RCCSR_MCRST _rccsr.bit._MCRST +#define RCCSR_SRST _rccsr.bit._SRST +#define RCCSR_WRST _rccsr.bit._WRST +#define RCCSR_MCMF _rccsr.bit._MCMF +__IO_EXTENDED WDTCSTR _wdtc; +#define WDTC _wdtc.byte +#define WDTC_WTI0 _wdtc.bit._WTI0 +#define WDTC_WTI1 _wdtc.bit._WTI1 +#define WDTC_WTI2 _wdtc.bit._WTI2 +#define WDTC_WTI3 _wdtc.bit._WTI3 +#define WDTC_WTCS0 _wdtc.bit._WTCS0 +#define WDTC_WTCS1 _wdtc.bit._WTCS1 +#define WDTC_RSTP _wdtc.bit._RSTP +#define WDTC_WTI _wdtc.bitc._WTI +#define WDTC_WTCS _wdtc.bitc._WTCS +__IO_EXTENDED WDTCPSTR _wdtcp; +#define WDTCP _wdtcp.byte +#define WDTCP_WCP0 _wdtcp.bit._WCP0 +#define WDTCP_WCP1 _wdtcp.bit._WCP1 +#define WDTCP_WCP2 _wdtcp.bit._WCP2 +#define WDTCP_WCP3 _wdtcp.bit._WCP3 +#define WDTCP_WCP4 _wdtcp.bit._WCP4 +#define WDTCP_WCP5 _wdtcp.bit._WCP5 +#define WDTCP_WCP6 _wdtcp.bit._WCP6 +#define WDTCP_WCP7 _wdtcp.bit._WCP7 +#define WDTCP_WCP _wdtcp.bitc._WCP +__IO_EXTENDED COARSTR _coar; +#define COAR _coar.byte +#define COAR_CKOE0 _coar.bit._CKOE0 +#define COAR_CKOXE0 _coar.bit._CKOXE0 +#define COAR_RUNC0 _coar.bit._RUNC0 +#define COAR_RUNM0 _coar.bit._RUNM0 +#define COAR_CKOE1 _coar.bit._CKOE1 +#define COAR_CKOXE1 _coar.bit._CKOXE1 +#define COAR_RUNC1 _coar.bit._RUNC1 +#define COAR_RUNM1 _coar.bit._RUNM1 +__IO_EXTENDED COCR0STR _cocr0; +#define COCR0 _cocr0.byte +#define COCR0_SEL0 _cocr0.bit._SEL0 +#define COCR0_SEL1 _cocr0.bit._SEL1 +#define COCR0_SEL2 _cocr0.bit._SEL2 +#define COCR0_SEL3 _cocr0.bit._SEL3 +#define COCR0_DIV0 _cocr0.bit._DIV0 +#define COCR0_DIV1 _cocr0.bit._DIV1 +#define COCR0_DIV2 _cocr0.bit._DIV2 +#define COCR0_SEL _cocr0.bitc._SEL +#define COCR0_DIV _cocr0.bitc._DIV +__IO_EXTENDED COCR1STR _cocr1; +#define COCR1 _cocr1.byte +#define COCR1_SEL0 _cocr1.bit._SEL0 +#define COCR1_SEL1 _cocr1.bit._SEL1 +#define COCR1_SEL2 _cocr1.bit._SEL2 +#define COCR1_SEL3 _cocr1.bit._SEL3 +#define COCR1_DIV0 _cocr1.bit._DIV0 +#define COCR1_DIV1 _cocr1.bit._DIV1 +#define COCR1_DIV2 _cocr1.bit._DIV2 +#define COCR1_SEL _cocr1.bitc._SEL +#define COCR1_DIV _cocr1.bitc._DIV +__IO_EXTENDED CMCRSTR _cmcr; +#define CMCR _cmcr.byte +#define CMCR_PDX _cmcr.bit._PDX +#define CMCR_MODEN _cmcr.bit._MODEN +#define CMCR_MODRUN _cmcr.bit._MODRUN +__IO_EXTENDED CMPRSTR _cmpr; +#define CMPR _cmpr.word +#define CMPR_C0 _cmpr.bit._C0 +#define CMPR_C1 _cmpr.bit._C1 +#define CMPR_C2 _cmpr.bit._C2 +#define CMPR_C3 _cmpr.bit._C3 +#define CMPR_C4 _cmpr.bit._C4 +#define CMPR_N0 _cmpr.bit._N0 +#define CMPR_N1 _cmpr.bit._N1 +#define CMPR_N2 _cmpr.bit._N2 +#define CMPR_N3 _cmpr.bit._N3 +#define CMPR_K0 _cmpr.bit._K0 +#define CMPR_K1 _cmpr.bit._K1 +#define CMPR_K2 _cmpr.bit._K2 +#define CMPR_K3 _cmpr.bit._K3 +#define CMPR_K4 _cmpr.bit._K4 +#define CMPR_C _cmpr.bitc._C +#define CMPR_N _cmpr.bitc._N +#define CMPR_K _cmpr.bitc._K +__IO_EXTENDED CMPRLSTR _cmprl; +#define CMPRL _cmprl.byte +#define CMPRL_C0 _cmprl.bit._C0 +#define CMPRL_C1 _cmprl.bit._C1 +#define CMPRL_C2 _cmprl.bit._C2 +#define CMPRL_C3 _cmprl.bit._C3 +#define CMPRL_C4 _cmprl.bit._C4 +#define CMPRL_N0 _cmprl.bit._N0 +#define CMPRL_N1 _cmprl.bit._N1 +#define CMPRL_N2 _cmprl.bit._N2 +#define CMPRL_C _cmprl.bitc._C +#define CMPRL_N _cmprl.bitc._N +__IO_EXTENDED CMPRHSTR _cmprh; +#define CMPRH _cmprh.byte +#define CMPRH_N3 _cmprh.bit._N3 +#define CMPRH_K0 _cmprh.bit._K0 +#define CMPRH_K1 _cmprh.bit._K1 +#define CMPRH_K2 _cmprh.bit._K2 +#define CMPRH_K3 _cmprh.bit._K3 +#define CMPRH_K4 _cmprh.bit._K4 +#define CMPRH_K _cmprh.bitc._K +__IO_EXTENDED VRCRSTR _vrcr; +#define VRCR _vrcr.byte +#define VRCR_LPBM0 _vrcr.bit._LPBM0 +#define VRCR_LPBM1 _vrcr.bit._LPBM1 +#define VRCR_LPMB2 _vrcr.bit._LPMB2 +#define VRCR_LPMA0 _vrcr.bit._LPMA0 +#define VRCR_LPMA1 _vrcr.bit._LPMA1 +#define VRCR_LPMA2 _vrcr.bit._LPMA2 +#define VRCR_HPM0 _vrcr.bit._HPM0 +#define VRCR_HPM1 _vrcr.bit._HPM1 +#define VRCR_LPBM _vrcr.bitc._LPBM +#define VRCR_LPMA _vrcr.bitc._LPMA +#define VRCR_HPM _vrcr.bitc._HPM +__IO_EXTENDED DDR00STR _ddr00; +#define DDR00 _ddr00.byte +#define DDR00_D0 _ddr00.bit._D0 +#define DDR00_D1 _ddr00.bit._D1 +#define DDR00_D2 _ddr00.bit._D2 +#define DDR00_D3 _ddr00.bit._D3 +#define DDR00_D4 _ddr00.bit._D4 +#define DDR00_D5 _ddr00.bit._D5 +#define DDR00_D6 _ddr00.bit._D6 +#define DDR00_D7 _ddr00.bit._D7 +__IO_EXTENDED DDR01STR _ddr01; +#define DDR01 _ddr01.byte +#define DDR01_D0 _ddr01.bit._D0 +#define DDR01_D1 _ddr01.bit._D1 +#define DDR01_D2 _ddr01.bit._D2 +#define DDR01_D3 _ddr01.bit._D3 +#define DDR01_D4 _ddr01.bit._D4 +#define DDR01_D5 _ddr01.bit._D5 +#define DDR01_D6 _ddr01.bit._D6 +#define DDR01_D7 _ddr01.bit._D7 +__IO_EXTENDED DDR02STR _ddr02; +#define DDR02 _ddr02.byte +#define DDR02_D0 _ddr02.bit._D0 +#define DDR02_D1 _ddr02.bit._D1 +#define DDR02_D2 _ddr02.bit._D2 +#define DDR02_D3 _ddr02.bit._D3 +#define DDR02_D4 _ddr02.bit._D4 +#define DDR02_D5 _ddr02.bit._D5 +#define DDR02_D6 _ddr02.bit._D6 +#define DDR02_D7 _ddr02.bit._D7 +__IO_EXTENDED DDR03STR _ddr03; +#define DDR03 _ddr03.byte +#define DDR03_D0 _ddr03.bit._D0 +#define DDR03_D1 _ddr03.bit._D1 +#define DDR03_D2 _ddr03.bit._D2 +#define DDR03_D3 _ddr03.bit._D3 +#define DDR03_D4 _ddr03.bit._D4 +#define DDR03_D5 _ddr03.bit._D5 +#define DDR03_D6 _ddr03.bit._D6 +#define DDR03_D7 _ddr03.bit._D7 +__IO_EXTENDED DDR04STR _ddr04; +#define DDR04 _ddr04.byte +#define DDR04_D0 _ddr04.bit._D0 +#define DDR04_D1 _ddr04.bit._D1 +#define DDR04_D2 _ddr04.bit._D2 +#define DDR04_D3 _ddr04.bit._D3 +#define DDR04_D4 _ddr04.bit._D4 +#define DDR04_D5 _ddr04.bit._D5 +#define DDR04_D6 _ddr04.bit._D6 +#define DDR04_D7 _ddr04.bit._D7 +__IO_EXTENDED DDR05STR _ddr05; +#define DDR05 _ddr05.byte +#define DDR05_D0 _ddr05.bit._D0 +#define DDR05_D1 _ddr05.bit._D1 +#define DDR05_D2 _ddr05.bit._D2 +#define DDR05_D3 _ddr05.bit._D3 +#define DDR05_D4 _ddr05.bit._D4 +#define DDR05_D5 _ddr05.bit._D5 +#define DDR05_D6 _ddr05.bit._D6 +#define DDR05_D7 _ddr05.bit._D7 +__IO_EXTENDED DDR06STR _ddr06; +#define DDR06 _ddr06.byte +#define DDR06_D0 _ddr06.bit._D0 +#define DDR06_D1 _ddr06.bit._D1 +#define DDR06_D2 _ddr06.bit._D2 +#define DDR06_D3 _ddr06.bit._D3 +#define DDR06_D4 _ddr06.bit._D4 +#define DDR06_D5 _ddr06.bit._D5 +#define DDR06_D6 _ddr06.bit._D6 +#define DDR06_D7 _ddr06.bit._D7 +__IO_EXTENDED DDR07STR _ddr07; +#define DDR07 _ddr07.byte +#define DDR07_D0 _ddr07.bit._D0 +#define DDR07_D1 _ddr07.bit._D1 +#define DDR07_D2 _ddr07.bit._D2 +#define DDR07_D3 _ddr07.bit._D3 +#define DDR07_D4 _ddr07.bit._D4 +#define DDR07_D5 _ddr07.bit._D5 +#define DDR07_D6 _ddr07.bit._D6 +#define DDR07_D7 _ddr07.bit._D7 +__IO_EXTENDED DDR08STR _ddr08; +#define DDR08 _ddr08.byte +#define DDR08_D0 _ddr08.bit._D0 +#define DDR08_D1 _ddr08.bit._D1 +#define DDR08_D2 _ddr08.bit._D2 +#define DDR08_D3 _ddr08.bit._D3 +#define DDR08_D4 _ddr08.bit._D4 +#define DDR08_D5 _ddr08.bit._D5 +#define DDR08_D6 _ddr08.bit._D6 +#define DDR08_D7 _ddr08.bit._D7 +__IO_EXTENDED DDR09STR _ddr09; +#define DDR09 _ddr09.byte +#define DDR09_D0 _ddr09.bit._D0 +#define DDR09_D1 _ddr09.bit._D1 +#define DDR09_D2 _ddr09.bit._D2 +#define DDR09_D3 _ddr09.bit._D3 +#define DDR09_D4 _ddr09.bit._D4 +#define DDR09_D5 _ddr09.bit._D5 +#define DDR09_D6 _ddr09.bit._D6 +#define DDR09_D7 _ddr09.bit._D7 +__IO_EXTENDED DDR10STR _ddr10; +#define DDR10 _ddr10.byte +#define DDR10_D0 _ddr10.bit._D0 +#define DDR10_D1 _ddr10.bit._D1 +__IO_EXTENDED PIER00STR _pier00; +#define PIER00 _pier00.byte +#define PIER00_IE0 _pier00.bit._IE0 +#define PIER00_IE1 _pier00.bit._IE1 +#define PIER00_IE2 _pier00.bit._IE2 +#define PIER00_IE3 _pier00.bit._IE3 +#define PIER00_IE4 _pier00.bit._IE4 +#define PIER00_IE5 _pier00.bit._IE5 +#define PIER00_IE6 _pier00.bit._IE6 +#define PIER00_IE7 _pier00.bit._IE7 +__IO_EXTENDED PIER01STR _pier01; +#define PIER01 _pier01.byte +#define PIER01_IE0 _pier01.bit._IE0 +#define PIER01_IE1 _pier01.bit._IE1 +#define PIER01_IE2 _pier01.bit._IE2 +#define PIER01_IE3 _pier01.bit._IE3 +#define PIER01_IE4 _pier01.bit._IE4 +#define PIER01_IE5 _pier01.bit._IE5 +#define PIER01_IE6 _pier01.bit._IE6 +#define PIER01_IE7 _pier01.bit._IE7 +__IO_EXTENDED PIER02STR _pier02; +#define PIER02 _pier02.byte +#define PIER02_IE0 _pier02.bit._IE0 +#define PIER02_IE1 _pier02.bit._IE1 +#define PIER02_IE2 _pier02.bit._IE2 +#define PIER02_IE3 _pier02.bit._IE3 +#define PIER02_IE4 _pier02.bit._IE4 +#define PIER02_IE5 _pier02.bit._IE5 +#define PIER02_IE6 _pier02.bit._IE6 +#define PIER02_IE7 _pier02.bit._IE7 +__IO_EXTENDED PIER03STR _pier03; +#define PIER03 _pier03.byte +#define PIER03_IE0 _pier03.bit._IE0 +#define PIER03_IE1 _pier03.bit._IE1 +#define PIER03_IE2 _pier03.bit._IE2 +#define PIER03_IE3 _pier03.bit._IE3 +#define PIER03_IE4 _pier03.bit._IE4 +#define PIER03_IE5 _pier03.bit._IE5 +#define PIER03_IE6 _pier03.bit._IE6 +#define PIER03_IE7 _pier03.bit._IE7 +__IO_EXTENDED PIER04STR _pier04; +#define PIER04 _pier04.byte +#define PIER04_IE0 _pier04.bit._IE0 +#define PIER04_IE1 _pier04.bit._IE1 +#define PIER04_IE2 _pier04.bit._IE2 +#define PIER04_IE3 _pier04.bit._IE3 +#define PIER04_IE4 _pier04.bit._IE4 +#define PIER04_IE5 _pier04.bit._IE5 +#define PIER04_IE6 _pier04.bit._IE6 +#define PIER04_IE7 _pier04.bit._IE7 +__IO_EXTENDED PIER05STR _pier05; +#define PIER05 _pier05.byte +#define PIER05_IE0 _pier05.bit._IE0 +#define PIER05_IE1 _pier05.bit._IE1 +#define PIER05_IE2 _pier05.bit._IE2 +#define PIER05_IE3 _pier05.bit._IE3 +#define PIER05_IE4 _pier05.bit._IE4 +#define PIER05_IE5 _pier05.bit._IE5 +#define PIER05_IE6 _pier05.bit._IE6 +#define PIER05_IE7 _pier05.bit._IE7 +__IO_EXTENDED PIER06STR _pier06; +#define PIER06 _pier06.byte +#define PIER06_IE0 _pier06.bit._IE0 +#define PIER06_IE1 _pier06.bit._IE1 +#define PIER06_IE2 _pier06.bit._IE2 +#define PIER06_IE3 _pier06.bit._IE3 +#define PIER06_IE4 _pier06.bit._IE4 +#define PIER06_IE5 _pier06.bit._IE5 +#define PIER06_IE6 _pier06.bit._IE6 +#define PIER06_IE7 _pier06.bit._IE7 +__IO_EXTENDED PIER07STR _pier07; +#define PIER07 _pier07.byte +#define PIER07_IE0 _pier07.bit._IE0 +#define PIER07_IE1 _pier07.bit._IE1 +#define PIER07_IE2 _pier07.bit._IE2 +#define PIER07_IE3 _pier07.bit._IE3 +#define PIER07_IE4 _pier07.bit._IE4 +#define PIER07_IE5 _pier07.bit._IE5 +#define PIER07_IE6 _pier07.bit._IE6 +#define PIER07_IE7 _pier07.bit._IE7 +__IO_EXTENDED PIER08STR _pier08; +#define PIER08 _pier08.byte +#define PIER08_IE0 _pier08.bit._IE0 +#define PIER08_IE1 _pier08.bit._IE1 +#define PIER08_IE2 _pier08.bit._IE2 +#define PIER08_IE3 _pier08.bit._IE3 +#define PIER08_IE4 _pier08.bit._IE4 +#define PIER08_IE5 _pier08.bit._IE5 +#define PIER08_IE6 _pier08.bit._IE6 +#define PIER08_IE7 _pier08.bit._IE7 +__IO_EXTENDED PIER09STR _pier09; +#define PIER09 _pier09.byte +#define PIER09_IE0 _pier09.bit._IE0 +#define PIER09_IE1 _pier09.bit._IE1 +#define PIER09_IE2 _pier09.bit._IE2 +#define PIER09_IE3 _pier09.bit._IE3 +#define PIER09_IE4 _pier09.bit._IE4 +#define PIER09_IE5 _pier09.bit._IE5 +#define PIER09_IE6 _pier09.bit._IE6 +#define PIER09_IE7 _pier09.bit._IE7 +__IO_EXTENDED PIER10STR _pier10; +#define PIER10 _pier10.byte +#define PIER10_IE0 _pier10.bit._IE0 +#define PIER10_IE1 _pier10.bit._IE1 +__IO_EXTENDED PILR00STR _pilr00; +#define PILR00 _pilr00.byte +#define PILR00_IL0 _pilr00.bit._IL0 +#define PILR00_IL1 _pilr00.bit._IL1 +#define PILR00_IL2 _pilr00.bit._IL2 +#define PILR00_IL3 _pilr00.bit._IL3 +#define PILR00_IL4 _pilr00.bit._IL4 +#define PILR00_IL5 _pilr00.bit._IL5 +#define PILR00_IL6 _pilr00.bit._IL6 +#define PILR00_IL7 _pilr00.bit._IL7 +__IO_EXTENDED PILR01STR _pilr01; +#define PILR01 _pilr01.byte +#define PILR01_IL0 _pilr01.bit._IL0 +#define PILR01_IL1 _pilr01.bit._IL1 +#define PILR01_IL2 _pilr01.bit._IL2 +#define PILR01_IL3 _pilr01.bit._IL3 +#define PILR01_IL4 _pilr01.bit._IL4 +#define PILR01_IL5 _pilr01.bit._IL5 +#define PILR01_IL6 _pilr01.bit._IL6 +#define PILR01_IL7 _pilr01.bit._IL7 +__IO_EXTENDED PILR02STR _pilr02; +#define PILR02 _pilr02.byte +#define PILR02_IL0 _pilr02.bit._IL0 +#define PILR02_IL1 _pilr02.bit._IL1 +#define PILR02_IL2 _pilr02.bit._IL2 +#define PILR02_IL3 _pilr02.bit._IL3 +#define PILR02_IL4 _pilr02.bit._IL4 +#define PILR02_IL5 _pilr02.bit._IL5 +#define PILR02_IL6 _pilr02.bit._IL6 +#define PILR02_IL7 _pilr02.bit._IL7 +__IO_EXTENDED PILR03STR _pilr03; +#define PILR03 _pilr03.byte +#define PILR03_IL0 _pilr03.bit._IL0 +#define PILR03_IL1 _pilr03.bit._IL1 +#define PILR03_IL2 _pilr03.bit._IL2 +#define PILR03_IL3 _pilr03.bit._IL3 +#define PILR03_IL4 _pilr03.bit._IL4 +#define PILR03_IL5 _pilr03.bit._IL5 +#define PILR03_IL6 _pilr03.bit._IL6 +#define PILR03_IL7 _pilr03.bit._IL7 +__IO_EXTENDED PILR04STR _pilr04; +#define PILR04 _pilr04.byte +#define PILR04_IL0 _pilr04.bit._IL0 +#define PILR04_IL1 _pilr04.bit._IL1 +#define PILR04_IL2 _pilr04.bit._IL2 +#define PILR04_IL3 _pilr04.bit._IL3 +#define PILR04_IL4 _pilr04.bit._IL4 +#define PILR04_IL5 _pilr04.bit._IL5 +#define PILR04_IL6 _pilr04.bit._IL6 +#define PILR04_IL7 _pilr04.bit._IL7 +__IO_EXTENDED PILR05STR _pilr05; +#define PILR05 _pilr05.byte +#define PILR05_IL0 _pilr05.bit._IL0 +#define PILR05_IL1 _pilr05.bit._IL1 +#define PILR05_IL2 _pilr05.bit._IL2 +#define PILR05_IL3 _pilr05.bit._IL3 +#define PILR05_IL4 _pilr05.bit._IL4 +#define PILR05_IL5 _pilr05.bit._IL5 +#define PILR05_IL6 _pilr05.bit._IL6 +#define PILR05_IL7 _pilr05.bit._IL7 +__IO_EXTENDED PILR06STR _pilr06; +#define PILR06 _pilr06.byte +#define PILR06_IL0 _pilr06.bit._IL0 +#define PILR06_IL1 _pilr06.bit._IL1 +#define PILR06_IL2 _pilr06.bit._IL2 +#define PILR06_IL3 _pilr06.bit._IL3 +#define PILR06_IL4 _pilr06.bit._IL4 +#define PILR06_IL5 _pilr06.bit._IL5 +#define PILR06_IL6 _pilr06.bit._IL6 +#define PILR06_IL7 _pilr06.bit._IL7 +__IO_EXTENDED PILR07STR _pilr07; +#define PILR07 _pilr07.byte +#define PILR07_IL0 _pilr07.bit._IL0 +#define PILR07_IL1 _pilr07.bit._IL1 +#define PILR07_IL2 _pilr07.bit._IL2 +#define PILR07_IL3 _pilr07.bit._IL3 +#define PILR07_IL4 _pilr07.bit._IL4 +#define PILR07_IL5 _pilr07.bit._IL5 +#define PILR07_IL6 _pilr07.bit._IL6 +#define PILR07_IL7 _pilr07.bit._IL7 +__IO_EXTENDED PILR08STR _pilr08; +#define PILR08 _pilr08.byte +#define PILR08_IL0 _pilr08.bit._IL0 +#define PILR08_IL1 _pilr08.bit._IL1 +#define PILR08_IL2 _pilr08.bit._IL2 +#define PILR08_IL3 _pilr08.bit._IL3 +#define PILR08_IL4 _pilr08.bit._IL4 +#define PILR08_IL5 _pilr08.bit._IL5 +#define PILR08_IL6 _pilr08.bit._IL6 +#define PILR08_IL7 _pilr08.bit._IL7 +__IO_EXTENDED PILR09STR _pilr09; +#define PILR09 _pilr09.byte +#define PILR09_IL0 _pilr09.bit._IL0 +#define PILR09_IL1 _pilr09.bit._IL1 +#define PILR09_IL2 _pilr09.bit._IL2 +#define PILR09_IL3 _pilr09.bit._IL3 +#define PILR09_IL4 _pilr09.bit._IL4 +#define PILR09_IL5 _pilr09.bit._IL5 +#define PILR09_IL6 _pilr09.bit._IL6 +#define PILR09_IL7 _pilr09.bit._IL7 +__IO_EXTENDED PILR10STR _pilr10; +#define PILR10 _pilr10.byte +#define PILR10_IL0 _pilr10.bit._IL0 +#define PILR10_IL1 _pilr10.bit._IL1 +__IO_EXTENDED EPILR00STR _epilr00; +#define EPILR00 _epilr00.byte +#define EPILR00_EIL0 _epilr00.bit._EIL0 +#define EPILR00_EIL1 _epilr00.bit._EIL1 +#define EPILR00_EIL2 _epilr00.bit._EIL2 +#define EPILR00_EIL3 _epilr00.bit._EIL3 +#define EPILR00_EIL4 _epilr00.bit._EIL4 +#define EPILR00_EIL5 _epilr00.bit._EIL5 +#define EPILR00_EIL6 _epilr00.bit._EIL6 +#define EPILR00_EIL7 _epilr00.bit._EIL7 +__IO_EXTENDED EPILR01STR _epilr01; +#define EPILR01 _epilr01.byte +#define EPILR01_EIL0 _epilr01.bit._EIL0 +#define EPILR01_EIL1 _epilr01.bit._EIL1 +#define EPILR01_EIL2 _epilr01.bit._EIL2 +#define EPILR01_EIL3 _epilr01.bit._EIL3 +#define EPILR01_EIL4 _epilr01.bit._EIL4 +#define EPILR01_EIL5 _epilr01.bit._EIL5 +#define EPILR01_EIL6 _epilr01.bit._EIL6 +#define EPILR01_EIL7 _epilr01.bit._EIL7 +__IO_EXTENDED EPILR02STR _epilr02; +#define EPILR02 _epilr02.byte +#define EPILR02_EIL0 _epilr02.bit._EIL0 +#define EPILR02_EIL1 _epilr02.bit._EIL1 +#define EPILR02_EIL2 _epilr02.bit._EIL2 +#define EPILR02_EIL3 _epilr02.bit._EIL3 +#define EPILR02_EIL4 _epilr02.bit._EIL4 +#define EPILR02_EIL5 _epilr02.bit._EIL5 +#define EPILR02_EIL6 _epilr02.bit._EIL6 +#define EPILR02_EIL7 _epilr02.bit._EIL7 +__IO_EXTENDED EPILR03STR _epilr03; +#define EPILR03 _epilr03.byte +#define EPILR03_EIL0 _epilr03.bit._EIL0 +#define EPILR03_EIL1 _epilr03.bit._EIL1 +#define EPILR03_EIL2 _epilr03.bit._EIL2 +#define EPILR03_EIL3 _epilr03.bit._EIL3 +#define EPILR03_EIL4 _epilr03.bit._EIL4 +#define EPILR03_EIL5 _epilr03.bit._EIL5 +#define EPILR03_EIL6 _epilr03.bit._EIL6 +#define EPILR03_EIL7 _epilr03.bit._EIL7 +__IO_EXTENDED EPILR04STR _epilr04; +#define EPILR04 _epilr04.byte +#define EPILR04_EIL0 _epilr04.bit._EIL0 +#define EPILR04_EIL1 _epilr04.bit._EIL1 +#define EPILR04_EIL2 _epilr04.bit._EIL2 +#define EPILR04_EIL3 _epilr04.bit._EIL3 +#define EPILR04_EIL4 _epilr04.bit._EIL4 +#define EPILR04_EIL5 _epilr04.bit._EIL5 +#define EPILR04_EIL6 _epilr04.bit._EIL6 +#define EPILR04_EIL7 _epilr04.bit._EIL7 +__IO_EXTENDED EPILR05STR _epilr05; +#define EPILR05 _epilr05.byte +#define EPILR05_EIL0 _epilr05.bit._EIL0 +#define EPILR05_EIL1 _epilr05.bit._EIL1 +#define EPILR05_EIL2 _epilr05.bit._EIL2 +#define EPILR05_EIL3 _epilr05.bit._EIL3 +#define EPILR05_EIL4 _epilr05.bit._EIL4 +#define EPILR05_EIL5 _epilr05.bit._EIL5 +#define EPILR05_EIL6 _epilr05.bit._EIL6 +#define EPILR05_EIL7 _epilr05.bit._EIL7 +__IO_EXTENDED EPILR06STR _epilr06; +#define EPILR06 _epilr06.byte +#define EPILR06_EIL0 _epilr06.bit._EIL0 +#define EPILR06_EIL1 _epilr06.bit._EIL1 +#define EPILR06_EIL2 _epilr06.bit._EIL2 +#define EPILR06_EIL3 _epilr06.bit._EIL3 +#define EPILR06_EIL4 _epilr06.bit._EIL4 +#define EPILR06_EIL5 _epilr06.bit._EIL5 +#define EPILR06_EIL6 _epilr06.bit._EIL6 +#define EPILR06_EIL7 _epilr06.bit._EIL7 +__IO_EXTENDED EPILR07STR _epilr07; +#define EPILR07 _epilr07.byte +#define EPILR07_EIL0 _epilr07.bit._EIL0 +#define EPILR07_EIL1 _epilr07.bit._EIL1 +#define EPILR07_EIL2 _epilr07.bit._EIL2 +#define EPILR07_EIL3 _epilr07.bit._EIL3 +#define EPILR07_EIL4 _epilr07.bit._EIL4 +#define EPILR07_EIL5 _epilr07.bit._EIL5 +#define EPILR07_EIL6 _epilr07.bit._EIL6 +#define EPILR07_EIL7 _epilr07.bit._EIL7 +__IO_EXTENDED EPILR08STR _epilr08; +#define EPILR08 _epilr08.byte +#define EPILR08_EIL0 _epilr08.bit._EIL0 +#define EPILR08_EIL1 _epilr08.bit._EIL1 +#define EPILR08_EIL2 _epilr08.bit._EIL2 +#define EPILR08_EIL3 _epilr08.bit._EIL3 +#define EPILR08_EIL4 _epilr08.bit._EIL4 +#define EPILR08_EIL5 _epilr08.bit._EIL5 +#define EPILR08_EIL6 _epilr08.bit._EIL6 +#define EPILR08_EIL7 _epilr08.bit._EIL7 +__IO_EXTENDED EPILR09STR _epilr09; +#define EPILR09 _epilr09.byte +#define EPILR09_EIL0 _epilr09.bit._EIL0 +#define EPILR09_EIL1 _epilr09.bit._EIL1 +#define EPILR09_EIL2 _epilr09.bit._EIL2 +#define EPILR09_EIL3 _epilr09.bit._EIL3 +#define EPILR09_EIL4 _epilr09.bit._EIL4 +#define EPILR09_EIL5 _epilr09.bit._EIL5 +#define EPILR09_EIL6 _epilr09.bit._EIL6 +#define EPILR09_EIL7 _epilr09.bit._EIL7 +__IO_EXTENDED EPILR10STR _epilr10; +#define EPILR10 _epilr10.byte +#define EPILR10_EIL0 _epilr10.bit._EIL0 +#define EPILR10_EIL1 _epilr10.bit._EIL1 +__IO_EXTENDED PODR00STR _podr00; +#define PODR00 _podr00.byte +#define PODR00_OD0 _podr00.bit._OD0 +#define PODR00_OD1 _podr00.bit._OD1 +#define PODR00_OD2 _podr00.bit._OD2 +#define PODR00_OD3 _podr00.bit._OD3 +#define PODR00_OD4 _podr00.bit._OD4 +#define PODR00_OD5 _podr00.bit._OD5 +#define PODR00_OD6 _podr00.bit._OD6 +#define PODR00_OD7 _podr00.bit._OD7 +__IO_EXTENDED PODR01STR _podr01; +#define PODR01 _podr01.byte +#define PODR01_OD0 _podr01.bit._OD0 +#define PODR01_OD1 _podr01.bit._OD1 +#define PODR01_OD2 _podr01.bit._OD2 +#define PODR01_OD3 _podr01.bit._OD3 +#define PODR01_OD4 _podr01.bit._OD4 +#define PODR01_OD5 _podr01.bit._OD5 +#define PODR01_OD6 _podr01.bit._OD6 +#define PODR01_OD7 _podr01.bit._OD7 +__IO_EXTENDED PODR02STR _podr02; +#define PODR02 _podr02.byte +#define PODR02_OD0 _podr02.bit._OD0 +#define PODR02_OD1 _podr02.bit._OD1 +#define PODR02_OD2 _podr02.bit._OD2 +#define PODR02_OD3 _podr02.bit._OD3 +#define PODR02_OD4 _podr02.bit._OD4 +#define PODR02_OD5 _podr02.bit._OD5 +#define PODR02_OD6 _podr02.bit._OD6 +#define PODR02_OD7 _podr02.bit._OD7 +__IO_EXTENDED PODR03STR _podr03; +#define PODR03 _podr03.byte +#define PODR03_OD0 _podr03.bit._OD0 +#define PODR03_OD1 _podr03.bit._OD1 +#define PODR03_OD2 _podr03.bit._OD2 +#define PODR03_OD3 _podr03.bit._OD3 +#define PODR03_OD4 _podr03.bit._OD4 +#define PODR03_OD5 _podr03.bit._OD5 +#define PODR03_OD6 _podr03.bit._OD6 +#define PODR03_OD7 _podr03.bit._OD7 +__IO_EXTENDED PODR04STR _podr04; +#define PODR04 _podr04.byte +#define PODR04_OD0 _podr04.bit._OD0 +#define PODR04_OD1 _podr04.bit._OD1 +#define PODR04_OD2 _podr04.bit._OD2 +#define PODR04_OD3 _podr04.bit._OD3 +#define PODR04_OD4 _podr04.bit._OD4 +#define PODR04_OD5 _podr04.bit._OD5 +#define PODR04_OD6 _podr04.bit._OD6 +#define PODR04_OD7 _podr04.bit._OD7 +__IO_EXTENDED PODR05STR _podr05; +#define PODR05 _podr05.byte +#define PODR05_OD0 _podr05.bit._OD0 +#define PODR05_OD1 _podr05.bit._OD1 +#define PODR05_OD2 _podr05.bit._OD2 +#define PODR05_OD3 _podr05.bit._OD3 +#define PODR05_OD4 _podr05.bit._OD4 +#define PODR05_OD5 _podr05.bit._OD5 +#define PODR05_OD6 _podr05.bit._OD6 +#define PODR05_OD7 _podr05.bit._OD7 +__IO_EXTENDED PODR06STR _podr06; +#define PODR06 _podr06.byte +#define PODR06_OD0 _podr06.bit._OD0 +#define PODR06_OD1 _podr06.bit._OD1 +#define PODR06_OD2 _podr06.bit._OD2 +#define PODR06_OD3 _podr06.bit._OD3 +#define PODR06_OD4 _podr06.bit._OD4 +#define PODR06_OD5 _podr06.bit._OD5 +#define PODR06_OD6 _podr06.bit._OD6 +#define PODR06_OD7 _podr06.bit._OD7 +__IO_EXTENDED PODR07STR _podr07; +#define PODR07 _podr07.byte +#define PODR07_OD0 _podr07.bit._OD0 +#define PODR07_OD1 _podr07.bit._OD1 +#define PODR07_OD2 _podr07.bit._OD2 +#define PODR07_OD3 _podr07.bit._OD3 +#define PODR07_OD4 _podr07.bit._OD4 +#define PODR07_OD5 _podr07.bit._OD5 +#define PODR07_OD6 _podr07.bit._OD6 +#define PODR07_OD7 _podr07.bit._OD7 +__IO_EXTENDED PODR08STR _podr08; +#define PODR08 _podr08.byte +#define PODR08_OD0 _podr08.bit._OD0 +#define PODR08_OD1 _podr08.bit._OD1 +#define PODR08_OD2 _podr08.bit._OD2 +#define PODR08_OD3 _podr08.bit._OD3 +#define PODR08_OD4 _podr08.bit._OD4 +#define PODR08_OD5 _podr08.bit._OD5 +#define PODR08_OD6 _podr08.bit._OD6 +#define PODR08_OD7 _podr08.bit._OD7 +__IO_EXTENDED PODR09STR _podr09; +#define PODR09 _podr09.byte +#define PODR09_OD0 _podr09.bit._OD0 +#define PODR09_OD1 _podr09.bit._OD1 +#define PODR09_OD2 _podr09.bit._OD2 +#define PODR09_OD3 _podr09.bit._OD3 +#define PODR09_OD4 _podr09.bit._OD4 +#define PODR09_OD5 _podr09.bit._OD5 +#define PODR09_OD6 _podr09.bit._OD6 +#define PODR09_OD7 _podr09.bit._OD7 +__IO_EXTENDED PODR10STR _podr10; +#define PODR10 _podr10.byte +#define PODR10_OD0 _podr10.bit._OD0 +#define PODR10_OD1 _podr10.bit._OD1 +__IO_EXTENDED PHDR08STR _phdr08; +#define PHDR08 _phdr08.byte +#define PHDR08_HD0 _phdr08.bit._HD0 +#define PHDR08_HD1 _phdr08.bit._HD1 +#define PHDR08_HD2 _phdr08.bit._HD2 +#define PHDR08_HD3 _phdr08.bit._HD3 +#define PHDR08_HD4 _phdr08.bit._HD4 +#define PHDR08_HD5 _phdr08.bit._HD5 +#define PHDR08_HD6 _phdr08.bit._HD6 +#define PHDR08_HD7 _phdr08.bit._HD7 +__IO_EXTENDED PHDR09STR _phdr09; +#define PHDR09 _phdr09.byte +#define PHDR09_HD0 _phdr09.bit._HD0 +#define PHDR09_HD1 _phdr09.bit._HD1 +#define PHDR09_HD2 _phdr09.bit._HD2 +#define PHDR09_HD3 _phdr09.bit._HD3 +#define PHDR09_HD4 _phdr09.bit._HD4 +#define PHDR09_HD5 _phdr09.bit._HD5 +#define PHDR09_HD6 _phdr09.bit._HD6 +#define PHDR09_HD7 _phdr09.bit._HD7 +__IO_EXTENDED PHDR10STR _phdr10; +#define PHDR10 _phdr10.byte +#define PHDR10_HD0 _phdr10.bit._HD0 +#define PHDR10_HD1 _phdr10.bit._HD1 +#define PHDR10_HD2 _phdr10.bit._HD2 +#define PHDR10_HD3 _phdr10.bit._HD3 +#define PHDR10_HD4 _phdr10.bit._HD4 +#define PHDR10_HD5 _phdr10.bit._HD5 +#define PHDR10_HD6 _phdr10.bit._HD6 +#define PHDR10_HD7 _phdr10.bit._HD7 +__IO_EXTENDED PUCR00STR _pucr00; +#define PUCR00 _pucr00.byte +#define PUCR00_PU0 _pucr00.bit._PU0 +#define PUCR00_PU1 _pucr00.bit._PU1 +#define PUCR00_PU2 _pucr00.bit._PU2 +#define PUCR00_PU3 _pucr00.bit._PU3 +#define PUCR00_PU4 _pucr00.bit._PU4 +#define PUCR00_PU5 _pucr00.bit._PU5 +#define PUCR00_PU6 _pucr00.bit._PU6 +#define PUCR00_PU7 _pucr00.bit._PU7 +__IO_EXTENDED PUCR01STR _pucr01; +#define PUCR01 _pucr01.byte +#define PUCR01_PU0 _pucr01.bit._PU0 +#define PUCR01_PU1 _pucr01.bit._PU1 +#define PUCR01_PU2 _pucr01.bit._PU2 +#define PUCR01_PU3 _pucr01.bit._PU3 +#define PUCR01_PU4 _pucr01.bit._PU4 +#define PUCR01_PU5 _pucr01.bit._PU5 +#define PUCR01_PU6 _pucr01.bit._PU6 +#define PUCR01_PU7 _pucr01.bit._PU7 +__IO_EXTENDED PUCR02STR _pucr02; +#define PUCR02 _pucr02.byte +#define PUCR02_PU0 _pucr02.bit._PU0 +#define PUCR02_PU1 _pucr02.bit._PU1 +#define PUCR02_PU2 _pucr02.bit._PU2 +#define PUCR02_PU3 _pucr02.bit._PU3 +#define PUCR02_PU4 _pucr02.bit._PU4 +#define PUCR02_PU5 _pucr02.bit._PU5 +#define PUCR02_PU6 _pucr02.bit._PU6 +#define PUCR02_PU7 _pucr02.bit._PU7 +__IO_EXTENDED PUCR03STR _pucr03; +#define PUCR03 _pucr03.byte +#define PUCR03_PU0 _pucr03.bit._PU0 +#define PUCR03_PU1 _pucr03.bit._PU1 +#define PUCR03_PU2 _pucr03.bit._PU2 +#define PUCR03_PU3 _pucr03.bit._PU3 +#define PUCR03_PU4 _pucr03.bit._PU4 +#define PUCR03_PU5 _pucr03.bit._PU5 +#define PUCR03_PU6 _pucr03.bit._PU6 +#define PUCR03_PU7 _pucr03.bit._PU7 +__IO_EXTENDED PUCR04STR _pucr04; +#define PUCR04 _pucr04.byte +#define PUCR04_PU0 _pucr04.bit._PU0 +#define PUCR04_PU1 _pucr04.bit._PU1 +#define PUCR04_PU2 _pucr04.bit._PU2 +#define PUCR04_PU3 _pucr04.bit._PU3 +#define PUCR04_PU4 _pucr04.bit._PU4 +#define PUCR04_PU5 _pucr04.bit._PU5 +#define PUCR04_PU6 _pucr04.bit._PU6 +#define PUCR04_PU7 _pucr04.bit._PU7 +__IO_EXTENDED PUCR05STR _pucr05; +#define PUCR05 _pucr05.byte +#define PUCR05_PU0 _pucr05.bit._PU0 +#define PUCR05_PU1 _pucr05.bit._PU1 +#define PUCR05_PU2 _pucr05.bit._PU2 +#define PUCR05_PU3 _pucr05.bit._PU3 +#define PUCR05_PU4 _pucr05.bit._PU4 +#define PUCR05_PU5 _pucr05.bit._PU5 +#define PUCR05_PU6 _pucr05.bit._PU6 +#define PUCR05_PU7 _pucr05.bit._PU7 +__IO_EXTENDED PUCR06STR _pucr06; +#define PUCR06 _pucr06.byte +#define PUCR06_PU0 _pucr06.bit._PU0 +#define PUCR06_PU1 _pucr06.bit._PU1 +#define PUCR06_PU2 _pucr06.bit._PU2 +#define PUCR06_PU3 _pucr06.bit._PU3 +#define PUCR06_PU4 _pucr06.bit._PU4 +#define PUCR06_PU5 _pucr06.bit._PU5 +#define PUCR06_PU6 _pucr06.bit._PU6 +#define PUCR06_PU7 _pucr06.bit._PU7 +__IO_EXTENDED PUCR07STR _pucr07; +#define PUCR07 _pucr07.byte +#define PUCR07_PU0 _pucr07.bit._PU0 +#define PUCR07_PU1 _pucr07.bit._PU1 +#define PUCR07_PU2 _pucr07.bit._PU2 +#define PUCR07_PU3 _pucr07.bit._PU3 +#define PUCR07_PU4 _pucr07.bit._PU4 +#define PUCR07_PU5 _pucr07.bit._PU5 +#define PUCR07_PU6 _pucr07.bit._PU6 +#define PUCR07_PU7 _pucr07.bit._PU7 +__IO_EXTENDED PUCR08STR _pucr08; +#define PUCR08 _pucr08.byte +#define PUCR08_PU0 _pucr08.bit._PU0 +#define PUCR08_PU1 _pucr08.bit._PU1 +#define PUCR08_PU2 _pucr08.bit._PU2 +#define PUCR08_PU3 _pucr08.bit._PU3 +#define PUCR08_PU4 _pucr08.bit._PU4 +#define PUCR08_PU5 _pucr08.bit._PU5 +#define PUCR08_PU6 _pucr08.bit._PU6 +#define PUCR08_PU7 _pucr08.bit._PU7 +__IO_EXTENDED PUCR09STR _pucr09; +#define PUCR09 _pucr09.byte +#define PUCR09_PU0 _pucr09.bit._PU0 +#define PUCR09_PU1 _pucr09.bit._PU1 +#define PUCR09_PU2 _pucr09.bit._PU2 +#define PUCR09_PU3 _pucr09.bit._PU3 +#define PUCR09_PU4 _pucr09.bit._PU4 +#define PUCR09_PU5 _pucr09.bit._PU5 +#define PUCR09_PU6 _pucr09.bit._PU6 +#define PUCR09_PU7 _pucr09.bit._PU7 +__IO_EXTENDED PUCR10STR _pucr10; +#define PUCR10 _pucr10.byte +#define PUCR10_PU0 _pucr10.bit._PU0 +#define PUCR10_PU1 _pucr10.bit._PU1 +__IO_EXTENDED EPSR00STR _epsr00; +#define EPSR00 _epsr00.byte +#define EPSR00_PS0 _epsr00.bit._PS0 +#define EPSR00_PS1 _epsr00.bit._PS1 +#define EPSR00_PS2 _epsr00.bit._PS2 +#define EPSR00_PS3 _epsr00.bit._PS3 +#define EPSR00_PS4 _epsr00.bit._PS4 +#define EPSR00_PS5 _epsr00.bit._PS5 +#define EPSR00_PS6 _epsr00.bit._PS6 +#define EPSR00_PS7 _epsr00.bit._PS7 +__IO_EXTENDED EPSR01STR _epsr01; +#define EPSR01 _epsr01.byte +#define EPSR01_PS0 _epsr01.bit._PS0 +#define EPSR01_PS1 _epsr01.bit._PS1 +#define EPSR01_PS2 _epsr01.bit._PS2 +#define EPSR01_PS3 _epsr01.bit._PS3 +#define EPSR01_PS4 _epsr01.bit._PS4 +#define EPSR01_PS5 _epsr01.bit._PS5 +#define EPSR01_PS6 _epsr01.bit._PS6 +#define EPSR01_PS7 _epsr01.bit._PS7 +__IO_EXTENDED EPSR02STR _epsr02; +#define EPSR02 _epsr02.byte +#define EPSR02_PS0 _epsr02.bit._PS0 +#define EPSR02_PS1 _epsr02.bit._PS1 +#define EPSR02_PS2 _epsr02.bit._PS2 +#define EPSR02_PS3 _epsr02.bit._PS3 +#define EPSR02_PS4 _epsr02.bit._PS4 +#define EPSR02_PS5 _epsr02.bit._PS5 +#define EPSR02_PS6 _epsr02.bit._PS6 +#define EPSR02_PS7 _epsr02.bit._PS7 +__IO_EXTENDED EPSR03STR _epsr03; +#define EPSR03 _epsr03.byte +#define EPSR03_PS0 _epsr03.bit._PS0 +#define EPSR03_PS1 _epsr03.bit._PS1 +#define EPSR03_PS2 _epsr03.bit._PS2 +#define EPSR03_PS3 _epsr03.bit._PS3 +#define EPSR03_PS4 _epsr03.bit._PS4 +#define EPSR03_PS5 _epsr03.bit._PS5 +#define EPSR03_PS6 _epsr03.bit._PS6 +#define EPSR03_PS7 _epsr03.bit._PS7 +__IO_EXTENDED EPSR04STR _epsr04; +#define EPSR04 _epsr04.byte +#define EPSR04_PS0 _epsr04.bit._PS0 +#define EPSR04_PS1 _epsr04.bit._PS1 +#define EPSR04_PS2 _epsr04.bit._PS2 +#define EPSR04_PS3 _epsr04.bit._PS3 +#define EPSR04_PS4 _epsr04.bit._PS4 +#define EPSR04_PS5 _epsr04.bit._PS5 +#define EPSR04_PS6 _epsr04.bit._PS6 +#define EPSR04_PS7 _epsr04.bit._PS7 +__IO_EXTENDED EPSR05STR _epsr05; +#define EPSR05 _epsr05.byte +#define EPSR05_PS0 _epsr05.bit._PS0 +#define EPSR05_PS1 _epsr05.bit._PS1 +#define EPSR05_PS2 _epsr05.bit._PS2 +#define EPSR05_PS3 _epsr05.bit._PS3 +#define EPSR05_PS4 _epsr05.bit._PS4 +#define EPSR05_PS5 _epsr05.bit._PS5 +#define EPSR05_PS6 _epsr05.bit._PS6 +#define EPSR05_PS7 _epsr05.bit._PS7 +__IO_EXTENDED EPSR06STR _epsr06; +#define EPSR06 _epsr06.byte +#define EPSR06_PS0 _epsr06.bit._PS0 +#define EPSR06_PS1 _epsr06.bit._PS1 +#define EPSR06_PS2 _epsr06.bit._PS2 +#define EPSR06_PS3 _epsr06.bit._PS3 +#define EPSR06_PS4 _epsr06.bit._PS4 +#define EPSR06_PS5 _epsr06.bit._PS5 +#define EPSR06_PS6 _epsr06.bit._PS6 +#define EPSR06_PS7 _epsr06.bit._PS7 +__IO_EXTENDED EPSR07STR _epsr07; +#define EPSR07 _epsr07.byte +#define EPSR07_PS0 _epsr07.bit._PS0 +#define EPSR07_PS1 _epsr07.bit._PS1 +#define EPSR07_PS2 _epsr07.bit._PS2 +#define EPSR07_PS3 _epsr07.bit._PS3 +#define EPSR07_PS4 _epsr07.bit._PS4 +#define EPSR07_PS5 _epsr07.bit._PS5 +#define EPSR07_PS6 _epsr07.bit._PS6 +#define EPSR07_PS7 _epsr07.bit._PS7 +__IO_EXTENDED EPSR08STR _epsr08; +#define EPSR08 _epsr08.byte +#define EPSR08_PS0 _epsr08.bit._PS0 +#define EPSR08_PS1 _epsr08.bit._PS1 +#define EPSR08_PS2 _epsr08.bit._PS2 +#define EPSR08_PS3 _epsr08.bit._PS3 +#define EPSR08_PS4 _epsr08.bit._PS4 +#define EPSR08_PS5 _epsr08.bit._PS5 +#define EPSR08_PS6 _epsr08.bit._PS6 +#define EPSR08_PS7 _epsr08.bit._PS7 +__IO_EXTENDED EPSR09STR _epsr09; +#define EPSR09 _epsr09.byte +#define EPSR09_PS0 _epsr09.bit._PS0 +#define EPSR09_PS1 _epsr09.bit._PS1 +#define EPSR09_PS2 _epsr09.bit._PS2 +#define EPSR09_PS3 _epsr09.bit._PS3 +#define EPSR09_PS4 _epsr09.bit._PS4 +#define EPSR09_PS5 _epsr09.bit._PS5 +#define EPSR09_PS6 _epsr09.bit._PS6 +#define EPSR09_PS7 _epsr09.bit._PS7 +__IO_EXTENDED EPSR10STR _epsr10; +#define EPSR10 _epsr10.byte +#define EPSR10_PS0 _epsr10.bit._PS0 +#define EPSR10_PS1 _epsr10.bit._PS1 +__IO_EXTENDED ADER0STR _ader0; +#define ADER0 _ader0.byte +#define ADER0_ADE0 _ader0.bit._ADE0 +#define ADER0_ADE1 _ader0.bit._ADE1 +#define ADER0_ADE2 _ader0.bit._ADE2 +#define ADER0_ADE3 _ader0.bit._ADE3 +#define ADER0_ADE4 _ader0.bit._ADE4 +#define ADER0_ADE5 _ader0.bit._ADE5 +#define ADER0_ADE6 _ader0.bit._ADE6 +#define ADER0_ADE7 _ader0.bit._ADE7 +__IO_EXTENDED ADER1STR _ader1; +#define ADER1 _ader1.byte +#define ADER1_ADE8 _ader1.bit._ADE8 +#define ADER1_ADE9 _ader1.bit._ADE9 +#define ADER1_ADE10 _ader1.bit._ADE10 +#define ADER1_ADE11 _ader1.bit._ADE11 +#define ADER1_ADE12 _ader1.bit._ADE12 +#define ADER1_ADE13 _ader1.bit._ADE13 +#define ADER1_ADE14 _ader1.bit._ADE14 +#define ADER1_ADE15 _ader1.bit._ADE15 +__IO_EXTENDED ADER2STR _ader2; +#define ADER2 _ader2.byte +#define ADER2_ADE16 _ader2.bit._ADE16 +#define ADER2_ADE17 _ader2.bit._ADE17 +#define ADER2_ADE18 _ader2.bit._ADE18 +#define ADER2_ADE19 _ader2.bit._ADE19 +#define ADER2_ADE20 _ader2.bit._ADE20 +#define ADER2_ADE21 _ader2.bit._ADE21 +#define ADER2_ADE22 _ader2.bit._ADE22 +#define ADER2_ADE23 _ader2.bit._ADE23 +__IO_EXTENDED PRRR0STR _prrr0; +#define PRRR0 _prrr0.byte +#define PRRR0_INT0_R _prrr0.bit._INT0_R +#define PRRR0_INT1_R _prrr0.bit._INT1_R +#define PRRR0_INT2_R _prrr0.bit._INT2_R +#define PRRR0_INT3_R _prrr0.bit._INT3_R +#define PRRR0_INT4_R _prrr0.bit._INT4_R +#define PRRR0_INT5_R _prrr0.bit._INT5_R +#define PRRR0_INT6_R _prrr0.bit._INT6_R +#define PRRR0_INT7_R _prrr0.bit._INT7_R +__IO_EXTENDED PRRR1STR _prrr1; +#define PRRR1 _prrr1.byte +#define PRRR1_INT8_R _prrr1.bit._INT8_R +#define PRRR1_INT9_R _prrr1.bit._INT9_R +#define PRRR1_INT10_R _prrr1.bit._INT10_R +#define PRRR1_INT11_R _prrr1.bit._INT11_R +#define PRRR1_INT12_R _prrr1.bit._INT12_R +#define PRRR1_INT13_R _prrr1.bit._INT13_R +#define PRRR1_INT14_R _prrr1.bit._INT14_R +#define PRRR1_INT15_R _prrr1.bit._INT15_R +__IO_EXTENDED PRRR2STR _prrr2; +#define PRRR2 _prrr2.byte +#define PRRR2_PPG0_R _prrr2.bit._PPG0_R +#define PRRR2_PPG1_R _prrr2.bit._PPG1_R +#define PRRR2_PPG2_R _prrr2.bit._PPG2_R +#define PRRR2_PPG3_R _prrr2.bit._PPG3_R +#define PRRR2_PPG4_R _prrr2.bit._PPG4_R +#define PRRR2_PPG5_R _prrr2.bit._PPG5_R +#define PRRR2_PPG6_R _prrr2.bit._PPG6_R +#define PRRR2_PPG7_R _prrr2.bit._PPG7_R +__IO_EXTENDED PRRR3STR _prrr3; +#define PRRR3 _prrr3.byte +#define PRRR3_TIN0_R _prrr3.bit._TIN0_R +#define PRRR3_TOT0_R _prrr3.bit._TOT0_R +#define PRRR3_TIN1_R _prrr3.bit._TIN1_R +#define PRRR3_TOT1_R _prrr3.bit._TOT1_R +#define PRRR3_TIN2_R _prrr3.bit._TIN2_R +#define PRRR3_TOT2_R _prrr3.bit._TOT2_R +#define PRRR3_TIN3_R _prrr3.bit._TIN3_R +#define PRRR3_TOT3_R _prrr3.bit._TOT3_R +__IO_EXTENDED PRRR4STR _prrr4; +#define PRRR4 _prrr4.byte +#define PRRR4_IN0_R _prrr4.bit._IN0_R +#define PRRR4_IN1_R _prrr4.bit._IN1_R +#define PRRR4_IN2_R _prrr4.bit._IN2_R +#define PRRR4_IN3_R _prrr4.bit._IN3_R +#define PRRR4_IN4_R _prrr4.bit._IN4_R +#define PRRR4_IN5_R _prrr4.bit._IN5_R +#define PRRR4_IN6_R _prrr4.bit._IN6_R +#define PRRR4_IN7_R _prrr4.bit._IN7_R +__IO_EXTENDED PRRR5STR _prrr5; +#define PRRR5 _prrr5.byte +#define PRRR5_OUT0_R _prrr5.bit._OUT0_R +#define PRRR5_OUT1_R _prrr5.bit._OUT1_R +#define PRRR5_OUT2_R _prrr5.bit._OUT2_R +#define PRRR5_OUT3_R _prrr5.bit._OUT3_R +#define PRRR5_OUT6_R _prrr5.bit._OUT6_R +#define PRRR5_OUT7_R _prrr5.bit._OUT7_R +__IO_EXTENDED PRRR6STR _prrr6; +#define PRRR6 _prrr6.byte +#define PRRR6_SGO0_R _prrr6.bit._SGO0_R +#define PRRR6_SGA0_R _prrr6.bit._SGA0_R +#define PRRR6_FRCK0_R _prrr6.bit._FRCK0_R +#define PRRR6_SIN2_R _prrr6.bit._SIN2_R +#define PRRR6_SOT2_R _prrr6.bit._SOT2_R +#define PRRR6_SCK2_R _prrr6.bit._SCK2_R +#define PRRR6_CKOT1_R _prrr6.bit._CKOT1_R +#define PRRR6_CKOTX1_R _prrr6.bit._CKOTX1_R +__IO_EXTENDED PRRR7STR _prrr7; +#define PRRR7 _prrr7.byte +#define PRRR7_ADTG_R _prrr7.bit._ADTG_R +#define PRRR7_NMI_R _prrr7.bit._NMI_R +#define PRRR7_CS3_R _prrr7.bit._CS3_R +#define PRRR7_INT3_R1 _prrr7.bit._INT3_R1 +#define PRRR7_INT4_R1 _prrr7.bit._INT4_R1 +#define PRRR7_INT5_R1 _prrr7.bit._INT5_R1 +#define PRRR7_RX2_R _prrr7.bit._RX2_R +#define PRRR7_TX2_R _prrr7.bit._TX2_R +__IO_EXTENDED PRRR8STR _prrr8; +#define PRRR8 _prrr8.byte +#define PRRR8_SIN7_R _prrr8.bit._SIN7_R +#define PRRR8_SOT7_R _prrr8.bit._SOT7_R +#define PRRR8_SCK7_R _prrr8.bit._SCK7_R +#define PRRR8_SIN8_R _prrr8.bit._SIN8_R +#define PRRR8_SOT8_R _prrr8.bit._SOT8_R +#define PRRR8_SCK8_R _prrr8.bit._SCK8_R +#define PRRR8_SIN9_R _prrr8.bit._SIN9_R +#define PRRR8_SOT9_R _prrr8.bit._SOT9_R +__IO_EXTENDED PRRR9STR _prrr9; +#define PRRR9 _prrr9.byte +#define PRRR9_SCK9_R _prrr9.bit._SCK9_R +#define PRRR9_SGO1_R _prrr9.bit._SGO1_R +#define PRRR9_SGA1_R _prrr9.bit._SGA1_R +#define PRRR9_FRCK2_R _prrr9.bit._FRCK2_R +#define PRRR9_OUT10_R _prrr9.bit._OUT10_R +#define PRRR9_CKOT0_R _prrr9.bit._CKOT0_R +__IO_EXTENDED WTBR0STR _wtbr0; +#define WTBR0 _wtbr0.word +#define WTBR0_D0 _wtbr0.bit._D0 +#define WTBR0_D1 _wtbr0.bit._D1 +#define WTBR0_D2 _wtbr0.bit._D2 +#define WTBR0_D3 _wtbr0.bit._D3 +#define WTBR0_D4 _wtbr0.bit._D4 +#define WTBR0_D5 _wtbr0.bit._D5 +#define WTBR0_D6 _wtbr0.bit._D6 +#define WTBR0_D7 _wtbr0.bit._D7 +#define WTBR0_D8 _wtbr0.bit._D8 +#define WTBR0_D9 _wtbr0.bit._D9 +#define WTBR0_D10 _wtbr0.bit._D10 +#define WTBR0_D11 _wtbr0.bit._D11 +#define WTBR0_D12 _wtbr0.bit._D12 +#define WTBR0_D13 _wtbr0.bit._D13 +#define WTBR0_D14 _wtbr0.bit._D14 +#define WTBR0_D15 _wtbr0.bit._D15 +#define WTBR0_D _wtbr0.bitc._D +__IO_EXTENDED WTBRL0STR _wtbrl0; +#define WTBRL0 _wtbrl0.byte +#define WTBRL0_D0 _wtbrl0.bit._D0 +#define WTBRL0_D1 _wtbrl0.bit._D1 +#define WTBRL0_D2 _wtbrl0.bit._D2 +#define WTBRL0_D3 _wtbrl0.bit._D3 +#define WTBRL0_D4 _wtbrl0.bit._D4 +#define WTBRL0_D5 _wtbrl0.bit._D5 +#define WTBRL0_D6 _wtbrl0.bit._D6 +#define WTBRL0_D7 _wtbrl0.bit._D7 +__IO_EXTENDED WTBRH0STR _wtbrh0; +#define WTBRH0 _wtbrh0.byte +#define WTBRH0_D8 _wtbrh0.bit._D8 +#define WTBRH0_D9 _wtbrh0.bit._D9 +#define WTBRH0_D10 _wtbrh0.bit._D10 +#define WTBRH0_D11 _wtbrh0.bit._D11 +#define WTBRH0_D12 _wtbrh0.bit._D12 +#define WTBRH0_D13 _wtbrh0.bit._D13 +#define WTBRH0_D14 _wtbrh0.bit._D14 +#define WTBRH0_D15 _wtbrh0.bit._D15 +__IO_EXTENDED WTBR1STR _wtbr1; +#define WTBR1 _wtbr1.byte +#define WTBR1_D16 _wtbr1.bit._D16 +#define WTBR1_D17 _wtbr1.bit._D17 +#define WTBR1_D18 _wtbr1.bit._D18 +#define WTBR1_D19 _wtbr1.bit._D19 +#define WTBR1_D20 _wtbr1.bit._D20 +#define WTBR1_D1 _wtbr1.bitc._D1 +__IO_EXTENDED WTSRSTR _wtsr; +#define WTSR _wtsr.byte +#define WTSR_S0 _wtsr.bit._S0 +#define WTSR_S1 _wtsr.bit._S1 +#define WTSR_S2 _wtsr.bit._S2 +#define WTSR_S3 _wtsr.bit._S3 +#define WTSR_S4 _wtsr.bit._S4 +#define WTSR_S5 _wtsr.bit._S5 +#define WTSR_S _wtsr.bitc._S +__IO_EXTENDED WTMRSTR _wtmr; +#define WTMR _wtmr.byte +#define WTMR_M0 _wtmr.bit._M0 +#define WTMR_M1 _wtmr.bit._M1 +#define WTMR_M2 _wtmr.bit._M2 +#define WTMR_M3 _wtmr.bit._M3 +#define WTMR_M4 _wtmr.bit._M4 +#define WTMR_M5 _wtmr.bit._M5 +#define WTMR_M _wtmr.bitc._M +__IO_EXTENDED WTHRSTR _wthr; +#define WTHR _wthr.byte +#define WTHR_H0 _wthr.bit._H0 +#define WTHR_H1 _wthr.bit._H1 +#define WTHR_H2 _wthr.bit._H2 +#define WTHR_H3 _wthr.bit._H3 +#define WTHR_H4 _wthr.bit._H4 +#define WTHR_H _wthr.bitc._H +__IO_EXTENDED WTCERSTR _wtcer; +#define WTCER _wtcer.byte +#define WTCER_INT4 _wtcer.bit._INT4 +#define WTCER_INTE4 _wtcer.bit._INTE4 +__IO_EXTENDED WTCKSRSTR _wtcksr; +#define WTCKSR _wtcksr.byte +#define WTCKSR_CKSEL0 _wtcksr.bit._CKSEL0 +#define WTCKSR_CKSEL1 _wtcksr.bit._CKSEL1 +#define WTCKSR_CKSEL _wtcksr.bitc._CKSEL +__IO_EXTENDED WTCRSTR _wtcr; +#define WTCR _wtcr.word +#define WTCR_ST _wtcr.bit._ST +#define WTCR_OE _wtcr.bit._OE +#define WTCR_UPDT _wtcr.bit._UPDT +#define WTCR_RUN _wtcr.bit._RUN +#define WTCR_INT0 _wtcr.bit._INT0 +#define WTCR_INTE0 _wtcr.bit._INTE0 +#define WTCR_INT1 _wtcr.bit._INT1 +#define WTCR_INTE1 _wtcr.bit._INTE1 +#define WTCR_INT2 _wtcr.bit._INT2 +#define WTCR_INTE2 _wtcr.bit._INTE2 +#define WTCR_INT3 _wtcr.bit._INT3 +#define WTCR_INTE3 _wtcr.bit._INTE3 +__IO_EXTENDED WTCRLSTR _wtcrl; +#define WTCRL _wtcrl.byte +#define WTCRL_ST _wtcrl.bit._ST +#define WTCRL_OE _wtcrl.bit._OE +#define WTCRL_UPDT _wtcrl.bit._UPDT +#define WTCRL_RUN _wtcrl.bit._RUN +__IO_EXTENDED WTCRHSTR _wtcrh; +#define WTCRH _wtcrh.byte +#define WTCRH_INT0 _wtcrh.bit._INT0 +#define WTCRH_INTE0 _wtcrh.bit._INTE0 +#define WTCRH_INT1 _wtcrh.bit._INT1 +#define WTCRH_INTE1 _wtcrh.bit._INTE1 +#define WTCRH_INT2 _wtcrh.bit._INT2 +#define WTCRH_INTE2 _wtcrh.bit._INTE2 +#define WTCRH_INT3 _wtcrh.bit._INT3 +#define WTCRH_INTE3 _wtcrh.bit._INTE3 +__IO_EXTENDED CUCRSTR _cucr; +#define CUCR _cucr.byte +#define CUCR_INTEN _cucr.bit._INTEN +#define CUCR_INT _cucr.bit._INT +#define CUCR_CKSEL _cucr.bit._CKSEL +#define CUCR_STRT _cucr.bit._STRT +#define CUCR_RESV _cucr.bit._RESV +__IO_EXTENDED CUTDSTR _cutd; +#define CUTD _cutd.word +#define CUTD_TDD0 _cutd.bit._TDD0 +#define CUTD_TDD1 _cutd.bit._TDD1 +#define CUTD_TDD2 _cutd.bit._TDD2 +#define CUTD_TDD3 _cutd.bit._TDD3 +#define CUTD_TDD4 _cutd.bit._TDD4 +#define CUTD_TDD5 _cutd.bit._TDD5 +#define CUTD_TDD6 _cutd.bit._TDD6 +#define CUTD_TDD7 _cutd.bit._TDD7 +#define CUTD_TDD8 _cutd.bit._TDD8 +#define CUTD_TDD9 _cutd.bit._TDD9 +#define CUTD_TDD10 _cutd.bit._TDD10 +#define CUTD_TDD11 _cutd.bit._TDD11 +#define CUTD_TDD12 _cutd.bit._TDD12 +#define CUTD_TDD13 _cutd.bit._TDD13 +#define CUTD_TDD14 _cutd.bit._TDD14 +#define CUTD_TDD15 _cutd.bit._TDD15 +#define CUTD_TDD _cutd.bitc._TDD +__IO_EXTENDED CUTDLSTR _cutdl; +#define CUTDL _cutdl.byte +#define CUTDL_TDD0 _cutdl.bit._TDD0 +#define CUTDL_TDD1 _cutdl.bit._TDD1 +#define CUTDL_TDD2 _cutdl.bit._TDD2 +#define CUTDL_TDD3 _cutdl.bit._TDD3 +#define CUTDL_TDD4 _cutdl.bit._TDD4 +#define CUTDL_TDD5 _cutdl.bit._TDD5 +#define CUTDL_TDD6 _cutdl.bit._TDD6 +#define CUTDL_TDD7 _cutdl.bit._TDD7 +__IO_EXTENDED CUTDHSTR _cutdh; +#define CUTDH _cutdh.byte +#define CUTDH_TDD8 _cutdh.bit._TDD8 +#define CUTDH_TDD9 _cutdh.bit._TDD9 +#define CUTDH_TDD10 _cutdh.bit._TDD10 +#define CUTDH_TDD11 _cutdh.bit._TDD11 +#define CUTDH_TDD12 _cutdh.bit._TDD12 +#define CUTDH_TDD13 _cutdh.bit._TDD13 +#define CUTDH_TDD14 _cutdh.bit._TDD14 +#define CUTDH_TDD15 _cutdh.bit._TDD15 +__IO_EXTENDED CUTRSTR _cutr; +#define CUTR _cutr.lword +#define CUTR_TDR0 _cutr.bit._TDR0 +#define CUTR_TDR1 _cutr.bit._TDR1 +#define CUTR_TDR2 _cutr.bit._TDR2 +#define CUTR_TDR3 _cutr.bit._TDR3 +#define CUTR_TDR4 _cutr.bit._TDR4 +#define CUTR_TDR5 _cutr.bit._TDR5 +#define CUTR_TDR6 _cutr.bit._TDR6 +#define CUTR_TDR7 _cutr.bit._TDR7 +#define CUTR_TDR8 _cutr.bit._TDR8 +#define CUTR_TDR9 _cutr.bit._TDR9 +#define CUTR_TDR10 _cutr.bit._TDR10 +#define CUTR_TDR11 _cutr.bit._TDR11 +#define CUTR_TDR12 _cutr.bit._TDR12 +#define CUTR_TDR13 _cutr.bit._TDR13 +#define CUTR_TDR14 _cutr.bit._TDR14 +#define CUTR_TDR15 _cutr.bit._TDR15 +#define CUTR_TDR16 _cutr.bit._TDR16 +#define CUTR_TDR17 _cutr.bit._TDR17 +#define CUTR_TDR18 _cutr.bit._TDR18 +#define CUTR_TDR19 _cutr.bit._TDR19 +#define CUTR_TDR20 _cutr.bit._TDR20 +#define CUTR_TDR21 _cutr.bit._TDR21 +#define CUTR_TDR22 _cutr.bit._TDR22 +#define CUTR_TDR23 _cutr.bit._TDR23 +__IO_EXTENDED CUTR2STR _cutr2; +#define CUTR2 _cutr2.word +#define CUTR2_TDR0 _cutr2.bit._TDR0 +#define CUTR2_TDR1 _cutr2.bit._TDR1 +#define CUTR2_TDR2 _cutr2.bit._TDR2 +#define CUTR2_TDR3 _cutr2.bit._TDR3 +#define CUTR2_TDR4 _cutr2.bit._TDR4 +#define CUTR2_TDR5 _cutr2.bit._TDR5 +#define CUTR2_TDR6 _cutr2.bit._TDR6 +#define CUTR2_TDR7 _cutr2.bit._TDR7 +#define CUTR2_TDR8 _cutr2.bit._TDR8 +#define CUTR2_TDR9 _cutr2.bit._TDR9 +#define CUTR2_TDR10 _cutr2.bit._TDR10 +#define CUTR2_TDR11 _cutr2.bit._TDR11 +#define CUTR2_TDR12 _cutr2.bit._TDR12 +#define CUTR2_TDR13 _cutr2.bit._TDR13 +#define CUTR2_TDR14 _cutr2.bit._TDR14 +#define CUTR2_TDR15 _cutr2.bit._TDR15 +__IO_EXTENDED CUTR2LSTR _cutr2l; +#define CUTR2L _cutr2l.byte +#define CUTR2L_TDR0 _cutr2l.bit._TDR0 +#define CUTR2L_TDR1 _cutr2l.bit._TDR1 +#define CUTR2L_TDR2 _cutr2l.bit._TDR2 +#define CUTR2L_TDR3 _cutr2l.bit._TDR3 +#define CUTR2L_TDR4 _cutr2l.bit._TDR4 +#define CUTR2L_TDR5 _cutr2l.bit._TDR5 +#define CUTR2L_TDR6 _cutr2l.bit._TDR6 +#define CUTR2L_TDR7 _cutr2l.bit._TDR7 +__IO_EXTENDED CUTR2HSTR _cutr2h; +#define CUTR2H _cutr2h.byte +#define CUTR2H_TDR8 _cutr2h.bit._TDR8 +#define CUTR2H_TDR9 _cutr2h.bit._TDR9 +#define CUTR2H_TDR10 _cutr2h.bit._TDR10 +#define CUTR2H_TDR11 _cutr2h.bit._TDR11 +#define CUTR2H_TDR12 _cutr2h.bit._TDR12 +#define CUTR2H_TDR13 _cutr2h.bit._TDR13 +#define CUTR2H_TDR14 _cutr2h.bit._TDR14 +#define CUTR2H_TDR15 _cutr2h.bit._TDR15 +__IO_EXTENDED CUTR1STR _cutr1; +#define CUTR1 _cutr1.word +#define CUTR1_TDR16 _cutr1.bit._TDR16 +#define CUTR1_TDR17 _cutr1.bit._TDR17 +#define CUTR1_TDR18 _cutr1.bit._TDR18 +#define CUTR1_TDR19 _cutr1.bit._TDR19 +#define CUTR1_TDR20 _cutr1.bit._TDR20 +#define CUTR1_TDR21 _cutr1.bit._TDR21 +#define CUTR1_TDR22 _cutr1.bit._TDR22 +#define CUTR1_TDR23 _cutr1.bit._TDR23 +__IO_EXTENDED CUTR1LSTR _cutr1l; +#define CUTR1L _cutr1l.byte +#define CUTR1L_TDR16 _cutr1l.bit._TDR16 +#define CUTR1L_TDR17 _cutr1l.bit._TDR17 +#define CUTR1L_TDR18 _cutr1l.bit._TDR18 +#define CUTR1L_TDR19 _cutr1l.bit._TDR19 +#define CUTR1L_TDR20 _cutr1l.bit._TDR20 +#define CUTR1L_TDR21 _cutr1l.bit._TDR21 +#define CUTR1L_TDR22 _cutr1l.bit._TDR22 +#define CUTR1L_TDR23 _cutr1l.bit._TDR23 +__IO_EXTENDED CUTR1HSTR _cutr1h; +#define CUTR1H _cutr1h.byte +__IO_EXTENDED TMISRSTR _tmisr; +#define TMISR _tmisr.byte +#define TMISR_TMIS0 _tmisr.bit._TMIS0 +#define TMISR_TMIS1 _tmisr.bit._TMIS1 +#define TMISR_TMIS2 _tmisr.bit._TMIS2 +#define TMISR_TMIS3 _tmisr.bit._TMIS3 +#define TMISR_TMIS4 _tmisr.bit._TMIS4 +#define TMISR_TMIS5 _tmisr.bit._TMIS5 +__IO_EXTENDED SMR7STR _smr7; +#define SMR7 _smr7.byte +#define SMR7_SOE _smr7.bit._SOE +#define SMR7_SCKE _smr7.bit._SCKE +#define SMR7_UPCL _smr7.bit._UPCL +#define SMR7_REST _smr7.bit._REST +#define SMR7_EXT _smr7.bit._EXT +#define SMR7_OTO _smr7.bit._OTO +#define SMR7_MD0 _smr7.bit._MD0 +#define SMR7_MD1 _smr7.bit._MD1 +#define SMR7_MD _smr7.bitc._MD +__IO_EXTENDED SCR7STR _scr7; +#define SCR7 _scr7.byte +#define SCR7_TXE _scr7.bit._TXE +#define SCR7_RXE _scr7.bit._RXE +#define SCR7_CRE _scr7.bit._CRE +#define SCR7_AD _scr7.bit._AD +#define SCR7_CL _scr7.bit._CL +#define SCR7_SBL _scr7.bit._SBL +#define SCR7_P _scr7.bit._P +#define SCR7_PEN _scr7.bit._PEN +__IO_EXTENDED IO_BYTE _tdr7; +#define TDR7 _tdr7 +__IO_EXTENDED IO_BYTE _rdr7; +#define RDR7 _rdr7 +__IO_EXTENDED SSR7STR _ssr7; +#define SSR7 _ssr7.byte +#define SSR7_TIE _ssr7.bit._TIE +#define SSR7_RIE _ssr7.bit._RIE +#define SSR7_BDS _ssr7.bit._BDS +#define SSR7_TDRE _ssr7.bit._TDRE +#define SSR7_RDRF _ssr7.bit._RDRF +#define SSR7_FRE _ssr7.bit._FRE +#define SSR7_ORE _ssr7.bit._ORE +#define SSR7_PE _ssr7.bit._PE +__IO_EXTENDED ECCR7STR _eccr7; +#define ECCR7 _eccr7.byte +#define ECCR7_TBI _eccr7.bit._TBI +#define ECCR7_RBI _eccr7.bit._RBI +#define ECCR7_BIE _eccr7.bit._BIE +#define ECCR7_SSM _eccr7.bit._SSM +#define ECCR7_SCDE _eccr7.bit._SCDE +#define ECCR7_MS _eccr7.bit._MS +#define ECCR7_LBR _eccr7.bit._LBR +#define ECCR7_INV _eccr7.bit._INV +__IO_EXTENDED ESCR7STR _escr7; +#define ESCR7 _escr7.byte +#define ESCR7_SCES _escr7.bit._SCES +#define ESCR7_CCO _escr7.bit._CCO +#define ESCR7_SIOP _escr7.bit._SIOP +#define ESCR7_SOPE _escr7.bit._SOPE +#define ESCR7_LBL0 _escr7.bit._LBL0 +#define ESCR7_LBL1 _escr7.bit._LBL1 +#define ESCR7_LBD _escr7.bit._LBD +#define ESCR7_LBIE _escr7.bit._LBIE +#define ESCR7_LBL _escr7.bitc._LBL +__IO_EXTENDED BGR7STR _bgr7; +#define BGR7 _bgr7.word +#define BGR7_BGR0 _bgr7.bit._BGR0 +#define BGR7_BGR1 _bgr7.bit._BGR1 +#define BGR7_BGR2 _bgr7.bit._BGR2 +#define BGR7_BGR3 _bgr7.bit._BGR3 +#define BGR7_BGR4 _bgr7.bit._BGR4 +#define BGR7_BGR5 _bgr7.bit._BGR5 +#define BGR7_BGR6 _bgr7.bit._BGR6 +#define BGR7_BGR7 _bgr7.bit._BGR7 +#define BGR7_BGR8 _bgr7.bit._BGR8 +#define BGR7_BGR9 _bgr7.bit._BGR9 +#define BGR7_BGR10 _bgr7.bit._BGR10 +#define BGR7_BGR11 _bgr7.bit._BGR11 +#define BGR7_BGR12 _bgr7.bit._BGR12 +#define BGR7_BGR13 _bgr7.bit._BGR13 +#define BGR7_BGR14 _bgr7.bit._BGR14 +#define BGR7_BGR15 _bgr7.bit._BGR15 +#define BGR7_BGR _bgr7.bitc._BGR +__IO_EXTENDED BGRL7STR _bgrl7; +#define BGRL7 _bgrl7.byte +#define BGRL7_BGR0 _bgrl7.bit._BGR0 +#define BGRL7_BGR1 _bgrl7.bit._BGR1 +#define BGRL7_BGR2 _bgrl7.bit._BGR2 +#define BGRL7_BGR3 _bgrl7.bit._BGR3 +#define BGRL7_BGR4 _bgrl7.bit._BGR4 +#define BGRL7_BGR5 _bgrl7.bit._BGR5 +#define BGRL7_BGR6 _bgrl7.bit._BGR6 +#define BGRL7_BGR7 _bgrl7.bit._BGR7 +__IO_EXTENDED BGRH7STR _bgrh7; +#define BGRH7 _bgrh7.byte +#define BGRH7_BGR8 _bgrh7.bit._BGR8 +#define BGRH7_BGR9 _bgrh7.bit._BGR9 +#define BGRH7_BGR10 _bgrh7.bit._BGR10 +#define BGRH7_BGR11 _bgrh7.bit._BGR11 +#define BGRH7_BGR12 _bgrh7.bit._BGR12 +#define BGRH7_BGR13 _bgrh7.bit._BGR13 +#define BGRH7_BGR14 _bgrh7.bit._BGR14 +#define BGRH7_BGR15 _bgrh7.bit._BGR15 +__IO_EXTENDED ESIR7STR _esir7; +#define ESIR7 _esir7.byte +#define ESIR7_AICD _esir7.bit._AICD +#define ESIR7_RBI _esir7.bit._RBI +#define ESIR7_RDRF _esir7.bit._RDRF +#define ESIR7_TDRE _esir7.bit._TDRE +__IO_EXTENDED SMR8STR _smr8; +#define SMR8 _smr8.byte +#define SMR8_SOE _smr8.bit._SOE +#define SMR8_SCKE _smr8.bit._SCKE +#define SMR8_UPCL _smr8.bit._UPCL +#define SMR8_REST _smr8.bit._REST +#define SMR8_EXT _smr8.bit._EXT +#define SMR8_OTO _smr8.bit._OTO +#define SMR8_MD0 _smr8.bit._MD0 +#define SMR8_MD1 _smr8.bit._MD1 +#define SMR8_MD _smr8.bitc._MD +__IO_EXTENDED SCR8STR _scr8; +#define SCR8 _scr8.byte +#define SCR8_TXE _scr8.bit._TXE +#define SCR8_RXE _scr8.bit._RXE +#define SCR8_CRE _scr8.bit._CRE +#define SCR8_AD _scr8.bit._AD +#define SCR8_CL _scr8.bit._CL +#define SCR8_SBL _scr8.bit._SBL +#define SCR8_P _scr8.bit._P +#define SCR8_PEN _scr8.bit._PEN +__IO_EXTENDED IO_BYTE _tdr8; +#define TDR8 _tdr8 +__IO_EXTENDED IO_BYTE _rdr8; +#define RDR8 _rdr8 +__IO_EXTENDED SSR8STR _ssr8; +#define SSR8 _ssr8.byte +#define SSR8_TIE _ssr8.bit._TIE +#define SSR8_RIE _ssr8.bit._RIE +#define SSR8_BDS _ssr8.bit._BDS +#define SSR8_TDRE _ssr8.bit._TDRE +#define SSR8_RDRF _ssr8.bit._RDRF +#define SSR8_FRE _ssr8.bit._FRE +#define SSR8_ORE _ssr8.bit._ORE +#define SSR8_PE _ssr8.bit._PE +__IO_EXTENDED ECCR8STR _eccr8; +#define ECCR8 _eccr8.byte +#define ECCR8_TBI _eccr8.bit._TBI +#define ECCR8_RBI _eccr8.bit._RBI +#define ECCR8_BIE _eccr8.bit._BIE +#define ECCR8_SSM _eccr8.bit._SSM +#define ECCR8_SCDE _eccr8.bit._SCDE +#define ECCR8_MS _eccr8.bit._MS +#define ECCR8_LBR _eccr8.bit._LBR +#define ECCR8_INV _eccr8.bit._INV +__IO_EXTENDED ESCR8STR _escr8; +#define ESCR8 _escr8.byte +#define ESCR8_SCES _escr8.bit._SCES +#define ESCR8_CCO _escr8.bit._CCO +#define ESCR8_SIOP _escr8.bit._SIOP +#define ESCR8_SOPE _escr8.bit._SOPE +#define ESCR8_LBL0 _escr8.bit._LBL0 +#define ESCR8_LBL1 _escr8.bit._LBL1 +#define ESCR8_LBD _escr8.bit._LBD +#define ESCR8_LBIE _escr8.bit._LBIE +#define ESCR8_LBL _escr8.bitc._LBL +__IO_EXTENDED BGR8STR _bgr8; +#define BGR8 _bgr8.word +#define BGR8_BGR0 _bgr8.bit._BGR0 +#define BGR8_BGR1 _bgr8.bit._BGR1 +#define BGR8_BGR2 _bgr8.bit._BGR2 +#define BGR8_BGR3 _bgr8.bit._BGR3 +#define BGR8_BGR4 _bgr8.bit._BGR4 +#define BGR8_BGR5 _bgr8.bit._BGR5 +#define BGR8_BGR6 _bgr8.bit._BGR6 +#define BGR8_BGR7 _bgr8.bit._BGR7 +#define BGR8_BGR8 _bgr8.bit._BGR8 +#define BGR8_BGR9 _bgr8.bit._BGR9 +#define BGR8_BGR10 _bgr8.bit._BGR10 +#define BGR8_BGR11 _bgr8.bit._BGR11 +#define BGR8_BGR12 _bgr8.bit._BGR12 +#define BGR8_BGR13 _bgr8.bit._BGR13 +#define BGR8_BGR14 _bgr8.bit._BGR14 +#define BGR8_BGR15 _bgr8.bit._BGR15 +#define BGR8_BGR _bgr8.bitc._BGR +__IO_EXTENDED BGRL8STR _bgrl8; +#define BGRL8 _bgrl8.byte +#define BGRL8_BGR0 _bgrl8.bit._BGR0 +#define BGRL8_BGR1 _bgrl8.bit._BGR1 +#define BGRL8_BGR2 _bgrl8.bit._BGR2 +#define BGRL8_BGR3 _bgrl8.bit._BGR3 +#define BGRL8_BGR4 _bgrl8.bit._BGR4 +#define BGRL8_BGR5 _bgrl8.bit._BGR5 +#define BGRL8_BGR6 _bgrl8.bit._BGR6 +#define BGRL8_BGR7 _bgrl8.bit._BGR7 +__IO_EXTENDED BGRH8STR _bgrh8; +#define BGRH8 _bgrh8.byte +#define BGRH8_BGR8 _bgrh8.bit._BGR8 +#define BGRH8_BGR9 _bgrh8.bit._BGR9 +#define BGRH8_BGR10 _bgrh8.bit._BGR10 +#define BGRH8_BGR11 _bgrh8.bit._BGR11 +#define BGRH8_BGR12 _bgrh8.bit._BGR12 +#define BGRH8_BGR13 _bgrh8.bit._BGR13 +#define BGRH8_BGR14 _bgrh8.bit._BGR14 +#define BGRH8_BGR15 _bgrh8.bit._BGR15 +__IO_EXTENDED ESIR8STR _esir8; +#define ESIR8 _esir8.byte +#define ESIR8_AICD _esir8.bit._AICD +#define ESIR8_RBI _esir8.bit._RBI +#define ESIR8_RDRF _esir8.bit._RDRF +#define ESIR8_TDRE _esir8.bit._TDRE +__IO_EXTENDED SMR9STR _smr9; +#define SMR9 _smr9.byte +#define SMR9_SOE _smr9.bit._SOE +#define SMR9_SCKE _smr9.bit._SCKE +#define SMR9_UPCL _smr9.bit._UPCL +#define SMR9_REST _smr9.bit._REST +#define SMR9_EXT _smr9.bit._EXT +#define SMR9_OTO _smr9.bit._OTO +#define SMR9_MD0 _smr9.bit._MD0 +#define SMR9_MD1 _smr9.bit._MD1 +#define SMR9_MD _smr9.bitc._MD +__IO_EXTENDED SCR9STR _scr9; +#define SCR9 _scr9.byte +#define SCR9_TXE _scr9.bit._TXE +#define SCR9_RXE _scr9.bit._RXE +#define SCR9_CRE _scr9.bit._CRE +#define SCR9_AD _scr9.bit._AD +#define SCR9_CL _scr9.bit._CL +#define SCR9_SBL _scr9.bit._SBL +#define SCR9_P _scr9.bit._P +#define SCR9_PEN _scr9.bit._PEN +__IO_EXTENDED IO_BYTE _tdr9; +#define TDR9 _tdr9 +__IO_EXTENDED IO_BYTE _rdr9; +#define RDR9 _rdr9 +__IO_EXTENDED SSR9STR _ssr9; +#define SSR9 _ssr9.byte +#define SSR9_TIE _ssr9.bit._TIE +#define SSR9_RIE _ssr9.bit._RIE +#define SSR9_BDS _ssr9.bit._BDS +#define SSR9_TDRE _ssr9.bit._TDRE +#define SSR9_RDRF _ssr9.bit._RDRF +#define SSR9_FRE _ssr9.bit._FRE +#define SSR9_ORE _ssr9.bit._ORE +#define SSR9_PE _ssr9.bit._PE +__IO_EXTENDED ECCR9STR _eccr9; +#define ECCR9 _eccr9.byte +#define ECCR9_TBI _eccr9.bit._TBI +#define ECCR9_RBI _eccr9.bit._RBI +#define ECCR9_BIE _eccr9.bit._BIE +#define ECCR9_SSM _eccr9.bit._SSM +#define ECCR9_SCDE _eccr9.bit._SCDE +#define ECCR9_MS _eccr9.bit._MS +#define ECCR9_LBR _eccr9.bit._LBR +#define ECCR9_INV _eccr9.bit._INV +__IO_EXTENDED ESCR9STR _escr9; +#define ESCR9 _escr9.byte +#define ESCR9_SCES _escr9.bit._SCES +#define ESCR9_CCO _escr9.bit._CCO +#define ESCR9_SIOP _escr9.bit._SIOP +#define ESCR9_SOPE _escr9.bit._SOPE +#define ESCR9_LBL0 _escr9.bit._LBL0 +#define ESCR9_LBL1 _escr9.bit._LBL1 +#define ESCR9_LBD _escr9.bit._LBD +#define ESCR9_LBIE _escr9.bit._LBIE +#define ESCR9_LBL _escr9.bitc._LBL +__IO_EXTENDED BGR9STR _bgr9; +#define BGR9 _bgr9.word +#define BGR9_BGR0 _bgr9.bit._BGR0 +#define BGR9_BGR1 _bgr9.bit._BGR1 +#define BGR9_BGR2 _bgr9.bit._BGR2 +#define BGR9_BGR3 _bgr9.bit._BGR3 +#define BGR9_BGR4 _bgr9.bit._BGR4 +#define BGR9_BGR5 _bgr9.bit._BGR5 +#define BGR9_BGR6 _bgr9.bit._BGR6 +#define BGR9_BGR7 _bgr9.bit._BGR7 +#define BGR9_BGR8 _bgr9.bit._BGR8 +#define BGR9_BGR9 _bgr9.bit._BGR9 +#define BGR9_BGR10 _bgr9.bit._BGR10 +#define BGR9_BGR11 _bgr9.bit._BGR11 +#define BGR9_BGR12 _bgr9.bit._BGR12 +#define BGR9_BGR13 _bgr9.bit._BGR13 +#define BGR9_BGR14 _bgr9.bit._BGR14 +#define BGR9_BGR15 _bgr9.bit._BGR15 +#define BGR9_BGR _bgr9.bitc._BGR +__IO_EXTENDED BGRL9STR _bgrl9; +#define BGRL9 _bgrl9.byte +#define BGRL9_BGR0 _bgrl9.bit._BGR0 +#define BGRL9_BGR1 _bgrl9.bit._BGR1 +#define BGRL9_BGR2 _bgrl9.bit._BGR2 +#define BGRL9_BGR3 _bgrl9.bit._BGR3 +#define BGRL9_BGR4 _bgrl9.bit._BGR4 +#define BGRL9_BGR5 _bgrl9.bit._BGR5 +#define BGRL9_BGR6 _bgrl9.bit._BGR6 +#define BGRL9_BGR7 _bgrl9.bit._BGR7 +__IO_EXTENDED BGRH9STR _bgrh9; +#define BGRH9 _bgrh9.byte +#define BGRH9_BGR8 _bgrh9.bit._BGR8 +#define BGRH9_BGR9 _bgrh9.bit._BGR9 +#define BGRH9_BGR10 _bgrh9.bit._BGR10 +#define BGRH9_BGR11 _bgrh9.bit._BGR11 +#define BGRH9_BGR12 _bgrh9.bit._BGR12 +#define BGRH9_BGR13 _bgrh9.bit._BGR13 +#define BGRH9_BGR14 _bgrh9.bit._BGR14 +#define BGRH9_BGR15 _bgrh9.bit._BGR15 +__IO_EXTENDED ESIR9STR _esir9; +#define ESIR9 _esir9.byte +#define ESIR9_AICD _esir9.bit._AICD +#define ESIR9_RBI _esir9.bit._RBI +#define ESIR9_RDRF _esir9.bit._RDRF +#define ESIR9_TDRE _esir9.bit._TDRE +__IO_EXTENDED ACSR0STR _acsr0; +#define ACSR0 _acsr0.byte +#define ACSR0_PD _acsr0.bit._PD +#define ACSR0_IEN _acsr0.bit._IEN +#define ACSR0_IRQ _acsr0.bit._IRQ +#define ACSR0_OUT1 _acsr0.bit._OUT1 +#define ACSR0_OUT2 _acsr0.bit._OUT2 +#define ACSR0_UVEN _acsr0.bit._UVEN +#define ACSR0_OVEN _acsr0.bit._OVEN +#define ACSR0_CMD _acsr0.bit._CMD +__IO_EXTENDED AECSR0STR _aecsr0; +#define AECSR0 _aecsr0.byte +#define AECSR0_INTREF _aecsr0.bit._INTREF +#define AECSR0_ACE _aecsr0.bit._ACE +__IO_EXTENDED ACSR1STR _acsr1; +#define ACSR1 _acsr1.byte +#define ACSR1_PD _acsr1.bit._PD +#define ACSR1_IEN _acsr1.bit._IEN +#define ACSR1_IRQ _acsr1.bit._IRQ +#define ACSR1_OUT1 _acsr1.bit._OUT1 +#define ACSR1_OUT2 _acsr1.bit._OUT2 +#define ACSR1_UVEN _acsr1.bit._UVEN +#define ACSR1_OVEN _acsr1.bit._OVEN +#define ACSR1_CMD _acsr1.bit._CMD +__IO_EXTENDED AECSR1STR _aecsr1; +#define AECSR1 _aecsr1.byte +#define AECSR1_INTREF _aecsr1.bit._INTREF +#define AECSR1_ACE _aecsr1.bit._ACE +__IO_EXTENDED PTMR6STR _ptmr6; +#define PTMR6 _ptmr6.word +#define PTMR6_D0 _ptmr6.bit._D0 +#define PTMR6_D1 _ptmr6.bit._D1 +#define PTMR6_D2 _ptmr6.bit._D2 +#define PTMR6_D3 _ptmr6.bit._D3 +#define PTMR6_D4 _ptmr6.bit._D4 +#define PTMR6_D5 _ptmr6.bit._D5 +#define PTMR6_D6 _ptmr6.bit._D6 +#define PTMR6_D7 _ptmr6.bit._D7 +#define PTMR6_D8 _ptmr6.bit._D8 +#define PTMR6_D9 _ptmr6.bit._D9 +#define PTMR6_D10 _ptmr6.bit._D10 +#define PTMR6_D11 _ptmr6.bit._D11 +#define PTMR6_D12 _ptmr6.bit._D12 +#define PTMR6_D13 _ptmr6.bit._D13 +#define PTMR6_D14 _ptmr6.bit._D14 +#define PTMR6_D15 _ptmr6.bit._D15 +#define PTMR6_D _ptmr6.bitc._D +__IO_EXTENDED PCSR6STR _pcsr6; +#define PCSR6 _pcsr6.word +#define PCSR6_D0 _pcsr6.bit._D0 +#define PCSR6_D1 _pcsr6.bit._D1 +#define PCSR6_D2 _pcsr6.bit._D2 +#define PCSR6_D3 _pcsr6.bit._D3 +#define PCSR6_D4 _pcsr6.bit._D4 +#define PCSR6_D5 _pcsr6.bit._D5 +#define PCSR6_D6 _pcsr6.bit._D6 +#define PCSR6_D7 _pcsr6.bit._D7 +#define PCSR6_D8 _pcsr6.bit._D8 +#define PCSR6_D9 _pcsr6.bit._D9 +#define PCSR6_D10 _pcsr6.bit._D10 +#define PCSR6_D11 _pcsr6.bit._D11 +#define PCSR6_D12 _pcsr6.bit._D12 +#define PCSR6_D13 _pcsr6.bit._D13 +#define PCSR6_D14 _pcsr6.bit._D14 +#define PCSR6_D15 _pcsr6.bit._D15 +#define PCSR6_D _pcsr6.bitc._D +__IO_EXTENDED PDUT6STR _pdut6; +#define PDUT6 _pdut6.word +#define PDUT6_D0 _pdut6.bit._D0 +#define PDUT6_D1 _pdut6.bit._D1 +#define PDUT6_D2 _pdut6.bit._D2 +#define PDUT6_D3 _pdut6.bit._D3 +#define PDUT6_D4 _pdut6.bit._D4 +#define PDUT6_D5 _pdut6.bit._D5 +#define PDUT6_D6 _pdut6.bit._D6 +#define PDUT6_D7 _pdut6.bit._D7 +#define PDUT6_D8 _pdut6.bit._D8 +#define PDUT6_D9 _pdut6.bit._D9 +#define PDUT6_D10 _pdut6.bit._D10 +#define PDUT6_D11 _pdut6.bit._D11 +#define PDUT6_D12 _pdut6.bit._D12 +#define PDUT6_D13 _pdut6.bit._D13 +#define PDUT6_D14 _pdut6.bit._D14 +#define PDUT6_D15 _pdut6.bit._D15 +#define PDUT6_D _pdut6.bitc._D +__IO_EXTENDED PCN6STR _pcn6; +#define PCN6 _pcn6.word +#define PCN6_OSEL _pcn6.bit._OSEL +#define PCN6_OE _pcn6.bit._OE +#define PCN6_IRS0 _pcn6.bit._IRS0 +#define PCN6_IRS1 _pcn6.bit._IRS1 +#define PCN6_IRQF _pcn6.bit._IRQF +#define PCN6_IREN _pcn6.bit._IREN +#define PCN6_EGS0 _pcn6.bit._EGS0 +#define PCN6_EGS1 _pcn6.bit._EGS1 +#define PCN6_PGMS _pcn6.bit._PGMS +#define PCN6_CKS0 _pcn6.bit._CKS0 +#define PCN6_CKS1 _pcn6.bit._CKS1 +#define PCN6_RTRG _pcn6.bit._RTRG +#define PCN6_MDSE _pcn6.bit._MDSE +#define PCN6_STGR _pcn6.bit._STGR +#define PCN6_CNTE _pcn6.bit._CNTE +#define PCN6_IRS _pcn6.bitc._IRS +#define PCN6_EGS _pcn6.bitc._EGS +#define PCN6_CKS _pcn6.bitc._CKS +__IO_EXTENDED PCNL6STR _pcnl6; +#define PCNL6 _pcnl6.byte +#define PCNL6_OSEL _pcnl6.bit._OSEL +#define PCNL6_OE _pcnl6.bit._OE +#define PCNL6_IRS0 _pcnl6.bit._IRS0 +#define PCNL6_IRS1 _pcnl6.bit._IRS1 +#define PCNL6_IRQF _pcnl6.bit._IRQF +#define PCNL6_IREN _pcnl6.bit._IREN +#define PCNL6_EGS0 _pcnl6.bit._EGS0 +#define PCNL6_EGS1 _pcnl6.bit._EGS1 +#define PCNL6_IRS _pcnl6.bitc._IRS +#define PCNL6_EGS _pcnl6.bitc._EGS +__IO_EXTENDED PCNH6STR _pcnh6; +#define PCNH6 _pcnh6.byte +#define PCNH6_PGMS _pcnh6.bit._PGMS +#define PCNH6_CKS0 _pcnh6.bit._CKS0 +#define PCNH6_CKS1 _pcnh6.bit._CKS1 +#define PCNH6_RTRG _pcnh6.bit._RTRG +#define PCNH6_MDSE _pcnh6.bit._MDSE +#define PCNH6_STGR _pcnh6.bit._STGR +#define PCNH6_CNTE _pcnh6.bit._CNTE +#define PCNH6_CKS _pcnh6.bitc._CKS +__IO_EXTENDED PTMR7STR _ptmr7; +#define PTMR7 _ptmr7.word +#define PTMR7_D0 _ptmr7.bit._D0 +#define PTMR7_D1 _ptmr7.bit._D1 +#define PTMR7_D2 _ptmr7.bit._D2 +#define PTMR7_D3 _ptmr7.bit._D3 +#define PTMR7_D4 _ptmr7.bit._D4 +#define PTMR7_D5 _ptmr7.bit._D5 +#define PTMR7_D6 _ptmr7.bit._D6 +#define PTMR7_D7 _ptmr7.bit._D7 +#define PTMR7_D8 _ptmr7.bit._D8 +#define PTMR7_D9 _ptmr7.bit._D9 +#define PTMR7_D10 _ptmr7.bit._D10 +#define PTMR7_D11 _ptmr7.bit._D11 +#define PTMR7_D12 _ptmr7.bit._D12 +#define PTMR7_D13 _ptmr7.bit._D13 +#define PTMR7_D14 _ptmr7.bit._D14 +#define PTMR7_D15 _ptmr7.bit._D15 +#define PTMR7_D _ptmr7.bitc._D +__IO_EXTENDED PCSR7STR _pcsr7; +#define PCSR7 _pcsr7.word +#define PCSR7_D0 _pcsr7.bit._D0 +#define PCSR7_D1 _pcsr7.bit._D1 +#define PCSR7_D2 _pcsr7.bit._D2 +#define PCSR7_D3 _pcsr7.bit._D3 +#define PCSR7_D4 _pcsr7.bit._D4 +#define PCSR7_D5 _pcsr7.bit._D5 +#define PCSR7_D6 _pcsr7.bit._D6 +#define PCSR7_D7 _pcsr7.bit._D7 +#define PCSR7_D8 _pcsr7.bit._D8 +#define PCSR7_D9 _pcsr7.bit._D9 +#define PCSR7_D10 _pcsr7.bit._D10 +#define PCSR7_D11 _pcsr7.bit._D11 +#define PCSR7_D12 _pcsr7.bit._D12 +#define PCSR7_D13 _pcsr7.bit._D13 +#define PCSR7_D14 _pcsr7.bit._D14 +#define PCSR7_D15 _pcsr7.bit._D15 +#define PCSR7_D _pcsr7.bitc._D +__IO_EXTENDED PDUT7STR _pdut7; +#define PDUT7 _pdut7.word +#define PDUT7_D0 _pdut7.bit._D0 +#define PDUT7_D1 _pdut7.bit._D1 +#define PDUT7_D2 _pdut7.bit._D2 +#define PDUT7_D3 _pdut7.bit._D3 +#define PDUT7_D4 _pdut7.bit._D4 +#define PDUT7_D5 _pdut7.bit._D5 +#define PDUT7_D6 _pdut7.bit._D6 +#define PDUT7_D7 _pdut7.bit._D7 +#define PDUT7_D8 _pdut7.bit._D8 +#define PDUT7_D9 _pdut7.bit._D9 +#define PDUT7_D10 _pdut7.bit._D10 +#define PDUT7_D11 _pdut7.bit._D11 +#define PDUT7_D12 _pdut7.bit._D12 +#define PDUT7_D13 _pdut7.bit._D13 +#define PDUT7_D14 _pdut7.bit._D14 +#define PDUT7_D15 _pdut7.bit._D15 +#define PDUT7_D _pdut7.bitc._D +__IO_EXTENDED PCN7STR _pcn7; +#define PCN7 _pcn7.word +#define PCN7_OSEL _pcn7.bit._OSEL +#define PCN7_OE _pcn7.bit._OE +#define PCN7_IRS0 _pcn7.bit._IRS0 +#define PCN7_IRS1 _pcn7.bit._IRS1 +#define PCN7_IRQF _pcn7.bit._IRQF +#define PCN7_IREN _pcn7.bit._IREN +#define PCN7_EGS0 _pcn7.bit._EGS0 +#define PCN7_EGS1 _pcn7.bit._EGS1 +#define PCN7_PGMS _pcn7.bit._PGMS +#define PCN7_CKS0 _pcn7.bit._CKS0 +#define PCN7_CKS1 _pcn7.bit._CKS1 +#define PCN7_RTRG _pcn7.bit._RTRG +#define PCN7_MDSE _pcn7.bit._MDSE +#define PCN7_STGR _pcn7.bit._STGR +#define PCN7_CNTE _pcn7.bit._CNTE +#define PCN7_IRS _pcn7.bitc._IRS +#define PCN7_EGS _pcn7.bitc._EGS +#define PCN7_CKS _pcn7.bitc._CKS +__IO_EXTENDED PCNL7STR _pcnl7; +#define PCNL7 _pcnl7.byte +#define PCNL7_OSEL _pcnl7.bit._OSEL +#define PCNL7_OE _pcnl7.bit._OE +#define PCNL7_IRS0 _pcnl7.bit._IRS0 +#define PCNL7_IRS1 _pcnl7.bit._IRS1 +#define PCNL7_IRQF _pcnl7.bit._IRQF +#define PCNL7_IREN _pcnl7.bit._IREN +#define PCNL7_EGS0 _pcnl7.bit._EGS0 +#define PCNL7_EGS1 _pcnl7.bit._EGS1 +#define PCNL7_IRS _pcnl7.bitc._IRS +#define PCNL7_EGS _pcnl7.bitc._EGS +__IO_EXTENDED PCNH7STR _pcnh7; +#define PCNH7 _pcnh7.byte +#define PCNH7_PGMS _pcnh7.bit._PGMS +#define PCNH7_CKS0 _pcnh7.bit._CKS0 +#define PCNH7_CKS1 _pcnh7.bit._CKS1 +#define PCNH7_RTRG _pcnh7.bit._RTRG +#define PCNH7_MDSE _pcnh7.bit._MDSE +#define PCNH7_STGR _pcnh7.bit._STGR +#define PCNH7_CNTE _pcnh7.bit._CNTE +#define PCNH7_CKS _pcnh7.bitc._CKS +__IO_EXTENDED GCN12STR _gcn12; +#define GCN12 _gcn12.word +#define GCN12_TSEL00 _gcn12.bit._TSEL00 +#define GCN12_TSEL01 _gcn12.bit._TSEL01 +#define GCN12_TSEL02 _gcn12.bit._TSEL02 +#define GCN12_TSEL03 _gcn12.bit._TSEL03 +#define GCN12_TSEL10 _gcn12.bit._TSEL10 +#define GCN12_TSEL11 _gcn12.bit._TSEL11 +#define GCN12_TSEL12 _gcn12.bit._TSEL12 +#define GCN12_TSEL13 _gcn12.bit._TSEL13 +#define GCN12_TSEL20 _gcn12.bit._TSEL20 +#define GCN12_TSEL21 _gcn12.bit._TSEL21 +#define GCN12_TSEL22 _gcn12.bit._TSEL22 +#define GCN12_TSEL23 _gcn12.bit._TSEL23 +#define GCN12_TSEL30 _gcn12.bit._TSEL30 +#define GCN12_TSEL31 _gcn12.bit._TSEL31 +#define GCN12_TSEL32 _gcn12.bit._TSEL32 +#define GCN12_TSEL33 _gcn12.bit._TSEL33 +#define GCN12_TSEL0 _gcn12.bitc._TSEL0 +#define GCN12_TSEL1 _gcn12.bitc._TSEL1 +#define GCN12_TSEL2 _gcn12.bitc._TSEL2 +#define GCN12_TSEL3 _gcn12.bitc._TSEL3 +__IO_EXTENDED GCN1L2STR _gcn1l2; +#define GCN1L2 _gcn1l2.byte +#define GCN1L2_TSEL00 _gcn1l2.bit._TSEL00 +#define GCN1L2_TSEL01 _gcn1l2.bit._TSEL01 +#define GCN1L2_TSEL02 _gcn1l2.bit._TSEL02 +#define GCN1L2_TSEL03 _gcn1l2.bit._TSEL03 +#define GCN1L2_TSEL10 _gcn1l2.bit._TSEL10 +#define GCN1L2_TSEL11 _gcn1l2.bit._TSEL11 +#define GCN1L2_TSEL12 _gcn1l2.bit._TSEL12 +#define GCN1L2_TSEL13 _gcn1l2.bit._TSEL13 +#define GCN1L2_TSEL0 _gcn1l2.bitc._TSEL0 +#define GCN1L2_TSEL1 _gcn1l2.bitc._TSEL1 +__IO_EXTENDED GCN1H2STR _gcn1h2; +#define GCN1H2 _gcn1h2.byte +#define GCN1H2_TSEL20 _gcn1h2.bit._TSEL20 +#define GCN1H2_TSEL21 _gcn1h2.bit._TSEL21 +#define GCN1H2_TSEL22 _gcn1h2.bit._TSEL22 +#define GCN1H2_TSEL23 _gcn1h2.bit._TSEL23 +#define GCN1H2_TSEL30 _gcn1h2.bit._TSEL30 +#define GCN1H2_TSEL31 _gcn1h2.bit._TSEL31 +#define GCN1H2_TSEL32 _gcn1h2.bit._TSEL32 +#define GCN1H2_TSEL33 _gcn1h2.bit._TSEL33 +#define GCN1H2_TSEL2 _gcn1h2.bitc._TSEL2 +#define GCN1H2_TSEL3 _gcn1h2.bitc._TSEL3 +__IO_EXTENDED GCN22STR _gcn22; +#define GCN22 _gcn22.word +#define GCN22_EN0 _gcn22.bit._EN0 +#define GCN22_EN1 _gcn22.bit._EN1 +#define GCN22_EN2 _gcn22.bit._EN2 +#define GCN22_EN3 _gcn22.bit._EN3 +#define GCN22_CKSEL0 _gcn22.bit._CKSEL0 +#define GCN22_CKSEL1 _gcn22.bit._CKSEL1 +#define GCN22_CKSEL2 _gcn22.bit._CKSEL2 +#define GCN22_CKSEL3 _gcn22.bit._CKSEL3 +#define GCN22_EN _gcn22.bitc._EN +#define GCN22_CKSEL _gcn22.bitc._CKSEL +__IO_EXTENDED GCN2L2STR _gcn2l2; +#define GCN2L2 _gcn2l2.byte +#define GCN2L2_EN0 _gcn2l2.bit._EN0 +#define GCN2L2_EN1 _gcn2l2.bit._EN1 +#define GCN2L2_EN2 _gcn2l2.bit._EN2 +#define GCN2L2_EN3 _gcn2l2.bit._EN3 +#define GCN2L2_EN _gcn2l2.bitc._EN +__IO_EXTENDED GCN2H2STR _gcn2h2; +#define GCN2H2 _gcn2h2.byte +#define GCN2H2_CKSEL0 _gcn2h2.bit._CKSEL0 +#define GCN2H2_CKSEL1 _gcn2h2.bit._CKSEL1 +#define GCN2H2_CKSEL2 _gcn2h2.bit._CKSEL2 +#define GCN2H2_CKSEL3 _gcn2h2.bit._CKSEL3 +#define GCN2H2_CKSEL _gcn2h2.bitc._CKSEL +__IO_EXTENDED PTMR8STR _ptmr8; +#define PTMR8 _ptmr8.word +#define PTMR8_D0 _ptmr8.bit._D0 +#define PTMR8_D1 _ptmr8.bit._D1 +#define PTMR8_D2 _ptmr8.bit._D2 +#define PTMR8_D3 _ptmr8.bit._D3 +#define PTMR8_D4 _ptmr8.bit._D4 +#define PTMR8_D5 _ptmr8.bit._D5 +#define PTMR8_D6 _ptmr8.bit._D6 +#define PTMR8_D7 _ptmr8.bit._D7 +#define PTMR8_D8 _ptmr8.bit._D8 +#define PTMR8_D9 _ptmr8.bit._D9 +#define PTMR8_D10 _ptmr8.bit._D10 +#define PTMR8_D11 _ptmr8.bit._D11 +#define PTMR8_D12 _ptmr8.bit._D12 +#define PTMR8_D13 _ptmr8.bit._D13 +#define PTMR8_D14 _ptmr8.bit._D14 +#define PTMR8_D15 _ptmr8.bit._D15 +#define PTMR8_D _ptmr8.bitc._D +__IO_EXTENDED PCSR8STR _pcsr8; +#define PCSR8 _pcsr8.word +#define PCSR8_D0 _pcsr8.bit._D0 +#define PCSR8_D1 _pcsr8.bit._D1 +#define PCSR8_D2 _pcsr8.bit._D2 +#define PCSR8_D3 _pcsr8.bit._D3 +#define PCSR8_D4 _pcsr8.bit._D4 +#define PCSR8_D5 _pcsr8.bit._D5 +#define PCSR8_D6 _pcsr8.bit._D6 +#define PCSR8_D7 _pcsr8.bit._D7 +#define PCSR8_D8 _pcsr8.bit._D8 +#define PCSR8_D9 _pcsr8.bit._D9 +#define PCSR8_D10 _pcsr8.bit._D10 +#define PCSR8_D11 _pcsr8.bit._D11 +#define PCSR8_D12 _pcsr8.bit._D12 +#define PCSR8_D13 _pcsr8.bit._D13 +#define PCSR8_D14 _pcsr8.bit._D14 +#define PCSR8_D15 _pcsr8.bit._D15 +#define PCSR8_D _pcsr8.bitc._D +__IO_EXTENDED PDUT8STR _pdut8; +#define PDUT8 _pdut8.word +#define PDUT8_D0 _pdut8.bit._D0 +#define PDUT8_D1 _pdut8.bit._D1 +#define PDUT8_D2 _pdut8.bit._D2 +#define PDUT8_D3 _pdut8.bit._D3 +#define PDUT8_D4 _pdut8.bit._D4 +#define PDUT8_D5 _pdut8.bit._D5 +#define PDUT8_D6 _pdut8.bit._D6 +#define PDUT8_D7 _pdut8.bit._D7 +#define PDUT8_D8 _pdut8.bit._D8 +#define PDUT8_D9 _pdut8.bit._D9 +#define PDUT8_D10 _pdut8.bit._D10 +#define PDUT8_D11 _pdut8.bit._D11 +#define PDUT8_D12 _pdut8.bit._D12 +#define PDUT8_D13 _pdut8.bit._D13 +#define PDUT8_D14 _pdut8.bit._D14 +#define PDUT8_D15 _pdut8.bit._D15 +#define PDUT8_D _pdut8.bitc._D +__IO_EXTENDED PCN8STR _pcn8; +#define PCN8 _pcn8.word +#define PCN8_OSEL _pcn8.bit._OSEL +#define PCN8_OE _pcn8.bit._OE +#define PCN8_IRS0 _pcn8.bit._IRS0 +#define PCN8_IRS1 _pcn8.bit._IRS1 +#define PCN8_IRQF _pcn8.bit._IRQF +#define PCN8_IREN _pcn8.bit._IREN +#define PCN8_EGS0 _pcn8.bit._EGS0 +#define PCN8_EGS1 _pcn8.bit._EGS1 +#define PCN8_PGMS _pcn8.bit._PGMS +#define PCN8_CKS0 _pcn8.bit._CKS0 +#define PCN8_CKS1 _pcn8.bit._CKS1 +#define PCN8_RTRG _pcn8.bit._RTRG +#define PCN8_MDSE _pcn8.bit._MDSE +#define PCN8_STGR _pcn8.bit._STGR +#define PCN8_CNTE _pcn8.bit._CNTE +#define PCN8_IRS _pcn8.bitc._IRS +#define PCN8_EGS _pcn8.bitc._EGS +#define PCN8_CKS _pcn8.bitc._CKS +__IO_EXTENDED PCNL8STR _pcnl8; +#define PCNL8 _pcnl8.byte +#define PCNL8_OSEL _pcnl8.bit._OSEL +#define PCNL8_OE _pcnl8.bit._OE +#define PCNL8_IRS0 _pcnl8.bit._IRS0 +#define PCNL8_IRS1 _pcnl8.bit._IRS1 +#define PCNL8_IRQF _pcnl8.bit._IRQF +#define PCNL8_IREN _pcnl8.bit._IREN +#define PCNL8_EGS0 _pcnl8.bit._EGS0 +#define PCNL8_EGS1 _pcnl8.bit._EGS1 +#define PCNL8_IRS _pcnl8.bitc._IRS +#define PCNL8_EGS _pcnl8.bitc._EGS +__IO_EXTENDED PCNH8STR _pcnh8; +#define PCNH8 _pcnh8.byte +#define PCNH8_PGMS _pcnh8.bit._PGMS +#define PCNH8_CKS0 _pcnh8.bit._CKS0 +#define PCNH8_CKS1 _pcnh8.bit._CKS1 +#define PCNH8_RTRG _pcnh8.bit._RTRG +#define PCNH8_MDSE _pcnh8.bit._MDSE +#define PCNH8_STGR _pcnh8.bit._STGR +#define PCNH8_CNTE _pcnh8.bit._CNTE +#define PCNH8_CKS _pcnh8.bitc._CKS +__IO_EXTENDED PTMR9STR _ptmr9; +#define PTMR9 _ptmr9.word +#define PTMR9_D0 _ptmr9.bit._D0 +#define PTMR9_D1 _ptmr9.bit._D1 +#define PTMR9_D2 _ptmr9.bit._D2 +#define PTMR9_D3 _ptmr9.bit._D3 +#define PTMR9_D4 _ptmr9.bit._D4 +#define PTMR9_D5 _ptmr9.bit._D5 +#define PTMR9_D6 _ptmr9.bit._D6 +#define PTMR9_D7 _ptmr9.bit._D7 +#define PTMR9_D8 _ptmr9.bit._D8 +#define PTMR9_D9 _ptmr9.bit._D9 +#define PTMR9_D10 _ptmr9.bit._D10 +#define PTMR9_D11 _ptmr9.bit._D11 +#define PTMR9_D12 _ptmr9.bit._D12 +#define PTMR9_D13 _ptmr9.bit._D13 +#define PTMR9_D14 _ptmr9.bit._D14 +#define PTMR9_D15 _ptmr9.bit._D15 +#define PTMR9_D _ptmr9.bitc._D +__IO_EXTENDED PCSR9STR _pcsr9; +#define PCSR9 _pcsr9.word +#define PCSR9_D0 _pcsr9.bit._D0 +#define PCSR9_D1 _pcsr9.bit._D1 +#define PCSR9_D2 _pcsr9.bit._D2 +#define PCSR9_D3 _pcsr9.bit._D3 +#define PCSR9_D4 _pcsr9.bit._D4 +#define PCSR9_D5 _pcsr9.bit._D5 +#define PCSR9_D6 _pcsr9.bit._D6 +#define PCSR9_D7 _pcsr9.bit._D7 +#define PCSR9_D8 _pcsr9.bit._D8 +#define PCSR9_D9 _pcsr9.bit._D9 +#define PCSR9_D10 _pcsr9.bit._D10 +#define PCSR9_D11 _pcsr9.bit._D11 +#define PCSR9_D12 _pcsr9.bit._D12 +#define PCSR9_D13 _pcsr9.bit._D13 +#define PCSR9_D14 _pcsr9.bit._D14 +#define PCSR9_D15 _pcsr9.bit._D15 +#define PCSR9_D _pcsr9.bitc._D +__IO_EXTENDED PDUT9STR _pdut9; +#define PDUT9 _pdut9.word +#define PDUT9_D0 _pdut9.bit._D0 +#define PDUT9_D1 _pdut9.bit._D1 +#define PDUT9_D2 _pdut9.bit._D2 +#define PDUT9_D3 _pdut9.bit._D3 +#define PDUT9_D4 _pdut9.bit._D4 +#define PDUT9_D5 _pdut9.bit._D5 +#define PDUT9_D6 _pdut9.bit._D6 +#define PDUT9_D7 _pdut9.bit._D7 +#define PDUT9_D8 _pdut9.bit._D8 +#define PDUT9_D9 _pdut9.bit._D9 +#define PDUT9_D10 _pdut9.bit._D10 +#define PDUT9_D11 _pdut9.bit._D11 +#define PDUT9_D12 _pdut9.bit._D12 +#define PDUT9_D13 _pdut9.bit._D13 +#define PDUT9_D14 _pdut9.bit._D14 +#define PDUT9_D15 _pdut9.bit._D15 +#define PDUT9_D _pdut9.bitc._D +__IO_EXTENDED PCN9STR _pcn9; +#define PCN9 _pcn9.word +#define PCN9_OSEL _pcn9.bit._OSEL +#define PCN9_OE _pcn9.bit._OE +#define PCN9_IRS0 _pcn9.bit._IRS0 +#define PCN9_IRS1 _pcn9.bit._IRS1 +#define PCN9_IRQF _pcn9.bit._IRQF +#define PCN9_IREN _pcn9.bit._IREN +#define PCN9_EGS0 _pcn9.bit._EGS0 +#define PCN9_EGS1 _pcn9.bit._EGS1 +#define PCN9_PGMS _pcn9.bit._PGMS +#define PCN9_CKS0 _pcn9.bit._CKS0 +#define PCN9_CKS1 _pcn9.bit._CKS1 +#define PCN9_RTRG _pcn9.bit._RTRG +#define PCN9_MDSE _pcn9.bit._MDSE +#define PCN9_STGR _pcn9.bit._STGR +#define PCN9_CNTE _pcn9.bit._CNTE +#define PCN9_IRS _pcn9.bitc._IRS +#define PCN9_EGS _pcn9.bitc._EGS +#define PCN9_CKS _pcn9.bitc._CKS +__IO_EXTENDED PCNL9STR _pcnl9; +#define PCNL9 _pcnl9.byte +#define PCNL9_OSEL _pcnl9.bit._OSEL +#define PCNL9_OE _pcnl9.bit._OE +#define PCNL9_IRS0 _pcnl9.bit._IRS0 +#define PCNL9_IRS1 _pcnl9.bit._IRS1 +#define PCNL9_IRQF _pcnl9.bit._IRQF +#define PCNL9_IREN _pcnl9.bit._IREN +#define PCNL9_EGS0 _pcnl9.bit._EGS0 +#define PCNL9_EGS1 _pcnl9.bit._EGS1 +#define PCNL9_IRS _pcnl9.bitc._IRS +#define PCNL9_EGS _pcnl9.bitc._EGS +__IO_EXTENDED PCNH9STR _pcnh9; +#define PCNH9 _pcnh9.byte +#define PCNH9_PGMS _pcnh9.bit._PGMS +#define PCNH9_CKS0 _pcnh9.bit._CKS0 +#define PCNH9_CKS1 _pcnh9.bit._CKS1 +#define PCNH9_RTRG _pcnh9.bit._RTRG +#define PCNH9_MDSE _pcnh9.bit._MDSE +#define PCNH9_STGR _pcnh9.bit._STGR +#define PCNH9_CNTE _pcnh9.bit._CNTE +#define PCNH9_CKS _pcnh9.bitc._CKS +__IO_EXTENDED PTMR10STR _ptmr10; +#define PTMR10 _ptmr10.word +#define PTMR10_D0 _ptmr10.bit._D0 +#define PTMR10_D1 _ptmr10.bit._D1 +#define PTMR10_D2 _ptmr10.bit._D2 +#define PTMR10_D3 _ptmr10.bit._D3 +#define PTMR10_D4 _ptmr10.bit._D4 +#define PTMR10_D5 _ptmr10.bit._D5 +#define PTMR10_D6 _ptmr10.bit._D6 +#define PTMR10_D7 _ptmr10.bit._D7 +#define PTMR10_D8 _ptmr10.bit._D8 +#define PTMR10_D9 _ptmr10.bit._D9 +#define PTMR10_D10 _ptmr10.bit._D10 +#define PTMR10_D11 _ptmr10.bit._D11 +#define PTMR10_D12 _ptmr10.bit._D12 +#define PTMR10_D13 _ptmr10.bit._D13 +#define PTMR10_D14 _ptmr10.bit._D14 +#define PTMR10_D15 _ptmr10.bit._D15 +#define PTMR10_D _ptmr10.bitc._D +__IO_EXTENDED PCSR10STR _pcsr10; +#define PCSR10 _pcsr10.word +#define PCSR10_D0 _pcsr10.bit._D0 +#define PCSR10_D1 _pcsr10.bit._D1 +#define PCSR10_D2 _pcsr10.bit._D2 +#define PCSR10_D3 _pcsr10.bit._D3 +#define PCSR10_D4 _pcsr10.bit._D4 +#define PCSR10_D5 _pcsr10.bit._D5 +#define PCSR10_D6 _pcsr10.bit._D6 +#define PCSR10_D7 _pcsr10.bit._D7 +#define PCSR10_D8 _pcsr10.bit._D8 +#define PCSR10_D9 _pcsr10.bit._D9 +#define PCSR10_D10 _pcsr10.bit._D10 +#define PCSR10_D11 _pcsr10.bit._D11 +#define PCSR10_D12 _pcsr10.bit._D12 +#define PCSR10_D13 _pcsr10.bit._D13 +#define PCSR10_D14 _pcsr10.bit._D14 +#define PCSR10_D15 _pcsr10.bit._D15 +#define PCSR10_D _pcsr10.bitc._D +__IO_EXTENDED PDUT10STR _pdut10; +#define PDUT10 _pdut10.word +#define PDUT10_D0 _pdut10.bit._D0 +#define PDUT10_D1 _pdut10.bit._D1 +#define PDUT10_D2 _pdut10.bit._D2 +#define PDUT10_D3 _pdut10.bit._D3 +#define PDUT10_D4 _pdut10.bit._D4 +#define PDUT10_D5 _pdut10.bit._D5 +#define PDUT10_D6 _pdut10.bit._D6 +#define PDUT10_D7 _pdut10.bit._D7 +#define PDUT10_D8 _pdut10.bit._D8 +#define PDUT10_D9 _pdut10.bit._D9 +#define PDUT10_D10 _pdut10.bit._D10 +#define PDUT10_D11 _pdut10.bit._D11 +#define PDUT10_D12 _pdut10.bit._D12 +#define PDUT10_D13 _pdut10.bit._D13 +#define PDUT10_D14 _pdut10.bit._D14 +#define PDUT10_D15 _pdut10.bit._D15 +#define PDUT10_D _pdut10.bitc._D +__IO_EXTENDED PCN10STR _pcn10; +#define PCN10 _pcn10.word +#define PCN10_OSEL _pcn10.bit._OSEL +#define PCN10_OE _pcn10.bit._OE +#define PCN10_IRS0 _pcn10.bit._IRS0 +#define PCN10_IRS1 _pcn10.bit._IRS1 +#define PCN10_IRQF _pcn10.bit._IRQF +#define PCN10_IREN _pcn10.bit._IREN +#define PCN10_EGS0 _pcn10.bit._EGS0 +#define PCN10_EGS1 _pcn10.bit._EGS1 +#define PCN10_PGMS _pcn10.bit._PGMS +#define PCN10_CKS0 _pcn10.bit._CKS0 +#define PCN10_CKS1 _pcn10.bit._CKS1 +#define PCN10_RTRG _pcn10.bit._RTRG +#define PCN10_MDSE _pcn10.bit._MDSE +#define PCN10_STGR _pcn10.bit._STGR +#define PCN10_CNTE _pcn10.bit._CNTE +#define PCN10_IRS _pcn10.bitc._IRS +#define PCN10_EGS _pcn10.bitc._EGS +#define PCN10_CKS _pcn10.bitc._CKS +__IO_EXTENDED PCNL10STR _pcnl10; +#define PCNL10 _pcnl10.byte +#define PCNL10_OSEL _pcnl10.bit._OSEL +#define PCNL10_OE _pcnl10.bit._OE +#define PCNL10_IRS0 _pcnl10.bit._IRS0 +#define PCNL10_IRS1 _pcnl10.bit._IRS1 +#define PCNL10_IRQF _pcnl10.bit._IRQF +#define PCNL10_IREN _pcnl10.bit._IREN +#define PCNL10_EGS0 _pcnl10.bit._EGS0 +#define PCNL10_EGS1 _pcnl10.bit._EGS1 +#define PCNL10_IRS _pcnl10.bitc._IRS +#define PCNL10_EGS _pcnl10.bitc._EGS +__IO_EXTENDED PCNH10STR _pcnh10; +#define PCNH10 _pcnh10.byte +#define PCNH10_PGMS _pcnh10.bit._PGMS +#define PCNH10_CKS0 _pcnh10.bit._CKS0 +#define PCNH10_CKS1 _pcnh10.bit._CKS1 +#define PCNH10_RTRG _pcnh10.bit._RTRG +#define PCNH10_MDSE _pcnh10.bit._MDSE +#define PCNH10_STGR _pcnh10.bit._STGR +#define PCNH10_CNTE _pcnh10.bit._CNTE +#define PCNH10_CKS _pcnh10.bitc._CKS +__IO_EXTENDED PTMR11STR _ptmr11; +#define PTMR11 _ptmr11.word +#define PTMR11_D0 _ptmr11.bit._D0 +#define PTMR11_D1 _ptmr11.bit._D1 +#define PTMR11_D2 _ptmr11.bit._D2 +#define PTMR11_D3 _ptmr11.bit._D3 +#define PTMR11_D4 _ptmr11.bit._D4 +#define PTMR11_D5 _ptmr11.bit._D5 +#define PTMR11_D6 _ptmr11.bit._D6 +#define PTMR11_D7 _ptmr11.bit._D7 +#define PTMR11_D8 _ptmr11.bit._D8 +#define PTMR11_D9 _ptmr11.bit._D9 +#define PTMR11_D10 _ptmr11.bit._D10 +#define PTMR11_D11 _ptmr11.bit._D11 +#define PTMR11_D12 _ptmr11.bit._D12 +#define PTMR11_D13 _ptmr11.bit._D13 +#define PTMR11_D14 _ptmr11.bit._D14 +#define PTMR11_D15 _ptmr11.bit._D15 +#define PTMR11_D _ptmr11.bitc._D +__IO_EXTENDED PCSR11STR _pcsr11; +#define PCSR11 _pcsr11.word +#define PCSR11_D0 _pcsr11.bit._D0 +#define PCSR11_D1 _pcsr11.bit._D1 +#define PCSR11_D2 _pcsr11.bit._D2 +#define PCSR11_D3 _pcsr11.bit._D3 +#define PCSR11_D4 _pcsr11.bit._D4 +#define PCSR11_D5 _pcsr11.bit._D5 +#define PCSR11_D6 _pcsr11.bit._D6 +#define PCSR11_D7 _pcsr11.bit._D7 +#define PCSR11_D8 _pcsr11.bit._D8 +#define PCSR11_D9 _pcsr11.bit._D9 +#define PCSR11_D10 _pcsr11.bit._D10 +#define PCSR11_D11 _pcsr11.bit._D11 +#define PCSR11_D12 _pcsr11.bit._D12 +#define PCSR11_D13 _pcsr11.bit._D13 +#define PCSR11_D14 _pcsr11.bit._D14 +#define PCSR11_D15 _pcsr11.bit._D15 +#define PCSR11_D _pcsr11.bitc._D +__IO_EXTENDED PDUT11STR _pdut11; +#define PDUT11 _pdut11.word +#define PDUT11_D0 _pdut11.bit._D0 +#define PDUT11_D1 _pdut11.bit._D1 +#define PDUT11_D2 _pdut11.bit._D2 +#define PDUT11_D3 _pdut11.bit._D3 +#define PDUT11_D4 _pdut11.bit._D4 +#define PDUT11_D5 _pdut11.bit._D5 +#define PDUT11_D6 _pdut11.bit._D6 +#define PDUT11_D7 _pdut11.bit._D7 +#define PDUT11_D8 _pdut11.bit._D8 +#define PDUT11_D9 _pdut11.bit._D9 +#define PDUT11_D10 _pdut11.bit._D10 +#define PDUT11_D11 _pdut11.bit._D11 +#define PDUT11_D12 _pdut11.bit._D12 +#define PDUT11_D13 _pdut11.bit._D13 +#define PDUT11_D14 _pdut11.bit._D14 +#define PDUT11_D15 _pdut11.bit._D15 +#define PDUT11_D _pdut11.bitc._D +__IO_EXTENDED PCN11STR _pcn11; +#define PCN11 _pcn11.word +#define PCN11_OSEL _pcn11.bit._OSEL +#define PCN11_OE _pcn11.bit._OE +#define PCN11_IRS0 _pcn11.bit._IRS0 +#define PCN11_IRS1 _pcn11.bit._IRS1 +#define PCN11_IRQF _pcn11.bit._IRQF +#define PCN11_IREN _pcn11.bit._IREN +#define PCN11_EGS0 _pcn11.bit._EGS0 +#define PCN11_EGS1 _pcn11.bit._EGS1 +#define PCN11_PGMS _pcn11.bit._PGMS +#define PCN11_CKS0 _pcn11.bit._CKS0 +#define PCN11_CKS1 _pcn11.bit._CKS1 +#define PCN11_RTRG _pcn11.bit._RTRG +#define PCN11_MDSE _pcn11.bit._MDSE +#define PCN11_STGR _pcn11.bit._STGR +#define PCN11_CNTE _pcn11.bit._CNTE +#define PCN11_IRS _pcn11.bitc._IRS +#define PCN11_EGS _pcn11.bitc._EGS +#define PCN11_CKS _pcn11.bitc._CKS +__IO_EXTENDED PCNL11STR _pcnl11; +#define PCNL11 _pcnl11.byte +#define PCNL11_OSEL _pcnl11.bit._OSEL +#define PCNL11_OE _pcnl11.bit._OE +#define PCNL11_IRS0 _pcnl11.bit._IRS0 +#define PCNL11_IRS1 _pcnl11.bit._IRS1 +#define PCNL11_IRQF _pcnl11.bit._IRQF +#define PCNL11_IREN _pcnl11.bit._IREN +#define PCNL11_EGS0 _pcnl11.bit._EGS0 +#define PCNL11_EGS1 _pcnl11.bit._EGS1 +#define PCNL11_IRS _pcnl11.bitc._IRS +#define PCNL11_EGS _pcnl11.bitc._EGS +__IO_EXTENDED PCNH11STR _pcnh11; +#define PCNH11 _pcnh11.byte +#define PCNH11_PGMS _pcnh11.bit._PGMS +#define PCNH11_CKS0 _pcnh11.bit._CKS0 +#define PCNH11_CKS1 _pcnh11.bit._CKS1 +#define PCNH11_RTRG _pcnh11.bit._RTRG +#define PCNH11_MDSE _pcnh11.bit._MDSE +#define PCNH11_STGR _pcnh11.bit._STGR +#define PCNH11_CNTE _pcnh11.bit._CNTE +#define PCNH11_CKS _pcnh11.bitc._CKS +__IO_EXTENDED GCN13STR _gcn13; +#define GCN13 _gcn13.word +#define GCN13_TSEL00 _gcn13.bit._TSEL00 +#define GCN13_TSEL01 _gcn13.bit._TSEL01 +#define GCN13_TSEL02 _gcn13.bit._TSEL02 +#define GCN13_TSEL03 _gcn13.bit._TSEL03 +#define GCN13_TSEL10 _gcn13.bit._TSEL10 +#define GCN13_TSEL11 _gcn13.bit._TSEL11 +#define GCN13_TSEL12 _gcn13.bit._TSEL12 +#define GCN13_TSEL13 _gcn13.bit._TSEL13 +#define GCN13_TSEL20 _gcn13.bit._TSEL20 +#define GCN13_TSEL21 _gcn13.bit._TSEL21 +#define GCN13_TSEL22 _gcn13.bit._TSEL22 +#define GCN13_TSEL23 _gcn13.bit._TSEL23 +#define GCN13_TSEL30 _gcn13.bit._TSEL30 +#define GCN13_TSEL31 _gcn13.bit._TSEL31 +#define GCN13_TSEL32 _gcn13.bit._TSEL32 +#define GCN13_TSEL33 _gcn13.bit._TSEL33 +#define GCN13_TSEL0 _gcn13.bitc._TSEL0 +#define GCN13_TSEL1 _gcn13.bitc._TSEL1 +#define GCN13_TSEL2 _gcn13.bitc._TSEL2 +#define GCN13_TSEL3 _gcn13.bitc._TSEL3 +__IO_EXTENDED GCN1L3STR _gcn1l3; +#define GCN1L3 _gcn1l3.byte +#define GCN1L3_TSEL00 _gcn1l3.bit._TSEL00 +#define GCN1L3_TSEL01 _gcn1l3.bit._TSEL01 +#define GCN1L3_TSEL02 _gcn1l3.bit._TSEL02 +#define GCN1L3_TSEL03 _gcn1l3.bit._TSEL03 +#define GCN1L3_TSEL10 _gcn1l3.bit._TSEL10 +#define GCN1L3_TSEL11 _gcn1l3.bit._TSEL11 +#define GCN1L3_TSEL12 _gcn1l3.bit._TSEL12 +#define GCN1L3_TSEL13 _gcn1l3.bit._TSEL13 +#define GCN1L3_TSEL0 _gcn1l3.bitc._TSEL0 +#define GCN1L3_TSEL1 _gcn1l3.bitc._TSEL1 +__IO_EXTENDED GCN1H3STR _gcn1h3; +#define GCN1H3 _gcn1h3.byte +#define GCN1H3_TSEL20 _gcn1h3.bit._TSEL20 +#define GCN1H3_TSEL21 _gcn1h3.bit._TSEL21 +#define GCN1H3_TSEL22 _gcn1h3.bit._TSEL22 +#define GCN1H3_TSEL23 _gcn1h3.bit._TSEL23 +#define GCN1H3_TSEL30 _gcn1h3.bit._TSEL30 +#define GCN1H3_TSEL31 _gcn1h3.bit._TSEL31 +#define GCN1H3_TSEL32 _gcn1h3.bit._TSEL32 +#define GCN1H3_TSEL33 _gcn1h3.bit._TSEL33 +#define GCN1H3_TSEL2 _gcn1h3.bitc._TSEL2 +#define GCN1H3_TSEL3 _gcn1h3.bitc._TSEL3 +__IO_EXTENDED GCN23STR _gcn23; +#define GCN23 _gcn23.word +#define GCN23_EN0 _gcn23.bit._EN0 +#define GCN23_EN1 _gcn23.bit._EN1 +#define GCN23_EN2 _gcn23.bit._EN2 +#define GCN23_EN3 _gcn23.bit._EN3 +#define GCN23_CKSEL0 _gcn23.bit._CKSEL0 +#define GCN23_CKSEL1 _gcn23.bit._CKSEL1 +#define GCN23_CKSEL2 _gcn23.bit._CKSEL2 +#define GCN23_CKSEL3 _gcn23.bit._CKSEL3 +#define GCN23_EN _gcn23.bitc._EN +#define GCN23_CKSEL _gcn23.bitc._CKSEL +__IO_EXTENDED GCN2L3STR _gcn2l3; +#define GCN2L3 _gcn2l3.byte +#define GCN2L3_EN0 _gcn2l3.bit._EN0 +#define GCN2L3_EN1 _gcn2l3.bit._EN1 +#define GCN2L3_EN2 _gcn2l3.bit._EN2 +#define GCN2L3_EN3 _gcn2l3.bit._EN3 +#define GCN2L3_EN _gcn2l3.bitc._EN +__IO_EXTENDED GCN2H3STR _gcn2h3; +#define GCN2H3 _gcn2h3.byte +#define GCN2H3_CKSEL0 _gcn2h3.bit._CKSEL0 +#define GCN2H3_CKSEL1 _gcn2h3.bit._CKSEL1 +#define GCN2H3_CKSEL2 _gcn2h3.bit._CKSEL2 +#define GCN2H3_CKSEL3 _gcn2h3.bit._CKSEL3 +#define GCN2H3_CKSEL _gcn2h3.bitc._CKSEL +__IO_EXTENDED PTMR12STR _ptmr12; +#define PTMR12 _ptmr12.word +#define PTMR12_D0 _ptmr12.bit._D0 +#define PTMR12_D1 _ptmr12.bit._D1 +#define PTMR12_D2 _ptmr12.bit._D2 +#define PTMR12_D3 _ptmr12.bit._D3 +#define PTMR12_D4 _ptmr12.bit._D4 +#define PTMR12_D5 _ptmr12.bit._D5 +#define PTMR12_D6 _ptmr12.bit._D6 +#define PTMR12_D7 _ptmr12.bit._D7 +#define PTMR12_D8 _ptmr12.bit._D8 +#define PTMR12_D9 _ptmr12.bit._D9 +#define PTMR12_D10 _ptmr12.bit._D10 +#define PTMR12_D11 _ptmr12.bit._D11 +#define PTMR12_D12 _ptmr12.bit._D12 +#define PTMR12_D13 _ptmr12.bit._D13 +#define PTMR12_D14 _ptmr12.bit._D14 +#define PTMR12_D15 _ptmr12.bit._D15 +#define PTMR12_D _ptmr12.bitc._D +__IO_EXTENDED PCSR12STR _pcsr12; +#define PCSR12 _pcsr12.word +#define PCSR12_D0 _pcsr12.bit._D0 +#define PCSR12_D1 _pcsr12.bit._D1 +#define PCSR12_D2 _pcsr12.bit._D2 +#define PCSR12_D3 _pcsr12.bit._D3 +#define PCSR12_D4 _pcsr12.bit._D4 +#define PCSR12_D5 _pcsr12.bit._D5 +#define PCSR12_D6 _pcsr12.bit._D6 +#define PCSR12_D7 _pcsr12.bit._D7 +#define PCSR12_D8 _pcsr12.bit._D8 +#define PCSR12_D9 _pcsr12.bit._D9 +#define PCSR12_D10 _pcsr12.bit._D10 +#define PCSR12_D11 _pcsr12.bit._D11 +#define PCSR12_D12 _pcsr12.bit._D12 +#define PCSR12_D13 _pcsr12.bit._D13 +#define PCSR12_D14 _pcsr12.bit._D14 +#define PCSR12_D15 _pcsr12.bit._D15 +#define PCSR12_D _pcsr12.bitc._D +__IO_EXTENDED PDUT12STR _pdut12; +#define PDUT12 _pdut12.word +#define PDUT12_D0 _pdut12.bit._D0 +#define PDUT12_D1 _pdut12.bit._D1 +#define PDUT12_D2 _pdut12.bit._D2 +#define PDUT12_D3 _pdut12.bit._D3 +#define PDUT12_D4 _pdut12.bit._D4 +#define PDUT12_D5 _pdut12.bit._D5 +#define PDUT12_D6 _pdut12.bit._D6 +#define PDUT12_D7 _pdut12.bit._D7 +#define PDUT12_D8 _pdut12.bit._D8 +#define PDUT12_D9 _pdut12.bit._D9 +#define PDUT12_D10 _pdut12.bit._D10 +#define PDUT12_D11 _pdut12.bit._D11 +#define PDUT12_D12 _pdut12.bit._D12 +#define PDUT12_D13 _pdut12.bit._D13 +#define PDUT12_D14 _pdut12.bit._D14 +#define PDUT12_D15 _pdut12.bit._D15 +#define PDUT12_D _pdut12.bitc._D +__IO_EXTENDED PCN12STR _pcn12; +#define PCN12 _pcn12.word +#define PCN12_OSEL _pcn12.bit._OSEL +#define PCN12_OE _pcn12.bit._OE +#define PCN12_IRS0 _pcn12.bit._IRS0 +#define PCN12_IRS1 _pcn12.bit._IRS1 +#define PCN12_IRQF _pcn12.bit._IRQF +#define PCN12_IREN _pcn12.bit._IREN +#define PCN12_EGS0 _pcn12.bit._EGS0 +#define PCN12_EGS1 _pcn12.bit._EGS1 +#define PCN12_PGMS _pcn12.bit._PGMS +#define PCN12_CKS0 _pcn12.bit._CKS0 +#define PCN12_CKS1 _pcn12.bit._CKS1 +#define PCN12_RTRG _pcn12.bit._RTRG +#define PCN12_MDSE _pcn12.bit._MDSE +#define PCN12_STGR _pcn12.bit._STGR +#define PCN12_CNTE _pcn12.bit._CNTE +#define PCN12_IRS _pcn12.bitc._IRS +#define PCN12_EGS _pcn12.bitc._EGS +#define PCN12_CKS _pcn12.bitc._CKS +__IO_EXTENDED PCNL12STR _pcnl12; +#define PCNL12 _pcnl12.byte +#define PCNL12_OSEL _pcnl12.bit._OSEL +#define PCNL12_OE _pcnl12.bit._OE +#define PCNL12_IRS0 _pcnl12.bit._IRS0 +#define PCNL12_IRS1 _pcnl12.bit._IRS1 +#define PCNL12_IRQF _pcnl12.bit._IRQF +#define PCNL12_IREN _pcnl12.bit._IREN +#define PCNL12_EGS0 _pcnl12.bit._EGS0 +#define PCNL12_EGS1 _pcnl12.bit._EGS1 +#define PCNL12_IRS _pcnl12.bitc._IRS +#define PCNL12_EGS _pcnl12.bitc._EGS +__IO_EXTENDED PCNH12STR _pcnh12; +#define PCNH12 _pcnh12.byte +#define PCNH12_PGMS _pcnh12.bit._PGMS +#define PCNH12_CKS0 _pcnh12.bit._CKS0 +#define PCNH12_CKS1 _pcnh12.bit._CKS1 +#define PCNH12_RTRG _pcnh12.bit._RTRG +#define PCNH12_MDSE _pcnh12.bit._MDSE +#define PCNH12_STGR _pcnh12.bit._STGR +#define PCNH12_CNTE _pcnh12.bit._CNTE +#define PCNH12_CKS _pcnh12.bitc._CKS +__IO_EXTENDED PTMR13STR _ptmr13; +#define PTMR13 _ptmr13.word +#define PTMR13_D0 _ptmr13.bit._D0 +#define PTMR13_D1 _ptmr13.bit._D1 +#define PTMR13_D2 _ptmr13.bit._D2 +#define PTMR13_D3 _ptmr13.bit._D3 +#define PTMR13_D4 _ptmr13.bit._D4 +#define PTMR13_D5 _ptmr13.bit._D5 +#define PTMR13_D6 _ptmr13.bit._D6 +#define PTMR13_D7 _ptmr13.bit._D7 +#define PTMR13_D8 _ptmr13.bit._D8 +#define PTMR13_D9 _ptmr13.bit._D9 +#define PTMR13_D10 _ptmr13.bit._D10 +#define PTMR13_D11 _ptmr13.bit._D11 +#define PTMR13_D12 _ptmr13.bit._D12 +#define PTMR13_D13 _ptmr13.bit._D13 +#define PTMR13_D14 _ptmr13.bit._D14 +#define PTMR13_D15 _ptmr13.bit._D15 +#define PTMR13_D _ptmr13.bitc._D +__IO_EXTENDED PCSR13STR _pcsr13; +#define PCSR13 _pcsr13.word +#define PCSR13_D0 _pcsr13.bit._D0 +#define PCSR13_D1 _pcsr13.bit._D1 +#define PCSR13_D2 _pcsr13.bit._D2 +#define PCSR13_D3 _pcsr13.bit._D3 +#define PCSR13_D4 _pcsr13.bit._D4 +#define PCSR13_D5 _pcsr13.bit._D5 +#define PCSR13_D6 _pcsr13.bit._D6 +#define PCSR13_D7 _pcsr13.bit._D7 +#define PCSR13_D8 _pcsr13.bit._D8 +#define PCSR13_D9 _pcsr13.bit._D9 +#define PCSR13_D10 _pcsr13.bit._D10 +#define PCSR13_D11 _pcsr13.bit._D11 +#define PCSR13_D12 _pcsr13.bit._D12 +#define PCSR13_D13 _pcsr13.bit._D13 +#define PCSR13_D14 _pcsr13.bit._D14 +#define PCSR13_D15 _pcsr13.bit._D15 +#define PCSR13_D _pcsr13.bitc._D +__IO_EXTENDED PDUT13STR _pdut13; +#define PDUT13 _pdut13.word +#define PDUT13_D0 _pdut13.bit._D0 +#define PDUT13_D1 _pdut13.bit._D1 +#define PDUT13_D2 _pdut13.bit._D2 +#define PDUT13_D3 _pdut13.bit._D3 +#define PDUT13_D4 _pdut13.bit._D4 +#define PDUT13_D5 _pdut13.bit._D5 +#define PDUT13_D6 _pdut13.bit._D6 +#define PDUT13_D7 _pdut13.bit._D7 +#define PDUT13_D8 _pdut13.bit._D8 +#define PDUT13_D9 _pdut13.bit._D9 +#define PDUT13_D10 _pdut13.bit._D10 +#define PDUT13_D11 _pdut13.bit._D11 +#define PDUT13_D12 _pdut13.bit._D12 +#define PDUT13_D13 _pdut13.bit._D13 +#define PDUT13_D14 _pdut13.bit._D14 +#define PDUT13_D15 _pdut13.bit._D15 +#define PDUT13_D _pdut13.bitc._D +__IO_EXTENDED PCN13STR _pcn13; +#define PCN13 _pcn13.word +#define PCN13_OSEL _pcn13.bit._OSEL +#define PCN13_OE _pcn13.bit._OE +#define PCN13_IRS0 _pcn13.bit._IRS0 +#define PCN13_IRS1 _pcn13.bit._IRS1 +#define PCN13_IRQF _pcn13.bit._IRQF +#define PCN13_IREN _pcn13.bit._IREN +#define PCN13_EGS0 _pcn13.bit._EGS0 +#define PCN13_EGS1 _pcn13.bit._EGS1 +#define PCN13_PGMS _pcn13.bit._PGMS +#define PCN13_CKS0 _pcn13.bit._CKS0 +#define PCN13_CKS1 _pcn13.bit._CKS1 +#define PCN13_RTRG _pcn13.bit._RTRG +#define PCN13_MDSE _pcn13.bit._MDSE +#define PCN13_STGR _pcn13.bit._STGR +#define PCN13_CNTE _pcn13.bit._CNTE +#define PCN13_IRS _pcn13.bitc._IRS +#define PCN13_EGS _pcn13.bitc._EGS +#define PCN13_CKS _pcn13.bitc._CKS +__IO_EXTENDED PCNL13STR _pcnl13; +#define PCNL13 _pcnl13.byte +#define PCNL13_OSEL _pcnl13.bit._OSEL +#define PCNL13_OE _pcnl13.bit._OE +#define PCNL13_IRS0 _pcnl13.bit._IRS0 +#define PCNL13_IRS1 _pcnl13.bit._IRS1 +#define PCNL13_IRQF _pcnl13.bit._IRQF +#define PCNL13_IREN _pcnl13.bit._IREN +#define PCNL13_EGS0 _pcnl13.bit._EGS0 +#define PCNL13_EGS1 _pcnl13.bit._EGS1 +#define PCNL13_IRS _pcnl13.bitc._IRS +#define PCNL13_EGS _pcnl13.bitc._EGS +__IO_EXTENDED PCNH13STR _pcnh13; +#define PCNH13 _pcnh13.byte +#define PCNH13_PGMS _pcnh13.bit._PGMS +#define PCNH13_CKS0 _pcnh13.bit._CKS0 +#define PCNH13_CKS1 _pcnh13.bit._CKS1 +#define PCNH13_RTRG _pcnh13.bit._RTRG +#define PCNH13_MDSE _pcnh13.bit._MDSE +#define PCNH13_STGR _pcnh13.bit._STGR +#define PCNH13_CNTE _pcnh13.bit._CNTE +#define PCNH13_CKS _pcnh13.bitc._CKS +__IO_EXTENDED PTMR14STR _ptmr14; +#define PTMR14 _ptmr14.word +#define PTMR14_D0 _ptmr14.bit._D0 +#define PTMR14_D1 _ptmr14.bit._D1 +#define PTMR14_D2 _ptmr14.bit._D2 +#define PTMR14_D3 _ptmr14.bit._D3 +#define PTMR14_D4 _ptmr14.bit._D4 +#define PTMR14_D5 _ptmr14.bit._D5 +#define PTMR14_D6 _ptmr14.bit._D6 +#define PTMR14_D7 _ptmr14.bit._D7 +#define PTMR14_D8 _ptmr14.bit._D8 +#define PTMR14_D9 _ptmr14.bit._D9 +#define PTMR14_D10 _ptmr14.bit._D10 +#define PTMR14_D11 _ptmr14.bit._D11 +#define PTMR14_D12 _ptmr14.bit._D12 +#define PTMR14_D13 _ptmr14.bit._D13 +#define PTMR14_D14 _ptmr14.bit._D14 +#define PTMR14_D15 _ptmr14.bit._D15 +#define PTMR14_D _ptmr14.bitc._D +__IO_EXTENDED PCSR14STR _pcsr14; +#define PCSR14 _pcsr14.word +#define PCSR14_D0 _pcsr14.bit._D0 +#define PCSR14_D1 _pcsr14.bit._D1 +#define PCSR14_D2 _pcsr14.bit._D2 +#define PCSR14_D3 _pcsr14.bit._D3 +#define PCSR14_D4 _pcsr14.bit._D4 +#define PCSR14_D5 _pcsr14.bit._D5 +#define PCSR14_D6 _pcsr14.bit._D6 +#define PCSR14_D7 _pcsr14.bit._D7 +#define PCSR14_D8 _pcsr14.bit._D8 +#define PCSR14_D9 _pcsr14.bit._D9 +#define PCSR14_D10 _pcsr14.bit._D10 +#define PCSR14_D11 _pcsr14.bit._D11 +#define PCSR14_D12 _pcsr14.bit._D12 +#define PCSR14_D13 _pcsr14.bit._D13 +#define PCSR14_D14 _pcsr14.bit._D14 +#define PCSR14_D15 _pcsr14.bit._D15 +#define PCSR14_D _pcsr14.bitc._D +__IO_EXTENDED PDUT14STR _pdut14; +#define PDUT14 _pdut14.word +#define PDUT14_D0 _pdut14.bit._D0 +#define PDUT14_D1 _pdut14.bit._D1 +#define PDUT14_D2 _pdut14.bit._D2 +#define PDUT14_D3 _pdut14.bit._D3 +#define PDUT14_D4 _pdut14.bit._D4 +#define PDUT14_D5 _pdut14.bit._D5 +#define PDUT14_D6 _pdut14.bit._D6 +#define PDUT14_D7 _pdut14.bit._D7 +#define PDUT14_D8 _pdut14.bit._D8 +#define PDUT14_D9 _pdut14.bit._D9 +#define PDUT14_D10 _pdut14.bit._D10 +#define PDUT14_D11 _pdut14.bit._D11 +#define PDUT14_D12 _pdut14.bit._D12 +#define PDUT14_D13 _pdut14.bit._D13 +#define PDUT14_D14 _pdut14.bit._D14 +#define PDUT14_D15 _pdut14.bit._D15 +#define PDUT14_D _pdut14.bitc._D +__IO_EXTENDED PCN14STR _pcn14; +#define PCN14 _pcn14.word +#define PCN14_OSEL _pcn14.bit._OSEL +#define PCN14_OE _pcn14.bit._OE +#define PCN14_IRS0 _pcn14.bit._IRS0 +#define PCN14_IRS1 _pcn14.bit._IRS1 +#define PCN14_IRQF _pcn14.bit._IRQF +#define PCN14_IREN _pcn14.bit._IREN +#define PCN14_EGS0 _pcn14.bit._EGS0 +#define PCN14_EGS1 _pcn14.bit._EGS1 +#define PCN14_PGMS _pcn14.bit._PGMS +#define PCN14_CKS0 _pcn14.bit._CKS0 +#define PCN14_CKS1 _pcn14.bit._CKS1 +#define PCN14_RTRG _pcn14.bit._RTRG +#define PCN14_MDSE _pcn14.bit._MDSE +#define PCN14_STGR _pcn14.bit._STGR +#define PCN14_CNTE _pcn14.bit._CNTE +#define PCN14_IRS _pcn14.bitc._IRS +#define PCN14_EGS _pcn14.bitc._EGS +#define PCN14_CKS _pcn14.bitc._CKS +__IO_EXTENDED PCNL14STR _pcnl14; +#define PCNL14 _pcnl14.byte +#define PCNL14_OSEL _pcnl14.bit._OSEL +#define PCNL14_OE _pcnl14.bit._OE +#define PCNL14_IRS0 _pcnl14.bit._IRS0 +#define PCNL14_IRS1 _pcnl14.bit._IRS1 +#define PCNL14_IRQF _pcnl14.bit._IRQF +#define PCNL14_IREN _pcnl14.bit._IREN +#define PCNL14_EGS0 _pcnl14.bit._EGS0 +#define PCNL14_EGS1 _pcnl14.bit._EGS1 +#define PCNL14_IRS _pcnl14.bitc._IRS +#define PCNL14_EGS _pcnl14.bitc._EGS +__IO_EXTENDED PCNH14STR _pcnh14; +#define PCNH14 _pcnh14.byte +#define PCNH14_PGMS _pcnh14.bit._PGMS +#define PCNH14_CKS0 _pcnh14.bit._CKS0 +#define PCNH14_CKS1 _pcnh14.bit._CKS1 +#define PCNH14_RTRG _pcnh14.bit._RTRG +#define PCNH14_MDSE _pcnh14.bit._MDSE +#define PCNH14_STGR _pcnh14.bit._STGR +#define PCNH14_CNTE _pcnh14.bit._CNTE +#define PCNH14_CKS _pcnh14.bitc._CKS +__IO_EXTENDED PTMR15STR _ptmr15; +#define PTMR15 _ptmr15.word +#define PTMR15_D0 _ptmr15.bit._D0 +#define PTMR15_D1 _ptmr15.bit._D1 +#define PTMR15_D2 _ptmr15.bit._D2 +#define PTMR15_D3 _ptmr15.bit._D3 +#define PTMR15_D4 _ptmr15.bit._D4 +#define PTMR15_D5 _ptmr15.bit._D5 +#define PTMR15_D6 _ptmr15.bit._D6 +#define PTMR15_D7 _ptmr15.bit._D7 +#define PTMR15_D8 _ptmr15.bit._D8 +#define PTMR15_D9 _ptmr15.bit._D9 +#define PTMR15_D10 _ptmr15.bit._D10 +#define PTMR15_D11 _ptmr15.bit._D11 +#define PTMR15_D12 _ptmr15.bit._D12 +#define PTMR15_D13 _ptmr15.bit._D13 +#define PTMR15_D14 _ptmr15.bit._D14 +#define PTMR15_D15 _ptmr15.bit._D15 +#define PTMR15_D _ptmr15.bitc._D +__IO_EXTENDED PCSR15STR _pcsr15; +#define PCSR15 _pcsr15.word +#define PCSR15_D0 _pcsr15.bit._D0 +#define PCSR15_D1 _pcsr15.bit._D1 +#define PCSR15_D2 _pcsr15.bit._D2 +#define PCSR15_D3 _pcsr15.bit._D3 +#define PCSR15_D4 _pcsr15.bit._D4 +#define PCSR15_D5 _pcsr15.bit._D5 +#define PCSR15_D6 _pcsr15.bit._D6 +#define PCSR15_D7 _pcsr15.bit._D7 +#define PCSR15_D8 _pcsr15.bit._D8 +#define PCSR15_D9 _pcsr15.bit._D9 +#define PCSR15_D10 _pcsr15.bit._D10 +#define PCSR15_D11 _pcsr15.bit._D11 +#define PCSR15_D12 _pcsr15.bit._D12 +#define PCSR15_D13 _pcsr15.bit._D13 +#define PCSR15_D14 _pcsr15.bit._D14 +#define PCSR15_D15 _pcsr15.bit._D15 +#define PCSR15_D _pcsr15.bitc._D +__IO_EXTENDED PDUT15STR _pdut15; +#define PDUT15 _pdut15.word +#define PDUT15_D0 _pdut15.bit._D0 +#define PDUT15_D1 _pdut15.bit._D1 +#define PDUT15_D2 _pdut15.bit._D2 +#define PDUT15_D3 _pdut15.bit._D3 +#define PDUT15_D4 _pdut15.bit._D4 +#define PDUT15_D5 _pdut15.bit._D5 +#define PDUT15_D6 _pdut15.bit._D6 +#define PDUT15_D7 _pdut15.bit._D7 +#define PDUT15_D8 _pdut15.bit._D8 +#define PDUT15_D9 _pdut15.bit._D9 +#define PDUT15_D10 _pdut15.bit._D10 +#define PDUT15_D11 _pdut15.bit._D11 +#define PDUT15_D12 _pdut15.bit._D12 +#define PDUT15_D13 _pdut15.bit._D13 +#define PDUT15_D14 _pdut15.bit._D14 +#define PDUT15_D15 _pdut15.bit._D15 +#define PDUT15_D _pdut15.bitc._D +__IO_EXTENDED PCN15STR _pcn15; +#define PCN15 _pcn15.word +#define PCN15_OSEL _pcn15.bit._OSEL +#define PCN15_OE _pcn15.bit._OE +#define PCN15_IRS0 _pcn15.bit._IRS0 +#define PCN15_IRS1 _pcn15.bit._IRS1 +#define PCN15_IRQF _pcn15.bit._IRQF +#define PCN15_IREN _pcn15.bit._IREN +#define PCN15_EGS0 _pcn15.bit._EGS0 +#define PCN15_EGS1 _pcn15.bit._EGS1 +#define PCN15_PGMS _pcn15.bit._PGMS +#define PCN15_CKS0 _pcn15.bit._CKS0 +#define PCN15_CKS1 _pcn15.bit._CKS1 +#define PCN15_RTRG _pcn15.bit._RTRG +#define PCN15_MDSE _pcn15.bit._MDSE +#define PCN15_STGR _pcn15.bit._STGR +#define PCN15_CNTE _pcn15.bit._CNTE +#define PCN15_IRS _pcn15.bitc._IRS +#define PCN15_EGS _pcn15.bitc._EGS +#define PCN15_CKS _pcn15.bitc._CKS +__IO_EXTENDED PCNL15STR _pcnl15; +#define PCNL15 _pcnl15.byte +#define PCNL15_OSEL _pcnl15.bit._OSEL +#define PCNL15_OE _pcnl15.bit._OE +#define PCNL15_IRS0 _pcnl15.bit._IRS0 +#define PCNL15_IRS1 _pcnl15.bit._IRS1 +#define PCNL15_IRQF _pcnl15.bit._IRQF +#define PCNL15_IREN _pcnl15.bit._IREN +#define PCNL15_EGS0 _pcnl15.bit._EGS0 +#define PCNL15_EGS1 _pcnl15.bit._EGS1 +#define PCNL15_IRS _pcnl15.bitc._IRS +#define PCNL15_EGS _pcnl15.bitc._EGS +__IO_EXTENDED PCNH15STR _pcnh15; +#define PCNH15 _pcnh15.byte +#define PCNH15_PGMS _pcnh15.bit._PGMS +#define PCNH15_CKS0 _pcnh15.bit._CKS0 +#define PCNH15_CKS1 _pcnh15.bit._CKS1 +#define PCNH15_RTRG _pcnh15.bit._RTRG +#define PCNH15_MDSE _pcnh15.bit._MDSE +#define PCNH15_STGR _pcnh15.bit._STGR +#define PCNH15_CNTE _pcnh15.bit._CNTE +#define PCNH15_CKS _pcnh15.bitc._CKS +__IO_EXTENDED PRRR10STR _prrr10; +#define PRRR10 _prrr10.byte +#define PRRR10_PPG8_R _prrr10.bit._PPG8_R +#define PRRR10_PPG9_R _prrr10.bit._PPG9_R +#define PRRR10_PPG10_R _prrr10.bit._PPG10_R +#define PRRR10_PPG11_R _prrr10.bit._PPG11_R +#define PRRR10_TTG8_R _prrr10.bit._TTG8_R +#define PRRR10_TTG9_R _prrr10.bit._TTG9_R +#define PRRR10_TTG10_R _prrr10.bit._TTG10_R +#define PRRR10_TTG11_R _prrr10.bit._TTG11_R +__IO_EXTENDED PRRR11STR _prrr11; +#define PRRR11 _prrr11.byte +#define PRRR11_PPG16_R _prrr11.bit._PPG16_R +#define PRRR11_PPG17_R _prrr11.bit._PPG17_R +#define PRRR11_PPG18_R _prrr11.bit._PPG18_R +#define PRRR11_PPG19_R _prrr11.bit._PPG19_R +#define PRRR11_TTG16_R _prrr11.bit._TTG16_R +#define PRRR11_TTG17_R _prrr11.bit._TTG17_R +#define PRRR11_TTG18_R _prrr11.bit._TTG18_R +#define PRRR11_TTG19_R _prrr11.bit._TTG19_R +__IO_EXTENDED PRRR12STR _prrr12; +#define PRRR12 _prrr12.byte +#define PRRR12_CS0_R _prrr12.bit._CS0_R +#define PRRR12_CS1_R _prrr12.bit._CS1_R +#define PRRR12_CS2_R _prrr12.bit._CS2_R +#define PRRR12_CS4_R _prrr12.bit._CS4_R +#define PRRR12_CS5_R _prrr12.bit._CS5_R +__IO_EXTENDED PRRR13STR _prrr13; +#define PRRR13 _prrr13.byte +__IO_EXTENDED EAC0STR _eac0; +#define EAC0 _eac0.word +#define EAC0_R0 _eac0.bit._R0 +#define EAC0_R1 _eac0.bit._R1 +#define EAC0_R2 _eac0.bit._R2 +#define EAC0_ACE _eac0.bit._ACE +#define EAC0_STS _eac0.bit._STS +#define EAC0_WSF _eac0.bit._WSF +#define EAC0_ES _eac0.bit._ES +#define EAC0_BW _eac0.bit._BW +#define EAC0_CSE _eac0.bit._CSE +#define EAC0_CSL _eac0.bit._CSL +#define EAC0_ATL _eac0.bit._ATL +#define EAC0_R _eac0.bitc._R +__IO_EXTENDED EACL0STR _eacl0; +#define EACL0 _eacl0.byte +#define EACL0_R0 _eacl0.bit._R0 +#define EACL0_R1 _eacl0.bit._R1 +#define EACL0_R2 _eacl0.bit._R2 +#define EACL0_ACE _eacl0.bit._ACE +#define EACL0_STS _eacl0.bit._STS +#define EACL0_WSF _eacl0.bit._WSF +#define EACL0_ES _eacl0.bit._ES +#define EACL0_BW _eacl0.bit._BW +#define EACL0_R _eacl0.bitc._R +__IO_EXTENDED EACH0STR _each0; +#define EACH0 _each0.byte +#define EACH0_CSE _each0.bit._CSE +#define EACH0_CSL _each0.bit._CSL +#define EACH0_ATL _each0.bit._ATL +__IO_EXTENDED EAC1STR _eac1; +#define EAC1 _eac1.word +#define EAC1_R0 _eac1.bit._R0 +#define EAC1_R1 _eac1.bit._R1 +#define EAC1_R2 _eac1.bit._R2 +#define EAC1_ACE _eac1.bit._ACE +#define EAC1_STS _eac1.bit._STS +#define EAC1_WSF _eac1.bit._WSF +#define EAC1_ES _eac1.bit._ES +#define EAC1_BW _eac1.bit._BW +#define EAC1_CSE _eac1.bit._CSE +#define EAC1_CSL _eac1.bit._CSL +#define EAC1_ATL _eac1.bit._ATL +#define EAC1_R _eac1.bitc._R +__IO_EXTENDED EACL1STR _eacl1; +#define EACL1 _eacl1.byte +#define EACL1_R0 _eacl1.bit._R0 +#define EACL1_R1 _eacl1.bit._R1 +#define EACL1_R2 _eacl1.bit._R2 +#define EACL1_ACE _eacl1.bit._ACE +#define EACL1_STS _eacl1.bit._STS +#define EACL1_WSF _eacl1.bit._WSF +#define EACL1_ES _eacl1.bit._ES +#define EACL1_BW _eacl1.bit._BW +#define EACL1_R _eacl1.bitc._R +__IO_EXTENDED EACH1STR _each1; +#define EACH1 _each1.byte +#define EACH1_CSE _each1.bit._CSE +#define EACH1_CSL _each1.bit._CSL +#define EACH1_ATL _each1.bit._ATL +__IO_EXTENDED EAC2STR _eac2; +#define EAC2 _eac2.word +#define EAC2_R0 _eac2.bit._R0 +#define EAC2_R1 _eac2.bit._R1 +#define EAC2_R2 _eac2.bit._R2 +#define EAC2_ACE _eac2.bit._ACE +#define EAC2_STS _eac2.bit._STS +#define EAC2_WSF _eac2.bit._WSF +#define EAC2_ES _eac2.bit._ES +#define EAC2_BW _eac2.bit._BW +#define EAC2_EASZ0 _eac2.bit._EASZ0 +#define EAC2_EASZ1 _eac2.bit._EASZ1 +#define EAC2_EASZ2 _eac2.bit._EASZ2 +#define EAC2_CSE _eac2.bit._CSE +#define EAC2_CSL _eac2.bit._CSL +#define EAC2_ATL _eac2.bit._ATL +#define EAC2_R _eac2.bitc._R +#define EAC2_EASZ _eac2.bitc._EASZ +__IO_EXTENDED EACL2STR _eacl2; +#define EACL2 _eacl2.byte +#define EACL2_R0 _eacl2.bit._R0 +#define EACL2_R1 _eacl2.bit._R1 +#define EACL2_R2 _eacl2.bit._R2 +#define EACL2_ACE _eacl2.bit._ACE +#define EACL2_STS _eacl2.bit._STS +#define EACL2_WSF _eacl2.bit._WSF +#define EACL2_ES _eacl2.bit._ES +#define EACL2_BW _eacl2.bit._BW +#define EACL2_R _eacl2.bitc._R +__IO_EXTENDED EACH2STR _each2; +#define EACH2 _each2.byte +#define EACH2_EASZ0 _each2.bit._EASZ0 +#define EACH2_EASZ1 _each2.bit._EASZ1 +#define EACH2_EASZ2 _each2.bit._EASZ2 +#define EACH2_CSE _each2.bit._CSE +#define EACH2_CSL _each2.bit._CSL +#define EACH2_ATL _each2.bit._ATL +#define EACH2_EASZ _each2.bitc._EASZ +__IO_EXTENDED EAC3STR _eac3; +#define EAC3 _eac3.word +#define EAC3_R0 _eac3.bit._R0 +#define EAC3_R1 _eac3.bit._R1 +#define EAC3_R2 _eac3.bit._R2 +#define EAC3_ACE _eac3.bit._ACE +#define EAC3_STS _eac3.bit._STS +#define EAC3_WSF _eac3.bit._WSF +#define EAC3_ES _eac3.bit._ES +#define EAC3_BW _eac3.bit._BW +#define EAC3_EASZ0 _eac3.bit._EASZ0 +#define EAC3_EASZ1 _eac3.bit._EASZ1 +#define EAC3_EASZ2 _eac3.bit._EASZ2 +#define EAC3_CSE _eac3.bit._CSE +#define EAC3_CSL _eac3.bit._CSL +#define EAC3_ATL _eac3.bit._ATL +#define EAC3_R _eac3.bitc._R +#define EAC3_EASZ _eac3.bitc._EASZ +__IO_EXTENDED EACL3STR _eacl3; +#define EACL3 _eacl3.byte +#define EACL3_R0 _eacl3.bit._R0 +#define EACL3_R1 _eacl3.bit._R1 +#define EACL3_R2 _eacl3.bit._R2 +#define EACL3_ACE _eacl3.bit._ACE +#define EACL3_STS _eacl3.bit._STS +#define EACL3_WSF _eacl3.bit._WSF +#define EACL3_ES _eacl3.bit._ES +#define EACL3_BW _eacl3.bit._BW +#define EACL3_R _eacl3.bitc._R +__IO_EXTENDED EACH3STR _each3; +#define EACH3 _each3.byte +#define EACH3_EASZ0 _each3.bit._EASZ0 +#define EACH3_EASZ1 _each3.bit._EASZ1 +#define EACH3_EASZ2 _each3.bit._EASZ2 +#define EACH3_CSE _each3.bit._CSE +#define EACH3_CSL _each3.bit._CSL +#define EACH3_ATL _each3.bit._ATL +#define EACH3_EASZ _each3.bitc._EASZ +__IO_EXTENDED EAC4STR _eac4; +#define EAC4 _eac4.word +#define EAC4_R0 _eac4.bit._R0 +#define EAC4_R1 _eac4.bit._R1 +#define EAC4_R2 _eac4.bit._R2 +#define EAC4_ACE _eac4.bit._ACE +#define EAC4_STS _eac4.bit._STS +#define EAC4_WSF _eac4.bit._WSF +#define EAC4_ES _eac4.bit._ES +#define EAC4_BW _eac4.bit._BW +#define EAC4_EASZ0 _eac4.bit._EASZ0 +#define EAC4_EASZ1 _eac4.bit._EASZ1 +#define EAC4_EASZ2 _eac4.bit._EASZ2 +#define EAC4_CSE _eac4.bit._CSE +#define EAC4_CSL _eac4.bit._CSL +#define EAC4_ATL _eac4.bit._ATL +#define EAC4_R _eac4.bitc._R +#define EAC4_EASZ _eac4.bitc._EASZ +__IO_EXTENDED EACL4STR _eacl4; +#define EACL4 _eacl4.byte +#define EACL4_R0 _eacl4.bit._R0 +#define EACL4_R1 _eacl4.bit._R1 +#define EACL4_R2 _eacl4.bit._R2 +#define EACL4_ACE _eacl4.bit._ACE +#define EACL4_STS _eacl4.bit._STS +#define EACL4_WSF _eacl4.bit._WSF +#define EACL4_ES _eacl4.bit._ES +#define EACL4_BW _eacl4.bit._BW +#define EACL4_R _eacl4.bitc._R +__IO_EXTENDED EACH4STR _each4; +#define EACH4 _each4.byte +#define EACH4_EASZ0 _each4.bit._EASZ0 +#define EACH4_EASZ1 _each4.bit._EASZ1 +#define EACH4_EASZ2 _each4.bit._EASZ2 +#define EACH4_CSE _each4.bit._CSE +#define EACH4_CSL _each4.bit._CSL +#define EACH4_ATL _each4.bit._ATL +#define EACH4_EASZ _each4.bitc._EASZ +__IO_EXTENDED EAC5STR _eac5; +#define EAC5 _eac5.word +#define EAC5_R0 _eac5.bit._R0 +#define EAC5_R1 _eac5.bit._R1 +#define EAC5_R2 _eac5.bit._R2 +#define EAC5_ACE _eac5.bit._ACE +#define EAC5_STS _eac5.bit._STS +#define EAC5_WSF _eac5.bit._WSF +#define EAC5_ES _eac5.bit._ES +#define EAC5_BW _eac5.bit._BW +#define EAC5_EASZ0 _eac5.bit._EASZ0 +#define EAC5_EASZ1 _eac5.bit._EASZ1 +#define EAC5_EASZ2 _eac5.bit._EASZ2 +#define EAC5_CSE _eac5.bit._CSE +#define EAC5_CSL _eac5.bit._CSL +#define EAC5_ATL _eac5.bit._ATL +#define EAC5_R _eac5.bitc._R +#define EAC5_EASZ _eac5.bitc._EASZ +__IO_EXTENDED EACL5STR _eacl5; +#define EACL5 _eacl5.byte +#define EACL5_R0 _eacl5.bit._R0 +#define EACL5_R1 _eacl5.bit._R1 +#define EACL5_R2 _eacl5.bit._R2 +#define EACL5_ACE _eacl5.bit._ACE +#define EACL5_STS _eacl5.bit._STS +#define EACL5_WSF _eacl5.bit._WSF +#define EACL5_ES _eacl5.bit._ES +#define EACL5_BW _eacl5.bit._BW +#define EACL5_R _eacl5.bitc._R +__IO_EXTENDED EACH5STR _each5; +#define EACH5 _each5.byte +#define EACH5_EASZ0 _each5.bit._EASZ0 +#define EACH5_EASZ1 _each5.bit._EASZ1 +#define EACH5_EASZ2 _each5.bit._EASZ2 +#define EACH5_CSE _each5.bit._CSE +#define EACH5_CSL _each5.bit._CSL +#define EACH5_ATL _each5.bit._ATL +#define EACH5_EASZ _each5.bitc._EASZ +__IO_EXTENDED EAS2STR _eas2; +#define EAS2 _eas2.byte +#define EAS2_A0 _eas2.bit._A0 +#define EAS2_A1 _eas2.bit._A1 +#define EAS2_A2 _eas2.bit._A2 +#define EAS2_A3 _eas2.bit._A3 +#define EAS2_A4 _eas2.bit._A4 +#define EAS2_A5 _eas2.bit._A5 +#define EAS2_A6 _eas2.bit._A6 +#define EAS2_A7 _eas2.bit._A7 +#define EAS2_A _eas2.bitc._A +__IO_EXTENDED EAS3STR _eas3; +#define EAS3 _eas3.byte +#define EAS3_A0 _eas3.bit._A0 +#define EAS3_A1 _eas3.bit._A1 +#define EAS3_A2 _eas3.bit._A2 +#define EAS3_A3 _eas3.bit._A3 +#define EAS3_A4 _eas3.bit._A4 +#define EAS3_A5 _eas3.bit._A5 +#define EAS3_A6 _eas3.bit._A6 +#define EAS3_A7 _eas3.bit._A7 +#define EAS3_A _eas3.bitc._A +__IO_EXTENDED EAS4STR _eas4; +#define EAS4 _eas4.byte +#define EAS4_A0 _eas4.bit._A0 +#define EAS4_A1 _eas4.bit._A1 +#define EAS4_A2 _eas4.bit._A2 +#define EAS4_A3 _eas4.bit._A3 +#define EAS4_A4 _eas4.bit._A4 +#define EAS4_A5 _eas4.bit._A5 +#define EAS4_A6 _eas4.bit._A6 +#define EAS4_A7 _eas4.bit._A7 +#define EAS4_A _eas4.bitc._A +__IO_EXTENDED EAS5STR _eas5; +#define EAS5 _eas5.byte +#define EAS5_A0 _eas5.bit._A0 +#define EAS5_A1 _eas5.bit._A1 +#define EAS5_A2 _eas5.bit._A2 +#define EAS5_A3 _eas5.bit._A3 +#define EAS5_A4 _eas5.bit._A4 +#define EAS5_A5 _eas5.bit._A5 +#define EAS5_A6 _eas5.bit._A6 +#define EAS5_A7 _eas5.bit._A7 +__IO_EXTENDED EBMSTR _ebm; +#define EBM _ebm.byte +#define EBM_EAE0 _ebm.bit._EAE0 +#define EBM_EAE1 _ebm.bit._EAE1 +#define EBM_EAE2 _ebm.bit._EAE2 +#define EBM_EAE3 _ebm.bit._EAE3 +#define EBM_EAE4 _ebm.bit._EAE4 +#define EBM_EAE5 _ebm.bit._EAE5 +#define EBM_ERE _ebm.bit._ERE +#define EBM_NMS _ebm.bit._NMS +#define EBM_EAE _ebm.bitc._EAE +__IO_EXTENDED EBCFSTR _ebcf; +#define EBCF _ebcf.byte +#define EBCF_DIV0 _ebcf.bit._DIV0 +#define EBCF_DIV1 _ebcf.bit._DIV1 +#define EBCF_DIV2 _ebcf.bit._DIV2 +#define EBCF_CSM _ebcf.bit._CSM +#define EBCF_CKI _ebcf.bit._CKI +#define EBCF_CKE _ebcf.bit._CKE +#define EBCF_RYE _ebcf.bit._RYE +#define EBCF_HDE _ebcf.bit._HDE +#define EBCF_DIV _ebcf.bitc._DIV +__IO_EXTENDED EBAE0STR _ebae0; +#define EBAE0 _ebae0.byte +#define EBAE0_A00 _ebae0.bit._A00 +#define EBAE0_A01 _ebae0.bit._A01 +#define EBAE0_A02 _ebae0.bit._A02 +#define EBAE0_A03 _ebae0.bit._A03 +#define EBAE0_A04 _ebae0.bit._A04 +#define EBAE0_A05 _ebae0.bit._A05 +#define EBAE0_A06 _ebae0.bit._A06 +#define EBAE0_A07 _ebae0.bit._A07 +__IO_EXTENDED EBAE1STR _ebae1; +#define EBAE1 _ebae1.byte +#define EBAE1_A08 _ebae1.bit._A08 +#define EBAE1_A09 _ebae1.bit._A09 +#define EBAE1_A10 _ebae1.bit._A10 +#define EBAE1_A11 _ebae1.bit._A11 +#define EBAE1_A12 _ebae1.bit._A12 +#define EBAE1_A13 _ebae1.bit._A13 +#define EBAE1_A14 _ebae1.bit._A14 +#define EBAE1_A15 _ebae1.bit._A15 +__IO_EXTENDED EBAE2STR _ebae2; +#define EBAE2 _ebae2.byte +#define EBAE2_A16 _ebae2.bit._A16 +#define EBAE2_A17 _ebae2.bit._A17 +#define EBAE2_A18 _ebae2.bit._A18 +#define EBAE2_A19 _ebae2.bit._A19 +#define EBAE2_A20 _ebae2.bit._A20 +#define EBAE2_A21 _ebae2.bit._A21 +#define EBAE2_A22 _ebae2.bit._A22 +#define EBAE2_A23 _ebae2.bit._A23 +__IO_EXTENDED EBCSSTR _ebcs; +#define EBCS _ebcs.byte +#define EBCS_LBE _ebcs.bit._LBE +#define EBCS_UBE _ebcs.bit._UBE +#define EBCS_WRLE _ebcs.bit._WRLE +#define EBCS_WRHE _ebcs.bit._WRHE +#define EBCS_RDE _ebcs.bit._RDE +#define EBCS_ASE _ebcs.bit._ASE +#define EBCS_ASL _ebcs.bit._ASL +__IO_EXTENDED CTRLR0STR _ctrlr0; +#define CTRLR0 _ctrlr0.word +#define CTRLR0_INIT _ctrlr0.bit._INIT +#define CTRLR0_IE _ctrlr0.bit._IE +#define CTRLR0_SIE _ctrlr0.bit._SIE +#define CTRLR0_EIE _ctrlr0.bit._EIE +#define CTRLR0_DAR _ctrlr0.bit._DAR +#define CTRLR0_CCE _ctrlr0.bit._CCE +#define CTRLR0_TEST _ctrlr0.bit._TEST +__IO_EXTENDED CTRLRL0STR _ctrlrl0; +#define CTRLRL0 _ctrlrl0.byte +#define CTRLRL0_INIT _ctrlrl0.bit._INIT +#define CTRLRL0_IE _ctrlrl0.bit._IE +#define CTRLRL0_SIE _ctrlrl0.bit._SIE +#define CTRLRL0_EIE _ctrlrl0.bit._EIE +#define CTRLRL0_DAR _ctrlrl0.bit._DAR +#define CTRLRL0_CCE _ctrlrl0.bit._CCE +#define CTRLRL0_TEST _ctrlrl0.bit._TEST +__IO_EXTENDED CTRLRH0STR _ctrlrh0; +#define CTRLRH0 _ctrlrh0.byte +__IO_EXTENDED STATR0STR _statr0; +#define STATR0 _statr0.word +#define STATR0_LEC0 _statr0.bit._LEC0 +#define STATR0_LEC1 _statr0.bit._LEC1 +#define STATR0_LEC2 _statr0.bit._LEC2 +#define STATR0_TXOK _statr0.bit._TXOK +#define STATR0_RXOK _statr0.bit._RXOK +#define STATR0_EPASS _statr0.bit._EPASS +#define STATR0_EWARN _statr0.bit._EWARN +#define STATR0_BOFF _statr0.bit._BOFF +#define STATR0_LEC _statr0.bitc._LEC +__IO_EXTENDED STATRL0STR _statrl0; +#define STATRL0 _statrl0.byte +#define STATRL0_LEC0 _statrl0.bit._LEC0 +#define STATRL0_LEC1 _statrl0.bit._LEC1 +#define STATRL0_LEC2 _statrl0.bit._LEC2 +#define STATRL0_TXOK _statrl0.bit._TXOK +#define STATRL0_RXOK _statrl0.bit._RXOK +#define STATRL0_EPASS _statrl0.bit._EPASS +#define STATRL0_EWARN _statrl0.bit._EWARN +#define STATRL0_BOFF _statrl0.bit._BOFF +#define STATRL0_LEC _statrl0.bitc._LEC +__IO_EXTENDED STATRH0STR _statrh0; +#define STATRH0 _statrh0.byte +__IO_EXTENDED ERRCNT0STR _errcnt0; +#define ERRCNT0 _errcnt0.word +#define ERRCNT0_TEC0 _errcnt0.bit._TEC0 +#define ERRCNT0_TEC1 _errcnt0.bit._TEC1 +#define ERRCNT0_TEC2 _errcnt0.bit._TEC2 +#define ERRCNT0_TEC3 _errcnt0.bit._TEC3 +#define ERRCNT0_TEC4 _errcnt0.bit._TEC4 +#define ERRCNT0_TEC5 _errcnt0.bit._TEC5 +#define ERRCNT0_TEC6 _errcnt0.bit._TEC6 +#define ERRCNT0_TEC7 _errcnt0.bit._TEC7 +#define ERRCNT0_REC0 _errcnt0.bit._REC0 +#define ERRCNT0_REC1 _errcnt0.bit._REC1 +#define ERRCNT0_REC2 _errcnt0.bit._REC2 +#define ERRCNT0_REC3 _errcnt0.bit._REC3 +#define ERRCNT0_REC4 _errcnt0.bit._REC4 +#define ERRCNT0_REC5 _errcnt0.bit._REC5 +#define ERRCNT0_REC6 _errcnt0.bit._REC6 +#define ERRCNT0_RP _errcnt0.bit._RP +#define ERRCNT0_TEC _errcnt0.bitc._TEC +#define ERRCNT0_REC _errcnt0.bitc._REC +__IO_EXTENDED ERRCNTL0STR _errcntl0; +#define ERRCNTL0 _errcntl0.byte +#define ERRCNTL0_TEC0 _errcntl0.bit._TEC0 +#define ERRCNTL0_TEC1 _errcntl0.bit._TEC1 +#define ERRCNTL0_TEC2 _errcntl0.bit._TEC2 +#define ERRCNTL0_TEC3 _errcntl0.bit._TEC3 +#define ERRCNTL0_TEC4 _errcntl0.bit._TEC4 +#define ERRCNTL0_TEC5 _errcntl0.bit._TEC5 +#define ERRCNTL0_TEC6 _errcntl0.bit._TEC6 +#define ERRCNTL0_TEC7 _errcntl0.bit._TEC7 +#define ERRCNTL0_TEC _errcntl0.bitc._TEC +__IO_EXTENDED ERRCNTH0STR _errcnth0; +#define ERRCNTH0 _errcnth0.byte +#define ERRCNTH0_REC0 _errcnth0.bit._REC0 +#define ERRCNTH0_REC1 _errcnth0.bit._REC1 +#define ERRCNTH0_REC2 _errcnth0.bit._REC2 +#define ERRCNTH0_REC3 _errcnth0.bit._REC3 +#define ERRCNTH0_REC4 _errcnth0.bit._REC4 +#define ERRCNTH0_REC5 _errcnth0.bit._REC5 +#define ERRCNTH0_REC6 _errcnth0.bit._REC6 +#define ERRCNTH0_RP _errcnth0.bit._RP +#define ERRCNTH0_REC _errcnth0.bitc._REC +__IO_EXTENDED BTR0STR _btr0; +#define BTR0 _btr0.word +#define BTR0_BRP0 _btr0.bit._BRP0 +#define BTR0_BRP1 _btr0.bit._BRP1 +#define BTR0_BRP2 _btr0.bit._BRP2 +#define BTR0_BRP3 _btr0.bit._BRP3 +#define BTR0_BRP4 _btr0.bit._BRP4 +#define BTR0_BRP5 _btr0.bit._BRP5 +#define BTR0_SJW0 _btr0.bit._SJW0 +#define BTR0_SJW1 _btr0.bit._SJW1 +#define BTR0_TSEG10 _btr0.bit._TSEG10 +#define BTR0_TSEG11 _btr0.bit._TSEG11 +#define BTR0_TSEG12 _btr0.bit._TSEG12 +#define BTR0_TSEG13 _btr0.bit._TSEG13 +#define BTR0_TSEG20 _btr0.bit._TSEG20 +#define BTR0_TSEG21 _btr0.bit._TSEG21 +#define BTR0_TSEG22 _btr0.bit._TSEG22 +#define BTR0_BRP _btr0.bitc._BRP +#define BTR0_SJW _btr0.bitc._SJW +#define BTR0_TSEG1 _btr0.bitc._TSEG1 +#define BTR0_TSEG2 _btr0.bitc._TSEG2 +__IO_EXTENDED BTRL0STR _btrl0; +#define BTRL0 _btrl0.byte +#define BTRL0_BRP0 _btrl0.bit._BRP0 +#define BTRL0_BRP1 _btrl0.bit._BRP1 +#define BTRL0_BRP2 _btrl0.bit._BRP2 +#define BTRL0_BRP3 _btrl0.bit._BRP3 +#define BTRL0_BRP4 _btrl0.bit._BRP4 +#define BTRL0_BRP5 _btrl0.bit._BRP5 +#define BTRL0_SJW0 _btrl0.bit._SJW0 +#define BTRL0_SJW1 _btrl0.bit._SJW1 +#define BTRL0_BRP _btrl0.bitc._BRP +#define BTRL0_SJW _btrl0.bitc._SJW +__IO_EXTENDED BTRH0STR _btrh0; +#define BTRH0 _btrh0.byte +#define BTRH0_TSEG10 _btrh0.bit._TSEG10 +#define BTRH0_TSEG11 _btrh0.bit._TSEG11 +#define BTRH0_TSEG12 _btrh0.bit._TSEG12 +#define BTRH0_TSEG13 _btrh0.bit._TSEG13 +#define BTRH0_TSEG20 _btrh0.bit._TSEG20 +#define BTRH0_TSEG21 _btrh0.bit._TSEG21 +#define BTRH0_TSEG22 _btrh0.bit._TSEG22 +#define BTRH0_TSEG1 _btrh0.bitc._TSEG1 +#define BTRH0_TSEG2 _btrh0.bitc._TSEG2 +__IO_EXTENDED INTR0STR _intr0; +#define INTR0 _intr0.word +#define INTR0_INTID0 _intr0.bit._INTID0 +#define INTR0_INTID1 _intr0.bit._INTID1 +#define INTR0_INTID2 _intr0.bit._INTID2 +#define INTR0_INTID3 _intr0.bit._INTID3 +#define INTR0_INTID4 _intr0.bit._INTID4 +#define INTR0_INTID5 _intr0.bit._INTID5 +#define INTR0_INTID6 _intr0.bit._INTID6 +#define INTR0_INTID7 _intr0.bit._INTID7 +#define INTR0_INTID8 _intr0.bit._INTID8 +#define INTR0_INTID9 _intr0.bit._INTID9 +#define INTR0_INTID10 _intr0.bit._INTID10 +#define INTR0_INTID11 _intr0.bit._INTID11 +#define INTR0_INTID12 _intr0.bit._INTID12 +#define INTR0_INTID13 _intr0.bit._INTID13 +#define INTR0_INTID14 _intr0.bit._INTID14 +#define INTR0_INTID15 _intr0.bit._INTID15 +#define INTR0_INTID _intr0.bitc._INTID +__IO_EXTENDED INTRL0STR _intrl0; +#define INTRL0 _intrl0.byte +#define INTRL0_INTID0 _intrl0.bit._INTID0 +#define INTRL0_INTID1 _intrl0.bit._INTID1 +#define INTRL0_INTID2 _intrl0.bit._INTID2 +#define INTRL0_INTID3 _intrl0.bit._INTID3 +#define INTRL0_INTID4 _intrl0.bit._INTID4 +#define INTRL0_INTID5 _intrl0.bit._INTID5 +#define INTRL0_INTID6 _intrl0.bit._INTID6 +#define INTRL0_INTID7 _intrl0.bit._INTID7 +__IO_EXTENDED INTRH0STR _intrh0; +#define INTRH0 _intrh0.byte +#define INTRH0_INTID8 _intrh0.bit._INTID8 +#define INTRH0_INTID9 _intrh0.bit._INTID9 +#define INTRH0_INTID10 _intrh0.bit._INTID10 +#define INTRH0_INTID11 _intrh0.bit._INTID11 +#define INTRH0_INTID12 _intrh0.bit._INTID12 +#define INTRH0_INTID13 _intrh0.bit._INTID13 +#define INTRH0_INTID14 _intrh0.bit._INTID14 +#define INTRH0_INTID15 _intrh0.bit._INTID15 +__IO_EXTENDED TESTR0STR _testr0; +#define TESTR0 _testr0.word +#define TESTR0_BASIC _testr0.bit._BASIC +#define TESTR0_SILENT _testr0.bit._SILENT +#define TESTR0_LBACK _testr0.bit._LBACK +#define TESTR0_TX0 _testr0.bit._TX0 +#define TESTR0_TX1 _testr0.bit._TX1 +#define TESTR0_RX _testr0.bit._RX +__IO_EXTENDED TESTRL0STR _testrl0; +#define TESTRL0 _testrl0.byte +#define TESTRL0_BASIC _testrl0.bit._BASIC +#define TESTRL0_SILENT _testrl0.bit._SILENT +#define TESTRL0_LBACK _testrl0.bit._LBACK +#define TESTRL0_TX0 _testrl0.bit._TX0 +#define TESTRL0_TX1 _testrl0.bit._TX1 +#define TESTRL0_RX _testrl0.bit._RX +__IO_EXTENDED TESTRH0STR _testrh0; +#define TESTRH0 _testrh0.byte +__IO_EXTENDED BRPER0STR _brper0; +#define BRPER0 _brper0.word +#define BRPER0_BRPE0 _brper0.bit._BRPE0 +#define BRPER0_BRPE1 _brper0.bit._BRPE1 +#define BRPER0_BRPE2 _brper0.bit._BRPE2 +#define BRPER0_BRPE3 _brper0.bit._BRPE3 +#define BRPER0_BRPE _brper0.bitc._BRPE +__IO_EXTENDED BRPERL0STR _brperl0; +#define BRPERL0 _brperl0.byte +#define BRPERL0_BRPE0 _brperl0.bit._BRPE0 +#define BRPERL0_BRPE1 _brperl0.bit._BRPE1 +#define BRPERL0_BRPE2 _brperl0.bit._BRPE2 +#define BRPERL0_BRPE3 _brperl0.bit._BRPE3 +#define BRPERL0_BRPE _brperl0.bitc._BRPE +__IO_EXTENDED BRPERH0STR _brperh0; +#define BRPERH0 _brperh0.byte +__IO_EXTENDED IF1CREQ0STR _if1creq0; +#define IF1CREQ0 _if1creq0.word +#define IF1CREQ0_MSGN0 _if1creq0.bit._MSGN0 +#define IF1CREQ0_MSGN1 _if1creq0.bit._MSGN1 +#define IF1CREQ0_MSGN2 _if1creq0.bit._MSGN2 +#define IF1CREQ0_MSGN3 _if1creq0.bit._MSGN3 +#define IF1CREQ0_MSGN4 _if1creq0.bit._MSGN4 +#define IF1CREQ0_MSGN5 _if1creq0.bit._MSGN5 +#define IF1CREQ0_MSGN6 _if1creq0.bit._MSGN6 +#define IF1CREQ0_MSGN7 _if1creq0.bit._MSGN7 +#define IF1CREQ0_BUSY _if1creq0.bit._BUSY +__IO_EXTENDED IF1CREQL0STR _if1creql0; +#define IF1CREQL0 _if1creql0.byte +#define IF1CREQL0_MSGN0 _if1creql0.bit._MSGN0 +#define IF1CREQL0_MSGN1 _if1creql0.bit._MSGN1 +#define IF1CREQL0_MSGN2 _if1creql0.bit._MSGN2 +#define IF1CREQL0_MSGN3 _if1creql0.bit._MSGN3 +#define IF1CREQL0_MSGN4 _if1creql0.bit._MSGN4 +#define IF1CREQL0_MSGN5 _if1creql0.bit._MSGN5 +#define IF1CREQL0_MSGN6 _if1creql0.bit._MSGN6 +#define IF1CREQL0_MSGN7 _if1creql0.bit._MSGN7 +__IO_EXTENDED IF1CREQH0STR _if1creqh0; +#define IF1CREQH0 _if1creqh0.byte +#define IF1CREQH0_BUSY _if1creqh0.bit._BUSY +__IO_EXTENDED IF1CMSK0STR _if1cmsk0; +#define IF1CMSK0 _if1cmsk0.word +#define IF1CMSK0_DATAB _if1cmsk0.bit._DATAB +#define IF1CMSK0_DATAA _if1cmsk0.bit._DATAA +#define IF1CMSK0_TXREQ _if1cmsk0.bit._TXREQ +#define IF1CMSK0_CIP _if1cmsk0.bit._CIP +#define IF1CMSK0_CONTROL _if1cmsk0.bit._CONTROL +#define IF1CMSK0_ARB _if1cmsk0.bit._ARB +#define IF1CMSK0_MASK _if1cmsk0.bit._MASK +#define IF1CMSK0_WRRD _if1cmsk0.bit._WRRD +__IO_EXTENDED IF1CMSKL0STR _if1cmskl0; +#define IF1CMSKL0 _if1cmskl0.byte +#define IF1CMSKL0_DATAB _if1cmskl0.bit._DATAB +#define IF1CMSKL0_DATAA _if1cmskl0.bit._DATAA +#define IF1CMSKL0_TXREQ _if1cmskl0.bit._TXREQ +#define IF1CMSKL0_CIP _if1cmskl0.bit._CIP +#define IF1CMSKL0_CONTROL _if1cmskl0.bit._CONTROL +#define IF1CMSKL0_ARB _if1cmskl0.bit._ARB +#define IF1CMSKL0_MASK _if1cmskl0.bit._MASK +#define IF1CMSKL0_WRRD _if1cmskl0.bit._WRRD +__IO_EXTENDED IF1CMSKH0STR _if1cmskh0; +#define IF1CMSKH0 _if1cmskh0.byte +__IO_EXTENDED IF1MSK0STR _if1msk0; +#define IF1MSK0 _if1msk0.lword +#define IF1MSK0_MSK0 _if1msk0.bit._MSK0 +#define IF1MSK0_MSK1 _if1msk0.bit._MSK1 +#define IF1MSK0_MSK2 _if1msk0.bit._MSK2 +#define IF1MSK0_MSK3 _if1msk0.bit._MSK3 +#define IF1MSK0_MSK4 _if1msk0.bit._MSK4 +#define IF1MSK0_MSK5 _if1msk0.bit._MSK5 +#define IF1MSK0_MSK6 _if1msk0.bit._MSK6 +#define IF1MSK0_MSK7 _if1msk0.bit._MSK7 +#define IF1MSK0_MSK8 _if1msk0.bit._MSK8 +#define IF1MSK0_MSK9 _if1msk0.bit._MSK9 +#define IF1MSK0_MSK10 _if1msk0.bit._MSK10 +#define IF1MSK0_MSK11 _if1msk0.bit._MSK11 +#define IF1MSK0_MSK12 _if1msk0.bit._MSK12 +#define IF1MSK0_MSK13 _if1msk0.bit._MSK13 +#define IF1MSK0_MSK14 _if1msk0.bit._MSK14 +#define IF1MSK0_MSK15 _if1msk0.bit._MSK15 +#define IF1MSK0_MSK16 _if1msk0.bit._MSK16 +#define IF1MSK0_MSK17 _if1msk0.bit._MSK17 +#define IF1MSK0_MSK18 _if1msk0.bit._MSK18 +#define IF1MSK0_MSK19 _if1msk0.bit._MSK19 +#define IF1MSK0_MSK20 _if1msk0.bit._MSK20 +#define IF1MSK0_MSK21 _if1msk0.bit._MSK21 +#define IF1MSK0_MSK22 _if1msk0.bit._MSK22 +#define IF1MSK0_MSK23 _if1msk0.bit._MSK23 +#define IF1MSK0_MSK24 _if1msk0.bit._MSK24 +#define IF1MSK0_MSK25 _if1msk0.bit._MSK25 +#define IF1MSK0_MSK26 _if1msk0.bit._MSK26 +#define IF1MSK0_MSK27 _if1msk0.bit._MSK27 +#define IF1MSK0_MSK28 _if1msk0.bit._MSK28 +#define IF1MSK0_MDIR _if1msk0.bit._MDIR +#define IF1MSK0_MXTD _if1msk0.bit._MXTD +#define IF1MSK0_MSK _if1msk0.bitc._MSK +__IO_EXTENDED IF1MSK10STR _if1msk10; +#define IF1MSK10 _if1msk10.word +#define IF1MSK10_MSK0 _if1msk10.bit._MSK0 +#define IF1MSK10_MSK1 _if1msk10.bit._MSK1 +#define IF1MSK10_MSK2 _if1msk10.bit._MSK2 +#define IF1MSK10_MSK3 _if1msk10.bit._MSK3 +#define IF1MSK10_MSK4 _if1msk10.bit._MSK4 +#define IF1MSK10_MSK5 _if1msk10.bit._MSK5 +#define IF1MSK10_MSK6 _if1msk10.bit._MSK6 +#define IF1MSK10_MSK7 _if1msk10.bit._MSK7 +#define IF1MSK10_MSK8 _if1msk10.bit._MSK8 +#define IF1MSK10_MSK9 _if1msk10.bit._MSK9 +#define IF1MSK10_MSK10 _if1msk10.bit._MSK10 +#define IF1MSK10_MSK11 _if1msk10.bit._MSK11 +#define IF1MSK10_MSK12 _if1msk10.bit._MSK12 +#define IF1MSK10_MSK13 _if1msk10.bit._MSK13 +#define IF1MSK10_MSK14 _if1msk10.bit._MSK14 +#define IF1MSK10_MSK15 _if1msk10.bit._MSK15 +__IO_EXTENDED IF1MSK1L0STR _if1msk1l0; +#define IF1MSK1L0 _if1msk1l0.byte +#define IF1MSK1L0_MSK0 _if1msk1l0.bit._MSK0 +#define IF1MSK1L0_MSK1 _if1msk1l0.bit._MSK1 +#define IF1MSK1L0_MSK2 _if1msk1l0.bit._MSK2 +#define IF1MSK1L0_MSK3 _if1msk1l0.bit._MSK3 +#define IF1MSK1L0_MSK4 _if1msk1l0.bit._MSK4 +#define IF1MSK1L0_MSK5 _if1msk1l0.bit._MSK5 +#define IF1MSK1L0_MSK6 _if1msk1l0.bit._MSK6 +#define IF1MSK1L0_MSK7 _if1msk1l0.bit._MSK7 +__IO_EXTENDED IF1MSK1H0STR _if1msk1h0; +#define IF1MSK1H0 _if1msk1h0.byte +#define IF1MSK1H0_MSK8 _if1msk1h0.bit._MSK8 +#define IF1MSK1H0_MSK9 _if1msk1h0.bit._MSK9 +#define IF1MSK1H0_MSK10 _if1msk1h0.bit._MSK10 +#define IF1MSK1H0_MSK11 _if1msk1h0.bit._MSK11 +#define IF1MSK1H0_MSK12 _if1msk1h0.bit._MSK12 +#define IF1MSK1H0_MSK13 _if1msk1h0.bit._MSK13 +#define IF1MSK1H0_MSK14 _if1msk1h0.bit._MSK14 +#define IF1MSK1H0_MSK15 _if1msk1h0.bit._MSK15 +__IO_EXTENDED IF1MSK20STR _if1msk20; +#define IF1MSK20 _if1msk20.word +#define IF1MSK20_MSK16 _if1msk20.bit._MSK16 +#define IF1MSK20_MSK17 _if1msk20.bit._MSK17 +#define IF1MSK20_MSK18 _if1msk20.bit._MSK18 +#define IF1MSK20_MSK19 _if1msk20.bit._MSK19 +#define IF1MSK20_MSK20 _if1msk20.bit._MSK20 +#define IF1MSK20_MSK21 _if1msk20.bit._MSK21 +#define IF1MSK20_MSK22 _if1msk20.bit._MSK22 +#define IF1MSK20_MSK23 _if1msk20.bit._MSK23 +#define IF1MSK20_MSK24 _if1msk20.bit._MSK24 +#define IF1MSK20_MSK25 _if1msk20.bit._MSK25 +#define IF1MSK20_MSK26 _if1msk20.bit._MSK26 +#define IF1MSK20_MSK27 _if1msk20.bit._MSK27 +#define IF1MSK20_MSK28 _if1msk20.bit._MSK28 +#define IF1MSK20_MDIR _if1msk20.bit._MDIR +#define IF1MSK20_MXTD _if1msk20.bit._MXTD +__IO_EXTENDED IF1MSK2L0STR _if1msk2l0; +#define IF1MSK2L0 _if1msk2l0.byte +#define IF1MSK2L0_MSK16 _if1msk2l0.bit._MSK16 +#define IF1MSK2L0_MSK17 _if1msk2l0.bit._MSK17 +#define IF1MSK2L0_MSK18 _if1msk2l0.bit._MSK18 +#define IF1MSK2L0_MSK19 _if1msk2l0.bit._MSK19 +#define IF1MSK2L0_MSK20 _if1msk2l0.bit._MSK20 +#define IF1MSK2L0_MSK21 _if1msk2l0.bit._MSK21 +#define IF1MSK2L0_MSK22 _if1msk2l0.bit._MSK22 +#define IF1MSK2L0_MSK23 _if1msk2l0.bit._MSK23 +__IO_EXTENDED IF1MSK2H0STR _if1msk2h0; +#define IF1MSK2H0 _if1msk2h0.byte +#define IF1MSK2H0_MSK24 _if1msk2h0.bit._MSK24 +#define IF1MSK2H0_MSK25 _if1msk2h0.bit._MSK25 +#define IF1MSK2H0_MSK26 _if1msk2h0.bit._MSK26 +#define IF1MSK2H0_MSK27 _if1msk2h0.bit._MSK27 +#define IF1MSK2H0_MSK28 _if1msk2h0.bit._MSK28 +#define IF1MSK2H0_MDIR _if1msk2h0.bit._MDIR +#define IF1MSK2H0_MXTD _if1msk2h0.bit._MXTD +__IO_EXTENDED IF1ARB0STR _if1arb0; +#define IF1ARB0 _if1arb0.lword +#define IF1ARB0_ID0 _if1arb0.bit._ID0 +#define IF1ARB0_ID1 _if1arb0.bit._ID1 +#define IF1ARB0_ID2 _if1arb0.bit._ID2 +#define IF1ARB0_ID3 _if1arb0.bit._ID3 +#define IF1ARB0_ID4 _if1arb0.bit._ID4 +#define IF1ARB0_ID5 _if1arb0.bit._ID5 +#define IF1ARB0_ID6 _if1arb0.bit._ID6 +#define IF1ARB0_ID7 _if1arb0.bit._ID7 +#define IF1ARB0_ID8 _if1arb0.bit._ID8 +#define IF1ARB0_ID9 _if1arb0.bit._ID9 +#define IF1ARB0_ID10 _if1arb0.bit._ID10 +#define IF1ARB0_ID11 _if1arb0.bit._ID11 +#define IF1ARB0_ID12 _if1arb0.bit._ID12 +#define IF1ARB0_ID13 _if1arb0.bit._ID13 +#define IF1ARB0_ID14 _if1arb0.bit._ID14 +#define IF1ARB0_ID15 _if1arb0.bit._ID15 +#define IF1ARB0_ID16 _if1arb0.bit._ID16 +#define IF1ARB0_ID17 _if1arb0.bit._ID17 +#define IF1ARB0_ID18 _if1arb0.bit._ID18 +#define IF1ARB0_ID19 _if1arb0.bit._ID19 +#define IF1ARB0_ID20 _if1arb0.bit._ID20 +#define IF1ARB0_ID21 _if1arb0.bit._ID21 +#define IF1ARB0_ID22 _if1arb0.bit._ID22 +#define IF1ARB0_ID23 _if1arb0.bit._ID23 +#define IF1ARB0_ID24 _if1arb0.bit._ID24 +#define IF1ARB0_ID25 _if1arb0.bit._ID25 +#define IF1ARB0_ID26 _if1arb0.bit._ID26 +#define IF1ARB0_ID27 _if1arb0.bit._ID27 +#define IF1ARB0_ID28 _if1arb0.bit._ID28 +#define IF1ARB0_DIR _if1arb0.bit._DIR +#define IF1ARB0_XTD _if1arb0.bit._XTD +#define IF1ARB0_MSGVAL _if1arb0.bit._MSGVAL +#define IF1ARB0_ID _if1arb0.bitc._ID +__IO_EXTENDED IF1ARB10STR _if1arb10; +#define IF1ARB10 _if1arb10.word +#define IF1ARB10_ID0 _if1arb10.bit._ID0 +#define IF1ARB10_ID1 _if1arb10.bit._ID1 +#define IF1ARB10_ID2 _if1arb10.bit._ID2 +#define IF1ARB10_ID3 _if1arb10.bit._ID3 +#define IF1ARB10_ID4 _if1arb10.bit._ID4 +#define IF1ARB10_ID5 _if1arb10.bit._ID5 +#define IF1ARB10_ID6 _if1arb10.bit._ID6 +#define IF1ARB10_ID7 _if1arb10.bit._ID7 +#define IF1ARB10_ID8 _if1arb10.bit._ID8 +#define IF1ARB10_ID9 _if1arb10.bit._ID9 +#define IF1ARB10_ID10 _if1arb10.bit._ID10 +#define IF1ARB10_ID11 _if1arb10.bit._ID11 +#define IF1ARB10_ID12 _if1arb10.bit._ID12 +#define IF1ARB10_ID13 _if1arb10.bit._ID13 +#define IF1ARB10_ID14 _if1arb10.bit._ID14 +#define IF1ARB10_ID15 _if1arb10.bit._ID15 +__IO_EXTENDED IF1ARB1L0STR _if1arb1l0; +#define IF1ARB1L0 _if1arb1l0.byte +#define IF1ARB1L0_ID0 _if1arb1l0.bit._ID0 +#define IF1ARB1L0_ID1 _if1arb1l0.bit._ID1 +#define IF1ARB1L0_ID2 _if1arb1l0.bit._ID2 +#define IF1ARB1L0_ID3 _if1arb1l0.bit._ID3 +#define IF1ARB1L0_ID4 _if1arb1l0.bit._ID4 +#define IF1ARB1L0_ID5 _if1arb1l0.bit._ID5 +#define IF1ARB1L0_ID6 _if1arb1l0.bit._ID6 +#define IF1ARB1L0_ID7 _if1arb1l0.bit._ID7 +__IO_EXTENDED IF1ARB1H0STR _if1arb1h0; +#define IF1ARB1H0 _if1arb1h0.byte +#define IF1ARB1H0_ID8 _if1arb1h0.bit._ID8 +#define IF1ARB1H0_ID9 _if1arb1h0.bit._ID9 +#define IF1ARB1H0_ID10 _if1arb1h0.bit._ID10 +#define IF1ARB1H0_ID11 _if1arb1h0.bit._ID11 +#define IF1ARB1H0_ID12 _if1arb1h0.bit._ID12 +#define IF1ARB1H0_ID13 _if1arb1h0.bit._ID13 +#define IF1ARB1H0_ID14 _if1arb1h0.bit._ID14 +#define IF1ARB1H0_ID15 _if1arb1h0.bit._ID15 +__IO_EXTENDED IF1ARB20STR _if1arb20; +#define IF1ARB20 _if1arb20.word +#define IF1ARB20_ID16 _if1arb20.bit._ID16 +#define IF1ARB20_ID17 _if1arb20.bit._ID17 +#define IF1ARB20_ID18 _if1arb20.bit._ID18 +#define IF1ARB20_ID19 _if1arb20.bit._ID19 +#define IF1ARB20_ID20 _if1arb20.bit._ID20 +#define IF1ARB20_ID21 _if1arb20.bit._ID21 +#define IF1ARB20_ID22 _if1arb20.bit._ID22 +#define IF1ARB20_ID23 _if1arb20.bit._ID23 +#define IF1ARB20_ID24 _if1arb20.bit._ID24 +#define IF1ARB20_ID25 _if1arb20.bit._ID25 +#define IF1ARB20_ID26 _if1arb20.bit._ID26 +#define IF1ARB20_ID27 _if1arb20.bit._ID27 +#define IF1ARB20_ID28 _if1arb20.bit._ID28 +#define IF1ARB20_DIR _if1arb20.bit._DIR +#define IF1ARB20_XTD _if1arb20.bit._XTD +#define IF1ARB20_MSGVAL _if1arb20.bit._MSGVAL +__IO_EXTENDED IF1ARB2L0STR _if1arb2l0; +#define IF1ARB2L0 _if1arb2l0.byte +#define IF1ARB2L0_ID16 _if1arb2l0.bit._ID16 +#define IF1ARB2L0_ID17 _if1arb2l0.bit._ID17 +#define IF1ARB2L0_ID18 _if1arb2l0.bit._ID18 +#define IF1ARB2L0_ID19 _if1arb2l0.bit._ID19 +#define IF1ARB2L0_ID20 _if1arb2l0.bit._ID20 +#define IF1ARB2L0_ID21 _if1arb2l0.bit._ID21 +#define IF1ARB2L0_ID22 _if1arb2l0.bit._ID22 +#define IF1ARB2L0_ID23 _if1arb2l0.bit._ID23 +__IO_EXTENDED IF1ARB2H0STR _if1arb2h0; +#define IF1ARB2H0 _if1arb2h0.byte +#define IF1ARB2H0_ID24 _if1arb2h0.bit._ID24 +#define IF1ARB2H0_ID25 _if1arb2h0.bit._ID25 +#define IF1ARB2H0_ID26 _if1arb2h0.bit._ID26 +#define IF1ARB2H0_ID27 _if1arb2h0.bit._ID27 +#define IF1ARB2H0_ID28 _if1arb2h0.bit._ID28 +#define IF1ARB2H0_DIR _if1arb2h0.bit._DIR +#define IF1ARB2H0_XTD _if1arb2h0.bit._XTD +#define IF1ARB2H0_MSGVAL _if1arb2h0.bit._MSGVAL +__IO_EXTENDED IF1MCTR0STR _if1mctr0; +#define IF1MCTR0 _if1mctr0.word +#define IF1MCTR0_DLC0 _if1mctr0.bit._DLC0 +#define IF1MCTR0_DLC1 _if1mctr0.bit._DLC1 +#define IF1MCTR0_DLC2 _if1mctr0.bit._DLC2 +#define IF1MCTR0_DLC3 _if1mctr0.bit._DLC3 +#define IF1MCTR0_EOB _if1mctr0.bit._EOB +#define IF1MCTR0_TXRQST _if1mctr0.bit._TXRQST +#define IF1MCTR0_RMTEN _if1mctr0.bit._RMTEN +#define IF1MCTR0_RXIE _if1mctr0.bit._RXIE +#define IF1MCTR0_TXIE _if1mctr0.bit._TXIE +#define IF1MCTR0_UMASK _if1mctr0.bit._UMASK +#define IF1MCTR0_INTPND _if1mctr0.bit._INTPND +#define IF1MCTR0_MSGLST _if1mctr0.bit._MSGLST +#define IF1MCTR0_NEWDAT _if1mctr0.bit._NEWDAT +#define IF1MCTR0_DLC _if1mctr0.bitc._DLC +__IO_EXTENDED IF1MCTRL0STR _if1mctrl0; +#define IF1MCTRL0 _if1mctrl0.byte +#define IF1MCTRL0_DLC0 _if1mctrl0.bit._DLC0 +#define IF1MCTRL0_DLC1 _if1mctrl0.bit._DLC1 +#define IF1MCTRL0_DLC2 _if1mctrl0.bit._DLC2 +#define IF1MCTRL0_DLC3 _if1mctrl0.bit._DLC3 +#define IF1MCTRL0_EOB _if1mctrl0.bit._EOB +#define IF1MCTRL0_DLC _if1mctrl0.bitc._DLC +__IO_EXTENDED IF1MCTRH0STR _if1mctrh0; +#define IF1MCTRH0 _if1mctrh0.byte +#define IF1MCTRH0_TXRQST _if1mctrh0.bit._TXRQST +#define IF1MCTRH0_RMTEN _if1mctrh0.bit._RMTEN +#define IF1MCTRH0_RXIE _if1mctrh0.bit._RXIE +#define IF1MCTRH0_TXIE _if1mctrh0.bit._TXIE +#define IF1MCTRH0_UMASK _if1mctrh0.bit._UMASK +#define IF1MCTRH0_INTPND _if1mctrh0.bit._INTPND +#define IF1MCTRH0_MSGLST _if1mctrh0.bit._MSGLST +#define IF1MCTRH0_NEWDAT _if1mctrh0.bit._NEWDAT +__IO_EXTENDED IF1DTA0STR _if1dta0; +#define IF1DTA0 _if1dta0.lword +__IO_EXTENDED IF1DTA10STR _if1dta10; +#define IF1DTA10 _if1dta10.word +__IO_EXTENDED IF1DTA1L0STR _if1dta1l0; +#define IF1DTA1L0 _if1dta1l0.byte +__IO_EXTENDED IF1DTA1H0STR _if1dta1h0; +#define IF1DTA1H0 _if1dta1h0.byte +__IO_EXTENDED IF1DTA20STR _if1dta20; +#define IF1DTA20 _if1dta20.word +__IO_EXTENDED IF1DTA2L0STR _if1dta2l0; +#define IF1DTA2L0 _if1dta2l0.byte +__IO_EXTENDED IF1DTA2H0STR _if1dta2h0; +#define IF1DTA2H0 _if1dta2h0.byte +__IO_EXTENDED IF1DTB0STR _if1dtb0; +#define IF1DTB0 _if1dtb0.lword +__IO_EXTENDED IF1DTB10STR _if1dtb10; +#define IF1DTB10 _if1dtb10.word +__IO_EXTENDED IF1DTB1L0STR _if1dtb1l0; +#define IF1DTB1L0 _if1dtb1l0.byte +__IO_EXTENDED IF1DTB1H0STR _if1dtb1h0; +#define IF1DTB1H0 _if1dtb1h0.byte +__IO_EXTENDED IF1DTB20STR _if1dtb20; +#define IF1DTB20 _if1dtb20.word +__IO_EXTENDED IF1DTB2L0STR _if1dtb2l0; +#define IF1DTB2L0 _if1dtb2l0.byte +__IO_EXTENDED IF1DTB2H0STR _if1dtb2h0; +#define IF1DTB2H0 _if1dtb2h0.byte +__IO_EXTENDED IF2CREQ0STR _if2creq0; +#define IF2CREQ0 _if2creq0.word +#define IF2CREQ0_MSGN0 _if2creq0.bit._MSGN0 +#define IF2CREQ0_MSGN1 _if2creq0.bit._MSGN1 +#define IF2CREQ0_MSGN2 _if2creq0.bit._MSGN2 +#define IF2CREQ0_MSGN3 _if2creq0.bit._MSGN3 +#define IF2CREQ0_MSGN4 _if2creq0.bit._MSGN4 +#define IF2CREQ0_MSGN5 _if2creq0.bit._MSGN5 +#define IF2CREQ0_MSGN6 _if2creq0.bit._MSGN6 +#define IF2CREQ0_MSGN7 _if2creq0.bit._MSGN7 +#define IF2CREQ0_BUSY _if2creq0.bit._BUSY +__IO_EXTENDED IF2CREQL0STR _if2creql0; +#define IF2CREQL0 _if2creql0.byte +#define IF2CREQL0_MSGN0 _if2creql0.bit._MSGN0 +#define IF2CREQL0_MSGN1 _if2creql0.bit._MSGN1 +#define IF2CREQL0_MSGN2 _if2creql0.bit._MSGN2 +#define IF2CREQL0_MSGN3 _if2creql0.bit._MSGN3 +#define IF2CREQL0_MSGN4 _if2creql0.bit._MSGN4 +#define IF2CREQL0_MSGN5 _if2creql0.bit._MSGN5 +#define IF2CREQL0_MSGN6 _if2creql0.bit._MSGN6 +#define IF2CREQL0_MSGN7 _if2creql0.bit._MSGN7 +__IO_EXTENDED IF2CREQH0STR _if2creqh0; +#define IF2CREQH0 _if2creqh0.byte +#define IF2CREQH0_BUSY _if2creqh0.bit._BUSY +__IO_EXTENDED IF2CMSK0STR _if2cmsk0; +#define IF2CMSK0 _if2cmsk0.word +#define IF2CMSK0_DATAB _if2cmsk0.bit._DATAB +#define IF2CMSK0_DATAA _if2cmsk0.bit._DATAA +#define IF2CMSK0_TXREQ _if2cmsk0.bit._TXREQ +#define IF2CMSK0_CIP _if2cmsk0.bit._CIP +#define IF2CMSK0_CONTROL _if2cmsk0.bit._CONTROL +#define IF2CMSK0_ARB _if2cmsk0.bit._ARB +#define IF2CMSK0_MASK _if2cmsk0.bit._MASK +#define IF2CMSK0_WRRD _if2cmsk0.bit._WRRD +__IO_EXTENDED IF2CMSKL0STR _if2cmskl0; +#define IF2CMSKL0 _if2cmskl0.byte +#define IF2CMSKL0_DATAB _if2cmskl0.bit._DATAB +#define IF2CMSKL0_DATAA _if2cmskl0.bit._DATAA +#define IF2CMSKL0_TXREQ _if2cmskl0.bit._TXREQ +#define IF2CMSKL0_CIP _if2cmskl0.bit._CIP +#define IF2CMSKL0_CONTROL _if2cmskl0.bit._CONTROL +#define IF2CMSKL0_ARB _if2cmskl0.bit._ARB +#define IF2CMSKL0_MASK _if2cmskl0.bit._MASK +#define IF2CMSKL0_WRRD _if2cmskl0.bit._WRRD +__IO_EXTENDED IF2CMSKH0STR _if2cmskh0; +#define IF2CMSKH0 _if2cmskh0.byte +__IO_EXTENDED IF2MSK0STR _if2msk0; +#define IF2MSK0 _if2msk0.lword +#define IF2MSK0_MSK0 _if2msk0.bit._MSK0 +#define IF2MSK0_MSK1 _if2msk0.bit._MSK1 +#define IF2MSK0_MSK2 _if2msk0.bit._MSK2 +#define IF2MSK0_MSK3 _if2msk0.bit._MSK3 +#define IF2MSK0_MSK4 _if2msk0.bit._MSK4 +#define IF2MSK0_MSK5 _if2msk0.bit._MSK5 +#define IF2MSK0_MSK6 _if2msk0.bit._MSK6 +#define IF2MSK0_MSK7 _if2msk0.bit._MSK7 +#define IF2MSK0_MSK8 _if2msk0.bit._MSK8 +#define IF2MSK0_MSK9 _if2msk0.bit._MSK9 +#define IF2MSK0_MSK10 _if2msk0.bit._MSK10 +#define IF2MSK0_MSK11 _if2msk0.bit._MSK11 +#define IF2MSK0_MSK12 _if2msk0.bit._MSK12 +#define IF2MSK0_MSK13 _if2msk0.bit._MSK13 +#define IF2MSK0_MSK14 _if2msk0.bit._MSK14 +#define IF2MSK0_MSK15 _if2msk0.bit._MSK15 +#define IF2MSK0_MSK16 _if2msk0.bit._MSK16 +#define IF2MSK0_MSK17 _if2msk0.bit._MSK17 +#define IF2MSK0_MSK18 _if2msk0.bit._MSK18 +#define IF2MSK0_MSK19 _if2msk0.bit._MSK19 +#define IF2MSK0_MSK20 _if2msk0.bit._MSK20 +#define IF2MSK0_MSK21 _if2msk0.bit._MSK21 +#define IF2MSK0_MSK22 _if2msk0.bit._MSK22 +#define IF2MSK0_MSK23 _if2msk0.bit._MSK23 +#define IF2MSK0_MSK24 _if2msk0.bit._MSK24 +#define IF2MSK0_MSK25 _if2msk0.bit._MSK25 +#define IF2MSK0_MSK26 _if2msk0.bit._MSK26 +#define IF2MSK0_MSK27 _if2msk0.bit._MSK27 +#define IF2MSK0_MSK28 _if2msk0.bit._MSK28 +#define IF2MSK0_MDIR _if2msk0.bit._MDIR +#define IF2MSK0_MXTD _if2msk0.bit._MXTD +#define IF2MSK0_MSK _if2msk0.bitc._MSK +__IO_EXTENDED IF2MSK10STR _if2msk10; +#define IF2MSK10 _if2msk10.word +#define IF2MSK10_MSK0 _if2msk10.bit._MSK0 +#define IF2MSK10_MSK1 _if2msk10.bit._MSK1 +#define IF2MSK10_MSK2 _if2msk10.bit._MSK2 +#define IF2MSK10_MSK3 _if2msk10.bit._MSK3 +#define IF2MSK10_MSK4 _if2msk10.bit._MSK4 +#define IF2MSK10_MSK5 _if2msk10.bit._MSK5 +#define IF2MSK10_MSK6 _if2msk10.bit._MSK6 +#define IF2MSK10_MSK7 _if2msk10.bit._MSK7 +#define IF2MSK10_MSK8 _if2msk10.bit._MSK8 +#define IF2MSK10_MSK9 _if2msk10.bit._MSK9 +#define IF2MSK10_MSK10 _if2msk10.bit._MSK10 +#define IF2MSK10_MSK11 _if2msk10.bit._MSK11 +#define IF2MSK10_MSK12 _if2msk10.bit._MSK12 +#define IF2MSK10_MSK13 _if2msk10.bit._MSK13 +#define IF2MSK10_MSK14 _if2msk10.bit._MSK14 +#define IF2MSK10_MSK15 _if2msk10.bit._MSK15 +__IO_EXTENDED IF2MSK1L0STR _if2msk1l0; +#define IF2MSK1L0 _if2msk1l0.byte +#define IF2MSK1L0_MSK0 _if2msk1l0.bit._MSK0 +#define IF2MSK1L0_MSK1 _if2msk1l0.bit._MSK1 +#define IF2MSK1L0_MSK2 _if2msk1l0.bit._MSK2 +#define IF2MSK1L0_MSK3 _if2msk1l0.bit._MSK3 +#define IF2MSK1L0_MSK4 _if2msk1l0.bit._MSK4 +#define IF2MSK1L0_MSK5 _if2msk1l0.bit._MSK5 +#define IF2MSK1L0_MSK6 _if2msk1l0.bit._MSK6 +#define IF2MSK1L0_MSK7 _if2msk1l0.bit._MSK7 +__IO_EXTENDED IF2MSK1H0STR _if2msk1h0; +#define IF2MSK1H0 _if2msk1h0.byte +#define IF2MSK1H0_MSK8 _if2msk1h0.bit._MSK8 +#define IF2MSK1H0_MSK9 _if2msk1h0.bit._MSK9 +#define IF2MSK1H0_MSK10 _if2msk1h0.bit._MSK10 +#define IF2MSK1H0_MSK11 _if2msk1h0.bit._MSK11 +#define IF2MSK1H0_MSK12 _if2msk1h0.bit._MSK12 +#define IF2MSK1H0_MSK13 _if2msk1h0.bit._MSK13 +#define IF2MSK1H0_MSK14 _if2msk1h0.bit._MSK14 +#define IF2MSK1H0_MSK15 _if2msk1h0.bit._MSK15 +__IO_EXTENDED IF2MSK20STR _if2msk20; +#define IF2MSK20 _if2msk20.word +#define IF2MSK20_MSK16 _if2msk20.bit._MSK16 +#define IF2MSK20_MSK17 _if2msk20.bit._MSK17 +#define IF2MSK20_MSK18 _if2msk20.bit._MSK18 +#define IF2MSK20_MSK19 _if2msk20.bit._MSK19 +#define IF2MSK20_MSK20 _if2msk20.bit._MSK20 +#define IF2MSK20_MSK21 _if2msk20.bit._MSK21 +#define IF2MSK20_MSK22 _if2msk20.bit._MSK22 +#define IF2MSK20_MSK23 _if2msk20.bit._MSK23 +#define IF2MSK20_MSK24 _if2msk20.bit._MSK24 +#define IF2MSK20_MSK25 _if2msk20.bit._MSK25 +#define IF2MSK20_MSK26 _if2msk20.bit._MSK26 +#define IF2MSK20_MSK27 _if2msk20.bit._MSK27 +#define IF2MSK20_MSK28 _if2msk20.bit._MSK28 +#define IF2MSK20_MDIR _if2msk20.bit._MDIR +#define IF2MSK20_MXTD _if2msk20.bit._MXTD +__IO_EXTENDED IF2MSK2L0STR _if2msk2l0; +#define IF2MSK2L0 _if2msk2l0.byte +#define IF2MSK2L0_MSK16 _if2msk2l0.bit._MSK16 +#define IF2MSK2L0_MSK17 _if2msk2l0.bit._MSK17 +#define IF2MSK2L0_MSK18 _if2msk2l0.bit._MSK18 +#define IF2MSK2L0_MSK19 _if2msk2l0.bit._MSK19 +#define IF2MSK2L0_MSK20 _if2msk2l0.bit._MSK20 +#define IF2MSK2L0_MSK21 _if2msk2l0.bit._MSK21 +#define IF2MSK2L0_MSK22 _if2msk2l0.bit._MSK22 +#define IF2MSK2L0_MSK23 _if2msk2l0.bit._MSK23 +__IO_EXTENDED IF2MSK2H0STR _if2msk2h0; +#define IF2MSK2H0 _if2msk2h0.byte +#define IF2MSK2H0_MSK24 _if2msk2h0.bit._MSK24 +#define IF2MSK2H0_MSK25 _if2msk2h0.bit._MSK25 +#define IF2MSK2H0_MSK26 _if2msk2h0.bit._MSK26 +#define IF2MSK2H0_MSK27 _if2msk2h0.bit._MSK27 +#define IF2MSK2H0_MSK28 _if2msk2h0.bit._MSK28 +#define IF2MSK2H0_MDIR _if2msk2h0.bit._MDIR +#define IF2MSK2H0_MXTD _if2msk2h0.bit._MXTD +__IO_EXTENDED IF2ARB0STR _if2arb0; +#define IF2ARB0 _if2arb0.lword +#define IF2ARB0_ID0 _if2arb0.bit._ID0 +#define IF2ARB0_ID1 _if2arb0.bit._ID1 +#define IF2ARB0_ID2 _if2arb0.bit._ID2 +#define IF2ARB0_ID3 _if2arb0.bit._ID3 +#define IF2ARB0_ID4 _if2arb0.bit._ID4 +#define IF2ARB0_ID5 _if2arb0.bit._ID5 +#define IF2ARB0_ID6 _if2arb0.bit._ID6 +#define IF2ARB0_ID7 _if2arb0.bit._ID7 +#define IF2ARB0_ID8 _if2arb0.bit._ID8 +#define IF2ARB0_ID9 _if2arb0.bit._ID9 +#define IF2ARB0_ID10 _if2arb0.bit._ID10 +#define IF2ARB0_ID11 _if2arb0.bit._ID11 +#define IF2ARB0_ID12 _if2arb0.bit._ID12 +#define IF2ARB0_ID13 _if2arb0.bit._ID13 +#define IF2ARB0_ID14 _if2arb0.bit._ID14 +#define IF2ARB0_ID15 _if2arb0.bit._ID15 +#define IF2ARB0_ID16 _if2arb0.bit._ID16 +#define IF2ARB0_ID17 _if2arb0.bit._ID17 +#define IF2ARB0_ID18 _if2arb0.bit._ID18 +#define IF2ARB0_ID19 _if2arb0.bit._ID19 +#define IF2ARB0_ID20 _if2arb0.bit._ID20 +#define IF2ARB0_ID21 _if2arb0.bit._ID21 +#define IF2ARB0_ID22 _if2arb0.bit._ID22 +#define IF2ARB0_ID23 _if2arb0.bit._ID23 +#define IF2ARB0_ID24 _if2arb0.bit._ID24 +#define IF2ARB0_ID25 _if2arb0.bit._ID25 +#define IF2ARB0_ID26 _if2arb0.bit._ID26 +#define IF2ARB0_ID27 _if2arb0.bit._ID27 +#define IF2ARB0_ID28 _if2arb0.bit._ID28 +#define IF2ARB0_DIR _if2arb0.bit._DIR +#define IF2ARB0_XTD _if2arb0.bit._XTD +#define IF2ARB0_MSGVAL _if2arb0.bit._MSGVAL +#define IF2ARB0_ID _if2arb0.bitc._ID +__IO_EXTENDED IF2ARB10STR _if2arb10; +#define IF2ARB10 _if2arb10.word +#define IF2ARB10_ID0 _if2arb10.bit._ID0 +#define IF2ARB10_ID1 _if2arb10.bit._ID1 +#define IF2ARB10_ID2 _if2arb10.bit._ID2 +#define IF2ARB10_ID3 _if2arb10.bit._ID3 +#define IF2ARB10_ID4 _if2arb10.bit._ID4 +#define IF2ARB10_ID5 _if2arb10.bit._ID5 +#define IF2ARB10_ID6 _if2arb10.bit._ID6 +#define IF2ARB10_ID7 _if2arb10.bit._ID7 +#define IF2ARB10_ID8 _if2arb10.bit._ID8 +#define IF2ARB10_ID9 _if2arb10.bit._ID9 +#define IF2ARB10_ID10 _if2arb10.bit._ID10 +#define IF2ARB10_ID11 _if2arb10.bit._ID11 +#define IF2ARB10_ID12 _if2arb10.bit._ID12 +#define IF2ARB10_ID13 _if2arb10.bit._ID13 +#define IF2ARB10_ID14 _if2arb10.bit._ID14 +#define IF2ARB10_ID15 _if2arb10.bit._ID15 +__IO_EXTENDED IF2ARB1L0STR _if2arb1l0; +#define IF2ARB1L0 _if2arb1l0.byte +#define IF2ARB1L0_ID0 _if2arb1l0.bit._ID0 +#define IF2ARB1L0_ID1 _if2arb1l0.bit._ID1 +#define IF2ARB1L0_ID2 _if2arb1l0.bit._ID2 +#define IF2ARB1L0_ID3 _if2arb1l0.bit._ID3 +#define IF2ARB1L0_ID4 _if2arb1l0.bit._ID4 +#define IF2ARB1L0_ID5 _if2arb1l0.bit._ID5 +#define IF2ARB1L0_ID6 _if2arb1l0.bit._ID6 +#define IF2ARB1L0_ID7 _if2arb1l0.bit._ID7 +__IO_EXTENDED IF2ARB1H0STR _if2arb1h0; +#define IF2ARB1H0 _if2arb1h0.byte +#define IF2ARB1H0_ID8 _if2arb1h0.bit._ID8 +#define IF2ARB1H0_ID9 _if2arb1h0.bit._ID9 +#define IF2ARB1H0_ID10 _if2arb1h0.bit._ID10 +#define IF2ARB1H0_ID11 _if2arb1h0.bit._ID11 +#define IF2ARB1H0_ID12 _if2arb1h0.bit._ID12 +#define IF2ARB1H0_ID13 _if2arb1h0.bit._ID13 +#define IF2ARB1H0_ID14 _if2arb1h0.bit._ID14 +#define IF2ARB1H0_ID15 _if2arb1h0.bit._ID15 +__IO_EXTENDED IF2ARB20STR _if2arb20; +#define IF2ARB20 _if2arb20.word +#define IF2ARB20_ID16 _if2arb20.bit._ID16 +#define IF2ARB20_ID17 _if2arb20.bit._ID17 +#define IF2ARB20_ID18 _if2arb20.bit._ID18 +#define IF2ARB20_ID19 _if2arb20.bit._ID19 +#define IF2ARB20_ID20 _if2arb20.bit._ID20 +#define IF2ARB20_ID21 _if2arb20.bit._ID21 +#define IF2ARB20_ID22 _if2arb20.bit._ID22 +#define IF2ARB20_ID23 _if2arb20.bit._ID23 +#define IF2ARB20_ID24 _if2arb20.bit._ID24 +#define IF2ARB20_ID25 _if2arb20.bit._ID25 +#define IF2ARB20_ID26 _if2arb20.bit._ID26 +#define IF2ARB20_ID27 _if2arb20.bit._ID27 +#define IF2ARB20_ID28 _if2arb20.bit._ID28 +#define IF2ARB20_DIR _if2arb20.bit._DIR +#define IF2ARB20_XTD _if2arb20.bit._XTD +#define IF2ARB20_MSGVAL _if2arb20.bit._MSGVAL +__IO_EXTENDED IF2ARB2L0STR _if2arb2l0; +#define IF2ARB2L0 _if2arb2l0.byte +#define IF2ARB2L0_ID16 _if2arb2l0.bit._ID16 +#define IF2ARB2L0_ID17 _if2arb2l0.bit._ID17 +#define IF2ARB2L0_ID18 _if2arb2l0.bit._ID18 +#define IF2ARB2L0_ID19 _if2arb2l0.bit._ID19 +#define IF2ARB2L0_ID20 _if2arb2l0.bit._ID20 +#define IF2ARB2L0_ID21 _if2arb2l0.bit._ID21 +#define IF2ARB2L0_ID22 _if2arb2l0.bit._ID22 +#define IF2ARB2L0_ID23 _if2arb2l0.bit._ID23 +__IO_EXTENDED IF2ARB2H0STR _if2arb2h0; +#define IF2ARB2H0 _if2arb2h0.byte +#define IF2ARB2H0_ID24 _if2arb2h0.bit._ID24 +#define IF2ARB2H0_ID25 _if2arb2h0.bit._ID25 +#define IF2ARB2H0_ID26 _if2arb2h0.bit._ID26 +#define IF2ARB2H0_ID27 _if2arb2h0.bit._ID27 +#define IF2ARB2H0_ID28 _if2arb2h0.bit._ID28 +#define IF2ARB2H0_DIR _if2arb2h0.bit._DIR +#define IF2ARB2H0_XTD _if2arb2h0.bit._XTD +#define IF2ARB2H0_MSGVAL _if2arb2h0.bit._MSGVAL +__IO_EXTENDED IF2MCTR0STR _if2mctr0; +#define IF2MCTR0 _if2mctr0.word +#define IF2MCTR0_DLC0 _if2mctr0.bit._DLC0 +#define IF2MCTR0_DLC1 _if2mctr0.bit._DLC1 +#define IF2MCTR0_DLC2 _if2mctr0.bit._DLC2 +#define IF2MCTR0_DLC3 _if2mctr0.bit._DLC3 +#define IF2MCTR0_EOB _if2mctr0.bit._EOB +#define IF2MCTR0_TXRQST _if2mctr0.bit._TXRQST +#define IF2MCTR0_RMTEN _if2mctr0.bit._RMTEN +#define IF2MCTR0_RXIE _if2mctr0.bit._RXIE +#define IF2MCTR0_TXIE _if2mctr0.bit._TXIE +#define IF2MCTR0_UMASK _if2mctr0.bit._UMASK +#define IF2MCTR0_INTPND _if2mctr0.bit._INTPND +#define IF2MCTR0_MSGLST _if2mctr0.bit._MSGLST +#define IF2MCTR0_NEWDAT _if2mctr0.bit._NEWDAT +#define IF2MCTR0_DLC _if2mctr0.bitc._DLC +__IO_EXTENDED IF2MCTRL0STR _if2mctrl0; +#define IF2MCTRL0 _if2mctrl0.byte +#define IF2MCTRL0_DLC0 _if2mctrl0.bit._DLC0 +#define IF2MCTRL0_DLC1 _if2mctrl0.bit._DLC1 +#define IF2MCTRL0_DLC2 _if2mctrl0.bit._DLC2 +#define IF2MCTRL0_DLC3 _if2mctrl0.bit._DLC3 +#define IF2MCTRL0_EOB _if2mctrl0.bit._EOB +#define IF2MCTRL0_DLC _if2mctrl0.bitc._DLC +__IO_EXTENDED IF2MCTRH0STR _if2mctrh0; +#define IF2MCTRH0 _if2mctrh0.byte +#define IF2MCTRH0_TXRQST _if2mctrh0.bit._TXRQST +#define IF2MCTRH0_RMTEN _if2mctrh0.bit._RMTEN +#define IF2MCTRH0_RXIE _if2mctrh0.bit._RXIE +#define IF2MCTRH0_TXIE _if2mctrh0.bit._TXIE +#define IF2MCTRH0_UMASK _if2mctrh0.bit._UMASK +#define IF2MCTRH0_INTPND _if2mctrh0.bit._INTPND +#define IF2MCTRH0_MSGLST _if2mctrh0.bit._MSGLST +#define IF2MCTRH0_NEWDAT _if2mctrh0.bit._NEWDAT +__IO_EXTENDED IF2DTA0STR _if2dta0; +#define IF2DTA0 _if2dta0.lword +__IO_EXTENDED IF2DTA10STR _if2dta10; +#define IF2DTA10 _if2dta10.word +__IO_EXTENDED IF2DTA1L0STR _if2dta1l0; +#define IF2DTA1L0 _if2dta1l0.byte +__IO_EXTENDED IF2DTA1H0STR _if2dta1h0; +#define IF2DTA1H0 _if2dta1h0.byte +__IO_EXTENDED IF2DTA20STR _if2dta20; +#define IF2DTA20 _if2dta20.word +__IO_EXTENDED IF2DTA2L0STR _if2dta2l0; +#define IF2DTA2L0 _if2dta2l0.byte +__IO_EXTENDED IF2DTA2H0STR _if2dta2h0; +#define IF2DTA2H0 _if2dta2h0.byte +__IO_EXTENDED IF2DTB0STR _if2dtb0; +#define IF2DTB0 _if2dtb0.lword +__IO_EXTENDED IF2DTB10STR _if2dtb10; +#define IF2DTB10 _if2dtb10.word +__IO_EXTENDED IF2DTB1L0STR _if2dtb1l0; +#define IF2DTB1L0 _if2dtb1l0.byte +__IO_EXTENDED IF2DTB1H0STR _if2dtb1h0; +#define IF2DTB1H0 _if2dtb1h0.byte +__IO_EXTENDED IF2DTB20STR _if2dtb20; +#define IF2DTB20 _if2dtb20.word +__IO_EXTENDED IF2DTB2L0STR _if2dtb2l0; +#define IF2DTB2L0 _if2dtb2l0.byte +__IO_EXTENDED IF2DTB2H0STR _if2dtb2h0; +#define IF2DTB2H0 _if2dtb2h0.byte +__IO_EXTENDED TREQR0STR _treqr0; +#define TREQR0 _treqr0.lword +#define TREQR0_TXRQST1 _treqr0.bit._TXRQST1 +#define TREQR0_TXRQST2 _treqr0.bit._TXRQST2 +#define TREQR0_TXRQST3 _treqr0.bit._TXRQST3 +#define TREQR0_TXRQST4 _treqr0.bit._TXRQST4 +#define TREQR0_TXRQST5 _treqr0.bit._TXRQST5 +#define TREQR0_TXRQST6 _treqr0.bit._TXRQST6 +#define TREQR0_TXRQST7 _treqr0.bit._TXRQST7 +#define TREQR0_TXRQST8 _treqr0.bit._TXRQST8 +#define TREQR0_TXRQST9 _treqr0.bit._TXRQST9 +#define TREQR0_TXRQST10 _treqr0.bit._TXRQST10 +#define TREQR0_TXRQST11 _treqr0.bit._TXRQST11 +#define TREQR0_TXRQST12 _treqr0.bit._TXRQST12 +#define TREQR0_TXRQST13 _treqr0.bit._TXRQST13 +#define TREQR0_TXRQST14 _treqr0.bit._TXRQST14 +#define TREQR0_TXRQST15 _treqr0.bit._TXRQST15 +#define TREQR0_TXRQST16 _treqr0.bit._TXRQST16 +#define TREQR0_TXRQST17 _treqr0.bit._TXRQST17 +#define TREQR0_TXRQST18 _treqr0.bit._TXRQST18 +#define TREQR0_TXRQST19 _treqr0.bit._TXRQST19 +#define TREQR0_TXRQST20 _treqr0.bit._TXRQST20 +#define TREQR0_TXRQST21 _treqr0.bit._TXRQST21 +#define TREQR0_TXRQST22 _treqr0.bit._TXRQST22 +#define TREQR0_TXRQST23 _treqr0.bit._TXRQST23 +#define TREQR0_TXRQST24 _treqr0.bit._TXRQST24 +#define TREQR0_TXRQST25 _treqr0.bit._TXRQST25 +#define TREQR0_TXRQST26 _treqr0.bit._TXRQST26 +#define TREQR0_TXRQST27 _treqr0.bit._TXRQST27 +#define TREQR0_TXRQST28 _treqr0.bit._TXRQST28 +#define TREQR0_TXRQST29 _treqr0.bit._TXRQST29 +#define TREQR0_TXRQST30 _treqr0.bit._TXRQST30 +#define TREQR0_TXRQST31 _treqr0.bit._TXRQST31 +#define TREQR0_TXRQST32 _treqr0.bit._TXRQST32 +#define TREQR0_TXRQST _treqr0.bitc._TXRQST +__IO_EXTENDED TREQR10STR _treqr10; +#define TREQR10 _treqr10.word +#define TREQR10_TXRQST1 _treqr10.bit._TXRQST1 +#define TREQR10_TXRQST2 _treqr10.bit._TXRQST2 +#define TREQR10_TXRQST3 _treqr10.bit._TXRQST3 +#define TREQR10_TXRQST4 _treqr10.bit._TXRQST4 +#define TREQR10_TXRQST5 _treqr10.bit._TXRQST5 +#define TREQR10_TXRQST6 _treqr10.bit._TXRQST6 +#define TREQR10_TXRQST7 _treqr10.bit._TXRQST7 +#define TREQR10_TXRQST8 _treqr10.bit._TXRQST8 +#define TREQR10_TXRQST9 _treqr10.bit._TXRQST9 +#define TREQR10_TXRQST10 _treqr10.bit._TXRQST10 +#define TREQR10_TXRQST11 _treqr10.bit._TXRQST11 +#define TREQR10_TXRQST12 _treqr10.bit._TXRQST12 +#define TREQR10_TXRQST13 _treqr10.bit._TXRQST13 +#define TREQR10_TXRQST14 _treqr10.bit._TXRQST14 +#define TREQR10_TXRQST15 _treqr10.bit._TXRQST15 +#define TREQR10_TXRQST16 _treqr10.bit._TXRQST16 +__IO_EXTENDED TREQR1L0STR _treqr1l0; +#define TREQR1L0 _treqr1l0.byte +#define TREQR1L0_TXRQST1 _treqr1l0.bit._TXRQST1 +#define TREQR1L0_TXRQST2 _treqr1l0.bit._TXRQST2 +#define TREQR1L0_TXRQST3 _treqr1l0.bit._TXRQST3 +#define TREQR1L0_TXRQST4 _treqr1l0.bit._TXRQST4 +#define TREQR1L0_TXRQST5 _treqr1l0.bit._TXRQST5 +#define TREQR1L0_TXRQST6 _treqr1l0.bit._TXRQST6 +#define TREQR1L0_TXRQST7 _treqr1l0.bit._TXRQST7 +#define TREQR1L0_TXRQST8 _treqr1l0.bit._TXRQST8 +__IO_EXTENDED TREQR1H0STR _treqr1h0; +#define TREQR1H0 _treqr1h0.byte +#define TREQR1H0_TXRQST9 _treqr1h0.bit._TXRQST9 +#define TREQR1H0_TXRQST10 _treqr1h0.bit._TXRQST10 +#define TREQR1H0_TXRQST11 _treqr1h0.bit._TXRQST11 +#define TREQR1H0_TXRQST12 _treqr1h0.bit._TXRQST12 +#define TREQR1H0_TXRQST13 _treqr1h0.bit._TXRQST13 +#define TREQR1H0_TXRQST14 _treqr1h0.bit._TXRQST14 +#define TREQR1H0_TXRQST15 _treqr1h0.bit._TXRQST15 +#define TREQR1H0_TXRQST16 _treqr1h0.bit._TXRQST16 +__IO_EXTENDED TREQR20STR _treqr20; +#define TREQR20 _treqr20.word +#define TREQR20_TXRQST17 _treqr20.bit._TXRQST17 +#define TREQR20_TXRQST18 _treqr20.bit._TXRQST18 +#define TREQR20_TXRQST19 _treqr20.bit._TXRQST19 +#define TREQR20_TXRQST20 _treqr20.bit._TXRQST20 +#define TREQR20_TXRQST21 _treqr20.bit._TXRQST21 +#define TREQR20_TXRQST22 _treqr20.bit._TXRQST22 +#define TREQR20_TXRQST23 _treqr20.bit._TXRQST23 +#define TREQR20_TXRQST24 _treqr20.bit._TXRQST24 +#define TREQR20_TXRQST25 _treqr20.bit._TXRQST25 +#define TREQR20_TXRQST26 _treqr20.bit._TXRQST26 +#define TREQR20_TXRQST27 _treqr20.bit._TXRQST27 +#define TREQR20_TXRQST28 _treqr20.bit._TXRQST28 +#define TREQR20_TXRQST29 _treqr20.bit._TXRQST29 +#define TREQR20_TXRQST30 _treqr20.bit._TXRQST30 +#define TREQR20_TXRQST31 _treqr20.bit._TXRQST31 +#define TREQR20_TXRQST32 _treqr20.bit._TXRQST32 +__IO_EXTENDED TREQR2L0STR _treqr2l0; +#define TREQR2L0 _treqr2l0.byte +#define TREQR2L0_TXRQST17 _treqr2l0.bit._TXRQST17 +#define TREQR2L0_TXRQST18 _treqr2l0.bit._TXRQST18 +#define TREQR2L0_TXRQST19 _treqr2l0.bit._TXRQST19 +#define TREQR2L0_TXRQST20 _treqr2l0.bit._TXRQST20 +#define TREQR2L0_TXRQST21 _treqr2l0.bit._TXRQST21 +#define TREQR2L0_TXRQST22 _treqr2l0.bit._TXRQST22 +#define TREQR2L0_TXRQST23 _treqr2l0.bit._TXRQST23 +#define TREQR2L0_TXRQST24 _treqr2l0.bit._TXRQST24 +__IO_EXTENDED TREQR2H0STR _treqr2h0; +#define TREQR2H0 _treqr2h0.byte +#define TREQR2H0_TXRQST25 _treqr2h0.bit._TXRQST25 +#define TREQR2H0_TXRQST26 _treqr2h0.bit._TXRQST26 +#define TREQR2H0_TXRQST27 _treqr2h0.bit._TXRQST27 +#define TREQR2H0_TXRQST28 _treqr2h0.bit._TXRQST28 +#define TREQR2H0_TXRQST29 _treqr2h0.bit._TXRQST29 +#define TREQR2H0_TXRQST30 _treqr2h0.bit._TXRQST30 +#define TREQR2H0_TXRQST31 _treqr2h0.bit._TXRQST31 +#define TREQR2H0_TXRQST32 _treqr2h0.bit._TXRQST32 +__IO_EXTENDED NEWDT0STR _newdt0; +#define NEWDT0 _newdt0.lword +#define NEWDT0_NEWDAT1 _newdt0.bit._NEWDAT1 +#define NEWDT0_NEWDAT2 _newdt0.bit._NEWDAT2 +#define NEWDT0_NEWDAT3 _newdt0.bit._NEWDAT3 +#define NEWDT0_NEWDAT4 _newdt0.bit._NEWDAT4 +#define NEWDT0_NEWDAT5 _newdt0.bit._NEWDAT5 +#define NEWDT0_NEWDAT6 _newdt0.bit._NEWDAT6 +#define NEWDT0_NEWDAT7 _newdt0.bit._NEWDAT7 +#define NEWDT0_NEWDAT8 _newdt0.bit._NEWDAT8 +#define NEWDT0_NEWDAT9 _newdt0.bit._NEWDAT9 +#define NEWDT0_NEWDAT10 _newdt0.bit._NEWDAT10 +#define NEWDT0_NEWDAT11 _newdt0.bit._NEWDAT11 +#define NEWDT0_NEWDAT12 _newdt0.bit._NEWDAT12 +#define NEWDT0_NEWDAT13 _newdt0.bit._NEWDAT13 +#define NEWDT0_NEWDAT14 _newdt0.bit._NEWDAT14 +#define NEWDT0_NEWDAT15 _newdt0.bit._NEWDAT15 +#define NEWDT0_NEWDAT16 _newdt0.bit._NEWDAT16 +#define NEWDT0_NEWDAT17 _newdt0.bit._NEWDAT17 +#define NEWDT0_NEWDAT18 _newdt0.bit._NEWDAT18 +#define NEWDT0_NEWDAT19 _newdt0.bit._NEWDAT19 +#define NEWDT0_NEWDAT20 _newdt0.bit._NEWDAT20 +#define NEWDT0_NEWDAT21 _newdt0.bit._NEWDAT21 +#define NEWDT0_NEWDAT22 _newdt0.bit._NEWDAT22 +#define NEWDT0_NEWDAT23 _newdt0.bit._NEWDAT23 +#define NEWDT0_NEWDAT24 _newdt0.bit._NEWDAT24 +#define NEWDT0_NEWDAT25 _newdt0.bit._NEWDAT25 +#define NEWDT0_NEWDAT26 _newdt0.bit._NEWDAT26 +#define NEWDT0_NEWDAT27 _newdt0.bit._NEWDAT27 +#define NEWDT0_NEWDAT28 _newdt0.bit._NEWDAT28 +#define NEWDT0_NEWDAT29 _newdt0.bit._NEWDAT29 +#define NEWDT0_NEWDAT30 _newdt0.bit._NEWDAT30 +#define NEWDT0_NEWDAT31 _newdt0.bit._NEWDAT31 +#define NEWDT0_NEWDAT32 _newdt0.bit._NEWDAT32 +#define NEWDT0_NEWDAT _newdt0.bitc._NEWDAT +__IO_EXTENDED NEWDT10STR _newdt10; +#define NEWDT10 _newdt10.word +#define NEWDT10_NEWDAT1 _newdt10.bit._NEWDAT1 +#define NEWDT10_NEWDAT2 _newdt10.bit._NEWDAT2 +#define NEWDT10_NEWDAT3 _newdt10.bit._NEWDAT3 +#define NEWDT10_NEWDAT4 _newdt10.bit._NEWDAT4 +#define NEWDT10_NEWDAT5 _newdt10.bit._NEWDAT5 +#define NEWDT10_NEWDAT6 _newdt10.bit._NEWDAT6 +#define NEWDT10_NEWDAT7 _newdt10.bit._NEWDAT7 +#define NEWDT10_NEWDAT8 _newdt10.bit._NEWDAT8 +#define NEWDT10_NEWDAT9 _newdt10.bit._NEWDAT9 +#define NEWDT10_NEWDAT10 _newdt10.bit._NEWDAT10 +#define NEWDT10_NEWDAT11 _newdt10.bit._NEWDAT11 +#define NEWDT10_NEWDAT12 _newdt10.bit._NEWDAT12 +#define NEWDT10_NEWDAT13 _newdt10.bit._NEWDAT13 +#define NEWDT10_NEWDAT14 _newdt10.bit._NEWDAT14 +#define NEWDT10_NEWDAT15 _newdt10.bit._NEWDAT15 +#define NEWDT10_NEWDAT16 _newdt10.bit._NEWDAT16 +__IO_EXTENDED NEWDT1L0STR _newdt1l0; +#define NEWDT1L0 _newdt1l0.byte +#define NEWDT1L0_NEWDAT1 _newdt1l0.bit._NEWDAT1 +#define NEWDT1L0_NEWDAT2 _newdt1l0.bit._NEWDAT2 +#define NEWDT1L0_NEWDAT3 _newdt1l0.bit._NEWDAT3 +#define NEWDT1L0_NEWDAT4 _newdt1l0.bit._NEWDAT4 +#define NEWDT1L0_NEWDAT5 _newdt1l0.bit._NEWDAT5 +#define NEWDT1L0_NEWDAT6 _newdt1l0.bit._NEWDAT6 +#define NEWDT1L0_NEWDAT7 _newdt1l0.bit._NEWDAT7 +#define NEWDT1L0_NEWDAT8 _newdt1l0.bit._NEWDAT8 +__IO_EXTENDED NEWDT1H0STR _newdt1h0; +#define NEWDT1H0 _newdt1h0.byte +#define NEWDT1H0_NEWDAT9 _newdt1h0.bit._NEWDAT9 +#define NEWDT1H0_NEWDAT10 _newdt1h0.bit._NEWDAT10 +#define NEWDT1H0_NEWDAT11 _newdt1h0.bit._NEWDAT11 +#define NEWDT1H0_NEWDAT12 _newdt1h0.bit._NEWDAT12 +#define NEWDT1H0_NEWDAT13 _newdt1h0.bit._NEWDAT13 +#define NEWDT1H0_NEWDAT14 _newdt1h0.bit._NEWDAT14 +#define NEWDT1H0_NEWDAT15 _newdt1h0.bit._NEWDAT15 +#define NEWDT1H0_NEWDAT16 _newdt1h0.bit._NEWDAT16 +__IO_EXTENDED NEWDT20STR _newdt20; +#define NEWDT20 _newdt20.word +#define NEWDT20_NEWDAT17 _newdt20.bit._NEWDAT17 +#define NEWDT20_NEWDAT18 _newdt20.bit._NEWDAT18 +#define NEWDT20_NEWDAT19 _newdt20.bit._NEWDAT19 +#define NEWDT20_NEWDAT20 _newdt20.bit._NEWDAT20 +#define NEWDT20_NEWDAT21 _newdt20.bit._NEWDAT21 +#define NEWDT20_NEWDAT22 _newdt20.bit._NEWDAT22 +#define NEWDT20_NEWDAT23 _newdt20.bit._NEWDAT23 +#define NEWDT20_NEWDAT24 _newdt20.bit._NEWDAT24 +#define NEWDT20_NEWDAT25 _newdt20.bit._NEWDAT25 +#define NEWDT20_NEWDAT26 _newdt20.bit._NEWDAT26 +#define NEWDT20_NEWDAT27 _newdt20.bit._NEWDAT27 +#define NEWDT20_NEWDAT28 _newdt20.bit._NEWDAT28 +#define NEWDT20_NEWDAT29 _newdt20.bit._NEWDAT29 +#define NEWDT20_NEWDAT30 _newdt20.bit._NEWDAT30 +#define NEWDT20_NEWDAT31 _newdt20.bit._NEWDAT31 +#define NEWDT20_NEWDAT32 _newdt20.bit._NEWDAT32 +__IO_EXTENDED NEWDT2L0STR _newdt2l0; +#define NEWDT2L0 _newdt2l0.byte +#define NEWDT2L0_NEWDAT17 _newdt2l0.bit._NEWDAT17 +#define NEWDT2L0_NEWDAT18 _newdt2l0.bit._NEWDAT18 +#define NEWDT2L0_NEWDAT19 _newdt2l0.bit._NEWDAT19 +#define NEWDT2L0_NEWDAT20 _newdt2l0.bit._NEWDAT20 +#define NEWDT2L0_NEWDAT21 _newdt2l0.bit._NEWDAT21 +#define NEWDT2L0_NEWDAT22 _newdt2l0.bit._NEWDAT22 +#define NEWDT2L0_NEWDAT23 _newdt2l0.bit._NEWDAT23 +#define NEWDT2L0_NEWDAT24 _newdt2l0.bit._NEWDAT24 +__IO_EXTENDED NEWDT2H0STR _newdt2h0; +#define NEWDT2H0 _newdt2h0.byte +#define NEWDT2H0_NEWDAT25 _newdt2h0.bit._NEWDAT25 +#define NEWDT2H0_NEWDAT26 _newdt2h0.bit._NEWDAT26 +#define NEWDT2H0_NEWDAT27 _newdt2h0.bit._NEWDAT27 +#define NEWDT2H0_NEWDAT28 _newdt2h0.bit._NEWDAT28 +#define NEWDT2H0_NEWDAT29 _newdt2h0.bit._NEWDAT29 +#define NEWDT2H0_NEWDAT30 _newdt2h0.bit._NEWDAT30 +#define NEWDT2H0_NEWDAT31 _newdt2h0.bit._NEWDAT31 +#define NEWDT2H0_NEWDAT32 _newdt2h0.bit._NEWDAT32 +__IO_EXTENDED INTPND0STR _intpnd0; +#define INTPND0 _intpnd0.lword +#define INTPND0_INTPND1 _intpnd0.bit._INTPND1 +#define INTPND0_INTPND2 _intpnd0.bit._INTPND2 +#define INTPND0_INTPND3 _intpnd0.bit._INTPND3 +#define INTPND0_INTPND4 _intpnd0.bit._INTPND4 +#define INTPND0_INTPND5 _intpnd0.bit._INTPND5 +#define INTPND0_INTPND6 _intpnd0.bit._INTPND6 +#define INTPND0_INTPND7 _intpnd0.bit._INTPND7 +#define INTPND0_INTPND8 _intpnd0.bit._INTPND8 +#define INTPND0_INTPND9 _intpnd0.bit._INTPND9 +#define INTPND0_INTPND10 _intpnd0.bit._INTPND10 +#define INTPND0_INTPND11 _intpnd0.bit._INTPND11 +#define INTPND0_INTPND12 _intpnd0.bit._INTPND12 +#define INTPND0_INTPND13 _intpnd0.bit._INTPND13 +#define INTPND0_INTPND14 _intpnd0.bit._INTPND14 +#define INTPND0_INTPND15 _intpnd0.bit._INTPND15 +#define INTPND0_INTPND16 _intpnd0.bit._INTPND16 +#define INTPND0_INTPND17 _intpnd0.bit._INTPND17 +#define INTPND0_INTPND18 _intpnd0.bit._INTPND18 +#define INTPND0_INTPND19 _intpnd0.bit._INTPND19 +#define INTPND0_INTPND20 _intpnd0.bit._INTPND20 +#define INTPND0_INTPND21 _intpnd0.bit._INTPND21 +#define INTPND0_INTPND22 _intpnd0.bit._INTPND22 +#define INTPND0_INTPND23 _intpnd0.bit._INTPND23 +#define INTPND0_INTPND24 _intpnd0.bit._INTPND24 +#define INTPND0_INTPND25 _intpnd0.bit._INTPND25 +#define INTPND0_INTPND26 _intpnd0.bit._INTPND26 +#define INTPND0_INTPND27 _intpnd0.bit._INTPND27 +#define INTPND0_INTPND28 _intpnd0.bit._INTPND28 +#define INTPND0_INTPND29 _intpnd0.bit._INTPND29 +#define INTPND0_INTPND30 _intpnd0.bit._INTPND30 +#define INTPND0_INTPND31 _intpnd0.bit._INTPND31 +#define INTPND0_INTPND32 _intpnd0.bit._INTPND32 +#define INTPND0_INTPND _intpnd0.bitc._INTPND +__IO_EXTENDED INTPND10STR _intpnd10; +#define INTPND10 _intpnd10.word +#define INTPND10_INTPND1 _intpnd10.bit._INTPND1 +#define INTPND10_INTPND2 _intpnd10.bit._INTPND2 +#define INTPND10_INTPND3 _intpnd10.bit._INTPND3 +#define INTPND10_INTPND4 _intpnd10.bit._INTPND4 +#define INTPND10_INTPND5 _intpnd10.bit._INTPND5 +#define INTPND10_INTPND6 _intpnd10.bit._INTPND6 +#define INTPND10_INTPND7 _intpnd10.bit._INTPND7 +#define INTPND10_INTPND8 _intpnd10.bit._INTPND8 +#define INTPND10_INTPND9 _intpnd10.bit._INTPND9 +#define INTPND10_INTPND10 _intpnd10.bit._INTPND10 +#define INTPND10_INTPND11 _intpnd10.bit._INTPND11 +#define INTPND10_INTPND12 _intpnd10.bit._INTPND12 +#define INTPND10_INTPND13 _intpnd10.bit._INTPND13 +#define INTPND10_INTPND14 _intpnd10.bit._INTPND14 +#define INTPND10_INTPND15 _intpnd10.bit._INTPND15 +#define INTPND10_INTPND16 _intpnd10.bit._INTPND16 +__IO_EXTENDED INTPND1L0STR _intpnd1l0; +#define INTPND1L0 _intpnd1l0.byte +#define INTPND1L0_INTPND1 _intpnd1l0.bit._INTPND1 +#define INTPND1L0_INTPND2 _intpnd1l0.bit._INTPND2 +#define INTPND1L0_INTPND3 _intpnd1l0.bit._INTPND3 +#define INTPND1L0_INTPND4 _intpnd1l0.bit._INTPND4 +#define INTPND1L0_INTPND5 _intpnd1l0.bit._INTPND5 +#define INTPND1L0_INTPND6 _intpnd1l0.bit._INTPND6 +#define INTPND1L0_INTPND7 _intpnd1l0.bit._INTPND7 +#define INTPND1L0_INTPND8 _intpnd1l0.bit._INTPND8 +__IO_EXTENDED INTPND1H0STR _intpnd1h0; +#define INTPND1H0 _intpnd1h0.byte +#define INTPND1H0_INTPND9 _intpnd1h0.bit._INTPND9 +#define INTPND1H0_INTPND10 _intpnd1h0.bit._INTPND10 +#define INTPND1H0_INTPND11 _intpnd1h0.bit._INTPND11 +#define INTPND1H0_INTPND12 _intpnd1h0.bit._INTPND12 +#define INTPND1H0_INTPND13 _intpnd1h0.bit._INTPND13 +#define INTPND1H0_INTPND14 _intpnd1h0.bit._INTPND14 +#define INTPND1H0_INTPND15 _intpnd1h0.bit._INTPND15 +#define INTPND1H0_INTPND16 _intpnd1h0.bit._INTPND16 +__IO_EXTENDED INTPND20STR _intpnd20; +#define INTPND20 _intpnd20.word +#define INTPND20_INTPND17 _intpnd20.bit._INTPND17 +#define INTPND20_INTPND18 _intpnd20.bit._INTPND18 +#define INTPND20_INTPND19 _intpnd20.bit._INTPND19 +#define INTPND20_INTPND20 _intpnd20.bit._INTPND20 +#define INTPND20_INTPND21 _intpnd20.bit._INTPND21 +#define INTPND20_INTPND22 _intpnd20.bit._INTPND22 +#define INTPND20_INTPND23 _intpnd20.bit._INTPND23 +#define INTPND20_INTPND24 _intpnd20.bit._INTPND24 +#define INTPND20_INTPND25 _intpnd20.bit._INTPND25 +#define INTPND20_INTPND26 _intpnd20.bit._INTPND26 +#define INTPND20_INTPND27 _intpnd20.bit._INTPND27 +#define INTPND20_INTPND28 _intpnd20.bit._INTPND28 +#define INTPND20_INTPND29 _intpnd20.bit._INTPND29 +#define INTPND20_INTPND30 _intpnd20.bit._INTPND30 +#define INTPND20_INTPND31 _intpnd20.bit._INTPND31 +#define INTPND20_INTPND32 _intpnd20.bit._INTPND32 +__IO_EXTENDED INTPND2L0STR _intpnd2l0; +#define INTPND2L0 _intpnd2l0.byte +#define INTPND2L0_INTPND17 _intpnd2l0.bit._INTPND17 +#define INTPND2L0_INTPND18 _intpnd2l0.bit._INTPND18 +#define INTPND2L0_INTPND19 _intpnd2l0.bit._INTPND19 +#define INTPND2L0_INTPND20 _intpnd2l0.bit._INTPND20 +#define INTPND2L0_INTPND21 _intpnd2l0.bit._INTPND21 +#define INTPND2L0_INTPND22 _intpnd2l0.bit._INTPND22 +#define INTPND2L0_INTPND23 _intpnd2l0.bit._INTPND23 +#define INTPND2L0_INTPND24 _intpnd2l0.bit._INTPND24 +__IO_EXTENDED INTPND2H0STR _intpnd2h0; +#define INTPND2H0 _intpnd2h0.byte +#define INTPND2H0_INTPND25 _intpnd2h0.bit._INTPND25 +#define INTPND2H0_INTPND26 _intpnd2h0.bit._INTPND26 +#define INTPND2H0_INTPND27 _intpnd2h0.bit._INTPND27 +#define INTPND2H0_INTPND28 _intpnd2h0.bit._INTPND28 +#define INTPND2H0_INTPND29 _intpnd2h0.bit._INTPND29 +#define INTPND2H0_INTPND30 _intpnd2h0.bit._INTPND30 +#define INTPND2H0_INTPND31 _intpnd2h0.bit._INTPND31 +#define INTPND2H0_INTPND32 _intpnd2h0.bit._INTPND32 +__IO_EXTENDED MSGVAL0STR _msgval0; +#define MSGVAL0 _msgval0.lword +#define MSGVAL0_MSGVAL1 _msgval0.bit._MSGVAL1 +#define MSGVAL0_MSGVAL2 _msgval0.bit._MSGVAL2 +#define MSGVAL0_MSGVAL3 _msgval0.bit._MSGVAL3 +#define MSGVAL0_MSGVAL4 _msgval0.bit._MSGVAL4 +#define MSGVAL0_MSGVAL5 _msgval0.bit._MSGVAL5 +#define MSGVAL0_MSGVAL6 _msgval0.bit._MSGVAL6 +#define MSGVAL0_MSGVAL7 _msgval0.bit._MSGVAL7 +#define MSGVAL0_MSGVAL8 _msgval0.bit._MSGVAL8 +#define MSGVAL0_MSGVAL9 _msgval0.bit._MSGVAL9 +#define MSGVAL0_MSGVAL10 _msgval0.bit._MSGVAL10 +#define MSGVAL0_MSGVAL11 _msgval0.bit._MSGVAL11 +#define MSGVAL0_MSGVAL12 _msgval0.bit._MSGVAL12 +#define MSGVAL0_MSGVAL13 _msgval0.bit._MSGVAL13 +#define MSGVAL0_MSGVAL14 _msgval0.bit._MSGVAL14 +#define MSGVAL0_MSGVAL15 _msgval0.bit._MSGVAL15 +#define MSGVAL0_MSGVAL16 _msgval0.bit._MSGVAL16 +#define MSGVAL0_MSGVAL17 _msgval0.bit._MSGVAL17 +#define MSGVAL0_MSGVAL18 _msgval0.bit._MSGVAL18 +#define MSGVAL0_MSGVAL19 _msgval0.bit._MSGVAL19 +#define MSGVAL0_MSGVAL20 _msgval0.bit._MSGVAL20 +#define MSGVAL0_MSGVAL21 _msgval0.bit._MSGVAL21 +#define MSGVAL0_MSGVAL22 _msgval0.bit._MSGVAL22 +#define MSGVAL0_MSGVAL23 _msgval0.bit._MSGVAL23 +#define MSGVAL0_MSGVAL24 _msgval0.bit._MSGVAL24 +#define MSGVAL0_MSGVAL25 _msgval0.bit._MSGVAL25 +#define MSGVAL0_MSGVAL26 _msgval0.bit._MSGVAL26 +#define MSGVAL0_MSGVAL27 _msgval0.bit._MSGVAL27 +#define MSGVAL0_MSGVAL28 _msgval0.bit._MSGVAL28 +#define MSGVAL0_MSGVAL29 _msgval0.bit._MSGVAL29 +#define MSGVAL0_MSGVAL30 _msgval0.bit._MSGVAL30 +#define MSGVAL0_MSGVAL31 _msgval0.bit._MSGVAL31 +#define MSGVAL0_MSGVAL32 _msgval0.bit._MSGVAL32 +#define MSGVAL0_MSGVAL _msgval0.bitc._MSGVAL +__IO_EXTENDED MSGVAL10STR _msgval10; +#define MSGVAL10 _msgval10.word +#define MSGVAL10_MSGVAL1 _msgval10.bit._MSGVAL1 +#define MSGVAL10_MSGVAL2 _msgval10.bit._MSGVAL2 +#define MSGVAL10_MSGVAL3 _msgval10.bit._MSGVAL3 +#define MSGVAL10_MSGVAL4 _msgval10.bit._MSGVAL4 +#define MSGVAL10_MSGVAL5 _msgval10.bit._MSGVAL5 +#define MSGVAL10_MSGVAL6 _msgval10.bit._MSGVAL6 +#define MSGVAL10_MSGVAL7 _msgval10.bit._MSGVAL7 +#define MSGVAL10_MSGVAL8 _msgval10.bit._MSGVAL8 +#define MSGVAL10_MSGVAL9 _msgval10.bit._MSGVAL9 +#define MSGVAL10_MSGVAL10 _msgval10.bit._MSGVAL10 +#define MSGVAL10_MSGVAL11 _msgval10.bit._MSGVAL11 +#define MSGVAL10_MSGVAL12 _msgval10.bit._MSGVAL12 +#define MSGVAL10_MSGVAL13 _msgval10.bit._MSGVAL13 +#define MSGVAL10_MSGVAL14 _msgval10.bit._MSGVAL14 +#define MSGVAL10_MSGVAL15 _msgval10.bit._MSGVAL15 +#define MSGVAL10_MSGVAL16 _msgval10.bit._MSGVAL16 +__IO_EXTENDED MSGVAL1L0STR _msgval1l0; +#define MSGVAL1L0 _msgval1l0.byte +#define MSGVAL1L0_MSGVAL1 _msgval1l0.bit._MSGVAL1 +#define MSGVAL1L0_MSGVAL2 _msgval1l0.bit._MSGVAL2 +#define MSGVAL1L0_MSGVAL3 _msgval1l0.bit._MSGVAL3 +#define MSGVAL1L0_MSGVAL4 _msgval1l0.bit._MSGVAL4 +#define MSGVAL1L0_MSGVAL5 _msgval1l0.bit._MSGVAL5 +#define MSGVAL1L0_MSGVAL6 _msgval1l0.bit._MSGVAL6 +#define MSGVAL1L0_MSGVAL7 _msgval1l0.bit._MSGVAL7 +#define MSGVAL1L0_MSGVAL8 _msgval1l0.bit._MSGVAL8 +__IO_EXTENDED MSGVAL1H0STR _msgval1h0; +#define MSGVAL1H0 _msgval1h0.byte +#define MSGVAL1H0_MSGVAL9 _msgval1h0.bit._MSGVAL9 +#define MSGVAL1H0_MSGVAL10 _msgval1h0.bit._MSGVAL10 +#define MSGVAL1H0_MSGVAL11 _msgval1h0.bit._MSGVAL11 +#define MSGVAL1H0_MSGVAL12 _msgval1h0.bit._MSGVAL12 +#define MSGVAL1H0_MSGVAL13 _msgval1h0.bit._MSGVAL13 +#define MSGVAL1H0_MSGVAL14 _msgval1h0.bit._MSGVAL14 +#define MSGVAL1H0_MSGVAL15 _msgval1h0.bit._MSGVAL15 +#define MSGVAL1H0_MSGVAL16 _msgval1h0.bit._MSGVAL16 +__IO_EXTENDED MSGVAL20STR _msgval20; +#define MSGVAL20 _msgval20.word +#define MSGVAL20_MSGVAL17 _msgval20.bit._MSGVAL17 +#define MSGVAL20_MSGVAL18 _msgval20.bit._MSGVAL18 +#define MSGVAL20_MSGVAL19 _msgval20.bit._MSGVAL19 +#define MSGVAL20_MSGVAL20 _msgval20.bit._MSGVAL20 +#define MSGVAL20_MSGVAL21 _msgval20.bit._MSGVAL21 +#define MSGVAL20_MSGVAL22 _msgval20.bit._MSGVAL22 +#define MSGVAL20_MSGVAL23 _msgval20.bit._MSGVAL23 +#define MSGVAL20_MSGVAL24 _msgval20.bit._MSGVAL24 +#define MSGVAL20_MSGVAL25 _msgval20.bit._MSGVAL25 +#define MSGVAL20_MSGVAL26 _msgval20.bit._MSGVAL26 +#define MSGVAL20_MSGVAL27 _msgval20.bit._MSGVAL27 +#define MSGVAL20_MSGVAL28 _msgval20.bit._MSGVAL28 +#define MSGVAL20_MSGVAL29 _msgval20.bit._MSGVAL29 +#define MSGVAL20_MSGVAL30 _msgval20.bit._MSGVAL30 +#define MSGVAL20_MSGVAL31 _msgval20.bit._MSGVAL31 +#define MSGVAL20_MSGVAL32 _msgval20.bit._MSGVAL32 +__IO_EXTENDED MSGVAL2L0STR _msgval2l0; +#define MSGVAL2L0 _msgval2l0.byte +#define MSGVAL2L0_MSGVAL17 _msgval2l0.bit._MSGVAL17 +#define MSGVAL2L0_MSGVAL18 _msgval2l0.bit._MSGVAL18 +#define MSGVAL2L0_MSGVAL19 _msgval2l0.bit._MSGVAL19 +#define MSGVAL2L0_MSGVAL20 _msgval2l0.bit._MSGVAL20 +#define MSGVAL2L0_MSGVAL21 _msgval2l0.bit._MSGVAL21 +#define MSGVAL2L0_MSGVAL22 _msgval2l0.bit._MSGVAL22 +#define MSGVAL2L0_MSGVAL23 _msgval2l0.bit._MSGVAL23 +#define MSGVAL2L0_MSGVAL24 _msgval2l0.bit._MSGVAL24 +__IO_EXTENDED MSGVAL2H0STR _msgval2h0; +#define MSGVAL2H0 _msgval2h0.byte +#define MSGVAL2H0_MSGVAL25 _msgval2h0.bit._MSGVAL25 +#define MSGVAL2H0_MSGVAL26 _msgval2h0.bit._MSGVAL26 +#define MSGVAL2H0_MSGVAL27 _msgval2h0.bit._MSGVAL27 +#define MSGVAL2H0_MSGVAL28 _msgval2h0.bit._MSGVAL28 +#define MSGVAL2H0_MSGVAL29 _msgval2h0.bit._MSGVAL29 +#define MSGVAL2H0_MSGVAL30 _msgval2h0.bit._MSGVAL30 +#define MSGVAL2H0_MSGVAL31 _msgval2h0.bit._MSGVAL31 +#define MSGVAL2H0_MSGVAL32 _msgval2h0.bit._MSGVAL32 +__IO_EXTENDED COER0STR _coer0; +#define COER0 _coer0.byte +#define COER0_OE _coer0.bit._OE +__IO_EXTENDED CTRLR1STR _ctrlr1; +#define CTRLR1 _ctrlr1.word +#define CTRLR1_INIT _ctrlr1.bit._INIT +#define CTRLR1_IE _ctrlr1.bit._IE +#define CTRLR1_SIE _ctrlr1.bit._SIE +#define CTRLR1_EIE _ctrlr1.bit._EIE +#define CTRLR1_DAR _ctrlr1.bit._DAR +#define CTRLR1_CCE _ctrlr1.bit._CCE +#define CTRLR1_TEST _ctrlr1.bit._TEST +__IO_EXTENDED CTRLRL1STR _ctrlrl1; +#define CTRLRL1 _ctrlrl1.byte +#define CTRLRL1_INIT _ctrlrl1.bit._INIT +#define CTRLRL1_IE _ctrlrl1.bit._IE +#define CTRLRL1_SIE _ctrlrl1.bit._SIE +#define CTRLRL1_EIE _ctrlrl1.bit._EIE +#define CTRLRL1_DAR _ctrlrl1.bit._DAR +#define CTRLRL1_CCE _ctrlrl1.bit._CCE +#define CTRLRL1_TEST _ctrlrl1.bit._TEST +__IO_EXTENDED CTRLRH1STR _ctrlrh1; +#define CTRLRH1 _ctrlrh1.byte +__IO_EXTENDED STATR1STR _statr1; +#define STATR1 _statr1.word +#define STATR1_LEC0 _statr1.bit._LEC0 +#define STATR1_LEC1 _statr1.bit._LEC1 +#define STATR1_LEC2 _statr1.bit._LEC2 +#define STATR1_TXOK _statr1.bit._TXOK +#define STATR1_RXOK _statr1.bit._RXOK +#define STATR1_EPASS _statr1.bit._EPASS +#define STATR1_EWARN _statr1.bit._EWARN +#define STATR1_BOFF _statr1.bit._BOFF +#define STATR1_LEC _statr1.bitc._LEC +__IO_EXTENDED STATRL1STR _statrl1; +#define STATRL1 _statrl1.byte +#define STATRL1_LEC0 _statrl1.bit._LEC0 +#define STATRL1_LEC1 _statrl1.bit._LEC1 +#define STATRL1_LEC2 _statrl1.bit._LEC2 +#define STATRL1_TXOK _statrl1.bit._TXOK +#define STATRL1_RXOK _statrl1.bit._RXOK +#define STATRL1_EPASS _statrl1.bit._EPASS +#define STATRL1_EWARN _statrl1.bit._EWARN +#define STATRL1_BOFF _statrl1.bit._BOFF +#define STATRL1_LEC _statrl1.bitc._LEC +__IO_EXTENDED STATRH1STR _statrh1; +#define STATRH1 _statrh1.byte +__IO_EXTENDED ERRCNT1STR _errcnt1; +#define ERRCNT1 _errcnt1.word +#define ERRCNT1_TEC0 _errcnt1.bit._TEC0 +#define ERRCNT1_TEC1 _errcnt1.bit._TEC1 +#define ERRCNT1_TEC2 _errcnt1.bit._TEC2 +#define ERRCNT1_TEC3 _errcnt1.bit._TEC3 +#define ERRCNT1_TEC4 _errcnt1.bit._TEC4 +#define ERRCNT1_TEC5 _errcnt1.bit._TEC5 +#define ERRCNT1_TEC6 _errcnt1.bit._TEC6 +#define ERRCNT1_TEC7 _errcnt1.bit._TEC7 +#define ERRCNT1_REC0 _errcnt1.bit._REC0 +#define ERRCNT1_REC1 _errcnt1.bit._REC1 +#define ERRCNT1_REC2 _errcnt1.bit._REC2 +#define ERRCNT1_REC3 _errcnt1.bit._REC3 +#define ERRCNT1_REC4 _errcnt1.bit._REC4 +#define ERRCNT1_REC5 _errcnt1.bit._REC5 +#define ERRCNT1_REC6 _errcnt1.bit._REC6 +#define ERRCNT1_RP _errcnt1.bit._RP +#define ERRCNT1_TEC _errcnt1.bitc._TEC +#define ERRCNT1_REC _errcnt1.bitc._REC +__IO_EXTENDED ERRCNTL1STR _errcntl1; +#define ERRCNTL1 _errcntl1.byte +#define ERRCNTL1_TEC0 _errcntl1.bit._TEC0 +#define ERRCNTL1_TEC1 _errcntl1.bit._TEC1 +#define ERRCNTL1_TEC2 _errcntl1.bit._TEC2 +#define ERRCNTL1_TEC3 _errcntl1.bit._TEC3 +#define ERRCNTL1_TEC4 _errcntl1.bit._TEC4 +#define ERRCNTL1_TEC5 _errcntl1.bit._TEC5 +#define ERRCNTL1_TEC6 _errcntl1.bit._TEC6 +#define ERRCNTL1_TEC7 _errcntl1.bit._TEC7 +#define ERRCNTL1_TEC _errcntl1.bitc._TEC +__IO_EXTENDED ERRCNTH1STR _errcnth1; +#define ERRCNTH1 _errcnth1.byte +#define ERRCNTH1_REC0 _errcnth1.bit._REC0 +#define ERRCNTH1_REC1 _errcnth1.bit._REC1 +#define ERRCNTH1_REC2 _errcnth1.bit._REC2 +#define ERRCNTH1_REC3 _errcnth1.bit._REC3 +#define ERRCNTH1_REC4 _errcnth1.bit._REC4 +#define ERRCNTH1_REC5 _errcnth1.bit._REC5 +#define ERRCNTH1_REC6 _errcnth1.bit._REC6 +#define ERRCNTH1_RP _errcnth1.bit._RP +#define ERRCNTH1_REC _errcnth1.bitc._REC +__IO_EXTENDED BTR1STR _btr1; +#define BTR1 _btr1.word +#define BTR1_BRP0 _btr1.bit._BRP0 +#define BTR1_BRP1 _btr1.bit._BRP1 +#define BTR1_BRP2 _btr1.bit._BRP2 +#define BTR1_BRP3 _btr1.bit._BRP3 +#define BTR1_BRP4 _btr1.bit._BRP4 +#define BTR1_BRP5 _btr1.bit._BRP5 +#define BTR1_SJW0 _btr1.bit._SJW0 +#define BTR1_SJW1 _btr1.bit._SJW1 +#define BTR1_TSEG10 _btr1.bit._TSEG10 +#define BTR1_TSEG11 _btr1.bit._TSEG11 +#define BTR1_TSEG12 _btr1.bit._TSEG12 +#define BTR1_TSEG13 _btr1.bit._TSEG13 +#define BTR1_TSEG20 _btr1.bit._TSEG20 +#define BTR1_TSEG21 _btr1.bit._TSEG21 +#define BTR1_TSEG22 _btr1.bit._TSEG22 +#define BTR1_BRP _btr1.bitc._BRP +#define BTR1_SJW _btr1.bitc._SJW +#define BTR1_TSEG1 _btr1.bitc._TSEG1 +#define BTR1_TSEG2 _btr1.bitc._TSEG2 +__IO_EXTENDED BTRL1STR _btrl1; +#define BTRL1 _btrl1.byte +#define BTRL1_BRP0 _btrl1.bit._BRP0 +#define BTRL1_BRP1 _btrl1.bit._BRP1 +#define BTRL1_BRP2 _btrl1.bit._BRP2 +#define BTRL1_BRP3 _btrl1.bit._BRP3 +#define BTRL1_BRP4 _btrl1.bit._BRP4 +#define BTRL1_BRP5 _btrl1.bit._BRP5 +#define BTRL1_SJW0 _btrl1.bit._SJW0 +#define BTRL1_SJW1 _btrl1.bit._SJW1 +#define BTRL1_BRP _btrl1.bitc._BRP +#define BTRL1_SJW _btrl1.bitc._SJW +__IO_EXTENDED BTRH1STR _btrh1; +#define BTRH1 _btrh1.byte +#define BTRH1_TSEG10 _btrh1.bit._TSEG10 +#define BTRH1_TSEG11 _btrh1.bit._TSEG11 +#define BTRH1_TSEG12 _btrh1.bit._TSEG12 +#define BTRH1_TSEG13 _btrh1.bit._TSEG13 +#define BTRH1_TSEG20 _btrh1.bit._TSEG20 +#define BTRH1_TSEG21 _btrh1.bit._TSEG21 +#define BTRH1_TSEG22 _btrh1.bit._TSEG22 +#define BTRH1_TSEG1 _btrh1.bitc._TSEG1 +#define BTRH1_TSEG2 _btrh1.bitc._TSEG2 +__IO_EXTENDED INTR1STR _intr1; +#define INTR1 _intr1.word +#define INTR1_INTID0 _intr1.bit._INTID0 +#define INTR1_INTID1 _intr1.bit._INTID1 +#define INTR1_INTID2 _intr1.bit._INTID2 +#define INTR1_INTID3 _intr1.bit._INTID3 +#define INTR1_INTID4 _intr1.bit._INTID4 +#define INTR1_INTID5 _intr1.bit._INTID5 +#define INTR1_INTID6 _intr1.bit._INTID6 +#define INTR1_INTID7 _intr1.bit._INTID7 +#define INTR1_INTID8 _intr1.bit._INTID8 +#define INTR1_INTID9 _intr1.bit._INTID9 +#define INTR1_INTID10 _intr1.bit._INTID10 +#define INTR1_INTID11 _intr1.bit._INTID11 +#define INTR1_INTID12 _intr1.bit._INTID12 +#define INTR1_INTID13 _intr1.bit._INTID13 +#define INTR1_INTID14 _intr1.bit._INTID14 +#define INTR1_INTID15 _intr1.bit._INTID15 +#define INTR1_INTID _intr1.bitc._INTID +__IO_EXTENDED INTRL1STR _intrl1; +#define INTRL1 _intrl1.byte +#define INTRL1_INTID0 _intrl1.bit._INTID0 +#define INTRL1_INTID1 _intrl1.bit._INTID1 +#define INTRL1_INTID2 _intrl1.bit._INTID2 +#define INTRL1_INTID3 _intrl1.bit._INTID3 +#define INTRL1_INTID4 _intrl1.bit._INTID4 +#define INTRL1_INTID5 _intrl1.bit._INTID5 +#define INTRL1_INTID6 _intrl1.bit._INTID6 +#define INTRL1_INTID7 _intrl1.bit._INTID7 +__IO_EXTENDED INTRH1STR _intrh1; +#define INTRH1 _intrh1.byte +#define INTRH1_INTID8 _intrh1.bit._INTID8 +#define INTRH1_INTID9 _intrh1.bit._INTID9 +#define INTRH1_INTID10 _intrh1.bit._INTID10 +#define INTRH1_INTID11 _intrh1.bit._INTID11 +#define INTRH1_INTID12 _intrh1.bit._INTID12 +#define INTRH1_INTID13 _intrh1.bit._INTID13 +#define INTRH1_INTID14 _intrh1.bit._INTID14 +#define INTRH1_INTID15 _intrh1.bit._INTID15 +__IO_EXTENDED TESTR1STR _testr1; +#define TESTR1 _testr1.word +#define TESTR1_BASIC _testr1.bit._BASIC +#define TESTR1_SILENT _testr1.bit._SILENT +#define TESTR1_LBACK _testr1.bit._LBACK +#define TESTR1_TX0 _testr1.bit._TX0 +#define TESTR1_TX1 _testr1.bit._TX1 +#define TESTR1_RX _testr1.bit._RX +__IO_EXTENDED TESTRL1STR _testrl1; +#define TESTRL1 _testrl1.byte +#define TESTRL1_BASIC _testrl1.bit._BASIC +#define TESTRL1_SILENT _testrl1.bit._SILENT +#define TESTRL1_LBACK _testrl1.bit._LBACK +#define TESTRL1_TX0 _testrl1.bit._TX0 +#define TESTRL1_TX1 _testrl1.bit._TX1 +#define TESTRL1_RX _testrl1.bit._RX +__IO_EXTENDED TESTRH1STR _testrh1; +#define TESTRH1 _testrh1.byte +__IO_EXTENDED BRPER1STR _brper1; +#define BRPER1 _brper1.word +#define BRPER1_BRPE0 _brper1.bit._BRPE0 +#define BRPER1_BRPE1 _brper1.bit._BRPE1 +#define BRPER1_BRPE2 _brper1.bit._BRPE2 +#define BRPER1_BRPE3 _brper1.bit._BRPE3 +#define BRPER1_BRPE _brper1.bitc._BRPE +__IO_EXTENDED BRPERL1STR _brperl1; +#define BRPERL1 _brperl1.byte +#define BRPERL1_BRPE0 _brperl1.bit._BRPE0 +#define BRPERL1_BRPE1 _brperl1.bit._BRPE1 +#define BRPERL1_BRPE2 _brperl1.bit._BRPE2 +#define BRPERL1_BRPE3 _brperl1.bit._BRPE3 +#define BRPERL1_BRPE _brperl1.bitc._BRPE +__IO_EXTENDED BRPERH1STR _brperh1; +#define BRPERH1 _brperh1.byte +__IO_EXTENDED IF1CREQ1STR _if1creq1; +#define IF1CREQ1 _if1creq1.word +#define IF1CREQ1_MSGN0 _if1creq1.bit._MSGN0 +#define IF1CREQ1_MSGN1 _if1creq1.bit._MSGN1 +#define IF1CREQ1_MSGN2 _if1creq1.bit._MSGN2 +#define IF1CREQ1_MSGN3 _if1creq1.bit._MSGN3 +#define IF1CREQ1_MSGN4 _if1creq1.bit._MSGN4 +#define IF1CREQ1_MSGN5 _if1creq1.bit._MSGN5 +#define IF1CREQ1_MSGN6 _if1creq1.bit._MSGN6 +#define IF1CREQ1_MSGN7 _if1creq1.bit._MSGN7 +#define IF1CREQ1_BUSY _if1creq1.bit._BUSY +__IO_EXTENDED IF1CREQL1STR _if1creql1; +#define IF1CREQL1 _if1creql1.byte +#define IF1CREQL1_MSGN0 _if1creql1.bit._MSGN0 +#define IF1CREQL1_MSGN1 _if1creql1.bit._MSGN1 +#define IF1CREQL1_MSGN2 _if1creql1.bit._MSGN2 +#define IF1CREQL1_MSGN3 _if1creql1.bit._MSGN3 +#define IF1CREQL1_MSGN4 _if1creql1.bit._MSGN4 +#define IF1CREQL1_MSGN5 _if1creql1.bit._MSGN5 +#define IF1CREQL1_MSGN6 _if1creql1.bit._MSGN6 +#define IF1CREQL1_MSGN7 _if1creql1.bit._MSGN7 +__IO_EXTENDED IF1CREQH1STR _if1creqh1; +#define IF1CREQH1 _if1creqh1.byte +#define IF1CREQH1_BUSY _if1creqh1.bit._BUSY +__IO_EXTENDED IF1CMSK1STR _if1cmsk1; +#define IF1CMSK1 _if1cmsk1.word +#define IF1CMSK1_DATAB _if1cmsk1.bit._DATAB +#define IF1CMSK1_DATAA _if1cmsk1.bit._DATAA +#define IF1CMSK1_TXREQ _if1cmsk1.bit._TXREQ +#define IF1CMSK1_CIP _if1cmsk1.bit._CIP +#define IF1CMSK1_CONTROL _if1cmsk1.bit._CONTROL +#define IF1CMSK1_ARB _if1cmsk1.bit._ARB +#define IF1CMSK1_MASK _if1cmsk1.bit._MASK +#define IF1CMSK1_WRRD _if1cmsk1.bit._WRRD +__IO_EXTENDED IF1CMSKL1STR _if1cmskl1; +#define IF1CMSKL1 _if1cmskl1.byte +#define IF1CMSKL1_DATAB _if1cmskl1.bit._DATAB +#define IF1CMSKL1_DATAA _if1cmskl1.bit._DATAA +#define IF1CMSKL1_TXREQ _if1cmskl1.bit._TXREQ +#define IF1CMSKL1_CIP _if1cmskl1.bit._CIP +#define IF1CMSKL1_CONTROL _if1cmskl1.bit._CONTROL +#define IF1CMSKL1_ARB _if1cmskl1.bit._ARB +#define IF1CMSKL1_MASK _if1cmskl1.bit._MASK +#define IF1CMSKL1_WRRD _if1cmskl1.bit._WRRD +__IO_EXTENDED IF1CMSKH1STR _if1cmskh1; +#define IF1CMSKH1 _if1cmskh1.byte +__IO_EXTENDED IF1MSK1STR _if1msk1; +#define IF1MSK1 _if1msk1.lword +#define IF1MSK1_MSK0 _if1msk1.bit._MSK0 +#define IF1MSK1_MSK1 _if1msk1.bit._MSK1 +#define IF1MSK1_MSK2 _if1msk1.bit._MSK2 +#define IF1MSK1_MSK3 _if1msk1.bit._MSK3 +#define IF1MSK1_MSK4 _if1msk1.bit._MSK4 +#define IF1MSK1_MSK5 _if1msk1.bit._MSK5 +#define IF1MSK1_MSK6 _if1msk1.bit._MSK6 +#define IF1MSK1_MSK7 _if1msk1.bit._MSK7 +#define IF1MSK1_MSK8 _if1msk1.bit._MSK8 +#define IF1MSK1_MSK9 _if1msk1.bit._MSK9 +#define IF1MSK1_MSK10 _if1msk1.bit._MSK10 +#define IF1MSK1_MSK11 _if1msk1.bit._MSK11 +#define IF1MSK1_MSK12 _if1msk1.bit._MSK12 +#define IF1MSK1_MSK13 _if1msk1.bit._MSK13 +#define IF1MSK1_MSK14 _if1msk1.bit._MSK14 +#define IF1MSK1_MSK15 _if1msk1.bit._MSK15 +#define IF1MSK1_MSK16 _if1msk1.bit._MSK16 +#define IF1MSK1_MSK17 _if1msk1.bit._MSK17 +#define IF1MSK1_MSK18 _if1msk1.bit._MSK18 +#define IF1MSK1_MSK19 _if1msk1.bit._MSK19 +#define IF1MSK1_MSK20 _if1msk1.bit._MSK20 +#define IF1MSK1_MSK21 _if1msk1.bit._MSK21 +#define IF1MSK1_MSK22 _if1msk1.bit._MSK22 +#define IF1MSK1_MSK23 _if1msk1.bit._MSK23 +#define IF1MSK1_MSK24 _if1msk1.bit._MSK24 +#define IF1MSK1_MSK25 _if1msk1.bit._MSK25 +#define IF1MSK1_MSK26 _if1msk1.bit._MSK26 +#define IF1MSK1_MSK27 _if1msk1.bit._MSK27 +#define IF1MSK1_MSK28 _if1msk1.bit._MSK28 +#define IF1MSK1_MDIR _if1msk1.bit._MDIR +#define IF1MSK1_MXTD _if1msk1.bit._MXTD +#define IF1MSK1_MSK _if1msk1.bitc._MSK +__IO_EXTENDED IF1MSK11STR _if1msk11; +#define IF1MSK11 _if1msk11.word +#define IF1MSK11_MSK0 _if1msk11.bit._MSK0 +#define IF1MSK11_MSK1 _if1msk11.bit._MSK1 +#define IF1MSK11_MSK2 _if1msk11.bit._MSK2 +#define IF1MSK11_MSK3 _if1msk11.bit._MSK3 +#define IF1MSK11_MSK4 _if1msk11.bit._MSK4 +#define IF1MSK11_MSK5 _if1msk11.bit._MSK5 +#define IF1MSK11_MSK6 _if1msk11.bit._MSK6 +#define IF1MSK11_MSK7 _if1msk11.bit._MSK7 +#define IF1MSK11_MSK8 _if1msk11.bit._MSK8 +#define IF1MSK11_MSK9 _if1msk11.bit._MSK9 +#define IF1MSK11_MSK10 _if1msk11.bit._MSK10 +#define IF1MSK11_MSK11 _if1msk11.bit._MSK11 +#define IF1MSK11_MSK12 _if1msk11.bit._MSK12 +#define IF1MSK11_MSK13 _if1msk11.bit._MSK13 +#define IF1MSK11_MSK14 _if1msk11.bit._MSK14 +#define IF1MSK11_MSK15 _if1msk11.bit._MSK15 +__IO_EXTENDED IF1MSK1L1STR _if1msk1l1; +#define IF1MSK1L1 _if1msk1l1.byte +#define IF1MSK1L1_MSK0 _if1msk1l1.bit._MSK0 +#define IF1MSK1L1_MSK1 _if1msk1l1.bit._MSK1 +#define IF1MSK1L1_MSK2 _if1msk1l1.bit._MSK2 +#define IF1MSK1L1_MSK3 _if1msk1l1.bit._MSK3 +#define IF1MSK1L1_MSK4 _if1msk1l1.bit._MSK4 +#define IF1MSK1L1_MSK5 _if1msk1l1.bit._MSK5 +#define IF1MSK1L1_MSK6 _if1msk1l1.bit._MSK6 +#define IF1MSK1L1_MSK7 _if1msk1l1.bit._MSK7 +__IO_EXTENDED IF1MSK1H1STR _if1msk1h1; +#define IF1MSK1H1 _if1msk1h1.byte +#define IF1MSK1H1_MSK8 _if1msk1h1.bit._MSK8 +#define IF1MSK1H1_MSK9 _if1msk1h1.bit._MSK9 +#define IF1MSK1H1_MSK10 _if1msk1h1.bit._MSK10 +#define IF1MSK1H1_MSK11 _if1msk1h1.bit._MSK11 +#define IF1MSK1H1_MSK12 _if1msk1h1.bit._MSK12 +#define IF1MSK1H1_MSK13 _if1msk1h1.bit._MSK13 +#define IF1MSK1H1_MSK14 _if1msk1h1.bit._MSK14 +#define IF1MSK1H1_MSK15 _if1msk1h1.bit._MSK15 +__IO_EXTENDED IF1MSK21STR _if1msk21; +#define IF1MSK21 _if1msk21.word +#define IF1MSK21_MSK16 _if1msk21.bit._MSK16 +#define IF1MSK21_MSK17 _if1msk21.bit._MSK17 +#define IF1MSK21_MSK18 _if1msk21.bit._MSK18 +#define IF1MSK21_MSK19 _if1msk21.bit._MSK19 +#define IF1MSK21_MSK20 _if1msk21.bit._MSK20 +#define IF1MSK21_MSK21 _if1msk21.bit._MSK21 +#define IF1MSK21_MSK22 _if1msk21.bit._MSK22 +#define IF1MSK21_MSK23 _if1msk21.bit._MSK23 +#define IF1MSK21_MSK24 _if1msk21.bit._MSK24 +#define IF1MSK21_MSK25 _if1msk21.bit._MSK25 +#define IF1MSK21_MSK26 _if1msk21.bit._MSK26 +#define IF1MSK21_MSK27 _if1msk21.bit._MSK27 +#define IF1MSK21_MSK28 _if1msk21.bit._MSK28 +#define IF1MSK21_MDIR _if1msk21.bit._MDIR +#define IF1MSK21_MXTD _if1msk21.bit._MXTD +__IO_EXTENDED IF1MSK2L1STR _if1msk2l1; +#define IF1MSK2L1 _if1msk2l1.byte +#define IF1MSK2L1_MSK16 _if1msk2l1.bit._MSK16 +#define IF1MSK2L1_MSK17 _if1msk2l1.bit._MSK17 +#define IF1MSK2L1_MSK18 _if1msk2l1.bit._MSK18 +#define IF1MSK2L1_MSK19 _if1msk2l1.bit._MSK19 +#define IF1MSK2L1_MSK20 _if1msk2l1.bit._MSK20 +#define IF1MSK2L1_MSK21 _if1msk2l1.bit._MSK21 +#define IF1MSK2L1_MSK22 _if1msk2l1.bit._MSK22 +#define IF1MSK2L1_MSK23 _if1msk2l1.bit._MSK23 +__IO_EXTENDED IF1MSK2H1STR _if1msk2h1; +#define IF1MSK2H1 _if1msk2h1.byte +#define IF1MSK2H1_MSK24 _if1msk2h1.bit._MSK24 +#define IF1MSK2H1_MSK25 _if1msk2h1.bit._MSK25 +#define IF1MSK2H1_MSK26 _if1msk2h1.bit._MSK26 +#define IF1MSK2H1_MSK27 _if1msk2h1.bit._MSK27 +#define IF1MSK2H1_MSK28 _if1msk2h1.bit._MSK28 +#define IF1MSK2H1_MDIR _if1msk2h1.bit._MDIR +#define IF1MSK2H1_MXTD _if1msk2h1.bit._MXTD +__IO_EXTENDED IF1ARB1STR _if1arb1; +#define IF1ARB1 _if1arb1.lword +#define IF1ARB1_ID0 _if1arb1.bit._ID0 +#define IF1ARB1_ID1 _if1arb1.bit._ID1 +#define IF1ARB1_ID2 _if1arb1.bit._ID2 +#define IF1ARB1_ID3 _if1arb1.bit._ID3 +#define IF1ARB1_ID4 _if1arb1.bit._ID4 +#define IF1ARB1_ID5 _if1arb1.bit._ID5 +#define IF1ARB1_ID6 _if1arb1.bit._ID6 +#define IF1ARB1_ID7 _if1arb1.bit._ID7 +#define IF1ARB1_ID8 _if1arb1.bit._ID8 +#define IF1ARB1_ID9 _if1arb1.bit._ID9 +#define IF1ARB1_ID10 _if1arb1.bit._ID10 +#define IF1ARB1_ID11 _if1arb1.bit._ID11 +#define IF1ARB1_ID12 _if1arb1.bit._ID12 +#define IF1ARB1_ID13 _if1arb1.bit._ID13 +#define IF1ARB1_ID14 _if1arb1.bit._ID14 +#define IF1ARB1_ID15 _if1arb1.bit._ID15 +#define IF1ARB1_ID16 _if1arb1.bit._ID16 +#define IF1ARB1_ID17 _if1arb1.bit._ID17 +#define IF1ARB1_ID18 _if1arb1.bit._ID18 +#define IF1ARB1_ID19 _if1arb1.bit._ID19 +#define IF1ARB1_ID20 _if1arb1.bit._ID20 +#define IF1ARB1_ID21 _if1arb1.bit._ID21 +#define IF1ARB1_ID22 _if1arb1.bit._ID22 +#define IF1ARB1_ID23 _if1arb1.bit._ID23 +#define IF1ARB1_ID24 _if1arb1.bit._ID24 +#define IF1ARB1_ID25 _if1arb1.bit._ID25 +#define IF1ARB1_ID26 _if1arb1.bit._ID26 +#define IF1ARB1_ID27 _if1arb1.bit._ID27 +#define IF1ARB1_ID28 _if1arb1.bit._ID28 +#define IF1ARB1_DIR _if1arb1.bit._DIR +#define IF1ARB1_XTD _if1arb1.bit._XTD +#define IF1ARB1_MSGVAL _if1arb1.bit._MSGVAL +#define IF1ARB1_ID _if1arb1.bitc._ID +__IO_EXTENDED IF1ARB11STR _if1arb11; +#define IF1ARB11 _if1arb11.word +#define IF1ARB11_ID0 _if1arb11.bit._ID0 +#define IF1ARB11_ID1 _if1arb11.bit._ID1 +#define IF1ARB11_ID2 _if1arb11.bit._ID2 +#define IF1ARB11_ID3 _if1arb11.bit._ID3 +#define IF1ARB11_ID4 _if1arb11.bit._ID4 +#define IF1ARB11_ID5 _if1arb11.bit._ID5 +#define IF1ARB11_ID6 _if1arb11.bit._ID6 +#define IF1ARB11_ID7 _if1arb11.bit._ID7 +#define IF1ARB11_ID8 _if1arb11.bit._ID8 +#define IF1ARB11_ID9 _if1arb11.bit._ID9 +#define IF1ARB11_ID10 _if1arb11.bit._ID10 +#define IF1ARB11_ID11 _if1arb11.bit._ID11 +#define IF1ARB11_ID12 _if1arb11.bit._ID12 +#define IF1ARB11_ID13 _if1arb11.bit._ID13 +#define IF1ARB11_ID14 _if1arb11.bit._ID14 +#define IF1ARB11_ID15 _if1arb11.bit._ID15 +__IO_EXTENDED IF1ARB1L1STR _if1arb1l1; +#define IF1ARB1L1 _if1arb1l1.byte +#define IF1ARB1L1_ID0 _if1arb1l1.bit._ID0 +#define IF1ARB1L1_ID1 _if1arb1l1.bit._ID1 +#define IF1ARB1L1_ID2 _if1arb1l1.bit._ID2 +#define IF1ARB1L1_ID3 _if1arb1l1.bit._ID3 +#define IF1ARB1L1_ID4 _if1arb1l1.bit._ID4 +#define IF1ARB1L1_ID5 _if1arb1l1.bit._ID5 +#define IF1ARB1L1_ID6 _if1arb1l1.bit._ID6 +#define IF1ARB1L1_ID7 _if1arb1l1.bit._ID7 +__IO_EXTENDED IF1ARB1H1STR _if1arb1h1; +#define IF1ARB1H1 _if1arb1h1.byte +#define IF1ARB1H1_ID8 _if1arb1h1.bit._ID8 +#define IF1ARB1H1_ID9 _if1arb1h1.bit._ID9 +#define IF1ARB1H1_ID10 _if1arb1h1.bit._ID10 +#define IF1ARB1H1_ID11 _if1arb1h1.bit._ID11 +#define IF1ARB1H1_ID12 _if1arb1h1.bit._ID12 +#define IF1ARB1H1_ID13 _if1arb1h1.bit._ID13 +#define IF1ARB1H1_ID14 _if1arb1h1.bit._ID14 +#define IF1ARB1H1_ID15 _if1arb1h1.bit._ID15 +__IO_EXTENDED IF1ARB21STR _if1arb21; +#define IF1ARB21 _if1arb21.word +#define IF1ARB21_ID16 _if1arb21.bit._ID16 +#define IF1ARB21_ID17 _if1arb21.bit._ID17 +#define IF1ARB21_ID18 _if1arb21.bit._ID18 +#define IF1ARB21_ID19 _if1arb21.bit._ID19 +#define IF1ARB21_ID20 _if1arb21.bit._ID20 +#define IF1ARB21_ID21 _if1arb21.bit._ID21 +#define IF1ARB21_ID22 _if1arb21.bit._ID22 +#define IF1ARB21_ID23 _if1arb21.bit._ID23 +#define IF1ARB21_ID24 _if1arb21.bit._ID24 +#define IF1ARB21_ID25 _if1arb21.bit._ID25 +#define IF1ARB21_ID26 _if1arb21.bit._ID26 +#define IF1ARB21_ID27 _if1arb21.bit._ID27 +#define IF1ARB21_ID28 _if1arb21.bit._ID28 +#define IF1ARB21_DIR _if1arb21.bit._DIR +#define IF1ARB21_XTD _if1arb21.bit._XTD +#define IF1ARB21_MSGVAL _if1arb21.bit._MSGVAL +__IO_EXTENDED IF1ARB2L1STR _if1arb2l1; +#define IF1ARB2L1 _if1arb2l1.byte +#define IF1ARB2L1_ID16 _if1arb2l1.bit._ID16 +#define IF1ARB2L1_ID17 _if1arb2l1.bit._ID17 +#define IF1ARB2L1_ID18 _if1arb2l1.bit._ID18 +#define IF1ARB2L1_ID19 _if1arb2l1.bit._ID19 +#define IF1ARB2L1_ID20 _if1arb2l1.bit._ID20 +#define IF1ARB2L1_ID21 _if1arb2l1.bit._ID21 +#define IF1ARB2L1_ID22 _if1arb2l1.bit._ID22 +#define IF1ARB2L1_ID23 _if1arb2l1.bit._ID23 +__IO_EXTENDED IF1ARB2H1STR _if1arb2h1; +#define IF1ARB2H1 _if1arb2h1.byte +#define IF1ARB2H1_ID24 _if1arb2h1.bit._ID24 +#define IF1ARB2H1_ID25 _if1arb2h1.bit._ID25 +#define IF1ARB2H1_ID26 _if1arb2h1.bit._ID26 +#define IF1ARB2H1_ID27 _if1arb2h1.bit._ID27 +#define IF1ARB2H1_ID28 _if1arb2h1.bit._ID28 +#define IF1ARB2H1_DIR _if1arb2h1.bit._DIR +#define IF1ARB2H1_XTD _if1arb2h1.bit._XTD +#define IF1ARB2H1_MSGVAL _if1arb2h1.bit._MSGVAL +__IO_EXTENDED IF1MCTR1STR _if1mctr1; +#define IF1MCTR1 _if1mctr1.word +#define IF1MCTR1_DLC0 _if1mctr1.bit._DLC0 +#define IF1MCTR1_DLC1 _if1mctr1.bit._DLC1 +#define IF1MCTR1_DLC2 _if1mctr1.bit._DLC2 +#define IF1MCTR1_DLC3 _if1mctr1.bit._DLC3 +#define IF1MCTR1_EOB _if1mctr1.bit._EOB +#define IF1MCTR1_TXRQST _if1mctr1.bit._TXRQST +#define IF1MCTR1_RMTEN _if1mctr1.bit._RMTEN +#define IF1MCTR1_RXIE _if1mctr1.bit._RXIE +#define IF1MCTR1_TXIE _if1mctr1.bit._TXIE +#define IF1MCTR1_UMASK _if1mctr1.bit._UMASK +#define IF1MCTR1_INTPND _if1mctr1.bit._INTPND +#define IF1MCTR1_MSGLST _if1mctr1.bit._MSGLST +#define IF1MCTR1_NEWDAT _if1mctr1.bit._NEWDAT +#define IF1MCTR1_DLC _if1mctr1.bitc._DLC +__IO_EXTENDED IF1MCTRL1STR _if1mctrl1; +#define IF1MCTRL1 _if1mctrl1.byte +#define IF1MCTRL1_DLC0 _if1mctrl1.bit._DLC0 +#define IF1MCTRL1_DLC1 _if1mctrl1.bit._DLC1 +#define IF1MCTRL1_DLC2 _if1mctrl1.bit._DLC2 +#define IF1MCTRL1_DLC3 _if1mctrl1.bit._DLC3 +#define IF1MCTRL1_EOB _if1mctrl1.bit._EOB +#define IF1MCTRL1_DLC _if1mctrl1.bitc._DLC +__IO_EXTENDED IF1MCTRH1STR _if1mctrh1; +#define IF1MCTRH1 _if1mctrh1.byte +#define IF1MCTRH1_TXRQST _if1mctrh1.bit._TXRQST +#define IF1MCTRH1_RMTEN _if1mctrh1.bit._RMTEN +#define IF1MCTRH1_RXIE _if1mctrh1.bit._RXIE +#define IF1MCTRH1_TXIE _if1mctrh1.bit._TXIE +#define IF1MCTRH1_UMASK _if1mctrh1.bit._UMASK +#define IF1MCTRH1_INTPND _if1mctrh1.bit._INTPND +#define IF1MCTRH1_MSGLST _if1mctrh1.bit._MSGLST +#define IF1MCTRH1_NEWDAT _if1mctrh1.bit._NEWDAT +__IO_EXTENDED IF1DTA1STR _if1dta1; +#define IF1DTA1 _if1dta1.lword +__IO_EXTENDED IF1DTA11STR _if1dta11; +#define IF1DTA11 _if1dta11.word +__IO_EXTENDED IF1DTA1L1STR _if1dta1l1; +#define IF1DTA1L1 _if1dta1l1.byte +__IO_EXTENDED IF1DTA1H1STR _if1dta1h1; +#define IF1DTA1H1 _if1dta1h1.byte +__IO_EXTENDED IF1DTA21STR _if1dta21; +#define IF1DTA21 _if1dta21.word +__IO_EXTENDED IF1DTA2L1STR _if1dta2l1; +#define IF1DTA2L1 _if1dta2l1.byte +__IO_EXTENDED IF1DTA2H1STR _if1dta2h1; +#define IF1DTA2H1 _if1dta2h1.byte +__IO_EXTENDED IF1DTB1STR _if1dtb1; +#define IF1DTB1 _if1dtb1.lword +__IO_EXTENDED IF1DTB11STR _if1dtb11; +#define IF1DTB11 _if1dtb11.word +__IO_EXTENDED IF1DTB1L1STR _if1dtb1l1; +#define IF1DTB1L1 _if1dtb1l1.byte +__IO_EXTENDED IF1DTB1H1STR _if1dtb1h1; +#define IF1DTB1H1 _if1dtb1h1.byte +__IO_EXTENDED IF1DTB21STR _if1dtb21; +#define IF1DTB21 _if1dtb21.word +__IO_EXTENDED IF1DTB2L1STR _if1dtb2l1; +#define IF1DTB2L1 _if1dtb2l1.byte +__IO_EXTENDED IF1DTB2H1STR _if1dtb2h1; +#define IF1DTB2H1 _if1dtb2h1.byte +__IO_EXTENDED IF2CREQ1STR _if2creq1; +#define IF2CREQ1 _if2creq1.word +#define IF2CREQ1_MSGN0 _if2creq1.bit._MSGN0 +#define IF2CREQ1_MSGN1 _if2creq1.bit._MSGN1 +#define IF2CREQ1_MSGN2 _if2creq1.bit._MSGN2 +#define IF2CREQ1_MSGN3 _if2creq1.bit._MSGN3 +#define IF2CREQ1_MSGN4 _if2creq1.bit._MSGN4 +#define IF2CREQ1_MSGN5 _if2creq1.bit._MSGN5 +#define IF2CREQ1_MSGN6 _if2creq1.bit._MSGN6 +#define IF2CREQ1_MSGN7 _if2creq1.bit._MSGN7 +#define IF2CREQ1_BUSY _if2creq1.bit._BUSY +__IO_EXTENDED IF2CREQL1STR _if2creql1; +#define IF2CREQL1 _if2creql1.byte +#define IF2CREQL1_MSGN0 _if2creql1.bit._MSGN0 +#define IF2CREQL1_MSGN1 _if2creql1.bit._MSGN1 +#define IF2CREQL1_MSGN2 _if2creql1.bit._MSGN2 +#define IF2CREQL1_MSGN3 _if2creql1.bit._MSGN3 +#define IF2CREQL1_MSGN4 _if2creql1.bit._MSGN4 +#define IF2CREQL1_MSGN5 _if2creql1.bit._MSGN5 +#define IF2CREQL1_MSGN6 _if2creql1.bit._MSGN6 +#define IF2CREQL1_MSGN7 _if2creql1.bit._MSGN7 +__IO_EXTENDED IF2CREQH1STR _if2creqh1; +#define IF2CREQH1 _if2creqh1.byte +#define IF2CREQH1_BUSY _if2creqh1.bit._BUSY +__IO_EXTENDED IF2CMSK1STR _if2cmsk1; +#define IF2CMSK1 _if2cmsk1.word +#define IF2CMSK1_DATAB _if2cmsk1.bit._DATAB +#define IF2CMSK1_DATAA _if2cmsk1.bit._DATAA +#define IF2CMSK1_TXREQ _if2cmsk1.bit._TXREQ +#define IF2CMSK1_CIP _if2cmsk1.bit._CIP +#define IF2CMSK1_CONTROL _if2cmsk1.bit._CONTROL +#define IF2CMSK1_ARB _if2cmsk1.bit._ARB +#define IF2CMSK1_MASK _if2cmsk1.bit._MASK +#define IF2CMSK1_WRRD _if2cmsk1.bit._WRRD +__IO_EXTENDED IF2CMSKL1STR _if2cmskl1; +#define IF2CMSKL1 _if2cmskl1.byte +#define IF2CMSKL1_DATAB _if2cmskl1.bit._DATAB +#define IF2CMSKL1_DATAA _if2cmskl1.bit._DATAA +#define IF2CMSKL1_TXREQ _if2cmskl1.bit._TXREQ +#define IF2CMSKL1_CIP _if2cmskl1.bit._CIP +#define IF2CMSKL1_CONTROL _if2cmskl1.bit._CONTROL +#define IF2CMSKL1_ARB _if2cmskl1.bit._ARB +#define IF2CMSKL1_MASK _if2cmskl1.bit._MASK +#define IF2CMSKL1_WRRD _if2cmskl1.bit._WRRD +__IO_EXTENDED IF2CMSKH1STR _if2cmskh1; +#define IF2CMSKH1 _if2cmskh1.byte +__IO_EXTENDED IF2MSK1STR _if2msk1; +#define IF2MSK1 _if2msk1.lword +#define IF2MSK1_MSK0 _if2msk1.bit._MSK0 +#define IF2MSK1_MSK1 _if2msk1.bit._MSK1 +#define IF2MSK1_MSK2 _if2msk1.bit._MSK2 +#define IF2MSK1_MSK3 _if2msk1.bit._MSK3 +#define IF2MSK1_MSK4 _if2msk1.bit._MSK4 +#define IF2MSK1_MSK5 _if2msk1.bit._MSK5 +#define IF2MSK1_MSK6 _if2msk1.bit._MSK6 +#define IF2MSK1_MSK7 _if2msk1.bit._MSK7 +#define IF2MSK1_MSK8 _if2msk1.bit._MSK8 +#define IF2MSK1_MSK9 _if2msk1.bit._MSK9 +#define IF2MSK1_MSK10 _if2msk1.bit._MSK10 +#define IF2MSK1_MSK11 _if2msk1.bit._MSK11 +#define IF2MSK1_MSK12 _if2msk1.bit._MSK12 +#define IF2MSK1_MSK13 _if2msk1.bit._MSK13 +#define IF2MSK1_MSK14 _if2msk1.bit._MSK14 +#define IF2MSK1_MSK15 _if2msk1.bit._MSK15 +#define IF2MSK1_MSK16 _if2msk1.bit._MSK16 +#define IF2MSK1_MSK17 _if2msk1.bit._MSK17 +#define IF2MSK1_MSK18 _if2msk1.bit._MSK18 +#define IF2MSK1_MSK19 _if2msk1.bit._MSK19 +#define IF2MSK1_MSK20 _if2msk1.bit._MSK20 +#define IF2MSK1_MSK21 _if2msk1.bit._MSK21 +#define IF2MSK1_MSK22 _if2msk1.bit._MSK22 +#define IF2MSK1_MSK23 _if2msk1.bit._MSK23 +#define IF2MSK1_MSK24 _if2msk1.bit._MSK24 +#define IF2MSK1_MSK25 _if2msk1.bit._MSK25 +#define IF2MSK1_MSK26 _if2msk1.bit._MSK26 +#define IF2MSK1_MSK27 _if2msk1.bit._MSK27 +#define IF2MSK1_MSK28 _if2msk1.bit._MSK28 +#define IF2MSK1_MDIR _if2msk1.bit._MDIR +#define IF2MSK1_MXTD _if2msk1.bit._MXTD +#define IF2MSK1_MSK _if2msk1.bitc._MSK +__IO_EXTENDED IF2MSK11STR _if2msk11; +#define IF2MSK11 _if2msk11.word +#define IF2MSK11_MSK0 _if2msk11.bit._MSK0 +#define IF2MSK11_MSK1 _if2msk11.bit._MSK1 +#define IF2MSK11_MSK2 _if2msk11.bit._MSK2 +#define IF2MSK11_MSK3 _if2msk11.bit._MSK3 +#define IF2MSK11_MSK4 _if2msk11.bit._MSK4 +#define IF2MSK11_MSK5 _if2msk11.bit._MSK5 +#define IF2MSK11_MSK6 _if2msk11.bit._MSK6 +#define IF2MSK11_MSK7 _if2msk11.bit._MSK7 +#define IF2MSK11_MSK8 _if2msk11.bit._MSK8 +#define IF2MSK11_MSK9 _if2msk11.bit._MSK9 +#define IF2MSK11_MSK10 _if2msk11.bit._MSK10 +#define IF2MSK11_MSK11 _if2msk11.bit._MSK11 +#define IF2MSK11_MSK12 _if2msk11.bit._MSK12 +#define IF2MSK11_MSK13 _if2msk11.bit._MSK13 +#define IF2MSK11_MSK14 _if2msk11.bit._MSK14 +#define IF2MSK11_MSK15 _if2msk11.bit._MSK15 +__IO_EXTENDED IF2MSK1L1STR _if2msk1l1; +#define IF2MSK1L1 _if2msk1l1.byte +#define IF2MSK1L1_MSK0 _if2msk1l1.bit._MSK0 +#define IF2MSK1L1_MSK1 _if2msk1l1.bit._MSK1 +#define IF2MSK1L1_MSK2 _if2msk1l1.bit._MSK2 +#define IF2MSK1L1_MSK3 _if2msk1l1.bit._MSK3 +#define IF2MSK1L1_MSK4 _if2msk1l1.bit._MSK4 +#define IF2MSK1L1_MSK5 _if2msk1l1.bit._MSK5 +#define IF2MSK1L1_MSK6 _if2msk1l1.bit._MSK6 +#define IF2MSK1L1_MSK7 _if2msk1l1.bit._MSK7 +__IO_EXTENDED IF2MSK1H1STR _if2msk1h1; +#define IF2MSK1H1 _if2msk1h1.byte +#define IF2MSK1H1_MSK8 _if2msk1h1.bit._MSK8 +#define IF2MSK1H1_MSK9 _if2msk1h1.bit._MSK9 +#define IF2MSK1H1_MSK10 _if2msk1h1.bit._MSK10 +#define IF2MSK1H1_MSK11 _if2msk1h1.bit._MSK11 +#define IF2MSK1H1_MSK12 _if2msk1h1.bit._MSK12 +#define IF2MSK1H1_MSK13 _if2msk1h1.bit._MSK13 +#define IF2MSK1H1_MSK14 _if2msk1h1.bit._MSK14 +#define IF2MSK1H1_MSK15 _if2msk1h1.bit._MSK15 +__IO_EXTENDED IF2MSK21STR _if2msk21; +#define IF2MSK21 _if2msk21.word +#define IF2MSK21_MSK16 _if2msk21.bit._MSK16 +#define IF2MSK21_MSK17 _if2msk21.bit._MSK17 +#define IF2MSK21_MSK18 _if2msk21.bit._MSK18 +#define IF2MSK21_MSK19 _if2msk21.bit._MSK19 +#define IF2MSK21_MSK20 _if2msk21.bit._MSK20 +#define IF2MSK21_MSK21 _if2msk21.bit._MSK21 +#define IF2MSK21_MSK22 _if2msk21.bit._MSK22 +#define IF2MSK21_MSK23 _if2msk21.bit._MSK23 +#define IF2MSK21_MSK24 _if2msk21.bit._MSK24 +#define IF2MSK21_MSK25 _if2msk21.bit._MSK25 +#define IF2MSK21_MSK26 _if2msk21.bit._MSK26 +#define IF2MSK21_MSK27 _if2msk21.bit._MSK27 +#define IF2MSK21_MSK28 _if2msk21.bit._MSK28 +#define IF2MSK21_MDIR _if2msk21.bit._MDIR +#define IF2MSK21_MXTD _if2msk21.bit._MXTD +__IO_EXTENDED IF2MSK2L1STR _if2msk2l1; +#define IF2MSK2L1 _if2msk2l1.byte +#define IF2MSK2L1_MSK16 _if2msk2l1.bit._MSK16 +#define IF2MSK2L1_MSK17 _if2msk2l1.bit._MSK17 +#define IF2MSK2L1_MSK18 _if2msk2l1.bit._MSK18 +#define IF2MSK2L1_MSK19 _if2msk2l1.bit._MSK19 +#define IF2MSK2L1_MSK20 _if2msk2l1.bit._MSK20 +#define IF2MSK2L1_MSK21 _if2msk2l1.bit._MSK21 +#define IF2MSK2L1_MSK22 _if2msk2l1.bit._MSK22 +#define IF2MSK2L1_MSK23 _if2msk2l1.bit._MSK23 +__IO_EXTENDED IF2MSK2H1STR _if2msk2h1; +#define IF2MSK2H1 _if2msk2h1.byte +#define IF2MSK2H1_MSK24 _if2msk2h1.bit._MSK24 +#define IF2MSK2H1_MSK25 _if2msk2h1.bit._MSK25 +#define IF2MSK2H1_MSK26 _if2msk2h1.bit._MSK26 +#define IF2MSK2H1_MSK27 _if2msk2h1.bit._MSK27 +#define IF2MSK2H1_MSK28 _if2msk2h1.bit._MSK28 +#define IF2MSK2H1_MDIR _if2msk2h1.bit._MDIR +#define IF2MSK2H1_MXTD _if2msk2h1.bit._MXTD +__IO_EXTENDED IF2ARB1STR _if2arb1; +#define IF2ARB1 _if2arb1.lword +#define IF2ARB1_ID0 _if2arb1.bit._ID0 +#define IF2ARB1_ID1 _if2arb1.bit._ID1 +#define IF2ARB1_ID2 _if2arb1.bit._ID2 +#define IF2ARB1_ID3 _if2arb1.bit._ID3 +#define IF2ARB1_ID4 _if2arb1.bit._ID4 +#define IF2ARB1_ID5 _if2arb1.bit._ID5 +#define IF2ARB1_ID6 _if2arb1.bit._ID6 +#define IF2ARB1_ID7 _if2arb1.bit._ID7 +#define IF2ARB1_ID8 _if2arb1.bit._ID8 +#define IF2ARB1_ID9 _if2arb1.bit._ID9 +#define IF2ARB1_ID10 _if2arb1.bit._ID10 +#define IF2ARB1_ID11 _if2arb1.bit._ID11 +#define IF2ARB1_ID12 _if2arb1.bit._ID12 +#define IF2ARB1_ID13 _if2arb1.bit._ID13 +#define IF2ARB1_ID14 _if2arb1.bit._ID14 +#define IF2ARB1_ID15 _if2arb1.bit._ID15 +#define IF2ARB1_ID16 _if2arb1.bit._ID16 +#define IF2ARB1_ID17 _if2arb1.bit._ID17 +#define IF2ARB1_ID18 _if2arb1.bit._ID18 +#define IF2ARB1_ID19 _if2arb1.bit._ID19 +#define IF2ARB1_ID20 _if2arb1.bit._ID20 +#define IF2ARB1_ID21 _if2arb1.bit._ID21 +#define IF2ARB1_ID22 _if2arb1.bit._ID22 +#define IF2ARB1_ID23 _if2arb1.bit._ID23 +#define IF2ARB1_ID24 _if2arb1.bit._ID24 +#define IF2ARB1_ID25 _if2arb1.bit._ID25 +#define IF2ARB1_ID26 _if2arb1.bit._ID26 +#define IF2ARB1_ID27 _if2arb1.bit._ID27 +#define IF2ARB1_ID28 _if2arb1.bit._ID28 +#define IF2ARB1_DIR _if2arb1.bit._DIR +#define IF2ARB1_XTD _if2arb1.bit._XTD +#define IF2ARB1_MSGVAL _if2arb1.bit._MSGVAL +#define IF2ARB1_ID _if2arb1.bitc._ID +__IO_EXTENDED IF2ARB11STR _if2arb11; +#define IF2ARB11 _if2arb11.word +#define IF2ARB11_ID0 _if2arb11.bit._ID0 +#define IF2ARB11_ID1 _if2arb11.bit._ID1 +#define IF2ARB11_ID2 _if2arb11.bit._ID2 +#define IF2ARB11_ID3 _if2arb11.bit._ID3 +#define IF2ARB11_ID4 _if2arb11.bit._ID4 +#define IF2ARB11_ID5 _if2arb11.bit._ID5 +#define IF2ARB11_ID6 _if2arb11.bit._ID6 +#define IF2ARB11_ID7 _if2arb11.bit._ID7 +#define IF2ARB11_ID8 _if2arb11.bit._ID8 +#define IF2ARB11_ID9 _if2arb11.bit._ID9 +#define IF2ARB11_ID10 _if2arb11.bit._ID10 +#define IF2ARB11_ID11 _if2arb11.bit._ID11 +#define IF2ARB11_ID12 _if2arb11.bit._ID12 +#define IF2ARB11_ID13 _if2arb11.bit._ID13 +#define IF2ARB11_ID14 _if2arb11.bit._ID14 +#define IF2ARB11_ID15 _if2arb11.bit._ID15 +__IO_EXTENDED IF2ARB1L1STR _if2arb1l1; +#define IF2ARB1L1 _if2arb1l1.byte +#define IF2ARB1L1_ID0 _if2arb1l1.bit._ID0 +#define IF2ARB1L1_ID1 _if2arb1l1.bit._ID1 +#define IF2ARB1L1_ID2 _if2arb1l1.bit._ID2 +#define IF2ARB1L1_ID3 _if2arb1l1.bit._ID3 +#define IF2ARB1L1_ID4 _if2arb1l1.bit._ID4 +#define IF2ARB1L1_ID5 _if2arb1l1.bit._ID5 +#define IF2ARB1L1_ID6 _if2arb1l1.bit._ID6 +#define IF2ARB1L1_ID7 _if2arb1l1.bit._ID7 +__IO_EXTENDED IF2ARB1H1STR _if2arb1h1; +#define IF2ARB1H1 _if2arb1h1.byte +#define IF2ARB1H1_ID8 _if2arb1h1.bit._ID8 +#define IF2ARB1H1_ID9 _if2arb1h1.bit._ID9 +#define IF2ARB1H1_ID10 _if2arb1h1.bit._ID10 +#define IF2ARB1H1_ID11 _if2arb1h1.bit._ID11 +#define IF2ARB1H1_ID12 _if2arb1h1.bit._ID12 +#define IF2ARB1H1_ID13 _if2arb1h1.bit._ID13 +#define IF2ARB1H1_ID14 _if2arb1h1.bit._ID14 +#define IF2ARB1H1_ID15 _if2arb1h1.bit._ID15 +__IO_EXTENDED IF2ARB21STR _if2arb21; +#define IF2ARB21 _if2arb21.word +#define IF2ARB21_ID16 _if2arb21.bit._ID16 +#define IF2ARB21_ID17 _if2arb21.bit._ID17 +#define IF2ARB21_ID18 _if2arb21.bit._ID18 +#define IF2ARB21_ID19 _if2arb21.bit._ID19 +#define IF2ARB21_ID20 _if2arb21.bit._ID20 +#define IF2ARB21_ID21 _if2arb21.bit._ID21 +#define IF2ARB21_ID22 _if2arb21.bit._ID22 +#define IF2ARB21_ID23 _if2arb21.bit._ID23 +#define IF2ARB21_ID24 _if2arb21.bit._ID24 +#define IF2ARB21_ID25 _if2arb21.bit._ID25 +#define IF2ARB21_ID26 _if2arb21.bit._ID26 +#define IF2ARB21_ID27 _if2arb21.bit._ID27 +#define IF2ARB21_ID28 _if2arb21.bit._ID28 +#define IF2ARB21_DIR _if2arb21.bit._DIR +#define IF2ARB21_XTD _if2arb21.bit._XTD +#define IF2ARB21_MSGVAL _if2arb21.bit._MSGVAL +__IO_EXTENDED IF2ARB2L1STR _if2arb2l1; +#define IF2ARB2L1 _if2arb2l1.byte +#define IF2ARB2L1_ID16 _if2arb2l1.bit._ID16 +#define IF2ARB2L1_ID17 _if2arb2l1.bit._ID17 +#define IF2ARB2L1_ID18 _if2arb2l1.bit._ID18 +#define IF2ARB2L1_ID19 _if2arb2l1.bit._ID19 +#define IF2ARB2L1_ID20 _if2arb2l1.bit._ID20 +#define IF2ARB2L1_ID21 _if2arb2l1.bit._ID21 +#define IF2ARB2L1_ID22 _if2arb2l1.bit._ID22 +#define IF2ARB2L1_ID23 _if2arb2l1.bit._ID23 +__IO_EXTENDED IF2ARB2H1STR _if2arb2h1; +#define IF2ARB2H1 _if2arb2h1.byte +#define IF2ARB2H1_ID24 _if2arb2h1.bit._ID24 +#define IF2ARB2H1_ID25 _if2arb2h1.bit._ID25 +#define IF2ARB2H1_ID26 _if2arb2h1.bit._ID26 +#define IF2ARB2H1_ID27 _if2arb2h1.bit._ID27 +#define IF2ARB2H1_ID28 _if2arb2h1.bit._ID28 +#define IF2ARB2H1_DIR _if2arb2h1.bit._DIR +#define IF2ARB2H1_XTD _if2arb2h1.bit._XTD +#define IF2ARB2H1_MSGVAL _if2arb2h1.bit._MSGVAL +__IO_EXTENDED IF2MCTR1STR _if2mctr1; +#define IF2MCTR1 _if2mctr1.word +#define IF2MCTR1_DLC0 _if2mctr1.bit._DLC0 +#define IF2MCTR1_DLC1 _if2mctr1.bit._DLC1 +#define IF2MCTR1_DLC2 _if2mctr1.bit._DLC2 +#define IF2MCTR1_DLC3 _if2mctr1.bit._DLC3 +#define IF2MCTR1_EOB _if2mctr1.bit._EOB +#define IF2MCTR1_TXRQST _if2mctr1.bit._TXRQST +#define IF2MCTR1_RMTEN _if2mctr1.bit._RMTEN +#define IF2MCTR1_RXIE _if2mctr1.bit._RXIE +#define IF2MCTR1_TXIE _if2mctr1.bit._TXIE +#define IF2MCTR1_UMASK _if2mctr1.bit._UMASK +#define IF2MCTR1_INTPND _if2mctr1.bit._INTPND +#define IF2MCTR1_MSGLST _if2mctr1.bit._MSGLST +#define IF2MCTR1_NEWDAT _if2mctr1.bit._NEWDAT +#define IF2MCTR1_DLC _if2mctr1.bitc._DLC +__IO_EXTENDED IF2MCTRL1STR _if2mctrl1; +#define IF2MCTRL1 _if2mctrl1.byte +#define IF2MCTRL1_DLC0 _if2mctrl1.bit._DLC0 +#define IF2MCTRL1_DLC1 _if2mctrl1.bit._DLC1 +#define IF2MCTRL1_DLC2 _if2mctrl1.bit._DLC2 +#define IF2MCTRL1_DLC3 _if2mctrl1.bit._DLC3 +#define IF2MCTRL1_EOB _if2mctrl1.bit._EOB +#define IF2MCTRL1_DLC _if2mctrl1.bitc._DLC +__IO_EXTENDED IF2MCTRH1STR _if2mctrh1; +#define IF2MCTRH1 _if2mctrh1.byte +#define IF2MCTRH1_TXRQST _if2mctrh1.bit._TXRQST +#define IF2MCTRH1_RMTEN _if2mctrh1.bit._RMTEN +#define IF2MCTRH1_RXIE _if2mctrh1.bit._RXIE +#define IF2MCTRH1_TXIE _if2mctrh1.bit._TXIE +#define IF2MCTRH1_UMASK _if2mctrh1.bit._UMASK +#define IF2MCTRH1_INTPND _if2mctrh1.bit._INTPND +#define IF2MCTRH1_MSGLST _if2mctrh1.bit._MSGLST +#define IF2MCTRH1_NEWDAT _if2mctrh1.bit._NEWDAT +__IO_EXTENDED IF2DTA1STR _if2dta1; +#define IF2DTA1 _if2dta1.lword +__IO_EXTENDED IF2DTA11STR _if2dta11; +#define IF2DTA11 _if2dta11.word +__IO_EXTENDED IF2DTA1L1STR _if2dta1l1; +#define IF2DTA1L1 _if2dta1l1.byte +__IO_EXTENDED IF2DTA1H1STR _if2dta1h1; +#define IF2DTA1H1 _if2dta1h1.byte +__IO_EXTENDED IF2DTA21STR _if2dta21; +#define IF2DTA21 _if2dta21.word +__IO_EXTENDED IF2DTA2L1STR _if2dta2l1; +#define IF2DTA2L1 _if2dta2l1.byte +__IO_EXTENDED IF2DTA2H1STR _if2dta2h1; +#define IF2DTA2H1 _if2dta2h1.byte +__IO_EXTENDED IF2DTB1STR _if2dtb1; +#define IF2DTB1 _if2dtb1.lword +__IO_EXTENDED IF2DTB11STR _if2dtb11; +#define IF2DTB11 _if2dtb11.word +__IO_EXTENDED IF2DTB1L1STR _if2dtb1l1; +#define IF2DTB1L1 _if2dtb1l1.byte +__IO_EXTENDED IF2DTB1H1STR _if2dtb1h1; +#define IF2DTB1H1 _if2dtb1h1.byte +__IO_EXTENDED IF2DTB21STR _if2dtb21; +#define IF2DTB21 _if2dtb21.word +__IO_EXTENDED IF2DTB2L1STR _if2dtb2l1; +#define IF2DTB2L1 _if2dtb2l1.byte +__IO_EXTENDED IF2DTB2H1STR _if2dtb2h1; +#define IF2DTB2H1 _if2dtb2h1.byte +__IO_EXTENDED TREQR1STR _treqr1; +#define TREQR1 _treqr1.lword +#define TREQR1_TXRQST1 _treqr1.bit._TXRQST1 +#define TREQR1_TXRQST2 _treqr1.bit._TXRQST2 +#define TREQR1_TXRQST3 _treqr1.bit._TXRQST3 +#define TREQR1_TXRQST4 _treqr1.bit._TXRQST4 +#define TREQR1_TXRQST5 _treqr1.bit._TXRQST5 +#define TREQR1_TXRQST6 _treqr1.bit._TXRQST6 +#define TREQR1_TXRQST7 _treqr1.bit._TXRQST7 +#define TREQR1_TXRQST8 _treqr1.bit._TXRQST8 +#define TREQR1_TXRQST9 _treqr1.bit._TXRQST9 +#define TREQR1_TXRQST10 _treqr1.bit._TXRQST10 +#define TREQR1_TXRQST11 _treqr1.bit._TXRQST11 +#define TREQR1_TXRQST12 _treqr1.bit._TXRQST12 +#define TREQR1_TXRQST13 _treqr1.bit._TXRQST13 +#define TREQR1_TXRQST14 _treqr1.bit._TXRQST14 +#define TREQR1_TXRQST15 _treqr1.bit._TXRQST15 +#define TREQR1_TXRQST16 _treqr1.bit._TXRQST16 +#define TREQR1_TXRQST17 _treqr1.bit._TXRQST17 +#define TREQR1_TXRQST18 _treqr1.bit._TXRQST18 +#define TREQR1_TXRQST19 _treqr1.bit._TXRQST19 +#define TREQR1_TXRQST20 _treqr1.bit._TXRQST20 +#define TREQR1_TXRQST21 _treqr1.bit._TXRQST21 +#define TREQR1_TXRQST22 _treqr1.bit._TXRQST22 +#define TREQR1_TXRQST23 _treqr1.bit._TXRQST23 +#define TREQR1_TXRQST24 _treqr1.bit._TXRQST24 +#define TREQR1_TXRQST25 _treqr1.bit._TXRQST25 +#define TREQR1_TXRQST26 _treqr1.bit._TXRQST26 +#define TREQR1_TXRQST27 _treqr1.bit._TXRQST27 +#define TREQR1_TXRQST28 _treqr1.bit._TXRQST28 +#define TREQR1_TXRQST29 _treqr1.bit._TXRQST29 +#define TREQR1_TXRQST30 _treqr1.bit._TXRQST30 +#define TREQR1_TXRQST31 _treqr1.bit._TXRQST31 +#define TREQR1_TXRQST32 _treqr1.bit._TXRQST32 +#define TREQR1_TXRQST _treqr1.bitc._TXRQST +__IO_EXTENDED TREQR11STR _treqr11; +#define TREQR11 _treqr11.word +#define TREQR11_TXRQST1 _treqr11.bit._TXRQST1 +#define TREQR11_TXRQST2 _treqr11.bit._TXRQST2 +#define TREQR11_TXRQST3 _treqr11.bit._TXRQST3 +#define TREQR11_TXRQST4 _treqr11.bit._TXRQST4 +#define TREQR11_TXRQST5 _treqr11.bit._TXRQST5 +#define TREQR11_TXRQST6 _treqr11.bit._TXRQST6 +#define TREQR11_TXRQST7 _treqr11.bit._TXRQST7 +#define TREQR11_TXRQST8 _treqr11.bit._TXRQST8 +#define TREQR11_TXRQST9 _treqr11.bit._TXRQST9 +#define TREQR11_TXRQST10 _treqr11.bit._TXRQST10 +#define TREQR11_TXRQST11 _treqr11.bit._TXRQST11 +#define TREQR11_TXRQST12 _treqr11.bit._TXRQST12 +#define TREQR11_TXRQST13 _treqr11.bit._TXRQST13 +#define TREQR11_TXRQST14 _treqr11.bit._TXRQST14 +#define TREQR11_TXRQST15 _treqr11.bit._TXRQST15 +#define TREQR11_TXRQST16 _treqr11.bit._TXRQST16 +__IO_EXTENDED TREQR1L1STR _treqr1l1; +#define TREQR1L1 _treqr1l1.byte +#define TREQR1L1_TXRQST1 _treqr1l1.bit._TXRQST1 +#define TREQR1L1_TXRQST2 _treqr1l1.bit._TXRQST2 +#define TREQR1L1_TXRQST3 _treqr1l1.bit._TXRQST3 +#define TREQR1L1_TXRQST4 _treqr1l1.bit._TXRQST4 +#define TREQR1L1_TXRQST5 _treqr1l1.bit._TXRQST5 +#define TREQR1L1_TXRQST6 _treqr1l1.bit._TXRQST6 +#define TREQR1L1_TXRQST7 _treqr1l1.bit._TXRQST7 +#define TREQR1L1_TXRQST8 _treqr1l1.bit._TXRQST8 +__IO_EXTENDED TREQR1H1STR _treqr1h1; +#define TREQR1H1 _treqr1h1.byte +#define TREQR1H1_TXRQST9 _treqr1h1.bit._TXRQST9 +#define TREQR1H1_TXRQST10 _treqr1h1.bit._TXRQST10 +#define TREQR1H1_TXRQST11 _treqr1h1.bit._TXRQST11 +#define TREQR1H1_TXRQST12 _treqr1h1.bit._TXRQST12 +#define TREQR1H1_TXRQST13 _treqr1h1.bit._TXRQST13 +#define TREQR1H1_TXRQST14 _treqr1h1.bit._TXRQST14 +#define TREQR1H1_TXRQST15 _treqr1h1.bit._TXRQST15 +#define TREQR1H1_TXRQST16 _treqr1h1.bit._TXRQST16 +__IO_EXTENDED TREQR21STR _treqr21; +#define TREQR21 _treqr21.word +#define TREQR21_TXRQST17 _treqr21.bit._TXRQST17 +#define TREQR21_TXRQST18 _treqr21.bit._TXRQST18 +#define TREQR21_TXRQST19 _treqr21.bit._TXRQST19 +#define TREQR21_TXRQST20 _treqr21.bit._TXRQST20 +#define TREQR21_TXRQST21 _treqr21.bit._TXRQST21 +#define TREQR21_TXRQST22 _treqr21.bit._TXRQST22 +#define TREQR21_TXRQST23 _treqr21.bit._TXRQST23 +#define TREQR21_TXRQST24 _treqr21.bit._TXRQST24 +#define TREQR21_TXRQST25 _treqr21.bit._TXRQST25 +#define TREQR21_TXRQST26 _treqr21.bit._TXRQST26 +#define TREQR21_TXRQST27 _treqr21.bit._TXRQST27 +#define TREQR21_TXRQST28 _treqr21.bit._TXRQST28 +#define TREQR21_TXRQST29 _treqr21.bit._TXRQST29 +#define TREQR21_TXRQST30 _treqr21.bit._TXRQST30 +#define TREQR21_TXRQST31 _treqr21.bit._TXRQST31 +#define TREQR21_TXRQST32 _treqr21.bit._TXRQST32 +__IO_EXTENDED TREQR2L1STR _treqr2l1; +#define TREQR2L1 _treqr2l1.byte +#define TREQR2L1_TXRQST17 _treqr2l1.bit._TXRQST17 +#define TREQR2L1_TXRQST18 _treqr2l1.bit._TXRQST18 +#define TREQR2L1_TXRQST19 _treqr2l1.bit._TXRQST19 +#define TREQR2L1_TXRQST20 _treqr2l1.bit._TXRQST20 +#define TREQR2L1_TXRQST21 _treqr2l1.bit._TXRQST21 +#define TREQR2L1_TXRQST22 _treqr2l1.bit._TXRQST22 +#define TREQR2L1_TXRQST23 _treqr2l1.bit._TXRQST23 +#define TREQR2L1_TXRQST24 _treqr2l1.bit._TXRQST24 +__IO_EXTENDED TREQR2H1STR _treqr2h1; +#define TREQR2H1 _treqr2h1.byte +#define TREQR2H1_TXRQST25 _treqr2h1.bit._TXRQST25 +#define TREQR2H1_TXRQST26 _treqr2h1.bit._TXRQST26 +#define TREQR2H1_TXRQST27 _treqr2h1.bit._TXRQST27 +#define TREQR2H1_TXRQST28 _treqr2h1.bit._TXRQST28 +#define TREQR2H1_TXRQST29 _treqr2h1.bit._TXRQST29 +#define TREQR2H1_TXRQST30 _treqr2h1.bit._TXRQST30 +#define TREQR2H1_TXRQST31 _treqr2h1.bit._TXRQST31 +#define TREQR2H1_TXRQST32 _treqr2h1.bit._TXRQST32 +__IO_EXTENDED NEWDT1STR _newdt1; +#define NEWDT1 _newdt1.lword +#define NEWDT1_NEWDAT1 _newdt1.bit._NEWDAT1 +#define NEWDT1_NEWDAT2 _newdt1.bit._NEWDAT2 +#define NEWDT1_NEWDAT3 _newdt1.bit._NEWDAT3 +#define NEWDT1_NEWDAT4 _newdt1.bit._NEWDAT4 +#define NEWDT1_NEWDAT5 _newdt1.bit._NEWDAT5 +#define NEWDT1_NEWDAT6 _newdt1.bit._NEWDAT6 +#define NEWDT1_NEWDAT7 _newdt1.bit._NEWDAT7 +#define NEWDT1_NEWDAT8 _newdt1.bit._NEWDAT8 +#define NEWDT1_NEWDAT9 _newdt1.bit._NEWDAT9 +#define NEWDT1_NEWDAT10 _newdt1.bit._NEWDAT10 +#define NEWDT1_NEWDAT11 _newdt1.bit._NEWDAT11 +#define NEWDT1_NEWDAT12 _newdt1.bit._NEWDAT12 +#define NEWDT1_NEWDAT13 _newdt1.bit._NEWDAT13 +#define NEWDT1_NEWDAT14 _newdt1.bit._NEWDAT14 +#define NEWDT1_NEWDAT15 _newdt1.bit._NEWDAT15 +#define NEWDT1_NEWDAT16 _newdt1.bit._NEWDAT16 +#define NEWDT1_NEWDAT17 _newdt1.bit._NEWDAT17 +#define NEWDT1_NEWDAT18 _newdt1.bit._NEWDAT18 +#define NEWDT1_NEWDAT19 _newdt1.bit._NEWDAT19 +#define NEWDT1_NEWDAT20 _newdt1.bit._NEWDAT20 +#define NEWDT1_NEWDAT21 _newdt1.bit._NEWDAT21 +#define NEWDT1_NEWDAT22 _newdt1.bit._NEWDAT22 +#define NEWDT1_NEWDAT23 _newdt1.bit._NEWDAT23 +#define NEWDT1_NEWDAT24 _newdt1.bit._NEWDAT24 +#define NEWDT1_NEWDAT25 _newdt1.bit._NEWDAT25 +#define NEWDT1_NEWDAT26 _newdt1.bit._NEWDAT26 +#define NEWDT1_NEWDAT27 _newdt1.bit._NEWDAT27 +#define NEWDT1_NEWDAT28 _newdt1.bit._NEWDAT28 +#define NEWDT1_NEWDAT29 _newdt1.bit._NEWDAT29 +#define NEWDT1_NEWDAT30 _newdt1.bit._NEWDAT30 +#define NEWDT1_NEWDAT31 _newdt1.bit._NEWDAT31 +#define NEWDT1_NEWDAT32 _newdt1.bit._NEWDAT32 +#define NEWDT1_NEWDAT _newdt1.bitc._NEWDAT +__IO_EXTENDED NEWDT11STR _newdt11; +#define NEWDT11 _newdt11.word +#define NEWDT11_NEWDAT1 _newdt11.bit._NEWDAT1 +#define NEWDT11_NEWDAT2 _newdt11.bit._NEWDAT2 +#define NEWDT11_NEWDAT3 _newdt11.bit._NEWDAT3 +#define NEWDT11_NEWDAT4 _newdt11.bit._NEWDAT4 +#define NEWDT11_NEWDAT5 _newdt11.bit._NEWDAT5 +#define NEWDT11_NEWDAT6 _newdt11.bit._NEWDAT6 +#define NEWDT11_NEWDAT7 _newdt11.bit._NEWDAT7 +#define NEWDT11_NEWDAT8 _newdt11.bit._NEWDAT8 +#define NEWDT11_NEWDAT9 _newdt11.bit._NEWDAT9 +#define NEWDT11_NEWDAT10 _newdt11.bit._NEWDAT10 +#define NEWDT11_NEWDAT11 _newdt11.bit._NEWDAT11 +#define NEWDT11_NEWDAT12 _newdt11.bit._NEWDAT12 +#define NEWDT11_NEWDAT13 _newdt11.bit._NEWDAT13 +#define NEWDT11_NEWDAT14 _newdt11.bit._NEWDAT14 +#define NEWDT11_NEWDAT15 _newdt11.bit._NEWDAT15 +#define NEWDT11_NEWDAT16 _newdt11.bit._NEWDAT16 +__IO_EXTENDED NEWDT1L1STR _newdt1l1; +#define NEWDT1L1 _newdt1l1.byte +#define NEWDT1L1_NEWDAT1 _newdt1l1.bit._NEWDAT1 +#define NEWDT1L1_NEWDAT2 _newdt1l1.bit._NEWDAT2 +#define NEWDT1L1_NEWDAT3 _newdt1l1.bit._NEWDAT3 +#define NEWDT1L1_NEWDAT4 _newdt1l1.bit._NEWDAT4 +#define NEWDT1L1_NEWDAT5 _newdt1l1.bit._NEWDAT5 +#define NEWDT1L1_NEWDAT6 _newdt1l1.bit._NEWDAT6 +#define NEWDT1L1_NEWDAT7 _newdt1l1.bit._NEWDAT7 +#define NEWDT1L1_NEWDAT8 _newdt1l1.bit._NEWDAT8 +__IO_EXTENDED NEWDT1H1STR _newdt1h1; +#define NEWDT1H1 _newdt1h1.byte +#define NEWDT1H1_NEWDAT9 _newdt1h1.bit._NEWDAT9 +#define NEWDT1H1_NEWDAT10 _newdt1h1.bit._NEWDAT10 +#define NEWDT1H1_NEWDAT11 _newdt1h1.bit._NEWDAT11 +#define NEWDT1H1_NEWDAT12 _newdt1h1.bit._NEWDAT12 +#define NEWDT1H1_NEWDAT13 _newdt1h1.bit._NEWDAT13 +#define NEWDT1H1_NEWDAT14 _newdt1h1.bit._NEWDAT14 +#define NEWDT1H1_NEWDAT15 _newdt1h1.bit._NEWDAT15 +#define NEWDT1H1_NEWDAT16 _newdt1h1.bit._NEWDAT16 +__IO_EXTENDED NEWDT21STR _newdt21; +#define NEWDT21 _newdt21.word +#define NEWDT21_NEWDAT17 _newdt21.bit._NEWDAT17 +#define NEWDT21_NEWDAT18 _newdt21.bit._NEWDAT18 +#define NEWDT21_NEWDAT19 _newdt21.bit._NEWDAT19 +#define NEWDT21_NEWDAT20 _newdt21.bit._NEWDAT20 +#define NEWDT21_NEWDAT21 _newdt21.bit._NEWDAT21 +#define NEWDT21_NEWDAT22 _newdt21.bit._NEWDAT22 +#define NEWDT21_NEWDAT23 _newdt21.bit._NEWDAT23 +#define NEWDT21_NEWDAT24 _newdt21.bit._NEWDAT24 +#define NEWDT21_NEWDAT25 _newdt21.bit._NEWDAT25 +#define NEWDT21_NEWDAT26 _newdt21.bit._NEWDAT26 +#define NEWDT21_NEWDAT27 _newdt21.bit._NEWDAT27 +#define NEWDT21_NEWDAT28 _newdt21.bit._NEWDAT28 +#define NEWDT21_NEWDAT29 _newdt21.bit._NEWDAT29 +#define NEWDT21_NEWDAT30 _newdt21.bit._NEWDAT30 +#define NEWDT21_NEWDAT31 _newdt21.bit._NEWDAT31 +#define NEWDT21_NEWDAT32 _newdt21.bit._NEWDAT32 +__IO_EXTENDED NEWDT2L1STR _newdt2l1; +#define NEWDT2L1 _newdt2l1.byte +#define NEWDT2L1_NEWDAT17 _newdt2l1.bit._NEWDAT17 +#define NEWDT2L1_NEWDAT18 _newdt2l1.bit._NEWDAT18 +#define NEWDT2L1_NEWDAT19 _newdt2l1.bit._NEWDAT19 +#define NEWDT2L1_NEWDAT20 _newdt2l1.bit._NEWDAT20 +#define NEWDT2L1_NEWDAT21 _newdt2l1.bit._NEWDAT21 +#define NEWDT2L1_NEWDAT22 _newdt2l1.bit._NEWDAT22 +#define NEWDT2L1_NEWDAT23 _newdt2l1.bit._NEWDAT23 +#define NEWDT2L1_NEWDAT24 _newdt2l1.bit._NEWDAT24 +__IO_EXTENDED NEWDT2H1STR _newdt2h1; +#define NEWDT2H1 _newdt2h1.byte +#define NEWDT2H1_NEWDAT25 _newdt2h1.bit._NEWDAT25 +#define NEWDT2H1_NEWDAT26 _newdt2h1.bit._NEWDAT26 +#define NEWDT2H1_NEWDAT27 _newdt2h1.bit._NEWDAT27 +#define NEWDT2H1_NEWDAT28 _newdt2h1.bit._NEWDAT28 +#define NEWDT2H1_NEWDAT29 _newdt2h1.bit._NEWDAT29 +#define NEWDT2H1_NEWDAT30 _newdt2h1.bit._NEWDAT30 +#define NEWDT2H1_NEWDAT31 _newdt2h1.bit._NEWDAT31 +#define NEWDT2H1_NEWDAT32 _newdt2h1.bit._NEWDAT32 +__IO_EXTENDED INTPND1STR _intpnd1; +#define INTPND1 _intpnd1.lword +#define INTPND1_INTPND1 _intpnd1.bit._INTPND1 +#define INTPND1_INTPND2 _intpnd1.bit._INTPND2 +#define INTPND1_INTPND3 _intpnd1.bit._INTPND3 +#define INTPND1_INTPND4 _intpnd1.bit._INTPND4 +#define INTPND1_INTPND5 _intpnd1.bit._INTPND5 +#define INTPND1_INTPND6 _intpnd1.bit._INTPND6 +#define INTPND1_INTPND7 _intpnd1.bit._INTPND7 +#define INTPND1_INTPND8 _intpnd1.bit._INTPND8 +#define INTPND1_INTPND9 _intpnd1.bit._INTPND9 +#define INTPND1_INTPND10 _intpnd1.bit._INTPND10 +#define INTPND1_INTPND11 _intpnd1.bit._INTPND11 +#define INTPND1_INTPND12 _intpnd1.bit._INTPND12 +#define INTPND1_INTPND13 _intpnd1.bit._INTPND13 +#define INTPND1_INTPND14 _intpnd1.bit._INTPND14 +#define INTPND1_INTPND15 _intpnd1.bit._INTPND15 +#define INTPND1_INTPND16 _intpnd1.bit._INTPND16 +#define INTPND1_INTPND17 _intpnd1.bit._INTPND17 +#define INTPND1_INTPND18 _intpnd1.bit._INTPND18 +#define INTPND1_INTPND19 _intpnd1.bit._INTPND19 +#define INTPND1_INTPND20 _intpnd1.bit._INTPND20 +#define INTPND1_INTPND21 _intpnd1.bit._INTPND21 +#define INTPND1_INTPND22 _intpnd1.bit._INTPND22 +#define INTPND1_INTPND23 _intpnd1.bit._INTPND23 +#define INTPND1_INTPND24 _intpnd1.bit._INTPND24 +#define INTPND1_INTPND25 _intpnd1.bit._INTPND25 +#define INTPND1_INTPND26 _intpnd1.bit._INTPND26 +#define INTPND1_INTPND27 _intpnd1.bit._INTPND27 +#define INTPND1_INTPND28 _intpnd1.bit._INTPND28 +#define INTPND1_INTPND29 _intpnd1.bit._INTPND29 +#define INTPND1_INTPND30 _intpnd1.bit._INTPND30 +#define INTPND1_INTPND31 _intpnd1.bit._INTPND31 +#define INTPND1_INTPND32 _intpnd1.bit._INTPND32 +#define INTPND1_INTPND _intpnd1.bitc._INTPND +__IO_EXTENDED INTPND11STR _intpnd11; +#define INTPND11 _intpnd11.word +#define INTPND11_INTPND1 _intpnd11.bit._INTPND1 +#define INTPND11_INTPND2 _intpnd11.bit._INTPND2 +#define INTPND11_INTPND3 _intpnd11.bit._INTPND3 +#define INTPND11_INTPND4 _intpnd11.bit._INTPND4 +#define INTPND11_INTPND5 _intpnd11.bit._INTPND5 +#define INTPND11_INTPND6 _intpnd11.bit._INTPND6 +#define INTPND11_INTPND7 _intpnd11.bit._INTPND7 +#define INTPND11_INTPND8 _intpnd11.bit._INTPND8 +#define INTPND11_INTPND9 _intpnd11.bit._INTPND9 +#define INTPND11_INTPND10 _intpnd11.bit._INTPND10 +#define INTPND11_INTPND11 _intpnd11.bit._INTPND11 +#define INTPND11_INTPND12 _intpnd11.bit._INTPND12 +#define INTPND11_INTPND13 _intpnd11.bit._INTPND13 +#define INTPND11_INTPND14 _intpnd11.bit._INTPND14 +#define INTPND11_INTPND15 _intpnd11.bit._INTPND15 +#define INTPND11_INTPND16 _intpnd11.bit._INTPND16 +__IO_EXTENDED INTPND1L1STR _intpnd1l1; +#define INTPND1L1 _intpnd1l1.byte +#define INTPND1L1_INTPND1 _intpnd1l1.bit._INTPND1 +#define INTPND1L1_INTPND2 _intpnd1l1.bit._INTPND2 +#define INTPND1L1_INTPND3 _intpnd1l1.bit._INTPND3 +#define INTPND1L1_INTPND4 _intpnd1l1.bit._INTPND4 +#define INTPND1L1_INTPND5 _intpnd1l1.bit._INTPND5 +#define INTPND1L1_INTPND6 _intpnd1l1.bit._INTPND6 +#define INTPND1L1_INTPND7 _intpnd1l1.bit._INTPND7 +#define INTPND1L1_INTPND8 _intpnd1l1.bit._INTPND8 +__IO_EXTENDED INTPND1H1STR _intpnd1h1; +#define INTPND1H1 _intpnd1h1.byte +#define INTPND1H1_INTPND9 _intpnd1h1.bit._INTPND9 +#define INTPND1H1_INTPND10 _intpnd1h1.bit._INTPND10 +#define INTPND1H1_INTPND11 _intpnd1h1.bit._INTPND11 +#define INTPND1H1_INTPND12 _intpnd1h1.bit._INTPND12 +#define INTPND1H1_INTPND13 _intpnd1h1.bit._INTPND13 +#define INTPND1H1_INTPND14 _intpnd1h1.bit._INTPND14 +#define INTPND1H1_INTPND15 _intpnd1h1.bit._INTPND15 +#define INTPND1H1_INTPND16 _intpnd1h1.bit._INTPND16 +__IO_EXTENDED INTPND21STR _intpnd21; +#define INTPND21 _intpnd21.word +#define INTPND21_INTPND17 _intpnd21.bit._INTPND17 +#define INTPND21_INTPND18 _intpnd21.bit._INTPND18 +#define INTPND21_INTPND19 _intpnd21.bit._INTPND19 +#define INTPND21_INTPND20 _intpnd21.bit._INTPND20 +#define INTPND21_INTPND21 _intpnd21.bit._INTPND21 +#define INTPND21_INTPND22 _intpnd21.bit._INTPND22 +#define INTPND21_INTPND23 _intpnd21.bit._INTPND23 +#define INTPND21_INTPND24 _intpnd21.bit._INTPND24 +#define INTPND21_INTPND25 _intpnd21.bit._INTPND25 +#define INTPND21_INTPND26 _intpnd21.bit._INTPND26 +#define INTPND21_INTPND27 _intpnd21.bit._INTPND27 +#define INTPND21_INTPND28 _intpnd21.bit._INTPND28 +#define INTPND21_INTPND29 _intpnd21.bit._INTPND29 +#define INTPND21_INTPND30 _intpnd21.bit._INTPND30 +#define INTPND21_INTPND31 _intpnd21.bit._INTPND31 +#define INTPND21_INTPND32 _intpnd21.bit._INTPND32 +__IO_EXTENDED INTPND2L1STR _intpnd2l1; +#define INTPND2L1 _intpnd2l1.byte +#define INTPND2L1_INTPND17 _intpnd2l1.bit._INTPND17 +#define INTPND2L1_INTPND18 _intpnd2l1.bit._INTPND18 +#define INTPND2L1_INTPND19 _intpnd2l1.bit._INTPND19 +#define INTPND2L1_INTPND20 _intpnd2l1.bit._INTPND20 +#define INTPND2L1_INTPND21 _intpnd2l1.bit._INTPND21 +#define INTPND2L1_INTPND22 _intpnd2l1.bit._INTPND22 +#define INTPND2L1_INTPND23 _intpnd2l1.bit._INTPND23 +#define INTPND2L1_INTPND24 _intpnd2l1.bit._INTPND24 +__IO_EXTENDED INTPND2H1STR _intpnd2h1; +#define INTPND2H1 _intpnd2h1.byte +#define INTPND2H1_INTPND25 _intpnd2h1.bit._INTPND25 +#define INTPND2H1_INTPND26 _intpnd2h1.bit._INTPND26 +#define INTPND2H1_INTPND27 _intpnd2h1.bit._INTPND27 +#define INTPND2H1_INTPND28 _intpnd2h1.bit._INTPND28 +#define INTPND2H1_INTPND29 _intpnd2h1.bit._INTPND29 +#define INTPND2H1_INTPND30 _intpnd2h1.bit._INTPND30 +#define INTPND2H1_INTPND31 _intpnd2h1.bit._INTPND31 +#define INTPND2H1_INTPND32 _intpnd2h1.bit._INTPND32 +__IO_EXTENDED MSGVAL1STR _msgval1; +#define MSGVAL1 _msgval1.lword +#define MSGVAL1_MSGVAL1 _msgval1.bit._MSGVAL1 +#define MSGVAL1_MSGVAL2 _msgval1.bit._MSGVAL2 +#define MSGVAL1_MSGVAL3 _msgval1.bit._MSGVAL3 +#define MSGVAL1_MSGVAL4 _msgval1.bit._MSGVAL4 +#define MSGVAL1_MSGVAL5 _msgval1.bit._MSGVAL5 +#define MSGVAL1_MSGVAL6 _msgval1.bit._MSGVAL6 +#define MSGVAL1_MSGVAL7 _msgval1.bit._MSGVAL7 +#define MSGVAL1_MSGVAL8 _msgval1.bit._MSGVAL8 +#define MSGVAL1_MSGVAL9 _msgval1.bit._MSGVAL9 +#define MSGVAL1_MSGVAL10 _msgval1.bit._MSGVAL10 +#define MSGVAL1_MSGVAL11 _msgval1.bit._MSGVAL11 +#define MSGVAL1_MSGVAL12 _msgval1.bit._MSGVAL12 +#define MSGVAL1_MSGVAL13 _msgval1.bit._MSGVAL13 +#define MSGVAL1_MSGVAL14 _msgval1.bit._MSGVAL14 +#define MSGVAL1_MSGVAL15 _msgval1.bit._MSGVAL15 +#define MSGVAL1_MSGVAL16 _msgval1.bit._MSGVAL16 +#define MSGVAL1_MSGVAL17 _msgval1.bit._MSGVAL17 +#define MSGVAL1_MSGVAL18 _msgval1.bit._MSGVAL18 +#define MSGVAL1_MSGVAL19 _msgval1.bit._MSGVAL19 +#define MSGVAL1_MSGVAL20 _msgval1.bit._MSGVAL20 +#define MSGVAL1_MSGVAL21 _msgval1.bit._MSGVAL21 +#define MSGVAL1_MSGVAL22 _msgval1.bit._MSGVAL22 +#define MSGVAL1_MSGVAL23 _msgval1.bit._MSGVAL23 +#define MSGVAL1_MSGVAL24 _msgval1.bit._MSGVAL24 +#define MSGVAL1_MSGVAL25 _msgval1.bit._MSGVAL25 +#define MSGVAL1_MSGVAL26 _msgval1.bit._MSGVAL26 +#define MSGVAL1_MSGVAL27 _msgval1.bit._MSGVAL27 +#define MSGVAL1_MSGVAL28 _msgval1.bit._MSGVAL28 +#define MSGVAL1_MSGVAL29 _msgval1.bit._MSGVAL29 +#define MSGVAL1_MSGVAL30 _msgval1.bit._MSGVAL30 +#define MSGVAL1_MSGVAL31 _msgval1.bit._MSGVAL31 +#define MSGVAL1_MSGVAL32 _msgval1.bit._MSGVAL32 +#define MSGVAL1_MSGVAL _msgval1.bitc._MSGVAL +__IO_EXTENDED MSGVAL11STR _msgval11; +#define MSGVAL11 _msgval11.word +#define MSGVAL11_MSGVAL1 _msgval11.bit._MSGVAL1 +#define MSGVAL11_MSGVAL2 _msgval11.bit._MSGVAL2 +#define MSGVAL11_MSGVAL3 _msgval11.bit._MSGVAL3 +#define MSGVAL11_MSGVAL4 _msgval11.bit._MSGVAL4 +#define MSGVAL11_MSGVAL5 _msgval11.bit._MSGVAL5 +#define MSGVAL11_MSGVAL6 _msgval11.bit._MSGVAL6 +#define MSGVAL11_MSGVAL7 _msgval11.bit._MSGVAL7 +#define MSGVAL11_MSGVAL8 _msgval11.bit._MSGVAL8 +#define MSGVAL11_MSGVAL9 _msgval11.bit._MSGVAL9 +#define MSGVAL11_MSGVAL10 _msgval11.bit._MSGVAL10 +#define MSGVAL11_MSGVAL11 _msgval11.bit._MSGVAL11 +#define MSGVAL11_MSGVAL12 _msgval11.bit._MSGVAL12 +#define MSGVAL11_MSGVAL13 _msgval11.bit._MSGVAL13 +#define MSGVAL11_MSGVAL14 _msgval11.bit._MSGVAL14 +#define MSGVAL11_MSGVAL15 _msgval11.bit._MSGVAL15 +#define MSGVAL11_MSGVAL16 _msgval11.bit._MSGVAL16 +__IO_EXTENDED MSGVAL1L1STR _msgval1l1; +#define MSGVAL1L1 _msgval1l1.byte +#define MSGVAL1L1_MSGVAL1 _msgval1l1.bit._MSGVAL1 +#define MSGVAL1L1_MSGVAL2 _msgval1l1.bit._MSGVAL2 +#define MSGVAL1L1_MSGVAL3 _msgval1l1.bit._MSGVAL3 +#define MSGVAL1L1_MSGVAL4 _msgval1l1.bit._MSGVAL4 +#define MSGVAL1L1_MSGVAL5 _msgval1l1.bit._MSGVAL5 +#define MSGVAL1L1_MSGVAL6 _msgval1l1.bit._MSGVAL6 +#define MSGVAL1L1_MSGVAL7 _msgval1l1.bit._MSGVAL7 +#define MSGVAL1L1_MSGVAL8 _msgval1l1.bit._MSGVAL8 +__IO_EXTENDED MSGVAL1H1STR _msgval1h1; +#define MSGVAL1H1 _msgval1h1.byte +#define MSGVAL1H1_MSGVAL9 _msgval1h1.bit._MSGVAL9 +#define MSGVAL1H1_MSGVAL10 _msgval1h1.bit._MSGVAL10 +#define MSGVAL1H1_MSGVAL11 _msgval1h1.bit._MSGVAL11 +#define MSGVAL1H1_MSGVAL12 _msgval1h1.bit._MSGVAL12 +#define MSGVAL1H1_MSGVAL13 _msgval1h1.bit._MSGVAL13 +#define MSGVAL1H1_MSGVAL14 _msgval1h1.bit._MSGVAL14 +#define MSGVAL1H1_MSGVAL15 _msgval1h1.bit._MSGVAL15 +#define MSGVAL1H1_MSGVAL16 _msgval1h1.bit._MSGVAL16 +__IO_EXTENDED MSGVAL21STR _msgval21; +#define MSGVAL21 _msgval21.word +#define MSGVAL21_MSGVAL17 _msgval21.bit._MSGVAL17 +#define MSGVAL21_MSGVAL18 _msgval21.bit._MSGVAL18 +#define MSGVAL21_MSGVAL19 _msgval21.bit._MSGVAL19 +#define MSGVAL21_MSGVAL20 _msgval21.bit._MSGVAL20 +#define MSGVAL21_MSGVAL21 _msgval21.bit._MSGVAL21 +#define MSGVAL21_MSGVAL22 _msgval21.bit._MSGVAL22 +#define MSGVAL21_MSGVAL23 _msgval21.bit._MSGVAL23 +#define MSGVAL21_MSGVAL24 _msgval21.bit._MSGVAL24 +#define MSGVAL21_MSGVAL25 _msgval21.bit._MSGVAL25 +#define MSGVAL21_MSGVAL26 _msgval21.bit._MSGVAL26 +#define MSGVAL21_MSGVAL27 _msgval21.bit._MSGVAL27 +#define MSGVAL21_MSGVAL28 _msgval21.bit._MSGVAL28 +#define MSGVAL21_MSGVAL29 _msgval21.bit._MSGVAL29 +#define MSGVAL21_MSGVAL30 _msgval21.bit._MSGVAL30 +#define MSGVAL21_MSGVAL31 _msgval21.bit._MSGVAL31 +#define MSGVAL21_MSGVAL32 _msgval21.bit._MSGVAL32 +__IO_EXTENDED MSGVAL2L1STR _msgval2l1; +#define MSGVAL2L1 _msgval2l1.byte +#define MSGVAL2L1_MSGVAL17 _msgval2l1.bit._MSGVAL17 +#define MSGVAL2L1_MSGVAL18 _msgval2l1.bit._MSGVAL18 +#define MSGVAL2L1_MSGVAL19 _msgval2l1.bit._MSGVAL19 +#define MSGVAL2L1_MSGVAL20 _msgval2l1.bit._MSGVAL20 +#define MSGVAL2L1_MSGVAL21 _msgval2l1.bit._MSGVAL21 +#define MSGVAL2L1_MSGVAL22 _msgval2l1.bit._MSGVAL22 +#define MSGVAL2L1_MSGVAL23 _msgval2l1.bit._MSGVAL23 +#define MSGVAL2L1_MSGVAL24 _msgval2l1.bit._MSGVAL24 +__IO_EXTENDED MSGVAL2H1STR _msgval2h1; +#define MSGVAL2H1 _msgval2h1.byte +#define MSGVAL2H1_MSGVAL25 _msgval2h1.bit._MSGVAL25 +#define MSGVAL2H1_MSGVAL26 _msgval2h1.bit._MSGVAL26 +#define MSGVAL2H1_MSGVAL27 _msgval2h1.bit._MSGVAL27 +#define MSGVAL2H1_MSGVAL28 _msgval2h1.bit._MSGVAL28 +#define MSGVAL2H1_MSGVAL29 _msgval2h1.bit._MSGVAL29 +#define MSGVAL2H1_MSGVAL30 _msgval2h1.bit._MSGVAL30 +#define MSGVAL2H1_MSGVAL31 _msgval2h1.bit._MSGVAL31 +#define MSGVAL2H1_MSGVAL32 _msgval2h1.bit._MSGVAL32 +__IO_EXTENDED COER1STR _coer1; +#define COER1 _coer1.byte +#define COER1_OE _coer1.bit._OE +# undef ___IOWIDTH +#endif /* __MB90XXX_H */ diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/serial/serial.c b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/serial/serial.c new file mode 100644 index 000000000..61518d067 --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/serial/serial.c @@ -0,0 +1,220 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER. + * + * This file only supports UART 1 + */ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "queue.h" +#include "task.h" + +/* Demo application includes. */ +#include "serial.h" + +/* The queue used to hold received characters. */ +static xQueueHandle xRxedChars; + +/* The queue used to hold characters waiting transmission. */ +static xQueueHandle xCharsForTx; + +static volatile portSHORT sTHREEmpty; + +static volatile portSHORT queueFail = pdFALSE; + +/*-----------------------------------------------------------*/ +xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) +{ + /* Initialise the hardware. */ + portENTER_CRITICAL(); + { + /* Create the queues used by the com test task. */ + xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof(signed portCHAR) ); + xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof(signed portCHAR) ); + + if( xRxedChars == 0 ) + { + queueFail = pdTRUE; + } + + if( xCharsForTx == 0 ) + { + queueFail = pdTRUE; + } + + /* Initialize UART asynchronous mode */ + BGR0 = configCLKP1_CLOCK_HZ / ulWantedBaud; + + SCR0 = 0x17; /* 8N1 */ + SMR0 = 0x0d; /* enable SOT3, Reset, normal mode */ + SSR0 = 0x02; /* LSB first, enable receive interrupts */ + + PIER08_IE2 = 1; /* enable input */ + DDR08_D2 = 0; /* switch P08_2 to input */ + DDR08_D3 = 1; /* switch P08_3 to output */ + } + + portEXIT_CRITICAL(); + + /* Unlike other ports, this serial code does not allow for more than one + com port. We therefore don't return a pointer to a port structure and can + instead just return NULL. */ + return NULL; +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) +{ + /* Get the next character from the buffer. Return false if no characters + are available, or arrive before xBlockTime expires. */ + if( xQueueReceive(xRxedChars, pcRxedChar, xBlockTime) ) + { + return pdTRUE; + } + else + { + return pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) +{ +signed portBASE_TYPE xReturn; + + /* Transmit a character. */ + portENTER_CRITICAL(); + { + if( sTHREEmpty == pdTRUE ) + { + /* If sTHREEmpty is true then the UART Tx ISR has indicated that + there are no characters queued to be transmitted - so we can + write the character directly to the shift Tx register. */ + sTHREEmpty = pdFALSE; + TDR0 = cOutChar; + xReturn = pdPASS; + } + else + { + /* sTHREEmpty is false, so there are still characters waiting to be + transmitted. We have to queue this character so it gets + transmitted in turn. */ + + /* Return false if after the block time there is no room on the Tx + queue. It is ok to block inside a critical section as each task + maintains it's own critical section status. */ + if( xQueueSend(xCharsForTx, &cOutChar, xBlockTime) == pdTRUE ) + { + xReturn = pdPASS; + } + else + { + xReturn = pdFAIL; + } + } + + if( pdPASS == xReturn ) + { + /* Turn on the Tx interrupt so the ISR will remove the character from the + queue and send it. This does not need to be in a critical section as + if the interrupt has already removed the character the next interrupt + will simply turn off the Tx interrupt again. */ + SSR0_TIE = 1; + } + } + + portEXIT_CRITICAL(); + + return pdPASS; +} +/*-----------------------------------------------------------*/ + +/* + * UART RX interrupt service routine. + */ +__interrupt void UART0_RxISR( void ) +{ +volatile signed portCHAR cChar; + + /* Get the character from the UART and post it on the queue of Rxed + characters. */ + cChar = RDR0; + + if( xQueueGenericSendFromISR(xRxedChars, ( const void *const ) &cChar, (signed portBASE_TYPE) pdFALSE, (portBASE_TYPE) 0) ) + { + /*If the post causes a task to wake force a context switch + as the woken task may have a higher priority than the task we have + interrupted. */ + portYIELD_FROM_ISR(); + } +} +/*-----------------------------------------------------------*/ + +/* + * UART Tx interrupt service routine. + */ +__interrupt void UART0_TxISR( void ) +{ +signed portCHAR cChar; +signed portBASE_TYPE xTaskWoken; + + /* The previous character has been transmitted. See if there are any + further characters waiting transmission. */ + if( xQueueReceiveFromISR(xCharsForTx, &cChar, &xTaskWoken) == pdTRUE ) + { + /* There was another character queued - transmit it now. */ + TDR0 = cChar; + } + else + { + /* There were no other characters to transmit. */ + sTHREEmpty = pdTRUE; + + /* Disable transmit interrupts */ + SSR0_TIE = 0; + } +} diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/utility/taskutility.c b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/utility/taskutility.c new file mode 100644 index 000000000..717d22502 --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/utility/taskutility.c @@ -0,0 +1,218 @@ +/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ + +/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ + +/* ELIGIBILITY FOR ANY PURPOSES. */ + +/* (C) Fujitsu Microelectronics Europe GmbH */ + +/*------------------------------------------------------------------------ + taskutility.C + - +-------------------------------------------------------------------------*/ + +/*************************@INCLUDE_START************************/ +#include "mb96348hs.h" +#include "FreeRTOS.h" +#include "task.h" + +static void vUART1Task( void *pvParameters ); + +/**************************@INCLUDE_END*************************/ + +/*********************@GLOBAL_VARIABLES_START*******************/ +const char ASCII[] = "0123456789ABCDEF"; + +xTaskHandle UART_TaskHandle; + +void InitUart1( void ) +{ + /* Initialize UART asynchronous mode */ + BGR1 = configCLKP1_CLOCK_HZ / 9600; /* 9600 Baud @ CLKP1 - 56 MHz */ + + SCR1 = 0x17; /* 8N1 */ + SMR1 = 0x0d; /* enable SOT3, Reset, normal mode */ + SSR1 = 0x02; /* LSB first, enable receive interrupts */ + + PIER08_IE5 = 1; /* enable input */ + DDR08_D5 = 0; /* switch P08_5 to input */ + DDR08_D6 = 1; /* switch P08_6 to output */ +} + +void Putch1( char ch ) /* sends a char */ +{ + while( SSR1_TDRE == 0 ); + + /* wait for transmit buffer empty */ + TDR1 = ch; /* put ch into buffer */ +} + +char Getch1( void ) /* waits for and returns incomming char */ +{ + volatile unsigned ch; + + while( SSR1_RDRF == 0 ); + + /* wait for data received */ + if( SSR1_ORE ) /* overrun error */ + { + ch = RDR1; /* reset error flags */ + return ( char ) ( -1 ); + } + else + { + return( RDR1 ); /* return char */ + } +} + +void Puts1( const char *Name1 ) /* Puts a String to UART */ +{ + volatile portSHORT i, len; + len = strlen( Name1 ); + + for( i = 0; i < strlen(Name1); i++ ) /* go through string */ + { + if( Name1[i] == 10 ) + { + Putch1( 13 ); + } + + Putch1( Name1[i] ); /* send it out */ + } +} + +void Puthex1( unsigned long n, unsigned char digits ) +{ + unsigned portCHAR digit = 0, div = 0, i; + + div = ( 4 * (digits - 1) ); /* init shift divisor */ + for( i = 0; i < digits; i++ ) + { + digit = ( (n >> div) & 0xF ); /* get hex-digit value */ + Putch1( digit + ((digit < 0xA) ? '0' : 'A' - 0xA) ); + div -= 4; /* next digit shift */ + } +} + +void Putdec1( unsigned long x, int digits ) +{ + portSHORT i; + portCHAR buf[10], sign = 1; + + if( digits < 0 ) + { /* should be print of zero? */ + digits *= ( -1 ); + sign = 1; + } + + buf[digits] = '\0'; /* end sign of string */ + + for( i = digits; i > 0; i-- ) + { + buf[i - 1] = ASCII[x % 10]; + x = x / 10; + } + + if( sign ) + { + for( i = 0; buf[i] == '0'; i++ ) + { /* no print of zero */ + if( i < digits - 1 ) + { + buf[i] = ' '; + } + } + } + + Puts1( buf ); /* send string */ +} + +void vTraceListTasks( unsigned portBASE_TYPE uxPriority ) +{ + portENTER_CRITICAL(); + InitUart1(); + portENTER_CRITICAL(); + xTaskCreate( vUART1Task, (signed portCHAR *) "UART1", ( unsigned portSHORT ) 2048, ( void * ) NULL, uxPriority, &UART_TaskHandle ); +} + +static void vUART1Task( void *pvParameters ) +{ + portCHAR tasklist_buff[512]; + portCHAR trace_buff[512]; + unsigned portLONG trace_len; + signed portLONG i, j, l = 0; + + unsigned portCHAR ch; + ( void ) pvParameters; + + Puts1( "\n -------------MB96348 FreeRTOS DEMO Task List and Trace Utility----------- \n" ); + + for( ;; ) + { + Puts1( "\n\rPress any of the following keys for the corresponding functionality: " ); + + Puts1( "\n\r1: To call vTaskList() and display current task status " ); + + Puts1( "\n\r2: To call vTaskStartTrace() and to display trace results once the trace ends" ); + + SSR1_RIE = 1; + + vTaskSuspend( NULL ); + + ch = Getch1(); + + switch( ch ) + { + case '1': + vTaskList( (signed char *) tasklist_buff ); + Puts1( "\n\rThe current task list is as follows...." ); + Puts1( "\n\r----------------------------------------------" ); + Puts1( "\n\rName State Priority Stack Number" ); + Puts1( "\n\r----------------------------------------------" ); + Puts1( tasklist_buff ); + Puts1( "\r----------------------------------------------" ); + break; + + case '2': + vTaskStartTrace( (signed char *) trace_buff, 512 ); + Puts1( "\n\rThe trace started!!" ); + vTaskDelay( (portTickType) 500 ); + trace_len = ulTaskEndTrace(); + Puts1( "\n\rThe trace ended!!" ); + Puts1( "\n\rThe trace is as follows...." ); + Puts1( "\n\r--------------------------------------------------------" ); + Puts1( "\n\r Tick | Task Number | Tick | Task Number |" ); + Puts1( "\n\r--------------------------------------------------------\n\r" ); + + for( i = 0; i < trace_len; i += 4 ) + { + for( j = i + 3; j >= i; j-- ) + { + Puthex1( trace_buff[j], 2 ); + } + + Puts1( " | " ); + l++; + if( l == 4 ) + { + Puts1( "\n" ); + l = 0; + } + } + + Puts1( "\r--------------------------------------------------------" ); + break; + + default: + break; + } + + Puts1( "\n" ); + } +} + +__interrupt void UART1_RxISR( void ) +{ + SSR1_RIE = 0; + vTaskResume( UART_TaskHandle ); +} diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/vectors.c b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/vectors.c new file mode 100644 index 000000000..f838cbc22 --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/vectors.c @@ -0,0 +1,192 @@ +/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ +/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ +/* ELIGIBILITY FOR ANY PURPOSES. */ +/* (C) Fujitsu Microelectronics Europe GmbH */ + +/*--------------------------------------------------------------------------- + VECTORS.C + - Interrupt level (priority) setting + - Interrupt vector definition +-----------------------------------------------------------------------------*/ +#include "mb96348hs.h" +#include "config.h" + +/*--------------------------------------------------------------------------- + InitIrqLevels() + This function pre-sets all interrupt control registers. It can be used + to set all interrupt priorities in static applications. If this file + contains assignments to dedicated resources, verify that the + appropriate controller is used. + NOTE: value 7 disables the interrupt and value 0 sets highest priority. +-----------------------------------------------------------------------------*/ +#define MIN_ICR 12 +#define MAX_ICR 96 + +#define DEFAULT_ILM_MASK 7 + +void InitIrqLevels( void ) +{ +volatile int irq; + + for( irq = MIN_ICR; irq <= MAX_ICR; irq++ ) + { + ICR = ( irq << 8 ) | DEFAULT_ILM_MASK; + } + + ICR = ( (51 & 0xFF) << 8 ) | ( DEFAULT_ILM_MASK - 1 ); /* Reload Timer 0 of MB9634x Series */ + ICR = ( (12 & 0xFF) << 8 ) | ( DEFAULT_ILM_MASK - 1 ); /* Delayed interrupt of 16FX Family */ + + #if ( INCLUDE_AltStartComTestTasks == 1 ) + ICR = ( 79 << 8 ) | ( DEFAULT_ILM_MASK - 1 ); /* UART 0 Rx of MB9634x Series */ + ICR = ( 80 << 8 ) | ( DEFAULT_ILM_MASK - 1 ); /* UART 0 Tx of MB9634x Series */ + #endif + + #if ( INCLUDE_TraceListTasks == 1 ) + ICR = ( 81 << 8 ) | ( DEFAULT_ILM_MASK - 1 ); /* UART 1 Rx of MB9634x Series */ + #endif +} + +/*--------------------------------------------------------------------------- + Prototypes + Add your own prototypes here. Each vector definition needs is proto- + type. Either do it here or include a header file containing them. +-----------------------------------------------------------------------------*/ +__interrupt void DefaultIRQHandler( void ); + +extern __interrupt void prvRLT0_TICKISR( void ); + +#if ( INCLUDE_AltStartComTestTasks == 1 ) +extern __interrupt void UART0_RxISR( void ); +extern __interrupt void UART0_TxISR( void ); +#endif +extern __interrupt void vPortYield( void ); +extern __interrupt void vPortYieldDelayed( void ); + +#if ( INCLUDE_TraceListTasks == 1 ) +extern __interrupt void UART1_RxISR( void ); +#endif + +/*--------------------------------------------------------------------------- + Vector definiton for MB9634x + Use following statements to define vectors. All resource related + vectors are predefined. Remaining software interrupts can be added here + as well. + NOTE: If software interrupts 0 to 7 are defined here, this might + conflict with the reset vector in the start-up file. +-----------------------------------------------------------------------------*/ +#pragma intvect DefaultIRQHandler 11 /* Non-maskable Interrupt */ + +#pragma intvect vPortYieldDelayed 12 /* Delayed Interrupt */ + +#pragma intvect DefaultIRQHandler 13 /* RC Timer */ +#pragma intvect DefaultIRQHandler 14 /* Main Clock Timer */ +#pragma intvect DefaultIRQHandler 15 /* Sub Clock Timer */ +#pragma intvect DefaultIRQHandler 16 /* Reserved */ +#pragma intvect DefaultIRQHandler 17 /* EXT0 */ +#pragma intvect DefaultIRQHandler 18 /* EXT1 */ +#pragma intvect DefaultIRQHandler 19 /* EXT2 */ +#pragma intvect DefaultIRQHandler 20 /* EXT3 */ +#pragma intvect DefaultIRQHandler 21 /* EXT4 */ +#pragma intvect DefaultIRQHandler 22 /* EXT5 */ +#pragma intvect DefaultIRQHandler 23 /* EXT6 */ +#pragma intvect DefaultIRQHandler 24 /* EXT7 */ +#pragma intvect DefaultIRQHandler 25 /* EXT8 */ +#pragma intvect DefaultIRQHandler 26 /* EXT9 */ +#pragma intvect DefaultIRQHandler 27 /* EXT10 */ +#pragma intvect DefaultIRQHandler 28 /* EXT11 */ +#pragma intvect DefaultIRQHandler 29 /* EXT12 */ +#pragma intvect DefaultIRQHandler 30 /* EXT13 */ +#pragma intvect DefaultIRQHandler 31 /* EXT14 */ +#pragma intvect DefaultIRQHandler 32 /* EXT15 */ +#pragma intvect DefaultIRQHandler 33 /* CAN0 */ +#pragma intvect DefaultIRQHandler 34 /* CAN1 */ +#pragma intvect DefaultIRQHandler 35 /* PPG0 */ +#pragma intvect DefaultIRQHandler 36 /* PPG1 */ +#pragma intvect DefaultIRQHandler 37 /* PPG2 */ +#pragma intvect DefaultIRQHandler 38 /* PPG3 */ +#pragma intvect DefaultIRQHandler 39 /* PPG4 */ +#pragma intvect DefaultIRQHandler 40 /* PPG5 */ +#pragma intvect DefaultIRQHandler 41 /* PPG6 */ +#pragma intvect DefaultIRQHandler 42 /* PPG7 */ +#pragma intvect DefaultIRQHandler 43 /* PPG8 */ +#pragma intvect DefaultIRQHandler 44 /* PPG9 */ +#pragma intvect DefaultIRQHandler 45 /* PPG10 */ +#pragma intvect DefaultIRQHandler 46 /* PPG11 */ +#pragma intvect DefaultIRQHandler 47 /* PPG12 */ +#pragma intvect DefaultIRQHandler 48 /* PPG13 */ +#pragma intvect DefaultIRQHandler 49 /* PPG14 */ +#pragma intvect DefaultIRQHandler 50 /* PPG15 */ + +#pragma intvect prvRLT0_TICKISR 51 /* RLT0 */ + +#pragma intvect DefaultIRQHandler 52 /* RLT1 */ +#pragma intvect DefaultIRQHandler 53 /* RLT2 */ +#pragma intvect DefaultIRQHandler 54 /* RLT3 */ +#pragma intvect DefaultIRQHandler 55 /* PPGRLT - RLT6 */ +#pragma intvect DefaultIRQHandler 56 /* ICU0 */ +#pragma intvect DefaultIRQHandler 57 /* ICU1 */ +#pragma intvect DefaultIRQHandler 58 /* ICU2 */ +#pragma intvect DefaultIRQHandler 59 /* ICU3 */ +#pragma intvect DefaultIRQHandler 60 /* ICU4 */ +#pragma intvect DefaultIRQHandler 61 /* ICU5 */ +#pragma intvect DefaultIRQHandler 62 /* ICU6 */ +#pragma intvect DefaultIRQHandler 63 /* ICU7 */ +#pragma intvect DefaultIRQHandler 64 /* OCU0 */ +#pragma intvect DefaultIRQHandler 65 /* OCU1 */ +#pragma intvect DefaultIRQHandler 66 /* OCU2 */ +#pragma intvect DefaultIRQHandler 67 /* OCU3 */ +#pragma intvect DefaultIRQHandler 68 /* OCU4 */ +#pragma intvect DefaultIRQHandler 69 /* OCU5 */ +#pragma intvect DefaultIRQHandler 70 /* OCU6 */ +#pragma intvect DefaultIRQHandler 71 /* OCU7 */ +#pragma intvect DefaultIRQHandler 72 /* FRT0 */ +#pragma intvect DefaultIRQHandler 73 /* FRT1 */ +#pragma intvect DefaultIRQHandler 74 /* I2C0 */ +#pragma intvect DefaultIRQHandler 75 /* I2C1 */ +#pragma intvect DefaultIRQHandler 76 /* ADC */ +#pragma intvect DefaultIRQHandler 77 /* ALARM0 */ +#pragma intvect DefaultIRQHandler 78 /* ALARM1 */ + +#if ( INCLUDE_AltStartComTestTasks == 1 ) + #pragma intvect UART0_RxISR 79 /* LIN-UART 0 RX */ + #pragma intvect UART0_TxISR 80 /* LIN-UART 0 TX */ +#else + #pragma intvect DefaultIRQHandler 79 /* LIN-UART 0 RX */ + #pragma intvect DefaultIRQHandler 80 /* LIN-UART 0 TX */ +#endif +#if ( INCLUDE_TraceListTasks == 1 ) + #pragma intvect UART1_RxISR 81 /* LIN-UART 1 RX */ +#else + #pragma intvect DefaultIRQHandler 81 /* LIN-UART 1 RX */ +#endif +#pragma intvect DefaultIRQHandler 82 /* LIN-UART 1 TX */ +#pragma intvect DefaultIRQHandler 83 /* LIN-UART 2 RX */ +#pragma intvect DefaultIRQHandler 84 /* LIN-UART 2 TX */ +#pragma intvect DefaultIRQHandler 85 /* LIN-UART 3 RX */ +#pragma intvect DefaultIRQHandler 86 /* LIN-UART 3 TX */ +#pragma intvect DefaultIRQHandler 87 /* MAIN FLASH IRQ */ +#pragma intvect DefaultIRQHandler 88 /* SATELLITE FLASH IRQ (not on all devices) */ +#pragma intvect DefaultIRQHandler 89 /* LIN-UART 7 RX (not on all devices) */ +#pragma intvect DefaultIRQHandler 90 /* LIN-UART 7 TX (not on all devices) */ +#pragma intvect DefaultIRQHandler 91 /* LIN-UART 8 RX (not on all devices) */ +#pragma intvect DefaultIRQHandler 92 /* LIN-UART 8 TX (not on all devices) */ +#pragma intvect DefaultIRQHandler 93 /* LIN-UART 9 RX (not on all devices) */ +#pragma intvect DefaultIRQHandler 94 /* LIN-UART 9 TX (not on all devices) */ +#pragma intvect DefaultIRQHandler 95 /* RTC (not on all devices) */ +#pragma intvect DefaultIRQHandler 96 /* CAL (not on all devices) */ + +#pragma intvect vPortYield 122 /* INT #122 */ + +/*--------------------------------------------------------------------------- + DefaultIRQHandler() + This function is a placeholder for all vector definitions. Either use + your own placeholder or add necessary code here. +-----------------------------------------------------------------------------*/ +__interrupt void DefaultIRQHandler( void ) +{ + __DI(); /* disable interrupts */ + while( 1 ) + { + __wait_nop(); /* halt system */ + } +} diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/watchdog/watchdog.c b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/watchdog/watchdog.c new file mode 100644 index 000000000..7d43fd017 --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/watchdog/watchdog.c @@ -0,0 +1,67 @@ +/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ + +/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ + +/* ELIGIBILITY FOR ANY PURPOSES. */ + +/* (C) Fujitsu Microelectronics Europe GmbH */ + +/*------------------------------------------------------------------------ + watchdog.c + - This file contains the function deefinition for hardware watchdog. +-------------------------------------------------------------------------*/ +#include "mb96348hs.h" +#include "FreeRTOS.h" +#include "task.h" +#include "watchdog.h" + +/*--------------------------------------------------------------------------- + * Setup Watchdog + *---------------------------------------------------------------------------*/ +#if WATCHDOG != WTC_NONE +void InitWatchdog( void ) +{ + WDTC_WTI = WTC_PER_2_23; /* 2^23/CLKWT */ + WDTC_WTCS = WTC_CLKMC; /* CLKWT=CLKMC, Watchdog expiration delay = 2.097s @ 4MHZ CLKMC*/ + WDTCP = 0x00; /* Activate Watchdog, Clear Pattern 0x00 */ +} + +#endif + +/*--------------------------------------------------------------------------- + * The below task clears the watchdog and blocks itself for WTC_CLR_PER ticks. + *---------------------------------------------------------------------------*/ +#if WATCHDOG == WTC_IN_TASK +static void prvWatchdogTask( void *pvParameters ) +{ + const portTickType xFrequency = WTC_CLR_PER; + portTickType xLastWakeTime; + ( void ) pvParameters; + + /* Get currrent tick count */ + xLastWakeTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Get currrent tick count */ + xLastWakeTime = xTaskGetTickCount(); + + Kick_Watchdog(); + + /* Block the task for WTC_CLR_PER ticks (1s) at watchdog overflow period of WTC_PER_2_23 CLKMC cycles */ + vTaskDelayUntil( &xLastWakeTime, xFrequency ); + } +} + +#endif + +/*--------------------------------------------------------------------------- + * The below function creates hardware watchdog task. + *---------------------------------------------------------------------------*/ +#if WATCHDOG == WTC_IN_TASK +void vStartWatchdogTask( unsigned portBASE_TYPE uxPriority ) +{ + xTaskCreate( prvWatchdogTask, (signed portCHAR *) "KickWTC", portMINIMAL_STACK_SIZE, ( void * ) NULL, uxPriority, ( xTaskHandle * ) NULL ); +} + +#endif diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/watchdog/watchdog.h b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/watchdog/watchdog.h new file mode 100644 index 000000000..26df68be5 --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/watchdog/watchdog.h @@ -0,0 +1,90 @@ +/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ + +/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ + +/* ELIGIBILITY FOR ANY PURPOSES. */ + +/* (C) Fujitsu Microelectronics Europe GmbH */ + +/*------------------------------------------------------------------------ + watchdog.h + - This file contains the defines and function declaration for hardware watchdog. +-------------------------------------------------------------------------*/ + +/* + * Clear watchdog defines + */ +#define WTC_NONE 0 /* Don't initialize and clear watchdog */ +#define WTC_IN_TASK 1 /* Clear Watchdog in dedicated task */ +#define WTC_IN_TICK 2 /* Clear Watchdog in TICK Hook */ +#define WTC_IN_IDLE 3 /* Clear Watchdog in Idle Hook */ + +#define WATCHDOG WTC_IN_TASK /* Clear Watchdog in vWatchdogTask() */ + +/*------------------------------------------------------------------------*/ + +/* + * Watchdog period defines + */ +#define WTC_PER_2_9 0 /* The watchdog period is 2^9/CLKWT */ +#define WTC_PER_2_10 1 /* The watchdog period is 2^10/CLKWT */ +#define WTC_PER_2_11 2 /* The watchdog period is 2^11/CLKWT */ +#define WTC_PER_2_12 3 /* The watchdog period is 2^12/CLKWT */ +#define WTC_PER_2_13 4 /* The watchdog period is 2^13/CLKWT */ +#define WTC_PER_2_14 5 /* The watchdog period is 2^14/CLKWT */ +#define WTC_PER_2_15 6 /* The watchdog period is 2^15/CLKWT */ +#define WTC_PER_2_16 7 /* The watchdog period is 2^16/CLKWT */ +#define WTC_PER_2_17 8 /* The watchdog period is 2^17/CLKWT */ +#define WTC_PER_2_18 9 /* The watchdog period is 2^18/CLKWT */ +#define WTC_PER_2_19 10 /* The watchdog period is 2^19/CLKWT */ +#define WTC_PER_2_20 11 /* The watchdog period is 2^20/CLKWT */ +#define WTC_PER_2_21 12 /* The watchdog period is 2^21/CLKWT */ +#define WTC_PER_2_22 13 /* The watchdog period is 2^22/CLKWT */ +#define WTC_PER_2_23 14 /* The watchdog period is 2^23/CLKWT */ +#define WTC_PER_2_24 15 /* The watchdog period is 2^24/CLKWT */ + +/*------------------------------------------------------------------------*/ + +/* + * Watchdog Clock source defines + */ +#define WTC_CLKRC0 0 /* The watchdog clock is CLKRC */ +#define WTC_CLKRC1 1 /* The watchdog clock is CLKRC, + changing RC clock while watchdog opeation causes reset */ +#define WTC_CLKMC 2 /* The watchdog clock is CLKMC */ +#define WTC_CLKSC 3 /* The watchdog clock is CLKSC */ + +/*------------------------------------------------------------------------*/ + +/* + * Watchdog Reset at transition to Stop mode defines + */ +#define WTC_RSTP_0 0 /* No watchdog reset at transition to Stop mode */ +#define WTC_RSTP_1 1 /* watchdog reset at transition to Stop mode */ + +/*------------------------------------------------------------------------*/ + +/* + * After every WTC_CLR_PER ticks the watchdog would be cleared in the prvWatchdogTask(). + * This period needs to be chosed in accordance with the current CLKWT and the above + * setting WTC_PER_2_XX. + */ +#define WTC_CLR_PER 100 /* The watchdog clear period in RTOS ticks */ + +/*------------------------------------------------------------------------*/ + +/* + * Kick_watchdog Macro to clear watchdog + */ +#define Kick_Watchdog() \ + { \ + WDTCP = 0x00; \ + } + +/*------------------------------------------------------------------------*/ + +/* + * Watchdog function declarations + */ +void InitWatchdog( void ); +void vStartWatchdogTask( unsigned portBASE_TYPE uxPriority ); diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/options.dat b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/options.dat new file mode 100644 index 000000000..d911491f6 --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/options.dat @@ -0,0 +1,387 @@ +$CPUSERIES-907 +$Prj-Config_1 +$0 +-g +-w 0 +-INF LIST +-D __CONFIG__=1 +-I ".\Src" +-I ".\Src\config" +-I ".\Src\watchdog" +-I "..\..\Common\include" +-I "..\..\..\Source\include" +-I "..\..\..\Source\portable\Softune\MB96340" +-O 4 +-K SPEED +-model MEDIUM +-B +-Xdof +-xauto 127 +-x vTaskSwitchContext,vTaskIncrementTick +-K EOPT +-K LIB +-K UNROLL +$other +-INF srcin +-D __96340 +$time +1202822767 +$end +$1 +-g +-w 2 +-D __CONFIG__=1 +-I ".\Src\config" +-I ".\Src\os" +-I ".\Src\port" +-linf ON +-lsrc ON +-lsec ON +-lcros OFF +-linc ON +-lexp OBJ +-pl 60 +-pw 100 +-tab 8 +-lf +-Xdof +$other +$time +1200393386 +$end +$2 +-g +-AL 2 +-ra _INRAM01=0x000180/0x00037F +-ra _INRAM02=0x002240/0x007FFF +-ro _INROM03=0xF80000/0xFFFFFF +-ro _INROM01=0xDE0000/0xDE7FFF +-ro _INROM02=0xDF0000/0xDF7FFF +-sc CONST/Data/BYTE=0xFF8000 +-check_rora +-check_locate +-rg 0 +-m +-pl 60 +-pw 132 +-Xals +-Xalr +-na +-w 2 +-Xdof +$other +-Xset_rora +$time +1202811016 +$end +$3 +-dt s,d,r,a +-pl 60 +-pw 132 +-g +-Xdof +$other +$time +1202811016 +$end +$4 +-Xdof +$other +$time +1200320865 +$end +$5 +$other +$time +1200320865 +$end +$Prjend +$Prj-Config_2 +$0 +-g +-w 3 +-INF LIST +-D __CONFIG__=2 +-I ".\Src" +-I ".\Src\config" +-I ".\Src\watchdog" +-I "..\..\Common\include" +-I "..\..\..\Source\include" +-I "..\..\..\Source\portable\Softune\MB96340" +-O 4 +-K SPEED +-model MEDIUM +-B +-Xdof +-xauto 127 +-x vTaskSwitchContext,vTaskIncrementTick +-K EOPT +-K LIB +-K UNROLL +$other +-INF srcin +-D __96340 +$time +1202809391 +$end +$1 +-g +-w 2 +-D __CONFIG__=2 +-I "C:\Fujitsu\FreeRTOS\FreeRTOS Port 16FX\96340_FreeRTOS_96348hs-v17\96340_FreeRTOS_96348hs-v17\Src\os" +-I "C:\Fujitsu\FreeRTOS\FreeRTOS Port 16FX\96340_FreeRTOS_96348hs-v17\96340_FreeRTOS_96348hs-v17\Src\port" +-linf ON +-lsrc ON +-lsec ON +-lcros OFF +-linc ON +-lexp OBJ +-pl 60 +-pw 100 +-tab 8 +-lf +-Xdof +$other +$time +1200332591 +$end +$2 +-g +-AL 2 +-ra _INRAM01=0x000180/0x00037F +-ra _INRAM02=0x002240/0x007FFF +-ro _INROM03=0xF80000/0xFFFFFF +-ro _INROM01=0xDE0000/0xDE7FFF +-ro _INROM02=0xDF0000/0xDF7FFF +-sc CONST/Data/BYTE=0xFF8000 +-check_rora +-check_locate +-rg 0 +-m +-pl 60 +-pw 132 +-Xals +-Xalr +-na +-w 2 +-Xdof +$other +-Xset_rora +$time +1202811016 +$end +$3 +-dt s,d,r,a +-pl 60 +-pw 132 +-g +-Xdof +$other +$time +1202811016 +$end +$4 +-Xdof +$other +$time +1200320939 +$end +$5 +$other +$time +1200320939 +$end +$Prjend +$Prj-Config_3 +$0 +-g +-w 1 +-INF LIST +-D __CONFIG__=3 +-I ".\Src" +-I ".\Src\config" +-I ".\Src\watchdog" +-I "..\..\Common\include" +-I "..\..\..\Source\include" +-I "..\..\..\Source\portable\Softune\MB96340" +-O 4 +-K SPEED +-model MEDIUM +-B +-Xdof +-xauto 127 +-x vTaskSwitchContext,vTaskIncrementTick +-K EOPT +-K LIB +-K UNROLL +$other +-INF srcin +-D __96340 +$time +1202828865 +$end +$1 +-g +-w 2 +-D __CONFIG__=3 +-I "C:\Fujitsu\FreeRTOS\FreeRTOS Port 16FX\96340_FreeRTOS_96348hs-v17\96340_FreeRTOS_96348hs-v17\Src\os" +-I "C:\Fujitsu\FreeRTOS\FreeRTOS Port 16FX\96340_FreeRTOS_96348hs-v17\96340_FreeRTOS_96348hs-v17\Src\port" +-linf ON +-lsrc ON +-lsec ON +-lcros OFF +-linc ON +-lexp OBJ +-pl 60 +-pw 100 +-tab 8 +-lf +-Xdof +$other +$time +1200332591 +$end +$2 +-g +-AL 2 +-ra _INRAM01=0x000180/0x00037F +-ra _INRAM02=0x002240/0x007FFF +-ro _INROM03=0xF80000/0xFFFFFF +-ro _INROM01=0xDE0000/0xDE7FFF +-ro _INROM02=0xDF0000/0xDF7FFF +-sc CONST/Data/BYTE=0xFF8000 +-check_rora +-check_locate +-rg 0 +-m +-pl 60 +-pw 132 +-Xals +-Xalr +-na +-w 2 +-Xdof +$other +-Xset_rora +$time +1202811016 +$end +$3 +-dt s,d,r,a +-pl 60 +-pw 132 +-g +-Xdof +$other +$time +1202811016 +$end +$4 +-Xdof +$other +$time +1200332229 +$end +$5 +$other +$time +1200332229 +$end +$Prjend +$Prj-Config_4 +$0 +-g +-w 1 +-INF LIST +-D __CONFIG__=4 +-I ".\Src" +-I ".\Src\config" +-I ".\Src\watchdog" +-I "..\..\Common\include" +-I "..\..\..\Source\include" +-I "..\..\..\Source\portable\Softune\MB96340" +-O 4 +-K SPEED +-model MEDIUM +-B +-Xdof +-xauto 127 +-x vTaskSwitchContext,vTaskIncrementTick +-K EOPT +-K LIB +-K UNROLL +$other +-INF srcin +-D __96340 +$time +1202825423 +$end +$1 +-g +-w 2 +-D __CONFIG__=4 +-I "C:\Fujitsu\FreeRTOS\FreeRTOS Port 16FX\96340_FreeRTOS_96348hs-v17\96340_FreeRTOS_96348hs-v17\Src\os" +-I "C:\Fujitsu\FreeRTOS\FreeRTOS Port 16FX\96340_FreeRTOS_96348hs-v17\96340_FreeRTOS_96348hs-v17\Src\port" +-linf ON +-lsrc ON +-lsec ON +-lcros OFF +-linc ON +-lexp OBJ +-pl 60 +-pw 100 +-tab 8 +-lf +-Xdof +$other +$time +1200332591 +$end +$2 +-g +-AL 2 +-ra _INRAM01=0x000180/0x00037F +-ra _INRAM02=0x002240/0x007FFF +-ro _INROM03=0xF80000/0xFFFFFF +-ro _INROM01=0xDE0000/0xDE7FFF +-ro _INROM02=0xDF0000/0xDF7FFF +-sc CONST/Data/BYTE=0xFF8000 +-check_rora +-check_locate +-rg 0 +-m +-pl 60 +-pw 132 +-Xals +-Xalr +-na +-w 2 +-Xdof +$other +-Xset_rora +$time +1202811016 +$end +$3 +-dt s,d,r,a +-pl 60 +-pw 132 +-g +-Xdof +$other +$time +1202811016 +$end +$4 +-Xdof +$other +$time +1200332258 +$end +$5 +$other +$time +1200332258 +$end +$Prjend +$CPUSERIESEND diff --git a/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/readme.txt b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/readme.txt new file mode 100644 index 000000000..19b255502 --- /dev/null +++ b/20080212/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/readme.txt @@ -0,0 +1,147 @@ +========================================================================== + Template Project for MB96348HS Series +========================================================================== + Fujitsu Microelectronics Europe GmbH + + The following software is for demonstration purposes only. It is not + fully tested, nor validated in order to fullfill its task under all + circumstances. Therefore, this software or any part of it must only be + used in an evaluation laboratory environment. + This software is subject to the rules of our standard DISCLAIMER, that is + delivered with our SW-tools on the Fujitsu Microcontrollers DVD + (V5.0 or higher "\START.HTM"). +========================================================================== + +History +Date Ver Author Softune Description +2007-10-29 1.0 MPi V30L33R11 original version +2007-11-02 1.1 MPi V30L33R11 Added the watchdog functionality + Used vTaskStartScheduler() instead + of xPortStartScheduler() +2007-11-12 1.2 MPi V30L33R11 Updated FreeRTOS 4.6.1 and tested +2007-11-23 1.3 MPi V30L33R11 Seperated watchdog functionality in watchdog.c + and watchdog.h +2008-01-03 1.4 MPi V30L33R11 Added portYIELDFromISR() and now all the + demo application functions are working. +2008-01-04 1.5 MPi V30L33R11 Updated FreeRTOS 4.7.0 and tested +2008-01-10 1.6 MPi V30L33R11 Replaced INT9 with INT #122 in macro portYIELD() +2008-01-14 1.7 MPi V30L33R11 Modified the code to work with SK-16FX-100PMC V1.1 +2008-01-15 1.8 MPi V30L33R11 Integrated SVN releases 1.5 and 1.6. +========================================================================== +1.0. +This is a project is to test the FreeRTOS port for 16FX and the demo application +which runs on FLASH-CAN-100P-240. + +This FreeRTOS port uses the Task Stack pointed by User Stack pointer (USB:USP) for +tasks and the system stack pointed by System Stack pointer (SSB:SSP) for everything +else. + +This port is tested with MEDIUM and LARGE memory model and seems to be working fine. +The define MEMMODEL has to be configured in order to use the corresponding memory +model. + +This port doesnt use any register banking and always uses bank 0. It also consider that +the parameters to the tasks is passed via stack and not via registers. + +In this port the implemetation of portENTER_CRITICAL() and portEXIT_CRITICAL() macros +is changed in order to make them more efficient. Now usCriticalNesting variable is not +used to keep track of global interrupt enable. Rather the current PS is stored on to +the stack and interrupts are disabled for portENTER_CRITICAL(). And for portEXIT_CRITICAL() +simply the PS is restored from stack. + +1.1. +In this port, the functionality is added to initialize and clear the watchdog in the +dedicated task, Tick Hook or the Idle Hook. The place exactly where the wtachdog can be +cleared can be configured. Though Idle Hook is not an approproiate place to clear the +watchdog, its done here for demonstration purpose only. + +Also from Main function vTaskStartScheduler() function is called instead of xPortStartScheduler(). +After doing this change now no more IDLE task is required to be added seperately as +vTaskStartScheduler() adds prvIdleTask() on its own. + +1.2. +Updated the FreeRTOS version to 4.6.1 and tested with the same. + +1.3. +Moved the watchdog functionality to watchdog.c and watchdog.h. + +1.4. +Added portYIELDFromISR() which uses delayed interrupt. This macro needs to be used from the +application ISRs in order to force a context switch from them if required. It should be noted +that the interrupt priority of such application ISRs MUST be always higher than the dealyed +interrupt (currently 23) in order to perform the context switch correctly. + +It should be also noted that the RLT0 and Delayed Interrupt priority MUST be always same in order +to assure correct working of this port. + +Now portYIELD() used software interrupt INT9 instead of delayed interrupt. + +Now all the queue functions works ok. + +Tested with the heap_1.c, heap_2.c and heap_3.c. + +At one time, either of heap_1.c or heap_2.c or heap_3.c needs to be used. Hence the files those are not +required to be used should be removed from the target of the build. + +Added the __STD_LIB_sbrk.c file in order to define the *sbrk() function. This is required while using +heap_3.c file which uses the dynamic memory allocation. + +Made changes to the demo application files crhook.c. Please refer the file and grep for "Added by MPi" +to find the changes. It should be noted that if INCLUDE_StartHookCoRoutines is defined as 0 (i.e. if +vStartHookCoRoutines() functionality is NOT required) then crhook.c file should be removed from target +build and uncomment the vApplicationTickHook() function from main.c should be uncommnented. + +Added taskutility.c file. This file contains vUART2Task() which calls vTaskList() and vTaskStartTrace() +functions. + +If vCreateBlockTimeTasks() is not called then the LED at PDR00_P7 blinks at normal rate (3s). + +This port is tested with MEDIUM and LARGE memory model and working fine. + +configMINIMAL_STACK_SIZE value changed to 172 from 70 in order to make the port work. + +1.5. +Updated the FreeRTOS version to 4.7.0 and tested with the same. Tested for pre-emptive as well as +co-operative approach. + +1.6. +portYIELD() macro now uses INT #122 instead of INT9. + +Optimized functions vParTestToggleLED() and vParTestSetLED() in main.c. + +Now watchdog uses 2^23 as clock prescaler instead of 2^24. Also updated the WTC_CLR_PER in watchdog.h. + +1.7. +Modified the code to work with SK-16FX-100PMC V1.1. + +Made changes to the demo application files crflash.c. Please refer the file and grep for "Added by MPi" +to find the changes. + +Made changes to taskutility.c and vectors.c in order to use UART1 instead of UART2. + +Made changes to main.c file in order to handle use the 7-segment display (SEG1) connected to Port09 for tasks +and 7-segment display (SEG2) connected to Port00 for co-routines. + +Added config.h and moved the demo application configs there. + +1.8. +It should be noted that the readme, appnote and SVN tag version numbers may be different for the same release. + +This readme is specific to project FreeRTOS_96348hs_SK16FX100PMC. And this project specifically works +on board SK-16FX-100PMC V1.1 along with EUROScope debugger. + +Created 4 different configuration Config_1 to Config_4. Each config includes certain demo application function. +More details specific to each configuration can be found in the appnote. + +Used relative path to include files instead of absolute. + +Created config, MemMang, serial and utility subdirectories and moved corresponding functionlaity there. + +Updated config.h, main.c and start.asm in order to have configuration specific build. + +Clock settings: +--------------- +Crystal: 4 MHz +CLKB: 56 MHz +CLKP1: 56 MHz +CLKP2: 56 MHz diff --git a/20080212/Demo/MCF5235_GCC/Changelog.txt b/20080212/Demo/MCF5235_GCC/Changelog.txt new file mode 100644 index 000000000..0290fbae0 --- /dev/null +++ b/20080212/Demo/MCF5235_GCC/Changelog.txt @@ -0,0 +1,4 @@ + +2006-08-31 (REL_1_2) Christian Walter : + Notes: Recreated from lwIP port. + diff --git a/20080212/Demo/MCF5235_GCC/FreeRTOSConfig.h b/20080212/Demo/MCF5235_GCC/FreeRTOSConfig.h new file mode 100644 index 000000000..da10332b0 --- /dev/null +++ b/20080212/Demo/MCF5235_GCC/FreeRTOSConfig.h @@ -0,0 +1,85 @@ +/* + FreeRTOS V4.6.1 - Copyright (C) 2003-2006 Richard Barry. + MCF5235 Port - Copyright (C) 2006 Christian Walter. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 25000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 7 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 256 ) +#define configMAX_TASK_NAME_LEN ( 16 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/MCF5235_GCC/LICENSE_FREESCALE.TXT b/20080212/Demo/MCF5235_GCC/LICENSE_FREESCALE.TXT new file mode 100644 index 000000000..7e58b1174 --- /dev/null +++ b/20080212/Demo/MCF5235_GCC/LICENSE_FREESCALE.TXT @@ -0,0 +1,35 @@ +MCF523x example code + +IMPORTANT. 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The waiver by Freescale of any breach of any provision of this Agreement will not operate or be construed as a waiver of any other or a subsequent breach of the same or a different provision. diff --git a/20080212/Demo/MCF5235_GCC/Makefile b/20080212/Demo/MCF5235_GCC/Makefile new file mode 100644 index 000000000..7a2da52f6 --- /dev/null +++ b/20080212/Demo/MCF5235_GCC/Makefile @@ -0,0 +1,87 @@ +# +# FreeRTOS 4.1.0 - MCF5235 Coldfire Port +# +# Copyright (c) 2006 Christian Walter, Vienna 2006. +# +# $Id: Makefile,v 1.1 2006/08/31 22:45:48 wolti Exp $ +# +# --------------------------------------------------------------------------- +BASE = /opt/gcc-m68k/bin +CC = $(BASE)/m68k-elf-gcc +CXX = $(BASE)/m68k-elf-g++ +OBJCOPY = $(BASE)/m68k-elf-objcopy +SIZE = $(BASE)/m68k-elf-size +INSIGHT = $(BASE)/m68k-bdm-elf-insight +BDMFLASH = $(BASE)/bdmflash + +#CFLAGS = -MD -O2 -m528x -Wall +CFLAGS = -MD -gdwarf-2 -g3 -m528x -Wall \ + -D'GCC_MCF5235=1' -D'_GCC_USES_FP=1' \ + -D'__IPSBAR=((vuint8 *) 0x40000000)' -D'FSYS_2=25000000UL' \ + -I. -Iinclude -Iinclude/arch -Ifec \ + -I../../Source/include -I../Common/include + +ASFLAGS = -MD -gdwarf-2 -g3 -m528x -Wa,--register-prefix-optional \ + -Wa,--bitwise-or -Wa,--defsym,IPSBAR=0x40000000 +LDSCRIPT = m5235-ram.ld +LDFLAGS = -nostartfiles -m528x -Wl,--script=$(LDSCRIPT) + +TGT = demo +OTHER_CSRC = +OTHER_ASRC = $(addprefix system/, crt0.S vector.S) +CSRC = demo.c \ + $(addprefix system/, init.c newlib.c serial.c) \ + $(addprefix ../Common/Minimal/, PollQ.c integer.c flop.c BlockQ.c semtest.c dynamic.c ) \ + $(addprefix ../../Source/, tasks.c queue.c list.c) \ + $(addprefix ../../Source/portable/MemMang/, heap_3.c) \ + $(addprefix ../../Source/portable/GCC/MCF5235/, port.c) + +ASRC = $(addprefix system/, mcf5xxx.S ) +OBJS = $(CSRC:.c=.o) $(ASRC:.S=.o) +NOLINK_OBJS = $(OTHER_CSRC:.c=.o) $(OTHER_ASRC:.S=.o) +DEPS = $(OBJS:.o=.d) $(NOLINK_OBJS:.o=.d) +BIN = $(TGT).elf + +.PHONY: clean all + +all: $(BIN) + +flash-programm: $(TGT).elf + $(OBJCOPY) -O binary $(TGT).elf $(TGT).bin + @BIN_SIZE=`du -b $(TGT).bin | awk '//{ print $$1; }'`; \ + echo "programming $(TGT).bin with size $$BIN_SIZE to flash..."; \ + $(BDMFLASH) /dev/bdmcf20 0x00000000 1 2 write $(TGT).bin 0 + +flash-verify: + @BIN_SIZE=`du -b $(TGT).bin | awk '//{ print $$1; }'`; \ + echo "loading $$BIN_SIZE bytes from target into $(TGT).vrf..."; \ + $(BDMFLASH) /dev/bdmcf20 0x00000000 1 2 read $(TGT).vrf 0 $$BIN_SIZE + +flash-erase: + $(BDMFLASH) /dev/bdmcf20 0x00000000 1 2 erase + +debug: + $(INSIGHT) --command=m5235.gdb --se=$(TGT).elf + +$(BIN): $(OBJS) $(NOLINK_OBJS) + $(CC) $(LDFLAGS) -Wl,-Map=$(TGT).map $(OBJS) $(LDLIBS) -o $@ + +clean: + rm -f $(DEPS) + rm -f $(OBJS) $(NOLINK_OBJS) + rm -f $(BIN) $(TGT).map + +# --------------------------------------------------------------------------- +# rules for code generation +# --------------------------------------------------------------------------- +%.o: %.c + $(CC) $(CFLAGS) -o $@ -c $< + +%.o: %.S + $(CC) $(ASFLAGS) -o $@ -c $< + +# --------------------------------------------------------------------------- +# # compiler generated dependencies +# --------------------------------------------------------------------------- +-include $(DEPS) + diff --git a/20080212/Demo/MCF5235_GCC/demo.c b/20080212/Demo/MCF5235_GCC/demo.c new file mode 100644 index 000000000..f16b05640 --- /dev/null +++ b/20080212/Demo/MCF5235_GCC/demo.c @@ -0,0 +1,308 @@ +/* + FreeRTOS V4.6.1 - Copyright (C) 2003-2006 Richard Barry. + MCF5235 Port - Copyright (C) 2006 Christian Walter. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* ------------------------ System includes ------------------------------- */ +#include +#include + +/* ------------------------ FreeRTOS includes ----------------------------- */ +#include "FreeRTOS.h" +#include "task.h" + +/* ------------------------ Demo application includes --------------------- */ +#include "partest.h" +#include "flash.h" +#include "integer.h" +#include "PollQ.h" +#include "comtest2.h" +#include "semtest.h" +#include "flop.h" +#include "dynamic.h" +#include "BlockQ.h" +#include "serial.h" + +/* ------------------------ Defines --------------------------------------- */ +/* Constants for the ComTest tasks. */ +#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 38400 ) +#define mainCOM_TEST_LED ( -1 ) + +/* Priorities for the demo application tasks. */ +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) + +/* Interval in which tasks are checked. */ +#define mainCHECK_PERIOD ( ( portTickType ) 2000 / portTICK_RATE_MS ) + +/* Constants used by the vMemCheckTask() task. */ +#define mainCOUNT_INITIAL_VALUE ( ( unsigned portLONG ) 0 ) +#define mainNO_TASK ( 0 ) + +/* The size of the memory blocks allocated by the vMemCheckTask() task. */ +#define mainMEM_CHECK_SIZE_1 ( ( size_t ) 51 ) +#define mainMEM_CHECK_SIZE_2 ( ( size_t ) 52 ) +#define mainMEM_CHECK_SIZE_3 ( ( size_t ) 151 ) + +/* ------------------------ Static variables ------------------------------ */ +xComPortHandle xSTDComPort = NULL; + +/* ------------------------ Static functions ------------------------------ */ +static portTASK_FUNCTION( vErrorChecks, pvParameters ); +static portLONG prvCheckOtherTasksAreStillRunning( unsigned portLONG + ulMemCheckTaskCount ); +static portTASK_FUNCTION( vMemCheckTask, pvParameters ); + +/* ------------------------ Implementation -------------------------------- */ +int +main( int argc, char *argv[] ) +{ + asm volatile ( "move.w #0x2000, %sr\n\t" ); + + xSTDComPort = xSerialPortInitMinimal( 38400, 8 ); + + /* Start the demo/test application tasks. */ + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartMathTasks( tskIDLE_PRIORITY ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartDynamicPriorityTasks( ); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + + /* Start the check task - which is defined in this file. */ + xTaskCreate( vErrorChecks, ( signed portCHAR * )"Check", 512, NULL, + mainCHECK_TASK_PRIORITY, NULL ); + + /* Now all the tasks have been started - start the scheduler. */ + vTaskStartScheduler( ); + + /* Should never get here! */ + return 0; +} + + + +static +portTASK_FUNCTION( vErrorChecks, pvParameters ) +{ + unsigned portLONG ulMemCheckTaskRunningCount; + xTaskHandle xCreatedTask; + + /* The parameters are not used in this function. */ + ( void )pvParameters; + + xSerialPortInitMinimal( mainCOM_TEST_BAUD_RATE, 8 ); + + for( ;; ) + { + ulMemCheckTaskRunningCount = mainCOUNT_INITIAL_VALUE; + xCreatedTask = mainNO_TASK; + + if( xTaskCreate + ( vMemCheckTask, ( signed portCHAR * )"MEM_CHECK", + configMINIMAL_STACK_SIZE, ( void * )&ulMemCheckTaskRunningCount, + tskIDLE_PRIORITY, &xCreatedTask ) != pdPASS ) + { + xSerialPutChar( xSTDComPort, 'E', portMAX_DELAY ); + } + + /* Delay until it is time to execute again. */ + vTaskDelay( mainCHECK_PERIOD ); + + /* Delete the dynamically created task. */ + if( xCreatedTask != mainNO_TASK ) + { + vTaskDelete( xCreatedTask ); + } + + if( prvCheckOtherTasksAreStillRunning( ulMemCheckTaskRunningCount ) != + pdPASS ) + { + xSerialPutChar( xSTDComPort, 'E', portMAX_DELAY ); + } + else + { + xSerialPutChar( xSTDComPort, '.', portMAX_DELAY ); + } + } +} + +static portLONG +prvCheckOtherTasksAreStillRunning( unsigned portLONG ulMemCheckTaskCount ) +{ + portLONG lReturn = ( portLONG ) pdPASS; + + /* Check all the demo tasks (other than the flash tasks) to ensure + * that they are all still running, and that none of them have detected + * an error. + */ + + if( xAreIntegerMathsTaskStillRunning( ) != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xArePollingQueuesStillRunning( ) != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreMathsTaskStillRunning( ) != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreSemaphoreTasksStillRunning( ) != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreDynamicPriorityTasksStillRunning( ) != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreBlockingQueuesStillRunning( ) != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + if( ulMemCheckTaskCount == mainCOUNT_INITIAL_VALUE ) + { + // The vMemCheckTask did not increment the counter - it must + // have failed. + lReturn = ( portLONG ) pdFAIL; + } + return lReturn; +} + +static void +vMemCheckTask( void *pvParameters ) +{ + unsigned portLONG *pulMemCheckTaskRunningCounter; + void *pvMem1, *pvMem2, *pvMem3; + static portLONG lErrorOccurred = pdFALSE; + + /* This task is dynamically created then deleted during each cycle of the + vErrorChecks task to check the operation of the memory allocator. Each time + the task is created memory is allocated for the stack and TCB. Each time + the task is deleted this memory is returned to the heap. This task itself + exercises the allocator by allocating and freeing blocks. + + The task executes at the idle priority so does not require a delay. + + pulMemCheckTaskRunningCounter is incremented each cycle to indicate to the + vErrorChecks() task that this task is still executing without error. */ + + pulMemCheckTaskRunningCounter = ( unsigned portLONG * )pvParameters; + + for( ;; ) + { + if( lErrorOccurred == pdFALSE ) + { + /* We have never seen an error so increment the counter. */ + ( *pulMemCheckTaskRunningCounter )++; + } + + /* Allocate some memory - just to give the allocator some extra + exercise. This has to be in a critical section to ensure the + task does not get deleted while it has memory allocated. */ + vTaskSuspendAll( ); + { + pvMem1 = pvPortMalloc( mainMEM_CHECK_SIZE_1 ); + if( pvMem1 == NULL ) + { + lErrorOccurred = pdTRUE; + } + else + { + memset( pvMem1, 0xaa, mainMEM_CHECK_SIZE_1 ); + vPortFree( pvMem1 ); + } + } + xTaskResumeAll( ); + + /* Again - with a different size block. */ + vTaskSuspendAll( ); + { + pvMem2 = pvPortMalloc( mainMEM_CHECK_SIZE_2 ); + if( pvMem2 == NULL ) + { + lErrorOccurred = pdTRUE; + } + else + { + memset( pvMem2, 0xaa, mainMEM_CHECK_SIZE_2 ); + vPortFree( pvMem2 ); + } + } + xTaskResumeAll( ); + + /* Again - with a different size block. */ + vTaskSuspendAll( ); + { + pvMem3 = pvPortMalloc( mainMEM_CHECK_SIZE_3 ); + if( pvMem3 == NULL ) + { + lErrorOccurred = pdTRUE; + } + else + { + memset( pvMem3, 0xaa, mainMEM_CHECK_SIZE_3 ); + vPortFree( pvMem3 ); + } + } + xTaskResumeAll( ); + } +} + +void +vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ +} + +void +vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +} diff --git a/20080212/Demo/MCF5235_GCC/include/arch/mcf523x.h b/20080212/Demo/MCF5235_GCC/include/arch/mcf523x.h new file mode 100644 index 000000000..ae9dd63f6 --- /dev/null +++ b/20080212/Demo/MCF5235_GCC/include/arch/mcf523x.h @@ -0,0 +1,46 @@ +/* + * These files are taken from the MCF523X source code example package + * which is available on the Freescale website. Freescale explicitly + * grants the redistribution and modification of these source files. + * The complete licensing information is available in the file + * LICENSE_FREESCALE.TXT. + * + * File: mcf523x.h + * Purpose: Register and bit definitions for the MCF523X + * + * Notes: + * + */ + +#ifndef __MCF523X_H__ +#define __MCF523X_H__ + +/*********************************************************************/ + +#include "mcf523x/mcf523x_fec.h" +#include "mcf523x/mcf523x_rng.h" +#include "mcf523x/mcf523x_fmpll.h" +#include "mcf523x/mcf523x_cs.h" +#include "mcf523x/mcf523x_intc0.h" +#include "mcf523x/mcf523x_intc1.h" +#include "mcf523x/mcf523x_sdramc.h" +#include "mcf523x/mcf523x_sram.h" +#include "mcf523x/mcf523x_uart.h" +#include "mcf523x/mcf523x_timer.h" +#include "mcf523x/mcf523x_qspi.h" +#include "mcf523x/mcf523x_eport.h" +#include "mcf523x/mcf523x_i2c.h" +#include "mcf523x/mcf523x_scm.h" +#include "mcf523x/mcf523x_pit.h" +#include "mcf523x/mcf523x_can.h" +#include "mcf523x/mcf523x_wtm.h" +#include "mcf523x/mcf523x_gpio.h" +#include "mcf523x/mcf523x_mdha.h" +#include "mcf523x/mcf523x_ccm.h" +#include "mcf523x/mcf523x_rcm.h" +#include "mcf523x/mcf523x_etpu.h" + + +/********************************************************************/ + +#endif /* __MCF523X_H__ */ diff --git a/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_can.h b/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_can.h new file mode 100644 index 000000000..a193ba6fd --- /dev/null +++ b/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_can.h @@ -0,0 +1,325 @@ +/* + * These files are taken from the MCF523X source code example package + * which is available on the Freescale website. Freescale explicitly + * grants the redistribution and modification of these source files. + * The complete licensing information is available in the file + * LICENSE_FREESCALE.TXT. + * + * File: mcf523x_can.h + * Purpose: Register and bit definitions for the MCF523X + * + * Notes: + * + */ + +#ifndef __MCF523X_CAN_H__ +#define __MCF523X_CAN_H__ + +/********************************************************************* +* +* FlexCAN Module (CAN) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_CAN_CANMCR0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0000])) +#define MCF_CAN_CANCTRL0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0004])) +#define MCF_CAN_TIMER0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0008])) +#define MCF_CAN_RXGMASK0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0010])) +#define MCF_CAN_RX14MASK0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0014])) +#define MCF_CAN_RX15MASK0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0018])) +#define MCF_CAN_ERRCNT0 (*(vuint32*)(void*)(&__IPSBAR[0x1C001C])) +#define MCF_CAN_ERRSTAT0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0020])) +#define MCF_CAN_IMASK0 (*(vuint16*)(void*)(&__IPSBAR[0x1C002A])) +#define MCF_CAN_IFLAG0 (*(vuint16*)(void*)(&__IPSBAR[0x1C0032])) +#define MCF_CAN_CANMCR1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0000])) +#define MCF_CAN_CANCTRL1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0004])) +#define MCF_CAN_TIMER1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0008])) +#define MCF_CAN_RXGMASK1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0010])) +#define MCF_CAN_RX14MASK1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0014])) +#define MCF_CAN_RX15MASK1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0018])) +#define MCF_CAN_ERRCNT1 (*(vuint32*)(void*)(&__IPSBAR[0x1F001C])) +#define MCF_CAN_ERRSTAT1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0020])) +#define MCF_CAN_IMASK1 (*(vuint16*)(void*)(&__IPSBAR[0x1F002A])) +#define MCF_CAN_IFLAG1 (*(vuint16*)(void*)(&__IPSBAR[0x1F0032])) +#define MCF_CAN_CANMCR(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0000+((x)*0x30000)])) +#define MCF_CAN_CANCTRL(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0004+((x)*0x30000)])) +#define MCF_CAN_TIMER(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0008+((x)*0x30000)])) +#define MCF_CAN_RXGMASK(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0010+((x)*0x30000)])) +#define MCF_CAN_RX14MASK(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0014+((x)*0x30000)])) +#define MCF_CAN_RX15MASK(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0018+((x)*0x30000)])) +#define MCF_CAN_ERRCNT(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C001C+((x)*0x30000)])) +#define MCF_CAN_ERRSTAT(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0020+((x)*0x30000)])) +#define MCF_CAN_IMASK(x) (*(vuint16*)(void*)(&__IPSBAR[0x1C002A+((x)*0x30000)])) +#define MCF_CAN_IFLAG(x) (*(vuint16*)(void*)(&__IPSBAR[0x1C0032+((x)*0x30000)])) + +#define MCF_CAN_MBUF0_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0080+((x)*0x30000)])) +#define MCF_CAN_MBUF0_TMSTP(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0082+((x)*0x30000)])) +#define MCF_CAN_MBUF0_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0084+((x)*0x30000)])) +#define MCF_CAN_MBUF0_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0088+((x)*0x30000)])) +#define MCF_CAN_MBUF0_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0089+((x)*0x30000)])) +#define MCF_CAN_MBUF0_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008A+((x)*0x30000)])) +#define MCF_CAN_MBUF0_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008B+((x)*0x30000)])) +#define MCF_CAN_MBUF0_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008C+((x)*0x30000)])) +#define MCF_CAN_MBUF0_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008D+((x)*0x30000)])) +#define MCF_CAN_MBUF0_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008E+((x)*0x30000)])) +#define MCF_CAN_MBUF0_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008F+((x)*0x30000)])) +#define MCF_CAN_MBUF1_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0090+((x)*0x30000)])) +#define MCF_CAN_MBUF1_TMSTP(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0092+((x)*0x30000)])) +#define MCF_CAN_MBUF1_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0094+((x)*0x30000)])) +#define MCF_CAN_MBUF1_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0098+((x)*0x30000)])) +#define MCF_CAN_MBUF1_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0099+((x)*0x30000)])) +#define MCF_CAN_MBUF1_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009A+((x)*0x30000)])) +#define MCF_CAN_MBUF1_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009B+((x)*0x30000)])) +#define MCF_CAN_MBUF1_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009C+((x)*0x30000)])) +#define MCF_CAN_MBUF1_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009D+((x)*0x30000)])) +#define MCF_CAN_MBUF1_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009E+((x)*0x30000)])) +#define MCF_CAN_MBUF1_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009F+((x)*0x30000)])) +#define MCF_CAN_MBUF2_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00A0+((x)*0x30000)])) +#define MCF_CAN_MBUF2_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00A4+((x)*0x30000)])) +#define MCF_CAN_MBUF2_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00A8+((x)*0x30000)])) +#define MCF_CAN_MBUF2_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00A9+((x)*0x30000)])) +#define MCF_CAN_MBUF2_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AA+((x)*0x30000)])) +#define MCF_CAN_MBUF2_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AB+((x)*0x30000)])) +#define MCF_CAN_MBUF2_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AC+((x)*0x30000)])) +#define MCF_CAN_MBUF2_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AD+((x)*0x30000)])) +#define MCF_CAN_MBUF2_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AE+((x)*0x30000)])) +#define MCF_CAN_MBUF2_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AF+((x)*0x30000)])) +#define MCF_CAN_MBUF3_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00B0+((x)*0x30000)])) +#define MCF_CAN_MBUF3_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00B4+((x)*0x30000)])) +#define MCF_CAN_MBUF3_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00B8+((x)*0x30000)])) +#define MCF_CAN_MBUF3_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00B9+((x)*0x30000)])) +#define MCF_CAN_MBUF3_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BA+((x)*0x30000)])) +#define MCF_CAN_MBUF3_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BB+((x)*0x30000)])) +#define MCF_CAN_MBUF3_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BC+((x)*0x30000)])) +#define MCF_CAN_MBUF3_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BD+((x)*0x30000)])) +#define MCF_CAN_MBUF3_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BE+((x)*0x30000)])) +#define MCF_CAN_MBUF3_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BF+((x)*0x30000)])) +#define MCF_CAN_MBUF4_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00C0+((x)*0x30000)])) +#define MCF_CAN_MBUF4_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00C4+((x)*0x30000)])) +#define MCF_CAN_MBUF4_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00C8+((x)*0x30000)])) +#define MCF_CAN_MBUF4_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00C9+((x)*0x30000)])) +#define MCF_CAN_MBUF4_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CA+((x)*0x30000)])) +#define MCF_CAN_MBUF4_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CB+((x)*0x30000)])) +#define MCF_CAN_MBUF4_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CC+((x)*0x30000)])) +#define MCF_CAN_MBUF4_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CD+((x)*0x30000)])) +#define MCF_CAN_MBUF4_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CE+((x)*0x30000)])) +#define MCF_CAN_MBUF4_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CF+((x)*0x30000)])) +#define MCF_CAN_MBUF5_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00D0+((x)*0x30000)])) +#define MCF_CAN_MBUF5_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00D4+((x)*0x30000)])) +#define MCF_CAN_MBUF5_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00D8+((x)*0x30000)])) +#define MCF_CAN_MBUF5_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00D9+((x)*0x30000)])) +#define MCF_CAN_MBUF5_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DA+((x)*0x30000)])) +#define MCF_CAN_MBUF5_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DB+((x)*0x30000)])) +#define MCF_CAN_MBUF5_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DC+((x)*0x30000)])) +#define MCF_CAN_MBUF5_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DD+((x)*0x30000)])) +#define MCF_CAN_MBUF5_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DE+((x)*0x30000)])) +#define MCF_CAN_MBUF5_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DF+((x)*0x30000)])) +#define MCF_CAN_MBUF6_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00E0+((x)*0x30000)])) +#define MCF_CAN_MBUF6_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00E4+((x)*0x30000)])) +#define MCF_CAN_MBUF6_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00E8+((x)*0x30000)])) +#define MCF_CAN_MBUF6_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00E9+((x)*0x30000)])) +#define MCF_CAN_MBUF6_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EA+((x)*0x30000)])) +#define MCF_CAN_MBUF6_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EB+((x)*0x30000)])) +#define MCF_CAN_MBUF6_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EC+((x)*0x30000)])) +#define MCF_CAN_MBUF6_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00ED+((x)*0x30000)])) +#define MCF_CAN_MBUF6_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EE+((x)*0x30000)])) +#define MCF_CAN_MBUF6_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EF+((x)*0x30000)])) +#define MCF_CAN_MBUF7_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00F0+((x)*0x30000)])) +#define MCF_CAN_MBUF7_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00F4+((x)*0x30000)])) +#define MCF_CAN_MBUF7_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00F8+((x)*0x30000)])) +#define MCF_CAN_MBUF7_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00F9+((x)*0x30000)])) +#define MCF_CAN_MBUF7_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FA+((x)*0x30000)])) +#define MCF_CAN_MBUF7_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FB+((x)*0x30000)])) +#define MCF_CAN_MBUF7_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FC+((x)*0x30000)])) +#define MCF_CAN_MBUF7_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FD+((x)*0x30000)])) +#define MCF_CAN_MBUF7_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FE+((x)*0x30000)])) +#define MCF_CAN_MBUF7_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FF+((x)*0x30000)])) +#define MCF_CAN_MBUF8_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0100+((x)*0x30000)])) +#define MCF_CAN_MBUF8_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0104+((x)*0x30000)])) +#define MCF_CAN_MBUF8_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0108+((x)*0x30000)])) +#define MCF_CAN_MBUF8_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0109+((x)*0x30000)])) +#define MCF_CAN_MBUF8_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010A+((x)*0x30000)])) +#define MCF_CAN_MBUF8_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010B+((x)*0x30000)])) +#define MCF_CAN_MBUF8_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010C+((x)*0x30000)])) +#define MCF_CAN_MBUF8_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010D+((x)*0x30000)])) +#define MCF_CAN_MBUF8_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010E+((x)*0x30000)])) +#define MCF_CAN_MBUF8_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010F+((x)*0x30000)])) +#define MCF_CAN_MBUF9_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0100+((x)*0x30000)])) +#define MCF_CAN_MBUF9_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0114+((x)*0x30000)])) +#define MCF_CAN_MBUF9_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0118+((x)*0x30000)])) +#define MCF_CAN_MBUF9_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0119+((x)*0x30000)])) +#define MCF_CAN_MBUF9_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011A+((x)*0x30000)])) +#define MCF_CAN_MBUF9_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011B+((x)*0x30000)])) +#define MCF_CAN_MBUF9_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011C+((x)*0x30000)])) +#define MCF_CAN_MBUF9_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011D+((x)*0x30000)])) +#define MCF_CAN_MBUF9_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011E+((x)*0x30000)])) +#define MCF_CAN_MBUF9_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011F+((x)*0x30000)])) +#define MCF_CAN_MBUF10_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0120+((x)*0x30000)])) +#define MCF_CAN_MBUF10_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0124+((x)*0x30000)])) +#define MCF_CAN_MBUF10_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0128+((x)*0x30000)])) +#define MCF_CAN_MBUF10_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0129+((x)*0x30000)])) +#define MCF_CAN_MBUF10_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012A+((x)*0x30000)])) +#define MCF_CAN_MBUF10_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012B+((x)*0x30000)])) +#define MCF_CAN_MBUF10_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012C+((x)*0x30000)])) +#define MCF_CAN_MBUF10_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012D+((x)*0x30000)])) +#define MCF_CAN_MBUF10_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012E+((x)*0x30000)])) +#define MCF_CAN_MBUF10_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012F+((x)*0x30000)])) +#define MCF_CAN_MBUF11_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0130+((x)*0x30000)])) +#define MCF_CAN_MBUF11_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0134+((x)*0x30000)])) +#define MCF_CAN_MBUF11_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0138+((x)*0x30000)])) +#define MCF_CAN_MBUF11_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0139+((x)*0x30000)])) +#define MCF_CAN_MBUF11_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013A+((x)*0x30000)])) +#define MCF_CAN_MBUF11_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013B+((x)*0x30000)])) +#define MCF_CAN_MBUF11_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013C+((x)*0x30000)])) +#define MCF_CAN_MBUF11_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013D+((x)*0x30000)])) +#define MCF_CAN_MBUF11_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013E+((x)*0x30000)])) +#define MCF_CAN_MBUF11_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013F+((x)*0x30000)])) +#define MCF_CAN_MBUF12_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0140+((x)*0x30000)])) +#define MCF_CAN_MBUF12_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0144+((x)*0x30000)])) +#define MCF_CAN_MBUF12_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0148+((x)*0x30000)])) +#define MCF_CAN_MBUF12_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0149+((x)*0x30000)])) +#define MCF_CAN_MBUF12_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014A+((x)*0x30000)])) +#define MCF_CAN_MBUF12_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014B+((x)*0x30000)])) +#define MCF_CAN_MBUF12_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014C+((x)*0x30000)])) +#define MCF_CAN_MBUF12_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014D+((x)*0x30000)])) +#define MCF_CAN_MBUF12_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014E+((x)*0x30000)])) +#define MCF_CAN_MBUF12_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014F+((x)*0x30000)])) +#define MCF_CAN_MBUF13_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0150+((x)*0x30000)])) +#define MCF_CAN_MBUF13_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0154+((x)*0x30000)])) +#define MCF_CAN_MBUF13_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0158+((x)*0x30000)])) +#define MCF_CAN_MBUF13_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0159+((x)*0x30000)])) +#define MCF_CAN_MBUF13_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015A+((x)*0x30000)])) +#define MCF_CAN_MBUF13_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015B+((x)*0x30000)])) +#define MCF_CAN_MBUF13_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015C+((x)*0x30000)])) +#define MCF_CAN_MBUF13_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015D+((x)*0x30000)])) +#define MCF_CAN_MBUF13_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015E+((x)*0x30000)])) +#define MCF_CAN_MBUF13_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015F+((x)*0x30000)])) +#define MCF_CAN_MBUF14_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0160+((x)*0x30000)])) +#define MCF_CAN_MBUF14_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0164+((x)*0x30000)])) +#define MCF_CAN_MBUF14_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0168+((x)*0x30000)])) +#define MCF_CAN_MBUF14_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0169+((x)*0x30000)])) +#define MCF_CAN_MBUF14_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016A+((x)*0x30000)])) +#define MCF_CAN_MBUF14_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016B+((x)*0x30000)])) +#define MCF_CAN_MBUF14_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016C+((x)*0x30000)])) +#define MCF_CAN_MBUF14_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016D+((x)*0x30000)])) +#define MCF_CAN_MBUF14_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016E+((x)*0x30000)])) +#define MCF_CAN_MBUF14_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016F+((x)*0x30000)])) +#define MCF_CAN_MBUF15_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0170+((x)*0x30000)])) +#define MCF_CAN_MBUF15_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0174+((x)*0x30000)])) +#define MCF_CAN_MBUF15_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0178+((x)*0x30000)])) +#define MCF_CAN_MBUF15_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0179+((x)*0x30000)])) +#define MCF_CAN_MBUF15_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017A+((x)*0x30000)])) +#define MCF_CAN_MBUF15_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017B+((x)*0x30000)])) +#define MCF_CAN_MBUF15_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017C+((x)*0x30000)])) +#define MCF_CAN_MBUF15_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017D+((x)*0x30000)])) +#define MCF_CAN_MBUF15_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017E+((x)*0x30000)])) +#define MCF_CAN_MBUF15_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017F+((x)*0x30000)])) + + +#define MCF_CAN_MBUF0_DATAL(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0088+((x)*0x30000)])) +#define MCF_CAN_MBUF0_DATAH(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C008C+((x)*0x30000)])) +#define MCF_CAN_MBUF1_DATAL(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0098+((x)*0x30000)])) +#define MCF_CAN_MBUF1_DATAH(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C009C+((x)*0x30000)])) +#define MCF_CAN_MBUF2_DATAL(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00A8+((x)*0x30000)])) +#define MCF_CAN_MBUF2_DATAH(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00AC+((x)*0x30000)])) + + +/* Bit definitions and macros for MCF_CAN_CANMCR */ +#define MCF_CAN_CANMCR_MAXMB(x) (((x)&0x0000000F)<<0) +#define MCF_CAN_CANMCR_SUPV (0x00800000) +#define MCF_CAN_CANMCR_FRZACK (0x01000000) +#define MCF_CAN_CANMCR_SOFTRST (0x02000000) +#define MCF_CAN_CANMCR_HALT (0x10000000) +#define MCF_CAN_CANMCR_FRZ (0x40000000) +#define MCF_CAN_CANMCR_MDIS (0x80000000) + +/* Bit definitions and macros for MCF_CAN_CANCTRL */ +#define MCF_CAN_CANCTRL_PROPSEG(x) (((x)&0x00000007)<<0) +#define MCF_CAN_CANCTRL_LOM (0x00000008) +#define MCF_CAN_CANCTRL_LBUF (0x00000010) +#define MCF_CAN_CANCTRL_TSYNC (0x00000020) +#define MCF_CAN_CANCTRL_BOFFREC (0x00000040) +#define MCF_CAN_CANCTRL_SAMP (0x00000080) +#define MCF_CAN_CANCTRL_LPB (0x00001000) +#define MCF_CAN_CANCTRL_CLKSRC (0x00002000) +#define MCF_CAN_CANCTRL_ERRMSK (0x00004000) +#define MCF_CAN_CANCTRL_BOFFMSK (0x00008000) +#define MCF_CAN_CANCTRL_PSEG2(x) (((x)&0x00000007)<<16) +#define MCF_CAN_CANCTRL_PSEG1(x) (((x)&0x00000007)<<19) +#define MCF_CAN_CANCTRL_RJW(x) (((x)&0x00000003)<<22) +#define MCF_CAN_CANCTRL_PRESDIV(x) (((x)&0x000000FF)<<24) + +/* Bit definitions and macros for MCF_CAN_TIMER */ +#define MCF_CAN_TIMER_TIMER(x) (((x)&0x0000FFFF)<<0) + +/* Bit definitions and macros for MCF_CAN_RXGMASK */ +#define MCF_CAN_RXGMASK_MI(x) (((x)&0x1FFFFFFF)<<0) + +/* Bit definitions and macros for MCF_CAN_RX14MASK */ +#define MCF_CAN_RX14MASK_MI(x) (((x)&0x1FFFFFFF)<<0) + +/* Bit definitions and macros for MCF_CAN_RX15MASK */ +#define MCF_CAN_RX15MASK_MI(x) (((x)&0x1FFFFFFF)<<0) + +/* Bit definitions and macros for MCF_CAN_ERRCNT */ +#define MCF_CAN_ERRCNT_TXECTR(x) (((x)&0x000000FF)<<0) +#define MCF_CAN_ERRCNT_RXECTR(x) (((x)&0x000000FF)<<8) + +/* Bit definitions and macros for MCF_CAN_ERRSTAT */ +#define MCF_CAN_ERRSTAT_WAKINT (0x00000001) +#define MCF_CAN_ERRSTAT_ERRINT (0x00000002) +#define MCF_CAN_ERRSTAT_BOFFINT (0x00000004) +#define MCF_CAN_ERRSTAT_FLTCONF(x) (((x)&0x00000003)<<4) +#define MCF_CAN_ERRSTAT_TXRX (0x00000040) +#define MCF_CAN_ERRSTAT_IDLE (0x00000080) +#define MCF_CAN_ERRSTAT_RXWRN (0x00000100) +#define MCF_CAN_ERRSTAT_TXWRN (0x00000200) +#define MCF_CAN_ERRSTAT_STFERR (0x00000400) +#define MCF_CAN_ERRSTAT_FRMERR (0x00000800) +#define MCF_CAN_ERRSTAT_CRCERR (0x00001000) +#define MCF_CAN_ERRSTAT_ACKERR (0x00002000) +#define MCF_CAN_ERRSTAT_BITERR(x) (((x)&0x00000003)<<14) +#define MCF_CAN_ERRSTAT_FLTCONF_ACTIVE (0x00000000) +#define MCF_CAN_ERRSTAT_FLTCONF_PASSIVE (0x00000010) +#define MCF_CAN_ERRSTAT_FLTCONF_BUSOFF (0x00000020) + +/* Bit definitions and macros for MCF_CAN_IMASK */ +#define MCF_CAN_IMASK_BUF0M (0x0001) +#define MCF_CAN_IMASK_BUF1M (0x0002) +#define MCF_CAN_IMASK_BUF2M (0x0004) +#define MCF_CAN_IMASK_BUF3M (0x0008) +#define MCF_CAN_IMASK_BUF4M (0x0010) +#define MCF_CAN_IMASK_BUF5M (0x0020) +#define MCF_CAN_IMASK_BUF6M (0x0040) +#define MCF_CAN_IMASK_BUF7M (0x0080) +#define MCF_CAN_IMASK_BUF8M (0x0100) +#define MCF_CAN_IMASK_BUF9M (0x0200) +#define MCF_CAN_IMASK_BUF10M (0x0400) +#define MCF_CAN_IMASK_BUF11M (0x0800) +#define MCF_CAN_IMASK_BUF12M (0x1000) +#define MCF_CAN_IMASK_BUF13M (0x2000) +#define MCF_CAN_IMASK_BUF14M (0x4000) +#define MCF_CAN_IMASK_BUF15M (0x8000) + +/* Bit definitions and macros for MCF_CAN_IFLAG */ +#define MCF_CAN_IFLAG_BUF0I (0x0001) +#define MCF_CAN_IFLAG_BUF1I (0x0002) +#define MCF_CAN_IFLAG_BUF2I (0x0004) +#define MCF_CAN_IFLAG_BUF3I (0x0008) +#define MCF_CAN_IFLAG_BUF4I (0x0010) +#define MCF_CAN_IFLAG_BUF5I (0x0020) +#define MCF_CAN_IFLAG_BUF6I (0x0040) +#define MCF_CAN_IFLAG_BUF7I (0x0080) +#define MCF_CAN_IFLAG_BUF8I (0x0100) +#define MCF_CAN_IFLAG_BUF9I (0x0200) +#define MCF_CAN_IFLAG_BUF10I (0x0400) +#define MCF_CAN_IFLAG_BUF11I (0x0800) +#define MCF_CAN_IFLAG_BUF12I (0x1000) +#define MCF_CAN_IFLAG_BUF13I (0x2000) +#define MCF_CAN_IFLAG_BUF14I (0x4000) +#define MCF_CAN_IFLAG_BUF15I (0x8000) + +/********************************************************************/ + +#endif /* __MCF523X_CAN_H__ */ diff --git a/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_ccm.h b/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_ccm.h new file mode 100644 index 000000000..dd3b71c64 --- /dev/null +++ b/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_ccm.h @@ -0,0 +1,56 @@ +/* + * These files are taken from the MCF523X source code example package + * which is available on the Freescale website. Freescale explicitly + * grants the redistribution and modification of these source files. + * The complete licensing information is available in the file + * LICENSE_FREESCALE.TXT. + * + * File: mcf523x_ccm.h + * Purpose: Register and bit definitions for the MCF523X + * + * Notes: + * + */ + +#ifndef __MCF523X_CCM_H__ +#define __MCF523X_CCM_H__ + +/********************************************************************* +* +* Chip Configuration Module (CCM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_CCM_CCR (*(vuint16*)(void*)(&__IPSBAR[0x110004])) +#define MCF_CCM_LPCR (*(vuint8 *)(void*)(&__IPSBAR[0x110007])) +#define MCF_CCM_CIR (*(vuint16*)(void*)(&__IPSBAR[0x11000A])) +#define MCF_CCM_RCON (*(vuint16*)(void*)(&__IPSBAR[0x110008])) + +/* Bit definitions and macros for MCF_CCM_CCR */ +#define MCF_CCM_CCR_BMT(x) (((x)&0x0007)<<0) +#define MCF_CCM_CCR_BME (0x0008) +#define MCF_CCM_CCR_SZEN (0x0040) +#define MCF_CCM_CCR_MODE(x) (((x)&0x0007)<<8) + +/* Bit definitions and macros for MCF_CCM_LPCR */ +#define MCF_CCM_LPCR_STPMD(x) (((x)&0x03)<<3) +#define MCF_CCM_LPCR_LPMD(x) (((x)&0x03)<<6) +#define MCF_CCM_LPCR_LPMD_STOP (0xC0) +#define MCF_CCM_LPCR_LPMD_WAIT (0x80) +#define MCF_CCM_LPCR_LPMD_DOZE (0x40) +#define MCF_CCM_LPCR_LPMD_RUN (0x00) + +/* Bit definitions and macros for MCF_CCM_CIR */ +#define MCF_CCM_CIR_PRN(x) (((x)&0x003F)<<0) +#define MCF_CCM_CIR_PIN(x) (((x)&0x03FF)<<6) + +/* Bit definitions and macros for MCF_CCM_RCON */ +#define MCF_CCM_RCON_MODE (0x0001) +#define MCF_CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3) +#define MCF_CCM_RCON_RLOAD (0x0020) +#define MCF_CCM_RCON_RCSC(x) (((x)&0x0003)<<8) + +/********************************************************************/ + +#endif /* __MCF523X_CCM_H__ */ diff --git a/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_cs.h b/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_cs.h new file mode 100644 index 000000000..240cdf214 --- /dev/null +++ b/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_cs.h @@ -0,0 +1,101 @@ +/* + * These files are taken from the MCF523X source code example package + * which is available on the Freescale website. Freescale explicitly + * grants the redistribution and modification of these source files. + * The complete licensing information is available in the file + * LICENSE_FREESCALE.TXT. + * + * File: mcf523x_cs.h + * Purpose: Register and bit definitions for the MCF523X + * + * Notes: + * + */ + +#ifndef __MCF523X_CS_H__ +#define __MCF523X_CS_H__ + +/********************************************************************* +* +* Chip Selects (CS) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_CS_CSAR0 (*(vuint16*)(void*)(&__IPSBAR[0x000080])) +#define MCF_CS_CSMR0 (*(vuint32*)(void*)(&__IPSBAR[0x000084])) +#define MCF_CS_CSCR0 (*(vuint16*)(void*)(&__IPSBAR[0x00008A])) +#define MCF_CS_CSAR1 (*(vuint16*)(void*)(&__IPSBAR[0x00008C])) +#define MCF_CS_CSMR1 (*(vuint32*)(void*)(&__IPSBAR[0x000090])) +#define MCF_CS_CSCR1 (*(vuint16*)(void*)(&__IPSBAR[0x000096])) +#define MCF_CS_CSAR2 (*(vuint16*)(void*)(&__IPSBAR[0x000098])) +#define MCF_CS_CSMR2 (*(vuint32*)(void*)(&__IPSBAR[0x00009C])) +#define MCF_CS_CSCR2 (*(vuint16*)(void*)(&__IPSBAR[0x0000A2])) +#define MCF_CS_CSAR3 (*(vuint16*)(void*)(&__IPSBAR[0x0000A4])) +#define MCF_CS_CSMR3 (*(vuint32*)(void*)(&__IPSBAR[0x0000A8])) +#define MCF_CS_CSCR3 (*(vuint16*)(void*)(&__IPSBAR[0x0000AE])) +#define MCF_CS_CSAR4 (*(vuint16*)(void*)(&__IPSBAR[0x0000B0])) +#define MCF_CS_CSMR4 (*(vuint32*)(void*)(&__IPSBAR[0x0000B4])) +#define MCF_CS_CSCR4 (*(vuint16*)(void*)(&__IPSBAR[0x0000BA])) +#define MCF_CS_CSAR5 (*(vuint16*)(void*)(&__IPSBAR[0x0000BC])) +#define MCF_CS_CSMR5 (*(vuint32*)(void*)(&__IPSBAR[0x0000C0])) +#define MCF_CS_CSCR5 (*(vuint16*)(void*)(&__IPSBAR[0x0000C6])) +#define MCF_CS_CSAR6 (*(vuint16*)(void*)(&__IPSBAR[0x0000C8])) +#define MCF_CS_CSMR6 (*(vuint32*)(void*)(&__IPSBAR[0x0000CC])) +#define MCF_CS_CSCR6 (*(vuint16*)(void*)(&__IPSBAR[0x0000D2])) +#define MCF_CS_CSAR7 (*(vuint16*)(void*)(&__IPSBAR[0x0000D4])) +#define MCF_CS_CSMR7 (*(vuint32*)(void*)(&__IPSBAR[0x0000D8])) +#define MCF_CS_CSCR7 (*(vuint16*)(void*)(&__IPSBAR[0x0000DE])) +#define MCF_CS_CSAR(x) (*(vuint16*)(void*)(&__IPSBAR[0x000080+((x)*0x00C)])) +#define MCF_CS_CSMR(x) (*(vuint32*)(void*)(&__IPSBAR[0x000084+((x)*0x00C)])) +#define MCF_CS_CSCR(x) (*(vuint16*)(void*)(&__IPSBAR[0x00008A+((x)*0x00C)])) + +/* Bit definitions and macros for MCF_CS_CSAR */ +#define MCF_CS_CSAR_BA(x) ((uint16)(((x)&0xFFFF0000)>>16)) + +/* Bit definitions and macros for MCF_CS_CSMR */ +#define MCF_CS_CSMR_V (0x00000001) +#define MCF_CS_CSMR_UD (0x00000002) +#define MCF_CS_CSMR_UC (0x00000004) +#define MCF_CS_CSMR_SD (0x00000008) +#define MCF_CS_CSMR_SC (0x00000010) +#define MCF_CS_CSMR_CI (0x00000020) +#define MCF_CS_CSMR_AM (0x00000040) +#define MCF_CS_CSMR_WP (0x00000100) +#define MCF_CS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16) +#define MCF_CS_CSMR_BAM_4G (0xFFFF0000) +#define MCF_CS_CSMR_BAM_2G (0x7FFF0000) +#define MCF_CS_CSMR_BAM_1G (0x3FFF0000) +#define MCF_CS_CSMR_BAM_1024M (0x3FFF0000) +#define MCF_CS_CSMR_BAM_512M (0x1FFF0000) +#define MCF_CS_CSMR_BAM_256M (0x0FFF0000) +#define MCF_CS_CSMR_BAM_128M (0x07FF0000) +#define MCF_CS_CSMR_BAM_64M (0x03FF0000) +#define MCF_CS_CSMR_BAM_32M (0x01FF0000) +#define MCF_CS_CSMR_BAM_16M (0x00FF0000) +#define MCF_CS_CSMR_BAM_8M (0x007F0000) +#define MCF_CS_CSMR_BAM_4M (0x003F0000) +#define MCF_CS_CSMR_BAM_2M (0x001F0000) +#define MCF_CS_CSMR_BAM_1M (0x000F0000) +#define MCF_CS_CSMR_BAM_1024K (0x000F0000) +#define MCF_CS_CSMR_BAM_512K (0x00070000) +#define MCF_CS_CSMR_BAM_256K (0x00030000) +#define MCF_CS_CSMR_BAM_128K (0x00010000) +#define MCF_CS_CSMR_BAM_64K (0x00000000) + +/* Bit definitions and macros for MCF_CS_CSCR */ +#define MCF_CS_CSCR_SWWS(x) (((x)&0x0007)<<0) +#define MCF_CS_CSCR_BSTW (0x0008) +#define MCF_CS_CSCR_BSTR (0x0010) +#define MCF_CS_CSCR_BEM (0x0020) +#define MCF_CS_CSCR_PS(x) (((x)&0x0003)<<6) +#define MCF_CS_CSCR_AA (0x0100) +#define MCF_CS_CSCR_IWS(x) (((x)&0x000F)<<10) +#define MCF_CS_CSCR_SRWS(x) (((x)&0x0003)<<14) +#define MCF_CS_CSCR_PS_8 (0x0040) +#define MCF_CS_CSCR_PS_16 (0x0080) +#define MCF_CS_CSCR_PS_32 (0x0000) + +/********************************************************************/ + +#endif /* __MCF523X_CS_H__ */ diff --git a/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_eport.h b/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_eport.h new file mode 100644 index 000000000..9ee8d7c1c --- /dev/null +++ b/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_eport.h @@ -0,0 +1,92 @@ +/* + * These files are taken from the MCF523X source code example package + * which is available on the Freescale website. Freescale explicitly + * grants the redistribution and modification of these source files. + * The complete licensing information is available in the file + * LICENSE_FREESCALE.TXT. + * + * File: mcf523x_eport.h + * Purpose: Register and bit definitions for the MCF523X + * + * Notes: + * + */ + +#ifndef __MCF523X_EPORT_H__ +#define __MCF523X_EPORT_H__ + +/********************************************************************* +* +* Edge Port Module (EPORT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_EPORT_EPPAR (*(vuint16*)(void*)(&__IPSBAR[0x130000])) +#define MCF_EPORT_EPDDR (*(vuint8 *)(void*)(&__IPSBAR[0x130002])) +#define MCF_EPORT_EPIER (*(vuint8 *)(void*)(&__IPSBAR[0x130003])) +#define MCF_EPORT_EPDR (*(vuint8 *)(void*)(&__IPSBAR[0x130004])) +#define MCF_EPORT_EPPDR (*(vuint8 *)(void*)(&__IPSBAR[0x130005])) +#define MCF_EPORT_EPFR (*(vuint8 *)(void*)(&__IPSBAR[0x130006])) + +/* Bit definitions and macros for MCF_EPORT_EPPAR */ +#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2) +#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4) +#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6) +#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8) +#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10) +#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12) +#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14) +#define MCF_EPORT_EPPAR_EPPAx_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPAx_RISING (1) +#define MCF_EPORT_EPPAR_EPPAx_FALLING (2) +#define MCF_EPORT_EPPAR_EPPAx_BOTH (3) + +/* Bit definitions and macros for MCF_EPORT_EPDDR */ +#define MCF_EPORT_EPDDR_EPDD1 (0x02) +#define MCF_EPORT_EPDDR_EPDD2 (0x04) +#define MCF_EPORT_EPDDR_EPDD3 (0x08) +#define MCF_EPORT_EPDDR_EPDD4 (0x10) +#define MCF_EPORT_EPDDR_EPDD5 (0x20) +#define MCF_EPORT_EPDDR_EPDD6 (0x40) +#define MCF_EPORT_EPDDR_EPDD7 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPIER */ +#define MCF_EPORT_EPIER_EPIE1 (0x02) +#define MCF_EPORT_EPIER_EPIE2 (0x04) +#define MCF_EPORT_EPIER_EPIE3 (0x08) +#define MCF_EPORT_EPIER_EPIE4 (0x10) +#define MCF_EPORT_EPIER_EPIE5 (0x20) +#define MCF_EPORT_EPIER_EPIE6 (0x40) +#define MCF_EPORT_EPIER_EPIE7 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPDR */ +#define MCF_EPORT_EPDR_EPD1 (0x02) +#define MCF_EPORT_EPDR_EPD2 (0x04) +#define MCF_EPORT_EPDR_EPD3 (0x08) +#define MCF_EPORT_EPDR_EPD4 (0x10) +#define MCF_EPORT_EPDR_EPD5 (0x20) +#define MCF_EPORT_EPDR_EPD6 (0x40) +#define MCF_EPORT_EPDR_EPD7 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPPDR */ +#define MCF_EPORT_EPPDR_EPPD1 (0x02) +#define MCF_EPORT_EPPDR_EPPD2 (0x04) +#define MCF_EPORT_EPPDR_EPPD3 (0x08) +#define MCF_EPORT_EPPDR_EPPD4 (0x10) +#define MCF_EPORT_EPPDR_EPPD5 (0x20) +#define MCF_EPORT_EPPDR_EPPD6 (0x40) +#define MCF_EPORT_EPPDR_EPPD7 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPFR */ +#define MCF_EPORT_EPFR_EPF1 (0x02) +#define MCF_EPORT_EPFR_EPF2 (0x04) +#define MCF_EPORT_EPFR_EPF3 (0x08) +#define MCF_EPORT_EPFR_EPF4 (0x10) +#define MCF_EPORT_EPFR_EPF5 (0x20) +#define MCF_EPORT_EPFR_EPF6 (0x40) +#define MCF_EPORT_EPFR_EPF7 (0x80) + +/********************************************************************/ + +#endif /* __MCF523X_EPORT_H__ */ diff --git a/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_etpu.h b/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_etpu.h new file mode 100644 index 000000000..5a0d9ca74 --- /dev/null +++ b/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_etpu.h @@ -0,0 +1,493 @@ +/* + * These files are taken from the MCF523X source code example package + * which is available on the Freescale website. Freescale explicitly + * grants the redistribution and modification of these source files. + * The complete licensing information is available in the file + * LICENSE_FREESCALE.TXT. + * + * File: mcf523x_etpu.h + * Purpose: Register and bit definitions for the MCF523X + * + * Notes: + * + */ + +#ifndef __MCF523X_ETPU_H__ +#define __MCF523X_ETPU_H__ + +/********************************************************************* +* +* enhanced Time Processor Unit (ETPU) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_ETPU_EMCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0000])) +#define MCF_ETPU_ECDCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0004])) +#define MCF_ETPU_EMISCCR (*(vuint32*)(void*)(&__IPSBAR[0x1D000C])) +#define MCF_ETPU_ESCMODR (*(vuint32*)(void*)(&__IPSBAR[0x1D0010])) +#define MCF_ETPU_EECR (*(vuint32*)(void*)(&__IPSBAR[0x1D0014])) +#define MCF_ETPU_ETBCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0020])) +#define MCF_ETPU_ETB1R (*(vuint32*)(void*)(&__IPSBAR[0x1D0024])) +#define MCF_ETPU_ETB2R (*(vuint32*)(void*)(&__IPSBAR[0x1D0028])) +#define MCF_ETPU_EREDCR (*(vuint32*)(void*)(&__IPSBAR[0x1D002C])) +#define MCF_ETPU_ECISR (*(vuint32*)(void*)(&__IPSBAR[0x1D0200])) +#define MCF_ETPU_ECDTRSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0210])) +#define MCF_ETPU_ECIOSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0220])) +#define MCF_ETPU_ECDTROSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0230])) +#define MCF_ETPU_ECIER (*(vuint32*)(void*)(&__IPSBAR[0x1D0240])) +#define MCF_ETPU_ECDTRER (*(vuint32*)(void*)(&__IPSBAR[0x1D0250])) +#define MCF_ETPU_ECPSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0280])) +#define MCF_ETPU_ECSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0290])) +#define MCF_ETPU_EC0SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0404])) +#define MCF_ETPU_EC1SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0414])) +#define MCF_ETPU_EC2SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0424])) +#define MCF_ETPU_EC3SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0434])) +#define MCF_ETPU_EC4SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0444])) +#define MCF_ETPU_EC5SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0454])) +#define MCF_ETPU_EC6SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0464])) +#define MCF_ETPU_EC7SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0474])) +#define MCF_ETPU_EC8SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0484])) +#define MCF_ETPU_EC9SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0494])) +#define MCF_ETPU_EC10SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04A4])) +#define MCF_ETPU_EC11SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04B4])) +#define MCF_ETPU_EC12SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04C4])) +#define MCF_ETPU_EC13SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04D4])) +#define MCF_ETPU_EC14SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04E4])) +#define MCF_ETPU_EC15SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04F4])) +#define MCF_ETPU_EC16SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0504])) +#define MCF_ETPU_EC17SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0514])) +#define MCF_ETPU_EC18SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0524])) +#define MCF_ETPU_EC19SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0534])) +#define MCF_ETPU_EC20SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0544])) +#define MCF_ETPU_EC21SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0554])) +#define MCF_ETPU_EC22SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0564])) +#define MCF_ETPU_EC23SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0574])) +#define MCF_ETPU_EC24SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0584])) +#define MCF_ETPU_EC25SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0594])) +#define MCF_ETPU_EC26SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05A4])) +#define MCF_ETPU_EC27SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05B4])) +#define MCF_ETPU_EC28SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05C4])) +#define MCF_ETPU_EC29SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05D4])) +#define MCF_ETPU_EC30SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05E4])) +#define MCF_ETPU_EC31SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05F4])) +#define MCF_ETPU_ECnSCR(x) (*(vuint32*)(void*)(&__IPSBAR[0x1D0404+((x)*0x010)])) +#define MCF_ETPU_EC0CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0400])) +#define MCF_ETPU_EC1CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0410])) +#define MCF_ETPU_EC2CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0420])) +#define MCF_ETPU_EC3CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0430])) +#define MCF_ETPU_EC4CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0440])) +#define MCF_ETPU_EC5CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0450])) +#define MCF_ETPU_EC6CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0460])) +#define MCF_ETPU_EC7CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0470])) +#define MCF_ETPU_EC8CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0480])) +#define MCF_ETPU_EC9CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0490])) +#define MCF_ETPU_EC10CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04A0])) +#define MCF_ETPU_EC11CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04B0])) +#define MCF_ETPU_EC12CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04C0])) +#define MCF_ETPU_EC13CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04D0])) +#define MCF_ETPU_EC14CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04E0])) +#define MCF_ETPU_EC15CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04F0])) +#define MCF_ETPU_EC16CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0500])) +#define MCF_ETPU_EC17CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0510])) +#define MCF_ETPU_EC18CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0520])) +#define MCF_ETPU_EC19CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0530])) +#define MCF_ETPU_EC20CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0540])) +#define MCF_ETPU_EC21CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0550])) +#define MCF_ETPU_EC22CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0560])) +#define MCF_ETPU_EC23CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0570])) +#define MCF_ETPU_EC24CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0580])) +#define MCF_ETPU_EC25CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0590])) +#define MCF_ETPU_EC26CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05A0])) +#define MCF_ETPU_EC27CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05B0])) +#define MCF_ETPU_EC28CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05C0])) +#define MCF_ETPU_EC29CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05D0])) +#define MCF_ETPU_EC30CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05E0])) +#define MCF_ETPU_EC31CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05F0])) +#define MCF_ETPU_ECnCR(x) (*(vuint32*)(void*)(&__IPSBAR[0x1D0400+((x)*0x010)])) +#define MCF_ETPU_EC0HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0408])) +#define MCF_ETPU_EC1HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0418])) +#define MCF_ETPU_EC2HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0428])) +#define MCF_ETPU_EC3HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0438])) +#define MCF_ETPU_EC4HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0448])) +#define MCF_ETPU_EC5HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0458])) +#define MCF_ETPU_EC6HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0468])) +#define MCF_ETPU_EC7HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0478])) +#define MCF_ETPU_EC8HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0488])) +#define MCF_ETPU_EC9HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0498])) +#define MCF_ETPU_EC10HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04A8])) +#define MCF_ETPU_EC11HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04B8])) +#define MCF_ETPU_EC12HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04C8])) +#define MCF_ETPU_EC13HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04D8])) +#define MCF_ETPU_EC14HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04E8])) +#define MCF_ETPU_EC15HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04F8])) +#define MCF_ETPU_EC16HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0508])) +#define MCF_ETPU_EC17HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0518])) +#define MCF_ETPU_EC18HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0528])) +#define MCF_ETPU_EC19HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0538])) +#define MCF_ETPU_EC20HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0548])) +#define MCF_ETPU_EC21HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0558])) +#define MCF_ETPU_EC22HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0568])) +#define MCF_ETPU_EC23HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0578])) +#define MCF_ETPU_EC24HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0588])) +#define MCF_ETPU_EC25HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0598])) +#define MCF_ETPU_EC26HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05A8])) +#define MCF_ETPU_EC27HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05B8])) +#define MCF_ETPU_EC28HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05C8])) +#define MCF_ETPU_EC29HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05D8])) +#define MCF_ETPU_EC30HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05E8])) +#define MCF_ETPU_EC31HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05F8])) +#define MCF_ETPU_ECnHSSR(x) (*(vuint32*)(void*)(&__IPSBAR[0x1D0408+((x)*0x010)])) + +/* Bit definitions and macros for MCF_ETPU_EMCR */ +#define MCF_ETPU_EMCR_GTBE (0x00000001) +#define MCF_ETPU_EMCR_VIS (0x00000040) +#define MCF_ETPU_EMCR_SCMMISEN (0x00000200) +#define MCF_ETPU_EMCR_SCMMISF (0x00000400) +#define MCF_ETPU_EMCR_SCMSIZE(x) (((x)&0x0000001F)<<16) +#define MCF_ETPU_EMCR_ILF2 (0x01000000) +#define MCF_ETPU_EMCR_ILF1 (0x02000000) +#define MCF_ETPU_EMCR_MGE2 (0x04000000) +#define MCF_ETPU_EMCR_MGE1 (0x08000000) +#define MCF_ETPU_EMCR_GEC (0x80000000) + +/* Bit definitions and macros for MCF_ETPU_ECDCR */ +#define MCF_ETPU_ECDCR_PARM1(x) (((x)&0x0000007F)<<0) +#define MCF_ETPU_ECDCR_WR (0x00000080) +#define MCF_ETPU_ECDCR_PARM0(x) (((x)&0x0000007F)<<8) +#define MCF_ETPU_ECDCR_PWIDTH (0x00008000) +#define MCF_ETPU_ECDCR_PBASE(x) (((x)&0x000003FF)<<16) +#define MCF_ETPU_ECDCR_CTBASE(x) (((x)&0x0000001F)<<26) +#define MCF_ETPU_ECDCR_STS (0x80000000) + +/* Bit definitions and macros for MCF_ETPU_EECR */ +#define MCF_ETPU_EECR_ETB(x) (((x)&0x0000001F)<<0) +#define MCF_ETPU_EECR_CDFC(x) (((x)&0x00000003)<<14) +#define MCF_ETPU_EECR_FPSK(x) (((x)&0x00000007)<<16) +#define MCF_ETPU_EECR_HLTF (0x00800000) +#define MCF_ETPU_EECR_STF (0x10000000) +#define MCF_ETPU_EECR_MDIS (0x40000000) +#define MCF_ETPU_EECR_FEND (0x80000000) + +/* Bit definitions and macros for MCF_ETPU_ETBCR */ +#define MCF_ETPU_ETBCR_TCR1P(x) (((x)&0x000000FF)<<0) +#define MCF_ETPU_ETBCR_TCR1CTL(x) (((x)&0x00000003)<<14) +#define MCF_ETPU_ETBCR_TCR2P(x) (((x)&0x0000003F)<<16) +#define MCF_ETPU_ETBCR_AM (0x02000000) +#define MCF_ETPU_ETBCR_TCRCF(x) (((x)&0x00000003)<<27) +#define MCF_ETPU_ETBCR_TCR2CTL(x) (((x)&0x00000007)<<29) + +/* Bit definitions and macros for MCF_ETPU_ETB1R */ +#define MCF_ETPU_ETB1R_TCR1(x) (((x)&0x00FFFFFF)<<0) + +/* Bit definitions and macros for MCF_ETPU_ETB2R */ +#define MCF_ETPU_ETB2R_TCR2(x) (((x)&0x00FFFFFF)<<0) + +/* Bit definitions and macros for MCF_ETPU_EREDCR */ +#define MCF_ETPU_EREDCR_SRV2(x) (((x)&0x0000000F)<<0) +#define MCF_ETPU_EREDCR_SERVER_ID2(x) (((x)&0x0000000F)<<8) +#define MCF_ETPU_EREDCR_RSC2 (0x00004000) +#define MCF_ETPU_EREDCR_REN2 (0x00008000) +#define MCF_ETPU_EREDCR_SRV1(x) (((x)&0x0000000F)<<16) +#define MCF_ETPU_EREDCR_SERVER_ID1(x) (((x)&0x0000000F)<<24) +#define MCF_ETPU_EREDCR_RSC1 (0x40000000) +#define MCF_ETPU_EREDCR_REN1 (0x80000000) + +/* Bit definitions and macros for MCF_ETPU_ECISR */ +#define MCF_ETPU_ECISR_CIS0 (0x00000001) +#define MCF_ETPU_ECISR_CIS1 (0x00000002) +#define MCF_ETPU_ECISR_CIS2 (0x00000004) +#define MCF_ETPU_ECISR_CIS3 (0x00000008) +#define MCF_ETPU_ECISR_CIS4 (0x00000010) +#define MCF_ETPU_ECISR_CIS5 (0x00000020) +#define MCF_ETPU_ECISR_CIS6 (0x00000040) +#define MCF_ETPU_ECISR_CIS7 (0x00000080) +#define MCF_ETPU_ECISR_CIS8 (0x00000100) +#define MCF_ETPU_ECISR_CIS9 (0x00000200) +#define MCF_ETPU_ECISR_CIS10 (0x00000400) +#define MCF_ETPU_ECISR_CIS11 (0x00000800) +#define MCF_ETPU_ECISR_CIS12 (0x00001000) +#define MCF_ETPU_ECISR_CIS13 (0x00002000) +#define MCF_ETPU_ECISR_CIS14 (0x00004000) +#define MCF_ETPU_ECISR_CIS15 (0x00008000) +#define MCF_ETPU_ECISR_CIS16 (0x00010000) +#define MCF_ETPU_ECISR_CIS17 (0x00020000) +#define MCF_ETPU_ECISR_CIS18 (0x00040000) +#define MCF_ETPU_ECISR_CIS19 (0x00080000) +#define MCF_ETPU_ECISR_CIS20 (0x00100000) +#define MCF_ETPU_ECISR_CIS21 (0x00200000) +#define MCF_ETPU_ECISR_CIS22 (0x00400000) +#define MCF_ETPU_ECISR_CIS23 (0x00800000) +#define MCF_ETPU_ECISR_CIS24 (0x01000000) +#define MCF_ETPU_ECISR_CIS25 (0x02000000) +#define MCF_ETPU_ECISR_CIS26 (0x04000000) +#define MCF_ETPU_ECISR_CIS27 (0x08000000) +#define MCF_ETPU_ECISR_CIS28 (0x10000000) +#define MCF_ETPU_ECISR_CIS29 (0x20000000) +#define MCF_ETPU_ECISR_CIS30 (0x40000000) +#define MCF_ETPU_ECISR_CIS31 (0x80000000) + +/* Bit definitions and macros for MCF_ETPU_ECDTRSR */ +#define MCF_ETPU_ECDTRSR_DTRS0 (0x00000001) +#define MCF_ETPU_ECDTRSR_DTRS1 (0x00000002) +#define MCF_ETPU_ECDTRSR_DTRS2 (0x00000004) +#define MCF_ETPU_ECDTRSR_DTRS3 (0x00000008) +#define MCF_ETPU_ECDTRSR_DTRS4 (0x00000010) +#define MCF_ETPU_ECDTRSR_DTRS5 (0x00000020) +#define MCF_ETPU_ECDTRSR_DTRS6 (0x00000040) +#define MCF_ETPU_ECDTRSR_DTRS7 (0x00000080) +#define MCF_ETPU_ECDTRSR_DTRS8 (0x00000100) +#define MCF_ETPU_ECDTRSR_DTRS9 (0x00000200) +#define MCF_ETPU_ECDTRSR_DTRS10 (0x00000400) +#define MCF_ETPU_ECDTRSR_DTRS11 (0x00000800) +#define MCF_ETPU_ECDTRSR_DTRS12 (0x00001000) +#define MCF_ETPU_ECDTRSR_DTRS13 (0x00002000) +#define MCF_ETPU_ECDTRSR_DTRS14 (0x00004000) +#define MCF_ETPU_ECDTRSR_DTRS15 (0x00008000) +#define MCF_ETPU_ECDTRSR_DTRS16 (0x00010000) +#define MCF_ETPU_ECDTRSR_DTRS17 (0x00020000) +#define MCF_ETPU_ECDTRSR_DTRS18 (0x00040000) +#define MCF_ETPU_ECDTRSR_DTRS19 (0x00080000) +#define MCF_ETPU_ECDTRSR_DTRS20 (0x00100000) +#define MCF_ETPU_ECDTRSR_DTRS21 (0x00200000) +#define MCF_ETPU_ECDTRSR_DTRS22 (0x00400000) +#define MCF_ETPU_ECDTRSR_DTRS23 (0x00800000) +#define MCF_ETPU_ECDTRSR_DTRS24 (0x01000000) +#define MCF_ETPU_ECDTRSR_DTRS25 (0x02000000) +#define MCF_ETPU_ECDTRSR_DTRS26 (0x04000000) +#define MCF_ETPU_ECDTRSR_DTRS27 (0x08000000) +#define MCF_ETPU_ECDTRSR_DTRS28 (0x10000000) +#define MCF_ETPU_ECDTRSR_DTRS29 (0x20000000) +#define MCF_ETPU_ECDTRSR_DTRS30 (0x40000000) +#define MCF_ETPU_ECDTRSR_DTRS31 (0x80000000) + +/* Bit definitions and macros for MCF_ETPU_ECIOSR */ +#define MCF_ETPU_ECIOSR_CIOS0 (0x00000001) +#define MCF_ETPU_ECIOSR_CIOS1 (0x00000002) +#define MCF_ETPU_ECIOSR_CIOS2 (0x00000004) +#define MCF_ETPU_ECIOSR_CIOS3 (0x00000008) +#define MCF_ETPU_ECIOSR_CIOS4 (0x00000010) +#define MCF_ETPU_ECIOSR_CIOS5 (0x00000020) +#define MCF_ETPU_ECIOSR_CIOS6 (0x00000040) +#define MCF_ETPU_ECIOSR_CIOS7 (0x00000080) +#define MCF_ETPU_ECIOSR_CIOS8 (0x00000100) +#define MCF_ETPU_ECIOSR_CIOS9 (0x00000200) +#define MCF_ETPU_ECIOSR_CIOS10 (0x00000400) +#define MCF_ETPU_ECIOSR_CIOS11 (0x00000800) +#define MCF_ETPU_ECIOSR_CIOS12 (0x00001000) +#define MCF_ETPU_ECIOSR_CIOS13 (0x00002000) +#define MCF_ETPU_ECIOSR_CIOS14 (0x00004000) +#define MCF_ETPU_ECIOSR_CIOS15 (0x00008000) +#define MCF_ETPU_ECIOSR_CIOS16 (0x00010000) +#define MCF_ETPU_ECIOSR_CIOS17 (0x00020000) +#define MCF_ETPU_ECIOSR_CIOS18 (0x00040000) +#define MCF_ETPU_ECIOSR_CIOS19 (0x00080000) +#define MCF_ETPU_ECIOSR_CIOS20 (0x00100000) +#define MCF_ETPU_ECIOSR_CIOS21 (0x00200000) +#define MCF_ETPU_ECIOSR_CIOS22 (0x00400000) +#define MCF_ETPU_ECIOSR_CIOS23 (0x00800000) +#define MCF_ETPU_ECIOSR_CIOS24 (0x01000000) +#define MCF_ETPU_ECIOSR_CIOS25 (0x02000000) +#define MCF_ETPU_ECIOSR_CIOS26 (0x04000000) +#define MCF_ETPU_ECIOSR_CIOS27 (0x08000000) +#define MCF_ETPU_ECIOSR_CIOS28 (0x10000000) +#define MCF_ETPU_ECIOSR_CIOS29 (0x20000000) +#define MCF_ETPU_ECIOSR_CIOS30 (0x40000000) +#define MCF_ETPU_ECIOSR_CIOS31 (0x80000000) + +/* Bit definitions and macros for MCF_ETPU_ECDTROSR */ +#define MCF_ETPU_ECDTROSR_DTROS0 (0x00000001) +#define MCF_ETPU_ECDTROSR_DTROS1 (0x00000002) +#define MCF_ETPU_ECDTROSR_DTROS2 (0x00000004) +#define MCF_ETPU_ECDTROSR_DTROS3 (0x00000008) +#define MCF_ETPU_ECDTROSR_DTROS4 (0x00000010) +#define MCF_ETPU_ECDTROSR_DTROS5 (0x00000020) +#define MCF_ETPU_ECDTROSR_DTROS6 (0x00000040) +#define MCF_ETPU_ECDTROSR_DTROS7 (0x00000080) +#define MCF_ETPU_ECDTROSR_DTROS8 (0x00000100) +#define MCF_ETPU_ECDTROSR_DTROS9 (0x00000200) +#define MCF_ETPU_ECDTROSR_DTROS10 (0x00000400) +#define MCF_ETPU_ECDTROSR_DTROS11 (0x00000800) +#define MCF_ETPU_ECDTROSR_DTROS12 (0x00001000) +#define MCF_ETPU_ECDTROSR_DTROS13 (0x00002000) +#define MCF_ETPU_ECDTROSR_DTROS14 (0x00004000) +#define MCF_ETPU_ECDTROSR_DTROS15 (0x00008000) +#define MCF_ETPU_ECDTROSR_DTROS16 (0x00010000) +#define MCF_ETPU_ECDTROSR_DTROS17 (0x00020000) +#define MCF_ETPU_ECDTROSR_DTROS18 (0x00040000) +#define MCF_ETPU_ECDTROSR_DTROS19 (0x00080000) +#define MCF_ETPU_ECDTROSR_DTROS20 (0x00100000) +#define MCF_ETPU_ECDTROSR_DTROS21 (0x00200000) +#define MCF_ETPU_ECDTROSR_DTROS22 (0x00400000) +#define MCF_ETPU_ECDTROSR_DTROS23 (0x00800000) +#define MCF_ETPU_ECDTROSR_DTROS24 (0x01000000) +#define MCF_ETPU_ECDTROSR_DTROS25 (0x02000000) +#define MCF_ETPU_ECDTROSR_DTROS26 (0x04000000) +#define MCF_ETPU_ECDTROSR_DTROS27 (0x08000000) +#define MCF_ETPU_ECDTROSR_DTROS28 (0x10000000) +#define MCF_ETPU_ECDTROSR_DTROS29 (0x20000000) +#define MCF_ETPU_ECDTROSR_DTROS30 (0x40000000) +#define MCF_ETPU_ECDTROSR_DTROS31 (0x80000000) + +/* Bit definitions and macros for MCF_ETPU_ECIER */ +#define MCF_ETPU_ECIER_CIE0 (0x00000001) +#define MCF_ETPU_ECIER_CIE1 (0x00000002) +#define MCF_ETPU_ECIER_CIE2 (0x00000004) +#define MCF_ETPU_ECIER_CIE3 (0x00000008) +#define MCF_ETPU_ECIER_CIE4 (0x00000010) +#define MCF_ETPU_ECIER_CIE5 (0x00000020) +#define MCF_ETPU_ECIER_CIE6 (0x00000040) +#define MCF_ETPU_ECIER_CIE7 (0x00000080) +#define MCF_ETPU_ECIER_CIE8 (0x00000100) +#define MCF_ETPU_ECIER_CIE9 (0x00000200) +#define MCF_ETPU_ECIER_CIE10 (0x00000400) +#define MCF_ETPU_ECIER_CIE11 (0x00000800) +#define MCF_ETPU_ECIER_CIE12 (0x00001000) +#define MCF_ETPU_ECIER_CIE13 (0x00002000) +#define MCF_ETPU_ECIER_CIE14 (0x00004000) +#define MCF_ETPU_ECIER_CIE15 (0x00008000) +#define MCF_ETPU_ECIER_CIE16 (0x00010000) +#define MCF_ETPU_ECIER_CIE17 (0x00020000) +#define MCF_ETPU_ECIER_CIE18 (0x00040000) +#define MCF_ETPU_ECIER_CIE19 (0x00080000) +#define MCF_ETPU_ECIER_CIE20 (0x00100000) +#define MCF_ETPU_ECIER_CIE21 (0x00200000) +#define MCF_ETPU_ECIER_CIE22 (0x00400000) +#define MCF_ETPU_ECIER_CIE23 (0x00800000) +#define MCF_ETPU_ECIER_CIE24 (0x01000000) +#define MCF_ETPU_ECIER_CIE25 (0x02000000) +#define MCF_ETPU_ECIER_CIE26 (0x04000000) +#define MCF_ETPU_ECIER_CIE27 (0x08000000) +#define MCF_ETPU_ECIER_CIE28 (0x10000000) +#define MCF_ETPU_ECIER_CIE29 (0x20000000) +#define MCF_ETPU_ECIER_CIE30 (0x40000000) +#define MCF_ETPU_ECIER_CIE31 (0x80000000) + +/* Bit definitions and macros for MCF_ETPU_ECDTRER */ +#define MCF_ETPU_ECDTRER_DTRE0 (0x00000001) +#define MCF_ETPU_ECDTRER_DTRE1 (0x00000002) +#define MCF_ETPU_ECDTRER_DTRE2 (0x00000004) +#define MCF_ETPU_ECDTRER_DTRE3 (0x00000008) +#define MCF_ETPU_ECDTRER_DTRE4 (0x00000010) +#define MCF_ETPU_ECDTRER_DTRE5 (0x00000020) +#define MCF_ETPU_ECDTRER_DTRE6 (0x00000040) +#define MCF_ETPU_ECDTRER_DTRE7 (0x00000080) +#define MCF_ETPU_ECDTRER_DTRE8 (0x00000100) +#define MCF_ETPU_ECDTRER_DTRE9 (0x00000200) +#define MCF_ETPU_ECDTRER_DTRE10 (0x00000400) +#define MCF_ETPU_ECDTRER_DTRE11 (0x00000800) +#define MCF_ETPU_ECDTRER_DTRE12 (0x00001000) +#define MCF_ETPU_ECDTRER_DTRE13 (0x00002000) +#define MCF_ETPU_ECDTRER_DTRE14 (0x00004000) +#define MCF_ETPU_ECDTRER_DTRE15 (0x00008000) +#define MCF_ETPU_ECDTRER_DTRE16 (0x00010000) +#define MCF_ETPU_ECDTRER_DTRE17 (0x00020000) +#define MCF_ETPU_ECDTRER_DTRE18 (0x00040000) +#define MCF_ETPU_ECDTRER_DTRE19 (0x00080000) +#define MCF_ETPU_ECDTRER_DTRE20 (0x00100000) +#define MCF_ETPU_ECDTRER_DTRE21 (0x00200000) +#define MCF_ETPU_ECDTRER_DTRE22 (0x00400000) +#define MCF_ETPU_ECDTRER_DTRE23 (0x00800000) +#define MCF_ETPU_ECDTRER_DTRE24 (0x01000000) +#define MCF_ETPU_ECDTRER_DTRE25 (0x02000000) +#define MCF_ETPU_ECDTRER_DTRE26 (0x04000000) +#define MCF_ETPU_ECDTRER_DTRE27 (0x08000000) +#define MCF_ETPU_ECDTRER_DTRE28 (0x10000000) +#define MCF_ETPU_ECDTRER_DTRE29 (0x20000000) +#define MCF_ETPU_ECDTRER_DTRE30 (0x40000000) +#define MCF_ETPU_ECDTRER_DTRE31 (0x80000000) + +/* Bit definitions and macros for MCF_ETPU_ECPSSR */ +#define MCF_ETPU_ECPSSR_SR0 (0x00000001) +#define MCF_ETPU_ECPSSR_SR1 (0x00000002) +#define MCF_ETPU_ECPSSR_SR2 (0x00000004) +#define MCF_ETPU_ECPSSR_SR3 (0x00000008) +#define MCF_ETPU_ECPSSR_SR4 (0x00000010) +#define MCF_ETPU_ECPSSR_SR5 (0x00000020) +#define MCF_ETPU_ECPSSR_SR6 (0x00000040) +#define MCF_ETPU_ECPSSR_SR7 (0x00000080) +#define MCF_ETPU_ECPSSR_SR8 (0x00000100) +#define MCF_ETPU_ECPSSR_SR9 (0x00000200) +#define MCF_ETPU_ECPSSR_SR10 (0x00000400) +#define MCF_ETPU_ECPSSR_SR11 (0x00000800) +#define MCF_ETPU_ECPSSR_SR12 (0x00001000) +#define MCF_ETPU_ECPSSR_SR13 (0x00002000) +#define MCF_ETPU_ECPSSR_SR14 (0x00004000) +#define MCF_ETPU_ECPSSR_SR15 (0x00008000) +#define MCF_ETPU_ECPSSR_SR16 (0x00010000) +#define MCF_ETPU_ECPSSR_SR17 (0x00020000) +#define MCF_ETPU_ECPSSR_SR18 (0x00040000) +#define MCF_ETPU_ECPSSR_SR19 (0x00080000) +#define MCF_ETPU_ECPSSR_SR20 (0x00100000) +#define MCF_ETPU_ECPSSR_SR21 (0x00200000) +#define MCF_ETPU_ECPSSR_SR22 (0x00400000) +#define MCF_ETPU_ECPSSR_SR23 (0x00800000) +#define MCF_ETPU_ECPSSR_SR24 (0x01000000) +#define MCF_ETPU_ECPSSR_SR25 (0x02000000) +#define MCF_ETPU_ECPSSR_SR26 (0x04000000) +#define MCF_ETPU_ECPSSR_SR27 (0x08000000) +#define MCF_ETPU_ECPSSR_SR28 (0x10000000) +#define MCF_ETPU_ECPSSR_SR29 (0x20000000) +#define MCF_ETPU_ECPSSR_SR30 (0x40000000) +#define MCF_ETPU_ECPSSR_SR31 (0x80000000) + +/* Bit definitions and macros for MCF_ETPU_ECSSR */ +#define MCF_ETPU_ECSSR_SS0 (0x00000001) +#define MCF_ETPU_ECSSR_SS1 (0x00000002) +#define MCF_ETPU_ECSSR_SS2 (0x00000004) +#define MCF_ETPU_ECSSR_SS3 (0x00000008) +#define MCF_ETPU_ECSSR_SS4 (0x00000010) +#define MCF_ETPU_ECSSR_SS5 (0x00000020) +#define MCF_ETPU_ECSSR_SS6 (0x00000040) +#define MCF_ETPU_ECSSR_SS7 (0x00000080) +#define MCF_ETPU_ECSSR_SS8 (0x00000100) +#define MCF_ETPU_ECSSR_SS9 (0x00000200) +#define MCF_ETPU_ECSSR_SS10 (0x00000400) +#define MCF_ETPU_ECSSR_SS11 (0x00000800) +#define MCF_ETPU_ECSSR_SS12 (0x00001000) +#define MCF_ETPU_ECSSR_SS13 (0x00002000) +#define MCF_ETPU_ECSSR_SS14 (0x00004000) +#define MCF_ETPU_ECSSR_SS15 (0x00008000) +#define MCF_ETPU_ECSSR_SS16 (0x00010000) +#define MCF_ETPU_ECSSR_SS17 (0x00020000) +#define MCF_ETPU_ECSSR_SS18 (0x00040000) +#define MCF_ETPU_ECSSR_SS19 (0x00080000) +#define MCF_ETPU_ECSSR_SS20 (0x00100000) +#define MCF_ETPU_ECSSR_SS21 (0x00200000) +#define MCF_ETPU_ECSSR_SS22 (0x00400000) +#define MCF_ETPU_ECSSR_SS23 (0x00800000) +#define MCF_ETPU_ECSSR_SS24 (0x01000000) +#define MCF_ETPU_ECSSR_SS25 (0x02000000) +#define MCF_ETPU_ECSSR_SS26 (0x04000000) +#define MCF_ETPU_ECSSR_SS27 (0x08000000) +#define MCF_ETPU_ECSSR_SS28 (0x10000000) +#define MCF_ETPU_ECSSR_SS29 (0x20000000) +#define MCF_ETPU_ECSSR_SS30 (0x40000000) +#define MCF_ETPU_ECSSR_SS31 (0x80000000) + +/* Bit definitions and macros for MCF_ETPU_ECnSCR */ +#define MCF_ETPU_ECnSCR_FM(x) (((x)&0x00000003)<<0) +#define MCF_ETPU_ECnSCR_OBE (0x00002000) +#define MCF_ETPU_ECnSCR_OPS (0x00004000) +#define MCF_ETPU_ECnSCR_IPS (0x00008000) +#define MCF_ETPU_ECnSCR_DTROS (0x00400000) +#define MCF_ETPU_ECnSCR_DTRS (0x00800000) +#define MCF_ETPU_ECnSCR_CIOS (0x40000000) +#define MCF_ETPU_ECnSCR_CIS (0x80000000) + +/* Bit definitions and macros for MCF_ETPU_ECnCR */ +#define MCF_ETPU_ECnCR_CPBA(x) (((x)&0x000007FF)<<0) +#define MCF_ETPU_ECnCR_OPOL (0x00004000) +#define MCF_ETPU_ECnCR_ODIS (0x00008000) +#define MCF_ETPU_ECnCR_CFS(x) (((x)&0x0000001F)<<16) +#define MCF_ETPU_ECnCR_ETCS (0x01000000) +#define MCF_ETPU_ECnCR_CPR(x) (((x)&0x00000003)<<28) +#define MCF_ETPU_ECnCR_DTRE (0x40000000) +#define MCF_ETPU_ECnCR_CIE (0x80000000) + +/* Bit definitions and macros for MCF_ETPU_ECnHSSR */ +#define MCF_ETPU_ECnHSSR_HSR(x) (((x)&0x00000007)<<0) + +/********************************************************************/ + +#endif /* __MCF523X_ETPU_H__ */ diff --git a/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_fec.h b/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_fec.h new file mode 100644 index 000000000..a4a209d50 --- /dev/null +++ b/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_fec.h @@ -0,0 +1,208 @@ +/* + * These files are taken from the MCF523X source code example package + * which is available on the Freescale website. Freescale explicitly + * grants the redistribution and modification of these source files. + * The complete licensing information is available in the file + * LICENSE_FREESCALE.TXT. + * + * File: mcf523x_fec.h + * Purpose: Register and bit definitions for the MCF523X + * + * Notes: + * + */ + +#ifndef __MCF523X_FEC_H__ +#define __MCF523X_FEC_H__ + +/********************************************************************* +* +* Fast Ethernet Controller (FEC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_FEC_EIR (*(vuint32*)(void*)(&__IPSBAR[0x001004])) +#define MCF_FEC_EIMR (*(vuint32*)(void*)(&__IPSBAR[0x001008])) +#define MCF_FEC_RDAR (*(vuint32*)(void*)(&__IPSBAR[0x001010])) +#define MCF_FEC_TDAR (*(vuint32*)(void*)(&__IPSBAR[0x001014])) +#define MCF_FEC_ECR (*(vuint32*)(void*)(&__IPSBAR[0x001024])) +#define MCF_FEC_MMFR (*(vuint32*)(void*)(&__IPSBAR[0x001040])) +#define MCF_FEC_MSCR (*(vuint32*)(void*)(&__IPSBAR[0x001044])) +#define MCF_FEC_MIBC (*(vuint32*)(void*)(&__IPSBAR[0x001064])) +#define MCF_FEC_RCR (*(vuint32*)(void*)(&__IPSBAR[0x001084])) +#define MCF_FEC_TCR (*(vuint32*)(void*)(&__IPSBAR[0x0010C4])) +#define MCF_FEC_PALR (*(vuint32*)(void*)(&__IPSBAR[0x0010E4])) +#define MCF_FEC_PAUR (*(vuint32*)(void*)(&__IPSBAR[0x0010E8])) +#define MCF_FEC_OPD (*(vuint32*)(void*)(&__IPSBAR[0x0010EC])) +#define MCF_FEC_IAUR (*(vuint32*)(void*)(&__IPSBAR[0x001118])) +#define MCF_FEC_IALR (*(vuint32*)(void*)(&__IPSBAR[0x00111C])) +#define MCF_FEC_GAUR (*(vuint32*)(void*)(&__IPSBAR[0x001120])) +#define MCF_FEC_GALR (*(vuint32*)(void*)(&__IPSBAR[0x001124])) +#define MCF_FEC_TFWR (*(vuint32*)(void*)(&__IPSBAR[0x001144])) +#define MCF_FEC_FRBR (*(vuint32*)(void*)(&__IPSBAR[0x00114C])) +#define MCF_FEC_FRSR (*(vuint32*)(void*)(&__IPSBAR[0x001150])) +#define MCF_FEC_ERDSR (*(vuint32*)(void*)(&__IPSBAR[0x001180])) +#define MCF_FEC_ETDSR (*(vuint32*)(void*)(&__IPSBAR[0x001184])) +#define MCF_FEC_EMRBR (*(vuint32*)(void*)(&__IPSBAR[0x001188])) +#define MCF_FEC_RMON_T_DROP (*(vuint32*)(void*)(&__IPSBAR[0x001200])) +#define MCF_FEC_RMON_T_PACKETS (*(vuint32*)(void*)(&__IPSBAR[0x001204])) +#define MCF_FEC_RMON_T_BC_PKT (*(vuint32*)(void*)(&__IPSBAR[0x001208])) +#define MCF_FEC_RMON_T_MC_PKT (*(vuint32*)(void*)(&__IPSBAR[0x00120C])) +#define MCF_FEC_RMON_T_CRC_ALIGN (*(vuint32*)(void*)(&__IPSBAR[0x001210])) +#define MCF_FEC_RMON_T_UNDERSIZE (*(vuint32*)(void*)(&__IPSBAR[0x001214])) +#define MCF_FEC_RMON_T_OVERSIZE (*(vuint32*)(void*)(&__IPSBAR[0x001218])) +#define MCF_FEC_RMON_T_FRAG (*(vuint32*)(void*)(&__IPSBAR[0x00121C])) +#define MCF_FEC_RMON_T_JAB (*(vuint32*)(void*)(&__IPSBAR[0x001220])) +#define MCF_FEC_RMON_T_COL (*(vuint32*)(void*)(&__IPSBAR[0x001224])) +#define MCF_FEC_RMON_T_P64 (*(vuint32*)(void*)(&__IPSBAR[0x001228])) +#define MCF_FEC_RMON_T_P65TO127 (*(vuint32*)(void*)(&__IPSBAR[0x00122C])) +#define MCF_FEC_RMON_T_P128TO255 (*(vuint32*)(void*)(&__IPSBAR[0x001230])) +#define MCF_FEC_RMON_T_P256TO511 (*(vuint32*)(void*)(&__IPSBAR[0x001234])) +#define MCF_FEC_RMON_T_P512TO1023 (*(vuint32*)(void*)(&__IPSBAR[0x001238])) +#define MCF_FEC_RMON_T_P1024TO2047 (*(vuint32*)(void*)(&__IPSBAR[0x00123C])) +#define MCF_FEC_RMON_T_P_GTE2048 (*(vuint32*)(void*)(&__IPSBAR[0x001240])) +#define MCF_FEC_RMON_T_OCTETS (*(vuint32*)(void*)(&__IPSBAR[0x001244])) +#define MCF_FEC_IEEE_T_DROP (*(vuint32*)(void*)(&__IPSBAR[0x001248])) +#define MCF_FEC_IEEE_T_FRAME_OK (*(vuint32*)(void*)(&__IPSBAR[0x00124C])) +#define MCF_FEC_IEEE_T_1COL (*(vuint32*)(void*)(&__IPSBAR[0x001250])) +#define MCF_FEC_IEEE_T_MCOL (*(vuint32*)(void*)(&__IPSBAR[0x001254])) +#define MCF_FEC_IEEE_T_DEF (*(vuint32*)(void*)(&__IPSBAR[0x001258])) +#define MCF_FEC_IEEE_T_LCOL (*(vuint32*)(void*)(&__IPSBAR[0x00125C])) +#define MCF_FEC_IEEE_T_EXCOL (*(vuint32*)(void*)(&__IPSBAR[0x001260])) +#define MCF_FEC_IEEE_T_MACERR (*(vuint32*)(void*)(&__IPSBAR[0x001264])) +#define MCF_FEC_IEEE_T_CSERR (*(vuint32*)(void*)(&__IPSBAR[0x001268])) +#define MCF_FEC_IEEE_T_SQE (*(vuint32*)(void*)(&__IPSBAR[0x00126C])) +#define MCF_FEC_IEEE_T_FDXFC (*(vuint32*)(void*)(&__IPSBAR[0x001270])) +#define MCF_FEC_IEEE_T_OCTETS_OK (*(vuint32*)(void*)(&__IPSBAR[0x001274])) +#define MCF_FEC_RMON_R_PACKETS (*(vuint32*)(void*)(&__IPSBAR[0x001284])) +#define MCF_FEC_RMON_R_BC_PKT (*(vuint32*)(void*)(&__IPSBAR[0x001288])) +#define MCF_FEC_RMON_R_MC_PKT (*(vuint32*)(void*)(&__IPSBAR[0x00128C])) +#define MCF_FEC_RMON_R_CRC_ALIGN (*(vuint32*)(void*)(&__IPSBAR[0x001290])) +#define MCF_FEC_RMON_R_UNDERSIZE (*(vuint32*)(void*)(&__IPSBAR[0x001294])) +#define MCF_FEC_RMON_R_OVERSIZE (*(vuint32*)(void*)(&__IPSBAR[0x001298])) +#define MCF_FEC_RMON_R_FRAG (*(vuint32*)(void*)(&__IPSBAR[0x00129C])) +#define MCF_FEC_RMON_R_JAB (*(vuint32*)(void*)(&__IPSBAR[0x0012A0])) +#define MCF_FEC_RMON_R_RESVD_0 (*(vuint32*)(void*)(&__IPSBAR[0x0012A4])) +#define MCF_FEC_RMON_R_P64 (*(vuint32*)(void*)(&__IPSBAR[0x0012A8])) +#define MCF_FEC_RMON_R_P65TO127 (*(vuint32*)(void*)(&__IPSBAR[0x0012AC])) +#define MCF_FEC_RMON_R_P128TO255 (*(vuint32*)(void*)(&__IPSBAR[0x0012B0])) +#define MCF_FEC_RMON_R_P256TO511 (*(vuint32*)(void*)(&__IPSBAR[0x0012B4])) +#define MCF_FEC_RMON_R_512TO1023 (*(vuint32*)(void*)(&__IPSBAR[0x0012B8])) +#define MCF_FEC_RMON_R_P_GTE2048 (*(vuint32*)(void*)(&__IPSBAR[0x0012C0])) +#define MCF_FEC_RMON_R_1024TO2047 (*(vuint32*)(void*)(&__IPSBAR[0x0012BC])) +#define MCF_FEC_RMON_R_OCTETS (*(vuint32*)(void*)(&__IPSBAR[0x0012C4])) +#define MCF_FEC_IEEE_R_DROP (*(vuint32*)(void*)(&__IPSBAR[0x0012C8])) +#define MCF_FEC_IEEE_R_FRAME_OK (*(vuint32*)(void*)(&__IPSBAR[0x0012CC])) +#define MCF_FEC_IEEE_R_CRC (*(vuint32*)(void*)(&__IPSBAR[0x0012D0])) +#define MCF_FEC_IEEE_R_ALIGN (*(vuint32*)(void*)(&__IPSBAR[0x0012D4])) +#define MCF_FEC_IEEE_R_MACERR (*(vuint32*)(void*)(&__IPSBAR[0x0012D8])) +#define MCF_FEC_IEEE_R_FDXFC (*(vuint32*)(void*)(&__IPSBAR[0x0012DC])) +#define MCF_FEC_IEEE_R_OCTETS_OK (*(vuint32*)(void*)(&__IPSBAR[0x0012E0])) + +/* Bit definitions and macros for MCF_FEC_EIR */ +#define MCF_FEC_EIR_UN (0x00080000) +#define MCF_FEC_EIR_RL (0x00100000) +#define MCF_FEC_EIR_LC (0x00200000) +#define MCF_FEC_EIR_EBERR (0x00400000) +#define MCF_FEC_EIR_MII (0x00800000) +#define MCF_FEC_EIR_RXB (0x01000000) +#define MCF_FEC_EIR_RXF (0x02000000) +#define MCF_FEC_EIR_TXB (0x04000000) +#define MCF_FEC_EIR_TXF (0x08000000) +#define MCF_FEC_EIR_GRA (0x10000000) +#define MCF_FEC_EIR_BABT (0x20000000) +#define MCF_FEC_EIR_BABR (0x40000000) +#define MCF_FEC_EIR_HBERR (0x80000000) + +/* Bit definitions and macros for MCF_FEC_EIMR */ +#define MCF_FEC_EIMR_UN (0x00080000) +#define MCF_FEC_EIMR_RL (0x00100000) +#define MCF_FEC_EIMR_LC (0x00200000) +#define MCF_FEC_EIMR_EBERR (0x00400000) +#define MCF_FEC_EIMR_MII (0x00800000) +#define MCF_FEC_EIMR_RXB (0x01000000) +#define MCF_FEC_EIMR_RXF (0x02000000) +#define MCF_FEC_EIMR_TXB (0x04000000) +#define MCF_FEC_EIMR_TXF (0x08000000) +#define MCF_FEC_EIMR_GRA (0x10000000) +#define MCF_FEC_EIMR_BABT (0x20000000) +#define MCF_FEC_EIMR_BABR (0x40000000) +#define MCF_FEC_EIMR_HBERR (0x80000000) + +/* Bit definitions and macros for MCF_FEC_RDAR */ +#define MCF_FEC_RDAR_R_DES_ACTIVE (0x01000000) + +/* Bit definitions and macros for MCF_FEC_TDAR */ +#define MCF_FEC_TDAR_X_DES_ACTIVE (0x01000000) + +/* Bit definitions and macros for MCF_FEC_ECR */ +#define MCF_FEC_ECR_RESET (0x00000001) +#define MCF_FEC_ECR_ETHER_EN (0x00000002) + +/* Bit definitions and macros for MCF_FEC_MMFR */ +#define MCF_FEC_MMFR_DATA(x) (((x)&0x0000FFFF)<<0) +#define MCF_FEC_MMFR_TA(x) (((x)&0x00000003)<<16) +#define MCF_FEC_MMFR_RA(x) (((x)&0x0000001F)<<18) +#define MCF_FEC_MMFR_PA(x) (((x)&0x0000001F)<<23) +#define MCF_FEC_MMFR_OP(x) (((x)&0x00000003)<<28) +#define MCF_FEC_MMFR_ST(x) (((x)&0x00000003)<<30) +#define MCF_FEC_MMFR_ST_01 (0x40000000) +#define MCF_FEC_MMFR_OP_READ (0x20000000) +#define MCF_FEC_MMFR_OP_WRITE (0x10000000) +#define MCF_FEC_MMFR_TA_10 (0x00020000) + + +/* Bit definitions and macros for MCF_FEC_MSCR */ +#define MCF_FEC_MSCR_MII_SPEED(x) (((x)&0x0000003F)<<1) +#define MCF_FEC_MSCR_DIS_PREAMBLE (0x00000080) + +/* Bit definitions and macros for MCF_FEC_MIBC */ +#define MCF_FEC_MIBC_MIB_IDLE (0x40000000) +#define MCF_FEC_MIBC_MIB_DISABLE (0x80000000) + +/* Bit definitions and macros for MCF_FEC_RCR */ +#define MCF_FEC_RCR_LOOP (0x00000001) +#define MCF_FEC_RCR_DRT (0x00000002) +#define MCF_FEC_RCR_MII_MODE (0x00000004) +#define MCF_FEC_RCR_PROM (0x00000008) +#define MCF_FEC_RCR_BC_REJ (0x00000010) +#define MCF_FEC_RCR_FCE (0x00000020) +#define MCF_FEC_RCR_MAX_FL(x) (((x)&0x000007FF)<<16) + +/* Bit definitions and macros for MCF_FEC_TCR */ +#define MCF_FEC_TCR_GTS (0x00000001) +#define MCF_FEC_TCR_HBC (0x00000002) +#define MCF_FEC_TCR_FDEN (0x00000004) +#define MCF_FEC_TCR_TFC_PAUSE (0x00000008) +#define MCF_FEC_TCR_RFC_PAUSE (0x00000010) + +/* Bit definitions and macros for MCF_FEC_PAUR */ +#define MCF_FEC_PAUR_TYPE(x) (((x)&0x0000FFFF)<<0) +#define MCF_FEC_PAUR_PADDR2(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for MCF_FEC_OPD */ +#define MCF_FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0) +#define MCF_FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for MCF_FEC_TFWR */ +#define MCF_FEC_TFWR_X_WMRK(x) (((x)&0x00000003)<<0) + +/* Bit definitions and macros for MCF_FEC_FRBR */ +#define MCF_FEC_FRBR_R_BOUND(x) (((x)&0x000000FF)<<2) + +/* Bit definitions and macros for MCF_FEC_FRSR */ +#define MCF_FEC_FRSR_R_FSTART(x) (((x)&0x000000FF)<<2) + +/* Bit definitions and macros for MCF_FEC_ERDSR */ +#define MCF_FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<2) + +/* Bit definitions and macros for MCF_FEC_ETDSR */ +#define MCF_FEC_ETDSR_X_DES_START(x) (((x)&0x3FFFFFFF)<<2) + +/* Bit definitions and macros for MCF_FEC_EMRBR */ +#define MCF_FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x0000007F)<<4) + +/********************************************************************/ + +#endif /* __MCF523X_FEC_H__ */ diff --git a/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_fmpll.h b/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_fmpll.h new file mode 100644 index 000000000..3f132e896 --- /dev/null +++ b/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_fmpll.h @@ -0,0 +1,55 @@ +/* + * These files are taken from the MCF523X source code example package + * which is available on the Freescale website. Freescale explicitly + * grants the redistribution and modification of these source files. + * The complete licensing information is available in the file + * LICENSE_FREESCALE.TXT. + * + * File: mcf523x_fmpll.h + * Purpose: Register and bit definitions for the MCF523X + * + * Notes: + * + */ + +#ifndef __MCF523X_FMPLL_H__ +#define __MCF523X_FMPLL_H__ + +/********************************************************************* +* +* Frequency Modulated Phase Locked Loop (FMPLL) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_FMPLL_SYNCR (*(vuint32*)(void*)(&__IPSBAR[0x120000])) +#define MCF_FMPLL_SYNSR (*(vuint32*)(void*)(&__IPSBAR[0x120004])) + +/* Bit definitions and macros for MCF_FMPLL_SYNCR */ +#define MCF_FMPLL_SYNCR_EXP(x) (((x)&0x000003FF)<<0) +#define MCF_FMPLL_SYNCR_DEPTH(x) (((x)&0x00000003)<<10) +#define MCF_FMPLL_SYNCR_RATE (0x00001000) +#define MCF_FMPLL_SYNCR_LOCIRQ (0x00002000) +#define MCF_FMPLL_SYNCR_LOLIRQ (0x00004000) +#define MCF_FMPLL_SYNCR_DISCLK (0x00008000) +#define MCF_FMPLL_SYNCR_LOCRE (0x00010000) +#define MCF_FMPLL_SYNCR_LOLRE (0x00020000) +#define MCF_FMPLL_SYNCR_LOCEN (0x00040000) +#define MCF_FMPLL_SYNCR_RFD(x) (((x)&0x00000007)<<19) +#define MCF_FMPLL_SYNCR_MFD(x) (((x)&0x00000007)<<24) + +/* Bit definitions and macros for MCF_FMPLL_SYNSR */ +#define MCF_FMPLL_SYNSR_CALPASS (0x00000001) +#define MCF_FMPLL_SYNSR_CALDONE (0x00000002) +#define MCF_FMPLL_SYNSR_LOCF (0x00000004) +#define MCF_FMPLL_SYNSR_LOCK (0x00000008) +#define MCF_FMPLL_SYNSR_LOCKS (0x00000010) +#define MCF_FMPLL_SYNSR_PLLREF (0x00000020) +#define MCF_FMPLL_SYNSR_PLLSEL (0x00000040) +#define MCF_FMPLL_SYNSR_MODE (0x00000080) +#define MCF_FMPLL_SYNSR_LOC (0x00000100) +#define MCF_FMPLL_SYNSR_LOLF (0x00000200) + +/********************************************************************/ + +#endif /* __MCF523X_FMPLL_H__ */ diff --git a/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_gpio.h b/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_gpio.h new file mode 100644 index 000000000..df8c36600 --- /dev/null +++ b/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_gpio.h @@ -0,0 +1,676 @@ +/* + * These files are taken from the MCF523X source code example package + * which is available on the Freescale website. Freescale explicitly + * grants the redistribution and modification of these source files. + * The complete licensing information is available in the file + * LICENSE_FREESCALE.TXT. + * + * File: mcf523x_gpio.h + * Purpose: Register and bit definitions for the MCF523X + * + * Notes: + * + */ + +#ifndef __MCF523X_GPIO_H__ +#define __MCF523X_GPIO_H__ + +/********************************************************************* +* +* General Purpose I/O (GPIO) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_GPIO_PODR_ADDR (*(vuint8 *)(void*)(&__IPSBAR[0x100000])) +#define MCF_GPIO_PODR_DATAH (*(vuint8 *)(void*)(&__IPSBAR[0x100001])) +#define MCF_GPIO_PODR_DATAL (*(vuint8 *)(void*)(&__IPSBAR[0x100002])) +#define MCF_GPIO_PODR_BUSCTL (*(vuint8 *)(void*)(&__IPSBAR[0x100003])) +#define MCF_GPIO_PODR_BS (*(vuint8 *)(void*)(&__IPSBAR[0x100004])) +#define MCF_GPIO_PODR_CS (*(vuint8 *)(void*)(&__IPSBAR[0x100005])) +#define MCF_GPIO_PODR_SDRAM (*(vuint8 *)(void*)(&__IPSBAR[0x100006])) +#define MCF_GPIO_PODR_FECI2C (*(vuint8 *)(void*)(&__IPSBAR[0x100007])) +#define MCF_GPIO_PODR_UARTH (*(vuint8 *)(void*)(&__IPSBAR[0x100008])) +#define MCF_GPIO_PODR_UARTL (*(vuint8 *)(void*)(&__IPSBAR[0x100009])) +#define MCF_GPIO_PODR_QSPI (*(vuint8 *)(void*)(&__IPSBAR[0x10000A])) +#define MCF_GPIO_PODR_TIMER (*(vuint8 *)(void*)(&__IPSBAR[0x10000B])) +#define MCF_GPIO_PODR_ETPU (*(vuint8 *)(void*)(&__IPSBAR[0x10000C])) +#define MCF_GPIO_PDDR_APDDR (*(vuint8 *)(void*)(&__IPSBAR[0x100010])) +#define MCF_GPIO_PDDR_DATAH (*(vuint8 *)(void*)(&__IPSBAR[0x100011])) +#define MCF_GPIO_PDDR_DATAL (*(vuint8 *)(void*)(&__IPSBAR[0x100012])) +#define MCF_GPIO_PDDR_BUSCTL (*(vuint8 *)(void*)(&__IPSBAR[0x100013])) +#define MCF_GPIO_PDDR_BS (*(vuint8 *)(void*)(&__IPSBAR[0x100014])) +#define MCF_GPIO_PDDR_CS (*(vuint8 *)(void*)(&__IPSBAR[0x100015])) +#define MCF_GPIO_PDDR_SDRAM (*(vuint8 *)(void*)(&__IPSBAR[0x100016])) +#define MCF_GPIO_PDDR_FECI2C (*(vuint8 *)(void*)(&__IPSBAR[0x100017])) +#define MCF_GPIO_PDDR_UARTH (*(vuint8 *)(void*)(&__IPSBAR[0x100018])) +#define MCF_GPIO_PDDR_UARTL (*(vuint8 *)(void*)(&__IPSBAR[0x100019])) +#define MCF_GPIO_PDDR_QSPI (*(vuint8 *)(void*)(&__IPSBAR[0x10001A])) +#define MCF_GPIO_PDDR_TIMER (*(vuint8 *)(void*)(&__IPSBAR[0x10001B])) +#define MCF_GPIO_PDDR_ETPU (*(vuint8 *)(void*)(&__IPSBAR[0x10001C])) +#define MCF_GPIO_PPDSDR_ADDR (*(vuint8 *)(void*)(&__IPSBAR[0x100020])) +#define MCF_GPIO_PPDSDR_DATAH (*(vuint8 *)(void*)(&__IPSBAR[0x100021])) +#define MCF_GPIO_PPDSDR_DATAL (*(vuint8 *)(void*)(&__IPSBAR[0x100022])) +#define MCF_GPIO_PPDSDR_BUSCTL (*(vuint8 *)(void*)(&__IPSBAR[0x100023])) +#define MCF_GPIO_PPDSDR_BS (*(vuint8 *)(void*)(&__IPSBAR[0x100024])) +#define MCF_GPIO_PPDSDR_FECI2C (*(vuint8 *)(void*)(&__IPSBAR[0x100027])) +#define MCF_GPIO_PPDSDR_CS (*(vuint8 *)(void*)(&__IPSBAR[0x100025])) +#define MCF_GPIO_PPDSDR_SDRAM (*(vuint8 *)(void*)(&__IPSBAR[0x100026])) +#define MCF_GPIO_PPDSDR_UARTH (*(vuint8 *)(void*)(&__IPSBAR[0x100028])) +#define MCF_GPIO_PPDSDR_UARTL (*(vuint8 *)(void*)(&__IPSBAR[0x100029])) +#define MCF_GPIO_PPDSDR_QSPI (*(vuint8 *)(void*)(&__IPSBAR[0x10002A])) +#define MCF_GPIO_PPDSDR_TIMER (*(vuint8 *)(void*)(&__IPSBAR[0x10002B])) +#define MCF_GPIO_PPDSDR_ETPU (*(vuint8 *)(void*)(&__IPSBAR[0x10002C])) +#define MCF_GPIO_PCLRR_ADDR (*(vuint8 *)(void*)(&__IPSBAR[0x100030])) +#define MCF_GPIO_PCLRR_DATAH (*(vuint8 *)(void*)(&__IPSBAR[0x100031])) +#define MCF_GPIO_PCLRR_DATAL (*(vuint8 *)(void*)(&__IPSBAR[0x100032])) +#define MCF_GPIO_PCLRR_BUSCTL (*(vuint8 *)(void*)(&__IPSBAR[0x100033])) +#define MCF_GPIO_PCLRR_BS (*(vuint8 *)(void*)(&__IPSBAR[0x100034])) +#define MCF_GPIO_PCLRR_CS (*(vuint8 *)(void*)(&__IPSBAR[0x100035])) +#define MCF_GPIO_PCLRR_SDRAM (*(vuint8 *)(void*)(&__IPSBAR[0x100036])) +#define MCF_GPIO_PCLRR_FECI2C (*(vuint8 *)(void*)(&__IPSBAR[0x100037])) +#define MCF_GPIO_PCLRR_UARTH (*(vuint8 *)(void*)(&__IPSBAR[0x100038])) +#define MCF_GPIO_PCLRR_UARTL (*(vuint8 *)(void*)(&__IPSBAR[0x100039])) +#define MCF_GPIO_PCLRR_QSPI (*(vuint8 *)(void*)(&__IPSBAR[0x10003A])) +#define MCF_GPIO_PCLRR_TIMER (*(vuint8 *)(void*)(&__IPSBAR[0x10003B])) +#define MCF_GPIO_PCLRR_ETPU (*(vuint8 *)(void*)(&__IPSBAR[0x10003C])) +#define MCF_GPIO_PAR_AD (*(vuint8 *)(void*)(&__IPSBAR[0x100040])) +#define MCF_GPIO_PAR_BUSCTL (*(vuint16*)(void*)(&__IPSBAR[0x100042])) +#define MCF_GPIO_PAR_BS (*(vuint8 *)(void*)(&__IPSBAR[0x100044])) +#define MCF_GPIO_PAR_CS (*(vuint8 *)(void*)(&__IPSBAR[0x100045])) +#define MCF_GPIO_PAR_SDRAM (*(vuint8 *)(void*)(&__IPSBAR[0x100046])) +#define MCF_GPIO_PAR_FECI2C (*(vuint8 *)(void*)(&__IPSBAR[0x100047])) +#define MCF_GPIO_PAR_UART (*(vuint16*)(void*)(&__IPSBAR[0x100048])) +#define MCF_GPIO_PAR_QSPI (*(vuint8 *)(void*)(&__IPSBAR[0x10004A])) +#define MCF_GPIO_PAR_TIMER (*(vuint16*)(void*)(&__IPSBAR[0x10004C])) +#define MCF_GPIO_PAR_ETPU (*(vuint8 *)(void*)(&__IPSBAR[0x10004E])) +#define MCF_GPIO_DSCR_EIM (*(vuint8 *)(void*)(&__IPSBAR[0x100050])) +#define MCF_GPIO_DSCR_ETPU (*(vuint8 *)(void*)(&__IPSBAR[0x100051])) +#define MCF_GPIO_DSCR_FECI2C (*(vuint8 *)(void*)(&__IPSBAR[0x100052])) +#define MCF_GPIO_DSCR_UART (*(vuint8 *)(void*)(&__IPSBAR[0x100053])) +#define MCF_GPIO_DSCR_QSPI (*(vuint8 *)(void*)(&__IPSBAR[0x100054])) +#define MCF_GPIO_DSCR_TIMER (*(vuint8 *)(void*)(&__IPSBAR[0x100055])) + +/* Bit definitions and macros for MCF_GPIO_PODR_ADDR */ +#define MCF_GPIO_PODR_ADDR_PODR_ADDR5 (0x20) +#define MCF_GPIO_PODR_ADDR_PODR_ADDR6 (0x40) +#define MCF_GPIO_PODR_ADDR_PODR_ADDR7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_DATAH */ +#define MCF_GPIO_PODR_DATAH_PODR_DATAH0 (0x01) +#define MCF_GPIO_PODR_DATAH_PODR_DATAH1 (0x02) +#define MCF_GPIO_PODR_DATAH_PODR_DATAH2 (0x04) +#define MCF_GPIO_PODR_DATAH_PODR_DATAH3 (0x08) +#define MCF_GPIO_PODR_DATAH_PODR_DATAH4 (0x10) +#define MCF_GPIO_PODR_DATAH_PODR_DATAH5 (0x20) +#define MCF_GPIO_PODR_DATAH_PODR_DATAH6 (0x40) +#define MCF_GPIO_PODR_DATAH_PODR_DATAH7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_DATAL */ +#define MCF_GPIO_PODR_DATAL_PODR_DATAL0 (0x01) +#define MCF_GPIO_PODR_DATAL_PODR_DATAL1 (0x02) +#define MCF_GPIO_PODR_DATAL_PODR_DATAL2 (0x04) +#define MCF_GPIO_PODR_DATAL_PODR_DATAL3 (0x08) +#define MCF_GPIO_PODR_DATAL_PODR_DATAL4 (0x10) +#define MCF_GPIO_PODR_DATAL_PODR_DATAL5 (0x20) +#define MCF_GPIO_PODR_DATAL_PODR_DATAL6 (0x40) +#define MCF_GPIO_PODR_DATAL_PODR_DATAL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_BUSCTL */ +#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL0 (0x01) +#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL1 (0x02) +#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL2 (0x04) +#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL3 (0x08) +#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL4 (0x10) +#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL5 (0x20) +#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL6 (0x40) +#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_BS */ +#define MCF_GPIO_PODR_BS_PODR_BS0 (0x01) +#define MCF_GPIO_PODR_BS_PODR_BS1 (0x02) +#define MCF_GPIO_PODR_BS_PODR_BS2 (0x04) +#define MCF_GPIO_PODR_BS_PODR_BS3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PODR_CS */ +#define MCF_GPIO_PODR_CS_PODR_CS1 (0x02) +#define MCF_GPIO_PODR_CS_PODR_CS2 (0x04) +#define MCF_GPIO_PODR_CS_PODR_CS3 (0x08) +#define MCF_GPIO_PODR_CS_PODR_CS4 (0x10) +#define MCF_GPIO_PODR_CS_PODR_CS5 (0x20) +#define MCF_GPIO_PODR_CS_PODR_CS6 (0x40) +#define MCF_GPIO_PODR_CS_PODR_CS7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_SDRAM */ +#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM0 (0x01) +#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM1 (0x02) +#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM2 (0x04) +#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM3 (0x08) +#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM4 (0x10) +#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */ +#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x01) +#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x02) +#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x04) +#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PODR_UARTH */ +#define MCF_GPIO_PODR_UARTH_PODR_UARTH0 (0x01) +#define MCF_GPIO_PODR_UARTH_PODR_UARTH1 (0x02) + +/* Bit definitions and macros for MCF_GPIO_PODR_UARTL */ +#define MCF_GPIO_PODR_UARTL_PODR_UARTL0 (0x01) +#define MCF_GPIO_PODR_UARTL_PODR_UARTL1 (0x02) +#define MCF_GPIO_PODR_UARTL_PODR_UARTL2 (0x04) +#define MCF_GPIO_PODR_UARTL_PODR_UARTL3 (0x08) +#define MCF_GPIO_PODR_UARTL_PODR_UARTL4 (0x10) +#define MCF_GPIO_PODR_UARTL_PODR_UARTL5 (0x20) +#define MCF_GPIO_PODR_UARTL_PODR_UARTL6 (0x40) +#define MCF_GPIO_PODR_UARTL_PODR_UARTL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_QSPI */ +#define MCF_GPIO_PODR_QSPI_PODR_QSPI0 (0x01) +#define MCF_GPIO_PODR_QSPI_PODR_QSPI1 (0x02) +#define MCF_GPIO_PODR_QSPI_PODR_QSPI2 (0x04) +#define MCF_GPIO_PODR_QSPI_PODR_QSPI3 (0x08) +#define MCF_GPIO_PODR_QSPI_PODR_QSPI4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PODR_TIMER */ +#define MCF_GPIO_PODR_TIMER_PODR_TIMER0 (0x01) +#define MCF_GPIO_PODR_TIMER_PODR_TIMER1 (0x02) +#define MCF_GPIO_PODR_TIMER_PODR_TIMER2 (0x04) +#define MCF_GPIO_PODR_TIMER_PODR_TIMER3 (0x08) +#define MCF_GPIO_PODR_TIMER_PODR_TIMER4 (0x10) +#define MCF_GPIO_PODR_TIMER_PODR_TIMER5 (0x20) +#define MCF_GPIO_PODR_TIMER_PODR_TIMER6 (0x40) +#define MCF_GPIO_PODR_TIMER_PODR_TIMER7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_ETPU */ +#define MCF_GPIO_PODR_ETPU_PODR_ETPU0 (0x01) +#define MCF_GPIO_PODR_ETPU_PODR_ETPU1 (0x02) +#define MCF_GPIO_PODR_ETPU_PODR_ETPU2 (0x04) + +/* Bit definitions and macros for MCF_GPIO_PDDR_APDDR */ +#define MCF_GPIO_PDDR_APDDR_PDDR_APDDR5 (0x20) +#define MCF_GPIO_PDDR_APDDR_PDDR_APDDR6 (0x40) +#define MCF_GPIO_PDDR_APDDR_PDDR_APDDR7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_DATAH */ +#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH0 (0x01) +#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH1 (0x02) +#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH2 (0x04) +#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH3 (0x08) +#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH4 (0x10) +#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH5 (0x20) +#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH6 (0x40) +#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_DATAL */ +#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL0 (0x01) +#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL1 (0x02) +#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL2 (0x04) +#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL3 (0x08) +#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL4 (0x10) +#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL5 (0x20) +#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL6 (0x40) +#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_BUSCTL */ +#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL0 (0x01) +#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL1 (0x02) +#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL2 (0x04) +#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL3 (0x08) +#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL4 (0x10) +#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL5 (0x20) +#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL6 (0x40) +#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_BS */ +#define MCF_GPIO_PDDR_BS_PDDR_BS0 (0x01) +#define MCF_GPIO_PDDR_BS_PDDR_BS3(x) (((x)&0x07)<<1) + +/* Bit definitions and macros for MCF_GPIO_PDDR_CS */ +#define MCF_GPIO_PDDR_CS_PDDR_CS1 (0x02) +#define MCF_GPIO_PDDR_CS_PDDR_CS2 (0x04) +#define MCF_GPIO_PDDR_CS_PDDR_CS3 (0x08) +#define MCF_GPIO_PDDR_CS_PDDR_CS4 (0x10) +#define MCF_GPIO_PDDR_CS_PDDR_CS5 (0x20) +#define MCF_GPIO_PDDR_CS_PDDR_CS6 (0x40) +#define MCF_GPIO_PDDR_CS_PDDR_CS7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_SDRAM */ +#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM0 (0x01) +#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM1 (0x02) +#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM2 (0x04) +#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM3 (0x08) +#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM4 (0x10) +#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */ +#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x01) +#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x02) +#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x04) +#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PDDR_UARTH */ +#define MCF_GPIO_PDDR_UARTH_PDDR_UARTH0 (0x01) +#define MCF_GPIO_PDDR_UARTH_PDDR_UARTH1 (0x02) + +/* Bit definitions and macros for MCF_GPIO_PDDR_UARTL */ +#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL0 (0x01) +#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL1 (0x02) +#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL2 (0x04) +#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL3 (0x08) +#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL4 (0x10) +#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL5 (0x20) +#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL6 (0x40) +#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_QSPI */ +#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI0 (0x01) +#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI1 (0x02) +#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI2 (0x04) +#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI3 (0x08) +#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PDDR_TIMER */ +#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER0 (0x01) +#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER1 (0x02) +#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER2 (0x04) +#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER3 (0x08) +#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER4 (0x10) +#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER5 (0x20) +#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER6 (0x40) +#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_ETPU */ +#define MCF_GPIO_PDDR_ETPU_PDDR_ETPU0 (0x01) +#define MCF_GPIO_PDDR_ETPU_PDDR_ETPU1 (0x02) +#define MCF_GPIO_PDDR_ETPU_PDDR_ETPU2 (0x04) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_ADDR */ +#define MCF_GPIO_PPDSDR_ADDR_PPDSDR_ADDR5 (0x20) +#define MCF_GPIO_PPDSDR_ADDR_PPDSDR_ADDR6 (0x40) +#define MCF_GPIO_PPDSDR_ADDR_PPDSDR_ADDR7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_DATAH */ +#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH0 (0x01) +#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH1 (0x02) +#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH2 (0x04) +#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH3 (0x08) +#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH4 (0x10) +#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH5 (0x20) +#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH6 (0x40) +#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_DATAL */ +#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL0 (0x01) +#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL1 (0x02) +#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL2 (0x04) +#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL3 (0x08) +#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL4 (0x10) +#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL5 (0x20) +#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL6 (0x40) +#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_BUSCTL */ +#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL0 (0x01) +#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL1 (0x02) +#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL2 (0x04) +#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL3 (0x08) +#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL4 (0x10) +#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL5 (0x20) +#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL6 (0x40) +#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_BS */ +#define MCF_GPIO_PPDSDR_BS_PPDSDR_BS0 (0x01) +#define MCF_GPIO_PPDSDR_BS_PPDSDR_BS1 (0x02) +#define MCF_GPIO_PPDSDR_BS_PPDSDR_BS2 (0x04) +#define MCF_GPIO_PPDSDR_BS_PPDSDR_BS3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */ +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x01) +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x02) +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x04) +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_CS */ +#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS1 (0x02) +#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS2 (0x04) +#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS3 (0x08) +#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS4 (0x10) +#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS5 (0x20) +#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS6 (0x40) +#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_SDRAM */ +#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM0 (0x01) +#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM1 (0x02) +#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM2 (0x04) +#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM3 (0x08) +#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM4 (0x10) +#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM5 (0x20) +#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM6 (0x40) +#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_UARTH */ +#define MCF_GPIO_PPDSDR_UARTH_PPDSDR_UARTH0 (0x01) +#define MCF_GPIO_PPDSDR_UARTH_PPDSDR_UARTH1 (0x02) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_UARTL */ +#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL0 (0x01) +#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL1 (0x02) +#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL2 (0x04) +#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL3 (0x08) +#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL4 (0x10) +#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL5 (0x20) +#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL6 (0x40) +#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_QSPI */ +#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI0 (0x01) +#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI1 (0x02) +#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI2 (0x04) +#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI3 (0x08) +#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_TIMER */ +#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER0 (0x01) +#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER1 (0x02) +#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER2 (0x04) +#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER3 (0x08) +#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER4 (0x10) +#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER5 (0x20) +#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER6 (0x40) +#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_ETPU */ +#define MCF_GPIO_PPDSDR_ETPU_PPDSDR_ETPU0 (0x01) +#define MCF_GPIO_PPDSDR_ETPU_PPDSDR_ETPU1 (0x02) +#define MCF_GPIO_PPDSDR_ETPU_PPDSDR_ETPU2 (0x04) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_ADDR */ +#define MCF_GPIO_PCLRR_ADDR_PCLRR_ADDR5 (0x20) +#define MCF_GPIO_PCLRR_ADDR_PCLRR_ADDR6 (0x40) +#define MCF_GPIO_PCLRR_ADDR_PCLRR_ADDR7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_DATAH */ +#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH0 (0x01) +#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH1 (0x02) +#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH2 (0x04) +#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH3 (0x08) +#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH4 (0x10) +#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH5 (0x20) +#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH6 (0x40) +#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_DATAL */ +#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL0 (0x01) +#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL1 (0x02) +#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL2 (0x04) +#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL3 (0x08) +#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL4 (0x10) +#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL5 (0x20) +#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL6 (0x40) +#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_BUSCTL */ +#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL0 (0x01) +#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL1 (0x02) +#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL2 (0x04) +#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL3 (0x08) +#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL4 (0x10) +#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL5 (0x20) +#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL6 (0x40) +#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_BS */ +#define MCF_GPIO_PCLRR_BS_PCLRR_BS0 (0x01) +#define MCF_GPIO_PCLRR_BS_PCLRR_BS1 (0x02) +#define MCF_GPIO_PCLRR_BS_PCLRR_BS2 (0x04) +#define MCF_GPIO_PCLRR_BS_PCLRR_BS3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_CS */ +#define MCF_GPIO_PCLRR_CS_PCLRR_CS1 (0x02) +#define MCF_GPIO_PCLRR_CS_PCLRR_CS2 (0x04) +#define MCF_GPIO_PCLRR_CS_PCLRR_CS3 (0x08) +#define MCF_GPIO_PCLRR_CS_PCLRR_CS4 (0x10) +#define MCF_GPIO_PCLRR_CS_PCLRR_CS5 (0x20) +#define MCF_GPIO_PCLRR_CS_PCLRR_CS6 (0x40) +#define MCF_GPIO_PCLRR_CS_PCLRR_CS7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_SDRAM */ +#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM0 (0x01) +#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM1 (0x02) +#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM2 (0x04) +#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM3 (0x08) +#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM4 (0x10) +#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */ +#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x01) +#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x02) +#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2 (0x04) +#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_UARTH */ +#define MCF_GPIO_PCLRR_UARTH_PCLRR_UARTH0 (0x01) +#define MCF_GPIO_PCLRR_UARTH_PCLRR_UARTH1 (0x02) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_UARTL */ +#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL0 (0x01) +#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL1 (0x02) +#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL2 (0x04) +#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL3 (0x08) +#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL4 (0x10) +#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL5 (0x20) +#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL6 (0x40) +#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_QSPI */ +#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI0 (0x01) +#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI1 (0x02) +#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI2 (0x04) +#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI3 (0x08) +#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_TIMER */ +#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER0 (0x01) +#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER1 (0x02) +#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER2 (0x04) +#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER3 (0x08) +#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER4 (0x10) +#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER5 (0x20) +#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER6 (0x40) +#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_ETPU */ +#define MCF_GPIO_PCLRR_ETPU_PCLRR_ETPU0 (0x01) +#define MCF_GPIO_PCLRR_ETPU_PCLRR_ETPU1 (0x02) +#define MCF_GPIO_PCLRR_ETPU_PCLRR_ETPU2 (0x04) + +/* Bit definitions and macros for MCF_GPIO_PAR_AD */ +#define MCF_GPIO_PAR_AD_PAR_DATAL (0x01) +#define MCF_GPIO_PAR_AD_PAR_ADDR21 (0x20) +#define MCF_GPIO_PAR_AD_PAR_ADDR22 (0x40) +#define MCF_GPIO_PAR_AD_PAR_ADDR23 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PAR_BUSCTL */ +#define MCF_GPIO_PAR_BUSCTL_PAR_TIP(x) (((x)&0x0003)<<0) +#define MCF_GPIO_PAR_BUSCTL_PAR_TS(x) (((x)&0x0003)<<2) +#define MCF_GPIO_PAR_BUSCTL_PAR_TSIZ0 (0x0010) +#define MCF_GPIO_PAR_BUSCTL_PAR_TSIZ1 (0x0040) +#define MCF_GPIO_PAR_BUSCTL_PAR_RWB (0x0100) +#define MCF_GPIO_PAR_BUSCTL_PAR_TEA(x) (((x)&0x0003)<<10) +#define MCF_GPIO_PAR_BUSCTL_PAR_TA (0x1000) +#define MCF_GPIO_PAR_BUSCTL_PAR_OE (0x4000) +#define MCF_GPIO_PAR_BUSCTL_PAR_TEA_GPIO (0x0000) +#define MCF_GPIO_PAR_BUSCTL_PAR_TEA_DMA (0x0800) +#define MCF_GPIO_PAR_BUSCTL_PAR_TEA_TEA (0x0C00) +#define MCF_GPIO_PAR_BUSCTL_PAR_TS_GPIO (0x0000) +#define MCF_GPIO_PAR_BUSCTL_PAR_TS_DMA (0x0080) +#define MCF_GPIO_PAR_BUSCTL_PAR_TS_TS (0x00C0) +#define MCF_GPIO_PAR_BUSCTL_PAR_TIP_GPIO (0x0000) +#define MCF_GPIO_PAR_BUSCTL_PAR_TIP_DMA (0x0002) +#define MCF_GPIO_PAR_BUSCTL_PAR_TIP_TEA (0x0003) + +/* Bit definitions and macros for MCF_GPIO_PAR_BS */ +#define MCF_GPIO_PAR_BS_PAR_BS0 (0x01) +#define MCF_GPIO_PAR_BS_PAR_BS1 (0x02) +#define MCF_GPIO_PAR_BS_PAR_BS2 (0x04) +#define MCF_GPIO_PAR_BS_PAR_BS3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PAR_CS */ +#define MCF_GPIO_PAR_CS_PAR_CS1 (0x02) +#define MCF_GPIO_PAR_CS_PAR_CS2 (0x04) +#define MCF_GPIO_PAR_CS_PAR_CS3 (0x08) +#define MCF_GPIO_PAR_CS_PAR_CS4 (0x10) +#define MCF_GPIO_PAR_CS_PAR_CS5 (0x20) +#define MCF_GPIO_PAR_CS_PAR_CS6 (0x40) +#define MCF_GPIO_PAR_CS_PAR_CS7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PAR_SDRAM */ +#define MCF_GPIO_PAR_SDRAM_PAR_SDCS0 (0x01) +#define MCF_GPIO_PAR_SDRAM_PAR_SDCS1 (0x02) +#define MCF_GPIO_PAR_SDRAM_PAR_SCKE (0x04) +#define MCF_GPIO_PAR_SDRAM_PAR_SRAS (0x08) +#define MCF_GPIO_PAR_SDRAM_PAR_SCAS (0x10) +#define MCF_GPIO_PAR_SDRAM_PAR_SDWE (0x20) +#define MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(x) (((x)&0x03)<<6) + +/* Bit definitions and macros for MCF_GPIO_PAR_FECI2C */ +#define MCF_GPIO_PAR_FECI2C_PAR_SDA(x) (((x)&0x03)<<0) +#define MCF_GPIO_PAR_FECI2C_PAR_SCL(x) (((x)&0x03)<<2) +#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO(x) (((x)&0x03)<<4) +#define MCF_GPIO_PAR_FECI2C_PAR_EMDC(x) (((x)&0x03)<<6) +#define MCF_GPIO_PAR_FECI2C_PAR_EMDC_GPIO (0x00) +#define MCF_GPIO_PAR_FECI2C_PAR_EMDC_UART2 (0x40) +#define MCF_GPIO_PAR_FECI2C_PAR_EMDC_I2C (0x80) +#define MCF_GPIO_PAR_FECI2C_PAR_EMDC_FEC (0xC0) +#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO_GPIO (0x00) +#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO_UART2 (0x10) +#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO_I2C (0x20) +#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO_FEC (0x30) +#define MCF_GPIO_PAR_FECI2C_PAR_SCL_GPIO (0x00) +#define MCF_GPIO_PAR_FECI2C_PAR_SCL_FLEX (0x08) +#define MCF_GPIO_PAR_FECI2C_PAR_SCL_I2C (0x0C) +#define MCF_GPIO_PAR_FECI2C_PAR_SDA_GPIO (0x00) +#define MCF_GPIO_PAR_FECI2C_PAR_SDA_FLEX (0x02) +#define MCF_GPIO_PAR_FECI2C_PAR_SDA_I2C (0x03) + +/* Bit definitions and macros for MCF_GPIO_PAR_UART */ +#define MCF_GPIO_PAR_UART_PAR_U0RTS (0x0001) +#define MCF_GPIO_PAR_UART_PAR_U0CTS (0x0002) +#define MCF_GPIO_PAR_UART_PAR_U0TXD (0x0004) +#define MCF_GPIO_PAR_UART_PAR_U0RXD (0x0008) +#define MCF_GPIO_PAR_UART_PAR_U1RTS(x) (((x)&0x0003)<<4) +#define MCF_GPIO_PAR_UART_PAR_U1CTS(x) (((x)&0x0003)<<6) +#define MCF_GPIO_PAR_UART_PAR_U1TXD(x) (((x)&0x0003)<<8) +#define MCF_GPIO_PAR_UART_PAR_U1RXD(x) (((x)&0x0003)<<10) +#define MCF_GPIO_PAR_UART_PAR_U2TXD (0x1000) +#define MCF_GPIO_PAR_UART_PAR_U2RXD (0x2000) +#define MCF_GPIO_PAR_UART_PAR_CAN1EN (0x4000) +#define MCF_GPIO_PAR_UART_PAR_DREQ2 (0x8000) +#define MCF_GPIO_PAR_UART_PAR_U1RXD_GPIO (0x0000) +#define MCF_GPIO_PAR_UART_PAR_U1RXD_FLEX (0x0800) +#define MCF_GPIO_PAR_UART_PAR_U1RXD_UART1 (0x0C00) +#define MCF_GPIO_PAR_UART_PAR_U1TXD_GPIO (0x0000) +#define MCF_GPIO_PAR_UART_PAR_U1TXD_FLEX (0x0200) +#define MCF_GPIO_PAR_UART_PAR_U1TXD_UART1 (0x0300) +#define MCF_GPIO_PAR_UART_PAR_U1CTS_GPIO (0x0000) +#define MCF_GPIO_PAR_UART_PAR_U1CTS_UART2 (0x0080) +#define MCF_GPIO_PAR_UART_PAR_U1CTS_UART1 (0x00C0) +#define MCF_GPIO_PAR_UART_PAR_U1RTS_GPIO (0x0000) +#define MCF_GPIO_PAR_UART_PAR_U1RTS_UART2 (0x0020) +#define MCF_GPIO_PAR_UART_PAR_U1RTS_UART1 (0x0030) + +/* Bit definitions and macros for MCF_GPIO_PAR_QSPI */ +#define MCF_GPIO_PAR_QSPI_PAR_SCK(x) (((x)&0x03)<<0) +#define MCF_GPIO_PAR_QSPI_PAR_DOUT (0x04) +#define MCF_GPIO_PAR_QSPI_PAR_DIN(x) (((x)&0x03)<<3) +#define MCF_GPIO_PAR_QSPI_PAR_PCS0 (0x20) +#define MCF_GPIO_PAR_QSPI_PAR_PCS1(x) (((x)&0x03)<<6) +#define MCF_GPIO_PAR_QSPI_PAR_PCS1_GPIO (0x00) +#define MCF_GPIO_PAR_QSPI_PAR_PCS1_SDRAMC (0x80) +#define MCF_GPIO_PAR_QSPI_PAR_PCS1_QSPI (0xC0) +#define MCF_GPIO_PAR_QSPI_PAR_DIN_GPIO (0x00) +#define MCF_GPIO_PAR_QSPI_PAR_DIN_I2C (0x10) +#define MCF_GPIO_PAR_QSPI_PAR_DIN_QSPI (0x1C) +#define MCF_GPIO_PAR_QSPI_PAR_SCK_GPIO (0x00) +#define MCF_GPIO_PAR_QSPI_PAR_SCK_I2C (0x02) +#define MCF_GPIO_PAR_QSPI_PAR_SCK_QSPI (0x03) + +/* Bit definitions and macros for MCF_GPIO_PAR_TIMER */ +#define MCF_GPIO_PAR_TIMER_PAR_T0OUT(x) (((x)&0x0003)<<0) +#define MCF_GPIO_PAR_TIMER_PAR_T1OUT(x) (((x)&0x0003)<<2) +#define MCF_GPIO_PAR_TIMER_PAR_T2OUT(x) (((x)&0x0003)<<4) +#define MCF_GPIO_PAR_TIMER_PAR_T3OUT(x) (((x)&0x0003)<<6) +#define MCF_GPIO_PAR_TIMER_PAR_T0IN(x) (((x)&0x0003)<<8) +#define MCF_GPIO_PAR_TIMER_PAR_T1IN(x) (((x)&0x0003)<<10) +#define MCF_GPIO_PAR_TIMER_PAR_T2IN(x) (((x)&0x0003)<<12) +#define MCF_GPIO_PAR_TIMER_PAR_T3IN(x) (((x)&0x0003)<<14) +#define MCF_GPIO_PAR_TIMER_PAR_T3IN_GPIO (0x0000) +#define MCF_GPIO_PAR_TIMER_PAR_T3IN_QSPI (0x4000) +#define MCF_GPIO_PAR_TIMER_PAR_T3IN_UART2 (0x8000) +#define MCF_GPIO_PAR_TIMER_PAR_T3IN_T3IN (0xC000) +#define MCF_GPIO_PAR_TIMER_PAR_T2IN_GPIO (0x0000) +#define MCF_GPIO_PAR_TIMER_PAR_T2IN_T2OUT (0x1000) +#define MCF_GPIO_PAR_TIMER_PAR_T2IN_DMA (0x2000) +#define MCF_GPIO_PAR_TIMER_PAR_T2IN_T2IN (0x3000) +#define MCF_GPIO_PAR_TIMER_PAR_T1IN_GPIO (0x0000) +#define MCF_GPIO_PAR_TIMER_PAR_T1IN_T1OUT (0x0400) +#define MCF_GPIO_PAR_TIMER_PAR_T1IN_DMA (0x0800) +#define MCF_GPIO_PAR_TIMER_PAR_T1IN_T1IN (0x0C00) +#define MCF_GPIO_PAR_TIMER_PAR_T0IN_GPIO (0x0000) +#define MCF_GPIO_PAR_TIMER_PAR_T0IN_DMA (0x0200) +#define MCF_GPIO_PAR_TIMER_PAR_T0IN_T0IN (0x0300) +#define MCF_GPIO_PAR_TIMER_PAR_T3OUT_GPIO (0x0000) +#define MCF_GPIO_PAR_TIMER_PAR_T3OUT_QSPI (0x0040) +#define MCF_GPIO_PAR_TIMER_PAR_T3OUT_UART2 (0x0080) +#define MCF_GPIO_PAR_TIMER_PAR_T3OUT_T3OUT (0x00C0) +#define MCF_GPIO_PAR_TIMER_PAR_T2OUT_GPIO (0x0000) +#define MCF_GPIO_PAR_TIMER_PAR_T2OUT_DMA (0x0020) +#define MCF_GPIO_PAR_TIMER_PAR_T2OUT_T2OUT (0x0030) +#define MCF_GPIO_PAR_TIMER_PAR_T1OUT_GPIO (0x0000) +#define MCF_GPIO_PAR_TIMER_PAR_T1OUT_DMA (0x0008) +#define MCF_GPIO_PAR_TIMER_PAR_T1OUT_T1OUT (0x000C) +#define MCF_GPIO_PAR_TIMER_PAR_T0OUT_GPIO (0x0000) +#define MCF_GPIO_PAR_TIMER_PAR_T0OUT_DMA (0x0002) +#define MCF_GPIO_PAR_TIMER_PAR_T0OUT_T0OUT (0x0003) + +/* Bit definitions and macros for MCF_GPIO_PAR_ETPU */ +#define MCF_GPIO_PAR_ETPU_PAR_LTPU_ODIS (0x01) +#define MCF_GPIO_PAR_ETPU_PAR_UTPU_ODIS (0x02) +#define MCF_GPIO_PAR_ETPU_PAR_TCRCLK (0x04) + +/* Bit definitions and macros for MCF_GPIO_DSCR_EIM */ +#define MCF_GPIO_DSCR_EIM_DSCR_EIM0 (0x01) +#define MCF_GPIO_DSCR_EIM_DSCR_EIM1 (0x10) + +/* Bit definitions and macros for MCF_GPIO_DSCR_ETPU */ +#define MCF_GPIO_DSCR_ETPU_DSCR_ETPU_7_0 (0x01) +#define MCF_GPIO_DSCR_ETPU_DSCR_ETPU_15_8 (0x04) +#define MCF_GPIO_DSCR_ETPU_DSCR_ETPU_23_16 (0x10) +#define MCF_GPIO_DSCR_ETPU_DSCR_ETPU_31_24 (0x40) + +/* Bit definitions and macros for MCF_GPIO_DSCR_FECI2C */ +#define MCF_GPIO_DSCR_FECI2C_DSCR_I2C (0x01) +#define MCF_GPIO_DSCR_FECI2C_DSCR_FEC (0x10) + +/* Bit definitions and macros for MCF_GPIO_DSCR_UART */ +#define MCF_GPIO_DSCR_UART_DSCR_UART0 (0x01) +#define MCF_GPIO_DSCR_UART_DSCR_UART1 (0x04) +#define MCF_GPIO_DSCR_UART_DSCR_UART2 (0x10) +#define MCF_GPIO_DSCR_UART_DSCR_IRQ (0x40) + +/* Bit definitions and macros for MCF_GPIO_DSCR_QSPI */ +#define MCF_GPIO_DSCR_QSPI_DSCR_QSPI (0x01) + +/* Bit definitions and macros for MCF_GPIO_DSCR_TIMER */ +#define MCF_GPIO_DSCR_TIMER_DSCR_TIMER (0x01) + +/********************************************************************/ + +#endif /* __MCF523X_GPIO_H__ */ diff --git a/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_i2c.h b/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_i2c.h new file mode 100644 index 000000000..3bb780b82 --- /dev/null +++ b/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_i2c.h @@ -0,0 +1,63 @@ +/* + * These files are taken from the MCF523X source code example package + * which is available on the Freescale website. Freescale explicitly + * grants the redistribution and modification of these source files. + * The complete licensing information is available in the file + * LICENSE_FREESCALE.TXT. + * + * File: mcf523x_i2c.h + * Purpose: Register and bit definitions for the MCF523X + * + * Notes: + * + */ + +#ifndef __MCF523X_I2C_H__ +#define __MCF523X_I2C_H__ + +/********************************************************************* +* +* I2C Module (I2C) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_I2C_I2AR (*(vuint8 *)(void*)(&__IPSBAR[0x000300])) +#define MCF_I2C_I2FDR (*(vuint8 *)(void*)(&__IPSBAR[0x000304])) +#define MCF_I2C_I2CR (*(vuint8 *)(void*)(&__IPSBAR[0x000308])) +#define MCF_I2C_I2SR (*(vuint8 *)(void*)(&__IPSBAR[0x00030C])) +#define MCF_I2C_I2DR (*(vuint8 *)(void*)(&__IPSBAR[0x000310])) +#define MCF_I2C_I2ICR (*(vuint8 *)(void*)(&__IPSBAR[0x000320])) + +/* Bit definitions and macros for MCF_I2C_I2AR */ +#define MCF_I2C_I2AR_ADR(x) (((x)&0x7F)<<1) + +/* Bit definitions and macros for MCF_I2C_I2FDR */ +#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)<<0) + +/* Bit definitions and macros for MCF_I2C_I2CR */ +#define MCF_I2C_I2CR_RSTA (0x04) +#define MCF_I2C_I2CR_TXAK (0x08) +#define MCF_I2C_I2CR_MTX (0x10) +#define MCF_I2C_I2CR_MSTA (0x20) +#define MCF_I2C_I2CR_IIEN (0x40) +#define MCF_I2C_I2CR_IEN (0x80) + +/* Bit definitions and macros for MCF_I2C_I2SR */ +#define MCF_I2C_I2SR_RXAK (0x01) +#define MCF_I2C_I2SR_IIF (0x02) +#define MCF_I2C_I2SR_SRW (0x04) +#define MCF_I2C_I2SR_IAL (0x10) +#define MCF_I2C_I2SR_IBB (0x20) +#define MCF_I2C_I2SR_IAAS (0x40) +#define MCF_I2C_I2SR_ICF (0x80) + +/* Bit definitions and macros for MCF_I2C_I2ICR */ +#define MCF_I2C_I2ICR_IE (0x01) +#define MCF_I2C_I2ICR_RE (0x02) +#define MCF_I2C_I2ICR_TE (0x04) +#define MCF_I2C_I2ICR_BNBE (0x08) + +/********************************************************************/ + +#endif /* __MCF523X_I2C_H__ */ diff --git a/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_intc0.h b/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_intc0.h new file mode 100644 index 000000000..2e06524f4 --- /dev/null +++ b/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_intc0.h @@ -0,0 +1,323 @@ +/* + * These files are taken from the MCF523X source code example package + * which is available on the Freescale website. Freescale explicitly + * grants the redistribution and modification of these source files. + * The complete licensing information is available in the file + * LICENSE_FREESCALE.TXT. + * + * File: mcf523x_intc0.h + * Purpose: Register and bit definitions for the MCF523X + * + * Notes: + * + */ + +#ifndef __MCF523X_INTC0_H__ +#define __MCF523X_INTC0_H__ + +/********************************************************************* +* +* Interrupt Controller 0 (INTC0) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_INTC0_IPRH (*(vuint32*)(void*)(&__IPSBAR[0x000C00])) +#define MCF_INTC0_IPRL (*(vuint32*)(void*)(&__IPSBAR[0x000C04])) +#define MCF_INTC0_IMRH (*(vuint32*)(void*)(&__IPSBAR[0x000C08])) +#define MCF_INTC0_IMRL (*(vuint32*)(void*)(&__IPSBAR[0x000C0C])) +#define MCF_INTC0_INTFRCH (*(vuint32*)(void*)(&__IPSBAR[0x000C10])) +#define MCF_INTC0_INTFRCL (*(vuint32*)(void*)(&__IPSBAR[0x000C14])) +#define MCF_INTC0_IRLR (*(vuint8 *)(void*)(&__IPSBAR[0x000C18])) +#define MCF_INTC0_IACKLPR (*(vuint8 *)(void*)(&__IPSBAR[0x000C19])) +#define MCF_INTC0_ICR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000C40])) +#define MCF_INTC0_ICR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000C41])) +#define MCF_INTC0_ICR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000C42])) +#define MCF_INTC0_ICR3 (*(vuint8 *)(void*)(&__IPSBAR[0x000C43])) +#define MCF_INTC0_ICR4 (*(vuint8 *)(void*)(&__IPSBAR[0x000C44])) +#define MCF_INTC0_ICR5 (*(vuint8 *)(void*)(&__IPSBAR[0x000C45])) +#define MCF_INTC0_ICR6 (*(vuint8 *)(void*)(&__IPSBAR[0x000C46])) +#define MCF_INTC0_ICR7 (*(vuint8 *)(void*)(&__IPSBAR[0x000C47])) +#define MCF_INTC0_ICR8 (*(vuint8 *)(void*)(&__IPSBAR[0x000C48])) +#define MCF_INTC0_ICR9 (*(vuint8 *)(void*)(&__IPSBAR[0x000C49])) +#define MCF_INTC0_ICR10 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4A])) +#define MCF_INTC0_ICR11 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4B])) +#define MCF_INTC0_ICR12 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4C])) +#define MCF_INTC0_ICR13 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4D])) +#define MCF_INTC0_ICR14 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4E])) +#define MCF_INTC0_ICR15 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4F])) +#define MCF_INTC0_ICR16 (*(vuint8 *)(void*)(&__IPSBAR[0x000C50])) +#define MCF_INTC0_ICR17 (*(vuint8 *)(void*)(&__IPSBAR[0x000C51])) +#define MCF_INTC0_ICR18 (*(vuint8 *)(void*)(&__IPSBAR[0x000C52])) +#define MCF_INTC0_ICR19 (*(vuint8 *)(void*)(&__IPSBAR[0x000C53])) +#define MCF_INTC0_ICR20 (*(vuint8 *)(void*)(&__IPSBAR[0x000C54])) +#define MCF_INTC0_ICR21 (*(vuint8 *)(void*)(&__IPSBAR[0x000C55])) +#define MCF_INTC0_ICR22 (*(vuint8 *)(void*)(&__IPSBAR[0x000C56])) +#define MCF_INTC0_ICR23 (*(vuint8 *)(void*)(&__IPSBAR[0x000C57])) +#define MCF_INTC0_ICR24 (*(vuint8 *)(void*)(&__IPSBAR[0x000C58])) +#define MCF_INTC0_ICR25 (*(vuint8 *)(void*)(&__IPSBAR[0x000C59])) +#define MCF_INTC0_ICR26 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5A])) +#define MCF_INTC0_ICR27 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5B])) +#define MCF_INTC0_ICR28 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5C])) +#define MCF_INTC0_ICR29 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5D])) +#define MCF_INTC0_ICR30 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5E])) +#define MCF_INTC0_ICR31 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5F])) +#define MCF_INTC0_ICR32 (*(vuint8 *)(void*)(&__IPSBAR[0x000C60])) +#define MCF_INTC0_ICR33 (*(vuint8 *)(void*)(&__IPSBAR[0x000C61])) +#define MCF_INTC0_ICR34 (*(vuint8 *)(void*)(&__IPSBAR[0x000C62])) +#define MCF_INTC0_ICR35 (*(vuint8 *)(void*)(&__IPSBAR[0x000C63])) +#define MCF_INTC0_ICR36 (*(vuint8 *)(void*)(&__IPSBAR[0x000C64])) +#define MCF_INTC0_ICR37 (*(vuint8 *)(void*)(&__IPSBAR[0x000C65])) +#define MCF_INTC0_ICR38 (*(vuint8 *)(void*)(&__IPSBAR[0x000C66])) +#define MCF_INTC0_ICR39 (*(vuint8 *)(void*)(&__IPSBAR[0x000C67])) +#define MCF_INTC0_ICR40 (*(vuint8 *)(void*)(&__IPSBAR[0x000C68])) +#define MCF_INTC0_ICR41 (*(vuint8 *)(void*)(&__IPSBAR[0x000C69])) +#define MCF_INTC0_ICR42 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6A])) +#define MCF_INTC0_ICR43 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6B])) +#define MCF_INTC0_ICR44 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6C])) +#define MCF_INTC0_ICR45 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6D])) +#define MCF_INTC0_ICR46 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6E])) +#define MCF_INTC0_ICR47 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6F])) +#define MCF_INTC0_ICR48 (*(vuint8 *)(void*)(&__IPSBAR[0x000C70])) +#define MCF_INTC0_ICR49 (*(vuint8 *)(void*)(&__IPSBAR[0x000C71])) +#define MCF_INTC0_ICR50 (*(vuint8 *)(void*)(&__IPSBAR[0x000C72])) +#define MCF_INTC0_ICR51 (*(vuint8 *)(void*)(&__IPSBAR[0x000C73])) +#define MCF_INTC0_ICR52 (*(vuint8 *)(void*)(&__IPSBAR[0x000C74])) +#define MCF_INTC0_ICR53 (*(vuint8 *)(void*)(&__IPSBAR[0x000C75])) +#define MCF_INTC0_ICR54 (*(vuint8 *)(void*)(&__IPSBAR[0x000C76])) +#define MCF_INTC0_ICR55 (*(vuint8 *)(void*)(&__IPSBAR[0x000C77])) +#define MCF_INTC0_ICR56 (*(vuint8 *)(void*)(&__IPSBAR[0x000C78])) +#define MCF_INTC0_ICR57 (*(vuint8 *)(void*)(&__IPSBAR[0x000C79])) +#define MCF_INTC0_ICR58 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7A])) +#define MCF_INTC0_ICR59 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7B])) +#define MCF_INTC0_ICR60 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7C])) +#define MCF_INTC0_ICR61 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7D])) +#define MCF_INTC0_ICR62 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7E])) +#define MCF_INTC0_ICR63 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7F])) +#define MCF_INTC0_ICRn(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000C40+((x)*0x001)])) +#define MCF_INTC0_SWIACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CE0])) +#define MCF_INTC0_L1IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CE4])) +#define MCF_INTC0_L2IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CE8])) +#define MCF_INTC0_L3IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CEC])) +#define MCF_INTC0_L4IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CF0])) +#define MCF_INTC0_L5IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CF4])) +#define MCF_INTC0_L6IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CF8])) +#define MCF_INTC0_L7IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CFC])) +#define MCF_INTC0_LnIACK(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000CE4+((x)*0x004)])) + +/* Bit definitions and macros for MCF_INTC0_IPRH */ +#define MCF_INTC0_IPRH_INT32 (0x00000001) +#define MCF_INTC0_IPRH_INT33 (0x00000002) +#define MCF_INTC0_IPRH_INT34 (0x00000004) +#define MCF_INTC0_IPRH_INT35 (0x00000008) +#define MCF_INTC0_IPRH_INT36 (0x00000010) +#define MCF_INTC0_IPRH_INT37 (0x00000020) +#define MCF_INTC0_IPRH_INT38 (0x00000040) +#define MCF_INTC0_IPRH_INT39 (0x00000080) +#define MCF_INTC0_IPRH_INT40 (0x00000100) +#define MCF_INTC0_IPRH_INT41 (0x00000200) +#define MCF_INTC0_IPRH_INT42 (0x00000400) +#define MCF_INTC0_IPRH_INT43 (0x00000800) +#define MCF_INTC0_IPRH_INT44 (0x00001000) +#define MCF_INTC0_IPRH_INT45 (0x00002000) +#define MCF_INTC0_IPRH_INT46 (0x00004000) +#define MCF_INTC0_IPRH_INT47 (0x00008000) +#define MCF_INTC0_IPRH_INT48 (0x00010000) +#define MCF_INTC0_IPRH_INT49 (0x00020000) +#define MCF_INTC0_IPRH_INT50 (0x00040000) +#define MCF_INTC0_IPRH_INT51 (0x00080000) +#define MCF_INTC0_IPRH_INT52 (0x00100000) +#define MCF_INTC0_IPRH_INT53 (0x00200000) +#define MCF_INTC0_IPRH_INT54 (0x00400000) +#define MCF_INTC0_IPRH_INT55 (0x00800000) +#define MCF_INTC0_IPRH_INT56 (0x01000000) +#define MCF_INTC0_IPRH_INT57 (0x02000000) +#define MCF_INTC0_IPRH_INT58 (0x04000000) +#define MCF_INTC0_IPRH_INT59 (0x08000000) +#define MCF_INTC0_IPRH_INT60 (0x10000000) +#define MCF_INTC0_IPRH_INT61 (0x20000000) +#define MCF_INTC0_IPRH_INT62 (0x40000000) +#define MCF_INTC0_IPRH_INT63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC0_IPRL */ +#define MCF_INTC0_IPRL_INT1 (0x00000002) +#define MCF_INTC0_IPRL_INT2 (0x00000004) +#define MCF_INTC0_IPRL_INT3 (0x00000008) +#define MCF_INTC0_IPRL_INT4 (0x00000010) +#define MCF_INTC0_IPRL_INT5 (0x00000020) +#define MCF_INTC0_IPRL_INT6 (0x00000040) +#define MCF_INTC0_IPRL_INT7 (0x00000080) +#define MCF_INTC0_IPRL_INT8 (0x00000100) +#define MCF_INTC0_IPRL_INT9 (0x00000200) +#define MCF_INTC0_IPRL_INT10 (0x00000400) +#define MCF_INTC0_IPRL_INT11 (0x00000800) +#define MCF_INTC0_IPRL_INT12 (0x00001000) +#define MCF_INTC0_IPRL_INT13 (0x00002000) +#define MCF_INTC0_IPRL_INT14 (0x00004000) +#define MCF_INTC0_IPRL_INT15 (0x00008000) +#define MCF_INTC0_IPRL_INT16 (0x00010000) +#define MCF_INTC0_IPRL_INT17 (0x00020000) +#define MCF_INTC0_IPRL_INT18 (0x00040000) +#define MCF_INTC0_IPRL_INT19 (0x00080000) +#define MCF_INTC0_IPRL_INT20 (0x00100000) +#define MCF_INTC0_IPRL_INT21 (0x00200000) +#define MCF_INTC0_IPRL_INT22 (0x00400000) +#define MCF_INTC0_IPRL_INT23 (0x00800000) +#define MCF_INTC0_IPRL_INT24 (0x01000000) +#define MCF_INTC0_IPRL_INT25 (0x02000000) +#define MCF_INTC0_IPRL_INT26 (0x04000000) +#define MCF_INTC0_IPRL_INT27 (0x08000000) +#define MCF_INTC0_IPRL_INT28 (0x10000000) +#define MCF_INTC0_IPRL_INT29 (0x20000000) +#define MCF_INTC0_IPRL_INT30 (0x40000000) +#define MCF_INTC0_IPRL_INT31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC0_IMRH */ +#define MCF_INTC0_IMRH_INT_MASK32 (0x00000001) +#define MCF_INTC0_IMRH_INT_MASK33 (0x00000002) +#define MCF_INTC0_IMRH_INT_MASK34 (0x00000004) +#define MCF_INTC0_IMRH_INT_MASK35 (0x00000008) +#define MCF_INTC0_IMRH_INT_MASK36 (0x00000010) +#define MCF_INTC0_IMRH_INT_MASK37 (0x00000020) +#define MCF_INTC0_IMRH_INT_MASK38 (0x00000040) +#define MCF_INTC0_IMRH_INT_MASK39 (0x00000080) +#define MCF_INTC0_IMRH_INT_MASK40 (0x00000100) +#define MCF_INTC0_IMRH_INT_MASK41 (0x00000200) +#define MCF_INTC0_IMRH_INT_MASK42 (0x00000400) +#define MCF_INTC0_IMRH_INT_MASK43 (0x00000800) +#define MCF_INTC0_IMRH_INT_MASK44 (0x00001000) +#define MCF_INTC0_IMRH_INT_MASK45 (0x00002000) +#define MCF_INTC0_IMRH_INT_MASK46 (0x00004000) +#define MCF_INTC0_IMRH_INT_MASK47 (0x00008000) +#define MCF_INTC0_IMRH_INT_MASK48 (0x00010000) +#define MCF_INTC0_IMRH_INT_MASK49 (0x00020000) +#define MCF_INTC0_IMRH_INT_MASK50 (0x00040000) +#define MCF_INTC0_IMRH_INT_MASK51 (0x00080000) +#define MCF_INTC0_IMRH_INT_MASK52 (0x00100000) +#define MCF_INTC0_IMRH_INT_MASK53 (0x00200000) +#define MCF_INTC0_IMRH_INT_MASK54 (0x00400000) +#define MCF_INTC0_IMRH_INT_MASK55 (0x00800000) +#define MCF_INTC0_IMRH_INT_MASK56 (0x01000000) +#define MCF_INTC0_IMRH_INT_MASK57 (0x02000000) +#define MCF_INTC0_IMRH_INT_MASK58 (0x04000000) +#define MCF_INTC0_IMRH_INT_MASK59 (0x08000000) +#define MCF_INTC0_IMRH_INT_MASK60 (0x10000000) +#define MCF_INTC0_IMRH_INT_MASK61 (0x20000000) +#define MCF_INTC0_IMRH_INT_MASK62 (0x40000000) +#define MCF_INTC0_IMRH_INT_MASK63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC0_IMRL */ +#define MCF_INTC0_IMRL_MASKALL (0x00000001) +#define MCF_INTC0_IMRL_INT_MASK1 (0x00000002) +#define MCF_INTC0_IMRL_INT_MASK2 (0x00000004) +#define MCF_INTC0_IMRL_INT_MASK3 (0x00000008) +#define MCF_INTC0_IMRL_INT_MASK4 (0x00000010) +#define MCF_INTC0_IMRL_INT_MASK5 (0x00000020) +#define MCF_INTC0_IMRL_INT_MASK6 (0x00000040) +#define MCF_INTC0_IMRL_INT_MASK7 (0x00000080) +#define MCF_INTC0_IMRL_INT_MASK8 (0x00000100) +#define MCF_INTC0_IMRL_INT_MASK9 (0x00000200) +#define MCF_INTC0_IMRL_INT_MASK10 (0x00000400) +#define MCF_INTC0_IMRL_INT_MASK11 (0x00000800) +#define MCF_INTC0_IMRL_INT_MASK12 (0x00001000) +#define MCF_INTC0_IMRL_INT_MASK13 (0x00002000) +#define MCF_INTC0_IMRL_INT_MASK14 (0x00004000) +#define MCF_INTC0_IMRL_INT_MASK15 (0x00008000) +#define MCF_INTC0_IMRL_INT_MASK16 (0x00010000) +#define MCF_INTC0_IMRL_INT_MASK17 (0x00020000) +#define MCF_INTC0_IMRL_INT_MASK18 (0x00040000) +#define MCF_INTC0_IMRL_INT_MASK19 (0x00080000) +#define MCF_INTC0_IMRL_INT_MASK20 (0x00100000) +#define MCF_INTC0_IMRL_INT_MASK21 (0x00200000) +#define MCF_INTC0_IMRL_INT_MASK22 (0x00400000) +#define MCF_INTC0_IMRL_INT_MASK23 (0x00800000) +#define MCF_INTC0_IMRL_INT_MASK24 (0x01000000) +#define MCF_INTC0_IMRL_INT_MASK25 (0x02000000) +#define MCF_INTC0_IMRL_INT_MASK26 (0x04000000) +#define MCF_INTC0_IMRL_INT_MASK27 (0x08000000) +#define MCF_INTC0_IMRL_INT_MASK28 (0x10000000) +#define MCF_INTC0_IMRL_INT_MASK29 (0x20000000) +#define MCF_INTC0_IMRL_INT_MASK30 (0x40000000) +#define MCF_INTC0_IMRL_INT_MASK31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC0_INTFRCH */ +#define MCF_INTC0_INTFRCH_INTFRC32 (0x00000001) +#define MCF_INTC0_INTFRCH_INTFRC33 (0x00000002) +#define MCF_INTC0_INTFRCH_INTFRC34 (0x00000004) +#define MCF_INTC0_INTFRCH_INTFRC35 (0x00000008) +#define MCF_INTC0_INTFRCH_INTFRC36 (0x00000010) +#define MCF_INTC0_INTFRCH_INTFRC37 (0x00000020) +#define MCF_INTC0_INTFRCH_INTFRC38 (0x00000040) +#define MCF_INTC0_INTFRCH_INTFRC39 (0x00000080) +#define MCF_INTC0_INTFRCH_INTFRC40 (0x00000100) +#define MCF_INTC0_INTFRCH_INTFRC41 (0x00000200) +#define MCF_INTC0_INTFRCH_INTFRC42 (0x00000400) +#define MCF_INTC0_INTFRCH_INTFRC43 (0x00000800) +#define MCF_INTC0_INTFRCH_INTFRC44 (0x00001000) +#define MCF_INTC0_INTFRCH_INTFRC45 (0x00002000) +#define MCF_INTC0_INTFRCH_INTFRC46 (0x00004000) +#define MCF_INTC0_INTFRCH_INTFRC47 (0x00008000) +#define MCF_INTC0_INTFRCH_INTFRC48 (0x00010000) +#define MCF_INTC0_INTFRCH_INTFRC49 (0x00020000) +#define MCF_INTC0_INTFRCH_INTFRC50 (0x00040000) +#define MCF_INTC0_INTFRCH_INTFRC51 (0x00080000) +#define MCF_INTC0_INTFRCH_INTFRC52 (0x00100000) +#define MCF_INTC0_INTFRCH_INTFRC53 (0x00200000) +#define MCF_INTC0_INTFRCH_INTFRC54 (0x00400000) +#define MCF_INTC0_INTFRCH_INTFRC55 (0x00800000) +#define MCF_INTC0_INTFRCH_INTFRC56 (0x01000000) +#define MCF_INTC0_INTFRCH_INTFRC57 (0x02000000) +#define MCF_INTC0_INTFRCH_INTFRC58 (0x04000000) +#define MCF_INTC0_INTFRCH_INTFRC59 (0x08000000) +#define MCF_INTC0_INTFRCH_INTFRC60 (0x10000000) +#define MCF_INTC0_INTFRCH_INTFRC61 (0x20000000) +#define MCF_INTC0_INTFRCH_INTFRC62 (0x40000000) +#define MCF_INTC0_INTFRCH_INTFRC63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC0_INTFRCL */ +#define MCF_INTC0_INTFRCL_INTFRC1 (0x00000002) +#define MCF_INTC0_INTFRCL_INTFRC2 (0x00000004) +#define MCF_INTC0_INTFRCL_INTFRC3 (0x00000008) +#define MCF_INTC0_INTFRCL_INTFRC4 (0x00000010) +#define MCF_INTC0_INTFRCL_INTFRC5 (0x00000020) +#define MCF_INTC0_INTFRCL_INT6 (0x00000040) +#define MCF_INTC0_INTFRCL_INT7 (0x00000080) +#define MCF_INTC0_INTFRCL_INT8 (0x00000100) +#define MCF_INTC0_INTFRCL_INT9 (0x00000200) +#define MCF_INTC0_INTFRCL_INT10 (0x00000400) +#define MCF_INTC0_INTFRCL_INTFRC11 (0x00000800) +#define MCF_INTC0_INTFRCL_INTFRC12 (0x00001000) +#define MCF_INTC0_INTFRCL_INTFRC13 (0x00002000) +#define MCF_INTC0_INTFRCL_INTFRC14 (0x00004000) +#define MCF_INTC0_INTFRCL_INT15 (0x00008000) +#define MCF_INTC0_INTFRCL_INTFRC16 (0x00010000) +#define MCF_INTC0_INTFRCL_INTFRC17 (0x00020000) +#define MCF_INTC0_INTFRCL_INTFRC18 (0x00040000) +#define MCF_INTC0_INTFRCL_INTFRC19 (0x00080000) +#define MCF_INTC0_INTFRCL_INTFRC20 (0x00100000) +#define MCF_INTC0_INTFRCL_INTFRC21 (0x00200000) +#define MCF_INTC0_INTFRCL_INTFRC22 (0x00400000) +#define MCF_INTC0_INTFRCL_INTFRC23 (0x00800000) +#define MCF_INTC0_INTFRCL_INTFRC24 (0x01000000) +#define MCF_INTC0_INTFRCL_INTFRC25 (0x02000000) +#define MCF_INTC0_INTFRCL_INTFRC26 (0x04000000) +#define MCF_INTC0_INTFRCL_INTFRC27 (0x08000000) +#define MCF_INTC0_INTFRCL_INTFRC28 (0x10000000) +#define MCF_INTC0_INTFRCL_INTFRC29 (0x20000000) +#define MCF_INTC0_INTFRCL_INTFRC30 (0x40000000) +#define MCF_INTC0_INTFRCL_INTFRC31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC0_IRLR */ +#define MCF_INTC0_IRLR_IRQ(x) (((x)&0x7F)<<1) + +/* Bit definitions and macros for MCF_INTC0_IACKLPR */ +#define MCF_INTC0_IACKLPR_PRI(x) (((x)&0x0F)<<0) +#define MCF_INTC0_IACKLPR_LEVEL(x) (((x)&0x07)<<4) + +/* Bit definitions and macros for MCF_INTC0_ICRn */ +#define MCF_INTC0_ICRn_IP(x) (((x)&0x07)<<0) +#define MCF_INTC0_ICRn_IL(x) (((x)&0x07)<<3) + +/********************************************************************/ + +#endif /* __MCF523X_INTC0_H__ */ diff --git a/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_intc1.h b/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_intc1.h new file mode 100644 index 000000000..7e8972c07 --- /dev/null +++ b/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_intc1.h @@ -0,0 +1,323 @@ +/* + * These files are taken from the MCF523X source code example package + * which is available on the Freescale website. Freescale explicitly + * grants the redistribution and modification of these source files. + * The complete licensing information is available in the file + * LICENSE_FREESCALE.TXT. + * + * File: mcf523x_intc1.h + * Purpose: Register and bit definitions for the MCF523X + * + * Notes: + * + */ + +#ifndef __MCF523X_INTC1_H__ +#define __MCF523X_INTC1_H__ + +/********************************************************************* +* +* Interrupt Controller 1 (INTC1) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_INTC1_IPRH (*(vuint32*)(void*)(&__IPSBAR[0x000D00])) +#define MCF_INTC1_IPRL (*(vuint32*)(void*)(&__IPSBAR[0x000D04])) +#define MCF_INTC1_IMRH (*(vuint32*)(void*)(&__IPSBAR[0x000D08])) +#define MCF_INTC1_IMRL (*(vuint32*)(void*)(&__IPSBAR[0x000D0C])) +#define MCF_INTC1_INTFRCH (*(vuint32*)(void*)(&__IPSBAR[0x000D10])) +#define MCF_INTC1_INTFRCL (*(vuint32*)(void*)(&__IPSBAR[0x000D14])) +#define MCF_INTC1_IRLR (*(vuint8 *)(void*)(&__IPSBAR[0x000D18])) +#define MCF_INTC1_IACKLPR (*(vuint8 *)(void*)(&__IPSBAR[0x000D19])) +#define MCF_INTC1_ICR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000D40])) +#define MCF_INTC1_ICR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000D41])) +#define MCF_INTC1_ICR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000D42])) +#define MCF_INTC1_ICR3 (*(vuint8 *)(void*)(&__IPSBAR[0x000D43])) +#define MCF_INTC1_ICR4 (*(vuint8 *)(void*)(&__IPSBAR[0x000D44])) +#define MCF_INTC1_ICR5 (*(vuint8 *)(void*)(&__IPSBAR[0x000D45])) +#define MCF_INTC1_ICR6 (*(vuint8 *)(void*)(&__IPSBAR[0x000D46])) +#define MCF_INTC1_ICR7 (*(vuint8 *)(void*)(&__IPSBAR[0x000D47])) +#define MCF_INTC1_ICR8 (*(vuint8 *)(void*)(&__IPSBAR[0x000D48])) +#define MCF_INTC1_ICR9 (*(vuint8 *)(void*)(&__IPSBAR[0x000D49])) +#define MCF_INTC1_ICR10 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4A])) +#define MCF_INTC1_ICR11 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4B])) +#define MCF_INTC1_ICR12 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4C])) +#define MCF_INTC1_ICR13 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4D])) +#define MCF_INTC1_ICR14 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4E])) +#define MCF_INTC1_ICR15 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4F])) +#define MCF_INTC1_ICR16 (*(vuint8 *)(void*)(&__IPSBAR[0x000D50])) +#define MCF_INTC1_ICR17 (*(vuint8 *)(void*)(&__IPSBAR[0x000D51])) +#define MCF_INTC1_ICR18 (*(vuint8 *)(void*)(&__IPSBAR[0x000D52])) +#define MCF_INTC1_ICR19 (*(vuint8 *)(void*)(&__IPSBAR[0x000D53])) +#define MCF_INTC1_ICR20 (*(vuint8 *)(void*)(&__IPSBAR[0x000D54])) +#define MCF_INTC1_ICR21 (*(vuint8 *)(void*)(&__IPSBAR[0x000D55])) +#define MCF_INTC1_ICR22 (*(vuint8 *)(void*)(&__IPSBAR[0x000D56])) +#define MCF_INTC1_ICR23 (*(vuint8 *)(void*)(&__IPSBAR[0x000D57])) +#define MCF_INTC1_ICR24 (*(vuint8 *)(void*)(&__IPSBAR[0x000D58])) +#define MCF_INTC1_ICR25 (*(vuint8 *)(void*)(&__IPSBAR[0x000D59])) +#define MCF_INTC1_ICR26 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5A])) +#define MCF_INTC1_ICR27 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5B])) +#define MCF_INTC1_ICR28 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5C])) +#define MCF_INTC1_ICR29 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5D])) +#define MCF_INTC1_ICR30 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5E])) +#define MCF_INTC1_ICR31 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5F])) +#define MCF_INTC1_ICR32 (*(vuint8 *)(void*)(&__IPSBAR[0x000D60])) +#define MCF_INTC1_ICR33 (*(vuint8 *)(void*)(&__IPSBAR[0x000D61])) +#define MCF_INTC1_ICR34 (*(vuint8 *)(void*)(&__IPSBAR[0x000D62])) +#define MCF_INTC1_ICR35 (*(vuint8 *)(void*)(&__IPSBAR[0x000D63])) +#define MCF_INTC1_ICR36 (*(vuint8 *)(void*)(&__IPSBAR[0x000D64])) +#define MCF_INTC1_ICR37 (*(vuint8 *)(void*)(&__IPSBAR[0x000D65])) +#define MCF_INTC1_ICR38 (*(vuint8 *)(void*)(&__IPSBAR[0x000D66])) +#define MCF_INTC1_ICR39 (*(vuint8 *)(void*)(&__IPSBAR[0x000D67])) +#define MCF_INTC1_ICR40 (*(vuint8 *)(void*)(&__IPSBAR[0x000D68])) +#define MCF_INTC1_ICR41 (*(vuint8 *)(void*)(&__IPSBAR[0x000D69])) +#define MCF_INTC1_ICR42 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6A])) +#define MCF_INTC1_ICR43 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6B])) +#define MCF_INTC1_ICR44 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6C])) +#define MCF_INTC1_ICR45 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6D])) +#define MCF_INTC1_ICR46 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6E])) +#define MCF_INTC1_ICR47 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6F])) +#define MCF_INTC1_ICR48 (*(vuint8 *)(void*)(&__IPSBAR[0x000D70])) +#define MCF_INTC1_ICR49 (*(vuint8 *)(void*)(&__IPSBAR[0x000D71])) +#define MCF_INTC1_ICR50 (*(vuint8 *)(void*)(&__IPSBAR[0x000D72])) +#define MCF_INTC1_ICR51 (*(vuint8 *)(void*)(&__IPSBAR[0x000D73])) +#define MCF_INTC1_ICR52 (*(vuint8 *)(void*)(&__IPSBAR[0x000D74])) +#define MCF_INTC1_ICR53 (*(vuint8 *)(void*)(&__IPSBAR[0x000D75])) +#define MCF_INTC1_ICR54 (*(vuint8 *)(void*)(&__IPSBAR[0x000D76])) +#define MCF_INTC1_ICR55 (*(vuint8 *)(void*)(&__IPSBAR[0x000D77])) +#define MCF_INTC1_ICR56 (*(vuint8 *)(void*)(&__IPSBAR[0x000D78])) +#define MCF_INTC1_ICR57 (*(vuint8 *)(void*)(&__IPSBAR[0x000D79])) +#define MCF_INTC1_ICR58 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7A])) +#define MCF_INTC1_ICR59 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7B])) +#define MCF_INTC1_ICR60 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7C])) +#define MCF_INTC1_ICR61 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7D])) +#define MCF_INTC1_ICR62 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7E])) +#define MCF_INTC1_ICR63 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7F])) +#define MCF_INTC1_ICRn(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000D40+((x)*0x001)])) +#define MCF_INTC1_SWIACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DE0])) +#define MCF_INTC1_L1IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DE4])) +#define MCF_INTC1_L2IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DE8])) +#define MCF_INTC1_L3IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DEC])) +#define MCF_INTC1_L4IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DF0])) +#define MCF_INTC1_L5IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DF4])) +#define MCF_INTC1_L6IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DF8])) +#define MCF_INTC1_L7IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DFC])) +#define MCF_INTC1_LnIACK(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000DE4+((x)*0x004)])) + +/* Bit definitions and macros for MCF_INTC1_IPRH */ +#define MCF_INTC1_IPRH_INT32 (0x00000001) +#define MCF_INTC1_IPRH_INT33 (0x00000002) +#define MCF_INTC1_IPRH_INT34 (0x00000004) +#define MCF_INTC1_IPRH_INT35 (0x00000008) +#define MCF_INTC1_IPRH_INT36 (0x00000010) +#define MCF_INTC1_IPRH_INT37 (0x00000020) +#define MCF_INTC1_IPRH_INT38 (0x00000040) +#define MCF_INTC1_IPRH_INT39 (0x00000080) +#define MCF_INTC1_IPRH_INT40 (0x00000100) +#define MCF_INTC1_IPRH_INT41 (0x00000200) +#define MCF_INTC1_IPRH_INT42 (0x00000400) +#define MCF_INTC1_IPRH_INT43 (0x00000800) +#define MCF_INTC1_IPRH_INT44 (0x00001000) +#define MCF_INTC1_IPRH_INT45 (0x00002000) +#define MCF_INTC1_IPRH_INT46 (0x00004000) +#define MCF_INTC1_IPRH_INT47 (0x00008000) +#define MCF_INTC1_IPRH_INT48 (0x00010000) +#define MCF_INTC1_IPRH_INT49 (0x00020000) +#define MCF_INTC1_IPRH_INT50 (0x00040000) +#define MCF_INTC1_IPRH_INT51 (0x00080000) +#define MCF_INTC1_IPRH_INT52 (0x00100000) +#define MCF_INTC1_IPRH_INT53 (0x00200000) +#define MCF_INTC1_IPRH_INT54 (0x00400000) +#define MCF_INTC1_IPRH_INT55 (0x00800000) +#define MCF_INTC1_IPRH_INT56 (0x01000000) +#define MCF_INTC1_IPRH_INT57 (0x02000000) +#define MCF_INTC1_IPRH_INT58 (0x04000000) +#define MCF_INTC1_IPRH_INT59 (0x08000000) +#define MCF_INTC1_IPRH_INT60 (0x10000000) +#define MCF_INTC1_IPRH_INT61 (0x20000000) +#define MCF_INTC1_IPRH_INT62 (0x40000000) +#define MCF_INTC1_IPRH_INT63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC1_IPRL */ +#define MCF_INTC1_IPRL_INT1 (0x00000002) +#define MCF_INTC1_IPRL_INT2 (0x00000004) +#define MCF_INTC1_IPRL_INT3 (0x00000008) +#define MCF_INTC1_IPRL_INT4 (0x00000010) +#define MCF_INTC1_IPRL_INT5 (0x00000020) +#define MCF_INTC1_IPRL_INT6 (0x00000040) +#define MCF_INTC1_IPRL_INT7 (0x00000080) +#define MCF_INTC1_IPRL_INT8 (0x00000100) +#define MCF_INTC1_IPRL_INT9 (0x00000200) +#define MCF_INTC1_IPRL_INT10 (0x00000400) +#define MCF_INTC1_IPRL_INT11 (0x00000800) +#define MCF_INTC1_IPRL_INT12 (0x00001000) +#define MCF_INTC1_IPRL_INT13 (0x00002000) +#define MCF_INTC1_IPRL_INT14 (0x00004000) +#define MCF_INTC1_IPRL_INT15 (0x00008000) +#define MCF_INTC1_IPRL_INT16 (0x00010000) +#define MCF_INTC1_IPRL_INT17 (0x00020000) +#define MCF_INTC1_IPRL_INT18 (0x00040000) +#define MCF_INTC1_IPRL_INT19 (0x00080000) +#define MCF_INTC1_IPRL_INT20 (0x00100000) +#define MCF_INTC1_IPRL_INT21 (0x00200000) +#define MCF_INTC1_IPRL_INT22 (0x00400000) +#define MCF_INTC1_IPRL_INT23 (0x00800000) +#define MCF_INTC1_IPRL_INT24 (0x01000000) +#define MCF_INTC1_IPRL_INT25 (0x02000000) +#define MCF_INTC1_IPRL_INT26 (0x04000000) +#define MCF_INTC1_IPRL_INT27 (0x08000000) +#define MCF_INTC1_IPRL_INT28 (0x10000000) +#define MCF_INTC1_IPRL_INT29 (0x20000000) +#define MCF_INTC1_IPRL_INT30 (0x40000000) +#define MCF_INTC1_IPRL_INT31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC1_IMRH */ +#define MCF_INTC1_IMRH_INT_MASK32 (0x00000001) +#define MCF_INTC1_IMRH_INT_MASK33 (0x00000002) +#define MCF_INTC1_IMRH_INT_MASK34 (0x00000004) +#define MCF_INTC1_IMRH_INT_MASK35 (0x00000008) +#define MCF_INTC1_IMRH_INT_MASK36 (0x00000010) +#define MCF_INTC1_IMRH_INT_MASK37 (0x00000020) +#define MCF_INTC1_IMRH_INT_MASK38 (0x00000040) +#define MCF_INTC1_IMRH_INT_MASK39 (0x00000080) +#define MCF_INTC1_IMRH_INT_MASK40 (0x00000100) +#define MCF_INTC1_IMRH_INT_MASK41 (0x00000200) +#define MCF_INTC1_IMRH_INT_MASK42 (0x00000400) +#define MCF_INTC1_IMRH_INT_MASK43 (0x00000800) +#define MCF_INTC1_IMRH_INT_MASK44 (0x00001000) +#define MCF_INTC1_IMRH_INT_MASK45 (0x00002000) +#define MCF_INTC1_IMRH_INT_MASK46 (0x00004000) +#define MCF_INTC1_IMRH_INT_MASK47 (0x00008000) +#define MCF_INTC1_IMRH_INT_MASK48 (0x00010000) +#define MCF_INTC1_IMRH_INT_MASK49 (0x00020000) +#define MCF_INTC1_IMRH_INT_MASK50 (0x00040000) +#define MCF_INTC1_IMRH_INT_MASK51 (0x00080000) +#define MCF_INTC1_IMRH_INT_MASK52 (0x00100000) +#define MCF_INTC1_IMRH_INT_MASK53 (0x00200000) +#define MCF_INTC1_IMRH_INT_MASK54 (0x00400000) +#define MCF_INTC1_IMRH_INT_MASK55 (0x00800000) +#define MCF_INTC1_IMRH_INT_MASK56 (0x01000000) +#define MCF_INTC1_IMRH_INT_MASK57 (0x02000000) +#define MCF_INTC1_IMRH_INT_MASK58 (0x04000000) +#define MCF_INTC1_IMRH_INT_MASK59 (0x08000000) +#define MCF_INTC1_IMRH_INT_MASK60 (0x10000000) +#define MCF_INTC1_IMRH_INT_MASK61 (0x20000000) +#define MCF_INTC1_IMRH_INT_MASK62 (0x40000000) +#define MCF_INTC1_IMRH_INT_MASK63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC1_IMRL */ +#define MCF_INTC1_IMRL_MASKALL (0x00000001) +#define MCF_INTC1_IMRL_INT_MASK1 (0x00000002) +#define MCF_INTC1_IMRL_INT_MASK2 (0x00000004) +#define MCF_INTC1_IMRL_INT_MASK3 (0x00000008) +#define MCF_INTC1_IMRL_INT_MASK4 (0x00000010) +#define MCF_INTC1_IMRL_INT_MASK5 (0x00000020) +#define MCF_INTC1_IMRL_INT_MASK6 (0x00000040) +#define MCF_INTC1_IMRL_INT_MASK7 (0x00000080) +#define MCF_INTC1_IMRL_INT_MASK8 (0x00000100) +#define MCF_INTC1_IMRL_INT_MASK9 (0x00000200) +#define MCF_INTC1_IMRL_INT_MASK10 (0x00000400) +#define MCF_INTC1_IMRL_INT_MASK11 (0x00000800) +#define MCF_INTC1_IMRL_INT_MASK12 (0x00001000) +#define MCF_INTC1_IMRL_INT_MASK13 (0x00002000) +#define MCF_INTC1_IMRL_INT_MASK14 (0x00004000) +#define MCF_INTC1_IMRL_INT_MASK15 (0x00008000) +#define MCF_INTC1_IMRL_INT_MASK16 (0x00010000) +#define MCF_INTC1_IMRL_INT_MASK17 (0x00020000) +#define MCF_INTC1_IMRL_INT_MASK18 (0x00040000) +#define MCF_INTC1_IMRL_INT_MASK19 (0x00080000) +#define MCF_INTC1_IMRL_INT_MASK20 (0x00100000) +#define MCF_INTC1_IMRL_INT_MASK21 (0x00200000) +#define MCF_INTC1_IMRL_INT_MASK22 (0x00400000) +#define MCF_INTC1_IMRL_INT_MASK23 (0x00800000) +#define MCF_INTC1_IMRL_INT_MASK24 (0x01000000) +#define MCF_INTC1_IMRL_INT_MASK25 (0x02000000) +#define MCF_INTC1_IMRL_INT_MASK26 (0x04000000) +#define MCF_INTC1_IMRL_INT_MASK27 (0x08000000) +#define MCF_INTC1_IMRL_INT_MASK28 (0x10000000) +#define MCF_INTC1_IMRL_INT_MASK29 (0x20000000) +#define MCF_INTC1_IMRL_INT_MASK30 (0x40000000) +#define MCF_INTC1_IMRL_INT_MASK31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC1_INTFRCH */ +#define MCF_INTC1_INTFRCH_INTFRC32 (0x00000001) +#define MCF_INTC1_INTFRCH_INTFRC33 (0x00000002) +#define MCF_INTC1_INTFRCH_INTFRC34 (0x00000004) +#define MCF_INTC1_INTFRCH_INTFRC35 (0x00000008) +#define MCF_INTC1_INTFRCH_INTFRC36 (0x00000010) +#define MCF_INTC1_INTFRCH_INTFRC37 (0x00000020) +#define MCF_INTC1_INTFRCH_INTFRC38 (0x00000040) +#define MCF_INTC1_INTFRCH_INTFRC39 (0x00000080) +#define MCF_INTC1_INTFRCH_INTFRC40 (0x00000100) +#define MCF_INTC1_INTFRCH_INTFRC41 (0x00000200) +#define MCF_INTC1_INTFRCH_INTFRC42 (0x00000400) +#define MCF_INTC1_INTFRCH_INTFRC43 (0x00000800) +#define MCF_INTC1_INTFRCH_INTFRC44 (0x00001000) +#define MCF_INTC1_INTFRCH_INTFRC45 (0x00002000) +#define MCF_INTC1_INTFRCH_INTFRC46 (0x00004000) +#define MCF_INTC1_INTFRCH_INTFRC47 (0x00008000) +#define MCF_INTC1_INTFRCH_INTFRC48 (0x00010000) +#define MCF_INTC1_INTFRCH_INTFRC49 (0x00020000) +#define MCF_INTC1_INTFRCH_INTFRC50 (0x00040000) +#define MCF_INTC1_INTFRCH_INTFRC51 (0x00080000) +#define MCF_INTC1_INTFRCH_INTFRC52 (0x00100000) +#define MCF_INTC1_INTFRCH_INTFRC53 (0x00200000) +#define MCF_INTC1_INTFRCH_INTFRC54 (0x00400000) +#define MCF_INTC1_INTFRCH_INTFRC55 (0x00800000) +#define MCF_INTC1_INTFRCH_INTFRC56 (0x01000000) +#define MCF_INTC1_INTFRCH_INTFRC57 (0x02000000) +#define MCF_INTC1_INTFRCH_INTFRC58 (0x04000000) +#define MCF_INTC1_INTFRCH_INTFRC59 (0x08000000) +#define MCF_INTC1_INTFRCH_INTFRC60 (0x10000000) +#define MCF_INTC1_INTFRCH_INTFRC61 (0x20000000) +#define MCF_INTC1_INTFRCH_INTFRC62 (0x40000000) +#define MCF_INTC1_INTFRCH_INTFRC63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC1_INTFRCL */ +#define MCF_INTC1_INTFRCL_INTFRC1 (0x00000002) +#define MCF_INTC1_INTFRCL_INTFRC2 (0x00000004) +#define MCF_INTC1_INTFRCL_INTFRC3 (0x00000008) +#define MCF_INTC1_INTFRCL_INTFRC4 (0x00000010) +#define MCF_INTC1_INTFRCL_INTFRC5 (0x00000020) +#define MCF_INTC1_INTFRCL_INT6 (0x00000040) +#define MCF_INTC1_INTFRCL_INT7 (0x00000080) +#define MCF_INTC1_INTFRCL_INT8 (0x00000100) +#define MCF_INTC1_INTFRCL_INT9 (0x00000200) +#define MCF_INTC1_INTFRCL_INT10 (0x00000400) +#define MCF_INTC1_INTFRCL_INTFRC11 (0x00000800) +#define MCF_INTC1_INTFRCL_INTFRC12 (0x00001000) +#define MCF_INTC1_INTFRCL_INTFRC13 (0x00002000) +#define MCF_INTC1_INTFRCL_INTFRC14 (0x00004000) +#define MCF_INTC1_INTFRCL_INT15 (0x00008000) +#define MCF_INTC1_INTFRCL_INTFRC16 (0x00010000) +#define MCF_INTC1_INTFRCL_INTFRC17 (0x00020000) +#define MCF_INTC1_INTFRCL_INTFRC18 (0x00040000) +#define MCF_INTC1_INTFRCL_INTFRC19 (0x00080000) +#define MCF_INTC1_INTFRCL_INTFRC20 (0x00100000) +#define MCF_INTC1_INTFRCL_INTFRC21 (0x00200000) +#define MCF_INTC1_INTFRCL_INTFRC22 (0x00400000) +#define MCF_INTC1_INTFRCL_INTFRC23 (0x00800000) +#define MCF_INTC1_INTFRCL_INTFRC24 (0x01000000) +#define MCF_INTC1_INTFRCL_INTFRC25 (0x02000000) +#define MCF_INTC1_INTFRCL_INTFRC26 (0x04000000) +#define MCF_INTC1_INTFRCL_INTFRC27 (0x08000000) +#define MCF_INTC1_INTFRCL_INTFRC28 (0x10000000) +#define MCF_INTC1_INTFRCL_INTFRC29 (0x20000000) +#define MCF_INTC1_INTFRCL_INTFRC30 (0x40000000) +#define MCF_INTC1_INTFRCL_INTFRC31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC1_IRLR */ +#define MCF_INTC1_IRLR_IRQ(x) (((x)&0x7F)<<1) + +/* Bit definitions and macros for MCF_INTC1_IACKLPR */ +#define MCF_INTC1_IACKLPR_PRI(x) (((x)&0x0F)<<0) +#define MCF_INTC1_IACKLPR_LEVEL(x) (((x)&0x07)<<4) + +/* Bit definitions and macros for MCF_INTC1_ICRn */ +#define MCF_INTC1_ICRn_IP(x) (((x)&0x07)<<0) +#define MCF_INTC1_ICRn_IL(x) (((x)&0x07)<<3) + +/********************************************************************/ + +#endif /* __MCF523X_INTC1_H__ */ diff --git a/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_mdha.h b/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_mdha.h new file mode 100644 index 000000000..cc2ff2710 --- /dev/null +++ b/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_mdha.h @@ -0,0 +1,101 @@ +/* + * These files are taken from the MCF523X source code example package + * which is available on the Freescale website. Freescale explicitly + * grants the redistribution and modification of these source files. + * The complete licensing information is available in the file + * LICENSE_FREESCALE.TXT. + * + * File: mcf523x_mdha.h + * Purpose: Register and bit definitions for the MCF523X + * + * Notes: + * + */ + +#ifndef __MCF523X_MDHA_H__ +#define __MCF523X_MDHA_H__ + +/********************************************************************* +* +* Message Digest Hardware Accelerator (MDHA) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_MDHA_MDMR (*(vuint32*)(void*)(&__IPSBAR[0x190000])) +#define MCF_MDHA_MDCR (*(vuint32*)(void*)(&__IPSBAR[0x190004])) +#define MCF_MDHA_MDCMR (*(vuint32*)(void*)(&__IPSBAR[0x190008])) +#define MCF_MDHA_MDSR (*(vuint32*)(void*)(&__IPSBAR[0x19000C])) +#define MCF_MDHA_MDISR (*(vuint32*)(void*)(&__IPSBAR[0x190010])) +#define MCF_MDHA_MDIMR (*(vuint32*)(void*)(&__IPSBAR[0x190014])) +#define MCF_MDHA_MDDSR (*(vuint32*)(void*)(&__IPSBAR[0x19001C])) +#define MCF_MDHA_MDIN (*(vuint32*)(void*)(&__IPSBAR[0x190020])) +#define MCF_MDHA_MDA0 (*(vuint32*)(void*)(&__IPSBAR[0x190030])) +#define MCF_MDHA_MDB0 (*(vuint32*)(void*)(&__IPSBAR[0x190034])) +#define MCF_MDHA_MDC0 (*(vuint32*)(void*)(&__IPSBAR[0x190038])) +#define MCF_MDHA_MDD0 (*(vuint32*)(void*)(&__IPSBAR[0x19003C])) +#define MCF_MDHA_MDE0 (*(vuint32*)(void*)(&__IPSBAR[0x190040])) +#define MCF_MDHA_MDMDS (*(vuint32*)(void*)(&__IPSBAR[0x190044])) +#define MCF_MDHA_MDA1 (*(vuint32*)(void*)(&__IPSBAR[0x190070])) +#define MCF_MDHA_MDB1 (*(vuint32*)(void*)(&__IPSBAR[0x190074])) +#define MCF_MDHA_MDC1 (*(vuint32*)(void*)(&__IPSBAR[0x190078])) +#define MCF_MDHA_MDD1 (*(vuint32*)(void*)(&__IPSBAR[0x19007C])) +#define MCF_MDHA_MDE1 (*(vuint32*)(void*)(&__IPSBAR[0x190080])) + +/* Bit definitions and macros for MCF_MDHA_MDMR */ +#define MCF_MDHA_MDMR_ALG (0x00000001) +#define MCF_MDHA_MDMR_PDATA (0x00000004) +#define MCF_MDHA_MDMR_MAC(x) (((x)&0x00000003)<<3) +#define MCF_MDHA_MDMR_INIT (0x00000020) +#define MCF_MDHA_MDMR_IPAD (0x00000040) +#define MCF_MDHA_MDMR_OPAD (0x00000080) +#define MCF_MDHA_MDMR_SWAP (0x00000100) +#define MCF_MDHA_MDMR_MACFULL (0x00000200) +#define MCF_MDHA_MDMR_SSL (0x00000400) + +/* Bit definitions and macros for MCF_MDHA_MDCR */ +#define MCF_MDHA_MDCR_IE (0x00000001) + +/* Bit definitions and macros for MCF_MDHA_MDCMR */ +#define MCF_MDHA_MDCMR_SWR (0x00000001) +#define MCF_MDHA_MDCMR_RI (0x00000002) +#define MCF_MDHA_MDCMR_CI (0x00000004) +#define MCF_MDHA_MDCMR_GO (0x00000008) + +/* Bit definitions and macros for MCF_MDHA_MDSR */ +#define MCF_MDHA_MDSR_INT (0x00000001) +#define MCF_MDHA_MDSR_DONE (0x00000002) +#define MCF_MDHA_MDSR_ERR (0x00000004) +#define MCF_MDHA_MDSR_RD (0x00000008) +#define MCF_MDHA_MDSR_BUSY (0x00000010) +#define MCF_MDHA_MDSR_END (0x00000020) +#define MCF_MDHA_MDSR_HSH (0x00000040) +#define MCF_MDHA_MDSR_GNW (0x00000080) +#define MCF_MDHA_MDSR_FS(x) (((x)&0x00000007)<<8) +#define MCF_MDHA_MDSR_APD(x) (((x)&0x00000007)<<13) +#define MCF_MDHA_MDSR_IFL(x) (((x)&0x000000FF)<<16) + +/* Bit definitions and macros for MCF_MDHA_MDIR */ +#define MCF_MDHA_MDIR_IFO (0x00000001) +#define MCF_MDHA_MDIR_NON (0x00000004) +#define MCF_MDHA_MDIR_IME (0x00000010) +#define MCF_MDHA_MDIR_IDS (0x00000020) +#define MCF_MDHA_MDIR_RMDP (0x00000080) +#define MCF_MDHA_MDIR_ERE (0x00000100) +#define MCF_MDHA_MDIR_GTDS (0x00000200) + +/* Bit definitions and macros for MCF_MDHA_MDIMR */ +#define MCF_MDHA_MDIMR_IFO (0x00000001) +#define MCF_MDHA_MDIMR_NON (0x00000004) +#define MCF_MDHA_MDIMR_IME (0x00000010) +#define MCF_MDHA_MDIMR_IDS (0x00000020) +#define MCF_MDHA_MDIMR_RMDP (0x00000080) +#define MCF_MDHA_MDIMR_ERE (0x00000100) +#define MCF_MDHA_MDIMR_GTDS (0x00000200) + +/* Bit definitions and macros for MCF_MDHA_MDDSR */ +#define MCF_MDHA_MDDSR_DATASIZE(x) (((x)&0x1FFFFFFF)<<0) + +/********************************************************************/ + +#endif /* __MCF523X_MDHA_H__ */ diff --git a/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_pit.h b/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_pit.h new file mode 100644 index 000000000..a3798f070 --- /dev/null +++ b/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_pit.h @@ -0,0 +1,89 @@ +/* + * These files are taken from the MCF523X source code example package + * which is available on the Freescale website. Freescale explicitly + * grants the redistribution and modification of these source files. + * The complete licensing information is available in the file + * LICENSE_FREESCALE.TXT. + * + * File: mcf523x_pit.h + * Purpose: Register and bit definitions for the MCF523X + * + * Notes: + * + */ + +#ifndef __MCF523X_PIT_H__ +#define __MCF523X_PIT_H__ + +/********************************************************************* +* +* Programmable Interrupt Timer Modules (PIT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PIT_PCSR0 (*(vuint16*)(void*)(&__IPSBAR[0x150000])) +#define MCF_PIT_PMR0 (*(vuint16*)(void*)(&__IPSBAR[0x150002])) +#define MCF_PIT_PCNTR0 (*(vuint16*)(void*)(&__IPSBAR[0x150004])) +#define MCF_PIT_PCSR1 (*(vuint16*)(void*)(&__IPSBAR[0x160000])) +#define MCF_PIT_PMR1 (*(vuint16*)(void*)(&__IPSBAR[0x160002])) +#define MCF_PIT_PCNTR1 (*(vuint16*)(void*)(&__IPSBAR[0x160004])) +#define MCF_PIT_PCSR2 (*(vuint16*)(void*)(&__IPSBAR[0x170000])) +#define MCF_PIT_PMR2 (*(vuint16*)(void*)(&__IPSBAR[0x170002])) +#define MCF_PIT_PCNTR2 (*(vuint16*)(void*)(&__IPSBAR[0x170004])) +#define MCF_PIT_PCSR3 (*(vuint16*)(void*)(&__IPSBAR[0x180000])) +#define MCF_PIT_PMR3 (*(vuint16*)(void*)(&__IPSBAR[0x180002])) +#define MCF_PIT_PCNTR3 (*(vuint16*)(void*)(&__IPSBAR[0x180004])) +#define MCF_PIT_PCSR(x) (*(vuint16*)(void*)(&__IPSBAR[0x150000+((x)*0x10000)])) +#define MCF_PIT_PMR(x) (*(vuint16*)(void*)(&__IPSBAR[0x150002+((x)*0x10000)])) +#define MCF_PIT_PCNTR(x) (*(vuint16*)(void*)(&__IPSBAR[0x150004+((x)*0x10000)])) + +/* Bit definitions and macros for MCF_PIT_PCSR */ +#define MCF_PIT_PCSR_EN (0x0001) +#define MCF_PIT_PCSR_RLD (0x0002) +#define MCF_PIT_PCSR_PIF (0x0004) +#define MCF_PIT_PCSR_PIE (0x0008) +#define MCF_PIT_PCSR_OVW (0x0010) +#define MCF_PIT_PCSR_HALTED (0x0020) +#define MCF_PIT_PCSR_DOZE (0x0040) +#define MCF_PIT_PCSR_PRE(x) (((x)&0x000F)<<8) + +/* Bit definitions and macros for MCF_PIT_PMR */ +#define MCF_PIT_PMR_PM0 (0x0001) +#define MCF_PIT_PMR_PM1 (0x0002) +#define MCF_PIT_PMR_PM2 (0x0004) +#define MCF_PIT_PMR_PM3 (0x0008) +#define MCF_PIT_PMR_PM4 (0x0010) +#define MCF_PIT_PMR_PM5 (0x0020) +#define MCF_PIT_PMR_PM6 (0x0040) +#define MCF_PIT_PMR_PM7 (0x0080) +#define MCF_PIT_PMR_PM8 (0x0100) +#define MCF_PIT_PMR_PM9 (0x0200) +#define MCF_PIT_PMR_PM10 (0x0400) +#define MCF_PIT_PMR_PM11 (0x0800) +#define MCF_PIT_PMR_PM12 (0x1000) +#define MCF_PIT_PMR_PM13 (0x2000) +#define MCF_PIT_PMR_PM14 (0x4000) +#define MCF_PIT_PMR_PM15 (0x8000) + +/* Bit definitions and macros for MCF_PIT_PCNTR */ +#define MCF_PIT_PCNTR_PC0 (0x0001) +#define MCF_PIT_PCNTR_PC1 (0x0002) +#define MCF_PIT_PCNTR_PC2 (0x0004) +#define MCF_PIT_PCNTR_PC3 (0x0008) +#define MCF_PIT_PCNTR_PC4 (0x0010) +#define MCF_PIT_PCNTR_PC5 (0x0020) +#define MCF_PIT_PCNTR_PC6 (0x0040) +#define MCF_PIT_PCNTR_PC7 (0x0080) +#define MCF_PIT_PCNTR_PC8 (0x0100) +#define MCF_PIT_PCNTR_PC9 (0x0200) +#define MCF_PIT_PCNTR_PC10 (0x0400) +#define MCF_PIT_PCNTR_PC11 (0x0800) +#define MCF_PIT_PCNTR_PC12 (0x1000) +#define MCF_PIT_PCNTR_PC13 (0x2000) +#define MCF_PIT_PCNTR_PC14 (0x4000) +#define MCF_PIT_PCNTR_PC15 (0x8000) + +/********************************************************************/ + +#endif /* __MCF523X_PIT_H__ */ diff --git a/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_qspi.h b/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_qspi.h new file mode 100644 index 000000000..9f05ada61 --- /dev/null +++ b/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_qspi.h @@ -0,0 +1,69 @@ +/* + * These files are taken from the MCF523X source code example package + * which is available on the Freescale website. Freescale explicitly + * grants the redistribution and modification of these source files. + * The complete licensing information is available in the file + * LICENSE_FREESCALE.TXT. + * + * File: mcf523x_qspi.h + * Purpose: Register and bit definitions for the MCF523X + * + * Notes: + * + */ + +#ifndef __MCF523X_QSPI_H__ +#define __MCF523X_QSPI_H__ + +/********************************************************************* +* +* Queued Serial Peripheral Interface (QSPI) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_QSPI_QMR (*(vuint16*)(void*)(&__IPSBAR[0x000340])) +#define MCF_QSPI_QDLYR (*(vuint16*)(void*)(&__IPSBAR[0x000344])) +#define MCF_QSPI_QWR (*(vuint16*)(void*)(&__IPSBAR[0x000348])) +#define MCF_QSPI_QIR (*(vuint16*)(void*)(&__IPSBAR[0x00034C])) +#define MCF_QSPI_QAR (*(vuint16*)(void*)(&__IPSBAR[0x000350])) +#define MCF_QSPI_QDR (*(vuint16*)(void*)(&__IPSBAR[0x000354])) + +/* Bit definitions and macros for MCF_QSPI_QMR */ +#define MCF_QSPI_QMR_BAUD(x) (((x)&0x00FF)<<0) +#define MCF_QSPI_QMR_CPHA (0x0100) +#define MCF_QSPI_QMR_CPOL (0x0200) +#define MCF_QSPI_QMR_BITS(x) (((x)&0x000F)<<10) +#define MCF_QSPI_QMR_DOHIE (0x4000) +#define MCF_QSPI_QMR_MSTR (0x8000) + +/* Bit definitions and macros for MCF_QSPI_QDLYR */ +#define MCF_QSPI_QDLYR_DTL(x) (((x)&0x00FF)<<0) +#define MCF_QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8) +#define MCF_QSPI_QDLYR_SPE (0x8000) + +/* Bit definitions and macros for MCF_QSPI_QWR */ +#define MCF_QSPI_QWR_NEWQP(x) (((x)&0x000F)<<0) +#define MCF_QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8) +#define MCF_QSPI_QWR_CSIV (0x1000) +#define MCF_QSPI_QWR_WRTO (0x2000) +#define MCF_QSPI_QWR_WREN (0x4000) +#define MCF_QSPI_QWR_HALT (0x8000) + +/* Bit definitions and macros for MCF_QSPI_QIR */ +#define MCF_QSPI_QIR_SPIF (0x0001) +#define MCF_QSPI_QIR_ABRT (0x0004) +#define MCF_QSPI_QIR_WCEF (0x0008) +#define MCF_QSPI_QIR_SPIFE (0x0100) +#define MCF_QSPI_QIR_ABRTE (0x0400) +#define MCF_QSPI_QIR_WCEFE (0x0800) +#define MCF_QSPI_QIR_ABRTL (0x1000) +#define MCF_QSPI_QIR_ABRTB (0x4000) +#define MCF_QSPI_QIR_WCEFB (0x8000) + +/* Bit definitions and macros for MCF_QSPI_QAR */ +#define MCF_QSPI_QAR_ADDR(x) (((x)&0x003F)<<0) + +/********************************************************************/ + +#endif /* __MCF523X_QSPI_H__ */ diff --git a/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_rcm.h b/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_rcm.h new file mode 100644 index 000000000..cae92d22b --- /dev/null +++ b/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_rcm.h @@ -0,0 +1,42 @@ +/* + * These files are taken from the MCF523X source code example package + * which is available on the Freescale website. Freescale explicitly + * grants the redistribution and modification of these source files. + * The complete licensing information is available in the file + * LICENSE_FREESCALE.TXT. + * + * File: mcf523x_rcm.h + * Purpose: Register and bit definitions for the MCF523X + * + * Notes: + * + */ + +#ifndef __MCF523X_RCM_H__ +#define __MCF523X_RCM_H__ + +/********************************************************************* +* +* Reset Configuration Module (RCM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_RCM_RCR (*(vuint8 *)(void*)(&__IPSBAR[0x110000])) +#define MCF_RCM_RSR (*(vuint8 *)(void*)(&__IPSBAR[0x110001])) + +/* Bit definitions and macros for MCF_RCM_RCR */ +#define MCF_RCM_RCR_FRCRSTOUT (0x40) +#define MCF_RCM_RCR_SOFTRST (0x80) + +/* Bit definitions and macros for MCF_RCM_RSR */ +#define MCF_RCM_RSR_LOL (0x01) +#define MCF_RCM_RSR_LOC (0x02) +#define MCF_RCM_RSR_EXT (0x04) +#define MCF_RCM_RSR_POR (0x08) +#define MCF_RCM_RSR_WDR (0x10) +#define MCF_RCM_RSR_SOFT (0x20) + +/********************************************************************/ + +#endif /* __MCF523X_RCM_H__ */ diff --git a/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_rng.h b/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_rng.h new file mode 100644 index 000000000..4bfca3d6c --- /dev/null +++ b/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_rng.h @@ -0,0 +1,46 @@ +/* + * These files are taken from the MCF523X source code example package + * which is available on the Freescale website. Freescale explicitly + * grants the redistribution and modification of these source files. + * The complete licensing information is available in the file + * LICENSE_FREESCALE.TXT. + * + * File: mcf523x_rng.h + * Purpose: Register and bit definitions for the MCF523X + * + * Notes: + * + */ + +#ifndef __MCF523X_RNG_H__ +#define __MCF523X_RNG_H__ + +/********************************************************************* +* +* Random Number Generator (RNG) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_RNG_RNGCR (*(vuint32*)(void*)(&__IPSBAR[0x1A0000])) +#define MCF_RNG_RNGSR (*(vuint32*)(void*)(&__IPSBAR[0x1A0004])) +#define MCF_RNG_RNGER (*(vuint32*)(void*)(&__IPSBAR[0x1A0008])) +#define MCF_RNG_RNGOUT (*(vuint32*)(void*)(&__IPSBAR[0x1A000C])) + +/* Bit definitions and macros for MCF_RNG_RNGCR */ +#define MCF_RNG_RNGCR_GO (0x00000001) +#define MCF_RNG_RNGCR_HA (0x00000002) +#define MCF_RNG_RNGCR_IM (0x00000004) +#define MCF_RNG_RNGCR_CI (0x00000008) + +/* Bit definitions and macros for MCF_RNG_RNGSR */ +#define MCF_RNG_RNGSR_SV (0x00000001) +#define MCF_RNG_RNGSR_LRS (0x00000002) +#define MCF_RNG_RNGSR_FUF (0x00000004) +#define MCF_RNG_RNGSR_EI (0x00000008) +#define MCF_RNG_RNGSR_OFL(x) (((x)&0x000000FF)<<8) +#define MCF_RNG_RNGSR_OFS(x) (((x)&0x000000FF)<<16) + +/********************************************************************/ + +#endif /* __MCF523X_RNG_H__ */ diff --git a/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_scm.h b/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_scm.h new file mode 100644 index 000000000..e330ee990 --- /dev/null +++ b/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_scm.h @@ -0,0 +1,150 @@ +/* + * These files are taken from the MCF523X source code example package + * which is available on the Freescale website. Freescale explicitly + * grants the redistribution and modification of these source files. + * The complete licensing information is available in the file + * LICENSE_FREESCALE.TXT. + * + * File: mcf523x_scm.h + * Purpose: Register and bit definitions for the MCF523X + * + * Notes: + * + */ + +#ifndef __MCF523X_SCM_H__ +#define __MCF523X_SCM_H__ + +/********************************************************************* +* +* System Control Module (SCM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SCM_IPSBAR (*(vuint32*)(void*)(&__IPSBAR[0x000000])) +#define MCF_SCM_RAMBAR (*(vuint32*)(void*)(&__IPSBAR[0x000008])) +#define MCF_SCM_CRSR (*(vuint8 *)(void*)(&__IPSBAR[0x000010])) +#define MCF_SCM_CWCR (*(vuint8 *)(void*)(&__IPSBAR[0x000011])) +#define MCF_SCM_LPICR (*(vuint8 *)(void*)(&__IPSBAR[0x000012])) +#define MCF_SCM_CWSR (*(vuint8 *)(void*)(&__IPSBAR[0x000013])) +#define MCF_SCM_DMAREQC (*(vuint32*)(void*)(&__IPSBAR[0x000014])) +#define MCF_SCM_MPARK (*(vuint32*)(void*)(&__IPSBAR[0x00001C])) +#define MCF_SCM_MPR (*(vuint8 *)(void*)(&__IPSBAR[0x000020])) +#define MCF_SCM_PACR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000024])) +#define MCF_SCM_PACR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000025])) +#define MCF_SCM_PACR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000026])) +#define MCF_SCM_PACR3 (*(vuint8 *)(void*)(&__IPSBAR[0x000027])) +#define MCF_SCM_PACR4 (*(vuint8 *)(void*)(&__IPSBAR[0x000028])) +#define MCF_SCM_PACR5 (*(vuint8 *)(void*)(&__IPSBAR[0x00002A])) +#define MCF_SCM_PACR6 (*(vuint8 *)(void*)(&__IPSBAR[0x00002B])) +#define MCF_SCM_PACR7 (*(vuint8 *)(void*)(&__IPSBAR[0x00002C])) +#define MCF_SCM_PACR8 (*(vuint8 *)(void*)(&__IPSBAR[0x00002E])) +#define MCF_SCM_GPACR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000030])) + +/* Bit definitions and macros for MCF_SCM_IPSBAR */ +#define MCF_SCM_IPSBAR_V (0x00000001) +#define MCF_SCM_IPSBAR_BA(x) (((x)&0x00000003)<<30) + +/* Bit definitions and macros for MCF_SCM_RAMBAR */ +#define MCF_SCM_RAMBAR_BDE (0x00000200) +#define MCF_SCM_RAMBAR_BA(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for MCF_SCM_CRSR */ +#define MCF_SCM_CRSR_CWDR (0x20) +#define MCF_SCM_CRSR_EXT (0x80) + +/* Bit definitions and macros for MCF_SCM_CWCR */ +#define MCF_SCM_CWCR_CWTIC (0x01) +#define MCF_SCM_CWCR_CWTAVAL (0x02) +#define MCF_SCM_CWCR_CWTA (0x04) +#define MCF_SCM_CWCR_CWT(x) (((x)&0x07)<<3) +#define MCF_SCM_CWCR_CWRI (0x40) +#define MCF_SCM_CWCR_CWE (0x80) + +/* Bit definitions and macros for MCF_SCM_LPICR */ +#define MCF_SCM_LPICR_XLPM_IPL(x) (((x)&0x07)<<4) +#define MCF_SCM_LPICR_ENBSTOP (0x80) + +/* Bit definitions and macros for MCF_SCM_DMAREQC */ +#define MCF_SCM_DMAREQC_DMAC0(x) (((x)&0x0000000F)<<0) +#define MCF_SCM_DMAREQC_DMAC1(x) (((x)&0x0000000F)<<4) +#define MCF_SCM_DMAREQC_DMAC2(x) (((x)&0x0000000F)<<8) +#define MCF_SCM_DMAREQC_DMAC3(x) (((x)&0x0000000F)<<12) + +/* Bit definitions and macros for MCF_SCM_MPARK */ +#define MCF_SCM_MPARK_LCKOUT_TIME(x) (((x)&0x0000000F)<<8) +#define MCF_SCM_MPARK_PRKLAST (0x00001000) +#define MCF_SCM_MPARK_TIMEOUT (0x00002000) +#define MCF_SCM_MPARK_FIXED (0x00004000) +#define MCF_SCM_MPARK_M1_PRTY(x) (((x)&0x00000003)<<16) +#define MCF_SCM_MPARK_M0_PRTY(x) (((x)&0x00000003)<<18) +#define MCF_SCM_MPARK_M2_PRTY(x) (((x)&0x00000003)<<20) +#define MCF_SCM_MPARK_M3_PRTY(x) (((x)&0x00000003)<<22) +#define MCF_SCM_MPARK_BCR24BIT (0x01000000) +#define MCF_SCM_MPARK_M2_P_EN (0x02000000) + +/* Bit definitions and macros for MCF_SCM_MPR */ +#define MCF_SCM_MPR_MPR(x) (((x)&0x0F)<<0) + +/* Bit definitions and macros for MCF_SCM_PACR0 */ +#define MCF_SCM_PACR0_ACCESS_CTRL0(x) (((x)&0x07)<<0) +#define MCF_SCM_PACR0_LOCK0 (0x08) +#define MCF_SCM_PACR0_ACCESS_CTRL1(x) (((x)&0x07)<<4) +#define MCF_SCM_PACR0_LOCK1 (0x80) + +/* Bit definitions and macros for MCF_SCM_PACR1 */ +#define MCF_SCM_PACR1_ACCESS_CTRL0(x) (((x)&0x07)<<0) +#define MCF_SCM_PACR1_LOCK0 (0x08) +#define MCF_SCM_PACR1_ACCESS_CTRL1(x) (((x)&0x07)<<4) +#define MCF_SCM_PACR1_LOCK1 (0x80) + +/* Bit definitions and macros for MCF_SCM_PACR2 */ +#define MCF_SCM_PACR2_ACCESS_CTRL0(x) (((x)&0x07)<<0) +#define MCF_SCM_PACR2_LOCK0 (0x08) +#define MCF_SCM_PACR2_ACCESS_CTRL1(x) (((x)&0x07)<<4) +#define MCF_SCM_PACR2_LOCK1 (0x80) + +/* Bit definitions and macros for MCF_SCM_PACR3 */ +#define MCF_SCM_PACR3_ACCESS_CTRL0(x) (((x)&0x07)<<0) +#define MCF_SCM_PACR3_LOCK0 (0x08) +#define MCF_SCM_PACR3_ACCESS_CTRL1(x) (((x)&0x07)<<4) +#define MCF_SCM_PACR3_LOCK1 (0x80) + +/* Bit definitions and macros for MCF_SCM_PACR4 */ +#define MCF_SCM_PACR4_ACCESS_CTRL0(x) (((x)&0x07)<<0) +#define MCF_SCM_PACR4_LOCK0 (0x08) +#define MCF_SCM_PACR4_ACCESS_CTRL1(x) (((x)&0x07)<<4) +#define MCF_SCM_PACR4_LOCK1 (0x80) + +/* Bit definitions and macros for MCF_SCM_PACR5 */ +#define MCF_SCM_PACR5_ACCESS_CTRL0(x) (((x)&0x07)<<0) +#define MCF_SCM_PACR5_LOCK0 (0x08) +#define MCF_SCM_PACR5_ACCESS_CTRL1(x) (((x)&0x07)<<4) +#define MCF_SCM_PACR5_LOCK1 (0x80) + +/* Bit definitions and macros for MCF_SCM_PACR6 */ +#define MCF_SCM_PACR6_ACCESS_CTRL0(x) (((x)&0x07)<<0) +#define MCF_SCM_PACR6_LOCK0 (0x08) +#define MCF_SCM_PACR6_ACCESS_CTRL1(x) (((x)&0x07)<<4) +#define MCF_SCM_PACR6_LOCK1 (0x80) + +/* Bit definitions and macros for MCF_SCM_PACR7 */ +#define MCF_SCM_PACR7_ACCESS_CTRL0(x) (((x)&0x07)<<0) +#define MCF_SCM_PACR7_LOCK0 (0x08) +#define MCF_SCM_PACR7_ACCESS_CTRL1(x) (((x)&0x07)<<4) +#define MCF_SCM_PACR7_LOCK1 (0x80) + +/* Bit definitions and macros for MCF_SCM_PACR8 */ +#define MCF_SCM_PACR8_ACCESS_CTRL0(x) (((x)&0x07)<<0) +#define MCF_SCM_PACR8_LOCK0 (0x08) +#define MCF_SCM_PACR8_ACCESS_CTRL1(x) (((x)&0x07)<<4) +#define MCF_SCM_PACR8_LOCK1 (0x80) + +/* Bit definitions and macros for MCF_SCM_GPACR0 */ +#define MCF_SCM_GPACR0_ACCESS_CTRL(x) (((x)&0x0F)<<0) +#define MCF_SCM_GPACR0_LOCK (0x80) + +/********************************************************************/ + +#endif /* __MCF523X_SCM_H__ */ diff --git a/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_sdramc.h b/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_sdramc.h new file mode 100644 index 000000000..87eb0acef --- /dev/null +++ b/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_sdramc.h @@ -0,0 +1,94 @@ +/* + * These files are taken from the MCF523X source code example package + * which is available on the Freescale website. Freescale explicitly + * grants the redistribution and modification of these source files. + * The complete licensing information is available in the file + * LICENSE_FREESCALE.TXT. + * + * File: mcf523x_sdramc.h + * Purpose: Register and bit definitions for the MCF523X + * + * Notes: + * + */ + +#ifndef __MCF523X_SDRAMC_H__ +#define __MCF523X_SDRAMC_H__ + +/********************************************************************* +* +* SDRAM Controller (SDRAMC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SDRAMC_DCR (*(vuint16*)(void*)(&__IPSBAR[0x000040])) +#define MCF_SDRAMC_DACR0 (*(vuint32*)(void*)(&__IPSBAR[0x000048])) +#define MCF_SDRAMC_DMR0 (*(vuint32*)(void*)(&__IPSBAR[0x00004C])) +#define MCF_SDRAMC_DACR1 (*(vuint32*)(void*)(&__IPSBAR[0x000050])) +#define MCF_SDRAMC_DMR1 (*(vuint32*)(void*)(&__IPSBAR[0x000054])) + +/* Bit definitions and macros for MCF_SDRAMC_DCR */ +#define MCF_SDRAMC_DCR_RC(x) (((x)&0x01FF)<<0) +#define MCF_SDRAMC_DCR_RTIM(x) (((x)&0x0003)<<9) +#define MCF_SDRAMC_DCR_IS (0x0800) +#define MCF_SDRAMC_DCR_COC (0x1000) +#define MCF_SDRAMC_DCR_NAM (0x2000) + +/* Bit definitions and macros for MCF_SDRAMC_DACR0 */ +#define MCF_SDRAMC_DACR0_IP (0x00000008) +#define MCF_SDRAMC_DACR0_PS(x) (((x)&0x00000003)<<4) +#define MCF_SDRAMC_DACR0_MRS (0x00000040) +#define MCF_SDRAMC_DACR0_CBM(x) (((x)&0x00000007)<<8) +#define MCF_SDRAMC_DACR0_CASL(x) (((x)&0x00000003)<<12) +#define MCF_SDRAMC_DACR0_RE (0x00008000) +#define MCF_SDRAMC_DACR0_BA(x) (((x)&0x00003FFF)<<18) + +/* Bit definitions and macros for MCF_SDRAMC_DMR0 */ +#define MCF_SDRAMC_DMR0_V (0x00000001) +#define MCF_SDRAMC_DMR0_WP (0x00000100) +#define MCF_SDRAMC_DMR0_BAM(x) (((x)&0x00003FFF)<<18) + +/* Bit definitions and macros for MCF_SDRAMC_DACR1 */ +#define MCF_SDRAMC_DACR1_IP (0x00000008) +#define MCF_SDRAMC_DACR1_PS(x) (((x)&0x00000003)<<4) +#define MCF_SDRAMC_DACR1_MRS (0x00000040) +#define MCF_SDRAMC_DACR1_CBM(x) (((x)&0x00000007)<<8) +#define MCF_SDRAMC_DACR1_CASL(x) (((x)&0x00000003)<<12) +#define MCF_SDRAMC_DACR1_RE (0x00008000) +#define MCF_SDRAMC_DACR1_BA(x) (((x)&0x00003FFF)<<18) + +/* Bit definitions and macros for MCF_SDRAMC_DMR1 */ +#define MCF_SDRAMC_DMR1_V (0x00000001) +#define MCF_SDRAMC_DMR1_WP (0x00000100) +#define MCF_SDRAMC_DMR1_BAM(x) (((x)&0x00003FFF)<<18) + +/********************************************************************/ + +#define MCF_SDRAMC_DMR_BAM_4G (0xFFFC0000) +#define MCF_SDRAMC_DMR_BAM_2G (0x7FFC0000) +#define MCF_SDRAMC_DMR_BAM_1G (0x3FFC0000) +#define MCF_SDRAMC_DMR_BAM_1024M (0x3FFC0000) +#define MCF_SDRAMC_DMR_BAM_512M (0x1FFC0000) +#define MCF_SDRAMC_DMR_BAM_256M (0x0FFC0000) +#define MCF_SDRAMC_DMR_BAM_128M (0x07FC0000) +#define MCF_SDRAMC_DMR_BAM_64M (0x03FC0000) +#define MCF_SDRAMC_DMR_BAM_32M (0x01FC0000) +#define MCF_SDRAMC_DMR_BAM_16M (0x00FC0000) +#define MCF_SDRAMC_DMR_BAM_8M (0x007C0000) +#define MCF_SDRAMC_DMR_BAM_4M (0x003C0000) +#define MCF_SDRAMC_DMR_BAM_2M (0x001C0000) +#define MCF_SDRAMC_DMR_BAM_1M (0x000C0000) +#define MCF_SDRAMC_DMR_BAM_1024K (0x000C0000) +#define MCF_SDRAMC_DMR_BAM_512K (0x00040000) +#define MCF_SDRAMC_DMR_BAM_256K (0x00000000) +#define MCF_SDRAMC_DMR_WP (0x00000100) +#define MCF_SDRAMC_DMR_CI (0x00000040) +#define MCF_SDRAMC_DMR_AM (0x00000020) +#define MCF_SDRAMC_DMR_SC (0x00000010) +#define MCF_SDRAMC_DMR_SD (0x00000008) +#define MCF_SDRAMC_DMR_UC (0x00000004) +#define MCF_SDRAMC_DMR_UD (0x00000002) +#define MCF_SDRAMC_DMR_V (0x00000001) + +#endif /* __MCF523X_SDRAMC_H__ */ diff --git a/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_skha.h b/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_skha.h new file mode 100644 index 000000000..ae4dc57ab --- /dev/null +++ b/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_skha.h @@ -0,0 +1,120 @@ +/* + * These files are taken from the MCF523X source code example package + * which is available on the Freescale website. Freescale explicitly + * grants the redistribution and modification of these source files. + * The complete licensing information is available in the file + * LICENSE_FREESCALE.TXT. + * + * File: mcf523x_skha.h + * Purpose: Register and bit definitions for the MCF523X + * + * Notes: + * + */ + +#ifndef __MCF523X_SKHA_H__ +#define __MCF523X_SKHA_H__ + +/********************************************************************* +* +* Symmetric Key Hardware Accelerator (SKHA) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SKHA_SKMR (*(vuint32*)(void*)(&__IPSBAR[0x1B0000])) +#define MCF_SKHA_SKCR (*(vuint32*)(void*)(&__IPSBAR[0x1B0004])) +#define MCF_SKHA_SKCMR (*(vuint32*)(void*)(&__IPSBAR[0x1B0008])) +#define MCF_SKHA_SKSR (*(vuint32*)(void*)(&__IPSBAR[0x1B000C])) +#define MCF_SKHA_SKIR (*(vuint32*)(void*)(&__IPSBAR[0x1B0010])) +#define MCF_SKHA_SKIMR (*(vuint32*)(void*)(&__IPSBAR[0x1B0014])) +#define MCF_SKHA_SKKSR (*(vuint32*)(void*)(&__IPSBAR[0x1B0018])) +#define MCF_SKHA_SKDSR (*(vuint32*)(void*)(&__IPSBAR[0x1B001C])) +#define MCF_SKHA_SKIN (*(vuint32*)(void*)(&__IPSBAR[0x1B0020])) +#define MCF_SKHA_SKOUT (*(vuint32*)(void*)(&__IPSBAR[0x1B0024])) +#define MCF_SKHA_SKKDR0 (*(vuint32*)(void*)(&__IPSBAR[0x1B0030])) +#define MCF_SKHA_SKKDR1 (*(vuint32*)(void*)(&__IPSBAR[0x1B0034])) +#define MCF_SKHA_SKKDR2 (*(vuint32*)(void*)(&__IPSBAR[0x1B0038])) +#define MCF_SKHA_SKKDR3 (*(vuint32*)(void*)(&__IPSBAR[0x1B003C])) +#define MCF_SKHA_SKKDR4 (*(vuint32*)(void*)(&__IPSBAR[0x1B0040])) +#define MCF_SKHA_SKKDR5 (*(vuint32*)(void*)(&__IPSBAR[0x1B0044])) +#define MCF_SKHA_SKKDRn(x) (*(vuint32*)(void*)(&__IPSBAR[0x1B0030+((x)*0x004)])) +#define MCF_SKHA_SKCR0 (*(vuint32*)(void*)(&__IPSBAR[0x1B0070])) +#define MCF_SKHA_SKCR1 (*(vuint32*)(void*)(&__IPSBAR[0x1B0074])) +#define MCF_SKHA_SKCR2 (*(vuint32*)(void*)(&__IPSBAR[0x1B0078])) +#define MCF_SKHA_SKCR3 (*(vuint32*)(void*)(&__IPSBAR[0x1B007C])) +#define MCF_SKHA_SKCR4 (*(vuint32*)(void*)(&__IPSBAR[0x1B0080])) +#define MCF_SKHA_SKCR5 (*(vuint32*)(void*)(&__IPSBAR[0x1B0084])) +#define MCF_SKHA_SKCR6 (*(vuint32*)(void*)(&__IPSBAR[0x1B0088])) +#define MCF_SKHA_SKCR7 (*(vuint32*)(void*)(&__IPSBAR[0x1B008C])) +#define MCF_SKHA_SKCR8 (*(vuint32*)(void*)(&__IPSBAR[0x1B0090])) +#define MCF_SKHA_SKCR9 (*(vuint32*)(void*)(&__IPSBAR[0x1B0094])) +#define MCF_SKHA_SKCR10 (*(vuint32*)(void*)(&__IPSBAR[0x1B0098])) +#define MCF_SKHA_SKCR11 (*(vuint32*)(void*)(&__IPSBAR[0x1B009C])) +#define MCF_SKHA_SKCRn(x) (*(vuint32*)(void*)(&__IPSBAR[0x1B0070+((x)*0x004)])) + +/* Bit definitions and macros for MCF_SKHA_SKMR */ +#define MCF_SKHA_SKMR_ALG(x) (((x)&0x00000003)<<0) +#define MCF_SKHA_SKMR_DIR (0x00000004) +#define MCF_SKHA_SKMR_CM(x) (((x)&0x00000003)<<3) +#define MCF_SKHA_SKMR_DKP (0x00000100) +#define MCF_SKHA_SKMR_CTRM(x) (((x)&0x0000000F)<<9) +#define MCF_SKHA_SKMR_CM_ECB (0x00000000) +#define MCF_SKHA_SKMR_CM_CBC (0x00000008) +#define MCF_SKHA_SKMR_CM_CTR (0x00000018) +#define MCF_SKHA_SKMR_DIR_DEC (0x00000000) +#define MCF_SKHA_SKMR_DIR_ENC (0x00000004) +#define MCF_SKHA_SKMR_ALG_AES (0x00000000) +#define MCF_SKHA_SKMR_ALG_DES (0x00000001) +#define MCF_SKHA_SKMR_ALG_TDES (0x00000002) + +/* Bit definitions and macros for MCF_SKHA_SKCR */ +#define MCF_SKHA_SKCR_IE (0x00000001) + +/* Bit definitions and macros for MCF_SKHA_SKCMR */ +#define MCF_SKHA_SKCMR_SWR (0x00000001) +#define MCF_SKHA_SKCMR_RI (0x00000002) +#define MCF_SKHA_SKCMR_CI (0x00000004) +#define MCF_SKHA_SKCMR_GO (0x00000008) + +/* Bit definitions and macros for MCF_SKHA_SKSR */ +#define MCF_SKHA_SKSR_INT (0x00000001) +#define MCF_SKHA_SKSR_DONE (0x00000002) +#define MCF_SKHA_SKSR_ERR (0x00000004) +#define MCF_SKHA_SKSR_RD (0x00000008) +#define MCF_SKHA_SKSR_BUSY (0x00000010) +#define MCF_SKHA_SKSR_IFL(x) (((x)&0x000000FF)<<16) +#define MCF_SKHA_SKSR_OFL(x) (((x)&0x000000FF)<<24) + +/* Bit definitions and macros for MCF_SKHA_SKIR */ +#define MCF_SKHA_SKIR_IFO (0x00000001) +#define MCF_SKHA_SKIR_OFU (0x00000002) +#define MCF_SKHA_SKIR_NEIF (0x00000004) +#define MCF_SKHA_SKIR_NEOF (0x00000008) +#define MCF_SKHA_SKIR_IME (0x00000010) +#define MCF_SKHA_SKIR_DSE (0x00000020) +#define MCF_SKHA_SKIR_KSE (0x00000040) +#define MCF_SKHA_SKIR_RMDP (0x00000080) +#define MCF_SKHA_SKIR_ERE (0x00000100) +#define MCF_SKHA_SKIR_KPE (0x00000200) +#define MCF_SKHA_SKIR_KRE (0x00000400) + +/* Bit definitions and macros for MCF_SKHA_SKIMR */ +#define MCF_SKHA_SKIMR_IFO (0x00000001) +#define MCF_SKHA_SKIMR_OFU (0x00000002) +#define MCF_SKHA_SKIMR_NEIF (0x00000004) +#define MCF_SKHA_SKIMR_NEOF (0x00000008) +#define MCF_SKHA_SKIMR_IME (0x00000010) +#define MCF_SKHA_SKIMR_DSE (0x00000020) +#define MCF_SKHA_SKIMR_KSE (0x00000040) +#define MCF_SKHA_SKIMR_RMDP (0x00000080) +#define MCF_SKHA_SKIMR_ERE (0x00000100) +#define MCF_SKHA_SKIMR_KPE (0x00000200) +#define MCF_SKHA_SKIMR_KRE (0x00000400) + +/* Bit definitions and macros for MCF_SKHA_SKKSR */ +#define MCF_SKHA_SKKSR_KEYSIZE(x) (((x)&0x0000003F)<<0) + +/********************************************************************/ + +#endif /* __MCF523X_SKHA_H__ */ diff --git a/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_sram.h b/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_sram.h new file mode 100644 index 000000000..74626c2be --- /dev/null +++ b/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_sram.h @@ -0,0 +1,42 @@ +/* + * These files are taken from the MCF523X source code example package + * which is available on the Freescale website. Freescale explicitly + * grants the redistribution and modification of these source files. + * The complete licensing information is available in the file + * LICENSE_FREESCALE.TXT. + * + * File: mcf523x_sram.h + * Purpose: Register and bit definitions for the MCF523X + * + * Notes: + * + */ + +#ifndef __MCF523X_SRAM_H__ +#define __MCF523X_SRAM_H__ + +/********************************************************************* +* +* 64KByte System SRAM (SRAM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SRAM_RAMBAR (*(vuint32*)(void*)(&__IPSBAR[0x20000000])) + +/* Bit definitions and macros for MCF_SRAM_RAMBAR */ +#define MCF_SRAM_RAMBAR_V (0x00000001) +#define MCF_SRAM_RAMBAR_UD (0x00000002) +#define MCF_SRAM_RAMBAR_UC (0x00000004) +#define MCF_SRAM_RAMBAR_SD (0x00000008) +#define MCF_SRAM_RAMBAR_SC (0x00000010) +#define MCF_SRAM_RAMBAR_CI (0x00000020) +#define MCF_SRAM_RAMBAR_WP (0x00000100) +#define MCF_SRAM_RAMBAR_SPV (0x00000200) +#define MCF_SRAM_RAMBAR_PRI2 (0x00000400) +#define MCF_SRAM_RAMBAR_PRI1 (0x00000800) +#define MCF_SRAM_RAMBAR_BA(x) (((x)&0x0000FFFF)<<16) + +/********************************************************************/ + +#endif /* __MCF523X_SRAM_H__ */ diff --git a/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_timer.h b/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_timer.h new file mode 100644 index 000000000..359e895f7 --- /dev/null +++ b/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_timer.h @@ -0,0 +1,83 @@ +/* + * These files are taken from the MCF523X source code example package + * which is available on the Freescale website. Freescale explicitly + * grants the redistribution and modification of these source files. + * The complete licensing information is available in the file + * LICENSE_FREESCALE.TXT. + * + * File: mcf523x_timer.h + * Purpose: Register and bit definitions for the MCF523X + * + * Notes: + * + */ + +#ifndef __MCF523X_TIMER_H__ +#define __MCF523X_TIMER_H__ + +/********************************************************************* +* +* DMA Timers (TIMER) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_TIMER_DTMR0 (*(vuint16*)(void*)(&__IPSBAR[0x000400])) +#define MCF_TIMER_DTXMR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000402])) +#define MCF_TIMER_DTER0 (*(vuint8 *)(void*)(&__IPSBAR[0x000403])) +#define MCF_TIMER_DTRR0 (*(vuint32*)(void*)(&__IPSBAR[0x000404])) +#define MCF_TIMER_DTCR0 (*(vuint32*)(void*)(&__IPSBAR[0x000408])) +#define MCF_TIMER_DTCN0 (*(vuint32*)(void*)(&__IPSBAR[0x00040C])) +#define MCF_TIMER_DTMR1 (*(vuint16*)(void*)(&__IPSBAR[0x000440])) +#define MCF_TIMER_DTXMR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000442])) +#define MCF_TIMER_DTER1 (*(vuint8 *)(void*)(&__IPSBAR[0x000443])) +#define MCF_TIMER_DTRR1 (*(vuint32*)(void*)(&__IPSBAR[0x000444])) +#define MCF_TIMER_DTCR1 (*(vuint32*)(void*)(&__IPSBAR[0x000448])) +#define MCF_TIMER_DTCN1 (*(vuint32*)(void*)(&__IPSBAR[0x00044C])) +#define MCF_TIMER_DTMR2 (*(vuint16*)(void*)(&__IPSBAR[0x000480])) +#define MCF_TIMER_DTXMR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000482])) +#define MCF_TIMER_DTER2 (*(vuint8 *)(void*)(&__IPSBAR[0x000483])) +#define MCF_TIMER_DTRR2 (*(vuint32*)(void*)(&__IPSBAR[0x000484])) +#define MCF_TIMER_DTCR2 (*(vuint32*)(void*)(&__IPSBAR[0x000488])) +#define MCF_TIMER_DTCN2 (*(vuint32*)(void*)(&__IPSBAR[0x00048C])) +#define MCF_TIMER_DTMR3 (*(vuint16*)(void*)(&__IPSBAR[0x0004C0])) +#define MCF_TIMER_DTXMR3 (*(vuint8 *)(void*)(&__IPSBAR[0x0004C2])) +#define MCF_TIMER_DTER3 (*(vuint8 *)(void*)(&__IPSBAR[0x0004C3])) +#define MCF_TIMER_DTRR3 (*(vuint32*)(void*)(&__IPSBAR[0x0004C4])) +#define MCF_TIMER_DTCR3 (*(vuint32*)(void*)(&__IPSBAR[0x0004C8])) +#define MCF_TIMER_DTCN3 (*(vuint32*)(void*)(&__IPSBAR[0x0004CC])) +#define MCF_TIMER_DTMR(x) (*(vuint16*)(void*)(&__IPSBAR[0x000400+((x)*0x040)])) +#define MCF_TIMER_DTXMR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000402+((x)*0x040)])) +#define MCF_TIMER_DTER(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000403+((x)*0x040)])) +#define MCF_TIMER_DTRR(x) (*(vuint32*)(void*)(&__IPSBAR[0x000404+((x)*0x040)])) +#define MCF_TIMER_DTCR(x) (*(vuint32*)(void*)(&__IPSBAR[0x000408+((x)*0x040)])) +#define MCF_TIMER_DTCN(x) (*(vuint32*)(void*)(&__IPSBAR[0x00040C+((x)*0x040)])) + +/* Bit definitions and macros for MCF_TIMER_DTMR */ +#define MCF_TIMER_DTMR_RST (0x0001) +#define MCF_TIMER_DTMR_CLK(x) (((x)&0x0003)<<1) +#define MCF_TIMER_DTMR_FRR (0x0008) +#define MCF_TIMER_DTMR_ORRI (0x0010) +#define MCF_TIMER_DTMR_OM (0x0020) +#define MCF_TIMER_DTMR_CE(x) (((x)&0x0003)<<6) +#define MCF_TIMER_DTMR_PS(x) (((x)&0x00FF)<<8) +#define MCF_TIMER_DTMR_CE_ANY (0x00C0) +#define MCF_TIMER_DTMR_CE_FALL (0x0080) +#define MCF_TIMER_DTMR_CE_RISE (0x0040) +#define MCF_TIMER_DTMR_CE_NONE (0x0000) +#define MCF_TIMER_DTMR_CLK_DTIN (0x0006) +#define MCF_TIMER_DTMR_CLK_DIV16 (0x0004) +#define MCF_TIMER_DTMR_CLK_DIV1 (0x0002) +#define MCF_TIMER_DTMR_CLK_STOP (0x0000) + +/* Bit definitions and macros for MCF_TIMER_DTXMR */ +#define MCF_TIMER_DTXMR_MODE16 (0x01) +#define MCF_TIMER_DTXMR_DMAEN (0x80) + +/* Bit definitions and macros for MCF_TIMER_DTER */ +#define MCF_TIMER_DTER_CAP (0x01) +#define MCF_TIMER_DTER_REF (0x02) + +/********************************************************************/ + +#endif /* __MCF523X_TIMER_H__ */ diff --git a/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_uart.h b/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_uart.h new file mode 100644 index 000000000..f70a71c4e --- /dev/null +++ b/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_uart.h @@ -0,0 +1,186 @@ +/* + * These files are taken from the MCF523X source code example package + * which is available on the Freescale website. Freescale explicitly + * grants the redistribution and modification of these source files. + * The complete licensing information is available in the file + * LICENSE_FREESCALE.TXT. + * + * File: mcf523x_uart.h + * Purpose: Register and bit definitions for the MCF523X + * + * Notes: + * + */ + +#ifndef __MCF523X_UART_H__ +#define __MCF523X_UART_H__ + +/********************************************************************* +* +* Universal Asynchronous Receiver Transmitter (UART) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_UART_UMR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000200])) +#define MCF_UART_USR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000204])) +#define MCF_UART_UCSR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000204])) +#define MCF_UART_UCR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000208])) +#define MCF_UART_URB0 (*(vuint8 *)(void*)(&__IPSBAR[0x00020C])) +#define MCF_UART_UTB0 (*(vuint8 *)(void*)(&__IPSBAR[0x00020C])) +#define MCF_UART_UIPCR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000210])) +#define MCF_UART_UACR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000210])) +#define MCF_UART_UISR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000214])) +#define MCF_UART_UIMR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000214])) +#define MCF_UART_UBG10 (*(vuint8 *)(void*)(&__IPSBAR[0x000218])) +#define MCF_UART_UBG20 (*(vuint8 *)(void*)(&__IPSBAR[0x00021C])) +#define MCF_UART_UIP0 (*(vuint8 *)(void*)(&__IPSBAR[0x000234])) +#define MCF_UART_UOP10 (*(vuint8 *)(void*)(&__IPSBAR[0x000238])) +#define MCF_UART_UOP00 (*(vuint8 *)(void*)(&__IPSBAR[0x00023C])) +#define MCF_UART_UMR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000240])) +#define MCF_UART_USR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000244])) +#define MCF_UART_UCSR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000244])) +#define MCF_UART_UCR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000248])) +#define MCF_UART_URB1 (*(vuint8 *)(void*)(&__IPSBAR[0x00024C])) +#define MCF_UART_UTB1 (*(vuint8 *)(void*)(&__IPSBAR[0x00024C])) +#define MCF_UART_UIPCR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000250])) +#define MCF_UART_UACR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000250])) +#define MCF_UART_UISR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000254])) +#define MCF_UART_UIMR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000254])) +#define MCF_UART_UBG11 (*(vuint8 *)(void*)(&__IPSBAR[0x000258])) +#define MCF_UART_UBG21 (*(vuint8 *)(void*)(&__IPSBAR[0x00025C])) +#define MCF_UART_UIP1 (*(vuint8 *)(void*)(&__IPSBAR[0x000274])) +#define MCF_UART_UOP11 (*(vuint8 *)(void*)(&__IPSBAR[0x000278])) +#define MCF_UART_UOP01 (*(vuint8 *)(void*)(&__IPSBAR[0x00027C])) +#define MCF_UART_UMR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000280])) +#define MCF_UART_USR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000284])) +#define MCF_UART_UCSR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000284])) +#define MCF_UART_UCR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000288])) +#define MCF_UART_URB2 (*(vuint8 *)(void*)(&__IPSBAR[0x00028C])) +#define MCF_UART_UTB2 (*(vuint8 *)(void*)(&__IPSBAR[0x00028C])) +#define MCF_UART_UIPCR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000290])) +#define MCF_UART_UACR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000290])) +#define MCF_UART_UISR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000294])) +#define MCF_UART_UIMR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000294])) +#define MCF_UART_UBG12 (*(vuint8 *)(void*)(&__IPSBAR[0x000298])) +#define MCF_UART_UBG22 (*(vuint8 *)(void*)(&__IPSBAR[0x00029C])) +#define MCF_UART_UIP2 (*(vuint8 *)(void*)(&__IPSBAR[0x0002B4])) +#define MCF_UART_UOP12 (*(vuint8 *)(void*)(&__IPSBAR[0x0002B8])) +#define MCF_UART_UOP02 (*(vuint8 *)(void*)(&__IPSBAR[0x0002BC])) +#define MCF_UART_UMR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000200+((x)*0x040)])) +#define MCF_UART_USR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000204+((x)*0x040)])) +#define MCF_UART_UCSR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000204+((x)*0x040)])) +#define MCF_UART_UCR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000208+((x)*0x040)])) +#define MCF_UART_URB(x) (*(vuint8 *)(void*)(&__IPSBAR[0x00020C+((x)*0x040)])) +#define MCF_UART_UTB(x) (*(vuint8 *)(void*)(&__IPSBAR[0x00020C+((x)*0x040)])) +#define MCF_UART_UIPCR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000210+((x)*0x040)])) +#define MCF_UART_UACR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000210+((x)*0x040)])) +#define MCF_UART_UISR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000214+((x)*0x040)])) +#define MCF_UART_UIMR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000214+((x)*0x040)])) +#define MCF_UART_UBG1(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000218+((x)*0x040)])) +#define MCF_UART_UBG2(x) (*(vuint8 *)(void*)(&__IPSBAR[0x00021C+((x)*0x040)])) +#define MCF_UART_UIP(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000234+((x)*0x040)])) +#define MCF_UART_UOP1(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000238+((x)*0x040)])) +#define MCF_UART_UOP0(x) (*(vuint8 *)(void*)(&__IPSBAR[0x00023C+((x)*0x040)])) + +/* Bit definitions and macros for MCF_UART_UMR */ +#define MCF_UART_UMR_BC(x) (((x)&0x03)<<0) +#define MCF_UART_UMR_PT (0x04) +#define MCF_UART_UMR_PM(x) (((x)&0x03)<<3) +#define MCF_UART_UMR_ERR (0x20) +#define MCF_UART_UMR_RXIRQ (0x40) +#define MCF_UART_UMR_RXRTS (0x80) +#define MCF_UART_UMR_SB(x) (((x)&0x0F)<<0) +#define MCF_UART_UMR_TXCTS (0x10) +#define MCF_UART_UMR_TXRTS (0x20) +#define MCF_UART_UMR_CM(x) (((x)&0x03)<<6) +#define MCF_UART_UMR_PM_MULTI_ADDR (0x1C) +#define MCF_UART_UMR_PM_MULTI_DATA (0x18) +#define MCF_UART_UMR_PM_NONE (0x10) +#define MCF_UART_UMR_PM_FORCE_HI (0x0C) +#define MCF_UART_UMR_PM_FORCE_LO (0x08) +#define MCF_UART_UMR_PM_ODD (0x04) +#define MCF_UART_UMR_PM_EVEN (0x00) +#define MCF_UART_UMR_BC_5 (0x00) +#define MCF_UART_UMR_BC_6 (0x01) +#define MCF_UART_UMR_BC_7 (0x02) +#define MCF_UART_UMR_BC_8 (0x03) +#define MCF_UART_UMR_CM_NORMAL (0x00) +#define MCF_UART_UMR_CM_ECHO (0x40) +#define MCF_UART_UMR_CM_LOCAL_LOOP (0x80) +#define MCF_UART_UMR_CM_REMOTE_LOOP (0xC0) +#define MCF_UART_UMR_SB_STOP_BITS_1 (0x07) +#define MCF_UART_UMR_SB_STOP_BITS_15 (0x08) +#define MCF_UART_UMR_SB_STOP_BITS_2 (0x0F) + +/* Bit definitions and macros for MCF_UART_USR */ +#define MCF_UART_USR_RXRDY (0x01) +#define MCF_UART_USR_FFULL (0x02) +#define MCF_UART_USR_TXRDY (0x04) +#define MCF_UART_USR_TXEMP (0x08) +#define MCF_UART_USR_OE (0x10) +#define MCF_UART_USR_PE (0x20) +#define MCF_UART_USR_FE (0x40) +#define MCF_UART_USR_RB (0x80) + +/* Bit definitions and macros for MCF_UART_UCSR */ +#define MCF_UART_UCSR_TCS(x) (((x)&0x0F)<<0) +#define MCF_UART_UCSR_RCS(x) (((x)&0x0F)<<4) +#define MCF_UART_UCSR_RCS_SYS_CLK (0xD0) +#define MCF_UART_UCSR_RCS_CTM16 (0xE0) +#define MCF_UART_UCSR_RCS_CTM (0xF0) +#define MCF_UART_UCSR_TCS_SYS_CLK (0x0D) +#define MCF_UART_UCSR_TCS_CTM16 (0x0E) +#define MCF_UART_UCSR_TCS_CTM (0x0F) + +/* Bit definitions and macros for MCF_UART_UCR */ +#define MCF_UART_UCR_RXC(x) (((x)&0x03)<<0) +#define MCF_UART_UCR_TXC(x) (((x)&0x03)<<2) +#define MCF_UART_UCR_MISC(x) (((x)&0x07)<<4) +#define MCF_UART_UCR_NONE (0x00) +#define MCF_UART_UCR_STOP_BREAK (0x70) +#define MCF_UART_UCR_START_BREAK (0x60) +#define MCF_UART_UCR_BKCHGINT (0x50) +#define MCF_UART_UCR_RESET_ERROR (0x40) +#define MCF_UART_UCR_RESET_TX (0x30) +#define MCF_UART_UCR_RESET_RX (0x20) +#define MCF_UART_UCR_RESET_MR (0x10) +#define MCF_UART_UCR_TX_DISABLED (0x08) +#define MCF_UART_UCR_TX_ENABLED (0x04) +#define MCF_UART_UCR_RX_DISABLED (0x02) +#define MCF_UART_UCR_RX_ENABLED (0x01) + +/* Bit definitions and macros for MCF_UART_UIPCR */ +#define MCF_UART_UIPCR_CTS (0x01) +#define MCF_UART_UIPCR_COS (0x10) + +/* Bit definitions and macros for MCF_UART_UACR */ +#define MCF_UART_UACR_IEC (0x01) + +/* Bit definitions and macros for MCF_UART_UISR */ +#define MCF_UART_UISR_TXRDY (0x01) +#define MCF_UART_UISR_RXRDY_FU (0x02) +#define MCF_UART_UISR_DB (0x04) +#define MCF_UART_UISR_RXFTO (0x08) +#define MCF_UART_UISR_TXFIFO (0x10) +#define MCF_UART_UISR_RXFIFO (0x20) +#define MCF_UART_UISR_COS (0x80) + +/* Bit definitions and macros for MCF_UART_UIMR */ +#define MCF_UART_UIMR_TXRDY (0x01) +#define MCF_UART_UIMR_RXRDY_FU (0x02) +#define MCF_UART_UIMR_DB (0x04) +#define MCF_UART_UIMR_COS (0x80) + +/* Bit definitions and macros for MCF_UART_UIP */ +#define MCF_UART_UIP_CTS (0x01) + +/* Bit definitions and macros for MCF_UART_UOP1 */ +#define MCF_UART_UOP1_RTS (0x01) + +/* Bit definitions and macros for MCF_UART_UOP0 */ +#define MCF_UART_UOP0_RTS (0x01) + +/********************************************************************/ + +#endif /* __MCF523X_UART_H__ */ diff --git a/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_wtm.h b/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_wtm.h new file mode 100644 index 000000000..1e5f9f97f --- /dev/null +++ b/20080212/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_wtm.h @@ -0,0 +1,92 @@ +/* + * These files are taken from the MCF523X source code example package + * which is available on the Freescale website. Freescale explicitly + * grants the redistribution and modification of these source files. + * The complete licensing information is available in the file + * LICENSE_FREESCALE.TXT. + * + * File: mcf523x_wtm.h + * Purpose: Register and bit definitions for the MCF523X + * + * Notes: + * + */ + +#ifndef __MCF523X_WTM_H__ +#define __MCF523X_WTM_H__ + +/********************************************************************* +* +* Watchdog Timer Modules (WTM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_WTM_WCR (*(vuint16*)(void*)(&__IPSBAR[0x140000])) +#define MCF_WTM_WMR (*(vuint16*)(void*)(&__IPSBAR[0x140002])) +#define MCF_WTM_WCNTR (*(vuint16*)(void*)(&__IPSBAR[0x140004])) +#define MCF_WTM_WSR (*(vuint16*)(void*)(&__IPSBAR[0x140006])) + +/* Bit definitions and macros for MCF_WTM_WCR */ +#define MCF_WTM_WCR_EN (0x0001) +#define MCF_WTM_WCR_HALTED (0x0002) +#define MCF_WTM_WCR_DOZE (0x0004) +#define MCF_WTM_WCR_WAIT (0x0008) + +/* Bit definitions and macros for MCF_WTM_WMR */ +#define MCF_WTM_WMR_WM0 (0x0001) +#define MCF_WTM_WMR_WM1 (0x0002) +#define MCF_WTM_WMR_WM2 (0x0004) +#define MCF_WTM_WMR_WM3 (0x0008) +#define MCF_WTM_WMR_WM4 (0x0010) +#define MCF_WTM_WMR_WM5 (0x0020) +#define MCF_WTM_WMR_WM6 (0x0040) +#define MCF_WTM_WMR_WM7 (0x0080) +#define MCF_WTM_WMR_WM8 (0x0100) +#define MCF_WTM_WMR_WM9 (0x0200) +#define MCF_WTM_WMR_WM10 (0x0400) +#define MCF_WTM_WMR_WM11 (0x0800) +#define MCF_WTM_WMR_WM12 (0x1000) +#define MCF_WTM_WMR_WM13 (0x2000) +#define MCF_WTM_WMR_WM14 (0x4000) +#define MCF_WTM_WMR_WM15 (0x8000) + +/* Bit definitions and macros for MCF_WTM_WCNTR */ +#define MCF_WTM_WCNTR_WC0 (0x0001) +#define MCF_WTM_WCNTR_WC1 (0x0002) +#define MCF_WTM_WCNTR_WC2 (0x0004) +#define MCF_WTM_WCNTR_WC3 (0x0008) +#define MCF_WTM_WCNTR_WC4 (0x0010) +#define MCF_WTM_WCNTR_WC5 (0x0020) +#define MCF_WTM_WCNTR_WC6 (0x0040) +#define MCF_WTM_WCNTR_WC7 (0x0080) +#define MCF_WTM_WCNTR_WC8 (0x0100) +#define MCF_WTM_WCNTR_WC9 (0x0200) +#define MCF_WTM_WCNTR_WC10 (0x0400) +#define MCF_WTM_WCNTR_WC11 (0x0800) +#define MCF_WTM_WCNTR_WC12 (0x1000) +#define MCF_WTM_WCNTR_WC13 (0x2000) +#define MCF_WTM_WCNTR_WC14 (0x4000) +#define MCF_WTM_WCNTR_WC15 (0x8000) + +/* Bit definitions and macros for MCF_WTM_WSR */ +#define MCF_WTM_WSR_WS0 (0x0001) +#define MCF_WTM_WSR_WS1 (0x0002) +#define MCF_WTM_WSR_WS2 (0x0004) +#define MCF_WTM_WSR_WS3 (0x0008) +#define MCF_WTM_WSR_WS4 (0x0010) +#define MCF_WTM_WSR_WS5 (0x0020) +#define MCF_WTM_WSR_WS6 (0x0040) +#define MCF_WTM_WSR_WS7 (0x0080) +#define MCF_WTM_WSR_WS8 (0x0100) +#define MCF_WTM_WSR_WS9 (0x0200) +#define MCF_WTM_WSR_WS10 (0x0400) +#define MCF_WTM_WSR_WS11 (0x0800) +#define MCF_WTM_WSR_WS12 (0x1000) +#define MCF_WTM_WSR_WS13 (0x2000) +#define MCF_WTM_WSR_WS14 (0x4000) +#define MCF_WTM_WSR_WS15 (0x8000) + +/********************************************************************/ + +#endif /* __MCF523X_WTM_H__ */ diff --git a/20080212/Demo/MCF5235_GCC/include/arch/mcf5xxx.h b/20080212/Demo/MCF5235_GCC/include/arch/mcf5xxx.h new file mode 100644 index 000000000..01153e409 --- /dev/null +++ b/20080212/Demo/MCF5235_GCC/include/arch/mcf5xxx.h @@ -0,0 +1,196 @@ +/* + * These files are taken from the MCF523X source code example package + * which is available on the Freescale website. Freescale explicitly + * grants the redistribution and modification of these source files. + * The complete licensing information is available in the file + * LICENSE_FREESCALE.TXT. + * + * File: mcf5xxx.h + * Purpose: Definitions common to all ColdFire processors + * + * Notes: + */ + +#ifndef _CPU_MCF5XXX_H +#define _CPU_MCF5XXX_H + +/***********************************************************************/ +/* + * Misc. Defines + */ + +#ifdef FALSE +#undef FALSE +#endif +#define FALSE (0) + +#ifdef TRUE +#undef TRUE +#endif +#define TRUE (1) + +#ifdef NULL +#undef NULL +#endif +#define NULL (0) + +/***********************************************************************/ +/* + * The basic data types + */ + +typedef unsigned char uint8; /* 8 bits */ +typedef unsigned short int uint16; /* 16 bits */ +typedef unsigned long int uint32; /* 32 bits */ + +typedef signed char int8; /* 8 bits */ +typedef signed short int int16; /* 16 bits */ +typedef signed long int int32; /* 32 bits */ + +typedef volatile uint8 vuint8; /* 8 bits */ +typedef volatile uint16 vuint16; /* 16 bits */ +typedef volatile uint32 vuint32; /* 32 bits */ + +/***********************************************************************/ +/* + * Common M68K & ColdFire definitions + */ + +#define ADDRESS uint32 +#define INSTRUCTION uint16 +#define ILLEGAL 0x4AFC +#define CPU_WORD_SIZE 16 + +#define MCF5XXX_SR_T (0x8000) +#define MCF5XXX_SR_S (0x2000) +#define MCF5XXX_SR_M (0x1000) +#define MCF5XXX_SR_IPL (0x0700) +#define MCF5XXX_SR_IPL_0 (0x0000) +#define MCF5XXX_SR_IPL_1 (0x0100) +#define MCF5XXX_SR_IPL_2 (0x0200) +#define MCF5XXX_SR_IPL_3 (0x0300) +#define MCF5XXX_SR_IPL_4 (0x0400) +#define MCF5XXX_SR_IPL_5 (0x0500) +#define MCF5XXX_SR_IPL_6 (0x0600) +#define MCF5XXX_SR_IPL_7 (0x0700) +#define MCF5XXX_SR_X (0x0010) +#define MCF5XXX_SR_N (0x0008) +#define MCF5XXX_SR_Z (0x0004) +#define MCF5XXX_SR_V (0x0002) +#define MCF5XXX_SR_C (0x0001) + +#define MCF5XXX_CACR_CENB (0x80000000) +#define MCF5XXX_CACR_CPDI (0x10000000) +#define MCF5XXX_CACR_CPD (0x10000000) +#define MCF5XXX_CACR_CFRZ (0x08000000) +#define MCF5XXX_CACR_CINV (0x01000000) +#define MCF5XXX_CACR_DIDI (0x00800000) +#define MCF5XXX_CACR_DISD (0x00400000) +#define MCF5XXX_CACR_INVI (0x00200000) +#define MCF5XXX_CACR_INVD (0x00100000) +#define MCF5XXX_CACR_CEIB (0x00000400) +#define MCF5XXX_CACR_DCM_WR (0x00000000) +#define MCF5XXX_CACR_DCM_CB (0x00000100) +#define MCF5XXX_CACR_DCM_IP (0x00000200) +#define MCF5XXX_CACR_DCM (0x00000200) +#define MCF5XXX_CACR_DCM_II (0x00000300) +#define MCF5XXX_CACR_DBWE (0x00000100) +#define MCF5XXX_CACR_DWP (0x00000020) +#define MCF5XXX_CACR_EUST (0x00000010) +#define MCF5XXX_CACR_CLNF_00 (0x00000000) +#define MCF5XXX_CACR_CLNF_01 (0x00000002) +#define MCF5XXX_CACR_CLNF_10 (0x00000004) +#define MCF5XXX_CACR_CLNF_11 (0x00000006) + +#define MCF5XXX_ACR_AB(a) ((a)&0xFF000000) +#define MCF5XXX_ACR_AM(a) (((a)&0xFF000000) >> 8) +#define MCF5XXX_ACR_EN (0x00008000) +#define MCF5XXX_ACR_SM_USER (0x00000000) +#define MCF5XXX_ACR_SM_SUPER (0x00002000) +#define MCF5XXX_ACR_SM_IGNORE (0x00006000) +#define MCF5XXX_ACR_ENIB (0x00000080) +#define MCF5XXX_ACR_CM (0x00000040) +#define MCF5XXX_ACR_DCM_WR (0x00000000) +#define MCF5XXX_ACR_DCM_CB (0x00000020) +#define MCF5XXX_ACR_DCM_IP (0x00000040) +#define MCF5XXX_ACR_DCM_II (0x00000060) +#define MCF5XXX_ACR_CM (0x00000040) +#define MCF5XXX_ACR_BWE (0x00000020) +#define MCF5XXX_ACR_WP (0x00000004) + +#define MCF5XXX_RAMBAR_BA(a) ((a)&0xFFFFC000) +#define MCF5XXX_RAMBAR_PRI_00 (0x00000000) +#define MCF5XXX_RAMBAR_PRI_01 (0x00004000) +#define MCF5XXX_RAMBAR_PRI_10 (0x00008000) +#define MCF5XXX_RAMBAR_PRI_11 (0x0000C000) +#define MCF5XXX_RAMBAR_WP (0x00000100) +#define MCF5XXX_RAMBAR_CI (0x00000020) +#define MCF5XXX_RAMBAR_SC (0x00000010) +#define MCF5XXX_RAMBAR_SD (0x00000008) +#define MCF5XXX_RAMBAR_UC (0x00000004) +#define MCF5XXX_RAMBAR_UD (0x00000002) +#define MCF5XXX_RAMBAR_V (0x00000001) + +/***********************************************************************/ +/* + * The ColdFire family of processors has a simplified exception stack + * frame that looks like the following: + * + * 3322222222221111 111111 + * 1098765432109876 5432109876543210 + * 8 +----------------+----------------+ + * | Program Counter | + * 4 +----------------+----------------+ + * |FS/Fmt/Vector/FS| SR | + * SP --> 0 +----------------+----------------+ + * + * The stack self-aligns to a 4-byte boundary at an exception, with + * the FS/Fmt/Vector/FS field indicating the size of the adjustment + * (SP += 0,1,2,3 bytes). + */ + +#define MCF5XXX_RD_SF_FORMAT(PTR) \ + ((*((uint16 *)(PTR)) >> 12) & 0x00FF) + +#define MCF5XXX_RD_SF_VECTOR(PTR) \ + ((*((uint16 *)(PTR)) >> 2) & 0x00FF) + +#define MCF5XXX_RD_SF_FS(PTR) \ + ( ((*((uint16 *)(PTR)) & 0x0C00) >> 8) | (*((uint16 *)(PTR)) & 0x0003) ) + +#define MCF5XXX_SF_SR(PTR) *((uint16 *)(PTR)+1) +#define MCF5XXX_SF_PC(PTR) *((uint32 *)(PTR)+1) + +/********************************************************************/ +/* + * Functions provided by mcf5xxx.s + */ + +int asm_set_ipl (uint32); +void mcf5xxx_wr_cacr (uint32); +void mcf5xxx_wr_acr0 (uint32); +void mcf5xxx_wr_acr1 (uint32); +void mcf5xxx_wr_acr2 (uint32); +void mcf5xxx_wr_acr3 (uint32); +void mcf5xxx_wr_other_a7 (uint32); +void mcf5xxx_wr_other_sp (uint32); +void mcf5xxx_wr_vbr (uint32); +void mcf5xxx_wr_macsr (uint32); +void mcf5xxx_wr_mask (uint32); +void mcf5xxx_wr_acc0 (uint32); +void mcf5xxx_wr_accext01 (uint32); +void mcf5xxx_wr_accext23 (uint32); +void mcf5xxx_wr_acc1 (uint32); +void mcf5xxx_wr_acc2 (uint32); +void mcf5xxx_wr_acc3 (uint32); +void mcf5xxx_wr_sr (uint32); +void mcf5xxx_wr_rambar0 (uint32); +void mcf5xxx_wr_rambar1 (uint32); +void mcf5xxx_wr_mbar (uint32); +void mcf5xxx_wr_mbar0 (uint32); +void mcf5xxx_wr_mbar1 (uint32); + +/********************************************************************/ + +#endif /* _CPU_MCF5XXX_H */ + diff --git a/20080212/Demo/MCF5235_GCC/m5235-ram.ld b/20080212/Demo/MCF5235_GCC/m5235-ram.ld new file mode 100644 index 000000000..7119d3f51 --- /dev/null +++ b/20080212/Demo/MCF5235_GCC/m5235-ram.ld @@ -0,0 +1,119 @@ +STARTUP(system/crt0.o) +INPUT(system/vector.o) +OUTPUT_ARCH(m68k) +SEARCH_DIR(.) +GROUP(-lc -lgcc) + +__DYNAMIC = 0; + +MEMORY +{ + sdram (rwx) : ORIGIN = 0x00000000, LENGTH = 0x01000000 + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 + ipsbar (rwx) : ORIGIN = 0x40000000, LENGTH = 0x40000000 + flash (rwx) : ORIGIN = 0x80000000, LENGTH = 0x00080000 +} + +PROVIDE (__stack = 0x2000FFFC); + +SECTIONS +{ + .sdram : {} > sdram + .ipsbar : {} > ipsbar + .sram (NOLOAD) : { *(.vector_ram); *(.nbuf) } > sram + .flash : {} > flash + + .text : + { + __text_start = . ; + *(.vector_rom) + . = ALIGN (0x100); + *(.text) + . = ALIGN (16); + + *(.eh_frame) + . = ALIGN (16); + + *(.gnu.linkonce.t.*) + + . = ALIGN(0x4); + __CTOR_LIST__ = .; + ___CTOR_LIST__ = .; + LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2) + *(.ctors) + LONG(0) + __CTOR_END__ = .; + __DTOR_LIST__ = .; + ___DTOR_LIST__ = .; + LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2) + *(.dtors) + LONG(0) + __DTOR_END__ = .; + *(.rodata) + *(.rodata.*) + *(.gcc_except_table) + + . = ALIGN(0x2); + __INIT_SECTION__ = . ; + LONG (0x4e560000) /* linkw %fp,#0 */ + *(.init) + SHORT (0x4e5e) /* unlk %fp */ + SHORT (0x4e75) /* rts */ + + __FINI_SECTION__ = . ; + LONG (0x4e560000) /* linkw %fp,#0 */ + *(.fini) + SHORT (0x4e5e) /* unlk %fp */ + SHORT (0x4e75) /* rts */ + + *(.lit) + . = ALIGN(16); + _etext = .; + etext = .; + } > sdram + + .data : + { + copy_start = .; + *(.shdata) + *(.data) + *(.gnu.linkonce.d.*) + . = ALIGN (16); + _edata = .; + copy_end = .; + } > sdram + __data_load_start = LOADADDR(.data); + __data_load_end = __data_load_start + SIZEOF(.data); + + .bss : + { + . = ALIGN(0x4); + __bss_start = . ; + *(.shbss) + *(.bss) + *(COMMON) + _end = ALIGN (0x8); + __end = _end; + } > sdram + + .stab 0 (NOLOAD) : + { + *(.stab) + } + + .stabstr 0 (NOLOAD) : + { + *(.stabstr) + } +} + +__IPSBAR = ADDR(.ipsbar); + +__SDRAM = ADDR(.sdram); +__SDRAM_SIZE = SIZEOF(.sdram); + +__SRAM = ADDR(.sram); +__SRAM_SIZE = SIZEOF(.sram); + +__FLASH = ADDR(.flash); +__FLASH_SIZE = SIZEOF(.flash); diff --git a/20080212/Demo/MCF5235_GCC/m5235-rom.ld b/20080212/Demo/MCF5235_GCC/m5235-rom.ld new file mode 100644 index 000000000..7119d3f51 --- /dev/null +++ b/20080212/Demo/MCF5235_GCC/m5235-rom.ld @@ -0,0 +1,119 @@ +STARTUP(system/crt0.o) +INPUT(system/vector.o) +OUTPUT_ARCH(m68k) +SEARCH_DIR(.) +GROUP(-lc -lgcc) + +__DYNAMIC = 0; + +MEMORY +{ + sdram (rwx) : ORIGIN = 0x00000000, LENGTH = 0x01000000 + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 + ipsbar (rwx) : ORIGIN = 0x40000000, LENGTH = 0x40000000 + flash (rwx) : ORIGIN = 0x80000000, LENGTH = 0x00080000 +} + +PROVIDE (__stack = 0x2000FFFC); + +SECTIONS +{ + .sdram : {} > sdram + .ipsbar : {} > ipsbar + .sram (NOLOAD) : { *(.vector_ram); *(.nbuf) } > sram + .flash : {} > flash + + .text : + { + __text_start = . ; + *(.vector_rom) + . = ALIGN (0x100); + *(.text) + . = ALIGN (16); + + *(.eh_frame) + . = ALIGN (16); + + *(.gnu.linkonce.t.*) + + . = ALIGN(0x4); + __CTOR_LIST__ = .; + ___CTOR_LIST__ = .; + LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2) + *(.ctors) + LONG(0) + __CTOR_END__ = .; + __DTOR_LIST__ = .; + ___DTOR_LIST__ = .; + LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2) + *(.dtors) + LONG(0) + __DTOR_END__ = .; + *(.rodata) + *(.rodata.*) + *(.gcc_except_table) + + . = ALIGN(0x2); + __INIT_SECTION__ = . ; + LONG (0x4e560000) /* linkw %fp,#0 */ + *(.init) + SHORT (0x4e5e) /* unlk %fp */ + SHORT (0x4e75) /* rts */ + + __FINI_SECTION__ = . ; + LONG (0x4e560000) /* linkw %fp,#0 */ + *(.fini) + SHORT (0x4e5e) /* unlk %fp */ + SHORT (0x4e75) /* rts */ + + *(.lit) + . = ALIGN(16); + _etext = .; + etext = .; + } > sdram + + .data : + { + copy_start = .; + *(.shdata) + *(.data) + *(.gnu.linkonce.d.*) + . = ALIGN (16); + _edata = .; + copy_end = .; + } > sdram + __data_load_start = LOADADDR(.data); + __data_load_end = __data_load_start + SIZEOF(.data); + + .bss : + { + . = ALIGN(0x4); + __bss_start = . ; + *(.shbss) + *(.bss) + *(COMMON) + _end = ALIGN (0x8); + __end = _end; + } > sdram + + .stab 0 (NOLOAD) : + { + *(.stab) + } + + .stabstr 0 (NOLOAD) : + { + *(.stabstr) + } +} + +__IPSBAR = ADDR(.ipsbar); + +__SDRAM = ADDR(.sdram); +__SDRAM_SIZE = SIZEOF(.sdram); + +__SRAM = ADDR(.sram); +__SRAM_SIZE = SIZEOF(.sram); + +__FLASH = ADDR(.flash); +__FLASH_SIZE = SIZEOF(.flash); diff --git a/20080212/Demo/MCF5235_GCC/m5235.gdb b/20080212/Demo/MCF5235_GCC/m5235.gdb new file mode 100644 index 000000000..545fbea31 --- /dev/null +++ b/20080212/Demo/MCF5235_GCC/m5235.gdb @@ -0,0 +1,134 @@ +set $IPSBAR = 0x40000000 + +set $DCR = $IPSBAR + 0x000040 +set $DACR0 = $IPSBAR + 0x000048 +set $DMR0 = $IPSBAR + 0x00004C + +set $CSAR0 = $IPSBAR + 0x000080 +set $CSMR0 = $IPSBAR + 0x000084 +set $CSCR0 = $IPSBAR + 0x00008A + +set $PAR_SDRAM = $IPSBAR + 0x100046 +set $PAR_AD = $IPSBAR + 0x100040 + +set $WCR = $IPSBAR + 0x140000 + +define delay + set $delay = 0 + while ($delay < 20000) + set $delay += 1 + end +end + +define delay_memsync + set $delay = 0 + while ($delay < 10000) + set $delay += 1 + end +end + +define setup-cs + # 2MB FLASH on CS0 at 0x80000000 + set *(unsigned short *)$CSAR0 = 0x00008000 + set *(unsigned long *)$CSMR0 = 0x001F0101 + set *(unsigned short *)$CSCR0 = 0x00001980 +end + +define setup-sdram + # Set PAR_SDRAM to allow SDRAM signals to be enable + set *(unsigned char *)$PAR_SDRAM = 0x3F + # Set PAR_AD to allow 32-bit SDRAM if the external boot device is 16-bit + set *(unsigned char *)$PAR_AD = 0xE1 + + # SDRAM + set *(unsigned short *)$DCR = 0x0446 + set *(unsigned long *)$DACR0 = 0x00001300 + set *(unsigned long *)$DMR0 = 0x00FC0001 + + # Set IP in DACR and init precharge. + set *(unsigned long *)$DACR0 |= 0x00000008 + set *(0x00000000) = 0xAA55AA55 + delay + + # Set RE in DACR + set *(unsigned long *)$DACR0 |= 0x00008000 + # Issue IMRS + set *(unsigned long *)$DACR0 |= 0x00000040 + set *(0x00000400) = 0xAA55AA55 + delay +end + +define setup-other + # Turn Off WCR + set *(unsigned char *)$WCR = 0x00 +end + +define setup-and-load + bdm-reset + + # Set VBR to the vector table. + set $vbr = 0x00000000 + # Set internal SRAM to start at 0x20000000 + set $rambar = 0x20000001 + + setup-other + setup-cs + setup-sdram +end + +define debug-sramtest + set $srambase = 0x20000000 + set $sramsize = 0x00010000 + set $j = 0 + printf "Testing SRAM : 0x%08X - 0x%08X\n", $srambase, ($srambase + $sramsize) + set $i = $srambase + while $i < ($srambase + $sramsize) + set *(unsigned long *)($i) = 0xAA55AA55 + delay_memsync + if 0xAA55AA55 != *(unsigned long *)$i + printf " 0x%08X = FAIL\n", $i + else + printf " 0x%08X = OK", $i + if $j % 4 == 3 + printf "\n" + end + set $j = $j + 1 + end + set $i = $i + 0x400 + end +en + +define debug-ramtest + set $sdrambase = 0x00000000 + set $sdramsize = 0x01000000 + set $j = 0 + printf "Testing SDRAM : 0x%08X - 0x%08X\n", $sdrambase, ($sdrambase + $sdramsize) + set $i = $sdrambase + while $i < ($sdrambase + $sdramsize) + set *(unsigned long *)($i) = 0xAA55AA55 + delay_memsync + if 0xAA55AA55 != *(unsigned long *)$i + printf " 0x%08X = FAIL\n", $i + else + printf " 0x%08X = OK", $i + if $j % 4 == 3 + printf "\n" + end + set $j = $j + 1 + end + set $i = $i + 0x10000 + end + printf "\n" +end + +define execute + set $pc = *(long *)0x00000004 + tbreak main + tk gdbtk_update +end + +define debug-printexception + printf "vector: %d", *(unsigned short *)$sp >> 2 &0x1F + printf "old pc: 0x%08x", *(unsigned long *)($sp + 4) + printf "old sr: 0x%02x", *(unsigned short *)($sp + 2) +end diff --git a/20080212/Demo/MCF5235_GCC/system/crt0.S b/20080212/Demo/MCF5235_GCC/system/crt0.S new file mode 100644 index 000000000..5e8c06615 --- /dev/null +++ b/20080212/Demo/MCF5235_GCC/system/crt0.S @@ -0,0 +1,125 @@ +/* + FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + .title "crt0.S" + + .extern main + .extern __stack + .extern __bss_start + .extern __text_start + .extern init_main + + .equ MCF5XXX_RAMBAR_SPV, 0x00000200 + .equ MCF5XXX_RAMBAR_V, 0x00000001 + .global start + + .align 4 +debug: + .word 0x2C80 /* write to CSR */ + .word 0x0010 + .word 0x0400 + .word 0x0000 + +start: + /* disable all interrupts on startup. */ + move.w #0x2700, sr + + /* prepare internal SRAM. */ + move.l #__SRAM, d0 + ori.l #( MCF5XXX_RAMBAR_SPV | MCF5XXX_RAMBAR_V ), d0 + movec d0, rambar + + /* prepare stack and frame pointer. */ + move.l #__stack, sp + link a6, #-8 + + /* initialize hardware. */ + jsr init_main + + /* zero out the bss section. */ + move.l #__bss_start, d1 + move.l #_end, d0 + cmp.l d0, d1 + jbeq 3f + move.l d1, a0 + sub.l d1, d0 + subq.l #1, d0 +2: + clr.b (a0)+ + subq.l #1, d0 + jbpl 2b +3: + + /* Relocate the data section. */ + move.l #__data_load_start, %a0 /* .data in ROM */ + move.l #copy_start, %a1 /* .data in RAM */ + + /* Test if the two sections overlap. This is the case when we are working + * with the debugger and the debugger loads the .data section. + */ + cmpa.l %a0, %a1 + beq 2f +1: + /* Have we already copied everything. */ + cmpa.l #__data_load_end, %a0 + beq 2f + move.b (%a0)+, (%a1)+ + bra 1b + +2: + + /* C library */ + move.l #__FINI_SECTION__, -(%sp) + jsr atexit + jsr __INIT_SECTION__ + + /* call main(int argc, char *argv[] */ + move.l #0, -(sp) + move.l #0, -(sp) + move.l #0, -(sp) + jsr main + lea (sp, 12), %sp + + /* stop on exit from main. */ +1: + halt + diff --git a/20080212/Demo/MCF5235_GCC/system/init.c b/20080212/Demo/MCF5235_GCC/system/init.c new file mode 100644 index 000000000..51f75f65c --- /dev/null +++ b/20080212/Demo/MCF5235_GCC/system/init.c @@ -0,0 +1,753 @@ +/* + FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#include "mcf5xxx.h" +#include "mcf523x.h" + +/* Function prototypes */ +void init_main( void ); +static void disable_interrupts( void ); +static void disable_watchdog_timer( void ); +static void disable_cache( void ); +static void init_ipsbar( void ); +static void init_basics( void ); +static void init_clock_config( void ); +static void init_chip_selects( void ); +static void init_bus_config( void ); +static void init_cache( void ); +static void init_eport( void ); +static void init_flexcan( void ); +static void init_power_management( void ); +static void init_dma_timers( void ); +static void init_interrupt_timers( void ); +static void init_watchdog_timers( void ); +static void init_pin_assignments( void ); +static void init_sdram_controller( void ); +static void init_interrupt_controller( void ); + + +/********************************************************************* +* init_main - Main entry point for initialisation code * +**********************************************************************/ +void +init_main( void ) +{ + + /* Initialise base address of peripherals, VBR, etc */ + init_ipsbar( ); + init_basics( ); + init_clock_config( ); + + /* Disable interrupts, watchdog timer, cache */ + disable_interrupts( ); + disable_watchdog_timer( ); + disable_cache( ); + + /* Initialise individual modules */ + init_chip_selects( ); + init_bus_config( ); + init_cache( ); + init_eport( ); + init_flexcan( ); + init_power_management( ); + init_dma_timers( ); + init_interrupt_timers( ); + init_watchdog_timers( ); + init_pin_assignments( ); + init_sdram_controller( ); + + /* Initialise interrupt controller */ + init_interrupt_controller( ); +} + +/********************************************************************* +* disable_interrupts - Disable all interrupt sources * +**********************************************************************/ +static void +disable_interrupts( void ) +{ + vuint8 *p; + int i; + + + /* Set ICR008-ICR063 to 0x0 */ + p = ( vuint8 * ) & MCF_INTC0_ICR8; + for( i = 8; i <= 63; i++ ) + *p++ = 0x0; + + /* Set ICR108-ICR163 to 0x0 */ + p = ( vuint8 * ) & MCF_INTC1_ICR8; + for( i = 108; i <= 163; i++ ) + *p++ = 0x0; +} + + +/********************************************************************* +* disable_watchdog_timer - Disable system watchdog timer * +**********************************************************************/ +static void +disable_watchdog_timer( void ) +{ + + /* Disable Core Watchdog Timer */ + MCF_SCM_CWCR = 0; +} + +/********************************************************************* +* disable_cache - Disable and invalidate cache * +**********************************************************************/ +static void +disable_cache( void ) +{ + asm ( "move.l #0x01000000, %d0" ); + asm ( "movec %d0, %CACR" ); +} + +/********************************************************************* +* init_basics - Configuration Information & VBR * +**********************************************************************/ +static void +init_basics( void ) +{ + int i; + extern uint32 __RAMVEC[]; + extern uint32 __ROMVEC[]; + + /* Transfer size not driven on SIZ[1:0] pins during external cycles + Processor Status (PST) and Debug Data (DDATA) functions disabled + Bus monitor disabled + Output pads configured for full strength + */ + MCF_CCM_CCR = ( 0x1 << 15 ) | MCF_CCM_CCR_BME; + + /* Set up RAM vectors */ + for( i = 0; i < 256; i++ ) + + { + __RAMVEC[i] = __ROMVEC[i]; + } + asm( "move.l %0,%%d0": :"i"( __RAMVEC ) ); + asm( "movec %d0,%vbr" ); +} + + +/********************************************************************* +* init_clock_config - Clock Module * +**********************************************************************/ +static void +init_clock_config( void ) +{ + /* Clock module uses normal PLL mode with 25.0000 MHz external reference (Fref) + MFD = 0, RFD = 1 + Bus clock frequency = 25.00 MHz + Processor clock frequency = 2 x bus clock = 50.00 MHz + Frequency Modulation disabled + Loss of clock detection disabled + Reset/Interrupt on loss of lock disabled + */ + MCF_FMPLL_SYNCR = 0x00100000; /* Set RFD=RFD+1 to avoid frequency overshoot */ + while( ( MCF_FMPLL_SYNSR & 0x08 ) == 0 ) /* Wait for PLL to lock */ + ; + MCF_FMPLL_SYNCR = 0x00080000; /* Set desired RFD */ + while( ( MCF_FMPLL_SYNSR & 0x08 ) == 0 ) /* Wait for PLL to lock */ + ; +} + + +/********************************************************************* +* init_ipsbar - Internal Peripheral System Base Address (IPSBAR) * +**********************************************************************/ +static void +init_ipsbar( void ) +{ + extern int __SRAM; + + /* Base address of internal peripherals (IPSBAR) = 0x40000000 + + Note: Processor powers up with IPS base address = 0x40000000 + Write to IPS base + 0x00000000 to set new value + */ + *( vuint32 * ) 0x40000000 = ( vuint32 ) __IPSBAR + 1; + + /* Configure RAMBAR in SCM module and allow dual-ported access. */ + MCF_SCM_RAMBAR = ( uint32 ) &__SRAM | MCF_SCM_RAMBAR_BDE; +} + +/********************************************************************* +* init_chip_selects - Chip Select Module * +**********************************************************************/ +static void +init_chip_selects( void ) +{ + extern void __FLASH; + uint32 FLASH_ADDR = (uint32)&__FLASH; + + /* Chip Select 0 - External Flash */ + MCF_CS_CSAR0 = MCF_CS_CSAR_BA( FLASH_ADDR ); + MCF_CS_CSCR0 = ( 0 + | MCF_CS_CSCR_IWS( 6 ) + | MCF_CS_CSCR_AA | MCF_CS_CSCR_PS_16 ); + MCF_CS_CSMR0 = MCF_CS_CSMR_BAM_2M | MCF_CS_CSMR_V; + + /* Chip Select 1 disabled (CSMR1[V] = 0) */ + MCF_CS_CSAR1 = 0; + MCF_CS_CSMR1 = 0; + MCF_CS_CSCR1 = 0; + + /* Chip Select 2 disabled (CSMR2[V] = 0) */ + MCF_CS_CSAR2 = 0; + MCF_CS_CSMR2 = 0; + MCF_CS_CSCR2 = 0; + + /* Chip Select 3 disabled (CSMR3[V] = 0) */ + MCF_CS_CSAR3 = 0; + MCF_CS_CSMR3 = 0; + MCF_CS_CSCR3 = 0; + + /* Chip Select 4 disabled (CSMR4[V] = 0) */ + MCF_CS_CSAR4 = 0; + MCF_CS_CSMR4 = 0; + MCF_CS_CSCR4 = 0; + + /* Chip Select 5 disabled (CSMR5[V] = 0) */ + MCF_CS_CSAR5 = 0; + MCF_CS_CSMR5 = 0; + MCF_CS_CSCR5 = 0; + + /* Chip Select 6 disabled (CSMR6[V] = 0) */ + MCF_CS_CSAR6 = 0; + MCF_CS_CSMR6 = 0; + MCF_CS_CSCR6 = 0; + + /* Chip Select 7 disabled (CSMR7[V] = 0) */ + MCF_CS_CSAR7 = 0; + MCF_CS_CSMR7 = 0; + MCF_CS_CSCR7 = 0; +} + +/********************************************************************* +* init_bus_config - Internal Bus Arbitration * +**********************************************************************/ +static void +init_bus_config( void ) +{ + + /* Use round robin arbitration scheme + Assigned priorities (highest first): + Ethernet + DMA Controller + ColdFire Core + DMA bandwidth control disabled + Park on last active bus master + */ + MCF_SCM_MPARK = + MCF_SCM_MPARK_M3_PRTY( 0x3 ) | MCF_SCM_MPARK_M2_PRTY( 0x2 ) | + MCF_SCM_MPARK_M1_PRTY( 0x1 ); +} + +/********************************************************************* +* init_cache - Instruction/Data Cache * +**********************************************************************/ +static void +init_cache( void ) +{ + /* Configured as split cache: 4 KByte instruction cache and 4 Kbyte data cache + ACR0: Don't cache accesses to 16 MB memory region at address $20000000 + ACR1: Don't cache accesses to 1 GB memory region at address $40000000 + CACR: Cache accesses to the rest of memory + */ + asm("move.l #0x80000000,%d0"); + asm("movec %d0,%CACR"); + asm("move.l #0x2000c040,%d0"); + asm("movec %d0,%ACR0"); + asm("move.l #0x403fc040,%d0"); + asm("movec %d0,%ACR1"); + + /* Instruction/Data cache disabled. */ + //asm( "move.l #0x00000000, %d0" ); + //asm( "movec %d0,%cacr" ); +} + +/********************************************************************* +* init_eport - Edge Port Module (EPORT) * +**********************************************************************/ +static void +init_eport( void ) +{ + + /* Pins 1-7 configured as GPIO inputs */ + MCF_EPORT_EPPAR = 0; + MCF_EPORT_EPDDR = 0; + MCF_EPORT_EPIER = 0; +} + +/********************************************************************* +* init_flexcan - FlexCAN Module * +**********************************************************************/ +static void +init_flexcan( void ) +{ + + /* FlexCAN controller 0 disabled (CANMCR0[MDIS]=1) */ + MCF_CAN_IMASK0 = 0; + MCF_CAN_RXGMASK0 = MCF_CAN_RXGMASK_MI( 0x1fffffff ); + MCF_CAN_RX14MASK0 = MCF_CAN_RX14MASK_MI( 0x1fffffff ); + MCF_CAN_RX15MASK0 = MCF_CAN_RX15MASK_MI( 0x1fffffff ); + MCF_CAN_CANCTRL0 = 0; + MCF_CAN_CANMCR0 = + MCF_CAN_CANMCR_MDIS | MCF_CAN_CANMCR_FRZ | MCF_CAN_CANMCR_HALT | + MCF_CAN_CANMCR_SUPV | MCF_CAN_CANMCR_MAXMB( 0xf ); + + /* FlexCAN controller 1 disabled (CANMCR1[MDIS]=1) */ + MCF_CAN_IMASK1 = 0; + MCF_CAN_RXGMASK1 = MCF_CAN_RXGMASK_MI( 0x1fffffff ); + MCF_CAN_RX14MASK1 = MCF_CAN_RX14MASK_MI( 0x1fffffff ); + MCF_CAN_RX15MASK1 = MCF_CAN_RX15MASK_MI( 0x1fffffff ); + MCF_CAN_CANCTRL1 = 0; + MCF_CAN_CANMCR1 = + MCF_CAN_CANMCR_MDIS | MCF_CAN_CANMCR_FRZ | MCF_CAN_CANMCR_HALT | + MCF_CAN_CANMCR_SUPV | MCF_CAN_CANMCR_MAXMB( 0xf ); +} + +/********************************************************************* +* init_power_management - Power Management * +**********************************************************************/ +static void +init_power_management( void ) +{ + + /* On executing STOP instruction, processor enters RUN mode + Mode is exited when an interrupt of level 1 or higher is received + */ + MCF_SCM_LPICR = MCF_SCM_LPICR_ENBSTOP; + MCF_CCM_LPCR = 0; +} + +/********************************************************************* +* init_sdram_controller - SDRAM Controller * +**********************************************************************/ +static void +init_sdram_controller( void ) +{ + extern void __SDRAM; + uint32 SDRAM_ADDR = (uint32)&__SDRAM; + int i; + + + /* + * Check to see if the SDRAM has already been initialized + * by a run control tool + */ + if( !( MCF_SDRAMC_DACR0 & MCF_SDRAMC_DACR0_RE ) ) + { + /* Initialize DRAM Control Register: DCR */ + MCF_SDRAMC_DCR = ( MCF_SDRAMC_DCR_RTIM( 1 ) | + MCF_SDRAMC_DCR_RC( ( 15 * FSYS_2 ) >> 4 ) ); + + /* Initialize DACR0 */ + MCF_SDRAMC_DACR0 = ( MCF_SDRAMC_DACR0_BA( SDRAM_ADDR >> 18UL ) | + MCF_SDRAMC_DACR0_CASL( 1 ) | + MCF_SDRAMC_DACR0_CBM( 3 ) | + MCF_SDRAMC_DACR0_PS( 0 ) ); + + /* Initialize DMR0 */ + MCF_SDRAMC_DMR0 = ( MCF_SDRAMC_DMR_BAM_16M | MCF_SDRAMC_DMR0_V ); + + /* Set IP (bit 3) in DACR */ + MCF_SDRAMC_DACR0 |= MCF_SDRAMC_DACR0_IP; + + /* Wait 30ns to allow banks to precharge */ + for( i = 0; i < 5; i++ ) + { + asm volatile ( " nop" ); + } + /* Write to this block to initiate precharge */ + *( uint32 * ) ( SDRAM_ADDR ) = 0xA5A59696; + + /* Set RE (bit 15) in DACR */ + MCF_SDRAMC_DACR0 |= MCF_SDRAMC_DACR0_RE; + + /* Wait for at least 8 auto refresh cycles to occur */ + for( i = 0; i < 2000; i++ ) + { + asm volatile ( "nop" ); + } + /* Finish the configuration by issuing the IMRS. */ + MCF_SDRAMC_DACR0 |= MCF_SDRAMC_DACR0_MRS; + + /* Write to the SDRAM Mode Register */ + *( uint32 * ) ( SDRAM_ADDR + 0x400 ) = 0xA5A59696; + } +} + +/********************************************************************* +* init_dma_timers - DMA Timer Modules * +**********************************************************************/ +static void +init_dma_timers( void ) +{ + + /* DMA Timer 0 disabled (DTMR0[RST] = 0) */ + MCF_TIMER_DTMR0 = 0; + MCF_TIMER_DTXMR0 = 0; + MCF_TIMER_DTRR0 = 0xffffffff; + + /* DMA Timer 1 disabled (DTMR1[RST] = 0) */ + MCF_TIMER_DTMR1 = 0; + MCF_TIMER_DTXMR1 = 0; + MCF_TIMER_DTRR1 = 0xffffffff; + + /* DMA Timer 2 disabled (DTMR2[RST] = 0) */ + MCF_TIMER_DTMR2 = 0; + MCF_TIMER_DTXMR2 = 0; + MCF_TIMER_DTRR2 = 0xffffffff; + + /* DMA Timer 3 disabled (DTMR3[RST] = 0) */ + MCF_TIMER_DTMR3 = 0; + MCF_TIMER_DTXMR3 = 0; + MCF_TIMER_DTRR3 = 0xffffffff; +} + +/********************************************************************** +* init_interrupt_timers - Programmable Interrupt Timer (PIT) Modules * +***********************************************************************/ +static void +init_interrupt_timers( void ) +{ + + /* PIT0 disabled (PCSR0[EN]=0) */ + MCF_PIT_PCSR0 = 0; + + /* PIT1 disabled (PCSR1[EN]=0) */ + MCF_PIT_PCSR1 = 0; + + /* PIT2 disabled (PCSR2[EN]=0) */ + MCF_PIT_PCSR2 = 0; + + /* PIT3 disabled (PCSR3[EN]=0) */ + MCF_PIT_PCSR3 = 0; +} + +/********************************************************************* +* init_watchdog_timers - Watchdog Timer Modules * +**********************************************************************/ +static void +init_watchdog_timers( void ) +{ + + /* Watchdog Timer disabled (WCR[EN]=0) + NOTE: WCR and WMR cannot be written again until after the + processor is reset. + */ + MCF_WTM_WCR = MCF_WTM_WCR_WAIT | MCF_WTM_WCR_DOZE | MCF_WTM_WCR_HALTED; + MCF_WTM_WMR = 0xffff; + + /* Core Watchdog Timer disabled (CWCR[CWE]=0) */ + MCF_SCM_CWCR = 0; +} + +/********************************************************************* +* init_interrupt_controller - Interrupt Controller * +**********************************************************************/ +static void +init_interrupt_controller( void ) +{ + + /* Configured interrupt sources in order of priority... + Level 7: External interrupt /IRQ7, (initially masked) + Level 6: External interrupt /IRQ6, (initially masked) + Level 5: External interrupt /IRQ5, (initially masked) + Level 4: External interrupt /IRQ4, (initially masked) + Level 3: External interrupt /IRQ3, (initially masked) + Level 2: External interrupt /IRQ2, (initially masked) + Level 1: External interrupt /IRQ1, (initially masked) + */ + MCF_INTC0_ICR1 = 0; + MCF_INTC0_ICR2 = 0; + MCF_INTC0_ICR3 = 0; + MCF_INTC0_ICR4 = 0; + MCF_INTC0_ICR5 = 0; + MCF_INTC0_ICR6 = 0; + MCF_INTC0_ICR7 = 0; + MCF_INTC0_ICR8 = 0; + MCF_INTC0_ICR9 = 0; + MCF_INTC0_ICR10 = 0; + MCF_INTC0_ICR11 = 0; + MCF_INTC0_ICR12 = 0; + MCF_INTC0_ICR13 = 0; + MCF_INTC0_ICR14 = 0; + MCF_INTC0_ICR15 = 0; + MCF_INTC0_ICR17 = 0; + MCF_INTC0_ICR18 = 0; + MCF_INTC0_ICR19 = 0; + MCF_INTC0_ICR20 = 0; + MCF_INTC0_ICR21 = 0; + MCF_INTC0_ICR22 = 0; + MCF_INTC0_ICR23 = 0; + MCF_INTC0_ICR24 = 0; + MCF_INTC0_ICR25 = 0; + MCF_INTC0_ICR26 = 0; + MCF_INTC0_ICR27 = 0; + MCF_INTC0_ICR28 = 0; + MCF_INTC0_ICR29 = 0; + MCF_INTC0_ICR30 = 0; + MCF_INTC0_ICR31 = 0; + MCF_INTC0_ICR32 = 0; + MCF_INTC0_ICR33 = 0; + MCF_INTC0_ICR34 = 0; + MCF_INTC0_ICR35 = 0; + MCF_INTC0_ICR36 = 0; + MCF_INTC0_ICR37 = 0; + MCF_INTC0_ICR38 = 0; + MCF_INTC0_ICR39 = 0; + MCF_INTC0_ICR40 = 0; + MCF_INTC0_ICR41 = 0; + MCF_INTC0_ICR42 = 0; + MCF_INTC0_ICR43 = 0; + MCF_INTC0_ICR44 = 0; + MCF_INTC0_ICR45 = 0; + MCF_INTC0_ICR46 = 0; + MCF_INTC0_ICR47 = 0; + MCF_INTC0_ICR48 = 0; + MCF_INTC0_ICR49 = 0; + MCF_INTC0_ICR50 = 0; + MCF_INTC0_ICR51 = 0; + MCF_INTC0_ICR52 = 0; + MCF_INTC0_ICR53 = 0; + MCF_INTC0_ICR54 = 0; + MCF_INTC0_ICR55 = 0; + MCF_INTC0_ICR56 = 0; + MCF_INTC0_ICR57 = 0; + MCF_INTC0_ICR58 = 0; + MCF_INTC0_ICR59 = 0; + MCF_INTC0_ICR60 = 0; + MCF_INTC1_ICR8 = 0; + MCF_INTC1_ICR9 = 0; + MCF_INTC1_ICR10 = 0; + MCF_INTC1_ICR11 = 0; + MCF_INTC1_ICR12 = 0; + MCF_INTC1_ICR13 = 0; + MCF_INTC1_ICR14 = 0; + MCF_INTC1_ICR15 = 0; + MCF_INTC1_ICR16 = 0; + MCF_INTC1_ICR17 = 0; + MCF_INTC1_ICR18 = 0; + MCF_INTC1_ICR19 = 0; + MCF_INTC1_ICR20 = 0; + MCF_INTC1_ICR21 = 0; + MCF_INTC1_ICR22 = 0; + MCF_INTC1_ICR23 = 0; + MCF_INTC1_ICR24 = 0; + MCF_INTC1_ICR25 = 0; + MCF_INTC1_ICR27 = 0; + MCF_INTC1_ICR28 = 0; + MCF_INTC1_ICR29 = 0; + MCF_INTC1_ICR30 = 0; + MCF_INTC1_ICR31 = 0; + MCF_INTC1_ICR32 = 0; + MCF_INTC1_ICR33 = 0; + MCF_INTC1_ICR34 = 0; + MCF_INTC1_ICR35 = 0; + MCF_INTC1_ICR36 = 0; + MCF_INTC1_ICR37 = 0; + MCF_INTC1_ICR38 = 0; + MCF_INTC1_ICR39 = 0; + MCF_INTC1_ICR40 = 0; + MCF_INTC1_ICR41 = 0; + MCF_INTC1_ICR42 = 0; + MCF_INTC1_ICR59 = 0; + MCF_INTC0_IMRH = 0xffffffff; + MCF_INTC0_IMRL = + MCF_INTC0_IMRL_INT_MASK31 | MCF_INTC0_IMRL_INT_MASK30 | + MCF_INTC0_IMRL_INT_MASK29 | MCF_INTC0_IMRL_INT_MASK28 | + MCF_INTC0_IMRL_INT_MASK27 | MCF_INTC0_IMRL_INT_MASK26 | + MCF_INTC0_IMRL_INT_MASK25 | MCF_INTC0_IMRL_INT_MASK24 | + MCF_INTC0_IMRL_INT_MASK23 | MCF_INTC0_IMRL_INT_MASK22 | + MCF_INTC0_IMRL_INT_MASK21 | MCF_INTC0_IMRL_INT_MASK20 | + MCF_INTC0_IMRL_INT_MASK19 | MCF_INTC0_IMRL_INT_MASK18 | + MCF_INTC0_IMRL_INT_MASK17 | MCF_INTC0_IMRL_INT_MASK16 | + MCF_INTC0_IMRL_INT_MASK15 | MCF_INTC0_IMRL_INT_MASK14 | + MCF_INTC0_IMRL_INT_MASK13 | MCF_INTC0_IMRL_INT_MASK12 | + MCF_INTC0_IMRL_INT_MASK11 | MCF_INTC0_IMRL_INT_MASK10 | + MCF_INTC0_IMRL_INT_MASK9 | MCF_INTC0_IMRL_INT_MASK8 | + MCF_INTC0_IMRL_INT_MASK7 | MCF_INTC0_IMRL_INT_MASK6 | + MCF_INTC0_IMRL_INT_MASK5 | MCF_INTC0_IMRL_INT_MASK4 | + MCF_INTC0_IMRL_INT_MASK3 | MCF_INTC0_IMRL_INT_MASK2 | + MCF_INTC0_IMRL_INT_MASK1; + MCF_INTC1_IMRH = 0xffffffff; + MCF_INTC1_IMRL = + MCF_INTC1_IMRL_INT_MASK31 | MCF_INTC1_IMRL_INT_MASK30 | + MCF_INTC1_IMRL_INT_MASK29 | MCF_INTC1_IMRL_INT_MASK28 | + MCF_INTC1_IMRL_INT_MASK27 | MCF_INTC1_IMRL_INT_MASK26 | + MCF_INTC1_IMRL_INT_MASK25 | MCF_INTC1_IMRL_INT_MASK24 | + MCF_INTC1_IMRL_INT_MASK23 | MCF_INTC1_IMRL_INT_MASK22 | + MCF_INTC1_IMRL_INT_MASK21 | MCF_INTC1_IMRL_INT_MASK20 | + MCF_INTC1_IMRL_INT_MASK19 | MCF_INTC1_IMRL_INT_MASK18 | + MCF_INTC1_IMRL_INT_MASK17 | MCF_INTC1_IMRL_INT_MASK16 | + MCF_INTC1_IMRL_INT_MASK15 | MCF_INTC1_IMRL_INT_MASK14 | + MCF_INTC1_IMRL_INT_MASK13 | MCF_INTC1_IMRL_INT_MASK12 | + MCF_INTC1_IMRL_INT_MASK11 | MCF_INTC1_IMRL_INT_MASK10 | + MCF_INTC1_IMRL_INT_MASK9 | MCF_INTC1_IMRL_INT_MASK8 | + MCF_INTC1_IMRL_INT_MASK7 | MCF_INTC1_IMRL_INT_MASK6 | + MCF_INTC1_IMRL_INT_MASK5 | MCF_INTC1_IMRL_INT_MASK4 | + MCF_INTC1_IMRL_INT_MASK3 | MCF_INTC1_IMRL_INT_MASK2 | + MCF_INTC1_IMRL_INT_MASK1; +} + +/********************************************************************* +* init_pin_assignments - Pin Assignment and General Purpose I/O * +**********************************************************************/ +static void +init_pin_assignments( void ) +{ + + /* Pin assignments for port ADDR + Pins are all GPIO inputs + */ + MCF_GPIO_PDDR_APDDR = 0; + MCF_GPIO_PAR_AD = MCF_GPIO_PAR_AD_PAR_ADDR23 + | MCF_GPIO_PAR_AD_PAR_ADDR22 + | MCF_GPIO_PAR_AD_PAR_ADDR21 | MCF_GPIO_PAR_AD_PAR_DATAL; + + /* Pin assignments for ports DATAH and DATAL + Pins are all GPIO inputs + */ + MCF_GPIO_PDDR_DATAH = 0; + MCF_GPIO_PDDR_DATAL = 0; + + /* Pin assignments for port BUSCTL + Pin /OE : External bus output enable, /OE + Pin /TA : External bus transfer acknowledge, /TA + Pin /TEA : External bus transfer error acknowledge, /TEA + Pin R/W : External bus read/write indication, R/W + Pin TSIZ1 : External bus transfer size TSIZ1 or DMA acknowledge /DACK1 + Pin TSIZ0 : External bus transfer size TSIZ0 or DMA acknowledge /DACK0 + Pin /TS : External bus transfer start, /TS + Pin /TIP : External bus transfer in progess, /TIP + */ + MCF_GPIO_PDDR_BUSCTL = 0; + MCF_GPIO_PAR_BUSCTL = + MCF_GPIO_PAR_BUSCTL_PAR_OE | MCF_GPIO_PAR_BUSCTL_PAR_TA | + MCF_GPIO_PAR_BUSCTL_PAR_TEA( 0x3 ) | MCF_GPIO_PAR_BUSCTL_PAR_RWB | + MCF_GPIO_PAR_BUSCTL_PAR_TSIZ1 | MCF_GPIO_PAR_BUSCTL_PAR_TSIZ0 | + MCF_GPIO_PAR_BUSCTL_PAR_TS( 0x3 ) | + MCF_GPIO_PAR_BUSCTL_PAR_TIP( 0x3 ); + + /* Pin assignments for port BS + Pin /BS3 : External byte strobe /BS3 + Pin /BS2 : External byte strobe /BS2 + Pin /BS1 : External byte strobe /BS1 + Pin /BS0 : External byte strobe /BS0 + */ + MCF_GPIO_PDDR_BS = 0; + MCF_GPIO_PAR_BS = + MCF_GPIO_PAR_BS_PAR_BS3 | MCF_GPIO_PAR_BS_PAR_BS2 | + MCF_GPIO_PAR_BS_PAR_BS1 | MCF_GPIO_PAR_BS_PAR_BS0; + + /* Pin assignments for port CS + Pin /CS7 : Chip select /CS7 + Pin /CS6 : Chip select /CS6 + Pin /CS5 : Chip select /CS5 + Pin /CS4 : Chip select /CS4 + Pin /CS3 : Chip select /CS3 + Pin /CS2 : Chip select /CS2 + Pin /CS1 : Chip select /CS1 + */ + MCF_GPIO_PDDR_CS = 0; + MCF_GPIO_PAR_CS = + MCF_GPIO_PAR_CS_PAR_CS7 | MCF_GPIO_PAR_CS_PAR_CS6 | + MCF_GPIO_PAR_CS_PAR_CS5 | MCF_GPIO_PAR_CS_PAR_CS4 | + MCF_GPIO_PAR_CS_PAR_CS3 | MCF_GPIO_PAR_CS_PAR_CS2 | + MCF_GPIO_PAR_CS_PAR_CS1; + + /* Pin assignments for port SDRAM + Pin /SD_WE : SDRAM controller /SD_WE + Pin /SD_SCAS : SDRAM controller /SD_SCAS + Pin /SD_SRAS : SDRAM controller /SD_SRAS + Pin /SD_SCKE : SDRAM controller /SD_SCKE + Pin /SD_CS1 : SDRAM controller /SD_CS1 + Pin /SD_CS0 : SDRAM controller /SD_CS0 + */ + MCF_GPIO_PDDR_SDRAM = 0; + MCF_GPIO_PAR_SDRAM = + MCF_GPIO_PAR_SDRAM_PAR_SDWE | MCF_GPIO_PAR_SDRAM_PAR_SCAS | + MCF_GPIO_PAR_SDRAM_PAR_SRAS | MCF_GPIO_PAR_SDRAM_PAR_SCKE | + MCF_GPIO_PAR_SDRAM_PAR_SDCS1 | MCF_GPIO_PAR_SDRAM_PAR_SDCS0; + + /* Pin assignments for port FECI2C + Pins are all GPIO inputs + */ + MCF_GPIO_PDDR_FECI2C = 0; + MCF_GPIO_PAR_FECI2C = + MCF_GPIO_PAR_FECI2C_PAR_EMDC_FEC | MCF_GPIO_PAR_FECI2C_PAR_EMDIO_FEC; + + /* Pin assignments for port UARTL + Pins are all GPIO inputs + */ + MCF_GPIO_PDDR_UARTL = 0; + MCF_GPIO_PAR_UART = 0; + + /* Pin assignments for port UARTH + Pin U2TXD : GPIO input + Pin U2RXD : GPIO input + Pin /IRQ2 : Interrupt request /IRQ2 or GPIO + */ + MCF_GPIO_PDDR_UARTH = 0; + + /* Pin assignments for port QSPI + Pins are all GPIO inputs + */ + MCF_GPIO_PDDR_QSPI = 0; + MCF_GPIO_PAR_QSPI = 0; + + /* Pin assignments for port TIMER + Pins are all GPIO inputs + */ + MCF_GPIO_PDDR_TIMER = 0; + MCF_GPIO_PAR_TIMER = 0; + + /* Pin assignments for port ETPU + Pins are all GPIO inputs + */ + MCF_GPIO_PDDR_ETPU = 0; + MCF_GPIO_PAR_ETPU = 0; +} diff --git a/20080212/Demo/MCF5235_GCC/system/mcf5xxx.S b/20080212/Demo/MCF5235_GCC/system/mcf5xxx.S new file mode 100644 index 000000000..b68c689c4 --- /dev/null +++ b/20080212/Demo/MCF5235_GCC/system/mcf5xxx.S @@ -0,0 +1,249 @@ +/* + * Lowest level routines for all ColdFire processors. Based on the + * MCF523x examples from Freescale. + * + * Freescale explicitly grants the redistribution and modification + * of these source files. The complete licensing information is + * available in the file LICENSE_FREESCALE.TXT. + * + * Modifications Copyright (c) 2006 Christian Walter + * + * File: $Id: mcf5xxx.S,v 1.2 2006/09/24 22:50:22 wolti Exp $ + */ + + .global asm_set_ipl + .global _asm_set_ipl + .global mcf5xxx_wr_cacr + .global _mcf5xxx_wr_cacr + .global mcf5xxx_wr_acr0 + .global _mcf5xxx_wr_acr0 + .global mcf5xxx_wr_acr1 + .global _mcf5xxx_wr_acr1 + .global mcf5xxx_wr_acr2 + .global _mcf5xxx_wr_acr2 + .global mcf5xxx_wr_acr3 + .global _mcf5xxx_wr_acr3 + .global mcf5xxx_wr_other_sp + .global _mcf5xxx_wr_other_sp + .global mcf5xxx_wr_other_a7 + .global _mcf5xxx_wr_other_a7 + .global mcf5xxx_wr_vbr + .global _mcf5xxx_wr_vbr + .global mcf5xxx_wr_macsr + .global _mcf5xxx_wr_macsr + .global mcf5xxx_wr_mask + .global _mcf5xxx_wr_mask + .global mcf5xxx_wr_acc0 + .global _mcf5xxx_wr_acc0 + .global mcf5xxx_wr_accext01 + .global _mcf5xxx_wr_accext01 + .global mcf5xxx_wr_accext23 + .global _mcf5xxx_wr_accext23 + .global mcf5xxx_wr_acc1 + .global _mcf5xxx_wr_acc1 + .global mcf5xxx_wr_acc2 + .global _mcf5xxx_wr_acc2 + .global mcf5xxx_wr_acc3 + .global _mcf5xxx_wr_acc3 + .global mcf5xxx_wr_sr + .global _mcf5xxx_wr_sr + .global mcf5xxx_wr_rambar0 + .global _mcf5xxx_wr_rambar0 + .global mcf5xxx_wr_rambar1 + .global _mcf5xxx_wr_rambar1 + .global mcf5xxx_wr_mbar + .global _mcf5xxx_wr_mbar + .global mcf5xxx_wr_mbar0 + .global _mcf5xxx_wr_mbar0 + .global mcf5xxx_wr_mbar1 + .global _mcf5xxx_wr_mbar1 + + .text + +/********************************************************************/ +/* + * This routines changes the IPL to the value passed into the routine. + * It also returns the old IPL value back. + * Calling convention from C: + * old_ipl = asm_set_ipl(new_ipl); + * For the Diab Data C compiler, it passes return value thru D0. + * Note that only the least significant three bits of the passed + * value are used. + */ + +asm_set_ipl: +_asm_set_ipl: + link a6,#-8 + movem.l d6-d7,(sp) + + move.w sr,d7 /* current sr */ + + move.l d7,d0 /* prepare return value */ + andi.l #0x0700,d0 /* mask out IPL */ + lsr.l #8,d0 /* IPL */ + + move.l 8(a6),d6 /* get argument */ + andi.l #0x07,d6 /* least significant three bits */ + lsl.l #8,d6 /* move over to make mask */ + + andi.l #0x0000F8FF,d7 /* zero out current IPL */ + or.l d6,d7 /* place new IPL in sr */ + move.w d7,sr + + movem.l (sp),d6-d7 + lea 8(sp),sp + unlk a6 + rts + +/********************************************************************/ +/* + * These routines write to the special purpose registers in the ColdFire + * core. Since these registers are write-only in the supervisor model, + * no corresponding read routines exist. + */ + +mcf5xxx_wr_cacr: +_mcf5xxx_wr_cacr: + move.l 4(sp),d0 + .long 0x4e7b0002 /* movec d0,cacr */ + nop + rts + +mcf5xxx_wr_acr0: +_mcf5xxx_wr_acr0: + move.l 4(sp),d0 + .long 0x4e7b0004 /* movec d0,ACR0 */ + nop + rts + +mcf5xxx_wr_acr1: +_mcf5xxx_wr_acr1: + move.l 4(sp),d0 + .long 0x4e7b0005 /* movec d0,ACR1 */ + nop + rts + +mcf5xxx_wr_acr2: +_mcf5xxx_wr_acr2: + move.l 4(sp),d0 + .long 0x4e7b0006 /* movec d0,ACR2 */ + nop + rts + +mcf5xxx_wr_acr3: +_mcf5xxx_wr_acr3: + move.l 4(sp),d0 + .long 0x4e7b0007 /* movec d0,ACR3 */ + nop + rts + +mcf5xxx_wr_other_sp: +_mcf5xxx_wr_other_sp: +mcf5xxx_wr_other_a7: +_mcf5xxx_wr_other_a7: + move.l 4(sp),d0 + .long 0x4e7b0800 /* movec d0,OTHER_A7 */ + nop + rts + +mcf5xxx_wr_vbr: +_mcf5xxx_wr_vbr: + move.l 4(sp),d0 + .long 0x4e7b0801 /* movec d0,VBR */ + nop + rts + +mcf5xxx_wr_macsr: +_mcf5xxx_wr_macsr: + move.l 4(sp),d0 + .long 0x4e7b0804 /* movec d0,MACSR */ + nop + rts + +mcf5xxx_wr_mask: +_mcf5xxx_wr_mask: + move.l 4(sp),d0 + .long 0x4e7b0805 /* movec d0,MASK */ + nop + rts + +mcf5xxx_wr_acc0: +_mcf5xxx_wr_acc0: + move.l 4(sp),d0 + .long 0x4e7b0806 /* movec d0,ACC0 */ + nop + rts + +mcf5xxx_wr_accext01: +_mcf5xxx_wr_accext01: + move.l 4(sp),d0 + .long 0x4e7b0807 /* movec d0,ACCEXT01 */ + nop + rts + +mcf5xxx_wr_accext23: +_mcf5xxx_wr_accext23: + move.l 4(sp),d0 + .long 0x4e7b0808 /* movec d0,ACCEXT23 */ + nop + rts + +mcf5xxx_wr_acc1: +_mcf5xxx_wr_acc1: + move.l 4(sp),d0 + .long 0x4e7b0809 /* movec d0,ACC1 */ + nop + rts + +mcf5xxx_wr_acc2: +_mcf5xxx_wr_acc2: + move.l 4(sp),d0 + .long 0x4e7b080A /* movec d0,ACC2 */ + nop + rts + +mcf5xxx_wr_acc3: +_mcf5xxx_wr_acc3: + move.l 4(sp),d0 + .long 0x4e7b080B /* movec d0,ACC3 */ + nop + rts + +mcf5xxx_wr_sr: +_mcf5xxx_wr_sr: + move.l 4(sp),d0 + move.w d0,SR + rts + +mcf5xxx_wr_rambar0: +_mcf5xxx_wr_rambar0: + move.l 4(sp),d0 + .long 0x4e7b0C04 /* movec d0,RAMBAR0 */ + nop + rts + +mcf5xxx_wr_rambar1: +_mcf5xxx_wr_rambar1: + move.l 4(sp),d0 + .long 0x4e7b0C05 /* movec d0,RAMBAR1 */ + nop + rts + +mcf5xxx_wr_mbar: +_mcf5xxx_wr_mbar: +mcf5xxx_wr_mbar0: +_mcf5xxx_wr_mbar0: + move.l 4(sp),d0 + .long 0x4e7b0C0F /* movec d0,MBAR0 */ + nop + rts + +mcf5xxx_wr_mbar1: +_mcf5xxx_wr_mbar1: + move.l 4(sp),d0 + .long 0x4e7b0C0E /* movec d0,MBAR1 */ + nop + rts + + .end +/********************************************************************/ diff --git a/20080212/Demo/MCF5235_GCC/system/newlib.c b/20080212/Demo/MCF5235_GCC/system/newlib.c new file mode 100644 index 000000000..665e1eda2 --- /dev/null +++ b/20080212/Demo/MCF5235_GCC/system/newlib.c @@ -0,0 +1,156 @@ +/* + FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* ------------------------ System includes ------------------------------- */ +#include +#include +#include +#include + +/* ------------------------ FreeRTOS includes ----------------------------- */ +#include +#include + +/* ------------------------ Prototypes ------------------------------------ */ +void vSerialPutStringNOISR( xComPortHandle pxPort, + const signed portCHAR * const pcString, + unsigned portSHORT usStringLength ); + +/* ------------------------ Start implementation -------------------------- */ +void +_exit( int status ) +{ + asm volatile ( "halt" ); + + for( ;; ); +} + +pid_t +getpid( void ) +{ + return 0; +} + +int +kill( pid_t pid, int sig ) +{ + _exit( 0 ); +} + +int +close( int fd ) +{ + return 0; +} + +int +fstat( int fd, struct stat *buf ) +{ + buf->st_mode = S_IFCHR; + buf->st_blksize = 0; + return 0; +} + +ssize_t +write( int fd, const void *buf, size_t nbytes ) +{ + ssize_t res = nbytes; + extern xComPortHandle xSTDComPort; + switch ( fd ) + { + case STDERR_FILENO: + vSerialPutStringNOISR( xSTDComPort, + ( const signed portCHAR * const )buf, + ( unsigned portSHORT )nbytes ); + break; + case STDOUT_FILENO: + vSerialPutString( xSTDComPort, + ( const signed portCHAR * const)buf, + ( unsigned portSHORT )nbytes ); + break; + default: + errno = EIO; + res = -1; + break; + } + return res; +} + +int +read( int fd, void *buf, size_t nbytes ) +{ + switch ( fd ) + { + default: + errno = EIO; + return -1; + } +} + +int +isatty( int fd ) +{ + return 0; +} + +off_t +lseek( int fd, off_t offset, int whence ) +{ + errno = EIO; + return ( off_t ) - 1; +} + +extern char _end[]; +char *heap_ptr; + +void * +sbrk( ptrdiff_t nbytes ) +{ + char *base; + + if( !heap_ptr ) + heap_ptr = ( char * )&_end; + base = heap_ptr; + heap_ptr += nbytes; + + return base; +} diff --git a/20080212/Demo/MCF5235_GCC/system/serial.c b/20080212/Demo/MCF5235_GCC/system/serial.c new file mode 100644 index 000000000..24fafdf5a --- /dev/null +++ b/20080212/Demo/MCF5235_GCC/system/serial.c @@ -0,0 +1,308 @@ +/* + FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* ------------------------ MCF523x includes ------------------------------ */ +#include "mcf5xxx.h" +#include "mcf523x.h" + +/* ------------------------ FreeRTOS includes ----------------------------- */ +#include "FreeRTOS.h" +#include "queue.h" +#include "task.h" + +#include "serial.h" + +/* ----------------------- Defines ----------------------------------------- */ +#define BAUDRATE_VALUE(fsys, baud) ( ( fsys )/(32UL * baud) ) +#define MCF_UART_VECTOR ( 64 + 13 ) +#define COM_NIFACE 1 +#define COM_BLOCK_RETRYTIME 10 + +/* ------------------------ Static functions ------------------------------ */ +static void prvSerialISR( void ); + +/* ------------------------ Static variables ------------------------------ */ +typedef struct +{ + portBASE_TYPE xInitialized; + xQueueHandle xRXChars; + xQueueHandle xTXChars; +} xComPortIF_t; + +static xComPortIF_t xComPortIF[ COM_NIFACE ]; + +/* ------------------------ Begin implementation -------------------------- */ +xComPortHandle +xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, + unsigned portBASE_TYPE uxQueueLength ) +{ + extern void ( *__RAMVEC[] ) ( ); + xComPortHandle xReturn; + portBASE_TYPE xOldIPL; + + /* Create the queues used to hold Rx and Tx characters. */ + xComPortIF[ 0 ].xRXChars = + xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE )sizeof( signed portCHAR ) ); + xComPortIF[ 0 ].xTXChars = + xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE )sizeof( signed portCHAR ) ); + + /* If the queues were created correctly then setup the serial port hardware. */ + if( ( xComPortIF[ 0 ].xRXChars != 0 ) && ( xComPortIF[ 0 ].xTXChars != 0 ) ) + { + xOldIPL = portSET_IPL( portIPL_MAX ); + + /* UART 0: Reset transmitter, receiver and mode register pointer */ + MCF_UART_UCR0 = MCF_UART_UCR_MISC( 0x3 ); + MCF_UART_UCR0 = MCF_UART_UCR_MISC( 0x2 ); + MCF_UART_UCR0 = MCF_UART_UCR_MISC( 0x1 ); + + /* Enable receive interrupts. */ + MCF_UART_UIMR0 = MCF_UART_UIMR_RXRDY_FU; + + /* 8 Databits, 1 Stopbit and no parity */ + MCF_UART_UMR0 = MCF_UART_UMR_PM( 0x3 ) | MCF_UART_UMR_SB( 0x7 ) | MCF_UART_UMR_BC( 0x3 ); + + /* UART 0 Clocking */ + MCF_UART_UCSR0 = MCF_UART_UCSR_RCS( 0xd ) | MCF_UART_UCSR_TCS( 0xd ); + MCF_UART_UBG10 = BAUDRATE_VALUE( FSYS_2, ulWantedBaud ) >> 8U; + MCF_UART_UBG20 = BAUDRATE_VALUE( FSYS_2, ulWantedBaud ) & 0xFFU; + + /* UART 0: Enable interrupts */ + __RAMVEC[MCF_UART_VECTOR] = prvSerialISR; + MCF_INTC0_ICR13 = MCF_INTC0_ICRn_IL( 0x2 ) | MCF_INTC0_ICRn_IP( 0x1 ); + MCF_INTC0_IMRL &= ~MCF_INTC0_IMRL_INT_MASK13; + + /* UART 0 Miscellaneous */ + MCF_UART_UACR0 = 0; + + /* UART 0: Enable pins */ + MCF_GPIO_PAR_UART = MCF_GPIO_PAR_UART_PAR_U0RXD | MCF_GPIO_PAR_UART_PAR_U0TXD; + + /* Enable the UART. */ + MCF_UART_UCR0 = MCF_UART_UCR_RXC( 0x1 ) | MCF_UART_UCR_TXC( 0x1 ); + + xComPortIF[ 0 ].xInitialized = TRUE; + xReturn = ( xComPortHandle ) &xComPortIF[ 0 ]; + + ( void )portSET_IPL( xOldIPL ); + } + else + { + xReturn = ( xComPortHandle ) 0; + } + + return xReturn; +} + +signed portBASE_TYPE +xSerialGetChar( xComPortHandle pxPort, signed portCHAR * pcRxedChar, + portTickType xBlockTime ) +{ + int i; + portBASE_TYPE xResult = pdFALSE; + /* Lookup the correct interface. */ + for( i = 0; i < COM_NIFACE; i++ ) + { + if( pxPort == ( xComPortHandle ) &xComPortIF[ i ] ) + { + break; + } + } + /* This COM port is available. */ + if( ( i != COM_NIFACE ) && xComPortIF[ i ].xInitialized ) + { + /* Get the next character from the buffer. Return false if no characters + * are available, or arrive before xBlockTime expires. + */ + if( xQueueReceive( xComPortIF[ i ].xRXChars, pcRxedChar, xBlockTime ) ) + { + xResult = pdTRUE; + } + } + return xResult; +} + +void +vSerialPutString( xComPortHandle pxPort, const signed portCHAR * + const pcString, unsigned portSHORT usStringLength ) +{ + int i; + signed portCHAR *pChNext; + + /* Send each character in the string, one at a time. */ + pChNext = ( signed portCHAR * )pcString; + for( i = 0; i < usStringLength; i++ ) + { + /* Block until character has been transmitted. */ + while( xSerialPutChar( pxPort, *pChNext, COM_BLOCK_RETRYTIME ) != pdTRUE ); pChNext++; + } +} + +signed portBASE_TYPE +xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, + portTickType xBlockTime ) +{ + int i; + portBASE_TYPE xResult = pdFALSE; + portBASE_TYPE xOldIPL; + /* Lookup the correct interface. */ + for( i = 0; i < COM_NIFACE; i++ ) + { + if( pxPort == ( xComPortHandle ) &xComPortIF[ i ] ) + { + break; + } + } + /* This COM port is available. */ + if( ( i != COM_NIFACE ) && xComPortIF[ i ].xInitialized ) + { + /* Place the character in the queue of characters to be transmitted. */ + if( xQueueSend( xComPortIF[ i ].xTXChars, &cOutChar, xBlockTime ) == pdPASS ) + { + /* Turn on the Tx interrupt so the ISR will remove the character from the + * queue and send it. */ + MCF_UART_UIMR0 = MCF_UART_UIMR_TXRDY | MCF_UART_UIMR_RXRDY_FU; + xResult = pdTRUE; + } + } + return xResult; +} + +signed portBASE_TYPE +xSerialPutCharNOISR( xComPortHandle pxPort, signed portCHAR cOutChar ) +{ + int i; + portBASE_TYPE xResult = pdFALSE; + portBASE_TYPE xOldIPL = portSET_IPL( portIPL_MAX ); + /* Lookup the correct interface. */ + for( i = 0; i < COM_NIFACE; i++ ) + { + if( pxPort == ( xComPortHandle ) &xComPortIF[ i ] ) + { + break; + } + } + /* This COM port is available. Support for this only available for COM1 right now. */ + if( ( i != COM_NIFACE ) && ( i == 0 ) ) + { + /* Wait until the transmit buffer is ready. */ + while( !( MCF_UART_USR0 & MCF_UART_USR_TXRDY ) ); + /* Place the character in the transmit buffer. */ + MCF_UART_UTB0 = cOutChar; + xResult = pdTRUE; + } + ( void )portSET_IPL( xOldIPL ); + return xResult; +} + +void +vSerialPutStringNOISR( xComPortHandle pxPort, const signed portCHAR * + const pcString, unsigned portSHORT usStringLength ) +{ + int i; + signed portCHAR *pChNext; + portBASE_TYPE xOldIPL = portSET_IPL( portIPL_MAX ); + + /* Send each character in the string, one at a time. */ + pChNext = ( signed portCHAR * )pcString; + for( i = 0; i < usStringLength; i++ ) + { + /* Block until character has been transmitted. */ + while( xSerialPutCharNOISR( pxPort, *pChNext ) != pdTRUE ); + pChNext++; + } + ( void )portSET_IPL( xOldIPL ); +} + +void +vSerialClose( xComPortHandle xPort ) +{ + /* Not supported as not required by the demo application. */ +} + +void +prvSerialISR( void ) +{ + static signed portCHAR cChar; + static portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByRx = pdFALSE; + + /* We have to remvoe the effect of the GCC. Please note that the + * __attribute__ ((interrupt_handler)) does not work here because we + * have to do the storing of the registers ourself. Another problem + * is the usage of a frame pointer which is unlinked on entry. + */ +#if _GCC_USES_FP == 1 + asm volatile ( "unlk %fp\n\t" ); +#endif + /* This ISR can cause a context switch, so the first statement must be + * a call to the portENTER_SWITCHING_ISR() macro. This must be BEFORE any + * variable declarations. + */ + portENTER_SWITCHING_ISR(); + + /* Ready to send a character from the buffer. */ + if( MCF_UART_USR0 & MCF_UART_USR_TXRDY ) + { + /* Transmit buffer is ready. Test if there are characters available. */ + if( xQueueReceiveFromISR( xComPortIF[ 0 ].xTXChars, &cChar, &xTaskWokenByTx ) == + pdTRUE ) + { + /* A character was retrieved from the queue so can be sent. */ + MCF_UART_UTB0 = cChar; + } + else + { + /* Leave only receiver enabled. */ + MCF_UART_UIMR0 = MCF_UART_UIMR_RXRDY_FU; + } + } + if( MCF_UART_USR0 & MCF_UART_USR_RXRDY ) + { + cChar = MCF_UART_URB0; + xTaskWokenByRx = + xQueueSendFromISR( xComPortIF[ 0].xRXChars, &cChar, xTaskWokenByRx ); + } + /* Exit the ISR. If a task was woken by either a character being + * or transmitted then a context switch will occur. + */ + portEXIT_SWITCHING_ISR( ( xTaskWokenByTx || xTaskWokenByRx ) ); +} diff --git a/20080212/Demo/MCF5235_GCC/system/vector.S b/20080212/Demo/MCF5235_GCC/system/vector.S new file mode 100644 index 000000000..debbac3c0 --- /dev/null +++ b/20080212/Demo/MCF5235_GCC/system/vector.S @@ -0,0 +1,312 @@ +/* + FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + .extern __stack + .extern start + .extern fec_handler + .extern fec_if + .extern decrement_timers + .global __RAMVEC + .global __ROMVEC + + .equ MCF_PIT_PCSR0, IPSBAR + 0x150000 + .equ MCF_PIT_PCSR_PIF, 0x0004 + + .section .vector_rom, "x" +__ROMVEC: + .long __stack /* Reset: Initial Stack Pointer */ + .long start /* Reset: Initial Program Counter */ + .long VecDefault /* Bus Error */ + .long VecDefault /* Address Error */ + .long VecDefault /* Illegal Instruction */ + .long VecDefault /* Zero Divison */ + .space 4 /* reserved */ + .space 4 /* reserved */ + .long VecDefault /* Privilege Violation */ + .long VecDefault /* Trace */ + .long VecDefault /* Unimplemented line-a opcode */ + .long VecDefault /* Unimplemented line-b opcode */ + .long VecDefault /* Non-PC breakpoint debug interrupt */ + .long VecDefault /* PC breakpoint debug interrupt */ + .long VecDefault /* Format Error */ + .long VecDefault /* Uninitialized Interrupt */ + .org 0x60 + .long IRQSpurious /* Spurious Interrupt */ + .long IRQDefault /* Level 1 Interrupt */ + .long IRQDefault /* Level 2 Interrupt */ + .long IRQDefault /* Level 3 Interrupt */ + .long IRQDefault /* Level 4 Interrupt */ + .long IRQDefault /* Level 5 Interrupt */ + .long IRQDefault /* Level 6 Interrupt */ + .long IRQDefault /* Level 7 Interrupt */ + .org 0x80 + .long TrapDefault /* TRAP 0 */ + .long TrapDefault /* TRAP 1 */ + .long TrapDefault /* TRAP 2 */ + .long TrapDefault /* TRAP 3 */ + .long TrapDefault /* TRAP 4 */ + .long TrapDefault /* TRAP 5 */ + .long TrapDefault /* TRAP 6 */ + .long TrapDefault /* TRAP 7 */ + .long TrapDefault /* TRAP 8 */ + .long TrapDefault /* TRAP 9 */ + .long TrapDefault /* TRAP 10 */ + .long TrapDefault /* TRAP 11 */ + .long TrapDefault /* TRAP 12 */ + .long TrapDefault /* TRAP 13 */ + .long TrapDefault /* TRAP 14 */ + .long TrapDefault /* TRAP 15 */ + .org 0x100 + .long IRQDefault /* User-Defined Interrupt 0 */ + .long IRQDefault /* User-Defined Interrupt 1 */ + .long IRQDefault /* User-Defined Interrupt 2 */ + .long IRQDefault /* User-Defined Interrupt 3 */ + .long IRQDefault /* User-Defined Interrupt 4 */ + .long IRQDefault /* User-Defined Interrupt 5 */ + .long IRQDefault /* User-Defined Interrupt 6 */ + .long IRQDefault /* User-Defined Interrupt 7 */ + .long IRQDefault /* User-Defined Interrupt 8 */ + .long IRQDefault /* User-Defined Interrupt 9 */ + .long IRQDefault /* User-Defined Interrupt 10 */ + .long IRQDefault /* User-Defined Interrupt 11 */ + .long IRQDefault /* User-Defined Interrupt 12 */ + .long IRQDefault /* User-Defined Interrupt 13 */ + .long IRQDefault /* User-Defined Interrupt 14 */ + .long IRQDefault /* User-Defined Interrupt 15 */ + .long IRQDefault /* User-Defined Interrupt 16 */ + .long IRQDefault /* User-Defined Interrupt 17 */ + .long IRQDefault /* User-Defined Interrupt 18 */ + .long IRQDefault /* User-Defined Interrupt 19 */ + .long IRQDefault /* User-Defined Interrupt 20 */ + .long IRQDefault /* User-Defined Interrupt 21 */ + .long IRQDefault /* User-Defined Interrupt 22 */ + .long IRQDefault /* Transmit frame interrupt */ + .long IRQDefault /* Transmit buffer interrupt */ + .long IRQDefault /* Transmit FIFO underrun */ + .long IRQDefault /* Collision retry limit */ + .long IRQDefault /* Receive frame interrupt */ + .long IRQDefault /* Receive buffer interrupt */ + .long IRQDefault /* MII interrupt */ + .long IRQDefault /* Late collision */ + .long IRQDefault /* Heartbeat error */ + .long IRQDefault /* Graceful stop complete */ + .long IRQDefault /* Ethernet bus error */ + .long IRQDefault /* Babbling transmit error */ + .long IRQDefault /* Babbling receive error */ + .long IRQDefault /* Timer interrupt */ + .long IRQDefault /* User-Defined Interrupt 37 */ + .long IRQDefault /* User-Defined Interrupt 38 */ + .long IRQDefault /* User-Defined Interrupt 39 */ + .long IRQDefault /* User-Defined Interrupt 40 */ + .long IRQDefault /* User-Defined Interrupt 41 */ + .long IRQDefault /* User-Defined Interrupt 42 */ + .long IRQDefault /* User-Defined Interrupt 43 */ + .long IRQDefault /* User-Defined Interrupt 44 */ + .long IRQDefault /* User-Defined Interrupt 45 */ + .long IRQDefault /* User-Defined Interrupt 46 */ + .long IRQDefault /* User-Defined Interrupt 47 */ + .long IRQDefault /* User-Defined Interrupt 48 */ + .long IRQDefault /* User-Defined Interrupt 49 */ + .long IRQDefault /* User-Defined Interrupt 50 */ + .long IRQDefault /* User-Defined Interrupt 51 */ + .long IRQDefault /* User-Defined Interrupt 52 */ + .long IRQDefault /* User-Defined Interrupt 53 */ + .long IRQDefault /* User-Defined Interrupt 54 */ + .long IRQDefault /* User-Defined Interrupt 55 */ + .long IRQDefault /* User-Defined Interrupt 56 */ + .long IRQDefault /* User-Defined Interrupt 57 */ + .long IRQDefault /* User-Defined Interrupt 58 */ + .long IRQDefault /* User-Defined Interrupt 59 */ + .long IRQDefault /* User-Defined Interrupt 60 */ + .long IRQDefault /* User-Defined Interrupt 61 */ + .long IRQDefault /* User-Defined Interrupt 62 */ + .long IRQDefault /* User-Defined Interrupt 63 */ + .long IRQDefault /* User-Defined Interrupt 64 */ + .long IRQDefault /* User-Defined Interrupt 65 */ + .long IRQDefault /* User-Defined Interrupt 66 */ + .long IRQDefault /* User-Defined Interrupt 67 */ + .long IRQDefault /* User-Defined Interrupt 68 */ + .long IRQDefault /* User-Defined Interrupt 69 */ + .long IRQDefault /* User-Defined Interrupt 70 */ + .long IRQDefault /* User-Defined Interrupt 71 */ + .long IRQDefault /* User-Defined Interrupt 72 */ + .long IRQDefault /* User-Defined Interrupt 73 */ + .long IRQDefault /* User-Defined Interrupt 74 */ + .long IRQDefault /* User-Defined Interrupt 75 */ + .long IRQDefault /* User-Defined Interrupt 76 */ + .long IRQDefault /* User-Defined Interrupt 77 */ + .long IRQDefault /* User-Defined Interrupt 78 */ + .long IRQDefault /* User-Defined Interrupt 79 */ + .long IRQDefault /* User-Defined Interrupt 80 */ + .long IRQDefault /* User-Defined Interrupt 81 */ + .long IRQDefault /* User-Defined Interrupt 82 */ + .long IRQDefault /* User-Defined Interrupt 83 */ + .long IRQDefault /* User-Defined Interrupt 84 */ + .long IRQDefault /* User-Defined Interrupt 85 */ + .long IRQDefault /* User-Defined Interrupt 86 */ + .long IRQDefault /* User-Defined Interrupt 87 */ + .long IRQDefault /* User-Defined Interrupt 88 */ + .long IRQDefault /* User-Defined Interrupt 89 */ + .long IRQDefault /* User-Defined Interrupt 90 */ + .long IRQDefault /* User-Defined Interrupt 91 */ + .long IRQDefault /* User-Defined Interrupt 92 */ + .long IRQDefault /* User-Defined Interrupt 93 */ + .long IRQDefault /* User-Defined Interrupt 94 */ + .long IRQDefault /* User-Defined Interrupt 95 */ + .long IRQDefault /* User-Defined Interrupt 96 */ + .long IRQDefault /* User-Defined Interrupt 97 */ + .long IRQDefault /* User-Defined Interrupt 98 */ + .long IRQDefault /* User-Defined Interrupt 99 */ + .long IRQDefault /* User-Defined Interrupt 100 */ + .long IRQDefault /* User-Defined Interrupt 101 */ + .long IRQDefault /* User-Defined Interrupt 102 */ + .long IRQDefault /* User-Defined Interrupt 103 */ + .long IRQDefault /* User-Defined Interrupt 104 */ + .long IRQDefault /* User-Defined Interrupt 105 */ + .long IRQDefault /* User-Defined Interrupt 106 */ + .long IRQDefault /* User-Defined Interrupt 107 */ + .long IRQDefault /* User-Defined Interrupt 108 */ + .long IRQDefault /* User-Defined Interrupt 109 */ + .long IRQDefault /* User-Defined Interrupt 110 */ + .long IRQDefault /* User-Defined Interrupt 111 */ + .long IRQDefault /* User-Defined Interrupt 112 */ + .long IRQDefault /* User-Defined Interrupt 113 */ + .long IRQDefault /* User-Defined Interrupt 114 */ + .long IRQDefault /* User-Defined Interrupt 115 */ + .long IRQDefault /* User-Defined Interrupt 116 */ + .long IRQDefault /* User-Defined Interrupt 117 */ + .long IRQDefault /* User-Defined Interrupt 118 */ + .long IRQDefault /* User-Defined Interrupt 119 */ + .long IRQDefault /* User-Defined Interrupt 120 */ + .long IRQDefault /* User-Defined Interrupt 121 */ + .long IRQDefault /* User-Defined Interrupt 122 */ + .long IRQDefault /* User-Defined Interrupt 123 */ + .long IRQDefault /* User-Defined Interrupt 124 */ + .long IRQDefault /* User-Defined Interrupt 125 */ + .long IRQDefault /* User-Defined Interrupt 126 */ + .long IRQDefault /* User-Defined Interrupt 127 */ + .long IRQDefault /* User-Defined Interrupt 128 */ + .long IRQDefault /* User-Defined Interrupt 129 */ + .long IRQDefault /* User-Defined Interrupt 130 */ + .long IRQDefault /* User-Defined Interrupt 131 */ + .long IRQDefault /* User-Defined Interrupt 132 */ + .long IRQDefault /* User-Defined Interrupt 133 */ + .long IRQDefault /* User-Defined Interrupt 134 */ + .long IRQDefault /* User-Defined Interrupt 135 */ + .long IRQDefault /* User-Defined Interrupt 136 */ + .long IRQDefault /* User-Defined Interrupt 137 */ + .long IRQDefault /* User-Defined Interrupt 138 */ + .long IRQDefault /* User-Defined Interrupt 139 */ + .long IRQDefault /* User-Defined Interrupt 140 */ + .long IRQDefault /* User-Defined Interrupt 141 */ + .long IRQDefault /* User-Defined Interrupt 142 */ + .long IRQDefault /* User-Defined Interrupt 143 */ + .long IRQDefault /* User-Defined Interrupt 144 */ + .long IRQDefault /* User-Defined Interrupt 145 */ + .long IRQDefault /* User-Defined Interrupt 146 */ + .long IRQDefault /* User-Defined Interrupt 147 */ + .long IRQDefault /* User-Defined Interrupt 148 */ + .long IRQDefault /* User-Defined Interrupt 149 */ + .long IRQDefault /* User-Defined Interrupt 150 */ + .long IRQDefault /* User-Defined Interrupt 151 */ + .long IRQDefault /* User-Defined Interrupt 152 */ + .long IRQDefault /* User-Defined Interrupt 153 */ + .long IRQDefault /* User-Defined Interrupt 154 */ + .long IRQDefault /* User-Defined Interrupt 155 */ + .long IRQDefault /* User-Defined Interrupt 156 */ + .long IRQDefault /* User-Defined Interrupt 157 */ + .long IRQDefault /* User-Defined Interrupt 158 */ + .long IRQDefault /* User-Defined Interrupt 159 */ + .long IRQDefault /* User-Defined Interrupt 160 */ + .long IRQDefault /* User-Defined Interrupt 161 */ + .long IRQDefault /* User-Defined Interrupt 162 */ + .long IRQDefault /* User-Defined Interrupt 163 */ + .long IRQDefault /* User-Defined Interrupt 164 */ + .long IRQDefault /* User-Defined Interrupt 165 */ + .long IRQDefault /* User-Defined Interrupt 166 */ + .long IRQDefault /* User-Defined Interrupt 167 */ + .long IRQDefault /* User-Defined Interrupt 168 */ + .long IRQDefault /* User-Defined Interrupt 169 */ + .long IRQDefault /* User-Defined Interrupt 170 */ + .long IRQDefault /* User-Defined Interrupt 171 */ + .long IRQDefault /* User-Defined Interrupt 172 */ + .long IRQDefault /* User-Defined Interrupt 173 */ + .long IRQDefault /* User-Defined Interrupt 174 */ + .long IRQDefault /* User-Defined Interrupt 175 */ + .long IRQDefault /* User-Defined Interrupt 176 */ + .long IRQDefault /* User-Defined Interrupt 177 */ + .long IRQDefault /* User-Defined Interrupt 178 */ + .long IRQDefault /* User-Defined Interrupt 179 */ + .long IRQDefault /* User-Defined Interrupt 180 */ + .long IRQDefault /* User-Defined Interrupt 181 */ + .long IRQDefault /* User-Defined Interrupt 182 */ + .long IRQDefault /* User-Defined Interrupt 183 */ + .long IRQDefault /* User-Defined Interrupt 184 */ + .long IRQDefault /* User-Defined Interrupt 185 */ + .long IRQDefault /* User-Defined Interrupt 186 */ + .long IRQDefault /* User-Defined Interrupt 187 */ + .long IRQDefault /* User-Defined Interrupt 188 */ + .long IRQDefault /* User-Defined Interrupt 189 */ + .long IRQDefault /* User-Defined Interrupt 190 */ + .long IRQDefault /* User-Defined Interrupt 191 */ + .org 0x00000400 + + .section .vector_ram +__RAMVEC: + .space 0x400 + + .section .text +VecDefault: + halt + bra VecDefault + +IRQDefault: + halt + bra IRQDefault + +IRQSpurious: + halt + bra IRQSpurious + +TrapDefault: + halt + bra TrapDefault diff --git a/20080212/Demo/MicroBlaze/FreeRTOSConfig.h b/20080212/Demo/MicroBlaze/FreeRTOSConfig.h new file mode 100644 index 000000000..994a40155 --- /dev/null +++ b/20080212/Demo/MicroBlaze/FreeRTOSConfig.h @@ -0,0 +1,87 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include "xparameters.h" + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 100000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 120 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 18 * 1024 ) ) +#define configMAX_TASK_NAME_LEN ( 5 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/MicroBlaze/ParTest/ParTest.c b/20080212/Demo/MicroBlaze/ParTest/ParTest.c new file mode 100644 index 000000000..b8b8969bf --- /dev/null +++ b/20080212/Demo/MicroBlaze/ParTest/ParTest.c @@ -0,0 +1,162 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +/* Kernel includes. */ +#include "FreeRTOS.h" + +/* Demo application includes. */ +#include "partest.h" + +/* Library includes. */ +#include "xgpio_l.h" + +/* Misc hardware specific definitions. */ +#define partstALL_AS_OUTPUT 0x00 +#define partstCHANNEL_1 0x01 +#define partstMAX_4BIT_LED 0x03 + +/* The outputs are split into two IO sections, these variables maintain the +current value of either section. */ +static unsigned portBASE_TYPE uxCurrentOutput4Bit, uxCurrentOutput5Bit; + +/*-----------------------------------------------------------*/ +/* + * Setup the IO for the LED outputs. + */ +void vParTestInitialise( void ) +{ + /* Set both sets of LED's on the demo board to outputs. */ + XGpio_mSetDataDirection( XPAR_LEDS_4BIT_BASEADDR, partstCHANNEL_1, partstALL_AS_OUTPUT ); + XGpio_mSetDataDirection( XPAR_LEDS_POSITIONS_BASEADDR, partstCHANNEL_1, partstALL_AS_OUTPUT ); + + /* Start with all outputs off. */ + uxCurrentOutput4Bit = 0; + XGpio_mSetDataReg( XPAR_LEDS_4BIT_BASEADDR, partstCHANNEL_1, 0x00 ); + uxCurrentOutput5Bit = 0; + XGpio_mSetDataReg( XPAR_LEDS_POSITIONS_BASEADDR, partstCHANNEL_1, 0x00 ); +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ +unsigned portBASE_TYPE uxBaseAddress, *puxCurrentValue; + + portENTER_CRITICAL(); + { + /* Which IO section does the LED being set/cleared belong to? The + 4 bit or 5 bit outputs? */ + if( uxLED <= partstMAX_4BIT_LED ) + { + uxBaseAddress = XPAR_LEDS_4BIT_BASEADDR; + puxCurrentValue = &uxCurrentOutput4Bit; + } + else + { + uxBaseAddress = XPAR_LEDS_POSITIONS_BASEADDR; + puxCurrentValue = &uxCurrentOutput5Bit; + uxLED -= partstMAX_4BIT_LED; + } + + /* Setup the bit mask accordingly. */ + uxLED = 0x01 << uxLED; + + /* Maintain the current output value. */ + if( xValue ) + { + *puxCurrentValue |= uxLED; + } + else + { + *puxCurrentValue &= ~uxLED; + } + + /* Write the value to the port. */ + XGpio_mSetDataReg( uxBaseAddress, partstCHANNEL_1, *puxCurrentValue ); + } + portEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned portBASE_TYPE uxBaseAddress, *puxCurrentValue; + + portENTER_CRITICAL(); + { + /* Which IO section does the LED being toggled belong to? The + 4 bit or 5 bit outputs? */ + if( uxLED <= partstMAX_4BIT_LED ) + { + uxBaseAddress = XPAR_LEDS_4BIT_BASEADDR; + puxCurrentValue = &uxCurrentOutput4Bit; + } + else + { + uxBaseAddress = XPAR_LEDS_POSITIONS_BASEADDR; + puxCurrentValue = &uxCurrentOutput5Bit; + uxLED -= partstMAX_4BIT_LED; + } + + /* Setup the bit mask accordingly. */ + uxLED = 0x01 << uxLED; + + /* Maintain the current output value. */ + if( *puxCurrentValue & uxLED ) + { + *puxCurrentValue &= ~uxLED; + } + else + { + *puxCurrentValue |= uxLED; + } + + /* Write the value to the port. */ + XGpio_mSetDataReg(uxBaseAddress, partstCHANNEL_1, *puxCurrentValue ); + } + portEXIT_CRITICAL(); +} + + diff --git a/20080212/Demo/MicroBlaze/__xps/bitinit.opt b/20080212/Demo/MicroBlaze/__xps/bitinit.opt new file mode 100644 index 000000000..2496fab76 --- /dev/null +++ b/20080212/Demo/MicroBlaze/__xps/bitinit.opt @@ -0,0 +1 @@ + -pe microblaze_0 RTOSDemo/executable.elf diff --git a/20080212/Demo/MicroBlaze/__xps/libgen.opt b/20080212/Demo/MicroBlaze/__xps/libgen.opt new file mode 100644 index 000000000..77b154845 --- /dev/null +++ b/20080212/Demo/MicroBlaze/__xps/libgen.opt @@ -0,0 +1 @@ + -p virtex4 diff --git a/20080212/Demo/MicroBlaze/__xps/platgen.opt b/20080212/Demo/MicroBlaze/__xps/platgen.opt new file mode 100644 index 000000000..f56ee64ea --- /dev/null +++ b/20080212/Demo/MicroBlaze/__xps/platgen.opt @@ -0,0 +1 @@ + -p virtex4 -lang vhdl -st xst diff --git a/20080212/Demo/MicroBlaze/__xps/rtosdemo_compiler.opt b/20080212/Demo/MicroBlaze/__xps/rtosdemo_compiler.opt new file mode 100644 index 000000000..c108c4082 --- /dev/null +++ b/20080212/Demo/MicroBlaze/__xps/rtosdemo_compiler.opt @@ -0,0 +1,23 @@ +microblaze_0 +RTOSDEMO_SOURCES = main.c ParTest/ParTest.c ../../Source/tasks.c ../../Source/queue.c ../../Source/list.c ../../Source/portable/MemMang/heap_1.c ../../Source/portable/GCC/MicroBlaze/port.c ../../Source/portable/GCC/MicroBlaze/portasm.s ../Common/Minimal/flash.c serial/serial.c ../Common/Minimal/comtest.c ../Common/Minimal/integer.c ../Common/Minimal/semtest.c ../Common/Minimal/dynamic.c ../Common/Minimal/PollQ.c ../Common/Minimal/BlockQ.c +RTOSDEMO_HEADERS = FreeRTOSConfig.h +RTOSDEMO_CC = mb-gcc +RTOSDEMO_CC_SIZE = mb-size +RTOSDEMO_CC_OPT = -Os +RTOSDEMO_CFLAGS = -D MICROBLAZE_GCC -Wall +RTOSDEMO_CC_SEARCH = # -B +RTOSDEMO_LIBPATH = -L./microblaze_0/lib/ # -L +RTOSDEMO_INCLUDES = -I./microblaze_0/include/ -IDev/FreeRTOS/Demo/MicroBlaze/ -I. -I../Common/include -I../../Source/include -I../../Source/portable/GCC/MicroBlaze +RTOSDEMO_LFLAGS = # -l +RTOSDEMO_CC_PREPROC_FLAG = # -Wp, +RTOSDEMO_CC_ASM_FLAG = # -Wa, +RTOSDEMO_CC_LINKER_FLAG = -Wl,-Map=rtosdemo.map +RTOSDEMO_LINKER_SCRIPT = +RTOSDEMO_CC_DEBUG_FLAG = -g +RTOSDEMO_CC_GLOBPTR_FLAG= # -mxl-gp-opt +RTOSDEMO_MODE = executable +RTOSDEMO_LIBG_OPT = -$(RTOSDEMO_MODE) microblaze_0 +RTOSDEMO_CC_SOFTMUL_FLAG= -mno-xl-soft-mul +RTOSDEMO_CC_START_ADDR_FLAG= # -Wl,-defsym -Wl,_TEXT_START_ADDR= +RTOSDEMO_CC_STACK_SIZE_FLAG= # -Wl,-defsym -Wl,_STACK_SIZE= + $(RTOSDEMO_CC_SOFTMUL_FLAG) \ diff --git a/20080212/Demo/MicroBlaze/__xps/simgen.opt b/20080212/Demo/MicroBlaze/__xps/simgen.opt new file mode 100644 index 000000000..236453ae0 --- /dev/null +++ b/20080212/Demo/MicroBlaze/__xps/simgen.opt @@ -0,0 +1 @@ + -p virtex4 -lang vhdl -pe microblaze_0 RTOSDemo/executable.elf -s mti diff --git a/20080212/Demo/MicroBlaze/__xps/testapp_peripheral_compiler.opt b/20080212/Demo/MicroBlaze/__xps/testapp_peripheral_compiler.opt new file mode 100644 index 000000000..67e70306a --- /dev/null +++ b/20080212/Demo/MicroBlaze/__xps/testapp_peripheral_compiler.opt @@ -0,0 +1,23 @@ +microblaze_0 +TESTAPP_PERIPHERAL_SOURCES = TestApp_Peripheral/src/TestApp_Peripheral.c TestApp_Peripheral/src/xuartlite_selftest_example.c +TESTAPP_PERIPHERAL_HEADERS = +TESTAPP_PERIPHERAL_CC = mb-gcc +TESTAPP_PERIPHERAL_CC_SIZE = mb-size +TESTAPP_PERIPHERAL_CC_OPT = -O2 +TESTAPP_PERIPHERAL_CFLAGS = +TESTAPP_PERIPHERAL_CC_SEARCH = # -B +TESTAPP_PERIPHERAL_LIBPATH = -L./microblaze_0/lib/ # -L +TESTAPP_PERIPHERAL_INCLUDES = -I./microblaze_0/include/ # -I +TESTAPP_PERIPHERAL_LFLAGS = # -l +TESTAPP_PERIPHERAL_CC_PREPROC_FLAG = # -Wp, +TESTAPP_PERIPHERAL_CC_ASM_FLAG = # -Wa, +TESTAPP_PERIPHERAL_CC_LINKER_FLAG = # -Wl, +TESTAPP_PERIPHERAL_LINKER_SCRIPT = TestApp_Peripheral/src/TestApp_Peripheral_LinkScr +TESTAPP_PERIPHERAL_CC_DEBUG_FLAG = -g +TESTAPP_PERIPHERAL_CC_GLOBPTR_FLAG= # -mxl-gp-opt +TESTAPP_PERIPHERAL_MODE = executable +TESTAPP_PERIPHERAL_LIBG_OPT = -$(TESTAPP_PERIPHERAL_MODE) microblaze_0 +TESTAPP_PERIPHERAL_CC_SOFTMUL_FLAG= -mno-xl-soft-mul +TESTAPP_PERIPHERAL_CC_START_ADDR_FLAG= # -Wl,-defsym -Wl,_TEXT_START_ADDR= +TESTAPP_PERIPHERAL_CC_STACK_SIZE_FLAG= # -Wl,-defsym -Wl,_STACK_SIZE= + $(TESTAPP_PERIPHERAL_CC_SOFTMUL_FLAG) \ diff --git a/20080212/Demo/MicroBlaze/__xps/vpgen.opt b/20080212/Demo/MicroBlaze/__xps/vpgen.opt new file mode 100644 index 000000000..8ea8f6640 --- /dev/null +++ b/20080212/Demo/MicroBlaze/__xps/vpgen.opt @@ -0,0 +1 @@ + -p xc4vfx12ff668-10 diff --git a/20080212/Demo/MicroBlaze/__xps/xpsxflow.opt b/20080212/Demo/MicroBlaze/__xps/xpsxflow.opt new file mode 100644 index 000000000..bf6b9048d --- /dev/null +++ b/20080212/Demo/MicroBlaze/__xps/xpsxflow.opt @@ -0,0 +1 @@ +-device xc4vfx12ff668-10 diff --git a/20080212/Demo/MicroBlaze/_impact.cmd b/20080212/Demo/MicroBlaze/_impact.cmd new file mode 100644 index 000000000..a712a7180 --- /dev/null +++ b/20080212/Demo/MicroBlaze/_impact.cmd @@ -0,0 +1,7 @@ +setMode -bs +setCable -port auto +identify +identifyMPM +setAttribute -position 3 -attr configFileName -value "implementation/download.bit" +program -p 3 +quit diff --git a/20080212/Demo/MicroBlaze/crt0.s b/20080212/Demo/MicroBlaze/crt0.s new file mode 100644 index 000000000..8198096e8 --- /dev/null +++ b/20080212/Demo/MicroBlaze/crt0.s @@ -0,0 +1,126 @@ +###################################-*-asm*- +# +# Copyright (c) 2001 Xilinx, Inc. All rights reserved. +# +# Xilinx, Inc. CONFIDENTIAL +# +# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A +# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR +# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION +# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE +# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. +# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO +# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO +# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY +# AND FITNESS FOR A PARTICULAR PURPOSE. +# +# crt0.s +# +# C RunTime: +# Used for initialization of small data +# anchors and stack for programs compiled using +# Xilinx Gnu Tools. This routine also intializes the +# exception and interrupt handlers +# +# $Id: crt0.s,v 1.1.4.2 2005/05/26 21:50:39 vasanth Exp $ +# +####################################### + +/* Vector map (Interrupts, Exceptions, Breakpoints) */ +# # 0x00 # Jump to Start +# # 0x04 # nop +# # 0x08 # Imm instr for soft exception address [Hi halfword] +# # 0x0c # Jump to sof Exception handler [Lo halfword] +# # 0x10 # Imm instr for interrupt address [Hi halfword] +# # 0x14 # Jump to interrupt handler [Lo halfword] +# # 0x18 # nop - Reserved for breakpoint vector +# # 0x1C # nop - Reserved for breakpoint vector +# # 0x20 # Imm instr for hw exception address [Hi halfword] +# # 0x24 # Jump instr to hw exception handler [Lo halfword] + + .globl _start + +/* Set the exception and interrupt address vectors */ +/* to jump to the appropriate handlers */ + + .align 2 + .ent _start + _start: + bri _start1 # 0x00 + nop # 0x04 + nop # 0x08 # Reserve space for software exception vector + nop # 0x0c + nop # 0x10 # Reserve space for interrupt vector + nop # 0x14 + nop # 0x18 # Reserve space for breakpoint vector + nop # 0x1c + nop # 0x18 # Reserve space for hw exception vector + nop # 0x1c + + _start1: +/* Set the Small Data Anchors and the Stack pointer */ + la r13, r0, _SDA_BASE_ + la r2, r0, _SDA2_BASE_ + la r1, r0, _stack-16 # 16 bytes (4 words are needed by + # crt for args and link reg ) + +/* Set the opcodes brai and imm for handlers */ + la r6,r0,0xb8080000 # [opcode for brai ] + swi r6,r0,0x4 # [brai opcode for reset] + swi r6,r0,0xc # [brai opcode for exception] + swi r6,r0,0x14 # [brai opcode for interrupt] + swi r6,r0,0x24 # [brai opcode for hw exceptions] + + la r6,r0,0xb0000000 # [opcode for imm ] + swi r6,r0,0x0 # [imm opcode for reset] + swi r6,r0,0x8 # [imm opcode for exception] + swi r6,r0,0x10 # [imm opocde for interrupt] + swi r6,r0,0x20 # [imm opocde for hw exceptions] + +/* Set Reset vector */ + la r6,r0,_start1 + sw r6,r1,r0 + lhu r7,r1,r0 + shi r7,r0, 0x2 # [imm for reset] + shi r6,r0, 0x6 # [lower half for reset] + +/* Set Software Exception Handler */ + la r6,r0,_exception_handler + sw r6,r1,r0 + lhu r7,r1,r0 + shi r7,r0, 0xa # [imm for exception] + shi r6,r0, 0xe # [lower half for exception ] + +/* Set Interrupt Handler */ + la r6,r0,_interrupt_handler + sw r6,r1,r0 + lhu r7,r1,r0 + shi r7,r0, 0x12 # [imm for exception] + shi r6,r0, 0x16 # [lower half for intterupt ] + +/* Set HW Exception Handler */ + la r6,r0,_hw_exception_handler + sw r6,r1,r0 + lhu r7,r1,r0 + shi r7,r0, 0x22 # [imm for exception] + shi r6,r0, 0x26 # [lower half for hw exception] + +/* initialize bss sections */ + brlid r15,_crtinit + nop + +/* Adjust the stack pointer */ + addi r1,r1,16 + +/* Fall through to exit */ + .end _start + +/* Use this exit function */ + .globl exit # exit library call + .ent exit +exit: + bri exit + .end exit + diff --git a/20080212/Demo/MicroBlaze/data/system.ucf b/20080212/Demo/MicroBlaze/data/system.ucf new file mode 100644 index 000000000..81a63a2f8 --- /dev/null +++ b/20080212/Demo/MicroBlaze/data/system.ucf @@ -0,0 +1,74 @@ +############################################################################ +## This system.ucf file is generated by Base System Builder based on the +## settings in the selected Xilinx Board Definition file. Please add other +## user constraints to this file based on customer design specifications. +############################################################################ + +Net sys_clk_pin LOC=AE14; +Net sys_clk_pin IOSTANDARD = LVCMOS33; +Net sys_rst_pin LOC=D6; +Net sys_rst_pin PULLUP; +## System level constraints +Net sys_clk_pin TNM_NET = sys_clk_pin; +TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 10000 ps; +Net sys_rst_pin TIG; + +## FPGA pin constraints +Net fpga_0_RS232_Uart_RX_pin LOC=W2; +Net fpga_0_RS232_Uart_RX_pin IOSTANDARD = LVCMOS33; +Net fpga_0_RS232_Uart_TX_pin LOC=W1; +Net fpga_0_RS232_Uart_TX_pin IOSTANDARD = LVCMOS33; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> LOC=G5; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> PULLUP; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> SLEW = SLOW; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> DRIVE = 2; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> TIG; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> LOC=G6; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> PULLUP; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> SLEW = SLOW; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> DRIVE = 2; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> TIG; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> LOC=A11; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> PULLUP; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> SLEW = SLOW; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> DRIVE = 2; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> TIG; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> LOC=A12; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> PULLUP; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> SLEW = SLOW; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> DRIVE = 2; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> TIG; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> LOC=C6; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> PULLUP; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> SLEW = SLOW; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> DRIVE = 2; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> TIG; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> LOC=F9; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> PULLUP; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> SLEW = SLOW; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> DRIVE = 2; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> TIG; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> LOC=A5; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> PULLUP; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> SLEW = SLOW; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> DRIVE = 2; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> TIG; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> LOC=E10; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> PULLUP; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> SLEW = SLOW; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> DRIVE = 2; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> TIG; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> LOC=E2; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> IOSTANDARD = LVCMOS25; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> PULLUP; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> SLEW = SLOW; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> DRIVE = 2; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> TIG; diff --git a/20080212/Demo/MicroBlaze/etc/bitgen.ut b/20080212/Demo/MicroBlaze/etc/bitgen.ut new file mode 100644 index 000000000..442444880 --- /dev/null +++ b/20080212/Demo/MicroBlaze/etc/bitgen.ut @@ -0,0 +1,21 @@ +-g ConfigRate:4 +-g CclkPin:PULLUP +-g TdoPin:PULLNONE +-g M1Pin:PULLDOWN +-g DonePin:PULLUP +-g DriveDone:No +-g StartUpClk:JTAGCLK +-g DONE_cycle:4 +-g GTS_cycle:5 +-g M0Pin:PULLUP +-g M2Pin:PULLUP +-g ProgPin:PULLUP +-g TckPin:PULLUP +-g TdiPin:PULLUP +-g TmsPin:PULLUP +-g DonePipe:No +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:NONE +-m +-g Persist:No diff --git a/20080212/Demo/MicroBlaze/etc/bitgen_spartan3.ut b/20080212/Demo/MicroBlaze/etc/bitgen_spartan3.ut new file mode 100644 index 000000000..65522563b --- /dev/null +++ b/20080212/Demo/MicroBlaze/etc/bitgen_spartan3.ut @@ -0,0 +1,15 @@ +-g CclkPin:PULLUP +-g TdoPin:PULLNONE +-g M1Pin:PULLDOWN +-g DonePin:PULLUP +-g StartUpClk:JTAGCLK +-g M0Pin:PULLUP +-g M2Pin:PULLUP +-g ProgPin:PULLUP +-g TckPin:PULLUP +-g TdiPin:PULLUP +-g TmsPin:PULLUP +-g LCK_cycle:NoWait +-g Security:NONE +-m +-g Persist:No diff --git a/20080212/Demo/MicroBlaze/etc/download.cmd b/20080212/Demo/MicroBlaze/etc/download.cmd new file mode 100644 index 000000000..15728dcff --- /dev/null +++ b/20080212/Demo/MicroBlaze/etc/download.cmd @@ -0,0 +1,6 @@ +setMode -bscan +setCable -p auto +identify +assignfile -p 3 -file implementation/download.bit +program -p 3 +quit diff --git a/20080212/Demo/MicroBlaze/etc/fast_runtime.opt b/20080212/Demo/MicroBlaze/etc/fast_runtime.opt new file mode 100644 index 000000000..7335e7a21 --- /dev/null +++ b/20080212/Demo/MicroBlaze/etc/fast_runtime.opt @@ -0,0 +1,80 @@ +FLOWTYPE = FPGA; +############################################################### +## Filename: fast_runtime.opt +## +## Option File For Xilinx FPGA Implementation Flow for Fast +## Runtime. +## +## Version: 4.1.1 +############################################################### +# +# Options for Translator +# +# Type "ngdbuild -h" for a detailed list of ngdbuild command line options +# +Program ngdbuild +-p ; # Partname to use - picked from xflow commandline +-nt timestamp; # NGO File generation. Regenerate only when + # source netlist is newer than existing + # NGO file (default) +-bm .bmm # Block RAM memory map file +; # User design - pick from xflow command line +-uc .ucf; # ucf constraints +.ngd; # Name of NGD file. Filebase same as design filebase +End Program ngdbuild + +# +# Options for Mapper +# +# Type "map -h " for a detailed list of map command line options +# +Program map +-o _map.ncd; # Output Mapped ncd file +-pr b; # Pack internal FF/latches into IOBs +#-fp .mfp; # Floorplan file +.ngd; # Input NGD file +.pcf; # Physical constraints file +END Program map + +# +# Options for Post Map Trace +# +# Type "trce -h" for a detailed list of trce command line options +# +Program post_map_trce +-e 3; # Produce error report limited to 3 items per constraint +#-o _map.twr; # Output trace report file +-xml _map.twx; # Output XML version of the timing report +#-tsi _map.tsi; # Produce Timing Specification Interaction report +_map.ncd; # Input mapped ncd +.pcf; # Physical constraints file +END Program post_map_trce + +# +# Options for Place and Route +# +# Type "par -h" for a detailed list of par command line options +# +Program par +-w; # Overwrite existing placed and routed ncd +-ol high; # Overall effort level +_map.ncd; # Input mapped NCD file +.ncd; # Output placed and routed NCD +.pcf; # Input physical constraints file +END Program par + +# +# Options for Post Par Trace +# +# Type "trce -h" for a detailed list of trce command line options +# +Program post_par_trce +-e 3; # Produce error report limited to 3 items per constraint +#-o .twr; # Output trace report file +-xml .twx; # Output XML version of the timing report +#-tsi .tsi; # Produce Timing Specification Interaction report +.ncd; # Input placed and routed ncd +.pcf; # Physical constraints file +END Program post_par_trce + + diff --git a/20080212/Demo/MicroBlaze/etc/xmd_microblaze_0.opt b/20080212/Demo/MicroBlaze/etc/xmd_microblaze_0.opt new file mode 100644 index 000000000..43994b0af --- /dev/null +++ b/20080212/Demo/MicroBlaze/etc/xmd_microblaze_0.opt @@ -0,0 +1 @@ +connect mb mdm -cable type xilinx_parallel port LPT1 frequency 5000000 -debugdevice cpunr 1 diff --git a/20080212/Demo/MicroBlaze/main.c b/20080212/Demo/MicroBlaze/main.c new file mode 100644 index 000000000..568f50a19 --- /dev/null +++ b/20080212/Demo/MicroBlaze/main.c @@ -0,0 +1,446 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + * Creates all the demo application tasks, then starts the scheduler. The WEB + * documentation provides more details of the standard demo application tasks. + * + * In addition to the standard tasks, main() creates two "Register Check" + * tasks. These tasks write known values into every general purpose register, + * then check each register to ensure it still contains the expected (written) + * value. The register check tasks operate at the idle priority so will get + * repeatedly preempted. A register being found to contain an incorrect value + * following such a preemption would be indicative of an error in the context + * switch mechanism. + * + * Main.c also creates a task called "Check". This only executes every three + * seconds but has the highest priority so is guaranteed to get processor time. + * Its main function is to check that all the other tasks are still operational. + * Each task (other than the "flash" tasks) maintains a unique count that is + * incremented each time the task successfully completes its function. Should + * any error occur within such a task the count is permanently halted. The + * check task inspects the count of each task to ensure it has changed since + * the last time the check task executed. If all the count variables have + * changed all the tasks are still executing error free, and the check task + * toggles the onboard LED. Should any task contain an error at any time + * the LED toggle rate will change from 3 seconds to 500ms. + * + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo application includes. */ +#include "ParTest.h" +#include "flash.h" +#include "comtest2.h" +#include "integer.h" +#include "semtest.h" +#include "BlockQ.h" +#include "dynamic.h" +#include "PollQ.h" + +/* Hardware library includes. */ +#include + +/* The rate at which the 'check' LED will flash when no errors have been +detected. */ +#define mainNO_ERROR_CHECK_PERIOD 3000 + +/* The rate at which the 'check' LED will flash when an error has been +detected in one of the demo tasks. */ +#define mainERROR_CHECK_PERIOD 500 + +/* Demo application task priorities. */ +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) + +/* Software cannot influence the BAUD rate used by the simple UART +implementation. */ +#define mainBAUD_RATE 0 + +/* The LED flashed by the 'check' task to indicate the system status. */ +#define mainCHECK_TASK_LED 3 + +/* The first LED flashed by the COM port test tasks. LED mainCOM_TEST_LED + 1 +will also be used. */ +#define mainCOM_TEST_LED 4 + +/* The register test task does not make any function calls so does not require +much stack at all. */ +#define mainTINY_STACK 70 + +/* + * The task that executes at the highest priority and calls + * prvCheckOtherTasksAreStillRunning(). See the description at the top + * of the file. + */ +static void vErrorChecks( void *pvParameters ); + +/* + * Checks that all the demo application tasks are still executing without error + * - as described at the top of the file. + */ +static portBASE_TYPE prvCheckOtherTasksAreStillRunning( void ); + +/* + * The register test task as described at the top of this file. + */ +static void vRegisterTest( void *pvParameters ); + +/* + * Perform any necessary hardware configuration. + */ +static void prvSetupHardware( void ); + +/* Set to pdFAIL should an error be discovered in the register test tasks. */ +static unsigned portLONG ulRegisterTestStatus = pdPASS; +const unsigned portLONG *pulStatusAddr = &ulRegisterTestStatus; + +/*-----------------------------------------------------------*/ + +/* + * Create all the demo tasks - then start the scheduler. + */ +int main (void) +{ + /* When re-starting a debug session (rather than cold booting) we want + to ensure the installed interrupt handlers do not execute until after the + scheduler has been started. */ + portDISABLE_INTERRUPTS(); + + prvSetupHardware(); + + /* Start the standard demo application tasks. */ + vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainBAUD_RATE, mainCOM_TEST_LED ); + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vStartDynamicPriorityTasks(); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + + /* Create two register check tasks - using a different parameter for each. + The parameter is used to generate the known values written to the registers. */ + #if configUSE_PREEMPTION == 1 + xTaskCreate( vRegisterTest, "Reg1", mainTINY_STACK, ( void * ) 10, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vRegisterTest, "Reg2", mainTINY_STACK, ( void * ) 20, tskIDLE_PRIORITY, NULL ); + #endif + + /* Create the 'check' task that is defined in this file. */ + xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Finally start the scheduler. */ + vTaskStartScheduler(); + + /* Should not get here as the processor is now under control of the + scheduler! */ + + return 0; +} +/*-----------------------------------------------------------*/ + +static void vErrorChecks( void *pvParameters ) +{ +portTickType xDelayPeriod = mainNO_ERROR_CHECK_PERIOD; + + /* The parameters are not used. */ + ( void ) pvParameters; + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. The delay period used will depend on whether + or not an error has been discovered in one of the demo tasks. */ + for( ;; ) + { + vTaskDelay( xDelayPeriod ); + if( !prvCheckOtherTasksAreStillRunning() ) + { + /* An error has been found. Shorten the delay period to make + the LED flash faster. */ + xDelayPeriod = mainERROR_CHECK_PERIOD; + } + + vParTestToggleLED( mainCHECK_TASK_LED ); + } +} +/*-----------------------------------------------------------*/ + +static portBASE_TYPE prvCheckOtherTasksAreStillRunning( void ) +{ +static portBASE_TYPE xAllTestsPass = pdTRUE; + + /* Return pdFALSE if any demo application task set has encountered + an error. */ + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + xAllTestsPass = pdFALSE; + } + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + xAllTestsPass = pdFALSE; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + xAllTestsPass = pdFALSE; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + xAllTestsPass = pdFAIL; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + xAllTestsPass = ( portLONG ) pdFAIL; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + xAllTestsPass = ( portLONG ) pdFAIL; + } + + /* Mutual exclusion on this variable is not necessary as we only read it. */ + if( ulRegisterTestStatus != pdPASS ) + { + xAllTestsPass = pdFALSE; + } + + return xAllTestsPass; +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Ensure the interrupt controller is enabled in order that subsequent + code can successfully configure the peripherals. */ + XIntc_mMasterEnable( XPAR_OPB_INTC_0_BASEADDR ); + + /* Initialise the GPIO used for the LED's. */ + vParTestInitialise(); +} +/*-----------------------------------------------------------*/ + +static void vRegisterTest( void *pvParameters ) +{ + for( ;; ) + { + /* Fill the registers with their register number plus the offset + (added) value. The added value is passed in as a parameter so + is contained in r5. */ + asm volatile ( "addi r3, r5, 3 \n\t" \ + "addi r4, r5, 4 \n\t" \ + "addi r6, r5, 6 \n\t" \ + "addi r7, r5, 7 \n\t" \ + "addi r8, r5, 8 \n\t" \ + "addi r9, r5, 9 \n\t" \ + "addi r10, r5, 10 \n\t" \ + "addi r11, r5, 11 \n\t" \ + "addi r12, r5, 12 \n\t" \ + "addi r16, r5, 16 \n\t" \ + "addi r17, r5, 17 \n\t" \ + "addi r18, r5, 18 \n\t" \ + "addi r19, r5, 19 \n\t" \ + "addi r20, r5, 20 \n\t" \ + "addi r21, r5, 21 \n\t" \ + "addi r22, r5, 22 \n\t" \ + "addi r23, r5, 23 \n\t" \ + "addi r24, r5, 24 \n\t" \ + "addi r25, r5, 25 \n\t" \ + "addi r26, r5, 26 \n\t" \ + "addi r27, r5, 27 \n\t" \ + "addi r28, r5, 28 \n\t" \ + "addi r29, r5, 29 \n\t" \ + "addi r30, r5, 30 \n\t" \ + "addi r31, r5, 31 \n\t" + ); + + /* Now read back the register values to ensure they are as we expect. + This task will get preempted frequently so other tasks are likely to + have executed since the register values were written. */ + + /* r3 should contain r5 + 3. Subtract 3 to leave r3 equal to r5. */ + asm volatile ( "addi r3, r3, -3 " ); + + /* Compare r3 and r5. If they are not equal then either r3 or r5 + contains the wrong value and *pulStatusAddr is to pdFAIL. */ + asm volatile ( "cmp r3, r3, r5 \n\t" \ + "beqi r3, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" + ); + + /* Repeat for all the other registers. */ + asm volatile ( "addi r4, r4, -4 \n\t" \ + "cmp r4, r4, r5 \n\t" \ + "beqi r4, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" \ + "addi r6, r6, -6 \n\t" \ + "cmp r6, r6, r5 \n\t" \ + "beqi r6, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" \ + "addi r7, r7, -7 \n\t" \ + "cmp r7, r7, r5 \n\t" \ + "beqi r7, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" \ + "addi r8, r8, -8 \n\t" \ + "cmp r8, r8, r5 \n\t" \ + "beqi r8, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" \ + "addi r9, r9, -9 \n\t" \ + "cmp r9, r9, r5 \n\t" \ + "beqi r9, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" \ + "addi r10, r10, -10 \n\t" \ + "cmp r10, r10, r5 \n\t" \ + "beqi r10, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" \ + "addi r11, r11, -11 \n\t" \ + "cmp r11, r11, r5 \n\t" \ + "beqi r11, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" \ + "addi r12, r12, -12 \n\t" \ + "cmp r12, r12, r5 \n\t" \ + "beqi r12, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" \ + "sw r0, r0, r3 \n\t" \ + "addi r16, r16, -16 \n\t" \ + "cmp r16, r16, r5 \n\t" \ + "beqi r16, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" \ + "addi r17, r17, -17 \n\t" \ + "cmp r17, r17, r5 \n\t" \ + "beqi r17, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" \ + "addi r18, r18, -18 \n\t" \ + "cmp r18, r18, r5 \n\t" \ + "beqi r18, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" \ + "addi r19, r19, -19 \n\t" \ + "cmp r19, r19, r5 \n\t" \ + "beqi r19, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" \ + "addi r20, r20, -20 \n\t" \ + "cmp r20, r20, r5 \n\t" \ + "beqi r20, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" \ + "addi r21, r21, -21 \n\t" \ + "cmp r21, r21, r5 \n\t" \ + "beqi r21, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" \ + "addi r22, r22, -22 \n\t" \ + "cmp r22, r22, r5 \n\t" \ + "beqi r22, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" \ + "addi r23, r23, -23 \n\t" \ + "cmp r23, r23, r5 \n\t" \ + "beqi r23, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" \ + "addi r24, r24, -24 \n\t" \ + "cmp r24, r24, r5 \n\t" \ + "beqi r24, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" \ + "addi r25, r25, -25 \n\t" \ + "cmp r25, r25, r5 \n\t" \ + "beqi r25, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" \ + "addi r26, r26, -26 \n\t" \ + "cmp r26, r26, r5 \n\t" \ + "beqi r26, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" \ + "addi r27, r27, -27 \n\t" \ + "cmp r27, r27, r5 \n\t" \ + "beqi r27, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" \ + "addi r28, r28, -28 \n\t" \ + "cmp r28, r28, r5 \n\t" \ + "beqi r28, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" \ + "addi r29, r29, -29 \n\t" \ + "cmp r29, r29, r5 \n\t" \ + "beqi r29, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" \ + "addi r30, r30, -30 \n\t" \ + "cmp r30, r30, r5 \n\t" \ + "beqi r30, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" \ + "addi r31, r31, -31 \n\t" \ + "cmp r31, r31, r5 \n\t" \ + "beqi r31, 12 \n\t" \ + "lwi r3, r0, pulStatusAddr \n\t" \ + "sw r0, r0, r3 \n\t" + ); + } +} + + + diff --git a/20080212/Demo/MicroBlaze/platgen.opt b/20080212/Demo/MicroBlaze/platgen.opt new file mode 100644 index 000000000..1a984fdb6 --- /dev/null +++ b/20080212/Demo/MicroBlaze/platgen.opt @@ -0,0 +1,7 @@ +-p +xc4vfx12ff668-10 +-lang +vhdl +-st +xst +system.mhs diff --git a/20080212/Demo/MicroBlaze/serial/serial.c b/20080212/Demo/MicroBlaze/serial/serial.c new file mode 100644 index 000000000..b026a5ad8 --- /dev/null +++ b/20080212/Demo/MicroBlaze/serial/serial.c @@ -0,0 +1,205 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +/* + BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART +*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "queue.h" +#include "task.h" + +/* Demo application includes. */ +#include "serial.h" + +/* Microblaze driver includes. */ +#include "xuartlite_l.h" +#include "xintc_l.h" + +/*-----------------------------------------------------------*/ + +/* Queues used to hold received characters, and characters waiting to be +transmitted. */ +static xQueueHandle xRxedChars; +static xQueueHandle xCharsForTx; + +/*-----------------------------------------------------------*/ + +xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) +{ +unsigned portLONG ulControlReg, ulMask; + + /* NOTE: The baud rate used by this driver is determined by the hardware + parameterization of the UART Lite peripheral, and the baud value passed to + this function has no effect. */ + + /* Create the queues used to hold Rx and Tx characters. */ + xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + + if( ( xRxedChars ) && ( xCharsForTx ) ) + { + /* Disable the interrupt. */ + XUartLite_mDisableIntr( XPAR_RS232_UART_BASEADDR ); + + /* Flush the fifos. */ + ulControlReg = XIo_In32( XPAR_RS232_UART_BASEADDR + XUL_STATUS_REG_OFFSET ); + XIo_Out32( XPAR_RS232_UART_BASEADDR + XUL_CONTROL_REG_OFFSET, ulControlReg | XUL_CR_FIFO_TX_RESET | XUL_CR_FIFO_RX_RESET ); + + /* Enable the interrupt again. The interrupt controller has not yet been + initialised so there is no chance of receiving an interrupt until the + scheduler has been started. */ + XUartLite_mEnableIntr( XPAR_RS232_UART_BASEADDR ); + + /* Enable the interrupt in the interrupt controller while maintaining + all the other bit settings. */ + ulMask = XIntc_In32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ) ); + ulMask |= XPAR_RS232_UART_INTERRUPT_MASK; + XIntc_Out32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ), ( ulMask ) ); + XIntc_mAckIntr( XPAR_INTC_SINGLE_BASEADDR, 2 ); + } + + return ( xComPortHandle ) 0; +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) +{ + /* The port handle is not required as this driver only supports one UART. */ + ( void ) pxPort; + + /* Get the next character from the buffer. Return false if no characters + are available, or arrive before xBlockTime expires. */ + if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) + { + return pdTRUE; + } + else + { + return pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) +{ +portBASE_TYPE xReturn = pdTRUE; + + portENTER_CRITICAL(); + { + /* If the UART FIFO is full we can block posting the new data on the + Tx queue. */ + if( XUartLite_mIsTransmitFull( XPAR_RS232_UART_BASEADDR ) ) + { + if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) + { + xReturn = pdFAIL; + } + } + /* Otherwise, if there is data already in the queue we should add the + new data to the back of the queue to ensure the sequencing is + maintained. */ + else if( uxQueueMessagesWaiting( xCharsForTx ) ) + { + if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) + { + xReturn = pdFAIL; + } + } + /* If the UART FIFO is not full and there is no data already in the + queue we can write directly to the FIFO without disrupting the + sequence. */ + else + { + XIo_Out32( XPAR_RS232_UART_BASEADDR + XUL_TX_FIFO_OFFSET, cOutChar ); + } + } + portEXIT_CRITICAL(); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +void vSerialClose( xComPortHandle xPort ) +{ + /* Not supported as not required by the demo application. */ + ( void ) xPort; +} +/*-----------------------------------------------------------*/ + +void vSerialISR( void *pvBaseAddress ) +{ +unsigned portLONG ulISRStatus; +portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByRx = pdFALSE; +portCHAR cChar; + + /* Determine the cause of the interrupt. */ + ulISRStatus = XIo_In32( XPAR_RS232_UART_BASEADDR + XUL_STATUS_REG_OFFSET ); + + if( ( ulISRStatus & ( XUL_SR_RX_FIFO_FULL | XUL_SR_RX_FIFO_VALID_DATA ) ) != 0 ) + { + /* A character is available - place it in the queue of received + characters. This might wake a task that was blocked waiting for + data. */ + cChar = ( portCHAR )XIo_In32( XPAR_RS232_UART_BASEADDR + XUL_RX_FIFO_OFFSET ); + xTaskWokenByRx = xQueueSendFromISR( xRxedChars, &cChar, xTaskWokenByRx ); + } + + if( ( ulISRStatus & XUL_SR_TX_FIFO_EMPTY ) != 0 ) + { + /* There is space in the FIFO - if there are any characters queue for + transmission they can be send to the UART now. This might unblock a + task that was waiting for space to become available on the Tx queue. */ + if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE ) + { + XIo_Out32( XPAR_RS232_UART_BASEADDR + XUL_TX_FIFO_OFFSET, cChar ); + } + } + + /* If we woke any tasks we may require a context switch. */ + if( xTaskWokenByTx || xTaskWokenByRx ) + { + portYIELD_FROM_ISR(); + } +} diff --git a/20080212/Demo/MicroBlaze/system.bsb b/20080212/Demo/MicroBlaze/system.bsb new file mode 100644 index 000000000..cc6c27827 --- /dev/null +++ b/20080212/Demo/MicroBlaze/system.bsb @@ -0,0 +1 @@ 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\ No newline at end of file diff --git a/20080212/Demo/MicroBlaze/system.make b/20080212/Demo/MicroBlaze/system.make new file mode 100644 index 000000000..143cd8096 --- /dev/null +++ b/20080212/Demo/MicroBlaze/system.make @@ -0,0 +1,258 @@ +################################################################# +# Makefile generated by Xilinx Platform Studio +# Project:E:\Dev\FreeRTOS\Demo\MicroBlaze\system.xmp +################################################################# + +# Name of the Microprocessor system +# The hardware specification of the system is in file : +# E:\Dev\FreeRTOS\Demo\MicroBlaze\system.mhs +# The software specification of the system is in file : +# E:\Dev\FreeRTOS\Demo\MicroBlaze\system.mss + +include system_incl.make + + +################################################################# +# EXTERNAL TARGETS +################################################################# +all: + @echo "Makefile to build a Microprocessor system :" + @echo "Run make with any of the following targets" + @echo " " + @echo " netlist : Generates the netlist for the given MHS " + @echo " bits : Runs Implementation tools to generate the bitstream" + @echo " exporttopn:Export to ProjNav" + @echo " " + @echo " libs : Configures the sw libraries for this system" + @echo " program : Compiles the program sources for all the processor instances" + @echo " " + @echo " init_bram: Initializes bitstream with BRAM data" + @echo " ace : Generate ace file from bitstream and elf" + @echo " download : Downloads the bitstream onto the board" + @echo " " + @echo " sim : Generates HDL simulation models and runs simulator for chosen simulation mode" + @echo " simmodel : Generates HDL simulation models for chosen simulation mode" + @echo " behavioral_model:Generates behavioral HDL models with BRAM initialization" + @echo " structural_model:Generates structural simulation HDL models with BRAM initialization" + @echo " timing_model : Generates timing simulation HDL models with BRAM initialization" + @echo " vp : Generates virtual platform model" + @echo " " + @echo " netlistclean: Deletes netlist" + @echo " bitsclean: Deletes bit, ncd, bmm files" + @echo " hwclean : Deletes implementation dir" + @echo " libsclean: Deletes sw libraries" + @echo " programclean: Deletes compiled ELF files" + @echo " swclean : Deletes sw libraries and ELF files" + @echo " simclean : Deletes simulation dir" + @echo " vpclean : Deletes virtualplatform dir" + @echo " clean : Deletes all generated files/directories" + @echo " " + @echo " make : (Default)" + @echo " Creates a Microprocessor system using default initializations" + @echo " specified for each processor in MSS file" + + +bits: $(SYSTEM_BIT) + +ace: $(SYSTEM_ACE) + +netlist: $(POSTSYN_NETLIST) + +libs: $(LIBRARIES) + +program: $(ALL_USER_ELF_FILES) + +download: $(DOWNLOAD_BIT) dummy + @echo "*********************************************" + @echo "Downloading Bitstream onto the target board" + @echo "*********************************************" + impact -batch etc/download.cmd + +init_bram: $(DOWNLOAD_BIT) + +sim: $(DEFAULT_SIM_SCRIPT) + cd simulation/behavioral; \ + $(SIM_CMD) & + +simmodel: $(DEFAULT_SIM_SCRIPT) + +behavioral_model: $(BEHAVIORAL_SIM_SCRIPT) + +structural_model: $(STRUCTURAL_SIM_SCRIPT) + +timing_model: $(TIMING_SIM_SCRIPT) + +vp: $(VPEXEC) + +clean: hwclean libsclean programclean simclean vpclean + rm -f _impact.cmd + +hwclean: netlistclean bitsclean + rm -rf implementation synthesis xst hdl + rm -rf xst.srp $(SYSTEM).srp + +netlistclean: + rm -f $(POSTSYN_NETLIST) + rm -f $(BMM_FILE) + +bitsclean: + rm -f $(SYSTEM_BIT) + rm -f implementation/$(SYSTEM).ncd + rm -f implementation/$(SYSTEM)_bd.bmm + +bitsclean: + +simclean: + rm -rf simulation/behavioral + +swclean: libsclean programclean + @echo "" + +libsclean: $(LIBSCLEAN_TARGETS) + +programclean: $(PROGRAMCLEAN_TARGETS) + +vpclean: + rm -rf virtualplatform + +################################################################# +# SOFTWARE PLATFORM FLOW +################################################################# + + +$(LIBRARIES): $(MHSFILE) $(MSSFILE) __xps/libgen.opt + @echo "*********************************************" + @echo "Creating software libraries..." + @echo "*********************************************" + libgen $(LIBGEN_OPTIONS) $(MSSFILE) + + +microblaze_0_libsclean: + rm -rf microblaze_0/lib/ + +$(MICROBLAZE_0_XMDSTUB): $(LIBRARIES) + +################################################################# +# SOFTWARE APPLICATION RTOSDEMO +################################################################# + +RTOSDemo_program: $(RTOSDEMO_OUTPUT) + +$(RTOSDEMO_OUTPUT) : $(RTOSDEMO_SOURCES) $(RTOSDEMO_HEADERS) $(RTOSDEMO_LINKER_SCRIPT) \ + $(LIBRARIES) __xps/rtosdemo_compiler.opt + @mkdir -p $(RTOSDEMO_OUTPUT_DIR) + $(RTOSDEMO_CC) $(RTOSDEMO_CC_OPT) $(RTOSDEMO_SOURCES) -o $(RTOSDEMO_OUTPUT) \ + $(RTOSDEMO_OTHER_CC_FLAGS) $(RTOSDEMO_INCLUDES) $(RTOSDEMO_LIBPATH) \ + -xl-mode-$(RTOSDEMO_MODE) \ + $(RTOSDEMO_CFLAGS) $(RTOSDEMO_LFLAGS) + $(RTOSDEMO_CC_SIZE) $(RTOSDEMO_OUTPUT) + +RTOSDemo_programclean: + rm -f $(RTOSDEMO_OUTPUT) + +################################################################# +# BOOTLOOP ELF FILES +################################################################# + + + +$(MICROBLAZE_0_BOOTLOOP): $(MICROBLAZE_BOOTLOOP) + @mkdir -p $(BOOTLOOP_DIR) + cp -f $(MICROBLAZE_BOOTLOOP) $(MICROBLAZE_0_BOOTLOOP) + +################################################################# +# HARDWARE IMPLEMENTATION FLOW +################################################################# + + +$(BMM_FILE) \ +$(WRAPPER_NGC_FILES): $(MHSFILE) __xps/platgen.opt \ + $(CORE_STATE_DEVELOPMENT_FILES) + @echo "****************************************************" + @echo "Creating system netlist for hardware specification.." + @echo "****************************************************" + platgen $(PLATGEN_OPTIONS) -st xst $(MHSFILE) + +$(POSTSYN_NETLIST): $(WRAPPER_NGC_FILES) + @echo "Running synthesis..." + bash -c "cd synthesis; ./synthesis.sh; cd .." + +$(SYSTEM_BIT): $(BMM_FILE) $(POSTSYN_NETLIST) __xps/xpsxflow.opt \ + $(UCF_FILE) $(BITGEN_UT_FILE) $(FASTRUNTIME_OPT_FILE) + @echo "Copying Xilinx Implementation tool scripts.." + @cp -f $(BITGEN_UT_FILE) implementation/bitgen.ut + @cp -f $(FASTRUNTIME_OPT_FILE) implementation/fast_runtime.opt + @cp -f $(UCF_FILE) implementation/$(SYSTEM).ucf + @echo "*********************************************" + @echo "Running Xilinx Implementation tools.." + @echo "*********************************************" + xflow -wd implementation -p $(DEVICE) -implement fast_runtime.opt $(SYSTEM).ngc + cd implementation; bitgen -w -f bitgen.ut $(SYSTEM) + +exporttopn: + @echo "You have chosen XPS for implementation tool flow." + @echo "Please select ProjNav as your implementation flow in Project Options." + @echo "In batch mode, use commad xset pnproj ." + +$(DOWNLOAD_BIT): $(SYSTEM_BIT) $(BRAMINIT_ELF_FILES) __xps/bitinit.opt + @cp -f implementation/$(SYSTEM)_bd.bmm . + @echo "*********************************************" + @echo "Initializing BRAM contents of the bitstream" + @echo "*********************************************" + bitinit $(MHSFILE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_FILE_ARGS) \ + -bt $(SYSTEM_BIT) -o $(DOWNLOAD_BIT) + @rm -f $(SYSTEM)_bd.bmm + +$(SYSTEM_ACE): $(DOWNLOAD_BIT) $(RTOSDEMO_OUTPUT) + @echo "*********************************************" + @echo "Creating system ace file" + @echo "*********************************************" + xmd -tcl genace.tcl -jprog -hw $(DOWNLOAD_BIT) -elf $(RTOSDEMO_OUTPUT) -ace $(SYSTEM_ACE) + +################################################################# +# SIMULATION FLOW +################################################################# + + +################## BEHAVIORAL SIMULATION ################## + +$(BEHAVIORAL_SIM_SCRIPT): $(MHSFILE) __xps/simgen.opt \ + $(BRAMINIT_ELF_FILES) + @echo "*********************************************" + @echo "Creating behavioral simulation models..." + @echo "*********************************************" + simgen $(SIMGEN_OPTIONS) -m behavioral $(MHSFILE) + +################## STRUCTURAL SIMULATION ################## + +$(STRUCTURAL_SIM_SCRIPT): $(WRAPPER_NGC_FILES) __xps/simgen.opt \ + $(BRAMINIT_ELF_FILES) + @echo "*********************************************" + @echo "Creating structural simulation models..." + @echo "*********************************************" + simgen $(SIMGEN_OPTIONS) -sd implementation -m structural $(MHSFILE) + + +################## TIMING SIMULATION ################## + +$(TIMING_SIM_SCRIPT): $(SYSTEM_BIT) __xps/simgen.opt \ + $(BRAMINIT_ELF_FILES) + @echo "*********************************************" + @echo "Creating timing simulation models..." + @echo "*********************************************" + simgen $(SIMGEN_OPTIONS) -sd implementation -m timing $(MHSFILE) + +################################################################# +# VIRTUAL PLATFORM FLOW +################################################################# + + +$(VPEXEC): $(MHSFILE) __xps/vpgen.opt + @echo "****************************************************" + @echo "Creating virtual platform for hardware specification.." + @echo "****************************************************" + vpgen $(VPGEN_OPTIONS) $(MHSFILE) + +dummy: + @echo "" + diff --git a/20080212/Demo/MicroBlaze/system.mhs b/20080212/Demo/MicroBlaze/system.mhs new file mode 100644 index 000000000..2999abcea --- /dev/null +++ b/20080212/Demo/MicroBlaze/system.mhs @@ -0,0 +1,196 @@ +# ############################################################################## +# Created by Base System Builder Wizard for Xilinx EDK 7.1.2 Build EDK_H.12.5.1 +# Sun Nov 13 16:46:19 2005 +# Target Board: Xilinx Virtex 4 ML403 Evaluation Platform Rev 1 +# Family: virtex4 +# Device: xc4vfx12 +# Package: ff668 +# Speed Grade: -10 +# Processor: Microblaze +# System clock frequency: 100.000000 MHz +# Debug interface: On-Chip HW Debug Module +# On Chip Memory : 64 KB +# ############################################################################## + + + PARAMETER VERSION = 2.1.0 + + + PORT fpga_0_RS232_Uart_RX_pin = fpga_0_RS232_Uart_RX, DIR = INPUT + PORT fpga_0_RS232_Uart_TX_pin = fpga_0_RS232_Uart_TX, DIR = OUTPUT + PORT fpga_0_LEDs_4Bit_GPIO_IO_pin = fpga_0_LEDs_4Bit_GPIO_IO, DIR = INOUT, VEC = [0:3] + PORT fpga_0_LEDs_Positions_GPIO_IO_pin = fpga_0_LEDs_Positions_GPIO_IO, DIR = INOUT, VEC = [0:4] + PORT sys_clk_pin = dcm_clk_s, DIR = INPUT, SIGIS = DCMCLK + PORT sys_rst_pin = sys_rst_s, DIR = INPUT + + +BEGIN microblaze + PARAMETER INSTANCE = microblaze_0 + PARAMETER HW_VER = 4.00.a + PARAMETER C_DEBUG_ENABLED = 1 + PARAMETER C_NUMBER_OF_PC_BRK = 2 + PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1 + PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1 + BUS_INTERFACE DLMB = dlmb + BUS_INTERFACE ILMB = ilmb + BUS_INTERFACE DOPB = mb_opb + BUS_INTERFACE IOPB = mb_opb + PORT CLK = sys_clk_s + PORT DBG_CAPTURE = DBG_CAPTURE_s + PORT DBG_CLK = DBG_CLK_s + PORT DBG_REG_EN = DBG_REG_EN_s + PORT DBG_TDI = DBG_TDI_s + PORT DBG_TDO = DBG_TDO_s + PORT DBG_UPDATE = DBG_UPDATE_s + PORT Interrupt = Interrupt +END + +BEGIN opb_v20 + PARAMETER INSTANCE = mb_opb + PARAMETER HW_VER = 1.10.c + PARAMETER C_EXT_RESET_HIGH = 0 + PORT SYS_Rst = sys_rst_s + PORT OPB_Clk = sys_clk_s +END + +BEGIN opb_mdm + PARAMETER INSTANCE = debug_module + PARAMETER HW_VER = 2.00.a + PARAMETER C_MB_DBG_PORTS = 1 + PARAMETER C_USE_UART = 1 + PARAMETER C_UART_WIDTH = 8 + PARAMETER C_BASEADDR = 0x41400000 + PARAMETER C_HIGHADDR = 0x4140ffff + BUS_INTERFACE SOPB = mb_opb + PORT OPB_Clk = sys_clk_s + PORT DBG_CAPTURE_0 = DBG_CAPTURE_s + PORT DBG_CLK_0 = DBG_CLK_s + PORT DBG_REG_EN_0 = DBG_REG_EN_s + PORT DBG_TDI_0 = DBG_TDI_s + PORT DBG_TDO_0 = DBG_TDO_s + PORT DBG_UPDATE_0 = DBG_UPDATE_s +END + +BEGIN lmb_v10 + PARAMETER INSTANCE = ilmb + PARAMETER HW_VER = 1.00.a + PARAMETER C_EXT_RESET_HIGH = 0 + PORT SYS_Rst = sys_rst_s + PORT LMB_Clk = sys_clk_s +END + +BEGIN lmb_v10 + PARAMETER INSTANCE = dlmb + PARAMETER HW_VER = 1.00.a + PARAMETER C_EXT_RESET_HIGH = 0 + PORT SYS_Rst = sys_rst_s + PORT LMB_Clk = sys_clk_s +END + +BEGIN lmb_bram_if_cntlr + PARAMETER INSTANCE = dlmb_cntlr + PARAMETER HW_VER = 1.00.b + PARAMETER C_BASEADDR = 0x00000000 + PARAMETER C_HIGHADDR = 0x0000ffff + BUS_INTERFACE SLMB = dlmb + BUS_INTERFACE BRAM_PORT = dlmb_port +END + +BEGIN lmb_bram_if_cntlr + PARAMETER INSTANCE = ilmb_cntlr + PARAMETER HW_VER = 1.00.b + PARAMETER C_BASEADDR = 0x00000000 + PARAMETER C_HIGHADDR = 0x0000ffff + BUS_INTERFACE SLMB = ilmb + BUS_INTERFACE BRAM_PORT = ilmb_port +END + +BEGIN bram_block + PARAMETER INSTANCE = lmb_bram + PARAMETER HW_VER = 1.00.a + BUS_INTERFACE PORTA = ilmb_port + BUS_INTERFACE PORTB = dlmb_port +END + +BEGIN opb_uartlite + PARAMETER INSTANCE = RS232_Uart + PARAMETER HW_VER = 1.00.b + PARAMETER C_BAUDRATE = 9600 + PARAMETER C_DATA_BITS = 8 + PARAMETER C_ODD_PARITY = 0 + PARAMETER C_USE_PARITY = 0 + PARAMETER C_CLK_FREQ = 100000000 + PARAMETER C_BASEADDR = 0x40600000 + PARAMETER C_HIGHADDR = 0x4060ffff + BUS_INTERFACE SOPB = mb_opb + PORT OPB_Clk = sys_clk_s + PORT Interrupt = RS232_Uart_Interrupt + PORT RX = fpga_0_RS232_Uart_RX + PORT TX = fpga_0_RS232_Uart_TX +END + +BEGIN opb_gpio + PARAMETER INSTANCE = LEDs_4Bit + PARAMETER HW_VER = 3.01.b + PARAMETER C_GPIO_WIDTH = 4 + PARAMETER C_IS_DUAL = 0 + PARAMETER C_IS_BIDIR = 1 + PARAMETER C_ALL_INPUTS = 0 + PARAMETER C_BASEADDR = 0x40020000 + PARAMETER C_HIGHADDR = 0x4002ffff + BUS_INTERFACE SOPB = mb_opb + PORT OPB_Clk = sys_clk_s + PORT GPIO_IO = fpga_0_LEDs_4Bit_GPIO_IO +END + +BEGIN opb_gpio + PARAMETER INSTANCE = LEDs_Positions + PARAMETER HW_VER = 3.01.b + PARAMETER C_GPIO_WIDTH = 5 + PARAMETER C_IS_DUAL = 0 + PARAMETER C_IS_BIDIR = 1 + PARAMETER C_ALL_INPUTS = 0 + PARAMETER C_BASEADDR = 0x40000000 + PARAMETER C_HIGHADDR = 0x4000ffff + BUS_INTERFACE SOPB = mb_opb + PORT OPB_Clk = sys_clk_s + PORT GPIO_IO = fpga_0_LEDs_Positions_GPIO_IO +END + +BEGIN opb_timer + PARAMETER INSTANCE = opb_timer_1 + PARAMETER HW_VER = 1.00.b + PARAMETER C_COUNT_WIDTH = 32 + PARAMETER C_ONE_TIMER_ONLY = 1 + PARAMETER C_BASEADDR = 0x41c00000 + PARAMETER C_HIGHADDR = 0x41c0ffff + BUS_INTERFACE SOPB = mb_opb + PORT OPB_Clk = sys_clk_s + PORT Interrupt = opb_timer_1_Interrupt +END + +BEGIN opb_intc + PARAMETER INSTANCE = opb_intc_0 + PARAMETER HW_VER = 1.00.c + PARAMETER C_BASEADDR = 0x41200000 + PARAMETER C_HIGHADDR = 0x4120ffff + PARAMETER C_HAS_IPR = 0 + BUS_INTERFACE SOPB = mb_opb + PORT Irq = Interrupt + PORT Intr = RS232_Uart_Interrupt & opb_timer_1_Interrupt +END + +BEGIN dcm_module + PARAMETER INSTANCE = dcm_0 + PARAMETER HW_VER = 1.00.a + PARAMETER C_CLK0_BUF = TRUE + PARAMETER C_CLKIN_PERIOD = 10.000000 + PARAMETER C_CLK_FEEDBACK = 1X + PARAMETER C_EXT_RESET_HIGH = 1 + PORT CLKIN = dcm_clk_s + PORT CLK0 = sys_clk_s + PORT CLKFB = sys_clk_s + PORT RST = net_gnd + PORT LOCKED = dcm_0_lock +END + diff --git a/20080212/Demo/MicroBlaze/system.mss b/20080212/Demo/MicroBlaze/system.mss new file mode 100644 index 000000000..6c13869ca --- /dev/null +++ b/20080212/Demo/MicroBlaze/system.mss @@ -0,0 +1,84 @@ + + PARAMETER VERSION = 2.2.0 + + +BEGIN OS + PARAMETER OS_NAME = standalone + PARAMETER OS_VER = 1.00.a + PARAMETER PROC_INSTANCE = microblaze_0 +END + + +BEGIN PROCESSOR + PARAMETER DRIVER_NAME = cpu + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = microblaze_0 + PARAMETER COMPILER = mb-gcc + PARAMETER ARCHIVER = mb-ar + PARAMETER XMDSTUB_PERIPHERAL = debug_module +END + + +BEGIN DRIVER + PARAMETER DRIVER_NAME = opbarb + PARAMETER DRIVER_VER = 1.02.a + PARAMETER HW_INSTANCE = mb_opb +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = uartlite + PARAMETER DRIVER_VER = 1.00.b + PARAMETER HW_INSTANCE = debug_module +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = bram + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = dlmb_cntlr +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = bram + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = ilmb_cntlr +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = uartlite + PARAMETER DRIVER_VER = 1.00.b + PARAMETER HW_INSTANCE = RS232_Uart + PARAMETER int_handler = vSerialISR, int_port = Interrupt +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = gpio + PARAMETER DRIVER_VER = 2.00.a + PARAMETER HW_INSTANCE = LEDs_4Bit +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = gpio + PARAMETER DRIVER_VER = 2.00.a + PARAMETER HW_INSTANCE = LEDs_Positions +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = tmrctr + PARAMETER DRIVER_VER = 1.00.b + PARAMETER HW_INSTANCE = opb_timer_1 + PARAMETER int_handler = vTickISR, int_port = Interrupt +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = intc + PARAMETER DRIVER_VER = 1.00.c + PARAMETER HW_INSTANCE = opb_intc_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = dcm_0 +END + + diff --git a/20080212/Demo/MicroBlaze/system.xmp b/20080212/Demo/MicroBlaze/system.xmp new file mode 100644 index 000000000..c899fd9b5 --- /dev/null +++ b/20080212/Demo/MicroBlaze/system.xmp @@ -0,0 +1,66 @@ +#Please do not modify this file by hand +XmpVersion: 7.1 +IntStyle: default +MHS File: system.mhs +MSS File: system.mss +NPL File: projnav/system.ise +Architecture: virtex4 +Device: xc4vfx12 +Package: ff668 +SpeedGrade: -10 +UseProjNav: 0 +AddToNPL: 0 +PNImportBitFile: +PNImportBmmFile: +UserCmd1: +UserCmd1Type: 0 +UserCmd2: +UserCmd2Type: 0 +SynProj: xst +ReloadPbde: 0 +MainMhsEditor: 0 +InsertNoPads: 0 +HdlLang: VHDL +Simulator: mti +SimModel: BEHAVIORAL +SimXLib: +SimEdkLib: +MixLangSim: 1 +UcfFile: data/system.ucf +Processor: microblaze_0 +BootLoop: 0 +XmdStub: 0 +SwProj: RTOSDemo +Processor: microblaze_0 +Executable: RTOSDemo/executable.elf +Source: main.c +Source: ParTest/ParTest.c +Source: ../../Source/tasks.c +Source: ../../Source/queue.c +Source: ../../Source/list.c +Source: ../../Source/portable/MemMang/heap_1.c +Source: ../../Source/portable/GCC/MicroBlaze/port.c +Source: ../../Source/portable/GCC/MicroBlaze/portasm.s +Source: ../Common/Minimal/flash.c +Source: serial/serial.c +Source: ../Common/Minimal/comtest.c +Source: ../Common/Minimal/integer.c +Source: ../Common/Minimal/semtest.c +Source: ../Common/Minimal/dynamic.c +Source: ../Common/Minimal/PollQ.c +Source: ../Common/Minimal/BlockQ.c +Header: FreeRTOSConfig.h +DefaultInit: EXECUTABLE +InitBram: 1 +Active: 1 +CompilerOptLevel: 4 +GlobPtrOpt: 0 +DebugSym: 1 +SearchIncl: . ../Common/include ../../Source/include ../../Source/portable/GCC/MicroBlaze +AsmOpt: +LinkOpt: -Map=rtosdemo.map +ProgStart: +StackSize: +HeapSize: +LinkerScript: +ProgCCFlags: -D MICROBLAZE_GCC -Wall diff --git a/20080212/Demo/MicroBlaze/system_incl.make b/20080212/Demo/MicroBlaze/system_incl.make new file mode 100644 index 000000000..9973ee322 --- /dev/null +++ b/20080212/Demo/MicroBlaze/system_incl.make @@ -0,0 +1,134 @@ +################################################################# +# Makefile generated by Xilinx Platform Studio +# Project:E:\Dev\FreeRTOS\Demo\MicroBlaze\system.xmp +################################################################# + +XILINX_EDK_DIR = C:/devtools/xilinx/EDK + +SYSTEM = system + +MHSFILE = system.mhs + +MSSFILE = system.mss + +FPGA_ARCH = virtex4 + +DEVICE = xc4vfx12ff668-10 + +LANGUAGE = vhdl + +SEARCHPATHOPT = + +SUBMODULE_OPT = + +PLATGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(SUBMODULE_OPT) + +LIBGEN_OPTIONS = -mhs $(MHSFILE) -p $(DEVICE) $(SEARCHPATHOPT) \ + $(MICROBLAZE_0_LIBG_OPT) + +VPGEN_OPTIONS = -p $(DEVICE) $(SEARCHPATHOPT) + +RTOSDEMO_OUTPUT_DIR = RTOSDemo +RTOSDEMO_OUTPUT = $(RTOSDEMO_OUTPUT_DIR)/executable.elf + +MICROBLAZE_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/microblaze/mb_bootloop.elf +PPC405_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc405/ppc_bootloop.elf +BOOTLOOP_DIR = bootloops + +MICROBLAZE_0_BOOTLOOP = $(BOOTLOOP_DIR)/microblaze_0.elf +MICROBLAZE_0_XMDSTUB = microblaze_0/code/xmdstub.elf + +BRAMINIT_ELF_FILES = $(RTOSDEMO_OUTPUT) +BRAMINIT_ELF_FILE_ARGS = -pe microblaze_0 $(RTOSDEMO_OUTPUT) + +ALL_USER_ELF_FILES = $(RTOSDEMO_OUTPUT) + +SIM_CMD = vsim + +BEHAVIORAL_SIM_SCRIPT = simulation/behavioral/$(SYSTEM).do + +STRUCTURAL_SIM_SCRIPT = simulation/structural/$(SYSTEM).do + +TIMING_SIM_SCRIPT = simulation/timing/$(SYSTEM).do + +DEFAULT_SIM_SCRIPT = $(BEHAVIORAL_SIM_SCRIPT) + +MIX_LANG_SIM_OPT = -mixed yes + +SIMGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(SUBMODULE_OPT) $(BRAMINIT_ELF_FILE_ARGS) $(MIX_LANG_SIM_OPT) -s mti + +MICROBLAZE_0_XMDSTUB = microblaze_0/code/xmdstub.elf + +LIBRARIES = \ + microblaze_0/lib/libxil.a +VPEXEC = virtualplatform/vpexec.exe + +LIBSCLEAN_TARGETS = microblaze_0_libsclean + +PROGRAMCLEAN_TARGETS = RTOSDemo_programclean + +CORE_STATE_DEVELOPMENT_FILES = + +WRAPPER_NGC_FILES = implementation/microblaze_0_wrapper.ngc \ +implementation/mb_opb_wrapper.ngc \ +implementation/debug_module_wrapper.ngc \ +implementation/ilmb_wrapper.ngc \ +implementation/dlmb_wrapper.ngc \ +implementation/dlmb_cntlr_wrapper.ngc \ +implementation/ilmb_cntlr_wrapper.ngc \ +implementation/lmb_bram_wrapper.ngc \ +implementation/rs232_uart_wrapper.ngc \ +implementation/leds_4bit_wrapper.ngc \ +implementation/leds_positions_wrapper.ngc \ +implementation/opb_timer_1_wrapper.ngc \ +implementation/opb_intc_0_wrapper.ngc \ +implementation/dcm_0_wrapper.ngc + +POSTSYN_NETLIST = implementation/$(SYSTEM).ngc + +SYSTEM_BIT = implementation/$(SYSTEM).bit + +DOWNLOAD_BIT = implementation/download.bit + +SYSTEM_ACE = implementation/$(SYSTEM).ace + +UCF_FILE = data/system.ucf + +BMM_FILE = implementation/$(SYSTEM).bmm + +FASTRUNTIME_OPT_FILE = etc/fast_runtime.opt +BITGEN_UT_FILE = etc/bitgen.ut + +################################################################# +# SOFTWARE APPLICATION RTOSDEMO +################################################################# + +RTOSDEMO_SOURCES = main.c ParTest/ParTest.c ../../Source/tasks.c ../../Source/queue.c ../../Source/list.c ../../Source/portable/MemMang/heap_1.c ../../Source/portable/GCC/MicroBlaze/port.c ../../Source/portable/GCC/MicroBlaze/portasm.s ../Common/Minimal/flash.c serial/serial.c ../Common/Minimal/comtest.c ../Common/Minimal/integer.c ../Common/Minimal/semtest.c ../Common/Minimal/dynamic.c ../Common/Minimal/PollQ.c ../Common/Minimal/BlockQ.c + +RTOSDEMO_HEADERS = FreeRTOSConfig.h + +RTOSDEMO_CC = mb-gcc +RTOSDEMO_CC_SIZE = mb-size +RTOSDEMO_CC_OPT = -Os +RTOSDEMO_CFLAGS = -D MICROBLAZE_GCC -Wall +RTOSDEMO_CC_SEARCH = # -B +RTOSDEMO_LIBPATH = -L./microblaze_0/lib/ # -L +RTOSDEMO_INCLUDES = -I./microblaze_0/include/ -IDev/FreeRTOS/Demo/MicroBlaze/ -I. -I../Common/include -I../../Source/include -I../../Source/portable/GCC/MicroBlaze +RTOSDEMO_LFLAGS = # -l +RTOSDEMO_CC_PREPROC_FLAG = # -Wp, +RTOSDEMO_CC_ASM_FLAG = # -Wa, +RTOSDEMO_CC_LINKER_FLAG = -Wl,-Map=rtosdemo.map +RTOSDEMO_LINKER_SCRIPT = +RTOSDEMO_LINKER_SCRIPT_FLAG = #-Wl,-T -Wl,$(RTOSDEMO_LINKER_SCRIPT) +RTOSDEMO_CC_DEBUG_FLAG = -g +RTOSDEMO_CC_GLOBPTR_FLAG= # -mxl-gp-opt +RTOSDEMO_MODE = executable +RTOSDEMO_LIBG_OPT = -$(RTOSDEMO_MODE) microblaze_0 +RTOSDEMO_CC_SOFTMUL_FLAG= -mno-xl-soft-mul +RTOSDEMO_CC_START_ADDR_FLAG= # -Wl,-defsym -Wl,_TEXT_START_ADDR= +RTOSDEMO_CC_STACK_SIZE_FLAG= # -Wl,-defsym -Wl,_STACK_SIZE= +RTOSDEMO_OTHER_CC_FLAGS= $(RTOSDEMO_CC_GLOBPTR_FLAG) \ + $(RTOSDEMO_CC_START_ADDR_FLAG) $(RTOSDEMO_CC_STACK_SIZE_FLAG) \ + $(RTOSDEMO_CC_SOFTMUL_FLAG) \ + $(RTOSDEMO_CC_PREPROC_FLAG) $(RTOSDEMO_CC_ASM_FLAG) $(RTOSDEMO_CC_LINKER_FLAG) \ + $(RTOSDEMO_LINKER_SCRIPT_FLAG) $(RTOSDEMO_CC_DEBUG_FLAG) diff --git a/20080212/Demo/PC/FRConfig.h b/20080212/Demo/PC/FRConfig.h new file mode 100644 index 000000000..81dc04f3b --- /dev/null +++ b/20080212/Demo/PC/FRConfig.h @@ -0,0 +1,94 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include + +/*----------------------------------------------------------- + * Application specific definitions for the x86 port. + *----------------------------------------------------------*/ + +/* These are the only definitions that can be modified!. */ +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 1 +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 128 ) /* This can be made smaller if required. */ +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 32 * 1024 ) ) +#define configMAX_TASK_NAME_LEN ( 16 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 1 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_CO_ROUTINES 1 + +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 10 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + + +/* The maximum number of characters a task name can take, +including the null terminator. */ +#define configMAX_TASK_NAME_LEN ( 16 ) + +/* Set the following definitions to 1 to include the component, or zero +to exclude the component. */ + +/* Include/exclude the stated API function. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + +/* + * The tick count (and times defined in tick count units) can be either a 16bit + * or a 32 bit value. See documentation on http://www.FreeRTOS.org to decide + * which to use. + */ +#define configUSE_16_BIT_TICKS 1 + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/PC/FileIO/fileIO.c b/20080212/Demo/PC/FileIO/fileIO.c new file mode 100644 index 000000000..b6ccd010b --- /dev/null +++ b/20080212/Demo/PC/FileIO/fileIO.c @@ -0,0 +1,98 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#include +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo program include files. */ +#include "fileio.h" + +void vDisplayMessage( const portCHAR * const pcMessageToPrint ) +{ + taskENTER_CRITICAL(); + printf( "%s", pcMessageToPrint ); + fflush( stdout ); + taskEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +void vWriteMessageToDisk( const portCHAR * const pcMessage ) +{ +const portCHAR * const pcFileName = "a:\\RTOSlog.txt"; +const portCHAR * const pcSeparator = "\r\n-----------------------\r\n"; +FILE *pf; + + taskENTER_CRITICAL(); + { + pf = fopen( pcFileName, "a" ); + if( pf != NULL ) + { + fwrite( pcMessage, strlen( pcMessage ), ( unsigned portSHORT ) 1, pf ); + fwrite( pcSeparator, strlen( pcSeparator ), ( unsigned portSHORT ) 1, pf ); + fclose( pf ); + } + } + taskEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +void vWriteBufferToDisk( const portCHAR * const pcBuffer, unsigned portLONG ulBufferLength ) +{ +const portCHAR * const pcFileName = "a:\\trace.bin"; +FILE *pf; + + taskENTER_CRITICAL(); + { + pf = fopen( pcFileName, "wb" ); + if( pf ) + { + fwrite( pcBuffer, ( size_t ) ulBufferLength, ( unsigned portSHORT ) 1, pf ); + fclose( pf ); + } + } + taskEXIT_CRITICAL(); +} + diff --git a/20080212/Demo/PC/FreeRTOSConfig.h b/20080212/Demo/PC/FreeRTOSConfig.h new file mode 100644 index 000000000..717f29dcd --- /dev/null +++ b/20080212/Demo/PC/FreeRTOSConfig.h @@ -0,0 +1,91 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include +#include + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 1 +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 256 ) /* This can be made smaller if required. */ +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 32 * 1024 ) ) +#define configMAX_TASK_NAME_LEN ( 16 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 1 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_CO_ROUTINES 1 +#define configUSE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_ALTERNATIVE_API 1 +#define configUSE_RECURSIVE_MUTEXES 1 + +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 10 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/PC/ParTest/ParTest.c b/20080212/Demo/PC/ParTest/ParTest.c new file mode 100644 index 000000000..f09a930b1 --- /dev/null +++ b/20080212/Demo/PC/ParTest/ParTest.c @@ -0,0 +1,131 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V1.01: + + + Types used updated. + + Add vParTestToggleLED(); + + +Changes from V2.0.0 + + + Use scheduler suspends in place of critical sections. +*/ + +#include "FreeRTOS.h" +#include "partest.h" +#include "task.h" + +#define partstALL_OUTPUTS_OFF ( ( unsigned portCHAR ) 0x00 ) +#define partstMAX_OUTPUT_LED ( ( unsigned portCHAR ) 7 ) + +/*lint -e956 File scope parameters okay here. */ +static unsigned portSHORT usPortAddress = partstDEFAULT_PORT_ADDRESS; +static volatile unsigned portCHAR ucCurrentOutputValue = partstALL_OUTPUTS_OFF; +/*lint +e956 */ + + +/*----------------------------------------------------------- + * Simple parallel port IO routines + *-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ + ucCurrentOutputValue = partstALL_OUTPUTS_OFF; + + portOUTPUT_BYTE( usPortAddress, ( unsigned ) partstALL_OUTPUTS_OFF ); +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, portBASE_TYPE xValue ) +{ +unsigned portCHAR ucBit = ( unsigned portCHAR ) 1; + + if( uxLED <= partstMAX_OUTPUT_LED ) + { + ucBit <<= uxLED; + } + + vTaskSuspendAll(); + { + if( xValue == pdTRUE ) + { + ucBit ^= ( unsigned portCHAR ) 0xff; + ucCurrentOutputValue &= ucBit; + } + else + { + ucCurrentOutputValue |= ucBit; + } + + portOUTPUT_BYTE( usPortAddress, ( unsigned ) ucCurrentOutputValue ); + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned portCHAR ucBit; + + if( uxLED <= partstMAX_OUTPUT_LED ) + { + ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED; + + vTaskSuspendAll(); + { + if( ucCurrentOutputValue & ucBit ) + { + ucCurrentOutputValue &= ~ucBit; + } + else + { + ucCurrentOutputValue |= ucBit; + } + + portOUTPUT_BYTE( usPortAddress, ( unsigned ) ucCurrentOutputValue ); + } + xTaskResumeAll(); + } +} + diff --git a/20080212/Demo/PC/RTOSDEMO.IDE b/20080212/Demo/PC/RTOSDEMO.IDE new file mode 100644 index 0000000000000000000000000000000000000000..18c17b6166ef37dcf415ebfb566826bc5162fa5c GIT binary patch literal 44966 zcmd_TdwiGGohN?s&Fz~Dxe*{h0$)N15kd$ME&>Xup3n8%&vVXs&bMZ0WT11fCsMm~X{2Rj=s<7xSfrtUpf}yjF(LDm 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Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/** + * Creates all the demo application tasks and co-routines, then starts the + * scheduler. + * + * Main. c also creates a task called "Print". This only executes every + * five seconds but has the highest priority so is guaranteed to get + * processor time. Its main function is to check that all the other tasks + * are still operational. Nearly all the tasks in the demo application + * maintain a unique count that is incremented each time the task successfully + * completes its function. Should any error occur within the task the count is + * permanently halted. The print task checks the count of each task to ensure + * it has changed since the last time the print task executed. If any count is + * found not to have changed the print task displays an appropriate message. + * If all the tasks are still incrementing their unique counts the print task + * displays an "OK" message. + * + * The LED flash tasks do not maintain a count as they already provide visual + * feedback of their status. + * + * The print task blocks on the queue into which messages that require + * displaying are posted. It will therefore only block for the full 5 seconds + * if no messages are posted onto the queue. + * + * Main. c also provides a demonstration of how the trace visualisation utility + * can be used, and how the scheduler can be stopped. + * + * \page MainC main.c + * \ingroup DemoFiles + *
+ */ + +#include +#include +#include "FreeRTOS.h" +#include "task.h" +#include "croutine.h" +#include "partest.h" +#include "serial.h" + +/* Demo file headers. */ +#include "BlockQ.h" +#include "PollQ.h" +#include "death.h" +#include "crflash.h" +#include "flop.h" +#include "print.h" +#include "comtest.h" +#include "fileio.h" +#include "semtest.h" +#include "integer.h" +#include "dynamic.h" +#include "mevents.h" +#include "crhook.h" +#include "blocktim.h" +#include "AltBlock.h" +#include "GenQTest.h" +#include "QPeek.h" +#include "countsem.h" +#include "AltQTest.h" +#include "AltPollQ.h" +#include "AltBlckQ.h" +#include "RecMutex.h" + +/* Priority definitions for the tasks in the demo application. */ +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainPRINT_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_BLOCK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainSEMAPHORE_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainGENERIC_QUEUE_PRIORITY ( tskIDLE_PRIORITY ) + +#define mainPRINT_STACK_SIZE ( ( unsigned portSHORT ) 512 ) +#define mainDEBUG_LOG_BUFFER_SIZE ( ( unsigned portSHORT ) 20480 ) + +/* The number of flash co-routines to create. */ +#define mainNUM_FLASH_CO_ROUTINES ( 8 ) + +/* Task function for the "Print" task as described at the top of the file. */ +static void vErrorChecks( void *pvParameters ); + +/* Function that checks the unique count of all the other tasks as described at +the top of the file. */ +static void prvCheckOtherTasksAreStillRunning( void ); + +/* Key presses can be used to start/stop the trace visualisation utility or stop +the scheduler. */ +static void prvCheckForKeyPresses( void ); + +/* Buffer used by the trace visualisation utility so only needed if the trace +being used. */ +#if configUSE_TRACE_FACILITY == 1 + static portCHAR pcWriteBuffer[ mainDEBUG_LOG_BUFFER_SIZE ]; +#endif + +/* Constant definition used to turn on/off the pre-emptive scheduler. */ +static const portSHORT sUsingPreemption = configUSE_PREEMPTION; + +/* Start the math tasks appropriate to the build. The Borland port does +not yet support floating point so uses the integer equivalent. */ +static void prvStartMathTasks( void ); + +/* Check which ever tasks are relevant to this build. */ +static portBASE_TYPE prvCheckMathTasksAreStillRunning( void ); + +/*-----------------------------------------------------------*/ + +portSHORT main( void ) +{ + /* Initialise hardware and utilities. */ + vParTestInitialise(); + vPrintInitialise(); + + /* CREATE ALL THE DEMO APPLICATION TASKS. */ + prvStartMathTasks(); + vStartComTestTasks( mainCOM_TEST_PRIORITY, serCOM1, ser115200 ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartBlockingQueueTasks( mainQUEUE_BLOCK_PRIORITY ); + vCreateBlockTimeTasks(); + vStartGenericQueueTasks( mainGENERIC_QUEUE_PRIORITY ); + vStartSemaphoreTasks( mainSEMAPHORE_TASK_PRIORITY ); + vStartDynamicPriorityTasks(); + vStartMultiEventTasks(); + vStartQueuePeekTasks(); + vStartCountingSemaphoreTasks(); + vStartAltGenericQueueTasks( mainGENERIC_QUEUE_PRIORITY ); + vCreateAltBlockTimeTasks(); + vStartAltBlockingQueueTasks( mainQUEUE_BLOCK_PRIORITY ); + vStartAltPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartRecursiveMutexTasks(); + + /* Create the "Print" task as described at the top of the file. */ + xTaskCreate( vErrorChecks, "Print", mainPRINT_STACK_SIZE, NULL, mainPRINT_TASK_PRIORITY, NULL ); + + /* This task has to be created last as it keeps account of the number of tasks + it expects to see running. */ + vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); + + /* Create the co-routines that flash the LED's. */ + vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES ); + + /* Create the co-routines that communicate with the tick hook. */ + vStartHookCoRoutines(); + + /* Set the scheduler running. This function will not return unless a task + calls vTaskEndScheduler(). */ + vTaskStartScheduler(); + + return 1; +} +/*-----------------------------------------------------------*/ + +static void vErrorChecks( void *pvParameters ) +{ +portTickType xExpectedWakeTime; +const portTickType xPrintRate = ( portTickType ) 5000 / portTICK_RATE_MS; +const portLONG lMaxAllowableTimeDifference = ( portLONG ) 0; +portTickType xWakeTime; +portLONG lTimeDifference; +const portCHAR *pcReceivedMessage; +const portCHAR * const pcTaskBlockedTooLongMsg = "Print task blocked too long!\r\n"; + + ( void ) pvParameters; + + /* Loop continuously, blocking, then checking all the other tasks are still + running, before blocking once again. This task blocks on the queue of + messages that require displaying so will wake either by its time out expiring, + or a message becoming available. */ + for( ;; ) + { + /* Calculate the time we will unblock if no messages are received + on the queue. This is used to check that we have not blocked for too long. */ + xExpectedWakeTime = xTaskGetTickCount(); + xExpectedWakeTime += xPrintRate; + + /* Block waiting for either a time out or a message to be posted that + required displaying. */ + pcReceivedMessage = pcPrintGetNextMessage( xPrintRate ); + + /* Was a message received? */ + if( pcReceivedMessage == NULL ) + { + /* A message was not received so we timed out, did we unblock at the + expected time? */ + xWakeTime = xTaskGetTickCount(); + + /* Calculate the difference between the time we unblocked and the + time we should have unblocked. */ + if( xWakeTime > xExpectedWakeTime ) + { + lTimeDifference = ( portLONG ) ( xWakeTime - xExpectedWakeTime ); + } + else + { + lTimeDifference = ( portLONG ) ( xExpectedWakeTime - xWakeTime ); + } + + if( lTimeDifference > lMaxAllowableTimeDifference ) + { + /* We blocked too long - create a message that will get + printed out the next time around. If we are not using + preemption then we won't expect the timing to be so + accurate. */ + if( sUsingPreemption == pdTRUE ) + { + vPrintDisplayMessage( &pcTaskBlockedTooLongMsg ); + } + } + + /* Check the other tasks are still running, just in case. */ + prvCheckOtherTasksAreStillRunning(); + } + else + { + /* We unblocked due to a message becoming available. Send the message + for printing. */ + vDisplayMessage( pcReceivedMessage ); + } + + /* Key presses are used to invoke the trace visualisation utility, or end + the program. */ + prvCheckForKeyPresses(); + } +} +/*-----------------------------------------------------------*/ + +static void prvCheckForKeyPresses( void ) +{ +portSHORT sIn; + + taskENTER_CRITICAL(); + #ifdef DEBUG_BUILD + /* kbhit can be used in .exe's that are executed from the command + line, but not if executed through the debugger. */ + sIn = 0; + #else + sIn = kbhit(); + #endif + taskEXIT_CRITICAL(); + + if( sIn ) + { + /* Key presses can be used to start/stop the trace utility, or end the + program. */ + sIn = getch(); + switch( sIn ) + { + /* Only define keys for turning on and off the trace if the trace + is being used. */ + #if configUSE_TRACE_FACILITY == 1 + case 't' : vTaskList( pcWriteBuffer ); + vWriteMessageToDisk( pcWriteBuffer ); + break; + case 's' : vTaskStartTrace( pcWriteBuffer, mainDEBUG_LOG_BUFFER_SIZE ); + break; + + case 'e' : { + unsigned portLONG ulBufferLength; + ulBufferLength = ulTaskEndTrace(); + vWriteBufferToDisk( pcWriteBuffer, ulBufferLength ); + } + break; + #endif + + default : vTaskEndScheduler(); + break; + } + } +} +/*-----------------------------------------------------------*/ + +static void prvCheckOtherTasksAreStillRunning( void ) +{ +static portSHORT sErrorHasOccurred = pdFALSE; + + if( prvCheckMathTasksAreStillRunning() != pdTRUE ) + { + vDisplayMessage( "Maths task count unchanged!\r\n" ); + sErrorHasOccurred = pdTRUE; + } + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + vDisplayMessage( "Com test count unchanged!\r\n" ); + sErrorHasOccurred = pdTRUE; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + vDisplayMessage( "Blocking queues count unchanged!\r\n" ); + sErrorHasOccurred = pdTRUE; + } + + if( xAreAltBlockingQueuesStillRunning() != pdTRUE ) + { + vDisplayMessage( "Alt blocking queues count unchanged!\r\n" ); + sErrorHasOccurred = pdTRUE; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + vDisplayMessage( "Polling queue count unchanged!\r\n" ); + sErrorHasOccurred = pdTRUE; + } + + if( xAreAltPollingQueuesStillRunning() != pdTRUE ) + { + vDisplayMessage( "Alt polling queue count unchanged!\r\n" ); + sErrorHasOccurred = pdTRUE; + } + + if( xIsCreateTaskStillRunning() != pdTRUE ) + { + vDisplayMessage( "Incorrect number of tasks running!\r\n" ); + sErrorHasOccurred = pdTRUE; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + vDisplayMessage( "Semaphore take count unchanged!\r\n" ); + sErrorHasOccurred = pdTRUE; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + vDisplayMessage( "Dynamic priority count unchanged!\r\n" ); + sErrorHasOccurred = pdTRUE; + } + + if( xAreMultiEventTasksStillRunning() != pdTRUE ) + { + vDisplayMessage( "Error in multi events tasks!\r\n" ); + sErrorHasOccurred = pdTRUE; + } + + if( xAreFlashCoRoutinesStillRunning() != pdTRUE ) + { + vDisplayMessage( "Error in co-routine flash tasks!\r\n" ); + sErrorHasOccurred = pdTRUE; + } + + if( xAreHookCoRoutinesStillRunning() != pdTRUE ) + { + vDisplayMessage( "Error in tick hook to co-routine communications!\r\n" ); + sErrorHasOccurred = pdTRUE; + } + + if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + vDisplayMessage( "Error in block time test tasks!\r\n" ); + sErrorHasOccurred = pdTRUE; + } + + if( xAreAltBlockTimeTestTasksStillRunning() != pdTRUE ) + { + vDisplayMessage( "Error in fast block time test tasks!\r\n" ); + sErrorHasOccurred = pdTRUE; + } + + if( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + vDisplayMessage( "Error in generic queue test task!\r\n" ); + sErrorHasOccurred = pdTRUE; + } + + if( xAreAltGenericQueueTasksStillRunning() != pdTRUE ) + { + vDisplayMessage( "Error in fast generic queue test task!\r\n" ); + sErrorHasOccurred = pdTRUE; + } + + if( xAreQueuePeekTasksStillRunning() != pdTRUE ) + { + vDisplayMessage( "Error in queue peek test task!\r\n" ); + sErrorHasOccurred = pdTRUE; + } + + if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE ) + { + vDisplayMessage( "Error in counting semaphore demo task!\r\n" ); + sErrorHasOccurred = pdTRUE; + } + + if( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + { + vDisplayMessage( "Error in recursive mutex tasks!\r\n" ); + sErrorHasOccurred = pdTRUE; + } + + if( sErrorHasOccurred == pdFALSE ) + { + vDisplayMessage( "OK " ); + } +} +/*-----------------------------------------------------------*/ + +static void prvStartMathTasks( void ) +{ + #ifdef BCC_INDUSTRIAL_PC_PORT + /* The Borland project does not yet support floating point. */ + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + #else + vStartMathTasks( tskIDLE_PRIORITY ); + #endif +} +/*-----------------------------------------------------------*/ + +static portBASE_TYPE prvCheckMathTasksAreStillRunning( void ) +{ + #ifdef BCC_INDUSTRIAL_PC_PORT + /* The Borland project does not yet support floating point. */ + return xAreIntegerMathsTaskStillRunning(); + #else + return xAreMathsTaskStillRunning(); + #endif +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ + /* The co-routines are executed in the idle task using the idle task + hook. */ + vCoRoutineSchedule(); +} +/*-----------------------------------------------------------*/ + diff --git a/20080212/Demo/PC/rtosdemo.DSW b/20080212/Demo/PC/rtosdemo.DSW new file mode 100644 index 0000000000000000000000000000000000000000..3b8e4254c9d0c743abd01a40fcf416db1066e1af GIT binary patch literal 3390 zcmeHJOK%%h6h7ClO!FufY6Gncxm1mU(rOwzkG9FmnT)ALQb)Fd&4^|^bCbDb9+qcp zl67}<1v`ENhz064Kr2=(P=5d{E7}FH0M_N)>rRzvMS&WtNbQk*&wS^e=jS^!ZgxAZ zfNE3={D|#Ew8C9RPXd{E`4w^!VC%R2S0@1qMk^fvoGyvLf{+Wnt(^C|K{AO#aRZ@pP-tmzvywYsLm=dg&>Dlqea zwAaDj_f3ymNK!lKL{{Jlz8q$@ug>EI>oGqH@#16n9`j}3TMRToRSo=vLAPTuL&TXa zml-X~GKxzr9@#-?U?wl{R}!9hZrrZTgt5PE#1?BAqZbxqJoEx9DtrRRBuC>oQC!~T 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+7 +VComponent +8 +WRect +0 +0 +7168 +8192 +0 +0 +9 +WFileName +12 +rtosdemo.tgt +6 +63 +7 diff --git a/20080212/Demo/PC/serial/serial.c b/20080212/Demo/PC/serial/serial.c new file mode 100644 index 000000000..7ee8de9a1 --- /dev/null +++ b/20080212/Demo/PC/serial/serial.c @@ -0,0 +1,691 @@ +/* + This serial port driver is borrowed heavily from DZComm. I have + simplified it by removing a lot of the functionality (hardware + flow control, etc.). For more details and the full version see + http://dzcomm.sourceforge.net + + + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V1.00: + + + Call to the more efficient portSWITCH_CONTEXT() replaces the call to + taskYIELD() in the ISR. + +Changes from V1.2.0: + + + Added vSerialPutString(). + +Changes from V1.2.3 + + + The function xPortInitMinimal() has been renamed to + xSerialPortInitMinimal() and the function xPortInit() has been renamed + to xSerialPortInit(). + +Changes From V2.0.0 + + + Use portTickType in place of unsigned pdLONG for delay periods. + + cQueueReieveFromISR() used in place of xQueueReceive() in ISR. +*/ + + +#include +#include +#include "FreeRTOS.h" +#include "queue.h" +#include "task.h" +#include "semphr.h" +#include "portasm.h" + +#define serMAX_IRQs ( 16 ) +#define serTRANSMIT_HOLD_EMPTY_INT ( 0x02 ) +#define serCOM1_STANDARD_IRQ ( ( unsigned portCHAR ) 4 ) +#define serCOM2_STANDARD_IRQ ( ( unsigned portCHAR ) 3 ) + + +#define serIMR_8259_0 ( ( unsigned portCHAR ) 0x21 ) +#define serIMR_8259_1 ( ( unsigned portCHAR ) 0xa1 ) +#define serISR_8259_0 ( ( unsigned portCHAR ) 0x20 ) +#define serISR_8259_1 ( ( unsigned portCHAR ) 0xa0 ) +#define serALL_COMS_INTERRUPTS ( ( unsigned portCHAR ) 0x0f ) +#define serALL_MODEM_CTRL_INTERRUPTS ( ( unsigned portCHAR ) 0x0f ) + +#define serTRANSMIT_HOLD_OFFSET ( 0 ) +#define serRECEIVE_DATA_OFFSET ( 0 ) +#define serBAUD_RATE_DIVISOR_LOW_OFFSET ( 0 ) +#define serBAUD_RATE_DIVISOR_HIGH_OFFSET ( 1 ) +#define serINTERRUPT_ENABLE_OFFSET ( 1 ) +#define serINTERRUPT_ID_OFFSET ( 2 ) +#define serFIFO_CTRL_OFFSET ( 2 ) +#define serLINE_CTRL_OFFSET ( 3 ) +#define serMODEM_CTRL_OFFSET ( 4 ) +#define serLINE_STATUS_OFFSET ( 5 ) +#define serMODEM_STATUS_OFFSET ( 6 ) +#define serSCR_OFFSET ( 7 ) + +#define serMAX_BAUD ( ( unsigned portLONG ) 115200UL ) + +#define serNO_INTERRUPTS ( 0x00 ) + +#define vInterruptOn( pxPort, ucInterrupt ) \ +{ \ + unsigned portCHAR ucIn = portINPUT_BYTE( pxPort->usInterruptEnableReg ); \ + if( !( ucIn & ucInterrupt ) ) \ + { \ + portOUTPUT_BYTE( pxPort->usInterruptEnableReg, ucIn | ucInterrupt ); \ + } \ +} +/*-----------------------------------------------------------*/ + +#define vInterruptOff( pxPort, ucInterrupt ) \ +{ \ + unsigned portCHAR ucIn = portINPUT_BYTE( pxPort->usInterruptEnableReg ); \ + if( ucIn & ucInterrupt ) \ + { \ + portOUTPUT_BYTE( pxPort->usInterruptEnableReg, ucIn & ~ucInterrupt); \ + } \ +} +/*-----------------------------------------------------------*/ + +typedef enum +{ + serCOM1, + serCOM2, + serCOM3, + serCOM4, + serCOM5, + serCOM6, + serCOM7, + serCOM8 +} eCOMPort; + +typedef enum +{ + serNO_PARITY, + serODD_PARITY, + serEVEN_PARITY, + serMARK_PARITY, + serSPACE_PARITY +} eParity; + +typedef enum +{ + serSTOP_1, + serSTOP_2 +} eStopBits; + +typedef enum +{ + serBITS_5, + serBITS_6, + serBITS_7, + serBITS_8 +} eDataBits; + +typedef enum +{ + ser50, + ser75, + ser110, + ser134, + ser150, + ser200, + ser300, + ser600, + ser1200, + ser1800, + ser2400, + ser4800, + ser9600, + ser19200, + ser38400, + ser57600, + ser115200 +} eBaud; + +/* This *MUST* match the order in the eBaud definition. */ +unsigned portLONG ulBaudFromEnum[] = +{ + ( unsigned portLONG ) 50, + ( unsigned portLONG ) 75, + ( unsigned portLONG ) 110, + ( unsigned portLONG ) 134, + ( unsigned portLONG ) 150, + ( unsigned portLONG ) 200, + ( unsigned portLONG ) 300, + ( unsigned portLONG ) 600, + ( unsigned portLONG ) 1200, + ( unsigned portLONG ) 1800, + ( unsigned portLONG ) 2400, + ( unsigned portLONG ) 4800, + ( unsigned portLONG ) 9600, + ( unsigned portLONG ) 19200, + ( unsigned portLONG ) 38400UL, + ( unsigned portLONG ) 57600UL, + ( unsigned portLONG ) 115200UL +}; + +typedef struct xCOM_PORT +{ + unsigned portSHORT sPort; /* comm port address eg. 0x3f8 */ + unsigned portCHAR ucIRQ; /* comm IRQ eg. 3 */ + + /* Next two fields used for setting up the IRQ routine and + * (un)masking the interrupt in certain circumstances. + */ + unsigned portSHORT usIRQVector; + unsigned portCHAR ucInterruptEnableMast; + + /* Read/Write buffers. */ + xQueueHandle xRxedChars; + xQueueHandle xCharsForTx; + + /* This lot are set up to minimise CPU time where accessing the comm + * port's registers. + */ + unsigned portSHORT usTransmitHoldReg; + unsigned portSHORT usReceiveDataRegister; + unsigned portSHORT usBaudRateDivisorLow; + unsigned portSHORT usBaudRateDivisorHigh; + unsigned portSHORT usInterruptEnableReg; + unsigned portSHORT usInterruptIDReg; + unsigned portSHORT usFIFOCtrlReg; + unsigned portSHORT usLineCtrlReg; + unsigned portSHORT usModemCtrlReg; + unsigned portSHORT usLineStatusReg; + unsigned portSHORT usModemStatusReg; + unsigned portSHORT usSCRReg; + unsigned portSHORT us8259InterruptServiceReg; + unsigned portSHORT us8259InterruptMaskReg; + + /* This semaphore does nothing useful except test a feature of the + scheduler. */ + xSemaphoreHandle xTestSem; + +} xComPort; + +typedef xComPort *xComPortHandle; + +/* A xComPort structure can be associated with each IRQ. Initially none +are create/installed. */ +xComPort *xPortStatus[ serMAX_IRQs ] = { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL }; + +/*-----------------------------------------------------------*/ + +/* These prototypes are repeated here so we don't have to include the serial header. This allows +the xComPortHandle structure details to be private to this file. */ +xComPortHandle xSerialPortInit( eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits, unsigned portBASE_TYPE uxBufferLength ); +portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, portCHAR *pcRxedChar, portTickType xBlockTime ); +portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, portCHAR cOutChar, portTickType xBlockTime ); +portBASE_TYPE xSerialWaitForSemaphore( xComPortHandle xPort ); + +static void prvSetupPortHardware( xComPort *pxPort, eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits ); +static portSHORT sComPortISR( const xComPort * const pxPort ); + +/*-----------------------------------------------------------*/ + +/* Define an interrupt handler for each slot in the xPortStatus array. */ + +#define COM_IRQ_WRAPPER(N) \ + static void __interrupt COM_IRQ##N##_WRAPPER( void ) \ + { \ + portDISABLE_INTERRUPTS(); \ + if( sComPortISR( xPortStatus[##N##] ) ) \ + { \ + portSWITCH_CONTEXT(); \ + } \ + } + +COM_IRQ_WRAPPER( 0 ) +COM_IRQ_WRAPPER( 1 ) +COM_IRQ_WRAPPER( 2 ) +COM_IRQ_WRAPPER( 3 ) +COM_IRQ_WRAPPER( 4 ) +COM_IRQ_WRAPPER( 5 ) +COM_IRQ_WRAPPER( 6 ) +COM_IRQ_WRAPPER( 7 ) +COM_IRQ_WRAPPER( 8 ) +COM_IRQ_WRAPPER( 9 ) +COM_IRQ_WRAPPER( 10 ) +COM_IRQ_WRAPPER( 11 ) +COM_IRQ_WRAPPER( 12 ) +COM_IRQ_WRAPPER( 13 ) +COM_IRQ_WRAPPER( 14 ) +COM_IRQ_WRAPPER( 15 ) + +static pxISR xISRs[ serMAX_IRQs ] = +{ + COM_IRQ0_WRAPPER, + COM_IRQ1_WRAPPER, + COM_IRQ2_WRAPPER, + COM_IRQ3_WRAPPER, + COM_IRQ4_WRAPPER, + COM_IRQ5_WRAPPER, + COM_IRQ6_WRAPPER, + COM_IRQ7_WRAPPER, + COM_IRQ8_WRAPPER, + COM_IRQ9_WRAPPER, + COM_IRQ10_WRAPPER, + COM_IRQ11_WRAPPER, + COM_IRQ12_WRAPPER, + COM_IRQ13_WRAPPER, + COM_IRQ14_WRAPPER, + COM_IRQ15_WRAPPER +}; + +static pxISR xOldISRs[ serMAX_IRQs ] = { NULL }; + +/*-----------------------------------------------------------*/ + + +xComPortHandle xSerialPortInit( eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits, unsigned portBASE_TYPE uxBufferLength ) +{ +xComPort *pxPort; + + /* Create a structure to handle this port. */ + pxPort = ( xComPort * ) pvPortMalloc( sizeof( xComPort ) ); + + if( pxPort != NULL ) + { + /* Create the queues used by the comtest task. */ + pxPort->xRxedChars = xQueueCreate( uxBufferLength, ( unsigned portBASE_TYPE ) sizeof( portCHAR ) ); + pxPort->xCharsForTx = xQueueCreate( uxBufferLength, ( unsigned portBASE_TYPE ) sizeof( portCHAR ) ); + + /* Create the test semaphore. This does nothing useful except test a feature of the scheduler. */ + vSemaphoreCreateBinary( pxPort->xTestSem ); + + prvSetupPortHardware( pxPort, ePort, eWantedBaud, eWantedParity, eWantedDataBits, eWantedStopBits ); + + return pxPort; + } + + return NULL; +} +/*-----------------------------------------------------------*/ + +static void prvSetupPortHardware( xComPort *pxPort, eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits ) +{ +portSHORT sIn; +unsigned portLONG ulDivisor; +unsigned portCHAR ucDivisorLow; +unsigned portCHAR ucDivisorHigh; +unsigned portCHAR ucCommParam; + + /* IRQ numbers - standard */ + if( ( ePort == serCOM1 ) || ( ePort == serCOM3 ) || ( ePort == serCOM5 ) || ( ePort == serCOM7 ) ) + { + pxPort->ucIRQ = serCOM1_STANDARD_IRQ; + pxPort->sPort = 0x3f8; + } + else + { + pxPort->ucIRQ = serCOM2_STANDARD_IRQ; + pxPort->sPort = 0x2f8; + } + + /* Set up variables in port making it easy to see which sIn/o address is which */ + pxPort->usTransmitHoldReg = pxPort->sPort + serTRANSMIT_HOLD_OFFSET; + pxPort->usReceiveDataRegister = pxPort->sPort + serRECEIVE_DATA_OFFSET; + pxPort->usBaudRateDivisorLow = pxPort->sPort + serBAUD_RATE_DIVISOR_LOW_OFFSET; + pxPort->usBaudRateDivisorHigh = pxPort->sPort + serBAUD_RATE_DIVISOR_HIGH_OFFSET; + pxPort->usInterruptEnableReg = pxPort->sPort + serINTERRUPT_ENABLE_OFFSET; + pxPort->usInterruptIDReg = pxPort->sPort + serINTERRUPT_ID_OFFSET; + pxPort->usFIFOCtrlReg = pxPort->sPort + serFIFO_CTRL_OFFSET; + pxPort->usLineCtrlReg = pxPort->sPort + serLINE_CTRL_OFFSET; + pxPort->usModemCtrlReg = pxPort->sPort + serMODEM_CTRL_OFFSET; + pxPort->usLineStatusReg = pxPort->sPort + serLINE_STATUS_OFFSET; + pxPort->usModemStatusReg = pxPort->sPort + serMODEM_STATUS_OFFSET; + pxPort->usSCRReg = pxPort->sPort + serSCR_OFFSET; + + /* Set communication parameters. */ + ulDivisor = serMAX_BAUD / ulBaudFromEnum[ eWantedBaud ]; + ucDivisorLow = ( unsigned portCHAR ) ulDivisor & ( unsigned portCHAR ) 0xff; + ucDivisorHigh = ( unsigned portCHAR ) ( ( ( unsigned portSHORT ) ulDivisor >> 8 ) & 0xff ); + + switch( eWantedParity ) + { + case serNO_PARITY: ucCommParam = 0x00; + break; + case serODD_PARITY: ucCommParam = 0x08; + break; + case serEVEN_PARITY: ucCommParam = 0x18; + break; + case serMARK_PARITY: ucCommParam = 0x28; + break; + case serSPACE_PARITY: ucCommParam = 0x38; + break; + default: ucCommParam = 0x00; + break; + } + + switch ( eWantedDataBits ) + { + case serBITS_5: ucCommParam |= 0x00; + break; + case serBITS_6: ucCommParam |= 0x01; + break; + case serBITS_7: ucCommParam |= 0x02; + break; + case serBITS_8: ucCommParam |= 0x03; + break; + default: ucCommParam |= 0x03; + break; + } + + if( eWantedStopBits == serSTOP_2 ) + { + ucCommParam |= 0x04; + } + + /* Reset UART into known state - Thanks to Bradley Town */ + portOUTPUT_BYTE( pxPort->usLineCtrlReg, 0x00 ); /* Access usTransmitHoldReg/RBR/usInterruptEnableReg */ + portOUTPUT_BYTE( pxPort->usInterruptEnableReg, 0x00 ); /* Disable interrupts from UART */ + portOUTPUT_BYTE( pxPort->usModemCtrlReg, 0x04 ); /* Enable some multi-port cards */ + + /* Code based on stuff from SVAsync lib. Clear UART Status and data registers + setting up FIFO if possible */ + sIn = portINPUT_BYTE( pxPort->usSCRReg ); + portOUTPUT_BYTE( pxPort->usSCRReg, 0x55 ); + + if( portINPUT_BYTE( pxPort->usSCRReg ) == 0x55 ) + { + /* The chip is better than an 8250 */ + portOUTPUT_BYTE( pxPort->usSCRReg, sIn ); /* Set usSCRReg back to what it was before */ + portINPUT_BYTE( pxPort->usSCRReg); /* Give slow motherboards a chance */ + + /* Try and start the FIFO. It appears that some chips need a two call + protocol, but those that don't seem to work even if you do start it twice. + The first call is simply to start it, the second starts it and sets an 8 + byte FIFO trigger level. */ + portOUTPUT_BYTE( pxPort->usFIFOCtrlReg, 0x01 ); + portINPUT_BYTE( pxPort->usFIFOCtrlReg ); /* Give slow motherboards a chance to catch up */ + portOUTPUT_BYTE( pxPort->usFIFOCtrlReg, 0x87 ); + + /* Check that the FIFO initialised */ + if( ( portINPUT_BYTE( pxPort->usInterruptIDReg ) & 0xc0 ) != 0xc0 ) + { + /* It didn't so we assume it isn't there but disable it to be on the + safe side. */ + portOUTPUT_BYTE( pxPort->usInterruptIDReg, 0xfe ); + } + } + + /* End of (modified) SVAsync code. + Set interrupt parameters calculating mask for 8259 controller's + IMR and number of interrupt handler for given irq level */ + if (pxPort->ucIRQ <= 7) + { + /* if 0<=irq<=7 first IMR address used */ + pxPort->ucInterruptEnableMast = ~(0x01 << pxPort->ucIRQ); + pxPort->usIRQVector = pxPort->ucIRQ + 8; + pxPort->us8259InterruptMaskReg = serIMR_8259_0; + pxPort->us8259InterruptServiceReg = serISR_8259_0; + } + else + { + pxPort->ucInterruptEnableMast = ~( 0x01 << ( pxPort->ucIRQ % 8 ) ); + pxPort->usIRQVector = 0x70 + ( pxPort->ucIRQ - 8) ; + pxPort->us8259InterruptMaskReg = serIMR_8259_1; + pxPort->us8259InterruptServiceReg = serISR_8259_1; + } + + /* Set Port Toggle to usBaudRateDivisorLow/usBaudRateDivisorHigh registers + to set baud rate */ + portOUTPUT_BYTE( pxPort->usLineCtrlReg, ucCommParam | 0x80 ); + portOUTPUT_BYTE( pxPort->usBaudRateDivisorLow, ucDivisorLow ); + portOUTPUT_BYTE( pxPort->usBaudRateDivisorHigh, ucDivisorHigh ); + + /* reset usLineCtrlReg and Port Toggleout */ + portOUTPUT_BYTE( pxPort->usLineCtrlReg, ucCommParam & 0x7F ); + + portENTER_CRITICAL(); + + if( xPortStatus[ pxPort->ucIRQ ] == NULL ) + { + xPortStatus[ pxPort->ucIRQ ] = pxPort; + } + + xOldISRs[ pxPort->ucIRQ ] = _dos_getvect( pxPort->usIRQVector ); + _dos_setvect( pxPort->usIRQVector, xISRs[ pxPort->ucIRQ ] ); + + /* enable interrupt pxPort->ucIRQ level */ + portOUTPUT_BYTE( pxPort->us8259InterruptMaskReg, portINPUT_BYTE( pxPort->us8259InterruptMaskReg ) & pxPort->ucInterruptEnableMast ); + + /* And allow interrupts again now the hairy bit's done */ + portEXIT_CRITICAL(); + + /* This version does not allow flow control. */ + portOUTPUT_BYTE( pxPort->usModemCtrlReg, serALL_MODEM_CTRL_INTERRUPTS ); + + /* enable all communication's interrupts */ + portOUTPUT_BYTE( pxPort->usInterruptEnableReg, serALL_COMS_INTERRUPTS ); +} +/*-----------------------------------------------------------*/ + +static portSHORT sComPortISR( const xComPort * const pxPort ) +{ +portSHORT sInterruptID; +portCHAR cIn, cOut; +portBASE_TYPE xTaskWokenByPost = pdFALSE, xAnotherTaskWokenByPost = pdFALSE, xTaskWokenByTx = pdFALSE; +extern void vComTestUnsuspendTask( void ); + + portOUTPUT_BYTE( pxPort->us8259InterruptMaskReg, ( portINPUT_BYTE( pxPort->us8259InterruptMaskReg) | ~pxPort->ucInterruptEnableMast ) ); + + /* Decide which UART has issued the interrupt */ + sInterruptID = portINPUT_BYTE( pxPort->usInterruptIDReg ); + + /* service whatever requests the calling UART may have. The top 4 bits are + either unused or indicate the presence of a functioning FIFO, which we don't + need to know. So trim them off to simplify the switch statement below. */ + sInterruptID &= 0x0f; + do + { + switch( sInterruptID ) + { + case 0x0c: /* Timeout + Called when FIFO not up to trigger level but no activity for + a while. Handled exactly as RDAINT, see below for + description. */ + do + { + cIn = ( portCHAR ) portINPUT_BYTE( pxPort->usReceiveDataRegister ); + xTaskWokenByPost = xQueueSendFromISR( pxPort->xRxedChars, &cIn, xTaskWokenByPost ); + + /* Also release the semaphore - this does nothing interesting and is just a test. + We first attempt to unsuspend the task to check the scheduler correctely detects + this as an invalid call, then give the semaphore for real. */ + vComTestUnsuspendTask(); + xAnotherTaskWokenByPost = xSemaphoreGiveFromISR( pxPort->xTestSem, xAnotherTaskWokenByPost ); + + } while( portINPUT_BYTE( pxPort->usLineStatusReg ) & 0x01 ); + break; + + case 0x06: /* LSINT */ + portINPUT_BYTE( pxPort->usLineStatusReg ); + break; + + case 0x04: /* RDAINT */ + /* The usInterruptIDReg flag tested above stops when the + FIFO is below the trigger level rather than empty, whereas + this flag allows one to empty it: (do loop because there + must be at least one to read by virtue of having got here.) */ + do + { + cIn = ( portCHAR ) portINPUT_BYTE( pxPort->usReceiveDataRegister ); + xTaskWokenByPost = xQueueSendFromISR( pxPort->xRxedChars, &cIn, xTaskWokenByPost ); + + /* Also release the semaphore - this does nothing interesting and is just a test. + We first attempt to unsuspend the task to check the scheduler correctely detects + this as an invalid call, then give the semaphore for real. */ + vComTestUnsuspendTask(); + xAnotherTaskWokenByPost = xSemaphoreGiveFromISR( pxPort->xTestSem, xAnotherTaskWokenByPost ); + + } while( portINPUT_BYTE( pxPort->usLineStatusReg ) & 0x01 ); + break; + + case 0x02: /* serTRANSMIT_HOLD_EMPTY_INT */ + if( xQueueReceiveFromISR( pxPort->xCharsForTx, &cOut, &xTaskWokenByTx ) != pdTRUE ) + { + /* Queue empty, nothing to send */ + vInterruptOff( pxPort, serTRANSMIT_HOLD_EMPTY_INT); + } + else + { + portOUTPUT_BYTE( pxPort->usTransmitHoldReg, ( portSHORT ) cOut ); + } + break; + + case 0x00: /* MSINT */ + portINPUT_BYTE( pxPort->usModemStatusReg ); + break; + } + + /* Get the next instruction, trimming as above */ + sInterruptID = portINPUT_BYTE( pxPort->usInterruptIDReg ) & 0x0f; + + } while( !( sInterruptID & 0x01 ) ); + + if( pxPort->ucIRQ > 7 ) + { + portOUTPUT_BYTE( 0xA0, 0x60 + ( pxPort->ucIRQ & 0x07 ) ); + portOUTPUT_BYTE( 0x20, 0x62); + } + else + { + portOUTPUT_BYTE( 0x20, 0x60 + pxPort->ucIRQ ); + } + + portOUTPUT_BYTE( pxPort->us8259InterruptMaskReg, portINPUT_BYTE( pxPort->us8259InterruptMaskReg ) & pxPort->ucInterruptEnableMast ); + + /* If posting any of the characters to a queue woke a task that was blocked on + the queue we may want to return to the task just woken (depending on its + priority relative to the task this ISR interrupted. */ + if( xTaskWokenByPost || xAnotherTaskWokenByPost || xTaskWokenByTx ) + { + return pdTRUE; + } + else + { + return pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, portCHAR *pcRxedChar, portTickType xBlockTime ) +{ + /* Get the next character from the buffer, note that this routine is only + called having checked that the is (at least) one to get */ + if( xQueueReceive( pxPort->xRxedChars, pcRxedChar, xBlockTime ) ) + { + return pdTRUE; + } + else + { + return pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, portCHAR cOutChar, portTickType xBlockTime ) +{ + if( xQueueSend( pxPort->xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) + { + return pdFAIL; + } + + vInterruptOn( pxPort, serTRANSMIT_HOLD_EMPTY_INT ); + + return pdPASS; +} +/*-----------------------------------------------------------*/ + +void vSerialPutString( xComPortHandle pxPort, const portCHAR * const pcString, unsigned portSHORT usStringLength ) +{ +portCHAR * pcNextChar; +const portTickType xNoBlock = ( portTickType ) 0; + + /* Stop warnings. */ + ( void ) usStringLength; + + pcNextChar = ( portCHAR * ) pcString; + while( *pcNextChar ) + { + xSerialPutChar( pxPort, *pcNextChar, xNoBlock ); + pcNextChar++; + } +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xSerialWaitForSemaphore( xComPortHandle xPort ) +{ +const portTickType xBlockTime = ( portTickType ) 0xffff; + + /* This function does nothing interesting, but test the + semaphore from ISR mechanism. */ + return xSemaphoreTake( xPort->xTestSem, xBlockTime ); +} +/*-----------------------------------------------------------*/ + +void vSerialClose( xComPortHandle xPort ) +{ + portENTER_CRITICAL(); + + /* Turn off the interrupts. */ + portOUTPUT_BYTE( xPort->usModemCtrlReg, serNO_INTERRUPTS ); + portOUTPUT_BYTE( xPort->usInterruptEnableReg, serNO_INTERRUPTS ); + + /* Put back the original ISR. */ + _dos_setvect( xPort->usIRQVector, xOldISRs[ xPort->ucIRQ ] ); + + /* Remove the reference in the array of xComPort structures. */ + xPortStatus[ xPort->ucIRQ ] = NULL; + + /* Delete the queues. */ + vQueueDelete( xPort->xRxedChars ); + vQueueDelete( xPort->xCharsForTx ); + + vPortFree( ( void * ) xPort ); + + portEXIT_CRITICAL(); +} + diff --git a/20080212/Demo/PIC18_MPLAB/18f452.lkr b/20080212/Demo/PIC18_MPLAB/18f452.lkr new file mode 100644 index 000000000..3e844289c --- /dev/null +++ b/20080212/Demo/PIC18_MPLAB/18f452.lkr @@ -0,0 +1,24 @@ +// $Id: 18f452.lkr,v 1.4 2003/03/13 05:02:23 sealep Exp $ +// File: 18f452.lkr +// Sample linker script for the PIC18F452 processor + +LIBPATH . + +FILES c018i.o +FILES clib.lib +FILES p18f452.lib + +CODEPAGE NAME=vectors START=0x0 END=0x39 PROTECTED +CODEPAGE NAME=page START=0x3A END=0x7FFF +CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED +CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED +CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED +CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED + +ACCESSBANK NAME=accessram START=0x0 END=0x7F +DATABANK NAME=BIG_BLOCK START=0x80 END=0x5FF +ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED + +SECTION NAME=CONFIG ROM=config + +STACK SIZE=0x60 RAM=BIG_BLOCK diff --git a/20080212/Demo/PIC18_MPLAB/FreeRTOSConfig.h b/20080212/Demo/PIC18_MPLAB/FreeRTOSConfig.h new file mode 100644 index 000000000..5e128eb21 --- /dev/null +++ b/20080212/Demo/PIC18_MPLAB/FreeRTOSConfig.h @@ -0,0 +1,87 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 ) +#define configMINIMAL_STACK_SIZE ( 105 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) 1024 ) +#define configMAX_TASK_NAME_LEN ( 4 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 1 +#define configIDLE_SHOULD_YIELD 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/PIC18_MPLAB/ParTest/ParTest.c b/20080212/Demo/PIC18_MPLAB/ParTest/ParTest.c new file mode 100644 index 000000000..1a3ab2939 --- /dev/null +++ b/20080212/Demo/PIC18_MPLAB/ParTest/ParTest.c @@ -0,0 +1,133 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V2.0.0 + + + Use scheduler suspends in place of critical sections. +*/ + +#include "FreeRTOS.h" +#include "task.h" +#include "partest.h" + +/*----------------------------------------------------------- + * Simple parallel port IO routines for the FED 40pin demo board. + * The four LED's are connected to D4 to D7. + *-----------------------------------------------------------*/ + +#define partstBIT_AS_OUTPUT ( ( unsigned portSHORT ) 0 ) +#define partstSET_OUTPUT ( ( unsigned portSHORT ) 1 ) +#define partstCLEAR_OUTPUT ( ( unsigned portSHORT ) 0 ) + +#define partstENABLE_GENERAL_IO ( ( unsigned portCHAR ) 7 ) + +/*-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ + /* Set the top four bits of port D to output. */ + TRISDbits.TRISD7 = partstBIT_AS_OUTPUT; + TRISDbits.TRISD6 = partstBIT_AS_OUTPUT; + TRISDbits.TRISD5 = partstBIT_AS_OUTPUT; + TRISDbits.TRISD4 = partstBIT_AS_OUTPUT; + + /* Start with all bits off. */ + PORTDbits.RD7 = partstCLEAR_OUTPUT; + PORTDbits.RD6 = partstCLEAR_OUTPUT; + PORTDbits.RD5 = partstCLEAR_OUTPUT; + PORTDbits.RD4 = partstCLEAR_OUTPUT; + + /* Enable the driver. */ + ADCON1 = partstENABLE_GENERAL_IO; + TRISEbits.TRISE2 = partstBIT_AS_OUTPUT; + PORTEbits.RE2 = partstSET_OUTPUT; +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, portBASE_TYPE xValue ) +{ + /* We are only using the top nibble, so LED 0 corresponds to bit 4. */ + vTaskSuspendAll(); + { + switch( uxLED ) + { + case 3 : PORTDbits.RD7 = ( portSHORT ) xValue; + break; + case 2 : PORTDbits.RD6 = ( portSHORT ) xValue; + break; + case 1 : PORTDbits.RD5 = ( portSHORT ) xValue; + break; + case 0 : PORTDbits.RD4 = ( portSHORT ) xValue; + break; + default : /* There are only 4 LED's. */ + break; + } + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ + /* We are only using the top nibble, so LED 0 corresponds to bit 4. */ + vTaskSuspendAll(); + { + switch( uxLED ) + { + case 3 : PORTDbits.RD7 = !( PORTDbits.RD7 ); + break; + case 2 : PORTDbits.RD6 = !( PORTDbits.RD6 ); + break; + case 1 : PORTDbits.RD5 = !( PORTDbits.RD5 ); + break; + case 0 : PORTDbits.RD4 = !( PORTDbits.RD4 ); + break; + default : /* There are only 4 LED's. */ + break; + } + } + xTaskResumeAll(); +} + + + diff --git a/20080212/Demo/PIC18_MPLAB/main1.c b/20080212/Demo/PIC18_MPLAB/main1.c new file mode 100644 index 000000000..18bfd8ac3 --- /dev/null +++ b/20080212/Demo/PIC18_MPLAB/main1.c @@ -0,0 +1,196 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + * Instead of the normal single demo application, the PIC18F demo is split + * into several smaller programs of which this is the first. This enables the + * demo's to be executed on the RAM limited 40 pin devices. The 64 and 80 pin + * devices require a more costly development platform and are not so readily + * available. + * + * The RTOSDemo1 project is configured for a PIC18F452 device. Main1.c starts 5 + * tasks (including the idle task). + * + * The first task runs at the idle priority. It repeatedly performs a 32bit + * calculation and checks it's result against the expected value. This checks + * that the temporary storage utilised by the compiler to hold intermediate + * results does not get corrupted when the task gets switched in and out. See + * demo/common/minimal/integer.c for more information. + * + * The second and third tasks pass an incrementing value between each other on + * a message queue. See demo/common/minimal/PollQ.c for more information. + * + * Main1.c also creates a check task. This periodically checks that all the + * other tasks are still running and have not experienced any unexpected + * results. If all the other tasks are executing correctly an LED is flashed + * once every mainCHECK_PERIOD milliseconds. If any of the tasks have not + * executed, or report and error, the frequency of the LED flash will increase + * to mainERROR_FLASH_RATE. + * + * On entry to main an 'X' is transmitted. Monitoring the serial port using a + * dumb terminal allows for verification that the device is not continuously + * being reset (no more than one 'X' should be transmitted). + * + * http://www.FreeRTOS.org contains important information on the use of the + * PIC18F port. + */ + +/* +Changes from V2.0.0 + + + Delay periods are now specified using variables and constants of + portTickType rather than unsigned portLONG. +*/ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo app include files. */ +#include "pollq.h" +#include "integer.h" +#include "partest.h" +#include "serial.h" + +/* The period between executions of the check task before and after an error +has been discovered. If an error has been discovered the check task runs +more frequently - increasing the LED flash rate. */ +#define mainNO_ERROR_CHECK_PERIOD ( ( portTickType ) 1000 / portTICK_RATE_MS ) +#define mainERROR_CHECK_PERIOD ( ( portTickType ) 100 / portTICK_RATE_MS ) + +/* Priority definitions for some of the tasks. Other tasks just use the idle +priority. */ +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) + +/* The LED that is flashed by the check task. */ +#define mainCHECK_TASK_LED ( 0 ) + +/* Constants required for the communications. Only one character is ever +transmitted. */ +#define mainCOMMS_QUEUE_LENGTH ( 5 ) +#define mainNO_BLOCK ( ( portTickType ) 0 ) +#define mainBAUD_RATE ( ( unsigned portLONG ) 9600 ) + +/* + * The task function for the "Check" task. + */ +static void vErrorChecks( void *pvParameters ); + +/* + * Checks the unique counts of other tasks to ensure they are still operational. + * Returns pdTRUE if an error is detected, otherwise pdFALSE. + */ +static portBASE_TYPE prvCheckOtherTasksAreStillRunning( void ); + +/*-----------------------------------------------------------*/ + +/* Creates the tasks, then starts the scheduler. */ +void main( void ) +{ + /* Initialise the required hardware. */ + vParTestInitialise(); + vPortInitialiseBlocks(); + + /* Send a character so we have some visible feedback of a reset. */ + xSerialPortInitMinimal( mainBAUD_RATE, mainCOMMS_QUEUE_LENGTH ); + xSerialPutChar( NULL, 'X', mainNO_BLOCK ); + + /* Start the standard demo tasks found in the demo\common directory. */ + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + + /* Start the check task defined in this file. */ + xTaskCreate( vErrorChecks, ( const portCHAR * const ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Start the scheduler. Will never return here. */ + vTaskStartScheduler(); +} +/*-----------------------------------------------------------*/ + +static void vErrorChecks( void *pvParameters ) +{ +portTickType xDelayTime = mainNO_ERROR_CHECK_PERIOD; +portBASE_TYPE xErrorOccurred; + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. */ + for( ;; ) + { + /* Wait until it is time to check the other tasks. */ + vTaskDelay( xDelayTime ); + + /* Check all the other tasks are running, and running without ever + having an error. */ + xErrorOccurred = prvCheckOtherTasksAreStillRunning(); + + /* If an error was detected increase the frequency of the LED flash. */ + if( xErrorOccurred == pdTRUE ) + { + xDelayTime = mainERROR_CHECK_PERIOD; + } + + /* Flash the LED for visual feedback. */ + vParTestToggleLED( mainCHECK_TASK_LED ); + } +} +/*-----------------------------------------------------------*/ + +static portBASE_TYPE prvCheckOtherTasksAreStillRunning( void ) +{ +portBASE_TYPE xErrorHasOccurred = pdFALSE; + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + xErrorHasOccurred = pdTRUE; + } + + return xErrorHasOccurred; +} +/*-----------------------------------------------------------*/ + + diff --git a/20080212/Demo/PIC18_MPLAB/main2.c b/20080212/Demo/PIC18_MPLAB/main2.c new file mode 100644 index 000000000..57167baf9 --- /dev/null +++ b/20080212/Demo/PIC18_MPLAB/main2.c @@ -0,0 +1,171 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + * Instead of the normal single demo application, the PIC18F demo is split + * into several smaller programs of which this is the second. This enables the + * demo's to be executed on the RAM limited 40 pin devices. The 64 and 80 pin + * devices require a more costly development platform and are not so readily + * available. + * + * The RTOSDemo2 project is configured for a PIC18F452 device. Main2.c starts + * 5 tasks (including the idle task). + * + * The first, second and third tasks do nothing but flash an LED. This gives + * visual feedback that everything is executing as expected. One task flashes + * an LED every 333ms (i.e. on and off every 333/2 ms), then next every 666ms + * and the last every 999ms. + * + * The last task runs at the idle priority. It repeatedly performs a 32bit + * calculation and checks it's result against the expected value. This checks + * that the temporary storage utilised by the compiler to hold intermediate + * results does not get corrupted when the task gets switched in and out. + * should the calculation ever provide an incorrect result the final LED is + * turned on. + * + * On entry to main() an 'X' is transmitted. Monitoring the serial port using a + * dumb terminal allows for verification that the device is not continuously + * being reset (no more than one 'X' should be transmitted). + * + * http://www.FreeRTOS.org contains important information on the use of the + * PIC18F port. + */ + +/* +Changes from V2.0.0 + + + Delay periods are now specified using variables and constants of + portTickType rather than unsigned portLONG. +*/ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo app include files. */ +#include "flash.h" +#include "partest.h" +#include "serial.h" + +/* Priority definitions for the LED tasks. Other tasks just use the idle +priority. */ +#define mainLED_FLASH_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portBASE_TYPE ) 1 ) + +/* The LED that is lit when should the calculation fail. */ +#define mainCHECK_TASK_LED ( ( unsigned portBASE_TYPE ) 3 ) + +/* Constants required for the communications. Only one character is ever +transmitted. */ +#define mainCOMMS_QUEUE_LENGTH ( ( unsigned portBASE_TYPE ) 5 ) +#define mainNO_BLOCK ( ( portTickType ) 0 ) +#define mainBAUD_RATE ( ( unsigned portLONG ) 9600 ) + +/* + * The task that performs the 32 bit calculation at the idle priority. + */ +static void vCalculationTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* Creates the tasks, then starts the scheduler. */ +void main( void ) +{ + /* Initialise the required hardware. */ + vParTestInitialise(); + vPortInitialiseBlocks(); + + /* Send a character so we have some visible feedback of a reset. */ + xSerialPortInitMinimal( mainBAUD_RATE, mainCOMMS_QUEUE_LENGTH ); + xSerialPutChar( NULL, 'X', mainNO_BLOCK ); + + /* Start the standard LED flash tasks as defined in demo/common/minimal. */ + vStartLEDFlashTasks( mainLED_FLASH_PRIORITY ); + + /* Start the check task defined in this file. */ + xTaskCreate( vCalculationTask, ( const portCHAR * const ) "Check", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + + /* Start the scheduler. */ + vTaskStartScheduler(); +} +/*-----------------------------------------------------------*/ + +static void vCalculationTask( void *pvParameters ) +{ +volatile unsigned long ulCalculatedValue; /* Volatile to ensure optimisation is minimal. */ + + /* Continuously perform a calculation. If the calculation result is ever + incorrect turn the LED on. */ + for( ;; ) + { + /* A good optimising compiler would just remove all this! */ + ulCalculatedValue = 1234UL; + ulCalculatedValue *= 99UL; + + if( ulCalculatedValue != 122166UL ) + { + vParTestSetLED( mainCHECK_TASK_LED, pdTRUE ); + } + + ulCalculatedValue *= 9876UL; + + if( ulCalculatedValue != 1206511416UL ) + { + vParTestSetLED( mainCHECK_TASK_LED, pdTRUE ); + } + + ulCalculatedValue /= 15UL; + + if( ulCalculatedValue != 80434094UL ) + { + vParTestSetLED( mainCHECK_TASK_LED, pdTRUE ); + } + + ulCalculatedValue += 918273UL; + + if( ulCalculatedValue != 81352367UL ) + { + vParTestSetLED( mainCHECK_TASK_LED, pdTRUE ); + } + } +} +/*-----------------------------------------------------------*/ + diff --git a/20080212/Demo/PIC18_MPLAB/main3.c b/20080212/Demo/PIC18_MPLAB/main3.c new file mode 100644 index 000000000..db7f11101 --- /dev/null +++ b/20080212/Demo/PIC18_MPLAB/main3.c @@ -0,0 +1,200 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + * THIS DEMO APPLICATION REQUIRES A LOOPBACK CONNECTOR TO BE FITTED TO THE PIC + * USART PORT - connect pin 2 to pin 3 on J2. + * + * Instead of the normal single demo application, the PIC18F demo is split + * into several smaller programs of which this is the third. This enables the + * demo's to be executed on the RAM limited 40 pin devices. The 64 and 80 pin + * devices require a more costly development platform and are not so readily + * available. + * + * The RTOSDemo3 project is configured for a PIC18F452 device. Main3.c starts + * 5 tasks (including the idle task). + * + * The first task repeatedly transmits a string of characters on the PIC USART + * port. The second task receives the characters, checking that the correct + * sequence is maintained (i.e. what is transmitted is identical to that + * received). Each transmitted and each received character causes an LED to + * flash. See demo/common/minimal/comtest. c for more information. + * + * The third task continuously performs a 32 bit calculation. This is a good + * test of the context switch mechanism as the 8 bit architecture requires + * the use of several file registers to perform the 32 bit operations. See + * demo/common/minimal/integer. c for more information. + * + * The third task is the check task. This periodically checks that the other + * tasks are still running and have not experienced any errors. If no errors + * have been reported by either the comms or integer tasks an LED is flashed + * with a frequency mainNO_ERROR_CHECK_PERIOD. If an error is discovered the + * frequency is increased to mainERROR_FLASH_RATE. + * + * The check task also provides a visual indication of a system reset by + * flashing the one remaining LED (mainRESET_LED) when it starts. After + * this initial flash mainRESET_LED should remain off. + * + * http://www.FreeRTOS.org contains important information on the use of the + * PIC18F port. + */ + +/* +Changes from V2.0.0 + + + Delay periods are now specified using variables and constants of + portTickType rather than unsigned portLONG. +*/ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo app include files. */ +#include "partest.h" +#include "serial.h" +#include "comtest.h" +#include "integer.h" + +/* Priority definitions for the LED tasks. Other tasks just use the idle +priority. */ +#define mainCOMM_TEST_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portBASE_TYPE ) 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portBASE_TYPE ) 3 ) + +/* The period between executions of the check task before and after an error +has been discovered. If an error has been discovered the check task runs +more frequently - increasing the LED flash rate. */ +#define mainNO_ERROR_CHECK_PERIOD ( ( portTickType ) 1000 / portTICK_RATE_MS ) +#define mainERROR_CHECK_PERIOD ( ( portTickType ) 100 / portTICK_RATE_MS ) + +/* The period for which mainRESET_LED remain on every reset. */ +#define mainRESET_LED_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS ) + +/* The LED that is toggled whenever a character is transmitted. +mainCOMM_TX_RX_LED + 1 will be toggled every time a character is received. */ +#define mainCOMM_TX_RX_LED ( ( unsigned portBASE_TYPE ) 2 ) + +/* The LED that is flashed by the check task at a rate that indicates the +error status. */ +#define mainCHECK_TASK_LED ( ( unsigned portBASE_TYPE ) 1 ) + +/* The LED that is flashed once upon every reset. */ +#define mainRESET_LED ( ( unsigned portBASE_TYPE ) 0 ) + +/* Constants required for the communications. */ +#define mainCOMMS_QUEUE_LENGTH ( ( unsigned portBASE_TYPE ) 5 ) +#define mainBAUD_RATE ( ( unsigned portLONG ) 57600 ) +/*-----------------------------------------------------------*/ + +/* + * Task function which periodically checks the other tasks for errors. Flashes + * an LED at a rate that indicates whether an error has ever been detected. + */ +static void vErrorChecks( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* Creates the tasks, then starts the scheduler. */ +void main( void ) +{ + /* Initialise the required hardware. */ + vParTestInitialise(); + + /* Initialise the block memory allocator. */ + vPortInitialiseBlocks(); + + /* Start the standard comtest tasks as defined in demo/common/minimal. */ + vAltStartComTestTasks( mainCOMM_TEST_PRIORITY, mainBAUD_RATE, mainCOMM_TX_RX_LED ); + + /* Start the standard 32bit calculation task as defined in + demo/common/minimal. */ + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + + /* Start the check task defined in this file. */ + xTaskCreate( vErrorChecks, ( const portCHAR * const ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Start the scheduler. This will never return. */ + vTaskStartScheduler(); +} +/*-----------------------------------------------------------*/ + +static void vErrorChecks( void *pvParameters ) +{ +portTickType xDelayTime = mainNO_ERROR_CHECK_PERIOD; +volatile unsigned portLONG ulDummy = 3UL; + + /* Toggle the LED so we can see when a reset occurs. */ + vParTestSetLED( mainRESET_LED, pdTRUE ); + vTaskDelay( mainRESET_LED_PERIOD ); + vParTestSetLED( mainRESET_LED, pdFALSE ); + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. */ + for( ;; ) + { + /* Wait until it is time to check the other tasks. */ + vTaskDelay( xDelayTime ); + + /* Perform an integer calculation - just to ensure the registers + get used. The result is not important. */ + ulDummy *= 3UL; + + /* Check all the other tasks are running, and running without ever + having an error. The delay period is lowered if an error is reported, + causing the LED to flash at a higher rate. */ + if( xAreIntegerMathsTaskStillRunning() == pdFALSE ) + { + xDelayTime = mainERROR_CHECK_PERIOD; + } + + if( xAreComTestTasksStillRunning() == pdFALSE ) + { + xDelayTime = mainERROR_CHECK_PERIOD; + } + + /* Flash the LED for visual feedback. The rate of the flash will + indicate the health of the system. */ + vParTestToggleLED( mainCHECK_TASK_LED ); + } +} +/*-----------------------------------------------------------*/ + diff --git a/20080212/Demo/PIC18_MPLAB/makebin1.bat b/20080212/Demo/PIC18_MPLAB/makebin1.bat new file mode 100644 index 000000000..2e9132f61 --- /dev/null +++ b/20080212/Demo/PIC18_MPLAB/makebin1.bat @@ -0,0 +1,3 @@ +del rtosdemo.hex +copy rtosdemo1.hex rtosdemo.hex +hex2bin rtosdemo.hex diff --git a/20080212/Demo/PIC18_MPLAB/makebin2.bat b/20080212/Demo/PIC18_MPLAB/makebin2.bat new file mode 100644 index 000000000..9c4a7e56e --- /dev/null +++ b/20080212/Demo/PIC18_MPLAB/makebin2.bat @@ -0,0 +1,3 @@ +del rtosdemo.hex +copy rtosdemo2.hex rtosdemo.hex +hex2bin rtosdemo.hex diff --git a/20080212/Demo/PIC18_MPLAB/makebin3.bat b/20080212/Demo/PIC18_MPLAB/makebin3.bat new file mode 100644 index 000000000..57db0de0e --- /dev/null +++ b/20080212/Demo/PIC18_MPLAB/makebin3.bat @@ -0,0 +1,3 @@ +del rtosdemo.hex +copy rtosdemo3.hex rtosdemo.hex +hex2bin rtosdemo.hex diff --git a/20080212/Demo/PIC18_MPLAB/readme.txt b/20080212/Demo/PIC18_MPLAB/readme.txt new file mode 100644 index 000000000..a46af4d5d --- /dev/null +++ b/20080212/Demo/PIC18_MPLAB/readme.txt @@ -0,0 +1,12 @@ +Unfortunately the project files: + +RTOSDemo1.mcp +RTOSDemo2.mcp +and RTOSDemo3.mcp + +contain absolute paths. I don't know how to get around this, so if somebody knows, let me know! + +Edit the paths in a text editor before use. + +See the PIC port section of www.FreeRTOS.org for more information. + diff --git a/20080212/Demo/PIC18_MPLAB/rtosdemo.mcw b/20080212/Demo/PIC18_MPLAB/rtosdemo.mcw new file mode 100644 index 0000000000000000000000000000000000000000..1b81b6c19bc78e2cfa2d4716e7a77739e7befa38 GIT binary patch literal 45568 zcmeHQ4|J8qm7kXv{t6b85F^I$0;mBah7d3);tL5F1SBRAVtl(0lR#4QPxA0l`?}_| zR#O`nR;guKwCSlEbGj^nt##8aXG@nTo;|e9*<&kGwxY70ZY7Eqm9=R0_nYs#d0(DM zczMuDbZ*XlGvCaex%1t*cjkVR@0;oV)g{Nizjw-ODhw7WxB8@aoEq&&cOg#HFiEKx zM2MgC_V!wdN+D`s1WDjyv~?6Z?>1m8ko`R#I0iTtI1cCmrT`}ZCju`9ehCN_P?rGX zfbqZt;ACJT@KRtB@G{^O;N`$%;1xjX%T$DmflGkXfYX69fL8*q0$vSF1I`4_0$u}5 z2VM)D4ZIGR0h|NO1kMF!0p|hd1Fr{W0~Y{q0Nw~(2)qfn2zWEl3(NtsJ-G;%0&fB4 z1M`5(fy;om0#^Xn09OK60a>O1;qAaeU=gqwcn5Gbkom+59ST)F{`~0UC8`eLM)ei6 zK5|G@qxx)~{XP_|n=tORZ13|fH;9_pxqwngbEB$ImH3SYF2)GtlyRhWun!5jxcgew zfZsZ_ff87$$`F>R4H30znu>AJZln#m(zE<<3~gZ{0QuLc^{N{DR)S+Ku7}eHQ=+(k zv0?J3&T$wSET$T<#({c|kf7(n~y zSV{e%{j*#+(*8MClmPDpmIChr`hcVrScmH};N8G-U4Zgg}`+Q3`R#p}kuPVYt zZN0BxS?=07*-NwLWv*RWup(!%uePkZZtm=ID#1p7ePacPX4jTeR|+sn=3*qyhUBs^ z0&_gRW9sREch>0u`5b;XPNf_?6Ig=Y@nK}GL<@bO-H2EvM$ckMv&hb&{`>42*Y>M( zEo5JSKFGnm;X_$JC>!<2!7_6(E0iOo?DWtAo-gGb4|K(*sx`_x#K8CcN%bPWBYn>dN1-groM*3~Qmv>JN zR=k@UytwYQKzen&BF)5($w8KL@@@w$ueEs!zG~MzTS^EC8Lii0}TjAXHu44r*T;$)D$A?OYCKCf)s_3J>+3v) zl^d!X{goSGKE_Ss7HdCgpr~;N*4U1~PI8%mk1I!|T z6etjFTp)rXT0bdQ!Yc6Nyt@>Z!t5uf2v{K>CFqAWRj5fLuIz=eb{L8_;4E#N4 z$0oF<9HUD$BvXf!LbPgwmW&^GaJBPTM%$0i8pOlWlo1%>{eu0`37$ z!c8B^RO+8F`N~)t{2)#>0c9*p&VN{?`{T7=!LiJZI+&K$nTxx&{CnyH=Why!$fh{k zh9vcKw1I7V4LBZ^JchI@X1;aPfhC8RKQ_(vtD6F!&^1sG{l_cc`^M_AX=}>-2VA0{fETr{_h>TjhLL zhdFR1b#yMd-C9I?r~HPRSAFmz%22jWKRvM|{hr~?%~Hpq+k4!BcP!tL{ptj{ABI$) z@Q}1jYkFck-K$|joO)rDRfKgA3E?3-I=cF;`Xc%5Q>G{)`6)fxviLI^NIM7u_ss2y zdGjMWn?bh&8GsV_8KhzU|9qg6^nE++g*xPfGaw_@qm$Z!Y%2SlpzXxN zC+VT#Vh9)QbJ367RFhj@+fcTV_S>+@zq+huQ>A(07d5`x1att+?0Uz23rR%LVYWM)CKxgXugggLq9+KYFoeq z*)rW%+Y{qxnriaI6tJzde*)Y2H6Z7s-d^_u^kugoz6JL%Atyl{qQ8^(Mqn<|W?-DA zo_OJtW+T1qM(7k>IuI_%wDme4Y*Xi)IamPgC?IXv*RCO+Ezi ze_AiSviB#8o@ev=U=E%ZGq6f0y4#l#VPpat{gKd zqZ9LjZX)gEfUSp=pTlK`;?!>@T6V&6`|bKcqM;@w=uU?% zF`aennHzKyy-0iSadpsr95fxjY18SXVLI#SzAoryKI7RKQ#uZ}1-7Go zoO8HNz&hGz2i>eM5BV(1xB&B5M?p!@y>PxIXRduw-mG&`$8Pu%L3ascBz#%60d?v7 zLHx*cri5%{EAn_hOkICM!zfFbj4M#x5xA7vzTOq2eVG$i%)>1N1ObckgIBz_2O9t#~5Xsx$& zXdBAytlewfCo+WxX*-d3@VVXn^4|U>u90`+>bAg+V#=^f%ZzjSN~E!VZ$Z%gqwiYr zs;jS!c@U^v?xxm-A$^o~oi973)$)1P8ucw(HFi33?DPTX&7zsqo{-KPJ5}mJuv6M< zu6~}b#T;0!SFwFqH`<6eL%%B1>(`sG_T)oahNh^tXUzWdsj<_MJ)g=to3Yc8KA&3u z<&t%;I@?;s?=^NhvhB1O2HJKlt<=n?#_u)Hrx)t;>D{o;$Miq=jh%j;?X&>@<8rPe zm80Ly^XbTWK3#|Y`gbnO0%ZNgJfB_|&!_B@^R~v)Ny+4I6l+K_=7&{%=^Xbsf zr^Zf4ww?03i6iOSOwD{cqW>>r?DX^e|5L8_%6kCD?;XkiKQ(sxdA3u&aQc*4?^PG- zdk&VTV}AeK5(vG2R*V%luDS6ot;it}@Bi@~vPnRGS2580`11ar=bztyDtAHu_y3CY zmlm~n1F;4;+^;|Q%9u-k|8OOE^ZlrSK=@1Oq~SMZ=hBA6D89d-8!zu+TKxI`93@Z& zY4H2c$bsK~@O4l=!i(Q=w$hh_;6a;cF}PKN?>%@IpV(E`ux`2ud07T6xXcg!(} z?}GB)(oz3Dyob%WKuJkY4DlG=oo8M#Lgr-;X36*VCjQPS)-nUjlrwc<*?&?ah1J0{M`2d?onJ-8A_^0f;#>QS6OkUBfcA<{6 zzwrdwo)X0O97_z|r{6xr`{1A{Mw<170ly*s^!K!Udx_r|8~7qgAY2pX;7u2!311`) zkb4c+giNCeA{rAK2^a|&2^a|&2^a|&2^a|&2^a|&2^a|&2^a|&2^a|&2^a|&2^a|& z2^a|&2^a|&2^a|&2^a|&2^a|&2^a|&2^a|&2^a|&2^a|&2^a|&2^a|&2^a|&2^a|& z2^a|&2^a|&2^a|&2^a|&2^a|&2^a|&37mHc^xuD^{|V5MFiXL%9^7Ao;5>)SSyuKv zk3`>0&%%y7iFR$OD9|NPE@7n43Y zfZakuAm?5S|3)>uv!G{0vHwsa*mKVs!WzBjP`RqIE{FX)0rx*0rFc`94N_X}KO<($ z@8iPGzYg&q-hB(JWZeH0Tv!?y+5SIMLC-y72u}XP+xf~WKPig+k31+U`e#{O8TMRi z#2!SoIE%9eXRk*NNsvG9o!h!_kJy1=-8a57@kyLNp7G-`f#>)4*S}0PAA2vI+xeS3 zevxNdvK<5Q4^N}M?6UWv$prVgIDa!UoG8L;p8rX{0+AHs9-XrP(>!qIIk?fn*eL9e zdzC$HZ&t=L_-fB#m!0vB@s~0f=svtf2hy(3M0{LU&HJ#KcgIf*uJ?g~%Ndnz9d&hInqdcTJ z&rjsONRRum7ZlQ4H*jAhYu_gBuSE2eTKh7!BL7d%?G3R0BAltn^RSuEeVK$u7ieTJ zCuxWD^Ks-k_i{Qs-{K?r)QKlEIsy!tcQZn&DC-G7S8}j3d_k(#VNWaBOH10obcyrq z=98e|UQq<@i^Y2mB2D;m4=&*=bWD@|wImHmef2Uv6yGfD#Z`qffSo|T*8Iy|&&r^O zwa~_mPLi|6x&Im4L!BTDRA61kPj;mI_<&17Ck;=-woantZ#4V=4S)XUu@o}?Tm08! z=erHqfsaz~BhEH?)MCWW)~2g)|5U)MfK#0}=7_hB9yL97_W{?Q7w7Cd7&iVo`A5Rf zQLTUyJ^q!niYgN9a6T8DltBBmqzSI&_{b^DcjTcVHdDpO#qX)wVp- zJ|LjejcLH?n&pqVYi8Knp@6B>tY5Z-QPM5iq{7%RA#4w-n4x<#-5z}obx+I-JIh@Ki}RouajIZej@$ARn^{cNH&#^E*3Ygj*R?Fe*|!|S zm*Q+&?kUS%8+Rt>B_uX&p^EsUMb1%^f%yJEoa|U`WTkpj?AHUgnB8&`@ z;s0htV9)jD2iD)y%!N27A%Qg|t z*ST%$^={*h7;CK&wp*U-G4JJZk_GU7=_h5p9P*QL(Ga$UBwl6$m?ra&=#|%|<8`>7 zN#4oXpW*tmZ*Yw0}2hG1- z*P+*PSdSAP0?ETbTJ5)hj{v_7YymzB{9E7_;8x(@0UrZC4%`O(4)6)!cY)i1e-GRN z{0HDp;FG|ofZqeQ0>2Mr{}}jeBmnViJErZ(y4tz=$<%MrMcN_#WQJb^KUv10vyIb5 z@P)bFR1RO)r&n7VaRx)9JsNXOrVJyr56?h66~c_uBXykqCJcd=eXip)%*WU%g#b7o z&$G1CTG(KvDpbX471kboz@co?*Y7#cIvp(hIk*4QstbPV3E*Mir2n(f>90Nwzq1`E zi>@V__re@-l(g=kxnf@TH%>4fU{1;^#k&Yw`2- zb3Ww6Fb(YxKfl5*BYwUg*Jtzdp9M`m5WS~;cyDfhKc9T3-?1jhbn){iA&oqbB6P~_ z1g;12^Viw!WZzO|yr!Su33|$n@;jTKe;8$n%dtB06<{aI3Uk~DEr&=wD#Lt%X(@`iQezVL;L;2aS^Bfo3FAw*#w^oOI zW6tAJA6q5Yhh3JRJt6k+NI#Gwc7Cl&jOH=XxY%#ItBb#^OhD zJ(9fmOvW + +/* +** These fuses are for PIC18F4620 +*/ +#pragma __config _CONFIG1H,_IESO_OFF_1H & _FCMEN_OFF_1H & _OSC_HSPLL_1H +#pragma __config _CONFIG2L,_BORV_21_2L & _BOREN_SBORDIS_2L & _PWRT_ON_2L +#pragma __config _CONFIG2H,_WDTPS_32768_2H & _WDT_OFF_2H +#pragma __config _CONFIG3H,_MCLRE_ON_3H & _LPT1OSC_OFF_3H & _PBADEN_OFF_3H & _CCP2MX_PORTC_3H +#pragma __config _CONFIG4L,_DEBUG_OFF_4L & _XINST_OFF_4L & _LVP_OFF_4L & _STVREN_OFF_4L +#pragma __config _CONFIG5L,_CP3_OFF_5L & _CP2_OFF_5L & _CP1_OFF_5L & _CP0_OFF_5L +#pragma __config _CONFIG5H,_CPD_OFF_5H & _CPB_OFF_5H +#pragma __config _CONFIG6L,_WRT3_OFF_6L & _WRT2_OFF_6L & _WRT1_OFF_6L & _WRT0_OFF_6L +#pragma __config _CONFIG6H,_WRTD_OFF_6H & _WRTB_OFF_6H & _WRTC_OFF_6H +#pragma __config _CONFIG7L,_EBTR3_OFF_7L & _EBTR2_OFF_7L & _EBTR1_OFF_7L & _EBTR0_OFF_7L +#pragma __config _CONFIG7H,_EBTRB_OFF_7H diff --git a/20080212/Demo/PIC18_WizC/Demo1/interrupt.c b/20080212/Demo/PIC18_WizC/Demo1/interrupt.c new file mode 100644 index 000000000..a0e13419a --- /dev/null +++ b/20080212/Demo/PIC18_WizC/Demo1/interrupt.c @@ -0,0 +1,119 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + + Added functionality to only call vTaskSwitchContext() once + when handling multiple interruptsources in a single interruptcall. + + + Included Filenames changed to a .c extension to allow stepping through + code using F7. + +Changes from V3.0.1 +*/ + +#include + +/* Scheduler include files. */ +#include +#include +#include + +static bit uxSwitchRequested; + +/* + * Vector for the ISR. + */ +void pointed Interrupt() +{ + /* + * Save the context of the current task. + */ + portSAVE_CONTEXT( portINTERRUPTS_FORCED ); + + /* + * No contextswitch requested yet + */ + uxSwitchRequested = pdFALSE; + + /* + * Was the interrupt the FreeRTOS SystemTick? + */ + #include + +/******************************************************************************* +** DO NOT MODIFY ANYTHING ABOVE THIS LINE +******************************************************************************** +** Enter the includes for the ISR-code of the FreeRTOS drivers below. +** +** You cannot use local variables. Alternatives are: +** - Use static variables (Global RAM usage increases) +** - Call a function (Additional cycles are needed) +** - Use unused SFR's (preferred, no additional overhead) +** See "../Serial/isrSerialTx.c" for an example of this last option +*******************************************************************************/ + + + + + + + +/******************************************************************************* +** DO NOT MODIFY ANYTHING BELOW THIS LINE +*******************************************************************************/ + /* + * Was a contextswitch requested by one of the + * interrupthandlers? + */ + if ( uxSwitchRequested ) + { + vTaskSwitchContext(); + } + + /* + * Restore the context of the (possibly other) task. + */ + portRESTORE_CONTEXT(); + + #pragma asmline retfie 0 +} diff --git a/20080212/Demo/PIC18_WizC/Demo1/main.c b/20080212/Demo/PIC18_WizC/Demo1/main.c new file mode 100644 index 000000000..d97dabf04 --- /dev/null +++ b/20080212/Demo/PIC18_WizC/Demo1/main.c @@ -0,0 +1,212 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + +Changes from V3.0.1 +*/ + +/* + * Instead of the normal single demo application, the PIC18F demo is split + * into several smaller programs of which this is the first. This enables the + * demo's to be executed on the RAM limited PIC-devices. + * + * The Demo1 project is configured for a PIC18F4620 device. Main.c starts 9 + * tasks (including the idle task). + + * This first demo is included to do a quick check on the FreeRTOS + * installation. It is also included to demonstrate a minimal project-setup + * to use FreeRTOS in a wizC environment. + * + * Eight independant tasks are created. All tasks share the same taskcode. + * Each task blinks a different led on portB. The blinkrate for each task + * is different, but chosen in such a way that portB will show a binary + * counter pattern. All blinkrates are derived from a single master-rate. + * By default, this masterrate is set to 100 milliseconds. Although such + * a low value will make it almost impossible to see some of the leds + * actually blink, it is a good value when using the wizC-simulator. + * When testing on a real chip, changing the value to eg. 500 milliseconds + * would be appropiate. + */ + +/* Scheduler include files. */ +#include +#include + +#define mainBLINK_LED_INTERVAL ( ( portTickType ) 100 / ( portTICK_RATE_MS ) ) + +/* The LED that is flashed by the B0 task. */ +#define mainBLINK_LED0_PORT LATD +#define mainBLINK_LED0_TRIS TRISD +#define mainBLINK_LED0_PIN 0 +#define mainBLINK_LED0_INTERVAL ((mainBLINK_LED_INTERVAL) << (mainBLINK_LED0_PIN)) + +/* The LED that is flashed by the B1 task. */ +#define mainBLINK_LED1_PORT LATD +#define mainBLINK_LED1_TRIS TRISD +#define mainBLINK_LED1_PIN 1 +#define mainBLINK_LED1_INTERVAL ((mainBLINK_LED_INTERVAL) << (mainBLINK_LED1_PIN)) + +/* The LED that is flashed by the B2 task. */ +#define mainBLINK_LED2_PORT LATD +#define mainBLINK_LED2_TRIS TRISD +#define mainBLINK_LED2_PIN 2 +#define mainBLINK_LED2_INTERVAL ((mainBLINK_LED_INTERVAL) << (mainBLINK_LED2_PIN)) + +/* The LED that is flashed by the B3 task. */ +#define mainBLINK_LED3_PORT LATD +#define mainBLINK_LED3_TRIS TRISD +#define mainBLINK_LED3_PIN 3 +#define mainBLINK_LED3_INTERVAL ((mainBLINK_LED_INTERVAL) << (mainBLINK_LED3_PIN)) + +/* The LED that is flashed by the B4 task. */ +#define mainBLINK_LED4_PORT LATD +#define mainBLINK_LED4_TRIS TRISD +#define mainBLINK_LED4_PIN 4 +#define mainBLINK_LED4_INTERVAL ((mainBLINK_LED_INTERVAL) << (mainBLINK_LED4_PIN)) + +/* The LED that is flashed by the B5 task. */ +#define mainBLINK_LED5_PORT LATD +#define mainBLINK_LED5_TRIS TRISD +#define mainBLINK_LED5_PIN 5 +#define mainBLINK_LED5_INTERVAL ((mainBLINK_LED_INTERVAL) << (mainBLINK_LED5_PIN)) + +/* The LED that is flashed by the B6 task. */ +#define mainBLINK_LED6_PORT LATD +#define mainBLINK_LED6_TRIS TRISD +#define mainBLINK_LED6_PIN 6 +#define mainBLINK_LED6_INTERVAL ((mainBLINK_LED_INTERVAL) << (mainBLINK_LED6_PIN)) + +/* The LED that is flashed by the B7 task. */ +#define mainBLINK_LED7_PORT LATD +#define mainBLINK_LED7_TRIS TRISD +#define mainBLINK_LED7_PIN 7 +#define mainBLINK_LED7_INTERVAL ((mainBLINK_LED_INTERVAL) << (mainBLINK_LED7_PIN)) + +typedef struct { + unsigned char *port; + unsigned char *tris; + unsigned char pin; + portTickType interval; +} SBLINK; + +const SBLINK sled0 = {&mainBLINK_LED0_PORT, &mainBLINK_LED0_TRIS, mainBLINK_LED0_PIN, mainBLINK_LED0_INTERVAL}; +const SBLINK sled1 = {&mainBLINK_LED1_PORT, &mainBLINK_LED1_TRIS, mainBLINK_LED1_PIN, mainBLINK_LED1_INTERVAL}; +const SBLINK sled2 = {&mainBLINK_LED2_PORT, &mainBLINK_LED2_TRIS, mainBLINK_LED2_PIN, mainBLINK_LED2_INTERVAL}; +const SBLINK sled3 = {&mainBLINK_LED3_PORT, &mainBLINK_LED3_TRIS, mainBLINK_LED3_PIN, mainBLINK_LED3_INTERVAL}; +const SBLINK sled4 = {&mainBLINK_LED4_PORT, &mainBLINK_LED4_TRIS, mainBLINK_LED4_PIN, mainBLINK_LED4_INTERVAL}; +const SBLINK sled5 = {&mainBLINK_LED5_PORT, &mainBLINK_LED5_TRIS, mainBLINK_LED5_PIN, mainBLINK_LED5_INTERVAL}; +const SBLINK sled6 = {&mainBLINK_LED6_PORT, &mainBLINK_LED6_TRIS, mainBLINK_LED6_PIN, mainBLINK_LED6_INTERVAL}; +const SBLINK sled7 = {&mainBLINK_LED7_PORT, &mainBLINK_LED7_TRIS, mainBLINK_LED7_PIN, mainBLINK_LED7_INTERVAL}; + +/* + * The task code for the "vBlink" task. + */ +static portTASK_FUNCTION_PROTO(vBlink, pvParameters); + +/*-----------------------------------------------------------*/ + +/* + * Creates the tasks, then starts the scheduler. + */ +void main( void ) +{ + /* + * Start the blink tasks defined in this file. + */ + xTaskCreate( vBlink, "B0", configMINIMAL_STACK_SIZE, &sled0, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vBlink, "B1", configMINIMAL_STACK_SIZE, &sled1, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vBlink, "B2", configMINIMAL_STACK_SIZE, &sled2, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vBlink, "B3", configMINIMAL_STACK_SIZE, &sled3, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vBlink, "B4", configMINIMAL_STACK_SIZE, &sled4, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vBlink, "B5", configMINIMAL_STACK_SIZE, &sled5, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vBlink, "B6", configMINIMAL_STACK_SIZE, &sled6, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vBlink, "B7", configMINIMAL_STACK_SIZE, &sled7, tskIDLE_PRIORITY, NULL ); + + /* + * Start the scheduler. + */ + vTaskStartScheduler( ); + + while(1) /* This point should never be reached. */ + { + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION(vBlink, pvParameters) +{ + unsigned char *Port = ((SBLINK *)pvParameters)->port; + unsigned char *Tris = ((SBLINK *)pvParameters)->tris; + unsigned char Pin = ((SBLINK *)pvParameters)->pin; + portTickType Interval = ((SBLINK *)pvParameters)->interval; + + portTickType xLastWakeTime; + + /* + * Initialize the hardware + */ + *Tris &= ~(1< diff --git a/20080212/Demo/PIC18_WizC/Demo2/fuses.c b/20080212/Demo/PIC18_WizC/Demo2/fuses.c new file mode 100644 index 000000000..c9552b350 --- /dev/null +++ b/20080212/Demo/PIC18_WizC/Demo2/fuses.c @@ -0,0 +1,68 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + +Changes from V3.0.1 +*/ + +/* +** Here are the configuration words set. See the PIC datasheet +** and the wizC manual for an explanation +*/ +#include + +/* +** These fuses are for PIC18F4620 +*/ +#pragma __config _CONFIG1H,_IESO_OFF_1H & _FCMEN_OFF_1H & _OSC_HSPLL_1H +#pragma __config _CONFIG2L,_BORV_21_2L & _BOREN_SBORDIS_2L & _PWRT_ON_2L +#pragma __config _CONFIG2H,_WDTPS_32768_2H & _WDT_OFF_2H +#pragma __config _CONFIG3H,_MCLRE_ON_3H & _LPT1OSC_OFF_3H & _PBADEN_OFF_3H & _CCP2MX_PORTC_3H +#pragma __config _CONFIG4L,_DEBUG_OFF_4L & _XINST_OFF_4L & _LVP_OFF_4L & _STVREN_OFF_4L +#pragma __config _CONFIG5L,_CP3_OFF_5L & _CP2_OFF_5L & _CP1_OFF_5L & _CP0_OFF_5L +#pragma __config _CONFIG5H,_CPD_OFF_5H & _CPB_OFF_5H +#pragma __config _CONFIG6L,_WRT3_OFF_6L & _WRT2_OFF_6L & _WRT1_OFF_6L & _WRT0_OFF_6L +#pragma __config _CONFIG6H,_WRTD_OFF_6H & _WRTB_OFF_6H & _WRTC_OFF_6H +#pragma __config _CONFIG7L,_EBTR3_OFF_7L & _EBTR2_OFF_7L & _EBTR1_OFF_7L & _EBTR0_OFF_7L +#pragma __config _CONFIG7H,_EBTRB_OFF_7H diff --git a/20080212/Demo/PIC18_WizC/Demo2/interrupt.c b/20080212/Demo/PIC18_WizC/Demo2/interrupt.c new file mode 100644 index 000000000..1e2a5749b --- /dev/null +++ b/20080212/Demo/PIC18_WizC/Demo2/interrupt.c @@ -0,0 +1,128 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + + Added functionality to only call vTaskSwitchContext() once + when handling multiple interruptsources in a single interruptcall. + + + Included Filenames changed to a .c extension to allow stepping through + code using F7. + +Changes from V3.0.1 +*/ + +#include + +/* Scheduler include files. */ +#include +#include +#include + +static bit uxSwitchRequested; + +/* + * Vector for the ISR. + */ +void pointed Interrupt() +{ + /* + * Save the context of the current task. + */ + portSAVE_CONTEXT( portINTERRUPTS_FORCED ); + + /* + * No contextswitch requested yet + */ + uxSwitchRequested = pdFALSE; + + /* + * Was the interrupt the FreeRTOS SystemTick? + */ + #include + +/******************************************************************************* +** DO NOT MODIFY ANYTHING ABOVE THIS LINE +******************************************************************************** +** Enter the includes for the ISR-code of the FreeRTOS drivers below. +** +** You cannot use local variables. Alternatives are: +** - Use static variables (Global RAM usage increases) +** - Call a function (Additional cycles are needed) +** - Use unused SFR's (preferred, no additional overhead) +** See "../Serial/isrSerialTx.c" for an example of this last option +*******************************************************************************/ + + + + /* + * Was the interrupt a byte being received? + */ + #include "../Serial/isrSerialRx.c" + + + /* + * Was the interrupt the Tx register becoming empty? + */ + #include "../Serial/isrSerialTx.c" + + + +/******************************************************************************* +** DO NOT MODIFY ANYTHING BELOW THIS LINE +*******************************************************************************/ + /* + * Was a contextswitch requested by one of the + * interrupthandlers? + */ + if ( uxSwitchRequested ) + { + vTaskSwitchContext(); + } + + /* + * Restore the context of the (possibly other) task. + */ + portRESTORE_CONTEXT(); + + #pragma asmline retfie 0 +} diff --git a/20080212/Demo/PIC18_WizC/Demo2/main.c b/20080212/Demo/PIC18_WizC/Demo2/main.c new file mode 100644 index 000000000..0f874c1d9 --- /dev/null +++ b/20080212/Demo/PIC18_WizC/Demo2/main.c @@ -0,0 +1,208 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + +Changes from V3.0.1 +*/ + +/* + * Instead of the normal single demo application, the PIC18F demo is split + * into several smaller programs of which this is the second. This enables the + * demo's to be executed on the RAM limited PIC-devices. + * + * The Demo2 project is configured for a PIC18F4620 device. Main.c starts 12 + * tasks (including the idle task). See the indicated files in the demo/common + * directory for more information. + * + * demo/common/minimal/integer.c: Creates 1 task + * demo/common/minimal/PollQ.c: Creates 2 tasks + * demo/common/minimal/semtest.c: Creates 4 tasks + * demo/common/minimal/flash.c: Creates 3 tasks + * + * Main.c also creates a check task. This periodically checks that all the + * other tasks are still running and have not experienced any unexpected + * results. If all the other tasks are executing correctly an LED is flashed + * once every mainCHECK_PERIOD milliseconds. If any of the tasks have not + * executed, or report an error, the frequency of the LED flash will increase + * to mainERROR_FLASH_RATE. + * + * On entry to main an 'X' is transmitted. Monitoring the serial port using a + * dumb terminal allows for verification that the device is not continuously + * being reset (no more than one 'X' should be transmitted). + * + * http://www.FreeRTOS.org contains important information on the use of the + * wizC PIC18F port. + */ + +/* Scheduler include files. */ +#include +#include + +/* Demo app include files. */ +#include "integer.h" +#include "pollq.h" +#include "semtest.h" +#include "flash.h" +#include "partest.h" +#include "serial.h" + +/* The period between executions of the check task before and after an error +has been discovered. If an error has been discovered the check task runs +more frequently - increasing the LED flash rate. */ +#define mainNO_ERROR_CHECK_PERIOD ( ( portTickType ) 10000 / portTICK_RATE_MS ) +#define mainERROR_CHECK_PERIOD ( ( portTickType ) 1000 / portTICK_RATE_MS ) +#define mainCHECK_TASK_LED ( ( unsigned portCHAR ) 3 ) + +/* Priority definitions for some of the tasks. Other tasks just use the idle +priority. */ +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 3 ) +#define mainLED_FLASH_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 2 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 1 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 1 ) +#define mainINTEGER_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 0 ) + +/* Constants required for the communications. Only one character is ever +transmitted. */ +#define mainCOMMS_QUEUE_LENGTH ( ( unsigned portCHAR ) 5 ) +#define mainNO_BLOCK ( ( portTickType ) 0 ) +#define mainBAUD_RATE ( ( unsigned portLONG ) 57600 ) + +/* + * The task function for the "Check" task. + */ +static portTASK_FUNCTION_PROTO( vErrorChecks, pvParameters ); + +/* + * Checks the unique counts of other tasks to ensure they are still operational. + * Returns pdTRUE if an error is detected, otherwise pdFALSE. + */ +static portCHAR prvCheckOtherTasksAreStillRunning( void ); + +/*-----------------------------------------------------------*/ + +/* Creates the tasks, then starts the scheduler. */ +void main( void ) +{ + /* Initialise the required hardware. */ + vParTestInitialise(); + + /* Send a character so we have some visible feedback of a reset. */ + xSerialPortInitMinimal( mainBAUD_RATE, mainCOMMS_QUEUE_LENGTH ); + xSerialPutChar( NULL, 'X', mainNO_BLOCK ); + + /* Start a few of the standard demo tasks found in the demo\common directory. */ + vStartIntegerMathTasks( mainINTEGER_PRIORITY); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartLEDFlashTasks( mainLED_FLASH_PRIORITY ); + + /* Start the check task defined in this file. */ + xTaskCreate( vErrorChecks, ( const portCHAR * const ) "Check", portMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Start the scheduler. Will never return here. */ + vTaskStartScheduler(); + + while(1) /* This point should never be reached. */ + { + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vErrorChecks, pvParameters ) +{ +portTickType xLastCheckTime; +portTickType xDelayTime = mainNO_ERROR_CHECK_PERIOD; +portCHAR cErrorOccurred; + + /* We need to initialise xLastCheckTime prior to the first call to + vTaskDelayUntil(). */ + xLastCheckTime = xTaskGetTickCount(); + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. */ + for( ;; ) + { + /* Wait until it is time to check the other tasks again. */ + vTaskDelayUntil( &xLastCheckTime, xDelayTime ); + + /* Check all the other tasks are running, and running without ever + having an error. */ + cErrorOccurred = prvCheckOtherTasksAreStillRunning(); + + /* If an error was detected increase the frequency of the LED flash. */ + if( cErrorOccurred == pdTRUE ) + { + xDelayTime = mainERROR_CHECK_PERIOD; + } + + /* Flash the LED for visual feedback. */ + vParTestToggleLED( mainCHECK_TASK_LED ); + } +} +/*-----------------------------------------------------------*/ + +static portCHAR prvCheckOtherTasksAreStillRunning( void ) +{ + portCHAR cErrorHasOccurred = ( portCHAR ) pdFALSE; + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + cErrorHasOccurred = ( portCHAR ) pdTRUE; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + cErrorHasOccurred = ( portCHAR ) pdTRUE; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + cErrorHasOccurred = ( portCHAR ) pdTRUE; + } + + return cErrorHasOccurred; +} +/*-----------------------------------------------------------*/ + + diff --git a/20080212/Demo/PIC18_WizC/Demo3/Demo3.PC b/20080212/Demo/PIC18_WizC/Demo3/Demo3.PC new file mode 100644 index 000000000..1fed171da --- /dev/null +++ b/20080212/Demo/PIC18_WizC/Demo3/Demo3.PC @@ -0,0 +1,503 @@ +[F29011781] +x=0 +y=118 +[F29216334] +x=0 +y=189 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+y=85 +[F18602004] +x=49 +y=1124 +[F18601966] +x=0 +y=0 +[F20220814] +x=0 +y=628 +[F29055566] +x=0 +y=137 +[F30163230] +x=33 +y=61 +[F29565054] +x=0 +y=0 +[F30163486] +x=32 +y=44 +[F29565310] +x=0 +y=0 +[F30089258] +x=0 +y=107 +[F29012293] +x=0 +y=114 +[F28446561] +x=0 +y=0 +[F30243165] +x=0 +y=4852 +[F27125515] +x=0 +y=0 +[F15568046] +x=0 +y=0 +[F20528681] +x=0 +y=0 +[F30163742] +x=0 +y=20 +[F33200396] +x=0 +y=107 +[F32375968] +x=0 +y=0 +[F28917072] +x=0 +y=114 +[F31779807] +x=0 +y=0 diff --git a/20080212/Demo/PIC18_WizC/Demo3/FreeRTOSConfig.h b/20080212/Demo/PIC18_WizC/Demo3/FreeRTOSConfig.h new file mode 100644 index 000000000..0b1ad2f58 --- /dev/null +++ b/20080212/Demo/PIC18_WizC/Demo3/FreeRTOSConfig.h @@ -0,0 +1,92 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + + TickRate reduced to 250Hz. + + + configIDLE_SHOULD_YIELD added. + +Changes from V3.0.1 +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION ( 1 ) +#define configUSE_IDLE_HOOK ( 0 ) +#define configUSE_TICK_HOOK ( 0 ) +#define configTICK_RATE_HZ ( 250 ) +#define configMAX_PRIORITIES ( 4 ) +#define configMINIMAL_STACK_SIZE portMINIMAL_STACK_SIZE +#define configMAX_TASK_NAME_LEN ( 3 ) +#define configUSE_TRACE_FACILITY ( 0 ) +#define configUSE_16_BIT_TICKS ( 1 ) +#define configIDLE_SHOULD_YIELD ( 1 ) + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the component, or zero +to exclude the component. */ + +/* Include/exclude the stated API function. */ +#define INCLUDE_vTaskPrioritySet ( 0 ) +#define INCLUDE_uxTaskPriorityGet ( 0 ) +#define INCLUDE_vTaskDelete ( 0 ) +#define INCLUDE_vTaskCleanUpResources ( 0 ) +#define INCLUDE_vTaskSuspend ( 0 ) +#define INCLUDE_vTaskDelayUntil ( 1 ) +#define INCLUDE_vTaskDelay ( 0 ) + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/PIC18_WizC/Demo3/MallocConfig.h b/20080212/Demo/PIC18_WizC/Demo3/MallocConfig.h new file mode 100644 index 000000000..195258b51 --- /dev/null +++ b/20080212/Demo/PIC18_WizC/Demo3/MallocConfig.h @@ -0,0 +1,41 @@ +#ifndef _MALLOC_SETTINGS_H +#define _MALLOC_SETTINGS_H +/********************************************************************* +** Title: Dynamic memory (de-)allocation library for wizC. +** +** Author: Marcel van Lieshout +** +** Copyright: (c) 2005, HMCS, Marcel van Lieshout +** +** License: This software is released to the public domain and comes +** without warranty and/or guarantees of any kind. You have +** the right to use, copy, modify and/or (re-)distribute the +** software as long as the reference to the author is +** maintained in the software and a reference to the author +** is included in any documentation of each product in which +** this library (in it's original or in a modified form) +** is used. +*********************************************************************/ + +/********************************************************************* +** The model to use +*********************************************************************/ +//#define MALLOC_SMALL +#define MALLOC_LARGE + +/********************************************************************* +** The size of the heap +*********************************************************************/ +#define MALLOC_HEAP_SIZE (3200) + +/********************************************************************* +** Should released memory be scribbled with 0x55 before releasing it? +*********************************************************************/ +//#define MALLOC_SCRIBBLE + +/******************************************************************** +** Enable Debug-mode? +*********************************************************************/ +//#define MALLOC_DEBUG + +#endif /* _MALLOC_SETTINGS_H */ diff --git a/20080212/Demo/PIC18_WizC/Demo3/WIZCmake.h b/20080212/Demo/PIC18_WizC/Demo3/WIZCmake.h new file mode 100644 index 000000000..b1ea6f5d4 --- /dev/null +++ b/20080212/Demo/PIC18_WizC/Demo3/WIZCmake.h @@ -0,0 +1,63 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + + Several modules predefined to avoid linker problems + +Changes from V3.0.1 +*/ + +#ifndef _memcpy + #define _memcpy 1 +#endif + +#ifndef _memset + #define _memset 1 +#endif + +#ifndef _strncpy + #define _strncpy 1 +#endif + + +#pragma wizcpp searchpath <../../Common/Include/> diff --git a/20080212/Demo/PIC18_WizC/Demo3/fuses.c b/20080212/Demo/PIC18_WizC/Demo3/fuses.c new file mode 100644 index 000000000..c9552b350 --- /dev/null +++ b/20080212/Demo/PIC18_WizC/Demo3/fuses.c @@ -0,0 +1,68 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + +Changes from V3.0.1 +*/ + +/* +** Here are the configuration words set. See the PIC datasheet +** and the wizC manual for an explanation +*/ +#include + +/* +** These fuses are for PIC18F4620 +*/ +#pragma __config _CONFIG1H,_IESO_OFF_1H & _FCMEN_OFF_1H & _OSC_HSPLL_1H +#pragma __config _CONFIG2L,_BORV_21_2L & _BOREN_SBORDIS_2L & _PWRT_ON_2L +#pragma __config _CONFIG2H,_WDTPS_32768_2H & _WDT_OFF_2H +#pragma __config _CONFIG3H,_MCLRE_ON_3H & _LPT1OSC_OFF_3H & _PBADEN_OFF_3H & _CCP2MX_PORTC_3H +#pragma __config _CONFIG4L,_DEBUG_OFF_4L & _XINST_OFF_4L & _LVP_OFF_4L & _STVREN_OFF_4L +#pragma __config _CONFIG5L,_CP3_OFF_5L & _CP2_OFF_5L & _CP1_OFF_5L & _CP0_OFF_5L +#pragma __config _CONFIG5H,_CPD_OFF_5H & _CPB_OFF_5H +#pragma __config _CONFIG6L,_WRT3_OFF_6L & _WRT2_OFF_6L & _WRT1_OFF_6L & _WRT0_OFF_6L +#pragma __config _CONFIG6H,_WRTD_OFF_6H & _WRTB_OFF_6H & _WRTC_OFF_6H +#pragma __config _CONFIG7L,_EBTR3_OFF_7L & _EBTR2_OFF_7L & _EBTR1_OFF_7L & _EBTR0_OFF_7L +#pragma __config _CONFIG7H,_EBTRB_OFF_7H diff --git a/20080212/Demo/PIC18_WizC/Demo3/interrupt.c b/20080212/Demo/PIC18_WizC/Demo3/interrupt.c new file mode 100644 index 000000000..1e2a5749b --- /dev/null +++ b/20080212/Demo/PIC18_WizC/Demo3/interrupt.c @@ -0,0 +1,128 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + + Added functionality to only call vTaskSwitchContext() once + when handling multiple interruptsources in a single interruptcall. + + + Included Filenames changed to a .c extension to allow stepping through + code using F7. + +Changes from V3.0.1 +*/ + +#include + +/* Scheduler include files. */ +#include +#include +#include + +static bit uxSwitchRequested; + +/* + * Vector for the ISR. + */ +void pointed Interrupt() +{ + /* + * Save the context of the current task. + */ + portSAVE_CONTEXT( portINTERRUPTS_FORCED ); + + /* + * No contextswitch requested yet + */ + uxSwitchRequested = pdFALSE; + + /* + * Was the interrupt the FreeRTOS SystemTick? + */ + #include + +/******************************************************************************* +** DO NOT MODIFY ANYTHING ABOVE THIS LINE +******************************************************************************** +** Enter the includes for the ISR-code of the FreeRTOS drivers below. +** +** You cannot use local variables. Alternatives are: +** - Use static variables (Global RAM usage increases) +** - Call a function (Additional cycles are needed) +** - Use unused SFR's (preferred, no additional overhead) +** See "../Serial/isrSerialTx.c" for an example of this last option +*******************************************************************************/ + + + + /* + * Was the interrupt a byte being received? + */ + #include "../Serial/isrSerialRx.c" + + + /* + * Was the interrupt the Tx register becoming empty? + */ + #include "../Serial/isrSerialTx.c" + + + +/******************************************************************************* +** DO NOT MODIFY ANYTHING BELOW THIS LINE +*******************************************************************************/ + /* + * Was a contextswitch requested by one of the + * interrupthandlers? + */ + if ( uxSwitchRequested ) + { + vTaskSwitchContext(); + } + + /* + * Restore the context of the (possibly other) task. + */ + portRESTORE_CONTEXT(); + + #pragma asmline retfie 0 +} diff --git a/20080212/Demo/PIC18_WizC/Demo3/main.c b/20080212/Demo/PIC18_WizC/Demo3/main.c new file mode 100644 index 000000000..50e8fdee0 --- /dev/null +++ b/20080212/Demo/PIC18_WizC/Demo3/main.c @@ -0,0 +1,200 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + +Changes from V3.0.1 +*/ + +/* + * Instead of the normal single demo application, the PIC18F demo is split + * into several smaller programs of which this is the third. This enables the + * demo's to be executed on the RAM limited PIC-devices. + * + * The Demo3 project is configured for a PIC18F4620 device. Main.c starts 12 + * tasks (including the idle task). See the indicated files in the demo/common + * directory for more information. + * + * demo/common/minimal/integer.c: Creates 1 task + * demo/common/minimal/BlockQ.c: Creates 6 tasks + * demo/common/minimal/flash.c: Creates 3 tasks + * + * Main.c also creates a check task. This periodically checks that all the + * other tasks are still running and have not experienced any unexpected + * results. If all the other tasks are executing correctly an LED is flashed + * once every mainCHECK_PERIOD milliseconds. If any of the tasks have not + * executed, or report an error, the frequency of the LED flash will increase + * to mainERROR_FLASH_RATE. + * + * On entry to main an 'X' is transmitted. Monitoring the serial port using a + * dumb terminal allows for verification that the device is not continuously + * being reset (no more than one 'X' should be transmitted). + * + * http://www.FreeRTOS.org contains important information on the use of the + * wizC PIC18F port. + */ + +/* Scheduler include files. */ +#include +#include + +/* Demo app include files. */ +#include "integer.h" +#include "BlockQ.h" +#include "flash.h" +#include "partest.h" +#include "serial.h" + +/* The period between executions of the check task before and after an error +has been discovered. If an error has been discovered the check task runs +more frequently - increasing the LED flash rate. */ +#define mainNO_ERROR_CHECK_PERIOD ( ( portTickType ) 10000 / portTICK_RATE_MS ) +#define mainERROR_CHECK_PERIOD ( ( portTickType ) 1000 / portTICK_RATE_MS ) +#define mainCHECK_TASK_LED ( ( unsigned portCHAR ) 3 ) + +/* Priority definitions for some of the tasks. Other tasks just use the idle +priority. */ +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 3 ) +#define mainLED_FLASH_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 2 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 1 ) +#define mainINTEGER_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 0 ) + +/* Constants required for the communications. Only one character is ever +transmitted. */ +#define mainCOMMS_QUEUE_LENGTH ( ( unsigned portCHAR ) 5 ) +#define mainNO_BLOCK ( ( portTickType ) 0 ) +#define mainBAUD_RATE ( ( unsigned portLONG ) 57600 ) + +/* + * The task function for the "Check" task. + */ +static portTASK_FUNCTION_PROTO( vErrorChecks, pvParameters ); + +/* + * Checks the unique counts of other tasks to ensure they are still operational. + * Returns pdTRUE if an error is detected, otherwise pdFALSE. + */ +static portCHAR prvCheckOtherTasksAreStillRunning( void ); + +/*-----------------------------------------------------------*/ + +/* Creates the tasks, then starts the scheduler. */ +void main( void ) +{ + /* Initialise the required hardware. */ + vParTestInitialise(); + + /* Send a character so we have some visible feedback of a reset. */ + xSerialPortInitMinimal( mainBAUD_RATE, mainCOMMS_QUEUE_LENGTH ); + xSerialPutChar( NULL, 'X', mainNO_BLOCK ); + + /* Start the standard demo tasks found in the demo\common directory. */ + vStartIntegerMathTasks( mainINTEGER_PRIORITY); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vStartLEDFlashTasks( mainLED_FLASH_PRIORITY ); + + /* Start the check task defined in this file. */ + xTaskCreate( vErrorChecks, ( const portCHAR * const ) "Check", portMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Start the scheduler. Will never return here. */ + vTaskStartScheduler( ); + + while(1) /* This point should never be reached. */ + { + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vErrorChecks, pvParameters ) +{ + portTickType xLastCheckTime; + portTickType xDelayTime = mainNO_ERROR_CHECK_PERIOD; + portCHAR cErrorOccurred; + + /* We need to initialise xLastCheckTime prior to the first call to + vTaskDelayUntil(). */ + xLastCheckTime = xTaskGetTickCount(); + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. */ + for( ;; ) + { + /* Wait until it is time to check the other tasks again. */ + vTaskDelayUntil( &xLastCheckTime, xDelayTime ); + + /* Check all the other tasks are running, and running without ever + having an error. */ + cErrorOccurred = prvCheckOtherTasksAreStillRunning(); + + /* If an error was detected increase the frequency of the LED flash. */ + if( cErrorOccurred == pdTRUE ) + { + xDelayTime = mainERROR_CHECK_PERIOD; + } + + /* Flash the LED for visual feedback. */ + vParTestToggleLED( mainCHECK_TASK_LED ); + } +} + +/*-----------------------------------------------------------*/ + +static portCHAR prvCheckOtherTasksAreStillRunning( void ) +{ + portCHAR cErrorHasOccurred = ( portCHAR ) pdFALSE; + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + cErrorHasOccurred = ( portCHAR ) pdTRUE; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + cErrorHasOccurred = ( portCHAR ) pdTRUE; + } + + return cErrorHasOccurred; +} +/*-----------------------------------------------------------*/ + + diff --git a/20080212/Demo/PIC18_WizC/Demo4/Demo4.PC b/20080212/Demo/PIC18_WizC/Demo4/Demo4.PC new file mode 100644 index 000000000..f4ee06de5 --- /dev/null +++ b/20080212/Demo/PIC18_WizC/Demo4/Demo4.PC @@ -0,0 +1,475 @@ +[F29012037] +x=0 +y=115 +[F15207742] +x=0 +y=48 +[F10478061] +x=0 +y=48 +[F28429921] +x=0 +y=0 +[ProjectGroup] +nFiles=1 +FileName0=Demo4.PC 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b/20080212/Demo/PIC18_WizC/Demo4/FreeRTOSConfig.h new file mode 100644 index 000000000..221a585ce --- /dev/null +++ b/20080212/Demo/PIC18_WizC/Demo4/FreeRTOSConfig.h @@ -0,0 +1,92 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + + TickRate reduced to 250Hz. + + + configIDLE_SHOULD_YIELD added. + +Changes from V3.0.1 +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION ( 1 ) +#define configUSE_IDLE_HOOK ( 0 ) +#define configUSE_TICK_HOOK ( 0 ) +#define configTICK_RATE_HZ ( 250 ) +#define configMAX_PRIORITIES ( 4 ) +#define configMINIMAL_STACK_SIZE portMINIMAL_STACK_SIZE +#define configMAX_TASK_NAME_LEN ( 3 ) +#define configUSE_TRACE_FACILITY ( 0 ) +#define configUSE_16_BIT_TICKS ( 1 ) +#define configIDLE_SHOULD_YIELD ( 1 ) + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the component, or zero +to exclude the component. */ + +/* Include/exclude the stated API function. */ +#define INCLUDE_vTaskPrioritySet ( 1 ) +#define INCLUDE_uxTaskPriorityGet ( 1 ) +#define INCLUDE_vTaskDelete ( 0 ) +#define INCLUDE_vTaskCleanUpResources ( 0 ) +#define INCLUDE_vTaskSuspend ( 1 ) +#define INCLUDE_vTaskDelayUntil ( 1 ) +#define INCLUDE_vTaskDelay ( 1 ) + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/PIC18_WizC/Demo4/MallocConfig.h b/20080212/Demo/PIC18_WizC/Demo4/MallocConfig.h new file mode 100644 index 000000000..195258b51 --- /dev/null +++ b/20080212/Demo/PIC18_WizC/Demo4/MallocConfig.h @@ -0,0 +1,41 @@ +#ifndef _MALLOC_SETTINGS_H +#define _MALLOC_SETTINGS_H +/********************************************************************* +** Title: Dynamic memory (de-)allocation library for wizC. +** +** Author: Marcel van Lieshout +** +** Copyright: (c) 2005, HMCS, Marcel van Lieshout +** +** License: This software is released to the public domain and comes +** without warranty and/or guarantees of any kind. You have +** the right to use, copy, modify and/or (re-)distribute the +** software as long as the reference to the author is +** maintained in the software and a reference to the author +** is included in any documentation of each product in which +** this library (in it's original or in a modified form) +** is used. +*********************************************************************/ + +/********************************************************************* +** The model to use +*********************************************************************/ +//#define MALLOC_SMALL +#define MALLOC_LARGE + +/********************************************************************* +** The size of the heap +*********************************************************************/ +#define MALLOC_HEAP_SIZE (3200) + +/********************************************************************* +** Should released memory be scribbled with 0x55 before releasing it? +*********************************************************************/ +//#define MALLOC_SCRIBBLE + +/******************************************************************** +** Enable Debug-mode? +*********************************************************************/ +//#define MALLOC_DEBUG + +#endif /* _MALLOC_SETTINGS_H */ diff --git a/20080212/Demo/PIC18_WizC/Demo4/WIZCmake.h b/20080212/Demo/PIC18_WizC/Demo4/WIZCmake.h new file mode 100644 index 000000000..b1ea6f5d4 --- /dev/null +++ b/20080212/Demo/PIC18_WizC/Demo4/WIZCmake.h @@ -0,0 +1,63 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + + Several modules predefined to avoid linker problems + +Changes from V3.0.1 +*/ + +#ifndef _memcpy + #define _memcpy 1 +#endif + +#ifndef _memset + #define _memset 1 +#endif + +#ifndef _strncpy + #define _strncpy 1 +#endif + + +#pragma wizcpp searchpath <../../Common/Include/> diff --git a/20080212/Demo/PIC18_WizC/Demo4/fuses.c b/20080212/Demo/PIC18_WizC/Demo4/fuses.c new file mode 100644 index 000000000..c9552b350 --- /dev/null +++ b/20080212/Demo/PIC18_WizC/Demo4/fuses.c @@ -0,0 +1,68 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + +Changes from V3.0.1 +*/ + +/* +** Here are the configuration words set. See the PIC datasheet +** and the wizC manual for an explanation +*/ +#include + +/* +** These fuses are for PIC18F4620 +*/ +#pragma __config _CONFIG1H,_IESO_OFF_1H & _FCMEN_OFF_1H & _OSC_HSPLL_1H +#pragma __config _CONFIG2L,_BORV_21_2L & _BOREN_SBORDIS_2L & _PWRT_ON_2L +#pragma __config _CONFIG2H,_WDTPS_32768_2H & _WDT_OFF_2H +#pragma __config _CONFIG3H,_MCLRE_ON_3H & _LPT1OSC_OFF_3H & _PBADEN_OFF_3H & _CCP2MX_PORTC_3H +#pragma __config _CONFIG4L,_DEBUG_OFF_4L & _XINST_OFF_4L & _LVP_OFF_4L & _STVREN_OFF_4L +#pragma __config _CONFIG5L,_CP3_OFF_5L & _CP2_OFF_5L & _CP1_OFF_5L & _CP0_OFF_5L +#pragma __config _CONFIG5H,_CPD_OFF_5H & _CPB_OFF_5H +#pragma __config _CONFIG6L,_WRT3_OFF_6L & _WRT2_OFF_6L & _WRT1_OFF_6L & _WRT0_OFF_6L +#pragma __config _CONFIG6H,_WRTD_OFF_6H & _WRTB_OFF_6H & _WRTC_OFF_6H +#pragma __config _CONFIG7L,_EBTR3_OFF_7L & _EBTR2_OFF_7L & _EBTR1_OFF_7L & _EBTR0_OFF_7L +#pragma __config _CONFIG7H,_EBTRB_OFF_7H diff --git a/20080212/Demo/PIC18_WizC/Demo4/interrupt.c b/20080212/Demo/PIC18_WizC/Demo4/interrupt.c new file mode 100644 index 000000000..1e2a5749b --- /dev/null +++ b/20080212/Demo/PIC18_WizC/Demo4/interrupt.c @@ -0,0 +1,128 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + + Added functionality to only call vTaskSwitchContext() once + when handling multiple interruptsources in a single interruptcall. + + + Included Filenames changed to a .c extension to allow stepping through + code using F7. + +Changes from V3.0.1 +*/ + +#include + +/* Scheduler include files. */ +#include +#include +#include + +static bit uxSwitchRequested; + +/* + * Vector for the ISR. + */ +void pointed Interrupt() +{ + /* + * Save the context of the current task. + */ + portSAVE_CONTEXT( portINTERRUPTS_FORCED ); + + /* + * No contextswitch requested yet + */ + uxSwitchRequested = pdFALSE; + + /* + * Was the interrupt the FreeRTOS SystemTick? + */ + #include + +/******************************************************************************* +** DO NOT MODIFY ANYTHING ABOVE THIS LINE +******************************************************************************** +** Enter the includes for the ISR-code of the FreeRTOS drivers below. +** +** You cannot use local variables. Alternatives are: +** - Use static variables (Global RAM usage increases) +** - Call a function (Additional cycles are needed) +** - Use unused SFR's (preferred, no additional overhead) +** See "../Serial/isrSerialTx.c" for an example of this last option +*******************************************************************************/ + + + + /* + * Was the interrupt a byte being received? + */ + #include "../Serial/isrSerialRx.c" + + + /* + * Was the interrupt the Tx register becoming empty? + */ + #include "../Serial/isrSerialTx.c" + + + +/******************************************************************************* +** DO NOT MODIFY ANYTHING BELOW THIS LINE +*******************************************************************************/ + /* + * Was a contextswitch requested by one of the + * interrupthandlers? + */ + if ( uxSwitchRequested ) + { + vTaskSwitchContext(); + } + + /* + * Restore the context of the (possibly other) task. + */ + portRESTORE_CONTEXT(); + + #pragma asmline retfie 0 +} diff --git a/20080212/Demo/PIC18_WizC/Demo4/main.c b/20080212/Demo/PIC18_WizC/Demo4/main.c new file mode 100644 index 000000000..8f0b8ddce --- /dev/null +++ b/20080212/Demo/PIC18_WizC/Demo4/main.c @@ -0,0 +1,199 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + +Changes from V3.0.1 +*/ + +/* + * Instead of the normal single demo application, the PIC18F demo is split + * into several smaller programs of which this is the fourth. This enables the + * demo's to be executed on the RAM limited PIC-devices. + * + * The Demo4 project is configured for a PIC18F4620 device. Main.c starts 11 + * tasks (including the idle task). See the indicated files in the demo/common + * directory for more information. + * + * demo/common/minimal/integer.c: Creates 1 task + * demo/common/minimal/dynamic.c: Creates 5 tasks + * demo/common/minimal/flash.c: Creates 3 tasks + * + * Main.c also creates a check task. This periodically checks that all the + * other tasks are still running and have not experienced any unexpected + * results. If all the other tasks are executing correctly an LED is flashed + * once every mainCHECK_PERIOD milliseconds. If any of the tasks have not + * executed, or report an error, the frequency of the LED flash will increase + * to mainERROR_FLASH_RATE. + * + * On entry to main an 'X' is transmitted. Monitoring the serial port using a + * dumb terminal allows for verification that the device is not continuously + * being reset (no more than one 'X' should be transmitted). + * + * http://www.FreeRTOS.org contains important information on the use of the + * wizC PIC18F port. + */ + +/* Scheduler include files. */ +#include +#include + +/* Demo app include files. */ +#include "integer.h" +#include "dynamic.h" +#include "flash.h" +#include "partest.h" +#include "serial.h" + +/* The period between executions of the check task before and after an error +has been discovered. If an error has been discovered the check task runs +more frequently - increasing the LED flash rate. */ +#define mainNO_ERROR_CHECK_PERIOD ( ( portTickType ) 10000 / portTICK_RATE_MS ) +#define mainERROR_CHECK_PERIOD ( ( portTickType ) 1000 / portTICK_RATE_MS ) +#define mainCHECK_TASK_LED ( ( unsigned portCHAR ) 3 ) + +/* Priority definitions for some of the tasks. Other tasks just use the idle +priority. */ +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 3 ) +#define mainLED_FLASH_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 2 ) +#define mainINTEGER_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 0 ) + +/* Constants required for the communications. Only one character is ever +transmitted. */ +#define mainCOMMS_QUEUE_LENGTH ( ( unsigned portCHAR ) 5 ) +#define mainNO_BLOCK ( ( portTickType ) 0 ) +#define mainBAUD_RATE ( ( unsigned portLONG ) 57600 ) + +/* + * The task function for the "Check" task. + */ +static portTASK_FUNCTION_PROTO( vErrorChecks, pvParameters ); + +/* + * Checks the unique counts of other tasks to ensure they are still operational. + * Returns pdTRUE if an error is detected, otherwise pdFALSE. + */ +static portCHAR prvCheckOtherTasksAreStillRunning( void ); + +/*-----------------------------------------------------------*/ + +/* Creates the tasks, then starts the scheduler. */ +void main( void ) +{ + /* Initialise the required hardware. */ + vParTestInitialise(); + + /* Send a character so we have some visible feedback of a reset. */ + xSerialPortInitMinimal( mainBAUD_RATE, mainCOMMS_QUEUE_LENGTH ); + xSerialPutChar( NULL, 'X', mainNO_BLOCK ); + + /* Start the standard demo tasks found in the demo\common directory. */ + vStartIntegerMathTasks( mainINTEGER_PRIORITY); + vStartDynamicPriorityTasks(); + vStartLEDFlashTasks( mainLED_FLASH_PRIORITY ); + + /* Start the check task defined in this file. */ + xTaskCreate( vErrorChecks, ( const portCHAR * const ) "Check", portMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Start the scheduler. Will never return here. */ + vTaskStartScheduler( ); + + while(1) /* This point should never be reached. */ + { + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vErrorChecks, pvParameters ) +{ + portTickType xLastCheckTime; + portTickType xDelayTime = mainNO_ERROR_CHECK_PERIOD; + portCHAR cErrorOccurred; + + /* We need to initialise xLastCheckTime prior to the first call to + vTaskDelayUntil(). */ + xLastCheckTime = xTaskGetTickCount(); + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. */ + for( ;; ) + { + /* Wait until it is time to check the other tasks again. */ + vTaskDelayUntil( &xLastCheckTime, xDelayTime ); + + /* Check all the other tasks are running, and running without ever + having an error. */ + cErrorOccurred = prvCheckOtherTasksAreStillRunning(); + + /* If an error was detected increase the frequency of the LED flash. */ + if( cErrorOccurred == pdTRUE ) + { + xDelayTime = mainERROR_CHECK_PERIOD; + } + + /* Flash the LED for visual feedback. */ + vParTestToggleLED( mainCHECK_TASK_LED ); + } +} + +/*-----------------------------------------------------------*/ + +static portCHAR prvCheckOtherTasksAreStillRunning( void ) +{ + portCHAR cErrorHasOccurred = ( portCHAR ) pdFALSE; + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + cErrorHasOccurred = ( portCHAR ) pdTRUE; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + cErrorHasOccurred = ( portCHAR ) pdTRUE; + } + + return cErrorHasOccurred; +} +/*-----------------------------------------------------------*/ + + diff --git a/20080212/Demo/PIC18_WizC/Demo5/Demo5.PC b/20080212/Demo/PIC18_WizC/Demo5/Demo5.PC new file mode 100644 index 000000000..479208633 --- /dev/null +++ b/20080212/Demo/PIC18_WizC/Demo5/Demo5.PC @@ -0,0 +1,536 @@ +[F29012293] +x=0 +y=114 +[F10478061] +x=0 +y=48 +[F15207742] +x=0 +y=48 +[F28446561] +x=0 +y=0 +[F30163742] +x=38 +y=56 +[F29565566] +x=0 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either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + + TickRate reduced to 250Hz. + + + configIDLE_SHOULD_YIELD added. + +Changes from V3.0.1 +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION ( 1 ) +#define configUSE_IDLE_HOOK ( 0 ) +#define configUSE_TICK_HOOK ( 0 ) +#define configTICK_RATE_HZ ( 250 ) +#define configMAX_PRIORITIES ( 3 ) +#define configMINIMAL_STACK_SIZE portMINIMAL_STACK_SIZE +#define configMAX_TASK_NAME_LEN ( 3 ) +#define configUSE_TRACE_FACILITY ( 0 ) +#define configUSE_16_BIT_TICKS ( 1 ) +#define configIDLE_SHOULD_YIELD ( 1 ) + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the component, or zero +to exclude the component. */ + +/* Include/exclude the stated API function. */ +#define INCLUDE_vTaskPrioritySet ( 0 ) +#define INCLUDE_uxTaskPriorityGet ( 0 ) +#define INCLUDE_vTaskDelete ( 0 ) +#define INCLUDE_vTaskCleanUpResources ( 0 ) +#define INCLUDE_vTaskSuspend ( 0 ) +#define INCLUDE_vTaskDelayUntil ( 1 ) +#define INCLUDE_vTaskDelay ( 0 ) + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/PIC18_WizC/Demo5/MallocConfig.h b/20080212/Demo/PIC18_WizC/Demo5/MallocConfig.h new file mode 100644 index 000000000..195258b51 --- /dev/null +++ b/20080212/Demo/PIC18_WizC/Demo5/MallocConfig.h @@ -0,0 +1,41 @@ +#ifndef _MALLOC_SETTINGS_H +#define _MALLOC_SETTINGS_H +/********************************************************************* +** Title: Dynamic memory (de-)allocation library for wizC. +** +** Author: Marcel van Lieshout +** +** Copyright: (c) 2005, HMCS, Marcel van Lieshout +** +** License: This software is released to the public domain and comes +** without warranty and/or guarantees of any kind. You have +** the right to use, copy, modify and/or (re-)distribute the +** software as long as the reference to the author is +** maintained in the software and a reference to the author +** is included in any documentation of each product in which +** this library (in it's original or in a modified form) +** is used. +*********************************************************************/ + +/********************************************************************* +** The model to use +*********************************************************************/ +//#define MALLOC_SMALL +#define MALLOC_LARGE + +/********************************************************************* +** The size of the heap +*********************************************************************/ +#define MALLOC_HEAP_SIZE (3200) + +/********************************************************************* +** Should released memory be scribbled with 0x55 before releasing it? +*********************************************************************/ +//#define MALLOC_SCRIBBLE + +/******************************************************************** +** Enable Debug-mode? +*********************************************************************/ +//#define MALLOC_DEBUG + +#endif /* _MALLOC_SETTINGS_H */ diff --git a/20080212/Demo/PIC18_WizC/Demo5/WIZCmake.h b/20080212/Demo/PIC18_WizC/Demo5/WIZCmake.h new file mode 100644 index 000000000..b1ea6f5d4 --- /dev/null +++ b/20080212/Demo/PIC18_WizC/Demo5/WIZCmake.h @@ -0,0 +1,63 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + + Several modules predefined to avoid linker problems + +Changes from V3.0.1 +*/ + +#ifndef _memcpy + #define _memcpy 1 +#endif + +#ifndef _memset + #define _memset 1 +#endif + +#ifndef _strncpy + #define _strncpy 1 +#endif + + +#pragma wizcpp searchpath <../../Common/Include/> diff --git a/20080212/Demo/PIC18_WizC/Demo5/fuses.c b/20080212/Demo/PIC18_WizC/Demo5/fuses.c new file mode 100644 index 000000000..c9552b350 --- /dev/null +++ b/20080212/Demo/PIC18_WizC/Demo5/fuses.c @@ -0,0 +1,68 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + +Changes from V3.0.1 +*/ + +/* +** Here are the configuration words set. See the PIC datasheet +** and the wizC manual for an explanation +*/ +#include + +/* +** These fuses are for PIC18F4620 +*/ +#pragma __config _CONFIG1H,_IESO_OFF_1H & _FCMEN_OFF_1H & _OSC_HSPLL_1H +#pragma __config _CONFIG2L,_BORV_21_2L & _BOREN_SBORDIS_2L & _PWRT_ON_2L +#pragma __config _CONFIG2H,_WDTPS_32768_2H & _WDT_OFF_2H +#pragma __config _CONFIG3H,_MCLRE_ON_3H & _LPT1OSC_OFF_3H & _PBADEN_OFF_3H & _CCP2MX_PORTC_3H +#pragma __config _CONFIG4L,_DEBUG_OFF_4L & _XINST_OFF_4L & _LVP_OFF_4L & _STVREN_OFF_4L +#pragma __config _CONFIG5L,_CP3_OFF_5L & _CP2_OFF_5L & _CP1_OFF_5L & _CP0_OFF_5L +#pragma __config _CONFIG5H,_CPD_OFF_5H & _CPB_OFF_5H +#pragma __config _CONFIG6L,_WRT3_OFF_6L & _WRT2_OFF_6L & _WRT1_OFF_6L & _WRT0_OFF_6L +#pragma __config _CONFIG6H,_WRTD_OFF_6H & _WRTB_OFF_6H & _WRTC_OFF_6H +#pragma __config _CONFIG7L,_EBTR3_OFF_7L & _EBTR2_OFF_7L & _EBTR1_OFF_7L & _EBTR0_OFF_7L +#pragma __config _CONFIG7H,_EBTRB_OFF_7H diff --git a/20080212/Demo/PIC18_WizC/Demo5/interrupt.c b/20080212/Demo/PIC18_WizC/Demo5/interrupt.c new file mode 100644 index 000000000..1e2a5749b --- /dev/null +++ b/20080212/Demo/PIC18_WizC/Demo5/interrupt.c @@ -0,0 +1,128 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + + Added functionality to only call vTaskSwitchContext() once + when handling multiple interruptsources in a single interruptcall. + + + Included Filenames changed to a .c extension to allow stepping through + code using F7. + +Changes from V3.0.1 +*/ + +#include + +/* Scheduler include files. */ +#include +#include +#include + +static bit uxSwitchRequested; + +/* + * Vector for the ISR. + */ +void pointed Interrupt() +{ + /* + * Save the context of the current task. + */ + portSAVE_CONTEXT( portINTERRUPTS_FORCED ); + + /* + * No contextswitch requested yet + */ + uxSwitchRequested = pdFALSE; + + /* + * Was the interrupt the FreeRTOS SystemTick? + */ + #include + +/******************************************************************************* +** DO NOT MODIFY ANYTHING ABOVE THIS LINE +******************************************************************************** +** Enter the includes for the ISR-code of the FreeRTOS drivers below. +** +** You cannot use local variables. Alternatives are: +** - Use static variables (Global RAM usage increases) +** - Call a function (Additional cycles are needed) +** - Use unused SFR's (preferred, no additional overhead) +** See "../Serial/isrSerialTx.c" for an example of this last option +*******************************************************************************/ + + + + /* + * Was the interrupt a byte being received? + */ + #include "../Serial/isrSerialRx.c" + + + /* + * Was the interrupt the Tx register becoming empty? + */ + #include "../Serial/isrSerialTx.c" + + + +/******************************************************************************* +** DO NOT MODIFY ANYTHING BELOW THIS LINE +*******************************************************************************/ + /* + * Was a contextswitch requested by one of the + * interrupthandlers? + */ + if ( uxSwitchRequested ) + { + vTaskSwitchContext(); + } + + /* + * Restore the context of the (possibly other) task. + */ + portRESTORE_CONTEXT(); + + #pragma asmline retfie 0 +} diff --git a/20080212/Demo/PIC18_WizC/Demo5/main.c b/20080212/Demo/PIC18_WizC/Demo5/main.c new file mode 100644 index 000000000..e43f586bb --- /dev/null +++ b/20080212/Demo/PIC18_WizC/Demo5/main.c @@ -0,0 +1,188 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + +Changes from V3.0.1 +*/ + +/* + * Instead of the normal single demo application, the PIC18F demo is split + * into several smaller programs of which this is the fifth. This enables the + * demo's to be executed on the RAM limited PIC-devices. + * + * The Demo5 project is configured for a PIC18F4620 device. Main.c starts 13 + * tasks (including the idle task). See the indicated files in the demo/common + * directory for more information. + * + * demo/common/minimal/flop.c: Creates 8 tasks + * demo/common/minimal/flash.c: Creates 3 tasks + * + * Main.c also creates a check task. This periodically checks that all the + * other tasks are still running and have not experienced any unexpected + * results. If all the other tasks are executing correctly an LED is flashed + * once every mainCHECK_PERIOD milliseconds. If any of the tasks have not + * executed, or report an error, the frequency of the LED flash will increase + * to mainERROR_FLASH_RATE. + * + * On entry to main an 'X' is transmitted. Monitoring the serial port using a + * dumb terminal allows for verification that the device is not continuously + * being reset (no more than one 'X' should be transmitted). + * + * http://www.FreeRTOS.org contains important information on the use of the + * wizC PIC18F port. + */ + +/* Scheduler include files. */ +#include +#include + +/* Demo app include files. */ +#include "flop.h" +#include "flash.h" +#include "partest.h" +#include "serial.h" + +/* The period between executions of the check task before and after an error +has been discovered. If an error has been discovered the check task runs +more frequently - increasing the LED flash rate. */ +#define mainNO_ERROR_CHECK_PERIOD ( ( portTickType ) 10000 / portTICK_RATE_MS ) +#define mainERROR_CHECK_PERIOD ( ( portTickType ) 1000 / portTICK_RATE_MS ) +#define mainCHECK_TASK_LED ( ( unsigned portCHAR ) 3 ) + +/* Priority definitions for some of the tasks. Other tasks just use the idle +priority. */ +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 2 ) +#define mainLED_FLASH_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 1 ) + +/* Constants required for the communications. Only one character is ever +transmitted. */ +#define mainCOMMS_QUEUE_LENGTH ( ( unsigned portCHAR ) 5 ) +#define mainNO_BLOCK ( ( portTickType ) 0 ) +#define mainBAUD_RATE ( ( unsigned portLONG ) 57600 ) + +/* + * The task function for the "Check" task. + */ +static portTASK_FUNCTION_PROTO( vErrorChecks, pvParameters ); + +/* + * Checks the unique counts of other tasks to ensure they are still operational. + * Returns pdTRUE if an error is detected, otherwise pdFALSE. + */ +static portCHAR prvCheckOtherTasksAreStillRunning( void ); + +/*-----------------------------------------------------------*/ + +/* Creates the tasks, then starts the scheduler. */ +void main( void ) +{ + /* Initialise the required hardware. */ + vParTestInitialise(); + + /* Send a character so we have some visible feedback of a reset. */ + xSerialPortInitMinimal( mainBAUD_RATE, mainCOMMS_QUEUE_LENGTH ); + xSerialPutChar( NULL, 'X', mainNO_BLOCK ); + + /* Start a few of the standard demo tasks found in the demo\common directory. */ + vStartMathTasks( tskIDLE_PRIORITY ); + vStartLEDFlashTasks( mainLED_FLASH_PRIORITY ); + + /* Start the check task defined in this file. */ + xTaskCreate( vErrorChecks, ( const portCHAR * const ) "Check", portMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Start the scheduler. Will never return here. */ + vTaskStartScheduler(); + + while(1) /* This point should never be reached. */ + { + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vErrorChecks, pvParameters ) +{ +portTickType xLastCheckTime; +portTickType xDelayTime = mainNO_ERROR_CHECK_PERIOD; +portCHAR cErrorOccurred; + + /* We need to initialise xLastCheckTime prior to the first call to + vTaskDelayUntil(). */ + xLastCheckTime = xTaskGetTickCount(); + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. */ + for( ;; ) + { + /* Wait until it is time to check the other tasks again. */ + vTaskDelayUntil( &xLastCheckTime, xDelayTime ); + + /* Check all the other tasks are running, and running without ever + having an error. */ + cErrorOccurred = prvCheckOtherTasksAreStillRunning(); + + /* If an error was detected increase the frequency of the LED flash. */ + if( cErrorOccurred == pdTRUE ) + { + xDelayTime = mainERROR_CHECK_PERIOD; + } + + /* Flash the LED for visual feedback. */ + vParTestToggleLED( mainCHECK_TASK_LED ); + } +} +/*-----------------------------------------------------------*/ + +static portCHAR prvCheckOtherTasksAreStillRunning( void ) +{ + portCHAR cErrorHasOccurred = ( portCHAR ) pdFALSE; + + if( xAreMathsTaskStillRunning() != pdTRUE ) + { + cErrorHasOccurred = ( portCHAR ) pdTRUE; + } + return cErrorHasOccurred; +} +/*-----------------------------------------------------------*/ + + diff --git a/20080212/Demo/PIC18_WizC/Demo6/Demo6.PC b/20080212/Demo/PIC18_WizC/Demo6/Demo6.PC new file mode 100644 index 000000000..5f5f39862 --- /dev/null +++ b/20080212/Demo/PIC18_WizC/Demo6/Demo6.PC @@ -0,0 +1,632 @@ +[F29012549] +x=0 +y=111 +[F15207742] +x=0 +y=48 +[F28463201] +x=0 +y=0 +[F30163998] +x=60 +y=44 +[F29565822] +x=2 +y=23 +[F26101515] +x=0 +y=269 +[ProjectGroup] +nFiles=1 +FileName0=Demo6.PC +[Project] +nFiles=6 +UseAD=0 +CompatOpts=0 +AutoHead= +IdentifierPrint=0 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FILES\FED\PIXIE\Libs\LibsUser\LIBFREERTOS\Modules\tasks.c +Files16=C:\PROGRAM FILES\FED\PIXIE\Libs\LibsUser\LIBFREERTOS\Modules\tasks.c +Files17=C:\PROGRAM FILES\FED\PIXIE\Libs\LibsUser\LIBFREERTOS\Modules\port.c +Files18=C:\PROGRAM FILES\FED\PIXIE\Libs\LibsUser\LIBMALLOC\Malloc.c +Files19=C:\PROGRAM FILES\FED\PIXIE\Libs\LIBSTRINGS\STRINGS16.C +[PinConnections] +nPins=0 +[AssCode] +ProcType=18F4620 +[Information] +Column0=-1 +Column1=8 +Column2=4 +Column3=16 +Column4=-1 +Column5=50 +MemoHeight=154 +WindowState=0 +Top=418 +Left=339 +Width=339 +Height=209 +[F29012805] +x=0 +y=110 +[F29217358] +x=0 +y=163 +[F30243933] +x=0 +y=4673 +[F29217125] +x=17 +y=37 +[F30827659] +x=0 +y=4704 +[F20376480] +x=0 +y=1329 +[F30164254] +x=57 +y=45 +[F29566078] +x=30 +y=28 +[Window4098] +aHeight=0 +aWidth=0 +Height=38 +Width=25 +isMinimised=0 +isVisible=1 +ShowBorder=0 +ShowCaption=0 +Sizeable=1 +x=10 +y=299 +Left=13 +Top=137 +Group=0 +Page=-1 +[ExtDev4098] +Type=4 +TypeN=PushButton +Ports0=2 +Bit0=6 +ConLev0=-1 +ConPars0_0=1 +Ports1=2 +Bit1=7 +ConLev1=-1 +Pars0=0 +Pars1=1 +Name=PushButton +FileName= +Layer=0 +Pars2=0 +[F28479841] +x=0 +y=78 +[F30090026] +x=13 +y=50 +[F29453097] +x=0 +y=144 +[F20121086] +x=23 +y=71 +[F20258362] +x=0 +y=7159 +[F20414028] +x=0 +y=6113 +[F10478061] +x=0 +y=48 +[F29011525] +x=0 +y=145 +[F28396641] +x=10 +y=9 +[F30162974] +x=0 +y=0 +[F29564798] +x=30 +y=28 +[F30146592] +x=0 +y=59 +[F20220814] +x=0 +y=497 +[F20539803] +x=0 +y=228 +[F15568046] +x=1 +y=293 +[Window4099] +aHeight=0 +aWidth=0 +Height=38 +Width=25 +isMinimised=0 +isVisible=1 +ShowBorder=0 +ShowCaption=0 +Sizeable=1 +x=10 +y=299 +Left=13 +Top=137 +Group=0 +Page=-1 +[ExtDev4099] +Type=4 +TypeN=PushButton +Ports0=2 +Bit0=6 +ConLev0=-1 +ConPars0_0=1 +Ports1=2 +Bit1=7 +ConLev1=-1 +Pars0=0 +Pars1=1 +Name=PushButton +FileName= +Layer=0 +[F15679330] +x=0 +y=112 +[F30165122] +x=0 +y=4469 +[F30427679] +x=0 +y=46 +[F30394911] +x=0 +y=0 +[F20441499] +x=0 +y=0 +[F29730335] +x=0 +y=78 +[F24752775] +x=40 +y=52 +[F24752903] +x=40 +y=52 +[F29013061] +x=0 +y=113 +[F27123467] +x=55 +y=67 +[F28496481] +x=8 +y=29 +[F20528681] +x=18 +y=94 +[F28479879] +x=49 +y=2522 +[F28931976] +x=0 +y=0 +[F29801213] +x=24 +y=36 +[F29801181] +x=24 +y=36 +[F24754146] +x=0 +y=0 +[F20122654] +x=0 +y=44 +[F20558577] +x=6 +y=5403 +[F29471871] +x=13 +y=4972 +[F15787712] +x=0 +y=47 diff --git a/20080212/Demo/PIC18_WizC/Demo6/FreeRTOSConfig.h b/20080212/Demo/PIC18_WizC/Demo6/FreeRTOSConfig.h new file mode 100644 index 000000000..2596c2dfc --- /dev/null +++ b/20080212/Demo/PIC18_WizC/Demo6/FreeRTOSConfig.h @@ -0,0 +1,92 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + + TickRate reduced to 250Hz. + + + configIDLE_SHOULD_YIELD added. + +Changes from V3.0.1 +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION ( 1 ) +#define configUSE_IDLE_HOOK ( 0 ) +#define configUSE_TICK_HOOK ( 0 ) +#define configTICK_RATE_HZ ( 250 ) +#define configMAX_PRIORITIES ( 3 ) +#define configMINIMAL_STACK_SIZE portMINIMAL_STACK_SIZE +#define configMAX_TASK_NAME_LEN ( 3 ) +#define configUSE_TRACE_FACILITY ( 0 ) +#define configUSE_16_BIT_TICKS ( 1 ) +#define configIDLE_SHOULD_YIELD ( 1 ) + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the component, or zero +to exclude the component. */ + +/* Include/exclude the stated API function. */ +#define INCLUDE_vTaskPrioritySet ( 0 ) +#define INCLUDE_uxTaskPriorityGet ( 0 ) +#define INCLUDE_vTaskDelete ( 0 ) +#define INCLUDE_vTaskCleanUpResources ( 0 ) +#define INCLUDE_vTaskSuspend ( 0 ) +#define INCLUDE_vTaskDelayUntil ( 1 ) +#define INCLUDE_vTaskDelay ( 1 ) + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/PIC18_WizC/Demo6/MallocConfig.h b/20080212/Demo/PIC18_WizC/Demo6/MallocConfig.h new file mode 100644 index 000000000..195258b51 --- /dev/null +++ b/20080212/Demo/PIC18_WizC/Demo6/MallocConfig.h @@ -0,0 +1,41 @@ +#ifndef _MALLOC_SETTINGS_H +#define _MALLOC_SETTINGS_H +/********************************************************************* +** Title: Dynamic memory (de-)allocation library for wizC. +** +** Author: Marcel van Lieshout +** +** Copyright: (c) 2005, HMCS, Marcel van Lieshout +** +** License: This software is released to the public domain and comes +** without warranty and/or guarantees of any kind. You have +** the right to use, copy, modify and/or (re-)distribute the +** software as long as the reference to the author is +** maintained in the software and a reference to the author +** is included in any documentation of each product in which +** this library (in it's original or in a modified form) +** is used. +*********************************************************************/ + +/********************************************************************* +** The model to use +*********************************************************************/ +//#define MALLOC_SMALL +#define MALLOC_LARGE + +/********************************************************************* +** The size of the heap +*********************************************************************/ +#define MALLOC_HEAP_SIZE (3200) + +/********************************************************************* +** Should released memory be scribbled with 0x55 before releasing it? +*********************************************************************/ +//#define MALLOC_SCRIBBLE + +/******************************************************************** +** Enable Debug-mode? +*********************************************************************/ +//#define MALLOC_DEBUG + +#endif /* _MALLOC_SETTINGS_H */ diff --git a/20080212/Demo/PIC18_WizC/Demo6/WIZCmake.h b/20080212/Demo/PIC18_WizC/Demo6/WIZCmake.h new file mode 100644 index 000000000..b1ea6f5d4 --- /dev/null +++ b/20080212/Demo/PIC18_WizC/Demo6/WIZCmake.h @@ -0,0 +1,63 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + + Several modules predefined to avoid linker problems + +Changes from V3.0.1 +*/ + +#ifndef _memcpy + #define _memcpy 1 +#endif + +#ifndef _memset + #define _memset 1 +#endif + +#ifndef _strncpy + #define _strncpy 1 +#endif + + +#pragma wizcpp searchpath <../../Common/Include/> diff --git a/20080212/Demo/PIC18_WizC/Demo6/fuses.c b/20080212/Demo/PIC18_WizC/Demo6/fuses.c new file mode 100644 index 000000000..c9552b350 --- /dev/null +++ b/20080212/Demo/PIC18_WizC/Demo6/fuses.c @@ -0,0 +1,68 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + +Changes from V3.0.1 +*/ + +/* +** Here are the configuration words set. See the PIC datasheet +** and the wizC manual for an explanation +*/ +#include + +/* +** These fuses are for PIC18F4620 +*/ +#pragma __config _CONFIG1H,_IESO_OFF_1H & _FCMEN_OFF_1H & _OSC_HSPLL_1H +#pragma __config _CONFIG2L,_BORV_21_2L & _BOREN_SBORDIS_2L & _PWRT_ON_2L +#pragma __config _CONFIG2H,_WDTPS_32768_2H & _WDT_OFF_2H +#pragma __config _CONFIG3H,_MCLRE_ON_3H & _LPT1OSC_OFF_3H & _PBADEN_OFF_3H & _CCP2MX_PORTC_3H +#pragma __config _CONFIG4L,_DEBUG_OFF_4L & _XINST_OFF_4L & _LVP_OFF_4L & _STVREN_OFF_4L +#pragma __config _CONFIG5L,_CP3_OFF_5L & _CP2_OFF_5L & _CP1_OFF_5L & _CP0_OFF_5L +#pragma __config _CONFIG5H,_CPD_OFF_5H & _CPB_OFF_5H +#pragma __config _CONFIG6L,_WRT3_OFF_6L & _WRT2_OFF_6L & _WRT1_OFF_6L & _WRT0_OFF_6L +#pragma __config _CONFIG6H,_WRTD_OFF_6H & _WRTB_OFF_6H & _WRTC_OFF_6H +#pragma __config _CONFIG7L,_EBTR3_OFF_7L & _EBTR2_OFF_7L & _EBTR1_OFF_7L & _EBTR0_OFF_7L +#pragma __config _CONFIG7H,_EBTRB_OFF_7H diff --git a/20080212/Demo/PIC18_WizC/Demo6/interrupt.c b/20080212/Demo/PIC18_WizC/Demo6/interrupt.c new file mode 100644 index 000000000..1e2a5749b --- /dev/null +++ b/20080212/Demo/PIC18_WizC/Demo6/interrupt.c @@ -0,0 +1,128 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + + Added functionality to only call vTaskSwitchContext() once + when handling multiple interruptsources in a single interruptcall. + + + Included Filenames changed to a .c extension to allow stepping through + code using F7. + +Changes from V3.0.1 +*/ + +#include + +/* Scheduler include files. */ +#include +#include +#include + +static bit uxSwitchRequested; + +/* + * Vector for the ISR. + */ +void pointed Interrupt() +{ + /* + * Save the context of the current task. + */ + portSAVE_CONTEXT( portINTERRUPTS_FORCED ); + + /* + * No contextswitch requested yet + */ + uxSwitchRequested = pdFALSE; + + /* + * Was the interrupt the FreeRTOS SystemTick? + */ + #include + +/******************************************************************************* +** DO NOT MODIFY ANYTHING ABOVE THIS LINE +******************************************************************************** +** Enter the includes for the ISR-code of the FreeRTOS drivers below. +** +** You cannot use local variables. Alternatives are: +** - Use static variables (Global RAM usage increases) +** - Call a function (Additional cycles are needed) +** - Use unused SFR's (preferred, no additional overhead) +** See "../Serial/isrSerialTx.c" for an example of this last option +*******************************************************************************/ + + + + /* + * Was the interrupt a byte being received? + */ + #include "../Serial/isrSerialRx.c" + + + /* + * Was the interrupt the Tx register becoming empty? + */ + #include "../Serial/isrSerialTx.c" + + + +/******************************************************************************* +** DO NOT MODIFY ANYTHING BELOW THIS LINE +*******************************************************************************/ + /* + * Was a contextswitch requested by one of the + * interrupthandlers? + */ + if ( uxSwitchRequested ) + { + vTaskSwitchContext(); + } + + /* + * Restore the context of the (possibly other) task. + */ + portRESTORE_CONTEXT(); + + #pragma asmline retfie 0 +} diff --git a/20080212/Demo/PIC18_WizC/Demo6/main.c b/20080212/Demo/PIC18_WizC/Demo6/main.c new file mode 100644 index 000000000..908b16325 --- /dev/null +++ b/20080212/Demo/PIC18_WizC/Demo6/main.c @@ -0,0 +1,180 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + +Changes from V3.0.1 +*/ + +/* + * Instead of the normal single demo application, the PIC18F demo is split + * into several smaller programs of which this is the sixth. This enables the + * demo's to be executed on the RAM limited PIC-devices. + * + * The Demo6 project is configured for a PIC18F4620 device. Main.c starts 4 + * tasks (including the idle task). See the indicated files in the demo/common + * directory for more information. + * + * demo/common/minimal/comtest.c: Creates 2 tasks + * ATTENTION: Comtest needs a loopback-connector on the serial port. + * + * Main.c also creates a check task. This periodically checks that all the + * other tasks are still running and have not experienced any unexpected + * results. If all the other tasks are executing correctly an LED is flashed + * once every mainCHECK_PERIOD milliseconds. If any of the tasks have not + * executed, or report an error, the frequency of the LED flash will increase + * to mainERROR_FLASH_RATE. + * + * http://www.FreeRTOS.org contains important information on the use of the + * wizC PIC18F port. + */ + +/* Scheduler include files. */ +#include +#include + +/* Demo app include files. */ +#include "partest.h" +#include "serial.h" +#include "comtest.h" + +/* The period between executions of the check task before and after an error +has been discovered. If an error has been discovered the check task runs +more frequently - increasing the LED flash rate. */ +#define mainNO_ERROR_CHECK_PERIOD ( ( portTickType ) 10000 / portTICK_RATE_MS ) +#define mainERROR_CHECK_PERIOD ( ( portTickType ) 1000 / portTICK_RATE_MS ) +#define mainCHECK_TASK_LED ( ( unsigned portCHAR ) 3 ) + +/* Priority definitions for some of the tasks. Other tasks just use the idle +priority. */ +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 2 ) +#define mainCOMM_TEST_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 1 ) + +/* The LED that is toggled whenever a character is transmitted. +mainCOMM_TX_RX_LED + 1 will be toggled every time a character is received. */ +#define mainCOMM_TX_RX_LED ( ( unsigned portCHAR ) 0 ) + +/* Constants required for the communications. */ +#define mainBAUD_RATE ( ( unsigned portLONG ) 57600 ) + +/* + * The task function for the "Check" task. + */ +static portTASK_FUNCTION_PROTO( vErrorChecks, pvParameters ); + +/* + * Checks the unique counts of other tasks to ensure they are still operational. + * Returns pdTRUE if an error is detected, otherwise pdFALSE. + */ +static portCHAR prvCheckOtherTasksAreStillRunning( void ); + +/*-----------------------------------------------------------*/ + +/* Creates the tasks, then starts the scheduler. */ +void main( void ) +{ + /* Initialise the required hardware. */ + vParTestInitialise(); + + /* Start a few of the standard demo tasks found in the demo\common directory. */ + vAltStartComTestTasks( mainCOMM_TEST_PRIORITY, mainBAUD_RATE, mainCOMM_TX_RX_LED ); + + /* Start the check task defined in this file. */ + xTaskCreate( vErrorChecks, ( const portCHAR * const ) "Check", portMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Start the scheduler. Will never return here. */ + vTaskStartScheduler(); + + while(1) /* This point should never be reached. */ + { + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vErrorChecks, pvParameters ) +{ +portTickType xLastCheckTime; +portTickType xDelayTime = mainNO_ERROR_CHECK_PERIOD; +portCHAR cErrorOccurred; + + /* We need to initialise xLastCheckTime prior to the first call to + vTaskDelayUntil(). */ + xLastCheckTime = xTaskGetTickCount(); + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. */ + for( ;; ) + { + /* Wait until it is time to check the other tasks again. */ + vTaskDelayUntil( &xLastCheckTime, xDelayTime ); + + /* Check all the other tasks are running, and running without ever + having an error. */ + cErrorOccurred = prvCheckOtherTasksAreStillRunning(); + + /* If an error was detected increase the frequency of the LED flash. */ + if( cErrorOccurred == pdTRUE ) + { + xDelayTime = mainERROR_CHECK_PERIOD; + } + + /* Flash the LED for visual feedback. */ + vParTestToggleLED( mainCHECK_TASK_LED ); + } +} +/*-----------------------------------------------------------*/ + +static portCHAR prvCheckOtherTasksAreStillRunning( void ) +{ + portCHAR cErrorHasOccurred = ( portCHAR ) pdFALSE; + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + cErrorHasOccurred = ( portCHAR ) pdTRUE; + } + + return cErrorHasOccurred; +} +/*-----------------------------------------------------------*/ + + diff --git a/20080212/Demo/PIC18_WizC/Demo7/Demo7.PC b/20080212/Demo/PIC18_WizC/Demo7/Demo7.PC new file mode 100644 index 000000000..a89bd1912 --- /dev/null +++ b/20080212/Demo/PIC18_WizC/Demo7/Demo7.PC @@ -0,0 +1,546 @@ +[F29012549] +x=0 +y=111 +[F15207742] +x=0 +y=48 +[F26101515] +x=0 +y=269 +[F28463201] +x=0 +y=0 +[F20539803] +x=0 +y=233 +[ProjectGroup] +nFiles=1 +FileName0=Demo7.PC +[Project] +nFiles=7 +UseAD=0 +CompatOpts=0 +AutoHead= +IdentifierPrint=0 +TreePrint=0 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index 000000000..8e54bdbd1 --- /dev/null +++ b/20080212/Demo/PIC18_WizC/Demo7/FreeRTOSConfig.h @@ -0,0 +1,92 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + + TickRate reduced to 250Hz. + + + configIDLE_SHOULD_YIELD added. + +Changes from V3.0.1 +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION ( 1 ) +#define configUSE_IDLE_HOOK ( 0 ) +#define configUSE_TICK_HOOK ( 0 ) +#define configTICK_RATE_HZ ( 250 ) +#define configMAX_PRIORITIES ( 4 ) +#define configMINIMAL_STACK_SIZE portMINIMAL_STACK_SIZE +#define configMAX_TASK_NAME_LEN ( 3 ) +#define configUSE_TRACE_FACILITY ( 0 ) +#define configUSE_16_BIT_TICKS ( 1 ) +#define configIDLE_SHOULD_YIELD ( 1 ) + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the component, or zero +to exclude the component. */ + +/* Include/exclude the stated API function. */ +#define INCLUDE_vTaskPrioritySet ( 0 ) +#define INCLUDE_uxTaskPriorityGet ( 0 ) +#define INCLUDE_vTaskDelete ( 1 ) +#define INCLUDE_vTaskCleanUpResources ( 0 ) +#define INCLUDE_vTaskSuspend ( 0 ) +#define INCLUDE_vTaskDelayUntil ( 1 ) +#define INCLUDE_vTaskDelay ( 1 ) + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/PIC18_WizC/Demo7/MallocConfig.h b/20080212/Demo/PIC18_WizC/Demo7/MallocConfig.h new file mode 100644 index 000000000..195258b51 --- /dev/null +++ b/20080212/Demo/PIC18_WizC/Demo7/MallocConfig.h @@ -0,0 +1,41 @@ +#ifndef _MALLOC_SETTINGS_H +#define _MALLOC_SETTINGS_H +/********************************************************************* +** Title: Dynamic memory (de-)allocation library for wizC. +** +** Author: Marcel van Lieshout +** +** Copyright: (c) 2005, HMCS, Marcel van Lieshout +** +** License: This software is released to the public domain and comes +** without warranty and/or guarantees of any kind. You have +** the right to use, copy, modify and/or (re-)distribute the +** software as long as the reference to the author is +** maintained in the software and a reference to the author +** is included in any documentation of each product in which +** this library (in it's original or in a modified form) +** is used. +*********************************************************************/ + +/********************************************************************* +** The model to use +*********************************************************************/ +//#define MALLOC_SMALL +#define MALLOC_LARGE + +/********************************************************************* +** The size of the heap +*********************************************************************/ +#define MALLOC_HEAP_SIZE (3200) + +/********************************************************************* +** Should released memory be scribbled with 0x55 before releasing it? +*********************************************************************/ +//#define MALLOC_SCRIBBLE + +/******************************************************************** +** Enable Debug-mode? +*********************************************************************/ +//#define MALLOC_DEBUG + +#endif /* _MALLOC_SETTINGS_H */ diff --git a/20080212/Demo/PIC18_WizC/Demo7/WIZCmake.h b/20080212/Demo/PIC18_WizC/Demo7/WIZCmake.h new file mode 100644 index 000000000..b1ea6f5d4 --- /dev/null +++ b/20080212/Demo/PIC18_WizC/Demo7/WIZCmake.h @@ -0,0 +1,63 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + + Several modules predefined to avoid linker problems + +Changes from V3.0.1 +*/ + +#ifndef _memcpy + #define _memcpy 1 +#endif + +#ifndef _memset + #define _memset 1 +#endif + +#ifndef _strncpy + #define _strncpy 1 +#endif + + +#pragma wizcpp searchpath <../../Common/Include/> diff --git a/20080212/Demo/PIC18_WizC/Demo7/fuses.c b/20080212/Demo/PIC18_WizC/Demo7/fuses.c new file mode 100644 index 000000000..c9552b350 --- /dev/null +++ b/20080212/Demo/PIC18_WizC/Demo7/fuses.c @@ -0,0 +1,68 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + +Changes from V3.0.1 +*/ + +/* +** Here are the configuration words set. See the PIC datasheet +** and the wizC manual for an explanation +*/ +#include + +/* +** These fuses are for PIC18F4620 +*/ +#pragma __config _CONFIG1H,_IESO_OFF_1H & _FCMEN_OFF_1H & _OSC_HSPLL_1H +#pragma __config _CONFIG2L,_BORV_21_2L & _BOREN_SBORDIS_2L & _PWRT_ON_2L +#pragma __config _CONFIG2H,_WDTPS_32768_2H & _WDT_OFF_2H +#pragma __config _CONFIG3H,_MCLRE_ON_3H & _LPT1OSC_OFF_3H & _PBADEN_OFF_3H & _CCP2MX_PORTC_3H +#pragma __config _CONFIG4L,_DEBUG_OFF_4L & _XINST_OFF_4L & _LVP_OFF_4L & _STVREN_OFF_4L +#pragma __config _CONFIG5L,_CP3_OFF_5L & _CP2_OFF_5L & _CP1_OFF_5L & _CP0_OFF_5L +#pragma __config _CONFIG5H,_CPD_OFF_5H & _CPB_OFF_5H +#pragma __config _CONFIG6L,_WRT3_OFF_6L & _WRT2_OFF_6L & _WRT1_OFF_6L & _WRT0_OFF_6L +#pragma __config _CONFIG6H,_WRTD_OFF_6H & _WRTB_OFF_6H & _WRTC_OFF_6H +#pragma __config _CONFIG7L,_EBTR3_OFF_7L & _EBTR2_OFF_7L & _EBTR1_OFF_7L & _EBTR0_OFF_7L +#pragma __config _CONFIG7H,_EBTRB_OFF_7H diff --git a/20080212/Demo/PIC18_WizC/Demo7/interrupt.c b/20080212/Demo/PIC18_WizC/Demo7/interrupt.c new file mode 100644 index 000000000..1e2a5749b --- /dev/null +++ b/20080212/Demo/PIC18_WizC/Demo7/interrupt.c @@ -0,0 +1,128 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + + Added functionality to only call vTaskSwitchContext() once + when handling multiple interruptsources in a single interruptcall. + + + Included Filenames changed to a .c extension to allow stepping through + code using F7. + +Changes from V3.0.1 +*/ + +#include + +/* Scheduler include files. */ +#include +#include +#include + +static bit uxSwitchRequested; + +/* + * Vector for the ISR. + */ +void pointed Interrupt() +{ + /* + * Save the context of the current task. + */ + portSAVE_CONTEXT( portINTERRUPTS_FORCED ); + + /* + * No contextswitch requested yet + */ + uxSwitchRequested = pdFALSE; + + /* + * Was the interrupt the FreeRTOS SystemTick? + */ + #include + +/******************************************************************************* +** DO NOT MODIFY ANYTHING ABOVE THIS LINE +******************************************************************************** +** Enter the includes for the ISR-code of the FreeRTOS drivers below. +** +** You cannot use local variables. Alternatives are: +** - Use static variables (Global RAM usage increases) +** - Call a function (Additional cycles are needed) +** - Use unused SFR's (preferred, no additional overhead) +** See "../Serial/isrSerialTx.c" for an example of this last option +*******************************************************************************/ + + + + /* + * Was the interrupt a byte being received? + */ + #include "../Serial/isrSerialRx.c" + + + /* + * Was the interrupt the Tx register becoming empty? + */ + #include "../Serial/isrSerialTx.c" + + + +/******************************************************************************* +** DO NOT MODIFY ANYTHING BELOW THIS LINE +*******************************************************************************/ + /* + * Was a contextswitch requested by one of the + * interrupthandlers? + */ + if ( uxSwitchRequested ) + { + vTaskSwitchContext(); + } + + /* + * Restore the context of the (possibly other) task. + */ + portRESTORE_CONTEXT(); + + #pragma asmline retfie 0 +} diff --git a/20080212/Demo/PIC18_WizC/Demo7/main.c b/20080212/Demo/PIC18_WizC/Demo7/main.c new file mode 100644 index 000000000..86fab72e0 --- /dev/null +++ b/20080212/Demo/PIC18_WizC/Demo7/main.c @@ -0,0 +1,194 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + +Changes from V3.0.1 +*/ + +/* + * Instead of the normal single demo application, the PIC18F demo is split + * into several smaller programs of which this is the seventh. This enables the + * demo's to be executed on the RAM limited PIC-devices. + * + * The Demo7 project is configured for a PIC18F4620 device. Main.c starts 10 + * tasks (including the idle task). See the indicated files in the demo/common + * directory for more information. + * + * demo/common/minimal/flash.c: Creates 3 tasks + * demo/common/minimal/death.c: Creates 1 controltask and + * creates/deletes 4 suicidaltasks + * + * Main.c also creates a check task. This periodically checks that all the + * other tasks are still running and have not experienced any unexpected + * results. If all the other tasks are executing correctly an LED is flashed + * once every mainCHECK_PERIOD milliseconds. If any of the tasks have not + * executed, or report an error, the frequency of the LED flash will increase + * to mainERROR_FLASH_RATE. + * + * On entry to main an 'X' is transmitted. Monitoring the serial port using a + * dumb terminal allows for verification that the device is not continuously + * being reset (no more than one 'X' should be transmitted). + * + * http://www.FreeRTOS.org contains important information on the use of the + * wizC PIC18F port. + */ + +/* Scheduler include files. */ +#include +#include + +/* Demo app include files. */ +#include "death.h" +#include "flash.h" +#include "partest.h" +#include "serial.h" + +/* The period between executions of the check task before and after an error +has been discovered. If an error has been discovered the check task runs +more frequently - increasing the LED flash rate. */ +#define mainNO_ERROR_CHECK_PERIOD ( ( portTickType ) 10000 / portTICK_RATE_MS ) +#define mainERROR_CHECK_PERIOD ( ( portTickType ) 1000 / portTICK_RATE_MS ) +#define mainCHECK_TASK_LED ( ( unsigned portCHAR ) 3 ) + +/* Priority definitions for some of the tasks. Other tasks just use the idle +priority. */ +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 2 ) +#define mainLED_FLASH_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 2 ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 1 ) + +/* Constants required for the communications. Only one character is ever +transmitted. */ +#define mainCOMMS_QUEUE_LENGTH ( ( unsigned portCHAR ) 5 ) +#define mainNO_BLOCK ( ( portTickType ) 0 ) +#define mainBAUD_RATE ( ( unsigned portLONG ) 57600 ) + +/* + * The task function for the "Check" task. + */ +static portTASK_FUNCTION_PROTO( vErrorChecks, pvParameters ); + +/* + * Checks the unique counts of other tasks to ensure they are still operational. + * Returns pdTRUE if an error is detected, otherwise pdFALSE. + */ +static portCHAR prvCheckOtherTasksAreStillRunning( void ); + +/*-----------------------------------------------------------*/ + +/* Creates the tasks, then starts the scheduler. */ +void main( void ) +{ + /* Initialise the required hardware. */ + vParTestInitialise(); + + /* Send a character so we have some visible feedback of a reset. */ + xSerialPortInitMinimal( mainBAUD_RATE, mainCOMMS_QUEUE_LENGTH ); + xSerialPutChar( NULL, 'X', mainNO_BLOCK ); + + /* Start a few of the standard demo tasks found in the demo\common directory. */ + vStartLEDFlashTasks( mainLED_FLASH_PRIORITY ); + + /* Start the check task defined in this file. */ + xTaskCreate( vErrorChecks, ( const portCHAR * const ) "Check", portMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* This task has to be created last as it keeps account of the number of tasks + it expects to see running. */ + vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); + + /* Start the scheduler. Will never return here. */ + vTaskStartScheduler(); + + while(1) /* This point should never be reached. */ + { + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vErrorChecks, pvParameters ) +{ +portTickType xLastCheckTime; +portTickType xDelayTime = mainNO_ERROR_CHECK_PERIOD; +portCHAR cErrorOccurred; + + /* We need to initialise xLastCheckTime prior to the first call to + vTaskDelayUntil(). */ + xLastCheckTime = xTaskGetTickCount(); + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. */ + for( ;; ) + { + /* Wait until it is time to check the other tasks again. */ + vTaskDelayUntil( &xLastCheckTime, xDelayTime ); + + /* Check all the other tasks are running, and running without ever + having an error. */ + cErrorOccurred = prvCheckOtherTasksAreStillRunning(); + + /* If an error was detected increase the frequency of the LED flash. */ + if( cErrorOccurred == pdTRUE ) + { + xDelayTime = mainERROR_CHECK_PERIOD; + } + + /* Flash the LED for visual feedback. */ + vParTestToggleLED( mainCHECK_TASK_LED ); + } +} +/*-----------------------------------------------------------*/ + +static portCHAR prvCheckOtherTasksAreStillRunning( void ) +{ + portCHAR cErrorHasOccurred = ( portCHAR ) pdFALSE; + + if( xIsCreateTaskStillRunning() != pdTRUE ) + { + cErrorHasOccurred = ( portCHAR ) pdTRUE; + } + + return cErrorHasOccurred; +} +/*-----------------------------------------------------------*/ + + diff --git a/20080212/Demo/PIC18_WizC/ParTest/ParTest.c b/20080212/Demo/PIC18_WizC/ParTest/ParTest.c new file mode 100644 index 000000000..07796b127 --- /dev/null +++ b/20080212/Demo/PIC18_WizC/ParTest/ParTest.c @@ -0,0 +1,135 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + +Changes from V3.0.1 +*/ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include + +#include "partest.h" + +/*----------------------------------------------------------- + * Simple parallel port IO routines for the FED 40pin demo board. + * The four LED's are connected to D4 to D7. + *-----------------------------------------------------------*/ + +#define partstBIT_AS_OUTPUT ( ( unsigned portSHORT ) 0 ) +#define partstSET_OUTPUT ( ( unsigned portSHORT ) 1 ) +#define partstCLEAR_OUTPUT ( ( unsigned portSHORT ) 0 ) + +#define partstENABLE_GENERAL_IO ( ( unsigned portCHAR ) 7 ) + +/*-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ + /* Set the top four bits of port D to output. */ + bTRD7 = partstBIT_AS_OUTPUT; + bTRD6 = partstBIT_AS_OUTPUT; + bTRD5 = partstBIT_AS_OUTPUT; + bTRD4 = partstBIT_AS_OUTPUT; + + /* Start with all bits off. */ + bRD7 = partstCLEAR_OUTPUT; + bRD6 = partstCLEAR_OUTPUT; + bRD5 = partstCLEAR_OUTPUT; + bRD4 = partstCLEAR_OUTPUT; + + /* Enable the driver. */ + ADCON1 = partstENABLE_GENERAL_IO; + bTRE2 = partstBIT_AS_OUTPUT; + bRE2 = partstSET_OUTPUT; +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portCHAR ucLED, portCHAR cValue ) +{ + /* We are only using the top nibble, so LED 0 corresponds to bit 4. */ + vTaskSuspendAll(); + { + switch( ucLED ) + { + case 3 : bRD7 = ( portSHORT ) cValue; + break; + case 2 : bRD6 = ( portSHORT ) cValue; + break; + case 1 : bRD5 = ( portSHORT ) cValue; + break; + case 0 : bRD4 = ( portSHORT ) cValue; + break; + default : /* There are only 4 LED's. */ + break; + } + } + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portCHAR ucLED ) +{ + /* We are only using the top nibble, so LED 0 corresponds to bit 4. */ + vTaskSuspendAll(); + { + switch( ucLED ) + { + case 3 : bRD7 = !bRD7; + break; + case 2 : bRD6 = !bRD6; + break; + case 1 : bRD5 = !bRD5; + break; + case 0 : bRD4 = !bRD4 ); + break; + default : /* There are only 4 LED's. */ + break; + } + } + xTaskResumeAll(); +} + + + diff --git a/20080212/Demo/PIC18_WizC/serial/isrSerialRx.c b/20080212/Demo/PIC18_WizC/serial/isrSerialRx.c new file mode 100644 index 000000000..e4b596d09 --- /dev/null +++ b/20080212/Demo/PIC18_WizC/serial/isrSerialRx.c @@ -0,0 +1,116 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + + ISRcode pulled inline to reduce stack-usage. + + + Added functionality to only call vTaskSwitchContext() once + when handling multiple interruptsources in a single interruptcall. + + + Filename changed to a .c extension to allow stepping through code + using F7. + +Changes from V3.0.1 +*/ + +#ifndef _FREERTOS_SERIAL_ISRSERIALRX_C +#define _FREERTOS_SERIAL_ISRSERIALRX_C + +#define serCONTINUOUS_RX ( 1 ) +#define serCLEAR_OVERRUN ( 0 ) + +{ + /* + * Was the interrupt a byte being received? + */ + if( bRCIF && bRCIE) + { + /* + * Queue to interface between comms API and interrupt routine. + */ + extern xQueueHandle xRxedChars; + + /* + * Because we are not allowed to use local variables here, + * PRODL is (ab)used as temporary storage. This is allowed + * because this SFR will be restored before exiting the ISR. + */ + extern portCHAR cChar; + #pragma locate cChar &PRODL + + /* + * If there was a framing error, just get and ignore + * the character + */ + if( bFERR ) + { + cChar = RCREG; + } + else + { + /* + * Get the character and post it on the queue of Rxed + * characters. If the post causes a task to wake ask + * for a context switch as the woken task may have a + * higher priority than the task we have interrupted. + */ + cChar = RCREG; + + /* + * Clear any overrun errors. + */ + if( bOERR ) + { + bCREN = serCLEAR_OVERRUN; + bCREN = serCONTINUOUS_RX; + } + + if( xQueueSendFromISR( xRxedChars, ( const void * ) &cChar, pdFALSE ) ) + { + uxSwitchRequested = pdTRUE; + } + } + } +} + +#endif /* _FREERTOS_SERIAL_ISRSERIALRX_C */ diff --git a/20080212/Demo/PIC18_WizC/serial/isrSerialTx.c b/20080212/Demo/PIC18_WizC/serial/isrSerialTx.c new file mode 100644 index 000000000..feac91a18 --- /dev/null +++ b/20080212/Demo/PIC18_WizC/serial/isrSerialTx.c @@ -0,0 +1,109 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + + ISRcode pulled inline to reduce stack-usage. + + + Added functionality to only call vTaskSwitchContext() once + when handling multiple interruptsources in a single interruptcall. + + + Filename changed to a .c extension to allow stepping through code + using F7. + +Changes from V3.0.1 +*/ + +#ifndef _FREERTOS_SERIAL_ISRSERIALTX_C +#define _FREERTOS_SERIAL_ISRSERIALTX_C + +#define serINTERRUPT_DISABLED ( 0 ) + + +{ + /* + * Was the interrupt the Tx register becoming empty? + */ + if( bTXIF && bTXIE) + { + /* + * Queue to interface between comms API and interrupt routine. + */ + extern xQueueHandle xCharsForTx; + + /* + * Because we are not allowed to use local variables here, + * PRODL and PRODH are (ab)used as temporary storage. This + * is allowed because these SFR's will be restored before + * exiting the ISR. + */ + extern portCHAR cChar; + #pragma locate cChar &PRODL + extern portBASE_TYPE pxTaskWoken; + #pragma locate pxTaskWoken &PRODH + + if( xQueueReceiveFromISR( xCharsForTx, &cChar, &pxTaskWoken ) == pdTRUE ) + { + /* + * Send the next character queued for Tx. + */ + TXREG = cChar; + } + else + { + /* + * Queue empty, nothing to send. + */ + bTXIE = serINTERRUPT_DISABLED; + } + + /* + * If we woke another task, ask for a contextswitch + */ + if( pxTaskWoken == pdTRUE ) + { + uxSwitchRequested = pdTRUE; + } + } +} + +#endif /* _FREERTOS_SERIAL_ISRSERIALTX_C */ diff --git a/20080212/Demo/PIC18_WizC/serial/serial.c b/20080212/Demo/PIC18_WizC/serial/serial.c new file mode 100644 index 000000000..5005c2dcb --- /dev/null +++ b/20080212/Demo/PIC18_WizC/serial/serial.c @@ -0,0 +1,187 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + + ISRcode removed. Is now pulled inline to reduce stack-usage. + +Changes from V3.0.1 +*/ + +/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER. */ + +/* Scheduler header files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +#include "serial.h" + +/* Hardware pin definitions. */ +#define serTX_PIN bTRC6 +#define serRX_PIN bTRC7 + +/* Bit/register definitions. */ +#define serINPUT ( 1 ) +#define serOUTPUT ( 0 ) +#define serINTERRUPT_ENABLED ( 1 ) + +/* All ISR's use the PIC18 low priority interrupt. */ +#define serLOW_PRIORITY ( 0 ) + +/*-----------------------------------------------------------*/ + +/* Queues to interface between comms API and interrupt routines. */ +xQueueHandle xRxedChars; +xQueueHandle xCharsForTx; + +/*-----------------------------------------------------------*/ + +xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portCHAR ucQueueLength ) +{ + unsigned portSHORT usSPBRG; + + /* Create the queues used by the ISR's to interface to tasks. */ + xRxedChars = xQueueCreate( ucQueueLength, ( unsigned portBASE_TYPE ) sizeof( portCHAR ) ); + xCharsForTx = xQueueCreate( ucQueueLength, ( unsigned portBASE_TYPE ) sizeof( portCHAR ) ); + + portENTER_CRITICAL(); + + /* Setup the IO pins to enable the USART IO. */ + serTX_PIN = serINPUT; // YES really! See datasheet + serRX_PIN = serINPUT; + + /* Set the TX config register. */ + TXSTA = 0b00100000; + // ||||||||--bit0: TX9D = n/a + // |||||||---bit1: TRMT = ReadOnly + // ||||||----bit2: BRGH = High speed + // |||||-----bit3: SENDB = n/a + // ||||------bit4: SYNC = Asynchronous mode + // |||-------bit5: TXEN = Transmit enable + // ||--------bit6: TX9 = 8-bit transmission + // |---------bit7: CSRC = n/a + + /* Set the Receive config register. */ + RCSTA = 0b10010000; + // ||||||||--bit0: RX9D = ReadOnly + // |||||||---bit1: OERR = ReadOnly + // ||||||----bit2: FERR = ReadOnly + // |||||-----bit3: ADDEN = n/a + // ||||------bit4: CREN = Enable receiver + // |||-------bit5: SREN = n/a + // ||--------bit6: RX9 = 8-bit reception + // |---------bit7: SPEN = Serial port enabled + + /* Calculate the baud rate generator value. + We use low-speed (BRGH=0), the formula is + SPBRG = ( ( FOSC / Desired Baud Rate ) / 64 ) - 1 */ + usSPBRG = ( ( APROCFREQ / ulWantedBaud ) / 64 ) - 1; + if( usSPBRG > 255 ) + { + SPBRG = 255; + } + else + { + SPBRG = usSPBRG; + } + + /* Set the serial interrupts to use the same priority as the tick. */ + bTXIP = serLOW_PRIORITY; + bRCIP = serLOW_PRIORITY; + + /* Enable the Rx interrupt now, the Tx interrupt will get enabled when + we have data to send. */ + bRCIE = serINTERRUPT_ENABLED; + + portEXIT_CRITICAL(); + + /* Unlike other ports, this serial code does not allow for more than one + com port. We therefore don't return a pointer to a port structure and + can instead just return NULL. */ + return NULL; +} +/*-----------------------------------------------------------*/ + +xComPortHandle xSerialPortInit( eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits, unsigned portCHAR ucBufferLength ) +{ + /* This is not implemented in this port. + Use xSerialPortInitMinimal() instead. */ + return NULL; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, portCHAR *pcRxedChar, portTickType xBlockTime ) +{ + /* Get the next character from the buffer. Return false if no characters + are available, or arrive before xBlockTime expires. */ + if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) + { + return ( portCHAR ) pdTRUE; + } + + return ( portCHAR ) pdFALSE; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, portCHAR cOutChar, portTickType xBlockTime ) +{ + /* Return false if after the block time there is no room on the Tx queue. */ + if( xQueueSend( xCharsForTx, ( const void * ) &cOutChar, xBlockTime ) != ( portCHAR ) pdPASS ) + { + return pdFAIL; + } + + /* Turn interrupt on - ensure the compiler only generates a single + instruction for this. */ + bTXIE = serINTERRUPT_ENABLED; + + return pdPASS; +} +/*-----------------------------------------------------------*/ + +void vSerialClose( xComPortHandle xPort ) +{ + /* Not implemented for this port. + To implement, turn off the interrupts and delete the memory + allocated to the queues. */ +} diff --git a/20080212/Demo/PIC24_MPLAB/FreeRTOSConfig.h b/20080212/Demo/PIC24_MPLAB/FreeRTOSConfig.h new file mode 100644 index 000000000..30a1ac10b --- /dev/null +++ b/20080212/Demo/PIC24_MPLAB/FreeRTOSConfig.h @@ -0,0 +1,89 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 0 +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 16000000 ) /* Fosc / 2 */ +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 ) +#define configMINIMAL_STACK_SIZE ( 115 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) 5120 ) +#define configMAX_TASK_NAME_LEN ( 4 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 1 +#define configIDLE_SHOULD_YIELD 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 1 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + +#define configKERNEL_INTERRUPT_PRIORITY 0x01 + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/PIC24_MPLAB/ParTest/ParTest.c b/20080212/Demo/PIC24_MPLAB/ParTest/ParTest.c new file mode 100644 index 000000000..e9ae1bce8 --- /dev/null +++ b/20080212/Demo/PIC24_MPLAB/ParTest/ParTest.c @@ -0,0 +1,113 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* Demo app includes. */ +#include "partest.h" + +#define ptOUTPUT 0 +#define ptALL_OFF 0 + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ + /* The explorer 16 board has LED's on port A. All bits are set as output + so PORTA is read-modified-written directly. */ + TRISA = ptOUTPUT; + PORTA = ptALL_OFF; +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ +unsigned portBASE_TYPE uxLEDBit; + + /* Which port A bit is being modified? */ + uxLEDBit = 1 << uxLED; + + if( xValue ) + { + /* Turn the LED on. */ + portENTER_CRITICAL(); + { + PORTA |= uxLEDBit; + } + portEXIT_CRITICAL(); + } + else + { + /* Turn the LED off. */ + portENTER_CRITICAL(); + { + PORTA &= ~uxLEDBit; + } + portEXIT_CRITICAL(); + } +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned portBASE_TYPE uxLEDBit; + + uxLEDBit = 1 << uxLED; + portENTER_CRITICAL(); + { + /* If the LED is already on - turn it off. If the LED is already + off, turn it on. */ + if( PORTA & uxLEDBit ) + { + PORTA &= ~uxLEDBit; + } + else + { + PORTA |= uxLEDBit; + } + } + portEXIT_CRITICAL(); +} + diff --git a/20080212/Demo/PIC24_MPLAB/RTOSDemo.mcs b/20080212/Demo/PIC24_MPLAB/RTOSDemo.mcs new file mode 100644 index 000000000..ad85eb9d5 --- /dev/null +++ b/20080212/Demo/PIC24_MPLAB/RTOSDemo.mcs @@ -0,0 +1,3 @@ +[Header] +MagicCookie={0b13fe8c-dfe0-40eb-8900-6712719559a7} +Version=1.0 diff --git a/20080212/Demo/PIC24_MPLAB/RTOSDemo.mcw b/20080212/Demo/PIC24_MPLAB/RTOSDemo.mcw new file mode 100644 index 0000000000000000000000000000000000000000..61dc2e940e5bdfad3faa94c8b4487bdb46a5ac43 GIT binary patch literal 154624 zcmeHw3w#vSz5i?yUJ(!?AS&7gQBfgoHV*=q*JiVU)P!uaE8$+23&ZXZwrpnC+1Vt} z6saQBmR7XZSCyjHiqG1L6|7c!Tdlp-inn-6YpZB|7ay(IT5IKgfAiR#&4WzBDE3~K z%KPZhp+jc22N#b5$l~z-00aL-8)=Nc1rz~8fZ@O};4EMUPz)Rcj08pjqk&@qOaWmm zPy!qWj04646M*A^iNFcKiNHy~B;aJ=6yP&}8<-4C0Zs*`0;d6|17`r!fHQ&Vm~>}T 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b/20080212/Demo/PIC24_MPLAB/RTOSDemo_PIC24.mcs new file mode 100644 index 000000000..ad85eb9d5 --- /dev/null +++ b/20080212/Demo/PIC24_MPLAB/RTOSDemo_PIC24.mcs @@ -0,0 +1,3 @@ +[Header] +MagicCookie={0b13fe8c-dfe0-40eb-8900-6712719559a7} +Version=1.0 diff --git a/20080212/Demo/PIC24_MPLAB/lcd.c b/20080212/Demo/PIC24_MPLAB/lcd.c new file mode 100644 index 000000000..ff82a4427 --- /dev/null +++ b/20080212/Demo/PIC24_MPLAB/lcd.c @@ -0,0 +1,217 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* Demo includes. */ +#include "lcd.h" + +/* + * The LCD is written to by more than one task so is controlled by this + * 'gatekeeper' task. This is the only task that is actually permitted to + * access the LCD directly. Other tasks wanting to display a message send + * the message to the gatekeeper. + */ +static void vLCDTask( void *pvParameters ); + +/* + * Setup the peripherals required to communicate with the LCD. + */ +static void prvSetupLCD( void ); + +/* + * Move to the first (0) or second (1) row of the LCD. + */ +static void prvLCDGotoRow( unsigned portSHORT usRow ); + +/* + * Write a string of text to the LCD. + */ +static void prvLCDPutString( portCHAR *pcString ); + +/* + * Clear the LCD. + */ +static void prvLCDClear( void ); + +/*-----------------------------------------------------------*/ + +/* Brief delay to permit the LCD to catch up with commands. */ +#define lcdSHORT_DELAY 3 + +/* SFR that seems to be missing from the standard header files. */ +#define PMAEN *( ( unsigned short * ) 0x60c ) + +/* LCD commands. */ +#define lcdDEFAULT_FUNCTION 0x3c +#define lcdDISPLAY_CONTROL 0x0c +#define lcdCLEAR_DISPLAY 0x01 +#define lcdENTRY_MODE 0x06 + +/* The length of the queue used to send messages to the LCD gatekeeper task. */ +#define lcdQUEUE_SIZE 3 +/*-----------------------------------------------------------*/ + +/* The queue used to send messages to the LCD task. */ +xQueueHandle xLCDQueue; + + +/*-----------------------------------------------------------*/ + +xQueueHandle xStartLCDTask( void ) +{ + /* Create the queue used by the LCD task. Messages for display on the LCD + are received via this queue. */ + xLCDQueue = xQueueCreate( lcdQUEUE_SIZE, sizeof( xLCDMessage ) ); + + /* Start the task that will write to the LCD. The LCD hardware is + initialised from within the task itself so delays can be used. */ + xTaskCreate( vLCDTask, ( signed portCHAR * ) "LCD", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY + 1, NULL ); + + return xLCDQueue; +} +/*-----------------------------------------------------------*/ + +static void prvLCDGotoRow( unsigned portSHORT usRow ) +{ + if( usRow == 0 ) + { + PMADDR = 0x0000; + PMDIN1 = 0x02; + } + else + { + PMADDR = 0x0000; + PMDIN1 = 0xc0; + } + + vTaskDelay( lcdSHORT_DELAY ); +} +/*-----------------------------------------------------------*/ + +static void prvLCDPutString( portCHAR *pcString ) +{ + /* Write out each character with appropriate delay between each. */ + while( *pcString ) + { + PMADDR = 0x0001; + PMDIN1 = *pcString; + pcString++; + vTaskDelay( lcdSHORT_DELAY ); + } +} +/*-----------------------------------------------------------*/ + +static void prvLCDClear( void ) +{ + /* Clear the display. */ + PMADDR = 0x0000; + PMDIN1 = lcdCLEAR_DISPLAY; + vTaskDelay( lcdSHORT_DELAY ); +} +/*-----------------------------------------------------------*/ + +static void prvSetupLCD( void ) +{ + /* Setup the PMP. */ + PMCON = 0x83BF; + PMMODE = 0x3FF; + PMAEN = 1; + PMADDR = 0x0000; + vTaskDelay( lcdSHORT_DELAY ); + + /* Set the default function. */ + PMDIN1 = lcdDEFAULT_FUNCTION; + vTaskDelay( lcdSHORT_DELAY ); + + /* Set the display control. */ + PMDIN1 = lcdDISPLAY_CONTROL; + vTaskDelay( lcdSHORT_DELAY ); + + /* Clear the display. */ + PMDIN1 = lcdCLEAR_DISPLAY; + vTaskDelay( lcdSHORT_DELAY ); + + /* Set the entry mode. */ + PMDIN1 = lcdENTRY_MODE; + vTaskDelay( lcdSHORT_DELAY ); +} +/*-----------------------------------------------------------*/ + +static void vLCDTask( void *pvParameters ) +{ +xLCDMessage xMessage; +unsigned portSHORT usRow = 0; + + /* Initialise the hardware. This uses delays so must not be called prior + to the scheduler being started. */ + prvSetupLCD(); + + /* Welcome message. */ + prvLCDPutString( "www.FreeRTOS.org" ); + + for( ;; ) + { + /* Wait for a message to arrive that requires displaying. */ + while( xQueueReceive( xLCDQueue, &xMessage, portMAX_DELAY ) != pdPASS ); + + /* Clear the current display value. */ + prvLCDClear(); + + /* Switch rows each time so we can see that the display is still being + updated. */ + prvLCDGotoRow( usRow & 0x01 ); + usRow++; + prvLCDPutString( xMessage.pcMessage ); + + /* Delay the requested amount of time to ensure the text just written + to the LCD is not overwritten. */ + vTaskDelay( xMessage.xMinDisplayTime ); + } +} + + + + diff --git a/20080212/Demo/PIC24_MPLAB/lcd.h b/20080212/Demo/PIC24_MPLAB/lcd.h new file mode 100644 index 000000000..738560192 --- /dev/null +++ b/20080212/Demo/PIC24_MPLAB/lcd.h @@ -0,0 +1,64 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef LCD_INC_H +#define LCD_INC_H + +/* Create the task that will control the LCD. Returned is a handle to the queue +on which messages to get written to the LCD should be written. */ +xQueueHandle xStartLCDTask( void ); + +typedef struct +{ + /* The minimum amount of time the message should remain on the LCD without + being overwritten. */ + portTickType xMinDisplayTime; + + /* A pointer to the string to be displayed. */ + portCHAR *pcMessage; + +} xLCDMessage; + + +#endif /* LCD_INC_H */ + + diff --git a/20080212/Demo/PIC24_MPLAB/main.c b/20080212/Demo/PIC24_MPLAB/main.c new file mode 100644 index 000000000..a137350f6 --- /dev/null +++ b/20080212/Demo/PIC24_MPLAB/main.c @@ -0,0 +1,262 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + * Creates all the demo application tasks, then starts the scheduler. The WEB + * documentation provides more details of the standard demo application tasks. + * In addition to the standard demo tasks, the following tasks and tests are + * defined and/or created within this file: + * + * "Fast Interrupt Test" - A high frequency periodic interrupt is generated + * using a free running timer to demonstrate the use of the + * configKERNEL_INTERRUPT_PRIORITY configuration constant. The interrupt + * service routine measures the number of processor clocks that occur between + * each interrupt - and in so doing measures the jitter in the interrupt + * timing. The maximum measured jitter time is latched in the usMaxJitter + * variable, and displayed on the LCD by the 'Check' as described below. + * The fast interrupt is configured and handled in the timer_test.c source + * file. + * + * "LCD" task - the LCD task is a 'gatekeeper' task. It is the only task that + * is permitted to access the LCD directly. Other tasks wishing to write a + * message to the LCD send the message on a queue to the LCD task instead of + * accessing the LCD themselves. The LCD task just blocks on the queue waiting + * for messages - waking and displaying the messages as they arrive. The LCD + * task is defined in lcd.c. + * + * "Check" task - This only executes every three seconds but has the highest + * priority so is guaranteed to get processor time. Its main function is to + * check that all the standard demo tasks are still operational. Should any + * unexpected behaviour within a demo task be discovered the 'check' task will + * write "FAIL #n" to the LCD (via the LCD task). If all the demo tasks are + * executing with their expected behaviour then the check task writes the max + * jitter time to the LCD (again via the LCD task), as described above. + */ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "croutine.h" + +/* Demo application includes. */ +#include "BlockQ.h" +#include "crflash.h" +#include "blocktim.h" +#include "integer.h" +#include "comtest2.h" +#include "partest.h" +#include "lcd.h" +#include "timertest.h" + +/* Demo task priorities. */ +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainCOM_TEST_PRIORITY ( 2 ) + +/* The check task may require a bit more stack as it calls sprintf(). */ +#define mainCHECK_TAKS_STACK_SIZE ( configMINIMAL_STACK_SIZE * 2 ) + +/* The execution period of the check task. */ +#define mainCHECK_TASK_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS ) + +/* The number of flash co-routines to create. */ +#define mainNUM_FLASH_COROUTINES ( 5 ) + +/* Baud rate used by the comtest tasks. */ +#define mainCOM_TEST_BAUD_RATE ( 19200 ) + +/* The LED used by the comtest tasks. mainCOM_TEST_LED + 1 is also used. +See the comtest.c file for more information. */ +#define mainCOM_TEST_LED ( 6 ) + +/* The frequency at which the "fast interrupt test" interrupt will occur. */ +#define mainTEST_INTERRUPT_FREQUENCY ( 20000 ) + +/* The number of processor clocks we expect to occur between each "fast +interrupt test" interrupt. */ +#define mainEXPECTED_CLOCKS_BETWEEN_INTERRUPTS ( configCPU_CLOCK_HZ / mainTEST_INTERRUPT_FREQUENCY ) + +/* The number of nano seconds between each processor clock. */ +#define mainNS_PER_CLOCK ( ( unsigned portSHORT ) ( ( 1.0 / ( double ) configCPU_CLOCK_HZ ) * 1000000000.0 ) ) + +/* Dimension the buffer used to hold the value of the maximum jitter time when +it is converted to a string. */ +#define mainMAX_STRING_LENGTH ( 20 ) + +/*-----------------------------------------------------------*/ + +/* + * The check task as described at the top of this file. + */ +static void vCheckTask( void *pvParameters ); + +/* + * Setup the processor ready for the demo. + */ +static void prvSetupHardware( void ); + +/*-----------------------------------------------------------*/ + +/* The queue used to send messages to the LCD task. */ +static xQueueHandle xLCDQueue; + +/*-----------------------------------------------------------*/ + +/* + * Create the demo tasks then start the scheduler. + */ +int main( void ) +{ + /* Configure any hardware required for this demo. */ + prvSetupHardware(); + + /* Create the standard demo tasks. */ + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vStartFlashCoRoutines( mainNUM_FLASH_COROUTINES ); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); + vCreateBlockTimeTasks(); + + /* Create the test tasks defined within this file. */ + xTaskCreate( vCheckTask, ( signed portCHAR * ) "Check", mainCHECK_TAKS_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Start the task that will control the LCD. This returns the handle + to the queue used to write text out to the task. */ + xLCDQueue = xStartLCDTask(); + + /* Start the high frequency interrupt test. */ + vSetupTimerTest( mainTEST_INTERRUPT_FREQUENCY ); + + /* Finally start the scheduler. */ + vTaskStartScheduler(); + + /* Will only reach here if there is insufficient heap available to start + the scheduler. */ + return 0; +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + vParTestInitialise(); +} +/*-----------------------------------------------------------*/ + +static void vCheckTask( void *pvParameters ) +{ +/* Used to wake the task at the correct frequency. */ +portTickType xLastExecutionTime; + +/* The maximum jitter time measured by the fast interrupt test. */ +extern unsigned portSHORT usMaxJitter ; + +/* Buffer into which the maximum jitter time is written as a string. */ +static portCHAR cStringBuffer[ mainMAX_STRING_LENGTH ]; + +/* The message that is sent on the queue to the LCD task. The first +parameter is the minimum time (in ticks) that the message should be +left on the LCD without being overwritten. The second parameter is a pointer +to the message to display itself. */ +xLCDMessage xMessage = { 0, cStringBuffer }; + +/* Set to pdTRUE should an error be detected in any of the standard demo tasks. */ +unsigned portSHORT usErrorDetected = pdFALSE; + + /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() + works correctly. */ + xLastExecutionTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Wait until it is time for the next cycle. */ + vTaskDelayUntil( &xLastExecutionTime, mainCHECK_TASK_PERIOD ); + + /* Has an error been found in any of the standard demo tasks? */ + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + usErrorDetected = pdTRUE; + sprintf( cStringBuffer, "FAIL #1" ); + } + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + usErrorDetected = pdTRUE; + sprintf( cStringBuffer, "FAIL #2" ); + } + + if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + usErrorDetected = pdTRUE; + sprintf( cStringBuffer, "FAIL #3" ); + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + usErrorDetected = pdTRUE; + sprintf( cStringBuffer, "FAIL #4" ); + } + + if( usErrorDetected == pdFALSE ) + { + /* No errors have been discovered, so display the maximum jitter + timer discovered by the "fast interrupt test". */ + sprintf( cStringBuffer, "%dns max jitter", ( portSHORT ) ( usMaxJitter - mainEXPECTED_CLOCKS_BETWEEN_INTERRUPTS ) * mainNS_PER_CLOCK ); + } + + /* Send the message to the LCD gatekeeper for display. */ + xQueueSend( xLCDQueue, &xMessage, portMAX_DELAY ); + } +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ + /* Schedule the co-routines from within the idle task hook. */ + vCoRoutineSchedule(); +} +/*-----------------------------------------------------------*/ + diff --git a/20080212/Demo/PIC24_MPLAB/p24FJ128GA010.gld b/20080212/Demo/PIC24_MPLAB/p24FJ128GA010.gld new file mode 100644 index 000000000..630a066c9 --- /dev/null +++ b/20080212/Demo/PIC24_MPLAB/p24FJ128GA010.gld @@ -0,0 +1,1333 @@ +/* +** Linker script for PIC24FJ128GA010 +*/ + +OUTPUT_ARCH("24FJ128GA010") +EXTERN(__resetPRI) +EXTERN(__resetALT) + + +/* +** Memory Regions +*/ +MEMORY +{ + data (a!xr) : ORIGIN = 0x800, LENGTH = 0x2000 + reset : ORIGIN = 0x0, LENGTH = 0x4 + ivt : ORIGIN = 0x4, LENGTH = 0xFC + aivt : ORIGIN = 0x104, LENGTH = 0xFC + program (xr) : ORIGIN = 0x200, LENGTH = 0x155FC + config2 : ORIGIN = 0x157FC, LENGTH = 0x2 + config1 : ORIGIN = 0x157FE, LENGTH = 0x2 +} +__IVT_BASE = 0x4; +__AIVT_BASE = 0x104; +__DATA_BASE = 0x800; +__CODE_BASE = 0x200; + + +/* +** ==================== Section Map ====================== +*/ +SECTIONS +{ + /* + ** ========== Program Memory ========== + */ + + + /* + ** Reset Instruction + */ + .reset : + { + SHORT(ABSOLUTE(__reset)); + SHORT(0x04); + SHORT((ABSOLUTE(__reset) >> 16) & 0x7F); + SHORT(0); + } >reset + + + /* + ** Interrupt Vector Tables + ** + ** The primary and alternate tables are loaded + ** here, between sections .reset and .text. + ** Vector table source code appears below. + */ + + + /* + ** User Code and Library Code + */ + .text __CODE_BASE : + { + *(.handle); + *(.libc) *(.libm) *(.libdsp); /* keep together in this order */ + *(.lib*); + *(.text); + } >program + + + /* + ** Configuration Words + */ + __CONFIG2 : + { *(__CONFIG2.sec) } >config2 + __CONFIG1 : + { *(__CONFIG1.sec) } >config1 + + + /* + ** =========== Data Memory =========== + */ + + + /* + ** ICD Debug Exec + ** + ** This section provides optional storage for + ** the ICD2 debugger. Define a global symbol + ** named __ICD2RAM to enable ICD2. This section + ** must be loaded at data address 0x800. + */ + .icd __DATA_BASE (NOLOAD): + { + . += (DEFINED (__ICD2RAM) ? 0x50 : 0 ); + } > data + + + /* + ** Other sections in data memory are not explicitly mapped. + ** Instead they are allocated according to their section + ** attributes, which is most efficient. + ** + ** If a specific arrangement of sections is required + ** (other than what can be achieved using attributes) + ** additional sections may be defined here. See chapter + ** 10.5 in the MPLAB ASM30/LINK30 User's Guide (DS51317) + ** for more information. + */ + + + /* + ** ========== Debug Info ============== + */ + + .comment 0 : { *(.comment) } + + /* + ** DWARF-2 + */ + .debug_info 0 : { *(.debug_info) *(.gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_ranges 0 : { *(.debug_ranges) } + .debug_aranges 0 : { *(.debug_aranges) } + +} /* SECTIONS */ + +/* +** ================= End of Section Map ================ +*/ + +/* +** Section Map for Interrupt Vector Tables +*/ +SECTIONS +{ + +/* +** Interrupt Vector Table +*/ +.ivt __IVT_BASE : + { + LONG( DEFINED(__ReservedTrap0) ? ABSOLUTE(__ReservedTrap0) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__OscillatorFail) ? ABSOLUTE(__OscillatorFail) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__AddressError) ? ABSOLUTE(__AddressError) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__StackError) ? ABSOLUTE(__StackError) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__MathError) ? ABSOLUTE(__MathError) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__ReservedTrap5) ? ABSOLUTE(__ReservedTrap5) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__ReservedTrap6) ? ABSOLUTE(__ReservedTrap6) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__ReservedTrap7) ? ABSOLUTE(__ReservedTrap7) : + ABSOLUTE(__DefaultInterrupt)); + + LONG( DEFINED(__INT0Interrupt) ? ABSOLUTE(__INT0Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__IC1Interrupt) ? ABSOLUTE(__IC1Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__OC1Interrupt) ? ABSOLUTE(__OC1Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__T1Interrupt) ? ABSOLUTE(__T1Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt4) ? ABSOLUTE(__Interrupt4) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__IC2Interrupt) ? ABSOLUTE(__IC2Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__OC2Interrupt) ? ABSOLUTE(__OC2Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__T2Interrupt) ? ABSOLUTE(__T2Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__T3Interrupt) ? ABSOLUTE(__T3Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__SPI1ErrInterrupt) ? ABSOLUTE(__SPI1ErrInterrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__SPI1TInterrupt) ? ABSOLUTE(__SPI1TInterrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__U1RXInterrupt) ? ABSOLUTE(__U1RXInterrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__U1TXInterrupt) ? ABSOLUTE(__U1TXInterrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__ADC1Interrupt) ? ABSOLUTE(__ADC1Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt14) ? ABSOLUTE(__Interrupt14) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt15) ? ABSOLUTE(__Interrupt15) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__SI2C1Interrupt) ? ABSOLUTE(__SI2C1Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__MI2C1Interrupt) ? ABSOLUTE(__MI2C1Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__CompInterrupt) ? ABSOLUTE(__CompInterrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__CNInterrupt) ? ABSOLUTE(__CNInterrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__INT1Interrupt) ? ABSOLUTE(__INT1Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt21) ? ABSOLUTE(__Interrupt21) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt22) ? ABSOLUTE(__Interrupt22) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt23) ? ABSOLUTE(__Interrupt23) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt24) ? ABSOLUTE(__Interrupt24) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__OC3Interrupt) ? ABSOLUTE(__OC3Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__OC4Interrupt) ? ABSOLUTE(__OC4Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__T4Interrupt) ? ABSOLUTE(__T4Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__T5Interrupt) ? ABSOLUTE(__T5Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__INT2Interrupt) ? ABSOLUTE(__INT2Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__U2RXInterrupt) ? ABSOLUTE(__U2RXInterrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__U2TXInterrupt) ? ABSOLUTE(__U2TXInterrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__SPI2ErrInterrupt) ? ABSOLUTE(__SPI2ErrInterrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__SPI2Interrupt) ? ABSOLUTE(__SPI2Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt34) ? ABSOLUTE(__Interrupt34) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt35) ? ABSOLUTE(__Interrupt35) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt36) ? ABSOLUTE(__Interrupt36) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__IC3Interrupt) ? ABSOLUTE(__IC3Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__IC4Interrupt) ? ABSOLUTE(__IC4Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__IC5Interrupt) ? ABSOLUTE(__IC5Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt40) ? ABSOLUTE(__Interrupt40) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__OC5Interrupt) ? ABSOLUTE(__OC5Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt42) ? ABSOLUTE(__Interrupt42) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt43) ? ABSOLUTE(__Interrupt43) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt44) ? ABSOLUTE(__Interrupt44) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__PMPInterrupt) ? ABSOLUTE(__PMPInterrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt46) ? ABSOLUTE(__Interrupt46) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt47) ? ABSOLUTE(__Interrupt47) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt48) ? ABSOLUTE(__Interrupt48) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__SI2C2Interrupt) ? ABSOLUTE(__SI2C2Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__MI2C2Interrupt) ? ABSOLUTE(__MI2C2Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt51) ? ABSOLUTE(__Interrupt51) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt52) ? ABSOLUTE(__Interrupt52) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__INT3Interrupt) ? ABSOLUTE(__INT3Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__INT4Interrupt) ? ABSOLUTE(__INT4Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt55) ? ABSOLUTE(__Interrupt55) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt56) ? ABSOLUTE(__Interrupt56) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt57) ? ABSOLUTE(__Interrupt57) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt58) ? ABSOLUTE(__Interrupt58) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt59) ? ABSOLUTE(__Interrupt59) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt60) ? ABSOLUTE(__Interrupt60) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt61) ? ABSOLUTE(__Interrupt61) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__RTCCInterrupt) ? ABSOLUTE(__RTCCInterrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt63) ? ABSOLUTE(__Interrupt63) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt64) ? ABSOLUTE(__Interrupt64) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__U1ErrInterrupt) ? ABSOLUTE(__U1ErrInterrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__U2ErrInterrupt) ? ABSOLUTE(__U2ErrInterrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__CRCInterrupt) ? ABSOLUTE(__CRCInterrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt68) ? ABSOLUTE(__Interrupt68) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt69) ? ABSOLUTE(__Interrupt69) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt70) ? ABSOLUTE(__Interrupt70) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt71) ? ABSOLUTE(__Interrupt71) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt72) ? ABSOLUTE(__Interrupt72) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt73) ? ABSOLUTE(__Interrupt73) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt74) ? ABSOLUTE(__Interrupt74) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt75) ? ABSOLUTE(__Interrupt75) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt76) ? ABSOLUTE(__Interrupt76) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt77) ? ABSOLUTE(__Interrupt77) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt78) ? ABSOLUTE(__Interrupt78) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt79) ? ABSOLUTE(__Interrupt79) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt80) ? ABSOLUTE(__Interrupt80) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt81) ? ABSOLUTE(__Interrupt81) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt82) ? ABSOLUTE(__Interrupt82) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt83) ? ABSOLUTE(__Interrupt83) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt84) ? ABSOLUTE(__Interrupt84) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt85) ? ABSOLUTE(__Interrupt85) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt86) ? ABSOLUTE(__Interrupt86) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt87) ? ABSOLUTE(__Interrupt87) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt88) ? ABSOLUTE(__Interrupt88) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt89) ? ABSOLUTE(__Interrupt89) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt90) ? ABSOLUTE(__Interrupt90) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt91) ? ABSOLUTE(__Interrupt91) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt92) ? ABSOLUTE(__Interrupt92) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt93) ? ABSOLUTE(__Interrupt93) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt94) ? ABSOLUTE(__Interrupt94) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt95) ? ABSOLUTE(__Interrupt95) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt96) ? ABSOLUTE(__Interrupt96) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt97) ? ABSOLUTE(__Interrupt97) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt98) ? ABSOLUTE(__Interrupt98) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt99) ? ABSOLUTE(__Interrupt99) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt100) ? ABSOLUTE(__Interrupt100) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt101) ? ABSOLUTE(__Interrupt101) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt102) ? ABSOLUTE(__Interrupt102) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt103) ? ABSOLUTE(__Interrupt103) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt104) ? ABSOLUTE(__Interrupt104) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt105) ? ABSOLUTE(__Interrupt105) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt106) ? ABSOLUTE(__Interrupt106) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt107) ? ABSOLUTE(__Interrupt107) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt108) ? ABSOLUTE(__Interrupt108) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt109) ? ABSOLUTE(__Interrupt109) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt110) ? ABSOLUTE(__Interrupt110) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt111) ? ABSOLUTE(__Interrupt111) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt112) ? ABSOLUTE(__Interrupt112) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt113) ? ABSOLUTE(__Interrupt113) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt114) ? ABSOLUTE(__Interrupt114) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt115) ? ABSOLUTE(__Interrupt115) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt116) ? ABSOLUTE(__Interrupt116) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt117) ? ABSOLUTE(__Interrupt117) : + ABSOLUTE(__DefaultInterrupt)); + } >ivt + + +/* +** Alternate Interrupt Vector Table +*/ +.aivt __AIVT_BASE : + { + LONG( DEFINED(__AltReservedTrap0) ? ABSOLUTE(__AltReservedTrap0) : + (DEFINED(__ReservedTrap0) ? ABSOLUTE(__ReservedTrap0) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltOscillatorFail) ? ABSOLUTE(__AltOscillatorFail) : + (DEFINED(__OscillatorFail) ? ABSOLUTE(__OscillatorFail) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltAddressError) ? ABSOLUTE(__AltAddressError) : + (DEFINED(__AddressError) ? ABSOLUTE(__AddressError) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltStackError) ? ABSOLUTE(__AltStackError) : + (DEFINED(__StackError) ? ABSOLUTE(__StackError) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltMathError) ? ABSOLUTE(__AltMathError) : + (DEFINED(__MathError) ? ABSOLUTE(__MathError) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltReservedTrap5) ? ABSOLUTE(__AltReservedTrap5) : + (DEFINED(__ReservedTrap5) ? ABSOLUTE(__ReservedTrap5) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltReservedTrap6) ? ABSOLUTE(__AltReservedTrap6) : + (DEFINED(__ReservedTrap6) ? ABSOLUTE(__ReservedTrap6) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltReservedTrap7) ? ABSOLUTE(__AltReservedTrap7) : + (DEFINED(__ReservedTrap7) ? ABSOLUTE(__ReservedTrap7) : + ABSOLUTE(__DefaultInterrupt))); + + LONG( DEFINED(__AltINT0Interrupt) ? ABSOLUTE(__AltINT0Interrupt) : + (DEFINED(__INT0Interrupt) ? ABSOLUTE(__INT0Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltIC1Interrupt) ? ABSOLUTE(__AltIC1Interrupt) : + (DEFINED(__IC1Interrupt) ? ABSOLUTE(__IC1Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltOC1Interrupt) ? ABSOLUTE(__AltOC1Interrupt) : + (DEFINED(__OC1Interrupt) ? ABSOLUTE(__OC1Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltT1Interrupt) ? ABSOLUTE(__AltT1Interrupt) : + (DEFINED(__T1Interrupt) ? ABSOLUTE(__T1Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt4) ? ABSOLUTE(__AltInterrupt4) : + (DEFINED(__Interrupt4) ? ABSOLUTE(__Interrupt4) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltIC2Interrupt) ? ABSOLUTE(__AltIC2Interrupt) : + (DEFINED(__IC2Interrupt) ? ABSOLUTE(__IC2Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltOC2Interrupt) ? ABSOLUTE(__AltOC2Interrupt) : + (DEFINED(__OC2Interrupt) ? ABSOLUTE(__OC2Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltT2Interrupt) ? ABSOLUTE(__AltT2Interrupt) : + (DEFINED(__T2Interrupt) ? ABSOLUTE(__T2Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltT3Interrupt) ? ABSOLUTE(__AltT3Interrupt) : + (DEFINED(__T3Interrupt) ? ABSOLUTE(__T3Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltSPI1ErrInterrupt) ? ABSOLUTE(__AltSPI1ErrInterrupt) : + (DEFINED(__SPI1ErrInterrupt) ? ABSOLUTE(__SPI1ErrInterrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltSPI1TInterrupt) ? ABSOLUTE(__AltSPI1TInterrupt) : + (DEFINED(__SPI1TInterrupt) ? ABSOLUTE(__SPI1TInterrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltU1RXInterrupt) ? ABSOLUTE(__AltU1RXInterrupt) : + (DEFINED(__U1RXInterrupt) ? ABSOLUTE(__U1RXInterrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltU1TXInterrupt) ? ABSOLUTE(__AltU1TXInterrupt) : + (DEFINED(__U1TXInterrupt) ? ABSOLUTE(__U1TXInterrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltADC1Interrupt) ? ABSOLUTE(__AltADC1Interrupt) : + (DEFINED(__ADC1Interrupt) ? ABSOLUTE(__ADC1Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt14) ? ABSOLUTE(__AltInterrupt14) : + (DEFINED(__Interrupt14) ? ABSOLUTE(__Interrupt14) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt15) ? ABSOLUTE(__AltInterrupt15) : + (DEFINED(__Interrupt15) ? ABSOLUTE(__Interrupt15) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltSI2C1Interrupt) ? ABSOLUTE(__AltSI2C1Interrupt) : + (DEFINED(__SI2C1Interrupt) ? ABSOLUTE(__SI2C1Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltMI2C1Interrupt) ? ABSOLUTE(__AltMI2C1Interrupt) : + (DEFINED(__MI2C1Interrupt) ? ABSOLUTE(__MI2C1Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltCompInterrupt) ? ABSOLUTE(__AltCompInterrupt) : + (DEFINED(__CompInterrupt) ? ABSOLUTE(__CompInterrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltCNInterrupt) ? ABSOLUTE(__AltCNInterrupt) : + (DEFINED(__CNInterrupt) ? ABSOLUTE(__CNInterrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltINT1Interrupt) ? ABSOLUTE(__AltINT1Interrupt) : + (DEFINED(__INT1Interrupt) ? ABSOLUTE(__INT1Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt21) ? ABSOLUTE(__AltInterrupt21) : + (DEFINED(__Interrupt21) ? ABSOLUTE(__Interrupt21) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt22) ? ABSOLUTE(__AltInterrupt22) : + (DEFINED(__Interrupt22) ? ABSOLUTE(__Interrupt22) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt23) ? ABSOLUTE(__AltInterrupt23) : + (DEFINED(__Interrupt23) ? ABSOLUTE(__Interrupt23) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt24) ? ABSOLUTE(__AltInterrupt24) : + (DEFINED(__Interrupt24) ? ABSOLUTE(__Interrupt24) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltOC3Interrupt) ? ABSOLUTE(__AltOC3Interrupt) : + (DEFINED(__OC3Interrupt) ? ABSOLUTE(__OC3Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltOC4Interrupt) ? ABSOLUTE(__AltOC4Interrupt) : + (DEFINED(__OC4Interrupt) ? ABSOLUTE(__OC4Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltT4Interrupt) ? ABSOLUTE(__AltT4Interrupt) : + (DEFINED(__T4Interrupt) ? ABSOLUTE(__T4Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltT5Interrupt) ? ABSOLUTE(__AltT5Interrupt) : + (DEFINED(__T5Interrupt) ? ABSOLUTE(__T5Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltINT2Interrupt) ? ABSOLUTE(__AltINT2Interrupt) : + (DEFINED(__INT2Interrupt) ? ABSOLUTE(__INT2Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltU2RXInterrupt) ? ABSOLUTE(__AltU2RXInterrupt) : + (DEFINED(__U2RXInterrupt) ? ABSOLUTE(__U2RXInterrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltU2TXInterrupt) ? ABSOLUTE(__AltU2TXInterrupt) : + (DEFINED(__U2TXInterrupt) ? ABSOLUTE(__U2TXInterrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltSPI2ErrInterrupt) ? ABSOLUTE(__AltSPI2ErrInterrupt) : + (DEFINED(__SPI2ErrInterrupt) ? ABSOLUTE(__SPI2ErrInterrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltSPI2Interrupt) ? ABSOLUTE(__AltSPI2Interrupt) : + (DEFINED(__SPI2Interrupt) ? ABSOLUTE(__SPI2Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt34) ? ABSOLUTE(__AltInterrupt34) : + (DEFINED(__Interrupt34) ? ABSOLUTE(__Interrupt34) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt35) ? ABSOLUTE(__AltInterrupt35) : + (DEFINED(__Interrupt35) ? ABSOLUTE(__Interrupt35) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt36) ? ABSOLUTE(__AltInterrupt36) : + (DEFINED(__Interrupt36) ? ABSOLUTE(__Interrupt36) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltIC3Interrupt) ? ABSOLUTE(__AltIC3Interrupt) : + (DEFINED(__IC3Interrupt) ? ABSOLUTE(__IC3Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltIC4Interrupt) ? ABSOLUTE(__AltIC4Interrupt) : + (DEFINED(__IC4Interrupt) ? ABSOLUTE(__IC4Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltIC5Interrupt) ? ABSOLUTE(__AltIC5Interrupt) : + (DEFINED(__IC5Interrupt) ? ABSOLUTE(__IC5Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt40) ? ABSOLUTE(__AltInterrupt40) : + (DEFINED(__Interrupt40) ? ABSOLUTE(__Interrupt40) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltOC5Interrupt) ? ABSOLUTE(__AltOC5Interrupt) : + (DEFINED(__OC5Interrupt) ? ABSOLUTE(__OC5Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt42) ? ABSOLUTE(__AltInterrupt42) : + (DEFINED(__Interrupt42) ? ABSOLUTE(__Interrupt42) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt43) ? ABSOLUTE(__AltInterrupt43) : + (DEFINED(__Interrupt43) ? ABSOLUTE(__Interrupt43) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt44) ? ABSOLUTE(__AltInterrupt44) : + (DEFINED(__Interrupt44) ? ABSOLUTE(__Interrupt44) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltPMPInterrupt) ? ABSOLUTE(__AltPMPInterrupt) : + (DEFINED(__PMPInterrupt) ? ABSOLUTE(__PMPInterrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt46) ? ABSOLUTE(__AltInterrupt46) : + (DEFINED(__Interrupt46) ? ABSOLUTE(__Interrupt46) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt47) ? ABSOLUTE(__AltInterrupt47) : + (DEFINED(__Interrupt47) ? ABSOLUTE(__Interrupt47) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt48) ? ABSOLUTE(__AltInterrupt48) : + (DEFINED(__Interrupt48) ? ABSOLUTE(__Interrupt48) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltSI2C2Interrupt) ? ABSOLUTE(__AltSI2C2Interrupt) : + (DEFINED(__SI2C2Interrupt) ? ABSOLUTE(__SI2C2Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltMI2C2Interrupt) ? ABSOLUTE(__AltMI2C2Interrupt) : + (DEFINED(__MI2C2Interrupt) ? ABSOLUTE(__MI2C2Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt51) ? ABSOLUTE(__AltInterrupt51) : + (DEFINED(__Interrupt51) ? ABSOLUTE(__Interrupt51) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt52) ? ABSOLUTE(__AltInterrupt52) : + (DEFINED(__Interrupt52) ? ABSOLUTE(__Interrupt52) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltINT3Interrupt) ? ABSOLUTE(__AltINT3Interrupt) : + (DEFINED(__INT3Interrupt) ? ABSOLUTE(__INT3Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltINT4Interrupt) ? ABSOLUTE(__AltINT4Interrupt) : + (DEFINED(__INT4Interrupt) ? ABSOLUTE(__INT4Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt55) ? ABSOLUTE(__AltInterrupt55) : + (DEFINED(__Interrupt55) ? ABSOLUTE(__Interrupt55) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt56) ? ABSOLUTE(__AltInterrupt56) : + (DEFINED(__Interrupt56) ? ABSOLUTE(__Interrupt56) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt57) ? ABSOLUTE(__AltInterrupt57) : + (DEFINED(__Interrupt57) ? ABSOLUTE(__Interrupt57) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt58) ? ABSOLUTE(__AltInterrupt58) : + (DEFINED(__Interrupt58) ? ABSOLUTE(__Interrupt58) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt59) ? ABSOLUTE(__AltInterrupt59) : + (DEFINED(__Interrupt59) ? ABSOLUTE(__Interrupt59) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt60) ? ABSOLUTE(__AltInterrupt60) : + (DEFINED(__Interrupt60) ? ABSOLUTE(__Interrupt60) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt61) ? ABSOLUTE(__AltInterrupt61) : + (DEFINED(__Interrupt61) ? ABSOLUTE(__Interrupt61) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltRTCCInterrupt) ? ABSOLUTE(__AltRTCCInterrupt) : + (DEFINED(__RTCCInterrupt) ? ABSOLUTE(__RTCCInterrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt63) ? ABSOLUTE(__AltInterrupt63) : + (DEFINED(__Interrupt63) ? ABSOLUTE(__Interrupt63) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt64) ? ABSOLUTE(__AltInterrupt64) : + (DEFINED(__Interrupt64) ? ABSOLUTE(__Interrupt64) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltU1ErrInterrupt) ? ABSOLUTE(__AltU1ErrInterrupt) : + (DEFINED(__U1ErrInterrupt) ? ABSOLUTE(__U1ErrInterrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltU2ErrInterrupt) ? ABSOLUTE(__AltU2ErrInterrupt) : + (DEFINED(__U2ErrInterrupt) ? ABSOLUTE(__U2ErrInterrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltCRCInterrupt) ? ABSOLUTE(__AltCRCInterrupt) : + (DEFINED(__CRCInterrupt) ? ABSOLUTE(__CRCInterrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt68) ? ABSOLUTE(__AltInterrupt68) : + (DEFINED(__Interrupt68) ? ABSOLUTE(__Interrupt68) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt69) ? ABSOLUTE(__AltInterrupt69) : + (DEFINED(__Interrupt69) ? ABSOLUTE(__Interrupt69) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt70) ? ABSOLUTE(__AltInterrupt70) : + (DEFINED(__Interrupt70) ? ABSOLUTE(__Interrupt70) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt71) ? ABSOLUTE(__AltInterrupt71) : + (DEFINED(__Interrupt71) ? ABSOLUTE(__Interrupt71) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt72) ? ABSOLUTE(__AltInterrupt72) : + (DEFINED(__Interrupt72) ? ABSOLUTE(__Interrupt72) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt73) ? ABSOLUTE(__AltInterrupt73) : + (DEFINED(__Interrupt73) ? ABSOLUTE(__Interrupt73) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt74) ? ABSOLUTE(__AltInterrupt74) : + (DEFINED(__Interrupt74) ? ABSOLUTE(__Interrupt74) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt75) ? ABSOLUTE(__AltInterrupt75) : + (DEFINED(__Interrupt75) ? ABSOLUTE(__Interrupt75) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt76) ? ABSOLUTE(__AltInterrupt76) : + (DEFINED(__Interrupt76) ? ABSOLUTE(__Interrupt76) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt77) ? ABSOLUTE(__AltInterrupt77) : + (DEFINED(__Interrupt77) ? ABSOLUTE(__Interrupt77) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt78) ? ABSOLUTE(__AltInterrupt78) : + (DEFINED(__Interrupt78) ? ABSOLUTE(__Interrupt78) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt79) ? ABSOLUTE(__AltInterrupt79) : + (DEFINED(__Interrupt79) ? ABSOLUTE(__Interrupt79) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt80) ? ABSOLUTE(__AltInterrupt80) : + (DEFINED(__Interrupt80) ? ABSOLUTE(__Interrupt80) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt81) ? ABSOLUTE(__AltInterrupt81) : + (DEFINED(__Interrupt81) ? ABSOLUTE(__Interrupt81) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt82) ? ABSOLUTE(__AltInterrupt82) : + (DEFINED(__Interrupt82) ? ABSOLUTE(__Interrupt82) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt83) ? ABSOLUTE(__AltInterrupt83) : + (DEFINED(__Interrupt83) ? ABSOLUTE(__Interrupt83) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt84) ? ABSOLUTE(__AltInterrupt84) : + (DEFINED(__Interrupt84) ? ABSOLUTE(__Interrupt84) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt85) ? ABSOLUTE(__AltInterrupt85) : + (DEFINED(__Interrupt85) ? ABSOLUTE(__Interrupt85) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt86) ? ABSOLUTE(__AltInterrupt86) : + (DEFINED(__Interrupt86) ? ABSOLUTE(__Interrupt86) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt87) ? ABSOLUTE(__AltInterrupt87) : + (DEFINED(__Interrupt87) ? ABSOLUTE(__Interrupt87) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt88) ? ABSOLUTE(__AltInterrupt88) : + (DEFINED(__Interrupt88) ? ABSOLUTE(__Interrupt88) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt89) ? ABSOLUTE(__AltInterrupt89) : + (DEFINED(__Interrupt89) ? ABSOLUTE(__Interrupt89) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt90) ? ABSOLUTE(__AltInterrupt90) : + (DEFINED(__Interrupt90) ? ABSOLUTE(__Interrupt90) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt91) ? ABSOLUTE(__AltInterrupt91) : + (DEFINED(__Interrupt91) ? ABSOLUTE(__Interrupt91) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt92) ? ABSOLUTE(__AltInterrupt92) : + (DEFINED(__Interrupt92) ? ABSOLUTE(__Interrupt92) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt93) ? ABSOLUTE(__AltInterrupt93) : + (DEFINED(__Interrupt93) ? ABSOLUTE(__Interrupt93) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt94) ? ABSOLUTE(__AltInterrupt94) : + (DEFINED(__Interrupt94) ? ABSOLUTE(__Interrupt94) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt95) ? ABSOLUTE(__AltInterrupt95) : + (DEFINED(__Interrupt95) ? ABSOLUTE(__Interrupt95) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt96) ? ABSOLUTE(__AltInterrupt96) : + (DEFINED(__Interrupt96) ? ABSOLUTE(__Interrupt96) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt97) ? ABSOLUTE(__AltInterrupt97) : + (DEFINED(__Interrupt97) ? ABSOLUTE(__Interrupt97) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt98) ? ABSOLUTE(__AltInterrupt98) : + (DEFINED(__Interrupt98) ? ABSOLUTE(__Interrupt98) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt99) ? ABSOLUTE(__AltInterrupt99) : + (DEFINED(__Interrupt99) ? ABSOLUTE(__Interrupt99) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt100) ? ABSOLUTE(__AltInterrupt100) : + (DEFINED(__Interrupt100) ? ABSOLUTE(__Interrupt100) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt101) ? ABSOLUTE(__AltInterrupt101) : + (DEFINED(__Interrupt101) ? ABSOLUTE(__Interrupt101) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt102) ? ABSOLUTE(__AltInterrupt102) : + (DEFINED(__Interrupt102) ? ABSOLUTE(__Interrupt102) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt103) ? ABSOLUTE(__AltInterrupt103) : + (DEFINED(__Interrupt103) ? ABSOLUTE(__Interrupt103) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt104) ? ABSOLUTE(__AltInterrupt104) : + (DEFINED(__Interrupt104) ? ABSOLUTE(__Interrupt104) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt105) ? ABSOLUTE(__AltInterrupt105) : + (DEFINED(__Interrupt105) ? ABSOLUTE(__Interrupt105) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt106) ? ABSOLUTE(__AltInterrupt106) : + (DEFINED(__Interrupt106) ? ABSOLUTE(__Interrupt106) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt107) ? ABSOLUTE(__AltInterrupt107) : + (DEFINED(__Interrupt107) ? ABSOLUTE(__Interrupt107) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt108) ? ABSOLUTE(__AltInterrupt108) : + (DEFINED(__Interrupt108) ? ABSOLUTE(__Interrupt108) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt109) ? ABSOLUTE(__AltInterrupt109) : + (DEFINED(__Interrupt109) ? ABSOLUTE(__Interrupt109) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt110) ? ABSOLUTE(__AltInterrupt110) : + (DEFINED(__Interrupt110) ? ABSOLUTE(__Interrupt110) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt111) ? ABSOLUTE(__AltInterrupt111) : + (DEFINED(__Interrupt111) ? ABSOLUTE(__Interrupt111) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt112) ? ABSOLUTE(__AltInterrupt112) : + (DEFINED(__Interrupt112) ? ABSOLUTE(__Interrupt112) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt113) ? ABSOLUTE(__AltInterrupt113) : + (DEFINED(__Interrupt113) ? ABSOLUTE(__Interrupt113) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt114) ? ABSOLUTE(__AltInterrupt114) : + (DEFINED(__Interrupt114) ? ABSOLUTE(__Interrupt114) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt115) ? ABSOLUTE(__AltInterrupt115) : + (DEFINED(__Interrupt115) ? ABSOLUTE(__Interrupt115) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt116) ? ABSOLUTE(__AltInterrupt116) : + (DEFINED(__Interrupt116) ? ABSOLUTE(__Interrupt116) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt117) ? ABSOLUTE(__AltInterrupt117) : + (DEFINED(__Interrupt117) ? ABSOLUTE(__Interrupt117) : + ABSOLUTE(__DefaultInterrupt))); + } >aivt +} /* SECTIONS */ + + +/* +** ============== Equates for SFR Addresses ============= +*/ + + WREG0 = 0x0; +_WREG0 = 0x0; + WREG1 = 0x2; +_WREG1 = 0x2; + WREG2 = 0x4; +_WREG2 = 0x4; + WREG3 = 0x6; +_WREG3 = 0x6; + WREG4 = 0x8; +_WREG4 = 0x8; + WREG5 = 0xA; +_WREG5 = 0xA; + WREG6 = 0xC; +_WREG6 = 0xC; + WREG7 = 0xE; +_WREG7 = 0xE; + WREG8 = 0x10; +_WREG8 = 0x10; + WREG9 = 0x12; +_WREG9 = 0x12; + WREG10 = 0x14; +_WREG10 = 0x14; + WREG11 = 0x16; +_WREG11 = 0x16; + WREG12 = 0x18; +_WREG12 = 0x18; + WREG13 = 0x1A; +_WREG13 = 0x1A; + WREG14 = 0x1C; +_WREG14 = 0x1C; + WREG15 = 0x1E; +_WREG15 = 0x1E; + SPLIM = 0x20; +_SPLIM = 0x20; + PCL = 0x2E; +_PCL = 0x2E; + PCH = 0x30; +_PCH = 0x30; + TBLPAG = 0x32; +_TBLPAG = 0x32; + PSVPAG = 0x34; +_PSVPAG = 0x34; + RCOUNT = 0x36; +_RCOUNT = 0x36; + SR = 0x42; +_SR = 0x42; +_SRbits = 0x42; + CORCON = 0x44; +_CORCON = 0x44; +_CORCONbits = 0x44; + DISICNT = 0x52; +_DISICNT = 0x52; + CNEN1 = 0x60; +_CNEN1 = 0x60; +_CNEN1bits = 0x60; + CNEN2 = 0x62; +_CNEN2 = 0x62; +_CNEN2bits = 0x62; + CNPU1 = 0x68; +_CNPU1 = 0x68; +_CNPU1bits = 0x68; + CNPU2 = 0x6A; +_CNPU2 = 0x6A; +_CNPU2bits = 0x6A; + INTCON1 = 0x80; +_INTCON1 = 0x80; +_INTCON1bits = 0x80; + INTCON2 = 0x82; +_INTCON2 = 0x82; +_INTCON2bits = 0x82; + IFS0 = 0x84; +_IFS0 = 0x84; +_IFS0bits = 0x84; + IFS1 = 0x86; +_IFS1 = 0x86; +_IFS1bits = 0x86; + IFS2 = 0x88; +_IFS2 = 0x88; +_IFS2bits = 0x88; + IFS3 = 0x8A; +_IFS3 = 0x8A; +_IFS3bits = 0x8A; + IFS4 = 0x8C; +_IFS4 = 0x8C; +_IFS4bits = 0x8C; + IEC0 = 0x94; +_IEC0 = 0x94; +_IEC0bits = 0x94; + IEC1 = 0x96; +_IEC1 = 0x96; +_IEC1bits = 0x96; + IEC2 = 0x98; +_IEC2 = 0x98; +_IEC2bits = 0x98; + IEC3 = 0x9A; +_IEC3 = 0x9A; +_IEC3bits = 0x9A; + IEC4 = 0x9C; +_IEC4 = 0x9C; +_IEC4bits = 0x9C; + IPC0 = 0xA4; +_IPC0 = 0xA4; +_IPC0bits = 0xA4; + IPC1 = 0xA6; +_IPC1 = 0xA6; +_IPC1bits = 0xA6; + IPC2 = 0xA8; +_IPC2 = 0xA8; +_IPC2bits = 0xA8; + IPC3 = 0xAA; +_IPC3 = 0xAA; +_IPC3bits = 0xAA; + IPC4 = 0xAC; +_IPC4 = 0xAC; +_IPC4bits = 0xAC; + IPC5 = 0xAE; +_IPC5 = 0xAE; +_IPC5bits = 0xAE; + IPC6 = 0xB0; +_IPC6 = 0xB0; +_IPC6bits = 0xB0; + IPC7 = 0xB2; +_IPC7 = 0xB2; +_IPC7bits = 0xB2; + IPC8 = 0xB4; +_IPC8 = 0xB4; +_IPC8bits = 0xB4; + IPC9 = 0xB6; +_IPC9 = 0xB6; +_IPC9bits = 0xB6; + IPC10 = 0xB8; +_IPC10 = 0xB8; +_IPC10bits = 0xB8; + IPC11 = 0xBA; +_IPC11 = 0xBA; +_IPC11bits = 0xBA; + IPC12 = 0xBC; +_IPC12 = 0xBC; +_IPC12bits = 0xBC; + IPC13 = 0xBE; +_IPC13 = 0xBE; +_IPC13bits = 0xBE; + IPC15 = 0xC2; +_IPC15 = 0xC2; +_IPC15bits = 0xC2; + IPC16 = 0xC4; +_IPC16 = 0xC4; +_IPC16bits = 0xC4; + TMR1 = 0x100; +_TMR1 = 0x100; + PR1 = 0x102; +_PR1 = 0x102; + T1CON = 0x104; +_T1CON = 0x104; +_T1CONbits = 0x104; + TMR2 = 0x106; +_TMR2 = 0x106; + TMR3HLD = 0x108; +_TMR3HLD = 0x108; + TMR3 = 0x10A; +_TMR3 = 0x10A; + PR2 = 0x10C; +_PR2 = 0x10C; + PR3 = 0x10E; +_PR3 = 0x10E; + T2CON = 0x110; +_T2CON = 0x110; +_T2CONbits = 0x110; + T3CON = 0x112; +_T3CON = 0x112; +_T3CONbits = 0x112; + TMR4 = 0x114; +_TMR4 = 0x114; + TMR5HLD = 0x116; +_TMR5HLD = 0x116; + TMR5 = 0x118; +_TMR5 = 0x118; + PR4 = 0x11A; +_PR4 = 0x11A; + PR5 = 0x11C; +_PR5 = 0x11C; + T4CON = 0x11E; +_T4CON = 0x11E; +_T4CONbits = 0x11E; + T5CON = 0x120; +_T5CON = 0x120; +_T5CONbits = 0x120; + IC1BUF = 0x140; +_IC1BUF = 0x140; + IC1CON = 0x142; +_IC1CON = 0x142; +_IC1CONbits = 0x142; + IC2BUF = 0x144; +_IC2BUF = 0x144; + IC2CON = 0x146; +_IC2CON = 0x146; +_IC2CONbits = 0x146; + IC3BUF = 0x148; +_IC3BUF = 0x148; + IC3CON = 0x14A; +_IC3CON = 0x14A; +_IC3CONbits = 0x14A; + IC4BUF = 0x14C; +_IC4BUF = 0x14C; + IC4CON = 0x14E; +_IC4CON = 0x14E; +_IC4CONbits = 0x14E; + IC5BUF = 0x150; +_IC5BUF = 0x150; + IC5CON = 0x152; +_IC5CON = 0x152; +_IC5CONbits = 0x152; + OC1RS = 0x180; +_OC1RS = 0x180; + OC1R = 0x182; +_OC1R = 0x182; + OC1CON = 0x184; +_OC1CON = 0x184; +_OC1CONbits = 0x184; + OC2RS = 0x186; +_OC2RS = 0x186; + OC2R = 0x188; +_OC2R = 0x188; + OC2CON = 0x18A; +_OC2CON = 0x18A; +_OC2CONbits = 0x18A; + OC3RS = 0x18C; +_OC3RS = 0x18C; + OC3R = 0x18E; +_OC3R = 0x18E; + OC3CON = 0x190; +_OC3CON = 0x190; +_OC3CONbits = 0x190; + OC4RS = 0x192; +_OC4RS = 0x192; + OC4R = 0x194; +_OC4R = 0x194; + OC4CON = 0x196; +_OC4CON = 0x196; +_OC4CONbits = 0x196; + OC5RS = 0x198; +_OC5RS = 0x198; + OC5R = 0x19A; +_OC5R = 0x19A; + OC5CON = 0x19C; +_OC5CON = 0x19C; +_OC5CONbits = 0x19C; + I2C1RCV = 0x200; +_I2C1RCV = 0x200; + I2C1TRN = 0x202; +_I2C1TRN = 0x202; + I2C1BRG = 0x204; +_I2C1BRG = 0x204; + I2C1CON = 0x206; +_I2C1CON = 0x206; +_I2C1CONbits = 0x206; + I2C1STAT = 0x208; +_I2C1STAT = 0x208; +_I2C1STATbits = 0x208; + I2C1ADD = 0x20A; +_I2C1ADD = 0x20A; + I2C1MSK = 0x20C; +_I2C1MSK = 0x20C; + I2C2RCV = 0x210; +_I2C2RCV = 0x210; + I2C2TRN = 0x212; +_I2C2TRN = 0x212; + I2C2BRG = 0x214; +_I2C2BRG = 0x214; + I2C2CON = 0x216; +_I2C2CON = 0x216; +_I2C2CONbits = 0x216; + I2C2STAT = 0x218; +_I2C2STAT = 0x218; +_I2C2STATbits = 0x218; + I2C2ADD = 0x21A; +_I2C2ADD = 0x21A; + I2C2MSK = 0x21C; +_I2C2MSK = 0x21C; + U1MODE = 0x220; +_U1MODE = 0x220; +_U1MODEbits = 0x220; + U1STA = 0x222; +_U1STA = 0x222; +_U1STAbits = 0x222; + U1TXREG = 0x224; +_U1TXREG = 0x224; + U1RXREG = 0x226; +_U1RXREG = 0x226; + U1BRG = 0x228; +_U1BRG = 0x228; + U2MODE = 0x230; +_U2MODE = 0x230; +_U2MODEbits = 0x230; + U2STA = 0x232; +_U2STA = 0x232; +_U2STAbits = 0x232; + U2TXREG = 0x234; +_U2TXREG = 0x234; + U2RXREG = 0x236; +_U2RXREG = 0x236; + U2BRG = 0x238; +_U2BRG = 0x238; + SPI1STAT = 0x240; +_SPI1STAT = 0x240; +_SPI1STATbits = 0x240; + SPI1CON1 = 0x242; +_SPI1CON1 = 0x242; +_SPI1CON1bits = 0x242; + SPI1CON2 = 0x244; +_SPI1CON2 = 0x244; +_SPI1CON2bits = 0x244; + SPI1BUF = 0x248; +_SPI1BUF = 0x248; + SPI2STAT = 0x260; +_SPI2STAT = 0x260; +_SPI2STATbits = 0x260; + SPI2CON1 = 0x262; +_SPI2CON1 = 0x262; +_SPI2CON1bits = 0x262; + SPI2CON2 = 0x264; +_SPI2CON2 = 0x264; +_SPI2CON2bits = 0x264; + SPI2BUF = 0x268; +_SPI2BUF = 0x268; + TRISA = 0x2C0; +_TRISA = 0x2C0; +_TRISAbits = 0x2C0; + PORTA = 0x2C2; +_PORTA = 0x2C2; +_PORTAbits = 0x2C2; + LATA = 0x2C4; +_LATA = 0x2C4; +_LATAbits = 0x2C4; + TRISB = 0x2C6; +_TRISB = 0x2C6; +_TRISBbits = 0x2C6; + PORTB = 0x2C8; +_PORTB = 0x2C8; +_PORTBbits = 0x2C8; + LATB = 0x2CA; +_LATB = 0x2CA; +_LATBbits = 0x2CA; + TRISC = 0x2CC; +_TRISC = 0x2CC; +_TRISCbits = 0x2CC; + PORTC = 0x2CE; +_PORTC = 0x2CE; +_PORTCbits = 0x2CE; + LATC = 0x2D0; +_LATC = 0x2D0; +_LATCbits = 0x2D0; + TRISD = 0x2D2; +_TRISD = 0x2D2; +_TRISDbits = 0x2D2; + PORTD = 0x2D4; +_PORTD = 0x2D4; +_PORTDbits = 0x2D4; + LATD = 0x2D6; +_LATD = 0x2D6; +_LATDbits = 0x2D6; + TRISE = 0x2D8; +_TRISE = 0x2D8; +_TRISEbits = 0x2D8; + PORTE = 0x2DA; +_PORTE = 0x2DA; +_PORTEbits = 0x2DA; + LATE = 0x2DC; +_LATE = 0x2DC; +_LATEbits = 0x2DC; + TRISF = 0x2DE; +_TRISF = 0x2DE; +_TRISFbits = 0x2DE; + PORTF = 0x2E0; +_PORTF = 0x2E0; +_PORTFbits = 0x2E0; + LATF = 0x2E2; +_LATF = 0x2E2; +_LATFbits = 0x2E2; + TRISG = 0x2E4; +_TRISG = 0x2E4; +_TRISGbits = 0x2E4; + PORTG = 0x2E6; +_PORTG = 0x2E6; +_PORTGbits = 0x2E6; + LATG = 0x2E8; +_LATG = 0x2E8; +_LATGbits = 0x2E8; + PADCFG1 = 0x2FC; +_PADCFG1 = 0x2FC; +_PADCFG1bits = 0x2FC; + ADC1BUF0 = 0x300; +_ADC1BUF0 = 0x300; + ADC1BUF1 = 0x302; +_ADC1BUF1 = 0x302; + ADC1BUF2 = 0x304; +_ADC1BUF2 = 0x304; + ADC1BUF3 = 0x306; +_ADC1BUF3 = 0x306; + ADC1BUF4 = 0x308; +_ADC1BUF4 = 0x308; + ADC1BUF5 = 0x30A; +_ADC1BUF5 = 0x30A; + ADC1BUF6 = 0x30C; +_ADC1BUF6 = 0x30C; + ADC1BUF7 = 0x30E; +_ADC1BUF7 = 0x30E; + ADC1BUF8 = 0x310; +_ADC1BUF8 = 0x310; + ADC1BUF9 = 0x312; +_ADC1BUF9 = 0x312; + ADC1BUFA = 0x314; +_ADC1BUFA = 0x314; + ADC1BUFB = 0x316; +_ADC1BUFB = 0x316; + ADC1BUFC = 0x318; +_ADC1BUFC = 0x318; + ADC1BUFD = 0x31A; +_ADC1BUFD = 0x31A; + ADC1BUFE = 0x31C; +_ADC1BUFE = 0x31C; + ADC1BUFF = 0x31E; +_ADC1BUFF = 0x31E; + AD1CON1 = 0x320; +_AD1CON1 = 0x320; +_AD1CON1bits = 0x320; + AD1CON2 = 0x322; +_AD1CON2 = 0x322; +_AD1CON2bits = 0x322; + AD1CON3 = 0x324; +_AD1CON3 = 0x324; +_AD1CON3bits = 0x324; + AD1CHS = 0x328; +_AD1CHS = 0x328; +_AD1CHSbits = 0x328; + AD1PCFG = 0x32C; +_AD1PCFG = 0x32C; +_AD1PCFGbits = 0x32C; + AD1CSSL = 0x330; +_AD1CSSL = 0x330; +_AD1CSSLbits = 0x330; + PMCON = 0x600; +_PMCON = 0x600; +_PMCONbits = 0x600; + PMMODE = 0x602; +_PMMODE = 0x602; +_PMMODEbits = 0x602; + PMADDR = 0x604; +_PMADDR = 0x604; +_PMADDRbits = 0x604; + PMDOUT1 = 0x604; +_PMDOUT1 = 0x604; + PMDOUT2 = 0x606; +_PMDOUT2 = 0x606; + PMDIN1 = 0x608; +_PMDIN1 = 0x608; + PMDIN2 = 0x60A; +_PMDIN2 = 0x60A; + PMPEN = 0x60C; +_PMPEN = 0x60C; +_PMPENbits = 0x60C; + PMSTAT = 0x60E; +_PMSTAT = 0x60E; +_PMSTATbits = 0x60E; + ALRMVAL = 0x620; +_ALRMVAL = 0x620; + ALCFGRPT = 0x622; +_ALCFGRPT = 0x622; +_ALCFGRPTbits = 0x622; + RTCVAL = 0x624; +_RTCVAL = 0x624; + RCFGCAL = 0x626; +_RCFGCAL = 0x626; +_RCFGCALbits = 0x626; + CMCON = 0x630; +_CMCON = 0x630; +_CMCONbits = 0x630; + CVRCON = 0x632; +_CVRCON = 0x632; +_CVRCONbits = 0x632; + CRCCON = 0x640; +_CRCCON = 0x640; +_CRCCONbits = 0x640; + CRCXOR = 0x642; +_CRCXOR = 0x642; + CRCDAT = 0x644; +_CRCDAT = 0x644; + CRCWDAT = 0x646; +_CRCWDAT = 0x646; + ODCA = 0x6C0; +_ODCA = 0x6C0; +_ODCAbits = 0x6C0; + ODCB = 0x6C6; +_ODCB = 0x6C6; +_ODCBbits = 0x6C6; + ODCC = 0x6CC; +_ODCC = 0x6CC; +_ODCCbits = 0x6CC; + ODCD = 0x6D2; +_ODCD = 0x6D2; +_ODCDbits = 0x6D2; + ODCE = 0x6D8; +_ODCE = 0x6D8; +_ODCEbits = 0x6D8; + ODCF = 0x6DE; +_ODCF = 0x6DE; +_ODCFbits = 0x6DE; + ODCG = 0x6E4; +_ODCG = 0x6E4; +_ODCGbits = 0x6E4; + RCON = 0x740; +_RCON = 0x740; +_RCONbits = 0x740; + OSCCON = 0x742; +_OSCCON = 0x742; +_OSCCONbits = 0x742; + CLKDIV = 0x744; +_CLKDIV = 0x744; +_CLKDIVbits = 0x744; + OSCTUN = 0x748; +_OSCTUN = 0x748; +_OSCTUNbits = 0x748; + NVMCON = 0x760; +_NVMCON = 0x760; +_NVMCONbits = 0x760; + NVMKEY = 0x766; +_NVMKEY = 0x766; + PMD1 = 0x770; +_PMD1 = 0x770; +_PMD1bits = 0x770; + PMD2 = 0x772; +_PMD2 = 0x772; +_PMD2bits = 0x772; + PMD3 = 0x774; +_PMD3 = 0x774; +_PMD3bits = 0x774; diff --git a/20080212/Demo/PIC24_MPLAB/serial/serial.c b/20080212/Demo/PIC24_MPLAB/serial/serial.c new file mode 100644 index 000000000..b24d211f2 --- /dev/null +++ b/20080212/Demo/PIC24_MPLAB/serial/serial.c @@ -0,0 +1,242 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER. + +NOTE: This driver is primarily to test the scheduler functionality. It does +not effectively use the buffers or DMA and is therefore not intended to be +an example of an efficient driver. */ + +/* Standard include file. */ +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "queue.h" +#include "task.h" + +/* Demo app include files. */ +#include "serial.h" + +/* Hardware setup. */ +#define serOUTPUT 0 +#define serINPUT 1 +#define serLOW_SPEED 0 +#define serONE_STOP_BIT 0 +#define serEIGHT_DATA_BITS_NO_PARITY 0 +#define serNORMAL_IDLE_STATE 0 +#define serAUTO_BAUD_OFF 0 +#define serLOOPBACK_OFF 0 +#define serWAKE_UP_DISABLE 0 +#define serNO_HARDWARE_FLOW_CONTROL 0 +#define serSTANDARD_IO 0 +#define serNO_IRDA 0 +#define serCONTINUE_IN_IDLE_MODE 0 +#define serUART_ENABLED 1 +#define serINTERRUPT_ON_SINGLE_CHAR 0 +#define serTX_ENABLE 1 +#define serINTERRUPT_ENABLE 1 +#define serINTERRUPT_DISABLE 0 +#define serCLEAR_FLAG 0 +#define serSET_FLAG 1 + + +/* The queues used to communicate between tasks and ISR's. */ +static xQueueHandle xRxedChars; +static xQueueHandle xCharsForTx; + +static portBASE_TYPE xTxHasEnded; +/*-----------------------------------------------------------*/ + +xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) +{ +portCHAR cChar; + + /* Create the queues used by the com test task. */ + xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + + /* Setup the UART. */ + U2MODEbits.BRGH = serLOW_SPEED; + U2MODEbits.STSEL = serONE_STOP_BIT; + U2MODEbits.PDSEL = serEIGHT_DATA_BITS_NO_PARITY; + U2MODEbits.RXINV = serNORMAL_IDLE_STATE; + U2MODEbits.ABAUD = serAUTO_BAUD_OFF; + U2MODEbits.LPBACK = serLOOPBACK_OFF; + U2MODEbits.WAKE = serWAKE_UP_DISABLE; + U2MODEbits.UEN = serNO_HARDWARE_FLOW_CONTROL; + U2MODEbits.IREN = serNO_IRDA; + U2MODEbits.USIDL = serCONTINUE_IN_IDLE_MODE; + U2MODEbits.UARTEN = serUART_ENABLED; + + U2BRG = (unsigned portSHORT)(( (float)configCPU_CLOCK_HZ / ( (float)16 * (float)ulWantedBaud ) ) - (float)0.5); + + U2STAbits.URXISEL = serINTERRUPT_ON_SINGLE_CHAR; + U2STAbits.UTXEN = serTX_ENABLE; + U2STAbits.UTXINV = serNORMAL_IDLE_STATE; + U2STAbits.UTXISEL0 = serINTERRUPT_ON_SINGLE_CHAR; + U2STAbits.UTXISEL1 = serINTERRUPT_ON_SINGLE_CHAR; + + /* It is assumed that this function is called prior to the scheduler being + started. Therefore interrupts must not be allowed to occur yet as they + may attempt to perform a context switch. */ + portDISABLE_INTERRUPTS(); + + IFS1bits.U2RXIF = serCLEAR_FLAG; + IFS1bits.U2TXIF = serCLEAR_FLAG; + IPC7bits.U2RXIP = configKERNEL_INTERRUPT_PRIORITY; + IPC7bits.U2TXIP = configKERNEL_INTERRUPT_PRIORITY; + IEC1bits.U2TXIE = serINTERRUPT_ENABLE; + IEC1bits.U2RXIE = serINTERRUPT_ENABLE; + + /* Clear the Rx buffer. */ + while( U2STAbits.URXDA == serSET_FLAG ) + { + cChar = U2RXREG; + } + + xTxHasEnded = pdTRUE; + + return NULL; +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) +{ + /* Only one port is supported. */ + ( void ) pxPort; + + /* Get the next character from the buffer. Return false if no characters + are available or arrive before xBlockTime expires. */ + if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) + { + return pdTRUE; + } + else + { + return pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) +{ + /* Only one port is supported. */ + ( void ) pxPort; + + /* Return false if after the block time there is no room on the Tx queue. */ + if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) + { + return pdFAIL; + } + + /* A critical section should not be required as xTxHasEnded will not be + written to by the ISR if it is already 0 (is this correct?). */ + if( xTxHasEnded ) + { + xTxHasEnded = pdFALSE; + IFS1bits.U2TXIF = serSET_FLAG; + } + + return pdPASS; +} +/*-----------------------------------------------------------*/ + +void vSerialClose( xComPortHandle xPort ) +{ +} +/*-----------------------------------------------------------*/ + +void __attribute__((__interrupt__, auto_psv)) _U2RXInterrupt( void ) +{ +portCHAR cChar; +portBASE_TYPE xYieldRequired = pdFALSE; + + /* Get the character and post it on the queue of Rxed characters. + If the post causes a task to wake force a context switch as the woken task + may have a higher priority than the task we have interrupted. */ + IFS1bits.U2RXIF = serCLEAR_FLAG; + while( U2STAbits.URXDA ) + { + cChar = U2RXREG; + xYieldRequired = xQueueSendFromISR( xRxedChars, &cChar, xYieldRequired ); + } + + if( xYieldRequired != pdFALSE ) + { + taskYIELD(); + } +} +/*-----------------------------------------------------------*/ + +void __attribute__((__interrupt__, auto_psv)) _U2TXInterrupt( void ) +{ +signed portCHAR cChar; +portBASE_TYPE xTaskWoken = pdFALSE; + + /* If the transmit buffer is full we cannot get the next character. + Another interrupt will occur the next time there is space so this does + not matter. */ + IFS1bits.U2TXIF = serCLEAR_FLAG; + while( !( U2STAbits.UTXBF ) ) + { + if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWoken ) == pdTRUE ) + { + /* Send the next character queued for Tx. */ + U2TXREG = cChar; + } + else + { + /* Queue empty, nothing to send. */ + xTxHasEnded = pdTRUE; + break; + } + } + + if( xTaskWoken != pdFALSE ) + { + taskYIELD(); + } +} + + diff --git a/20080212/Demo/PIC24_MPLAB/timertest.c b/20080212/Demo/PIC24_MPLAB/timertest.c new file mode 100644 index 000000000..cb36ab2f5 --- /dev/null +++ b/20080212/Demo/PIC24_MPLAB/timertest.c @@ -0,0 +1,151 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* High speed timer test as described in main.c. */ + + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* Demo includes. */ +#include "partest.h" + +/* The number of interrupts to pass before we start looking at the jitter. */ +#define timerSETTLE_TIME 5 + +/* The maximum value the 16bit timer can contain. */ +#define timerMAX_COUNT 0xffff + +/*-----------------------------------------------------------*/ + +/* + * Measure the time between this interrupt and the previous interrupt to + * calculate the timing jitter. Remember the maximum value the jitter has + * ever been calculated to be. + */ +static void prvCalculateAndStoreJitter( void ); + +/*-----------------------------------------------------------*/ + +/* The maximum time (in processor clocks) between two consecutive timer +interrupts so far. */ +unsigned portSHORT usMaxJitter = 0; + +/*-----------------------------------------------------------*/ + +void vSetupTimerTest( unsigned portSHORT usFrequencyHz ) +{ + /* T2 is used to generate interrupts. T4 is used to provide an accurate + time measurement. */ + T2CON = 0; + T4CON = 0; + TMR2 = 0; + TMR4 = 0; + + /* Timer 2 is going to interrupt at usFrequencyHz Hz. */ + PR2 = ( unsigned portSHORT ) ( configCPU_CLOCK_HZ / ( unsigned portLONG ) usFrequencyHz ); + + /* Timer 4 is going to free run from minimum to maximum value. */ + PR4 = ( unsigned portSHORT ) timerMAX_COUNT; + + /* Setup timer 2 interrupt priority to be above the kernel priority so + the timer jitter is not effected by the kernel activity. */ + IPC1bits.T2IP = configKERNEL_INTERRUPT_PRIORITY + 1; + + /* Clear the interrupt as a starting condition. */ + IFS0bits.T2IF = 0; + + /* Enable the interrupt. */ + IEC0bits.T2IE = 1; + + /* Start both timers. */ + T2CONbits.TON = 1; + T4CONbits.TON = 1; +} +/*-----------------------------------------------------------*/ + +static void prvCalculateAndStoreJitter( void ) +{ +static unsigned portSHORT usLastCount = 0, usSettleCount = 0; +unsigned portSHORT usThisCount, usDifference; + + /* Capture the timer value as we enter the interrupt. */ + usThisCount = TMR4; + + if( usSettleCount >= timerSETTLE_TIME ) + { + /* What is the difference between the timer value in this interrupt + and the value from the last interrupt. */ + usDifference = usThisCount - usLastCount; + + /* Store the difference in the timer values if it is larger than the + currently stored largest value. The difference over and above the + expected difference will give the 'jitter' in the processing of these + interrupts. */ + if( usDifference > usMaxJitter ) + { + usMaxJitter = usDifference; + } + } + else + { + /* Don't bother storing any values for the first couple of + interrupts. */ + usSettleCount++; + } + + /* Remember what the timer value was this time through, so we can calculate + the difference the next time through. */ + usLastCount = usThisCount; +} +/*-----------------------------------------------------------*/ + +void __attribute__((__interrupt__, auto_psv)) _T2Interrupt( void ) +{ + /* Work out the time between this and the previous interrupt. */ + prvCalculateAndStoreJitter(); + + /* Clear the timer interrupt. */ + IFS0bits.T2IF = 0; +} + + diff --git a/20080212/Demo/PIC24_MPLAB/timertest.h b/20080212/Demo/PIC24_MPLAB/timertest.h new file mode 100644 index 000000000..a8c060386 --- /dev/null +++ b/20080212/Demo/PIC24_MPLAB/timertest.h @@ -0,0 +1,52 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef TIMER_TEST_H +#define TIMER_TEST_H + +/* Setup the high frequency timer interrupt. */ +void vSetupTimerTest( unsigned portSHORT usFrequencyHz ); + +#endif /* TIMER_TEST_H */ + + + diff --git a/20080212/Demo/PIC32MX_MPLAB/FreeRTOSConfig.h b/20080212/Demo/PIC32MX_MPLAB/FreeRTOSConfig.h new file mode 100644 index 000000000..ce407e4da --- /dev/null +++ b/20080212/Demo/PIC32MX_MPLAB/FreeRTOSConfig.h @@ -0,0 +1,93 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 72000000UL ) +#define configPERIPHERAL_CLOCK_HZ ( ( unsigned portLONG ) 36000000UL ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) +#define configMINIMAL_STACK_SIZE ( 230 ) +#define configISR_STACK_SIZE ( 130 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) 29000 ) +#define configMAX_TASK_NAME_LEN ( 8 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + +#define configKERNEL_INTERRUPT_PRIORITY 0x01 + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/PIC32MX_MPLAB/ParTest/ParTest.c b/20080212/Demo/PIC32MX_MPLAB/ParTest/ParTest.c new file mode 100644 index 000000000..2f0700c2e --- /dev/null +++ b/20080212/Demo/PIC32MX_MPLAB/ParTest/ParTest.c @@ -0,0 +1,99 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* Demo app includes. */ +#include "partest.h" + +#define ptOUTPUT 0 +#define ptALL_OFF 0 + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ + /* All LEDs output. */ + TRISA = ptOUTPUT; + PORTA = ptALL_OFF; + + mJTAGPortEnable( 0 ); +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ +unsigned portBASE_TYPE uxLEDBit; + + /* Which port A bit is being modified? */ + uxLEDBit = 1 << uxLED; + + if( xValue ) + { + /* Turn the LED on. Use of the PORTASET register removes the need + to use a critical section. */ + PORTASET = uxLEDBit; + } + else + { + /* Turn the LED off. Use of the PORTACLR register removes the need + to use a critical section. */ + PORTACLR = uxLEDBit; + } +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned portBASE_TYPE uxLEDBit; + + uxLEDBit = 1 << uxLED; + + /* Use of the PORTAINV register removes the need to use a critical section. */ + PORTAINV = uxLEDBit; +} + + + diff --git a/20080212/Demo/PIC32MX_MPLAB/RTOSDemo.mcp b/20080212/Demo/PIC32MX_MPLAB/RTOSDemo.mcp new file mode 100644 index 000000000..41ae67367 --- /dev/null +++ b/20080212/Demo/PIC32MX_MPLAB/RTOSDemo.mcp @@ -0,0 +1,94 @@ +[HEADER] +magic_cookie={66E99B07-E706-4689-9E80-9B2582898A13} +file_version=1.0 +[PATH_INFO] +BuildDirPolicy=BuildDirIsProjectDir +dir_src= +dir_bin= +dir_tmp= +dir_sin=..\..\Source\portable\MPLAB\PIC32MX;. +dir_inc=.;.;..\common\include;..\..\source\portable\mplab\pic32mx;..\..\source\include +dir_lib= +dir_lkr= +[CAT_FILTERS] +filter_src=*.s;*.c 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-Map="$(BINDIR_)$(TARGETBASE).map" +TS{0396C0A1-9052-4E4F-8B84-EF0162B1B4E9}= +[INSTRUMENTED_TRACE] +enable=0 +transport=0 +format=0 diff --git a/20080212/Demo/PIC32MX_MPLAB/RTOSDemo.mcs b/20080212/Demo/PIC32MX_MPLAB/RTOSDemo.mcs new file mode 100644 index 000000000..a44fd7f95 --- /dev/null +++ b/20080212/Demo/PIC32MX_MPLAB/RTOSDemo.mcs @@ -0,0 +1,271 @@ +[Header] +MagicCookie={0b13fe8c-dfe0-40eb-8900-6712719559a7} +Version=1.0 +[File000] +Location=C:\Temp\RC\1\Demo\PIC32MX_MPLAB\main.o +Folder=Intermediary +DeviceName=PIC32MX360F512L +LanguageToolSuiteID={14495C23-81F8-43F3-8A44-859C583D7760} +LanguageToolID={430F471F-7ECB-4852-A80D-DEF9A5C8E751} +LanguageToolLocation=C:\Devtools\Microchip\MPLAB C32\bin\pic32-gcc.exe +PPAD=$(BINDIR)||$(TMPDIR)||$(AINDIR)|..\..\Source\portable\MPLAB\PIC32MX;.||$(INCDIR)|.;.;..\common\include;..\..\source\portable\mplab\pic32mx;..\..\source\include||$(LIBDIR)||$(LKRDIR)|| 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zo)6BKqwwo_UA`QJU(bi-%Tf6C{OEi+3csF@$d{w=>-ngBISRj?kIk2(@ay@B`EnF~ zJ)f8>N4h{50!x8}=H`1O2Yt{mwCam8NG7v;-Q`1SnG zd^rlgo-fXqqwwqb-T879em!53FGu0m^9Sj$gzn<6S%Tf6Cd|195g-mUW zIf{RMxKa6X6n;G)n=eP<*Ygwe50!GxOyr{CYks zUyj1B=X3JqDExXpH&>40Umx!Ld^rlgo?nzNN8#7=dHHe_em%cDUyj1B=U3#*QTX-z z%6vHrzn;&}m!t6O`PKPy6n;HlkS|A}*K;n%S-5Srn+7zX0S#zC0~*kP1~i}n4QN0E v|K|;K$$Dm8vL5{N{X literal 0 HcmV?d00001 diff --git a/20080212/Demo/PIC32MX_MPLAB/RegisterTestTasks.s b/20080212/Demo/PIC32MX_MPLAB/RegisterTestTasks.s new file mode 100644 index 000000000..6b6c2d8e2 --- /dev/null +++ b/20080212/Demo/PIC32MX_MPLAB/RegisterTestTasks.s @@ -0,0 +1,339 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +#include +#include + + .set nomips16 + .set noreorder + + + .global vRegTest1 + .global vRegTest2 + + +/* .section .FreeRTOS, ax, @progbits */ + .set noreorder + .set noat + .ent vRegTest1 + +/* Address of $4 ulStatus1 is held in A0, so don't mess with the value of $4 */ + +vRegTest1: + addiu $1, $0, 0x11 + addiu $2, $0, 0x12 + addiu $3, $0, 0x13 + addiu $5, $0, 0x15 + addiu $6, $0, 0x16 + addiu $7, $0, 0x17 + addiu $8, $0, 0x18 + addiu $9, $0, 0x19 + addiu $10, $0, 0x110 + addiu $11, $0, 0x111 + addiu $12, $0, 0x112 + addiu $13, $0, 0x113 + addiu $14, $0, 0x114 + addiu $15, $0, 0x115 + addiu $16, $0, 0x116 + addiu $17, $0, 0x117 + addiu $18, $0, 0x118 + addiu $19, $0, 0x119 + addiu $20, $0, 0x120 + addiu $21, $0, 0x121 + addiu $22, $0, 0x122 + addiu $23, $0, 0x123 + addiu $24, $0, 0x124 + addiu $25, $0, 0x125 + addiu $30, $0, 0x130 + + #if configUSE_PREEMPTION == 0 + syscall 0 + #endif + + addiu $1, $1, -0x11 + beq $1, $0, .+12 + nop + sw $0, 0($4) + addiu $2, $2, -0x12 + beq $2, $0, .+12 + nop + sw $0, 0($4) + addiu $3, $3, -0x13 + beq $3, $0, .+12 + nop + sw $0, 0($4) + addiu $5, $5, -0x15 + beq $5, $0, .+12 + nop + sw $0, 0($4) + addiu $6, $6, -0x16 + beq $6, $0, .+12 + nop + sw $0, 0($4) + addiu $7, $7, -0x17 + beq $7, $0, .+12 + nop + sw $0, 0($4) + addiu $8, $8, -0x18 + beq $8, $0, .+12 + nop + sw $0, 0($4) + addiu $9, $9, -0x19 + beq $9, $0, .+12 + nop + sw $0, 0($4) + addiu $10, $10, -0x110 + beq $10, $0, .+12 + nop + sw $0, 0($4) + addiu $11, $11, -0x111 + beq $11, $0, .+12 + nop + sw $0, 0($4) + addiu $12, $12, -0x112 + beq $12, $0, .+12 + nop + sw $0, 0($4) + addiu $13, $13, -0x113 + beq $13, $0, .+12 + nop + sw $0, 0($4) + addiu $14, $14, -0x114 + beq $14, $0, .+12 + nop + sw $0, 0($4) + addiu $15, $15, -0x115 + beq $15, $0, .+12 + nop + sw $0, 0($4) + addiu $16, $16, -0x116 + beq $16, $0, .+12 + nop + sw $0, 0($4) + addiu $17, $17, -0x117 + beq $17, $0, .+12 + nop + sw $0, 0($4) + addiu $18, $18, -0x118 + beq $18, $0, .+12 + nop + sw $0, 0($4) + addiu $19, $19, -0x119 + beq $19, $0, .+12 + nop + sw $0, 0($4) + addiu $20, $20, -0x120 + beq $20, $0, .+12 + nop + sw $0, 0($4) + addiu $21, $21, -0x121 + beq $21, $0, .+12 + nop + sw $0, 0($4) + addiu $22, $22, -0x122 + beq $22, $0, .+12 + nop + sw $0, 0($4) + addiu $23, $23, -0x123 + beq $23, $0, .+12 + nop + sw $0, 0($4) + addiu $24, $24, -0x124 + beq $24, $0, .+12 + nop + sw $0, 0($4) + addiu $25, $25, -0x125 + beq $25, $0, .+12 + nop + sw $0, 0($4) + addiu $30, $30, -0x130 + beq $30, $0, .+12 + nop + sw $0, 0($4) + jr $31 + nop + + .end vRegTest1 + + +/* .section .FreeRTOS, ax, @progbits */ + .set noreorder + .set noat + .ent vRegTest2 + +vRegTest2: + + addiu $1, $0, 0x10 + addiu $2, $0, 0x20 + addiu $3, $0, 0x30 + addiu $5, $0, 0x50 + addiu $6, $0, 0x60 + addiu $7, $0, 0x70 + addiu $8, $0, 0x80 + addiu $9, $0, 0x90 + addiu $10, $0, 0x100 + addiu $11, $0, 0x110 + addiu $12, $0, 0x120 + addiu $13, $0, 0x130 + addiu $14, $0, 0x140 + addiu $15, $0, 0x150 + addiu $16, $0, 0x160 + addiu $17, $0, 0x170 + addiu $18, $0, 0x180 + addiu $19, $0, 0x190 + addiu $20, $0, 0x200 + addiu $21, $0, 0x210 + addiu $22, $0, 0x220 + addiu $23, $0, 0x230 + addiu $24, $0, 0x240 + addiu $25, $0, 0x250 + addiu $30, $0, 0x300 + + #if configUSE_PREEMPTION == 0 + syscall 0 + #endif + + addiu $1, $1, -0x10 + beq $1, $0, .+12 + nop + sw $0, 0($4) + addiu $2, $2, -0x20 + beq $2, $0, .+12 + nop + sw $0, 0($4) + addiu $3, $3, -0x30 + beq $3, $0, .+12 + nop + sw $0, 0($4) + addiu $5, $5, -0x50 + beq $5, $0, .+12 + nop + sw $0, 0($4) + addiu $6, $6, -0x60 + beq $6, $0, .+12 + nop + sw $0, 0($4) + addiu $7, $7, -0x70 + beq $7, $0, .+12 + nop + sw $0, 0($4) + addiu $8, $8, -0x80 + beq $8, $0, .+12 + nop + sw $0, 0($4) + addiu $9, $9, -0x90 + beq $9, $0, .+12 + nop + sw $0, 0($4) + addiu $10, $10, -0x100 + beq $10, $0, .+12 + nop + sw $0, 0($4) + addiu $11, $11, -0x110 + beq $11, $0, .+12 + nop + sw $0, 0($4) + addiu $12, $12, -0x120 + beq $12, $0, .+12 + nop + sw $0, 0($4) + addiu $13, $13, -0x130 + beq $13, $0, .+12 + nop + sw $0, 0($4) + addiu $14, $14, -0x140 + beq $14, $0, .+12 + nop + sw $0, 0($4) + addiu $15, $15, -0x150 + beq $15, $0, .+12 + nop + sw $0, 0($4) + addiu $16, $16, -0x160 + beq $16, $0, .+12 + nop + sw $0, 0($4) + addiu $17, $17, -0x170 + beq $17, $0, .+12 + nop + sw $0, 0($4) + addiu $18, $18, -0x180 + beq $18, $0, .+12 + nop + sw $0, 0($4) + addiu $19, $19, -0x190 + beq $19, $0, .+12 + nop + sw $0, 0($4) + addiu $20, $20, -0x200 + beq $20, $0, .+12 + nop + sw $0, 0($4) + addiu $21, $21, -0x210 + beq $21, $0, .+12 + nop + sw $0, 0($4) + addiu $22, $22, -0x220 + beq $22, $0, .+12 + nop + sw $0, 0($4) + addiu $23, $23, -0x230 + beq $23, $0, .+12 + nop + sw $0, 0($4) + addiu $24, $24, -0x240 + beq $24, $0, .+12 + nop + sw $0, 0($4) + addiu $25, $25, -0x250 + beq $25, $0, .+12 + nop + sw $0, 0($4) + addiu $30, $30, -0x300 + beq $30, $0, .+12 + nop + sw $0, 0($4) + jr $31 + nop + + .end vRegTest2 diff --git a/20080212/Demo/PIC32MX_MPLAB/lcd.c b/20080212/Demo/PIC32MX_MPLAB/lcd.c new file mode 100644 index 000000000..3f74e9fbf --- /dev/null +++ b/20080212/Demo/PIC32MX_MPLAB/lcd.c @@ -0,0 +1,249 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* peripheral library include */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* Demo includes. */ +#include "lcd.h" + +/* + * The LCD is written to by more than one task so is controlled by this + * 'gatekeeper' task. This is the only task that is actually permitted to + * access the LCD directly. Other tasks wanting to display a message send + * the message to the gatekeeper. + */ +static void vLCDTask( void *pvParameters ); + +/* + * Setup the peripherals required to communicate with the LCD. + */ +static void prvSetupLCD( void ); + +/* + * Move to the first (0) or second (1) row of the LCD. + */ +static void prvLCDGotoRow( unsigned portSHORT usRow ); + +/* + * Write a string of text to the LCD. + */ +static void prvLCDPutString( portCHAR *pcString ); + +/* + * Clear the LCD. + */ +static void prvLCDClear( void ); + +/*-----------------------------------------------------------*/ + +/* Brief delay to permit the LCD to catch up with commands. */ +#define lcdVERY_SHORT_DELAY ( 1 ) +#define lcdSHORT_DELAY ( 4 / portTICK_RATE_MS ) +#define lcdLONG_DELAY ( 15 / portTICK_RATE_MS ) + +/* LCD specific definitions. */ +#define LCD_CLEAR_DISPLAY_CMD 0x01 +#define LCD_CURSOR_HOME_CMD 0x02 +#define LCD_ENTRY_MODE_CMD 0x04 +#define LCD_ENTRY_MODE_INCREASE 0x02 +#define LCD_DISPLAY_CTRL_CMD 0x08 +#define LCD_DISPLAY_CTRL_DISPLAY_ON 0x04 +#define LCD_FUNCTION_SET_CMD 0x20 +#define LCD_FUNCTION_SET_8_BITS 0x10 +#define LCD_FUNCTION_SET_2_LINES 0x08 +#define LCD_FUNCTION_SET_LRG_FONT 0x04 +#define LCD_NEW_LINE 0xC0 +#define LCD_COMMAND_ADDRESS 0x00 +#define LCD_DATA_ADDRESS 0x01 + +/* The length of the queue used to send messages to the LCD gatekeeper task. */ +#define lcdQUEUE_SIZE 3 + +/*-----------------------------------------------------------*/ + +/* The queue used to send messages to the LCD task. */ +xQueueHandle xLCDQueue; + +/* LCD access functions. */ +static void prvLCDCommand( portCHAR cCommand ); +static void prvLCDData( portCHAR cChar ); + +/*-----------------------------------------------------------*/ + +xQueueHandle xStartLCDTask( void ) +{ + /* Create the queue used by the LCD task. Messages for display on the LCD + are received via this queue. */ + xLCDQueue = xQueueCreate( lcdQUEUE_SIZE, sizeof( xLCDMessage )); + + /* Start the task that will write to the LCD. The LCD hardware is + initialised from within the task itself so delays can be used. */ + xTaskCreate( vLCDTask, ( signed portCHAR * ) "LCD", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY + 1, NULL ); + + return xLCDQueue; +} +/*-----------------------------------------------------------*/ + +static void prvLCDGotoRow( unsigned portSHORT usRow ) +{ + if(usRow == 0) + { + prvLCDCommand( LCD_CURSOR_HOME_CMD ); + } + else + { + prvLCDCommand( LCD_NEW_LINE ); + } +} +/*-----------------------------------------------------------*/ + +static void prvLCDCommand( portCHAR cCommand ) +{ + PMPSetAddress( LCD_COMMAND_ADDRESS ); + PMPMasterWrite( cCommand ); + vTaskDelay( lcdSHORT_DELAY ); +} +/*-----------------------------------------------------------*/ + +static void prvLCDData( portCHAR cChar ) +{ + PMPSetAddress( LCD_DATA_ADDRESS ); + PMPMasterWrite( cChar ); + vTaskDelay( lcdVERY_SHORT_DELAY ); +} +/*-----------------------------------------------------------*/ + +static void prvLCDPutString( portCHAR *pcString ) +{ + /* Write out each character with appropriate delay between each. */ + while(*pcString) + { + prvLCDData(*pcString); + pcString++; + vTaskDelay(lcdSHORT_DELAY); + } +} +/*-----------------------------------------------------------*/ + +static void prvLCDClear(void) +{ + prvLCDCommand(LCD_CLEAR_DISPLAY_CMD); +} +/*-----------------------------------------------------------*/ + +static void prvSetupLCD(void) +{ + /* Wait for proper power up. */ + vTaskDelay( lcdLONG_DELAY ); + + /* Open the PMP port */ + mPMPOpen((PMP_ON | PMP_READ_WRITE_EN | PMP_CS2_CS1_EN | + PMP_LATCH_POL_HI | PMP_CS2_POL_HI | PMP_CS1_POL_HI | + PMP_WRITE_POL_HI | PMP_READ_POL_HI), + (PMP_MODE_MASTER1 | PMP_WAIT_BEG_4 | PMP_WAIT_MID_15 | + PMP_WAIT_END_4), + PMP_PEN_0, 0); + + /* Wait for the LCD to power up correctly. */ + vTaskDelay( lcdLONG_DELAY ); + vTaskDelay( lcdLONG_DELAY ); + vTaskDelay( lcdLONG_DELAY ); + + /* Set up the LCD function. */ + prvLCDCommand( LCD_FUNCTION_SET_CMD | LCD_FUNCTION_SET_8_BITS | LCD_FUNCTION_SET_2_LINES | LCD_FUNCTION_SET_LRG_FONT ); + + /* Turn the display on. */ + prvLCDCommand( LCD_DISPLAY_CTRL_CMD | LCD_DISPLAY_CTRL_DISPLAY_ON ); + + /* Clear the display. */ + prvLCDCommand( LCD_CLEAR_DISPLAY_CMD ); + vTaskDelay( lcdLONG_DELAY ); + + /* Increase the cursor. */ + prvLCDCommand( LCD_ENTRY_MODE_CMD | LCD_ENTRY_MODE_INCREASE ); + vTaskDelay( lcdLONG_DELAY ); + vTaskDelay( lcdLONG_DELAY ); + vTaskDelay( lcdLONG_DELAY ); +} +/*-----------------------------------------------------------*/ + +static void vLCDTask(void *pvParameters) +{ +xLCDMessage xMessage; +unsigned portSHORT usRow = 0; + + /* Initialise the hardware. This uses delays so must not be called prior + to the scheduler being started. */ + prvSetupLCD(); + + /* Welcome message. */ + prvLCDPutString( "www.FreeRTOS.org" ); + + for(;;) + { + /* Wait for a message to arrive that requires displaying. */ + while( xQueueReceive( xLCDQueue, &xMessage, portMAX_DELAY ) != pdPASS ); + + /* Clear the current display value. */ + prvLCDClear(); + + /* Switch rows each time so we can see that the display is still being + updated. */ + prvLCDGotoRow( usRow & 0x01 ); + usRow++; + prvLCDPutString( xMessage.pcMessage ); + + /* Delay the requested amount of time to ensure the text just written + to the LCD is not overwritten. */ + vTaskDelay( xMessage.xMinDisplayTime ); + } +} + + + + diff --git a/20080212/Demo/PIC32MX_MPLAB/lcd.h b/20080212/Demo/PIC32MX_MPLAB/lcd.h new file mode 100644 index 000000000..738560192 --- /dev/null +++ b/20080212/Demo/PIC32MX_MPLAB/lcd.h @@ -0,0 +1,64 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef LCD_INC_H +#define LCD_INC_H + +/* Create the task that will control the LCD. Returned is a handle to the queue +on which messages to get written to the LCD should be written. */ +xQueueHandle xStartLCDTask( void ); + +typedef struct +{ + /* The minimum amount of time the message should remain on the LCD without + being overwritten. */ + portTickType xMinDisplayTime; + + /* A pointer to the string to be displayed. */ + portCHAR *pcMessage; + +} xLCDMessage; + + +#endif /* LCD_INC_H */ + + diff --git a/20080212/Demo/PIC32MX_MPLAB/main.c b/20080212/Demo/PIC32MX_MPLAB/main.c new file mode 100644 index 000000000..af411fe9f --- /dev/null +++ b/20080212/Demo/PIC32MX_MPLAB/main.c @@ -0,0 +1,368 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + * Creates all the demo application tasks, then starts the scheduler. The WEB + * documentation provides more details of the standard demo application tasks. + * In addition to the standard demo tasks, the following tasks and tests are + * defined and/or created within this file: + * + * "Fast Interrupt Test" - A high frequency periodic interrupt is generated + * using a free running timer to demonstrate the use of the + * configKERNEL_INTERRUPT_PRIORITY configuration constant. The interrupt + * service routine measures the number of processor clocks that occur between + * each interrupt - and in so doing measures the jitter in the interrupt timing. + * The maximum measured jitter time is latched in the ulMaxJitter variable, and + * displayed on the LCD display by the 'LCD' task as described below. The + * fast interrupt is configured and handled in the timertest.c source file. + * + * "LCD" task - the LCD task is a 'gatekeeper' task. It is the only task that + * is permitted to access the display directly. Other tasks wishing to write a + * message to the LCD send the message on a queue to the LCD task instead of + * accessing the LCD themselves. The LCD task just blocks on the queue waiting + * for messages - waking and displaying the messages as they arrive. + * + * "Check" task - This only executes every three seconds but has the highest + * priority so is guaranteed to get processor time. Its main function is to + * check that all the standard demo tasks are still operational. Should any + * unexpected behaviour within a demo task be discovered the check task will + * write an error to the LCD (via the LCD task). If all the demo tasks are + * executing with their expected behaviour then the check task writes the + * maximum jitter time to the LCD (as described above) - again via the LCD task. + * + * "Register test" tasks - These tasks are used in part to test the kernel port. + * They set each processor register to a known value, then check that the + * register still contains that value. Each of the tasks sets the registers + * to different values, and will get swapping in and out between setting and + * then subsequently checking the register values. Discovery of an incorrect + * value would be indicative of an error in the task switching mechanism. + */ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* Demo application includes. */ +#include "partest.h" +#include "integer.h" +#include "blocktim.h" +#include "flash.h" +#include "semtest.h" +#include "GenQTest.h" +#include "QPeek.h" +#include "lcd.h" +#include "comtest2.h" +#include "timertest.h" + +#pragma config FPLLMUL = MUL_18, FPLLIDIV = DIV_2, FPLLODIV = DIV_1, FWDTEN = OFF +#pragma config POSCMOD = HS, FNOSC = PRIPLL, FPBDIV = DIV_2 + +/*-----------------------------------------------------------*/ + +/* The rate at which the LED controlled by the 'check' task will flash when no +errors have been detected. */ +#define mainNO_ERROR_PERIOD ( 3000 / portTICK_RATE_MS ) + +/* The rate at which the LED controlled by the 'check' task will flash when an +error has been detected. */ +#define mainERROR_PERIOD ( 500 ) + +/* The priorities of the various demo application tasks. */ +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainINTEGER_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY ) + +/* The LED controlled by the 'check' task. */ +#define mainCHECK_LED ( 7 ) + +/* The LED used by the comtest tasks. mainCOM_TEST_LED + 1 is also used. +See the comtest.c file for more information. */ +#define mainCOM_TEST_LED ( 4 ) + +/* Baud rate used by the comtest tasks. */ +#define mainCOM_TEST_BAUD_RATE ( 115200 ) + +/* Misc. */ +#define mainDONT_WAIT ( 0 ) + +/* Dimension the buffer used to hold the value of the maximum jitter time when +it is converted to a string. */ +#define mainMAX_STRING_LENGTH ( 20 ) + +/* The frequency at which the "fast interrupt test" interrupt will occur. */ +#define mainTEST_INTERRUPT_FREQUENCY ( 20000 ) + +/* The number of timer clocks we expect to occur between each "fast +interrupt test" interrupt. */ +#define mainEXPECTED_CLOCKS_BETWEEN_INTERRUPTS ( ( configCPU_CLOCK_HZ >> 1 ) / mainTEST_INTERRUPT_FREQUENCY ) + +/* The number of nano seconds between each core clock. */ +#define mainNS_PER_CLOCK ( ( unsigned portLONG ) ( ( 1.0 / ( double ) ( configCPU_CLOCK_HZ >> 1 ) ) * 1000000000.0 ) ) + +/*-----------------------------------------------------------*/ + +/* + * Setup the processor ready for the demo. + */ +static void prvSetupHardware( void ); + +/* + * Implements the 'check' task functionality as described at the top of this + * file. + */ +static void prvCheckTask( void *pvParameters ) __attribute__((noreturn)); + +/* + * Tasks that test the context switch mechanism by filling the processor + * registers with known values, then checking that the values contained + * within the registers is as expected. The tasks are likely to get swapped + * in and out between setting the register values and checking the register + * values. */ +static void prvTestTask1( void *pvParameters ); +static void prvTestTask2( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* The queue used to send messages to the LCD task. */ +static xQueueHandle xLCDQueue; + +/* Flag used by prvTestTask1() and prvTestTask2() to indicate their status +(pass/fail). */ +unsigned portLONG ulStatus1 = pdPASS; + +/* Variables incremented by prvTestTask1() and prvTestTask2() respectively on +each iteration of their function. This is used to detect either task stopping +their execution.. */ +unsigned portLONG ulRegTest1Cycles = 0, ulRegTest2Cycles = 0; + +/*-----------------------------------------------------------*/ + + +/* + * Create the demo tasks then start the scheduler. + */ +int main( void ) +{ + /* Configure any hardware required for this demo. */ + prvSetupHardware(); + + /* Create the LCD task - this returns the queue to use when writing + messages to the LCD. */ + xLCDQueue = xStartLCDTask(); + + /* Create all the other standard demo tasks. */ + vStartLEDFlashTasks( tskIDLE_PRIORITY ); + vCreateBlockTimeTasks(); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartIntegerMathTasks( mainINTEGER_TASK_PRIORITY ); + vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY ); + vStartQueuePeekTasks(); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); + + /* Create the tasks defined within this file. */ + xTaskCreate( prvTestTask1, "Tst1", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + xTaskCreate( prvTestTask2, "Tst2", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + + /* prvCheckTask uses sprintf so requires more stack. */ + xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE * 2, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Setup the high frequency, high priority, timer test. */ + vSetupTimerTest( mainTEST_INTERRUPT_FREQUENCY ); + + /* Finally start the scheduler. */ + vTaskStartScheduler(); + + /* Will only reach here if there is insufficient heap available to start + the scheduler. */ + return 0; +} +/*-----------------------------------------------------------*/ + +static void prvTestTask1( void *pvParameters ) +{ +extern void vRegTest1( unsigned long * ); + + for( ;; ) + { + /* Perform the register test function. */ + vRegTest1( &ulStatus1 ); + + /* Increment the counter so the check task knows we are still + running. */ + ulRegTest1Cycles++; + } +} +/*-----------------------------------------------------------*/ + +static void prvTestTask2( void *pvParameters ) +{ +extern void vRegTest2( unsigned long * ); + + for( ;; ) + { + /* Perform the register test function. */ + vRegTest2( &ulStatus1 ); + + /* Increment the counter so the check task knows we are still + running. */ + ulRegTest2Cycles++; + } +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Set the system and peripheral bus speeds and enable the program cache*/ + SYSTEMConfigPerformance( configCPU_CLOCK_HZ ); + + /* Setup to use the external interrupt controller. */ + INTEnableSystemMultiVectoredInt(); + + portDISABLE_INTERRUPTS(); + + /* Setup the digital IO for the LED's. */ + vParTestInitialise(); +} +/*-----------------------------------------------------------*/ + +static void prvCheckTask( void *pvParameters ) +{ +unsigned portLONG ulLastRegTest1Value = 0, ulLastRegTest2Value = 0, ulTicksToWait = mainNO_ERROR_PERIOD; +portTickType xLastExecutionTime; + +/* Buffer into which the maximum jitter time is written as a string. */ +static portCHAR cStringBuffer[ mainMAX_STRING_LENGTH ]; + +/* The maximum jitter time measured by the fast interrupt test. */ +extern unsigned portLONG ulMaxJitter ; +xLCDMessage xMessage = { ( 200 / portTICK_RATE_MS ), cStringBuffer }; + + /* Initialise the variable used to control our iteration rate prior to + its first use. */ + xLastExecutionTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Wait until it is time to run the tests again. */ + vTaskDelayUntil( &xLastExecutionTime, ulTicksToWait ); + + /* Has either register check 1 or 2 task discovered an error? */ + if( ulStatus1 != pdPASS ) + { + ulTicksToWait = mainERROR_PERIOD; + xMessage.pcMessage = "Error: Reg test1"; + } + + /* Check that the register test 1 task is still running. */ + if( ulLastRegTest1Value == ulRegTest1Cycles ) + { + ulTicksToWait = mainERROR_PERIOD; + xMessage.pcMessage = "Error: Reg test2"; + } + ulLastRegTest1Value = ulRegTest1Cycles; + + + /* Check that the register test 2 task is still running. */ + if( ulLastRegTest2Value == ulRegTest2Cycles ) + { + ulTicksToWait = mainERROR_PERIOD; + xMessage.pcMessage = "Error: Reg test3"; + } + ulLastRegTest2Value = ulRegTest2Cycles; + + + /* Have any of the standard demo tasks detected an error in their + operation? */ + if( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + ulTicksToWait = mainERROR_PERIOD; + xMessage.pcMessage = "Error: Gen Q"; + } + else if( xAreQueuePeekTasksStillRunning() != pdTRUE ) + { + ulTicksToWait = mainERROR_PERIOD; + xMessage.pcMessage = "Error: Q Peek"; + } + else if( xAreComTestTasksStillRunning() != pdTRUE ) + { + ulTicksToWait = mainERROR_PERIOD; + xMessage.pcMessage = "Error: COM test"; + } + else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + ulTicksToWait = mainERROR_PERIOD; + xMessage.pcMessage = "Error: Blck time"; + } + else if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + ulTicksToWait = mainERROR_PERIOD; + xMessage.pcMessage = "Error: Sem test"; + } + else if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + ulTicksToWait = mainERROR_PERIOD; + xMessage.pcMessage = "Error: Int math"; + } + + /* Write the max jitter time to the string buffer. It will only be + displayed if no errors have been detected. */ + sprintf( cStringBuffer, "%dns max jitter", ( int ) ( ( ulMaxJitter - mainEXPECTED_CLOCKS_BETWEEN_INTERRUPTS ) * mainNS_PER_CLOCK ) ); + + xQueueSend( xLCDQueue, &xMessage, mainDONT_WAIT ); + vParTestToggleLED( mainCHECK_LED ); + } +} +/*-----------------------------------------------------------*/ + +void vApplicationGeneralExceptionHandler( unsigned portLONG ulCause, unsigned portLONG ulStatus ) +{ + /* This overrides the definition provided by the kernel. Other exceptions + should be handled here. */ + for( ;; ); +} diff --git a/20080212/Demo/PIC32MX_MPLAB/serial/serial.c b/20080212/Demo/PIC32MX_MPLAB/serial/serial.c new file mode 100644 index 000000000..d2d93451e --- /dev/null +++ b/20080212/Demo/PIC32MX_MPLAB/serial/serial.c @@ -0,0 +1,196 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER. + +NOTE: This driver is primarily to test the scheduler functionality. It does +not effectively use the buffers or DMA and is therefore not intended to be +an example of an efficient driver. */ + +/* Standard include file. */ +#include +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "queue.h" +#include "task.h" + +/* Demo app include files. */ +#include "serial.h" + +/* Hardware setup. */ +#define serSET_FLAG ( 1 ) + +/* The queues used to communicate between tasks and ISR's. */ +static xQueueHandle xRxedChars; +static xQueueHandle xCharsForTx; + +/* Flag used to indicate the tx status. */ +static portBASE_TYPE xTxHasEnded; + +/*-----------------------------------------------------------*/ + +/* The UART interrupt handler. */ +void __attribute__( (interrupt(ipl1), vector(_UART2_VECTOR))) vU2InterruptWrapper( void ); + +/*-----------------------------------------------------------*/ + +xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) +{ +unsigned portSHORT usBRG; + + /* Create the queues used by the com test task. */ + xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + + /* Configure the UART and interrupts. */ + usBRG = (unsigned portSHORT)(( (float)configPERIPHERAL_CLOCK_HZ / ( (float)16 * (float)ulWantedBaud ) ) - (float)0.5); + OpenUART2( UART_EN, UART_RX_ENABLE | UART_TX_ENABLE | UART_INT_TX | UART_INT_RX_CHAR, usBRG ); + ConfigIntUART2( configKERNEL_INTERRUPT_PRIORITY | UART_INT_SUB_PR0 | UART_TX_INT_EN | UART_RX_INT_EN ); + + xTxHasEnded = pdTRUE; + + /* Only a single port is implemented so we don't need to return anything. */ + return NULL; +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) +{ + /* Only one port is supported. */ + ( void ) pxPort; + + /* Get the next character from the buffer. Return false if no characters + are available or arrive before xBlockTime expires. */ + if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) + { + return pdTRUE; + } + else + { + return pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) +{ + /* Only one port is supported. */ + ( void ) pxPort; + + /* Return false if after the block time there is no room on the Tx queue. */ + if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) + { + return pdFAIL; + } + + /* A critical section should not be required as xTxHasEnded will not be + written to by the ISR if it is already 0 (is this correct?). */ + if( xTxHasEnded ) + { + xTxHasEnded = pdFALSE; + IFS1bits.U2TXIF = serSET_FLAG; + } + + return pdPASS; +} +/*-----------------------------------------------------------*/ + +void vSerialClose( xComPortHandle xPort ) +{ +} +/*-----------------------------------------------------------*/ + +void vU2InterruptHandler( void ) +{ +/* Declared static to minimise stack use. */ +static portCHAR cChar; +static portBASE_TYPE xYieldRequired; + + xYieldRequired = pdFALSE; + + /* Are any Rx interrupts pending? */ + if( mU2RXGetIntFlag() ) + { + while( U2STAbits.URXDA ) + { + /* Retrieve the received character and place it in the queue of + received characters. */ + cChar = U2RXREG; + xYieldRequired = xQueueSendFromISR( xRxedChars, &cChar, xYieldRequired ); + } + mU2RXClearIntFlag(); + } + + /* Are any Tx interrupts pending? */ + if( mU2TXGetIntFlag() ) + { + while( !( U2STAbits.UTXBF ) ) + { + if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xYieldRequired ) == pdTRUE ) + { + /* Send the next character queued for Tx. */ + U2TXREG = cChar; + } + else + { + /* Queue empty, nothing to send. */ + xTxHasEnded = pdTRUE; + break; + } + } + + mU2TXClearIntFlag(); + } + + /* If sending or receiving necessitates a context switch, then switch now. */ + portEND_SWITCHING_ISR( xYieldRequired ); +} + + + + + + + diff --git a/20080212/Demo/PIC32MX_MPLAB/serial/serial_isr.S b/20080212/Demo/PIC32MX_MPLAB/serial/serial_isr.S new file mode 100644 index 000000000..15c9773a8 --- /dev/null +++ b/20080212/Demo/PIC32MX_MPLAB/serial/serial_isr.S @@ -0,0 +1,24 @@ +#include +#include +#include "ISR_Support.h" + + .set nomips16 + .set noreorder + + .extern vU2InterruptHandler + .extern xISRStackTop + .global vU2InterruptWrapper + + .set noreorder + .set noat + .ent vU2InterruptWrapper + +vU2InterruptWrapper: + + portSAVE_CONTEXT + jal vU2InterruptHandler + nop + portRESTORE_CONTEXT + + .end vU2InterruptWrapper + diff --git a/20080212/Demo/PIC32MX_MPLAB/timertest.c b/20080212/Demo/PIC32MX_MPLAB/timertest.c new file mode 100644 index 000000000..07a212fc5 --- /dev/null +++ b/20080212/Demo/PIC32MX_MPLAB/timertest.c @@ -0,0 +1,131 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* High speed timer test as described in main.c. */ + + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* Demo includes. */ +#include "partest.h" + +/* The number of interrupts to pass before we start looking at the jitter. */ +#define timerSETTLE_TIME 200 + +/* The maximum value the 16bit timer can contain. */ +#define timerMAX_COUNT 0xffff + + +/*-----------------------------------------------------------*/ + +/* The maximum time (in processor clocks) between two consecutive timer +interrupts so far. */ +unsigned portLONG ulMaxJitter = 0; + +/*-----------------------------------------------------------*/ + +void vSetupTimerTest( unsigned portSHORT usFrequencyHz ) +{ + /* T2 is used to generate interrupts. The core timer is used to provide an + accurate time measurement. */ + T2CON = 0; + TMR2 = 0; + + /* Timer 2 is going to interrupt at usFrequencyHz Hz. */ + PR2 = ( unsigned portSHORT ) ( configPERIPHERAL_CLOCK_HZ / ( unsigned portLONG ) usFrequencyHz ); + + /* Setup timer 2 interrupt priority to be above the kernel priority so + the timer jitter is not effected by the kernel activity. */ + ConfigIntTimer2( T2_INT_ON | ( configKERNEL_INTERRUPT_PRIORITY + 1 ) ); + + /* Clear the interrupt as a starting condition. */ + IFS0bits.T2IF = 0; + + /* Enable the interrupt. */ + IEC0bits.T2IE = 1; + + /* Start the timer. */ + T2CONbits.TON = 1; +} +/*-----------------------------------------------------------*/ + +void __attribute__( (interrupt(ipl0), vector(_TIMER_2_VECTOR))) vT2InterruptHandler( void ); +void vT2InterruptHandler( void ) +{ +static unsigned portLONG ulLastCount = 0, ulSettleCount = 0; +static unsigned portLONG ulThisCount, ulDifference; + + /* Capture the timer value as we enter the interrupt. */ + ulThisCount = _CP0_GET_COUNT(); + + if( ulSettleCount >= timerSETTLE_TIME ) + { + /* What is the difference between the timer value in this interrupt + and the value from the last interrupt. */ + ulDifference = ulThisCount - ulLastCount; + + /* Store the difference in the timer values if it is larger than the + currently stored largest value. The difference over and above the + expected difference will give the 'jitter' in the processing of these + interrupts. */ + if( ulDifference > ulMaxJitter ) + { + ulMaxJitter = ulDifference; + } + } + else + { + /* Don't bother storing any values for the first couple of + interrupts. */ + ulSettleCount++; + } + + /* Remember what the timer value was this time through, so we can calculate + the difference the next time through. */ + ulLastCount = ulThisCount; + + /* Clear the timer interrupt. */ + IFS0bits.T2IF = 0; +} + + diff --git a/20080212/Demo/PIC32MX_MPLAB/timertest.h b/20080212/Demo/PIC32MX_MPLAB/timertest.h new file mode 100644 index 000000000..a8c060386 --- /dev/null +++ b/20080212/Demo/PIC32MX_MPLAB/timertest.h @@ -0,0 +1,52 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef TIMER_TEST_H +#define TIMER_TEST_H + +/* Setup the high frequency timer interrupt. */ +void vSetupTimerTest( unsigned portSHORT usFrequencyHz ); + +#endif /* TIMER_TEST_H */ + + + diff --git a/20080212/Demo/WizNET_DEMO_GCC_ARM7/FreeRTOSConfig.h b/20080212/Demo/WizNET_DEMO_GCC_ARM7/FreeRTOSConfig.h new file mode 100644 index 000000000..d4fb9a96e --- /dev/null +++ b/20080212/Demo/WizNET_DEMO_GCC_ARM7/FreeRTOSConfig.h @@ -0,0 +1,91 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include + + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 58982400 ) /* =14.7456MHz xtal multiplied by 4 using the PLL. */ +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 128 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 23 * 1024 ) ) +#define configMAX_TASK_NAME_LEN ( 16 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + + + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/WizNET_DEMO_GCC_ARM7/HTTP_Serv.c b/20080212/Demo/WizNET_DEMO_GCC_ARM7/HTTP_Serv.c new file mode 100644 index 000000000..3597f3fac --- /dev/null +++ b/20080212/Demo/WizNET_DEMO_GCC_ARM7/HTTP_Serv.c @@ -0,0 +1,96 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +/* Standard includes. */ +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Application includes. */ +#include "tcp.h" + +/* Misc constants. */ +#define tcpPOLL_DELAY ( ( portTickType ) 12 / portTICK_RATE_MS ) +#define tcpCONNECTION_DELAY ( ( portTickType ) 8 / portTICK_RATE_MS ) +/*-----------------------------------------------------------*/ + +/* + * This task initialises the hardware then processes one TCP connection at a + * time. When an HTTP client connects we just simply send a single page then + * disconnect - reset the socket data and wait for the next connection. + */ +void vHTTPServerTask( void *pvParameters ) +{ + /* Reset the network hardware. */ + vTCPHardReset(); + + /* Loop, processing connections are they arrive. */ + for( ;; ) + { + /* Initialise the TCP interface. + + The current minimal implementation does not check for buffer overflows + in the WIZnet hardware, so simply resets all the buffers for each + connection - and only processes one connection at a time. */ + if( lTCPSoftReset() ) + { + /* Create the socket that is going to accept incoming connections. */ + if( lTCPCreateSocket() ) + { + /* Wait for a connection. */ + vTCPListen(); + + /* Process connections as they arrive. This function will only + return once the connection has been closed. */ + lProcessConnection(); + } + } + + /* If we get here then the connection completed or failed. Wait a + while then try or start again. */ + vTaskDelay( tcpCONNECTION_DELAY ); + } +} + diff --git a/20080212/Demo/WizNET_DEMO_GCC_ARM7/HTTP_Serv.h b/20080212/Demo/WizNET_DEMO_GCC_ARM7/HTTP_Serv.h new file mode 100644 index 000000000..291180238 --- /dev/null +++ b/20080212/Demo/WizNET_DEMO_GCC_ARM7/HTTP_Serv.h @@ -0,0 +1,48 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef HTTP_H +#define HTTP_H + +void vHTTPServerTask( void *pvParameters ); + +#endif diff --git a/20080212/Demo/WizNET_DEMO_GCC_ARM7/Makefile b/20080212/Demo/WizNET_DEMO_GCC_ARM7/Makefile new file mode 100644 index 000000000..e1eecc337 --- /dev/null +++ b/20080212/Demo/WizNET_DEMO_GCC_ARM7/Makefile @@ -0,0 +1,116 @@ +# FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. +# +# This file is part of the FreeRTOS.org distribution. +# +# FreeRTOS.org is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# FreeRTOS.org is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with FreeRTOS.org; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +# +# A special exception to the GPL can be applied should you wish to distribute +# a combined work that includes FreeRTOS.org, without being obliged to provide +# the source code for any proprietary components. See the licensing section +# of http://www.FreeRTOS.org for full details of how and when the exception +# can be applied. +# +# *************************************************************************** +# See http://www.FreeRTOS.org for documentation, latest information, license +# and contact details. Please ensure to read the configuration and relevant +# port sections of the online documentation. +# *************************************************************************** + + +CC=arm-elf-gcc +OBJCOPY=arm-elf-objcopy +ARCH=arm-elf-ar +CRT0=boot.s +USE_THUMB_MODE=YES +DEBUG=-g +OPTIM=-Os +RUN_MODE=RUN_FROM_ROM +LDSCRIPT=lpc2106-rom.ld + + +# +# CFLAGS common to both the THUMB and ARM mode builds +# +CFLAGS=-Wall -D $(RUN_MODE) -D GCC_ARM7 -I. -I../../Source/include \ + -I../Common/include $(DEBUG) -mcpu=arm7tdmi -T$(LDSCRIPT) \ + -Wcast-align $(OPTIM) -fomit-frame-pointer + +ifeq ($(USE_THUMB_MODE),YES) + CFLAGS += -mthumb-interwork -D THUMB_INTERWORK + THUMB_FLAGS=-mthumb +endif + + +LINKER_FLAGS=-Xlinker -oWebServeDemo.elf -Xlinker -M -Xlinker -Map=WebServeDemo.map + +# +# Source files that can be built to THUMB mode. +# +THUMB_SRC = \ +../../Source/tasks.c \ +../../Source/queue.c \ +../../Source/list.c \ +../../Source/portable/MemMang/heap_2.c \ +../../Source/portable/GCC/ARM7_LPC2000/port.c \ +../Common/Minimal/flash.c \ +../Common/Minimal/dynamic.c \ +../Common/Minimal/semtest.c \ +../Common/Minimal/PollQ.c \ +../Common/Minimal/BlockQ.c \ +../Common/Minimal/integer.c \ +../ARM7_LPC2106_GCC/ParTest/ParTest.c \ +main.c \ +TCP.c \ +HTTP_Serv.c \ +i2c.c + +# +# Source files that must be built to ARM mode. +# +ARM_SRC = \ +../../Source/portable/GCC/ARM7_LPC2000/portISR.c \ +i2cISR.c \ +TCPISR.c + +# +# Define all object files. +# +ARM_OBJ = $(ARM_SRC:.c=.o) +THUMB_OBJ = $(THUMB_SRC:.c=.o) + +WebServeDemo.hex : WebServeDemo.elf + $(OBJCOPY) WebServeDemo.elf -O ihex WebServeDemo.hex + +WebServeDemo.elf : $(ARM_OBJ) $(THUMB_OBJ) $(CRT0) Makefile + $(CC) $(CFLAGS) $(ARM_OBJ) $(THUMB_OBJ) -nostartfiles $(CRT0) $(LINKER_FLAGS) + +$(THUMB_OBJ) : %.o : %.c $(LDSCRIPT) Makefile + $(CC) -c $(THUMB_FLAGS) $(CFLAGS) $< -o $@ + +$(ARM_OBJ) : %.o : %.c $(LDSCRIPT) Makefile + $(CC) -c $(CFLAGS) $< -o $@ + +clean : + touch makefile + + + + + + + + + + diff --git a/20080212/Demo/WizNET_DEMO_GCC_ARM7/TCP.c b/20080212/Demo/WizNET_DEMO_GCC_ARM7/TCP.c new file mode 100644 index 000000000..e05bfa658 --- /dev/null +++ b/20080212/Demo/WizNET_DEMO_GCC_ARM7/TCP.c @@ -0,0 +1,750 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + Changes from V3.2.3 + + + Modified char* types to compile without warning when using GCC V4.0.1. + + Corrected the address to which the MAC address is written. Thanks to + Bill Knight for this correction. + + Changes from V3.2.4 + + + Changed the default MAC address to something more realistic. + +*/ + +/* Standard includes. */ +#include +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" +#include "tcp.h" +#include "serial.h" + +/* Application includes. */ +#include "i2c.h" +#include "html_pages.h" + +/*-----------------------------------------------------------*/ + +/* Hardwired i2c address of the WIZNet device. */ +#define tcpDEVICE_ADDRESS ( ( unsigned portCHAR ) 0x00 ) + +/* Constants used to configure the Tx and Rx buffer sizes within the WIZnet +device. */ +#define tcp8K_RX ( ( unsigned portCHAR ) 0x03 ) +#define tcp8K_TX ( ( unsigned portCHAR ) 0x03 ) + +/* Constants used to generate the WIZnet internal buffer addresses. */ +#define tcpSINGLE_SOCKET_ADDR_MASK ( ( unsigned portLONG ) 0x1fff ) +#define tcpSINGLE_SOCKET_ADDR_OFFSET ( ( unsigned portLONG ) 0x4000 ) + +/* Bit definitions of the commands that can be sent to the command register. */ +#define tcpRESET_CMD ( ( unsigned portCHAR ) 0x80 ) +#define tcpSYS_INIT_CMD ( ( unsigned portCHAR ) 0x01 ) +#define tcpSOCK_STREAM ( ( unsigned portCHAR ) 0x01 ) +#define tcpSOCK_INIT ( ( unsigned portCHAR ) 0x02 ) +#define tcpLISTEN_CMD ( ( unsigned portCHAR ) 0x08 ) +#define tcpRECEIVE_CMD ( ( unsigned portCHAR ) 0x40 ) +#define tcpDISCONNECT_CMD ( ( unsigned portCHAR ) 0x10 ) +#define tcpSEND_CMD ( ( unsigned portCHAR ) 0x20 ) + +/* Constants required to handle the interrupts. */ +#define tcpCLEAR_EINT0 ( 1 ) +#define i2cCLEAR_ALL_INTERRUPTS ( ( unsigned portCHAR ) 0xff ) +#define i2cCHANNEL_0_ISR_ENABLE ( ( unsigned portCHAR ) 0x01 ) +#define i2cCHANNEL_0_ISR_DISABLE ( ( unsigned portCHAR ) 0x00 ) +#define tcpWAKE_ON_EINT0 ( 1 ) +#define tcpENABLE_EINT0_FUNCTION ( ( unsigned portLONG ) 0x01 ) +#define tcpEINT0_VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x4000 ) +#define tcpEINT0_VIC_CHANNEL ( ( unsigned portLONG ) 14 ) +#define tcpEINT0_VIC_ENABLE ( ( unsigned portLONG ) 0x0020 ) + +/* Various delays used in the driver. */ +#define tcpRESET_DELAY ( ( portTickType ) 16 / portTICK_RATE_MS ) +#define tcpINIT_DELAY ( ( portTickType ) 500 / portTICK_RATE_MS ) +#define tcpLONG_DELAY ( ( portTickType ) 500 / portTICK_RATE_MS ) +#define tcpSHORT_DELAY ( ( portTickType ) 5 / portTICK_RATE_MS ) +#define tcpCONNECTION_WAIT_DELAY ( ( portTickType ) 100 / portTICK_RATE_MS ) +#define tcpNO_DELAY ( ( portTickType ) 0 ) + +/* Length of the data to read for various register reads. */ +#define tcpSTATUS_READ_LEN ( ( unsigned portLONG ) 1 ) +#define tcpSHADOW_READ_LEN ( ( unsigned portLONG ) 1 ) + +/* Register addresses within the WIZnet device. */ +#define tcpCOMMAND_REG ( ( unsigned portSHORT ) 0x0000 ) +#define tcpGATEWAY_ADDR_REG ( ( unsigned portSHORT ) 0x0080 ) +#define tcpSUBNET_MASK_REG ( ( unsigned portSHORT ) 0x0084 ) +#define tcpSOURCE_HA_REG ( ( unsigned portSHORT ) 0x0088 ) +#define tpcSOURCE_IP_REG ( ( unsigned portSHORT ) 0x008E ) +#define tpcSOCKET_OPT_REG ( ( unsigned portSHORT ) 0x00A1 ) +#define tcpSOURCE_PORT_REG ( ( unsigned portSHORT ) 0x00AE ) +#define tcpTX_WRITE_POINTER_REG ( ( unsigned portSHORT ) 0x0040 ) +#define tcpTX_READ_POINTER_REG ( ( unsigned portSHORT ) 0x0044 ) +#define tcpTX_ACK_POINTER_REG ( ( unsigned portSHORT ) 0x0018 ) +#define tcpTX_MEM_SIZE_REG ( ( unsigned portSHORT ) 0x0096 ) +#define tcpRX_MEM_SIZE_REG ( ( unsigned portSHORT ) 0x0095 ) +#define tcpINTERRUPT_STATUS_REG ( ( unsigned portSHORT ) 0x0004 ) +#define tcpTX_WRITE_SHADOW_REG ( ( unsigned portSHORT ) 0x01F0 ) +#define tcpTX_ACK_SHADOW_REG ( ( unsigned portSHORT ) 0x01E2 ) +#define tcpISR_MASK_REG ( ( unsigned portSHORT ) 0x0009 ) +#define tcpINTERRUPT_REG ( ( unsigned portSHORT ) 0x0008 ) +#define tcpSOCKET_STATE_REG ( ( unsigned portSHORT ) 0x00a0 ) + +/* Constants required for hardware setup. */ +#define tcpRESET_ACTIVE_LOW ( ( unsigned portLONG ) 0x20 ) +#define tcpRESET_ACTIVE_HIGH ( ( unsigned portLONG ) 0x10 ) + +/* Constants defining the source of the WIZnet ISR. */ +#define tcpISR_SYS_INIT ( ( unsigned portCHAR ) 0x01 ) +#define tcpISR_SOCKET_INIT ( ( unsigned portCHAR ) 0x02 ) +#define tcpISR_ESTABLISHED ( ( unsigned portCHAR ) 0x04 ) +#define tcpISR_CLOSED ( ( unsigned portCHAR ) 0x08 ) +#define tcpISR_TIMEOUT ( ( unsigned portCHAR ) 0x10 ) +#define tcpISR_TX_COMPLETE ( ( unsigned portCHAR ) 0x20 ) +#define tcpISR_RX_COMPLETE ( ( unsigned portCHAR ) 0x40 ) + +/* Constants defining the socket status bits. */ +#define tcpSTATUS_ESTABLISHED ( ( unsigned portCHAR ) 0x06 ) +#define tcpSTATUS_LISTEN ( ( unsigned portCHAR ) 0x02 ) + +/* Misc constants. */ +#define tcpNO_STATUS_BITS ( ( unsigned portCHAR ) 0x00 ) +#define i2cNO_ADDR_REQUIRED ( ( unsigned portSHORT ) 0x0000 ) +#define i2cNO_DATA_REQUIRED ( 0x0000 ) +#define tcpISR_QUEUE_LENGTH ( ( unsigned portBASE_TYPE ) 10 ) +#define tcpISR_QUEUE_ITEM_SIZE ( ( unsigned portBASE_TYPE ) 0 ) +#define tcpBUFFER_LEN ( 4 * 1024 ) +#define tcpMAX_REGISTER_LEN ( 4 ) +#define tcpMAX_ATTEMPTS_TO_CHECK_BUFFER ( 6 ) +#define tcpMAX_NON_LISTEN_STAUS_READS ( 5 ) + +/* Message definitions. The IP address, MAC address, gateway address, etc. +is set here! */ +const unsigned portCHAR const ucDataGAR[] = { 172, 25, 218, 3 }; /* Gateway address. */ +const unsigned portCHAR const ucDataMSR[] = { 255, 255, 255, 0 }; /* Subnet mask. */ +const unsigned portCHAR const ucDataSIPR[] = { 172, 25, 218, 201 };/* IP address. */ +const unsigned portCHAR const ucDataSHAR[] = { 00, 23, 30, 41, 15, 26 }; /* MAC address - DO NOT USE THIS ON A PUBLIC NETWORK! */ + +/* Other fixed messages. */ +const unsigned portCHAR const ucDataReset[] = { tcpRESET_CMD }; +const unsigned portCHAR const ucDataInit[] = { tcpSYS_INIT_CMD }; +const unsigned portCHAR const ucDataProtocol[] = { tcpSOCK_STREAM }; +const unsigned portCHAR const ucDataPort[] = { 0xBA, 0xCC }; +const unsigned portCHAR const ucDataSockInit[] = { tcpSOCK_INIT }; +const unsigned portCHAR const ucDataTxWritePointer[] = { 0x11, 0x22, 0x00, 0x00 }; +const unsigned portCHAR const ucDataTxAckPointer[] = { 0x11, 0x22, 0x00, 0x00 }; +const unsigned portCHAR const ucDataTxReadPointer[] = { 0x11, 0x22, 0x00, 0x00 }; +const unsigned portCHAR const ucDataListen[] = { tcpLISTEN_CMD }; +const unsigned portCHAR const ucDataReceiveCmd[] = { tcpRECEIVE_CMD }; +const unsigned portCHAR const ucDataSetTxBufSize[] = { tcp8K_TX }; +const unsigned portCHAR const ucDataSetRxBufSize[] = { tcp8K_RX }; +const unsigned portCHAR const ucDataSend[] = { tcpSEND_CMD }; +const unsigned portCHAR const ucDataDisconnect[] = { tcpDISCONNECT_CMD }; +const unsigned portCHAR const ucDataEnableISR[] = { i2cCHANNEL_0_ISR_ENABLE }; +const unsigned portCHAR const ucDataDisableISR[] = { i2cCHANNEL_0_ISR_DISABLE }; +const unsigned portCHAR const ucDataClearInterrupt[] = { i2cCLEAR_ALL_INTERRUPTS }; + +static xSemaphoreHandle xMessageComplete = NULL; +xQueueHandle xTCPISRQueue = NULL; + +/* Dynamically generate and send an html page. */ +static void prvSendSamplePage( void ); + +/* Read a register from the WIZnet device via the i2c interface. */ +static void prvReadRegister( unsigned portCHAR *pucDestination, unsigned portSHORT usAddress, unsigned portLONG ulLength ); + +/* Send the entire Tx buffer (the Tx buffer within the WIZnet device). */ +static void prvFlushBuffer( unsigned portLONG ulTxAddress ); + +/* Write a string to the WIZnet Tx buffer. */ +static void prvWriteString( const portCHAR * const pucTxBuffer, portLONG lTxLen, unsigned portLONG *pulTxAddress ); + +/* Convert a number to a string. */ +void ultoa( unsigned portLONG ulVal, portCHAR *pcBuffer, portLONG lIgnore ); + +/*-----------------------------------------------------------*/ + +void ultoa( unsigned portLONG ulVal, portCHAR *pcBuffer, portLONG lIgnore ) +{ +unsigned portLONG lNibble; +portLONG lIndex; + + /* Simple routine to convert an unsigned long value into a string in hex + format. */ + + /* For each nibble in the number we are converting. */ + for( lIndex = 0; lIndex < ( sizeof( ulVal ) * 2 ); lIndex++ ) + { + /* Take the top four bits of the number. */ + lNibble = ( ulVal >> 28 ); + + /* We are converting it to a hex string, so is the number in the range + 0-10 or A-F? */ + if( lNibble < 10 ) + { + pcBuffer[ lIndex ] = '0' + lNibble; + } + else + { + lNibble -= 10; + pcBuffer[ lIndex ] = 'A' + lNibble; + } + + /* Shift off the top nibble so we use the next nibble next time around. */ + ulVal <<= 4; + } + + /* Mark the end of the string with a null terminator. */ + pcBuffer[ lIndex ] = 0x00; +} +/*-----------------------------------------------------------*/ + +static void prvReadRegister( unsigned portCHAR *pucDestination, unsigned portSHORT usAddress, unsigned portLONG ulLength ) +{ +unsigned portCHAR ucRxBuffer[ tcpMAX_REGISTER_LEN ]; + + /* Read a register value from the WIZnet device. */ + + /* First write out the address of the register we want to read. */ + i2cMessage( ucRxBuffer, i2cNO_DATA_REQUIRED, tcpDEVICE_ADDRESS, usAddress, i2cWRITE, NULL, portMAX_DELAY ); + + /* Then read back from that address. */ + i2cMessage( ( unsigned portCHAR * ) pucDestination, ulLength, tcpDEVICE_ADDRESS, i2cNO_ADDR_REQUIRED, i2cREAD, xMessageComplete, portMAX_DELAY ); + + /* I2C messages are queued so use the semaphore to wait for the read to + complete - otherwise we will leave this function before the I2C + transactions have completed. */ + xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ); +} +/*-----------------------------------------------------------*/ + +void vTCPHardReset( void ) +{ + /* Physical reset of the WIZnet device by using the GPIO lines to hold the + WIZnet reset lines active for a few milliseconds. */ + + /* Make sure the interrupt from the WIZnet is disabled. */ + VICIntEnClear |= tcpEINT0_VIC_CHANNEL_BIT; + + /* If xMessageComplete is NULL then this is the first time that this + function has been called and the queue and semaphore used in this file + have not yet been created. */ + if( xMessageComplete == NULL ) + { + /* Create and obtain the semaphore used when we want to wait for an i2c + message to be completed. */ + vSemaphoreCreateBinary( xMessageComplete ); + xSemaphoreTake( xMessageComplete, tcpNO_DELAY ); + + /* Create the queue used to communicate between the WIZnet and TCP tasks. */ + xTCPISRQueue = xQueueCreate( tcpISR_QUEUE_LENGTH, tcpISR_QUEUE_ITEM_SIZE ); + } + + /* Use the GPIO to reset the network hardware. */ + GPIO_IOCLR = tcpRESET_ACTIVE_LOW; + GPIO_IOSET = tcpRESET_ACTIVE_HIGH; + + /* Delay with the network hardware in reset for a short while. */ + vTaskDelay( tcpRESET_DELAY ); + + GPIO_IOCLR = tcpRESET_ACTIVE_HIGH; + GPIO_IOSET = tcpRESET_ACTIVE_LOW; + + vTaskDelay( tcpINIT_DELAY ); + + /* Setup the EINT0 to interrupt on required events from the WIZnet device. + First enable the EINT0 function of the pin. */ + PCB_PINSEL1 |= tcpENABLE_EINT0_FUNCTION; + + /* We want the TCP comms to wake us from power save. */ + SCB_EXTWAKE = tcpWAKE_ON_EINT0; + + /* Install the ISR into the VIC - but don't enable it yet! */ + portENTER_CRITICAL(); + { + extern void ( vEINT0_ISR_Wrapper )( void ); + + VICIntSelect &= ~( tcpEINT0_VIC_CHANNEL_BIT ); + VICVectAddr3 = ( portLONG ) vEINT0_ISR_Wrapper; + + VICVectCntl3 = tcpEINT0_VIC_CHANNEL | tcpEINT0_VIC_ENABLE; + } + portEXIT_CRITICAL(); + + /* Enable interrupts in the WIZnet itself. */ + i2cMessage( ucDataEnableISR, sizeof( ucDataEnableISR ), tcpDEVICE_ADDRESS, tcpISR_MASK_REG, i2cWRITE, NULL, portMAX_DELAY ); + + vTaskDelay( tcpLONG_DELAY ); +} +/*-----------------------------------------------------------*/ + +portLONG lTCPSoftReset( void ) +{ +unsigned portCHAR ucStatus; +extern volatile portLONG lTransactionCompleted; + + /* Send a message to the WIZnet device to tell it set all it's registers + back to their default states. Then setup the WIZnet device as required. */ + + /* Reset the internal WIZnet registers. */ + i2cMessage( ucDataReset, sizeof( ucDataReset ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY ); + + /* Now we can configure the protocol. Here the MAC address, gateway + address, subnet mask and IP address are configured. */ + i2cMessage( ucDataSHAR, sizeof( ucDataSHAR ), tcpDEVICE_ADDRESS, tcpSOURCE_HA_REG, i2cWRITE, NULL, portMAX_DELAY ); + i2cMessage( ucDataGAR, sizeof( ucDataGAR ), tcpDEVICE_ADDRESS, tcpGATEWAY_ADDR_REG, i2cWRITE, NULL, portMAX_DELAY ); + i2cMessage( ucDataMSR, sizeof( ucDataMSR ), tcpDEVICE_ADDRESS, tcpSUBNET_MASK_REG, i2cWRITE, NULL, portMAX_DELAY ); + i2cMessage( ucDataSIPR, sizeof( ucDataSIPR ), tcpDEVICE_ADDRESS, tpcSOURCE_IP_REG, i2cWRITE, NULL, portMAX_DELAY ); + + /* Next the memory buffers are configured to give all the WIZnet internal + memory over to a single socket. This gives the socket the maximum internal + Tx and Rx buffer space. */ + i2cMessage( ucDataSetTxBufSize, sizeof( ucDataSetTxBufSize ), tcpDEVICE_ADDRESS, tcpTX_MEM_SIZE_REG, i2cWRITE, NULL, portMAX_DELAY ); + i2cMessage( ucDataSetRxBufSize, sizeof( ucDataSetRxBufSize ), tcpDEVICE_ADDRESS, tcpRX_MEM_SIZE_REG, i2cWRITE, NULL, portMAX_DELAY ); + + /* Send the sys init command so the above parameters take effect. */ + i2cMessage( ucDataInit, sizeof( ucDataInit ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY ); + + /* Seems to like a little wait here. */ + vTaskDelay( tcpINIT_DELAY ); + + /* Read back the status to ensure the system initialised ok. */ + prvReadRegister( &ucStatus, tcpINTERRUPT_STATUS_REG, tcpSTATUS_READ_LEN ); + + /* We should find that the sys init was successful. */ + if( ucStatus != tcpISR_SYS_INIT ) + { + return ( portLONG ) pdFAIL; + } + + /* No i2c errors yet. */ + portENTER_CRITICAL(); + lTransactionCompleted = pdTRUE; + portEXIT_CRITICAL(); + + return ( portLONG ) pdPASS; +} +/*-----------------------------------------------------------*/ + +portLONG lTCPCreateSocket( void ) +{ +unsigned portCHAR ucStatus; + + /* Create and configure a socket. */ + + /* Setup and init the socket. Here the port number is set and the socket + is initialised. */ + i2cMessage( ucDataProtocol, sizeof( ucDataProtocol),tcpDEVICE_ADDRESS, tpcSOCKET_OPT_REG, i2cWRITE, NULL, portMAX_DELAY ); + i2cMessage( ucDataPort, sizeof( ucDataPort), tcpDEVICE_ADDRESS, tcpSOURCE_PORT_REG, i2cWRITE, NULL, portMAX_DELAY ); + i2cMessage( ucDataSockInit, sizeof( ucDataSockInit),tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, xMessageComplete, portMAX_DELAY ); + + /* Wait for the Init command to be sent. */ + if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) ) + { + /* For some reason the message was not transmitted within our block + period. */ + return ( portLONG ) pdFAIL; + } + + /* Allow the socket to initialise. */ + vTaskDelay( tcpINIT_DELAY ); + + /* Read back the status to ensure the socket initialised ok. */ + prvReadRegister( &ucStatus, tcpINTERRUPT_STATUS_REG, tcpSTATUS_READ_LEN ); + + /* We should find that the socket init was successful. */ + if( ucStatus != tcpISR_SOCKET_INIT ) + { + return ( portLONG ) pdFAIL; + } + + + /* Setup the Tx pointer registers to indicate that the Tx buffer is empty. */ + i2cMessage( ucDataTxReadPointer, sizeof( ucDataTxReadPointer ), tcpDEVICE_ADDRESS, tcpTX_READ_POINTER_REG, i2cWRITE, NULL, portMAX_DELAY ); + vTaskDelay( tcpSHORT_DELAY ); + i2cMessage( ucDataTxWritePointer, sizeof( ucDataTxWritePointer ), tcpDEVICE_ADDRESS, tcpTX_WRITE_POINTER_REG, i2cWRITE, NULL, portMAX_DELAY ); + vTaskDelay( tcpSHORT_DELAY ); + i2cMessage( ucDataTxAckPointer, sizeof( ucDataTxAckPointer ), tcpDEVICE_ADDRESS, tcpTX_ACK_POINTER_REG, i2cWRITE, NULL, portMAX_DELAY ); + vTaskDelay( tcpSHORT_DELAY ); + + return ( portLONG ) pdPASS; +} +/*-----------------------------------------------------------*/ + +void vTCPListen( void ) +{ +unsigned portCHAR ucISR; + + /* Start a passive listen on the socket. */ + + /* Enable interrupts in the WizNet device after ensuring none are + currently pending. */ + while( SCB_EXTINT & tcpCLEAR_EINT0 ) + { + /* The WIZnet device is still asserting and interrupt so tell it to + clear. */ + i2cMessage( ucDataClearInterrupt, sizeof( ucDataClearInterrupt ), tcpDEVICE_ADDRESS, tcpINTERRUPT_REG, i2cWRITE, xMessageComplete, portMAX_DELAY ); + xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ); + + vTaskDelay( 1 ); + SCB_EXTINT = tcpCLEAR_EINT0; + } + + while( xQueueReceive( xTCPISRQueue, &ucISR, tcpNO_DELAY ) ) + { + /* Just clearing the queue used by the ISR routine to tell this task + that the WIZnet device needs attention. */ + } + + /* Now all the pending interrupts have been cleared we can enable the + processor interrupts. */ + VICIntEnable |= tcpEINT0_VIC_CHANNEL_BIT; + + /* Then start listening for incoming connections. */ + i2cMessage( ucDataListen, sizeof( ucDataListen ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY ); +} +/*-----------------------------------------------------------*/ + +portLONG lProcessConnection( void ) +{ +unsigned portCHAR ucISR, ucState, ucLastState = 2, ucShadow; +extern volatile portLONG lTransactionCompleted; +portLONG lSameStateCount = 0, lDataSent = pdFALSE; +unsigned portLONG ulWritePointer, ulAckPointer; + + /* No I2C errors can yet have occurred. */ + portENTER_CRITICAL(); + lTransactionCompleted = pdTRUE; + portEXIT_CRITICAL(); + + /* Keep looping - processing interrupts, until we have completed a + transaction. This uses the WIZnet in it's simplest form. The socket + accepts a connection - we process the connection - then close the socket. + We then go back to reinitialise everything and start again. */ + while( lTransactionCompleted == pdTRUE ) + { + /* Wait for a message on the queue from the WIZnet ISR. When the + WIZnet device asserts an interrupt the ISR simply posts a message + onto this queue to wake this task. */ + if( xQueueReceive( xTCPISRQueue, &ucISR, tcpCONNECTION_WAIT_DELAY ) ) + { + /* The ISR posted a message on this queue to tell us that the + WIZnet device asserted an interrupt. The ISR cannot process + an I2C message so cannot tell us what caused the interrupt so + we have to query the device here. This task is the highest + priority in the system so will run immediately following the ISR. */ + prvReadRegister( &ucISR, tcpINTERRUPT_STATUS_REG, tcpSTATUS_READ_LEN ); + + /* Once we have read what caused the ISR we can clear the interrupt + in the WIZnet. */ + i2cMessage( ucDataClearInterrupt, sizeof( ucDataClearInterrupt ), tcpDEVICE_ADDRESS, tcpINTERRUPT_REG, i2cWRITE, NULL, portMAX_DELAY ); + + /* Now we can clear the processor interrupt and re-enable ready for + the next. */ + SCB_EXTINT = tcpCLEAR_EINT0; + VICIntEnable |= tcpEINT0_VIC_CHANNEL_BIT; + + /* Process the interrupt ... */ + + if( ucISR & tcpISR_ESTABLISHED ) + { + /* A connection has been established - respond by sending + a receive command. */ + i2cMessage( ucDataReceiveCmd, sizeof( ucDataReceiveCmd ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY ); + } + + if( ucISR & tcpISR_RX_COMPLETE ) + { + /* We message has been received. This will be an HTTP get + command. We only have one page to send so just send it without + regard to what the actual requested page was. */ + prvSendSamplePage(); + } + + if( ucISR & tcpISR_TX_COMPLETE ) + { + /* We have a TX complete interrupt - which oddly does not + indicate that the message being sent is complete so we cannot + yet close the socket. Instead we read the position of the Tx + pointer within the WIZnet device so we know how much data it + has to send. Later we will read the ack pointer and compare + this to the Tx pointer to ascertain whether the transmission + has completed. */ + + /* First read the shadow register. */ + prvReadRegister( &ucShadow, tcpTX_WRITE_SHADOW_REG, tcpSHADOW_READ_LEN ); + + /* Now a short delay is required. */ + vTaskDelay( tcpSHORT_DELAY ); + + /* Then we can read the real register. */ + prvReadRegister( ( unsigned portCHAR * ) &ulWritePointer, tcpTX_WRITE_POINTER_REG, sizeof( ulWritePointer ) ); + + /* We cannot do anything more here but need to remember that + this interrupt has occurred. */ + lDataSent = pdTRUE; + } + + if( ucISR & tcpISR_CLOSED ) + { + /* The socket has been closed so we can leave this function. */ + lTransactionCompleted = pdFALSE; + } + } + else + { + /* We have not received an interrupt from the WIZnet device for a + while. Read the socket status and check that everything is as + expected. */ + prvReadRegister( &ucState, tcpSOCKET_STATE_REG, tcpSTATUS_READ_LEN ); + + if( ( ucState == tcpSTATUS_ESTABLISHED ) && ( lDataSent > 0 ) ) + { + /* The socket is established and we have already received a Tx + end interrupt. We must therefore be waiting for the Tx buffer + inside the WIZnet device to be empty before we can close the + socket. + + Read the Ack pointer register to see if it has caught up with + the Tx pointer register. First we have to read the shadow + register. */ + prvReadRegister( &ucShadow, tcpTX_ACK_SHADOW_REG, tcpSHADOW_READ_LEN ); + vTaskDelay( tcpSHORT_DELAY ); + prvReadRegister( ( unsigned portCHAR * ) &ulAckPointer, tcpTX_ACK_POINTER_REG, sizeof( ulWritePointer ) ); + + if( ulAckPointer == ulWritePointer ) + { + /* The Ack and write pointer are now equal and we can + safely close the socket. */ + i2cMessage( ucDataDisconnect, sizeof( ucDataDisconnect ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY ); + } + else + { + /* Keep a count of how many times we encounter the Tx + buffer still containing data. */ + lDataSent++; + if( lDataSent > tcpMAX_ATTEMPTS_TO_CHECK_BUFFER ) + { + /* Assume we cannot complete sending the data and + therefore cannot safely close the socket. Start over. */ + vTCPHardReset(); + lTransactionCompleted = pdFALSE; + } + } + } + else if( ucState != tcpSTATUS_LISTEN ) + { + /* If we have not yet received a Tx end interrupt we would only + ever expect to find the socket still listening for any + sustained period. */ + if( ucState == ucLastState ) + { + lSameStateCount++; + if( lSameStateCount > tcpMAX_NON_LISTEN_STAUS_READS ) + { + /* We are persistently in an unexpected state. Assume + we cannot safely close the socket and start over. */ + vTCPHardReset(); + lTransactionCompleted = pdFALSE; + } + } + } + else + { + /* We are in the listen state so are happy that everything + is as expected. */ + lSameStateCount = 0; + } + + /* Remember what state we are in this time around so we can check + for a persistence on an unexpected state. */ + ucLastState = ucState; + } + } + + /* We are going to reinitialise the WIZnet device so do not want our + interrupts from the WIZnet to be processed. */ + VICIntEnClear |= tcpEINT0_VIC_CHANNEL_BIT; + return lTransactionCompleted; +} +/*-----------------------------------------------------------*/ + +static void prvWriteString( const portCHAR * const pucTxBuffer, portLONG lTxLen, unsigned portLONG *pulTxAddress ) +{ +unsigned portLONG ulSendAddress; + + /* Send a string to the Tx buffer internal to the WIZnet device. */ + + /* Calculate the address to which we are going to write in the buffer. */ + ulSendAddress = ( *pulTxAddress & tcpSINGLE_SOCKET_ADDR_MASK ) + tcpSINGLE_SOCKET_ADDR_OFFSET; + + /* Send the buffer to the calculated address. Use the semaphore so we + can wait until the entire message has been transferred. */ + i2cMessage( ( unsigned portCHAR * ) pucTxBuffer, lTxLen, tcpDEVICE_ADDRESS, ( unsigned portSHORT ) ulSendAddress, i2cWRITE, xMessageComplete, portMAX_DELAY ); + + /* Wait until the semaphore indicates that the message has been transferred. */ + if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) ) + { + return; + } + + /* Return the new address of the end of the buffer (within the WIZnet + device). */ + *pulTxAddress += ( unsigned portLONG ) lTxLen; +} +/*-----------------------------------------------------------*/ + +static void prvFlushBuffer( unsigned portLONG ulTxAddress ) +{ +unsigned portCHAR ucTxBuffer[ tcpMAX_REGISTER_LEN ]; + + /* We have written some data to the Tx buffer internal to the WIZnet + device. Now we update the Tx pointer inside the WIZnet then send a + Send command - which causes the data up to the new Tx pointer to be + transmitted. */ + + /* Make sure endieness is correct for transmission. */ + ulTxAddress = htonl( ulTxAddress ); + + /* Place the new Tx pointer in the string to be transmitted. */ + ucTxBuffer[ 0 ] = ( unsigned portCHAR ) ( ulTxAddress & 0xff ); + ulTxAddress >>= 8; + ucTxBuffer[ 1 ] = ( unsigned portCHAR ) ( ulTxAddress & 0xff ); + ulTxAddress >>= 8; + ucTxBuffer[ 2 ] = ( unsigned portCHAR ) ( ulTxAddress & 0xff ); + ulTxAddress >>= 8; + ucTxBuffer[ 3 ] = ( unsigned portCHAR ) ( ulTxAddress & 0xff ); + ulTxAddress >>= 8; + + /* And send it to the WIZnet device. */ + i2cMessage( ucTxBuffer, sizeof( ulTxAddress ), tcpDEVICE_ADDRESS, tcpTX_WRITE_POINTER_REG, i2cWRITE, xMessageComplete, portMAX_DELAY ); + + if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) ) + { + return; + } + + vTaskDelay( tcpSHORT_DELAY ); + + /* Transmit! */ + i2cMessage( ucDataSend, sizeof( ucDataSend ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, xMessageComplete, portMAX_DELAY ); + + if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) ) + { + return; + } +} +/*-----------------------------------------------------------*/ + +static void prvSendSamplePage( void ) +{ +extern portLONG lErrorInTask; +unsigned portLONG ulTxAddress; +unsigned portCHAR ucShadow; +portLONG lIndex; +static unsigned portLONG ulRefreshCount = 0x00; +static portCHAR cPageBuffer[ tcpBUFFER_LEN ]; + + + /* This function just generates a sample page of HTML which gets + sent each time a client attaches to the socket. The page is created + from two fixed strings (cSamplePageFirstPart and cSamplePageSecondPart) + with a bit of dynamically generated data in the middle. */ + + /* We need to know the address to which the html string should be sent + in the WIZnet Tx buffer. First read the shadow register. */ + prvReadRegister( &ucShadow, tcpTX_WRITE_SHADOW_REG, tcpSHADOW_READ_LEN ); + + /* Now a short delay is required. */ + vTaskDelay( tcpSHORT_DELAY ); + + /* Now we can read the real pointer value. */ + prvReadRegister( ( unsigned portCHAR * ) &ulTxAddress, tcpTX_WRITE_POINTER_REG, sizeof( ulTxAddress ) ); + + /* Make sure endieness is correct. */ + ulTxAddress = htonl( ulTxAddress ); + + /* Send the start of the page. */ + prvWriteString( cSamplePageFirstPart, strlen( cSamplePageFirstPart ), &ulTxAddress ); + + /* Generate a bit of dynamic data and place it in the buffer ready to be + transmitted. */ + strcpy( cPageBuffer, "
Number of ticks since boot = 0x" ); + lIndex = strlen( cPageBuffer ); + ultoa( xTaskGetTickCount(), &( cPageBuffer[ lIndex ] ), 0 ); + strcat( cPageBuffer, "
Number of tasks executing = "); + lIndex = strlen( cPageBuffer ); + ultoa( ( unsigned portLONG ) uxTaskGetNumberOfTasks(), &( cPageBuffer[ lIndex ] ), 0 ); + strcat( cPageBuffer, "
IO port 0 state (used by flash tasks) = 0x" ); + lIndex = strlen( cPageBuffer ); + ultoa( ( unsigned portLONG ) GPIO0_IOPIN, &( cPageBuffer[ lIndex ] ), 0 ); + strcat( cPageBuffer, "
Refresh = 0x" ); + lIndex = strlen( cPageBuffer ); + ultoa( ( unsigned portLONG ) ulRefreshCount, &( cPageBuffer[ lIndex ] ), 0 ); + + if( lErrorInTask ) + { + strcat( cPageBuffer, "

An error has occurred in at least one task." ); + } + else + { + strcat( cPageBuffer, "

All tasks executing without error." ); + } + + ulRefreshCount++; + + /* Send the dynamically generated string. */ + prvWriteString( cPageBuffer, strlen( cPageBuffer ), &ulTxAddress ); + + /* Finish the page. */ + prvWriteString( cSamplePageSecondPart, strlen( cSamplePageSecondPart ), &ulTxAddress ); + + /* Tell the WIZnet to send the data we have just written to its Tx buffer. */ + prvFlushBuffer( ulTxAddress ); +} + diff --git a/20080212/Demo/WizNET_DEMO_GCC_ARM7/TCP.h b/20080212/Demo/WizNET_DEMO_GCC_ARM7/TCP.h new file mode 100644 index 000000000..e8df16715 --- /dev/null +++ b/20080212/Demo/WizNET_DEMO_GCC_ARM7/TCP.h @@ -0,0 +1,55 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef TCP_H +#define TCP_H + +#define htonl(A) ((((A) & 0xff000000) >> 24) | (((A) & 0x00ff0000) >> 8) | (((A) & 0x0000ff00) << 8) | (((A) & 0x000000ff) << 24)) + +void vTCPHardReset( void ); +portLONG lTCPSoftReset( void ); +portLONG lTCPCreateSocket( void ); +portLONG lTCPListen( void ); +portLONG lProcessConnection( void ); +void vTCPListen( void ); + +#endif diff --git a/20080212/Demo/WizNET_DEMO_GCC_ARM7/TCPISR.c b/20080212/Demo/WizNET_DEMO_GCC_ARM7/TCPISR.c new file mode 100644 index 000000000..d344b677c --- /dev/null +++ b/20080212/Demo/WizNET_DEMO_GCC_ARM7/TCPISR.c @@ -0,0 +1,105 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* Constants required for interrupt management. */ +#define tcpCLEAR_VIC_INTERRUPT ( 0 ) +#define tcpEINT0_VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x4000 ) + +/* EINT0 interrupt handler. This processes interrupts from the WIZnet device. */ +void vEINT0_ISR_Wrapper( void ) __attribute__((naked)); + +/* The handler that goes with the EINT0 wrapper. */ +void vEINT0_ISR_Handler( void ); + +/* Variable is required for its address, but does not otherwise get used. */ +static portLONG lDummyVariable; + +/* + * When the WIZnet device asserts an interrupt we send an (empty) message to + * the TCP task. This wakes the task so the interrupt can be processed. The + * source of the interrupt has to be ascertained by the TCP task as this + * requires an I2C transaction which cannot be performed from this ISR. + * Note this code predates the introduction of semaphores, a semaphore should + * be used in place of the empty queue message. + */ +void vEINT0_ISR_Handler( void ) +{ +extern xQueueHandle xTCPISRQueue; +portBASE_TYPE xTaskWoken = pdFALSE; + + /* Just wake the TCP task so it knows an ISR has occurred. */ + xTaskWoken = xQueueSendFromISR( xTCPISRQueue, ( void * ) &lDummyVariable, xTaskWoken ); + + /* We cannot carry on processing interrupts until the TCP task has + processed this one - so for now interrupts are disabled. The TCP task will + re-enable it. */ + VICIntEnClear |= tcpEINT0_VIC_CHANNEL_BIT; + + /* Clear the interrupt bit. */ + VICVectAddr = tcpCLEAR_VIC_INTERRUPT; + + if( xTaskWoken ) + { + portYIELD_FROM_ISR(); + } +} +/*-----------------------------------------------------------*/ + +void vEINT0_ISR_Wrapper( void ) +{ + /* Save the context of the interrupted task. */ + portSAVE_CONTEXT(); + + /* The handler must be a separate function from the wrapper to + ensure the correct stack frame is set up. */ + vEINT0_ISR_Handler(); + + /* Restore the context of whichever task is going to run next. */ + portRESTORE_CONTEXT(); +} + + diff --git a/20080212/Demo/WizNET_DEMO_GCC_ARM7/boot.s b/20080212/Demo/WizNET_DEMO_GCC_ARM7/boot.s new file mode 100644 index 000000000..33e5226eb --- /dev/null +++ b/20080212/Demo/WizNET_DEMO_GCC_ARM7/boot.s @@ -0,0 +1,157 @@ + /* Sample initialization file */ + + .extern main + .extern exit + + .text + .code 32 + + + .align 0 + + .extern __bss_beg__ + .extern __bss_end__ + .extern __stack_end__ + .extern __data_beg__ + .extern __data_end__ + .extern __data+beg_src__ + + .global start + .global endless_loop + + /* Stack Sizes */ + .set UND_STACK_SIZE, 0x00000004 + .set ABT_STACK_SIZE, 0x00000004 + .set FIQ_STACK_SIZE, 0x00000004 + .set IRQ_STACK_SIZE, 0X00000400 + .set SVC_STACK_SIZE, 0x00000400 + + /* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */ + .set MODE_USR, 0x10 /* User Mode */ + .set MODE_FIQ, 0x11 /* FIQ Mode */ + .set MODE_IRQ, 0x12 /* IRQ Mode */ + .set MODE_SVC, 0x13 /* Supervisor Mode */ + .set MODE_ABT, 0x17 /* Abort Mode */ + .set MODE_UND, 0x1B /* Undefined Mode */ + .set MODE_SYS, 0x1F /* System Mode */ + + .equ I_BIT, 0x80 /* when I bit is set, IRQ is disabled */ + .equ F_BIT, 0x40 /* when F bit is set, FIQ is disabled */ + + +start: +_start: +_mainCRTStartup: + + /* Setup a stack for each mode - note that this only sets up a usable stack + for system/user, SWI and IRQ modes. Also each mode is setup with + interrupts initially disabled. */ + ldr r0, .LC6 + msr CPSR_c, #MODE_UND|I_BIT|F_BIT /* Undefined Instruction Mode + mov sp, r0 + sub r0, r0, #UND_STACK_SIZE + msr CPSR_c, #MODE_ABT|I_BIT|F_BIT /* Abort Mode */ + mov sp, r0 + sub r0, r0, #ABT_STACK_SIZE + msr CPSR_c, #MODE_FIQ|I_BIT|F_BIT /* FIQ Mode */ + mov sp, r0 + sub r0, r0, #FIQ_STACK_SIZE + msr CPSR_c, #MODE_IRQ|I_BIT|F_BIT /* IRQ Mode */ + mov sp, r0 + sub r0, r0, #IRQ_STACK_SIZE + msr CPSR_c, #MODE_SVC|I_BIT|F_BIT /* Supervisor Mode */ + mov sp, r0 + sub r0, r0, #SVC_STACK_SIZE + msr CPSR_c, #MODE_SYS|I_BIT|F_BIT /* System Mode */ + mov sp, r0 + + /* We want to start in supervisor mode. Operation will switch to system + mode when the first task starts. */ + msr CPSR_c, #MODE_SVC|I_BIT|F_BIT + + /* Clear BSS. */ + + mov a2, #0 /* Fill value */ + mov fp, a2 /* Null frame pointer */ + mov r7, a2 /* Null frame pointer for Thumb */ + + ldr r1, .LC1 /* Start of memory block */ + ldr r3, .LC2 /* End of memory block */ + subs r3, r3, r1 /* Length of block */ + beq .end_clear_loop + mov r2, #0 + +.clear_loop: + strb r2, [r1], #1 + subs r3, r3, #1 + bgt .clear_loop + +.end_clear_loop: + + /* Initialise data. */ + + ldr r1, .LC3 /* Start of memory block */ + ldr r2, .LC4 /* End of memory block */ + ldr r3, .LC5 + subs r3, r3, r1 /* Length of block */ + beq .end_set_loop + +.set_loop: + ldrb r4, [r2], #1 + strb r4, [r1], #1 + subs r3, r3, #1 + bgt .set_loop + +.end_set_loop: + + mov r0, #0 /* no arguments */ + mov r1, #0 /* no argv either */ + + bl main + +endless_loop: + b endless_loop + + + .align 0 + + .LC1: + .word __bss_beg__ + .LC2: + .word __bss_end__ + .LC3: + .word __data_beg__ + .LC4: + .word __data_beg_src__ + .LC5: + .word __data_end__ + .LC6: + .word __stack_end__ + + + /* Setup vector table. Note that undf, pabt, dabt, fiq just execute + a null loop. */ + +.section .startup,"ax" + .code 32 + .align 0 + + b _start /* reset - _start */ + ldr pc, _undf /* undefined - _undf */ + ldr pc, _swi /* SWI - _swi */ + ldr pc, _pabt /* program abort - _pabt */ + ldr pc, _dabt /* data abort - _dabt */ + nop /* reserved */ + ldr pc, [pc,#-0xFF0] /* IRQ - read the VIC */ + ldr pc, _fiq /* FIQ - _fiq */ + +_undf: .word __undf /* undefined */ +_swi: .word vPortYieldProcessor /* SWI */ +_pabt: .word __pabt /* program abort */ +_dabt: .word __dabt /* data abort */ +_fiq: .word __fiq /* FIQ */ + +__undf: b . /* undefined */ +__pabt: b . /* program abort */ +__dabt: b . /* data abort */ +__fiq: b . /* FIQ */ diff --git a/20080212/Demo/WizNET_DEMO_GCC_ARM7/html_pages.h b/20080212/Demo/WizNET_DEMO_GCC_ARM7/html_pages.h new file mode 100644 index 000000000..07bd3e0cb --- /dev/null +++ b/20080212/Demo/WizNET_DEMO_GCC_ARM7/html_pages.h @@ -0,0 +1,76 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef HTML_PAGES_H +#define HTML_PAGES_H + +/* Simply defines some strings that get sent as HTML pages. */ + +const portCHAR * const cSamplePageFirstPart = +"HTTP/1.0 200 OK\r\n" +"Content-type: text/html\r\n" +"\r\n" +"\r\n" +"\r\n" +"\r\n" +"FreeRTOS - Live embedded WEB server demo\r\n" +"\r\n" +"\r\n" +"\r\n" +"FreeRTOS Homepage

" +"

Embedded WEB Server
On the FreeRTOS real time kernel

\r\n" +"

\r\n" +"This demo is now using FreeRTOS.org V4.x.x!

" +"This page is being served by the FreeRTOS embedded WEB server running on an ARM7 microcontroller.\r\n

";
+
+const portCHAR * const cSamplePageSecondPart =
+"
" +"If all is well you should see that 18 tasks are executing - 15 standard demo tasks, the embedded WEB server" +" task, the error check task and the idle task.

" +"\r\n" +"\r\n" +"\r\n"; + + + +#endif + diff --git a/20080212/Demo/WizNET_DEMO_GCC_ARM7/i2c.c b/20080212/Demo/WizNET_DEMO_GCC_ARM7/i2c.c new file mode 100644 index 000000000..199a422aa --- /dev/null +++ b/20080212/Demo/WizNET_DEMO_GCC_ARM7/i2c.c @@ -0,0 +1,219 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +/* Standard includes. */ +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "queue.h" +#include "semphr.h" + +/* Application includes. */ +#include "i2c.h" + +/*-----------------------------------------------------------*/ + +/* Constants to setup the microcontroller IO. */ +#define mainSDA_ENABLE ( ( unsigned portLONG ) 0x0040 ) +#define mainSCL_ENABLE ( ( unsigned portLONG ) 0x0010 ) + +/* Bit definitions within the I2CONCLR register. */ +#define i2cSTA_BIT ( ( unsigned portCHAR ) 0x20 ) +#define i2cSI_BIT ( ( unsigned portCHAR ) 0x08 ) +#define i2cSTO_BIT ( ( unsigned portCHAR ) 0x10 ) + +/* Constants required to setup the VIC. */ +#define i2cI2C_VIC_CHANNEL ( ( unsigned portLONG ) 0x0009 ) +#define i2cI2C_VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x0200 ) +#define i2cI2C_VIC_ENABLE ( ( unsigned portLONG ) 0x0020 ) + +/* Misc constants. */ +#define i2cNO_BLOCK ( ( portTickType ) 0 ) +#define i2cQUEUE_LENGTH ( ( unsigned portCHAR ) 5 ) +#define i2cEXTRA_MESSAGES ( ( unsigned portCHAR ) 2 ) +#define i2cREAD_TX_LEN ( ( unsigned portLONG ) 2 ) +#define i2cACTIVE_MASTER_MODE ( ( unsigned portCHAR ) 0x40 ) +#define i2cTIMERL ( 200 ) +#define i2cTIMERH ( 200 ) + +/* Array of message definitions. See the header file for more information +on the structure members. There are two more places in the queue than as +defined by i2cQUEUE_LENGTH. This is to ensure that there is always a free +message available - one can be in the process of being transmitted and one +can be left free. */ +static xI2CMessage xTxMessages[ i2cQUEUE_LENGTH + i2cEXTRA_MESSAGES ]; + +/* Function in the ARM part of the code used to create the queues. */ +extern void vI2CISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxTxMessages, unsigned portLONG **ppulBusFree ); + +/* Index to the next free message in the xTxMessages array. */ +unsigned portLONG ulNextFreeMessage = ( unsigned portLONG ) 0; + +/* Queue of messages that are waiting transmission. */ +static xQueueHandle xMessagesForTx; + +/* Flag to indicate the state of the I2C ISR state machine. */ +static unsigned portLONG *pulBusFree; + +/*-----------------------------------------------------------*/ +void i2cMessage( const unsigned portCHAR * const pucMessage, portLONG lMessageLength, unsigned portCHAR ucSlaveAddress, unsigned portSHORT usBufferAddress, unsigned portLONG ulDirection, xSemaphoreHandle xMessageCompleteSemaphore, portTickType xBlockTime ) +{ +extern volatile xI2CMessage *pxCurrentMessage; +xI2CMessage *pxNextFreeMessage; +signed portBASE_TYPE xReturn; + + portENTER_CRITICAL(); + { + /* This message is guaranteed to be free as there are two more messages + than spaces in the queue allowing for one message to be in process of + being transmitted and one to be left free. */ + pxNextFreeMessage = &( xTxMessages[ ulNextFreeMessage ] ); + + /* Fill the message with the data to be sent. */ + + /* Pointer to the actual data. Only a pointer is stored (i.e. the + actual data is not copied, so the data being pointed to must still + be valid when the message eventually gets sent (it may be queued for + a while. */ + pxNextFreeMessage->pucBuffer = ( unsigned portCHAR * ) pucMessage; + + /* This is the address of the I2C device we are going to transmit this + message to. */ + pxNextFreeMessage->ucSlaveAddress = ucSlaveAddress | ( unsigned portCHAR ) ulDirection; + + /* A semaphore can be used to allow the I2C ISR to indicate that the + message has been sent. This can be NULL if you don't want to wait for + the message transmission to complete. */ + pxNextFreeMessage->xMessageCompleteSemaphore = xMessageCompleteSemaphore; + + /* How many bytes are to be sent? */ + pxNextFreeMessage->lMessageLength = lMessageLength; + + /* The address within the WIZnet device to which the data will be + written. This could be the address of a register, or alternatively + a location within the WIZnet Tx buffer. */ + pxNextFreeMessage->ucBufferAddressLowByte = ( unsigned portCHAR ) ( usBufferAddress & 0xff ); + + /* Second byte of the address. */ + usBufferAddress >>= 8; + pxNextFreeMessage->ucBufferAddressHighByte = ( unsigned portCHAR ) ( usBufferAddress & 0xff ); + + /* Increment to the next message in the array - with a wrap around check. */ + ulNextFreeMessage++; + if( ulNextFreeMessage >= ( i2cQUEUE_LENGTH + i2cEXTRA_MESSAGES ) ) + { + ulNextFreeMessage = ( unsigned portLONG ) 0; + } + + /* Is the I2C interrupt in the middle of transmitting a message? */ + if( *pulBusFree == ( unsigned portLONG ) pdTRUE ) + { + /* No message is currently being sent or queued to be sent. We + can start the ISR sending this message immediately. */ + pxCurrentMessage = pxNextFreeMessage; + + I2C_I2CONCLR = i2cSI_BIT; + I2C_I2CONSET = i2cSTA_BIT; + + *pulBusFree = ( unsigned portLONG ) pdFALSE; + } + else + { + /* The I2C interrupt routine is mid sending a message. Queue + this message ready to be sent. */ + xReturn = xQueueSend( xMessagesForTx, &pxNextFreeMessage, xBlockTime ); + + /* We may have blocked while trying to queue the message. If this + was the case then the interrupt would have been enabled and we may + now find that the I2C interrupt routine is no longer sending a + message. */ + if( ( *pulBusFree == ( unsigned portLONG ) pdTRUE ) && ( xReturn == pdPASS ) ) + { + /* Get the next message in the queue (this should be the + message we just posted) and start off the transmission + again. */ + xQueueReceive( xMessagesForTx, &pxNextFreeMessage, i2cNO_BLOCK ); + pxCurrentMessage = pxNextFreeMessage; + + I2C_I2CONCLR = i2cSI_BIT; + I2C_I2CONSET = i2cSTA_BIT; + + *pulBusFree = ( unsigned portLONG ) pdFALSE; + } + } + } + portEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +void i2cInit( void ) +{ +extern void ( vI2C_ISR_Wrapper )( void ); + + /* Create the queue used to send messages to the ISR. */ + vI2CISRCreateQueues( i2cQUEUE_LENGTH, &xMessagesForTx, &pulBusFree ); + + /* Configure the I2C hardware. */ + + I2C_I2CONCLR = 0xff; + + PCB_PINSEL0 |= mainSDA_ENABLE; + PCB_PINSEL0 |= mainSCL_ENABLE; + + I2C_I2SCLL = i2cTIMERL; + I2C_I2SCLH = i2cTIMERH; + I2C_I2CONSET = i2cACTIVE_MASTER_MODE; + + portENTER_CRITICAL(); + { + /* Setup the VIC for the i2c interrupt. */ + VICIntSelect &= ~( i2cI2C_VIC_CHANNEL_BIT ); + VICIntEnable |= i2cI2C_VIC_CHANNEL_BIT; + VICVectAddr2 = ( portLONG ) vI2C_ISR_Wrapper; + + VICVectCntl2 = i2cI2C_VIC_CHANNEL | i2cI2C_VIC_ENABLE; + } + portEXIT_CRITICAL(); +} + diff --git a/20080212/Demo/WizNET_DEMO_GCC_ARM7/i2c.h b/20080212/Demo/WizNET_DEMO_GCC_ARM7/i2c.h new file mode 100644 index 000000000..d484348fa --- /dev/null +++ b/20080212/Demo/WizNET_DEMO_GCC_ARM7/i2c.h @@ -0,0 +1,96 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef I2C_H +#define I2C_H + +/* Structure used to capture the I2C message details. The structure is then + * queued for processing by the I2C ISR. + */ +typedef struct AN_I2C_MESSAGE +{ + portLONG lMessageLength; /*< How many bytes of data to send or received - excluding the buffer address. */ + unsigned portCHAR ucSlaveAddress; /*< The slave address of the WIZnet on the I2C bus. */ + unsigned portCHAR ucBufferAddressLowByte; /*< The address within the WIZnet device to which data should be read from / written to. */ + unsigned portCHAR ucBufferAddressHighByte; /*< As above, high byte. */ + xSemaphoreHandle xMessageCompleteSemaphore; /*< Contains a reference to a semaphore if the application tasks wants notifying when the message has been transacted. */ + unsigned portCHAR *pucBuffer; /*< Pointer to the buffer from where data will be read for transmission, or into which received data will be placed. */ +} xI2CMessage; + +/* Constants to use as the ulDirection parameter of i2cMessage(). */ +#define i2cWRITE ( ( unsigned portLONG ) 0 ) +#define i2cREAD ( ( unsigned portLONG ) 1 ) + +/** + * Must be called once before any calls to i2cMessage. + */ +void i2cInit( void ); + +/** + * Send or receive a message over the I2C bus. + * + * @param pucMessage The data to be transmitted or the buffer into which + * received data will be placed. + * + * @param lMessageLength The number of bytes to either transmit or receive. + * + * @param ucSlaveAddress The slave address of the WIZNet device on the I2C bus. + * + * @param usBufferAddress The address within the WIZNet device to which data is + * either written to or read from. The WIZnet has it's + * own Rx and Tx buffers. + * + * @param ulDirection Must be either i2cWRITE or i2cREAD as #defined above. + * + * @param xMessageCompleteSemaphore + * Can be used to pass a semaphore reference if the + * calling task want notification of when the message has + * completed. Otherwise NULL can be passed. + * + * @param xBlockTime The time to wait for a space in the message queue to + * become available should one not be available + * immediately. + */ +void i2cMessage( const unsigned portCHAR * const pucMessage, portLONG lMessageLength, unsigned portCHAR ucSlaveAddress, unsigned portSHORT usBufferAddress, unsigned portLONG ulDirection, xSemaphoreHandle xMessageCompleteSemaphore, portTickType xBlockTime ); + +#endif + diff --git a/20080212/Demo/WizNET_DEMO_GCC_ARM7/i2cISR.c b/20080212/Demo/WizNET_DEMO_GCC_ARM7/i2cISR.c new file mode 100644 index 000000000..ff84d0e18 --- /dev/null +++ b/20080212/Demo/WizNET_DEMO_GCC_ARM7/i2cISR.c @@ -0,0 +1,373 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +/* Standard includes. */ +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "semphr.h" + +/* Application includes. */ +#include "i2c.h" + +/*-----------------------------------------------------------*/ + +/* Bit definitions within the I2CONCLR register. */ +#define i2cSTA_BIT ( ( unsigned portCHAR ) 0x20 ) +#define i2cSI_BIT ( ( unsigned portCHAR ) 0x08 ) +#define i2cSTO_BIT ( ( unsigned portCHAR ) 0x10 ) +#define i2cAA_BIT ( ( unsigned portCHAR ) 0x04 ) + +/* Status codes for the I2STAT register. */ +#define i2cSTATUS_START_TXED ( 0x08 ) +#define i2cSTATUS_REP_START_TXED ( 0x10 ) +#define i2cSTATUS_TX_ADDR_ACKED ( 0x18 ) +#define i2cSTATUS_DATA_TXED ( 0x28 ) +#define i2cSTATUS_RX_ADDR_ACKED ( 0x40 ) +#define i2cSTATUS_DATA_RXED ( 0x50 ) +#define i2cSTATUS_LAST_BYTE_RXED ( 0x58 ) + +/* Constants for operation of the VIC. */ +#define i2cCLEAR_VIC_INTERRUPT ( 0 ) + +/* Misc constants. */ +#define i2cJUST_ONE_BYTE_TO_RX ( 1 ) +#define i2cBUFFER_ADDRESS_BYTES ( 2 ) + +/* End the current transmission and free the bus. */ +#define i2cEND_TRANSMISSION( lStatus ) \ +{ \ + I2C_I2CONCLR = i2cAA_BIT; \ + I2C_I2CONSET = i2cSTO_BIT; \ + eCurrentState = eSentStart; \ + lTransactionCompleted = lStatus; \ +} +/*-----------------------------------------------------------*/ + +/* Valid i2c communication states. */ +typedef enum +{ + eSentStart, /*<< Last action was the transmission of a start bit. */ + eSentAddressForWrite, /*<< Last action was the transmission of the slave address we are to write to. */ + eSentAddressForRead, /*<< Last action was the transmission of the slave address we are to read from. */ + eSentData, /*<< Last action was the transmission of a data byte. */ + eReceiveData /*<< We expected data to be received. */ +} I2C_STATE; +/*-----------------------------------------------------------*/ + +/* Points to the message currently being sent. */ +volatile xI2CMessage *pxCurrentMessage = NULL; + +/* The queue of messages waiting to be transmitted. */ +static xQueueHandle xMessagesForTx; + +/* Flag used to indicate whether or not the ISR is amid sending a message. */ +unsigned portLONG ulBusFree = ( unsigned portLONG ) pdTRUE; + +/* Setting this to true will cause the TCP task to think a message is +complete and thus restart. It can therefore be used under error states +to force a restart. */ +volatile portLONG lTransactionCompleted = pdTRUE; + +/*-----------------------------------------------------------*/ + +void vI2CISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxTxMessages, unsigned portLONG **ppulBusFree ) +{ + /* Create the queues used to hold Rx and Tx characters. */ + xMessagesForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( xI2CMessage * ) ); + + /* Pass back a reference to the queue and bus free flag so the I2C API file + can post messages. */ + *pxTxMessages = xMessagesForTx; + *ppulBusFree = &ulBusFree; +} +/*-----------------------------------------------------------*/ + +/* The ISR entry point. */ +void vI2C_ISR_Wrapper( void ) __attribute__ (( naked )); + +/* The ISR function to perform the actual work. This must be a separate +function from the wrapper to ensure the correct stack frame is set up. */ +void vI2C_ISR_Handler( void ); + +/*-----------------------------------------------------------*/ + +void vI2C_ISR_Wrapper( void ) +{ + /* Save the context of the interrupted task. */ + portSAVE_CONTEXT(); + + /* Call the handler to perform the actual work. This must be a + separate function to ensure the correct stack frame is set up. */ + vI2C_ISR_Handler(); + + /* Restore the context of whichever task is going to run next. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +void vI2C_ISR_Handler( void ) +{ +/* Holds the current transmission state. */ +static I2C_STATE eCurrentState = eSentStart; +static portLONG lMessageIndex = -i2cBUFFER_ADDRESS_BYTES; /* There are two address bytes to send prior to the data. */ +portBASE_TYPE xTaskWokenByTx = pdFALSE; +portLONG lBytesLeft; + + /* The action taken for this interrupt depends on our current state. */ + switch( eCurrentState ) + { + case eSentStart : + + /* We sent a start bit, if it was successful we can + go on to send the slave address. */ + if( ( I2C_I2STAT == i2cSTATUS_START_TXED ) || ( I2C_I2STAT == i2cSTATUS_REP_START_TXED ) ) + { + /* Send the slave address. */ + I2C_I2DAT = pxCurrentMessage->ucSlaveAddress; + + if( pxCurrentMessage->ucSlaveAddress & i2cREAD ) + { + /* We are then going to read bytes back from the + slave. */ + eCurrentState = eSentAddressForRead; + + /* Initialise the buffer index so the first byte goes + into the first buffer position. */ + lMessageIndex = 0; + } + else + { + /* We are then going to write some data to the slave. */ + eCurrentState = eSentAddressForWrite; + + /* When writing bytes we first have to send the two + byte buffer address so lMessageIndex is set negative, + when it reaches 0 it is time to send the actual data. */ + lMessageIndex = -i2cBUFFER_ADDRESS_BYTES; + } + } + else + { + /* Could not send the start bit so give up. */ + i2cEND_TRANSMISSION( pdFAIL ); + } + + I2C_I2CONCLR = i2cSTA_BIT; + + break; + + case eSentAddressForWrite : + + /* We sent the address of the slave we are going to write to. + If this was acknowledged we can go on to send the data. */ + if( I2C_I2STAT == i2cSTATUS_TX_ADDR_ACKED ) + { + /* Start the first byte transmitting which is the + first byte of the buffer address to which the data will + be sent. */ + I2C_I2DAT = pxCurrentMessage->ucBufferAddressHighByte; + eCurrentState = eSentData; + } + else + { + /* Address was not acknowledged so give up. */ + i2cEND_TRANSMISSION( pdFAIL ); + } + break; + + case eSentAddressForRead : + + /* We sent the address of the slave we are going to read from. + If this was acknowledged we can go on to read the data. */ + if( I2C_I2STAT == i2cSTATUS_RX_ADDR_ACKED ) + { + eCurrentState = eReceiveData; + if( pxCurrentMessage->lMessageLength > i2cJUST_ONE_BYTE_TO_RX ) + { + /* Don't ack the last byte of the message. */ + I2C_I2CONSET = i2cAA_BIT; + } + } + else + { + /* Something unexpected happened - give up. */ + i2cEND_TRANSMISSION( pdFAIL ); + } + break; + + case eReceiveData : + + /* We have just received a byte from the slave. */ + if( ( I2C_I2STAT == i2cSTATUS_DATA_RXED ) || ( I2C_I2STAT == i2cSTATUS_LAST_BYTE_RXED ) ) + { + /* Buffer the byte just received then increment the index + so it points to the next free space. */ + pxCurrentMessage->pucBuffer[ lMessageIndex ] = I2C_I2DAT; + lMessageIndex++; + + /* How many more bytes are we expecting to receive? */ + lBytesLeft = pxCurrentMessage->lMessageLength - lMessageIndex; + if( lBytesLeft == ( unsigned portLONG ) 0 ) + { + /* This was the last byte in the message. */ + i2cEND_TRANSMISSION( pdPASS ); + + /* If xMessageCompleteSemaphore is not null then there + is a task waiting for this message to complete and we + must 'give' the semaphore so the task is woken.*/ + if( pxCurrentMessage->xMessageCompleteSemaphore ) + { + xTaskWokenByTx = xSemaphoreGiveFromISR( pxCurrentMessage->xMessageCompleteSemaphore, xTaskWokenByTx ); + } + + /* Are there any other messages to transact? */ + if( xQueueReceiveFromISR( xMessagesForTx, &pxCurrentMessage, &xTaskWokenByTx ) == pdTRUE ) + { + /* Start the next message - which was + retrieved from the queue. */ + I2C_I2CONSET = i2cSTA_BIT; + } + else + { + /* No more messages were found to be waiting for + transaction so the bus is free. */ + ulBusFree = ( unsigned portLONG ) pdTRUE; + } + } + else + { + /* There are more bytes to receive but don't ack the + last byte. */ + if( lBytesLeft <= i2cJUST_ONE_BYTE_TO_RX ) + { + I2C_I2CONCLR = i2cAA_BIT; + } + } + } + else + { + /* Something unexpected happened - give up. */ + i2cEND_TRANSMISSION( pdFAIL ); + } + + break; + + case eSentData : + + /* We sent a data byte, if successful send the next byte in + the message. */ + if( I2C_I2STAT == i2cSTATUS_DATA_TXED ) + { + /* Index to the next byte to send. */ + lMessageIndex++; + if( lMessageIndex < 0 ) + { + /* lMessage index is still negative so we have so far + only sent the first byte of the buffer address. Send + the second byte now, then initialise the buffer index + to zero so the next byte sent comes from the actual + data buffer. */ + I2C_I2DAT = pxCurrentMessage->ucBufferAddressLowByte; + } + else if( lMessageIndex < pxCurrentMessage->lMessageLength ) + { + /* Simply send the next byte in the tx buffer. */ + I2C_I2DAT = pxCurrentMessage->pucBuffer[ lMessageIndex ]; + } + else + { + /* No more bytes in this message to be send. Finished + sending message - send a stop bit. */ + i2cEND_TRANSMISSION( pdPASS ); + + /* If xMessageCompleteSemaphore is not null then there + is a task waiting for this message to be sent and the + semaphore must be 'given' to wake the task. */ + if( pxCurrentMessage->xMessageCompleteSemaphore ) + { + xTaskWokenByTx = xSemaphoreGiveFromISR( pxCurrentMessage->xMessageCompleteSemaphore, xTaskWokenByTx ); + } + + /* Are there any other messages to transact? */ + if( xQueueReceiveFromISR( xMessagesForTx, &pxCurrentMessage, &xTaskWokenByTx ) == pdTRUE ) + { + /* Start the next message from the Tx queue. */ + I2C_I2CONSET = i2cSTA_BIT; + } + else + { + /* No more message were queues for transaction so + the bus is free. */ + ulBusFree = ( unsigned portLONG ) pdTRUE; + } + } + } + else + { + /* Something unexpected happened, give up. */ + i2cEND_TRANSMISSION( pdFAIL ); + } + break; + + default : + + /* Should never get here. */ + eCurrentState = eSentStart; + break; + } + + /* Clear the interrupt. */ + I2C_I2CONCLR = i2cSI_BIT; + VICVectAddr = i2cCLEAR_VIC_INTERRUPT; + + if( xTaskWokenByTx ) + { + portYIELD_FROM_ISR(); + } +} +/*-----------------------------------------------------------*/ + diff --git a/20080212/Demo/WizNET_DEMO_GCC_ARM7/lpc2106-rom.ld b/20080212/Demo/WizNET_DEMO_GCC_ARM7/lpc2106-rom.ld new file mode 100644 index 000000000..e7cf25a22 --- /dev/null +++ b/20080212/Demo/WizNET_DEMO_GCC_ARM7/lpc2106-rom.ld @@ -0,0 +1,49 @@ +MEMORY +{ + flash : ORIGIN = 0, LENGTH = 120K + ram : ORIGIN = 0x40000000, LENGTH = 64K +} + +__stack_end__ = 0x40000000 + 64K - 4; + +SECTIONS +{ + . = 0; + startup : { *(.startup)} >flash + + prog : + { + *(.text) + *(.rodata) + *(.rodata*) + *(.glue_7) + *(.glue_7t) + } >flash + + __end_of_text__ = .; + + .data : + { + __data_beg__ = .; + __data_beg_src__ = __end_of_text__; + *(.data) + __data_end__ = .; + } >ram AT>flash + + .bss : + { + __bss_beg__ = .; + *(.bss) + } >ram + + /* Align here to ensure that the .bss section occupies space up to + _end. Align after .bss to ensure correct alignment even if the + .bss section disappears because there are no input sections. */ + . = ALIGN(32 / 8); +} + . = ALIGN(32 / 8); + _end = .; + _bss_end__ = . ; __bss_end__ = . ; __end__ = . ; + PROVIDE (end = .); + + diff --git a/20080212/Demo/WizNET_DEMO_GCC_ARM7/lpc210x.h b/20080212/Demo/WizNET_DEMO_GCC_ARM7/lpc210x.h new file mode 100644 index 000000000..3f1e3042d --- /dev/null +++ b/20080212/Demo/WizNET_DEMO_GCC_ARM7/lpc210x.h @@ -0,0 +1,321 @@ +#ifndef lpc210x_h +#define lpc210x_h +/******************************************************************************* +lpc210x.h - Register defs for Philips LPC210X: LPC2104, LPC2105 and LPC2106 + + +THE SOFTWARE IS DELIVERED "AS IS" WITHOUT WARRANTY OR CONDITION OF ANY KIND, +EITHER EXPRESS, IMPLIED OR STATUTORY. THIS INCLUDES WITHOUT LIMITATION ANY +WARRANTY OR CONDITION WITH RESPECT TO MERCHANTABILITY OR FITNESS FOR ANY +PARTICULAR PURPOSE, OR AGAINST THE INFRINGEMENTS OF INTELLECTUAL PROPERTY RIGHTS +OF OTHERS. + +This file may be freely used for commercial and non-commercial applications, +including being redistributed with any tools. + +If you find a problem with the file, please report it so that it can be fixed. + +Created by Sten Larsson (sten_larsson at yahoo com) + +Edited by Richard Barry. +*******************************************************************************/ + +#define REG8 (volatile unsigned char*) +#define REG16 (volatile unsigned short*) +#define REG32 (volatile unsigned int*) + + +/*############################################################################## +## MISC +##############################################################################*/ + + /* Constants for data to put in IRQ/FIQ Exception Vectors */ +#define VECTDATA_IRQ 0xE51FFFF0 /* LDR PC,[PC,#-0xFF0] */ +#define VECTDATA_FIQ /* __TODO */ + + +/*############################################################################## +## VECTORED INTERRUPT CONTROLLER +##############################################################################*/ + +#define VICIRQStatus (*(REG32 (0xFFFFF000))) +#define VICFIQStatus (*(REG32 (0xFFFFF004))) +#define VICRawIntr (*(REG32 (0xFFFFF008))) +#define VICIntSelect (*(REG32 (0xFFFFF00C))) +#define VICIntEnable (*(REG32 (0xFFFFF010))) +#define VICIntEnClear (*(REG32 (0xFFFFF014))) +#define VICSoftInt (*(REG32 (0xFFFFF018))) +#define VICSoftIntClear (*(REG32 (0xFFFFF01C))) +#define VICProtection (*(REG32 (0xFFFFF020))) +#define VICVectAddr (*(REG32 (0xFFFFF030))) +#define VICDefVectAddr (*(REG32 (0xFFFFF034))) + +#define VICVectAddr0 (*(REG32 (0xFFFFF100))) +#define VICVectAddr1 (*(REG32 (0xFFFFF104))) +#define VICVectAddr2 (*(REG32 (0xFFFFF108))) +#define VICVectAddr3 (*(REG32 (0xFFFFF10C))) +#define VICVectAddr4 (*(REG32 (0xFFFFF110))) +#define VICVectAddr5 (*(REG32 (0xFFFFF114))) +#define VICVectAddr6 (*(REG32 (0xFFFFF118))) +#define VICVectAddr7 (*(REG32 (0xFFFFF11C))) +#define VICVectAddr8 (*(REG32 (0xFFFFF120))) +#define VICVectAddr9 (*(REG32 (0xFFFFF124))) +#define VICVectAddr10 (*(REG32 (0xFFFFF128))) +#define VICVectAddr11 (*(REG32 (0xFFFFF12C))) +#define VICVectAddr12 (*(REG32 (0xFFFFF130))) +#define VICVectAddr13 (*(REG32 (0xFFFFF134))) +#define VICVectAddr14 (*(REG32 (0xFFFFF138))) +#define VICVectAddr15 (*(REG32 (0xFFFFF13C))) + +#define VICVectCntl0 (*(REG32 (0xFFFFF200))) +#define VICVectCntl1 (*(REG32 (0xFFFFF204))) +#define VICVectCntl2 (*(REG32 (0xFFFFF208))) +#define VICVectCntl3 (*(REG32 (0xFFFFF20C))) +#define VICVectCntl4 (*(REG32 (0xFFFFF210))) +#define VICVectCntl5 (*(REG32 (0xFFFFF214))) +#define VICVectCntl6 (*(REG32 (0xFFFFF218))) +#define VICVectCntl7 (*(REG32 (0xFFFFF21C))) +#define VICVectCntl8 (*(REG32 (0xFFFFF220))) +#define VICVectCntl9 (*(REG32 (0xFFFFF224))) +#define VICVectCntl10 (*(REG32 (0xFFFFF228))) +#define VICVectCntl11 (*(REG32 (0xFFFFF22C))) +#define VICVectCntl12 (*(REG32 (0xFFFFF230))) +#define VICVectCntl13 (*(REG32 (0xFFFFF234))) +#define VICVectCntl14 (*(REG32 (0xFFFFF238))) +#define VICVectCntl15 (*(REG32 (0xFFFFF23C))) + +#define VICITCR (*(REG32 (0xFFFFF300))) +#define VICITIP1 (*(REG32 (0xFFFFF304))) +#define VICITIP2 (*(REG32 (0xFFFFF308))) +#define VICITOP1 (*(REG32 (0xFFFFF30C))) +#define VICITOP2 (*(REG32 (0xFFFFF310))) +#define VICPeriphID0 (*(REG32 (0xFFFFFFE0))) +#define VICPeriphID1 (*(REG32 (0xFFFFFFE4))) +#define VICPeriphID2 (*(REG32 (0xFFFFFFE8))) +#define VICPeriphID3 (*(REG32 (0xFFFFFFEC))) + +#define VICIntEnClr VICIntEnClear +#define VICSoftIntClr VICSoftIntClear + + +/*############################################################################## +## PCB - Pin Connect Block +##############################################################################*/ + +#define PCB_PINSEL0 (*(REG32 (0xE002C000))) +#define PCB_PINSEL1 (*(REG32 (0xE002C004))) + + +/*############################################################################## +## GPIO - General Purpose I/O +##############################################################################*/ + +#define GPIO_IOPIN (*(REG32 (0xE0028000))) /* ALTERNATE NAME GPIO = GPIO0 */ +#define GPIO_IOSET (*(REG32 (0xE0028004))) +#define GPIO_IODIR (*(REG32 (0xE0028008))) +#define GPIO_IOCLR (*(REG32 (0xE002800C))) + +#define GPIO0_IOPIN (*(REG32 (0xE0028000))) /* ALTERNATE NAME GPIO = GPIO0 */ +#define GPIO0_IOSET (*(REG32 (0xE0028004))) +#define GPIO0_IODIR (*(REG32 (0xE0028008))) +#define GPIO0_IOCLR (*(REG32 (0xE002800C))) + + +/*############################################################################## +## UART0 / UART1 +##############################################################################*/ + +/* ---- UART 0 --------------------------------------------- */ +#define UART0_RBR (*(REG32 (0xE000C000))) +#define UART0_THR (*(REG32 (0xE000C000))) +#define UART0_IER (*(REG32 (0xE000C004))) +#define UART0_IIR (*(REG32 (0xE000C008))) +#define UART0_FCR (*(REG32 (0xE000C008))) +#define UART0_LCR (*(REG32 (0xE000C00C))) +#define UART0_LSR (*(REG32 (0xE000C014))) +#define UART0_SCR (*(REG32 (0xE000C01C))) +#define UART0_DLL (*(REG32 (0xE000C000))) +#define UART0_DLM (*(REG32 (0xE000C004))) + +/* ---- UART 1 --------------------------------------------- */ +#define UART1_RBR (*(REG32 (0xE0010000))) +#define UART1_THR (*(REG32 (0xE0010000))) +#define UART1_IER (*(REG32 (0xE0010004))) +#define UART1_IIR (*(REG32 (0xE0010008))) +#define UART1_FCR (*(REG32 (0xE0010008))) +#define UART1_LCR (*(REG32 (0xE001000C))) +#define UART1_LSR (*(REG32 (0xE0010014))) +#define UART1_SCR (*(REG32 (0xE001001C))) +#define UART1_DLL (*(REG32 (0xE0010000))) +#define UART1_DLM (*(REG32 (0xE0010004))) +#define UART1_MCR (*(REG32 (0xE0010010))) +#define UART1_MSR (*(REG32 (0xE0010018))) + + +/*############################################################################## +## I2C +##############################################################################*/ + +#define I2C_I2CONSET (*(REG32 (0xE001C000))) +#define I2C_I2STAT (*(REG32 (0xE001C004))) +#define I2C_I2DAT (*(REG32 (0xE001C008))) +#define I2C_I2ADR (*(REG32 (0xE001C00C))) +#define I2C_I2SCLH (*(REG32 (0xE001C010))) +#define I2C_I2SCLL (*(REG32 (0xE001C014))) +#define I2C_I2CONCLR (*(REG32 (0xE001C018))) + + +/*############################################################################## +## SPI - Serial Peripheral Interface +##############################################################################*/ + +#define SPI_SPCR (*(REG32 (0xE0020000))) +#define SPI_SPSR (*(REG32 (0xE0020004))) +#define SPI_SPDR (*(REG32 (0xE0020008))) +#define SPI_SPCCR (*(REG32 (0xE002000C))) +#define SPI_SPTCR (*(REG32 (0xE0020010))) +#define SPI_SPTSR (*(REG32 (0xE0020014))) +#define SPI_SPTOR (*(REG32 (0xE0020018))) +#define SPI_SPINT (*(REG32 (0xE002001C))) + + +/*############################################################################## +## Timer 0 and Timer 1 +##############################################################################*/ + +/* ---- Timer 0 -------------------------------------------- */ +#define T0_IR (*(REG32 (0xE0004000))) +#define T0_TCR (*(REG32 (0xE0004004))) +#define T0_TC (*(REG32 (0xE0004008))) +#define T0_PR (*(REG32 (0xE000400C))) +#define T0_PC (*(REG32 (0xE0004010))) +#define T0_MCR (*(REG32 (0xE0004014))) +#define T0_MR0 (*(REG32 (0xE0004018))) +#define T0_MR1 (*(REG32 (0xE000401C))) +#define T0_MR2 (*(REG32 (0xE0004020))) +#define T0_MR3 (*(REG32 (0xE0004024))) +#define T0_CCR (*(REG32 (0xE0004028))) +#define T0_CR0 (*(REG32 (0xE000402C))) +#define T0_CR1 (*(REG32 (0xE0004030))) +#define T0_CR2 (*(REG32 (0xE0004034))) +#define T0_CR3 (*(REG32 (0xE0004038))) +#define T0_EMR (*(REG32 (0xE000403C))) + +/* ---- Timer 1 -------------------------------------------- */ +#define T1_IR (*(REG32 (0xE0008000))) +#define T1_TCR (*(REG32 (0xE0008004))) +#define T1_TC (*(REG32 (0xE0008008))) +#define T1_PR (*(REG32 (0xE000800C))) +#define T1_PC (*(REG32 (0xE0008010))) +#define T1_MCR (*(REG32 (0xE0008014))) +#define T1_MR0 (*(REG32 (0xE0008018))) +#define T1_MR1 (*(REG32 (0xE000801C))) +#define T1_MR2 (*(REG32 (0xE0008020))) +#define T1_MR3 (*(REG32 (0xE0008024))) +#define T1_CCR (*(REG32 (0xE0008028))) +#define T1_CR0 (*(REG32 (0xE000802C))) +#define T1_CR1 (*(REG32 (0xE0008030))) +#define T1_CR2 (*(REG32 (0xE0008034))) +#define T1_CR3 (*(REG32 (0xE0008038))) +#define T1_EMR (*(REG32 (0xE000803C))) + + +/*############################################################################## +## PWM +##############################################################################*/ + +#define PWM_IR (*(REG32 (0xE0014000))) +#define PWM_TCR (*(REG32 (0xE0014004))) +#define PWM_TC (*(REG32 (0xE0014008))) +#define PWM_PR (*(REG32 (0xE001400C))) +#define PWM_PC (*(REG32 (0xE0014010))) +#define PWM_MCR (*(REG32 (0xE0014014))) +#define PWM_MR0 (*(REG32 (0xE0014018))) +#define PWM_MR1 (*(REG32 (0xE001401C))) +#define PWM_MR2 (*(REG32 (0xE0014020))) +#define PWM_MR3 (*(REG32 (0xE0014024))) +#define PWM_MR4 (*(REG32 (0xE0014040))) +#define PWM_MR5 (*(REG32 (0xE0014044))) +#define PWM_MR6 (*(REG32 (0xE0014048))) +#define PWM_EMR (*(REG32 (0xE001403C))) +#define PWM_PCR (*(REG32 (0xE001404C))) +#define PWM_LER (*(REG32 (0xE0014050))) +#define PWM_CCR (*(REG32 (0xE0014028))) +#define PWM_CR0 (*(REG32 (0xE001402C))) +#define PWM_CR1 (*(REG32 (0xE0014030))) +#define PWM_CR2 (*(REG32 (0xE0014034))) +#define PWM_CR3 (*(REG32 (0xE0014038))) + +/*############################################################################## +## RTC +##############################################################################*/ + +/* ---- RTC: Miscellaneous Register Group ------------------ */ +#define RTC_ILR (*(REG32 (0xE0024000))) +#define RTC_CTC (*(REG32 (0xE0024004))) +#define RTC_CCR (*(REG32 (0xE0024008))) +#define RTC_CIIR (*(REG32 (0xE002400C))) +#define RTC_AMR (*(REG32 (0xE0024010))) +#define RTC_CTIME0 (*(REG32 (0xE0024014))) +#define RTC_CTIME1 (*(REG32 (0xE0024018))) +#define RTC_CTIME2 (*(REG32 (0xE002401C))) + +/* ---- RTC: Timer Control Group --------------------------- */ +#define RTC_SEC (*(REG32 (0xE0024020))) +#define RTC_MIN (*(REG32 (0xE0024024))) +#define RTC_HOUR (*(REG32 (0xE0024028))) +#define RTC_DOM (*(REG32 (0xE002402C))) +#define RTC_DOW (*(REG32 (0xE0024030))) +#define RTC_DOY (*(REG32 (0xE0024034))) +#define RTC_MONTH (*(REG32 (0xE0024038))) +#define RTC_YEAR (*(REG32 (0xE002403C))) + +/* ---- RTC: Alarm Control Group --------------------------- */ +#define RTC_ALSEC (*(REG32 (0xE0024060))) +#define RTC_ALMIN (*(REG32 (0xE0024064))) +#define RTC_ALHOUR (*(REG32 (0xE0024068))) +#define RTC_ALDOM (*(REG32 (0xE002406C))) +#define RTC_ALDOW (*(REG32 (0xE0024070))) +#define RTC_ALDOY (*(REG32 (0xE0024074))) +#define RTC_ALMON (*(REG32 (0xE0024078))) +#define RTC_ALYEAR (*(REG32 (0xE002407C))) + +/* ---- RTC: Reference Clock Divider Group ----------------- */ +#define RTC_PREINT (*(REG32 (0xE0024080))) +#define RTC_PREFRAC (*(REG32 (0xE0024084))) + + +/*############################################################################## +## WD - Watchdog +##############################################################################*/ + +#define WD_WDMOD (*(REG32 (0xE0000000))) +#define WD_WDTC (*(REG32 (0xE0000004))) +#define WD_WDFEED (*(REG32 (0xE0000008))) +#define WD_WDTV (*(REG32 (0xE000000C))) + + +/*############################################################################## +## System Control Block +##############################################################################*/ + +#define SCB_EXTINT (*(REG32 (0xE01FC140))) +#define SCB_EXTWAKE (*(REG32 (0xE01FC144))) +#define SCB_MEMMAP (*(REG32 (0xE01FC040))) +#define SCB_PLLCON (*(REG32 (0xE01FC080))) +#define SCB_PLLCFG (*(REG32 (0xE01FC084))) +#define SCB_PLLSTAT (*(REG32 (0xE01FC088))) +#define SCB_PLLFEED (*(REG32 (0xE01FC08C))) +#define SCB_PCON (*(REG32 (0xE01FC0C0))) +#define SCB_PCONP (*(REG32 (0xE01FC0C4))) +#define SCB_VPBDIV (*(REG32 (0xE01FC100))) + +/*############################################################################## +## Memory Accelerator Module (MAM) +##############################################################################*/ + +#define MAM_TIM (*(REG32 (0xE01FC004))) +#define MAM_CR (*(REG32 (0xE01FC000))) + +#endif /* lpc210x_h */ + diff --git a/20080212/Demo/WizNET_DEMO_GCC_ARM7/main.c b/20080212/Demo/WizNET_DEMO_GCC_ARM7/main.c new file mode 100644 index 000000000..ed1c74ef3 --- /dev/null +++ b/20080212/Demo/WizNET_DEMO_GCC_ARM7/main.c @@ -0,0 +1,308 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. + The processor MUST be in supervisor mode when vTaskStartScheduler is + called. The demo applications included in the FreeRTOS.org download switch + to supervisor mode prior to main being called. If you are not using one of + these demo application projects then ensure Supervisor mode is used. +*/ + + +/* + * Program entry point. + * + * main() is responsible for setting up the microcontroller peripherals, then + * starting the demo application tasks. Once the tasks have been created the + * scheduler is started and main() should never complete. + * + * The demo creates the three standard 'flash' tasks to provide some visual + * feedback that the system and scheduler are still operating correctly. + * + * The HTTP server task operates at the highest priority so will always preempt + * the flash or idle task on TCP/IP events. + */ + +/* Standard includes. */ +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "semphr.h" +#include "task.h" + +/* Application includes. */ +#include "i2c.h" +#include "HTTP_Serv.h" +#include "flash.h" +#include "partest.h" +#include "dynamic.h" +#include "semtest.h" +#include "PollQ.h" +#include "BlockQ.h" +#include "integer.h" + +/*-----------------------------------------------------------*/ + +/* Constants to setup the PLL. */ +#define mainPLL_MUL_4 ( ( unsigned portCHAR ) 0x0003 ) +#define mainPLL_DIV_1 ( ( unsigned portCHAR ) 0x0000 ) +#define mainPLL_ENABLE ( ( unsigned portCHAR ) 0x0001 ) +#define mainPLL_CONNECT ( ( unsigned portCHAR ) 0x0003 ) +#define mainPLL_FEED_BYTE1 ( ( unsigned portCHAR ) 0xaa ) +#define mainPLL_FEED_BYTE2 ( ( unsigned portCHAR ) 0x55 ) +#define mainPLL_LOCK ( ( unsigned portLONG ) 0x0400 ) + +/* Constants to setup the MAM. */ +#define mainMAM_TIM_3 ( ( unsigned portCHAR ) 0x03 ) +#define mainMAM_MODE_FULL ( ( unsigned portCHAR ) 0x02 ) + +/* Constants to setup the peripheral bus. */ +#define mainBUS_CLK_FULL ( ( unsigned portCHAR ) 0x01 ) + +/* Constants to setup I/O and processor. */ +#define mainBUS_CLK_FULL ( ( unsigned portCHAR ) 0x01 ) +#define mainLED_TO_OUTPUT ( ( unsigned portLONG ) 0xff0000 ) +#define mainJTAG_PORT ( ( unsigned portLONG ) 0x3E0000UL ) + +/* Priorities for the demo application tasks. */ +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainHTTP_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainERROR_CHECK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* Flash rates of the on board LED to indicate the health of the system. */ +#define mainNO_ERROR_DELAY ( 3000 ) +#define mainERROR_DELAY ( 500 ) +#define mainON_BOARD_LED_BIT ( ( unsigned portLONG ) 0x80 ) + +/*-----------------------------------------------------------*/ + +/* + * The Olimex demo board has a single built in LED. This function simply + * toggles its state. + */ +void prvToggleOnBoardLED( void ); + +/* + * Configure the processor for use with the Olimex demo board. + */ +static void prvSetupHardware( void ); + +/* + * Simply check for errors and toggle the onboard LED. + */ +static void prvErrorChecks( void *pvParameters ); + +/* + * Return true if the demo tasks are executing without error - otherwise + * return false. + */ +static void prvMainCheckOtherTasksAreStillRunning( void ); +/*-----------------------------------------------------------*/ + +/* Flag set by prvMainCheckOtherTasksAreStillExecuting(). */ +portLONG lErrorInTask = pdFALSE; + +/* + * Application entry point: + * Starts all the other tasks, then starts the scheduler. + */ +int main( void ) +{ + /* Setup the hardware for use with the Olimex demo board. */ + prvSetupHardware(); + + /* Start the standard flash tasks so the WEB server is not the only thing + running. */ + vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); + vStartSemaphoreTasks( tskIDLE_PRIORITY ); + vStartDynamicPriorityTasks(); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + + /* Start the WEB server task and the error check task. */ + xTaskCreate( vHTTPServerTask, ( signed portCHAR * ) "HTTP", configMINIMAL_STACK_SIZE, NULL, mainHTTP_TASK_PRIORITY, NULL ); + xTaskCreate( prvErrorChecks, ( signed portCHAR * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainERROR_CHECK_PRIORITY, NULL ); + + /* Now all the tasks have been started - start the scheduler. + + NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. + The processor MUST be in supervisor mode when vTaskStartScheduler is + called. The demo applications included in the FreeRTOS.org download switch + to supervisor mode prior to main being called. If you are not using one of + these demo application projects then ensure Supervisor mode is used. */ + vTaskStartScheduler(); + + /* Should never reach here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + #ifdef RUN_FROM_RAM + /* Remap the interrupt vectors to RAM if we are are running from RAM. */ + SCB_MEMMAP = 2; + #endif + + /* Set all GPIO to output other than the P0.14 (BSL), and the JTAG pins. + The JTAG pins are left as input as I'm not sure what will happen if the + Wiggler is connected after powerup - not that it would be a good idea to + do that anyway. */ + GPIO_IODIR = ~( mainJTAG_PORT ); + + /* Setup the PLL to multiply the XTAL input by 4. */ + SCB_PLLCFG = ( mainPLL_MUL_4 | mainPLL_DIV_1 ); + + /* Activate the PLL by turning it on then feeding the correct sequence of + bytes. */ + SCB_PLLCON = mainPLL_ENABLE; + SCB_PLLFEED = mainPLL_FEED_BYTE1; + SCB_PLLFEED = mainPLL_FEED_BYTE2; + + /* Wait for the PLL to lock... */ + while( !( SCB_PLLSTAT & mainPLL_LOCK ) ); + + /* ...before connecting it using the feed sequence again. */ + SCB_PLLCON = mainPLL_CONNECT; + SCB_PLLFEED = mainPLL_FEED_BYTE1; + SCB_PLLFEED = mainPLL_FEED_BYTE2; + + /* Setup and turn on the MAM. Three cycle access is used due to the fast + PLL used. It is possible faster overall performance could be obtained by + tuning the MAM and PLL settings. */ + MAM_TIM = mainMAM_TIM_3; + MAM_CR = mainMAM_MODE_FULL; + + /* Setup the peripheral bus to be the same as the PLL output. */ + SCB_VPBDIV = mainBUS_CLK_FULL; + + /* Initialise the i2c peripheral. */ + i2cInit(); + + /* Initialise the LED's used by the flash tasks. */ + vParTestInitialise(); +} +/*-----------------------------------------------------------*/ + +static void prvMainCheckOtherTasksAreStillRunning( void ) +{ + /* Check all the demo tasks (other than the flash tasks) to ensure + that they are all still running, and that none of them have detected + an error. */ + + /* This function is called from more than one task. */ + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + lErrorInTask = pdTRUE; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + lErrorInTask = pdTRUE; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + lErrorInTask = pdTRUE; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + lErrorInTask = pdTRUE; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + lErrorInTask = pdTRUE; + } +} +/*-----------------------------------------------------------*/ + +void prvToggleOnBoardLED( void ) +{ +unsigned portLONG ulState; + + ulState = GPIO0_IOPIN; + if( ulState & mainON_BOARD_LED_BIT ) + { + GPIO_IOCLR = mainON_BOARD_LED_BIT; + } + else + { + GPIO_IOSET = mainON_BOARD_LED_BIT; + } +} +/*-----------------------------------------------------------*/ + +static void prvErrorChecks( void *pvParameters ) +{ +portTickType xDelay = mainNO_ERROR_DELAY; + + /* The parameters are not used. */ + ( void ) pvParameters; + + for( ;; ) + { + /* How long we delay depends on whether an error has been detected + or not. Therefore the flash rate of the on board LED indicates + whether or not an error has occurred. */ + vTaskDelay( xDelay ); + + /* Update the lErrorInTask flag. */ + prvMainCheckOtherTasksAreStillRunning(); + + if( lErrorInTask ) + { + /* An error has been found so reduce the delay period and in so + doing speed up the flash rate of the on board LED. */ + xDelay = mainERROR_DELAY; + } + + prvToggleOnBoardLED(); + } +} + diff --git a/20080212/Demo/WizNET_DEMO_TERN_186/186.cfg b/20080212/Demo/WizNET_DEMO_TERN_186/186.cfg new file mode 100644 index 000000000..f7e61706c --- /dev/null +++ b/20080212/Demo/WizNET_DEMO_TERN_186/186.cfg @@ -0,0 +1,145 @@ +// 186.cfg +// You must select RAM, ROM for your controller 04-26-2000 +// Your TERN controller is installed with SRAM and ROM with different sizes. +// For debug, 128K or 512K SRAM can be selected +// For build a ROM, you need to select the ROM size. +// How to select ? +// 1) commend out the unwanted #define RAM size line with "//" +// 2) delete the "//" preceding the wanted #define RAM size line +// + +// #define RAM 32 // 32KB SRAM installed +#define RAM 128 // 128KB SRAM installed +// #define RAM 512 // 512KB SRAM installed + +// #define ROM 32 // Use 32KB ROM chip 27C256-70 +#define ROM 64 // Use 64KB ROM chip 27C512-70 +// #define ROM 128 // Use 128KB ROM chip 27C010-70 +// #define ROM 256 // Use 256KB ROM chip 27C020-70 +// #define ROM 512 // Use 512KB ROM chip 27C040-70, Change Jumper on board + + +cputype Am186ES // AMD188/6 based controllers + +#if defined(__PDREMOTE__) + +#if RAM == 32 +map 0x00000 to 0x00fff as reserved // interrupt vector table +map 0x01000 to 0x03fff as rdwr // System RAM area (60KB RAM) +map 0x04000 to 0x07fff as rdonly // Simulated EPROM area (64KB RAM) +map 0x08000 to 0xfffff as reserved // No access allowed +#define CODE_START 0x0400 // Start of application code, STEP2 ! + +#elif RAM == 128 +map 0x00000 to 0x00fff as reserved // interrupt vector table +map 0x01000 to 0x07fff as rdwr // System RAM area (60KB RAM) +map 0x08000 to 0x1ffff as rdonly // Simulated EPROM area (64KB RAM) +map 0x20000 to 0xfffff as reserved // No access allowed +#define CODE_START 0x0800 // Start of application code + +#elif RAM == 512 +map 0x00000 to 0x00fff as reserved // interrupt vector table +map 0x01000 to 0x07fff as rdwr // System RAM area (60KB RAM) +map 0x08000 to 0x7ffff as rdonly // Simulated EPROM area(480KB RAM) +map 0x80000 to 0xfffff as reserved // No access allowed +#define CODE_START 0x0800 // Start of application code +#endif + +#define DATA_START 0x0100 // Start of application data +#define BOOT_START 0x1fc0 // Start of initialization code + +#else +#if ROM == 32 +map 0x00000 to 0x1ffff as rdwr // 128KB RAM address space +map 0x20000 to 0xf7fff as reserved // No access +map 0xF8000 to 0xfffff as rdonly // 32KB EPROM address space +#define CODE_START 0xF800 // Start of application code +#elif ROM == 64 +map 0x00000 to 0x1ffff as rdwr // 128KB RAM address space +map 0x20000 to 0xEffff as reserved // No access +map 0xF0000 to 0xfffff as rdonly // 64KB EPROM address space +#define CODE_START 0xF000 // Start of application code +#elif ROM == 128 +map 0x00000 to 0x1ffff as rdwr // 128KB RAM address space +map 0x20000 to 0xDffff as reserved // No access +map 0xE0000 to 0xfffff as rdonly // 128KB EPROM address space +#define CODE_START 0xE000 // Start of application code +#elif ROM == 256 +map 0x00000 to 0x1ffff as rdwr // 128KB RAM address space +map 0x20000 to 0xBffff as reserved // No access +map 0xC0000 to 0xfffff as rdonly // 256KB EPROM address space +#define CODE_START 0xC000 // Start of application code +#elif ROM == 512 +map 0x00000 to 0x1ffff as rdwr // 128KB RAM address space +map 0x20000 to 0x7ffff as reserved // No access +map 0x80000 to 0xfffff as rdonly // 512KB EPROM address space +#define CODE_START 0x8000 // Start of application code +#endif + +#define DATA_START 0x0040 // Start of application data +#define BOOT_START 0xffc0 // Start of initialization code + +initcode reset \ // Reset vector to program entry point + umcs = 0x80bf \ // 512K ROM, 3 wait states + lmcs = 0x7fbf \ // 512K RAM, 3 wait states + mpcs = 0xa0bf \ + mmcs = 0x81ff \ + pacs = 0x007f + +class ??LOCATE = BOOT_START // Chip select initialization +output ??LOCATE + +#if ROM == 32 // 27C256-90 EPROM or FLASH +hexfile binary offset=0xf8000 size=32 // for 27C256, bin file +#elif ROM == 64 // 27C512-90 EPROM or FLASH +hexfile binary offset=0xF0000 size=64 // for 27C512 +#elif ROM == 128 // 27C010-90 EPROM or FLASH +hexfile binary offset=0xE0000 size=128 // for 27C010 +#elif ROM == 256 // 27C020-90 EPROM or FLASH +hexfile binary offset=0xC0000 size=256 // for 27C020 +#elif ROM == 512 // 27C040-90 EPROM or FLASH +hexfile Intel86 offset=0x80000 size=512 // for 27C040, output .HEX file +#endif + +#endif + + +// +// Start of common configuration file settings. +// + +absfile axe86 // Paradigm C++ debugging output +listfile segments // Absolute segment map + +dup DATA ROMDATA // Make a copy of initialized data +dup FAR_DATA ROMFARDATA // Make a copy of far initialized data + +#if defined(__COMPFARDATA__) // Compress and display results +compress ROMFARDATA +display compression +#endif + +class CODE = CODE_START // Application code +class DATA = DATA_START // Application data + +order DATA \ // RAM class organization + BSS \ + NVRAM \ + EDATA \ + STACK \ + FAR_DATA ENDFAR_DATA \ + FAR_BSS ENDFAR_BSS \ + FAR_HEAP ENDFAR_HEAP + +order CODE \ // EPROM class organization + INITDATA EXITDATA \ + FAR_CONST ENDFAR_CONST \ + ROMDATA ENDROMDATA \ + ROMFARDATA ENDROMFARDATA + +output CODE \ // Classes in the output file(s) + INITDATA EXITDATA \ + FAR_CONST ENDFAR_CONST \ + ROMDATA ENDROMDATA \ + ROMFARDATA ENDROMFARDATA + \ No newline at end of file diff --git a/20080212/Demo/WizNET_DEMO_TERN_186/AE.LIB b/20080212/Demo/WizNET_DEMO_TERN_186/AE.LIB new file mode 100644 index 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z=}HKOXk|IwOw=&oM|oiMK@-K^jTw-8clwVrsJ$NNgm_&#@l8CSB<#`29XT~iyo* +#include + +/* Tern includes. */ +#include "utils\system_common.h" +#include "i2chip_hw.h" +#include "socket.h" + +/* FreeRTOS.org includes. */ +#include +#include +#include + +/* The standard http port on which we are going to listen. */ +#define httpPORT 80 + +#define httpTX_WAIT 2 + +/* Network address configuration. */ +const unsigned portCHAR ucMacAddress[] = { 12, 128, 12, 34, 56, 78 }; +const unsigned portCHAR ucGatewayAddress[] = { 192, 168, 2, 1 }; +const unsigned portCHAR ucIPAddress[] = { 172, 25, 218, 210 }; +const unsigned portCHAR ucSubnetMask[] = { 255, 255, 255, 0 }; + +/* The number of sockets this task is going to handle. */ +#define httpSOCKET_NUM 3 +unsigned portCHAR ucConnection[ httpSOCKET_NUM ]; + +/* The maximum data buffer size we can handle. */ +#define httpSOCKET_BUFFER_SIZE 2048 + +/* Standard HTTP response. */ +#define httpOUTPUT_OK "HTTP/1.0 200 OK\r\nContent-Type: text/html\r\n\r\n" + +/* Hard coded HTML components. Other data is generated dynamically. */ +#define HTML_OUTPUT_BEGIN "\ +\ +

FreeRTOS.orgtm + Tern E-Enginetm

\ +FreeRTOS.org Homepage

\ +

Task status table:\r\n\ +

Task          State  Priority  Stack	#
\
+************************************************
"
+
+#define HTML_OUTPUT_END   "\
+"
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the data structures used to hold the socket status.
+ */
+static void prvHTTPInit( void );
+
+/*
+ * Setup the Ethernet interface with the network addressing information.
+ */
+static void prvNetifInit( void );
+
+/*
+ * Generate the dynamic components of the served WEB page and transmit the 
+ * entire page through the socket.
+ */
+static void prvTransmitHTTP( unsigned portCHAR socket );
+/*-----------------------------------------------------------*/
+
+/* This variable is simply incremented by the idle task hook so the number of
+iterations the idle task has performed can be displayed as part of the served
+page. */
+unsigned portLONG ulIdleLoops = 0UL;
+
+/* Data buffer shared by sockets. */
+unsigned portCHAR ucSocketBuffer[ httpSOCKET_BUFFER_SIZE ];
+
+/* The semaphore used by the Ethernet ISR to signal that the task should wake
+and process whatever caused the interrupt. */
+xSemaphoreHandle xTCPSemaphore = NULL;
+
+/*-----------------------------------------------------------*/
+void vHTTPTask( void * pvParameters )
+{
+portSHORT i, sLen;
+unsigned portCHAR ucState;
+
+	( void ) pvParameters;
+
+    /* Create the semaphore used to communicate between this task and the
+    WIZnet ISR. */
+    vSemaphoreCreateBinary( xTCPSemaphore );
+
+	/* Make sure everything is setup before we start. */
+	prvNetifInit();
+	prvHTTPInit();
+
+	for( ;; )
+	{
+		/* Wait until the ISR tells us there is something to do. */
+    	xSemaphoreTake( xTCPSemaphore, portMAX_DELAY );
+
+		/* Check each socket. */
+		for( i = 0; i < httpSOCKET_NUM; i++ )
+		{
+			ucState = select( i, SEL_CONTROL );
+
+			switch (ucState)
+			{
+				case SOCK_ESTABLISHED :  /* new connection established. */
+
+					if( ( sLen = select( i, SEL_RECV ) ) > 0 )
+					{
+						if( sLen > httpSOCKET_BUFFER_SIZE ) 
+						{
+							sLen = httpSOCKET_BUFFER_SIZE;
+						}
+
+						disable();
+						
+						sLen = recv( i, ucSocketBuffer, sLen );    
+
+						if( ucConnection[ i ] == 1 )
+						{	
+							/* This is our first time processing a HTTP
+							 request on this connection. */
+							prvTransmitHTTP( i );
+							ucConnection[i] = 0;
+						}
+						enable();
+					}
+					break;
+
+				case SOCK_CLOSE_WAIT :
+
+					close(i);
+					break;
+
+				case SOCK_CLOSED :
+
+					ucConnection[i] = 1;
+					socket( i, SOCK_STREAM, 80, 0x00 );
+					NBlisten( i ); /* reinitialize socket. */
+					break;
+			}
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvHTTPInit( void )
+{
+unsigned portCHAR ucIndex;
+
+	/* There are 4 total sockets available; we will claim 3 for HTTP. */
+	for(ucIndex = 0; ucIndex < httpSOCKET_NUM; ucIndex++)
+	{
+		socket( ucIndex, SOCK_STREAM, httpPORT, 0x00 );
+		NBlisten( ucIndex );
+		ucConnection[ ucIndex ] = 1;
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvNetifInit( void )
+{
+	i2chip_init();
+	initW3100A();
+
+	setMACAddr( ( unsigned portCHAR * ) ucMacAddress );
+	setgateway( ( unsigned portCHAR * ) ucGatewayAddress );
+	setsubmask( ( unsigned portCHAR * ) ucSubnetMask );
+	setIP( ( unsigned portCHAR * ) ucIPAddress );
+
+	/* See definition of 'sysinit' in socket.c
+	 - 8 KB transmit buffer, and 8 KB receive buffer available.  These buffers
+	   are shared by all 4 channels.
+	 - (0x55, 0x55) configures the send and receive buffers at 
+		httpSOCKET_BUFFER_SIZE bytes for each of the 4 channels. */
+	sysinit( 0x55, 0x55 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvTransmitHTTP(unsigned portCHAR socket)
+{
+extern portSHORT usCheckStatus;
+
+	/* Send the http and html headers. */
+	send( socket, ( unsigned portCHAR * ) httpOUTPUT_OK, strlen( httpOUTPUT_OK ) );
+	send( socket, ( unsigned portCHAR * ) HTML_OUTPUT_BEGIN, strlen( HTML_OUTPUT_BEGIN ) );
+
+	/* Generate then send the table showing the status of each task. */
+	vTaskList( ucSocketBuffer );
+ 	send( socket, ( unsigned portCHAR * ) ucSocketBuffer, strlen( ucSocketBuffer ) );
+
+	/* Send the number of times the idle task has looped. */
+    sprintf( ucSocketBuffer, "


The idle task has looped 0x%08lx times
", ulIdleLoops ); + send( socket, ( unsigned portCHAR * ) ucSocketBuffer, strlen( ucSocketBuffer ) ); + + /* Send the tick count. */ + sprintf( ucSocketBuffer, "The tick count is 0x%08lx
", xTaskGetTickCount() ); + send( socket, ( unsigned portCHAR * ) ucSocketBuffer, strlen( ucSocketBuffer ) ); + + /* Show a message indicating whether or not the check task has discovered + an error in any of the standard demo tasks. */ + if( usCheckStatus == 0 ) + { + sprintf( ucSocketBuffer, "No errors detected." ); + send( socket, ( unsigned portCHAR * ) ucSocketBuffer, strlen( ucSocketBuffer ) ); + } + else + { + sprintf( ucSocketBuffer, "An error has been detected in at least one task %x.

", usCheckStatus ); + send( socket, ( unsigned portCHAR * ) ucSocketBuffer, strlen( ucSocketBuffer ) ); + } + + /* Finish the page off. */ + send( socket, (unsigned portCHAR*)HTML_OUTPUT_END, strlen(HTML_OUTPUT_END)); + + /* Must make sure the data is gone before closing the socket. */ + while( !tx_empty( socket ) ) + { + vTaskDelay( httpTX_WAIT ); + } + close(socket); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ + ulIdleLoops++; +} + + + + + + + + + + + + + + + + + + + + diff --git a/20080212/Demo/WizNET_DEMO_TERN_186/HTTPTask.h b/20080212/Demo/WizNET_DEMO_TERN_186/HTTPTask.h new file mode 100644 index 000000000..27e09fd9a --- /dev/null +++ b/20080212/Demo/WizNET_DEMO_TERN_186/HTTPTask.h @@ -0,0 +1,49 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef HTTP_TASK_H +#define HTTP_TASK_H + +void vHTTPTask( void *pvParameters ); + +#endif + diff --git a/20080212/Demo/WizNET_DEMO_TERN_186/RTOSDemo.DSW b/20080212/Demo/WizNET_DEMO_TERN_186/RTOSDemo.DSW new file mode 100644 index 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Note all byte access is at even addresses +* 2005/10/8 : Modified constants for easier initialization. +* +* Description : Header file of W3100A for TERN embedded controller +******************************************************************************** +*/ +#ifndef __SOCKET_H__ +#define __SOCKET_H__ + +#include "types.h" +#include "i2chip_hw.h" +#include + +/*******************************************************************/ +#define MAX_SOCK_NUM 4 // Concurrent maxmium number of socket + +#define I2CHIP_C0_CR 0x00 +#define I2CHIP_C1_CR 0x01 +#define I2CHIP_C2_CR 0x02 +#define I2CHIP_C3_CR 0x03 +#define I2CHIP_C0_ISR 0x04 +#define I2CHIP_C1_ISR 0x05 +#define I2CHIP_C2_ISR 0x06 +#define I2CHIP_C3_ISR 0x07 +#define I2CHIP_IR 0x08 +#define I2CHIP_IMR 0x09 + +#define I2CHIP_IDM_OR 0x0C +#define I2CHIP_IDM_AR0 0x0D +#define I2CHIP_IDM_AR1 0x0E +#define I2CHIP_IDM_DR 0x0F +#define I2CHIP_C0_RW_PR 0x10 +#define I2CHIP_C0_RR_PR 0x14 +#define I2CHIP_C0_TA_PR 0x18 +#define I2CHIP_C1_RW_PR 0x1C +#define I2CHIP_C1_RR_PR 0x20 +#define I2CHIP_C1_TA_PR 0x24 +#define I2CHIP_C2_RW_PR 0x28 +#define I2CHIP_C2_RR_PR 0x2C +#define I2CHIP_C2_TA_PR 0x30 +#define I2CHIP_C3_RW_PR 0x34 +#define I2CHIP_C3_RR_PR 0x38 +#define I2CHIP_C3_TA_PR 0x3C +#define I2CHIP_C0_TW_PR 0x40 +#define I2CHIP_C0_TR_PR 0x44 +#define I2CHIP_C1_TW_PR 0x4C +#define I2CHIP_C1_TR_PR 0x50 +#define I2CHIP_C2_TW_PR 0x58 +#define I2CHIP_C2_TR_PR 0x5C +#define I2CHIP_C3_TW_PR 0x64 +#define I2CHIP_C3_TR_PR 0x68 +#define I2CHIP_GAR 0x80 +#define I2CHIP_SMR 0x84 +#define I2CHIP_SHAR 0x88 +#define I2CHIP_SIPR 0x8E +#define I2CHIP_IRTR 0x92 +#define I2CHIP_RCR 0x94 +#define I2CHIP_RMSR 0x95 +#define I2CHIP_TMSR 0x96 +#define I2CHIP_C0_SSR 0xA0 +#define I2CHIP_C0_SOPR 0xA1 +#define I2CHIP_C0_DIR 0xA8 +#define I2CHIP_CO_DPR 0xAC +#define I2CHIP_C0_SPR 0xAE +#define I2CHIP_C0_IPR 0xB0 +#define I2CHIP_C0_TOSR 0xB1 +#define I2CHIP_C0_MSSR 0xB2 + +#define I2CHIP_C1_SSR 0xB8 +#define I2CHIP_C1_SOPR 0xB9 +#define I2CHIP_C1_DIR 0xC0 +#define I2CHIP_C1_DPR 0xC4 +#define I2CHIP_C1_SPR 0xC6 +#define I2CHIP_C1_IPR 0xC8 +#define I2CHIP_C1_TOSR 0xC9 +#define I2CHIP_C1_MSSR 0xCA + +#define I2CHIP_C2_SSR 0xD0 +#define I2CHIP_C2_SOPR 0xD1 +#define I2CHIP_C2_DIR 0xD8 +#define I2CHIP_C2_DPR 0xDC +#define I2CHIP_C2_SPR 0xDE +#define I2CHIP_C2_IPR 0xE0 +#define I2CHIP_C2_TOSR 0xE1 +#define I2CHIP_C2_MSSR 0xE2 + +#define I2CHIP_C3_SSR 0xE8 +#define I2CHIP_C3_SOPR 0xE9 +#define I2CHIP_C3_DIR 0xF0 +#define I2CHIP_C3_DPR 0xF4 +#define I2CHIP_C3_SPR 0xF6 +#define I2CHIP_C3_IPR 0xF8 +#define I2CHIP_C3_TOSR 0xF9 +#define I2CHIP_C3_MSSR 0xFA + +#define MAX_SEGMENT_SIZE 1460 // Maximum TCP transmission packet size +#define MAX_BUF_SIZE1 0 + + +/* SOCKET OPTION(Settting OPT_PROTOCOL REG.) */ +#define SOCKOPT_BROADCAST 0x80 // Transmission, Reception of broadcasting data +#define SOCKOPT_NDTIMEOUT 0x40 // Setting timeout +#define SOCKOPT_NDACK 0x20 // Setting No Delayed Ack(TCP) +#define SOCKOPT_SWS 0x10 // Setting Silly Window Syndrome(TCP) + +/* OPTION(Setting OPT_PROTOCOL REG.) for MAC LAYER RAW MODE */ +#define MACLOPT_RXERR 0x80 // Setting reception of error packet +#define MACLOPT_BROADCAST 0x40 // Setting reception of broadcast packet +#define MACLOPT_PROMISC 0x20 // Setting reception of promiscuous packet + +/* Distinguish TCP / UDP / IP RAW / MAC RAW (Setting OPT_PROTOCOL REG.) */ +#define SOCK_CLOSEDM 0x00 // unused socket +#define SOCK_STREAM 0x01 // TCP +#define SOCK_DGRAM 0x02 // UDP +#define SOCK_IPL_RAW 0x03 // IP LAYER RAW SOCK +#define SOCK_MACL_RAW 0x04 // MAC LAYER RAW SOCK + +/* Setting IP PROTOCOL */ +#define IPPROTO_IP 0 // dummy for IP +#define IPPROTO_ICMP 1 // control message protocol +#define IPPROTO_IGMP 2 // internet group management protocol +#define IPPROTO_GGP 3 // gateway^2 (deprecated) +#define IPPROTO_TCP 6 // tcp +#define IPPROTO_PUP 12 // pup +#define IPPROTO_UDP 17 // user datagram protocol +#define IPPROTO_IDP 22 // xns idp +#define IPPROTO_ND 77 // UNOFFICIAL net disk proto +#define IPPROTO_RAW 255 // raw IP packet + +/* Select parameter to use */ +#define SEL_CONTROL 0 //Confirm socket status +#define SEL_SEND 1 // Confirm Tx free buffer size +#define SEL_RECV 2 // Confirm Rx data size + +/* Command variables */ +#define CSYS_INIT 0x01 // To set up network information(mac address, gateway address, + // subnet mask, source ip) +#define CSOCK_INIT 0x02 // To initialize socket +#define CCONNECT 0x04 // To establish connection as tcp client mode +#define CLISTEN 0x08 // To wait for connection request as tcp server mode +#define CCLOSE 0x10 // To terminate connection +#define CSEND 0x20 // To send data +#define CRECV 0x40 // To receive data +#define CSW_RESET 0x80 // To do software reset + +#define CSET_MEMORY_TEST 0x80 // To set the memory test bit +#define CRESET_MEMORY_TEST 0x00 // To clear the memory test bit + +/* Status Variables */ +#define SSYS_INIT_OK 0x01 // Completion of CSYS_INIT command +#define SSOCK_INIT_OK 0x02 // Completion of CSOCK_INIT command +#define SESTABLISHED 0x04 // Completion of connection setup +#define SCLOSED 0x08 // Completion of CCLOSED command +#define SSEND_OK 0x20 // Completion of sending data +#define SRECV_OK 0x40 // Completion of receiving data + +/* Socket Status Vabiables */ +#define SOCK_CLOSED 0x00 // Status of connection closed +#define SOCK_ARP 0x01 // Status of ARP +#define SOCK_LISTEN 0x02 // Status of waiting for TCP connection setup +#define SOCK_SYNSENT 0x03 // Status of setting up TCP connection +#define SOCK_SYNSENT_ACK 0x04 // Status of setting up TCP connection +#define SOCK_SYNRECV 0x05 // Status of setting up TCP connection +#define SOCK_ESTABLISHED 0x06 // Status of TCP connection established +#define SOCK_CLOSE_WAIT 0x07 // Status of closing TCP connection +#define SOCK_LAST_ACK 0x08 // Status of closing TCP connection +#define SOCK_FIN_WAIT1 0x09 // Status of closing TCP connection +#define SOCK_FIN_WAIT2 0x0A // Status of closing TCP connection +#define SOCK_CLOSING 0x0B // Status of closing TCP connection +#define SOCK_TIME_WAIT 0x0C // Status of closing TCP connection +#define SOCK_RESET 0x0D // Status of closing TCP connection +#define SOCK_INIT 0x0E // Status of socket initialization +#define SOCK_UDP 0x0F // Status of UDP +#define SOCK_RAW 0x10 // Status of IP RAW + +/* TERN Behavior Parameters */ +#define TERN_TDMA_THRES 10000 // Use DMA for transmits if data > thres bytes. +#define TERN_RDMA_THRES 10000 // Use DMA for receives if data > thres bytes. + // High thres value effectively disables DMA + +void far interrupt in4_isr_i2chip(void); + +//void ISR_ESTABLISHED(SOCKET s); +//void ISR_CLOSED(SOCKET s); +//void ISR_RX(SOCKET s); + +void initW3100A(void); +void sysinit(u_char sbufsize, u_char rbufsize); +void setsubmask(u_char * addr); +void setgateway(u_char * addr); +void setMACAddr(u_char * addr); +void setIP(u_char * addr); + +char socket(SOCKET s, u_char protocol, u_int port, u_char flag); + +void setIPprotocol(SOCKET s, u_char ipprotocol); + +void setINTMask(u_char mask); +void settimeout(u_char * val); +void setTOS(SOCKET s, u_char tos); + +void GetDestAddr(SOCKET s, u_char* addr); + +//void setbroadcast(SOCKET s); + +char connect(SOCKET s, u_char far * addr, u_int port); +char NBconnect(SOCKET s, u_char far * addr, u_int port); + +//char listen(SOCKET s, u_char far * addr, u_int far * port); +char NBlisten(SOCKET s); + +void initseqnum(SOCKET s); + +int send(SOCKET s, u_char far * buf, u_int len); +int send_in(SOCKET s, u_char far * buf, u_int len); +int recv(SOCKET s, u_char far * buf, u_int len); + +u_int sendto(SOCKET , u_char far * buf, u_int, u_char * addr, u_int); +u_int sendto_in(SOCKET , u_char far *, u_int); +u_int recvfrom(SOCKET , u_char far * buf, u_int, u_char * addr, u_int *); + +u_int read_data(SOCKET s, u_int src_offset, u_char far * dst, u_int len); +u_int write_data(SOCKET s, u_char far * src, u_int dst_offset, u_int len); + +void close(SOCKET s); +char reset_sock(SOCKET s); + +u_int select(SOCKET s, u_char func); +void recv_clear(SOCKET s); +u_char tx_empty(SOCKET s); + +#endif // __SOCKET_H__ diff --git a/20080212/Demo/WizNET_DEMO_TERN_186/include/TYPES.H b/20080212/Demo/WizNET_DEMO_TERN_186/include/TYPES.H new file mode 100644 index 000000000..eb4551e94 --- /dev/null +++ b/20080212/Demo/WizNET_DEMO_TERN_186/include/TYPES.H @@ -0,0 +1,64 @@ +/* +******************************************************************************** +* Wiznet. +* 5F Simmtech Bldg., 228-3, Nonhyun-dong, Kangnam-gu, +* Seoul, Korea +* +* (c) Copyright 2002, Wiznet, Seoul, Korea +* +* Filename : types.h +* Programmer(s): +* Created : 2002/01/ +* Modified : +* Description : Define of data type. +******************************************************************************** +*/ + +#ifndef _TYPES_H_ +#define _TYPES_H_ + +#ifndef NULL +# define NULL ((void *) 0) +#endif + +typedef enum { false, true } bool; + +#ifndef _SIZE_T +#define _SIZE_T +typedef unsigned int size_t; +#endif + +typedef unsigned char BYTE; // 8-bit value +typedef unsigned char UCHAR; // 8-bit value +typedef int INT; // 16-bit value +typedef unsigned int UINT; // 16-bit value +typedef unsigned short USHORT; // 16-bit value +typedef unsigned short WORD; // 16-bit value +typedef unsigned long ULONG; // 32-bit value +typedef unsigned long DWORD; // 32-bit value + +// bsd +typedef unsigned char u_char; // 8-bit value +typedef unsigned short u_short; // 16-bit value +typedef unsigned int u_int; // 16-bit value +typedef unsigned long u_long; // 32-bit value + +typedef UCHAR SOCKET; + + +/* Type for treating 4 byte variables with byte by byte */ +typedef union un_l2cval + { + u_long lVal; + u_char cVal[4]; + }; + +/* Type for treating 2 byte variables with byte by byte */ +typedef union un_i2cval + { + u_int iVal; + u_char cVal[2]; + }; + +#endif // _TYPES_H_ + diff --git a/20080212/Demo/WizNET_DEMO_TERN_186/include/ae.H b/20080212/Demo/WizNET_DEMO_TERN_186/include/ae.H new file mode 100644 index 000000000..060c7efb0 --- /dev/null +++ b/20080212/Demo/WizNET_DEMO_TERN_186/include/ae.H @@ -0,0 +1,264 @@ +#ifndef _AE_H_ +#define _AE_H_ + +/********************************************************************* + ae.h headers for AM188ES 6-20-99 7-16-98 +*********************************************************************/ +/* Data structure for Serial operation */ + +typedef struct { + unsigned char ready; /* TRUE when ready */ + unsigned char baud; + unsigned int mode; + unsigned char iflag; /* interrupt status */ + unsigned char* in_buf; /* Input buffer */ + unsigned int in_tail; /* Input buffer TAIL ptr */ + unsigned int in_head; /* Input buffer HEAD ptr */ + unsigned int in_size; /* Input buffer size */ + unsigned int in_crcnt; /* Input count */ + unsigned char in_mt; /* Input buffer FLAG */ + unsigned char in_full; /* input buffer full */ + unsigned char* out_buf; /* Output buffer */ + unsigned int out_tail; /* Output buffer TAIL ptr */ + unsigned int out_head; /* Output buffer HEAD ptr */ + unsigned int out_size; /* Output buffer size */ + unsigned char out_full; /* Output buffer FLAG */ + unsigned char out_mt; /* Output buffer MT */ + unsigned char tmso; // transmit macro service operation + unsigned char rts; + unsigned char dtr; + unsigned char en485; + unsigned char err; + unsigned char node; + unsigned char cr; /* scc CR register */ + unsigned char slave; + unsigned int in_segm; /* input buffer segment */ + unsigned int in_offs; /* input buffer offset */ + unsigned int out_segm; /* output buffer segment */ + unsigned int out_offs; /* output buffer offset */ + unsigned char byte_delay; /* V25 macro service byte delay */ +} COM; + + +typedef struct{ + unsigned char sec1; + unsigned char sec10; + unsigned char min1; + unsigned char min10; + unsigned char hour1; + unsigned char hour10; + unsigned char day1; + unsigned char day10; + unsigned char mon1; + unsigned char mon10; + unsigned char year1; + unsigned char year10; + unsigned char wk; +} TIM; + +void ae_init(void); +void ae_reset(void); +void led(int i); //P12 used for led +void delay_ms(int m); +void delay0(unsigned int t); +void HLPRsetvect( + unsigned int wVec, /* Interrupt vector number */ + void far *ih /* Interrupt handler to install */ + ); + +void clka_en(int i); +void clkb_en(int i); +void pwr_save_en(int i); +void hitwd(void); + +// +// reset ee to remain enabled for reads +// where s = segment register value pointing to ee starting addr. +// for example = 0x8000 +// +void amd_ee_read_reset(unsigned int s); + +// +// sec=0x00-0x07 for AM29F010, 16K/sector +// sec=0 0x00000-0x03fff +// sec=1 0x04000-0x07fff +// sec=2 0x08000-0x0bfff +// sec=3 0x0c000-0x0ffff +// sec=4 0x10000-0x13fff +// sec=5 0x14000-0x17fff +// sec=6 0x18000-0x1bfff +// sec=7 0x1c000-0x1ffff +// +// sec=0x10-0x17 for AM29F040 +// sec=10 0x00000-0x0ffff +// sec=11 0x10000-0x1ffff +// sec=12 0x20000-0x2ffff +// sec=13 0x30000-0x3ffff +// sec=14 0x40000-0x4ffff +// sec=15 0x50000-0x5ffff +// sec=16 0x60000-0x6ffff +// sec=17 0x70000-0x7ffff +// segm=segment register value pointing to ee address 0 +// returns: if pass, return(0); +// if fail, return(1); +// +int amd_ee_sec_erase(unsigned int segm, unsigned char sec ); + +// +// write one byte dat to AM29F040, at address of s:o +// Approximately 70 us for 0 wait, 80us for 1 wait. +// where s=segment register, it is fixed to 0x8000 +// o=offset register +// returns: if pass, return(0); +// if fail, return(1); +// +// Be aware of that a data bit "0" can not be programmed back to a "1" !!! +// Attempting to do so will hang up the system !!! +// you can program the "1"s to "0"s. +// Only erase operation can convert "0"s to "1"s +// +// + +int amd_ee_byte_pro_512(unsigned int s, unsigned int o, unsigned char dat); + +// +// write one byte dat to AM29F010, at address of s:o, 80us per byte approx. +// where s=segment register, you may use s=0x8000-0xe000 +// o=offset register +// returns: if pass, return(0); +// if fail, return(1); +// +// Be aware of that a data bit "0" can not be programmed back to a "1" !!! +// Attempting to do so will hang up the system !!! +// you can program the "1"s to "0"s. +// Only erase operation can convert "0"s to "1"s +// + +int amd_ee_byte_pro_128(unsigned int s, unsigned int o, unsigned char dat); + +// +// unsigned char rtc_rds(char* time_string); +// put a time string into time_string, based on the reading of RTC. +// At least 15 bytes of buffer must be available for the time_string +// returns 0, if RTC OK, or returns 1, if problem +// +unsigned char rtc_rds(char* time_string); +int rtc_rd(TIM *r); +void rtc_init(unsigned char*); +unsigned char r_rd(void); +int r_out(unsigned char v); + + +void t2_init(unsigned int tm,unsigned int ta,void interrupt far(*t2_isr)()); +void t1_init(unsigned int tm,unsigned int ta,unsigned int tb,void interrupt far(*t1_isr)()); +void t0_init(unsigned int tm,unsigned int ta,unsigned int tb,void interrupt far(*t0_isr)()); +unsigned int t2_rd(void); +unsigned int t1_rd(void); +unsigned int t0_rd(void); + +// Analog to Digital conversion using TLC2543 on the A-Engine-88/86 +// Input: +// unsigned char c = input channel +// c = 0, input ch = AD0 +// c = 1, input ch = AD1 +// c = 2, input ch = AD2 +// c = 3, input ch = AD3 +// c = 4, input ch = AD4 +// c = 5, input ch = AD5 +// c = 6, input ch = AD6 +// c = 7, input ch = AD7 +// c = 8, input ch = AD8 +// c = 9, input ch = AD9 +// c = a, input ch = AD10 +// In order to operate ADC, P11 must be input. +// P11 is shared by RTC, EE. It must be high while power on/reset +// For AE88, using PPI for ADC, I20,I21,I22 must be output +// For AE86, using PAL for ADC, T0=CLK, T1=DIN, T2=ADCS +// Enter the ae_ad12(unsigned char c); EE is stopped first. +// Enter the ae86_ad12(unsigned char c); EE is stopped first. +// +// Output: 12 bit AD data of the previous channel ! +// Unipolar: +// (Vref+ - Vref-)=0x7ff +// Vref- = 0x000 +// Vref+ = 0xfff +// +// +int ae_ad12(unsigned char c); + +// outportb(0x120,1); // T0=0, CLK +// outportb(0x128,1); // T1=0, DIN +// outportb(0x130,1); // T2=0, ADCS +int ae86_ad12(unsigned char c); + +void nmi_init(void interrupt far (* nmi_isr)()); +void int0_init(unsigned char i, void interrupt far (*int0_isr)()); +void int1_init(unsigned char i, void interrupt far (*int1_isr)()); +void int2_init(unsigned char i, void interrupt far (*int2_isr)()); +void int3_init(unsigned char i, void interrupt far (*int3_isr)()); +void int4_init(unsigned char i, void interrupt far (*int4_isr)()); +void int5_init(unsigned char i, void interrupt far (*int5_isr)()); +void int6_init(unsigned char i, void interrupt far (*int6_isr)()); + + +// +// void pio_init(char bit, char mode) +// where bit=0-31 +// mode=0, Normal operation +// mode=1, Input with pullup/down +// mode=2, Output +// mode=3, input without pull +// +void pio_init(char bit, char mode); + + +// +// void pio_wr(char bit, char dat) +// where bit=0-31 +// dat=0/1 +// +void pio_wr(char bit, char dat); + +// +// unsigned int pio_rd(char port) +// return P15-P0, if port=0 +// return P31-P16, if port=1 +// +unsigned int pio_rd(char port); + +// setup I/O wait states for I/O instructions +// where wait = 0-7 +// wait=0, wait states = 0, I/O enable for 100 ns +// wait=1, wait states = 1, I/O enable for 100+25 ns +// wait=2, wait states = 2, I/O enable for 100+50 ns +// wait=3, wait states = 3, I/O enable for 100+75 ns +// wait=4, wait states = 5, I/O enable for 100+125 ns +// wait=5, wait states = 7, I/O enable for 100+175 ns +// wait=6, wait states = 9, I/O enable for 100+225 ns +// wait=7, wait states = 15, I/O enable for 100+375 ns +void io_wait(char wait); + +unsigned int crc16(unsigned char *wptr, unsigned int count); + +/****************************************************** + void ae_da(int dat1, int dat2) + output dat to U11 DAC of AE88 + Requires P12=CLK, P26=DI, P29=LD/CS as output pins ! + where dat1 for channel A, dat2 for channel B; dat1/2 = 0-4095 +*******************************************************/ +void ae_da(int dat1, int dat2); + +/****************************************************** + void ae86_da(int dat1, int dat2) + output dat to U15 DAC of AE86 + Requires T0=CLK=0x120, T1=DI=0x128, T3=LD/CS=0x138 + where dat1 for channel A, dat2 for channel B; dat1/2 = 0-4095 + Output 0-2.5V at VA=J4.16, VB=J4.18 +*******************************************************/ +void ae86_da(int dat1, int dat2); +void interrupt reset_io_trap(); + +#endif + + + \ No newline at end of file diff --git a/20080212/Demo/WizNET_DEMO_TERN_186/include/i2chip_hw.h b/20080212/Demo/WizNET_DEMO_TERN_186/include/i2chip_hw.h new file mode 100644 index 000000000..2ea32c139 --- /dev/null +++ b/20080212/Demo/WizNET_DEMO_TERN_186/include/i2chip_hw.h @@ -0,0 +1,309 @@ +/* +******************************************************************************** +* TERN, Inc. +* (c) Copyright 2005, http://www.tern.com +* +* - Created to support i2chip module on a variety of TERN hardware platforms. +******************************************************************************** +*/ + +#ifndef _I2CHIP_HW_H_ +#define _I2CHIP_HW_H_ + +#include "types.h" + +#ifdef TERN_SC // SensorCore controller, has mapping identical to the RL +#define TERN_RL +#endif + +#ifdef TERN_RL // R-Engine-L controller, with mapping at MCS0. +#define I2CHIP_MCS_DIRECT +#define I2CHIP_INT4 +#define TERN_RE +#endif // TERN_RL + +#ifdef TERN_5E +#define TERN_586 +#endif + +#ifdef TERN_RD +#define TERN_RE +#endif // TERN_RD + +#ifdef TERN_RE +#define TERN_186 +#endif + +#ifdef TERN_P51 +void p51_window(unsigned int page); +#define I2CHIP_WINDOW +#define I2CHIP_P51 +#ifdef TERN_186 +#define I2CHIP_INT4 +#define TERN_16_BIT +#endif // TERN_186 +#ifdef TERN_586 +#define I2CHIP_INT0 +#define I2CHIP_WINDOW_IO +#endif // TERN_586 +#endif // TERN_P51 + +#ifdef TERN_CEYE +#define TERN_EE // C-Eye configured with onboard i2chip, same as EE +#endif + +#ifdef TERN_EE +#define TERN_186 +#define I2CHIP_MCS_DIRECT +#define I2CHIP_INT4 +#define TERN_16_BIT +#endif // TERN_EE + +#ifdef TERN_MMC +#define I2CHIP_WINDOW +#define I2CHIP_MMC +#ifdef TERN_RD +#define I2CHIP_INT3 +#else +#ifdef TERN_186 +#define I2CHIP_INT4 +#endif // TERN_186 +#endif // TERN_RD +#ifdef TERN_586 +#define I2CHIP_INT0 +#define I2CHIP_WINDOW_IO +#endif // TERN_586 +#endif // TERN_MMC + +#ifdef TERN_586 +#include "586.h" +void interrupt far int0_isr(void); +void interrupt far spu_m_isr(void); +void interrupt far spu_1_isr(void); +void interrupt far spu_2_isr(void); +#define MMCR 0xdf00 +#endif // TERN_586 + +#ifdef TERN_186 +#ifndef TERN_RE +#include "ae.h" +#else +#include "re.h" +#define I2CHIP_SHIFTED_ADDRESS +#endif +#endif + + +#ifndef I2CHIP_MCS_DIRECT +#ifndef I2CHIP_WINDOW +#ifndef I2CHIP_WINDOW_IO +#error You must define the TERN address mapping used to drive the I2CHIP module! +#endif // I2CHIP_WINDOW_IO +#endif // I2CHIP_MMC_WINDOW +#endif // I2CHIP_MCS_DIRECT + +#ifndef I2CHIP_INT0 +#ifndef I2CHIP_INT3 +#ifndef I2CHIP_INT4 +#ifndef I2CHIP_POLL +#error You must specify an interrupt/polling mechanism for the I2CHIP module! +#endif // I2CHIP_POLL +#endif // I2CHIP_INT3 +#endif // I2CHIP_INT4 +#endif // I2CHIP_INT0 + +#ifdef I2CHIP_POLL +#define I2CHIP_POLL_ISR(a) { delay_ms(20); disable(); a(); enable(); } +#define INT_INIT(isr) +#define INT_EOI +#endif // I2CHIP_POLL + +#ifdef I2CHIP_INT4 +#define INT_INIT(isr) int4_init(1, isr) +#define INT_EOI outport(0xff22,0x0010) +#define I2CHIP_POLL_ISR(a) +#endif + +#ifdef I2CHIP_INT3 +#define INT_INIT(isr) int3_init(1, isr) +#define INT_EOI outport(0xff22,0x000f) +#define I2CHIP_POLL_ISR(a) +#endif + +#ifdef I2CHIP_INT0 +#define INT_INIT(isr) int0_init(1, isr) +#define INT_EOI outportb(_MPICOCW2_IO,0x61); // 586 only EOI +#define I2CHIP_POLL_ISR(a) +#endif + + +#ifdef I2CHIP_SHIFTED_ADDRESS +#define SA_OFFSET(a) ((a) << 1) +#else +#define SA_OFFSET(a) a +#endif // I2CHIP_SHIFTED_ADDRESS ... *if* + + +// -------------------- WINDOW-RELATED DEFINES ---------------------- +#ifdef I2CHIP_WINDOW +void i2chip_set_page(u_int addr); +#define I2CHIP_SET_PAGE(p) i2chip_set_page(p) + +u_char far* i2chip_mkptr(u_int addr); +void i2chip_push_window(u_int addr); +void i2chip_pop_window(void); +u_int i2chip_get_window(void); +void i2chip_set_window(u_int window_addr); + +// Set to command window. +// Note that if you're using other MMC chips within your application, you will +// need to call this function regularly, if you've changed the MMC chip/page +// selection via mmc_window(). The driver code otherwise assume that you never +// change away from chip 7, page 0. +#define WINDOW_RESTORE_BASE i2chip_mkptr(0) + +// ----------------------- I2CHIP_WINDOW_IO ---------------------------- +#ifdef I2CHIP_WINDOW_IO + +#ifdef TERN_5E +#define I2CHIP_BASE_SEG 0x2000 // Address offset for W3100A +#else +#define I2CHIP_BASE_SEG 0x1800 // Address offset for W3100A +#endif + +#define COMMAND_BASE_SEG 0x0000 +#define SEND_DATA_BUF 0x4000 // Internal Tx buffer address of W3100A +#define RECV_DATA_BUF 0x6000 // Internal Rx buffer address of W3100A +#define WINDOW_BASE_SEGM COMMAND_BASE_SEG + +#define MK_FP_WINDOW(a, b) i2chip_mkptr(a+SA_OFFSET(b)) +#define MK_FP_SA MK_FP_WINDOW + +u_char io_read_value(u_char far* addr); +void io_write_value(u_char far* addr, u_char value); +#define READ_VALUE(a) io_read_value(a) +#define WRITE_VALUE(a, v) io_write_value(a, v) + +#define WINDOW_PTR_INC(a) \ + if ((FP_OFF(a) & 0xff) == 0xff) \ + a = MK_FP_WINDOW(i2chip_get_window() + 0x100, 0); \ + else \ + a++; + +#endif // I2CHIP_WINDOW_IO + +// -------------------- !NOT! I2CHIP_WINDOW_IO ---------------------------- +#ifndef I2CHIP_WINDOW_IO + +#define READ_VALUE(a) *(a) +#define WRITE_VALUE(a, v) *(a) = v + +#define WINDOW_BASE_SEGM 0x8000 +#define MK_FP_WINDOW(a, b) i2chip_mkptr(a+SA_OFFSET(b)) +#define MK_FP_SA MK_FP_WINDOW + +#ifdef I2CHIP_SHIFTED_ADDRESS +#define COMMAND_BASE_SEG 0x0000 +#define SEND_DATA_BUF 0x8000 +#define RECV_DATA_BUF 0xC000 +#define WINDOW_PTR_INC(a) \ + if ((FP_OFF(a) & 0xff) == 0xfe) \ + a = MK_FP_WINDOW(i2chip_get_window() + 0x100, 0); \ + else \ + a+=2; +#else +#define COMMAND_BASE_SEG 0x0000 +#define SEND_DATA_BUF 0x4000 +#define RECV_DATA_BUF 0x6000 +#define WINDOW_PTR_INC(a) \ + if ((FP_OFF(a) & 0xff) == 0xff) \ + a = MK_FP_WINDOW(i2chip_get_window() + 0x100, 0); \ + else \ + a++; +#endif // I2CHIP_SHIFTED_ADDRESS +#endif // NOT I2CHIP_WINDOW_IO + +#endif // I2CHIP_WINDOW + +// -------------------- I2CHIP_DIRECT ---------------------------- +#ifdef I2CHIP_MCS_DIRECT + +#define READ_VALUE(a) *(a) +#define WRITE_VALUE(a, v) *(a) = v + +#define I2CHIP_BASE_SEG 0x8000 +#define MK_FP_SA(a, b) MK_FP(a, SA_OFFSET(b)) +#define WINDOW_PTR_INC(a) a+=SA_OFFSET(1); +#define WINDOW_RESTORE_BASE +#define MK_FP_WINDOW MK_FP_SA +#define WINDOW_BASE_SEG I2CHIP_BASE_SEG +#define COMMAND_BASE_SEG I2CHIP_BASE_SEG + +#ifdef I2CHIP_SHIFTED_ADDRESS +#define SEND_DATA_BUF 0x8800 // Internal Tx buffer address of W3100A +#define RECV_DATA_BUF 0x8C00 // Internal Rx buffer address of W3100A +#else +#define SEND_DATA_BUF 0x8400 // Internal Tx buffer address of W3100A +#define RECV_DATA_BUF 0x8600 // Internal Rx buffer address of W3100A +#endif // I2CHIP_SHIFTED_ADDRESS + +#endif // I2CHIP_MCS_DIRECT + +/* Internal register set of W3100A */ +#define COMMAND(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, i))) +#define INT_STATUS(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, I2CHIP_C0_ISR + i))) +#define INT_REG ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, I2CHIP_IR))) +#define INTMASK ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, I2CHIP_IMR))) +#define RESETSOCK ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, 0x0A))) + +#define RX_PTR_BASE I2CHIP_C0_RW_PR +#define RX_PTR_SIZE (I2CHIP_C1_RW_PR - I2CHIP_C0_RW_PR) + +#define RX_WR_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, RX_PTR_BASE + RX_PTR_SIZE * i))) +#define RX_RD_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, RX_PTR_BASE + RX_PTR_SIZE * i + 0x04))) +#define RX_ACK_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, TX_PTR_BASE + TX_PTR_SIZE * i + 0x08))) + +#define TX_PTR_BASE I2CHIP_C0_TW_PR +#define TX_PTR_SIZE (I2CHIP_C1_TW_PR - I2CHIP_C0_TW_PR) + +#define TX_WR_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, TX_PTR_BASE + TX_PTR_SIZE * i))) +#define TX_RD_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, TX_PTR_BASE + TX_PTR_SIZE * i + 0x04))) +#define TX_ACK_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, RX_PTR_BASE + RX_PTR_SIZE * i + 0x08))) + +/* Shadow Register Pointer Define */ +/* For windowing purposes, these are definitely outside the first 256-byte Window... +therefore, use the MK_FP_WINDOW macros instead. */ +#define SHADOW_RXWR_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, 0x1E0 + 3*i))) +#define SHADOW_RXRD_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, 0x1E1 + 3*i))) +#define SHADOW_TXACK_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, 0x1E2 + 3*i))) +#define SHADOW_TXWR_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, 0x1F0 + 3*i))) +#define SHADOW_TXRD_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, 0x1F1 + 3*i))) + +#define SOCK_BASE I2CHIP_C0_SSR +#define SOCK_SIZE (I2CHIP_C1_SSR - I2CHIP_C0_SSR) + +#define SOCK_STATUS(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, SOCK_BASE + SOCK_SIZE * i))) +#define OPT_PROTOCOL(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, SOCK_BASE + SOCK_SIZE * i + 0x01))) +#define DST_HA_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, SOCK_BASE + SOCK_SIZE * i + 0x02))) +#define DST_IP_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, SOCK_BASE + SOCK_SIZE * i + 0x08))) +#define DST_PORT_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, SOCK_BASE + SOCK_SIZE * i + 0x0C))) +#define SRC_PORT_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, SOCK_BASE + SOCK_SIZE * i + 0x0E))) +#define IP_PROTOCOL(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, SOCK_BASE + SOCK_SIZE * i + 0x10))) +#define TOS(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG,SOCK_BASE + SOCK_SIZE * i + 0x11))) +#define MSS(i) ((u_int far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, SOCK_BASE + SOCK_SIZE * i + 0x12))) +#define P_WINDOW(i) ((u_int far *)(MK_FP_WINDOW(COMMAND_BASE_SEG,SOCK_BASE + SOCK_SIZE * i + 0x14))) +#define WINDOW(i) ((u_int far*)(MK_FP_WINDOW(COMMAND_BASE_SEG, SOCK_BASE + SOCK_SIZE * i + 0x16))) + +#define GATEWAY_PTR ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG,I2CHIP_GAR))) +#define SUBNET_MASK_PTR ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG,I2CHIP_SMR))) + +#define SRC_HA_PTR ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG,I2CHIP_SHAR))) +#define SRC_IP_PTR ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG,I2CHIP_SIPR))) +#define TIMEOUT_PTR ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG,I2CHIP_IRTR))) + +#define RX_DMEM_SIZE ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG,I2CHIP_RMSR))) +#define TX_DMEM_SIZE ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG,I2CHIP_TMSR))) + +void i2chip_init(void); + +#endif // _irchip_hw_h diff --git a/20080212/Demo/WizNET_DEMO_TERN_186/include/utils/system_common.h b/20080212/Demo/WizNET_DEMO_TERN_186/include/utils/system_common.h new file mode 100644 index 000000000..1a40cf80d --- /dev/null +++ b/20080212/Demo/WizNET_DEMO_TERN_186/include/utils/system_common.h @@ -0,0 +1,12 @@ +#ifndef _SYSTEM_COMMON_H_ +#define _SYSTEM_COMMON_H_ + +typedef unsigned char UCHAR8; +typedef unsigned int UINT16; + +#define RETURN_OK 0 // Non-zero return values are always + // error values. +#define RETURN_ILLEGAL 1 // Some sort of illegal argument. +#define RETURN_MEM 2 // Out of memory space. + +#endif // _SYSTEM_COMMON_H_ \ No newline at end of file diff --git a/20080212/Demo/WizNET_DEMO_TERN_186/main.c b/20080212/Demo/WizNET_DEMO_TERN_186/main.c new file mode 100644 index 000000000..9e0742b27 --- /dev/null +++ b/20080212/Demo/WizNET_DEMO_TERN_186/main.c @@ -0,0 +1,206 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + * Creates all the demo application tasks then starts the scheduler. In + * addition to the standard demo application tasks main() creates the + * HTTPServer task, and a "Check" task. The Check task periodically inspects + * all the other tasks in the system to see if any errors have been reported. + * The error status is then displayed on the served WEB page. + */ + +/* Tern includes. */ +#include +#include + +/* FreeRTOS.org includes. */ +#include +#include + +/* Demo application includes. */ +#include "HTTPTask.h" +#include "integer.h" +#include "PollQ.h" +#include "semtest.h" +#include "dynamic.h" +#include "BlockQ.h" +#include "Death.h" +#include "serial.h" +#include "comtest.h" + +/* How often should the "check" task execute? */ +#define mainCHECK_DELAY ( 3000 / portTICK_RATE_MS ) + +/* Priorities allocated to the various tasks. */ +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainHTTP_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainSUICIDE_TASKS_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) + +/* Used to indicate the error status. A value of 0 means that an error has not +been detected in any task. A non zero value indicates which group of demo +tasks has reported an error. See prvCheckTask() for bit definitions. */ +unsigned portSHORT usCheckStatus = 0; + +/*-----------------------------------------------------------*/ + +/* + * Setup any hardware required by the demo - other than the RTOS tick which + * is configured when the scheduler is started. + */ +static void prvSetupHardware( void ); + +/* + * Periodically inspect all the other tasks, updating usCheckStatus should an + * error be discovered in any task. + */ +static void prvCheckTask( void *pvParameters ); +/*-----------------------------------------------------------*/ + +void main(void) +{ + prvSetupHardware(); + + /* Start the HTTP server task. */ + xTaskCreate( vHTTPTask, "WizNet", configMINIMAL_STACK_SIZE, NULL, mainHTTP_TASK_PRIORITY, NULL ); + + /* Start the demo/test application tasks. See the demo application + section of the FreeRTOS.org WEB site for more information. */ + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartDynamicPriorityTasks(); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vStartComTestTasks( mainCOM_TEST_PRIORITY, serCOM2, ser57600 ); + + /* Start the task that checks the other demo tasks for errors. */ + xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* The suicide tasks must be created last as they monitor the number of + tasks in the system to ensure there are no more or fewer than expected + compared to the number that were executing when the task started. */ + vCreateSuicidalTasks( mainSUICIDE_TASKS_PRIORITY ); + + /* Finally start the scheduler. */ + vTaskStartScheduler(); + + /* Should not get here! */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + ae_init(); +} +/*-----------------------------------------------------------*/ + +static void prvCheckTask( void *pvParameters ) +{ + ( void ) pvParameters; + + /* Check all the demo tasks to ensure that they are all still running, and + that none of them have detected an error. */ + for( ;; ) + { + /* Block until it is time to check again. */ + vTaskDelay( mainCHECK_DELAY ); + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + usCheckStatus |= 0x01; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + usCheckStatus |= 0x02; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + usCheckStatus |= 0x04; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + usCheckStatus |= 0x08; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + usCheckStatus |= 0x10; + } + + if( xIsCreateTaskStillRunning() != pdTRUE ) + { + usCheckStatus |= 0x20; + } + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + usCheckStatus |= 0x40; + } + } +} +/*-----------------------------------------------------------*/ + +/* This is included to prevent link errors - allowing the 'full' version of +the comtest tasks to be used. It can be ignored. */ +void vPrintDisplayMessage( const portCHAR * const * ppcMessageToSend ) +{ + ( void ) ppcMessageToSend; +} + + + + + + + + + + + + diff --git a/20080212/Demo/WizNET_DEMO_TERN_186/serial/serial.c b/20080212/Demo/WizNET_DEMO_TERN_186/serial/serial.c new file mode 100644 index 000000000..d784a93d7 --- /dev/null +++ b/20080212/Demo/WizNET_DEMO_TERN_186/serial/serial.c @@ -0,0 +1,452 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +#include +#include +#include "FreeRTOS.h" +#include "portasm.h" +#include "queue.h" +#include "task.h" +#include "semphr.h" + +#define serMAX_PORTS ( ( unsigned portSHORT ) 2 ) + +#define serPORT_0_INT_REG ( 0xff44 ) +#define serPORT_0_BAUD_REG ( 0xff88 ) +#define serPORT_0_RX_REG ( 0xff86 ) +#define serPORT_0_TX_REG ( 0xff84 ) +#define serPORT_0_STATUS_REG ( 0xff82 ) +#define serPORT_0_CTRL_REG ( 0xff80 ) +#define serPORT_0_IRQ ( 0x14 ) + +#define serPORT_1_INT_REG ( 0xff42 ) +#define serPORT_1_BAUD_REG ( 0xff18 ) +#define serPORT_1_RX_REG ( 0xff16 ) +#define serPORT_1_TX_REG ( 0xff14 ) +#define serPORT_1_STATUS_REG ( 0xff12 ) +#define serPORT_1_CTRL_REG ( 0xff10 ) +#define serPORT_1_IRQ ( 0x11 ) + +#define serTX_EMPTY ( ( unsigned portSHORT ) 0x40 ) +#define serRX_READY ( ( unsigned portSHORT ) 0x80 ) + +#define serRESET_PIC( usEOI_TYPE ) portOUTPUT_WORD( ( unsigned portSHORT ) 0xff22, usEOI_TYPE ) +#define serTX_HOLD_EMPTY_INT ( ( unsigned portSHORT ) 0x100 ) + +#define serENABLE_INTERRUPTS ( ( unsigned portSHORT ) 0x80 ) +#define serMODE ( ( unsigned portSHORT ) 0x01 ) +#define serENABLE_TX_MACHINES ( ( unsigned portSHORT ) 0x40 ) +#define serENABLE_RX_MACHINES ( ( unsigned portSHORT ) 0x20 ) +#define serINTERRUPT_MASK ( ( unsigned portSHORT ) 0x08 ) +#define serCLEAR_ALL_STATUS_BITS ( ( unsigned portSHORT ) 0x00 ) +#define serINTERRUPT_PRIORITY ( ( unsigned portSHORT ) 0x01 ) /*< Just below the scheduler priority. */ + +#define serDONT_BLOCK ( ( portTickType ) 0 ) + +typedef enum +{ + serCOM1 = 0, + serCOM2, + serCOM3, + serCOM4, + serCOM5, + serCOM6, + serCOM7, + serCOM8 +} eCOMPort; + +typedef enum +{ + serNO_PARITY, + serODD_PARITY, + serEVEN_PARITY, + serMARK_PARITY, + serSPACE_PARITY +} eParity; + +typedef enum +{ + serSTOP_1, + serSTOP_2 +} eStopBits; + +typedef enum +{ + serBITS_5, + serBITS_6, + serBITS_7, + serBITS_8 +} eDataBits; + +typedef enum +{ + ser50 = 0, + ser75, + ser110, + ser134, + ser150, + ser200, + ser300, + ser600, + ser1200, + ser1800, + ser2400, + ser4800, + ser9600, + ser19200, + ser38400, + ser57600, + ser115200 +} eBaud; + +typedef struct xCOM_PORT +{ + /* Hardware parameters for this port. */ + portSHORT sTxInterruptOn; + unsigned portSHORT usIntReg; + unsigned portSHORT usBaudReg; + unsigned portSHORT usRxReg; + unsigned portSHORT usTxReg; + unsigned portSHORT usStatusReg; + unsigned portSHORT usCtrlReg; + + unsigned portSHORT usIRQVector; + + /* Queues used for communications with com test task. */ + xQueueHandle xRxedChars; + xQueueHandle xCharsForTx; + + /* This semaphore does nothing useful except test a feature of the + scheduler. */ + xSemaphoreHandle xTestSem; + +} xComPort; + +static xComPort xPorts[ serMAX_PORTS ] = +{ + { pdFALSE, serPORT_0_INT_REG, serPORT_0_BAUD_REG, serPORT_0_RX_REG, serPORT_0_TX_REG, serPORT_0_STATUS_REG, serPORT_0_CTRL_REG, serPORT_0_IRQ, NULL, NULL, NULL }, + { pdFALSE, serPORT_1_INT_REG, serPORT_1_BAUD_REG, serPORT_1_RX_REG, serPORT_1_TX_REG, serPORT_1_STATUS_REG, serPORT_1_CTRL_REG, serPORT_1_IRQ, NULL, NULL, NULL } +}; + +typedef xComPort * xComPortHandle; + +/** + * Lookup the baud rate from the enum. + */ +static unsigned portLONG prvBaud( eBaud eWantedBaud ); + +/* These prototypes are repeated here so we don't have to include the serial header. This allows +the xComPortHandle structure details to be private to this file. */ +xComPortHandle xSerialPortInit( eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits, unsigned portBASE_TYPE uxBufferLength ); +portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, portCHAR *pcRxedChar, portTickType xBlockTime ); +portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, portCHAR cOutChar, portTickType xBlockTime ); +void vSerialClose( xComPortHandle xPort ); +portSHORT sSerialWaitForSemaphore( xComPortHandle xPort ); +/*-----------------------------------------------------------*/ + +static portSHORT xComPortISR( xComPort * const pxPort ); + +#define vInterruptOn( pxPort, usInterrupt ) \ +{ \ +unsigned portSHORT usIn; \ + \ + portENTER_CRITICAL(); \ + { \ + if( pxPort->sTxInterruptOn == pdFALSE ) \ + { \ + usIn = portINPUT_WORD( pxPort->usCtrlReg ); \ + portOUTPUT_WORD( pxPort->usCtrlReg, usIn | usInterrupt ); \ + \ + pxPort->sTxInterruptOn = pdTRUE; \ + } \ + } \ + portEXIT_CRITICAL(); \ +} +/*-----------------------------------------------------------*/ + +#define vInterruptOff( pxPort, usInterrupt ) \ +{ \ + unsigned portSHORT usIn = portINPUT_WORD( pxPort->usCtrlReg ); \ + if( usIn & usInterrupt ) \ + { \ + portOUTPUT_WORD( pxPort->usCtrlReg, usIn & ~usInterrupt); \ + pxPort->sTxInterruptOn = pdFALSE; \ + } \ +} +/*-----------------------------------------------------------*/ + + +/* Define an interrupt handler for each port */ +#define COM_IRQ_WRAPPER(N) \ + static void __interrupt COM_IRQ##N##_WRAPPER( void ) \ + { \ + if( xComPortISR( &( xPorts[##N##] ) ) ) \ + { \ + portEND_SWITCHING_ISR(); \ + } \ + } + + + +COM_IRQ_WRAPPER( 0 ) +COM_IRQ_WRAPPER( 1 ) + +static pxISR xISRs[ serMAX_PORTS ] = +{ + COM_IRQ0_WRAPPER, + COM_IRQ1_WRAPPER +}; + +/*-----------------------------------------------------------*/ + +static unsigned portLONG prvBaud( eBaud eWantedBaud ) +{ + switch( eWantedBaud ) + { + case ser50 : return 50UL; + case ser75 : return 75UL; + case ser110 : return 110UL; + case ser134 : return 134UL; + case ser150 : return 150UL; + case ser200 : return 200UL; + case ser300 : return 300UL; + case ser600 : return 600UL; + case ser1200 : return 1200UL; + case ser1800 : return 1800UL; + case ser2400 : return 2400UL; + case ser4800 : return 4800UL; + case ser19200 : return 19200UL; + case ser38400 : return 38400UL; + case ser57600 : return 57600UL; + case ser115200 : return 115200UL; + default : return 9600UL; + } +} + +/*-----------------------------------------------------------*/ + +xComPortHandle xSerialPortInit( eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits, unsigned portBASE_TYPE uxBufferLength ) +{ +unsigned portSHORT usPort; +xComPortHandle pxPort = NULL; +unsigned portLONG ulBaudDiv; + + /* BAUDDIV = ( Microprocessor Clock / Baud Rate ) / 16 */ + ulBaudDiv = ( configCPU_CLOCK_HZ / prvBaud( eWantedBaud ) ) / 16UL; + + /* Only n, 8, 1 is supported so these parameters are not required for this + port. */ + ( void ) eWantedParity; + ( void ) eWantedDataBits; + ( void ) eWantedStopBits; + + /* Currently only n,8,1 is supported. */ + + usPort = ( unsigned portSHORT ) ePort; + + if( usPort < serMAX_PORTS ) + { + pxPort = &( xPorts[ usPort ] ); + + portENTER_CRITICAL(); + { + unsigned portSHORT usInWord; + + /* Create the queues used by the com test task. */ + pxPort->xRxedChars = xQueueCreate( uxBufferLength, ( unsigned portBASE_TYPE ) sizeof( portCHAR ) ); + pxPort->xCharsForTx = xQueueCreate( uxBufferLength, ( unsigned portBASE_TYPE ) sizeof( portCHAR ) ); + + /* Create the test semaphore. This does nothing useful except test a feature of the scheduler. */ + vSemaphoreCreateBinary( pxPort->xTestSem ); + + /* There is no ISR here already to restore later. */ + setvect( ( portSHORT ) pxPort->usIRQVector, xISRs[ usPort ] ); + + usInWord = portINPUT_WORD( pxPort->usIntReg ); + usInWord &= ~serINTERRUPT_MASK; + usInWord |= serINTERRUPT_PRIORITY; + portOUTPUT_WORD( pxPort->usIntReg, usInWord ); + + portOUTPUT_WORD( pxPort->usBaudReg, ( unsigned portSHORT ) ulBaudDiv ); + portOUTPUT_WORD( pxPort->usCtrlReg, serENABLE_INTERRUPTS | serMODE | serENABLE_TX_MACHINES | serENABLE_RX_MACHINES ); + + portOUTPUT_WORD( pxPort->usStatusReg, serCLEAR_ALL_STATUS_BITS ); + } + portEXIT_CRITICAL(); + } + + return pxPort; +} /*lint !e715 Some parameters are not used as only a subset of the serial port functionality is currently implemented. */ +/*-----------------------------------------------------------*/ + +void vSerialPutString( xComPortHandle pxPort, const portCHAR * const pcString, unsigned portSHORT usStringLength ) +{ +unsigned portSHORT usByte; +portCHAR *pcNextChar; + + pcNextChar = ( portCHAR * ) pcString; + + for( usByte = 0; usByte < usStringLength; usByte++ ) + { + xQueueSend( pxPort->xCharsForTx, pcNextChar, serDONT_BLOCK ); + pcNextChar++; + } + + vInterruptOn( pxPort, serTX_HOLD_EMPTY_INT ); +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, portCHAR *pcRxedChar, portTickType xBlockTime ) +{ + /* Get the next character from the buffer, note that this routine is only + called having checked that the is (at least) one to get */ + if( xQueueReceive( pxPort->xRxedChars, pcRxedChar, xBlockTime ) ) + { + return pdTRUE; + } + else + { + return pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, portCHAR cOutChar, portTickType xBlockTime ) +{ + if( xQueueSend( pxPort->xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) + { + return pdFAIL; + } + + vInterruptOn( pxPort, serTX_HOLD_EMPTY_INT ); + + return pdPASS; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xSerialWaitForSemaphore( xComPortHandle xPort ) +{ +const portTickType xBlockTime = ( portTickType ) 0xffff; + + /* This function does nothing interesting, but test the + semaphore from ISR mechanism. */ + return xSemaphoreTake( xPort->xTestSem, xBlockTime ); +} +/*-----------------------------------------------------------*/ + +void vSerialClose( xComPortHandle xPort ) +{ +unsigned portSHORT usOutput; + + /* Turn off the interrupts. We may also want to delete the queues and/or + re-install the original ISR. */ + + portENTER_CRITICAL(); + { + usOutput = portINPUT_WORD( xPort->usCtrlReg ); + + usOutput &= ~serENABLE_INTERRUPTS; + usOutput &= ~serENABLE_TX_MACHINES; + usOutput &= ~serENABLE_RX_MACHINES; + portOUTPUT_WORD( xPort->usCtrlReg, usOutput ); + + usOutput = portINPUT_WORD( xPort->usIntReg ); + usOutput |= serINTERRUPT_MASK; + portOUTPUT_WORD( xPort->usIntReg, usOutput ); + } + portEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ +unsigned short usStatus; +static portBASE_TYPE xComPortISR( xComPort * const pxPort ) +{ +unsigned portSHORT usStatusRegister; +portCHAR cChar; +portBASE_TYPE xTaskWokenByPost = pdFALSE, xAnotherTaskWokenByPost = pdFALSE, xTaskWokenByTx = pdFALSE; + + /* NOTE: THIS IS NOT AN EFFICIENT ISR AS IT IS DESIGNED SOLELY TO TEST + THE SCHEDULER FUNCTIONALITY. REAL APPLICATIONS SHOULD NOT USE THIS + FUNCTION. */ + + usStatusRegister = portINPUT_WORD( pxPort->usStatusReg ); + + if( usStatusRegister & serRX_READY ) + { + cChar = ( portCHAR ) portINPUT_WORD( pxPort->usRxReg ); + xTaskWokenByPost = xQueueSendFromISR( pxPort->xRxedChars, &cChar, xTaskWokenByPost ); + + /* Also release the semaphore - this does nothing interesting and is just a test. */ + xAnotherTaskWokenByPost = xSemaphoreGiveFromISR( pxPort->xTestSem, xAnotherTaskWokenByPost ); + } + else if( pxPort->sTxInterruptOn && ( usStatusRegister & serTX_EMPTY ) ) + { + if( xQueueReceiveFromISR( pxPort->xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE ) + { + portOUTPUT_WORD( pxPort->usTxReg, ( unsigned portSHORT ) cChar ); + } + else + { + /* Queue empty, nothing to send */ + vInterruptOff( pxPort, serTX_HOLD_EMPTY_INT ); + } + } + + serRESET_PIC( pxPort->usIRQVector ); + + /* If posting to the queue woke a task that was blocked on the queue we may + want to switch to the woken task - depending on its priority relative to + the task interrupted by this ISR. */ + if( xTaskWokenByPost || xAnotherTaskWokenByPost || xTaskWokenByTx) + { + return pdTRUE; + } + else + { + return pdFALSE; + } +} + + + + + diff --git a/20080212/Demo/WizNET_DEMO_TERN_186/tern_code/i2chip_hw.c b/20080212/Demo/WizNET_DEMO_TERN_186/tern_code/i2chip_hw.c new file mode 100644 index 000000000..eb513ef1b --- /dev/null +++ b/20080212/Demo/WizNET_DEMO_TERN_186/tern_code/i2chip_hw.c @@ -0,0 +1,239 @@ +/* +******************************************************************************** +* TERN, Inc. +* (c) Copyright 2005, http://www.tern.com +* +* - Created to support i2chip module on a variety of TERN hardware platforms. +******************************************************************************** +*/ + +#include +#include "i2chip_hw.h" + +#ifdef I2CHIP_MMC +#include "mmc.h" +#endif + +void i2chip_init(void) +{ + +#ifdef TERN_586 +/* + poke(MMCR,_BOOTCSCTL_,peek(MMCR,_BOOTCSCTL_)&0xffc9); // ROM 1 wait + poke(MMCR,_ROMCS2CTL_,peek(MMCR,_ROMCS2CTL_)&0xffc8); // SRAM 0 wait + + pokeb(MMCR, _GPCSRT_, 24); // set the GP CS recovery time, 12 works + pokeb(MMCR, _GPCSPW_, 128); // set the GP CS width, 64 works + pokeb(MMCR, _GPCSOFF_, 16); // set the GP CS offset, 8 works + pokeb(MMCR, _GPRDW_, 80); // set the GP RD pulse width, 50 works + pokeb(MMCR, _GPRDOFF_, 30); // set the GP RD offset, 15 works + pokeb(MMCR, _GPWRW_, 80); // set the GP WR pulse width, 50 + pokeb(MMCR, _GPWROFF_, 30); // set the GP WR offset, 15 +*/ + +#ifdef TERN_5E + pokeb(MMCR, _GPCSDW_, peekb(MMCR, _GPCSDW_)&0xf7); // set /CS3-/CSM Data Width=8 + pokeb(MMCR, _CSPFS_, peekb(MMCR, _CSPFS_)|0x08); // set the GP CS3 PIN Function + poke(MMCR, _PAR15_, 0x2000); // set CS3 I/O region + poke(MMCR, _PAR15_+2, 0x2dff); // set CS3 I/O region, 512 bytes + + pokeb(MMCR, _GPCSDW_, peekb(MMCR, _GPCSDW_)&0x7f); // CS7=J4.3 Data Width=8, /CSI +// pokeb(MMCR, _GPCSDW_, peekb(MMCR, _GPCSDW_)|0x80); // CS7=J4.3 Data Width=16 + pokeb(MMCR, _CSPFS_, peekb(MMCR, _CSPFS_)|0x80); // set the GP CS7 PIN Function + poke(MMCR, _PAR7_, 0x4000); // set CS7 I/O region + poke(MMCR, _PAR7_+2, 0x3dff); // set CS7 I/O region, 512 bytes +#else + // If it's not 5E, then it must be 5P... in which case, we use PCS0 and + // PCS1 as the chip-selects. + pokeb(MMCR, _GPCSDW_, peekb(MMCR, _GPCSDW_)&0xfe); // CS0 Data Width=8 + poke(MMCR, _PIOPFS31_16_, peek(MMCR,_PIOPFS31_16_)|0x0800); // P27=/CS0 + poke(MMCR, _PAR13_, 0x1800); // CS0 I/O region + poke(MMCR, _PAR13_+2, 0x21ff); // CS0 I/O RW, 512 bytes, start 0x1800 +#endif + +a HLPRsetvect(0x47, (void far *) spu_m_isr); + HLPRsetvect(0x4f, (void far *) spu_1_isr); + HLPRsetvect(0x57, (void far *) spu_2_isr); +#endif // 186, or RE + +#ifdef TERN_186 + pio_init(18, 0); // P18=CTS1 for /PCS2 + +#ifdef TERN_16_BIT + outport(0xfff2, 2); // AUXCON, MCS, Bus 16-bit +#endif + +#ifdef I2CHIP_MCS_DIRECT + outport(0xffa0,0xc0bf); // UMCS, 256K ROM, disable AD15-0 + outport(0xfff0,inport(0xfff0)|0x4000 ); // SYSCON, MCS0 0x80000-0xbffff + outport(0xffa8,0xa0bf ); // MPCS, MCS0=P14, 64KB, PCS I/O, + outport(0xffa6,0x81ff); // MMCS, base 0x80000, + outport(0xffa2,0x7fbf); // 512K RAM, + outport(0xffa4,0x007d); // PACS, base 0, + +#else + + outport( 0xffa0,0xc0bf); // UMCS, 256K ROM, 3 wait, disable AD15-0 + outport( 0xfff0,inport(0xfff0)|0x4000 ); // SYSCON, MCS0 0x80000-0xbffff +// outport( 0xffa8,0xa0bc ); // MPCS, MCS0=P14, 64KB, PCS I/O 0 wait +// outport( 0xffa8,0xa0bd ); // MPCS, MCS0=P14, 64KB, PCS I/O 1 wait + outport( 0xffa8,0xa0bf ); // MPCS, MCS0=P14, 64KB, PCS I/O 1 wait +#endif // I2CHIP_MCS_DIRECT + +#ifndef TERN_RE // 80 MHz R- boards can't tolerate zero wait state. + outport( 0xffa6,0x81ff ); // MMCS, base 0x80000 + outport(0xffa2,0x7fbe); // 512K RAM, 0 wait states + outport(0xffa4,0x007d); // PACS, base 0, 0 wait +#endif + pio_init(14,0); // Enable /MCS0 + +#endif // TERN_186 + + +#ifdef I2CHIP_WINDOW +#ifdef I2CHIP_SHIFTED_ADDRESS + pio_init(12, 2); // Configure P12 as A7, an output we'll be using. + pio_wr(12, 0); // Set A7 low, initially. +#endif + WINDOW_RESTORE_BASE; // Equivalent to calling mmc_window(7, 0); +#endif +} + +#ifdef I2CHIP_WINDOW + +void i2chip_set_page(u_int page) +{ + u_int new_page = page; + +#ifdef I2CHIP_SHIFTED_ADDRESS + if (page & 0x01) // ... we're checking the right-most bit in the page. + outport(0xff74, inport(0xff74) | 0x1000 ); // Using P12 as A7... + else + outport(0xff74, inport(0xff74) & 0xefff ); + + new_page = page >> 1; +#endif + +#ifdef I2CHIP_MMC + mmc_window(7, new_page); // See mmc.c +#endif +#ifdef I2CHIP_P51 + p51_window(new_page); +#endif +} + +static u_int s_addr = 0xffff; +u_char far* i2chip_mkptr(u_int addr) +{ + if ((s_addr & 0xff00) == (addr & 0xff00)) // No point... no point... + return MK_FP(WINDOW_BASE_SEGM, addr & 0xff); + + s_addr = addr ; + + // So the argument to this function is... what again? + // I think it should be the highest 16-bits... or, in other words, + // FP_SEG of a huge ptr. + // Ok, and the *return* value should be a UINT value for the new + // segment address to be used, if it's at all needed. TODO + I2CHIP_SET_PAGE(s_addr >> 8); // Portable version +// outportb(0x00, addr>>8); // quicker version + + return MK_FP(WINDOW_BASE_SEGM, addr & 0xff); +} + +void i2chip_set_window(u_int window_addr) +{ + s_addr = window_addr; + I2CHIP_SET_PAGE(s_addr >> 8); +} + +// Still inside #define I2CHIP_WINDOW ... + +u_int i2chip_get_window(void) +{ + return s_addr & 0xff00; +} + +void i2chip_push_window(u_int addr) +{ + I2CHIP_SET_PAGE(addr>>8); +} + +void i2chip_pop_window(void) +{ + I2CHIP_SET_PAGE(s_addr >> 8); +} + +#ifdef I2CHIP_WINDOW_IO +u_char io_read_value(u_char far* addr) +{ + // return value ... we assume the page is already set. So, instead, + // we just go ahead and output valeu. + return inportb(I2CHIP_BASE_SEG + (FP_OFF(addr) & 0xff)); +} + +void io_write_value(u_char far* addr, u_char value) +{ + // Get the last whatever bytes... and write value. + outportb(I2CHIP_BASE_SEG + (FP_OFF(addr) & 0xff), value); +} + +#endif // I2CHIP_WINDOW_IO + + +#ifdef I2CHIP_P51 +void p51_window(unsigned int page) +{ +asm xor ax, ax +asm mov ax, page +#ifdef I2CHIP_WINDOW_IO +asm mov dx, 1040h +asm out dx, al +#else +asm out 040h, al +#endif +// use J1.19=/CS6 +} +#endif // I2CHIP_P51 + +#endif // I2CHIP_WINDOW + +#ifdef TERN_586 +/* +// Function: spu_m_isr +// P22=Master PIC IR7, interrupt vector=0x47, /INTA +*/ +void interrupt far spu_m_isr(void) +{ +disable(); +// Issue the EOI to interrupt controller +outportb(_MPICOCW2_IO,0x67); // Specific EQI for master IR7 +enable(); +} + +/* +// Function: spu_1_isr +// P10=slave1 PIC IR7, Master IR2, interrupt vector=0x4f, /INTC +*/ +void interrupt far spu_1_isr(void) +{ +disable(); +// Issue the EOI to interrupt controller + outportb(_S1PICOCW2_IO,0x67); // Specific EOI for slave 1 IR7 + outportb(_MPICOCW2_IO,0x62); // Specific EQI for master IR2 +enable(); +} + +/* +// Function: spu_2_isr +// P20=Slave2 PIC IR7, Master IR5, interrupt vector=0x57, GPIRQ7=PIO16 GP timer1 +*/ +void interrupt far spu_2_isr(void) +{ +disable(); +// Issue the EOI to interrupt controller + outportb(_S2PICOCW2_IO,0x67); // Specific EOI for slave 1 IR7 + outportb(_MPICOCW2_IO,0x65); // Specific EQI for master IR5 +enable(); +} +#endif diff --git a/20080212/Demo/WizNET_DEMO_TERN_186/tern_code/socket.c b/20080212/Demo/WizNET_DEMO_TERN_186/tern_code/socket.c new file mode 100644 index 000000000..4749e16d8 --- /dev/null +++ b/20080212/Demo/WizNET_DEMO_TERN_186/tern_code/socket.c @@ -0,0 +1,1869 @@ +/* +******************************************************************************** +* TERN, Inc. +* (c) Copyright 2005, http://www.tern.com +* +* MODIFIED BY RICHARD BARRY TO ADD SEMAPHORE FOR COMMUNICATION BETWEEN THE +* WIZnet ISR AND THE HTTP TASK. +* +* - Derived based on development version provided by Wiznet. +* +* Filename : socket.h +* Programmer(s): +* Created : 2002/06/20 +* Modified : +* 2002/09/27 : - Renaming +* INT_STATUS --> INT_REG +* STATUS(i) --> INT_STATUS(i) +* C_STATUS(i) --> SOCK_STATUS(i) +* 2003/11/06 : Ported for use with TERN controller. Note all byte access is at even addresses +* 2005/10/8 : Modified constants for easier initialization. +* +* Description : Header file of W3100A for TERN embedded controller +******************************************************************************** +*/ +/* +############################################################################### +File Include Section +############################################################################### +*/ +#include "i2chip_hw.h" +#include "socket.h" +#include "types.h" +#include +#include + +#include +#include +#include + + +/* +############################################################################### +Local Variable Declaration Section +############################################################################### +*/ +u_char I_STATUS[4]; // Store Interrupt Status according to channels +u_int Local_Port; // Designate Local Port +union un_l2cval SEQ_NUM; // Set initial sequence number + +u_long SMASK[MAX_SOCK_NUM]; // Variable to store MASK of Tx in each channel, + // on setting dynamic memory size. +u_long RMASK[MAX_SOCK_NUM]; // Variable to store MASK of Rx in each channel, + // on setting dynamic memory size. +int SSIZE[MAX_SOCK_NUM]; // Maximun Tx memory size by each channel +int RSIZE[MAX_SOCK_NUM]; // Maximun Rx memory size by each channel + +u_int SBUFBASEADDRESS[MAX_SOCK_NUM]; // Maximun Tx memory base address by each channel +u_int RBUFBASEADDRESS[MAX_SOCK_NUM]; // Maximun Rx memory base address by each channel + +/* +############################################################################### +Function Implementation Section +############################################################################### +*/ + +/* +******************************************************************************** +* Interrupt handling function of the W3100A +* +* Description : +* Stores the status information that each function waits for in the global variable I_STATUS +* for transfer. I_STATUS stores the interrupt status value for each channel. +* Arguments : None +* Returns : None +* Note : Internal Function +******************************************************************************** +*/ + +portBASE_TYPE prvProcessISR( void ) +{ +unsigned char status; +extern xSemaphoreHandle xTCPSemaphore; +portBASE_TYPE xSwitchRequired = pdFALSE; + +#ifdef I2CHIP_WINDOW +u_int current_window = i2chip_get_window(); +#endif + +status = READ_VALUE(INT_REG); + + +if (status) + { + xSwitchRequired = pdTRUE; + // channel 0 interrupt(sysinit, sockinit, established, closed, timeout, send_ok, recv_ok) + if (status & 0x01) + { + I_STATUS[0] = READ_VALUE(INT_STATUS(0)); + +// if (I_STATUS[0] & SESTABLISHED) +// ISR_ESTABLISHED(0); +// if (I_STATUS[0] & SCLOSED) +// ISR_CLOSED(0); + + WRITE_VALUE(INT_REG, 0x01); + } + + // channel 1 interrupt(sysinit, sockinit, established, closed, timeout, send_ok, recv_ok) + if (status & 0x02) + { + I_STATUS[1] = READ_VALUE(INT_STATUS(1)); + +// if (I_STATUS[1] & SESTABLISHED) +// ISR_ESTABLISHED(1); +// if (I_STATUS[1] & SCLOSED) +// ISR_CLOSED(1); + + WRITE_VALUE(INT_REG, 0x02); + } + + // channel 2 interrupt(sysinit, sockinit, established, closed, timeout, send_ok, recv_ok) + if (status & 0x04) + { + I_STATUS[2] = READ_VALUE(INT_STATUS(2)); + +// if (I_STATUS[2] & SESTABLISHED) +// ISR_ESTABLISHED(2); +// if (I_STATUS[2] & SCLOSED) +// ISR_CLOSED(2); + + WRITE_VALUE(INT_REG, 0x04); + } + + // channel 3 interrupt(sysinit, sockinit, established, closed, timeout, send_ok, recv_ok) + if (status & 0x08) + { + I_STATUS[3] = READ_VALUE(INT_STATUS(3)); + +// if (I_STATUS[3] & SESTABLISHED) ISR_ESTABLISHED(3); +// if (I_STATUS[3] & SCLOSED) ISR_CLOSED(3); + + WRITE_VALUE(INT_REG, 0x08); + } + + // channel 0 receive interrupt + if (status & 0x10) + { +// ISR_RX(0); + WRITE_VALUE(INT_REG, 0x10); + } + + // channel 1 receive interrupt + if (status & 0x20) + { +// ISR_RX(1); + WRITE_VALUE(INT_REG, 0x20); + } + + // channel 2 receive interrupt + if (status & 0x40) + { +// ISR_RX(2); + WRITE_VALUE(INT_REG, 0x40); + } + + // channel 3 receive interrupt + if (status & 0x80) + { +// ISR_RX(3); + WRITE_VALUE(INT_REG, 0x80); + } + status = READ_VALUE(INT_REG); + } + +WRITE_VALUE(INT_REG, 0xFF); + +#ifdef I2CHIP_WINDOW +i2chip_set_window(current_window); +#endif + + if( xSwitchRequired == pdTRUE ) + { + xSwitchRequired = xSemaphoreGiveFromISR( xTCPSemaphore, pdFALSE ); + } + + return xSwitchRequired; +} + +void far interrupt in4_isr_i2chip(void) +{ + if( prvProcessISR() == pdTRUE ) + { + portEND_SWITCHING_ISR(); + } + + INT_EOI; +} + +/* +**************************************************************************************************** +* Established connection interrupt handling function. +* +* Description : +* Called upon connection establishment, and may be inserted in user code if needed by +* the programmer. +* Arguments : None +* Returns : None +* Note : Internal Function +**************************************************************************************************** +*/ +/* +void ISR_ESTABLISHED(SOCKET s) +{ +// TO ADD YOUR CODE +} +*/ + +/* +**************************************************************************************************** +* Closed connection interrupt handling function +* +* Description : +* Called upon connection closure, and may be inserted in user code if needed by the programmer. +* Arguments : None +* Returns : None +* Note : Internal Function +**************************************************************************************************** +*/ +/* +void ISR_CLOSED(SOCKET s) +{ +// TO ADD YOUR CODE +} +*/ + +/* +**************************************************************************************************** +* Received data interrupt handling function +* +* Description : +* Called upon receiving data, and may be inserted in user code if needed by the programmer. +* Arguments : None +* Returns : None +* Note : Internal Function +**************************************************************************************************** +*/ +/* +void ISR_RX(SOCKET s) +{ +// TO ADD YOUR CODE +} +*/ + +/* +**************************************************************************************************** +* W3100A Initialization Function +* +* Description: Reset of W3100A S/W and Registeration of i386 interrupt +* Arguments : None. +* Returns : None. +* Note : +**************************************************************************************************** +*/ +void initW3100A(void) +{ + +// Install interrupt handler for i2Chip +INT_INIT(in4_isr_i2chip); + + +Local_Port = 1000; // This default value will be set if you didn't designate it when you + // create a socket. If you don't designate port number and create a + // socket continuously, the port number will be assigned with + // incremented by one to Local_Port +SEQ_NUM.lVal = 4294967293ul; // Sets the initial SEQ# to be used for TCP communication. + // (It should be ramdom value) +WRITE_VALUE(COMMAND(0), CSW_RESET); // Software RESET +} + +/* +**************************************************************************************************** +* W3100A initialization function +* +* Description : +* Sets the Tx, Rx memory size by each channel, source MAC, source IP, gateway, and subnet mask +* to be used by the W3100A to the designated values. +* May be called when reflecting modified network information or Tx, Rx memory size on the W3100A +* Include Ping Request for ARP update (In case that a device embedding W3100A is directly +* connected to Router) +* Arguments : sbufsize - Tx memory size (00 - 1KByte, 01- 2KBtye, 10 - 4KByte, 11 - 8KByte) +* bit 1-0 : Tx memory size of channel #0 +* bit 3-2 : Tx memory size of channel #1 +* bit 5-4 : Tx memory size of channel #2 +* bit 7-6 : Tx memory size of channel #3 +* rbufsize - Rx memory size (00 - 1KByte, 01- 2KBtye, 10 - 4KByte, 11 - 8KByte) +* bit 1-0 : Rx memory size of channel #0 +* bit 3-2 : Rx memory size of channel #1 +* bit 5-4 : Rx memory size of channel #2 +* bit 7-6 : Rx memory size of channel #3 +* Returns : None +* Note : API Function +* Maximum memory size for Tx, Rx in W3100A is 8KBytes, +* In the range of 8KBytes, the memory size could be allocated dynamically by +* each channel +* Be attentive to sum of memory size shouldn't exceed 8Kbytes +* and to data transmission and receiption from non-allocated channel may cause +* some problems. +* If 8KBytes memory already is assigned to centain channel, other 3 channels +* couldn't be used, for there's no available memory. +* If two 4KBytes memory are assigned to two each channels, other 2 channels couldn't +* be used, for there's no available memory. +* (Example of memory assignment) +* sbufsize => 00000011, rbufsize => 00000011 : +* Assign 8KBytes for Tx and Rx to channel #0, Cannot use channel #1,#2,#3 +* sbufsize => 00001010, rbufsize => 00001010 : +* Assign 4KBytes for Tx and Rx to each channel #0,#1 respectively. Cannot use +* channel #2,#3 +* sbufsize => 01010101, rbufsize => 01010101 : +* Assign 2KBytes for Tx and Rx to each all channels respectively. +* sbufsize => 00010110, rbufsize => 01010101 : +* Assign 4KBytes for Tx, 2KBytes for Rx to channel #0 +* s 2KBytes for Tx, 2KBytes for Rx to channel #1 +* 2KBytes for Tx, 2KBytes for Rx to channel #2 +* 2KBytes is available exclusively for Rx in channel #3. There's no memory for Tx. +**************************************************************************************************** +*/ +void sysinit(u_char sbufsize, u_char rbufsize) +{ +char i; +int ssum,rsum; + +ssum = 0; +rsum = 0; + +// Set Tx memory size for each channel +WRITE_VALUE(TX_DMEM_SIZE, sbufsize); + +// Set Rx memory size for each channel +WRITE_VALUE(RX_DMEM_SIZE, rbufsize); + +// Set Base Address of Tx memory for channel #0 +SBUFBASEADDRESS[0] = 0; + +// Set Base Address of Rx memory for channel #0 +RBUFBASEADDRESS[0] = 0; + +// Set maximum memory size for Tx and Rx, mask, base address of memory by each channel +for(i = 0 ; i < MAX_SOCK_NUM; i++) + { + SSIZE[i] = 0; + RSIZE[i] = 0; + if(ssum < 8192) + { + switch((sbufsize >> i*2) & 0x03) // Set maximum Tx memory size + { + case 0: + SSIZE[i] = 1024; + SMASK[i] = 0x000003FF; + break; + + case 1: + SSIZE[i] = 2048; + SMASK[i] = 0x000007FF; + break; + + case 2: + SSIZE[i] = 4096; + SMASK[i] = 0x00000FFF; + break; + + case 3: + SSIZE[i] = 8192; + SMASK[i] = 0x00001FFF; + break; + } + } + if(rsum < 8192) + { + switch((rbufsize >> i*2) & 0x03) // Set maximum Rx memory size + { + case 0: + RSIZE[i] = 1024; + RMASK[i] = 0x000003FF; + break; + + case 1: + RSIZE[i] = 2048; + RMASK[i] = 0x000007FF; + break; + + case 2: + RSIZE[i] = 4096; + RMASK[i] = 0x00000FFF; + break; + + case 3: + RSIZE[i] = 8192; + RMASK[i] = 0x00001FFF; + break; + } + } + ssum += SSIZE[i]; + rsum += RSIZE[i]; + + // Set base address of Tx and Rx memory for channel #1,#2,#3 + if(i != 0) + { + SBUFBASEADDRESS[i] = ssum - SSIZE[i]; + RBUFBASEADDRESS[i] = rsum - RSIZE[i]; + } + } + + WRITE_VALUE(COMMAND(0), CSYS_INIT); + +while(!(I_STATUS[0] & SSYS_INIT_OK)) + I2CHIP_POLL_ISR(in4_isr_i2chip); + +#ifdef __PING__ + { + u_char xdata pingbuf[8]; + setIPprotocol(0, IPPROTO_ICMP); + socket(0, SOCK_IPL_RAW, 3000,0); // Create a socket for ARP update + + pingbuf[0] = 8; // ICMP TYPE + pingbuf[1] = 0; // ICMP CODE + pingbuf[2] = 0xf7; // CHECKSUM (already calculated) + pingbuf[3] = 0xfd; + pingbuf[4] = 0; // ID + pingbuf[5] = 1; + pingbuf[6] = 0; // SEQ # + pingbuf[7] = 1; + pingbuf[8] = 0; // Data 1 Byte + + sendto(0, pingbuf, 9, GATEWAY_PTR,3000); // Ping Request + close(0); + printf("Route MAC Update Success"); + } +#endif +} + +/* +**************************************************************************************************** +* Function to set subnet mask +* +* Description: +* Arguments : addr--> Pointer that has the value to be set +* Returns : None. +* Note : +**************************************************************************************************** +*/ +void setsubmask(u_char * addr) +{ +u_char i; +u_char far* sm_ptr = SUBNET_MASK_PTR; // We can only convert to 'regular' + // pointer if we're confident arithmetic + // won't take us out of current window. + +for (i = 0; i < 4; i++) + { + WRITE_VALUE(sm_ptr + SA_OFFSET(i), addr[i]); + } +} + +/* +**************************************************************************************************** +* Function to set gateway IP +* +* Description: +* Arguments : addr--> Pointer that has Gateway IP to be set +* Returns : None. +* Note : +**************************************************************************************************** +*/ +void setgateway(u_char * addr) +{ +u_char i; +u_char far* gw_ptr = GATEWAY_PTR; // We can only convert to 'regular' + // pointer if we're confident arithmetic + // won't take us out of current window. +for (i = 0; i < 4; i++) + { + WRITE_VALUE(gw_ptr + SA_OFFSET(i), addr[i]); + } +} + +/* +**************************************************************************************************** +* Function to set W3100A IP +* +* Description: +* Arguments : addr--> Pointer that has Source IP to be set +* Returns : None. +* Note : +**************************************************************************************************** +*/ +void setIP(u_char * addr) +{ +u_char i; +u_char far* src_ptr = SRC_IP_PTR; // We can only convert to 'regular' + // pointer if we're confident arithmetic + // won't take us out of current window. + +for (i = 0; i < 4; i++) + { + WRITE_VALUE(src_ptr + SA_OFFSET(i), addr[i]); + } +} + +// DEBUG +void getIP(u_char* addr) +{ +u_char i; +u_char far* src_ptr = SRC_IP_PTR; // We can only convert to 'regular' + // pointer if we're confident arithmetic + // won't take us out of current window. + +for (i = 0; i < 4; i++) + addr[i] = READ_VALUE(src_ptr + SA_OFFSET(i)); +} + + +/* +**************************************************************************************************** +* Function to set MAC +* +* Description: +* Arguments : addr--> Pointer that has MAC to be set +* Returns : None. +* Note : +**************************************************************************************************** +*/ +void setMACAddr(u_char * addr) +{ +u_char i; +u_char far* ha_ptr = SRC_HA_PTR; // We can only convert to 'regular' + // pointer if we're confident arithmetic + // won't take us out of current window. + +for (i = 0; i < 6; i++) + { + WRITE_VALUE(ha_ptr + SA_OFFSET(i), addr[i]); + } +} + +/* +**************************************************************************************************** +* Function to set TCP timeout +* +* Description: The function that used to adjust time to resend TCP +* Arguments : val --> Pointer that has the value to be set +* Upper 2 byte:Initial timeout value +* Last 1 byte:The count to retry till timeout +* Returns : None. +* Note : +**************************************************************************************************** +*/ +void settimeout(u_char * val) +{ +u_char i; +u_char far* tout_ptr = TIMEOUT_PTR; // We can only convert to 'regular' + // pointer if we're confident arithmetic + // won't take us out of current window. + +for (i = 0; i < 3; i++) + { + WRITE_VALUE(tout_ptr + SA_OFFSET(i), val[i]); + } +} + +/* +**************************************************************************************************** +* Function to set interrupt mask. +* +* Description: +* Arguments : mask--> Mask value to be set ('1'-> interrupt ) +* Returns : None. +* Note : +**************************************************************************************************** +*/ +void setINTMask(u_char mask) +{ +WRITE_VALUE(INTMASK, mask); +} + +/* +**************************************************************************************************** +* Function to set enable in sending and receiving of broadcast data +* +* Description: Enable to process of broadcating data in UDP or IP RAW mode. +* Arguments : s --> Channel No. to be set +* Returns : None. +* Note : +**************************************************************************************************** +*/ +void setbroadcast(SOCKET s) +{ +u_char val = READ_VALUE(OPT_PROTOCOL(s)); +WRITE_VALUE(OPT_PROTOCOL(s), val | SOCKOPT_BROADCAST); +} + +/* +**************************************************************************************************** +* Function to set process protocol in IP RAW mode. +* +* Description: +* Arguments : s--> Channel No. to be set +* tos-->Protocol Value to be set +* Returns : None. +* Note : +**************************************************************************************************** +*/ +void setTOS(SOCKET s, u_char tos) +{ +WRITE_VALUE(TOS(s), tos); +} + +/* +**************************************************************************************************** +* Upper layer protocol setup function in IP RAW Mode +* +* Description : Upper layer protocol setup function in protocol field of IP header when +* developing upper layer protocol like ICMP, IGMP, EGP etc. by using IP Protocol +* Arguments : s - Channel number +* ipprotocol - Upper layer protocol setting value of IP Protocol +* (Possible to use designated IPPROTO_ in header file) +* Returns : None +* Note : API Function +* This function should be called before calling socket() that is, before +* socket initialization. +**************************************************************************************************** +*/ +void setIPprotocol(SOCKET s, u_char ipprotocol) +{ +WRITE_VALUE(IP_PROTOCOL(s), ipprotocol); +} + +/* +**************************************************************************************************** +* Initialization function to appropriate channel +* +* Description : Initialize designated channel and wait until W3100 has done. +* Arguments : s - channel number +* protocol - designate protocol for channel +* SOCK_STREAM(0x01) -> TCP. +* SOCK_DGRAM(0x02) -> UDP. +* SOCK_IPL_RAW(0x03) -> IP LAYER RAW. +* SOCK_MACL_RAW(0x04) -> MAC LAYER RAW. +* port - designate source port for appropriate channel +* flag - designate option to be used in appropriate. +* SOCKOPT_BROADCAST(0x80) -> Send/receive broadcast message in UDP +* SOCKOPT_NDTIMEOUT(0x40) -> Use register value which designated TIMEOUT +* value +* SOCKOPT_NDACK(0x20) -> When not using no delayed ack +* SOCKOPT_SWS(0x10) -> When not using silly window syndrome +* Returns : When succeeded : Channel number, failed :-1 +* Note : API Function +**************************************************************************************************** +*/ +char socket(SOCKET s, u_char protocol, u_int port, u_char flag) +{ +u_char k; + +//Designate socket protocol and option +WRITE_VALUE(OPT_PROTOCOL(s), protocol | flag); + +// setup designated port number +if (port != 0) + { + k = (u_char)((port & 0xff00) >> 8); + WRITE_VALUE(SRC_PORT_PTR(s), k); + k = (u_char)(port & 0x00ff); + WRITE_VALUE(SRC_PORT_PTR(s) + SA_OFFSET(1), k); + } +else + { + // Designate random port number which is managed by local when you didn't designate source port + Local_Port++; + + WRITE_VALUE(SRC_PORT_PTR(s), (u_char)((Local_Port & 0xff00) >> 8)); + WRITE_VALUE(SRC_PORT_PTR(s) + SA_OFFSET(1), (u_char)(Local_Port & 0x00ff)); + } + +// SOCK_INIT +I_STATUS[s] = 0; +WRITE_VALUE(COMMAND(s), CSOCK_INIT); + +// Waiting Interrupt to CSOCK_INIT +while (I_STATUS[s] == 0) + I2CHIP_POLL_ISR(in4_isr_i2chip); + +if (!(I_STATUS[s] & SSOCK_INIT_OK)) + return(-1); + +initseqnum(s); // Use initial seq# with random number + +return(s); +} + +/* +**************************************************************************************************** +* Connection establishing function to designated peer. +* +* Description : This function establish a connection to the peer by designated channel, +* and wait until the connection is established successfully. (TCP client mode) +* Arguments : s - channel number +* addr - destination IP Address +* port - destination Port Number +* Returns : when succeeded : 1, failed : -1 +* Note : API Function +**************************************************************************************************** +*/ +char connect(SOCKET s, u_char far * addr, u_int port) +{ + +if (port != 0) + { //designate destination port + WRITE_VALUE(DST_PORT_PTR(s), (u_char)((port & 0xff00) >> 8)); + WRITE_VALUE(DST_PORT_PTR(s) + SA_OFFSET(1), (u_char)(port & 0x00ff)); + } +else + return(-1); + + WRITE_VALUE(DST_IP_PTR(s), addr[0]); //designate destination IP address + WRITE_VALUE(DST_IP_PTR(s) + SA_OFFSET(1), addr[1]); + WRITE_VALUE(DST_IP_PTR(s) + SA_OFFSET(2), addr[2]); + WRITE_VALUE(DST_IP_PTR(s) + SA_OFFSET(3), addr[3]); + +I_STATUS[s] = 0; + + WRITE_VALUE(COMMAND(s), CCONNECT); // CONNECT + I2CHIP_POLL_ISR(in4_isr_i2chip); + +// Wait until connection is established successfully +while (I_STATUS[s] == 0) + { + // When failed, appropriate channel will be closed and return an error + if (select(s, SEL_CONTROL) == SOCK_CLOSED) + return -1; + } + +if (!(I_STATUS[s] & SESTABLISHED)) + return(-1); + +return(1); +} + +/* +**************************************************************************************************** +* Connection establishing function to designated peer. (Non-blocking Mode) +* +* Description : This function establish a connection to the peer by designated channel. +* +* Arguments : s - channel number +* addr - destination IP Address +* port - destination Port Number +* Returns : when succeeded : 1, failed : -1 +* Note : API Function +**************************************************************************************************** +*/ +char NBconnect(SOCKET s, u_char far * addr, u_int port) +{ + +if (port != 0) + { //designate destination port + WRITE_VALUE(DST_PORT_PTR(s), (u_char) ((port & 0xff00) >> 8) ); + WRITE_VALUE(DST_PORT_PTR(s) + SA_OFFSET(1), (u_char)(port & 0x00ff)); + } +else + return(-1); + + WRITE_VALUE(DST_IP_PTR(s), addr[0]); //designate destination IP address + WRITE_VALUE(DST_IP_PTR(s) + SA_OFFSET(1), addr[1]); + WRITE_VALUE(DST_IP_PTR(s) + SA_OFFSET(2), addr[2]); + WRITE_VALUE(DST_IP_PTR(s) + SA_OFFSET(3), addr[3]); + +I_STATUS[s] = 0; + +WRITE_VALUE(COMMAND(s), CCONNECT); // CONNECT +return(1); +} + +/* +**************************************************************************************************** +* Waits for connection request from a peer (Blocking Mode) +* +* Description : Wait for connection request from a peer through designated channel (TCP Server mode) +* Arguments : s - channel number +* addr - IP Address of the peer when a connection is established +* port - Port number of the peer when a connection is established +* Returns : When succeeded : 1, failed : -1 +* Note : API Function +**************************************************************************************************** +*/ +/* +char listen(SOCKET s, u_char far * addr, u_int far * port) +{ +u_int i; + +I_STATUS[s] = 0; + +// LISTEN +COMMAND(s) = CLISTEN; + +// Wait until connection is established +while (I_STATUS[s] == 0) + { + // When failed to connect, the designated channel will be closed and return an error. + if (select(s, SEL_CONTROL) == SOCK_CLOSED) + return -1; + } + +// Receive IP address and port number of the peer connected +if (I_STATUS[s] & SESTABLISHED) + { + i = *DST_PORT_PTR(s); + *port = (u_int)((i & 0xff00) >> 8); + i = *(DST_PORT_PTR(s) + 2); + i = (u_int)(i & 0x00ff); + *port += (i << 8); + + addr[0] = *DST_IP_PTR(s); + addr[1] = *(DST_IP_PTR(s) + 2); + addr[2] = *(DST_IP_PTR(s) + 4); + addr[3] = *(DST_IP_PTR(s) + 6); + } +else + return(-1); + +return(1); +} +*/ + +/* +**************************************************************************************************** +* Waits for connection request from a peer (Non-blocking Mode) +* +* Description : Wait for connection request from a peer through designated channel (TCP Server mode) +* Arguments : s - channel number +* Returns : None +* Note : API Function +**************************************************************************************************** +*/ +char NBlisten(SOCKET s) +{ +I_STATUS[s] = 0; + +// LISTEN +WRITE_VALUE(COMMAND(s), CLISTEN); + +return(1); +} + +/* +**************************************************************************************************** +* Create random value for initial Seq# when establishing TCP connection +* +* Description : In this function, you can add some source codes to create random number for +* initial Seq#. In real, TCP initial SEQ# should be random value. +* (Currently, we're using static value in EVB/DK.) +* Arguments : s - channel number +* Returns : None +* Note : API Function +**************************************************************************************************** +*/ +void initseqnum(SOCKET s) +{ +// Designate initial seq# +// If you have random number generation function, assign random number instead of SEQ_NUM.lVal++. +SEQ_NUM.lVal++; + +//randomize(); +//SEQ_NUM.lVal = rand(); + +WRITE_VALUE(TX_WR_PTR(s), SEQ_NUM.cVal[0]); +WRITE_VALUE(TX_WR_PTR(s) + SA_OFFSET(1), SEQ_NUM.cVal[1]); +WRITE_VALUE(TX_WR_PTR(s) + SA_OFFSET(2), SEQ_NUM.cVal[2]); +WRITE_VALUE(TX_WR_PTR(s) + SA_OFFSET(3), SEQ_NUM.cVal[3]); +delay0(2); + +WRITE_VALUE(TX_RD_PTR(s), SEQ_NUM.cVal[0]); +WRITE_VALUE(TX_RD_PTR(s) + SA_OFFSET(1), SEQ_NUM.cVal[1]); +WRITE_VALUE(TX_RD_PTR(s) + SA_OFFSET(2), SEQ_NUM.cVal[2]); +WRITE_VALUE(TX_RD_PTR(s) + SA_OFFSET(3), SEQ_NUM.cVal[3]); +delay0(2); + +WRITE_VALUE(TX_ACK_PTR(s), SEQ_NUM.cVal[0]); +WRITE_VALUE(TX_ACK_PTR(s) + SA_OFFSET(1), SEQ_NUM.cVal[1]); +WRITE_VALUE(TX_ACK_PTR(s) + SA_OFFSET(2), SEQ_NUM.cVal[2]); +WRITE_VALUE(TX_ACK_PTR(s) + SA_OFFSET(3), SEQ_NUM.cVal[3]); +delay0(2); +} + +/* +**************************************************************************************************** +* Function for sending TCP data. +* +* Description : Function for sending TCP data and Composed of the send() and send_in() functions. +* The send() function is an application I/F function. +* It continues to call the send_in() function to complete the sending of the data up to the +* size of the data to be sent when the application is called. +* The send_in() function receives the return value (the size of the data sent), calculates +* the size of the data to be sent, and calls the send_in() function again if there is any +* data left to be sent. +* Arguments : s - channel number +* buf - Pointer pointing data to send +* len - data size to send +* Returns : Succeed: sent data size, Failed: -1; +* Note : API Function +**************************************************************************************************** +*/ +int send(SOCKET s, u_char far * buf, u_int len) +{ +int ptr, size; +u_char huge* huge_buf = (u_char huge*)buf; +u_char far* local_buf = (u_char far*)huge_buf; + +if (len <= 0) + return (0); +else + { + ptr = 0; + do + { + size = send_in(s, local_buf + ptr, len); + if (size == -1) + return -1; + len = len - size; + ptr += size; + } while ( len > 0); + } +return ptr; +} + +/* +**************************************************************************************************** +* Internal function for sending TCP data. +* +* Description : Called by the send() function for TCP transmission. +* It first calculates the free transmit buffer size +* and compares it with the size of the data to be transmitted to determine the transmission size. +* After calculating the data size, it copies data from TX_WR_PTR. +* It waits if there is a previous send command in process. +* When the send command is cleared, it updates the TX_WR_PTR up to the size to be transmitted + and performs the send command. +* Arguments : s - channel number +* buf - Pointer pointing data to send +* len - data size to send +* Returns : Succeeded: sent data size, Failed: -1 +* Note : Internal Function +**************************************************************************************************** +*/ +int send_in(SOCKET s, u_char far * buf, u_int len) +{ +u_char k; +u_int size; +union un_l2cval wr_ptr, ack_ptr; +unsigned int offset; + +S_START: +disable(); // CT: Shadow register access should not conflict with ISR. +k = READ_VALUE(SHADOW_TXWR_PTR(s)); +WINDOW_RESTORE_BASE; // Needed whenever we touch a shadow ptr; different window. +delay0(2); +wr_ptr.cVal[3] = READ_VALUE(TX_WR_PTR(s)); +wr_ptr.cVal[2] = READ_VALUE(TX_WR_PTR(s) + SA_OFFSET(1)); +wr_ptr.cVal[1] = READ_VALUE(TX_WR_PTR(s) + SA_OFFSET(2)); +wr_ptr.cVal[0] = READ_VALUE(TX_WR_PTR(s) + SA_OFFSET(3)); + +k = READ_VALUE(SHADOW_TXACK_PTR(s)); +WINDOW_RESTORE_BASE; // Needed whenever we touch a shadow ptr; different window. +delay0(2); +ack_ptr.cVal[3] = READ_VALUE(TX_ACK_PTR(s)); +ack_ptr.cVal[2] = READ_VALUE(TX_ACK_PTR(s) + SA_OFFSET(1)); +ack_ptr.cVal[1] = READ_VALUE(TX_ACK_PTR(s) + SA_OFFSET(2)); +ack_ptr.cVal[0] = READ_VALUE(TX_ACK_PTR(s) + SA_OFFSET(3)); +enable(); + +// Suppress compiler errors that k is not used +k = k; + +// Calculate send free buffer size +if (wr_ptr.lVal >= ack_ptr.lVal) + size = (u_int)(SSIZE[s] - (wr_ptr.lVal - ack_ptr.lVal)); +else + size = (u_int)(SSIZE[s] - (0 - ack_ptr.lVal + wr_ptr.lVal)); + +// Recalulate after some delay because of error in pointer calculation +if (size > SSIZE[s]) + { + if (select(s, SEL_CONTROL) != SOCK_ESTABLISHED) + return -1; + delay_ms(1); + goto S_START; + } + +// Wait when previous sending has not finished yet and there's no free buffer +if (size == 0) + { + if (select(s, SEL_CONTROL) != SOCK_ESTABLISHED) + return -1; + + delay_ms(1); + goto S_START; + } +else if (size < len) + { + len = size; + } + +// Calculate pointer to data copy +offset = (UINT)(wr_ptr.lVal & SMASK[s]); + +// copy data +write_data(s, buf, offset, len); + +while (READ_VALUE(COMMAND(s)) & CSEND) + { + // Confirm previous send command + if (select(s, SEL_CONTROL) != SOCK_ESTABLISHED) + return -1; + } + +// update tx_wr_ptr +wr_ptr.lVal = wr_ptr.lVal + len; +WRITE_VALUE(TX_WR_PTR(s), wr_ptr.cVal[3]); +WRITE_VALUE(TX_WR_PTR(s) + SA_OFFSET(1), wr_ptr.cVal[2]); +WRITE_VALUE(TX_WR_PTR(s) + SA_OFFSET(2), wr_ptr.cVal[1]); +WRITE_VALUE(TX_WR_PTR(s) + SA_OFFSET(3), wr_ptr.cVal[0]); + +delay0(1); + +// SEND +WRITE_VALUE(COMMAND(s), CSEND); + +return(len); +} + +/* +**************************************************************************************************** +* TCP data receiving function. +* +* Description : This function is to clear out any received TCP data. +* Arguments : s - channel number +* Returns : None +* Note : API Fcuntion +**************************************************************************************************** +*/ +void recv_clear(SOCKET s) +{ +u_char k; +u_int size; +union un_l2cval wr_ptr, rd_ptr; + +disable(); +k = READ_VALUE(SHADOW_RXWR_PTR(s)); +WINDOW_RESTORE_BASE; // Needed whenever we touch a shadow ptr; different window. +delay0(2); +wr_ptr.cVal[3] = READ_VALUE(RX_WR_PTR(s)); +wr_ptr.cVal[2] = READ_VALUE(RX_WR_PTR(s) + SA_OFFSET(1)); +wr_ptr.cVal[1] = READ_VALUE(RX_WR_PTR(s) + SA_OFFSET(2)); +wr_ptr.cVal[0] = READ_VALUE(RX_WR_PTR(s) + SA_OFFSET(3)); + +k = READ_VALUE(SHADOW_RXRD_PTR(s)); +WINDOW_RESTORE_BASE; // Needed whenever we touch a shadow ptr; different window. +delay0(2); +rd_ptr.cVal[3] = READ_VALUE(RX_RD_PTR(s)); +rd_ptr.cVal[2] = READ_VALUE(RX_RD_PTR(s) + SA_OFFSET(1)); +rd_ptr.cVal[1] = READ_VALUE(RX_RD_PTR(s) + SA_OFFSET(2)); +rd_ptr.cVal[0] = READ_VALUE(RX_RD_PTR(s) + SA_OFFSET(3)); +enable(); + +// Suppress compiler errors that k is not used +k = k; + +// calculate received data size +if (wr_ptr.lVal >= rd_ptr.lVal) + size = (u_int)(wr_ptr.lVal - rd_ptr.lVal); +else + size = (u_int)(0 - rd_ptr.lVal + wr_ptr.lVal); + +// Update rx_rd_ptr +rd_ptr.lVal += size; +WRITE_VALUE(RX_RD_PTR(s), rd_ptr.cVal[3]); +WRITE_VALUE(RX_RD_PTR(s) + SA_OFFSET(1), rd_ptr.cVal[2]); +WRITE_VALUE(RX_RD_PTR(s) + SA_OFFSET(2), rd_ptr.cVal[1]); +WRITE_VALUE(RX_RD_PTR(s) + SA_OFFSET(3), rd_ptr.cVal[0]); + +// RECV + WRITE_VALUE(COMMAND(s), CRECV); +} + +/* +**************************************************************************************************** +* TCP data receiving function. +* +* Description : This function is for receiving TCP data. +* The recv() function is an application I/F function. It will read up to len chars if there are + enough characters in the buffer, otherwise will onl read the number of characters availiable +* Arguments : s - channel number +* buf - Pointer where the data to be received is copied +* len - Size of the data to be received +* Returns : Succeeded: received data size, Failed: -1 +* Note : API Fcuntion +**************************************************************************************************** +*/ +int recv(SOCKET s, u_char far * buf, u_int len) +{ +u_char k; +u_int size; +union un_l2cval wr_ptr, rd_ptr; +unsigned int offset; + +// If out length is 0, then we do not need to do anything +if (len <= 0) + return (0); + +disable(); +k = READ_VALUE(SHADOW_RXWR_PTR(s)); +WINDOW_RESTORE_BASE; // Needed whenever we touch a shadow ptr; different window. +delay0(2); +wr_ptr.cVal[3] = READ_VALUE(RX_WR_PTR(s)); +wr_ptr.cVal[2] = READ_VALUE(RX_WR_PTR(s) + SA_OFFSET(1)); +wr_ptr.cVal[1] = READ_VALUE(RX_WR_PTR(s) + SA_OFFSET(2)); +wr_ptr.cVal[0] = READ_VALUE(RX_WR_PTR(s) + SA_OFFSET(3)); + +k = READ_VALUE(SHADOW_RXRD_PTR(s)); +WINDOW_RESTORE_BASE; // Needed whenever we touch a shadow ptr; different window. +delay0(2); +rd_ptr.cVal[3] = READ_VALUE(RX_RD_PTR(s)); +rd_ptr.cVal[2] = READ_VALUE(RX_RD_PTR(s) + SA_OFFSET(1)); +rd_ptr.cVal[1] = READ_VALUE(RX_RD_PTR(s) + SA_OFFSET(2)); +rd_ptr.cVal[0] = READ_VALUE(RX_RD_PTR(s) + SA_OFFSET(3)); +enable(); + +// Suppress compiler errors that k is not used +k = k; + +// calculate IIM7010A received data size +if (wr_ptr.lVal == rd_ptr.lVal) + return(0); +else if (wr_ptr.lVal >= rd_ptr.lVal) + size = (u_int)(wr_ptr.lVal - rd_ptr.lVal); +else + size = (u_int)(0 - rd_ptr.lVal + wr_ptr.lVal); + +// Make sure we do not try to read more characters than what is availiable in the IIM7010 buffer +if (size < len) + len = size; + +// Calculate pointer to be copied received data +offset = ((UINT)(rd_ptr.lVal & RMASK[s])); + +// Copy received data +size = read_data(s, offset, buf, len); + +// Update rx_rd_ptr +rd_ptr.lVal += size; +WRITE_VALUE(RX_RD_PTR(s), rd_ptr.cVal[3]); +WRITE_VALUE(RX_RD_PTR(s) + SA_OFFSET(1), rd_ptr.cVal[2]); +WRITE_VALUE(RX_RD_PTR(s) + SA_OFFSET(2), rd_ptr.cVal[1]); +WRITE_VALUE(RX_RD_PTR(s) + SA_OFFSET(3), rd_ptr.cVal[0]); + +// RECV + WRITE_VALUE(COMMAND(s), CRECV); +return(size); +} + + +/* +**************************************************************************************************** +* UDP data sending function. +* +* Description : Composed of the sendto()and sendto_in() functions. +* The send() function is an application I/F function. +* It continues to call the send_in() function to complete the sending of the data up to the +* size of the data to be sent +* when the application is called.Unlike TCP transmission, it designates the destination address +* and the port. +* Arguments : s - channel port +* buf - Pointer pointing data to send +* len - data size to send +* addr - destination IP address to send data +* port - destination port number to send data +* Returns : Sent data size +* Note : API Function +**************************************************************************************************** +*/ +u_int sendto(SOCKET s, u_char far * buf, u_int len, u_char * addr, u_int port) +{ +//char val; +u_int ptr, size; + +// Wait until previous send commnad has completed. +while(READ_VALUE(COMMAND(s)) & CSEND) + { + if(select(s, SEL_CONTROL) == SOCK_CLOSED) + return -1; // Error. + } + +// Designate destination port number. +if (port != 0) + { + WRITE_VALUE(DST_PORT_PTR(s), (u_char)((port & 0xff00) >> 8)); + WRITE_VALUE(DST_PORT_PTR(s) + SA_OFFSET(1), (u_char)(port & 0x00ff)); + } + +// Designate destination IP address +WRITE_VALUE(DST_IP_PTR(s), addr[0]); +WRITE_VALUE(DST_IP_PTR(s) + SA_OFFSET(1), addr[1]); +WRITE_VALUE(DST_IP_PTR(s) + SA_OFFSET(2), addr[2]); +WRITE_VALUE(DST_IP_PTR(s) + SA_OFFSET(3), addr[3]); + +if (len <= 0) + return (0); +else + { + ptr = 0; + do + { + size = sendto_in(s, buf + ptr, len); + len = len - size; + ptr += size; + } while ( len > 0); + } +return ptr; +} + +/* +**************************************************************************************************** +* UDP data sending function. +* +* Description : An internal function that is the same as the send_in() function of the TCP. +* Arguments : s - Channel number +* buf - Pointer indicating the data to send +* len - data size to send +* Returns : Sent data size +* Note : Internal Function +**************************************************************************************************** +*/ +u_int sendto_in(SOCKET s, u_char far * buf, u_int len) +{ +u_char k; +u_int size; +union un_l2cval wr_ptr, rd_ptr; +unsigned int offset; + +S2_START: +disable(); +k = READ_VALUE(SHADOW_TXWR_PTR(s)); +WINDOW_RESTORE_BASE; // Needed whenever we touch a shadow ptr; different window. +delay0(2); +wr_ptr.cVal[3] = READ_VALUE(TX_WR_PTR(s)); +wr_ptr.cVal[2] = READ_VALUE(TX_WR_PTR(s) + SA_OFFSET(1)); +wr_ptr.cVal[1] = READ_VALUE(TX_WR_PTR(s) + SA_OFFSET(2)); +wr_ptr.cVal[0] = READ_VALUE(TX_WR_PTR(s) + SA_OFFSET(3)); + +k = READ_VALUE(SHADOW_TXRD_PTR(s)); +WINDOW_RESTORE_BASE; // Needed whenever we touch a shadow ptr; different window. +delay0(2); +rd_ptr.cVal[3] = READ_VALUE(TX_RD_PTR(s)); +rd_ptr.cVal[2] = READ_VALUE(TX_RD_PTR(s) + SA_OFFSET(1)); +rd_ptr.cVal[1] = READ_VALUE(TX_RD_PTR(s) + SA_OFFSET(2)); +rd_ptr.cVal[0] = READ_VALUE(TX_RD_PTR(s) + SA_OFFSET(3)); +enable(); + +// Suppress compiler errors that k is not used +k = k; + +// Calculate free buffer size to send +if (wr_ptr.lVal >= rd_ptr.lVal) + size = (u_int)(SSIZE[s] - (wr_ptr.lVal - rd_ptr.lVal)); +else + size = (u_int)(SSIZE[s] - (0 - rd_ptr.lVal + wr_ptr.lVal)); + +// Recalulate after some delay because of error in pointer caluation +if (size > SSIZE[s]) + { + delay_ms(1); + goto S2_START; + } + +// Wait when previous sending has not finished yet and there's no free buffer +if (size == 0) + { + delay_ms(1); + goto S2_START; + + } +else if (size < len) + { + len = size; + } + +// Calculate pointer to copy data pointer +offset =(UINT)(wr_ptr.lVal & SMASK[s]); + +// copy data +write_data(s, buf, offset, len); + +// Confirm previous send command +while (READ_VALUE(COMMAND(s)) & CSEND) + { + if(select(s, SEL_CONTROL)==SOCK_CLOSED) + return -1; // Error + } + +// update tx_wr_ptr +wr_ptr.lVal = wr_ptr.lVal + len; +WRITE_VALUE(TX_WR_PTR(s), wr_ptr.cVal[3]); +WRITE_VALUE(TX_WR_PTR(s) + SA_OFFSET(1), wr_ptr.cVal[2]); +WRITE_VALUE(TX_WR_PTR(s) + SA_OFFSET(2), wr_ptr.cVal[1]); +WRITE_VALUE(TX_WR_PTR(s) + SA_OFFSET(3), wr_ptr.cVal[0]); + +delay0(1); + +// SEND +WRITE_VALUE(COMMAND(s), CSEND); + +return(len); +} + +/* +**************************************************************************************************** +* UDP data receiving function. +* +* Description : Function for receiving UDP and IP layer RAW mode data, and handling the data header. +* Arguments : s - channel number +* buf - Pointer where the data to be received is copied +* len - Size of the data to be received +* addr - Peer IP address for receiving +* port - Peer port number for receiving +* Returns : Received data size +* Note : API Function +**************************************************************************************************** +*/ +u_int recvfrom(SOCKET s, u_char far *buf, u_int len, u_char *addr, u_int *port) +{ +struct _UDPHeader // When receiving UDP data, header added by W3100A + { + union + { + struct + { + u_int size; + u_char addr[4]; + u_int port; + } header; + u_char stream[8]; + } u; + } UDPHeader; + +u_int ret; +union un_l2cval wr_ptr, rd_ptr; +u_long size; +u_char k; +unsigned int offset; + +if(select(s,SEL_CONTROL)==SOCK_CLOSED) + return -1; + +disable(); +k = READ_VALUE(SHADOW_RXWR_PTR(s)); +WINDOW_RESTORE_BASE; // Needed whenever we touch a shadow ptr; different window. +delay0(2); +wr_ptr.cVal[3] = READ_VALUE(RX_WR_PTR(s)); +wr_ptr.cVal[2] = READ_VALUE(RX_WR_PTR(s) + SA_OFFSET(1)); +wr_ptr.cVal[1] = READ_VALUE(RX_WR_PTR(s) + SA_OFFSET(2)); +wr_ptr.cVal[0] = READ_VALUE(RX_WR_PTR(s) + SA_OFFSET(3)); + +k = READ_VALUE(SHADOW_RXRD_PTR(s)); +WINDOW_RESTORE_BASE; // Needed whenever we touch a shadow ptr; different window. +delay0(2); +rd_ptr.cVal[3] = READ_VALUE(RX_RD_PTR(s)); +rd_ptr.cVal[2] = READ_VALUE(RX_RD_PTR(s) + SA_OFFSET(1)); +rd_ptr.cVal[1] = READ_VALUE(RX_RD_PTR(s) + SA_OFFSET(2)); +rd_ptr.cVal[0] = READ_VALUE(RX_RD_PTR(s) + SA_OFFSET(3)); +enable(); + +// Suppress compiler errors that k is not used +k = k; + +// Calculate received data size +if (len <= 0) + return (0); +else if (wr_ptr.lVal >= rd_ptr.lVal) + size = wr_ptr.lVal - rd_ptr.lVal; +else + size = 0 - rd_ptr.lVal + wr_ptr.lVal; + +if (size == 0) + return 0; + + // Calulate received data pointer +offset = ((UINT)(rd_ptr.lVal & RMASK[s])); + +// When UDP data +if (( READ_VALUE(OPT_PROTOCOL(s)) & 0x07) == SOCK_DGRAM) + { + // Copy W3100A UDP header + read_data(s, offset, UDPHeader.u.stream, 8); + + // Read UDP Packet size + size = UDPHeader.u.stream[0]; + size = (size << 8) + UDPHeader.u.stream[1]; + + // Read IP address of the peer + addr[0] = UDPHeader.u.header.addr[0]; + addr[1] = UDPHeader.u.header.addr[1]; + addr[2] = UDPHeader.u.header.addr[2]; + addr[3] = UDPHeader.u.header.addr[3]; + + // Read Port number of the peer + *port = UDPHeader.u.stream[6]; + *port = (*port << 8) + UDPHeader.u.stream[7]; + + // Increase read pointer by 8, because already read as UDP header size + rd_ptr.lVal += 8; + + // Calculate UDP data copy pointer + offset = ((UINT)(rd_ptr.lVal & RMASK[s])); + + // Calculate data size of current UDP Packet from UDP header + size = size - 8; + + // Copy one UDP data packet to user-specific buffer + ret = read_data(s, offset, buf, (u_int)size); + + // Increase read pointer by UDP packet data size + rd_ptr.lVal += ret; + } +else if ((READ_VALUE(OPT_PROTOCOL(s)) & 0x07) == SOCK_IPL_RAW) // When IP layer RAW mode data + { + // Copy W3100A IP Raw header + read_data(s, offset, UDPHeader.u.stream, 6); + + // Read IP layer RAW Packet size + size = UDPHeader.u.stream[0]; + size = (size << 8) + UDPHeader.u.stream[1]; + + // Read IP address of the peer + addr[0] = UDPHeader.u.header.addr[0]; + addr[1] = UDPHeader.u.header.addr[1]; + addr[2] = UDPHeader.u.header.addr[2]; + addr[3] = UDPHeader.u.header.addr[3]; + + // Increase read pointer by 6, because already read as IP RAW header size + rd_ptr.lVal += 6; + + // Calculate IP layer raw mode data pointer + offset = ((UINT)(rd_ptr.lVal & RMASK[s])); + + // Copy one IP Raw data packet to user-specific buffer + ret = read_data(s, offset, buf, (u_int)size); + rd_ptr.lVal = rd_ptr.lVal + (ret - 4); + } + + // Update rx_rd_ptr + WRITE_VALUE(RX_RD_PTR(s), rd_ptr.cVal[3]); + WRITE_VALUE(RX_RD_PTR(s) + SA_OFFSET(1), rd_ptr.cVal[2]); + WRITE_VALUE(RX_RD_PTR(s) + SA_OFFSET(2), rd_ptr.cVal[1]); + WRITE_VALUE(RX_RD_PTR(s) + SA_OFFSET(3), rd_ptr.cVal[0]); + + // RECV + WRITE_VALUE(COMMAND(s), CRECV); + +// Real received size return +return(ret); +} + +/* +**************************************************************************************************** +* Channel closing function. +* +* Description : Function for closing the connection of the designated channel. +* Arguments : s - channel number +* Returns : None +* Note : API Function +**************************************************************************************************** +*/ +void close(SOCKET s) +{ +u_int len; +short sAttempts = 0; + +I_STATUS[s] = 0; + +if (select(s, SEL_CONTROL) == SOCK_CLOSED) + return; // Already closed + +// When closing, if there's data which have not processed, Insert some source codes to handle this +// Or before application call close(), handle those data first and call close() later. + +len = select(s, SEL_SEND); +if (len == SSIZE[s]) + { + // CLOSE + WRITE_VALUE(COMMAND(s), CCLOSE); + // TODO: The 'SCLOSED' status value is only set briefly as part of the close, + // and will otherwise quickly return to normal. That means your code might + // become 'stuck' at this point even if the packet has closed normally. + // Rather than a while() call, it might be preferred to time out on this + // close check and return to the application after some time. + while(!(I_STATUS[s] & SCLOSED)) + { + sAttempts++; + if( sAttempts > 10 ) + { + break; + } + I2CHIP_POLL_ISR(in4_isr_i2chip); + } + } +} + +u_char tx_empty(SOCKET s) +{ + return (select(s, SEL_SEND) == SSIZE[s]); +} + +/* +**************************************************************************************************** +* Channel closing function. +* +* Description : Function for closing the connection of the designated channel. +* Arguments : s - channel number +* Returns : None +* Note : API Function +**************************************************************************************************** +*/ +char reset_sock(SOCKET s) +{ +u_char c; + +c = 1 << s; + +// RESET +WRITE_VALUE(RESETSOCK, c); +return (1); +} + +/* +**************************************************************************************************** +* Function handling the channel socket information. +* +* Description : Return socket information of designated channel +* Arguments : s - channel number +* func - SEL_CONTROL(0x00) -> return socket status +* SEL_SEND(0x01) -> return free transmit buffer size +* SEL_RECV(0x02) -> return received data size +* Returns : socket status or free transmit buffer size or received data size +* Note : API Function +**************************************************************************************************** +*/ +u_int select(SOCKET s, u_char func) +{ +u_int val; +union un_l2cval rd_ptr, wr_ptr, ack_ptr; +u_char k; + +switch (func) + { + // socket status information + case SEL_CONTROL : + val = READ_VALUE(SOCK_STATUS(s)); + break; + + // Calculate send free buffer size + case SEL_SEND : + disable(); + k = READ_VALUE(SHADOW_TXWR_PTR(s)); + WINDOW_RESTORE_BASE; // Needed whenever we touch a shadow ptr; different window. + delay0(2); + wr_ptr.cVal[3] = READ_VALUE(TX_WR_PTR(s)); + wr_ptr.cVal[2] = READ_VALUE(TX_WR_PTR(s) + SA_OFFSET(1)); + wr_ptr.cVal[1] = READ_VALUE(TX_WR_PTR(s) + SA_OFFSET(2)); + wr_ptr.cVal[0] = READ_VALUE(TX_WR_PTR(s) + SA_OFFSET(3)); + + if (( READ_VALUE(OPT_PROTOCOL(s)) & 0x07) == SOCK_STREAM) // TCP + { + k = READ_VALUE(SHADOW_TXACK_PTR(s)); + WINDOW_RESTORE_BASE; // Needed whenever we touch a shadow ptr; different window. + delay0(2); + ack_ptr.cVal[3] = READ_VALUE(TX_ACK_PTR(s)); + ack_ptr.cVal[2] = READ_VALUE(TX_ACK_PTR(s) + SA_OFFSET(1)); + ack_ptr.cVal[1] = READ_VALUE(TX_ACK_PTR(s) + SA_OFFSET(2)); + ack_ptr.cVal[0] = READ_VALUE(TX_ACK_PTR(s) + SA_OFFSET(3)); + enable(); + + if (wr_ptr.lVal >= ack_ptr.lVal) + val = (u_int)(SSIZE[s] - (wr_ptr.lVal - ack_ptr.lVal)); + else + val = (u_int)(SSIZE[s] - (0 - ack_ptr.lVal + wr_ptr.lVal)); + } + else // UDP, IP RAW ... (except TCP) + { + k = READ_VALUE(SHADOW_TXRD_PTR(s)); + WINDOW_RESTORE_BASE; // Needed whenever we touch a shadow ptr; different window. + delay0(2); + rd_ptr.cVal[3] = READ_VALUE(TX_RD_PTR(s)); + rd_ptr.cVal[2] = READ_VALUE(TX_RD_PTR(s) + SA_OFFSET(1)); + rd_ptr.cVal[1] = READ_VALUE(TX_RD_PTR(s) + SA_OFFSET(2)); + rd_ptr.cVal[0] = READ_VALUE(TX_RD_PTR(s) + SA_OFFSET(3)); + enable(); + + if (wr_ptr.lVal >= rd_ptr.lVal) + val = (u_int)(SSIZE[s] - (wr_ptr.lVal - rd_ptr.lVal)); + else + val = (u_int)(SSIZE[s] - (0 - rd_ptr.lVal + wr_ptr.lVal)); + } + break; + + // Calculate received data size + case SEL_RECV : + disable(); + k = READ_VALUE(SHADOW_RXWR_PTR(s)); + WINDOW_RESTORE_BASE; // Needed whenever we touch a shadow ptr; different window. + delay0(2); + wr_ptr.cVal[3] = READ_VALUE(RX_WR_PTR(s)); + wr_ptr.cVal[2] = READ_VALUE(RX_WR_PTR(s) + SA_OFFSET(1)); + wr_ptr.cVal[1] = READ_VALUE(RX_WR_PTR(s) + SA_OFFSET(2)); + wr_ptr.cVal[0] = READ_VALUE(RX_WR_PTR(s) + SA_OFFSET(3)); + + k = READ_VALUE(SHADOW_RXRD_PTR(s)); + WINDOW_RESTORE_BASE; // Needed whenever we touch a shadow ptr; different window. + delay0(2); + rd_ptr.cVal[3] = READ_VALUE(RX_RD_PTR(s)); + rd_ptr.cVal[2] = READ_VALUE(RX_RD_PTR(s) + SA_OFFSET(1)); + rd_ptr.cVal[1] = READ_VALUE(RX_RD_PTR(s) + SA_OFFSET(2)); + rd_ptr.cVal[0] = READ_VALUE(RX_RD_PTR(s) + SA_OFFSET(3)); + enable(); + + if (wr_ptr.lVal == rd_ptr.lVal) + val = 0; + else if (wr_ptr.lVal > rd_ptr.lVal) + val = (u_int)(wr_ptr.lVal - rd_ptr.lVal); + else + val = (u_int)(0 - rd_ptr.lVal + wr_ptr.lVal); + break; + + default : + val = -1; + break; + } +// Suppress compiler errors that k is not used +k = k; +return(val); +} + +// +// unsigned char dma_read_i2chip (unsigned int i2_segm, unsigned int i2_offs, +// unsigned int cnt, unsigned int des_segm, unsigned int des_offs); +// Using DMA0 to read data from i2chip buffer into destination SRAM. +// where: +// unsigned int cnt = number of sectors, 512-byte per sector +// unsigned int des_segm = segment of destination SRAM data memory +// unsigned int des_offs = offset of destination SRAM data memory +// unsigned int i2_segm = segment of i2chip buffer mapped in memory +// unsigned int i2_offs = offset of i2chip buffer mapped in memory +// return DMA counter value +// +unsigned int dma_read_i2chip(u_char far* i2_src, u_char far* des, u_int cnt) +{ + u_int des_segm, des_offs; + u_int i2_segm, i2_offs; + u_long temp; + + temp = ((long)FP_SEG(des) << 4) + ((long)FP_OFF(des)); + des_segm = (u_int)(temp >> 16); + des_offs = (u_int)(temp & 0xffff); + + temp = ((long)FP_SEG(i2_src) << 4) + ((long)FP_OFF(i2_src)); + i2_segm = (u_int)(temp >> 16); + i2_offs = (u_int)(temp & 0xffff); + + outport(0xffc6, des_segm); /* D0DSTH destination SRAM segment */ + outport(0xffc4, des_offs); /* D0DSTL destination SRAM offset */ + outport(0xffc2, i2_segm); /* D0SRCH=SP0RD */ + outport(0xffc0, i2_offs); /* D0SRCL=SP0RD */ + outport(0xffc8, cnt); // D0TC counter + outport(0xfff8,0x0504); // PLLCON, 0203=10M,050f=40M, 051f=80MHz +// DMA0 mem-mem, 16-bit, unsync, Start moving data line below + outport(0xffca, 0xb60e); /* D0CON 1011 0110 0000 1111 */ +// outport(0xffca, 0xb42e); // 1011 0100 0010 1110 + while( inport(0xffc8) ); /* D0TC counter=0, DMA complete */ + outport(0xfff8,0x051f); // PLLCON, 0203=10M,050f=40M, 051f=80MHz +return( inport(0xffc8) ); // counter +} + +// +// unsigned int dma_write_i2chip (unsigned int src_segm, unsigned int src_offs, +// unsigned int cnt, unsigned int i2_segm, unsigned int i2_offs); +// Using DMA0 to write data from memory into i2chip. +// where: +// unsigned int cnt = number of 16-bit DMA transfers +// unsigned int src_segm = segment of the source SRAM data memory +// unsigned int src_offs = offset of the source SRAM data memory +// unsigned int i2_segm = segment of i2chip buffer mapped in memory +// unsigned int i2_offs = offset of i2chip buffer mapped in memory +// return DMA counter value +// +unsigned int dma_write_i2chip(u_char far* src, u_char far* i2_dest, u_int cnt) +{ + u_int src_segm, src_offs; + u_int i2_segm, i2_offs; + u_long temp; + + temp = (FP_SEG(src) << 4) + (FP_OFF(src)); + src_segm = (u_int)(temp >> 4); + src_offs = (u_int)(temp & 0xffff); + + temp = (FP_SEG(i2_dest) << 4) + (FP_OFF(i2_dest)); + i2_segm = (u_int)(temp >> 4); + i2_offs = (u_int)(temp & 0xffff); + + outport(0xffc8, cnt); // D0TC counter + outport(0xffc6, i2_segm); // D0DSTH=i2chip buffer segment + outport(0xffc4, i2_offs); // D0DSTL=i2chip buffer offset + outport(0xffc2, src_segm); /* D0SRCH=SP0RD */ + outport(0xffc0, src_offs); /* D0SRCL=SP0RD */ +// outport(0xfff8,0x050f); // PLLCON, 0203=10M,050f=40M, 051f=80MHz +// DMA0 mem-mem, 16-bit, unsync, Start moving data line below + outport(0xffca, 0xb60f); /* D0CON 1011 0110 0000 1111 */ + while( inport(0xffc8) ); /* D0TC counter=0, DMA complete */ +// outport(0xfff8,0x051f); // PLLCON, 0203=10M,050f=40M, 051f=80MHz + +return( inport(0xffc8) ); // counter +} + +/* +**************************************************************************************************** +* Copies the receive buffer data of the W3100A to the system buffer. +* +* Description : Copies the receive buffer data of the W3100A to the system buffer. +* It is called from the recv()or recvfrom() function. +* Arguments : s - channel number +* src - receive buffer pointer of W3100A +* dst - system buffer pointer +* len - data size to copy +* Returns : copied data size +* Note : Internal Function +**************************************************************************************************** +*/ +u_int read_data(SOCKET s, u_int offset, u_char far * dst, u_int len) +{ + u_int i, size, size1; + u_char far* src = (u_char far*)(MK_FP_WINDOW(RECV_DATA_BUF, + RBUFBASEADDRESS[s] + offset)); +// src = (u_char far*)(MK_FP_WINDOW(RECV_DATA_BUF, +// 0)); + + if (len == 0) + { + WINDOW_RESTORE_BASE; // Needed whenever we do a call to MK_FP_WINDOW. + return 0; + } + + if ((offset + len) > RSIZE[s]) + { + size = (u_int)(RSIZE[s] - offset); + + if (size > TERN_RDMA_THRES) + { + dma_read_i2chip(src, dst, size); + } + else + { + for (i = 0; i < size; i++) + { + *dst++ = READ_VALUE(src); + WINDOW_PTR_INC(src); + + } + } + + size1 = len - size; + src = (u_char far *)(MK_FP_WINDOW(RECV_DATA_BUF, (RBUFBASEADDRESS[s]))); + + if (size1 > TERN_RDMA_THRES) + { + dma_read_i2chip(src, dst, size); + } + else + { + for (i = 0; i < size1; i++) + { + *dst++ = READ_VALUE(src); + WINDOW_PTR_INC(src); + } + } + } + else + { + if (len > TERN_RDMA_THRES) + { + dma_read_i2chip(src, dst, size); + } + else + { + for (i = 0; i < len; i++) + { + *dst++ = READ_VALUE(src); + WINDOW_PTR_INC(src); + } + } + } + WINDOW_RESTORE_BASE; // Needed whenever we do a call to MK_FP_WINDOW. + return len; +} + + +/* +**************************************************************************************************** +* Copies the system buffer data to the transmit buffer of the W3100A. +* +* Description : Copies the system buffer data to the transmit buffer of the W3100A. +* It is called from the send_in()or sendto_in() function. +* Arguments : s - channel number +* src - system buffer pointer +* dst - send buffer pointer of W3100A +* len - data size to copy +* Returns : copied data size +* Note : Internal Function +**************************************************************************************************** +*/ +u_int write_data(SOCKET s, u_char far * src, u_int offset, u_int len) +{ + u_int i, size, size1; + u_char far* dst = (u_char far*)MK_FP_WINDOW(SEND_DATA_BUF, + SBUFBASEADDRESS[s] + offset); + + if (len == 0) + { + WINDOW_RESTORE_BASE; // Needed whenever we do a call to MK_FP_WINDOW. + return 0; + } + + if ((offset + len) > SSIZE[s]) + { + size = (u_int)(SSIZE[s] - offset); + + for (i = 0; i < size; i++) + { + WRITE_VALUE(dst, *src++); + WINDOW_PTR_INC(dst); + } + + size1 = len - size; + dst = (u_char far *)(MK_FP_WINDOW(SEND_DATA_BUF, (SBUFBASEADDRESS[s]))); + + for (i = 0; i < size1; i++) + { + WRITE_VALUE(dst, *src++); + WINDOW_PTR_INC(dst); + } + } + else + { + for (i = 0; i < len; i++) + { + WRITE_VALUE(dst, *src++); + WINDOW_PTR_INC(dst); + } + } + WINDOW_RESTORE_BASE; // Needed whenever we do a call to MK_FP_WINDOW. + return len; +} + + + diff --git a/20080212/Demo/dsPIC_MPLAB/FreeRTOSConfig.h b/20080212/Demo/dsPIC_MPLAB/FreeRTOSConfig.h new file mode 100644 index 000000000..a4e1c7fd6 --- /dev/null +++ b/20080212/Demo/dsPIC_MPLAB/FreeRTOSConfig.h @@ -0,0 +1,89 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 0 +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 25000000 ) /* Fosc / 2 */ +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 ) +#define configMINIMAL_STACK_SIZE ( 105 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) 5120 ) +#define configMAX_TASK_NAME_LEN ( 4 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 1 +#define configIDLE_SHOULD_YIELD 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 1 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + +#define configKERNEL_INTERRUPT_PRIORITY 0x01 + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/dsPIC_MPLAB/ParTest/ParTest.c b/20080212/Demo/dsPIC_MPLAB/ParTest/ParTest.c new file mode 100644 index 000000000..65a277406 --- /dev/null +++ b/20080212/Demo/dsPIC_MPLAB/ParTest/ParTest.c @@ -0,0 +1,123 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* Demo app includes. */ +#include "partest.h" + +#define ptOUTPUT 0 +#define ptALL_OFF 0 + +unsigned portBASE_TYPE uxOutput; + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ + /* The explorer 16 board has LED's on port A. All bits are set as output + so PORTA is read-modified-written directly. Two pins have change + notification pullups that need disabling. */ + CNPU2bits.CN22PUE = 0; + CNPU2bits.CN23PUE = 0; + TRISA = ptOUTPUT; + PORTA = ptALL_OFF; + uxOutput = ptALL_OFF; +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ +unsigned portBASE_TYPE uxLEDBit; + + /* Which port A bit is being modified? */ + uxLEDBit = 1 << uxLED; + + if( xValue ) + { + /* Turn the LED on. */ + portENTER_CRITICAL(); + { + uxOutput |= uxLEDBit; + PORTA = uxOutput; + } + portEXIT_CRITICAL(); + } + else + { + /* Turn the LED off. */ + portENTER_CRITICAL(); + { + uxOutput &= ~uxLEDBit; + PORTA = uxOutput; + } + portEXIT_CRITICAL(); + } +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned portBASE_TYPE uxLEDBit; + + uxLEDBit = 1 << uxLED; + portENTER_CRITICAL(); + { + /* If the LED is already on - turn it off. If the LED is already + off, turn it on. */ + if( uxOutput & uxLEDBit ) + { + uxOutput &= ~uxLEDBit; + PORTA = uxOutput; + } + else + { + uxOutput |= uxLEDBit; + PORTA = uxOutput; + } + } + portEXIT_CRITICAL(); +} + diff --git a/20080212/Demo/dsPIC_MPLAB/RTOSDemo.mcs b/20080212/Demo/dsPIC_MPLAB/RTOSDemo.mcs new file mode 100644 index 000000000..ad85eb9d5 --- /dev/null +++ b/20080212/Demo/dsPIC_MPLAB/RTOSDemo.mcs @@ -0,0 +1,3 @@ +[Header] +MagicCookie={0b13fe8c-dfe0-40eb-8900-6712719559a7} +Version=1.0 diff --git a/20080212/Demo/dsPIC_MPLAB/RTOSDemo.mcw b/20080212/Demo/dsPIC_MPLAB/RTOSDemo.mcw new file mode 100644 index 0000000000000000000000000000000000000000..02fb43b1d3e5180cfd8962a2320a08269489b085 GIT binary patch literal 150528 zcmeI53t$_?oyJ$T^D+qp6Ot4HRYGV2Bu18H$4T?DWjl6>v1*AVcZiD>X=AI%k}Aou zllnqh5(<=-M|&;p0S!>v&}oaH^~CXeZv3~Co>vCArAo2#&Y=m)SW9>@wjJjFWJM{$ zHpAXIbm)*7?83&w5Q4=0A0Y5Il#%E7U!f9c3^X1Z2b~Gchf1Mipo!2V=ve4D2u(ma z9x8)QfTlnvLQ|n>&~)en&`HqA&eMB)j|); z=kr+fLZ*HCcGI%0(0Nh&E|5&1_Nqpp1?MCVb=WG?ETza%f_%&}Xqk@i;lS}LmTsLm3dF?a4o$LRb zi2L_+{j=}(CgSU(9o?x=CYp#l>!O+TM1-~lTK)BESE9Tt%+5q>6|LQwr1mcxfo&y% z-p7ZY(u=cDiQe-gI3rc)g;yYS0nQN5Q+&}hbU(G5S3F&}`RheXmE~vyybkClkEv3M z*a+cfV08KJ#p90&VSlz3cB1mkpUaeG|4_I2%o3l%v`pu~AKTA796NZROqqPJOqu@b zRei}ZSNGvm9O{A}y48!Wjw2Grg41Vc^A*Ou0^zS9>;Tks@-n5^Cw~@C&Fl(*U=Vdk#7d-#J0K|HuoZ&*P_V*o7wAf z{IUk@eStw*-?H`fGG$iLTNfRK|Mu$+?RuGu?X!PSyLrZ62G{-anI7=g(_e{g#~wx5 z)r$Q?hl*F1)Nj5N>9|iZPr4xTnKawex8vpo8bhY5o<6N_-#dqj=NSHrP1E|cd=S45 z+f3K~6FuL3NZ)&rQww_=+uPrss@Y{6)0T6kem)pxx_QQi$sq-PZ{i$213iJjMjXEh z?0*Y(?r~RZ`77g21UHJVOnDIY#=oI+s6iaI0ml8-*sJ^g1hEfG;yC?v$e%otCDZz* z?=RE#5v=rKyY>00edclYfiAQc^W4(^pk{FJICJUer}p^{&D7Z3jBVDPd0u#T?Pi{D zwmUku(G2Xcd~CBk7fHmaLG#&*I9qS>ZZ_jG&JEaS`(jzN%K>$sK4F=%9O@mvOnDo1 zVv}UCX3wled)NDNkM9dg4EfF7?9^CH$M)@eruJ=MWVlOF_bCYDKI8Ucn{_vj)80Jf zZLPaGW@s5$J~Buf+@#ytf^DATdGPOo*7Q01w!)`-1lQ!`bu$zn^8F~bn{WUf6%pO@Z`wtL?(-BFqgNpnA*zHo$Mh z96-fi8|IX)m|N;cI5!9yJ*^wF-L;r8II6xi>zki=>iFv~R($t-Kilx03dZpm;~0GO$zbxD{<9)8*694n7-)KMlb)#3)0_7HU^$m#Vf!q7 z@Ec^rp*&Q)-)Ku5+w*lVzM-cuvdA~N_FTZbDA*9JS2qOLHl|dS^X6ci8dF1QH68RO zB5H7zr@XS;x_nfL%e4<&*MvH1$xZu^g7IQ*=CdQ zr$bNA4`{RUfUnUtF0iV(F_G#Tt9vCY)%BSor8tmC7Aa#^M%0MHmT8$&P?&E zj!CuQOmu^aQ7V(dV+2~|a{zs$VSmJNX02sbUyhJ4`Ui1BKnMr{As_^VfDjM@LO=)z z0U;m+gn$qb0zyCt2mv7=1cZPP5CTF#2nYcoAOwVf5D)@FKnMr{As_^VfDjM@LO=)z z0U;m+gn$qb0zyCt2mv7=1cZPP5CTF#2nYcoAOwVf5cqp0a89Is`puU-(0cR2%59gf zp7)Kv=dxPM)_?tx{wn}k;|;fcDpoS$dKGl$nr8#!n(LmJzV-N#+t=4W(Mw=&{g>$| zfVu8TZvCAAR=r4I4I-`rXWw!C7p9>7{AizChjQERy`cOK)PGOIrZ<~j-q~-d6|Nna1oH~47^trm z$n}7@j-Wj^1NOP@3+ux&43%o~-RCW!ebcwb8QOl8wvMbd-f-Knuh~5T5xB0{{wTHfdH@qLf;BmU9k0G7WSvs-L{3x#X zx*Im{K)EQgf6Ul7%lstv-(2p~%7i4!LF_-ZG|+=3ue9|X8OF5SUo&Q}vMT@{uaqhC z5N9{+li#rr+biR2!7;`UuuO1^v46`_Ur!Cv(y>g8!#plq=Ib%4q@~+~G-lcij?=N6 zv2o*lp_nfeS7YP6p(Iy;9b2|4n(hw8oXzoQCK`%GH>s&H-b5^s8aE*vtINb2Lt%Ad zBbJXU_jZO-X*DzMxcY|1+VfTh)_R+2+x!iIQvIlwW@0$DIvS58dID;1<{0gOz7$o_ zfeG5)xuGs~?4%aI(;teboqjbHU9YG2XEw&vW0YfCV-ask4Q15UR76dUAL|c?Vrpdk zBww^wjir5RsyQC+ENU;M0V8WnMc5;A^{o|Z+@C?>MU8YW4$@eG%k63WNQJv*MXjsC zH4#A-F4uftH0}(1w9!X8^F1zSMD6g-bDmXGrEPJPahJPR&2v_kSFhq+$K`BkQsHww zJ?rvhY#(e7TzB+)Q@IZ7Z3xlV3y&zX`pkZYaTvZBYg_jIMPI#adpUd2+qAV_8Sh%I zdwJuQK8Am@!J(~R`V7{;yfyRv;$1kl3B_@v9GkfKTx&WUjm1KlM5==2sdBL-75r%A z;ZQOe+gR6~$t2>uM6_M51?P<=!WUxcvX3)n4X>8Q@J2QsPq|BT1my2b^wdT+gyLZ} z!p0bhrbFvuDx+!X{i!f*G{-Y)Djte8wt1OKJ5(Rt5XFh3DKwTq0{d<<^Y=tE;m&Bh zqc$FCNuaSMQY|=P97g?EKP{XYA_6mQh|_XycQ5K|DGJl+hrG#dw2El5Q#0Sjb&W0Y zXgV81O@(5)SiB-C0*Q**@Y~dIVuPCU`p(nyVoWWo*0@&5RCh9C$(0}$FODSQ>e8hw zWHwIP?a7@C_hC;40j@&56R7}e$QE&4T5SnMW<0^xx3a&@<3)pl6}ypgqv@&~KsNK`%fr zLcfRp0KEkL5qcT=6SNn41$q^F4cZ6&8G0T13$!0P0C7pf|A7ude}&$J-h$qS{sz4R zX&n#hs`*M=Z6(5TZirb)HcC*5jOm2-oN@n{_7m{`43+-Mi7T zGLF`d3OFGk1cZPP5CTF#2nYcoAOwVf5D)@FKnMr{As_^VfDjM@LO=)z0U;m+gn$qb z0zyCt2mv7=1cZPP5CTF#2nYcoAOwVf5D)@FKnMr{As_^VfDjM@LO=)z0U;m+gn$qb z0zyCt2mv7=1cZPP5CTF#2nYcoAOwVf5D)@FKnMr{As_^VfDjM@LO=)z0U;m+gn$qb z0zyCt2mv7=1cZPP5CTF#2nYcoAOwVf5D)@FKnMr{As_^VfDjM@LO=)z0U;m+gn$qb z0zyCt2mv7=1cZPP5CTF#2nYcoAOwVf5D)@FKnMr{As_^VfDjM@LO=)z0U;m+gn$qb z0zyCt2mv7=1cZPP5CTF#2nYcoAOwVf5D)@FKnMr{As__$5%4MrC9Y%?Rr^f$J7#C6 zOeu04vN$_wPC}%KMnu2TsI)0gWrbD(RY@r!C1xiRBhK_u*q@KI(~b0vN)+}~l%Nft z9ZEXSvdkWZ{ZnCkhG9Pfi%F#de^tr?e7cnyWufB2wmmmPaX88lm3f{rOcK}27i@j; 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+ +/* + * Setup the processor ready for the demo. + */ +static void prvSetupHardware( void ); + +/*-----------------------------------------------------------*/ + +/* The queue used to send messages to the LCD task. */ +static xQueueHandle xLCDQueue; + +/*-----------------------------------------------------------*/ + +/* + * Create the demo tasks then start the scheduler. + */ +int main( void ) +{ + /* Configure any hardware required for this demo. */ + prvSetupHardware(); + + /* Create the standard demo tasks. */ + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vStartFlashCoRoutines( mainNUM_FLASH_COROUTINES ); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); + vCreateBlockTimeTasks(); + + /* Create the test tasks defined within this file. */ + xTaskCreate( vCheckTask, ( signed portCHAR * ) "Check", mainCHECK_TAKS_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Start the task that will control the LCD. This returns the handle + to the queue used to write text out to the task. */ + xLCDQueue = xStartLCDTask(); + + /* Start the high frequency interrupt test. */ + vSetupTimerTest( mainTEST_INTERRUPT_FREQUENCY ); + + /* Finally start the scheduler. */ + vTaskStartScheduler(); + + /* Will only reach here if there is insufficient heap available to start + the scheduler. */ + return 0; +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + vParTestInitialise(); +} +/*-----------------------------------------------------------*/ + +static void vCheckTask( void *pvParameters ) +{ +/* Used to wake the task at the correct frequency. */ +portTickType xLastExecutionTime; + +/* The maximum jitter time measured by the fast interrupt test. */ +extern unsigned portSHORT usMaxJitter ; + +/* Buffer into which the maximum jitter time is written as a string. */ +static portCHAR cStringBuffer[ mainMAX_STRING_LENGTH ]; + +/* The message that is sent on the queue to the LCD task. The first +parameter is the minimum time (in ticks) that the message should be +left on the LCD without being overwritten. The second parameter is a pointer +to the message to display itself. */ +xLCDMessage xMessage = { 0, cStringBuffer }; + +/* Set to pdTRUE should an error be detected in any of the standard demo tasks. */ +unsigned portSHORT usErrorDetected = pdFALSE; + + /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() + works correctly. */ + xLastExecutionTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Wait until it is time for the next cycle. */ + vTaskDelayUntil( &xLastExecutionTime, mainCHECK_TASK_PERIOD ); + + /* Has an error been found in any of the standard demo tasks? */ + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + usErrorDetected = pdTRUE; + sprintf( cStringBuffer, "FAIL #1" ); + } + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + usErrorDetected = pdTRUE; + sprintf( cStringBuffer, "FAIL #2" ); + } + + if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + usErrorDetected = pdTRUE; + sprintf( cStringBuffer, "FAIL #3" ); + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + usErrorDetected = pdTRUE; + sprintf( cStringBuffer, "FAIL #4" ); + } + + if( usErrorDetected == pdFALSE ) + { + /* No errors have been discovered, so display the maximum jitter + timer discovered by the "fast interrupt test". */ + sprintf( cStringBuffer, "%dns max jitter", ( portSHORT ) ( usMaxJitter - mainEXPECTED_CLOCKS_BETWEEN_INTERRUPTS ) * mainNS_PER_CLOCK ); + } + + /* Send the message to the LCD gatekeeper for display. */ + xQueueSend( xLCDQueue, &xMessage, portMAX_DELAY ); + } +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ + /* Schedule the co-routines from within the idle task hook. */ + vCoRoutineSchedule(); +} +/*-----------------------------------------------------------*/ + diff --git a/20080212/Demo/dsPIC_MPLAB/p33FJ256GP710.gld b/20080212/Demo/dsPIC_MPLAB/p33FJ256GP710.gld new file mode 100644 index 000000000..c5e6cffae --- /dev/null +++ b/20080212/Demo/dsPIC_MPLAB/p33FJ256GP710.gld @@ -0,0 +1,1986 @@ +/* +** Linker script for PIC33FJ256GP710 +*/ + +OUTPUT_ARCH("33FJ256GP710") +EXTERN(__resetPRI) +EXTERN(__resetALT) + + +/* +** Memory Regions +*/ +MEMORY +{ + data (a!xr) : ORIGIN = 0x800, LENGTH = 0x7800 + reset : ORIGIN = 0x0, LENGTH = 0x4 + ivt : ORIGIN = 0x4, LENGTH = 0xFC + aivt : ORIGIN = 0x104, LENGTH = 0xFC + program (xr) : ORIGIN = 0x200, LENGTH = 0x2AA00 + FBS : ORIGIN = 0xF80000, LENGTH = 0x2 + FSS : ORIGIN = 0xF80002, LENGTH = 0x2 + FGS : ORIGIN = 0xF80004, LENGTH = 0x2 + FOSCSEL : ORIGIN = 0xF80006, LENGTH = 0x2 + FOSC : ORIGIN = 0xF80008, LENGTH = 0x2 + FWDT : ORIGIN = 0xF8000A, LENGTH = 0x2 + FPOR : ORIGIN = 0xF8000C, LENGTH = 0x2 + CONFIG3 : ORIGIN = 0xF8000E, LENGTH = 0x2 + FUID0 : ORIGIN = 0xF80010, LENGTH = 0x2 + FUID1 : ORIGIN = 0xF80012, LENGTH = 0x2 + FUID2 : ORIGIN = 0xF80014, LENGTH = 0x2 + FUID3 : ORIGIN = 0xF80016, LENGTH = 0x2 +} +__IVT_BASE = 0x4; +__AIVT_BASE = 0x104; +__DATA_BASE = 0x800; +__YDATA_BASE = 0x4800; +__DMA_BASE = 0x7800; +__DMA_END = 0x7FFF; +__CODE_BASE = 0x200; + + +/* +** ==================== Section Map ====================== +*/ +SECTIONS +{ + /* + ** ========== Program Memory ========== + */ + + + /* + ** Reset Instruction + */ + .reset : + { + SHORT(ABSOLUTE(__reset)); + SHORT(0x04); + SHORT((ABSOLUTE(__reset) >> 16) & 0x7F); + SHORT(0); + } >reset + + + /* + ** Interrupt Vector Tables + ** + ** The primary and alternate tables are loaded + ** here, between sections .reset and .text. + ** Vector table source code appears below. + */ + + + /* + ** User Code and Library Code + */ + .text __CODE_BASE : + { + *(.handle); + *(.libc) *(.libm) *(.libdsp); /* keep together in this order */ + *(.lib*); + *(.text); + } >program + + + /* + ** Configuration Words + */ + __FBS : + { *(__FBS.sec) } >FBS + __FSS : + { *(__FSS.sec) } >FSS + __FGS : + { *(__FGS.sec) } >FGS + __FOSCSEL : + { *(__FOSCSEL.sec) } >FOSCSEL + __FOSC : + { *(__FOSC.sec) } >FOSC + __FWDT : + { *(__FWDT.sec) } >FWDT + __FPOR : + { *(__FPOR.sec) } >FPOR + __FUID0 : + { *(__FUID0.sec) } >FUID0 + __FUID1 : + { *(__FUID1.sec) } >FUID1 + __FUID2 : + { *(__FUID2.sec) } >FUID2 + __FUID3 : + { *(__FUID3.sec) } >FUID3 + + + /* + ** =========== Data Memory =========== + */ + + + /* + ** ICD Debug Exec + ** + ** This section provides optional storage for + ** the ICD2 debugger. Define a global symbol + ** named __ICD2RAM to enable ICD2. This section + ** must be loaded at data address 0x800. + */ + .icd __DATA_BASE (NOLOAD): + { + . += (DEFINED (__ICD2RAM) ? 0x50 : 0 ); + } > data + + + /* + ** Other sections in data memory are not explicitly mapped. + ** Instead they are allocated according to their section + ** attributes, which is most efficient. + ** + ** If a specific arrangement of sections is required + ** (other than what can be achieved using attributes) + ** additional sections may be defined here. See chapter + ** 10.5 in the MPLAB ASM30/LINK30 User's Guide (DS51317) + ** for more information. + */ + + + /* + ** ========== Debug Info ============== + */ + + .comment 0 : { *(.comment) } + + /* + ** DWARF-2 + */ + .debug_info 0 : { *(.debug_info) *(.gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_ranges 0 : { *(.debug_ranges) } + .debug_aranges 0 : { *(.debug_aranges) } + +} /* SECTIONS */ + +/* +** ================= End of Section Map ================ +*/ + +/* +** Section Map for Interrupt Vector Tables +*/ +SECTIONS +{ + +/* +** Interrupt Vector Table +*/ +.ivt __IVT_BASE : + { + LONG( DEFINED(__ReservedTrap0) ? ABSOLUTE(__ReservedTrap0) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__OscillatorFail) ? ABSOLUTE(__OscillatorFail) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__AddressError) ? ABSOLUTE(__AddressError) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__StackError) ? ABSOLUTE(__StackError) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__MathError) ? ABSOLUTE(__MathError) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__DMACError) ? ABSOLUTE(__DMACError) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__ReservedTrap6) ? ABSOLUTE(__ReservedTrap6) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__ReservedTrap7) ? ABSOLUTE(__ReservedTrap7) : + ABSOLUTE(__DefaultInterrupt)); + + LONG( DEFINED(__INT0Interrupt) ? ABSOLUTE(__INT0Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__IC1Interrupt) ? ABSOLUTE(__IC1Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__OC1Interrupt) ? ABSOLUTE(__OC1Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__T1Interrupt) ? ABSOLUTE(__T1Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__DMA0Interrupt) ? ABSOLUTE(__DMA0Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__IC2Interrupt) ? ABSOLUTE(__IC2Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__OC2Interrupt) ? ABSOLUTE(__OC2Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__T2Interrupt) ? ABSOLUTE(__T2Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__T3Interrupt) ? ABSOLUTE(__T3Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__SPI1ErrInterrupt) ? ABSOLUTE(__SPI1ErrInterrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__SPI1Interrupt) ? ABSOLUTE(__SPI1Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__U1RXInterrupt) ? ABSOLUTE(__U1RXInterrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__U1TXInterrupt) ? ABSOLUTE(__U1TXInterrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__ADC1Interrupt) ? ABSOLUTE(__ADC1Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__DMA1Interrupt) ? ABSOLUTE(__DMA1Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt15) ? ABSOLUTE(__Interrupt15) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__SI2C1Interrupt) ? ABSOLUTE(__SI2C1Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__MI2C1Interrupt) ? ABSOLUTE(__MI2C1Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt18) ? ABSOLUTE(__Interrupt18) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__CNInterrupt) ? ABSOLUTE(__CNInterrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__INT1Interrupt) ? ABSOLUTE(__INT1Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__ADC2Interrupt) ? ABSOLUTE(__ADC2Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__IC7Interrupt) ? ABSOLUTE(__IC7Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__IC8Interrupt) ? ABSOLUTE(__IC8Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__DMA2Interrupt) ? ABSOLUTE(__DMA2Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__OC3Interrupt) ? ABSOLUTE(__OC3Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__OC4Interrupt) ? ABSOLUTE(__OC4Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__T4Interrupt) ? ABSOLUTE(__T4Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__T5Interrupt) ? ABSOLUTE(__T5Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__INT2Interrupt) ? ABSOLUTE(__INT2Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__U2RXInterrupt) ? ABSOLUTE(__U2RXInterrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__U2TXInterrupt) ? ABSOLUTE(__U2TXInterrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__SPI2ErrInterrupt) ? ABSOLUTE(__SPI2ErrInterrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__SPI2Interrupt) ? ABSOLUTE(__SPI2Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__C1RxRdyInterrupt) ? ABSOLUTE(__C1RxRdyInterrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__C1Interrupt) ? ABSOLUTE(__C1Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__DMA3Interrupt) ? ABSOLUTE(__DMA3Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__IC3Interrupt) ? ABSOLUTE(__IC3Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__IC4Interrupt) ? ABSOLUTE(__IC4Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__IC5Interrupt) ? ABSOLUTE(__IC5Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__IC6Interrupt) ? ABSOLUTE(__IC6Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__OC5Interrupt) ? ABSOLUTE(__OC5Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__OC6Interrupt) ? ABSOLUTE(__OC6Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__OC7Interrupt) ? ABSOLUTE(__OC7Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__OC8Interrupt) ? ABSOLUTE(__OC8Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt45) ? ABSOLUTE(__Interrupt45) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__DMA4Interrupt) ? ABSOLUTE(__DMA4Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__T6Interrupt) ? ABSOLUTE(__T6Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__T7Interrupt) ? ABSOLUTE(__T7Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__SI2C2Interrupt) ? ABSOLUTE(__SI2C2Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__MI2C2Interrupt) ? ABSOLUTE(__MI2C2Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__T8Interrupt) ? ABSOLUTE(__T8Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__T9Interrupt) ? ABSOLUTE(__T9Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__INT3Interrupt) ? ABSOLUTE(__INT3Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__INT4Interrupt) ? ABSOLUTE(__INT4Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__C2RxRdyInterrupt) ? ABSOLUTE(__C2RxRdyInterrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__C2Interrupt) ? ABSOLUTE(__C2Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt57) ? ABSOLUTE(__Interrupt57) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt58) ? ABSOLUTE(__Interrupt58) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__DCIErrInterrupt) ? ABSOLUTE(__DCIErrInterrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__DCIInterrupt) ? ABSOLUTE(__DCIInterrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__DMA5Interrupt) ? ABSOLUTE(__DMA5Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt62) ? ABSOLUTE(__Interrupt62) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt63) ? ABSOLUTE(__Interrupt63) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt64) ? ABSOLUTE(__Interrupt64) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__U1ErrInterrupt) ? ABSOLUTE(__U1ErrInterrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__U2ErrInterrupt) ? ABSOLUTE(__U2ErrInterrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt68) ? ABSOLUTE(__Interrupt68) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__DMA6Interrupt) ? ABSOLUTE(__DMA6Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__DMA7Interrupt) ? ABSOLUTE(__DMA7Interrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__C1TxReqInterrupt) ? ABSOLUTE(__C1TxReqInterrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__C2TxReqInterrupt) ? ABSOLUTE(__C2TxReqInterrupt) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt72) ? ABSOLUTE(__Interrupt72) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt73) ? ABSOLUTE(__Interrupt73) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt74) ? ABSOLUTE(__Interrupt74) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt75) ? ABSOLUTE(__Interrupt75) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt76) ? ABSOLUTE(__Interrupt76) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt77) ? ABSOLUTE(__Interrupt77) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt78) ? ABSOLUTE(__Interrupt78) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt79) ? ABSOLUTE(__Interrupt79) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt80) ? ABSOLUTE(__Interrupt80) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt81) ? ABSOLUTE(__Interrupt81) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt82) ? ABSOLUTE(__Interrupt82) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt83) ? ABSOLUTE(__Interrupt83) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt84) ? ABSOLUTE(__Interrupt84) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt85) ? ABSOLUTE(__Interrupt85) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt86) ? ABSOLUTE(__Interrupt86) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt87) ? ABSOLUTE(__Interrupt87) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt88) ? ABSOLUTE(__Interrupt88) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt89) ? ABSOLUTE(__Interrupt89) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt90) ? ABSOLUTE(__Interrupt90) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt91) ? ABSOLUTE(__Interrupt91) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt92) ? ABSOLUTE(__Interrupt92) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt93) ? ABSOLUTE(__Interrupt93) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt94) ? ABSOLUTE(__Interrupt94) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt95) ? ABSOLUTE(__Interrupt95) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt96) ? ABSOLUTE(__Interrupt96) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt97) ? ABSOLUTE(__Interrupt97) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt98) ? ABSOLUTE(__Interrupt98) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt99) ? ABSOLUTE(__Interrupt99) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt100) ? ABSOLUTE(__Interrupt100) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt101) ? ABSOLUTE(__Interrupt101) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt102) ? ABSOLUTE(__Interrupt102) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt103) ? ABSOLUTE(__Interrupt103) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt104) ? ABSOLUTE(__Interrupt104) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt105) ? ABSOLUTE(__Interrupt105) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt106) ? ABSOLUTE(__Interrupt106) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt107) ? ABSOLUTE(__Interrupt107) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt108) ? ABSOLUTE(__Interrupt108) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt109) ? ABSOLUTE(__Interrupt109) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt110) ? ABSOLUTE(__Interrupt110) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt111) ? ABSOLUTE(__Interrupt111) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt112) ? ABSOLUTE(__Interrupt112) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt113) ? ABSOLUTE(__Interrupt113) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt114) ? ABSOLUTE(__Interrupt114) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt115) ? ABSOLUTE(__Interrupt115) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt116) ? ABSOLUTE(__Interrupt116) : + ABSOLUTE(__DefaultInterrupt)); + LONG( DEFINED(__Interrupt117) ? ABSOLUTE(__Interrupt117) : + ABSOLUTE(__DefaultInterrupt)); + } >ivt + + +/* +** Alternate Interrupt Vector Table +*/ +.aivt __AIVT_BASE : + { + LONG( DEFINED(__AltReservedTrap0) ? ABSOLUTE(__AltReservedTrap0) : + (DEFINED(__ReservedTrap0) ? ABSOLUTE(__ReservedTrap0) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltOscillatorFail) ? ABSOLUTE(__AltOscillatorFail) : + (DEFINED(__OscillatorFail) ? ABSOLUTE(__OscillatorFail) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltAddressError) ? ABSOLUTE(__AltAddressError) : + (DEFINED(__AddressError) ? ABSOLUTE(__AddressError) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltStackError) ? ABSOLUTE(__AltStackError) : + (DEFINED(__StackError) ? ABSOLUTE(__StackError) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltMathError) ? ABSOLUTE(__AltMathError) : + (DEFINED(__MathError) ? ABSOLUTE(__MathError) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltDMACError) ? ABSOLUTE(__AltDMACError) : + (DEFINED(__DMACError) ? ABSOLUTE(__DMACError) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltReservedTrap6) ? ABSOLUTE(__AltReservedTrap6) : + (DEFINED(__ReservedTrap6) ? ABSOLUTE(__ReservedTrap6) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltReservedTrap7) ? ABSOLUTE(__AltReservedTrap7) : + (DEFINED(__ReservedTrap7) ? ABSOLUTE(__ReservedTrap7) : + ABSOLUTE(__DefaultInterrupt))); + + LONG( DEFINED(__AltINT0Interrupt) ? ABSOLUTE(__AltINT0Interrupt) : + (DEFINED(__INT0Interrupt) ? ABSOLUTE(__INT0Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltIC1Interrupt) ? ABSOLUTE(__AltIC1Interrupt) : + (DEFINED(__IC1Interrupt) ? ABSOLUTE(__IC1Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltOC1Interrupt) ? ABSOLUTE(__AltOC1Interrupt) : + (DEFINED(__OC1Interrupt) ? ABSOLUTE(__OC1Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltT1Interrupt) ? ABSOLUTE(__AltT1Interrupt) : + (DEFINED(__T1Interrupt) ? ABSOLUTE(__T1Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltDMA0Interrupt) ? ABSOLUTE(__AltDMA0Interrupt) : + (DEFINED(__DMA0Interrupt) ? ABSOLUTE(__DMA0Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltIC2Interrupt) ? ABSOLUTE(__AltIC2Interrupt) : + (DEFINED(__IC2Interrupt) ? ABSOLUTE(__IC2Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltOC2Interrupt) ? ABSOLUTE(__AltOC2Interrupt) : + (DEFINED(__OC2Interrupt) ? ABSOLUTE(__OC2Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltT2Interrupt) ? ABSOLUTE(__AltT2Interrupt) : + (DEFINED(__T2Interrupt) ? ABSOLUTE(__T2Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltT3Interrupt) ? ABSOLUTE(__AltT3Interrupt) : + (DEFINED(__T3Interrupt) ? ABSOLUTE(__T3Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltSPI1ErrInterrupt) ? ABSOLUTE(__AltSPI1ErrInterrupt) : + (DEFINED(__SPI1ErrInterrupt) ? ABSOLUTE(__SPI1ErrInterrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltSPI1Interrupt) ? ABSOLUTE(__AltSPI1Interrupt) : + (DEFINED(__SPI1Interrupt) ? ABSOLUTE(__SPI1Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltU1RXInterrupt) ? ABSOLUTE(__AltU1RXInterrupt) : + (DEFINED(__U1RXInterrupt) ? ABSOLUTE(__U1RXInterrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltU1TXInterrupt) ? ABSOLUTE(__AltU1TXInterrupt) : + (DEFINED(__U1TXInterrupt) ? ABSOLUTE(__U1TXInterrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltADC1Interrupt) ? ABSOLUTE(__AltADC1Interrupt) : + (DEFINED(__ADC1Interrupt) ? ABSOLUTE(__ADC1Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltDMA1Interrupt) ? ABSOLUTE(__AltDMA1Interrupt) : + (DEFINED(__DMA1Interrupt) ? ABSOLUTE(__DMA1Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt15) ? ABSOLUTE(__AltInterrupt15) : + (DEFINED(__Interrupt15) ? ABSOLUTE(__Interrupt15) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltSI2C1Interrupt) ? ABSOLUTE(__AltSI2C1Interrupt) : + (DEFINED(__SI2C1Interrupt) ? ABSOLUTE(__SI2C1Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltMI2C1Interrupt) ? ABSOLUTE(__AltMI2C1Interrupt) : + (DEFINED(__MI2C1Interrupt) ? ABSOLUTE(__MI2C1Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt18) ? ABSOLUTE(__AltInterrupt18) : + (DEFINED(__Interrupt18) ? ABSOLUTE(__Interrupt18) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltCNInterrupt) ? ABSOLUTE(__AltCNInterrupt) : + (DEFINED(__CNInterrupt) ? ABSOLUTE(__CNInterrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltINT1Interrupt) ? ABSOLUTE(__AltINT1Interrupt) : + (DEFINED(__INT1Interrupt) ? ABSOLUTE(__INT1Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltADC2Interrupt) ? ABSOLUTE(__AltADC2Interrupt) : + (DEFINED(__ADC2Interrupt) ? ABSOLUTE(__ADC2Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltIC7Interrupt) ? ABSOLUTE(__AltIC7Interrupt) : + (DEFINED(__IC7Interrupt) ? ABSOLUTE(__IC7Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltIC8Interrupt) ? ABSOLUTE(__AltIC8Interrupt) : + (DEFINED(__IC8Interrupt) ? ABSOLUTE(__IC8Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltDMA2Interrupt) ? ABSOLUTE(__AltDMA2Interrupt) : + (DEFINED(__DMA2Interrupt) ? ABSOLUTE(__DMA2Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltOC3Interrupt) ? ABSOLUTE(__AltOC3Interrupt) : + (DEFINED(__OC3Interrupt) ? ABSOLUTE(__OC3Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltOC4Interrupt) ? ABSOLUTE(__AltOC4Interrupt) : + (DEFINED(__OC4Interrupt) ? ABSOLUTE(__OC4Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltT4Interrupt) ? ABSOLUTE(__AltT4Interrupt) : + (DEFINED(__T4Interrupt) ? ABSOLUTE(__T4Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltT5Interrupt) ? ABSOLUTE(__AltT5Interrupt) : + (DEFINED(__T5Interrupt) ? ABSOLUTE(__T5Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltINT2Interrupt) ? ABSOLUTE(__AltINT2Interrupt) : + (DEFINED(__INT2Interrupt) ? ABSOLUTE(__INT2Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltU2RXInterrupt) ? ABSOLUTE(__AltU2RXInterrupt) : + (DEFINED(__U2RXInterrupt) ? ABSOLUTE(__U2RXInterrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltU2TXInterrupt) ? ABSOLUTE(__AltU2TXInterrupt) : + (DEFINED(__U2TXInterrupt) ? ABSOLUTE(__U2TXInterrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltSPI2ErrInterrupt) ? ABSOLUTE(__AltSPI2ErrInterrupt) : + (DEFINED(__SPI2ErrInterrupt) ? ABSOLUTE(__SPI2ErrInterrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltSPI2Interrupt) ? ABSOLUTE(__AltSPI2Interrupt) : + (DEFINED(__SPI2Interrupt) ? ABSOLUTE(__SPI2Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltC1RxRdyInterrupt) ? ABSOLUTE(__AltC1RxRdyInterrupt) : + (DEFINED(__C1RxRdyInterrupt) ? ABSOLUTE(__C1RxRdyInterrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltC1Interrupt) ? ABSOLUTE(__AltC1Interrupt) : + (DEFINED(__C1Interrupt) ? ABSOLUTE(__C1Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltDMA3Interrupt) ? ABSOLUTE(__AltDMA3Interrupt) : + (DEFINED(__DMA3Interrupt) ? ABSOLUTE(__DMA3Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltIC3Interrupt) ? ABSOLUTE(__AltIC3Interrupt) : + (DEFINED(__IC3Interrupt) ? ABSOLUTE(__IC3Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltIC4Interrupt) ? ABSOLUTE(__AltIC4Interrupt) : + (DEFINED(__IC4Interrupt) ? ABSOLUTE(__IC4Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltIC5Interrupt) ? ABSOLUTE(__AltIC5Interrupt) : + (DEFINED(__IC5Interrupt) ? ABSOLUTE(__IC5Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltIC6Interrupt) ? ABSOLUTE(__AltIC6Interrupt) : + (DEFINED(__IC6Interrupt) ? ABSOLUTE(__IC6Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltOC5Interrupt) ? ABSOLUTE(__AltOC5Interrupt) : + (DEFINED(__OC5Interrupt) ? ABSOLUTE(__OC5Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltOC6Interrupt) ? ABSOLUTE(__AltOC6Interrupt) : + (DEFINED(__OC6Interrupt) ? ABSOLUTE(__OC6Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltOC7Interrupt) ? ABSOLUTE(__AltOC7Interrupt) : + (DEFINED(__OC7Interrupt) ? ABSOLUTE(__OC7Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltOC8Interrupt) ? ABSOLUTE(__AltOC8Interrupt) : + (DEFINED(__OC8Interrupt) ? ABSOLUTE(__OC8Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt45) ? ABSOLUTE(__AltInterrupt45) : + (DEFINED(__Interrupt45) ? ABSOLUTE(__Interrupt45) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltDMA4Interrupt) ? ABSOLUTE(__AltDMA4Interrupt) : + (DEFINED(__DMA4Interrupt) ? ABSOLUTE(__DMA4Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltT6Interrupt) ? ABSOLUTE(__AltT6Interrupt) : + (DEFINED(__T6Interrupt) ? ABSOLUTE(__T6Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltT7Interrupt) ? ABSOLUTE(__AltT7Interrupt) : + (DEFINED(__T7Interrupt) ? ABSOLUTE(__T7Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltSI2C2Interrupt) ? ABSOLUTE(__AltSI2C2Interrupt) : + (DEFINED(__SI2C2Interrupt) ? ABSOLUTE(__SI2C2Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltMI2C2Interrupt) ? ABSOLUTE(__AltMI2C2Interrupt) : + (DEFINED(__MI2C2Interrupt) ? ABSOLUTE(__MI2C2Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltT8Interrupt) ? ABSOLUTE(__AltT8Interrupt) : + (DEFINED(__T8Interrupt) ? ABSOLUTE(__T8Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltT9Interrupt) ? ABSOLUTE(__AltT9Interrupt) : + (DEFINED(__T9Interrupt) ? ABSOLUTE(__T9Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltINT3Interrupt) ? ABSOLUTE(__AltINT3Interrupt) : + (DEFINED(__INT3Interrupt) ? ABSOLUTE(__INT3Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltINT4Interrupt) ? ABSOLUTE(__AltINT4Interrupt) : + (DEFINED(__INT4Interrupt) ? ABSOLUTE(__INT4Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltC2RxRdyInterrupt) ? ABSOLUTE(__AltC2RxRdyInterrupt) : + (DEFINED(__C2RxRdyInterrupt) ? ABSOLUTE(__C2RxRdyInterrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltC2Interrupt) ? ABSOLUTE(__AltC2Interrupt) : + (DEFINED(__C2Interrupt) ? ABSOLUTE(__C2Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt57) ? ABSOLUTE(__AltInterrupt57) : + (DEFINED(__Interrupt57) ? ABSOLUTE(__Interrupt57) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt58) ? ABSOLUTE(__AltInterrupt58) : + (DEFINED(__Interrupt58) ? ABSOLUTE(__Interrupt58) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltDCIErrInterrupt) ? ABSOLUTE(__AltDCIErrInterrupt) : + (DEFINED(__DCIErrInterrupt) ? ABSOLUTE(__DCIErrInterrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltDCIInterrupt) ? ABSOLUTE(__AltDCIInterrupt) : + (DEFINED(__DCIInterrupt) ? ABSOLUTE(__DCIInterrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltDMA5Interrupt) ? ABSOLUTE(__AltDMA5Interrupt) : + (DEFINED(__DMA5Interrupt) ? ABSOLUTE(__DMA5Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt62) ? ABSOLUTE(__AltInterrupt62) : + (DEFINED(__Interrupt62) ? ABSOLUTE(__Interrupt62) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt63) ? ABSOLUTE(__AltInterrupt63) : + (DEFINED(__Interrupt63) ? ABSOLUTE(__Interrupt63) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt64) ? ABSOLUTE(__AltInterrupt64) : + (DEFINED(__Interrupt64) ? ABSOLUTE(__Interrupt64) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltU1ErrInterrupt) ? ABSOLUTE(__AltU1ErrInterrupt) : + (DEFINED(__U1ErrInterrupt) ? ABSOLUTE(__U1ErrInterrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltU2ErrInterrupt) ? ABSOLUTE(__AltU2ErrInterrupt) : + (DEFINED(__U2ErrInterrupt) ? ABSOLUTE(__U2ErrInterrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt68) ? ABSOLUTE(__AltInterrupt68) : + (DEFINED(__Interrupt68) ? ABSOLUTE(__Interrupt68) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltDMA6Interrupt) ? ABSOLUTE(__AltDMA6Interrupt) : + (DEFINED(__DMA6Interrupt) ? ABSOLUTE(__DMA6Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltDMA7Interrupt) ? ABSOLUTE(__AltDMA7Interrupt) : + (DEFINED(__DMA7Interrupt) ? ABSOLUTE(__DMA7Interrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltC1TxReqInterrupt) ? ABSOLUTE(__AltC1TxReqInterrupt) : + (DEFINED(__C1TxReqInterrupt) ? ABSOLUTE(__C1TxReqInterrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltC2TxReqInterrupt) ? ABSOLUTE(__AltC2TxReqInterrupt) : + (DEFINED(__C2TxReqInterrupt) ? ABSOLUTE(__C2TxReqInterrupt) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt72) ? ABSOLUTE(__AltInterrupt72) : + (DEFINED(__Interrupt72) ? ABSOLUTE(__Interrupt72) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt73) ? ABSOLUTE(__AltInterrupt73) : + (DEFINED(__Interrupt73) ? ABSOLUTE(__Interrupt73) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt74) ? ABSOLUTE(__AltInterrupt74) : + (DEFINED(__Interrupt74) ? ABSOLUTE(__Interrupt74) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt75) ? ABSOLUTE(__AltInterrupt75) : + (DEFINED(__Interrupt75) ? ABSOLUTE(__Interrupt75) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt76) ? ABSOLUTE(__AltInterrupt76) : + (DEFINED(__Interrupt76) ? ABSOLUTE(__Interrupt76) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt77) ? ABSOLUTE(__AltInterrupt77) : + (DEFINED(__Interrupt77) ? ABSOLUTE(__Interrupt77) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt78) ? ABSOLUTE(__AltInterrupt78) : + (DEFINED(__Interrupt78) ? ABSOLUTE(__Interrupt78) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt79) ? ABSOLUTE(__AltInterrupt79) : + (DEFINED(__Interrupt79) ? ABSOLUTE(__Interrupt79) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt80) ? ABSOLUTE(__AltInterrupt80) : + (DEFINED(__Interrupt80) ? ABSOLUTE(__Interrupt80) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt81) ? ABSOLUTE(__AltInterrupt81) : + (DEFINED(__Interrupt81) ? ABSOLUTE(__Interrupt81) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt82) ? ABSOLUTE(__AltInterrupt82) : + (DEFINED(__Interrupt82) ? ABSOLUTE(__Interrupt82) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt83) ? ABSOLUTE(__AltInterrupt83) : + (DEFINED(__Interrupt83) ? ABSOLUTE(__Interrupt83) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt84) ? ABSOLUTE(__AltInterrupt84) : + (DEFINED(__Interrupt84) ? ABSOLUTE(__Interrupt84) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt85) ? ABSOLUTE(__AltInterrupt85) : + (DEFINED(__Interrupt85) ? ABSOLUTE(__Interrupt85) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt86) ? ABSOLUTE(__AltInterrupt86) : + (DEFINED(__Interrupt86) ? ABSOLUTE(__Interrupt86) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt87) ? ABSOLUTE(__AltInterrupt87) : + (DEFINED(__Interrupt87) ? ABSOLUTE(__Interrupt87) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt88) ? ABSOLUTE(__AltInterrupt88) : + (DEFINED(__Interrupt88) ? ABSOLUTE(__Interrupt88) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt89) ? ABSOLUTE(__AltInterrupt89) : + (DEFINED(__Interrupt89) ? ABSOLUTE(__Interrupt89) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt90) ? ABSOLUTE(__AltInterrupt90) : + (DEFINED(__Interrupt90) ? ABSOLUTE(__Interrupt90) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt91) ? ABSOLUTE(__AltInterrupt91) : + (DEFINED(__Interrupt91) ? ABSOLUTE(__Interrupt91) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt92) ? ABSOLUTE(__AltInterrupt92) : + (DEFINED(__Interrupt92) ? ABSOLUTE(__Interrupt92) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt93) ? ABSOLUTE(__AltInterrupt93) : + (DEFINED(__Interrupt93) ? ABSOLUTE(__Interrupt93) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt94) ? ABSOLUTE(__AltInterrupt94) : + (DEFINED(__Interrupt94) ? ABSOLUTE(__Interrupt94) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt95) ? ABSOLUTE(__AltInterrupt95) : + (DEFINED(__Interrupt95) ? ABSOLUTE(__Interrupt95) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt96) ? ABSOLUTE(__AltInterrupt96) : + (DEFINED(__Interrupt96) ? ABSOLUTE(__Interrupt96) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt97) ? ABSOLUTE(__AltInterrupt97) : + (DEFINED(__Interrupt97) ? ABSOLUTE(__Interrupt97) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt98) ? ABSOLUTE(__AltInterrupt98) : + (DEFINED(__Interrupt98) ? ABSOLUTE(__Interrupt98) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt99) ? ABSOLUTE(__AltInterrupt99) : + (DEFINED(__Interrupt99) ? ABSOLUTE(__Interrupt99) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt100) ? ABSOLUTE(__AltInterrupt100) : + (DEFINED(__Interrupt100) ? ABSOLUTE(__Interrupt100) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt101) ? ABSOLUTE(__AltInterrupt101) : + (DEFINED(__Interrupt101) ? ABSOLUTE(__Interrupt101) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt102) ? ABSOLUTE(__AltInterrupt102) : + (DEFINED(__Interrupt102) ? ABSOLUTE(__Interrupt102) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt103) ? ABSOLUTE(__AltInterrupt103) : + (DEFINED(__Interrupt103) ? ABSOLUTE(__Interrupt103) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt104) ? ABSOLUTE(__AltInterrupt104) : + (DEFINED(__Interrupt104) ? ABSOLUTE(__Interrupt104) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt105) ? ABSOLUTE(__AltInterrupt105) : + (DEFINED(__Interrupt105) ? ABSOLUTE(__Interrupt105) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt106) ? ABSOLUTE(__AltInterrupt106) : + (DEFINED(__Interrupt106) ? ABSOLUTE(__Interrupt106) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt107) ? ABSOLUTE(__AltInterrupt107) : + (DEFINED(__Interrupt107) ? ABSOLUTE(__Interrupt107) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt108) ? ABSOLUTE(__AltInterrupt108) : + (DEFINED(__Interrupt108) ? ABSOLUTE(__Interrupt108) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt109) ? ABSOLUTE(__AltInterrupt109) : + (DEFINED(__Interrupt109) ? ABSOLUTE(__Interrupt109) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt110) ? ABSOLUTE(__AltInterrupt110) : + (DEFINED(__Interrupt110) ? ABSOLUTE(__Interrupt110) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt111) ? ABSOLUTE(__AltInterrupt111) : + (DEFINED(__Interrupt111) ? ABSOLUTE(__Interrupt111) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt112) ? ABSOLUTE(__AltInterrupt112) : + (DEFINED(__Interrupt112) ? ABSOLUTE(__Interrupt112) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt113) ? ABSOLUTE(__AltInterrupt113) : + (DEFINED(__Interrupt113) ? ABSOLUTE(__Interrupt113) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt114) ? ABSOLUTE(__AltInterrupt114) : + (DEFINED(__Interrupt114) ? ABSOLUTE(__Interrupt114) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt115) ? ABSOLUTE(__AltInterrupt115) : + (DEFINED(__Interrupt115) ? ABSOLUTE(__Interrupt115) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt116) ? ABSOLUTE(__AltInterrupt116) : + (DEFINED(__Interrupt116) ? ABSOLUTE(__Interrupt116) : + ABSOLUTE(__DefaultInterrupt))); + LONG( DEFINED(__AltInterrupt117) ? ABSOLUTE(__AltInterrupt117) : + (DEFINED(__Interrupt117) ? ABSOLUTE(__Interrupt117) : + ABSOLUTE(__DefaultInterrupt))); + } >aivt +} /* SECTIONS */ + + +/* +** ============== Equates for SFR Addresses ============= +*/ + + WREG0 = 0x0; +_WREG0 = 0x0; + WREG1 = 0x2; +_WREG1 = 0x2; + WREG2 = 0x4; +_WREG2 = 0x4; + WREG3 = 0x6; +_WREG3 = 0x6; + WREG4 = 0x8; +_WREG4 = 0x8; + WREG5 = 0xA; +_WREG5 = 0xA; + WREG6 = 0xC; +_WREG6 = 0xC; + WREG7 = 0xE; +_WREG7 = 0xE; + WREG8 = 0x10; +_WREG8 = 0x10; + WREG9 = 0x12; +_WREG9 = 0x12; + WREG10 = 0x14; +_WREG10 = 0x14; + WREG11 = 0x16; +_WREG11 = 0x16; + WREG12 = 0x18; +_WREG12 = 0x18; + WREG13 = 0x1A; +_WREG13 = 0x1A; + WREG14 = 0x1C; +_WREG14 = 0x1C; + WREG15 = 0x1E; +_WREG15 = 0x1E; + SPLIM = 0x20; +_SPLIM = 0x20; + ACCAL = 0x22; +_ACCAL = 0x22; + ACCAH = 0x24; +_ACCAH = 0x24; + ACCAU = 0x26; +_ACCAU = 0x26; + ACCBL = 0x28; +_ACCBL = 0x28; + ACCBH = 0x2A; +_ACCBH = 0x2A; + ACCBU = 0x2C; +_ACCBU = 0x2C; + PCL = 0x2E; +_PCL = 0x2E; + PCH = 0x30; +_PCH = 0x30; + TBLPAG = 0x32; +_TBLPAG = 0x32; + PSVPAG = 0x34; +_PSVPAG = 0x34; + RCOUNT = 0x36; +_RCOUNT = 0x36; + DCOUNT = 0x38; +_DCOUNT = 0x38; + DOSTARTL = 0x3A; +_DOSTARTL = 0x3A; + DOSTARTH = 0x3C; +_DOSTARTH = 0x3C; + DOENDL = 0x3E; +_DOENDL = 0x3E; + DOENDH = 0x40; +_DOENDH = 0x40; + SR = 0x42; +_SR = 0x42; +_SRbits = 0x42; + CORCON = 0x44; +_CORCON = 0x44; +_CORCONbits = 0x44; + MODCON = 0x46; +_MODCON = 0x46; +_MODCONbits = 0x46; + XMODSRT = 0x48; +_XMODSRT = 0x48; + XMODEND = 0x4A; +_XMODEND = 0x4A; + YMODSRT = 0x4C; +_YMODSRT = 0x4C; + YMODEND = 0x4E; +_YMODEND = 0x4E; + XBREV = 0x50; +_XBREV = 0x50; +_XBREVbits = 0x50; + DISICNT = 0x52; +_DISICNT = 0x52; + CNEN1 = 0x60; +_CNEN1 = 0x60; +_CNEN1bits = 0x60; + CNEN2 = 0x62; +_CNEN2 = 0x62; +_CNEN2bits = 0x62; + CNPU1 = 0x68; +_CNPU1 = 0x68; +_CNPU1bits = 0x68; + CNPU2 = 0x6A; +_CNPU2 = 0x6A; +_CNPU2bits = 0x6A; + INTCON1 = 0x80; +_INTCON1 = 0x80; +_INTCON1bits = 0x80; + INTCON2 = 0x82; +_INTCON2 = 0x82; +_INTCON2bits = 0x82; + IFS0 = 0x84; +_IFS0 = 0x84; +_IFS0bits = 0x84; + IFS1 = 0x86; +_IFS1 = 0x86; +_IFS1bits = 0x86; + IFS2 = 0x88; +_IFS2 = 0x88; +_IFS2bits = 0x88; + IFS3 = 0x8A; +_IFS3 = 0x8A; +_IFS3bits = 0x8A; + IFS4 = 0x8C; +_IFS4 = 0x8C; +_IFS4bits = 0x8C; + IEC0 = 0x94; +_IEC0 = 0x94; +_IEC0bits = 0x94; + IEC1 = 0x96; +_IEC1 = 0x96; +_IEC1bits = 0x96; + IEC2 = 0x98; +_IEC2 = 0x98; +_IEC2bits = 0x98; + IEC3 = 0x9A; +_IEC3 = 0x9A; +_IEC3bits = 0x9A; + IEC4 = 0x9C; +_IEC4 = 0x9C; +_IEC4bits = 0x9C; + IPC0 = 0xA4; +_IPC0 = 0xA4; +_IPC0bits = 0xA4; + IPC1 = 0xA6; +_IPC1 = 0xA6; +_IPC1bits = 0xA6; + IPC2 = 0xA8; +_IPC2 = 0xA8; +_IPC2bits = 0xA8; + IPC3 = 0xAA; +_IPC3 = 0xAA; +_IPC3bits = 0xAA; + IPC4 = 0xAC; +_IPC4 = 0xAC; +_IPC4bits = 0xAC; + IPC5 = 0xAE; +_IPC5 = 0xAE; +_IPC5bits = 0xAE; + IPC6 = 0xB0; +_IPC6 = 0xB0; +_IPC6bits = 0xB0; + IPC7 = 0xB2; +_IPC7 = 0xB2; +_IPC7bits = 0xB2; + IPC8 = 0xB4; +_IPC8 = 0xB4; +_IPC8bits = 0xB4; + IPC9 = 0xB6; +_IPC9 = 0xB6; +_IPC9bits = 0xB6; + IPC10 = 0xB8; +_IPC10 = 0xB8; +_IPC10bits = 0xB8; + IPC11 = 0xBA; +_IPC11 = 0xBA; +_IPC11bits = 0xBA; + IPC12 = 0xBC; +_IPC12 = 0xBC; +_IPC12bits = 0xBC; + IPC13 = 0xBE; +_IPC13 = 0xBE; +_IPC13bits = 0xBE; + IPC14 = 0xC0; +_IPC14 = 0xC0; +_IPC14bits = 0xC0; + IPC15 = 0xC2; +_IPC15 = 0xC2; +_IPC15bits = 0xC2; + IPC16 = 0xC4; +_IPC16 = 0xC4; +_IPC16bits = 0xC4; + IPC17 = 0xC6; +_IPC17 = 0xC6; +_IPC17bits = 0xC6; + INTTREG = 0xE0; +_INTTREG = 0xE0; +_INTTREGbits = 0xE0; + TMR1 = 0x100; +_TMR1 = 0x100; + PR1 = 0x102; +_PR1 = 0x102; + T1CON = 0x104; +_T1CON = 0x104; +_T1CONbits = 0x104; + TMR2 = 0x106; +_TMR2 = 0x106; + TMR3HLD = 0x108; +_TMR3HLD = 0x108; + TMR3 = 0x10A; +_TMR3 = 0x10A; + PR2 = 0x10C; +_PR2 = 0x10C; + PR3 = 0x10E; +_PR3 = 0x10E; + T2CON = 0x110; +_T2CON = 0x110; +_T2CONbits = 0x110; + T3CON = 0x112; +_T3CON = 0x112; +_T3CONbits = 0x112; + TMR4 = 0x114; +_TMR4 = 0x114; + TMR5HLD = 0x116; +_TMR5HLD = 0x116; + TMR5 = 0x118; +_TMR5 = 0x118; + PR4 = 0x11A; +_PR4 = 0x11A; + PR5 = 0x11C; +_PR5 = 0x11C; + T4CON = 0x11E; +_T4CON = 0x11E; +_T4CONbits = 0x11E; + T5CON = 0x120; +_T5CON = 0x120; +_T5CONbits = 0x120; + TMR6 = 0x122; +_TMR6 = 0x122; + TMR7HLD = 0x124; +_TMR7HLD = 0x124; + TMR7 = 0x126; +_TMR7 = 0x126; + PR6 = 0x128; +_PR6 = 0x128; + PR7 = 0x12A; +_PR7 = 0x12A; + T6CON = 0x12C; +_T6CON = 0x12C; +_T6CONbits = 0x12C; + T7CON = 0x12E; +_T7CON = 0x12E; +_T7CONbits = 0x12E; + TMR8 = 0x130; +_TMR8 = 0x130; + TMR9HLD = 0x132; +_TMR9HLD = 0x132; + TMR9 = 0x134; +_TMR9 = 0x134; + PR8 = 0x136; +_PR8 = 0x136; + PR9 = 0x138; +_PR9 = 0x138; + T8CON = 0x13A; +_T8CON = 0x13A; +_T8CONbits = 0x13A; + T9CON = 0x13C; +_T9CON = 0x13C; +_T9CONbits = 0x13C; + IC1BUF = 0x140; +_IC1BUF = 0x140; + IC1CON = 0x142; +_IC1CON = 0x142; +_IC1CONbits = 0x142; + IC2BUF = 0x144; +_IC2BUF = 0x144; + IC2CON = 0x146; +_IC2CON = 0x146; +_IC2CONbits = 0x146; + IC3BUF = 0x148; +_IC3BUF = 0x148; + IC3CON = 0x14A; +_IC3CON = 0x14A; +_IC3CONbits = 0x14A; + IC4BUF = 0x14C; +_IC4BUF = 0x14C; + IC4CON = 0x14E; +_IC4CON = 0x14E; +_IC4CONbits = 0x14E; + IC5BUF = 0x150; +_IC5BUF = 0x150; + IC5CON = 0x152; +_IC5CON = 0x152; +_IC5CONbits = 0x152; + IC6BUF = 0x154; +_IC6BUF = 0x154; + IC6CON = 0x156; +_IC6CON = 0x156; +_IC6CONbits = 0x156; + IC7BUF = 0x158; +_IC7BUF = 0x158; + IC7CON = 0x15A; +_IC7CON = 0x15A; +_IC7CONbits = 0x15A; + IC8BUF = 0x15C; +_IC8BUF = 0x15C; + IC8CON = 0x15E; +_IC8CON = 0x15E; +_IC8CONbits = 0x15E; + OC1RS = 0x180; +_OC1RS = 0x180; + OC1R = 0x182; +_OC1R = 0x182; + OC1CON = 0x184; +_OC1CON = 0x184; +_OC1CONbits = 0x184; + OC2RS = 0x186; +_OC2RS = 0x186; + OC2R = 0x188; +_OC2R = 0x188; + OC2CON = 0x18A; +_OC2CON = 0x18A; +_OC2CONbits = 0x18A; + OC3RS = 0x18C; +_OC3RS = 0x18C; + OC3R = 0x18E; +_OC3R = 0x18E; + OC3CON = 0x190; +_OC3CON = 0x190; +_OC3CONbits = 0x190; + OC4RS = 0x192; +_OC4RS = 0x192; + OC4R = 0x194; +_OC4R = 0x194; + OC4CON = 0x196; +_OC4CON = 0x196; +_OC4CONbits = 0x196; + OC5RS = 0x198; +_OC5RS = 0x198; + OC5R = 0x19A; +_OC5R = 0x19A; + OC5CON = 0x19C; +_OC5CON = 0x19C; +_OC5CONbits = 0x19C; + OC6RS = 0x19E; +_OC6RS = 0x19E; + OC6R = 0x1A0; +_OC6R = 0x1A0; + OC6CON = 0x1A2; +_OC6CON = 0x1A2; +_OC6CONbits = 0x1A2; + OC7RS = 0x1A4; +_OC7RS = 0x1A4; + OC7R = 0x1A6; +_OC7R = 0x1A6; + OC7CON = 0x1A8; +_OC7CON = 0x1A8; +_OC7CONbits = 0x1A8; + OC8RS = 0x1AA; +_OC8RS = 0x1AA; + OC8R = 0x1AC; +_OC8R = 0x1AC; + OC8CON = 0x1AE; +_OC8CON = 0x1AE; +_OC8CONbits = 0x1AE; + I2C1RCV = 0x200; +_I2C1RCV = 0x200; + I2C1TRN = 0x202; +_I2C1TRN = 0x202; + I2C1BRG = 0x204; +_I2C1BRG = 0x204; + I2C1CON = 0x206; +_I2C1CON = 0x206; +_I2C1CONbits = 0x206; + I2C1STAT = 0x208; +_I2C1STAT = 0x208; +_I2C1STATbits = 0x208; + I2C1ADD = 0x20A; +_I2C1ADD = 0x20A; + I2C1MSK = 0x20C; +_I2C1MSK = 0x20C; + I2C2RCV = 0x210; +_I2C2RCV = 0x210; + I2C2TRN = 0x212; +_I2C2TRN = 0x212; + I2C2BRG = 0x214; +_I2C2BRG = 0x214; + I2C2CON = 0x216; +_I2C2CON = 0x216; +_I2C2CONbits = 0x216; + I2C2STAT = 0x218; +_I2C2STAT = 0x218; +_I2C2STATbits = 0x218; + I2C2ADD = 0x21A; +_I2C2ADD = 0x21A; + I2C2MSK = 0x21C; +_I2C2MSK = 0x21C; + U1MODE = 0x220; +_U1MODE = 0x220; +_U1MODEbits = 0x220; + U1STA = 0x222; +_U1STA = 0x222; +_U1STAbits = 0x222; + U1TXREG = 0x224; +_U1TXREG = 0x224; +_U1TXREGbits = 0x224; + U1RXREG = 0x226; +_U1RXREG = 0x226; +_U1RXREGbits = 0x226; + U1BRG = 0x228; +_U1BRG = 0x228; + U2MODE = 0x230; +_U2MODE = 0x230; +_U2MODEbits = 0x230; + U2STA = 0x232; +_U2STA = 0x232; +_U2STAbits = 0x232; + U2TXREG = 0x234; +_U2TXREG = 0x234; +_U2TXREGbits = 0x234; + U2RXREG = 0x236; +_U2RXREG = 0x236; +_U2RXREGbits = 0x236; + U2BRG = 0x238; +_U2BRG = 0x238; + SPI1STAT = 0x240; +_SPI1STAT = 0x240; +_SPI1STATbits = 0x240; + SPI1CON1 = 0x242; +_SPI1CON1 = 0x242; +_SPI1CON1bits = 0x242; + SPI1CON2 = 0x244; +_SPI1CON2 = 0x244; +_SPI1CON2bits = 0x244; + SPI1BUF = 0x248; +_SPI1BUF = 0x248; + SPI2STAT = 0x260; +_SPI2STAT = 0x260; +_SPI2STATbits = 0x260; + SPI2CON1 = 0x262; +_SPI2CON1 = 0x262; +_SPI2CON1bits = 0x262; + SPI2CON2 = 0x264; +_SPI2CON2 = 0x264; +_SPI2CON2bits = 0x264; + SPI2BUF = 0x268; +_SPI2BUF = 0x268; + DCICON1 = 0x280; +_DCICON1 = 0x280; +_DCICON1bits = 0x280; + DCICON2 = 0x282; +_DCICON2 = 0x282; +_DCICON2bits = 0x282; + DCICON3 = 0x284; +_DCICON3 = 0x284; +_DCICON3bits = 0x284; + DCISTAT = 0x286; +_DCISTAT = 0x286; +_DCISTATbits = 0x286; + TSCON = 0x288; +_TSCON = 0x288; +_TSCONbits = 0x288; + RSCON = 0x28C; +_RSCON = 0x28C; +_RSCONbits = 0x28C; + RXBUF0 = 0x290; +_RXBUF0 = 0x290; + RXBUF1 = 0x292; +_RXBUF1 = 0x292; + RXBUF2 = 0x294; +_RXBUF2 = 0x294; + RXBUF3 = 0x296; +_RXBUF3 = 0x296; + TXBUF0 = 0x298; +_TXBUF0 = 0x298; + TXBUF1 = 0x29A; +_TXBUF1 = 0x29A; + TXBUF2 = 0x29C; +_TXBUF2 = 0x29C; + TXBUF3 = 0x29E; +_TXBUF3 = 0x29E; + TRISA = 0x2C0; +_TRISA = 0x2C0; +_TRISAbits = 0x2C0; + PORTA = 0x2C2; +_PORTA = 0x2C2; +_PORTAbits = 0x2C2; + LATA = 0x2C4; +_LATA = 0x2C4; +_LATAbits = 0x2C4; + TRISB = 0x2C6; +_TRISB = 0x2C6; +_TRISBbits = 0x2C6; + PORTB = 0x2C8; +_PORTB = 0x2C8; +_PORTBbits = 0x2C8; + LATB = 0x2CA; +_LATB = 0x2CA; +_LATBbits = 0x2CA; + TRISC = 0x2CC; +_TRISC = 0x2CC; +_TRISCbits = 0x2CC; + PORTC = 0x2CE; +_PORTC = 0x2CE; +_PORTCbits = 0x2CE; + LATC = 0x2D0; +_LATC = 0x2D0; +_LATCbits = 0x2D0; + TRISD = 0x2D2; +_TRISD = 0x2D2; +_TRISDbits = 0x2D2; + PORTD = 0x2D4; +_PORTD = 0x2D4; +_PORTDbits = 0x2D4; + LATD = 0x2D6; +_LATD = 0x2D6; +_LATDbits = 0x2D6; + TRISE = 0x2D8; +_TRISE = 0x2D8; +_TRISEbits = 0x2D8; + PORTE = 0x2DA; +_PORTE = 0x2DA; +_PORTEbits = 0x2DA; + LATE = 0x2DC; +_LATE = 0x2DC; +_LATEbits = 0x2DC; + TRISF = 0x2DE; +_TRISF = 0x2DE; +_TRISFbits = 0x2DE; + PORTF = 0x2E0; +_PORTF = 0x2E0; +_PORTFbits = 0x2E0; + LATF = 0x2E2; +_LATF = 0x2E2; +_LATFbits = 0x2E2; + TRISG = 0x2E4; +_TRISG = 0x2E4; +_TRISGbits = 0x2E4; + PORTG = 0x2E6; +_PORTG = 0x2E6; +_PORTGbits = 0x2E6; + LATG = 0x2E8; +_LATG = 0x2E8; +_LATGbits = 0x2E8; + ADC1BUF0 = 0x300; +_ADC1BUF0 = 0x300; + AD1CON1 = 0x320; +_AD1CON1 = 0x320; +_AD1CON1bits = 0x320; + AD1CON2 = 0x322; +_AD1CON2 = 0x322; +_AD1CON2bits = 0x322; + AD1CON3 = 0x324; +_AD1CON3 = 0x324; +_AD1CON3bits = 0x324; + AD1CHS123 = 0x326; +_AD1CHS123 = 0x326; +_AD1CHS123bits = 0x326; + AD1CHS0 = 0x328; +_AD1CHS0 = 0x328; +_AD1CHS0bits = 0x328; + AD1PCFGH = 0x32A; +_AD1PCFGH = 0x32A; +_AD1PCFGHbits = 0x32A; + AD1PCFGL = 0x32C; +_AD1PCFGL = 0x32C; +_AD1PCFGLbits = 0x32C; + AD1CSSH = 0x32E; +_AD1CSSH = 0x32E; +_AD1CSSHbits = 0x32E; + AD1CSSL = 0x330; +_AD1CSSL = 0x330; +_AD1CSSLbits = 0x330; + AD1CON4 = 0x332; +_AD1CON4 = 0x332; +_AD1CON4bits = 0x332; + ADC2BUF0 = 0x340; +_ADC2BUF0 = 0x340; + AD2CON1 = 0x360; +_AD2CON1 = 0x360; +_AD2CON1bits = 0x360; + AD2CON2 = 0x362; +_AD2CON2 = 0x362; +_AD2CON2bits = 0x362; + AD2CON3 = 0x364; +_AD2CON3 = 0x364; +_AD2CON3bits = 0x364; + AD2CHS123 = 0x366; +_AD2CHS123 = 0x366; +_AD2CHS123bits = 0x366; + AD2CHS0 = 0x368; +_AD2CHS0 = 0x368; +_AD2CHS0bits = 0x368; + AD2PCFGL = 0x36C; +_AD2PCFGL = 0x36C; +_AD2PCFGLbits = 0x36C; + AD2CSSL = 0x370; +_AD2CSSL = 0x370; +_AD2CSSLbits = 0x370; + AD2CON4 = 0x372; +_AD2CON4 = 0x372; +_AD2CON4bits = 0x372; + DMA0CON = 0x380; +_DMA0CON = 0x380; +_DMA0CONbits = 0x380; + DMA0REQ = 0x382; +_DMA0REQ = 0x382; +_DMA0REQbits = 0x382; + DMA0STA = 0x384; +_DMA0STA = 0x384; + DMA0STB = 0x386; +_DMA0STB = 0x386; + DMA0PAD = 0x388; +_DMA0PAD = 0x388; + DMA0CNT = 0x38A; +_DMA0CNT = 0x38A; + DMA1CON = 0x38C; +_DMA1CON = 0x38C; +_DMA1CONbits = 0x38C; + DMA1REQ = 0x38E; +_DMA1REQ = 0x38E; +_DMA1REQbits = 0x38E; + DMA1STA = 0x390; +_DMA1STA = 0x390; + DMA1STB = 0x392; +_DMA1STB = 0x392; + DMA1PAD = 0x394; +_DMA1PAD = 0x394; + DMA1CNT = 0x396; +_DMA1CNT = 0x396; + DMA2CON = 0x398; +_DMA2CON = 0x398; +_DMA2CONbits = 0x398; + DMA2REQ = 0x39A; +_DMA2REQ = 0x39A; +_DMA2REQbits = 0x39A; + DMA2STA = 0x39C; +_DMA2STA = 0x39C; + DMA2STB = 0x39E; +_DMA2STB = 0x39E; + DMA2PAD = 0x3A0; +_DMA2PAD = 0x3A0; + DMA2CNT = 0x3A2; +_DMA2CNT = 0x3A2; + DMA3CON = 0x3A4; +_DMA3CON = 0x3A4; +_DMA3CONbits = 0x3A4; + DMA3REQ = 0x3A6; +_DMA3REQ = 0x3A6; +_DMA3REQbits = 0x3A6; + DMA3STA = 0x3A8; +_DMA3STA = 0x3A8; + DMA3STB = 0x3AA; +_DMA3STB = 0x3AA; + DMA3PAD = 0x3AC; +_DMA3PAD = 0x3AC; + DMA3CNT = 0x3AE; +_DMA3CNT = 0x3AE; + DMA4CON = 0x3B0; +_DMA4CON = 0x3B0; +_DMA4CONbits = 0x3B0; + DMA4REQ = 0x3B2; +_DMA4REQ = 0x3B2; +_DMA4REQbits = 0x3B2; + DMA4STA = 0x3B4; +_DMA4STA = 0x3B4; + DMA4STB = 0x3B6; +_DMA4STB = 0x3B6; + DMA4PAD = 0x3B8; +_DMA4PAD = 0x3B8; + DMA4CNT = 0x3BA; +_DMA4CNT = 0x3BA; + DMA5CON = 0x3BC; +_DMA5CON = 0x3BC; +_DMA5CONbits = 0x3BC; + DMA5REQ = 0x3BE; +_DMA5REQ = 0x3BE; +_DMA5REQbits = 0x3BE; + DMA5STA = 0x3C0; +_DMA5STA = 0x3C0; + DMA5STB = 0x3C2; +_DMA5STB = 0x3C2; + DMA5PAD = 0x3C4; +_DMA5PAD = 0x3C4; + DMA5CNT = 0x3C6; +_DMA5CNT = 0x3C6; + DMA6CON = 0x3C8; +_DMA6CON = 0x3C8; +_DMA6CONbits = 0x3C8; + DMA6REQ = 0x3CA; +_DMA6REQ = 0x3CA; +_DMA6REQbits = 0x3CA; + DMA6STA = 0x3CC; +_DMA6STA = 0x3CC; + DMA6STB = 0x3CE; +_DMA6STB = 0x3CE; + DMA6PAD = 0x3D0; +_DMA6PAD = 0x3D0; + DMA6CNT = 0x3D2; +_DMA6CNT = 0x3D2; + DMA7CON = 0x3D4; +_DMA7CON = 0x3D4; +_DMA7CONbits = 0x3D4; + DMA7REQ = 0x3D6; +_DMA7REQ = 0x3D6; +_DMA7REQbits = 0x3D6; + DMA7STA = 0x3D8; +_DMA7STA = 0x3D8; + DMA7STB = 0x3DA; +_DMA7STB = 0x3DA; + DMA7PAD = 0x3DC; +_DMA7PAD = 0x3DC; + DMA7CNT = 0x3DE; +_DMA7CNT = 0x3DE; + DMACS0 = 0x3E0; +_DMACS0 = 0x3E0; +_DMACS0bits = 0x3E0; + DMACS1 = 0x3E2; +_DMACS1 = 0x3E2; +_DMACS1bits = 0x3E2; + DSADR = 0x3E4; +_DSADR = 0x3E4; + C1CTRL1 = 0x400; +_C1CTRL1 = 0x400; +_C1CTRL1bits = 0x400; + C1CTRL2 = 0x402; +_C1CTRL2 = 0x402; +_C1CTRL2bits = 0x402; + C1VEC = 0x404; +_C1VEC = 0x404; +_C1VECbits = 0x404; + C1FCTRL = 0x406; +_C1FCTRL = 0x406; +_C1FCTRLbits = 0x406; + C1FIFO = 0x408; +_C1FIFO = 0x408; +_C1FIFObits = 0x408; + C1INTF = 0x40A; +_C1INTF = 0x40A; +_C1INTFbits = 0x40A; + C1INTE = 0x40C; +_C1INTE = 0x40C; +_C1INTEbits = 0x40C; + C1EC = 0x40E; +_C1EC = 0x40E; +_C1ECbits = 0x40E; + C1RERRCNT = 0x40E; +_C1RERRCNT = 0x40E; + C1TERRCNT = 0x40F; +_C1TERRCNT = 0x40F; + C1CFG1 = 0x410; +_C1CFG1 = 0x410; +_C1CFG1bits = 0x410; + C1CFG2 = 0x412; +_C1CFG2 = 0x412; +_C1CFG2bits = 0x412; + C1FEN1 = 0x414; +_C1FEN1 = 0x414; +_C1FEN1bits = 0x414; + C1FMSKSEL1 = 0x418; +_C1FMSKSEL1 = 0x418; +_C1FMSKSEL1bits = 0x418; + C1FMSKSEL2 = 0x41A; +_C1FMSKSEL2 = 0x41A; +_C1FMSKSEL2bits = 0x41A; + C1BUFPNT1 = 0x420; +_C1BUFPNT1 = 0x420; +_C1BUFPNT1bits = 0x420; + C1RXFUL1 = 0x420; +_C1RXFUL1 = 0x420; +_C1RXFUL1bits = 0x420; + C1BUFPNT2 = 0x422; +_C1BUFPNT2 = 0x422; +_C1BUFPNT2bits = 0x422; + C1RXFUL2 = 0x422; +_C1RXFUL2 = 0x422; +_C1RXFUL2bits = 0x422; + C1BUFPNT3 = 0x424; +_C1BUFPNT3 = 0x424; +_C1BUFPNT3bits = 0x424; + C1BUFPNT4 = 0x426; +_C1BUFPNT4 = 0x426; +_C1BUFPNT4bits = 0x426; + C1RXOVF1 = 0x428; +_C1RXOVF1 = 0x428; +_C1RXOVF1bits = 0x428; + C1RXOVF2 = 0x42A; +_C1RXOVF2 = 0x42A; +_C1RXOVF2bits = 0x42A; + C1RXM0SID = 0x430; +_C1RXM0SID = 0x430; +_C1RXM0SIDbits = 0x430; + C1TR01CON = 0x430; +_C1TR01CON = 0x430; +_C1TR01CONbits = 0x430; + C1RXM0EID = 0x432; +_C1RXM0EID = 0x432; +_C1RXM0EIDbits = 0x432; + C1TR23CON = 0x432; +_C1TR23CON = 0x432; +_C1TR23CONbits = 0x432; + C1RXM1SID = 0x434; +_C1RXM1SID = 0x434; +_C1RXM1SIDbits = 0x434; + C1TR45CON = 0x434; +_C1TR45CON = 0x434; +_C1TR45CONbits = 0x434; + C1RXM1EID = 0x436; +_C1RXM1EID = 0x436; +_C1RXM1EIDbits = 0x436; + C1TR67CON = 0x436; +_C1TR67CON = 0x436; +_C1TR67CONbits = 0x436; + C1RXM2SID = 0x438; +_C1RXM2SID = 0x438; +_C1RXM2SIDbits = 0x438; + C1RXM2EID = 0x43A; +_C1RXM2EID = 0x43A; +_C1RXM2EIDbits = 0x43A; + C1RXD = 0x440; +_C1RXD = 0x440; + C1RXF0SID = 0x440; +_C1RXF0SID = 0x440; +_C1RXF0SIDbits = 0x440; + C1RXF0EID = 0x442; +_C1RXF0EID = 0x442; +_C1RXF0EIDbits = 0x442; + C1TXD = 0x442; +_C1TXD = 0x442; + C1RXF1SID = 0x444; +_C1RXF1SID = 0x444; +_C1RXF1SIDbits = 0x444; + C1RXF1EID = 0x446; +_C1RXF1EID = 0x446; +_C1RXF1EIDbits = 0x446; + C1RXF2SID = 0x448; +_C1RXF2SID = 0x448; +_C1RXF2SIDbits = 0x448; + C1RXF2EID = 0x44A; +_C1RXF2EID = 0x44A; +_C1RXF2EIDbits = 0x44A; + C1RXF3SID = 0x44C; +_C1RXF3SID = 0x44C; +_C1RXF3SIDbits = 0x44C; + C1RXF3EID = 0x44E; +_C1RXF3EID = 0x44E; +_C1RXF3EIDbits = 0x44E; + C1RXF4SID = 0x450; +_C1RXF4SID = 0x450; +_C1RXF4SIDbits = 0x450; + C1RXF4EID = 0x452; +_C1RXF4EID = 0x452; +_C1RXF4EIDbits = 0x452; + C1RXF5SID = 0x454; +_C1RXF5SID = 0x454; +_C1RXF5SIDbits = 0x454; + C1RXF5EID = 0x456; +_C1RXF5EID = 0x456; +_C1RXF5EIDbits = 0x456; + C1RXF6SID = 0x458; +_C1RXF6SID = 0x458; +_C1RXF6SIDbits = 0x458; + C1RXF6EID = 0x45A; +_C1RXF6EID = 0x45A; +_C1RXF6EIDbits = 0x45A; + C1RXF7SID = 0x45C; +_C1RXF7SID = 0x45C; +_C1RXF7SIDbits = 0x45C; + C1RXF7EID = 0x45E; +_C1RXF7EID = 0x45E; +_C1RXF7EIDbits = 0x45E; + C1RXF8SID = 0x460; +_C1RXF8SID = 0x460; +_C1RXF8SIDbits = 0x460; + C1RXF8EID = 0x462; +_C1RXF8EID = 0x462; +_C1RXF8EIDbits = 0x462; + C1RXF9SID = 0x464; +_C1RXF9SID = 0x464; +_C1RXF9SIDbits = 0x464; + C1RXF9EID = 0x466; +_C1RXF9EID = 0x466; +_C1RXF9EIDbits = 0x466; + C1RXF10SID = 0x468; +_C1RXF10SID = 0x468; +_C1RXF10SIDbits = 0x468; + C1RXF10EID = 0x46A; +_C1RXF10EID = 0x46A; +_C1RXF10EIDbits = 0x46A; + C1RXF11SID = 0x46C; +_C1RXF11SID = 0x46C; +_C1RXF11SIDbits = 0x46C; + C1RXF11EID = 0x46E; +_C1RXF11EID = 0x46E; +_C1RXF11EIDbits = 0x46E; + C1RXF12SID = 0x470; +_C1RXF12SID = 0x470; +_C1RXF12SIDbits = 0x470; + C1RXF12EID = 0x472; +_C1RXF12EID = 0x472; +_C1RXF12EIDbits = 0x472; + C1RXF13SID = 0x474; +_C1RXF13SID = 0x474; +_C1RXF13SIDbits = 0x474; + C1RXF13EID = 0x476; +_C1RXF13EID = 0x476; +_C1RXF13EIDbits = 0x476; + C1RXF14SID = 0x478; +_C1RXF14SID = 0x478; +_C1RXF14SIDbits = 0x478; + C1RXF14EID = 0x47A; +_C1RXF14EID = 0x47A; +_C1RXF14EIDbits = 0x47A; + C1RXF15SID = 0x47C; +_C1RXF15SID = 0x47C; +_C1RXF15SIDbits = 0x47C; + C1RXF15EID = 0x47E; +_C1RXF15EID = 0x47E; +_C1RXF15EIDbits = 0x47E; + C2CTRL1 = 0x500; +_C2CTRL1 = 0x500; +_C2CTRL1bits = 0x500; + C2CTRL2 = 0x502; +_C2CTRL2 = 0x502; +_C2CTRL2bits = 0x502; + C2VEC = 0x504; +_C2VEC = 0x504; +_C2VECbits = 0x504; + C2FCTRL = 0x506; +_C2FCTRL = 0x506; +_C2FCTRLbits = 0x506; + C2FIFO = 0x508; +_C2FIFO = 0x508; +_C2FIFObits = 0x508; + C2INTF = 0x50A; +_C2INTF = 0x50A; +_C2INTFbits = 0x50A; + C2INTE = 0x50C; +_C2INTE = 0x50C; +_C2INTEbits = 0x50C; + C2EC = 0x50E; +_C2EC = 0x50E; +_C2ECbits = 0x50E; + C2RERRCNT = 0x50E; +_C2RERRCNT = 0x50E; + C2TERRCNT = 0x50F; +_C2TERRCNT = 0x50F; + C2CFG1 = 0x510; +_C2CFG1 = 0x510; +_C2CFG1bits = 0x510; + C2CFG2 = 0x512; +_C2CFG2 = 0x512; +_C2CFG2bits = 0x512; + C2FEN1 = 0x514; +_C2FEN1 = 0x514; +_C2FEN1bits = 0x514; + C2FMSKSEL1 = 0x518; +_C2FMSKSEL1 = 0x518; +_C2FMSKSEL1bits = 0x518; + C2FMSKSEL2 = 0x51A; +_C2FMSKSEL2 = 0x51A; +_C2FMSKSEL2bits = 0x51A; + C2BUFPNT1 = 0x520; +_C2BUFPNT1 = 0x520; +_C2BUFPNT1bits = 0x520; + C2RXFUL1 = 0x520; +_C2RXFUL1 = 0x520; +_C2RXFUL1bits = 0x520; + C2BUFPNT2 = 0x522; +_C2BUFPNT2 = 0x522; +_C2BUFPNT2bits = 0x522; + C2RXFUL2 = 0x522; +_C2RXFUL2 = 0x522; +_C2RXFUL2bits = 0x522; + C2BUFPNT3 = 0x524; +_C2BUFPNT3 = 0x524; +_C2BUFPNT3bits = 0x524; + C2BUFPNT4 = 0x526; +_C2BUFPNT4 = 0x526; +_C2BUFPNT4bits = 0x526; + C2RXOVF1 = 0x528; +_C2RXOVF1 = 0x528; +_C2RXOVF1bits = 0x528; + C2RXOVF2 = 0x52A; +_C2RXOVF2 = 0x52A; +_C2RXOVF2bits = 0x52A; + C2RXM0SID = 0x530; +_C2RXM0SID = 0x530; +_C2RXM0SIDbits = 0x530; + C2TR01CON = 0x530; +_C2TR01CON = 0x530; +_C2TR01CONbits = 0x530; + C2RXM0EID = 0x532; +_C2RXM0EID = 0x532; +_C2RXM0EIDbits = 0x532; + C2TR23CON = 0x532; +_C2TR23CON = 0x532; +_C2TR23CONbits = 0x532; + C2RXM1SID = 0x534; +_C2RXM1SID = 0x534; +_C2RXM1SIDbits = 0x534; + C2TR45CON = 0x534; +_C2TR45CON = 0x534; +_C2TR45CONbits = 0x534; + C2RXM1EID = 0x536; +_C2RXM1EID = 0x536; +_C2RXM1EIDbits = 0x536; + C2TR67CON = 0x536; +_C2TR67CON = 0x536; +_C2TR67CONbits = 0x536; + C2RXM2SID = 0x538; +_C2RXM2SID = 0x538; +_C2RXM2SIDbits = 0x538; + C2RXM2EID = 0x53A; +_C2RXM2EID = 0x53A; +_C2RXM2EIDbits = 0x53A; + C2RXD = 0x540; +_C2RXD = 0x540; + C2RXF0SID = 0x540; +_C2RXF0SID = 0x540; +_C2RXF0SIDbits = 0x540; + C2RXF0EID = 0x542; +_C2RXF0EID = 0x542; +_C2RXF0EIDbits = 0x542; + C2TXD = 0x542; +_C2TXD = 0x542; + C2RXF1SID = 0x544; +_C2RXF1SID = 0x544; +_C2RXF1SIDbits = 0x544; + C2RXF1EID = 0x546; +_C2RXF1EID = 0x546; +_C2RXF1EIDbits = 0x546; + C2RXF2SID = 0x548; +_C2RXF2SID = 0x548; +_C2RXF2SIDbits = 0x548; + C2RXF2EID = 0x54A; +_C2RXF2EID = 0x54A; +_C2RXF2EIDbits = 0x54A; + C2RXF3SID = 0x54C; +_C2RXF3SID = 0x54C; +_C2RXF3SIDbits = 0x54C; + C2RXF3EID = 0x54E; +_C2RXF3EID = 0x54E; +_C2RXF3EIDbits = 0x54E; + C2RXF4SID = 0x550; +_C2RXF4SID = 0x550; +_C2RXF4SIDbits = 0x550; + C2RXF4EID = 0x552; +_C2RXF4EID = 0x552; +_C2RXF4EIDbits = 0x552; + C2RXF5SID = 0x554; +_C2RXF5SID = 0x554; +_C2RXF5SIDbits = 0x554; + C2RXF5EID = 0x556; +_C2RXF5EID = 0x556; +_C2RXF5EIDbits = 0x556; + C2RXF6SID = 0x558; +_C2RXF6SID = 0x558; +_C2RXF6SIDbits = 0x558; + C2RXF6EID = 0x55A; +_C2RXF6EID = 0x55A; +_C2RXF6EIDbits = 0x55A; + C2RXF7SID = 0x55C; +_C2RXF7SID = 0x55C; +_C2RXF7SIDbits = 0x55C; + C2RXF7EID = 0x55E; +_C2RXF7EID = 0x55E; +_C2RXF7EIDbits = 0x55E; + C2RXF8SID = 0x560; +_C2RXF8SID = 0x560; +_C2RXF8SIDbits = 0x560; + C2RXF8EID = 0x562; +_C2RXF8EID = 0x562; +_C2RXF8EIDbits = 0x562; + C2RXF9SID = 0x564; +_C2RXF9SID = 0x564; +_C2RXF9SIDbits = 0x564; + C2RXF9EID = 0x566; +_C2RXF9EID = 0x566; +_C2RXF9EIDbits = 0x566; + C2RXF10SID = 0x568; +_C2RXF10SID = 0x568; +_C2RXF10SIDbits = 0x568; + C2RXF10EID = 0x56A; +_C2RXF10EID = 0x56A; +_C2RXF10EIDbits = 0x56A; + C2RXF11SID = 0x56C; +_C2RXF11SID = 0x56C; +_C2RXF11SIDbits = 0x56C; + C2RXF11EID = 0x56E; +_C2RXF11EID = 0x56E; +_C2RXF11EIDbits = 0x56E; + C2RXF12SID = 0x570; +_C2RXF12SID = 0x570; +_C2RXF12SIDbits = 0x570; + C2RXF12EID = 0x572; +_C2RXF12EID = 0x572; +_C2RXF12EIDbits = 0x572; + C2RXF13SID = 0x574; +_C2RXF13SID = 0x574; +_C2RXF13SIDbits = 0x574; + C2RXF13EID = 0x576; +_C2RXF13EID = 0x576; +_C2RXF13EIDbits = 0x576; + C2RXF14SID = 0x578; +_C2RXF14SID = 0x578; +_C2RXF14SIDbits = 0x578; + C2RXF14EID = 0x57A; +_C2RXF14EID = 0x57A; +_C2RXF14EIDbits = 0x57A; + C2RXF15SID = 0x57C; +_C2RXF15SID = 0x57C; +_C2RXF15SIDbits = 0x57C; + C2RXF15EID = 0x57E; +_C2RXF15EID = 0x57E; +_C2RXF15EIDbits = 0x57E; + ODCA = 0x6C0; +_ODCA = 0x6C0; +_ODCAbits = 0x6C0; + ODCD = 0x6D2; +_ODCD = 0x6D2; +_ODCDbits = 0x6D2; + ODCF = 0x6DE; +_ODCF = 0x6DE; +_ODCFbits = 0x6DE; + ODCG = 0x6E4; +_ODCG = 0x6E4; +_ODCGbits = 0x6E4; + RCON = 0x740; +_RCON = 0x740; +_RCONbits = 0x740; + OSCCON = 0x742; +_OSCCON = 0x742; +_OSCCONbits = 0x742; + CLKDIV = 0x744; +_CLKDIV = 0x744; +_CLKDIVbits = 0x744; + PLLFBD = 0x746; +_PLLFBD = 0x746; +_PLLFBDbits = 0x746; + OSCTUN = 0x748; +_OSCTUN = 0x748; +_OSCTUNbits = 0x748; + BSRAM = 0x750; +_BSRAM = 0x750; +_BSRAMbits = 0x750; + SSRAM = 0x752; +_SSRAM = 0x752; +_SSRAMbits = 0x752; + NVMCON = 0x760; +_NVMCON = 0x760; +_NVMCONbits = 0x760; + NVMKEY = 0x766; +_NVMKEY = 0x766; + PMD1 = 0x770; +_PMD1 = 0x770; +_PMD1bits = 0x770; + PMD2 = 0x772; +_PMD2 = 0x772; +_PMD2bits = 0x772; + PMD3 = 0x774; +_PMD3 = 0x774; +_PMD3bits = 0x774; diff --git a/20080212/Demo/dsPIC_MPLAB/serial/serial.c b/20080212/Demo/dsPIC_MPLAB/serial/serial.c new file mode 100644 index 000000000..7846e92bb --- /dev/null +++ b/20080212/Demo/dsPIC_MPLAB/serial/serial.c @@ -0,0 +1,241 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER. + +NOTE: This driver is primarily to test the scheduler functionality. It does +not effectively use the buffers or DMA and is therefore not intended to be +an example of an efficient driver. */ + +/* Standard include file. */ +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "queue.h" +#include "task.h" + +/* Demo app include files. */ +#include "serial.h" + +/* Hardware setup. */ +#define serOUTPUT 0 +#define serINPUT 1 +#define serLOW_SPEED 0 +#define serONE_STOP_BIT 0 +#define serEIGHT_DATA_BITS_NO_PARITY 0 +#define serNORMAL_IDLE_STATE 0 +#define serAUTO_BAUD_OFF 0 +#define serLOOPBACK_OFF 0 +#define serWAKE_UP_DISABLE 0 +#define serNO_HARDWARE_FLOW_CONTROL 0 +#define serSTANDARD_IO 0 +#define serNO_IRDA 0 +#define serCONTINUE_IN_IDLE_MODE 0 +#define serUART_ENABLED 1 +#define serINTERRUPT_ON_SINGLE_CHAR 0 +#define serTX_ENABLE 1 +#define serINTERRUPT_ENABLE 1 +#define serINTERRUPT_DISABLE 0 +#define serCLEAR_FLAG 0 +#define serSET_FLAG 1 + + +/* The queues used to communicate between tasks and ISR's. */ +static xQueueHandle xRxedChars; +static xQueueHandle xCharsForTx; + +static portBASE_TYPE xTxHasEnded; +/*-----------------------------------------------------------*/ + +xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) +{ +portCHAR cChar; + + /* Create the queues used by the com test task. */ + xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + + /* Setup the UART. */ + U2MODEbits.BRGH = serLOW_SPEED; + U2MODEbits.STSEL = serONE_STOP_BIT; + U2MODEbits.PDSEL = serEIGHT_DATA_BITS_NO_PARITY; + U2MODEbits.ABAUD = serAUTO_BAUD_OFF; + U2MODEbits.LPBACK = serLOOPBACK_OFF; + U2MODEbits.WAKE = serWAKE_UP_DISABLE; + U2MODEbits.UEN = serNO_HARDWARE_FLOW_CONTROL; + U2MODEbits.IREN = serNO_IRDA; + U2MODEbits.USIDL = serCONTINUE_IN_IDLE_MODE; + U2MODEbits.UARTEN = serUART_ENABLED; + + U2BRG = (unsigned portSHORT)(( (float)configCPU_CLOCK_HZ / ( (float)16 * (float)ulWantedBaud ) ) - (float)0.5); + + U2STAbits.URXISEL = serINTERRUPT_ON_SINGLE_CHAR; + U2STAbits.UTXEN = serTX_ENABLE; + U2STAbits.UTXINV = serNORMAL_IDLE_STATE; + U2STAbits.UTXISEL0 = serINTERRUPT_ON_SINGLE_CHAR; + U2STAbits.UTXISEL1 = serINTERRUPT_ON_SINGLE_CHAR; + + /* It is assumed that this function is called prior to the scheduler being + started. Therefore interrupts must not be allowed to occur yet as they + may attempt to perform a context switch. */ + portDISABLE_INTERRUPTS(); + + IFS1bits.U2RXIF = serCLEAR_FLAG; + IFS1bits.U2TXIF = serCLEAR_FLAG; + IPC7bits.U2RXIP = configKERNEL_INTERRUPT_PRIORITY; + IPC7bits.U2TXIP = configKERNEL_INTERRUPT_PRIORITY; + IEC1bits.U2TXIE = serINTERRUPT_ENABLE; + IEC1bits.U2RXIE = serINTERRUPT_ENABLE; + + /* Clear the Rx buffer. */ + while( U2STAbits.URXDA == serSET_FLAG ) + { + cChar = U2RXREG; + } + + xTxHasEnded = pdTRUE; + + return NULL; +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) +{ + /* Only one port is supported. */ + ( void ) pxPort; + + /* Get the next character from the buffer. Return false if no characters + are available or arrive before xBlockTime expires. */ + if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) + { + return pdTRUE; + } + else + { + return pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) +{ + /* Only one port is supported. */ + ( void ) pxPort; + + /* Return false if after the block time there is no room on the Tx queue. */ + if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) + { + return pdFAIL; + } + + /* A critical section should not be required as xTxHasEnded will not be + written to by the ISR if it is already 0 (is this correct?). */ + if( xTxHasEnded ) + { + xTxHasEnded = pdFALSE; + IFS1bits.U2TXIF = serSET_FLAG; + } + + return pdPASS; +} +/*-----------------------------------------------------------*/ + +void vSerialClose( xComPortHandle xPort ) +{ +} +/*-----------------------------------------------------------*/ + +void __attribute__((__interrupt__, auto_psv)) _U2RXInterrupt( void ) +{ +portCHAR cChar; +portBASE_TYPE xYieldRequired = pdFALSE; + + /* Get the character and post it on the queue of Rxed characters. + If the post causes a task to wake force a context switch as the woken task + may have a higher priority than the task we have interrupted. */ + IFS1bits.U2RXIF = serCLEAR_FLAG; + while( U2STAbits.URXDA ) + { + cChar = U2RXREG; + xYieldRequired = xQueueSendFromISR( xRxedChars, &cChar, xYieldRequired ); + } + + if( xYieldRequired != pdFALSE ) + { + taskYIELD(); + } +} +/*-----------------------------------------------------------*/ + +void __attribute__((__interrupt__, auto_psv)) _U2TXInterrupt( void ) +{ +signed portCHAR cChar; +portBASE_TYPE xTaskWoken = pdFALSE; + + /* If the transmit buffer is full we cannot get the next character. + Another interrupt will occur the next time there is space so this does + not matter. */ + IFS1bits.U2TXIF = serCLEAR_FLAG; + while( !( U2STAbits.UTXBF ) ) + { + if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWoken ) == pdTRUE ) + { + /* Send the next character queued for Tx. */ + U2TXREG = cChar; + } + else + { + /* Queue empty, nothing to send. */ + xTxHasEnded = pdTRUE; + break; + } + } + + if( xTaskWoken != pdFALSE ) + { + taskYIELD(); + } +} + + diff --git a/20080212/Demo/dsPIC_MPLAB/timertest.c b/20080212/Demo/dsPIC_MPLAB/timertest.c new file mode 100644 index 000000000..cb36ab2f5 --- /dev/null +++ b/20080212/Demo/dsPIC_MPLAB/timertest.c @@ -0,0 +1,151 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* High speed timer test as described in main.c. */ + + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* Demo includes. */ +#include "partest.h" + +/* The number of interrupts to pass before we start looking at the jitter. */ +#define timerSETTLE_TIME 5 + +/* The maximum value the 16bit timer can contain. */ +#define timerMAX_COUNT 0xffff + +/*-----------------------------------------------------------*/ + +/* + * Measure the time between this interrupt and the previous interrupt to + * calculate the timing jitter. Remember the maximum value the jitter has + * ever been calculated to be. + */ +static void prvCalculateAndStoreJitter( void ); + +/*-----------------------------------------------------------*/ + +/* The maximum time (in processor clocks) between two consecutive timer +interrupts so far. */ +unsigned portSHORT usMaxJitter = 0; + +/*-----------------------------------------------------------*/ + +void vSetupTimerTest( unsigned portSHORT usFrequencyHz ) +{ + /* T2 is used to generate interrupts. T4 is used to provide an accurate + time measurement. */ + T2CON = 0; + T4CON = 0; + TMR2 = 0; + TMR4 = 0; + + /* Timer 2 is going to interrupt at usFrequencyHz Hz. */ + PR2 = ( unsigned portSHORT ) ( configCPU_CLOCK_HZ / ( unsigned portLONG ) usFrequencyHz ); + + /* Timer 4 is going to free run from minimum to maximum value. */ + PR4 = ( unsigned portSHORT ) timerMAX_COUNT; + + /* Setup timer 2 interrupt priority to be above the kernel priority so + the timer jitter is not effected by the kernel activity. */ + IPC1bits.T2IP = configKERNEL_INTERRUPT_PRIORITY + 1; + + /* Clear the interrupt as a starting condition. */ + IFS0bits.T2IF = 0; + + /* Enable the interrupt. */ + IEC0bits.T2IE = 1; + + /* Start both timers. */ + T2CONbits.TON = 1; + T4CONbits.TON = 1; +} +/*-----------------------------------------------------------*/ + +static void prvCalculateAndStoreJitter( void ) +{ +static unsigned portSHORT usLastCount = 0, usSettleCount = 0; +unsigned portSHORT usThisCount, usDifference; + + /* Capture the timer value as we enter the interrupt. */ + usThisCount = TMR4; + + if( usSettleCount >= timerSETTLE_TIME ) + { + /* What is the difference between the timer value in this interrupt + and the value from the last interrupt. */ + usDifference = usThisCount - usLastCount; + + /* Store the difference in the timer values if it is larger than the + currently stored largest value. The difference over and above the + expected difference will give the 'jitter' in the processing of these + interrupts. */ + if( usDifference > usMaxJitter ) + { + usMaxJitter = usDifference; + } + } + else + { + /* Don't bother storing any values for the first couple of + interrupts. */ + usSettleCount++; + } + + /* Remember what the timer value was this time through, so we can calculate + the difference the next time through. */ + usLastCount = usThisCount; +} +/*-----------------------------------------------------------*/ + +void __attribute__((__interrupt__, auto_psv)) _T2Interrupt( void ) +{ + /* Work out the time between this and the previous interrupt. */ + prvCalculateAndStoreJitter(); + + /* Clear the timer interrupt. */ + IFS0bits.T2IF = 0; +} + + diff --git a/20080212/Demo/dsPIC_MPLAB/timertest.h b/20080212/Demo/dsPIC_MPLAB/timertest.h new file mode 100644 index 000000000..a8c060386 --- /dev/null +++ b/20080212/Demo/dsPIC_MPLAB/timertest.h @@ -0,0 +1,52 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef TIMER_TEST_H +#define TIMER_TEST_H + +/* Setup the high frequency timer interrupt. */ +void vSetupTimerTest( unsigned portSHORT usFrequencyHz ); + +#endif /* TIMER_TEST_H */ + + + diff --git a/20080212/Demo/lwIP_AVR32_UC3/AT32UC3A/GCC/Makefile b/20080212/Demo/lwIP_AVR32_UC3/AT32UC3A/GCC/Makefile new file mode 100644 index 000000000..6f51ddb10 --- /dev/null +++ b/20080212/Demo/lwIP_AVR32_UC3/AT32UC3A/GCC/Makefile @@ -0,0 +1,618 @@ +# Hey Emacs, this is a -*- makefile -*- + +# Goals available on make command line: +# +# [all] Default goal: build the project. +# clean Clean up the project. +# rebuild Rebuild the project. +# ccversion Display CC version information. +# cppfiles file.i Generate preprocessed files from C source files. +# asfiles file.x Generate preprocessed assembler files from C and assembler source files. +# objfiles file.o Generate object files from C and assembler source files. +# a file.a Archive: create A output file from object files. +# elf file.elf Link: create ELF output file from object files. +# lss file.lss Create extended listing from target output file. +# sym file.sym Create symbol table from target output file. +# hex file.hex Create Intel HEX image from ELF output file. +# bin file.bin Create binary image from ELF output file. +# sizes Display target size information. +# isp Use ISP instead of JTAGICE mkII when programming. +# cpuinfo Get CPU information. +# halt Stop CPU execution. +# chiperase Perform a JTAG Chip Erase command. +# erase Perform a flash chip erase. +# program Program MCU memory from ELF output file. +# secureflash Protect chip by setting security bit. +# reset Reset MCU. +# debug Open a debug connection with the MCU. +# run Start CPU execution. +# readregs Read CPU registers. +# doc Build the documentation. +# cleandoc Clean up the documentation. +# rebuilddoc Rebuild the documentation. +# verbose Display main executed commands. + +# Copyright (c) 2007, Atmel Corporation All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation and/ +# or other materials provided with the distribution. +# +# 3. The name of ATMEL may not be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND +# SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, +# INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +# OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + +# ** ** ** *** ** ** ** ** ** ** ** ** ** ** ** +# ENVIRONMENT SETTINGS +# ** ** ** *** ** ** ** ** ** ** ** ** ** ** ** + +FirstWord = $(if $(1),$(word 1,$(1))) +LastWord = $(if $(1),$(word $(words $(1)),$(1))) + +MAKE = make +MAKECFG = config.mk +TGTTYPE = $(suffix $(TARGET)) + +RM = rm -Rf + +AR = avr32-ar +ARFLAGS = rcs + +CPP = $(CC) -E +CPPFLAGS = -march=$(ARCH) -mpart=$(PART) $(WARNINGS) $(DEFS) \ + $(PLATFORM_INC_PATH:%=-I%) $(INC_PATH:%=-I%) $(CPP_EXTRA_FLAGS) +DPNDFILES = $(CSRCS:.c=.d) $(ASSRCS:.S=.d) +CPPFILES = $(CSRCS:.c=.i) + +CC = avr32-gcc +CFLAGS = $(DEBUG) $(OPTIMIZATION) $(C_EXTRA_FLAGS) \ + $(PLATFORM_INC_PATH:%=-Wa,-I%) $(INC_PATH:%=-Wa,-I%) $(AS_EXTRA_FLAGS) +ASFILES = $(CSRCS:.c=.x) $(ASSRCS:.S=.x) + +AS = avr32-as +ASFLAGS = $(DEBUG) \ + $(PLATFORM_INC_PATH:%=-Wa,-I%) $(INC_PATH:%=-Wa,-I%) $(AS_EXTRA_FLAGS) +OBJFILES = $(CSRCS:.c=.o) $(ASSRCS:.S=.o) + +LD = avr32-ld +LDFLAGS = -march=$(ARCH) -mpart=$(PART) \ + $(LIB_PATH:%=-L%) $(LINKER_SCRIPT:%=-T%) $(LD_EXTRA_FLAGS) +LOADLIBES = +LDLIBS = $(LIBS:%=-l%) + +OBJDUMP = avr32-objdump +LSS = $(TARGET:$(TGTTYPE)=.lss) + +NM = avr32-nm +SYM = $(TARGET:$(TGTTYPE)=.sym) + +OBJCOPY = avr32-objcopy +HEX = $(TARGET:$(TGTTYPE)=.hex) +BIN = $(TARGET:$(TGTTYPE)=.bin) + +SIZE = avr32-size + +SLEEP = sleep +SLEEPUSB = 9 + +PROGRAM = avr32program + +ISP = batchisp +ISPFLAGS = -device at32$(PART) -hardware usb -operation + +DBGPROXY = avr32gdbproxy + +DOCGEN = doxygen + + +# ** ** ** *** ** ** ** ** ** ** ** ** ** ** ** +# MESSAGES +# ** ** ** *** ** ** ** ** ** ** ** ** ** ** ** + +ERR_TARGET_TYPE = Target type not supported: `$(TGTTYPE)' +MSG_CLEANING = Cleaning project. +MSG_PREPROCESSING = Preprocessing \`$<\' to \`$@\'. +MSG_COMPILING = Compiling \`$<\' to \`$@\'. +MSG_ASSEMBLING = Assembling \`$<\' to \`$@\'. +MSG_ARCHIVING = Archiving to \`$@\'. +MSG_LINKING = Linking to \`$@\'. +MSG_EXTENDED_LISTING = Creating extended listing to \`$@\'. +MSG_SYMBOL_TABLE = Creating symbol table to \`$@\'. +MSG_IHEX_IMAGE = Creating Intel HEX image to \`$@\'. +MSG_BINARY_IMAGE = Creating binary image to \`$@\'. +MSG_GETTING_CPU_INFO = Getting CPU information. +MSG_HALTING = Stopping CPU execution. +MSG_ERASING_CHIP = Performing a JTAG Chip Erase command. +MSG_ERASING = Performing a flash chip erase. +MSG_PROGRAMMING = Programming MCU memory from \`$(TARGET)\'. +MSG_SECURING_FLASH = Protecting chip by setting security bit. +MSG_RESETTING = Resetting MCU. +MSG_DEBUGGING = Opening debug connection with MCU. +MSG_RUNNING = Starting CPU execution. +MSG_READING_CPU_REGS = Reading CPU registers. +MSG_CLEANING_DOC = Cleaning documentation. +MSG_GENERATING_DOC = Generating documentation to \`$(DOC_PATH)\'. + + +# ** ** ** *** ** ** ** ** ** ** ** ** ** ** ** +# MAKE RULES +# ** ** ** *** ** ** ** ** ** ** ** ** ** ** ** + +# Include the make configuration file. +include $(MAKECFG) + +# ** ** TOP-LEVEL RULES ** ** + +# Default goal: build the project. +ifeq ($(TGTTYPE),.a) +.PHONY: all +all: ccversion a lss sym sizes +else +ifeq ($(TGTTYPE),.elf) +.PHONY: all +all: ccversion elf lss sym hex bin sizes +else +$(error $(ERR_TARGET_TYPE)) +endif +endif + +# Clean up the project. +.PHONY: clean +clean: + @echo $(MSG_CLEANING) + -$(VERBOSE_CMD)$(RM) $(BIN) + -$(VERBOSE_CMD)$(RM) $(HEX) + -$(VERBOSE_CMD)$(RM) $(SYM) + -$(VERBOSE_CMD)$(RM) $(LSS) + -$(VERBOSE_CMD)$(RM) $(TARGET) + -$(VERBOSE_CMD)$(RM) $(OBJFILES) + -$(VERBOSE_CMD)$(RM) $(ASFILES) + -$(VERBOSE_CMD)$(RM) $(CPPFILES) + -$(VERBOSE_CMD)$(RM) $(DPNDFILES) + $(VERBOSE_NL) + +# Rebuild the project. +.PHONY: rebuild +rebuild: clean all + +# Display CC version information. +.PHONY: ccversion +ccversion: + @echo + @echo + @$(CC) --version + +# Generate preprocessed files from C source files. +.PHONY: cppfiles +cppfiles: $(CPPFILES) + +# Generate preprocessed assembler files from C and assembler source files. +.PHONY: asfiles +asfiles: $(ASFILES) + +# Generate object files from C and assembler source files. +.PHONY: objfiles +objfiles: $(OBJFILES) + +ifeq ($(TGTTYPE),.a) +# Archive: create A output file from object files. +.PHONY: a +a: $(TARGET) +else +ifeq ($(TGTTYPE),.elf) +# Link: create ELF output file from object files. +.PHONY: elf +elf: $(TARGET) +endif +endif + +# Create extended listing from target output file. +.PHONY: lss +lss: $(LSS) + +# Create symbol table from target output file. +.PHONY: sym +sym: $(SYM) + +ifeq ($(TGTTYPE),.elf) + +# Create Intel HEX image from ELF output file. +.PHONY: hex +hex: $(HEX) + +# Create binary image from ELF output file. +.PHONY: bin +bin: $(BIN) + +endif + +# Display target size information. +.PHONY: sizes +sizes: $(TARGET) + @echo + @echo +ifeq ($(TGTTYPE),.a) + @$(SIZE) -Bxt $< +else +ifeq ($(TGTTYPE),.elf) + @$(SIZE) -Ax $< + @$(SIZE) -Bx $< +endif +endif + @echo + @echo + +ifeq ($(TGTTYPE),.elf) + +# Use ISP instead of JTAGICE mkII when programming. +.PHONY: isp +ifeq ($(filter-out isp verbose,$(MAKECMDGOALS)),) +isp: all +else +isp: + @: +endif + +ifeq ($(findstring isp,$(MAKECMDGOALS)),) + +# Get CPU information. +.PHONY: cpuinfo +cpuinfo: + @echo + @echo $(MSG_GETTING_CPU_INFO) + $(VERBOSE_CMD)$(PROGRAM) cpuinfo +ifneq ($(call LastWord,$(filter cpuinfo chiperase erase program secureflash reset debug run readregs,$(MAKECMDGOALS))),cpuinfo) + @$(SLEEP) $(SLEEPUSB) +else + @echo +endif + +# Stop CPU execution. +.PHONY: halt +halt: +ifeq ($(filter cpuinfo chiperase erase program secureflash reset run readregs,$(MAKECMDGOALS)),) + @echo + @echo $(MSG_HALTING) + $(VERBOSE_CMD)$(PROGRAM) halt +ifneq ($(call LastWord,$(filter halt debug,$(MAKECMDGOALS))),halt) + @$(SLEEP) $(SLEEPUSB) +else + @echo +endif +else + @: +endif + +# Perform a JTAG Chip Erase command. +.PHONY: chiperase +chiperase: + @echo + @echo $(MSG_ERASING_CHIP) + $(VERBOSE_CMD)$(PROGRAM) chiperase +ifneq ($(call LastWord,$(filter cpuinfo chiperase program secureflash reset debug run readregs,$(MAKECMDGOALS))),chiperase) + @$(SLEEP) $(SLEEPUSB) +else + @echo +endif + +# Perform a flash chip erase. +.PHONY: erase +erase: +ifeq ($(filter chiperase program,$(MAKECMDGOALS)),) + @echo + @echo $(MSG_ERASING) + $(VERBOSE_CMD)$(PROGRAM) erase $(FLASH:%=-f%) +ifneq ($(call LastWord,$(filter cpuinfo erase secureflash reset debug run readregs,$(MAKECMDGOALS))),erase) + @$(SLEEP) $(SLEEPUSB) +else + @echo +endif +else + @: +endif + +# Program MCU memory from ELF output file. +.PHONY: program +program: all + @echo + @echo $(MSG_PROGRAMMING) + $(VERBOSE_CMD)$(PROGRAM) program $(FLASH:%=-f%) $(PROG_CLOCK:%=-c%) -e -v -R $(if $(findstring run,$(MAKECMDGOALS)),-r) $(TARGET) +ifneq ($(call LastWord,$(filter cpuinfo chiperase program secureflash debug readregs,$(MAKECMDGOALS))),program) + @$(SLEEP) $(SLEEPUSB) +else + @echo +endif + +# Protect chip by setting security bit. +.PHONY: secureflash +secureflash: + @echo + @echo $(MSG_SECURING_FLASH) + $(VERBOSE_CMD)$(PROGRAM) secureflash +ifneq ($(call LastWord,$(filter cpuinfo chiperase erase program secureflash reset debug run readregs,$(MAKECMDGOALS))),secureflash) + @$(SLEEP) $(SLEEPUSB) +else + @echo +endif + +# Reset MCU. +.PHONY: reset +reset: +ifeq ($(filter program run,$(MAKECMDGOALS)),) + @echo + @echo $(MSG_RESETTING) + $(VERBOSE_CMD)$(PROGRAM) reset +ifneq ($(call LastWord,$(filter cpuinfo chiperase erase secureflash reset debug readregs,$(MAKECMDGOALS))),reset) + @$(SLEEP) $(SLEEPUSB) +else + @echo +endif +else + @: +endif + +# Open a debug connection with the MCU. +.PHONY: debug +debug: + @echo + @echo $(MSG_DEBUGGING) + $(VERBOSE_CMD)$(DBGPROXY) $(FLASH:%=-f%) +ifneq ($(call LastWord,$(filter cpuinfo halt chiperase erase program secureflash reset debug run readregs,$(MAKECMDGOALS))),debug) + @$(SLEEP) $(SLEEPUSB) +else + @echo +endif + +# Start CPU execution. +.PHONY: run +run: +ifeq ($(findstring program,$(MAKECMDGOALS)),) + @echo + @echo $(MSG_RUNNING) + $(VERBOSE_CMD)$(PROGRAM) run $(if $(findstring reset,$(MAKECMDGOALS)),-R) +ifneq ($(call LastWord,$(filter cpuinfo chiperase erase secureflash debug run readregs,$(MAKECMDGOALS))),run) + @$(SLEEP) $(SLEEPUSB) +else + @echo +endif +else + @: +endif + +# Read CPU registers. +.PHONY: readregs +readregs: + @echo + @echo $(MSG_READING_CPU_REGS) + $(VERBOSE_CMD)$(PROGRAM) readregs +ifneq ($(call LastWord,$(filter cpuinfo chiperase erase program secureflash reset debug run readregs,$(MAKECMDGOALS))),readregs) + @$(SLEEP) $(SLEEPUSB) +else + @echo +endif + +else + +# Perform a flash chip erase. +.PHONY: erase +erase: +ifeq ($(findstring program,$(MAKECMDGOALS)),) + @echo + @echo $(MSG_ERASING) + $(VERBOSE_CMD)$(ISP) $(ISPFLAGS) erase f memory flash blankcheck +ifeq ($(call LastWord,$(filter erase secureflash debug run,$(MAKECMDGOALS))),erase) + @echo +endif +else + @: +endif + +# Program MCU memory from ELF output file. +.PHONY: program +program: all + @echo + @echo $(MSG_PROGRAMMING) + $(VERBOSE_CMD)$(ISP) $(ISPFLAGS) erase f memory flash blankcheck loadbuffer $(TARGET) program verify $(if $(findstring run,$(MAKECMDGOALS)),$(if $(findstring secureflash,$(MAKECMDGOALS)),,start $(if $(findstring reset,$(MAKECMDGOALS)),,no)reset 0)) +ifeq ($(call LastWord,$(filter program secureflash debug,$(MAKECMDGOALS))),program) + @echo +endif + +# Protect chip by setting security bit. +.PHONY: secureflash +secureflash: + @echo + @echo $(MSG_SECURING_FLASH) + $(VERBOSE_CMD)$(ISP) $(ISPFLAGS) memory security addrange 0x0 0x0 fillbuffer 0x01 program $(if $(findstring run,$(MAKECMDGOALS)),start $(if $(findstring reset,$(MAKECMDGOALS)),,no)reset 0) +ifeq ($(call LastWord,$(filter erase program secureflash debug,$(MAKECMDGOALS))),secureflash) + @echo +endif + +# Reset MCU. +.PHONY: reset +reset: + @: + +# Open a debug connection with the MCU. +.PHONY: debug +debug: + @echo + @echo $(MSG_DEBUGGING) + $(VERBOSE_CMD)$(DBGPROXY) $(FLASH:%=-f%) +ifeq ($(call LastWord,$(filter erase program secureflash debug run,$(MAKECMDGOALS))),debug) + @echo +endif + +# Start CPU execution. +.PHONY: run +run: +ifeq ($(filter program secureflash,$(MAKECMDGOALS)),) + @echo + @echo $(MSG_RUNNING) + $(VERBOSE_CMD)$(ISP) $(ISPFLAGS) start $(if $(findstring reset,$(MAKECMDGOALS)),,no)reset 0 +ifeq ($(call LastWord,$(filter erase debug run,$(MAKECMDGOALS))),run) + @echo +endif +else + @: +endif + +endif + +endif + +# Build the documentation. +.PHONY: doc +doc: + @echo + @echo $(MSG_GENERATING_DOC) + $(VERBOSE_CMD)cd $(dir $(DOC_CFG)) && $(DOCGEN) $(notdir $(DOC_CFG)) + @echo + +# Clean up the documentation. +.PHONY: cleandoc +cleandoc: + @echo $(MSG_CLEANING_DOC) + -$(VERBOSE_CMD)$(RM) $(DOC_PATH) + $(VERBOSE_NL) + +# Rebuild the documentation. +.PHONY: rebuilddoc +rebuilddoc: cleandoc doc + +# Display main executed commands. +.PHONY: verbose +ifeq ($(filter-out isp verbose,$(MAKECMDGOALS)),) +verbose: all +else +verbose: + @: +endif +ifneq ($(findstring verbose,$(MAKECMDGOALS)),) +# Prefix displaying the following command if and only if verbose is a goal. +VERBOSE_CMD = +# New line displayed if and only if verbose is a goal. +VERBOSE_NL = @echo +else +VERBOSE_CMD = @ +VERBOSE_NL = +endif + +# ** ** COMPILATION RULES ** ** + +# Include silently the dependency files. +-include $(DPNDFILES) + +# The dependency files are not built alone but along with first generation files. +$(DPNDFILES): + +# First generation files depend on make files. +$(CPPFILES) $(ASFILES) $(OBJFILES): Makefile $(MAKECFG) + +ifeq ($(TGTTYPE),.elf) +# Files resulting from linking depend on linker script. +$(TARGET): $(LINKER_SCRIPT) +endif + +# Preprocess: create preprocessed files from C source files. +%.i: %.c %.d + @echo $(MSG_PREPROCESSING) + $(VERBOSE_CMD)$(CPP) $(CPPFLAGS) -MD -MP -MT '$*.i $*.x $*.o' -o $@ $< + @touch $*.d + @touch $@ + $(VERBOSE_NL) + +# Preprocess & compile: create assembler files from C source files. +%.x: %.c %.d + @echo $(MSG_COMPILING) + $(VERBOSE_CMD)$(CC) -S $(CPPFLAGS) -MD -MP -MT '$*.i $*.o' $(CFLAGS) -o $@ $< + @touch $*.d + @touch $@ + $(VERBOSE_NL) + +# Preprocess: create preprocessed files from assembler source files. +%.x: %.S %.d + @echo $(MSG_PREPROCESSING) + $(VERBOSE_CMD)$(CPP) $(CPPFLAGS) -MD -MP -MT '$*.x $*.o' -o $@ $< + @touch $*.d + @touch $@ + $(VERBOSE_NL) + +# Preprocess, compile & assemble: create object files from C source files. +%.o: %.c %.d + @echo $(MSG_COMPILING) + $(VERBOSE_CMD)$(CC) -c $(CPPFLAGS) -MD -MP -MT '$*.i $*.x' $(CFLAGS) -o $@ $< + @touch $*.d + @touch $@ + $(VERBOSE_NL) + +# Preprocess & assemble: create object files from assembler source files. +%.o: %.S %.d + @echo $(MSG_ASSEMBLING) + $(VERBOSE_CMD)$(CC) -c $(CPPFLAGS) -MD -MP -MT '$*.x' $(ASFLAGS) -o $@ $< + @touch $*.d + @touch $@ + $(VERBOSE_NL) + +.PRECIOUS: $(OBJFILES) +ifeq ($(TGTTYPE),.a) +# Archive: create A output file from object files. +.SECONDARY: $(TARGET) +$(TARGET): $(OBJFILES) + @echo $(MSG_ARCHIVING) + $(VERBOSE_CMD)$(AR) $(ARFLAGS) $@ $(filter %.o,$+) + $(VERBOSE_NL) +else +ifeq ($(TGTTYPE),.elf) +# Link: create ELF output file from object files. +.SECONDARY: $(TARGET) +$(TARGET): $(OBJFILES) + @echo $(MSG_LINKING) + $(VERBOSE_CMD)$(CC) $(LDFLAGS) $(filter %.o,$+) $(LOADLIBES) $(LDLIBS) -o $@ + $(VERBOSE_NL) +endif +endif + +# Create extended listing from target output file. +$(LSS): $(TARGET) + @echo $(MSG_EXTENDED_LISTING) + $(VERBOSE_CMD)$(OBJDUMP) -h -S $< > $@ + $(VERBOSE_NL) + +# Create symbol table from target output file. +$(SYM): $(TARGET) + @echo $(MSG_SYMBOL_TABLE) + $(VERBOSE_CMD)$(NM) -n $< > $@ + $(VERBOSE_NL) + +ifeq ($(TGTTYPE),.elf) + +# Create Intel HEX image from ELF output file. +$(HEX): $(TARGET) + @echo $(MSG_IHEX_IMAGE) + $(VERBOSE_CMD)$(OBJCOPY) -O ihex $< $@ + $(VERBOSE_NL) + +# Create binary image from ELF output file. +$(BIN): $(TARGET) + @echo $(MSG_BINARY_IMAGE) + $(VERBOSE_CMD)$(OBJCOPY) -O binary $< $@ + $(VERBOSE_NL) + +endif diff --git a/20080212/Demo/lwIP_AVR32_UC3/AT32UC3A/GCC/config.mk b/20080212/Demo/lwIP_AVR32_UC3/AT32UC3A/GCC/config.mk new file mode 100644 index 000000000..4712cdf6b --- /dev/null +++ b/20080212/Demo/lwIP_AVR32_UC3/AT32UC3A/GCC/config.mk @@ -0,0 +1,198 @@ +# Hey Emacs, this is a -*- makefile -*- + +# The purpose of this file is to define the build configuration variables used +# by the generic Makefile. See Makefile header for further information. + +# Copyright (c) 2007, Atmel Corporation All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation and/ +# or other materials provided with the distribution. +# +# 3. The name of ATMEL may not be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND +# SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, +# INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +# OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + +# Base paths +PRJ_PATH = ../.. +APPS_PATH = $(PRJ_PATH)/APPLICATIONS +BRDS_PATH = $(PRJ_PATH)/BOARDS +COMP_PATH = $(PRJ_PATH)/COMPONENTS +DRVR_PATH = $(PRJ_PATH)/DRIVERS +SERV_PATH = $(PRJ_PATH)/SERVICES +UTIL_PATH = $(PRJ_PATH)/UTILS + +# Demo paths +FREERTOS_PATH = ../../../.. +FREERTOS_PORT_PATH = $(FREERTOS_PATH)/Source/portable/GCC/AVR32_UC3 +FREERTOS_MEM_PATH = $(FREERTOS_PATH)/Source/portable/MemMang +DEMO_PATH = ../.. +ETH_PATH = $(DEMO_PATH)/NETWORK +WEB_PATH = $(ETH_PATH)/BasicWEB +TFTP_PATH = $(ETH_PATH)/BasicTFTP +SMTP_PATH = $(ETH_PATH)/BasicSMTP +LWIP_PATH = $(FREERTOS_PATH)/Demo/Common/ethernet/lwIP +LWIP_PORT_PATH = $(ETH_PATH)/lwip-port/AT32UC3A + +# CPU architecture: {ap|uc} +ARCH = uc + +# Part: {none|ap7xxx|uc3xxxxx} +PART = uc3a0512 + +# Flash memories: [{cfi|internal}@address,size]... +FLASH = internal@0x80000000,512Kb + +# Clock source to use when programming: [{xtal|extclk|int}] +PROG_CLOCK = xtal + +# Device/Platform/Board include path +PLATFORM_INC_PATH = \ + $(BRDS_PATH)/ + +# Target name: {*.a|*.elf} +TARGET = $(PART)-lwipdemo.elf + +# Definitions: [-D name[=definition]...] [-U name...] +# Things that might be added to DEFS: +# BOARD Board used: {EVKxxxx} +# EXT_BOARD Extension board used (if any): {EXTxxxx} +DEFS = -D BOARD=EVK1100 -D FREERTOS_USED -D HTTP_USED=1 -D TFTP_USED=1 -D SMTP_USED=0 + +# Include path +INC_PATH = \ + $(UTIL_PATH)/ \ + $(UTIL_PATH)/PREPROCESSOR/ \ + $(SERV_PATH)/USB/CLASS/DFU/EXAMPLES/ISP/BOOT/ \ + $(DRVR_PATH)/INTC/ \ + $(DRVR_PATH)/TC/ \ + $(DRVR_PATH)/PM/ \ + $(DRVR_PATH)/GPIO/ \ + $(DRVR_PATH)/FLASHC/ \ + $(DRVR_PATH)/MACB/ \ + $(DEMO_PATH)/ \ + $(FREERTOS_PATH)/Source/include/ \ + $(FREERTOS_PATH)/Demo/Common/include/ \ + $(FREERTOS_PORT_PATH)/ \ + $(FREERTOS_MEM_PATH)/ \ + $(ETH_PATH)/ \ + $(LWIP_PATH)/include/ \ + $(LWIP_PATH)/include/ipv4/ \ + $(LWIP_PORT_PATH)/ \ + $(WEB_PATH)/ \ + $(TFTP_PATH)/ \ + $(SMTP_PATH)/ + +# C source files + +LWIP_SRC = \ + $(LWIP_PATH)/core/inet.c \ + $(LWIP_PATH)/core/mem.c \ + $(LWIP_PATH)/core/memp.c \ + $(LWIP_PATH)/core/netif.c \ + $(LWIP_PATH)/core/pbuf.c \ + $(LWIP_PATH)/core/raw.c \ + $(LWIP_PATH)/core/stats.c \ + $(LWIP_PATH)/core/sys.c \ + $(LWIP_PATH)/core/tcp.c \ + $(LWIP_PATH)/core/tcp_in.c \ + $(LWIP_PATH)/core/tcp_out.c \ + $(LWIP_PATH)/core/ipv4/ip.c \ + $(LWIP_PATH)/core/ipv4/ip_addr.c \ + $(LWIP_PATH)/core/ipv4/icmp.c \ + $(LWIP_PATH)/api/sockets.c \ + $(LWIP_PATH)/api/tcpip.c \ + $(LWIP_PATH)/api/api_msg.c \ + $(LWIP_PATH)/api/err.c \ + $(LWIP_PATH)/api/api_lib.c \ + $(LWIP_PATH)/netif/etharp.c \ + $(LWIP_PATH)/core/udp.c \ + $(LWIP_PATH)/core/ipv4/ip_frag.c + +CSRCS = \ + $(BRDS_PATH)/EVK1100/led.c \ + $(DRVR_PATH)/INTC/intc.c \ + $(DRVR_PATH)/TC/tc.c \ + $(DRVR_PATH)/PM/pm.c \ + $(DRVR_PATH)/MACB/macb.c \ + $(DRVR_PATH)/GPIO/gpio.c \ + $(DRVR_PATH)/FLASHC/flashc.c \ + $(DEMO_PATH)/main.c \ + $(DEMO_PATH)/PARTEST/ParTest.c \ + $(DEMO_PATH)/SERIAL/serial.c \ + $(FREERTOS_PATH)/Source/tasks.c \ + $(FREERTOS_PATH)/Source/queue.c \ + $(FREERTOS_PATH)/Source/list.c \ + $(FREERTOS_PATH)/Source/croutine.c \ + $(FREERTOS_PATH)/Demo/Common/Minimal/flash.c \ + $(FREERTOS_PORT_PATH)/port.c \ + $(FREERTOS_MEM_PATH)/heap_3.c \ + $(LWIP_SRC) \ + $(LWIP_PORT_PATH)/sys_arch.c \ + $(LWIP_PORT_PATH)/ethernetif.c \ + $(WEB_PATH)/BasicWEB.c \ + $(TFTP_PATH)/BasicTFTP.c \ + $(SMTP_PATH)/BasicSMTP.c \ + $(ETH_PATH)/ethernet.c \ + $(DEMO_PATH)/printf-stdarg.c + +# Assembler source files +ASSRCS = \ + $(SERV_PATH)/USB/CLASS/DFU/EXAMPLES/ISP/BOOT/trampoline.S \ + $(FREERTOS_PORT_PATH)/exception.S + +# Library path +LIB_PATH = + +# Libraries to link with the project +LIBS = + +# Linker script file if any +LINKER_SCRIPT = $(UTIL_PATH)/LINKER_SCRIPTS/AT32UC3A/0512/GCC/link_uc3a0512.lds + +# Options to request or suppress warnings: [-fsyntax-only] [-pedantic[-errors]] [-w] [-Wwarning...] +# For further details, refer to the chapter "GCC Command Options" of the GCC manual. +WARNINGS = -Wall + +# Options for debugging: [-g]... +# For further details, refer to the chapter "GCC Command Options" of the GCC manual. +DEBUG = -g + +# Options that control optimization: [-O[0|1|2|3|s]]... +# For further details, refer to the chapter "GCC Command Options" of the GCC manual. +OPTIMIZATION = -O0 -ffunction-sections -fdata-sections + +# Extra flags to use when preprocessing +CPP_EXTRA_FLAGS = + +# Extra flags to use when compiling +C_EXTRA_FLAGS = + +# Extra flags to use when assembling +AS_EXTRA_FLAGS = + +# Extra flags to use when linking +LD_EXTRA_FLAGS = -Wl,--gc-sections -Wl,-e,_trampoline + +# Documentation path +DOC_PATH = ./DOC/ + +# Documentation configuration file +DOC_CFG = ./doxyfile.doxygen diff --git a/20080212/Demo/lwIP_AVR32_UC3/AT32UC3A/GCC/gdb.ini b/20080212/Demo/lwIP_AVR32_UC3/AT32UC3A/GCC/gdb.ini new file mode 100644 index 000000000..3e2d67002 --- /dev/null +++ b/20080212/Demo/lwIP_AVR32_UC3/AT32UC3A/GCC/gdb.ini @@ -0,0 +1,8 @@ +target extended-remote 127.0.0.1:1024 +symbol uc3a0512-demo.elf + + +define current_task +printf "Task name: %s\n", ((tskTCB *)pxCurrentTCB)->pcTaskName +printf "pxTopOfStack: %x\n", ((tskTCB *)pxCurrentTCB)->pxTopOfStack +end diff --git a/20080212/Demo/lwIP_AVR32_UC3/AT32UC3A/GCC/gdb_cmdfile.txt b/20080212/Demo/lwIP_AVR32_UC3/AT32UC3A/GCC/gdb_cmdfile.txt new file mode 100644 index 000000000..832686600 --- /dev/null +++ b/20080212/Demo/lwIP_AVR32_UC3/AT32UC3A/GCC/gdb_cmdfile.txt @@ -0,0 +1,8 @@ +target extended-remote 127.0.0.1:4711 +symbol uc3a0512-demo.elf + + +define current_task +printf "Task name: %s\n", ((tskTCB *)pxCurrentTCB)->pcTaskName +printf "pxTopOfStack: %x\n", ((tskTCB *)pxCurrentTCB)->pxTopOfStack +end diff --git a/20080212/Demo/lwIP_AVR32_UC3/AT32UC3A/IAR/Debug/Obj/lwipdemo.pbd b/20080212/Demo/lwIP_AVR32_UC3/AT32UC3A/IAR/Debug/Obj/lwipdemo.pbd new file mode 100644 index 000000000..eae6bf4bd --- /dev/null +++ b/20080212/Demo/lwIP_AVR32_UC3/AT32UC3A/IAR/Debug/Obj/lwipdemo.pbd @@ -0,0 +1,49 @@ +This is an internal working file generated by the Source Browser. +20:24 19s +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\lwIP_AVR32_UC3\AT32UC3A\IAR\Debug\Obj\BasicSMTP.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\lwIP_AVR32_UC3\AT32UC3A\IAR\Debug\Obj\BasicTFTP.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\lwIP_AVR32_UC3\AT32UC3A\IAR\Debug\Obj\BasicWEB.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\lwIP_AVR32_UC3\AT32UC3A\IAR\Debug\Obj\ParTest.pbi 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+C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\lwIP_AVR32_UC3\AT32UC3A\IAR\Debug\Obj\udp.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\lwIP_AVR32_UC3\AT32UC3A\IAR\Debug\Obj\usart.pbi +C:\E\Dev\FreeRTOS\Releases\Code\V4.5.0\Demo\lwIP_AVR32_UC3\AT32UC3A\IAR\Debug\Obj\write.pbi diff --git a/20080212/Demo/lwIP_AVR32_UC3/AT32UC3A/IAR/lwipdemo.ewd b/20080212/Demo/lwIP_AVR32_UC3/AT32UC3A/IAR/lwipdemo.ewd new file mode 100644 index 000000000..8ef76f6cf --- /dev/null +++ b/20080212/Demo/lwIP_AVR32_UC3/AT32UC3A/IAR/lwipdemo.ewd @@ -0,0 +1,190 @@ + + + + 1 + + Debug + + AVR32 + + 1 + + C-SPY + 2 + + 0 + 1 + 1 + + + + + + + + + + + + + + + + + JTAGICEMKIIAVR32 + 3 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + SIMAVR32 + 2 + + 0 + 1 + 1 + + + + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin + 1 + + + + + + diff --git a/20080212/Demo/lwIP_AVR32_UC3/AT32UC3A/IAR/lwipdemo.ewp b/20080212/Demo/lwIP_AVR32_UC3/AT32UC3A/IAR/lwipdemo.ewp new file mode 100644 index 000000000..4d6b3435d --- /dev/null +++ b/20080212/Demo/lwIP_AVR32_UC3/AT32UC3A/IAR/lwipdemo.ewp @@ -0,0 +1,1002 @@ + + + + 1 + + Debug + + AVR32 + + 1 + + General + 2 + + 0 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCAVR32 + 3 + + 5 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AAVR32 + 2 + + 0 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JAVATOC + 0 + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + XLINK + 2 + + 14 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + XAR + 2 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + DLIB + + $PROJ_DIR$\..\..\..\..\Source\portable\IAR\AVR32_UC3\read.c + + + $PROJ_DIR$\..\..\SERVICES\USB\CLASS\DFU\EXAMPLES\ISP\BOOT\trampoline.s82 + + + $PROJ_DIR$\..\..\..\..\Source\portable\IAR\AVR32_UC3\write.c + + + + Drivers + + $PROJ_DIR$\..\..\DRIVERS\FLASHC\flashc.c + + + $PROJ_DIR$\..\..\DRIVERS\GPIO\gpio.c + + + $PROJ_DIR$\..\..\DRIVERS\INTC\intc.c + + + $PROJ_DIR$\..\..\BOARDS\EVK1100\led.c + + + $PROJ_DIR$\..\..\DRIVERS\MACB\macb.c + + + $PROJ_DIR$\..\..\DRIVERS\PM\pm.c + + + $PROJ_DIR$\..\..\DRIVERS\TC\tc.c + + + $PROJ_DIR$\..\..\DRIVERS\USART\usart.c + + + + FreeRTOS + + AVR32_UC3 + + $PROJ_DIR$\..\..\..\..\Source\portable\IAR\AVR32_UC3\exception.s82 + + + $PROJ_DIR$\..\..\..\..\Source\portable\IAR\AVR32_UC3\port.c + + + + Source + + $PROJ_DIR$\..\..\..\..\Source\portable\MemMang\heap_3.c + + + $PROJ_DIR$\..\..\..\..\Source\list.c + + + $PROJ_DIR$\..\..\..\..\Source\queue.c + + + $PROJ_DIR$\..\..\..\..\Source\tasks.c + + + + $PROJ_DIR$\..\..\..\Common\Minimal\flash.c + + + + NETWORK + + lwip + + $PROJ_DIR$\..\..\..\Common\ethernet\lwIP\api\api_lib.c + + + $PROJ_DIR$\..\..\..\Common\ethernet\lwIP\api\api_msg.c + + + $PROJ_DIR$\..\..\..\Common\ethernet\lwIP\api\err.c + + + $PROJ_DIR$\..\..\..\Common\ethernet\lwIP\netif\etharp.c + + + $PROJ_DIR$\..\..\NETWORK\lwip-port\AT32UC3A\ethernetif.c + + + $PROJ_DIR$\..\..\..\Common\ethernet\lwIP\core\ipv4\icmp.c + + + $PROJ_DIR$\..\..\..\Common\ethernet\lwIP\core\inet.c + + + $PROJ_DIR$\..\..\..\Common\ethernet\lwIP\core\ipv4\ip.c + + + $PROJ_DIR$\..\..\..\Common\ethernet\lwIP\core\ipv4\ip_addr.c + + + $PROJ_DIR$\..\..\..\Common\ethernet\lwIP\core\ipv4\ip_frag.c + + + $PROJ_DIR$\..\..\..\Common\ethernet\lwIP\core\mem.c + + + $PROJ_DIR$\..\..\..\Common\ethernet\lwIP\core\memp.c + + + $PROJ_DIR$\..\..\..\Common\ethernet\lwIP\core\netif.c + + + $PROJ_DIR$\..\..\..\Common\ethernet\lwIP\core\pbuf.c + + + $PROJ_DIR$\..\..\..\Common\ethernet\lwIP\core\raw.c + + + $PROJ_DIR$\..\..\..\Common\ethernet\lwIP\api\sockets.c + + + $PROJ_DIR$\..\..\..\Common\ethernet\lwIP\core\stats.c + + + $PROJ_DIR$\..\..\..\Common\ethernet\lwIP\core\sys.c + + + $PROJ_DIR$\..\..\NETWORK\lwip-port\AT32UC3A\sys_arch.c + + + $PROJ_DIR$\..\..\..\Common\ethernet\lwIP\core\tcp.c + + + $PROJ_DIR$\..\..\..\Common\ethernet\lwIP\core\tcp_in.c + + + $PROJ_DIR$\..\..\..\Common\ethernet\lwIP\core\tcp_out.c + + + $PROJ_DIR$\..\..\..\Common\ethernet\lwIP\api\tcpip.c + + + $PROJ_DIR$\..\..\..\Common\ethernet\lwIP\core\udp.c + + + + Services + + $PROJ_DIR$\..\..\NETWORK\BasicSMTP\BasicSMTP.c + + + $PROJ_DIR$\..\..\NETWORK\BasicTFTP\BasicTFTP.c + + + $PROJ_DIR$\..\..\NETWORK\BasicWEB\BasicWEB.c + + + $PROJ_DIR$\..\..\NETWORK\ethernet.c + + + + + $PROJ_DIR$\..\..\main.c + + + $PROJ_DIR$\..\..\PARTEST\ParTest.c + + + $PROJ_DIR$\..\..\SERIAL\serial.c + + + + diff --git a/20080212/Demo/lwIP_AVR32_UC3/AT32UC3A/IAR/lwipdemo.eww b/20080212/Demo/lwIP_AVR32_UC3/AT32UC3A/IAR/lwipdemo.eww new file mode 100644 index 000000000..125e9e5d0 --- /dev/null +++ b/20080212/Demo/lwIP_AVR32_UC3/AT32UC3A/IAR/lwipdemo.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\lwipdemo.ewp + + + + + diff --git a/20080212/Demo/lwIP_AVR32_UC3/AT32UC3A/IAR/settings/lwipdemo.cspy.bat b/20080212/Demo/lwIP_AVR32_UC3/AT32UC3A/IAR/settings/lwipdemo.cspy.bat new file mode 100644 index 000000000..c8e602098 --- /dev/null +++ b/20080212/Demo/lwIP_AVR32_UC3/AT32UC3A/IAR/settings/lwipdemo.cspy.bat @@ -0,0 +1,32 @@ +@REM This bat file has been generated by the IAR Embeddded Workbench +@REM C-SPY interactive debugger,as an aid to preparing a command +@REM line for running the cspybat command line utility with the +@REM appropriate settings. +@REM +@REM After making some adjustments to this file, you can launch cspybat +@REM by typing the name of this file followed by the name of the debug +@REM file (usually an ubrof file). Note that this file is generated +@REM every time a new debug session is initialized, so you may want to +@REM move or rename the file before making changes. +@REM +@REM Note: some command line arguments cannot be properly generated +@REM by this process. Specifically, the plugin which is responsible +@REM for the Terminal I/O window (and other C runtime functionality) +@REM comes in a special version for cspybat, and the name of that +@REM plugin dll is not known when generating this file. It resides in +@REM the $TOOLKIT_DIR$\bin folder and is usually called XXXbat.dll or +@REM XXXlibsupportbat.dll, where XXX is the name of the corresponding +@REM tool chain. Replace the '' parameter +@REM below with the appropriate file name. Other plugins loaded by +@REM C-SPY are usually not needed by, or will not work in, cspybat +@REM but they are listed at the end of this file for reference. + + +"C:\Devtools\IAR Systems\Embedded Workbench 4.0\common\bin\cspybat" "C:\Devtools\IAR Systems\Embedded Workbench 4.0\avr32\bin\avr32proc.dll" "C:\Devtools\IAR Systems\Embedded Workbench 4.0\avr32\bin\avr32jtagicemkII.dll" %1 --plugin "C:\Devtools\IAR Systems\Embedded Workbench 4.0\avr32\bin\" --backend -B "--core" "avr32a" "--avr32_simd_instructions" "disabled" "--avr32_dsp_instructions" "enabled" "--avr32_rmw_instructions" "enabled" "-p" "C:\Devtools\IAR Systems\Embedded Workbench 4.0\avr32\config\iouc3a0512.ddf" "-d" "jtagicemkII" "--drv_communication" "USB" "--jtagice_clock" "100000" + + +@REM Loaded plugins: +@REM avr32LibSupport.dll +@REM C:\Devtools\IAR Systems\Embedded Workbench 4.0\common\plugins\CodeCoverage\CodeCoverage.dll +@REM C:\Devtools\IAR Systems\Embedded Workbench 4.0\common\plugins\Profiling\Profiling.dll +@REM C:\Devtools\IAR Systems\Embedded Workbench 4.0\common\plugins\stack\stack.dll diff --git a/20080212/Demo/lwIP_AVR32_UC3/AT32UC3A/IAR/settings/lwipdemo.dbgdt b/20080212/Demo/lwIP_AVR32_UC3/AT32UC3A/IAR/settings/lwipdemo.dbgdt new file mode 100644 index 000000000..33f4649c2 --- /dev/null +++ b/20080212/Demo/lwIP_AVR32_UC3/AT32UC3A/IAR/settings/lwipdemo.dbgdt @@ -0,0 +1,5 @@ + + + + + diff --git a/20080212/Demo/lwIP_AVR32_UC3/AT32UC3A/IAR/settings/lwipdemo.dni b/20080212/Demo/lwIP_AVR32_UC3/AT32UC3A/IAR/settings/lwipdemo.dni new file mode 100644 index 000000000..4520689fb --- /dev/null +++ b/20080212/Demo/lwIP_AVR32_UC3/AT32UC3A/IAR/settings/lwipdemo.dni @@ -0,0 +1,5 @@ +[Breakpoints] +Count=0 +[TraceHelper] +Enabled=0 +ShowSource=1 diff --git a/20080212/Demo/lwIP_AVR32_UC3/AT32UC3A/IAR/settings/lwipdemo.wsdt b/20080212/Demo/lwIP_AVR32_UC3/AT32UC3A/IAR/settings/lwipdemo.wsdt new file mode 100644 index 000000000..2a6a3cc94 --- /dev/null +++ b/20080212/Demo/lwIP_AVR32_UC3/AT32UC3A/IAR/settings/lwipdemo.wsdt @@ -0,0 +1,66 @@ + + + + + + lwipdemo/Debug + + + + + + + + 20100626867 + + + + + + + 124272727 + + + + + + + + + TabID-32105-15798 + Workspace + Workspace + + + lwipdemo + + + + 0 + + + TabID-10086-15801 + Build + Build + + + + + 0 + + + + + + 0100000010000001 + + + + + + + iaridepm.enu1-2-2740198-2-2200200142857203666142857755601-2-21981402-2-214042001002857203666142857203666 + + + + diff --git a/20080212/Demo/lwIP_AVR32_UC3/BOARDS/EVK1100/evk1100.h b/20080212/Demo/lwIP_AVR32_UC3/BOARDS/EVK1100/evk1100.h new file mode 100644 index 000000000..2905fff22 --- /dev/null +++ b/20080212/Demo/lwIP_AVR32_UC3/BOARDS/EVK1100/evk1100.h @@ -0,0 +1,325 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief AT32UC3A EVK1100 board header file. + * + * This file contains definitions and services related to the features of the + * EVK1100 board. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 AT32UC3A devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef _EVK1100_H_ +#define _EVK1100_H_ + +#include "compiler.h" + +#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling. +# include "led.h" +#endif // __AVR32_ABI_COMPILER__ + + +/*! \name Oscillator Definitions + */ +//! @{ + +// RCOsc has no custom calibration by default. Set the following definition to +// the appropriate value if a custom RCOsc calibration has been applied to your +// part. +//#define FRCOSC 115200 //!< RCOsc frequency: Hz. + +#define FOSC32 32768 //!< Osc32 frequency: Hz. +#define OSC32_STARTUP 3 //!< Osc32 startup time: RCOsc periods. + +#define FOSC0 12000000 //!< Osc0 frequency: Hz. +#define OSC0_STARTUP 3 //!< Osc0 startup time: RCOsc periods. + +// Osc1 crystal is not mounted by default. Set the following definitions to the +// appropriate values if a custom Osc1 crystal is mounted on your board. +//#define FOSC1 12000000 //!< Osc1 frequency: Hz. +//#define OSC1_STARTUP 3 //!< Osc1 startup time: RCOsc periods. + +//! @} + + +/*! \name SDRAM Definitions + */ +//! @{ + +//! Part header file of used SDRAM(s). +#define SDRAM_PART_HDR "MT48LC16M16A2TG7E/mt48lc16m16a2tg7e.h" + +//! Data bus width to use the SDRAM(s) with (16 or 32 bits; always 16 bits on +//! UC3). +#define SDRAM_DBW 16 + +//! @} + + +/*! \name USB Definitions + */ +//! @{ + +//! Multiplexed pin used for USB_ID: AVR32_USBB_USB_ID_x_x. +//! To be selected according to the AVR32_USBB_USB_ID_x_x_PIN and +//! AVR32_USBB_USB_ID_x_x_FUNCTION definitions from . +#define USB_ID AVR32_USBB_USB_ID_0_0 + +//! Multiplexed pin used for USB_VBOF: AVR32_USBB_USB_VBOF_x_x. +//! To be selected according to the AVR32_USBB_USB_VBOF_x_x_PIN and +//! AVR32_USBB_USB_VBOF_x_x_FUNCTION definitions from . +#ifdef EVK1100_REVA +# define USB_VBOF AVR32_USBB_USB_VBOF_0_0 +#else +# define USB_VBOF AVR32_USBB_USB_VBOF_0_1 +#endif + +//! Active level of the USB_VBOF output pin. +#ifdef EVK1100_REVA +# define USB_VBOF_ACTIVE_LEVEL HIGH +#else +# define USB_VBOF_ACTIVE_LEVEL LOW +#endif + +//! USB overcurrent detection pin. +#ifdef EVK1100_REVA +# define USB_OVERCURRENT_DETECT_PIN AVR32_PIN_PB18 +#else +# define USB_OVERCURRENT_DETECT_PIN AVR32_PIN_PX33 +#endif + +//! @} + + +//! GPIO connection of the MAC PHY PWR_DOWN/INT signal. +#ifdef EVK1100_REVA +# define MACB_INTERRUPT_PIN AVR32_PIN_PX12 +#else +# define MACB_INTERRUPT_PIN AVR32_PIN_PA24 +#endif + + +//! Number of LEDs. +#define LED_COUNT 8 + +/*! \name GPIO Connections of LEDs + */ +//! @{ +#ifdef EVK1100_REVA +# define LED0_GPIO AVR32_PIN_PX13 +# define LED1_GPIO AVR32_PIN_PX14 +# define LED2_GPIO AVR32_PIN_PX15 +# define LED3_GPIO AVR32_PIN_PX16 +# define LED4_GPIO AVR32_PIN_PB19 +# define LED5_GPIO AVR32_PIN_PB20 +# define LED6_GPIO AVR32_PIN_PB21 +# define LED7_GPIO AVR32_PIN_PB22 +#else +# define LED0_GPIO AVR32_PIN_PB27 +# define LED1_GPIO AVR32_PIN_PB28 +# define LED2_GPIO AVR32_PIN_PB29 +# define LED3_GPIO AVR32_PIN_PB30 +# define LED4_GPIO AVR32_PIN_PB19 +# define LED5_GPIO AVR32_PIN_PB20 +# define LED6_GPIO AVR32_PIN_PB21 +# define LED7_GPIO AVR32_PIN_PB22 +#endif +//! @} + +/*! \name PWM Channels of LEDs + */ +//! @{ +#define LED0_PWM (-1) +#define LED1_PWM (-1) +#define LED2_PWM (-1) +#define LED3_PWM (-1) +#define LED4_PWM 0 +#define LED5_PWM 1 +#define LED6_PWM 2 +#define LED7_PWM 3 +//! @} + +/*! \name PWM Functions of LEDs + */ +//! @{ +#define LED0_PWM_FUNCTION (-1) +#define LED1_PWM_FUNCTION (-1) +#define LED2_PWM_FUNCTION (-1) +#define LED3_PWM_FUNCTION (-1) +#define LED4_PWM_FUNCTION AVR32_PWM_PWM_0_FUNCTION +#define LED5_PWM_FUNCTION AVR32_PWM_PWM_1_FUNCTION +#define LED6_PWM_FUNCTION AVR32_PWM_PWM_2_FUNCTION +#define LED7_PWM_FUNCTION AVR32_PWM_PWM_3_FUNCTION +//! @} + +/*! \name Color Identifiers of LEDs to Use with LED Functions + */ +//! @{ +#ifdef EVK1100_REVA +# define LED_MONO0_GREEN LED4 +# define LED_MONO1_GREEN LED5 +# define LED_MONO2_GREEN LED6 +# define LED_MONO3_GREEN LED7 +# define LED_BI0_GREEN LED1 +# define LED_BI0_RED LED0 +# define LED_BI1_GREEN LED3 +# define LED_BI1_RED LED2 +#else +# define LED_MONO0_GREEN LED0 +# define LED_MONO1_GREEN LED1 +# define LED_MONO2_GREEN LED2 +# define LED_MONO3_GREEN LED3 +# define LED_BI0_GREEN LED5 +# define LED_BI0_RED LED4 +# define LED_BI1_GREEN LED7 +# define LED_BI1_RED LED6 +#endif +//! @} + + +/*! \name GPIO Connections of Push Buttons + */ +//! @{ +#ifdef EVK1100_REVA +# define GPIO_PUSH_BUTTON_0 AVR32_PIN_PB28 +# define GPIO_PUSH_BUTTON_1 AVR32_PIN_PB29 +# define GPIO_PUSH_BUTTON_2 AVR32_PIN_PB27 +#else +# define GPIO_PUSH_BUTTON_0 AVR32_PIN_PX16 +# define GPIO_PUSH_BUTTON_1 AVR32_PIN_PX19 +# define GPIO_PUSH_BUTTON_2 AVR32_PIN_PX22 +#endif +//! @} + + +/*! \name GPIO Connections of the Joystick + */ +//! @{ +#define GPIO_JOYSTICK_PUSH AVR32_PIN_PA20 +#define GPIO_JOYSTICK_LEFT AVR32_PIN_PA25 +#define GPIO_JOYSTICK_RIGHT AVR32_PIN_PA28 +#define GPIO_JOYSTICK_UP AVR32_PIN_PA26 +#define GPIO_JOYSTICK_DOWN AVR32_PIN_PA27 +//! @} + + +/*! \name ADC Connection of the Potentiometer + */ +//! @{ +#define ADC_POTENTIOMETER_CHANNEL 1 +#define ADC_POTENTIOMETER_PIN AVR32_ADC_AD_1_PIN +#define ADC_POTENTIOMETER_FUNCTION AVR32_ADC_AD_1_FUNCTION +//! @} + + +/*! \name ADC Connection of the Temperature Sensor + */ +//! @{ +#define ADC_TEMPERATURE_CHANNEL 0 +#define ADC_TEMPERATURE_PIN AVR32_ADC_AD_0_PIN +#define ADC_TEMPERATURE_FUNCTION AVR32_ADC_AD_0_FUNCTION +//! @} + + +/*! \name ADC Connection of the Light Sensor + */ +//! @{ +#define ADC_LIGHT_CHANNEL 2 +#define ADC_LIGHT_PIN AVR32_ADC_AD_2_PIN +#define ADC_LIGHT_FUNCTION AVR32_ADC_AD_2_FUNCTION +//! @} + + +/*! \name SPI Connections of the DIP204 LCD + */ +//! @{ +#define DIP204_SPI (&AVR32_SPI1) +#define DIP204_SPI_CS 2 +#define DIP204_SPI_SCK_PIN AVR32_SPI1_SCK_0_PIN +#define DIP204_SPI_SCK_FUNCTION AVR32_SPI1_SCK_0_FUNCTION +#define DIP204_SPI_MISO_PIN AVR32_SPI1_MISO_0_PIN +#define DIP204_SPI_MISO_FUNCTION AVR32_SPI1_MISO_0_FUNCTION +#define DIP204_SPI_MOSI_PIN AVR32_SPI1_MOSI_0_PIN +#define DIP204_SPI_MOSI_FUNCTION AVR32_SPI1_MOSI_0_FUNCTION +#define DIP204_SPI_NPCS_PIN AVR32_SPI1_NPCS_2_PIN +#define DIP204_SPI_NPCS_FUNCTION AVR32_SPI1_NPCS_2_FUNCTION +//! @} + +/*! \name GPIO and PWM Connections of the DIP204 LCD Backlight + */ +//! @{ +#define DIP204_BACKLIGHT_PIN AVR32_PIN_PB18 +#define DIP204_PWM_CHANNEL 6 +#define DIP204_PWM_PIN AVR32_PWM_PWM_6_PIN +#define DIP204_PWM_FUNCTION AVR32_PWM_PWM_6_FUNCTION +//! @} + + +/*! \name SPI Connections of the AT45DBX Data Flash Memory + */ +//! @{ +#define AT45DBX_SPI (&AVR32_SPI1) +#define AT45DBX_SPI_SCK_PIN AVR32_SPI1_SCK_0_PIN +#define AT45DBX_SPI_SCK_FUNCTION AVR32_SPI1_SCK_0_FUNCTION +#define AT45DBX_SPI_MISO_PIN AVR32_SPI1_MISO_0_PIN +#define AT45DBX_SPI_MISO_FUNCTION AVR32_SPI1_MISO_0_FUNCTION +#define AT45DBX_SPI_MOSI_PIN AVR32_SPI1_MOSI_0_PIN +#define AT45DBX_SPI_MOSI_FUNCTION AVR32_SPI1_MOSI_0_FUNCTION +#define AT45DBX_SPI_NPCS0_PIN AVR32_SPI1_NPCS_0_PIN +#define AT45DBX_SPI_NPCS0_FUNCTION AVR32_SPI1_NPCS_0_FUNCTION +//! @} + + +/*! \name GPIO and SPI Connections of the SD/MMC Connector + */ +//! @{ +#define SD_MMC_CARD_DETECT_PIN AVR32_PIN_PA02 +#define SD_MMC_WRITE_PROTECT_PIN AVR32_PIN_PA07 +#define SD_MMC_SPI (&AVR32_SPI1) +#define SD_MMC_SPI_CS 1 +#define SD_MMC_SPI_SCK_PIN AVR32_SPI1_SCK_0_PIN +#define SD_MMC_SPI_SCK_FUNCTION AVR32_SPI1_SCK_0_FUNCTION +#define SD_MMC_SPI_MISO_PIN AVR32_SPI1_MISO_0_PIN +#define SD_MMC_SPI_MISO_FUNCTION AVR32_SPI1_MISO_0_FUNCTION +#define SD_MMC_SPI_MOSI_PIN AVR32_SPI1_MOSI_0_PIN +#define SD_MMC_SPI_MOSI_FUNCTION AVR32_SPI1_MOSI_0_FUNCTION +#define SD_MMC_SPI_NPCS_PIN AVR32_SPI1_NPCS_1_PIN +#define SD_MMC_SPI_NPCS_FUNCTION AVR32_SPI1_NPCS_1_FUNCTION +//! @} + + +#endif // _EVK1100_H_ diff --git a/20080212/Demo/lwIP_AVR32_UC3/BOARDS/EVK1100/led.c b/20080212/Demo/lwIP_AVR32_UC3/BOARDS/EVK1100/led.c new file mode 100644 index 000000000..9f0952bc9 --- /dev/null +++ b/20080212/Demo/lwIP_AVR32_UC3/BOARDS/EVK1100/led.c @@ -0,0 +1,305 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief AT32UC3A EVK1100 board LEDs support package. + * + * This file contains definitions and services related to the LED features of + * the EVK1100 board. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 AT32UC3A devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include +#include "preprocessor.h" +#include "compiler.h" +#include "evk1100.h" +#include "led.h" + + +//! Structure describing LED hardware connections. +typedef const struct +{ + struct + { + U32 PORT; //!< LED GPIO port. + U32 PIN_MASK; //!< Bit-mask of LED pin in GPIO port. + } GPIO; //!< LED GPIO descriptor. + struct + { + S32 CHANNEL; //!< LED PWM channel (< 0 if N/A). + S32 FUNCTION; //!< LED pin PWM function (< 0 if N/A). + } PWM; //!< LED PWM descriptor. +} tLED_DESCRIPTOR; + + +//! Hardware descriptors of all LEDs. +static tLED_DESCRIPTOR LED_DESCRIPTOR[LED_COUNT] = +{ +#define INSERT_LED_DESCRIPTOR(LED_NO, unused) \ + { \ + {LED##LED_NO##_GPIO / 32, 1 << (LED##LED_NO##_GPIO % 32)},\ + {LED##LED_NO##_PWM, LED##LED_NO##_PWM_FUNCTION } \ + }, + MREPEAT(LED_COUNT, INSERT_LED_DESCRIPTOR, ~) +#undef INSERT_LED_DESCRIPTOR +}; + + +//! Saved state of all LEDs. +static volatile U32 LED_State = (1 << LED_COUNT) - 1; + + +U32 LED_Read_Display(void) +{ + return LED_State; +} + + +void LED_Display(U32 leds) +{ + tLED_DESCRIPTOR *led_descriptor; + volatile avr32_gpio_port_t *led_gpio_port; + + leds &= (1 << LED_COUNT) - 1; + LED_State = leds; + for (led_descriptor = &LED_DESCRIPTOR[0]; + led_descriptor < LED_DESCRIPTOR + LED_COUNT; + led_descriptor++) + { + led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT]; + if (leds & 1) + { + led_gpio_port->ovrc = led_descriptor->GPIO.PIN_MASK; + } + else + { + led_gpio_port->ovrs = led_descriptor->GPIO.PIN_MASK; + } + led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK; + leds >>= 1; + } +} + + +U32 LED_Read_Display_Mask(U32 mask) +{ + return Rd_bits(LED_State, mask); +} + + +void LED_Display_Mask(U32 mask, U32 leds) +{ + tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1; + volatile avr32_gpio_port_t *led_gpio_port; + U8 led_shift; + + mask &= (1 << LED_COUNT) - 1; + Wr_bits(LED_State, mask, leds); + while (mask) + { + led_shift = 1 + ctz(mask); + led_descriptor += led_shift; + led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT]; + leds >>= led_shift - 1; + if (leds & 1) + { + led_gpio_port->ovrc = led_descriptor->GPIO.PIN_MASK; + } + else + { + led_gpio_port->ovrs = led_descriptor->GPIO.PIN_MASK; + } + led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK; + leds >>= 1; + mask >>= led_shift; + } +} + + +Bool LED_Test(U32 leds) +{ + return Tst_bits(LED_State, leds); +} + + +void LED_Off(U32 leds) +{ + tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1; + volatile avr32_gpio_port_t *led_gpio_port; + U8 led_shift; + + leds &= (1 << LED_COUNT) - 1; + Clr_bits(LED_State, leds); + while (leds) + { + led_shift = 1 + ctz(leds); + led_descriptor += led_shift; + led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT]; + led_gpio_port->ovrs = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK; + leds >>= led_shift; + } +} + + +void LED_On(U32 leds) +{ + tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1; + volatile avr32_gpio_port_t *led_gpio_port; + U8 led_shift; + + leds &= (1 << LED_COUNT) - 1; + Set_bits(LED_State, leds); + while (leds) + { + led_shift = 1 + ctz(leds); + led_descriptor += led_shift; + led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT]; + led_gpio_port->ovrc = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK; + leds >>= led_shift; + } +} + + +void LED_Toggle(U32 leds) +{ + tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1; + volatile avr32_gpio_port_t *led_gpio_port; + U8 led_shift; + + leds &= (1 << LED_COUNT) - 1; + Tgl_bits(LED_State, leds); + while (leds) + { + led_shift = 1 + ctz(leds); + led_descriptor += led_shift; + led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT]; + led_gpio_port->ovrt = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK; + leds >>= led_shift; + } +} + + +U32 LED_Read_Display_Field(U32 field) +{ + return Rd_bitfield(LED_State, field); +} + + +void LED_Display_Field(U32 field, U32 leds) +{ + LED_Display_Mask(field, leds << ctz(field)); +} + + +U8 LED_Get_Intensity(U32 led) +{ + tLED_DESCRIPTOR *led_descriptor; + + // Check that the argument value is valid. + led = ctz(led); + led_descriptor = &LED_DESCRIPTOR[led]; + if (led >= LED_COUNT || led_descriptor->PWM.CHANNEL < 0) return 0; + + // Return the duty cycle value if the LED PWM channel is enabled, else 0. + return (AVR32_PWM.sr & (1 << led_descriptor->PWM.CHANNEL)) ? + AVR32_PWM.channel[led_descriptor->PWM.CHANNEL].cdty : 0; +} + + +void LED_Set_Intensity(U32 leds, U8 intensity) +{ + tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1; + volatile avr32_pwm_channel_t *led_pwm_channel; + volatile avr32_gpio_port_t *led_gpio_port; + U8 led_shift; + + // For each specified LED... + for (leds &= (1 << LED_COUNT) - 1; leds; leds >>= led_shift) + { + // Select the next specified LED and check that it has a PWM channel. + led_shift = 1 + ctz(leds); + led_descriptor += led_shift; + if (led_descriptor->PWM.CHANNEL < 0) continue; + + // Initialize or update the LED PWM channel. + led_pwm_channel = &AVR32_PWM.channel[led_descriptor->PWM.CHANNEL]; + if (!(AVR32_PWM.sr & (1 << led_descriptor->PWM.CHANNEL))) + { + led_pwm_channel->cmr = (AVR32_PWM_CPRE_MCK << AVR32_PWM_CPRE_OFFSET) & + ~(AVR32_PWM_CALG_MASK | + AVR32_PWM_CPOL_MASK | + AVR32_PWM_CPD_MASK); + led_pwm_channel->cprd = 0x000000FF; + led_pwm_channel->cdty = intensity; + AVR32_PWM.ena = 1 << led_descriptor->PWM.CHANNEL; + } + else + { + AVR32_PWM.isr; + while (!(AVR32_PWM.isr & (1 << led_descriptor->PWM.CHANNEL))); + led_pwm_channel->cupd = intensity; + } + + // Switch the LED pin to its PWM function. + led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT]; + if (led_descriptor->PWM.FUNCTION & 0x1) + { + led_gpio_port->pmr0s = led_descriptor->GPIO.PIN_MASK; + } + else + { + led_gpio_port->pmr0c = led_descriptor->GPIO.PIN_MASK; + } + if (led_descriptor->PWM.FUNCTION & 0x2) + { + led_gpio_port->pmr1s = led_descriptor->GPIO.PIN_MASK; + } + else + { + led_gpio_port->pmr1c = led_descriptor->GPIO.PIN_MASK; + } + led_gpio_port->gperc = led_descriptor->GPIO.PIN_MASK; + } +} diff --git a/20080212/Demo/lwIP_AVR32_UC3/BOARDS/EVK1100/led.h b/20080212/Demo/lwIP_AVR32_UC3/BOARDS/EVK1100/led.h new file mode 100644 index 000000000..aa26a0af1 --- /dev/null +++ b/20080212/Demo/lwIP_AVR32_UC3/BOARDS/EVK1100/led.h @@ -0,0 +1,186 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief AT32UC3A EVK1100 board LEDs support package. + * + * This file contains definitions and services related to the LED features of + * the EVK1100 board. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 AT32UC3A devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef _LED_H_ +#define _LED_H_ + +#include "compiler.h" + + +/*! \name Identifiers of LEDs to Use with LED Functions + */ +//! @{ +#define LED0 0x01 +#define LED1 0x02 +#define LED2 0x04 +#define LED3 0x08 +#define LED4 0x10 +#define LED5 0x20 +#define LED6 0x40 +#define LED7 0x80 +//! @} + + +/*! \brief Gets the last state of all LEDs set through the LED API. + * + * \return State of all LEDs (1 bit per LED). + * + * \note The GPIO pin configuration of all LEDs is left unchanged. + */ +extern U32 LED_Read_Display(void); + +/*! \brief Sets the state of all LEDs. + * + * \param leds New state of all LEDs (1 bit per LED). + * + * \note The pins of all LEDs are set to GPIO output mode. + */ +extern void LED_Display(U32 leds); + +/*! \brief Gets the last state of the specified LEDs set through the LED API. + * + * \param mask LEDs of which to get the state (1 bit per LED). + * + * \return State of the specified LEDs (1 bit per LED). + * + * \note The GPIO pin configuration of all LEDs is left unchanged. + */ +extern U32 LED_Read_Display_Mask(U32 mask); + +/*! \brief Sets the state of the specified LEDs. + * + * \param mask LEDs of which to set the state (1 bit per LED). + * + * \param leds New state of the specified LEDs (1 bit per LED). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +extern void LED_Display_Mask(U32 mask, U32 leds); + +/*! \brief Tests the last state of the specified LEDs set through the LED API. + * + * \param leds LEDs of which to test the state (1 bit per LED). + * + * \return \c TRUE if at least one of the specified LEDs has a state on, else + * \c FALSE. + * + * \note The GPIO pin configuration of all LEDs is left unchanged. + */ +extern Bool LED_Test(U32 leds); + +/*! \brief Turns off the specified LEDs. + * + * \param leds LEDs to turn off (1 bit per LED). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +extern void LED_Off(U32 leds); + +/*! \brief Turns on the specified LEDs. + * + * \param leds LEDs to turn on (1 bit per LED). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +extern void LED_On(U32 leds); + +/*! \brief Toggles the specified LEDs. + * + * \param leds LEDs to toggle (1 bit per LED). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +extern void LED_Toggle(U32 leds); + +/*! \brief Gets as a bit-field the last state of the specified LEDs set through + * the LED API. + * + * \param field LEDs of which to get the state (1 bit per LED). + * + * \return State of the specified LEDs (1 bit per LED, beginning with the first + * specified LED). + * + * \note The GPIO pin configuration of all LEDs is left unchanged. + */ +extern U32 LED_Read_Display_Field(U32 field); + +/*! \brief Sets as a bit-field the state of the specified LEDs. + * + * \param field LEDs of which to set the state (1 bit per LED). + * \param leds New state of the specified LEDs (1 bit per LED, beginning with + * the first specified LED). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +extern void LED_Display_Field(U32 field, U32 leds); + +/*! \brief Gets the intensity of the specified LED. + * + * \param led LED of which to get the intensity (1 bit per LED; only the least + * significant set bit is used). + * + * \return Intensity of the specified LED (0x00 to 0xFF). + * + * \warning The PWM channel of the specified LED is supposed to be used only by + * this module. + * + * \note The GPIO pin configuration of all LEDs is left unchanged. + */ +extern U8 LED_Get_Intensity(U32 led); + +/*! \brief Sets the intensity of the specified LEDs. + * + * \param leds LEDs of which to set the intensity (1 bit per LED). + * \param intensity New intensity of the specified LEDs (0x00 to 0xFF). + * + * \warning The PWM channels of the specified LEDs are supposed to be used only + * by this module. + * + * \note The pins of the specified LEDs are set to PWM output mode. + */ +extern void LED_Set_Intensity(U32 leds, U8 intensity); + + +#endif // _LED_H_ diff --git a/20080212/Demo/lwIP_AVR32_UC3/BOARDS/EVK1101/evk1101.h b/20080212/Demo/lwIP_AVR32_UC3/BOARDS/EVK1101/evk1101.h new file mode 100644 index 000000000..87291f54f --- /dev/null +++ b/20080212/Demo/lwIP_AVR32_UC3/BOARDS/EVK1101/evk1101.h @@ -0,0 +1,239 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief AT32UC3B EVK1101 board header file. + * + * This file contains definitions and services related to the features of the + * EVK1101 board. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 AT32UC3B devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef _EVK1101_H_ +#define _EVK1101_H_ + +#include "compiler.h" + +#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling. +# include "led.h" +#endif // __AVR32_ABI_COMPILER__ + + +/*! \name Oscillator Definitions + */ +//! @{ + +// RCOsc has no custom calibration by default. Set the following definition to +// the appropriate value if a custom RCOsc calibration has been applied to your +// part. +//#define FRCOSC 115200 //!< RCOsc frequency: Hz. + +#define FOSC32 32768 //!< Osc32 frequency: Hz. +#define OSC32_STARTUP 3 //!< Osc32 startup time: RCOsc periods. + +#define FOSC0 12000000 //!< Osc0 frequency: Hz. +#define OSC0_STARTUP 3 //!< Osc0 startup time: RCOsc periods. + +// Osc1 crystal is not mounted by default. Set the following definitions to the +// appropriate values if a custom Osc1 crystal is mounted on your board. +//#define FOSC1 12000000 //!< Osc1 frequency: Hz. +//#define OSC1_STARTUP 3 //!< Osc1 startup time: RCOsc periods. + +//! @} + + +/*! \name USB Definitions + */ +//! @{ + +//! Multiplexed pin used for USB_ID: AVR32_USBB_USB_ID_x_x. +//! To be selected according to the AVR32_USBB_USB_ID_x_x_PIN and +//! AVR32_USBB_USB_ID_x_x_FUNCTION definitions from . +#define USB_ID AVR32_USBB_USB_ID_0_0 + +//! Multiplexed pin used for USB_VBOF: AVR32_USBB_USB_VBOF_x_x. +//! To be selected according to the AVR32_USBB_USB_VBOF_x_x_PIN and +//! AVR32_USBB_USB_VBOF_x_x_FUNCTION definitions from . +#define USB_VBOF AVR32_USBB_USB_VBOF_0_0 + +//! Active level of the USB_VBOF output pin. +#define USB_VBOF_ACTIVE_LEVEL LOW + +//! USB overcurrent detection pin. +#define USB_OVERCURRENT_DETECT_PIN AVR32_PIN_PA20 + +//! @} + + +//! Number of LEDs. +#define LED_COUNT 4 + +/*! \name GPIO Connections of LEDs + */ +//! @{ +#define LED0_GPIO AVR32_PIN_PA07 +#define LED1_GPIO AVR32_PIN_PA08 +#define LED2_GPIO AVR32_PIN_PA21 +#define LED3_GPIO AVR32_PIN_PA22 +//! @} + +/*! \name PWM Channels of LEDs + */ +//! @{ +#define LED0_PWM 0 +#define LED1_PWM 1 +#define LED2_PWM 2 +#define LED3_PWM 6 +//! @} + +/*! \name PWM Functions of LEDs + */ +//! @{ +#define LED0_PWM_FUNCTION AVR32_PWM_PWM_0_0_FUNCTION +#define LED1_PWM_FUNCTION AVR32_PWM_PWM_1_0_FUNCTION +#define LED2_PWM_FUNCTION AVR32_PWM_PWM_2_0_FUNCTION +#define LED3_PWM_FUNCTION AVR32_PWM_PWM_6_0_FUNCTION +//! @} + +/*! \name Color Identifiers of LEDs to Use with LED Functions + */ +//! @{ +#define LED_MONO0_GREEN LED0 +#define LED_MONO1_GREEN LED1 +#define LED_MONO2_GREEN LED2 +#define LED_MONO3_GREEN LED3 +//! @} + + +/*! \name GPIO Connections of Push Buttons + */ +//! @{ +#define GPIO_PUSH_BUTTON_0 AVR32_PIN_PB02 +#define GPIO_PUSH_BUTTON_1 AVR32_PIN_PB03 +//! @} + + +/*! \name GPIO Connections of the Joystick + */ +//! @{ +#define GPIO_JOYSTICK_PUSH AVR32_PIN_PA13 +#define GPIO_JOYSTICK_LEFT AVR32_PIN_PB06 +#define GPIO_JOYSTICK_RIGHT AVR32_PIN_PB09 +#define GPIO_JOYSTICK_UP AVR32_PIN_PB07 +#define GPIO_JOYSTICK_DOWN AVR32_PIN_PB08 +//! @} + + +/*! \name ADC Connection of the Temperature Sensor + */ +//! @{ +#define ADC_TEMPERATURE_CHANNEL 7 +#define ADC_TEMPERATURE_PIN AVR32_ADC_AD_7_PIN +#define ADC_TEMPERATURE_FUNCTION AVR32_ADC_AD_7_FUNCTION +//! @} + + +/*! \name ADC Connection of the Light Sensor + */ +//! @{ +#define ADC_LIGHT_CHANNEL 6 +#define ADC_LIGHT_PIN AVR32_ADC_AD_6_PIN +#define ADC_LIGHT_FUNCTION AVR32_ADC_AD_6_FUNCTION +//! @} + + +/*! \name ADC Connections of the Accelerometer + */ +//! @{ +#define ADC_ACC_X_CHANNEL 1 +#define ADC_ACC_X_PIN AVR32_ADC_AD_1_PIN +#define ADC_ACC_X_FUNCTION AVR32_ADC_AD_1_FUNCTION +#define ADC_ACC_Y_CHANNEL 2 +#define ADC_ACC_Y_PIN AVR32_ADC_AD_2_PIN +#define ADC_ACC_Y_FUNCTION AVR32_ADC_AD_2_FUNCTION +#define ADC_ACC_Z_CHANNEL 3 +#define ADC_ACC_Z_PIN AVR32_ADC_AD_3_PIN +#define ADC_ACC_Z_FUNCTION AVR32_ADC_AD_3_FUNCTION +//! @} + + +/*! \name PWM Connections of Audio + */ +//! @{ +#define AUDIO_LOW_PWM_CHANNEL 5 +#define AUDIO_LOW_PWM_PIN AVR32_PWM_PWM_5_0_PIN +#define AUDIO_LOW_PWM_FUNCTION AVR32_PWM_PWM_5_0_FUNCTION +#define AUDIO_HIGH_PWM_CHANNEL 6 +#define AUDIO_HIGH_PWM_PIN AVR32_PWM_PWM_6_1_PIN +#define AUDIO_HIGH_PWM_FUNCTION AVR32_PWM_PWM_6_1_FUNCTION +//! @} + + +/*! \name SPI Connections of the AT45DBX Data Flash Memory + */ +//! @{ +#define AT45DBX_SPI (&AVR32_SPI) +#define AT45DBX_SPI_SCK_PIN AVR32_SPI_SCK_0_0_PIN +#define AT45DBX_SPI_SCK_FUNCTION AVR32_SPI_SCK_0_0_FUNCTION +#define AT45DBX_SPI_MISO_PIN AVR32_SPI_MISO_0_0_PIN +#define AT45DBX_SPI_MISO_FUNCTION AVR32_SPI_MISO_0_0_FUNCTION +#define AT45DBX_SPI_MOSI_PIN AVR32_SPI_MOSI_0_0_PIN +#define AT45DBX_SPI_MOSI_FUNCTION AVR32_SPI_MOSI_0_0_FUNCTION +#define AT45DBX_SPI_NPCS0_PIN AVR32_SPI_NPCS_0_0_PIN +#define AT45DBX_SPI_NPCS0_FUNCTION AVR32_SPI_NPCS_0_0_FUNCTION +//! @} + + +/*! \name GPIO and SPI Connections of the SD/MMC Connector + */ +//! @{ +#define SD_MMC_CARD_DETECT_PIN AVR32_PIN_PB00 +#define SD_MMC_WRITE_PROTECT_PIN AVR32_PIN_PB01 +#define SD_MMC_SPI (&AVR32_SPI) +#define SD_MMC_SPI_CS 1 +#define SD_MMC_SPI_SCK_PIN AVR32_SPI_SCK_0_0_PIN +#define SD_MMC_SPI_SCK_FUNCTION AVR32_SPI_SCK_0_0_FUNCTION +#define SD_MMC_SPI_MISO_PIN AVR32_SPI_MISO_0_0_PIN +#define SD_MMC_SPI_MISO_FUNCTION AVR32_SPI_MISO_0_0_FUNCTION +#define SD_MMC_SPI_MOSI_PIN AVR32_SPI_MOSI_0_0_PIN +#define SD_MMC_SPI_MOSI_FUNCTION AVR32_SPI_MOSI_0_0_FUNCTION +#define SD_MMC_SPI_NPCS_PIN AVR32_SPI_NPCS_1_0_PIN +#define SD_MMC_SPI_NPCS_FUNCTION AVR32_SPI_NPCS_1_0_FUNCTION +//! @} + + +#endif // _EVK1101_H_ diff --git a/20080212/Demo/lwIP_AVR32_UC3/BOARDS/EVK1101/led.c b/20080212/Demo/lwIP_AVR32_UC3/BOARDS/EVK1101/led.c new file mode 100644 index 000000000..70705769b --- /dev/null +++ b/20080212/Demo/lwIP_AVR32_UC3/BOARDS/EVK1101/led.c @@ -0,0 +1,305 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief AT32UC3B EVK1101 board LEDs support package. + * + * This file contains definitions and services related to the LED features of + * the EVK1101 board. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 AT32UC3B devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include +#include "preprocessor.h" +#include "compiler.h" +#include "evk1101.h" +#include "led.h" + + +//! Structure describing LED hardware connections. +typedef const struct +{ + struct + { + U32 PORT; //!< LED GPIO port. + U32 PIN_MASK; //!< Bit-mask of LED pin in GPIO port. + } GPIO; //!< LED GPIO descriptor. + struct + { + S32 CHANNEL; //!< LED PWM channel (< 0 if N/A). + S32 FUNCTION; //!< LED pin PWM function (< 0 if N/A). + } PWM; //!< LED PWM descriptor. +} tLED_DESCRIPTOR; + + +//! Hardware descriptors of all LEDs. +static tLED_DESCRIPTOR LED_DESCRIPTOR[LED_COUNT] = +{ +#define INSERT_LED_DESCRIPTOR(LED_NO, unused) \ + { \ + {LED##LED_NO##_GPIO / 32, 1 << (LED##LED_NO##_GPIO % 32)},\ + {LED##LED_NO##_PWM, LED##LED_NO##_PWM_FUNCTION } \ + }, + MREPEAT(LED_COUNT, INSERT_LED_DESCRIPTOR, ~) +#undef INSERT_LED_DESCRIPTOR +}; + + +//! Saved state of all LEDs. +static volatile U32 LED_State = (1 << LED_COUNT) - 1; + + +U32 LED_Read_Display(void) +{ + return LED_State; +} + + +void LED_Display(U32 leds) +{ + tLED_DESCRIPTOR *led_descriptor; + volatile avr32_gpio_port_t *led_gpio_port; + + leds &= (1 << LED_COUNT) - 1; + LED_State = leds; + for (led_descriptor = &LED_DESCRIPTOR[0]; + led_descriptor < LED_DESCRIPTOR + LED_COUNT; + led_descriptor++) + { + led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT]; + if (leds & 1) + { + led_gpio_port->ovrc = led_descriptor->GPIO.PIN_MASK; + } + else + { + led_gpio_port->ovrs = led_descriptor->GPIO.PIN_MASK; + } + led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK; + leds >>= 1; + } +} + + +U32 LED_Read_Display_Mask(U32 mask) +{ + return Rd_bits(LED_State, mask); +} + + +void LED_Display_Mask(U32 mask, U32 leds) +{ + tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1; + volatile avr32_gpio_port_t *led_gpio_port; + U8 led_shift; + + mask &= (1 << LED_COUNT) - 1; + Wr_bits(LED_State, mask, leds); + while (mask) + { + led_shift = 1 + ctz(mask); + led_descriptor += led_shift; + led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT]; + leds >>= led_shift - 1; + if (leds & 1) + { + led_gpio_port->ovrc = led_descriptor->GPIO.PIN_MASK; + } + else + { + led_gpio_port->ovrs = led_descriptor->GPIO.PIN_MASK; + } + led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK; + leds >>= 1; + mask >>= led_shift; + } +} + + +Bool LED_Test(U32 leds) +{ + return Tst_bits(LED_State, leds); +} + + +void LED_Off(U32 leds) +{ + tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1; + volatile avr32_gpio_port_t *led_gpio_port; + U8 led_shift; + + leds &= (1 << LED_COUNT) - 1; + Clr_bits(LED_State, leds); + while (leds) + { + led_shift = 1 + ctz(leds); + led_descriptor += led_shift; + led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT]; + led_gpio_port->ovrs = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK; + leds >>= led_shift; + } +} + + +void LED_On(U32 leds) +{ + tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1; + volatile avr32_gpio_port_t *led_gpio_port; + U8 led_shift; + + leds &= (1 << LED_COUNT) - 1; + Set_bits(LED_State, leds); + while (leds) + { + led_shift = 1 + ctz(leds); + led_descriptor += led_shift; + led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT]; + led_gpio_port->ovrc = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK; + leds >>= led_shift; + } +} + + +void LED_Toggle(U32 leds) +{ + tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1; + volatile avr32_gpio_port_t *led_gpio_port; + U8 led_shift; + + leds &= (1 << LED_COUNT) - 1; + Tgl_bits(LED_State, leds); + while (leds) + { + led_shift = 1 + ctz(leds); + led_descriptor += led_shift; + led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT]; + led_gpio_port->ovrt = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK; + leds >>= led_shift; + } +} + + +U32 LED_Read_Display_Field(U32 field) +{ + return Rd_bitfield(LED_State, field); +} + + +void LED_Display_Field(U32 field, U32 leds) +{ + LED_Display_Mask(field, leds << ctz(field)); +} + + +U8 LED_Get_Intensity(U32 led) +{ + tLED_DESCRIPTOR *led_descriptor; + + // Check that the argument value is valid. + led = ctz(led); + led_descriptor = &LED_DESCRIPTOR[led]; + if (led >= LED_COUNT || led_descriptor->PWM.CHANNEL < 0) return 0; + + // Return the duty cycle value if the LED PWM channel is enabled, else 0. + return (AVR32_PWM.sr & (1 << led_descriptor->PWM.CHANNEL)) ? + AVR32_PWM.channel[led_descriptor->PWM.CHANNEL].cdty : 0; +} + + +void LED_Set_Intensity(U32 leds, U8 intensity) +{ + tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1; + volatile avr32_pwm_channel_t *led_pwm_channel; + volatile avr32_gpio_port_t *led_gpio_port; + U8 led_shift; + + // For each specified LED... + for (leds &= (1 << LED_COUNT) - 1; leds; leds >>= led_shift) + { + // Select the next specified LED and check that it has a PWM channel. + led_shift = 1 + ctz(leds); + led_descriptor += led_shift; + if (led_descriptor->PWM.CHANNEL < 0) continue; + + // Initialize or update the LED PWM channel. + led_pwm_channel = &AVR32_PWM.channel[led_descriptor->PWM.CHANNEL]; + if (!(AVR32_PWM.sr & (1 << led_descriptor->PWM.CHANNEL))) + { + led_pwm_channel->cmr = (AVR32_PWM_CPRE_MCK << AVR32_PWM_CPRE_OFFSET) & + ~(AVR32_PWM_CALG_MASK | + AVR32_PWM_CPOL_MASK | + AVR32_PWM_CPD_MASK); + led_pwm_channel->cprd = 0x000000FF; + led_pwm_channel->cdty = intensity; + AVR32_PWM.ena = 1 << led_descriptor->PWM.CHANNEL; + } + else + { + AVR32_PWM.isr; + while (!(AVR32_PWM.isr & (1 << led_descriptor->PWM.CHANNEL))); + led_pwm_channel->cupd = intensity; + } + + // Switch the LED pin to its PWM function. + led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT]; + if (led_descriptor->PWM.FUNCTION & 0x1) + { + led_gpio_port->pmr0s = led_descriptor->GPIO.PIN_MASK; + } + else + { + led_gpio_port->pmr0c = led_descriptor->GPIO.PIN_MASK; + } + if (led_descriptor->PWM.FUNCTION & 0x2) + { + led_gpio_port->pmr1s = led_descriptor->GPIO.PIN_MASK; + } + else + { + led_gpio_port->pmr1c = led_descriptor->GPIO.PIN_MASK; + } + led_gpio_port->gperc = led_descriptor->GPIO.PIN_MASK; + } +} diff --git a/20080212/Demo/lwIP_AVR32_UC3/BOARDS/EVK1101/led.h b/20080212/Demo/lwIP_AVR32_UC3/BOARDS/EVK1101/led.h new file mode 100644 index 000000000..bf8948712 --- /dev/null +++ b/20080212/Demo/lwIP_AVR32_UC3/BOARDS/EVK1101/led.h @@ -0,0 +1,182 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief AT32UC3B EVK1101 board LEDs support package. + * + * This file contains definitions and services related to the LED features of + * the EVK1101 board. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 AT32UC3B devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef _LED_H_ +#define _LED_H_ + +#include "compiler.h" + + +/*! \name Identifiers of LEDs to Use with LED Functions + */ +//! @{ +#define LED0 0x01 +#define LED1 0x02 +#define LED2 0x04 +#define LED3 0x08 +//! @} + + +/*! \brief Gets the last state of all LEDs set through the LED API. + * + * \return State of all LEDs (1 bit per LED). + * + * \note The GPIO pin configuration of all LEDs is left unchanged. + */ +extern U32 LED_Read_Display(void); + +/*! \brief Sets the state of all LEDs. + * + * \param leds New state of all LEDs (1 bit per LED). + * + * \note The pins of all LEDs are set to GPIO output mode. + */ +extern void LED_Display(U32 leds); + +/*! \brief Gets the last state of the specified LEDs set through the LED API. + * + * \param mask LEDs of which to get the state (1 bit per LED). + * + * \return State of the specified LEDs (1 bit per LED). + * + * \note The GPIO pin configuration of all LEDs is left unchanged. + */ +extern U32 LED_Read_Display_Mask(U32 mask); + +/*! \brief Sets the state of the specified LEDs. + * + * \param mask LEDs of which to set the state (1 bit per LED). + * + * \param leds New state of the specified LEDs (1 bit per LED). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +extern void LED_Display_Mask(U32 mask, U32 leds); + +/*! \brief Tests the last state of the specified LEDs set through the LED API. + * + * \param leds LEDs of which to test the state (1 bit per LED). + * + * \return \c TRUE if at least one of the specified LEDs has a state on, else + * \c FALSE. + * + * \note The GPIO pin configuration of all LEDs is left unchanged. + */ +extern Bool LED_Test(U32 leds); + +/*! \brief Turns off the specified LEDs. + * + * \param leds LEDs to turn off (1 bit per LED). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +extern void LED_Off(U32 leds); + +/*! \brief Turns on the specified LEDs. + * + * \param leds LEDs to turn on (1 bit per LED). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +extern void LED_On(U32 leds); + +/*! \brief Toggles the specified LEDs. + * + * \param leds LEDs to toggle (1 bit per LED). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +extern void LED_Toggle(U32 leds); + +/*! \brief Gets as a bit-field the last state of the specified LEDs set through + * the LED API. + * + * \param field LEDs of which to get the state (1 bit per LED). + * + * \return State of the specified LEDs (1 bit per LED, beginning with the first + * specified LED). + * + * \note The GPIO pin configuration of all LEDs is left unchanged. + */ +extern U32 LED_Read_Display_Field(U32 field); + +/*! \brief Sets as a bit-field the state of the specified LEDs. + * + * \param field LEDs of which to set the state (1 bit per LED). + * \param leds New state of the specified LEDs (1 bit per LED, beginning with + * the first specified LED). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +extern void LED_Display_Field(U32 field, U32 leds); + +/*! \brief Gets the intensity of the specified LED. + * + * \param led LED of which to get the intensity (1 bit per LED; only the least + * significant set bit is used). + * + * \return Intensity of the specified LED (0x00 to 0xFF). + * + * \warning The PWM channel of the specified LED is supposed to be used only by + * this module. + * + * \note The GPIO pin configuration of all LEDs is left unchanged. + */ +extern U8 LED_Get_Intensity(U32 led); + +/*! \brief Sets the intensity of the specified LEDs. + * + * \param leds LEDs of which to set the intensity (1 bit per LED). + * \param intensity New intensity of the specified LEDs (0x00 to 0xFF). + * + * \warning The PWM channels of the specified LEDs are supposed to be used only + * by this module. + * + * \note The pins of the specified LEDs are set to PWM output mode. + */ +extern void LED_Set_Intensity(U32 leds, U8 intensity); + + +#endif // _LED_H_ diff --git a/20080212/Demo/lwIP_AVR32_UC3/BOARDS/board.h b/20080212/Demo/lwIP_AVR32_UC3/BOARDS/board.h new file mode 100644 index 000000000..346165ef6 --- /dev/null +++ b/20080212/Demo/lwIP_AVR32_UC3/BOARDS/board.h @@ -0,0 +1,82 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Standard board header file. + * + * This file includes the appropriate board header file according to the + * defined board. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include + +/*! \name Base Boards + */ +//! @{ +#define EVK1100 1 //!< AT32UC3A EVK1100 board. +#define EVK1101 2 //!< AT32UC3B EVK1101 board. +//! @} + +/*! \name Extension Boards + */ +//! @{ +#define EXT1102 1 //!< AT32UC3B EXT1102 board. +//! @} + +#if BOARD == EVK1100 +# include "EVK1100/evk1100.h" +#elif BOARD == EVK1101 +# include "EVK1101/evk1101.h" +#else +# error No known AVR32 board defined +#endif + +#if EXT_BOARD == EXT1102 +# include "EXT1102/ext1102.h" +#endif + + +#ifndef FRCOSC +# define FRCOSC AVR32_PM_RCOSC_FREQUENCY //!< Default RCOsc frequency. +#endif + + +#endif // _BOARD_H_ diff --git a/20080212/Demo/lwIP_AVR32_UC3/DRIVERS/FLASHC/flashc.c b/20080212/Demo/lwIP_AVR32_UC3/DRIVERS/FLASHC/flashc.c new file mode 100644 index 000000000..f9a2c6ec1 --- /dev/null +++ b/20080212/Demo/lwIP_AVR32_UC3/DRIVERS/FLASHC/flashc.c @@ -0,0 +1,1095 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief FLASHC driver for AVR32 UC3. + * + * AVR32 Flash Controller driver module. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with a FLASHC module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include +#include +#include "compiler.h" +#include "flashc.h" + + +/*! \name FLASHC Writable Bit-Field Registers + */ +//! @{ + +typedef union +{ + unsigned long fcr; + avr32_flashc_fcr_t FCR; +} u_avr32_flashc_fcr_t; + +typedef union +{ + unsigned long fcmd; + avr32_flashc_fcmd_t FCMD; +} u_avr32_flashc_fcmd_t; + +//! @} + + +/*! \name Flash Properties + */ +//! @{ + + +unsigned int flashc_get_flash_size(void) +{ + static const unsigned int FLASH_SIZE[1 << AVR32_FLASHC_FSR_FSZ_SIZE] = + { + 32 << 10, + 64 << 10, + 128 << 10, + 256 << 10, + 384 << 10, + 512 << 10, + 768 << 10, + 1024 << 10 + }; + return FLASH_SIZE[(AVR32_FLASHC.fsr & AVR32_FLASHC_FSR_FSZ_MASK) >> AVR32_FLASHC_FSR_FSZ_OFFSET]; +} + + +unsigned int flashc_get_page_count(void) +{ + return flashc_get_flash_size() / AVR32_FLASHC_PAGE_SIZE; +} + + +unsigned int flashc_get_page_count_per_region(void) +{ + return flashc_get_page_count() / AVR32_FLASHC_REGIONS; +} + + +unsigned int flashc_get_page_region(int page_number) +{ + return ((page_number >= 0) ? page_number : flashc_get_page_number()) / flashc_get_page_count_per_region(); +} + + +unsigned int flashc_get_region_first_page_number(unsigned int region) +{ + return region * flashc_get_page_count_per_region(); +} + + +//! @} + + +/*! \name FLASHC Control + */ +//! @{ + + +unsigned int flashc_get_wait_state(void) +{ + return (AVR32_FLASHC.fcr & AVR32_FLASHC_FCR_FWS_MASK) >> AVR32_FLASHC_FCR_FWS_OFFSET; +} + + +void flashc_set_wait_state(unsigned int wait_state) +{ + u_avr32_flashc_fcr_t u_avr32_flashc_fcr = {AVR32_FLASHC.fcr}; + u_avr32_flashc_fcr.FCR.fws = wait_state; + AVR32_FLASHC.fcr = u_avr32_flashc_fcr.fcr; +} + + +Bool flashc_is_ready_int_enabled(void) +{ + return ((AVR32_FLASHC.fcr & AVR32_FLASHC_FCR_FRDY_MASK) != 0); +} + + +void flashc_enable_ready_int(Bool enable) +{ + u_avr32_flashc_fcr_t u_avr32_flashc_fcr = {AVR32_FLASHC.fcr}; + u_avr32_flashc_fcr.FCR.frdy = (enable != FALSE); + AVR32_FLASHC.fcr = u_avr32_flashc_fcr.fcr; +} + + +Bool flashc_is_lock_error_int_enabled(void) +{ + return ((AVR32_FLASHC.fcr & AVR32_FLASHC_FCR_LOCKE_MASK) != 0); +} + + +void flashc_enable_lock_error_int(Bool enable) +{ + u_avr32_flashc_fcr_t u_avr32_flashc_fcr = {AVR32_FLASHC.fcr}; + u_avr32_flashc_fcr.FCR.locke = (enable != FALSE); + AVR32_FLASHC.fcr = u_avr32_flashc_fcr.fcr; +} + + +Bool flashc_is_prog_error_int_enabled(void) +{ + return ((AVR32_FLASHC.fcr & AVR32_FLASHC_FCR_PROGE_MASK) != 0); +} + + +void flashc_enable_prog_error_int(Bool enable) +{ + u_avr32_flashc_fcr_t u_avr32_flashc_fcr = {AVR32_FLASHC.fcr}; + u_avr32_flashc_fcr.FCR.proge = (enable != FALSE); + AVR32_FLASHC.fcr = u_avr32_flashc_fcr.fcr; +} + + +//! @} + + +/*! \name FLASHC Status + */ +//! @{ + + +Bool flashc_is_ready(void) +{ + return ((AVR32_FLASHC.fsr & AVR32_FLASHC_FSR_FRDY_MASK) != 0); +} + + +void flashc_default_wait_until_ready(void) +{ + while (!flashc_is_ready()); +} + + +void (*volatile flashc_wait_until_ready)(void) = flashc_default_wait_until_ready; + + +/*! \brief Gets the error status of the FLASHC. + * + * \return The error status of the FLASHC built up from + * \c AVR32_FLASHC_FSR_LOCKE_MASK and \c AVR32_FLASHC_FSR_PROGE_MASK. + * + * \warning This hardware error status is cleared by all functions reading the + * Flash Status Register (FSR). This function is therefore not part of + * the driver's API which instead presents \ref flashc_is_lock_error + * and \ref flashc_is_programming_error. + */ +static unsigned int flashc_get_error_status(void) +{ + return AVR32_FLASHC.fsr & (AVR32_FLASHC_FSR_LOCKE_MASK | + AVR32_FLASHC_FSR_PROGE_MASK); +} + + +//! Sticky error status of the FLASHC. +//! This variable is updated by functions that issue FLASHC commands. It +//! contains the cumulated FLASHC error status of all the FLASHC commands issued +//! by a function. +static unsigned int flashc_error_status = 0; + + +Bool flashc_is_lock_error(void) +{ + return ((flashc_error_status & AVR32_FLASHC_FSR_LOCKE_MASK) != 0); +} + + +Bool flashc_is_programming_error(void) +{ + return ((flashc_error_status & AVR32_FLASHC_FSR_PROGE_MASK) != 0); +} + + +//! @} + + +/*! \name FLASHC Command Control + */ +//! @{ + + +unsigned int flashc_get_command(void) +{ + return (AVR32_FLASHC.fcmd & AVR32_FLASHC_FCMD_CMD_MASK) >> AVR32_FLASHC_FCMD_CMD_OFFSET; +} + + +unsigned int flashc_get_page_number(void) +{ + return (AVR32_FLASHC.fcmd & AVR32_FLASHC_FCMD_PAGEN_MASK) >> AVR32_FLASHC_FCMD_PAGEN_OFFSET; +} + + +void flashc_issue_command(unsigned int command, int page_number) +{ + u_avr32_flashc_fcmd_t u_avr32_flashc_fcmd; + flashc_wait_until_ready(); + u_avr32_flashc_fcmd.fcmd = AVR32_FLASHC.fcmd; + u_avr32_flashc_fcmd.FCMD.cmd = command; + if (page_number >= 0) u_avr32_flashc_fcmd.FCMD.pagen = page_number; + u_avr32_flashc_fcmd.FCMD.key = AVR32_FLASHC_FCMD_KEY_KEY; + AVR32_FLASHC.fcmd = u_avr32_flashc_fcmd.fcmd; + flashc_error_status = flashc_get_error_status(); + flashc_wait_until_ready(); +} + + +//! @} + + +/*! \name FLASHC Global Commands + */ +//! @{ + + +void flashc_no_operation(void) +{ + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_NOP, -1); +} + + +void flashc_erase_all(void) +{ + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_EA, -1); +} + + +//! @} + + +/*! \name FLASHC Protection Mechanisms + */ +//! @{ + + +Bool flashc_is_security_bit_active(void) +{ + return ((AVR32_FLASHC.fsr & AVR32_FLASHC_FSR_SECURITY_MASK) != 0); +} + + +void flashc_activate_security_bit(void) +{ + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_SSB, -1); +} + + +unsigned int flashc_get_bootloader_protected_size(void) +{ + unsigned int bootprot = (1 << AVR32_FLASHC_FGPFR_BOOTPROT_SIZE) - 1 - + flashc_read_gp_fuse_bitfield(AVR32_FLASHC_FGPFR_BOOTPROT_OFFSET, + AVR32_FLASHC_FGPFR_BOOTPROT_SIZE); + return (bootprot) ? AVR32_FLASHC_PAGE_SIZE << bootprot : 0; +} + + +unsigned int flashc_set_bootloader_protected_size(unsigned int bootprot_size) +{ + flashc_set_gp_fuse_bitfield(AVR32_FLASHC_FGPFR_BOOTPROT_OFFSET, + AVR32_FLASHC_FGPFR_BOOTPROT_SIZE, + (1 << AVR32_FLASHC_FGPFR_BOOTPROT_SIZE) - 1 - + ((bootprot_size) ? + 32 - clz((((min(max(bootprot_size, AVR32_FLASHC_PAGE_SIZE << 1), + AVR32_FLASHC_PAGE_SIZE << + ((1 << AVR32_FLASHC_FGPFR_BOOTPROT_SIZE) - 1)) + + AVR32_FLASHC_PAGE_SIZE - 1) / + AVR32_FLASHC_PAGE_SIZE) << 1) - 1) - 1 : + 0)); + return flashc_get_bootloader_protected_size(); +} + + +Bool flashc_is_external_privileged_fetch_locked(void) +{ + return (!flashc_read_gp_fuse_bit(AVR32_FLASHC_FGPFR_EPFL_OFFSET)); +} + + +void flashc_lock_external_privileged_fetch(Bool lock) +{ + flashc_set_gp_fuse_bit(AVR32_FLASHC_FGPFR_EPFL_OFFSET, !lock); +} + + +Bool flashc_is_page_region_locked(int page_number) +{ + return flashc_is_region_locked(flashc_get_page_region(page_number)); +} + + +Bool flashc_is_region_locked(unsigned int region) +{ + return ((AVR32_FLASHC.fsr & AVR32_FLASHC_FSR_LOCK0_MASK << (region & (AVR32_FLASHC_REGIONS - 1))) != 0); +} + + +void flashc_lock_page_region(int page_number, Bool lock) +{ + flashc_issue_command((lock) ? AVR32_FLASHC_FCMD_CMD_LP : AVR32_FLASHC_FCMD_CMD_UP, page_number); +} + + +void flashc_lock_region(unsigned int region, Bool lock) +{ + flashc_lock_page_region(flashc_get_region_first_page_number(region), lock); +} + + +void flashc_lock_all_regions(Bool lock) +{ + unsigned int error_status = 0; + unsigned int region = AVR32_FLASHC_REGIONS; + while (region) + { + flashc_lock_region(--region, lock); + error_status |= flashc_error_status; + } + flashc_error_status = error_status; +} + + +//! @} + + +/*! \name Access to General-Purpose Fuses + */ +//! @{ + + +Bool flashc_read_gp_fuse_bit(unsigned int gp_fuse_bit) +{ + return ((AVR32_FLASHC.fgpfr & AVR32_FLASHC_FGPFR_GPF00_MASK << (gp_fuse_bit & 0x1F)) != 0); +} + + +U32 flashc_read_gp_fuse_bitfield(unsigned int pos, unsigned int width) +{ + return AVR32_FLASHC.fgpfr >> (AVR32_FLASHC_FGPFR_GPF00_OFFSET + (pos & 0x1F)) & + ((1 << min(width, 32)) - 1); +} + + +U8 flashc_read_gp_fuse_byte(unsigned int gp_fuse_byte) +{ + return AVR32_FLASHC.fgpfr >> (AVR32_FLASHC_FGPFR_GPF00_OFFSET + ((gp_fuse_byte & 0x03) << 3)); +} + + +U32 flashc_read_all_gp_fuses(void) +{ + return AVR32_FLASHC.fgpfr; +} + + +Bool flashc_erase_gp_fuse_bit(unsigned int gp_fuse_bit, Bool check) +{ + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_EGPB, gp_fuse_bit & 0x1F); + return (check) ? flashc_read_gp_fuse_bit(gp_fuse_bit) : TRUE; +} + + +Bool flashc_erase_gp_fuse_bitfield(unsigned int pos, unsigned int width, Bool check) +{ + unsigned int error_status = 0; + unsigned int gp_fuse_bit; + pos &= 0x1F; + width = min(width, 32); + for (gp_fuse_bit = pos; gp_fuse_bit < pos + width; gp_fuse_bit++) + { + flashc_erase_gp_fuse_bit(gp_fuse_bit, FALSE); + error_status |= flashc_error_status; + } + flashc_error_status = error_status; + return (check) ? (flashc_read_gp_fuse_bitfield(pos, width) == (1 << width) - 1) : TRUE; +} + + +Bool flashc_erase_gp_fuse_byte(unsigned int gp_fuse_byte, Bool check) +{ + unsigned int error_status; + unsigned int current_gp_fuse_byte; + U32 value = flashc_read_all_gp_fuses(); + flashc_erase_all_gp_fuses(FALSE); + error_status = flashc_error_status; + for (current_gp_fuse_byte = 0; current_gp_fuse_byte < 4; current_gp_fuse_byte++, value >>= 8) + { + if (current_gp_fuse_byte != gp_fuse_byte) + { + flashc_write_gp_fuse_byte(current_gp_fuse_byte, value); + error_status |= flashc_error_status; + } + } + flashc_error_status = error_status; + return (check) ? (flashc_read_gp_fuse_byte(gp_fuse_byte) == 0xFF) : TRUE; +} + + +Bool flashc_erase_all_gp_fuses(Bool check) +{ + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_EAGPF, -1); + return (check) ? (flashc_read_all_gp_fuses() == 0xFFFFFFFF) : TRUE; +} + + +void flashc_write_gp_fuse_bit(unsigned int gp_fuse_bit, Bool value) +{ + if (!value) + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_WGPB, gp_fuse_bit & 0x1F); +} + + +void flashc_write_gp_fuse_bitfield(unsigned int pos, unsigned int width, U32 value) +{ + unsigned int error_status = 0; + unsigned int gp_fuse_bit; + pos &= 0x1F; + width = min(width, 32); + for (gp_fuse_bit = pos; gp_fuse_bit < pos + width; gp_fuse_bit++, value >>= 1) + { + flashc_write_gp_fuse_bit(gp_fuse_bit, value & 0x01); + error_status |= flashc_error_status; + } + flashc_error_status = error_status; +} + + +void flashc_write_gp_fuse_byte(unsigned int gp_fuse_byte, U8 value) +{ + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_PGPFB, (gp_fuse_byte & 0x03) | value << 2); +} + + +void flashc_write_all_gp_fuses(U32 value) +{ + unsigned int error_status = 0; + unsigned int gp_fuse_byte; + for (gp_fuse_byte = 0; gp_fuse_byte < 4; gp_fuse_byte++, value >>= 8) + { + flashc_write_gp_fuse_byte(gp_fuse_byte, value); + error_status |= flashc_error_status; + } + flashc_error_status = error_status; +} + + +void flashc_set_gp_fuse_bit(unsigned int gp_fuse_bit, Bool value) +{ + if (value) + flashc_erase_gp_fuse_bit(gp_fuse_bit, FALSE); + else + flashc_write_gp_fuse_bit(gp_fuse_bit, FALSE); +} + + +void flashc_set_gp_fuse_bitfield(unsigned int pos, unsigned int width, U32 value) +{ + unsigned int error_status = 0; + unsigned int gp_fuse_bit; + pos &= 0x1F; + width = min(width, 32); + for (gp_fuse_bit = pos; gp_fuse_bit < pos + width; gp_fuse_bit++, value >>= 1) + { + flashc_set_gp_fuse_bit(gp_fuse_bit, value & 0x01); + error_status |= flashc_error_status; + } + flashc_error_status = error_status; +} + + +void flashc_set_gp_fuse_byte(unsigned int gp_fuse_byte, U8 value) +{ + unsigned int error_status; + switch (value) + { + case 0xFF: + flashc_erase_gp_fuse_byte(gp_fuse_byte, FALSE); + break; + case 0x00: + flashc_write_gp_fuse_byte(gp_fuse_byte, 0x00); + break; + default: + flashc_erase_gp_fuse_byte(gp_fuse_byte, FALSE); + error_status = flashc_error_status; + flashc_write_gp_fuse_byte(gp_fuse_byte, value); + flashc_error_status |= error_status; + } +} + + +void flashc_set_all_gp_fuses(U32 value) +{ + unsigned int error_status; + switch (value) + { + case 0xFFFFFFFF: + flashc_erase_all_gp_fuses(FALSE); + break; + case 0x00000000: + flashc_write_all_gp_fuses(0x00000000); + break; + default: + flashc_erase_all_gp_fuses(FALSE); + error_status = flashc_error_status; + flashc_write_all_gp_fuses(value); + flashc_error_status |= error_status; + } +} + + +//! @} + + +/*! \name Access to Flash Pages + */ +//! @{ + + +void flashc_clear_page_buffer(void) +{ + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_CPB, -1); +} + + +Bool flashc_is_page_erased(void) +{ + return ((AVR32_FLASHC.fsr & AVR32_FLASHC_FSR_QPRR_MASK) != 0); +} + + +Bool flashc_quick_page_read(int page_number) +{ + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_QPR, page_number); + return flashc_is_page_erased(); +} + + +Bool flashc_erase_page(int page_number, Bool check) +{ + Bool page_erased = TRUE; + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_EP, page_number); + if (check) + { + unsigned int error_status = flashc_error_status; + page_erased = flashc_quick_page_read(-1); + flashc_error_status |= error_status; + } + return page_erased; +} + + +Bool flashc_erase_all_pages(Bool check) +{ + Bool all_pages_erased = TRUE; + unsigned int error_status = 0; + unsigned int page_number = flashc_get_page_count(); + while (page_number) + { + all_pages_erased &= flashc_erase_page(--page_number, check); + error_status |= flashc_error_status; + } + flashc_error_status = error_status; + return all_pages_erased; +} + + +void flashc_write_page(int page_number) +{ + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_WP, page_number); +} + + +Bool flashc_check_user_page_erase(void) +{ + volatile U64 *user_page_ptr = (U64 *)AVR32_FLASHC_USER_PAGE; + while (user_page_ptr < (U64 *)(AVR32_FLASHC_USER_PAGE + AVR32_FLASHC_USER_PAGE_SIZE)) + { + if (*user_page_ptr++ != 0xFFFFFFFFFFFFFFFFULL) + return FALSE; + } + return TRUE; +} + + +Bool flashc_erase_user_page(Bool check) +{ + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_EUP, -1); + return (check) ? flashc_check_user_page_erase() : TRUE; +} + + +void flashc_write_user_page(void) +{ + flashc_issue_command(AVR32_FLASHC_FCMD_CMD_WUP, -1); +} + + +volatile void *flashc_memset8(volatile void *dst, U8 src, size_t nbytes, Bool erase) +{ + return flashc_memset16(dst, src | (U16)src << 8, nbytes, erase); +} + + +volatile void *flashc_memset16(volatile void *dst, U16 src, size_t nbytes, Bool erase) +{ + return flashc_memset32(dst, src | (U32)src << 16, nbytes, erase); +} + + +volatile void *flashc_memset32(volatile void *dst, U32 src, size_t nbytes, Bool erase) +{ + return flashc_memset64(dst, src | (U64)src << 32, nbytes, erase); +} + + +volatile void *flashc_memset64(volatile void *dst, U64 src, size_t nbytes, Bool erase) +{ + // Use aggregated pointers to have several alignments available for a same address. + UnionCVPtr flash_array_end; + UnionVPtr dest; + Union64 source = {0}; + StructCVPtr dest_end; + UnionCVPtr flash_page_source_end; + Bool incomplete_flash_page_end; + Union64 flash_dword; + UnionVPtr tmp; + unsigned int error_status = 0; + unsigned int i; + + // Reformat arguments. + flash_array_end.u8ptr = AVR32_FLASH + flashc_get_flash_size(); + dest.u8ptr = dst; + for (i = (Get_align((U32)dest.u8ptr, sizeof(U64)) - 1) & (sizeof(U64) - 1); + src; i = (i - 1) & (sizeof(U64) - 1)) + { + source.u8[i] = src; + src >>= 8; + } + dest_end.u8ptr = dest.u8ptr + nbytes; + + // If destination is outside flash, go to next flash page if any. + if (dest.u8ptr < AVR32_FLASH) + { + dest.u8ptr = AVR32_FLASH; + } + else if (flash_array_end.u8ptr <= dest.u8ptr && dest.u8ptr < AVR32_FLASHC_USER_PAGE) + { + dest.u8ptr = AVR32_FLASHC_USER_PAGE; + } + + // If end of destination is outside flash, move it to the end of the previous flash page if any. + if (dest_end.u8ptr > AVR32_FLASHC_USER_PAGE + AVR32_FLASHC_USER_PAGE_SIZE) + { + dest_end.u8ptr = AVR32_FLASHC_USER_PAGE + AVR32_FLASHC_USER_PAGE_SIZE; + } + else if (AVR32_FLASHC_USER_PAGE >= dest_end.u8ptr && dest_end.u8ptr > flash_array_end.u8ptr) + { + dest_end.u8ptr = flash_array_end.u8ptr; + } + + // Align each end of destination pointer with its natural boundary. + dest_end.u16ptr = (U16 *)Align_down((U32)dest_end.u8ptr, sizeof(U16)); + dest_end.u32ptr = (U32 *)Align_down((U32)dest_end.u16ptr, sizeof(U32)); + dest_end.u64ptr = (U64 *)Align_down((U32)dest_end.u32ptr, sizeof(U64)); + + // While end of destination is not reached... + while (dest.u8ptr < dest_end.u8ptr) + { + // Clear the page buffer in order to prepare data for a flash page write. + flashc_clear_page_buffer(); + error_status |= flashc_error_status; + + // Determine where the source data will end in the current flash page. + flash_page_source_end.u64ptr = + (U64 *)min((U32)dest_end.u64ptr, + Align_down((U32)dest.u8ptr, AVR32_FLASHC_PAGE_SIZE) + AVR32_FLASHC_PAGE_SIZE); + + // Determine if the current destination page has an incomplete end. + incomplete_flash_page_end = (Align_down((U32)dest.u8ptr, AVR32_FLASHC_PAGE_SIZE) >= + Align_down((U32)dest_end.u8ptr, AVR32_FLASHC_PAGE_SIZE)); + + // Use a flash double-word buffer to manage unaligned accesses. + flash_dword.u64 = source.u64; + + // If destination does not point to the beginning of the current flash page... + if (!Test_align((U32)dest.u8ptr, AVR32_FLASHC_PAGE_SIZE)) + { + // If page erase is requested... + if (erase) + { + // Fill the beginning of the page buffer with the current flash page data. + for (tmp.u8ptr = (U8 *)Align_down((U32)dest.u8ptr, AVR32_FLASHC_PAGE_SIZE); + tmp.u64ptr < (U64 *)Align_down((U32)dest.u8ptr, sizeof(U64)); + tmp.u64ptr++) + *tmp.u64ptr = *tmp.u64ptr; + } + + // If destination is not 64-bit aligned... + if (!Test_align((U32)dest.u8ptr, sizeof(U64))) + { + // If page erase is requested... + if (erase) + { + // Fill the beginning of the flash double-word buffer with the current flash page data. + for (i = 0; i < Get_align((U32)dest.u8ptr, sizeof(U64)); i++) + flash_dword.u8[i] = *tmp.u8ptr++; + } + // If page erase is not requested... + else + { + // Erase the beginning of the flash double-word buffer. + for (i = 0; i < Get_align((U32)dest.u8ptr, sizeof(U64)); i++) + flash_dword.u8[i] = 0xFF; + } + + // Align the destination pointer with its 64-bit boundary. + dest.u64ptr = (U64 *)Align_down((U32)dest.u8ptr, sizeof(U64)); + + // If the current destination double-word is not the last one... + if (dest.u64ptr < dest_end.u64ptr) + { + // Write the flash double-word buffer to the page buffer and reinitialize it. + *dest.u64ptr++ = flash_dword.u64; + flash_dword.u64 = source.u64; + } + } + } + + // Write the source data to the page buffer with 64-bit alignment. + for (i = flash_page_source_end.u64ptr - dest.u64ptr; i; i--) + *dest.u64ptr++ = source.u64; + + // If the current destination page has an incomplete end... + if (incomplete_flash_page_end) + { + // If page erase is requested... + if (erase) + { + tmp.u8ptr = (volatile U8 *)dest_end.u8ptr; + + // If end of destination is not 64-bit aligned... + if (!Test_align((U32)dest_end.u8ptr, sizeof(U64))) + { + // Fill the end of the flash double-word buffer with the current flash page data. + for (i = Get_align((U32)dest_end.u8ptr, sizeof(U64)); i < sizeof(U64); i++) + flash_dword.u8[i] = *tmp.u8ptr++; + + // Write the flash double-word buffer to the page buffer. + *dest.u64ptr++ = flash_dword.u64; + } + + // Fill the end of the page buffer with the current flash page data. + for (; !Test_align((U32)tmp.u64ptr, AVR32_FLASHC_PAGE_SIZE); tmp.u64ptr++) + *tmp.u64ptr = *tmp.u64ptr; + } + // If page erase is not requested but end of destination is not 64-bit aligned... + else if (!Test_align((U32)dest_end.u8ptr, sizeof(U64))) + { + // Erase the end of the flash double-word buffer. + for (i = Get_align((U32)dest_end.u8ptr, sizeof(U64)); i < sizeof(U64); i++) + flash_dword.u8[i] = 0xFF; + + // Write the flash double-word buffer to the page buffer. + *dest.u64ptr++ = flash_dword.u64; + } + } + + // If the current flash page is in the flash array... + if (dest.u8ptr <= AVR32_FLASHC_USER_PAGE) + { + // Erase the current page if requested and write it from the page buffer. + if (erase) + { + flashc_erase_page(-1, FALSE); + error_status |= flashc_error_status; + } + flashc_write_page(-1); + error_status |= flashc_error_status; + + // If the end of the flash array is reached, go to the User page. + if (dest.u8ptr >= flash_array_end.u8ptr) + dest.u8ptr = AVR32_FLASHC_USER_PAGE; + } + // If the current flash page is the User page... + else + { + // Erase the User page if requested and write it from the page buffer. + if (erase) + { + flashc_erase_user_page(FALSE); + error_status |= flashc_error_status; + } + flashc_write_user_page(); + error_status |= flashc_error_status; + } + } + + // Update the FLASHC error status. + flashc_error_status = error_status; + + // Return the initial destination pointer as the standard memset function does. + return dst; +} + + +volatile void *flashc_memcpy(volatile void *dst, const void *src, size_t nbytes, Bool erase) +{ + // Use aggregated pointers to have several alignments available for a same address. + UnionCVPtr flash_array_end; + UnionVPtr dest; + UnionCPtr source; + StructCVPtr dest_end; + UnionCVPtr flash_page_source_end; + Bool incomplete_flash_page_end; + Union64 flash_dword; + Bool flash_dword_pending = FALSE; + UnionVPtr tmp; + unsigned int error_status = 0; + unsigned int i, j; + + // Reformat arguments. + flash_array_end.u8ptr = AVR32_FLASH + flashc_get_flash_size(); + dest.u8ptr = dst; + source.u8ptr = src; + dest_end.u8ptr = dest.u8ptr + nbytes; + + // If destination is outside flash, go to next flash page if any. + if (dest.u8ptr < AVR32_FLASH) + { + source.u8ptr += AVR32_FLASH - dest.u8ptr; + dest.u8ptr = AVR32_FLASH; + } + else if (flash_array_end.u8ptr <= dest.u8ptr && dest.u8ptr < AVR32_FLASHC_USER_PAGE) + { + source.u8ptr += AVR32_FLASHC_USER_PAGE - dest.u8ptr; + dest.u8ptr = AVR32_FLASHC_USER_PAGE; + } + + // If end of destination is outside flash, move it to the end of the previous flash page if any. + if (dest_end.u8ptr > AVR32_FLASHC_USER_PAGE + AVR32_FLASHC_USER_PAGE_SIZE) + { + dest_end.u8ptr = AVR32_FLASHC_USER_PAGE + AVR32_FLASHC_USER_PAGE_SIZE; + } + else if (AVR32_FLASHC_USER_PAGE >= dest_end.u8ptr && dest_end.u8ptr > flash_array_end.u8ptr) + { + dest_end.u8ptr = flash_array_end.u8ptr; + } + + // Align each end of destination pointer with its natural boundary. + dest_end.u16ptr = (U16 *)Align_down((U32)dest_end.u8ptr, sizeof(U16)); + dest_end.u32ptr = (U32 *)Align_down((U32)dest_end.u16ptr, sizeof(U32)); + dest_end.u64ptr = (U64 *)Align_down((U32)dest_end.u32ptr, sizeof(U64)); + + // While end of destination is not reached... + while (dest.u8ptr < dest_end.u8ptr) + { + // Clear the page buffer in order to prepare data for a flash page write. + flashc_clear_page_buffer(); + error_status |= flashc_error_status; + + // Determine where the source data will end in the current flash page. + flash_page_source_end.u64ptr = + (U64 *)min((U32)dest_end.u64ptr, + Align_down((U32)dest.u8ptr, AVR32_FLASHC_PAGE_SIZE) + AVR32_FLASHC_PAGE_SIZE); + + // Determine if the current destination page has an incomplete end. + incomplete_flash_page_end = (Align_down((U32)dest.u8ptr, AVR32_FLASHC_PAGE_SIZE) >= + Align_down((U32)dest_end.u8ptr, AVR32_FLASHC_PAGE_SIZE)); + + // If destination does not point to the beginning of the current flash page... + if (!Test_align((U32)dest.u8ptr, AVR32_FLASHC_PAGE_SIZE)) + { + // If page erase is requested... + if (erase) + { + // Fill the beginning of the page buffer with the current flash page data. + for (tmp.u8ptr = (U8 *)Align_down((U32)dest.u8ptr, AVR32_FLASHC_PAGE_SIZE); + tmp.u64ptr < (U64 *)Align_down((U32)dest.u8ptr, sizeof(U64)); + tmp.u64ptr++) + *tmp.u64ptr = *tmp.u64ptr; + } + + // If destination is not 64-bit aligned... + if (!Test_align((U32)dest.u8ptr, sizeof(U64))) + { + // If page erase is requested... + if (erase) + { + // Fill the beginning of the flash double-word buffer with the current flash page data. + for (i = 0; i < Get_align((U32)dest.u8ptr, sizeof(U64)); i++) + flash_dword.u8[i] = *tmp.u8ptr++; + } + // If page erase is not requested... + else + { + // Erase the beginning of the flash double-word buffer. + for (i = 0; i < Get_align((U32)dest.u8ptr, sizeof(U64)); i++) + flash_dword.u8[i] = 0xFF; + } + + // Fill the end of the flash double-word buffer with the source data. + for (; i < sizeof(U64); i++) + flash_dword.u8[i] = *source.u8ptr++; + + // Align the destination pointer with its 64-bit boundary. + dest.u64ptr = (U64 *)Align_down((U32)dest.u8ptr, sizeof(U64)); + + // If the current destination double-word is not the last one... + if (dest.u64ptr < dest_end.u64ptr) + { + // Write the flash double-word buffer to the page buffer. + *dest.u64ptr++ = flash_dword.u64; + } + // If the current destination double-word is the last one, the flash + // double-word buffer must be kept for later. + else flash_dword_pending = TRUE; + } + } + + // Read the source data with the maximal possible alignment and write it to + // the page buffer with 64-bit alignment. + switch (Get_align((U32)source.u8ptr, sizeof(U32))) + { + case 0: + for (i = flash_page_source_end.u64ptr - dest.u64ptr; i; i--) + *dest.u64ptr++ = *source.u64ptr++; + break; + + case sizeof(U16): + for (i = flash_page_source_end.u64ptr - dest.u64ptr; i; i--) + { + for (j = 0; j < sizeof(U64) / sizeof(U16); j++) flash_dword.u16[j] = *source.u16ptr++; + *dest.u64ptr++ = flash_dword.u64; + } + break; + + default: + for (i = flash_page_source_end.u64ptr - dest.u64ptr; i; i--) + { + for (j = 0; j < sizeof(U64); j++) flash_dword.u8[j] = *source.u8ptr++; + *dest.u64ptr++ = flash_dword.u64; + } + } + + // If the current destination page has an incomplete end... + if (incomplete_flash_page_end) + { + // If the flash double-word buffer is in use, do not initialize it. + if (flash_dword_pending) i = Get_align((U32)dest_end.u8ptr, sizeof(U64)); + // If the flash double-word buffer is free... + else + { + // Fill the beginning of the flash double-word buffer with the source data. + for (i = 0; i < Get_align((U32)dest_end.u8ptr, sizeof(U64)); i++) + flash_dword.u8[i] = *source.u8ptr++; + } + + // If page erase is requested... + if (erase) + { + tmp.u8ptr = (volatile U8 *)dest_end.u8ptr; + + // If end of destination is not 64-bit aligned... + if (!Test_align((U32)dest_end.u8ptr, sizeof(U64))) + { + // Fill the end of the flash double-word buffer with the current flash page data. + for (; i < sizeof(U64); i++) + flash_dword.u8[i] = *tmp.u8ptr++; + + // Write the flash double-word buffer to the page buffer. + *dest.u64ptr++ = flash_dword.u64; + } + + // Fill the end of the page buffer with the current flash page data. + for (; !Test_align((U32)tmp.u64ptr, AVR32_FLASHC_PAGE_SIZE); tmp.u64ptr++) + *tmp.u64ptr = *tmp.u64ptr; + } + // If page erase is not requested but end of destination is not 64-bit aligned... + else if (!Test_align((U32)dest_end.u8ptr, sizeof(U64))) + { + // Erase the end of the flash double-word buffer. + for (; i < sizeof(U64); i++) + flash_dword.u8[i] = 0xFF; + + // Write the flash double-word buffer to the page buffer. + *dest.u64ptr++ = flash_dword.u64; + } + } + + // If the current flash page is in the flash array... + if (dest.u8ptr <= AVR32_FLASHC_USER_PAGE) + { + // Erase the current page if requested and write it from the page buffer. + if (erase) + { + flashc_erase_page(-1, FALSE); + error_status |= flashc_error_status; + } + flashc_write_page(-1); + error_status |= flashc_error_status; + + // If the end of the flash array is reached, go to the User page. + if (dest.u8ptr >= flash_array_end.u8ptr) + { + source.u8ptr += AVR32_FLASHC_USER_PAGE - dest.u8ptr; + dest.u8ptr = AVR32_FLASHC_USER_PAGE; + } + } + // If the current flash page is the User page... + else + { + // Erase the User page if requested and write it from the page buffer. + if (erase) + { + flashc_erase_user_page(FALSE); + error_status |= flashc_error_status; + } + flashc_write_user_page(); + error_status |= flashc_error_status; + } + } + + // Update the FLASHC error status. + flashc_error_status = error_status; + + // Return the initial destination pointer as the standard memcpy function does. + return dst; +} + + +//! @} diff --git a/20080212/Demo/lwIP_AVR32_UC3/DRIVERS/FLASHC/flashc.h b/20080212/Demo/lwIP_AVR32_UC3/DRIVERS/FLASHC/flashc.h new file mode 100644 index 000000000..fec9d08a2 --- /dev/null +++ b/20080212/Demo/lwIP_AVR32_UC3/DRIVERS/FLASHC/flashc.h @@ -0,0 +1,885 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief FLASHC driver for AVR32 UC3. + * + * AVR32 Flash Controller driver module. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with a FLASHC module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef _FLASHC_H_ +#define _FLASHC_H_ + +#include +#include +#include "compiler.h" + + +//! Number of flash regions defined by the FLASHC. +#define AVR32_FLASHC_REGIONS (AVR32_FLASHC_FLASH_SIZE /\ + (AVR32_FLASHC_PAGES_PR_REGION * AVR32_FLASHC_PAGE_SIZE)) + + +/*! \name Flash Properties + */ +//! @{ + +/*! \brief Gets the size of the whole flash array. + * + * \return The size of the whole flash array in bytes. + */ +extern unsigned int flashc_get_flash_size(void); + +/*! \brief Gets the total number of pages in the flash array. + * + * \return The total number of pages in the flash array. + */ +extern unsigned int flashc_get_page_count(void); + +/*! \brief Gets the number of pages in each flash region. + * + * \return The number of pages in each flash region. + */ +extern unsigned int flashc_get_page_count_per_region(void); + +/*! \brief Gets the region number of a page. + * + * \param page_number The page number: + * \arg \c 0 to (flashc_get_page_count() - 1): a page number within + * the flash array; + * \arg < 0: the current page number. + * + * \return The region number of the specified page. + */ +extern unsigned int flashc_get_page_region(int page_number); + +/*! \brief Gets the number of the first page of a region. + * + * \param region The region number: \c 0 to (AVR32_FLASHC_REGIONS - 1). + * + * \return The number of the first page of the specified region. + */ +extern unsigned int flashc_get_region_first_page_number(unsigned int region); + +//! @} + + +/*! \name FLASHC Control + */ +//! @{ + +/*! \brief Gets the number of wait states of flash read accesses. + * + * \return The number of wait states of flash read accesses. + */ +extern unsigned int flashc_get_wait_state(void); + +/*! \brief Sets the number of wait states of flash read accesses. + * + * \param wait_state The number of wait states of flash read accesses: \c 0 to + * \c 1. + */ +extern void flashc_set_wait_state(unsigned int wait_state); + +/*! \brief Tells whether the Flash Ready interrupt is enabled. + * + * \return Whether the Flash Ready interrupt is enabled. + */ +extern Bool flashc_is_ready_int_enabled(void); + +/*! \brief Enables or disables the Flash Ready interrupt. + * + * \param enable Whether to enable the Flash Ready interrupt: \c TRUE or + * \c FALSE. + */ +extern void flashc_enable_ready_int(Bool enable); + +/*! \brief Tells whether the Lock Error interrupt is enabled. + * + * \return Whether the Lock Error interrupt is enabled. + */ +extern Bool flashc_is_lock_error_int_enabled(void); + +/*! \brief Enables or disables the Lock Error interrupt. + * + * \param enable Whether to enable the Lock Error interrupt: \c TRUE or + * \c FALSE. + */ +extern void flashc_enable_lock_error_int(Bool enable); + +/*! \brief Tells whether the Programming Error interrupt is enabled. + * + * \return Whether the Programming Error interrupt is enabled. + */ +extern Bool flashc_is_prog_error_int_enabled(void); + +/*! \brief Enables or disables the Programming Error interrupt. + * + * \param enable Whether to enable the Programming Error interrupt: \c TRUE or + * \c FALSE. + */ +extern void flashc_enable_prog_error_int(Bool enable); + +//! @} + + +/*! \name FLASHC Status + */ +//! @{ + +/*! \brief Tells whether the FLASHC is ready to run a new command. + * + * \return Whether the FLASHC is ready to run a new command. + */ +extern Bool flashc_is_ready(void); + +/*! \brief Waits actively until the FLASHC is ready to run a new command. + * + * This is the default function assigned to \ref flashc_wait_until_ready. + */ +extern void flashc_default_wait_until_ready(void); + +//! Pointer to the function used by the driver when it needs to wait until the +//! FLASHC is ready to run a new command. +//! The default function is \ref flashc_default_wait_until_ready. +//! The user may change this pointer to use another implementation. +extern void (*volatile flashc_wait_until_ready)(void); + +/*! \brief Tells whether a Lock Error has occurred during the last function + * called that issued one or more FLASHC commands. + * + * \return Whether a Lock Error has occurred during the last function called + * that issued one or more FLASHC commands. + */ +extern Bool flashc_is_lock_error(void); + +/*! \brief Tells whether a Programming Error has occurred during the last + * function called that issued one or more FLASHC commands. + * + * \return Whether a Programming Error has occurred during the last function + * called that issued one or more FLASHC commands. + */ +extern Bool flashc_is_programming_error(void); + +//! @} + + +/*! \name FLASHC Command Control + */ +//! @{ + +/*! \brief Gets the last issued FLASHC command. + * + * \return The last issued FLASHC command. + */ +extern unsigned int flashc_get_command(void); + +/*! \brief Gets the current FLASHC page number. + * + * \return The current FLASHC page number. + */ +extern unsigned int flashc_get_page_number(void); + +/*! \brief Issues a FLASHC command. + * + * \param command The command: \c AVR32_FLASHC_FCMD_CMD_x. + * \param page_number The page number to apply the command to: + * \arg \c 0 to (flashc_get_page_count() - 1): a page number within + * the flash array; + * \arg < 0: use this to apply the command to the current page number + * or if the command does not apply to any page number; + * \arg this argument may have other meanings according to the command. See + * the FLASHC chapter of the MCU datasheet. + * + * \warning A Lock Error is issued if the command violates the protection + * mechanism. + * + * \warning A Programming Error is issued if the command is invalid. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern void flashc_issue_command(unsigned int command, int page_number); + +//! @} + + +/*! \name FLASHC Global Commands + */ +//! @{ + +/*! \brief Issues a No Operation command to the FLASHC. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern void flashc_no_operation(void); + +/*! \brief Issues an Erase All command to the FLASHC. + * + * This command erases all bits in the flash array, the general-purpose fuse + * bits and the Security bit. The User page is not erased. + * + * This command also ensures that all volatile memories, such as register file + * and RAMs, are erased before the Security bit is erased, i.e. deactivated. + * + * \warning A Lock Error is issued if at least one region is locked or the + * bootloader protection is active. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note An erase operation can only set bits. + */ +extern void flashc_erase_all(void); + +//! @} + + +/*! \name FLASHC Protection Mechanisms + */ +//! @{ + +/*! \brief Tells whether the Security bit is active. + * + * \return Whether the Security bit is active. + */ +extern Bool flashc_is_security_bit_active(void); + +/*! \brief Activates the Security bit. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern void flashc_activate_security_bit(void); + +/*! \brief Gets the bootloader protected size. + * + * \return The bootloader protected size in bytes. + */ +extern unsigned int flashc_get_bootloader_protected_size(void); + +/*! \brief Sets the bootloader protected size. + * + * \param bootprot_size The wanted bootloader protected size in bytes. If this + * size is not supported, the actual size will be the + * nearest greater available size or the maximal possible + * size if the requested size is too large. + * + * \return The actual bootloader protected size in bytes. + * + * \warning A Lock Error is issued if the Security bit is active. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern unsigned int flashc_set_bootloader_protected_size(unsigned int bootprot_size); + +/*! \brief Tells whether external privileged fetch is locked. + * + * \return Whether external privileged fetch is locked. + */ +extern Bool flashc_is_external_privileged_fetch_locked(void); + +/*! \brief Locks or unlocks external privileged fetch. + * + * \param lock Whether to lock external privileged fetch: \c TRUE or \c FALSE. + * + * \warning A Lock Error is issued if the Security bit is active. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern void flashc_lock_external_privileged_fetch(Bool lock); + +/*! \brief Tells whether the region of a page is locked. + * + * \param page_number The page number: + * \arg \c 0 to (flashc_get_page_count() - 1): a page number within + * the flash array; + * \arg < 0: the current page number. + * + * \return Whether the region of the specified page is locked. + */ +extern Bool flashc_is_page_region_locked(int page_number); + +/*! \brief Tells whether a region is locked. + * + * \param region The region number: \c 0 to (AVR32_FLASHC_REGIONS - 1). + * + * \return Whether the specified region is locked. + */ +extern Bool flashc_is_region_locked(unsigned int region); + +/*! \brief Locks or unlocks the region of a page. + * + * \param page_number The page number: + * \arg \c 0 to (flashc_get_page_count() - 1): a page number within + * the flash array; + * \arg < 0: the current page number. + * \param lock Whether to lock the region of the specified page: \c TRUE or + * \c FALSE. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern void flashc_lock_page_region(int page_number, Bool lock); + +/*! \brief Locks or unlocks a region. + * + * \param region The region number: \c 0 to (AVR32_FLASHC_REGIONS - 1). + * \param lock Whether to lock the specified region: \c TRUE or \c FALSE. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern void flashc_lock_region(unsigned int region, Bool lock); + +/*! \brief Locks or unlocks all regions. + * + * \param lock Whether to lock the regions: \c TRUE or \c FALSE. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern void flashc_lock_all_regions(Bool lock); + +//! @} + + +/*! \name Access to General-Purpose Fuses + */ +//! @{ + +/*! \brief Reads a general-purpose fuse bit. + * + * \param gp_fuse_bit The general-purpose fuse bit: \c 0 to \c 31. + * + * \return The value of the specified general-purpose fuse bit. + */ +extern Bool flashc_read_gp_fuse_bit(unsigned int gp_fuse_bit); + +/*! \brief Reads a general-purpose fuse bit-field. + * + * \param pos The bit-position of the general-purpose fuse bit-field: \c 0 to + * \c 31. + * \param width The bit-width of the general-purpose fuse bit-field: \c 0 to + * \c 32. + * + * \return The value of the specified general-purpose fuse bit-field. + */ +extern U32 flashc_read_gp_fuse_bitfield(unsigned int pos, unsigned int width); + +/*! \brief Reads a general-purpose fuse byte. + * + * \param gp_fuse_byte The general-purpose fuse byte: \c 0 to \c 3. + * + * \return The value of the specified general-purpose fuse byte. + */ +extern U8 flashc_read_gp_fuse_byte(unsigned int gp_fuse_byte); + +/*! \brief Reads all general-purpose fuses. + * + * \return The value of all general-purpose fuses as a word. + */ +extern U32 flashc_read_all_gp_fuses(void); + +/*! \brief Erases a general-purpose fuse bit. + * + * \param gp_fuse_bit The general-purpose fuse bit: \c 0 to \c 31. + * \param check Whether to check erase: \c TRUE or \c FALSE. + * + * \return Whether the erase succeeded or always \c TRUE if erase check was not + * requested. + * + * \warning A Lock Error is issued if the Security bit is active and the command + * is applied to BOOTPROT or EPFL fuses. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note An erase operation can only set bits. + */ +extern Bool flashc_erase_gp_fuse_bit(unsigned int gp_fuse_bit, Bool check); + +/*! \brief Erases a general-purpose fuse bit-field. + * + * \param pos The bit-position of the general-purpose fuse bit-field: \c 0 to + * \c 31. + * \param width The bit-width of the general-purpose fuse bit-field: \c 0 to + * \c 32. + * \param check Whether to check erase: \c TRUE or \c FALSE. + * + * \return Whether the erase succeeded or always \c TRUE if erase check was not + * requested. + * + * \warning A Lock Error is issued if the Security bit is active and the command + * is applied to BOOTPROT or EPFL fuses. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note An erase operation can only set bits. + */ +extern Bool flashc_erase_gp_fuse_bitfield(unsigned int pos, unsigned int width, Bool check); + +/*! \brief Erases a general-purpose fuse byte. + * + * \param gp_fuse_byte The general-purpose fuse byte: \c 0 to \c 3. + * \param check Whether to check erase: \c TRUE or \c FALSE. + * + * \return Whether the erase succeeded or always \c TRUE if erase check was not + * requested. + * + * \warning A Lock Error is issued if the Security bit is active. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note An erase operation can only set bits. + */ +extern Bool flashc_erase_gp_fuse_byte(unsigned int gp_fuse_byte, Bool check); + +/*! \brief Erases all general-purpose fuses. + * + * \param check Whether to check erase: \c TRUE or \c FALSE. + * + * \return Whether the erase succeeded or always \c TRUE if erase check was not + * requested. + * + * \warning A Lock Error is issued if the Security bit is active. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note An erase operation can only set bits. + */ +extern Bool flashc_erase_all_gp_fuses(Bool check); + +/*! \brief Writes a general-purpose fuse bit. + * + * \param gp_fuse_bit The general-purpose fuse bit: \c 0 to \c 31. + * \param value The value of the specified general-purpose fuse bit. + * + * \warning A Lock Error is issued if the Security bit is active and the command + * is applied to BOOTPROT or EPFL fuses. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note A write operation can only clear bits. + */ +extern void flashc_write_gp_fuse_bit(unsigned int gp_fuse_bit, Bool value); + +/*! \brief Writes a general-purpose fuse bit-field. + * + * \param pos The bit-position of the general-purpose fuse bit-field: \c 0 to + * \c 31. + * \param width The bit-width of the general-purpose fuse bit-field: \c 0 to + * \c 32. + * \param value The value of the specified general-purpose fuse bit-field. + * + * \warning A Lock Error is issued if the Security bit is active and the command + * is applied to BOOTPROT or EPFL fuses. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note A write operation can only clear bits. + */ +extern void flashc_write_gp_fuse_bitfield(unsigned int pos, unsigned int width, U32 value); + +/*! \brief Writes a general-purpose fuse byte. + * + * \param gp_fuse_byte The general-purpose fuse byte: \c 0 to \c 3. + * \param value The value of the specified general-purpose fuse byte. + * + * \warning A Lock Error is issued if the Security bit is active. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note A write operation can only clear bits. + */ +extern void flashc_write_gp_fuse_byte(unsigned int gp_fuse_byte, U8 value); + +/*! \brief Writes all general-purpose fuses. + * + * \param value The value of all general-purpose fuses as a word. + * + * \warning A Lock Error is issued if the Security bit is active. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note A write operation can only clear bits. + */ +extern void flashc_write_all_gp_fuses(U32 value); + +/*! \brief Sets a general-purpose fuse bit with the appropriate erase and write + * operations. + * + * \param gp_fuse_bit The general-purpose fuse bit: \c 0 to \c 31. + * \param value The value of the specified general-purpose fuse bit. + * + * \warning A Lock Error is issued if the Security bit is active and the command + * is applied to BOOTPROT or EPFL fuses. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern void flashc_set_gp_fuse_bit(unsigned int gp_fuse_bit, Bool value); + +/*! \brief Sets a general-purpose fuse bit-field with the appropriate erase and + * write operations. + * + * \param pos The bit-position of the general-purpose fuse bit-field: \c 0 to + * \c 31. + * \param width The bit-width of the general-purpose fuse bit-field: \c 0 to + * \c 32. + * \param value The value of the specified general-purpose fuse bit-field. + * + * \warning A Lock Error is issued if the Security bit is active and the command + * is applied to BOOTPROT or EPFL fuses. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern void flashc_set_gp_fuse_bitfield(unsigned int pos, unsigned int width, U32 value); + +/*! \brief Sets a general-purpose fuse byte with the appropriate erase and write + * operations. + * + * \param gp_fuse_byte The general-purpose fuse byte: \c 0 to \c 3. + * \param value The value of the specified general-purpose fuse byte. + * + * \warning A Lock Error is issued if the Security bit is active. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern void flashc_set_gp_fuse_byte(unsigned int gp_fuse_byte, U8 value); + +/*! \brief Sets all general-purpose fuses with the appropriate erase and write + * operations. + * + * \param value The value of all general-purpose fuses as a word. + * + * \warning A Lock Error is issued if the Security bit is active. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern void flashc_set_all_gp_fuses(U32 value); + +//! @} + + +/*! \name Access to Flash Pages + */ +//! @{ + +/*! \brief Clears the page buffer. + * + * This command resets all bits in the page buffer to one. Write accesses to the + * page buffer can only change page buffer bits from one to zero. + * + * \warning The page buffer is not automatically reset after a page write. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern void flashc_clear_page_buffer(void); + +/*! \brief Tells whether the page to which the last Quick Page Read command was + * applied was erased. + * + * \return Whether the page to which the last Quick Page Read command was + * applied was erased. + */ +extern Bool flashc_is_page_erased(void); + +/*! \brief Applies the Quick Page Read command to a page. + * + * \param page_number The page number: + * \arg \c 0 to (flashc_get_page_count() - 1): a page number within + * the flash array; + * \arg < 0: the current page number. + * + * \return Whether the specified page is erased. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern Bool flashc_quick_page_read(int page_number); + +/*! \brief Erases a page. + * + * \param page_number The page number: + * \arg \c 0 to (flashc_get_page_count() - 1): a page number within + * the flash array; + * \arg < 0: the current page number. + * \param check Whether to check erase: \c TRUE or \c FALSE. + * + * \return Whether the erase succeeded or always \c TRUE if erase check was not + * requested. + * + * \warning A Lock Error is issued if the command is applied to a page belonging + * to a locked region or to the bootloader protected area. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note An erase operation can only set bits. + */ +extern Bool flashc_erase_page(int page_number, Bool check); + +/*! \brief Erases all pages within the flash array. + * + * \param check Whether to check erase: \c TRUE or \c FALSE. + * + * \return Whether the erase succeeded or always \c TRUE if erase check was not + * requested. + * + * \warning A Lock Error is issued if at least one region is locked or the + * bootloader protection is active. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note An erase operation can only set bits. + */ +extern Bool flashc_erase_all_pages(Bool check); + +/*! \brief Writes a page from the page buffer. + * + * \param page_number The page number: + * \arg \c 0 to (flashc_get_page_count() - 1): a page number within + * the flash array; + * \arg < 0: the current page number. + * + * \warning A Lock Error is issued if the command is applied to a page belonging + * to a locked region or to the bootloader protected area. + * + * \warning The page buffer is not automatically reset after a page write. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note A write operation can only clear bits. + */ +extern void flashc_write_page(int page_number); + +/*! \brief Checks whether the User page is erased. + * + * \return Whether the User page is erased. + */ +extern Bool flashc_check_user_page_erase(void); + +/*! \brief Erases the User page. + * + * \param check Whether to check erase: \c TRUE or \c FALSE. + * + * \return Whether the erase succeeded or always \c TRUE if erase check was not + * requested. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note An erase operation can only set bits. + */ +extern Bool flashc_erase_user_page(Bool check); + +/*! \brief Writes the User page from the page buffer. + * + * \warning The page buffer is not automatically reset after a page write. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + * + * \note A write operation can only clear bits. + */ +extern void flashc_write_user_page(void); + +/*! \brief Copies \a nbytes bytes to the flash destination pointed to by \a dst + * from the repeated \a src source byte. + * + * The destination areas that are not within the flash array or the User page + * are ignored. + * + * All pointer and size alignments are supported. + * + * \param dst Pointer to flash destination. + * \param src Source byte. + * \param nbytes Number of bytes to set. + * \param erase Whether to erase before writing: \c TRUE or \c FALSE. + * + * \return The value of \a dst. + * + * \warning A Lock Error is issued if the command is applied to pages belonging + * to a locked region or to the bootloader protected area. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern volatile void *flashc_memset8(volatile void *dst, U8 src, size_t nbytes, Bool erase); + +/*! \brief Copies \a nbytes bytes to the flash destination pointed to by \a dst + * from the repeated \a src big-endian source half-word. + * + * The destination areas that are not within the flash array or the User page + * are ignored. + * + * All pointer and size alignments are supported. + * + * \param dst Pointer to flash destination. + * \param src Source half-word. + * \param nbytes Number of bytes to set. + * \param erase Whether to erase before writing: \c TRUE or \c FALSE. + * + * \return The value of \a dst. + * + * \warning A Lock Error is issued if the command is applied to pages belonging + * to a locked region or to the bootloader protected area. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern volatile void *flashc_memset16(volatile void *dst, U16 src, size_t nbytes, Bool erase); + +/*! \brief Copies \a nbytes bytes to the flash destination pointed to by \a dst + * from the repeated \a src big-endian source word. + * + * The destination areas that are not within the flash array or the User page + * are ignored. + * + * All pointer and size alignments are supported. + * + * \param dst Pointer to flash destination. + * \param src Source word. + * \param nbytes Number of bytes to set. + * \param erase Whether to erase before writing: \c TRUE or \c FALSE. + * + * \return The value of \a dst. + * + * \warning A Lock Error is issued if the command is applied to pages belonging + * to a locked region or to the bootloader protected area. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern volatile void *flashc_memset32(volatile void *dst, U32 src, size_t nbytes, Bool erase); + +/*! \brief Copies \a nbytes bytes to the flash destination pointed to by \a dst + * from the repeated \a src big-endian source double-word. + * + * The destination areas that are not within the flash array or the User page + * are ignored. + * + * All pointer and size alignments are supported. + * + * \param dst Pointer to flash destination. + * \param src Source double-word. + * \param nbytes Number of bytes to set. + * \param erase Whether to erase before writing: \c TRUE or \c FALSE. + * + * \return The value of \a dst. + * + * \warning A Lock Error is issued if the command is applied to pages belonging + * to a locked region or to the bootloader protected area. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern volatile void *flashc_memset64(volatile void *dst, U64 src, size_t nbytes, Bool erase); + +/*! \brief Copies \a nbytes bytes to the flash destination pointed to by \a dst + * from the repeated \a src big-endian source pattern. + * + * The destination areas that are not within the flash array or the User page + * are ignored. + * + * All pointer and size alignments are supported. + * + * \param dst Pointer to flash destination. + * \param src Source double-word. + * \param src_width \a src width in bits: 8, 16, 32 or 64. + * \param nbytes Number of bytes to set. + * \param erase Whether to erase before writing: \c TRUE or \c FALSE. + * + * \return The value of \a dst. + * + * \warning A Lock Error is issued if the command is applied to pages belonging + * to a locked region or to the bootloader protected area. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +#define flashc_memset(dst, src, src_width, nbytes, erase) \ + TPASTE2(flashc_memset, src_width)((dst), (src), (nbytes), (erase)) + +/*! \brief Copies \a nbytes bytes to the flash destination pointed to by \a dst + * from the source pointed to by \a src. + * + * The destination areas that are not within the flash array or the User page + * are ignored. + * + * All pointer and size alignments are supported. + * + * \param dst Pointer to flash destination. + * \param src Pointer to source data. + * \param nbytes Number of bytes to copy. + * \param erase Whether to erase before writing: \c TRUE or \c FALSE. + * + * \return The value of \a dst. + * + * \warning If copying takes place between areas that overlap, the behavior is + * undefined. + * + * \warning A Lock Error is issued if the command is applied to pages belonging + * to a locked region or to the bootloader protected area. + * + * \note The FLASHC error status returned by \ref flashc_is_lock_error and + * \ref flashc_is_programming_error is updated. + */ +extern volatile void *flashc_memcpy(volatile void *dst, const void *src, size_t nbytes, Bool erase); + +//! @} + + +#endif // _FLASHC_H_ diff --git a/20080212/Demo/lwIP_AVR32_UC3/DRIVERS/GPIO/gpio.c b/20080212/Demo/lwIP_AVR32_UC3/DRIVERS/GPIO/gpio.c new file mode 100644 index 000000000..9b61a65aa --- /dev/null +++ b/20080212/Demo/lwIP_AVR32_UC3/DRIVERS/GPIO/gpio.c @@ -0,0 +1,260 @@ +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief GPIO driver for AVR32 UC3. + * + * This file defines a useful set of functions for the GPIO. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with a GPIO module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + *****************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include "gpio.h" + + +//! GPIO module instance. +#define GPIO AVR32_GPIO + + +int gpio_enable_module(const gpio_map_t gpiomap, unsigned int size) +{ + int status = GPIO_SUCCESS; + unsigned int i; + + for (i = 0; i < size; i++) + { + status |= gpio_enable_module_pin(gpiomap->pin, gpiomap->function); + gpiomap++; + } + + return status; +} + + +int gpio_enable_module_pin(unsigned int pin, unsigned int function) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + + // Enable the correct function. + switch (function) + { + case 0: // A function. + gpio_port->pmr0c = 1 << (pin & 0x1F); + gpio_port->pmr1c = 1 << (pin & 0x1F); + break; + + case 1: // B function. + gpio_port->pmr0s = 1 << (pin & 0x1F); + gpio_port->pmr1c = 1 << (pin & 0x1F); + break; + + case 2: // C function. + gpio_port->pmr0c = 1 << (pin & 0x1F); + gpio_port->pmr1s = 1 << (pin & 0x1F); + break; + + default: + return GPIO_INVALID_ARGUMENT; + } + + // Disable GPIO control. + gpio_port->gperc = 1 << (pin & 0x1F); + + return GPIO_SUCCESS; +} + + +void gpio_enable_gpio(const gpio_map_t gpiomap, unsigned int size) +{ + unsigned int i; + + for (i = 0; i < size; i++) + { + gpio_enable_gpio_pin(gpiomap->pin); + gpiomap++; + } +} + + +void gpio_enable_gpio_pin(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + gpio_port->oderc = 1 << (pin & 0x1F); + gpio_port->gpers = 1 << (pin & 0x1F); +} + + +void gpio_enable_pin_open_drain(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + gpio_port->odmers = 1 << (pin & 0x1F); +} + + +void gpio_disable_pin_open_drain(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + gpio_port->odmerc = 1 << (pin & 0x1F); +} + + +void gpio_enable_pin_pull_up(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + gpio_port->puers = 1 << (pin & 0x1F); +} + + +void gpio_disable_pin_pull_up(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + gpio_port->puerc = 1 << (pin & 0x1F); +} + + +int gpio_get_pin_value(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + return (gpio_port->pvr >> (pin & 0x1F)) & 1; +} + + +int gpio_get_gpio_pin_output_value(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + return (gpio_port->ovr >> (pin & 0x1F)) & 1; +} + + +void gpio_set_gpio_pin(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + + gpio_port->ovrs = 1 << (pin & 0x1F); // Value to be driven on the I/O line: 1. + gpio_port->oders = 1 << (pin & 0x1F); // The GPIO output driver is enabled for that pin. + gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin. +} + + +void gpio_clr_gpio_pin(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + + gpio_port->ovrc = 1 << (pin & 0x1F); // Value to be driven on the I/O line: 0. + gpio_port->oders = 1 << (pin & 0x1F); // The GPIO output driver is enabled for that pin. + gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin. +} + + +void gpio_tgl_gpio_pin(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + + gpio_port->ovrt = 1 << (pin & 0x1F); // Toggle the I/O line. + gpio_port->oders = 1 << (pin & 0x1F); // The GPIO output driver is enabled for that pin. + gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin. +} + + +void gpio_enable_pin_glitch_filter(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + gpio_port->gfers = 1 << (pin & 0x1F); +} + + +void gpio_disable_pin_glitch_filter(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + gpio_port->gferc = 1 << (pin & 0x1F); +} + + +int gpio_enable_pin_interrupt(unsigned int pin, unsigned int mode) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + + // Enable the glitch filter. + gpio_port->gfers = 1 << (pin & 0x1F); + + // Configure the edge detector. + switch (mode) + { + case GPIO_PIN_CHANGE: + gpio_port->imr0c = 1 << (pin & 0x1F); + gpio_port->imr1c = 1 << (pin & 0x1F); + break; + + case GPIO_RISING_EDGE: + gpio_port->imr0s = 1 << (pin & 0x1F); + gpio_port->imr1c = 1 << (pin & 0x1F); + break; + + case GPIO_FALLING_EDGE: + gpio_port->imr0c = 1 << (pin & 0x1F); + gpio_port->imr1s = 1 << (pin & 0x1F); + break; + + default: + return GPIO_INVALID_ARGUMENT; + } + + // Enable interrupt. + gpio_port->iers = 1 << (pin & 0x1F); + + return GPIO_SUCCESS; +} + + +void gpio_disable_pin_interrupt(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + gpio_port->ierc = 1 << (pin & 0x1F); +} + + +int gpio_get_pin_interrupt_flag(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + return (gpio_port->ifr >> (pin & 0x1F)) & 1; +} + + +void gpio_clear_pin_interrupt_flag(unsigned int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5]; + gpio_port->ifrc = 1 << (pin & 0x1F); +} diff --git a/20080212/Demo/lwIP_AVR32_UC3/DRIVERS/GPIO/gpio.h b/20080212/Demo/lwIP_AVR32_UC3/DRIVERS/GPIO/gpio.h new file mode 100644 index 000000000..3e2c6ff07 --- /dev/null +++ b/20080212/Demo/lwIP_AVR32_UC3/DRIVERS/GPIO/gpio.h @@ -0,0 +1,230 @@ +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief GPIO header for AVR32 UC3. + * + * This file contains basic GPIO driver functions. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with a GPIO module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + *****************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef _GPIO_H_ +#define _GPIO_H_ + +#include + + +/*! \name Return Values of the GPIO API + */ +//! @{ +#define GPIO_SUCCESS 0 //!< Function successfully completed. +#define GPIO_INVALID_ARGUMENT 1 //!< Input parameters are out of range. +//! @} + + +/*! \name Interrupt Trigger Modes + */ +//! @{ +#define GPIO_PIN_CHANGE 0 //!< Interrupt triggered upon pin change. +#define GPIO_RISING_EDGE 1 //!< Interrupt triggered upon rising edge. +#define GPIO_FALLING_EDGE 2 //!< Interrupt triggered upon falling edge. +//! @} + + +//! A type definition of pins and modules connectivity. +typedef struct +{ + unsigned char pin; //!< Module pin. + unsigned char function; //!< Module function. +} gpio_map_t[]; + + +/*! \brief Enables specific module modes for a set of pins. + * + * \param gpiomap The pin map. + * \param size The number of pins in \a gpiomap. + * + * \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT. + */ +extern int gpio_enable_module(const gpio_map_t gpiomap, unsigned int size); + +/*! \brief Enables a specific module mode for a pin. + * + * \param pin The pin number.\n + * Refer to the product header file `uc3x.h' (where x is the part + * number; e.g. x = a0512) for module pins. E.g., to enable a PWM + * channel output, the pin number can be AVR32_PWM_PWM_3_PIN for PWM + * channel 3. + * \param function The pin function.\n + * Refer to the product header file `uc3x.h' (where x is the + * part number; e.g. x = a0512) for module pin functions. E.g., + * to enable a PWM channel output, the pin function can be + * AVR32_PWM_PWM_3_FUNCTION for PWM channel 3. + * + * \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT. + */ +extern int gpio_enable_module_pin(unsigned int pin, unsigned int function); + +/*! \brief Enables the GPIO mode of a set of pins. + * + * \param gpiomap The pin map. + * \param size The number of pins in \a gpiomap. + */ +extern void gpio_enable_gpio(const gpio_map_t gpiomap, unsigned int size); + +/*! \brief Enables the GPIO mode of a pin. + * + * \param pin The pin number.\n + * Refer to the product header file `uc3x.h' (where x is the part + * number; e.g. x = a0512) for pin definitions. E.g., to enable the + * GPIO mode of PX21, AVR32_PIN_PX21 can be used. Module pins such as + * AVR32_PWM_PWM_3_PIN for PWM channel 3 can also be used to release + * module pins for GPIO. + */ +extern void gpio_enable_gpio_pin(unsigned int pin); + +/*! \brief Enables the open-drain mode of a pin. + * + * \param pin The pin number. + */ +extern void gpio_enable_pin_open_drain(unsigned int pin); + +/*! \brief Disables the open-drain mode of a pin. + * + * \param pin The pin number. + */ +extern void gpio_disable_pin_open_drain(unsigned int pin); + +/*! \brief Enables the pull-up resistor of a pin. + * + * \param pin The pin number. + */ +extern void gpio_enable_pin_pull_up(unsigned int pin); + +/*! \brief Disables the pull-up resistor of a pin. + * + * \param pin The pin number. + */ +extern void gpio_disable_pin_pull_up(unsigned int pin); + +/*! \brief Returns the value of a pin. + * + * \param pin The pin number. + * + * \return The pin value. + */ +extern int gpio_get_pin_value(unsigned int pin); + +/*! \brief Returns the output value set for a GPIO pin. + * + * \param pin The pin number. + * + * \return The pin output value. + */ +extern int gpio_get_gpio_pin_output_value(unsigned int pin); + +/*! \brief Drives a GPIO pin to 1. + * + * \param pin The pin number. + */ +extern void gpio_set_gpio_pin(unsigned int pin); + +/*! \brief Drives a GPIO pin to 0. + * + * \param pin The pin number. + */ +extern void gpio_clr_gpio_pin(unsigned int pin); + +/*! \brief Toggles a GPIO pin. + * + * \param pin The pin number. + */ +extern void gpio_tgl_gpio_pin(unsigned int pin); + +/*! \brief Enables the glitch filter of a pin. + * + * When the glitch filter is enabled, a glitch with duration of less than 1 + * clock cycle is automatically rejected, while a pulse with duration of 2 clock + * cycles or more is accepted. For pulse durations between 1 clock cycle and 2 + * clock cycles, the pulse may or may not be taken into account, depending on + * the precise timing of its occurrence. Thus for a pulse to be guaranteed + * visible it must exceed 2 clock cycles, whereas for a glitch to be reliably + * filtered out, its duration must not exceed 1 clock cycle. The filter + * introduces 2 clock cycles latency. + * + * \param pin The pin number. + */ +extern void gpio_enable_pin_glitch_filter(unsigned int pin); + +/*! \brief Disables the glitch filter of a pin. + * + * \param pin The pin number. + */ +extern void gpio_disable_pin_glitch_filter(unsigned int pin); + +/*! \brief Enables the interrupt of a pin with the specified settings. + * + * \param pin The pin number. + * \param mode The trigger mode (\ref GPIO_PIN_CHANGE, \ref GPIO_RISING_EDGE or + * \ref GPIO_FALLING_EDGE). + * + * \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT. + */ +extern int gpio_enable_pin_interrupt(unsigned int pin, unsigned int mode); + +/*! \brief Disables the interrupt of a pin. + * + * \param pin The pin number. + */ +extern void gpio_disable_pin_interrupt(unsigned int pin); + +/*! \brief Gets the interrupt flag of a pin. + * + * \param pin The pin number. + * + * \return The pin interrupt flag. + */ +extern int gpio_get_pin_interrupt_flag(unsigned int pin); + +/*! \brief Clears the interrupt flag of a pin. + * + * \param pin The pin number. + */ +extern void gpio_clear_pin_interrupt_flag(unsigned int pin); + + +#endif // _GPIO_H_ diff --git a/20080212/Demo/lwIP_AVR32_UC3/DRIVERS/INTC/intc.c b/20080212/Demo/lwIP_AVR32_UC3/DRIVERS/INTC/intc.c new file mode 100644 index 000000000..8bd9b880e --- /dev/null +++ b/20080212/Demo/lwIP_AVR32_UC3/DRIVERS/INTC/intc.c @@ -0,0 +1,200 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief INTC driver for AVR32 UC3. + * + * AVR32 Interrupt Controller driver module. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with an INTC module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include +#include "compiler.h" +#include "preprocessor.h" +#include "intc.h" + + +//! Values to store in the interrupt priority registers for the various interrupt priority levels. +extern const unsigned int ipr_val[AVR32_INTC_NUM_INT_LEVELS]; + +//! Creates a table of interrupt line handlers per interrupt group in order to optimize RAM space. +//! Each line handler table contains a set of pointers to interrupt handlers. +#if __GNUC__ +#define DECL_INT_LINE_HANDLER_TABLE(GRP, unused) \ +static volatile __int_handler _int_line_handler_table_##GRP[Max(AVR32_INTC_NUM_IRQS_PER_GRP##GRP, 1)]; +#elif __ICCAVR32__ +#define DECL_INT_LINE_HANDLER_TABLE(GRP, unused) \ +static volatile __no_init __int_handler _int_line_handler_table_##GRP[Max(AVR32_INTC_NUM_IRQS_PER_GRP##GRP, 1)]; +#endif +MREPEAT(AVR32_INTC_NUM_INT_GRPS, DECL_INT_LINE_HANDLER_TABLE, ~); +#undef DECL_INT_LINE_HANDLER_TABLE + +//! Table containing for each interrupt group the number of interrupt request +//! lines and a pointer to the table of interrupt line handlers. +static const struct +{ + unsigned int num_irqs; + volatile __int_handler *_int_line_handler_table; +} _int_handler_table[AVR32_INTC_NUM_INT_GRPS] = +{ +#define INSERT_INT_LINE_HANDLER_TABLE(GRP, unused) \ + {AVR32_INTC_NUM_IRQS_PER_GRP##GRP, _int_line_handler_table_##GRP}, + MREPEAT(AVR32_INTC_NUM_INT_GRPS, INSERT_INT_LINE_HANDLER_TABLE, ~) +#undef INSERT_INT_LINE_HANDLER_TABLE +}; + + +/*! \brief Default interrupt handler. + * + * \note Taken and adapted from Newlib. + */ +#if __GNUC__ +__attribute__((__interrupt__)) +#elif __ICCAVR32__ +__interrupt +#endif +static void _unhandled_interrupt(void) +{ + // Catch unregistered interrupts. + while (TRUE); +} + + +/*! \brief Gets the interrupt handler of the current event at the \a int_lev + * interrupt priority level (called from exception.S). + * + * \param int_lev Interrupt priority level to handle. + * + * \return Interrupt handler to execute. + * + * \note Taken and adapted from Newlib. + */ +__int_handler _get_interrupt_handler(unsigned int int_lev) +{ + // ICR3 is mapped first, ICR0 last. + // Code in exception.S puts int_lev in R12 which is used by AVR32-GCC to pass + // a single argument to a function. + unsigned int int_grp = (&AVR32_INTC.icr3)[INT3 - int_lev]; + unsigned int int_req = AVR32_INTC.irr[int_grp]; + + // As an interrupt may disappear while it is being fetched by the CPU + // (spurious interrupt caused by a delayed response from an MCU peripheral to + // an interrupt flag clear or interrupt disable instruction), check if there + // are remaining interrupt lines to process. + // If a spurious interrupt occurs, the status register (SR) contains an + // execution mode and interrupt level masks corresponding to a level 0 + // interrupt, whatever the interrupt priority level causing the spurious + // event. This behavior has been chosen because a spurious interrupt has not + // to be a priority one and because it may not cause any trouble to other + // interrupts. + // However, these spurious interrupts place the hardware in an unstable state + // and could give problems in other/future versions of the CPU, so the + // software has to be written so that they never occur. The only safe way of + // achieving this is to always clear or disable peripheral interrupts with the + // following sequence: + // 1: Mask the interrupt in the CPU by setting GM (or IxM) in SR. + // 2: Perform the bus access to the peripheral register that clears or + // disables the interrupt. + // 3: Wait until the interrupt has actually been cleared or disabled by the + // peripheral. This is usually performed by reading from a register in the + // same peripheral (it DOES NOT have to be the same register that was + // accessed in step 2, but it MUST be in the same peripheral), what takes + // bus system latencies into account, but peripheral internal latencies + // (generally 0 cycle) also have to be considered. + // 4: Unmask the interrupt in the CPU by clearing GM (or IxM) in SR. + // Note that steps 1 and 4 are useless inside interrupt handlers as the + // corresponding interrupt level is automatically masked by IxM (unless IxM is + // explicitly cleared by the software). + // + // Get the right IRQ handler. + // + // If several interrupt lines are active in the group, the interrupt line with + // the highest number is selected. This is to be coherent with the + // prioritization of interrupt groups performed by the hardware interrupt + // controller. + // + // If no handler has been registered for the pending interrupt, + // _unhandled_interrupt will be selected thanks to the initialization of + // _int_line_handler_table_x by INTC_init_interrupts. + // + // exception.S will provide the interrupt handler with a clean interrupt stack + // frame, with nothing more pushed onto the stack. The interrupt handler must + // manage the `rete' instruction, what can be done thanks to pure assembly, + // inline assembly or the `__attribute__((__interrupt__))' C function + // attribute. + return (int_req) ? _int_handler_table[int_grp]._int_line_handler_table[32 - clz(int_req) - 1] : NULL; +} + + +void INTC_init_interrupts(void) +{ + unsigned int int_grp, int_req; + + // For all interrupt groups, + for (int_grp = 0; int_grp < AVR32_INTC_NUM_INT_GRPS; int_grp++) + { + // For all interrupt request lines of each group, + for (int_req = 0; int_req < _int_handler_table[int_grp].num_irqs; int_req++) + { + // Assign _unhandled_interrupt as default interrupt handler. + _int_handler_table[int_grp]._int_line_handler_table[int_req] = &_unhandled_interrupt; + } + + // Set the interrupt group priority register to its default value. + // By default, all interrupt groups are linked to the interrupt priority + // level 0 and to the interrupt vector _int0. + AVR32_INTC.ipr[int_grp] = ipr_val[INT0]; + } +} + + +void INTC_register_interrupt(__int_handler handler, unsigned int irq, unsigned int int_lev) +{ + // Determine the group of the IRQ. + unsigned int int_grp = irq / AVR32_INTC_MAX_NUM_IRQS_PER_GRP; + + // Store in _int_line_handler_table_x the pointer to the interrupt handler, so + // that _get_interrupt_handler can retrieve it when the interrupt is vectored. + _int_handler_table[int_grp]._int_line_handler_table[irq % AVR32_INTC_MAX_NUM_IRQS_PER_GRP] = handler; + + // Program the corresponding IPRX register to set the interrupt priority level + // and the interrupt vector offset that will be fetched by the core interrupt + // system. + // NOTE: The _intx functions are intermediate assembly functions between the + // core interrupt system and the user interrupt handler. + AVR32_INTC.ipr[int_grp] = ipr_val[int_lev & (AVR32_INTC_IPR0_INTLEV_MASK >> AVR32_INTC_IPR0_INTLEV_OFFSET)]; +} diff --git a/20080212/Demo/lwIP_AVR32_UC3/DRIVERS/INTC/intc.h b/20080212/Demo/lwIP_AVR32_UC3/DRIVERS/INTC/intc.h new file mode 100644 index 000000000..93ecef436 --- /dev/null +++ b/20080212/Demo/lwIP_AVR32_UC3/DRIVERS/INTC/intc.h @@ -0,0 +1,104 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief INTC driver for AVR32 UC3. + * + * AVR32 Interrupt Controller driver module. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with an INTC module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef _INTC_H_ +#define _INTC_H_ + +#include "compiler.h" + + +//! Maximal number of interrupt request lines per group. +#define AVR32_INTC_MAX_NUM_IRQS_PER_GRP 32 + +//! Number of interrupt priority levels. +#define AVR32_INTC_NUM_INT_LEVELS (1 << AVR32_INTC_IPR0_INTLEV_SIZE) + +/*! \name Interrupt Priority Levels + */ +//! @{ +#define INT0 0 //!< Lowest interrupt priority level. +#define INT1 1 +#define INT2 2 +#define INT3 3 //!< Highest interrupt priority level. +//! @} + + +#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling. + +//! Pointer to interrupt handler. +#if __GNUC__ +typedef void (*__int_handler)(void); +#elif __ICCAVR32__ +typedef void (__interrupt *__int_handler)(void); +#endif + + +/*! \brief Initializes the hardware interrupt controller driver. + * + * \note Taken and adapted from Newlib. + */ +extern void INTC_init_interrupts(void); + +/*! \brief Registers an interrupt handler. + * + * \param handler Interrupt handler to register. + * \param irq IRQ of the interrupt handler to register. + * \param int_lev Interrupt priority level to assign to the group of this IRQ. + * + * \warning The interrupt handler must manage the `rete' instruction, what can + * be done thanks to pure assembly, inline assembly or the + * `__attribute__((__interrupt__))' C function attribute. + * + * \warning If several interrupt handlers of a same group are registered with + * different priority levels, only the latest priority level set will + * be effective. + * + * \note Taken and adapted from Newlib. + */ +extern void INTC_register_interrupt(__int_handler handler, unsigned int irq, unsigned int int_lev); + +#endif // __AVR32_ABI_COMPILER__ + + +#endif // _INTC_H_ diff --git a/20080212/Demo/lwIP_AVR32_UC3/DRIVERS/MACB/macb.c b/20080212/Demo/lwIP_AVR32_UC3/DRIVERS/MACB/macb.c new file mode 100644 index 000000000..e4043a2fb --- /dev/null +++ b/20080212/Demo/lwIP_AVR32_UC3/DRIVERS/MACB/macb.c @@ -0,0 +1,999 @@ +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief MACB driver for EVK1100 board. + * + * This file defines a useful set of functions for the MACB interface on + * AVR32 devices. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with a MACB module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + *****************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include +#include +#include + + +#ifdef FREERTOS_USED + #include "FreeRTOS.h" + #include "task.h" + #include "semphr.h" +#endif +#include "macb.h" +#include "gpio.h" +#include "conf_eth.h" +#include "intc.h" + + +/* Size of each receive buffer - DO NOT CHANGE. */ +#define RX_BUFFER_SIZE 128 + + +/* The buffer addresses written into the descriptors must be aligned so the +last few bits are zero. These bits have special meaning for the MACB +peripheral and cannot be used as part of the address. */ +#define ADDRESS_MASK ( ( unsigned long ) 0xFFFFFFFC ) + +/* Bit used within the address stored in the descriptor to mark the last +descriptor in the array. */ +#define RX_WRAP_BIT ( ( unsigned long ) 0x02 ) + +/* A short delay is used to wait for a buffer to become available, should +one not be immediately available when trying to transmit a frame. */ +#define BUFFER_WAIT_DELAY ( 2 ) + +#ifndef FREERTOS_USED +#define portENTER_CRITICAL Disable_global_interrupt +#define portEXIT_CRITICAL Enable_global_interrupt +#define portENTER_SWITCHING_ISR() +#define portEXIT_SWITCHING_ISR() +#endif + + +/* Buffer written to by the MACB DMA. Must be aligned as described by the +comment above the ADDRESS_MASK definition. */ +#if __GNUC__ +static volatile char pcRxBuffer[ ETHERNET_CONF_NB_RX_BUFFERS * RX_BUFFER_SIZE ] __attribute__ ((aligned (8))); +#elif __ICCAVR32__ +#pragma data_alignment=8 +static volatile char pcRxBuffer[ ETHERNET_CONF_NB_RX_BUFFERS * RX_BUFFER_SIZE ]; +#endif + + +/* Buffer read by the MACB DMA. Must be aligned as described by the comment +above the ADDRESS_MASK definition. */ +#if __GNUC__ +static volatile char pcTxBuffer[ ETHERNET_CONF_NB_TX_BUFFERS * ETHERNET_CONF_TX_BUFFER_SIZE ] __attribute__ ((aligned (8))); +#elif __ICCAVR32__ +#pragma data_alignment=8 +static volatile char pcTxBuffer[ ETHERNET_CONF_NB_TX_BUFFERS * ETHERNET_CONF_TX_BUFFER_SIZE ]; +#endif + +/* Descriptors used to communicate between the program and the MACB peripheral. +These descriptors hold the locations and state of the Rx and Tx buffers. */ +static volatile AVR32_TxTdDescriptor xTxDescriptors[ ETHERNET_CONF_NB_TX_BUFFERS ]; +static volatile AVR32_RxTdDescriptor xRxDescriptors[ ETHERNET_CONF_NB_RX_BUFFERS ]; + +/* The IP and Ethernet addresses are read from the header files. */ +char cMACAddress[ 6 ] = { ETHERNET_CONF_ETHADDR0,ETHERNET_CONF_ETHADDR1,ETHERNET_CONF_ETHADDR2,ETHERNET_CONF_ETHADDR3,ETHERNET_CONF_ETHADDR4,ETHERNET_CONF_ETHADDR5 }; + +/*-----------------------------------------------------------*/ + +/* See the header file for descriptions of public functions. */ + +/* + * Prototype for the MACB interrupt function - called by the asm wrapper. + */ +#ifdef FREERTOS_USED +#if __GNUC__ +__attribute__((naked)) +#elif __ICCAVR32__ +#pragma shadow_registers = full // Naked. +#endif +#else +#if __GNUC__ +__attribute__((__interrupt__)) +#elif __ICCAVR32__ +__interrupt +#endif +#endif +void vMACB_ISR( void ); +static long prvMACB_ISR_NonNakedBehaviour( void ); + + +#if ETHERNET_CONF_USE_PHY_IT +#ifdef FREERTOS_USED +#if __GNUC__ +__attribute__((naked)) +#elif __ICCAVR32__ +#pragma shadow_registers = full // Naked. +#endif +#else +#if __GNUC__ +__attribute__((__interrupt__)) +#elif __ICCAVR32__ +__interrupt +#endif +#endif +void vPHY_ISR( void ); +static long prvPHY_ISR_NonNakedBehaviour( void ); +#endif + + +/* + * Initialise both the Tx and Rx descriptors used by the MACB. + */ +static void prvSetupDescriptors(volatile avr32_macb_t * macb); + +/* + * Write our MAC address into the MACB. + */ +static void prvSetupMACAddress( volatile avr32_macb_t * macb ); + +/* + * Configure the MACB for interrupts. + */ +static void prvSetupMACBInterrupt( volatile avr32_macb_t * macb ); + +/* + * Some initialisation functions. + */ +static Bool prvProbePHY( volatile avr32_macb_t * macb ); +static unsigned long ulReadMDIO(volatile avr32_macb_t * macb, unsigned short usAddress); +static void vWriteMDIO(volatile avr32_macb_t * macb, unsigned short usAddress, unsigned short usValue); + + +#ifdef FREERTOS_USED +/* The semaphore used by the MACB ISR to wake the MACB task. */ +static xSemaphoreHandle xSemaphore = NULL; +#else +static volatile Bool DataToRead = FALSE; +#endif + +/* Holds the index to the next buffer from which data will be read. */ +volatile unsigned long ulNextRxBuffer = 0; + + +long lMACBSend(volatile avr32_macb_t * macb, char *pcFrom, unsigned long ulLength, long lEndOfFrame ) +{ +static unsigned long uxTxBufferIndex = 0; +char *pcBuffer; +unsigned long ulLastBuffer, ulDataBuffered = 0, ulDataRemainingToSend, ulLengthToSend; + + + /* If the length of data to be transmitted is greater than each individual + transmit buffer then the data will be split into more than one buffer. + Loop until the entire length has been buffered. */ + while( ulDataBuffered < ulLength ) + { + // Is a buffer available ? + while( !( xTxDescriptors[ uxTxBufferIndex ].U_Status.status & AVR32_TRANSMIT_OK ) ) + { + // There is no room to write the Tx data to the Tx buffer. + // Wait a short while, then try again. +#ifdef FREERTOS_USED + vTaskDelay( BUFFER_WAIT_DELAY ); +#else + __asm__ __volatile__ ("nop"); +#endif + } + + portENTER_CRITICAL(); + { + // Get the address of the buffer from the descriptor, + // then copy the data into the buffer. + pcBuffer = ( char * ) xTxDescriptors[ uxTxBufferIndex ].addr; + + // How much can we write to the buffer ? + ulDataRemainingToSend = ulLength - ulDataBuffered; + if( ulDataRemainingToSend <= ETHERNET_CONF_TX_BUFFER_SIZE ) + { + // We can write all the remaining bytes. + ulLengthToSend = ulDataRemainingToSend; + } + else + { + // We can't write more than ETH_TX_BUFFER_SIZE in one go. + ulLengthToSend = ETHERNET_CONF_TX_BUFFER_SIZE; + } + // Copy the data into the buffer. + memcpy( ( void * ) pcBuffer, ( void * ) &( pcFrom[ ulDataBuffered ] ), ulLengthToSend ); + ulDataBuffered += ulLengthToSend; + // Is this the last data for the frame ? + if( lEndOfFrame && ( ulDataBuffered >= ulLength ) ) + { + // No more data remains for this frame so we can start the transmission. + ulLastBuffer = AVR32_LAST_BUFFER; + } + else + { + // More data to come for this frame. + ulLastBuffer = 0; + } + // Fill out the necessary in the descriptor to get the data sent, + // then move to the next descriptor, wrapping if necessary. + if( uxTxBufferIndex >= ( ETHERNET_CONF_NB_TX_BUFFERS - 1 ) ) + { + xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( ulLengthToSend & ( unsigned long ) AVR32_LENGTH_FRAME ) + | ulLastBuffer + | AVR32_TRANSMIT_WRAP; + uxTxBufferIndex = 0; + } + else + { + xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( ulLengthToSend & ( unsigned long ) AVR32_LENGTH_FRAME ) + | ulLastBuffer; + uxTxBufferIndex++; + } + /* If this is the last buffer to be sent for this frame we can + start the transmission. */ + if( ulLastBuffer ) + { + macb->ncr |= AVR32_MACB_TSTART_MASK; + } + } + portEXIT_CRITICAL(); + } + + return PASS; +} + + +unsigned long ulMACBInputLength( void ) +{ +register unsigned long ulIndex , ulLength = 0; +unsigned int uiTemp; + + // Skip any fragments. We are looking for the first buffer that contains + // data and has the SOF (start of frame) bit set. + while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AVR32_OWNERSHIP_BIT ) && !( xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AVR32_SOF ) ) + { + // Ignoring this buffer. Mark it as free again. + uiTemp = xRxDescriptors[ ulNextRxBuffer ].addr; + xRxDescriptors[ ulNextRxBuffer ].addr = uiTemp & ~( AVR32_OWNERSHIP_BIT ); + ulNextRxBuffer++; + if( ulNextRxBuffer >= ETHERNET_CONF_NB_RX_BUFFERS ) + { + ulNextRxBuffer = 0; + } + } + + // We are going to walk through the descriptors that make up this frame, + // but don't want to alter ulNextRxBuffer as this would prevent vMACBRead() + // from finding the data. Therefore use a copy of ulNextRxBuffer instead. + ulIndex = ulNextRxBuffer; + + // Walk through the descriptors until we find the last buffer for this frame. + // The last buffer will give us the length of the entire frame. + while( ( xRxDescriptors[ ulIndex ].addr & AVR32_OWNERSHIP_BIT ) && !ulLength ) + { + ulLength = xRxDescriptors[ ulIndex ].U_Status.status & AVR32_LENGTH_FRAME; + // Increment to the next buffer, wrapping if necessary. + ulIndex++; + if( ulIndex >= ETHERNET_CONF_NB_RX_BUFFERS ) + { + ulIndex = 0; + } + } + return ulLength; +} +/*-----------------------------------------------------------*/ + +void vMACBRead( char *pcTo, unsigned long ulSectionLength, unsigned long ulTotalFrameLength ) +{ +static unsigned long ulSectionBytesReadSoFar = 0, ulBufferPosition = 0, ulFameBytesReadSoFar = 0; +static char *pcSource; +register unsigned long ulBytesRemainingInBuffer, ulRemainingSectionBytes; +unsigned int uiTemp; + + // Read ulSectionLength bytes from the Rx buffers. + // This is not necessarily any correspondence between the length of our Rx buffers, + // and the length of the data we are returning or the length of the data being requested. + // Therefore, between calls we have to remember not only which buffer we are currently + // processing, but our position within that buffer. + // This would be greatly simplified if PBUF_POOL_BUFSIZE could be guaranteed to be greater + // than the size of each Rx buffer, and that memory fragmentation did not occur. + + // This function should only be called after a call to ulMACBInputLength(). + // This will ensure ulNextRxBuffer is set to the correct buffer. */ + + // vMACBRead is called with pcTo set to NULL to indicate that we are about + // to read a new frame. Any fragments remaining in the frame we were + // processing during the last call should be dropped. + if( pcTo == NULL ) + { + // How many bytes are indicated as being in this buffer? + // If none then the buffer is completely full and the frame is contained within more + // than one buffer. + // Reset our state variables ready for the next read from this buffer. + pcSource = ( char * )( xRxDescriptors[ ulNextRxBuffer ].addr & ADDRESS_MASK ); + ulFameBytesReadSoFar = ( unsigned long ) 0; + ulBufferPosition = ( unsigned long ) 0; + } + else + { + // Loop until we have obtained the required amount of data. + ulSectionBytesReadSoFar = 0; + while( ulSectionBytesReadSoFar < ulSectionLength ) + { + // We may have already read some data from this buffer. + // How much data remains in the buffer? + ulBytesRemainingInBuffer = ( RX_BUFFER_SIZE - ulBufferPosition ); + + // How many more bytes do we need to read before we have the + // required amount of data? + ulRemainingSectionBytes = ulSectionLength - ulSectionBytesReadSoFar; + + // Do we want more data than remains in the buffer? + if( ulRemainingSectionBytes > ulBytesRemainingInBuffer ) + { + // We want more data than remains in the buffer so we can + // write the remains of the buffer to the destination, then move + // onto the next buffer to get the rest. + memcpy( &( pcTo[ ulSectionBytesReadSoFar ] ), &( pcSource[ ulBufferPosition ] ), ulBytesRemainingInBuffer ); + ulSectionBytesReadSoFar += ulBytesRemainingInBuffer; + ulFameBytesReadSoFar += ulBytesRemainingInBuffer; + + // Mark the buffer as free again. + uiTemp = xRxDescriptors[ ulNextRxBuffer ].addr; + xRxDescriptors[ ulNextRxBuffer ].addr = uiTemp & ~( AVR32_OWNERSHIP_BIT ); + // Move onto the next buffer. + ulNextRxBuffer++; + + if( ulNextRxBuffer >= ETHERNET_CONF_NB_RX_BUFFERS ) + { + ulNextRxBuffer = ( unsigned long ) 0; + } + + // Reset the variables for the new buffer. + pcSource = ( char * )( xRxDescriptors[ ulNextRxBuffer ].addr & ADDRESS_MASK ); + ulBufferPosition = ( unsigned long ) 0; + } + else + { + // We have enough data in this buffer to send back. + // Read out enough data and remember how far we read up to. + memcpy( &( pcTo[ ulSectionBytesReadSoFar ] ), &( pcSource[ ulBufferPosition ] ), ulRemainingSectionBytes ); + + // There may be more data in this buffer yet. + // Increment our position in this buffer past the data we have just read. + ulBufferPosition += ulRemainingSectionBytes; + ulSectionBytesReadSoFar += ulRemainingSectionBytes; + ulFameBytesReadSoFar += ulRemainingSectionBytes; + + // Have we now finished with this buffer? + if( ( ulBufferPosition >= RX_BUFFER_SIZE ) || ( ulFameBytesReadSoFar >= ulTotalFrameLength ) ) + { + // Mark the buffer as free again. + uiTemp = xRxDescriptors[ ulNextRxBuffer ].addr; + xRxDescriptors[ ulNextRxBuffer ].addr = uiTemp & ~( AVR32_OWNERSHIP_BIT ); + // Move onto the next buffer. + ulNextRxBuffer++; + + if( ulNextRxBuffer >= ETHERNET_CONF_NB_RX_BUFFERS ) + { + ulNextRxBuffer = 0; + } + + pcSource = ( char * )( xRxDescriptors[ ulNextRxBuffer ].addr & ADDRESS_MASK ); + ulBufferPosition = 0; + } + } + } + } +} +/*-----------------------------------------------------------*/ +void vMACBSetMACAddress(const char * MACAddress) +{ + memcpy(cMACAddress, MACAddress, sizeof(cMACAddress)); +} + +Bool xMACBInit( volatile avr32_macb_t * macb ) +{ +volatile unsigned long status; + + // set up registers + macb->ncr = 0; + macb->tsr = ~0UL; + macb->rsr = ~0UL; + macb->idr = ~0UL; + status = macb->isr; + + +#if ETHERNET_CONF_USE_RMII_INTERFACE + // RMII used, set 0 to the USRIO Register + macb->usrio &= ~AVR32_MACB_RMII_MASK; +#else + // RMII not used, set 1 to the USRIO Register + macb->usrio |= AVR32_MACB_RMII_MASK; +#endif + + // Load our MAC address into the MACB. + prvSetupMACAddress(macb); + + // Setup the buffers and descriptors. + prvSetupDescriptors(macb); + +#if ETHERNET_CONF_SYSTEM_CLOCK <= 20000000 + macb->ncfgr |= (AVR32_MACB_NCFGR_CLK_DIV8 << AVR32_MACB_NCFGR_CLK_OFFSET); +#elif ETHERNET_CONF_SYSTEM_CLOCK <= 40000000 + macb->ncfgr |= (AVR32_MACB_NCFGR_CLK_DIV16 << AVR32_MACB_NCFGR_CLK_OFFSET); +#elif ETHERNET_CONF_SYSTEM_CLOCK <= 80000000 + macb->ncfgr |= AVR32_MACB_NCFGR_CLK_DIV32 << AVR32_MACB_NCFGR_CLK_OFFSET; +#elif ETHERNET_CONF_SYSTEM_CLOCK <= 160000000 + macb->ncfgr |= AVR32_MACB_NCFGR_CLK_DIV64 << AVR32_MACB_NCFGR_CLK_OFFSET; +#else +# error System clock too fast +#endif + + // Are we connected? + if( prvProbePHY(macb) == TRUE ) + { + // Enable the interrupt! + portENTER_CRITICAL(); + { + prvSetupMACBInterrupt(macb); + } + portEXIT_CRITICAL(); + // Enable Rx and Tx, plus the stats register. + macb->ncr = AVR32_MACB_NCR_TE_MASK | AVR32_MACB_NCR_RE_MASK; + return (TRUE); + } + return (FALSE); +} + +void vDisableMACBOperations(volatile avr32_macb_t * macb) +{ +#if ETHERNET_CONF_USE_PHY_IT +volatile avr32_gpio_t *gpio = &AVR32_GPIO; +volatile avr32_gpio_port_t *gpio_port = &gpio->port[MACB_INTERRUPT_PIN/32]; + + gpio_port->ierc = 1 << (MACB_INTERRUPT_PIN%32); +#endif + + // write the MACB control register : disable Tx & Rx + macb->ncr &= ~((1 << AVR32_MACB_RE_OFFSET) | (1 << AVR32_MACB_TE_OFFSET)); + // We no more want to interrupt on Rx and Tx events. + macb->idr = AVR32_MACB_IER_RCOMP_MASK | AVR32_MACB_IER_TCOMP_MASK; +} + + +void vClearMACBTxBuffer( void ) +{ +static unsigned long uxNextBufferToClear = 0; + + // Called on Tx interrupt events to set the AVR32_TRANSMIT_OK bit in each + // Tx buffer within the frame just transmitted. This marks all the buffers + // as available again. + + // The first buffer in the frame should have the bit set automatically. */ + if( xTxDescriptors[ uxNextBufferToClear ].U_Status.status & AVR32_TRANSMIT_OK ) + { + // Loop through the other buffers in the frame. + while( !( xTxDescriptors[ uxNextBufferToClear ].U_Status.status & AVR32_LAST_BUFFER ) ) + { + uxNextBufferToClear++; + + if( uxNextBufferToClear >= ETHERNET_CONF_NB_TX_BUFFERS ) + { + uxNextBufferToClear = 0; + } + + xTxDescriptors[ uxNextBufferToClear ].U_Status.status |= AVR32_TRANSMIT_OK; + } + + // Start with the next buffer the next time a Tx interrupt is called. + uxNextBufferToClear++; + + // Do we need to wrap back to the first buffer? + if( uxNextBufferToClear >= ETHERNET_CONF_NB_TX_BUFFERS ) + { + uxNextBufferToClear = 0; + } + } +} + +static void prvSetupDescriptors(volatile avr32_macb_t * macb) +{ +unsigned long xIndex; +unsigned long ulAddress; + + // Initialise xRxDescriptors descriptor. + for( xIndex = 0; xIndex < ETHERNET_CONF_NB_RX_BUFFERS; ++xIndex ) + { + // Calculate the address of the nth buffer within the array. + ulAddress = ( unsigned long )( pcRxBuffer + ( xIndex * RX_BUFFER_SIZE ) ); + + // Write the buffer address into the descriptor. + // The DMA will place the data at this address when this descriptor is being used. + // Mask off the bottom bits of the address as these have special meaning. + xRxDescriptors[ xIndex ].addr = ulAddress & ADDRESS_MASK; + } + + // The last buffer has the wrap bit set so the MACB knows to wrap back + // to the first buffer. + xRxDescriptors[ ETHERNET_CONF_NB_RX_BUFFERS - 1 ].addr |= RX_WRAP_BIT; + + // Initialise xTxDescriptors. + for( xIndex = 0; xIndex < ETHERNET_CONF_NB_TX_BUFFERS; ++xIndex ) + { + // Calculate the address of the nth buffer within the array. + ulAddress = ( unsigned long )( pcTxBuffer + ( xIndex * ETHERNET_CONF_TX_BUFFER_SIZE ) ); + + // Write the buffer address into the descriptor. + // The DMA will read data from here when the descriptor is being used. + xTxDescriptors[ xIndex ].addr = ulAddress & ADDRESS_MASK; + xTxDescriptors[ xIndex ].U_Status.status = AVR32_TRANSMIT_OK; + } + + // The last buffer has the wrap bit set so the MACB knows to wrap back + // to the first buffer. + xTxDescriptors[ ETHERNET_CONF_NB_TX_BUFFERS - 1 ].U_Status.status = AVR32_TRANSMIT_WRAP | AVR32_TRANSMIT_OK; + + // Tell the MACB where to find the descriptors. + macb->rbqp = ( unsigned long )xRxDescriptors; + macb->tbqp = ( unsigned long )xTxDescriptors; + + // Enable the copy of data into the buffers, ignore broadcasts, + // and don't copy FCS. + macb->ncfgr |= (AVR32_MACB_CAF_MASK | AVR32_MACB_NBC_MASK | AVR32_MACB_NCFGR_DRFCS_MASK); + +} + +static void prvSetupMACAddress( volatile avr32_macb_t * macb ) +{ + // Must be written SA1L then SA1H. + macb->sa1b = ( ( unsigned long ) cMACAddress[ 3 ] << 24 ) | + ( ( unsigned long ) cMACAddress[ 2 ] << 16 ) | + ( ( unsigned long ) cMACAddress[ 1 ] << 8 ) | + cMACAddress[ 0 ]; + + macb->sa1t = ( ( unsigned long ) cMACAddress[ 5 ] << 8 ) | + cMACAddress[ 4 ]; +} + +static void prvSetupMACBInterrupt( volatile avr32_macb_t * macb ) +{ +#ifdef FREERTOS_USED + // Create the semaphore used to trigger the MACB task. + if (xSemaphore == NULL) + { + vSemaphoreCreateBinary( xSemaphore ); + } +#else + // Create the flag used to trigger the MACB polling task. + DataToRead = FALSE; +#endif + + +#ifdef FREERTOS_USED + if( xSemaphore != NULL) + { + // We start by 'taking' the semaphore so the ISR can 'give' it when the + // first interrupt occurs. + xSemaphoreTake( xSemaphore, 0 ); +#endif + // Setup the interrupt for MACB. + // Register the interrupt handler to the interrupt controller at interrupt level 2 + INTC_register_interrupt((__int_handler)&vMACB_ISR, AVR32_MACB_IRQ, INT2); + +#if ETHERNET_CONF_USE_PHY_IT + /* GPIO enable interrupt upon rising edge */ + gpio_enable_pin_interrupt(MACB_INTERRUPT_PIN, GPIO_FALLING_EDGE); + // Setup the interrupt for PHY. + // Register the interrupt handler to the interrupt controller at interrupt level 2 + INTC_register_interrupt((__int_handler)&vPHY_ISR, (AVR32_GPIO_IRQ_0 + (MACB_INTERRUPT_PIN/8)), INT2); + /* enable interrupts on INT pin */ + vWriteMDIO( macb, PHY_MICR , ( MICR_INTEN | MICR_INTOE )); + /* enable "link change" interrupt for Phy */ + vWriteMDIO( macb, PHY_MISR , MISR_LINK_INT_EN ); +#endif + + // We want to interrupt on Rx and Tx events + macb->ier = AVR32_MACB_IER_RCOMP_MASK | AVR32_MACB_IER_TCOMP_MASK; +#ifdef FREERTOS_USED + } +#endif +} + +/*! Read a register on MDIO bus (access to the PHY) + * This function is looping until PHY gets ready + * + * \param macb Input. instance of the MACB to use + * \param usAddress Input. register to set. + * + * \return unsigned long data that has been read + */ +static unsigned long ulReadMDIO(volatile avr32_macb_t * macb, unsigned short usAddress) +{ +unsigned long value, status; + + // initiate transaction : enable management port + macb->ncr |= AVR32_MACB_NCR_MPE_MASK; + // Write the PHY configuration frame to the MAN register + macb->man = (AVR32_MACB_SOF_MASK & (0x01<nsr; + } while (!(status & AVR32_MACB_NSR_IDLE_MASK)); + // read the register value in maintenance register + value = macb->man & 0x0000ffff; + // disable management port + macb->ncr &= ~AVR32_MACB_NCR_MPE_MASK; + // return the read value + return (value); +} + +/*! Write a given value to a register on MDIO bus (access to the PHY) + * This function is looping until PHY gets ready + * + * \param *macb Input. instance of the MACB to use + * \param usAddress Input. register to set. + * \param usValue Input. value to write. + * + */ +static void vWriteMDIO(volatile avr32_macb_t * macb, unsigned short usAddress, unsigned short usValue) +{ +unsigned long status; + + // initiate transaction : enable management port + macb->ncr |= AVR32_MACB_NCR_MPE_MASK; + // Write the PHY configuration frame to the MAN register + macb->man = (( AVR32_MACB_SOF_MASK & (0x01<nsr; + } while (!(status & AVR32_MACB_NSR_IDLE_MASK)); + // disable management port + macb->ncr &= ~AVR32_MACB_NCR_MPE_MASK; +} + +static Bool prvProbePHY( volatile avr32_macb_t * macb ) +{ +volatile unsigned long mii_status, phy_ctrl; +volatile unsigned long config; +unsigned long upper, lower, mode, advertise, lpa; +volatile unsigned long physID; + + // Read Phy Identifier register 1 & 2 + lower = ulReadMDIO(macb, PHY_PHYSID2); + upper = ulReadMDIO(macb, PHY_PHYSID1); + // get Phy ID, ignore Revision + physID = ((upper << 16) & 0xFFFF0000) | (lower & 0xFFF0); + // check if it match config + if (physID == ETHERNET_CONF_PHY_ID) + { + // read RBR + mode = ulReadMDIO(macb, PHY_RBR); + // set RMII mode if not done + if ((mode & RBR_RMII) != RBR_RMII) + { + // force RMII flag if strap options are wrong + mode |= RBR_RMII; + vWriteMDIO(macb, PHY_RBR, mode); + } + + // set advertise register +#if ETHERNET_CONF_AN_ENABLE == 1 + advertise = ADVERTISE_CSMA | ADVERTISE_ALL; +#else + advertise = ADVERTISE_CSMA; + #if ETHERNET_CONF_USE_100MB + #if ETHERNET_CONF_USE_FULL_DUPLEX + advertise |= ADVERTISE_100FULL; + #else + advertise |= ADVERTISE_100HALF; + #endif + #else + #if ETHERNET_CONF_USE_FULL_DUPLEX + advertise |= ADVERTISE_10FULL; + #else + advertise |= ADVERTISE_10HALF; + #endif + #endif +#endif + // write advertise register + vWriteMDIO(macb, PHY_ADVERTISE, advertise); + // read Control register + config = ulReadMDIO(macb, PHY_BMCR); + // read Phy Control register + phy_ctrl = ulReadMDIO(macb, PHY_PHYCR); +#if ETHERNET_CONF_AN_ENABLE + #if ETHERNET_CONF_AUTO_CROSS_ENABLE + // enable Auto MDIX + phy_ctrl |= PHYCR_MDIX_EN; + #else + // disable Auto MDIX + phy_ctrl &= ~PHYCR_MDIX_EN; + #if ETHERNET_CONF_CROSSED_LINK + // force direct link = Use crossed RJ45 cable + phy_ctrl &= ~PHYCR_MDIX_FORCE; + #else + // force crossed link = Use direct RJ45 cable + phy_ctrl |= PHYCR_MDIX_FORCE; + #endif + #endif + // reset auto-negociation capability + config |= (BMCR_ANRESTART | BMCR_ANENABLE); +#else + // disable Auto MDIX + phy_ctrl &= ~PHYCR_MDIX_EN; + #if ETHERNET_CONF_CROSSED_LINK + // force direct link = Use crossed RJ45 cable + phy_ctrl &= ~PHYCR_MDIX_FORCE; + #else + // force crossed link = Use direct RJ45 cable + phy_ctrl |= PHYCR_MDIX_FORCE; + #endif + // clear AN bit + config &= ~BMCR_ANENABLE; + + #if ETHERNET_CONF_USE_100MB + config |= BMCR_SPEED100; + #else + config &= ~BMCR_SPEED100; + #endif + #if ETHERNET_CONF_USE_FULL_DUPLEX + config |= BMCR_FULLDPLX; + #else + config &= ~BMCR_FULLDPLX; + #endif +#endif + // update Phy ctrl register + vWriteMDIO(macb, PHY_PHYCR, phy_ctrl); + + // update ctrl register + vWriteMDIO(macb, PHY_BMCR, config); + + // loop while link status isn't OK + do { + mii_status = ulReadMDIO(macb, PHY_BMSR); + } while (!(mii_status & BMSR_LSTATUS)); + + // read the LPA configuration of the PHY + lpa = ulReadMDIO(macb, PHY_LPA); + + // read the MACB config register + config = AVR32_MACB.ncfgr; + + // if 100MB needed + if ((lpa & advertise) & (LPA_100HALF | LPA_100FULL)) + { + config |= AVR32_MACB_SPD_MASK; + } + else + { + config &= ~(AVR32_MACB_SPD_MASK); + } + + // if FULL DUPLEX needed + if ((lpa & advertise) & (LPA_10FULL | LPA_100FULL)) + { + config |= AVR32_MACB_FD_MASK; + } + else + { + config &= ~(AVR32_MACB_FD_MASK); + } + + // write the MACB config register + macb->ncfgr = config; + + return TRUE; + } + return FALSE; +} + + +void vMACBWaitForInput( unsigned long ulTimeOut ) +{ +#ifdef FREERTOS_USED + // Just wait until we are signled from an ISR that data is available, or + // we simply time out. + xSemaphoreTake( xSemaphore, ulTimeOut ); +#else +unsigned long i; + gpio_clr_gpio_pin(LED0_GPIO); + i = ulTimeOut * 1000; + // wait for an interrupt to occurs + do + { + if ( DataToRead == TRUE ) + { + // IT occurs, reset interrupt flag + portENTER_CRITICAL(); + DataToRead = FALSE; + portEXIT_CRITICAL(); + break; + } + i--; + } + while(i != 0); + gpio_set_gpio_pin(LED0_GPIO); +#endif +} + + +/* + * The MACB ISR. Handles both Tx and Rx complete interrupts. + */ +#ifdef FREERTOS_USED +#if __GNUC__ +__attribute__((naked)) +#elif __ICCAVR32__ +#pragma shadow_registers = full // Naked. +#endif +#else +#if __GNUC__ +__attribute__((__interrupt__)) +#elif __ICCAVR32__ +__interrupt +#endif +#endif +void vMACB_ISR( void ) +{ + // This ISR can cause a context switch, so the first statement must be a + // call to the portENTER_SWITCHING_ISR() macro. This must be BEFORE any + // variable declarations. + portENTER_SWITCHING_ISR(); + + // the return value is used by FreeRTOS to change the context if needed after rete instruction + // in standalone use, this value should be ignored + prvMACB_ISR_NonNakedBehaviour(); + + // Exit the ISR. If a task was woken by either a character being received + // or transmitted then a context switch will occur. + portEXIT_SWITCHING_ISR(); +} +/*-----------------------------------------------------------*/ + +#if __GNUC__ +__attribute__((__noinline__)) +#elif __ICCAVR32__ +#pragma optimize = no_inline +#endif +static long prvMACB_ISR_NonNakedBehaviour( void ) +{ + + // Variable definitions can be made now. + volatile unsigned long ulIntStatus, ulEventStatus; + long xSwitchRequired = FALSE; + + // Find the cause of the interrupt. + ulIntStatus = AVR32_MACB.isr; + ulEventStatus = AVR32_MACB.rsr; + + if( ( ulIntStatus & AVR32_MACB_IDR_RCOMP_MASK ) || ( ulEventStatus & AVR32_MACB_REC_MASK ) ) + { + // A frame has been received, signal the IP task so it can process + // the Rx descriptors. + portENTER_CRITICAL(); +#ifdef FREERTOS_USED + xSwitchRequired = xSemaphoreGiveFromISR( xSemaphore, FALSE ); +#else + DataToRead = TRUE; +#endif + portEXIT_CRITICAL(); + AVR32_MACB.rsr = AVR32_MACB_REC_MASK; + AVR32_MACB.rsr; + } + + if( ulIntStatus & AVR32_MACB_TCOMP_MASK ) + { + // A frame has been transmitted. Mark all the buffers used by the + // frame just transmitted as free again. + vClearMACBTxBuffer(); + AVR32_MACB.tsr = AVR32_MACB_TSR_COMP_MASK; + AVR32_MACB.tsr; + } + + return ( xSwitchRequired ); +} + + + +#if ETHERNET_CONF_USE_PHY_IT +/* + * The PHY ISR. Handles Phy interrupts. + */ +#ifdef FREERTOS_USED +#if __GNUC__ +__attribute__((naked)) +#elif __ICCAVR32__ +#pragma shadow_registers = full // Naked. +#endif +#else +#if __GNUC__ +__attribute__((__interrupt__)) +#elif __ICCAVR32__ +__interrupt +#endif +#endif +void vPHY_ISR( void ) +{ + // This ISR can cause a context switch, so the first statement must be a + // call to the portENTER_SWITCHING_ISR() macro. This must be BEFORE any + // variable declarations. + portENTER_SWITCHING_ISR(); + + // the return value is used by FreeRTOS to change the context if needed after rete instruction + // in standalone use, this value should be ignored + prvPHY_ISR_NonNakedBehaviour(); + + // Exit the ISR. If a task was woken by either a character being received + // or transmitted then a context switch will occur. + portEXIT_SWITCHING_ISR(); +} +/*-----------------------------------------------------------*/ + +#if __GNUC__ +__attribute__((__noinline__)) +#elif __ICCAVR32__ +#pragma optimize = no_inline +#endif +static long prvPHY_ISR_NonNakedBehaviour( void ) +{ + + // Variable definitions can be made now. + volatile unsigned long ulIntStatus, ulEventStatus; + long xSwitchRequired = FALSE; + volatile avr32_gpio_t *gpio = &AVR32_GPIO; + volatile avr32_gpio_port_t *gpio_port = &gpio->port[MACB_INTERRUPT_PIN/32]; + + // read Phy Interrupt register Status + ulIntStatus = ulReadMDIO(&AVR32_MACB, PHY_MISR); + + // read Phy status register + ulEventStatus = ulReadMDIO(&AVR32_MACB, PHY_BMSR); + // dummy read + ulEventStatus = ulReadMDIO(&AVR32_MACB, PHY_BMSR); + + // clear interrupt flag on GPIO + gpio_port->ifrc = 1 << (MACB_INTERRUPT_PIN%32); + + return ( xSwitchRequired ); +} +#endif diff --git a/20080212/Demo/lwIP_AVR32_UC3/DRIVERS/MACB/macb.h b/20080212/Demo/lwIP_AVR32_UC3/DRIVERS/MACB/macb.h new file mode 100644 index 000000000..f29b4c0ba --- /dev/null +++ b/20080212/Demo/lwIP_AVR32_UC3/DRIVERS/MACB/macb.h @@ -0,0 +1,422 @@ +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief MACB example driver for EVK1100 board. + * + * This file defines a useful set of functions for the MACB interface on + * AVR32 devices. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with a MACB module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + *****************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef AVR32_MACB_H +#define AVR32_MACB_H + +#include + +#ifdef FREERTOS_USED +#include +#endif + +#include "conf_eth.h" + +/*! \name Rx Ring descriptor flags + */ +//! @{ +#define AVR32_MACB_RX_USED_OFFSET 0 +#define AVR32_MACB_RX_USED_SIZE 1 +#define AVR32_MACB_RX_WRAP_OFFSET 1 +#define AVR32_MACB_RX_WRAP_SIZE 1 +#define AVR32_MACB_RX_LEN_OFFSET 0 +#define AVR32_MACB_RX_LEN_SIZE 12 +#define AVR32_MACB_RX_OFFSET_OFFSET 12 +#define AVR32_MACB_RX_OFFSET_SIZE 2 +#define AVR32_MACB_RX_SOF_OFFSET 14 +#define AVR32_MACB_RX_SOF_SIZE 1 +#define AVR32_MACB_RX_EOF_OFFSET 15 +#define AVR32_MACB_RX_EOF_SIZE 1 +#define AVR32_MACB_RX_CFI_OFFSET 16 +#define AVR32_MACB_RX_CFI_SIZE 1 +//! @} + +/*! \name Tx Ring descriptor flags + */ +//! @{ +#define AVR32_MACB_TX_LEN_OFFSET 0 +#define AVR32_MACB_TX_LEN_SIZE 11 +#define AVR32_MACB_TX_EOF_OFFSET 15 +#define AVR32_MACB_TX_EOF_SIZE 1 +#define AVR32_MACB_TX_NOCRC_OFFSET 16 +#define AVR32_MACB_TX_NOCRC_SIZE 1 +#define AVR32_MACB_TX_EMF_OFFSET 27 +#define AVR32_MACB_TX_EMF_SIZE 1 +#define AVR32_MACB_TX_UNR_OFFSET 28 +#define AVR32_MACB_TX_UNR_SIZE 1 +#define AVR32_MACB_TX_MAXRETRY_OFFSET 29 +#define AVR32_MACB_TX_MAXRETRY_SIZE 1 +#define AVR32_MACB_TX_WRAP_OFFSET 30 +#define AVR32_MACB_TX_WRAP_SIZE 1 +#define AVR32_MACB_TX_USED_OFFSET 31 +#define AVR32_MACB_TX_USED_SIZE 1 +//! @} + +/*! \name Generic MII registers. + */ +//! @{ +#define PHY_BMCR 0x00 //!< Basic mode control register +#define PHY_BMSR 0x01 //!< Basic mode status register +#define PHY_PHYSID1 0x02 //!< PHYS ID 1 +#define PHY_PHYSID2 0x03 //!< PHYS ID 2 +#define PHY_ADVERTISE 0x04 //!< Advertisement control reg +#define PHY_LPA 0x05 //!< Link partner ability reg +//! @} + +#if BOARD == EVK1100 +/*! \name Extended registers for DP83848 + */ +//! @{ +#define PHY_RBR 0x17 //!< RMII Bypass reg +#define PHY_MICR 0x11 //!< Interrupt Control reg +#define PHY_MISR 0x12 //!< Interrupt Status reg +#define PHY_PHYCR 0x19 //!< Phy CTRL reg +//! @} +#endif + + +/*! \name Basic mode control register. + */ +//! @{ +#define BMCR_RESV 0x007f //!< Unused... +#define BMCR_CTST 0x0080 //!< Collision test +#define BMCR_FULLDPLX 0x0100 //!< Full duplex +#define BMCR_ANRESTART 0x0200 //!< Auto negotiation restart +#define BMCR_ISOLATE 0x0400 //!< Disconnect PHY from MII +#define BMCR_PDOWN 0x0800 //!< Powerdown the PHY +#define BMCR_ANENABLE 0x1000 //!< Enable auto negotiation +#define BMCR_SPEED100 0x2000 //!< Select 100Mbps +#define BMCR_LOOPBACK 0x4000 //!< TXD loopback bits +#define BMCR_RESET 0x8000 //!< Reset the PHY +//! @} + +/*! \name Basic mode status register. + */ +//! @{ +#define BMSR_ERCAP 0x0001 //!< Ext-reg capability +#define BMSR_JCD 0x0002 //!< Jabber detected +#define BMSR_LSTATUS 0x0004 //!< Link status +#define BMSR_ANEGCAPABLE 0x0008 //!< Able to do auto-negotiation +#define BMSR_RFAULT 0x0010 //!< Remote fault detected +#define BMSR_ANEGCOMPLETE 0x0020 //!< Auto-negotiation complete +#define BMSR_RESV 0x00c0 //!< Unused... +#define BMSR_ESTATEN 0x0100 //!< Extended Status in R15 +#define BMSR_100FULL2 0x0200 //!< Can do 100BASE-T2 HDX +#define BMSR_100HALF2 0x0400 //!< Can do 100BASE-T2 FDX +#define BMSR_10HALF 0x0800 //!< Can do 10mbps, half-duplex +#define BMSR_10FULL 0x1000 //!< Can do 10mbps, full-duplex +#define BMSR_100HALF 0x2000 //!< Can do 100mbps, half-duplex +#define BMSR_100FULL 0x4000 //!< Can do 100mbps, full-duplex +#define BMSR_100BASE4 0x8000 //!< Can do 100mbps, 4k packets +//! @} + +/*! \name Advertisement control register. + */ +//! @{ +#define ADVERTISE_SLCT 0x001f //!< Selector bits +#define ADVERTISE_CSMA 0x0001 //!< Only selector supported +#define ADVERTISE_10HALF 0x0020 //!< Try for 10mbps half-duplex +#define ADVERTISE_1000XFULL 0x0020 //!< Try for 1000BASE-X full-duplex +#define ADVERTISE_10FULL 0x0040 //!< Try for 10mbps full-duplex +#define ADVERTISE_1000XHALF 0x0040 //!< Try for 1000BASE-X half-duplex +#define ADVERTISE_100HALF 0x0080 //!< Try for 100mbps half-duplex +#define ADVERTISE_1000XPAUSE 0x0080 //!< Try for 1000BASE-X pause +#define ADVERTISE_100FULL 0x0100 //!< Try for 100mbps full-duplex +#define ADVERTISE_1000XPSE_ASYM 0x0100 //!< Try for 1000BASE-X asym pause +#define ADVERTISE_100BASE4 0x0200 //!< Try for 100mbps 4k packets +#define ADVERTISE_PAUSE_CAP 0x0400 //!< Try for pause +#define ADVERTISE_PAUSE_ASYM 0x0800 //!< Try for asymetric pause +#define ADVERTISE_RESV 0x1000 //!< Unused... +#define ADVERTISE_RFAULT 0x2000 //!< Say we can detect faults +#define ADVERTISE_LPACK 0x4000 //!< Ack link partners response +#define ADVERTISE_NPAGE 0x8000 //!< Next page bit +//! @} + +#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | ADVERTISE_CSMA) +#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ + ADVERTISE_100HALF | ADVERTISE_100FULL) + +/*! \name Link partner ability register. + */ +//! @{ +#define LPA_SLCT 0x001f //!< Same as advertise selector +#define LPA_10HALF 0x0020 //!< Can do 10mbps half-duplex +#define LPA_1000XFULL 0x0020 //!< Can do 1000BASE-X full-duplex +#define LPA_10FULL 0x0040 //!< Can do 10mbps full-duplex +#define LPA_1000XHALF 0x0040 //!< Can do 1000BASE-X half-duplex +#define LPA_100HALF 0x0080 //!< Can do 100mbps half-duplex +#define LPA_1000XPAUSE 0x0080 //!< Can do 1000BASE-X pause +#define LPA_100FULL 0x0100 //!< Can do 100mbps full-duplex +#define LPA_1000XPAUSE_ASYM 0x0100 //!< Can do 1000BASE-X pause asym +#define LPA_100BASE4 0x0200 //!< Can do 100mbps 4k packets +#define LPA_PAUSE_CAP 0x0400 //!< Can pause +#define LPA_PAUSE_ASYM 0x0800 //!< Can pause asymetrically +#define LPA_RESV 0x1000 //!< Unused... +#define LPA_RFAULT 0x2000 //!< Link partner faulted +#define LPA_LPACK 0x4000 //!< Link partner acked us +#define LPA_NPAGE 0x8000 //!< Next page bit + +#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) +#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) +//! @} + +#if BOARD == EVK1100 +/*! RMII Bypass Register */ +#define RBR_RMII 0x0020 //!< RMII Mode +/*! \name Interrupt Ctrl Register. + */ +//! @{ +#define MICR_INTEN 0x0002 //!< Enable interrupts +#define MICR_INTOE 0x0001 //!< Enable INT output +//! @} + +/*! \name Interrupt Status Register. + */ +//! @{ +#define MISR_ED_INT_EN 0x0040 //!< Energy Detect enabled +#define MISR_LINK_INT_EN 0x0020 //!< Link status change enabled +#define MISR_SPD_INT_EN 0x0010 //!< Speed change enabled +#define MISR_DP_INT_EN 0x0008 //!< Duplex mode change enabled +#define MISR_ANC_INT_EN 0x0004 //!< Auto-Neg complete enabled +#define MISR_FHF_INT_EN 0x0002 //!< False Carrier enabled +#define MISR_RHF_INT_EN 0x0001 //!< Receive Error enabled +#define MISR_ED_INT 0x4000 //!< Energy Detect +#define MISR_LINK_INT 0x2000 //!< Link status change +#define MISR_SPD_INT 0x1000 //!< Speed change +#define MISR_DP_INT 0x0800 //!< Duplex mode change +#define MISR_ANC_INT 0x0400 //!< Auto-Neg complete +#define MISR_FHF_INT 0x0200 //!< False Carrier +#define MISR_RHF_INT 0x0100 //!< Receive Error +//! @} + +/*! \name Phy Ctrl Register. + */ +//! @{ +#define PHYCR_MDIX_EN 0x8000 //!< Enable Auto MDIX +#define PHYCR_MDIX_FORCE 0x4000 //!< Force MDIX crossed +//! @} +#endif + +/*! Packet structure. + */ +//! @{ +typedef struct +{ + char *data; + unsigned int len; +} macb_packet_t; +//! @} + +/*! Receive Transfer descriptor structure. + */ +//! @{ +typedef struct _AVR32_RxTdDescriptor { + unsigned int addr; + union + { + unsigned int status; + struct { + unsigned int BroadCast:1; + unsigned int MultiCast:1; + unsigned int UniCast:1; + unsigned int ExternalAdd:1; + unsigned int Res1:1; + unsigned int Sa1Match:1; + unsigned int Sa2Match:1; + unsigned int Sa3Match:1; + unsigned int Sa4Match:1; + unsigned int TypeID:1; + unsigned int VlanTag:1; + unsigned int PriorityTag:1; + unsigned int VlanPriority:3; + unsigned int Cfi:1; + unsigned int EndOfFrame:1; + unsigned int StartOfFrame:1; + unsigned int Rxbuf_off:2; + unsigned int Res0:1; + unsigned int Length:11; + }S_Status; + }U_Status; +}AVR32_RxTdDescriptor, *AVR32P_RxTdDescriptor; +//! @} + +/*! Transmit Transfer descriptor structure. + */ +//! @{ +typedef struct _AVR32_TxTdDescriptor { + unsigned int addr; + union + { + unsigned int status; + struct { + unsigned int BuffUsed:1; + unsigned int Wrap:1; + unsigned int TransmitError:1; + unsigned int TransmitUnderrun:1; + unsigned int BufExhausted:1; + unsigned int Res1:10; + unsigned int NoCrc:1; + unsigned int LastBuff:1; + unsigned int Res0:4; + unsigned int Length:11; + }S_Status; + }U_Status; +}AVR32_TxTdDescriptor, *AVR32P_TxTdDescriptor; +//! @} + +/*! Mask for frame used. */ +#define AVR32_OWNERSHIP_BIT 0x00000001 + +/*! Receive status defintion. + */ +//! @{ +#define AVR32_BROADCAST_ADDR ((unsigned int) (1 << 31)) //* Broadcat address detected +#define AVR32_MULTICAST_HASH ((unsigned int) (1 << 30)) //* MultiCast hash match +#define AVR32_UNICAST_HASH ((unsigned int) (1 << 29)) //* UniCast hash match +#define AVR32_EXTERNAL_ADDR ((unsigned int) (1 << 28)) //* External Address match +#define AVR32_SA1_ADDR ((unsigned int) (1 << 26)) //* Specific address 1 match +#define AVR32_SA2_ADDR ((unsigned int) (1 << 25)) //* Specific address 2 match +#define AVR32_SA3_ADDR ((unsigned int) (1 << 24)) //* Specific address 3 match +#define AVR32_SA4_ADDR ((unsigned int) (1 << 23)) //* Specific address 4 match +#define AVR32_TYPE_ID ((unsigned int) (1 << 22)) //* Type ID match +#define AVR32_VLAN_TAG ((unsigned int) (1 << 21)) //* VLAN tag detected +#define AVR32_PRIORITY_TAG ((unsigned int) (1 << 20)) //* PRIORITY tag detected +#define AVR32_VLAN_PRIORITY ((unsigned int) (7 << 17)) //* PRIORITY Mask +#define AVR32_CFI_IND ((unsigned int) (1 << 16)) //* CFI indicator +#define AVR32_EOF ((unsigned int) (1 << 15)) //* EOF +#define AVR32_SOF ((unsigned int) (1 << 14)) //* SOF +#define AVR32_RBF_OFFSET ((unsigned int) (3 << 12)) //* Receive Buffer Offset Mask +#define AVR32_LENGTH_FRAME ((unsigned int) 0x0FFF) //* Length of frame +//! @} + +/* Transmit Status definition */ +//! @{ +#define AVR32_TRANSMIT_OK ((unsigned int) (1 << 31)) //* +#define AVR32_TRANSMIT_WRAP ((unsigned int) (1 << 30)) //* Wrap bit: mark the last descriptor +#define AVR32_TRANSMIT_ERR ((unsigned int) (1 << 29)) //* RLE:transmit error +#define AVR32_TRANSMIT_UND ((unsigned int) (1 << 28)) //* Transmit Underrun +#define AVR32_BUF_EX ((unsigned int) (1 << 27)) //* Buffers exhausted in mid frame +#define AVR32_TRANSMIT_NO_CRC ((unsigned int) (1 << 16)) //* No CRC will be appended to the current frame +#define AVR32_LAST_BUFFER ((unsigned int) (1 << 15)) //* +//! @} + +/** + * \brief Initialise the MACB driver. + * + * \param *macb Base address of the MACB + * + * \return TRUE if success, FALSE otherwise. + */ +Bool xMACBInit( volatile avr32_macb_t * macb ); + +/** + * \brief Send ulLength bytes from pcFrom. This copies the buffer to one of the + * MACB Tx buffers, then indicates to the MACB that the buffer is ready. + * If lEndOfFrame is true then the data being copied is the end of the frame + * and the frame can be transmitted. + * + * \param *macb Base address of the MACB + * \param *pcFrom Address of the data buffer + * \param ulLength Length of the frame + * \param lEndOfFrame Flag for End Of Frame + * + * \return length sent. + */ +long lMACBSend(volatile avr32_macb_t * macb, char *pcFrom, unsigned long ulLength, long lEndOfFrame ); + + +/** + * \brief Frames can be read from the MACB in multiple sections. + * Read ulSectionLength bytes from the MACB receive buffers to pcTo. + * ulTotalFrameLength is the size of the entire frame. Generally vMACBRead + * will be repetedly called until the sum of all the ulSectionLenths totals + * the value of ulTotalFrameLength. + * + * \param *pcTo Address of the buffer + * \param ulSectionLength Length of the buffer + * \param ulTotalFrameLength Length of the frame + */ +void vMACBRead( char *pcTo, unsigned long ulSectionLength, unsigned long ulTotalFrameLength ); + +/** + * \brief Called by the Tx interrupt, this function traverses the buffers used to + * hold the frame that has just completed transmission and marks each as + * free again. + */ +void vClearMACBTxBuffer( void ); + +/** + * \brief Suspend on a semaphore waiting either for the semaphore to be obtained + * or a timeout. The semaphore is used by the MACB ISR to indicate that + * data has been received and is ready for processing. + * + * \param ulTimeOut time to wait for an input + * + */ +void vMACBWaitForInput( unsigned long ulTimeOut ); + +/** + * \brief Function to get length of the next frame in the receive buffers + * + * \return the length of the next frame in the receive buffers. + */ +unsigned long ulMACBInputLength( void ); + +/** + * \brief Set the MACB Physical address (SA1B & SA1T registers). + * + * \param *MACAddress the MAC address to set. + */ +void vMACBSetMACAddress(const char * MACAddress); + +/** + * \brief Disable MACB operations (Tx and Rx). + * + * \param *macb Base address of the MACB + */ +void vDisableMACBOperations(volatile avr32_macb_t * macb); + +#endif + diff --git a/20080212/Demo/lwIP_AVR32_UC3/DRIVERS/PM/pm.c b/20080212/Demo/lwIP_AVR32_UC3/DRIVERS/PM/pm.c new file mode 100644 index 000000000..e2f08d923 --- /dev/null +++ b/20080212/Demo/lwIP_AVR32_UC3/DRIVERS/PM/pm.c @@ -0,0 +1,510 @@ +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Power Manager driver. + * + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + *****************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include "pm.h" + + +/*! \name PM Writable Bit-Field Registers + */ +//! @{ + +typedef union +{ + unsigned long mcctrl; + avr32_pm_mcctrl_t MCCTRL; +} u_avr32_pm_mcctrl_t; + +typedef union +{ + unsigned long cksel; + avr32_pm_cksel_t CKSEL; +} u_avr32_pm_cksel_t; + +typedef union +{ + unsigned long pll; + avr32_pm_pll_t PLL; +} u_avr32_pm_pll_t; + +typedef union +{ + unsigned long oscctrl0; + avr32_pm_oscctrl0_t OSCCTRL0; +} u_avr32_pm_oscctrl0_t; + +typedef union +{ + unsigned long oscctrl1; + avr32_pm_oscctrl1_t OSCCTRL1; +} u_avr32_pm_oscctrl1_t; + +typedef union +{ + unsigned long oscctrl32; + avr32_pm_oscctrl32_t OSCCTRL32; +} u_avr32_pm_oscctrl32_t; + +typedef union +{ + unsigned long ier; + avr32_pm_ier_t IER; +} u_avr32_pm_ier_t; + +typedef union +{ + unsigned long idr; + avr32_pm_idr_t IDR; +} u_avr32_pm_idr_t; + +typedef union +{ + unsigned long icr; + avr32_pm_icr_t ICR; +} u_avr32_pm_icr_t; + +typedef union +{ + unsigned long gcctrl; + avr32_pm_gcctrl_t GCCTRL; +} u_avr32_pm_gcctrl_t; + +typedef union +{ + unsigned long rccr; + avr32_pm_rccr_t RCCR; +} u_avr32_pm_rccr_t; + +typedef union +{ + unsigned long bgcr; + avr32_pm_bgcr_t BGCR; +} u_avr32_pm_bgcr_t; + +typedef union +{ + unsigned long vregcr; + avr32_pm_vregcr_t VREGCR; +} u_avr32_pm_vregcr_t; + +typedef union +{ + unsigned long bod; + avr32_pm_bod_t BOD; +} u_avr32_pm_bod_t; + +//! @} + + +/*! \brief Sets the mode of the oscillator 0. + * + * \param pm Base address of the Power Manager (i.e. &AVR32_PM). + * \param mode Oscillator 0 mode (i.e. AVR32_PM_OSCCTRL0_MODE_x). + */ +static void pm_set_osc0_mode(volatile avr32_pm_t *pm, unsigned int mode) +{ + // Read + u_avr32_pm_oscctrl0_t u_avr32_pm_oscctrl0 = {pm->oscctrl0}; + // Modify + u_avr32_pm_oscctrl0.OSCCTRL0.mode = mode; + // Write + pm->oscctrl0 = u_avr32_pm_oscctrl0.oscctrl0; +} + + +void pm_enable_osc0_ext_clock(volatile avr32_pm_t *pm) +{ + pm_set_osc0_mode(pm, AVR32_PM_OSCCTRL0_MODE_EXT_CLOCK); +} + + +void pm_enable_osc0_crystal(volatile avr32_pm_t *pm, unsigned int fosc0) +{ + pm_set_osc0_mode(pm, (fosc0 < 8000000) ? AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G2 : + AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G3); +} + + +void pm_enable_clk0(volatile avr32_pm_t *pm, unsigned int startup) +{ + pm_enable_clk0_no_wait(pm, startup); + pm_wait_for_clk0_ready(pm); +} + + +void pm_disable_clk0(volatile avr32_pm_t *pm) +{ + pm->mcctrl &= ~AVR32_PM_MCCTRL_OSC0EN_MASK; +} + + +void pm_enable_clk0_no_wait(volatile avr32_pm_t *pm, unsigned int startup) +{ + // Read register + u_avr32_pm_oscctrl0_t u_avr32_pm_oscctrl0 = {pm->oscctrl0}; + // Modify + u_avr32_pm_oscctrl0.OSCCTRL0.startup = startup; + // Write back + pm->oscctrl0 = u_avr32_pm_oscctrl0.oscctrl0; + + pm->mcctrl |= AVR32_PM_MCCTRL_OSC0EN_MASK; +} + + +void pm_wait_for_clk0_ready(volatile avr32_pm_t *pm) +{ + while (!(pm->poscsr & AVR32_PM_POSCSR_OSC0RDY_MASK)); +} + + +/*! \brief Sets the mode of the oscillator 1. + * + * \param pm Base address of the Power Manager (i.e. &AVR32_PM). + * \param mode Oscillator 1 mode (i.e. AVR32_PM_OSCCTRL1_MODE_x). + */ +static void pm_set_osc1_mode(volatile avr32_pm_t *pm, unsigned int mode) +{ + // Read + u_avr32_pm_oscctrl1_t u_avr32_pm_oscctrl1 = {pm->oscctrl1}; + // Modify + u_avr32_pm_oscctrl1.OSCCTRL1.mode = mode; + // Write + pm->oscctrl1 = u_avr32_pm_oscctrl1.oscctrl1; +} + + +void pm_enable_osc1_ext_clock(volatile avr32_pm_t *pm) +{ + pm_set_osc1_mode(pm, AVR32_PM_OSCCTRL1_MODE_EXT_CLOCK); +} + + +void pm_enable_osc1_crystal(volatile avr32_pm_t *pm, unsigned int fosc1) +{ + pm_set_osc1_mode(pm, (fosc1 < 8000000) ? AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G2 : + AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G3); +} + + +void pm_enable_clk1(volatile avr32_pm_t *pm, unsigned int startup) +{ + pm_enable_clk1_no_wait(pm, startup); + pm_wait_for_clk1_ready(pm); +} + + +void pm_disable_clk1(volatile avr32_pm_t *pm) +{ + pm->mcctrl &= ~AVR32_PM_MCCTRL_OSC1EN_MASK; +} + + +void pm_enable_clk1_no_wait(volatile avr32_pm_t *pm, unsigned int startup) +{ + // Read register + u_avr32_pm_oscctrl1_t u_avr32_pm_oscctrl1 = {pm->oscctrl1}; + // Modify + u_avr32_pm_oscctrl1.OSCCTRL1.startup = startup; + // Write back + pm->oscctrl1 = u_avr32_pm_oscctrl1.oscctrl1; + + pm->mcctrl |= AVR32_PM_MCCTRL_OSC1EN_MASK; +} + + +void pm_wait_for_clk1_ready(volatile avr32_pm_t *pm) +{ + while (!(pm->poscsr & AVR32_PM_POSCSR_OSC1RDY_MASK)); +} + + +/*! \brief Sets the mode of the 32-kHz oscillator. + * + * \param pm Base address of the Power Manager (i.e. &AVR32_PM). + * \param mode 32-kHz oscillator mode (i.e. AVR32_PM_OSCCTRL32_MODE_x). + */ +static void pm_set_osc32_mode(volatile avr32_pm_t *pm, unsigned int mode) +{ + // Read + u_avr32_pm_oscctrl32_t u_avr32_pm_oscctrl32 = {pm->oscctrl32}; + // Modify + u_avr32_pm_oscctrl32.OSCCTRL32.mode = mode; + // Write + pm->oscctrl32 = u_avr32_pm_oscctrl32.oscctrl32; +} + + +void pm_enable_osc32_ext_clock(volatile avr32_pm_t *pm) +{ + pm_set_osc32_mode(pm, AVR32_PM_OSCCTRL32_MODE_EXT_CLOCK); +} + + +void pm_enable_osc32_crystal(volatile avr32_pm_t *pm) +{ + pm_set_osc32_mode(pm, AVR32_PM_OSCCTRL32_MODE_CRYSTAL); +} + + +void pm_enable_clk32(volatile avr32_pm_t *pm, unsigned int startup) +{ + pm_enable_clk32_no_wait(pm, startup); + pm_wait_for_clk32_ready(pm); +} + + +void pm_disable_clk32(volatile avr32_pm_t *pm) +{ + pm->oscctrl32 &= ~AVR32_PM_OSCCTRL32_OSC32EN_MASK; +} + + +void pm_enable_clk32_no_wait(volatile avr32_pm_t *pm, unsigned int startup) +{ + // Read register + u_avr32_pm_oscctrl32_t u_avr32_pm_oscctrl32 = {pm->oscctrl32}; + // Modify + u_avr32_pm_oscctrl32.OSCCTRL32.osc32en = 1; + u_avr32_pm_oscctrl32.OSCCTRL32.startup = startup; + // Write back + pm->oscctrl32 = u_avr32_pm_oscctrl32.oscctrl32; +} + + +void pm_wait_for_clk32_ready(volatile avr32_pm_t *pm) +{ + while (!(pm->poscsr & AVR32_PM_POSCSR_OSC32RDY_MASK)); +} + + +void pm_cksel(volatile avr32_pm_t *pm, + unsigned int pbadiv, + unsigned int pbasel, + unsigned int pbbdiv, + unsigned int pbbsel, + unsigned int hsbdiv, + unsigned int hsbsel) +{ + u_avr32_pm_cksel_t u_avr32_pm_cksel = {0}; + + u_avr32_pm_cksel.CKSEL.cpusel = hsbsel; + u_avr32_pm_cksel.CKSEL.cpudiv = hsbdiv; + u_avr32_pm_cksel.CKSEL.hsbsel = hsbsel; + u_avr32_pm_cksel.CKSEL.hsbdiv = hsbdiv; + u_avr32_pm_cksel.CKSEL.pbasel = pbasel; + u_avr32_pm_cksel.CKSEL.pbadiv = pbadiv; + u_avr32_pm_cksel.CKSEL.pbbsel = pbbsel; + u_avr32_pm_cksel.CKSEL.pbbdiv = pbbdiv; + + pm->cksel = u_avr32_pm_cksel.cksel; + + // Wait for ckrdy bit and then clear it + while (!(pm->poscsr & AVR32_PM_POSCSR_CKRDY_MASK)); +} + + +void pm_gc_setup(volatile avr32_pm_t *pm, + unsigned int gc, + unsigned int osc_or_pll, // Use Osc (=0) or PLL (=1) + unsigned int pll_osc, // Sel Osc0/PLL0 or Osc1/PLL1 + unsigned int diven, + unsigned int div) +{ + u_avr32_pm_gcctrl_t u_avr32_pm_gcctrl = {0}; + + u_avr32_pm_gcctrl.GCCTRL.oscsel = pll_osc; + u_avr32_pm_gcctrl.GCCTRL.pllsel = osc_or_pll; + u_avr32_pm_gcctrl.GCCTRL.diven = diven; + u_avr32_pm_gcctrl.GCCTRL.div = div; + + pm->gcctrl[gc] = u_avr32_pm_gcctrl.gcctrl; +} + + +void pm_gc_enable(volatile avr32_pm_t *pm, + unsigned int gc) +{ + pm->gcctrl[gc] |= AVR32_PM_GCCTRL_CEN_MASK; +} + + +void pm_gc_disable(volatile avr32_pm_t *pm, + unsigned int gc) +{ + pm->gcctrl[gc] &= ~AVR32_PM_GCCTRL_CEN_MASK; +} + + +void pm_pll_setup(volatile avr32_pm_t *pm, + unsigned int pll, + unsigned int mul, + unsigned int div, + unsigned int osc, + unsigned int lockcount) +{ + u_avr32_pm_pll_t u_avr32_pm_pll = {0}; + + u_avr32_pm_pll.PLL.pllosc = osc; + u_avr32_pm_pll.PLL.plldiv = div; + u_avr32_pm_pll.PLL.pllmul = mul; + u_avr32_pm_pll.PLL.pllcount = lockcount; + + pm->pll[pll] = u_avr32_pm_pll.pll; +} + + +void pm_pll_set_option(volatile avr32_pm_t *pm, + unsigned int pll, + unsigned int pll_freq, + unsigned int pll_div2, + unsigned int pll_wbwdisable) +{ + u_avr32_pm_pll_t u_avr32_pm_pll = {pm->pll[pll]}; + u_avr32_pm_pll.PLL.pllopt = pll_freq | (pll_div2 << 1) | (pll_wbwdisable << 2); + pm->pll[pll] = u_avr32_pm_pll.pll; +} + + +unsigned int pm_pll_get_option(volatile avr32_pm_t *pm, + unsigned int pll) +{ + return (pm->pll[pll] & AVR32_PM_PLLOPT_MASK) >> AVR32_PM_PLLOPT_OFFSET; +} + + +void pm_pll_enable(volatile avr32_pm_t *pm, + unsigned int pll) +{ + pm->pll[pll] |= AVR32_PM_PLLEN_MASK; +} + + +void pm_pll_disable(volatile avr32_pm_t *pm, + unsigned int pll) +{ + pm->pll[pll] &= ~AVR32_PM_PLLEN_MASK; +} + + +void pm_wait_for_pll0_locked(volatile avr32_pm_t *pm) +{ + while (!(pm->poscsr & AVR32_PM_POSCSR_LOCK0_MASK)); + + // Bypass the lock signal of the PLL + pm->pll[0] |= AVR32_PM_PLL0_PLLBPL_MASK; +} + + +void pm_wait_for_pll1_locked(volatile avr32_pm_t *pm) +{ + while (!(pm->poscsr & AVR32_PM_POSCSR_LOCK1_MASK)); + + // Bypass the lock signal of the PLL + pm->pll[1] |= AVR32_PM_PLL1_PLLBPL_MASK; +} + + +void pm_switch_to_clock(volatile avr32_pm_t *pm, unsigned long clock) +{ + // Read + u_avr32_pm_mcctrl_t u_avr32_pm_mcctrl = {pm->mcctrl}; + // Modify + u_avr32_pm_mcctrl.MCCTRL.mcsel = clock; + // Write back + pm->mcctrl = u_avr32_pm_mcctrl.mcctrl; +} + + +void pm_switch_to_osc0(volatile avr32_pm_t *pm, unsigned int fosc0, unsigned int startup) +{ + pm_enable_osc0_crystal(pm, fosc0); // Enable the Osc0 in crystal mode + pm_enable_clk0(pm, startup); // Crystal startup time - This parameter is critical and depends on the characteristics of the crystal + pm_switch_to_clock(pm, AVR32_PM_MCSEL_OSC0); // Then switch main clock to Osc0 +} + + +void pm_bod_enable_irq(volatile avr32_pm_t *pm) +{ + pm->ier = AVR32_PM_IER_BODDET_MASK; +} + + +void pm_bod_disable_irq(volatile avr32_pm_t *pm) +{ + pm->idr = AVR32_PM_IDR_BODDET_MASK; +} + + +void pm_bod_clear_irq(volatile avr32_pm_t *pm) +{ + pm->icr = AVR32_PM_ICR_BODDET_MASK; +} + + +unsigned long pm_bod_get_irq_status(volatile avr32_pm_t *pm) +{ + return ((pm->isr & AVR32_PM_ISR_BODDET_MASK) != 0); +} + + +unsigned long pm_bod_get_irq_enable_bit(volatile avr32_pm_t *pm) +{ + return ((pm->imr & AVR32_PM_IMR_BODDET_MASK) != 0); +} + + +unsigned long pm_bod_get_level(volatile avr32_pm_t *pm) +{ + return (pm->bod & AVR32_PM_BOD_LEVEL_MASK) >> AVR32_PM_BOD_LEVEL_OFFSET; +} + + +void pm_write_gplp(volatile avr32_pm_t *pm,unsigned long gplp, unsigned long value) +{ + pm->gplp[gplp] = value; +} + + +unsigned long pm_read_gplp(volatile avr32_pm_t *pm,unsigned long gplp) +{ + return pm->gplp[gplp]; +} diff --git a/20080212/Demo/lwIP_AVR32_UC3/DRIVERS/PM/pm.h b/20080212/Demo/lwIP_AVR32_UC3/DRIVERS/PM/pm.h new file mode 100644 index 000000000..12ab46962 --- /dev/null +++ b/20080212/Demo/lwIP_AVR32_UC3/DRIVERS/PM/pm.h @@ -0,0 +1,335 @@ +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Power Manager driver. + * + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + *****************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef _PM_H_ +#define _PM_H_ + +#include +#include "compiler.h" +#include "preprocessor.h" + + +/*! \brief Sets the MCU in the specified sleep mode. + * + * \param mode Sleep mode: + * \arg \c AVR32_PM_SMODE_IDLE: Idle; + * \arg \c AVR32_PM_SMODE_FROZEN: Frozen; + * \arg \c AVR32_PM_SMODE_STANDBY: Standby; + * \arg \c AVR32_PM_SMODE_STOP: Stop; + * \arg \c AVR32_PM_SMODE_SHUTDOWN: Shutdown (DeepStop); + * \arg \c AVR32_PM_SMODE_STATIC: Static. + */ +#define SLEEP(mode) {__asm__ __volatile__ ("sleep "STRINGZ(mode));} + + +/*! \brief Gets the MCU reset cause. + * + * \param pm Base address of the Power Manager instance (i.e. &AVR32_PM). + * + * \return The MCU reset cause which can be masked with the + * \c AVR32_PM_RCAUSE_x_MASK bit-masks to isolate specific causes. + */ +#if __GNUC__ +__attribute__((__always_inline__)) +#endif +extern __inline__ unsigned int pm_get_reset_cause(volatile avr32_pm_t *pm) +{ + return pm->rcause; +} + + +/*! + * \brief This function will enable the external clock mode of the oscillator 0. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + */ +extern void pm_enable_osc0_ext_clock(volatile avr32_pm_t *pm); + + +/*! + * \brief This function will enable the crystal mode of the oscillator 0. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param fosc0 Oscillator 0 crystal frequency (Hz) + */ +extern void pm_enable_osc0_crystal(volatile avr32_pm_t *pm, unsigned int fosc0); + + +/*! + * \brief This function will enable the oscillator 0 to be used with a startup time. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param startup Clock 0 startup time. Time is expressed in term of RCOsc periods (3-bit value) + */ +extern void pm_enable_clk0(volatile avr32_pm_t *pm, unsigned int startup); + + +/*! + * \brief This function will disable the oscillator 0. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + */ +extern void pm_disable_clk0(volatile avr32_pm_t *pm); + + +/*! + * \brief This function will enable the oscillator 0 to be used with no startup time. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param startup Clock 0 startup time. Time is expressed in term of RCOsc periods (3-bit value) but not checked. + */ +extern void pm_enable_clk0_no_wait(volatile avr32_pm_t *pm, unsigned int startup); + + +/*! + * \brief This function will wait until the Osc0 clock is ready. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + */ +extern void pm_wait_for_clk0_ready(volatile avr32_pm_t *pm); + + +/*! + * \brief This function will enable the external clock mode of the oscillator 1. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + */ +extern void pm_enable_osc1_ext_clock(volatile avr32_pm_t *pm); + + +/*! + * \brief This function will enable the crystal mode of the oscillator 1. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param fosc1 Oscillator 1 crystal frequency (Hz) + */ +extern void pm_enable_osc1_crystal(volatile avr32_pm_t *pm, unsigned int fosc1); + + +/*! + * \brief This function will enable the oscillator 1 to be used with a startup time. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param startup Clock 1 startup time. Time is expressed in term of RCOsc periods (3-bit value) + */ +extern void pm_enable_clk1(volatile avr32_pm_t *pm, unsigned int startup); + + +/*! + * \brief This function will disable the oscillator 1. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + */ +extern void pm_disable_clk1(volatile avr32_pm_t *pm); + + +/*! + * \brief This function will enable the oscillator 1 to be used with no startup time. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param startup Clock 1 startup time. Time is expressed in term of RCOsc periods (3-bit value) but not checked. + */ +extern void pm_enable_clk1_no_wait(volatile avr32_pm_t *pm, unsigned int startup); + + +/*! + * \brief This function will wait until the Osc1 clock is ready. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + */ +extern void pm_wait_for_clk1_ready(volatile avr32_pm_t *pm); + + +/*! + * \brief This function will enable the external clock mode of the 32-kHz oscillator. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + */ +extern void pm_enable_osc32_ext_clock(volatile avr32_pm_t *pm); + + +/*! + * \brief This function will enable the crystal mode of the 32-kHz oscillator. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + */ +extern void pm_enable_osc32_crystal(volatile avr32_pm_t *pm); + + +/*! + * \brief This function will enable the oscillator 32 to be used with a startup time. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param startup Clock 32 kHz startup time. Time is expressed in term of RCOsc periods (3-bit value) + */ +extern void pm_enable_clk32(volatile avr32_pm_t *pm, unsigned int startup); + + +/*! + * \brief This function will disable the oscillator 32. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + */ +extern void pm_disable_clk32(volatile avr32_pm_t *pm); + + +/*! + * \brief This function will enable the oscillator 32 to be used with no startup time. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param startup Clock 32 kHz startup time. Time is expressed in term of RCOsc periods (3-bit value) but not checked. + */ +extern void pm_enable_clk32_no_wait(volatile avr32_pm_t *pm, unsigned int startup); + + +/*! + * \brief This function will wait until the osc32 clock is ready. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + */ +extern void pm_wait_for_clk32_ready(volatile avr32_pm_t *pm); + + +/*! + * \brief This function will select all the power manager clocks. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param pbadiv Peripheral Bus A clock divisor enable + * \param pbasel Peripheral Bus A select + * \param pbbdiv Peripheral Bus B clock divisor enable + * \param pbbsel Peripheral Bus B select + * \param hsbdiv High Speed Bus clock divisor enable (CPU clock = HSB clock) + * \param hsbsel High Speed Bus select (CPU clock = HSB clock ) + */ +extern void pm_cksel(volatile avr32_pm_t *pm, unsigned int pbadiv, unsigned int pbasel, unsigned int pbbdiv, unsigned int pbbsel, unsigned int hsbdiv, unsigned int hsbsel); + + +/*! + * \brief This function will setup a generic clock. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param gc generic clock number (0 for gc0...) + * \param osc_or_pll Use OSC (=0) or PLL (=1) + * \param pll_osc Select Osc0/PLL0 or Osc1/PLL1 + * \param diven Generic clock divisor enable + * \param div Generic clock divisor + */ +extern void pm_gc_setup(volatile avr32_pm_t *pm, unsigned int gc, unsigned int osc_or_pll, unsigned int pll_osc, unsigned int diven, unsigned int div); + + +/*! + * \brief This function will enable a generic clock. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param gc generic clock number (0 for gc0...) + */ +extern void pm_gc_enable(volatile avr32_pm_t *pm, unsigned int gc); + + +/*! + * \brief This function will disable a generic clock. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param gc generic clock number (0 for gc0...) + */ +extern void pm_gc_disable(volatile avr32_pm_t *pm, unsigned int gc); + + +/*! + * \brief This function will setup a PLL. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param pll PLL number(0 for PLL0, 1 for PLL1) + * \param mul PLL MUL in the PLL formula + * \param div PLL DIV in the PLL formula + * \param osc OSC number (0 for osc0, 1 for osc1) + * \param lockcount PLL lockount + */ +extern void pm_pll_setup(volatile avr32_pm_t *pm, unsigned int pll, unsigned int mul, unsigned int div, unsigned int osc, unsigned int lockcount); + + +/*! + * \brief This function will set a PLL option. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param pll PLL number(0 for PLL0, 1 for PLL1) + * \param pll_freq Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz. + * \param pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value) + * \param pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode. + */ +extern void pm_pll_set_option(volatile avr32_pm_t *pm, unsigned int pll, unsigned int pll_freq, unsigned int pll_div2, unsigned int pll_wbwdisable); + + +/*! + * \brief This function will get a PLL option. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param pll PLL number(0 for PLL0, 1 for PLL1) + * \return Option + */ +extern unsigned int pm_pll_get_option(volatile avr32_pm_t *pm, unsigned int pll); + + +/*! + * \brief This function will enable a PLL. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param pll PLL number(0 for PLL0, 1 for PLL1) + */ +extern void pm_pll_enable(volatile avr32_pm_t *pm, unsigned int pll); + + +/*! + * \brief This function will disable a PLL. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param pll PLL number(0 for PLL0, 1 for PLL1) + */ +extern void pm_pll_disable(volatile avr32_pm_t *pm, unsigned int pll); + + +/*! + * \brief This function will wait for PLL0 locked + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + */ +extern void pm_wait_for_pll0_locked(volatile avr32_pm_t *pm); + + +/*! + * \brief This function will wait for PLL1 locked + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + */ +extern void pm_wait_for_pll1_locked(volatile avr32_pm_t *pm); + + +/*! + * \brief This function will switch the power manager main clock. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param clock Clock to be switched on. AVR32_PM_MCSEL_SLOW for RCOsc, AVR32_PM_MCSEL_OSC0 for Osc0, AVR32_PM_MCSEL_PLL0 for PLL0. + */ +extern void pm_switch_to_clock(volatile avr32_pm_t *pm, unsigned long clock); + + +/*! + * \brief Switch main clock to clock Osc0 (crystal mode) + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param fosc0 Oscillator 0 crystal frequency (Hz) + * \param startup Crystal 0 startup time. Time is expressed in term of RCOsc periods (3-bit value) + */ +extern void pm_switch_to_osc0(volatile avr32_pm_t *pm, unsigned int fosc0, unsigned int startup); + + +#endif // _PM_H_ diff --git a/20080212/Demo/lwIP_AVR32_UC3/DRIVERS/TC/tc.c b/20080212/Demo/lwIP_AVR32_UC3/DRIVERS/TC/tc.c new file mode 100644 index 000000000..e63cc8f9f --- /dev/null +++ b/20080212/Demo/lwIP_AVR32_UC3/DRIVERS/TC/tc.c @@ -0,0 +1,292 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief TC driver for AVR32 UC3. + * + * AVR32 Timer/Counter driver module. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with a TC module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include +#include "compiler.h" +#include "tc.h" + + +int tc_get_interrupt_settings(volatile avr32_tc_t *tc, unsigned int channel) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + return tc->channel[channel].imr; +} + + +int tc_configure_interrupts(volatile avr32_tc_t *tc, unsigned int channel, const tc_interrupt_t *bitfield) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + // Enable the appropriate interrupts. + tc->channel[channel].ier = bitfield->etrgs << AVR32_TC_ETRGS_OFFSET | + bitfield->ldrbs << AVR32_TC_LDRBS_OFFSET | + bitfield->ldras << AVR32_TC_LDRAS_OFFSET | + bitfield->cpcs << AVR32_TC_CPCS_OFFSET | + bitfield->cpbs << AVR32_TC_CPBS_OFFSET | + bitfield->cpas << AVR32_TC_CPAS_OFFSET | + bitfield->lovrs << AVR32_TC_LOVRS_OFFSET | + bitfield->covfs << AVR32_TC_COVFS_OFFSET; + + // Disable the appropriate interrupts. + tc->channel[channel].idr = (~bitfield->etrgs & 1) << AVR32_TC_ETRGS_OFFSET | + (~bitfield->ldrbs & 1) << AVR32_TC_LDRBS_OFFSET | + (~bitfield->ldras & 1) << AVR32_TC_LDRAS_OFFSET | + (~bitfield->cpcs & 1) << AVR32_TC_CPCS_OFFSET | + (~bitfield->cpbs & 1) << AVR32_TC_CPBS_OFFSET | + (~bitfield->cpas & 1) << AVR32_TC_CPAS_OFFSET | + (~bitfield->lovrs & 1) << AVR32_TC_LOVRS_OFFSET | + (~bitfield->covfs & 1) << AVR32_TC_COVFS_OFFSET; + + return 0; +} + + +int tc_select_external_clock(volatile avr32_tc_t *tc, unsigned int channel, unsigned int ext_clk_sig_src) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS || ext_clk_sig_src >= 1 << AVR32_TC_BMR_TC0XC0S_SIZE) + return TC_INVALID_ARGUMENT; + + // Clear bit-field and set the correct behavior. + tc->bmr = (tc->bmr & ~(AVR32_TC_BMR_TC0XC0S_MASK << (channel * AVR32_TC_BMR_TC0XC0S_SIZE))) | + (ext_clk_sig_src << (channel * AVR32_TC_BMR_TC0XC0S_SIZE)); + + return 0; +} + + +int tc_init_capture(volatile avr32_tc_t *tc, const tc_capture_opt_t *opt) +{ + // Check for valid input. + if (opt->channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + // MEASURE SIGNALS: Capture operating mode. + tc->channel[opt->channel].cmr = opt->ldrb << AVR32_TC_LDRB_OFFSET | + opt->ldra << AVR32_TC_LDRA_OFFSET | + 0 << AVR32_TC_WAVE_OFFSET | + opt->cpctrg << AVR32_TC_CPCTRG_OFFSET | + opt->abetrg << AVR32_TC_ABETRG_OFFSET | + opt->etrgedg << AVR32_TC_ETRGEDG_OFFSET| + opt->ldbdis << AVR32_TC_LDBDIS_OFFSET | + opt->ldbstop << AVR32_TC_LDBSTOP_OFFSET | + opt->burst << AVR32_TC_BURST_OFFSET | + opt->clki << AVR32_TC_CLKI_OFFSET | + opt->tcclks << AVR32_TC_TCCLKS_OFFSET; + + return 0; +} + + +int tc_init_waveform(volatile avr32_tc_t *tc, const tc_waveform_opt_t *opt) +{ + // Check for valid input. + if (opt->channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + // GENERATE SIGNALS: Waveform operating mode. + tc->channel[opt->channel].cmr = opt->bswtrg << AVR32_TC_BSWTRG_OFFSET | + opt->beevt << AVR32_TC_BEEVT_OFFSET | + opt->bcpc << AVR32_TC_BCPC_OFFSET | + opt->bcpb << AVR32_TC_BCPB_OFFSET | + opt->aswtrg << AVR32_TC_ASWTRG_OFFSET | + opt->aeevt << AVR32_TC_AEEVT_OFFSET | + opt->acpc << AVR32_TC_ACPC_OFFSET | + opt->acpa << AVR32_TC_ACPA_OFFSET | + 1 << AVR32_TC_WAVE_OFFSET | + opt->wavsel << AVR32_TC_WAVSEL_OFFSET | + opt->enetrg << AVR32_TC_ENETRG_OFFSET | + opt->eevt << AVR32_TC_EEVT_OFFSET | + opt->eevtedg << AVR32_TC_EEVTEDG_OFFSET | + opt->cpcdis << AVR32_TC_CPCDIS_OFFSET | + opt->cpcstop << AVR32_TC_CPCSTOP_OFFSET | + opt->burst << AVR32_TC_BURST_OFFSET | + opt->clki << AVR32_TC_CLKI_OFFSET | + opt->tcclks << AVR32_TC_TCCLKS_OFFSET; + + return 0; +} + + +int tc_start(volatile avr32_tc_t *tc, unsigned int channel) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + // Enable, reset and start the selected timer/counter channel. + tc->channel[channel].ccr = AVR32_TC_SWTRG_MASK | AVR32_TC_CLKEN_MASK; + + return 0; +} + + +int tc_stop(volatile avr32_tc_t *tc, unsigned int channel) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + // Disable the selected timer/counter channel. + tc->channel[channel].ccr = AVR32_TC_CLKDIS_MASK; + + return 0; +} + + +int tc_software_trigger(volatile avr32_tc_t *tc, unsigned int channel) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + // Reset the selected timer/counter channel. + tc->channel[channel].ccr = AVR32_TC_SWTRG_MASK; + + return 0; +} + + +void tc_sync_trigger(volatile avr32_tc_t *tc) +{ + // Reset all channels of the selected timer/counter. + tc->bcr = AVR32_TC_BCR_SYNC_MASK; +} + + +int tc_read_sr(volatile avr32_tc_t *tc, unsigned int channel) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + return tc->channel[channel].sr; +} + + +int tc_read_tc(volatile avr32_tc_t *tc, unsigned int channel) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + return Rd_bitfield(tc->channel[channel].cv, AVR32_TC_CV_MASK); +} + + +int tc_read_ra(volatile avr32_tc_t *tc, unsigned int channel) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + return Rd_bitfield(tc->channel[channel].ra, AVR32_TC_RA_MASK); +} + + +int tc_read_rb(volatile avr32_tc_t *tc, unsigned int channel) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + return Rd_bitfield(tc->channel[channel].rb, AVR32_TC_RB_MASK); +} + + +int tc_read_rc(volatile avr32_tc_t *tc, unsigned int channel) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + return Rd_bitfield(tc->channel[channel].rc, AVR32_TC_RC_MASK); +} + + +int tc_write_ra(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + // This function is only available in WAVEFORM mode. + if (Tst_bits(tc->channel[channel].cmr, AVR32_TC_WAVE_MASK)) + Wr_bitfield(tc->channel[channel].ra, AVR32_TC_RA_MASK, value); + + return value; +} + + +int tc_write_rb(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + // This function is only available in WAVEFORM mode. + if (Tst_bits(tc->channel[channel].cmr, AVR32_TC_WAVE_MASK)) + Wr_bitfield(tc->channel[channel].rb, AVR32_TC_RB_MASK, value); + + return value; +} + + +int tc_write_rc(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + // This function is only available in WAVEFORM mode. + if (Tst_bits(tc->channel[channel].cmr, AVR32_TC_WAVE_MASK)) + Wr_bitfield(tc->channel[channel].rc, AVR32_TC_RC_MASK, value); + + return value; +} diff --git a/20080212/Demo/lwIP_AVR32_UC3/DRIVERS/TC/tc.h b/20080212/Demo/lwIP_AVR32_UC3/DRIVERS/TC/tc.h new file mode 100644 index 000000000..381008bee --- /dev/null +++ b/20080212/Demo/lwIP_AVR32_UC3/DRIVERS/TC/tc.h @@ -0,0 +1,580 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Timer/Counter driver for AVR32 UC3. + * + * AVR32 Timer/Counter driver module. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with a TC module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef _TC_H_ +#define _TC_H_ + +#include + + +//! TC driver functions return value in case of invalid argument(s). +#define TC_INVALID_ARGUMENT (-1) + +//! Number of timer/counter channels. +#define TC_NUMBER_OF_CHANNELS (sizeof(((avr32_tc_t *)0)->channel) / sizeof(avr32_tc_channel_t)) + +/*! \name External Clock Signal 0 Selection + */ +//! @{ +#define TC_CH0_EXT_CLK0_SRC_TCLK0 AVR32_TC_TC0XC0S_TCLK0 +#define TC_CH0_EXT_CLK0_SRC_NO_CLK AVR32_TC_TC0XC0S_NO_CLK +#define TC_CH0_EXT_CLK0_SRC_TIOA1 AVR32_TC_TC0XC0S_TIOA1 +#define TC_CH0_EXT_CLK0_SRC_TIOA2 AVR32_TC_TC0XC0S_TIOA2 +//! @} + +/*! \name External Clock Signal 1 Selection + */ +//! @{ +#define TC_CH1_EXT_CLK1_SRC_TCLK1 AVR32_TC_TC1XC1S_TCLK1 +#define TC_CH1_EXT_CLK1_SRC_NO_CLK AVR32_TC_TC1XC1S_NO_CLK +#define TC_CH1_EXT_CLK1_SRC_TIOA0 AVR32_TC_TC1XC1S_TIOA0 +#define TC_CH1_EXT_CLK1_SRC_TIOA2 AVR32_TC_TC1XC1S_TIOA2 +//! @} + +/*! \name External Clock Signal 2 Selection + */ +//! @{ +#define TC_CH2_EXT_CLK2_SRC_TCLK2 AVR32_TC_TC2XC2S_TCLK2 +#define TC_CH2_EXT_CLK2_SRC_NO_CLK AVR32_TC_TC2XC2S_NO_CLK +#define TC_CH2_EXT_CLK2_SRC_TIOA0 AVR32_TC_TC2XC2S_TIOA0 +#define TC_CH2_EXT_CLK2_SRC_TIOA1 AVR32_TC_TC2XC2S_TIOA1 +//! @} + +/*! \name Event/Trigger Actions on Output + */ +//! @{ +#define TC_EVT_EFFECT_NOOP AVR32_TC_NONE +#define TC_EVT_EFFECT_SET AVR32_TC_SET +#define TC_EVT_EFFECT_CLEAR AVR32_TC_CLEAR +#define TC_EVT_EFFECT_TOGGLE AVR32_TC_TOGGLE +//! @} + +/*! \name RC Compare Trigger Enable + */ +//! @{ +#define TC_NO_TRIGGER_COMPARE_RC 0 +#define TC_TRIGGER_COMPARE_RC 1 +//! @} + +/*! \name Waveform Selection + */ +//! @{ +#define TC_WAVEFORM_SEL_UP_MODE AVR32_TC_WAVSEL_UP_NO_AUTO +#define TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER AVR32_TC_WAVSEL_UP_AUTO +#define TC_WAVEFORM_SEL_UPDOWN_MODE AVR32_TC_WAVSEL_UPDOWN_NO_AUTO +#define TC_WAVEFORM_SEL_UPDOWN_MODE_RC_TRIGGER AVR32_TC_WAVSEL_UPDOWN_AUTO +//! @} + +/*! \name TIOA or TIOB External Trigger Selection + */ +//! @{ +#define TC_EXT_TRIG_SEL_TIOA 1 +#define TC_EXT_TRIG_SEL_TIOB 0 +//! @} + +/*! \name External Event Selection + */ +//! @{ +#define TC_EXT_EVENT_SEL_TIOB_INPUT AVR32_TC_EEVT_TIOB_INPUT +#define TC_EXT_EVENT_SEL_XC0_OUTPUT AVR32_TC_EEVT_XC0_OUTPUT +#define TC_EXT_EVENT_SEL_XC1_OUTPUT AVR32_TC_EEVT_XC1_OUTPUT +#define TC_EXT_EVENT_SEL_XC2_OUTPUT AVR32_TC_EEVT_XC2_OUTPUT +//! @} + +/*! \name Edge Selection + */ +//! @{ +#define TC_SEL_NO_EDGE AVR32_TC_EEVTEDG_NO_EDGE +#define TC_SEL_RISING_EDGE AVR32_TC_EEVTEDG_POS_EDGE +#define TC_SEL_FALLING_EDGE AVR32_TC_EEVTEDG_NEG_EDGE +#define TC_SEL_EACH_EDGE AVR32_TC_EEVTEDG_BOTH_EDGES +//! @} + +/*! \name Burst Signal Selection + */ +//! @{ +#define TC_BURST_NOT_GATED AVR32_TC_BURST_NOT_GATED +#define TC_BURST_CLK_AND_XC0 AVR32_TC_BURST_CLK_AND_XC0 +#define TC_BURST_CLK_AND_XC1 AVR32_TC_BURST_CLK_AND_XC1 +#define TC_BURST_CLK_AND_XC2 AVR32_TC_BURST_CLK_AND_XC2 +//! @} + +/*! \name Clock Invert + */ +//! @{ +#define TC_CLOCK_RISING_EDGE 0 +#define TC_CLOCK_FALLING_EDGE 1 +//! @} + +/*! \name Clock Selection + */ +//! @{ +#define TC_CLOCK_SOURCE_TC1 AVR32_TC_TCCLKS_TIMER_DIV1_CLOCK +#define TC_CLOCK_SOURCE_TC2 AVR32_TC_TCCLKS_TIMER_DIV2_CLOCK +#define TC_CLOCK_SOURCE_TC3 AVR32_TC_TCCLKS_TIMER_DIV3_CLOCK +#define TC_CLOCK_SOURCE_TC4 AVR32_TC_TCCLKS_TIMER_DIV4_CLOCK +#define TC_CLOCK_SOURCE_TC5 AVR32_TC_TCCLKS_TIMER_DIV5_CLOCK +#define TC_CLOCK_SOURCE_XC0 AVR32_TC_TCCLKS_XC0 +#define TC_CLOCK_SOURCE_XC1 AVR32_TC_TCCLKS_XC1 +#define TC_CLOCK_SOURCE_XC2 AVR32_TC_TCCLKS_XC2 +//! @} + + +//! Timer/counter interrupts. +typedef struct +{ + unsigned int :24; + + //! External trigger interrupt. + unsigned int etrgs : 1; + + //! RB load interrupt. + unsigned int ldrbs : 1; + + //! RA load interrupt. + unsigned int ldras : 1; + + //! RC compare interrupt. + unsigned int cpcs : 1; + + //! RB compare interrupt. + unsigned int cpbs : 1; + + //! RA compare interrupt. + unsigned int cpas : 1; + + //! Load overrun interrupt. + unsigned int lovrs : 1; + + //! Counter overflow interrupt. + unsigned int covfs : 1; +} tc_interrupt_t; + +//! Parameters when initializing a timer/counter in capture mode. +typedef struct +{ + //! Channel to initialize. + unsigned int channel ; + + unsigned int :12; + + //! RB loading selection:\n + //! - \ref TC_SEL_NO_EDGE;\n + //! - \ref TC_SEL_RISING_EDGE;\n + //! - \ref TC_SEL_FALLING_EDGE;\n + //! - \ref TC_SEL_EACH_EDGE. + unsigned int ldrb : 2; + + //! RA loading selection:\n + //! - \ref TC_SEL_NO_EDGE;\n + //! - \ref TC_SEL_RISING_EDGE;\n + //! - \ref TC_SEL_FALLING_EDGE;\n + //! - \ref TC_SEL_EACH_EDGE. + unsigned int ldra : 2; + + unsigned int : 1; + + //! RC compare trigger enable:\n + //! - \ref TC_NO_TRIGGER_COMPARE_RC;\n + //! - \ref TC_TRIGGER_COMPARE_RC. + unsigned int cpctrg : 1; + + unsigned int : 3; + + //! TIOA or TIOB external trigger selection:\n + //! - \ref TC_EXT_TRIG_SEL_TIOA;\n + //! - \ref TC_EXT_TRIG_SEL_TIOB. + unsigned int abetrg : 1; + + //! External trigger edge selection:\n + //! - \ref TC_SEL_NO_EDGE;\n + //! - \ref TC_SEL_RISING_EDGE;\n + //! - \ref TC_SEL_FALLING_EDGE;\n + //! - \ref TC_SEL_EACH_EDGE. + unsigned int etrgedg : 2; + + //! Counter clock disable with RB loading:\n + //! - \c FALSE;\n + //! - \c TRUE. + unsigned int ldbdis : 1; + + //! Counter clock stopped with RB loading:\n + //! - \c FALSE;\n + //! - \c TRUE. + unsigned int ldbstop : 1; + + //! Burst signal selection:\n + //! - \ref TC_BURST_NOT_GATED;\n + //! - \ref TC_BURST_CLK_AND_XC0;\n + //! - \ref TC_BURST_CLK_AND_XC1;\n + //! - \ref TC_BURST_CLK_AND_XC2. + unsigned int burst : 2; + + //! Clock invert:\n + //! - \ref TC_CLOCK_RISING_EDGE;\n + //! - \ref TC_CLOCK_FALLING_EDGE. + unsigned int clki : 1; + + //! Clock selection:\n + //! - \ref TC_CLOCK_SOURCE_TC1;\n + //! - \ref TC_CLOCK_SOURCE_TC2;\n + //! - \ref TC_CLOCK_SOURCE_TC3;\n + //! - \ref TC_CLOCK_SOURCE_TC4;\n + //! - \ref TC_CLOCK_SOURCE_TC5;\n + //! - \ref TC_CLOCK_SOURCE_XC0;\n + //! - \ref TC_CLOCK_SOURCE_XC1;\n + //! - \ref TC_CLOCK_SOURCE_XC2. + unsigned int tcclks : 3; +} tc_capture_opt_t; + +//! Parameters when initializing a timer/counter in waveform mode. +typedef struct +{ + //! Channel to initialize. + unsigned int channel ; + + //! Software trigger effect on TIOB:\n + //! - \ref TC_EVT_EFFECT_NOOP;\n + //! - \ref TC_EVT_EFFECT_SET;\n + //! - \ref TC_EVT_EFFECT_CLEAR;\n + //! - \ref TC_EVT_EFFECT_TOGGLE. + unsigned int bswtrg : 2; + + //! External event effect on TIOB:\n + //! - \ref TC_EVT_EFFECT_NOOP;\n + //! - \ref TC_EVT_EFFECT_SET;\n + //! - \ref TC_EVT_EFFECT_CLEAR;\n + //! - \ref TC_EVT_EFFECT_TOGGLE. + unsigned int beevt : 2; + + //! RC compare effect on TIOB:\n + //! - \ref TC_EVT_EFFECT_NOOP;\n + //! - \ref TC_EVT_EFFECT_SET;\n + //! - \ref TC_EVT_EFFECT_CLEAR;\n + //! - \ref TC_EVT_EFFECT_TOGGLE. + unsigned int bcpc : 2; + + //! RB compare effect on TIOB:\n + //! - \ref TC_EVT_EFFECT_NOOP;\n + //! - \ref TC_EVT_EFFECT_SET;\n + //! - \ref TC_EVT_EFFECT_CLEAR;\n + //! - \ref TC_EVT_EFFECT_TOGGLE. + unsigned int bcpb : 2; + + //! Software trigger effect on TIOA:\n + //! - \ref TC_EVT_EFFECT_NOOP;\n + //! - \ref TC_EVT_EFFECT_SET;\n + //! - \ref TC_EVT_EFFECT_CLEAR;\n + //! - \ref TC_EVT_EFFECT_TOGGLE. + unsigned int aswtrg : 2; + + //! External event effect on TIOA:\n + //! - \ref TC_EVT_EFFECT_NOOP;\n + //! - \ref TC_EVT_EFFECT_SET;\n + //! - \ref TC_EVT_EFFECT_CLEAR;\n + //! - \ref TC_EVT_EFFECT_TOGGLE. + unsigned int aeevt : 2; + + //! RC compare effect on TIOA:\n + //! - \ref TC_EVT_EFFECT_NOOP;\n + //! - \ref TC_EVT_EFFECT_SET;\n + //! - \ref TC_EVT_EFFECT_CLEAR;\n + //! - \ref TC_EVT_EFFECT_TOGGLE. + unsigned int acpc : 2; + + //! RA compare effect on TIOA:\n + //! - \ref TC_EVT_EFFECT_NOOP;\n + //! - \ref TC_EVT_EFFECT_SET;\n + //! - \ref TC_EVT_EFFECT_CLEAR;\n + //! - \ref TC_EVT_EFFECT_TOGGLE. + unsigned int acpa : 2; + + unsigned int : 1; + + //! Waveform selection:\n + //! - \ref TC_WAVEFORM_SEL_UP_MODE;\n + //! - \ref TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER;\n + //! - \ref TC_WAVEFORM_SEL_UPDOWN_MODE;\n + //! - \ref TC_WAVEFORM_SEL_UPDOWN_MODE_RC_TRIGGER. + unsigned int wavsel : 2; + + //! External event trigger enable:\n + //! - \c FALSE;\n + //! - \c TRUE. + unsigned int enetrg : 1; + + //! External event selection:\n + //! - \ref TC_EXT_EVENT_SEL_TIOB_INPUT;\n + //! - \ref TC_EXT_EVENT_SEL_XC0_OUTPUT;\n + //! - \ref TC_EXT_EVENT_SEL_XC1_OUTPUT;\n + //! - \ref TC_EXT_EVENT_SEL_XC2_OUTPUT. + unsigned int eevt : 2; + + //! External event edge selection:\n + //! - \ref TC_SEL_NO_EDGE;\n + //! - \ref TC_SEL_RISING_EDGE;\n + //! - \ref TC_SEL_FALLING_EDGE;\n + //! - \ref TC_SEL_EACH_EDGE. + unsigned int eevtedg : 2; + + //! Counter clock disable with RC compare:\n + //! - \c FALSE;\n + //! - \c TRUE. + unsigned int cpcdis : 1; + + //! Counter clock stopped with RC compare:\n + //! - \c FALSE;\n + //! - \c TRUE. + unsigned int cpcstop : 1; + + //! Burst signal selection:\n + //! - \ref TC_BURST_NOT_GATED;\n + //! - \ref TC_BURST_CLK_AND_XC0;\n + //! - \ref TC_BURST_CLK_AND_XC1;\n + //! - \ref TC_BURST_CLK_AND_XC2. + unsigned int burst : 2; + + //! Clock invert:\n + //! - \ref TC_CLOCK_RISING_EDGE;\n + //! - \ref TC_CLOCK_FALLING_EDGE. + unsigned int clki : 1; + + //! Clock selection:\n + //! - \ref TC_CLOCK_SOURCE_TC1;\n + //! - \ref TC_CLOCK_SOURCE_TC2;\n + //! - \ref TC_CLOCK_SOURCE_TC3;\n + //! - \ref TC_CLOCK_SOURCE_TC4;\n + //! - \ref TC_CLOCK_SOURCE_TC5;\n + //! - \ref TC_CLOCK_SOURCE_XC0;\n + //! - \ref TC_CLOCK_SOURCE_XC1;\n + //! - \ref TC_CLOCK_SOURCE_XC2. + unsigned int tcclks : 3; +} tc_waveform_opt_t; + + +/*! \brief Reads timer/counter interrupt settings. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * + * \retval >=0 The interrupt enable configuration organized according to \ref tc_interrupt_t. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_get_interrupt_settings(volatile avr32_tc_t *tc, unsigned int channel); + +/*! \brief Enables various timer/counter interrupts. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * \param bitfield The interrupt enable configuration. + * + * \retval 0 Success. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_configure_interrupts(volatile avr32_tc_t *tc, unsigned int channel, const tc_interrupt_t *bitfield); + +/*! \brief Selects which external clock to use and how to configure it. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * \param ext_clk_sig_src External clock signal selection: + * \arg \c TC_CH0_EXT_CLK0_SRC_TCLK0; + * \arg \c TC_CH0_EXT_CLK0_SRC_NO_CLK; + * \arg \c TC_CH0_EXT_CLK0_SRC_TIOA1; + * \arg \c TC_CH0_EXT_CLK0_SRC_TIOA2; + * \arg \c TC_CH1_EXT_CLK1_SRC_TCLK1; + * \arg \c TC_CH1_EXT_CLK1_SRC_NO_CLK; + * \arg \c TC_CH1_EXT_CLK1_SRC_TIOA0; + * \arg \c TC_CH1_EXT_CLK1_SRC_TIOA2; + * \arg \c TC_CH2_EXT_CLK2_SRC_TCLK2; + * \arg \c TC_CH2_EXT_CLK2_SRC_NO_CLK; + * \arg \c TC_CH2_EXT_CLK2_SRC_TIOA0; + * \arg \c TC_CH2_EXT_CLK2_SRC_TIOA1. + * + * \retval 0 Success. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_select_external_clock(volatile avr32_tc_t *tc, unsigned int channel, unsigned int ext_clk_sig_src); + +/*! \brief Sets options for timer/counter capture initialization. + * + * \param tc Pointer to the TC instance to access. + * \param opt Options for capture mode. + * + * \retval 0 Success. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_init_capture(volatile avr32_tc_t *tc, const tc_capture_opt_t *opt); + +/*! \brief Sets options for timer/counter waveform initialization. + * + * \param tc Pointer to the TC instance to access. + * \param opt Options for waveform generation. + * + * \retval 0 Success. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_init_waveform(volatile avr32_tc_t *tc, const tc_waveform_opt_t *opt); + +/*! \brief Starts a timer/counter. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * + * \retval 0 Success. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_start(volatile avr32_tc_t *tc, unsigned int channel); + +/*! \brief Stops a timer/counter. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * + * \retval 0 Success. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_stop(volatile avr32_tc_t *tc, unsigned int channel); + +/*! \brief Performs a software trigger: the counter is reset and the clock is started. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * + * \retval 0 Success. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_software_trigger(volatile avr32_tc_t *tc, unsigned int channel); + +/*! \brief Asserts a SYNC signal to generate a software trigger and reset all channels. + * + * \param tc Pointer to the TC instance to access. + */ +extern void tc_sync_trigger(volatile avr32_tc_t *tc); + +/*! \brief Reads the status register. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * + * \retval >=0 Status register value. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_read_sr(volatile avr32_tc_t *tc, unsigned int channel); + +/*! \brief Reads the channel's TC counter and returns the value. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * + * \retval >=0 TC counter value. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_read_tc(volatile avr32_tc_t *tc, unsigned int channel); + +/*! \brief Reads the channel's RA register and returns the value. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * + * \retval >=0 RA register value. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_read_ra(volatile avr32_tc_t *tc, unsigned int channel); + +/*! \brief Reads the channel's RB register and returns the value. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * + * \retval >=0 RB register value. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_read_rb(volatile avr32_tc_t *tc, unsigned int channel); + +/*! \brief Reads the channel's RC register and returns the value. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * + * \retval >=0 RC register value. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_read_rc(volatile avr32_tc_t *tc, unsigned int channel); + +/*! \brief Writes a value to the channel's RA register. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * \param value Value to write to the RA register. + * + * \retval >=0 Written value. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_write_ra(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value); + +/*! \brief Writes a value to the channel's RB register. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * \param value Value to write to the RB register. + * + * \retval >=0 Written value. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_write_rb(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value); + +/*! \brief Writes a value to the channel's RC register. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * \param value Value to write to the RC register. + * + * \retval >=0 Written value. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_write_rc(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value); + + +#endif // _TC_H_ diff --git a/20080212/Demo/lwIP_AVR32_UC3/DRIVERS/USART/usart.c b/20080212/Demo/lwIP_AVR32_UC3/DRIVERS/USART/usart.c new file mode 100644 index 000000000..3110bf5af --- /dev/null +++ b/20080212/Demo/lwIP_AVR32_UC3/DRIVERS/USART/usart.c @@ -0,0 +1,448 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief USART driver for AVR32 UC3. + * + * This file contains basic functions for the AVR32 USART, with support for all + * modes, settings and clock speeds. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with a USART module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include "usart.h" + + +//------------------------------------------------------------------------------ +/*! \name Private Functions + */ +//! @{ + + +/*! \brief Checks if the USART is in multidrop mode. + * + * \param usart Base address of the USART instance. + * + * \return \c 1 if the USART is in multidrop mode, otherwise \c 0. + */ +#if __GNUC__ +__attribute__((__always_inline__)) +#endif +static __inline__ int usart_mode_is_multidrop(volatile avr32_usart_t *usart) +{ + return ((usart->mr >> AVR32_USART_MR_PAR_OFFSET) & AVR32_USART_MR_PAR_MULTI) == AVR32_USART_MR_PAR_MULTI; +} + + +/*! \brief Calculates a clock divider (\e CD) that gets the USART as close to a + * wanted baudrate as possible. + * + * \todo manage the FP fractal part to avoid big errors + * + * Baudrate calculation: + * \f$ baudrate = \frac{Selected Clock}{16 \times CD} \f$ with 16x oversampling or + * \f$ baudrate = \frac{Selected Clock}{8 \times CD} \f$ with 8x oversampling or + * \f$ baudrate = \frac{Selected Clock}{CD} \f$ with SYNC bit set to allow high speed. + * + * \param usart Base address of the USART instance. + * \param baudrate Wanted baudrate. + * \param pba_hz USART module input clock frequency (PBA clock, Hz). + * + * \retval USART_SUCCESS Baudrate successfully initialized. + * \retval USART_INVALID_INPUT Wanted baudrate is impossible with given clock speed. + */ + +static int usart_set_baudrate(volatile avr32_usart_t *usart, unsigned int baudrate, long pba_hz) +{ + // Clock divider. + int cd; + + // Baudrate calculation. + if (baudrate < pba_hz / 16) + { + // Use 16x oversampling, clear SYNC bit. + usart->mr &=~ (AVR32_USART_MR_OVER_MASK | AVR32_USART_MR_SYNC_MASK); + cd = (pba_hz + 8 * baudrate) / (16 * baudrate); + + if ((cd >65535)) return USART_INVALID_INPUT; + } + else if (baudrate < pba_hz / 8) + { + // Use 8x oversampling. + usart->mr |= AVR32_USART_MR_OVER_MASK; + // clear SYNC bit + usart->mr &=~ AVR32_USART_MR_SYNC_MASK; + + cd = (pba_hz + 4 * baudrate) / (8 * baudrate); + + if ((cd < 1)||(cd >65535)) return USART_INVALID_INPUT; + } + else + { + // set SYNC to 1 + usart->mr |= AVR32_USART_MR_SYNC_MASK; + // use PBA/BaudRate + cd = (pba_hz / baudrate); + } + usart->brgr = cd << AVR32_USART_BRGR_CD_OFFSET; + + return USART_SUCCESS; +} + +//! @} + + +//------------------------------------------------------------------------------ +/*! \name Initialization Functions + */ +//! @{ + + +void usart_reset(volatile avr32_usart_t *usart) +{ + // Disable all USART interrupts. + // Interrupts needed should be set explicitly on every reset. + usart->idr = 0xFFFFFFFF; + + // Reset mode and other registers that could cause unpredictable behavior after reset. + usart->mr = 0; + usart->rtor = 0; + usart->ttgr = 0; + + // Shutdown TX and RX (will be re-enabled when setup has successfully completed), + // reset status bits and turn off DTR and RTS. + usart->cr = AVR32_USART_CR_RSTRX_MASK | + AVR32_USART_CR_RSTTX_MASK | + AVR32_USART_CR_RSTSTA_MASK | + AVR32_USART_CR_RSTIT_MASK | + AVR32_USART_CR_RSTNACK_MASK | + AVR32_USART_CR_DTRDIS_MASK | + AVR32_USART_CR_RTSDIS_MASK; +} + + +int usart_init_rs232(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz) +{ + // Reset the USART and shutdown TX and RX. + usart_reset(usart); + + // Check input values. + if (!opt) // Null pointer. + return USART_INVALID_INPUT; + if (opt->charlength < 5 || opt->charlength > 9 || + opt->paritytype > 7 || + opt->stopbits > 2 + 255 || + opt->channelmode > 3) + return USART_INVALID_INPUT; + + if (usart_set_baudrate(usart, opt->baudrate, pba_hz) == USART_INVALID_INPUT) + return USART_INVALID_INPUT; + + if (opt->charlength == 9) + { + // Character length set to 9 bits. MODE9 dominates CHRL. + usart->mr |= AVR32_USART_MR_MODE9_MASK; + } + else + { + // CHRL gives the character length (- 5) when MODE9 = 0. + usart->mr |= (opt->charlength - 5) << AVR32_USART_MR_CHRL_OFFSET; + } + + usart->mr |= (opt->channelmode << AVR32_USART_MR_CHMODE_OFFSET) | + (opt->paritytype << AVR32_USART_MR_PAR_OFFSET); + + if (opt->stopbits > USART_2_STOPBITS) + { + // Set two stop bits + usart->mr |= AVR32_USART_MR_NBSTOP_2 << AVR32_USART_MR_NBSTOP_OFFSET; + // and a timeguard period gives the rest. + usart->ttgr = opt->stopbits - USART_2_STOPBITS; + } + else + // Insert 1, 1.5 or 2 stop bits. + usart->mr |= opt->stopbits << AVR32_USART_MR_NBSTOP_OFFSET; + + // Setup complete; enable communication. + // Enable input and output. + usart->cr |= AVR32_USART_CR_TXEN_MASK | + AVR32_USART_CR_RXEN_MASK; + + return USART_SUCCESS; +} + + +int usart_init_hw_handshaking(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz) +{ + // First: Setup standard RS232. + if (usart_init_rs232(usart, opt, pba_hz) == USART_INVALID_INPUT) + return USART_INVALID_INPUT; + + // Clear previous mode. + usart->mr &= ~AVR32_USART_MR_MODE_MASK; + // Hardware handshaking. + usart->mr |= USART_MODE_HW_HSH << AVR32_USART_MR_MODE_OFFSET; + + return USART_SUCCESS; +} + + +int usart_init_IrDA(volatile avr32_usart_t *usart, const usart_options_t *opt, + long pba_hz, unsigned char irda_filter) +{ + // First: Setup standard RS232. + if (usart_init_rs232(usart, opt, pba_hz) == USART_INVALID_INPUT) + return USART_INVALID_INPUT; + + // Set IrDA counter. + usart->ifr = irda_filter; + + // Activate "low-pass filtering" of input. + usart->mr |= AVR32_USART_MR_FILTER_MASK; + + return USART_SUCCESS; +} + + +int usart_init_modem(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz) +{ + // First: Setup standard RS232. + if (usart_init_rs232(usart, opt, pba_hz) == USART_INVALID_INPUT) + return USART_INVALID_INPUT; + + // Clear previous mode. + usart->mr &= ~AVR32_USART_MR_MODE_MASK; + // Set modem mode. + usart->mr |= USART_MODE_MODEM << AVR32_USART_MR_MODE_OFFSET; + + return USART_SUCCESS; +} + + +int usart_init_rs485(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz) +{ + // First: Setup standard RS232. + if (usart_init_rs232(usart, opt, pba_hz) == USART_INVALID_INPUT) + return USART_INVALID_INPUT; + + // Clear previous mode. + usart->mr &= ~AVR32_USART_MR_MODE_MASK; + // Set RS485 mode. + usart->mr |= USART_MODE_RS485 << AVR32_USART_MR_MODE_OFFSET; + + return USART_SUCCESS; +} + + +int usart_init_iso7816(volatile avr32_usart_t *usart, const iso7816_options_t *opt, int t, long pba_hz) +{ + // Reset the USART and shutdown TX and RX. + usart_reset(usart); + + // Check input values. + if (!opt) // Null pointer. + return USART_INVALID_INPUT; + + if (t == 0) + { + // Set USART mode to ISO7816, T=0. + // The T=0 protocol always uses 2 stop bits. + usart->mr = (USART_MODE_ISO7816_T0 << AVR32_USART_MR_MODE_OFFSET) | + (AVR32_USART_MR_NBSTOP_2 << AVR32_USART_MR_NBSTOP_OFFSET) | + (opt->bit_order << AVR32_USART_MR_MSBF_OFFSET); // Allow MSBF in T=0. + } + else if (t == 1) + { + // Only LSB first in the T=1 protocol. + // max_iterations field is only used in T=0 mode. + if (opt->bit_order != 0 || + opt->max_iterations != 0) + return USART_INVALID_INPUT; + // Set USART mode to ISO7816, T=1. + // The T=1 protocol always uses 1 stop bit. + usart->mr = (USART_MODE_ISO7816_T1 << AVR32_USART_MR_MODE_OFFSET) | + (AVR32_USART_MR_NBSTOP_1 << AVR32_USART_MR_NBSTOP_OFFSET); + } + else + return USART_INVALID_INPUT; + + if (usart_set_baudrate(usart, opt->iso7816_hz, pba_hz) == USART_INVALID_INPUT) + return USART_INVALID_INPUT; + + // Set FIDI register: bit rate = selected clock/FI_DI_ratio/16. + usart->fidi = opt->fidi_ratio; + // Set ISO7816 spesific options in the MODE register. + usart->mr |= (opt->inhibit_nack << AVR32_USART_MR_INACK_OFFSET) | + (opt->dis_suc_nack << AVR32_USART_MR_DSNACK_OFFSET) | + (opt->max_iterations << AVR32_USART_MR_MAX_ITERATION_OFFSET) | + AVR32_USART_MR_CLKO_MASK; // Enable clock output. + + // Setup complete; enable input. + // Leave TX disabled for now. + usart->cr |= AVR32_USART_CR_RXEN_MASK; + + return USART_SUCCESS; +} +//! @} + + +//------------------------------------------------------------------------------ +/*! \name Transmit/Receive Functions + */ +//! @{ + + +int usart_send_address(volatile avr32_usart_t *usart, int address) +{ + // Check if USART is in multidrop / RS485 mode. + if (!usart_mode_is_multidrop(usart)) return USART_MODE_FAULT; + + // Prepare to send an address. + usart->cr |= AVR32_USART_CR_SENDA_MASK; + + // Write the address to TX. + usart_bw_write_char(usart, address); + + return USART_SUCCESS; +} + + +int usart_write_char(volatile avr32_usart_t *usart, int c) +{ + if (usart->csr & AVR32_USART_CSR_TXRDY_MASK) + { + usart->thr = c; + return USART_SUCCESS; + } + else + return USART_TX_BUSY; +} + + +int usart_putchar(volatile avr32_usart_t *usart, int c) +{ + int timeout = USART_DEFAULT_TIMEOUT; + + if (c == '\n') + { + do + { + if (!timeout--) return USART_FAILURE; + } while (usart_write_char(usart, '\r') != USART_SUCCESS); + + timeout = USART_DEFAULT_TIMEOUT; + } + + do + { + if (!timeout--) return USART_FAILURE; + } while (usart_write_char(usart, c) != USART_SUCCESS); + + return USART_SUCCESS; +} + + +int usart_read_char(volatile avr32_usart_t *usart, int *c) +{ + // Check for errors: frame, parity and overrun. In RS485 mode, a parity error + // would mean that an address char has been received. + if (usart->csr & (AVR32_USART_CSR_OVRE_MASK | + AVR32_USART_CSR_FRAME_MASK | + AVR32_USART_CSR_PARE_MASK)) + return USART_RX_ERROR; + + // No error; if we really did receive a char, read it and return SUCCESS. + if (usart->csr & AVR32_USART_CSR_RXRDY_MASK) + { + *c = (unsigned short)usart->rhr; + return USART_SUCCESS; + } + else + return USART_RX_EMPTY; +} + + +int usart_getchar(volatile avr32_usart_t *usart) +{ + int c, ret; + + while ((ret = usart_read_char(usart, &c)) == USART_RX_EMPTY); + + if (ret == USART_RX_ERROR) + return USART_FAILURE; + + return c; +} + + +void usart_write_line(volatile avr32_usart_t *usart, const char *string) +{ + while (*string != '\0') + usart_putchar(usart, *string++); +} + + +int usart_get_echo_line(volatile avr32_usart_t *usart) +{ + int rx_char; + int retval = USART_SUCCESS; + + while (1) + { + rx_char = usart_getchar(usart); + if (rx_char == USART_FAILURE) + { + usart_write_line(usart, "Error!!!\n"); + break; + } + if (rx_char == '\x03') + { + retval = USART_FAILURE; + break; + } + usart_putchar(usart, rx_char); + if (rx_char == '\r') + { + usart_putchar(usart, '\n'); + break; + } + } + + return retval; +} + + +//! @} diff --git a/20080212/Demo/lwIP_AVR32_UC3/DRIVERS/USART/usart.h b/20080212/Demo/lwIP_AVR32_UC3/DRIVERS/USART/usart.h new file mode 100644 index 000000000..1d731f871 --- /dev/null +++ b/20080212/Demo/lwIP_AVR32_UC3/DRIVERS/USART/usart.h @@ -0,0 +1,475 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief USART driver for AVR32 UC3. + * + * This file contains basic functions for the AVR32 USART, with support for all + * modes, settings and clock speeds. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with a USART module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef _USART_H_ +#define _USART_H_ + +#include +#include "compiler.h" + + +/*! \name Return Values + */ +//! @{ +#define USART_SUCCESS 0 //!< Successful completion. +#define USART_FAILURE -1 //!< Failure because of some unspecified reason. +#define USART_INVALID_INPUT 1 //!< Input value out of range. +#define USART_INVALID_ARGUMENT -1 //!< Argument value out of range. +#define USART_TX_BUSY 2 //!< Transmitter was busy. +#define USART_RX_EMPTY 3 //!< Nothing was received. +#define USART_RX_ERROR 4 //!< Transmission error occurred. +#define USART_MODE_FAULT 5 //!< USART not in the appropriate mode. +//! @} + +//! Default time-out value (number of attempts). +#define USART_DEFAULT_TIMEOUT 10000 + +/*! \name Parity Settings + */ +//! @{ +#define USART_EVEN_PARITY AVR32_USART_MR_PAR_EVEN //!< Use even parity on character transmission. +#define USART_ODD_PARITY AVR32_USART_MR_PAR_ODD //!< Use odd parity on character transmission. +#define USART_SPACE_PARITY AVR32_USART_MR_PAR_SPACE //!< Use a space as parity bit. +#define USART_MARK_PARITY AVR32_USART_MR_PAR_MARK //!< Use a mark as parity bit. +#define USART_NO_PARITY AVR32_USART_MR_PAR_NONE //!< Don't use a parity bit. +#define USART_MULTIDROP_PARITY AVR32_USART_MR_PAR_MULTI //!< Parity bit is used to flag address characters. +//! @} + +/*! \name Operating Modes + */ +//! @{ +#define USART_MODE_NORMAL AVR32_USART_MR_MODE_NORMAL //!< Normal RS232 mode. +#define USART_MODE_RS485 AVR32_USART_MR_MODE_RS485 //!< RS485 mode. +#define USART_MODE_HW_HSH AVR32_USART_MR_MODE_HARDWARE //!< RS232 mode with hardware handshaking. +#define USART_MODE_MODEM AVR32_USART_MR_MODE_MODEM //!< Modem mode. +#define USART_MODE_ISO7816_T0 AVR32_USART_MR_MODE_ISO7816_T0 //!< ISO7816, T = 0 mode. +#define USART_MODE_ISO7816_T1 AVR32_USART_MR_MODE_ISO7816_T1 //!< ISO7816, T = 1 mode. +#define USART_MODE_IRDA AVR32_USART_MR_MODE_IRDA //!< IrDA mode. +#define USART_MODE_SW_HSH AVR32_USART_MR_MODE_SOFTWARE //!< RS232 mode with software handshaking. +//! @} + + +/*! \name Channel Modes + */ +//! @{ +#define USART_NORMAL_CHMODE AVR32_USART_MR_CHMODE_NORMAL //!< Normal communication. +#define USART_AUTO_ECHO AVR32_USART_MR_CHMODE_ECHO //!< Echo data. +#define USART_LOCAL_LOOPBACK AVR32_USART_MR_CHMODE_LOCAL_LOOP //!< Local loopback. +#define USART_REMOTE_LOOPBACK AVR32_USART_MR_CHMODE_REMOTE_LOOP //!< Remote loopback. +//! @} + +/*! \name Stop Bits Settings + */ +//! @{ +#define USART_1_STOPBIT AVR32_USART_MR_NBSTOP_1 //!< Use 1 stop bit. +#define USART_1_5_STOPBITS AVR32_USART_MR_NBSTOP_1_5 //!< Use 1.5 stop bits. +#define USART_2_STOPBITS AVR32_USART_MR_NBSTOP_2 //!< Use 2 stop bits (for more, just give the number of bits). +//! @} + + +//! Input parameters when initializing RS232 and similar modes. +typedef struct +{ + //! Set baudrate of the USART. + unsigned long baudrate; + + //! Number of bits to transmit as a character (5 to 9). + unsigned char charlength; + + //! How to calculate the parity bit: \ref USART_EVEN_PARITY, \ref USART_ODD_PARITY, + //! \ref USART_SPACE_PARITY, \ref USART_MARK_PARITY, \ref USART_NO_PARITY or + //! \ref USART_MULTIDROP_PARITY. + unsigned char paritytype; + + //! Number of stop bits between two characters: \ref USART_1_STOPBIT, + //! \ref USART_1_5_STOPBITS, \ref USART_2_STOPBITS or any number from 3 to 257 + //! which will result in a time guard period of that length between characters. + unsigned short stopbits; + + //! Run the channel in testmode: \ref USART_NORMAL_CHMODE, \ref USART_AUTO_ECHO, + //! \ref USART_LOCAL_LOOPBACK or \ref USART_REMOTE_LOOPBACK. + unsigned char channelmode; +} usart_options_t; + +//! Input parameters when initializing ISO7816 modes. +typedef struct +{ + //! Set the frequency of the ISO7816 clock. + unsigned long iso7816_hz; + + //! The number of ISO7816 clock ticks in every bit period (1 to 2047, 0 = disable clock). + //! Bit rate = \ref iso7816_hz / \ref fidi_ratio. + unsigned short fidi_ratio; + + //! Inhibit Non Acknowledge:\n + //! - 0: the NACK is generated;\n + //! - 1: the NACK is not generated. + //! + //! \note This bit will be used only in ISO7816 mode, protocol T = 0 receiver. + int inhibit_nack; + + //! Disable successive NACKs. + //! Successive parity errors are counted up to the value in the \ref max_iterations field. + //! These parity errors generate a NACK on the ISO line. As soon as this value is reached, + //! no addititional NACK is sent on the ISO line. The ITERATION flag is asserted. + int dis_suc_nack; + + //! Max number of repetitions (0 to 7). + unsigned char max_iterations; + + //! Bit order in transmitted characters:\n + //! - 0: LSB first;\n + //! - 1: MSB first. + int bit_order; +} iso7816_options_t; + +//! Input parameters when initializing ISO7816 modes. +typedef struct +{ + //! Set the frequency of the SPI clock. + unsigned long baudrate; + + //! Number of bits to transmit as a character (5 to 9). + unsigned char charlength; + + //! Run the channel in testmode: \ref USART_NORMAL_CHMODE, \ref USART_AUTO_ECHO, + //! \ref USART_LOCAL_LOOPBACK or \ref USART_REMOTE_LOOPBACK. + unsigned char channelmode; + + //! Which SPI mode to use when transmitting. + unsigned char spimode; +} usart_spi_options_t; + + + + + +//------------------------------------------------------------------------------ +/*! \name Initialization Functions + */ +//! @{ + +/*! \brief Resets the USART and disables TX and RX. + * + * \param usart Base address of the USART instance. + */ +extern void usart_reset(volatile avr32_usart_t *usart); + +/*! \brief Sets up the USART to use the standard RS232 protocol. + * + * \param usart Base address of the USART instance. + * \param opt Options needed to set up RS232 communication (see \ref usart_options_t). + * \param pba_hz USART module input clock frequency (PBA clock, Hz). + * + * \retval USART_SUCCESS Mode successfully initialized. + * \retval USART_INVALID_INPUT One or more of the arguments is out of valid range. + */ +extern int usart_init_rs232(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz); + +/*! \brief Sets up the USART to use hardware handshaking. + * + * \param usart Base address of the USART instance. + * \param opt Options needed to set up RS232 communication (see \ref usart_options_t). + * \param pba_hz USART module input clock frequency (PBA clock, Hz). + * + * \retval USART_SUCCESS Mode successfully initialized. + * \retval USART_INVALID_INPUT One or more of the arguments is out of valid range. + * + * \note \ref usart_init_rs232 does not need to be invoked before this function. + */ +extern int usart_init_hw_handshaking(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz); + +/*! \brief Sets up the USART to use the IrDA protocol. + * + * \param usart Base address of the USART instance. + * \param opt Options needed to set up RS232 communication (see \ref usart_options_t). + * \param pba_hz USART module input clock frequency (PBA clock, Hz). + * \param irda_filter Counter used to distinguish received ones from zeros. + * + * \retval USART_SUCCESS Mode successfully initialized. + * \retval USART_INVALID_INPUT One or more of the arguments is out of valid range. + */ +extern int usart_init_IrDA(volatile avr32_usart_t *usart, const usart_options_t *opt, + long pba_hz, unsigned char irda_filter); + +/*! \brief Sets up the USART to use the modem protocol, activating dedicated inputs/outputs. + * + * \param usart Base address of the USART instance. + * \param opt Options needed to set up RS232 communication (see \ref usart_options_t). + * \param pba_hz USART module input clock frequency (PBA clock, Hz). + * + * \retval USART_SUCCESS Mode successfully initialized. + * \retval USART_INVALID_INPUT One or more of the arguments is out of valid range. + */ +extern int usart_init_modem(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz); + +/*! \brief Sets up the USART to use the RS485 protocol. + * + * \param usart Base address of the USART instance. + * \param opt Options needed to set up RS232 communication (see \ref usart_options_t). + * \param pba_hz USART module input clock frequency (PBA clock, Hz). + * + * \retval USART_SUCCESS Mode successfully initialized. + * \retval USART_INVALID_INPUT One or more of the arguments is out of valid range. + */ +extern int usart_init_rs485(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz); + +/*! \brief Sets up the USART to use the ISO7816 T=0 or T=1 smartcard protocols. + * + * \param usart Base address of the USART instance. + * \param opt Options needed to set up ISO7816 communication (see \ref iso7816_options_t). + * \param t ISO7816 mode to use (T=0 or T=1). + * \param pba_hz USART module input clock frequency (PBA clock, Hz). + * + * \retval USART_SUCCESS Mode successfully initialized. + * \retval USART_INVALID_INPUT One or more of the arguments is out of valid range. + */ +extern int usart_init_iso7816(volatile avr32_usart_t *usart, const iso7816_options_t *opt, int t, long pba_hz); + +/*! \brief Sets up the USART to use the SPI mode as master. + * + * \param usart Base address of the USART instance. + * \param opt Options needed to set up SPI mode (see \ref usart_spi_options_t). + * \param pba_hz USART module input clock frequency (PBA clock, Hz). + * + * \retval USART_SUCCESS Mode successfully initialized. + * \retval USART_INVALID_INPUT One or more of the arguments is out of valid range. + */ +extern int usart_init_spi_master(volatile avr32_usart_t *usart, const usart_spi_options_t *opt, long pba_hz); + + +/*! \brief Sets up the USART to use the SPI mode as slave. + * + * \param usart Base address of the USART instance. + * \param opt Options needed to set up SPI mode (see \ref usart_spi_options_t). + * \param pba_hz USART module input clock frequency (PBA clock, Hz). + * + * \retval USART_SUCCESS Mode successfully initialized. + * \retval USART_INVALID_INPUT One or more of the arguments is out of valid range. + */ +extern int usart_init_spi_slave(volatile avr32_usart_t *usart, const usart_spi_options_t *opt, long pba_hz); + +//! @} + +//------------------------------------------------------------------------------ +/*! \brief Selects slave chip. + * + * \param usart Base address of the USART instance. + * + * \return Status. + * \retval USART_SUCCESS Success. + */ +extern int usart_spi_selectChip(volatile avr32_usart_t *usart); + +/*! \brief Unselects slave chip. + * + * \param usart Base address of the USART instance. + * + * \return Status. + * \retval USART_SUCCESS Success. + * \retval USART_FAILURE Time out. + */ +extern int usart_spi_unselectChip(volatile avr32_usart_t *usart); + +//------------------------------------------------------------------------------ +/*! \name Read and Reset Error Status Bits + */ +//! @{ + +/*! \brief Resets the error status. + * + * This function resets the status bits indicating that a parity error, + * framing error or overrun has occurred. The RXBRK bit, indicating + * a start/end of break condition on the RX line, is also reset. + * + * \param usart Base address of the USART instance. + */ +#if __GNUC__ +__attribute__((__always_inline__)) +#endif +extern __inline__ void usart_reset_status(volatile avr32_usart_t *usart) +{ + usart->cr |= AVR32_USART_CR_RSTSTA_MASK; +} + +/*! \brief Checks if a parity error has occurred since last status reset. + * + * \param usart Base address of the USART instance. + * + * \return \c 1 if a parity error has been detected, otherwise \c 0. + */ +#if __GNUC__ +__attribute__((__always_inline__)) +#endif +extern __inline__ int usart_parity_error(volatile avr32_usart_t *usart) +{ + return (usart->csr & AVR32_USART_CSR_PARE_MASK) != 0; +} + +/*! \brief Checks if a framing error has occurred since last status reset. + * + * \param usart Base address of the USART instance. + * + * \return \c 1 if a framing error has been detected, otherwise \c 0. + */ +#if __GNUC__ +__attribute__((__always_inline__)) +#endif +extern __inline__ int usart_framing_error(volatile avr32_usart_t *usart) +{ + return (usart->csr & AVR32_USART_CSR_FRAME_MASK) != 0; +} + +/*! \brief Checks if an overrun error has occurred since last status reset. + * + * \param usart Base address of the USART instance. + * + * \return \c 1 if a overrun error has been detected, otherwise \c 0. + */ +#if __GNUC__ +__attribute__((__always_inline__)) +#endif +extern __inline__ int usart_overrun_error(volatile avr32_usart_t *usart) +{ + return (usart->csr & AVR32_USART_CSR_OVRE_MASK) != 0; +} + +//! @} + + +//------------------------------------------------------------------------------ +/*! \name Transmit/Receive Functions + */ +//! @{ + +/*! \brief Addresses a receiver. + * + * While in RS485 mode, receivers only accept data addressed to them. + * A packet/char with the address tag set has to precede any data. + * This function is used to address a receiver. This receiver should read + * all the following data, until an address packet addresses another receiver. + * + * \param usart Base address of the USART instance. + * \param address Address of the target device. + * + * \retval USART_SUCCESS Address successfully sent (if current mode is RS485). + * \retval USART_MODE_FAULT Wrong operating mode. + */ +extern int usart_send_address(volatile avr32_usart_t *usart, int address); + +/*! \brief Writes the given character to the TX buffer if the transmitter is ready. + * + * \param usart Base address of the USART instance. + * \param c The character (up to 9 bits) to transmit. + * + * \retval USART_SUCCESS The transmitter was ready. + * \retval USART_TX_BUSY The transmitter was busy. + */ +extern int usart_write_char(volatile avr32_usart_t *usart, int c); + +/*! \brief An active wait writing a character to the USART. + * + * \param usart Base address of the USART instance. + * \param c The character (up to 9 bits) to transmit. + */ +#if __GNUC__ +__attribute__((__always_inline__)) +#endif +extern __inline__ void usart_bw_write_char(volatile avr32_usart_t *usart, int c) +{ + while (usart_write_char(usart, c) != USART_SUCCESS); +} + +/*! \brief Sends a character with the USART. + * + * \param usart Base address of the USART instance. + * \param c Character to write. + * + * \retval USART_SUCCESS The character was written. + * \retval USART_FAILURE The function timed out before the USART transmitter became ready to send. + */ +extern int usart_putchar(volatile avr32_usart_t *usart, int c); + +/*! \brief Checks the RX buffer for a received character, and stores it at the + * given memory location. + * + * \param usart Base address of the USART instance. + * \param c Pointer to the where the read character should be stored + * (must be at least short in order to accept 9-bit characters). + * + * \retval USART_SUCCESS The character was read successfully. + * \retval USART_RX_EMPTY The RX buffer was empty. + * \retval USART_RX_ERROR An error was deteceted. + */ +extern int usart_read_char(volatile avr32_usart_t *usart, int *c); + +/*! \brief Waits until a character is received, and returns it. + * + * \param usart Base address of the USART instance. + * + * \return The received character, or \ref USART_FAILURE upon error. + */ +extern int usart_getchar(volatile avr32_usart_t *usart); + +/*! \brief Writes one character string to the USART. + * + * \param usart Base address of the USART instance. + * \param string String to be written. + */ +extern void usart_write_line(volatile avr32_usart_t *usart, const char *string); + +/*! \brief Gets and echoes characters until end of line. + * + * \param usart Base address of the USART instance. + * + * \retval USART_SUCCESS Success. + * \retval USART_FAILURE ETX character received. + */ +extern int usart_get_echo_line(volatile avr32_usart_t *usart); + +//! @} + + +#endif // _USART_H_ diff --git a/20080212/Demo/lwIP_AVR32_UC3/FreeRTOSConfig.h b/20080212/Demo/lwIP_AVR32_UC3/FreeRTOSConfig.h new file mode 100644 index 000000000..3f078d606 --- /dev/null +++ b/20080212/Demo/lwIP_AVR32_UC3/FreeRTOSConfig.h @@ -0,0 +1,103 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief FreeRTOS and lwIP example for AVR32 UC3. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include "board.h" + + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( 48000000 ) /* Hz clk gen */ +#define configPBA_CLOCK_HZ ( 24000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 8 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 256 ) +/* configTOTAL_HEAP_SIZE is not used when heap_3.c is used. */ +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1024*25 ) ) +#define configMAX_TASK_NAME_LEN ( 20 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 0 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_xTaskGetSchedulerState 0 + +/* configTICK_USE_TC is a boolean indicating whether to use a Timer Counter + for the tick generation. Timer Counter will generate an accurate Tick; + otherwise the CPU will generate a tick but with time drift. + configTICK_TC_CHANNEL is the TC channel. */ +#define configTICK_USE_TC 1 +#define configTICK_TC_CHANNEL 2 + +/* configHEAP_INIT is a boolean indicating whether to initialize the heap with + 0xA5 in order to be able to determine the maximal heap consumption. */ +#define configHEAP_INIT 0 + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/lwIP_AVR32_UC3/NETWORK/BasicSMTP/BasicSMTP.c b/20080212/Demo/lwIP_AVR32_UC3/NETWORK/BasicSMTP/BasicSMTP.c new file mode 100644 index 000000000..3dca3d37f --- /dev/null +++ b/20080212/Demo/lwIP_AVR32_UC3/NETWORK/BasicSMTP/BasicSMTP.c @@ -0,0 +1,325 @@ +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Basic SMTP Client for AVR32 UC3. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + *****************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + Implements a simplistic SMTP client. First time the task is started, connection is made and + email is sent. Mail flag is then reset. Each time you press the Push Button 0, a new mail will be sent. +*/ + +#if (SMTP_USED == 1) + +#include + +// Scheduler includes. +#include "FreeRTOS.h" +#include "task.h" +#include "BasicSMTP.h" + + +// Demo includes. +#include "portmacro.h" +#include "partest.h" +#include "intc.h" +#include "gpio.h" + +// lwIP includes. +#include "lwip/api.h" +#include "lwip/tcpip.h" +#include "lwip/memp.h" +#include "lwip/stats.h" +#include "lwip/opt.h" +#include "lwip/api.h" +#include "lwip/arch.h" +#include "lwip/sys.h" +#include "lwip/sockets.h" +#include "netif/loopif.h" + +//! SMTP default port +#define SMTP_PORT 25 +//! SMTP EHLO code answer +#define SMTP_EHLO_STRING "220" +//! SMTP end of transmission code answer +#define SMTP_END_OF_TRANSMISSION_STRING "221" +//! SMTP OK code answer +#define SMTP_OK_STRING "250" +//! SMTP start of transmission code answer +#define SMTP_START_OF_TRANSMISSION_STRING "354" +//! SMTP DATA +#define SMTP_DATA_STRING "DATA\r\n" +//! SMTP . +#define SMTP_MAIL_END_STRING "\r\n.\r\n" +//! SMTP QUIT +#define SMTP_QUIT_STRING "QUIT\r\n" + + +//! Server address +#error configure SMTP server address +portCHAR cServer[] = "192.168.0.1"; + +//! Fill here the mailfrom with your mail address +#error configure SMTP mail sender +char cMailfrom[] = "MAIL FROM: \r\n"; + +//! Fill here the mailto with your contact mail address +#error configure SMTP mail recipient +char cMailto[] = "RCPT TO: \r\n"; + +//! Fill here the mailcontent with the mail you want to send +#error configure SMTP mail content +char cMailcontent[] ="Subject: *** SPAM ***\r\nFROM: \"Your Name here\" \r\nTO: \"Your Contact here\" \r\n\r\nSay what you want here."; + +//! flag to send mail +Bool bSendMail = pdFALSE; + +//! buffer for SMTP response +portCHAR cTempBuffer[200]; + + +//_____ D E C L A R A T I O N S ____________________________________________ +//! interrupt handler. +#if __GNUC__ +__attribute__((naked)) +#elif __ICCAVR32__ +#pragma shadow_registers = full // Naked. +#endif +void vpushb_ISR( void ); + +//! soft interrupt handler. where treatment should be done +#if __GNUC__ +__attribute__((__noinline__)) +#endif +static portBASE_TYPE prvpushb_ISR_NonNakedBehaviour( void ); + + + +//! Basic SMTP client task definition +portTASK_FUNCTION( vBasicSMTPClient, pvParameters ) +{ + struct sockaddr_in stServeurSockAddr; + portLONG lRetval; + portLONG lSocket = -1; + + // configure push button 0 to produce IT on falling edge + gpio_enable_pin_interrupt(GPIO_PUSH_BUTTON_0 , GPIO_FALLING_EDGE); + // Disable all interrupts + vPortEnterCritical(); + // register push button 0 handler on level 3 + INTC_register_interrupt( (__int_handler)&vpushb_ISR, AVR32_GPIO_IRQ_0 + (GPIO_PUSH_BUTTON_0/8), INT3); + // Enable all interrupts + vPortExitCritical(); + + for (;;) + { + // wait for a signal to send a mail + while (bSendMail != pdTRUE) vTaskDelay(200); + + // Disable all interrupts + vPortEnterCritical(); + // clear the flag + bSendMail = pdFALSE; + // Enable all interrupts + vPortExitCritical(); + // clear the LED + vParTestSetLED( 3 , pdFALSE ); + // Set up port + memset(&stServeurSockAddr, 0, sizeof(stServeurSockAddr)); + stServeurSockAddr.sin_len = sizeof(stServeurSockAddr); + stServeurSockAddr.sin_addr.s_addr = inet_addr(cServer); + stServeurSockAddr.sin_port = htons(SMTP_PORT); + stServeurSockAddr.sin_family = AF_INET; + + // socket as a stream + if ( (lSocket = socket(AF_INET, SOCK_STREAM, 0)) < 0) + { + // socket failed, blink a LED and stay here + for (;;) { + vParTestToggleLED( 4 ); + vTaskDelay( 200 ); + } + } + // connect to the server + if(connect(lSocket,(struct sockaddr *)&stServeurSockAddr, sizeof(stServeurSockAddr)) < 0) + { + // connect failed, blink a LED and stay here + for (;;) { + vParTestToggleLED( 6 ); + vTaskDelay( 200 ); + } + } + else + { +//Server: 220 SMTP Ready + // wait for SMTP Server answer + do + { + lRetval = recv(lSocket, cTempBuffer, sizeof(cTempBuffer), 0); + }while (lRetval <= 0); + if (strncmp(cTempBuffer, SMTP_EHLO_STRING, sizeof(cTempBuffer)) >= 0) + { +//Client: EHLO smtp.domain.com + // send ehlo + send(lSocket, "HELO ", 5, 0); + send(lSocket, cServer, strlen(cServer), 0); + send(lSocket, "\r\n", 2, 0); +//Server: 250 + // wait for SMTP Server answer + do + { + lRetval = recv(lSocket, cTempBuffer, sizeof(cTempBuffer), 0); + }while (lRetval <= 0); + if (strncmp(cTempBuffer, SMTP_OK_STRING, sizeof(cTempBuffer)) >= 0) + { +//Client: MAIL FROM: + // send MAIL FROM + send(lSocket, cMailfrom, strlen(cMailfrom), 0); +//Server: 250 OK + // wait for SMTP Server answer + do + { + lRetval = recv(lSocket, cTempBuffer, sizeof(cTempBuffer), 0); + }while (lRetval <= 0); + if (strncmp(cTempBuffer, SMTP_OK_STRING, sizeof(cTempBuffer)) >= 0) + { +//Client: RCPT TO: + // send RCPT TO + send(lSocket, cMailto, strlen(cMailto), 0); +//Server: 250 OK + // wait for SMTP Server answer + do + { + lRetval = recv(lSocket, cTempBuffer, sizeof(cTempBuffer), 0); + }while (lRetval <= 0); + if (strncmp(cTempBuffer, SMTP_OK_STRING, sizeof(cTempBuffer)) >= 0) + { +//Client: DATA + // send DATA + send(lSocket, SMTP_DATA_STRING, 6, 0); +//Server: 354 Start mail input; end with . + // wait for SMTP Server answer + do + { + lRetval = recv(lSocket, cTempBuffer, sizeof(cTempBuffer), 0); + }while (lRetval <= 0); + if (strncmp(cTempBuffer, SMTP_START_OF_TRANSMISSION_STRING, sizeof(cTempBuffer)) >= 0) + { + // send content + send(lSocket, cMailcontent, strlen(cMailcontent), 0); +//Client: . + // send "." + send(lSocket, SMTP_MAIL_END_STRING, 5, 0); +//Server: 250 OK + // wait for SMTP Server answer + do + { + lRetval = recv(lSocket, cTempBuffer, sizeof(cTempBuffer), 0); + }while (lRetval <= 0); + if (strncmp(cTempBuffer, SMTP_OK_STRING, sizeof(cTempBuffer)) >= 0) + { +//Client: QUIT + // send QUIT + send(lSocket, SMTP_QUIT_STRING, 8, 0); +//Server: 221 smtp.domain.com closing transmission + do + { + lRetval = recv(lSocket, cTempBuffer, sizeof(cTempBuffer), 0); + }while (lRetval <= 0); + if (strncmp(cTempBuffer, SMTP_END_OF_TRANSMISSION_STRING, sizeof(cTempBuffer)) >= 0) + { + vParTestSetLED( 3 , pdTRUE ); + } + } + } + } + } + } + // close socket + close(lSocket); + } + } + } +} + +/*! \brief push button naked interrupt handler. + * + */ +#if __GNUC__ +__attribute__((naked)) +#elif __ICCAVR32__ +#pragma shadow_registers = full // Naked. +#endif +void vpushb_ISR( void ) +{ + /* This ISR can cause a context switch, so the first statement must be a + call to the portENTER_SWITCHING_ISR() macro. This must be BEFORE any + variable declarations. */ + portENTER_SWITCHING_ISR(); + + prvpushb_ISR_NonNakedBehaviour(); + + portEXIT_SWITCHING_ISR(); +} + +/*! \brief push button interrupt handler. Here, declarations should be done + * + */ +#if __GNUC__ +__attribute__((__noinline__)) +#elif __ICCAVR32__ +#pragma optimize = no_inline +#endif +static portBASE_TYPE prvpushb_ISR_NonNakedBehaviour( void ) +{ + if (gpio_get_pin_interrupt_flag(GPIO_PUSH_BUTTON_0)) + { + // set the flag + bSendMail = pdTRUE; + // allow new interrupt : clear the IFR flag + gpio_clear_pin_interrupt_flag(GPIO_PUSH_BUTTON_0); + } + // no context switch required, task is polling the flag + return( pdFALSE ); +} + + + + + +#endif diff --git a/20080212/Demo/lwIP_AVR32_UC3/NETWORK/BasicSMTP/BasicSMTP.h b/20080212/Demo/lwIP_AVR32_UC3/NETWORK/BasicSMTP/BasicSMTP.h new file mode 100644 index 000000000..b4e58b2d7 --- /dev/null +++ b/20080212/Demo/lwIP_AVR32_UC3/NETWORK/BasicSMTP/BasicSMTP.h @@ -0,0 +1,55 @@ +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Basic SMTP Client for AVR32 UC3. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + *****************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef BASIC_SMTP_SERVER_H +#define BASIC_SMTP_SERVER_H + +#include "portmacro.h" + + +/* The function that implements the SMTP client task. */ +portTASK_FUNCTION_PROTO( vBasicSMTPClient, pvParameters ); + + + +#endif + diff --git a/20080212/Demo/lwIP_AVR32_UC3/NETWORK/BasicTFTP/BasicTFTP.c b/20080212/Demo/lwIP_AVR32_UC3/NETWORK/BasicTFTP/BasicTFTP.c new file mode 100644 index 000000000..fe0838022 --- /dev/null +++ b/20080212/Demo/lwIP_AVR32_UC3/NETWORK/BasicTFTP/BasicTFTP.c @@ -0,0 +1,470 @@ +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Basic TFTP Server for AVR32 UC3. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + *****************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +/* + Implements a simplistic TFTP server. + + In order to put data on the TFTP server (not over 2048 bytes) + tftp 192.168.0.2 PUT + this will copy file from your hard drive to the RAM buffer of the application + + tftp 192.168.0.2 GET + this will copy file from the RAM buffer of the application to your hard drive + You can then check that src_filename and dst_filename are identical +*/ + +#if (TFTP_USED == 1) + +#include + + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "partest.h" +#include "BasicTFTP.h" + + +/* Demo includes. */ +#include "portmacro.h" + +/* lwIP includes. */ +#include "lwip/api.h" +#include "lwip/tcpip.h" +#include "lwip/memp.h" +#include "lwip/stats.h" +#include "lwip/opt.h" +#include "lwip/api.h" +#include "lwip/arch.h" +#include "lwip/sys.h" +#include "netif/loopif.h" +#include "lwip/sockets.h" + +#define O_WRONLY 1 +#define O_RDONLY 2 + + +/* The port on which we listen. */ +#define TFTP_PORT ( 69 ) + +/* Delay on close error. */ +#define TFTP_DELAY ( 10 ) + +/* Delay on bind error. */ +#define TFTP_ERROR_DELAY ( 40 ) + +#define TFTP_LED ( 4 ) + +char data_out[SEGSIZE+sizeof(struct tftphdr)]; +char data_in[SEGSIZE+sizeof(struct tftphdr)]; + +//struct tftp_server *server; + +/*------------------------------------------------------------*/ +static char * errmsg[] = { + "Undefined error code", // 0 nothing defined + "File not found", // 1 TFTP_ENOTFOUND + "Access violation", // 2 TFTP_EACCESS + "Disk full or allocation exceeded", // 3 TFTP_ENOSPACE + "Illegal TFTP operation", // 4 TFTP_EBADOP + "Unknown transfer ID", // 5 TFTP_EBADID + "File already exists", // 6 TFTP_EEXISTS + "No such user", // 7 TFTP_ENOUSER +}; + + +/* Send an error packet to the client */ +static void +tftpd_send_error(int s, struct tftphdr * reply, int err, + struct sockaddr_in *from_addr, int from_len) +{ + if ( ( 0 <= err ) && ( sizeof(errmsg)/sizeof(errmsg[0]) > err) ) { + reply->th_opcode = htons(ERROR); + reply->th_code = htons(err); + if ( (0 > err) || (sizeof(errmsg)/sizeof(errmsg[0]) <= err) ) + err = 0; // Do not copy a random string from hyperspace + strcpy(reply->th_msg, errmsg[err]); + sendto(s, reply, 4+strlen(reply->th_msg)+1, 0, + (struct sockaddr *)from_addr, from_len); + } +} + +portCHAR cRamBuffer[2048]; +int lCurrentBlock = 0; +int lTotalLength = 0; + + +int tftpd_close_data_file(int fd) +{ + lCurrentBlock = 0; + return (5); +} + +int tftpd_open_data_file(int fd, int mode) +{ + lCurrentBlock = 0; + return (5); +} + +int tftpd_read_data_file(int fd, portCHAR * buffer, int length) +{ +int lReturnValue; + + if ((lTotalLength -= length) >= 0) { + lReturnValue = length; + } + else + { + lReturnValue = lTotalLength + length; + lTotalLength = 0; + } + memcpy(buffer, &cRamBuffer[lCurrentBlock * SEGSIZE], lReturnValue); + lCurrentBlock++; + return (lReturnValue); +} + +// +// callback to store data to the RAM buffer +// +int tftpd_write_data_file(int fd, portCHAR * buffer, int length) +{ + lTotalLength += length; + memcpy(&cRamBuffer[lCurrentBlock * SEGSIZE], buffer, length); + lCurrentBlock++; + return (length); +} + +// +// Receive a file from the client +// +static void +tftpd_write_file(struct tftphdr *hdr, + struct sockaddr_in *from_addr, int from_len) +{ + + struct tftphdr *reply = (struct tftphdr *)data_out; + struct tftphdr *response = (struct tftphdr *)data_in; + int fd, len, ok, tries, closed, data_len, s; + unsigned short block; + struct timeval timeout; + fd_set fds; + int total_timeouts = 0; + struct sockaddr_in client_addr, local_addr; + int client_len; + + + s = socket(AF_INET, SOCK_DGRAM, 0); + if (s < 0) { + return; + } + + memset((char *)&local_addr, 0, sizeof(local_addr)); + local_addr.sin_family = AF_INET; + local_addr.sin_len = sizeof(local_addr); + local_addr.sin_addr.s_addr = htonl(INADDR_ANY); + local_addr.sin_port = htons(INADDR_ANY); + + if (bind(s, (struct sockaddr *)&local_addr, sizeof(local_addr)) < 0) { + // Problem setting up my end + close(s); + return; + } + + if ((fd = tftpd_open_data_file((int)hdr->th_stuff, O_WRONLY)) < 0) { + tftpd_send_error(s,reply,TFTP_ENOTFOUND,from_addr, from_len); + close(s); + return; + } + + ok = pdTRUE; + closed = pdFALSE; + block = 0; + while (ok) { + // Send ACK telling client he can send data + reply->th_opcode = htons(ACK); + reply->th_block = htons(block++); // postincrement + for (tries = 0; tries < TFTP_RETRIES_MAX; tries++) { + sendto(s, reply, 4, 0, (struct sockaddr *)from_addr, from_len); + repeat_select: + timeout.tv_sec = TFTP_TIMEOUT_PERIOD; + timeout.tv_usec = 0; + FD_ZERO(&fds); + FD_SET(s, &fds); + vParTestToggleLED( TFTP_LED ); + if (lwip_select(s+1, &fds, 0, 0, &timeout) <= 0) { + if (++total_timeouts > TFTP_TIMEOUT_MAX) { + tftpd_send_error(s,reply,TFTP_EBADOP,from_addr, from_len); + ok = pdFALSE; + break; + } + continue; // retry the send, using up one retry. + } + vParTestToggleLED( TFTP_LED ); + // Some data has arrived + data_len = sizeof(data_in); + client_len = sizeof(client_addr); + if ((data_len = recvfrom(s, data_in, data_len, 0, + (struct sockaddr *)&client_addr, &client_len)) < 0) { + // What happened? No data here! + continue; // retry the send, using up one retry. + } + if (ntohs(response->th_opcode) == DATA && + ntohs(response->th_block) < block) { + // Then it is repeat DATA with an old block; listen again, + // but do not repeat sending the current ack, and do not + // use up a retry count. (we do re-send the ack if + // subsequently we time out) + goto repeat_select; + } + if (ntohs(response->th_opcode) == DATA && + ntohs(response->th_block) == block) { + // Good data - write to file + len = tftpd_write_data_file(fd, response->th_data, data_len-4); + if (len < (data_len-4)) { + // File is "full" + tftpd_send_error(s,reply,TFTP_ENOSPACE, + from_addr, from_len); + ok = pdFALSE; // Give up + break; // out of the retries loop + } + if (data_len < (SEGSIZE+4)) { + // End of file + closed = pdTRUE; + ok = pdFALSE; + vParTestSetLED( 0 , 0 ); + + if (tftpd_close_data_file(fd) == -1) { + tftpd_send_error(s,reply,TFTP_EACCESS, + from_addr, from_len); + + break; // out of the retries loop + } + // Exception to the loop structure: we must ACK the last + // packet, the one that implied EOF: + reply->th_opcode = htons(ACK); + reply->th_block = htons(block++); // postincrement + sendto(s, reply, 4, 0, (struct sockaddr *)from_addr, from_len); + break; // out of the retries loop + } + // Happy! Break out of the retries loop. + break; + } + } // End of the retries loop. + if (TFTP_RETRIES_MAX <= tries) { + tftpd_send_error(s,reply,TFTP_EBADOP,from_addr, from_len); + ok = pdFALSE; + } + } + close(s); + if (!closed) { + tftpd_close_data_file(fd); + } +} + + +// +// Send a file to the client +// +static void +tftpd_read_file(struct tftphdr *hdr, + struct sockaddr_in *from_addr, int from_len) +{ + struct tftphdr *reply = (struct tftphdr *)data_out; + struct tftphdr *response = (struct tftphdr *)data_in; + int fd, len, tries, ok, data_len, s; + unsigned short block; + struct timeval timeout; + fd_set fds; + int total_timeouts = 0; + struct sockaddr_in client_addr, local_addr; + int client_len; + + s = socket(AF_INET, SOCK_DGRAM, 0); + if (s < 0) { + return; + } + memset((char *)&local_addr, 0, sizeof(local_addr)); + local_addr.sin_family = AF_INET; + local_addr.sin_len = sizeof(local_addr); + local_addr.sin_addr.s_addr = htonl(INADDR_ANY); + local_addr.sin_port = htons(INADDR_ANY); + if (bind(s, (struct sockaddr *)&local_addr, sizeof(local_addr)) < 0) { + // Problem setting up my end + close(s); + return; + } + if ((fd = tftpd_open_data_file((int)hdr->th_stuff, O_RDONLY)) < 0) { + tftpd_send_error(s,reply,TFTP_ENOTFOUND,from_addr, from_len); + close(s); + return; + } + block = 0; + ok = pdTRUE; + while (ok) { + // Read next chunk of file + len = tftpd_read_data_file(fd, reply->th_data, SEGSIZE); + reply->th_block = htons(++block); // preincrement + reply->th_opcode = htons(DATA); + for (tries = 0; tries < TFTP_RETRIES_MAX; tries++) { + if (sendto(s, reply, 4+len, 0, + (struct sockaddr *)from_addr, from_len) < 0) { + // Something went wrong with the network! + ok = pdFALSE; + break; + } + repeat_select: + timeout.tv_sec = TFTP_TIMEOUT_PERIOD; + timeout.tv_usec = 0; + FD_ZERO(&fds); + FD_SET(s, &fds); + vParTestToggleLED( TFTP_LED ); + if (select(s+1, &fds, 0, 0, &timeout) <= 0) { + if (++total_timeouts > TFTP_TIMEOUT_MAX) { + tftpd_send_error(s,reply,TFTP_EBADOP,from_addr, from_len); + ok = pdFALSE; + break; + } + continue; // retry the send, using up one retry. + } + vParTestToggleLED( TFTP_LED ); + data_len = sizeof(data_in); + client_len = sizeof(client_addr); + if ((data_len = recvfrom(s, data_in, data_len, 0, + (struct sockaddr *)&client_addr, + &client_len)) < 0) { + // What happened? Maybe someone lied to us... + continue; // retry the send, using up one retry. + } + if ((ntohs(response->th_opcode) == ACK) && + (ntohs(response->th_block) < block)) { + // Then it is a repeat ACK for an old block; listen again, + // but do not repeat sending the current block, and do not + // use up a retry count. (we do re-send the data if + // subsequently we time out) + goto repeat_select; + } + if ((ntohs(response->th_opcode) == ACK) && + (ntohs(response->th_block) == block)) { + // Happy! Break out of the retries loop. + break; + } + } // End of the retries loop. + if (TFTP_RETRIES_MAX <= tries) { + tftpd_send_error(s,reply,TFTP_EBADOP,from_addr, from_len); + ok = pdFALSE; + } + if (len < SEGSIZE) { + break; // That's end of file then. + } + } + close(s); + tftpd_close_data_file(fd); +} + + + +portTASK_FUNCTION( vBasicTFTPServer, pvParameters ) +{ + int lSocket; + int lDataLen, lRecvLen, lFromLen; + struct sockaddr_in sLocalAddr, sFromAddr; + portCHAR cData[SEGSIZE+sizeof(struct tftphdr)]; + struct tftphdr *sHdr = (struct tftphdr *)cData; + + // Set up port + // Network order in info; host order in server: + + for (;;) { + // Create socket + lSocket = socket(AF_INET, SOCK_DGRAM, 0); + if (lSocket < 0) { + return; + } + memset((char *)&sLocalAddr, 0, sizeof(sLocalAddr)); + sLocalAddr.sin_family = AF_INET; + sLocalAddr.sin_len = sizeof(sLocalAddr); + sLocalAddr.sin_addr.s_addr = htonl(INADDR_ANY); + sLocalAddr.sin_port = TFTP_PORT; + + if (bind(lSocket, (struct sockaddr *)&sLocalAddr, sizeof(sLocalAddr)) < 0) { + // Problem setting up my end + close(lSocket); + return; + } + + + lRecvLen = sizeof(cData); + lFromLen = sizeof(sFromAddr); + lDataLen = recvfrom(lSocket, sHdr, lRecvLen, 0, + (struct sockaddr *)&sFromAddr, &lFromLen); + vParTestSetLED( TFTP_LED , pdTRUE ); + close(lSocket); // so that other servers can bind to the TFTP socket + + if ( lDataLen < 0) { + + } else { + switch (ntohs(sHdr->th_opcode)) { + case WRQ: + tftpd_write_file(sHdr, &sFromAddr, lFromLen); + vParTestSetLED( TFTP_LED , pdFALSE ); + break; + case RRQ: + tftpd_read_file(sHdr, &sFromAddr, lFromLen); + vParTestSetLED( TFTP_LED , pdFALSE ); + break; + case ACK: + case DATA: + case ERROR: + vParTestSetLED( TFTP_LED , pdFALSE ); + // Ignore + break; + default: + for(;;) + { + vParTestToggleLED( TFTP_LED ); + vTaskDelay(200); + } + } + } + } +} +#endif diff --git a/20080212/Demo/lwIP_AVR32_UC3/NETWORK/BasicTFTP/BasicTFTP.h b/20080212/Demo/lwIP_AVR32_UC3/NETWORK/BasicTFTP/BasicTFTP.h new file mode 100644 index 000000000..371a9b594 --- /dev/null +++ b/20080212/Demo/lwIP_AVR32_UC3/NETWORK/BasicTFTP/BasicTFTP.h @@ -0,0 +1,154 @@ +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Basic TFTP Server for AVR32 UC3. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + *****************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef BASIC_TFTP_SERVER_H +#define BASIC_TFTP_SERVER_H + +#include "portmacro.h" + +/* tftp_support.h */ + +/* + * File transfer modes + */ +#define TFTP_NETASCII 0 // Text files +#define TFTP_OCTET 1 // Binary files + +/* + * Errors + */ + +// These initial 7 are passed across the net in "ERROR" packets. +#define TFTP_ENOTFOUND 1 /* file not found */ +#define TFTP_EACCESS 2 /* access violation */ +#define TFTP_ENOSPACE 3 /* disk full or allocation exceeded */ +#define TFTP_EBADOP 4 /* illegal TFTP operation */ +#define TFTP_EBADID 5 /* unknown transfer ID */ +#define TFTP_EEXISTS 6 /* file already exists */ +#define TFTP_ENOUSER 7 /* no such user */ +// These extensions are return codes in our API, *never* passed on the net. +#define TFTP_TIMEOUT 8 /* operation timed out */ +#define TFTP_NETERR 9 /* some sort of network error */ +#define TFTP_INVALID 10 /* invalid parameter */ +#define TFTP_PROTOCOL 11 /* protocol violation */ +#define TFTP_TOOLARGE 12 /* file is larger than buffer */ + +#define TFTP_TIMEOUT_PERIOD 5 // Seconds between retries +#define TFTP_TIMEOUT_MAX 50 // Max timeouts over all blocks +#define TFTP_RETRIES_MAX 5 // retries per block before giving up + +/* netdb.h */ +// Internet services +struct servent { +char *s_name; /* official service name */ +char **s_aliases; /* alias list */ +int s_port; /* port number */ +char *s_proto; /* protocol to use */ +}; + +/* arpa/tftp.h */ + +/* + * Trivial File Transfer Protocol (IEN-133) + */ +#define SEGSIZE 512 /* data segment size */ + +/* + * Packet types. + */ + +#define th_block th_u.tu_block +#define th_code th_u.tu_code +#define th_stuff th_u.tu_stuff +#define th_msg th_data + +/* + * Error codes. + */ +#define EUNDEF 0 /* not defined */ +#define ENOTFOUND 1 /* file not found */ +#define EACCESS 2 /* access violation */ +#define ENOSPACE 3 /* disk full or allocation exceeded */ +#define EBADOP 4 /* illegal TFTP operation */ +#define EBADID 5 /* unknown transfer ID */ +#define EEXISTS 6 /* file already exists */ +#define ENOUSER 7 /* no such user */ + + + +#define RRQ 01 /* read request */ +#define WRQ 02 /* write request */ +#define DATA 03 /* data packet */ +#define ACK 04 /* acknowledgement */ +#define ERROR 05 /* error code */ + +#if __ICCAVR32__ +#pragma pack(1) +#endif +struct tftphdr { + short th_opcode; /* packet type */ + union { + unsigned short tu_block; /* block # */ + short tu_code; /* error code */ + char tu_stuff[1]; /* request packet stuff */ + } +#if __GNUC__ + __attribute__ ((packed)) +#endif + th_u; + char th_data[1]; /* data or error string */ +} +#if __GNUC__ +__attribute__ ((packed)) +#endif +; +#if __ICCAVR32__ +#pragma pack() +#endif + +/* The function that implements the TFTP server task. */ +portTASK_FUNCTION_PROTO( vBasicTFTPServer, pvParameters ); + + + +#endif + diff --git a/20080212/Demo/lwIP_AVR32_UC3/NETWORK/BasicWEB/BasicWEB.c b/20080212/Demo/lwIP_AVR32_UC3/NETWORK/BasicWEB/BasicWEB.c new file mode 100644 index 000000000..80a381ed7 --- /dev/null +++ b/20080212/Demo/lwIP_AVR32_UC3/NETWORK/BasicWEB/BasicWEB.c @@ -0,0 +1,205 @@ +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Basic WEB Server for AVR32 UC3. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + *****************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +/* + Implements a simplistic WEB server. Every time a connection is made and + data is received a dynamic page that shows the current FreeRTOS.org kernel + statistics is generated and returned. The connection is then closed. + + This file was adapted from a FreeRTOS lwIP slip demo supplied by a third + party. +*/ + +#if (HTTP_USED == 1) + + +/* Standard includes. */ +#include +#include + +#include "conf_eth.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" +#include "partest.h" +#include "serial.h" + +/* Demo includes. */ +/* Demo app includes. */ +#include "portmacro.h" + +/* lwIP includes. */ +#include "lwip/api.h" +#include "lwip/tcpip.h" +#include "lwip/memp.h" +#include "lwip/stats.h" +#include "netif/loopif.h" + +/* ethernet includes */ +#include "ethernet.h" + +/*! The size of the buffer in which the dynamic WEB page is created. */ +#define webMAX_PAGE_SIZE 512 + +/*! Standard GET response. */ +#define webHTTP_OK "HTTP/1.0 200 OK\r\nContent-type: text/html\r\n\r\n" + +/*! The port on which we listen. */ +#define webHTTP_PORT ( 80 ) + +/*! Delay on close error. */ +#define webSHORT_DELAY ( 10 ) + +/*! Format of the dynamic page that is returned on each connection. */ +#define webHTML_START \ +"\ +\ +\ +\ +\r\nPage Hits = " + +#define webHTML_END \ +"\r\n\ +\r\n\ +" + +portCHAR cDynamicPage[ webMAX_PAGE_SIZE ]; +portCHAR cPageHits[ 11 ]; + + +/*! Function to process the current connection */ +static void prvweb_ParseHTMLRequest( struct netconn *pxNetCon ); + + +/*! \brief WEB server main task + * check for incoming connection and process it + * + * \param pvParameters Input. Not Used. + * + */ +portTASK_FUNCTION( vBasicWEBServer, pvParameters ) +{ +struct netconn *pxHTTPListener, *pxNewConnection; + + /* Create a new tcp connection handle */ + pxHTTPListener = netconn_new( NETCONN_TCP ); + netconn_bind(pxHTTPListener, NULL, webHTTP_PORT ); + netconn_listen( pxHTTPListener ); + + /* Loop forever */ + for( ;; ) + { + /* Wait for a first connection. */ + pxNewConnection = netconn_accept(pxHTTPListener); + vParTestSetLED(webCONN_LED, pdTRUE); + + if(pxNewConnection != NULL) + { + prvweb_ParseHTMLRequest(pxNewConnection); + }/* end if new connection */ + + vParTestSetLED(webCONN_LED, pdFALSE); + + } /* end infinite loop */ +} + + +/*! \brief parse the incoming request + * parse the HTML request and send file + * + * \param pxNetCon Input. The netconn to use to send and receive data. + * + */ +static void prvweb_ParseHTMLRequest( struct netconn *pxNetCon ) +{ +struct netbuf *pxRxBuffer; +portCHAR *pcRxString; +unsigned portSHORT usLength; +static unsigned portLONG ulPageHits = 0; + + /* We expect to immediately get data. */ + pxRxBuffer = netconn_recv( pxNetCon ); + + if( pxRxBuffer != NULL ) + { + /* Where is the data? */ + netbuf_data( pxRxBuffer, ( void * ) &pcRxString, &usLength ); + + /* Is this a GET? We don't handle anything else. */ + if( !strncmp( pcRxString, "GET", 3 ) ) + { + pcRxString = cDynamicPage; + + /* Update the hit count. */ + ulPageHits++; + sprintf( cPageHits, "%d", (int)ulPageHits ); + + /* Write out the HTTP OK header. */ + netconn_write( pxNetCon, webHTTP_OK, (u16_t) strlen( webHTTP_OK ), NETCONN_COPY ); + + /* Generate the dynamic page... First the page header. */ + strcpy( cDynamicPage, webHTML_START ); + + /* ... Then the hit count... */ + strcat( cDynamicPage, cPageHits ); + strcat( cDynamicPage, "

Task          State  Priority  Stack	#
************************************************
" );
+
+			/* ... Then the list of tasks and their status... */
+			vTaskList( ( signed portCHAR * ) cDynamicPage + strlen( cDynamicPage ) );
+
+			/* ... Finally the page footer. */
+			strcat( cDynamicPage, webHTML_END );
+
+			/* Write out the dynamically generated page. */
+			netconn_write( pxNetCon, cDynamicPage, (u16_t) strlen( cDynamicPage ), NETCONN_COPY );
+		}
+		netbuf_delete( pxRxBuffer );
+	}
+
+	netconn_close( pxNetCon );
+	netconn_delete( pxNetCon );
+}
+
+#endif
+
diff --git a/20080212/Demo/lwIP_AVR32_UC3/NETWORK/BasicWEB/BasicWEB.h b/20080212/Demo/lwIP_AVR32_UC3/NETWORK/BasicWEB/BasicWEB.h
new file mode 100644
index 000000000..95e932dd5
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/NETWORK/BasicWEB/BasicWEB.h
@@ -0,0 +1,57 @@
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief Basic WEB Server for AVR32 UC3.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ *****************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef BASIC_WEB_SERVER_H
+#define BASIC_WEB_SERVER_H
+
+#include "portmacro.h"
+
+
+/*! \brief WEB server main task
+ *
+ *  \param pvParameters   Input. Not Used.
+ *
+ */
+portTASK_FUNCTION_PROTO( vBasicWEBServer, pvParameters );
+
+#endif
+
diff --git a/20080212/Demo/lwIP_AVR32_UC3/NETWORK/ethernet.c b/20080212/Demo/lwIP_AVR32_UC3/NETWORK/ethernet.c
new file mode 100644
index 000000000..e14014c69
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/NETWORK/ethernet.c
@@ -0,0 +1,212 @@
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief ethernet management for AVR32 UC3.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ *****************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+
+#include 
+
+#include "conf_eth.h"
+
+/* Scheduler include files. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Demo program include files. */
+#include "partest.h"
+#include "serial.h"
+
+
+/* ethernet includes */
+#include "ethernet.h"
+#include "conf_eth.h"
+#include "macb.h"
+#include "gpio.h"
+
+#if (HTTP_USED == 1)
+  #include "BasicWEB.h"
+#endif
+
+#if (TFTP_USED == 1)
+  #include "BasicTFTP.h"
+#endif
+
+#if (SMTP_USED == 1)
+  #include "BasicSMTP.h"
+#endif
+
+/* lwIP includes */
+#include "lwip/sys.h"
+#include "lwip/api.h" 
+#include "lwip/tcpip.h"
+#include "lwip/memp.h" 
+#include "lwip/stats.h"
+#include "netif/loopif.h"
+
+
+//_____ M A C R O S ________________________________________________________
+
+
+//_____ D E F I N I T I O N S ______________________________________________
+
+/* global variable containing MAC Config (hw addr, IP, GW, ...) */
+struct netif MACB_if;
+
+//_____ D E C L A R A T I O N S ____________________________________________
+
+/* Initialisation required by lwIP. */
+static void prvlwIPInit( void );
+
+/* Initialisation of ethernet interfaces by reading config file */
+static void prvEthernetConfigureInterface(void * param);
+
+
+/*! \brief create ethernet task, for ethernet management.
+ *
+ *  \param uxPriority   Input. priority for the task, it should be low
+ *
+ */
+void vStartEthernetTask( unsigned portBASE_TYPE uxPriority )
+{
+static const gpio_map_t MACB_GPIO_MAP =
+{
+  {AVR32_MACB_MDC_0_PIN,    AVR32_MACB_MDC_0_FUNCTION   },
+  {AVR32_MACB_MDIO_0_PIN,   AVR32_MACB_MDIO_0_FUNCTION  },
+  {AVR32_MACB_RXD_0_PIN,    AVR32_MACB_RXD_0_FUNCTION   },
+  {AVR32_MACB_TXD_0_PIN,    AVR32_MACB_TXD_0_FUNCTION   },
+  {AVR32_MACB_RXD_1_PIN,    AVR32_MACB_RXD_1_FUNCTION   },
+  {AVR32_MACB_TXD_1_PIN,    AVR32_MACB_TXD_1_FUNCTION   },
+  {AVR32_MACB_TX_EN_0_PIN,  AVR32_MACB_TX_EN_0_FUNCTION },
+  {AVR32_MACB_RX_ER_0_PIN,  AVR32_MACB_RX_ER_0_FUNCTION },
+  {AVR32_MACB_RX_DV_0_PIN,  AVR32_MACB_RX_DV_0_FUNCTION },
+  {AVR32_MACB_TX_CLK_0_PIN, AVR32_MACB_TX_CLK_0_FUNCTION}
+};
+
+  // Assign GPIO to MACB
+  gpio_enable_module(MACB_GPIO_MAP, sizeof(MACB_GPIO_MAP) / sizeof(MACB_GPIO_MAP[0]));
+
+  /* Setup lwIP. */
+  prvlwIPInit();
+
+#if (HTTP_USED == 1)
+  /* Create the WEB server task.  This uses the lwIP RTOS abstraction layer.*/
+  sys_thread_new( vBasicWEBServer, ( void * ) NULL, ethWEBSERVER_PRIORITY );
+#endif
+
+#if (TFTP_USED == 1)
+  /* Create the TFTP server task.  This uses the lwIP RTOS abstraction layer.*/
+  sys_thread_new( vBasicTFTPServer, ( void * ) NULL, ethTFTPSERVER_PRIORITY );
+#endif
+
+#if (SMTP_USED == 1)
+  /* Create the SMTP Client task.  This uses the lwIP RTOS abstraction layer.*/
+  sys_thread_new( vBasicSMTPClient, ( void * ) NULL, ethSMTPCLIENT_PRIORITY );
+#endif
+
+}
+
+
+/*!
+ *  \brief start lwIP layer.
+ */
+static void prvlwIPInit( void )
+{
+	/* Initialize lwIP and its interface layer. */
+	#if LWIP_STATS
+		stats_init();
+	#endif
+
+	sys_init();
+	mem_init();
+	memp_init();
+	pbuf_init();
+	netif_init();
+	
+	/* once TCP stack has been initalized, set hw and IP parameters, initialize MACB too */
+	tcpip_init( prvEthernetConfigureInterface, NULL );
+}
+
+/*!
+ *  \brief set ethernet config 
+ */
+static void prvEthernetConfigureInterface(void * param)
+{
+struct ip_addr xIpAddr, xNetMask, xGateway;
+extern err_t ethernetif_init( struct netif *netif );
+portCHAR MacAddress[6];
+
+   /* Default MAC addr. */
+   MacAddress[0] = ETHERNET_CONF_ETHADDR0;
+   MacAddress[1] = ETHERNET_CONF_ETHADDR1;
+   MacAddress[2] = ETHERNET_CONF_ETHADDR2;
+   MacAddress[3] = ETHERNET_CONF_ETHADDR3;
+   MacAddress[4] = ETHERNET_CONF_ETHADDR4;
+   MacAddress[5] = ETHERNET_CONF_ETHADDR5;
+   
+   /* pass the MAC address to MACB module */
+   vMACBSetMACAddress( MacAddress );
+   
+   /* set MAC hardware address length to be used by lwIP */
+   MACB_if.hwaddr_len = 6;
+   
+   /* set MAC hardware address to be used by lwIP */
+   memcpy( MACB_if.hwaddr, MacAddress, MACB_if.hwaddr_len );
+   
+   /* Default ip addr. */
+   IP4_ADDR( &xIpAddr,ETHERNET_CONF_IPADDR0,ETHERNET_CONF_IPADDR1,ETHERNET_CONF_IPADDR2,ETHERNET_CONF_IPADDR3 );
+   
+   /* Default Subnet mask. */
+   IP4_ADDR( &xNetMask,ETHERNET_CONF_NET_MASK0,ETHERNET_CONF_NET_MASK1,ETHERNET_CONF_NET_MASK2,ETHERNET_CONF_NET_MASK3 );
+   
+   /* Default Gw addr. */
+   IP4_ADDR( &xGateway,ETHERNET_CONF_GATEWAY_ADDR0,ETHERNET_CONF_GATEWAY_ADDR1,ETHERNET_CONF_GATEWAY_ADDR2,ETHERNET_CONF_GATEWAY_ADDR3 );
+   
+   /* add data to netif */
+   netif_add( &MACB_if, &xIpAddr, &xNetMask, &xGateway, NULL, ethernetif_init, tcpip_input );
+   
+   /* make it the default interface */
+   netif_set_default( &MACB_if );
+   
+   /* bring it up */
+   netif_set_up( &MACB_if );
+}
+
+
+
diff --git a/20080212/Demo/lwIP_AVR32_UC3/NETWORK/ethernet.h b/20080212/Demo/lwIP_AVR32_UC3/NETWORK/ethernet.h
new file mode 100644
index 000000000..ef37e7c1e
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/NETWORK/ethernet.h
@@ -0,0 +1,57 @@
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief ethernet headers for AVR32 UC3.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ *****************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef ETHERNET_H
+#define ETHERNET_H
+
+/*! \brief create ethernet task, for ethernet management.
+ *
+ *  \param uxPriority   Input. priority for the task, it should be low
+ *
+ */
+void vStartEthernetTask( unsigned portBASE_TYPE uxPriority );
+
+
+
+#endif
+
+
diff --git a/20080212/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/IAR/errno.h b/20080212/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/IAR/errno.h
new file mode 100644
index 000000000..18eb1403b
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/IAR/errno.h
@@ -0,0 +1,63 @@
+/* errno.h standard header */
+#ifndef _ERRNO
+#define _ERRNO
+
+#ifndef _SYSTEM_BUILD
+  #pragma system_include
+#endif
+
+#ifndef _YVALS
+  #include 
+#endif
+_C_STD_BEGIN
+
+                /* ERROR CODES */
+#define EDOM    _EDOM
+#define ERANGE  _ERANGE
+#define EFPOS   _EFPOS
+#define EILSEQ  _EILSEQ
+
+               /* lwip error codes, from cygwin errno.h */
+#define EIO 5		      /* I/O error */
+#define EWOULDBLOCK 11          /* Operation would block */
+#define ENOMEM 12	      /* Not enough core */
+#define EFAULT 14	                        /* Bad address */
+#define EINVAL 22	                        /* Invalid argument */
+#define ENOSYS 88                         /* Function not implemented */
+#define ECONNRESET 104            /* Connection reset by peer */
+#define ENOBUFS 105	     /* No buffer space available */
+#define ENOPROTOOPT 109	     /* Protocol not available */
+#define ESHUTDOWN 110	     /* Can't send after socket shutdown */
+#define EADDRINUSE 112	     /* Address already in use */
+#define ECONNABORTED 113     /* Connection aborted */
+#define EHOSTUNREACH 118	     /* Host is unreachable */
+#define ENOTCONN 128	     /* Socket is not connected */
+
+#define _NERR   129   /* one more than last code */
+
+                /* DECLARATIONS */
+_C_LIB_DECL
+#if !_MULTI_THREAD || _COMPILER_TLS && !_GLOBAL_LOCALE
+  extern int _TLS_QUAL errno;
+
+#else /* !_MULTI_THREAD || _COMPILER_TLS && !_GLOBAL_LOCALE */
+  __INTRINSIC int *_Geterrno(void);
+
+  #define errno (*_Geterrno())
+#endif /* !_MULTI_THREAD || _COMPILER_TLS && !_GLOBAL_LOCALE */
+_END_C_LIB_DECL
+_C_STD_END
+#endif /* _ERRNO */
+
+#ifdef _STD_USING
+  #ifndef errno
+    using _CSTD errno;
+  #endif
+#endif /* _STD_USING */
+/*
+ * Copyright (c) 1992-2002 by P.J. Plauger.  ALL RIGHTS RESERVED.
+ * Consult your license regarding permissions and restrictions.
+V3.12:0576 */
+
+
+
diff --git a/20080212/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/arch/cc.h b/20080212/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/arch/cc.h
new file mode 100644
index 000000000..5d1c9052a
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/arch/cc.h
@@ -0,0 +1,88 @@
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief lwIP abstraction layer for AVR32 UC3.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ *****************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __CC_H__
+#define __CC_H__
+
+#include "cpu.h"
+
+typedef unsigned   char    u8_t;
+typedef signed     char    s8_t;
+typedef unsigned   short   u16_t;
+typedef signed     short   s16_t;
+typedef unsigned   long    u32_t;
+typedef signed     long    s32_t;
+typedef u32_t mem_ptr_t;
+typedef int sys_prot_t;
+
+/*! Defines for the LWIP_STATS feature. */
+#define S16_F   "d"
+#define U16_F   "d"
+#define X16_F   "d"
+#define X32_F   "d"
+#define U32_F   "d"
+#define S32_F   "d"
+
+#define LWIP_PLATFORM_DIAG(x)   
+#define LWIP_PLATFORM_ASSERT(x)   
+
+/* */
+#if __GNUC__
+#define PACK_STRUCT_BEGIN
+#elif __ICCAVR32__
+#define PACK_STRUCT_BEGIN _Pragma("pack(1)")
+#endif
+
+#if __GNUC__
+#define PACK_STRUCT_STRUCT __attribute__ ((__packed__))
+#elif __ICCAVR32__
+#define PACK_STRUCT_STRUCT
+#endif
+
+#if __GNUC__
+#define PACK_STRUCT_END
+#elif __ICCAVR32__
+#define PACK_STRUCT_END _Pragma("pack()")
+#endif
+
+#define PACK_STRUCT_FIELD(x) x
+
+#endif /* __CC_H__ */
diff --git a/20080212/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/arch/cpu.h b/20080212/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/arch/cpu.h
new file mode 100644
index 000000000..c411f9b2d
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/arch/cpu.h
@@ -0,0 +1,48 @@
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief lwIP abstraction layer for AVR32 UC3.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ *****************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef __CPU_H__
+#define __CPU_H__
+
+#define BYTE_ORDER BIG_ENDIAN
+
+#endif /* __CPU_H__ */
diff --git a/20080212/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/arch/init.h b/20080212/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/arch/init.h
new file mode 100644
index 000000000..6bf322e6c
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/arch/init.h
@@ -0,0 +1,55 @@
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief lwIP abstraction layer for AVR32 UC3.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ *****************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef __ARCH_INIT_H__
+#define __ARCH_INIT_H__
+
+#define TCPIP_INIT_DONE(arg)  tcpip_init_done(arg)
+
+void tcpip_init_done(void *);
+int wait_for_tcpip_init(void);
+
+#endif /* __ARCH_INIT_H__ */
+
+
+
+
diff --git a/20080212/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/arch/lib.h b/20080212/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/arch/lib.h
new file mode 100644
index 000000000..2ecf2afa7
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/arch/lib.h
@@ -0,0 +1,48 @@
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief lwIP abstraction layer for AVR32 UC3.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ *****************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __LIB_H__
+#define __LIB_H__
+
+#include 
+
+
+#endif /* __LIB_H__ */
diff --git a/20080212/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/arch/perf.h b/20080212/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/arch/perf.h
new file mode 100644
index 000000000..91d8f4114
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/arch/perf.h
@@ -0,0 +1,48 @@
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief lwIP abstraction layer for AVR32 UC3.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ *****************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __PERF_H__
+#define __PERF_H__
+
+#define PERF_START    /* null definition */
+#define PERF_STOP(x)  /* null definition */
+
+#endif /* __PERF_H__ */
diff --git a/20080212/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/arch/sys_arch.h b/20080212/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/arch/sys_arch.h
new file mode 100644
index 000000000..af2afc3ff
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/arch/sys_arch.h
@@ -0,0 +1,58 @@
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief lwIP abstraction layer for AVR32 UC3.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ *****************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __SYS_RTXC_H__
+#define __SYS_RTXC_H__
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "semphr.h"
+
+#define SYS_MBOX_NULL (xQueueHandle)0
+#define SYS_SEM_NULL  (xSemaphoreHandle)0
+
+typedef xSemaphoreHandle sys_sem_t;
+typedef xQueueHandle sys_mbox_t;
+typedef xTaskHandle sys_thread_t;
+
+#endif /* __SYS_RTXC_H__ */
+
diff --git a/20080212/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/ethernetif.c b/20080212/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/ethernetif.c
new file mode 100644
index 000000000..a262771f2
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/ethernetif.c
@@ -0,0 +1,380 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+/*
+ * This file is a skeleton for developing Ethernet network interface
+ * drivers for lwIP. Add code to the low_level functions and do a
+ * search-and-replace for the word "ethernetif" to replace it with
+ * something that better describes your network interface.
+ */
+
+#include "lwip/opt.h"
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/pbuf.h"
+#include "lwip/sys.h"
+#include 
+
+#include "conf_eth.h"
+
+#include "netif/etharp.h"
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "macb.h"
+
+#define netifMTU              ( 1500 )
+#define netifGUARD_BLOCK_TIME       ( 250 )
+#define IFNAME0 'e'
+#define IFNAME1 'm'
+
+
+struct ethernetif {
+  struct eth_addr *ethaddr;
+  /* Add whatever per-interface state that is needed here. */
+};
+
+static const struct eth_addr ethbroadcast = {{0xff,0xff,0xff,0xff,0xff,0xff}};
+
+/* Forward declarations. */
+void  ethernetif_input(void * );
+static err_t ethernetif_output(struct netif *netif, struct pbuf *p,
+             struct ip_addr *ipaddr);
+static struct netif *xNetIf = NULL;
+
+
+static void
+low_level_init(struct netif *netif)
+{
+//  struct ethernetif *ethernetif = netif->state;
+  unsigned portBASE_TYPE uxPriority;
+
+  /* maximum transfer unit */
+  netif->mtu = netifMTU;
+  
+  /* broadcast capability */
+  netif->flags = NETIF_FLAG_BROADCAST;
+ 
+  /* Do whatever else is needed to initialize interface. */  
+  xNetIf = netif;
+
+  /* Initialise the MACB.  This routine contains code that polls status bits.
+  If the Ethernet cable is not plugged in then this can take a considerable
+  time.  To prevent this starving lower priority tasks of processing time we
+  lower our priority prior to the call, then raise it back again once the
+  initialisation is complete. */
+  uxPriority = uxTaskPriorityGet( NULL );
+  vTaskPrioritySet( NULL, tskIDLE_PRIORITY );
+  while( xMACBInit(&AVR32_MACB) == FALSE )
+  {
+    __asm__ __volatile__ ( "nop" );
+  }
+  vTaskPrioritySet( NULL, uxPriority );
+
+  /* Create the task that handles the MACB. */
+  // xTaskCreate( ethernetif_input, ( signed portCHAR * ) "ETH_INT", netifINTERFACE_TASK_STACK_SIZE, NULL, netifINTERFACE_TASK_PRIORITY, NULL );
+  sys_thread_new( ethernetif_input, NULL, netifINTERFACE_TASK_PRIORITY );
+}
+
+/*
+ * low_level_output():
+ *
+ * Should do the actual transmission of the packet. The packet is
+ * contained in the pbuf that is passed to the function. This pbuf
+ * might be chained.
+ *
+ */
+
+static err_t
+low_level_output(struct netif *netif, struct pbuf *p)
+{
+struct pbuf *q;
+static xSemaphoreHandle xTxSemaphore = NULL;
+err_t xReturn = ERR_OK;
+
+  /* Parameter not used. */
+  ( void ) netif;
+
+  if( xTxSemaphore == NULL )
+  {
+    vSemaphoreCreateBinary( xTxSemaphore );
+  }
+
+  #if ETH_PAD_SIZE
+    pbuf_header( p, -ETH_PAD_SIZE );    /* drop the padding word */
+  #endif
+
+  /* Access to the MACB is guarded using a semaphore. */
+  if( xSemaphoreTake( xTxSemaphore, netifGUARD_BLOCK_TIME ) )
+  {
+    for( q = p; q != NULL; q = q->next )
+    {
+      /* Send the data from the pbuf to the interface, one pbuf at a
+      time. The size of the data in each pbuf is kept in the ->len
+      variable.  if q->next == NULL then this is the last pbuf in the
+      chain. */
+      if( !lMACBSend(&AVR32_MACB, q->payload, q->len, ( q->next == NULL ) ) )
+      {
+        xReturn = ~ERR_OK;
+      }
+    }
+    xSemaphoreGive( xTxSemaphore );
+  }
+  
+
+  #if ETH_PAD_SIZE
+    pbuf_header( p, ETH_PAD_SIZE );     /* reclaim the padding word */
+  #endif
+
+  #if LINK_STATS
+    lwip_stats.link.xmit++;
+  #endif /* LINK_STATS */
+
+    return xReturn;
+}
+
+/*
+ * low_level_input():
+ *
+ * Should allocate a pbuf and transfer the bytes of the incoming
+ * packet from the interface into the pbuf.
+ *
+ */
+
+static struct pbuf *
+low_level_input(struct netif *netif) {
+struct pbuf         *p = NULL;
+struct pbuf         *q;
+u16_t               len = 0;
+static xSemaphoreHandle xRxSemaphore = NULL;
+
+  /* Parameter not used. */
+  ( void ) netif;
+
+  if( xRxSemaphore == NULL )
+  {
+    vSemaphoreCreateBinary( xRxSemaphore );
+  }
+
+  /* Access to the emac is guarded using a semaphore. */
+  if( xSemaphoreTake( xRxSemaphore, netifGUARD_BLOCK_TIME ) )
+  {
+    /* Obtain the size of the packet. */
+    len = ulMACBInputLength();
+
+    if( len )
+    {
+      #if ETH_PAD_SIZE
+        len += ETH_PAD_SIZE;    /* allow room for Ethernet padding */
+      #endif
+  
+      /* We allocate a pbuf chain of pbufs from the pool. */
+      p = pbuf_alloc( PBUF_RAW, len, PBUF_POOL );
+  
+      if( p != NULL )
+      {
+        #if ETH_PAD_SIZE
+          pbuf_header( p, -ETH_PAD_SIZE );    /* drop the padding word */
+        #endif
+  
+        /* Let the driver know we are going to read a new packet. */
+        vMACBRead( NULL, 0, len );
+  
+        /* We iterate over the pbuf chain until we have read the entire
+        packet into the pbuf. */
+        for( q = p; q != NULL; q = q->next )
+        {
+          /* Read enough bytes to fill this pbuf in the chain. The
+          available data in the pbuf is given by the q->len variable. */
+          vMACBRead( q->payload, q->len, len );
+        }
+  
+        #if ETH_PAD_SIZE
+          pbuf_header( p, ETH_PAD_SIZE );     /* reclaim the padding word */
+        #endif
+        #if LINK_STATS
+          lwip_stats.link.recv++;
+        #endif /* LINK_STATS */
+      }
+      else
+      {
+        #if LINK_STATS
+          lwip_stats.link.memerr++;
+          lwip_stats.link.drop++;
+        #endif /* LINK_STATS */
+      }
+    }
+    xSemaphoreGive( xRxSemaphore );
+  }
+
+  return p;
+}
+
+/*
+ * ethernetif_output():
+ *
+ * This function is called by the TCP/IP stack when an IP packet
+ * should be sent. It calls the function called low_level_output() to
+ * do the actual transmission of the packet.
+ *
+ */
+
+static err_t
+ethernetif_output(struct netif *netif, struct pbuf *p,
+      struct ip_addr *ipaddr)
+{
+  
+ /* resolve hardware address, then send (or queue) packet */
+  return etharp_output(netif, ipaddr, p);
+ 
+}
+
+/*
+ * ethernetif_input():
+ *
+ * This function should be called when a packet is ready to be read
+ * from the interface. It uses the function low_level_input() that
+ * should handle the actual reception of bytes from the network
+ * interface.
+ *
+ */
+
+void ethernetif_input( void * pvParameters )
+{
+struct ethernetif   *ethernetif;
+struct eth_hdr      *ethhdr;
+struct pbuf         *p;
+
+  ( void ) pvParameters;
+
+  for( ;; )  {
+   
+    ethernetif = xNetIf->state;
+    do
+    {
+      ethernetif = xNetIf->state;
+
+      /* move received packet into a new pbuf */
+      p = low_level_input( xNetIf );
+
+      if( p == NULL )
+      {
+        /* No packet could be read.  Wait a for an interrupt to tell us
+        there is more data available. */
+        vMACBWaitForInput(100);
+      }
+
+    } while( p == NULL );
+
+    /* points to packet payload, which starts with an Ethernet header */
+    ethhdr = p->payload;
+  
+    #if LINK_STATS
+      lwip_stats.link.recv++;
+    #endif /* LINK_STATS */
+  
+    ethhdr = p->payload;
+  
+    switch( htons( ethhdr->type ) )
+    {
+      /* IP packet? */
+      case ETHTYPE_IP:
+        /* update ARP table */
+        etharp_ip_input( xNetIf, p );
+  
+        /* skip Ethernet header */
+        pbuf_header( p, (s16_t)-sizeof(struct eth_hdr) );
+  
+        /* pass to network layer */
+        xNetIf->input( p, xNetIf );
+        break;
+  
+      case ETHTYPE_ARP:
+        /* pass p to ARP module */
+        etharp_arp_input( xNetIf, ethernetif->ethaddr, p );
+        break;
+  
+      default:
+        pbuf_free( p );
+        p = NULL;
+        break;
+    }
+  }
+}
+
+static void
+arp_timer(void *arg)
+{
+  etharp_tmr();
+  sys_timeout(ARP_TMR_INTERVAL, arp_timer, NULL);
+}
+
+/*
+ * ethernetif_init():
+ *
+ * Should be called at the beginning of the program to set up the
+ * network interface. It calls the function low_level_init() to do the
+ * actual setup of the hardware.
+ *
+ */
+extern struct netif MACB_if;
+err_t
+ethernetif_init(struct netif *netif)
+{
+  struct ethernetif *ethernetif;
+  int i;
+    
+  ethernetif = (struct ethernetif *)mem_malloc(sizeof(struct ethernetif));
+  
+  if (ethernetif == NULL)
+  {
+    LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_init: out of memory\n"));
+    return ERR_MEM;
+  }
+  
+  netif->state = ethernetif;
+  netif->name[0] = IFNAME0;
+  netif->name[1] = IFNAME1;
+  netif->output = ethernetif_output;
+  netif->linkoutput = low_level_output;
+  
+  for(i = 0; i < 6; i++) netif->hwaddr[i] = MACB_if.hwaddr[i];
+  
+  low_level_init(netif);
+
+  etharp_init();
+
+  sys_timeout(ARP_TMR_INTERVAL, arp_timer, NULL);
+
+  return ERR_OK;
+}
+
diff --git a/20080212/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/lwip/opt.h b/20080212/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/lwip/opt.h
new file mode 100644
index 000000000..307a237a3
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/lwip/opt.h
@@ -0,0 +1,722 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_OPT_H__
+#define __LWIP_OPT_H__
+
+/* Include user defined options first */
+#include "lwipopts.h"
+#include "lwip/debug.h"
+
+/* Define default values for unconfigured parameters. */
+
+/* Platform specific locking */
+
+/*
+ * enable SYS_LIGHTWEIGHT_PROT in lwipopts.h if you want inter-task protection
+ * for certain critical regions during buffer allocation, deallocation and memory
+ * allocation and deallocation.
+ */
+#ifndef SYS_LIGHTWEIGHT_PROT
+#define SYS_LIGHTWEIGHT_PROT            0
+#endif
+
+#ifndef NO_SYS
+#define NO_SYS                          0
+#endif
+/* ---------- Memory options ---------- */
+#ifndef MEM_LIBC_MALLOC
+#define MEM_LIBC_MALLOC                 0
+#endif
+
+/* MEM_ALIGNMENT: should be set to the alignment of the CPU for which
+   lwIP is compiled. 4 byte alignment -> define MEM_ALIGNMENT to 4, 2
+   byte alignment -> define MEM_ALIGNMENT to 2. */
+
+#ifndef MEM_ALIGNMENT
+#define MEM_ALIGNMENT                   1
+#endif
+
+/* MEM_SIZE: the size of the heap memory. If the application will send
+a lot of data that needs to be copied, this should be set high. */
+#ifndef MEM_SIZE
+#define MEM_SIZE                        1600
+#endif
+
+#ifndef MEMP_SANITY_CHECK
+#define MEMP_SANITY_CHECK       0
+#endif
+
+/* MEMP_NUM_PBUF: the number of memp struct pbufs. If the application
+   sends a lot of data out of ROM (or other static memory), this
+   should be set high. */
+#ifndef MEMP_NUM_PBUF
+#define MEMP_NUM_PBUF                   16
+#endif
+
+/* Number of raw connection PCBs */
+#ifndef MEMP_NUM_RAW_PCB
+#define MEMP_NUM_RAW_PCB                4
+#endif
+
+/* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One
+   per active UDP "connection". */
+#ifndef MEMP_NUM_UDP_PCB
+#define MEMP_NUM_UDP_PCB                4
+#endif
+/* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP
+   connections. */
+#ifndef MEMP_NUM_TCP_PCB
+#define MEMP_NUM_TCP_PCB                5
+#endif
+/* MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP
+   connections. */
+#ifndef MEMP_NUM_TCP_PCB_LISTEN
+#define MEMP_NUM_TCP_PCB_LISTEN         8
+#endif
+/* MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP
+   segments. */
+#ifndef MEMP_NUM_TCP_SEG
+#define MEMP_NUM_TCP_SEG                16
+#endif
+/* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active
+   timeouts. */
+#ifndef MEMP_NUM_SYS_TIMEOUT
+#define MEMP_NUM_SYS_TIMEOUT            3
+#endif
+
+/* The following four are used only with the sequential API and can be
+   set to 0 if the application only will use the raw API. */
+/* MEMP_NUM_NETBUF: the number of struct netbufs. */
+#ifndef MEMP_NUM_NETBUF
+#define MEMP_NUM_NETBUF                 2
+#endif
+/* MEMP_NUM_NETCONN: the number of struct netconns. */
+#ifndef MEMP_NUM_NETCONN
+#define MEMP_NUM_NETCONN                4
+#endif
+/* MEMP_NUM_APIMSG: the number of struct api_msg, used for
+   communication between the TCP/IP stack and the sequential
+   programs. */
+#ifndef MEMP_NUM_API_MSG
+#define MEMP_NUM_API_MSG                8
+#endif
+/* MEMP_NUM_TCPIPMSG: the number of struct tcpip_msg, which is used
+   for sequential API communication and incoming packets. Used in
+   src/api/tcpip.c. */
+#ifndef MEMP_NUM_TCPIP_MSG
+#define MEMP_NUM_TCPIP_MSG              8
+#endif
+
+/* ---------- Pbuf options ---------- */
+/* PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */
+
+#ifndef PBUF_POOL_SIZE
+#define PBUF_POOL_SIZE                  16
+#endif
+
+/* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */
+
+#ifndef PBUF_POOL_BUFSIZE
+#define PBUF_POOL_BUFSIZE               128
+#endif
+
+/* PBUF_LINK_HLEN: the number of bytes that should be allocated for a
+   link level header. Defaults to 14 for Ethernet. */
+
+#ifndef PBUF_LINK_HLEN
+#define PBUF_LINK_HLEN                  14
+#endif
+
+
+
+/* ---------- ARP options ---------- */
+
+/** Number of active hardware address, IP address pairs cached */
+#ifndef ARP_TABLE_SIZE
+#define ARP_TABLE_SIZE                  10
+#endif
+
+/**
+ * If enabled, outgoing packets are queued during hardware address
+ * resolution.
+ *
+ * This feature has not stabilized yet. Single-packet queueing is
+ * believed to be stable, multi-packet queueing is believed to
+ * clash with the TCP segment queueing.
+ * 
+ * As multi-packet-queueing is currently disabled, enabling this
+ * _should_ work, but we need your testing feedback on lwip-users.
+ *
+ */
+#ifndef ARP_QUEUEING
+#define ARP_QUEUEING                    1
+#endif
+
+/* This option is deprecated */
+#ifdef ETHARP_QUEUE_FIRST
+#error ETHARP_QUEUE_FIRST option is deprecated. Remove it from your lwipopts.h.
+#endif
+
+/* This option is removed to comply with the ARP standard */
+#ifdef ETHARP_ALWAYS_INSERT
+#error ETHARP_ALWAYS_INSERT option is deprecated. Remove it from your lwipopts.h.
+#endif
+
+/* ---------- IP options ---------- */
+/* Define IP_FORWARD to 1 if you wish to have the ability to forward
+   IP packets across network interfaces. If you are going to run lwIP
+   on a device with only one network interface, define this to 0. */
+#ifndef IP_FORWARD
+#define IP_FORWARD                      0
+#endif
+
+/* If defined to 1, IP options are allowed (but not parsed). If
+   defined to 0, all packets with IP options are dropped. */
+#ifndef IP_OPTIONS
+#define IP_OPTIONS                      1
+#endif
+
+/** IP reassembly and segmentation. Even if they both deal with IP
+ *  fragments, note that these are orthogonal, one dealing with incoming
+ *  packets, the other with outgoing packets
+ */
+
+/** Reassemble incoming fragmented IP packets */
+#ifndef IP_REASSEMBLY
+#define IP_REASSEMBLY                   1
+#endif
+
+/** Fragment outgoing IP packets if their size exceeds MTU */
+#ifndef IP_FRAG
+#define IP_FRAG                         1
+#endif
+
+/* IP reassemly default age in seconds */
+#ifndef IP_REASS_MAXAGE
+#define IP_REASS_MAXAGE 3
+#endif
+
+/* IP reassembly buffer size (minus IP header) */
+#ifndef IP_REASS_BUFSIZE
+#define IP_REASS_BUFSIZE 5760
+#endif
+
+/* Assumed max MTU on any interface for IP frag buffer */
+#ifndef IP_FRAG_MAX_MTU
+#define IP_FRAG_MAX_MTU 1500
+#endif
+
+/** Global default value for Time To Live used by transport layers. */
+#ifndef IP_DEFAULT_TTL
+#define IP_DEFAULT_TTL                  255
+#endif
+
+/* ---------- ICMP options ---------- */
+
+#ifndef ICMP_TTL
+#define ICMP_TTL                        (IP_DEFAULT_TTL)
+#endif
+
+/* ---------- RAW options ---------- */
+
+#ifndef LWIP_RAW
+#define LWIP_RAW                        1
+#endif
+
+#ifndef RAW_TTL
+#define RAW_TTL                        (IP_DEFAULT_TTL)
+#endif
+
+/* ---------- DHCP options ---------- */
+
+#ifndef LWIP_DHCP
+#define LWIP_DHCP                       0
+#endif
+
+/* 1 if you want to do an ARP check on the offered address
+   (recommended). */
+#ifndef DHCP_DOES_ARP_CHECK
+#define DHCP_DOES_ARP_CHECK             1
+#endif
+
+/* ---------- SNMP options ---------- */
+/** @note UDP must be available for SNMP transport */
+#ifndef LWIP_SNMP
+#define LWIP_SNMP                       0
+#endif
+
+/** @note At least one request buffer is required.  */
+#ifndef SNMP_CONCURRENT_REQUESTS
+#define SNMP_CONCURRENT_REQUESTS        1
+#endif
+
+/** @note At least one trap destination is required */
+#ifndef SNMP_TRAP_DESTINATIONS
+#define SNMP_TRAP_DESTINATIONS          1
+#endif
+
+#ifndef SNMP_PRIVATE_MIB
+#define SNMP_PRIVATE_MIB                0
+#endif
+
+/* ---------- UDP options ---------- */
+#ifndef LWIP_UDP
+#define LWIP_UDP                        1
+#endif
+
+#ifndef UDP_TTL
+#define UDP_TTL                         (IP_DEFAULT_TTL)
+#endif
+
+/* ---------- TCP options ---------- */
+#ifndef LWIP_TCP
+#define LWIP_TCP                        1
+#endif
+
+#ifndef TCP_TTL
+#define TCP_TTL                         (IP_DEFAULT_TTL)
+#endif
+
+#ifndef TCP_WND
+#define TCP_WND                         2048
+#endif 
+
+#ifndef TCP_MAXRTX
+#define TCP_MAXRTX                      12
+#endif
+
+#ifndef TCP_SYNMAXRTX
+#define TCP_SYNMAXRTX                   6
+#endif
+
+
+/* Controls if TCP should queue segments that arrive out of
+   order. Define to 0 if your device is low on memory. */
+#ifndef TCP_QUEUE_OOSEQ
+#define TCP_QUEUE_OOSEQ                 1
+#endif
+
+/* TCP Maximum segment size. */
+#ifndef TCP_MSS
+#define TCP_MSS                         128 /* A *very* conservative default. */
+#endif
+
+/* TCP sender buffer space (bytes). */
+#ifndef TCP_SND_BUF
+#define TCP_SND_BUF                     256
+#endif
+
+/* TCP sender buffer space (pbufs). This must be at least = 2 *
+   TCP_SND_BUF/TCP_MSS for things to work. */
+#ifndef TCP_SND_QUEUELEN
+#define TCP_SND_QUEUELEN                4 * TCP_SND_BUF/TCP_MSS
+#endif
+
+
+/* Maximum number of retransmissions of data segments. */
+
+/* Maximum number of retransmissions of SYN segments. */
+
+/* TCP writable space (bytes). This must be less than or equal
+   to TCP_SND_BUF. It is the amount of space which must be
+   available in the tcp snd_buf for select to return writable */
+#ifndef TCP_SNDLOWAT
+#define TCP_SNDLOWAT                    TCP_SND_BUF/2
+#endif
+
+/* Support loop interface (127.0.0.1) */
+#ifndef LWIP_HAVE_LOOPIF
+#define LWIP_HAVE_LOOPIF                0
+#endif
+
+#ifndef LWIP_EVENT_API
+#define LWIP_EVENT_API                  0
+#define LWIP_CALLBACK_API               1
+#else 
+#define LWIP_EVENT_API                  1
+#define LWIP_CALLBACK_API               0
+#endif 
+
+#ifndef LWIP_COMPAT_SOCKETS
+#define LWIP_COMPAT_SOCKETS             1
+#endif
+
+
+#ifndef TCPIP_THREAD_PRIO
+#define TCPIP_THREAD_PRIO               1
+#endif
+
+#ifndef SLIPIF_THREAD_PRIO
+#define SLIPIF_THREAD_PRIO              1
+#endif
+
+#ifndef PPP_THREAD_PRIO
+#define PPP_THREAD_PRIO                 1
+#endif
+
+#ifndef DEFAULT_THREAD_PRIO
+#define DEFAULT_THREAD_PRIO             1
+#endif
+
+
+/* ---------- Socket Options ---------- */
+/* Enable SO_REUSEADDR and SO_REUSEPORT options */ 
+#ifdef SO_REUSE
+/* I removed the lot since this was an ugly hack. It broke the raw-API.
+   It also came with many ugly goto's, Christiaan Simons. */
+#error "SO_REUSE currently unavailable, this was a hack"
+#endif                                                                        
+
+
+/* ---------- Statistics options ---------- */
+#ifndef LWIP_STATS
+#define LWIP_STATS                      1
+#endif
+
+#if LWIP_STATS
+
+#ifndef LWIP_STATS_DISPLAY
+#define LWIP_STATS_DISPLAY 0
+#endif
+
+#ifndef LINK_STATS
+#define LINK_STATS  1
+#endif
+
+#ifndef IP_STATS
+#define IP_STATS    1
+#endif
+
+#ifndef IPFRAG_STATS
+#define IPFRAG_STATS    1
+#endif
+
+#ifndef ICMP_STATS
+#define ICMP_STATS  1
+#endif
+
+#ifndef UDP_STATS
+#define UDP_STATS   1
+#endif
+
+#ifndef TCP_STATS
+#define TCP_STATS   1
+#endif
+
+#ifndef MEM_STATS
+#define MEM_STATS   1
+#endif
+
+#ifndef MEMP_STATS
+#define MEMP_STATS  1
+#endif
+
+#ifndef PBUF_STATS
+#define PBUF_STATS  1
+#endif
+
+#ifndef SYS_STATS
+#define SYS_STATS   1
+#endif
+
+#ifndef RAW_STATS
+#define RAW_STATS   0
+#endif
+
+#else
+
+#define LINK_STATS  0
+#define IP_STATS    0
+#define IPFRAG_STATS    0
+#define ICMP_STATS  0
+#define UDP_STATS   0
+#define TCP_STATS   0
+#define MEM_STATS   0
+#define MEMP_STATS  0
+#define PBUF_STATS  0
+#define SYS_STATS   0
+#define RAW_STATS   0
+#define LWIP_STATS_DISPLAY  0
+
+#endif /* LWIP_STATS */
+
+/* ---------- PPP options ---------- */
+
+#ifndef PPP_SUPPORT
+#define PPP_SUPPORT                     0      /* Set for PPP */
+#endif
+
+#if PPP_SUPPORT 
+
+#define NUM_PPP                         1      /* Max PPP sessions. */
+
+
+
+#ifndef PAP_SUPPORT
+#define PAP_SUPPORT                     0      /* Set for PAP. */
+#endif
+
+#ifndef CHAP_SUPPORT
+#define CHAP_SUPPORT                    0      /* Set for CHAP. */
+#endif
+
+#define MSCHAP_SUPPORT                  0      /* Set for MSCHAP (NOT FUNCTIONAL!) */
+#define CBCP_SUPPORT                    0      /* Set for CBCP (NOT FUNCTIONAL!) */
+#define CCP_SUPPORT                     0      /* Set for CCP (NOT FUNCTIONAL!) */
+
+#ifndef VJ_SUPPORT
+#define VJ_SUPPORT                      0      /* Set for VJ header compression. */
+#endif
+
+#ifndef MD5_SUPPORT
+#define MD5_SUPPORT                     0      /* Set for MD5 (see also CHAP) */
+#endif
+
+
+/*
+ * Timeouts.
+ */
+#define FSM_DEFTIMEOUT                  6       /* Timeout time in seconds */
+#define FSM_DEFMAXTERMREQS              2       /* Maximum Terminate-Request transmissions */
+#define FSM_DEFMAXCONFREQS              10      /* Maximum Configure-Request transmissions */
+#define FSM_DEFMAXNAKLOOPS              5       /* Maximum number of nak loops */
+
+#define UPAP_DEFTIMEOUT                 6       /* Timeout (seconds) for retransmitting req */
+#define UPAP_DEFREQTIME                 30      /* Time to wait for auth-req from peer */
+
+#define CHAP_DEFTIMEOUT                 6       /* Timeout time in seconds */
+#define CHAP_DEFTRANSMITS               10      /* max # times to send challenge */
+
+
+/* Interval in seconds between keepalive echo requests, 0 to disable. */
+#if 1
+#define LCP_ECHOINTERVAL                0
+#else
+#define LCP_ECHOINTERVAL                10
+#endif
+
+/* Number of unanswered echo requests before failure. */
+#define LCP_MAXECHOFAILS                3
+
+/* Max Xmit idle time (in jiffies) before resend flag char. */
+#define PPP_MAXIDLEFLAG                 100
+
+/*
+ * Packet sizes
+ *
+ * Note - lcp shouldn't be allowed to negotiate stuff outside these
+ *    limits.  See lcp.h in the pppd directory.
+ * (XXX - these constants should simply be shared by lcp.c instead
+ *    of living in lcp.h)
+ */
+#define PPP_MTU                         1500     /* Default MTU (size of Info field) */
+#if 0
+#define PPP_MAXMTU  65535 - (PPP_HDRLEN + PPP_FCSLEN)
+#else
+#define PPP_MAXMTU                      1500 /* Largest MTU we allow */
+#endif
+#define PPP_MINMTU                      64
+#define PPP_MRU                         1500     /* default MRU = max length of info field */
+#define PPP_MAXMRU                      1500     /* Largest MRU we allow */
+#define PPP_DEFMRU                      296             /* Try for this */
+#define PPP_MINMRU                      128             /* No MRUs below this */
+
+
+#define MAXNAMELEN                      256     /* max length of hostname or name for auth */
+#define MAXSECRETLEN                    256     /* max length of password or secret */
+
+#endif /* PPP_SUPPORT */
+
+/* checksum options - set to zero for hardware checksum support */
+
+#ifndef CHECKSUM_GEN_IP
+#define CHECKSUM_GEN_IP                 1
+#endif
+ 
+#ifndef CHECKSUM_GEN_UDP
+#define CHECKSUM_GEN_UDP                1
+#endif
+ 
+#ifndef CHECKSUM_GEN_TCP
+#define CHECKSUM_GEN_TCP                1
+#endif
+ 
+#ifndef CHECKSUM_CHECK_IP
+#define CHECKSUM_CHECK_IP               1
+#endif
+ 
+#ifndef CHECKSUM_CHECK_UDP
+#define CHECKSUM_CHECK_UDP              1
+#endif
+
+#ifndef CHECKSUM_CHECK_TCP
+#define CHECKSUM_CHECK_TCP              1
+#endif
+
+/* Debugging options all default to off */
+
+#ifndef DBG_TYPES_ON
+#define DBG_TYPES_ON                    0
+#endif
+
+#ifndef ETHARP_DEBUG
+#define ETHARP_DEBUG                    DBG_OFF
+#endif
+
+#ifndef NETIF_DEBUG
+#define NETIF_DEBUG                     DBG_OFF
+#endif
+
+#ifndef PBUF_DEBUG
+#define PBUF_DEBUG                      DBG_OFF
+#endif
+
+#ifndef API_LIB_DEBUG
+#define API_LIB_DEBUG                   DBG_OFF
+#endif
+
+#ifndef API_MSG_DEBUG
+#define API_MSG_DEBUG                   DBG_OFF
+#endif
+
+#ifndef SOCKETS_DEBUG
+#define SOCKETS_DEBUG                   DBG_OFF
+#endif
+
+#ifndef ICMP_DEBUG
+#define ICMP_DEBUG                      DBG_OFF
+#endif
+
+#ifndef INET_DEBUG
+#define INET_DEBUG                      DBG_OFF
+#endif
+
+#ifndef IP_DEBUG
+#define IP_DEBUG                        DBG_OFF
+#endif
+
+#ifndef IP_REASS_DEBUG
+#define IP_REASS_DEBUG                  DBG_OFF
+#endif
+
+#ifndef RAW_DEBUG
+#define RAW_DEBUG                       DBG_OFF
+#endif
+
+#ifndef MEM_DEBUG
+#define MEM_DEBUG                       DBG_OFF
+#endif
+
+#ifndef MEMP_DEBUG
+#define MEMP_DEBUG                      DBG_OFF
+#endif
+
+#ifndef SYS_DEBUG
+#define SYS_DEBUG                       DBG_OFF
+#endif
+
+#ifndef TCP_DEBUG
+#define TCP_DEBUG                       DBG_OFF
+#endif
+
+#ifndef TCP_INPUT_DEBUG
+#define TCP_INPUT_DEBUG                 DBG_OFF
+#endif
+
+#ifndef TCP_FR_DEBUG
+#define TCP_FR_DEBUG                    DBG_OFF
+#endif
+
+#ifndef TCP_RTO_DEBUG
+#define TCP_RTO_DEBUG                   DBG_OFF
+#endif
+
+#ifndef TCP_REXMIT_DEBUG
+#define TCP_REXMIT_DEBUG                DBG_OFF
+#endif
+
+#ifndef TCP_CWND_DEBUG
+#define TCP_CWND_DEBUG                  DBG_OFF
+#endif
+
+#ifndef TCP_WND_DEBUG
+#define TCP_WND_DEBUG                   DBG_OFF
+#endif
+
+#ifndef TCP_OUTPUT_DEBUG
+#define TCP_OUTPUT_DEBUG                DBG_OFF
+#endif
+
+#ifndef TCP_RST_DEBUG
+#define TCP_RST_DEBUG                   DBG_OFF
+#endif
+
+#ifndef TCP_QLEN_DEBUG
+#define TCP_QLEN_DEBUG                  DBG_OFF
+#endif
+
+#ifndef UDP_DEBUG
+#define UDP_DEBUG                       DBG_OFF
+#endif
+
+#ifndef TCPIP_DEBUG
+#define TCPIP_DEBUG                     DBG_OFF
+#endif
+
+#ifndef PPP_DEBUG 
+#define PPP_DEBUG                       DBG_OFF
+#endif
+
+#ifndef SLIP_DEBUG 
+#define SLIP_DEBUG                      DBG_OFF
+#endif
+
+#ifndef DHCP_DEBUG 
+#define DHCP_DEBUG                      DBG_OFF
+#endif
+
+#ifndef SNMP_MSG_DEBUG 
+#define SNMP_MSG_DEBUG                  DBG_OFF
+#endif
+
+#ifndef SNMP_MIB_DEBUG 
+#define SNMP_MIB_DEBUG                  DBG_OFF
+#endif
+
+#ifndef DBG_MIN_LEVEL
+#define DBG_MIN_LEVEL                   DBG_LEVEL_OFF
+#endif
+
+#endif /* __LWIP_OPT_H__ */
+
+
+
diff --git a/20080212/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/lwipopts.h b/20080212/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/lwipopts.h
new file mode 100644
index 000000000..09f2a141c
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/lwipopts.h
@@ -0,0 +1,226 @@
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief lwIP configuration for AVR32 UC3.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ *****************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+
+#ifndef __LWIPOPTS_H__
+#define __LWIPOPTS_H__
+
+/* Include user defined options first */
+#include "conf_eth.h"
+// #include "lwip/debug.h"
+
+/* Define default values for unconfigured parameters. */
+#define LWIP_NOASSERT 1 // To suppress some errors for now (no debug output)
+
+/* These two control is reclaimer functions should be compiled
+   in. Should always be turned on (1). */
+#define MEM_RECLAIM             1
+#define MEMP_RECLAIM            1
+
+
+/* Platform specific locking */
+
+/*
+ * enable SYS_LIGHTWEIGHT_PROT in lwipopts.h if you want inter-task protection
+ * for certain critical regions during buffer allocation, deallocation and memory
+ * allocation and deallocation.
+ */
+#define SYS_LIGHTWEIGHT_PROT            1
+
+/* ---------- Memory options ---------- */
+// #define MEM_LIBC_MALLOC                 0
+
+/* MEM_ALIGNMENT: should be set to the alignment of the CPU for which
+   lwIP is compiled. 4 byte alignment -> define MEM_ALIGNMENT to 4, 2
+   byte alignment -> define MEM_ALIGNMENT to 2. */
+#define MEM_ALIGNMENT           4
+
+/* MEM_SIZE: the size of the heap memory. If the application will send
+a lot of data that needs to be copied, this should be set high. */
+#define MEM_SIZE                3 * 1024
+
+// #define MEMP_SANITY_CHECK       1
+
+/* MEMP_NUM_PBUF: the number of memp struct pbufs. If the application
+   sends a lot of data out of ROM (or other static memory), this
+   should be set high. */
+#define MEMP_NUM_PBUF           6
+
+/* Number of raw connection PCBs */
+#define MEMP_NUM_RAW_PCB                1
+
+#if (TFTP_USED == 1)
+  /* ---------- UDP options ---------- */
+  #define LWIP_UDP                1
+  #define UDP_TTL                 255
+  /* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One
+     per active UDP "connection". */
+
+  #define MEMP_NUM_UDP_PCB        1
+#else
+  /* ---------- UDP options ---------- */
+  #define LWIP_UDP                0
+  #define UDP_TTL                 0
+  /* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One
+     per active UDP "connection". */
+
+  #define MEMP_NUM_UDP_PCB        0
+#endif
+
+/* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP
+   connections. */
+#define MEMP_NUM_TCP_PCB        14
+/* MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP
+   connections. */
+#define MEMP_NUM_TCP_PCB_LISTEN 2
+/* MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP
+   segments. */
+#define MEMP_NUM_TCP_SEG        6
+/* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active
+   timeouts. */
+#define MEMP_NUM_SYS_TIMEOUT    6
+
+/* The following four are used only with the sequential API and can be
+   set to 0 if the application only will use the raw API. */
+/* MEMP_NUM_NETBUF: the number of struct netbufs. */
+#define MEMP_NUM_NETBUF         3
+/* MEMP_NUM_NETCONN: the number of struct netconns. */
+#define MEMP_NUM_NETCONN        6
+/* MEMP_NUM_APIMSG: the number of struct api_msg, used for
+   communication between the TCP/IP stack and the sequential
+   programs. */
+#define MEMP_NUM_API_MSG        4
+/* MEMP_NUM_TCPIPMSG: the number of struct tcpip_msg, which is used
+   for sequential API communication and incoming packets. Used in
+   src/api/tcpip.c. */
+#define MEMP_NUM_TCPIP_MSG      4
+
+
+/* ---------- Pbuf options ---------- */
+/* PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */
+
+#define PBUF_POOL_SIZE          6
+
+/* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */
+
+#define PBUF_POOL_BUFSIZE       500
+
+/* PBUF_LINK_HLEN: the number of bytes that should be allocated for a
+   link level header. */
+#define PBUF_LINK_HLEN          16
+
+/* ---------- TCP options ---------- */
+#define LWIP_TCP                1
+#define TCP_TTL                 255
+/* TCP receive window. */
+#define TCP_WND                 1500
+/* Controls if TCP should queue segments that arrive out of
+   order. Define to 0 if your device is low on memory. */
+#define TCP_QUEUE_OOSEQ         1
+
+/* TCP Maximum segment size. */
+#define TCP_MSS                 1500
+
+/* TCP sender buffer space (bytes). */
+#define TCP_SND_BUF             2150
+
+/* TCP sender buffer space (pbufs). This must be at least = 2 *
+   TCP_SND_BUF/TCP_MSS for things to work. */
+#define TCP_SND_QUEUELEN        6 * TCP_SND_BUF/TCP_MSS
+
+
+
+/* Maximum number of retransmissions of data segments. */
+#define TCP_MAXRTX              12
+
+/* Maximum number of retransmissions of SYN segments. */
+#define TCP_SYNMAXRTX           4
+
+/* ---------- ARP options ---------- */
+#define ARP_TABLE_SIZE 10
+#define ARP_QUEUEING 0
+
+/* ---------- IP options ---------- */
+/* Define IP_FORWARD to 1 if you wish to have the ability to forward
+   IP packets across network interfaces. If you are going to run lwIP
+   on a device with only one network interface, define this to 0. */
+#define IP_FORWARD              0
+
+/* If defined to 1, IP options are allowed (but not parsed). If
+   defined to 0, all packets with IP options are dropped. */
+#define IP_OPTIONS              1
+
+/* ---------- ICMP options ---------- */
+#define ICMP_TTL                255
+
+
+/* ---------- DHCP options ---------- */
+/* Define LWIP_DHCP to 1 if you want DHCP configuration of
+   interfaces. DHCP is not implemented in lwIP 0.5.1, however, so
+   turning this on does currently not work. */
+#define LWIP_DHCP               0
+
+/* 1 if you want to do an ARP check on the offered address
+   (recommended). */
+#define DHCP_DOES_ARP_CHECK     1
+
+#define TCPIP_THREAD_PRIO               lwipINTERFACE_TASK_PRIORITY
+
+/* ---------- Statistics options ---------- */
+#define LWIP_STATS 1
+
+#define LWIP_STATS_DISPLAY 1
+
+#if LWIP_STATS
+#define LINK_STATS 1
+#define IP_STATS   1
+#define ICMP_STATS 1
+#define UDP_STATS  1
+#define TCP_STATS  1
+#define MEM_STATS  1
+#define MEMP_STATS 1
+#define PBUF_STATS 1
+#define SYS_STATS  1
+#endif /* STATS */
+
+
+#endif /* __LWIPOPTS_H__ */
diff --git a/20080212/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/sys_arch.c b/20080212/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/sys_arch.c
new file mode 100644
index 000000000..95fc2649a
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/sys_arch.c
@@ -0,0 +1,429 @@
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief lwIP abstraction layer for AVR32 UC3.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ *****************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#include "conf_eth.h"
+
+#if (HTTP_USED == 1)
+  #include "BasicWEB.h"
+#endif
+
+#if (TFTP_USED == 1)
+  #include "BasicTFTP.h"
+#endif
+
+#if (SMTP_USED == 1)
+  #include "BasicSMTP.h"
+#endif
+
+/* lwIP includes. */
+#include "lwip/debug.h"
+#include "lwip/def.h"
+#include "lwip/sys.h"
+#include "lwip/mem.h"
+
+/* Message queue constants. */
+#define archMESG_QUEUE_LENGTH ( 6 )
+#define archPOST_BLOCK_TIME_MS  ( ( unsigned portLONG ) 10000 )
+
+struct timeoutlist 
+{
+  struct sys_timeouts timeouts;
+  xTaskHandle pid;
+};
+
+static struct timeoutlist timeoutlist[SYS_THREAD_MAX];
+static u16_t nextthread = 0;
+int intlevel = 0;
+
+extern void ethernetif_input( void * pvParameters );
+
+/*-----------------------------------------------------------------------------------*/
+//  Creates an empty mailbox.
+sys_mbox_t
+sys_mbox_new(void)
+{
+  xQueueHandle mbox;
+
+  mbox = xQueueCreate( archMESG_QUEUE_LENGTH, sizeof( void * ) );
+
+  return mbox;
+}
+
+/*-----------------------------------------------------------------------------------*/
+/*
+  Deallocates a mailbox. If there are messages still present in the
+  mailbox when the mailbox is deallocated, it is an indication of a
+  programming error in lwIP and the developer should be notified.
+*/
+void
+sys_mbox_free(sys_mbox_t mbox)
+{
+  if( uxQueueMessagesWaiting( mbox ) )
+  {
+    /* Line for breakpoint.  Should never break here! */
+    __asm__ __volatile__ ( "nop" );
+  }
+
+  vQueueDelete( mbox );
+}
+
+/*-----------------------------------------------------------------------------------*/
+//   Posts the "msg" to the mailbox.
+void
+sys_mbox_post(sys_mbox_t mbox, void *data)
+{   
+  xQueueSend( mbox, &data, ( portTickType ) ( archPOST_BLOCK_TIME_MS / portTICK_RATE_MS ) );
+}
+
+
+/*-----------------------------------------------------------------------------------*/
+/*
+  Blocks the thread until a message arrives in the mailbox, but does
+  not block the thread longer than "timeout" milliseconds (similar to
+  the sys_arch_sem_wait() function). The "msg" argument is a result
+  parameter that is set by the function (i.e., by doing "*msg =
+  ptr"). The "msg" parameter maybe NULL to indicate that the message
+  should be dropped.
+
+  The return values are the same as for the sys_arch_sem_wait() function:
+  Number of milliseconds spent waiting or SYS_ARCH_TIMEOUT if there was a
+  timeout.
+
+  Note that a function with a similar name, sys_mbox_fetch(), is
+  implemented by lwIP. 
+*/
+u32_t sys_arch_mbox_fetch(sys_mbox_t mbox, void **msg, u32_t timeout)
+{
+void *dummyptr;
+portTickType StartTime, EndTime, Elapsed;
+
+  StartTime = xTaskGetTickCount();
+
+  if( msg == NULL )
+  {
+    msg = &dummyptr;
+  }
+  
+  if( timeout != 0 )
+  {
+    if(pdTRUE == xQueueReceive( mbox, &(*msg), timeout ) )
+    {
+      EndTime = xTaskGetTickCount();
+      Elapsed = EndTime - StartTime;
+      if( Elapsed == 0 )
+      {
+        Elapsed = 1;
+      }
+      return ( Elapsed );
+    }
+    else // timed out blocking for message
+    {
+      *msg = NULL;
+      return SYS_ARCH_TIMEOUT;
+    }
+  }
+  else // block forever for a message.
+  {
+    while( pdTRUE != xQueueReceive( mbox, &(*msg), 10000 ) ) // time is arbitrary
+    {
+      ;
+    }
+    EndTime = xTaskGetTickCount();
+    Elapsed = EndTime - StartTime;
+    if( Elapsed == 0 )
+    {
+      Elapsed = 1;
+    }
+    return ( Elapsed ); // return time blocked TBD test
+  }
+}
+
+/*-----------------------------------------------------------------------------------*/
+//  Creates and returns a new semaphore. The "count" argument specifies
+//  the initial state of the semaphore. TBD finish and test
+sys_sem_t
+sys_sem_new(u8_t count)
+{
+  xSemaphoreHandle  xSemaphore = NULL;
+
+  portENTER_CRITICAL();
+  vSemaphoreCreateBinary( xSemaphore );
+  if( xSemaphore == NULL )
+  {
+    return NULL;  // TBD need assert
+  }
+  if(count == 0)  // Means we want the sem to be unavailable at init state.
+  {
+    xSemaphoreTake(xSemaphore,1);
+  }
+  portEXIT_CRITICAL();
+
+  return xSemaphore;
+}
+
+/*-----------------------------------------------------------------------------------*/
+/*
+  Blocks the thread while waiting for the semaphore to be
+  signaled. If the "timeout" argument is non-zero, the thread should
+  only be blocked for the specified time (measured in
+  milliseconds).
+
+  If the timeout argument is non-zero, the return value is the number of
+  milliseconds spent waiting for the semaphore to be signaled. If the
+  semaphore wasn't signaled within the specified time, the return value is
+  SYS_ARCH_TIMEOUT. If the thread didn't have to wait for the semaphore
+  (i.e., it was already signaled), the function may return zero.
+
+  Notice that lwIP implements a function with a similar name,
+  sys_sem_wait(), that uses the sys_arch_sem_wait() function.
+*/
+u32_t
+sys_arch_sem_wait(sys_sem_t sem, u32_t timeout)
+{
+portTickType StartTime, EndTime, Elapsed;
+
+  StartTime = xTaskGetTickCount();
+
+  if( timeout != 0)
+  {
+    if( xSemaphoreTake( sem, timeout ) == pdTRUE )
+    {
+      EndTime = xTaskGetTickCount();
+      Elapsed = EndTime - StartTime;
+      if( Elapsed == 0 )
+      {
+        Elapsed = 1;
+      }
+      return (Elapsed); // return time blocked TBD test
+    }
+    else
+    {
+      return SYS_ARCH_TIMEOUT;
+    }
+  }
+  else // must block without a timeout
+  {
+    while( xSemaphoreTake( sem, 10000 ) != pdTRUE )
+    {
+      ;
+    }
+    EndTime = xTaskGetTickCount();
+    Elapsed = EndTime - StartTime;
+    if( Elapsed == 0 )
+    {
+      Elapsed = 1;
+    }
+
+    return ( Elapsed ); // return time blocked
+  
+  }
+}
+
+/*-----------------------------------------------------------------------------------*/
+// Signals a semaphore
+void
+sys_sem_signal(sys_sem_t sem)
+{
+  xSemaphoreGive( sem );
+}
+
+/*-----------------------------------------------------------------------------------*/
+// Deallocates a semaphore
+void
+sys_sem_free(sys_sem_t sem)
+{
+  vQueueDelete( sem );
+}
+
+/*-----------------------------------------------------------------------------------*/
+// Initialize sys arch
+void
+sys_init(void)
+{
+
+  int i;
+
+  // Initialize the the per-thread sys_timeouts structures
+  // make sure there are no valid pids in the list
+  for(i = 0; i < SYS_THREAD_MAX; i++)
+  {
+    timeoutlist[i].pid = 0;
+    timeoutlist[i].timeouts.next = NULL;
+  }
+
+  // keep track of how many threads have been created
+  nextthread = 0;
+}
+
+/*-----------------------------------------------------------------------------------*/
+/*
+  Returns a pointer to the per-thread sys_timeouts structure. In lwIP,
+  each thread has a list of timeouts which is represented as a linked
+  list of sys_timeout structures. The sys_timeouts structure holds a
+  pointer to a linked list of timeouts. This function is called by
+  the lwIP timeout scheduler and must not return a NULL value. 
+
+  In a single threaded sys_arch implementation, this function will
+  simply return a pointer to a global sys_timeouts variable stored in
+  the sys_arch module.
+*/
+struct sys_timeouts *
+sys_arch_timeouts(void)
+{
+int i;
+xTaskHandle pid;
+struct timeoutlist *tl;  
+
+  pid = xTaskGetCurrentTaskHandle( );
+
+  for(i = 0; i < nextthread; i++)
+  {
+    tl = &(timeoutlist[i]);
+    if(tl->pid == pid)
+    {
+      return &(tl->timeouts);
+    }
+  }
+
+
+  // If we're here, this means the scheduler gave the focus to the task as it was
+  // being created(because of a higher priority). Since timeoutlist[] update is
+  // done just after the task creation, the array is not up-to-date.
+  // => the last array entry must be the one of the current task.
+  return( &( timeoutlist[nextthread].timeouts ) );
+/*
+  // Error
+  return NULL;
+*/
+}
+
+/*-----------------------------------------------------------------------------------*/
+/*-----------------------------------------------------------------------------------*/
+// TBD 
+/*-----------------------------------------------------------------------------------*/
+/*
+  Starts a new thread with priority "prio" that will begin its execution in the
+  function "thread()". The "arg" argument will be passed as an argument to the
+  thread() function. The id of the new thread is returned. Both the id and
+  the priority are system dependent.
+*/
+sys_thread_t sys_thread_new(void (* thread)(void *arg), void *arg, int prio)
+{
+xTaskHandle CreatedTask;
+int result = pdFAIL;
+static int iCall = 0;
+
+  if( thread == ethernetif_input )
+  {
+    result = xTaskCreate( thread, ( signed portCHAR * ) "ETHINT", netifINTERFACE_TASK_STACK_SIZE, arg, prio, &CreatedTask );
+  }
+  else if( iCall == 0 )
+  {
+    /* The first time this is called we are creating the lwIP handler. */
+    result = xTaskCreate( thread, ( signed portCHAR * ) "lwIP", lwipINTERFACE_STACK_SIZE, arg, prio, &CreatedTask );
+    iCall++;
+  }
+#if (HTTP_USED == 1)
+  else if (thread == vBasicWEBServer)
+  {
+    result = xTaskCreate( thread, ( signed portCHAR * ) "WEB", lwipBASIC_WEB_SERVER_STACK_SIZE, arg, prio, &CreatedTask );
+  }
+#endif
+#if (TFTP_USED == 1)
+  else if (thread == vBasicTFTPServer)
+  {
+    result = xTaskCreate( thread, ( signed portCHAR * ) "TFTP", lwipBASIC_TFTP_SERVER_STACK_SIZE, arg, prio, &CreatedTask );
+  }
+#endif
+#if (SMTP_USED == 1)
+  else if (thread == vBasicSMTPClient)
+  {
+    result = xTaskCreate( thread, ( signed portCHAR * ) "SMTP", lwipBASIC_SMTP_CLIENT_STACK_SIZE, arg, prio, &CreatedTask );
+  }
+#endif
+
+
+  // For each task created, store the task handle (pid) in the timers array.
+  // This scheme doesn't allow for threads to be deleted
+  timeoutlist[nextthread++].pid = CreatedTask;
+
+  if(result == pdPASS)
+  {
+    return CreatedTask;
+  }
+  else
+  {
+    return NULL;
+  }
+}
+
+/*
+  This optional function does a "fast" critical region protection and returns
+  the previous protection level. This function is only called during very short
+  critical regions. An embedded system which supports ISR-based drivers might
+  want to implement this function by disabling interrupts. Task-based systems
+  might want to implement this by using a mutex or disabling tasking. This
+  function should support recursive calls from the same task or interrupt. In
+  other words, sys_arch_protect() could be called while already protected. In
+  that case the return value indicates that it is already protected.
+
+  sys_arch_protect() is only required if your port is supporting an operating
+  system.
+*/
+sys_prot_t sys_arch_protect(void)
+{
+  vPortEnterCritical();
+  return 1;
+}
+
+/*
+  This optional function does a "fast" set of critical region protection to the
+  value specified by pval. See the documentation for sys_arch_protect() for
+  more information. This function is only required if your port is supporting
+  an operating system.
+*/
+void sys_arch_unprotect(sys_prot_t pval)
+{ 
+  ( void ) pval;
+  vPortExitCritical();
+}
+
diff --git a/20080212/Demo/lwIP_AVR32_UC3/PARTEST/ParTest.c b/20080212/Demo/lwIP_AVR32_UC3/PARTEST/ParTest.c
new file mode 100644
index 000000000..a2f1d1d3b
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/PARTEST/ParTest.c
@@ -0,0 +1,112 @@
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief FreeRTOS Led Driver example for AVR32 UC3.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ *****************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#include 
+#include "FreeRTOS.h"
+#include "task.h"
+#include "partest.h"
+
+
+/*-----------------------------------------------------------
+ * Simple parallel port IO routines.
+ *-----------------------------------------------------------*/
+
+#define partstALL_OUTPUTS_OFF     ( ( unsigned portCHAR ) 0x00 )
+#define partstMAX_OUTPUT_LED      ( ( unsigned portCHAR ) 8 )
+
+static volatile unsigned portCHAR ucCurrentOutputValue = partstALL_OUTPUTS_OFF; /*lint !e956 File scope parameters okay here. */
+
+/*-----------------------------------------------------------*/
+
+void vParTestInitialise( void )
+{
+	LED_Display(partstALL_OUTPUTS_OFF); /* Start with all LEDs off. */
+}
+/*-----------------------------------------------------------*/
+
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
+{
+unsigned portCHAR ucBit;
+
+	if( uxLED >= partstMAX_OUTPUT_LED )
+	{
+		return;
+	}
+
+	ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED;
+
+	vTaskSuspendAll();
+	{
+		if( xValue == pdTRUE )
+		{
+		  ucCurrentOutputValue |= ucBit;
+		}
+		else
+		{
+		  ucCurrentOutputValue &= ~ucBit;
+		}
+
+		LED_Display(ucCurrentOutputValue);
+	}
+	xTaskResumeAll();
+}
+/*-----------------------------------------------------------*/
+
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
+{
+	unsigned portCHAR ucBit;
+
+	if( uxLED >= partstMAX_OUTPUT_LED )
+	{
+		return;
+	}
+
+	ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED;
+
+	vTaskSuspendAll();
+	{
+		ucCurrentOutputValue ^= ucBit;
+		LED_Display(ucCurrentOutputValue);
+	}
+	xTaskResumeAll();
+}
+
diff --git a/20080212/Demo/lwIP_AVR32_UC3/SERIAL/serial.c b/20080212/Demo/lwIP_AVR32_UC3/SERIAL/serial.c
new file mode 100644
index 000000000..fe4f70646
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/SERIAL/serial.c
@@ -0,0 +1,365 @@
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief FreeRTOS serial port for AVR32 UC3.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ *****************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/*
+  BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR USART0.
+*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "queue.h"
+#include "task.h"
+
+/* Demo application includes. */
+#include "serial.h"
+#include 
+#include "board.h"
+#include "gpio.h"
+
+/*-----------------------------------------------------------*/
+
+/* Constants to setup and access the USART. */
+#define serINVALID_COMPORT_HANDLER        ( ( xComPortHandle ) 0 )
+#define serINVALID_QUEUE                  ( ( xQueueHandle ) 0 )
+#define serHANDLE                         ( ( xComPortHandle ) 1 )
+#define serNO_BLOCK                       ( ( portTickType ) 0 )
+
+/*-----------------------------------------------------------*/
+
+/* Queues used to hold received characters, and characters waiting to be
+transmitted. */
+static xQueueHandle xRxedChars;
+static xQueueHandle xCharsForTx;
+
+/*-----------------------------------------------------------*/
+
+/* Forward declaration. */
+static void vprvSerialCreateQueues( unsigned portBASE_TYPE uxQueueLength,
+        xQueueHandle *pxRxedChars,
+        xQueueHandle *pxCharsForTx );
+
+/*-----------------------------------------------------------*/
+
+#if __GNUC__
+__attribute__((__noinline__))
+#elif __ICCAVR32__
+#pragma optimize = no_inline
+#endif
+static portBASE_TYPE prvUSART0_ISR_NonNakedBehaviour( void )
+{
+  /* Now we can declare the local variables. */
+  signed portCHAR     cChar;
+  portBASE_TYPE     xTaskWokenByTx = pdFALSE, xTaskWokenByRx = pdFALSE;
+  unsigned portLONG     ulStatus;
+  volatile avr32_usart_t  *usart0 = &AVR32_USART0;
+  portBASE_TYPE retstatus;
+
+  /* What caused the interrupt? */
+  ulStatus = usart0->csr & usart0->imr;
+
+  if (ulStatus & AVR32_USART_CSR_TXRDY_MASK)
+  {
+    /* The interrupt was caused by the THR becoming empty.  Are there any
+       more characters to transmit? */
+    /* Because FreeRTOS is not supposed to run with nested interrupts, put all OS
+      calls in a critical section . */
+    portENTER_CRITICAL();
+    retstatus = xQueueReceiveFromISR(xCharsForTx, &cChar, &xTaskWokenByTx);
+    portEXIT_CRITICAL();
+    if (retstatus == pdTRUE)
+    {
+      /* A character was retrieved from the queue so can be sent to the
+         THR now. */
+      usart0->thr = cChar;
+    }
+    else
+    {
+      /* Queue empty, nothing to send so turn off the Tx interrupt. */
+      usart0->idr = AVR32_USART_IDR_TXRDY_MASK;
+    }
+  }
+
+  if (ulStatus & AVR32_USART_CSR_RXRDY_MASK)
+  {
+    /* The interrupt was caused by the receiver getting data. */
+    cChar = usart0->rhr; //TODO
+
+    /* Because FreeRTOS is not supposed to run with nested interrupts, put all OS
+      calls in a critical section . */
+    portENTER_CRITICAL();
+    retstatus = xQueueSendFromISR(xRxedChars, &cChar, pdFALSE);
+    portEXIT_CRITICAL();
+    if (retstatus)
+    {
+      xTaskWokenByRx = pdTRUE;
+    }
+  }
+
+  /* The return value will be used by portEXIT_SWITCHING_ISR() to know if it
+  should perform a vTaskSwitchContext(). */
+  return ( xTaskWokenByTx || xTaskWokenByRx );
+}
+
+
+/*
+ * USART0 interrupt service routine.
+ */
+#if __GNUC__
+__attribute__((__naked__))
+#elif __ICCAVR32__
+#pragma shadow_registers = full   // Naked.
+#endif
+static void vUSART0_ISR( void )
+{
+
+ /* This ISR can cause a context switch, so the first statement must be a
+  call to the portENTER_SWITCHING_ISR() macro.  This must be BEFORE any
+  variable declarations. */
+  portENTER_SWITCHING_ISR();
+  prvUSART0_ISR_NonNakedBehaviour();
+ /* Exit the ISR.  If a task was woken by either a character being received
+  or transmitted then a context switch will occur. */
+  portEXIT_SWITCHING_ISR();
+}
+/*-----------------------------------------------------------*/
+
+
+
+/*
+ * Init the serial port for the Minimal implementation.
+ */
+xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
+{
+  static const gpio_map_t USART0_GPIO_MAP =
+  {
+    { AVR32_USART0_RXD_0_PIN, AVR32_USART0_RXD_0_FUNCTION },
+    { AVR32_USART0_TXD_0_PIN, AVR32_USART0_TXD_0_FUNCTION }
+  };
+
+  xComPortHandle    xReturn = serHANDLE;
+  volatile avr32_usart_t  *usart0 = &AVR32_USART0;
+  int                           cd; /* USART0 Clock Divider. */
+
+  /* Create the rx and tx queues. */
+  vprvSerialCreateQueues( uxQueueLength, &xRxedChars, &xCharsForTx );
+
+  /* Configure USART0. */
+  if( ( xRxedChars != serINVALID_QUEUE ) &&
+      ( xCharsForTx != serINVALID_QUEUE ) &&
+      ( ulWantedBaud != ( unsigned portLONG ) 0 ) )
+  {
+    portENTER_CRITICAL();
+    {
+      /**
+       ** Reset USART0.
+       **/
+      /* Disable all USART0 interrupt sources to begin... */
+      usart0->idr = 0xFFFFFFFF;
+
+      /* Reset mode and other registers that could cause unpredictable
+         behaviour after reset */
+      usart0->mr = 0; /* Reset Mode register. */
+      usart0->rtor = 0; /* Reset Receiver Time-out register. */
+      usart0->ttgr = 0; /* Reset Transmitter Timeguard register. */
+
+      /* Shutdown RX and TX, reset status bits, reset iterations in CSR, reset NACK
+         and turn off DTR and RTS */
+      usart0->cr = AVR32_USART_CR_RSTRX_MASK   |
+                   AVR32_USART_CR_RSTTX_MASK   |
+                   AVR32_USART_CR_RXDIS_MASK   |
+                   AVR32_USART_CR_TXDIS_MASK   |
+                   AVR32_USART_CR_RSTSTA_MASK  |
+                   AVR32_USART_CR_RSTIT_MASK   |
+                   AVR32_USART_CR_RSTNACK_MASK |
+                   AVR32_USART_CR_DTRDIS_MASK  |
+                   AVR32_USART_CR_RTSDIS_MASK;
+
+      /**
+       ** Configure USART0.
+       **/
+      /* Enable USART0 RXD & TXD pins. */
+      gpio_enable_module( USART0_GPIO_MAP, sizeof( USART0_GPIO_MAP ) / sizeof( USART0_GPIO_MAP[0] ) );
+
+      /* Set the USART0 baudrate to be as close as possible to the wanted baudrate. */
+      /*
+       *             ** BAUDRATE CALCULATION **
+       *
+       *                 Selected Clock                       Selected Clock
+       *     baudrate = ----------------   or     baudrate = ----------------
+       *                    16 x CD                              8 x CD
+       *
+       *       (with 16x oversampling)              (with 8x oversampling)
+       */
+      if ( ulWantedBaud < (configCPU_CLOCK_HZ/16)  ){
+        /* Use 8x oversampling */
+        usart0->mr |= (1<brgr = (cd << AVR32_USART_BRGR_CD_OFFSET);
+      } else {
+        /* Use 16x oversampling */
+        usart0->mr &= ~(1< 65535) {
+          /* Baudrate is too low */
+          return serINVALID_COMPORT_HANDLER;
+        }
+      }
+      usart0->brgr = (cd << AVR32_USART_BRGR_CD_OFFSET);
+
+      /* Set the USART0 Mode register: Mode=Normal(0), Clk selection=MCK(0),
+         CHRL=8,  SYNC=0(asynchronous), PAR=None, NBSTOP=1, CHMODE=0, MSBF=0,
+         MODE9=0, CKLO=0, OVER(previously done when setting the baudrate),
+         other fields not used in this mode. */
+      usart0->mr |= ((8-5) << AVR32_USART_MR_CHRL_OFFSET  ) |
+                    (   4  << AVR32_USART_MR_PAR_OFFSET   ) |
+                    (   1  << AVR32_USART_MR_NBSTOP_OFFSET);
+
+      /* Write the Transmit Timeguard Register */
+      usart0->ttgr = 0;
+
+      // Register the USART0 interrupt handler to the interrupt controller and
+      // enable the USART0 interrupt.
+      INTC_register_interrupt((__int_handler)&vUSART0_ISR, AVR32_USART0_IRQ, INT1);
+
+      /* Enable USART0 interrupt sources (but not Tx for now)... */
+      usart0->ier = AVR32_USART_IER_RXRDY_MASK;
+
+      /* Enable receiver and transmitter... */
+      usart0->cr |= AVR32_USART_CR_TXEN_MASK | AVR32_USART_CR_RXEN_MASK;
+    }
+    portEXIT_CRITICAL();
+  }
+  else
+  {
+    xReturn = serINVALID_COMPORT_HANDLER;
+  }
+
+  return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )
+{
+  /* The port handle is not required as this driver only supports UART0. */
+  ( void ) pxPort;
+
+  /* Get the next character from the buffer.  Return false if no characters
+  are available, or arrive before xBlockTime expires. */
+  if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
+  {
+    return pdTRUE;
+  }
+  else
+  {
+    return pdFALSE;
+  }
+}
+/*-----------------------------------------------------------*/
+
+void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength )
+{
+signed portCHAR *pxNext;
+
+  /* NOTE: This implementation does not handle the queue being full as no
+  block time is used! */
+
+  /* The port handle is not required as this driver only supports UART0. */
+  ( void ) pxPort;
+
+  /* Send each character in the string, one at a time. */
+  pxNext = ( signed portCHAR * ) pcString;
+  while( *pxNext )
+  {
+    xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );
+    pxNext++;
+  }
+}
+/*-----------------------------------------------------------*/
+
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )
+{
+volatile avr32_usart_t  *usart0 = &AVR32_USART0;
+
+  /* Place the character in the queue of characters to be transmitted. */
+  if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )
+  {
+    return pdFAIL;
+  }
+
+  /* Turn on the Tx interrupt so the ISR will remove the character from the
+  queue and send it.   This does not need to be in a critical section as
+  if the interrupt has already removed the character the next interrupt
+  will simply turn off the Tx interrupt again. */
+  usart0->ier = (1 << AVR32_USART_IER_TXRDY_OFFSET);
+
+  return pdPASS;
+}
+/*-----------------------------------------------------------*/
+
+void vSerialClose( xComPortHandle xPort )
+{
+  /* Not supported as not required by the demo application. */
+}
+/*-----------------------------------------------------------*/
+
+/*###########################################################*/
+
+/*
+ * Create the rx and tx queues.
+ */
+static void vprvSerialCreateQueues(  unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars, xQueueHandle *pxCharsForTx )
+{
+  /* Create the queues used to hold Rx and Tx characters. */
+  xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
+  xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
+
+  /* Pass back a reference to the queues so the serial API file can
+  post/receive characters. */
+  *pxRxedChars = xRxedChars;
+  *pxCharsForTx = xCharsForTx;
+}
+/*-----------------------------------------------------------*/
diff --git a/20080212/Demo/lwIP_AVR32_UC3/SERVICES/USB/CLASS/DFU/EXAMPLES/ISP/BOOT/trampoline.S b/20080212/Demo/lwIP_AVR32_UC3/SERVICES/USB/CLASS/DFU/EXAMPLES/ISP/BOOT/trampoline.S
new file mode 100644
index 000000000..8c4651659
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/SERVICES/USB/CLASS/DFU/EXAMPLES/ISP/BOOT/trampoline.S
@@ -0,0 +1,72 @@
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief AVR32 UC3 ISP trampoline.
+ *
+ * In order to be able to program a project with both BatchISP and JTAGICE mkII
+ * without having to take the general-purpose fuses into consideration, add this
+ * file to the project and change the program entry point to _trampoline.
+ *
+ * The pre-programmed ISP will be erased if JTAGICE mkII is used.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  All AVR32UC devices can be used.
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#include "../conf_isp.h"
+
+
+//! @{
+//! \verbatim
+
+
+  // This must be linked @ 0x80000000 if it is to be run upon reset.
+  .section  .reset, "ax", @progbits
+
+
+  .global _trampoline
+  .type _trampoline, @function
+_trampoline:
+  // Jump to program start.
+  rjmp    program_start
+
+  .org  PROGRAM_START_OFFSET
+program_start:
+  // Jump to the C runtime startup routine.
+  lda.w   pc, _stext
+
+
+//! \endverbatim
+//! @}
diff --git a/20080212/Demo/lwIP_AVR32_UC3/SERVICES/USB/CLASS/DFU/EXAMPLES/ISP/BOOT/trampoline.s82 b/20080212/Demo/lwIP_AVR32_UC3/SERVICES/USB/CLASS/DFU/EXAMPLES/ISP/BOOT/trampoline.s82
new file mode 100644
index 000000000..b9e03b143
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/SERVICES/USB/CLASS/DFU/EXAMPLES/ISP/BOOT/trampoline.s82
@@ -0,0 +1,91 @@
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief AVR32 UC3 ISP trampoline.
+ *
+ * In order to be able to program a project with both BatchISP and JTAGICE mkII
+ * without having to take the general-purpose fuses into consideration, add this
+ * file to the project and change the program entry point to __trampoline.
+ *
+ * The pre-programmed ISP will be erased if JTAGICE mkII is used.
+ *
+ * - Compiler:           IAR EWAVR32
+ * - Supported devices:  All AVR32UC devices can be used.
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#include "../conf_isp.h"
+
+
+//! @{
+//! \verbatim
+
+
+  RSEG  SSTACK:DATA:NOROOT(2)
+
+
+  // This must be linked @ 0x80000000 if it is to be run upon reset.
+  RSEG  RESET:CODE:NOROOT(1)
+
+
+  PUBLIC  __trampoline
+__trampoline:
+  // Jump to program start.
+  rjmp    program_start
+
+  ORG PROGRAM_START_OFFSET
+program_start:
+  // Initialize the stack pointer.
+  lddpc   sp, ??SPS
+  // Jump to the C runtime startup routine.
+  lddpc   pc, ??cmain
+
+
+// Constant data area.
+
+  ALIGN 2
+
+??SPS:
+  DC32  SFE(SSTACK) & ~3
+
+  EXTERN  ?main
+??cmain:
+  DC32  ?main
+
+
+  END
+
+
+//! \endverbatim
+//! @}
diff --git a/20080212/Demo/lwIP_AVR32_UC3/SERVICES/USB/CLASS/DFU/EXAMPLES/ISP/conf_isp.h b/20080212/Demo/lwIP_AVR32_UC3/SERVICES/USB/CLASS/DFU/EXAMPLES/ISP/conf_isp.h
new file mode 100644
index 000000000..05fd4dcf7
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/SERVICES/USB/CLASS/DFU/EXAMPLES/ISP/conf_isp.h
@@ -0,0 +1,119 @@
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file ******************************************************************
+ *
+ * \brief ISP configuration file.
+ *
+ * This file contains the possible external configuration of the ISP.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices with a USB module can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ***************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef _CONF_ISP_H_
+#define _CONF_ISP_H_
+
+#include 
+#include "compiler.h"
+
+
+//_____ D E F I N I T I O N S ______________________________________________
+
+#define PRODUCT_MANUFACTURER_ID       0x58
+#define PRODUCT_FAMILY_ID             0x20
+
+#define ISP_VERSION                   0x00
+#define ISP_ID0                       0x00
+#define ISP_ID1                       0x00
+
+#define ISP_GPFB_FORCE                31
+#define ISP_GPFB_FORCE_MASK           0x80000000
+#define ISP_GPFB_FORCE_OFFSET         31
+#define ISP_GPFB_FORCE_SIZE           1
+
+#define ISP_GPFB_IO_COND_EN           30
+#define ISP_GPFB_IO_COND_EN_MASK      0x40000000
+#define ISP_GPFB_IO_COND_EN_OFFSET    30
+#define ISP_GPFB_IO_COND_EN_SIZE      1
+
+#define ISP_GPFB_BOD_EN               29
+#define ISP_GPFB_BOD_EN_MASK          0x20000000
+#define ISP_GPFB_BOD_EN_OFFSET        29
+#define ISP_GPFB_BOD_EN_SIZE          1
+
+#define ISP_CFG                       (*(volatile U32 *)ISP_CFG_ADDRESS)
+#define ISP_CFG_ADDRESS               (AVR32_FLASHC_USER_PAGE_ADDRESS + ISP_CFG_OFFSET)
+#define ISP_CFG_OFFSET                0x000001FC
+#define ISP_CFG_SIZE                  4
+
+#define ISP_CFG_BOOT_KEY              17
+#define ISP_CFG_BOOT_KEY_MASK         0xFFFE0000
+#define ISP_CFG_BOOT_KEY_OFFSET       17
+#define ISP_CFG_BOOT_KEY_SIZE         15
+#define ISP_CFG_BOOT_KEY_VALUE        0x494F
+
+#define ISP_CFG_IO_COND_LEVEL         16
+#define ISP_CFG_IO_COND_LEVEL_MASK    0x00010000
+#define ISP_CFG_IO_COND_LEVEL_OFFSET  16
+#define ISP_CFG_IO_COND_LEVEL_SIZE    1
+
+#define ISP_CFG_IO_COND_PIN           8
+#define ISP_CFG_IO_COND_PIN_MASK      0x0000FF00
+#define ISP_CFG_IO_COND_PIN_OFFSET    8
+#define ISP_CFG_IO_COND_PIN_SIZE      8
+
+#define ISP_CFG_CRC8                  0
+#define ISP_CFG_CRC8_MASK             0x000000FF
+#define ISP_CFG_CRC8_OFFSET           0
+#define ISP_CFG_CRC8_SIZE             8
+#define ISP_CFG_CRC8_POLYNOMIAL       0x107
+
+#define ISP_KEY                       (*(volatile U32 *)ISP_KEY_ADDRESS)
+#define ISP_KEY_ADDRESS               (AVR32_SRAM_ADDRESS + ISP_KEY_OFFSET)
+#define ISP_KEY_OFFSET                0x00000000
+#define ISP_KEY_SIZE                  4
+#define ISP_KEY_VALUE                 ('I' << 24 | 'S' << 16 | 'P' << 8 | 'K')
+
+#ifndef ISP_OSC
+  #define ISP_OSC                     0
+#endif
+
+#define DFU_FRAME_LENGTH              2048
+
+#define PROGRAM_START_ADDRESS         (AVR32_FLASH_ADDRESS + PROGRAM_START_OFFSET)
+#define PROGRAM_START_OFFSET          0x00002000
+
+
+#endif  // _CONF_ISP_H_
diff --git a/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/0128/GCC/link_uc3a0128.lds b/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/0128/GCC/link_uc3a0128.lds
new file mode 100644
index 000000000..29c4eb51d
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/0128/GCC/link_uc3a0128.lds
@@ -0,0 +1,263 @@
+/******************************************************************************
+ * AVR32 AT32UC3A0128 GNU LD script file.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  AVR32 AT32UC3A0128
+ *
+ * - author              Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+
+OUTPUT_ARCH(avr32:uc)
+
+ENTRY(_start)
+
+MEMORY
+{
+  FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00020000
+  INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x00007FFC
+  USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200
+  FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 0x00000200
+}
+
+PHDRS
+{
+  FLASH PT_LOAD;
+  INTRAM PT_NULL;
+  USERPAGE PT_LOAD;
+  FACTORYPAGE PT_LOAD;
+}
+
+SECTIONS
+{
+  /* If this heap size is selected, all the INTRAM space from the end of the
+     data area to the beginning of the stack will be allocated for the heap. */
+  __max_heap_size__ = -1;
+
+  /* Use a default heap size if heap size was not defined. */
+  __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__;
+
+  /* Use a default stack size if stack size was not defined. */
+  __stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 4K;
+
+  /* Read-only sections, merged into text segment: */
+  PROVIDE (__executable_start = 0x80000000); . = 0x80000000;
+  .interp         : { *(.interp) } >FLASH AT>FLASH :FLASH
+  .reset : {  *(.reset) } >FLASH AT>FLASH :FLASH
+  .hash           : { *(.hash) } >FLASH AT>FLASH :FLASH
+  .dynsym         : { *(.dynsym) } >FLASH AT>FLASH :FLASH
+  .dynstr         : { *(.dynstr) } >FLASH AT>FLASH :FLASH
+  .gnu.version    : { *(.gnu.version) } >FLASH AT>FLASH :FLASH
+  .gnu.version_d  : { *(.gnu.version_d) } >FLASH AT>FLASH :FLASH
+  .gnu.version_r  : { *(.gnu.version_r) } >FLASH AT>FLASH :FLASH
+  .rel.init       : { *(.rel.init) } >FLASH AT>FLASH :FLASH
+  .rela.init      : { *(.rela.init) } >FLASH AT>FLASH :FLASH
+  .rel.text       : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH
+  .rela.text      : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH
+  .rel.fini       : { *(.rel.fini) } >FLASH AT>FLASH :FLASH
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+  .rel.rodata     : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
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+  .rel.data       : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH
+  .rela.data      : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH
+  .rel.tdata	  : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH
+  .rela.tdata	  : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH
+  .rel.tbss	  : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH
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+  .rel.dtors      : { *(.rel.dtors) } >FLASH AT>FLASH :FLASH
+  .rela.dtors     : { *(.rela.dtors) } >FLASH AT>FLASH :FLASH
+  .rel.got        : { *(.rel.got) } >FLASH AT>FLASH :FLASH
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+  .rel.bss        : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH
+  .rela.bss       : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH
+  .rel.plt        : { *(.rel.plt) } >FLASH AT>FLASH :FLASH
+  .rela.plt       : { *(.rela.plt) } >FLASH AT>FLASH :FLASH
+  .init           :
+  {
+    KEEP (*(.init))
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  .plt            : { *(.plt) } >FLASH AT>FLASH :FLASH
+  .text           :
+  {
+    *(.text .stub .text.* .gnu.linkonce.t.*)
+    KEEP (*(.text.*personality*))
+    /* .gnu.warning sections are handled specially by elf32.em.  */
+    *(.gnu.warning)
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  .fini           :
+  {
+    KEEP (*(.fini))
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
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+  .eh_frame_hdr : { *(.eh_frame_hdr) } >FLASH AT>FLASH :FLASH
+  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH :FLASH
+  .gcc_except_table   : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH :FLASH
+  .lalign	: { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH :FLASH
+  . = ORIGIN(INTRAM);
+  .dalign	: { . = ALIGN(8); PROVIDE(_data = .); } >INTRAM AT>INTRAM :INTRAM
+  /* Exception handling  */
+  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) } >INTRAM AT>FLASH :FLASH
+  .gcc_except_table   : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >INTRAM AT>FLASH :FLASH
+  /* Thread Local Storage sections  */
+  .tdata	  : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >INTRAM AT>FLASH :FLASH
+  .tbss		  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >INTRAM AT>FLASH :FLASH
+  /* Ensure the __preinit_array_start label is properly aligned.  We
+     could instead move the label definition inside the section, but
+     the linker would then create the section even if it turns out to
+     be empty, which isn't pretty.  */
+  PROVIDE (__preinit_array_start = ALIGN(32 / 8));
+  .preinit_array     : { KEEP (*(.preinit_array)) } >INTRAM AT>FLASH :FLASH
+  PROVIDE (__preinit_array_end = .);
+  PROVIDE (__init_array_start = .);
+  .init_array     : { KEEP (*(.init_array)) } >INTRAM AT>FLASH :FLASH
+  PROVIDE (__init_array_end = .);
+  PROVIDE (__fini_array_start = .);
+  .fini_array     : { KEEP (*(.fini_array)) } >INTRAM AT>FLASH :FLASH
+  PROVIDE (__fini_array_end = .);
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin*.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  } >INTRAM AT>FLASH :FLASH
+  .dtors          :
+  {
+    KEEP (*crtbegin*.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  } >INTRAM AT>FLASH :FLASH
+  .jcr            : { KEEP (*(.jcr)) } >INTRAM AT>FLASH :FLASH
+  .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >INTRAM AT>FLASH :FLASH
+  .dynamic        : { *(.dynamic) } >INTRAM AT>FLASH :FLASH
+  .got            : { *(.got.plt) *(.got) } >INTRAM AT>FLASH :FLASH
+  .data           :
+  {
+    *(.data .data.* .gnu.linkonce.d.*)
+    KEEP (*(.gnu.linkonce.d.*personality*))
+    SORT(CONSTRUCTORS)
+  } >INTRAM AT>FLASH :FLASH
+  .data1          : { *(.data1) } >INTRAM AT>FLASH :FLASH
+  .balign	: { . = ALIGN(8); _edata = .; } >INTRAM AT>FLASH :FLASH
+  _edata = .;
+  PROVIDE (edata = .);
+  __bss_start = .;
+  .bss            :
+  {
+    *(.dynbss)
+    *(.bss .bss.* .gnu.linkonce.b.*)
+    *(COMMON)
+    /* Align here to ensure that the .bss section occupies space up to
+       _end.  Align after .bss to ensure correct alignment even if the
+       .bss section disappears because there are no input sections.  */
+    . = ALIGN(8);
+  } >INTRAM AT>INTRAM :INTRAM
+  . = ALIGN(8);
+  _end = .;
+  PROVIDE (end = .);
+  __heap_start__ = ALIGN(8);
+  .heap           :
+  {
+    *(.heap)
+    . = (__heap_size__ == __max_heap_size__) ?
+        ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ - ABSOLUTE(.) :
+        __heap_size__;
+  } >INTRAM AT>INTRAM :INTRAM
+  __heap_end__ = .;
+  /* Stabs debugging sections.  */
+  .stab          0 : { *(.stab) }
+  .stabstr       0 : { *(.stabstr) }
+  .stab.excl     0 : { *(.stab.excl) }
+  .stab.exclstr  0 : { *(.stab.exclstr) }
+  .stab.index    0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  .comment       0 : { *(.comment) }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  .stack         ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ :
+  {
+    _stack = .;
+    *(.stack)
+    . = __stack_size__;
+    _estack = .;
+  } >INTRAM AT>INTRAM :INTRAM
+  .userpage       : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE :USERPAGE
+  .factorypage    : { *(.factorypage .factorypage.*) } >FACTORYPAGE AT>FACTORYPAGE :FACTORYPAGE
+  /DISCARD/ : { *(.note.GNU-stack) }
+}
diff --git a/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/0128/IAR/lnkuc3a0128.xcl b/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/0128/IAR/lnkuc3a0128.xcl
new file mode 100644
index 000000000..3f42ec322
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/0128/IAR/lnkuc3a0128.xcl
@@ -0,0 +1,138 @@
+/******************************************************************************
+ * AVR32 AT32UC3A0128 XLINK command file for AVR32 IAR C/C++ Compiler.
+ *
+ * The assumed memory layout is the one of the AT32UC3A0128:
+ *
+ *   Start       Stop        Name     Type
+ *   ----------  ----------  -----    --------------
+ *   0x00000000  0x00007FFF  SRAM     RAM
+ *   0x80000000  0x8001FFFF  FLASH    FLASH
+ *
+ * Usage:  xlink  your_file(s)  -f xcl-file  libraries
+ *
+ * - Compiler:           IAR EWAVR32
+ * - Supported devices:  AVR32 AT32UC3A0128
+ *
+ * - author              Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/************************************************************************/
+/*      The following segments are defined in this link file:           */
+/*                                                                      */
+/*      Code segments                                                   */
+/*      CODE32    -- Program code used by __code32 functions.           */
+/*      RESET     -- Reset code.                                        */
+/*      EVSEG     -- Exception vector handlers.                         */
+/*                                                                      */
+/*      Constant segments                                               */
+/*      INITTAB   -- Segment initializer table.                         */
+/*      DIFUNCT   -- Dynamic initialization vector used by C++.         */
+/*      SWITCH    -- Switch tables.                                     */
+/*      ACTAB     -- Table of pointers to acall functions.              */
+/*                                                                      */
+/*      DATA21_ID -- Initialization data for DATA21_I.                  */
+/*      DATA32_ID -- Initialization data for DATA32_I.                  */
+/*      DATA32_C  -- Constant __data32 data.                            */
+/*                                                                      */
+/*      CHECKSUM  -- Checksum segment.                                  */
+/*                                                                      */
+/*      Data segments                                                   */
+/*      DATA21_I  -- Initialized __data21 data with non-zero            */
+/*                   initial value.                                     */
+/*      DATA32_I  -- Initialized __data32 data with non-zero            */
+/*                   initial value.                                     */
+/*      DATA21_Z  -- Initialized __data21 data with zero initial value. */
+/*      DATA32_Z  -- Initialized __data32 data with zero initial value. */
+/*      DATA21_N  -- Non-initialized __data21.                          */
+/*      DATA32_N  -- Non-initialized __data32.                          */
+/*      SSTACK    -- The system stack.                                  */
+/*      CSTACK    -- The application stack.                             */
+/*      HEAP      -- The heap used by malloc and free.                  */
+/*                                                                      */
+/************************************************************************/
+
+/************************************************************************/
+/*      Define CPU                                                      */
+/************************************************************************/
+
+-cavr32
+
+// Declare the IPR0 memory location
+-DIPR0=FFFF0800
+
+/************************************************************************/
+/*      Reset code is located at address 0x80000000 and up.             */
+/************************************************************************/
+
+-Z(CODE)RESET=80000000-8001FFFF
+
+/************************************************************************/
+/*      The exception handler code is located at address 0x80000000     */
+/*      and up. Make sure that the exception table gets properly        */
+/*      allocated. By using the special -Z@ allocation primitive, the   */
+/*      placement is guaranteed to be at _EVBASE and onwards.           */
+/************************************************************************/
+
+-Z@(CODE)EVTAB=80004000-8001FFFF
+-Z@(CODE)EV100=80004100-8001FFFF
+-P(CODE)EVSEG=80004000-8001FFFF
+
+/************************************************************************/
+/*      Allocate code and const segments.                               */
+/************************************************************************/
+
+-P(CODE)CODE32=80000000-8001FFFF
+-P(CONST)DATA32_C=80000000-8001FFFF
+
+// Initializers
+-Z(CONST)INITTAB,DIFUNCT=80000000-8001FFFF
+-Z(CONST)CHECKSUM,SWITCH=80000000-8001FFFF
+-Z(CONST)DATA21_ID,DATA32_ID=80000000-8001FFFF
+
+-Z(CONST)ACTAB,HTAB=80000000-8001FFFF
+
+/************************************************************************/
+/*      Allocate the read/write segments that are mapped to RAM.        */
+/************************************************************************/
+
+-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-00007FFF
+-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-00007FFF
+-Z(DATA)TRACEBUFFER=00000004-00007FFF
+
+-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-00007FFF
+-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-00007FFF
+-Z(DATA)HEAP+_HEAP_SIZE=00000004-00007FFF
+
+/************************************************************************/
+/*      End of File                                                     */
+/************************************************************************/
diff --git a/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/0256/GCC/link_uc3a0256.lds b/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/0256/GCC/link_uc3a0256.lds
new file mode 100644
index 000000000..6369fd426
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/0256/GCC/link_uc3a0256.lds
@@ -0,0 +1,263 @@
+/******************************************************************************
+ * AVR32 AT32UC3A0256 GNU LD script file.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  AVR32 AT32UC3A0256
+ *
+ * - author              Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+
+OUTPUT_ARCH(avr32:uc)
+
+ENTRY(_start)
+
+MEMORY
+{
+  FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00040000
+  INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x0000FFFC
+  USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200
+  FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 0x00000200
+}
+
+PHDRS
+{
+  FLASH PT_LOAD;
+  INTRAM PT_NULL;
+  USERPAGE PT_LOAD;
+  FACTORYPAGE PT_LOAD;
+}
+
+SECTIONS
+{
+  /* If this heap size is selected, all the INTRAM space from the end of the
+     data area to the beginning of the stack will be allocated for the heap. */
+  __max_heap_size__ = -1;
+
+  /* Use a default heap size if heap size was not defined. */
+  __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__;
+
+  /* Use a default stack size if stack size was not defined. */
+  __stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 4K;
+
+  /* Read-only sections, merged into text segment: */
+  PROVIDE (__executable_start = 0x80000000); . = 0x80000000;
+  .interp         : { *(.interp) } >FLASH AT>FLASH :FLASH
+  .reset : {  *(.reset) } >FLASH AT>FLASH :FLASH
+  .hash           : { *(.hash) } >FLASH AT>FLASH :FLASH
+  .dynsym         : { *(.dynsym) } >FLASH AT>FLASH :FLASH
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+  .gnu.version    : { *(.gnu.version) } >FLASH AT>FLASH :FLASH
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+  .gnu.version_r  : { *(.gnu.version_r) } >FLASH AT>FLASH :FLASH
+  .rel.init       : { *(.rel.init) } >FLASH AT>FLASH :FLASH
+  .rela.init      : { *(.rela.init) } >FLASH AT>FLASH :FLASH
+  .rel.text       : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH
+  .rela.text      : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH
+  .rel.fini       : { *(.rel.fini) } >FLASH AT>FLASH :FLASH
+  .rela.fini      : { *(.rela.fini) } >FLASH AT>FLASH :FLASH
+  .rel.rodata     : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
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+  .rel.data.rel.ro   : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH
+  .rela.data.rel.ro   : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH
+  .rel.data       : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH
+  .rela.data      : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH
+  .rel.tdata	  : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH
+  .rela.tdata	  : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH
+  .rel.tbss	  : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH
+  .rela.tbss	  : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH
+  .rel.ctors      : { *(.rel.ctors) } >FLASH AT>FLASH :FLASH
+  .rela.ctors     : { *(.rela.ctors) } >FLASH AT>FLASH :FLASH
+  .rel.dtors      : { *(.rel.dtors) } >FLASH AT>FLASH :FLASH
+  .rela.dtors     : { *(.rela.dtors) } >FLASH AT>FLASH :FLASH
+  .rel.got        : { *(.rel.got) } >FLASH AT>FLASH :FLASH
+  .rela.got       : { *(.rela.got) } >FLASH AT>FLASH :FLASH
+  .rel.bss        : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH
+  .rela.bss       : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH
+  .rel.plt        : { *(.rel.plt) } >FLASH AT>FLASH :FLASH
+  .rela.plt       : { *(.rela.plt) } >FLASH AT>FLASH :FLASH
+  .init           :
+  {
+    KEEP (*(.init))
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  .plt            : { *(.plt) } >FLASH AT>FLASH :FLASH
+  .text           :
+  {
+    *(.text .stub .text.* .gnu.linkonce.t.*)
+    KEEP (*(.text.*personality*))
+    /* .gnu.warning sections are handled specially by elf32.em.  */
+    *(.gnu.warning)
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  .fini           :
+  {
+    KEEP (*(.fini))
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
+  .rodata1        : { *(.rodata1) } >FLASH AT>FLASH :FLASH
+  .eh_frame_hdr : { *(.eh_frame_hdr) } >FLASH AT>FLASH :FLASH
+  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH :FLASH
+  .gcc_except_table   : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH :FLASH
+  .lalign	: { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH :FLASH
+  . = ORIGIN(INTRAM);
+  .dalign	: { . = ALIGN(8); PROVIDE(_data = .); } >INTRAM AT>INTRAM :INTRAM
+  /* Exception handling  */
+  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) } >INTRAM AT>FLASH :FLASH
+  .gcc_except_table   : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >INTRAM AT>FLASH :FLASH
+  /* Thread Local Storage sections  */
+  .tdata	  : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >INTRAM AT>FLASH :FLASH
+  .tbss		  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >INTRAM AT>FLASH :FLASH
+  /* Ensure the __preinit_array_start label is properly aligned.  We
+     could instead move the label definition inside the section, but
+     the linker would then create the section even if it turns out to
+     be empty, which isn't pretty.  */
+  PROVIDE (__preinit_array_start = ALIGN(32 / 8));
+  .preinit_array     : { KEEP (*(.preinit_array)) } >INTRAM AT>FLASH :FLASH
+  PROVIDE (__preinit_array_end = .);
+  PROVIDE (__init_array_start = .);
+  .init_array     : { KEEP (*(.init_array)) } >INTRAM AT>FLASH :FLASH
+  PROVIDE (__init_array_end = .);
+  PROVIDE (__fini_array_start = .);
+  .fini_array     : { KEEP (*(.fini_array)) } >INTRAM AT>FLASH :FLASH
+  PROVIDE (__fini_array_end = .);
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin*.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  } >INTRAM AT>FLASH :FLASH
+  .dtors          :
+  {
+    KEEP (*crtbegin*.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  } >INTRAM AT>FLASH :FLASH
+  .jcr            : { KEEP (*(.jcr)) } >INTRAM AT>FLASH :FLASH
+  .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >INTRAM AT>FLASH :FLASH
+  .dynamic        : { *(.dynamic) } >INTRAM AT>FLASH :FLASH
+  .got            : { *(.got.plt) *(.got) } >INTRAM AT>FLASH :FLASH
+  .data           :
+  {
+    *(.data .data.* .gnu.linkonce.d.*)
+    KEEP (*(.gnu.linkonce.d.*personality*))
+    SORT(CONSTRUCTORS)
+  } >INTRAM AT>FLASH :FLASH
+  .data1          : { *(.data1) } >INTRAM AT>FLASH :FLASH
+  .balign	: { . = ALIGN(8); _edata = .; } >INTRAM AT>FLASH :FLASH
+  _edata = .;
+  PROVIDE (edata = .);
+  __bss_start = .;
+  .bss            :
+  {
+    *(.dynbss)
+    *(.bss .bss.* .gnu.linkonce.b.*)
+    *(COMMON)
+    /* Align here to ensure that the .bss section occupies space up to
+       _end.  Align after .bss to ensure correct alignment even if the
+       .bss section disappears because there are no input sections.  */
+    . = ALIGN(8);
+  } >INTRAM AT>INTRAM :INTRAM
+  . = ALIGN(8);
+  _end = .;
+  PROVIDE (end = .);
+  __heap_start__ = ALIGN(8);
+  .heap           :
+  {
+    *(.heap)
+    . = (__heap_size__ == __max_heap_size__) ?
+        ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ - ABSOLUTE(.) :
+        __heap_size__;
+  } >INTRAM AT>INTRAM :INTRAM
+  __heap_end__ = .;
+  /* Stabs debugging sections.  */
+  .stab          0 : { *(.stab) }
+  .stabstr       0 : { *(.stabstr) }
+  .stab.excl     0 : { *(.stab.excl) }
+  .stab.exclstr  0 : { *(.stab.exclstr) }
+  .stab.index    0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  .comment       0 : { *(.comment) }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  .stack         ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ :
+  {
+    _stack = .;
+    *(.stack)
+    . = __stack_size__;
+    _estack = .;
+  } >INTRAM AT>INTRAM :INTRAM
+  .userpage       : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE :USERPAGE
+  .factorypage    : { *(.factorypage .factorypage.*) } >FACTORYPAGE AT>FACTORYPAGE :FACTORYPAGE
+  /DISCARD/ : { *(.note.GNU-stack) }
+}
diff --git a/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/0256/IAR/lnkuc3a0256.xcl b/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/0256/IAR/lnkuc3a0256.xcl
new file mode 100644
index 000000000..d037025d6
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/0256/IAR/lnkuc3a0256.xcl
@@ -0,0 +1,138 @@
+/******************************************************************************
+ * AVR32 AT32UC3A0256 XLINK command file for AVR32 IAR C/C++ Compiler.
+ *
+ * The assumed memory layout is the one of the AT32UC3A0256:
+ *
+ *   Start       Stop        Name     Type
+ *   ----------  ----------  -----    --------------
+ *   0x00000000  0x0000FFFF  SRAM     RAM
+ *   0x80000000  0x8003FFFF  FLASH    FLASH
+ *
+ * Usage:  xlink  your_file(s)  -f xcl-file  libraries
+ *
+ * - Compiler:           IAR EWAVR32
+ * - Supported devices:  AVR32 AT32UC3A0256
+ *
+ * - author              Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/************************************************************************/
+/*      The following segments are defined in this link file:           */
+/*                                                                      */
+/*      Code segments                                                   */
+/*      CODE32    -- Program code used by __code32 functions.           */
+/*      RESET     -- Reset code.                                        */
+/*      EVSEG     -- Exception vector handlers.                         */
+/*                                                                      */
+/*      Constant segments                                               */
+/*      INITTAB   -- Segment initializer table.                         */
+/*      DIFUNCT   -- Dynamic initialization vector used by C++.         */
+/*      SWITCH    -- Switch tables.                                     */
+/*      ACTAB     -- Table of pointers to acall functions.              */
+/*                                                                      */
+/*      DATA21_ID -- Initialization data for DATA21_I.                  */
+/*      DATA32_ID -- Initialization data for DATA32_I.                  */
+/*      DATA32_C  -- Constant __data32 data.                            */
+/*                                                                      */
+/*      CHECKSUM  -- Checksum segment.                                  */
+/*                                                                      */
+/*      Data segments                                                   */
+/*      DATA21_I  -- Initialized __data21 data with non-zero            */
+/*                   initial value.                                     */
+/*      DATA32_I  -- Initialized __data32 data with non-zero            */
+/*                   initial value.                                     */
+/*      DATA21_Z  -- Initialized __data21 data with zero initial value. */
+/*      DATA32_Z  -- Initialized __data32 data with zero initial value. */
+/*      DATA21_N  -- Non-initialized __data21.                          */
+/*      DATA32_N  -- Non-initialized __data32.                          */
+/*      SSTACK    -- The system stack.                                  */
+/*      CSTACK    -- The application stack.                             */
+/*      HEAP      -- The heap used by malloc and free.                  */
+/*                                                                      */
+/************************************************************************/
+
+/************************************************************************/
+/*      Define CPU                                                      */
+/************************************************************************/
+
+-cavr32
+
+// Declare the IPR0 memory location
+-DIPR0=FFFF0800
+
+/************************************************************************/
+/*      Reset code is located at address 0x80000000 and up.             */
+/************************************************************************/
+
+-Z(CODE)RESET=80000000-8003FFFF
+
+/************************************************************************/
+/*      The exception handler code is located at address 0x80000000     */
+/*      and up. Make sure that the exception table gets properly        */
+/*      allocated. By using the special -Z@ allocation primitive, the   */
+/*      placement is guaranteed to be at _EVBASE and onwards.           */
+/************************************************************************/
+
+-Z@(CODE)EVTAB=80004000-8003FFFF
+-Z@(CODE)EV100=80004100-8003FFFF
+-P(CODE)EVSEG=80004000-8003FFFF
+
+/************************************************************************/
+/*      Allocate code and const segments.                               */
+/************************************************************************/
+
+-P(CODE)CODE32=80000000-8003FFFF
+-P(CONST)DATA32_C=80000000-8003FFFF
+
+// Initializers
+-Z(CONST)INITTAB,DIFUNCT=80000000-8003FFFF
+-Z(CONST)CHECKSUM,SWITCH=80000000-8003FFFF
+-Z(CONST)DATA21_ID,DATA32_ID=80000000-8003FFFF
+
+-Z(CONST)ACTAB,HTAB=80000000-8003FFFF
+
+/************************************************************************/
+/*      Allocate the read/write segments that are mapped to RAM.        */
+/************************************************************************/
+
+-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-0000FFFF
+-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-0000FFFF
+-Z(DATA)TRACEBUFFER=00000004-0000FFFF
+
+-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-0000FFFF
+-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-0000FFFF
+-Z(DATA)HEAP+_HEAP_SIZE=00000004-0000FFFF
+
+/************************************************************************/
+/*      End of File                                                     */
+/************************************************************************/
diff --git a/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/0512/GCC/link_uc3a0512.lds b/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/0512/GCC/link_uc3a0512.lds
new file mode 100644
index 000000000..d89138cb5
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/0512/GCC/link_uc3a0512.lds
@@ -0,0 +1,263 @@
+/******************************************************************************
+ * AVR32 AT32UC3A0512 GNU LD script file.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  AVR32 AT32UC3A0512
+ *
+ * - author              Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+
+OUTPUT_ARCH(avr32:uc)
+
+ENTRY(_start)
+
+MEMORY
+{
+  FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00080000
+  INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x0000FFFC
+  USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200
+  FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 0x00000200
+}
+
+PHDRS
+{
+  FLASH PT_LOAD;
+  INTRAM PT_NULL;
+  USERPAGE PT_LOAD;
+  FACTORYPAGE PT_LOAD;
+}
+
+SECTIONS
+{
+  /* If this heap size is selected, all the INTRAM space from the end of the
+     data area to the beginning of the stack will be allocated for the heap. */
+  __max_heap_size__ = -1;
+
+  /* Use a default heap size if heap size was not defined. */
+  __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__;
+
+  /* Use a default stack size if stack size was not defined. */
+  __stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 4K;
+
+  /* Read-only sections, merged into text segment: */
+  PROVIDE (__executable_start = 0x80000000); . = 0x80000000;
+  .interp         : { *(.interp) } >FLASH AT>FLASH :FLASH
+  .reset : {  *(.reset) } >FLASH AT>FLASH :FLASH
+  .hash           : { *(.hash) } >FLASH AT>FLASH :FLASH
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+  .gnu.version    : { *(.gnu.version) } >FLASH AT>FLASH :FLASH
+  .gnu.version_d  : { *(.gnu.version_d) } >FLASH AT>FLASH :FLASH
+  .gnu.version_r  : { *(.gnu.version_r) } >FLASH AT>FLASH :FLASH
+  .rel.init       : { *(.rel.init) } >FLASH AT>FLASH :FLASH
+  .rela.init      : { *(.rela.init) } >FLASH AT>FLASH :FLASH
+  .rel.text       : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH
+  .rela.text      : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH
+  .rel.fini       : { *(.rel.fini) } >FLASH AT>FLASH :FLASH
+  .rela.fini      : { *(.rela.fini) } >FLASH AT>FLASH :FLASH
+  .rel.rodata     : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
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+  .rel.data.rel.ro   : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH
+  .rela.data.rel.ro   : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH
+  .rel.data       : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH
+  .rela.data      : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH
+  .rel.tdata	  : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH
+  .rela.tdata	  : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH
+  .rel.tbss	  : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH
+  .rela.tbss	  : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH
+  .rel.ctors      : { *(.rel.ctors) } >FLASH AT>FLASH :FLASH
+  .rela.ctors     : { *(.rela.ctors) } >FLASH AT>FLASH :FLASH
+  .rel.dtors      : { *(.rel.dtors) } >FLASH AT>FLASH :FLASH
+  .rela.dtors     : { *(.rela.dtors) } >FLASH AT>FLASH :FLASH
+  .rel.got        : { *(.rel.got) } >FLASH AT>FLASH :FLASH
+  .rela.got       : { *(.rela.got) } >FLASH AT>FLASH :FLASH
+  .rel.bss        : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH
+  .rela.bss       : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH
+  .rel.plt        : { *(.rel.plt) } >FLASH AT>FLASH :FLASH
+  .rela.plt       : { *(.rela.plt) } >FLASH AT>FLASH :FLASH
+  .init           :
+  {
+    KEEP (*(.init))
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  .plt            : { *(.plt) } >FLASH AT>FLASH :FLASH
+  .text           :
+  {
+    *(.text .stub .text.* .gnu.linkonce.t.*)
+    KEEP (*(.text.*personality*))
+    /* .gnu.warning sections are handled specially by elf32.em.  */
+    *(.gnu.warning)
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  .fini           :
+  {
+    KEEP (*(.fini))
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
+  .rodata1        : { *(.rodata1) } >FLASH AT>FLASH :FLASH
+  .eh_frame_hdr : { *(.eh_frame_hdr) } >FLASH AT>FLASH :FLASH
+  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH :FLASH
+  .gcc_except_table   : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH :FLASH
+  .lalign	: { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH :FLASH
+  . = ORIGIN(INTRAM);
+  .dalign	: { . = ALIGN(8); PROVIDE(_data = .); } >INTRAM AT>INTRAM :INTRAM
+  /* Exception handling  */
+  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) } >INTRAM AT>FLASH :FLASH
+  .gcc_except_table   : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >INTRAM AT>FLASH :FLASH
+  /* Thread Local Storage sections  */
+  .tdata	  : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >INTRAM AT>FLASH :FLASH
+  .tbss		  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >INTRAM AT>FLASH :FLASH
+  /* Ensure the __preinit_array_start label is properly aligned.  We
+     could instead move the label definition inside the section, but
+     the linker would then create the section even if it turns out to
+     be empty, which isn't pretty.  */
+  PROVIDE (__preinit_array_start = ALIGN(32 / 8));
+  .preinit_array     : { KEEP (*(.preinit_array)) } >INTRAM AT>FLASH :FLASH
+  PROVIDE (__preinit_array_end = .);
+  PROVIDE (__init_array_start = .);
+  .init_array     : { KEEP (*(.init_array)) } >INTRAM AT>FLASH :FLASH
+  PROVIDE (__init_array_end = .);
+  PROVIDE (__fini_array_start = .);
+  .fini_array     : { KEEP (*(.fini_array)) } >INTRAM AT>FLASH :FLASH
+  PROVIDE (__fini_array_end = .);
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin*.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  } >INTRAM AT>FLASH :FLASH
+  .dtors          :
+  {
+    KEEP (*crtbegin*.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  } >INTRAM AT>FLASH :FLASH
+  .jcr            : { KEEP (*(.jcr)) } >INTRAM AT>FLASH :FLASH
+  .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >INTRAM AT>FLASH :FLASH
+  .dynamic        : { *(.dynamic) } >INTRAM AT>FLASH :FLASH
+  .got            : { *(.got.plt) *(.got) } >INTRAM AT>FLASH :FLASH
+  .data           :
+  {
+    *(.data .data.* .gnu.linkonce.d.*)
+    KEEP (*(.gnu.linkonce.d.*personality*))
+    SORT(CONSTRUCTORS)
+  } >INTRAM AT>FLASH :FLASH
+  .data1          : { *(.data1) } >INTRAM AT>FLASH :FLASH
+  .balign	: { . = ALIGN(8); _edata = .; } >INTRAM AT>FLASH :FLASH
+  _edata = .;
+  PROVIDE (edata = .);
+  __bss_start = .;
+  .bss            :
+  {
+    *(.dynbss)
+    *(.bss .bss.* .gnu.linkonce.b.*)
+    *(COMMON)
+    /* Align here to ensure that the .bss section occupies space up to
+       _end.  Align after .bss to ensure correct alignment even if the
+       .bss section disappears because there are no input sections.  */
+    . = ALIGN(8);
+  } >INTRAM AT>INTRAM :INTRAM
+  . = ALIGN(8);
+  _end = .;
+  PROVIDE (end = .);
+  __heap_start__ = ALIGN(8);
+  .heap           :
+  {
+    *(.heap)
+    . = (__heap_size__ == __max_heap_size__) ?
+        ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ - ABSOLUTE(.) :
+        __heap_size__;
+  } >INTRAM AT>INTRAM :INTRAM
+  __heap_end__ = .;
+  /* Stabs debugging sections.  */
+  .stab          0 : { *(.stab) }
+  .stabstr       0 : { *(.stabstr) }
+  .stab.excl     0 : { *(.stab.excl) }
+  .stab.exclstr  0 : { *(.stab.exclstr) }
+  .stab.index    0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  .comment       0 : { *(.comment) }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  .stack         ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ :
+  {
+    _stack = .;
+    *(.stack)
+    . = __stack_size__;
+    _estack = .;
+  } >INTRAM AT>INTRAM :INTRAM
+  .userpage       : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE :USERPAGE
+  .factorypage    : { *(.factorypage .factorypage.*) } >FACTORYPAGE AT>FACTORYPAGE :FACTORYPAGE
+  /DISCARD/ : { *(.note.GNU-stack) }
+}
diff --git a/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/0512/IAR/lnkuc3a0512.xcl b/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/0512/IAR/lnkuc3a0512.xcl
new file mode 100644
index 000000000..d6173e786
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/0512/IAR/lnkuc3a0512.xcl
@@ -0,0 +1,138 @@
+/******************************************************************************
+ * AVR32 AT32UC3A0512 XLINK command file for AVR32 IAR C/C++ Compiler.
+ *
+ * The assumed memory layout is the one of the AT32UC3A0512:
+ *
+ *   Start       Stop        Name     Type
+ *   ----------  ----------  -----    --------------
+ *   0x00000000  0x0000FFFF  SRAM     RAM
+ *   0x80000000  0x8007FFFF  FLASH    FLASH
+ *
+ * Usage:  xlink  your_file(s)  -f xcl-file  libraries
+ *
+ * - Compiler:           IAR EWAVR32
+ * - Supported devices:  AVR32 AT32UC3A0512
+ *
+ * - author              Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/************************************************************************/
+/*      The following segments are defined in this link file:           */
+/*                                                                      */
+/*      Code segments                                                   */
+/*      CODE32    -- Program code used by __code32 functions.           */
+/*      RESET     -- Reset code.                                        */
+/*      EVSEG     -- Exception vector handlers.                         */
+/*                                                                      */
+/*      Constant segments                                               */
+/*      INITTAB   -- Segment initializer table.                         */
+/*      DIFUNCT   -- Dynamic initialization vector used by C++.         */
+/*      SWITCH    -- Switch tables.                                     */
+/*      ACTAB     -- Table of pointers to acall functions.              */
+/*                                                                      */
+/*      DATA21_ID -- Initialization data for DATA21_I.                  */
+/*      DATA32_ID -- Initialization data for DATA32_I.                  */
+/*      DATA32_C  -- Constant __data32 data.                            */
+/*                                                                      */
+/*      CHECKSUM  -- Checksum segment.                                  */
+/*                                                                      */
+/*      Data segments                                                   */
+/*      DATA21_I  -- Initialized __data21 data with non-zero            */
+/*                   initial value.                                     */
+/*      DATA32_I  -- Initialized __data32 data with non-zero            */
+/*                   initial value.                                     */
+/*      DATA21_Z  -- Initialized __data21 data with zero initial value. */
+/*      DATA32_Z  -- Initialized __data32 data with zero initial value. */
+/*      DATA21_N  -- Non-initialized __data21.                          */
+/*      DATA32_N  -- Non-initialized __data32.                          */
+/*      SSTACK    -- The system stack.                                  */
+/*      CSTACK    -- The application stack.                             */
+/*      HEAP      -- The heap used by malloc and free.                  */
+/*                                                                      */
+/************************************************************************/
+
+/************************************************************************/
+/*      Define CPU                                                      */
+/************************************************************************/
+
+-cavr32
+
+// Declare the IPR0 memory location
+-DIPR0=FFFF0800
+
+/************************************************************************/
+/*      Reset code is located at address 0x80000000 and up.             */
+/************************************************************************/
+
+-Z(CODE)RESET=80000000-8007FFFF
+
+/************************************************************************/
+/*      The exception handler code is located at address 0x80000000     */
+/*      and up. Make sure that the exception table gets properly        */
+/*      allocated. By using the special -Z@ allocation primitive, the   */
+/*      placement is guaranteed to be at _EVBASE and onwards.           */
+/************************************************************************/
+
+-Z@(CODE)EVTAB=80004000-8007FFFF
+-Z@(CODE)EV100=80004100-8007FFFF
+-P(CODE)EVSEG=80004000-8007FFFF
+
+/************************************************************************/
+/*      Allocate code and const segments.                               */
+/************************************************************************/
+
+-P(CODE)CODE32=80000000-8007FFFF
+-P(CONST)DATA32_C=80000000-8007FFFF
+
+// Initializers
+-Z(CONST)INITTAB,DIFUNCT=80000000-8007FFFF
+-Z(CONST)CHECKSUM,SWITCH=80000000-8007FFFF
+-Z(CONST)DATA21_ID,DATA32_ID=80000000-8007FFFF
+
+-Z(CONST)ACTAB,HTAB=80000000-8007FFFF
+
+/************************************************************************/
+/*      Allocate the read/write segments that are mapped to RAM.        */
+/************************************************************************/
+
+-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-0000FFFF
+-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-0000FFFF
+-Z(DATA)TRACEBUFFER=00000004-0000FFFF
+
+-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-0000FFFF
+-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-0000FFFF
+-Z(DATA)HEAP+_HEAP_SIZE=00000004-0000FFFF
+
+/************************************************************************/
+/*      End of File                                                     */
+/************************************************************************/
diff --git a/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/1128/GCC/link_uc3a1128.lds b/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/1128/GCC/link_uc3a1128.lds
new file mode 100644
index 000000000..ffc92e4da
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/1128/GCC/link_uc3a1128.lds
@@ -0,0 +1,263 @@
+/******************************************************************************
+ * AVR32 AT32UC3A1128 GNU LD script file.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  AVR32 AT32UC3A1128
+ *
+ * - author              Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+
+OUTPUT_ARCH(avr32:uc)
+
+ENTRY(_start)
+
+MEMORY
+{
+  FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00020000
+  INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x00007FFC
+  USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200
+  FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 0x00000200
+}
+
+PHDRS
+{
+  FLASH PT_LOAD;
+  INTRAM PT_NULL;
+  USERPAGE PT_LOAD;
+  FACTORYPAGE PT_LOAD;
+}
+
+SECTIONS
+{
+  /* If this heap size is selected, all the INTRAM space from the end of the
+     data area to the beginning of the stack will be allocated for the heap. */
+  __max_heap_size__ = -1;
+
+  /* Use a default heap size if heap size was not defined. */
+  __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__;
+
+  /* Use a default stack size if stack size was not defined. */
+  __stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 4K;
+
+  /* Read-only sections, merged into text segment: */
+  PROVIDE (__executable_start = 0x80000000); . = 0x80000000;
+  .interp         : { *(.interp) } >FLASH AT>FLASH :FLASH
+  .reset : {  *(.reset) } >FLASH AT>FLASH :FLASH
+  .hash           : { *(.hash) } >FLASH AT>FLASH :FLASH
+  .dynsym         : { *(.dynsym) } >FLASH AT>FLASH :FLASH
+  .dynstr         : { *(.dynstr) } >FLASH AT>FLASH :FLASH
+  .gnu.version    : { *(.gnu.version) } >FLASH AT>FLASH :FLASH
+  .gnu.version_d  : { *(.gnu.version_d) } >FLASH AT>FLASH :FLASH
+  .gnu.version_r  : { *(.gnu.version_r) } >FLASH AT>FLASH :FLASH
+  .rel.init       : { *(.rel.init) } >FLASH AT>FLASH :FLASH
+  .rela.init      : { *(.rela.init) } >FLASH AT>FLASH :FLASH
+  .rel.text       : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH
+  .rela.text      : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH
+  .rel.fini       : { *(.rel.fini) } >FLASH AT>FLASH :FLASH
+  .rela.fini      : { *(.rela.fini) } >FLASH AT>FLASH :FLASH
+  .rel.rodata     : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
+  .rela.rodata    : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
+  .rel.data.rel.ro   : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH
+  .rela.data.rel.ro   : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH
+  .rel.data       : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH
+  .rela.data      : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH
+  .rel.tdata	  : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH
+  .rela.tdata	  : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH
+  .rel.tbss	  : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH
+  .rela.tbss	  : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH
+  .rel.ctors      : { *(.rel.ctors) } >FLASH AT>FLASH :FLASH
+  .rela.ctors     : { *(.rela.ctors) } >FLASH AT>FLASH :FLASH
+  .rel.dtors      : { *(.rel.dtors) } >FLASH AT>FLASH :FLASH
+  .rela.dtors     : { *(.rela.dtors) } >FLASH AT>FLASH :FLASH
+  .rel.got        : { *(.rel.got) } >FLASH AT>FLASH :FLASH
+  .rela.got       : { *(.rela.got) } >FLASH AT>FLASH :FLASH
+  .rel.bss        : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH
+  .rela.bss       : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH
+  .rel.plt        : { *(.rel.plt) } >FLASH AT>FLASH :FLASH
+  .rela.plt       : { *(.rela.plt) } >FLASH AT>FLASH :FLASH
+  .init           :
+  {
+    KEEP (*(.init))
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  .plt            : { *(.plt) } >FLASH AT>FLASH :FLASH
+  .text           :
+  {
+    *(.text .stub .text.* .gnu.linkonce.t.*)
+    KEEP (*(.text.*personality*))
+    /* .gnu.warning sections are handled specially by elf32.em.  */
+    *(.gnu.warning)
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  .fini           :
+  {
+    KEEP (*(.fini))
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
+  .rodata1        : { *(.rodata1) } >FLASH AT>FLASH :FLASH
+  .eh_frame_hdr : { *(.eh_frame_hdr) } >FLASH AT>FLASH :FLASH
+  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH :FLASH
+  .gcc_except_table   : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH :FLASH
+  .lalign	: { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH :FLASH
+  . = ORIGIN(INTRAM);
+  .dalign	: { . = ALIGN(8); PROVIDE(_data = .); } >INTRAM AT>INTRAM :INTRAM
+  /* Exception handling  */
+  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) } >INTRAM AT>FLASH :FLASH
+  .gcc_except_table   : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >INTRAM AT>FLASH :FLASH
+  /* Thread Local Storage sections  */
+  .tdata	  : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >INTRAM AT>FLASH :FLASH
+  .tbss		  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >INTRAM AT>FLASH :FLASH
+  /* Ensure the __preinit_array_start label is properly aligned.  We
+     could instead move the label definition inside the section, but
+     the linker would then create the section even if it turns out to
+     be empty, which isn't pretty.  */
+  PROVIDE (__preinit_array_start = ALIGN(32 / 8));
+  .preinit_array     : { KEEP (*(.preinit_array)) } >INTRAM AT>FLASH :FLASH
+  PROVIDE (__preinit_array_end = .);
+  PROVIDE (__init_array_start = .);
+  .init_array     : { KEEP (*(.init_array)) } >INTRAM AT>FLASH :FLASH
+  PROVIDE (__init_array_end = .);
+  PROVIDE (__fini_array_start = .);
+  .fini_array     : { KEEP (*(.fini_array)) } >INTRAM AT>FLASH :FLASH
+  PROVIDE (__fini_array_end = .);
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin*.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  } >INTRAM AT>FLASH :FLASH
+  .dtors          :
+  {
+    KEEP (*crtbegin*.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  } >INTRAM AT>FLASH :FLASH
+  .jcr            : { KEEP (*(.jcr)) } >INTRAM AT>FLASH :FLASH
+  .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >INTRAM AT>FLASH :FLASH
+  .dynamic        : { *(.dynamic) } >INTRAM AT>FLASH :FLASH
+  .got            : { *(.got.plt) *(.got) } >INTRAM AT>FLASH :FLASH
+  .data           :
+  {
+    *(.data .data.* .gnu.linkonce.d.*)
+    KEEP (*(.gnu.linkonce.d.*personality*))
+    SORT(CONSTRUCTORS)
+  } >INTRAM AT>FLASH :FLASH
+  .data1          : { *(.data1) } >INTRAM AT>FLASH :FLASH
+  .balign	: { . = ALIGN(8); _edata = .; } >INTRAM AT>FLASH :FLASH
+  _edata = .;
+  PROVIDE (edata = .);
+  __bss_start = .;
+  .bss            :
+  {
+    *(.dynbss)
+    *(.bss .bss.* .gnu.linkonce.b.*)
+    *(COMMON)
+    /* Align here to ensure that the .bss section occupies space up to
+       _end.  Align after .bss to ensure correct alignment even if the
+       .bss section disappears because there are no input sections.  */
+    . = ALIGN(8);
+  } >INTRAM AT>INTRAM :INTRAM
+  . = ALIGN(8);
+  _end = .;
+  PROVIDE (end = .);
+  __heap_start__ = ALIGN(8);
+  .heap           :
+  {
+    *(.heap)
+    . = (__heap_size__ == __max_heap_size__) ?
+        ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ - ABSOLUTE(.) :
+        __heap_size__;
+  } >INTRAM AT>INTRAM :INTRAM
+  __heap_end__ = .;
+  /* Stabs debugging sections.  */
+  .stab          0 : { *(.stab) }
+  .stabstr       0 : { *(.stabstr) }
+  .stab.excl     0 : { *(.stab.excl) }
+  .stab.exclstr  0 : { *(.stab.exclstr) }
+  .stab.index    0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  .comment       0 : { *(.comment) }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  .stack         ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ :
+  {
+    _stack = .;
+    *(.stack)
+    . = __stack_size__;
+    _estack = .;
+  } >INTRAM AT>INTRAM :INTRAM
+  .userpage       : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE :USERPAGE
+  .factorypage    : { *(.factorypage .factorypage.*) } >FACTORYPAGE AT>FACTORYPAGE :FACTORYPAGE
+  /DISCARD/ : { *(.note.GNU-stack) }
+}
diff --git a/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/1128/IAR/lnkuc3a1128.xcl b/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/1128/IAR/lnkuc3a1128.xcl
new file mode 100644
index 000000000..9f9237cd7
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/1128/IAR/lnkuc3a1128.xcl
@@ -0,0 +1,138 @@
+/******************************************************************************
+ * AVR32 AT32UC3A1128 XLINK command file for AVR32 IAR C/C++ Compiler.
+ *
+ * The assumed memory layout is the one of the AT32UC3A1128:
+ *
+ *   Start       Stop        Name     Type
+ *   ----------  ----------  -----    --------------
+ *   0x00000000  0x00007FFF  SRAM     RAM
+ *   0x80000000  0x8001FFFF  FLASH    FLASH
+ *
+ * Usage:  xlink  your_file(s)  -f xcl-file  libraries
+ *
+ * - Compiler:           IAR EWAVR32
+ * - Supported devices:  AVR32 AT32UC3A1128
+ *
+ * - author              Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/************************************************************************/
+/*      The following segments are defined in this link file:           */
+/*                                                                      */
+/*      Code segments                                                   */
+/*      CODE32    -- Program code used by __code32 functions.           */
+/*      RESET     -- Reset code.                                        */
+/*      EVSEG     -- Exception vector handlers.                         */
+/*                                                                      */
+/*      Constant segments                                               */
+/*      INITTAB   -- Segment initializer table.                         */
+/*      DIFUNCT   -- Dynamic initialization vector used by C++.         */
+/*      SWITCH    -- Switch tables.                                     */
+/*      ACTAB     -- Table of pointers to acall functions.              */
+/*                                                                      */
+/*      DATA21_ID -- Initialization data for DATA21_I.                  */
+/*      DATA32_ID -- Initialization data for DATA32_I.                  */
+/*      DATA32_C  -- Constant __data32 data.                            */
+/*                                                                      */
+/*      CHECKSUM  -- Checksum segment.                                  */
+/*                                                                      */
+/*      Data segments                                                   */
+/*      DATA21_I  -- Initialized __data21 data with non-zero            */
+/*                   initial value.                                     */
+/*      DATA32_I  -- Initialized __data32 data with non-zero            */
+/*                   initial value.                                     */
+/*      DATA21_Z  -- Initialized __data21 data with zero initial value. */
+/*      DATA32_Z  -- Initialized __data32 data with zero initial value. */
+/*      DATA21_N  -- Non-initialized __data21.                          */
+/*      DATA32_N  -- Non-initialized __data32.                          */
+/*      SSTACK    -- The system stack.                                  */
+/*      CSTACK    -- The application stack.                             */
+/*      HEAP      -- The heap used by malloc and free.                  */
+/*                                                                      */
+/************************************************************************/
+
+/************************************************************************/
+/*      Define CPU                                                      */
+/************************************************************************/
+
+-cavr32
+
+// Declare the IPR0 memory location
+-DIPR0=FFFF0800
+
+/************************************************************************/
+/*      Reset code is located at address 0x80000000 and up.             */
+/************************************************************************/
+
+-Z(CODE)RESET=80000000-8001FFFF
+
+/************************************************************************/
+/*      The exception handler code is located at address 0x80000000     */
+/*      and up. Make sure that the exception table gets properly        */
+/*      allocated. By using the special -Z@ allocation primitive, the   */
+/*      placement is guaranteed to be at _EVBASE and onwards.           */
+/************************************************************************/
+
+-Z@(CODE)EVTAB=80004000-8001FFFF
+-Z@(CODE)EV100=80004100-8001FFFF
+-P(CODE)EVSEG=80004000-8001FFFF
+
+/************************************************************************/
+/*      Allocate code and const segments.                               */
+/************************************************************************/
+
+-P(CODE)CODE32=80000000-8001FFFF
+-P(CONST)DATA32_C=80000000-8001FFFF
+
+// Initializers
+-Z(CONST)INITTAB,DIFUNCT=80000000-8001FFFF
+-Z(CONST)CHECKSUM,SWITCH=80000000-8001FFFF
+-Z(CONST)DATA21_ID,DATA32_ID=80000000-8001FFFF
+
+-Z(CONST)ACTAB,HTAB=80000000-8001FFFF
+
+/************************************************************************/
+/*      Allocate the read/write segments that are mapped to RAM.        */
+/************************************************************************/
+
+-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-00007FFF
+-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-00007FFF
+-Z(DATA)TRACEBUFFER=00000004-00007FFF
+
+-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-00007FFF
+-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-00007FFF
+-Z(DATA)HEAP+_HEAP_SIZE=00000004-00007FFF
+
+/************************************************************************/
+/*      End of File                                                     */
+/************************************************************************/
diff --git a/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/1256/GCC/link_uc3a1256.lds b/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/1256/GCC/link_uc3a1256.lds
new file mode 100644
index 000000000..1e464f832
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/1256/GCC/link_uc3a1256.lds
@@ -0,0 +1,263 @@
+/******************************************************************************
+ * AVR32 AT32UC3A1256 GNU LD script file.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  AVR32 AT32UC3A1256
+ *
+ * - author              Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+
+OUTPUT_ARCH(avr32:uc)
+
+ENTRY(_start)
+
+MEMORY
+{
+  FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00040000
+  INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x0000FFFC
+  USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200
+  FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 0x00000200
+}
+
+PHDRS
+{
+  FLASH PT_LOAD;
+  INTRAM PT_NULL;
+  USERPAGE PT_LOAD;
+  FACTORYPAGE PT_LOAD;
+}
+
+SECTIONS
+{
+  /* If this heap size is selected, all the INTRAM space from the end of the
+     data area to the beginning of the stack will be allocated for the heap. */
+  __max_heap_size__ = -1;
+
+  /* Use a default heap size if heap size was not defined. */
+  __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__;
+
+  /* Use a default stack size if stack size was not defined. */
+  __stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 4K;
+
+  /* Read-only sections, merged into text segment: */
+  PROVIDE (__executable_start = 0x80000000); . = 0x80000000;
+  .interp         : { *(.interp) } >FLASH AT>FLASH :FLASH
+  .reset : {  *(.reset) } >FLASH AT>FLASH :FLASH
+  .hash           : { *(.hash) } >FLASH AT>FLASH :FLASH
+  .dynsym         : { *(.dynsym) } >FLASH AT>FLASH :FLASH
+  .dynstr         : { *(.dynstr) } >FLASH AT>FLASH :FLASH
+  .gnu.version    : { *(.gnu.version) } >FLASH AT>FLASH :FLASH
+  .gnu.version_d  : { *(.gnu.version_d) } >FLASH AT>FLASH :FLASH
+  .gnu.version_r  : { *(.gnu.version_r) } >FLASH AT>FLASH :FLASH
+  .rel.init       : { *(.rel.init) } >FLASH AT>FLASH :FLASH
+  .rela.init      : { *(.rela.init) } >FLASH AT>FLASH :FLASH
+  .rel.text       : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH
+  .rela.text      : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH
+  .rel.fini       : { *(.rel.fini) } >FLASH AT>FLASH :FLASH
+  .rela.fini      : { *(.rela.fini) } >FLASH AT>FLASH :FLASH
+  .rel.rodata     : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
+  .rela.rodata    : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
+  .rel.data.rel.ro   : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH
+  .rela.data.rel.ro   : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH
+  .rel.data       : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH
+  .rela.data      : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH
+  .rel.tdata	  : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH
+  .rela.tdata	  : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH
+  .rel.tbss	  : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH
+  .rela.tbss	  : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH
+  .rel.ctors      : { *(.rel.ctors) } >FLASH AT>FLASH :FLASH
+  .rela.ctors     : { *(.rela.ctors) } >FLASH AT>FLASH :FLASH
+  .rel.dtors      : { *(.rel.dtors) } >FLASH AT>FLASH :FLASH
+  .rela.dtors     : { *(.rela.dtors) } >FLASH AT>FLASH :FLASH
+  .rel.got        : { *(.rel.got) } >FLASH AT>FLASH :FLASH
+  .rela.got       : { *(.rela.got) } >FLASH AT>FLASH :FLASH
+  .rel.bss        : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH
+  .rela.bss       : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH
+  .rel.plt        : { *(.rel.plt) } >FLASH AT>FLASH :FLASH
+  .rela.plt       : { *(.rela.plt) } >FLASH AT>FLASH :FLASH
+  .init           :
+  {
+    KEEP (*(.init))
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  .plt            : { *(.plt) } >FLASH AT>FLASH :FLASH
+  .text           :
+  {
+    *(.text .stub .text.* .gnu.linkonce.t.*)
+    KEEP (*(.text.*personality*))
+    /* .gnu.warning sections are handled specially by elf32.em.  */
+    *(.gnu.warning)
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  .fini           :
+  {
+    KEEP (*(.fini))
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
+  .rodata1        : { *(.rodata1) } >FLASH AT>FLASH :FLASH
+  .eh_frame_hdr : { *(.eh_frame_hdr) } >FLASH AT>FLASH :FLASH
+  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH :FLASH
+  .gcc_except_table   : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH :FLASH
+  .lalign	: { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH :FLASH
+  . = ORIGIN(INTRAM);
+  .dalign	: { . = ALIGN(8); PROVIDE(_data = .); } >INTRAM AT>INTRAM :INTRAM
+  /* Exception handling  */
+  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) } >INTRAM AT>FLASH :FLASH
+  .gcc_except_table   : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >INTRAM AT>FLASH :FLASH
+  /* Thread Local Storage sections  */
+  .tdata	  : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >INTRAM AT>FLASH :FLASH
+  .tbss		  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >INTRAM AT>FLASH :FLASH
+  /* Ensure the __preinit_array_start label is properly aligned.  We
+     could instead move the label definition inside the section, but
+     the linker would then create the section even if it turns out to
+     be empty, which isn't pretty.  */
+  PROVIDE (__preinit_array_start = ALIGN(32 / 8));
+  .preinit_array     : { KEEP (*(.preinit_array)) } >INTRAM AT>FLASH :FLASH
+  PROVIDE (__preinit_array_end = .);
+  PROVIDE (__init_array_start = .);
+  .init_array     : { KEEP (*(.init_array)) } >INTRAM AT>FLASH :FLASH
+  PROVIDE (__init_array_end = .);
+  PROVIDE (__fini_array_start = .);
+  .fini_array     : { KEEP (*(.fini_array)) } >INTRAM AT>FLASH :FLASH
+  PROVIDE (__fini_array_end = .);
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin*.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  } >INTRAM AT>FLASH :FLASH
+  .dtors          :
+  {
+    KEEP (*crtbegin*.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  } >INTRAM AT>FLASH :FLASH
+  .jcr            : { KEEP (*(.jcr)) } >INTRAM AT>FLASH :FLASH
+  .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >INTRAM AT>FLASH :FLASH
+  .dynamic        : { *(.dynamic) } >INTRAM AT>FLASH :FLASH
+  .got            : { *(.got.plt) *(.got) } >INTRAM AT>FLASH :FLASH
+  .data           :
+  {
+    *(.data .data.* .gnu.linkonce.d.*)
+    KEEP (*(.gnu.linkonce.d.*personality*))
+    SORT(CONSTRUCTORS)
+  } >INTRAM AT>FLASH :FLASH
+  .data1          : { *(.data1) } >INTRAM AT>FLASH :FLASH
+  .balign	: { . = ALIGN(8); _edata = .; } >INTRAM AT>FLASH :FLASH
+  _edata = .;
+  PROVIDE (edata = .);
+  __bss_start = .;
+  .bss            :
+  {
+    *(.dynbss)
+    *(.bss .bss.* .gnu.linkonce.b.*)
+    *(COMMON)
+    /* Align here to ensure that the .bss section occupies space up to
+       _end.  Align after .bss to ensure correct alignment even if the
+       .bss section disappears because there are no input sections.  */
+    . = ALIGN(8);
+  } >INTRAM AT>INTRAM :INTRAM
+  . = ALIGN(8);
+  _end = .;
+  PROVIDE (end = .);
+  __heap_start__ = ALIGN(8);
+  .heap           :
+  {
+    *(.heap)
+    . = (__heap_size__ == __max_heap_size__) ?
+        ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ - ABSOLUTE(.) :
+        __heap_size__;
+  } >INTRAM AT>INTRAM :INTRAM
+  __heap_end__ = .;
+  /* Stabs debugging sections.  */
+  .stab          0 : { *(.stab) }
+  .stabstr       0 : { *(.stabstr) }
+  .stab.excl     0 : { *(.stab.excl) }
+  .stab.exclstr  0 : { *(.stab.exclstr) }
+  .stab.index    0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  .comment       0 : { *(.comment) }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  .stack         ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ :
+  {
+    _stack = .;
+    *(.stack)
+    . = __stack_size__;
+    _estack = .;
+  } >INTRAM AT>INTRAM :INTRAM
+  .userpage       : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE :USERPAGE
+  .factorypage    : { *(.factorypage .factorypage.*) } >FACTORYPAGE AT>FACTORYPAGE :FACTORYPAGE
+  /DISCARD/ : { *(.note.GNU-stack) }
+}
diff --git a/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/1256/IAR/lnkuc3a1256.xcl b/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/1256/IAR/lnkuc3a1256.xcl
new file mode 100644
index 000000000..823654a68
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/1256/IAR/lnkuc3a1256.xcl
@@ -0,0 +1,138 @@
+/******************************************************************************
+ * AVR32 AT32UC3A1256 XLINK command file for AVR32 IAR C/C++ Compiler.
+ *
+ * The assumed memory layout is the one of the AT32UC3A1256:
+ *
+ *   Start       Stop        Name     Type
+ *   ----------  ----------  -----    --------------
+ *   0x00000000  0x0000FFFF  SRAM     RAM
+ *   0x80000000  0x8003FFFF  FLASH    FLASH
+ *
+ * Usage:  xlink  your_file(s)  -f xcl-file  libraries
+ *
+ * - Compiler:           IAR EWAVR32
+ * - Supported devices:  AVR32 AT32UC3A1256
+ *
+ * - author              Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/************************************************************************/
+/*      The following segments are defined in this link file:           */
+/*                                                                      */
+/*      Code segments                                                   */
+/*      CODE32    -- Program code used by __code32 functions.           */
+/*      RESET     -- Reset code.                                        */
+/*      EVSEG     -- Exception vector handlers.                         */
+/*                                                                      */
+/*      Constant segments                                               */
+/*      INITTAB   -- Segment initializer table.                         */
+/*      DIFUNCT   -- Dynamic initialization vector used by C++.         */
+/*      SWITCH    -- Switch tables.                                     */
+/*      ACTAB     -- Table of pointers to acall functions.              */
+/*                                                                      */
+/*      DATA21_ID -- Initialization data for DATA21_I.                  */
+/*      DATA32_ID -- Initialization data for DATA32_I.                  */
+/*      DATA32_C  -- Constant __data32 data.                            */
+/*                                                                      */
+/*      CHECKSUM  -- Checksum segment.                                  */
+/*                                                                      */
+/*      Data segments                                                   */
+/*      DATA21_I  -- Initialized __data21 data with non-zero            */
+/*                   initial value.                                     */
+/*      DATA32_I  -- Initialized __data32 data with non-zero            */
+/*                   initial value.                                     */
+/*      DATA21_Z  -- Initialized __data21 data with zero initial value. */
+/*      DATA32_Z  -- Initialized __data32 data with zero initial value. */
+/*      DATA21_N  -- Non-initialized __data21.                          */
+/*      DATA32_N  -- Non-initialized __data32.                          */
+/*      SSTACK    -- The system stack.                                  */
+/*      CSTACK    -- The application stack.                             */
+/*      HEAP      -- The heap used by malloc and free.                  */
+/*                                                                      */
+/************************************************************************/
+
+/************************************************************************/
+/*      Define CPU                                                      */
+/************************************************************************/
+
+-cavr32
+
+// Declare the IPR0 memory location
+-DIPR0=FFFF0800
+
+/************************************************************************/
+/*      Reset code is located at address 0x80000000 and up.             */
+/************************************************************************/
+
+-Z(CODE)RESET=80000000-8003FFFF
+
+/************************************************************************/
+/*      The exception handler code is located at address 0x80000000     */
+/*      and up. Make sure that the exception table gets properly        */
+/*      allocated. By using the special -Z@ allocation primitive, the   */
+/*      placement is guaranteed to be at _EVBASE and onwards.           */
+/************************************************************************/
+
+-Z@(CODE)EVTAB=80004000-8003FFFF
+-Z@(CODE)EV100=80004100-8003FFFF
+-P(CODE)EVSEG=80004000-8003FFFF
+
+/************************************************************************/
+/*      Allocate code and const segments.                               */
+/************************************************************************/
+
+-P(CODE)CODE32=80000000-8003FFFF
+-P(CONST)DATA32_C=80000000-8003FFFF
+
+// Initializers
+-Z(CONST)INITTAB,DIFUNCT=80000000-8003FFFF
+-Z(CONST)CHECKSUM,SWITCH=80000000-8003FFFF
+-Z(CONST)DATA21_ID,DATA32_ID=80000000-8003FFFF
+
+-Z(CONST)ACTAB,HTAB=80000000-8003FFFF
+
+/************************************************************************/
+/*      Allocate the read/write segments that are mapped to RAM.        */
+/************************************************************************/
+
+-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-0000FFFF
+-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-0000FFFF
+-Z(DATA)TRACEBUFFER=00000004-0000FFFF
+
+-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-0000FFFF
+-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-0000FFFF
+-Z(DATA)HEAP+_HEAP_SIZE=00000004-0000FFFF
+
+/************************************************************************/
+/*      End of File                                                     */
+/************************************************************************/
diff --git a/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/1512/GCC/link_uc3a1512.lds b/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/1512/GCC/link_uc3a1512.lds
new file mode 100644
index 000000000..a171bd0b6
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/1512/GCC/link_uc3a1512.lds
@@ -0,0 +1,263 @@
+/******************************************************************************
+ * AVR32 AT32UC3A1512 GNU LD script file.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  AVR32 AT32UC3A1512
+ *
+ * - author              Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+
+OUTPUT_ARCH(avr32:uc)
+
+ENTRY(_start)
+
+MEMORY
+{
+  FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00080000
+  INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x0000FFFC
+  USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200
+  FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 0x00000200
+}
+
+PHDRS
+{
+  FLASH PT_LOAD;
+  INTRAM PT_NULL;
+  USERPAGE PT_LOAD;
+  FACTORYPAGE PT_LOAD;
+}
+
+SECTIONS
+{
+  /* If this heap size is selected, all the INTRAM space from the end of the
+     data area to the beginning of the stack will be allocated for the heap. */
+  __max_heap_size__ = -1;
+
+  /* Use a default heap size if heap size was not defined. */
+  __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__;
+
+  /* Use a default stack size if stack size was not defined. */
+  __stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 4K;
+
+  /* Read-only sections, merged into text segment: */
+  PROVIDE (__executable_start = 0x80000000); . = 0x80000000;
+  .interp         : { *(.interp) } >FLASH AT>FLASH :FLASH
+  .reset : {  *(.reset) } >FLASH AT>FLASH :FLASH
+  .hash           : { *(.hash) } >FLASH AT>FLASH :FLASH
+  .dynsym         : { *(.dynsym) } >FLASH AT>FLASH :FLASH
+  .dynstr         : { *(.dynstr) } >FLASH AT>FLASH :FLASH
+  .gnu.version    : { *(.gnu.version) } >FLASH AT>FLASH :FLASH
+  .gnu.version_d  : { *(.gnu.version_d) } >FLASH AT>FLASH :FLASH
+  .gnu.version_r  : { *(.gnu.version_r) } >FLASH AT>FLASH :FLASH
+  .rel.init       : { *(.rel.init) } >FLASH AT>FLASH :FLASH
+  .rela.init      : { *(.rela.init) } >FLASH AT>FLASH :FLASH
+  .rel.text       : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH
+  .rela.text      : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH
+  .rel.fini       : { *(.rel.fini) } >FLASH AT>FLASH :FLASH
+  .rela.fini      : { *(.rela.fini) } >FLASH AT>FLASH :FLASH
+  .rel.rodata     : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
+  .rela.rodata    : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
+  .rel.data.rel.ro   : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH
+  .rela.data.rel.ro   : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH
+  .rel.data       : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH
+  .rela.data      : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH
+  .rel.tdata	  : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH
+  .rela.tdata	  : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH
+  .rel.tbss	  : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH
+  .rela.tbss	  : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH
+  .rel.ctors      : { *(.rel.ctors) } >FLASH AT>FLASH :FLASH
+  .rela.ctors     : { *(.rela.ctors) } >FLASH AT>FLASH :FLASH
+  .rel.dtors      : { *(.rel.dtors) } >FLASH AT>FLASH :FLASH
+  .rela.dtors     : { *(.rela.dtors) } >FLASH AT>FLASH :FLASH
+  .rel.got        : { *(.rel.got) } >FLASH AT>FLASH :FLASH
+  .rela.got       : { *(.rela.got) } >FLASH AT>FLASH :FLASH
+  .rel.bss        : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH
+  .rela.bss       : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH
+  .rel.plt        : { *(.rel.plt) } >FLASH AT>FLASH :FLASH
+  .rela.plt       : { *(.rela.plt) } >FLASH AT>FLASH :FLASH
+  .init           :
+  {
+    KEEP (*(.init))
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  .plt            : { *(.plt) } >FLASH AT>FLASH :FLASH
+  .text           :
+  {
+    *(.text .stub .text.* .gnu.linkonce.t.*)
+    KEEP (*(.text.*personality*))
+    /* .gnu.warning sections are handled specially by elf32.em.  */
+    *(.gnu.warning)
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  .fini           :
+  {
+    KEEP (*(.fini))
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
+  .rodata1        : { *(.rodata1) } >FLASH AT>FLASH :FLASH
+  .eh_frame_hdr : { *(.eh_frame_hdr) } >FLASH AT>FLASH :FLASH
+  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH :FLASH
+  .gcc_except_table   : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH :FLASH
+  .lalign	: { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH :FLASH
+  . = ORIGIN(INTRAM);
+  .dalign	: { . = ALIGN(8); PROVIDE(_data = .); } >INTRAM AT>INTRAM :INTRAM
+  /* Exception handling  */
+  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) } >INTRAM AT>FLASH :FLASH
+  .gcc_except_table   : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >INTRAM AT>FLASH :FLASH
+  /* Thread Local Storage sections  */
+  .tdata	  : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >INTRAM AT>FLASH :FLASH
+  .tbss		  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >INTRAM AT>FLASH :FLASH
+  /* Ensure the __preinit_array_start label is properly aligned.  We
+     could instead move the label definition inside the section, but
+     the linker would then create the section even if it turns out to
+     be empty, which isn't pretty.  */
+  PROVIDE (__preinit_array_start = ALIGN(32 / 8));
+  .preinit_array     : { KEEP (*(.preinit_array)) } >INTRAM AT>FLASH :FLASH
+  PROVIDE (__preinit_array_end = .);
+  PROVIDE (__init_array_start = .);
+  .init_array     : { KEEP (*(.init_array)) } >INTRAM AT>FLASH :FLASH
+  PROVIDE (__init_array_end = .);
+  PROVIDE (__fini_array_start = .);
+  .fini_array     : { KEEP (*(.fini_array)) } >INTRAM AT>FLASH :FLASH
+  PROVIDE (__fini_array_end = .);
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin*.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  } >INTRAM AT>FLASH :FLASH
+  .dtors          :
+  {
+    KEEP (*crtbegin*.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  } >INTRAM AT>FLASH :FLASH
+  .jcr            : { KEEP (*(.jcr)) } >INTRAM AT>FLASH :FLASH
+  .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >INTRAM AT>FLASH :FLASH
+  .dynamic        : { *(.dynamic) } >INTRAM AT>FLASH :FLASH
+  .got            : { *(.got.plt) *(.got) } >INTRAM AT>FLASH :FLASH
+  .data           :
+  {
+    *(.data .data.* .gnu.linkonce.d.*)
+    KEEP (*(.gnu.linkonce.d.*personality*))
+    SORT(CONSTRUCTORS)
+  } >INTRAM AT>FLASH :FLASH
+  .data1          : { *(.data1) } >INTRAM AT>FLASH :FLASH
+  .balign	: { . = ALIGN(8); _edata = .; } >INTRAM AT>FLASH :FLASH
+  _edata = .;
+  PROVIDE (edata = .);
+  __bss_start = .;
+  .bss            :
+  {
+    *(.dynbss)
+    *(.bss .bss.* .gnu.linkonce.b.*)
+    *(COMMON)
+    /* Align here to ensure that the .bss section occupies space up to
+       _end.  Align after .bss to ensure correct alignment even if the
+       .bss section disappears because there are no input sections.  */
+    . = ALIGN(8);
+  } >INTRAM AT>INTRAM :INTRAM
+  . = ALIGN(8);
+  _end = .;
+  PROVIDE (end = .);
+  __heap_start__ = ALIGN(8);
+  .heap           :
+  {
+    *(.heap)
+    . = (__heap_size__ == __max_heap_size__) ?
+        ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ - ABSOLUTE(.) :
+        __heap_size__;
+  } >INTRAM AT>INTRAM :INTRAM
+  __heap_end__ = .;
+  /* Stabs debugging sections.  */
+  .stab          0 : { *(.stab) }
+  .stabstr       0 : { *(.stabstr) }
+  .stab.excl     0 : { *(.stab.excl) }
+  .stab.exclstr  0 : { *(.stab.exclstr) }
+  .stab.index    0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  .comment       0 : { *(.comment) }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  .stack         ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ :
+  {
+    _stack = .;
+    *(.stack)
+    . = __stack_size__;
+    _estack = .;
+  } >INTRAM AT>INTRAM :INTRAM
+  .userpage       : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE :USERPAGE
+  .factorypage    : { *(.factorypage .factorypage.*) } >FACTORYPAGE AT>FACTORYPAGE :FACTORYPAGE
+  /DISCARD/ : { *(.note.GNU-stack) }
+}
diff --git a/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/1512/IAR/lnkuc3a1512.xcl b/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/1512/IAR/lnkuc3a1512.xcl
new file mode 100644
index 000000000..33ec1d367
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3A/1512/IAR/lnkuc3a1512.xcl
@@ -0,0 +1,138 @@
+/******************************************************************************
+ * AVR32 AT32UC3A1512 XLINK command file for AVR32 IAR C/C++ Compiler.
+ *
+ * The assumed memory layout is the one of the AT32UC3A1512:
+ *
+ *   Start       Stop        Name     Type
+ *   ----------  ----------  -----    --------------
+ *   0x00000000  0x0000FFFF  SRAM     RAM
+ *   0x80000000  0x8007FFFF  FLASH    FLASH
+ *
+ * Usage:  xlink  your_file(s)  -f xcl-file  libraries
+ *
+ * - Compiler:           IAR EWAVR32
+ * - Supported devices:  AVR32 AT32UC3A1512
+ *
+ * - author              Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/************************************************************************/
+/*      The following segments are defined in this link file:           */
+/*                                                                      */
+/*      Code segments                                                   */
+/*      CODE32    -- Program code used by __code32 functions.           */
+/*      RESET     -- Reset code.                                        */
+/*      EVSEG     -- Exception vector handlers.                         */
+/*                                                                      */
+/*      Constant segments                                               */
+/*      INITTAB   -- Segment initializer table.                         */
+/*      DIFUNCT   -- Dynamic initialization vector used by C++.         */
+/*      SWITCH    -- Switch tables.                                     */
+/*      ACTAB     -- Table of pointers to acall functions.              */
+/*                                                                      */
+/*      DATA21_ID -- Initialization data for DATA21_I.                  */
+/*      DATA32_ID -- Initialization data for DATA32_I.                  */
+/*      DATA32_C  -- Constant __data32 data.                            */
+/*                                                                      */
+/*      CHECKSUM  -- Checksum segment.                                  */
+/*                                                                      */
+/*      Data segments                                                   */
+/*      DATA21_I  -- Initialized __data21 data with non-zero            */
+/*                   initial value.                                     */
+/*      DATA32_I  -- Initialized __data32 data with non-zero            */
+/*                   initial value.                                     */
+/*      DATA21_Z  -- Initialized __data21 data with zero initial value. */
+/*      DATA32_Z  -- Initialized __data32 data with zero initial value. */
+/*      DATA21_N  -- Non-initialized __data21.                          */
+/*      DATA32_N  -- Non-initialized __data32.                          */
+/*      SSTACK    -- The system stack.                                  */
+/*      CSTACK    -- The application stack.                             */
+/*      HEAP      -- The heap used by malloc and free.                  */
+/*                                                                      */
+/************************************************************************/
+
+/************************************************************************/
+/*      Define CPU                                                      */
+/************************************************************************/
+
+-cavr32
+
+// Declare the IPR0 memory location
+-DIPR0=FFFF0800
+
+/************************************************************************/
+/*      Reset code is located at address 0x80000000 and up.             */
+/************************************************************************/
+
+-Z(CODE)RESET=80000000-8007FFFF
+
+/************************************************************************/
+/*      The exception handler code is located at address 0x80000000     */
+/*      and up. Make sure that the exception table gets properly        */
+/*      allocated. By using the special -Z@ allocation primitive, the   */
+/*      placement is guaranteed to be at _EVBASE and onwards.           */
+/************************************************************************/
+
+-Z@(CODE)EVTAB=80004000-8007FFFF
+-Z@(CODE)EV100=80004100-8007FFFF
+-P(CODE)EVSEG=80004000-8007FFFF
+
+/************************************************************************/
+/*      Allocate code and const segments.                               */
+/************************************************************************/
+
+-P(CODE)CODE32=80000000-8007FFFF
+-P(CONST)DATA32_C=80000000-8007FFFF
+
+// Initializers
+-Z(CONST)INITTAB,DIFUNCT=80000000-8007FFFF
+-Z(CONST)CHECKSUM,SWITCH=80000000-8007FFFF
+-Z(CONST)DATA21_ID,DATA32_ID=80000000-8007FFFF
+
+-Z(CONST)ACTAB,HTAB=80000000-8007FFFF
+
+/************************************************************************/
+/*      Allocate the read/write segments that are mapped to RAM.        */
+/************************************************************************/
+
+-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-0000FFFF
+-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-0000FFFF
+-Z(DATA)TRACEBUFFER=00000004-0000FFFF
+
+-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-0000FFFF
+-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-0000FFFF
+-Z(DATA)HEAP+_HEAP_SIZE=00000004-0000FFFF
+
+/************************************************************************/
+/*      End of File                                                     */
+/************************************************************************/
diff --git a/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/0128/GCC/link_uc3b0128.lds b/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/0128/GCC/link_uc3b0128.lds
new file mode 100644
index 000000000..cf3a8db14
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/0128/GCC/link_uc3b0128.lds
@@ -0,0 +1,263 @@
+/******************************************************************************
+ * AVR32 AT32UC3B0128 GNU LD script file.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  AVR32 AT32UC3B0128
+ *
+ * - author              Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+
+OUTPUT_ARCH(avr32:uc)
+
+ENTRY(_start)
+
+MEMORY
+{
+  FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00020000
+  INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x00007FFC
+  USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200
+  FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 0x00000200
+}
+
+PHDRS
+{
+  FLASH PT_LOAD;
+  INTRAM PT_NULL;
+  USERPAGE PT_LOAD;
+  FACTORYPAGE PT_LOAD;
+}
+
+SECTIONS
+{
+  /* If this heap size is selected, all the INTRAM space from the end of the
+     data area to the beginning of the stack will be allocated for the heap. */
+  __max_heap_size__ = -1;
+
+  /* Use a default heap size if heap size was not defined. */
+  __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__;
+
+  /* Use a default stack size if stack size was not defined. */
+  __stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 4K;
+
+  /* Read-only sections, merged into text segment: */
+  PROVIDE (__executable_start = 0x80000000); . = 0x80000000;
+  .interp         : { *(.interp) } >FLASH AT>FLASH :FLASH
+  .reset : {  *(.reset) } >FLASH AT>FLASH :FLASH
+  .hash           : { *(.hash) } >FLASH AT>FLASH :FLASH
+  .dynsym         : { *(.dynsym) } >FLASH AT>FLASH :FLASH
+  .dynstr         : { *(.dynstr) } >FLASH AT>FLASH :FLASH
+  .gnu.version    : { *(.gnu.version) } >FLASH AT>FLASH :FLASH
+  .gnu.version_d  : { *(.gnu.version_d) } >FLASH AT>FLASH :FLASH
+  .gnu.version_r  : { *(.gnu.version_r) } >FLASH AT>FLASH :FLASH
+  .rel.init       : { *(.rel.init) } >FLASH AT>FLASH :FLASH
+  .rela.init      : { *(.rela.init) } >FLASH AT>FLASH :FLASH
+  .rel.text       : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH
+  .rela.text      : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH
+  .rel.fini       : { *(.rel.fini) } >FLASH AT>FLASH :FLASH
+  .rela.fini      : { *(.rela.fini) } >FLASH AT>FLASH :FLASH
+  .rel.rodata     : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
+  .rela.rodata    : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
+  .rel.data.rel.ro   : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH
+  .rela.data.rel.ro   : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH
+  .rel.data       : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH
+  .rela.data      : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH
+  .rel.tdata	  : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH
+  .rela.tdata	  : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH
+  .rel.tbss	  : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH
+  .rela.tbss	  : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH
+  .rel.ctors      : { *(.rel.ctors) } >FLASH AT>FLASH :FLASH
+  .rela.ctors     : { *(.rela.ctors) } >FLASH AT>FLASH :FLASH
+  .rel.dtors      : { *(.rel.dtors) } >FLASH AT>FLASH :FLASH
+  .rela.dtors     : { *(.rela.dtors) } >FLASH AT>FLASH :FLASH
+  .rel.got        : { *(.rel.got) } >FLASH AT>FLASH :FLASH
+  .rela.got       : { *(.rela.got) } >FLASH AT>FLASH :FLASH
+  .rel.bss        : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH
+  .rela.bss       : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH
+  .rel.plt        : { *(.rel.plt) } >FLASH AT>FLASH :FLASH
+  .rela.plt       : { *(.rela.plt) } >FLASH AT>FLASH :FLASH
+  .init           :
+  {
+    KEEP (*(.init))
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  .plt            : { *(.plt) } >FLASH AT>FLASH :FLASH
+  .text           :
+  {
+    *(.text .stub .text.* .gnu.linkonce.t.*)
+    KEEP (*(.text.*personality*))
+    /* .gnu.warning sections are handled specially by elf32.em.  */
+    *(.gnu.warning)
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  .fini           :
+  {
+    KEEP (*(.fini))
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
+  .rodata1        : { *(.rodata1) } >FLASH AT>FLASH :FLASH
+  .eh_frame_hdr : { *(.eh_frame_hdr) } >FLASH AT>FLASH :FLASH
+  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH :FLASH
+  .gcc_except_table   : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH :FLASH
+  .lalign	: { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH :FLASH
+  . = ORIGIN(INTRAM);
+  .dalign	: { . = ALIGN(8); PROVIDE(_data = .); } >INTRAM AT>INTRAM :INTRAM
+  /* Exception handling  */
+  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) } >INTRAM AT>FLASH :FLASH
+  .gcc_except_table   : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >INTRAM AT>FLASH :FLASH
+  /* Thread Local Storage sections  */
+  .tdata	  : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >INTRAM AT>FLASH :FLASH
+  .tbss		  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >INTRAM AT>FLASH :FLASH
+  /* Ensure the __preinit_array_start label is properly aligned.  We
+     could instead move the label definition inside the section, but
+     the linker would then create the section even if it turns out to
+     be empty, which isn't pretty.  */
+  PROVIDE (__preinit_array_start = ALIGN(32 / 8));
+  .preinit_array     : { KEEP (*(.preinit_array)) } >INTRAM AT>FLASH :FLASH
+  PROVIDE (__preinit_array_end = .);
+  PROVIDE (__init_array_start = .);
+  .init_array     : { KEEP (*(.init_array)) } >INTRAM AT>FLASH :FLASH
+  PROVIDE (__init_array_end = .);
+  PROVIDE (__fini_array_start = .);
+  .fini_array     : { KEEP (*(.fini_array)) } >INTRAM AT>FLASH :FLASH
+  PROVIDE (__fini_array_end = .);
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin*.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  } >INTRAM AT>FLASH :FLASH
+  .dtors          :
+  {
+    KEEP (*crtbegin*.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  } >INTRAM AT>FLASH :FLASH
+  .jcr            : { KEEP (*(.jcr)) } >INTRAM AT>FLASH :FLASH
+  .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >INTRAM AT>FLASH :FLASH
+  .dynamic        : { *(.dynamic) } >INTRAM AT>FLASH :FLASH
+  .got            : { *(.got.plt) *(.got) } >INTRAM AT>FLASH :FLASH
+  .data           :
+  {
+    *(.data .data.* .gnu.linkonce.d.*)
+    KEEP (*(.gnu.linkonce.d.*personality*))
+    SORT(CONSTRUCTORS)
+  } >INTRAM AT>FLASH :FLASH
+  .data1          : { *(.data1) } >INTRAM AT>FLASH :FLASH
+  .balign	: { . = ALIGN(8); _edata = .; } >INTRAM AT>FLASH :FLASH
+  _edata = .;
+  PROVIDE (edata = .);
+  __bss_start = .;
+  .bss            :
+  {
+    *(.dynbss)
+    *(.bss .bss.* .gnu.linkonce.b.*)
+    *(COMMON)
+    /* Align here to ensure that the .bss section occupies space up to
+       _end.  Align after .bss to ensure correct alignment even if the
+       .bss section disappears because there are no input sections.  */
+    . = ALIGN(8);
+  } >INTRAM AT>INTRAM :INTRAM
+  . = ALIGN(8);
+  _end = .;
+  PROVIDE (end = .);
+  __heap_start__ = ALIGN(8);
+  .heap           :
+  {
+    *(.heap)
+    . = (__heap_size__ == __max_heap_size__) ?
+        ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ - ABSOLUTE(.) :
+        __heap_size__;
+  } >INTRAM AT>INTRAM :INTRAM
+  __heap_end__ = .;
+  /* Stabs debugging sections.  */
+  .stab          0 : { *(.stab) }
+  .stabstr       0 : { *(.stabstr) }
+  .stab.excl     0 : { *(.stab.excl) }
+  .stab.exclstr  0 : { *(.stab.exclstr) }
+  .stab.index    0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  .comment       0 : { *(.comment) }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  .stack         ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ :
+  {
+    _stack = .;
+    *(.stack)
+    . = __stack_size__;
+    _estack = .;
+  } >INTRAM AT>INTRAM :INTRAM
+  .userpage       : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE :USERPAGE
+  .factorypage    : { *(.factorypage .factorypage.*) } >FACTORYPAGE AT>FACTORYPAGE :FACTORYPAGE
+  /DISCARD/ : { *(.note.GNU-stack) }
+}
diff --git a/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/0128/IAR/lnkuc3b0128.xcl b/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/0128/IAR/lnkuc3b0128.xcl
new file mode 100644
index 000000000..f45cf7392
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/0128/IAR/lnkuc3b0128.xcl
@@ -0,0 +1,138 @@
+/******************************************************************************
+ * AVR32 AT32UC3B0128 XLINK command file for AVR32 IAR C/C++ Compiler.
+ *
+ * The assumed memory layout is the one of the AT32UC3B0128:
+ *
+ *   Start       Stop        Name     Type
+ *   ----------  ----------  -----    --------------
+ *   0x00000000  0x00007FFF  SRAM     RAM
+ *   0x80000000  0x8001FFFF  FLASH    FLASH
+ *
+ * Usage:  xlink  your_file(s)  -f xcl-file  libraries
+ *
+ * - Compiler:           IAR EWAVR32
+ * - Supported devices:  AVR32 AT32UC3B0128
+ *
+ * - author              Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/************************************************************************/
+/*      The following segments are defined in this link file:           */
+/*                                                                      */
+/*      Code segments                                                   */
+/*      CODE32    -- Program code used by __code32 functions.           */
+/*      RESET     -- Reset code.                                        */
+/*      EVSEG     -- Exception vector handlers.                         */
+/*                                                                      */
+/*      Constant segments                                               */
+/*      INITTAB   -- Segment initializer table.                         */
+/*      DIFUNCT   -- Dynamic initialization vector used by C++.         */
+/*      SWITCH    -- Switch tables.                                     */
+/*      ACTAB     -- Table of pointers to acall functions.              */
+/*                                                                      */
+/*      DATA21_ID -- Initialization data for DATA21_I.                  */
+/*      DATA32_ID -- Initialization data for DATA32_I.                  */
+/*      DATA32_C  -- Constant __data32 data.                            */
+/*                                                                      */
+/*      CHECKSUM  -- Checksum segment.                                  */
+/*                                                                      */
+/*      Data segments                                                   */
+/*      DATA21_I  -- Initialized __data21 data with non-zero            */
+/*                   initial value.                                     */
+/*      DATA32_I  -- Initialized __data32 data with non-zero            */
+/*                   initial value.                                     */
+/*      DATA21_Z  -- Initialized __data21 data with zero initial value. */
+/*      DATA32_Z  -- Initialized __data32 data with zero initial value. */
+/*      DATA21_N  -- Non-initialized __data21.                          */
+/*      DATA32_N  -- Non-initialized __data32.                          */
+/*      SSTACK    -- The system stack.                                  */
+/*      CSTACK    -- The application stack.                             */
+/*      HEAP      -- The heap used by malloc and free.                  */
+/*                                                                      */
+/************************************************************************/
+
+/************************************************************************/
+/*      Define CPU                                                      */
+/************************************************************************/
+
+-cavr32
+
+// Declare the IPR0 memory location
+-DIPR0=FFFF0800
+
+/************************************************************************/
+/*      Reset code is located at address 0x80000000 and up.             */
+/************************************************************************/
+
+-Z(CODE)RESET=80000000-8001FFFF
+
+/************************************************************************/
+/*      The exception handler code is located at address 0x80000000     */
+/*      and up. Make sure that the exception table gets properly        */
+/*      allocated. By using the special -Z@ allocation primitive, the   */
+/*      placement is guaranteed to be at _EVBASE and onwards.           */
+/************************************************************************/
+
+-Z@(CODE)EVTAB=80004000-8001FFFF
+-Z@(CODE)EV100=80004100-8001FFFF
+-P(CODE)EVSEG=80004000-8001FFFF
+
+/************************************************************************/
+/*      Allocate code and const segments.                               */
+/************************************************************************/
+
+-P(CODE)CODE32=80000000-8001FFFF
+-P(CONST)DATA32_C=80000000-8001FFFF
+
+// Initializers
+-Z(CONST)INITTAB,DIFUNCT=80000000-8001FFFF
+-Z(CONST)CHECKSUM,SWITCH=80000000-8001FFFF
+-Z(CONST)DATA21_ID,DATA32_ID=80000000-8001FFFF
+
+-Z(CONST)ACTAB,HTAB=80000000-8001FFFF
+
+/************************************************************************/
+/*      Allocate the read/write segments that are mapped to RAM.        */
+/************************************************************************/
+
+-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-00007FFF
+-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-00007FFF
+-Z(DATA)TRACEBUFFER=00000004-00007FFF
+
+-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-00007FFF
+-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-00007FFF
+-Z(DATA)HEAP+_HEAP_SIZE=00000004-00007FFF
+
+/************************************************************************/
+/*      End of File                                                     */
+/************************************************************************/
diff --git a/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/0256/GCC/link_uc3b0256.lds b/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/0256/GCC/link_uc3b0256.lds
new file mode 100644
index 000000000..e23901562
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/0256/GCC/link_uc3b0256.lds
@@ -0,0 +1,263 @@
+/******************************************************************************
+ * AVR32 AT32UC3B0256 GNU LD script file.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  AVR32 AT32UC3B0256
+ *
+ * - author              Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+
+OUTPUT_ARCH(avr32:uc)
+
+ENTRY(_start)
+
+MEMORY
+{
+  FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00040000
+  INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x00007FFC
+  USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200
+  FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 0x00000200
+}
+
+PHDRS
+{
+  FLASH PT_LOAD;
+  INTRAM PT_NULL;
+  USERPAGE PT_LOAD;
+  FACTORYPAGE PT_LOAD;
+}
+
+SECTIONS
+{
+  /* If this heap size is selected, all the INTRAM space from the end of the
+     data area to the beginning of the stack will be allocated for the heap. */
+  __max_heap_size__ = -1;
+
+  /* Use a default heap size if heap size was not defined. */
+  __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__;
+
+  /* Use a default stack size if stack size was not defined. */
+  __stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 4K;
+
+  /* Read-only sections, merged into text segment: */
+  PROVIDE (__executable_start = 0x80000000); . = 0x80000000;
+  .interp         : { *(.interp) } >FLASH AT>FLASH :FLASH
+  .reset : {  *(.reset) } >FLASH AT>FLASH :FLASH
+  .hash           : { *(.hash) } >FLASH AT>FLASH :FLASH
+  .dynsym         : { *(.dynsym) } >FLASH AT>FLASH :FLASH
+  .dynstr         : { *(.dynstr) } >FLASH AT>FLASH :FLASH
+  .gnu.version    : { *(.gnu.version) } >FLASH AT>FLASH :FLASH
+  .gnu.version_d  : { *(.gnu.version_d) } >FLASH AT>FLASH :FLASH
+  .gnu.version_r  : { *(.gnu.version_r) } >FLASH AT>FLASH :FLASH
+  .rel.init       : { *(.rel.init) } >FLASH AT>FLASH :FLASH
+  .rela.init      : { *(.rela.init) } >FLASH AT>FLASH :FLASH
+  .rel.text       : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH
+  .rela.text      : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH
+  .rel.fini       : { *(.rel.fini) } >FLASH AT>FLASH :FLASH
+  .rela.fini      : { *(.rela.fini) } >FLASH AT>FLASH :FLASH
+  .rel.rodata     : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
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+  .rel.data       : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH
+  .rela.data      : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH
+  .rel.tdata	  : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH
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+  .rel.tbss	  : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH
+  .rela.tbss	  : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH
+  .rel.ctors      : { *(.rel.ctors) } >FLASH AT>FLASH :FLASH
+  .rela.ctors     : { *(.rela.ctors) } >FLASH AT>FLASH :FLASH
+  .rel.dtors      : { *(.rel.dtors) } >FLASH AT>FLASH :FLASH
+  .rela.dtors     : { *(.rela.dtors) } >FLASH AT>FLASH :FLASH
+  .rel.got        : { *(.rel.got) } >FLASH AT>FLASH :FLASH
+  .rela.got       : { *(.rela.got) } >FLASH AT>FLASH :FLASH
+  .rel.bss        : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH
+  .rela.bss       : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH
+  .rel.plt        : { *(.rel.plt) } >FLASH AT>FLASH :FLASH
+  .rela.plt       : { *(.rela.plt) } >FLASH AT>FLASH :FLASH
+  .init           :
+  {
+    KEEP (*(.init))
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  .plt            : { *(.plt) } >FLASH AT>FLASH :FLASH
+  .text           :
+  {
+    *(.text .stub .text.* .gnu.linkonce.t.*)
+    KEEP (*(.text.*personality*))
+    /* .gnu.warning sections are handled specially by elf32.em.  */
+    *(.gnu.warning)
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  .fini           :
+  {
+    KEEP (*(.fini))
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
+  .rodata1        : { *(.rodata1) } >FLASH AT>FLASH :FLASH
+  .eh_frame_hdr : { *(.eh_frame_hdr) } >FLASH AT>FLASH :FLASH
+  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH :FLASH
+  .gcc_except_table   : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH :FLASH
+  .lalign	: { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH :FLASH
+  . = ORIGIN(INTRAM);
+  .dalign	: { . = ALIGN(8); PROVIDE(_data = .); } >INTRAM AT>INTRAM :INTRAM
+  /* Exception handling  */
+  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) } >INTRAM AT>FLASH :FLASH
+  .gcc_except_table   : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >INTRAM AT>FLASH :FLASH
+  /* Thread Local Storage sections  */
+  .tdata	  : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >INTRAM AT>FLASH :FLASH
+  .tbss		  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >INTRAM AT>FLASH :FLASH
+  /* Ensure the __preinit_array_start label is properly aligned.  We
+     could instead move the label definition inside the section, but
+     the linker would then create the section even if it turns out to
+     be empty, which isn't pretty.  */
+  PROVIDE (__preinit_array_start = ALIGN(32 / 8));
+  .preinit_array     : { KEEP (*(.preinit_array)) } >INTRAM AT>FLASH :FLASH
+  PROVIDE (__preinit_array_end = .);
+  PROVIDE (__init_array_start = .);
+  .init_array     : { KEEP (*(.init_array)) } >INTRAM AT>FLASH :FLASH
+  PROVIDE (__init_array_end = .);
+  PROVIDE (__fini_array_start = .);
+  .fini_array     : { KEEP (*(.fini_array)) } >INTRAM AT>FLASH :FLASH
+  PROVIDE (__fini_array_end = .);
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin*.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  } >INTRAM AT>FLASH :FLASH
+  .dtors          :
+  {
+    KEEP (*crtbegin*.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  } >INTRAM AT>FLASH :FLASH
+  .jcr            : { KEEP (*(.jcr)) } >INTRAM AT>FLASH :FLASH
+  .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >INTRAM AT>FLASH :FLASH
+  .dynamic        : { *(.dynamic) } >INTRAM AT>FLASH :FLASH
+  .got            : { *(.got.plt) *(.got) } >INTRAM AT>FLASH :FLASH
+  .data           :
+  {
+    *(.data .data.* .gnu.linkonce.d.*)
+    KEEP (*(.gnu.linkonce.d.*personality*))
+    SORT(CONSTRUCTORS)
+  } >INTRAM AT>FLASH :FLASH
+  .data1          : { *(.data1) } >INTRAM AT>FLASH :FLASH
+  .balign	: { . = ALIGN(8); _edata = .; } >INTRAM AT>FLASH :FLASH
+  _edata = .;
+  PROVIDE (edata = .);
+  __bss_start = .;
+  .bss            :
+  {
+    *(.dynbss)
+    *(.bss .bss.* .gnu.linkonce.b.*)
+    *(COMMON)
+    /* Align here to ensure that the .bss section occupies space up to
+       _end.  Align after .bss to ensure correct alignment even if the
+       .bss section disappears because there are no input sections.  */
+    . = ALIGN(8);
+  } >INTRAM AT>INTRAM :INTRAM
+  . = ALIGN(8);
+  _end = .;
+  PROVIDE (end = .);
+  __heap_start__ = ALIGN(8);
+  .heap           :
+  {
+    *(.heap)
+    . = (__heap_size__ == __max_heap_size__) ?
+        ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ - ABSOLUTE(.) :
+        __heap_size__;
+  } >INTRAM AT>INTRAM :INTRAM
+  __heap_end__ = .;
+  /* Stabs debugging sections.  */
+  .stab          0 : { *(.stab) }
+  .stabstr       0 : { *(.stabstr) }
+  .stab.excl     0 : { *(.stab.excl) }
+  .stab.exclstr  0 : { *(.stab.exclstr) }
+  .stab.index    0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  .comment       0 : { *(.comment) }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  .stack         ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ :
+  {
+    _stack = .;
+    *(.stack)
+    . = __stack_size__;
+    _estack = .;
+  } >INTRAM AT>INTRAM :INTRAM
+  .userpage       : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE :USERPAGE
+  .factorypage    : { *(.factorypage .factorypage.*) } >FACTORYPAGE AT>FACTORYPAGE :FACTORYPAGE
+  /DISCARD/ : { *(.note.GNU-stack) }
+}
diff --git a/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/0256/IAR/lnkuc3b0256.xcl b/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/0256/IAR/lnkuc3b0256.xcl
new file mode 100644
index 000000000..46fcbea95
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/0256/IAR/lnkuc3b0256.xcl
@@ -0,0 +1,138 @@
+/******************************************************************************
+ * AVR32 AT32UC3B0256 XLINK command file for AVR32 IAR C/C++ Compiler.
+ *
+ * The assumed memory layout is the one of the AT32UC3B0256:
+ *
+ *   Start       Stop        Name     Type
+ *   ----------  ----------  -----    --------------
+ *   0x00000000  0x00007FFF  SRAM     RAM
+ *   0x80000000  0x8003FFFF  FLASH    FLASH
+ *
+ * Usage:  xlink  your_file(s)  -f xcl-file  libraries
+ *
+ * - Compiler:           IAR EWAVR32
+ * - Supported devices:  AVR32 AT32UC3B0256
+ *
+ * - author              Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/************************************************************************/
+/*      The following segments are defined in this link file:           */
+/*                                                                      */
+/*      Code segments                                                   */
+/*      CODE32    -- Program code used by __code32 functions.           */
+/*      RESET     -- Reset code.                                        */
+/*      EVSEG     -- Exception vector handlers.                         */
+/*                                                                      */
+/*      Constant segments                                               */
+/*      INITTAB   -- Segment initializer table.                         */
+/*      DIFUNCT   -- Dynamic initialization vector used by C++.         */
+/*      SWITCH    -- Switch tables.                                     */
+/*      ACTAB     -- Table of pointers to acall functions.              */
+/*                                                                      */
+/*      DATA21_ID -- Initialization data for DATA21_I.                  */
+/*      DATA32_ID -- Initialization data for DATA32_I.                  */
+/*      DATA32_C  -- Constant __data32 data.                            */
+/*                                                                      */
+/*      CHECKSUM  -- Checksum segment.                                  */
+/*                                                                      */
+/*      Data segments                                                   */
+/*      DATA21_I  -- Initialized __data21 data with non-zero            */
+/*                   initial value.                                     */
+/*      DATA32_I  -- Initialized __data32 data with non-zero            */
+/*                   initial value.                                     */
+/*      DATA21_Z  -- Initialized __data21 data with zero initial value. */
+/*      DATA32_Z  -- Initialized __data32 data with zero initial value. */
+/*      DATA21_N  -- Non-initialized __data21.                          */
+/*      DATA32_N  -- Non-initialized __data32.                          */
+/*      SSTACK    -- The system stack.                                  */
+/*      CSTACK    -- The application stack.                             */
+/*      HEAP      -- The heap used by malloc and free.                  */
+/*                                                                      */
+/************************************************************************/
+
+/************************************************************************/
+/*      Define CPU                                                      */
+/************************************************************************/
+
+-cavr32
+
+// Declare the IPR0 memory location
+-DIPR0=FFFF0800
+
+/************************************************************************/
+/*      Reset code is located at address 0x80000000 and up.             */
+/************************************************************************/
+
+-Z(CODE)RESET=80000000-8003FFFF
+
+/************************************************************************/
+/*      The exception handler code is located at address 0x80000000     */
+/*      and up. Make sure that the exception table gets properly        */
+/*      allocated. By using the special -Z@ allocation primitive, the   */
+/*      placement is guaranteed to be at _EVBASE and onwards.           */
+/************************************************************************/
+
+-Z@(CODE)EVTAB=80004000-8003FFFF
+-Z@(CODE)EV100=80004100-8003FFFF
+-P(CODE)EVSEG=80004000-8003FFFF
+
+/************************************************************************/
+/*      Allocate code and const segments.                               */
+/************************************************************************/
+
+-P(CODE)CODE32=80000000-8003FFFF
+-P(CONST)DATA32_C=80000000-8003FFFF
+
+// Initializers
+-Z(CONST)INITTAB,DIFUNCT=80000000-8003FFFF
+-Z(CONST)CHECKSUM,SWITCH=80000000-8003FFFF
+-Z(CONST)DATA21_ID,DATA32_ID=80000000-8003FFFF
+
+-Z(CONST)ACTAB,HTAB=80000000-8003FFFF
+
+/************************************************************************/
+/*      Allocate the read/write segments that are mapped to RAM.        */
+/************************************************************************/
+
+-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-00007FFF
+-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-00007FFF
+-Z(DATA)TRACEBUFFER=00000004-00007FFF
+
+-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-00007FFF
+-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-00007FFF
+-Z(DATA)HEAP+_HEAP_SIZE=00000004-00007FFF
+
+/************************************************************************/
+/*      End of File                                                     */
+/************************************************************************/
diff --git a/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/064/GCC/link_uc3b064.lds b/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/064/GCC/link_uc3b064.lds
new file mode 100644
index 000000000..579a3908c
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/064/GCC/link_uc3b064.lds
@@ -0,0 +1,263 @@
+/******************************************************************************
+ * AVR32 AT32UC3B064 GNU LD script file.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  AVR32 AT32UC3B064
+ *
+ * - author              Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+
+OUTPUT_ARCH(avr32:uc)
+
+ENTRY(_start)
+
+MEMORY
+{
+  FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00010000
+  INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x00003FFC
+  USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200
+  FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 0x00000200
+}
+
+PHDRS
+{
+  FLASH PT_LOAD;
+  INTRAM PT_NULL;
+  USERPAGE PT_LOAD;
+  FACTORYPAGE PT_LOAD;
+}
+
+SECTIONS
+{
+  /* If this heap size is selected, all the INTRAM space from the end of the
+     data area to the beginning of the stack will be allocated for the heap. */
+  __max_heap_size__ = -1;
+
+  /* Use a default heap size if heap size was not defined. */
+  __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__;
+
+  /* Use a default stack size if stack size was not defined. */
+  __stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 4K;
+
+  /* Read-only sections, merged into text segment: */
+  PROVIDE (__executable_start = 0x80000000); . = 0x80000000;
+  .interp         : { *(.interp) } >FLASH AT>FLASH :FLASH
+  .reset : {  *(.reset) } >FLASH AT>FLASH :FLASH
+  .hash           : { *(.hash) } >FLASH AT>FLASH :FLASH
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+  .gnu.version    : { *(.gnu.version) } >FLASH AT>FLASH :FLASH
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+  .gnu.version_r  : { *(.gnu.version_r) } >FLASH AT>FLASH :FLASH
+  .rel.init       : { *(.rel.init) } >FLASH AT>FLASH :FLASH
+  .rela.init      : { *(.rela.init) } >FLASH AT>FLASH :FLASH
+  .rel.text       : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH
+  .rela.text      : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH
+  .rel.fini       : { *(.rel.fini) } >FLASH AT>FLASH :FLASH
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+  .rel.rodata     : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
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+  .rela.plt       : { *(.rela.plt) } >FLASH AT>FLASH :FLASH
+  .init           :
+  {
+    KEEP (*(.init))
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  .plt            : { *(.plt) } >FLASH AT>FLASH :FLASH
+  .text           :
+  {
+    *(.text .stub .text.* .gnu.linkonce.t.*)
+    KEEP (*(.text.*personality*))
+    /* .gnu.warning sections are handled specially by elf32.em.  */
+    *(.gnu.warning)
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+  .fini           :
+  {
+    KEEP (*(.fini))
+  } >FLASH AT>FLASH :FLASH =0xd703d703
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+  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH :FLASH
+  .gcc_except_table   : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH :FLASH
+  .lalign	: { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH :FLASH
+  . = ORIGIN(INTRAM);
+  .dalign	: { . = ALIGN(8); PROVIDE(_data = .); } >INTRAM AT>INTRAM :INTRAM
+  /* Exception handling  */
+  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) } >INTRAM AT>FLASH :FLASH
+  .gcc_except_table   : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >INTRAM AT>FLASH :FLASH
+  /* Thread Local Storage sections  */
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+  .tbss		  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >INTRAM AT>FLASH :FLASH
+  /* Ensure the __preinit_array_start label is properly aligned.  We
+     could instead move the label definition inside the section, but
+     the linker would then create the section even if it turns out to
+     be empty, which isn't pretty.  */
+  PROVIDE (__preinit_array_start = ALIGN(32 / 8));
+  .preinit_array     : { KEEP (*(.preinit_array)) } >INTRAM AT>FLASH :FLASH
+  PROVIDE (__preinit_array_end = .);
+  PROVIDE (__init_array_start = .);
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+  PROVIDE (__init_array_end = .);
+  PROVIDE (__fini_array_start = .);
+  .fini_array     : { KEEP (*(.fini_array)) } >INTRAM AT>FLASH :FLASH
+  PROVIDE (__fini_array_end = .);
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin*.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  } >INTRAM AT>FLASH :FLASH
+  .dtors          :
+  {
+    KEEP (*crtbegin*.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  } >INTRAM AT>FLASH :FLASH
+  .jcr            : { KEEP (*(.jcr)) } >INTRAM AT>FLASH :FLASH
+  .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >INTRAM AT>FLASH :FLASH
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+  .got            : { *(.got.plt) *(.got) } >INTRAM AT>FLASH :FLASH
+  .data           :
+  {
+    *(.data .data.* .gnu.linkonce.d.*)
+    KEEP (*(.gnu.linkonce.d.*personality*))
+    SORT(CONSTRUCTORS)
+  } >INTRAM AT>FLASH :FLASH
+  .data1          : { *(.data1) } >INTRAM AT>FLASH :FLASH
+  .balign	: { . = ALIGN(8); _edata = .; } >INTRAM AT>FLASH :FLASH
+  _edata = .;
+  PROVIDE (edata = .);
+  __bss_start = .;
+  .bss            :
+  {
+    *(.dynbss)
+    *(.bss .bss.* .gnu.linkonce.b.*)
+    *(COMMON)
+    /* Align here to ensure that the .bss section occupies space up to
+       _end.  Align after .bss to ensure correct alignment even if the
+       .bss section disappears because there are no input sections.  */
+    . = ALIGN(8);
+  } >INTRAM AT>INTRAM :INTRAM
+  . = ALIGN(8);
+  _end = .;
+  PROVIDE (end = .);
+  __heap_start__ = ALIGN(8);
+  .heap           :
+  {
+    *(.heap)
+    . = (__heap_size__ == __max_heap_size__) ?
+        ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ - ABSOLUTE(.) :
+        __heap_size__;
+  } >INTRAM AT>INTRAM :INTRAM
+  __heap_end__ = .;
+  /* Stabs debugging sections.  */
+  .stab          0 : { *(.stab) }
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+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  .comment       0 : { *(.comment) }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
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+  /* DWARF 1.1 and DWARF 2 */
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+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  .stack         ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ :
+  {
+    _stack = .;
+    *(.stack)
+    . = __stack_size__;
+    _estack = .;
+  } >INTRAM AT>INTRAM :INTRAM
+  .userpage       : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE :USERPAGE
+  .factorypage    : { *(.factorypage .factorypage.*) } >FACTORYPAGE AT>FACTORYPAGE :FACTORYPAGE
+  /DISCARD/ : { *(.note.GNU-stack) }
+}
diff --git a/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/064/IAR/lnkuc3b064.xcl b/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/064/IAR/lnkuc3b064.xcl
new file mode 100644
index 000000000..ab7b2ee17
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/064/IAR/lnkuc3b064.xcl
@@ -0,0 +1,138 @@
+/******************************************************************************
+ * AVR32 AT32UC3B064 XLINK command file for AVR32 IAR C/C++ Compiler.
+ *
+ * The assumed memory layout is the one of the AT32UC3B064:
+ *
+ *   Start       Stop        Name     Type
+ *   ----------  ----------  -----    --------------
+ *   0x00000000  0x00003FFF  SRAM     RAM
+ *   0x80000000  0x8000FFFF  FLASH    FLASH
+ *
+ * Usage:  xlink  your_file(s)  -f xcl-file  libraries
+ *
+ * - Compiler:           IAR EWAVR32
+ * - Supported devices:  AVR32 AT32UC3B064
+ *
+ * - author              Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/************************************************************************/
+/*      The following segments are defined in this link file:           */
+/*                                                                      */
+/*      Code segments                                                   */
+/*      CODE32    -- Program code used by __code32 functions.           */
+/*      RESET     -- Reset code.                                        */
+/*      EVSEG     -- Exception vector handlers.                         */
+/*                                                                      */
+/*      Constant segments                                               */
+/*      INITTAB   -- Segment initializer table.                         */
+/*      DIFUNCT   -- Dynamic initialization vector used by C++.         */
+/*      SWITCH    -- Switch tables.                                     */
+/*      ACTAB     -- Table of pointers to acall functions.              */
+/*                                                                      */
+/*      DATA21_ID -- Initialization data for DATA21_I.                  */
+/*      DATA32_ID -- Initialization data for DATA32_I.                  */
+/*      DATA32_C  -- Constant __data32 data.                            */
+/*                                                                      */
+/*      CHECKSUM  -- Checksum segment.                                  */
+/*                                                                      */
+/*      Data segments                                                   */
+/*      DATA21_I  -- Initialized __data21 data with non-zero            */
+/*                   initial value.                                     */
+/*      DATA32_I  -- Initialized __data32 data with non-zero            */
+/*                   initial value.                                     */
+/*      DATA21_Z  -- Initialized __data21 data with zero initial value. */
+/*      DATA32_Z  -- Initialized __data32 data with zero initial value. */
+/*      DATA21_N  -- Non-initialized __data21.                          */
+/*      DATA32_N  -- Non-initialized __data32.                          */
+/*      SSTACK    -- The system stack.                                  */
+/*      CSTACK    -- The application stack.                             */
+/*      HEAP      -- The heap used by malloc and free.                  */
+/*                                                                      */
+/************************************************************************/
+
+/************************************************************************/
+/*      Define CPU                                                      */
+/************************************************************************/
+
+-cavr32
+
+// Declare the IPR0 memory location
+-DIPR0=FFFF0800
+
+/************************************************************************/
+/*      Reset code is located at address 0x80000000 and up.             */
+/************************************************************************/
+
+-Z(CODE)RESET=80000000-8000FFFF
+
+/************************************************************************/
+/*      The exception handler code is located at address 0x80000000     */
+/*      and up. Make sure that the exception table gets properly        */
+/*      allocated. By using the special -Z@ allocation primitive, the   */
+/*      placement is guaranteed to be at _EVBASE and onwards.           */
+/************************************************************************/
+
+-Z@(CODE)EVTAB=80004000-8000FFFF
+-Z@(CODE)EV100=80004100-8000FFFF
+-P(CODE)EVSEG=80004000-8000FFFF
+
+/************************************************************************/
+/*      Allocate code and const segments.                               */
+/************************************************************************/
+
+-P(CODE)CODE32=80000000-8000FFFF
+-P(CONST)DATA32_C=80000000-8000FFFF
+
+// Initializers
+-Z(CONST)INITTAB,DIFUNCT=80000000-8000FFFF
+-Z(CONST)CHECKSUM,SWITCH=80000000-8000FFFF
+-Z(CONST)DATA21_ID,DATA32_ID=80000000-8000FFFF
+
+-Z(CONST)ACTAB,HTAB=80000000-8000FFFF
+
+/************************************************************************/
+/*      Allocate the read/write segments that are mapped to RAM.        */
+/************************************************************************/
+
+-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-00003FFF
+-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-00003FFF
+-Z(DATA)TRACEBUFFER=00000004-00003FFF
+
+-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-00003FFF
+-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-00003FFF
+-Z(DATA)HEAP+_HEAP_SIZE=00000004-00003FFF
+
+/************************************************************************/
+/*      End of File                                                     */
+/************************************************************************/
diff --git a/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/1128/GCC/link_uc3b1128.lds b/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/1128/GCC/link_uc3b1128.lds
new file mode 100644
index 000000000..dba3d8df4
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/1128/GCC/link_uc3b1128.lds
@@ -0,0 +1,263 @@
+/******************************************************************************
+ * AVR32 AT32UC3B1128 GNU LD script file.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  AVR32 AT32UC3B1128
+ *
+ * - author              Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+
+OUTPUT_ARCH(avr32:uc)
+
+ENTRY(_start)
+
+MEMORY
+{
+  FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00020000
+  INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x00007FFC
+  USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200
+  FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 0x00000200
+}
+
+PHDRS
+{
+  FLASH PT_LOAD;
+  INTRAM PT_NULL;
+  USERPAGE PT_LOAD;
+  FACTORYPAGE PT_LOAD;
+}
+
+SECTIONS
+{
+  /* If this heap size is selected, all the INTRAM space from the end of the
+     data area to the beginning of the stack will be allocated for the heap. */
+  __max_heap_size__ = -1;
+
+  /* Use a default heap size if heap size was not defined. */
+  __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__;
+
+  /* Use a default stack size if stack size was not defined. */
+  __stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 4K;
+
+  /* Read-only sections, merged into text segment: */
+  PROVIDE (__executable_start = 0x80000000); . = 0x80000000;
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+  .rela.plt       : { *(.rela.plt) } >FLASH AT>FLASH :FLASH
+  .init           :
+  {
+    KEEP (*(.init))
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  .plt            : { *(.plt) } >FLASH AT>FLASH :FLASH
+  .text           :
+  {
+    *(.text .stub .text.* .gnu.linkonce.t.*)
+    KEEP (*(.text.*personality*))
+    /* .gnu.warning sections are handled specially by elf32.em.  */
+    *(.gnu.warning)
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  .fini           :
+  {
+    KEEP (*(.fini))
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
+  .rodata1        : { *(.rodata1) } >FLASH AT>FLASH :FLASH
+  .eh_frame_hdr : { *(.eh_frame_hdr) } >FLASH AT>FLASH :FLASH
+  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH :FLASH
+  .gcc_except_table   : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH :FLASH
+  .lalign	: { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH :FLASH
+  . = ORIGIN(INTRAM);
+  .dalign	: { . = ALIGN(8); PROVIDE(_data = .); } >INTRAM AT>INTRAM :INTRAM
+  /* Exception handling  */
+  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) } >INTRAM AT>FLASH :FLASH
+  .gcc_except_table   : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >INTRAM AT>FLASH :FLASH
+  /* Thread Local Storage sections  */
+  .tdata	  : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >INTRAM AT>FLASH :FLASH
+  .tbss		  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >INTRAM AT>FLASH :FLASH
+  /* Ensure the __preinit_array_start label is properly aligned.  We
+     could instead move the label definition inside the section, but
+     the linker would then create the section even if it turns out to
+     be empty, which isn't pretty.  */
+  PROVIDE (__preinit_array_start = ALIGN(32 / 8));
+  .preinit_array     : { KEEP (*(.preinit_array)) } >INTRAM AT>FLASH :FLASH
+  PROVIDE (__preinit_array_end = .);
+  PROVIDE (__init_array_start = .);
+  .init_array     : { KEEP (*(.init_array)) } >INTRAM AT>FLASH :FLASH
+  PROVIDE (__init_array_end = .);
+  PROVIDE (__fini_array_start = .);
+  .fini_array     : { KEEP (*(.fini_array)) } >INTRAM AT>FLASH :FLASH
+  PROVIDE (__fini_array_end = .);
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin*.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  } >INTRAM AT>FLASH :FLASH
+  .dtors          :
+  {
+    KEEP (*crtbegin*.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  } >INTRAM AT>FLASH :FLASH
+  .jcr            : { KEEP (*(.jcr)) } >INTRAM AT>FLASH :FLASH
+  .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >INTRAM AT>FLASH :FLASH
+  .dynamic        : { *(.dynamic) } >INTRAM AT>FLASH :FLASH
+  .got            : { *(.got.plt) *(.got) } >INTRAM AT>FLASH :FLASH
+  .data           :
+  {
+    *(.data .data.* .gnu.linkonce.d.*)
+    KEEP (*(.gnu.linkonce.d.*personality*))
+    SORT(CONSTRUCTORS)
+  } >INTRAM AT>FLASH :FLASH
+  .data1          : { *(.data1) } >INTRAM AT>FLASH :FLASH
+  .balign	: { . = ALIGN(8); _edata = .; } >INTRAM AT>FLASH :FLASH
+  _edata = .;
+  PROVIDE (edata = .);
+  __bss_start = .;
+  .bss            :
+  {
+    *(.dynbss)
+    *(.bss .bss.* .gnu.linkonce.b.*)
+    *(COMMON)
+    /* Align here to ensure that the .bss section occupies space up to
+       _end.  Align after .bss to ensure correct alignment even if the
+       .bss section disappears because there are no input sections.  */
+    . = ALIGN(8);
+  } >INTRAM AT>INTRAM :INTRAM
+  . = ALIGN(8);
+  _end = .;
+  PROVIDE (end = .);
+  __heap_start__ = ALIGN(8);
+  .heap           :
+  {
+    *(.heap)
+    . = (__heap_size__ == __max_heap_size__) ?
+        ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ - ABSOLUTE(.) :
+        __heap_size__;
+  } >INTRAM AT>INTRAM :INTRAM
+  __heap_end__ = .;
+  /* Stabs debugging sections.  */
+  .stab          0 : { *(.stab) }
+  .stabstr       0 : { *(.stabstr) }
+  .stab.excl     0 : { *(.stab.excl) }
+  .stab.exclstr  0 : { *(.stab.exclstr) }
+  .stab.index    0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  .comment       0 : { *(.comment) }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  .stack         ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ :
+  {
+    _stack = .;
+    *(.stack)
+    . = __stack_size__;
+    _estack = .;
+  } >INTRAM AT>INTRAM :INTRAM
+  .userpage       : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE :USERPAGE
+  .factorypage    : { *(.factorypage .factorypage.*) } >FACTORYPAGE AT>FACTORYPAGE :FACTORYPAGE
+  /DISCARD/ : { *(.note.GNU-stack) }
+}
diff --git a/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/1128/IAR/lnkuc3b1128.xcl b/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/1128/IAR/lnkuc3b1128.xcl
new file mode 100644
index 000000000..4d50bc137
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/1128/IAR/lnkuc3b1128.xcl
@@ -0,0 +1,138 @@
+/******************************************************************************
+ * AVR32 AT32UC3B1128 XLINK command file for AVR32 IAR C/C++ Compiler.
+ *
+ * The assumed memory layout is the one of the AT32UC3B1128:
+ *
+ *   Start       Stop        Name     Type
+ *   ----------  ----------  -----    --------------
+ *   0x00000000  0x00007FFF  SRAM     RAM
+ *   0x80000000  0x8001FFFF  FLASH    FLASH
+ *
+ * Usage:  xlink  your_file(s)  -f xcl-file  libraries
+ *
+ * - Compiler:           IAR EWAVR32
+ * - Supported devices:  AVR32 AT32UC3B1128
+ *
+ * - author              Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/************************************************************************/
+/*      The following segments are defined in this link file:           */
+/*                                                                      */
+/*      Code segments                                                   */
+/*      CODE32    -- Program code used by __code32 functions.           */
+/*      RESET     -- Reset code.                                        */
+/*      EVSEG     -- Exception vector handlers.                         */
+/*                                                                      */
+/*      Constant segments                                               */
+/*      INITTAB   -- Segment initializer table.                         */
+/*      DIFUNCT   -- Dynamic initialization vector used by C++.         */
+/*      SWITCH    -- Switch tables.                                     */
+/*      ACTAB     -- Table of pointers to acall functions.              */
+/*                                                                      */
+/*      DATA21_ID -- Initialization data for DATA21_I.                  */
+/*      DATA32_ID -- Initialization data for DATA32_I.                  */
+/*      DATA32_C  -- Constant __data32 data.                            */
+/*                                                                      */
+/*      CHECKSUM  -- Checksum segment.                                  */
+/*                                                                      */
+/*      Data segments                                                   */
+/*      DATA21_I  -- Initialized __data21 data with non-zero            */
+/*                   initial value.                                     */
+/*      DATA32_I  -- Initialized __data32 data with non-zero            */
+/*                   initial value.                                     */
+/*      DATA21_Z  -- Initialized __data21 data with zero initial value. */
+/*      DATA32_Z  -- Initialized __data32 data with zero initial value. */
+/*      DATA21_N  -- Non-initialized __data21.                          */
+/*      DATA32_N  -- Non-initialized __data32.                          */
+/*      SSTACK    -- The system stack.                                  */
+/*      CSTACK    -- The application stack.                             */
+/*      HEAP      -- The heap used by malloc and free.                  */
+/*                                                                      */
+/************************************************************************/
+
+/************************************************************************/
+/*      Define CPU                                                      */
+/************************************************************************/
+
+-cavr32
+
+// Declare the IPR0 memory location
+-DIPR0=FFFF0800
+
+/************************************************************************/
+/*      Reset code is located at address 0x80000000 and up.             */
+/************************************************************************/
+
+-Z(CODE)RESET=80000000-8001FFFF
+
+/************************************************************************/
+/*      The exception handler code is located at address 0x80000000     */
+/*      and up. Make sure that the exception table gets properly        */
+/*      allocated. By using the special -Z@ allocation primitive, the   */
+/*      placement is guaranteed to be at _EVBASE and onwards.           */
+/************************************************************************/
+
+-Z@(CODE)EVTAB=80004000-8001FFFF
+-Z@(CODE)EV100=80004100-8001FFFF
+-P(CODE)EVSEG=80004000-8001FFFF
+
+/************************************************************************/
+/*      Allocate code and const segments.                               */
+/************************************************************************/
+
+-P(CODE)CODE32=80000000-8001FFFF
+-P(CONST)DATA32_C=80000000-8001FFFF
+
+// Initializers
+-Z(CONST)INITTAB,DIFUNCT=80000000-8001FFFF
+-Z(CONST)CHECKSUM,SWITCH=80000000-8001FFFF
+-Z(CONST)DATA21_ID,DATA32_ID=80000000-8001FFFF
+
+-Z(CONST)ACTAB,HTAB=80000000-8001FFFF
+
+/************************************************************************/
+/*      Allocate the read/write segments that are mapped to RAM.        */
+/************************************************************************/
+
+-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-00007FFF
+-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-00007FFF
+-Z(DATA)TRACEBUFFER=00000004-00007FFF
+
+-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-00007FFF
+-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-00007FFF
+-Z(DATA)HEAP+_HEAP_SIZE=00000004-00007FFF
+
+/************************************************************************/
+/*      End of File                                                     */
+/************************************************************************/
diff --git a/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/1256/GCC/link_uc3b1256.lds b/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/1256/GCC/link_uc3b1256.lds
new file mode 100644
index 000000000..619a159a1
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/1256/GCC/link_uc3b1256.lds
@@ -0,0 +1,263 @@
+/******************************************************************************
+ * AVR32 AT32UC3B1256 GNU LD script file.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  AVR32 AT32UC3B1256
+ *
+ * - author              Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+
+OUTPUT_ARCH(avr32:uc)
+
+ENTRY(_start)
+
+MEMORY
+{
+  FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00040000
+  INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x00007FFC
+  USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200
+  FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 0x00000200
+}
+
+PHDRS
+{
+  FLASH PT_LOAD;
+  INTRAM PT_NULL;
+  USERPAGE PT_LOAD;
+  FACTORYPAGE PT_LOAD;
+}
+
+SECTIONS
+{
+  /* If this heap size is selected, all the INTRAM space from the end of the
+     data area to the beginning of the stack will be allocated for the heap. */
+  __max_heap_size__ = -1;
+
+  /* Use a default heap size if heap size was not defined. */
+  __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__;
+
+  /* Use a default stack size if stack size was not defined. */
+  __stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 4K;
+
+  /* Read-only sections, merged into text segment: */
+  PROVIDE (__executable_start = 0x80000000); . = 0x80000000;
+  .interp         : { *(.interp) } >FLASH AT>FLASH :FLASH
+  .reset : {  *(.reset) } >FLASH AT>FLASH :FLASH
+  .hash           : { *(.hash) } >FLASH AT>FLASH :FLASH
+  .dynsym         : { *(.dynsym) } >FLASH AT>FLASH :FLASH
+  .dynstr         : { *(.dynstr) } >FLASH AT>FLASH :FLASH
+  .gnu.version    : { *(.gnu.version) } >FLASH AT>FLASH :FLASH
+  .gnu.version_d  : { *(.gnu.version_d) } >FLASH AT>FLASH :FLASH
+  .gnu.version_r  : { *(.gnu.version_r) } >FLASH AT>FLASH :FLASH
+  .rel.init       : { *(.rel.init) } >FLASH AT>FLASH :FLASH
+  .rela.init      : { *(.rela.init) } >FLASH AT>FLASH :FLASH
+  .rel.text       : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH
+  .rela.text      : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH
+  .rel.fini       : { *(.rel.fini) } >FLASH AT>FLASH :FLASH
+  .rela.fini      : { *(.rela.fini) } >FLASH AT>FLASH :FLASH
+  .rel.rodata     : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
+  .rela.rodata    : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
+  .rel.data.rel.ro   : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH
+  .rela.data.rel.ro   : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH
+  .rel.data       : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH
+  .rela.data      : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH
+  .rel.tdata	  : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH
+  .rela.tdata	  : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH
+  .rel.tbss	  : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH
+  .rela.tbss	  : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH
+  .rel.ctors      : { *(.rel.ctors) } >FLASH AT>FLASH :FLASH
+  .rela.ctors     : { *(.rela.ctors) } >FLASH AT>FLASH :FLASH
+  .rel.dtors      : { *(.rel.dtors) } >FLASH AT>FLASH :FLASH
+  .rela.dtors     : { *(.rela.dtors) } >FLASH AT>FLASH :FLASH
+  .rel.got        : { *(.rel.got) } >FLASH AT>FLASH :FLASH
+  .rela.got       : { *(.rela.got) } >FLASH AT>FLASH :FLASH
+  .rel.bss        : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH
+  .rela.bss       : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH
+  .rel.plt        : { *(.rel.plt) } >FLASH AT>FLASH :FLASH
+  .rela.plt       : { *(.rela.plt) } >FLASH AT>FLASH :FLASH
+  .init           :
+  {
+    KEEP (*(.init))
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  .plt            : { *(.plt) } >FLASH AT>FLASH :FLASH
+  .text           :
+  {
+    *(.text .stub .text.* .gnu.linkonce.t.*)
+    KEEP (*(.text.*personality*))
+    /* .gnu.warning sections are handled specially by elf32.em.  */
+    *(.gnu.warning)
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  .fini           :
+  {
+    KEEP (*(.fini))
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
+  .rodata1        : { *(.rodata1) } >FLASH AT>FLASH :FLASH
+  .eh_frame_hdr : { *(.eh_frame_hdr) } >FLASH AT>FLASH :FLASH
+  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH :FLASH
+  .gcc_except_table   : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH :FLASH
+  .lalign	: { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH :FLASH
+  . = ORIGIN(INTRAM);
+  .dalign	: { . = ALIGN(8); PROVIDE(_data = .); } >INTRAM AT>INTRAM :INTRAM
+  /* Exception handling  */
+  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) } >INTRAM AT>FLASH :FLASH
+  .gcc_except_table   : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >INTRAM AT>FLASH :FLASH
+  /* Thread Local Storage sections  */
+  .tdata	  : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >INTRAM AT>FLASH :FLASH
+  .tbss		  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >INTRAM AT>FLASH :FLASH
+  /* Ensure the __preinit_array_start label is properly aligned.  We
+     could instead move the label definition inside the section, but
+     the linker would then create the section even if it turns out to
+     be empty, which isn't pretty.  */
+  PROVIDE (__preinit_array_start = ALIGN(32 / 8));
+  .preinit_array     : { KEEP (*(.preinit_array)) } >INTRAM AT>FLASH :FLASH
+  PROVIDE (__preinit_array_end = .);
+  PROVIDE (__init_array_start = .);
+  .init_array     : { KEEP (*(.init_array)) } >INTRAM AT>FLASH :FLASH
+  PROVIDE (__init_array_end = .);
+  PROVIDE (__fini_array_start = .);
+  .fini_array     : { KEEP (*(.fini_array)) } >INTRAM AT>FLASH :FLASH
+  PROVIDE (__fini_array_end = .);
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin*.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  } >INTRAM AT>FLASH :FLASH
+  .dtors          :
+  {
+    KEEP (*crtbegin*.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  } >INTRAM AT>FLASH :FLASH
+  .jcr            : { KEEP (*(.jcr)) } >INTRAM AT>FLASH :FLASH
+  .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >INTRAM AT>FLASH :FLASH
+  .dynamic        : { *(.dynamic) } >INTRAM AT>FLASH :FLASH
+  .got            : { *(.got.plt) *(.got) } >INTRAM AT>FLASH :FLASH
+  .data           :
+  {
+    *(.data .data.* .gnu.linkonce.d.*)
+    KEEP (*(.gnu.linkonce.d.*personality*))
+    SORT(CONSTRUCTORS)
+  } >INTRAM AT>FLASH :FLASH
+  .data1          : { *(.data1) } >INTRAM AT>FLASH :FLASH
+  .balign	: { . = ALIGN(8); _edata = .; } >INTRAM AT>FLASH :FLASH
+  _edata = .;
+  PROVIDE (edata = .);
+  __bss_start = .;
+  .bss            :
+  {
+    *(.dynbss)
+    *(.bss .bss.* .gnu.linkonce.b.*)
+    *(COMMON)
+    /* Align here to ensure that the .bss section occupies space up to
+       _end.  Align after .bss to ensure correct alignment even if the
+       .bss section disappears because there are no input sections.  */
+    . = ALIGN(8);
+  } >INTRAM AT>INTRAM :INTRAM
+  . = ALIGN(8);
+  _end = .;
+  PROVIDE (end = .);
+  __heap_start__ = ALIGN(8);
+  .heap           :
+  {
+    *(.heap)
+    . = (__heap_size__ == __max_heap_size__) ?
+        ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ - ABSOLUTE(.) :
+        __heap_size__;
+  } >INTRAM AT>INTRAM :INTRAM
+  __heap_end__ = .;
+  /* Stabs debugging sections.  */
+  .stab          0 : { *(.stab) }
+  .stabstr       0 : { *(.stabstr) }
+  .stab.excl     0 : { *(.stab.excl) }
+  .stab.exclstr  0 : { *(.stab.exclstr) }
+  .stab.index    0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  .comment       0 : { *(.comment) }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  .stack         ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ :
+  {
+    _stack = .;
+    *(.stack)
+    . = __stack_size__;
+    _estack = .;
+  } >INTRAM AT>INTRAM :INTRAM
+  .userpage       : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE :USERPAGE
+  .factorypage    : { *(.factorypage .factorypage.*) } >FACTORYPAGE AT>FACTORYPAGE :FACTORYPAGE
+  /DISCARD/ : { *(.note.GNU-stack) }
+}
diff --git a/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/1256/IAR/lnkuc3b1256.xcl b/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/1256/IAR/lnkuc3b1256.xcl
new file mode 100644
index 000000000..f765e4e9c
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/1256/IAR/lnkuc3b1256.xcl
@@ -0,0 +1,138 @@
+/******************************************************************************
+ * AVR32 AT32UC3B1256 XLINK command file for AVR32 IAR C/C++ Compiler.
+ *
+ * The assumed memory layout is the one of the AT32UC3B1256:
+ *
+ *   Start       Stop        Name     Type
+ *   ----------  ----------  -----    --------------
+ *   0x00000000  0x00007FFF  SRAM     RAM
+ *   0x80000000  0x8003FFFF  FLASH    FLASH
+ *
+ * Usage:  xlink  your_file(s)  -f xcl-file  libraries
+ *
+ * - Compiler:           IAR EWAVR32
+ * - Supported devices:  AVR32 AT32UC3B1256
+ *
+ * - author              Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/************************************************************************/
+/*      The following segments are defined in this link file:           */
+/*                                                                      */
+/*      Code segments                                                   */
+/*      CODE32    -- Program code used by __code32 functions.           */
+/*      RESET     -- Reset code.                                        */
+/*      EVSEG     -- Exception vector handlers.                         */
+/*                                                                      */
+/*      Constant segments                                               */
+/*      INITTAB   -- Segment initializer table.                         */
+/*      DIFUNCT   -- Dynamic initialization vector used by C++.         */
+/*      SWITCH    -- Switch tables.                                     */
+/*      ACTAB     -- Table of pointers to acall functions.              */
+/*                                                                      */
+/*      DATA21_ID -- Initialization data for DATA21_I.                  */
+/*      DATA32_ID -- Initialization data for DATA32_I.                  */
+/*      DATA32_C  -- Constant __data32 data.                            */
+/*                                                                      */
+/*      CHECKSUM  -- Checksum segment.                                  */
+/*                                                                      */
+/*      Data segments                                                   */
+/*      DATA21_I  -- Initialized __data21 data with non-zero            */
+/*                   initial value.                                     */
+/*      DATA32_I  -- Initialized __data32 data with non-zero            */
+/*                   initial value.                                     */
+/*      DATA21_Z  -- Initialized __data21 data with zero initial value. */
+/*      DATA32_Z  -- Initialized __data32 data with zero initial value. */
+/*      DATA21_N  -- Non-initialized __data21.                          */
+/*      DATA32_N  -- Non-initialized __data32.                          */
+/*      SSTACK    -- The system stack.                                  */
+/*      CSTACK    -- The application stack.                             */
+/*      HEAP      -- The heap used by malloc and free.                  */
+/*                                                                      */
+/************************************************************************/
+
+/************************************************************************/
+/*      Define CPU                                                      */
+/************************************************************************/
+
+-cavr32
+
+// Declare the IPR0 memory location
+-DIPR0=FFFF0800
+
+/************************************************************************/
+/*      Reset code is located at address 0x80000000 and up.             */
+/************************************************************************/
+
+-Z(CODE)RESET=80000000-8003FFFF
+
+/************************************************************************/
+/*      The exception handler code is located at address 0x80000000     */
+/*      and up. Make sure that the exception table gets properly        */
+/*      allocated. By using the special -Z@ allocation primitive, the   */
+/*      placement is guaranteed to be at _EVBASE and onwards.           */
+/************************************************************************/
+
+-Z@(CODE)EVTAB=80004000-8003FFFF
+-Z@(CODE)EV100=80004100-8003FFFF
+-P(CODE)EVSEG=80004000-8003FFFF
+
+/************************************************************************/
+/*      Allocate code and const segments.                               */
+/************************************************************************/
+
+-P(CODE)CODE32=80000000-8003FFFF
+-P(CONST)DATA32_C=80000000-8003FFFF
+
+// Initializers
+-Z(CONST)INITTAB,DIFUNCT=80000000-8003FFFF
+-Z(CONST)CHECKSUM,SWITCH=80000000-8003FFFF
+-Z(CONST)DATA21_ID,DATA32_ID=80000000-8003FFFF
+
+-Z(CONST)ACTAB,HTAB=80000000-8003FFFF
+
+/************************************************************************/
+/*      Allocate the read/write segments that are mapped to RAM.        */
+/************************************************************************/
+
+-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-00007FFF
+-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-00007FFF
+-Z(DATA)TRACEBUFFER=00000004-00007FFF
+
+-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-00007FFF
+-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-00007FFF
+-Z(DATA)HEAP+_HEAP_SIZE=00000004-00007FFF
+
+/************************************************************************/
+/*      End of File                                                     */
+/************************************************************************/
diff --git a/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/164/GCC/link_uc3b164.lds b/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/164/GCC/link_uc3b164.lds
new file mode 100644
index 000000000..cae225d89
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/164/GCC/link_uc3b164.lds
@@ -0,0 +1,263 @@
+/******************************************************************************
+ * AVR32 AT32UC3B164 GNU LD script file.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  AVR32 AT32UC3B164
+ *
+ * - author              Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+
+OUTPUT_ARCH(avr32:uc)
+
+ENTRY(_start)
+
+MEMORY
+{
+  FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00010000
+  INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x00003FFC
+  USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200
+  FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 0x00000200
+}
+
+PHDRS
+{
+  FLASH PT_LOAD;
+  INTRAM PT_NULL;
+  USERPAGE PT_LOAD;
+  FACTORYPAGE PT_LOAD;
+}
+
+SECTIONS
+{
+  /* If this heap size is selected, all the INTRAM space from the end of the
+     data area to the beginning of the stack will be allocated for the heap. */
+  __max_heap_size__ = -1;
+
+  /* Use a default heap size if heap size was not defined. */
+  __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__;
+
+  /* Use a default stack size if stack size was not defined. */
+  __stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 4K;
+
+  /* Read-only sections, merged into text segment: */
+  PROVIDE (__executable_start = 0x80000000); . = 0x80000000;
+  .interp         : { *(.interp) } >FLASH AT>FLASH :FLASH
+  .reset : {  *(.reset) } >FLASH AT>FLASH :FLASH
+  .hash           : { *(.hash) } >FLASH AT>FLASH :FLASH
+  .dynsym         : { *(.dynsym) } >FLASH AT>FLASH :FLASH
+  .dynstr         : { *(.dynstr) } >FLASH AT>FLASH :FLASH
+  .gnu.version    : { *(.gnu.version) } >FLASH AT>FLASH :FLASH
+  .gnu.version_d  : { *(.gnu.version_d) } >FLASH AT>FLASH :FLASH
+  .gnu.version_r  : { *(.gnu.version_r) } >FLASH AT>FLASH :FLASH
+  .rel.init       : { *(.rel.init) } >FLASH AT>FLASH :FLASH
+  .rela.init      : { *(.rela.init) } >FLASH AT>FLASH :FLASH
+  .rel.text       : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH
+  .rela.text      : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH
+  .rel.fini       : { *(.rel.fini) } >FLASH AT>FLASH :FLASH
+  .rela.fini      : { *(.rela.fini) } >FLASH AT>FLASH :FLASH
+  .rel.rodata     : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
+  .rela.rodata    : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
+  .rel.data.rel.ro   : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH
+  .rela.data.rel.ro   : { *(.rel.data.rel.ro*) } >FLASH AT>FLASH :FLASH
+  .rel.data       : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH
+  .rela.data      : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } >FLASH AT>FLASH :FLASH
+  .rel.tdata	  : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH
+  .rela.tdata	  : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } >FLASH AT>FLASH :FLASH
+  .rel.tbss	  : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH
+  .rela.tbss	  : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH
+  .rel.ctors      : { *(.rel.ctors) } >FLASH AT>FLASH :FLASH
+  .rela.ctors     : { *(.rela.ctors) } >FLASH AT>FLASH :FLASH
+  .rel.dtors      : { *(.rel.dtors) } >FLASH AT>FLASH :FLASH
+  .rela.dtors     : { *(.rela.dtors) } >FLASH AT>FLASH :FLASH
+  .rel.got        : { *(.rel.got) } >FLASH AT>FLASH :FLASH
+  .rela.got       : { *(.rela.got) } >FLASH AT>FLASH :FLASH
+  .rel.bss        : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH
+  .rela.bss       : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH
+  .rel.plt        : { *(.rel.plt) } >FLASH AT>FLASH :FLASH
+  .rela.plt       : { *(.rela.plt) } >FLASH AT>FLASH :FLASH
+  .init           :
+  {
+    KEEP (*(.init))
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  .plt            : { *(.plt) } >FLASH AT>FLASH :FLASH
+  .text           :
+  {
+    *(.text .stub .text.* .gnu.linkonce.t.*)
+    KEEP (*(.text.*personality*))
+    /* .gnu.warning sections are handled specially by elf32.em.  */
+    *(.gnu.warning)
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  .fini           :
+  {
+    KEEP (*(.fini))
+  } >FLASH AT>FLASH :FLASH =0xd703d703
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
+  .rodata1        : { *(.rodata1) } >FLASH AT>FLASH :FLASH
+  .eh_frame_hdr : { *(.eh_frame_hdr) } >FLASH AT>FLASH :FLASH
+  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH :FLASH
+  .gcc_except_table   : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH :FLASH
+  .lalign	: { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH :FLASH
+  . = ORIGIN(INTRAM);
+  .dalign	: { . = ALIGN(8); PROVIDE(_data = .); } >INTRAM AT>INTRAM :INTRAM
+  /* Exception handling  */
+  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) } >INTRAM AT>FLASH :FLASH
+  .gcc_except_table   : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >INTRAM AT>FLASH :FLASH
+  /* Thread Local Storage sections  */
+  .tdata	  : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >INTRAM AT>FLASH :FLASH
+  .tbss		  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >INTRAM AT>FLASH :FLASH
+  /* Ensure the __preinit_array_start label is properly aligned.  We
+     could instead move the label definition inside the section, but
+     the linker would then create the section even if it turns out to
+     be empty, which isn't pretty.  */
+  PROVIDE (__preinit_array_start = ALIGN(32 / 8));
+  .preinit_array     : { KEEP (*(.preinit_array)) } >INTRAM AT>FLASH :FLASH
+  PROVIDE (__preinit_array_end = .);
+  PROVIDE (__init_array_start = .);
+  .init_array     : { KEEP (*(.init_array)) } >INTRAM AT>FLASH :FLASH
+  PROVIDE (__init_array_end = .);
+  PROVIDE (__fini_array_start = .);
+  .fini_array     : { KEEP (*(.fini_array)) } >INTRAM AT>FLASH :FLASH
+  PROVIDE (__fini_array_end = .);
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin*.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  } >INTRAM AT>FLASH :FLASH
+  .dtors          :
+  {
+    KEEP (*crtbegin*.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  } >INTRAM AT>FLASH :FLASH
+  .jcr            : { KEEP (*(.jcr)) } >INTRAM AT>FLASH :FLASH
+  .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >INTRAM AT>FLASH :FLASH
+  .dynamic        : { *(.dynamic) } >INTRAM AT>FLASH :FLASH
+  .got            : { *(.got.plt) *(.got) } >INTRAM AT>FLASH :FLASH
+  .data           :
+  {
+    *(.data .data.* .gnu.linkonce.d.*)
+    KEEP (*(.gnu.linkonce.d.*personality*))
+    SORT(CONSTRUCTORS)
+  } >INTRAM AT>FLASH :FLASH
+  .data1          : { *(.data1) } >INTRAM AT>FLASH :FLASH
+  .balign	: { . = ALIGN(8); _edata = .; } >INTRAM AT>FLASH :FLASH
+  _edata = .;
+  PROVIDE (edata = .);
+  __bss_start = .;
+  .bss            :
+  {
+    *(.dynbss)
+    *(.bss .bss.* .gnu.linkonce.b.*)
+    *(COMMON)
+    /* Align here to ensure that the .bss section occupies space up to
+       _end.  Align after .bss to ensure correct alignment even if the
+       .bss section disappears because there are no input sections.  */
+    . = ALIGN(8);
+  } >INTRAM AT>INTRAM :INTRAM
+  . = ALIGN(8);
+  _end = .;
+  PROVIDE (end = .);
+  __heap_start__ = ALIGN(8);
+  .heap           :
+  {
+    *(.heap)
+    . = (__heap_size__ == __max_heap_size__) ?
+        ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ - ABSOLUTE(.) :
+        __heap_size__;
+  } >INTRAM AT>INTRAM :INTRAM
+  __heap_end__ = .;
+  /* Stabs debugging sections.  */
+  .stab          0 : { *(.stab) }
+  .stabstr       0 : { *(.stabstr) }
+  .stab.excl     0 : { *(.stab.excl) }
+  .stab.exclstr  0 : { *(.stab.exclstr) }
+  .stab.index    0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  .comment       0 : { *(.comment) }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  .stack         ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ :
+  {
+    _stack = .;
+    *(.stack)
+    . = __stack_size__;
+    _estack = .;
+  } >INTRAM AT>INTRAM :INTRAM
+  .userpage       : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE :USERPAGE
+  .factorypage    : { *(.factorypage .factorypage.*) } >FACTORYPAGE AT>FACTORYPAGE :FACTORYPAGE
+  /DISCARD/ : { *(.note.GNU-stack) }
+}
diff --git a/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/164/IAR/lnkuc3b164.xcl b/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/164/IAR/lnkuc3b164.xcl
new file mode 100644
index 000000000..01af490cf
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/UTILS/LINKER_SCRIPTS/AT32UC3B/164/IAR/lnkuc3b164.xcl
@@ -0,0 +1,138 @@
+/******************************************************************************
+ * AVR32 AT32UC3B164 XLINK command file for AVR32 IAR C/C++ Compiler.
+ *
+ * The assumed memory layout is the one of the AT32UC3B164:
+ *
+ *   Start       Stop        Name     Type
+ *   ----------  ----------  -----    --------------
+ *   0x00000000  0x00003FFF  SRAM     RAM
+ *   0x80000000  0x8000FFFF  FLASH    FLASH
+ *
+ * Usage:  xlink  your_file(s)  -f xcl-file  libraries
+ *
+ * - Compiler:           IAR EWAVR32
+ * - Supported devices:  AVR32 AT32UC3B164
+ *
+ * - author              Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/************************************************************************/
+/*      The following segments are defined in this link file:           */
+/*                                                                      */
+/*      Code segments                                                   */
+/*      CODE32    -- Program code used by __code32 functions.           */
+/*      RESET     -- Reset code.                                        */
+/*      EVSEG     -- Exception vector handlers.                         */
+/*                                                                      */
+/*      Constant segments                                               */
+/*      INITTAB   -- Segment initializer table.                         */
+/*      DIFUNCT   -- Dynamic initialization vector used by C++.         */
+/*      SWITCH    -- Switch tables.                                     */
+/*      ACTAB     -- Table of pointers to acall functions.              */
+/*                                                                      */
+/*      DATA21_ID -- Initialization data for DATA21_I.                  */
+/*      DATA32_ID -- Initialization data for DATA32_I.                  */
+/*      DATA32_C  -- Constant __data32 data.                            */
+/*                                                                      */
+/*      CHECKSUM  -- Checksum segment.                                  */
+/*                                                                      */
+/*      Data segments                                                   */
+/*      DATA21_I  -- Initialized __data21 data with non-zero            */
+/*                   initial value.                                     */
+/*      DATA32_I  -- Initialized __data32 data with non-zero            */
+/*                   initial value.                                     */
+/*      DATA21_Z  -- Initialized __data21 data with zero initial value. */
+/*      DATA32_Z  -- Initialized __data32 data with zero initial value. */
+/*      DATA21_N  -- Non-initialized __data21.                          */
+/*      DATA32_N  -- Non-initialized __data32.                          */
+/*      SSTACK    -- The system stack.                                  */
+/*      CSTACK    -- The application stack.                             */
+/*      HEAP      -- The heap used by malloc and free.                  */
+/*                                                                      */
+/************************************************************************/
+
+/************************************************************************/
+/*      Define CPU                                                      */
+/************************************************************************/
+
+-cavr32
+
+// Declare the IPR0 memory location
+-DIPR0=FFFF0800
+
+/************************************************************************/
+/*      Reset code is located at address 0x80000000 and up.             */
+/************************************************************************/
+
+-Z(CODE)RESET=80000000-8000FFFF
+
+/************************************************************************/
+/*      The exception handler code is located at address 0x80000000     */
+/*      and up. Make sure that the exception table gets properly        */
+/*      allocated. By using the special -Z@ allocation primitive, the   */
+/*      placement is guaranteed to be at _EVBASE and onwards.           */
+/************************************************************************/
+
+-Z@(CODE)EVTAB=80004000-8000FFFF
+-Z@(CODE)EV100=80004100-8000FFFF
+-P(CODE)EVSEG=80004000-8000FFFF
+
+/************************************************************************/
+/*      Allocate code and const segments.                               */
+/************************************************************************/
+
+-P(CODE)CODE32=80000000-8000FFFF
+-P(CONST)DATA32_C=80000000-8000FFFF
+
+// Initializers
+-Z(CONST)INITTAB,DIFUNCT=80000000-8000FFFF
+-Z(CONST)CHECKSUM,SWITCH=80000000-8000FFFF
+-Z(CONST)DATA21_ID,DATA32_ID=80000000-8000FFFF
+
+-Z(CONST)ACTAB,HTAB=80000000-8000FFFF
+
+/************************************************************************/
+/*      Allocate the read/write segments that are mapped to RAM.        */
+/************************************************************************/
+
+-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-00003FFF
+-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-00003FFF
+-Z(DATA)TRACEBUFFER=00000004-00003FFF
+
+-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-00003FFF
+-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-00003FFF
+-Z(DATA)HEAP+_HEAP_SIZE=00000004-00003FFF
+
+/************************************************************************/
+/*      End of File                                                     */
+/************************************************************************/
diff --git a/20080212/Demo/lwIP_AVR32_UC3/UTILS/PREPROCESSOR/mrepeat.h b/20080212/Demo/lwIP_AVR32_UC3/UTILS/PREPROCESSOR/mrepeat.h
new file mode 100644
index 000000000..83b5f4916
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/UTILS/PREPROCESSOR/mrepeat.h
@@ -0,0 +1,323 @@
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief Preprocessor macro repeating utils.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef _MREPEAT_H_
+#define _MREPEAT_H_
+
+#include "preprocessor.h"
+
+
+//! Maximal number of repetitions supported by MREPEAT.
+#define MREPEAT_LIMIT   256
+
+/*! \brief Macro repeat.
+ *
+ * This macro represents a horizontal repetition construct.
+ *
+ * \param count  The number of repetitious calls to macro. Valid values range from 0 to MREPEAT_LIMIT.
+ * \param macro  A binary operation of the form macro(n, data). This macro is expanded by MREPEAT with
+ *               the current repetition number and the auxiliary data argument.
+ * \param data   Auxiliary data passed to macro.
+ *
+ * \return       macro(0, data) macro(1, data) ... macro(count - 1, data)
+ */
+#define MREPEAT(count, macro, data)         TPASTE2(MREPEAT, count)(macro, data)
+
+#define MREPEAT0(  macro, data)
+#define MREPEAT1(  macro, data)       MREPEAT0(  macro, data)   macro(  0, data)
+#define MREPEAT2(  macro, data)       MREPEAT1(  macro, data)   macro(  1, data)
+#define MREPEAT3(  macro, data)       MREPEAT2(  macro, data)   macro(  2, data)
+#define MREPEAT4(  macro, data)       MREPEAT3(  macro, data)   macro(  3, data)
+#define MREPEAT5(  macro, data)       MREPEAT4(  macro, data)   macro(  4, data)
+#define MREPEAT6(  macro, data)       MREPEAT5(  macro, data)   macro(  5, data)
+#define MREPEAT7(  macro, data)       MREPEAT6(  macro, data)   macro(  6, data)
+#define MREPEAT8(  macro, data)       MREPEAT7(  macro, data)   macro(  7, data)
+#define MREPEAT9(  macro, data)       MREPEAT8(  macro, data)   macro(  8, data)
+#define MREPEAT10( macro, data)       MREPEAT9(  macro, data)   macro(  9, data)
+#define MREPEAT11( macro, data)       MREPEAT10( macro, data)   macro( 10, data)
+#define MREPEAT12( macro, data)       MREPEAT11( macro, data)   macro( 11, data)
+#define MREPEAT13( macro, data)       MREPEAT12( macro, data)   macro( 12, data)
+#define MREPEAT14( macro, data)       MREPEAT13( macro, data)   macro( 13, data)
+#define MREPEAT15( macro, data)       MREPEAT14( macro, data)   macro( 14, data)
+#define MREPEAT16( macro, data)       MREPEAT15( macro, data)   macro( 15, data)
+#define MREPEAT17( macro, data)       MREPEAT16( macro, data)   macro( 16, data)
+#define MREPEAT18( macro, data)       MREPEAT17( macro, data)   macro( 17, data)
+#define MREPEAT19( macro, data)       MREPEAT18( macro, data)   macro( 18, data)
+#define MREPEAT20( macro, data)       MREPEAT19( macro, data)   macro( 19, data)
+#define MREPEAT21( macro, data)       MREPEAT20( macro, data)   macro( 20, data)
+#define MREPEAT22( macro, data)       MREPEAT21( macro, data)   macro( 21, data)
+#define MREPEAT23( macro, data)       MREPEAT22( macro, data)   macro( 22, data)
+#define MREPEAT24( macro, data)       MREPEAT23( macro, data)   macro( 23, data)
+#define MREPEAT25( macro, data)       MREPEAT24( macro, data)   macro( 24, data)
+#define MREPEAT26( macro, data)       MREPEAT25( macro, data)   macro( 25, data)
+#define MREPEAT27( macro, data)       MREPEAT26( macro, data)   macro( 26, data)
+#define MREPEAT28( macro, data)       MREPEAT27( macro, data)   macro( 27, data)
+#define MREPEAT29( macro, data)       MREPEAT28( macro, data)   macro( 28, data)
+#define MREPEAT30( macro, data)       MREPEAT29( macro, data)   macro( 29, data)
+#define MREPEAT31( macro, data)       MREPEAT30( macro, data)   macro( 30, data)
+#define MREPEAT32( macro, data)       MREPEAT31( macro, data)   macro( 31, data)
+#define MREPEAT33( macro, data)       MREPEAT32( macro, data)   macro( 32, data)
+#define MREPEAT34( macro, data)       MREPEAT33( macro, data)   macro( 33, data)
+#define MREPEAT35( macro, data)       MREPEAT34( macro, data)   macro( 34, data)
+#define MREPEAT36( macro, data)       MREPEAT35( macro, data)   macro( 35, data)
+#define MREPEAT37( macro, data)       MREPEAT36( macro, data)   macro( 36, data)
+#define MREPEAT38( macro, data)       MREPEAT37( macro, data)   macro( 37, data)
+#define MREPEAT39( macro, data)       MREPEAT38( macro, data)   macro( 38, data)
+#define MREPEAT40( macro, data)       MREPEAT39( macro, data)   macro( 39, data)
+#define MREPEAT41( macro, data)       MREPEAT40( macro, data)   macro( 40, data)
+#define MREPEAT42( macro, data)       MREPEAT41( macro, data)   macro( 41, data)
+#define MREPEAT43( macro, data)       MREPEAT42( macro, data)   macro( 42, data)
+#define MREPEAT44( macro, data)       MREPEAT43( macro, data)   macro( 43, data)
+#define MREPEAT45( macro, data)       MREPEAT44( macro, data)   macro( 44, data)
+#define MREPEAT46( macro, data)       MREPEAT45( macro, data)   macro( 45, data)
+#define MREPEAT47( macro, data)       MREPEAT46( macro, data)   macro( 46, data)
+#define MREPEAT48( macro, data)       MREPEAT47( macro, data)   macro( 47, data)
+#define MREPEAT49( macro, data)       MREPEAT48( macro, data)   macro( 48, data)
+#define MREPEAT50( macro, data)       MREPEAT49( macro, data)   macro( 49, data)
+#define MREPEAT51( macro, data)       MREPEAT50( macro, data)   macro( 50, data)
+#define MREPEAT52( macro, data)       MREPEAT51( macro, data)   macro( 51, data)
+#define MREPEAT53( macro, data)       MREPEAT52( macro, data)   macro( 52, data)
+#define MREPEAT54( macro, data)       MREPEAT53( macro, data)   macro( 53, data)
+#define MREPEAT55( macro, data)       MREPEAT54( macro, data)   macro( 54, data)
+#define MREPEAT56( macro, data)       MREPEAT55( macro, data)   macro( 55, data)
+#define MREPEAT57( macro, data)       MREPEAT56( macro, data)   macro( 56, data)
+#define MREPEAT58( macro, data)       MREPEAT57( macro, data)   macro( 57, data)
+#define MREPEAT59( macro, data)       MREPEAT58( macro, data)   macro( 58, data)
+#define MREPEAT60( macro, data)       MREPEAT59( macro, data)   macro( 59, data)
+#define MREPEAT61( macro, data)       MREPEAT60( macro, data)   macro( 60, data)
+#define MREPEAT62( macro, data)       MREPEAT61( macro, data)   macro( 61, data)
+#define MREPEAT63( macro, data)       MREPEAT62( macro, data)   macro( 62, data)
+#define MREPEAT64( macro, data)       MREPEAT63( macro, data)   macro( 63, data)
+#define MREPEAT65( macro, data)       MREPEAT64( macro, data)   macro( 64, data)
+#define MREPEAT66( macro, data)       MREPEAT65( macro, data)   macro( 65, data)
+#define MREPEAT67( macro, data)       MREPEAT66( macro, data)   macro( 66, data)
+#define MREPEAT68( macro, data)       MREPEAT67( macro, data)   macro( 67, data)
+#define MREPEAT69( macro, data)       MREPEAT68( macro, data)   macro( 68, data)
+#define MREPEAT70( macro, data)       MREPEAT69( macro, data)   macro( 69, data)
+#define MREPEAT71( macro, data)       MREPEAT70( macro, data)   macro( 70, data)
+#define MREPEAT72( macro, data)       MREPEAT71( macro, data)   macro( 71, data)
+#define MREPEAT73( macro, data)       MREPEAT72( macro, data)   macro( 72, data)
+#define MREPEAT74( macro, data)       MREPEAT73( macro, data)   macro( 73, data)
+#define MREPEAT75( macro, data)       MREPEAT74( macro, data)   macro( 74, data)
+#define MREPEAT76( macro, data)       MREPEAT75( macro, data)   macro( 75, data)
+#define MREPEAT77( macro, data)       MREPEAT76( macro, data)   macro( 76, data)
+#define MREPEAT78( macro, data)       MREPEAT77( macro, data)   macro( 77, data)
+#define MREPEAT79( macro, data)       MREPEAT78( macro, data)   macro( 78, data)
+#define MREPEAT80( macro, data)       MREPEAT79( macro, data)   macro( 79, data)
+#define MREPEAT81( macro, data)       MREPEAT80( macro, data)   macro( 80, data)
+#define MREPEAT82( macro, data)       MREPEAT81( macro, data)   macro( 81, data)
+#define MREPEAT83( macro, data)       MREPEAT82( macro, data)   macro( 82, data)
+#define MREPEAT84( macro, data)       MREPEAT83( macro, data)   macro( 83, data)
+#define MREPEAT85( macro, data)       MREPEAT84( macro, data)   macro( 84, data)
+#define MREPEAT86( macro, data)       MREPEAT85( macro, data)   macro( 85, data)
+#define MREPEAT87( macro, data)       MREPEAT86( macro, data)   macro( 86, data)
+#define MREPEAT88( macro, data)       MREPEAT87( macro, data)   macro( 87, data)
+#define MREPEAT89( macro, data)       MREPEAT88( macro, data)   macro( 88, data)
+#define MREPEAT90( macro, data)       MREPEAT89( macro, data)   macro( 89, data)
+#define MREPEAT91( macro, data)       MREPEAT90( macro, data)   macro( 90, data)
+#define MREPEAT92( macro, data)       MREPEAT91( macro, data)   macro( 91, data)
+#define MREPEAT93( macro, data)       MREPEAT92( macro, data)   macro( 92, data)
+#define MREPEAT94( macro, data)       MREPEAT93( macro, data)   macro( 93, data)
+#define MREPEAT95( macro, data)       MREPEAT94( macro, data)   macro( 94, data)
+#define MREPEAT96( macro, data)       MREPEAT95( macro, data)   macro( 95, data)
+#define MREPEAT97( macro, data)       MREPEAT96( macro, data)   macro( 96, data)
+#define MREPEAT98( macro, data)       MREPEAT97( macro, data)   macro( 97, data)
+#define MREPEAT99( macro, data)       MREPEAT98( macro, data)   macro( 98, data)
+#define MREPEAT100(macro, data)       MREPEAT99( macro, data)   macro( 99, data)
+#define MREPEAT101(macro, data)       MREPEAT100(macro, data)   macro(100, data)
+#define MREPEAT102(macro, data)       MREPEAT101(macro, data)   macro(101, data)
+#define MREPEAT103(macro, data)       MREPEAT102(macro, data)   macro(102, data)
+#define MREPEAT104(macro, data)       MREPEAT103(macro, data)   macro(103, data)
+#define MREPEAT105(macro, data)       MREPEAT104(macro, data)   macro(104, data)
+#define MREPEAT106(macro, data)       MREPEAT105(macro, data)   macro(105, data)
+#define MREPEAT107(macro, data)       MREPEAT106(macro, data)   macro(106, data)
+#define MREPEAT108(macro, data)       MREPEAT107(macro, data)   macro(107, data)
+#define MREPEAT109(macro, data)       MREPEAT108(macro, data)   macro(108, data)
+#define MREPEAT110(macro, data)       MREPEAT109(macro, data)   macro(109, data)
+#define MREPEAT111(macro, data)       MREPEAT110(macro, data)   macro(110, data)
+#define MREPEAT112(macro, data)       MREPEAT111(macro, data)   macro(111, data)
+#define MREPEAT113(macro, data)       MREPEAT112(macro, data)   macro(112, data)
+#define MREPEAT114(macro, data)       MREPEAT113(macro, data)   macro(113, data)
+#define MREPEAT115(macro, data)       MREPEAT114(macro, data)   macro(114, data)
+#define MREPEAT116(macro, data)       MREPEAT115(macro, data)   macro(115, data)
+#define MREPEAT117(macro, data)       MREPEAT116(macro, data)   macro(116, data)
+#define MREPEAT118(macro, data)       MREPEAT117(macro, data)   macro(117, data)
+#define MREPEAT119(macro, data)       MREPEAT118(macro, data)   macro(118, data)
+#define MREPEAT120(macro, data)       MREPEAT119(macro, data)   macro(119, data)
+#define MREPEAT121(macro, data)       MREPEAT120(macro, data)   macro(120, data)
+#define MREPEAT122(macro, data)       MREPEAT121(macro, data)   macro(121, data)
+#define MREPEAT123(macro, data)       MREPEAT122(macro, data)   macro(122, data)
+#define MREPEAT124(macro, data)       MREPEAT123(macro, data)   macro(123, data)
+#define MREPEAT125(macro, data)       MREPEAT124(macro, data)   macro(124, data)
+#define MREPEAT126(macro, data)       MREPEAT125(macro, data)   macro(125, data)
+#define MREPEAT127(macro, data)       MREPEAT126(macro, data)   macro(126, data)
+#define MREPEAT128(macro, data)       MREPEAT127(macro, data)   macro(127, data)
+#define MREPEAT129(macro, data)       MREPEAT128(macro, data)   macro(128, data)
+#define MREPEAT130(macro, data)       MREPEAT129(macro, data)   macro(129, data)
+#define MREPEAT131(macro, data)       MREPEAT130(macro, data)   macro(130, data)
+#define MREPEAT132(macro, data)       MREPEAT131(macro, data)   macro(131, data)
+#define MREPEAT133(macro, data)       MREPEAT132(macro, data)   macro(132, data)
+#define MREPEAT134(macro, data)       MREPEAT133(macro, data)   macro(133, data)
+#define MREPEAT135(macro, data)       MREPEAT134(macro, data)   macro(134, data)
+#define MREPEAT136(macro, data)       MREPEAT135(macro, data)   macro(135, data)
+#define MREPEAT137(macro, data)       MREPEAT136(macro, data)   macro(136, data)
+#define MREPEAT138(macro, data)       MREPEAT137(macro, data)   macro(137, data)
+#define MREPEAT139(macro, data)       MREPEAT138(macro, data)   macro(138, data)
+#define MREPEAT140(macro, data)       MREPEAT139(macro, data)   macro(139, data)
+#define MREPEAT141(macro, data)       MREPEAT140(macro, data)   macro(140, data)
+#define MREPEAT142(macro, data)       MREPEAT141(macro, data)   macro(141, data)
+#define MREPEAT143(macro, data)       MREPEAT142(macro, data)   macro(142, data)
+#define MREPEAT144(macro, data)       MREPEAT143(macro, data)   macro(143, data)
+#define MREPEAT145(macro, data)       MREPEAT144(macro, data)   macro(144, data)
+#define MREPEAT146(macro, data)       MREPEAT145(macro, data)   macro(145, data)
+#define MREPEAT147(macro, data)       MREPEAT146(macro, data)   macro(146, data)
+#define MREPEAT148(macro, data)       MREPEAT147(macro, data)   macro(147, data)
+#define MREPEAT149(macro, data)       MREPEAT148(macro, data)   macro(148, data)
+#define MREPEAT150(macro, data)       MREPEAT149(macro, data)   macro(149, data)
+#define MREPEAT151(macro, data)       MREPEAT150(macro, data)   macro(150, data)
+#define MREPEAT152(macro, data)       MREPEAT151(macro, data)   macro(151, data)
+#define MREPEAT153(macro, data)       MREPEAT152(macro, data)   macro(152, data)
+#define MREPEAT154(macro, data)       MREPEAT153(macro, data)   macro(153, data)
+#define MREPEAT155(macro, data)       MREPEAT154(macro, data)   macro(154, data)
+#define MREPEAT156(macro, data)       MREPEAT155(macro, data)   macro(155, data)
+#define MREPEAT157(macro, data)       MREPEAT156(macro, data)   macro(156, data)
+#define MREPEAT158(macro, data)       MREPEAT157(macro, data)   macro(157, data)
+#define MREPEAT159(macro, data)       MREPEAT158(macro, data)   macro(158, data)
+#define MREPEAT160(macro, data)       MREPEAT159(macro, data)   macro(159, data)
+#define MREPEAT161(macro, data)       MREPEAT160(macro, data)   macro(160, data)
+#define MREPEAT162(macro, data)       MREPEAT161(macro, data)   macro(161, data)
+#define MREPEAT163(macro, data)       MREPEAT162(macro, data)   macro(162, data)
+#define MREPEAT164(macro, data)       MREPEAT163(macro, data)   macro(163, data)
+#define MREPEAT165(macro, data)       MREPEAT164(macro, data)   macro(164, data)
+#define MREPEAT166(macro, data)       MREPEAT165(macro, data)   macro(165, data)
+#define MREPEAT167(macro, data)       MREPEAT166(macro, data)   macro(166, data)
+#define MREPEAT168(macro, data)       MREPEAT167(macro, data)   macro(167, data)
+#define MREPEAT169(macro, data)       MREPEAT168(macro, data)   macro(168, data)
+#define MREPEAT170(macro, data)       MREPEAT169(macro, data)   macro(169, data)
+#define MREPEAT171(macro, data)       MREPEAT170(macro, data)   macro(170, data)
+#define MREPEAT172(macro, data)       MREPEAT171(macro, data)   macro(171, data)
+#define MREPEAT173(macro, data)       MREPEAT172(macro, data)   macro(172, data)
+#define MREPEAT174(macro, data)       MREPEAT173(macro, data)   macro(173, data)
+#define MREPEAT175(macro, data)       MREPEAT174(macro, data)   macro(174, data)
+#define MREPEAT176(macro, data)       MREPEAT175(macro, data)   macro(175, data)
+#define MREPEAT177(macro, data)       MREPEAT176(macro, data)   macro(176, data)
+#define MREPEAT178(macro, data)       MREPEAT177(macro, data)   macro(177, data)
+#define MREPEAT179(macro, data)       MREPEAT178(macro, data)   macro(178, data)
+#define MREPEAT180(macro, data)       MREPEAT179(macro, data)   macro(179, data)
+#define MREPEAT181(macro, data)       MREPEAT180(macro, data)   macro(180, data)
+#define MREPEAT182(macro, data)       MREPEAT181(macro, data)   macro(181, data)
+#define MREPEAT183(macro, data)       MREPEAT182(macro, data)   macro(182, data)
+#define MREPEAT184(macro, data)       MREPEAT183(macro, data)   macro(183, data)
+#define MREPEAT185(macro, data)       MREPEAT184(macro, data)   macro(184, data)
+#define MREPEAT186(macro, data)       MREPEAT185(macro, data)   macro(185, data)
+#define MREPEAT187(macro, data)       MREPEAT186(macro, data)   macro(186, data)
+#define MREPEAT188(macro, data)       MREPEAT187(macro, data)   macro(187, data)
+#define MREPEAT189(macro, data)       MREPEAT188(macro, data)   macro(188, data)
+#define MREPEAT190(macro, data)       MREPEAT189(macro, data)   macro(189, data)
+#define MREPEAT191(macro, data)       MREPEAT190(macro, data)   macro(190, data)
+#define MREPEAT192(macro, data)       MREPEAT191(macro, data)   macro(191, data)
+#define MREPEAT193(macro, data)       MREPEAT192(macro, data)   macro(192, data)
+#define MREPEAT194(macro, data)       MREPEAT193(macro, data)   macro(193, data)
+#define MREPEAT195(macro, data)       MREPEAT194(macro, data)   macro(194, data)
+#define MREPEAT196(macro, data)       MREPEAT195(macro, data)   macro(195, data)
+#define MREPEAT197(macro, data)       MREPEAT196(macro, data)   macro(196, data)
+#define MREPEAT198(macro, data)       MREPEAT197(macro, data)   macro(197, data)
+#define MREPEAT199(macro, data)       MREPEAT198(macro, data)   macro(198, data)
+#define MREPEAT200(macro, data)       MREPEAT199(macro, data)   macro(199, data)
+#define MREPEAT201(macro, data)       MREPEAT200(macro, data)   macro(200, data)
+#define MREPEAT202(macro, data)       MREPEAT201(macro, data)   macro(201, data)
+#define MREPEAT203(macro, data)       MREPEAT202(macro, data)   macro(202, data)
+#define MREPEAT204(macro, data)       MREPEAT203(macro, data)   macro(203, data)
+#define MREPEAT205(macro, data)       MREPEAT204(macro, data)   macro(204, data)
+#define MREPEAT206(macro, data)       MREPEAT205(macro, data)   macro(205, data)
+#define MREPEAT207(macro, data)       MREPEAT206(macro, data)   macro(206, data)
+#define MREPEAT208(macro, data)       MREPEAT207(macro, data)   macro(207, data)
+#define MREPEAT209(macro, data)       MREPEAT208(macro, data)   macro(208, data)
+#define MREPEAT210(macro, data)       MREPEAT209(macro, data)   macro(209, data)
+#define MREPEAT211(macro, data)       MREPEAT210(macro, data)   macro(210, data)
+#define MREPEAT212(macro, data)       MREPEAT211(macro, data)   macro(211, data)
+#define MREPEAT213(macro, data)       MREPEAT212(macro, data)   macro(212, data)
+#define MREPEAT214(macro, data)       MREPEAT213(macro, data)   macro(213, data)
+#define MREPEAT215(macro, data)       MREPEAT214(macro, data)   macro(214, data)
+#define MREPEAT216(macro, data)       MREPEAT215(macro, data)   macro(215, data)
+#define MREPEAT217(macro, data)       MREPEAT216(macro, data)   macro(216, data)
+#define MREPEAT218(macro, data)       MREPEAT217(macro, data)   macro(217, data)
+#define MREPEAT219(macro, data)       MREPEAT218(macro, data)   macro(218, data)
+#define MREPEAT220(macro, data)       MREPEAT219(macro, data)   macro(219, data)
+#define MREPEAT221(macro, data)       MREPEAT220(macro, data)   macro(220, data)
+#define MREPEAT222(macro, data)       MREPEAT221(macro, data)   macro(221, data)
+#define MREPEAT223(macro, data)       MREPEAT222(macro, data)   macro(222, data)
+#define MREPEAT224(macro, data)       MREPEAT223(macro, data)   macro(223, data)
+#define MREPEAT225(macro, data)       MREPEAT224(macro, data)   macro(224, data)
+#define MREPEAT226(macro, data)       MREPEAT225(macro, data)   macro(225, data)
+#define MREPEAT227(macro, data)       MREPEAT226(macro, data)   macro(226, data)
+#define MREPEAT228(macro, data)       MREPEAT227(macro, data)   macro(227, data)
+#define MREPEAT229(macro, data)       MREPEAT228(macro, data)   macro(228, data)
+#define MREPEAT230(macro, data)       MREPEAT229(macro, data)   macro(229, data)
+#define MREPEAT231(macro, data)       MREPEAT230(macro, data)   macro(230, data)
+#define MREPEAT232(macro, data)       MREPEAT231(macro, data)   macro(231, data)
+#define MREPEAT233(macro, data)       MREPEAT232(macro, data)   macro(232, data)
+#define MREPEAT234(macro, data)       MREPEAT233(macro, data)   macro(233, data)
+#define MREPEAT235(macro, data)       MREPEAT234(macro, data)   macro(234, data)
+#define MREPEAT236(macro, data)       MREPEAT235(macro, data)   macro(235, data)
+#define MREPEAT237(macro, data)       MREPEAT236(macro, data)   macro(236, data)
+#define MREPEAT238(macro, data)       MREPEAT237(macro, data)   macro(237, data)
+#define MREPEAT239(macro, data)       MREPEAT238(macro, data)   macro(238, data)
+#define MREPEAT240(macro, data)       MREPEAT239(macro, data)   macro(239, data)
+#define MREPEAT241(macro, data)       MREPEAT240(macro, data)   macro(240, data)
+#define MREPEAT242(macro, data)       MREPEAT241(macro, data)   macro(241, data)
+#define MREPEAT243(macro, data)       MREPEAT242(macro, data)   macro(242, data)
+#define MREPEAT244(macro, data)       MREPEAT243(macro, data)   macro(243, data)
+#define MREPEAT245(macro, data)       MREPEAT244(macro, data)   macro(244, data)
+#define MREPEAT246(macro, data)       MREPEAT245(macro, data)   macro(245, data)
+#define MREPEAT247(macro, data)       MREPEAT246(macro, data)   macro(246, data)
+#define MREPEAT248(macro, data)       MREPEAT247(macro, data)   macro(247, data)
+#define MREPEAT249(macro, data)       MREPEAT248(macro, data)   macro(248, data)
+#define MREPEAT250(macro, data)       MREPEAT249(macro, data)   macro(249, data)
+#define MREPEAT251(macro, data)       MREPEAT250(macro, data)   macro(250, data)
+#define MREPEAT252(macro, data)       MREPEAT251(macro, data)   macro(251, data)
+#define MREPEAT253(macro, data)       MREPEAT252(macro, data)   macro(252, data)
+#define MREPEAT254(macro, data)       MREPEAT253(macro, data)   macro(253, data)
+#define MREPEAT255(macro, data)       MREPEAT254(macro, data)   macro(254, data)
+#define MREPEAT256(macro, data)       MREPEAT255(macro, data)   macro(255, data)
+
+
+#endif  // _MREPEAT_H_
diff --git a/20080212/Demo/lwIP_AVR32_UC3/UTILS/PREPROCESSOR/preprocessor.h b/20080212/Demo/lwIP_AVR32_UC3/UTILS/PREPROCESSOR/preprocessor.h
new file mode 100644
index 000000000..8a5813ef6
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/UTILS/PREPROCESSOR/preprocessor.h
@@ -0,0 +1,50 @@
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief Preprocessor utils.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef _PREPROCESSOR_H_
+#define _PREPROCESSOR_H_
+
+#include "tpaste.h"
+#include "stringz.h"
+#include "mrepeat.h"
+
+
+#endif  // _PREPROCESSOR_H_
diff --git a/20080212/Demo/lwIP_AVR32_UC3/UTILS/PREPROCESSOR/stringz.h b/20080212/Demo/lwIP_AVR32_UC3/UTILS/PREPROCESSOR/stringz.h
new file mode 100644
index 000000000..8230b69e1
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/UTILS/PREPROCESSOR/stringz.h
@@ -0,0 +1,70 @@
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief Preprocessor stringizing utils.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef _STRINGZ_H_
+#define _STRINGZ_H_
+
+
+/*! \brief Stringize.
+ *
+ * Stringize a preprocessing token, this token being allowed to be \#defined.
+ *
+ * May be used only within macros with the token passed as an argument if the token is \#defined.
+ *
+ * For example, writing STRINGZ(PIN) within a macro \#defined by PIN_NAME(PIN)
+ * and invoked as PIN_NAME(PIN0) with PIN0 \#defined as A0 is equivalent to
+ * writing "A0".
+ */
+#define STRINGZ(x)                                #x
+
+/*! \brief Absolute stringize.
+ *
+ * Stringize a preprocessing token, this token being allowed to be \#defined.
+ *
+ * No restriction of use if the token is \#defined.
+ *
+ * For example, writing ASTRINGZ(PIN0) anywhere with PIN0 \#defined as A0 is
+ * equivalent to writing "A0".
+ */
+#define ASTRINGZ(x)                               STRINGZ(x)
+
+
+#endif  // _STRINGZ_H_
diff --git a/20080212/Demo/lwIP_AVR32_UC3/UTILS/PREPROCESSOR/tpaste.h b/20080212/Demo/lwIP_AVR32_UC3/UTILS/PREPROCESSOR/tpaste.h
new file mode 100644
index 000000000..ed1fe9cf6
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/UTILS/PREPROCESSOR/tpaste.h
@@ -0,0 +1,90 @@
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief Preprocessor token pasting utils.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef _TPASTE_H_
+#define _TPASTE_H_
+
+
+/*! \name Token Paste
+ *
+ * Paste N preprocessing tokens together, these tokens being allowed to be \#defined.
+ *
+ * May be used only within macros with the tokens passed as arguments if the tokens are \#defined.
+ *
+ * For example, writing TPASTE2(U, WIDTH) within a macro \#defined by
+ * UTYPE(WIDTH) and invoked as UTYPE(UL_WIDTH) with UL_WIDTH \#defined as 32 is
+ * equivalent to writing U32.
+ */
+//! @{
+#define TPASTE2( a, b)                            a##b
+#define TPASTE3( a, b, c)                         a##b##c
+#define TPASTE4( a, b, c, d)                      a##b##c##d
+#define TPASTE5( a, b, c, d, e)                   a##b##c##d##e
+#define TPASTE6( a, b, c, d, e, f)                a##b##c##d##e##f
+#define TPASTE7( a, b, c, d, e, f, g)             a##b##c##d##e##f##g
+#define TPASTE8( a, b, c, d, e, f, g, h)          a##b##c##d##e##f##g##h
+#define TPASTE9( a, b, c, d, e, f, g, h, i)       a##b##c##d##e##f##g##h##i
+#define TPASTE10(a, b, c, d, e, f, g, h, i, j)    a##b##c##d##e##f##g##h##i##j
+//! @}
+
+/*! \name Absolute Token Paste
+ *
+ * Paste N preprocessing tokens together, these tokens being allowed to be \#defined.
+ *
+ * No restriction of use if the tokens are \#defined.
+ *
+ * For example, writing ATPASTE2(U, UL_WIDTH) anywhere with UL_WIDTH \#defined
+ * as 32 is equivalent to writing U32.
+ */
+//! @{
+#define ATPASTE2( a, b)                           TPASTE2( a, b)
+#define ATPASTE3( a, b, c)                        TPASTE3( a, b, c)
+#define ATPASTE4( a, b, c, d)                     TPASTE4( a, b, c, d)
+#define ATPASTE5( a, b, c, d, e)                  TPASTE5( a, b, c, d, e)
+#define ATPASTE6( a, b, c, d, e, f)               TPASTE6( a, b, c, d, e, f)
+#define ATPASTE7( a, b, c, d, e, f, g)            TPASTE7( a, b, c, d, e, f, g)
+#define ATPASTE8( a, b, c, d, e, f, g, h)         TPASTE8( a, b, c, d, e, f, g, h)
+#define ATPASTE9( a, b, c, d, e, f, g, h, i)      TPASTE9( a, b, c, d, e, f, g, h, i)
+#define ATPASTE10(a, b, c, d, e, f, g, h, i, j)   TPASTE10(a, b, c, d, e, f, g, h, i, j)
+//! @}
+
+
+#endif  // _TPASTE_H_
diff --git a/20080212/Demo/lwIP_AVR32_UC3/UTILS/compiler.h b/20080212/Demo/lwIP_AVR32_UC3/UTILS/compiler.h
new file mode 100644
index 000000000..70cc8d05c
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/UTILS/compiler.h
@@ -0,0 +1,1018 @@
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief Compiler file for AVR32.
+ *
+ * This file defines commonly used types and macros.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef _COMPILER_H_
+#define _COMPILER_H_
+
+#if (__GNUC__ && __AVR32__) || (__ICCAVR32__ || __AAVR32__)
+#  include 
+#endif
+#if __ICCAVR32__
+#  include 
+#endif
+#include "preprocessor.h"
+
+
+//_____ D E C L A R A T I O N S ____________________________________________
+
+#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.
+
+#include 
+#include 
+
+
+#if __ICCAVR32__
+
+/*! \name Compiler Keywords
+ *
+ * Port of some keywords from GNU GCC for AVR32 to IAR Embedded Workbench for Atmel AVR32.
+ */
+//! @{
+#define __asm__             asm
+#define __inline__          inline
+#define __volatile__
+//! @}
+
+#endif
+
+
+/*! \name Usual Types
+ */
+//! @{
+typedef unsigned char           Bool; //!< Boolean.
+typedef unsigned char           U8 ;  //!< 8-bit unsigned integer.
+typedef unsigned short int      U16;  //!< 16-bit unsigned integer.
+typedef unsigned long int       U32;  //!< 32-bit unsigned integer.
+typedef unsigned long long int  U64;  //!< 64-bit unsigned integer.
+typedef signed char             S8 ;  //!< 8-bit signed integer.
+typedef signed short int        S16;  //!< 16-bit signed integer.
+typedef signed long int         S32;  //!< 32-bit signed integer.
+typedef signed long long int    S64;  //!< 64-bit signed integer.
+typedef float                   F32;  //!< 32-bit floating-point number.
+typedef double                  F64;  //!< 64-bit floating-point number.
+//! @}
+
+
+/*! \name Status Types
+ */
+//! @{
+typedef Bool                Status_bool_t;  //!< Boolean status.
+typedef U8                  Status_t;       //!< 8-bit-coded status.
+//! @}
+
+
+/*! \name Aliasing Aggregate Types
+ */
+//! @{
+
+//! 16-bit union.
+typedef union
+{
+  U16 u16   ;
+  U8  u8 [2];
+} Union16;
+
+//! 32-bit union.
+typedef union
+{
+  U32 u32   ;
+  U16 u16[2];
+  U8  u8 [4];
+} Union32;
+
+//! 64-bit union.
+typedef union
+{
+  U64 u64   ;
+  U32 u32[2];
+  U16 u16[4];
+  U8  u8 [8];
+} Union64;
+
+//! Union of pointers to 64-, 32-, 16- and 8-bit unsigned integers.
+typedef union
+{
+  U64 *u64ptr;
+  U32 *u32ptr;
+  U16 *u16ptr;
+  U8  *u8ptr ;
+} UnionPtr;
+
+//! Union of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers.
+typedef union
+{
+  volatile U64 *u64ptr;
+  volatile U32 *u32ptr;
+  volatile U16 *u16ptr;
+  volatile U8  *u8ptr ;
+} UnionVPtr;
+
+//! Union of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers.
+typedef union
+{
+  const U64 *u64ptr;
+  const U32 *u32ptr;
+  const U16 *u16ptr;
+  const U8  *u8ptr ;
+} UnionCPtr;
+
+//! Union of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers.
+typedef union
+{
+  const volatile U64 *u64ptr;
+  const volatile U32 *u32ptr;
+  const volatile U16 *u16ptr;
+  const volatile U8  *u8ptr ;
+} UnionCVPtr;
+
+//! Structure of pointers to 64-, 32-, 16- and 8-bit unsigned integers.
+typedef struct
+{
+  U64 *u64ptr;
+  U32 *u32ptr;
+  U16 *u16ptr;
+  U8  *u8ptr ;
+} StructPtr;
+
+//! Structure of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers.
+typedef struct
+{
+  volatile U64 *u64ptr;
+  volatile U32 *u32ptr;
+  volatile U16 *u16ptr;
+  volatile U8  *u8ptr ;
+} StructVPtr;
+
+//! Structure of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers.
+typedef struct
+{
+  const U64 *u64ptr;
+  const U32 *u32ptr;
+  const U16 *u16ptr;
+  const U8  *u8ptr ;
+} StructCPtr;
+
+//! Structure of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers.
+typedef struct
+{
+  const volatile U64 *u64ptr;
+  const volatile U32 *u32ptr;
+  const volatile U16 *u16ptr;
+  const volatile U8  *u8ptr ;
+} StructCVPtr;
+
+//! @}
+
+#endif  // __AVR32_ABI_COMPILER__
+
+
+//_____ M A C R O S ________________________________________________________
+
+/*! \name Usual Constants
+ */
+//! @{
+#define DISABLE   0
+#define ENABLE    1
+#define DISABLED  0
+#define ENABLED   1
+#define OFF       0
+#define ON        1
+#define FALSE     0
+#define TRUE      1
+#define KO        0
+#define OK        1
+#define PASS      0
+#define FAIL      1
+#define LOW       0
+#define HIGH      1
+#define CLR       0
+#define SET       1
+//! @}
+
+
+#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.
+
+/*! \name Bit-Field Handling
+ */
+//! @{
+
+/*! \brief Reads the bits of a value specified by a given bit-mask.
+ *
+ * \param value Value to read bits from.
+ * \param mask  Bit-mask indicating bits to read.
+ *
+ * \return Read bits.
+ */
+#define Rd_bits( value, mask)        ((value) & (mask))
+
+/*! \brief Writes the bits of a C lvalue specified by a given bit-mask.
+ *
+ * \param lvalue  C lvalue to write bits to.
+ * \param mask    Bit-mask indicating bits to write.
+ * \param bits    Bits to write.
+ *
+ * \return Resulting value with written bits.
+ */
+#define Wr_bits(lvalue, mask, bits)  ((lvalue) = ((lvalue) & ~(mask)) |\
+                                                 ((bits  ) &  (mask)))
+
+/*! \brief Tests the bits of a value specified by a given bit-mask.
+ *
+ * \param value Value of which to test bits.
+ * \param mask  Bit-mask indicating bits to test.
+ *
+ * \return \c 1 if at least one of the tested bits is set, else \c 0.
+ */
+#define Tst_bits( value, mask)  (Rd_bits(value, mask) != 0)
+
+/*! \brief Clears the bits of a C lvalue specified by a given bit-mask.
+ *
+ * \param lvalue  C lvalue of which to clear bits.
+ * \param mask    Bit-mask indicating bits to clear.
+ *
+ * \return Resulting value with cleared bits.
+ */
+#define Clr_bits(lvalue, mask)  ((lvalue) &= ~(mask))
+
+/*! \brief Sets the bits of a C lvalue specified by a given bit-mask.
+ *
+ * \param lvalue  C lvalue of which to set bits.
+ * \param mask    Bit-mask indicating bits to set.
+ *
+ * \return Resulting value with set bits.
+ */
+#define Set_bits(lvalue, mask)  ((lvalue) |=  (mask))
+
+/*! \brief Toggles the bits of a C lvalue specified by a given bit-mask.
+ *
+ * \param lvalue  C lvalue of which to toggle bits.
+ * \param mask    Bit-mask indicating bits to toggle.
+ *
+ * \return Resulting value with toggled bits.
+ */
+#define Tgl_bits(lvalue, mask)  ((lvalue) ^=  (mask))
+
+/*! \brief Reads the bit-field of a value specified by a given bit-mask.
+ *
+ * \param value Value to read a bit-field from.
+ * \param mask  Bit-mask indicating the bit-field to read.
+ *
+ * \return Read bit-field.
+ */
+#define Rd_bitfield( value, mask)           (Rd_bits( value, mask) >> ctz(mask))
+
+/*! \brief Writes the bit-field of a C lvalue specified by a given bit-mask.
+ *
+ * \param lvalue    C lvalue to write a bit-field to.
+ * \param mask      Bit-mask indicating the bit-field to write.
+ * \param bitfield  Bit-field to write.
+ *
+ * \return Resulting value with written bit-field.
+ */
+#define Wr_bitfield(lvalue, mask, bitfield) (Wr_bits(lvalue, mask, (U32)(bitfield) << ctz(mask)))
+
+//! @}
+
+
+/*! \brief This macro is used to test fatal errors.
+ *
+ * The macro tests if the expression is FALSE. If it is, a fatal error is
+ * detected and the application hangs up.
+ *
+ * \param expr  Expression to evaluate and supposed to be nonzero.
+ */
+#ifdef _ASSERT_ENABLE_
+  #define Assert(expr) \
+  {\
+    if (!(expr)) while (TRUE);\
+  }
+#else
+  #define Assert(expr)
+#endif
+
+
+/*! \name Zero-Bit Counting
+ *
+ * Under AVR32-GCC, __builtin_clz and __builtin_ctz behave like macros when
+ * applied to constant expressions (values known at compile time), so they are
+ * more optimized than the use of the corresponding assembly instructions and
+ * they can be used as constant expressions e.g. to initialize objects having
+ * static storage duration, and like the corresponding assembly instructions
+ * when applied to non-constant expressions (values unknown at compile time), so
+ * they are more optimized than an assembly periphrasis. Hence, clz and ctz
+ * ensure a possible and optimized behavior for both constant and non-constant
+ * expressions.
+ */
+//! @{
+
+/*! \brief Counts the leading zero bits of the given value considered as a 32-bit integer.
+ *
+ * \param u Value of which to count the leading zero bits.
+ *
+ * \return The count of leading zero bits in \a u.
+ */
+#if __GNUC__
+  #define clz(u)              __builtin_clz(u)
+#elif __ICCAVR32__
+  #define clz(u)              __count_leading_zeros(u)
+#endif
+
+/*! \brief Counts the trailing zero bits of the given value considered as a 32-bit integer.
+ *
+ * \param u Value of which to count the trailing zero bits.
+ *
+ * \return The count of trailing zero bits in \a u.
+ */
+#if __GNUC__
+  #define ctz(u)              __builtin_ctz(u)
+#elif __ICCAVR32__
+  #define ctz(u)              __count_trailing_zeros(u)
+#endif
+
+//! @}
+
+
+/*! \name Alignment
+ */
+//! @{
+
+/*! \brief Tests alignment of the number \a val with the \a n boundary.
+ *
+ * \param val Input value.
+ * \param n   Boundary.
+ *
+ * \return \c 1 if the number \a val is aligned with the \a n boundary, else \c 0.
+ */
+#define Test_align(val, n     ) (!Tst_bits( val, (n) - 1     )   )
+
+/*! \brief Gets alignment of the number \a val with respect to the \a n boundary.
+ *
+ * \param val Input value.
+ * \param n   Boundary.
+ *
+ * \return Alignment of the number \a val with respect to the \a n boundary.
+ */
+#define Get_align( val, n     ) (  Rd_bits( val, (n) - 1     )   )
+
+/*! \brief Sets alignment of the lvalue number \a lval to \a alg with respect to the \a n boundary.
+ *
+ * \param lval  Input/output lvalue.
+ * \param n     Boundary.
+ * \param alg   Alignment.
+ *
+ * \return New value of \a lval resulting from its alignment set to \a alg with respect to the \a n boundary.
+ */
+#define Set_align(lval, n, alg) (  Wr_bits(lval, (n) - 1, alg)   )
+
+/*! \brief Aligns the number \a val with the upper \a n boundary.
+ *
+ * \param val Input value.
+ * \param n   Boundary.
+ *
+ * \return Value resulting from the number \a val aligned with the upper \a n boundary.
+ */
+#define Align_up(  val, n     ) (((val) + ((n) - 1)) & ~((n) - 1))
+
+/*! \brief Aligns the number \a val with the lower \a n boundary.
+ *
+ * \param val Input value.
+ * \param n   Boundary.
+ *
+ * \return Value resulting from the number \a val aligned with the lower \a n boundary.
+ */
+#define Align_down(val, n     ) ( (val)              & ~((n) - 1))
+
+//! @}
+
+
+/*! \name Mathematics
+ *
+ * The same considerations as for clz and ctz apply here but AVR32-GCC does not
+ * provide built-in functions to access the assembly instructions abs, min and
+ * max and it does not produce them by itself in most cases, so two sets of
+ * macros are defined here:
+ *   - Abs, Min and Max to apply to constant expressions (values known at
+ *     compile time);
+ *   - abs, min and max to apply to non-constant expressions (values unknown at
+ *     compile time).
+ */
+//! @{
+
+/*! \brief Takes the absolute value of \a a.
+ *
+ * \param a Input value.
+ *
+ * \return Absolute value of \a a.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Abs(a)              (((a) <  0 ) ? -(a) : (a))
+
+/*! \brief Takes the minimal value of \a a and \a b.
+ *
+ * \param a Input value.
+ * \param b Input value.
+ *
+ * \return Minimal value of \a a and \a b.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Min(a, b)           (((a) < (b)) ?  (a) : (b))
+
+/*! \brief Takes the maximal value of \a a and \a b.
+ *
+ * \param a Input value.
+ * \param b Input value.
+ *
+ * \return Maximal value of \a a and \a b.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Max(a, b)           (((a) > (b)) ?  (a) : (b))
+
+/*! \brief Takes the absolute value of \a a.
+ *
+ * \param a Input value.
+ *
+ * \return Absolute value of \a a.
+ *
+ * \note More optimized if only used with values unknown at compile time.
+ */
+#if __GNUC__
+  #define abs(a) \
+  (\
+    {\
+      int __value = (a);\
+      __asm__ ("abs\t%0" : "+r" (__value) :  : "cc");\
+      __value;\
+    }\
+  )
+#elif __ICCAVR32__
+  #define abs(a)      Abs(a)
+#endif
+
+/*! \brief Takes the minimal value of \a a and \a b.
+ *
+ * \param a Input value.
+ * \param b Input value.
+ *
+ * \return Minimal value of \a a and \a b.
+ *
+ * \note More optimized if only used with values unknown at compile time.
+ */
+#if __GNUC__
+  #define min(a, b) \
+  (\
+    {\
+      int __value, __arg_a = (a), __arg_b = (b);\
+      __asm__ ("min\t%0, %1, %2" : "=r" (__value) : "r" (__arg_a), "r" (__arg_b));\
+      __value;\
+    }\
+  )
+#elif __ICCAVR32__
+  #define min(a, b)   __min(a, b)
+#endif
+
+/*! \brief Takes the maximal value of \a a and \a b.
+ *
+ * \param a Input value.
+ * \param b Input value.
+ *
+ * \return Maximal value of \a a and \a b.
+ *
+ * \note More optimized if only used with values unknown at compile time.
+ */
+#if __GNUC__
+  #define max(a, b) \
+  (\
+    {\
+      int __value, __arg_a = (a), __arg_b = (b);\
+      __asm__ ("max\t%0, %1, %2" : "=r" (__value) : "r" (__arg_a), "r" (__arg_b));\
+      __value;\
+    }\
+  )
+#elif __ICCAVR32__
+  #define max(a, b)   __max(a, b)
+#endif
+
+//! @}
+
+
+/*! \brief Calls the routine at address \a addr.
+ *
+ * It generates a long call opcode.
+ *
+ * For example, `Long_call(0x80000000)' generates a software reset on a UC3 if
+ * it is invoked from the CPU supervisor mode.
+ *
+ * \param addr  Address of the routine to call.
+ *
+ * \note It may be used as a long jump opcode in some special cases.
+ */
+#define Long_call(addr)                   ((*(void (*)(void))(addr))())
+
+/*! \brief Resets the CPU by software.
+ *
+ * \warning It shall not be called from the CPU application mode.
+ */
+#if __GNUC__
+  #define Reset_CPU() \
+  (\
+    {\
+      __asm__ __volatile__ (\
+        "lddpc   r9, 3f\n\t"\
+        "mfsr    r8, %[SR]\n\t"\
+        "bfextu  r8, r8, %[SR_MX_OFFSET], %[SR_MX_SIZE]\n\t"\
+        "cp.w    r8, 0b001\n\t"\
+        "breq    0f\n\t"\
+        "sub     r8, pc, $ - 1f\n\t"\
+        "pushm   r8-r9\n\t"\
+        "rete\n"\
+        "0:\n\t"\
+        "mtsr    %[SR], r9\n"\
+        "1:\n\t"\
+        "mov     r0, 0\n\t"\
+        "mov     r1, 0\n\t"\
+        "mov     r2, 0\n\t"\
+        "mov     r3, 0\n\t"\
+        "mov     r4, 0\n\t"\
+        "mov     r5, 0\n\t"\
+        "mov     r6, 0\n\t"\
+        "mov     r7, 0\n\t"\
+        "mov     r8, 0\n\t"\
+        "mov     r9, 0\n\t"\
+        "mov     r10, 0\n\t"\
+        "mov     r11, 0\n\t"\
+        "mov     r12, 0\n\t"\
+        "mov     sp, 0\n\t"\
+        "stdsp   sp[0], sp\n\t"\
+        "ldmts   sp, sp\n\t"\
+        "mov     lr, 0\n\t"\
+        "lddpc   pc, 2f\n\t"\
+        ".balign 4\n"\
+        "2:\n\t"\
+        ".word   _start\n"\
+        "3:\n\t"\
+        ".word   %[RESET_SR]"\
+        :\
+        : [SR] "i" (AVR32_SR),\
+          [SR_MX_OFFSET] "i" (AVR32_SR_M0_OFFSET),\
+          [SR_MX_SIZE] "i" (AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE),\
+          [RESET_SR] "i" (AVR32_SR_GM_MASK | AVR32_SR_EM_MASK | AVR32_SR_M0_MASK)\
+      );\
+    }\
+  )
+#elif __ICCAVR32__
+  #define Reset_CPU() \
+  {\
+    extern void *volatile __program_start;\
+    __asm__ __volatile__ (\
+      "mov     r7, LWRD(__program_start)\n\t"\
+      "orh     r7, HWRD(__program_start)\n\t"\
+      "mov     r9, LWRD("ASTRINGZ(AVR32_SR_GM_MASK | AVR32_SR_EM_MASK | AVR32_SR_M0_MASK)")\n\t"\
+      "orh     r9, HWRD("ASTRINGZ(AVR32_SR_GM_MASK | AVR32_SR_EM_MASK | AVR32_SR_M0_MASK)")\n\t"\
+      "mfsr    r8, "ASTRINGZ(AVR32_SR)"\n\t"\
+      "bfextu  r8, r8, "ASTRINGZ(AVR32_SR_M0_OFFSET)", "ASTRINGZ(AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE)"\n\t"\
+      "cp.w    r8, 001b\n\t"\
+      "breq    $ + 10\n\t"\
+      "sub     r8, pc, -12\n\t"\
+      "pushm   r8-r9\n\t"\
+      "rete\n\t"\
+      "mtsr    "ASTRINGZ(AVR32_SR)", r9\n\t"\
+      "mov     r0, 0\n\t"\
+      "mov     r1, 0\n\t"\
+      "mov     r2, 0\n\t"\
+      "mov     r3, 0\n\t"\
+      "mov     r4, 0\n\t"\
+      "mov     r5, 0\n\t"\
+      "mov     r6, 0\n\t"\
+      "st.w    r0[4], r7\n\t"\
+      "mov     r7, 0\n\t"\
+      "mov     r8, 0\n\t"\
+      "mov     r9, 0\n\t"\
+      "mov     r10, 0\n\t"\
+      "mov     r11, 0\n\t"\
+      "mov     r12, 0\n\t"\
+      "mov     sp, 0\n\t"\
+      "stdsp   sp[0], sp\n\t"\
+      "ldmts   sp, sp\n\t"\
+      "mov     lr, 0\n\t"\
+      "ld.w    pc, lr[4]"\
+    );\
+    __program_start;\
+  }
+#endif
+
+
+/*! \name System Register Access
+ */
+//! @{
+
+/*! \brief Gets the value of the \a sysreg system register.
+ *
+ * \param sysreg  Address of the system register of which to get the value.
+ *
+ * \return Value of the \a sysreg system register.
+ */
+#if __GNUC__
+  #define Get_system_register(sysreg)         __builtin_mfsr(sysreg)
+#elif __ICCAVR32__
+  #define Get_system_register(sysreg)         __get_system_register(sysreg)
+#endif
+
+/*! \brief Sets the value of the \a sysreg system register to \a value.
+ *
+ * \param sysreg  Address of the system register of which to set the value.
+ * \param value   Value to set the \a sysreg system register to.
+ */
+#if __GNUC__
+  #define Set_system_register(sysreg, value)  __builtin_mtsr(sysreg, value)
+#elif __ICCAVR32__
+  #define Set_system_register(sysreg, value)  __set_system_register(sysreg, value)
+#endif
+
+//! @}
+
+
+/*! \name CPU Status Register Access
+ */
+//! @{
+
+/*! \brief Tells whether exceptions are globally enabled.
+ *
+ * \return \c 1 if exceptions are globally enabled, else \c 0.
+ */
+#define Is_global_exception_enabled()       (!Tst_bits(Get_system_register(AVR32_SR), AVR32_SR_EM_MASK))
+
+/*! \brief Disables exceptions globally.
+ */
+#if __GNUC__
+  #define Disable_global_exception()        ({__asm__ __volatile__ ("ssrf\t%0" :  : "i" (AVR32_SR_EM_OFFSET));})
+#elif __ICCAVR32__
+  #define Disable_global_exception()        (__set_status_flag(AVR32_SR_EM_OFFSET))
+#endif
+
+/*! \brief Enables exceptions globally.
+ */
+#if __GNUC__
+  #define Enable_global_exception()         ({__asm__ __volatile__ ("csrf\t%0" :  : "i" (AVR32_SR_EM_OFFSET));})
+#elif __ICCAVR32__
+  #define Enable_global_exception()         (__clear_status_flag(AVR32_SR_EM_OFFSET))
+#endif
+
+/*! \brief Tells whether interrupts are globally enabled.
+ *
+ * \return \c 1 if interrupts are globally enabled, else \c 0.
+ */
+#define Is_global_interrupt_enabled()       (!Tst_bits(Get_system_register(AVR32_SR), AVR32_SR_GM_MASK))
+
+/*! \brief Disables interrupts globally.
+ */
+#if __GNUC__
+  #define Disable_global_interrupt()        ({__asm__ __volatile__ ("ssrf\t%0\n\tnop\n\tnop" :  : "i" (AVR32_SR_GM_OFFSET));})
+#elif __ICCAVR32__
+  #define Disable_global_interrupt()        {__asm__ __volatile__ ("ssrf\t"ASTRINGZ(AVR32_SR_GM_OFFSET)"\n\tnop\n\tnop");}
+#endif
+
+/*! \brief Enables interrupts globally.
+ */
+#if __GNUC__
+  #define Enable_global_interrupt()         ({__asm__ __volatile__ ("csrf\t%0" :  : "i" (AVR32_SR_GM_OFFSET));})
+#elif __ICCAVR32__
+  #define Enable_global_interrupt()         (__enable_interrupt())
+#endif
+
+/*! \brief Tells whether interrupt level \a int_lev is enabled.
+ *
+ * \param int_lev Interrupt level (0 to 3).
+ *
+ * \return \c 1 if interrupt level \a int_lev is enabled, else \c 0.
+ */
+#define Is_interrupt_level_enabled(int_lev) (!Tst_bits(Get_system_register(AVR32_SR), TPASTE3(AVR32_SR_I, int_lev, M_MASK)))
+
+/*! \brief Disables interrupt level \a int_lev.
+ *
+ * \param int_lev Interrupt level to disable (0 to 3).
+ */
+#if __GNUC__
+  #define Disable_interrupt_level(int_lev)  ({__asm__ __volatile__ ("ssrf\t%0\n\tnop\n\tnop" :  : "i" (TPASTE3(AVR32_SR_I, int_lev, M_OFFSET)));})
+#elif __ICCAVR32__
+  #define Disable_interrupt_level(int_lev)  {__asm__ __volatile__ ("ssrf\t"ASTRINGZ(TPASTE3(AVR32_SR_I, int_lev, M_OFFSET))"\n\tnop\n\tnop");}
+#endif
+
+/*! \brief Enables interrupt level \a int_lev.
+ *
+ * \param int_lev Interrupt level to enable (0 to 3).
+ */
+#if __GNUC__
+  #define Enable_interrupt_level(int_lev)   ({__asm__ __volatile__ ("csrf\t%0" :  : "i" (TPASTE3(AVR32_SR_I, int_lev, M_OFFSET)));})
+#elif __ICCAVR32__
+  #define Enable_interrupt_level(int_lev)   (__clear_status_flag(TPASTE3(AVR32_SR_I, int_lev, M_OFFSET)))
+#endif
+
+//! @}
+
+
+/*! \name Debug Register Access
+ */
+//! @{
+
+/*! \brief Gets the value of the \a dbgreg debug register.
+ *
+ * \param dbgreg  Address of the debug register of which to get the value.
+ *
+ * \return Value of the \a dbgreg debug register.
+ */
+#if __GNUC__
+  #define Get_debug_register(dbgreg)          __builtin_mfdr(dbgreg)
+#elif __ICCAVR32__
+  #define Get_debug_register(dbgreg)          __get_debug_register(dbgreg)
+#endif
+
+/*! \brief Sets the value of the \a dbgreg debug register to \a value.
+ *
+ * \param dbgreg  Address of the debug register of which to set the value.
+ * \param value   Value to set the \a dbgreg debug register to.
+ */
+#if __GNUC__
+  #define Set_debug_register(dbgreg, value)   __builtin_mtdr(dbgreg, value)
+#elif __ICCAVR32__
+  #define Set_debug_register(dbgreg, value)   __set_debug_register(dbgreg, value)
+#endif
+
+//! @}
+
+#endif  // __AVR32_ABI_COMPILER__
+
+
+//! Boolean evaluating MCU little endianism.
+#if (__GNUC__ && __AVR32__) || (__ICCAVR32__ || __AAVR32__)
+  #define LITTLE_ENDIAN_MCU     FALSE
+#endif
+
+// Check that MCU endianism is correctly defined.
+#ifndef LITTLE_ENDIAN_MCU
+  #error YOU MUST define the MCU endianism with LITTLE_ENDIAN_MCU: either FALSE or TRUE
+#endif
+
+//! Boolean evaluating MCU big endianism.
+#define BIG_ENDIAN_MCU        (!LITTLE_ENDIAN_MCU)
+
+
+#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.
+
+/*! \name MCU Endianism Handling
+ */
+//! @{
+
+#if LITTLE_ENDIAN_MCU
+
+  #define LSB(u16)        (((U8  *)&(u16))[0])  //!< Least significant byte of \a u16.
+  #define MSB(u16)        (((U8  *)&(u16))[1])  //!< Most significant byte of \a u16.
+
+  #define LSH(u32)        (((U16 *)&(u32))[0])  //!< Least significant half-word of \a u32.
+  #define MSH(u32)        (((U16 *)&(u32))[1])  //!< Most significant half-word of \a u32.
+  #define LSB0W(u32)      (((U8  *)&(u32))[0])  //!< Least significant byte of 1st rank of \a u32.
+  #define LSB1W(u32)      (((U8  *)&(u32))[1])  //!< Least significant byte of 2nd rank of \a u32.
+  #define LSB2W(u32)      (((U8  *)&(u32))[2])  //!< Least significant byte of 3rd rank of \a u32.
+  #define LSB3W(u32)      (((U8  *)&(u32))[3])  //!< Least significant byte of 4th rank of \a u32.
+  #define MSB3W(u32)      LSB0W(u32)            //!< Most significant byte of 4th rank of \a u32.
+  #define MSB2W(u32)      LSB1W(u32)            //!< Most significant byte of 3rd rank of \a u32.
+  #define MSB1W(u32)      LSB2W(u32)            //!< Most significant byte of 2nd rank of \a u32.
+  #define MSB0W(u32)      LSB3W(u32)            //!< Most significant byte of 1st rank of \a u32.
+
+  #define LSW(u64)        (((U32 *)&(u64))[0])  //!< Least significant word of \a u64.
+  #define MSW(u64)        (((U32 *)&(u64))[1])  //!< Most significant word of \a u64.
+  #define LSH0(u64)       (((U16 *)&(u64))[0])  //!< Least significant half-word of 1st rank of \a u64.
+  #define LSH1(u64)       (((U16 *)&(u64))[1])  //!< Least significant half-word of 2nd rank of \a u64.
+  #define LSH2(u64)       (((U16 *)&(u64))[2])  //!< Least significant half-word of 3rd rank of \a u64.
+  #define LSH3(u64)       (((U16 *)&(u64))[3])  //!< Least significant half-word of 4th rank of \a u64.
+  #define MSH3(u64)       LSH0(u64)             //!< Most significant half-word of 4th rank of \a u64.
+  #define MSH2(u64)       LSH1(u64)             //!< Most significant half-word of 3rd rank of \a u64.
+  #define MSH1(u64)       LSH2(u64)             //!< Most significant half-word of 2nd rank of \a u64.
+  #define MSH0(u64)       LSH3(u64)             //!< Most significant half-word of 1st rank of \a u64.
+  #define LSB0D(u64)      (((U8  *)&(u64))[0])  //!< Least significant byte of 1st rank of \a u64.
+  #define LSB1D(u64)      (((U8  *)&(u64))[1])  //!< Least significant byte of 2nd rank of \a u64.
+  #define LSB2D(u64)      (((U8  *)&(u64))[2])  //!< Least significant byte of 3rd rank of \a u64.
+  #define LSB3D(u64)      (((U8  *)&(u64))[3])  //!< Least significant byte of 4th rank of \a u64.
+  #define LSB4D(u64)      (((U8  *)&(u64))[4])  //!< Least significant byte of 5th rank of \a u64.
+  #define LSB5D(u64)      (((U8  *)&(u64))[5])  //!< Least significant byte of 6th rank of \a u64.
+  #define LSB6D(u64)      (((U8  *)&(u64))[6])  //!< Least significant byte of 7th rank of \a u64.
+  #define LSB7D(u64)      (((U8  *)&(u64))[7])  //!< Least significant byte of 8th rank of \a u64.
+  #define MSB7D(u64)      LSB0D(u64)            //!< Most significant byte of 8th rank of \a u64.
+  #define MSB6D(u64)      LSB1D(u64)            //!< Most significant byte of 7th rank of \a u64.
+  #define MSB5D(u64)      LSB2D(u64)            //!< Most significant byte of 6th rank of \a u64.
+  #define MSB4D(u64)      LSB3D(u64)            //!< Most significant byte of 5th rank of \a u64.
+  #define MSB3D(u64)      LSB4D(u64)            //!< Most significant byte of 4th rank of \a u64.
+  #define MSB2D(u64)      LSB5D(u64)            //!< Most significant byte of 3rd rank of \a u64.
+  #define MSB1D(u64)      LSB6D(u64)            //!< Most significant byte of 2nd rank of \a u64.
+  #define MSB0D(u64)      LSB7D(u64)            //!< Most significant byte of 1st rank of \a u64.
+
+#else // BIG_ENDIAN_MCU
+
+  #define MSB(u16)        (((U8  *)&(u16))[0])  //!< Most significant byte of \a u16.
+  #define LSB(u16)        (((U8  *)&(u16))[1])  //!< Least significant byte of \a u16.
+
+  #define MSH(u32)        (((U16 *)&(u32))[0])  //!< Most significant half-word of \a u32.
+  #define LSH(u32)        (((U16 *)&(u32))[1])  //!< Least significant half-word of \a u32.
+  #define MSB0W(u32)      (((U8  *)&(u32))[0])  //!< Most significant byte of 1st rank of \a u32.
+  #define MSB1W(u32)      (((U8  *)&(u32))[1])  //!< Most significant byte of 2nd rank of \a u32.
+  #define MSB2W(u32)      (((U8  *)&(u32))[2])  //!< Most significant byte of 3rd rank of \a u32.
+  #define MSB3W(u32)      (((U8  *)&(u32))[3])  //!< Most significant byte of 4th rank of \a u32.
+  #define LSB3W(u32)      MSB0W(u32)            //!< Least significant byte of 4th rank of \a u32.
+  #define LSB2W(u32)      MSB1W(u32)            //!< Least significant byte of 3rd rank of \a u32.
+  #define LSB1W(u32)      MSB2W(u32)            //!< Least significant byte of 2nd rank of \a u32.
+  #define LSB0W(u32)      MSB3W(u32)            //!< Least significant byte of 1st rank of \a u32.
+
+  #define MSW(u64)        (((U32 *)&(u64))[0])  //!< Most significant word of \a u64.
+  #define LSW(u64)        (((U32 *)&(u64))[1])  //!< Least significant word of \a u64.
+  #define MSH0(u64)       (((U16 *)&(u64))[0])  //!< Most significant half-word of 1st rank of \a u64.
+  #define MSH1(u64)       (((U16 *)&(u64))[1])  //!< Most significant half-word of 2nd rank of \a u64.
+  #define MSH2(u64)       (((U16 *)&(u64))[2])  //!< Most significant half-word of 3rd rank of \a u64.
+  #define MSH3(u64)       (((U16 *)&(u64))[3])  //!< Most significant half-word of 4th rank of \a u64.
+  #define LSH3(u64)       MSH0(u64)             //!< Least significant half-word of 4th rank of \a u64.
+  #define LSH2(u64)       MSH1(u64)             //!< Least significant half-word of 3rd rank of \a u64.
+  #define LSH1(u64)       MSH2(u64)             //!< Least significant half-word of 2nd rank of \a u64.
+  #define LSH0(u64)       MSH3(u64)             //!< Least significant half-word of 1st rank of \a u64.
+  #define MSB0D(u64)      (((U8  *)&(u64))[0])  //!< Most significant byte of 1st rank of \a u64.
+  #define MSB1D(u64)      (((U8  *)&(u64))[1])  //!< Most significant byte of 2nd rank of \a u64.
+  #define MSB2D(u64)      (((U8  *)&(u64))[2])  //!< Most significant byte of 3rd rank of \a u64.
+  #define MSB3D(u64)      (((U8  *)&(u64))[3])  //!< Most significant byte of 4th rank of \a u64.
+  #define MSB4D(u64)      (((U8  *)&(u64))[4])  //!< Most significant byte of 5th rank of \a u64.
+  #define MSB5D(u64)      (((U8  *)&(u64))[5])  //!< Most significant byte of 6th rank of \a u64.
+  #define MSB6D(u64)      (((U8  *)&(u64))[6])  //!< Most significant byte of 7th rank of \a u64.
+  #define MSB7D(u64)      (((U8  *)&(u64))[7])  //!< Most significant byte of 8th rank of \a u64.
+  #define LSB7D(u64)      MSB0D(u64)            //!< Least significant byte of 8th rank of \a u64.
+  #define LSB6D(u64)      MSB1D(u64)            //!< Least significant byte of 7th rank of \a u64.
+  #define LSB5D(u64)      MSB2D(u64)            //!< Least significant byte of 6th rank of \a u64.
+  #define LSB4D(u64)      MSB3D(u64)            //!< Least significant byte of 5th rank of \a u64.
+  #define LSB3D(u64)      MSB4D(u64)            //!< Least significant byte of 4th rank of \a u64.
+  #define LSB2D(u64)      MSB5D(u64)            //!< Least significant byte of 3rd rank of \a u64.
+  #define LSB1D(u64)      MSB6D(u64)            //!< Least significant byte of 2nd rank of \a u64.
+  #define LSB0D(u64)      MSB7D(u64)            //!< Least significant byte of 1st rank of \a u64.
+
+#endif
+
+//! @}
+
+
+/*! \name Endianism Conversion
+ *
+ * The same considerations as for clz and ctz apply here but AVR32-GCC's
+ * __builtin_bswap_16 and __builtin_bswap_32 do not behave like macros when
+ * applied to constant expressions, so two sets of macros are defined here:
+ *   - Swap16, Swap32 and Swap64 to apply to constant expressions (values known
+ *     at compile time);
+ *   - swap16, swap32 and swap64 to apply to non-constant expressions (values
+ *     unknown at compile time).
+ */
+//! @{
+
+/*! \brief Toggles the endianism of \a u16 (by swapping its bytes).
+ *
+ * \param u16 U16 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u16 with toggled endianism.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Swap16(u16) ((U16)(((U16)(u16) >> 8) |\
+                           ((U16)(u16) << 8)))
+
+/*! \brief Toggles the endianism of \a u32 (by swapping its bytes).
+ *
+ * \param u32 U32 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u32 with toggled endianism.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Swap32(u32) ((U32)(((U32)Swap16((U32)(u32) >> 16)) |\
+                           ((U32)Swap16((U32)(u32)) << 16)))
+
+/*! \brief Toggles the endianism of \a u64 (by swapping its bytes).
+ *
+ * \param u64 U64 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u64 with toggled endianism.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Swap64(u64) ((U64)(((U64)Swap32((U64)(u64) >> 32)) |\
+                           ((U64)Swap32((U64)(u64)) << 32)))
+
+/*! \brief Toggles the endianism of \a u16 (by swapping its bytes).
+ *
+ * \param u16 U16 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u16 with toggled endianism.
+ *
+ * \note More optimized if only used with values unknown at compile time.
+ */
+#if __GNUC__
+  #define swap16(u16) ((U16)__builtin_bswap_16((U16)(u16)))
+#elif __ICCAVR32__
+  #define swap16(u16) ((U16)__swap_bytes_in_halfwords((U16)(u16)))
+#endif
+
+/*! \brief Toggles the endianism of \a u32 (by swapping its bytes).
+ *
+ * \param u32 U32 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u32 with toggled endianism.
+ *
+ * \note More optimized if only used with values unknown at compile time.
+ */
+#if __GNUC__
+  #define swap32(u32) ((U32)__builtin_bswap_32((U32)(u32)))
+#elif __ICCAVR32__
+  #define swap32(u32) ((U32)__swap_bytes((U32)(u32)))
+#endif
+
+/*! \brief Toggles the endianism of \a u64 (by swapping its bytes).
+ *
+ * \param u64 U64 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u64 with toggled endianism.
+ *
+ * \note More optimized if only used with values unknown at compile time.
+ */
+#define swap64(u64) ((U64)(((U64)swap32((U64)(u64) >> 32)) |\
+                           ((U64)swap32((U64)(u64)) << 32)))
+
+//! @}
+
+
+/*! \name Target Abstraction
+ */
+//! @{
+
+#define _GLOBEXT_           extern      //!< extern storage-class specifier.
+#define _CONST_TYPE_        const       //!< const type qualifier.
+#define _MEM_TYPE_SLOW_                 //!< Slow memory type.
+#define _MEM_TYPE_MEDFAST_              //!< Fairly fast memory type.
+#define _MEM_TYPE_FAST_                 //!< Fast memory type.
+
+typedef U8                  Byte;       //!< 8-bit unsigned integer.
+
+#define memcmp_ram2ram      memcmp      //!< Target-specific memcmp of RAM to RAM.
+#define memcmp_code2ram     memcmp      //!< Target-specific memcmp of RAM to NVRAM.
+#define memcpy_ram2ram      memcpy      //!< Target-specific memcpy from RAM to RAM.
+#define memcpy_code2ram     memcpy      //!< Target-specific memcpy from NVRAM to RAM.
+
+#define LSB0(u32)           LSB0W(u32)  //!< Least significant byte of 1st rank of \a u32.
+#define LSB1(u32)           LSB1W(u32)  //!< Least significant byte of 2nd rank of \a u32.
+#define LSB2(u32)           LSB2W(u32)  //!< Least significant byte of 3rd rank of \a u32.
+#define LSB3(u32)           LSB3W(u32)  //!< Least significant byte of 4th rank of \a u32.
+#define MSB3(u32)           MSB3W(u32)  //!< Most significant byte of 4th rank of \a u32.
+#define MSB2(u32)           MSB2W(u32)  //!< Most significant byte of 3rd rank of \a u32.
+#define MSB1(u32)           MSB1W(u32)  //!< Most significant byte of 2nd rank of \a u32.
+#define MSB0(u32)           MSB0W(u32)  //!< Most significant byte of 1st rank of \a u32.
+
+//! @}
+
+#endif  // __AVR32_ABI_COMPILER__
+
+
+#endif  // _COMPILER_H_
diff --git a/20080212/Demo/lwIP_AVR32_UC3/conf_eth.h b/20080212/Demo/lwIP_AVR32_UC3/conf_eth.h
new file mode 100644
index 000000000..661ba4b52
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/conf_eth.h
@@ -0,0 +1,140 @@
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file ******************************************************************
+ *
+ * \brief Ethernet module configuration file.
+ *
+ * This file contains the possible external configuration of the Ethernet module.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ***************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef _CONF_ETH_H_
+#define _CONF_ETH_H_
+
+/*! define stack size for WEB server task */
+#define lwipBASIC_WEB_SERVER_STACK_SIZE   256
+
+/*! define stack size for TFTP server task */
+#define lwipBASIC_TFTP_SERVER_STACK_SIZE  1024
+
+/*! define stack size for SMTP Client task */
+#define lwipBASIC_SMTP_CLIENT_STACK_SIZE  256
+
+/*! define stack size for lwIP task */
+#define lwipINTERFACE_STACK_SIZE          512
+
+/*! define stack size for netif task */
+#define netifINTERFACE_TASK_STACK_SIZE    256
+
+/*! define WEB server priority */
+#define ethWEBSERVER_PRIORITY             ( tskIDLE_PRIORITY + 2 )
+
+/*! define TFTP server priority */
+#define ethTFTPSERVER_PRIORITY            ( tskIDLE_PRIORITY + 3 )
+
+/*! define SMTP Client priority */
+#define ethSMTPCLIENT_PRIORITY            ( tskIDLE_PRIORITY + 5 )
+
+/*! define lwIP task priority */
+#define lwipINTERFACE_TASK_PRIORITY       ( configMAX_PRIORITIES - 1 )
+
+/*! define netif task priority */
+#define netifINTERFACE_TASK_PRIORITY      ( configMAX_PRIORITIES - 1 )
+
+/*! Number of threads that can be started with sys_thread_new() */
+#define SYS_THREAD_MAX                      6
+
+/*! LED used by the ethernet task, toggled on each activation */
+#define webCONN_LED                         7
+
+/*! Phy Address (set through strap options) */
+#define ETHERNET_CONF_PHY_ADDR             0x01
+#define ETHERNET_CONF_PHY_ID               0x20005C90
+
+/*! Number of receive buffers */
+#define ETHERNET_CONF_NB_RX_BUFFERS        20
+
+/*! USE_RMII_INTERFACE must be defined as 1 to use an RMII interface, or 0
+to use an MII interface. */
+#define ETHERNET_CONF_USE_RMII_INTERFACE   1
+
+/*! Number of Transmit buffers */
+#define ETHERNET_CONF_NB_TX_BUFFERS        10
+
+/*! Size of each Transmit buffer. */
+#define ETHERNET_CONF_TX_BUFFER_SIZE       512
+
+/*! Clock definition */
+#define ETHERNET_CONF_SYSTEM_CLOCK         48000000
+
+/*! Use Auto Negociation to get speed and duplex */
+#define ETHERNET_CONF_AN_ENABLE                      1
+
+/*! Do not use auto cross capability */
+#define ETHERNET_CONF_AUTO_CROSS_ENABLE              0
+/*! use direct cable */
+#define ETHERNET_CONF_CROSSED_LINK                   0
+
+
+/* ethernet default parameters */
+/*! MAC address definition.  The MAC address must be unique on the network. */
+#define ETHERNET_CONF_ETHADDR0                        0x00
+#define ETHERNET_CONF_ETHADDR1                        0x04
+#define ETHERNET_CONF_ETHADDR2                        0x25
+#define ETHERNET_CONF_ETHADDR3                        0x40
+#define ETHERNET_CONF_ETHADDR4                        0x40
+#define ETHERNET_CONF_ETHADDR5                        0x40
+
+/*! The IP address being used. */
+#define ETHERNET_CONF_IPADDR0                         192
+#define ETHERNET_CONF_IPADDR1                         168
+#define ETHERNET_CONF_IPADDR2                         0
+#define ETHERNET_CONF_IPADDR3                         2
+
+/*! The gateway address being used. */
+#define ETHERNET_CONF_GATEWAY_ADDR0                   192
+#define ETHERNET_CONF_GATEWAY_ADDR1                   168
+#define ETHERNET_CONF_GATEWAY_ADDR2                   0
+#define ETHERNET_CONF_GATEWAY_ADDR3                   1
+
+/*! The network mask being used. */
+#define ETHERNET_CONF_NET_MASK0                       255
+#define ETHERNET_CONF_NET_MASK1                       255
+#define ETHERNET_CONF_NET_MASK2                       255
+#define ETHERNET_CONF_NET_MASK3                       0
+
+#endif
diff --git a/20080212/Demo/lwIP_AVR32_UC3/lwipopts.h b/20080212/Demo/lwIP_AVR32_UC3/lwipopts.h
new file mode 100644
index 000000000..21f325633
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/lwipopts.h
@@ -0,0 +1,229 @@
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief lwIP configuration for AVR32 UC3.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ *****************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+
+#ifndef __LWIPOPTS_H__
+#define __LWIPOPTS_H__
+
+/* Include user defined options first */
+#include "conf_eth.h"
+// #include "lwip/debug.h"
+
+#define LWIP_PLATFORM_DIAG(x)   
+#define LWIP_PLATFORM_ASSERT(x)   
+
+/* Define default values for unconfigured parameters. */
+#define LWIP_NOASSERT 1 // To suppress some errors for now (no debug output)
+
+/* These two control is reclaimer functions should be compiled
+   in. Should always be turned on (1). */
+#define MEM_RECLAIM             1
+#define MEMP_RECLAIM            1
+
+
+/* Platform specific locking */
+
+/*
+ * enable SYS_LIGHTWEIGHT_PROT in lwipopts.h if you want inter-task protection
+ * for certain critical regions during buffer allocation, deallocation and memory
+ * allocation and deallocation.
+ */
+#define SYS_LIGHTWEIGHT_PROT            1
+
+/* ---------- Memory options ---------- */
+// #define MEM_LIBC_MALLOC                 0
+
+/* MEM_ALIGNMENT: should be set to the alignment of the CPU for which
+   lwIP is compiled. 4 byte alignment -> define MEM_ALIGNMENT to 4, 2
+   byte alignment -> define MEM_ALIGNMENT to 2. */
+#define MEM_ALIGNMENT           4
+
+/* MEM_SIZE: the size of the heap memory. If the application will send
+a lot of data that needs to be copied, this should be set high. */
+#define MEM_SIZE                3 * 1024
+
+// #define MEMP_SANITY_CHECK       1
+
+/* MEMP_NUM_PBUF: the number of memp struct pbufs. If the application
+   sends a lot of data out of ROM (or other static memory), this
+   should be set high. */
+#define MEMP_NUM_PBUF           6
+
+/* Number of raw connection PCBs */
+#define MEMP_NUM_RAW_PCB                1
+
+#if (TFTP_USED == 1)
+  /* ---------- UDP options ---------- */
+  #define LWIP_UDP                1
+  #define UDP_TTL                 255
+  /* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One
+     per active UDP "connection". */
+
+  #define MEMP_NUM_UDP_PCB        1
+#else
+  /* ---------- UDP options ---------- */
+  #define LWIP_UDP                0
+  #define UDP_TTL                 0
+  /* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One
+     per active UDP "connection". */
+
+  #define MEMP_NUM_UDP_PCB        0
+#endif
+
+/* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP
+   connections. */
+#define MEMP_NUM_TCP_PCB        14
+/* MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP
+   connections. */
+#define MEMP_NUM_TCP_PCB_LISTEN 2
+/* MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP
+   segments. */
+#define MEMP_NUM_TCP_SEG        6
+/* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active
+   timeouts. */
+#define MEMP_NUM_SYS_TIMEOUT    6
+
+/* The following four are used only with the sequential API and can be
+   set to 0 if the application only will use the raw API. */
+/* MEMP_NUM_NETBUF: the number of struct netbufs. */
+#define MEMP_NUM_NETBUF         3
+/* MEMP_NUM_NETCONN: the number of struct netconns. */
+#define MEMP_NUM_NETCONN        6
+/* MEMP_NUM_APIMSG: the number of struct api_msg, used for
+   communication between the TCP/IP stack and the sequential
+   programs. */
+#define MEMP_NUM_API_MSG        4
+/* MEMP_NUM_TCPIPMSG: the number of struct tcpip_msg, which is used
+   for sequential API communication and incoming packets. Used in
+   src/api/tcpip.c. */
+#define MEMP_NUM_TCPIP_MSG      4
+
+
+/* ---------- Pbuf options ---------- */
+/* PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */
+
+#define PBUF_POOL_SIZE          6
+
+/* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */
+
+#define PBUF_POOL_BUFSIZE       500
+
+/* PBUF_LINK_HLEN: the number of bytes that should be allocated for a
+   link level header. */
+#define PBUF_LINK_HLEN          16
+
+/* ---------- TCP options ---------- */
+#define LWIP_TCP                1
+#define TCP_TTL                 255
+/* TCP receive window. */
+#define TCP_WND                 1500
+/* Controls if TCP should queue segments that arrive out of
+   order. Define to 0 if your device is low on memory. */
+#define TCP_QUEUE_OOSEQ         1
+
+/* TCP Maximum segment size. */
+#define TCP_MSS                 1500
+
+/* TCP sender buffer space (bytes). */
+#define TCP_SND_BUF             2150
+
+/* TCP sender buffer space (pbufs). This must be at least = 2 *
+   TCP_SND_BUF/TCP_MSS for things to work. */
+#define TCP_SND_QUEUELEN        6 * TCP_SND_BUF/TCP_MSS
+
+
+
+/* Maximum number of retransmissions of data segments. */
+#define TCP_MAXRTX              12
+
+/* Maximum number of retransmissions of SYN segments. */
+#define TCP_SYNMAXRTX           4
+
+/* ---------- ARP options ---------- */
+#define ARP_TABLE_SIZE 10
+#define ARP_QUEUEING 0
+
+/* ---------- IP options ---------- */
+/* Define IP_FORWARD to 1 if you wish to have the ability to forward
+   IP packets across network interfaces. If you are going to run lwIP
+   on a device with only one network interface, define this to 0. */
+#define IP_FORWARD              0
+
+/* If defined to 1, IP options are allowed (but not parsed). If
+   defined to 0, all packets with IP options are dropped. */
+#define IP_OPTIONS              1
+
+/* ---------- ICMP options ---------- */
+#define ICMP_TTL                255
+
+
+/* ---------- DHCP options ---------- */
+/* Define LWIP_DHCP to 1 if you want DHCP configuration of
+   interfaces. DHCP is not implemented in lwIP 0.5.1, however, so
+   turning this on does currently not work. */
+#define LWIP_DHCP               0
+
+/* 1 if you want to do an ARP check on the offered address
+   (recommended). */
+#define DHCP_DOES_ARP_CHECK     1
+
+#define TCPIP_THREAD_PRIO               lwipINTERFACE_TASK_PRIORITY
+
+/* ---------- Statistics options ---------- */
+#define LWIP_STATS 1
+
+#define LWIP_STATS_DISPLAY 1
+
+#if LWIP_STATS
+#define LINK_STATS 1
+#define IP_STATS   1
+#define ICMP_STATS 1
+#define UDP_STATS  1
+#define TCP_STATS  1
+#define MEM_STATS  1
+#define MEMP_STATS 1
+#define PBUF_STATS 1
+#define SYS_STATS  1
+#endif /* STATS */
+
+
+#endif /* __LWIPOPTS_H__ */
diff --git a/20080212/Demo/lwIP_AVR32_UC3/main.c b/20080212/Demo/lwIP_AVR32_UC3/main.c
new file mode 100644
index 000000000..342235509
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/main.c
@@ -0,0 +1,145 @@
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief FreeRTOS and lwIP example for AVR32 UC3.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ *****************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/* Environment include files. */
+#include 
+#include 
+#include "pm.h"
+#include "flashc.h"
+
+/* Scheduler include files. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Demo file headers. */
+#include "partest.h"
+#include "serial.h"
+#include "ethernet.h"
+#include "netif/etharp.h"
+#include "flash.h"
+
+/* Priority definitions for most of the tasks in the demo application. */
+#define mainLED_TASK_PRIORITY     ( tskIDLE_PRIORITY + 1 )
+#define mainETH_TASK_PRIORITY     ( tskIDLE_PRIORITY + 1 )
+
+/* Baud rate used by the serial port tasks. */
+#define mainCOM_BAUD_RATE      ( ( unsigned portLONG ) 57600 )
+#define mainCOM_BUFFER_LEN     ( ( unsigned portLONG ) 70 )
+
+/* An address in the internal Flash used to count resets.  This is used to check that
+the demo application is not unexpectedly resetting. */
+#define mainRESET_COUNT_ADDRESS     ( ( void * ) 0xC0000000 )
+
+
+//!
+//! \fn     main
+//! \brief  start the software here
+//!         1) Initialize the microcontroller and the shared hardware resources
+//!         of the board.
+//!         2) Launch the IP modules.
+//!         3) Start FreeRTOS.
+//! \return 42, which should never occur.
+//! \note
+//!
+int main( void )
+{
+volatile avr32_pm_t* pm = &AVR32_PM;
+
+	/* 1) Initialize the microcontroller and the shared hardware resources of the board. */
+
+	/* Switch to external oscillator 0 */
+	pm_switch_to_osc0( pm, FOSC0, OSC0_STARTUP );
+
+	/* Setup PLL0 on OSC0, mul+1=16 ,divisor by 1, lockcount=16, ie. 12Mhzx16/1 = 192MHz output.
+	   Extra div by 2 => 96MHz */
+	pm_pll_setup(pm,	/* volatile avr32_pm_t* pm */
+				0,		/* unsigned int pll */
+				15,		/* unsigned int mul */
+				1,		/* unsigned int div, Sel Osc0/PLL0 or Osc1/Pll1 */
+				0,		/* unsigned int osc */
+				16);		/* unsigned int lockcount */
+
+	pm_pll_set_option( pm, 0,   // pll0
+	                       0,   // Choose the range 160-240MHz.
+	                       1,   // div2
+	                       0 ); // wbwdisable
+
+	/* Enable PLL0 */
+	pm_pll_enable(pm,0);
+
+	/* Wait for PLL0 locked */
+	pm_wait_for_pll0_locked(pm) ;
+
+	/* Setup generic clock number 2 on PLL, with OSC0/PLL0, no divisor */
+	pm_gc_setup(pm,
+				0,
+				1, /* Use Osc (=0) or PLL (=1) */
+				0, /* Sel Osc0/PLL0 or Osc1/Pll1 */
+				0,
+				1);
+
+	/* Enable Generic clock 0*/
+	pm_gc_enable(pm, 0);
+
+	/* switch to clock */
+	pm_cksel( pm, 1, 1, 1, 0, 1, 0 );
+	flashc_set_wait_state( 1 );
+	pm_switch_to_clock( pm, AVR32_PM_MCCTRL_MCSEL_PLL0 );
+
+	/* Setup the LED's for output. */
+	vParTestInitialise();
+
+	/* Start the flash tasks just to provide visual feedback that the demo is
+	executing. */
+	vStartLEDFlashTasks( mainLED_TASK_PRIORITY );
+
+	/* 2) Start ethernet task. */
+	vStartEthernetTask( mainETH_TASK_PRIORITY );
+
+	/* 3) Start FreeRTOS. */
+	vTaskStartScheduler();
+
+	/* Will only reach here if there was insufficient memory to create the idle task. */
+
+	return 0;
+}
+/*-----------------------------------------------------------*/
diff --git a/20080212/Demo/lwIP_AVR32_UC3/printf-stdarg.c b/20080212/Demo/lwIP_AVR32_UC3/printf-stdarg.c
new file mode 100644
index 000000000..b4fca6450
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/printf-stdarg.c
@@ -0,0 +1,313 @@
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief sprintf functions to replace newlib for AVR32 UC3.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ *****************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+	Copyright 2001, 2002 Georges Menie (www.menie.org)
+	stdarg version contributed by Christian Ettinger
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU Lesser General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU Lesser General Public License for more details.
+
+    You should have received a copy of the GNU Lesser General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+
+/*
+	putchar is the only external dependency for this file,
+	if you have a working putchar, leave it commented out.
+	If not, uncomment the define below and
+	replace outbyte(c) by your own function call.
+
+#define putchar(c) outbyte(c)
+*/
+
+#include 
+#include 
+
+
+static void printchar(char **str, int c)
+{
+	extern int putchar(int c);
+	
+	if (str) {
+		**str = c;
+		++(*str);
+	}
+	else (void)putchar(c);
+}
+
+#define PAD_RIGHT 1
+#define PAD_ZERO 2
+
+static int prints(char **out, const char *string, int width, int pad)
+{
+	register int pc = 0, padchar = ' ';
+
+	if (width > 0) {
+		register int len = 0;
+		register const char *ptr;
+		for (ptr = string; *ptr; ++ptr) ++len;
+		if (len >= width) width = 0;
+		else width -= len;
+		if (pad & PAD_ZERO) padchar = '0';
+	}
+	if (!(pad & PAD_RIGHT)) {
+		for ( ; width > 0; --width) {
+			printchar (out, padchar);
+			++pc;
+		}
+	}
+	for ( ; *string ; ++string) {
+		printchar (out, *string);
+		++pc;
+	}
+	for ( ; width > 0; --width) {
+		printchar (out, padchar);
+		++pc;
+	}
+
+	return pc;
+}
+
+/* the following should be enough for 32 bit int */
+#define PRINT_BUF_LEN 12
+
+static int printi(char **out, int i, int b, int sg, int width, int pad, int letbase)
+{
+	char print_buf[PRINT_BUF_LEN];
+	register char *s;
+	register int t, neg = 0, pc = 0;
+	register unsigned int u = i;
+
+	if (i == 0) {
+		print_buf[0] = '0';
+		print_buf[1] = '\0';
+		return prints (out, print_buf, width, pad);
+	}
+
+	if (sg && b == 10 && i < 0) {
+		neg = 1;
+		u = -i;
+	}
+
+	s = print_buf + PRINT_BUF_LEN-1;
+	*s = '\0';
+
+	while (u) {
+		t = u % b;
+		if( t >= 10 )
+			t += letbase - '0' - 10;
+		*--s = t + '0';
+		u /= b;
+	}
+
+	if (neg) {
+		if( width && (pad & PAD_ZERO) ) {
+			printchar (out, '-');
+			++pc;
+			--width;
+		}
+		else {
+			*--s = '-';
+		}
+	}
+
+	return pc + prints (out, s, width, pad);
+}
+
+int fprintf(__FILE *stream, const char *format, ...)
+{
+return 0;
+}
+static int print(char **out, const char *format, va_list args )
+{
+	register int width, pad;
+	register int pc = 0;
+	char scr[2];
+
+	for (; *format != 0; ++format) {
+		if (*format == '%') {
+			++format;
+			width = pad = 0;
+			if (*format == '\0') break;
+			if (*format == '%') goto out;
+			if (*format == '-') {
+				++format;
+				pad = PAD_RIGHT;
+			}
+			while (*format == '0') {
+				++format;
+				pad |= PAD_ZERO;
+			}
+			for ( ; *format >= '0' && *format <= '9'; ++format) {
+				width *= 10;
+				width += *format - '0';
+			}
+			if( *format == 's' ) {
+				register char *s = (char *)va_arg( args, int );
+				pc += prints (out, s?s:"(null)", width, pad);
+				continue;
+			}
+			if( *format == 'd' ) {
+				pc += printi (out, va_arg( args, int ), 10, 1, width, pad, 'a');
+				continue;
+			}
+			if( *format == 'x' ) {
+				pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'a');
+				continue;
+			}
+			if( *format == 'X' ) {
+				pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'A');
+				continue;
+			}
+			if( *format == 'u' ) {
+				pc += printi (out, va_arg( args, int ), 10, 0, width, pad, 'a');
+				continue;
+			}
+			if( *format == 'c' ) {
+				/* char are converted to int then pushed on the stack */
+				scr[0] = (char)va_arg( args, int );
+				scr[1] = '\0';
+				pc += prints (out, scr, width, pad);
+				continue;
+			}
+		}
+		else {
+		out:
+			printchar (out, *format);
+			++pc;
+		}
+	}
+	if (out) **out = '\0';
+	va_end( args );
+	return pc;
+}
+
+int printk(const char *format, ...)
+{
+        va_list args;
+        
+        va_start( args, format );
+        return print( 0, format, args );
+}
+
+int sprintf(char *out, const char *format, ...)
+{
+        va_list args;
+        
+        va_start( args, format );
+        return print( &out, format, args );
+}
+
+#ifdef TEST_PRINTF
+int main(void)
+{
+	char *ptr = "Hello world!";
+	char *np = 0;
+	int i = 5;
+	unsigned int bs = sizeof(int)*8;
+	int mi;
+	char buf[80];
+
+	mi = (1 << (bs-1)) + 1;
+	printf("%s\n", ptr);
+	printf("printf test\n");
+	printf("%s is null pointer\n", np);
+	printf("%d = 5\n", i);
+	printf("%d = - max int\n", mi);
+	printf("char %c = 'a'\n", 'a');
+	printf("hex %x = ff\n", 0xff);
+	printf("hex %02x = 00\n", 0);
+	printf("signed %d = unsigned %u = hex %x\n", -3, -3, -3);
+	printf("%d %s(s)%", 0, "message");
+	printf("\n");
+	printf("%d %s(s) with %%\n", 0, "message");
+	sprintf(buf, "justif: \"%-10s\"\n", "left"); printf("%s", buf);
+	sprintf(buf, "justif: \"%10s\"\n", "right"); printf("%s", buf);
+	sprintf(buf, " 3: %04d zero padded\n", 3); printf("%s", buf);
+	sprintf(buf, " 3: %-4d left justif.\n", 3); printf("%s", buf);
+	sprintf(buf, " 3: %4d right justif.\n", 3); printf("%s", buf);
+	sprintf(buf, "-3: %04d zero padded\n", -3); printf("%s", buf);
+	sprintf(buf, "-3: %-4d left justif.\n", -3); printf("%s", buf);
+	sprintf(buf, "-3: %4d right justif.\n", -3); printf("%s", buf);
+
+	return 0;
+}
+
+/*
+ * if you compile this file with
+ *   gcc -Wall $(YOUR_C_OPTIONS) -DTEST_PRINTF -c printf.c
+ * you will get a normal warning:
+ *   printf.c:214: warning: spurious trailing `%' in format
+ * this line is testing an invalid % at the end of the format string.
+ *
+ * this should display (on 32bit int machine) :
+ *
+ * Hello world!
+ * printf test
+ * (null) is null pointer
+ * 5 = 5
+ * -2147483647 = - max int
+ * char a = 'a'
+ * hex ff = ff
+ * hex 00 = 00
+ * signed -3 = unsigned 4294967293 = hex fffffffd
+ * 0 message(s)
+ * 0 message(s) with %
+ * justif: "left      "
+ * justif: "     right"
+ *  3: 0003 zero padded
+ *  3: 3    left justif.
+ *  3:    3 right justif.
+ * -3: -003 zero padded
+ * -3: -3   left justif.
+ * -3:   -3 right justif.
+ */
+
+#endif
diff --git a/20080212/Demo/lwIP_AVR32_UC3/readme.html b/20080212/Demo/lwIP_AVR32_UC3/readme.html
new file mode 100644
index 000000000..b625a06fe
--- /dev/null
+++ b/20080212/Demo/lwIP_AVR32_UC3/readme.html
@@ -0,0 +1,80 @@
+
+
+   
+      
+   
+   
+
Back to the SERVICES main page

+
AVR®32 AT32UC3 Series Software Framework: Basic Web server and TFTP server example.

+

+
+
Copyright © 2007 Atmel Corporation

+
+
Introduction

+    
This example implements a basic Web server and a basic TFTP server.
+    It is running on top of the lwIP TCP/IP stack and the AVR32 UC3 freeRTOS.org port.

+    
This example thus contains a port of the lwIP TCP/IP stack. This port is using both the AVR32 UC3 freeRTOS.org port and the AVR32 UC3A MACB interface for the Ethernet access.
  
+
+
 

+
+
lwIP TCP/IP stack

+    
lwIP is an implementation of the TCP/IP protocol suite. The focus of the lwIP TCP/IP implementation is to reduce resource usage while still having a full scale TCP.

+    
lwIP features:
+    
  • IP (Internet Protocol) including packet forwarding over multiple network interfaces
    • 
+    
  • ICMP (Internet Control Message Protocol) for network maintenance and debugging
    • 
+    
  • UDP (User Datagram Protocol) including experimental UDP-lite extensions
    • 
+    
  • TCP (Transmission Control Protocol) with congestion control, RTT estimation and fast recovery/fast retransmit
    • 
+    
  • Specialized raw API for enhanced performance
    • 
+    
  • Optional Berkeley-alike socket API
    • 
+    
  • DHCP (Dynamic Host Configuration Protocol)
    • 
+    
  • PPP (Point-to-Point Protocol)
    • 
+    
  • ARP (Address Resolution Protocol) for Ethernet
    • 
+
    lwIP is freely available (under a BSD-style license) in C source code format and can be downloaded from the development homepage.
    
+
     
    
+
+
    The Basic Web server
    
+    
    Implements a simplistic WEB server. To use this demo part, define HTTP_USED to 1, else define to 0. (default is 1)
    
+    Demo description: Every time a connection is made and data is received, a dynamic page that shows the current FreeRTOS.org kernel statistics is generated and returned. The connection is then closed.
    
+    Note: The WEB server is reachable at the IP address 192.168.0.2.
+
+
     
    
+
+
    The Basic TFTP server
    
+    
    Implements a simplistic TFTP server. To use this demo part, define TFTP_USED to 1, else define to 0. (default is 1)
    
+    
    Demo description: 
+    
  • To put a file onto the TFTP server (Supported file size < 2048 bytes), on a PC command line type tftp 192.168.0.2 PUT "a_file": this will copy a_file from your hard drive to a RAM buffer of the demo.
    • 
+    
  • To get a file from the TFTP server, on a PC command line type tftp 192.168.0.2 GET "a_file": this will copy a_file from the RAM buffer of the application to the PC's hard drive.
    • 
+    Note 1: only one file at a time is supported on this TFTP server. This is because the TFTP server being a simplistic example, it does not use a file system to store files but a predefined RAM area of 2048 Bytes.
+    
    Note 2: The TFTP server is reachable at the IP address 192.168.0.2.
     
+
+
     
    
+
+
    The Basic SMTP client
    
+    
    Implements a simplistic SMTP client. To use this demo part, define SMTP_USED to 1, else define to 0. (default is 0)
    
+    
    Demo description: 
+    
  • Prior to compile and run the SMTP client, you will have to configure the connection settings :
+    
  • Server address : default is 192.168.0.1.
    • 
+    
  • Server name : used in the EHLO field, default is smtp.domain.com.
    • 
+    
  • Mail sender : used in the mailfrom field, default is sender@domain.com.
    • 
+    
  • Mail recipient : used in the mailto field, default is receiver@domain.com.
    • 
+    
  • Mail content : default is Subject: *** SPAM ***\r\nFROM: \"Your Name here\" \r\nTO: \"Your Contact here\" \r\n\r\nSay what you want here.
    • 
+    
    • 
+    
  • Once all fields are configured, remove the #error lines to allow compilation.
    • 
+    
  • Run the software and press Push Button 0 to send an email.
    • 
+
+
     
    
+
+
    Device Info
    
+    All AVR32 UC3A devices with a MACB module can be used. This example has been tested with the following setup(s):
+    
  • AT32UC3A0512 on the EVK1100 evaluation kit.
    • 
+    
+
     
    
+
+
+
    
+
+    
    AVR is a registered trademark of
+    Atmel Corporation.
    
+
+   
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/AT91SAM7S256_MemoryMap.xml b/20080212/Demo/lwIP_Demo_Rowley_ARM7/AT91SAM7S256_MemoryMap.xml
new file mode 100644
index 000000000..a8d8820fb
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/AT91SAM7S256_MemoryMap.xml
@@ -0,0 +1,3038 @@
+
+
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+  
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/AT91SAM7_Startup.s b/20080212/Demo/lwIP_Demo_Rowley_ARM7/AT91SAM7_Startup.s
new file mode 100644
index 000000000..ba5c46218
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/AT91SAM7_Startup.s
@@ -0,0 +1,173 @@
+/*****************************************************************************
+  Exception handlers and startup code for ATMEL AT91SAM7.
+
+  Copyright (c) 2004 Rowley Associates Limited.
+
+  This file may be distributed under the terms of the License Agreement
+  provided with this software. 
+ 
+  THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE
+  WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *****************************************************************************/
+
+#define REG_BASE 0xFFFFF000
+#define CKGR_MOR_OFFSET 0xC20
+#define CKGR_PLLR_OFFSET 0xC2C
+#define PMC_MCKR_OFFSET 0xC30
+#define PMC_SR_OFFSET 0xC68
+#define WDT_MR_OFFSET 0xD44
+#define MC_RCR_OFFSET 0xF00
+#define MC_FMR_OFFSET 0xF60
+
+#define CKGR_MOR_MOSCEN (1 << 0)
+#define CKGR_MOR_OSCBYPASS (1 << 1)
+#define CKGR_MOR_OSCOUNT_BIT_OFFSET (8)
+
+#define CKGR_PLLR_DIV_BIT_OFFSET (0)
+#define CKGR_PLLR_PLLCOUNT_BIT_OFFSET (8)
+#define CKGR_PLLR_OUT_BIT_OFFSET (14)
+#define CKGR_PLLR_MUL_BIT_OFFSET (16)
+#define CKGR_PLLR_USBDIV_BIT_OFFSET (28)
+
+#define PMC_MCKR_CSS_MAIN_CLOCK (0x1)
+#define PMC_MCKR_CSS_PLL_CLOCK (0x3)
+#define PMC_MCKR_PRES_CLK (0)
+#define PMC_MCKR_PRES_CLK_2 (1 << 2)
+#define PMC_MCKR_PRES_CLK_4 (2 << 2)
+#define PMC_MCKR_PRES_CLK_8 (3 << 2)
+#define PMC_MCKR_PRES_CLK_16 (4 << 2)
+#define PMC_MCKR_PRES_CLK_32 (5 << 2)
+#define PMC_MCKR_PRES_CLK_64 (6 << 2)
+
+#define PMC_SR_MOSCS (1 << 0)
+#define PMC_SR_LOCK (1 << 2)
+#define PMC_SR_MCKRDY (1 << 3)
+#define PMC_SR_PCKRDY0 (1 << 8)
+#define PMC_SR_PCKRDY1 (1 << 9)
+#define PMC_SR_PCKRDY2 (1 << 10)
+
+#define MC_RCR_RCB (1 << 0)
+
+#define MC_FMR_FWS_0FWS (0)
+#define MC_FMR_FWS_1FWS (1 << 8)
+#define MC_FMR_FWS_2FWS (2 << 8)
+#define MC_FMR_FWS_3FWS (3 << 8)
+#define MC_FMR_FMCN_BIT_OFFSET 16
+
+#define WDT_MR_WDDIS (1 << 15)
+
+  .section .vectors, "ax"
+  .code 32
+  .align 0
+  
+/*****************************************************************************
+  Exception Vectors
+ *****************************************************************************/
+_vectors:
+  ldr pc, [pc, #reset_handler_address - . - 8]  /* reset */
+  ldr pc, [pc, #undef_handler_address - . - 8]  /* undefined instruction */
+  ldr pc, [pc, #swi_handler_address - . - 8]    /* swi handler */
+  ldr pc, [pc, #pabort_handler_address - . - 8] /* abort prefetch */
+  ldr pc, [pc, #dabort_handler_address - . - 8] /* abort data */
+  nop
+  ldr pc, [PC, #-0xF20]    /* irq */
+  ldr pc, [pc, #fiq_handler_address - . - 8]    /* fiq */
+
+reset_handler_address:
+  .word reset_handler
+undef_handler_address:
+  .word undef_handler
+swi_handler_address:
+  .word swi_handler
+pabort_handler_address:
+  .word pabort_handler
+dabort_handler_address:
+  .word dabort_handler
+irq_handler_address:
+  .word irq_handler
+fiq_handler_address:
+  .word fiq_handler
+
+  .section .init, "ax"
+  .code 32
+  .align 0
+
+/******************************************************************************
+  Reset handler
+ ******************************************************************************/
+reset_handler:
+
+
+  ldr r10, =REG_BASE
+
+  /* Set up FLASH wait state */
+  ldr r0, =(50 << MC_FMR_FMCN_BIT_OFFSET) | MC_FMR_FWS_1FWS
+  str r0, [r10, #MC_FMR_OFFSET]
+
+  /* Disable Watchdog */
+  ldr r0, =WDT_MR_WDDIS
+  str r0, [r10, #WDT_MR_OFFSET]
+
+  /* Enable the main oscillator */
+  ldr r0, =(6 << CKGR_MOR_OSCOUNT_BIT_OFFSET) | CKGR_MOR_MOSCEN
+  str r0, [r10, #CKGR_MOR_OFFSET]
+  
+1:/* Wait for main oscillator to stabilize */
+  ldr r0, [r10, #PMC_SR_OFFSET]
+  tst r0, #PMC_SR_MOSCS
+  beq 1b
+
+  /* Set up the PLL */
+  ldr r0, =(5 << CKGR_PLLR_DIV_BIT_OFFSET) | (28 << CKGR_PLLR_PLLCOUNT_BIT_OFFSET) | (25 << CKGR_PLLR_MUL_BIT_OFFSET)
+  str r0, [r10, #CKGR_PLLR_OFFSET]
+  
+1:/* Wait for PLL to lock */
+  ldr r0, [r10, #PMC_SR_OFFSET]
+  tst r0, #PMC_SR_LOCK
+  beq 1b
+
+  /* Select PLL as clock source */
+  ldr r0, =(PMC_MCKR_CSS_PLL_CLOCK | PMC_MCKR_PRES_CLK_2)
+  str r0, [r10, #PMC_MCKR_OFFSET]
+  
+#ifdef __FLASH_BUILD
+  /* Copy exception vectors into Internal SRAM */
+  mov r8, #0x00200000
+  ldr r9, =_vectors
+  ldmia r9!, {r0-r7}
+  stmia r8!, {r0-r7}
+  ldmia r9!, {r0-r6}
+  stmia r8!, {r0-r6}
+
+  /* Remap Internal SRAM to 0x00000000 */
+  ldr r0, =MC_RCR_RCB
+  strb r0, [r10, #MC_RCR_OFFSET]
+#endif
+
+
+  /* Jump to the default C runtime startup code. */
+  b _start
+
+/******************************************************************************
+  Default exception handlers
+  (These are declared weak symbols so they can be redefined in user code)
+ ******************************************************************************/
+undef_handler:
+  b undef_handler
+  
+swi_handler:
+  b swi_handler
+  
+pabort_handler:
+  b pabort_handler
+  
+dabort_handler:
+  b dabort_handler
+  
+irq_handler:
+  b irq_handler
+  
+fiq_handler:
+  b fiq_handler
+
+  .weak undef_handler, swi_handler, pabort_handler, dabort_handler, irq_handler, fiq_handler
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/AT91SAM7_Target.js b/20080212/Demo/lwIP_Demo_Rowley_ARM7/AT91SAM7_Target.js
new file mode 100644
index 000000000..d7cbc435d
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/AT91SAM7_Target.js
@@ -0,0 +1,61 @@
+/******************************************************************************
+  Target Script for ATMEL AT91SAM7.
+
+  Copyright (c) 2004 Rowley Associates Limited.
+
+  This file may be distributed under the terms of the License Agreement
+  provided with this software.
+
+  THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE
+  WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ ******************************************************************************/
+
+function Reset()
+{
+  /* Reset and stop target */
+  TargetInterface.pokeWord(0xFFFFFD00, 0xA500000D); // RSTC_CR
+  TargetInterface.waitForDebugState(1000);
+  /* Configure Clock */
+  TargetInterface.pokeWord(0xFFFFFC20, 0x00000601); // CKGR_MOR
+  TargetInterface.delay(10);
+  TargetInterface.pokeWord(0xFFFFFC2C, 0x00191C05); // CKGR_PLLR
+  TargetInterface.delay(10);
+  TargetInterface.pokeWord(0xFFFFFC30, 0x00000007); // CKGR_MCKR
+  TargetInterface.delay(10);
+}
+
+function RAMReset()
+{
+  Reset();
+  /* Remap SRAM to 0x00000000 */
+  TargetInterface.pokeWord(0xFFFFFF00, 1); // MC_RCR 
+}
+
+function FLASHReset()
+{
+  Reset();
+
+// Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF;
+	
+    TargetInterface.pokeWord(0xffffffff,0xFFFFF124);
+    TargetInterface.pokeWord(0xffffffff,0xFFFFF128);
+// disable peripheral clock  Peripheral Clock Disable Register
+    TargetInterface.pokeWord(0xffffffff,0xFFFFFC14);
+
+// #define AT91C_TC0_SR    ((AT91_REG *) 	0xFFFA0020) // (TC0) Status Register
+// #define AT91C_TC1_SR    ((AT91_REG *) 	0xFFFA0060) // (TC1) Status Register
+// #define AT91C_TC2_SR    ((AT91_REG *) 	0xFFFA00A0) // (TC2) Status Register
+    TargetInterface.peekWord(0xFFFA0020);
+    TargetInterface.peekWord(0xFFFA0060);
+    TargetInterface.peekWord(0xFFFA00A0);
+
+//    for (__mac_i=0;__mac_i < 8; __mac_i++)
+//    {
+      // AT91C_BASE_AIC->AIC_EOICR
+//      __mac_pt  =  TargetInterface.peekWord(0xFFFFF130);
+    
+//    }
+//   __message "------------------------------- AIC 2 INIT ---------------------------------------------";  
+
+}
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/BasicWEB.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/BasicWEB.c
new file mode 100644
index 000000000..93febec38
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/BasicWEB.c
@@ -0,0 +1,230 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+/*
+	Implements a simplistic WEB server.  Every time a connection is made and
+	data is received a dynamic page that shows the current TCP/IP statistics
+	is generated and returned.  The connection is then closed.
+
+	This file was adapted from a FreeRTOS lwIP slip demo supplied by a third
+	party.
+*/
+
+/*
+	Changes from V3.2.2
+
+	+ Changed the page returned by the lwIP WEB server demo to display the 
+	  task status table rather than the TCP/IP statistics.
+*/
+
+
+/* Standard includes. */
+#include 
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "semphr.h"
+
+/* Demo includes. */
+#include "BasicWEB.h"
+#include "SAM7_EMAC.h"
+
+/* lwIP includes. */
+#include "lwip/api.h" 
+#include "lwip/tcpip.h"
+#include "lwip/memp.h" 
+#include "lwip/stats.h"
+#include "netif/loopif.h"
+
+/* The size of the buffer in which the dynamic WEB page is created. */
+#define webMAX_PAGE_SIZE	2048
+
+/* Standard GET response. */
+#define webHTTP_OK	"HTTP/1.0 200 OK\r\nContent-type: text/html\r\n\r\n"
+
+/* The port on which we listen. */
+#define webHTTP_PORT		( 80 )
+
+/* Delay on close error. */
+#define webSHORT_DELAY		( 10 )
+
+/* Format of the dynamic page that is returned on each connection. */
+#define webHTML_START \
+"\
+\
+\
+\
+\r\nPage Hits = "
+
+#define webHTML_END \
+"\r\n
    \ +\r\n\ +" + +/*------------------------------------------------------------*/ + +/* + * Process an incoming connection on port 80. + * + * This simply checks to see if the incoming data contains a GET request, and + * if so sends back a single dynamically created page. The connection is then + * closed. A more complete implementation could create a task for each + * connection. + */ +static void vProcessConnection( struct netconn *pxNetCon ); + +/*------------------------------------------------------------*/ + +static void vProcessConnection( struct netconn *pxNetCon ) +{ +static portCHAR cDynamicPage[ webMAX_PAGE_SIZE ], cPageHits[ 11 ]; +struct netbuf *pxRxBuffer; +portCHAR *pcRxString; +unsigned portSHORT usLength; +static unsigned portLONG ulPageHits = 0; + + /* We expect to immediately get data. */ + pxRxBuffer = netconn_recv( pxNetCon ); + + if( pxRxBuffer != NULL ) + { + /* Where is the data? */ + netbuf_data( pxRxBuffer, ( void * ) &pcRxString, &usLength ); + + /* Is this a GET? We don't handle anything else. */ + if( !strncmp( pcRxString, "GET", 3 ) ) + { + pcRxString = cDynamicPage; + + /* Update the hit count. */ + ulPageHits++; + sprintf( cPageHits, "%lu", ulPageHits ); + + /* Write out the HTTP OK header. */ + netconn_write(pxNetCon, webHTTP_OK, (u16_t)strlen( webHTTP_OK ), NETCONN_COPY ); + + /* Generate the dynamic page... + + ... First the page header. */ + strcpy( cDynamicPage, webHTML_START ); + /* ... Then the hit count... */ + strcat( cDynamicPage, cPageHits ); + strcat( cDynamicPage, "

    Task          State  Priority  Stack	#
    ************************************************
    " );
+			/* ... Then the list of tasks and their status... */
+			vTaskList( ( signed portCHAR * ) cDynamicPage + strlen( cDynamicPage ) );	
+			/* ... Finally the page footer. */
+			strcat( cDynamicPage, webHTML_END );
+
+			/* Write out the dynamically generated page. */
+			netconn_write(pxNetCon, cDynamicPage, (u16_t)strlen( cDynamicPage ), NETCONN_COPY );
+		}
+ 
+		netbuf_delete( pxRxBuffer );
+	}
+
+	netconn_close( pxNetCon );
+}
+/*------------------------------------------------------------*/
+
+void vlwIPInit( void )
+{
+    /* Initialize lwIP and its interface layer. */
+	sys_init();
+	mem_init();								
+	memp_init();
+	pbuf_init(); 
+	netif_init();
+	ip_init();
+	tcpip_init( NULL, NULL );
+}
+/*------------------------------------------------------------*/
+
+void vBasicWEBServer( void *pvParameters )
+{
+struct netconn *pxHTTPListener, *pxNewConnection;
+struct ip_addr xIpAddr, xNetMast, xGateway;
+extern err_t ethernetif_init( struct netif *netif );
+static struct netif EMAC_if;
+
+	/* Parameters are not used - suppress compiler error. */
+	( void ) pvParameters;
+
+
+	/* Create and configure the EMAC interface. */
+	IP4_ADDR(&xIpAddr,emacIPADDR0,emacIPADDR1,emacIPADDR2,emacIPADDR3);
+	IP4_ADDR(&xNetMast,emacNET_MASK0,emacNET_MASK1,emacNET_MASK2,emacNET_MASK3);
+	IP4_ADDR(&xGateway,emacGATEWAY_ADDR0,emacGATEWAY_ADDR1,emacGATEWAY_ADDR2,emacGATEWAY_ADDR3);
+	netif_add(&EMAC_if, &xIpAddr, &xNetMast, &xGateway, NULL, ethernetif_init, tcpip_input);
+
+	/* make it the default interface */
+    netif_set_default(&EMAC_if);
+
+	/* bring it up */
+    netif_set_up(&EMAC_if);
+	
+	/* Create a new tcp connection handle */
+
+ 	pxHTTPListener = netconn_new( NETCONN_TCP );
+	netconn_bind(pxHTTPListener, NULL, webHTTP_PORT );
+	netconn_listen( pxHTTPListener );
+
+	/* Loop forever */
+	for( ;; )
+	{
+		/* Wait for connection. */
+		pxNewConnection = netconn_accept(pxHTTPListener);
+
+		if(pxNewConnection != NULL)
+		{
+			/* Service connection. */
+			vProcessConnection( pxNewConnection );
+			while( netconn_delete( pxNewConnection ) != ERR_OK )
+			{
+				vTaskDelay( webSHORT_DELAY );
+			}
+		}
+	}
+}
+
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/BasicWEB.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/BasicWEB.h
new file mode 100644
index 000000000..6006fefd2
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/BasicWEB.h
@@ -0,0 +1,53 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+#ifndef BASIC_WEB_SERVER_H
+#define BASIC_WEB_SERVER_H
+
+/* The function that implements the WEB server task. */
+void vBasicWEBServer( void *pvParameters );
+
+/* Initialisation required by lwIP. */
+void vlwIPInit( void );
+
+#endif
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/Board.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/Board.h
new file mode 100644
index 000000000..f3ae3c11d
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/Board.h
@@ -0,0 +1,68 @@
+/*----------------------------------------------------------------------------
+*         ATMEL Microcontroller Software Support  -  ROUSSET  -
+*----------------------------------------------------------------------------
+* The software is delivered "AS IS" without warranty or condition of any
+* kind, either express, implied or statutory. This includes without
+* limitation any warranty or condition with respect to merchantability or
+* fitness for any particular purpose, or against the infringements of
+* intellectual property rights of others.
+*----------------------------------------------------------------------------
+* File Name           : Board.h
+* Object              : AT91SAM7X Evaluation Board Features Definition File.
+*
+* Creation            : JG   20/Jun/2005
+*----------------------------------------------------------------------------
+*/
+#ifndef Board_h
+#define Board_h
+
+#include "AT91SAM7X256.h"
+#include "ioat91sam7x256.h"
+
+#define true	-1
+#define false	0
+
+/*-------------------------------*/
+/* SAM7Board Memories Definition */
+/*-------------------------------*/
+// The AT91SAM7X128 embeds a 32-Kbyte SRAM bank, and 128K-Byte Flash
+
+#define  FLASH_PAGE_NB		256
+#define  FLASH_PAGE_SIZE	128
+
+/*-----------------*/
+/* Leds Definition */
+/*-----------------*/
+#define LED1            (1<<19)	// PB19
+#define LED2            (1<<20)	// PB20
+#define LED3            (1<<21)	// PB21
+#define LED4            (1<<22)	// PB22
+#define NB_LED			4
+
+#define LED_MASK        (LED1|LED2|LED3|LED4)
+
+/*-------------------------*/
+/* Push Buttons Definition */
+/*-------------------------*/
+
+#define SW1_MASK        (1<<21)	// PA21
+#define SW2_MASK        (1<<22)	// PA22
+#define SW3_MASK        (1<<23)	// PA23
+#define SW4_MASK        (1<<24)	// PA24
+#define SW_MASK         (SW1_MASK|SW2_MASK|SW3_MASK|SW4_MASK)
+
+
+#define SW1 	(1<<21)	// PA21
+#define SW2 	(1<<22)	// PA22
+#define SW3 	(1<<23)	// PA23
+#define SW4 	(1<<24)	// PA24
+
+/*--------------*/
+/* Master Clock */
+/*--------------*/
+
+#define EXT_OC          18432000   // Exetrnal ocilator MAINCK
+#define MCK             47923200   // MCK (PLLRC div by 2)
+#define MCKKHz          (MCK/1000) //
+
+#endif /* Board_h */
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/Cstartup_SAM7.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/Cstartup_SAM7.c
new file mode 100644
index 000000000..d9716c0ef
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/Cstartup_SAM7.c
@@ -0,0 +1,69 @@
+//*----------------------------------------------------------------------------
+//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
+//*----------------------------------------------------------------------------
+//* The software is delivered "AS IS" without warranty or condition of any
+//* kind, either express, implied or statutory. This includes without
+//* limitation any warranty or condition with respect to merchantability or
+//* fitness for any particular purpose, or against the infringements of
+//* intellectual property rights of others.
+//*----------------------------------------------------------------------------
+//* File Name           : Cstartup_SAM7.c
+//* Object              : Low level initializations written in C for IAR
+//*                       tools
+//* 1.0   08/Sep/04 JPP	: Creation
+//* 1.10  10/Sep/04 JPP : Update AT91C_CKGR_PLLCOUNT filed
+//*----------------------------------------------------------------------------
+
+
+// Include the board file description
+#include "Board.h"
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_LowLevelInit
+//* \brief This function performs very low level HW initialization
+//*        this function can be use a Stack, depending the compilation
+//*        optimization mode
+//*----------------------------------------------------------------------------
+void AT91F_LowLevelInit( void);
+void AT91F_LowLevelInit( void )
+{
+ AT91PS_PMC     pPMC = AT91C_BASE_PMC;
+
+    //* Set Flash Waite sate
+	//  Single Cycle Access at Up to 30 MHz, or 40
+	//  if MCK = 47923200 I have 50 Cycle for 1 useconde ( flied MC_FMR->FMCN
+	    AT91C_BASE_MC->MC_FMR = ((AT91C_MC_FMCN)&(75 <<16)) | AT91C_MC_FWS_1FWS ;
+
+    //* Watchdog Disable
+        AT91C_BASE_WDTC->WDTC_WDMR= AT91C_WDTC_WDDIS;
+
+	//* Set MCK at 47 923 200
+    // 1 Enabling the Main Oscillator:
+        // SCK = 1/32768 = 30.51 uSeconde
+    	// Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms
+       pPMC->PMC_MOR = ((( AT91C_CKGR_OSCOUNT & (0x06 <<8)) | AT91C_CKGR_MOSCEN ));
+        // Wait the startup time
+        while(!(pPMC->PMC_SR & AT91C_PMC_MOSCS));
+	// 2 Checking the Main Oscillator Frequency (Optional)
+	// 3 Setting PLL and divider:
+		// - div by 5 Fin = 3,6864 =(18,432 / 5)
+		// - Mul 25+1: Fout =	95,8464 =(3,6864 *26)
+		// for 96 MHz the erroe is 0.16%
+		//eld out NOT USED = 0 Fi
+       pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 5) |
+                         (AT91C_CKGR_PLLCOUNT & (28<<8)) |
+                         (AT91C_CKGR_MUL & (25<<16)));
+
+        // Wait the startup time
+        while(!(pPMC->PMC_SR & AT91C_PMC_LOCK));
+	// 4. Selection of Master Clock and Processor Clock
+        // select the PLL clock divided by 2
+       pPMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2 ;
+        while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
+
+        pPMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK ;
+        while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
+}
+
+
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/EMAC/Emac.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/EMAC/Emac.h
new file mode 100644
index 000000000..6523e6868
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/EMAC/Emac.h
@@ -0,0 +1,117 @@
+//*----------------------------------------------------------------------------
+//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
+//*----------------------------------------------------------------------------
+//* The software is delivered "AS IS" without warranty or condition of any
+//* kind, either express, implied or statutory. This includes without
+//* limitation any warranty or condition with respect to merchantability or
+//* fitness for any particular purpose, or against the infringements of
+//* intellectual property rights of others.
+//*----------------------------------------------------------------------------
+//* File Name           : Emac.h
+//* Object              : Emac header file
+//* Creation            : Hi   11/18/2002
+//*
+//*----------------------------------------------------------------------------
+#ifndef AT91C_EMAC_H
+#define AT91C_EMAC_H
+
+#include "lwipopts.h"
+
+
+/* Number of receive buffers */
+#define NB_RX_BUFFERS			20
+
+/* Size of each receive buffer - DO NOT CHANGE. */
+#define ETH_RX_BUFFER_SIZE		128         
+
+/* Number of Transmit buffers */
+#define NB_TX_BUFFERS			( MEMP_NUM_PBUF / 2 )	
+
+/* Size of each Transmit buffer. */
+#define ETH_TX_BUFFER_SIZE		( PBUF_POOL_BUFSIZE  )   
+
+/* Receive Transfer descriptor structure */
+typedef struct  _AT91S_RxTdDescriptor {
+	unsigned int addr;
+	union
+	{
+		unsigned int status;
+		struct {
+			unsigned int Length:11;
+			unsigned int Res0:1;
+			unsigned int Rxbuf_off:2;
+			unsigned int StartOfFrame:1;
+			unsigned int EndOfFrame:1;
+			unsigned int Cfi:1;
+			unsigned int VlanPriority:3;
+			unsigned int PriorityTag:1;
+			unsigned int VlanTag:1;
+			unsigned int TypeID:1;
+			unsigned int Sa4Match:1;
+			unsigned int Sa3Match:1;
+			unsigned int Sa2Match:1;
+			unsigned int Sa1Match:1;
+			unsigned int Res1:1;
+			unsigned int ExternalAdd:1;
+			unsigned int UniCast:1;
+			unsigned int MultiCast:1;
+			unsigned int BroadCast:1;
+		}S_Status;		
+	}U_Status;
+}AT91S_RxTdDescriptor, *AT91PS_RxTdDescriptor;
+
+
+/* Transmit Transfer descriptor structure */
+typedef struct _AT91S_TxTdDescriptor {
+	unsigned int addr;
+	union
+	{
+		unsigned int status;
+		struct {
+			unsigned int Length:11;
+			unsigned int Res0:4;
+			unsigned int LastBuff:1;
+			unsigned int NoCrc:1;
+			unsigned int Res1:10;
+			unsigned int BufExhausted:1;
+			unsigned int TransmitUnderrun:1;
+			unsigned int TransmitError:1;
+			unsigned int Wrap:1;
+			unsigned int BuffUsed:1;
+		}S_Status;		
+	}U_Status;
+}AT91S_TxTdDescriptor, *AT91PS_TxTdDescriptor;
+
+#define AT91C_OWNERSHIP_BIT		0x00000001
+
+/* Receive status defintion */
+#define AT91C_BROADCAST_ADDR	((unsigned int) (1 << 31))	//* Broadcat address detected
+#define AT91C_MULTICAST_HASH 	((unsigned int) (1 << 30))	//* MultiCast hash match
+#define AT91C_UNICAST_HASH 	    ((unsigned int) (1 << 29))	//* UniCast hash match
+#define AT91C_EXTERNAL_ADDR	    ((unsigned int) (1 << 28))	//* External Address match
+#define AT91C_SA1_ADDR	    	((unsigned int) (1 << 26))	//* Specific address 1 match
+#define AT91C_SA2_ADDR	    	((unsigned int) (1 << 25))	//* Specific address 2 match
+#define AT91C_SA3_ADDR	    	((unsigned int) (1 << 24))	//* Specific address 3 match
+#define AT91C_SA4_ADDR	    	((unsigned int) (1 << 23))	//* Specific address 4 match
+#define AT91C_TYPE_ID	    	((unsigned int) (1 << 22))	//* Type ID match
+#define AT91C_VLAN_TAG	    	((unsigned int) (1 << 21))	//* VLAN tag detected
+#define AT91C_PRIORITY_TAG    	((unsigned int) (1 << 20))	//* PRIORITY tag detected
+#define AT91C_VLAN_PRIORITY    	((unsigned int) (7 << 17))  //* PRIORITY Mask
+#define AT91C_CFI_IND        	((unsigned int) (1 << 16))  //* CFI indicator
+#define AT91C_EOF           	((unsigned int) (1 << 15))  //* EOF
+#define AT91C_SOF           	((unsigned int) (1 << 14))  //* SOF
+#define AT91C_RBF_OFFSET     	((unsigned int) (3 << 12))  //* Receive Buffer Offset Mask
+#define AT91C_LENGTH_FRAME     	((unsigned int) 0x07FF)     //* Length of frame
+
+/* Transmit Status definition */
+#define AT91C_TRANSMIT_OK		((unsigned int) (1 << 31))	//*
+#define AT91C_TRANSMIT_WRAP		((unsigned int) (1 << 30))	//* Wrap bit: mark the last descriptor
+#define AT91C_TRANSMIT_ERR		((unsigned int) (1 << 29))	//* RLE:transmit error
+#define AT91C_TRANSMIT_UND		((unsigned int) (1 << 28))	//* Transmit Underrun
+#define AT91C_BUF_EX     		((unsigned int) (1 << 27))	//* Buffers exhausted in mid frame
+#define AT91C_TRANSMIT_NO_CRC	((unsigned int) (1 << 16))	//* No CRC will be appended to the current frame
+#define AT91C_LAST_BUFFER    	((unsigned int) (1 << 15))	//*
+
+#define AT91C_EMAC_CLKEN 0x2
+
+#endif //* AT91C_EMAC_H
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/EMAC/SAM7_EMAC.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/EMAC/SAM7_EMAC.c
new file mode 100644
index 000000000..b808699a0
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/EMAC/SAM7_EMAC.c
@@ -0,0 +1,871 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+/*
+ * Interrupt driven driver for the EMAC peripheral.  This driver is not
+ * reentrant, re-entrancy is handled by a semaphore at the network interface
+ * level. 
+ */
+
+
+/*
+Changes from V3.2.2
+
+	+ Corrected the byte order when writing the MAC address to the MAC.
+	+ Support added for MII interfaces.  Previously only RMII was supported.
+
+Changes from V3.2.3
+
+	+ The MII interface is now the default.
+	+ Modified the initialisation sequence slightly to allow auto init more
+	  time to complete.
+
+Changes from V4.0.1
+
+	+ Made the function vClearEMACTxBuffer() more robust by moving the index
+	  manipulation into the if() statement.  This allows the tx interrupt to
+	  execute even when there is no data to handle.
+
+Changes from V4.0.4
+
+	+ Corrected the Rx frame length mask when obtaining the length from the
+	  rx descriptor.
+*/
+
+
+/* Standard includes. */
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "semphr.h"
+#include "task.h"
+
+/* Demo app includes. */
+#include "SAM7_EMAC.h"
+
+/* Hardware specific includes. */
+#include "Emac.h"
+#include "mii.h"
+#include "AT91SAM7X256.h"
+
+
+/* USE_RMII_INTERFACE must be defined as 1 to use an RMII interface, or 0
+to use an MII interface. */
+#define USE_RMII_INTERFACE 0
+
+
+/* The buffer addresses written into the descriptors must be aligned so the
+last few bits are zero.  These bits have special meaning for the EMAC
+peripheral and cannot be used as part of the address. */
+#define emacADDRESS_MASK			( ( unsigned portLONG ) 0xFFFFFFFC )
+
+/* Bit used within the address stored in the descriptor to mark the last
+descriptor in the array. */
+#define emacRX_WRAP_BIT				( ( unsigned portLONG ) 0x02 )
+
+/* Bit used within the Tx descriptor status to indicate whether the
+descriptor is under the control of the EMAC or the software. */
+#define emacTX_BUF_USED				( ( unsigned portLONG ) 0x80000000 )
+
+/* A short delay is used to wait for a buffer to become available, should
+one not be immediately available when trying to transmit a frame. */
+#define emacBUFFER_WAIT_DELAY		( 2 )
+#define emacMAX_WAIT_CYCLES			( ( portBASE_TYPE ) ( configTICK_RATE_HZ / 40 ) )
+
+/* The time to block waiting for input. */
+#define emacBLOCK_TIME_WAITING_FOR_INPUT	( ( portTickType ) 100 )
+
+/* Peripheral setup for the EMAC. */
+#define emacPERIPHERAL_A_SETUP 		( ( unsigned portLONG ) AT91C_PB2_ETX0			) | \
+									( ( unsigned portLONG ) AT91C_PB12_ETXER		) | \
+									( ( unsigned portLONG ) AT91C_PB16_ECOL			) | \
+									( ( unsigned portLONG ) AT91C_PB11_ETX3			) | \
+									( ( unsigned portLONG ) AT91C_PB6_ERX1			) | \
+									( ( unsigned portLONG ) AT91C_PB15_ERXDV		) | \
+									( ( unsigned portLONG ) AT91C_PB13_ERX2			) | \
+									( ( unsigned portLONG ) AT91C_PB3_ETX1			) | \
+									( ( unsigned portLONG ) AT91C_PB8_EMDC			) | \
+									( ( unsigned portLONG ) AT91C_PB5_ERX0			) | \
+									( ( unsigned portLONG ) AT91C_PB14_ERX3			) | \
+									( ( unsigned portLONG ) AT91C_PB4_ECRS_ECRSDV	) | \
+									( ( unsigned portLONG ) AT91C_PB1_ETXEN			) | \
+									( ( unsigned portLONG ) AT91C_PB10_ETX2			) | \
+									( ( unsigned portLONG ) AT91C_PB0_ETXCK_EREFCK	) | \
+									( ( unsigned portLONG ) AT91C_PB9_EMDIO			) | \
+									( ( unsigned portLONG ) AT91C_PB7_ERXER			) | \
+									( ( unsigned portLONG ) AT91C_PB17_ERXCK		);
+
+/* Misc defines. */
+#define emacINTERRUPT_LEVEL			( 5 )
+#define emacNO_DELAY				( 0 )
+#define emacTOTAL_FRAME_HEADER_SIZE	( 54 )
+#define emacPHY_INIT_DELAY			( 5000 / portTICK_RATE_MS )
+#define emacRESET_KEY				( ( unsigned portLONG ) 0xA5000000 )
+#define emacRESET_LENGTH			( ( unsigned portLONG ) ( 0x01 << 8 ) )
+
+/* The Atmel header file only defines the TX frame length mask. */
+#define emacRX_LENGTH_FRAME			( 0xfff )
+
+/*-----------------------------------------------------------*/
+
+/* Buffer written to by the EMAC DMA.  Must be aligned as described by the
+comment above the emacADDRESS_MASK definition. */
+static volatile portCHAR pcRxBuffer[ NB_RX_BUFFERS * ETH_RX_BUFFER_SIZE ] __attribute__ ((aligned (8)));
+
+/* Buffer read by the EMAC DMA.  Must be aligned as described by the comment
+above the emacADDRESS_MASK definition. */
+static portCHAR pcTxBuffer[ NB_TX_BUFFERS * ETH_TX_BUFFER_SIZE ] __attribute__ ((aligned (8)));
+
+/* Descriptors used to communicate between the program and the EMAC peripheral.
+These descriptors hold the locations and state of the Rx and Tx buffers. */
+static volatile AT91S_TxTdDescriptor xTxDescriptors[ NB_TX_BUFFERS ];
+static volatile AT91S_RxTdDescriptor xRxDescriptors[ NB_RX_BUFFERS ];
+
+/* The IP and Ethernet addresses are read from the header files. */
+const portCHAR cMACAddress[ 6 ] = { emacETHADDR0, emacETHADDR1, emacETHADDR2, emacETHADDR3, emacETHADDR4, emacETHADDR5 };
+const unsigned char ucIPAddress[ 4 ]  = { emacIPADDR0, emacIPADDR1, emacIPADDR2, emacIPADDR3 };
+
+/*-----------------------------------------------------------*/
+
+/* See the header file for descriptions of public functions. */
+
+/*
+ * Prototype for the EMAC interrupt function.
+ */
+void vEMACISR_Wrapper( void ) __attribute__ ((naked));
+
+/*
+ * Initialise both the Tx and Rx descriptors used by the EMAC.
+ */
+static void prvSetupDescriptors(void);
+
+/*
+ * Write our MAC address into the EMAC.  
+ */
+static void prvSetupMACAddress( void );
+
+/*
+ * Configure the EMAC and AIC for EMAC interrupts.
+ */
+static void prvSetupEMACInterrupt( void );
+
+/*
+ * Some initialisation functions taken from the Atmel EMAC sample code.
+ */
+static void vReadPHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG *pulValue );
+static portBASE_TYPE xGetLinkSpeed( void );
+static portBASE_TYPE prvProbePHY( void );
+#if USE_RMII_INTERFACE != 1
+	static void vWritePHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG ulValue);
+#endif
+
+
+/* The semaphore used by the EMAC ISR to wake the EMAC task. */
+static xSemaphoreHandle xSemaphore = NULL;
+
+/* Holds the index to the next buffer from which data will be read. */
+static volatile unsigned portLONG ulNextRxBuffer = 0;
+
+/*-----------------------------------------------------------*/
+
+/* See the header file for descriptions of public functions. */
+portLONG lEMACSend( portCHAR *pcFrom, unsigned portLONG ulLength, portLONG lEndOfFrame )
+{
+static unsigned portBASE_TYPE uxTxBufferIndex = 0;
+portBASE_TYPE xWaitCycles = 0;
+portLONG lReturn = pdPASS;
+portCHAR *pcBuffer;
+unsigned portLONG ulLastBuffer, ulDataBuffered = 0, ulDataRemainingToSend, ulLengthToSend;
+
+	/* If the length of data to be transmitted is greater than each individual
+	transmit buffer then the data will be split into more than one buffer.
+	Loop until the entire length has been buffered. */
+	while( ulDataBuffered < ulLength )
+	{
+		/* Is a buffer available? */
+		while( !( xTxDescriptors[ uxTxBufferIndex ].U_Status.status & AT91C_TRANSMIT_OK ) )
+		{
+			/* There is no room to write the Tx data to the Tx buffer.  Wait a
+			short while, then try again. */
+			xWaitCycles++;
+			if( xWaitCycles > emacMAX_WAIT_CYCLES )
+			{
+				/* Give up. */
+				lReturn = pdFAIL;
+				break;
+			}
+			else
+			{
+				vTaskDelay( emacBUFFER_WAIT_DELAY );
+			}
+		}
+	
+		/* lReturn will only be pdPASS if a buffer is available. */
+		if( lReturn == pdPASS )
+		{
+			portENTER_CRITICAL();
+			{
+				/* Get the address of the buffer from the descriptor, then copy 
+				the data into the buffer. */
+				pcBuffer = ( portCHAR * ) xTxDescriptors[ uxTxBufferIndex ].addr;
+
+				/* How much can we write to the buffer? */
+				ulDataRemainingToSend = ulLength - ulDataBuffered;
+				if( ulDataRemainingToSend <= ETH_TX_BUFFER_SIZE )
+				{
+					/* We can write all the remaining bytes. */
+					ulLengthToSend = ulDataRemainingToSend;
+				}
+				else
+				{
+					/* We can not write more than ETH_TX_BUFFER_SIZE in one go. */
+					ulLengthToSend = ETH_TX_BUFFER_SIZE;
+				}
+
+				/* Copy the data into the buffer. */
+				memcpy( ( void * ) pcBuffer, ( void * ) &( pcFrom[ ulDataBuffered ] ), ulLengthToSend );
+				ulDataBuffered += ulLengthToSend;
+
+				/* Is this the last data for the frame? */
+				if( lEndOfFrame && ( ulDataBuffered >= ulLength ) )
+				{
+					/* No more data remains for this frame so we can start the 
+					transmission. */
+					ulLastBuffer = AT91C_LAST_BUFFER;
+				}
+				else
+				{
+					/* More data to come for this frame. */
+					ulLastBuffer = 0;
+				}
+	
+				/* Fill out the necessary in the descriptor to get the data sent, 
+				then move to the next descriptor, wrapping if necessary. */
+				if( uxTxBufferIndex >= ( NB_TX_BUFFERS - 1 ) )
+				{				
+					xTxDescriptors[ uxTxBufferIndex ].U_Status.status = 	( ulLengthToSend & ( unsigned portLONG ) AT91C_LENGTH_FRAME )
+																			| ulLastBuffer
+																			| AT91C_TRANSMIT_WRAP;
+					uxTxBufferIndex = 0;
+				}
+				else
+				{
+					xTxDescriptors[ uxTxBufferIndex ].U_Status.status = 	( ulLengthToSend & ( unsigned portLONG ) AT91C_LENGTH_FRAME )
+																			| ulLastBuffer;
+					uxTxBufferIndex++;
+				}
+	
+				/* If this is the last buffer to be sent for this frame we can
+				start the transmission. */
+				if( ulLastBuffer )
+				{
+					AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TSTART;
+				}
+			}
+			portEXIT_CRITICAL();
+		}
+		else
+		{
+			break;
+		}
+	}
+
+	return lReturn;
+}
+/*-----------------------------------------------------------*/
+
+/* See the header file for descriptions of public functions. */
+unsigned portLONG ulEMACInputLength( void )
+{
+register unsigned portLONG ulIndex, ulLength = 0;
+
+	/* Skip any fragments.  We are looking for the first buffer that contains
+	data and has the SOF (start of frame) bit set. */
+	while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AT91C_OWNERSHIP_BIT ) && !( xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AT91C_SOF ) )
+	{
+		/* Ignoring this buffer.  Mark it as free again. */
+		xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );		
+		ulNextRxBuffer++;
+		if( ulNextRxBuffer >= NB_RX_BUFFERS )
+		{
+			ulNextRxBuffer = 0;
+		}
+	}
+
+	/* We are going to walk through the descriptors that make up this frame, 
+	but don't want to alter ulNextRxBuffer as this would prevent vEMACRead()
+	from finding the data.  Therefore use a copy of ulNextRxBuffer instead. */
+	ulIndex = ulNextRxBuffer;
+
+	/* Walk through the descriptors until we find the last buffer for this 
+	frame.  The last buffer will give us the length of the entire frame. */
+	while( ( xRxDescriptors[ ulIndex ].addr & AT91C_OWNERSHIP_BIT ) && !ulLength )
+	{
+		ulLength = xRxDescriptors[ ulIndex ].U_Status.status & emacRX_LENGTH_FRAME;
+
+		/* Increment to the next buffer, wrapping if necessary. */
+		ulIndex++;
+		if( ulIndex >= NB_RX_BUFFERS )
+		{
+			ulIndex = 0;
+		}
+	}
+
+	return ulLength;
+}
+/*-----------------------------------------------------------*/
+
+/* See the header file for descriptions of public functions. */
+void vEMACRead( portCHAR *pcTo, unsigned portLONG ulSectionLength, unsigned portLONG ulTotalFrameLength )
+{
+static unsigned portLONG ulSectionBytesReadSoFar = 0, ulBufferPosition = 0, ulFameBytesReadSoFar = 0;
+static portCHAR *pcSource;
+register unsigned portLONG ulBytesRemainingInBuffer, ulRemainingSectionBytes;
+
+	/* Read ulSectionLength bytes from the Rx buffers.  This is not necessarily any
+	correspondence between the length of our Rx buffers, and the length of the
+	data we are returning or the length of the data being requested.  Therefore, 
+	between calls  we have to remember not only which buffer we are currently 
+	processing, but our position within that buffer.  This would be greatly
+	simplified if PBUF_POOL_BUFSIZE could be guaranteed to be greater than
+	the size of each Rx buffer, and that memory fragmentation did not occur.
+	
+	This function should only be called after a call to ulEMACInputLength().
+	This will ensure ulNextRxBuffer is set to the correct buffer. */
+
+
+
+	/* vEMACRead is called with pcTo set to NULL to indicate that we are about
+	to read a new frame.  Any fragments remaining in the frame we were 
+	processing during the last call should be dropped. */
+	if( pcTo == NULL )
+	{
+		/* How many bytes are indicated as being in this buffer?  If none then
+		the buffer is completely full and the frame is contained within more
+		than one buffer. */
+
+		/* Reset our state variables ready for the next read from this buffer. */
+        pcSource = ( portCHAR * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );
+        ulFameBytesReadSoFar = ( unsigned portLONG ) 0;
+		ulBufferPosition = ( unsigned portLONG ) 0;
+	}
+	else
+	{
+		/* Loop until we have obtained the required amount of data. */
+        ulSectionBytesReadSoFar = 0;
+		while( ulSectionBytesReadSoFar < ulSectionLength )
+		{
+			/* We may have already read some data from this buffer.  How much
+			data remains in the buffer? */
+			ulBytesRemainingInBuffer = ( ETH_RX_BUFFER_SIZE - ulBufferPosition );
+
+			/* How many more bytes do we need to read before we have the 
+			required amount of data? */
+            ulRemainingSectionBytes = ulSectionLength - ulSectionBytesReadSoFar;
+
+			/* Do we want more data than remains in the buffer? */
+			if( ulRemainingSectionBytes > ulBytesRemainingInBuffer )
+			{
+				/* We want more data than remains in the buffer so we can 
+				write the remains of the buffer to the destination, then move
+				onto the next buffer to get the rest. */
+				memcpy( &( pcTo[ ulSectionBytesReadSoFar ] ), &( pcSource[ ulBufferPosition ] ), ulBytesRemainingInBuffer );
+				ulSectionBytesReadSoFar += ulBytesRemainingInBuffer;
+                ulFameBytesReadSoFar += ulBytesRemainingInBuffer;
+
+				/* Mark the buffer as free again. */
+				xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
+
+				/* Move onto the next buffer. */
+				ulNextRxBuffer++;
+				if( ulNextRxBuffer >= NB_RX_BUFFERS )
+				{
+					ulNextRxBuffer = ( unsigned portLONG ) 0;
+				}
+
+				/* Reset the variables for the new buffer. */
+				pcSource = ( portCHAR * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );
+				ulBufferPosition = ( unsigned portLONG ) 0;
+			}
+			else
+			{
+				/* We have enough data in this buffer to send back.  Read out
+				enough data and remember how far we read up to. */
+				memcpy( &( pcTo[ ulSectionBytesReadSoFar ] ), &( pcSource[ ulBufferPosition ] ), ulRemainingSectionBytes );
+
+				/* There may be more data in this buffer yet.  Increment our 
+				position in this buffer past the data we have just read. */
+				ulBufferPosition += ulRemainingSectionBytes;
+				ulSectionBytesReadSoFar += ulRemainingSectionBytes;
+                ulFameBytesReadSoFar += ulRemainingSectionBytes;
+
+				/* Have we now finished with this buffer? */
+				if( ( ulBufferPosition >= ETH_RX_BUFFER_SIZE ) || ( ulFameBytesReadSoFar >= ulTotalFrameLength ) )
+				{
+					/* Mark the buffer as free again. */
+					xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
+
+					/* Move onto the next buffer. */
+					ulNextRxBuffer++;
+					if( ulNextRxBuffer >= NB_RX_BUFFERS )
+					{
+						ulNextRxBuffer = 0;
+					}
+	
+					pcSource = ( portCHAR * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );
+					ulBufferPosition = 0;
+				}
+			}
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+/* See the header file for descriptions of public functions. */
+xSemaphoreHandle xEMACInit( void )
+{
+	/* Code supplied by Atmel -------------------------------*/
+
+	/* Disable pull up on RXDV => PHY normal mode (not in test mode),
+	PHY has internal pull down. */
+	AT91C_BASE_PIOB->PIO_PPUDR = 1 << 15;
+
+	#if USE_RMII_INTERFACE != 1
+	  	/* PHY has internal pull down : set MII mode. */
+	  	AT91C_BASE_PIOB->PIO_PPUDR = 1 << 16;
+	#endif
+
+	/* Clear PB18 <=> PHY powerdown. */
+   	AT91C_BASE_PIOB->PIO_PER = 1 << 18;
+	AT91C_BASE_PIOB->PIO_OER = 1 << 18;
+	AT91C_BASE_PIOB->PIO_CODR = 1 << 18;
+
+	/* After PHY power up, hardware reset. */
+	AT91C_BASE_RSTC->RSTC_RMR = emacRESET_KEY | emacRESET_LENGTH;
+	AT91C_BASE_RSTC->RSTC_RCR = emacRESET_KEY | AT91C_RSTC_EXTRST;
+
+	/* Wait for hardware reset end. */
+	while( !( AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL ) )
+	{
+		__asm volatile ( "NOP" );
+	}
+    __asm volatile ( "NOP" );
+
+	/* Setup the pins. */
+	AT91C_BASE_PIOB->PIO_ASR = emacPERIPHERAL_A_SETUP;
+	AT91C_BASE_PIOB->PIO_PDR = emacPERIPHERAL_A_SETUP;
+
+	/* Enable com between EMAC PHY.
+
+	Enable management port. */
+	AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;	
+
+	/* MDC = MCK/32. */
+	AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10;	
+
+	/* Wait for PHY auto init end (rather crude delay!). */
+	vTaskDelay( emacPHY_INIT_DELAY );
+
+	/* PHY configuration. */
+	#if USE_RMII_INTERFACE != 1
+	{
+		unsigned portLONG ulControl;
+
+		/* PHY has internal pull down : disable MII isolate. */
+		vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );
+		vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );
+		ulControl &= ~BMCR_ISOLATE;
+		vWritePHY( AT91C_PHY_ADDR, MII_BMCR, ulControl );
+	}
+	#endif
+
+	/* Disable management port again. */
+	AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
+
+	#if USE_RMII_INTERFACE != 1
+		/* Enable EMAC in MII mode, enable clock ERXCK and ETXCK. */
+		AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_CLKEN ;
+	#else
+		/* Enable EMAC in RMII mode, enable RMII clock (50MHz from oscillator
+		on ERFCK). */
+		AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_RMII | AT91C_EMAC_CLKEN ;
+	#endif
+
+	/* End of code supplied by Atmel ------------------------*/
+
+	/* Setup the buffers and descriptors. */
+	prvSetupDescriptors();
+	
+	/* Load our MAC address into the EMAC. */
+	prvSetupMACAddress();
+
+	/* Are we connected? */
+	if( prvProbePHY() )
+	{
+		/* Enable the interrupt! */
+		portENTER_CRITICAL();
+		{
+			prvSetupEMACInterrupt();
+			vPassEMACSemaphore( xSemaphore );
+		}
+		portEXIT_CRITICAL();
+	}
+
+	return xSemaphore;
+}
+/*-----------------------------------------------------------*/
+
+/* See the header file for descriptions of public functions. */
+void vClearEMACTxBuffer( void )
+{
+static unsigned portBASE_TYPE uxNextBufferToClear = 0;
+
+	/* Called on Tx interrupt events to reset the AT91C_TRANSMIT_OK bit in each 
+	Tx buffer within the frame just transmitted.  This marks all the buffers
+	as available again.
+
+	The first buffer in the frame should have the bit set automatically. */
+	if( xTxDescriptors[ uxNextBufferToClear ].U_Status.status & AT91C_TRANSMIT_OK )
+	{
+		/* Loop through the other buffers in the frame. */
+		while( !( xTxDescriptors[ uxNextBufferToClear ].U_Status.status & AT91C_LAST_BUFFER ) )
+		{
+			uxNextBufferToClear++;
+
+			if( uxNextBufferToClear >= NB_TX_BUFFERS )
+			{
+				uxNextBufferToClear = 0;
+			}
+
+			xTxDescriptors[ uxNextBufferToClear ].U_Status.status |= AT91C_TRANSMIT_OK;
+		}
+
+		/* Start with the next buffer the next time a Tx interrupt is called. */
+		uxNextBufferToClear++;
+
+		/* Do we need to wrap back to the first buffer? */
+		if( uxNextBufferToClear >= NB_TX_BUFFERS )
+		{
+			uxNextBufferToClear = 0;
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupDescriptors(void)
+{
+unsigned portBASE_TYPE xIndex;
+unsigned portLONG ulAddress;
+
+	/* Initialise xRxDescriptors descriptor. */
+	for( xIndex = 0; xIndex < NB_RX_BUFFERS; ++xIndex )
+	{
+		/* Calculate the address of the nth buffer within the array. */
+		ulAddress = ( unsigned portLONG )( pcRxBuffer + ( xIndex * ETH_RX_BUFFER_SIZE ) );
+
+		/* Write the buffer address into the descriptor.  The DMA will place
+		the data at this address when this descriptor is being used.  Mask off
+		the bottom bits of the address as these have special meaning. */
+		xRxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;
+	}	
+
+	/* The last buffer has the wrap bit set so the EMAC knows to wrap back
+	to the first buffer. */
+	xRxDescriptors[ NB_RX_BUFFERS - 1 ].addr |= emacRX_WRAP_BIT;
+
+	/* Initialise xTxDescriptors. */
+	for( xIndex = 0; xIndex < NB_TX_BUFFERS; ++xIndex )
+	{
+		/* Calculate the address of the nth buffer within the array. */
+		ulAddress = ( unsigned portLONG )( pcTxBuffer + ( xIndex * ETH_TX_BUFFER_SIZE ) );
+
+		/* Write the buffer address into the descriptor.  The DMA will read
+		data from here when the descriptor is being used. */
+		xTxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;
+		xTxDescriptors[ xIndex ].U_Status.status = AT91C_TRANSMIT_OK;
+	}	
+
+	/* The last buffer has the wrap bit set so the EMAC knows to wrap back
+	to the first buffer. */
+	xTxDescriptors[ NB_TX_BUFFERS - 1 ].U_Status.status = AT91C_TRANSMIT_WRAP | AT91C_TRANSMIT_OK;
+
+	/* Tell the EMAC where to find the descriptors. */
+	AT91C_BASE_EMAC->EMAC_RBQP = ( unsigned portLONG ) xRxDescriptors;
+	AT91C_BASE_EMAC->EMAC_TBQP = ( unsigned portLONG ) xTxDescriptors;
+	
+	/* Clear all the bits in the receive status register. */
+	AT91C_BASE_EMAC->EMAC_RSR = ( AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA );
+
+	/* Enable the copy of data into the buffers, ignore broadcasts, 
+	and don't copy FCS. */
+	AT91C_BASE_EMAC->EMAC_NCFGR |= ( AT91C_EMAC_CAF | AT91C_EMAC_NBC | AT91C_EMAC_DRFCS);
+
+	/* Enable Rx and Tx, plus the stats register. */
+	AT91C_BASE_EMAC->EMAC_NCR |= ( AT91C_EMAC_TE | AT91C_EMAC_RE | AT91C_EMAC_WESTAT );
+}	
+/*-----------------------------------------------------------*/
+
+static void prvSetupMACAddress( void )
+{
+	/* Must be written SA1L then SA1H. */
+	AT91C_BASE_EMAC->EMAC_SA1L =	( ( unsigned portLONG ) cMACAddress[ 3 ] << 24 ) |
+									( ( unsigned portLONG ) cMACAddress[ 2 ] << 16 ) |
+									( ( unsigned portLONG ) cMACAddress[ 1 ] << 8  ) |
+									cMACAddress[ 0 ];
+
+	AT91C_BASE_EMAC->EMAC_SA1H =	( ( unsigned portLONG ) cMACAddress[ 5 ] << 8 ) |
+									cMACAddress[ 4 ];
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupEMACInterrupt( void )
+{
+	/* Create the semaphore used to trigger the EMAC task. */
+	vSemaphoreCreateBinary( xSemaphore );
+	if( xSemaphore )
+	{
+		/* We start by 'taking' the semaphore so the ISR can 'give' it when the
+		first interrupt occurs. */
+		xSemaphoreTake( xSemaphore, emacNO_DELAY );
+		portENTER_CRITICAL();
+		{
+			/* We want to interrupt on Rx and Tx events. */
+			AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RCOMP | AT91C_EMAC_TCOMP;
+
+			/* Enable the interrupts in the AIC. */
+			AT91F_AIC_ConfigureIt( AT91C_ID_EMAC, emacINTERRUPT_LEVEL, AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, ( void (*)( void ) ) vEMACISR_Wrapper );
+            AT91C_BASE_AIC->AIC_IECR = 0x1 << AT91C_ID_EMAC;
+		}
+		portEXIT_CRITICAL();
+	}
+}
+
+
+
+
+
+/*
+ * The following functions are initialisation functions taken from the Atmel
+ * EMAC sample code.
+ */
+
+
+static portBASE_TYPE prvProbePHY( void )
+{
+unsigned portLONG ulPHYId1, ulPHYId2, ulStatus;
+portBASE_TYPE xReturn = pdPASS;
+	
+	/* Code supplied by Atmel (reformatted) -----------------*/
+
+	/* Enable management port */
+	AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;	
+   	AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10;
+
+	/* Read the PHY ID. */
+	vReadPHY( AT91C_PHY_ADDR, MII_PHYSID1, &ulPHYId1 );
+	vReadPHY(AT91C_PHY_ADDR, MII_PHYSID2, &ulPHYId2 );
+
+	/* AMD AM79C875:
+			PHY_ID1 = 0x0022
+			PHY_ID2 = 0x5541
+			Bits 3:0 Revision Number Four bit manufacturer?s revision number.
+				0001 stands for Rev. A, etc.
+	*/
+	if( ( ( ulPHYId1 << 16 ) | ( ulPHYId2 & 0xfff0 ) ) != MII_DM9161_ID )
+	{
+		/* Did not expect this ID. */
+		xReturn = pdFAIL;
+	}
+	else
+	{
+		ulStatus = xGetLinkSpeed();
+
+		if( ulStatus != pdPASS )
+		{
+			xReturn = pdFAIL;
+		}
+	}
+
+	/* Disable management port */
+	AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;	
+
+	/* End of code supplied by Atmel ------------------------*/
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static void vReadPHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG *pulValue )
+{
+	/* Code supplied by Atmel (reformatted) ----------------------*/
+
+	AT91C_BASE_EMAC->EMAC_MAN = 	(AT91C_EMAC_SOF & (0x01<<30))
+									| (2 << 16) | (2 << 28)
+									| ((ucPHYAddress & 0x1f) << 23)
+									| (ucAddress << 18);
+
+	/* Wait until IDLE bit in Network Status register is cleared. */
+	while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )
+	{
+		__asm( "NOP" );
+	}
+
+	*pulValue = ( AT91C_BASE_EMAC->EMAC_MAN & 0x0000ffff );	
+
+	/* End of code supplied by Atmel ------------------------*/
+}
+/*-----------------------------------------------------------*/
+
+#if USE_RMII_INTERFACE != 1
+static void vWritePHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG ulValue )
+{
+	/* Code supplied by Atmel (reformatted) ----------------------*/
+
+	AT91C_BASE_EMAC->EMAC_MAN = (( AT91C_EMAC_SOF & (0x01<<30))
+								| (2 << 16) | (1 << 28)
+								| ((ucPHYAddress & 0x1f) << 23)
+								| (ucAddress << 18))
+								| (ulValue & 0xffff);
+
+	/* Wait until IDLE bit in Network Status register is cleared */
+	while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )
+	{
+		__asm( "NOP" );
+	};
+
+	/* End of code supplied by Atmel ------------------------*/
+}
+#endif
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE xGetLinkSpeed( void )
+{
+	unsigned portLONG ulBMSR, ulBMCR, ulLPA, ulMACCfg, ulSpeed, ulDuplex;
+
+	/* Code supplied by Atmel (reformatted) -----------------*/
+
+	/* Link status is latched, so read twice to get current value */
+	vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);
+	vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);
+
+	if( !( ulBMSR & BMSR_LSTATUS ) )
+	{	
+		/* No Link. */
+		return pdFAIL;
+	}
+
+	vReadPHY(AT91C_PHY_ADDR, MII_BMCR, &ulBMCR);
+	if (ulBMCR & BMCR_ANENABLE)
+	{				
+		/* AutoNegotiation is enabled. */
+		if (!(ulBMSR & BMSR_ANEGCOMPLETE))
+		{
+			/* Auto-negotitation in progress. */
+			return pdFAIL;				
+		}		
+
+		vReadPHY(AT91C_PHY_ADDR, MII_LPA, &ulLPA);
+		if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_100HALF ) )
+		{
+			ulSpeed = SPEED_100;
+		}
+		else
+		{
+			ulSpeed = SPEED_10;
+		}
+
+		if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_10FULL ) )
+		{
+			ulDuplex = DUPLEX_FULL;
+		}
+		else
+		{
+			ulDuplex = DUPLEX_HALF;
+		}
+	}
+	else
+	{
+		ulSpeed = ( ulBMCR & BMCR_SPEED100 ) ? SPEED_100 : SPEED_10;
+		ulDuplex = ( ulBMCR & BMCR_FULLDPLX ) ? DUPLEX_FULL : DUPLEX_HALF;
+	}
+
+	/* Update the MAC */
+	ulMACCfg = AT91C_BASE_EMAC->EMAC_NCFGR & ~( AT91C_EMAC_SPD | AT91C_EMAC_FD );
+	if( ulSpeed == SPEED_100 )
+	{
+		if( ulDuplex == DUPLEX_FULL )
+		{
+			/* 100 Full Duplex */
+			AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD | AT91C_EMAC_FD;
+		}
+		else
+		{					
+			/* 100 Half Duplex */
+			AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD;
+		}
+	}
+	else
+	{
+		if (ulDuplex == DUPLEX_FULL)
+		{
+			/* 10 Full Duplex */
+			AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_FD;
+		}
+		else
+		{			/* 10 Half Duplex */
+			AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg;
+		}
+	}
+
+	/* End of code supplied by Atmel ------------------------*/
+
+	return pdPASS;
+}
+/*-----------------------------------------------------------*/
+
+void vEMACWaitForInput( void )
+{
+	/* Just wait until we are signled from an ISR that data is available, or
+	we simply time out. */
+	xSemaphoreTake( xSemaphore, emacBLOCK_TIME_WAITING_FOR_INPUT );
+}
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/EMAC/SAM7_EMAC.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/EMAC/SAM7_EMAC.h
new file mode 100644
index 000000000..9bb8ad103
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/EMAC/SAM7_EMAC.h
@@ -0,0 +1,130 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+/*
+Changes from V3.2.4
+
+	+ Modified the default MAC address as the one used previously was not liked
+	  by some routers.
+
+*/
+
+#ifndef SAM_7_EMAC_H
+#define SAM_7_EMAC_H
+
+/* MAC address definition.  The MAC address must be unique on the network. */
+#define emacETHADDR0 0
+#define emacETHADDR1 0xbd
+#define emacETHADDR2 0x33
+#define emacETHADDR3 0x06
+#define emacETHADDR4 0x68
+#define emacETHADDR5 0x22
+
+/* The IP address being used. */
+#define emacIPADDR0 172
+#define emacIPADDR1 25
+#define emacIPADDR2 218
+#define emacIPADDR3 205
+
+/* The gateway address being used. */
+#define emacGATEWAY_ADDR0 172
+#define emacGATEWAY_ADDR1 25
+#define emacGATEWAY_ADDR2 218
+#define emacGATEWAY_ADDR3 3
+
+/* The network mask being used. */
+#define emacNET_MASK0 255
+#define emacNET_MASK1 255
+#define emacNET_MASK2 0
+#define emacNET_MASK3 0
+
+/*
+ * Initialise the EMAC driver.  If successful a semaphore is returned that
+ * is used by the EMAC ISR to indicate that Rx packets have been received.
+ * If the initialisation fails then NULL is returned.
+ */
+xSemaphoreHandle xEMACInit( void );
+
+/*
+ * Send ulLength bytes from pcFrom.  This copies the buffer to one of the
+ * EMAC Tx buffers, then indicates to the EMAC that the buffer is ready.
+ * If lEndOfFrame is true then the data being copied is the end of the frame
+ * and the frame can be transmitted. 
+ */
+portLONG lEMACSend( portCHAR *pcFrom, unsigned portLONG ulLength, portLONG lEndOfFrame );
+
+/*
+ * Frames can be read from the EMAC in multiple sections.
+ * Read ulSectionLength bytes from the EMAC receive buffers to pcTo.  
+ * ulTotalFrameLength is the size of the entire frame.  Generally vEMACRead
+ * will be repetedly called until the sum of all the ulSectionLenths totals
+ * the value of ulTotalFrameLength.
+ */
+void vEMACRead( portCHAR *pcTo, unsigned portLONG ulSectionLength, unsigned portLONG ulTotalFrameLength );
+
+/*
+ * The EMAC driver and interrupt service routines are defined in different 
+ * files as the driver is compiled to THUMB, and the ISR to ARM.  This function
+ * simply passes the semaphore used to communicate between the two.
+ */
+void vPassEMACSemaphore( xSemaphoreHandle xCreatedSemaphore );
+
+/* 
+ * Called by the Tx interrupt, this function traverses the buffers used to
+ * hold the frame that has just completed transmission and marks each as
+ * free again.
+ */
+void vClearEMACTxBuffer( void );
+
+/*
+ * Suspend on a semaphore waiting either for the semaphore to be obtained 
+ * or a timeout.  The semaphore is used by the EMAC ISR to indicate that
+ * data has been received and is ready for processing.
+ */
+void vEMACWaitForInput( void );
+
+/*
+ * Return the length of the next frame in the receive buffers.
+ */
+unsigned portLONG ulEMACInputLength( void );
+
+#endif
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/EMAC/SAM7_EMAC_ISR.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/EMAC/SAM7_EMAC_ISR.c
new file mode 100644
index 000000000..0efcb7bed
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/EMAC/SAM7_EMAC_ISR.c
@@ -0,0 +1,126 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "semphr.h"
+#include "SAM7_EMAC.h"
+#include "AT91SAM7X256.h"
+
+/*-----------------------------------------------------------*/
+
+/* The semaphore used to signal the arrival of new data to the interface
+task. */
+static xSemaphoreHandle xSemaphore = NULL;
+
+/* The interrupt entry point is naked so we can control the context saving. */
+void vEMACISR_Wrapper( void ) __attribute__((naked));
+
+/* The interrupt handler function must be separate from the entry function
+to ensure the correct stack frame is set up. */
+void vEMACISR_Handler( void );
+
+/*-----------------------------------------------------------*/
+/*
+ * The EMAC ISR.  Handles both Tx and Rx complete interrupts.
+ */
+void vEMACISR_Handler( void )
+{
+volatile unsigned portLONG ulIntStatus, ulEventStatus;
+portBASE_TYPE xSwitchRequired = pdFALSE;
+extern void vClearEMACTxBuffer( void );
+
+	/* Find the cause of the interrupt. */
+	ulIntStatus = AT91C_BASE_EMAC->EMAC_ISR;
+	ulEventStatus = AT91C_BASE_EMAC->EMAC_RSR;
+
+	if( ( ulIntStatus & AT91C_EMAC_RCOMP ) || ( ulEventStatus & AT91C_EMAC_REC ) )
+	{
+		/* A frame has been received, signal the lwIP task so it can process
+		the Rx descriptors. */
+		xSwitchRequired = xSemaphoreGiveFromISR( xSemaphore, pdFALSE );
+		AT91C_BASE_EMAC->EMAC_RSR = AT91C_EMAC_REC;
+	}
+
+	if( ulIntStatus & AT91C_EMAC_TCOMP )
+	{
+		/* A frame has been transmitted.  Mark all the buffers used by the
+		frame just transmitted as free again. */
+		vClearEMACTxBuffer();
+		AT91C_BASE_EMAC->EMAC_TSR = AT91C_EMAC_COMP;
+	}
+
+	/* Clear the interrupt. */
+	AT91C_BASE_AIC->AIC_EOICR = 0;
+
+	/* If a task was woken by either a frame being received then we may need to 
+	switch to another task.  If the unblocked task was of higher priority then
+	the interrupted task it will then execute immediately that the ISR
+	completes. */
+	if( xSwitchRequired )
+	{
+		portYIELD_FROM_ISR();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void  vEMACISR_Wrapper( void )
+{
+	/* Save the context of the interrupted task. */
+	portSAVE_CONTEXT();
+
+	/* Call the handler to do the work.  This must be a separate
+	function to ensure the stack frame is set up correctly. */
+	vEMACISR_Handler();
+
+	/* Restore the context of whichever task will execute next. */
+	portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+void vPassEMACSemaphore( xSemaphoreHandle xCreatedSemaphore )
+{
+	/* Simply store the semaphore that should be used by the ISR. */
+	xSemaphore = xCreatedSemaphore;
+}
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/EMAC/mii.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/EMAC/mii.h
new file mode 100644
index 000000000..29b2f53d5
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/EMAC/mii.h
@@ -0,0 +1,105 @@
+/* Generic MII registers. */
+
+#define MII_BMCR            0x00        /* Basic mode control register */
+#define MII_BMSR            0x01        /* Basic mode status register  */
+#define MII_PHYSID1         0x02        /* PHYS ID 1                   */
+#define MII_PHYSID2         0x03        /* PHYS ID 2                   */
+#define MII_ADVERTISE       0x04        /* Advertisement control reg   */
+#define MII_LPA             0x05        /* Link partner ability reg    */
+#define MII_EXPANSION       0x06        /* Expansion register          */
+#define MII_DCOUNTER        0x12        /* Disconnect counter          */
+#define MII_FCSCOUNTER      0x13        /* False carrier counter       */
+#define MII_NWAYTEST        0x14        /* N-way auto-neg test reg     */
+#define MII_RERRCOUNTER     0x15        /* Receive error counter       */
+#define MII_SREVISION       0x16        /* Silicon revision            */
+#define MII_RESV1           0x17        /* Reserved...                 */
+#define MII_LBRERROR        0x18        /* Lpback, rx, bypass error    */
+#define MII_PHYADDR         0x19        /* PHY address                 */
+#define MII_RESV2           0x1a        /* Reserved...                 */
+#define MII_TPISTATUS       0x1b        /* TPI status for 10mbps       */
+#define MII_NCONFIG         0x1c        /* Network interface config    */
+
+/* Basic mode control register. */
+#define BMCR_RESV               0x007f  /* Unused...                   */
+#define BMCR_CTST               0x0080  /* Collision test              */
+#define BMCR_FULLDPLX           0x0100  /* Full duplex                 */
+#define BMCR_ANRESTART          0x0200  /* Auto negotiation restart    */
+#define BMCR_ISOLATE            0x0400  /* Disconnect DP83840 from MII */
+#define BMCR_PDOWN              0x0800  /* Powerdown the DP83840       */
+#define BMCR_ANENABLE           0x1000  /* Enable auto negotiation     */
+#define BMCR_SPEED100           0x2000  /* Select 100Mbps              */
+#define BMCR_LOOPBACK           0x4000  /* TXD loopback bits           */
+#define BMCR_RESET              0x8000  /* Reset the DP83840           */
+
+/* Basic mode status register. */
+#define BMSR_ERCAP              0x0001  /* Ext-reg capability          */
+#define BMSR_JCD                0x0002  /* Jabber detected             */
+#define BMSR_LSTATUS            0x0004  /* Link status                 */
+#define BMSR_ANEGCAPABLE        0x0008  /* Able to do auto-negotiation */
+#define BMSR_RFAULT             0x0010  /* Remote fault detected       */
+#define BMSR_ANEGCOMPLETE       0x0020  /* Auto-negotiation complete   */
+#define BMSR_RESV               0x07c0  /* Unused...                   */
+#define BMSR_10HALF             0x0800  /* Can do 10mbps, half-duplex  */
+#define BMSR_10FULL             0x1000  /* Can do 10mbps, full-duplex  */
+#define BMSR_100HALF            0x2000  /* Can do 100mbps, half-duplex */
+#define BMSR_100FULL            0x4000  /* Can do 100mbps, full-duplex */
+#define BMSR_100BASE4           0x8000  /* Can do 100mbps, 4k packets  */
+
+/* Advertisement control register. */
+#define ADVERTISE_SLCT          0x001f  /* Selector bits               */
+#define ADVERTISE_CSMA          0x0001  /* Only selector supported     */
+#define ADVERTISE_10HALF        0x0020  /* Try for 10mbps half-duplex  */
+#define ADVERTISE_10FULL        0x0040  /* Try for 10mbps full-duplex  */
+#define ADVERTISE_100HALF       0x0080  /* Try for 100mbps half-duplex */
+#define ADVERTISE_100FULL       0x0100  /* Try for 100mbps full-duplex */
+#define ADVERTISE_100BASE4      0x0200  /* Try for 100mbps 4k packets  */
+#define ADVERTISE_RESV          0x1c00  /* Unused...                   */
+#define ADVERTISE_RFAULT        0x2000  /* Say we can detect faults    */
+#define ADVERTISE_LPACK         0x4000  /* Ack link partners response  */
+#define ADVERTISE_NPAGE         0x8000  /* Next page bit               */
+
+#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
+			ADVERTISE_CSMA)
+#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
+                       ADVERTISE_100HALF | ADVERTISE_100FULL)
+
+/* Link partner ability register. */
+#define LPA_SLCT                0x001f  /* Same as advertise selector  */
+#define LPA_10HALF              0x0020  /* Can do 10mbps half-duplex   */
+#define LPA_10FULL              0x0040  /* Can do 10mbps full-duplex   */
+#define LPA_100HALF             0x0080  /* Can do 100mbps half-duplex  */
+#define LPA_100FULL             0x0100  /* Can do 100mbps full-duplex  */
+#define LPA_100BASE4            0x0200  /* Can do 100mbps 4k packets   */
+#define LPA_RESV                0x1c00  /* Unused...                   */
+#define LPA_RFAULT              0x2000  /* Link partner faulted        */
+#define LPA_LPACK               0x4000  /* Link partner acked us       */
+#define LPA_NPAGE               0x8000  /* Next page bit               */
+
+#define LPA_DUPLEX		(LPA_10FULL | LPA_100FULL)
+#define LPA_100			(LPA_100FULL | LPA_100HALF | LPA_100BASE4)
+
+/* Expansion register for auto-negotiation. */
+#define EXPANSION_NWAY          0x0001  /* Can do N-way auto-nego      */
+#define EXPANSION_LCWP          0x0002  /* Got new RX page code word   */
+#define EXPANSION_ENABLENPAGE   0x0004  /* This enables npage words    */
+#define EXPANSION_NPCAPABLE     0x0008  /* Link partner supports npage */
+#define EXPANSION_MFAULTS       0x0010  /* Multiple faults detected    */
+#define EXPANSION_RESV          0xffe0  /* Unused...                   */
+
+/* N-way test register. */
+#define NWAYTEST_RESV1          0x00ff  /* Unused...                   */
+#define NWAYTEST_LOOPBACK       0x0100  /* Enable loopback for N-way   */
+#define NWAYTEST_RESV2          0xfe00  /* Unused...                   */
+
+#define SPEED_10				10
+#define SPEED_100				100
+
+/* Duplex, half or full. */
+#define DUPLEX_HALF				0x00
+#define DUPLEX_FULL				0x01
+
+/* PHY ID */
+#define MII_DM9161_ID     0x0181b8a0
+#define MII_AM79C875_ID   0x00225540	/* 0x00225541 */
+
+#define AT91C_PHY_ADDR	31
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/FreeRTOSConfig.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/FreeRTOSConfig.h
new file mode 100644
index 000000000..a090c9175
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/FreeRTOSConfig.h
@@ -0,0 +1,89 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *----------------------------------------------------------*/
+
+/* The SWI is used by the scheduler. */
+#define vPortYieldProcessor swi_handler
+
+
+#define configUSE_PREEMPTION		1
+#define configUSE_IDLE_HOOK			1
+#define configUSE_TICK_HOOK			0
+#define configCPU_CLOCK_HZ			( ( unsigned portLONG ) 47923200 )
+#define configTICK_RATE_HZ			( ( portTickType ) 1000 )
+#define configMAX_PRIORITIES		( ( unsigned portBASE_TYPE ) 5 )
+#define configMINIMAL_STACK_SIZE	( ( unsigned portSHORT ) 110 )
+#define configTOTAL_HEAP_SIZE		( ( size_t ) 22000 )
+#define configMAX_TASK_NAME_LEN		( 16 )
+#define configUSE_TRACE_FACILITY	1
+#define configUSE_16_BIT_TICKS		0
+#define configIDLE_SHOULD_YIELD		1
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 		0
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+
+#define INCLUDE_vTaskPrioritySet			1
+#define INCLUDE_uxTaskPriorityGet			1
+#define INCLUDE_vTaskDelete					1
+#define INCLUDE_vTaskCleanUpResources		0
+#define INCLUDE_vTaskSuspend				1
+#define INCLUDE_vTaskDelayUntil				1
+#define INCLUDE_vTaskDelay					1
+#define INCLUDE_xTaskGetCurrentTaskHandle	1
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/ParTest/ParTest.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/ParTest/ParTest.c
new file mode 100644
index 000000000..3e0a94e6d
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/ParTest/ParTest.c
@@ -0,0 +1,96 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* Demo application includes. */
+#include "partest.h"
+
+/* Hardware specific includes. */
+#include "Board.h"
+
+
+/*-----------------------------------------------------------
+ * Simple parallel port IO routines for the LED's.  LED's can be set, cleared
+ * or toggled.
+ *-----------------------------------------------------------*/
+const unsigned portLONG ulLED_MASK[ NB_LED ]= { LED1, LED2, LED3, LED4 };
+
+void vParTestInitialise( void )
+{	
+	/* Start with all LED's off. */
+    AT91C_BASE_PIOB->PIO_SODR = LED_MASK;
+}
+/*-----------------------------------------------------------*/
+
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
+{
+	if( uxLED < ( portBASE_TYPE ) NB_LED )
+	{
+		if( xValue )
+		{
+			AT91C_BASE_PIOB->PIO_SODR = ulLED_MASK[ uxLED ];
+		}
+		else
+		{
+			AT91C_BASE_PIOB->PIO_CODR = ulLED_MASK[ uxLED ];
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
+{
+	if( uxLED < ( portBASE_TYPE ) NB_LED )
+	{
+		if( AT91C_BASE_PIOB->PIO_PDSR & ulLED_MASK[ uxLED ] )
+		{
+			AT91C_BASE_PIOB->PIO_CODR = ulLED_MASK[ uxLED ];
+		}
+		else
+		{
+			AT91C_BASE_PIOB->PIO_SODR = ulLED_MASK[ uxLED ];
+		}
+	}
+}
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/USB/FreeRTOSCDC.inf b/20080212/Demo/lwIP_Demo_Rowley_ARM7/USB/FreeRTOSCDC.inf
new file mode 100644
index 000000000..eb3cb61c1
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/USB/FreeRTOSCDC.inf
@@ -0,0 +1,48 @@
+[Version]
+Signature="$Windows NT$"
+Class=Ports
+ClassGuid={4D36E978-E325-11CE-BFC1-08002BE10318}
+Provider=%ATMEL%
+LayoutFile=layout.inf
+DriverVer=10/15/1999,5.0.2153.1
+
+[MANUFACTURER]
+%FreeRTOS%=FreeRTOS
+
+[FreeRTOS]
+%FreeRTOS_CDC%=Reader,USB\VID_EB03&PID_0920
+
+[Reader_Install.NTx86]
+;Windows2000
+
+[DestinationDirs]
+DefaultDestDir=12
+Reader.NT.Copy=12
+
+[Reader.NT]
+CopyFiles=Reader.NT.Copy
+AddReg=Reader.NT.AddReg
+
+[Reader.NT.Copy]
+usbser.sys
+
+[Reader.NT.AddReg]
+HKR,,NTMPDriver,,*ntkern
+HKR,,NTMPDriver,,usbser.sys
+HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider"
+[Reader.NT.Services]
+AddService = usbser, 0x00000002,Service_Inst
+
+[Service_Inst]
+DisplayName = %Serial.SvcDesc%
+ServiceType = 1 ; SERVICE_KERNEL_DRIVER
+StartType = 3 ; SERVICE_DEMAND_START
+ErrorControl = 1 ;SERVICE_ERROR_NORMAL
+ServiceBinary = %12%\usbser.sys
+LoadOrderGroup = Base
+
+[Strings]
+FreeRTOS = "FreeRTOS"
+FreeRTOS_CDC = "FreeRTOS CDC Demo"
+Serial.SvcDesc = "USB Serial emulation driver"
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/USB/USB-CDC.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/USB/USB-CDC.c
new file mode 100644
index 000000000..85b8a6f80
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/USB/USB-CDC.c
@@ -0,0 +1,873 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+/*
+	USB Communications Device Class driver.
+	Implements task vUSBCDCTask and provides an Abstract Control Model serial 
+	interface.  Control is through endpoint 0, device-to-host notification is 
+	provided by interrupt-in endpoint 3, and raw data is transferred through 
+	bulk endpoints 1 and 2.
+
+	- developed from original FreeRTOS HID example by Scott Miller
+	- modified to support 3.2 GCC by najay
+*/
+
+/* Standard includes. */
+#include 
+#include 
+
+/* Demo board includes. */
+#include "Board.h"
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+
+/* Demo app includes. */
+#include "USB-CDC.h"
+#include "descriptors.h"
+
+#define usbNO_BLOCK ( ( portTickType ) 0 )
+
+/* Reset all endpoints */
+static void prvResetEndPoints( void );
+
+/* Clear pull up resistor to detach device from host */
+static void vDetachUSBInterface( void );
+
+/* Set up interface and initialize variables */
+static void vInitUSBInterface( void );
+
+/* Handle control endpoint events. */
+static void prvProcessEndPoint0Interrupt( xISRStatus *pxMessage );
+
+/* Handle standard device requests. */
+static void prvHandleStandardDeviceRequest( xUSB_REQUEST *pxRequest );
+
+/* Handle standard interface requests. */
+static void prvHandleStandardInterfaceRequest( xUSB_REQUEST *pxRequest );
+
+/* Handle endpoint requests. */
+static void prvHandleStandardEndPointRequest( xUSB_REQUEST *pxRequest );
+
+/* Handle class interface requests. */
+static void prvHandleClassInterfaceRequest( xUSB_REQUEST *pxRequest );
+
+/* Prepare control data transfer.  prvSendNextSegment starts transfer. */
+static void prvSendControlData( unsigned portCHAR *pucData, unsigned portSHORT usRequestedLength, unsigned portLONG ulLengthLeftToSend, portLONG lSendingDescriptor );
+
+/* Send next segment of data for the control transfer */
+static void prvSendNextSegment( void );
+
+/* Send stall - used to respond to unsupported requests */
+static void prvSendStall( void );
+
+/* Send a zero-length (null) packet */
+static void prvSendZLP( void );
+
+/* Handle requests for standard interface descriptors */
+static void prvGetStandardInterfaceDescriptor( xUSB_REQUEST *pxRequest );
+
+/*------------------------------------------------------------*/
+
+/* File scope static variables */
+static unsigned portCHAR ucUSBConfig = ( unsigned portCHAR ) 0;
+static unsigned portLONG ulReceivedAddress = ( unsigned portLONG ) 0;
+static eDRIVER_STATE eDriverState = eNOTHING;
+
+/* Incoming and outgoing control data structures */
+static xCONTROL_MESSAGE pxControlTx;
+static xCONTROL_MESSAGE pxControlRx;
+
+/* Queue holding pointers to pending messages */
+xQueueHandle xUSBInterruptQueue; 
+
+/* Queues used to hold received characters, and characters waiting to be
+transmitted.  Rx queue must be larger than FIFO size. */
+static xQueueHandle xRxCDC; 
+static xQueueHandle xTxCDC; 
+
+/* Line coding - 115,200 baud, N-8-1 */
+static const unsigned portCHAR pxLineCoding[] = { 0x00, 0xC2, 0x01, 0x00, 0x00, 0x00, 0x08 };
+
+/* Status variables. */
+static unsigned portCHAR ucControlState;
+static unsigned int uiCurrentBank;
+
+
+/*------------------------------------------------------------*/
+
+
+void vUSBCDCTask( void *pvParameters )
+{
+xISRStatus *pxMessage;
+unsigned portLONG ulStatus;
+unsigned portLONG ulRxBytes;
+unsigned portCHAR ucByte;
+portBASE_TYPE xByte;
+
+	( void ) pvParameters;
+
+	/* Disconnect USB device from hub.  For debugging - causes host to register reset */
+	portENTER_CRITICAL();
+		 vDetachUSBInterface();
+	portEXIT_CRITICAL();
+	
+	vTaskDelay( portTICK_RATE_MS * 60 );
+
+	/* Init USB interface */
+	portENTER_CRITICAL();
+		vInitUSBInterface();
+	portEXIT_CRITICAL();
+	
+	/* Main task loop.  Process incoming endpoint 0 interrupts, handle data transfers. */
+	 
+	for( ;; )
+	{
+		/* Look for data coming from the ISR. */
+		if( xQueueReceive( xUSBInterruptQueue, &pxMessage, usbSHORTEST_DELAY ) )
+		{
+			if( pxMessage->ulISR & AT91C_UDP_EPINT0 )
+			{
+				/* All endpoint 0 interrupts are handled here. */
+				prvProcessEndPoint0Interrupt( pxMessage );
+			}
+
+			if( pxMessage->ulISR & AT91C_UDP_ENDBUSRES )
+			{
+				/* End of bus reset - reset the endpoints and de-configure. */
+				prvResetEndPoints();		
+			}
+		}
+		
+		/* See if we're ready to send and receive data. */
+		if( eDriverState == eREADY_TO_SEND && ucControlState ) 
+		{
+			if( ( !(AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_2 ] & AT91C_UDP_TXPKTRDY) ) && uxQueueMessagesWaiting( xTxCDC ) )
+			{
+				for( xByte = 0; xByte < 64; xByte++ )
+				{				   
+					if( !xQueueReceive( xTxCDC, &ucByte, 0 ) ) 
+					{
+						/* No data buffered to transmit. */
+						break;
+					}
+
+					/* Got a byte to transmit. */
+					AT91C_BASE_UDP->UDP_FDR[ usbEND_POINT_2 ] = ucByte;
+				} 
+				AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_2 ] |= AT91C_UDP_TXPKTRDY;
+			}
+
+			/* Check for incoming data (host-to-device) on endpoint 1. */
+			while( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] & (AT91C_UDP_RX_DATA_BK0 | AT91C_UDP_RX_DATA_BK1) )
+			{
+				ulRxBytes = (AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] >> 16) & usbRX_COUNT_MASK;
+
+				/* Only process FIFO if there's room to store it in the queue */
+				if( ulRxBytes < ( USB_CDC_QUEUE_SIZE - uxQueueMessagesWaiting( xRxCDC ) ) )
+				{
+					while( ulRxBytes-- )
+					{
+						ucByte = AT91C_BASE_UDP->UDP_FDR[ usbEND_POINT_1 ];
+						xQueueSend( xRxCDC, &ucByte, 0 );
+					}
+
+					/* Release the FIFO */
+					portENTER_CRITICAL();
+					{
+						ulStatus = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ];
+						usbCSR_CLEAR_BIT( &ulStatus, uiCurrentBank );
+						AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] = ulStatus;
+					}
+					portEXIT_CRITICAL();
+
+					/* Re-enable endpoint 1's interrupts */
+					AT91C_BASE_UDP->UDP_IER = AT91C_UDP_EPINT1;
+				
+					/* Update the current bank in use */
+					if( uiCurrentBank == AT91C_UDP_RX_DATA_BK0 ) 
+					{
+						uiCurrentBank = AT91C_UDP_RX_DATA_BK1;
+					}
+					else 
+					{
+						uiCurrentBank = AT91C_UDP_RX_DATA_BK0;
+					}
+
+				}
+				else 
+				{
+					break;
+				}
+			}
+		}
+	}
+}
+/*------------------------------------------------------------*/
+
+void vUSBSendByte( portCHAR cByte )
+{
+	/* Queue the byte to be sent.  The USB task will send it. */
+	xQueueSend( xTxCDC, &cByte, usbNO_BLOCK );
+}
+/*------------------------------------------------------------*/
+
+static void prvSendZLP( void )
+{
+unsigned portLONG ulStatus;
+
+	/* Wait until the FIFO is free - even though we are not going to use it.
+	THERE IS NO TIMEOUT HERE! */
+	while( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] & AT91C_UDP_TXPKTRDY )
+	{
+		vTaskDelay( usbSHORTEST_DELAY );
+	}
+
+	portENTER_CRITICAL();
+	{
+		/* Cancel any further pending data */
+		pxControlTx.ulTotalDataLength = pxControlTx.ulNextCharIndex;
+
+		/* Set the TXPKTRDY bit to cause a transmission with no data. */
+		ulStatus = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ];
+		usbCSR_SET_BIT( &ulStatus, AT91C_UDP_TXPKTRDY );
+		AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulStatus;
+	}
+	portEXIT_CRITICAL();
+}
+/*------------------------------------------------------------*/
+
+static void prvSendStall( void )
+{
+	unsigned portLONG ulStatus;
+
+	portENTER_CRITICAL();
+	{
+		/* Force a stall by simply setting the FORCESTALL bit in the CSR. */
+		ulStatus = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ];
+		usbCSR_SET_BIT( &ulStatus, AT91C_UDP_FORCESTALL );
+		AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulStatus;
+	}
+	portEXIT_CRITICAL();
+}
+/*------------------------------------------------------------*/
+
+static void prvResetEndPoints( void )
+{
+unsigned portLONG ulTemp;
+
+	eDriverState = eJUST_RESET;
+	ucControlState = 0;
+
+	/* Reset all the end points. */
+	AT91C_BASE_UDP->UDP_RSTEP  = usbEND_POINT_RESET_MASK;
+	AT91C_BASE_UDP->UDP_RSTEP  = ( unsigned portLONG ) 0x00;
+
+	/* Enable data to be sent and received. */
+	AT91C_BASE_UDP->UDP_FADDR = AT91C_UDP_FEN;
+
+	/* Repair the configuration end point. */
+	portENTER_CRITICAL();
+	{
+		ulTemp = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ];
+		usbCSR_SET_BIT( &ulTemp, ( ( unsigned portLONG ) ( AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_CTRL ) ) );
+		AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulTemp;
+		AT91C_BASE_UDP->UDP_IER = AT91C_UDP_EPINT0;
+	}
+	portEXIT_CRITICAL();
+	uiCurrentBank = AT91C_UDP_RX_DATA_BK0;
+}
+/*------------------------------------------------------------*/
+
+static void prvProcessEndPoint0Interrupt( xISRStatus *pxMessage )
+{
+static xUSB_REQUEST xRequest;
+unsigned portLONG ulRxBytes;
+
+	/* Get number of bytes received, if any */
+	ulRxBytes = pxMessage->ulCSR0 >> 16;
+	ulRxBytes &= usbRX_COUNT_MASK;
+
+	if( pxMessage->ulCSR0 & AT91C_UDP_TXCOMP )
+	{
+		/* We received a TX complete interrupt.  What we do depends on
+		what we sent to get this interrupt. */
+
+		if( eDriverState == eJUST_GOT_CONFIG )
+		{
+			/* We sent an acknowledgement of a SET_CONFIG request.  We
+			are now at the end of the enumeration.
+			
+			TODO: Config 0 sets unconfigured state, should enter Address state.
+			Request for unsupported config should stall. */
+			AT91C_BASE_UDP->UDP_GLBSTATE = AT91C_UDP_CONFG;
+			
+			/* Set up endpoints */
+			portENTER_CRITICAL();
+			{
+				unsigned portLONG ulTemp;
+
+				/* Set endpoint 1 to bulk-out */
+				ulTemp = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ];					
+				usbCSR_SET_BIT( &ulTemp, AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_BULK_OUT );
+				AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] = ulTemp;		
+				AT91C_BASE_UDP->UDP_IER = AT91C_UDP_EPINT1;
+				/* Set endpoint 2 to bulk-in */
+				ulTemp = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_2 ];					
+				usbCSR_SET_BIT( &ulTemp, AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_BULK_IN );
+				AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_2 ] = ulTemp;		
+				AT91C_BASE_UDP->UDP_IER = AT91C_UDP_EPINT2;
+					/* Set endpoint 3 to interrupt-in, enable it, and enable interrupts */
+				ulTemp = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_3 ];					
+				usbCSR_SET_BIT( &ulTemp, AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_INT_IN );
+				AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_3 ] = ulTemp;		
+				/*AT91F_UDP_EnableIt( AT91C_BASE_UDP, AT91C_UDP_EPINT3 );				 */
+			}
+			portEXIT_CRITICAL();
+
+			eDriverState = eREADY_TO_SEND;
+		}		
+		else if( eDriverState == eJUST_GOT_ADDRESS )
+		{
+			/* We sent an acknowledgement of a SET_ADDRESS request.  Move
+			to the addressed state. */
+			if( ulReceivedAddress != ( unsigned portLONG ) 0 )
+			{			
+				AT91C_BASE_UDP->UDP_GLBSTATE = AT91C_UDP_FADDEN;
+			}
+			else
+			{
+				AT91C_BASE_UDP->UDP_GLBSTATE = 0;
+			}			
+
+			AT91C_BASE_UDP->UDP_FADDR = ( AT91C_UDP_FEN | ulReceivedAddress );		
+			eDriverState = eNOTHING;
+		}
+		else
+		{		
+			/* The TXCOMP was not for any special type of transmission.  See
+			if there is any more data to send. */
+			prvSendNextSegment();
+		}
+	}
+
+	if( pxMessage->ulCSR0 & AT91C_UDP_RX_DATA_BK0 )
+	{
+		/* Received a control data packet.  May be a 0-length ACK or a data stage. */
+		unsigned portCHAR ucBytesToGet;
+	 
+		/* Got data.  Cancel any outgoing data. */
+		pxControlTx.ulNextCharIndex = pxControlTx.ulTotalDataLength;
+		
+		 /* Determine how many bytes we need to receive. */
+		ucBytesToGet = pxControlRx.ulTotalDataLength - pxControlRx.ulNextCharIndex;
+		if( ucBytesToGet > ulRxBytes ) 
+		{	
+			ucBytesToGet = ulRxBytes;
+		}
+
+		/* If we're not expecting any data, it's an ack - just quit now. */
+		if( !ucBytesToGet )
+		{
+			 return;
+		}
+
+		/* Get the required data and update the index. */
+		memcpy( pxControlRx.ucBuffer, pxMessage->ucFifoData, ucBytesToGet );
+		pxControlRx.ulNextCharIndex += ucBytesToGet;	
+	}
+
+	if( pxMessage->ulCSR0 & AT91C_UDP_RXSETUP )
+	{
+		/* Received a SETUP packet.  May be followed by data packets. */
+
+		if( ulRxBytes >= usbEXPECTED_NUMBER_OF_BYTES )
+		{		 		
+			/* Create an xUSB_REQUEST variable from the raw bytes array. */
+
+			xRequest.ucReqType = pxMessage->ucFifoData[ usbREQUEST_TYPE_INDEX ];
+			xRequest.ucRequest = pxMessage->ucFifoData[ usbREQUEST_INDEX ];
+
+			xRequest.usValue = pxMessage->ucFifoData[ usbVALUE_HIGH_BYTE ];
+			xRequest.usValue <<= 8;
+			xRequest.usValue |= pxMessage->ucFifoData[ usbVALUE_LOW_BYTE ];
+						
+			xRequest.usIndex = pxMessage->ucFifoData[ usbINDEX_HIGH_BYTE ];
+			xRequest.usIndex <<= 8;
+			xRequest.usIndex |= pxMessage->ucFifoData[ usbINDEX_LOW_BYTE ];
+			
+			xRequest.usLength = pxMessage->ucFifoData[ usbLENGTH_HIGH_BYTE ];
+			xRequest.usLength <<= 8;
+			xRequest.usLength |= pxMessage->ucFifoData[ usbLENGTH_LOW_BYTE ];
+
+			pxControlRx.ulNextCharIndex = 0;
+			if( ! (xRequest.ucReqType & 0x80) ) /* Host-to-Device transfer, may need to get data first */
+			{
+				if( xRequest.usLength > usbMAX_CONTROL_MESSAGE_SIZE )
+				{	
+					/* Too big!  No space for control data, stall and abort. */
+					prvSendStall();
+					return;
+				}
+
+				pxControlRx.ulTotalDataLength = xRequest.usLength;
+			}
+			else
+			{
+				/* We're sending the data, don't wait for any. */
+				pxControlRx.ulTotalDataLength = 0; 
+			}
+		}
+	}
+
+	/* See if we've got a pending request and all its associated data ready */
+	if( ( pxMessage->ulCSR0 & ( AT91C_UDP_RX_DATA_BK0 | AT91C_UDP_RXSETUP ) ) 
+		&& ( pxControlRx.ulNextCharIndex >= pxControlRx.ulTotalDataLength ) )
+	{
+		unsigned portCHAR ucRequest;
+
+		/* Manipulate the ucRequestType and the ucRequest parameters to 
+		generate a zero based request selection.  This is just done to 
+		break up the requests into subsections for clarity.  The 
+		alternative would be to have more huge switch statement that would
+		be difficult to optimise. */
+		ucRequest = ( ( xRequest.ucReqType & 0x60 ) >> 3 );
+		ucRequest |= ( xRequest.ucReqType & 0x03 );
+			
+		switch( ucRequest )
+		{
+			case usbSTANDARD_DEVICE_REQUEST:	
+				/* Standard Device request */
+				prvHandleStandardDeviceRequest( &xRequest );
+				break;
+
+			case usbSTANDARD_INTERFACE_REQUEST:	
+				/* Standard Interface request */
+				prvHandleStandardInterfaceRequest( &xRequest );
+				break;
+
+			case usbSTANDARD_END_POINT_REQUEST:	
+				/* Standard Endpoint request */
+				prvHandleStandardEndPointRequest( &xRequest );
+				break;
+
+			case usbCLASS_INTERFACE_REQUEST:	
+				/* Class Interface request */
+				prvHandleClassInterfaceRequest( &xRequest );
+				break;
+
+			default:	/* This is not something we want to respond to. */
+				prvSendStall();	
+		}
+	}
+}
+/*------------------------------------------------------------*/
+
+static void prvGetStandardDeviceDescriptor( xUSB_REQUEST *pxRequest )
+{
+	/* The type is in the high byte.  Return whatever has been requested. */
+	switch( ( pxRequest->usValue & 0xff00 ) >> 8 )
+	{
+		case usbDESCRIPTOR_TYPE_DEVICE:
+			prvSendControlData( ( unsigned portCHAR * ) &pxDeviceDescriptor, pxRequest->usLength, sizeof( pxDeviceDescriptor ), pdTRUE );
+			break;
+
+		case usbDESCRIPTOR_TYPE_CONFIGURATION:
+			prvSendControlData( ( unsigned portCHAR * ) &( pxConfigDescriptor ), pxRequest->usLength, sizeof( pxConfigDescriptor ), pdTRUE );
+			break;
+
+		case usbDESCRIPTOR_TYPE_STRING:
+
+			/* The index to the string descriptor is the lower byte. */
+			switch( pxRequest->usValue & 0xff )
+			{			
+				case usbLANGUAGE_STRING:
+					prvSendControlData( ( unsigned portCHAR * ) &pxLanguageStringDescriptor, pxRequest->usLength, sizeof(pxLanguageStringDescriptor), pdTRUE );
+					break;
+
+				case usbMANUFACTURER_STRING:
+					prvSendControlData( ( unsigned portCHAR * ) &pxManufacturerStringDescriptor, pxRequest->usLength, sizeof( pxManufacturerStringDescriptor ), pdTRUE );
+					break;
+
+				case usbPRODUCT_STRING:
+					prvSendControlData( ( unsigned portCHAR * ) &pxProductStringDescriptor, pxRequest->usLength, sizeof( pxProductStringDescriptor ), pdTRUE );
+					break;
+
+				case usbCONFIGURATION_STRING:
+					prvSendControlData( ( unsigned portCHAR * ) &pxConfigurationStringDescriptor, pxRequest->usLength, sizeof( pxConfigurationStringDescriptor ), pdTRUE );
+					break;
+
+				case usbINTERFACE_STRING:
+					prvSendControlData( ( unsigned portCHAR * ) &pxInterfaceStringDescriptor, pxRequest->usLength, sizeof( pxInterfaceStringDescriptor ), pdTRUE );
+					break;
+
+				default:
+					prvSendStall();
+					break;
+			}
+			break;
+
+		default:
+			prvSendStall();
+			break;
+	}
+}
+/*------------------------------------------------------------*/
+
+static void prvHandleStandardDeviceRequest( xUSB_REQUEST *pxRequest )
+{
+unsigned portSHORT usStatus = 0;
+
+	switch( pxRequest->ucRequest )
+	{
+		case usbGET_STATUS_REQUEST:
+			/* Just send two byte dummy status. */
+			prvSendControlData( ( unsigned portCHAR * ) &usStatus, sizeof( usStatus ), sizeof( usStatus ), pdFALSE );
+			break;
+
+		case usbGET_DESCRIPTOR_REQUEST:
+			/* Send device descriptor */
+			prvGetStandardDeviceDescriptor( pxRequest );
+			break;
+
+		case usbGET_CONFIGURATION_REQUEST:
+			/* Send selected device configuration */
+			prvSendControlData( ( unsigned portCHAR * ) &ucUSBConfig, sizeof( ucUSBConfig ), sizeof( ucUSBConfig ), pdFALSE );
+			break;
+
+		case usbSET_FEATURE_REQUEST:
+			prvSendZLP();
+			break;
+
+		case usbSET_ADDRESS_REQUEST:			
+			/* Get assigned address and send ack, but don't implement new address until we get a TXCOMP */
+			prvSendZLP();			
+			eDriverState = eJUST_GOT_ADDRESS;			
+			ulReceivedAddress = ( unsigned portLONG ) pxRequest->usValue;
+			break;
+
+		case usbSET_CONFIGURATION_REQUEST:
+			/* Ack SET_CONFIGURATION request, but don't implement until TXCOMP */
+			ucUSBConfig = ( unsigned portCHAR ) ( pxRequest->usValue & 0xff );
+			eDriverState = eJUST_GOT_CONFIG;
+			prvSendZLP();
+			break;
+
+		default:
+			/* Any unsupported request results in a STALL response. */
+			prvSendStall();
+			break;
+	}
+}
+/*------------------------------------------------------------*/
+
+static void prvHandleClassInterfaceRequest( xUSB_REQUEST *pxRequest )
+{
+	switch( pxRequest->ucRequest )
+	{
+		case usbSEND_ENCAPSULATED_COMMAND:
+			prvSendStall();
+			break;
+
+		case usbGET_ENCAPSULATED_RESPONSE:
+			prvSendStall();
+			break;
+
+		case usbSET_LINE_CODING:
+			/* Set line coding - baud rate, data bits, parity, stop bits */
+			prvSendZLP();
+			memcpy( ( void * ) pxLineCoding, pxControlRx.ucBuffer, sizeof( pxLineCoding ) );
+			break;
+
+		case usbGET_LINE_CODING:
+			/* Get line coding */
+			prvSendControlData( (unsigned portCHAR *) &pxLineCoding, pxRequest->usLength, sizeof( pxLineCoding ), pdFALSE );
+			break;
+
+		case usbSET_CONTROL_LINE_STATE:
+			/* D0: 1=DTR, 0=No DTR,  D1: 1=Activate Carrier, 0=Deactivate carrier (RTS, half-duplex) */
+			prvSendZLP();
+			ucControlState = pxRequest->usValue;
+			break;
+
+		default:
+			prvSendStall();
+			break;
+	}
+}
+/*------------------------------------------------------------*/
+
+static void prvGetStandardInterfaceDescriptor( xUSB_REQUEST *pxRequest )
+{
+	switch( ( pxRequest->usValue & ( unsigned portSHORT ) 0xff00 ) >> 8 )
+	{
+		default:
+			prvSendStall();
+			break;
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvHandleStandardInterfaceRequest( xUSB_REQUEST *pxRequest )
+{
+unsigned portSHORT usStatus = 0;
+
+	switch( pxRequest->ucRequest )
+	{
+		case usbGET_STATUS_REQUEST:
+			/* Send dummy 2 bytes. */
+			prvSendControlData( ( unsigned portCHAR * ) &usStatus, sizeof( usStatus ), sizeof( usStatus ), pdFALSE );
+			break;
+
+		case usbGET_DESCRIPTOR_REQUEST:
+			prvGetStandardInterfaceDescriptor( pxRequest ); 
+			break;
+
+		/* This minimal implementation does not respond to these. */
+		case usbGET_INTERFACE_REQUEST:
+		case usbSET_FEATURE_REQUEST:
+		case usbSET_INTERFACE_REQUEST:	
+
+		default:
+			prvSendStall();
+			break;
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvHandleStandardEndPointRequest( xUSB_REQUEST *pxRequest )
+{
+	switch( pxRequest->ucRequest )
+	{
+		/* This minimal implementation does not expect to respond to these. */
+		case usbGET_STATUS_REQUEST:
+		case usbCLEAR_FEATURE_REQUEST: 
+		case usbSET_FEATURE_REQUEST:
+
+		default:			
+			prvSendStall();
+			break;
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void vDetachUSBInterface( void)
+{
+	/* Setup the PIO for the USB pull up resistor. */
+	AT91C_BASE_PIOA->PIO_PER = AT91C_PIO_PA16;
+	AT91C_BASE_PIOA->PIO_OER = AT91C_PIO_PA16;
+
+
+	/* Disable pull up */
+	AT91C_BASE_PIOA->PIO_SODR = AT91C_PIO_PA16;
+} 
+/*-----------------------------------------------------------*/
+
+static void vInitUSBInterface( void )
+{
+extern void ( vUSB_ISR_Wrapper )( void );
+
+	/* Create the queue used to communicate between the USB ISR and task. */
+	xUSBInterruptQueue = xQueueCreate( usbQUEUE_LENGTH + 1, sizeof( xISRStatus * ) );
+	
+	/* Create the queues used to hold Rx and Tx characters. */
+	xRxCDC = xQueueCreate( USB_CDC_QUEUE_SIZE, ( unsigned portCHAR ) sizeof( signed portCHAR ) );
+	xTxCDC = xQueueCreate( USB_CDC_QUEUE_SIZE + 1, ( unsigned portCHAR ) sizeof( signed portCHAR ) );
+
+	if( (!xUSBInterruptQueue) || (!xRxCDC) || (!xTxCDC) )
+	{	
+		/* Not enough RAM to create queues!. */
+		return;
+	}
+	
+	/* Initialise a few state variables. */
+	pxControlTx.ulNextCharIndex = ( unsigned portLONG ) 0;
+	pxControlRx.ulNextCharIndex = ( unsigned portLONG ) 0;
+	ucUSBConfig = ( unsigned portCHAR ) 0;
+	eDriverState = eNOTHING;
+	ucControlState = 0;
+	uiCurrentBank = AT91C_UDP_RX_DATA_BK0;
+
+
+	/* HARDWARE SETUP */
+
+	/* Set the PLL USB Divider */
+	AT91C_BASE_CKGR->CKGR_PLLR |= AT91C_CKGR_USBDIV_1;
+
+	/* Enables the 48MHz USB clock UDPCK and System Peripheral USB Clock. */
+	AT91C_BASE_PMC->PMC_SCER = AT91C_PMC_UDP;
+	AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_UDP);
+
+	/* Setup the PIO for the USB pull up resistor. */
+	AT91C_BASE_PIOA->PIO_PER = AT91C_PIO_PA16;
+	AT91C_BASE_PIOA->PIO_OER = AT91C_PIO_PA16;
+
+
+	/* Start without the pullup - this will get set at the end of this 
+	function. */
+   	AT91C_BASE_PIOA->PIO_SODR = AT91C_PIO_PA16;
+
+
+	/* When using the USB debugger the peripheral registers do not always get
+	set to the correct default values.  To make sure set the relevant registers
+	manually here. */
+	AT91C_BASE_UDP->UDP_IDR = ( unsigned portLONG ) 0xffffffff;
+	AT91C_BASE_UDP->UDP_ICR = ( unsigned portLONG ) 0xffffffff;
+	AT91C_BASE_UDP->UDP_CSR[ 0 ] = ( unsigned portLONG ) 0x00;
+	AT91C_BASE_UDP->UDP_CSR[ 1 ] = ( unsigned portLONG ) 0x00;
+	AT91C_BASE_UDP->UDP_CSR[ 2 ] = ( unsigned portLONG ) 0x00;
+	AT91C_BASE_UDP->UDP_CSR[ 3 ] = ( unsigned portLONG ) 0x00;
+	AT91C_BASE_UDP->UDP_GLBSTATE = 0;
+	AT91C_BASE_UDP->UDP_FADDR = 0;
+
+	/* Enable the transceiver. */
+	AT91C_UDP_TRANSCEIVER_ENABLE = 0;
+
+	/* Enable the USB interrupts - other interrupts get enabled as the 
+	enumeration process progresses. */
+	AT91F_AIC_ConfigureIt( AT91C_ID_UDP, usbINTERRUPT_PRIORITY, AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, ( void (*)( void ) ) vUSB_ISR_Wrapper );
+	AT91C_BASE_AIC->AIC_IECR = 0x1 << AT91C_ID_UDP;
+
+
+	/* Wait a short while before making our presence known. */
+	vTaskDelay( usbINIT_DELAY );
+	AT91C_BASE_PIOA->PIO_CODR = AT91C_PIO_PA16;
+}
+/*-----------------------------------------------------------*/
+
+static void prvSendControlData( unsigned portCHAR *pucData, unsigned portSHORT usRequestedLength, unsigned portLONG ulLengthToSend, portLONG lSendingDescriptor )
+{
+	if( ( ( unsigned portLONG ) usRequestedLength < ulLengthToSend ) )
+	{
+		/* Cap the data length to that requested. */
+		ulLengthToSend = ( unsigned portSHORT ) usRequestedLength;
+	}
+	else if( ( ulLengthToSend < ( unsigned portLONG ) usRequestedLength ) && lSendingDescriptor )
+	{
+		/* We are sending a descriptor.  If the descriptor is an exact 
+		multiple of the FIFO length then it will have to be terminated
+		with a NULL packet.  Set the state to indicate this if
+		necessary. */
+		if( ( ulLengthToSend % usbFIFO_LENGTH ) == 0 )
+		{
+			eDriverState = eSENDING_EVEN_DESCRIPTOR;
+		}
+	}
+
+	/* Here we assume that the previous message has been sent.  THERE IS NO
+	BUFFER OVERFLOW PROTECTION HERE.
+
+	Copy the data to send into the buffer as we cannot send it all at once
+	(if it is greater than 8 bytes in length). */
+	memcpy( pxControlTx.ucBuffer, pucData, ulLengthToSend );
+
+	/* Reinitialise the buffer index so we start sending from the start of 
+	the data. */
+	pxControlTx.ulTotalDataLength = ulLengthToSend;
+	pxControlTx.ulNextCharIndex = ( unsigned portLONG ) 0;
+
+	/* Send the first 8 bytes now.  The rest will get sent in response to 
+	TXCOMP interrupts. */
+	prvSendNextSegment();
+}
+/*-----------------------------------------------------------*/
+
+static void prvSendNextSegment( void )
+{
+volatile unsigned portLONG ulNextLength, ulStatus, ulLengthLeftToSend;
+
+	/* Is there any data to send? */
+	if( pxControlTx.ulTotalDataLength > pxControlTx.ulNextCharIndex )
+	{
+		ulLengthLeftToSend = pxControlTx.ulTotalDataLength - pxControlTx.ulNextCharIndex;
+	
+		/* We can only send 8 bytes to the fifo at a time. */
+		if( ulLengthLeftToSend > usbFIFO_LENGTH )
+		{
+			ulNextLength = usbFIFO_LENGTH;
+		}
+		else
+		{
+			ulNextLength = ulLengthLeftToSend;
+		}
+
+		/* Wait until we can place data in the fifo.  THERE IS NO TIMEOUT
+		HERE! */
+		while( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] & AT91C_UDP_TXPKTRDY )
+		{
+			vTaskDelay( usbSHORTEST_DELAY );
+		}
+
+		/* Write the data to the FIFO. */
+		while( ulNextLength > ( unsigned portLONG ) 0 )
+		{
+			AT91C_BASE_UDP->UDP_FDR[ usbEND_POINT_0 ] = pxControlTx.ucBuffer[ pxControlTx.ulNextCharIndex ];
+	
+			ulNextLength--;
+			pxControlTx.ulNextCharIndex++;
+		}
+	
+		/* Start the transmission. */
+		portENTER_CRITICAL();
+		{
+			ulStatus = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ];
+			usbCSR_SET_BIT( &ulStatus, ( ( unsigned portLONG ) 0x10 ) );
+			AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulStatus;
+		}
+		portEXIT_CRITICAL();
+	}
+	else
+	{
+		/* There is no data to send.  If we were sending a descriptor and the 
+		descriptor was an exact multiple of the max packet size then we need
+		to send a null to terminate the transmission. */
+		if( eDriverState == eSENDING_EVEN_DESCRIPTOR )
+		{
+			prvSendZLP();
+			eDriverState = eNOTHING;
+		}
+	}
+}
+
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/USB/USB-CDC.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/USB/USB-CDC.h
new file mode 100644
index 000000000..ef997f919
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/USB/USB-CDC.h
@@ -0,0 +1,96 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+#ifndef USB_CDC_H
+#define USB_CDC_H
+
+#include "usb.h"
+
+#define USB_CDC_QUEUE_SIZE    200
+
+/* Structure used to take a snapshot of the USB status from within the ISR. */
+typedef struct X_ISR_STATUS
+{
+	unsigned portLONG ulISR;
+	unsigned portLONG ulCSR0;
+	unsigned portCHAR ucFifoData[ 8 ];
+} xISRStatus;
+
+/* Structure used to hold the received requests. */
+typedef struct 
+{
+	unsigned portCHAR ucReqType;
+	unsigned portCHAR ucRequest;
+	unsigned portSHORT usValue;
+	unsigned portSHORT usIndex;
+	unsigned portSHORT usLength;
+} xUSB_REQUEST;
+
+typedef enum
+{
+	eNOTHING,
+	eJUST_RESET,
+	eJUST_GOT_CONFIG,
+	eJUST_GOT_ADDRESS,
+	eSENDING_EVEN_DESCRIPTOR,
+	eREADY_TO_SEND
+} eDRIVER_STATE;
+
+/* Structure used to control the data being sent to the host. */
+typedef struct
+{
+	unsigned portCHAR ucBuffer[ usbMAX_CONTROL_MESSAGE_SIZE ];
+	unsigned portLONG ulNextCharIndex;
+	unsigned portLONG ulTotalDataLength;
+} xCONTROL_MESSAGE;
+
+/*-----------------------------------------------------------*/
+void vUSBCDCTask( void *pvParameters );
+
+/* Send cByte down the USB port.  Characters are simply buffered and not
+sent unless the port is connected. */
+void vUSBSendByte( portCHAR cByte );
+
+
+#endif
+
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/USB/USBIsr.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/USB/USBIsr.c
new file mode 100644
index 000000000..7190f8dd3
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/USB/USBIsr.c
@@ -0,0 +1,177 @@
+/*
+  FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+  This file is part of the FreeRTOS.org distribution.
+
+  FreeRTOS.org is free software; you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation; either version 2 of the License, or
+  (at your option) any later version.
+
+  FreeRTOS.org is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with FreeRTOS.org; if not, write to the Free Software
+  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+  A special exception to the GPL can be applied should you wish to distribute
+  a combined work that includes FreeRTOS.org, without being obliged to provide
+  the source code for any proprietary components.  See the licensing section 
+  of http://www.FreeRTOS.org for full details of how and when the exception
+  can be applied.
+
+  ***************************************************************************
+  See http://www.FreeRTOS.org for documentation, latest information, license 
+  and contact details.  Please ensure to read the configuration and relevant 
+  port sections of the online documentation.
+  ***************************************************************************
+*/
+
+
+/* 
+  BASIC INTERRUPT DRIVEN DRIVER FOR USB. 
+
+  This file contains all the usb components that must be compiled
+  to ARM mode.  The components that can be compiled to either ARM or THUMB
+  mode are contained in USB-CDC.c.
+
+*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+
+/* Demo application includes. */
+#include "Board.h"
+#include "usb.h"
+#include "USB-CDC.h"
+
+#define usbINT_CLEAR_MASK	(AT91C_UDP_TXCOMP | AT91C_UDP_STALLSENT | AT91C_UDP_RXSETUP | AT91C_UDP_RX_DATA_BK0 | AT91C_UDP_RX_DATA_BK1 )
+/*-----------------------------------------------------------*/
+
+/* Messages and queue used to communicate between the ISR and the USB task. */
+static xISRStatus xISRMessages[ usbQUEUE_LENGTH + 1 ];
+extern xQueueHandle xUSBInterruptQueue;
+/*-----------------------------------------------------------*/
+
+/* The ISR can cause a context switch so is declared naked. */
+void vUSB_ISR_Wrapper( void ) __attribute__ ((naked));
+
+/* The function that actually performs the ISR work.  This must be separate
+from the wrapper function to ensure the correct stack frame gets set up. */
+void vUSB_ISR_Handler( void );
+/*-----------------------------------------------------------*/
+
+void vUSB_ISR_Handler( void )
+{
+portCHAR cTaskWokenByPost = pdFALSE;
+static volatile unsigned portLONG ulNextMessage = 0;
+xISRStatus *pxMessage;
+unsigned portLONG ulRxBytes;
+unsigned portCHAR ucFifoIndex;
+
+    /* Use the next message from the array. */
+	pxMessage = &( xISRMessages[ ( ulNextMessage & usbQUEUE_LENGTH ) ] );
+	ulNextMessage++;
+
+    /* Save UDP ISR state for task-level processing. */
+	pxMessage->ulISR = AT91C_BASE_UDP->UDP_ISR;
+	pxMessage->ulCSR0 = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ];
+
+    /* Clear interrupts from ICR. */
+	AT91C_BASE_UDP->UDP_ICR = AT91C_BASE_UDP->UDP_IMR | AT91C_UDP_ENDBUSRES;
+	
+    
+	/* Process incoming FIFO data.  Must set DIR (if needed) and clear RXSETUP 
+	before exit. */
+
+    /* Read CSR and get incoming byte count. */
+	ulRxBytes = ( pxMessage->ulCSR0 >> 16 ) & usbRX_COUNT_MASK;
+	
+	/* Receive control transfers on endpoint 0. */
+	if( pxMessage->ulCSR0 & ( AT91C_UDP_RXSETUP | AT91C_UDP_RX_DATA_BK0 ) )
+	{
+		/* Save FIFO data buffer for either a SETUP or DATA stage */
+		for( ucFifoIndex = 0; ucFifoIndex < ulRxBytes; ucFifoIndex++ )
+		{
+			pxMessage->ucFifoData[ ucFifoIndex ] = AT91C_BASE_UDP->UDP_FDR[ usbEND_POINT_0 ];
+		}
+
+		/* Set direction for data stage.  Must be done before RXSETUP is 
+		cleared. */
+		if( ( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] & AT91C_UDP_RXSETUP ) )
+		{
+			if( ulRxBytes && ( pxMessage->ucFifoData[ usbREQUEST_TYPE_INDEX ] & 0x80 ) )
+			{
+				AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] |= AT91C_UDP_DIR;
+
+				/* Might not be wise in an ISR! */
+				while( !(AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] & AT91C_UDP_DIR) );
+			}
+
+			/* Clear RXSETUP */
+			AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] &= ~AT91C_UDP_RXSETUP;
+
+			/* Might not be wise in an ISR! */
+			while ( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] & AT91C_UDP_RXSETUP );
+		}
+		else
+		{
+		   /* Clear RX_DATA_BK0 */
+		   AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] &= ~AT91C_UDP_RX_DATA_BK0;
+
+		   /* Might not be wise in an ISR! */
+		   while ( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] & AT91C_UDP_RX_DATA_BK0 );
+		}
+	}
+	
+	/* If we received data on endpoint 1, disable its interrupts until it is 
+	processed in the main loop */
+	if( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] & ( AT91C_UDP_RX_DATA_BK0 | AT91C_UDP_RX_DATA_BK1 ) )
+	{
+		AT91C_BASE_UDP->UDP_IDR = AT91C_UDP_EPINT1;
+	}
+	
+	AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] &= ~( AT91C_UDP_TXCOMP | AT91C_UDP_STALLSENT );
+     
+	/* Clear interrupts for the other endpoints, retain data flags for endpoint 
+	1. */
+	AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] &= ~( AT91C_UDP_TXCOMP | AT91C_UDP_STALLSENT | AT91C_UDP_RXSETUP );
+	AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_2 ] &= ~usbINT_CLEAR_MASK;
+	AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_3 ] &= ~usbINT_CLEAR_MASK;
+
+	/* Post ISR data to queue for task-level processing */
+	cTaskWokenByPost = xQueueSendFromISR( xUSBInterruptQueue, &pxMessage, cTaskWokenByPost );
+
+	/* Clear AIC to complete ISR processing */
+	AT91C_BASE_AIC->AIC_EOICR = 0;
+
+	/* Do a task switch if needed */
+	if( cTaskWokenByPost )
+	{
+		/* This call will ensure that the unblocked task will be executed
+		immediately upon completion of the ISR if it has a priority higher
+		than the interrupted task. */
+		portYIELD_FROM_ISR();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vUSB_ISR_Wrapper( void )
+{
+	/* Save the context of the interrupted task. */
+	portSAVE_CONTEXT();
+
+	/* Call the handler to do the work.  This must be a separate
+	function to ensure the stack frame is set up correctly. */
+	vUSB_ISR_Handler();
+
+	/* Restore the context of whichever task will execute next. */
+	portRESTORE_CONTEXT();
+}
+
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/USB/descriptors.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/USB/descriptors.h
new file mode 100644
index 000000000..fd5be1f4a
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/USB/descriptors.h
@@ -0,0 +1,213 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+/*
+	- DESCRIPTOR DEFINITIONS -
+*/
+
+/* String descriptors used during the enumeration process.
+These take the form:
+
+{
+	Length of descriptor,
+	Descriptor type,
+	Data
+}
+*/
+
+const portCHAR pxLanguageStringDescriptor[] =
+{
+	4,
+	usbDESCRIPTOR_TYPE_STRING,
+	0x09, 0x04
+};
+
+const portCHAR pxManufacturerStringDescriptor[] = 
+{
+	18,
+	usbDESCRIPTOR_TYPE_STRING,
+
+	'F', 0x00, 'r', 0x00, 'e', 0x00, 'e', 0x00, 'R', 0x00, 'T', 0x00, 'O', 0x00, 'S', 0x00
+};
+
+const portCHAR pxProductStringDescriptor[] = 
+{
+	36,
+	usbDESCRIPTOR_TYPE_STRING,
+
+	'F', 0x00, 'r', 0x00, 'e', 0x00, 'e', 0x00, 'R', 0x00, 'T', 0x00, 'O', 0x00, 'S', 0x00, ' ', 0x00, 'C', 0x00, 'D', 0x00,
+	'C', 0x00, ' ', 0x00, 'D', 0x00, 'E', 0x00, 'M', 0x00, 'O', 0x00
+};
+
+const portCHAR pxConfigurationStringDescriptor[] = 
+{
+	38,
+	usbDESCRIPTOR_TYPE_STRING,
+
+	'C', 0x00, 'o', 0x00, 'n', 0x00, 'f', 0x00, 'i', 0x00, 'g', 0x00, 'u', 0x00, 'r', 0x00, 'a', 0x00, 't', 0x00, 'i', 0x00,
+	'o', 0x00, 'n', 0x00, ' ', 0x00, 'N', 0x00, 'a', 0x00, 'm', 0x00, 'e', 0x00
+};
+
+const portCHAR pxInterfaceStringDescriptor[] = 
+{
+	30,
+	usbDESCRIPTOR_TYPE_STRING,
+
+	'I', 0x00, 'n', 0x00, 't', 0x00, 'e', 0x00, 'r', 0x00, 'f', 0x00, 'a', 0x00, 'c', 0x00, 'e', 0x00, ' ', 0x00, 'N', 0x00,
+	'a', 0x00, 'm', 0x00, 'e', 0x00
+};
+
+/* Device should properly be 0x134A:0x9001, using 0x05F9:0xFFFF for Linux testing */
+const char pxDeviceDescriptor[] = 
+{
+	/* Device descriptor */
+	0x12,								/* bLength				*/
+	0x01,								/* bDescriptorType		*/
+	0x10, 0x01,							/* bcdUSBL				*/
+	0x02,								/* bDeviceClass:		*/
+	0x00,								/* bDeviceSubclass:		*/
+	0x00,								/* bDeviceProtocol:		*/
+	0x08,								/* bMaxPacketSize0		*/
+	0x03, 0xEB,							/* idVendorL			*/
+	0x20, 0x09,							/* idProductL			*/
+	0x10, 0x01,							/* bcdDeviceL			*/
+	usbMANUFACTURER_STRING,  			/* iManufacturer		*/
+	usbPRODUCT_STRING,					/* iProduct				*/
+	0x00,								/* SerialNumber			*/
+	0x01								/* bNumConfigs			*/
+};
+
+const char pxConfigDescriptor[] = {
+
+	/* Configuration 1 descriptor
+	Here we define two interfaces (0 and 1) and a total of 3 endpoints.
+	Interface 0 is a CDC Abstract Control Model interface with one interrupt-in endpoint.
+	Interface 1 is a CDC Data Interface class, with a bulk-in and bulk-out endpoint.
+	Endpoint 0 gets used as the CDC management element.
+	*/
+	0x09,				/* CbLength								*/
+	0x02,				/* CbDescriptorType					  	*/
+	0x43, 0x00,			/* CwTotalLength 2 EP + Control		?	*/
+	0x02,				/* CbNumInterfaces			  			*/
+	0x01,				/* CbConfigurationValue					*/
+	usbCONFIGURATION_STRING,/* CiConfiguration					*/
+	usbBUS_POWERED,		/* CbmAttributes Bus powered + Remote Wakeup*/
+	0x32,				/* CMaxPower: 100mA						*/
+
+	/* Communication Class Interface Descriptor Requirement		*/
+	0x09,				/* bLength								*/
+	0x04,				/* bDescriptorType						*/
+	0x00,				/* bInterfaceNumber						*/
+	0x00,				/* bAlternateSetting					*/
+	0x01,				/* bNumEndpoints						*/
+	0x02,				/* bInterfaceClass: Comm Interface Class */
+	0x02,				/* bInterfaceSubclass: Abstract Control Model*/
+	0x00,				/* bInterfaceProtocol					*/
+	usbINTERFACE_STRING,/* iInterface							*/
+
+	/* Header Functional Descriptor								*/
+	0x05,				/* bLength								*/
+	0x24,				/* bDescriptor type: CS_INTERFACE		*/
+	0x00,				/* bDescriptor subtype: Header Func Desc*/
+	0x10, 0x01,			/* bcdCDC:1.1  							*/
+
+	/* ACM Functional Descriptor								*/
+	0x04,				/* bFunctionLength						*/
+	0x24,				/* bDescriptor type: CS_INTERFACE		*/
+	0x02,				/* bDescriptor subtype: ACM Func Desc	*/
+	0x00,				/* bmCapabilities: We don't support squat*/
+
+	/* Union Functional Descriptor								*/
+	0x05,				/* bFunctionLength						*/
+	0x24,				/* bDescriptor type: CS_INTERFACE		*/
+	0x06,				/* bDescriptor subtype: Union Func Desc	*/
+	0x00,				/* bMasterInterface: CDC Interface		*/
+	0x01,				/* bSlaveInterface0: Data Class Interface*/
+
+	/* Call Management Functional Descriptor
+	0 in D1 and D0 indicates that device does not handle call management*/
+	0x05,				/* bFunctionLength						*/
+	0x24,				/* bDescriptor type: CS_INTERFACE		*/
+	0x01,				/* bDescriptor subtype: Call Management Func*/
+	0x00,				/* bmCapabilities: D1 + D0				*/
+	0x01,				/* bDataInterface: Data Class Interface 1*/
+
+	/* CDC Control - Endpoint 3 descriptor
+	This endpoint serves as a notification element.				*/
+
+	0x07,				/* bLength								*/
+	0x05,				/* bDescriptorType						*/
+	0x83,				/* bEndpointAddress, Endpoint 03 - IN	*/
+	0x03,				/* bmAttributes	  INT					*/
+	0x08, 0x00,			/* wMaxPacketSize: 8 bytes		   		*/
+	0xFF,				/* bInterval							*/
+
+	/* Data Class Interface Descriptor Requirement				*/
+	0x09,				/* bLength								*/
+	0x04,				/* bDescriptorType						*/
+	0x01,				/* bInterfaceNumber						*/
+	0x00,				/* bAlternateSetting					*/
+	0x02,				/* bNumEndPoints						*/
+	0x0A,				/* bInterfaceClass						*/
+	0x00,				/* bInterfaceSubclass					*/
+	0x00,				/* bInterfaceProtocol					*/
+	0x00,				/* iInterface							*/
+
+	/* CDC Data - Endpoint 1 descriptor */
+	0x07,				/* bLenght								*/
+	0x05,				/* bDescriptorType						*/
+	0x01,				/* bEndPointAddress, Endpoint 01 - OUT	*/
+	0x02,				/* bmAttributes BULK					*/
+	64,					/* wMaxPacketSize						*/
+	0x00,
+	0x00,				/* bInterval							*/
+
+	/* CDC Data - Endpoint 2 descriptor */
+	0x07,				/* bLength								*/
+	0x05,				/* bDescriptorType						*/
+	0x82,				/* bEndPointAddress, Endpoint 02 - IN	*/
+	0x02,				/* bmAttributes BULK					*/
+	64,					/* wMaxPacketSize						*/
+	0x00,
+	0x00				/* bInterval							*/
+};
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/USB/usb.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/USB/usb.h
new file mode 100644
index 000000000..c4dcdc906
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/USB/usb.h
@@ -0,0 +1,154 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+/* Descriptor type definitions. */
+#define usbDESCRIPTOR_TYPE_DEVICE			( 0x01 )
+#define usbDESCRIPTOR_TYPE_CONFIGURATION	( 0x02 )
+#define usbDESCRIPTOR_TYPE_STRING			( 0x03 )
+
+/* USB request type definitions. */
+#define usbGET_REPORT_REQUEST				( 0x01 )
+#define usbGET_IDLE_REQUEST					( 0x02 )
+#define usbGET_PROTOCOL_REQUEST				( 0x03 )
+#define usbSET_REPORT_REQUEST				( 0x09 )
+#define usbSET_IDLE_REQUEST					( 0x0A )
+#define usbSET_PROTOCOL_REQUEST				( 0x0B )
+#define usbGET_CONFIGURATION_REQUEST		( 0x08 )
+#define usbGET_STATUS_REQUEST				( 0x00 )
+#define usbCLEAR_FEATURE_REQUEST			( 0x01 )
+#define usbSET_FEATURE_REQUEST				( 0x03 )
+#define usbSET_ADDRESS_REQUEST				( 0x05 )
+#define usbGET_DESCRIPTOR_REQUEST			( 0x06 )
+#define usbSET_CONFIGURATION_REQUEST		( 0x09 )
+#define usbGET_INTERFACE_REQUEST			( 0x0A )
+#define usbSET_INTERFACE_REQUEST			( 0x0B )
+
+/* ACM Requests */
+#define usbSEND_ENCAPSULATED_COMMAND		( 0x00 )
+#define usbGET_ENCAPSULATED_RESPONSE		( 0x01 )
+#define usbSET_LINE_CODING					( 0x20 )
+#define usbGET_LINE_CODING					( 0x21 )
+#define usbSET_CONTROL_LINE_STATE			( 0x22 )
+
+/* Misc USB definitions. */
+#define usbDEVICE_CLASS_VENDOR_SPECIFIC		( 0xFF )
+#define usbBUS_POWERED						( 0x80 )
+#define usbHID_REPORT_DESCRIPTOR			( 0x22 )
+#define AT91C_UDP_TRANSCEIVER_ENABLE		( *( ( unsigned long * ) 0xfffb0074 ) )
+
+/* Index to the various string. */
+#define usbLANGUAGE_STRING					( 0 )
+#define usbMANUFACTURER_STRING				( 1 )
+#define usbPRODUCT_STRING					( 2 )
+#define usbCONFIGURATION_STRING				( 3 )
+#define usbINTERFACE_STRING					( 4 )
+
+/* Defines fields of standard SETUP request.  Now in normal order. */
+#define usbREQUEST_TYPE_INDEX				( 0 )
+#define usbREQUEST_INDEX					( 1 )
+#define usbVALUE_HIGH_BYTE					( 3 )
+#define usbVALUE_LOW_BYTE					( 2 )
+#define usbINDEX_HIGH_BYTE					( 5 )
+#define usbINDEX_LOW_BYTE					( 4 )
+#define usbLENGTH_HIGH_BYTE					( 7 )
+#define usbLENGTH_LOW_BYTE					( 6 )
+
+/* Misc application definitions. */
+#define usbINTERRUPT_PRIORITY				( 3 )
+#define usbQUEUE_LENGTH						( 0x3 )	/* Must have all bits set! */
+#define usbFIFO_LENGTH						( ( unsigned portLONG ) 8 )
+#define usbEND_POINT_0						( 0 )
+#define usbEND_POINT_1						( 1 )
+#define usbEND_POINT_2						( 2 )
+#define usbEND_POINT_3						( 3 )
+#define usbMAX_CONTROL_MESSAGE_SIZE			( 128 )
+#define usbRX_COUNT_MASK					( ( unsigned portLONG ) 0x7ff )
+#define AT91C_UDP_STALLSENT					AT91C_UDP_ISOERROR
+#define usbSHORTEST_DELAY					( ( portTickType ) 1 )
+#define usbINIT_DELAY						( ( portTickType ) 1000 / portTICK_RATE_MS )
+#define usbSHORT_DELAY						( ( portTickType ) 50 / portTICK_RATE_MS )
+#define usbEND_POINT_RESET_MASK				( ( unsigned portLONG ) 0x0f )
+#define usbDATA_INC							( ( portCHAR ) 5 )
+#define usbEXPECTED_NUMBER_OF_BYTES			( ( unsigned portLONG ) 8 )
+
+/* Control request types. */
+#define usbSTANDARD_DEVICE_REQUEST			( 0 )
+#define usbSTANDARD_INTERFACE_REQUEST		( 1 )
+#define usbSTANDARD_END_POINT_REQUEST		( 2 )
+#define usbCLASS_INTERFACE_REQUEST			( 5 )
+
+
+/* Macros to manipulate the control and status registers.  These registers 
+cannot be accessed using a direct read modify write operation outside of the 
+ISR as some bits are left unchanged by writing with a 0, and some are left 
+unchanged by writing with a 1. */
+
+
+#define usbCSR_SET_BIT( pulValueNow, ulBit )											\
+{																						\
+	/* Set TXCOMP, RX_DATA_BK0, RXSETUP, */												\
+	/* STALLSENT and RX_DATA_BK1 to 1 so the */											\
+	/* write has no effect. */															\
+	( * ( ( unsigned portLONG * ) pulValueNow ) ) |= ( unsigned portLONG ) 0x4f;		\
+																						\
+	/* Clear the FORCE_STALL and TXPKTRDY bits */										\
+	/* so the write has no effect. */													\
+	( * ( ( unsigned portLONG * ) pulValueNow ) ) &= ( unsigned portLONG ) 0xffffffcf;	\
+																						\
+	/* Set whichever bit we want set. */												\
+	( * ( ( unsigned portLONG * ) pulValueNow ) ) |= ( ulBit );							\
+}
+
+#define usbCSR_CLEAR_BIT( pulValueNow, ulBit )											\
+{																						\
+	/* Set TXCOMP, RX_DATA_BK0, RXSETUP, */												\
+	/* STALLSENT and RX_DATA_BK1 to 1 so the */											\
+	/* write has no effect. */															\
+	( * ( ( unsigned portLONG * ) pulValueNow ) ) |= ( unsigned portLONG ) 0x4f;		\
+																						\
+	/* Clear the FORCE_STALL and TXPKTRDY bits */										\
+	/* so the write has no effect. */													\
+	( * ( ( unsigned portLONG * ) pulValueNow ) ) &= ( unsigned portLONG ) 0xffffffcf;	\
+																						\
+	/* Clear whichever bit we want clear. */											\
+	( * ( ( unsigned portLONG * ) pulValueNow ) ) &= ( ~ulBit );						\
+}
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/atmel-rom.ld b/20080212/Demo/lwIP_Demo_Rowley_ARM7/atmel-rom.ld
new file mode 100644
index 000000000..db22b4acd
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/atmel-rom.ld
@@ -0,0 +1,49 @@
+MEMORY 
+{
+	flash	: ORIGIN = 0x00100000, LENGTH = 256K
+	ram		: ORIGIN = 0x00200000, LENGTH = 64K
+}
+
+__stack_end__ = 0x00200000 + 64K - 4;
+
+SECTIONS 
+{
+	. = 0;
+	startup : { *(.startup)} >flash
+
+	prog : 
+	{
+		*(.text)
+		*(.rodata)
+		*(.rodata*)
+		*(.glue_7)
+		*(.glue_7t)
+	} >flash
+
+	__end_of_text__ = .;
+
+	.data : 
+	{
+		__data_beg__ = .;
+		__data_beg_src__ = __end_of_text__;
+		*(.data)
+		__data_end__ = .;
+	} >ram AT>flash
+
+	.bss : 
+	{
+		__bss_beg__ = .;
+		*(.bss)
+	} >ram
+
+	/* Align here to ensure that the .bss section occupies space up to
+	_end.  Align after .bss to ensure correct alignment even if the
+	.bss section disappears because there are no input sections.  */
+	. = ALIGN(32 / 8);
+}
+	. = ALIGN(32 / 8);
+	_end = .;
+	_bss_end__ = . ; __bss_end__ = . ; __end__ = . ;
+	PROVIDE (end = .);
+
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/boot.s b/20080212/Demo/lwIP_Demo_Rowley_ARM7/boot.s
new file mode 100644
index 000000000..88fac35db
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/boot.s
@@ -0,0 +1,161 @@
+	/* Sample initialization file */
+
+	.extern main
+	.extern exit
+	.extern AT91F_LowLevelInit
+
+	.text
+	.code 32
+
+
+	.align  0
+
+	.extern __stack_end__
+	.extern __bss_beg__
+	.extern __bss_end__
+	.extern __data_beg__
+	.extern __data_end__
+	.extern __data+beg_src__
+
+	.global start
+	.global endless_loop
+
+	/* Stack Sizes */
+    .set  UND_STACK_SIZE, 0x00000004
+    .set  ABT_STACK_SIZE, 0x00000004
+    .set  FIQ_STACK_SIZE, 0x00000004
+    .set  IRQ_STACK_SIZE, 0X00000400
+    .set  SVC_STACK_SIZE, 0x00000400
+
+	/* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */
+    .set  MODE_USR, 0x10            /* User Mode */
+    .set  MODE_FIQ, 0x11            /* FIQ Mode */
+    .set  MODE_IRQ, 0x12            /* IRQ Mode */
+    .set  MODE_SVC, 0x13            /* Supervisor Mode */
+    .set  MODE_ABT, 0x17            /* Abort Mode */
+    .set  MODE_UND, 0x1B            /* Undefined Mode */
+    .set  MODE_SYS, 0x1F            /* System Mode */
+
+    .equ  I_BIT, 0x80               /* when I bit is set, IRQ is disabled */
+    .equ  F_BIT, 0x40               /* when F bit is set, FIQ is disabled */
+
+
+start:
+_start:
+_mainCRTStartup:
+
+	/* Setup a stack for each mode - note that this only sets up a usable stack
+	for system/user, SWI and IRQ modes.   Also each mode is setup with
+	interrupts initially disabled. */
+    ldr   r0, .LC6
+    msr   CPSR_c, #MODE_UND|I_BIT|F_BIT /* Undefined Instruction Mode */
+    mov   sp, r0
+    sub   r0, r0, #UND_STACK_SIZE
+    msr   CPSR_c, #MODE_ABT|I_BIT|F_BIT /* Abort Mode */
+    mov   sp, r0
+    sub   r0, r0, #ABT_STACK_SIZE
+    msr   CPSR_c, #MODE_FIQ|I_BIT|F_BIT /* FIQ Mode */
+    mov   sp, r0
+    sub   r0, r0, #FIQ_STACK_SIZE
+    msr   CPSR_c, #MODE_IRQ|I_BIT|F_BIT /* IRQ Mode */
+    mov   sp, r0
+    sub   r0, r0, #IRQ_STACK_SIZE
+    msr   CPSR_c, #MODE_SVC|I_BIT|F_BIT /* Supervisor Mode */
+    mov   sp, r0
+    sub   r0, r0, #SVC_STACK_SIZE
+    msr   CPSR_c, #MODE_SYS|I_BIT|F_BIT /* System Mode */
+    mov   sp, r0
+
+	/* We want to start in supervisor mode.  Operation will switch to system
+	mode when the first task starts. */
+	msr   CPSR_c, #MODE_SVC|I_BIT|F_BIT
+
+    bl		AT91F_LowLevelInit
+
+	/* Clear BSS. */
+
+	mov     a2, #0			/* Fill value */
+	mov		fp, a2			/* Null frame pointer */
+	mov		r7, a2			/* Null frame pointer for Thumb */
+
+	ldr		r1, .LC1		/* Start of memory block */
+	ldr		r3, .LC2		/* End of memory block */
+	subs	r3, r3, r1      /* Length of block */
+	beq		.end_clear_loop
+	mov		r2, #0
+
+.clear_loop:
+	strb	r2, [r1], #1
+	subs	r3, r3, #1
+	bgt		.clear_loop
+
+.end_clear_loop:
+
+	/* Initialise data. */
+
+	ldr		r1, .LC3		/* Start of memory block */
+	ldr		r2, .LC4		/* End of memory block */
+	ldr		r3, .LC5
+	subs	r3, r3, r1		/* Length of block */
+	beq		.end_set_loop
+
+.set_loop:
+	ldrb	r4, [r2], #1
+	strb	r4, [r1], #1
+	subs	r3, r3, #1
+	bgt		.set_loop
+
+.end_set_loop:
+
+	mov		r0, #0          /* no arguments  */
+	mov		r1, #0          /* no argv either */
+
+    ldr lr, =main	
+	bx	lr
+
+endless_loop:
+	b               endless_loop
+
+
+	.align 0
+
+	.LC1:
+	.word   __bss_beg__
+	.LC2:
+	.word   __bss_end__
+	.LC3:
+	.word   __data_beg__
+	.LC4:
+	.word   __data_beg_src__
+	.LC5:
+	.word   __data_end__
+	.LC6:
+	.word	__stack_end__
+
+
+	/* Setup vector table.  Note that undf, pabt, dabt, fiq just execute
+	a null loop. */
+
+.section .startup,"ax"
+         .code 32
+         .align 0
+
+	b     _start						/* reset - _start			*/
+	ldr   pc, _undf						/* undefined - _undf		*/
+	ldr   pc, _swi						/* SWI - _swi				*/
+	ldr   pc, _pabt						/* program abort - _pabt	*/
+	ldr   pc, _dabt						/* data abort - _dabt		*/
+	nop									/* reserved					*/
+	ldr   pc, [pc,#-0xF20]				/* IRQ - read the AIC		*/
+	ldr   pc, _fiq						/* FIQ - _fiq				*/
+
+_undf:  .word __undf                    /* undefined				*/
+_swi:   .word swi_handler				/* SWI						*/
+_pabt:  .word __pabt                    /* program abort			*/
+_dabt:  .word __dabt                    /* data abort				*/
+_fiq:   .word __fiq                     /* FIQ						*/
+
+__undf: b     .                         /* undefined				*/
+__pabt: b     .                         /* program abort			*/
+__dabt: b     .                         /* data abort				*/
+__fiq:  b     .                         /* FIQ						*/
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/crt0.s b/20080212/Demo/lwIP_Demo_Rowley_ARM7/crt0.s
new file mode 100644
index 000000000..a16c22012
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/crt0.s
@@ -0,0 +1,265 @@
+/*****************************************************************************
+ * Copyright (c) 2001, 2002 Rowley Associates Limited.                       *
+ *                                                                           *
+ * This file may be distributed under the terms of the License Agreement     *
+ * provided with this software.                                              *
+ *                                                                           *
+ * THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE   *
+ * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
+ *****************************************************************************/
+  .section .init, "ax"
+  .code 32
+  .align 0
+                
+  .weak _start
+  .global __start
+  .global __gccmain
+  .extern main
+  .extern exit
+
+/*****************************************************************************
+ * Function    : _start                                                      *
+ * Description : Main entry point and startup code for C system.             *
+ *****************************************************************************/
+_start:
+__start:                        
+  mrs r0, cpsr
+  bic r0, r0, #0x1F
+
+  /* Setup stacks */ 
+  orr r1, r0, #0x1B /* Undefined mode */
+  msr cpsr_cxsf, r1
+  ldr sp, =__stack_und_end__
+  
+  orr r1, r0, #0x17 /* Abort mode */
+  msr cpsr_cxsf, r1
+  ldr sp, =__stack_abt_end__
+
+  orr r1, r0, #0x12 /* IRQ mode */
+  msr cpsr_cxsf, r1
+  ldr sp, =__stack_irq_end__
+
+  orr r1, r0, #0x11 /* FIQ mode */
+  msr cpsr_cxsf, r1
+  ldr sp, =__stack_fiq_end__
+
+  orr r1, r0, #0x13 /* Supervisor mode */
+  msr cpsr_cxsf, r1
+  ldr sp, =__stack_svc_end__
+#ifdef SUPERVISOR_START
+  /* Start application in supervisor mode */
+  ldr r1, =__stack_end__ /* Setup user/system mode stack */ 
+  mov r2, sp
+  stmfd r2!, {r1}
+  ldmfd r2, {sp}^
+#else
+  /* Start application in system mode */
+  orr r1, r0, #0x1F /* System mode */
+  msr cpsr_cxsf, r1
+  ldr sp, =__stack_end__
+#endif
+  
+  /* Copy from initialised data section to data section (if necessary). */
+  ldr r0, =__data_load_start__
+  ldr r1, =__data_start__
+  cmp r0, r1
+  beq copy_data_end
+  
+  ldr r2, =__data_end__
+  subs r2, r2, r1
+  beq copy_data_end
+  
+copy_data_loop:
+  ldrb r3, [r0], #+1
+  strb r3, [r1], #+1
+  subs r2, r2, #1
+  bne copy_data_loop
+copy_data_end:  
+
+  /* Copy from initialised text section to text section (if necessary). */
+  ldr r0, =__text_load_start__
+  ldr r1, =__text_start__
+  cmp r0, r1
+  beq copy_text_end
+  
+  ldr r2, =__text_end__
+  subs r2, r2, r1
+  beq copy_text_end
+  
+copy_text_loop:
+  ldrb r3, [r0], #+1
+  strb r3, [r1], #+1
+  subs r2, r2, #1
+  bne copy_text_loop
+copy_text_end:  
+
+  /* Copy from initialised fast_text section to fast_text section (if necessary). */
+  ldr r0, =__fast_load_start__
+  ldr r1, =__fast_start__
+  cmp r0, r1
+  beq copy_fast_end
+  
+  ldr r2, =__fast_end__
+  subs r2, r2, r1
+  beq copy_fast_end
+  
+copy_fast_loop:
+  ldrb r3, [r0], #+1
+  strb r3, [r1], #+1
+  subs r2, r2, #1
+  bne copy_fast_loop
+copy_fast_end:  
+
+  /* Zero the bss. */
+  ldr r0, =__bss_start__
+  ldr r1, =__bss_end__
+  mov r2, #0
+zero_bss_loop:
+  cmp r0, r1
+  beq zero_bss_end
+  strb r2, [r0], #+1
+  b zero_bss_loop
+zero_bss_end:    
+
+#ifdef CHECK  
+  /* Check data */
+  ldr r0, =__data_load_start__
+  ldr r1, =__data_start__
+  cmp r0, r1
+  beq check_data_end
+  ldr r2, =__data_end__
+  subs r2, r2, r1
+  beq check_data_end
+  
+check_data_loop:
+  ldrb r3, [r0], #+1
+  ldrb r4, [r1], #+1
+  cmp r3, r4
+  bne data_error_loop
+  subs r2, r2, #1
+  bne check_data_loop
+check_data_end:  
+
+  /* Check text */
+  ldr r0, =__text_load_start__
+  ldr r1, =__text_start__
+  cmp r0, r1
+  beq check_text_end
+  ldr r2, =__text_end__
+  subs r2, r2, r1
+  beq check_text_end
+  
+check_text_loop:
+  ldrb r3, [r0], #+1
+  ldrb r4, [r1], #+1
+  cmp r3, r4
+  bne text_error_loop
+  subs r2, r2, #1
+  bne check_text_loop
+check_text_end:  
+
+  /* Check fast */
+  ldr r0, =__fast_load_start__
+  ldr r1, =__fast_start__
+  cmp r0, r1
+  beq check_fast_end
+  ldr r2, =__fast_end__
+  subs r2, r2, r1
+  beq check_fast_end
+  
+check_fast_loop:
+  ldrb r3, [r0], #+1
+  ldrb r4, [r1], #+1
+  cmp r3, r4
+  bne fast_error_loop
+  subs r2, r2, #1
+  bne check_fast_loop
+check_fast_end:  
+
+  /* Check bss */
+  ldr r0, =__bss_start__
+  ldr r1, =__bss_end__
+  mov r2, #0
+check_bss_loop:
+  cmp r0, r1
+  beq check_bss_end
+  ldrb r2, [r0], #+1
+  cmp r2, #0
+  bne bss_error_loop  
+  b check_bss_loop
+check_bss_end:    
+#endif
+
+  /* Initialise the heap */
+  ldr r0, = __heap_start__
+  ldr r1, = __heap_end__
+  sub r1, r1, r0     /* r1 = r1-r0 */ 
+  mov r2, #0
+  str r2, [r0], #+4 /* *r0++ = 0 */
+  str r1, [r0]      /* *r0 = __heap_end__ - __heap_start__ */
+
+  /* Call constructors */
+  ldr r0, =__ctors_start__
+  ldr r1, =__ctors_end__
+ctor_loop:
+  cmp r0, r1
+  beq ctor_end
+  ldr r2, [r0], #+4
+  stmfd sp!, {r0-r1}
+  mov lr, pc
+  mov pc, r2
+  ldmfd sp!, {r0-r1}
+  b ctor_loop
+ctor_end:
+
+  /* Setup initial call frame */
+  mov lr, #4
+  mov r12, sp
+  stmfd sp!, {r11-r12, lr-pc}
+  sub r11, r12, #0x00000004
+
+start:
+  /* Jump to main entry point */
+  mov r0, #0
+  mov r1, #0
+  ldr r2, =main
+  mov lr, pc
+#ifdef __ARM_ARCH_3__
+  mov pc, r2
+#else    
+  bx r2
+#endif
+
+  /* Call destructors */
+  ldr r0, =__dtors_start__
+  ldr r1, =__dtors_end__
+dtor_loop:
+  cmp r0, r1
+  beq dtor_end
+  ldr r2, [r0], #+4
+  stmfd sp!, {r0-r1}
+  mov lr, pc
+  mov pc, r2
+  ldmfd sp!, {r0-r1}
+  b dtor_loop
+dtor_end:
+
+  /* Return from main, loop forever. */
+exit_loop:
+  b exit_loop
+
+#ifdef CHECK
+data_error_loop:
+  b data_error_loop
+
+text_error_loop:
+  b text_error_loop
+  
+fast_error_loop:
+  b fast_error_loop
+  
+bss_error_loop:
+  b bss_error_loop  
+#endif
+  
+                  
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/flash_placement.xml b/20080212/Demo/lwIP_Demo_Rowley_ARM7/flash_placement.xml
new file mode 100644
index 000000000..0df08fd26
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/flash_placement.xml
@@ -0,0 +1,29 @@
+
+
+  
+    
+    
+    
+    
+    
+    
+    
+    
+    
+  
+  
+    
+    
+    
+    
+    
+    
+    
+    
+    
+  
+  
+    
+    
+  
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/CHANGELOG b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/CHANGELOG
new file mode 100644
index 000000000..67a56cd62
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/CHANGELOG
@@ -0,0 +1,536 @@
+FUTURE
+
+  * TODO: The lwIP source code makes some invalid assumptions on processor
+    word-length, storage sizes and alignment. See the mailing lists for
+    problems with exoteric (/DSP) architectures showing these problems.
+    We still have to fix some of these issues neatly.
+
+  * TODO: the ARP layer is not protected against concurrent access. If
+    you run from a multitasking OS, serialize access to ARP (called from
+    your network device driver and from a timeout thread.)
+
+HISTORY
+
+(HEAD)
+
+  2004-12-28 Leon Woestenberg 
+  * etharp.*: Disabled multiple packets on the ARP queue.
+    This clashes with TCP queueing.
+
+  2004-11-28 Leon Woestenberg 
+  * etharp.*: Fixed race condition from ARP request to ARP timeout.
+    Halved the ARP period, doubled the period counts.
+    ETHARP_MAX_PENDING now should be at least 2. This prevents
+    the counter from reaching 0 right away (which would allow
+    too little time for ARP responses to be received).
+    
+  2004-11-25 Leon Woestenberg 
+  * dhcp.c: Decline messages were not multicast but unicast.
+  * etharp.c: ETHARP_CREATE is renamed to ETHARP_TRY_HARD.
+    Do not try hard to insert arbitrary packet's source address,
+    etharp_ip_input() now calls etharp_update() without ETHARP_TRY_HARD. 
+    etharp_query() now always DOES call ETHARP_TRY_HARD so that users
+    querying an address will see it appear in the cache (DHCP could
+    suffer from this when a server invalidly gave an in-use address.)
+  * ipv4/ip_addr.h: Renamed ip_addr_maskcmp() to _netcmp() as we are
+    comparing network addresses (identifiers), not the network masks
+    themselves.
+  * ipv4/ip_addr.c: ip_addr_isbroadcast() now checks that the given
+    IP address actually belongs to the network of the given interface.
+
+  2004-11-24 Kieran Mansley 
+  * tcp.c: Increment pcb->snd_buf when ACK is received in SYN_SENT state.
+
+(STABLE-1_1_0-RC1)
+
+  2004-10-16 Kieran Mansley 
+  * tcp.c: Add code to tcp_recved() to send an ACK (window update) immediately,
+	even if one is already pending, if the rcv_wnd is above a threshold
+	(currently TCP_WND/2). This avoids waiting for a timer to expire to send a
+	delayed ACK in order to open the window if the stack is only receiving data.
+
+  2004-09-12 Kieran Mansley 
+  * tcp*.*: Retransmit time-out handling improvement by Sam Jansen.
+
+  2004-08-20 Tony Mountifield 
+  * etharp.c: Make sure the first pbuf queued on an ARP entry
+    is properly ref counted.
+
+  2004-07-27 Tony Mountifield 
+  * debug.h: Added (int) cast in LWIP_DEBUGF() to avoid compiler
+    warnings about comparison.
+  * pbuf.c: Stopped compiler complaining of empty if statement
+    when LWIP_DEBUGF() empty.  Closed an unclosed comment.
+  * tcp.c: Stopped compiler complaining of empty if statement
+    when LWIP_DEBUGF() empty.
+  * ip.h Corrected IPH_TOS() macro: returns a byte, so doesn't need htons().
+  * inet.c: Added a couple of casts to quiet the compiler.
+    No need to test isascii(c) before isdigit(c) or isxdigit(c).
+
+  2004-07-22 Tony Mountifield 
+  * inet.c: Made data types consistent in inet_ntoa().
+    Added casts for return values of checksum routines, to pacify compiler.
+  * ip_frag.c, tcp_out.c, sockets.c, pbuf.c
+    Small corrections to some debugging statements, to pacify compiler.
+
+  2004-07-21 Tony Mountifield 
+  * etharp.c: Removed spurious semicolon and added missing end-of-comment.
+  * ethernetif.c Updated low_level_output() to match prototype for
+    netif->linkoutput and changed low_level_input() similarly for consistency.
+  * api_msg.c: Changed recv_raw() from int to u8_t, to match prototype
+    of raw_recv() in raw.h and so avoid compiler error.
+  * sockets.c: Added trivial (int) cast to keep compiler happier.
+  * ip.c, netif.c Changed debug statements to use the tidier ip4_addrN() macros.
+  
+(STABLE-1_0_0)
+
+  ++ Changes:
+
+  2004-07-05 Leon Woestenberg 
+  * sockets.*: Restructured LWIP_PRIVATE_TIMEVAL. Make sure
+    your cc.h file defines this either 1 or 0. If non-defined,
+    defaults to 1.
+  * .c: Added  and  includes where used.
+  * etharp.c: Made some array indices unsigned.
+
+  2004-06-27 Leon Woestenberg 
+  * netif.*: Added netif_set_up()/down().
+  * dhcp.c: Changes to restart program flow.
+
+  2004-05-07 Leon Woestenberg 
+  * etharp.c: In find_entry(), instead of a list traversal per candidate, do a
+    single-pass lookup for different candidates. Should exploit locality.
+
+  2004-04-29 Leon Woestenberg 
+  * tcp*.c: Cleaned up source comment documentation for Doxygen processing.
+  * opt.h: ETHARP_ALWAYS_INSERT option removed to comply with ARP RFC.
+  * etharp.c: update_arp_entry() only adds new ARP entries when adviced to by
+    the caller. This deprecates the ETHARP_ALWAYS_INSERT overrule option.
+
+  ++ Bug fixes:
+
+  2004-04-27 Leon Woestenberg 
+  * etharp.c: Applied patch of bug #8708 by Toni Mountifield with a solution
+    suggested by Timmy Brolin. Fix for 32-bit processors that cannot access
+    non-aligned 32-bit words, such as soms 32-bit TCP/IP header fields. Fix
+    is to prefix the 14-bit Ethernet headers with two padding bytes.
+
+  2004-04-23 Leon Woestenberg 
+  * ip_addr.c: Fix in the ip_addr_isbroadcast() check.
+  * etharp.c: Fixed the case where the packet that initiates the ARP request
+    is not queued, and gets lost. Fixed the case where the packets destination
+    address is already known; we now always queue the packet and perform an ARP
+    request.
+  
+(STABLE-0_7_0)
+
+  ++ Bug fixes:
+
+  * Fixed TCP bug for SYN_SENT to ESTABLISHED state transition.
+  * Fixed TCP bug in dequeueing of FIN from out of order segment queue.
+  * Fixed two possible NULL references in rare cases.
+
+(STABLE-0_6_6)
+
+  ++ Bug fixes:
+
+  * Fixed DHCP which did not include the IP address in DECLINE messages.
+
+  ++ Changes:
+
+  * etharp.c has been hauled over a bit.
+
+(STABLE-0_6_5)
+
+  ++ Bug fixes:
+
+  * Fixed TCP bug induced by bad window resizing with unidirectional TCP traffic.
+  * Packets sent from ARP queue had invalid source hardware address.
+
+  ++ Changes:
+
+  * Pass-by ARP requests do now update the cache.
+
+  ++ New features:
+
+  * No longer dependent on ctype.h.
+  * New socket options.
+  * Raw IP pcb support.
+
+(STABLE-0_6_4)
+
+  ++ Bug fixes:
+
+  * Some debug formatters and casts fixed.
+  * Numereous fixes in PPP.
+
+  ++ Changes:
+
+  * DEBUGF now is LWIP_DEBUGF
+  * pbuf_dechain() has been re-enabled.
+  * Mentioned the changed use of CVS branches in README.
+
+(STABLE-0_6_3)
+
+  ++ Bug fixes:
+
+  * Fixed pool pbuf memory leak in pbuf_alloc().
+    Occured if not enough PBUF_POOL pbufs for a packet pbuf chain.
+    Reported by Savin Zlobec.
+
+  * PBUF_POOL chains had their tot_len field not set for non-first
+    pbufs. Fixed in pbuf_alloc().
+
+  ++ New features:
+
+  * Added PPP stack contributed by Marc Boucher
+
+  ++ Changes:
+
+  * Now drops short packets for ICMP/UDP/TCP protocols. More robust.
+
+  * ARP queueuing now queues the latest packet instead of the first.
+    This is the RFC recommended behaviour, but can be overridden in
+    lwipopts.h.
+
+(0.6.2)
+
+  ++ Bugfixes:
+
+  * TCP has been fixed to deal with the new use of the pbuf->ref
+    counter.
+
+  * DHCP dhcp_inform() crash bug fixed.
+
+  ++ Changes:
+
+  * Removed pbuf_pool_free_cache and pbuf_pool_alloc_cache. Also removed
+    pbuf_refresh(). This has sped up pbuf pool operations considerably.
+    Implemented by David Haas.
+
+(0.6.1)
+
+  ++ New features:
+
+  * The packet buffer implementation has been enhanced to support
+    zero-copy and copy-on-demand for packet buffers which have their
+    payloads in application-managed memory.
+    Implemented by David Haas.
+
+    Use PBUF_REF to make a pbuf refer to RAM. lwIP will use zero-copy
+    if an outgoing packet can be directly sent on the link, or perform
+    a copy-on-demand when necessary.
+
+    The application can safely assume the packet is sent, and the RAM
+    is available to the application directly after calling udp_send()
+    or similar function.
+
+  ++ Bugfixes:
+
+  * ARP_QUEUEING should now correctly work for all cases, including
+    PBUF_REF.
+    Implemented by Leon Woestenberg.
+
+  ++ Changes:
+
+  * IP_ADDR_ANY is no longer a NULL pointer. Instead, it is a pointer
+    to a '0.0.0.0' IP address.
+
+  * The packet buffer implementation is changed. The pbuf->ref counter
+    meaning has changed, and several pbuf functions have been
+    adapted accordingly.
+
+  * netif drivers have to be changed to set the hardware address length field
+    that must be initialized correctly by the driver (hint: 6 for Ethernet MAC).
+    See the contrib/ports/c16x cs8900 driver as a driver example.
+
+  * netif's have a dhcp field that must be initialized to NULL by the driver.
+    See the contrib/ports/c16x cs8900 driver as a driver example.
+
+(0.5.x) This file has been unmaintained up to 0.6.1. All changes are
+  logged in CVS but have not been explained here.
+
+(0.5.3) Changes since version 0.5.2
+
+  ++ Bugfixes:
+
+  * memp_malloc(MEMP_API_MSG) could fail with multiple application
+    threads because it wasn't protected by semaphores.
+
+  ++ Other changes:
+
+  * struct ip_addr now packed.
+
+  * The name of the time variable in arp.c has been changed to ctime
+    to avoid conflicts with the time() function.
+
+(0.5.2) Changes since version 0.5.1
+
+  ++ New features:
+
+  * A new TCP function, tcp_tmr(), now handles both TCP timers.
+
+  ++ Bugfixes:
+
+  * A bug in tcp_parseopt() could cause the stack to hang because of a
+    malformed TCP option.
+
+  * The address of new connections in the accept() function in the BSD
+    socket library was not handled correctly.
+
+  * pbuf_dechain() did not update the ->tot_len field of the tail.
+
+  * Aborted TCP connections were not handled correctly in all
+    situations.
+
+  ++ Other changes:
+
+  * All protocol header structs are now packed.
+
+  * The ->len field in the tcp_seg structure now counts the actual
+    amount of data, and does not add one for SYN and FIN segments.
+
+(0.5.1) Changes since version 0.5.0
+
+  ++ New features:
+
+  * Possible to run as a user process under Linux.
+
+  * Preliminary support for cross platform packed structs.
+
+  * ARP timer now implemented.
+
+  ++ Bugfixes:
+
+  * TCP output queue length was badly initialized when opening
+    connections.
+
+  * TCP delayed ACKs were not sent correctly.
+
+  * Explicit initialization of BSS segment variables.
+
+  * read() in BSD socket library could drop data.
+
+  * Problems with memory alignment.
+
+  * Situations when all TCP buffers were used could lead to
+    starvation.
+
+  * TCP MSS option wasn't parsed correctly.
+
+  * Problems with UDP checksum calculation.
+
+  * IP multicast address tests had endianess problems.
+
+  * ARP requests had wrong destination hardware address.
+
+  ++ Other changes:
+
+  * struct eth_addr changed from u16_t[3] array to u8_t[6].
+
+  * A ->linkoutput() member was added to struct netif.
+
+  * TCP and UDP ->dest_* struct members where changed to ->remote_*.
+
+  * ntoh* macros are now null definitions for big endian CPUs.
+
+(0.5.0) Changes since version 0.4.2
+
+  ++ New features:
+
+  * Redesigned operating system emulation layer to make porting easier.
+
+  * Better control over TCP output buffers.
+
+  * Documenation added.
+
+  ++ Bugfixes:
+
+  * Locking issues in buffer management.
+
+  * Bugfixes in the sequential API.
+
+  * IP forwarding could cause memory leakage. This has been fixed.
+
+  ++ Other changes:
+
+  * Directory structure somewhat changed; the core/ tree has been
+    collapsed.
+
+(0.4.2) Changes since version 0.4.1
+
+  ++ New features:
+
+  * Experimental ARP implementation added.
+
+  * Skeleton Ethernet driver added.
+
+  * Experimental BSD socket API library added.
+
+  ++ Bugfixes:
+
+  * In very intense situations, memory leakage could occur. This has
+    been fixed.
+
+  ++ Other changes:
+
+  * Variables named "data" and "code" have been renamed in order to
+    avoid name conflicts in certain compilers.
+
+  * Variable++ have in appliciable cases been translated to ++variable
+    since some compilers generate better code in the latter case.
+
+(0.4.1) Changes since version 0.4
+
+  ++ New features:
+
+  * TCP: Connection attempts time out earlier than data
+    transmissions. Nagle algorithm implemented. Push flag set on the
+    last segment in a burst.
+
+  * UDP: experimental support for UDP-Lite extensions.
+
+  ++ Bugfixes:
+
+  * TCP: out of order segments were in some cases handled incorrectly,
+    and this has now been fixed. Delayed acknowledgements was broken
+    in 0.4, has now been fixed. Binding to an address that is in use
+    now results in an error. Reset connections sometimes hung an
+    application; this has been fixed.
+
+  * Checksum calculation sometimes failed for chained pbufs with odd
+    lengths. This has been fixed.
+
+  * API: a lot of bug fixes in the API. The UDP API has been improved
+    and tested. Error reporting and handling has been
+    improved. Logical flaws and race conditions for incoming TCP
+    connections has been found and removed.
+
+  * Memory manager: alignment issues. Reallocating memory sometimes
+    failed, this has been fixed.
+
+  * Generic library: bcopy was flawed and has been fixed.
+
+  ++ Other changes:
+
+  * API: all datatypes has been changed from generic ones such as
+    ints, to specified ones such as u16_t. Functions that return
+    errors now have the correct type (err_t).
+
+  * General: A lot of code cleaned up and debugging code removed. Many
+    portability issues have been fixed.
+
+  * The license was changed; the advertising clause was removed.
+
+  * C64 port added.
+
+  * Thanks: Huge thanks go to Dagan Galarneau, Horst Garnetzke, Petri
+    Kosunen, Mikael Caleres, and Frits Wilmink for reporting and
+    fixing bugs!
+
+(0.4) Changes since version 0.3.1
+
+  * Memory management has been radically changed; instead of
+    allocating memory from a shared heap, memory for objects that are
+    rapidly allocated and deallocated is now kept in pools. Allocation
+    and deallocation from those memory pools is very fast. The shared
+    heap is still present but is used less frequently.
+
+  * The memory, memory pool, and packet buffer subsystems now support
+    4-, 2-, or 1-byte alignment.
+
+  * "Out of memory" situations are handled in a more robust way.
+
+  * Stack usage has been reduced.
+
+  * Easier configuration of lwIP parameters such as memory usage,
+    TTLs, statistics gathering, etc. All configuration parameters are
+    now kept in a single header file "lwipopts.h".
+
+  * The directory structure has been changed slightly so that all
+    architecture specific files are kept under the src/arch
+    hierarchy.
+
+  * Error propagation has been improved, both in the protocol modules
+    and in the API.
+
+  * The code for the RTXC architecture has been implemented, tested
+    and put to use.
+
+  * Bugs have been found and corrected in the TCP, UDP, IP, API, and
+    the Internet checksum modules.
+
+  * Bugs related to porting between a 32-bit and a 16-bit architecture
+    have been found and corrected.
+
+  * The license has been changed slightly to conform more with the
+    original BSD license, including the advertisement clause.
+
+(0.3.1) Changes since version 0.3
+
+  * Fix of a fatal bug in the buffer management. Pbufs with allocated
+    RAM never returned the RAM when the pbuf was deallocated.
+
+  * TCP congestion control, window updates and retransmissions did not
+    work correctly. This has now been fixed.
+
+  * Bugfixes in the API.
+
+(0.3) Changes since version 0.2
+
+  * New and improved directory structure. All include files are now
+    kept in a dedicated include/ directory.
+
+  * The API now has proper error handling. A new function,
+    netconn_err(), now returns an error code for the connection in
+    case of errors.
+
+  * Improvements in the memory management subsystem. The system now
+    keeps a pointer to the lowest free memory block. A new function,
+    mem_malloc2() tries to allocate memory once, and if it fails tries
+    to free some memory and retry the allocation.
+
+  * Much testing has been done with limited memory
+    configurations. lwIP now does a better job when overloaded.
+
+  * Some bugfixes and improvements to the buffer (pbuf) subsystem.
+
+  * Many bugfixes in the TCP code:
+
+    - Fixed a bug in tcp_close().
+
+    - The TCP receive window was incorrectly closed when out of
+      sequence segments was received. This has been fixed.
+
+    - Connections are now timed-out of the FIN-WAIT-2 state.
+
+    - The initial congestion window could in some cases be too
+      large. This has been fixed.
+
+    - The retransmission queue could in some cases be screwed up. This
+      has been fixed.
+
+    - TCP RST flag now handled correctly.
+
+    - Out of sequence data was in some cases never delivered to the
+      application. This has been fixed.
+
+    - Retransmitted segments now contain the correct acknowledgment
+      number and advertised window.
+
+    - TCP retransmission timeout backoffs are not correctly computed
+      (ala BSD). After a number of retransmissions, TCP now gives up
+      the connection.
+
+  * TCP connections now are kept on three lists, one for active
+    connections, one for listening connections, and one for
+    connections that are in TIME-WAIT. This greatly speeds up the fast
+    timeout processing for sending delayed ACKs.
+
+  * TCP now provides proper feedback to the application when a
+    connection has been successfully set up.
+
+  * More comments have been added to the code. The code has also been
+    somewhat cleaned up.
+
+(0.2) Initial public release.
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/COPYING b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/COPYING
new file mode 100644
index 000000000..e23898b5e
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/COPYING
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2001, 2002 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/FILES b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/FILES
new file mode 100644
index 000000000..66253196f
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/FILES
@@ -0,0 +1,4 @@
+src/      - The source code for the lwIP TCP/IP stack.
+doc/      - The documentation for lwIP.
+
+See also the FILES file in each subdirectory.
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/README b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/README
new file mode 100644
index 000000000..4795d3afe
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/README
@@ -0,0 +1,92 @@
+INTRODUCTION
+
+lwIP is a small independent implementation of the TCP/IP protocol
+suite that has been developed by Adam Dunkels at the Computer and
+Networks Architectures (CNA) lab at the Swedish Institute of Computer
+Science (SICS).
+
+The focus of the lwIP TCP/IP implementation is to reduce the RAM usage
+while still having a full scale TCP. This making lwIP suitable for use
+in embedded systems with tenths of kilobytes of free RAM and room for
+around 40 kilobytes of code ROM.
+
+FEATURES
+
+ * IP (Internet Protocol) including packet forwarding over multiple
+   network interfaces
+ * ICMP (Internet Control Message Protocol) for network maintenance
+   and debugging
+ * UDP (User Datagram Protocol) including experimental UDP-lite
+   extensions
+ * TCP (Transmission Control Protocol) with congestion control, RTT
+   estimation and fast recovery/fast retransmit
+ * Specialized API for enhanced performance
+ * Optional Berkeley socket API
+
+LICENSE
+
+lwIP is freely available under a BSD license.
+
+DEVELOPMENT
+
+lwIP has grown into an excellent TCP/IP stack for embedded devices,
+and developers using the stack often submit bug fixes, improvements,
+and additions to the stack to further increase its usefulness.
+
+Development of lwIP is hosted on Savannah, a central point for
+software development, maintenance and distribution. Everyone can
+help improve lwIP by use of Savannah's interface, CVS and the
+mailing list. A core team of developers will commit changes to the
+CVS source tree.
+
+The lwIP TCP/IP stack is maintained in the 'lwip' CVS module and
+contributions (such as platform ports) are in the 'contrib' module.
+
+The CVS main trunk is the stable branch, which contains bug fixes and
+tested features. The latest stable branch can be checked out by doing:
+  cvs -d:pserver:anoncvs@subversions.gnu.org:/cvsroot/lwip login
+  cvs -z3 -d:pserver:anoncvs@subversions.gnu.org:/cvsroot/lwip co lwip
+
+The 'STABLE' tag in the stable branch will represent the most stable
+revision (which may be somewhat older to protect us from errors
+introduced by merges). This 'STABLE' tagged version can be checked out
+by doing:
+  cvs -d:pserver:anoncvs@subversions.gnu.org:/cvsroot/lwip login
+  cvs -z3 -d:pserver:anoncvs@subversions.gnu.org:/cvsroot/lwip co -r STABLE lwip
+
+The 'DEVEL' branch is the active development branch, which contains
+bleeding edge changes, and may be instable. It can be checkout by doing:
+  cvs -d:pserver:anoncvs@subversions.gnu.org:/cvsroot/lwip login
+  cvs -z3 -d:pserver:anoncvs@subversions.gnu.org:/cvsroot/lwip co -r DEVEL lwip
+
+The current contrib CVS tree can be checked out by doing:
+  cvs -d:pserver:anoncvs@subversions.gnu.org:/cvsroot/lwip login
+  cvs -z3 -d:pserver:anoncvs@subversions.gnu.org:/cvsroot/lwip co contrib
+
+Last night's CVS tar ball can be downloaded from:
+  http://savannah.gnu.org/cvs.backups/lwip.tar.gz
+
+The current CVS trees are web-browsable:
+  http://savannah.nongnu.org/cgi-bin/viewcvs/lwip/lwip/
+  http://savannah.nongnu.org/cgi-bin/viewcvs/lwip/contrib/
+
+Submit patches and bugs via the lwIP project page:
+  http://savannah.nongnu.org/projects/lwip/
+
+
+DOCUMENTATION
+
+The original out-dated homepage of lwIP and Adam Dunkels' papers on
+lwIP are at the official lwIP home page:
+  http://www.sics.se/~adam/lwip/
+
+Self documentation of the source code is regularly extracted from the
+current CVS sources and is available from this web page:
+  http://www.nongnu.org/lwip/
+
+Reading Adam's papers, the files in docs/, browsing the source code
+documentation and browsing the mailing list archives is a good way to
+become familiar with the design of lwIP.
+
+Adam Dunkels 
+Leon Woestenberg 		    
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/cc.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/cc.h
new file mode 100644
index 000000000..cbb300a12
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/cc.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __CC_H__
+#define __CC_H__
+
+#include "cpu.h"
+
+typedef unsigned   char    u8_t;
+typedef signed     char    s8_t;
+typedef unsigned   short   u16_t;
+typedef signed     short   s16_t;
+typedef unsigned   long    u32_t;
+typedef signed     long    s32_t;
+typedef u32_t mem_ptr_t;
+typedef int sys_prot_t;
+
+
+#define PACK_STRUCT_BEGIN
+#define PACK_STRUCT_STRUCT __attribute__ ((__packed__))
+#define PACK_STRUCT_END
+#define PACK_STRUCT_FIELD(x) x
+
+#endif /* __CC_H__ */
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/cpu.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/cpu.h
new file mode 100644
index 000000000..2af31a864
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/cpu.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __CPU_H__
+#define __CPU_H__
+
+#define BYTE_ORDER LITTLE_ENDIAN
+
+#endif /* __CPU_H__ */
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/init.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/init.h
new file mode 100644
index 000000000..14b95158b
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/init.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __ARCH_INIT_H__
+#define __ARCH_INIT_H__
+
+#define TCPIP_INIT_DONE(arg)  tcpip_init_done(arg)
+
+void tcpip_init_done(void *);
+int wait_for_tcpip_init(void);
+
+#endif /* __ARCH_INIT_H__ */
+
+
+
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/lib.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/lib.h
new file mode 100644
index 000000000..9726dee12
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/lib.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LIB_H__
+#define __LIB_H__
+
+#include 
+
+
+#endif /* __LIB_H__ */
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/perf.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/perf.h
new file mode 100644
index 000000000..68afdb56f
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/perf.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __PERF_H__
+#define __PERF_H__
+
+#define PERF_START    /* null definition */
+#define PERF_STOP(x)  /* null definition */
+
+#endif /* __PERF_H__ */
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/sys_arch.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/sys_arch.h
new file mode 100644
index 000000000..406f1f641
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/sys_arch.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __SYS_RTXC_H__
+#define __SYS_RTXC_H__
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "semphr.h"
+
+#define SYS_MBOX_NULL (xQueueHandle)0
+#define SYS_SEM_NULL  (xSemaphoreHandle)0
+
+typedef xSemaphoreHandle sys_sem_t;
+typedef xQueueHandle sys_mbox_t;
+typedef xTaskHandle sys_thread_t;
+
+#endif /* __SYS_RTXC_H__ */
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/sys_arch.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/sys_arch.c
new file mode 100644
index 000000000..a48fa78f9
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/sys_arch.c
@@ -0,0 +1,385 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+/* lwIP includes. */
+#include "lwip/debug.h"
+#include "lwip/def.h"
+#include "lwip/sys.h"
+#include "lwip/mem.h"
+
+/* Message queue constants. */
+#define archMESG_QUEUE_LENGTH	( 6 )
+#define archPOST_BLOCK_TIME_MS	( ( unsigned portLONG ) 10000 )
+
+struct timeoutlist 
+{
+	struct sys_timeouts timeouts;
+	xTaskHandle pid;
+};
+
+/* This is the number of threads that can be started with sys_thread_new() */
+#define SYS_THREAD_MAX 4
+
+#define lwipTCP_STACK_SIZE			600
+#define lwipBASIC_SERVER_STACK_SIZE	250
+
+static struct timeoutlist timeoutlist[SYS_THREAD_MAX];
+static u16_t nextthread = 0;
+int intlevel = 0;
+
+
+/*-----------------------------------------------------------------------------------*/
+//  Creates an empty mailbox.
+sys_mbox_t
+sys_mbox_new(void)
+{
+	xQueueHandle mbox;
+
+	mbox = xQueueCreate( archMESG_QUEUE_LENGTH, sizeof( void * ) );
+
+	return mbox;
+}
+
+/*-----------------------------------------------------------------------------------*/
+/*
+  Deallocates a mailbox. If there are messages still present in the
+  mailbox when the mailbox is deallocated, it is an indication of a
+  programming error in lwIP and the developer should be notified.
+*/
+void
+sys_mbox_free(sys_mbox_t mbox)
+{
+	if( uxQueueMessagesWaiting( mbox ) )
+	{
+		/* Line for breakpoint.  Should never break here! */
+		__asm volatile ( "NOP" );
+	}
+
+	vQueueDelete( mbox ); 
+}
+
+/*-----------------------------------------------------------------------------------*/
+//   Posts the "msg" to the mailbox.
+void
+sys_mbox_post(sys_mbox_t mbox, void *data)
+{   
+	xQueueSend( mbox, &data, ( portTickType ) ( archPOST_BLOCK_TIME_MS / portTICK_RATE_MS ) );
+}
+
+
+/*-----------------------------------------------------------------------------------*/
+/*
+  Blocks the thread until a message arrives in the mailbox, but does
+  not block the thread longer than "timeout" milliseconds (similar to
+  the sys_arch_sem_wait() function). The "msg" argument is a result
+  parameter that is set by the function (i.e., by doing "*msg =
+  ptr"). The "msg" parameter maybe NULL to indicate that the message
+  should be dropped.
+
+  The return values are the same as for the sys_arch_sem_wait() function:
+  Number of milliseconds spent waiting or SYS_ARCH_TIMEOUT if there was a
+  timeout.
+
+  Note that a function with a similar name, sys_mbox_fetch(), is
+  implemented by lwIP. 
+*/
+u32_t sys_arch_mbox_fetch(sys_mbox_t mbox, void **msg, u32_t timeout)
+{
+void *dummyptr;
+portTickType StartTime, EndTime, Elapsed;
+
+	StartTime = xTaskGetTickCount();
+
+	if( msg == NULL )
+	{
+		msg = &dummyptr;
+	}
+		
+	if(	timeout != 0 )
+	{
+		if(pdTRUE == xQueueReceive( mbox, &(*msg), timeout ) )
+		{
+			EndTime = xTaskGetTickCount();
+			Elapsed = EndTime - StartTime;
+			if( Elapsed == 0 )
+			{
+				Elapsed = 1;
+			}
+			return ( Elapsed );
+		}
+		else // timed out blocking for message
+		{
+			*msg = NULL;
+			return SYS_ARCH_TIMEOUT;
+		}
+	}
+	else // block forever for a message.
+	{
+		while( pdTRUE != xQueueReceive( mbox, &(*msg), 10000 ) ) // time is arbitrary
+		{
+			;
+		}
+		EndTime = xTaskGetTickCount();
+		Elapsed = EndTime - StartTime;
+		if( Elapsed == 0 )
+		{
+			Elapsed = 1;
+		}
+		return ( Elapsed ); // return time blocked TBD test	
+	}
+}
+
+/*-----------------------------------------------------------------------------------*/
+//  Creates and returns a new semaphore. The "count" argument specifies
+//  the initial state of the semaphore. TBD finish and test
+sys_sem_t
+sys_sem_new(u8_t count)
+{
+	xSemaphoreHandle  xSemaphore;
+
+	portENTER_CRITICAL();
+	vSemaphoreCreateBinary( xSemaphore );
+	if(count == 0)	// Means it can't be taken
+	{
+		xSemaphoreTake(xSemaphore,1);
+	}
+	portEXIT_CRITICAL();
+
+	if( xSemaphore == NULL )
+	{
+		return NULL;	// TBD need assert
+	}
+	else
+	{
+		return xSemaphore;
+	}
+}
+
+/*-----------------------------------------------------------------------------------*/
+/*
+  Blocks the thread while waiting for the semaphore to be
+  signaled. If the "timeout" argument is non-zero, the thread should
+  only be blocked for the specified time (measured in
+  milliseconds).
+
+  If the timeout argument is non-zero, the return value is the number of
+  milliseconds spent waiting for the semaphore to be signaled. If the
+  semaphore wasn't signaled within the specified time, the return value is
+  SYS_ARCH_TIMEOUT. If the thread didn't have to wait for the semaphore
+  (i.e., it was already signaled), the function may return zero.
+
+  Notice that lwIP implements a function with a similar name,
+  sys_sem_wait(), that uses the sys_arch_sem_wait() function.
+*/
+u32_t
+sys_arch_sem_wait(sys_sem_t sem, u32_t timeout)
+{
+portTickType StartTime, EndTime, Elapsed;
+
+	StartTime = xTaskGetTickCount();
+
+	if(	timeout != 0)
+	{
+		if( xSemaphoreTake( sem, timeout ) == pdTRUE )
+		{
+			EndTime = xTaskGetTickCount();
+			Elapsed = EndTime - StartTime;
+			if( Elapsed == 0 )
+			{
+				Elapsed = 1;
+			}
+			return (Elapsed); // return time blocked TBD test	
+		}
+		else
+		{
+			return SYS_ARCH_TIMEOUT;
+		}
+	}
+	else // must block without a timeout
+	{
+		while( xSemaphoreTake( sem, 10000 ) != pdTRUE )
+		{
+			;
+		}
+		EndTime = xTaskGetTickCount();
+		Elapsed = EndTime - StartTime;
+		if( Elapsed == 0 )
+		{
+			Elapsed = 1;
+		}
+
+		return ( Elapsed ); // return time blocked	
+		 
+	}
+}
+
+/*-----------------------------------------------------------------------------------*/
+// Signals a semaphore
+void
+sys_sem_signal(sys_sem_t sem)
+{
+	xSemaphoreGive( sem );
+}
+
+/*-----------------------------------------------------------------------------------*/
+// Deallocates a semaphore
+void
+sys_sem_free(sys_sem_t sem)
+{
+	vQueueDelete( sem ); 
+}
+
+/*-----------------------------------------------------------------------------------*/
+// Initialize sys arch
+void
+sys_init(void)
+{
+
+	int i;
+
+	// Initialize the the per-thread sys_timeouts structures
+	// make sure there are no valid pids in the list
+	for(i = 0; i < SYS_THREAD_MAX; i++)
+	{
+		timeoutlist[i].pid = 0;
+	}
+
+	// keep track of how many threads have been created
+	nextthread = 0;
+}
+
+/*-----------------------------------------------------------------------------------*/
+/*
+  Returns a pointer to the per-thread sys_timeouts structure. In lwIP,
+  each thread has a list of timeouts which is represented as a linked
+  list of sys_timeout structures. The sys_timeouts structure holds a
+  pointer to a linked list of timeouts. This function is called by
+  the lwIP timeout scheduler and must not return a NULL value. 
+
+  In a single threaded sys_arch implementation, this function will
+  simply return a pointer to a global sys_timeouts variable stored in
+  the sys_arch module.
+*/
+struct sys_timeouts *
+sys_arch_timeouts(void)
+{
+int i;
+xTaskHandle pid;
+struct timeoutlist *tl;  
+
+	pid = xTaskGetCurrentTaskHandle( ); 
+
+	for(i = 0; i < nextthread; i++) 
+	{
+		tl = &timeoutlist[i];
+		if(tl->pid == pid) 
+		{
+			return &(tl->timeouts);
+		}
+	}
+
+	// Error
+	return NULL;
+}
+
+/*-----------------------------------------------------------------------------------*/
+/*-----------------------------------------------------------------------------------*/
+// TBD 
+/*-----------------------------------------------------------------------------------*/
+/*
+  Starts a new thread with priority "prio" that will begin its execution in the
+  function "thread()". The "arg" argument will be passed as an argument to the
+  thread() function. The id of the new thread is returned. Both the id and
+  the priority are system dependent.
+*/
+sys_thread_t sys_thread_new(void (* thread)(void *arg), void *arg, int prio)
+{
+xTaskHandle CreatedTask;
+int result;
+static int iCall = 0;
+
+	if( iCall == 0 )
+	{
+		/* The first time this is called we are creating the lwIP handler. */
+		result = xTaskCreate( thread, ( signed portCHAR * ) "lwIP", lwipTCP_STACK_SIZE, arg, prio, &CreatedTask );
+		iCall++;
+	}
+	else
+	{
+		result = xTaskCreate( thread, ( signed portCHAR * ) "WEBSvr", lwipBASIC_SERVER_STACK_SIZE, arg, prio, &CreatedTask );
+	}
+
+	// For each task created, store the task handle (pid) in the timers array.
+	// This scheme doesn't allow for threads to be deleted
+	timeoutlist[nextthread++].pid = CreatedTask;
+
+	if(result == pdPASS)
+	{
+		return CreatedTask;
+	}
+	else
+	{
+		return NULL;
+	}
+}
+
+/*
+  This optional function does a "fast" critical region protection and returns
+  the previous protection level. This function is only called during very short
+  critical regions. An embedded system which supports ISR-based drivers might
+  want to implement this function by disabling interrupts. Task-based systems
+  might want to implement this by using a mutex or disabling tasking. This
+  function should support recursive calls from the same task or interrupt. In
+  other words, sys_arch_protect() could be called while already protected. In
+  that case the return value indicates that it is already protected.
+
+  sys_arch_protect() is only required if your port is supporting an operating
+  system.
+*/
+sys_prot_t sys_arch_protect(void)
+{
+	vPortEnterCritical();
+	return 1;
+}
+
+/*
+  This optional function does a "fast" set of critical region protection to the
+  value specified by pval. See the documentation for sys_arch_protect() for
+  more information. This function is only required if your port is supporting
+  an operating system.
+*/
+void sys_arch_unprotect(sys_prot_t pval)
+{ 
+	( void ) pval;
+	vPortExitCritical();
+}
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/doc/contrib.txt b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/doc/contrib.txt
new file mode 100644
index 000000000..7c99b9be2
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/doc/contrib.txt
@@ -0,0 +1,62 @@
+1 Introduction
+
+This document describes some guidelines for people participating
+in lwIP development.
+
+2 How to contribute to lwIP
+
+Here is a short list of suggestions to anybody working with lwIP and 
+trying to contribute bug reports, fixes, enhancements, platform ports etc.
+First of all as you may already know lwIP is a volunteer project so feedback
+to fixes or questions might often come late. Hopefully the bug and patch tracking 
+features of Savannah help us not lose users' input.
+
+2.1 Source code style:
+
+1. do not use tabs.
+2. indentation is two spaces per level (i.e. per tab).
+3. end debug messages with a trailing newline (\n).
+4. one space between keyword and opening bracket.
+5. no space between function and opening bracket.
+6. one space and no newline before opening curly braces of a block.
+7. closing curly brace on a single line.
+8. spaces surrounding assignment and comparisons.
+9. use current source code style as further reference.
+
+2.2 Source code documentation style:
+
+1. JavaDoc compliant and Doxygen compatible.
+2. Function documentation above functions in .c files, not .h files.
+   (This forces you to synchronize documentation and implementation.)
+3. Use current documentation style as further reference.
+ 
+2.3 Bug reports and patches:
+
+1. Make sure you are reporting bugs or send patches against the latest
+   sources. (From the latest release and/or the current CVS sources.)
+2. If you think you found a bug make sure it's not already filed in the
+   bugtracker at Savannah.
+3. If you have a fix put the patch on Savannah. If it is a patch that affects
+   both core and arch specific stuff please separate them so that the core can
+   be applied separately while leaving the other patch 'open'. The prefered way
+   is to NOT touch archs you can't test and let maintainers take care of them.
+   This is a good way to see if they are used at all - the same goes for unix
+   netifs except tapif.
+4. Do not file a bug and post a fix to it to the patch area. Either a bug report
+   or a patch will be enough.
+   If you correct an existing bug then attach the patch to the bug rather than creating a new entry in the patch area.
+5. Trivial patches (compiler warning, indentation and spelling fixes or anything obvious which takes a line or two)
+   can go to the lwip-users list. This is still the fastest way of interaction and the list is not so crowded
+   as to allow for loss of fixes. Putting bugs on Savannah and subsequently closing them is too much an overhead
+   for reporting a compiler warning fix.
+6. Patches should be specific to a single change or to related changes.Do not mix bugfixes with spelling and other
+   trivial fixes unless the bugfix is trivial too.Do not reorganize code and rename identifiers in the same patch you
+   change behaviour if not necessary.A patch is easier to read and understand if it's to the point and short than
+   if it's not to the point and long :) so the chances for it to be applied are greater. 
+
+2.4 Platform porters:
+
+1. If you have ported lwIP to a platform (an OS, a uC/processor or a combination of these) and
+   you think it could benefit others[1] you might want discuss this on the mailing list. You
+   can also ask for CVS access to submit and maintain your port in the contrib CVS module.
+   
\ No newline at end of file
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/doc/rawapi.txt b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/doc/rawapi.txt
new file mode 100644
index 000000000..6d1c93cab
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/doc/rawapi.txt
@@ -0,0 +1,292 @@
+Raw TCP/IP interface for lwIP
+
+Authors: Adam Dunkels, Leon Woestenberg
+
+lwIP provides two Application Program's Interfaces (APIs) for programs
+to use for communication with the TCP/IP code:
+* low-level "core" / "callback" or "raw" API.
+* higher-level "sequential" API.
+
+The sequential API provides a way for ordinary, sequential, programs
+to use the lwIP stack. It is quite similar to the BSD socket API. The
+model of execution is based on the blocking open-read-write-close
+paradigm. Since the TCP/IP stack is event based by nature, the TCP/IP
+code and the application program must reside in different execution
+contexts (threads).
+
+** The remainder of this document discusses the "raw" API. **
+
+The raw TCP/IP interface allows the application program to integrate
+better with the TCP/IP code. Program execution is event based by
+having callback functions being called from within the TCP/IP
+code. The TCP/IP code and the application program both run in the same
+thread. The sequential API has a much higher overhead and is not very
+well suited for small systems since it forces a multithreaded paradigm
+on the application.
+
+The raw TCP/IP interface is not only faster in terms of code execution
+time but is also less memory intensive. The drawback is that program
+development is somewhat harder and application programs written for
+the raw TCP/IP interface are more difficult to understand. Still, this
+is the preferred way of writing applications that should be small in
+code size and memory usage.
+
+Both APIs can be used simultaneously by different application
+programs. In fact, the sequential API is implemented as an application
+program using the raw TCP/IP interface.
+
+--- Callbacks
+
+Program execution is driven by callbacks. Each callback is an ordinary
+C function that is called from within the TCP/IP code. Every callback
+function is passed the current TCP or UDP connection state as an
+argument. Also, in order to be able to keep program specific state,
+the callback functions are called with a program specified argument
+that is independent of the TCP/IP state.
+
+The function for setting the application connection state is:
+
+- void tcp_arg(struct tcp_pcb *pcb, void *arg)
+
+  Specifies the program specific state that should be passed to all
+  other callback functions. The "pcb" argument is the current TCP
+  connection control block, and the "arg" argument is the argument
+  that will be passed to the callbacks.
+
+  
+--- TCP connection setup
+
+The functions used for setting up connections is similar to that of
+the sequential API and of the BSD socket API. A new TCP connection
+identifier (i.e., a protocol control block - PCB) is created with the
+tcp_new() function. This PCB can then be either set to listen for new
+incoming connections or be explicitly connected to another host.
+
+- struct tcp_pcb *tcp_new(void)
+
+  Creates a new connection identifier (PCB). If memory is not
+  available for creating the new pcb, NULL is returned.
+
+- err_t tcp_bind(struct tcp_pcb *pcb, struct ip_addr *ipaddr,
+                 u16_t port)
+
+  Binds the pcb to a local IP address and port number. The IP address
+  can be specified as IP_ADDR_ANY in order to bind the connection to
+  all local IP addresses.
+
+  If another connection is bound to the same port, the function will
+  return ERR_USE, otherwise ERR_OK is returned.
+
+- struct tcp_pcb *tcp_listen(struct tcp_pcb *pcb)
+
+  Commands a pcb to start listening for incoming connections. When an
+  incoming connection is accepted, the function specified with the
+  tcp_accept() function will be called. The pcb will have to be bound
+  to a local port with the tcp_bind() function.
+
+  The tcp_listen() function returns a new connection identifier, and
+  the one passed as an argument to the function will be
+  deallocated. The reason for this behavior is that less memory is
+  needed for a connection that is listening, so tcp_listen() will
+  reclaim the memory needed for the original connection and allocate a
+  new smaller memory block for the listening connection.
+
+  tcp_listen() may return NULL if no memory was available for the
+  listening connection. If so, the memory associated with the pcb
+  passed as an argument to tcp_listen() will not be deallocated.
+
+- void tcp_accept(struct tcp_pcb *pcb,
+                  err_t (* accept)(void *arg, struct tcp_pcb *newpcb,
+                                   err_t err))
+
+  Specified the callback function that should be called when a new
+  connection arrives on a listening connection.
+      
+- err_t tcp_connect(struct tcp_pcb *pcb, struct ip_addr *ipaddr,
+                    u16_t port, err_t (* connected)(void *arg,
+                                                    struct tcp_pcb *tpcb,
+                                                    err_t err));
+
+  Sets up the pcb to connect to the remote host and sends the
+  initial SYN segment which opens the connection. 
+
+  The tcp_connect() function returns immediately; it does not wait for
+  the connection to be properly setup. Instead, it will call the
+  function specified as the fourth argument (the "connected" argument)
+  when the connection is established. If the connection could not be
+  properly established, either because the other host refused the
+  connection or because the other host didn't answer, the "connected"
+  function will be called with an the "err" argument set accordingly.
+
+  The tcp_connect() function can return ERR_MEM if no memory is
+  available for enqueueing the SYN segment. If the SYN indeed was
+  enqueued successfully, the tcp_connect() function returns ERR_OK.
+
+  
+--- Sending TCP data
+
+TCP data is sent by enqueueing the data with a call to
+tcp_write(). When the data is successfully transmitted to the remote
+host, the application will be notified with a call to a specified
+callback function.
+
+- err_t tcp_write(struct tcp_pcb *pcb, void *dataptr, u16_t len,
+                  u8_t copy)
+
+  Enqueues the data pointed to by the argument dataptr. The length of
+  the data is passed as the len parameter. The copy argument is either
+  0 or 1 and indicates whether the new memory should be allocated for
+  the data to be copied into. If the argument is 0, no new memory
+  should be allocated and the data should only be referenced by
+  pointer.
+
+  The tcp_write() function will fail and return ERR_MEM if the length
+  of the data exceeds the current send buffer size or if the length of
+  the queue of outgoing segment is larger than the upper limit defined
+  in lwipopts.h. The number of bytes available in the output queue can
+  be retrieved with the tcp_sndbuf() function.
+
+  The proper way to use this function is to call the function with at
+  most tcp_sndbuf() bytes of data. If the function returns ERR_MEM,
+  the application should wait until some of the currently enqueued
+  data has been successfully received by the other host and try again.
+
+- void tcp_sent(struct tcp_pcb *pcb,
+                err_t (* sent)(void *arg, struct tcp_pcb *tpcb,
+		               u16_t len))
+
+  Specifies the callback function that should be called when data has
+  successfully been received (i.e., acknowledged) by the remote
+  host. The len argument passed to the callback function gives the
+  amount bytes that was acknowledged by the last acknowledgment.
+
+  
+--- Receiving TCP data
+
+TCP data reception is callback based - an application specified
+callback function is called when new data arrives. When the
+application has taken the data, it has to call the tcp_recved()
+function to indicate that TCP can advertise increase the receive
+window.
+
+- void tcp_recv(struct tcp_pcb *pcb,
+                err_t (* recv)(void *arg, struct tcp_pcb *tpcb,
+                               struct pbuf *p, err_t err))
+
+  Sets the callback function that will be called when new data
+  arrives. The callback function will be passed a NULL pbuf to
+  indicate that the remote host has closed the connection.
+
+- void tcp_recved(struct tcp_pcb *pcb, u16_t len)
+
+  Must be called when the application has received the data. The len
+  argument indicates the length of the received data.
+    
+
+--- Application polling
+
+When a connection is idle (i.e., no data is either transmitted or
+received), lwIP will repeatedly poll the application by calling a
+specified callback function. This can be used either as a watchdog
+timer for killing connections that have stayed idle for too long, or
+as a method of waiting for memory to become available. For instance,
+if a call to tcp_write() has failed because memory wasn't available,
+the application may use the polling functionality to call tcp_write()
+again when the connection has been idle for a while.
+
+- void tcp_poll(struct tcp_pcb *pcb, u8_t interval,
+                err_t (* poll)(void *arg, struct tcp_pcb *tpcb))
+
+  Specifies the polling interval and the callback function that should
+  be called to poll the application. The interval is specified in
+  number of TCP coarse grained timer shots, which typically occurs
+  twice a second. An interval of 10 means that the application would
+  be polled every 5 seconds.
+
+
+--- Closing and aborting connections
+
+- err_t tcp_close(struct tcp_pcb *pcb)
+
+  Closes the connection. The function may return ERR_MEM if no memory
+  was available for closing the connection. If so, the application
+  should wait and try again either by using the acknowledgment
+  callback or the polling functionality. If the close succeeds, the
+  function returns ERR_OK.
+
+  The pcb is deallocated by the TCP code after a call to tcp_close(). 
+
+- void tcp_abort(struct tcp_pcb *pcb)
+
+  Aborts the connection by sending a RST (reset) segment to the remote
+  host. The pcb is deallocated. This function never fails.
+
+If a connection is aborted because of an error, the application is
+alerted of this event by the err callback. Errors that might abort a
+connection are when there is a shortage of memory. The callback
+function to be called is set using the tcp_err() function.
+
+- void tcp_err(struct tcp_pcb *pcb, void (* err)(void *arg,
+	       err_t err))
+
+  The error callback function does not get the pcb passed to it as a
+  parameter since the pcb may already have been deallocated.
+
+
+--- Lower layer TCP interface
+
+TCP provides a simple interface to the lower layers of the
+system. During system initialization, the function tcp_init() has
+to be called before any other TCP function is called. When the system
+is running, the two timer functions tcp_fasttmr() and tcp_slowtmr()
+must be called with regular intervals. The tcp_fasttmr() should be
+called every TCP_FAST_INTERVAL milliseconds (defined in tcp.h) and
+tcp_slowtmr() should be called every TCP_SLOW_INTERVAL milliseconds. 
+
+
+--- UDP interface
+
+The UDP interface is similar to that of TCP, but due to the lower
+level of complexity of UDP, the interface is significantly simpler.
+
+- struct udp_pcb *udp_new(void)
+
+  Creates a new UDP pcb which can be used for UDP communication. The
+  pcb is not active until it has either been bound to a local address
+  or connected to a remote address.
+
+- void udp_remove(struct udp_pcb *pcb)
+
+  Removes and deallocates the pcb.  
+  
+- err_t udp_bind(struct udp_pcb *pcb, struct ip_addr *ipaddr,
+                 u16_t port)
+
+  Binds the pcb to a local address. The IP-address argument "ipaddr"
+  can be IP_ADDR_ANY to indicate that it should listen to any local IP
+  address. The function currently always return ERR_OK.
+
+- err_t udp_connect(struct udp_pcb *pcb, struct ip_addr *ipaddr,
+                    u16_t port)
+
+  Sets the remote end of the pcb. This function does not generate any
+  network traffic, but only set the remote address of the pcb.
+
+- err_t udp_disconnect(struct udp_pcb *pcb)
+
+  Remove the remote end of the pcb. This function does not generate
+  any network traffic, but only removes the remote address of the pcb.
+
+- err_t udp_send(struct udp_pcb *pcb, struct pbuf *p)
+
+  Sends the pbuf p. The pbuf is not deallocated.
+
+- void udp_recv(struct udp_pcb *pcb,
+                void (* recv)(void *arg, struct udp_pcb *upcb,
+                                         struct pbuf *p,
+                                         struct ip_addr *addr,
+                                         u16_t port),
+                              void *recv_arg)
+
+  Specifies a callback function that should be called when a UDP
+  datagram is received.
\ No newline at end of file
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/doc/savannah.txt b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/doc/savannah.txt
new file mode 100644
index 000000000..56cc1f190
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/doc/savannah.txt
@@ -0,0 +1,135 @@
+Daily Use Guide for using Savannah for lwIP
+
+Table of Contents:
+
+1 - Obtaining lwIP from the CVS repository
+2 - Committers/developers CVS access using SSH (to be written)
+3 - Merging from DEVEL branch to main trunk (stable branch)
+4 - How to release lwIP
+
+
+
+1 Obtaining lwIP from the CVS repository
+----------------------------------------
+
+To perform an anonymous CVS checkout of the main trunk (this is where
+bug fixes and incremental enhancements occur), do this:
+
+export CVS_RSH=ssh
+cvs -d:ext:anoncvs@subversions.gnu.org:/cvsroot/lwip checkout lwip
+
+(If SSH asks about authenticity of the host, you can check the key
+ fingerprint against http://savannah.nongnu.org/cvs/?group=lwip)
+
+Or, obtain a stable branch (updated with bug fixes only) as follows:
+cvs -d:ext:anoncvs@subversions.gnu.org:/cvsroot/lwip checkout -r STABLE-0_7 -d lwip-0.7 lwip
+
+Or, obtain a specific (fixed) release as follows:
+cvs -d:ext:anoncvs@subversions.gnu.org:/cvsroot/lwip checkout -r STABLE-0_7_0 -d lwip-0.7.0 lwip
+
+Or, obtain a development branch (considered unstable!) as follows:
+cvs -d:ext:anoncvs@subversions.gnu.org:/cvsroot/lwip checkout -r DEVEL -d lwip-DEVEL lwip
+
+3 Committers/developers CVS access using SSH
+--------------------------------------------
+
+The Savannah server uses SSH (Secure Shell) protocol 2 authentication and encryption.
+As such, CVS commits to the server occur through a SSH tunnel for project members.
+To create a SSH2 key pair in UNIX-like environments, do this:
+
+ssh-keygen -t dsa
+
+Under Windows, a recommended SSH client is "PuTTY", freely available with good
+documentation and a graphic user interface. Use its key generator.
+
+Now paste the id_dsa.pub contents into your Savannah account public key list. Wait
+a while so that Savannah can update its configuration (This can take minutes).
+
+Try to login using SSH:
+
+ssh -v your_login@subversions.gnu.org
+
+If it tells you:
+
+Authenticating with public key "your_key_name"...
+Server refused to allocate pty
+
+then you could login; Savannah refuses to give you a shell - which is OK, as we
+are allowed to use SSH for CVS only. Now, you should be able to do this:
+
+export CVS_RSH=ssh
+cvs -d:ext:your_login@subversions.gnu.org:/cvsroot/lwip checkout lwip
+
+after which you can edit your local files with bug fixes or new features and
+commit them. Make sure you know what you are doing when using CVS to make
+changes on the repository. If in doubt, ask on the lwip-members mailing list.
+
+3 Merging from DEVEL branch to main trunk (stable)
+--------------------------------------------------
+
+Merging is a delicate process in CVS and requires the
+following disciplined steps in order to prevent conflicts
+in the future. Conflicts can be hard to solve!
+
+Merging from branch A to branch B requires that the A branch
+has a tag indicating the previous merger. This tag is called
+'merged_from_A_to_B'. After merging, the tag is moved in the
+A branch to remember this merger for future merge actions.
+
+IMPORTANT: AFTER COMMITTING A SUCCESFUL MERGE IN THE
+REPOSITORY, THE TAG MUST BE SET ON THE SOURCE BRANCH OF THE
+MERGE ACTION (REPLACING EXISTING TAGS WITH THE SAME NAME).
+
+Merge all changes in DEVEL since our last merge to main:
+
+In the working copy of the main trunk:
+cvs update -P -jmerged_from_DEVEL_to_main -jDEVEL 
+
+(This will apply the changes between 'merged_from_DEVEL_to_main'
+and 'DEVEL' to your work set of files)
+
+We can now commit the merge result.
+cvs commit -R -m "Merged from DEVEL to main." 
+
+If this worked out OK, we now move the tag in the DEVEL branch
+to this merge point, so we can use this point for future merges:
+
+cvs rtag -F -r DEVEL merged_from_DEVEL_to_main lwip 
+
+4 How to release lwIP
+---------------------
+
+First, checkout a clean copy of the branch to be released. Tag this set with
+tag name "STABLE-0_6_3". (I use release number 0.6.3 throughout this example).
+
+Login CVS using pserver authentication, then export a clean copy of the
+tagged tree. Export is similar to a checkout, except that the CVS metadata
+is not created locally. 
+
+export CVS_RSH=ssh
+cvs -d:ext:anoncvs@subversions.gnu.org:/cvsroot/lwip export -r STABLE-0_6_3 -d lwip-0.6.3 lwip
+
+Archive this directory using tar, gzip'd, bzip2'd and zip'd.
+
+tar czvf lwip-0.6.3.tar.gz lwip-0.6.3
+tar cjvf lwip-0.6.3.tar.bz2 lwip-0.6.3
+zip -r lwip-0.6.3.zip lwip-0.6.3
+
+Now, sign the archives with a detached GPG binary signature as follows:
+
+gpg -b lwip-0.6.3.tar.gz
+gpg -b lwip-0.6.3.tar.bz2
+gpg -b lwip-0.6.3.zip
+
+Upload these files using anonymous FTP:
+ncftp ftp://savannah.gnu.org/incoming/savannah/lwip
+
+ncftp>mput *0.6.3.*
+
+Additionally, you may post a news item on Savannah, like this:
+
+A new 0.6.3 release is now available here:
+http://savannah.nongnu.org/files/?group=lwip&highlight=0.6.3
+
+You will have to submit this via the user News interface, then approve
+this via the Administrator News interface.
\ No newline at end of file
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/doc/sys_arch.txt b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/doc/sys_arch.txt
new file mode 100644
index 000000000..95d0add73
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/doc/sys_arch.txt
@@ -0,0 +1,194 @@
+sys_arch interface for lwIP 0.6++
+
+Author: Adam Dunkels
+
+The operating system emulation layer provides a common interface
+between the lwIP code and the underlying operating system kernel. The
+general idea is that porting lwIP to new architectures requires only
+small changes to a few header files and a new sys_arch
+implementation. It is also possible to do a sys_arch implementation
+that does not rely on any underlying operating system.
+
+The sys_arch provides semaphores and mailboxes to lwIP. For the full
+lwIP functionality, multiple threads support can be implemented in the
+sys_arch, but this is not required for the basic lwIP
+functionality. Previous versions of lwIP required the sys_arch to
+implement timer scheduling as well but as of lwIP 0.5 this is
+implemented in a higher layer.
+
+In addition to the source file providing the functionality of sys_arch,
+the OS emulation layer must provide several header files defining
+macros used throughout lwip.  The files required and the macros they
+must define are listed below the sys_arch description.
+
+Semaphores can be either counting or binary - lwIP works with both
+kinds. Mailboxes are used for message passing and can be implemented
+either as a queue which allows multiple messages to be posted to a
+mailbox, or as a rendez-vous point where only one message can be
+posted at a time. lwIP works with both kinds, but the former type will
+be more efficient. A message in a mailbox is just a pointer, nothing
+more. 
+
+Semaphores are represented by the type "sys_sem_t" which is typedef'd
+in the sys_arch.h file. Mailboxes are equivalently represented by the
+type "sys_mbox_t". lwIP does not place any restrictions on how
+sys_sem_t or sys_mbox_t are represented internally.
+
+The following functions must be implemented by the sys_arch:
+
+- void sys_init(void)
+
+  Is called to initialize the sys_arch layer.
+
+- sys_sem_t sys_sem_new(u8_t count)
+
+  Creates and returns a new semaphore. The "count" argument specifies
+  the initial state of the semaphore.
+
+- void sys_sem_free(sys_sem_t sem)
+
+  Deallocates a semaphore.
+
+- void sys_sem_signal(sys_sem_t sem)
+
+  Signals a semaphore.
+
+- u32_t sys_arch_sem_wait(sys_sem_t sem, u32_t timeout)
+
+  Blocks the thread while waiting for the semaphore to be
+  signaled. If the "timeout" argument is non-zero, the thread should
+  only be blocked for the specified time (measured in
+  milliseconds).
+
+  If the timeout argument is non-zero, the return value is the number of
+  milliseconds spent waiting for the semaphore to be signaled. If the
+  semaphore wasn't signaled within the specified time, the return value is
+  SYS_ARCH_TIMEOUT. If the thread didn't have to wait for the semaphore
+  (i.e., it was already signaled), the function may return zero.
+
+  Notice that lwIP implements a function with a similar name,
+  sys_sem_wait(), that uses the sys_arch_sem_wait() function.
+
+- sys_mbox_t sys_mbox_new(void)
+
+  Creates an empty mailbox.
+
+- void sys_mbox_free(sys_mbox_t mbox)
+
+  Deallocates a mailbox. If there are messages still present in the
+  mailbox when the mailbox is deallocated, it is an indication of a
+  programming error in lwIP and the developer should be notified.
+
+- void sys_mbox_post(sys_mbox_t mbox, void *msg)
+
+  Posts the "msg" to the mailbox.
+
+- u32_t sys_arch_mbox_fetch(sys_mbox_t mbox, void **msg, u32_t timeout)
+
+  Blocks the thread until a message arrives in the mailbox, but does
+  not block the thread longer than "timeout" milliseconds (similar to
+  the sys_arch_sem_wait() function). The "msg" argument is a result
+  parameter that is set by the function (i.e., by doing "*msg =
+  ptr"). The "msg" parameter maybe NULL to indicate that the message
+  should be dropped.
+
+  The return values are the same as for the sys_arch_sem_wait() function:
+  Number of milliseconds spent waiting or SYS_ARCH_TIMEOUT if there was a
+  timeout.
+
+  Note that a function with a similar name, sys_mbox_fetch(), is
+  implemented by lwIP. 
+  
+- struct sys_timeouts *sys_arch_timeouts(void)
+
+  Returns a pointer to the per-thread sys_timeouts structure. In lwIP,
+  each thread has a list of timeouts which is repressented as a linked
+  list of sys_timeout structures. The sys_timeouts structure holds a
+  pointer to a linked list of timeouts. This function is called by
+  the lwIP timeout scheduler and must not return a NULL value. 
+
+  In a single threadd sys_arch implementation, this function will
+  simply return a pointer to a global sys_timeouts variable stored in
+  the sys_arch module.
+  
+If threads are supported by the underlying operating system and if
+such functionality is needed in lwIP, the following function will have
+to be implemented as well:
+
+- sys_thread_t sys_thread_new(void (* thread)(void *arg), void *arg, int prio)
+
+  Starts a new thread with priority "prio" that will begin its execution in the
+  function "thread()". The "arg" argument will be passed as an argument to the
+  thread() function. The id of the new thread is returned. Both the id and
+  the priority are system dependent.
+
+- sys_prot_t sys_arch_protect(void)
+
+  This optional function does a "fast" critical region protection and returns
+  the previous protection level. This function is only called during very short
+  critical regions. An embedded system which supports ISR-based drivers might
+  want to implement this function by disabling interrupts. Task-based systems
+  might want to implement this by using a mutex or disabling tasking. This
+  function should support recursive calls from the same task or interrupt. In
+  other words, sys_arch_protect() could be called while already protected. In
+  that case the return value indicates that it is already protected.
+
+  sys_arch_protect() is only required if your port is supporting an operating
+  system.
+
+- void sys_arch_unprotect(sys_prot_t pval)
+
+  This optional function does a "fast" set of critical region protection to the
+  value specified by pval. See the documentation for sys_arch_protect() for
+  more information. This function is only required if your port is supporting
+  an operating system.
+
+-------------------------------------------------------------------------------
+Additional files required for the "OS support" emulation layer:
+-------------------------------------------------------------------------------
+
+cc.h       - Architecture environment, some compiler specific, some
+             environment specific (probably should move env stuff 
+             to sys_arch.h.)
+
+  Typedefs for the types used by lwip -
+    u8_t, s8_t, u16_t, s16_t, u32_t, s32_t, mem_ptr_t
+
+  Compiler hints for packing lwip's structures -
+    PACK_STRUCT_FIELD(x)
+    PACK_STRUCT_STRUCT
+    PACK_STRUCT_BEGIN
+    PACK_STRUCT_END
+
+  Platform specific diagnostic output -
+    LWIP_PLATFORM_DIAG(x)    - non-fatal, print a message.
+    LWIP_PLATFORM_ASSERT(x)  - fatal, print message and abandon execution.
+
+  "lightweight" synchronization mechanisms -
+    SYS_ARCH_DECL_PROTECT(x) - declare a protection state variable.
+    SYS_ARCH_PROTECT(x)      - enter protection mode.
+    SYS_ARCH_UNPROTECT(x)    - leave protection mode.
+
+  If the compiler does not provide memset() this file must include a
+  definition of it, or include a file which defines it.
+
+  This file must either include a system-local  which defines
+  the standard *nix error codes, or it should #define LWIP_PROVIDE_ERRNO
+  to make lwip/arch.h define the codes which are used throughout.
+
+
+perf.h     - Architecture specific performance measurement.
+  Measurement calls made throughout lwip, these can be defined to nothing.
+    PERF_START               - start measuring something.
+    PERF_STOP(x)             - stop measuring something, and record the result.
+
+sys_arch.h - Tied to sys_arch.c
+
+  Arch dependent types for the following objects:
+    sys_sem_t, sys_mbox_t, sys_thread_t,
+  And, optionally:
+    sys_prot_t
+
+  Defines to set vars of sys_mbox_t and sys_sem_t to NULL.
+    SYS_MBOX_NULL NULL
+    SYS_SEM_NULL NULL
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/FILES b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/FILES
new file mode 100644
index 000000000..2b6573185
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/FILES
@@ -0,0 +1,13 @@
+api/      - The code for the high-level wrapper API. Not needed if
+            you use the lowel-level call-back/raw API.
+
+core/     - The core of the TPC/IP stack; protocol implementations,
+            memory and buffer management, and the low-level raw API.
+	    
+include/  - lwIP include files.
+
+netif/    - Generic network interface device drivers are kept here,
+            as well as the ARP module.
+
+For more information on the various subdirectories, check the FILES
+file in each directory.
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/api/api_lib.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/api/api_lib.c
new file mode 100644
index 000000000..43b210e64
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/api/api_lib.c
@@ -0,0 +1,729 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+/* This is the part of the API that is linked with
+   the application */
+
+#include "lwip/opt.h"
+#include "lwip/api.h"
+#include "lwip/api_msg.h"
+#include "lwip/memp.h"
+
+
+struct
+netbuf *netbuf_new(void)
+{
+  struct netbuf *buf;
+
+  buf = memp_malloc(MEMP_NETBUF);
+  if (buf != NULL) {
+    buf->p = NULL;
+    buf->ptr = NULL;
+    return buf;
+  } else {
+    return NULL;
+  }
+}
+
+void
+netbuf_delete(struct netbuf *buf)
+{
+  if (buf != NULL) {
+    if (buf->p != NULL) {
+      pbuf_free(buf->p);
+      buf->p = buf->ptr = NULL;
+    }
+    memp_free(MEMP_NETBUF, buf);
+  }
+}
+
+void *
+netbuf_alloc(struct netbuf *buf, u16_t size)
+{
+  /* Deallocate any previously allocated memory. */
+  if (buf->p != NULL) {
+    pbuf_free(buf->p);
+  }
+  buf->p = pbuf_alloc(PBUF_TRANSPORT, size, PBUF_RAM);
+  if (buf->p == NULL) {
+     return NULL;
+  }
+  buf->ptr = buf->p;
+  return buf->p->payload;
+}
+
+void
+netbuf_free(struct netbuf *buf)
+{
+  if (buf->p != NULL) {
+    pbuf_free(buf->p);
+  }
+  buf->p = buf->ptr = NULL;
+}
+
+void
+netbuf_ref(struct netbuf *buf, void *dataptr, u16_t size)
+{
+  if (buf->p != NULL) {
+    pbuf_free(buf->p);
+  }
+  buf->p = pbuf_alloc(PBUF_TRANSPORT, 0, PBUF_REF);
+  buf->p->payload = dataptr;
+  buf->p->len = buf->p->tot_len = size;
+  buf->ptr = buf->p;
+}
+
+void
+netbuf_chain(struct netbuf *head, struct netbuf *tail)
+{
+  pbuf_chain(head->p, tail->p);
+  head->ptr = head->p;
+  memp_free(MEMP_NETBUF, tail);
+}
+
+u16_t
+netbuf_len(struct netbuf *buf)
+{
+  return buf->p->tot_len;
+}
+
+err_t
+netbuf_data(struct netbuf *buf, void **dataptr, u16_t *len)
+{
+  if (buf->ptr == NULL) {
+    return ERR_BUF;
+  }
+  *dataptr = buf->ptr->payload;
+  *len = buf->ptr->len;
+  return ERR_OK;
+}
+
+s8_t
+netbuf_next(struct netbuf *buf)
+{
+  if (buf->ptr->next == NULL) {
+    return -1;
+  }
+  buf->ptr = buf->ptr->next;
+  if (buf->ptr->next == NULL) {
+    return 1;
+  }
+  return 0;
+}
+
+void
+netbuf_first(struct netbuf *buf)
+{
+  buf->ptr = buf->p;
+}
+
+void
+netbuf_copy_partial(struct netbuf *buf, void *dataptr, u16_t len, u16_t offset)
+{
+  struct pbuf *p;
+  u16_t i, left;
+
+  left = 0;
+
+  if(buf == NULL || dataptr == NULL) {
+    return;
+  }
+  
+  /* This implementation is bad. It should use bcopy
+     instead. */
+  for(p = buf->p; left < len && p != NULL; p = p->next) {
+    if (offset != 0 && offset >= p->len) {
+      offset -= p->len;
+    } else {    
+      for(i = offset; i < p->len; ++i) {
+  ((char *)dataptr)[left] = ((char *)p->payload)[i];
+  if (++left >= len) {
+    return;
+  }
+      }
+      offset = 0;
+    }
+  }
+}
+
+void
+netbuf_copy(struct netbuf *buf, void *dataptr, u16_t len)
+{
+  netbuf_copy_partial(buf, dataptr, len, 0);
+}
+
+struct ip_addr *
+netbuf_fromaddr(struct netbuf *buf)
+{
+  return buf->fromaddr;
+}
+
+u16_t
+netbuf_fromport(struct netbuf *buf)
+{
+  return buf->fromport;
+}
+
+struct
+netconn *netconn_new_with_proto_and_callback(enum netconn_type t, u16_t proto,
+                                   void (*callback)(struct netconn *, enum netconn_evt, u16_t len))
+{
+  struct netconn *conn;
+  struct api_msg *msg;
+
+  conn = memp_malloc(MEMP_NETCONN);
+  if (conn == NULL) {
+    return NULL;
+  }
+  
+  conn->err = ERR_OK;
+  conn->type = t;
+  conn->pcb.tcp = NULL;
+
+  if ((conn->mbox = sys_mbox_new()) == SYS_MBOX_NULL) {
+    memp_free(MEMP_NETCONN, conn);
+    return NULL;
+  }
+  conn->recvmbox = SYS_MBOX_NULL;
+  conn->acceptmbox = SYS_MBOX_NULL;
+  conn->sem = SYS_SEM_NULL;
+  conn->state = NETCONN_NONE;
+  conn->socket = 0;
+  conn->callback = callback;
+  conn->recv_avail = 0;
+
+  if((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+    memp_free(MEMP_NETCONN, conn);
+    return NULL;
+  }
+  
+  msg->type = API_MSG_NEWCONN;
+  msg->msg.msg.bc.port = proto; /* misusing the port field */
+  msg->msg.conn = conn;
+  api_msg_post(msg);  
+  sys_mbox_fetch(conn->mbox, NULL);
+  memp_free(MEMP_API_MSG, msg);
+
+  if ( conn->err != ERR_OK ) {
+    memp_free(MEMP_NETCONN, conn);
+    return NULL;
+  }
+
+  return conn;
+}
+
+
+struct
+netconn *netconn_new(enum netconn_type t)
+{
+  return netconn_new_with_proto_and_callback(t,0,NULL);
+}
+
+struct
+netconn *netconn_new_with_callback(enum netconn_type t,
+                                   void (*callback)(struct netconn *, enum netconn_evt, u16_t len))
+{
+  return netconn_new_with_proto_and_callback(t,0,callback);
+}
+
+
+err_t
+netconn_delete(struct netconn *conn)
+{
+  struct api_msg *msg;
+  void *mem;
+  
+  if (conn == NULL) {
+    return ERR_OK;
+  }
+  
+  if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+    return ERR_MEM;
+  }
+  
+  msg->type = API_MSG_DELCONN;
+  msg->msg.conn = conn;
+  api_msg_post(msg);  
+  sys_mbox_fetch(conn->mbox, NULL);
+  memp_free(MEMP_API_MSG, msg);
+
+  /* Drain the recvmbox. */
+  if (conn->recvmbox != SYS_MBOX_NULL) {
+    while (sys_arch_mbox_fetch(conn->recvmbox, &mem, 1) != SYS_ARCH_TIMEOUT) {
+      if (conn->type == NETCONN_TCP) {
+        if(mem != NULL)
+          pbuf_free((struct pbuf *)mem);
+      } else {
+        netbuf_delete((struct netbuf *)mem);
+      }
+    }
+    sys_mbox_free(conn->recvmbox);
+    conn->recvmbox = SYS_MBOX_NULL;
+  }
+ 
+
+  /* Drain the acceptmbox. */
+  if (conn->acceptmbox != SYS_MBOX_NULL) {
+    while (sys_arch_mbox_fetch(conn->acceptmbox, &mem, 1) != SYS_ARCH_TIMEOUT) {
+      netconn_delete((struct netconn *)mem);
+    }
+    
+    sys_mbox_free(conn->acceptmbox);
+    conn->acceptmbox = SYS_MBOX_NULL;
+  }
+
+  sys_mbox_free(conn->mbox);
+  conn->mbox = SYS_MBOX_NULL;
+  if (conn->sem != SYS_SEM_NULL) {
+    sys_sem_free(conn->sem);
+  }
+  /*  conn->sem = SYS_SEM_NULL;*/
+  memp_free(MEMP_NETCONN, conn);
+  return ERR_OK;
+}
+
+enum netconn_type
+netconn_type(struct netconn *conn)
+{
+  return conn->type;
+}
+
+err_t
+netconn_peer(struct netconn *conn, struct ip_addr *addr,
+       u16_t *port)
+{
+  switch (conn->type) {
+  case NETCONN_RAW:
+    /* return an error as connecting is only a helper for upper layers */
+    return ERR_CONN;
+  case NETCONN_UDPLITE:
+  case NETCONN_UDPNOCHKSUM:
+  case NETCONN_UDP:
+    if (conn->pcb.udp == NULL ||
+  ((conn->pcb.udp->flags & UDP_FLAGS_CONNECTED) == 0))
+     return ERR_CONN;
+    *addr = (conn->pcb.udp->remote_ip);
+    *port = conn->pcb.udp->remote_port;
+    break;
+  case NETCONN_TCP:
+    if (conn->pcb.tcp == NULL)
+      return ERR_CONN;
+    *addr = (conn->pcb.tcp->remote_ip);
+    *port = conn->pcb.tcp->remote_port;
+    break;
+  }
+  return (conn->err = ERR_OK);
+}
+
+err_t
+netconn_addr(struct netconn *conn, struct ip_addr **addr,
+       u16_t *port)
+{
+  switch (conn->type) {
+  case NETCONN_RAW:
+    *addr = &(conn->pcb.raw->local_ip);
+    *port = conn->pcb.raw->protocol;
+    break;
+  case NETCONN_UDPLITE:
+  case NETCONN_UDPNOCHKSUM:
+  case NETCONN_UDP:
+    *addr = &(conn->pcb.udp->local_ip);
+    *port = conn->pcb.udp->local_port;
+    break;
+  case NETCONN_TCP:
+    *addr = &(conn->pcb.tcp->local_ip);
+    *port = conn->pcb.tcp->local_port;
+    break;
+  }
+  return (conn->err = ERR_OK);
+}
+
+err_t
+netconn_bind(struct netconn *conn, struct ip_addr *addr,
+      u16_t port)
+{
+  struct api_msg *msg;
+
+  if (conn == NULL) {
+    return ERR_VAL;
+  }
+
+  if (conn->type != NETCONN_TCP &&
+     conn->recvmbox == SYS_MBOX_NULL) {
+    if ((conn->recvmbox = sys_mbox_new()) == SYS_MBOX_NULL) {
+      return ERR_MEM;
+    }
+  }
+  
+  if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+    return (conn->err = ERR_MEM);
+  }
+  msg->type = API_MSG_BIND;
+  msg->msg.conn = conn;
+  msg->msg.msg.bc.ipaddr = addr;
+  msg->msg.msg.bc.port = port;
+  api_msg_post(msg);
+  sys_mbox_fetch(conn->mbox, NULL);
+  memp_free(MEMP_API_MSG, msg);
+  return conn->err;
+}
+
+
+err_t
+netconn_connect(struct netconn *conn, struct ip_addr *addr,
+       u16_t port)
+{
+  struct api_msg *msg;
+  
+  if (conn == NULL) {
+    return ERR_VAL;
+  }
+
+
+  if (conn->recvmbox == SYS_MBOX_NULL) {
+    if ((conn->recvmbox = sys_mbox_new()) == SYS_MBOX_NULL) {
+      return ERR_MEM;
+    }
+  }
+  
+  if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+    return ERR_MEM;
+  }
+  msg->type = API_MSG_CONNECT;
+  msg->msg.conn = conn;  
+  msg->msg.msg.bc.ipaddr = addr;
+  msg->msg.msg.bc.port = port;
+  api_msg_post(msg);
+  sys_mbox_fetch(conn->mbox, NULL);
+  memp_free(MEMP_API_MSG, msg);
+  return conn->err;
+}
+
+err_t
+netconn_disconnect(struct netconn *conn)
+{
+  struct api_msg *msg;
+  
+  if (conn == NULL) {
+    return ERR_VAL;
+  }
+
+  if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+    return ERR_MEM;
+  }
+  msg->type = API_MSG_DISCONNECT;
+  msg->msg.conn = conn;  
+  api_msg_post(msg);
+  sys_mbox_fetch(conn->mbox, NULL);
+  memp_free(MEMP_API_MSG, msg);
+  return conn->err;
+
+}
+
+err_t
+netconn_listen(struct netconn *conn)
+{
+  struct api_msg *msg;
+
+  if (conn == NULL) {
+    return ERR_VAL;
+  }
+
+  if (conn->acceptmbox == SYS_MBOX_NULL) {
+    conn->acceptmbox = sys_mbox_new();
+    if (conn->acceptmbox == SYS_MBOX_NULL) {
+      return ERR_MEM;
+    }
+  }
+  
+  if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+    return (conn->err = ERR_MEM);
+  }
+  msg->type = API_MSG_LISTEN;
+  msg->msg.conn = conn;
+  api_msg_post(msg);
+  sys_mbox_fetch(conn->mbox, NULL);
+  memp_free(MEMP_API_MSG, msg);
+  return conn->err;
+}
+
+struct netconn *
+netconn_accept(struct netconn *conn)
+{
+  struct netconn *newconn;
+  
+  if (conn == NULL) {
+    return NULL;
+  }
+  
+  sys_mbox_fetch(conn->acceptmbox, (void **)&newconn);
+  /* Register event with callback */
+  if (conn->callback)
+      (*conn->callback)(conn, NETCONN_EVT_RCVMINUS, 0);
+  
+  return newconn;
+}
+
+struct netbuf *
+netconn_recv(struct netconn *conn)
+{
+  struct api_msg *msg;
+  struct netbuf *buf;
+  struct pbuf *p;
+  u16_t len;
+    
+  if (conn == NULL) {
+    return NULL;
+  }
+  
+  if (conn->recvmbox == SYS_MBOX_NULL) {
+    conn->err = ERR_CONN;
+    return NULL;
+  }
+
+  if (conn->err != ERR_OK) {
+    return NULL;
+  }
+
+  if (conn->type == NETCONN_TCP) {
+    if (conn->pcb.tcp->state == LISTEN) {
+      conn->err = ERR_CONN;
+      return NULL;
+    }
+
+
+    buf = memp_malloc(MEMP_NETBUF);
+
+    if (buf == NULL) {
+      conn->err = ERR_MEM;
+      return NULL;
+    }
+    
+    sys_mbox_fetch(conn->recvmbox, (void **)&p);
+
+    if (p != NULL)
+    {
+        len = p->tot_len;
+        conn->recv_avail -= len;
+    }
+    else
+        len = 0;
+    
+    /* Register event with callback */
+      if (conn->callback)
+        (*conn->callback)(conn, NETCONN_EVT_RCVMINUS, len);
+
+    /* If we are closed, we indicate that we no longer wish to receive
+       data by setting conn->recvmbox to SYS_MBOX_NULL. */
+    if (p == NULL) {
+      memp_free(MEMP_NETBUF, buf);
+      sys_mbox_free(conn->recvmbox);
+      conn->recvmbox = SYS_MBOX_NULL;
+      return NULL;
+    }
+
+    buf->p = p;
+    buf->ptr = p;
+    buf->fromport = 0;
+    buf->fromaddr = NULL;
+
+    /* Let the stack know that we have taken the data. */
+    if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+      conn->err = ERR_MEM;
+      return buf;
+    }
+    msg->type = API_MSG_RECV;
+    msg->msg.conn = conn;
+    if (buf != NULL) {
+      msg->msg.msg.len = buf->p->tot_len;
+    } else {
+      msg->msg.msg.len = 1;
+    }
+    api_msg_post(msg);
+
+    sys_mbox_fetch(conn->mbox, NULL);
+    memp_free(MEMP_API_MSG, msg);
+  } else {
+    sys_mbox_fetch(conn->recvmbox, (void **)&buf);
+  conn->recv_avail -= buf->p->tot_len;
+    /* Register event with callback */
+    if (conn->callback)
+        (*conn->callback)(conn, NETCONN_EVT_RCVMINUS, buf->p->tot_len);
+  }
+
+  
+
+    
+  LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_recv: received %p (err %d)\n", (void *)buf, conn->err));
+
+
+  return buf;
+}
+
+err_t
+netconn_send(struct netconn *conn, struct netbuf *buf)
+{
+  struct api_msg *msg;
+
+  if (conn == NULL) {
+    return ERR_VAL;
+  }
+
+  if (conn->err != ERR_OK) {
+    return conn->err;
+  }
+
+  if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+    return (conn->err = ERR_MEM);
+  }
+
+  LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_send: sending %d bytes\n", buf->p->tot_len));
+  msg->type = API_MSG_SEND;
+  msg->msg.conn = conn;
+  msg->msg.msg.p = buf->p;
+  api_msg_post(msg);
+
+  sys_mbox_fetch(conn->mbox, NULL);
+  memp_free(MEMP_API_MSG, msg);
+  return conn->err;
+}
+
+err_t
+netconn_write(struct netconn *conn, void *dataptr, u16_t size, u8_t copy)
+{
+  struct api_msg *msg;
+  u16_t len;
+  
+  if (conn == NULL) {
+    return ERR_VAL;
+  }
+
+  if (conn->err != ERR_OK) {
+    return conn->err;
+  }
+  
+  if (conn->sem == SYS_SEM_NULL) {
+    conn->sem = sys_sem_new(0);
+    if (conn->sem == SYS_SEM_NULL) {
+      return ERR_MEM;
+    }
+  }
+
+  if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+    return (conn->err = ERR_MEM);
+  }
+  msg->type = API_MSG_WRITE;
+  msg->msg.conn = conn;
+        
+
+  conn->state = NETCONN_WRITE;
+  while (conn->err == ERR_OK && size > 0) {
+    msg->msg.msg.w.dataptr = dataptr;
+    msg->msg.msg.w.copy = copy;
+    
+    if (conn->type == NETCONN_TCP) {
+      if (tcp_sndbuf(conn->pcb.tcp) == 0) {
+  sys_sem_wait(conn->sem);
+  if (conn->err != ERR_OK) {
+    goto ret;
+  }
+      }
+      if (size > tcp_sndbuf(conn->pcb.tcp)) {
+  /* We cannot send more than one send buffer's worth of data at a
+     time. */
+  len = tcp_sndbuf(conn->pcb.tcp);
+      } else {
+  len = size;
+      }
+    } else {
+      len = size;
+    }
+    
+    LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_write: writing %d bytes (%d)\n", len, copy));
+    msg->msg.msg.w.len = len;
+    api_msg_post(msg);
+    sys_mbox_fetch(conn->mbox, NULL);    
+    if (conn->err == ERR_OK) {
+      dataptr = (void *)((char *)dataptr + len);
+      size -= len;
+    } else if (conn->err == ERR_MEM) {
+      conn->err = ERR_OK;
+      sys_sem_wait(conn->sem);
+    } else {
+      goto ret;
+    }
+  }
+ ret:
+  memp_free(MEMP_API_MSG, msg);
+  conn->state = NETCONN_NONE;
+  if (conn->sem != SYS_SEM_NULL) {
+    sys_sem_free(conn->sem);
+    conn->sem = SYS_SEM_NULL;
+  }
+  
+  return conn->err;
+}
+
+err_t
+netconn_close(struct netconn *conn)
+{
+  struct api_msg *msg;
+
+  if (conn == NULL) {
+    return ERR_VAL;
+  }
+  if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+    return (conn->err = ERR_MEM);
+  }
+
+  conn->state = NETCONN_CLOSE;
+ again:
+  msg->type = API_MSG_CLOSE;
+  msg->msg.conn = conn;
+  api_msg_post(msg);
+  sys_mbox_fetch(conn->mbox, NULL);
+  if (conn->err == ERR_MEM &&
+     conn->sem != SYS_SEM_NULL) {
+    sys_sem_wait(conn->sem);
+    goto again;
+  }
+  conn->state = NETCONN_NONE;
+  memp_free(MEMP_API_MSG, msg);
+  return conn->err;
+}
+
+err_t
+netconn_err(struct netconn *conn)
+{
+  return conn->err;
+}
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/api/api_msg.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/api/api_msg.c
new file mode 100644
index 000000000..8247aaaab
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/api/api_msg.c
@@ -0,0 +1,810 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+#include "lwip/arch.h"
+#include "lwip/api_msg.h"
+#include "lwip/memp.h"
+#include "lwip/sys.h"
+#include "lwip/tcpip.h"
+
+#if LWIP_RAW
+static u8_t
+recv_raw(void *arg, struct raw_pcb *pcb, struct pbuf *p,
+    struct ip_addr *addr)
+{
+  struct netbuf *buf;
+  struct netconn *conn;
+
+  conn = arg;
+  if (!conn) return 0;
+
+  if (conn->recvmbox != SYS_MBOX_NULL) {
+    if (!(buf = memp_malloc(MEMP_NETBUF))) {
+      return 0;
+    }
+    pbuf_ref(p);
+    buf->p = p;
+    buf->ptr = p;
+    buf->fromaddr = addr;
+    buf->fromport = pcb->protocol;
+
+    conn->recv_avail += p->tot_len;
+    /* Register event with callback */
+    if (conn->callback)
+        (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, p->tot_len);
+    sys_mbox_post(conn->recvmbox, buf);
+  }
+
+  return 0; /* do not eat the packet */
+}
+#endif
+#if LWIP_UDP
+static void
+recv_udp(void *arg, struct udp_pcb *pcb, struct pbuf *p,
+   struct ip_addr *addr, u16_t port)
+{
+  struct netbuf *buf;
+  struct netconn *conn;
+
+  (void)pcb;
+
+  conn = arg;
+  
+  if (conn == NULL) {
+    pbuf_free(p);
+    return;
+  }
+  if (conn->recvmbox != SYS_MBOX_NULL) {
+    buf = memp_malloc(MEMP_NETBUF);
+    if (buf == NULL) {
+      pbuf_free(p);
+      return;
+    } else {
+      buf->p = p;
+      buf->ptr = p;
+      buf->fromaddr = addr;
+      buf->fromport = port;
+    }
+
+  conn->recv_avail += p->tot_len;
+    /* Register event with callback */
+    if (conn->callback)
+        (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, p->tot_len);
+    sys_mbox_post(conn->recvmbox, buf);
+  }
+}
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+
+static err_t
+recv_tcp(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err)
+{
+  struct netconn *conn;
+  u16_t len;
+
+  (void)pcb;
+
+  conn = arg;
+
+  if (conn == NULL) {
+    pbuf_free(p);
+    return ERR_VAL;
+  }
+
+  if (conn->recvmbox != SYS_MBOX_NULL) {
+        
+    conn->err = err;
+    if (p != NULL) {
+        len = p->tot_len;
+        conn->recv_avail += len;
+    }
+    else
+        len = 0;
+    /* Register event with callback */
+    if (conn->callback)
+        (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, len);
+    sys_mbox_post(conn->recvmbox, p);
+  }  
+  return ERR_OK;
+}
+
+
+static err_t
+poll_tcp(void *arg, struct tcp_pcb *pcb)
+{
+  struct netconn *conn;
+
+  (void)pcb;
+
+  conn = arg;
+  if (conn != NULL &&
+     (conn->state == NETCONN_WRITE || conn->state == NETCONN_CLOSE) &&
+     conn->sem != SYS_SEM_NULL) {
+    sys_sem_signal(conn->sem);
+  }
+  return ERR_OK;
+}
+
+static err_t
+sent_tcp(void *arg, struct tcp_pcb *pcb, u16_t len)
+{
+  struct netconn *conn;
+
+  (void)pcb;
+
+  conn = arg;
+  if (conn != NULL && conn->sem != SYS_SEM_NULL) {
+    sys_sem_signal(conn->sem);
+  }
+
+  if (conn && conn->callback)
+      if (tcp_sndbuf(conn->pcb.tcp) > TCP_SNDLOWAT)
+          (*conn->callback)(conn, NETCONN_EVT_SENDPLUS, len);
+  
+  return ERR_OK;
+}
+
+static void
+err_tcp(void *arg, err_t err)
+{
+  struct netconn *conn;
+
+  conn = arg;
+
+  conn->pcb.tcp = NULL;
+
+  
+  conn->err = err;
+  if (conn->recvmbox != SYS_MBOX_NULL) {
+    /* Register event with callback */
+    if (conn->callback)
+      (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, 0);
+    sys_mbox_post(conn->recvmbox, NULL);
+  }
+  if (conn->mbox != SYS_MBOX_NULL) {
+    sys_mbox_post(conn->mbox, NULL);
+  }
+  if (conn->acceptmbox != SYS_MBOX_NULL) {
+     /* Register event with callback */
+    if (conn->callback)
+      (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, 0);
+    sys_mbox_post(conn->acceptmbox, NULL);
+  }
+  if (conn->sem != SYS_SEM_NULL) {
+    sys_sem_signal(conn->sem);
+  }
+}
+
+static void
+setup_tcp(struct netconn *conn)
+{
+  struct tcp_pcb *pcb;
+  
+  pcb = conn->pcb.tcp;
+  tcp_arg(pcb, conn);
+  tcp_recv(pcb, recv_tcp);
+  tcp_sent(pcb, sent_tcp);
+  tcp_poll(pcb, poll_tcp, 4);
+  tcp_err(pcb, err_tcp);
+}
+
+static err_t
+accept_function(void *arg, struct tcp_pcb *newpcb, err_t err)
+{
+  sys_mbox_t mbox;
+  struct netconn *newconn;
+  struct netconn *conn;
+  
+#if API_MSG_DEBUG
+#if TCP_DEBUG
+  tcp_debug_print_state(newpcb->state);
+#endif /* TCP_DEBUG */
+#endif /* API_MSG_DEBUG */
+  conn = (struct netconn *)arg;
+  mbox = conn->acceptmbox;
+  newconn = memp_malloc(MEMP_NETCONN);
+  if (newconn == NULL) {
+    return ERR_MEM;
+  }
+  newconn->type = NETCONN_TCP;
+  newconn->pcb.tcp = newpcb;
+  setup_tcp(newconn);
+  newconn->recvmbox = sys_mbox_new();
+  if (newconn->recvmbox == SYS_MBOX_NULL) {
+    memp_free(MEMP_NETCONN, newconn);
+    return ERR_MEM;
+  }
+  newconn->mbox = sys_mbox_new();
+  if (newconn->mbox == SYS_MBOX_NULL) {
+    sys_mbox_free(newconn->recvmbox);
+    memp_free(MEMP_NETCONN, newconn);
+    return ERR_MEM;
+  }
+  newconn->sem = sys_sem_new(0);
+  if (newconn->sem == SYS_SEM_NULL) {
+    sys_mbox_free(newconn->recvmbox);
+    sys_mbox_free(newconn->mbox);
+    memp_free(MEMP_NETCONN, newconn);
+    return ERR_MEM;
+  }
+  newconn->acceptmbox = SYS_MBOX_NULL;
+  newconn->err = err;
+  /* Register event with callback */
+  if (conn->callback)
+  {
+    (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, 0);
+    /* We have to set the callback here even though
+     * the new socket is unknown. Mark the socket as -1. */
+    newconn->callback = conn->callback;
+    newconn->socket = -1;
+  }
+  
+  sys_mbox_post(mbox, newconn);
+  return ERR_OK;
+}
+#endif /* LWIP_TCP */
+
+static void
+do_newconn(struct api_msg_msg *msg)
+{
+   if(msg->conn->pcb.tcp != NULL) {
+   /* This "new" connection already has a PCB allocated. */
+   /* Is this an error condition? Should it be deleted? 
+      We currently just are happy and return. */
+     sys_mbox_post(msg->conn->mbox, NULL);
+     return;
+   }
+
+   msg->conn->err = ERR_OK;
+
+   /* Allocate a PCB for this connection */
+   switch(msg->conn->type) {
+#if LWIP_RAW
+   case NETCONN_RAW:
+      msg->conn->pcb.raw = raw_new(msg->msg.bc.port); /* misusing the port field */
+      raw_recv(msg->conn->pcb.raw, recv_raw, msg->conn);
+     break;
+#endif
+#if LWIP_UDP
+   case NETCONN_UDPLITE:
+      msg->conn->pcb.udp = udp_new();
+      if(msg->conn->pcb.udp == NULL) {
+         msg->conn->err = ERR_MEM;
+         break;
+      }
+      udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_UDPLITE);
+      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
+      break;
+   case NETCONN_UDPNOCHKSUM:
+      msg->conn->pcb.udp = udp_new();
+      if(msg->conn->pcb.udp == NULL) {
+         msg->conn->err = ERR_MEM;
+         break;
+      }
+      udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_NOCHKSUM);
+      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
+      break;
+   case NETCONN_UDP:
+      msg->conn->pcb.udp = udp_new();
+      if(msg->conn->pcb.udp == NULL) {
+         msg->conn->err = ERR_MEM;
+         break;
+      }
+      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
+      break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+   case NETCONN_TCP:
+      msg->conn->pcb.tcp = tcp_new();
+      if(msg->conn->pcb.tcp == NULL) {
+         msg->conn->err = ERR_MEM;
+         break;
+      }
+      setup_tcp(msg->conn);
+      break;
+#endif
+   }
+   
+  
+  sys_mbox_post(msg->conn->mbox, NULL);
+}
+
+
+static void
+do_delconn(struct api_msg_msg *msg)
+{
+  if (msg->conn->pcb.tcp != NULL) {
+    switch (msg->conn->type) {
+#if LWIP_RAW
+    case NETCONN_RAW:
+      raw_remove(msg->conn->pcb.raw);
+      break;
+#endif
+#if LWIP_UDP
+    case NETCONN_UDPLITE:
+      /* FALLTHROUGH */
+    case NETCONN_UDPNOCHKSUM:
+      /* FALLTHROUGH */
+    case NETCONN_UDP:
+      msg->conn->pcb.udp->recv_arg = NULL;
+      udp_remove(msg->conn->pcb.udp);
+      break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP      
+    case NETCONN_TCP:
+      if (msg->conn->pcb.tcp->state == LISTEN) {
+  tcp_arg(msg->conn->pcb.tcp, NULL);
+  tcp_accept(msg->conn->pcb.tcp, NULL);  
+  tcp_close(msg->conn->pcb.tcp);
+      } else {
+  tcp_arg(msg->conn->pcb.tcp, NULL);
+  tcp_sent(msg->conn->pcb.tcp, NULL);
+  tcp_recv(msg->conn->pcb.tcp, NULL);  
+  tcp_poll(msg->conn->pcb.tcp, NULL, 0);
+  tcp_err(msg->conn->pcb.tcp, NULL);
+  if (tcp_close(msg->conn->pcb.tcp) != ERR_OK) {
+    tcp_abort(msg->conn->pcb.tcp);
+  }
+      }
+#endif
+    default:  
+    break;
+    }
+  }
+  /* Trigger select() in socket layer */
+  if (msg->conn->callback)
+  {
+      (*msg->conn->callback)(msg->conn, NETCONN_EVT_RCVPLUS, 0);
+      (*msg->conn->callback)(msg->conn, NETCONN_EVT_SENDPLUS, 0);
+  }
+  
+  if (msg->conn->mbox != SYS_MBOX_NULL) {
+    sys_mbox_post(msg->conn->mbox, NULL);
+  }
+}
+
+static void
+do_bind(struct api_msg_msg *msg)
+{
+  if (msg->conn->pcb.tcp == NULL) {
+    switch (msg->conn->type) {
+#if LWIP_RAW
+    case NETCONN_RAW:
+      msg->conn->pcb.raw = raw_new(msg->msg.bc.port); /* misusing the port field as protocol */
+      raw_recv(msg->conn->pcb.raw, recv_raw, msg->conn);
+      break;
+#endif
+#if LWIP_UDP
+    case NETCONN_UDPLITE:
+      msg->conn->pcb.udp = udp_new();
+      udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_UDPLITE);
+      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
+      break;
+    case NETCONN_UDPNOCHKSUM:
+      msg->conn->pcb.udp = udp_new();
+      udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_NOCHKSUM);
+      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
+      break;
+    case NETCONN_UDP:
+      msg->conn->pcb.udp = udp_new();
+      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
+      break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP      
+    case NETCONN_TCP:
+      msg->conn->pcb.tcp = tcp_new();
+      setup_tcp(msg->conn);
+#endif /* LWIP_TCP */
+    default:  
+    break;
+    }
+  }
+  switch (msg->conn->type) {
+#if LWIP_RAW
+  case NETCONN_RAW:
+    msg->conn->err = raw_bind(msg->conn->pcb.raw,msg->msg.bc.ipaddr);
+    break;
+#endif
+#if LWIP_UDP
+  case NETCONN_UDPLITE:
+    /* FALLTHROUGH */
+  case NETCONN_UDPNOCHKSUM:
+    /* FALLTHROUGH */
+  case NETCONN_UDP:
+    msg->conn->err = udp_bind(msg->conn->pcb.udp, msg->msg.bc.ipaddr, msg->msg.bc.port);
+    break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+  case NETCONN_TCP:
+    msg->conn->err = tcp_bind(msg->conn->pcb.tcp,
+            msg->msg.bc.ipaddr, msg->msg.bc.port);
+#endif /* LWIP_TCP */
+  default:
+    break;
+  }
+  sys_mbox_post(msg->conn->mbox, NULL);
+}
+#if LWIP_TCP
+
+static err_t
+do_connected(void *arg, struct tcp_pcb *pcb, err_t err)
+{
+  struct netconn *conn;
+
+  (void)pcb;
+
+  conn = arg;
+
+  if (conn == NULL) {
+    return ERR_VAL;
+  }
+  
+  conn->err = err;
+  if (conn->type == NETCONN_TCP && err == ERR_OK) {
+    setup_tcp(conn);
+  }    
+  sys_mbox_post(conn->mbox, NULL);
+  return ERR_OK;
+}
+#endif  
+
+static void
+do_connect(struct api_msg_msg *msg)
+{
+  if (msg->conn->pcb.tcp == NULL) {
+    switch (msg->conn->type) {
+#if LWIP_RAW
+    case NETCONN_RAW:
+      msg->conn->pcb.raw = raw_new(msg->msg.bc.port); /* misusing the port field as protocol */
+      raw_recv(msg->conn->pcb.raw, recv_raw, msg->conn);
+      break;
+#endif
+#if LWIP_UDP
+    case NETCONN_UDPLITE:
+      msg->conn->pcb.udp = udp_new();
+      if (msg->conn->pcb.udp == NULL) {
+  msg->conn->err = ERR_MEM;
+  sys_mbox_post(msg->conn->mbox, NULL);
+  return;
+      }
+      udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_UDPLITE);
+      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
+      break;
+    case NETCONN_UDPNOCHKSUM:
+      msg->conn->pcb.udp = udp_new();
+      if (msg->conn->pcb.udp == NULL) {
+  msg->conn->err = ERR_MEM;
+  sys_mbox_post(msg->conn->mbox, NULL);
+  return;
+      }
+      udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_NOCHKSUM);
+      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
+      break;
+    case NETCONN_UDP:
+      msg->conn->pcb.udp = udp_new();
+      if (msg->conn->pcb.udp == NULL) {
+  msg->conn->err = ERR_MEM;
+  sys_mbox_post(msg->conn->mbox, NULL);
+  return;
+      }
+      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
+      break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP      
+    case NETCONN_TCP:
+      msg->conn->pcb.tcp = tcp_new();      
+      if (msg->conn->pcb.tcp == NULL) {
+  msg->conn->err = ERR_MEM;
+  sys_mbox_post(msg->conn->mbox, NULL);
+  return;
+      }
+#endif
+    default:
+      break;
+    }
+  }
+  switch (msg->conn->type) {
+#if LWIP_RAW
+  case NETCONN_RAW:
+    raw_connect(msg->conn->pcb.raw, msg->msg.bc.ipaddr);
+    sys_mbox_post(msg->conn->mbox, NULL);
+    break;
+#endif
+#if LWIP_UDP
+  case NETCONN_UDPLITE:
+    /* FALLTHROUGH */
+  case NETCONN_UDPNOCHKSUM:
+    /* FALLTHROUGH */
+  case NETCONN_UDP:
+    udp_connect(msg->conn->pcb.udp, msg->msg.bc.ipaddr, msg->msg.bc.port);
+    sys_mbox_post(msg->conn->mbox, NULL);
+    break;
+#endif 
+#if LWIP_TCP      
+  case NETCONN_TCP:
+    /*    tcp_arg(msg->conn->pcb.tcp, msg->conn);*/
+    setup_tcp(msg->conn);
+    tcp_connect(msg->conn->pcb.tcp, msg->msg.bc.ipaddr, msg->msg.bc.port,
+    do_connected);
+    /*tcp_output(msg->conn->pcb.tcp);*/
+#endif
+
+  default:
+    break;
+  }
+}
+
+static void
+do_disconnect(struct api_msg_msg *msg)
+{
+
+  switch (msg->conn->type) {
+#if LWIP_RAW
+  case NETCONN_RAW:
+    /* Do nothing as connecting is only a helper for upper lwip layers */
+    break;
+#endif
+#if LWIP_UDP
+  case NETCONN_UDPLITE:
+    /* FALLTHROUGH */
+  case NETCONN_UDPNOCHKSUM:
+    /* FALLTHROUGH */
+  case NETCONN_UDP:
+    udp_disconnect(msg->conn->pcb.udp);
+    break;
+#endif 
+  case NETCONN_TCP:
+    break;
+  }
+  sys_mbox_post(msg->conn->mbox, NULL);
+}
+
+
+static void
+do_listen(struct api_msg_msg *msg)
+{
+  if (msg->conn->pcb.tcp != NULL) {
+    switch (msg->conn->type) {
+#if LWIP_RAW
+    case NETCONN_RAW:
+      LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: listen RAW: cannot listen for RAW.\n"));
+      break;
+#endif
+#if LWIP_UDP
+    case NETCONN_UDPLITE:
+      /* FALLTHROUGH */
+    case NETCONN_UDPNOCHKSUM:
+      /* FALLTHROUGH */
+    case NETCONN_UDP:
+      LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: listen UDP: cannot listen for UDP.\n"));
+      break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP      
+    case NETCONN_TCP:
+      msg->conn->pcb.tcp = tcp_listen(msg->conn->pcb.tcp);
+      if (msg->conn->pcb.tcp == NULL) {
+  msg->conn->err = ERR_MEM;
+      } else {
+  if (msg->conn->acceptmbox == SYS_MBOX_NULL) {
+    msg->conn->acceptmbox = sys_mbox_new();
+    if (msg->conn->acceptmbox == SYS_MBOX_NULL) {
+      msg->conn->err = ERR_MEM;
+      break;
+    }
+  }
+  tcp_arg(msg->conn->pcb.tcp, msg->conn);
+  tcp_accept(msg->conn->pcb.tcp, accept_function);
+      }
+#endif
+    default:
+      break;
+    }
+  }
+  sys_mbox_post(msg->conn->mbox, NULL);
+}
+
+static void
+do_accept(struct api_msg_msg *msg)
+{
+  if (msg->conn->pcb.tcp != NULL) {
+    switch (msg->conn->type) {
+#if LWIP_RAW
+    case NETCONN_RAW:
+      LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: accept RAW: cannot accept for RAW.\n"));
+      break;
+#endif
+#if LWIP_UDP
+    case NETCONN_UDPLITE:
+      /* FALLTHROUGH */
+    case NETCONN_UDPNOCHKSUM:
+      /* FALLTHROUGH */
+    case NETCONN_UDP:    
+      LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: accept UDP: cannot accept for UDP.\n"));
+      break;
+#endif /* LWIP_UDP */
+    case NETCONN_TCP:
+      break;
+    }
+  }
+}
+
+static void
+do_send(struct api_msg_msg *msg)
+{
+  if (msg->conn->pcb.tcp != NULL) {
+    switch (msg->conn->type) {
+#if LWIP_RAW
+    case NETCONN_RAW:
+      raw_send(msg->conn->pcb.raw, msg->msg.p);
+      break;
+#endif
+#if LWIP_UDP
+    case NETCONN_UDPLITE:
+      /* FALLTHROUGH */
+    case NETCONN_UDPNOCHKSUM:
+      /* FALLTHROUGH */
+    case NETCONN_UDP:
+      udp_send(msg->conn->pcb.udp, msg->msg.p);
+      break;
+#endif /* LWIP_UDP */
+    case NETCONN_TCP:
+      break;
+    }
+  }
+  sys_mbox_post(msg->conn->mbox, NULL);
+}
+
+static void
+do_recv(struct api_msg_msg *msg)
+{
+#if LWIP_TCP
+  if (msg->conn->pcb.tcp != NULL) {
+    if (msg->conn->type == NETCONN_TCP) {
+      tcp_recved(msg->conn->pcb.tcp, msg->msg.len);
+    }
+  }
+#endif  
+  sys_mbox_post(msg->conn->mbox, NULL);
+}
+
+static void
+do_write(struct api_msg_msg *msg)
+{
+#if LWIP_TCP  
+  err_t err;
+#endif  
+  if (msg->conn->pcb.tcp != NULL) {
+    switch (msg->conn->type) {
+#if LWIP_RAW
+    case NETCONN_RAW:
+      msg->conn->err = ERR_VAL;
+      break;
+#endif
+#if LWIP_UDP 
+    case NETCONN_UDPLITE:
+      /* FALLTHROUGH */
+    case NETCONN_UDPNOCHKSUM:
+      /* FALLTHROUGH */
+    case NETCONN_UDP:
+      msg->conn->err = ERR_VAL;
+      break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP 
+    case NETCONN_TCP:      
+      err = tcp_write(msg->conn->pcb.tcp, msg->msg.w.dataptr,
+                      msg->msg.w.len, msg->msg.w.copy);
+      /* This is the Nagle algorithm: inhibit the sending of new TCP
+   segments when new outgoing data arrives from the user if any
+   previously transmitted data on the connection remains
+   unacknowledged. */
+      if(err == ERR_OK && (msg->conn->pcb.tcp->unacked == NULL || (msg->conn->pcb.tcp->flags & TF_NODELAY)) ) {
+  tcp_output(msg->conn->pcb.tcp);
+      }
+      msg->conn->err = err;
+      if (msg->conn->callback)
+          if (err == ERR_OK)
+          {
+              if (tcp_sndbuf(msg->conn->pcb.tcp) <= TCP_SNDLOWAT)
+                  (*msg->conn->callback)(msg->conn, NETCONN_EVT_SENDMINUS, msg->msg.w.len);
+          }
+#endif
+    default:
+      break;
+    }
+  }
+  sys_mbox_post(msg->conn->mbox, NULL);
+}
+
+static void
+do_close(struct api_msg_msg *msg)
+{
+  err_t err;
+
+  err = ERR_OK;
+
+  if (msg->conn->pcb.tcp != NULL) {
+    switch (msg->conn->type) {
+#if LWIP_RAW
+    case NETCONN_RAW:
+      break;
+#endif
+#if LWIP_UDP
+    case NETCONN_UDPLITE:
+      /* FALLTHROUGH */
+    case NETCONN_UDPNOCHKSUM:
+      /* FALLTHROUGH */
+    case NETCONN_UDP:
+      break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+    case NETCONN_TCP:
+      if (msg->conn->pcb.tcp->state == LISTEN) {
+  err = tcp_close(msg->conn->pcb.tcp);
+      }
+      msg->conn->err = err;      
+#endif
+    default:      
+      break;
+    }
+  }
+  sys_mbox_post(msg->conn->mbox, NULL);
+}
+
+typedef void (* api_msg_decode)(struct api_msg_msg *msg);
+static api_msg_decode decode[API_MSG_MAX] = {
+  do_newconn,
+  do_delconn,
+  do_bind,
+  do_connect,
+  do_disconnect,
+  do_listen,
+  do_accept,
+  do_send,
+  do_recv,
+  do_write,
+  do_close
+  };
+void
+api_msg_input(struct api_msg *msg)
+{  
+  decode[msg->type](&(msg->msg));
+}
+
+void
+api_msg_post(struct api_msg *msg)
+{
+  tcpip_apimsg(msg);
+}
+
+
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/api/err.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/api/err.c
new file mode 100644
index 000000000..cc6367814
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/api/err.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/err.h"
+
+#ifdef LWIP_DEBUG
+
+static char *err_strerr[] = {"Ok.",
+           "Out of memory error.",
+           "Buffer error.",
+           "Connection aborted.",
+           "Connection reset.",
+           "Connection closed.",
+           "Not connected.",
+           "Illegal value.",
+           "Illegal argument.",
+           "Routing problem.",
+           "Address in use."
+};
+
+
+char *
+lwip_strerr(err_t err)
+{
+  return err_strerr[-err];
+
+}
+
+
+#endif /* LWIP_DEBUG */
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/api/sockets.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/api/sockets.c
new file mode 100644
index 000000000..af96db436
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/api/sockets.c
@@ -0,0 +1,1359 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ * Improved by Marc Boucher  and David Haas 
+ *
+ */
+
+#include 
+#include 
+
+#include "lwip/opt.h"
+#include "lwip/api.h"
+#include "lwip/arch.h"
+#include "lwip/sys.h"
+
+#include "lwip/sockets.h"
+
+#define NUM_SOCKETS MEMP_NUM_NETCONN
+
+struct lwip_socket {
+  struct netconn *conn;
+  struct netbuf *lastdata;
+  u16_t lastoffset;
+  u16_t rcvevent;
+  u16_t sendevent;
+  u16_t  flags;
+  int err;
+};
+
+struct lwip_select_cb
+{
+    struct lwip_select_cb *next;
+    fd_set *readset;
+    fd_set *writeset;
+    fd_set *exceptset;
+    int sem_signalled;
+    sys_sem_t sem;
+};
+
+static struct lwip_socket sockets[NUM_SOCKETS];
+static struct lwip_select_cb *select_cb_list = 0;
+
+static sys_sem_t socksem = 0;
+static sys_sem_t selectsem = 0;
+
+static void
+event_callback(struct netconn *conn, enum netconn_evt evt, u16_t len);
+
+static int err_to_errno_table[11] = {
+    0,      /* ERR_OK    0      No error, everything OK. */
+    ENOMEM,    /* ERR_MEM  -1      Out of memory error.     */
+    ENOBUFS,    /* ERR_BUF  -2      Buffer error.            */
+    ECONNABORTED,  /* ERR_ABRT -3      Connection aborted.      */
+    ECONNRESET,    /* ERR_RST  -4      Connection reset.        */
+    ESHUTDOWN,    /* ERR_CLSD -5      Connection closed.       */
+    ENOTCONN,    /* ERR_CONN -6      Not connected.           */
+    EINVAL,    /* ERR_VAL  -7      Illegal value.           */
+    EIO,    /* ERR_ARG  -8      Illegal argument.        */
+    EHOSTUNREACH,  /* ERR_RTE  -9      Routing problem.         */
+    EADDRINUSE    /* ERR_USE  -10     Address in use.          */
+};
+
+#define err_to_errno(err) \
+  ((err) < (sizeof(err_to_errno_table)/sizeof(int))) ? \
+    err_to_errno_table[-(err)] : EIO
+
+#ifdef ERRNO
+#define set_errno(err) errno = (err)
+#else
+#define set_errno(err)
+#endif
+
+#define sock_set_errno(sk, e) do { \
+      sk->err = (e); \
+      set_errno(sk->err); \
+} while (0)
+
+
+static struct lwip_socket *
+get_socket(int s)
+{
+  struct lwip_socket *sock;
+
+  if ((s < 0) || (s > NUM_SOCKETS)) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("get_socket(%d): invalid\n", s));
+    set_errno(EBADF);
+    return NULL;
+  }
+
+  sock = &sockets[s];
+
+  if (!sock->conn) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("get_socket(%d): not active\n", s));
+    set_errno(EBADF);
+    return NULL;
+  }
+
+  return sock;
+}
+
+static int
+alloc_socket(struct netconn *newconn)
+{
+  int i;
+
+  if (!socksem)
+      socksem = sys_sem_new(1);
+
+  /* Protect socket array */
+  sys_sem_wait(socksem);
+
+  /* allocate a new socket identifier */
+  for(i = 0; i < NUM_SOCKETS; ++i) {
+    if (!sockets[i].conn) {
+      sockets[i].conn = newconn;
+      sockets[i].lastdata = NULL;
+      sockets[i].lastoffset = 0;
+      sockets[i].rcvevent = 0;
+      sockets[i].sendevent = 1; /* TCP send buf is empty */
+      sockets[i].flags = 0;
+      sockets[i].err = 0;
+      sys_sem_signal(socksem);
+      return i;
+    }
+  }
+  sys_sem_signal(socksem);
+  return -1;
+}
+
+int
+lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen)
+{
+  struct lwip_socket *sock;
+  struct netconn *newconn;
+  struct ip_addr naddr;
+  u16_t port;
+  int newsock;
+  struct sockaddr_in sin;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d)...\n", s));
+  sock = get_socket(s);
+  if (!sock) {
+    set_errno(EBADF);
+    return -1;
+  }
+
+  newconn = netconn_accept(sock->conn);
+
+  /* get the IP address and port of the remote host */
+  netconn_peer(newconn, &naddr, &port);
+
+  memset(&sin, 0, sizeof(sin));
+  sin.sin_len = sizeof(sin);
+  sin.sin_family = AF_INET;
+  sin.sin_port = htons(port);
+  sin.sin_addr.s_addr = naddr.addr;
+
+  if (*addrlen > sizeof(sin))
+      *addrlen = sizeof(sin);
+
+  memcpy(addr, &sin, *addrlen);
+
+  newsock = alloc_socket(newconn);
+  if (newsock == -1) {
+    netconn_delete(newconn);
+  sock_set_errno(sock, ENOBUFS);
+  return -1;
+  }
+  newconn->callback = event_callback;
+  sock = get_socket(newsock);
+
+  sys_sem_wait(socksem);
+  sock->rcvevent += -1 - newconn->socket;
+  newconn->socket = newsock;
+  sys_sem_signal(socksem);
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d) returning new sock=%d addr=", s, newsock));
+  ip_addr_debug_print(SOCKETS_DEBUG, &naddr);
+  LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u\n", port));
+
+  sock_set_errno(sock, 0);
+  return newsock;
+}
+
+int
+lwip_bind(int s, struct sockaddr *name, socklen_t namelen)
+{
+  struct lwip_socket *sock;
+  struct ip_addr local_addr;
+  u16_t local_port;
+  err_t err;
+
+  sock = get_socket(s);
+  if (!sock) {
+    set_errno(EBADF);
+    return -1;
+  }
+
+  local_addr.addr = ((struct sockaddr_in *)name)->sin_addr.s_addr;
+  local_port = ((struct sockaddr_in *)name)->sin_port;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d, addr=", s));
+  ip_addr_debug_print(SOCKETS_DEBUG, &local_addr);
+  LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u)\n", ntohs(local_port)));
+
+  err = netconn_bind(sock->conn, &local_addr, ntohs(local_port));
+
+  if (err != ERR_OK) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d) failed, err=%d\n", s, err));
+    sock_set_errno(sock, err_to_errno(err));
+    return -1;
+  }
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d) succeeded\n", s));
+  sock_set_errno(sock, 0);
+  return 0;
+}
+
+int
+lwip_close(int s)
+{
+  struct lwip_socket *sock;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_close(%d)\n", s));
+  if (!socksem)
+      socksem = sys_sem_new(1);
+
+  /* We cannot allow multiple closes of the same socket. */
+  sys_sem_wait(socksem);
+
+  sock = get_socket(s);
+  if (!sock) {
+      sys_sem_signal(socksem);
+      set_errno(EBADF);
+      return -1;
+  }
+
+  netconn_delete(sock->conn);
+  if (sock->lastdata) {
+    netbuf_delete(sock->lastdata);
+  }
+  sock->lastdata = NULL;
+  sock->lastoffset = 0;
+  sock->conn = NULL;
+  sys_sem_signal(socksem);
+  sock_set_errno(sock, 0);
+  return 0;
+}
+
+int
+lwip_connect(int s, struct sockaddr *name, socklen_t namelen)
+{
+  struct lwip_socket *sock;
+  err_t err;
+
+  sock = get_socket(s);
+  if (!sock) {
+    set_errno(EBADF);
+    return -1;
+  }
+
+  if (((struct sockaddr_in *)name)->sin_family == AF_UNSPEC) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d, AF_UNSPEC)\n", s));
+    err = netconn_disconnect(sock->conn);
+  } else {
+    struct ip_addr remote_addr;
+    u16_t remote_port;
+
+    remote_addr.addr = ((struct sockaddr_in *)name)->sin_addr.s_addr;
+    remote_port = ((struct sockaddr_in *)name)->sin_port;
+
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d, addr=", s));
+    ip_addr_debug_print(SOCKETS_DEBUG, &remote_addr);
+    LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u)\n", ntohs(remote_port)));
+
+    err = netconn_connect(sock->conn, &remote_addr, ntohs(remote_port));
+   }
+
+  if (err != ERR_OK) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d) failed, err=%d\n", s, err));
+    sock_set_errno(sock, err_to_errno(err));
+    return -1;
+  }
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d) succeeded\n", s));
+  sock_set_errno(sock, 0);
+  return 0;
+}
+
+int
+lwip_listen(int s, int backlog)
+{
+  struct lwip_socket *sock;
+  err_t err;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_listen(%d, backlog=%d)\n", s, backlog));
+  sock = get_socket(s);
+  if (!sock) {
+    set_errno(EBADF);
+    return -1;
+  }
+
+  err = netconn_listen(sock->conn);
+
+  if (err != ERR_OK) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_listen(%d) failed, err=%d\n", s, err));
+    sock_set_errno(sock, err_to_errno(err));
+    return -1;
+  }
+
+  sock_set_errno(sock, 0);
+  return 0;
+}
+
+int
+lwip_recvfrom(int s, void *mem, int len, unsigned int flags,
+        struct sockaddr *from, socklen_t *fromlen)
+{
+  struct lwip_socket *sock;
+  struct netbuf *buf;
+  u16_t buflen, copylen;
+  struct ip_addr *addr;
+  u16_t port;
+
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d, %p, %d, 0x%x, ..)\n", s, mem, len, flags));
+  sock = get_socket(s);
+  if (!sock) {
+    set_errno(EBADF);
+    return -1;
+  }
+
+  /* Check if there is data left from the last recv operation. */
+  if (sock->lastdata) {
+    buf = sock->lastdata;
+  } else {
+    /* If this is non-blocking call, then check first */
+    if (((flags & MSG_DONTWAIT) || (sock->flags & O_NONBLOCK))
+  && !sock->rcvevent)
+    {
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): returning EWOULDBLOCK\n", s));
+      sock_set_errno(sock, EWOULDBLOCK);
+      return -1;
+    }
+
+    /* No data was left from the previous operation, so we try to get
+       some from the network. */
+    buf = netconn_recv(sock->conn);
+
+    if (!buf) {
+      /* We should really do some error checking here. */
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): buf == NULL!\n", s));
+      sock_set_errno(sock, 0);
+      return 0;
+    }
+  }
+
+  buflen = netbuf_len(buf);
+
+  buflen -= sock->lastoffset;
+
+  if (len > buflen) {
+    copylen = buflen;
+  } else {
+    copylen = len;
+  }
+
+  /* copy the contents of the received buffer into
+     the supplied memory pointer mem */
+  netbuf_copy_partial(buf, mem, copylen, sock->lastoffset);
+
+  /* Check to see from where the data was. */
+  if (from && fromlen) {
+    struct sockaddr_in sin;
+
+    addr = netbuf_fromaddr(buf);
+    port = netbuf_fromport(buf);
+
+    memset(&sin, 0, sizeof(sin));
+    sin.sin_len = sizeof(sin);
+    sin.sin_family = AF_INET;
+    sin.sin_port = htons(port);
+    sin.sin_addr.s_addr = addr->addr;
+
+    if (*fromlen > sizeof(sin))
+      *fromlen = sizeof(sin);
+
+    memcpy(from, &sin, *fromlen);
+
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): addr=", s));
+    ip_addr_debug_print(SOCKETS_DEBUG, addr);
+    LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u len=%u\n", port, copylen));
+  } else {
+#if SOCKETS_DEBUG
+    addr = netbuf_fromaddr(buf);
+    port = netbuf_fromport(buf);
+
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): addr=", s));
+    ip_addr_debug_print(SOCKETS_DEBUG, addr);
+    LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u len=%u\n", port, copylen));
+#endif
+
+  }
+
+  /* If this is a TCP socket, check if there is data left in the
+     buffer. If so, it should be saved in the sock structure for next
+     time around. */
+  if (netconn_type(sock->conn) == NETCONN_TCP && buflen - copylen > 0) {
+    sock->lastdata = buf;
+    sock->lastoffset += copylen;
+  } else {
+    sock->lastdata = NULL;
+    sock->lastoffset = 0;
+    netbuf_delete(buf);
+  }
+
+
+  sock_set_errno(sock, 0);
+  return copylen;
+}
+
+int
+lwip_read(int s, void *mem, int len)
+{
+  return lwip_recvfrom(s, mem, len, 0, NULL, NULL);
+}
+
+int
+lwip_recv(int s, void *mem, int len, unsigned int flags)
+{
+  return lwip_recvfrom(s, mem, len, flags, NULL, NULL);
+}
+
+int
+lwip_send(int s, void *data, int size, unsigned int flags)
+{
+  struct lwip_socket *sock;
+  struct netbuf *buf;
+  err_t err;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d, data=%p, size=%d, flags=0x%x)\n", s, data, size, flags));
+
+  sock = get_socket(s);
+  if (!sock) {
+    set_errno(EBADF);
+    return -1;
+  }
+
+  switch (netconn_type(sock->conn)) {
+  case NETCONN_RAW:
+  case NETCONN_UDP:
+  case NETCONN_UDPLITE:
+  case NETCONN_UDPNOCHKSUM:
+    /* create a buffer */
+    buf = netbuf_new();
+
+    if (!buf) {
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d) ENOBUFS\n", s));
+      sock_set_errno(sock, ENOBUFS);
+      return -1;
+    }
+
+    /* make the buffer point to the data that should
+       be sent */
+    netbuf_ref(buf, data, size);
+
+    /* send the data */
+    err = netconn_send(sock->conn, buf);
+
+    /* deallocated the buffer */
+    netbuf_delete(buf);
+    break;
+  case NETCONN_TCP:
+    err = netconn_write(sock->conn, data, size, NETCONN_COPY);
+    break;
+  default:
+    err = ERR_ARG;
+    break;
+  }
+  if (err != ERR_OK) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d) err=%d\n", s, err));
+    sock_set_errno(sock, err_to_errno(err));
+    return -1;
+  }
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d) ok size=%d\n", s, size));
+  sock_set_errno(sock, 0);
+  return size;
+}
+
+int
+lwip_sendto(int s, void *data, int size, unsigned int flags,
+       struct sockaddr *to, socklen_t tolen)
+{
+  struct lwip_socket *sock;
+  struct ip_addr remote_addr, addr;
+  u16_t remote_port, port;
+  int ret,connected;
+
+  sock = get_socket(s);
+  if (!sock) {
+    set_errno(EBADF);
+    return -1;
+  }
+
+  /* get the peer if currently connected */
+  connected = (netconn_peer(sock->conn, &addr, &port) == ERR_OK);
+
+  remote_addr.addr = ((struct sockaddr_in *)to)->sin_addr.s_addr;
+  remote_port = ((struct sockaddr_in *)to)->sin_port;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_sendto(%d, data=%p, size=%d, flags=0x%x to=", s, data, size, flags));
+  ip_addr_debug_print(SOCKETS_DEBUG, &remote_addr);
+  LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u\n", ntohs(remote_port)));
+
+  netconn_connect(sock->conn, &remote_addr, ntohs(remote_port));
+
+  ret = lwip_send(s, data, size, flags);
+
+  /* reset the remote address and port number
+     of the connection */
+  if (connected)
+    netconn_connect(sock->conn, &addr, port);
+  else
+  netconn_disconnect(sock->conn);
+  return ret;
+}
+
+int
+lwip_socket(int domain, int type, int protocol)
+{
+  struct netconn *conn;
+  int i;
+
+  /* create a netconn */
+  switch (type) {
+  case SOCK_RAW:
+    conn = netconn_new_with_proto_and_callback(NETCONN_RAW, protocol, event_callback);
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_RAW, %d) = ", domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol));
+    break;
+  case SOCK_DGRAM:
+    conn = netconn_new_with_callback(NETCONN_UDP, event_callback);
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_DGRAM, %d) = ", domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol));
+    break;
+  case SOCK_STREAM:
+    conn = netconn_new_with_callback(NETCONN_TCP, event_callback);
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_STREAM, %d) = ", domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol));
+    break;
+  default:
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%d, %d/UNKNOWN, %d) = -1\n", domain, type, protocol));
+    set_errno(EINVAL);
+    return -1;
+  }
+
+  if (!conn) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("-1 / ENOBUFS (could not create netconn)\n"));
+    set_errno(ENOBUFS);
+    return -1;
+  }
+
+  i = alloc_socket(conn);
+
+  if (i == -1) {
+    netconn_delete(conn);
+  set_errno(ENOBUFS);
+  return -1;
+  }
+  conn->socket = i;
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("%d\n", i));
+  set_errno(0);
+  return i;
+}
+
+int
+lwip_write(int s, void *data, int size)
+{
+   return lwip_send(s, data, size, 0);
+}
+
+
+static int
+lwip_selscan(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset)
+{
+    int i, nready = 0;
+    fd_set lreadset, lwriteset, lexceptset;
+    struct lwip_socket *p_sock;
+
+    FD_ZERO(&lreadset);
+    FD_ZERO(&lwriteset);
+    FD_ZERO(&lexceptset);
+
+    /* Go through each socket in each list to count number of sockets which
+       currently match */
+    for(i = 0; i < maxfdp1; i++)
+    {
+        if (FD_ISSET(i, readset))
+        {
+            /* See if netconn of this socket is ready for read */
+            p_sock = get_socket(i);
+            if (p_sock && (p_sock->lastdata || p_sock->rcvevent))
+            {
+                FD_SET(i, &lreadset);
+		LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_selscan: fd=%d ready for reading\n", i));
+                nready++;
+            }
+        }
+        if (FD_ISSET(i, writeset))
+        {
+            /* See if netconn of this socket is ready for write */
+            p_sock = get_socket(i);
+            if (p_sock && p_sock->sendevent)
+            {
+                FD_SET(i, &lwriteset);
+		LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_selscan: fd=%d ready for writing\n", i));
+                nready++;
+            }
+        }
+    }
+    *readset = lreadset;
+    *writeset = lwriteset;
+    FD_ZERO(exceptset);
+
+    return nready;
+}
+
+
+
+int
+lwip_select(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset,
+               struct timeval *timeout)
+{
+    int i;
+    int nready;
+    fd_set lreadset, lwriteset, lexceptset;
+    u32_t msectimeout;
+    struct lwip_select_cb select_cb;
+    struct lwip_select_cb *p_selcb;
+
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select(%d, %p, %p, %p, tvsec=%ld tvusec=%ld)\n", maxfdp1, (void *)readset, (void *) writeset, (void *) exceptset, timeout ? timeout->tv_sec : -1L, timeout ? timeout->tv_usec : -1L));
+
+    select_cb.next = 0;
+    select_cb.readset = readset;
+    select_cb.writeset = writeset;
+    select_cb.exceptset = exceptset;
+    select_cb.sem_signalled = 0;
+
+    /* Protect ourselves searching through the list */
+    if (!selectsem)
+        selectsem = sys_sem_new(1);
+    sys_sem_wait(selectsem);
+
+    if (readset)
+        lreadset = *readset;
+    else
+        FD_ZERO(&lreadset);
+    if (writeset)
+        lwriteset = *writeset;
+    else
+        FD_ZERO(&lwriteset);
+    if (exceptset)
+        lexceptset = *exceptset;
+    else
+        FD_ZERO(&lexceptset);
+
+    /* Go through each socket in each list to count number of sockets which
+       currently match */
+    nready = lwip_selscan(maxfdp1, &lreadset, &lwriteset, &lexceptset);
+
+    /* If we don't have any current events, then suspend if we are supposed to */
+    if (!nready)
+    {
+        if (timeout && timeout->tv_sec == 0 && timeout->tv_usec == 0)
+        {
+            sys_sem_signal(selectsem);
+            if (readset)
+                FD_ZERO(readset);
+            if (writeset)
+                FD_ZERO(writeset);
+            if (exceptset)
+                FD_ZERO(exceptset);
+
+	    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: no timeout, returning 0\n"));
+	    set_errno(0);
+
+            return 0;
+        }
+
+        /* add our semaphore to list */
+        /* We don't actually need any dynamic memory. Our entry on the
+         * list is only valid while we are in this function, so it's ok
+         * to use local variables */
+
+        select_cb.sem = sys_sem_new(0);
+        /* Note that we are still protected */
+        /* Put this select_cb on top of list */
+        select_cb.next = select_cb_list;
+        select_cb_list = &select_cb;
+
+        /* Now we can safely unprotect */
+        sys_sem_signal(selectsem);
+
+        /* Now just wait to be woken */
+        if (timeout == 0)
+            /* Wait forever */
+            msectimeout = 0;
+        else
+            msectimeout =  ((timeout->tv_sec * 1000) + ((timeout->tv_usec + 500)/1000));
+
+        i = sys_sem_wait_timeout(select_cb.sem, msectimeout);
+
+        /* Take us off the list */
+        sys_sem_wait(selectsem);
+        if (select_cb_list == &select_cb)
+            select_cb_list = select_cb.next;
+        else
+            for (p_selcb = select_cb_list; p_selcb; p_selcb = p_selcb->next)
+                if (p_selcb->next == &select_cb)
+                {
+                    p_selcb->next = select_cb.next;
+                    break;
+                }
+
+        sys_sem_signal(selectsem);
+
+        sys_sem_free(select_cb.sem);
+        if (i == 0)             /* Timeout */
+        {
+            if (readset)
+                FD_ZERO(readset);
+            if (writeset)
+                FD_ZERO(writeset);
+            if (exceptset)
+                FD_ZERO(exceptset);
+
+	    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: timeout expired\n"));
+	    set_errno(0);
+
+            return 0;
+        }
+
+        if (readset)
+            lreadset = *readset;
+        else
+            FD_ZERO(&lreadset);
+        if (writeset)
+            lwriteset = *writeset;
+        else
+            FD_ZERO(&lwriteset);
+        if (exceptset)
+            lexceptset = *exceptset;
+        else
+            FD_ZERO(&lexceptset);
+
+        /* See what's set */
+        nready = lwip_selscan(maxfdp1, &lreadset, &lwriteset, &lexceptset);
+    }
+    else
+        sys_sem_signal(selectsem);
+
+    if (readset)
+        *readset = lreadset;
+    if (writeset)
+        *writeset = lwriteset;
+    if (exceptset)
+        *exceptset = lexceptset;
+
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: nready=%d\n", nready));
+    set_errno(0);
+
+    return nready;
+}
+
+
+static void
+event_callback(struct netconn *conn, enum netconn_evt evt, u16_t len)
+{
+    int s;
+    struct lwip_socket *sock;
+    struct lwip_select_cb *scb;
+
+    /* Get socket */
+    if (conn)
+    {
+        s = conn->socket;
+        if (s < 0)
+        {
+            /* Data comes in right away after an accept, even though
+             * the server task might not have created a new socket yet.
+             * Just count down (or up) if that's the case and we
+             * will use the data later. Note that only receive events
+             * can happen before the new socket is set up. */
+            if (evt == NETCONN_EVT_RCVPLUS)
+                conn->socket--;
+            return;
+        }
+
+        sock = get_socket(s);
+        if (!sock)
+            return;
+    }
+    else
+        return;
+
+    if (!selectsem)
+        selectsem = sys_sem_new(1);
+
+    sys_sem_wait(selectsem);
+    /* Set event as required */
+    switch (evt)
+    {
+      case NETCONN_EVT_RCVPLUS:
+        sock->rcvevent++;
+        break;
+      case NETCONN_EVT_RCVMINUS:
+        sock->rcvevent--;
+        break;
+      case NETCONN_EVT_SENDPLUS:
+        sock->sendevent = 1;
+        break;
+      case NETCONN_EVT_SENDMINUS:
+        sock->sendevent = 0;
+        break;
+    }
+    sys_sem_signal(selectsem);
+
+    /* Now decide if anyone is waiting for this socket */
+    /* NOTE: This code is written this way to protect the select link list
+       but to avoid a deadlock situation by releasing socksem before
+       signalling for the select. This means we need to go through the list
+       multiple times ONLY IF a select was actually waiting. We go through
+       the list the number of waiting select calls + 1. This list is
+       expected to be small. */
+    while (1)
+    {
+        sys_sem_wait(selectsem);
+        for (scb = select_cb_list; scb; scb = scb->next)
+        {
+            if (scb->sem_signalled == 0)
+            {
+                /* Test this select call for our socket */
+                if (scb->readset && FD_ISSET(s, scb->readset))
+                    if (sock->rcvevent)
+                        break;
+                if (scb->writeset && FD_ISSET(s, scb->writeset))
+                    if (sock->sendevent)
+                        break;
+            }
+        }
+        if (scb)
+        {
+            scb->sem_signalled = 1;
+            sys_sem_signal(selectsem);
+            sys_sem_signal(scb->sem);
+        } else {
+            sys_sem_signal(selectsem);
+            break;
+        }
+    }
+
+}
+
+
+
+
+int lwip_shutdown(int s, int how)
+{
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_shutdown(%d, how=%d)\n", s, how));
+  return lwip_close(s); /* XXX temporary hack until proper implementation */
+}
+
+int lwip_getpeername (int s, struct sockaddr *name, socklen_t *namelen)
+{
+  struct lwip_socket *sock;
+  struct sockaddr_in sin;
+  struct ip_addr naddr;
+
+  sock = get_socket(s);
+  if (!sock) {
+    set_errno(EBADF);
+    return -1;
+  }
+
+  memset(&sin, 0, sizeof(sin));
+  sin.sin_len = sizeof(sin);
+  sin.sin_family = AF_INET;
+
+  /* get the IP address and port of the remote host */
+  netconn_peer(sock->conn, &naddr, &sin.sin_port);
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getpeername(%d, addr=", s));
+  ip_addr_debug_print(SOCKETS_DEBUG, &naddr);
+  LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%d)\n", sin.sin_port));
+
+  sin.sin_port = htons(sin.sin_port);
+  sin.sin_addr.s_addr = naddr.addr;
+
+  if (*namelen > sizeof(sin))
+      *namelen = sizeof(sin);
+
+  memcpy(name, &sin, *namelen);
+  sock_set_errno(sock, 0);
+  return 0;
+}
+
+int lwip_getsockname (int s, struct sockaddr *name, socklen_t *namelen)
+{
+  struct lwip_socket *sock;
+  struct sockaddr_in sin;
+  struct ip_addr *naddr;
+
+  sock = get_socket(s);
+  if (!sock) {
+    set_errno(EBADF);
+    return -1;
+  }
+
+  memset(&sin, 0, sizeof(sin));
+  sin.sin_len = sizeof(sin);
+  sin.sin_family = AF_INET;
+
+  /* get the IP address and port of the remote host */
+  netconn_addr(sock->conn, &naddr, &sin.sin_port);
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockname(%d, addr=", s));
+  ip_addr_debug_print(SOCKETS_DEBUG, naddr);
+  LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%d)\n", sin.sin_port));
+
+  sin.sin_port = htons(sin.sin_port);
+  sin.sin_addr.s_addr = naddr->addr;
+
+  if (*namelen > sizeof(sin))
+      *namelen = sizeof(sin);
+
+  memcpy(name, &sin, *namelen);
+  sock_set_errno(sock, 0);
+  return 0;
+}
+
+int lwip_getsockopt (int s, int level, int optname, void *optval, socklen_t *optlen)
+{
+  int err = 0;
+  struct lwip_socket *sock = get_socket(s);
+
+  if(!sock) {
+   	set_errno(EBADF);
+    return -1;
+  }
+
+  if( NULL == optval || NULL == optlen ) {
+    sock_set_errno( sock, EFAULT );
+    return -1;
+  }
+
+  /* Do length and type checks for the various options first, to keep it readable. */
+  switch( level ) {
+   
+/* Level: SOL_SOCKET */
+  case SOL_SOCKET:
+      switch(optname) {
+         
+      case SO_ACCEPTCONN:
+      case SO_BROADCAST:
+      /* UNIMPL case SO_DEBUG: */
+      /* UNIMPL case SO_DONTROUTE: */
+      case SO_ERROR:
+      case SO_KEEPALIVE:
+      /* UNIMPL case SO_OOBINLINE: */
+      /* UNIMPL case SO_RCVBUF: */
+      /* UNIMPL case SO_SNDBUF: */
+      /* UNIMPL case SO_RCVLOWAT: */
+      /* UNIMPL case SO_SNDLOWAT: */
+#if SO_REUSE
+      case SO_REUSEADDR:
+      case SO_REUSEPORT:
+#endif /* SO_REUSE */
+      case SO_TYPE:
+      /* UNIMPL case SO_USELOOPBACK: */
+        if( *optlen < sizeof(int) ) {
+          err = EINVAL;
+        }
+          break;
+
+      default:
+        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, UNIMPL: optname=0x%x, ..)\n", s, optname));
+        err = ENOPROTOOPT;
+      }  /* switch */
+      break;
+                     
+/* Level: IPPROTO_IP */
+  case IPPROTO_IP:
+      switch(optname) {
+      /* UNIMPL case IP_HDRINCL: */
+      /* UNIMPL case IP_RCVDSTADDR: */
+      /* UNIMPL case IP_RCVIF: */
+      case IP_TTL:
+      case IP_TOS:
+        if( *optlen < sizeof(int) ) {
+          err = EINVAL;
+        }
+        break;
+
+      default:
+        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, UNIMPL: optname=0x%x, ..)\n", s, optname));
+        err = ENOPROTOOPT;
+      }  /* switch */
+      break;
+         
+/* Level: IPPROTO_TCP */
+  case IPPROTO_TCP:
+      if( *optlen < sizeof(int) ) {
+        err = EINVAL;
+        break;
+    }
+      
+      /* If this is no TCP socket, ignore any options. */
+      if ( sock->conn->type != NETCONN_TCP ) return 0;
+
+      switch( optname ) {
+      case TCP_NODELAY:
+      case TCP_KEEPALIVE:
+        break;
+         
+      default:
+        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, UNIMPL: optname=0x%x, ..)\n", s, optname));
+        err = ENOPROTOOPT;
+      }  /* switch */
+      break;
+
+/* UNDEFINED LEVEL */
+  default:
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, level=0x%x, UNIMPL: optname=0x%x, ..)\n", s, level, optname));
+      err = ENOPROTOOPT;
+  }  /* switch */
+
+   
+  if( 0 != err ) {
+    sock_set_errno(sock, err);
+    return -1;
+  }
+   
+
+
+  /* Now do the actual option processing */
+
+  switch(level) {
+   
+/* Level: SOL_SOCKET */
+  case SOL_SOCKET:
+    switch( optname ) {
+
+    /* The option flags */
+    case SO_ACCEPTCONN:
+    case SO_BROADCAST:
+    /* UNIMPL case SO_DEBUG: */
+    /* UNIMPL case SO_DONTROUTE: */
+    case SO_KEEPALIVE:
+    /* UNIMPL case SO_OOBINCLUDE: */
+#if SO_REUSE
+    case SO_REUSEADDR:
+    case SO_REUSEPORT:
+#endif /* SO_REUSE */
+    /*case SO_USELOOPBACK: UNIMPL */
+      *(int*)optval = sock->conn->pcb.tcp->so_options & optname;
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, optname=0x%x, ..) = %s\n", s, optname, (*(int*)optval?"on":"off")));
+      break;
+
+    case SO_TYPE:
+      switch (sock->conn->type) {
+      case NETCONN_RAW:
+        *(int*)optval = SOCK_RAW;
+        break;
+      case NETCONN_TCP:
+        *(int*)optval = SOCK_STREAM;
+        break;
+      case NETCONN_UDP:
+      case NETCONN_UDPLITE:
+      case NETCONN_UDPNOCHKSUM:
+        *(int*)optval = SOCK_DGRAM;
+        break;
+      default: /* unrecognized socket type */
+        *(int*)optval = sock->conn->type;
+        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_TYPE): unrecognized socket type %d\n", s, *(int *)optval));
+      }  /* switch */
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_TYPE) = %d\n", s, *(int *)optval));
+      break;
+
+    case SO_ERROR:
+      *(int *)optval = sock->err;
+      sock->err = 0;
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_ERROR) = %d\n", s, *(int *)optval));
+      break;
+    }  /* switch */
+    break;
+
+/* Level: IPPROTO_IP */
+  case IPPROTO_IP:
+    switch( optname ) {
+    case IP_TTL:
+      *(int*)optval = sock->conn->pcb.tcp->ttl;
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_TTL) = %d\n", s, *(int *)optval));
+      break;
+    case IP_TOS:
+      *(int*)optval = sock->conn->pcb.tcp->tos;
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_TOS) = %d\n", s, *(int *)optval));
+      break;
+    }  /* switch */
+    break;
+
+/* Level: IPPROTO_TCP */
+  case IPPROTO_TCP:
+    switch( optname ) {
+    case TCP_NODELAY:
+      *(int*)optval = (sock->conn->pcb.tcp->flags & TF_NODELAY);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, TCP_NODELAY) = %s\n", s, (*(int*)optval)?"on":"off") );
+      break;
+    case TCP_KEEPALIVE:
+      *(int*)optval = (int)sock->conn->pcb.tcp->keepalive;
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, TCP_KEEPALIVE) = %d\n", s, *(int *)optval));
+      break;
+    }  /* switch */
+    break;
+  }
+
+
+  sock_set_errno(sock, err);
+  return err ? -1 : 0;
+}
+
+int lwip_setsockopt (int s, int level, int optname, const void *optval, socklen_t optlen)
+{
+  struct lwip_socket *sock = get_socket(s);
+  int err = 0;
+
+  if(!sock) {
+   	set_errno(EBADF);
+    return -1;
+  }
+
+  if( NULL == optval ) {
+    sock_set_errno( sock, EFAULT );
+    return -1;
+  }
+
+
+  /* Do length and type checks for the various options first, to keep it readable. */
+  switch( level ) {
+
+/* Level: SOL_SOCKET */
+  case SOL_SOCKET:
+    switch(optname) {
+
+    case SO_BROADCAST:
+    /* UNIMPL case SO_DEBUG: */
+    /* UNIMPL case SO_DONTROUTE: */
+    case SO_KEEPALIVE:
+    /* UNIMPL case SO_OOBINLINE: */
+    /* UNIMPL case SO_RCVBUF: */
+    /* UNIMPL case SO_SNDBUF: */
+    /* UNIMPL case SO_RCVLOWAT: */
+    /* UNIMPL case SO_SNDLOWAT: */
+#if SO_REUSE
+    case SO_REUSEADDR:
+    case SO_REUSEPORT:
+#endif /* SO_REUSE */
+    /* UNIMPL case SO_USELOOPBACK: */
+      if( optlen < sizeof(int) ) {
+        err = EINVAL;
+      }
+      break;
+    default:
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, SOL_SOCKET, UNIMPL: optname=0x%x, ..)\n", s, optname));
+      err = ENOPROTOOPT;
+    }  /* switch */
+    break;
+
+/* Level: IPPROTO_IP */
+  case IPPROTO_IP:
+    switch(optname) {
+    /* UNIMPL case IP_HDRINCL: */
+    /* UNIMPL case IP_RCVDSTADDR: */
+    /* UNIMPL case IP_RCVIF: */
+    case IP_TTL:
+    case IP_TOS:
+      if( optlen < sizeof(int) ) {
+        err = EINVAL;
+      }
+        break;
+      default:
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, UNIMPL: optname=0x%x, ..)\n", s, optname));
+      err = ENOPROTOOPT;
+    }  /* switch */
+    break;
+
+/* Level: IPPROTO_TCP */
+  case IPPROTO_TCP:
+    if( optlen < sizeof(int) ) {
+      err = EINVAL;
+        break;
+    }
+
+    /* If this is no TCP socket, ignore any options. */
+    if ( sock->conn->type != NETCONN_TCP ) return 0;
+
+    switch( optname ) {
+    case TCP_NODELAY:
+    case TCP_KEEPALIVE:
+      break;
+
+    default:
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, UNIMPL: optname=0x%x, ..)\n", s, optname));
+      err = ENOPROTOOPT;
+    }  /* switch */
+    break;
+
+/* UNDEFINED LEVEL */      
+  default:
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, level=0x%x, UNIMPL: optname=0x%x, ..)\n", s, level, optname));
+    err = ENOPROTOOPT;
+  }  /* switch */
+
+
+  if( 0 != err ) {
+    sock_set_errno(sock, err);
+    return -1;
+  }
+
+
+
+  /* Now do the actual option processing */
+
+  switch(level) {
+
+/* Level: SOL_SOCKET */
+  case SOL_SOCKET:
+    switch(optname) {
+
+    /* The option flags */
+    case SO_BROADCAST:
+    /* UNIMPL case SO_DEBUG: */
+    /* UNIMPL case SO_DONTROUTE: */
+    case SO_KEEPALIVE:
+    /* UNIMPL case SO_OOBINCLUDE: */
+#if SO_REUSE
+    case SO_REUSEADDR:
+    case SO_REUSEPORT:
+#endif /* SO_REUSE */
+    /* UNIMPL case SO_USELOOPBACK: */
+      if ( *(int*)optval ) {
+        sock->conn->pcb.tcp->so_options |= optname;
+      } else {
+        sock->conn->pcb.tcp->so_options &= ~optname;
+      }
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, SOL_SOCKET, optname=0x%x, ..) -> %s\n", s, optname, (*(int*)optval?"on":"off")));
+      break;
+    }  /* switch */
+    break;
+
+/* Level: IPPROTO_IP */
+  case IPPROTO_IP:
+    switch( optname ) {
+    case IP_TTL:
+      sock->conn->pcb.tcp->ttl = (u8_t)(*(int*)optval);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, IP_TTL, ..) -> %u\n", s, sock->conn->pcb.tcp->ttl));
+      break;
+    case IP_TOS:
+      sock->conn->pcb.tcp->tos = (u8_t)(*(int*)optval);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, IP_TOS, ..)-> %u\n", s, sock->conn->pcb.tcp->tos));
+      break;
+    }  /* switch */
+    break;
+
+/* Level: IPPROTO_TCP */
+  case IPPROTO_TCP:
+    switch( optname ) {
+    case TCP_NODELAY:
+      if ( *(int*)optval ) {
+        sock->conn->pcb.tcp->flags |= TF_NODELAY;
+      } else {
+        sock->conn->pcb.tcp->flags &= ~TF_NODELAY;
+      }
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_NODELAY) -> %s\n", s, (*(int *)optval)?"on":"off") );
+      break;
+    case TCP_KEEPALIVE:
+      sock->conn->pcb.tcp->keepalive = (u32_t)(*(int*)optval);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPALIVE) -> %lu\n", s, sock->conn->pcb.tcp->keepalive));
+      break;
+    }  /* switch */
+    break;
+  }  /* switch */
+
+  sock_set_errno(sock, err);
+  return err ? -1 : 0;
+}
+
+int lwip_ioctl(int s, long cmd, void *argp)
+{
+  struct lwip_socket *sock = get_socket(s);
+
+  if(!sock) {
+   	set_errno(EBADF);
+    return -1;
+  }
+
+  switch (cmd) {
+  case FIONREAD:
+    if (!argp) {
+      sock_set_errno(sock, EINVAL);
+      return -1;
+    }
+
+    *((u16_t*)argp) = sock->conn->recv_avail;
+
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, FIONREAD, %p) = %u\n", s, argp, *((u16_t*)argp)));
+    sock_set_errno(sock, 0);
+    return 0;
+
+  case FIONBIO:
+    if (argp && *(u32_t*)argp)
+      sock->flags |= O_NONBLOCK;
+    else
+      sock->flags &= ~O_NONBLOCK;
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, FIONBIO, %d)\n", s, !!(sock->flags & O_NONBLOCK)));
+    sock_set_errno(sock, 0);
+    return 0;
+
+  default:
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, UNIMPL: 0x%lx, %p)\n", s, cmd, argp));
+    sock_set_errno(sock, ENOSYS); /* not yet implemented */
+    return -1;
+  }
+}
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/api/tcpip.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/api/tcpip.c
new file mode 100644
index 000000000..c580bddf9
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/api/tcpip.c
@@ -0,0 +1,184 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/sys.h"
+
+#include "lwip/memp.h"
+#include "lwip/pbuf.h"
+
+#include "lwip/ip.h"
+#include "lwip/udp.h"
+#include "lwip/tcp.h"
+
+#include "lwip/tcpip.h"
+
+static void (* tcpip_init_done)(void *arg) = NULL;
+static void *tcpip_init_done_arg;
+static sys_mbox_t mbox;
+
+#if LWIP_TCP
+static int tcpip_tcp_timer_active = 0;
+
+static void
+tcpip_tcp_timer(void *arg)
+{
+  (void)arg;
+
+  /* call TCP timer handler */
+  tcp_tmr();
+  /* timer still needed? */
+  if (tcp_active_pcbs || tcp_tw_pcbs) {
+    /* restart timer */
+    sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL);
+  } else {
+    /* disable timer */
+    tcpip_tcp_timer_active = 0;
+  }
+}
+
+#if !NO_SYS
+void
+tcp_timer_needed(void)
+{
+  /* timer is off but needed again? */
+  if (!tcpip_tcp_timer_active && (tcp_active_pcbs || tcp_tw_pcbs)) {
+    /* enable and start timer */
+    tcpip_tcp_timer_active = 1;
+    sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL);
+  }
+}
+#endif /* !NO_SYS */
+#endif /* LWIP_TCP */
+
+static void
+tcpip_thread(void *arg)
+{
+  struct tcpip_msg *msg;
+
+  (void)arg;
+
+  ip_init();
+#if LWIP_UDP  
+  udp_init();
+#endif
+#if LWIP_TCP
+  tcp_init();
+#endif
+  if (tcpip_init_done != NULL) {
+    tcpip_init_done(tcpip_init_done_arg);
+  }
+
+  while (1) {                          /* MAIN Loop */
+    sys_mbox_fetch(mbox, (void *)&msg);
+    switch (msg->type) {
+    case TCPIP_MSG_API:
+      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: API message %p\n", (void *)msg));
+      api_msg_input(msg->msg.apimsg);
+      break;
+    case TCPIP_MSG_INPUT:
+      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: IP packet %p\n", (void *)msg));
+      ip_input(msg->msg.inp.p, msg->msg.inp.netif);
+      break;
+    case TCPIP_MSG_CALLBACK:
+      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: CALLBACK %p\n", (void *)msg));
+      msg->msg.cb.f(msg->msg.cb.ctx);
+      break;
+    default:
+      break;
+    }
+    memp_free(MEMP_TCPIP_MSG, msg);
+  }
+}
+
+err_t
+tcpip_input(struct pbuf *p, struct netif *inp)
+{
+  struct tcpip_msg *msg;
+  
+  msg = memp_malloc(MEMP_TCPIP_MSG);
+  if (msg == NULL) {
+    pbuf_free(p);    
+    return ERR_MEM;  
+  }
+  
+  msg->type = TCPIP_MSG_INPUT;
+  msg->msg.inp.p = p;
+  msg->msg.inp.netif = inp;
+  sys_mbox_post(mbox, msg);
+  return ERR_OK;
+}
+
+err_t
+tcpip_callback(void (*f)(void *ctx), void *ctx)
+{
+  struct tcpip_msg *msg;
+  
+  msg = memp_malloc(MEMP_TCPIP_MSG);
+  if (msg == NULL) {
+    return ERR_MEM;  
+  }
+  
+  msg->type = TCPIP_MSG_CALLBACK;
+  msg->msg.cb.f = f;
+  msg->msg.cb.ctx = ctx;
+  sys_mbox_post(mbox, msg);
+  return ERR_OK;
+}
+
+void
+tcpip_apimsg(struct api_msg *apimsg)
+{
+  struct tcpip_msg *msg;
+  msg = memp_malloc(MEMP_TCPIP_MSG);
+  if (msg == NULL) {
+    memp_free(MEMP_API_MSG, apimsg);
+    return;
+  }
+  msg->type = TCPIP_MSG_API;
+  msg->msg.apimsg = apimsg;
+  sys_mbox_post(mbox, msg);
+}
+
+void
+tcpip_init(void (* initfunc)(void *), void *arg)
+{
+  tcpip_init_done = initfunc;
+  tcpip_init_done_arg = arg;
+  mbox = sys_mbox_new();
+  sys_thread_new(tcpip_thread, NULL, TCPIP_THREAD_PRIO);
+}
+
+
+
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/dhcp.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/dhcp.c
new file mode 100644
index 000000000..0caf7d0de
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/dhcp.c
@@ -0,0 +1,1454 @@
+/**
+ * @file
+ *
+ * Dynamic Host Configuration Protocol client
+ */
+
+/*
+ *
+ * Copyright (c) 2001-2004 Leon Woestenberg 
+ * Copyright (c) 2001-2004 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is a contribution to the lwIP TCP/IP stack.
+ * The Swedish Institute of Computer Science and Adam Dunkels
+ * are specifically granted permission to redistribute this
+ * source code.
+ *
+ * Author: Leon Woestenberg 
+ *
+ * This is a DHCP client for the lwIP TCP/IP stack. It aims to conform
+ * with RFC 2131 and RFC 2132.
+ *
+ * TODO:
+ * - Proper parsing of DHCP messages exploiting file/sname field overloading.
+ * - Add JavaDoc style documentation (API, internals).
+ * - Support for interfaces other than Ethernet (SLIP, PPP, ...)
+ *
+ * Please coordinate changes and requests with Leon Woestenberg
+ * 
+ *
+ * Integration with your code:
+ *
+ * In lwip/dhcp.h
+ * #define DHCP_COARSE_TIMER_SECS (recommended 60 which is a minute)
+ * #define DHCP_FINE_TIMER_MSECS (recommended 500 which equals TCP coarse timer)
+ *
+ * Then have your application call dhcp_coarse_tmr() and
+ * dhcp_fine_tmr() on the defined intervals.
+ *
+ * dhcp_start(struct netif *netif);
+ * starts a DHCP client instance which configures the interface by
+ * obtaining an IP address lease and maintaining it.
+ *
+ * Use dhcp_release(netif) to end the lease and use dhcp_stop(netif)
+ * to remove the DHCP client.
+ *
+ */
+ 
+#include 
+ 
+#include "lwip/stats.h"
+#include "lwip/mem.h"
+#include "lwip/udp.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/inet.h"
+#include "netif/etharp.h"
+
+#include "lwip/sys.h"
+#include "lwip/opt.h"
+#include "lwip/dhcp.h"
+
+#if LWIP_DHCP /* don't build if not configured for use in lwipopt.h */
+
+/** global transaction identifier, must be
+ *  unique for each DHCP request. We simply increment, starting
+ *  with this value (easy to match with a packet analyzer) */
+static u32_t xid = 0xABCD0000;
+
+/** DHCP client state machine functions */
+static void dhcp_handle_ack(struct netif *netif);
+static void dhcp_handle_nak(struct netif *netif);
+static void dhcp_handle_offer(struct netif *netif);
+
+static err_t dhcp_discover(struct netif *netif);
+static err_t dhcp_select(struct netif *netif);
+static void dhcp_check(struct netif *netif);
+static void dhcp_bind(struct netif *netif);
+static err_t dhcp_decline(struct netif *netif);
+static err_t dhcp_rebind(struct netif *netif);
+static void dhcp_set_state(struct dhcp *dhcp, unsigned char new_state);
+
+/** receive, unfold, parse and free incoming messages */
+static void dhcp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *addr, u16_t port);
+static err_t dhcp_unfold_reply(struct dhcp *dhcp);
+static u8_t *dhcp_get_option_ptr(struct dhcp *dhcp, u8_t option_type);
+static u8_t dhcp_get_option_byte(u8_t *ptr);
+static u16_t dhcp_get_option_short(u8_t *ptr);
+static u32_t dhcp_get_option_long(u8_t *ptr);
+static void dhcp_free_reply(struct dhcp *dhcp);
+
+/** set the DHCP timers */
+static void dhcp_timeout(struct netif *netif);
+static void dhcp_t1_timeout(struct netif *netif);
+static void dhcp_t2_timeout(struct netif *netif);
+
+/** build outgoing messages */
+/** create a DHCP request, fill in common headers */
+static err_t dhcp_create_request(struct netif *netif);
+/** free a DHCP request */
+static void dhcp_delete_request(struct netif *netif);
+/** add a DHCP option (type, then length in bytes) */
+static void dhcp_option(struct dhcp *dhcp, u8_t option_type, u8_t option_len);
+/** add option values */
+static void dhcp_option_byte(struct dhcp *dhcp, u8_t value);
+static void dhcp_option_short(struct dhcp *dhcp, u16_t value);
+static void dhcp_option_long(struct dhcp *dhcp, u32_t value);
+/** always add the DHCP options trailer to end and pad */
+static void dhcp_option_trailer(struct dhcp *dhcp);
+
+/**
+ * Back-off the DHCP client (because of a received NAK response).
+ *
+ * Back-off the DHCP client because of a received NAK. Receiving a
+ * NAK means the client asked for something non-sensible, for
+ * example when it tries to renew a lease obtained on another network.
+ *
+ * We back-off and will end up restarting a fresh DHCP negotiation later.
+ *
+ * @param state pointer to DHCP state structure
+ */
+static void dhcp_handle_nak(struct netif *netif) {
+  struct dhcp *dhcp = netif->dhcp;
+  u16_t msecs = 10 * 1000;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_handle_nak(netif=%p) %c%c%u\n", netif,
+    netif->name[0], netif->name[1], (unsigned int)netif->num));
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_handle_nak(): set request timeout %u msecs\n", msecs));
+  dhcp_set_state(dhcp, DHCP_BACKING_OFF);
+}
+
+/**
+ * Checks if the offered IP address is already in use.
+ *
+ * It does so by sending an ARP request for the offered address and
+ * entering CHECKING state. If no ARP reply is received within a small
+ * interval, the address is assumed to be free for use by us.
+ */
+static void dhcp_check(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result;
+  u16_t msecs;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_check(netif=%p) %c%c\n", (void *)netif, (unsigned int)netif->name[0],
+    (unsigned int)netif->name[1]));
+  /* create an ARP query for the offered IP address, expecting that no host
+     responds, as the IP address should not be in use. */
+  result = etharp_query(netif, &dhcp->offered_ip_addr, NULL);
+  if (result != ERR_OK) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_check: could not perform ARP query\n"));
+  }
+  dhcp->tries++;
+  msecs = 500;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_check(): set request timeout %u msecs\n", msecs));
+  dhcp_set_state(dhcp, DHCP_CHECKING);
+}
+
+/**
+ * Remember the configuration offered by a DHCP server.
+ *
+ * @param state pointer to DHCP state structure
+ */
+static void dhcp_handle_offer(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  /* obtain the server address */
+  u8_t *option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_SERVER_ID);
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_handle_offer(netif=%p) %c%c%u\n", netif,
+    netif->name[0], netif->name[1], netif->num));
+  if (option_ptr != NULL)
+  {
+    dhcp->server_ip_addr.addr = htonl(dhcp_get_option_long(&option_ptr[2]));
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_handle_offer(): server 0x%08lx\n", dhcp->server_ip_addr.addr));
+    /* remember offered address */
+    ip_addr_set(&dhcp->offered_ip_addr, (struct ip_addr *)&dhcp->msg_in->yiaddr);
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_handle_offer(): offer for 0x%08lx\n", dhcp->offered_ip_addr.addr));
+
+    dhcp_select(netif);
+  }
+}
+
+/**
+ * Select a DHCP server offer out of all offers.
+ *
+ * Simply select the first offer received.
+ *
+ * @param netif the netif under DHCP control
+ * @return lwIP specific error (see error.h)
+ */
+static err_t dhcp_select(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result;
+  u32_t msecs;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_select(netif=%p) %c%c%u\n", netif, netif->name[0], netif->name[1], netif->num));
+
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_request(netif);
+  if (result == ERR_OK)
+  {
+    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+    dhcp_option_byte(dhcp, DHCP_REQUEST);
+
+    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+    dhcp_option_short(dhcp, 576);
+
+    /* MUST request the offered IP address */
+    dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4);
+    dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr));
+
+    dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4);
+    dhcp_option_long(dhcp, ntohl(dhcp->server_ip_addr.addr));
+
+    dhcp_option(dhcp, DHCP_OPTION_PARAMETER_REQUEST_LIST, 4/*num options*/);
+    dhcp_option_byte(dhcp, DHCP_OPTION_SUBNET_MASK);
+    dhcp_option_byte(dhcp, DHCP_OPTION_ROUTER);
+    dhcp_option_byte(dhcp, DHCP_OPTION_BROADCAST);
+    dhcp_option_byte(dhcp, DHCP_OPTION_DNS_SERVER);
+
+    dhcp_option_trailer(dhcp);
+    /* shrink the pbuf to the actual content length */
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+    /* TODO: we really should bind to a specific local interface here
+       but we cannot specify an unconfigured netif as it is addressless */
+    udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
+    /* send broadcast to any DHCP server */
+    udp_connect(dhcp->pcb, IP_ADDR_BROADCAST, DHCP_SERVER_PORT);
+    udp_send(dhcp->pcb, dhcp->p_out);
+    /* reconnect to any (or to server here?!) */
+    udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT);
+    dhcp_delete_request(netif);
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_select: REQUESTING\n"));
+    dhcp_set_state(dhcp, DHCP_REQUESTING);
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_select: could not allocate DHCP request\n"));
+  }
+  dhcp->tries++;
+  msecs = dhcp->tries < 4 ? dhcp->tries * 1000 : 4 * 1000;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_select(): set request timeout %u msecs\n", msecs));
+  return result;
+}
+
+/**
+ * The DHCP timer that checks for lease renewal/rebind timeouts.
+ *
+ */
+void dhcp_coarse_tmr()
+{
+  struct netif *netif = netif_list;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_coarse_tmr()\n"));
+  /* iterate through all network interfaces */
+  while (netif != NULL) {
+    /* only act on DHCP configured interfaces */
+    if (netif->dhcp != NULL) {
+      /* timer is active (non zero), and triggers (zeroes) now? */
+      if (netif->dhcp->t2_timeout-- == 1) {
+        LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_coarse_tmr(): t2 timeout\n"));
+        /* this clients' rebind timeout triggered */
+        dhcp_t2_timeout(netif);
+      /* timer is active (non zero), and triggers (zeroes) now */
+      } else if (netif->dhcp->t1_timeout-- == 1) {
+        LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_coarse_tmr(): t1 timeout\n"));
+        /* this clients' renewal timeout triggered */
+        dhcp_t1_timeout(netif);
+      }
+    }
+    /* proceed to next netif */
+    netif = netif->next;
+  }
+}
+
+/**
+ * DHCP transaction timeout handling
+ *
+ * A DHCP server is expected to respond within a short period of time.
+ * This timer checks whether an outstanding DHCP request is timed out.
+ * 
+ */
+void dhcp_fine_tmr()
+{
+  struct netif *netif = netif_list;
+  /* loop through netif's */
+  while (netif != NULL) {
+    /* only act on DHCP configured interfaces */
+    if (netif->dhcp != NULL) {
+      /* timer is active (non zero), and is about to trigger now */
+      if (netif->dhcp->request_timeout-- == 1) {
+        /* { netif->dhcp->request_timeout == 0 } */
+        LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_fine_tmr(): request timeout\n"));
+        /* this clients' request timeout triggered */
+        dhcp_timeout(netif);
+      }
+    }
+    /* proceed to next network interface */
+    netif = netif->next;
+  }
+}
+
+/**
+ * A DHCP negotiation transaction, or ARP request, has timed out.
+ *
+ * The timer that was started with the DHCP or ARP request has
+ * timed out, indicating no response was received in time.
+ *
+ * @param netif the netif under DHCP control
+ *
+ */
+static void dhcp_timeout(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_timeout()\n"));
+  /* back-off period has passed, or server selection timed out */
+  if ((dhcp->state == DHCP_BACKING_OFF) || (dhcp->state == DHCP_SELECTING)) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_timeout(): restarting discovery\n"));
+    dhcp_discover(netif);
+  /* receiving the requested lease timed out */
+  } else if (dhcp->state == DHCP_REQUESTING) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): REQUESTING, DHCP request timed out\n"));
+    if (dhcp->tries <= 5) {
+      dhcp_select(netif);
+    } else {
+      LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): REQUESTING, releasing, restarting\n"));
+      dhcp_release(netif);
+      dhcp_discover(netif);
+    }
+  /* received no ARP reply for the offered address (which is good) */
+  } else if (dhcp->state == DHCP_CHECKING) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): CHECKING, ARP request timed out\n"));
+    if (dhcp->tries <= 1) {
+      dhcp_check(netif);
+    /* no ARP replies on the offered address,
+       looks like the IP address is indeed free */
+    } else {
+      /* bind the interface to the offered address */
+      dhcp_bind(netif);
+    }
+  }
+  /* did not get response to renew request? */
+  else if (dhcp->state == DHCP_RENEWING) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): RENEWING, DHCP request timed out\n"));
+    /* just retry renewal */
+    /* note that the rebind timer will eventually time-out if renew does not work */
+    dhcp_renew(netif);
+  /* did not get response to rebind request? */
+  } else if (dhcp->state == DHCP_REBINDING) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): REBINDING, DHCP request timed out\n"));
+    if (dhcp->tries <= 8) {
+      dhcp_rebind(netif);
+    } else {
+      LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): RELEASING, DISCOVERING\n"));
+      dhcp_release(netif);
+      dhcp_discover(netif);
+    }
+  }
+}
+
+/**
+ * The renewal period has timed out.
+ *
+ * @param netif the netif under DHCP control
+ */
+static void dhcp_t1_timeout(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_t1_timeout()\n"));
+  if ((dhcp->state == DHCP_REQUESTING) || (dhcp->state == DHCP_BOUND) || (dhcp->state == DHCP_RENEWING)) {
+    /* just retry to renew - note that the rebind timer (t2) will
+     * eventually time-out if renew tries fail. */
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_t1_timeout(): must renew\n"));
+    dhcp_renew(netif);
+  }
+}
+
+/**
+ * The rebind period has timed out.
+ *
+ */
+static void dhcp_t2_timeout(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_t2_timeout()\n"));
+  if ((dhcp->state == DHCP_REQUESTING) || (dhcp->state == DHCP_BOUND) || (dhcp->state == DHCP_RENEWING)) {
+    /* just retry to rebind */
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_t2_timeout(): must rebind\n"));
+    dhcp_rebind(netif);
+  }
+}
+
+/**
+ *
+ * @param netif the netif under DHCP control
+ */
+static void dhcp_handle_ack(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  u8_t *option_ptr;
+  /* clear options we might not get from the ACK */
+  dhcp->offered_sn_mask.addr = 0;
+  dhcp->offered_gw_addr.addr = 0;
+  dhcp->offered_bc_addr.addr = 0;
+
+  /* lease time given? */
+  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_LEASE_TIME);
+  if (option_ptr != NULL) {
+    /* remember offered lease time */
+    dhcp->offered_t0_lease = dhcp_get_option_long(option_ptr + 2);
+  }
+  /* renewal period given? */
+  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_T1);
+  if (option_ptr != NULL) {
+    /* remember given renewal period */
+    dhcp->offered_t1_renew = dhcp_get_option_long(option_ptr + 2);
+  } else {
+    /* calculate safe periods for renewal */
+    dhcp->offered_t1_renew = dhcp->offered_t0_lease / 2;
+  }
+
+  /* renewal period given? */
+  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_T2);
+  if (option_ptr != NULL) {
+    /* remember given rebind period */
+    dhcp->offered_t2_rebind = dhcp_get_option_long(option_ptr + 2);
+  } else {
+    /* calculate safe periods for rebinding */
+    dhcp->offered_t2_rebind = dhcp->offered_t0_lease;
+  }
+
+  /* (y)our internet address */
+  ip_addr_set(&dhcp->offered_ip_addr, &dhcp->msg_in->yiaddr);
+
+/**
+ * Patch #1308
+ * TODO: we must check if the file field is not overloaded by DHCP options!
+ */
+#if 0
+  /* boot server address */
+  ip_addr_set(&dhcp->offered_si_addr, &dhcp->msg_in->siaddr);
+  /* boot file name */
+  if (dhcp->msg_in->file[0]) {
+    dhcp->boot_file_name = mem_malloc(strlen(dhcp->msg_in->file) + 1);
+    strcpy(dhcp->boot_file_name, dhcp->msg_in->file);
+  }
+#endif
+
+  /* subnet mask */
+  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_SUBNET_MASK);
+  /* subnet mask given? */
+  if (option_ptr != NULL) {
+    dhcp->offered_sn_mask.addr = htonl(dhcp_get_option_long(&option_ptr[2]));
+  }
+
+  /* gateway router */
+  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_ROUTER);
+  if (option_ptr != NULL) {
+    dhcp->offered_gw_addr.addr = htonl(dhcp_get_option_long(&option_ptr[2]));
+  }
+
+  /* broadcast address */
+  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_BROADCAST);
+  if (option_ptr != NULL) {
+    dhcp->offered_bc_addr.addr = htonl(dhcp_get_option_long(&option_ptr[2]));
+  }
+  
+  /* DNS servers */
+  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_DNS_SERVER);
+  if (option_ptr != NULL) {
+    u8_t n;
+    dhcp->dns_count = dhcp_get_option_byte(&option_ptr[1]);
+    /* limit to at most DHCP_MAX_DNS DNS servers */
+    if (dhcp->dns_count > DHCP_MAX_DNS) dhcp->dns_count = DHCP_MAX_DNS;
+    for (n = 0; n < dhcp->dns_count; n++)
+    {
+      dhcp->offered_dns_addr[n].addr = htonl(dhcp_get_option_long(&option_ptr[2+(n<<2)]));
+    }
+  }
+}
+
+/**
+ * Start DHCP negotiation for a network interface.
+ *
+ * If no DHCP client instance was attached to this interface,
+ * a new client is created first. If a DHCP client instance
+ * was already present, it restarts negotiation.
+ *
+ * @param netif The lwIP network interface
+ * @return lwIP error code
+ * - ERR_OK - No error
+ * - ERR_MEM - Out of memory
+ *
+ */
+err_t dhcp_start(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result = ERR_OK;
+
+  LWIP_ASSERT("netif != NULL", netif != NULL);
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_start(netif=%p) %c%c%u\n", netif, netif->name[0], netif->name[1], netif->num));
+  netif->flags &= ~NETIF_FLAG_DHCP;
+
+  /* no DHCP client attached yet? */
+  if (dhcp == NULL) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): starting new DHCP client\n"));
+    dhcp = mem_malloc(sizeof(struct dhcp));
+    if (dhcp == NULL) {
+      LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): could not allocate dhcp\n"));
+      return ERR_MEM;
+    }
+    /* store this dhcp client in the netif */
+    netif->dhcp = dhcp;
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): allocated dhcp"));
+  /* already has DHCP client attached */
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE | 3, ("dhcp_start(): restarting DHCP configuration\n"));
+  }
+  	
+	/* clear data structure */
+	memset(dhcp, 0, sizeof(struct dhcp));
+  /* allocate UDP PCB */
+	dhcp->pcb = udp_new();
+	if (dhcp->pcb == NULL) {
+	  LWIP_DEBUGF(DHCP_DEBUG  | DBG_TRACE, ("dhcp_start(): could not obtain pcb\n"));
+	  mem_free((void *)dhcp);
+	  netif->dhcp = dhcp = NULL;
+	  return ERR_MEM;
+	}
+	LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): starting DHCP configuration\n"));
+  /* (re)start the DHCP negotiation */
+  result = dhcp_discover(netif);
+  if (result != ERR_OK) {
+    /* free resources allocated above */
+    dhcp_stop(netif);
+    return ERR_MEM;
+  }
+  netif->flags |= NETIF_FLAG_DHCP;
+  return result;
+}
+
+/**
+ * Inform a DHCP server of our manual configuration.
+ *
+ * This informs DHCP servers of our fixed IP address configuration
+ * by sending an INFORM message. It does not involve DHCP address
+ * configuration, it is just here to be nice to the network.
+ *
+ * @param netif The lwIP network interface
+ *
+ */
+void dhcp_inform(struct netif *netif)
+{
+  struct dhcp *dhcp;
+  err_t result = ERR_OK;
+  dhcp = mem_malloc(sizeof(struct dhcp));
+  if (dhcp == NULL) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_inform(): could not allocate dhcp\n"));
+    return;
+  }
+  netif->dhcp = dhcp;
+  memset(dhcp, 0, sizeof(struct dhcp));
+
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_inform(): allocated dhcp\n"));
+  dhcp->pcb = udp_new();
+  if (dhcp->pcb == NULL) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_inform(): could not obtain pcb"));
+    mem_free((void *)dhcp);
+    return;
+  }
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_inform(): created new udp pcb\n"));
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_request(netif);
+  if (result == ERR_OK) {
+
+    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+    dhcp_option_byte(dhcp, DHCP_INFORM);
+
+    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+    /* TODO: use netif->mtu ?! */
+    dhcp_option_short(dhcp, 576);
+
+    dhcp_option_trailer(dhcp);
+
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+    udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
+    udp_connect(dhcp->pcb, IP_ADDR_BROADCAST, DHCP_SERVER_PORT);
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_inform: INFORMING\n"));
+    udp_send(dhcp->pcb, dhcp->p_out);
+    udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT);
+    dhcp_delete_request(netif);
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_inform: could not allocate DHCP request\n"));
+  }
+
+  if (dhcp != NULL)
+  {
+    if (dhcp->pcb != NULL) udp_remove(dhcp->pcb);
+    dhcp->pcb = NULL;
+    mem_free((void *)dhcp);
+    netif->dhcp = NULL;
+  }
+}
+
+#if DHCP_DOES_ARP_CHECK
+/**
+ * Match an ARP reply with the offered IP address.
+ *
+ * @param addr The IP address we received a reply from
+ *
+ */
+void dhcp_arp_reply(struct netif *netif, struct ip_addr *addr)
+{
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_arp_reply()\n"));
+  /* is this DHCP client doing an ARP check? */
+  if ((netif->dhcp != NULL) && (netif->dhcp->state == DHCP_CHECKING)) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_arp_reply(): CHECKING, arp reply for 0x%08lx\n", addr->addr));
+    /* did a host respond with the address we
+       were offered by the DHCP server? */
+    if (ip_addr_cmp(addr, &netif->dhcp->offered_ip_addr)) {
+      /* we will not accept the offered address */
+      LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE | 1, ("dhcp_arp_reply(): arp reply matched with offered address, declining\n"));
+      dhcp_decline(netif);
+    }
+  }
+}
+
+/**
+ * Decline an offered lease.
+ *
+ * Tell the DHCP server we do not accept the offered address.
+ * One reason to decline the lease is when we find out the address
+ * is already in use by another host (through ARP).
+ */
+static err_t dhcp_decline(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result = ERR_OK;
+  u16_t msecs;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_decline()\n"));
+  dhcp_set_state(dhcp, DHCP_BACKING_OFF);
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_request(netif);
+  if (result == ERR_OK)
+  {
+    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+    dhcp_option_byte(dhcp, DHCP_DECLINE);
+
+    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+    dhcp_option_short(dhcp, 576);
+
+    dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4);
+    dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr));
+
+    dhcp_option_trailer(dhcp);
+    /* resize pbuf to reflect true size of options */
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+    udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
+    /* @todo: should we really connect here? we are performing sendto() */
+    udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT);
+    /* per section 4.4.4, broadcast DECLINE messages */
+    udp_sendto(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT);
+    dhcp_delete_request(netif);
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_decline: BACKING OFF\n"));
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_decline: could not allocate DHCP request\n"));
+  }
+  dhcp->tries++;
+  msecs = 10*1000;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+   LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_decline(): set request timeout %u msecs\n", msecs));
+  return result;
+}
+#endif
+
+
+/**
+ * Start the DHCP process, discover a DHCP server.
+ *
+ */
+static err_t dhcp_discover(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result = ERR_OK;
+  u16_t msecs;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_discover()\n"));
+  ip_addr_set(&dhcp->offered_ip_addr, IP_ADDR_ANY);
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_request(netif);
+  if (result == ERR_OK)
+  {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_discover: making request\n"));
+    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+    dhcp_option_byte(dhcp, DHCP_DISCOVER);
+
+    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+    dhcp_option_short(dhcp, 576);
+
+    dhcp_option(dhcp, DHCP_OPTION_PARAMETER_REQUEST_LIST, 4/*num options*/);
+    dhcp_option_byte(dhcp, DHCP_OPTION_SUBNET_MASK);
+    dhcp_option_byte(dhcp, DHCP_OPTION_ROUTER);
+    dhcp_option_byte(dhcp, DHCP_OPTION_BROADCAST);
+    dhcp_option_byte(dhcp, DHCP_OPTION_DNS_SERVER);
+
+    dhcp_option_trailer(dhcp);
+
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_discover: realloc()ing\n"));
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+    /* set receive callback function with netif as user data */
+    udp_recv(dhcp->pcb, dhcp_recv, netif);
+    udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
+    udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT);
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_discover: sendto(DISCOVER, IP_ADDR_BROADCAST, DHCP_SERVER_PORT)\n"));
+    udp_sendto(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT);
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_discover: deleting()ing\n"));
+    dhcp_delete_request(netif);
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_discover: SELECTING\n"));
+    dhcp_set_state(dhcp, DHCP_SELECTING);
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_discover: could not allocate DHCP request\n"));
+  }
+  dhcp->tries++;
+  msecs = dhcp->tries < 4 ? (dhcp->tries + 1) * 1000 : 10 * 1000;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_discover(): set request timeout %u msecs\n", msecs));
+  return result;
+}
+
+
+/**
+ * Bind the interface to the offered IP address.
+ *
+ * @param netif network interface to bind to the offered address
+ */
+static void dhcp_bind(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  struct ip_addr sn_mask, gw_addr;
+  LWIP_ASSERT("dhcp_bind: netif != NULL", netif != NULL);
+  LWIP_ASSERT("dhcp_bind: dhcp != NULL", dhcp != NULL);
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_bind(netif=%p) %c%c%u\n", netif, netif->name[0], netif->name[1], netif->num));
+
+  /* temporary DHCP lease? */
+  if (dhcp->offered_t1_renew != 0xffffffffUL) {
+    /* set renewal period timer */
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_bind(): t1 renewal timer %lu secs\n", dhcp->offered_t1_renew));
+    dhcp->t1_timeout = (dhcp->offered_t1_renew + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS;
+    if (dhcp->t1_timeout == 0) dhcp->t1_timeout = 1;
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_bind(): set request timeout %u msecs\n", dhcp->offered_t1_renew*1000));
+  }
+  /* set renewal period timer */
+  if (dhcp->offered_t2_rebind != 0xffffffffUL) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_bind(): t2 rebind timer %lu secs\n", dhcp->offered_t2_rebind));
+    dhcp->t2_timeout = (dhcp->offered_t2_rebind + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS;
+    if (dhcp->t2_timeout == 0) dhcp->t2_timeout = 1;
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_bind(): set request timeout %u msecs\n", dhcp->offered_t2_rebind*1000));
+  }
+  /* copy offered network mask */
+  ip_addr_set(&sn_mask, &dhcp->offered_sn_mask);
+
+  /* subnet mask not given? */
+  /* TODO: this is not a valid check. what if the network mask is 0? */
+  if (sn_mask.addr == 0) {
+    /* choose a safe subnet mask given the network class */
+    u8_t first_octet = ip4_addr1(&sn_mask);
+    if (first_octet <= 127) sn_mask.addr = htonl(0xff000000);
+    else if (first_octet >= 192) sn_mask.addr = htonl(0xffffff00);
+    else sn_mask.addr = htonl(0xffff0000);
+  }
+
+  ip_addr_set(&gw_addr, &dhcp->offered_gw_addr);
+  /* gateway address not given? */
+  if (gw_addr.addr == 0) {
+    /* copy network address */
+    gw_addr.addr = (dhcp->offered_ip_addr.addr & sn_mask.addr);
+    /* use first host address on network as gateway */
+    gw_addr.addr |= htonl(0x00000001);
+  }
+
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_bind(): IP: 0x%08lx\n", dhcp->offered_ip_addr.addr));
+  netif_set_ipaddr(netif, &dhcp->offered_ip_addr);
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_bind(): SN: 0x%08lx\n", sn_mask.addr));
+  netif_set_netmask(netif, &sn_mask);
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_bind(): GW: 0x%08lx\n", gw_addr.addr));
+  netif_set_gw(netif, &gw_addr);
+  /* bring the interface up */
+  netif_set_up(netif);
+  /* netif is now bound to DHCP leased address */
+  dhcp_set_state(dhcp, DHCP_BOUND);
+}
+
+/**
+ * Renew an existing DHCP lease at the involved DHCP server.
+ *
+ * @param netif network interface which must renew its lease
+ */
+err_t dhcp_renew(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result;
+  u16_t msecs;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_renew()\n"));
+  dhcp_set_state(dhcp, DHCP_RENEWING);
+
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_request(netif);
+  if (result == ERR_OK) {
+
+    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+    dhcp_option_byte(dhcp, DHCP_REQUEST);
+
+    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+    /* TODO: use netif->mtu in some way */
+    dhcp_option_short(dhcp, 576);
+
+#if 0
+    dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4);
+    dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr));
+#endif
+
+#if 0
+    dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4);
+    dhcp_option_long(dhcp, ntohl(dhcp->server_ip_addr.addr));
+#endif
+    /* append DHCP message trailer */
+    dhcp_option_trailer(dhcp);
+
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+    udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
+    udp_connect(dhcp->pcb, &dhcp->server_ip_addr, DHCP_SERVER_PORT);
+    udp_send(dhcp->pcb, dhcp->p_out);
+    dhcp_delete_request(netif);
+
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_renew: RENEWING\n"));
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_renew: could not allocate DHCP request\n"));
+  }
+  dhcp->tries++;
+  /* back-off on retries, but to a maximum of 20 seconds */
+  msecs = dhcp->tries < 10 ? dhcp->tries * 2000 : 20 * 1000;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+   LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_renew(): set request timeout %u msecs\n", msecs));
+  return result;
+}
+
+/**
+ * Rebind with a DHCP server for an existing DHCP lease.
+ *
+ * @param netif network interface which must rebind with a DHCP server
+ */
+static err_t dhcp_rebind(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result;
+  u16_t msecs;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_rebind()\n"));
+  dhcp_set_state(dhcp, DHCP_REBINDING);
+
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_request(netif);
+  if (result == ERR_OK)
+  {
+
+    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+    dhcp_option_byte(dhcp, DHCP_REQUEST);
+
+    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+    dhcp_option_short(dhcp, 576);
+
+#if 0
+    dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4);
+    dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr));
+
+    dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4);
+    dhcp_option_long(dhcp, ntohl(dhcp->server_ip_addr.addr));
+#endif
+
+    dhcp_option_trailer(dhcp);
+
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+    /* set remote IP association to any DHCP server */
+    udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
+    udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT);
+    /* broadcast to server */
+    udp_sendto(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT);
+    dhcp_delete_request(netif);
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_rebind: REBINDING\n"));
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_rebind: could not allocate DHCP request\n"));
+  }
+  dhcp->tries++;
+  msecs = dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+   LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_rebind(): set request timeout %u msecs\n", msecs));
+  return result;
+}
+
+/**
+ * Release a DHCP lease.
+ *
+ * @param netif network interface which must release its lease
+ */
+err_t dhcp_release(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result;
+  u16_t msecs;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_release()\n"));
+
+  /* idle DHCP client */
+  dhcp_set_state(dhcp, DHCP_OFF);
+  /* clean old DHCP offer */
+  dhcp->server_ip_addr.addr = 0;
+  dhcp->offered_ip_addr.addr = dhcp->offered_sn_mask.addr = 0;
+  dhcp->offered_gw_addr.addr = dhcp->offered_bc_addr.addr = 0;
+  dhcp->offered_t0_lease = dhcp->offered_t1_renew = dhcp->offered_t2_rebind = 0;
+  dhcp->dns_count = 0;
+  
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_request(netif);
+  if (result == ERR_OK) {
+    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+    dhcp_option_byte(dhcp, DHCP_RELEASE);
+
+    dhcp_option_trailer(dhcp);
+
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+    udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
+    udp_connect(dhcp->pcb, &dhcp->server_ip_addr, DHCP_SERVER_PORT);
+    udp_send(dhcp->pcb, dhcp->p_out);
+    dhcp_delete_request(netif);
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_release: RELEASED, DHCP_OFF\n"));
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_release: could not allocate DHCP request\n"));
+  }
+  dhcp->tries++;
+  msecs = dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_release(): set request timeout %u msecs\n", msecs));
+  /* bring the interface down */
+  netif_set_down(netif);
+  /* remove IP address from interface */
+  netif_set_ipaddr(netif, IP_ADDR_ANY);
+  netif_set_gw(netif, IP_ADDR_ANY);
+  netif_set_netmask(netif, IP_ADDR_ANY);
+  
+  /* TODO: netif_down(netif); */
+  return result;
+}
+/**
+ * Remove the DHCP client from the interface.
+ *
+ * @param netif The network interface to stop DHCP on
+ */
+void dhcp_stop(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  LWIP_ASSERT("dhcp_stop: netif != NULL", netif != NULL);
+
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_stop()\n"));
+  /* netif is DHCP configured? */
+  if (dhcp != NULL)
+  {
+    if (dhcp->pcb != NULL)
+    {
+      udp_remove(dhcp->pcb);
+      dhcp->pcb = NULL;
+    }
+    if (dhcp->p != NULL)
+    {
+      pbuf_free(dhcp->p);
+      dhcp->p = NULL;
+    }
+    /* free unfolded reply */
+    dhcp_free_reply(dhcp);
+    mem_free((void *)dhcp);
+    netif->dhcp = NULL;
+  }
+}
+
+/*
+ * Set the DHCP state of a DHCP client.
+ *
+ * If the state changed, reset the number of tries.
+ *
+ * TODO: we might also want to reset the timeout here?
+ */
+static void dhcp_set_state(struct dhcp *dhcp, unsigned char new_state)
+{
+  if (new_state != dhcp->state)
+  {
+    dhcp->state = new_state;
+    dhcp->tries = 0;
+  }
+}
+
+/*
+ * Concatenate an option type and length field to the outgoing
+ * DHCP message.
+ *
+ */
+static void dhcp_option(struct dhcp *dhcp, u8_t option_type, u8_t option_len)
+{
+  LWIP_ASSERT("dhcp_option_short: dhcp->options_out_len + 2 + option_len <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 2 + option_len <= DHCP_OPTIONS_LEN);
+  dhcp->msg_out->options[dhcp->options_out_len++] = option_type;
+  dhcp->msg_out->options[dhcp->options_out_len++] = option_len;
+}
+/*
+ * Concatenate a single byte to the outgoing DHCP message.
+ *
+ */
+static void dhcp_option_byte(struct dhcp *dhcp, u8_t value)
+{
+  LWIP_ASSERT("dhcp_option_short: dhcp->options_out_len < DHCP_OPTIONS_LEN", dhcp->options_out_len < DHCP_OPTIONS_LEN);
+  dhcp->msg_out->options[dhcp->options_out_len++] = value;
+}
+static void dhcp_option_short(struct dhcp *dhcp, u16_t value)
+{
+  LWIP_ASSERT("dhcp_option_short: dhcp->options_out_len + 2 <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 2 <= DHCP_OPTIONS_LEN);
+  dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0xff00U) >> 8;
+  dhcp->msg_out->options[dhcp->options_out_len++] =  value & 0x00ffU;
+}
+static void dhcp_option_long(struct dhcp *dhcp, u32_t value)
+{
+  LWIP_ASSERT("dhcp_option_long: dhcp->options_out_len + 4 <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 4 <= DHCP_OPTIONS_LEN);
+  dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0xff000000UL) >> 24;
+  dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0x00ff0000UL) >> 16;
+  dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0x0000ff00UL) >> 8;
+  dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0x000000ffUL);
+}
+
+/**
+ * Extract the DHCP message and the DHCP options.
+ *
+ * Extract the DHCP message and the DHCP options, each into a contiguous
+ * piece of memory. As a DHCP message is variable sized by its options,
+ * and also allows overriding some fields for options, the easy approach
+ * is to first unfold the options into a conitguous piece of memory, and
+ * use that further on.
+ *
+ */
+static err_t dhcp_unfold_reply(struct dhcp *dhcp)
+{
+  struct pbuf *p = dhcp->p;
+  u8_t *ptr;
+  u16_t i;
+  u16_t j = 0;
+  LWIP_ASSERT("dhcp->p != NULL", dhcp->p != NULL);
+  /* free any left-overs from previous unfolds */
+  dhcp_free_reply(dhcp);
+  /* options present? */
+  if (dhcp->p->tot_len > (sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN))
+  {
+    dhcp->options_in_len = dhcp->p->tot_len - (sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN);
+    dhcp->options_in = mem_malloc(dhcp->options_in_len);
+    if (dhcp->options_in == NULL)
+    {
+      LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_unfold_reply(): could not allocate dhcp->options\n"));
+      return ERR_MEM;
+    }
+  }
+  dhcp->msg_in = mem_malloc(sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN);
+  if (dhcp->msg_in == NULL)
+  {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_unfold_reply(): could not allocate dhcp->msg_in\n"));
+    mem_free((void *)dhcp->options_in);
+    dhcp->options_in = NULL;
+    return ERR_MEM;
+  }
+
+  ptr = (u8_t *)dhcp->msg_in;
+  /* proceed through struct dhcp_msg */
+  for (i = 0; i < sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN; i++)
+  {
+    *ptr++ = ((u8_t *)p->payload)[j++];
+    /* reached end of pbuf? */
+    if (j == p->len)
+    {
+      /* proceed to next pbuf in chain */
+      p = p->next;
+      j = 0;
+    }
+  }
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_unfold_reply(): copied %u bytes into dhcp->msg_in[]\n", i));
+  if (dhcp->options_in != NULL) {
+    ptr = (u8_t *)dhcp->options_in;
+    /* proceed through options */
+    for (i = 0; i < dhcp->options_in_len; i++) {
+      *ptr++ = ((u8_t *)p->payload)[j++];
+      /* reached end of pbuf? */
+      if (j == p->len) {
+        /* proceed to next pbuf in chain */
+        p = p->next;
+        j = 0;
+      }
+    }
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_unfold_reply(): copied %u bytes to dhcp->options_in[]\n", i));
+  }
+  return ERR_OK;
+}
+
+/**
+ * Free the incoming DHCP message including contiguous copy of
+ * its DHCP options.
+ *
+ */
+static void dhcp_free_reply(struct dhcp *dhcp)
+{
+  if (dhcp->msg_in != NULL) {
+    mem_free((void *)dhcp->msg_in);
+    dhcp->msg_in = NULL;
+  }
+  if (dhcp->options_in) {
+    mem_free((void *)dhcp->options_in);
+    dhcp->options_in = NULL;
+    dhcp->options_in_len = 0;
+  }
+  LWIP_DEBUGF(DHCP_DEBUG, ("dhcp_free_reply(): free'd\n"));
+}
+
+
+/**
+ * If an incoming DHCP message is in response to us, then trigger the state machine
+ */
+static void dhcp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *addr, u16_t port)
+{
+  struct netif *netif = (struct netif *)arg;
+  struct dhcp *dhcp = netif->dhcp;
+  struct dhcp_msg *reply_msg = (struct dhcp_msg *)p->payload;
+  u8_t *options_ptr;
+  u8_t msg_type;
+  u8_t i;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_recv(pbuf = %p) from DHCP server %u.%u.%u.%u port %u\n", p,
+    (unsigned int)(ntohl(addr->addr) >> 24 & 0xff), (unsigned int)(ntohl(addr->addr) >> 16 & 0xff),
+    (unsigned int)(ntohl(addr->addr) >>  8 & 0xff), (unsigned int)(ntohl(addr->addr) & 0xff), port));
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("pbuf->len = %u\n", p->len));
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("pbuf->tot_len = %u\n", p->tot_len));
+  /* prevent warnings about unused arguments */
+  (void)pcb; (void)addr; (void)port;
+  dhcp->p = p;
+  /* TODO: check packet length before reading them */
+  if (reply_msg->op != DHCP_BOOTREPLY) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("not a DHCP reply message, but type %u\n", reply_msg->op));
+    pbuf_free(p);
+    dhcp->p = NULL;
+    return;
+  }
+  /* iterate through hardware address and match against DHCP message */
+  for (i = 0; i < netif->hwaddr_len; i++) {
+    if (netif->hwaddr[i] != reply_msg->chaddr[i]) {
+      LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("netif->hwaddr[%u]==%02x != reply_msg->chaddr[%u]==%02x\n",
+        i, netif->hwaddr[i], i, reply_msg->chaddr[i]));
+      pbuf_free(p);
+      dhcp->p = NULL;
+      return;
+    }
+  }
+  /* match transaction ID against what we expected */
+  if (ntohl(reply_msg->xid) != dhcp->xid) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("transaction id mismatch\n"));
+    pbuf_free(p);
+    dhcp->p = NULL;
+    return;
+  }
+  /* option fields could be unfold? */
+  if (dhcp_unfold_reply(dhcp) != ERR_OK) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("problem unfolding DHCP message - too short on memory?\n"));
+    pbuf_free(p);
+    dhcp->p = NULL;
+    return;
+  }
+
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("searching DHCP_OPTION_MESSAGE_TYPE\n"));
+  /* obtain pointer to DHCP message type */
+  options_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_MESSAGE_TYPE);
+  if (options_ptr == NULL) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("DHCP_OPTION_MESSAGE_TYPE option not found\n"));
+    pbuf_free(p);
+    dhcp->p = NULL;
+    return;
+  }
+
+  /* read DHCP message type */
+  msg_type = dhcp_get_option_byte(options_ptr + 2);
+  /* message type is DHCP ACK? */
+  if (msg_type == DHCP_ACK) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("DHCP_ACK received\n"));
+    /* in requesting state? */
+    if (dhcp->state == DHCP_REQUESTING) {
+      dhcp_handle_ack(netif);
+      dhcp->request_timeout = 0;
+#if DHCP_DOES_ARP_CHECK
+      /* check if the acknowledged lease address is already in use */
+      dhcp_check(netif);
+#else
+      /* bind interface to the acknowledged lease address */
+      dhcp_bind(netif);
+#endif
+    }
+    /* already bound to the given lease address? */
+    else if ((dhcp->state == DHCP_REBOOTING) || (dhcp->state == DHCP_REBINDING) || (dhcp->state == DHCP_RENEWING)) {
+      dhcp->request_timeout = 0;
+      dhcp_bind(netif);
+    }
+  }
+  /* received a DHCP_NAK in appropriate state? */
+  else if ((msg_type == DHCP_NAK) &&
+    ((dhcp->state == DHCP_REBOOTING) || (dhcp->state == DHCP_REQUESTING) ||
+     (dhcp->state == DHCP_REBINDING) || (dhcp->state == DHCP_RENEWING  ))) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("DHCP_NAK received\n"));
+    dhcp->request_timeout = 0;
+    dhcp_handle_nak(netif);
+  }
+  /* received a DHCP_OFFER in DHCP_SELECTING state? */
+  else if ((msg_type == DHCP_OFFER) && (dhcp->state == DHCP_SELECTING)) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("DHCP_OFFER received in DHCP_SELECTING state\n"));
+    dhcp->request_timeout = 0;
+    /* remember offered lease */
+    dhcp_handle_offer(netif);
+  }
+  pbuf_free(p);
+  dhcp->p = NULL;
+}
+
+
+static err_t dhcp_create_request(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  u16_t i;
+  LWIP_ASSERT("dhcp_create_request: dhcp->p_out == NULL", dhcp->p_out == NULL);
+  LWIP_ASSERT("dhcp_create_request: dhcp->msg_out == NULL", dhcp->msg_out == NULL);
+  dhcp->p_out = pbuf_alloc(PBUF_TRANSPORT, sizeof(struct dhcp_msg), PBUF_RAM);
+  if (dhcp->p_out == NULL) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_create_request(): could not allocate pbuf\n"));
+    return ERR_MEM;
+  }
+  /* give unique transaction identifier to this request */
+  dhcp->xid = xid++;
+
+  dhcp->msg_out = (struct dhcp_msg *)dhcp->p_out->payload;
+
+  dhcp->msg_out->op = DHCP_BOOTREQUEST;
+  /* TODO: make link layer independent */
+  dhcp->msg_out->htype = DHCP_HTYPE_ETH;
+  /* TODO: make link layer independent */
+  dhcp->msg_out->hlen = DHCP_HLEN_ETH;
+  dhcp->msg_out->hops = 0;
+  dhcp->msg_out->xid = htonl(dhcp->xid);
+  dhcp->msg_out->secs = 0;
+  dhcp->msg_out->flags = 0;
+  dhcp->msg_out->ciaddr.addr = netif->ip_addr.addr;
+  dhcp->msg_out->yiaddr.addr = 0;
+  dhcp->msg_out->siaddr.addr = 0;
+  dhcp->msg_out->giaddr.addr = 0;
+  for (i = 0; i < DHCP_CHADDR_LEN; i++) {
+    /* copy netif hardware address, pad with zeroes */
+    dhcp->msg_out->chaddr[i] = (i < netif->hwaddr_len) ? netif->hwaddr[i] : 0/* pad byte*/;
+  }
+  for (i = 0; i < DHCP_SNAME_LEN; i++) dhcp->msg_out->sname[i] = 0;
+  for (i = 0; i < DHCP_FILE_LEN; i++) dhcp->msg_out->file[i] = 0;
+  dhcp->msg_out->cookie = htonl(0x63825363UL);
+  dhcp->options_out_len = 0;
+  /* fill options field with an incrementing array (for debugging purposes) */
+  for (i = 0; i < DHCP_OPTIONS_LEN; i++) dhcp->msg_out->options[i] = i;
+  return ERR_OK;
+}
+
+static void dhcp_delete_request(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  LWIP_ASSERT("dhcp_free_msg: dhcp->p_out != NULL", dhcp->p_out != NULL);
+  LWIP_ASSERT("dhcp_free_msg: dhcp->msg_out != NULL", dhcp->msg_out != NULL);
+  pbuf_free(dhcp->p_out);
+  dhcp->p_out = NULL;
+  dhcp->msg_out = NULL;
+}
+
+/**
+ * Add a DHCP message trailer
+ *
+ * Adds the END option to the DHCP message, and if
+ * necessary, up to three padding bytes.
+ */
+
+static void dhcp_option_trailer(struct dhcp *dhcp)
+{
+  LWIP_ASSERT("dhcp_option_trailer: dhcp->msg_out != NULL\n", dhcp->msg_out != NULL);
+  LWIP_ASSERT("dhcp_option_trailer: dhcp->options_out_len < DHCP_OPTIONS_LEN\n", dhcp->options_out_len < DHCP_OPTIONS_LEN);
+  dhcp->msg_out->options[dhcp->options_out_len++] = DHCP_OPTION_END;
+  /* packet is too small, or not 4 byte aligned? */
+  while ((dhcp->options_out_len < DHCP_MIN_OPTIONS_LEN) || (dhcp->options_out_len & 3)) {
+    /* LWIP_DEBUGF(DHCP_DEBUG, ("dhcp_option_trailer: dhcp->options_out_len=%u, DHCP_OPTIONS_LEN=%u", dhcp->options_out_len, DHCP_OPTIONS_LEN)); */
+    LWIP_ASSERT("dhcp_option_trailer: dhcp->options_out_len < DHCP_OPTIONS_LEN\n", dhcp->options_out_len < DHCP_OPTIONS_LEN);
+    /* add a fill/padding byte */
+    dhcp->msg_out->options[dhcp->options_out_len++] = 0;
+  }
+}
+
+/**
+ * Find the offset of a DHCP option inside the DHCP message.
+ *
+ * @param client DHCP client
+ * @param option_type
+ *
+ * @return a byte offset into the UDP message where the option was found, or
+ * zero if the given option was not found.
+ */
+static u8_t *dhcp_get_option_ptr(struct dhcp *dhcp, u8_t option_type)
+{
+  u8_t overload = DHCP_OVERLOAD_NONE;
+
+  /* options available? */
+  if ((dhcp->options_in != NULL) && (dhcp->options_in_len > 0)) {
+    /* start with options field */
+    u8_t *options = (u8_t *)dhcp->options_in;
+    u16_t offset = 0;
+    /* at least 1 byte to read and no end marker, then at least 3 bytes to read? */
+    while ((offset < dhcp->options_in_len) && (options[offset] != DHCP_OPTION_END)) {
+      /* LWIP_DEBUGF(DHCP_DEBUG, ("msg_offset=%u, q->len=%u", msg_offset, q->len)); */
+      /* are the sname and/or file field overloaded with options? */
+      if (options[offset] == DHCP_OPTION_OVERLOAD) {
+        LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("overloaded message detected\n"));
+        /* skip option type and length */
+        offset += 2;
+        overload = options[offset++];
+      }
+      /* requested option found */
+      else if (options[offset] == option_type) {
+        LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("option found at offset %u in options\n", offset));
+        return &options[offset];
+      /* skip option */
+      } else {
+         LWIP_DEBUGF(DHCP_DEBUG, ("skipping option %u in options\n", options[offset]));
+        /* skip option type */
+        offset++;
+        /* skip option length, and then length bytes */
+        offset += 1 + options[offset];
+      }
+    }
+    /* is this an overloaded message? */
+    if (overload != DHCP_OVERLOAD_NONE) {
+      u16_t field_len;
+      if (overload == DHCP_OVERLOAD_FILE) {
+        LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("overloaded file field\n"));
+        options = (u8_t *)&dhcp->msg_in->file;
+        field_len = DHCP_FILE_LEN;
+      } else if (overload == DHCP_OVERLOAD_SNAME) {
+        LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("overloaded sname field\n"));
+        options = (u8_t *)&dhcp->msg_in->sname;
+        field_len = DHCP_SNAME_LEN;
+      /* TODO: check if else if () is necessary */
+      } else {
+        LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("overloaded sname and file field\n"));
+        options = (u8_t *)&dhcp->msg_in->sname;
+        field_len = DHCP_FILE_LEN + DHCP_SNAME_LEN;
+      }
+      offset = 0;
+
+      /* at least 1 byte to read and no end marker */
+      while ((offset < field_len) && (options[offset] != DHCP_OPTION_END)) {
+        if (options[offset] == option_type) {
+           LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("option found at offset=%u\n", offset));
+          return &options[offset];
+        /* skip option */
+        } else {
+          LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("skipping option %u\n", options[offset]));
+          /* skip option type */
+          offset++;
+          offset += 1 + options[offset];
+        }
+      }
+    }
+  }
+  return 0;
+}
+
+/**
+ * Return the byte of DHCP option data.
+ *
+ * @param client DHCP client.
+ * @param ptr pointer obtained by dhcp_get_option_ptr().
+ *
+ * @return byte value at the given address.
+ */
+static u8_t dhcp_get_option_byte(u8_t *ptr)
+{
+  LWIP_DEBUGF(DHCP_DEBUG, ("option byte value=%u\n", *ptr));
+  return *ptr;
+}
+
+/**
+ * Return the 16-bit value of DHCP option data.
+ *
+ * @param client DHCP client.
+ * @param ptr pointer obtained by dhcp_get_option_ptr().
+ *
+ * @return byte value at the given address.
+ */
+static u16_t dhcp_get_option_short(u8_t *ptr)
+{
+  u16_t value;
+  value = *ptr++ << 8;
+  value |= *ptr;
+  LWIP_DEBUGF(DHCP_DEBUG, ("option short value=%u\n", value));
+  return value;
+}
+
+/**
+ * Return the 32-bit value of DHCP option data.
+ *
+ * @param client DHCP client.
+ * @param ptr pointer obtained by dhcp_get_option_ptr().
+ *
+ * @return byte value at the given address.
+ */
+static u32_t dhcp_get_option_long(u8_t *ptr)
+{
+  u32_t value;
+  value = (u32_t)(*ptr++) << 24;
+  value |= (u32_t)(*ptr++) << 16;
+  value |= (u32_t)(*ptr++) << 8;
+  value |= (u32_t)(*ptr++);
+  LWIP_DEBUGF(DHCP_DEBUG, ("option long value=%lu\n", value));
+  return value;
+}
+
+#endif /* LWIP_DHCP */
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/inet.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/inet.c
new file mode 100644
index 000000000..8b02cada3
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/inet.c
@@ -0,0 +1,377 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+
+/* inet.c
+ *
+ * Functions common to all TCP/IP modules, such as the Internet checksum and the
+ * byte order functions.
+ *
+ */
+
+
+#include "lwip/opt.h"
+
+#include "lwip/arch.h"
+
+#include "lwip/def.h"
+#include "lwip/inet.h"
+
+#include "lwip/sys.h"
+
+/* This is a reference implementation of the checksum algorithm
+
+ - it may not work on all architectures, and all processors, particularly
+   if they have issues with alignment and 16 bit access.
+
+ - in this case you will need to port it to your architecture and 
+   #define LWIP_CHKSUM  
+   in your sys_arch.h
+*/
+#ifndef LWIP_CHKSUM
+#define LWIP_CHKSUM lwip_standard_chksum
+static u16_t
+lwip_standard_chksum(void *dataptr, int len)
+{
+  u32_t acc;
+
+  LWIP_DEBUGF(INET_DEBUG, ("lwip_chksum(%p, %d)\n", (void *)dataptr, len));
+  for(acc = 0; len > 1; len -= 2) {
+      /*    acc = acc + *((u16_t *)dataptr)++;*/
+    acc += *(u16_t *)dataptr;
+    dataptr = (void *)((u16_t *)dataptr + 1);
+  }
+
+  /* add up any odd byte */
+  if (len == 1) {
+    acc += htons((u16_t)((*(u8_t *)dataptr) & 0xff) << 8);
+    LWIP_DEBUGF(INET_DEBUG, ("inet: chksum: odd byte %d\n", (unsigned int)(*(u8_t *)dataptr)));
+  } else {
+    LWIP_DEBUGF(INET_DEBUG, ("inet: chksum: no odd byte\n"));
+  }
+  acc = (acc >> 16) + (acc & 0xffffUL);
+
+  if ((acc & 0xffff0000) != 0) {
+    acc = (acc >> 16) + (acc & 0xffffUL);
+  }
+
+  return (u16_t)acc;
+}
+#endif
+
+/* inet_chksum_pseudo:
+ *
+ * Calculates the pseudo Internet checksum used by TCP and UDP for a pbuf chain.
+ */
+
+u16_t
+inet_chksum_pseudo(struct pbuf *p,
+       struct ip_addr *src, struct ip_addr *dest,
+       u8_t proto, u16_t proto_len)
+{
+  u32_t acc;
+  struct pbuf *q;
+  u8_t swapped;
+
+  acc = 0;
+  swapped = 0;
+  /* iterate through all pbuf in chain */
+  for(q = p; q != NULL; q = q->next) {
+    LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): checksumming pbuf %p (has next %p) \n",
+      (void *)q, (void *)q->next));
+    acc += LWIP_CHKSUM(q->payload, q->len);
+    /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): unwrapped lwip_chksum()=%lx \n", acc));*/
+    while (acc >> 16) {
+      acc = (acc & 0xffffUL) + (acc >> 16);
+    }
+    if (q->len % 2 != 0) {
+      swapped = 1 - swapped;
+      acc = ((acc & 0xff) << 8) | ((acc & 0xff00UL) >> 8);
+    }
+    /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): wrapped lwip_chksum()=%lx \n", acc));*/
+  }
+
+  if (swapped) {
+    acc = ((acc & 0xff) << 8) | ((acc & 0xff00UL) >> 8);
+  }
+  acc += (src->addr & 0xffffUL);
+  acc += ((src->addr >> 16) & 0xffffUL);
+  acc += (dest->addr & 0xffffUL);
+  acc += ((dest->addr >> 16) & 0xffffUL);
+  acc += (u32_t)htons((u16_t)proto);
+  acc += (u32_t)htons(proto_len);
+
+  while (acc >> 16) {
+    acc = (acc & 0xffffUL) + (acc >> 16);
+  }
+  LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): pbuf chain lwip_chksum()=%lx\n", acc));
+  return (u16_t)~(acc & 0xffffUL);
+}
+
+/* inet_chksum:
+ *
+ * Calculates the Internet checksum over a portion of memory. Used primarely for IP
+ * and ICMP.
+ */
+
+u16_t
+inet_chksum(void *dataptr, u16_t len)
+{
+  u32_t acc;
+
+  acc = LWIP_CHKSUM(dataptr, len);
+  while (acc >> 16) {
+    acc = (acc & 0xffff) + (acc >> 16);
+  }
+  return (u16_t)~(acc & 0xffff);
+}
+
+u16_t
+inet_chksum_pbuf(struct pbuf *p)
+{
+  u32_t acc;
+  struct pbuf *q;
+  u8_t swapped;
+
+  acc = 0;
+  swapped = 0;
+  for(q = p; q != NULL; q = q->next) {
+    acc += LWIP_CHKSUM(q->payload, q->len);
+    while (acc >> 16) {
+      acc = (acc & 0xffffUL) + (acc >> 16);
+    }
+    if (q->len % 2 != 0) {
+      swapped = 1 - swapped;
+      acc = (acc & 0x00ffUL << 8) | (acc & 0xff00UL >> 8);
+    }
+  }
+
+  if (swapped) {
+    acc = ((acc & 0x00ffUL) << 8) | ((acc & 0xff00UL) >> 8);
+  }
+  return (u16_t)~(acc & 0xffffUL);
+}
+
+/* Here for now until needed in other places in lwIP */
+#ifndef isascii
+#define in_range(c, lo, up)  ((u8_t)c >= lo && (u8_t)c <= up)
+#define isascii(c)           in_range(c, 0x20, 0x7f)
+#define isdigit(c)           in_range(c, '0', '9')
+#define isxdigit(c)          (isdigit(c) || in_range(c, 'a', 'f') || in_range(c, 'A', 'F'))
+#define islower(c)           in_range(c, 'a', 'z')
+#define isspace(c)           (c == ' ' || c == '\f' || c == '\n' || c == '\r' || c == '\t' || c == '\v')
+#endif		
+		
+
+ /*
+  * Ascii internet address interpretation routine.
+  * The value returned is in network order.
+  */
+
+ /*  */
+ /* inet_addr */
+ u32_t inet_addr(const char *cp)
+ {
+     struct in_addr val;
+
+     if (inet_aton(cp, &val)) {
+         return (val.s_addr);
+     }
+     return (INADDR_NONE);
+ }
+
+ /*
+  * Check whether "cp" is a valid ascii representation
+  * of an Internet address and convert to a binary address.
+  * Returns 1 if the address is valid, 0 if not.
+  * This replaces inet_addr, the return value from which
+  * cannot distinguish between failure and a local broadcast address.
+  */
+ /*  */
+ /* inet_aton */
+ int inet_aton(const char *cp, struct in_addr *addr)
+ {
+     u32_t val;
+     int base, n;
+     char c;
+     u32_t parts[4];
+     u32_t* pp = parts;
+
+     c = *cp;
+     for (;;) {
+         /*
+          * Collect number up to ``.''.
+          * Values are specified as for C:
+          * 0x=hex, 0=octal, isdigit=decimal.
+          */
+         if (!isdigit(c))
+             return (0);
+         val = 0; base = 10;
+         if (c == '0') {
+             c = *++cp;
+             if (c == 'x' || c == 'X')
+                 base = 16, c = *++cp;
+             else
+                 base = 8;
+         }
+         for (;;) {
+             if (isdigit(c)) {
+                 val = (val * base) + (int)(c - '0');
+                 c = *++cp;
+             } else if (base == 16 && isxdigit(c)) {
+                 val = (val << 4) |
+                     (int)(c + 10 - (islower(c) ? 'a' : 'A'));
+                 c = *++cp;
+             } else
+             break;
+         }
+         if (c == '.') {
+             /*
+              * Internet format:
+              *  a.b.c.d
+              *  a.b.c   (with c treated as 16 bits)
+              *  a.b (with b treated as 24 bits)
+              */
+             if (pp >= parts + 3)
+                 return (0);
+             *pp++ = val;
+             c = *++cp;
+         } else
+             break;
+     }
+     /*
+      * Check for trailing characters.
+      */
+     if (c != '\0' && (!isascii(c) || !isspace(c)))
+         return (0);
+     /*
+      * Concoct the address according to
+      * the number of parts specified.
+      */
+     n = pp - parts + 1;
+     switch (n) {
+
+     case 0:
+         return (0);     /* initial nondigit */
+
+     case 1:             /* a -- 32 bits */
+         break;
+
+     case 2:             /* a.b -- 8.24 bits */
+         if (val > 0xffffff)
+             return (0);
+         val |= parts[0] << 24;
+         break;
+
+     case 3:             /* a.b.c -- 8.8.16 bits */
+         if (val > 0xffff)
+             return (0);
+         val |= (parts[0] << 24) | (parts[1] << 16);
+         break;
+
+     case 4:             /* a.b.c.d -- 8.8.8.8 bits */
+         if (val > 0xff)
+             return (0);
+         val |= (parts[0] << 24) | (parts[1] << 16) | (parts[2] << 8);
+         break;
+     }
+     if (addr)
+         addr->s_addr = htonl(val);
+     return (1);
+ }
+
+/* Convert numeric IP address into decimal dotted ASCII representation.
+ * returns ptr to static buffer; not reentrant!
+ */
+char *inet_ntoa(struct in_addr addr)
+{
+  static char str[16];
+  u32_t s_addr = addr.s_addr;
+  char inv[3];
+  char *rp;
+  u8_t *ap;
+  u8_t rem;
+  u8_t n;
+  u8_t i;
+
+  rp = str;
+  ap = (u8_t *)&s_addr;
+  for(n = 0; n < 4; n++) {
+    i = 0;
+    do {
+      rem = *ap % (u8_t)10;
+      *ap /= (u8_t)10;
+      inv[i++] = '0' + rem;
+    } while(*ap);
+    while(i--)
+      *rp++ = inv[i];
+    *rp++ = '.';
+    ap++;
+  }
+  *--rp = 0;
+  return str;
+}
+
+
+#ifndef BYTE_ORDER
+#error BYTE_ORDER is not defined
+#endif
+#if BYTE_ORDER == LITTLE_ENDIAN
+
+u16_t
+htons(u16_t n)
+{
+  return ((n & 0xff) << 8) | ((n & 0xff00) >> 8);
+}
+
+u16_t
+ntohs(u16_t n)
+{
+  return htons(n);
+}
+
+u32_t
+htonl(u32_t n)
+{
+  return ((n & 0xff) << 24) |
+    ((n & 0xff00) << 8) |
+    ((n & 0xff0000) >> 8) |
+    ((n & 0xff000000) >> 24);
+}
+
+u32_t
+ntohl(u32_t n)
+{
+  return htonl(n);
+}
+
+#endif /* BYTE_ORDER == LITTLE_ENDIAN */
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/inet6.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/inet6.c
new file mode 100644
index 000000000..aebc6f381
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/inet6.c
@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+
+/* inet6.c
+ *
+ * Functions common to all TCP/IP modules, such as the Internet checksum and the
+ * byte order functions.
+ *
+ */
+
+
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+#include "lwip/inet.h"
+
+
+
+/* chksum:
+ *
+ * Sums up all 16 bit words in a memory portion. Also includes any odd byte.
+ * This function is used by the other checksum functions.
+ *
+ * For now, this is not optimized. Must be optimized for the particular processor
+ * arcitecture on which it is to run. Preferebly coded in assembler.
+ */
+
+static u32_t
+chksum(void *dataptr, u16_t len)
+{
+  u16_t *sdataptr = dataptr;
+  u32_t acc;
+  
+  
+  for(acc = 0; len > 1; len -= 2) {
+    acc += *sdataptr++;
+  }
+
+  /* add up any odd byte */
+  if (len == 1) {
+    acc += htons((u16_t)(*(u8_t *)dataptr) << 8);
+  }
+
+  return acc;
+
+}
+
+/* inet_chksum_pseudo:
+ *
+ * Calculates the pseudo Internet checksum used by TCP and UDP for a pbuf chain.
+ */
+
+u16_t
+inet_chksum_pseudo(struct pbuf *p,
+       struct ip_addr *src, struct ip_addr *dest,
+       u8_t proto, u32_t proto_len)
+{
+  u32_t acc;
+  struct pbuf *q;
+  u8_t swapped, i;
+
+  acc = 0;
+  swapped = 0;
+  for(q = p; q != NULL; q = q->next) {    
+    acc += chksum(q->payload, q->len);
+    while (acc >> 16) {
+      acc = (acc & 0xffff) + (acc >> 16);
+    }
+    if (q->len % 2 != 0) {
+      swapped = 1 - swapped;
+      acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8);
+    }
+  }
+
+  if (swapped) {
+    acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8);
+  }
+  
+  for(i = 0; i < 8; i++) {
+    acc += ((u16_t *)src->addr)[i] & 0xffff;
+    acc += ((u16_t *)dest->addr)[i] & 0xffff;
+    while (acc >> 16) {
+      acc = (acc & 0xffff) + (acc >> 16);
+    }
+  }
+  acc += (u16_t)htons((u16_t)proto);
+  acc += ((u16_t *)&proto_len)[0] & 0xffff;
+  acc += ((u16_t *)&proto_len)[1] & 0xffff;
+
+  while (acc >> 16) {
+    acc = (acc & 0xffff) + (acc >> 16);
+  }
+  return ~(acc & 0xffff);
+}
+
+/* inet_chksum:
+ *
+ * Calculates the Internet checksum over a portion of memory. Used primarely for IP
+ * and ICMP.
+ */
+
+u16_t
+inet_chksum(void *dataptr, u16_t len)
+{
+  u32_t acc, sum;
+
+  acc = chksum(dataptr, len);
+  sum = (acc & 0xffff) + (acc >> 16);
+  sum += (sum >> 16);
+  return ~(sum & 0xffff);
+}
+
+u16_t
+inet_chksum_pbuf(struct pbuf *p)
+{
+  u32_t acc;
+  struct pbuf *q;
+  u8_t swapped;
+  
+  acc = 0;
+  swapped = 0;
+  for(q = p; q != NULL; q = q->next) {
+    acc += chksum(q->payload, q->len);
+    while (acc >> 16) {
+      acc = (acc & 0xffff) + (acc >> 16);
+    }    
+    if (q->len % 2 != 0) {
+      swapped = 1 - swapped;
+      acc = (acc & 0xff << 8) | (acc & 0xff00 >> 8);
+    }
+  }
+ 
+  if (swapped) {
+    acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8);
+  }
+  return ~(acc & 0xffff);
+}
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv4/icmp.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv4/icmp.c
new file mode 100644
index 000000000..45525e44c
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv4/icmp.c
@@ -0,0 +1,205 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+/* Some ICMP messages should be passed to the transport protocols. This
+   is not implemented. */
+
+#include "lwip/opt.h"
+
+#include "lwip/icmp.h"
+#include "lwip/inet.h"
+#include "lwip/ip.h"
+#include "lwip/def.h"
+
+#include "lwip/stats.h"
+
+#include "lwip/snmp.h"
+
+#include 
+
+void
+icmp_input(struct pbuf *p, struct netif *inp)
+{
+  unsigned char type;
+  unsigned char code;
+  struct icmp_echo_hdr *iecho;
+  struct ip_hdr *iphdr;
+  struct ip_addr tmpaddr;
+  u16_t hlen;
+
+  ICMP_STATS_INC(icmp.recv);
+  snmp_inc_icmpinmsgs();
+
+
+  iphdr = p->payload;
+  hlen = IPH_HL(iphdr) * 4;
+  if (pbuf_header(p, -((s16_t)hlen)) || (p->tot_len < sizeof(u16_t)*2)) {
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: short ICMP (%u bytes) received\n", p->tot_len));
+    pbuf_free(p);
+    ICMP_STATS_INC(icmp.lenerr);
+    snmp_inc_icmpinerrors();
+    return;
+  }
+
+  type = *((u8_t *)p->payload);
+  code = *(((u8_t *)p->payload)+1);
+  switch (type) {
+  case ICMP_ECHO:
+    /* broadcast or multicast destination address? */
+    if (ip_addr_isbroadcast(&iphdr->dest, inp) || ip_addr_ismulticast(&iphdr->dest)) {
+      LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: Not echoing to multicast or broadcast pings\n"));
+      ICMP_STATS_INC(icmp.err);
+      pbuf_free(p);
+      return;
+    }
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ping\n"));
+    if (p->tot_len < sizeof(struct icmp_echo_hdr)) {
+      LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: bad ICMP echo received\n"));
+      pbuf_free(p);
+      ICMP_STATS_INC(icmp.lenerr);
+      snmp_inc_icmpinerrors();
+
+      return;
+    }
+    iecho = p->payload;
+    if (inet_chksum_pbuf(p) != 0) {
+      LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo\n"));
+      pbuf_free(p);
+      ICMP_STATS_INC(icmp.chkerr);
+      snmp_inc_icmpinerrors();
+      return;
+    }
+    tmpaddr.addr = iphdr->src.addr;
+    iphdr->src.addr = iphdr->dest.addr;
+    iphdr->dest.addr = tmpaddr.addr;
+    ICMPH_TYPE_SET(iecho, ICMP_ER);
+    /* adjust the checksum */
+    if (iecho->chksum >= htons(0xffff - (ICMP_ECHO << 8))) {
+      iecho->chksum += htons(ICMP_ECHO << 8) + 1;
+    } else {
+      iecho->chksum += htons(ICMP_ECHO << 8);
+    }
+    ICMP_STATS_INC(icmp.xmit);
+    /* increase number of messages attempted to send */
+    snmp_inc_icmpoutmsgs();
+    /* increase number of echo replies attempted to send */
+    snmp_inc_icmpoutechoreps();
+
+    pbuf_header(p, hlen);
+    ip_output_if(p, &(iphdr->src), IP_HDRINCL,
+		 IPH_TTL(iphdr), 0, IP_PROTO_ICMP, inp);
+    break;
+  default:
+  LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ICMP type %d code %d not supported.\n", (int)type, (int)code));
+    ICMP_STATS_INC(icmp.proterr);
+    ICMP_STATS_INC(icmp.drop);
+  }
+  pbuf_free(p);
+}
+
+void
+icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t)
+{
+  struct pbuf *q;
+  struct ip_hdr *iphdr;
+  struct icmp_dur_hdr *idur;
+
+  q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM);
+  /* ICMP header + IP header + 8 bytes of data */
+
+  iphdr = p->payload;
+
+  idur = q->payload;
+  ICMPH_TYPE_SET(idur, ICMP_DUR);
+  ICMPH_CODE_SET(idur, t);
+
+  memcpy((char *)q->payload + 8, p->payload, IP_HLEN + 8);
+
+  /* calculate checksum */
+  idur->chksum = 0;
+  idur->chksum = inet_chksum(idur, q->len);
+  ICMP_STATS_INC(icmp.xmit);
+  /* increase number of messages attempted to send */
+  snmp_inc_icmpoutmsgs();
+  /* increase number of destination unreachable messages attempted to send */
+  snmp_inc_icmpoutdestunreachs();
+
+  ip_output(q, NULL, &(iphdr->src),
+	    ICMP_TTL, 0, IP_PROTO_ICMP);
+  pbuf_free(q);
+}
+
+#if IP_FORWARD
+void
+icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t)
+{
+  struct pbuf *q;
+  struct ip_hdr *iphdr;
+  struct icmp_te_hdr *tehdr;
+
+  q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM);
+
+  iphdr = p->payload;
+  LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded from "));
+  ip_addr_debug_print(ICMP_DEBUG, &(iphdr->src));
+  LWIP_DEBUGF(ICMP_DEBUG, (" to "));
+  ip_addr_debug_print(ICMP_DEBUG, &(iphdr->dest));
+  LWIP_DEBUGF(ICMP_DEBUG, ("\n"));
+
+  tehdr = q->payload;
+  ICMPH_TYPE_SET(tehdr, ICMP_TE);
+  ICMPH_CODE_SET(tehdr, t);
+
+  /* copy fields from original packet */
+  memcpy((char *)q->payload + 8, (char *)p->payload, IP_HLEN + 8);
+
+  /* calculate checksum */
+  tehdr->chksum = 0;
+  tehdr->chksum = inet_chksum(tehdr, q->len);
+  ICMP_STATS_INC(icmp.xmit);
+  /* increase number of messages attempted to send */
+  snmp_inc_icmpoutmsgs();
+  /* increase number of destination unreachable messages attempted to send */
+  snmp_inc_icmpouttimeexcds();
+  ip_output(q, NULL, &(iphdr->src),
+	    ICMP_TTL, 0, IP_PROTO_ICMP);
+  pbuf_free(q);
+}
+
+#endif /* IP_FORWARD */
+
+
+
+
+
+
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv4/ip.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv4/ip.c
new file mode 100644
index 000000000..3d419c958
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv4/ip.c
@@ -0,0 +1,508 @@
+/* @file
+ *
+ * This is the IP layer implementation for incoming and outgoing IP traffic.
+ * 
+ * @see ip_frag.c
+ *
+ */
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/ip.h"
+#include "lwip/ip_frag.h"
+#include "lwip/inet.h"
+#include "lwip/netif.h"
+#include "lwip/icmp.h"
+#include "lwip/raw.h"
+#include "lwip/udp.h"
+#include "lwip/tcp.h"
+
+#include "lwip/stats.h"
+
+#include "arch/perf.h"
+
+#include "lwip/snmp.h"
+#if LWIP_DHCP
+#  include "lwip/dhcp.h"
+#endif /* LWIP_DHCP */
+
+
+/**
+ * Initializes the IP layer.
+ */
+
+void
+ip_init(void)
+{
+  /* no initializations as of yet */
+}
+
+/**
+ * Finds the appropriate network interface for a given IP address. It
+ * searches the list of network interfaces linearly. A match is found
+ * if the masked IP address of the network interface equals the masked
+ * IP address given to the function.
+ */
+
+struct netif *
+ip_route(struct ip_addr *dest)
+{
+  struct netif *netif;
+
+  /* iterate through netifs */
+  for(netif = netif_list; netif != NULL; netif = netif->next) {
+    /* network mask matches? */
+    if (ip_addr_netcmp(dest, &(netif->ip_addr), &(netif->netmask))) {
+      /* return netif on which to forward IP packet */
+      return netif;
+    }
+  }
+  /* no matching netif found, use default netif */
+  return netif_default;
+}
+#if IP_FORWARD
+
+/**
+ * Forwards an IP packet. It finds an appropriate route for the
+ * packet, decrements the TTL value of the packet, adjusts the
+ * checksum and outputs the packet on the appropriate interface.
+ */
+
+static struct netif *
+ip_forward(struct pbuf *p, struct ip_hdr *iphdr, struct netif *inp)
+{
+  struct netif *netif;
+
+  PERF_START;
+  /* Find network interface where to forward this IP packet to. */
+  netif = ip_route((struct ip_addr *)&(iphdr->dest));
+  if (netif == NULL) {
+    LWIP_DEBUGF(IP_DEBUG, ("ip_forward: no forwarding route for 0x%lx found\n",
+                      iphdr->dest.addr));
+    snmp_inc_ipnoroutes();
+    return (struct netif *)NULL;
+  }
+  /* Do not forward packets onto the same network interface on which
+   * they arrived. */
+  if (netif == inp) {
+    LWIP_DEBUGF(IP_DEBUG, ("ip_forward: not bouncing packets back on incoming interface.\n"));
+    snmp_inc_ipnoroutes();
+    return (struct netif *)NULL;
+  }
+
+  /* decrement TTL */
+  IPH_TTL_SET(iphdr, IPH_TTL(iphdr) - 1);
+  /* send ICMP if TTL == 0 */
+  if (IPH_TTL(iphdr) == 0) {
+    /* Don't send ICMP messages in response to ICMP messages */
+    if (IPH_PROTO(iphdr) != IP_PROTO_ICMP) {
+      icmp_time_exceeded(p, ICMP_TE_TTL);
+      snmp_inc_icmpouttimeexcds();
+    }
+    return (struct netif *)NULL;
+  }
+
+  /* Incrementally update the IP checksum. */
+  if (IPH_CHKSUM(iphdr) >= htons(0xffff - 0x100)) {
+    IPH_CHKSUM_SET(iphdr, IPH_CHKSUM(iphdr) + htons(0x100) + 1);
+  } else {
+    IPH_CHKSUM_SET(iphdr, IPH_CHKSUM(iphdr) + htons(0x100));
+  }
+
+  LWIP_DEBUGF(IP_DEBUG, ("ip_forward: forwarding packet to 0x%lx\n",
+                    iphdr->dest.addr));
+
+  IP_STATS_INC(ip.fw);
+  IP_STATS_INC(ip.xmit);
+    snmp_inc_ipforwdatagrams();
+
+  PERF_STOP("ip_forward");
+  /* transmit pbuf on chosen interface */
+  netif->output(netif, p, (struct ip_addr *)&(iphdr->dest));
+  return netif;
+}
+#endif /* IP_FORWARD */
+
+/**
+ * This function is called by the network interface device driver when
+ * an IP packet is received. The function does the basic checks of the
+ * IP header such as packet size being at least larger than the header
+ * size etc. If the packet was not destined for us, the packet is
+ * forwarded (using ip_forward). The IP checksum is always checked.
+ *
+ * Finally, the packet is sent to the upper layer protocol input function.
+ * 
+ * 
+ * 
+ */
+
+err_t
+ip_input(struct pbuf *p, struct netif *inp) {
+  struct ip_hdr *iphdr;
+  struct netif *netif;
+  u16_t iphdrlen;
+
+  IP_STATS_INC(ip.recv);
+  snmp_inc_ipinreceives();
+
+  /* identify the IP header */
+  iphdr = p->payload;
+  if (IPH_V(iphdr) != 4) {
+    LWIP_DEBUGF(IP_DEBUG | 1, ("IP packet dropped due to bad version number %u\n", IPH_V(iphdr)));
+    ip_debug_print(p);
+    pbuf_free(p);
+    IP_STATS_INC(ip.err);
+    IP_STATS_INC(ip.drop);
+    snmp_inc_ipunknownprotos();
+    return ERR_OK;
+  }
+  /* obtain IP header length in number of 32-bit words */
+  iphdrlen = IPH_HL(iphdr);
+  /* calculate IP header length in bytes */
+  iphdrlen *= 4;
+
+  /* header length exceeds first pbuf length? */
+  if (iphdrlen > p->len) {
+    LWIP_DEBUGF(IP_DEBUG | 2, ("IP header (len %u) does not fit in first pbuf (len %u), IP packet droppped.\n",
+      iphdrlen, p->len));
+    /* free (drop) packet pbufs */
+    pbuf_free(p);
+    IP_STATS_INC(ip.lenerr);
+    IP_STATS_INC(ip.drop);
+    snmp_inc_ipindiscards();
+    return ERR_OK;
+  }
+
+  /* verify checksum */
+#if CHECKSUM_CHECK_IP
+  if (inet_chksum(iphdr, iphdrlen) != 0) {
+
+    LWIP_DEBUGF(IP_DEBUG | 2, ("Checksum (0x%x) failed, IP packet dropped.\n", inet_chksum(iphdr, iphdrlen)));
+    ip_debug_print(p);
+    pbuf_free(p);
+    IP_STATS_INC(ip.chkerr);
+    IP_STATS_INC(ip.drop);
+    snmp_inc_ipindiscards();
+    return ERR_OK;
+  }
+#endif
+
+  /* Trim pbuf. This should have been done at the netif layer,
+   * but we'll do it anyway just to be sure that its done. */
+  pbuf_realloc(p, ntohs(IPH_LEN(iphdr)));
+
+  /* match packet against an interface, i.e. is this packet for us? */
+  for (netif = netif_list; netif != NULL; netif = netif->next) {
+
+    LWIP_DEBUGF(IP_DEBUG, ("ip_input: iphdr->dest 0x%lx netif->ip_addr 0x%lx (0x%lx, 0x%lx, 0x%lx)\n",
+      iphdr->dest.addr, netif->ip_addr.addr,
+      iphdr->dest.addr & netif->netmask.addr,
+      netif->ip_addr.addr & netif->netmask.addr,
+      iphdr->dest.addr & ~(netif->netmask.addr)));
+
+    /* interface is up and configured? */
+    if ((netif_is_up(netif)) && (!ip_addr_isany(&(netif->ip_addr))))
+    {
+      /* unicast to this interface address? */
+      if (ip_addr_cmp(&(iphdr->dest), &(netif->ip_addr)) ||
+         /* or broadcast on this interface network address? */
+         ip_addr_isbroadcast(&(iphdr->dest), netif)) {
+        LWIP_DEBUGF(IP_DEBUG, ("ip_input: packet accepted on interface %c%c\n",
+          netif->name[0], netif->name[1]));
+        /* break out of for loop */
+        break;
+      }
+    }
+  }
+#if LWIP_DHCP
+  /* Pass DHCP messages regardless of destination address. DHCP traffic is addressed
+   * using link layer addressing (such as Ethernet MAC) so we must not filter on IP.
+   * According to RFC 1542 section 3.1.1, referred by RFC 2131).
+   */
+  if (netif == NULL) {
+    /* remote port is DHCP server? */
+    if (IPH_PROTO(iphdr) == IP_PROTO_UDP) {
+      LWIP_DEBUGF(IP_DEBUG | DBG_TRACE | 1, ("ip_input: UDP packet to DHCP client port %u\n",
+        ntohs(((struct udp_hdr *)((u8_t *)iphdr + iphdrlen))->dest)));
+      if (ntohs(((struct udp_hdr *)((u8_t *)iphdr + iphdrlen))->dest) == DHCP_CLIENT_PORT) {
+        LWIP_DEBUGF(IP_DEBUG | DBG_TRACE | 1, ("ip_input: DHCP packet accepted.\n"));
+        netif = inp;
+      }
+    }
+  }
+#endif /* LWIP_DHCP */
+  /* packet not for us? */
+  if (netif == NULL) {
+    /* packet not for us, route or discard */
+    LWIP_DEBUGF(IP_DEBUG | DBG_TRACE | 1, ("ip_input: packet not for us.\n"));
+#if IP_FORWARD
+    /* non-broadcast packet? */
+    if (!ip_addr_isbroadcast(&(iphdr->dest), inp)) {
+      /* try to forward IP packet on (other) interfaces */
+      ip_forward(p, iphdr, inp);
+    }
+    else
+#endif /* IP_FORWARD */
+    {
+      snmp_inc_ipindiscards();
+    }
+    pbuf_free(p);
+    return ERR_OK;
+  }
+  /* packet consists of multiple fragments? */
+  if ((IPH_OFFSET(iphdr) & htons(IP_OFFMASK | IP_MF)) != 0) {
+#if IP_REASSEMBLY /* packet fragment reassembly code present? */
+    LWIP_DEBUGF(IP_DEBUG, ("IP packet is a fragment (id=0x%04x tot_len=%u len=%u MF=%u offset=%u), calling ip_reass()\n",
+      ntohs(IPH_ID(iphdr)), p->tot_len, ntohs(IPH_LEN(iphdr)), !!(IPH_OFFSET(iphdr) & htons(IP_MF)), (ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK)*8));
+    /* reassemble the packet*/
+    p = ip_reass(p);
+    /* packet not fully reassembled yet? */
+    if (p == NULL) {
+      return ERR_OK;
+    }
+    iphdr = p->payload;
+#else /* IP_REASSEMBLY == 0, no packet fragment reassembly code present */
+    pbuf_free(p);
+    LWIP_DEBUGF(IP_DEBUG | 2, ("IP packet dropped since it was fragmented (0x%x) (while IP_REASSEMBLY == 0).\n",
+      ntohs(IPH_OFFSET(iphdr))));
+    IP_STATS_INC(ip.opterr);
+    IP_STATS_INC(ip.drop);
+    snmp_inc_ipunknownprotos();
+    return ERR_OK;
+#endif /* IP_REASSEMBLY */
+  }
+
+#if IP_OPTIONS == 0 /* no support for IP options in the IP header? */
+  if (iphdrlen > IP_HLEN) {
+    LWIP_DEBUGF(IP_DEBUG | 2, ("IP packet dropped since there were IP options (while IP_OPTIONS == 0).\n"));
+    pbuf_free(p);
+    IP_STATS_INC(ip.opterr);
+    IP_STATS_INC(ip.drop);
+    snmp_inc_ipunknownprotos();
+    return ERR_OK;
+  }
+#endif /* IP_OPTIONS == 0 */
+
+  /* send to upper layers */
+  LWIP_DEBUGF(IP_DEBUG, ("ip_input: \n"));
+  ip_debug_print(p);
+  LWIP_DEBUGF(IP_DEBUG, ("ip_input: p->len %d p->tot_len %d\n", p->len, p->tot_len));
+
+#if LWIP_RAW
+  /* raw input did not eat the packet? */
+  if (raw_input(p, inp) == 0) {
+#endif /* LWIP_RAW */
+
+  switch (IPH_PROTO(iphdr)) {
+#if LWIP_UDP
+  case IP_PROTO_UDP:
+  case IP_PROTO_UDPLITE:
+    snmp_inc_ipindelivers();
+    udp_input(p, inp);
+    break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+  case IP_PROTO_TCP:
+    snmp_inc_ipindelivers();
+    tcp_input(p, inp);
+    break;
+#endif /* LWIP_TCP */
+  case IP_PROTO_ICMP:
+    snmp_inc_ipindelivers();
+    icmp_input(p, inp);
+    break;
+  default:
+    /* send ICMP destination protocol unreachable unless is was a broadcast */
+    if (!ip_addr_isbroadcast(&(iphdr->dest), inp) &&
+        !ip_addr_ismulticast(&(iphdr->dest))) {
+      p->payload = iphdr;
+      icmp_dest_unreach(p, ICMP_DUR_PROTO);
+    }
+    pbuf_free(p);
+
+    LWIP_DEBUGF(IP_DEBUG | 2, ("Unsupported transport protocol %d\n", IPH_PROTO(iphdr)));
+
+    IP_STATS_INC(ip.proterr);
+    IP_STATS_INC(ip.drop);
+    snmp_inc_ipunknownprotos();
+  }
+#if LWIP_RAW
+  } /* LWIP_RAW */
+#endif
+  return ERR_OK;
+}
+
+/**
+ * Sends an IP packet on a network interface. This function constructs
+ * the IP header and calculates the IP header checksum. If the source
+ * IP address is NULL, the IP address of the outgoing network
+ * interface is filled in as source address.
+ */
+
+err_t
+ip_output_if(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+             u8_t ttl, u8_t tos,
+             u8_t proto, struct netif *netif)
+{
+  struct ip_hdr *iphdr;
+  u16_t ip_id = 0;
+
+  snmp_inc_ipoutrequests();
+
+  if (dest != IP_HDRINCL) {
+    if (pbuf_header(p, IP_HLEN)) {
+      LWIP_DEBUGF(IP_DEBUG | 2, ("ip_output: not enough room for IP header in pbuf\n"));
+
+      IP_STATS_INC(ip.err);
+      snmp_inc_ipoutdiscards();
+      return ERR_BUF;
+    }
+
+    iphdr = p->payload;
+
+    IPH_TTL_SET(iphdr, ttl);
+    IPH_PROTO_SET(iphdr, proto);
+
+    ip_addr_set(&(iphdr->dest), dest);
+
+    IPH_VHLTOS_SET(iphdr, 4, IP_HLEN / 4, tos);
+    IPH_LEN_SET(iphdr, htons(p->tot_len));
+    IPH_OFFSET_SET(iphdr, htons(IP_DF));
+    IPH_ID_SET(iphdr, htons(ip_id));
+    ++ip_id;
+
+    if (ip_addr_isany(src)) {
+      ip_addr_set(&(iphdr->src), &(netif->ip_addr));
+    } else {
+      ip_addr_set(&(iphdr->src), src);
+    }
+
+    IPH_CHKSUM_SET(iphdr, 0);
+#if CHECKSUM_GEN_IP
+    IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN));
+#endif
+  } else {
+    iphdr = p->payload;
+    dest = &(iphdr->dest);
+  }
+
+#if IP_FRAG
+  /* don't fragment if interface has mtu set to 0 [loopif] */
+  if (netif->mtu && (p->tot_len > netif->mtu))
+    return ip_frag(p,netif,dest);
+#endif
+
+  IP_STATS_INC(ip.xmit);
+
+  LWIP_DEBUGF(IP_DEBUG, ("ip_output_if: %c%c%u\n", netif->name[0], netif->name[1], netif->num));
+  ip_debug_print(p);
+
+  LWIP_DEBUGF(IP_DEBUG, ("netif->output()"));
+
+  return netif->output(netif, p, dest);
+}
+
+/**
+ * Simple interface to ip_output_if. It finds the outgoing network
+ * interface and calls upon ip_output_if to do the actual work.
+ */
+
+err_t
+ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+          u8_t ttl, u8_t tos, u8_t proto)
+{
+  struct netif *netif;
+
+  if ((netif = ip_route(dest)) == NULL) {
+    LWIP_DEBUGF(IP_DEBUG | 2, ("ip_output: No route to 0x%lx\n", dest->addr));
+
+    IP_STATS_INC(ip.rterr);
+    snmp_inc_ipoutdiscards();
+    return ERR_RTE;
+  }
+
+  return ip_output_if(p, src, dest, ttl, tos, proto, netif);
+}
+
+#if IP_DEBUG
+void
+ip_debug_print(struct pbuf *p)
+{
+  struct ip_hdr *iphdr = p->payload;
+  u8_t *payload;
+
+  payload = (u8_t *)iphdr + IP_HLEN;
+
+  LWIP_DEBUGF(IP_DEBUG, ("IP header:\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|%2d |%2d |  0x%02x |     %5u     | (v, hl, tos, len)\n",
+                    IPH_V(iphdr),
+                    IPH_HL(iphdr),
+                    IPH_TOS(iphdr),
+                    ntohs(IPH_LEN(iphdr))));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|    %5u      |%u%u%u|    %4u   | (id, flags, offset)\n",
+                    ntohs(IPH_ID(iphdr)),
+                    ntohs(IPH_OFFSET(iphdr)) >> 15 & 1,
+                    ntohs(IPH_OFFSET(iphdr)) >> 14 & 1,
+                    ntohs(IPH_OFFSET(iphdr)) >> 13 & 1,
+                    ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|  %3u  |  %3u  |    0x%04x     | (ttl, proto, chksum)\n",
+                    IPH_TTL(iphdr),
+                    IPH_PROTO(iphdr),
+                    ntohs(IPH_CHKSUM(iphdr))));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|  %3u  |  %3u  |  %3u  |  %3u  | (src)\n",
+                    ip4_addr1(&iphdr->src),
+                    ip4_addr2(&iphdr->src),
+                    ip4_addr3(&iphdr->src),
+                    ip4_addr4(&iphdr->src)));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|  %3u  |  %3u  |  %3u  |  %3u  | (dest)\n",
+                    ip4_addr1(&iphdr->dest),
+                    ip4_addr2(&iphdr->dest),
+                    ip4_addr3(&iphdr->dest),
+                    ip4_addr4(&iphdr->dest)));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+}
+#endif /* IP_DEBUG */
+
+
+
+
+
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv4/ip_addr.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv4/ip_addr.c
new file mode 100644
index 000000000..cb465eef2
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv4/ip_addr.c
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/ip_addr.h"
+#include "lwip/inet.h"
+#include "lwip/netif.h"
+
+/* used by IP_ADDR_ANY and IP_ADDR_BROADCAST in ip_addr.h */
+const struct ip_addr ip_addr_any = { 0x00000000UL };
+const struct ip_addr ip_addr_broadcast = { 0xffffffffUL };
+
+/* Determine if an address is a broadcast address on a network interface 
+ * 
+ * @param addr address to be checked
+ * @param netif the network interface against which the address is checked
+ * @return returns non-zero if the address is a broadcast address
+ *
+ */
+
+u8_t ip_addr_isbroadcast(struct ip_addr *addr, struct netif *netif)
+{
+  /* all ones (broadcast) or all zeroes (old skool broadcast) */
+  if ((addr->addr == ip_addr_broadcast.addr) ||
+      (addr->addr == ip_addr_any.addr))
+    return 1;
+  /* no broadcast support on this network interface? */
+  else if ((netif->flags & NETIF_FLAG_BROADCAST) == 0)
+    /* the given address cannot be a broadcast address
+     * nor can we check against any broadcast addresses */
+    return 0;
+  /* address matches network interface address exactly? => no broadcast */
+  else if (addr->addr == netif->ip_addr.addr)
+    return 0;
+  /*  on the same (sub) network... */
+  else if (ip_addr_netcmp(addr, &(netif->ip_addr), &(netif->netmask))
+         /* ...and host identifier bits are all ones? =>... */
+          && ((addr->addr & ~netif->netmask.addr) ==
+           (ip_addr_broadcast.addr & ~netif->netmask.addr)))
+    /* => network broadcast address */
+    return 1;
+  else
+    return 0;
+}
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv4/ip_frag.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv4/ip_frag.c
new file mode 100644
index 000000000..380929317
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv4/ip_frag.c
@@ -0,0 +1,345 @@
+/* @file
+ * 
+ * This is the IP packet segmentation and reassembly implementation.
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Jani Monoses  
+ * original reassembly code by Adam Dunkels 
+ * 
+ */
+
+#include "lwip/opt.h"
+#include "lwip/sys.h"
+#include "lwip/ip.h"
+#include "lwip/ip_frag.h"
+#include "lwip/netif.h"
+
+#include "lwip/stats.h"
+
+#include 
+
+/*
+ * Copy len bytes from offset in pbuf to buffer 
+ *
+ * helper used by both ip_reass and ip_frag
+ */
+static struct pbuf *
+copy_from_pbuf(struct pbuf *p, u16_t * offset,
+           u8_t * buffer, u16_t len)
+{
+  u16_t l;
+
+  p->payload = (u8_t *)p->payload + *offset;
+  p->len -= *offset;
+  while (len) {
+    l = len < p->len ? len : p->len;
+    memcpy(buffer, p->payload, l);
+    buffer += l;
+    len -= l;
+    if (len)
+      p = p->next;
+    else
+      *offset = l;
+  }
+  return p;
+}
+
+#define IP_REASS_BUFSIZE 5760
+#define IP_REASS_MAXAGE 30
+#define IP_REASS_TMO 1000
+
+static u8_t ip_reassbuf[IP_HLEN + IP_REASS_BUFSIZE];
+static u8_t ip_reassbitmap[IP_REASS_BUFSIZE / (8 * 8)];
+static const u8_t bitmap_bits[8] = { 0xff, 0x7f, 0x3f, 0x1f,
+  0x0f, 0x07, 0x03, 0x01
+};
+static u16_t ip_reasslen;
+static u8_t ip_reassflags;
+#define IP_REASS_FLAG_LASTFRAG 0x01
+
+static u8_t ip_reasstmr;
+
+/* Reassembly timer */ 
+static void 
+ip_reass_timer(void *arg)
+{
+  (void)arg;
+  if (ip_reasstmr > 1) {
+    ip_reasstmr--;
+    sys_timeout(IP_REASS_TMO, ip_reass_timer, NULL);
+  } else if (ip_reasstmr == 1)
+  ip_reasstmr = 0;
+}
+
+struct pbuf *
+ip_reass(struct pbuf *p)
+{
+  struct pbuf *q;
+  struct ip_hdr *fraghdr, *iphdr;
+  u16_t offset, len;
+  u16_t i;
+
+  IPFRAG_STATS_INC(ip_frag.recv);
+
+  iphdr = (struct ip_hdr *) ip_reassbuf;
+  fraghdr = (struct ip_hdr *) p->payload;
+  /* If ip_reasstmr is zero, no packet is present in the buffer, so we
+     write the IP header of the fragment into the reassembly
+     buffer. The timer is updated with the maximum age. */
+  if (ip_reasstmr == 0) {
+    LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass: new packet\n"));
+    memcpy(iphdr, fraghdr, IP_HLEN);
+    ip_reasstmr = IP_REASS_MAXAGE;
+    sys_timeout(IP_REASS_TMO, ip_reass_timer, NULL);
+    ip_reassflags = 0;
+    /* Clear the bitmap. */
+    memset(ip_reassbitmap, 0, sizeof(ip_reassbitmap));
+  }
+
+  /* Check if the incoming fragment matches the one currently present
+     in the reasembly buffer. If so, we proceed with copying the
+     fragment into the buffer. */
+  if (ip_addr_cmp(&iphdr->src, &fraghdr->src) &&
+      ip_addr_cmp(&iphdr->dest, &fraghdr->dest) &&
+      IPH_ID(iphdr) == IPH_ID(fraghdr)) {
+    LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass: matching old packet\n"));
+    IPFRAG_STATS_INC(ip_frag.cachehit);
+    /* Find out the offset in the reassembly buffer where we should
+       copy the fragment. */
+    len = ntohs(IPH_LEN(fraghdr)) - IPH_HL(fraghdr) * 4;
+    offset = (ntohs(IPH_OFFSET(fraghdr)) & IP_OFFMASK) * 8;
+
+    /* If the offset or the offset + fragment length overflows the
+       reassembly buffer, we discard the entire packet. */
+    if (offset > IP_REASS_BUFSIZE || offset + len > IP_REASS_BUFSIZE) {
+      LWIP_DEBUGF(IP_REASS_DEBUG,
+       ("ip_reass: fragment outside of buffer (%d:%d/%d).\n", offset,
+        offset + len, IP_REASS_BUFSIZE));
+      sys_untimeout(ip_reass_timer, NULL);
+      ip_reasstmr = 0;
+      goto nullreturn;
+    }
+
+    /* Copy the fragment into the reassembly buffer, at the right
+       offset. */
+    LWIP_DEBUGF(IP_REASS_DEBUG,
+     ("ip_reass: copying with offset %d into %d:%d\n", offset,
+      IP_HLEN + offset, IP_HLEN + offset + len));
+    i = IPH_HL(fraghdr) * 4;
+    copy_from_pbuf(p, &i, &ip_reassbuf[IP_HLEN + offset], len);
+
+    /* Update the bitmap. */
+    if (offset / (8 * 8) == (offset + len) / (8 * 8)) {
+      LWIP_DEBUGF(IP_REASS_DEBUG,
+       ("ip_reass: updating single byte in bitmap.\n"));
+      /* If the two endpoints are in the same byte, we only update
+         that byte. */
+      ip_reassbitmap[offset / (8 * 8)] |=
+    bitmap_bits[(offset / 8) & 7] &
+    ~bitmap_bits[((offset + len) / 8) & 7];
+    } else {
+      /* If the two endpoints are in different bytes, we update the
+         bytes in the endpoints and fill the stuff inbetween with
+         0xff. */
+      ip_reassbitmap[offset / (8 * 8)] |= bitmap_bits[(offset / 8) & 7];
+      LWIP_DEBUGF(IP_REASS_DEBUG,
+       ("ip_reass: updating many bytes in bitmap (%d:%d).\n",
+        1 + offset / (8 * 8), (offset + len) / (8 * 8)));
+      for (i = 1 + offset / (8 * 8); i < (offset + len) / (8 * 8); ++i) {
+  ip_reassbitmap[i] = 0xff;
+      }
+      ip_reassbitmap[(offset + len) / (8 * 8)] |=
+    ~bitmap_bits[((offset + len) / 8) & 7];
+    }
+
+    /* If this fragment has the More Fragments flag set to zero, we
+       know that this is the last fragment, so we can calculate the
+       size of the entire packet. We also set the
+       IP_REASS_FLAG_LASTFRAG flag to indicate that we have received
+       the final fragment. */
+
+    if ((ntohs(IPH_OFFSET(fraghdr)) & IP_MF) == 0) {
+      ip_reassflags |= IP_REASS_FLAG_LASTFRAG;
+      ip_reasslen = offset + len;
+      LWIP_DEBUGF(IP_REASS_DEBUG,
+       ("ip_reass: last fragment seen, total len %d\n",
+        ip_reasslen));
+    }
+
+    /* Finally, we check if we have a full packet in the buffer. We do
+       this by checking if we have the last fragment and if all bits
+       in the bitmap are set. */
+    if (ip_reassflags & IP_REASS_FLAG_LASTFRAG) {
+      /* Check all bytes up to and including all but the last byte in
+         the bitmap. */
+      for (i = 0; i < ip_reasslen / (8 * 8) - 1; ++i) {
+  if (ip_reassbitmap[i] != 0xff) {
+    LWIP_DEBUGF(IP_REASS_DEBUG,
+     ("ip_reass: last fragment seen, bitmap %d/%d failed (%x)\n",
+      i, ip_reasslen / (8 * 8) - 1, ip_reassbitmap[i]));
+    goto nullreturn;
+  }
+      }
+      /* Check the last byte in the bitmap. It should contain just the
+         right amount of bits. */
+      if (ip_reassbitmap[ip_reasslen / (8 * 8)] !=
+    (u8_t) ~ bitmap_bits[ip_reasslen / 8 & 7]) {
+  LWIP_DEBUGF(IP_REASS_DEBUG,
+         ("ip_reass: last fragment seen, bitmap %d didn't contain %x (%x)\n",
+    ip_reasslen / (8 * 8), ~bitmap_bits[ip_reasslen / 8 & 7],
+    ip_reassbitmap[ip_reasslen / (8 * 8)]));
+  goto nullreturn;
+      }
+
+      /* Pretend to be a "normal" (i.e., not fragmented) IP packet
+         from now on. */
+      ip_reasslen += IP_HLEN;
+
+      IPH_LEN_SET(iphdr, htons(ip_reasslen));
+      IPH_OFFSET_SET(iphdr, 0);
+      IPH_CHKSUM_SET(iphdr, 0);
+      IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN));
+
+      /* If we have come this far, we have a full packet in the
+         buffer, so we allocate a pbuf and copy the packet into it. We
+         also reset the timer. */
+      sys_untimeout(ip_reass_timer, NULL);
+      ip_reasstmr = 0;
+      pbuf_free(p);
+      p = pbuf_alloc(PBUF_LINK, ip_reasslen, PBUF_POOL);
+      if (p != NULL) {
+  i = 0;
+  for (q = p; q != NULL; q = q->next) {
+    /* Copy enough bytes to fill this pbuf in the chain. The
+       available data in the pbuf is given by the q->len
+       variable. */
+    LWIP_DEBUGF(IP_REASS_DEBUG,
+     ("ip_reass: memcpy from %p (%d) to %p, %d bytes\n",
+      (void *)&ip_reassbuf[i], i, q->payload,
+      q->len > ip_reasslen - i ? ip_reasslen - i : q->len));
+    memcpy(q->payload, &ip_reassbuf[i],
+    q->len > ip_reasslen - i ? ip_reasslen - i : q->len);
+    i += q->len;
+  }
+  IPFRAG_STATS_INC(ip_frag.fw);
+      } else {
+  IPFRAG_STATS_INC(ip_frag.memerr);
+      }
+      LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass: p %p\n", (void*)p));
+      return p;
+    }
+  }
+
+nullreturn:
+  IPFRAG_STATS_INC(ip_frag.drop);
+  pbuf_free(p);
+  return NULL;
+}
+
+#define MAX_MTU 1500
+static u8_t buf[MEM_ALIGN_SIZE(MAX_MTU)];
+
+/**
+ * Fragment an IP packet if too large
+ *
+ * Chop the packet in mtu sized chunks and send them in order
+ * by using a fixed size static memory buffer (PBUF_ROM)
+ */
+err_t 
+ip_frag(struct pbuf *p, struct netif *netif, struct ip_addr *dest)
+{
+  struct pbuf *rambuf;
+  struct pbuf *header;
+  struct ip_hdr *iphdr;
+  u16_t nfb = 0;
+  u16_t left, cop;
+  u16_t mtu = netif->mtu;
+  u16_t ofo, omf;
+  u16_t last;
+  u16_t poff = IP_HLEN;
+  u16_t tmp;
+
+  /* Get a RAM based MTU sized pbuf */
+  rambuf = pbuf_alloc(PBUF_LINK, 0, PBUF_REF);
+  rambuf->tot_len = rambuf->len = mtu;
+  rambuf->payload = MEM_ALIGN((void *)buf);
+
+  /* Copy the IP header in it */
+  iphdr = rambuf->payload;
+  memcpy(iphdr, p->payload, IP_HLEN);
+
+  /* Save original offset */
+  tmp = ntohs(IPH_OFFSET(iphdr));
+  ofo = tmp & IP_OFFMASK;
+  omf = tmp & IP_MF;
+
+  left = p->tot_len - IP_HLEN;
+
+  while (left) {
+    last = (left <= mtu - IP_HLEN);
+
+    /* Set new offset and MF flag */
+    ofo += nfb;
+    tmp = omf | (IP_OFFMASK & (ofo));
+    if (!last)
+      tmp = tmp | IP_MF;
+    IPH_OFFSET_SET(iphdr, htons(tmp));
+
+    /* Fill this fragment */
+    nfb = (mtu - IP_HLEN) / 8;
+    cop = last ? left : nfb * 8;
+
+    p = copy_from_pbuf(p, &poff, (u8_t *) iphdr + IP_HLEN, cop);
+
+    /* Correct header */
+    IPH_LEN_SET(iphdr, htons(cop + IP_HLEN));
+    IPH_CHKSUM_SET(iphdr, 0);
+    IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN));
+
+    if (last)
+      pbuf_realloc(rambuf, left + IP_HLEN);
+    /* This part is ugly: we alloc a RAM based pbuf for 
+     * the link level header for each chunk and then 
+     * free it.A PBUF_ROM style pbuf for which pbuf_header
+     * worked would make things simpler.
+     */
+    header = pbuf_alloc(PBUF_LINK, 0, PBUF_RAM);
+    pbuf_chain(header, rambuf);
+    netif->output(netif, header, dest);
+    IPFRAG_STATS_INC(ip_frag.xmit);
+    pbuf_free(header);
+
+    left -= cop;
+  }
+  pbuf_free(rambuf);
+  return ERR_OK;
+}
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv6/README b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv6/README
new file mode 100644
index 000000000..362000486
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv6/README
@@ -0,0 +1 @@
+IPv6 support in lwIP is very experimental.
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv6/icmp6.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv6/icmp6.c
new file mode 100644
index 000000000..76d13ca17
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv6/icmp6.c
@@ -0,0 +1,184 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+/* Some ICMP messages should be passed to the transport protocols. This
+   is not implemented. */
+
+#include "lwip/opt.h"
+
+#include "lwip/icmp.h"
+#include "lwip/inet.h"
+#include "lwip/ip.h"
+#include "lwip/def.h"
+
+#include "lwip/stats.h"
+
+
+void
+icmp_input(struct pbuf *p, struct netif *inp)
+{
+  unsigned char type;
+  struct icmp_echo_hdr *iecho;
+  struct ip_hdr *iphdr;
+  struct ip_addr tmpaddr;
+
+#ifdef ICMP_STATS
+  ++lwip_stats.icmp.recv;
+#endif /* ICMP_STATS */
+
+  /* TODO: check length before accessing payload! */
+
+  type = ((char *)p->payload)[0];
+
+  switch (type) {
+  case ICMP6_ECHO:
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ping\n"));
+
+    if (p->tot_len < sizeof(struct icmp_echo_hdr)) {
+      LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: bad ICMP echo received\n"));
+
+      pbuf_free(p);
+#ifdef ICMP_STATS
+      ++lwip_stats.icmp.lenerr;
+#endif /* ICMP_STATS */
+
+      return;
+    }
+    iecho = p->payload;
+    iphdr = (struct ip_hdr *)((char *)p->payload - IP_HLEN);
+    if (inet_chksum_pbuf(p) != 0) {
+      LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo (%x)\n", inet_chksum_pseudo(p, &(iphdr->src), &(iphdr->dest), IP_PROTO_ICMP, p->tot_len)));
+
+#ifdef ICMP_STATS
+      ++lwip_stats.icmp.chkerr;
+#endif /* ICMP_STATS */
+    /*      return;*/
+    }
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp: p->len %d p->tot_len %d\n", p->len, p->tot_len));
+    ip_addr_set(&tmpaddr, &(iphdr->src));
+    ip_addr_set(&(iphdr->src), &(iphdr->dest));
+    ip_addr_set(&(iphdr->dest), &tmpaddr);
+    iecho->type = ICMP6_ER;
+    /* adjust the checksum */
+    if (iecho->chksum >= htons(0xffff - (ICMP6_ECHO << 8))) {
+      iecho->chksum += htons(ICMP6_ECHO << 8) + 1;
+    } else {
+      iecho->chksum += htons(ICMP6_ECHO << 8);
+    }
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo (%x)\n", inet_chksum_pseudo(p, &(iphdr->src), &(iphdr->dest), IP_PROTO_ICMP, p->tot_len)));
+#ifdef ICMP_STATS
+    ++lwip_stats.icmp.xmit;
+#endif /* ICMP_STATS */
+
+    /*    LWIP_DEBUGF("icmp: p->len %u p->tot_len %u\n", p->len, p->tot_len);*/
+    ip_output_if (p, &(iphdr->src), IP_HDRINCL,
+     iphdr->hoplim, IP_PROTO_ICMP, inp);
+    break;
+  default:
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ICMP type %d not supported.\n", (int)type));
+#ifdef ICMP_STATS
+    ++lwip_stats.icmp.proterr;
+    ++lwip_stats.icmp.drop;
+#endif /* ICMP_STATS */
+  }
+
+  pbuf_free(p);
+}
+
+void
+icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t)
+{
+  struct pbuf *q;
+  struct ip_hdr *iphdr;
+  struct icmp_dur_hdr *idur;
+
+  q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM);
+  /* ICMP header + IP header + 8 bytes of data */
+
+  iphdr = p->payload;
+
+  idur = q->payload;
+  idur->type = (char)ICMP6_DUR;
+  idur->icode = (char)t;
+
+  memcpy((char *)q->payload + 8, p->payload, IP_HLEN + 8);
+
+  /* calculate checksum */
+  idur->chksum = 0;
+  idur->chksum = inet_chksum(idur, q->len);
+#ifdef ICMP_STATS
+  ++lwip_stats.icmp.xmit;
+#endif /* ICMP_STATS */
+
+  ip_output(q, NULL,
+      (struct ip_addr *)&(iphdr->src), ICMP_TTL, IP_PROTO_ICMP);
+  pbuf_free(q);
+}
+
+void
+icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t)
+{
+  struct pbuf *q;
+  struct ip_hdr *iphdr;
+  struct icmp_te_hdr *tehdr;
+
+  LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded\n"));
+
+  q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM);
+
+  iphdr = p->payload;
+
+  tehdr = q->payload;
+  tehdr->type = (char)ICMP6_TE;
+  tehdr->icode = (char)t;
+
+  /* copy fields from original packet */
+  memcpy((char *)q->payload + 8, (char *)p->payload, IP_HLEN + 8);
+
+  /* calculate checksum */
+  tehdr->chksum = 0;
+  tehdr->chksum = inet_chksum(tehdr, q->len);
+#ifdef ICMP_STATS
+  ++lwip_stats.icmp.xmit;
+#endif /* ICMP_STATS */
+  ip_output(q, NULL,
+      (struct ip_addr *)&(iphdr->src), ICMP_TTL, IP_PROTO_ICMP);
+  pbuf_free(q);
+}
+
+
+
+
+
+
+
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv6/ip6.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv6/ip6.c
new file mode 100644
index 000000000..1a7f74ac8
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv6/ip6.c
@@ -0,0 +1,386 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+
+
+/* ip.c
+ *
+ * This is the code for the IP layer for IPv6.
+ *
+ */
+
+
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/ip.h"
+#include "lwip/inet.h"
+#include "lwip/netif.h"
+#include "lwip/icmp.h"
+#include "lwip/udp.h"
+#include "lwip/tcp.h"
+
+#include "lwip/stats.h"
+
+#include "arch/perf.h"
+
+/* ip_init:
+ *
+ * Initializes the IP layer.
+ */
+
+void
+ip_init(void)
+{
+}
+
+/* ip_route:
+ *
+ * Finds the appropriate network interface for a given IP address. It searches the
+ * list of network interfaces linearly. A match is found if the masked IP address of
+ * the network interface equals the masked IP address given to the function.
+ */
+
+struct netif *
+ip_route(struct ip_addr *dest)
+{
+  struct netif *netif;
+
+  for(netif = netif_list; netif != NULL; netif = netif->next) {
+    if (ip_addr_netcmp(dest, &(netif->ip_addr), &(netif->netmask))) {
+      return netif;
+    }
+  }
+
+  return netif_default;
+}
+
+/* ip_forward:
+ *
+ * Forwards an IP packet. It finds an appropriate route for the packet, decrements
+ * the TTL value of the packet, adjusts the checksum and outputs the packet on the
+ * appropriate interface.
+ */
+
+static void
+ip_forward(struct pbuf *p, struct ip_hdr *iphdr)
+{
+  struct netif *netif;
+
+  PERF_START;
+
+  if ((netif = ip_route((struct ip_addr *)&(iphdr->dest))) == NULL) {
+
+    LWIP_DEBUGF(IP_DEBUG, ("ip_input: no forwarding route found for "));
+#if IP_DEBUG
+    ip_addr_debug_print(IP_DEBUG, &(iphdr->dest));
+#endif /* IP_DEBUG */
+    LWIP_DEBUGF(IP_DEBUG, ("\n"));
+    pbuf_free(p);
+    return;
+  }
+  /* Decrement TTL and send ICMP if ttl == 0. */
+  if (--iphdr->hoplim == 0) {
+    /* Don't send ICMP messages in response to ICMP messages */
+    if (iphdr->nexthdr != IP_PROTO_ICMP) {
+      icmp_time_exceeded(p, ICMP_TE_TTL);
+    }
+    pbuf_free(p);
+    return;
+  }
+
+  /* Incremental update of the IP checksum. */
+  /*  if (iphdr->chksum >= htons(0xffff - 0x100)) {
+    iphdr->chksum += htons(0x100) + 1;
+  } else {
+    iphdr->chksum += htons(0x100);
+    }*/
+
+
+  LWIP_DEBUGF(IP_DEBUG, ("ip_forward: forwarding packet to "));
+#if IP_DEBUG
+  ip_addr_debug_print(IP_DEBUG, &(iphdr->dest));
+#endif /* IP_DEBUG */
+  LWIP_DEBUGF(IP_DEBUG, ("\n"));
+
+#ifdef IP_STATS
+  ++lwip_stats.ip.fw;
+  ++lwip_stats.ip.xmit;
+#endif /* IP_STATS */
+
+  PERF_STOP("ip_forward");
+
+  netif->output(netif, p, (struct ip_addr *)&(iphdr->dest));
+}
+
+/* ip_input:
+ *
+ * This function is called by the network interface device driver when an IP packet is
+ * received. The function does the basic checks of the IP header such as packet size
+ * being at least larger than the header size etc. If the packet was not destined for
+ * us, the packet is forwarded (using ip_forward). The IP checksum is always checked.
+ *
+ * Finally, the packet is sent to the upper layer protocol input function.
+ */
+
+void
+ip_input(struct pbuf *p, struct netif *inp) {
+  struct ip_hdr *iphdr;
+  struct netif *netif;
+
+
+  PERF_START;
+
+#if IP_DEBUG
+  ip_debug_print(p);
+#endif /* IP_DEBUG */
+
+
+#ifdef IP_STATS
+  ++lwip_stats.ip.recv;
+#endif /* IP_STATS */
+
+  /* identify the IP header */
+  iphdr = p->payload;
+
+
+  if (iphdr->v != 6) {
+    LWIP_DEBUGF(IP_DEBUG, ("IP packet dropped due to bad version number\n"));
+#if IP_DEBUG
+    ip_debug_print(p);
+#endif /* IP_DEBUG */
+    pbuf_free(p);
+#ifdef IP_STATS
+    ++lwip_stats.ip.err;
+    ++lwip_stats.ip.drop;
+#endif /* IP_STATS */
+    return;
+  }
+
+  /* is this packet for us? */
+  for(netif = netif_list; netif != NULL; netif = netif->next) {
+#if IP_DEBUG
+    LWIP_DEBUGF(IP_DEBUG, ("ip_input: iphdr->dest "));
+    ip_addr_debug_print(IP_DEBUG, &(iphdr->dest));
+    LWIP_DEBUGF(IP_DEBUG, ("netif->ip_addr "));
+    ip_addr_debug_print(IP_DEBUG, &(netif->ip_addr));
+    LWIP_DEBUGF(IP_DEBUG, ("\n"));
+#endif /* IP_DEBUG */
+    if (ip_addr_cmp(&(iphdr->dest), &(netif->ip_addr))) {
+      break;
+    }
+  }
+
+
+  if (netif == NULL) {
+    /* packet not for us, route or discard */
+#ifdef IP_FORWARD
+    ip_forward(p, iphdr);
+#endif
+    pbuf_free(p);
+    return;
+  }
+
+  pbuf_realloc(p, IP_HLEN + ntohs(iphdr->len));
+
+  /* send to upper layers */
+#if IP_DEBUG
+  /*  LWIP_DEBUGF("ip_input: \n");
+  ip_debug_print(p);
+  LWIP_DEBUGF("ip_input: p->len %u p->tot_len %u\n", p->len, p->tot_len);*/
+#endif /* IP_DEBUG */
+
+
+  pbuf_header(p, -IP_HLEN);
+
+  switch (iphdr->nexthdr) {
+  case IP_PROTO_UDP:
+    udp_input(p);
+    break;
+  case IP_PROTO_TCP:
+    tcp_input(p);
+    break;
+  case IP_PROTO_ICMP:
+    icmp_input(p, inp);
+    break;
+  default:
+    /* send ICMP destination protocol unreachable */
+    icmp_dest_unreach(p, ICMP_DUR_PROTO);
+    pbuf_free(p);
+    LWIP_DEBUGF(IP_DEBUG, ("Unsupported transport protocol %u\n",
+          iphdr->nexthdr));
+
+#ifdef IP_STATS
+    ++lwip_stats.ip.proterr;
+    ++lwip_stats.ip.drop;
+#endif /* IP_STATS */
+
+  }
+  PERF_STOP("ip_input");
+}
+
+
+/* ip_output_if:
+ *
+ * Sends an IP packet on a network interface. This function constructs the IP header
+ * and calculates the IP header checksum. If the source IP address is NULL,
+ * the IP address of the outgoing network interface is filled in as source address.
+ */
+
+err_t
+ip_output_if (struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+       u8_t ttl,
+       u8_t proto, struct netif *netif)
+{
+  struct ip_hdr *iphdr;
+
+  PERF_START;
+
+  printf("len %u tot_len %u\n", p->len, p->tot_len);
+  if (pbuf_header(p, IP_HLEN)) {
+    LWIP_DEBUGF(IP_DEBUG, ("ip_output: not enough room for IP header in pbuf\n"));
+#ifdef IP_STATS
+    ++lwip_stats.ip.err;
+#endif /* IP_STATS */
+
+    return ERR_BUF;
+  }
+  printf("len %u tot_len %u\n", p->len, p->tot_len);
+
+  iphdr = p->payload;
+
+
+  if (dest != IP_HDRINCL) {
+    printf("!IP_HDRLINCL\n");
+    iphdr->hoplim = ttl;
+    iphdr->nexthdr = proto;
+    iphdr->len = htons(p->tot_len - IP_HLEN);
+    ip_addr_set(&(iphdr->dest), dest);
+
+    iphdr->v = 6;
+
+    if (ip_addr_isany(src)) {
+      ip_addr_set(&(iphdr->src), &(netif->ip_addr));
+    } else {
+      ip_addr_set(&(iphdr->src), src);
+    }
+
+  } else {
+    dest = &(iphdr->dest);
+  }
+
+#ifdef IP_STATS
+  ++lwip_stats.ip.xmit;
+#endif /* IP_STATS */
+
+  LWIP_DEBUGF(IP_DEBUG, ("ip_output_if: %c%c (len %u)\n", netif->name[0], netif->name[1], p->tot_len));
+#if IP_DEBUG
+  ip_debug_print(p);
+#endif /* IP_DEBUG */
+
+  PERF_STOP("ip_output_if");
+  return netif->output(netif, p, dest);
+}
+
+/* ip_output:
+ *
+ * Simple interface to ip_output_if. It finds the outgoing network interface and
+ * calls upon ip_output_if to do the actual work.
+ */
+
+err_t
+ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+    u8_t ttl, u8_t proto)
+{
+  struct netif *netif;
+  if ((netif = ip_route(dest)) == NULL) {
+    LWIP_DEBUGF(IP_DEBUG, ("ip_output: No route to 0x%lx\n", dest->addr));
+#ifdef IP_STATS
+    ++lwip_stats.ip.rterr;
+#endif /* IP_STATS */
+    return ERR_RTE;
+  }
+
+  return ip_output_if (p, src, dest, ttl, proto, netif);
+}
+
+#if IP_DEBUG
+void
+ip_debug_print(struct pbuf *p)
+{
+  struct ip_hdr *iphdr = p->payload;
+  char *payload;
+
+  payload = (char *)iphdr + IP_HLEN;
+
+  LWIP_DEBUGF(IP_DEBUG, ("IP header:\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|%2d |  %x%x  |      %x%x           | (v, traffic class, flow label)\n",
+        iphdr->v,
+        iphdr->tclass1, iphdr->tclass2,
+        iphdr->flow1, iphdr->flow2));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|    %5u      | %2u  |  %2u   | (len, nexthdr, hoplim)\n",
+        ntohs(iphdr->len),
+        iphdr->nexthdr,
+        iphdr->hoplim));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|       %4lx      |       %4lx     | (src)\n",
+        ntohl(iphdr->src.addr[0]) >> 16 & 0xffff,
+        ntohl(iphdr->src.addr[0]) & 0xffff));
+  LWIP_DEBUGF(IP_DEBUG, ("|       %4lx      |       %4lx     | (src)\n",
+        ntohl(iphdr->src.addr[1]) >> 16 & 0xffff,
+        ntohl(iphdr->src.addr[1]) & 0xffff));
+  LWIP_DEBUGF(IP_DEBUG, ("|       %4lx      |       %4lx     | (src)\n",
+        ntohl(iphdr->src.addr[2]) >> 16 & 0xffff,
+        ntohl(iphdr->src.addr[2]) & 0xffff));
+  LWIP_DEBUGF(IP_DEBUG, ("|       %4lx      |       %4lx     | (src)\n",
+        ntohl(iphdr->src.addr[3]) >> 16 & 0xffff,
+        ntohl(iphdr->src.addr[3]) & 0xffff));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|       %4lx      |       %4lx     | (dest)\n",
+        ntohl(iphdr->dest.addr[0]) >> 16 & 0xffff,
+        ntohl(iphdr->dest.addr[0]) & 0xffff));
+  LWIP_DEBUGF(IP_DEBUG, ("|       %4lx      |       %4lx     | (dest)\n",
+        ntohl(iphdr->dest.addr[1]) >> 16 & 0xffff,
+        ntohl(iphdr->dest.addr[1]) & 0xffff));
+  LWIP_DEBUGF(IP_DEBUG, ("|       %4lx      |       %4lx     | (dest)\n",
+        ntohl(iphdr->dest.addr[2]) >> 16 & 0xffff,
+        ntohl(iphdr->dest.addr[2]) & 0xffff));
+  LWIP_DEBUGF(IP_DEBUG, ("|       %4lx      |       %4lx     | (dest)\n",
+        ntohl(iphdr->dest.addr[3]) >> 16 & 0xffff,
+        ntohl(iphdr->dest.addr[3]) & 0xffff));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+}
+#endif /* IP_DEBUG */
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv6/ip6_addr.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv6/ip6_addr.c
new file mode 100644
index 000000000..fbc03aa99
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv6/ip6_addr.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/ip_addr.h"
+#include "lwip/inet.h"
+
+
+int
+ip_addr_netcmp(struct ip_addr *addr1, struct ip_addr *addr2,
+                struct ip_addr *mask)
+{
+  return((addr1->addr[0] & mask->addr[0]) == (addr2->addr[0] & mask->addr[0]) &&
+         (addr1->addr[1] & mask->addr[1]) == (addr2->addr[1] & mask->addr[1]) &&
+         (addr1->addr[2] & mask->addr[2]) == (addr2->addr[2] & mask->addr[2]) &&
+         (addr1->addr[3] & mask->addr[3]) == (addr2->addr[3] & mask->addr[3]));
+        
+}
+
+int
+ip_addr_cmp(struct ip_addr *addr1, struct ip_addr *addr2)
+{
+  return(addr1->addr[0] == addr2->addr[0] &&
+         addr1->addr[1] == addr2->addr[1] &&
+         addr1->addr[2] == addr2->addr[2] &&
+         addr1->addr[3] == addr2->addr[3]);
+}
+
+void
+ip_addr_set(struct ip_addr *dest, struct ip_addr *src)
+{
+  memcpy(dest, src, sizeof(struct ip_addr));
+  /*  dest->addr[0] = src->addr[0];
+  dest->addr[1] = src->addr[1];
+  dest->addr[2] = src->addr[2];
+  dest->addr[3] = src->addr[3];*/
+}
+
+int
+ip_addr_isany(struct ip_addr *addr)
+{
+  if (addr == NULL) return 1;
+  return((addr->addr[0] | addr->addr[1] | addr->addr[2] | addr->addr[3]) == 0);
+}
+
+
+/*#if IP_DEBUG*/
+void
+ip_addr_debug_print(struct ip_addr *addr)
+{
+  printf("%lx:%lx:%lx:%lx:%lx:%lx:%lx:%lx",
+         ntohl(addr->addr[0]) >> 16 & 0xffff,
+         ntohl(addr->addr[0]) & 0xffff,
+         ntohl(addr->addr[1]) >> 16 & 0xffff,
+         ntohl(addr->addr[1]) & 0xffff,
+         ntohl(addr->addr[2]) >> 16 & 0xffff,
+         ntohl(addr->addr[2]) & 0xffff,
+         ntohl(addr->addr[3]) >> 16 & 0xffff,
+         ntohl(addr->addr[3]) & 0xffff);
+}
+/*#endif*/ /* IP_DEBUG */
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/mem.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/mem.c
new file mode 100644
index 000000000..6e061684a
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/mem.c
@@ -0,0 +1,310 @@
+/** @file
+ *
+ * Dynamic memory manager
+ *
+ */
+
+/* 
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include 
+
+#include "lwip/arch.h"
+#include "lwip/opt.h"
+#include "lwip/def.h"
+#include "lwip/mem.h"
+
+#include "lwip/sys.h"
+
+#include "lwip/stats.h"
+
+struct mem {
+  mem_size_t next, prev;
+#if MEM_ALIGNMENT == 1
+  u8_t used;
+#elif MEM_ALIGNMENT == 2
+  u16_t used;
+#elif MEM_ALIGNMENT == 4
+  u32_t used;
+#elif MEM_ALIGNMENT == 8
+  u64_t used;
+#else
+#error "unhandled MEM_ALIGNMENT size"
+#endif /* MEM_ALIGNMENT */
+}; 
+
+static struct mem *ram_end;
+static u8_t ram[MEM_SIZE + sizeof(struct mem) + MEM_ALIGNMENT];
+
+#define MIN_SIZE 12
+#if 0 /* this one does not align correctly for some, resulting in crashes */
+#define SIZEOF_STRUCT_MEM (unsigned int)MEM_ALIGN_SIZE(sizeof(struct mem))
+#else
+#define SIZEOF_STRUCT_MEM (sizeof(struct mem) + \
+                          (((sizeof(struct mem) % MEM_ALIGNMENT) == 0)? 0 : \
+                          (4 - (sizeof(struct mem) % MEM_ALIGNMENT))))
+#endif
+
+static struct mem *lfree;   /* pointer to the lowest free block */
+
+static sys_sem_t mem_sem;
+
+static void
+plug_holes(struct mem *mem)
+{
+  struct mem *nmem;
+  struct mem *pmem;
+
+  LWIP_ASSERT("plug_holes: mem >= ram", (u8_t *)mem >= ram);
+  LWIP_ASSERT("plug_holes: mem < ram_end", (u8_t *)mem < (u8_t *)ram_end);
+  LWIP_ASSERT("plug_holes: mem->used == 0", mem->used == 0);
+  
+  /* plug hole forward */
+  LWIP_ASSERT("plug_holes: mem->next <= MEM_SIZE", mem->next <= MEM_SIZE);
+  
+  nmem = (struct mem *)&ram[mem->next];
+  if (mem != nmem && nmem->used == 0 && (u8_t *)nmem != (u8_t *)ram_end) {
+    if (lfree == nmem) {
+      lfree = mem;
+    }
+    mem->next = nmem->next;
+    ((struct mem *)&ram[nmem->next])->prev = (u8_t *)mem - ram;
+  }
+
+  /* plug hole backward */
+  pmem = (struct mem *)&ram[mem->prev];
+  if (pmem != mem && pmem->used == 0) {
+    if (lfree == mem) {
+      lfree = pmem;
+    }
+    pmem->next = mem->next;
+    ((struct mem *)&ram[mem->next])->prev = (u8_t *)pmem - ram;
+  }
+
+}
+void
+mem_init(void)
+{
+  struct mem *mem;
+
+  memset(ram, 0, MEM_SIZE);
+  mem = (struct mem *)ram;
+  mem->next = MEM_SIZE;
+  mem->prev = 0;
+  mem->used = 0;
+  ram_end = (struct mem *)&ram[MEM_SIZE];
+  ram_end->used = 1;
+  ram_end->next = MEM_SIZE;
+  ram_end->prev = MEM_SIZE;
+
+  mem_sem = sys_sem_new(1);
+
+  lfree = (struct mem *)ram;
+
+#if MEM_STATS
+  lwip_stats.mem.avail = MEM_SIZE;
+#endif /* MEM_STATS */
+}
+void
+mem_free(void *rmem)
+{
+  struct mem *mem;
+
+  if (rmem == NULL) {
+    LWIP_DEBUGF(MEM_DEBUG | DBG_TRACE | 2, ("mem_free(p == NULL) was called.\n"));
+    return;
+  }
+  
+  sys_sem_wait(mem_sem);
+
+  LWIP_ASSERT("mem_free: legal memory", (u8_t *)rmem >= (u8_t *)ram &&
+    (u8_t *)rmem < (u8_t *)ram_end);
+  
+  if ((u8_t *)rmem < (u8_t *)ram || (u8_t *)rmem >= (u8_t *)ram_end) {
+    LWIP_DEBUGF(MEM_DEBUG | 3, ("mem_free: illegal memory\n"));
+#if MEM_STATS
+    ++lwip_stats.mem.err;
+#endif /* MEM_STATS */
+    sys_sem_signal(mem_sem);
+    return;
+  }
+  mem = (struct mem *)((u8_t *)rmem - SIZEOF_STRUCT_MEM);
+
+  LWIP_ASSERT("mem_free: mem->used", mem->used);
+  
+  mem->used = 0;
+
+  if (mem < lfree) {
+    lfree = mem;
+  }
+  
+#if MEM_STATS
+  lwip_stats.mem.used -= mem->next - ((u8_t *)mem - ram);
+  
+#endif /* MEM_STATS */
+  plug_holes(mem);
+  sys_sem_signal(mem_sem);
+}
+void *
+mem_reallocm(void *rmem, mem_size_t newsize)
+{
+  void *nmem;
+  nmem = mem_malloc(newsize);
+  if (nmem == NULL) {
+    return mem_realloc(rmem, newsize);
+  }
+  memcpy(nmem, rmem, newsize);
+  mem_free(rmem);
+  return nmem;
+}
+
+void *
+mem_realloc(void *rmem, mem_size_t newsize)
+{
+  mem_size_t size;
+  mem_size_t ptr, ptr2;
+  struct mem *mem, *mem2;
+
+  /* Expand the size of the allocated memory region so that we can
+     adjust for alignment. */
+  if ((newsize % MEM_ALIGNMENT) != 0) {
+   newsize += MEM_ALIGNMENT - ((newsize + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT);
+  }
+  
+  if (newsize > MEM_SIZE) {
+    return NULL;
+  }
+  
+  sys_sem_wait(mem_sem);
+  
+  LWIP_ASSERT("mem_realloc: legal memory", (u8_t *)rmem >= (u8_t *)ram &&
+   (u8_t *)rmem < (u8_t *)ram_end);
+  
+  if ((u8_t *)rmem < (u8_t *)ram || (u8_t *)rmem >= (u8_t *)ram_end) {
+    LWIP_DEBUGF(MEM_DEBUG | 3, ("mem_realloc: illegal memory\n"));
+    return rmem;
+  }
+  mem = (struct mem *)((u8_t *)rmem - SIZEOF_STRUCT_MEM);
+
+  ptr = (u8_t *)mem - ram;
+
+  size = mem->next - ptr - SIZEOF_STRUCT_MEM;
+#if MEM_STATS
+  lwip_stats.mem.used -= (size - newsize);
+#endif /* MEM_STATS */
+  
+  if (newsize + SIZEOF_STRUCT_MEM + MIN_SIZE < size) {
+    ptr2 = ptr + SIZEOF_STRUCT_MEM + newsize;
+    mem2 = (struct mem *)&ram[ptr2];
+    mem2->used = 0;
+    mem2->next = mem->next;
+    mem2->prev = ptr;
+    mem->next = ptr2;
+    if (mem2->next != MEM_SIZE) {
+      ((struct mem *)&ram[mem2->next])->prev = ptr2;
+    }
+
+    plug_holes(mem2);
+  }
+  sys_sem_signal(mem_sem);  
+  return rmem;
+}
+void *
+mem_malloc(mem_size_t size)
+{
+  mem_size_t ptr, ptr2;
+  struct mem *mem, *mem2;
+
+  if (size == 0) {
+    return NULL;
+  }
+
+  /* Expand the size of the allocated memory region so that we can
+     adjust for alignment. */
+  if ((size % MEM_ALIGNMENT) != 0) {
+    size += MEM_ALIGNMENT - ((size + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT);
+  }
+  
+  if (size > MEM_SIZE) {
+    return NULL;
+  }
+  
+  sys_sem_wait(mem_sem);
+
+  for (ptr = (u8_t *)lfree - ram; ptr < MEM_SIZE; ptr = ((struct mem *)&ram[ptr])->next) {
+    mem = (struct mem *)&ram[ptr];
+    if (!mem->used &&
+       mem->next - (ptr + SIZEOF_STRUCT_MEM) >= size + SIZEOF_STRUCT_MEM) {
+      ptr2 = ptr + SIZEOF_STRUCT_MEM + size;
+      mem2 = (struct mem *)&ram[ptr2];
+
+      mem2->prev = ptr;      
+      mem2->next = mem->next;
+      mem->next = ptr2;      
+      if (mem2->next != MEM_SIZE) {
+        ((struct mem *)&ram[mem2->next])->prev = ptr2;
+      }
+      
+      mem2->used = 0;      
+      mem->used = 1;
+#if MEM_STATS
+      lwip_stats.mem.used += (size + SIZEOF_STRUCT_MEM);
+      /*      if (lwip_stats.mem.max < lwip_stats.mem.used) {
+        lwip_stats.mem.max = lwip_stats.mem.used;
+  } */
+      if (lwip_stats.mem.max < ptr2) {
+        lwip_stats.mem.max = ptr2;
+      }      
+#endif /* MEM_STATS */
+
+      if (mem == lfree) {
+  /* Find next free block after mem */
+        while (lfree->used && lfree != ram_end) {
+    lfree = (struct mem *)&ram[lfree->next];
+        }
+        LWIP_ASSERT("mem_malloc: !lfree->used", !lfree->used);
+      }
+      sys_sem_signal(mem_sem);
+      LWIP_ASSERT("mem_malloc: allocated memory not above ram_end.",
+       (mem_ptr_t)mem + SIZEOF_STRUCT_MEM + size <= (mem_ptr_t)ram_end);
+      LWIP_ASSERT("mem_malloc: allocated memory properly aligned.",
+       (unsigned long)((u8_t *)mem + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT == 0);
+      return (u8_t *)mem + SIZEOF_STRUCT_MEM;
+    }    
+  }
+  LWIP_DEBUGF(MEM_DEBUG | 2, ("mem_malloc: could not allocate %d bytes\n", (int)size));
+#if MEM_STATS
+  ++lwip_stats.mem.err;
+#endif /* MEM_STATS */  
+  sys_sem_signal(mem_sem);
+  return NULL;
+}
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/memp.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/memp.c
new file mode 100644
index 000000000..731c8cade
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/memp.c
@@ -0,0 +1,274 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/memp.h"
+
+#include "lwip/pbuf.h"
+#include "lwip/udp.h"
+#include "lwip/raw.h"
+#include "lwip/tcp.h"
+#include "lwip/api.h"
+#include "lwip/api_msg.h"
+#include "lwip/tcpip.h"
+
+#include "lwip/sys.h"
+#include "lwip/stats.h"
+
+struct memp {
+  struct memp *next;
+};
+
+
+
+static struct memp *memp_tab[MEMP_MAX];
+
+static const u16_t memp_sizes[MEMP_MAX] = {
+  sizeof(struct pbuf),
+  sizeof(struct raw_pcb),
+  sizeof(struct udp_pcb),
+  sizeof(struct tcp_pcb),
+  sizeof(struct tcp_pcb_listen),
+  sizeof(struct tcp_seg),
+  sizeof(struct netbuf),
+  sizeof(struct netconn),
+  sizeof(struct api_msg),
+  sizeof(struct tcpip_msg),
+  sizeof(struct sys_timeout)
+};
+
+static const u16_t memp_num[MEMP_MAX] = {
+  MEMP_NUM_PBUF,
+  MEMP_NUM_RAW_PCB,
+  MEMP_NUM_UDP_PCB,
+  MEMP_NUM_TCP_PCB,
+  MEMP_NUM_TCP_PCB_LISTEN,
+  MEMP_NUM_TCP_SEG,
+  MEMP_NUM_NETBUF,
+  MEMP_NUM_NETCONN,
+  MEMP_NUM_API_MSG,
+  MEMP_NUM_TCPIP_MSG,
+  MEMP_NUM_SYS_TIMEOUT
+};
+
+static u8_t memp_memory[(MEMP_NUM_PBUF *
+       MEM_ALIGN_SIZE(sizeof(struct pbuf) +
+          sizeof(struct memp)) +
+      MEMP_NUM_RAW_PCB *
+       MEM_ALIGN_SIZE(sizeof(struct raw_pcb) +
+          sizeof(struct memp)) +
+      MEMP_NUM_UDP_PCB *
+       MEM_ALIGN_SIZE(sizeof(struct udp_pcb) +
+          sizeof(struct memp)) +
+      MEMP_NUM_TCP_PCB *
+       MEM_ALIGN_SIZE(sizeof(struct tcp_pcb) +
+          sizeof(struct memp)) +
+      MEMP_NUM_TCP_PCB_LISTEN *
+       MEM_ALIGN_SIZE(sizeof(struct tcp_pcb_listen) +
+          sizeof(struct memp)) +
+      MEMP_NUM_TCP_SEG *
+       MEM_ALIGN_SIZE(sizeof(struct tcp_seg) +
+          sizeof(struct memp)) +
+      MEMP_NUM_NETBUF *
+       MEM_ALIGN_SIZE(sizeof(struct netbuf) +
+          sizeof(struct memp)) +
+      MEMP_NUM_NETCONN *
+       MEM_ALIGN_SIZE(sizeof(struct netconn) +
+          sizeof(struct memp)) +
+      MEMP_NUM_API_MSG *
+       MEM_ALIGN_SIZE(sizeof(struct api_msg) +
+          sizeof(struct memp)) +
+      MEMP_NUM_TCPIP_MSG *
+       MEM_ALIGN_SIZE(sizeof(struct tcpip_msg) +
+          sizeof(struct memp)) +
+      MEMP_NUM_SYS_TIMEOUT *
+       MEM_ALIGN_SIZE(sizeof(struct sys_timeout) +
+          sizeof(struct memp)))];
+
+
+#if !SYS_LIGHTWEIGHT_PROT
+static sys_sem_t mutex;
+#endif
+
+#if MEMP_SANITY_CHECK
+static int
+memp_sanity(void)
+{
+  int i, c;
+  struct memp *m, *n;
+
+  for(i = 0; i < MEMP_MAX; i++) {
+    for(m = memp_tab[i]; m != NULL; m = m->next) {
+      c = 1;
+      for(n = memp_tab[i]; n != NULL; n = n->next) {
+         if (n == m) {
+          --c;
+        }
+        if (c < 0) return 0; /* LW was: abort(); */
+      }
+    }
+  }
+  return 1;
+}
+#endif /* MEMP_SANITY_CHECK*/
+
+void
+memp_init(void)
+{
+  struct memp *m, *memp;
+  u16_t i, j;
+  u16_t size;
+      
+#if MEMP_STATS
+  for(i = 0; i < MEMP_MAX; ++i) {
+    lwip_stats.memp[i].used = lwip_stats.memp[i].max =
+      lwip_stats.memp[i].err = 0;
+    lwip_stats.memp[i].avail = memp_num[i];
+  }
+#endif /* MEMP_STATS */
+
+  memp = (struct memp *)&memp_memory[0];
+  for(i = 0; i < MEMP_MAX; ++i) {
+    size = MEM_ALIGN_SIZE(memp_sizes[i] + sizeof(struct memp));
+    if (memp_num[i] > 0) {
+      memp_tab[i] = memp;
+      m = memp;
+      
+      for(j = 0; j < memp_num[i]; ++j) {
+  m->next = (struct memp *)MEM_ALIGN((u8_t *)m + size);
+  memp = m;
+  m = m->next;
+      }
+      memp->next = NULL;
+      memp = m;
+    } else {
+      memp_tab[i] = NULL;
+    }
+  }
+
+#if !SYS_LIGHTWEIGHT_PROT
+  mutex = sys_sem_new(1);
+#endif
+
+  
+}
+
+void *
+memp_malloc(memp_t type)
+{
+  struct memp *memp;
+  void *mem;
+#if SYS_LIGHTWEIGHT_PROT
+  SYS_ARCH_DECL_PROTECT(old_level);
+#endif
+ 
+  LWIP_ASSERT("memp_malloc: type < MEMP_MAX", type < MEMP_MAX);
+
+#if SYS_LIGHTWEIGHT_PROT
+  SYS_ARCH_PROTECT(old_level);
+#else /* SYS_LIGHTWEIGHT_PROT */  
+  sys_sem_wait(mutex);
+#endif /* SYS_LIGHTWEIGHT_PROT */  
+
+  memp = memp_tab[type];
+  
+  if (memp != NULL) {    
+    memp_tab[type] = memp->next;    
+    memp->next = NULL;
+#if MEMP_STATS
+    ++lwip_stats.memp[type].used;
+    if (lwip_stats.memp[type].used > lwip_stats.memp[type].max) {
+      lwip_stats.memp[type].max = lwip_stats.memp[type].used;
+    }
+#endif /* MEMP_STATS */
+#if SYS_LIGHTWEIGHT_PROT
+    SYS_ARCH_UNPROTECT(old_level);
+#else /* SYS_LIGHTWEIGHT_PROT */
+    sys_sem_signal(mutex);
+#endif /* SYS_LIGHTWEIGHT_PROT */  
+    LWIP_ASSERT("memp_malloc: memp properly aligned",
+     ((mem_ptr_t)MEM_ALIGN((u8_t *)memp + sizeof(struct memp)) % MEM_ALIGNMENT) == 0);
+
+    mem = MEM_ALIGN((u8_t *)memp + sizeof(struct memp));
+    return mem;
+  } else {
+    LWIP_DEBUGF(MEMP_DEBUG | 2, ("memp_malloc: out of memory in pool %d\n", type));
+#if MEMP_STATS
+    ++lwip_stats.memp[type].err;
+#endif /* MEMP_STATS */
+#if SYS_LIGHTWEIGHT_PROT
+  SYS_ARCH_UNPROTECT(old_level);
+#else /* SYS_LIGHTWEIGHT_PROT */
+  sys_sem_signal(mutex);
+#endif /* SYS_LIGHTWEIGHT_PROT */  
+    return NULL;
+  }
+}
+
+void
+memp_free(memp_t type, void *mem)
+{
+  struct memp *memp;
+#if SYS_LIGHTWEIGHT_PROT
+  SYS_ARCH_DECL_PROTECT(old_level);
+#endif /* SYS_LIGHTWEIGHT_PROT */  
+
+  if (mem == NULL) {
+    return;
+  }
+  memp = (struct memp *)((u8_t *)mem - sizeof(struct memp));
+
+#if SYS_LIGHTWEIGHT_PROT
+    SYS_ARCH_PROTECT(old_level);
+#else /* SYS_LIGHTWEIGHT_PROT */  
+  sys_sem_wait(mutex);
+#endif /* SYS_LIGHTWEIGHT_PROT */  
+
+#if MEMP_STATS
+  lwip_stats.memp[type].used--; 
+#endif /* MEMP_STATS */
+  
+  memp->next = memp_tab[type]; 
+  memp_tab[type] = memp;
+
+#if MEMP_SANITY_CHECK
+  LWIP_ASSERT("memp sanity", memp_sanity());
+#endif  
+
+#if SYS_LIGHTWEIGHT_PROT
+  SYS_ARCH_UNPROTECT(old_level);
+#else /* SYS_LIGHTWEIGHT_PROT */
+  sys_sem_signal(mutex);
+#endif /* SYS_LIGHTWEIGHT_PROT */  
+}
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/netif.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/netif.c
new file mode 100644
index 000000000..e8cabc99d
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/netif.c
@@ -0,0 +1,288 @@
+/**
+ * @file
+ *
+ * lwIP network interface abstraction
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/tcp.h"
+
+struct netif *netif_list = NULL;
+struct netif *netif_default = NULL;
+
+/**
+ * Add a network interface to the list of lwIP netifs.
+ *
+ * @param netif a pre-allocated netif structure
+ * @param ipaddr IP address for the new netif
+ * @param netmask network mask for the new netif
+ * @param gw default gateway IP address for the new netif
+ * @param state opaque data passed to the new netif
+ * @param init callback function that initializes the interface
+ * @param input callback function that is called to pass
+ * ingress packets up in the protocol layer stack.
+ *
+ * @return netif, or NULL if failed.
+ */
+struct netif *
+netif_add(struct netif *netif, struct ip_addr *ipaddr, struct ip_addr *netmask,
+  struct ip_addr *gw,
+  void *state,
+  err_t (* init)(struct netif *netif),
+  err_t (* input)(struct pbuf *p, struct netif *netif))
+{
+  static int netifnum = 0;
+  
+#if LWIP_DHCP
+  /* netif not under DHCP control by default */
+  netif->dhcp = NULL;
+#endif
+  /* remember netif specific state information data */
+  netif->state = state;
+  netif->num = netifnum++;
+  netif->input = input;
+
+  netif_set_addr(netif, ipaddr, netmask, gw);
+
+  /* call user specified initialization function for netif */
+  if (init(netif) != ERR_OK) {
+    return NULL;
+  }
+
+  /* add this netif to the list */
+  netif->next = netif_list;
+  netif_list = netif;
+  LWIP_DEBUGF(NETIF_DEBUG, ("netif: added interface %c%c IP addr ",
+    netif->name[0], netif->name[1]));
+  ip_addr_debug_print(NETIF_DEBUG, ipaddr);
+  LWIP_DEBUGF(NETIF_DEBUG, (" netmask "));
+  ip_addr_debug_print(NETIF_DEBUG, netmask);
+  LWIP_DEBUGF(NETIF_DEBUG, (" gw "));
+  ip_addr_debug_print(NETIF_DEBUG, gw);
+  LWIP_DEBUGF(NETIF_DEBUG, ("\n"));
+  return netif;
+}
+
+void
+netif_set_addr(struct netif *netif,struct ip_addr *ipaddr, struct ip_addr *netmask,
+    struct ip_addr *gw)
+{
+  netif_set_ipaddr(netif, ipaddr);
+  netif_set_netmask(netif, netmask);
+  netif_set_gw(netif, gw);
+}
+
+void netif_remove(struct netif * netif)
+{
+  if ( netif == NULL ) return;
+
+  /*  is it the first netif? */
+  if (netif_list == netif) {
+    netif_list = netif->next;
+  }
+  else {
+    /*  look for netif further down the list */
+    struct netif * tmpNetif;
+    for (tmpNetif = netif_list; tmpNetif != NULL; tmpNetif = tmpNetif->next) {
+      if (tmpNetif->next == netif) {
+        tmpNetif->next = netif->next;
+        break;
+        }
+    }
+    if (tmpNetif == NULL)
+      return; /*  we didn't find any netif today */
+  }
+  /* this netif is default? */
+  if (netif_default == netif)
+    /* reset default netif */
+    netif_default = NULL;
+  LWIP_DEBUGF( NETIF_DEBUG, ("netif_remove: removed netif\n") );
+}
+
+struct netif *
+netif_find(char *name)
+{
+  struct netif *netif;
+  u8_t num;
+
+  if (name == NULL) {
+    return NULL;
+  }
+
+  num = name[2] - '0';
+
+  for(netif = netif_list; netif != NULL; netif = netif->next) {
+    if (num == netif->num &&
+       name[0] == netif->name[0] &&
+       name[1] == netif->name[1]) {
+      LWIP_DEBUGF(NETIF_DEBUG, ("netif_find: found %c%c\n", name[0], name[1]));
+      return netif;
+    }
+  }
+  LWIP_DEBUGF(NETIF_DEBUG, ("netif_find: didn't find %c%c\n", name[0], name[1]));
+  return NULL;
+}
+
+void
+netif_set_ipaddr(struct netif *netif, struct ip_addr *ipaddr)
+{
+  /* TODO: Handling of obsolete pcbs */
+  /* See:  http://mail.gnu.org/archive/html/lwip-users/2003-03/msg00118.html */
+#if LWIP_TCP
+  struct tcp_pcb *pcb;
+  struct tcp_pcb_listen *lpcb;
+
+  /* address is actually being changed? */
+  if ((ip_addr_cmp(ipaddr, &(netif->ip_addr))) == 0)
+  {
+    /* extern struct tcp_pcb *tcp_active_pcbs; defined by tcp.h */
+    LWIP_DEBUGF(NETIF_DEBUG | 1, ("netif_set_ipaddr: netif address being changed\n"));
+    pcb = tcp_active_pcbs;
+    while (pcb != NULL) {
+      /* PCB bound to current local interface address? */
+      if (ip_addr_cmp(&(pcb->local_ip), &(netif->ip_addr))) {
+        /* this connection must be aborted */
+        struct tcp_pcb *next = pcb->next;
+        LWIP_DEBUGF(NETIF_DEBUG | 1, ("netif_set_ipaddr: aborting TCP pcb %p\n", (void *)pcb));
+        tcp_abort(pcb);
+        pcb = next;
+      } else {
+        pcb = pcb->next;
+      }
+    }
+    for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
+      /* PCB bound to current local interface address? */
+      if (ip_addr_cmp(&(lpcb->local_ip), &(netif->ip_addr))) {
+        /* The PCB is listening to the old ipaddr and
+         * is set to listen to the new one instead */
+        ip_addr_set(&(lpcb->local_ip), ipaddr);
+      }
+    }
+  }
+#endif
+  ip_addr_set(&(netif->ip_addr), ipaddr);
+#if 0 /* only allowed for Ethernet interfaces TODO: how can we check? */
+  /** For Ethernet network interfaces, we would like to send a
+   *  "gratuitous ARP"; this is an ARP packet sent by a node in order
+   *  to spontaneously cause other nodes to update an entry in their
+   *  ARP cache. From RFC 3220 "IP Mobility Support for IPv4" section 4.6.
+   */ 
+  etharp_query(netif, ipaddr, NULL);
+#endif
+  LWIP_DEBUGF(NETIF_DEBUG | DBG_TRACE | DBG_STATE | 3, ("netif: IP address of interface %c%c set to %u.%u.%u.%u\n",
+    netif->name[0], netif->name[1],
+    ip4_addr1(&netif->ip_addr),
+    ip4_addr2(&netif->ip_addr),
+    ip4_addr3(&netif->ip_addr),
+    ip4_addr4(&netif->ip_addr)));
+}
+
+void
+netif_set_gw(struct netif *netif, struct ip_addr *gw)
+{
+  ip_addr_set(&(netif->gw), gw);
+  LWIP_DEBUGF(NETIF_DEBUG | DBG_TRACE | DBG_STATE | 3, ("netif: GW address of interface %c%c set to %u.%u.%u.%u\n",
+    netif->name[0], netif->name[1],
+    ip4_addr1(&netif->gw),
+    ip4_addr2(&netif->gw),
+    ip4_addr3(&netif->gw),
+    ip4_addr4(&netif->gw)));
+}
+
+void
+netif_set_netmask(struct netif *netif, struct ip_addr *netmask)
+{
+  ip_addr_set(&(netif->netmask), netmask);
+  LWIP_DEBUGF(NETIF_DEBUG | DBG_TRACE | DBG_STATE | 3, ("netif: netmask of interface %c%c set to %u.%u.%u.%u\n",
+    netif->name[0], netif->name[1],
+    ip4_addr1(&netif->netmask),
+    ip4_addr2(&netif->netmask),
+    ip4_addr3(&netif->netmask),
+    ip4_addr4(&netif->netmask)));
+}
+
+void
+netif_set_default(struct netif *netif)
+{
+  netif_default = netif;
+  LWIP_DEBUGF(NETIF_DEBUG, ("netif: setting default interface %c%c\n",
+           netif ? netif->name[0] : '\'', netif ? netif->name[1] : '\''));
+}
+
+/**
+ * Bring an interface up, available for processing
+ * traffic.
+ * 
+ * @note: Enabling DHCP on a down interface will make it come
+ * up once configured.
+ * 
+ * @see dhcp_start()
+ */ 
+void netif_set_up(struct netif *netif)
+{
+  netif->flags |= NETIF_FLAG_UP;
+}
+
+/**
+ * Ask if an interface is up
+ */ 
+u8_t netif_is_up(struct netif *netif)
+{
+  return (netif->flags & NETIF_FLAG_UP)?1:0;
+}
+
+/**
+ * Bring an interface down, disabling any traffic processing.
+ *
+ * @note: Enabling DHCP on a down interface will make it come
+ * up once configured.
+ * 
+ * @see dhcp_start()
+ */ 
+void netif_set_down(struct netif *netif)
+{
+  netif->flags &= ~NETIF_FLAG_UP;
+}
+
+void
+netif_init(void)
+{
+  netif_list = netif_default = NULL;
+}
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/pbuf.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/pbuf.c
new file mode 100644
index 000000000..ad929c6b5
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/pbuf.c
@@ -0,0 +1,962 @@
+/**
+ * @file
+ * Packet buffer management
+ *
+ * Packets are built from the pbuf data structure. It supports dynamic
+ * memory allocation for packet contents or can reference externally
+ * managed packet contents both in RAM and ROM. Quick allocation for
+ * incoming packets is provided through pools with fixed sized pbufs.
+ *
+ * A packet may span over multiple pbufs, chained as a singly linked
+ * list. This is called a "pbuf chain".
+ *
+ * Multiple packets may be queued, also using this singly linked list.
+ * This is called a "packet queue".
+ * 
+ * So, a packet queue consists of one or more pbuf chains, each of
+ * which consist of one or more pbufs. Currently, queues are only
+ * supported in a limited section of lwIP, this is the etharp queueing
+ * code. Outside of this section no packet queues are supported yet.
+ * 
+ * The differences between a pbuf chain and a packet queue are very
+ * precise but subtle. 
+ *
+ * The last pbuf of a packet has a ->tot_len field that equals the
+ * ->len field. It can be found by traversing the list. If the last
+ * pbuf of a packet has a ->next field other than NULL, more packets
+ * are on the queue.
+ *
+ * Therefore, looping through a pbuf of a single packet, has an
+ * loop end condition (tot_len == p->len), NOT (next == NULL).
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/stats.h"
+
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+#include "lwip/pbuf.h"
+
+#include "lwip/sys.h"
+
+#include "arch/perf.h"
+
+#include 
+
+static u8_t pbuf_pool_memory[(PBUF_POOL_SIZE * MEM_ALIGN_SIZE(PBUF_POOL_BUFSIZE + sizeof(struct pbuf)))];
+
+#if !SYS_LIGHTWEIGHT_PROT
+static volatile u8_t pbuf_pool_free_lock, pbuf_pool_alloc_lock;
+static sys_sem_t pbuf_pool_free_sem;
+#endif
+
+static struct pbuf *pbuf_pool = NULL;
+
+/**
+ * Initializes the pbuf module.
+ *
+ * A large part of memory is allocated for holding the pool of pbufs.
+ * The size of the individual pbufs in the pool is given by the size
+ * parameter, and the number of pbufs in the pool by the num parameter.
+ *
+ * After the memory has been allocated, the pbufs are set up. The
+ * ->next pointer in each pbuf is set up to point to the next pbuf in
+ * the pool.
+ *
+ */
+void
+pbuf_init(void)
+{
+  struct pbuf *p, *q = NULL;
+  u16_t i;
+
+  pbuf_pool = (struct pbuf *)&pbuf_pool_memory[0];
+  LWIP_ASSERT("pbuf_init: pool aligned", (mem_ptr_t)pbuf_pool % MEM_ALIGNMENT == 0);
+
+#if PBUF_STATS
+  lwip_stats.pbuf.avail = PBUF_POOL_SIZE;
+#endif /* PBUF_STATS */
+
+  /* Set up ->next pointers to link the pbufs of the pool together */
+  p = pbuf_pool;
+
+  for(i = 0; i < PBUF_POOL_SIZE; ++i) {
+    p->next = (struct pbuf *)((u8_t *)p + PBUF_POOL_BUFSIZE + sizeof(struct pbuf));
+    p->len = p->tot_len = PBUF_POOL_BUFSIZE;
+    p->payload = MEM_ALIGN((void *)((u8_t *)p + sizeof(struct pbuf)));
+    p->flags = PBUF_FLAG_POOL;
+    q = p;
+    p = p->next;
+  }
+
+  /* The ->next pointer of last pbuf is NULL to indicate that there
+     are no more pbufs in the pool */
+  q->next = NULL;
+
+#if !SYS_LIGHTWEIGHT_PROT
+  pbuf_pool_alloc_lock = 0;
+  pbuf_pool_free_lock = 0;
+  pbuf_pool_free_sem = sys_sem_new(1);
+#endif
+}
+
+/**
+ * @internal only called from pbuf_alloc()
+ */
+static struct pbuf *
+pbuf_pool_alloc(void)
+{
+  struct pbuf *p = NULL;
+
+  SYS_ARCH_DECL_PROTECT(old_level);
+  SYS_ARCH_PROTECT(old_level);
+
+#if !SYS_LIGHTWEIGHT_PROT
+  /* Next, check the actual pbuf pool, but if the pool is locked, we
+     pretend to be out of buffers and return NULL. */
+  if (pbuf_pool_free_lock) {
+#if PBUF_STATS
+    ++lwip_stats.pbuf.alloc_locked;
+#endif /* PBUF_STATS */
+    return NULL;
+  }
+  pbuf_pool_alloc_lock = 1;
+  if (!pbuf_pool_free_lock) {
+#endif /* SYS_LIGHTWEIGHT_PROT */
+    p = pbuf_pool;
+    if (p) {
+      pbuf_pool = p->next;
+    }
+#if !SYS_LIGHTWEIGHT_PROT
+#if PBUF_STATS
+  } else {
+    ++lwip_stats.pbuf.alloc_locked;
+#endif /* PBUF_STATS */
+  }
+  pbuf_pool_alloc_lock = 0;
+#endif /* SYS_LIGHTWEIGHT_PROT */
+
+#if PBUF_STATS
+  if (p != NULL) {
+    ++lwip_stats.pbuf.used;
+    if (lwip_stats.pbuf.used > lwip_stats.pbuf.max) {
+      lwip_stats.pbuf.max = lwip_stats.pbuf.used;
+    }
+  }
+#endif /* PBUF_STATS */
+
+  SYS_ARCH_UNPROTECT(old_level);
+  return p;
+}
+
+
+/**
+ * Allocates a pbuf of the given type (possibly a chain for PBUF_POOL type).
+ *
+ * The actual memory allocated for the pbuf is determined by the
+ * layer at which the pbuf is allocated and the requested size
+ * (from the size parameter).
+ *
+ * @param flag this parameter decides how and where the pbuf
+ * should be allocated as follows:
+ *
+ * - PBUF_RAM: buffer memory for pbuf is allocated as one large
+ *             chunk. This includes protocol headers as well.
+ * - PBUF_ROM: no buffer memory is allocated for the pbuf, even for
+ *             protocol headers. Additional headers must be prepended
+ *             by allocating another pbuf and chain in to the front of
+ *             the ROM pbuf. It is assumed that the memory used is really
+ *             similar to ROM in that it is immutable and will not be
+ *             changed. Memory which is dynamic should generally not
+ *             be attached to PBUF_ROM pbufs. Use PBUF_REF instead.
+ * - PBUF_REF: no buffer memory is allocated for the pbuf, even for
+ *             protocol headers. It is assumed that the pbuf is only
+ *             being used in a single thread. If the pbuf gets queued,
+ *             then pbuf_take should be called to copy the buffer.
+ * - PBUF_POOL: the pbuf is allocated as a pbuf chain, with pbufs from
+ *              the pbuf pool that is allocated during pbuf_init().
+ *
+ * @return the allocated pbuf. If multiple pbufs where allocated, this
+ * is the first pbuf of a pbuf chain.
+ */
+struct pbuf *
+pbuf_alloc(pbuf_layer l, u16_t length, pbuf_flag flag)
+{
+  struct pbuf *p, *q, *r;
+  u16_t offset;
+  s32_t rem_len; /* remaining length */
+  LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_alloc(length=%u)\n", length));
+
+  /* determine header offset */
+  offset = 0;
+  switch (l) {
+  case PBUF_TRANSPORT:
+    /* add room for transport (often TCP) layer header */
+    offset += PBUF_TRANSPORT_HLEN;
+    /* FALLTHROUGH */
+  case PBUF_IP:
+    /* add room for IP layer header */
+    offset += PBUF_IP_HLEN;
+    /* FALLTHROUGH */
+  case PBUF_LINK:
+    /* add room for link layer header */
+    offset += PBUF_LINK_HLEN;
+    break;
+  case PBUF_RAW:
+    break;
+  default:
+    LWIP_ASSERT("pbuf_alloc: bad pbuf layer", 0);
+    return NULL;
+  }
+
+  switch (flag) {
+  case PBUF_POOL:
+    /* allocate head of pbuf chain into p */
+    p = pbuf_pool_alloc();
+    LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_alloc: allocated pbuf %p\n", (void *)p));
+    if (p == NULL) {
+#if PBUF_STATS
+      ++lwip_stats.pbuf.err;
+#endif /* PBUF_STATS */
+      return NULL;
+    }
+    p->next = NULL;
+
+    /* make the payload pointer point 'offset' bytes into pbuf data memory */
+    p->payload = MEM_ALIGN((void *)((u8_t *)p + (sizeof(struct pbuf) + offset)));
+    LWIP_ASSERT("pbuf_alloc: pbuf p->payload properly aligned",
+            ((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0);
+    /* the total length of the pbuf chain is the requested size */
+    p->tot_len = length;
+    /* set the length of the first pbuf in the chain */
+    p->len = length > PBUF_POOL_BUFSIZE - offset? PBUF_POOL_BUFSIZE - offset: length;
+    /* set reference count (needed here in case we fail) */
+    p->ref = 1;
+
+    /* now allocate the tail of the pbuf chain */
+
+    /* remember first pbuf for linkage in next iteration */
+    r = p;
+    /* remaining length to be allocated */
+    rem_len = length - p->len;
+    /* any remaining pbufs to be allocated? */
+    while (rem_len > 0) {
+      q = pbuf_pool_alloc();
+      if (q == NULL) {
+       LWIP_DEBUGF(PBUF_DEBUG | 2, ("pbuf_alloc: Out of pbufs in pool.\n"));
+#if PBUF_STATS
+        ++lwip_stats.pbuf.err;
+#endif /* PBUF_STATS */
+        /* free chain so far allocated */
+        pbuf_free(p);
+        /* bail out unsuccesfully */
+        return NULL;
+      }
+      q->next = NULL;
+      /* make previous pbuf point to this pbuf */
+      r->next = q;
+      /* set total length of this pbuf and next in chain */
+      q->tot_len = rem_len;
+      /* this pbuf length is pool size, unless smaller sized tail */
+      q->len = rem_len > PBUF_POOL_BUFSIZE? PBUF_POOL_BUFSIZE: rem_len;
+      q->payload = (void *)((u8_t *)q + sizeof(struct pbuf));
+      LWIP_ASSERT("pbuf_alloc: pbuf q->payload properly aligned",
+              ((mem_ptr_t)q->payload % MEM_ALIGNMENT) == 0);
+      q->ref = 1;
+      /* calculate remaining length to be allocated */
+      rem_len -= q->len;
+      /* remember this pbuf for linkage in next iteration */
+      r = q;
+    }
+    /* end of chain */
+    /*r->next = NULL;*/
+
+    break;
+  case PBUF_RAM:
+    /* If pbuf is to be allocated in RAM, allocate memory for it. */
+    p = mem_malloc(MEM_ALIGN_SIZE(sizeof(struct pbuf) + offset) + MEM_ALIGN_SIZE(length));
+    if (p == NULL) {
+      return NULL;
+    }
+    /* Set up internal structure of the pbuf. */
+    p->payload = MEM_ALIGN((void *)((u8_t *)p + sizeof(struct pbuf) + offset));
+    p->len = p->tot_len = length;
+    p->next = NULL;
+    p->flags = PBUF_FLAG_RAM;
+
+    LWIP_ASSERT("pbuf_alloc: pbuf->payload properly aligned",
+           ((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0);
+    break;
+  /* pbuf references existing (non-volatile static constant) ROM payload? */
+  case PBUF_ROM:
+  /* pbuf references existing (externally allocated) RAM payload? */
+  case PBUF_REF:
+    /* only allocate memory for the pbuf structure */
+    p = memp_malloc(MEMP_PBUF);
+    if (p == NULL) {
+      LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_alloc: Could not allocate MEMP_PBUF for PBUF_%s.\n", flag == PBUF_ROM?"ROM":"REF"));
+      return NULL;
+    }
+    /* caller must set this field properly, afterwards */
+    p->payload = NULL;
+    p->len = p->tot_len = length;
+    p->next = NULL;
+    p->flags = (flag == PBUF_ROM? PBUF_FLAG_ROM: PBUF_FLAG_REF);
+    break;
+  default:
+    LWIP_ASSERT("pbuf_alloc: erroneous flag", 0);
+    return NULL;
+  }
+  /* set reference count */
+  p->ref = 1;
+  LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_alloc(length=%u) == %p\n", length, (void *)p));
+  return p;
+}
+
+
+#if PBUF_STATS
+#define DEC_PBUF_STATS do { --lwip_stats.pbuf.used; } while (0)
+#else /* PBUF_STATS */
+#define DEC_PBUF_STATS
+#endif /* PBUF_STATS */
+
+#define PBUF_POOL_FAST_FREE(p)  do {                                    \
+                                  p->next = pbuf_pool;                  \
+                                  pbuf_pool = p;                        \
+                                  DEC_PBUF_STATS;                       \
+                                } while (0)
+
+#if SYS_LIGHTWEIGHT_PROT
+#define PBUF_POOL_FREE(p)  do {                                         \
+                                SYS_ARCH_DECL_PROTECT(old_level);       \
+                                SYS_ARCH_PROTECT(old_level);            \
+                                PBUF_POOL_FAST_FREE(p);                 \
+                                SYS_ARCH_UNPROTECT(old_level);          \
+                               } while (0)
+#else /* SYS_LIGHTWEIGHT_PROT */
+#define PBUF_POOL_FREE(p)  do {                                         \
+                             sys_sem_wait(pbuf_pool_free_sem);          \
+                             PBUF_POOL_FAST_FREE(p);                    \
+                             sys_sem_signal(pbuf_pool_free_sem);        \
+                           } while (0)
+#endif /* SYS_LIGHTWEIGHT_PROT */
+
+/**
+ * Shrink a pbuf chain to a desired length.
+ *
+ * @param p pbuf to shrink.
+ * @param new_len desired new length of pbuf chain
+ *
+ * Depending on the desired length, the first few pbufs in a chain might
+ * be skipped and left unchanged. The new last pbuf in the chain will be
+ * resized, and any remaining pbufs will be freed.
+ *
+ * @note If the pbuf is ROM/REF, only the ->tot_len and ->len fields are adjusted.
+ * @note May not be called on a packet queue.
+ *
+ * @bug Cannot grow the size of a pbuf (chain) (yet).
+ */
+void
+pbuf_realloc(struct pbuf *p, u16_t new_len)
+{
+  struct pbuf *q;
+  u16_t rem_len; /* remaining length */
+  s16_t grow;
+
+  LWIP_ASSERT("pbuf_realloc: sane p->flags", p->flags == PBUF_FLAG_POOL ||
+              p->flags == PBUF_FLAG_ROM ||
+              p->flags == PBUF_FLAG_RAM ||
+              p->flags == PBUF_FLAG_REF);
+
+  /* desired length larger than current length? */
+  if (new_len >= p->tot_len) {
+    /* enlarging not yet supported */
+    return;
+  }
+
+  /* the pbuf chain grows by (new_len - p->tot_len) bytes
+   * (which may be negative in case of shrinking) */
+  grow = new_len - p->tot_len;
+
+  /* first, step over any pbufs that should remain in the chain */
+  rem_len = new_len;
+  q = p;
+  /* should this pbuf be kept? */
+  while (rem_len > q->len) {
+    /* decrease remaining length by pbuf length */
+    rem_len -= q->len;
+    /* decrease total length indicator */
+    q->tot_len += grow;
+    /* proceed to next pbuf in chain */
+    q = q->next;
+  }
+  /* we have now reached the new last pbuf (in q) */
+  /* rem_len == desired length for pbuf q */
+
+  /* shrink allocated memory for PBUF_RAM */
+  /* (other types merely adjust their length fields */
+  if ((q->flags == PBUF_FLAG_RAM) && (rem_len != q->len)) {
+    /* reallocate and adjust the length of the pbuf that will be split */
+    mem_realloc(q, (u8_t *)q->payload - (u8_t *)q + rem_len);
+  }
+  /* adjust length fields for new last pbuf */
+  q->len = rem_len;
+  q->tot_len = q->len;
+
+  /* any remaining pbufs in chain? */
+  if (q->next != NULL) {
+    /* free remaining pbufs in chain */
+    pbuf_free(q->next);
+  }
+  /* q is last packet in chain */
+  q->next = NULL;
+
+}
+
+/**
+ * Adjusts the payload pointer to hide or reveal headers in the payload.
+ *
+ * Adjusts the ->payload pointer so that space for a header
+ * (dis)appears in the pbuf payload.
+ *
+ * The ->payload, ->tot_len and ->len fields are adjusted.
+ *
+ * @param hdr_size_inc Number of bytes to increment header size which
+ * increases the size of the pbuf. New space is on the front.
+ * (Using a negative value decreases the header size.)
+ * If hdr_size_inc is 0, this function does nothing and returns succesful.
+ *
+ * PBUF_ROM and PBUF_REF type buffers cannot have their sizes increased, so
+ * the call will fail. A check is made that the increase in header size does
+ * not move the payload pointer in front of the start of the buffer.
+ * @return non-zero on failure, zero on success.
+ *
+ */
+u8_t
+pbuf_header(struct pbuf *p, s16_t header_size_increment)
+{
+  void *payload;
+
+  LWIP_ASSERT("p != NULL", p != NULL);
+  if ((header_size_increment == 0) || (p == NULL)) return 0;
+ 
+  /* remember current payload pointer */
+  payload = p->payload;
+
+  /* pbuf types containing payloads? */
+  if (p->flags == PBUF_FLAG_RAM || p->flags == PBUF_FLAG_POOL) {
+    /* set new payload pointer */
+    p->payload = (u8_t *)p->payload - header_size_increment;
+    /* boundary check fails? */
+    if ((u8_t *)p->payload < (u8_t *)p + sizeof(struct pbuf)) {
+      LWIP_DEBUGF( PBUF_DEBUG | 2, ("pbuf_header: failed as %p < %p (not enough space for new header size)\n",
+        (void *)p->payload,
+        (void *)(p + 1)));\
+      /* restore old payload pointer */
+      p->payload = payload;
+      /* bail out unsuccesfully */
+      return 1;
+    }
+  /* pbuf types refering to external payloads? */
+  } else if (p->flags == PBUF_FLAG_REF || p->flags == PBUF_FLAG_ROM) {
+    /* hide a header in the payload? */
+    if ((header_size_increment < 0) && (header_size_increment - p->len <= 0)) {
+      /* increase payload pointer */
+      p->payload = (u8_t *)p->payload - header_size_increment;
+    } else {
+      /* cannot expand payload to front (yet!)
+       * bail out unsuccesfully */
+      return 1;
+    }
+  }
+  /* modify pbuf length fields */
+  p->len += header_size_increment;
+  p->tot_len += header_size_increment;
+
+  LWIP_DEBUGF( PBUF_DEBUG, ("pbuf_header: old %p new %p (%d)\n",
+    (void *)payload, (void *)p->payload, header_size_increment));
+
+  return 0;
+}
+
+/**
+ * Dereference a pbuf chain or queue and deallocate any no-longer-used
+ * pbufs at the head of this chain or queue.
+ *
+ * Decrements the pbuf reference count. If it reaches zero, the pbuf is
+ * deallocated.
+ *
+ * For a pbuf chain, this is repeated for each pbuf in the chain,
+ * up to the first pbuf which has a non-zero reference count after
+ * decrementing. So, when all reference counts are one, the whole
+ * chain is free'd.
+ *
+ * @param pbuf The pbuf (chain) to be dereferenced.
+ *
+ * @return the number of pbufs that were de-allocated
+ * from the head of the chain.
+ *
+ * @note MUST NOT be called on a packet queue (Not verified to work yet).
+ * @note the reference counter of a pbuf equals the number of pointers
+ * that refer to the pbuf (or into the pbuf).
+ *
+ * @internal examples:
+ *
+ * Assuming existing chains a->b->c with the following reference
+ * counts, calling pbuf_free(a) results in:
+ * 
+ * 1->2->3 becomes ...1->3
+ * 3->3->3 becomes 2->3->3
+ * 1->1->2 becomes ......1
+ * 2->1->1 becomes 1->1->1
+ * 1->1->1 becomes .......
+ *
+ */
+u8_t
+pbuf_free(struct pbuf *p)
+{
+  struct pbuf *q;
+  u8_t count;
+  SYS_ARCH_DECL_PROTECT(old_level);
+
+  LWIP_ASSERT("p != NULL", p != NULL);
+  /* if assertions are disabled, proceed with debug output */
+  if (p == NULL) {
+    LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_free(p == NULL) was called.\n"));
+    return 0;
+  }
+  LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_free(%p)\n", (void *)p));
+
+  PERF_START;
+
+  LWIP_ASSERT("pbuf_free: sane flags",
+    p->flags == PBUF_FLAG_RAM || p->flags == PBUF_FLAG_ROM ||
+    p->flags == PBUF_FLAG_REF || p->flags == PBUF_FLAG_POOL);
+
+  count = 0;
+  /* Since decrementing ref cannot be guaranteed to be a single machine operation
+   * we must protect it. Also, the later test of ref must be protected.
+   */
+  SYS_ARCH_PROTECT(old_level);
+  /* de-allocate all consecutive pbufs from the head of the chain that
+   * obtain a zero reference count after decrementing*/
+  while (p != NULL) {
+    /* all pbufs in a chain are referenced at least once */
+    LWIP_ASSERT("pbuf_free: p->ref > 0", p->ref > 0);
+    /* decrease reference count (number of pointers to pbuf) */
+    p->ref--;
+    /* this pbuf is no longer referenced to? */
+    if (p->ref == 0) {
+      /* remember next pbuf in chain for next iteration */
+      q = p->next;
+      LWIP_DEBUGF( PBUF_DEBUG | 2, ("pbuf_free: deallocating %p\n", (void *)p));
+      /* is this a pbuf from the pool? */
+      if (p->flags == PBUF_FLAG_POOL) {
+        p->len = p->tot_len = PBUF_POOL_BUFSIZE;
+        p->payload = (void *)((u8_t *)p + sizeof(struct pbuf));
+        PBUF_POOL_FREE(p);
+      /* is this a ROM or RAM referencing pbuf? */
+      } else if (p->flags == PBUF_FLAG_ROM || p->flags == PBUF_FLAG_REF) {
+        memp_free(MEMP_PBUF, p);
+      /* p->flags == PBUF_FLAG_RAM */
+      } else {
+        mem_free(p);
+      }
+      count++;
+      /* proceed to next pbuf */
+      p = q;
+    /* p->ref > 0, this pbuf is still referenced to */
+    /* (and so the remaining pbufs in chain as well) */
+    } else {
+      LWIP_DEBUGF( PBUF_DEBUG | 2, ("pbuf_free: %p has ref %u, ending here.\n", (void *)p, (unsigned int)p->ref));
+      /* stop walking through the chain */
+      p = NULL;
+    }
+  }
+  SYS_ARCH_UNPROTECT(old_level);
+  PERF_STOP("pbuf_free");
+  /* return number of de-allocated pbufs */
+  return count;
+}
+
+/**
+ * Count number of pbufs in a chain
+ *
+ * @param p first pbuf of chain
+ * @return the number of pbufs in a chain
+ */
+
+u8_t
+pbuf_clen(struct pbuf *p)
+{
+  u8_t len;
+
+  len = 0;
+  while (p != NULL) {
+    ++len;
+    p = p->next;
+  }
+  return len;
+}
+
+/**
+ * Increment the reference count of the pbuf.
+ *
+ * @param p pbuf to increase reference counter of
+ *
+ */
+void
+pbuf_ref(struct pbuf *p)
+{
+  SYS_ARCH_DECL_PROTECT(old_level);
+  /* pbuf given? */
+  if (p != NULL) {
+    SYS_ARCH_PROTECT(old_level);
+    ++(p->ref);
+    SYS_ARCH_UNPROTECT(old_level);
+  }
+}
+
+/**
+ * Concatenate two pbufs (each may be a pbuf chain) and take over
+ * the caller's reference of the tail pbuf.
+ * 
+ * @note The caller MAY NOT reference the tail pbuf afterwards.
+ * Use pbuf_chain() for that purpose.
+ * 
+ * @see pbuf_chain()
+ */
+
+void
+pbuf_cat(struct pbuf *h, struct pbuf *t)
+{
+  struct pbuf *p;
+
+  LWIP_ASSERT("h != NULL (programmer violates API)", h != NULL);
+  LWIP_ASSERT("t != NULL (programmer violates API)", t != NULL);
+  if ((h == NULL) || (t == NULL)) return;
+
+  /* proceed to last pbuf of chain */
+  for (p = h; p->next != NULL; p = p->next) {
+    /* add total length of second chain to all totals of first chain */
+    p->tot_len += t->tot_len;
+  }
+  /* { p is last pbuf of first h chain, p->next == NULL } */
+  LWIP_ASSERT("p->tot_len == p->len (of last pbuf in chain)", p->tot_len == p->len);
+  LWIP_ASSERT("p->next == NULL", p->next == NULL);
+  /* add total length of second chain to last pbuf total of first chain */
+  p->tot_len += t->tot_len;
+  /* chain last pbuf of head (p) with first of tail (t) */
+  p->next = t;
+  /* p->next now references t, but the caller will drop its reference to t,
+   * so netto there is no change to the reference count of t.
+   */
+}
+
+/**
+ * Chain two pbufs (or pbuf chains) together.
+ * 
+ * The caller MUST call pbuf_free(t) once it has stopped
+ * using it. Use pbuf_cat() instead if you no longer use t.
+ * 
+ * @param h head pbuf (chain)
+ * @param t tail pbuf (chain)
+ * @note The pbufs MUST belong to the same packet.
+ * @note MAY NOT be called on a packet queue.
+ *
+ * The ->tot_len fields of all pbufs of the head chain are adjusted.
+ * The ->next field of the last pbuf of the head chain is adjusted.
+ * The ->ref field of the first pbuf of the tail chain is adjusted.
+ *
+ */
+void
+pbuf_chain(struct pbuf *h, struct pbuf *t)
+{
+  pbuf_cat(h, t);
+  /* t is now referenced by h */
+  pbuf_ref(t);
+  LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2, ("pbuf_chain: %p references %p\n", (void *)h, (void *)t));
+}
+
+/* For packet queueing. Note that queued packets MUST be dequeued first
+ * using pbuf_dequeue() before calling other pbuf_() functions. */
+#if ARP_QUEUEING
+/**
+ * Add a packet to the end of a queue.
+ *
+ * @param q pointer to first packet on the queue
+ * @param n packet to be queued
+ *
+ * Both packets MUST be given, and must be different.
+ */
+void
+pbuf_queue(struct pbuf *p, struct pbuf *n)
+{
+#if PBUF_DEBUG /* remember head of queue */
+  struct pbuf *q = p;
+#endif
+  /* programmer stupidity checks */
+  LWIP_ASSERT("p == NULL in pbuf_queue: this indicates a programmer error\n", p != NULL);
+  LWIP_ASSERT("n == NULL in pbuf_queue: this indicates a programmer error\n", n != NULL);
+  LWIP_ASSERT("p == n in pbuf_queue: this indicates a programmer error\n", p != n);
+  if ((p == NULL) || (n == NULL) || (p == n)){
+    LWIP_DEBUGF(PBUF_DEBUG | DBG_HALT | 3, ("pbuf_queue: programmer argument error\n"))
+    return;
+  }
+
+  /* iterate through all packets on queue */
+  while (p->next != NULL) {
+/* be very picky about pbuf chain correctness */
+#if PBUF_DEBUG
+    /* iterate through all pbufs in packet */
+    while (p->tot_len != p->len) {
+      /* make sure invariant condition holds */
+      LWIP_ASSERT("p->len < p->tot_len", p->len < p->tot_len);
+      /* make sure each packet is complete */
+      LWIP_ASSERT("p->next != NULL", p->next != NULL);
+      p = p->next;
+      /* { p->tot_len == p->len => p is last pbuf of a packet } */
+    }
+    /* { p is last pbuf of a packet } */
+    /* proceed to next packet on queue */
+#endif
+    /* proceed to next pbuf */
+    if (p->next != NULL) p = p->next;
+  }
+  /* { p->tot_len == p->len and p->next == NULL } ==>
+   * { p is last pbuf of last packet on queue } */
+  /* chain last pbuf of queue with n */
+  p->next = n;
+  /* n is now referenced to by the (packet p in the) queue */
+  pbuf_ref(n);
+#if PBUF_DEBUG
+  LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2,
+    ("pbuf_queue: newly queued packet %p sits after packet %p in queue %p\n",
+    (void *)n, (void *)p, (void *)q));
+#endif
+}
+
+/**
+ * Remove a packet from the head of a queue.
+ *
+ * The caller MUST reference the remainder of the queue (as returned). The
+ * caller MUST NOT call pbuf_ref() as it implicitly takes over the reference
+ * from p.
+ * 
+ * @param p pointer to first packet on the queue which will be dequeued.
+ * @return first packet on the remaining queue (NULL if no further packets).
+ *
+ */
+struct pbuf *
+pbuf_dequeue(struct pbuf *p)
+{
+  struct pbuf *q;
+  LWIP_ASSERT("p != NULL", p != NULL);
+
+  /* iterate through all pbufs in packet p */
+  while (p->tot_len != p->len) {
+    /* make sure invariant condition holds */
+    LWIP_ASSERT("p->len < p->tot_len", p->len < p->tot_len);
+    /* make sure each packet is complete */
+    LWIP_ASSERT("p->next != NULL", p->next != NULL);
+    p = p->next;
+  }
+  /* { p->tot_len == p->len } => p is the last pbuf of the first packet */
+  /* remember next packet on queue in q */
+  q = p->next;
+  /* dequeue packet p from queue */
+  p->next = NULL;
+  /* any next packet on queue? */
+  if (q != NULL) {
+    /* although q is no longer referenced by p, it MUST be referenced by
+     * the caller, who is maintaining this packet queue. So, we do not call
+     * pbuf_free(q) here, resulting in an implicit pbuf_ref(q) for the caller. */
+    LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2, ("pbuf_dequeue: first remaining packet on queue is %p\n", (void *)q));
+  } else {
+    LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2, ("pbuf_dequeue: no further packets on queue\n"));
+  }
+  return q;
+}
+#endif
+
+/**
+ *
+ * Create PBUF_POOL (or PBUF_RAM) copies of PBUF_REF pbufs.
+ *
+ * Used to queue packets on behalf of the lwIP stack, such as
+ * ARP based queueing.
+ *
+ * Go through a pbuf chain and replace any PBUF_REF buffers
+ * with PBUF_POOL (or PBUF_RAM) pbufs, each taking a copy of
+ * the referenced data.
+ *
+ * @note You MUST explicitly use p = pbuf_take(p);
+ * The pbuf you give as argument, may have been replaced
+ * by a (differently located) copy through pbuf_take()!
+ *
+ * @note Any replaced pbufs will be freed through pbuf_free().
+ * This may deallocate them if they become no longer referenced.
+ *
+ * @param p Head of pbuf chain to process
+ *
+ * @return Pointer to head of pbuf chain
+ */
+struct pbuf *
+pbuf_take(struct pbuf *p)
+{
+  struct pbuf *q , *prev, *head;
+  LWIP_ASSERT("pbuf_take: p != NULL\n", p != NULL);
+  LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_take(%p)\n", (void*)p));
+
+  prev = NULL;
+  head = p;
+  /* iterate through pbuf chain */
+  do
+  {
+    /* pbuf is of type PBUF_REF? */
+    if (p->flags == PBUF_FLAG_REF) {
+      LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE, ("pbuf_take: encountered PBUF_REF %p\n", (void *)p));
+      /* allocate a pbuf (w/ payload) fully in RAM */
+      /* PBUF_POOL buffers are faster if we can use them */
+      if (p->len <= PBUF_POOL_BUFSIZE) {
+        q = pbuf_alloc(PBUF_RAW, p->len, PBUF_POOL);
+        if (q == NULL) {
+          LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_take: Could not allocate PBUF_POOL\n"));
+        }
+      } else {
+        /* no replacement pbuf yet */
+        q = NULL;
+        LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_take: PBUF_POOL too small to replace PBUF_REF\n"));
+      }
+      /* no (large enough) PBUF_POOL was available? retry with PBUF_RAM */
+      if (q == NULL) {
+        q = pbuf_alloc(PBUF_RAW, p->len, PBUF_RAM);
+        if (q == NULL) {
+          LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_take: Could not allocate PBUF_RAM\n"));
+        }
+      }
+      /* replacement pbuf could be allocated? */
+      if (q != NULL)
+      {
+        /* copy p to q */
+        /* copy successor */
+        q->next = p->next;
+        /* remove linkage from original pbuf */
+        p->next = NULL;
+        /* remove linkage to original pbuf */
+        if (prev != NULL) {
+          /* prev->next == p at this point */
+          LWIP_ASSERT("prev->next == p", prev->next == p);
+          /* break chain and insert new pbuf instead */
+          prev->next = q;
+        /* prev == NULL, so we replaced the head pbuf of the chain */
+        } else {
+          head = q;
+        }
+        /* copy pbuf payload */
+        memcpy(q->payload, p->payload, p->len);
+        q->tot_len = p->tot_len;
+        q->len = p->len;
+        /* in case p was the first pbuf, it is no longer refered to by
+         * our caller, as the caller MUST do p = pbuf_take(p);
+         * in case p was not the first pbuf, it is no longer refered to
+         * by prev. we can safely free the pbuf here.
+         * (note that we have set p->next to NULL already so that
+         * we will not free the rest of the chain by accident.)
+         */
+        pbuf_free(p);
+        /* do not copy ref, since someone else might be using the old buffer */
+        LWIP_DEBUGF(PBUF_DEBUG, ("pbuf_take: replaced PBUF_REF %p with %p\n", (void *)p, (void *)q));
+        p = q;
+      } else {
+        /* deallocate chain */
+        pbuf_free(head);
+        LWIP_DEBUGF(PBUF_DEBUG | 2, ("pbuf_take: failed to allocate replacement pbuf for %p\n", (void *)p));
+        return NULL;
+      }
+    /* p->flags != PBUF_FLAG_REF */
+    } else {
+      LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 1, ("pbuf_take: skipping pbuf not of type PBUF_REF\n"));
+    }
+    /* remember this pbuf */
+    prev = p;
+    /* proceed to next pbuf in original chain */
+    p = p->next;
+  } while (p);
+  LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 1, ("pbuf_take: end of chain reached.\n"));
+
+  return head;
+}
+
+/**
+ * Dechains the first pbuf from its succeeding pbufs in the chain.
+ *
+ * Makes p->tot_len field equal to p->len.
+ * @param p pbuf to dechain
+ * @return remainder of the pbuf chain, or NULL if it was de-allocated.
+ * @note May not be called on a packet queue.
+ */
+struct pbuf *
+pbuf_dechain(struct pbuf *p)
+{
+  struct pbuf *q;
+  u8_t tail_gone = 1;
+  /* tail */
+  q = p->next;
+  /* pbuf has successor in chain? */
+  if (q != NULL) {
+    /* assert tot_len invariant: (p->tot_len == p->len + (p->next? p->next->tot_len: 0) */
+    LWIP_ASSERT("p->tot_len == p->len + q->tot_len", q->tot_len == p->tot_len - p->len);
+    /* enforce invariant if assertion is disabled */
+    q->tot_len = p->tot_len - p->len;
+    /* decouple pbuf from remainder */
+    p->next = NULL;
+    /* total length of pbuf p is its own length only */
+    p->tot_len = p->len;
+    /* q is no longer referenced by p, free it */
+    LWIP_DEBUGF(PBUF_DEBUG | DBG_STATE, ("pbuf_dechain: unreferencing %p\n", (void *)q));
+    tail_gone = pbuf_free(q);
+    if (tail_gone > 0) {
+      LWIP_DEBUGF(PBUF_DEBUG | DBG_STATE,
+                  ("pbuf_dechain: deallocated %p (as it is no longer referenced)\n", (void *)q));
+    }
+    /* return remaining tail or NULL if deallocated */
+  }
+  /* assert tot_len invariant: (p->tot_len == p->len + (p->next? p->next->tot_len: 0) */
+  LWIP_ASSERT("p->tot_len == p->len", p->tot_len == p->len);
+  return (tail_gone > 0? NULL: q);
+}
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/raw.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/raw.c
new file mode 100644
index 000000000..5f1f5b24e
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/raw.c
@@ -0,0 +1,328 @@
+/**
+ * @file
+ * 
+ * Implementation of raw protocol PCBs for low-level handling of
+ * different types of protocols besides (or overriding) those
+ * already available in lwIP.
+ *
+ */
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include 
+
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+#include "lwip/memp.h"
+#include "lwip/inet.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/raw.h"
+
+#include "lwip/stats.h"
+
+#include "arch/perf.h"
+#include "lwip/snmp.h"
+
+#if LWIP_RAW
+
+/** The list of RAW PCBs */
+static struct raw_pcb *raw_pcbs = NULL;
+
+void
+raw_init(void)
+{
+  raw_pcbs = NULL;
+}
+
+/**
+ * Determine if in incoming IP packet is covered by a RAW PCB
+ * and if so, pass it to a user-provided receive callback function.
+ *
+ * Given an incoming IP datagram (as a chain of pbufs) this function
+ * finds a corresponding RAW PCB and calls the corresponding receive
+ * callback function.
+ *
+ * @param pbuf pbuf to be demultiplexed to a RAW PCB.
+ * @param netif network interface on which the datagram was received.
+ * @Return - 1 if the packet has been eaten by a RAW PCB receive
+ *           callback function. The caller MAY NOT not reference the
+ *           packet any longer, and MAY NOT call pbuf_free().
+ * @return - 0 if packet is not eaten (pbuf is still referenced by the
+ *           caller).
+ *
+ */
+u8_t
+raw_input(struct pbuf *p, struct netif *inp)
+{
+  struct raw_pcb *pcb;
+  struct ip_hdr *iphdr;
+  int proto;
+  u8_t eaten = 0;
+
+  ( void ) inp;
+
+  iphdr = p->payload;
+  proto = IPH_PROTO(iphdr);
+
+  pcb = raw_pcbs;
+  /* loop through all raw pcbs until the packet is eaten by one */
+  /* this allows multiple pcbs to match against the packet by design */
+  while ((eaten == 0) && (pcb != NULL)) {
+    if (pcb->protocol == proto) {
+      /* receive callback function available? */
+      if (pcb->recv != NULL) {
+        /* the receive callback function did not eat the packet? */
+        if (pcb->recv(pcb->recv_arg, pcb, p, &(iphdr->src)) != 0)
+        {
+          /* receive function ate the packet */
+          p = NULL;
+          eaten = 1;
+        }
+      }
+      /* no receive callback function was set for this raw PCB */
+      /* drop the packet */
+    }
+    pcb = pcb->next;
+  }
+  return eaten;
+}
+
+/**
+ * Bind a RAW PCB.
+ *
+ * @param pcb RAW PCB to be bound with a local address ipaddr.
+ * @param ipaddr local IP address to bind with. Use IP_ADDR_ANY to
+ * bind to all local interfaces.
+ *
+ * @return lwIP error code.
+ * - ERR_OK. Successful. No error occured.
+ * - ERR_USE. The specified IP address is already bound to by
+ * another RAW PCB.
+ *
+ * @see raw_disconnect()
+ */
+err_t
+raw_bind(struct raw_pcb *pcb, struct ip_addr *ipaddr)
+{
+  ip_addr_set(&pcb->local_ip, ipaddr);
+  return ERR_OK;
+}
+
+/**
+ * Connect an RAW PCB. This function is required by upper layers
+ * of lwip. Using the raw api you could use raw_sendto() instead
+ *
+ * This will associate the RAW PCB with the remote address.
+ *
+ * @param pcb RAW PCB to be connected with remote address ipaddr and port.
+ * @param ipaddr remote IP address to connect with.
+ *
+ * @return lwIP error code
+ *
+ * @see raw_disconnect() and raw_sendto()
+ */
+err_t
+raw_connect(struct raw_pcb *pcb, struct ip_addr *ipaddr)
+{
+  ip_addr_set(&pcb->remote_ip, ipaddr);
+  return ERR_OK;
+}
+
+
+/**
+ * Set the callback function for received packets that match the
+ * raw PCB's protocol and binding. 
+ * 
+ * The callback function MUST either
+ * - eat the packet by calling pbuf_free() and returning non-zero. The
+ *   packet will not be passed to other raw PCBs or other protocol layers.
+ * - not free the packet, and return zero. The packet will be matched
+ *   against further PCBs and/or forwarded to another protocol layers.
+ * 
+ * @return non-zero if the packet was free()d, zero if the packet remains
+ * available for others.
+ */
+void
+raw_recv(struct raw_pcb *pcb,
+         u8_t (* recv)(void *arg, struct raw_pcb *upcb, struct pbuf *p,
+                      struct ip_addr *addr),
+         void *recv_arg)
+{
+  /* remember recv() callback and user data */
+  pcb->recv = recv;
+  pcb->recv_arg = recv_arg;
+}
+
+/**
+ * Send the raw IP packet to the given address. Note that actually you cannot
+ * modify the IP headers (this is inconsistent with the receive callback where
+ * you actually get the IP headers), you can only specify the IP payload here.
+ * It requires some more changes in lwIP. (there will be a raw_send() function
+ * then.)
+ *
+ * @param pcb the raw pcb which to send
+ * @param p the IP payload to send
+ * @param ipaddr the destination address of the IP packet
+ *
+ */
+err_t
+raw_sendto(struct raw_pcb *pcb, struct pbuf *p, struct ip_addr *ipaddr)
+{
+  err_t err;
+  struct netif *netif;
+  struct ip_addr *src_ip;
+  struct pbuf *q; /* q will be sent down the stack */
+  
+  LWIP_DEBUGF(RAW_DEBUG | DBG_TRACE | 3, ("raw_sendto\n"));
+  
+  /* not enough space to add an IP header to first pbuf in given p chain? */
+  if (pbuf_header(p, IP_HLEN)) {
+    /* allocate header in new pbuf */
+    q = pbuf_alloc(PBUF_IP, 0, PBUF_RAM);
+    /* new header pbuf could not be allocated? */
+    if (q == NULL) {
+      LWIP_DEBUGF(RAW_DEBUG | DBG_TRACE | 2, ("raw_sendto: could not allocate header\n"));
+      return ERR_MEM;
+    }
+    /* chain header q in front of given pbuf p */
+    pbuf_chain(q, p);
+    /* { first pbuf q points to header pbuf } */
+    LWIP_DEBUGF(RAW_DEBUG, ("raw_sendto: added header pbuf %p before given pbuf %p\n", (void *)q, (void *)p));
+  }  else {
+    /* first pbuf q equals given pbuf */
+    q = p;
+    pbuf_header(q, -IP_HLEN);
+  }
+  
+  if ((netif = ip_route(ipaddr)) == NULL) {
+    LWIP_DEBUGF(RAW_DEBUG | 1, ("raw_sendto: No route to 0x%lx\n", ipaddr->addr));
+#if RAW_STATS
+    /*    ++lwip_stats.raw.rterr;*/
+#endif /* RAW_STATS */
+    /* free any temporary header pbuf allocated by pbuf_header() */
+    if (q != p) {
+      pbuf_free(q);
+    }
+    return ERR_RTE;
+  }
+
+  if (ip_addr_isany(&pcb->local_ip)) {
+    /* use outgoing network interface IP address as source address */
+    src_ip = &(netif->ip_addr);
+  } else {
+    /* use RAW PCB local IP address as source address */
+    src_ip = &(pcb->local_ip);
+  }
+
+  err = ip_output_if (q, src_ip, ipaddr, pcb->ttl, pcb->tos, pcb->protocol, netif);
+
+  /* did we chain a header earlier? */
+  if (q != p) {
+    /* free the header */
+    pbuf_free(q);
+  }
+  return err;
+}
+
+/**
+ * Send the raw IP packet to the address given by raw_connect()
+ *
+ * @param pcb the raw pcb which to send
+ * @param p the IP payload to send
+ * @param ipaddr the destination address of the IP packet
+ *
+ */
+err_t
+raw_send(struct raw_pcb *pcb, struct pbuf *p)
+{
+  return raw_sendto(pcb, p, &pcb->remote_ip);
+}
+
+/**
+ * Remove an RAW PCB.
+ *
+ * @param pcb RAW PCB to be removed. The PCB is removed from the list of
+ * RAW PCB's and the data structure is freed from memory.
+ *
+ * @see raw_new()
+ */
+void
+raw_remove(struct raw_pcb *pcb)
+{
+  struct raw_pcb *pcb2;
+  /* pcb to be removed is first in list? */
+  if (raw_pcbs == pcb) {
+    /* make list start at 2nd pcb */
+    raw_pcbs = raw_pcbs->next;
+    /* pcb not 1st in list */
+  } else for(pcb2 = raw_pcbs; pcb2 != NULL; pcb2 = pcb2->next) {
+    /* find pcb in raw_pcbs list */
+    if (pcb2->next != NULL && pcb2->next == pcb) {
+      /* remove pcb from list */
+      pcb2->next = pcb->next;
+    }
+  }
+  memp_free(MEMP_RAW_PCB, pcb);
+}
+
+/**
+ * Create a RAW PCB.
+ *
+ * @return The RAW PCB which was created. NULL if the PCB data structure
+ * could not be allocated.
+ *
+ * @param proto the protocol number of the IPs payload (e.g. IP_PROTO_ICMP)
+ *
+ * @see raw_remove()
+ */
+struct raw_pcb *
+raw_new(u16_t proto) {
+  struct raw_pcb *pcb;
+
+  LWIP_DEBUGF(RAW_DEBUG | DBG_TRACE | 3, ("raw_new\n"));
+
+  pcb = memp_malloc(MEMP_RAW_PCB);
+  /* could allocate RAW PCB? */
+  if (pcb != NULL) {
+    /* initialize PCB to all zeroes */
+    memset(pcb, 0, sizeof(struct raw_pcb));
+    pcb->protocol = proto;
+    pcb->ttl = RAW_TTL;
+    pcb->next = raw_pcbs;
+    raw_pcbs = pcb;
+  }
+  return pcb;
+}
+
+#endif /* LWIP_RAW */
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/stats.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/stats.c
new file mode 100644
index 000000000..5f9689258
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/stats.c
@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include 
+
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+
+#include "lwip/stats.h"
+#include "lwip/mem.h"
+
+
+#if LWIP_STATS
+struct stats_ lwip_stats;
+
+void
+stats_init(void)
+{
+  memset(&lwip_stats, 0, sizeof(struct stats_));
+}
+#if LWIP_STATS_DISPLAY
+void
+stats_display_proto(struct stats_proto *proto, char *name)
+{
+  LWIP_PLATFORM_DIAG(("\n%s\n\t", name));
+  LWIP_PLATFORM_DIAG(("xmit: %d\n\t", proto->xmit)); 
+  LWIP_PLATFORM_DIAG(("rexmit: %d\n\t", proto->rexmit)); 
+  LWIP_PLATFORM_DIAG(("recv: %d\n\t", proto->recv)); 
+  LWIP_PLATFORM_DIAG(("fw: %d\n\t", proto->fw)); 
+  LWIP_PLATFORM_DIAG(("drop: %d\n\t", proto->drop)); 
+  LWIP_PLATFORM_DIAG(("chkerr: %d\n\t", proto->chkerr)); 
+  LWIP_PLATFORM_DIAG(("lenerr: %d\n\t", proto->lenerr)); 
+  LWIP_PLATFORM_DIAG(("memerr: %d\n\t", proto->memerr)); 
+  LWIP_PLATFORM_DIAG(("rterr: %d\n\t", proto->rterr)); 
+  LWIP_PLATFORM_DIAG(("proterr: %d\n\t", proto->proterr)); 
+  LWIP_PLATFORM_DIAG(("opterr: %d\n\t", proto->opterr)); 
+  LWIP_PLATFORM_DIAG(("err: %d\n\t", proto->err)); 
+  LWIP_PLATFORM_DIAG(("cachehit: %d\n", proto->cachehit)); 
+}
+
+void
+stats_display_pbuf(struct stats_pbuf *pbuf)
+{
+  LWIP_PLATFORM_DIAG(("\nPBUF\n\t"));
+  LWIP_PLATFORM_DIAG(("avail: %d\n\t", pbuf->avail)); 
+  LWIP_PLATFORM_DIAG(("used: %d\n\t", pbuf->used)); 
+  LWIP_PLATFORM_DIAG(("max: %d\n\t", pbuf->max)); 
+  LWIP_PLATFORM_DIAG(("err: %d\n\t", pbuf->err)); 
+  LWIP_PLATFORM_DIAG(("alloc_locked: %d\n\t", pbuf->alloc_locked)); 
+  LWIP_PLATFORM_DIAG(("refresh_locked: %d\n", pbuf->refresh_locked)); 
+}
+
+void
+stats_display_mem(struct stats_mem *mem, char *name)
+{
+  LWIP_PLATFORM_DIAG(("\n MEM %s\n\t", name));
+  LWIP_PLATFORM_DIAG(("avail: %d\n\t", mem->avail)); 
+  LWIP_PLATFORM_DIAG(("used: %d\n\t", mem->used)); 
+  LWIP_PLATFORM_DIAG(("max: %d\n\t", mem->max)); 
+  LWIP_PLATFORM_DIAG(("err: %d\n", mem->err));
+  
+}
+
+void
+stats_display(void)
+{
+  int i;
+  char * memp_names[] = {"PBUF", "RAW_PCB", "UDP_PCB", "TCP_PCB", "TCP_PCB_LISTEN",
+	  		"TCP_SEG", "NETBUF", "NETCONN", "API_MSG", "TCP_MSG", "TIMEOUT"};
+  stats_display_proto(&lwip_stats.link, "LINK");
+  stats_display_proto(&lwip_stats.ip_frag, "IP_FRAG");
+  stats_display_proto(&lwip_stats.ip, "IP");
+  stats_display_proto(&lwip_stats.icmp, "ICMP");
+  stats_display_proto(&lwip_stats.udp, "UDP");
+  stats_display_proto(&lwip_stats.tcp, "TCP");
+  stats_display_pbuf(&lwip_stats.pbuf);
+  stats_display_mem(&lwip_stats.mem, "HEAP");
+  for (i = 0; i < MEMP_MAX; i++) {
+    stats_display_mem(&lwip_stats.memp[i], memp_names[i]);
+  }
+	
+}
+#endif /* LWIP_STATS_DISPLAY */
+#endif /* LWIP_STATS */
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/sys.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/sys.c
new file mode 100644
index 000000000..8134566ea
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/sys.c
@@ -0,0 +1,294 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/sys.h"
+#include "lwip/opt.h"
+#include "lwip/def.h"
+#include "lwip/memp.h"
+
+#if (NO_SYS == 0)
+
+struct sswt_cb
+{
+    int timeflag;
+    sys_sem_t *psem;
+};
+
+
+
+void
+sys_mbox_fetch(sys_mbox_t mbox, void **msg)
+{
+  u32_t time;
+  struct sys_timeouts *timeouts;
+  struct sys_timeout *tmptimeout;
+  sys_timeout_handler h;
+  void *arg;
+
+
+ again:
+  timeouts = sys_arch_timeouts();
+
+  if (!timeouts || !timeouts->next) {
+    sys_arch_mbox_fetch(mbox, msg, 0);
+  } else {
+    if (timeouts->next->time > 0) {
+      time = sys_arch_mbox_fetch(mbox, msg, timeouts->next->time);
+    } else {
+      time = SYS_ARCH_TIMEOUT;
+    }
+
+    if (time == SYS_ARCH_TIMEOUT) {
+      /* If time == SYS_ARCH_TIMEOUT, a timeout occured before a message
+   could be fetched. We should now call the timeout handler and
+   deallocate the memory allocated for the timeout. */
+      tmptimeout = timeouts->next;
+      timeouts->next = tmptimeout->next;
+      h = tmptimeout->h;
+      arg = tmptimeout->arg;
+      memp_free(MEMP_SYS_TIMEOUT, tmptimeout);
+      if (h != NULL) {
+        LWIP_DEBUGF(SYS_DEBUG, ("smf calling h=%p(%p)\n", (void *)h, (void *)arg));
+      	h(arg);
+      }
+
+      /* We try again to fetch a message from the mbox. */
+      goto again;
+    } else {
+      /* If time != SYS_ARCH_TIMEOUT, a message was received before the timeout
+   occured. The time variable is set to the number of
+   milliseconds we waited for the message. */
+      if (time <= timeouts->next->time) {
+  timeouts->next->time -= time;
+      } else {
+  timeouts->next->time = 0;
+      }
+    }
+
+  }
+}
+
+void
+sys_sem_wait(sys_sem_t sem)
+{
+  u32_t time;
+  struct sys_timeouts *timeouts;
+  struct sys_timeout *tmptimeout;
+  sys_timeout_handler h;
+  void *arg;
+
+  /*  while (sys_arch_sem_wait(sem, 1000) == 0);
+      return;*/
+
+ again:
+
+  timeouts = sys_arch_timeouts();
+
+  if (!timeouts || !timeouts->next) {
+    sys_arch_sem_wait(sem, 0);
+  } else {
+    if (timeouts->next->time > 0) {
+      time = sys_arch_sem_wait(sem, timeouts->next->time);
+    } else {
+      time = SYS_ARCH_TIMEOUT;
+    }
+
+    if (time == SYS_ARCH_TIMEOUT) {
+      /* If time == SYS_ARCH_TIMEOUT, a timeout occured before a message
+   could be fetched. We should now call the timeout handler and
+   deallocate the memory allocated for the timeout. */
+      tmptimeout = timeouts->next;
+      timeouts->next = tmptimeout->next;
+      h = tmptimeout->h;
+      arg = tmptimeout->arg;
+      memp_free(MEMP_SYS_TIMEOUT, tmptimeout);
+      if (h != NULL) {
+        LWIP_DEBUGF(SYS_DEBUG, ("ssw h=%p(%p)\n", (void *)h, (void *)arg));
+        h(arg);
+      }
+
+
+      /* We try again to fetch a message from the mbox. */
+      goto again;
+    } else {
+      /* If time != SYS_ARCH_TIMEOUT, a message was received before the timeout
+   occured. The time variable is set to the number of
+   milliseconds we waited for the message. */
+      if (time <= timeouts->next->time) {
+  timeouts->next->time -= time;
+      } else {
+  timeouts->next->time = 0;
+      }
+    }
+
+  }
+}
+
+void
+sys_timeout(u32_t msecs, sys_timeout_handler h, void *arg)
+{
+  struct sys_timeouts *timeouts;
+  struct sys_timeout *timeout, *t;
+
+  timeout = memp_malloc(MEMP_SYS_TIMEOUT);
+  if (timeout == NULL) {
+    return;
+  }
+  timeout->next = NULL;
+  timeout->h = h;
+  timeout->arg = arg;
+  timeout->time = msecs;
+
+  timeouts = sys_arch_timeouts();
+
+  LWIP_DEBUGF(SYS_DEBUG, ("sys_timeout: %p msecs=%lu h=%p arg=%p\n",
+    (void *)timeout, msecs, (void *)h, (void *)arg));
+
+  LWIP_ASSERT("sys_timeout: timeouts != NULL", timeouts != NULL);
+
+  if (timeouts->next == NULL) {
+    timeouts->next = timeout;
+    return;
+  }
+
+  if (timeouts->next->time > msecs) {
+    timeouts->next->time -= msecs;
+    timeout->next = timeouts->next;
+    timeouts->next = timeout;
+  } else {
+    for(t = timeouts->next; t != NULL; t = t->next) {
+      timeout->time -= t->time;
+      if (t->next == NULL || t->next->time > timeout->time) {
+        if (t->next != NULL) {
+          t->next->time -= timeout->time;
+        }
+        timeout->next = t->next;
+        t->next = timeout;
+        break;
+      }
+    }
+  }
+
+}
+
+/* Go through timeout list (for this task only) and remove the first matching entry,
+   even though the timeout has not triggered yet.
+*/
+
+void
+sys_untimeout(sys_timeout_handler h, void *arg)
+{
+    struct sys_timeouts *timeouts;
+    struct sys_timeout *prev_t, *t;
+
+    timeouts = sys_arch_timeouts();
+
+    if (timeouts->next == NULL)
+        return;
+
+    for (t = timeouts->next, prev_t = NULL; t != NULL; prev_t = t, t = t->next)
+    {
+        if ((t->h == h) && (t->arg == arg))
+        {
+            /* We have a match */
+            /* Unlink from previous in list */
+            if (prev_t == NULL)
+                timeouts->next = t->next;
+            else
+                prev_t->next = t->next;
+            /* If not the last one, add time of this one back to next */
+            if (t->next != NULL)
+                t->next->time += t->time;
+            memp_free(MEMP_SYS_TIMEOUT, t);
+            return;
+        }
+    }
+    return;
+}
+
+
+
+
+
+static void
+sswt_handler(void *arg)
+{
+    struct sswt_cb *sswt_cb = (struct sswt_cb *) arg;
+
+    /* Timeout. Set flag to TRUE and signal semaphore */
+    sswt_cb->timeflag = 1;
+    sys_sem_signal(*(sswt_cb->psem));
+}
+
+/* Wait for a semaphore with timeout (specified in ms) */
+/* timeout = 0: wait forever */
+/* Returns 0 on timeout. 1 otherwise */
+
+int
+sys_sem_wait_timeout(sys_sem_t sem, u32_t timeout)
+{
+    struct sswt_cb sswt_cb;
+
+    sswt_cb.psem = &sem;
+    sswt_cb.timeflag = 0;
+
+    /* If timeout is zero, then just wait forever */
+    if (timeout > 0)
+        /* Create a timer and pass it the address of our flag */
+        sys_timeout(timeout, sswt_handler, &sswt_cb);
+    sys_sem_wait(sem);
+    /* Was it a timeout? */
+    if (sswt_cb.timeflag)
+    {
+        /* timeout */
+        return 0;
+    } else {
+        /* Not a timeout. Remove timeout entry */
+        sys_untimeout(sswt_handler, &sswt_cb);
+        return 1;
+    }
+
+}
+
+
+void
+sys_msleep(u32_t ms)
+{
+  sys_sem_t delaysem = sys_sem_new(0);
+
+  sys_sem_wait_timeout(delaysem, ms);
+
+  sys_sem_free(delaysem);
+}
+
+
+#endif /* NO_SYS */
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/tcp.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/tcp.c
new file mode 100644
index 000000000..b36b79416
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/tcp.c
@@ -0,0 +1,1263 @@
+/**
+ * @file
+ *
+ * Transmission Control Protocol for IP
+ *
+ * This file contains common functions for the TCP implementation, such as functinos
+ * for manipulating the data structures and the TCP timer functions. TCP functions
+ * related to input and output is found in tcp_in.c and tcp_out.c respectively.
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include 
+
+#include "lwip/opt.h"
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+
+#include "lwip/tcp.h"
+#if LWIP_TCP
+
+/* Incremented every coarse grained timer shot
+   (typically every 500 ms, determined by TCP_COARSE_TIMEOUT). */
+u32_t tcp_ticks;
+const u8_t tcp_backoff[13] =
+    { 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7};
+
+/* The TCP PCB lists. */
+
+/** List of all TCP PCBs in LISTEN state */
+union tcp_listen_pcbs_t tcp_listen_pcbs;
+/** List of all TCP PCBs that are in a state in which
+ * they accept or send data. */
+struct tcp_pcb *tcp_active_pcbs;  
+/** List of all TCP PCBs in TIME-WAIT state */
+struct tcp_pcb *tcp_tw_pcbs;
+
+struct tcp_pcb *tcp_tmp_pcb;
+
+static u8_t tcp_timer;
+static u16_t tcp_new_port(void);
+
+/**
+ * Initializes the TCP layer.
+ */
+void
+tcp_init(void)
+{
+  /* Clear globals. */
+  tcp_listen_pcbs.listen_pcbs = NULL;
+  tcp_active_pcbs = NULL;
+  tcp_tw_pcbs = NULL;
+  tcp_tmp_pcb = NULL;
+  
+  /* initialize timer */
+  tcp_ticks = 0;
+  tcp_timer = 0;
+  
+}
+
+/**
+ * Called periodically to dispatch TCP timers.
+ *
+ */
+void
+tcp_tmr(void)
+{
+  /* Call tcp_fasttmr() every 250 ms */
+  tcp_fasttmr();
+
+  if (++tcp_timer & 1) {
+    /* Call tcp_tmr() every 500 ms, i.e., every other timer
+       tcp_tmr() is called. */
+    tcp_slowtmr();
+  }
+}
+
+/**
+ * Closes the connection held by the PCB.
+ *
+ */
+err_t
+tcp_close(struct tcp_pcb *pcb)
+{
+  err_t err;
+
+#if TCP_DEBUG
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_close: closing in state "));
+  tcp_debug_print_state(pcb->state);
+  LWIP_DEBUGF(TCP_DEBUG, ("\n"));
+#endif /* TCP_DEBUG */
+  switch (pcb->state) {
+  case CLOSED:
+    /* Closing a pcb in the CLOSED state might seem erroneous,
+     * however, it is in this state once allocated and as yet unused
+     * and the user needs some way to free it should the need arise.
+     * Calling tcp_close() with a pcb that has already been closed, (i.e. twice)
+     * or for a pcb that has been used and then entered the CLOSED state 
+     * is erroneous, but this should never happen as the pcb has in those cases
+     * been freed, and so any remaining handles are bogus. */
+    err = ERR_OK;
+    memp_free(MEMP_TCP_PCB, pcb);
+    pcb = NULL;
+    break;
+  case LISTEN:
+    err = ERR_OK;
+    tcp_pcb_remove((struct tcp_pcb **)&tcp_listen_pcbs.pcbs, pcb);
+    memp_free(MEMP_TCP_PCB_LISTEN, pcb);
+    pcb = NULL;
+    break;
+  case SYN_SENT:
+    err = ERR_OK;
+    tcp_pcb_remove(&tcp_active_pcbs, pcb);
+    memp_free(MEMP_TCP_PCB, pcb);
+    pcb = NULL;
+    break;
+  case SYN_RCVD:
+  case ESTABLISHED:
+    err = tcp_send_ctrl(pcb, TCP_FIN);
+    if (err == ERR_OK) {
+      pcb->state = FIN_WAIT_1;
+    }
+    break;
+  case CLOSE_WAIT:
+    err = tcp_send_ctrl(pcb, TCP_FIN);
+    if (err == ERR_OK) {
+      pcb->state = LAST_ACK;
+    }
+    break;
+  default:
+    /* Has already been closed, do nothing. */
+    err = ERR_OK;
+    pcb = NULL;
+    break;
+  }
+
+  if (pcb != NULL && err == ERR_OK) {
+    err = tcp_output(pcb);
+  }
+  return err;
+}
+
+/**
+ * Aborts a connection by sending a RST to the remote host and deletes
+ * the local protocol control block. This is done when a connection is
+ * killed because of shortage of memory.
+ *
+ */
+void
+tcp_abort(struct tcp_pcb *pcb)
+{
+  u32_t seqno, ackno;
+  u16_t remote_port, local_port;
+  struct ip_addr remote_ip, local_ip;
+#if LWIP_CALLBACK_API  
+  void (* errf)(void *arg, err_t err);
+#endif /* LWIP_CALLBACK_API */
+  void *errf_arg;
+
+  
+  /* Figure out on which TCP PCB list we are, and remove us. If we
+     are in an active state, call the receive function associated with
+     the PCB with a NULL argument, and send an RST to the remote end. */
+  if (pcb->state == TIME_WAIT) {
+    tcp_pcb_remove(&tcp_tw_pcbs, pcb);
+    memp_free(MEMP_TCP_PCB, pcb);
+  } else {
+    seqno = pcb->snd_nxt;
+    ackno = pcb->rcv_nxt;
+    ip_addr_set(&local_ip, &(pcb->local_ip));
+    ip_addr_set(&remote_ip, &(pcb->remote_ip));
+    local_port = pcb->local_port;
+    remote_port = pcb->remote_port;
+#if LWIP_CALLBACK_API
+    errf = pcb->errf;
+#endif /* LWIP_CALLBACK_API */
+    errf_arg = pcb->callback_arg;
+    tcp_pcb_remove(&tcp_active_pcbs, pcb);
+    if (pcb->unacked != NULL) {
+      tcp_segs_free(pcb->unacked);
+    }
+    if (pcb->unsent != NULL) {
+      tcp_segs_free(pcb->unsent);
+    }
+#if TCP_QUEUE_OOSEQ    
+    if (pcb->ooseq != NULL) {
+      tcp_segs_free(pcb->ooseq);
+    }
+#endif /* TCP_QUEUE_OOSEQ */
+    memp_free(MEMP_TCP_PCB, pcb);
+    TCP_EVENT_ERR(errf, errf_arg, ERR_ABRT);
+    LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_abort: sending RST\n"));
+    tcp_rst(seqno, ackno, &local_ip, &remote_ip, local_port, remote_port);
+  }
+}
+
+/**
+ * Binds the connection to a local portnumber and IP address. If the
+ * IP address is not given (i.e., ipaddr == NULL), the IP address of
+ * the outgoing network interface is used instead.
+ *
+ */
+
+err_t
+tcp_bind(struct tcp_pcb *pcb, struct ip_addr *ipaddr, u16_t port)
+{
+  struct tcp_pcb *cpcb;
+#if SO_REUSE
+  int reuse_port_all_set = 1;
+#endif /* SO_REUSE */
+
+  if (port == 0) {
+    port = tcp_new_port();
+  }
+#if SO_REUSE == 0
+  /* Check if the address already is in use. */
+  for(cpcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs;
+      cpcb != NULL; cpcb = cpcb->next) {
+    if (cpcb->local_port == port) {
+      if (ip_addr_isany(&(cpcb->local_ip)) ||
+        ip_addr_isany(ipaddr) ||
+        ip_addr_cmp(&(cpcb->local_ip), ipaddr)) {
+          return ERR_USE;
+      }
+    }
+  }
+  for(cpcb = tcp_active_pcbs;
+      cpcb != NULL; cpcb = cpcb->next) {
+    if (cpcb->local_port == port) {
+      if (ip_addr_isany(&(cpcb->local_ip)) ||
+   ip_addr_isany(ipaddr) ||
+   ip_addr_cmp(&(cpcb->local_ip), ipaddr)) {
+  return ERR_USE;
+      }
+    }
+  }
+#else /* SO_REUSE */
+  /* Search through list of PCB's in LISTEN state. 
+     
+  If there is a PCB bound to specified port and IP_ADDR_ANY another PCB can be bound to the interface IP
+  or to the loopback address on the same port if SOF_REUSEADDR is set. Any combination of PCB's bound to 
+  the same local port, but to one address out of {IP_ADDR_ANY, 127.0.0.1, interface IP} at a time is valid.
+  But no two PCB's bound to same local port and same local address is valid.
+  
+  If SOF_REUSEPORT is set several PCB's can be bound to same local port and same local address also. But then 
+  all PCB's must have the SOF_REUSEPORT option set.
+  
+  When the two options aren't set and specified port is already bound, ERR_USE is returned saying that 
+  address is already in use. */
+  for(cpcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs; cpcb != NULL; cpcb = cpcb->next) {
+    if(cpcb->local_port == port) {
+      if(ip_addr_cmp(&(cpcb->local_ip), ipaddr)) {
+        if(pcb->so_options & SOF_REUSEPORT) {
+          LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in listening PCB's: SO_REUSEPORT set and same address.\n"));
+          reuse_port_all_set = (reuse_port_all_set && (cpcb->so_options & SOF_REUSEPORT));
+        }
+        else {
+          LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in listening PCB's: SO_REUSEPORT not set and same address.\n"));
+          return ERR_USE;
+        }
+      }
+      else if((ip_addr_isany(ipaddr) && !ip_addr_isany(&(cpcb->local_ip))) ||
+              (!ip_addr_isany(ipaddr) && ip_addr_isany(&(cpcb->local_ip)))) {
+        if(!(pcb->so_options & SOF_REUSEADDR) && !(pcb->so_options & SOF_REUSEPORT)) {
+          LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in listening PCB's SO_REUSEPORT or SO_REUSEADDR not set and not the same address.\n"));
+          return ERR_USE;
+        }      
+        else {
+          LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in listening PCB's SO_REUSEPORT or SO_REUSEADDR set and not the same address.\n"));
+        }     
+      }
+    }
+  }
+
+  /* Search through list of PCB's in a state in which they can accept or send data. Same decription as for 
+     PCB's in state LISTEN applies to this PCB's regarding the options SOF_REUSEADDR and SOF_REUSEPORT. */
+  for(cpcb = tcp_active_pcbs; cpcb != NULL; cpcb = cpcb->next) {
+    if(cpcb->local_port == port) {
+      if(ip_addr_cmp(&(cpcb->local_ip), ipaddr)) {
+        if(pcb->so_options & SOF_REUSEPORT) {
+          LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in active PCB's SO_REUSEPORT set and same address.\n"));
+          reuse_port_all_set = (reuse_port_all_set && (cpcb->so_options & SOF_REUSEPORT));
+        }
+        else {
+          LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in active PCB's SO_REUSEPORT not set and same address.\n"));
+          return ERR_USE;
+        }
+      }
+      else if((ip_addr_isany(ipaddr) && !ip_addr_isany(&(cpcb->local_ip))) ||
+              (!ip_addr_isany(ipaddr) && ip_addr_isany(&(cpcb->local_ip)))) {
+        if(!(pcb->so_options & SOF_REUSEADDR) && !(pcb->so_options & SOF_REUSEPORT)) {
+          LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in active PCB's SO_REUSEPORT or SO_REUSEADDR not set and not the same address.\n"));
+          return ERR_USE;
+        }   
+        else {
+          LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in active PCB's SO_REUSEPORT or SO_REUSEADDR set and not the same address.\n"));
+        }        
+      }
+    }
+  }
+
+  /* Search through list of PCB's in TIME_WAIT state. If SO_REUSEADDR is set a bound combination [IP, port} 
+     can be rebound. The same applies when SOF_REUSEPORT is set. 
+     
+     If SOF_REUSEPORT is set several PCB's can be bound to same local port and same local address also. But then 
+     all PCB's must have the SOF_REUSEPORT option set.
+     
+     When the two options aren't set and specified port is already bound, ERR_USE is returned saying that 
+     address is already in use. */
+  for(cpcb = tcp_tw_pcbs; cpcb != NULL; cpcb = cpcb->next) {
+    if(cpcb->local_port == port) {
+      if(ip_addr_cmp(&(cpcb->local_ip), ipaddr)) {
+        if(!(pcb->so_options & SOF_REUSEADDR) && !(pcb->so_options & SOF_REUSEPORT)) {
+          LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in TIME_WAIT PCB's SO_REUSEPORT or SO_REUSEADDR not set and same address.\n"));
+          return ERR_USE;
+        }
+        else if(pcb->so_options & SOF_REUSEPORT) {
+          LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in TIME_WAIT PCB's SO_REUSEPORT set and same address.\n"));
+          reuse_port_all_set = (reuse_port_all_set && (cpcb->so_options & SOF_REUSEPORT));
+        }
+      }
+    }
+  }
+
+  /* If SOF_REUSEPORT isn't set in all PCB's bound to specified port and local address specified then 
+     {IP, port} can't be reused. */
+  if(!reuse_port_all_set) {
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: not all sockets have SO_REUSEPORT set.\n"));
+    return ERR_USE;
+  }
+#endif /* SO_REUSE */
+
+  if (!ip_addr_isany(ipaddr)) {
+    pcb->local_ip = *ipaddr;
+  }
+  pcb->local_port = port;
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: bind to port %u\n", port));
+  return ERR_OK;
+}
+#if LWIP_CALLBACK_API
+static err_t
+tcp_accept_null(void *arg, struct tcp_pcb *pcb, err_t err)
+{
+  (void)arg;
+  (void)pcb;
+  (void)err;
+
+  return ERR_ABRT;
+}
+#endif /* LWIP_CALLBACK_API */
+
+/**
+ * Set the state of the connection to be LISTEN, which means that it
+ * is able to accept incoming connections. The protocol control block
+ * is reallocated in order to consume less memory. Setting the
+ * connection to LISTEN is an irreversible process.
+ *
+ */
+struct tcp_pcb *
+tcp_listen(struct tcp_pcb *pcb)
+{
+  struct tcp_pcb_listen *lpcb;
+
+  /* already listening? */
+  if (pcb->state == LISTEN) {
+    return pcb;
+  }
+  lpcb = memp_malloc(MEMP_TCP_PCB_LISTEN);
+  if (lpcb == NULL) {
+    return NULL;
+  }
+  lpcb->callback_arg = pcb->callback_arg;
+  lpcb->local_port = pcb->local_port;
+  lpcb->state = LISTEN;
+  lpcb->so_options = pcb->so_options;
+  lpcb->so_options |= SOF_ACCEPTCONN;
+  lpcb->ttl = pcb->ttl;
+  lpcb->tos = pcb->tos;
+  ip_addr_set(&lpcb->local_ip, &pcb->local_ip);
+  memp_free(MEMP_TCP_PCB, pcb);
+#if LWIP_CALLBACK_API
+  lpcb->accept = tcp_accept_null;
+#endif /* LWIP_CALLBACK_API */
+  TCP_REG(&tcp_listen_pcbs.listen_pcbs, lpcb);
+  return (struct tcp_pcb *)lpcb;
+}
+
+/**
+ * This function should be called by the application when it has
+ * processed the data. The purpose is to advertise a larger window
+ * when the data has been processed.
+ *
+ */
+void
+tcp_recved(struct tcp_pcb *pcb, u16_t len)
+{
+  if ((u32_t)pcb->rcv_wnd + len > TCP_WND) {
+    pcb->rcv_wnd = TCP_WND;
+  } else {
+    pcb->rcv_wnd += len;
+  }
+  if (!(pcb->flags & TF_ACK_DELAY) &&
+     !(pcb->flags & TF_ACK_NOW)) {
+    /*
+     * We send an ACK here (if one is not already pending, hence
+     * the above tests) as tcp_recved() implies that the application
+     * has processed some data, and so we can open the receiver's
+     * window to allow more to be transmitted.  This could result in
+     * two ACKs being sent for each received packet in some limited cases
+     * (where the application is only receiving data, and is slow to
+     * process it) but it is necessary to guarantee that the sender can
+     * continue to transmit.
+     */
+    tcp_ack(pcb);
+  } 
+  else if (pcb->flags & TF_ACK_DELAY && pcb->rcv_wnd >= TCP_WND/2) {
+    /* If we can send a window update such that there is a full
+     * segment available in the window, do so now.  This is sort of
+     * nagle-like in its goals, and tries to hit a compromise between
+     * sending acks each time the window is updated, and only sending
+     * window updates when a timer expires.  The "threshold" used
+     * above (currently TCP_WND/2) can be tuned to be more or less
+     * aggressive  */
+    tcp_ack_now(pcb);
+  }
+
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_recved: recveived %u bytes, wnd %u (%u).\n",
+         len, pcb->rcv_wnd, TCP_WND - pcb->rcv_wnd));
+}
+
+/**
+ * A nastly hack featuring 'goto' statements that allocates a
+ * new TCP local port.
+ */
+static u16_t
+tcp_new_port(void)
+{
+  struct tcp_pcb *pcb;
+#ifndef TCP_LOCAL_PORT_RANGE_START
+#define TCP_LOCAL_PORT_RANGE_START 4096
+#define TCP_LOCAL_PORT_RANGE_END   0x7fff
+#endif
+  static u16_t port = TCP_LOCAL_PORT_RANGE_START;
+  
+ again:
+  if (++port > TCP_LOCAL_PORT_RANGE_END) {
+    port = TCP_LOCAL_PORT_RANGE_START;
+  }
+  
+  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+    if (pcb->local_port == port) {
+      goto again;
+    }
+  }
+  for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
+    if (pcb->local_port == port) {
+      goto again;
+    }
+  }
+  for(pcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs; pcb != NULL; pcb = pcb->next) {
+    if (pcb->local_port == port) {
+      goto again;
+    }
+  }
+  return port;
+}
+
+/**
+ * Connects to another host. The function given as the "connected"
+ * argument will be called when the connection has been established.
+ *
+ */
+err_t
+tcp_connect(struct tcp_pcb *pcb, struct ip_addr *ipaddr, u16_t port,
+      err_t (* connected)(void *arg, struct tcp_pcb *tpcb, err_t err))
+{
+  u32_t optdata;
+  err_t ret;
+  u32_t iss;
+
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_connect to port %u\n", port));
+  if (ipaddr != NULL) {
+    pcb->remote_ip = *ipaddr;
+  } else {
+    return ERR_VAL;
+  }
+  pcb->remote_port = port;
+  if (pcb->local_port == 0) {
+    pcb->local_port = tcp_new_port();
+  }
+  iss = tcp_next_iss();
+  pcb->rcv_nxt = 0;
+  pcb->snd_nxt = iss;
+  pcb->lastack = iss - 1;
+  pcb->snd_lbb = iss - 1;
+  pcb->rcv_wnd = TCP_WND;
+  pcb->snd_wnd = TCP_WND;
+  pcb->mss = TCP_MSS;
+  pcb->cwnd = 1;
+  pcb->ssthresh = pcb->mss * 10;
+  pcb->state = SYN_SENT;
+#if LWIP_CALLBACK_API  
+  pcb->connected = connected;
+#endif /* LWIP_CALLBACK_API */  
+  TCP_REG(&tcp_active_pcbs, pcb);
+  
+  /* Build an MSS option */
+  optdata = htonl(((u32_t)2 << 24) | 
+      ((u32_t)4 << 16) | 
+      (((u32_t)pcb->mss / 256) << 8) |
+      (pcb->mss & 255));
+
+  ret = tcp_enqueue(pcb, NULL, 0, TCP_SYN, 0, (u8_t *)&optdata, 4);
+  if (ret == ERR_OK) { 
+    tcp_output(pcb);
+  }
+  return ret;
+} 
+
+/**
+ * Called every 500 ms and implements the retransmission timer and the timer that
+ * removes PCBs that have been in TIME-WAIT for enough time. It also increments
+ * various timers such as the inactivity timer in each PCB.
+ */
+void
+tcp_slowtmr(void)
+{
+  struct tcp_pcb *pcb, *pcb2, *prev;
+  u32_t eff_wnd;
+  u8_t pcb_remove;      /* flag if a PCB should be removed */
+  err_t err;
+
+  err = ERR_OK;
+
+  ++tcp_ticks;
+
+  /* Steps through all of the active PCBs. */
+  prev = NULL;
+  pcb = tcp_active_pcbs;
+  if (pcb == NULL) {
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: no active pcbs\n"));
+  }
+  while (pcb != NULL) {
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: processing active pcb\n"));
+    LWIP_ASSERT("tcp_slowtmr: active pcb->state != CLOSED\n", pcb->state != CLOSED);
+    LWIP_ASSERT("tcp_slowtmr: active pcb->state != LISTEN\n", pcb->state != LISTEN);
+    LWIP_ASSERT("tcp_slowtmr: active pcb->state != TIME-WAIT\n", pcb->state != TIME_WAIT);
+
+    pcb_remove = 0;
+
+    if (pcb->state == SYN_SENT && pcb->nrtx == TCP_SYNMAXRTX) {
+      ++pcb_remove;
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max SYN retries reached\n"));
+    }
+    else if (pcb->nrtx == TCP_MAXRTX) {
+      ++pcb_remove;
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max DATA retries reached\n"));
+    } else {
+      ++pcb->rtime;
+      if (pcb->unacked != NULL && pcb->rtime >= pcb->rto) {
+
+        /* Time for a retransmission. */
+        LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_slowtmr: rtime %u pcb->rto %u\n",
+          pcb->rtime, pcb->rto));
+
+        /* Double retransmission time-out unless we are trying to
+         * connect to somebody (i.e., we are in SYN_SENT). */
+        if (pcb->state != SYN_SENT) {
+          pcb->rto = ((pcb->sa >> 3) + pcb->sv) << tcp_backoff[pcb->nrtx];
+        }
+        /* Reduce congestion window and ssthresh. */
+        eff_wnd = LWIP_MIN(pcb->cwnd, pcb->snd_wnd);
+        pcb->ssthresh = eff_wnd >> 1;
+        if (pcb->ssthresh < pcb->mss) {
+          pcb->ssthresh = pcb->mss * 2;
+        }
+        pcb->cwnd = pcb->mss;
+        LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: cwnd %u ssthresh %u\n",
+                                pcb->cwnd, pcb->ssthresh));
+ 
+        /* The following needs to be called AFTER cwnd is set to one mss - STJ */
+        tcp_rexmit_rto(pcb);
+     }
+    }
+    /* Check if this PCB has stayed too long in FIN-WAIT-2 */
+    if (pcb->state == FIN_WAIT_2) {
+      if ((u32_t)(tcp_ticks - pcb->tmr) >
+        TCP_FIN_WAIT_TIMEOUT / TCP_SLOW_INTERVAL) {
+        ++pcb_remove;
+        LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in FIN-WAIT-2\n"));
+      }
+    }
+
+   /* Check if KEEPALIVE should be sent */
+   if((pcb->so_options & SOF_KEEPALIVE) && ((pcb->state == ESTABLISHED) || (pcb->state == CLOSE_WAIT))) {
+      if((u32_t)(tcp_ticks - pcb->tmr) > (pcb->keepalive + TCP_MAXIDLE) / TCP_SLOW_INTERVAL)  {
+         LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: KEEPALIVE timeout. Aborting connection to %u.%u.%u.%u.\n",
+                                 ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip),
+                                 ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip)));
+
+         tcp_abort(pcb);
+      }
+      else if((u32_t)(tcp_ticks - pcb->tmr) > (pcb->keepalive + pcb->keep_cnt * TCP_KEEPINTVL) / TCP_SLOW_INTERVAL) {
+         tcp_keepalive(pcb);
+         pcb->keep_cnt++;
+      }
+   }
+
+    /* If this PCB has queued out of sequence data, but has been
+       inactive for too long, will drop the data (it will eventually
+       be retransmitted). */
+#if TCP_QUEUE_OOSEQ    
+    if (pcb->ooseq != NULL &&
+       (u32_t)tcp_ticks - pcb->tmr >=
+       pcb->rto * (u32_t)TCP_OOSEQ_TIMEOUT) {
+      tcp_segs_free(pcb->ooseq);
+      pcb->ooseq = NULL;
+      LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: dropping OOSEQ queued data\n"));
+    }
+#endif /* TCP_QUEUE_OOSEQ */
+
+    /* Check if this PCB has stayed too long in SYN-RCVD */
+    if (pcb->state == SYN_RCVD) {
+      if ((u32_t)(tcp_ticks - pcb->tmr) >
+   TCP_SYN_RCVD_TIMEOUT / TCP_SLOW_INTERVAL) {
+        ++pcb_remove;
+        LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in SYN-RCVD\n"));
+      }
+    }
+
+
+    /* If the PCB should be removed, do it. */
+    if (pcb_remove) {
+      tcp_pcb_purge(pcb);      
+      /* Remove PCB from tcp_active_pcbs list. */
+      if (prev != NULL) {
+  LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_active_pcbs", pcb != tcp_active_pcbs);
+        prev->next = pcb->next;
+      } else {
+        /* This PCB was the first. */
+        LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_active_pcbs", tcp_active_pcbs == pcb);
+        tcp_active_pcbs = pcb->next;
+      }
+
+      TCP_EVENT_ERR(pcb->errf, pcb->callback_arg, ERR_ABRT);
+
+      pcb2 = pcb->next;
+      memp_free(MEMP_TCP_PCB, pcb);
+      pcb = pcb2;
+    } else {
+
+      /* We check if we should poll the connection. */
+      ++pcb->polltmr;
+      if (pcb->polltmr >= pcb->pollinterval) {
+        pcb->polltmr = 0;
+        LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: polling application\n"));
+        TCP_EVENT_POLL(pcb, err);
+        if (err == ERR_OK) {
+          tcp_output(pcb);
+        }
+      }
+      
+      prev = pcb;
+      pcb = pcb->next;
+    }
+  }
+
+  
+  /* Steps through all of the TIME-WAIT PCBs. */
+  prev = NULL;    
+  pcb = tcp_tw_pcbs;
+  while (pcb != NULL) {
+    LWIP_ASSERT("tcp_slowtmr: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT);
+    pcb_remove = 0;
+
+    /* Check if this PCB has stayed long enough in TIME-WAIT */
+    if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) {
+      ++pcb_remove;
+    }
+    
+
+
+    /* If the PCB should be removed, do it. */
+    if (pcb_remove) {
+      tcp_pcb_purge(pcb);      
+      /* Remove PCB from tcp_tw_pcbs list. */
+      if (prev != NULL) {
+  LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_tw_pcbs", pcb != tcp_tw_pcbs);
+        prev->next = pcb->next;
+      } else {
+        /* This PCB was the first. */
+        LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_tw_pcbs", tcp_tw_pcbs == pcb);
+        tcp_tw_pcbs = pcb->next;
+      }
+      pcb2 = pcb->next;
+      memp_free(MEMP_TCP_PCB, pcb);
+      pcb = pcb2;
+    } else {
+      prev = pcb;
+      pcb = pcb->next;
+    }
+  }
+}
+
+/**
+ * Is called every TCP_FAST_INTERVAL (250 ms) and sends delayed ACKs.
+ */
+void
+tcp_fasttmr(void)
+{
+  struct tcp_pcb *pcb;
+
+  /* send delayed ACKs */  
+  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+    if (pcb->flags & TF_ACK_DELAY) {
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_fasttmr: delayed ACK\n"));
+      tcp_ack_now(pcb);
+      pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW);
+    }
+  }
+}
+
+/**
+ * Deallocates a list of TCP segments (tcp_seg structures).
+ *
+ */
+u8_t
+tcp_segs_free(struct tcp_seg *seg)
+{
+  u8_t count = 0;
+  struct tcp_seg *next;
+  while (seg != NULL) {
+    next = seg->next;
+    count += tcp_seg_free(seg);
+    seg = next;
+  }
+  return count;
+}
+
+/**
+ * Frees a TCP segment.
+ *
+ */
+u8_t
+tcp_seg_free(struct tcp_seg *seg)
+{
+  u8_t count = 0;
+  
+  if (seg != NULL) {
+    if (seg->p != NULL) {
+      count = pbuf_free(seg->p);
+#if TCP_DEBUG
+      seg->p = NULL;
+#endif /* TCP_DEBUG */
+    }
+    memp_free(MEMP_TCP_SEG, seg);
+  }
+  return count;
+}
+
+/**
+ * Sets the priority of a connection.
+ *
+ */
+void
+tcp_setprio(struct tcp_pcb *pcb, u8_t prio)
+{
+  pcb->prio = prio;
+}
+#if TCP_QUEUE_OOSEQ
+
+/**
+ * Returns a copy of the given TCP segment.
+ *
+ */ 
+struct tcp_seg *
+tcp_seg_copy(struct tcp_seg *seg)
+{
+  struct tcp_seg *cseg;
+
+  cseg = memp_malloc(MEMP_TCP_SEG);
+  if (cseg == NULL) {
+    return NULL;
+  }
+  memcpy((char *)cseg, (const char *)seg, sizeof(struct tcp_seg)); 
+  pbuf_ref(cseg->p);
+  return cseg;
+}
+#endif
+
+#if LWIP_CALLBACK_API
+static err_t
+tcp_recv_null(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err)
+{
+  arg = arg;
+  if (p != NULL) {
+    pbuf_free(p);
+  } else if (err == ERR_OK) {
+    return tcp_close(pcb);
+  }
+  return ERR_OK;
+}
+#endif /* LWIP_CALLBACK_API */
+
+static void
+tcp_kill_prio(u8_t prio)
+{
+  struct tcp_pcb *pcb, *inactive;
+  u32_t inactivity;
+  u8_t mprio;
+
+
+  mprio = TCP_PRIO_MAX;
+  
+  /* We kill the oldest active connection that has lower priority than
+     prio. */
+  inactivity = 0;
+  inactive = NULL;
+  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+    if (pcb->prio <= prio &&
+       pcb->prio <= mprio &&
+       (u32_t)(tcp_ticks - pcb->tmr) >= inactivity) {
+      inactivity = tcp_ticks - pcb->tmr;
+      inactive = pcb;
+      mprio = pcb->prio;
+    }
+  }
+  if (inactive != NULL) {
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_prio: killing oldest PCB %p (%ld)\n",
+           (void *)inactive, inactivity));
+    tcp_abort(inactive);
+  }      
+}
+
+
+static void
+tcp_kill_timewait(void)
+{
+  struct tcp_pcb *pcb, *inactive;
+  u32_t inactivity;
+
+  inactivity = 0;
+  inactive = NULL;
+  for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
+    if ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity) {
+      inactivity = tcp_ticks - pcb->tmr;
+      inactive = pcb;
+    }
+  }
+  if (inactive != NULL) {
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_timewait: killing oldest TIME-WAIT PCB %p (%ld)\n",
+           (void *)inactive, inactivity));
+    tcp_abort(inactive);
+  }      
+}
+
+
+
+struct tcp_pcb *
+tcp_alloc(u8_t prio)
+{
+  struct tcp_pcb *pcb;
+  u32_t iss;
+  
+  pcb = memp_malloc(MEMP_TCP_PCB);
+  if (pcb == NULL) {
+    /* Try killing oldest connection in TIME-WAIT. */
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest TIME-WAIT connection\n"));
+    tcp_kill_timewait();
+    pcb = memp_malloc(MEMP_TCP_PCB);
+    if (pcb == NULL) {
+      tcp_kill_prio(prio);    
+      pcb = memp_malloc(MEMP_TCP_PCB);
+    }
+  }
+  if (pcb != NULL) {
+    memset(pcb, 0, sizeof(struct tcp_pcb));
+    pcb->prio = TCP_PRIO_NORMAL;
+    pcb->snd_buf = TCP_SND_BUF;
+    pcb->snd_queuelen = 0;
+    pcb->rcv_wnd = TCP_WND;
+    pcb->tos = 0;
+    pcb->ttl = TCP_TTL;
+    pcb->mss = TCP_MSS;
+    pcb->rto = 3000 / TCP_SLOW_INTERVAL;
+    pcb->sa = 0;
+    pcb->sv = 3000 / TCP_SLOW_INTERVAL;
+    pcb->rtime = 0;
+    pcb->cwnd = 1;
+    iss = tcp_next_iss();
+    pcb->snd_wl2 = iss;
+    pcb->snd_nxt = iss;
+    pcb->snd_max = iss;
+    pcb->lastack = iss;
+    pcb->snd_lbb = iss;   
+    pcb->tmr = tcp_ticks;
+
+    pcb->polltmr = 0;
+
+#if LWIP_CALLBACK_API
+    pcb->recv = tcp_recv_null;
+#endif /* LWIP_CALLBACK_API */  
+    
+    /* Init KEEPALIVE timer */
+    pcb->keepalive = TCP_KEEPDEFAULT;
+    pcb->keep_cnt = 0;
+  }
+  return pcb;
+}
+
+/**
+ * Creates a new TCP protocol control block but doesn't place it on
+ * any of the TCP PCB lists.
+ *
+ * @internal: Maybe there should be a idle TCP PCB list where these
+ * PCBs are put on. We can then implement port reservation using
+ * tcp_bind(). Currently, we lack this (BSD socket type of) feature.
+ */
+
+struct tcp_pcb *
+tcp_new(void)
+{
+  return tcp_alloc(TCP_PRIO_NORMAL);
+}
+
+/*
+ * tcp_arg():
+ *
+ * Used to specify the argument that should be passed callback
+ * functions.
+ *
+ */ 
+
+void
+tcp_arg(struct tcp_pcb *pcb, void *arg)
+{  
+  pcb->callback_arg = arg;
+}
+#if LWIP_CALLBACK_API
+
+/**
+ * Used to specify the function that should be called when a TCP
+ * connection receives data.
+ *
+ */ 
+void
+tcp_recv(struct tcp_pcb *pcb,
+   err_t (* recv)(void *arg, struct tcp_pcb *tpcb, struct pbuf *p, err_t err))
+{
+  pcb->recv = recv;
+}
+
+/**
+ * Used to specify the function that should be called when TCP data
+ * has been successfully delivered to the remote host.
+ *
+ */ 
+
+void
+tcp_sent(struct tcp_pcb *pcb,
+   err_t (* sent)(void *arg, struct tcp_pcb *tpcb, u16_t len))
+{
+  pcb->sent = sent;
+}
+
+/**
+ * Used to specify the function that should be called when a fatal error
+ * has occured on the connection.
+ *
+ */ 
+void
+tcp_err(struct tcp_pcb *pcb,
+   void (* errf)(void *arg, err_t err))
+{
+  pcb->errf = errf;
+}
+
+/**
+ * Used for specifying the function that should be called when a
+ * LISTENing connection has been connected to another host.
+ *
+ */ 
+void
+tcp_accept(struct tcp_pcb *pcb,
+     err_t (* accept)(void *arg, struct tcp_pcb *newpcb, err_t err))
+{
+  ((struct tcp_pcb_listen *)pcb)->accept = accept;
+}
+#endif /* LWIP_CALLBACK_API */
+
+
+/**
+ * Used to specify the function that should be called periodically
+ * from TCP. The interval is specified in terms of the TCP coarse
+ * timer interval, which is called twice a second.
+ *
+ */ 
+void
+tcp_poll(struct tcp_pcb *pcb,
+   err_t (* poll)(void *arg, struct tcp_pcb *tpcb), u8_t interval)
+{
+#if LWIP_CALLBACK_API
+  pcb->poll = poll;
+#endif /* LWIP_CALLBACK_API */  
+  pcb->pollinterval = interval;
+}
+
+/**
+ * Purges a TCP PCB. Removes any buffered data and frees the buffer memory.
+ *
+ */
+void
+tcp_pcb_purge(struct tcp_pcb *pcb)
+{
+  if (pcb->state != CLOSED &&
+     pcb->state != TIME_WAIT &&
+     pcb->state != LISTEN) {
+
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge\n"));
+    
+    if (pcb->unsent != NULL) {    
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: not all data sent\n"));
+    }
+    if (pcb->unacked != NULL) {    
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->unacked\n"));
+    }
+#if TCP_QUEUE_OOSEQ /* LW */
+    if (pcb->ooseq != NULL) {    
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->ooseq\n"));
+    }
+    
+    tcp_segs_free(pcb->ooseq);
+    pcb->ooseq = NULL;
+#endif /* TCP_QUEUE_OOSEQ */
+    tcp_segs_free(pcb->unsent);
+    tcp_segs_free(pcb->unacked);
+    pcb->unacked = pcb->unsent = NULL;
+  }
+}
+
+/**
+ * Purges the PCB and removes it from a PCB list. Any delayed ACKs are sent first.
+ *
+ */
+void
+tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb)
+{
+  TCP_RMV(pcblist, pcb);
+
+  tcp_pcb_purge(pcb);
+  
+  /* if there is an outstanding delayed ACKs, send it */
+  if (pcb->state != TIME_WAIT &&
+     pcb->state != LISTEN &&
+     pcb->flags & TF_ACK_DELAY) {
+    pcb->flags |= TF_ACK_NOW;
+    tcp_output(pcb);
+  }  
+  pcb->state = CLOSED;
+
+  LWIP_ASSERT("tcp_pcb_remove: tcp_pcbs_sane()", tcp_pcbs_sane());
+}
+
+/**
+ * Calculates a new initial sequence number for new connections.
+ *
+ */
+u32_t
+tcp_next_iss(void)
+{
+  static u32_t iss = 6510;
+  
+  iss += tcp_ticks;       /* XXX */
+  return iss;
+}
+
+#if TCP_DEBUG || TCP_INPUT_DEBUG || TCP_OUTPUT_DEBUG
+void
+tcp_debug_print(struct tcp_hdr *tcphdr)
+{
+  LWIP_DEBUGF(TCP_DEBUG, ("TCP header:\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("|    %5u      |    %5u      | (src port, dest port)\n",
+         ntohs(tcphdr->src), ntohs(tcphdr->dest)));
+  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("|           %010lu          | (seq no)\n",
+          ntohl(tcphdr->seqno)));
+  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("|           %010lu          | (ack no)\n",
+         ntohl(tcphdr->ackno)));
+  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("| %2u |   |%u%u%u%u%u%u|     %5u     | (hdrlen, flags (",
+       TCPH_HDRLEN(tcphdr),
+         TCPH_FLAGS(tcphdr) >> 5 & 1,
+         TCPH_FLAGS(tcphdr) >> 4 & 1,
+         TCPH_FLAGS(tcphdr) >> 3 & 1,
+         TCPH_FLAGS(tcphdr) >> 2 & 1,
+         TCPH_FLAGS(tcphdr) >> 1 & 1,
+         TCPH_FLAGS(tcphdr) & 1,
+         ntohs(tcphdr->wnd)));
+  tcp_debug_print_flags(TCPH_FLAGS(tcphdr));
+  LWIP_DEBUGF(TCP_DEBUG, ("), win)\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("|    0x%04x     |     %5u     | (chksum, urgp)\n",
+         ntohs(tcphdr->chksum), ntohs(tcphdr->urgp)));
+  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
+}
+
+void
+tcp_debug_print_state(enum tcp_state s)
+{
+  LWIP_DEBUGF(TCP_DEBUG, ("State: "));
+  switch (s) {
+  case CLOSED:
+    LWIP_DEBUGF(TCP_DEBUG, ("CLOSED\n"));
+    break;
+ case LISTEN:
+   LWIP_DEBUGF(TCP_DEBUG, ("LISTEN\n"));
+   break;
+  case SYN_SENT:
+    LWIP_DEBUGF(TCP_DEBUG, ("SYN_SENT\n"));
+    break;
+  case SYN_RCVD:
+    LWIP_DEBUGF(TCP_DEBUG, ("SYN_RCVD\n"));
+    break;
+  case ESTABLISHED:
+    LWIP_DEBUGF(TCP_DEBUG, ("ESTABLISHED\n"));
+    break;
+  case FIN_WAIT_1:
+    LWIP_DEBUGF(TCP_DEBUG, ("FIN_WAIT_1\n"));
+    break;
+  case FIN_WAIT_2:
+    LWIP_DEBUGF(TCP_DEBUG, ("FIN_WAIT_2\n"));
+    break;
+  case CLOSE_WAIT:
+    LWIP_DEBUGF(TCP_DEBUG, ("CLOSE_WAIT\n"));
+    break;
+  case CLOSING:
+    LWIP_DEBUGF(TCP_DEBUG, ("CLOSING\n"));
+    break;
+  case LAST_ACK:
+    LWIP_DEBUGF(TCP_DEBUG, ("LAST_ACK\n"));
+    break;
+  case TIME_WAIT:
+    LWIP_DEBUGF(TCP_DEBUG, ("TIME_WAIT\n"));
+   break;
+  }
+}
+
+void
+tcp_debug_print_flags(u8_t flags)
+{
+  if (flags & TCP_FIN) {
+    LWIP_DEBUGF(TCP_DEBUG, ("FIN "));
+  }
+  if (flags & TCP_SYN) {
+    LWIP_DEBUGF(TCP_DEBUG, ("SYN "));
+  }
+  if (flags & TCP_RST) {
+    LWIP_DEBUGF(TCP_DEBUG, ("RST "));
+  }
+  if (flags & TCP_PSH) {
+    LWIP_DEBUGF(TCP_DEBUG, ("PSH "));
+  }
+  if (flags & TCP_ACK) {
+    LWIP_DEBUGF(TCP_DEBUG, ("ACK "));
+  }
+  if (flags & TCP_URG) {
+    LWIP_DEBUGF(TCP_DEBUG, ("URG "));
+  }
+  if (flags & TCP_ECE) {
+    LWIP_DEBUGF(TCP_DEBUG, ("ECE "));
+  }
+  if (flags & TCP_CWR) {
+    LWIP_DEBUGF(TCP_DEBUG, ("CWR "));
+  }
+}
+
+void
+tcp_debug_print_pcbs(void)
+{
+  struct tcp_pcb *pcb;
+  LWIP_DEBUGF(TCP_DEBUG, ("Active PCB states:\n"));
+  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+    LWIP_DEBUGF(TCP_DEBUG, ("Local port %u, foreign port %u snd_nxt %lu rcv_nxt %lu ",
+                       pcb->local_port, pcb->remote_port,
+                       pcb->snd_nxt, pcb->rcv_nxt));
+    tcp_debug_print_state(pcb->state);
+  }    
+  LWIP_DEBUGF(TCP_DEBUG, ("Listen PCB states:\n"));
+  for(pcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs; pcb != NULL; pcb = pcb->next) {
+    LWIP_DEBUGF(TCP_DEBUG, ("Local port %u, foreign port %u snd_nxt %lu rcv_nxt %lu ",
+                       pcb->local_port, pcb->remote_port,
+                       pcb->snd_nxt, pcb->rcv_nxt));
+    tcp_debug_print_state(pcb->state);
+  }    
+  LWIP_DEBUGF(TCP_DEBUG, ("TIME-WAIT PCB states:\n"));
+  for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
+    LWIP_DEBUGF(TCP_DEBUG, ("Local port %u, foreign port %u snd_nxt %lu rcv_nxt %lu ",
+                       pcb->local_port, pcb->remote_port,
+                       pcb->snd_nxt, pcb->rcv_nxt));
+    tcp_debug_print_state(pcb->state);
+  }    
+}
+
+int
+tcp_pcbs_sane(void)
+{
+  struct tcp_pcb *pcb;
+  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+    LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != CLOSED", pcb->state != CLOSED);
+    LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != LISTEN", pcb->state != LISTEN);
+    LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT);
+  }
+  for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
+    LWIP_ASSERT("tcp_pcbs_sane: tw pcb->state == TIME-WAIT", pcb->state == TIME_WAIT);
+  }
+  return 1;
+}
+#endif /* TCP_DEBUG */
+#endif /* LWIP_TCP */
+
+
+
+
+
+
+
+
+
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/tcp_in.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/tcp_in.c
new file mode 100644
index 000000000..0571661f4
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/tcp_in.c
@@ -0,0 +1,1240 @@
+/**
+ * @file
+ *
+ * Transmission Control Protocol, incoming traffic
+ *
+ * The input processing functions of TCP.
+ *
+ * These functions are generally called in the order (ip_input() ->) tcp_input() ->
+ * tcp_process() -> tcp_receive() (-> application).
+ * 
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/def.h"
+#include "lwip/opt.h"
+
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+
+#include "lwip/inet.h"
+#include "lwip/tcp.h"
+
+#include "lwip/stats.h"
+
+#include "arch/perf.h"
+#if LWIP_TCP
+/* These variables are global to all functions involved in the input
+   processing of TCP segments. They are set by the tcp_input()
+   function. */
+static struct tcp_seg inseg;
+static struct tcp_hdr *tcphdr;
+static struct ip_hdr *iphdr;
+static u32_t seqno, ackno;
+static u8_t flags;
+static u16_t tcplen;
+
+static u8_t recv_flags;
+static struct pbuf *recv_data;
+
+struct tcp_pcb *tcp_input_pcb;
+
+/* Forward declarations. */
+static err_t tcp_process(struct tcp_pcb *pcb);
+static void tcp_receive(struct tcp_pcb *pcb);
+static void tcp_parseopt(struct tcp_pcb *pcb);
+
+static err_t tcp_listen_input(struct tcp_pcb_listen *pcb);
+static err_t tcp_timewait_input(struct tcp_pcb *pcb);
+
+
+/* tcp_input:
+ *
+ * The initial input processing of TCP. It verifies the TCP header, demultiplexes
+ * the segment between the PCBs and passes it on to tcp_process(), which implements
+ * the TCP finite state machine. This function is called by the IP layer (in
+ * ip_input()).
+ */
+
+void
+tcp_input(struct pbuf *p, struct netif *inp)
+{
+  struct tcp_pcb *pcb, *prev;
+  struct tcp_pcb_listen *lpcb;
+  u8_t hdrlen;
+  err_t err;
+
+#if SO_REUSE
+  struct tcp_pcb *pcb_temp;
+  int reuse = 0;
+  int reuse_port = 0;
+#endif /* SO_REUSE */
+
+  PERF_START;
+
+  TCP_STATS_INC(tcp.recv);
+
+  iphdr = p->payload;
+  tcphdr = (struct tcp_hdr *)((u8_t *)p->payload + IPH_HL(iphdr) * 4);
+
+#if TCP_INPUT_DEBUG
+  tcp_debug_print(tcphdr);
+#endif
+
+  /* remove header from payload */
+  if (pbuf_header(p, -((s16_t)(IPH_HL(iphdr) * 4))) || (p->tot_len < sizeof(struct tcp_hdr))) {
+    /* drop short packets */
+    LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: short packet (%u bytes) discarded\n", p->tot_len));
+    TCP_STATS_INC(tcp.lenerr);
+    TCP_STATS_INC(tcp.drop);
+    pbuf_free(p);
+    return;
+  }
+
+  /* Don't even process incoming broadcasts/multicasts. */
+  if (ip_addr_isbroadcast(&(iphdr->dest), inp) ||
+      ip_addr_ismulticast(&(iphdr->dest))) {
+    pbuf_free(p);
+    return;
+  }
+
+#if CHECKSUM_CHECK_TCP
+  /* Verify TCP checksum. */
+  if (inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src),
+      (struct ip_addr *)&(iphdr->dest),
+      IP_PROTO_TCP, p->tot_len) != 0) {
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packet discarded due to failing checksum 0x%04x\n",
+        inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src), (struct ip_addr *)&(iphdr->dest),
+      IP_PROTO_TCP, p->tot_len)));
+#if TCP_DEBUG
+    tcp_debug_print(tcphdr);
+#endif /* TCP_DEBUG */
+    TCP_STATS_INC(tcp.chkerr);
+    TCP_STATS_INC(tcp.drop);
+
+    pbuf_free(p);
+    return;
+  }
+#endif
+
+  /* Move the payload pointer in the pbuf so that it points to the
+     TCP data instead of the TCP header. */
+  hdrlen = TCPH_HDRLEN(tcphdr);
+  pbuf_header(p, -(hdrlen * 4));
+
+  /* Convert fields in TCP header to host byte order. */
+  tcphdr->src = ntohs(tcphdr->src);
+  tcphdr->dest = ntohs(tcphdr->dest);
+  seqno = tcphdr->seqno = ntohl(tcphdr->seqno);
+  ackno = tcphdr->ackno = ntohl(tcphdr->ackno);
+  tcphdr->wnd = ntohs(tcphdr->wnd);
+
+  flags = TCPH_FLAGS(tcphdr) & TCP_FLAGS;
+  tcplen = p->tot_len + ((flags & TCP_FIN || flags & TCP_SYN)? 1: 0);
+
+  /* Demultiplex an incoming segment. First, we check if it is destined
+     for an active connection. */
+  prev = NULL;
+
+#if SO_REUSE
+  pcb_temp = tcp_active_pcbs;
+  
+ again_1:
+  
+  /* Iterate through the TCP pcb list for a fully matching pcb */
+  for(pcb = pcb_temp; pcb != NULL; pcb = pcb->next) {
+#else  /* SO_REUSE */
+  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+#endif  /* SO_REUSE */
+    LWIP_ASSERT("tcp_input: active pcb->state != CLOSED", pcb->state != CLOSED);
+    LWIP_ASSERT("tcp_input: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT);
+    LWIP_ASSERT("tcp_input: active pcb->state != LISTEN", pcb->state != LISTEN);
+    if (pcb->remote_port == tcphdr->src &&
+       pcb->local_port == tcphdr->dest &&
+       ip_addr_cmp(&(pcb->remote_ip), &(iphdr->src)) &&
+       ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest))) {
+
+#if SO_REUSE
+      if(pcb->so_options & SOF_REUSEPORT) {
+        if(reuse) {
+          /* We processed one PCB already */
+          LWIP_DEBUGF(TCP_INPUT_DEBUG,("tcp_input: second or later PCB and SOF_REUSEPORT set.\n"));
+        } else {
+          /* First PCB with this address */
+          LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: first PCB and SOF_REUSEPORT set.\n"));
+          reuse = 1;
+        }
+        
+        reuse_port = 1; 
+        p->ref++;
+        
+        /* We want to search on next socket after receiving */
+        pcb_temp = pcb->next;
+        
+        LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: reference counter on PBUF set to %i\n", p->ref));
+      } else  {
+        if(reuse) {
+          /* We processed one PCB already */
+          LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: second or later PCB but SOF_REUSEPORT not set !\n"));
+        }
+      }
+#endif /* SO_REUSE */
+
+      /* Move this PCB to the front of the list so that subsequent
+   lookups will be faster (we exploit locality in TCP segment
+   arrivals). */
+      LWIP_ASSERT("tcp_input: pcb->next != pcb (before cache)", pcb->next != pcb);
+      if (prev != NULL) {
+  prev->next = pcb->next;
+  pcb->next = tcp_active_pcbs;
+  tcp_active_pcbs = pcb;
+      }
+      LWIP_ASSERT("tcp_input: pcb->next != pcb (after cache)", pcb->next != pcb);
+      break;
+    }
+    prev = pcb;
+  }
+
+  if (pcb == NULL) {
+    /* If it did not go to an active connection, we check the connections
+       in the TIME-WAIT state. */
+
+    for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
+      LWIP_ASSERT("tcp_input: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT);
+      if (pcb->remote_port == tcphdr->src &&
+   pcb->local_port == tcphdr->dest &&
+   ip_addr_cmp(&(pcb->remote_ip), &(iphdr->src)) &&
+         ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest))) {
+  /* We don't really care enough to move this PCB to the front
+     of the list since we are not very likely to receive that
+     many segments for connections in TIME-WAIT. */
+  LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packed for TIME_WAITing connection.\n"));
+  tcp_timewait_input(pcb);
+  pbuf_free(p);
+  return;
+      }
+    }
+
+  /* Finally, if we still did not get a match, we check all PCBs that
+     are LISTENing for incoming connections. */
+    prev = NULL;
+    for(lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
+      if ((ip_addr_isany(&(lpcb->local_ip)) ||
+    ip_addr_cmp(&(lpcb->local_ip), &(iphdr->dest))) &&
+   lpcb->local_port == tcphdr->dest) {
+  /* Move this PCB to the front of the list so that subsequent
+     lookups will be faster (we exploit locality in TCP segment
+     arrivals). */
+  if (prev != NULL) {
+    ((struct tcp_pcb_listen *)prev)->next = lpcb->next;
+          /* our successor is the remainder of the listening list */
+    lpcb->next = tcp_listen_pcbs.listen_pcbs;
+          /* put this listening pcb at the head of the listening list */
+    tcp_listen_pcbs.listen_pcbs = lpcb;
+  }
+
+  LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packed for LISTENing connection.\n"));
+  tcp_listen_input(lpcb);
+  pbuf_free(p);
+  return;
+      }
+      prev = (struct tcp_pcb *)lpcb;
+    }
+  }
+
+#if TCP_INPUT_DEBUG
+  LWIP_DEBUGF(TCP_INPUT_DEBUG, ("+-+-+-+-+-+-+-+-+-+-+-+-+-+- tcp_input: flags "));
+  tcp_debug_print_flags(TCPH_FLAGS(tcphdr));
+  LWIP_DEBUGF(TCP_INPUT_DEBUG, ("-+-+-+-+-+-+-+-+-+-+-+-+-+-+\n"));
+#endif /* TCP_INPUT_DEBUG */
+
+
+  if (pcb != NULL) {
+    /* The incoming segment belongs to a connection. */
+#if TCP_INPUT_DEBUG
+#if TCP_DEBUG
+    tcp_debug_print_state(pcb->state);
+#endif /* TCP_DEBUG */
+#endif /* TCP_INPUT_DEBUG */
+
+    /* Set up a tcp_seg structure. */
+    inseg.next = NULL;
+    inseg.len = p->tot_len;
+    inseg.dataptr = p->payload;
+    inseg.p = p;
+    inseg.tcphdr = tcphdr;
+
+    recv_data = NULL;
+    recv_flags = 0;
+
+    tcp_input_pcb = pcb;
+    err = tcp_process(pcb);
+    tcp_input_pcb = NULL;
+    /* A return value of ERR_ABRT means that tcp_abort() was called
+       and that the pcb has been freed. If so, we don't do anything. */
+    if (err != ERR_ABRT) {
+      if (recv_flags & TF_RESET) {
+  /* TF_RESET means that the connection was reset by the other
+     end. We then call the error callback to inform the
+     application that the connection is dead before we
+     deallocate the PCB. */
+  TCP_EVENT_ERR(pcb->errf, pcb->callback_arg, ERR_RST);
+  tcp_pcb_remove(&tcp_active_pcbs, pcb);
+  memp_free(MEMP_TCP_PCB, pcb);
+      } else if (recv_flags & TF_CLOSED) {
+  /* The connection has been closed and we will deallocate the
+     PCB. */
+  tcp_pcb_remove(&tcp_active_pcbs, pcb);
+  memp_free(MEMP_TCP_PCB, pcb);
+      } else {
+  err = ERR_OK;
+  /* If the application has registered a "sent" function to be
+     called when new send buffer space is available, we call it
+     now. */
+  if (pcb->acked > 0) {
+    TCP_EVENT_SENT(pcb, pcb->acked, err);
+  }
+
+  if (recv_data != NULL) {
+    /* Notify application that data has been received. */
+    TCP_EVENT_RECV(pcb, recv_data, ERR_OK, err);
+  }
+
+  /* If a FIN segment was received, we call the callback
+     function with a NULL buffer to indicate EOF. */
+  if (recv_flags & TF_GOT_FIN) {
+    TCP_EVENT_RECV(pcb, NULL, ERR_OK, err);
+  }
+  /* If there were no errors, we try to send something out. */
+  if (err == ERR_OK) {
+    tcp_output(pcb);
+  }
+      }
+    }
+
+
+    /* We deallocate the incoming pbuf. If it was buffered by the
+       application, the application should have called pbuf_ref() to
+       increase the reference counter in the pbuf. If so, the buffer
+       isn't actually deallocated by the call to pbuf_free(), only the
+       reference count is decreased. */
+    if (inseg.p != NULL) pbuf_free(inseg.p);
+#if TCP_INPUT_DEBUG
+#if TCP_DEBUG
+    tcp_debug_print_state(pcb->state);
+#endif /* TCP_DEBUG */
+#endif /* TCP_INPUT_DEBUG */
+#if SO_REUSE
+    /* First socket should receive now */
+    if(reuse_port) {
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: searching next PCB.\n"));
+      reuse_port = 0;
+      
+      /* We are searching connected sockets */
+      goto again_1;
+    }
+#endif /* SO_REUSE */
+
+  } else {
+#if SO_REUSE
+    if(reuse) {
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: freeing PBUF with reference counter set to %i\n", p->ref));
+      pbuf_free(p);
+      goto end;
+    }
+#endif /* SO_REUSE */
+    /* If no matching PCB was found, send a TCP RST (reset) to the
+       sender. */
+    LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_input: no PCB match found, resetting.\n"));
+    if (!(TCPH_FLAGS(tcphdr) & TCP_RST)) {
+      TCP_STATS_INC(tcp.proterr);
+      TCP_STATS_INC(tcp.drop);
+      tcp_rst(ackno, seqno + tcplen,
+        &(iphdr->dest), &(iphdr->src),
+        tcphdr->dest, tcphdr->src);
+    }
+    pbuf_free(p);
+  }
+#if SO_REUSE
+ end:
+#endif /* SO_REUSE */
+  LWIP_ASSERT("tcp_input: tcp_pcbs_sane()", tcp_pcbs_sane());
+  PERF_STOP("tcp_input");
+}
+
+/* tcp_listen_input():
+ *
+ * Called by tcp_input() when a segment arrives for a listening
+ * connection.
+ */
+
+static err_t
+tcp_listen_input(struct tcp_pcb_listen *pcb)
+{
+  struct tcp_pcb *npcb;
+  u32_t optdata;
+
+  /* In the LISTEN state, we check for incoming SYN segments,
+     creates a new PCB, and responds with a SYN|ACK. */
+  if (flags & TCP_ACK) {
+    /* For incoming segments with the ACK flag set, respond with a
+       RST. */
+    LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_listen_input: ACK in LISTEN, sending reset\n"));
+    tcp_rst(ackno + 1, seqno + tcplen,
+      &(iphdr->dest), &(iphdr->src),
+      tcphdr->dest, tcphdr->src);
+  } else if (flags & TCP_SYN) {
+    LWIP_DEBUGF(TCP_DEBUG, ("TCP connection request %u -> %u.\n", tcphdr->src, tcphdr->dest));
+    npcb = tcp_alloc(pcb->prio);
+    /* If a new PCB could not be created (probably due to lack of memory),
+       we don't do anything, but rely on the sender will retransmit the
+       SYN at a time when we have more memory available. */
+    if (npcb == NULL) {
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_listen_input: could not allocate PCB\n"));
+      TCP_STATS_INC(tcp.memerr);
+      return ERR_MEM;
+    }
+    /* Set up the new PCB. */
+    ip_addr_set(&(npcb->local_ip), &(iphdr->dest));
+    npcb->local_port = pcb->local_port;
+    ip_addr_set(&(npcb->remote_ip), &(iphdr->src));
+    npcb->remote_port = tcphdr->src;
+    npcb->state = SYN_RCVD;
+    npcb->rcv_nxt = seqno + 1;
+    npcb->snd_wnd = tcphdr->wnd;
+    npcb->ssthresh = npcb->snd_wnd;
+    npcb->snd_wl1 = seqno - 1;/* initialise to seqno-1 to force window update */
+    npcb->callback_arg = pcb->callback_arg;
+#if LWIP_CALLBACK_API
+    npcb->accept = pcb->accept;
+#endif /* LWIP_CALLBACK_API */
+    /* inherit socket options */
+    npcb->so_options = pcb->so_options & (SOF_DEBUG|SOF_DONTROUTE|SOF_KEEPALIVE|SOF_OOBINLINE|SOF_LINGER);
+    /* Register the new PCB so that we can begin receiving segments
+       for it. */
+    TCP_REG(&tcp_active_pcbs, npcb);
+
+    /* Parse any options in the SYN. */
+    tcp_parseopt(npcb);
+
+    /* Build an MSS option. */
+    optdata = htonl(((u32_t)2 << 24) |
+        ((u32_t)4 << 16) |
+        (((u32_t)npcb->mss / 256) << 8) |
+        (npcb->mss & 255));
+    /* Send a SYN|ACK together with the MSS option. */
+    tcp_enqueue(npcb, NULL, 0, TCP_SYN | TCP_ACK, 0, (u8_t *)&optdata, 4);
+    return tcp_output(npcb);
+  }
+  return ERR_OK;
+}
+
+/* tcp_timewait_input():
+ *
+ * Called by tcp_input() when a segment arrives for a connection in
+ * TIME_WAIT.
+ */
+
+static err_t
+tcp_timewait_input(struct tcp_pcb *pcb)
+{
+  if (TCP_SEQ_GT(seqno + tcplen, pcb->rcv_nxt)) {
+    pcb->rcv_nxt = seqno + tcplen;
+  }
+  if (tcplen > 0) {
+    tcp_ack_now(pcb);
+  }
+  return tcp_output(pcb);
+}
+
+/* tcp_process
+ *
+ * Implements the TCP state machine. Called by tcp_input. In some
+ * states tcp_receive() is called to receive data. The tcp_seg
+ * argument will be freed by the caller (tcp_input()) unless the
+ * recv_data pointer in the pcb is set.
+ */
+
+static err_t
+tcp_process(struct tcp_pcb *pcb)
+{
+  struct tcp_seg *rseg;
+  u8_t acceptable = 0;
+  err_t err;
+
+
+  err = ERR_OK;
+
+  /* Process incoming RST segments. */
+  if (flags & TCP_RST) {
+    /* First, determine if the reset is acceptable. */
+    if (pcb->state == SYN_SENT) {
+      if (ackno == pcb->snd_nxt) {
+        acceptable = 1;
+      }
+    } else {
+      /*if (TCP_SEQ_GEQ(seqno, pcb->rcv_nxt) &&
+          TCP_SEQ_LEQ(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) {
+      */
+      if(TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt+pcb->rcv_wnd)){
+        acceptable = 1;
+      }
+    }
+
+    if (acceptable) {
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: Connection RESET\n"));
+      LWIP_ASSERT("tcp_input: pcb->state != CLOSED", pcb->state != CLOSED);
+      recv_flags = TF_RESET;
+      pcb->flags &= ~TF_ACK_DELAY;
+      return ERR_RST;
+    } else {
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: unacceptable reset seqno %lu rcv_nxt %lu\n",
+       seqno, pcb->rcv_nxt));
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_process: unacceptable reset seqno %lu rcv_nxt %lu\n",
+       seqno, pcb->rcv_nxt));
+      return ERR_OK;
+    }
+  }
+
+  /* Update the PCB (in)activity timer. */
+  pcb->tmr = tcp_ticks;
+  pcb->keep_cnt = 0;
+
+  /* Do different things depending on the TCP state. */
+  switch (pcb->state) {
+  case SYN_SENT:
+    LWIP_DEBUGF(TCP_INPUT_DEBUG, ("SYN-SENT: ackno %lu pcb->snd_nxt %lu unacked %lu\n", ackno,
+     pcb->snd_nxt, ntohl(pcb->unacked->tcphdr->seqno)));
+    if ((flags & TCP_ACK) && (flags & TCP_SYN)
+        && ackno == ntohl(pcb->unacked->tcphdr->seqno) + 1) {
+      pcb->snd_buf ++;
+      pcb->rcv_nxt = seqno + 1;
+      pcb->lastack = ackno;
+      pcb->snd_wnd = tcphdr->wnd;
+      pcb->snd_wl1 = seqno - 1; /* initialise to seqno - 1 to force window update */
+      pcb->state = ESTABLISHED;
+      pcb->cwnd = pcb->mss;
+      --pcb->snd_queuelen;
+      LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_process: SYN-SENT --queuelen %u\n", (unsigned int)pcb->snd_queuelen));
+      rseg = pcb->unacked;
+      pcb->unacked = rseg->next;
+      tcp_seg_free(rseg);
+
+      /* Parse any options in the SYNACK. */
+      tcp_parseopt(pcb);
+
+      /* Call the user specified function to call when sucessfully
+       * connected. */
+      TCP_EVENT_CONNECTED(pcb, ERR_OK, err);
+      tcp_ack(pcb);
+    }
+    break;
+  case SYN_RCVD:
+    if (flags & TCP_ACK &&
+       !(flags & TCP_RST)) {
+      /*if (TCP_SEQ_LT(pcb->lastack, ackno) &&
+        TCP_SEQ_LEQ(ackno, pcb->snd_nxt)) { */
+      if(TCP_SEQ_BETWEEN(ackno, pcb->lastack+1, pcb->snd_nxt)){
+        pcb->state = ESTABLISHED;
+        LWIP_DEBUGF(TCP_DEBUG, ("TCP connection established %u -> %u.\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+#if LWIP_CALLBACK_API
+        LWIP_ASSERT("pcb->accept != NULL", pcb->accept != NULL);
+#endif
+        /* Call the accept function. */
+        TCP_EVENT_ACCEPT(pcb, ERR_OK, err);
+        if (err != ERR_OK) {
+          /* If the accept function returns with an error, we abort
+           * the connection. */
+          tcp_abort(pcb);
+          return ERR_ABRT;
+        }
+        /* If there was any data contained within this ACK,
+         * we'd better pass it on to the application as well. */
+        tcp_receive(pcb);
+        pcb->cwnd = pcb->mss;
+      }
+    }
+    break;
+  case CLOSE_WAIT:
+    /* FALLTHROUGH */
+  case ESTABLISHED:
+    tcp_receive(pcb);
+    if (flags & TCP_FIN) {
+      tcp_ack_now(pcb);
+      pcb->state = CLOSE_WAIT;
+    }
+    break;
+  case FIN_WAIT_1:
+    tcp_receive(pcb);
+    if (flags & TCP_FIN) {
+      if (flags & TCP_ACK && ackno == pcb->snd_nxt) {
+        LWIP_DEBUGF(TCP_DEBUG,
+         ("TCP connection closed %d -> %d.\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+  tcp_ack_now(pcb);
+  tcp_pcb_purge(pcb);
+  TCP_RMV(&tcp_active_pcbs, pcb);
+  pcb->state = TIME_WAIT;
+  TCP_REG(&tcp_tw_pcbs, pcb);
+      } else {
+  tcp_ack_now(pcb);
+  pcb->state = CLOSING;
+      }
+    } else if (flags & TCP_ACK && ackno == pcb->snd_nxt) {
+      pcb->state = FIN_WAIT_2;
+    }
+    break;
+  case FIN_WAIT_2:
+    tcp_receive(pcb);
+    if (flags & TCP_FIN) {
+      LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed %u -> %u.\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+      tcp_ack_now(pcb);
+      tcp_pcb_purge(pcb);
+      TCP_RMV(&tcp_active_pcbs, pcb);
+      pcb->state = TIME_WAIT;
+      TCP_REG(&tcp_tw_pcbs, pcb);
+    }
+    break;
+  case CLOSING:
+    tcp_receive(pcb);
+    if (flags & TCP_ACK && ackno == pcb->snd_nxt) {
+      LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed %u -> %u.\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+      tcp_ack_now(pcb);
+      tcp_pcb_purge(pcb);
+      TCP_RMV(&tcp_active_pcbs, pcb);
+      pcb->state = TIME_WAIT;
+      TCP_REG(&tcp_tw_pcbs, pcb);
+    }
+    break;
+  case LAST_ACK:
+    tcp_receive(pcb);
+    if (flags & TCP_ACK && ackno == pcb->snd_nxt) {
+      LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed %u -> %u.\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+      pcb->state = CLOSED;
+      recv_flags = TF_CLOSED;
+    }
+    break;
+  default:
+    break;
+  }
+
+  return ERR_OK;
+}
+
+/* tcp_receive:
+ *
+ * Called by tcp_process. Checks if the given segment is an ACK for outstanding
+ * data, and if so frees the memory of the buffered data. Next, is places the
+ * segment on any of the receive queues (pcb->recved or pcb->ooseq). If the segment
+ * is buffered, the pbuf is referenced by pbuf_ref so that it will not be freed until
+ * i it has been removed from the buffer.
+ *
+ * If the incoming segment constitutes an ACK for a segment that was used for RTT
+ * estimation, the RTT is estimated here as well.
+ */
+
+static void
+tcp_receive(struct tcp_pcb *pcb)
+{
+  struct tcp_seg *next;
+#if TCP_QUEUE_OOSEQ
+  struct tcp_seg *prev, *cseg;
+#endif
+  struct pbuf *p;
+  s32_t off;
+  int m;
+  u32_t right_wnd_edge;
+  u16_t new_tot_len;
+
+
+  if (flags & TCP_ACK) {
+    right_wnd_edge = pcb->snd_wnd + pcb->snd_wl1;
+
+    /* Update window. */
+    if (TCP_SEQ_LT(pcb->snd_wl1, seqno) ||
+       (pcb->snd_wl1 == seqno && TCP_SEQ_LT(pcb->snd_wl2, ackno)) ||
+       (pcb->snd_wl2 == ackno && tcphdr->wnd > pcb->snd_wnd)) {
+      pcb->snd_wnd = tcphdr->wnd;
+      pcb->snd_wl1 = seqno;
+      pcb->snd_wl2 = ackno;
+      LWIP_DEBUGF(TCP_WND_DEBUG, ("tcp_receive: window update %lu\n", pcb->snd_wnd));
+#if TCP_WND_DEBUG
+    } else {
+      if (pcb->snd_wnd != tcphdr->wnd) {
+        LWIP_DEBUGF(TCP_WND_DEBUG, ("tcp_receive: no window update lastack %lu snd_max %lu ackno %lu wl1 %lu seqno %lu wl2 %lu\n",
+                               pcb->lastack, pcb->snd_max, ackno, pcb->snd_wl1, seqno, pcb->snd_wl2));
+      }
+#endif /* TCP_WND_DEBUG */
+    }
+
+
+    if (pcb->lastack == ackno) {
+      pcb->acked = 0;
+
+      if (pcb->snd_wl1 + pcb->snd_wnd == right_wnd_edge){
+        ++pcb->dupacks;
+        if (pcb->dupacks >= 3 && pcb->unacked != NULL) {
+          if (!(pcb->flags & TF_INFR)) {
+            /* This is fast retransmit. Retransmit the first unacked segment. */
+            LWIP_DEBUGF(TCP_FR_DEBUG, ("tcp_receive: dupacks %u (%lu), fast retransmit %lu\n",
+                                       (unsigned int)pcb->dupacks, pcb->lastack,
+                                       ntohl(pcb->unacked->tcphdr->seqno)));
+            tcp_rexmit(pcb);
+            /* Set ssthresh to max (FlightSize / 2, 2*SMSS) */
+            /*pcb->ssthresh = LWIP_MAX((pcb->snd_max -
+                                      pcb->lastack) / 2,
+                                      2 * pcb->mss);*/
+            /* Set ssthresh to half of the minimum of the currenct cwnd and the advertised window */
+            if(pcb->cwnd > pcb->snd_wnd)
+              pcb->ssthresh = pcb->snd_wnd / 2;
+            else
+              pcb->ssthresh = pcb->cwnd / 2;
+
+            pcb->cwnd = pcb->ssthresh + 3 * pcb->mss;
+            pcb->flags |= TF_INFR;
+          } else {
+            /* Inflate the congestion window, but not if it means that
+               the value overflows. */
+            if ((u16_t)(pcb->cwnd + pcb->mss) > pcb->cwnd) {
+              pcb->cwnd += pcb->mss;
+            }
+          }
+        }
+      } else {
+        LWIP_DEBUGF(TCP_FR_DEBUG, ("tcp_receive: dupack averted %lu %lu\n",
+                                   pcb->snd_wl1 + pcb->snd_wnd, right_wnd_edge));
+      }
+    } else
+      /*if (TCP_SEQ_LT(pcb->lastack, ackno) &&
+        TCP_SEQ_LEQ(ackno, pcb->snd_max)) { */
+      if(TCP_SEQ_BETWEEN(ackno, pcb->lastack+1, pcb->snd_max)){
+      /* We come here when the ACK acknowledges new data. */
+      
+      /* Reset the "IN Fast Retransmit" flag, since we are no longer
+         in fast retransmit. Also reset the congestion window to the
+         slow start threshold. */
+      if (pcb->flags & TF_INFR) {
+        pcb->flags &= ~TF_INFR;
+        pcb->cwnd = pcb->ssthresh;
+      }
+
+      /* Reset the number of retransmissions. */
+      pcb->nrtx = 0;
+
+      /* Reset the retransmission time-out. */
+      pcb->rto = (pcb->sa >> 3) + pcb->sv;
+
+      /* Update the send buffer space. */
+      pcb->acked = ackno - pcb->lastack;
+      pcb->snd_buf += pcb->acked;
+
+      /* Reset the fast retransmit variables. */
+      pcb->dupacks = 0;
+      pcb->lastack = ackno;
+
+      /* Update the congestion control variables (cwnd and
+         ssthresh). */
+      if (pcb->state >= ESTABLISHED) {
+        if (pcb->cwnd < pcb->ssthresh) {
+          if ((u16_t)(pcb->cwnd + pcb->mss) > pcb->cwnd) {
+            pcb->cwnd += pcb->mss;
+          }
+          LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: slow start cwnd %u\n", pcb->cwnd));
+        } else {
+          u16_t new_cwnd = (pcb->cwnd + pcb->mss * pcb->mss / pcb->cwnd);
+          if (new_cwnd > pcb->cwnd) {
+            pcb->cwnd = new_cwnd;
+          }
+          LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: congestion avoidance cwnd %u\n", pcb->cwnd));
+        }
+      }
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: ACK for %lu, unacked->seqno %lu:%lu\n",
+                                    ackno,
+                                    pcb->unacked != NULL?
+                                    ntohl(pcb->unacked->tcphdr->seqno): 0,
+                                    pcb->unacked != NULL?
+                                    ntohl(pcb->unacked->tcphdr->seqno) + TCP_TCPLEN(pcb->unacked): 0));
+
+      /* Remove segment from the unacknowledged list if the incoming
+         ACK acknowlegdes them. */
+      while (pcb->unacked != NULL &&
+             TCP_SEQ_LEQ(ntohl(pcb->unacked->tcphdr->seqno) +
+                         TCP_TCPLEN(pcb->unacked), ackno)) {
+        LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %lu:%lu from pcb->unacked\n",
+                                      ntohl(pcb->unacked->tcphdr->seqno),
+                                      ntohl(pcb->unacked->tcphdr->seqno) +
+                                      TCP_TCPLEN(pcb->unacked)));
+
+        next = pcb->unacked;
+        pcb->unacked = pcb->unacked->next;
+
+        LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %u ... ", (unsigned int)pcb->snd_queuelen));
+        pcb->snd_queuelen -= pbuf_clen(next->p);
+        tcp_seg_free(next);
+
+        LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%u (after freeing unacked)\n", (unsigned int)pcb->snd_queuelen));
+        if (pcb->snd_queuelen != 0) {
+          LWIP_ASSERT("tcp_receive: valid queue length", pcb->unacked != NULL ||
+                      pcb->unsent != NULL);
+        }
+      }
+      pcb->polltmr = 0;
+    }
+
+    /* We go through the ->unsent list to see if any of the segments
+       on the list are acknowledged by the ACK. This may seem
+       strange since an "unsent" segment shouldn't be acked. The
+       rationale is that lwIP puts all outstanding segments on the
+       ->unsent list after a retransmission, so these segments may
+       in fact have been sent once. */
+    while (pcb->unsent != NULL &&
+           /*TCP_SEQ_LEQ(ntohl(pcb->unsent->tcphdr->seqno) + TCP_TCPLEN(pcb->unsent), ackno) &&
+             TCP_SEQ_LEQ(ackno, pcb->snd_max)*/
+           TCP_SEQ_BETWEEN(ackno, ntohl(pcb->unsent->tcphdr->seqno) + TCP_TCPLEN(pcb->unsent), pcb->snd_max)
+           ) {
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %lu:%lu from pcb->unsent\n",
+                                    ntohl(pcb->unsent->tcphdr->seqno), ntohl(pcb->unsent->tcphdr->seqno) +
+                                    TCP_TCPLEN(pcb->unsent)));
+
+      next = pcb->unsent;
+      pcb->unsent = pcb->unsent->next;
+      LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %u ... ", (unsigned int)pcb->snd_queuelen));
+      pcb->snd_queuelen -= pbuf_clen(next->p);
+      tcp_seg_free(next);
+      LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%u (after freeing unsent)\n", (unsigned int)pcb->snd_queuelen));
+      if (pcb->snd_queuelen != 0) {
+        LWIP_ASSERT("tcp_receive: valid queue length",
+          pcb->unacked != NULL || pcb->unsent != NULL);
+      }
+
+      if (pcb->unsent != NULL) {
+        pcb->snd_nxt = htonl(pcb->unsent->tcphdr->seqno);
+      }
+    }
+    /* End of ACK for new data processing. */
+
+    LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: pcb->rttest %u rtseq %lu ackno %lu\n",
+                                pcb->rttest, pcb->rtseq, ackno));
+
+    /* RTT estimation calculations. This is done by checking if the
+       incoming segment acknowledges the segment we use to take a
+       round-trip time measurement. */
+    if (pcb->rttest && TCP_SEQ_LT(pcb->rtseq, ackno)) {
+      m = tcp_ticks - pcb->rttest;
+
+      LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: experienced rtt %u ticks (%u msec).\n",
+                                  m, m * TCP_SLOW_INTERVAL));
+
+      /* This is taken directly from VJs original code in his paper */
+      m = m - (pcb->sa >> 3);
+      pcb->sa += m;
+      if (m < 0) {
+        m = -m;
+      }
+      m = m - (pcb->sv >> 2);
+      pcb->sv += m;
+      pcb->rto = (pcb->sa >> 3) + pcb->sv;
+
+      LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: RTO %u (%u miliseconds)\n",
+                                  pcb->rto, pcb->rto * TCP_SLOW_INTERVAL));
+
+      pcb->rttest = 0;
+    }
+  }
+
+  /* If the incoming segment contains data, we must process it
+     further. */
+  if (tcplen > 0) {
+    /* This code basically does three things:
+
+    +) If the incoming segment contains data that is the next
+    in-sequence data, this data is passed to the application. This
+    might involve trimming the first edge of the data. The rcv_nxt
+    variable and the advertised window are adjusted.
+
+    +) If the incoming segment has data that is above the next
+    sequence number expected (->rcv_nxt), the segment is placed on
+    the ->ooseq queue. This is done by finding the appropriate
+    place in the ->ooseq queue (which is ordered by sequence
+    number) and trim the segment in both ends if needed. An
+    immediate ACK is sent to indicate that we received an
+    out-of-sequence segment.
+
+    +) Finally, we check if the first segment on the ->ooseq queue
+    now is in sequence (i.e., if rcv_nxt >= ooseq->seqno). If
+    rcv_nxt > ooseq->seqno, we must trim the first edge of the
+    segment on ->ooseq before we adjust rcv_nxt. The data in the
+    segments that are now on sequence are chained onto the
+    incoming segment so that we only need to call the application
+    once.
+    */
+
+    /* First, we check if we must trim the first edge. We have to do
+       this if the sequence number of the incoming segment is less
+       than rcv_nxt, and the sequence number plus the length of the
+       segment is larger than rcv_nxt. */
+    /*    if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)){
+          if (TCP_SEQ_LT(pcb->rcv_nxt, seqno + tcplen)) {*/
+    if(TCP_SEQ_BETWEEN(pcb->rcv_nxt, seqno+1, seqno+tcplen-1)){
+      /* Trimming the first edge is done by pushing the payload
+         pointer in the pbuf downwards. This is somewhat tricky since
+         we do not want to discard the full contents of the pbuf up to
+         the new starting point of the data since we have to keep the
+         TCP header which is present in the first pbuf in the chain.
+         
+         What is done is really quite a nasty hack: the first pbuf in
+         the pbuf chain is pointed to by inseg.p. Since we need to be
+         able to deallocate the whole pbuf, we cannot change this
+         inseg.p pointer to point to any of the later pbufs in the
+         chain. Instead, we point the ->payload pointer in the first
+         pbuf to data in one of the later pbufs. We also set the
+         inseg.data pointer to point to the right place. This way, the
+         ->p pointer will still point to the first pbuf, but the
+         ->p->payload pointer will point to data in another pbuf.
+         
+         After we are done with adjusting the pbuf pointers we must
+         adjust the ->data pointer in the seg and the segment
+         length.*/
+      
+      off = pcb->rcv_nxt - seqno;
+      p = inseg.p;
+      if (inseg.p->len < off) {
+        new_tot_len = inseg.p->tot_len - off;
+        while (p->len < off) {
+          off -= p->len;
+          /* KJM following line changed (with addition of new_tot_len var)
+             to fix bug #9076
+             inseg.p->tot_len -= p->len; */
+          p->tot_len = new_tot_len;
+          p->len = 0;
+          p = p->next;
+        }
+        pbuf_header(p, -off);
+      } else {
+        pbuf_header(inseg.p, -off);
+      }
+      /* KJM following line changed to use p->payload rather than inseg->p->payload
+         to fix bug #9076 */
+      inseg.dataptr = p->payload;
+      inseg.len -= pcb->rcv_nxt - seqno;
+      inseg.tcphdr->seqno = seqno = pcb->rcv_nxt;
+    }
+    else{
+      if(TCP_SEQ_LT(seqno, pcb->rcv_nxt)){
+        /* the whole segment is < rcv_nxt */
+        /* must be a duplicate of a packet that has already been correctly handled */
+        
+        LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: duplicate seqno %lu\n", seqno));
+        tcp_ack_now(pcb);
+      }
+    }
+
+    /* The sequence number must be within the window (above rcv_nxt
+       and below rcv_nxt + rcv_wnd) in order to be further
+       processed. */
+    /*if (TCP_SEQ_GEQ(seqno, pcb->rcv_nxt) &&
+      TCP_SEQ_LT(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) {*/
+    if(TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd - 1)){
+      if (pcb->rcv_nxt == seqno) {
+        /* The incoming segment is the next in sequence. We check if
+           we have to trim the end of the segment and update rcv_nxt
+           and pass the data to the application. */
+#if TCP_QUEUE_OOSEQ
+        if (pcb->ooseq != NULL &&
+            TCP_SEQ_LEQ(pcb->ooseq->tcphdr->seqno, seqno + inseg.len)) {
+          /* We have to trim the second edge of the incoming
+             segment. */
+          inseg.len = pcb->ooseq->tcphdr->seqno - seqno;
+          pbuf_realloc(inseg.p, inseg.len);
+        }
+#endif /* TCP_QUEUE_OOSEQ */
+
+        tcplen = TCP_TCPLEN(&inseg);
+
+        pcb->rcv_nxt += tcplen;
+
+        /* Update the receiver's (our) window. */
+        if (pcb->rcv_wnd < tcplen) {
+          pcb->rcv_wnd = 0;
+        } else {
+          pcb->rcv_wnd -= tcplen;
+        }
+
+        /* If there is data in the segment, we make preparations to
+           pass this up to the application. The ->recv_data variable
+           is used for holding the pbuf that goes to the
+           application. The code for reassembling out-of-sequence data
+           chains its data on this pbuf as well.
+
+           If the segment was a FIN, we set the TF_GOT_FIN flag that will
+           be used to indicate to the application that the remote side has
+           closed its end of the connection. */
+        if (inseg.p->tot_len > 0) {
+          recv_data = inseg.p;
+          /* Since this pbuf now is the responsibility of the
+             application, we delete our reference to it so that we won't
+             (mistakingly) deallocate it. */
+          inseg.p = NULL;
+        }
+        if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) {
+          LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: received FIN.\n"));
+          recv_flags = TF_GOT_FIN;
+        }
+
+#if TCP_QUEUE_OOSEQ
+        /* We now check if we have segments on the ->ooseq queue that
+           is now in sequence. */
+        while (pcb->ooseq != NULL &&
+               pcb->ooseq->tcphdr->seqno == pcb->rcv_nxt) {
+
+          cseg = pcb->ooseq;
+          seqno = pcb->ooseq->tcphdr->seqno;
+
+          pcb->rcv_nxt += TCP_TCPLEN(cseg);
+          if (pcb->rcv_wnd < TCP_TCPLEN(cseg)) {
+            pcb->rcv_wnd = 0;
+          } else {
+            pcb->rcv_wnd -= TCP_TCPLEN(cseg);
+          }
+          if (cseg->p->tot_len > 0) {
+            /* Chain this pbuf onto the pbuf that we will pass to
+               the application. */
+            if (recv_data) {
+              pbuf_cat(recv_data, cseg->p);
+            } else {
+              recv_data = cseg->p;
+            }
+            cseg->p = NULL;
+          }
+          if (TCPH_FLAGS(cseg->tcphdr) & TCP_FIN) {
+            LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: dequeued FIN.\n"));
+            recv_flags = TF_GOT_FIN;
+          }
+
+
+          pcb->ooseq = cseg->next;
+          tcp_seg_free(cseg);
+        }
+#endif /* TCP_QUEUE_OOSEQ */
+
+
+        /* Acknowledge the segment(s). */
+        tcp_ack(pcb);
+
+      } else {
+        /* We get here if the incoming segment is out-of-sequence. */
+        tcp_ack_now(pcb);
+#if TCP_QUEUE_OOSEQ
+        /* We queue the segment on the ->ooseq queue. */
+        if (pcb->ooseq == NULL) {
+          pcb->ooseq = tcp_seg_copy(&inseg);
+        } else {
+          /* If the queue is not empty, we walk through the queue and
+             try to find a place where the sequence number of the
+             incoming segment is between the sequence numbers of the
+             previous and the next segment on the ->ooseq queue. That is
+             the place where we put the incoming segment. If needed, we
+             trim the second edges of the previous and the incoming
+             segment so that it will fit into the sequence.
+
+             If the incoming segment has the same sequence number as a
+             segment on the ->ooseq queue, we discard the segment that
+             contains less data. */
+
+          prev = NULL;
+          for(next = pcb->ooseq; next != NULL; next = next->next) {
+            if (seqno == next->tcphdr->seqno) {
+              /* The sequence number of the incoming segment is the
+                 same as the sequence number of the segment on
+                 ->ooseq. We check the lengths to see which one to
+                 discard. */
+              if (inseg.len > next->len) {
+                /* The incoming segment is larger than the old
+                   segment. We replace the old segment with the new
+                   one. */
+                cseg = tcp_seg_copy(&inseg);
+                if (cseg != NULL) {
+                  cseg->next = next->next;
+                  if (prev != NULL) {
+                    prev->next = cseg;
+                  } else {
+                    pcb->ooseq = cseg;
+                  }
+                }
+                break;
+              } else {
+                /* Either the lenghts are the same or the incoming
+                   segment was smaller than the old one; in either
+                   case, we ditch the incoming segment. */
+                break;
+              }
+            } else {
+              if (prev == NULL) {
+                if (TCP_SEQ_LT(seqno, next->tcphdr->seqno)) {
+                  /* The sequence number of the incoming segment is lower
+                     than the sequence number of the first segment on the
+                     queue. We put the incoming segment first on the
+                     queue. */
+
+                  if (TCP_SEQ_GT(seqno + inseg.len, next->tcphdr->seqno)) {
+                    /* We need to trim the incoming segment. */
+                    inseg.len = next->tcphdr->seqno - seqno;
+                    pbuf_realloc(inseg.p, inseg.len);
+                  }
+                  cseg = tcp_seg_copy(&inseg);
+                  if (cseg != NULL) {
+                    cseg->next = next;
+                    pcb->ooseq = cseg;
+                  }
+                  break;
+                }
+              } else 
+                /*if (TCP_SEQ_LT(prev->tcphdr->seqno, seqno) &&
+                  TCP_SEQ_LT(seqno, next->tcphdr->seqno)) {*/
+                if(TCP_SEQ_BETWEEN(seqno, prev->tcphdr->seqno+1, next->tcphdr->seqno-1)){
+                /* The sequence number of the incoming segment is in
+                   between the sequence numbers of the previous and
+                   the next segment on ->ooseq. We trim and insert the
+                   incoming segment and trim the previous segment, if
+                   needed. */
+                if (TCP_SEQ_GT(seqno + inseg.len, next->tcphdr->seqno)) {
+                  /* We need to trim the incoming segment. */
+                  inseg.len = next->tcphdr->seqno - seqno;
+                  pbuf_realloc(inseg.p, inseg.len);
+                }
+
+                cseg = tcp_seg_copy(&inseg);
+                if (cseg != NULL) {
+                  cseg->next = next;
+                  prev->next = cseg;
+                  if (TCP_SEQ_GT(prev->tcphdr->seqno + prev->len, seqno)) {
+                    /* We need to trim the prev segment. */
+                    prev->len = seqno - prev->tcphdr->seqno;
+                    pbuf_realloc(prev->p, prev->len);
+                  }
+                }
+                break;
+              }
+              /* If the "next" segment is the last segment on the
+                 ooseq queue, we add the incoming segment to the end
+                 of the list. */
+              if (next->next == NULL &&
+                  TCP_SEQ_GT(seqno, next->tcphdr->seqno)) {
+                next->next = tcp_seg_copy(&inseg);
+                if (next->next != NULL) {
+                  if (TCP_SEQ_GT(next->tcphdr->seqno + next->len, seqno)) {
+                    /* We need to trim the last segment. */
+                    next->len = seqno - next->tcphdr->seqno;
+                    pbuf_realloc(next->p, next->len);
+                  }
+                }
+                break;
+              }
+            }
+            prev = next;
+          }
+        }
+#endif /* TCP_QUEUE_OOSEQ */
+
+      }
+    } else {
+      /*if (TCP_SEQ_GT(pcb->rcv_nxt, seqno) ||
+        TCP_SEQ_GEQ(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) {*/
+      if(!TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd-1)){
+        tcp_ack_now(pcb);
+      }
+    }
+  } else {
+    /* Segments with length 0 is taken care of here. Segments that
+       fall out of the window are ACKed. */
+    /*if (TCP_SEQ_GT(pcb->rcv_nxt, seqno) ||
+      TCP_SEQ_GEQ(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) {*/
+    if(!TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd-1)){
+      tcp_ack_now(pcb);
+    }
+  }
+}
+
+/*
+ * tcp_parseopt:
+ *
+ * Parses the options contained in the incoming segment. (Code taken
+ * from uIP with only small changes.)
+ *
+ */
+
+static void
+tcp_parseopt(struct tcp_pcb *pcb)
+{
+  u8_t c;
+  u8_t *opts, opt;
+  u16_t mss;
+
+  opts = (u8_t *)tcphdr + TCP_HLEN;
+
+  /* Parse the TCP MSS option, if present. */
+  if(TCPH_HDRLEN(tcphdr) > 0x5) {
+    for(c = 0; c < (TCPH_HDRLEN(tcphdr) - 5) << 2 ;) {
+      opt = opts[c];
+      if (opt == 0x00) {
+        /* End of options. */
+  break;
+      } else if (opt == 0x01) {
+        ++c;
+        /* NOP option. */
+      } else if (opt == 0x02 &&
+        opts[c + 1] == 0x04) {
+        /* An MSS option with the right option length. */
+        mss = (opts[c + 2] << 8) | opts[c + 3];
+        pcb->mss = mss > TCP_MSS? TCP_MSS: mss;
+
+        /* And we are done processing options. */
+        break;
+      } else {
+  if (opts[c + 1] == 0) {
+          /* If the length field is zero, the options are malformed
+             and we don't process them further. */
+          break;
+        }
+        /* All other options have a length field, so that we easily
+           can skip past them. */
+        c += opts[c + 1];
+      }
+    }
+  }
+}
+#endif /* LWIP_TCP */
+
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/tcp_out.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/tcp_out.c
new file mode 100644
index 000000000..a2ecb2faa
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/tcp_out.c
@@ -0,0 +1,724 @@
+/**
+ * @file
+ *
+ * Transmission Control Protocol, outgoing traffic
+ *
+ * The output functions of TCP.
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/def.h"
+#include "lwip/opt.h"
+
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+#include "lwip/sys.h"
+
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+
+#include "lwip/inet.h"
+#include "lwip/tcp.h"
+
+#include "lwip/stats.h"
+
+#include 
+
+#if LWIP_TCP
+
+/* Forward declarations.*/
+static void tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb);
+
+err_t
+tcp_send_ctrl(struct tcp_pcb *pcb, u8_t flags)
+{
+  /* no data, no length, flags, copy=1, no optdata, no optdatalen */
+  return tcp_enqueue(pcb, NULL, 0, flags, 1, NULL, 0);
+}
+
+/**
+ * Write data for sending (but does not send it immediately).
+ *
+ * It waits in the expectation of more data being sent soon (as
+ * it can send them more efficiently by combining them together).
+ * To prompt the system to send data now, call tcp_output() after
+ * calling tcp_write().
+ * 
+ * @arg pcb Protocol control block of the TCP connection to enqueue data for. 
+ * 
+ * @see tcp_write()
+ */
+
+err_t
+tcp_write(struct tcp_pcb *pcb, const void *arg, u16_t len, u8_t copy)
+{
+  LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_write(pcb=%p, arg=%p, len=%u, copy=%d)\n", (void *)pcb,
+    arg, len, (unsigned int)copy));
+  /* connection is in valid state for data transmission? */
+  if (pcb->state == ESTABLISHED ||
+     pcb->state == CLOSE_WAIT ||
+     pcb->state == SYN_SENT ||
+     pcb->state == SYN_RCVD) {
+    if (len > 0) {
+      return tcp_enqueue(pcb, (void *)arg, len, 0, copy, NULL, 0);
+    }
+    return ERR_OK;
+  } else {
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | DBG_STATE | 3, ("tcp_write() called in invalid state\n"));
+    return ERR_CONN;
+  }
+}
+
+/**
+ * Enqueue either data or TCP options (but not both) for tranmission
+ * 
+ * 
+ * 
+ * @arg pcb Protocol control block for the TCP connection to enqueue data for.
+ * @arg arg Pointer to the data to be enqueued for sending.
+ * @arg len Data length in bytes
+ * @arg flags
+ * @arg copy 1 if data must be copied, 0 if data is non-volatile and can be
+ * referenced.
+ * @arg optdata
+ * @arg optlen
+ */
+err_t
+tcp_enqueue(struct tcp_pcb *pcb, void *arg, u16_t len,
+  u8_t flags, u8_t copy,
+  u8_t *optdata, u8_t optlen)
+{
+  struct pbuf *p;
+  struct tcp_seg *seg, *useg, *queue=NULL;
+  u32_t left, seqno;
+  u16_t seglen;
+  void *ptr;
+  u8_t queuelen;
+
+  LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_enqueue(pcb=%p, arg=%p, len=%u, flags=%x, copy=%u)\n",
+    (void *)pcb, arg, len, (unsigned int)flags, (unsigned int)copy));
+  LWIP_ASSERT("tcp_enqueue: len == 0 || optlen == 0 (programmer violates API)",
+      len == 0 || optlen == 0);
+  LWIP_ASSERT("tcp_enqueue: arg == NULL || optdata == NULL (programmer violates API)",
+      arg == NULL || optdata == NULL);
+  /* fail on too much data */
+  if (len > pcb->snd_buf) {
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 3, ("tcp_enqueue: too much data (len=%u > snd_buf=%u)\n", len, pcb->snd_buf));
+    return ERR_MEM;
+  }
+  left = len;
+  ptr = arg;
+
+  /* seqno will be the sequence number of the first segment enqueued
+   * by the call to this function. */
+  seqno = pcb->snd_lbb;
+
+  LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue: queuelen: %u\n", (unsigned int)pcb->snd_queuelen));
+
+  /* If total number of pbufs on the unsent/unacked queues exceeds the
+   * configured maximum, return an error */
+  queuelen = pcb->snd_queuelen;
+  if (queuelen >= TCP_SND_QUEUELEN) {
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 3, ("tcp_enqueue: too long queue %u (max %u)\n", queuelen, TCP_SND_QUEUELEN));
+    goto memerr;
+  }
+  if (queuelen != 0) {
+    LWIP_ASSERT("tcp_enqueue: pbufs on queue => at least one queue non-empty",
+      pcb->unacked != NULL || pcb->unsent != NULL);
+  } else {
+    LWIP_ASSERT("tcp_enqueue: no pbufs on queue => both queues empty",
+      pcb->unacked == NULL && pcb->unsent == NULL);
+  }
+
+  /* First, break up the data into segments and tuck them together in
+   * the local "queue" variable. */
+  useg = NULL;
+  queue = NULL;
+  seg = NULL;
+  seglen = 0;
+  while (queue == NULL || left > 0) {
+
+    /* The segment length should be the MSS if the data to be enqueued
+     * is larger than the MSS. */
+    seglen = left > pcb->mss? pcb->mss: left;
+
+    /* Allocate memory for tcp_seg, and fill in fields. */
+    seg = memp_malloc(MEMP_TCP_SEG);
+    if (seg == NULL) {
+      LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: could not allocate memory for tcp_seg\n"));
+      goto memerr;
+    }
+    seg->next = NULL;
+    seg->p = NULL;
+
+    /* first segment of to-be-queued data? */
+    if (queue == NULL) {
+      queue = seg;
+    }
+    /* subsequent segments of to-be-queued data */
+    else {
+      /* Attach the segment to the end of the queued segments */
+      LWIP_ASSERT("useg != NULL", useg != NULL);
+      useg->next = seg;
+    }
+    /* remember last segment of to-be-queued data for next iteration */
+    useg = seg;
+
+    /* If copy is set, memory should be allocated
+     * and data copied into pbuf, otherwise data comes from
+     * ROM or other static memory, and need not be copied. If
+     * optdata is != NULL, we have options instead of data. */
+     
+    /* options? */
+    if (optdata != NULL) {
+      if ((seg->p = pbuf_alloc(PBUF_TRANSPORT, optlen, PBUF_RAM)) == NULL) {
+        goto memerr;
+      }
+      ++queuelen;
+      seg->dataptr = seg->p->payload;
+    }
+    /* copy from volatile memory? */
+    else if (copy) {
+      if ((seg->p = pbuf_alloc(PBUF_TRANSPORT, seglen, PBUF_RAM)) == NULL) {
+        LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue : could not allocate memory for pbuf copy size %u\n", seglen));
+        goto memerr;
+      }
+      ++queuelen;
+      if (arg != NULL) {
+        memcpy(seg->p->payload, ptr, seglen);
+      }
+      seg->dataptr = seg->p->payload;
+    }
+    /* do not copy data */
+    else {
+      /* First, allocate a pbuf for holding the data.
+       * since the referenced data is available at least until it is sent out on the
+       * link (as it has to be ACKed by the remote party) we can safely use PBUF_ROM
+       * instead of PBUF_REF here.
+       */
+      if ((p = pbuf_alloc(PBUF_TRANSPORT, seglen, PBUF_ROM)) == NULL) {
+        LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: could not allocate memory for zero-copy pbuf\n"));
+        goto memerr;
+      }
+      ++queuelen;
+      /* reference the non-volatile payload data */
+      p->payload = ptr;
+      seg->dataptr = ptr;
+
+      /* Second, allocate a pbuf for the headers. */
+      if ((seg->p = pbuf_alloc(PBUF_TRANSPORT, 0, PBUF_RAM)) == NULL) {
+        /* If allocation fails, we have to deallocate the data pbuf as
+         * well. */
+        pbuf_free(p);
+        LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: could not allocate memory for header pbuf\n"));
+        goto memerr;
+      }
+      ++queuelen;
+
+      /* Concatenate the headers and data pbufs together. */
+      pbuf_cat(seg->p/*header*/, p/*data*/);
+      p = NULL;
+    }
+
+    /* Now that there are more segments queued, we check again if the
+    length of the queue exceeds the configured maximum. */
+    if (queuelen > TCP_SND_QUEUELEN) {
+      LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: queue too long %u (%u)\n", queuelen, TCP_SND_QUEUELEN));
+      goto memerr;
+    }
+
+    seg->len = seglen;
+
+    /* build TCP header */
+    if (pbuf_header(seg->p, TCP_HLEN)) {
+      LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: no room for TCP header in pbuf.\n"));
+      TCP_STATS_INC(tcp.err);
+      goto memerr;
+    }
+    seg->tcphdr = seg->p->payload;
+    seg->tcphdr->src = htons(pcb->local_port);
+    seg->tcphdr->dest = htons(pcb->remote_port);
+    seg->tcphdr->seqno = htonl(seqno);
+    seg->tcphdr->urgp = 0;
+    TCPH_FLAGS_SET(seg->tcphdr, flags);
+    /* don't fill in tcphdr->ackno and tcphdr->wnd until later */
+
+    /* Copy the options into the header, if they are present. */
+    if (optdata == NULL) {
+      TCPH_HDRLEN_SET(seg->tcphdr, 5);
+    }
+    else {
+      TCPH_HDRLEN_SET(seg->tcphdr, (5 + optlen / 4));
+      /* Copy options into data portion of segment.
+       Options can thus only be sent in non data carrying
+       segments such as SYN|ACK. */
+      memcpy(seg->dataptr, optdata, optlen);
+    }
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | DBG_TRACE, ("tcp_enqueue: queueing %lu:%lu (0x%x)\n",
+      ntohl(seg->tcphdr->seqno),
+      ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg),
+      flags));
+
+    left -= seglen;
+    seqno += seglen;
+    ptr = (void *)((char *)ptr + seglen);
+  }
+
+  /* Now that the data to be enqueued has been broken up into TCP
+  segments in the queue variable, we add them to the end of the
+  pcb->unsent queue. */
+  if (pcb->unsent == NULL) {
+    useg = NULL;
+  }
+  else {
+    for (useg = pcb->unsent; useg->next != NULL; useg = useg->next);
+  }
+  /* { useg is last segment on the unsent queue, NULL if list is empty } */
+
+  /* If there is room in the last pbuf on the unsent queue,
+  chain the first pbuf on the queue together with that. */
+  if (useg != NULL &&
+    TCP_TCPLEN(useg) != 0 &&
+    !(TCPH_FLAGS(useg->tcphdr) & (TCP_SYN | TCP_FIN)) &&
+    !(flags & (TCP_SYN | TCP_FIN)) &&
+    /* fit within max seg size */
+    useg->len + queue->len <= pcb->mss) {
+    /* Remove TCP header from first segment of our to-be-queued list */
+    pbuf_header(queue->p, -TCP_HLEN);
+    pbuf_cat(useg->p, queue->p);
+    useg->len += queue->len;
+    useg->next = queue->next;
+
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | DBG_TRACE | DBG_STATE, ("tcp_enqueue: chaining segments, new len %u\n", useg->len));
+    if (seg == queue) {
+      seg = NULL;
+    }
+    memp_free(MEMP_TCP_SEG, queue);
+  }
+  else {
+    /* empty list */
+    if (useg == NULL) {
+      /* initialize list with this segment */
+      pcb->unsent = queue;
+    }
+    /* enqueue segment */
+    else {
+      useg->next = queue;
+    }
+  }
+  if ((flags & TCP_SYN) || (flags & TCP_FIN)) {
+    ++len;
+  }
+  pcb->snd_lbb += len;
+  pcb->snd_buf -= len;
+  /* update number of segments on the queues */
+  pcb->snd_queuelen = queuelen;
+  LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue: %d (after enqueued)\n", pcb->snd_queuelen));
+  if (pcb->snd_queuelen != 0) {
+    LWIP_ASSERT("tcp_enqueue: valid queue length",
+      pcb->unacked != NULL || pcb->unsent != NULL);
+  }
+
+  /* Set the PSH flag in the last segment that we enqueued, but only
+  if the segment has data (indicated by seglen > 0). */
+  if (seg != NULL && seglen > 0 && seg->tcphdr != NULL) {
+    TCPH_SET_FLAG(seg->tcphdr, TCP_PSH);
+  }
+
+  return ERR_OK;
+  memerr:
+  TCP_STATS_INC(tcp.memerr);
+
+  if (queue != NULL) {
+    tcp_segs_free(queue);
+  }
+  if (pcb->snd_queuelen != 0) {
+    LWIP_ASSERT("tcp_enqueue: valid queue length", pcb->unacked != NULL ||
+      pcb->unsent != NULL);
+  }
+  LWIP_DEBUGF(TCP_QLEN_DEBUG | DBG_STATE, ("tcp_enqueue: %d (with mem err)\n", pcb->snd_queuelen));
+  return ERR_MEM;
+}
+
+/* find out what we can send and send it */
+err_t
+tcp_output(struct tcp_pcb *pcb)
+{
+  struct pbuf *p;
+  struct tcp_hdr *tcphdr;
+  struct tcp_seg *seg, *useg;
+  u32_t wnd;
+#if TCP_CWND_DEBUG
+  int i = 0;
+#endif /* TCP_CWND_DEBUG */
+
+  /* First, check if we are invoked by the TCP input processing
+     code. If so, we do not output anything. Instead, we rely on the
+     input processing code to call us when input processing is done
+     with. */
+  if (tcp_input_pcb == pcb) {
+    return ERR_OK;
+  }
+
+  wnd = LWIP_MIN(pcb->snd_wnd, pcb->cwnd);
+
+  seg = pcb->unsent;
+
+  /* useg should point to last segment on unacked queue */
+  useg = pcb->unacked;
+  if (useg != NULL) {
+    for (; useg->next != NULL; useg = useg->next);
+  }                                                                             
+   
+  /* If the TF_ACK_NOW flag is set and no data will be sent (either
+   * because the ->unsent queue is empty or because the window does
+   * not allow it), construct an empty ACK segment and send it.
+   *
+   * If data is to be sent, we will just piggyback the ACK (see below).
+   */
+  if (pcb->flags & TF_ACK_NOW &&
+     (seg == NULL ||
+      ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len > wnd)) {
+    p = pbuf_alloc(PBUF_IP, TCP_HLEN, PBUF_RAM);
+    if (p == NULL) {
+      LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: (ACK) could not allocate pbuf\n"));
+      return ERR_BUF;
+    }
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: sending ACK for %lu\n", pcb->rcv_nxt));
+    /* remove ACK flags from the PCB, as we send an empty ACK now */
+    pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW);
+
+    tcphdr = p->payload;
+    tcphdr->src = htons(pcb->local_port);
+    tcphdr->dest = htons(pcb->remote_port);
+    tcphdr->seqno = htonl(pcb->snd_nxt);
+    tcphdr->ackno = htonl(pcb->rcv_nxt);
+    TCPH_FLAGS_SET(tcphdr, TCP_ACK);
+    tcphdr->wnd = htons(pcb->rcv_wnd);
+    tcphdr->urgp = 0;
+    TCPH_HDRLEN_SET(tcphdr, 5);
+
+    tcphdr->chksum = 0;
+#if CHECKSUM_GEN_TCP
+    tcphdr->chksum = inet_chksum_pseudo(p, &(pcb->local_ip), &(pcb->remote_ip),
+          IP_PROTO_TCP, p->tot_len);
+#endif
+    ip_output(p, &(pcb->local_ip), &(pcb->remote_ip), pcb->ttl, pcb->tos,
+        IP_PROTO_TCP);
+    pbuf_free(p);
+
+    return ERR_OK;
+  }
+
+#if TCP_OUTPUT_DEBUG
+  if (seg == NULL) {
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: nothing to send (%p)\n", pcb->unsent));
+  }
+#endif /* TCP_OUTPUT_DEBUG */
+#if TCP_CWND_DEBUG
+  if (seg == NULL) {
+    LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %lu, cwnd %lu, wnd %lu, seg == NULL, ack %lu\n",
+                            pcb->snd_wnd, pcb->cwnd, wnd,
+                            pcb->lastack));
+  } else {
+    LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %lu, cwnd %lu, wnd %lu, effwnd %lu, seq %lu, ack %lu\n",
+                            pcb->snd_wnd, pcb->cwnd, wnd,
+                            ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len,
+                            ntohl(seg->tcphdr->seqno), pcb->lastack));
+  }
+#endif /* TCP_CWND_DEBUG */
+  /* data available and window allows it to be sent? */
+  while (seg != NULL &&
+  ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len <= wnd) {
+#if TCP_CWND_DEBUG
+    LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %lu, cwnd %lu, wnd %lu, effwnd %lu, seq %lu, ack %lu, i%d\n",
+                            pcb->snd_wnd, pcb->cwnd, wnd,
+                            ntohl(seg->tcphdr->seqno) + seg->len -
+                            pcb->lastack,
+                            ntohl(seg->tcphdr->seqno), pcb->lastack, i));
+    ++i;
+#endif /* TCP_CWND_DEBUG */
+
+    pcb->unsent = seg->next;
+
+    if (pcb->state != SYN_SENT) {
+      TCPH_SET_FLAG(seg->tcphdr, TCP_ACK);
+      pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW);
+    }
+
+    tcp_output_segment(seg, pcb);
+    pcb->snd_nxt = ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg);
+    if (TCP_SEQ_LT(pcb->snd_max, pcb->snd_nxt)) {
+      pcb->snd_max = pcb->snd_nxt;
+    }
+    /* put segment on unacknowledged list if length > 0 */
+    if (TCP_TCPLEN(seg) > 0) {
+      seg->next = NULL;
+      /* unacked list is empty? */
+      if (pcb->unacked == NULL) {
+        pcb->unacked = seg;
+        useg = seg;
+      /* unacked list is not empty? */
+      } else {
+        /* In the case of fast retransmit, the packet should not go to the tail
+         * of the unacked queue, but rather at the head. We need to check for
+         * this case. -STJ Jul 27, 2004 */
+        if (TCP_SEQ_LT(ntohl(seg->tcphdr->seqno), ntohl(useg->tcphdr->seqno))){
+          /* add segment to head of unacked list */
+          seg->next = pcb->unacked;
+          pcb->unacked = seg;
+        } else {
+          /* add segment to tail of unacked list */
+          useg->next = seg;
+          useg = useg->next;
+        }
+      }
+    /* do not queue empty segments on the unacked list */
+    } else {
+      tcp_seg_free(seg);
+    }
+    seg = pcb->unsent;
+  }
+  return ERR_OK;
+}
+
+/**
+ * Actually send a TCP segment over IP
+ */
+static void
+tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb)
+{
+  u16_t len;
+  struct netif *netif;
+
+  /* The TCP header has already been constructed, but the ackno and
+   wnd fields remain. */
+  seg->tcphdr->ackno = htonl(pcb->rcv_nxt);
+
+  /* silly window avoidance */
+  if (pcb->rcv_wnd < pcb->mss) {
+    seg->tcphdr->wnd = 0;
+  } else {
+    /* advertise our receive window size in this TCP segment */
+    seg->tcphdr->wnd = htons(pcb->rcv_wnd);
+  }
+
+  /* If we don't have a local IP address, we get one by
+     calling ip_route(). */
+  if (ip_addr_isany(&(pcb->local_ip))) {
+    netif = ip_route(&(pcb->remote_ip));
+    if (netif == NULL) {
+      return;
+    }
+    ip_addr_set(&(pcb->local_ip), &(netif->ip_addr));
+  }
+
+  pcb->rtime = 0;
+
+  if (pcb->rttest == 0) {
+    pcb->rttest = tcp_ticks;
+    pcb->rtseq = ntohl(seg->tcphdr->seqno);
+
+    LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_output_segment: rtseq %lu\n", pcb->rtseq));
+  }
+  LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output_segment: %lu:%lu\n",
+          htonl(seg->tcphdr->seqno), htonl(seg->tcphdr->seqno) +
+          seg->len));
+
+  len = (u16_t)((u8_t *)seg->tcphdr - (u8_t *)seg->p->payload);
+
+  seg->p->len -= len;
+  seg->p->tot_len -= len;
+
+  seg->p->payload = seg->tcphdr;
+
+  seg->tcphdr->chksum = 0;
+#if CHECKSUM_GEN_TCP
+  seg->tcphdr->chksum = inet_chksum_pseudo(seg->p,
+             &(pcb->local_ip),
+             &(pcb->remote_ip),
+             IP_PROTO_TCP, seg->p->tot_len);
+#endif
+  TCP_STATS_INC(tcp.xmit);
+
+  ip_output(seg->p, &(pcb->local_ip), &(pcb->remote_ip), pcb->ttl, pcb->tos,
+      IP_PROTO_TCP);
+}
+
+void
+tcp_rst(u32_t seqno, u32_t ackno,
+  struct ip_addr *local_ip, struct ip_addr *remote_ip,
+  u16_t local_port, u16_t remote_port)
+{
+  struct pbuf *p;
+  struct tcp_hdr *tcphdr;
+  p = pbuf_alloc(PBUF_IP, TCP_HLEN, PBUF_RAM);
+  if (p == NULL) {
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_rst: could not allocate memory for pbuf\n"));
+      return;
+  }
+
+  tcphdr = p->payload;
+  tcphdr->src = htons(local_port);
+  tcphdr->dest = htons(remote_port);
+  tcphdr->seqno = htonl(seqno);
+  tcphdr->ackno = htonl(ackno);
+  TCPH_FLAGS_SET(tcphdr, TCP_RST | TCP_ACK);
+  tcphdr->wnd = htons(TCP_WND);
+  tcphdr->urgp = 0;
+  TCPH_HDRLEN_SET(tcphdr, 5);
+
+  tcphdr->chksum = 0;
+#if CHECKSUM_GEN_TCP
+  tcphdr->chksum = inet_chksum_pseudo(p, local_ip, remote_ip,
+              IP_PROTO_TCP, p->tot_len);
+#endif
+  TCP_STATS_INC(tcp.xmit);
+   /* Send output with hardcoded TTL since we have no access to the pcb */
+  ip_output(p, local_ip, remote_ip, TCP_TTL, 0, IP_PROTO_TCP);
+  pbuf_free(p);
+  LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_rst: seqno %lu ackno %lu.\n", seqno, ackno));
+}
+
+/* requeue all unacked segments for retransmission */
+void
+tcp_rexmit_rto(struct tcp_pcb *pcb)
+{
+  struct tcp_seg *seg;
+
+  if (pcb->unacked == NULL) {
+    return;
+  }
+
+  /* Move all unacked segments to the head of the unsent queue */
+  for (seg = pcb->unacked; seg->next != NULL; seg = seg->next);
+  /* concatenate unsent queue after unacked queue */
+  seg->next = pcb->unsent;
+  /* unsent queue is the concatenated queue (of unacked, unsent) */
+  pcb->unsent = pcb->unacked;
+  /* unacked queue is now empty */
+  pcb->unacked = NULL;
+
+  pcb->snd_nxt = ntohl(pcb->unsent->tcphdr->seqno);
+  /* increment number of retransmissions */
+  ++pcb->nrtx;
+
+  /* Don't take any RTT measurements after retransmitting. */
+  pcb->rttest = 0;
+
+  /* Do the actual retransmission */
+  tcp_output(pcb);
+}
+
+void
+tcp_rexmit(struct tcp_pcb *pcb)
+{
+  struct tcp_seg *seg;
+
+  if (pcb->unacked == NULL) {
+    return;
+  }
+
+  /* Move the first unacked segment to the unsent queue */
+  seg = pcb->unacked->next;
+  pcb->unacked->next = pcb->unsent;
+  pcb->unsent = pcb->unacked;
+  pcb->unacked = seg;
+
+  pcb->snd_nxt = ntohl(pcb->unsent->tcphdr->seqno);
+
+  ++pcb->nrtx;
+
+  /* Don't take any rtt measurements after retransmitting. */
+  pcb->rttest = 0;
+
+  /* Do the actual retransmission. */
+  tcp_output(pcb);
+
+}
+
+
+void
+tcp_keepalive(struct tcp_pcb *pcb)
+{
+   struct pbuf *p;
+   struct tcp_hdr *tcphdr;
+
+   LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: sending KEEPALIVE probe to %u.%u.%u.%u\n",
+                           ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip),
+                           ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip)));
+
+   LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: tcp_ticks %lu   pcb->tmr %lu  pcb->keep_cnt %u\n", tcp_ticks, pcb->tmr, pcb->keep_cnt));
+   
+   p = pbuf_alloc(PBUF_IP, TCP_HLEN, PBUF_RAM);
+
+   if(p == NULL) {
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: could not allocate memory for pbuf\n"));
+      return;
+   }
+
+   tcphdr = p->payload;
+   tcphdr->src = htons(pcb->local_port);
+   tcphdr->dest = htons(pcb->remote_port);
+   tcphdr->seqno = htonl(pcb->snd_nxt - 1);
+   tcphdr->ackno = htonl(pcb->rcv_nxt);
+   tcphdr->wnd = htons(pcb->rcv_wnd);
+   tcphdr->urgp = 0;
+   TCPH_HDRLEN_SET(tcphdr, 5);
+   
+   tcphdr->chksum = 0;
+#if CHECKSUM_GEN_TCP
+   tcphdr->chksum = inet_chksum_pseudo(p, &pcb->local_ip, &pcb->remote_ip, IP_PROTO_TCP, p->tot_len);
+#endif
+  TCP_STATS_INC(tcp.xmit);
+
+   /* Send output to IP */
+  ip_output(p, &pcb->local_ip, &pcb->remote_ip, pcb->ttl, 0, IP_PROTO_TCP);
+
+  pbuf_free(p);
+
+  LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_keepalive: seqno %lu ackno %lu.\n", pcb->snd_nxt - 1, pcb->rcv_nxt));
+}
+
+#endif /* LWIP_TCP */
+
+
+
+
+
+
+
+
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/udp.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/udp.c
new file mode 100644
index 000000000..8bea4ed5e
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/udp.c
@@ -0,0 +1,801 @@
+/**
+ * @file
+ * User Datagram Protocol module
+ *
+ */
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+
+/* udp.c
+ *
+ * The code for the User Datagram Protocol UDP.
+ *
+ */
+
+#include 
+
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+#include "lwip/memp.h"
+#include "lwip/inet.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/udp.h"
+#include "lwip/icmp.h"
+
+#include "lwip/stats.h"
+
+#include "arch/perf.h"
+#include "lwip/snmp.h"
+
+/* The list of UDP PCBs */
+#if LWIP_UDP
+/* was static, but we may want to access this from a socket layer */
+struct udp_pcb *udp_pcbs = NULL;
+
+static struct udp_pcb *pcb_cache = NULL;
+
+
+void
+udp_init(void)
+{
+  udp_pcbs = pcb_cache = NULL;
+}
+
+/**
+ * Process an incoming UDP datagram.
+ *
+ * Given an incoming UDP datagram (as a chain of pbufs) this function
+ * finds a corresponding UDP PCB and
+ *
+ * @param pbuf pbuf to be demultiplexed to a UDP PCB.
+ * @param netif network interface on which the datagram was received.
+ *
+ */
+void
+udp_input(struct pbuf *p, struct netif *inp)
+{
+  struct udp_hdr *udphdr;
+  struct udp_pcb *pcb;
+  struct ip_hdr *iphdr;
+  u16_t src, dest;
+
+#if SO_REUSE
+  struct udp_pcb *pcb_temp;
+  int reuse = 0;
+  int reuse_port_1 = 0;
+  int reuse_port_2 = 0;
+#endif /* SO_REUSE */
+  
+  PERF_START;
+
+  UDP_STATS_INC(udp.recv);
+
+  iphdr = p->payload;
+
+  if (pbuf_header(p, -((s16_t)(UDP_HLEN + IPH_HL(iphdr) * 4)))) {
+    /* drop short packets */
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_input: short UDP datagram (%u bytes) discarded\n", p->tot_len));
+    UDP_STATS_INC(udp.lenerr);
+    UDP_STATS_INC(udp.drop);
+    snmp_inc_udpinerrors();
+    pbuf_free(p);
+    goto end;
+  }
+
+  udphdr = (struct udp_hdr *)((u8_t *)p->payload - UDP_HLEN);
+
+  LWIP_DEBUGF(UDP_DEBUG, ("udp_input: received datagram of length %u\n", p->tot_len));
+
+  src = ntohs(udphdr->src);
+  dest = ntohs(udphdr->dest);
+
+  udp_debug_print(udphdr);
+
+  /* print the UDP source and destination */
+  LWIP_DEBUGF(UDP_DEBUG, ("udp (%u.%u.%u.%u, %u) <-- (%u.%u.%u.%u, %u)\n",
+    ip4_addr1(&iphdr->dest), ip4_addr2(&iphdr->dest),
+    ip4_addr3(&iphdr->dest), ip4_addr4(&iphdr->dest), ntohs(udphdr->dest),
+    ip4_addr1(&iphdr->src), ip4_addr2(&iphdr->src),
+    ip4_addr3(&iphdr->src), ip4_addr4(&iphdr->src), ntohs(udphdr->src)));
+
+#if SO_REUSE
+  pcb_temp = udp_pcbs;
+  
+ again_1:
+  
+  /* Iterate through the UDP pcb list for a fully matching pcb */
+  for (pcb = pcb_temp; pcb != NULL; pcb = pcb->next) {
+#else  /* SO_REUSE */ 
+  /* Iterate through the UDP pcb list for a fully matching pcb */
+  for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) {
+#endif  /* SO_REUSE */ 
+    /* print the PCB local and remote address */
+    LWIP_DEBUGF(UDP_DEBUG, ("pcb (%u.%u.%u.%u, %u) --- (%u.%u.%u.%u, %u)\n",
+      ip4_addr1(&pcb->local_ip), ip4_addr2(&pcb->local_ip),
+      ip4_addr3(&pcb->local_ip), ip4_addr4(&pcb->local_ip), pcb->local_port,
+      ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip),
+      ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip), pcb->remote_port));
+
+       /* PCB remote port matches UDP source port? */
+    if ((pcb->remote_port == src) &&
+       /* PCB local port matches UDP destination port? */
+       (pcb->local_port == dest) &&
+       /* accepting from any remote (source) IP address? or... */
+       (ip_addr_isany(&pcb->remote_ip) ||
+       /* PCB remote IP address matches UDP source IP address? */
+        ip_addr_cmp(&(pcb->remote_ip), &(iphdr->src))) &&
+       /* accepting on any local (netif) IP address? or... */
+       (ip_addr_isany(&pcb->local_ip) ||
+       /* PCB local IP address matches UDP destination IP address? */
+        ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest)))) {
+#if SO_REUSE
+      if (pcb->so_options & SOF_REUSEPORT) {
+        if(reuse) {
+          /* We processed one PCB already */
+          LWIP_DEBUGF(UDP_DEBUG, ("udp_input: second or later PCB and SOF_REUSEPORT set.\n"));
+        } else {
+          /* First PCB with this address */
+          LWIP_DEBUGF(UDP_DEBUG, ("udp_input: first PCB and SOF_REUSEPORT set.\n"));
+          reuse = 1;
+        }
+        
+        reuse_port_1 = 1; 
+        p->ref++;
+        LWIP_DEBUGF(UDP_DEBUG, ("udp_input: reference counter on PBUF set to %i\n", p->ref));
+      } else {
+        if (reuse) {
+          /* We processed one PCB already */
+          LWIP_DEBUGF(UDP_DEBUG, ("udp_input: second or later PCB but SOF_REUSEPORT not set !\n"));
+        }
+      }
+#endif /* SO_REUSE */
+      break;
+    }
+  }
+  /* no fully matching pcb found? then look for an unconnected pcb */
+  if (pcb == NULL) {
+    /* Iterate through the UDP PCB list for a pcb that matches
+       the local address. */
+
+#if SO_REUSE
+    pcb_temp = udp_pcbs;
+    
+  again_2:
+
+    for (pcb = pcb_temp; pcb != NULL; pcb = pcb->next) {
+#else  /* SO_REUSE */ 
+    for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) {
+#endif  /* SO_REUSE */ 
+      LWIP_DEBUGF(UDP_DEBUG, ("pcb (%u.%u.%u.%u, %u) --- (%u.%u.%u.%u, %u)\n",
+        ip4_addr1(&pcb->local_ip), ip4_addr2(&pcb->local_ip),
+        ip4_addr3(&pcb->local_ip), ip4_addr4(&pcb->local_ip), pcb->local_port,
+        ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip),
+        ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip), pcb->remote_port));
+      /* unconnected? */
+      if (((pcb->flags & UDP_FLAGS_CONNECTED) == 0) &&
+         /* destination port matches? */
+        (pcb->local_port == dest) &&
+        /* not bound to a specific (local) interface address? or... */
+        (ip_addr_isany(&pcb->local_ip) ||
+        /* ...matching interface address? */
+        ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest)))) {
+#if SO_REUSE
+        if (pcb->so_options & SOF_REUSEPORT) {
+          if (reuse) {
+            /* We processed one PCB already */
+            LWIP_DEBUGF(UDP_DEBUG, ("udp_input: second or later PCB and SOF_REUSEPORT set.\n"));
+          } else {
+            /* First PCB with this address */
+            LWIP_DEBUGF(UDP_DEBUG, ("udp_input: first PCB and SOF_REUSEPORT set.\n"));
+            reuse = 1;
+          }
+          
+          reuse_port_2 = 1; 
+          p->ref++;
+          LWIP_DEBUGF(UDP_DEBUG, ("udp_input: reference counter on PBUF set to %i\n", p->ref));
+        } else {
+          if (reuse) {
+            /* We processed one PCB already */
+            LWIP_DEBUGF(UDP_DEBUG, ("udp_input: second or later PCB but SOF_REUSEPORT not set !\n"));
+          }
+        }
+#endif /* SO_REUSE */
+        break;
+      }
+    }
+  }
+
+  /* Check checksum if this is a match or if it was directed at us. */
+  if (pcb != NULL  || ip_addr_cmp(&inp->ip_addr, &iphdr->dest))
+    {
+    LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE, ("udp_input: calculating checksum\n"));
+    pbuf_header(p, UDP_HLEN);
+#ifdef IPv6
+    if (iphdr->nexthdr == IP_PROTO_UDPLITE) {
+#else
+    if (IPH_PROTO(iphdr) == IP_PROTO_UDPLITE) {
+#endif /* IPv4 */
+      /* Do the UDP Lite checksum */
+#if CHECKSUM_CHECK_UDP
+      if (inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src),
+         (struct ip_addr *)&(iphdr->dest),
+         IP_PROTO_UDPLITE, ntohs(udphdr->len)) != 0) {
+  LWIP_DEBUGF(UDP_DEBUG | 2, ("udp_input: UDP Lite datagram discarded due to failing checksum\n"));
+  UDP_STATS_INC(udp.chkerr);
+  UDP_STATS_INC(udp.drop);
+  snmp_inc_udpinerrors();
+  pbuf_free(p);
+  goto end;
+      }
+#endif
+    } else {
+#if CHECKSUM_CHECK_UDP
+      if (udphdr->chksum != 0) {
+  if (inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src),
+       (struct ip_addr *)&(iphdr->dest),
+        IP_PROTO_UDP, p->tot_len) != 0) {
+    LWIP_DEBUGF(UDP_DEBUG | 2, ("udp_input: UDP datagram discarded due to failing checksum\n"));
+
+    UDP_STATS_INC(udp.chkerr);
+    UDP_STATS_INC(udp.drop);
+    snmp_inc_udpinerrors();
+    pbuf_free(p);
+    goto end;
+  }
+      }
+#endif
+    }
+    pbuf_header(p, -UDP_HLEN);
+    if (pcb != NULL) {
+      snmp_inc_udpindatagrams();
+      pcb->recv(pcb->recv_arg, pcb, p, &(iphdr->src), src);
+#if SO_REUSE
+      /* First socket should receive now */
+      if(reuse_port_1 || reuse_port_2) {
+        /* We want to search on next socket after receiving */
+        pcb_temp = pcb->next;
+        
+        if(reuse_port_1) {
+          /* We are searching connected sockets */
+          reuse_port_1 = 0;
+          reuse_port_2 = 0;
+          goto again_1;
+        } else {
+          /* We are searching unconnected sockets */
+          reuse_port_1 = 0;
+          reuse_port_2 = 0;
+          goto again_2;
+        }
+      }
+#endif /* SO_REUSE */ 
+    } else {
+#if SO_REUSE
+      if(reuse) {
+        LWIP_DEBUGF(UDP_DEBUG, ("udp_input: freeing PBUF with reference counter set to %i\n", p->ref));
+        pbuf_free(p);
+        goto end;
+      }
+#endif /* SO_REUSE */
+      LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE, ("udp_input: not for us.\n"));
+
+      /* No match was found, send ICMP destination port unreachable unless
+      destination address was broadcast/multicast. */
+
+      if (!ip_addr_isbroadcast(&iphdr->dest, inp) &&
+          !ip_addr_ismulticast(&iphdr->dest)) {
+
+  /* adjust pbuf pointer */
+  p->payload = iphdr;
+  icmp_dest_unreach(p, ICMP_DUR_PORT);
+      }
+      UDP_STATS_INC(udp.proterr);
+      UDP_STATS_INC(udp.drop);
+    snmp_inc_udpnoports();
+      pbuf_free(p);
+    }
+  } else {
+    pbuf_free(p);
+  }
+  end:
+
+  PERF_STOP("udp_input");
+}
+
+/**
+ * Send data to a specified address using UDP.
+ *
+ * @param pcb UDP PCB used to send the data.
+ * @param pbuf chain of pbuf's to be sent.
+ * @param dst_ip Destination IP address.
+ * @param dst_port Destination UDP port.
+ *
+ * If the PCB already has a remote address association, it will
+ * be restored after the data is sent.
+ * 
+ * @return lwIP error code.
+ * - ERR_OK. Successful. No error occured.
+ * - ERR_MEM. Out of memory.
+ * - ERR_RTE. Could not find route to destination address.
+ *
+ * @see udp_disconnect() udp_send()
+ */
+err_t
+udp_sendto(struct udp_pcb *pcb, struct pbuf *p,
+  struct ip_addr *dst_ip, u16_t dst_port)
+{
+  err_t err;
+  /* temporary space for current PCB remote address */
+  struct ip_addr pcb_remote_ip;
+  u16_t pcb_remote_port;
+  /* remember current remote peer address of PCB */
+  pcb_remote_ip.addr = pcb->remote_ip.addr;
+  pcb_remote_port = pcb->remote_port;
+  /* copy packet destination address to PCB remote peer address */
+  pcb->remote_ip.addr = dst_ip->addr;
+  pcb->remote_port = dst_port;
+  /* send to the packet destination address */
+  err = udp_send(pcb, p);
+  /* restore PCB remote peer address */
+  pcb->remote_ip.addr = pcb_remote_ip.addr;
+  pcb->remote_port = pcb_remote_port;
+  return err;
+}
+
+/**
+ * Send data using UDP.
+ *
+ * @param pcb UDP PCB used to send the data.
+ * @param pbuf chain of pbuf's to be sent.
+ *
+ * @return lwIP error code.
+ * - ERR_OK. Successful. No error occured.
+ * - ERR_MEM. Out of memory.
+ * - ERR_RTE. Could not find route to destination address.
+ *
+ * @see udp_disconnect() udp_sendto()
+ */
+err_t
+udp_send(struct udp_pcb *pcb, struct pbuf *p)
+{
+  struct udp_hdr *udphdr;
+  struct netif *netif;
+  struct ip_addr *src_ip;
+  err_t err;
+  struct pbuf *q; /* q will be sent down the stack */
+
+  LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 3, ("udp_send\n"));
+
+  /* if the PCB is not yet bound to a port, bind it here */
+  if (pcb->local_port == 0) {
+    LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 2, ("udp_send: not yet bound to a port, binding now\n"));
+    err = udp_bind(pcb, &pcb->local_ip, pcb->local_port);
+    if (err != ERR_OK) {
+      LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 2, ("udp_send: forced port bind failed\n"));
+      return err;
+    }
+  }
+
+  /* not enough space to add an UDP header to first pbuf in given p chain? */
+  if (pbuf_header(p, UDP_HLEN)) {
+    /* allocate header in a seperate new pbuf */
+    q = pbuf_alloc(PBUF_IP, UDP_HLEN, PBUF_RAM);
+    /* new header pbuf could not be allocated? */
+    if (q == NULL) {
+      LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 2, ("udp_send: could not allocate header\n"));
+      return ERR_MEM;
+    }
+    /* chain header q in front of given pbuf p */
+    pbuf_chain(q, p);
+    /* { first pbuf q points to header pbuf } */
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: added header pbuf %p before given pbuf %p\n", (void *)q, (void *)p));
+  /* adding a header within p succeeded */
+  } else {
+    /* first pbuf q equals given pbuf */
+    q = p;
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: added header in given pbuf %p\n", (void *)p));
+  }
+  /* { q now represents the packet to be sent } */
+  udphdr = q->payload;
+  udphdr->src = htons(pcb->local_port);
+  udphdr->dest = htons(pcb->remote_port);
+  /* in UDP, 0 checksum means 'no checksum' */
+  udphdr->chksum = 0x0000; 
+
+  /* find the outgoing network interface for this packet */
+  netif = ip_route(&(pcb->remote_ip));
+  /* no outgoing network interface could be found? */
+  if (netif == NULL) {
+    LWIP_DEBUGF(UDP_DEBUG | 1, ("udp_send: No route to 0x%lx\n", pcb->remote_ip.addr));
+    UDP_STATS_INC(udp.rterr);
+    return ERR_RTE;
+  }
+  /* PCB local address is IP_ANY_ADDR? */
+  if (ip_addr_isany(&pcb->local_ip)) {
+    /* use outgoing network interface IP address as source address */
+    src_ip = &(netif->ip_addr);
+  } else {
+    /* use UDP PCB local IP address as source address */
+    src_ip = &(pcb->local_ip);
+  }
+
+  LWIP_DEBUGF(UDP_DEBUG, ("udp_send: sending datagram of length %u\n", q->tot_len));
+
+  /* UDP Lite protocol? */
+  if (pcb->flags & UDP_FLAGS_UDPLITE) {
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP LITE packet length %u\n", q->tot_len));
+    /* set UDP message length in UDP header */
+    udphdr->len = htons(pcb->chksum_len);
+    /* calculate checksum */
+#if CHECKSUM_GEN_UDP
+    udphdr->chksum = inet_chksum_pseudo(q, src_ip, &(pcb->remote_ip),
+          IP_PROTO_UDP, pcb->chksum_len);
+    /* chksum zero must become 0xffff, as zero means 'no checksum' */
+    if (udphdr->chksum == 0x0000) udphdr->chksum = 0xffff;
+#else
+    udphdr->chksum = 0x0000;
+#endif
+    /* output to IP */
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: ip_output_if (,,,,IP_PROTO_UDPLITE,)\n"));
+    err = ip_output_if (q, src_ip, &pcb->remote_ip, pcb->ttl, pcb->tos, IP_PROTO_UDPLITE, netif);    
+  /* UDP */
+  } else {
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP packet length %u\n", q->tot_len));
+    udphdr->len = htons(q->tot_len);
+    /* calculate checksum */
+#if CHECKSUM_GEN_UDP
+    if ((pcb->flags & UDP_FLAGS_NOCHKSUM) == 0) {
+      udphdr->chksum = inet_chksum_pseudo(q, src_ip, &pcb->remote_ip, IP_PROTO_UDP, q->tot_len);
+      /* chksum zero must become 0xffff, as zero means 'no checksum' */
+      if (udphdr->chksum == 0x0000) udphdr->chksum = 0xffff;
+    }
+#else
+    udphdr->chksum = 0x0000;
+#endif
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP checksum 0x%04x\n", udphdr->chksum));
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: ip_output_if (,,,,IP_PROTO_UDP,)\n"));
+    /* output to IP */
+    err = ip_output_if(q, src_ip, &pcb->remote_ip, pcb->ttl, pcb->tos, IP_PROTO_UDP, netif);    
+  }
+  /* TODO: must this be increased even if error occured? */
+  snmp_inc_udpoutdatagrams();
+
+  /* did we chain a seperate header pbuf earlier? */
+  if (q != p) {
+    /* free the header pbuf */
+    pbuf_free(q); q = NULL;
+    /* { p is still referenced by the caller, and will live on } */
+  }
+
+  UDP_STATS_INC(udp.xmit);
+  return err;
+}
+
+/**
+ * Bind an UDP PCB.
+ *
+ * @param pcb UDP PCB to be bound with a local address ipaddr and port.
+ * @param ipaddr local IP address to bind with. Use IP_ADDR_ANY to
+ * bind to all local interfaces.
+ * @param port local UDP port to bind with.
+ *
+ * @return lwIP error code.
+ * - ERR_OK. Successful. No error occured.
+ * - ERR_USE. The specified ipaddr and port are already bound to by
+ * another UDP PCB.
+ *
+ * @see udp_disconnect()
+ */
+err_t
+udp_bind(struct udp_pcb *pcb, struct ip_addr *ipaddr, u16_t port)
+{
+  struct udp_pcb *ipcb;
+  u8_t rebind;
+#if SO_REUSE
+  int reuse_port_all_set = 1;
+#endif /* SO_REUSE */
+  LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 3, ("udp_bind(ipaddr = "));
+  ip_addr_debug_print(UDP_DEBUG, ipaddr);
+  LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 3, (", port = %u)\n", port));
+
+  rebind = 0;
+  /* Check for double bind and rebind of the same pcb */
+  for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
+    /* is this UDP PCB already on active list? */
+    if (pcb == ipcb) {
+      /* pcb may occur at most once in active list */
+      LWIP_ASSERT("rebind == 0", rebind == 0);
+      /* pcb already in list, just rebind */
+      rebind = 1;
+    }
+
+#if SO_REUSE == 0
+/* this code does not allow upper layer to share a UDP port for
+   listening to broadcast or multicast traffic (See SO_REUSE_ADDR and
+   SO_REUSE_PORT under *BSD). TODO: See where it fits instead, OR
+   combine with implementation of UDP PCB flags. Leon Woestenberg. */
+#ifdef LWIP_UDP_TODO
+    /* port matches that of PCB in list? */
+    else if ((ipcb->local_port == port) &&
+       /* IP address matches, or one is IP_ADDR_ANY? */
+       (ip_addr_isany(&(ipcb->local_ip)) ||
+       ip_addr_isany(ipaddr) ||
+       ip_addr_cmp(&(ipcb->local_ip), ipaddr))) {
+      /* other PCB already binds to this local IP and port */
+      LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: local port %u already bound by another pcb\n", port));
+      return ERR_USE;
+    }
+#endif
+
+#else /* SO_REUSE */
+      /* Search through list of PCB's. 
+         
+      If there is a PCB bound to specified port and IP_ADDR_ANY another PCB can be bound to the interface IP
+      or to the loopback address on the same port if SOF_REUSEADDR is set. Any combination of PCB's bound to 
+      the same local port, but to one address out of {IP_ADDR_ANY, 127.0.0.1, interface IP} at a time is valid.
+      But no two PCB's bound to same local port and same local address is valid.
+      
+      If SOF_REUSEPORT is set several PCB's can be bound to same local port and same local address also. But then 
+      all PCB's must have the SOF_REUSEPORT option set.
+      
+      When the two options aren't set and specified port is already bound, ERR_USE is returned saying that 
+      address is already in use. */
+    else if (ipcb->local_port == port) {
+      if(ip_addr_cmp(&(ipcb->local_ip), ipaddr)) {
+        if(pcb->so_options & SOF_REUSEPORT) {
+          LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: in UDP PCB's SO_REUSEPORT set and same address.\n"));
+          reuse_port_all_set = (reuse_port_all_set && (ipcb->so_options & SOF_REUSEPORT));
+        }
+        else {
+          LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: in UDP PCB's SO_REUSEPORT not set and same address.\n"));
+          return ERR_USE;
+        }
+      }
+      else if((ip_addr_isany(ipaddr) && !ip_addr_isany(&(ipcb->local_ip))) ||
+              (!ip_addr_isany(ipaddr) && ip_addr_isany(&(ipcb->local_ip)))) {
+        if(!(pcb->so_options & SOF_REUSEADDR) && !(pcb->so_options & SOF_REUSEPORT)) {
+          LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: in UDP PCB's SO_REUSEPORT or SO_REUSEADDR not set and not the same address.\n"));
+          return ERR_USE;
+        }           
+      }
+    }
+#endif /* SO_REUSE */
+
+  }
+
+#if SO_REUSE
+  /* If SOF_REUSEPORT isn't set in all PCB's bound to specified port and local address specified then 
+     {IP, port} can't be reused. */
+  if(!reuse_port_all_set) {
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: not all sockets have SO_REUSEPORT set.\n"));
+    return ERR_USE;
+  }
+#endif /* SO_REUSE */
+
+  ip_addr_set(&pcb->local_ip, ipaddr);
+  /* no port specified? */
+  if (port == 0) {
+#ifndef UDP_LOCAL_PORT_RANGE_START
+#define UDP_LOCAL_PORT_RANGE_START 4096
+#define UDP_LOCAL_PORT_RANGE_END   0x7fff
+#endif
+    port = UDP_LOCAL_PORT_RANGE_START;
+    ipcb = udp_pcbs;
+    while ((ipcb != NULL) && (port != UDP_LOCAL_PORT_RANGE_END)) {
+      if (ipcb->local_port == port) {
+        port++;
+        ipcb = udp_pcbs;
+      } else
+        ipcb = ipcb->next;
+    }
+    if (ipcb != NULL) {
+      /* no more ports available in local range */
+      LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: out of free UDP ports\n"));
+      return ERR_USE;
+    }
+  }
+  pcb->local_port = port;
+  /* pcb not active yet? */
+  if (rebind == 0) {
+    /* place the PCB on the active list if not already there */
+    pcb->next = udp_pcbs;
+    udp_pcbs = pcb;
+  }
+  LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | DBG_STATE, ("udp_bind: bound to %u.%u.%u.%u, port %u\n",
+   (unsigned int)(ntohl(pcb->local_ip.addr) >> 24 & 0xff),
+   (unsigned int)(ntohl(pcb->local_ip.addr) >> 16 & 0xff),
+   (unsigned int)(ntohl(pcb->local_ip.addr) >> 8 & 0xff),
+   (unsigned int)(ntohl(pcb->local_ip.addr) & 0xff), pcb->local_port));
+  return ERR_OK;
+}
+/**
+ * Connect an UDP PCB.
+ *
+ * This will associate the UDP PCB with the remote address.
+ *
+ * @param pcb UDP PCB to be connected with remote address ipaddr and port.
+ * @param ipaddr remote IP address to connect with.
+ * @param port remote UDP port to connect with.
+ *
+ * @return lwIP error code
+ *
+ * @see udp_disconnect()
+ */
+err_t
+udp_connect(struct udp_pcb *pcb, struct ip_addr *ipaddr, u16_t port)
+{
+  struct udp_pcb *ipcb;
+
+  if (pcb->local_port == 0) {
+    err_t err = udp_bind(pcb, &pcb->local_ip, pcb->local_port);
+    if (err != ERR_OK)
+      return err;
+  }
+
+  ip_addr_set(&pcb->remote_ip, ipaddr);
+  pcb->remote_port = port;
+  pcb->flags |= UDP_FLAGS_CONNECTED;
+/** TODO: this functionality belongs in upper layers */
+#ifdef LWIP_UDP_TODO
+  /* Nail down local IP for netconn_addr()/getsockname() */
+  if (ip_addr_isany(&pcb->local_ip) && !ip_addr_isany(&pcb->remote_ip)) {
+    struct netif *netif;
+
+    if ((netif = ip_route(&(pcb->remote_ip))) == NULL) {
+      LWIP_DEBUGF(UDP_DEBUG, ("udp_connect: No route to 0x%lx\n", pcb->remote_ip.addr));
+        UDP_STATS_INC(udp.rterr);
+      return ERR_RTE;
+    }
+    /** TODO: this will bind the udp pcb locally, to the interface which
+        is used to route output packets to the remote address. However, we
+        might want to accept incoming packets on any interface! */
+    pcb->local_ip = netif->ip_addr;
+  } else if (ip_addr_isany(&pcb->remote_ip)) {
+    pcb->local_ip.addr = 0;
+  }
+#endif
+  LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | DBG_STATE, ("udp_connect: connected to %u.%u.%u.%u, port %u\n",
+   (unsigned int)(ntohl(pcb->remote_ip.addr) >> 24 & 0xff),
+   (unsigned int)(ntohl(pcb->remote_ip.addr) >> 16 & 0xff),
+   (unsigned int)(ntohl(pcb->remote_ip.addr) >> 8 & 0xff),
+   (unsigned int)(ntohl(pcb->remote_ip.addr) & 0xff), pcb->remote_port));
+
+  /* Insert UDP PCB into the list of active UDP PCBs. */
+  for(ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
+    if (pcb == ipcb) {
+      /* already on the list, just return */
+      return ERR_OK;
+    }
+  }
+  /* PCB not yet on the list, add PCB now */
+  pcb->next = udp_pcbs;
+  udp_pcbs = pcb;
+  return ERR_OK;
+}
+
+void
+udp_disconnect(struct udp_pcb *pcb)
+{
+  /* reset remote address association */
+  ip_addr_set(&pcb->remote_ip, IP_ADDR_ANY);
+  pcb->remote_port = 0;
+  /* mark PCB as unconnected */
+  pcb->flags &= ~UDP_FLAGS_CONNECTED;
+}
+
+void
+udp_recv(struct udp_pcb *pcb,
+   void (* recv)(void *arg, struct udp_pcb *upcb, struct pbuf *p,
+           struct ip_addr *addr, u16_t port),
+   void *recv_arg)
+{
+  /* remember recv() callback and user data */
+  pcb->recv = recv;
+  pcb->recv_arg = recv_arg;
+}
+/**
+ * Remove an UDP PCB.
+ *
+ * @param pcb UDP PCB to be removed. The PCB is removed from the list of
+ * UDP PCB's and the data structure is freed from memory.
+ *
+ * @see udp_new()
+ */
+void
+udp_remove(struct udp_pcb *pcb)
+{
+  struct udp_pcb *pcb2;
+  /* pcb to be removed is first in list? */
+  if (udp_pcbs == pcb) {
+    /* make list start at 2nd pcb */
+    udp_pcbs = udp_pcbs->next;
+  /* pcb not 1st in list */
+  } else for(pcb2 = udp_pcbs; pcb2 != NULL; pcb2 = pcb2->next) {
+    /* find pcb in udp_pcbs list */
+    if (pcb2->next != NULL && pcb2->next == pcb) {
+      /* remove pcb from list */
+      pcb2->next = pcb->next;
+    }
+  }
+  memp_free(MEMP_UDP_PCB, pcb);
+}
+/**
+ * Create a UDP PCB.
+ *
+ * @return The UDP PCB which was created. NULL if the PCB data structure
+ * could not be allocated.
+ *
+ * @see udp_remove()
+ */
+struct udp_pcb *
+udp_new(void) {
+  struct udp_pcb *pcb;
+  pcb = memp_malloc(MEMP_UDP_PCB);
+  /* could allocate UDP PCB? */
+  if (pcb != NULL) {
+    /* initialize PCB to all zeroes */
+    memset(pcb, 0, sizeof(struct udp_pcb));
+    pcb->ttl = UDP_TTL;
+  }
+  
+  
+  return pcb;
+}
+
+#if UDP_DEBUG
+int
+udp_debug_print(struct udp_hdr *udphdr)
+{
+  LWIP_DEBUGF(UDP_DEBUG, ("UDP header:\n"));
+  LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(UDP_DEBUG, ("|     %5u     |     %5u     | (src port, dest port)\n",
+         ntohs(udphdr->src), ntohs(udphdr->dest)));
+  LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(UDP_DEBUG, ("|     %5u     |     0x%04x    | (len, chksum)\n",
+         ntohs(udphdr->len), ntohs(udphdr->chksum)));
+  LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n"));
+  return 0;
+}
+#endif /* UDP_DEBUG */
+
+#endif /* LWIP_UDP */
+
+
+
+
+
+
+
+
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv4/lwip/icmp.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv4/lwip/icmp.h
new file mode 100644
index 000000000..04307e743
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv4/lwip/icmp.h
@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_ICMP_H__
+#define __LWIP_ICMP_H__
+
+#include "lwip/arch.h"
+
+#include "lwip/opt.h"
+#include "lwip/pbuf.h"
+
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+
+#define ICMP_ER 0      /* echo reply */
+#define ICMP_DUR 3     /* destination unreachable */
+#define ICMP_SQ 4      /* source quench */
+#define ICMP_RD 5      /* redirect */
+#define ICMP_ECHO 8    /* echo */
+#define ICMP_TE 11     /* time exceeded */
+#define ICMP_PP 12     /* parameter problem */
+#define ICMP_TS 13     /* timestamp */
+#define ICMP_TSR 14    /* timestamp reply */
+#define ICMP_IRQ 15    /* information request */
+#define ICMP_IR 16     /* information reply */
+
+enum icmp_dur_type {
+  ICMP_DUR_NET = 0,    /* net unreachable */
+  ICMP_DUR_HOST = 1,   /* host unreachable */
+  ICMP_DUR_PROTO = 2,  /* protocol unreachable */
+  ICMP_DUR_PORT = 3,   /* port unreachable */
+  ICMP_DUR_FRAG = 4,   /* fragmentation needed and DF set */
+  ICMP_DUR_SR = 5      /* source route failed */
+};
+
+enum icmp_te_type {
+  ICMP_TE_TTL = 0,     /* time to live exceeded in transit */
+  ICMP_TE_FRAG = 1     /* fragment reassembly time exceeded */
+};
+
+void icmp_input(struct pbuf *p, struct netif *inp);
+
+void icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t);
+void icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t);
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct icmp_echo_hdr {
+  PACK_STRUCT_FIELD(u16_t _type_code);
+  PACK_STRUCT_FIELD(u16_t chksum);
+  PACK_STRUCT_FIELD(u16_t id);
+  PACK_STRUCT_FIELD(u16_t seqno);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+
+PACK_STRUCT_BEGIN
+struct icmp_dur_hdr {
+  PACK_STRUCT_FIELD(u16_t _type_code);
+  PACK_STRUCT_FIELD(u16_t chksum);
+  PACK_STRUCT_FIELD(u32_t unused);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+
+PACK_STRUCT_BEGIN
+struct icmp_te_hdr {
+  PACK_STRUCT_FIELD(u16_t _type_code);
+  PACK_STRUCT_FIELD(u16_t chksum);
+  PACK_STRUCT_FIELD(u32_t unused);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define ICMPH_TYPE(hdr) (ntohs((hdr)->_type_code) >> 8)
+#define ICMPH_CODE(hdr) (ntohs((hdr)->_type_code) & 0xff)
+
+#define ICMPH_TYPE_SET(hdr, type) ((hdr)->_type_code = htons(ICMPH_CODE(hdr) | ((type) << 8)))
+#define ICMPH_CODE_SET(hdr, code) ((hdr)->_type_code = htons((code) | (ICMPH_TYPE(hdr) << 8)))
+
+#endif /* __LWIP_ICMP_H__ */
+    
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv4/lwip/inet.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv4/lwip/inet.h
new file mode 100644
index 000000000..21463accf
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv4/lwip/inet.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_INET_H__
+#define __LWIP_INET_H__
+
+#include "lwip/arch.h"
+
+#include "lwip/opt.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+
+u16_t inet_chksum(void *dataptr, u16_t len);
+u16_t inet_chksum_pbuf(struct pbuf *p);
+u16_t inet_chksum_pseudo(struct pbuf *p,
+       struct ip_addr *src, struct ip_addr *dest,
+       u8_t proto, u16_t proto_len);
+
+u32_t inet_addr(const char *cp);
+int inet_aton(const char *cp, struct in_addr *addr);
+char *inet_ntoa(struct in_addr addr); /* returns ptr to static buffer; not reentrant! */
+
+#ifdef htons
+#undef htons
+#endif /* htons */
+#ifdef htonl
+#undef htonl
+#endif /* htonl */
+#ifdef ntohs
+#undef ntohs
+#endif /* ntohs */
+#ifdef ntohl
+#undef ntohl
+#endif /* ntohl */
+
+#if BYTE_ORDER == BIG_ENDIAN
+#define htons(x) (x)
+#define ntohs(x) (x)
+#define htonl(x) (x)
+#define ntohl(x) (x)
+#else
+#ifdef LWIP_PREFIX_BYTEORDER_FUNCS
+/* workaround for naming collisions on some platforms */
+#define htons lwip_htons
+#define ntohs lwip_ntohs
+#define htonl lwip_htonl
+#define ntohl lwip_ntohl
+#endif
+u16_t htons(u16_t x);
+u16_t ntohs(u16_t x);
+u32_t htonl(u32_t x);
+u32_t ntohl(u32_t x);
+#endif
+
+#endif /* __LWIP_INET_H__ */
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv4/lwip/ip.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv4/lwip/ip.h
new file mode 100644
index 000000000..34ca7a8fc
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv4/lwip/ip.h
@@ -0,0 +1,154 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_IP_H__
+#define __LWIP_IP_H__
+
+#include "lwip/arch.h"
+
+#include "lwip/def.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+
+#include "lwip/err.h"
+
+
+void ip_init(void);
+struct netif *ip_route(struct ip_addr *dest);
+err_t ip_input(struct pbuf *p, struct netif *inp);
+err_t ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+		u8_t ttl, u8_t tos, u8_t proto);
+err_t ip_output_if(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+		   u8_t ttl, u8_t tos, u8_t proto,
+       struct netif *netif);
+
+#define IP_HLEN 20
+
+#define IP_PROTO_ICMP 1
+#define IP_PROTO_UDP 17
+#define IP_PROTO_UDPLITE 170
+#define IP_PROTO_TCP 6
+
+/* This is passed as the destination address to ip_output_if (not
+   to ip_output), meaning that an IP header already is constructed
+   in the pbuf. This is used when TCP retransmits. */
+#ifdef IP_HDRINCL
+#undef IP_HDRINCL
+#endif /* IP_HDRINCL */
+#define IP_HDRINCL  NULL
+
+
+/* This is the common part of all PCB types. It needs to be at the
+   beginning of a PCB type definition. It is located here so that
+   changes to this common part are made in one location instead of
+   having to change all PCB structs. */
+#define IP_PCB struct ip_addr local_ip; \
+  struct ip_addr remote_ip; \
+   /* Socket options */  \
+  u16_t so_options;      \
+   /* Type Of Service */ \
+  u8_t tos;              \
+  /* Time To Live */     \
+  u8_t ttl
+
+/*
+ * Option flags per-socket. These are the same like SO_XXX.
+ */
+#define	SOF_DEBUG	    (u16_t)0x0001U		/* turn on debugging info recording */
+#define	SOF_ACCEPTCONN	(u16_t)0x0002U		/* socket has had listen() */
+#define	SOF_REUSEADDR	(u16_t)0x0004U		/* allow local address reuse */
+#define	SOF_KEEPALIVE	(u16_t)0x0008U		/* keep connections alive */
+#define	SOF_DONTROUTE	(u16_t)0x0010U		/* just use interface addresses */
+#define	SOF_BROADCAST	(u16_t)0x0020U		/* permit sending of broadcast msgs */
+#define	SOF_USELOOPBACK	(u16_t)0x0040U		/* bypass hardware when possible */
+#define	SOF_LINGER	    (u16_t)0x0080U		/* linger on close if data present */
+#define	SOF_OOBINLINE	(u16_t)0x0100U		/* leave received OOB data in line */
+#define	SOF_REUSEPORT	(u16_t)0x0200U		/* allow local address & port reuse */
+
+
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip_hdr {
+  /* version / header length / type of service */
+  PACK_STRUCT_FIELD(u16_t _v_hl_tos);
+  /* total length */
+  PACK_STRUCT_FIELD(u16_t _len);
+  /* identification */
+  PACK_STRUCT_FIELD(u16_t _id);
+  /* fragment offset field */
+  PACK_STRUCT_FIELD(u16_t _offset);
+#define IP_RF 0x8000        /* reserved fragment flag */
+#define IP_DF 0x4000        /* dont fragment flag */
+#define IP_MF 0x2000        /* more fragments flag */
+#define IP_OFFMASK 0x1fff   /* mask for fragmenting bits */
+  /* time to live / protocol*/
+  PACK_STRUCT_FIELD(u16_t _ttl_proto);
+  /* checksum */
+  PACK_STRUCT_FIELD(u16_t _chksum);
+  /* source and destination IP addresses */
+  PACK_STRUCT_FIELD(struct ip_addr src);
+  PACK_STRUCT_FIELD(struct ip_addr dest); 
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define IPH_V(hdr)  (ntohs((hdr)->_v_hl_tos) >> 12)
+#define IPH_HL(hdr) ((ntohs((hdr)->_v_hl_tos) >> 8) & 0x0f)
+#define IPH_TOS(hdr) (ntohs((hdr)->_v_hl_tos) & 0xff)
+#define IPH_LEN(hdr) ((hdr)->_len)
+#define IPH_ID(hdr) ((hdr)->_id)
+#define IPH_OFFSET(hdr) ((hdr)->_offset)
+#define IPH_TTL(hdr) (ntohs((hdr)->_ttl_proto) >> 8)
+#define IPH_PROTO(hdr) (ntohs((hdr)->_ttl_proto) & 0xff)
+#define IPH_CHKSUM(hdr) ((hdr)->_chksum)
+
+#define IPH_VHLTOS_SET(hdr, v, hl, tos) (hdr)->_v_hl_tos = (htons(((v) << 12) | ((hl) << 8) | (tos)))
+#define IPH_LEN_SET(hdr, len) (hdr)->_len = (len)
+#define IPH_ID_SET(hdr, id) (hdr)->_id = (id)
+#define IPH_OFFSET_SET(hdr, off) (hdr)->_offset = (off)
+#define IPH_TTL_SET(hdr, ttl) (hdr)->_ttl_proto = (htons(IPH_PROTO(hdr) | ((ttl) << 8)))
+#define IPH_PROTO_SET(hdr, proto) (hdr)->_ttl_proto = (htons((proto) | (IPH_TTL(hdr) << 8)))
+#define IPH_CHKSUM_SET(hdr, chksum) (hdr)->_chksum = (chksum)
+
+#if IP_DEBUG
+void ip_debug_print(struct pbuf *p);
+#else
+#define ip_debug_print(p)
+#endif /* IP_DEBUG */
+
+#endif /* __LWIP_IP_H__ */
+
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv4/lwip/ip_addr.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv4/lwip/ip_addr.h
new file mode 100644
index 000000000..2fe12f7d8
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv4/lwip/ip_addr.h
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_IP_ADDR_H__
+#define __LWIP_IP_ADDR_H__
+
+#include "lwip/arch.h"
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip_addr {
+  PACK_STRUCT_FIELD(u32_t addr);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip_addr2 {
+  PACK_STRUCT_FIELD(u16_t addrw[2]);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/* For compatibility with BSD code */
+struct in_addr {
+  u32_t s_addr;
+};
+
+struct netif;
+
+extern const struct ip_addr ip_addr_any;
+extern const struct ip_addr ip_addr_broadcast;
+
+/** IP_ADDR_ can be used as a fixed IP address
+ *  for the wildcard and the broadcast address
+ */
+#define IP_ADDR_ANY ((struct ip_addr *)&ip_addr_any)
+#define IP_ADDR_BROADCAST ((struct ip_addr *)&ip_addr_broadcast)
+
+#define INADDR_NONE    ((u32_t) 0xffffffff)  /* 255.255.255.255 */
+#define INADDR_LOOPBACK    ((u32_t) 0x7f000001)  /* 127.0.0.1 */
+
+/* Definitions of the bits in an Internet address integer.
+
+   On subnets, host and network parts are found according to
+   the subnet mask, not these masks.  */
+
+#define  IN_CLASSA(a)    ((((u32_t)(a)) & 0x80000000) == 0)
+#define  IN_CLASSA_NET    0xff000000
+#define  IN_CLASSA_NSHIFT  24
+#define  IN_CLASSA_HOST    (0xffffffff & ~IN_CLASSA_NET)
+#define  IN_CLASSA_MAX    128
+
+#define  IN_CLASSB(a)    ((((u32_t)(a)) & 0xc0000000) == 0x80000000)
+#define  IN_CLASSB_NET    0xffff0000
+#define  IN_CLASSB_NSHIFT  16
+#define  IN_CLASSB_HOST    (0xffffffff & ~IN_CLASSB_NET)
+#define  IN_CLASSB_MAX    65536
+
+#define  IN_CLASSC(a)    ((((u32_t)(a)) & 0xe0000000) == 0xc0000000)
+#define  IN_CLASSC_NET    0xffffff00
+#define  IN_CLASSC_NSHIFT  8
+#define  IN_CLASSC_HOST    (0xffffffff & ~IN_CLASSC_NET)
+
+#define IN_CLASSD(a)        (((u32_t)(a) & 0xf0000000) == 0xe0000000)
+#define IN_CLASSD_NET       0xf0000000  /* These ones aren't really */
+#define IN_CLASSD_NSHIFT    28      /* net and host fields, but */
+#define IN_CLASSD_HOST      0x0fffffff  /* routing needn't know.    */
+#define IN_MULTICAST(a)     IN_CLASSD(a)
+
+#define IN_EXPERIMENTAL(a)  (((u32_t)(a) & 0xf0000000) == 0xf0000000)
+#define IN_BADCLASS(a)      (((u32_t)(a) & 0xf0000000) == 0xf0000000)
+
+#define IN_LOOPBACKNET      127         /* official! */
+
+
+#define IP4_ADDR(ipaddr, a,b,c,d) (ipaddr)->addr = htonl(((u32_t)(a & 0xff) << 24) | ((u32_t)(b & 0xff) << 16) | \
+                                                         ((u32_t)(c & 0xff) << 8) | (u32_t)(d & 0xff))
+
+#define ip_addr_set(dest, src) (dest)->addr = \
+                               ((src) == NULL? 0:\
+                               (src)->addr)
+/**
+ * Determine if two address are on the same network.
+ *
+ * @arg addr1 IP address 1
+ * @arg addr2 IP address 2
+ * @arg mask network identifier mask
+ * @return !0 if the network identifiers of both address match
+ */
+#define ip_addr_netcmp(addr1, addr2, mask) (((addr1)->addr & \
+                                              (mask)->addr) == \
+                                             ((addr2)->addr & \
+                                              (mask)->addr))
+#define ip_addr_cmp(addr1, addr2) ((addr1)->addr == (addr2)->addr)
+
+#define ip_addr_isany(addr1) ((addr1) == NULL || (addr1)->addr == 0)
+
+u8_t ip_addr_isbroadcast(struct ip_addr *, struct netif *);
+
+#define ip_addr_ismulticast(addr1) (((addr1)->addr & ntohl(0xf0000000)) == ntohl(0xe0000000))
+
+
+#define ip_addr_debug_print(debug, ipaddr) LWIP_DEBUGF(debug, ("%u.%u.%u.%u", \
+        ipaddr?(unsigned int)(ntohl((ipaddr)->addr) >> 24) & 0xff:0, \
+        ipaddr?(unsigned int)(ntohl((ipaddr)->addr) >> 16) & 0xff:0, \
+        ipaddr?(unsigned int)(ntohl((ipaddr)->addr) >> 8) & 0xff:0, \
+        ipaddr?(unsigned int)ntohl((ipaddr)->addr) & 0xff:0U))
+
+/* cast to unsigned int, as it is used as argument to printf functions
+ * which expect integer arguments */
+#define ip4_addr1(ipaddr) ((unsigned int)(ntohl((ipaddr)->addr) >> 24) & 0xff)
+#define ip4_addr2(ipaddr) ((unsigned int)(ntohl((ipaddr)->addr) >> 16) & 0xff)
+#define ip4_addr3(ipaddr) ((unsigned int)(ntohl((ipaddr)->addr) >> 8) & 0xff)
+#define ip4_addr4(ipaddr) ((unsigned int)(ntohl((ipaddr)->addr)) & 0xff)
+#endif /* __LWIP_IP_ADDR_H__ */
+
+
+
+
+
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv4/lwip/ip_frag.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv4/lwip/ip_frag.h
new file mode 100644
index 000000000..ea4d2c497
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv4/lwip/ip_frag.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Jani Monoses 
+ *
+ */
+
+#ifndef __LWIP_IP_FRAG_H__
+#define __LWIP_IP_FRAG_H__
+
+#include "lwip/err.h"
+#include "lwip/pbuf.h"
+#include "lwip/netif.h"
+#include "lwip/ip_addr.h"
+
+struct pbuf * ip_reass(struct pbuf *);
+err_t ip_frag(struct pbuf *, struct netif *, struct ip_addr *);
+
+#endif /* __LWIP_IP_FRAG_H__ */
+
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv6/lwip/icmp.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv6/lwip/icmp.h
new file mode 100644
index 000000000..9c63a3f45
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv6/lwip/icmp.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_ICMP_H__
+#define __LWIP_ICMP_H__
+
+#include "lwip/arch.h"
+
+#include "lwip/opt.h"
+#include "lwip/pbuf.h"
+
+#include "lwip/netif.h"
+
+#define ICMP6_DUR  1
+#define ICMP6_TE   3
+#define ICMP6_ECHO 128    /* echo */
+#define ICMP6_ER   129      /* echo reply */
+
+
+enum icmp_dur_type {
+  ICMP_DUR_NET = 0,    /* net unreachable */
+  ICMP_DUR_HOST = 1,   /* host unreachable */
+  ICMP_DUR_PROTO = 2,  /* protocol unreachable */
+  ICMP_DUR_PORT = 3,   /* port unreachable */
+  ICMP_DUR_FRAG = 4,   /* fragmentation needed and DF set */
+  ICMP_DUR_SR = 5      /* source route failed */
+};
+
+enum icmp_te_type {
+  ICMP_TE_TTL = 0,     /* time to live exceeded in transit */
+  ICMP_TE_FRAG = 1     /* fragment reassembly time exceeded */
+};
+
+void icmp_input(struct pbuf *p, struct netif *inp);
+
+void icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t);
+void icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t);
+
+struct icmp_echo_hdr {
+  u8_t type;
+  u8_t icode;
+  u16_t chksum;
+  u16_t id;
+  u16_t seqno;
+};
+
+struct icmp_dur_hdr {
+  u8_t type;
+  u8_t icode;
+  u16_t chksum;
+  u32_t unused;
+};
+
+struct icmp_te_hdr {
+  u8_t type;
+  u8_t icode;
+  u16_t chksum;
+  u32_t unused;
+};
+
+#endif /* __LWIP_ICMP_H__ */
+    
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv6/lwip/inet.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv6/lwip/inet.h
new file mode 100644
index 000000000..b13ce57b7
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv6/lwip/inet.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_INET_H__
+#define __LWIP_INET_H__
+
+#include "lwip/arch.h"
+
+#include "lwip/opt.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+
+u16_t inet_chksum(void *data, u16_t len);
+u16_t inet_chksum_pbuf(struct pbuf *p);
+u16_t inet_chksum_pseudo(struct pbuf *p,
+       struct ip_addr *src, struct ip_addr *dest,
+       u8_t proto, u32_t proto_len);
+
+u32_t inet_addr(const char *cp);
+int inet_aton(const char *cp, struct in_addr *addr);
+
+#ifndef _MACHINE_ENDIAN_H_
+#ifndef _NETINET_IN_H
+#ifndef _LINUX_BYTEORDER_GENERIC_H
+u16_t htons(u16_t n);
+u16_t ntohs(u16_t n);
+u32_t htonl(u32_t n);
+u32_t ntohl(u32_t n);
+#endif /* _LINUX_BYTEORDER_GENERIC_H */
+#endif /* _NETINET_IN_H */
+#endif /* _MACHINE_ENDIAN_H_ */
+
+#endif /* __LWIP_INET_H__ */
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv6/lwip/ip.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv6/lwip/ip.h
new file mode 100644
index 000000000..6c4c50960
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv6/lwip/ip.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_IP_H__
+#define __LWIP_IP_H__
+
+#include "lwip/opt.h"
+#include "lwip/def.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+
+#include "lwip/err.h"
+
+#define IP_HLEN 40
+
+#define IP_PROTO_ICMP 58
+#define IP_PROTO_UDP 17
+#define IP_PROTO_UDPLITE 170
+#define IP_PROTO_TCP 6
+
+/* This is passed as the destination address to ip_output_if (not
+   to ip_output), meaning that an IP header already is constructed
+   in the pbuf. This is used when TCP retransmits. */
+#ifdef IP_HDRINCL
+#undef IP_HDRINCL
+#endif /* IP_HDRINCL */
+#define IP_HDRINCL  NULL
+
+
+/* The IPv6 header. */
+struct ip_hdr {
+#if BYTE_ORDER == LITTLE_ENDIAN
+  u8_t tclass1:4, v:4;
+  u8_t flow1:4, tclass2:4;  
+#else
+  u8_t v:4, tclass1:4;
+  u8_t tclass2:8, flow1:4;
+#endif
+  u16_t flow2;
+  u16_t len;                /* payload length */
+  u8_t nexthdr;             /* next header */
+  u8_t hoplim;              /* hop limit (TTL) */
+  struct ip_addr src, dest;          /* source and destination IP addresses */
+};
+
+void ip_init(void);
+
+#include "lwip/netif.h"
+
+struct netif *ip_route(struct ip_addr *dest);
+
+void ip_input(struct pbuf *p, struct netif *inp);
+
+/* source and destination addresses in network byte order, please */
+err_t ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+         unsigned char ttl, unsigned char proto);
+
+err_t ip_output_if(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+      unsigned char ttl, unsigned char proto,
+      struct netif *netif);
+
+#if IP_DEBUG
+void ip_debug_print(struct pbuf *p);
+#endif /* IP_DEBUG */
+
+#endif /* __LWIP_IP_H__ */
+
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv6/lwip/ip_addr.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv6/lwip/ip_addr.h
new file mode 100644
index 000000000..d3937d36a
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv6/lwip/ip_addr.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_IP_ADDR_H__
+#define __LWIP_IP_ADDR_H__
+
+#include "lwip/arch.h"
+
+#define IP_ADDR_ANY 0
+
+struct ip_addr {
+  u32_t addr[4];
+};
+
+#define IP6_ADDR(ipaddr, a,b,c,d,e,f,g,h) do { (ipaddr)->addr[0] = htonl((u32_t)((a & 0xffff) << 16) | (b & 0xffff)); \
+                                               (ipaddr)->addr[1] = htonl(((c & 0xffff) << 16) | (d & 0xffff)); \
+                                               (ipaddr)->addr[2] = htonl(((e & 0xffff) << 16) | (f & 0xffff)); \
+                                               (ipaddr)->addr[3] = htonl(((g & 0xffff) << 16) | (h & 0xffff)); } while(0)
+
+int ip_addr_netcmp(struct ip_addr *addr1, struct ip_addr *addr2,
+        struct ip_addr *mask);
+int ip_addr_cmp(struct ip_addr *addr1, struct ip_addr *addr2);
+void ip_addr_set(struct ip_addr *dest, struct ip_addr *src);
+int ip_addr_isany(struct ip_addr *addr);
+
+
+#if IP_DEBUG
+void ip_addr_debug_print(struct ip_addr *addr);
+#endif /* IP_DEBUG */
+
+#endif /* __LWIP_IP_ADDR_H__ */
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/api.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/api.h
new file mode 100644
index 000000000..1059eca2e
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/api.h
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_API_H__
+#define __LWIP_API_H__
+
+#include "lwip/opt.h"
+#include "lwip/pbuf.h"
+#include "lwip/sys.h"
+
+#include "lwip/ip.h"
+
+#include "lwip/raw.h"
+#include "lwip/udp.h"
+#include "lwip/tcp.h"
+
+#include "lwip/err.h"
+
+#define NETCONN_NOCOPY 0x00
+#define NETCONN_COPY   0x01
+
+enum netconn_type {
+  NETCONN_TCP,
+  NETCONN_UDP,
+  NETCONN_UDPLITE,
+  NETCONN_UDPNOCHKSUM,
+  NETCONN_RAW
+};
+
+enum netconn_state {
+  NETCONN_NONE,
+  NETCONN_WRITE,
+  NETCONN_ACCEPT,
+  NETCONN_RECV,
+  NETCONN_CONNECT,
+  NETCONN_CLOSE
+};
+
+enum netconn_evt {
+  NETCONN_EVT_RCVPLUS,
+  NETCONN_EVT_RCVMINUS,
+  NETCONN_EVT_SENDPLUS,
+  NETCONN_EVT_SENDMINUS
+};
+
+struct netbuf {
+  struct pbuf *p, *ptr;
+  struct ip_addr *fromaddr;
+  u16_t fromport;
+  err_t err;
+};
+
+struct netconn {
+  enum netconn_type type;
+  enum netconn_state state;
+  union {
+    struct tcp_pcb *tcp;
+    struct udp_pcb *udp;
+    struct raw_pcb *raw;
+  } pcb;
+  err_t err;
+  sys_mbox_t mbox;
+  sys_mbox_t recvmbox;
+  sys_mbox_t acceptmbox;
+  sys_sem_t sem;
+  int socket;
+  u16_t recv_avail;
+  void (* callback)(struct netconn *, enum netconn_evt, u16_t len);
+};
+
+/* Network buffer functions: */
+struct netbuf *   netbuf_new      (void);
+void              netbuf_delete   (struct netbuf *buf);
+void *            netbuf_alloc    (struct netbuf *buf, u16_t size);
+void              netbuf_free     (struct netbuf *buf);
+void              netbuf_ref      (struct netbuf *buf,
+           void *dataptr, u16_t size);
+void              netbuf_chain    (struct netbuf *head,
+           struct netbuf *tail);
+
+u16_t             netbuf_len      (struct netbuf *buf);
+err_t             netbuf_data     (struct netbuf *buf,
+           void **dataptr, u16_t *len);
+s8_t              netbuf_next     (struct netbuf *buf);
+void              netbuf_first    (struct netbuf *buf);
+
+void              netbuf_copy     (struct netbuf *buf,
+           void *dataptr, u16_t len);
+void              netbuf_copy_partial(struct netbuf *buf, void *dataptr, 
+              u16_t len, u16_t offset);
+struct ip_addr *  netbuf_fromaddr (struct netbuf *buf);
+u16_t             netbuf_fromport (struct netbuf *buf);
+
+/* Network connection functions: */
+struct netconn *  netconn_new     (enum netconn_type type);
+struct
+netconn *netconn_new_with_callback(enum netconn_type t,
+                                   void (*callback)(struct netconn *, enum netconn_evt, u16_t len));
+struct
+netconn *netconn_new_with_proto_and_callback(enum netconn_type t, u16_t proto,
+                                   void (*callback)(struct netconn *, enum netconn_evt, u16_t len));
+err_t             netconn_delete  (struct netconn *conn);
+enum netconn_type netconn_type    (struct netconn *conn);
+err_t             netconn_peer    (struct netconn *conn,
+           struct ip_addr *addr,
+           u16_t *port);
+err_t             netconn_addr    (struct netconn *conn,
+           struct ip_addr **addr,
+           u16_t *port);
+err_t             netconn_bind    (struct netconn *conn,
+           struct ip_addr *addr,
+           u16_t port);
+err_t             netconn_connect (struct netconn *conn,
+           struct ip_addr *addr,
+           u16_t port);
+err_t             netconn_disconnect (struct netconn *conn);
+err_t             netconn_listen  (struct netconn *conn);
+struct netconn *  netconn_accept  (struct netconn *conn);
+struct netbuf *   netconn_recv    (struct netconn *conn);
+err_t             netconn_send    (struct netconn *conn,
+           struct netbuf *buf);
+err_t             netconn_write   (struct netconn *conn,
+           void *dataptr, u16_t size,
+           u8_t copy);
+err_t             netconn_close   (struct netconn *conn);
+
+err_t             netconn_err     (struct netconn *conn);
+
+#endif /* __LWIP_API_H__ */
+
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/api_msg.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/api_msg.h
new file mode 100644
index 000000000..3ed585c44
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/api_msg.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_API_MSG_H__
+#define __LWIP_API_MSG_H__
+
+#include "lwip/opt.h"
+#include "lwip/pbuf.h"
+#include "lwip/sys.h"
+
+#include "lwip/ip.h"
+
+#include "lwip/udp.h"
+#include "lwip/tcp.h"
+
+#include "lwip/api.h"
+
+enum api_msg_type {
+  API_MSG_NEWCONN,
+  API_MSG_DELCONN,
+  
+  API_MSG_BIND,
+  API_MSG_CONNECT,
+  API_MSG_DISCONNECT,
+
+  API_MSG_LISTEN,
+  API_MSG_ACCEPT,
+
+  API_MSG_SEND,
+  API_MSG_RECV,
+  API_MSG_WRITE,
+
+  API_MSG_CLOSE,
+  
+  API_MSG_MAX
+};
+
+struct api_msg_msg {
+  struct netconn *conn;
+  enum netconn_type conntype;
+  union {
+    struct pbuf *p;   
+    struct  {
+      struct ip_addr *ipaddr;
+      u16_t port;
+    } bc;
+    struct {
+      void *dataptr;
+      u16_t len;
+      unsigned char copy;
+    } w;    
+    sys_mbox_t mbox;
+    u16_t len;
+  } msg;
+};
+
+struct api_msg {
+  enum api_msg_type type;
+  struct api_msg_msg msg;
+};
+
+void api_msg_input(struct api_msg *msg);
+void api_msg_post(struct api_msg *msg);
+
+#endif /* __LWIP_API_MSG_H__ */
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/arch.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/arch.h
new file mode 100644
index 000000000..f5e10513f
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/arch.h
@@ -0,0 +1,216 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_ARCH_H__
+#define __LWIP_ARCH_H__
+
+#ifndef LITTLE_ENDIAN
+#define LITTLE_ENDIAN 1234
+#endif
+
+#ifndef BIG_ENDIAN
+#define BIG_ENDIAN 4321
+#endif
+
+#include "arch/cc.h"
+
+#ifndef PACK_STRUCT_BEGIN
+#define PACK_STRUCT_BEGIN
+#endif /* PACK_STRUCT_BEGIN */
+
+#ifndef PACK_STRUCT_END
+#define PACK_STRUCT_END
+#endif /* PACK_STRUCT_END */
+
+#ifndef PACK_STRUCT_FIELD
+#define PACK_STRUCT_FIELD(x) x
+#endif /* PACK_STRUCT_FIELD */
+
+
+
+#ifdef LWIP_PROVIDE_ERRNO
+
+#define  EPERM     1  /* Operation not permitted */
+#define  ENOENT     2  /* No such file or directory */
+#define  ESRCH     3  /* No such process */
+#define  EINTR     4  /* Interrupted system call */
+#define  EIO     5  /* I/O error */
+#define  ENXIO     6  /* No such device or address */
+#define  E2BIG     7  /* Arg list too long */
+#define  ENOEXEC     8  /* Exec format error */
+#define  EBADF     9  /* Bad file number */
+#define  ECHILD    10  /* No child processes */
+#define  EAGAIN    11  /* Try again */
+#define  ENOMEM    12  /* Out of memory */
+#define  EACCES    13  /* Permission denied */
+#define  EFAULT    14  /* Bad address */
+#define  ENOTBLK    15  /* Block device required */
+#define  EBUSY    16  /* Device or resource busy */
+#define  EEXIST    17  /* File exists */
+#define  EXDEV    18  /* Cross-device link */
+#define  ENODEV    19  /* No such device */
+#define  ENOTDIR    20  /* Not a directory */
+#define  EISDIR    21  /* Is a directory */
+#define  EINVAL    22  /* Invalid argument */
+#define  ENFILE    23  /* File table overflow */
+#define  EMFILE    24  /* Too many open files */
+#define  ENOTTY    25  /* Not a typewriter */
+#define  ETXTBSY    26  /* Text file busy */
+#define  EFBIG    27  /* File too large */
+#define  ENOSPC    28  /* No space left on device */
+#define  ESPIPE    29  /* Illegal seek */
+#define  EROFS    30  /* Read-only file system */
+#define  EMLINK    31  /* Too many links */
+#define  EPIPE    32  /* Broken pipe */
+#define  EDOM    33  /* Math argument out of domain of func */
+#define  ERANGE    34  /* Math result not representable */
+#define  EDEADLK    35  /* Resource deadlock would occur */
+#define  ENAMETOOLONG  36  /* File name too long */
+#define  ENOLCK    37  /* No record locks available */
+#define  ENOSYS    38  /* Function not implemented */
+#define  ENOTEMPTY  39  /* Directory not empty */
+#define  ELOOP    40  /* Too many symbolic links encountered */
+#define  EWOULDBLOCK  EAGAIN  /* Operation would block */
+#define  ENOMSG    42  /* No message of desired type */
+#define  EIDRM    43  /* Identifier removed */
+#define  ECHRNG    44  /* Channel number out of range */
+#define  EL2NSYNC  45  /* Level 2 not synchronized */
+#define  EL3HLT    46  /* Level 3 halted */
+#define  EL3RST    47  /* Level 3 reset */
+#define  ELNRNG    48  /* Link number out of range */
+#define  EUNATCH    49  /* Protocol driver not attached */
+#define  ENOCSI    50  /* No CSI structure available */
+#define  EL2HLT    51  /* Level 2 halted */
+#define  EBADE    52  /* Invalid exchange */
+#define  EBADR    53  /* Invalid request descriptor */
+#define  EXFULL    54  /* Exchange full */
+#define  ENOANO    55  /* No anode */
+#define  EBADRQC    56  /* Invalid request code */
+#define  EBADSLT    57  /* Invalid slot */
+
+#define  EDEADLOCK  EDEADLK
+
+#define  EBFONT    59  /* Bad font file format */
+#define  ENOSTR    60  /* Device not a stream */
+#define  ENODATA    61  /* No data available */
+#define  ETIME    62  /* Timer expired */
+#define  ENOSR    63  /* Out of streams resources */
+#define  ENONET    64  /* Machine is not on the network */
+#define  ENOPKG    65  /* Package not installed */
+#define  EREMOTE    66  /* Object is remote */
+#define  ENOLINK    67  /* Link has been severed */
+#define  EADV    68  /* Advertise error */
+#define  ESRMNT    69  /* Srmount error */
+#define  ECOMM    70  /* Communication error on send */
+#define  EPROTO    71  /* Protocol error */
+#define  EMULTIHOP  72  /* Multihop attempted */
+#define  EDOTDOT    73  /* RFS specific error */
+#define  EBADMSG    74  /* Not a data message */
+#define  EOVERFLOW  75  /* Value too large for defined data type */
+#define  ENOTUNIQ  76  /* Name not unique on network */
+#define  EBADFD    77  /* File descriptor in bad state */
+#define  EREMCHG    78  /* Remote address changed */
+#define  ELIBACC    79  /* Can not access a needed shared library */
+#define  ELIBBAD    80  /* Accessing a corrupted shared library */
+#define  ELIBSCN    81  /* .lib section in a.out corrupted */
+#define  ELIBMAX    82  /* Attempting to link in too many shared libraries */
+#define  ELIBEXEC  83  /* Cannot exec a shared library directly */
+#define  EILSEQ    84  /* Illegal byte sequence */
+#define  ERESTART  85  /* Interrupted system call should be restarted */
+#define  ESTRPIPE  86  /* Streams pipe error */
+#define  EUSERS    87  /* Too many users */
+#define  ENOTSOCK  88  /* Socket operation on non-socket */
+#define  EDESTADDRREQ  89  /* Destination address required */
+#define  EMSGSIZE  90  /* Message too long */
+#define  EPROTOTYPE  91  /* Protocol wrong type for socket */
+#define  ENOPROTOOPT  92  /* Protocol not available */
+#define  EPROTONOSUPPORT  93  /* Protocol not supported */
+#define  ESOCKTNOSUPPORT  94  /* Socket type not supported */
+#define  EOPNOTSUPP  95  /* Operation not supported on transport endpoint */
+#define  EPFNOSUPPORT  96  /* Protocol family not supported */
+#define  EAFNOSUPPORT  97  /* Address family not supported by protocol */
+#define  EADDRINUSE  98  /* Address already in use */
+#define  EADDRNOTAVAIL  99  /* Cannot assign requested address */
+#define  ENETDOWN  100  /* Network is down */
+#define  ENETUNREACH  101  /* Network is unreachable */
+#define  ENETRESET  102  /* Network dropped connection because of reset */
+#define  ECONNABORTED  103  /* Software caused connection abort */
+#define  ECONNRESET  104  /* Connection reset by peer */
+#define  ENOBUFS    105  /* No buffer space available */
+#define  EISCONN    106  /* Transport endpoint is already connected */
+#define  ENOTCONN  107  /* Transport endpoint is not connected */
+#define  ESHUTDOWN  108  /* Cannot send after transport endpoint shutdown */
+#define  ETOOMANYREFS  109  /* Too many references: cannot splice */
+#define  ETIMEDOUT  110  /* Connection timed out */
+#define  ECONNREFUSED  111  /* Connection refused */
+#define  EHOSTDOWN  112  /* Host is down */
+#define  EHOSTUNREACH  113  /* No route to host */
+#define  EALREADY  114  /* Operation already in progress */
+#define  EINPROGRESS  115  /* Operation now in progress */
+#define  ESTALE    116  /* Stale NFS file handle */
+#define  EUCLEAN    117  /* Structure needs cleaning */
+#define  ENOTNAM    118  /* Not a XENIX named type file */
+#define  ENAVAIL    119  /* No XENIX semaphores available */
+#define  EISNAM    120  /* Is a named type file */
+#define  EREMOTEIO  121  /* Remote I/O error */
+#define  EDQUOT    122  /* Quota exceeded */
+
+#define  ENOMEDIUM  123  /* No medium found */
+#define  EMEDIUMTYPE  124  /* Wrong medium type */
+
+
+#define	ENSROK		0	/* DNS server returned answer with no data */
+#define	ENSRNODATA	160	/* DNS server returned answer with no data */
+#define	ENSRFORMERR	161	/* DNS server claims query was misformatted */
+#define	ENSRSERVFAIL 162	/* DNS server returned general failure */
+#define	ENSRNOTFOUND 163	/* Domain name not found */
+#define	ENSRNOTIMP	164	/* DNS server does not implement requested operation */
+#define	ENSRREFUSED	165	/* DNS server refused query */
+#define	ENSRBADQUERY 166	/* Misformatted DNS query */
+#define	ENSRBADNAME	167	/* Misformatted domain name */
+#define	ENSRBADFAMILY 168	/* Unsupported address family */
+#define	ENSRBADRESP	169	/* Misformatted DNS reply */
+#define	ENSRCONNREFUSED	170	/* Could not contact DNS servers */
+#define	ENSRTIMEOUT	171	/* Timeout while contacting DNS servers */
+#define	ENSROF		172	/* End of file */
+#define	ENSRFILE	173	/* Error reading file */
+#define	ENSRNOMEM	174	/* Out of memory */
+#define	ENSRDESTRUCTION	175	/* Application terminated lookup */
+#define	ENSRQUERYDOMAINTOOLONG	176	/* Domain name is too long */
+#define	ENSRCNAMELOOP	177	/* Domain name is too long */
+
+#ifndef errno
+extern int errno;
+#endif
+
+#endif /* LWIP_PROVIDE_ERRNO */
+
+#endif /* __LWIP_ARCH_H__ */
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/debug.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/debug.h
new file mode 100644
index 000000000..eb9eda7fe
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/debug.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_DEBUG_H__
+#define __LWIP_DEBUG_H__
+
+#include "arch/cc.h"
+
+/** lower two bits indicate debug level
+ * - 0 off
+ * - 1 warning
+ * - 2 serious
+ * - 3 severe
+ */
+
+#define DBG_LEVEL_OFF     0
+#define DBG_LEVEL_WARNING 1  /* bad checksums, dropped packets, ... */
+#define DBG_LEVEL_SERIOUS 2  /* memory allocation failures, ... */
+#define DBG_LEVEL_SEVERE  3  /* */ 
+#define DBG_MASK_LEVEL    3
+
+/** flag for LWIP_DEBUGF to enable that debug message */
+#define DBG_ON  0x80U
+/** flag for LWIP_DEBUGF to disable that debug message */
+#define DBG_OFF 0x00U
+
+/** flag for LWIP_DEBUGF indicating a tracing message (to follow program flow) */
+#define DBG_TRACE   0x40U
+/** flag for LWIP_DEBUGF indicating a state debug message (to follow module states) */
+#define DBG_STATE   0x20U
+/** flag for LWIP_DEBUGF indicating newly added code, not thoroughly tested yet */
+#define DBG_FRESH   0x10U
+/** flag for LWIP_DEBUGF to halt after printing this debug message */
+#define DBG_HALT    0x08U
+
+#ifndef LWIP_NOASSERT
+#  define LWIP_ASSERT(x,y) do { if(!(y)) LWIP_PLATFORM_ASSERT(x); } while(0)
+#else
+#  define LWIP_ASSERT(x,y) 
+#endif
+
+#ifdef LWIP_DEBUG
+/** print debug message only if debug message type is enabled...
+ *  AND is of correct type AND is at least DBG_LEVEL
+ */
+#  define LWIP_DEBUGF(debug,x) do { if (((debug) & DBG_ON) && ((debug) & DBG_TYPES_ON) && ((int)((debug) & DBG_MASK_LEVEL) >= DBG_MIN_LEVEL)) { LWIP_PLATFORM_DIAG(x); if ((debug) & DBG_HALT) while(1); } } while(0)
+#  define LWIP_ERROR(x)   do { LWIP_PLATFORM_DIAG(x); } while(0)  
+#else /* LWIP_DEBUG */
+#  define LWIP_DEBUGF(debug,x) 
+#  define LWIP_ERROR(x)  
+#endif /* LWIP_DEBUG */
+
+#endif /* __LWIP_DEBUG_H__ */
+
+
+
+
+
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/def.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/def.h
new file mode 100644
index 000000000..f26bdd040
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/def.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_DEF_H__
+#define __LWIP_DEF_H__
+
+/* this might define NULL already */
+#include "arch/cc.h"
+
+#define LWIP_MAX(x , y)  (x) > (y) ? (x) : (y)
+#define LWIP_MIN(x , y)  (x) < (y) ? (x) : (y)
+
+#ifndef NULL
+#define NULL ((void *)0)
+#endif
+
+
+#endif /* __LWIP_DEF_H__ */
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/dhcp.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/dhcp.h
new file mode 100644
index 000000000..df51bdc96
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/dhcp.h
@@ -0,0 +1,223 @@
+/** @file
+ */
+
+#ifndef __LWIP_DHCP_H__
+#define __LWIP_DHCP_H__
+
+#include "lwip/opt.h"
+#include "lwip/netif.h"
+#include "lwip/udp.h"
+
+/** period (in seconds) of the application calling dhcp_coarse_tmr() */
+#define DHCP_COARSE_TIMER_SECS 60 
+/** period (in milliseconds) of the application calling dhcp_fine_tmr() */
+#define DHCP_FINE_TIMER_MSECS 500 
+
+struct dhcp
+{
+  /** current DHCP state machine state */
+  u8_t state;
+  /** retries of current request */
+  u8_t tries;
+  /** transaction identifier of last sent request */ 
+  u32_t xid;
+  /** our connection to the DHCP server */ 
+  struct udp_pcb *pcb;
+  /** (first) pbuf of incoming msg */
+  struct pbuf *p;
+  /** incoming msg */
+  struct dhcp_msg *msg_in;
+  /** incoming msg options */
+  struct dhcp_msg *options_in; 
+  /** ingoing msg options length */
+  u16_t options_in_len;
+
+  struct pbuf *p_out; /* pbuf of outcoming msg */
+  struct dhcp_msg *msg_out; /* outgoing msg */
+  u16_t options_out_len; /* outgoing msg options length */
+  u16_t request_timeout; /* #ticks with period DHCP_FINE_TIMER_SECS for request timeout */
+  u16_t t1_timeout;  /* #ticks with period DHCP_COARSE_TIMER_SECS for renewal time */
+  u16_t t2_timeout;  /* #ticks with period DHCP_COARSE_TIMER_SECS for rebind time */
+  struct ip_addr server_ip_addr; /* dhcp server address that offered this lease */
+  struct ip_addr offered_ip_addr;
+  struct ip_addr offered_sn_mask;
+  struct ip_addr offered_gw_addr;
+  struct ip_addr offered_bc_addr;
+#define DHCP_MAX_DNS 2
+  u32_t dns_count; /* actual number of DNS servers obtained */
+  struct ip_addr offered_dns_addr[DHCP_MAX_DNS]; /* DNS server addresses */
+ 
+  u32_t offered_t0_lease; /* lease period (in seconds) */
+  u32_t offered_t1_renew; /* recommended renew time (usually 50% of lease period) */
+  u32_t offered_t2_rebind; /* recommended rebind time (usually 66% of lease period)  */
+/** Patch #1308
+ *  TODO: See dhcp.c "TODO"s
+ */
+#if 0
+  struct ip_addr offered_si_addr;
+  u8_t *boot_file_name;
+#endif
+};
+
+/* MUST be compiled with "pack structs" or equivalent! */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+/** minimum set of fields of any DHCP message */
+struct dhcp_msg
+{
+  PACK_STRUCT_FIELD(u8_t op);
+  PACK_STRUCT_FIELD(u8_t htype);
+  PACK_STRUCT_FIELD(u8_t hlen);
+  PACK_STRUCT_FIELD(u8_t hops);
+  PACK_STRUCT_FIELD(u32_t xid);
+  PACK_STRUCT_FIELD(u16_t secs);
+  PACK_STRUCT_FIELD(u16_t flags);
+  PACK_STRUCT_FIELD(struct ip_addr ciaddr);
+  PACK_STRUCT_FIELD(struct ip_addr yiaddr);
+  PACK_STRUCT_FIELD(struct ip_addr siaddr);
+  PACK_STRUCT_FIELD(struct ip_addr giaddr);
+#define DHCP_CHADDR_LEN 16U
+  PACK_STRUCT_FIELD(u8_t chaddr[DHCP_CHADDR_LEN]);
+#define DHCP_SNAME_LEN 64U
+  PACK_STRUCT_FIELD(u8_t sname[DHCP_SNAME_LEN]);
+#define DHCP_FILE_LEN 128U
+  PACK_STRUCT_FIELD(u8_t file[DHCP_FILE_LEN]);
+  PACK_STRUCT_FIELD(u32_t cookie);
+#define DHCP_MIN_OPTIONS_LEN 68U
+/** make sure user does not configure this too small */
+#if ((defined(DHCP_OPTIONS_LEN)) && (DHCP_OPTIONS_LEN < DHCP_MIN_OPTIONS_LEN))
+#  undef DHCP_OPTIONS_LEN
+#endif
+/** allow this to be configured in lwipopts.h, but not too small */
+#if (!defined(DHCP_OPTIONS_LEN))
+/** set this to be sufficient for your options in outgoing DHCP msgs */
+#  define DHCP_OPTIONS_LEN DHCP_MIN_OPTIONS_LEN
+#endif
+  PACK_STRUCT_FIELD(u8_t options[DHCP_OPTIONS_LEN]);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/** start DHCP configuration */
+err_t dhcp_start(struct netif *netif);
+/** enforce early lease renewal (not needed normally)*/
+err_t dhcp_renew(struct netif *netif);
+/** release the DHCP lease, usually called before dhcp_stop()*/
+err_t dhcp_release(struct netif *netif);
+/** stop DHCP configuration */
+void dhcp_stop(struct netif *netif);
+/** inform server of our manual IP address */
+void dhcp_inform(struct netif *netif);
+
+/** if enabled, check whether the offered IP address is not in use, using ARP */
+#if DHCP_DOES_ARP_CHECK
+void dhcp_arp_reply(struct netif *netif, struct ip_addr *addr);
+#endif
+
+/** to be called every minute */
+void dhcp_coarse_tmr(void);
+/** to be called every half second */
+void dhcp_fine_tmr(void);
+ 
+/** DHCP message item offsets and length */
+#define DHCP_MSG_OFS (UDP_DATA_OFS)  
+  #define DHCP_OP_OFS (DHCP_MSG_OFS + 0)
+  #define DHCP_HTYPE_OFS (DHCP_MSG_OFS + 1)
+  #define DHCP_HLEN_OFS (DHCP_MSG_OFS + 2)
+  #define DHCP_HOPS_OFS (DHCP_MSG_OFS + 3)
+  #define DHCP_XID_OFS (DHCP_MSG_OFS + 4)
+  #define DHCP_SECS_OFS (DHCP_MSG_OFS + 8)
+  #define DHCP_FLAGS_OFS (DHCP_MSG_OFS + 10)
+  #define DHCP_CIADDR_OFS (DHCP_MSG_OFS + 12)
+  #define DHCP_YIADDR_OFS (DHCP_MSG_OFS + 16)
+  #define DHCP_SIADDR_OFS (DHCP_MSG_OFS + 20)
+  #define DHCP_GIADDR_OFS (DHCP_MSG_OFS + 24)
+  #define DHCP_CHADDR_OFS (DHCP_MSG_OFS + 28)
+  #define DHCP_SNAME_OFS (DHCP_MSG_OFS + 44)
+  #define DHCP_FILE_OFS (DHCP_MSG_OFS + 108)
+#define DHCP_MSG_LEN 236
+
+#define DHCP_COOKIE_OFS (DHCP_MSG_OFS + DHCP_MSG_LEN)
+#define DHCP_OPTIONS_OFS (DHCP_MSG_OFS + DHCP_MSG_LEN + 4)
+
+#define DHCP_CLIENT_PORT 68  
+#define DHCP_SERVER_PORT 67
+
+/** DHCP client states */
+#define DHCP_REQUESTING 1
+#define DHCP_INIT 2
+#define DHCP_REBOOTING 3
+#define DHCP_REBINDING 4
+#define DHCP_RENEWING 5
+#define DHCP_SELECTING 6
+#define DHCP_INFORMING 7
+#define DHCP_CHECKING 8
+#define DHCP_PERMANENT 9
+#define DHCP_BOUND 10
+/** not yet implemented #define DHCP_RELEASING 11 */
+#define DHCP_BACKING_OFF 12
+#define DHCP_OFF 13
+ 
+#define DHCP_BOOTREQUEST 1
+#define DHCP_BOOTREPLY 2
+
+#define DHCP_DISCOVER 1
+#define DHCP_OFFER 2
+#define DHCP_REQUEST 3
+#define DHCP_DECLINE 4
+#define DHCP_ACK 5
+#define DHCP_NAK 6
+#define DHCP_RELEASE 7
+#define DHCP_INFORM 8
+
+#define DHCP_HTYPE_ETH 1
+
+#define DHCP_HLEN_ETH 6
+
+#define DHCP_BROADCAST_FLAG 15
+#define DHCP_BROADCAST_MASK (1 << DHCP_FLAG_BROADCAST)
+
+/** BootP options */
+#define DHCP_OPTION_PAD 0
+#define DHCP_OPTION_SUBNET_MASK 1 /* RFC 2132 3.3 */
+#define DHCP_OPTION_ROUTER 3
+#define DHCP_OPTION_DNS_SERVER 6 
+#define DHCP_OPTION_HOSTNAME 12
+#define DHCP_OPTION_IP_TTL 23
+#define DHCP_OPTION_MTU 26
+#define DHCP_OPTION_BROADCAST 28
+#define DHCP_OPTION_TCP_TTL 37
+#define DHCP_OPTION_END 255
+
+/** DHCP options */
+#define DHCP_OPTION_REQUESTED_IP 50 /* RFC 2132 9.1, requested IP address */
+#define DHCP_OPTION_LEASE_TIME 51 /* RFC 2132 9.2, time in seconds, in 4 bytes */
+#define DHCP_OPTION_OVERLOAD 52 /* RFC2132 9.3, use file and/or sname field for options */
+
+#define DHCP_OPTION_MESSAGE_TYPE 53 /* RFC 2132 9.6, important for DHCP */
+#define DHCP_OPTION_MESSAGE_TYPE_LEN 1
+
+
+#define DHCP_OPTION_SERVER_ID 54 /* RFC 2132 9.7, server IP address */
+#define DHCP_OPTION_PARAMETER_REQUEST_LIST 55 /* RFC 2132 9.8, requested option types */
+
+#define DHCP_OPTION_MAX_MSG_SIZE 57 /* RFC 2132 9.10, message size accepted >= 576 */
+#define DHCP_OPTION_MAX_MSG_SIZE_LEN 2
+
+#define DHCP_OPTION_T1 58 /* T1 renewal time */
+#define DHCP_OPTION_T2 59 /* T2 rebinding time */
+#define DHCP_OPTION_CLIENT_ID 61
+#define DHCP_OPTION_TFTP_SERVERNAME 66
+#define DHCP_OPTION_BOOTFILE 67
+
+/** possible combinations of overloading the file and sname fields with options */
+#define DHCP_OVERLOAD_NONE 0
+#define DHCP_OVERLOAD_FILE 1
+#define DHCP_OVERLOAD_SNAME  2
+#define DHCP_OVERLOAD_SNAME_FILE 3
+
+#endif /*__LWIP_DHCP_H__*/
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/err.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/err.h
new file mode 100644
index 000000000..fc90f2eab
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/err.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_ERR_H__
+#define __LWIP_ERR_H__
+
+#include "lwip/opt.h"
+
+#include "arch/cc.h"
+
+typedef s8_t err_t;
+
+/* Definitions for error constants. */
+
+#define ERR_OK    0      /* No error, everything OK. */
+#define ERR_MEM  -1      /* Out of memory error.     */
+#define ERR_BUF  -2      /* Buffer error.            */
+
+
+#define ERR_ABRT -3      /* Connection aborted.      */
+#define ERR_RST  -4      /* Connection reset.        */
+#define ERR_CLSD -5      /* Connection closed.       */
+#define ERR_CONN -6      /* Not connected.           */
+
+#define ERR_VAL  -7      /* Illegal value.           */
+
+#define ERR_ARG  -8      /* Illegal argument.        */
+
+#define ERR_RTE  -9      /* Routing problem.         */
+
+#define ERR_USE  -10     /* Address in use.          */
+
+#define ERR_IF   -11     /* Low-level netif error    */
+#define ERR_ISCONN -12   /* Already connected.       */
+
+
+#ifdef LWIP_DEBUG
+extern char *lwip_strerr(err_t err);
+#else
+#define lwip_strerr(x) ""
+#endif /* LWIP_DEBUG */
+#endif /* __LWIP_ERR_H__ */
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/mem.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/mem.h
new file mode 100644
index 000000000..b88ea9c8d
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/mem.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_MEM_H__
+#define __LWIP_MEM_H__
+
+#include "lwip/opt.h"
+#include "lwip/arch.h"
+
+#if MEM_SIZE > 64000l
+typedef u32_t mem_size_t;
+#else
+typedef u16_t mem_size_t;
+#endif /* MEM_SIZE > 64000 */
+
+
+void mem_init(void);
+
+void *mem_malloc(mem_size_t size);
+void mem_free(void *mem);
+void *mem_realloc(void *mem, mem_size_t size);
+void *mem_reallocm(void *mem, mem_size_t size);
+
+#ifndef MEM_ALIGN_SIZE
+#define MEM_ALIGN_SIZE(size) (((size) + MEM_ALIGNMENT - 1) & ~(MEM_ALIGNMENT-1))
+#endif
+
+#ifndef MEM_ALIGN
+#define MEM_ALIGN(addr) ((void *)(((mem_ptr_t)(addr) + MEM_ALIGNMENT - 1) & ~(mem_ptr_t)(MEM_ALIGNMENT-1)))
+#endif
+
+#endif /* __LWIP_MEM_H__ */
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/memp.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/memp.h
new file mode 100644
index 000000000..6da033f27
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/memp.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#ifndef __LWIP_MEMP_H__
+#define __LWIP_MEMP_H__
+
+#include "lwip/opt.h"
+
+typedef enum {
+  MEMP_PBUF,
+  MEMP_RAW_PCB,
+  MEMP_UDP_PCB,
+  MEMP_TCP_PCB,
+  MEMP_TCP_PCB_LISTEN,
+  MEMP_TCP_SEG,
+
+  MEMP_NETBUF,
+  MEMP_NETCONN,
+  MEMP_API_MSG,
+  MEMP_TCPIP_MSG,
+
+  MEMP_SYS_TIMEOUT,
+  
+  MEMP_MAX
+} memp_t;
+
+void memp_init(void);
+
+void *memp_malloc(memp_t type);
+void *memp_realloc(memp_t fromtype, memp_t totype, void *mem);
+void memp_free(memp_t type, void *mem);
+
+#endif /* __LWIP_MEMP_H__  */
+    
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/netif.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/netif.h
new file mode 100644
index 000000000..d4a18ffbe
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/netif.h
@@ -0,0 +1,150 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_NETIF_H__
+#define __LWIP_NETIF_H__
+
+#include "lwip/opt.h"
+
+#include "lwip/err.h"
+
+#include "lwip/ip_addr.h"
+
+#include "lwip/inet.h"
+#include "lwip/pbuf.h"
+#if LWIP_DHCP
+#  include "lwip/dhcp.h"
+#endif
+
+/** must be the maximum of all used hardware address lengths
+    across all types of interfaces in use */
+#define NETIF_MAX_HWADDR_LEN 6U
+
+/** TODO: define the use (where, when, whom) of netif flags */
+
+/** whether the network interface is 'up'. this is
+ * a software flag used to control whether this network
+ * interface is enabled and processes traffic.
+ */
+#define NETIF_FLAG_UP 0x1U
+/** if set, the netif has broadcast capability */
+#define NETIF_FLAG_BROADCAST 0x2U
+/** if set, the netif is one end of a point-to-point connection */
+#define NETIF_FLAG_POINTTOPOINT 0x4U
+/** if set, the interface is configured using DHCP */
+#define NETIF_FLAG_DHCP 0x08U
+/** if set, the interface has an active link
+ *  (set by the network interface driver) */
+#define NETIF_FLAG_LINK_UP 0x10U
+
+/** Generic data structure used for all lwIP network interfaces.
+ *  The following fields should be filled in by the initialization
+ *  function for the device driver: hwaddr_len, hwaddr[], mtu, flags */
+
+struct netif {
+  /** pointer to next in linked list */
+  struct netif *next;
+
+  /** IP address configuration in network byte order */
+  struct ip_addr ip_addr;
+  struct ip_addr netmask;
+  struct ip_addr gw;
+
+  /** This function is called by the network device driver
+   *  to pass a packet up the TCP/IP stack. */
+  err_t (* input)(struct pbuf *p, struct netif *inp);
+  /** This function is called by the IP module when it wants
+   *  to send a packet on the interface. This function typically
+   *  first resolves the hardware address, then sends the packet. */
+  err_t (* output)(struct netif *netif, struct pbuf *p,
+       struct ip_addr *ipaddr);
+  /** This function is called by the ARP module when it wants
+   *  to send a packet on the interface. This function outputs
+   *  the pbuf as-is on the link medium. */
+  err_t (* linkoutput)(struct netif *netif, struct pbuf *p);
+  /** This field can be set by the device driver and could point
+   *  to state information for the device. */
+  void *state;
+#if LWIP_DHCP
+  /** the DHCP client state information for this netif */
+  struct dhcp *dhcp;
+#endif
+  /** number of bytes used in hwaddr */
+  unsigned char hwaddr_len;
+  /** link level hardware address of this interface */
+  unsigned char hwaddr[NETIF_MAX_HWADDR_LEN];
+  /** maximum transfer unit (in bytes) */
+  u16_t mtu;
+  /** flags (see NETIF_FLAG_ above) */
+  u8_t flags;
+  /** link type */
+  u8_t link_type;
+  /** descriptive abbreviation */
+  char name[2];
+  /** number of this interface */
+  u8_t num;
+};
+
+/** The list of network interfaces. */
+extern struct netif *netif_list;
+/** The default network interface. */
+extern struct netif *netif_default;
+
+/* netif_init() must be called first. */
+void netif_init(void);
+
+struct netif *netif_add(struct netif *netif, struct ip_addr *ipaddr, struct ip_addr *netmask,
+      struct ip_addr *gw,
+      void *state,
+      err_t (* init)(struct netif *netif),
+      err_t (* input)(struct pbuf *p, struct netif *netif));
+
+void
+netif_set_addr(struct netif *netif,struct ip_addr *ipaddr, struct ip_addr *netmask,
+    struct ip_addr *gw);
+void netif_remove(struct netif * netif);
+
+/* Returns a network interface given its name. The name is of the form
+   "et0", where the first two letters are the "name" field in the
+   netif structure, and the digit is in the num field in the same
+   structure. */
+struct netif *netif_find(char *name);
+
+void netif_set_default(struct netif *netif);
+
+void netif_set_ipaddr(struct netif *netif, struct ip_addr *ipaddr);
+void netif_set_netmask(struct netif *netif, struct ip_addr *netmast);
+void netif_set_gw(struct netif *netif, struct ip_addr *gw);
+void netif_set_up(struct netif *netif);
+void netif_set_down(struct netif *netif);
+u8_t netif_is_up(struct netif *netif);
+
+#endif /* __LWIP_NETIF_H__ */
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/opt.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/opt.h
new file mode 100644
index 000000000..f8c18221e
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/opt.h
@@ -0,0 +1,669 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_OPT_H__
+#define __LWIP_OPT_H__
+
+/* Include user defined options first */
+#include "lwipopts.h"
+#include "lwip/debug.h"
+
+/* Define default values for unconfigured parameters. */
+
+/* Platform specific locking */
+
+/*
+ * enable SYS_LIGHTWEIGHT_PROT in lwipopts.h if you want inter-task protection
+ * for certain critical regions during buffer allocation, deallocation and memory
+ * allocation and deallocation.
+ */
+#ifndef SYS_LIGHTWEIGHT_PROT
+#define SYS_LIGHTWEIGHT_PROT            0
+#endif
+
+#ifndef NO_SYS
+#define NO_SYS                          0
+#endif
+/* ---------- Memory options ---------- */
+/* MEM_ALIGNMENT: should be set to the alignment of the CPU for which
+   lwIP is compiled. 4 byte alignment -> define MEM_ALIGNMENT to 4, 2
+   byte alignment -> define MEM_ALIGNMENT to 2. */
+
+#ifndef MEM_ALIGNMENT
+#define MEM_ALIGNMENT                   1
+#endif
+
+/* MEM_SIZE: the size of the heap memory. If the application will send
+a lot of data that needs to be copied, this should be set high. */
+#ifndef MEM_SIZE
+#define MEM_SIZE                        1600
+#endif
+
+#ifndef MEMP_SANITY_CHECK
+#define MEMP_SANITY_CHECK		0
+#endif
+
+/* MEMP_NUM_PBUF: the number of memp struct pbufs. If the application
+   sends a lot of data out of ROM (or other static memory), this
+   should be set high. */
+#ifndef MEMP_NUM_PBUF
+#define MEMP_NUM_PBUF                   16
+#endif
+
+/* Number of raw connection PCBs */
+#ifndef MEMP_NUM_RAW_PCB
+#define MEMP_NUM_RAW_PCB                4
+#endif
+
+/* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One
+   per active UDP "connection". */
+#ifndef MEMP_NUM_UDP_PCB
+#define MEMP_NUM_UDP_PCB                4
+#endif
+/* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP
+   connections. */
+#ifndef MEMP_NUM_TCP_PCB
+#define MEMP_NUM_TCP_PCB                5
+#endif
+/* MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP
+   connections. */
+#ifndef MEMP_NUM_TCP_PCB_LISTEN
+#define MEMP_NUM_TCP_PCB_LISTEN         8
+#endif
+/* MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP
+   segments. */
+#ifndef MEMP_NUM_TCP_SEG
+#define MEMP_NUM_TCP_SEG                16
+#endif
+/* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active
+   timeouts. */
+#ifndef MEMP_NUM_SYS_TIMEOUT
+#define MEMP_NUM_SYS_TIMEOUT            3
+#endif
+
+/* The following four are used only with the sequential API and can be
+   set to 0 if the application only will use the raw API. */
+/* MEMP_NUM_NETBUF: the number of struct netbufs. */
+#ifndef MEMP_NUM_NETBUF
+#define MEMP_NUM_NETBUF                 2
+#endif
+/* MEMP_NUM_NETCONN: the number of struct netconns. */
+#ifndef MEMP_NUM_NETCONN
+#define MEMP_NUM_NETCONN                4
+#endif
+/* MEMP_NUM_APIMSG: the number of struct api_msg, used for
+   communication between the TCP/IP stack and the sequential
+   programs. */
+#ifndef MEMP_NUM_API_MSG
+#define MEMP_NUM_API_MSG                8
+#endif
+/* MEMP_NUM_TCPIPMSG: the number of struct tcpip_msg, which is used
+   for sequential API communication and incoming packets. Used in
+   src/api/tcpip.c. */
+#ifndef MEMP_NUM_TCPIP_MSG
+#define MEMP_NUM_TCPIP_MSG              8
+#endif
+
+/* ---------- Pbuf options ---------- */
+/* PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */
+
+#ifndef PBUF_POOL_SIZE
+#define PBUF_POOL_SIZE                  16
+#endif
+
+/* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */
+
+#ifndef PBUF_POOL_BUFSIZE
+#define PBUF_POOL_BUFSIZE               128
+#endif
+
+/* PBUF_LINK_HLEN: the number of bytes that should be allocated for a
+   link level header. Defaults to 14 for Ethernet. */
+
+#ifndef PBUF_LINK_HLEN
+#define PBUF_LINK_HLEN                  14
+#endif
+
+
+
+/* ---------- ARP options ---------- */
+
+/** Number of active hardware address, IP address pairs cached */
+#ifndef ARP_TABLE_SIZE
+#define ARP_TABLE_SIZE                  10
+#endif
+
+/**
+ * If enabled, outgoing packets are queued during hardware address
+ * resolution.
+ *
+ * This feature has not stabilized yet. Single-packet queueing is
+ * believed to be stable, multi-packet queueing is believed to
+ * clash with the TCP segment queueing.
+ * 
+ * As multi-packet-queueing is currently disabled, enabling this
+ * _should_ work, but we need your testing feedback on lwip-users.
+ *
+ */
+#ifndef ARP_QUEUEING
+#define ARP_QUEUEING                    1
+#endif
+
+/* This option is deprecated */
+#ifdef ETHARP_QUEUE_FIRST
+#error ETHARP_QUEUE_FIRST option is deprecated. Remove it from your lwipopts.h.
+#endif
+
+/* This option is removed to comply with the ARP standard */
+#ifdef ETHARP_ALWAYS_INSERT
+#error ETHARP_ALWAYS_INSERT option is deprecated. Remove it from your lwipopts.h.
+#endif
+
+/* ---------- IP options ---------- */
+/* Define IP_FORWARD to 1 if you wish to have the ability to forward
+   IP packets across network interfaces. If you are going to run lwIP
+   on a device with only one network interface, define this to 0. */
+#ifndef IP_FORWARD
+#define IP_FORWARD                      0
+#endif
+
+/* If defined to 1, IP options are allowed (but not parsed). If
+   defined to 0, all packets with IP options are dropped. */
+#ifndef IP_OPTIONS
+#define IP_OPTIONS                      1
+#endif
+
+/** IP reassembly and segmentation. Even if they both deal with IP
+ *  fragments, note that these are orthogonal, one dealing with incoming
+ *  packets, the other with outgoing packets
+ */
+
+/** Reassemble incoming fragmented IP packets */
+#ifndef IP_REASSEMBLY
+#define IP_REASSEMBLY                   1
+#endif
+
+/** Fragment outgoing IP packets if their size exceeds MTU */
+#ifndef IP_FRAG
+#define IP_FRAG                         1
+#endif
+
+/* ---------- ICMP options ---------- */
+
+#ifndef ICMP_TTL
+#define ICMP_TTL                        255
+#endif
+
+/* ---------- RAW options ---------- */
+
+#ifndef LWIP_RAW
+#define LWIP_RAW                        1
+#endif
+
+#ifndef RAW_TTL
+#define RAW_TTL                        255
+#endif
+
+/* ---------- DHCP options ---------- */
+
+#ifndef LWIP_DHCP
+#define LWIP_DHCP                       0
+#endif
+
+/* 1 if you want to do an ARP check on the offered address
+   (recommended). */
+#ifndef DHCP_DOES_ARP_CHECK
+#define DHCP_DOES_ARP_CHECK             1
+#endif
+
+/* ---------- UDP options ---------- */
+#ifndef LWIP_UDP
+#define LWIP_UDP                        1
+#endif
+
+#ifndef UDP_TTL
+#define UDP_TTL                         255
+#endif
+
+/* ---------- TCP options ---------- */
+#ifndef LWIP_TCP
+#define LWIP_TCP                        1
+#endif
+
+#ifndef TCP_TTL
+#define TCP_TTL                         255
+#endif
+
+#ifndef TCP_WND
+#define TCP_WND                         2048
+#endif 
+
+#ifndef TCP_MAXRTX
+#define TCP_MAXRTX                      12
+#endif
+
+#ifndef TCP_SYNMAXRTX
+#define TCP_SYNMAXRTX                   6
+#endif
+
+
+/* Controls if TCP should queue segments that arrive out of
+   order. Define to 0 if your device is low on memory. */
+#ifndef TCP_QUEUE_OOSEQ
+#define TCP_QUEUE_OOSEQ                 1
+#endif
+
+/* TCP Maximum segment size. */
+#ifndef TCP_MSS
+#define TCP_MSS                         128 /* A *very* conservative default. */
+#endif
+
+/* TCP sender buffer space (bytes). */
+#ifndef TCP_SND_BUF
+#define TCP_SND_BUF                     256
+#endif
+
+/* TCP sender buffer space (pbufs). This must be at least = 2 *
+   TCP_SND_BUF/TCP_MSS for things to work. */
+#ifndef TCP_SND_QUEUELEN
+#define TCP_SND_QUEUELEN                4 * TCP_SND_BUF/TCP_MSS
+#endif
+
+
+/* Maximum number of retransmissions of data segments. */
+
+/* Maximum number of retransmissions of SYN segments. */
+
+/* TCP writable space (bytes). This must be less than or equal
+   to TCP_SND_BUF. It is the amount of space which must be
+   available in the tcp snd_buf for select to return writable */
+#ifndef TCP_SNDLOWAT
+#define TCP_SNDLOWAT                    TCP_SND_BUF/2
+#endif
+
+/* Support loop interface (127.0.0.1) */
+#ifndef LWIP_HAVE_LOOPIF
+#define LWIP_HAVE_LOOPIF		1
+#endif
+
+#ifndef LWIP_EVENT_API
+#define LWIP_EVENT_API                  0
+#define LWIP_CALLBACK_API               1
+#else 
+#define LWIP_EVENT_API                  1
+#define LWIP_CALLBACK_API               0
+#endif 
+
+#ifndef LWIP_COMPAT_SOCKETS
+#define LWIP_COMPAT_SOCKETS             1
+#endif
+
+
+#ifndef TCPIP_THREAD_PRIO
+#define TCPIP_THREAD_PRIO               1
+#endif
+
+#ifndef SLIPIF_THREAD_PRIO
+#define SLIPIF_THREAD_PRIO              1
+#endif
+
+#ifndef PPP_THREAD_PRIO
+#define PPP_THREAD_PRIO                 1
+#endif
+
+#ifndef DEFAULT_THREAD_PRIO
+#define DEFAULT_THREAD_PRIO             1
+#endif
+
+
+/* ---------- Socket Options ---------- */
+/* Enable SO_REUSEADDR and SO_REUSEPORT options */ 
+#ifndef SO_REUSE
+# define SO_REUSE 0
+#endif                                                                        
+
+
+/* ---------- Statistics options ---------- */
+#ifndef LWIP_STATS
+#define LWIP_STATS                      1
+#endif
+
+#if LWIP_STATS
+
+#ifndef LWIP_STATS_DISPLAY
+#define LWIP_STATS_DISPLAY 0
+#endif
+
+#ifndef LINK_STATS
+#define LINK_STATS	1
+#endif
+
+#ifndef IP_STATS
+#define IP_STATS	1
+#endif
+
+#ifndef IPFRAG_STATS
+#define IPFRAG_STATS	1
+#endif
+
+#ifndef ICMP_STATS
+#define ICMP_STATS	1
+#endif
+
+#ifndef UDP_STATS
+#define UDP_STATS	1
+#endif
+
+#ifndef TCP_STATS
+#define TCP_STATS	1
+#endif
+
+#ifndef MEM_STATS
+#define MEM_STATS	1
+#endif
+
+#ifndef MEMP_STATS
+#define MEMP_STATS	1
+#endif
+
+#ifndef PBUF_STATS
+#define PBUF_STATS	1
+#endif
+
+#ifndef SYS_STATS
+#define SYS_STATS	1
+#endif
+
+#ifndef RAW_STATS
+#define RAW_STATS	0
+#endif
+
+#else
+
+#define LINK_STATS	0
+#define IP_STATS	0
+#define IPFRAG_STATS	0
+#define ICMP_STATS	0
+#define UDP_STATS	0
+#define TCP_STATS	0
+#define MEM_STATS	0
+#define MEMP_STATS	0
+#define PBUF_STATS	0
+#define SYS_STATS	0
+#define RAW_STATS	0
+#define LWIP_STATS_DISPLAY	0
+
+#endif /* LWIP_STATS */
+
+/* ---------- PPP options ---------- */
+
+#ifndef PPP_SUPPORT
+#define PPP_SUPPORT                     0      /* Set for PPP */
+#endif
+
+#if PPP_SUPPORT 
+
+#define NUM_PPP                         1      /* Max PPP sessions. */
+
+
+
+#ifndef PAP_SUPPORT
+#define PAP_SUPPORT                     0      /* Set for PAP. */
+#endif
+
+#ifndef CHAP_SUPPORT
+#define CHAP_SUPPORT                    0      /* Set for CHAP. */
+#endif
+
+#define MSCHAP_SUPPORT                  0      /* Set for MSCHAP (NOT FUNCTIONAL!) */
+#define CBCP_SUPPORT                    0      /* Set for CBCP (NOT FUNCTIONAL!) */
+#define CCP_SUPPORT                     0      /* Set for CCP (NOT FUNCTIONAL!) */
+
+#ifndef VJ_SUPPORT
+#define VJ_SUPPORT                      0      /* Set for VJ header compression. */
+#endif
+
+#ifndef MD5_SUPPORT
+#define MD5_SUPPORT                     0      /* Set for MD5 (see also CHAP) */
+#endif
+
+
+/*
+ * Timeouts.
+ */
+#define FSM_DEFTIMEOUT                  6       /* Timeout time in seconds */
+#define FSM_DEFMAXTERMREQS              2       /* Maximum Terminate-Request transmissions */
+#define FSM_DEFMAXCONFREQS              10      /* Maximum Configure-Request transmissions */
+#define FSM_DEFMAXNAKLOOPS              5       /* Maximum number of nak loops */
+
+#define UPAP_DEFTIMEOUT                 6       /* Timeout (seconds) for retransmitting req */
+#define UPAP_DEFREQTIME                 30      /* Time to wait for auth-req from peer */
+
+#define CHAP_DEFTIMEOUT                 6       /* Timeout time in seconds */
+#define CHAP_DEFTRANSMITS               10      /* max # times to send challenge */
+
+
+/* Interval in seconds between keepalive echo requests, 0 to disable. */
+#if 1
+#define LCP_ECHOINTERVAL                0
+#else
+#define LCP_ECHOINTERVAL                10
+#endif
+
+/* Number of unanswered echo requests before failure. */
+#define LCP_MAXECHOFAILS                3
+
+/* Max Xmit idle time (in jiffies) before resend flag char. */
+#define PPP_MAXIDLEFLAG                 100
+
+/*
+ * Packet sizes
+ *
+ * Note - lcp shouldn't be allowed to negotiate stuff outside these
+ *    limits.  See lcp.h in the pppd directory.
+ * (XXX - these constants should simply be shared by lcp.c instead
+ *    of living in lcp.h)
+ */
+#define PPP_MTU                         1500     /* Default MTU (size of Info field) */
+#if 0
+#define PPP_MAXMTU  65535 - (PPP_HDRLEN + PPP_FCSLEN)
+#else
+#define PPP_MAXMTU                      1500 /* Largest MTU we allow */
+#endif
+#define PPP_MINMTU                      64
+#define PPP_MRU                         1500     /* default MRU = max length of info field */
+#define PPP_MAXMRU                      1500     /* Largest MRU we allow */
+#define PPP_DEFMRU                      296             /* Try for this */
+#define PPP_MINMRU                      128             /* No MRUs below this */
+
+
+#define MAXNAMELEN                      256     /* max length of hostname or name for auth */
+#define MAXSECRETLEN                    256     /* max length of password or secret */
+
+#endif /* PPP_SUPPORT */
+
+/* checksum options - set to zero for hardware checksum support */
+
+#ifndef CHECKSUM_GEN_IP
+#define CHECKSUM_GEN_IP                 1
+#endif
+ 
+#ifndef CHECKSUM_GEN_UDP
+#define CHECKSUM_GEN_UDP                1
+#endif
+ 
+#ifndef CHECKSUM_GEN_TCP
+#define CHECKSUM_GEN_TCP                1
+#endif
+ 
+#ifndef CHECKSUM_CHECK_IP
+#define CHECKSUM_CHECK_IP               1
+#endif
+ 
+#ifndef CHECKSUM_CHECK_UDP
+#define CHECKSUM_CHECK_UDP              1
+#endif
+
+#ifndef CHECKSUM_CHECK_TCP
+#define CHECKSUM_CHECK_TCP              1
+#endif
+
+/* Debugging options all default to off */
+
+#ifndef DBG_TYPES_ON
+#define DBG_TYPES_ON                    0
+#endif
+
+#ifndef ETHARP_DEBUG
+#define ETHARP_DEBUG                    DBG_OFF
+#endif
+
+#ifndef NETIF_DEBUG
+#define NETIF_DEBUG                     DBG_OFF
+#endif
+
+#ifndef PBUF_DEBUG
+#define PBUF_DEBUG                      DBG_OFF
+#endif
+
+#ifndef API_LIB_DEBUG
+#define API_LIB_DEBUG                   DBG_OFF
+#endif
+
+#ifndef API_MSG_DEBUG
+#define API_MSG_DEBUG                   DBG_OFF
+#endif
+
+#ifndef SOCKETS_DEBUG
+#define SOCKETS_DEBUG                   DBG_OFF
+#endif
+
+#ifndef ICMP_DEBUG
+#define ICMP_DEBUG                      DBG_OFF
+#endif
+
+#ifndef INET_DEBUG
+#define INET_DEBUG                      DBG_OFF
+#endif
+
+#ifndef IP_DEBUG
+#define IP_DEBUG                        DBG_OFF
+#endif
+
+#ifndef IP_REASS_DEBUG
+#define IP_REASS_DEBUG                  DBG_OFF
+#endif
+
+#ifndef RAW_DEBUG
+#define RAW_DEBUG                       DBG_OFF
+#endif
+
+#ifndef MEM_DEBUG
+#define MEM_DEBUG                       DBG_OFF
+#endif
+
+#ifndef MEMP_DEBUG
+#define MEMP_DEBUG                      DBG_OFF
+#endif
+
+#ifndef SYS_DEBUG
+#define SYS_DEBUG                       DBG_OFF
+#endif
+
+#ifndef TCP_DEBUG
+#define TCP_DEBUG                       DBG_OFF
+#endif
+
+#ifndef TCP_INPUT_DEBUG
+#define TCP_INPUT_DEBUG                 DBG_OFF
+#endif
+
+#ifndef TCP_FR_DEBUG
+#define TCP_FR_DEBUG                    DBG_OFF
+#endif
+
+#ifndef TCP_RTO_DEBUG
+#define TCP_RTO_DEBUG                   DBG_OFF
+#endif
+
+#ifndef TCP_REXMIT_DEBUG
+#define TCP_REXMIT_DEBUG                DBG_OFF
+#endif
+
+#ifndef TCP_CWND_DEBUG
+#define TCP_CWND_DEBUG                  DBG_OFF
+#endif
+
+#ifndef TCP_WND_DEBUG
+#define TCP_WND_DEBUG                   DBG_OFF
+#endif
+
+#ifndef TCP_OUTPUT_DEBUG
+#define TCP_OUTPUT_DEBUG                DBG_OFF
+#endif
+
+#ifndef TCP_RST_DEBUG
+#define TCP_RST_DEBUG                   DBG_OFF
+#endif
+
+#ifndef TCP_QLEN_DEBUG
+#define TCP_QLEN_DEBUG                  DBG_OFF
+#endif
+
+#ifndef UDP_DEBUG
+#define UDP_DEBUG                       DBG_OFF
+#endif
+
+#ifndef TCPIP_DEBUG
+#define TCPIP_DEBUG                     DBG_OFF
+#endif
+
+#ifndef PPP_DEBUG 
+#define PPP_DEBUG                       DBG_OFF
+#endif
+
+#ifndef SLIP_DEBUG 
+#define SLIP_DEBUG                      DBG_OFF
+#endif
+
+#ifndef DHCP_DEBUG 
+#define DHCP_DEBUG                      DBG_OFF
+#endif
+
+
+#ifndef DBG_MIN_LEVEL
+#define DBG_MIN_LEVEL                   DBG_LEVEL_OFF
+#endif
+
+#endif /* __LWIP_OPT_H__ */
+
+
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/pbuf.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/pbuf.h
new file mode 100644
index 000000000..0b187e121
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/pbuf.h
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#ifndef __LWIP_PBUF_H__
+#define __LWIP_PBUF_H__
+
+#include "arch/cc.h"
+
+
+#define PBUF_TRANSPORT_HLEN 20
+#define PBUF_IP_HLEN        20
+
+typedef enum {
+  PBUF_TRANSPORT,
+  PBUF_IP,
+  PBUF_LINK,
+  PBUF_RAW
+} pbuf_layer;
+
+typedef enum {
+  PBUF_RAM,
+  PBUF_ROM,
+  PBUF_REF,
+  PBUF_POOL
+} pbuf_flag;
+
+/* Definitions for the pbuf flag field. These are NOT the flags that
+ * are passed to pbuf_alloc(). */
+#define PBUF_FLAG_RAM   0x00U    /* Flags that pbuf data is stored in RAM */
+#define PBUF_FLAG_ROM   0x01U    /* Flags that pbuf data is stored in ROM */
+#define PBUF_FLAG_POOL  0x02U    /* Flags that the pbuf comes from the pbuf pool */
+#define PBUF_FLAG_REF   0x04U    /* Flags thet the pbuf payload refers to RAM */
+
+/** indicates this packet was broadcast on the link */
+#define PBUF_FLAG_LINK_BROADCAST 0x80U
+
+struct pbuf {
+  /** next pbuf in singly linked pbuf chain */
+  struct pbuf *next;
+
+  /** pointer to the actual data in the buffer */
+  void *payload;
+  
+  /**
+   * total length of this buffer and all next buffers in chain
+   * belonging to the same packet.
+   *
+   * For non-queue packet chains this is the invariant:
+   * p->tot_len == p->len + (p->next? p->next->tot_len: 0)
+   */
+  u16_t tot_len;
+  
+  /** length of this buffer */
+  u16_t len;  
+
+  /** flags telling the type of pbuf, see PBUF_FLAG_ */
+  u16_t flags;
+  
+  /**
+   * the reference count always equals the number of pointers
+   * that refer to this pbuf. This can be pointers from an application,
+   * the stack itself, or pbuf->next pointers from a chain.
+   */
+  u16_t ref;
+  
+};
+
+void pbuf_init(void);
+
+struct pbuf *pbuf_alloc(pbuf_layer l, u16_t size, pbuf_flag flag);
+void pbuf_realloc(struct pbuf *p, u16_t size); 
+u8_t pbuf_header(struct pbuf *p, s16_t header_size);
+void pbuf_ref(struct pbuf *p);
+void pbuf_ref_chain(struct pbuf *p);
+u8_t pbuf_free(struct pbuf *p);
+u8_t pbuf_clen(struct pbuf *p);  
+void pbuf_cat(struct pbuf *h, struct pbuf *t);
+void pbuf_chain(struct pbuf *h, struct pbuf *t);
+struct pbuf *pbuf_take(struct pbuf *f);
+struct pbuf *pbuf_dechain(struct pbuf *p);
+void pbuf_queue(struct pbuf *p, struct pbuf *n);
+struct pbuf * pbuf_dequeue(struct pbuf *p);
+
+#endif /* __LWIP_PBUF_H__ */
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/raw.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/raw.h
new file mode 100644
index 000000000..83b32da9d
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/raw.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_RAW_H__
+#define __LWIP_RAW_H__
+
+#include "lwip/arch.h"
+
+#include "lwip/pbuf.h"
+#include "lwip/inet.h"
+#include "lwip/ip.h"
+
+struct raw_pcb {
+/* Common members of all PCB types */
+  IP_PCB;
+
+  struct raw_pcb *next;
+
+  u16_t protocol;
+
+  u8_t (* recv)(void *arg, struct raw_pcb *pcb, struct pbuf *p,
+    struct ip_addr *addr);
+  void *recv_arg;
+};
+
+/* The following functions is the application layer interface to the
+   RAW code. */
+struct raw_pcb * raw_new        (u16_t proto);
+void             raw_remove     (struct raw_pcb *pcb);
+err_t            raw_bind       (struct raw_pcb *pcb, struct ip_addr *ipaddr);
+err_t            raw_connect    (struct raw_pcb *pcb, struct ip_addr *ipaddr);
+
+void             raw_recv       (struct raw_pcb *pcb,
+                                 u8_t (* recv)(void *arg, struct raw_pcb *pcb,
+                                              struct pbuf *p,
+                                              struct ip_addr *addr),
+                                 void *recv_arg);
+err_t            raw_sendto    (struct raw_pcb *pcb, struct pbuf *p, struct ip_addr *ipaddr);
+err_t            raw_send       (struct raw_pcb *pcb, struct pbuf *p);
+
+/* The following functions are the lower layer interface to RAW. */
+u8_t              raw_input      (struct pbuf *p, struct netif *inp);
+void             raw_init       (void);
+
+
+#endif /* __LWIP_RAW_H__ */
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/sio.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/sio.h
new file mode 100644
index 000000000..5fc28a4d6
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/sio.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ */
+
+/*
+ * This is the interface to the platform specific serial IO module
+ * It needs to be implemented by those platforms which need SLIP or PPP
+ */
+
+#include "arch/cc.h"
+
+#ifndef __sio_fd_t_defined
+typedef void * sio_fd_t;
+#endif
+
+#ifndef sio_open
+sio_fd_t sio_open(u8_t);
+#endif
+
+#ifndef sio_send
+void sio_send(u8_t, sio_fd_t);
+#endif
+
+#ifndef sio_recv
+u8_t sio_recv(sio_fd_t);
+#endif
+
+#ifndef sio_read
+u32_t sio_read(sio_fd_t, u8_t *, u32_t);
+#endif
+
+#ifndef sio_write
+u32_t sio_write(sio_fd_t, u8_t *, u32_t);
+#endif
+
+#ifndef sio_read_abort
+void sio_read_abort(sio_fd_t);
+#endif
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/snmp.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/snmp.h
new file mode 100644
index 000000000..4e806914b
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/snmp.h
@@ -0,0 +1,178 @@
+/*
+ * Copyright (c) 2001, 2002 Leon Woestenberg 
+ * Copyright (c) 2001, 2002 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Leon Woestenberg 
+ *
+ */
+#ifndef __LWIP_SNMP_H__
+#define __LWIP_SNMP_H__
+
+#include "lwip/opt.h"
+
+/* SNMP support available? */
+#if defined(LWIP_SNMP) && (LWIP_SNMP > 0)
+
+/* network interface */
+void snmp_add_ifinoctets(unsigned long value); 
+void snmp_inc_ifinucastpkts(void);
+void snmp_inc_ifinnucastpkts(void);
+void snmp_inc_ifindiscards(void);
+void snmp_add_ifoutoctets(unsigned long value);
+void snmp_inc_ifoutucastpkts(void);
+void snmp_inc_ifoutnucastpkts(void);
+void snmp_inc_ifoutdiscards(void);
+
+/* IP */
+void snmp_inc_ipinreceives(void);
+void snmp_inc_ipindelivers(void);
+void snmp_inc_ipindiscards(void);
+void snmp_inc_ipoutdiscards(void);
+void snmp_inc_ipoutrequests(void);
+void snmp_inc_ipunknownprotos(void);
+void snmp_inc_ipnoroutes(void);
+void snmp_inc_ipforwdatagrams(void);
+
+/* ICMP */
+void snmp_inc_icmpinmsgs(void);
+void snmp_inc_icmpinerrors(void);
+void snmp_inc_icmpindestunreachs(void);
+void snmp_inc_icmpintimeexcds(void);
+void snmp_inc_icmpinparmprobs(void);
+void snmp_inc_icmpinsrcquenchs(void);
+void snmp_inc_icmpinredirects(void);
+void snmp_inc_icmpinechos(void);
+void snmp_inc_icmpinechoreps(void);
+void snmp_inc_icmpintimestamps(void);
+void snmp_inc_icmpintimestampreps(void);
+void snmp_inc_icmpinaddrmasks(void);
+void snmp_inc_icmpinaddrmaskreps(void);
+void snmp_inc_icmpoutmsgs(void);
+void snmp_inc_icmpouterrors(void);
+void snmp_inc_icmpoutdestunreachs(void);
+void snmp_inc_icmpouttimeexcds(void);
+void snmp_inc_icmpoutparmprobs(void);
+void snmp_inc_icmpoutsrcquenchs(void);
+void snmp_inc_icmpoutredirects(void); 
+void snmp_inc_icmpoutechos(void);
+void snmp_inc_icmpoutechoreps(void);
+void snmp_inc_icmpouttimestamps(void);
+void snmp_inc_icmpouttimestampreps(void);
+void snmp_inc_icmpoutaddrmasks(void);
+void snmp_inc_icmpoutaddrmaskreps(void);
+
+/* TCP */
+void snmp_inc_tcpactiveopens(void);
+void snmp_inc_tcppassiveopens(void);
+void snmp_inc_tcpattemptfails(void);
+void snmp_inc_tcpestabresets(void);
+void snmp_inc_tcpcurrestab(void);
+void snmp_inc_tcpinsegs(void);
+void snmp_inc_tcpoutsegs(void);
+void snmp_inc_tcpretranssegs(void);
+void snmp_inc_tcpinerrs(void);
+void snmp_inc_tcpoutrsts(void);
+
+/* UDP */
+void snmp_inc_udpindatagrams(void);
+void snmp_inc_udpnoports(void);
+void snmp_inc_udpinerrors(void);
+void snmp_inc_udpoutdatagrams(void);
+
+/* LWIP_SNMP support not available */
+/* define everything to be empty */
+#else
+
+/* network interface */
+#define snmp_add_ifinoctets(value) 
+#define snmp_inc_ifinucastpkts()
+#define snmp_inc_ifinnucastpkts()
+#define snmp_inc_ifindiscards()
+#define snmp_add_ifoutoctets(value)
+#define snmp_inc_ifoutucastpkts()
+#define snmp_inc_ifoutnucastpkts()
+#define snmp_inc_ifoutdiscards()
+
+/* IP */
+#define snmp_inc_ipinreceives()
+#define snmp_inc_ipindelivers()
+#define snmp_inc_ipindiscards()
+#define snmp_inc_ipoutdiscards()
+#define snmp_inc_ipoutrequests()
+#define snmp_inc_ipunknownprotos()
+#define snmp_inc_ipnoroutes()
+#define snmp_inc_ipforwdatagrams()
+
+/* ICMP */
+#define snmp_inc_icmpinmsgs()
+#define snmp_inc_icmpinerrors() 
+#define snmp_inc_icmpindestunreachs() 
+#define snmp_inc_icmpintimeexcds()
+#define snmp_inc_icmpinparmprobs() 
+#define snmp_inc_icmpinsrcquenchs() 
+#define snmp_inc_icmpinredirects() 
+#define snmp_inc_icmpinechos() 
+#define snmp_inc_icmpinechoreps()
+#define snmp_inc_icmpintimestamps() 
+#define snmp_inc_icmpintimestampreps()
+#define snmp_inc_icmpinaddrmasks()
+#define snmp_inc_icmpinaddrmaskreps()
+#define snmp_inc_icmpoutmsgs()
+#define snmp_inc_icmpouterrors()
+#define snmp_inc_icmpoutdestunreachs() 
+#define snmp_inc_icmpouttimeexcds() 
+#define snmp_inc_icmpoutparmprobs()
+#define snmp_inc_icmpoutsrcquenchs()
+#define snmp_inc_icmpoutredirects() 
+#define snmp_inc_icmpoutechos() 
+#define snmp_inc_icmpoutechoreps()
+#define snmp_inc_icmpouttimestamps()
+#define snmp_inc_icmpouttimestampreps()
+#define snmp_inc_icmpoutaddrmasks()
+#define snmp_inc_icmpoutaddrmaskreps()
+/* TCP */
+#define snmp_inc_tcpactiveopens()
+#define snmp_inc_tcppassiveopens()
+#define snmp_inc_tcpattemptfails()
+#define snmp_inc_tcpestabresets()
+#define snmp_inc_tcpcurrestab()
+#define snmp_inc_tcpinsegs()
+#define snmp_inc_tcpoutsegs()
+#define snmp_inc_tcpretranssegs()
+#define snmp_inc_tcpinerrs()
+#define snmp_inc_tcpoutrsts()
+
+/* UDP */
+#define snmp_inc_udpindatagrams()
+#define snmp_inc_udpnoports()
+#define snmp_inc_udpinerrors()
+#define snmp_inc_udpoutdatagrams()
+
+#endif
+
+#endif /* __LWIP_SNMP_H__ */
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/sockets.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/sockets.h
new file mode 100644
index 000000000..9c25035ad
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/sockets.h
@@ -0,0 +1,271 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+
+#ifndef __LWIP_SOCKETS_H__
+#define __LWIP_SOCKETS_H__
+#include "lwip/ip_addr.h"
+
+struct sockaddr_in {
+  u8_t sin_len;
+  u8_t sin_family;
+  u16_t sin_port;
+  struct in_addr sin_addr;
+  char sin_zero[8];
+};
+
+struct sockaddr {
+  u8_t sa_len;
+  u8_t sa_family;
+  char sa_data[14];
+};
+
+#ifndef socklen_t
+#  define socklen_t int
+#endif
+
+
+#define SOCK_STREAM     1
+#define SOCK_DGRAM      2
+#define SOCK_RAW        3
+
+/*
+ * Option flags per-socket.
+ */
+#define  SO_DEBUG  0x0001    /* turn on debugging info recording */
+#define  SO_ACCEPTCONN  0x0002    /* socket has had listen() */
+#define  SO_REUSEADDR  0x0004    /* allow local address reuse */
+#define  SO_KEEPALIVE  0x0008    /* keep connections alive */
+#define  SO_DONTROUTE  0x0010    /* just use interface addresses */
+#define  SO_BROADCAST  0x0020    /* permit sending of broadcast msgs */
+#define  SO_USELOOPBACK  0x0040    /* bypass hardware when possible */
+#define  SO_LINGER  0x0080    /* linger on close if data present */
+#define  SO_OOBINLINE  0x0100    /* leave received OOB data in line */
+#define	 SO_REUSEPORT	0x0200		/* allow local address & port reuse */
+
+#define SO_DONTLINGER   (int)(~SO_LINGER)
+
+/*
+ * Additional options, not kept in so_options.
+ */
+#define SO_SNDBUF  0x1001    /* send buffer size */
+#define SO_RCVBUF  0x1002    /* receive buffer size */
+#define SO_SNDLOWAT  0x1003    /* send low-water mark */
+#define SO_RCVLOWAT  0x1004    /* receive low-water mark */
+#define SO_SNDTIMEO  0x1005    /* send timeout */
+#define SO_RCVTIMEO  0x1006    /* receive timeout */
+#define  SO_ERROR  0x1007    /* get error status and clear */
+#define  SO_TYPE    0x1008    /* get socket type */
+
+
+
+/*
+ * Structure used for manipulating linger option.
+ */
+struct linger {
+       int l_onoff;                /* option on/off */
+       int l_linger;               /* linger time */
+};
+
+/*
+ * Level number for (get/set)sockopt() to apply to socket itself.
+ */
+#define  SOL_SOCKET  0xfff    /* options for socket level */
+
+
+#define AF_UNSPEC       0
+#define AF_INET         2
+#define PF_INET         AF_INET
+#define PF_UNSPEC       AF_UNSPEC
+
+#define IPPROTO_IP      0
+#define IPPROTO_TCP     6
+#define IPPROTO_UDP     17
+
+#define INADDR_ANY      0
+#define INADDR_BROADCAST 0xffffffff
+
+/* Flags we can use with send and recv. */
+#define MSG_DONTWAIT    0x40            /* Nonblocking i/o for this operation only */
+
+
+/*
+ * Options for level IPPROTO_IP
+ */
+#define IP_TOS       1
+#define IP_TTL       2
+
+
+#define IPTOS_TOS_MASK          0x1E
+#define IPTOS_TOS(tos)          ((tos) & IPTOS_TOS_MASK)
+#define IPTOS_LOWDELAY          0x10
+#define IPTOS_THROUGHPUT        0x08
+#define IPTOS_RELIABILITY       0x04
+#define IPTOS_LOWCOST           0x02
+#define IPTOS_MINCOST           IPTOS_LOWCOST
+
+/*
+ * Definitions for IP precedence (also in ip_tos) (hopefully unused)
+ */
+#define IPTOS_PREC_MASK                 0xe0
+#define IPTOS_PREC(tos)                ((tos) & IPTOS_PREC_MASK)
+#define IPTOS_PREC_NETCONTROL           0xe0
+#define IPTOS_PREC_INTERNETCONTROL      0xc0
+#define IPTOS_PREC_CRITIC_ECP           0xa0
+#define IPTOS_PREC_FLASHOVERRIDE        0x80
+#define IPTOS_PREC_FLASH                0x60
+#define IPTOS_PREC_IMMEDIATE            0x40
+#define IPTOS_PREC_PRIORITY             0x20
+#define IPTOS_PREC_ROUTINE              0x00
+
+
+/*
+ * Commands for ioctlsocket(),  taken from the BSD file fcntl.h.
+ *
+ *
+ * Ioctl's have the command encoded in the lower word,
+ * and the size of any in or out parameters in the upper
+ * word.  The high 2 bits of the upper word are used
+ * to encode the in/out status of the parameter; for now
+ * we restrict parameters to at most 128 bytes.
+ */
+#if !defined(FIONREAD) || !defined(FIONBIO)
+#define IOCPARM_MASK    0x7f            /* parameters must be < 128 bytes */
+#define IOC_VOID        0x20000000      /* no parameters */
+#define IOC_OUT         0x40000000      /* copy out parameters */
+#define IOC_IN          0x80000000      /* copy in parameters */
+#define IOC_INOUT       (IOC_IN|IOC_OUT)
+                                        /* 0x20000000 distinguishes new &
+                                           old ioctl's */
+#define _IO(x,y)        (IOC_VOID|((x)<<8)|(y))
+
+#define _IOR(x,y,t)     (IOC_OUT|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y))
+
+#define _IOW(x,y,t)     (IOC_IN|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y))
+#endif
+
+#ifndef FIONREAD
+#define FIONREAD    _IOR('f', 127, unsigned long) /* get # bytes to read */
+#endif
+#ifndef FIONBIO
+#define FIONBIO     _IOW('f', 126, unsigned long) /* set/clear non-blocking i/o */
+#endif
+
+/* Socket I/O Controls */
+#ifndef SIOCSHIWAT
+#define SIOCSHIWAT  _IOW('s',  0, unsigned long)  /* set high watermark */
+#define SIOCGHIWAT  _IOR('s',  1, unsigned long)  /* get high watermark */
+#define SIOCSLOWAT  _IOW('s',  2, unsigned long)  /* set low watermark */
+#define SIOCGLOWAT  _IOR('s',  3, unsigned long)  /* get low watermark */
+#define SIOCATMARK  _IOR('s',  7, unsigned long)  /* at oob mark? */
+#endif
+
+#ifndef O_NONBLOCK
+#define O_NONBLOCK    04000U
+#endif
+
+#ifndef FD_SET
+  #undef  FD_SETSIZE
+  #define FD_SETSIZE    16
+  #define FD_SET(n, p)  ((p)->fd_bits[(n)/8] |=  (1 << ((n) & 7)))
+  #define FD_CLR(n, p)  ((p)->fd_bits[(n)/8] &= ~(1 << ((n) & 7)))
+  #define FD_ISSET(n,p) ((p)->fd_bits[(n)/8] &   (1 << ((n) & 7)))
+  #define FD_ZERO(p)    memset((void*)(p),0,sizeof(*(p)))
+
+  typedef struct fd_set {
+          unsigned char fd_bits [(FD_SETSIZE+7)/8];
+        } fd_set;
+
+/* 
+ * only define this in sockets.c so it does not interfere
+ * with other projects namespaces where timeval is present
+ */ 
+#ifndef LWIP_TIMEVAL_PRIVATE
+#define LWIP_TIMEVAL_PRIVATE 1
+#endif
+
+#if LWIP_TIMEVAL_PRIVATE
+  struct timeval {
+    long    tv_sec;         /* seconds */
+    long    tv_usec;        /* and microseconds */
+  };
+#endif
+
+#endif
+
+int lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen);
+int lwip_bind(int s, struct sockaddr *name, socklen_t namelen);
+int lwip_shutdown(int s, int how);
+int lwip_getpeername (int s, struct sockaddr *name, socklen_t *namelen);
+int lwip_getsockname (int s, struct sockaddr *name, socklen_t *namelen);
+int lwip_getsockopt (int s, int level, int optname, void *optval, socklen_t *optlen);
+int lwip_setsockopt (int s, int level, int optname, const void *optval, socklen_t optlen);
+int lwip_close(int s);
+int lwip_connect(int s, struct sockaddr *name, socklen_t namelen);
+int lwip_listen(int s, int backlog);
+int lwip_recv(int s, void *mem, int len, unsigned int flags);
+int lwip_read(int s, void *mem, int len);
+int lwip_recvfrom(int s, void *mem, int len, unsigned int flags,
+      struct sockaddr *from, socklen_t *fromlen);
+int lwip_send(int s, void *dataptr, int size, unsigned int flags);
+int lwip_sendto(int s, void *dataptr, int size, unsigned int flags,
+    struct sockaddr *to, socklen_t tolen);
+int lwip_socket(int domain, int type, int protocol);
+int lwip_write(int s, void *dataptr, int size);
+int lwip_select(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset,
+                struct timeval *timeout);
+int lwip_ioctl(int s, long cmd, void *argp);
+
+#if LWIP_COMPAT_SOCKETS
+#define accept(a,b,c)         lwip_accept(a,b,c)
+#define bind(a,b,c)           lwip_bind(a,b,c)
+#define shutdown(a,b)         lwip_shutdown(a,b)
+#define close(s)              lwip_close(s)
+#define connect(a,b,c)        lwip_connect(a,b,c)
+#define getsockname(a,b,c)    lwip_getsockname(a,b,c)
+#define getpeername(a,b,c)    lwip_getpeername(a,b,c)
+#define setsockopt(a,b,c,d,e) lwip_setsockopt(a,b,c,d,e)
+#define getsockopt(a,b,c,d,e) lwip_getsockopt(a,b,c,d,e)
+#define listen(a,b)           lwip_listen(a,b)
+#define recv(a,b,c,d)         lwip_recv(a,b,c,d)
+#define read(a,b,c)           lwip_read(a,b,c)
+#define recvfrom(a,b,c,d,e,f) lwip_recvfrom(a,b,c,d,e,f)
+#define send(a,b,c,d)         lwip_send(a,b,c,d)
+#define sendto(a,b,c,d,e,f)   lwip_sendto(a,b,c,d,e,f)
+#define socket(a,b,c)         lwip_socket(a,b,c)
+#define write(a,b,c)          lwip_write(a,b,c)
+#define select(a,b,c,d,e)     lwip_select(a,b,c,d,e)
+#define ioctlsocket(a,b,c)    lwip_ioctl(a,b,c)
+#endif /* LWIP_COMPAT_SOCKETS */
+
+#endif /* __LWIP_SOCKETS_H__ */
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/stats.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/stats.h
new file mode 100644
index 000000000..29dfd5731
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/stats.h
@@ -0,0 +1,158 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_STATS_H__
+#define __LWIP_STATS_H__
+
+#include "lwip/opt.h"
+#include "arch/cc.h"
+
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+
+#if LWIP_STATS
+
+struct stats_proto {
+  u16_t xmit;    /* Transmitted packets. */
+  u16_t rexmit;  /* Retransmitted packets. */
+  u16_t recv;    /* Received packets. */
+  u16_t fw;      /* Forwarded packets. */
+  u16_t drop;    /* Dropped packets. */
+  u16_t chkerr;  /* Checksum error. */
+  u16_t lenerr;  /* Invalid length error. */
+  u16_t memerr;  /* Out of memory error. */
+  u16_t rterr;   /* Routing error. */
+  u16_t proterr; /* Protocol error. */
+  u16_t opterr;  /* Error in options. */
+  u16_t err;     /* Misc error. */
+  u16_t cachehit;
+};
+
+struct stats_mem {
+  mem_size_t avail;
+  mem_size_t used;
+  mem_size_t max;  
+  mem_size_t err;
+};
+
+struct stats_pbuf {
+  u16_t avail;
+  u16_t used;
+  u16_t max;  
+  u16_t err;
+
+  u16_t alloc_locked;
+  u16_t refresh_locked;
+};
+
+struct stats_syselem {
+  u16_t used;
+  u16_t max;
+  u16_t err;
+};
+
+struct stats_sys {
+  struct stats_syselem sem;
+  struct stats_syselem mbox;
+};
+
+struct stats_ {
+  struct stats_proto link;
+  struct stats_proto ip_frag;
+  struct stats_proto ip;
+  struct stats_proto icmp;
+  struct stats_proto udp;
+  struct stats_proto tcp;
+  struct stats_pbuf pbuf;
+  struct stats_mem mem;
+  struct stats_mem memp[MEMP_MAX];
+  struct stats_sys sys;
+};
+
+extern struct stats_ lwip_stats;
+
+
+void stats_init(void);
+
+#define STATS_INC(x) ++lwip_stats.x
+#else
+#define stats_init()
+#define STATS_INC(x)
+#endif /* LWIP_STATS */
+
+#if TCP_STATS
+#define TCP_STATS_INC(x) STATS_INC(x)
+#else
+#define TCP_STATS_INC(x)
+#endif
+
+#if UDP_STATS
+#define UDP_STATS_INC(x) STATS_INC(x)
+#else
+#define UDP_STATS_INC(x)
+#endif
+
+#if ICMP_STATS
+#define ICMP_STATS_INC(x) STATS_INC(x)
+#else
+#define ICMP_STATS_INC(x)
+#endif
+
+#if IP_STATS
+#define IP_STATS_INC(x) STATS_INC(x)
+#else
+#define IP_STATS_INC(x)
+#endif
+
+#if IPFRAG_STATS
+#define IPFRAG_STATS_INC(x) STATS_INC(x)
+#else
+#define IPFRAG_STATS_INC(x)
+#endif
+
+#if LINK_STATS
+#define LINK_STATS_INC(x) STATS_INC(x)
+#else
+#define LINK_STATS_INC(x)
+#endif
+
+/* Display of statistics */
+#if LWIP_STATS_DISPLAY
+void stats_display(void);
+#else
+#define stats_display()
+#endif
+
+#endif /* __LWIP_STATS_H__ */
+
+
+
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/sys.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/sys.h
new file mode 100644
index 000000000..d2328c462
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/sys.h
@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_SYS_H__
+#define __LWIP_SYS_H__
+
+#include "arch/cc.h"
+
+#include "lwip/opt.h"
+
+
+#if NO_SYS
+
+/* For a totally minimal and standalone system, we provide null
+   definitions of the sys_ functions. */
+typedef u8_t sys_sem_t;
+typedef u8_t sys_mbox_t;
+struct sys_timeout {u8_t dummy;};
+
+#define sys_init()
+#define sys_timeout(m,h,a)
+#define sys_untimeout(m,a)
+#define sys_sem_new(c) c
+#define sys_sem_signal(s)
+#define sys_sem_wait(s)
+#define sys_sem_free(s)
+#define sys_mbox_new() 0
+#define sys_mbox_fetch(m,d)
+#define sys_mbox_post(m,d)
+#define sys_mbox_free(m)
+
+#define sys_thread_new(t,a,p)
+
+#else /* NO_SYS */
+
+#include "arch/sys_arch.h"
+
+/** Return code for timeouts from sys_arch_mbox_fetch and sys_arch_sem_wait */
+#define SYS_ARCH_TIMEOUT 0xffffffff
+
+typedef void (* sys_timeout_handler)(void *arg);
+
+struct sys_timeout {
+  struct sys_timeout *next;
+  u32_t time;
+  sys_timeout_handler h;
+  void *arg;
+};
+
+struct sys_timeouts {
+  struct sys_timeout *next;
+};
+
+/* sys_init() must be called before anthing else. */
+void sys_init(void);
+
+/*
+ * sys_timeout():
+ *
+ * Schedule a timeout a specified amount of milliseconds in the
+ * future. When the timeout occurs, the specified timeout handler will
+ * be called. The handler will be passed the "arg" argument when
+ * called.
+ *
+ */
+void sys_timeout(u32_t msecs, sys_timeout_handler h, void *arg);
+void sys_untimeout(sys_timeout_handler h, void *arg);
+struct sys_timeouts *sys_arch_timeouts(void);
+
+/* Semaphore functions. */
+sys_sem_t sys_sem_new(u8_t count);
+void sys_sem_signal(sys_sem_t sem);
+u32_t sys_arch_sem_wait(sys_sem_t sem, u32_t timeout);
+void sys_sem_free(sys_sem_t sem);
+void sys_sem_wait(sys_sem_t sem);
+int sys_sem_wait_timeout(sys_sem_t sem, u32_t timeout);
+
+/* Time functions. */
+#ifndef sys_msleep
+void sys_msleep(u32_t ms); /* only has a (close to) 1 jiffy resolution. */
+#endif
+#ifndef sys_jiffies
+u32_t sys_jiffies(void); /* since power up. */
+#endif
+
+/* Mailbox functions. */
+sys_mbox_t sys_mbox_new(void);
+void sys_mbox_post(sys_mbox_t mbox, void *msg);
+u32_t sys_arch_mbox_fetch(sys_mbox_t mbox, void **msg, u32_t timeout);
+void sys_mbox_free(sys_mbox_t mbox);
+void sys_mbox_fetch(sys_mbox_t mbox, void **msg);
+
+
+/* Thread functions. */
+sys_thread_t sys_thread_new(void (* thread)(void *arg), void *arg, int prio);
+
+/* The following functions are used only in Unix code, and
+   can be omitted when porting the stack. */
+/* Returns the current time in microseconds. */
+unsigned long sys_now(void);
+
+#endif /* NO_SYS */
+
+/* Critical Region Protection */
+/* These functions must be implemented in the sys_arch.c file.
+   In some implementations they can provide a more light-weight protection
+   mechanism than using semaphores. Otherwise semaphores can be used for
+   implementation */
+#ifndef SYS_ARCH_PROTECT
+/** SYS_LIGHTWEIGHT_PROT
+ * define SYS_LIGHTWEIGHT_PROT in lwipopts.h if you want inter-task protection
+ * for certain critical regions during buffer allocation, deallocation and memory
+ * allocation and deallocation.
+ */
+#if SYS_LIGHTWEIGHT_PROT
+
+/** SYS_ARCH_DECL_PROTECT
+ * declare a protection variable. This macro will default to defining a variable of
+ * type sys_prot_t. If a particular port needs a different implementation, then
+ * this macro may be defined in sys_arch.h.
+ */
+#define SYS_ARCH_DECL_PROTECT(lev) sys_prot_t lev
+/** SYS_ARCH_PROTECT
+ * Perform a "fast" protect. This could be implemented by
+ * disabling interrupts for an embedded system or by using a semaphore or
+ * mutex. The implementation should allow calling SYS_ARCH_PROTECT when
+ * already protected. The old protection level is returned in the variable
+ * "lev". This macro will default to calling the sys_arch_protect() function
+ * which should be implemented in sys_arch.c. If a particular port needs a
+ * different implementation, then this macro may be defined in sys_arch.h
+ */
+#define SYS_ARCH_PROTECT(lev) lev = sys_arch_protect()
+/** SYS_ARCH_UNPROTECT
+ * Perform a "fast" set of the protection level to "lev". This could be
+ * implemented by setting the interrupt level to "lev" within the MACRO or by
+ * using a semaphore or mutex.  This macro will default to calling the
+ * sys_arch_unprotect() function which should be implemented in
+ * sys_arch.c. If a particular port needs a different implementation, then
+ * this macro may be defined in sys_arch.h
+ */
+#define SYS_ARCH_UNPROTECT(lev) sys_arch_unprotect(lev)
+sys_prot_t sys_arch_protect(void);
+void sys_arch_unprotect(sys_prot_t pval);
+
+#else
+
+#define SYS_ARCH_DECL_PROTECT(lev)
+#define SYS_ARCH_PROTECT(lev)
+#define SYS_ARCH_UNPROTECT(lev)
+
+#endif /* SYS_LIGHTWEIGHT_PROT */
+
+#endif /* SYS_ARCH_PROTECT */
+
+#endif /* __LWIP_SYS_H__ */
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/tcp.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/tcp.h
new file mode 100644
index 000000000..81eb51e08
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/tcp.h
@@ -0,0 +1,531 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_TCP_H__
+#define __LWIP_TCP_H__
+
+#include "lwip/sys.h"
+#include "lwip/mem.h"
+
+#include "lwip/pbuf.h"
+#include "lwip/opt.h"
+#include "lwip/ip.h"
+#include "lwip/icmp.h"
+
+#include "lwip/err.h"
+
+struct tcp_pcb;
+
+/* Functions for interfacing with TCP: */
+
+/* Lower layer interface to TCP: */
+void             tcp_init    (void);  /* Must be called first to
+           initialize TCP. */
+void             tcp_tmr     (void);  /* Must be called every
+           TCP_TMR_INTERVAL
+           ms. (Typically 250 ms). */
+/* Application program's interface: */
+struct tcp_pcb * tcp_new     (void);
+struct tcp_pcb * tcp_alloc   (u8_t prio);
+
+void             tcp_arg     (struct tcp_pcb *pcb, void *arg);
+void             tcp_accept  (struct tcp_pcb *pcb,
+            err_t (* accept)(void *arg, struct tcp_pcb *newpcb,
+                 err_t err));
+void             tcp_recv    (struct tcp_pcb *pcb,
+            err_t (* recv)(void *arg, struct tcp_pcb *tpcb,
+          struct pbuf *p, err_t err));
+void             tcp_sent    (struct tcp_pcb *pcb,
+            err_t (* sent)(void *arg, struct tcp_pcb *tpcb,
+               u16_t len));
+void             tcp_poll    (struct tcp_pcb *pcb,
+            err_t (* poll)(void *arg, struct tcp_pcb *tpcb),
+            u8_t interval);
+void             tcp_err     (struct tcp_pcb *pcb,
+            void (* err)(void *arg, err_t err));
+
+#define          tcp_mss(pcb)      ((pcb)->mss)
+#define          tcp_sndbuf(pcb)   ((pcb)->snd_buf)
+
+void             tcp_recved  (struct tcp_pcb *pcb, u16_t len);
+err_t            tcp_bind    (struct tcp_pcb *pcb, struct ip_addr *ipaddr,
+            u16_t port);
+err_t            tcp_connect (struct tcp_pcb *pcb, struct ip_addr *ipaddr,
+            u16_t port, err_t (* connected)(void *arg,
+                    struct tcp_pcb *tpcb,
+                    err_t err));
+struct tcp_pcb * tcp_listen  (struct tcp_pcb *pcb);
+void             tcp_abort   (struct tcp_pcb *pcb);
+err_t            tcp_close   (struct tcp_pcb *pcb);
+err_t            tcp_write   (struct tcp_pcb *pcb, const void *dataptr, u16_t len,
+            u8_t copy);
+
+void             tcp_setprio (struct tcp_pcb *pcb, u8_t prio);
+
+#define TCP_PRIO_MIN    1
+#define TCP_PRIO_NORMAL 64
+#define TCP_PRIO_MAX    127
+
+/* It is also possible to call these two functions at the right
+   intervals (instead of calling tcp_tmr()). */
+void             tcp_slowtmr (void);
+void             tcp_fasttmr (void);
+
+
+/* Only used by IP to pass a TCP segment to TCP: */
+void             tcp_input   (struct pbuf *p, struct netif *inp);
+/* Used within the TCP code only: */
+err_t            tcp_output  (struct tcp_pcb *pcb);
+void             tcp_rexmit  (struct tcp_pcb *pcb);
+void             tcp_rexmit_rto  (struct tcp_pcb *pcb);
+
+
+
+#define TCP_SEQ_LT(a,b)     ((s32_t)((a)-(b)) < 0)
+#define TCP_SEQ_LEQ(a,b)    ((s32_t)((a)-(b)) <= 0)
+#define TCP_SEQ_GT(a,b)     ((s32_t)((a)-(b)) > 0)
+#define TCP_SEQ_GEQ(a,b)    ((s32_t)((a)-(b)) >= 0)
+/* is b<=a<=c? */
+#if 0 /* see bug #10548 */
+#define TCP_SEQ_BETWEEN(a,b,c) ((c)-(b) >= (a)-(b))
+#endif
+#define TCP_SEQ_BETWEEN(a,b,c) (TCP_SEQ_GEQ(a,b) && TCP_SEQ_LEQ(a,c))
+#define TCP_FIN 0x01U
+#define TCP_SYN 0x02U
+#define TCP_RST 0x04U
+#define TCP_PSH 0x08U
+#define TCP_ACK 0x10U
+#define TCP_URG 0x20U
+#define TCP_ECE 0x40U
+#define TCP_CWR 0x80U
+
+#define TCP_FLAGS 0x3fU
+
+/* Length of the TCP header, excluding options. */
+#define TCP_HLEN 20
+
+#ifndef TCP_TMR_INTERVAL
+#define TCP_TMR_INTERVAL       250  /* The TCP timer interval in
+                                       milliseconds. */
+#endif /* TCP_TMR_INTERVAL */
+
+#ifndef TCP_FAST_INTERVAL
+#define TCP_FAST_INTERVAL      TCP_TMR_INTERVAL /* the fine grained timeout in
+                                       milliseconds */
+#endif /* TCP_FAST_INTERVAL */
+
+#ifndef TCP_SLOW_INTERVAL
+#define TCP_SLOW_INTERVAL      (2*TCP_TMR_INTERVAL)  /* the coarse grained timeout in
+                                       milliseconds */
+#endif /* TCP_SLOW_INTERVAL */
+
+#define TCP_FIN_WAIT_TIMEOUT 20000 /* milliseconds */
+#define TCP_SYN_RCVD_TIMEOUT 20000 /* milliseconds */
+
+#define TCP_OOSEQ_TIMEOUT        6 /* x RTO */
+
+#define TCP_MSL 60000  /* The maximum segment lifetime in microseconds */
+
+/*
+ * User-settable options (used with setsockopt).
+ */
+#define	TCP_NODELAY	   0x01	   /* don't delay send to coalesce packets */
+#define TCP_KEEPALIVE  0x02    /* send KEEPALIVE probes when idle for pcb->keepalive miliseconds */
+
+/* Keepalive values */
+#define  TCP_KEEPDEFAULT   7200000                       /* KEEPALIVE timer in miliseconds */
+#define  TCP_KEEPINTVL     75000                         /* Time between KEEPALIVE probes in miliseconds */
+#define  TCP_KEEPCNT       9                             /* Counter for KEEPALIVE probes */
+#define  TCP_MAXIDLE       TCP_KEEPCNT * TCP_KEEPINTVL   /* Maximum KEEPALIVE probe time */
+
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct tcp_hdr {
+  PACK_STRUCT_FIELD(u16_t src);
+  PACK_STRUCT_FIELD(u16_t dest);
+  PACK_STRUCT_FIELD(u32_t seqno);
+  PACK_STRUCT_FIELD(u32_t ackno);
+  PACK_STRUCT_FIELD(u16_t _hdrlen_rsvd_flags);
+  PACK_STRUCT_FIELD(u16_t wnd);
+  PACK_STRUCT_FIELD(u16_t chksum);
+  PACK_STRUCT_FIELD(u16_t urgp);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define TCPH_OFFSET(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) >> 8)
+#define TCPH_HDRLEN(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) >> 12)
+#define TCPH_FLAGS(phdr)  (ntohs((phdr)->_hdrlen_rsvd_flags) & TCP_FLAGS)
+
+#define TCPH_OFFSET_SET(phdr, offset) (phdr)->_hdrlen_rsvd_flags = htons(((offset) << 8) | TCPH_FLAGS(phdr))
+#define TCPH_HDRLEN_SET(phdr, len) (phdr)->_hdrlen_rsvd_flags = htons(((len) << 12) | TCPH_FLAGS(phdr))
+#define TCPH_FLAGS_SET(phdr, flags) (phdr)->_hdrlen_rsvd_flags = htons((ntohs((phdr)->_hdrlen_rsvd_flags) & ~TCP_FLAGS) | (flags))
+#define TCPH_SET_FLAG(phdr, flags ) (phdr)->_hdrlen_rsvd_flags = htons(ntohs((phdr)->_hdrlen_rsvd_flags) | (flags))
+#define TCPH_UNSET_FLAG(phdr, flags) (phdr)->_hdrlen_rsvd_flags = htons(ntohs((phdr)->_hdrlen_rsvd_flags) | (TCPH_FLAGS(phdr) & ~(flags)) )
+
+#define TCP_TCPLEN(seg) ((seg)->len + ((TCPH_FLAGS((seg)->tcphdr) & TCP_FIN || \
+          TCPH_FLAGS((seg)->tcphdr) & TCP_SYN)? 1: 0))
+
+enum tcp_state {
+  CLOSED      = 0,
+  LISTEN      = 1,
+  SYN_SENT    = 2,
+  SYN_RCVD    = 3,
+  ESTABLISHED = 4,
+  FIN_WAIT_1  = 5,
+  FIN_WAIT_2  = 6,
+  CLOSE_WAIT  = 7,
+  CLOSING     = 8,
+  LAST_ACK    = 9,
+  TIME_WAIT   = 10
+};
+
+/* the TCP protocol control block */
+struct tcp_pcb {
+/** common PCB members */
+  IP_PCB;
+/** protocol specific PCB members */
+  struct tcp_pcb *next; /* for the linked list */
+  enum tcp_state state; /* TCP state */
+  u8_t prio;
+  void *callback_arg;
+
+  u16_t local_port;
+  u16_t remote_port;
+  
+  u8_t flags;
+#define TF_ACK_DELAY (u8_t)0x01U   /* Delayed ACK. */
+#define TF_ACK_NOW   (u8_t)0x02U   /* Immediate ACK. */
+#define TF_INFR      (u8_t)0x04U   /* In fast recovery. */
+#define TF_RESET     (u8_t)0x08U   /* Connection was reset. */
+#define TF_CLOSED    (u8_t)0x10U   /* Connection was sucessfully closed. */
+#define TF_GOT_FIN   (u8_t)0x20U   /* Connection was closed by the remote end. */
+#define TF_NODELAY   (u8_t)0x40U   /* Disable Nagle algorithm */
+
+  /* receiver variables */
+  u32_t rcv_nxt;   /* next seqno expected */
+  u16_t rcv_wnd;   /* receiver window */
+  
+  /* Timers */
+  u32_t tmr;
+  u8_t polltmr, pollinterval;
+  
+  /* Retransmission timer. */
+  u16_t rtime;
+  
+  u16_t mss;   /* maximum segment size */
+  
+  /* RTT (round trip time) estimation variables */
+  u32_t rttest; /* RTT estimate in 500ms ticks */
+  u32_t rtseq;  /* sequence number being timed */
+  s16_t sa, sv; /* @todo document this */
+
+  u16_t rto;    /* retransmission time-out */
+  u8_t nrtx;    /* number of retransmissions */
+
+  /* fast retransmit/recovery */
+  u32_t lastack; /* Highest acknowledged seqno. */
+  u8_t dupacks;
+  
+  /* congestion avoidance/control variables */
+  u16_t cwnd;  
+  u16_t ssthresh;
+
+  /* sender variables */
+  u32_t snd_nxt,       /* next seqno to be sent */
+    snd_max,       /* Highest seqno sent. */
+    snd_wnd,       /* sender window */
+    snd_wl1, snd_wl2, /* Sequence and acknowledgement numbers of last
+       window update. */
+    snd_lbb;       /* Sequence number of next byte to be buffered. */
+
+  u16_t acked;
+  
+  u16_t snd_buf;   /* Available buffer space for sending (in bytes). */
+  u8_t snd_queuelen; /* Available buffer space for sending (in tcp_segs). */
+  
+  
+  /* These are ordered by sequence number: */
+  struct tcp_seg *unsent;   /* Unsent (queued) segments. */
+  struct tcp_seg *unacked;  /* Sent but unacknowledged segments. */
+#if TCP_QUEUE_OOSEQ  
+  struct tcp_seg *ooseq;    /* Received out of sequence segments. */
+#endif /* TCP_QUEUE_OOSEQ */
+
+#if LWIP_CALLBACK_API
+  /* Function to be called when more send buffer space is available. */
+  err_t (* sent)(void *arg, struct tcp_pcb *pcb, u16_t space);
+  
+  /* Function to be called when (in-sequence) data has arrived. */
+  err_t (* recv)(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err);
+
+  /* Function to be called when a connection has been set up. */
+  err_t (* connected)(void *arg, struct tcp_pcb *pcb, err_t err);
+
+  /* Function to call when a listener has been connected. */
+  err_t (* accept)(void *arg, struct tcp_pcb *newpcb, err_t err);
+
+  /* Function which is called periodically. */
+  err_t (* poll)(void *arg, struct tcp_pcb *pcb);
+
+  /* Function to be called whenever a fatal error occurs. */
+  void (* errf)(void *arg, err_t err);
+#endif /* LWIP_CALLBACK_API */
+
+  /* idle time before KEEPALIVE is sent */
+  u32_t keepalive;
+  
+  /* KEEPALIVE counter */
+  u8_t keep_cnt;
+};
+
+struct tcp_pcb_listen {  
+/* Common members of all PCB types */
+  IP_PCB;
+
+/* Protocol specific PCB members */
+  struct tcp_pcb_listen *next;   /* for the linked list */
+  
+  /* Even if state is obviously LISTEN this is here for
+   * field compatibility with tpc_pcb to which it is cast sometimes
+   * Until a cleaner solution emerges this is here.FIXME
+   */ 
+  enum tcp_state state;   /* TCP state */
+
+  u8_t prio;
+  void *callback_arg;
+  
+  u16_t local_port; 
+
+#if LWIP_CALLBACK_API
+  /* Function to call when a listener has been connected. */
+  err_t (* accept)(void *arg, struct tcp_pcb *newpcb, err_t err);
+#endif /* LWIP_CALLBACK_API */
+};
+
+#if LWIP_EVENT_API
+
+enum lwip_event {
+  LWIP_EVENT_ACCEPT,
+  LWIP_EVENT_SENT,
+  LWIP_EVENT_RECV,
+  LWIP_EVENT_CONNECTED,
+  LWIP_EVENT_POLL,
+  LWIP_EVENT_ERR
+};
+
+err_t lwip_tcp_event(void *arg, struct tcp_pcb *pcb,
+         enum lwip_event,
+         struct pbuf *p,
+         u16_t size,
+         err_t err);
+
+#define TCP_EVENT_ACCEPT(pcb,err,ret)    ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+                LWIP_EVENT_ACCEPT, NULL, 0, err)
+#define TCP_EVENT_SENT(pcb,space,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+                   LWIP_EVENT_SENT, NULL, space, ERR_OK)
+#define TCP_EVENT_RECV(pcb,p,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+                LWIP_EVENT_RECV, (p), 0, (err))
+#define TCP_EVENT_CONNECTED(pcb,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+                LWIP_EVENT_CONNECTED, NULL, 0, (err))
+#define TCP_EVENT_POLL(pcb,ret)       ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+                LWIP_EVENT_POLL, NULL, 0, ERR_OK)
+#define TCP_EVENT_ERR(errf,arg,err)  lwip_tcp_event((arg), NULL, \
+                LWIP_EVENT_ERR, NULL, 0, (err))
+#else /* LWIP_EVENT_API */
+#define TCP_EVENT_ACCEPT(pcb,err,ret)     \
+                        if((pcb)->accept != NULL) \
+                        (ret = (pcb)->accept((pcb)->callback_arg,(pcb),(err)))
+#define TCP_EVENT_SENT(pcb,space,ret) \
+                        if((pcb)->sent != NULL) \
+                        (ret = (pcb)->sent((pcb)->callback_arg,(pcb),(space)))
+#define TCP_EVENT_RECV(pcb,p,err,ret) \
+                        if((pcb)->recv != NULL) \
+                        { ret = (pcb)->recv((pcb)->callback_arg,(pcb),(p),(err)); } else { \
+                          if (p) pbuf_free(p); }
+#define TCP_EVENT_CONNECTED(pcb,err,ret) \
+                        if((pcb)->connected != NULL) \
+                        (ret = (pcb)->connected((pcb)->callback_arg,(pcb),(err)))
+#define TCP_EVENT_POLL(pcb,ret) \
+                        if((pcb)->poll != NULL) \
+                        (ret = (pcb)->poll((pcb)->callback_arg,(pcb)))
+#define TCP_EVENT_ERR(errf,arg,err) \
+                        if((errf) != NULL) \
+                        (errf)((arg),(err))
+#endif /* LWIP_EVENT_API */
+
+/* This structure represents a TCP segment on the unsent and unacked queues */
+struct tcp_seg {
+  struct tcp_seg *next;    /* used when putting segements on a queue */
+  struct pbuf *p;          /* buffer containing data + TCP header */
+  void *dataptr;           /* pointer to the TCP data in the pbuf */
+  u16_t len;               /* the TCP length of this segment */
+  struct tcp_hdr *tcphdr;  /* the TCP header */
+};
+
+/* Internal functions and global variables: */
+struct tcp_pcb *tcp_pcb_copy(struct tcp_pcb *pcb);
+void tcp_pcb_purge(struct tcp_pcb *pcb);
+void tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb);
+
+u8_t tcp_segs_free(struct tcp_seg *seg);
+u8_t tcp_seg_free(struct tcp_seg *seg);
+struct tcp_seg *tcp_seg_copy(struct tcp_seg *seg);
+
+#define tcp_ack(pcb)     if((pcb)->flags & TF_ACK_DELAY) { \
+                            (pcb)->flags &= ~TF_ACK_DELAY; \
+                            (pcb)->flags |= TF_ACK_NOW; \
+                            tcp_output(pcb); \
+                         } else { \
+                            (pcb)->flags |= TF_ACK_DELAY; \
+                         }
+
+#define tcp_ack_now(pcb) (pcb)->flags |= TF_ACK_NOW; \
+                         tcp_output(pcb)
+
+err_t tcp_send_ctrl(struct tcp_pcb *pcb, u8_t flags);
+err_t tcp_enqueue(struct tcp_pcb *pcb, void *dataptr, u16_t len,
+    u8_t flags, u8_t copy,
+                u8_t *optdata, u8_t optlen);
+
+void tcp_rexmit_seg(struct tcp_pcb *pcb, struct tcp_seg *seg);
+
+void tcp_rst(u32_t seqno, u32_t ackno,
+       struct ip_addr *local_ip, struct ip_addr *remote_ip,
+       u16_t local_port, u16_t remote_port);
+
+u32_t tcp_next_iss(void);
+
+void tcp_keepalive(struct tcp_pcb *pcb);
+
+extern struct tcp_pcb *tcp_input_pcb;
+extern u32_t tcp_ticks;
+
+#if TCP_DEBUG || TCP_INPUT_DEBUG || TCP_OUTPUT_DEBUG
+void tcp_debug_print(struct tcp_hdr *tcphdr);
+void tcp_debug_print_flags(u8_t flags);
+void tcp_debug_print_state(enum tcp_state s);
+void tcp_debug_print_pcbs(void);
+int tcp_pcbs_sane(void);
+#else
+#  define tcp_debug_print(tcphdr)
+#  define tcp_debug_print_flags(flags)
+#  define tcp_debug_print_state(s)
+#  define tcp_debug_print_pcbs()
+#  define tcp_pcbs_sane() 1
+#endif /* TCP_DEBUG */
+
+#if NO_SYS
+#define tcp_timer_needed()
+#else
+void tcp_timer_needed(void);
+#endif
+
+/* The TCP PCB lists. */
+union tcp_listen_pcbs_t { /* List of all TCP PCBs in LISTEN state. */
+	struct tcp_pcb_listen *listen_pcbs; 
+	struct tcp_pcb *pcbs;
+};
+extern union tcp_listen_pcbs_t tcp_listen_pcbs;
+extern struct tcp_pcb *tcp_active_pcbs;  /* List of all TCP PCBs that are in a
+              state in which they accept or send
+              data. */
+extern struct tcp_pcb *tcp_tw_pcbs;      /* List of all TCP PCBs in TIME-WAIT. */
+
+extern struct tcp_pcb *tcp_tmp_pcb;      /* Only used for temporary storage. */
+
+/* Axioms about the above lists:   
+   1) Every TCP PCB that is not CLOSED is in one of the lists.
+   2) A PCB is only in one of the lists.
+   3) All PCBs in the tcp_listen_pcbs list is in LISTEN state.
+   4) All PCBs in the tcp_tw_pcbs list is in TIME-WAIT state.
+*/
+
+/* Define two macros, TCP_REG and TCP_RMV that registers a TCP PCB
+   with a PCB list or removes a PCB from a list, respectively. */
+#if 0
+#define TCP_REG(pcbs, npcb) do {\
+                            LWIP_DEBUGF(TCP_DEBUG, ("TCP_REG %p local port %d\n", npcb, npcb->local_port)); \
+                            for(tcp_tmp_pcb = *pcbs; \
+          tcp_tmp_pcb != NULL; \
+        tcp_tmp_pcb = tcp_tmp_pcb->next) { \
+                                LWIP_ASSERT("TCP_REG: already registered\n", tcp_tmp_pcb != npcb); \
+                            } \
+                            LWIP_ASSERT("TCP_REG: pcb->state != CLOSED", npcb->state != CLOSED); \
+                            npcb->next = *pcbs; \
+                            LWIP_ASSERT("TCP_REG: npcb->next != npcb", npcb->next != npcb); \
+                            *(pcbs) = npcb; \
+                            LWIP_ASSERT("TCP_RMV: tcp_pcbs sane", tcp_pcbs_sane()); \
+              tcp_timer_needed(); \
+                            } while(0)
+#define TCP_RMV(pcbs, npcb) do { \
+                            LWIP_ASSERT("TCP_RMV: pcbs != NULL", *pcbs != NULL); \
+                            LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removing %p from %p\n", npcb, *pcbs)); \
+                            if(*pcbs == npcb) { \
+                               *pcbs = (*pcbs)->next; \
+                            } else for(tcp_tmp_pcb = *pcbs; tcp_tmp_pcb != NULL; tcp_tmp_pcb = tcp_tmp_pcb->next) { \
+                               if(tcp_tmp_pcb->next != NULL && tcp_tmp_pcb->next == npcb) { \
+                                  tcp_tmp_pcb->next = npcb->next; \
+                                  break; \
+                               } \
+                            } \
+                            npcb->next = NULL; \
+                            LWIP_ASSERT("TCP_RMV: tcp_pcbs sane", tcp_pcbs_sane()); \
+                            LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removed %p from %p\n", npcb, *pcbs)); \
+                            } while(0)
+
+#else /* LWIP_DEBUG */
+#define TCP_REG(pcbs, npcb) do { \
+                            npcb->next = *pcbs; \
+                            *(pcbs) = npcb; \
+              tcp_timer_needed(); \
+                            } while(0)
+#define TCP_RMV(pcbs, npcb) do { \
+                            if(*(pcbs) == npcb) { \
+                               (*(pcbs)) = (*pcbs)->next; \
+                            } else for(tcp_tmp_pcb = *pcbs; tcp_tmp_pcb != NULL; tcp_tmp_pcb = tcp_tmp_pcb->next) { \
+                               if(tcp_tmp_pcb->next != NULL && tcp_tmp_pcb->next == npcb) { \
+                                  tcp_tmp_pcb->next = npcb->next; \
+                                  break; \
+                               } \
+                            } \
+                            npcb->next = NULL; \
+                            } while(0)
+#endif /* LWIP_DEBUG */
+#endif /* __LWIP_TCP_H__ */
+
+
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/tcpip.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/tcpip.h
new file mode 100644
index 000000000..242664ef7
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/tcpip.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_TCPIP_H__
+#define __LWIP_TCPIP_H__
+
+#include "lwip/api_msg.h"
+#include "lwip/pbuf.h"
+
+void tcpip_init(void (* tcpip_init_done)(void *), void *arg);
+void tcpip_apimsg(struct api_msg *apimsg);
+err_t tcpip_input(struct pbuf *p, struct netif *inp);
+err_t tcpip_callback(void (*f)(void *ctx), void *ctx);
+
+void tcpip_tcp_timer_needed(void);
+
+enum tcpip_msg_type {
+  TCPIP_MSG_API,
+  TCPIP_MSG_INPUT,
+  TCPIP_MSG_CALLBACK
+};
+
+struct tcpip_msg {
+  enum tcpip_msg_type type;
+  sys_sem_t *sem;
+  union {
+    struct api_msg *apimsg;
+    struct {
+      struct pbuf *p;
+      struct netif *netif;
+    } inp;
+    struct {
+      void (*f)(void *ctx);
+      void *ctx;
+    } cb;
+  } msg;
+};
+
+
+#endif /* __LWIP_TCPIP_H__ */
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/udp.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/udp.h
new file mode 100644
index 000000000..c9d7958d8
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/udp.h
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_UDP_H__
+#define __LWIP_UDP_H__
+
+#include "lwip/arch.h"
+
+#include "lwip/pbuf.h"
+#include "lwip/inet.h"
+#include "lwip/ip.h"
+
+#define UDP_HLEN 8
+
+struct udp_hdr {
+  PACK_STRUCT_FIELD(u16_t src);
+  PACK_STRUCT_FIELD(u16_t dest);  /* src/dest UDP ports */
+  PACK_STRUCT_FIELD(u16_t len);
+  PACK_STRUCT_FIELD(u16_t chksum);
+} PACK_STRUCT_STRUCT;
+
+#define UDP_FLAGS_NOCHKSUM 0x01U
+#define UDP_FLAGS_UDPLITE  0x02U
+#define UDP_FLAGS_CONNECTED  0x04U
+
+struct udp_pcb {
+/* Common members of all PCB types */
+  IP_PCB;
+
+/* Protocol specific PCB members */
+
+  struct udp_pcb *next;
+
+  u8_t flags;
+  u16_t local_port, remote_port;
+  
+  u16_t chksum_len;
+  
+  void (* recv)(void *arg, struct udp_pcb *pcb, struct pbuf *p,
+    struct ip_addr *addr, u16_t port);
+  void *recv_arg;  
+};
+
+/* The following functions is the application layer interface to the
+   UDP code. */
+struct udp_pcb * udp_new        (void);
+void             udp_remove     (struct udp_pcb *pcb);
+err_t            udp_bind       (struct udp_pcb *pcb, struct ip_addr *ipaddr,
+                 u16_t port);
+err_t            udp_connect    (struct udp_pcb *pcb, struct ip_addr *ipaddr,
+                 u16_t port);
+void             udp_disconnect    (struct udp_pcb *pcb);
+void             udp_recv       (struct udp_pcb *pcb,
+         void (* recv)(void *arg, struct udp_pcb *upcb,
+                 struct pbuf *p,
+                 struct ip_addr *addr,
+                 u16_t port),
+         void *recv_arg);
+err_t            udp_sendto     (struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *dst_ip, u16_t dst_port);
+err_t            udp_send       (struct udp_pcb *pcb, struct pbuf *p);
+
+#define          udp_flags(pcb)  ((pcb)->flags)
+#define          udp_setflags(pcb, f)  ((pcb)->flags = (f))
+
+/* The following functions are the lower layer interface to UDP. */
+void             udp_input      (struct pbuf *p, struct netif *inp);
+void             udp_init       (void);
+
+#if UDP_DEBUG
+int udp_debug_print(struct udp_hdr *udphdr);
+#else
+#define udp_debug_print(udphdr)
+#endif
+#endif /* __LWIP_UDP_H__ */
+
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/netif/etharp.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/netif/etharp.h
new file mode 100644
index 000000000..26fa3effb
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/netif/etharp.h
@@ -0,0 +1,126 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * Copyright (c) 2003-2004 Leon Woestenberg 
+ * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#ifndef __NETIF_ETHARP_H__
+#define __NETIF_ETHARP_H__
+
+#ifndef ETH_PAD_SIZE
+#define ETH_PAD_SIZE 0
+#endif
+
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/ip.h"
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct eth_addr {
+  PACK_STRUCT_FIELD(u8_t addr[6]);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct eth_hdr {
+#if ETH_PAD_SIZE
+  PACK_STRUCT_FIELD(u8_t padding[ETH_PAD_SIZE]);
+#endif
+  PACK_STRUCT_FIELD(struct eth_addr dest);
+  PACK_STRUCT_FIELD(struct eth_addr src);
+  PACK_STRUCT_FIELD(u16_t type);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+/** the ARP message */
+struct etharp_hdr {
+  PACK_STRUCT_FIELD(struct eth_hdr ethhdr);
+  PACK_STRUCT_FIELD(u16_t hwtype);
+  PACK_STRUCT_FIELD(u16_t proto);
+  PACK_STRUCT_FIELD(u16_t _hwlen_protolen);
+  PACK_STRUCT_FIELD(u16_t opcode);
+  PACK_STRUCT_FIELD(struct eth_addr shwaddr);
+  PACK_STRUCT_FIELD(struct ip_addr2 sipaddr);
+  PACK_STRUCT_FIELD(struct eth_addr dhwaddr);
+  PACK_STRUCT_FIELD(struct ip_addr2 dipaddr);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ethip_hdr {
+  PACK_STRUCT_FIELD(struct eth_hdr eth);
+  PACK_STRUCT_FIELD(struct ip_hdr ip);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/** 5 seconds period */
+#define ARP_TMR_INTERVAL 5000
+
+#define ETHTYPE_ARP 0x0806
+#define ETHTYPE_IP  0x0800
+
+void etharp_init(void);
+void etharp_tmr(void);
+void etharp_ip_input(struct netif *netif, struct pbuf *p);
+void etharp_arp_input(struct netif *netif, struct eth_addr *ethaddr,
+         struct pbuf *p);
+err_t etharp_output(struct netif *netif, struct ip_addr *ipaddr,
+         struct pbuf *q);
+err_t etharp_query(struct netif *netif, struct ip_addr *ipaddr, struct pbuf *q);
+err_t etharp_request(struct netif *netif, struct ip_addr *ipaddr);
+
+#endif /* __NETIF_ARP_H__ */
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/netif/loopif.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/netif/loopif.h
new file mode 100644
index 000000000..7fd548733
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/netif/loopif.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __NETIF_LOOPIF_H__
+#define __NETIF_LOOPIF_H__
+
+#include "lwip/netif.h"
+
+err_t loopif_init(struct netif *netif);
+
+#endif /* __NETIF_LOOPIF_H__ */
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/netif/slipif.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/netif/slipif.h
new file mode 100644
index 000000000..d9060fc97
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/netif/slipif.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2001, Swedish Institute of Computer Science.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. Neither the name of the Institute nor the names of its contributors 
+ *    may be used to endorse or promote products derived from this software 
+ *    without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
+ * SUCH DAMAGE. 
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __NETIF_SLIPIF_H__
+#define __NETIF_SLIPIF_H__
+
+#include "lwip/netif.h"
+
+err_t slipif_init(struct netif * netif);
+ 
+#endif 
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/FILES b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/FILES
new file mode 100644
index 000000000..825d40715
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/FILES
@@ -0,0 +1,27 @@
+This directory contains generic network interface device drivers that
+do not contain any hardware or architecture specific code. The files
+are:
+
+etharp.c
+          Implements the ARP (Address Resolution Protocol) over
+          Ethernet. The code in this file should be used together with
+          Ethernet device drivers. Note that this module has been
+          largely made Ethernet independent so you should be able to
+          adapt this for other link layers (such as Firewire).
+
+ethernetif.c
+          An example of how an Ethernet device driver could look. This
+          file can be used as a "skeleton" for developing new Ethernet
+          network device drivers. It uses the etharp.c ARP code.
+
+loopif.c
+          An example network interface that shows how a "loopback"
+          interface would work. This is not really intended for actual
+          use, but as a very basic example of how initialization and
+          output functions work.
+
+slipif.c
+          A generic implementation of the SLIP (Serial Line IP)
+          protocol. It requires a sio (serial I/O) module to work.
+	  
+ppp/      Point-to-Point Protocol stack
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/etharp.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/etharp.c
new file mode 100644
index 000000000..11f4973bd
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/etharp.c
@@ -0,0 +1,828 @@
+/**
+ * @file
+ * Address Resolution Protocol module for IP over Ethernet
+ *
+ * Functionally, ARP is divided into two parts. The first maps an IP address
+ * to a physical address when sending a packet, and the second part answers
+ * requests from other machines for our physical address.
+ *
+ * This implementation complies with RFC 826 (Ethernet ARP). It supports
+ * Gratuitious ARP from RFC3220 (IP Mobility Support for IPv4) section 4.6
+ * if an interface calls etharp_query(our_netif, its_ip_addr, NULL) upon
+ * address change.
+ */
+
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * Copyright (c) 2003-2004 Leon Woestenberg 
+ * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#include "lwip/opt.h"
+#include "lwip/inet.h"
+#include "netif/etharp.h"
+#include "lwip/ip.h"
+#include "lwip/stats.h"
+
+/* ARP needs to inform DHCP of any ARP replies? */
+#if (LWIP_DHCP && DHCP_DOES_ARP_CHECK)
+#  include "lwip/dhcp.h"
+#endif
+
+/** the time an ARP entry stays valid after its last update,
+ * (240 * 5) seconds = 20 minutes.
+ */
+#define ARP_MAXAGE 240
+/** the time an ARP entry stays pending after first request,
+ * (2 * 5) seconds = 10 seconds.
+ * 
+ * @internal Keep this number at least 2, otherwise it might
+ * run out instantly if the timeout occurs directly after a request.
+ */
+#define ARP_MAXPENDING 2
+
+#define HWTYPE_ETHERNET 1
+
+/** ARP message types */
+#define ARP_REQUEST 1
+#define ARP_REPLY 2
+
+#define ARPH_HWLEN(hdr) (ntohs((hdr)->_hwlen_protolen) >> 8)
+#define ARPH_PROTOLEN(hdr) (ntohs((hdr)->_hwlen_protolen) & 0xff)
+
+#define ARPH_HWLEN_SET(hdr, len) (hdr)->_hwlen_protolen = htons(ARPH_PROTOLEN(hdr) | ((len) << 8))
+#define ARPH_PROTOLEN_SET(hdr, len) (hdr)->_hwlen_protolen = htons((len) | (ARPH_HWLEN(hdr) << 8))
+
+enum etharp_state {
+  ETHARP_STATE_EMPTY,
+  ETHARP_STATE_PENDING,
+  ETHARP_STATE_STABLE,
+  /** @internal transitional state used in etharp_tmr() for convenience*/
+  ETHARP_STATE_EXPIRED
+};
+
+struct etharp_entry {
+#if ARP_QUEUEING
+  /** 
+   * Pointer to queue of pending outgoing packets on this ARP entry.
+   */
+   struct pbuf *p;
+#endif
+  struct ip_addr ipaddr;
+  struct eth_addr ethaddr;
+  enum etharp_state state;
+  u8_t ctime;
+};
+
+static const struct eth_addr ethbroadcast = {{0xff,0xff,0xff,0xff,0xff,0xff}};
+static struct etharp_entry arp_table[ARP_TABLE_SIZE];
+
+/**
+ * Try hard to create a new entry - we want the IP address to appear in
+ * the cache (even if this means removing an active entry or so). */
+#define ETHARP_TRY_HARD 1
+
+static s8_t find_entry(struct ip_addr *ipaddr, u8_t flags);
+static err_t update_arp_entry(struct netif *netif, struct ip_addr *ipaddr, struct eth_addr *ethaddr, u8_t flags);
+/**
+ * Initializes ARP module.
+ */
+void
+etharp_init(void)
+{
+  u8_t i;
+  /* clear ARP entries */
+  for(i = 0; i < ARP_TABLE_SIZE; ++i) {
+    arp_table[i].state = ETHARP_STATE_EMPTY;
+#if ARP_QUEUEING
+    arp_table[i].p = NULL;
+#endif
+    arp_table[i].ctime = 0;
+  }
+}
+
+/**
+ * Clears expired entries in the ARP table.
+ *
+ * This function should be called every ETHARP_TMR_INTERVAL microseconds (5 seconds),
+ * in order to expire entries in the ARP table.
+ */
+void
+etharp_tmr(void)
+{
+  u8_t i;
+
+  LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer\n"));
+  /* remove expired entries from the ARP table */
+  for (i = 0; i < ARP_TABLE_SIZE; ++i) {
+    arp_table[i].ctime++;
+    /* stable entry? */
+    if ((arp_table[i].state == ETHARP_STATE_STABLE) &&
+         /* entry has become old? */
+        (arp_table[i].ctime >= ARP_MAXAGE)) {
+      LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: expired stable entry %u.\n", i));
+      arp_table[i].state = ETHARP_STATE_EXPIRED;
+    /* pending entry? */
+    } else if (arp_table[i].state == ETHARP_STATE_PENDING) {
+      /* entry unresolved/pending for too long? */
+      if (arp_table[i].ctime >= ARP_MAXPENDING) {
+        LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: expired pending entry %u.\n", i));
+        arp_table[i].state = ETHARP_STATE_EXPIRED;
+#if ARP_QUEUEING
+      } else if (arp_table[i].p != NULL) {
+        /* resend an ARP query here */
+#endif
+      }
+    }
+    /* clean up entries that have just been expired */
+    if (arp_table[i].state == ETHARP_STATE_EXPIRED) {
+#if ARP_QUEUEING
+      /* and empty packet queue */
+      if (arp_table[i].p != NULL) {
+        /* remove all queued packets */
+        LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: freeing entry %u, packet queue %p.\n", i, (void *)(arp_table[i].p)));
+        pbuf_free(arp_table[i].p);
+        arp_table[i].p = NULL;
+      }
+#endif
+      /* recycle entry for re-use */      
+      arp_table[i].state = ETHARP_STATE_EMPTY;
+    }
+  }
+}
+
+/**
+ * Search the ARP table for a matching or new entry.
+ * 
+ * If an IP address is given, return a pending or stable ARP entry that matches
+ * the address. If no match is found, create a new entry with this address set,
+ * but in state ETHARP_EMPTY. The caller must check and possibly change the
+ * state of the returned entry.
+ * 
+ * If ipaddr is NULL, return a initialized new entry in state ETHARP_EMPTY.
+ * 
+ * In all cases, attempt to create new entries from an empty entry. If no
+ * empty entries are available and ETHARP_TRY_HARD flag is set, recycle
+ * old entries. Heuristic choose the least important entry for recycling.
+ *
+ * @param ipaddr IP address to find in ARP cache, or to add if not found.
+ * @param flags
+ * - ETHARP_TRY_HARD: Try hard to create a entry by allowing recycling of
+ * active (stable or pending) entries.
+ *  
+ * @return The ARP entry index that matched or is created, ERR_MEM if no
+ * entry is found or could be recycled.
+ */
+static s8_t find_entry(struct ip_addr *ipaddr, u8_t flags)
+{
+  s8_t old_pending = ARP_TABLE_SIZE, old_stable = ARP_TABLE_SIZE;
+  s8_t empty = ARP_TABLE_SIZE;
+  u8_t i = 0, age_pending = 0, age_stable = 0;
+#if ARP_QUEUEING
+  /* oldest entry with packets on queue */
+  s8_t old_queue = ARP_TABLE_SIZE;
+  /* its age */
+  u8_t age_queue = 0;
+#endif
+
+  /**
+   * a) do a search through the cache, remember candidates
+   * b) select candidate entry
+   * c) create new entry
+   */
+
+  /* a) in a single search sweep, do all of this
+   * 1) remember the first empty entry (if any)
+   * 2) remember the oldest stable entry (if any)
+   * 3) remember the oldest pending entry without queued packets (if any)
+   * 4) remember the oldest pending entry with queued packets (if any)
+   * 5) search for a matching IP entry, either pending or stable
+   *    until 5 matches, or all entries are searched for.
+   */
+
+  for (i = 0; i < ARP_TABLE_SIZE; ++i) {
+    /* no empty entry found yet and now we do find one? */
+    if ((empty == ARP_TABLE_SIZE) && (arp_table[i].state == ETHARP_STATE_EMPTY)) {
+      LWIP_DEBUGF(ETHARP_DEBUG, ("find_entry: found empty entry %d\n", i));
+      /* remember first empty entry */
+      empty = i;
+    }
+    /* pending entry? */
+    else if (arp_table[i].state == ETHARP_STATE_PENDING) {
+      /* if given, does IP address match IP address in ARP entry? */
+      if (ipaddr && ip_addr_cmp(ipaddr, &arp_table[i].ipaddr)) {
+        LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: found matching pending entry %d\n", i));
+        /* found exact IP address match, simply bail out */
+        return i;
+#if ARP_QUEUEING
+      /* pending with queued packets? */
+      } else if (arp_table[i].p != NULL) {
+        if (arp_table[i].ctime >= age_queue) {
+          old_queue = i;
+          age_queue = arp_table[i].ctime;
+        }
+#endif
+      /* pending without queued packets? */
+      } else {
+        if (arp_table[i].ctime >= age_pending) {
+          old_pending = i;
+          age_pending = arp_table[i].ctime;
+        }
+      }        
+    }
+    /* stable entry? */
+    else if (arp_table[i].state == ETHARP_STATE_STABLE) {
+      /* if given, does IP address match IP address in ARP entry? */
+      if (ipaddr && ip_addr_cmp(ipaddr, &arp_table[i].ipaddr)) {
+        LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: found matching stable entry %d\n", i));
+        /* found exact IP address match, simply bail out */
+        return i;
+      /* remember entry with oldest stable entry in oldest, its age in maxtime */
+      } else if (arp_table[i].ctime >= age_stable) {
+        old_stable = i;
+        age_stable = arp_table[i].ctime;
+      }
+    }
+  }
+  /* { we have no match } => try to create a new entry */
+   
+  /* no empty entry found and not allowed to recycle? */
+  if ((empty == ARP_TABLE_SIZE) && ((flags & ETHARP_TRY_HARD) == 0))
+  {
+  	return (s8_t)ERR_MEM;
+  }
+  
+  /* b) choose the least destructive entry to recycle:
+   * 1) empty entry
+   * 2) oldest stable entry
+   * 3) oldest pending entry without queued packets
+   * 4) oldest pending entry without queued packets
+   * 
+   * { ETHARP_TRY_HARD is set at this point }
+   */ 
+
+  /* 1) empty entry available? */
+  if (empty < ARP_TABLE_SIZE) {
+    i = empty;
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: selecting empty entry %d\n", i));
+  }
+  /* 2) found recyclable stable entry? */
+  else if (old_stable < ARP_TABLE_SIZE) {
+    /* recycle oldest stable*/
+    i = old_stable;
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: selecting oldest stable entry %d\n", i));
+#if ARP_QUEUEING
+    /* no queued packets should exist on stable entries */
+    LWIP_ASSERT("arp_table[i].p == NULL", arp_table[i].p == NULL);
+#endif
+  /* 3) found recyclable pending entry without queued packets? */
+  } else if (old_pending < ARP_TABLE_SIZE) {
+    /* recycle oldest pending */
+    i = old_pending;
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: selecting oldest pending entry %d (without queue)\n", i));
+#if ARP_QUEUEING
+  /* 4) found recyclable pending entry with queued packets? */
+  } else if (old_queue < ARP_TABLE_SIZE) {
+    /* recycle oldest pending */
+    i = old_queue;
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: selecting oldest pending entry %d, freeing packet queue %p\n", i, (void *)(arp_table[i].p)));
+    pbuf_free(arp_table[i].p);
+    arp_table[i].p = NULL;
+#endif
+    /* no empty or recyclable entries found */
+  } else {
+    return (s8_t)ERR_MEM;
+  }
+
+  /* { empty or recyclable entry found } */
+  LWIP_ASSERT("i < ARP_TABLE_SIZE", i < ARP_TABLE_SIZE);
+
+  /* recycle entry (no-op for an already empty entry) */
+  arp_table[i].state = ETHARP_STATE_EMPTY;
+
+  /* IP address given? */
+  if (ipaddr != NULL) {
+    /* set IP address */
+    ip_addr_set(&arp_table[i].ipaddr, ipaddr);
+  }
+  arp_table[i].ctime = 0;
+  return (err_t)i;
+}
+
+/**
+ * Update (or insert) a IP/MAC address pair in the ARP cache.
+ *
+ * If a pending entry is resolved, any queued packets will be sent
+ * at this point.
+ * 
+ * @param ipaddr IP address of the inserted ARP entry.
+ * @param ethaddr Ethernet address of the inserted ARP entry.
+ * @param flags Defines behaviour:
+ * - ETHARP_TRY_HARD Allows ARP to insert this as a new item. If not specified,
+ * only existing ARP entries will be updated.
+ *
+ * @return
+ * - ERR_OK Succesfully updated ARP cache.
+ * - ERR_MEM If we could not add a new ARP entry when ETHARP_TRY_HARD was set.
+ * - ERR_ARG Non-unicast address given, those will not appear in ARP cache.
+ *
+ * @see pbuf_free()
+ */
+static err_t
+update_arp_entry(struct netif *netif, struct ip_addr *ipaddr, struct eth_addr *ethaddr, u8_t flags)
+{
+  s8_t i, k;
+  LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 3, ("update_arp_entry()\n"));
+  LWIP_ASSERT("netif->hwaddr_len != 0", netif->hwaddr_len != 0);
+  LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: %u.%u.%u.%u - %02x:%02x:%02x:%02x:%02x:%02x\n",
+                                        ip4_addr1(ipaddr), ip4_addr2(ipaddr), ip4_addr3(ipaddr), ip4_addr4(ipaddr), 
+                                        ethaddr->addr[0], ethaddr->addr[1], ethaddr->addr[2],
+                                        ethaddr->addr[3], ethaddr->addr[4], ethaddr->addr[5]));
+  /* non-unicast address? */
+  if (ip_addr_isany(ipaddr) ||
+      ip_addr_isbroadcast(ipaddr, netif) ||
+      ip_addr_ismulticast(ipaddr)) {
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: will not add non-unicast IP address to ARP cache\n"));
+    return ERR_ARG;
+  }
+  /* find or create ARP entry */
+  i = find_entry(ipaddr, flags);
+  /* bail out if no entry could be found */
+  if (i < 0) return (err_t)i;
+  
+  /* mark it stable */
+  arp_table[i].state = ETHARP_STATE_STABLE;
+
+  LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: updating stable entry %u\n", i));
+  /* update address */
+  for (k = 0; k < netif->hwaddr_len; ++k) {
+    arp_table[i].ethaddr.addr[k] = ethaddr->addr[k];
+  }
+  /* reset time stamp */
+  arp_table[i].ctime = 0;
+/* this is where we will send out queued packets! */
+#if ARP_QUEUEING
+  while (arp_table[i].p != NULL) {
+    /* get the first packet on the queue */
+    struct pbuf *p = arp_table[i].p;
+    /* Ethernet header */
+    struct eth_hdr *ethhdr = p->payload;
+    /* remember (and reference) remainder of queue */
+    /* note: this will also terminate the p pbuf chain */
+    arp_table[i].p = pbuf_dequeue(p);
+    /* fill-in Ethernet header */
+    for (k = 0; k < netif->hwaddr_len; ++k) {
+      ethhdr->dest.addr[k] = ethaddr->addr[k];
+      ethhdr->src.addr[k] = netif->hwaddr[k];
+    }
+    ethhdr->type = htons(ETHTYPE_IP);
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: sending queued IP packet %p.\n", (void *)p));
+    /* send the queued IP packet */
+    netif->linkoutput(netif, p);
+    /* free the queued IP packet */
+    pbuf_free(p);
+  }
+#endif
+  return ERR_OK;
+}
+
+/**
+ * Updates the ARP table using the given IP packet.
+ *
+ * Uses the incoming IP packet's source address to update the
+ * ARP cache for the local network. The function does not alter
+ * or free the packet. This function must be called before the
+ * packet p is passed to the IP layer.
+ *
+ * @param netif The lwIP network interface on which the IP packet pbuf arrived.
+ * @param pbuf The IP packet that arrived on netif.
+ *
+ * @return NULL
+ *
+ * @see pbuf_free()
+ */
+void
+etharp_ip_input(struct netif *netif, struct pbuf *p)
+{
+  struct ethip_hdr *hdr;
+
+  /* Only insert an entry if the source IP address of the
+     incoming IP packet comes from a host on the local network. */
+  hdr = p->payload;
+  /* source is not on the local network? */
+  if (!ip_addr_netcmp(&(hdr->ip.src), &(netif->ip_addr), &(netif->netmask))) {
+    /* do nothing */
+    return;
+  }
+
+  LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_ip_input: updating ETHARP table.\n"));
+  /* update ARP table */
+  /* @todo We could use ETHARP_TRY_HARD if we think we are going to talk
+   * back soon (for example, if the destination IP address is ours. */
+  update_arp_entry(netif, &(hdr->ip.src), &(hdr->eth.src), 0);
+}
+
+
+/**
+ * Responds to ARP requests to us. Upon ARP replies to us, add entry to cache  
+ * send out queued IP packets. Updates cache with snooped address pairs.
+ *
+ * Should be called for incoming ARP packets. The pbuf in the argument
+ * is freed by this function.
+ *
+ * @param netif The lwIP network interface on which the ARP packet pbuf arrived.
+ * @param pbuf The ARP packet that arrived on netif. Is freed by this function.
+ * @param ethaddr Ethernet address of netif.
+ *
+ * @return NULL
+ *
+ * @see pbuf_free()
+ */
+void
+etharp_arp_input(struct netif *netif, struct eth_addr *ethaddr, struct pbuf *p)
+{
+  struct etharp_hdr *hdr;
+  /* these are aligned properly, whereas the ARP header fields might not be */
+  struct ip_addr sipaddr, dipaddr;
+  u8_t i;
+  u8_t for_us;
+
+  /* drop short ARP packets */
+  if (p->tot_len < sizeof(struct etharp_hdr)) {
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 1, ("etharp_arp_input: packet dropped, too short (%d/%d)\n", p->tot_len, sizeof(struct etharp_hdr)));
+    pbuf_free(p);
+    return;
+  }
+
+  hdr = p->payload;
+ 
+  /* get aligned copies of addresses */
+  *(struct ip_addr2 *)&sipaddr = hdr->sipaddr;
+  *(struct ip_addr2 *)&dipaddr = hdr->dipaddr;
+
+  /* this interface is not configured? */
+  if (netif->ip_addr.addr == 0) {
+    for_us = 0;
+  } else {
+    /* ARP packet directed to us? */
+    for_us = ip_addr_cmp(&dipaddr, &(netif->ip_addr));
+  }
+
+  /* ARP message directed to us? */
+  if (for_us) {
+    /* add IP address in ARP cache; assume requester wants to talk to us.
+     * can result in directly sending the queued packets for this host. */
+    update_arp_entry(netif, &sipaddr, &(hdr->shwaddr), ETHARP_TRY_HARD);
+  /* ARP message not directed to us? */
+  } else {
+    /* update the source IP address in the cache, if present */
+    update_arp_entry(netif, &sipaddr, &(hdr->shwaddr), 0);
+  }
+
+  /* now act on the message itself */
+  switch (htons(hdr->opcode)) {
+  /* ARP request? */
+  case ARP_REQUEST:
+    /* ARP request. If it asked for our address, we send out a
+     * reply. In any case, we time-stamp any existing ARP entry,
+     * and possiby send out an IP packet that was queued on it. */
+
+    LWIP_DEBUGF (ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: incoming ARP request\n"));
+    /* ARP request for our address? */
+    if (for_us) {
+
+      LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: replying to ARP request for our IP address\n"));
+      /* re-use pbuf to send ARP reply */
+      hdr->opcode = htons(ARP_REPLY);
+
+      hdr->dipaddr = hdr->sipaddr;
+      hdr->sipaddr = *(struct ip_addr2 *)&netif->ip_addr;
+
+      for(i = 0; i < netif->hwaddr_len; ++i) {
+        hdr->dhwaddr.addr[i] = hdr->shwaddr.addr[i];
+        hdr->shwaddr.addr[i] = ethaddr->addr[i];
+        hdr->ethhdr.dest.addr[i] = hdr->dhwaddr.addr[i];
+        hdr->ethhdr.src.addr[i] = ethaddr->addr[i];
+      }
+
+      hdr->hwtype = htons(HWTYPE_ETHERNET);
+      ARPH_HWLEN_SET(hdr, netif->hwaddr_len);
+
+      hdr->proto = htons(ETHTYPE_IP);
+      ARPH_PROTOLEN_SET(hdr, sizeof(struct ip_addr));
+
+      hdr->ethhdr.type = htons(ETHTYPE_ARP);
+      /* return ARP reply */
+      netif->linkoutput(netif, p);
+    /* we are not configured? */
+    } else if (netif->ip_addr.addr == 0) {
+      /* { for_us == 0 and netif->ip_addr.addr == 0 } */
+      LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: we are unconfigured, ARP request ignored.\n"));
+    /* request was not directed to us */
+    } else {
+      /* { for_us == 0 and netif->ip_addr.addr != 0 } */
+      LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: ARP request was not for us.\n"));
+    }
+    break;
+  case ARP_REPLY:
+    /* ARP reply. We already updated the ARP cache earlier. */
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: incoming ARP reply\n"));
+#if (LWIP_DHCP && DHCP_DOES_ARP_CHECK)
+    /* When unconfigured, DHCP wants to know about ARP replies from the
+     * address offered to us, as that means someone else uses it already! */
+    if (netif->ip_addr.addr == 0) dhcp_arp_reply(netif, &sipaddr);
+#endif
+    break;
+  default:
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: ARP unknown opcode type %d\n", htons(hdr->opcode)));
+    break;
+  }
+  /* free ARP packet */
+  pbuf_free(p);
+}
+
+/**
+ * Resolve and fill-in Ethernet address header for outgoing packet.
+ *
+ * For IP multicast and broadcast, corresponding Ethernet addresses
+ * are selected and the packet is transmitted on the link.
+ *
+ * For unicast addresses, the packet is submitted to etharp_query(). In
+ * case the IP address is outside the local network, the IP address of
+ * the gateway is used.
+ *
+ * @param netif The lwIP network interface which the IP packet will be sent on.
+ * @param ipaddr The IP address of the packet destination.
+ * @param pbuf The pbuf(s) containing the IP packet to be sent.
+ *
+ * @return
+ * - ERR_RTE No route to destination (no gateway to external networks),
+ * or the return type of either etharp_query() or netif->linkoutput().
+ */
+err_t
+etharp_output(struct netif *netif, struct ip_addr *ipaddr, struct pbuf *q)
+{
+  struct eth_addr *dest, *srcaddr, mcastaddr;
+  struct eth_hdr *ethhdr;
+  u8_t i;
+
+  /* make room for Ethernet header - should not fail */
+  if (pbuf_header(q, sizeof(struct eth_hdr)) != 0) {
+    /* bail out */
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 2, ("etharp_output: could not allocate room for header.\n"));
+    LINK_STATS_INC(link.lenerr);
+    return ERR_BUF;
+  }
+
+  /* assume unresolved Ethernet address */
+  dest = NULL;
+  /* Determine on destination hardware address. Broadcasts and multicasts
+   * are special, other IP addresses are looked up in the ARP table. */
+
+  /* broadcast destination IP address? */
+  if (ip_addr_isbroadcast(ipaddr, netif)) {
+    /* broadcast on Ethernet also */
+    dest = (struct eth_addr *)ðbroadcast;
+  /* multicast destination IP address? */
+  } else if (ip_addr_ismulticast(ipaddr)) {
+    /* Hash IP multicast address to MAC address.*/
+    mcastaddr.addr[0] = 0x01;
+    mcastaddr.addr[1] = 0x00;
+    mcastaddr.addr[2] = 0x5e;
+    mcastaddr.addr[3] = ip4_addr2(ipaddr) & 0x7f;
+    mcastaddr.addr[4] = ip4_addr3(ipaddr);
+    mcastaddr.addr[5] = ip4_addr4(ipaddr);
+    /* destination Ethernet address is multicast */
+    dest = &mcastaddr;
+  /* unicast destination IP address? */
+  } else {
+    /* outside local network? */
+    if (!ip_addr_netcmp(ipaddr, &(netif->ip_addr), &(netif->netmask))) {
+      /* interface has default gateway? */
+      if (netif->gw.addr != 0) {
+        /* send to hardware address of default gateway IP address */
+        ipaddr = &(netif->gw);
+      /* no default gateway available */
+      } else {
+        /* no route to destination error (default gateway missing) */
+        return ERR_RTE;
+      }
+    }
+    /* queue on destination Ethernet address belonging to ipaddr */
+    return etharp_query(netif, ipaddr, q);
+  }
+
+  /* continuation for multicast/broadcast destinations */
+  /* obtain source Ethernet address of the given interface */
+  srcaddr = (struct eth_addr *)netif->hwaddr;
+  ethhdr = q->payload;
+  for (i = 0; i < netif->hwaddr_len; i++) {
+    ethhdr->dest.addr[i] = dest->addr[i];
+    ethhdr->src.addr[i] = srcaddr->addr[i];
+  }
+  ethhdr->type = htons(ETHTYPE_IP);
+  /* send packet directly on the link */
+  return netif->linkoutput(netif, q);
+}
+
+/**
+ * Send an ARP request for the given IP address and/or queue a packet.
+ *
+ * If the IP address was not yet in the cache, a pending ARP cache entry
+ * is added and an ARP request is sent for the given address. The packet
+ * is queued on this entry.
+ *
+ * If the IP address was already pending in the cache, a new ARP request
+ * is sent for the given address. The packet is queued on this entry.
+ *
+ * If the IP address was already stable in the cache, and a packet is
+ * given, it is directly sent and no ARP request is sent out. 
+ * 
+ * If the IP address was already stable in the cache, and no packet is
+ * given, an ARP request is sent out.
+ * 
+ * @param netif The lwIP network interface on which ipaddr
+ * must be queried for.
+ * @param ipaddr The IP address to be resolved.
+ * @param q If non-NULL, a pbuf that must be delivered to the IP address.
+ * q is not freed by this function.
+ *
+ * @return
+ * - ERR_BUF Could not make room for Ethernet header.
+ * - ERR_MEM Hardware address unknown, and no more ARP entries available
+ *   to query for address or queue the packet.
+ * - ERR_MEM Could not queue packet due to memory shortage.
+ * - ERR_RTE No route to destination (no gateway to external networks).
+ * - ERR_ARG Non-unicast address given, those will not appear in ARP cache.
+ *
+ */
+err_t etharp_query(struct netif *netif, struct ip_addr *ipaddr, struct pbuf *q)
+{
+  struct pbuf *p;
+  struct eth_addr * srcaddr = (struct eth_addr *)netif->hwaddr;
+  err_t result = ERR_MEM;
+  s8_t i; /* ARP entry index */
+  u8_t k; /* Ethernet address octet index */
+
+  /* non-unicast address? */
+  if (ip_addr_isbroadcast(ipaddr, netif) ||
+      ip_addr_ismulticast(ipaddr) ||
+      ip_addr_isany(ipaddr)) {
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: will not add non-unicast IP address to ARP cache\n"));
+    return ERR_ARG;
+  }
+
+  /* find entry in ARP cache, ask to create entry if queueing packet */
+  i = find_entry(ipaddr, ETHARP_TRY_HARD);
+
+  /* could not find or create entry? */
+  if (i < 0)
+  {
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: could not create ARP entry\n"));
+	#ifdef LWIP_DEBUG
+    if (q) LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: packet dropped\n"));
+	#endif
+    return (err_t)i;
+  }
+
+  /* mark a fresh entry as pending (we just sent a request) */
+  if (arp_table[i].state == ETHARP_STATE_EMPTY) {
+    arp_table[i].state = ETHARP_STATE_PENDING;
+  }
+
+  /* { i is either a STABLE or (new or existing) PENDING entry } */
+  LWIP_ASSERT("arp_table[i].state == PENDING or STABLE",
+  ((arp_table[i].state == ETHARP_STATE_PENDING) ||
+   (arp_table[i].state == ETHARP_STATE_STABLE)));
+
+  /* do we have a pending entry? or an implicit query request? */
+  if ((arp_table[i].state == ETHARP_STATE_PENDING) || (q == NULL)) {
+    /* try to resolve it; send out ARP request */
+    result = etharp_request(netif, ipaddr);
+  }
+  
+  /* packet given? */
+  if (q != NULL) {
+    /* stable entry? */
+    if (arp_table[i].state == ETHARP_STATE_STABLE) {
+      /* we have a valid IP->Ethernet address mapping,
+       * fill in the Ethernet header for the outgoing packet */
+      struct eth_hdr *ethhdr = q->payload;
+      for(k = 0; k < netif->hwaddr_len; k++) {
+        ethhdr->dest.addr[k] = arp_table[i].ethaddr.addr[k];
+        ethhdr->src.addr[k]  = srcaddr->addr[k];
+      }
+      ethhdr->type = htons(ETHTYPE_IP);
+      LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: sending packet %p\n", (void *)q));
+      /* send the packet */
+      result = netif->linkoutput(netif, q);
+    /* pending entry? (either just created or already pending */
+    } else if (arp_table[i].state == ETHARP_STATE_PENDING) {
+#if ARP_QUEUEING /* queue the given q packet */
+      /* copy any PBUF_REF referenced payloads into PBUF_RAM */
+      /* (the caller of lwIP assumes the referenced payload can be
+       * freed after it returns from the lwIP call that brought us here) */
+      p = pbuf_take(q);
+      /* packet could be taken over? */
+      if (p != NULL) {
+        /* queue packet ... */
+        if (arp_table[i].p == NULL) {
+        	/* ... in the empty queue */
+        	pbuf_ref(p);
+        	arp_table[i].p = p;
+#if 0 /* multi-packet-queueing disabled, see bug #11400 */
+        } else {
+        	/* ... at tail of non-empty queue */
+          pbuf_queue(arp_table[i].p, p);
+#endif
+        }
+        LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: queued packet %p on ARP entry %d\n", (void *)q, i));
+        result = ERR_OK;
+      } else {
+        LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: could not queue a copy of PBUF_REF packet %p (out of memory)\n", (void *)q));
+        /* { result == ERR_MEM } through initialization */
+      }
+#else /* ARP_QUEUEING == 0 */
+      /* q && state == PENDING && ARP_QUEUEING == 0 => result = ERR_MEM */
+      /* { result == ERR_MEM } through initialization */
+      LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: Ethernet destination address unknown, queueing disabled, packet %p dropped\n", (void *)q));
+#endif
+    }
+  }
+  return result;
+}
+
+err_t etharp_request(struct netif *netif, struct ip_addr *ipaddr)
+{
+  struct pbuf *p;
+  struct eth_addr * srcaddr = (struct eth_addr *)netif->hwaddr;
+  err_t result = ERR_OK;
+  u8_t k; /* ARP entry index */
+
+  /* allocate a pbuf for the outgoing ARP request packet */
+  p = pbuf_alloc(PBUF_LINK, sizeof(struct etharp_hdr), PBUF_RAM);
+  /* could allocate a pbuf for an ARP request? */
+  if (p != NULL) {
+    struct etharp_hdr *hdr = p->payload;
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_request: sending ARP request.\n"));
+    hdr->opcode = htons(ARP_REQUEST);
+    for (k = 0; k < netif->hwaddr_len; k++)
+    {
+      hdr->shwaddr.addr[k] = srcaddr->addr[k];
+      /* the hardware address is what we ask for, in
+       * a request it is a don't-care value, we use zeroes */
+      hdr->dhwaddr.addr[k] = 0x00;
+    }
+    hdr->dipaddr = *(struct ip_addr2 *)ipaddr;
+    hdr->sipaddr = *(struct ip_addr2 *)&netif->ip_addr;
+
+    hdr->hwtype = htons(HWTYPE_ETHERNET);
+    ARPH_HWLEN_SET(hdr, netif->hwaddr_len);
+
+    hdr->proto = htons(ETHTYPE_IP);
+    ARPH_PROTOLEN_SET(hdr, sizeof(struct ip_addr));
+    for (k = 0; k < netif->hwaddr_len; ++k)
+    {
+      /* broadcast to all network interfaces on the local network */
+      hdr->ethhdr.dest.addr[k] = 0xff;
+      hdr->ethhdr.src.addr[k] = srcaddr->addr[k];
+    }
+    hdr->ethhdr.type = htons(ETHTYPE_ARP);
+    /* send ARP query */
+    result = netif->linkoutput(netif, p);
+    /* free ARP query packet */
+    pbuf_free(p);
+    p = NULL;
+  /* could not allocate pbuf for ARP request */
+  } else {
+    result = ERR_MEM;
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 2, ("etharp_request: could not allocate pbuf for ARP request.\n"));
+  }
+  return result;
+}
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ethernetif.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ethernetif.c
new file mode 100644
index 000000000..7d4719ec9
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ethernetif.c
@@ -0,0 +1,354 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+/* lwIP includes. */
+#include 
+#include "lwip/opt.h"
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/pbuf.h"
+#include "lwip/sys.h"
+#include 
+#include "netif/etharp.h"
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "SAM7_EMAC.h"
+#include "Emac.h"
+
+#define netifMTU							( 1500 )
+#define netifINTERFACE_TASK_STACK_SIZE		( 350 )
+#define netifINTERFACE_TASK_PRIORITY		( configMAX_PRIORITIES - 1 )
+#define netifGUARD_BLOCK_TIME				( 250 )
+#define IFNAME0 'e'
+#define IFNAME1 'm'
+
+/* lwIP definitions. */
+struct ethernetif
+{
+	struct eth_addr *ethaddr;
+};
+static const struct eth_addr    ethbroadcast = { { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff } };
+static struct netif *xNetIf = NULL;
+
+/* Forward declarations. */
+static void ethernetif_input( void * );
+static err_t ethernetif_output( struct netif *netif, struct pbuf *p, struct ip_addr *ipaddr );
+err_t ethernetif_init( struct netif *netif );
+
+
+/*-----------------------------------------------------------*/
+
+static void low_level_init( struct netif *netif )
+{
+unsigned portBASE_TYPE uxPriority;
+
+	/* set MAC hardware address length */
+	netif->hwaddr_len = 6;
+
+	/* set MAC hardware address */
+	netif->hwaddr[0] = emacETHADDR0;
+	netif->hwaddr[1] = emacETHADDR1;
+	netif->hwaddr[2] = emacETHADDR2;
+	netif->hwaddr[3] = emacETHADDR3;
+	netif->hwaddr[4] = emacETHADDR4;
+	netif->hwaddr[5] = emacETHADDR5;
+
+	/* maximum transfer unit */
+	netif->mtu = netifMTU;
+
+	/* broadcast capability */
+	netif->flags = NETIF_FLAG_BROADCAST;
+
+	xNetIf = netif;
+
+	/* Initialise the EMAC.  This routine contains code that polls status bits.  
+	If the Ethernet cable is not plugged in then this can take a considerable 
+	time.  To prevent this starving lower priority tasks of processing time we
+	lower our priority prior to the call, then raise it back again once the
+	initialisation is complete. */
+	uxPriority = uxTaskPriorityGet( NULL );
+	vTaskPrioritySet( NULL, tskIDLE_PRIORITY );
+	while( xEMACInit() == NULL )
+	{
+		__asm( "NOP" );
+	}
+	vTaskPrioritySet( NULL, uxPriority );
+
+	/* Create the task that handles the EMAC. */
+	xTaskCreate( ethernetif_input, ( signed portCHAR * ) "ETH_INT", netifINTERFACE_TASK_STACK_SIZE, NULL, netifINTERFACE_TASK_PRIORITY, NULL );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * low_level_output(): Should do the actual transmission of the packet. The 
+ * packet is contained in the pbuf that is passed to the function. This pbuf 
+ * might be chained.
+ */
+static err_t low_level_output( struct netif *netif, struct pbuf *p )
+{
+struct pbuf *q;
+static xSemaphoreHandle xTxSemaphore = NULL;
+err_t xReturn = ERR_OK;
+
+	/* Parameter not used. */
+	( void ) netif;
+
+	if( xTxSemaphore == NULL )
+	{
+		vSemaphoreCreateBinary( xTxSemaphore );
+	}
+
+	#if ETH_PAD_SIZE
+		pbuf_header( p, -ETH_PAD_SIZE );    /* drop the padding word */
+	#endif
+
+	/* Access to the EMAC is guarded using a semaphore. */
+	if( xSemaphoreTake( xTxSemaphore, netifGUARD_BLOCK_TIME ) )
+	{
+		for( q = p; q != NULL; q = q->next )
+		{
+			/* Send the data from the pbuf to the interface, one pbuf at a 
+			time. The size of the data in each pbuf is kept in the ->len 
+			variable.  if q->next == NULL then this is the last pbuf in the
+			chain. */
+			if( !lEMACSend( q->payload, q->len, ( q->next == NULL ) ) )
+			{
+				xReturn = ~ERR_OK;
+			}
+		}
+
+        xSemaphoreGive( xTxSemaphore );
+	}
+	
+
+	#if ETH_PAD_SIZE
+		pbuf_header( p, ETH_PAD_SIZE );     /* reclaim the padding word */
+	#endif
+
+	#if LINK_STATS
+		lwip_stats.link.xmit++;
+	#endif /* LINK_STATS */
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * low_level_input(): Should allocate a pbuf and transfer the bytes of the 
+ * incoming packet from the interface into the pbuf. 
+ */
+static struct pbuf *low_level_input( struct netif *netif )
+{
+struct pbuf         *p = NULL, *q;
+u16_t               len = 0;
+static xSemaphoreHandle xRxSemaphore = NULL;
+
+	/* Parameter not used. */
+	( void ) netif;
+
+	if( xRxSemaphore == NULL )
+	{
+		vSemaphoreCreateBinary( xRxSemaphore );
+	}
+
+	/* Access to the emac is guarded using a semaphore. */
+   	if( xSemaphoreTake( xRxSemaphore, netifGUARD_BLOCK_TIME ) )
+	{
+		/* Obtain the size of the packet. */
+		len = ulEMACInputLength();
+	
+		if( len )
+		{
+			#if ETH_PAD_SIZE
+				len += ETH_PAD_SIZE;    /* allow room for Ethernet padding */
+			#endif
+	
+			/* We allocate a pbuf chain of pbufs from the pool. */
+			p = pbuf_alloc( PBUF_RAW, len, PBUF_POOL );
+		
+			if( p != NULL )
+			{
+				#if ETH_PAD_SIZE
+					pbuf_header( p, -ETH_PAD_SIZE );    /* drop the padding word */
+				#endif
+		
+				/* Let the driver know we are going to read a new packet. */
+				vEMACRead( NULL, 0, len );
+					
+				/* We iterate over the pbuf chain until we have read the entire
+				packet into the pbuf. */				
+				for( q = p; q != NULL; q = q->next )
+				{
+					/* Read enough bytes to fill this pbuf in the chain. The 
+					available data in the pbuf is given by the q->len variable. */
+					vEMACRead( q->payload, q->len, len );
+				}
+		
+				#if ETH_PAD_SIZE
+					pbuf_header( p, ETH_PAD_SIZE );     /* reclaim the padding word */
+				#endif
+				#if LINK_STATS
+					lwip_stats.link.recv++;
+				#endif /* LINK_STATS */
+			}
+			else
+			{
+				#if LINK_STATS
+					lwip_stats.link.memerr++;
+					lwip_stats.link.drop++;
+				#endif /* LINK_STATS */
+			}
+		}
+
+		xSemaphoreGive( xRxSemaphore );
+	}
+
+	return p;
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * ethernetif_output(): This function is called by the TCP/IP stack when an 
+ * IP packet should be sent. It calls the function called low_level_output() 
+ * to do the actual transmission of the packet.
+ */
+static err_t ethernetif_output( struct netif *netif, struct pbuf *p, struct ip_addr *ipaddr )
+{
+    /* resolve hardware address, then send (or queue) packet */
+    return etharp_output( netif, ipaddr, p );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * ethernetif_input(): This function should be called when a packet is ready to 
+ * be read from the interface. It uses the function low_level_input() that 
+ * should handle the actual reception of bytes from the network interface.
+ */
+static void ethernetif_input( void * pvParameters )
+{
+struct ethernetif   *ethernetif;
+struct eth_hdr      *ethhdr;
+struct pbuf         *p;
+
+	( void ) pvParameters;
+
+	for( ;; )
+	{
+		do
+		{
+			ethernetif = xNetIf->state;
+
+			/* move received packet into a new pbuf */
+			p = low_level_input( xNetIf );
+
+			if( p == NULL )
+			{
+				/* No packet could be read.  Wait a for an interrupt to tell us 
+				there is more data available. */
+				vEMACWaitForInput();
+			}
+
+		} while( p == NULL );
+	
+		/* points to packet payload, which starts with an Ethernet header */
+		ethhdr = p->payload;
+	
+		#if LINK_STATS
+			lwip_stats.link.recv++;
+		#endif /* LINK_STATS */
+	
+		ethhdr = p->payload;
+	
+		switch( htons( ethhdr->type ) )
+		{
+			/* IP packet? */
+			case ETHTYPE_IP:
+				/* update ARP table */
+				etharp_ip_input( xNetIf, p );
+		
+				/* skip Ethernet header */
+				pbuf_header( p, (s16_t)-sizeof(struct eth_hdr) );
+		
+				/* pass to network layer */
+				xNetIf->input( p, xNetIf );
+				break;
+		
+			case ETHTYPE_ARP:
+				/* pass p to ARP module */
+				etharp_arp_input( xNetIf, ethernetif->ethaddr, p );
+				break;
+		
+			default:
+				pbuf_free( p );
+				p = NULL;
+				break;
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void arp_timer( void *arg )
+{
+	( void ) arg;
+
+    etharp_tmr();
+    sys_timeout( ARP_TMR_INTERVAL, arp_timer, NULL );
+}
+/*-----------------------------------------------------------*/
+
+err_t ethernetif_init( struct netif *netif )
+{
+struct ethernetif   *ethernetif;
+
+	ethernetif = mem_malloc( sizeof(struct ethernetif) );
+
+	if( ethernetif == NULL )
+	{
+		LWIP_DEBUGF( NETIF_DEBUG, ("ethernetif_init: out of memory\n") );
+		return ERR_MEM;
+	}
+
+	netif->state = ethernetif;
+	netif->name[0] = IFNAME0;
+	netif->name[1] = IFNAME1;
+	netif->output = ethernetif_output;
+	netif->linkoutput = low_level_output;
+
+	ethernetif->ethaddr = ( struct eth_addr * ) &( netif->hwaddr[0] );
+
+	low_level_init( netif );
+	etharp_init();
+	sys_timeout( ARP_TMR_INTERVAL, arp_timer, NULL );
+
+	return ERR_OK;
+}
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/loopif.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/loopif.c
new file mode 100644
index 000000000..9440a6c11
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/loopif.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#include "lwip/opt.h"
+
+#if LWIP_HAVE_LOOPIF
+
+#include "netif/loopif.h"
+#include "lwip/mem.h"
+
+#if defined(LWIP_DEBUG) && defined(LWIP_TCPDUMP)
+#include "netif/tcpdump.h"
+#endif /* LWIP_DEBUG && LWIP_TCPDUMP */
+
+#include "lwip/tcp.h"
+#include "lwip/ip.h"
+
+static void
+loopif_input( void * arg )
+{
+	struct netif *netif = (struct netif *)( ((void **)arg)[ 0 ] );
+	struct pbuf *r = (struct pbuf *)( ((void **)arg)[ 1 ] );
+
+	mem_free( arg );
+	netif -> input( r, netif );
+}
+
+static err_t
+loopif_output(struct netif *netif, struct pbuf *p,
+       struct ip_addr *ipaddr)
+{
+  struct pbuf *q, *r;
+  char *ptr;
+  void **arg;
+
+#if defined(LWIP_DEBUG) && defined(LWIP_TCPDUMP)
+  tcpdump(p);
+#endif /* LWIP_DEBUG && LWIP_TCPDUMP */
+  
+  r = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM);
+  if (r != NULL) {
+    ptr = r->payload;
+    
+    for(q = p; q != NULL; q = q->next) {
+      memcpy(ptr, q->payload, q->len);
+      ptr += q->len;
+    }
+
+    arg = mem_malloc( sizeof( void *[2]));
+	if( NULL == arg ) {
+		return ERR_MEM;
+	}
+	
+	arg[0] = netif;
+	arg[1] = r;
+	/**
+	 * workaround (patch #1779) to try to prevent bug #2595:
+	 * When connecting to "localhost" with the loopif interface,
+	 * tcp_output doesn't get the opportunity to finnish sending the
+	 * segment before tcp_process gets it, resulting in tcp_process
+	 * referencing pcb->unacked-> which still is NULL.
+	 * 
+	 * TODO: Is there still a race condition here? Leon
+	 */
+	sys_timeout( 1, loopif_input, arg );
+	
+    return ERR_OK;    
+  }
+  return ERR_MEM;
+}
+
+err_t
+loopif_init(struct netif *netif)
+{
+  netif->name[0] = 'l';
+  netif->name[1] = 'o';
+#if 0 /** TODO: I think this should be enabled, or not? Leon */
+  netif->input = loopif_input;
+#endif
+  netif->output = loopif_output;
+  return ERR_OK;
+}
+
+#endif /* LWIP_HAVE_LOOPIF */
+
+
+
+
+
+
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/auth.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/auth.c
new file mode 100644
index 000000000..0786a2e81
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/auth.c
@@ -0,0 +1,927 @@
+/*****************************************************************************
+* auth.c - Network Authentication and Phase Control program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* Copyright (c) 1997 by Global Election Systems Inc.  All rights reserved.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-08 Guy Lancaster , Global Election Systems Inc.
+*   Ported from public pppd code.
+*****************************************************************************/
+/*
+ * auth.c - PPP authentication and phase control.
+ *
+ * Copyright (c) 1993 The Australian National University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the Australian National University.  The name of the University
+ * may not be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include "ppp.h"
+#if PPP_SUPPORT > 0
+#include "fsm.h"
+#include "lcp.h"
+#include "pap.h"
+#include "chap.h"
+#include "auth.h"
+#include "ipcp.h"
+
+#if CBCP_SUPPORT > 0
+#include "cbcp.h"
+#endif
+
+#include "pppdebug.h"
+
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+
+/* Bits in auth_pending[] */
+#define PAP_WITHPEER    1
+#define PAP_PEER    2
+#define CHAP_WITHPEER   4
+#define CHAP_PEER   8
+
+
+                                                                    
+/************************/
+/*** LOCAL DATA TYPES ***/
+/************************/
+/* Used for storing a sequence of words.  Usually malloced. */
+struct wordlist {
+    struct wordlist *next;
+    char        word[1];
+};
+
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+extern char *crypt (const char *, const char *);
+
+/* Prototypes for procedures local to this file. */
+
+static void network_phase (int);
+static void check_idle (void *);
+static void connect_time_expired (void *);
+#if 0
+static int  login (char *, char *, char **, int *);
+#endif
+static void logout (void);
+static int  null_login (int);
+static int  get_pap_passwd (int, char *, char *);
+static int  have_pap_secret (void);
+static int  have_chap_secret (char *, char *, u32_t);
+static int  ip_addr_check (u32_t, struct wordlist *);
+#if 0 /* PAP_SUPPORT > 0 || CHAP_SUPPORT > 0 */
+static void set_allowed_addrs(int unit, struct wordlist *addrs);
+static void free_wordlist (struct wordlist *);
+#endif
+#if CBCP_SUPPORT > 0
+static void callback_phase (int);
+#endif
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+#if PAP_SUPPORT > 0 || CHAP_SUPPORT > 0
+/* The name by which the peer authenticated itself to us. */
+static char peer_authname[MAXNAMELEN];
+#endif
+
+/* Records which authentication operations haven't completed yet. */
+static int auth_pending[NUM_PPP];
+
+/* Set if we have successfully called login() */
+static int logged_in;
+
+/* Set if we have run the /etc/ppp/auth-up script. */
+static int did_authup;
+
+/* List of addresses which the peer may use. */
+static struct wordlist *addresses[NUM_PPP];
+
+/* Number of network protocols which we have opened. */
+static int num_np_open;
+
+/* Number of network protocols which have come up. */
+static int num_np_up;
+
+#if PAP_SUPPORT > 0 || CHAP_SUPPORT > 0
+/* Set if we got the contents of passwd[] from the pap-secrets file. */
+static int passwd_from_file;
+#endif
+
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ * An Open on LCP has requested a change from Dead to Establish phase.
+ * Do what's necessary to bring the physical layer up.
+ */
+void link_required(int unit)
+{
+    AUTHDEBUG((LOG_INFO, "link_required: %d\n", unit));
+}
+
+/*
+ * LCP has terminated the link; go to the Dead phase and take the
+ * physical layer down.
+ */
+void link_terminated(int unit)
+{
+    AUTHDEBUG((LOG_INFO, "link_terminated: %d\n", unit));
+    
+    if (lcp_phase[unit] == PHASE_DEAD)
+        return;
+    if (logged_in)
+        logout();
+    lcp_phase[unit] = PHASE_DEAD;
+    AUTHDEBUG((LOG_NOTICE, "Connection terminated.\n"));
+	pppMainWakeup(unit);
+}
+
+/*
+ * LCP has gone down; it will either die or try to re-establish.
+ */
+void link_down(int unit)
+{
+    int i;
+    struct protent *protp;
+    
+    AUTHDEBUG((LOG_INFO, "link_down: %d\n", unit));
+    if (did_authup) {
+        /* XXX Do link down processing. */
+        did_authup = 0;
+    }
+    for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) {
+        if (!protp->enabled_flag)
+            continue;
+        if (protp->protocol != PPP_LCP && protp->lowerdown != NULL)
+            (*protp->lowerdown)(unit);
+        if (protp->protocol < 0xC000 && protp->close != NULL)
+            (*protp->close)(unit, "LCP down");
+    }
+    num_np_open = 0;
+    num_np_up = 0;
+    if (lcp_phase[unit] != PHASE_DEAD)
+        lcp_phase[unit] = PHASE_TERMINATE;
+	pppMainWakeup(unit);
+}
+
+/*
+ * The link is established.
+ * Proceed to the Dead, Authenticate or Network phase as appropriate.
+ */
+void link_established(int unit)
+{
+    int auth;
+    int i;
+    struct protent *protp;
+    lcp_options *wo = &lcp_wantoptions[unit];
+    lcp_options *go = &lcp_gotoptions[unit];
+#if PAP_SUPPORT > 0 || CHAP_SUPPORT > 0
+    lcp_options *ho = &lcp_hisoptions[unit];
+#endif
+    
+    AUTHDEBUG((LOG_INFO, "link_established: %d\n", unit));
+    /*
+     * Tell higher-level protocols that LCP is up.
+     */
+    for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i)
+        if (protp->protocol != PPP_LCP && protp->enabled_flag
+                && protp->lowerup != NULL)
+            (*protp->lowerup)(unit);
+    
+    if (ppp_settings.auth_required && !(go->neg_chap || go->neg_upap)) {
+        /*
+         * We wanted the peer to authenticate itself, and it refused:
+         * treat it as though it authenticated with PAP using a username
+         * of "" and a password of "".  If that's not OK, boot it out.
+         */
+        if (!wo->neg_upap || !null_login(unit)) {
+            AUTHDEBUG((LOG_WARNING, "peer refused to authenticate\n"));
+            lcp_close(unit, "peer refused to authenticate");
+            return;
+        }
+    }
+    
+    lcp_phase[unit] = PHASE_AUTHENTICATE;
+    auth = 0;
+#if CHAP_SUPPORT > 0
+    if (go->neg_chap) {
+        ChapAuthPeer(unit, ppp_settings.our_name, go->chap_mdtype);
+        auth |= CHAP_PEER;
+    } 
+#endif
+#if PAP_SUPPORT > 0 && CHAP_SUPPORT > 0
+    else
+#endif
+#if PAP_SUPPORT > 0
+    if (go->neg_upap) {
+        upap_authpeer(unit);
+        auth |= PAP_PEER;
+    }
+#endif
+#if CHAP_SUPPORT > 0
+    if (ho->neg_chap) {
+        ChapAuthWithPeer(unit, ppp_settings.user, ho->chap_mdtype);
+        auth |= CHAP_WITHPEER;
+    }
+#endif
+#if PAP_SUPPORT > 0 && CHAP_SUPPORT > 0
+    else
+#endif
+#if PAP_SUPPORT > 0
+    if (ho->neg_upap) {
+        if (ppp_settings.passwd[0] == 0) {
+            passwd_from_file = 1;
+            if (!get_pap_passwd(unit, ppp_settings.user, ppp_settings.passwd))
+                AUTHDEBUG((LOG_ERR, "No secret found for PAP login\n"));
+        }
+        upap_authwithpeer(unit, ppp_settings.user, ppp_settings.passwd);
+        auth |= PAP_WITHPEER;
+    }
+#endif
+    auth_pending[unit] = auth;
+    
+    if (!auth)
+        network_phase(unit);
+}
+
+
+/*
+ * The peer has failed to authenticate himself using `protocol'.
+ */
+void auth_peer_fail(int unit, u16_t protocol)
+{
+    AUTHDEBUG((LOG_INFO, "auth_peer_fail: %d proto=%X\n", unit, protocol));
+    /*
+     * Authentication failure: take the link down
+     */
+    lcp_close(unit, "Authentication failed");
+}
+
+
+#if PAP_SUPPORT > 0 || CHAP_SUPPORT > 0
+/*
+ * The peer has been successfully authenticated using `protocol'.
+ */
+void auth_peer_success(int unit, u16_t protocol, char *name, int namelen)
+{
+    int pbit;
+    
+    AUTHDEBUG((LOG_INFO, "auth_peer_success: %d proto=%X\n", unit, protocol));
+    switch (protocol) {
+    case PPP_CHAP:
+        pbit = CHAP_PEER;
+        break;
+    case PPP_PAP:
+        pbit = PAP_PEER;
+        break;
+    default:
+        AUTHDEBUG((LOG_WARNING, "auth_peer_success: unknown protocol %x\n",
+               protocol));
+        return;
+    }
+    
+    /*
+     * Save the authenticated name of the peer for later.
+     */
+    if (namelen > sizeof(peer_authname) - 1)
+        namelen = sizeof(peer_authname) - 1;
+    BCOPY(name, peer_authname, namelen);
+    peer_authname[namelen] = 0;
+    
+    /*
+     * If there is no more authentication still to be done,
+     * proceed to the network (or callback) phase.
+     */
+    if ((auth_pending[unit] &= ~pbit) == 0)
+        network_phase(unit);
+}
+
+/*
+ * We have failed to authenticate ourselves to the peer using `protocol'.
+ */
+void auth_withpeer_fail(int unit, u16_t protocol)
+{
+    int errCode = PPPERR_AUTHFAIL;
+    
+    AUTHDEBUG((LOG_INFO, "auth_withpeer_fail: %d proto=%X\n", unit, protocol));
+    if (passwd_from_file)
+        BZERO(ppp_settings.passwd, MAXSECRETLEN);
+    /* 
+     * XXX Warning: the unit number indicates the interface which is
+     * not necessarily the PPP connection.  It works here as long
+     * as we are only supporting PPP interfaces.
+     */
+    pppIOCtl(unit, PPPCTLS_ERRCODE, &errCode);
+
+    /*
+     * We've failed to authenticate ourselves to our peer.
+     * He'll probably take the link down, and there's not much
+     * we can do except wait for that.
+     */
+}
+
+/*
+ * We have successfully authenticated ourselves with the peer using `protocol'.
+ */
+void auth_withpeer_success(int unit, u16_t protocol)
+{
+    int pbit;
+    
+    AUTHDEBUG((LOG_INFO, "auth_withpeer_success: %d proto=%X\n", unit, protocol));
+    switch (protocol) {
+    case PPP_CHAP:
+        pbit = CHAP_WITHPEER;
+        break;
+    case PPP_PAP:
+        if (passwd_from_file)
+            BZERO(ppp_settings.passwd, MAXSECRETLEN);
+        pbit = PAP_WITHPEER;
+        break;
+    default:
+        AUTHDEBUG((LOG_WARNING, "auth_peer_success: unknown protocol %x\n",
+               protocol));
+        pbit = 0;
+    }
+    
+    /*
+     * If there is no more authentication still being done,
+     * proceed to the network (or callback) phase.
+     */
+    if ((auth_pending[unit] &= ~pbit) == 0)
+        network_phase(unit);
+}
+#endif
+
+
+/*
+ * np_up - a network protocol has come up.
+ */
+void np_up(int unit, u16_t proto)
+{
+    AUTHDEBUG((LOG_INFO, "np_up: %d proto=%X\n", unit, proto));
+    if (num_np_up == 0) {
+	AUTHDEBUG((LOG_INFO, "np_up: maxconnect=%d idle_time_limit=%d\n",ppp_settings.maxconnect,ppp_settings.idle_time_limit));
+        /*
+         * At this point we consider that the link has come up successfully.
+         */
+        if (ppp_settings.idle_time_limit > 0)
+            TIMEOUT(check_idle, NULL, ppp_settings.idle_time_limit);
+        
+        /*
+         * Set a timeout to close the connection once the maximum
+         * connect time has expired.
+         */
+        if (ppp_settings.maxconnect > 0)
+            TIMEOUT(connect_time_expired, 0, ppp_settings.maxconnect);
+    }
+    ++num_np_up;
+}
+
+/*
+ * np_down - a network protocol has gone down.
+ */
+void np_down(int unit, u16_t proto)
+{
+    AUTHDEBUG((LOG_INFO, "np_down: %d proto=%X\n", unit, proto));
+    if (--num_np_up == 0 && ppp_settings.idle_time_limit > 0) {
+        UNTIMEOUT(check_idle, NULL);
+    }
+}
+
+/*
+ * np_finished - a network protocol has finished using the link.
+ */
+void np_finished(int unit, u16_t proto)
+{
+    AUTHDEBUG((LOG_INFO, "np_finished: %d proto=%X\n", unit, proto));
+    if (--num_np_open <= 0) {
+        /* no further use for the link: shut up shop. */
+        lcp_close(0, "No network protocols running");
+    }
+}
+
+/*
+ * auth_reset - called when LCP is starting negotiations to recheck
+ * authentication options, i.e. whether we have appropriate secrets
+ * to use for authenticating ourselves and/or the peer.
+ */
+void auth_reset(int unit)
+{
+    lcp_options *go = &lcp_gotoptions[unit];
+    lcp_options *ao = &lcp_allowoptions[0];
+    ipcp_options *ipwo = &ipcp_wantoptions[0];
+    u32_t remote;
+    
+    AUTHDEBUG((LOG_INFO, "auth_reset: %d\n", unit));
+    ao->neg_upap = !ppp_settings.refuse_pap && (ppp_settings.passwd[0] != 0 || get_pap_passwd(unit, NULL, NULL));
+    ao->neg_chap = !ppp_settings.refuse_chap && ppp_settings.passwd[0] != 0 /*have_chap_secret(ppp_settings.user, ppp_settings.remote_name, (u32_t)0)*/;
+    
+    if (go->neg_upap && !have_pap_secret())
+        go->neg_upap = 0;
+    if (go->neg_chap) {
+        remote = ipwo->accept_remote? 0: ipwo->hisaddr;
+        if (!have_chap_secret(ppp_settings.remote_name, ppp_settings.our_name, remote))
+            go->neg_chap = 0;
+    }
+}
+
+
+#if PAP_SUPPORT > 0
+/*
+ * check_passwd - Check the user name and passwd against the PAP secrets
+ * file.  If requested, also check against the system password database,
+ * and login the user if OK.
+ *
+ * returns:
+ *  UPAP_AUTHNAK: Authentication failed.
+ *  UPAP_AUTHACK: Authentication succeeded.
+ * In either case, msg points to an appropriate message.
+ */
+int check_passwd(
+	int unit,
+	char *auser,
+	int userlen,
+	char *apasswd,
+	int passwdlen,
+	char **msg,
+	int *msglen
+)
+{
+#if 1
+	*msg = (char *) 0;
+	return UPAP_AUTHACK;     /* XXX Assume all entries OK. */
+#else
+    int ret = 0;
+    struct wordlist *addrs = NULL;
+    char passwd[256], user[256];
+    char secret[MAXWORDLEN];
+    static u_short attempts = 0;
+    
+    /*
+     * Make copies of apasswd and auser, then null-terminate them.
+     */
+    BCOPY(apasswd, passwd, passwdlen);
+    passwd[passwdlen] = '\0';
+    BCOPY(auser, user, userlen);
+    user[userlen] = '\0';
+    *msg = (char *) 0;
+
+    /* XXX Validate user name and password. */
+    ret = UPAP_AUTHACK;     /* XXX Assume all entries OK. */
+        
+    if (ret == UPAP_AUTHNAK) {
+        if (*msg == (char *) 0)
+            *msg = "Login incorrect";
+        *msglen = strlen(*msg);
+        /*
+         * Frustrate passwd stealer programs.
+         * Allow 10 tries, but start backing off after 3 (stolen from login).
+         * On 10'th, drop the connection.
+         */
+        if (attempts++ >= 10) {
+            AUTHDEBUG((LOG_WARNING, "%d LOGIN FAILURES BY %s\n", attempts, user));
+            /*ppp_panic("Excess Bad Logins");*/
+        }
+        if (attempts > 3) {
+            sys_msleep((attempts - 3) * 5);
+        }
+        if (addrs != NULL) {
+            free_wordlist(addrs);
+        }
+    } else {
+        attempts = 0;           /* Reset count */
+        if (*msg == (char *) 0)
+            *msg = "Login ok";
+        *msglen = strlen(*msg);
+        set_allowed_addrs(unit, addrs);
+    }
+    
+    BZERO(passwd, sizeof(passwd));
+    BZERO(secret, sizeof(secret));
+    
+    return ret;
+#endif
+}
+#endif
+
+
+/*
+ * auth_ip_addr - check whether the peer is authorized to use
+ * a given IP address.  Returns 1 if authorized, 0 otherwise.
+ */
+int auth_ip_addr(int unit, u32_t addr)
+{
+    return ip_addr_check(addr, addresses[unit]);
+}
+
+/*
+ * bad_ip_adrs - return 1 if the IP address is one we don't want
+ * to use, such as an address in the loopback net or a multicast address.
+ * addr is in network byte order.
+ */
+int bad_ip_adrs(u32_t addr)
+{
+    addr = ntohl(addr);
+    return (addr >> IN_CLASSA_NSHIFT) == IN_LOOPBACKNET
+        || IN_MULTICAST(addr) || IN_BADCLASS(addr);
+}
+
+
+#if CHAP_SUPPORT > 0
+/*
+ * get_secret - open the CHAP secret file and return the secret
+ * for authenticating the given client on the given server.
+ * (We could be either client or server).
+ */
+int get_secret(
+    int unit,
+    char *client,
+    char *server,
+    char *secret,
+    int *secret_len,
+    int save_addrs
+)
+{
+#if 1
+    int len;
+    struct wordlist *addrs;
+    
+    addrs = NULL;
+
+    if(!client || !client[0] || strcmp(client, ppp_settings.user)) {
+	return 0;
+    }
+
+    len = strlen(ppp_settings.passwd);
+    if (len > MAXSECRETLEN) {
+        AUTHDEBUG((LOG_ERR, "Secret for %s on %s is too long\n", client, server));
+        len = MAXSECRETLEN;
+    }
+    BCOPY(ppp_settings.passwd, secret, len);
+    *secret_len = len;
+    
+    return 1;
+#else
+    int ret = 0, len;
+    struct wordlist *addrs;
+    char secbuf[MAXWORDLEN];
+    
+    addrs = NULL;
+    secbuf[0] = 0;
+
+    /* XXX Find secret. */  
+    if (ret < 0)
+        return 0;
+    
+    if (save_addrs)
+        set_allowed_addrs(unit, addrs);
+    
+    len = strlen(secbuf);
+    if (len > MAXSECRETLEN) {
+        AUTHDEBUG((LOG_ERR, "Secret for %s on %s is too long\n", client, server));
+        len = MAXSECRETLEN;
+    }
+    BCOPY(secbuf, secret, len);
+    BZERO(secbuf, sizeof(secbuf));
+    *secret_len = len;
+    
+    return 1;
+#endif
+}
+#endif
+
+
+#if 0 /* UNUSED */
+/*
+ * auth_check_options - called to check authentication options.
+ */
+void auth_check_options(void)
+{
+    lcp_options *wo = &lcp_wantoptions[0];
+    int can_auth;
+    ipcp_options *ipwo = &ipcp_wantoptions[0];
+    u32_t remote;
+    
+    /* Default our_name to hostname, and user to our_name */
+    if (ppp_settings.our_name[0] == 0 || ppp_settings.usehostname)
+        strcpy(ppp_settings.our_name, ppp_settings.hostname);
+    if (ppp_settings.user[0] == 0)
+        strcpy(ppp_settings.user, ppp_settings.our_name);
+    
+    /* If authentication is required, ask peer for CHAP or PAP. */
+    if (ppp_settings.auth_required && !wo->neg_chap && !wo->neg_upap) {
+        wo->neg_chap = 1;
+        wo->neg_upap = 1;
+    }
+    
+    /*
+     * Check whether we have appropriate secrets to use
+     * to authenticate the peer.
+     */
+    can_auth = wo->neg_upap && have_pap_secret();
+    if (!can_auth && wo->neg_chap) {
+        remote = ipwo->accept_remote? 0: ipwo->hisaddr;
+        can_auth = have_chap_secret(ppp_settings.remote_name, ppp_settings.our_name, remote);
+    }
+    
+    if (ppp_settings.auth_required && !can_auth) {
+        ppp_panic("No auth secret");
+    }
+}
+#endif
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+/*
+ * Proceed to the network phase.
+ */
+static void network_phase(int unit)
+{
+    int i;
+    struct protent *protp;
+    lcp_options *go = &lcp_gotoptions[unit];
+    
+    /*
+     * If the peer had to authenticate, run the auth-up script now.
+     */
+    if ((go->neg_chap || go->neg_upap) && !did_authup) {
+        /* XXX Do setup for peer authentication. */
+        did_authup = 1;
+    }
+    
+#if CBCP_SUPPORT > 0
+    /*
+     * If we negotiated callback, do it now.
+     */
+    if (go->neg_cbcp) {
+        lcp_phase[unit] = PHASE_CALLBACK;
+        (*cbcp_protent.open)(unit);
+        return;
+    }
+#endif
+    
+    lcp_phase[unit] = PHASE_NETWORK;
+    for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i)
+        if (protp->protocol < 0xC000 && protp->enabled_flag
+                && protp->open != NULL) {
+            (*protp->open)(unit);
+            if (protp->protocol != PPP_CCP)
+                ++num_np_open;
+        }
+    
+    if (num_np_open == 0)
+        /* nothing to do */
+        lcp_close(0, "No network protocols running");
+}
+
+/*
+ * check_idle - check whether the link has been idle for long
+ * enough that we can shut it down.
+ */
+static void check_idle(void *arg)
+{
+    struct ppp_idle idle;
+    u_short itime;
+    
+	(void)arg;
+    if (!get_idle_time(0, &idle))
+        return;
+    itime = LWIP_MIN(idle.xmit_idle, idle.recv_idle);
+    if (itime >= ppp_settings.idle_time_limit) {
+        /* link is idle: shut it down. */
+        AUTHDEBUG((LOG_INFO, "Terminating connection due to lack of activity.\n"));
+        lcp_close(0, "Link inactive");
+    } else {
+        TIMEOUT(check_idle, NULL, ppp_settings.idle_time_limit - itime);
+    }
+}
+
+/*
+ * connect_time_expired - log a message and close the connection.
+ */
+static void connect_time_expired(void *arg)
+{
+	(void)arg;
+
+    AUTHDEBUG((LOG_INFO, "Connect time expired\n"));
+    lcp_close(0, "Connect time expired");   /* Close connection */
+}
+
+#if 0
+/*
+ * login - Check the user name and password against the system
+ * password database, and login the user if OK.
+ *
+ * returns:
+ *  UPAP_AUTHNAK: Login failed.
+ *  UPAP_AUTHACK: Login succeeded.
+ * In either case, msg points to an appropriate message.
+ */
+static int login(char *user, char *passwd, char **msg, int *msglen)
+{
+    /* XXX Fail until we decide that we want to support logins. */
+    return (UPAP_AUTHNAK);
+}
+#endif
+
+/*
+ * logout - Logout the user.
+ */
+static void logout(void)
+{
+    logged_in = 0;
+}
+
+
+/*
+ * null_login - Check if a username of "" and a password of "" are
+ * acceptable, and iff so, set the list of acceptable IP addresses
+ * and return 1.
+ */
+static int null_login(int unit)
+{
+	(void)unit;
+    /* XXX Fail until we decide that we want to support logins. */
+    return 0;
+}
+
+
+/*
+ * get_pap_passwd - get a password for authenticating ourselves with
+ * our peer using PAP.  Returns 1 on success, 0 if no suitable password
+ * could be found.
+ */
+static int get_pap_passwd(int unit, char *user, char *passwd)
+{
+/* normally we would reject PAP if no password is provided,
+   but this causes problems with some providers (like CHT in Taiwan)
+   who incorrectly request PAP and expect a bogus/empty password, so
+   always provide a default user/passwd of "none"/"none"
+*/
+    if(user)
+    	strcpy(user,   "none");
+    if(passwd)
+    	strcpy(passwd, "none");
+
+    return 1;
+}
+
+
+/*
+ * have_pap_secret - check whether we have a PAP file with any
+ * secrets that we could possibly use for authenticating the peer.
+ */
+static int have_pap_secret(void)
+{
+    /* XXX Fail until we set up our passwords. */
+    return 0;
+}
+
+
+/*
+ * have_chap_secret - check whether we have a CHAP file with a
+ * secret that we could possibly use for authenticating `client'
+ * on `server'.  Either can be the null string, meaning we don't
+ * know the identity yet.
+ */
+static int have_chap_secret(char *client, char *server, u32_t remote)
+{
+	(void)client;
+	(void)server;
+	(void)remote;
+    /* XXX Fail until we set up our passwords. */
+    return 0;
+}
+
+
+#if 0 /* PAP_SUPPORT > 0 || CHAP_SUPPORT > 0 */
+/*
+ * set_allowed_addrs() - set the list of allowed addresses.
+ */
+static void set_allowed_addrs(int unit, struct wordlist *addrs)
+{
+    if (addresses[unit] != NULL)
+        free_wordlist(addresses[unit]);
+    addresses[unit] = addrs;
+
+#if 0
+    /*
+     * If there's only one authorized address we might as well
+     * ask our peer for that one right away
+     */
+    if (addrs != NULL && addrs->next == NULL) {
+        char *p = addrs->word;
+        struct ipcp_options *wo = &ipcp_wantoptions[unit];
+        u32_t a;
+        struct hostent *hp;
+        
+        if (wo->hisaddr == 0 && *p != '!' && *p != '-'
+                && strchr(p, '/') == NULL) {
+            hp = gethostbyname(p);
+            if (hp != NULL && hp->h_addrtype == AF_INET)
+                a = *(u32_t *)hp->h_addr;
+            else
+                a = inet_addr(p);
+            if (a != (u32_t) -1)
+                wo->hisaddr = a;
+        }
+    }
+#endif
+}
+#endif
+
+static int ip_addr_check(u32_t addr, struct wordlist *addrs)
+{
+    
+    /* don't allow loopback or multicast address */
+    if (bad_ip_adrs(addr))
+        return 0;
+    
+    if (addrs == NULL)
+        return !ppp_settings.auth_required;      /* no addresses authorized */
+    
+    /* XXX All other addresses allowed. */
+    return 1;
+}
+
+#if 0 /* PAP_SUPPORT > 0 || CHAP_SUPPORT */
+/*
+ * free_wordlist - release memory allocated for a wordlist.
+ */
+static void free_wordlist(struct wordlist *wp)
+{
+    struct wordlist *next;
+    
+    while (wp != NULL) {
+        next = wp->next;
+        free(wp);
+        wp = next;
+    }
+}
+#endif
+
+#endif /* PPP_SUPPORT */
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/auth.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/auth.h
new file mode 100644
index 000000000..58174056c
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/auth.h
@@ -0,0 +1,94 @@
+/*****************************************************************************
+* auth.h -  PPP Authentication and phase control header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1998 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-04 Guy Lancaster , Global Election Systems Inc.
+*	Original derived from BSD pppd.h.
+*****************************************************************************/
+/*
+ * pppd.h - PPP daemon global declarations.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ */
+
+#ifndef AUTH_H
+#define AUTH_H
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+void link_required (int);		/* we are starting to use the link */
+void link_terminated (int);	/* we are finished with the link */
+void link_down (int);			/* the LCP layer has left the Opened state */
+void link_established (int);	/* the link is up; authenticate now */
+void np_up (int, u16_t);			/* a network protocol has come up */
+void np_down (int, u16_t);		/* a network protocol has gone down */
+void np_finished (int, u16_t);	/* a network protocol no longer needs link */
+void auth_peer_fail (int, u16_t);/* peer failed to authenticate itself */
+
+/* peer successfully authenticated itself */
+void auth_peer_success (int, u16_t, char *, int);
+
+/* we failed to authenticate ourselves */
+void auth_withpeer_fail (int, u16_t);
+
+/* we successfully authenticated ourselves */
+void auth_withpeer_success (int, u16_t);
+
+/* check authentication options supplied */
+void auth_check_options (void);
+void auth_reset (int);			/* check what secrets we have */
+
+/* Check peer-supplied username/password */
+int  check_passwd (int, char *, int, char *, int, char **, int *);
+
+/* get "secret" for chap */
+int  get_secret (int, char *, char *, char *, int *, int);
+
+/* check if IP address is authorized */
+int  auth_ip_addr (int, u32_t);
+
+/* check if IP address is unreasonable */
+int  bad_ip_adrs (u32_t);
+
+
+#endif /* AUTH_H */
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/chap.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/chap.c
new file mode 100644
index 000000000..30441bdc8
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/chap.c
@@ -0,0 +1,872 @@
+/*** WARNING - THIS HAS NEVER BEEN FINISHED ***/
+/*****************************************************************************
+* chap.c - Network Challenge Handshake Authentication Protocol program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-04 Guy Lancaster , Global Election Systems Inc.
+*	Original based on BSD chap.c.
+*****************************************************************************/
+/*
+ * chap.c - Challenge Handshake Authentication Protocol.
+ *
+ * Copyright (c) 1993 The Australian National University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the Australian National University.  The name of the University
+ * may not be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Copyright (c) 1991 Gregory M. Christy.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Gregory M. Christy.  The name of the author may not be used to
+ * endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include "ppp.h"
+#if PPP_SUPPORT > 0
+#include "magic.h"
+
+#if CHAP_SUPPORT > 0
+
+#include "randm.h"
+#include "auth.h"
+#include "md5.h"
+#include "chap.h"
+#include "chpms.h"
+#include "pppdebug.h"
+
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+
+
+/************************/
+/*** LOCAL DATA TYPES ***/
+/************************/
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+/*
+ * Protocol entry points.
+ */
+static void ChapInit (int);
+static void ChapLowerUp (int);
+static void ChapLowerDown (int);
+static void ChapInput (int, u_char *, int);
+static void ChapProtocolReject (int);
+static int  ChapPrintPkt (u_char *, int,
+			      void (*) (void *, char *, ...), void *);
+
+static void ChapChallengeTimeout (void *);
+static void ChapResponseTimeout (void *);
+static void ChapReceiveChallenge (chap_state *, u_char *, int, int);
+static void ChapRechallenge (void *);
+static void ChapReceiveResponse (chap_state *, u_char *, int, int);
+static void ChapReceiveSuccess(chap_state *cstate, u_char *inp, u_char id, int len);
+static void ChapReceiveFailure(chap_state *cstate, u_char *inp, u_char id, int len);
+static void ChapSendStatus (chap_state *, int);
+static void ChapSendChallenge (chap_state *);
+static void ChapSendResponse (chap_state *);
+static void ChapGenChallenge (chap_state *);
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+chap_state chap[NUM_PPP];		/* CHAP state; one for each unit */
+
+struct protent chap_protent = {
+    PPP_CHAP,
+    ChapInit,
+    ChapInput,
+    ChapProtocolReject,
+    ChapLowerUp,
+    ChapLowerDown,
+    NULL,
+    NULL,
+#if 0
+    ChapPrintPkt,
+    NULL,
+#endif
+    1,
+    "CHAP",
+#if 0
+    NULL,
+    NULL,
+    NULL
+#endif
+};
+
+
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+static char *ChapCodenames[] = {
+	"Challenge", "Response", "Success", "Failure"
+};
+
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ * ChapAuthWithPeer - Authenticate us with our peer (start client).
+ *
+ */
+void ChapAuthWithPeer(int unit, char *our_name, int digest)
+{
+	chap_state *cstate = &chap[unit];
+	
+	cstate->resp_name = our_name;
+	cstate->resp_type = digest;
+	
+	if (cstate->clientstate == CHAPCS_INITIAL ||
+			cstate->clientstate == CHAPCS_PENDING) {
+		/* lower layer isn't up - wait until later */
+		cstate->clientstate = CHAPCS_PENDING;
+		return;
+	}
+	
+	/*
+	 * We get here as a result of LCP coming up.
+	 * So even if CHAP was open before, we will 
+	 * have to re-authenticate ourselves.
+	 */
+	cstate->clientstate = CHAPCS_LISTEN;
+}
+
+
+/*
+ * ChapAuthPeer - Authenticate our peer (start server).
+ */
+void ChapAuthPeer(int unit, char *our_name, int digest)
+{
+	chap_state *cstate = &chap[unit];
+	
+	cstate->chal_name = our_name;
+	cstate->chal_type = digest;
+	
+	if (cstate->serverstate == CHAPSS_INITIAL ||
+			cstate->serverstate == CHAPSS_PENDING) {
+		/* lower layer isn't up - wait until later */
+		cstate->serverstate = CHAPSS_PENDING;
+		return;
+	}
+	
+	ChapGenChallenge(cstate);
+	ChapSendChallenge(cstate);		/* crank it up dude! */
+	cstate->serverstate = CHAPSS_INITIAL_CHAL;
+}
+
+
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+/*
+ * ChapInit - Initialize a CHAP unit.
+ */
+static void ChapInit(int unit)
+{
+	chap_state *cstate = &chap[unit];
+	
+	BZERO(cstate, sizeof(*cstate));
+	cstate->unit = unit;
+	cstate->clientstate = CHAPCS_INITIAL;
+	cstate->serverstate = CHAPSS_INITIAL;
+	cstate->timeouttime = CHAP_DEFTIMEOUT;
+	cstate->max_transmits = CHAP_DEFTRANSMITS;
+	/* random number generator is initialized in magic_init */
+}
+
+
+/*
+ * ChapChallengeTimeout - Timeout expired on sending challenge.
+ */
+static void ChapChallengeTimeout(void *arg)
+{
+	chap_state *cstate = (chap_state *) arg;
+	
+	/* if we aren't sending challenges, don't worry.  then again we */
+	/* probably shouldn't be here either */
+	if (cstate->serverstate != CHAPSS_INITIAL_CHAL &&
+			cstate->serverstate != CHAPSS_RECHALLENGE)
+		return;
+	
+	if (cstate->chal_transmits >= cstate->max_transmits) {
+		/* give up on peer */
+		CHAPDEBUG((LOG_ERR, "Peer failed to respond to CHAP challenge\n"));
+		cstate->serverstate = CHAPSS_BADAUTH;
+		auth_peer_fail(cstate->unit, PPP_CHAP);
+		return;
+	}
+	
+	ChapSendChallenge(cstate);		/* Re-send challenge */
+}
+
+
+/*
+ * ChapResponseTimeout - Timeout expired on sending response.
+ */
+static void ChapResponseTimeout(void *arg)
+{
+	chap_state *cstate = (chap_state *) arg;
+	
+	/* if we aren't sending a response, don't worry. */
+	if (cstate->clientstate != CHAPCS_RESPONSE)
+		return;
+	
+	ChapSendResponse(cstate);		/* re-send response */
+}
+
+
+/*
+ * ChapRechallenge - Time to challenge the peer again.
+ */
+static void ChapRechallenge(void *arg)
+{
+	chap_state *cstate = (chap_state *) arg;
+	
+	/* if we aren't sending a response, don't worry. */
+	if (cstate->serverstate != CHAPSS_OPEN)
+		return;
+	
+	ChapGenChallenge(cstate);
+	ChapSendChallenge(cstate);
+	cstate->serverstate = CHAPSS_RECHALLENGE;
+}
+
+
+/*
+ * ChapLowerUp - The lower layer is up.
+ *
+ * Start up if we have pending requests.
+ */
+static void ChapLowerUp(int unit)
+{
+	chap_state *cstate = &chap[unit];
+	
+	if (cstate->clientstate == CHAPCS_INITIAL)
+		cstate->clientstate = CHAPCS_CLOSED;
+	else if (cstate->clientstate == CHAPCS_PENDING)
+		cstate->clientstate = CHAPCS_LISTEN;
+	
+	if (cstate->serverstate == CHAPSS_INITIAL)
+		cstate->serverstate = CHAPSS_CLOSED;
+	else if (cstate->serverstate == CHAPSS_PENDING) {
+		ChapGenChallenge(cstate);
+		ChapSendChallenge(cstate);
+		cstate->serverstate = CHAPSS_INITIAL_CHAL;
+	}
+}
+
+
+/*
+ * ChapLowerDown - The lower layer is down.
+ *
+ * Cancel all timeouts.
+ */
+static void ChapLowerDown(int unit)
+{
+	chap_state *cstate = &chap[unit];
+	
+	/* Timeout(s) pending?  Cancel if so. */
+	if (cstate->serverstate == CHAPSS_INITIAL_CHAL ||
+			cstate->serverstate == CHAPSS_RECHALLENGE)
+		UNTIMEOUT(ChapChallengeTimeout, cstate);
+	else if (cstate->serverstate == CHAPSS_OPEN
+			&& cstate->chal_interval != 0)
+		UNTIMEOUT(ChapRechallenge, cstate);
+	if (cstate->clientstate == CHAPCS_RESPONSE)
+		UNTIMEOUT(ChapResponseTimeout, cstate);
+	
+	cstate->clientstate = CHAPCS_INITIAL;
+	cstate->serverstate = CHAPSS_INITIAL;
+}
+
+
+/*
+ * ChapProtocolReject - Peer doesn't grok CHAP.
+ */
+static void ChapProtocolReject(int unit)
+{
+	chap_state *cstate = &chap[unit];
+	
+	if (cstate->serverstate != CHAPSS_INITIAL &&
+			cstate->serverstate != CHAPSS_CLOSED)
+		auth_peer_fail(unit, PPP_CHAP);
+	if (cstate->clientstate != CHAPCS_INITIAL &&
+			cstate->clientstate != CHAPCS_CLOSED)
+		auth_withpeer_fail(unit, PPP_CHAP);
+	ChapLowerDown(unit);		/* shutdown chap */
+}
+
+
+/*
+ * ChapInput - Input CHAP packet.
+ */
+static void ChapInput(int unit, u_char *inpacket, int packet_len)
+{
+	chap_state *cstate = &chap[unit];
+	u_char *inp;
+	u_char code, id;
+	int len;
+	
+	/*
+	 * Parse header (code, id and length).
+	 * If packet too short, drop it.
+	 */
+	inp = inpacket;
+	if (packet_len < CHAP_HEADERLEN) {
+		CHAPDEBUG((LOG_INFO, "ChapInput: rcvd short header.\n"));
+		return;
+	}
+	GETCHAR(code, inp);
+	GETCHAR(id, inp);
+	GETSHORT(len, inp);
+	if (len < CHAP_HEADERLEN) {
+		CHAPDEBUG((LOG_INFO, "ChapInput: rcvd illegal length.\n"));
+		return;
+	}
+	if (len > packet_len) {
+		CHAPDEBUG((LOG_INFO, "ChapInput: rcvd short packet.\n"));
+		return;
+	}
+	len -= CHAP_HEADERLEN;
+	
+	/*
+	 * Action depends on code (as in fact it usually does :-).
+	 */
+	switch (code) {
+	case CHAP_CHALLENGE:
+		ChapReceiveChallenge(cstate, inp, id, len);
+		break;
+	
+	case CHAP_RESPONSE:
+		ChapReceiveResponse(cstate, inp, id, len);
+		break;
+	
+	case CHAP_FAILURE:
+		ChapReceiveFailure(cstate, inp, id, len);
+		break;
+	
+	case CHAP_SUCCESS:
+		ChapReceiveSuccess(cstate, inp, id, len);
+		break;
+	
+	default:				/* Need code reject? */
+		CHAPDEBUG((LOG_WARNING, "Unknown CHAP code (%d) received.\n", code));
+		break;
+	}
+}
+
+
+/*
+ * ChapReceiveChallenge - Receive Challenge and send Response.
+ */
+static void ChapReceiveChallenge(chap_state *cstate, u_char *inp, int id, int len)
+{
+	int rchallenge_len;
+	u_char *rchallenge;
+	int secret_len;
+	char secret[MAXSECRETLEN];
+	char rhostname[256];
+	MD5_CTX mdContext;
+	u_char hash[MD5_SIGNATURE_SIZE];
+	
+	CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: Rcvd id %d.\n", id));
+	if (cstate->clientstate == CHAPCS_CLOSED ||
+		cstate->clientstate == CHAPCS_PENDING) {
+		CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: in state %d\n",
+			   cstate->clientstate));
+		return;
+	}
+	
+	if (len < 2) {
+		CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: rcvd short packet.\n"));
+		return;
+	}
+	
+	GETCHAR(rchallenge_len, inp);
+	len -= sizeof (u_char) + rchallenge_len;	/* now name field length */
+	if (len < 0) {
+		CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: rcvd short packet.\n"));
+		return;
+	}
+	rchallenge = inp;
+	INCPTR(rchallenge_len, inp);
+	
+	if (len >= sizeof(rhostname))
+		len = sizeof(rhostname) - 1;
+	BCOPY(inp, rhostname, len);
+	rhostname[len] = '\000';
+	
+	CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: received name field '%s'\n",
+	       rhostname));
+	
+	/* Microsoft doesn't send their name back in the PPP packet */
+	if (ppp_settings.remote_name[0] != 0 && (ppp_settings.explicit_remote || rhostname[0] == 0)) {
+		strncpy(rhostname, ppp_settings.remote_name, sizeof(rhostname));
+		rhostname[sizeof(rhostname) - 1] = 0;
+		CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: using '%s' as remote name\n",
+			   rhostname));
+	}
+	
+	/* get secret for authenticating ourselves with the specified host */
+	if (!get_secret(cstate->unit, cstate->resp_name, rhostname,
+			    secret, &secret_len, 0)) {
+		secret_len = 0;		/* assume null secret if can't find one */
+		CHAPDEBUG((LOG_WARNING, "No CHAP secret found for authenticating us to %s\n", rhostname));
+	}
+	
+	/* cancel response send timeout if necessary */
+	if (cstate->clientstate == CHAPCS_RESPONSE)
+		UNTIMEOUT(ChapResponseTimeout, cstate);
+	
+	cstate->resp_id = id;
+	cstate->resp_transmits = 0;
+	
+	/*  generate MD based on negotiated type */
+	switch (cstate->resp_type) { 
+	
+	case CHAP_DIGEST_MD5:
+		MD5Init(&mdContext);
+		MD5Update(&mdContext, &cstate->resp_id, 1);
+		MD5Update(&mdContext, (u_char*)secret, secret_len);
+		MD5Update(&mdContext, rchallenge, rchallenge_len);
+		MD5Final(hash, &mdContext);
+		BCOPY(hash, cstate->response, MD5_SIGNATURE_SIZE);
+		cstate->resp_length = MD5_SIGNATURE_SIZE;
+		break;
+	
+#ifdef CHAPMS
+	case CHAP_MICROSOFT:
+		ChapMS(cstate, rchallenge, rchallenge_len, secret, secret_len);
+		break;
+#endif
+	
+	default:
+		CHAPDEBUG((LOG_INFO, "unknown digest type %d\n", cstate->resp_type));
+		return;
+	}
+	
+	BZERO(secret, sizeof(secret));
+	ChapSendResponse(cstate);
+}
+
+
+/*
+ * ChapReceiveResponse - Receive and process response.
+ */
+static void ChapReceiveResponse(chap_state *cstate, u_char *inp, int id, int len)
+{
+	u_char *remmd, remmd_len;
+	int secret_len, old_state;
+	int code;
+	char rhostname[256];
+	MD5_CTX mdContext;
+	char secret[MAXSECRETLEN];
+	u_char hash[MD5_SIGNATURE_SIZE];
+	
+	CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: Rcvd id %d.\n", id));
+	
+	if (cstate->serverstate == CHAPSS_CLOSED ||
+			cstate->serverstate == CHAPSS_PENDING) {
+		CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: in state %d\n",
+		cstate->serverstate));
+		return;
+	}
+	
+	if (id != cstate->chal_id)
+		return;			/* doesn't match ID of last challenge */
+	
+	/*
+	* If we have received a duplicate or bogus Response,
+	* we have to send the same answer (Success/Failure)
+	* as we did for the first Response we saw.
+	*/
+	if (cstate->serverstate == CHAPSS_OPEN) {
+		ChapSendStatus(cstate, CHAP_SUCCESS);
+		return;
+	}
+	if (cstate->serverstate == CHAPSS_BADAUTH) {
+		ChapSendStatus(cstate, CHAP_FAILURE);
+		return;
+	}
+	
+	if (len < 2) {
+		CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: rcvd short packet.\n"));
+		return;
+	}
+	GETCHAR(remmd_len, inp);		/* get length of MD */
+	remmd = inp;			/* get pointer to MD */
+	INCPTR(remmd_len, inp);
+	
+	len -= sizeof (u_char) + remmd_len;
+	if (len < 0) {
+		CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: rcvd short packet.\n"));
+		return;
+	}
+	
+	UNTIMEOUT(ChapChallengeTimeout, cstate);
+	
+	if (len >= sizeof(rhostname))
+		len = sizeof(rhostname) - 1;
+	BCOPY(inp, rhostname, len);
+	rhostname[len] = '\000';
+	
+	CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: received name field: %s\n",
+				rhostname));
+	
+	/*
+	* Get secret for authenticating them with us,
+	* do the hash ourselves, and compare the result.
+	*/
+	code = CHAP_FAILURE;
+	if (!get_secret(cstate->unit, rhostname, cstate->chal_name,
+	secret, &secret_len, 1)) {
+/*        CHAPDEBUG((LOG_WARNING, TL_CHAP, "No CHAP secret found for authenticating %s\n", rhostname)); */
+		CHAPDEBUG((LOG_WARNING, "No CHAP secret found for authenticating %s\n",
+		rhostname));
+	} else {
+	
+		/*  generate MD based on negotiated type */
+		switch (cstate->chal_type) { 
+		
+		case CHAP_DIGEST_MD5:		/* only MD5 is defined for now */
+			if (remmd_len != MD5_SIGNATURE_SIZE)
+				break;			/* it's not even the right length */
+			MD5Init(&mdContext);
+			MD5Update(&mdContext, &cstate->chal_id, 1);
+			MD5Update(&mdContext, (u_char*)secret, secret_len);
+			MD5Update(&mdContext, cstate->challenge, cstate->chal_len);
+			MD5Final(hash, &mdContext); 
+			
+			/* compare local and remote MDs and send the appropriate status */
+			if (memcmp (hash, remmd, MD5_SIGNATURE_SIZE) == 0)
+				code = CHAP_SUCCESS;	/* they are the same! */
+			break;
+		
+		default:
+			CHAPDEBUG((LOG_INFO, "unknown digest type %d\n", cstate->chal_type));
+		}
+	}
+	
+	BZERO(secret, sizeof(secret));
+	ChapSendStatus(cstate, code);
+	
+	if (code == CHAP_SUCCESS) {
+		old_state = cstate->serverstate;
+		cstate->serverstate = CHAPSS_OPEN;
+		if (old_state == CHAPSS_INITIAL_CHAL) {
+			auth_peer_success(cstate->unit, PPP_CHAP, rhostname, len);
+		}
+		if (cstate->chal_interval != 0)
+			TIMEOUT(ChapRechallenge, cstate, cstate->chal_interval);
+	} else {
+		CHAPDEBUG((LOG_ERR, "CHAP peer authentication failed\n"));
+		cstate->serverstate = CHAPSS_BADAUTH;
+		auth_peer_fail(cstate->unit, PPP_CHAP);
+	}
+}
+
+/*
+ * ChapReceiveSuccess - Receive Success
+ */
+static void ChapReceiveSuccess(chap_state *cstate, u_char *inp, u_char id, int len)
+{
+
+	CHAPDEBUG((LOG_INFO, "ChapReceiveSuccess: Rcvd id %d.\n", id));
+	
+	if (cstate->clientstate == CHAPCS_OPEN)
+		/* presumably an answer to a duplicate response */
+		return;
+	
+	if (cstate->clientstate != CHAPCS_RESPONSE) {
+		/* don't know what this is */
+		CHAPDEBUG((LOG_INFO, "ChapReceiveSuccess: in state %d\n",
+			   cstate->clientstate));
+		return;
+	}
+	
+	UNTIMEOUT(ChapResponseTimeout, cstate);
+	
+	/*
+	 * Print message.
+	 */
+	if (len > 0)
+		PRINTMSG(inp, len);
+	
+	cstate->clientstate = CHAPCS_OPEN;
+	
+	auth_withpeer_success(cstate->unit, PPP_CHAP);
+}
+
+
+/*
+ * ChapReceiveFailure - Receive failure.
+ */
+static void ChapReceiveFailure(chap_state *cstate, u_char *inp, u_char id, int len)
+{
+	CHAPDEBUG((LOG_INFO, "ChapReceiveFailure: Rcvd id %d.\n", id));
+	
+	if (cstate->clientstate != CHAPCS_RESPONSE) {
+		/* don't know what this is */
+		CHAPDEBUG((LOG_INFO, "ChapReceiveFailure: in state %d\n",
+			   cstate->clientstate));
+		return;
+	}
+	
+	UNTIMEOUT(ChapResponseTimeout, cstate);
+	
+	/*
+	 * Print message.
+	 */
+	if (len > 0)
+		PRINTMSG(inp, len);
+	
+	CHAPDEBUG((LOG_ERR, "CHAP authentication failed\n"));
+	auth_withpeer_fail(cstate->unit, PPP_CHAP);
+}
+
+
+/*
+ * ChapSendChallenge - Send an Authenticate challenge.
+ */
+static void ChapSendChallenge(chap_state *cstate)
+{
+	u_char *outp;
+	int chal_len, name_len;
+	int outlen;
+	
+	chal_len = cstate->chal_len;
+	name_len = strlen(cstate->chal_name);
+	outlen = CHAP_HEADERLEN + sizeof (u_char) + chal_len + name_len;
+	outp = outpacket_buf[cstate->unit];
+	
+	MAKEHEADER(outp, PPP_CHAP);		/* paste in a CHAP header */
+	
+	PUTCHAR(CHAP_CHALLENGE, outp);
+	PUTCHAR(cstate->chal_id, outp);
+	PUTSHORT(outlen, outp);
+	
+	PUTCHAR(chal_len, outp);		/* put length of challenge */
+	BCOPY(cstate->challenge, outp, chal_len);
+	INCPTR(chal_len, outp);
+	
+	BCOPY(cstate->chal_name, outp, name_len);	/* append hostname */
+	
+	pppWrite(cstate->unit, outpacket_buf[cstate->unit], outlen + PPP_HDRLEN);
+	
+	CHAPDEBUG((LOG_INFO, "ChapSendChallenge: Sent id %d.\n", cstate->chal_id));
+	
+	TIMEOUT(ChapChallengeTimeout, cstate, cstate->timeouttime);
+	++cstate->chal_transmits;
+}
+
+
+/*
+ * ChapSendStatus - Send a status response (ack or nak).
+ */
+static void ChapSendStatus(chap_state *cstate, int code)
+{
+	u_char *outp;
+	int outlen, msglen;
+	char msg[256];
+	
+	if (code == CHAP_SUCCESS)
+		strcpy(msg, "Welcome!");
+	else
+		strcpy(msg, "I don't like you.  Go 'way.");
+	msglen = strlen(msg);
+	
+	outlen = CHAP_HEADERLEN + msglen;
+	outp = outpacket_buf[cstate->unit];
+	
+	MAKEHEADER(outp, PPP_CHAP);		/* paste in a header */
+	
+	PUTCHAR(code, outp);
+	PUTCHAR(cstate->chal_id, outp);
+	PUTSHORT(outlen, outp);
+	BCOPY(msg, outp, msglen);
+	pppWrite(cstate->unit, outpacket_buf[cstate->unit], outlen + PPP_HDRLEN);
+	
+	CHAPDEBUG((LOG_INFO, "ChapSendStatus: Sent code %d, id %d.\n", code,
+	       cstate->chal_id));
+}
+
+/*
+ * ChapGenChallenge is used to generate a pseudo-random challenge string of
+ * a pseudo-random length between min_len and max_len.  The challenge
+ * string and its length are stored in *cstate, and various other fields of
+ * *cstate are initialized.
+ */
+
+static void ChapGenChallenge(chap_state *cstate)
+{
+	int chal_len;
+	u_char *ptr = cstate->challenge;
+	int i;
+	
+	/* pick a random challenge length between MIN_CHALLENGE_LENGTH and 
+	   MAX_CHALLENGE_LENGTH */  
+	chal_len = (unsigned)
+				((((magic() >> 16) *
+			        (MAX_CHALLENGE_LENGTH - MIN_CHALLENGE_LENGTH)) >> 16)
+			     + MIN_CHALLENGE_LENGTH);
+	cstate->chal_len = chal_len;
+	cstate->chal_id = ++cstate->id;
+	cstate->chal_transmits = 0;
+	
+	/* generate a random string */
+	for (i = 0; i < chal_len; i++ )
+		*ptr++ = (char) (magic() & 0xff);
+}
+
+/*
+ * ChapSendResponse - send a response packet with values as specified
+ * in *cstate.
+ */
+/* ARGSUSED */
+static void ChapSendResponse(chap_state *cstate)
+{
+	u_char *outp;
+	int outlen, md_len, name_len;
+	
+	md_len = cstate->resp_length;
+	name_len = strlen(cstate->resp_name);
+	outlen = CHAP_HEADERLEN + sizeof (u_char) + md_len + name_len;
+	outp = outpacket_buf[cstate->unit];
+	
+	MAKEHEADER(outp, PPP_CHAP);
+	
+	PUTCHAR(CHAP_RESPONSE, outp);	/* we are a response */
+	PUTCHAR(cstate->resp_id, outp);	/* copy id from challenge packet */
+	PUTSHORT(outlen, outp);			/* packet length */
+	
+	PUTCHAR(md_len, outp);			/* length of MD */
+	BCOPY(cstate->response, outp, md_len);		/* copy MD to buffer */
+	INCPTR(md_len, outp);
+	
+	BCOPY(cstate->resp_name, outp, name_len);	/* append our name */
+	
+	/* send the packet */
+	pppWrite(cstate->unit, outpacket_buf[cstate->unit], outlen + PPP_HDRLEN);
+	
+	cstate->clientstate = CHAPCS_RESPONSE;
+	TIMEOUT(ChapResponseTimeout, cstate, cstate->timeouttime);
+	++cstate->resp_transmits;
+}
+
+/*
+ * ChapPrintPkt - print the contents of a CHAP packet.
+ */
+static int ChapPrintPkt(
+	u_char *p,
+	int plen,
+	void (*printer) (void *, char *, ...),
+	void *arg
+)
+{
+	int code, id, len;
+	int clen, nlen;
+	u_char x;
+	
+	if (plen < CHAP_HEADERLEN)
+		return 0;
+	GETCHAR(code, p);
+	GETCHAR(id, p);
+	GETSHORT(len, p);
+	if (len < CHAP_HEADERLEN || len > plen)
+		return 0;
+	
+	if (code >= 1 && code <= sizeof(ChapCodenames) / sizeof(char *))
+		printer(arg, " %s", ChapCodenames[code-1]);
+	else
+		printer(arg, " code=0x%x", code);
+	printer(arg, " id=0x%x", id);
+	len -= CHAP_HEADERLEN;
+	switch (code) {
+	case CHAP_CHALLENGE:
+	case CHAP_RESPONSE:
+		if (len < 1)
+			break;
+		clen = p[0];
+		if (len < clen + 1)
+			break;
+		++p;
+		nlen = len - clen - 1;
+		printer(arg, " <");
+		for (; clen > 0; --clen) {
+			GETCHAR(x, p);
+			printer(arg, "%.2x", x);
+		}
+		printer(arg, ">, name = %.*Z", nlen, p);
+		break;
+	case CHAP_FAILURE:
+	case CHAP_SUCCESS:
+		printer(arg, " %.*Z", len, p);
+		break;
+	default:
+		for (clen = len; clen > 0; --clen) {
+			GETCHAR(x, p);
+			printer(arg, " %.2x", x);
+		}
+	}
+	
+	return len + CHAP_HEADERLEN;
+}
+
+#endif
+
+#endif /* PPP_SUPPORT */
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/chap.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/chap.h
new file mode 100644
index 000000000..1aca13414
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/chap.h
@@ -0,0 +1,167 @@
+/*****************************************************************************
+* chap.h - Network Challenge Handshake Authentication Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1998 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-03 Guy Lancaster , Global Election Systems Inc.
+*	Original built from BSD network code.
+******************************************************************************/
+/*
+ * chap.h - Challenge Handshake Authentication Protocol definitions.
+ *
+ * Copyright (c) 1993 The Australian National University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the Australian National University.  The name of the University
+ * may not be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Copyright (c) 1991 Gregory M. Christy
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the author.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * $Id: chap.h,v 1.1 2003/05/27 14:37:56 jani Exp $
+ */
+
+#ifndef CHAP_H
+#define CHAP_H
+
+/*************************
+*** PUBLIC DEFINITIONS ***
+*************************/
+
+/* Code + ID + length */
+#define CHAP_HEADERLEN		4
+
+/*
+ * CHAP codes.
+ */
+
+#define CHAP_DIGEST_MD5		5	/* use MD5 algorithm */
+#define MD5_SIGNATURE_SIZE	16	/* 16 bytes in a MD5 message digest */
+#define CHAP_MICROSOFT		0x80	/* use Microsoft-compatible alg. */
+#define MS_CHAP_RESPONSE_LEN	49	/* Response length for MS-CHAP */
+
+#define CHAP_CHALLENGE		1
+#define CHAP_RESPONSE		2
+#define CHAP_SUCCESS		3
+#define CHAP_FAILURE    	4
+
+/*
+ *  Challenge lengths (for challenges we send) and other limits.
+ */
+#define MIN_CHALLENGE_LENGTH	32
+#define MAX_CHALLENGE_LENGTH	64
+#define MAX_RESPONSE_LENGTH	64	/* sufficient for MD5 or MS-CHAP */
+
+/*
+ * Client (peer) states.
+ */
+#define CHAPCS_INITIAL		0	/* Lower layer down, not opened */
+#define CHAPCS_CLOSED		1	/* Lower layer up, not opened */
+#define CHAPCS_PENDING		2	/* Auth us to peer when lower up */
+#define CHAPCS_LISTEN		3	/* Listening for a challenge */
+#define CHAPCS_RESPONSE		4	/* Sent response, waiting for status */
+#define CHAPCS_OPEN		5	/* We've received Success */
+
+/*
+ * Server (authenticator) states.
+ */
+#define CHAPSS_INITIAL		0	/* Lower layer down, not opened */
+#define CHAPSS_CLOSED		1	/* Lower layer up, not opened */
+#define CHAPSS_PENDING		2	/* Auth peer when lower up */
+#define CHAPSS_INITIAL_CHAL	3	/* We've sent the first challenge */
+#define CHAPSS_OPEN		4	/* We've sent a Success msg */
+#define CHAPSS_RECHALLENGE	5	/* We've sent another challenge */
+#define CHAPSS_BADAUTH		6	/* We've sent a Failure msg */
+
+/************************
+*** PUBLIC DATA TYPES ***
+************************/
+
+/*
+ * Each interface is described by a chap structure.
+ */
+
+typedef struct chap_state {
+    int unit;			/* Interface unit number */
+    int clientstate;		/* Client state */
+    int serverstate;		/* Server state */
+    u_char challenge[MAX_CHALLENGE_LENGTH]; /* last challenge string sent */
+    u_char chal_len;		/* challenge length */
+    u_char chal_id;		/* ID of last challenge */
+    u_char chal_type;		/* hash algorithm for challenges */
+    u_char id;			/* Current id */
+    char *chal_name;		/* Our name to use with challenge */
+    int chal_interval;		/* Time until we challenge peer again */
+    int timeouttime;		/* Timeout time in seconds */
+    int max_transmits;		/* Maximum # of challenge transmissions */
+    int chal_transmits;		/* Number of transmissions of challenge */
+    int resp_transmits;		/* Number of transmissions of response */
+    u_char response[MAX_RESPONSE_LENGTH];	/* Response to send */
+    u_char resp_length;		/* length of response */
+    u_char resp_id;		/* ID for response messages */
+    u_char resp_type;		/* hash algorithm for responses */
+    char *resp_name;		/* Our name to send with response */
+} chap_state;
+
+
+/******************
+*** PUBLIC DATA ***
+******************/
+extern chap_state chap[];
+
+extern struct protent chap_protent;
+
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+
+void ChapAuthWithPeer (int, char *, int);
+void ChapAuthPeer (int, char *, int);
+
+#endif /* CHAP_H */
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/chpms.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/chpms.c
new file mode 100644
index 000000000..306434460
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/chpms.c
@@ -0,0 +1,398 @@
+/*** WARNING - THIS CODE HAS NOT BEEN FINISHED! ***/
+/*****************************************************************************
+* chpms.c - Network MicroSoft Challenge Handshake Authentication Protocol program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* Copyright (c) 1997 by Global Election Systems Inc.  All rights reserved.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-08 Guy Lancaster , Global Election Systems Inc.
+*	Original based on BSD chap_ms.c.
+*****************************************************************************/
+/*
+ * chap_ms.c - Microsoft MS-CHAP compatible implementation.
+ *
+ * Copyright (c) 1995 Eric Rosenquist, Strata Software Limited.
+ * http://www.strataware.com/
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Eric Rosenquist.  The name of the author may not be used to
+ * endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+/*
+ * Modifications by Lauri Pesonen / lpesonen@clinet.fi, april 1997
+ *
+ *   Implemented LANManager type password response to MS-CHAP challenges.
+ *   Now pppd provides both NT style and LANMan style blocks, and the
+ *   prefered is set by option "ms-lanman". Default is to use NT.
+ *   The hash text (StdText) was taken from Win95 RASAPI32.DLL.
+ *
+ *   You should also use DOMAIN\\USERNAME as described in README.MSCHAP80
+ */
+
+#define USE_CRYPT
+
+
+#include "ppp.h"
+
+#if MSCHAP_SUPPORT > 0
+
+#include "md4.h"
+#ifndef USE_CRYPT
+#include "des.h"
+#endif
+#include "chap.h"
+#include "chpms.h"
+#include "pppdebug.h"
+
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+
+
+/************************/
+/*** LOCAL DATA TYPES ***/
+/************************/
+typedef struct {
+    u_char LANManResp[24];
+    u_char NTResp[24];
+    u_char UseNT;		/* If 1, ignore the LANMan response field */
+} MS_ChapResponse;
+/* We use MS_CHAP_RESPONSE_LEN, rather than sizeof(MS_ChapResponse),
+   in case this struct gets padded. */
+
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+
+/* XXX Don't know what to do with these. */
+extern void setkey(const char *);
+extern void encrypt(char *, int);
+
+static void	DesEncrypt (u_char *, u_char *, u_char *);
+static void	MakeKey (u_char *, u_char *);
+
+#ifdef USE_CRYPT
+static void	Expand (u_char *, u_char *);
+static void	Collapse (u_char *, u_char *);
+#endif
+
+static void ChallengeResponse(
+	u_char *challenge,	/* IN   8 octets */
+	u_char *pwHash,		/* IN  16 octets */
+	u_char *response	/* OUT 24 octets */
+);
+static void ChapMS_NT(
+	char *rchallenge,
+	int rchallenge_len,
+	char *secret,
+	int secret_len,
+	MS_ChapResponse *response
+);
+static u_char Get7Bits(
+	u_char *input,
+	int startBit
+);
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+void ChapMS(
+	chap_state *cstate,
+	char *rchallenge,
+	int rchallenge_len,
+	char *secret,
+	int secret_len
+)
+{
+	MS_ChapResponse	response;
+#ifdef MSLANMAN
+	extern int ms_lanman;
+#endif
+	
+#if 0
+	CHAPDEBUG((LOG_INFO, "ChapMS: secret is '%.*s'\n", secret_len, secret));
+#endif
+	BZERO(&response, sizeof(response));
+	
+	/* Calculate both always */
+	ChapMS_NT(rchallenge, rchallenge_len, secret, secret_len, &response);
+	
+#ifdef MSLANMAN
+	ChapMS_LANMan(rchallenge, rchallenge_len, secret, secret_len, &response);
+	
+	/* prefered method is set by option  */
+	response.UseNT = !ms_lanman;
+#else
+	response.UseNT = 1;
+#endif
+	
+	BCOPY(&response, cstate->response, MS_CHAP_RESPONSE_LEN);
+	cstate->resp_length = MS_CHAP_RESPONSE_LEN;
+}
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+static void ChallengeResponse(
+	u_char *challenge,	/* IN   8 octets */
+	u_char *pwHash,		/* IN  16 octets */
+	u_char *response	/* OUT 24 octets */
+)
+{
+	char    ZPasswordHash[21];
+	
+	BZERO(ZPasswordHash, sizeof(ZPasswordHash));
+	BCOPY(pwHash, ZPasswordHash, 16);
+	
+#if 0
+	log_packet(ZPasswordHash, sizeof(ZPasswordHash), "ChallengeResponse - ZPasswordHash", LOG_DEBUG);
+#endif
+	
+	DesEncrypt(challenge, ZPasswordHash +  0, response + 0);
+	DesEncrypt(challenge, ZPasswordHash +  7, response + 8);
+	DesEncrypt(challenge, ZPasswordHash + 14, response + 16);
+	
+#if 0
+	log_packet(response, 24, "ChallengeResponse - response", LOG_DEBUG);
+#endif
+}
+
+
+#ifdef USE_CRYPT
+static void DesEncrypt(
+	u_char *clear,	/* IN  8 octets */
+	u_char *key,	/* IN  7 octets */
+	u_char *cipher	/* OUT 8 octets */
+)
+{
+	u_char des_key[8];
+	u_char crypt_key[66];
+	u_char des_input[66];
+	
+	MakeKey(key, des_key);
+	
+	Expand(des_key, crypt_key);
+	setkey(crypt_key);
+	
+#if 0
+	CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet input : %02X%02X%02X%02X%02X%02X%02X%02X\n",
+	       clear[0], clear[1], clear[2], clear[3], clear[4], clear[5], clear[6], clear[7]));
+#endif
+	
+	Expand(clear, des_input);
+	encrypt(des_input, 0);
+	Collapse(des_input, cipher);
+	
+#if 0
+	CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet output: %02X%02X%02X%02X%02X%02X%02X%02X\n",
+	       cipher[0], cipher[1], cipher[2], cipher[3], cipher[4], cipher[5], cipher[6], cipher[7]));
+#endif
+}
+
+#else /* USE_CRYPT */
+
+static void DesEncrypt(
+	u_char *clear,	/* IN  8 octets */
+	u_char *key,	/* IN  7 octets */
+	u_char *cipher	/* OUT 8 octets */
+)
+{
+	des_cblock		des_key;
+	des_key_schedule	key_schedule;
+	
+	MakeKey(key, des_key);
+	
+	des_set_key(&des_key, key_schedule);
+	
+#if 0
+	CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet input : %02X%02X%02X%02X%02X%02X%02X%02X\n",
+	       clear[0], clear[1], clear[2], clear[3], clear[4], clear[5], clear[6], clear[7]));
+#endif
+	
+	des_ecb_encrypt((des_cblock *)clear, (des_cblock *)cipher, key_schedule, 1);
+	
+#if 0
+	CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet output: %02X%02X%02X%02X%02X%02X%02X%02X\n",
+	       cipher[0], cipher[1], cipher[2], cipher[3], cipher[4], cipher[5], cipher[6], cipher[7]));
+#endif
+}
+
+#endif /* USE_CRYPT */
+
+
+static u_char Get7Bits(
+	u_char *input,
+	int startBit
+)
+{
+	register unsigned int	word;
+	
+	word  = (unsigned)input[startBit / 8] << 8;
+	word |= (unsigned)input[startBit / 8 + 1];
+	
+	word >>= 15 - (startBit % 8 + 7);
+	
+	return word & 0xFE;
+}
+
+#ifdef USE_CRYPT
+
+/* in == 8-byte string (expanded version of the 56-bit key)
+ * out == 64-byte string where each byte is either 1 or 0
+ * Note that the low-order "bit" is always ignored by by setkey()
+ */
+static void Expand(u_char *in, u_char *out)
+{
+	int j, c;
+	int i;
+	
+	for(i = 0; i < 64; in++){
+		c = *in;
+		for(j = 7; j >= 0; j--)
+			*out++ = (c >> j) & 01;
+		i += 8;
+	}
+}
+
+/* The inverse of Expand
+ */
+static void Collapse(u_char *in, u_char *out)
+{
+	int j;
+	int i;
+	unsigned int c;
+	
+	for (i = 0; i < 64; i += 8, out++) {
+		c = 0;
+		for (j = 7; j >= 0; j--, in++)
+			c |= *in << j;
+		*out = c & 0xff;
+	}
+}
+#endif
+
+static void MakeKey(
+	u_char *key,		/* IN  56 bit DES key missing parity bits */
+	u_char *des_key		/* OUT 64 bit DES key with parity bits added */
+)
+{
+	des_key[0] = Get7Bits(key,  0);
+	des_key[1] = Get7Bits(key,  7);
+	des_key[2] = Get7Bits(key, 14);
+	des_key[3] = Get7Bits(key, 21);
+	des_key[4] = Get7Bits(key, 28);
+	des_key[5] = Get7Bits(key, 35);
+	des_key[6] = Get7Bits(key, 42);
+	des_key[7] = Get7Bits(key, 49);
+	
+#ifndef USE_CRYPT
+	des_set_odd_parity((des_cblock *)des_key);
+#endif
+	
+#if 0
+	CHAPDEBUG((LOG_INFO, "MakeKey: 56-bit input : %02X%02X%02X%02X%02X%02X%02X\n",
+	       key[0], key[1], key[2], key[3], key[4], key[5], key[6]));
+	CHAPDEBUG((LOG_INFO, "MakeKey: 64-bit output: %02X%02X%02X%02X%02X%02X%02X%02X\n",
+	       des_key[0], des_key[1], des_key[2], des_key[3], des_key[4], des_key[5], des_key[6], des_key[7]));
+#endif
+}
+
+static void ChapMS_NT(
+	char *rchallenge,
+	int rchallenge_len,
+	char *secret,
+	int secret_len,
+	MS_ChapResponse *response
+)
+{
+	int			i;
+	MDstruct	md4Context;
+	u_char		unicodePassword[MAX_NT_PASSWORD * 2];
+	static int	low_byte_first = -1;
+	
+	/* Initialize the Unicode version of the secret (== password). */
+	/* This implicitly supports 8-bit ISO8859/1 characters. */
+	BZERO(unicodePassword, sizeof(unicodePassword));
+	for (i = 0; i < secret_len; i++)
+		unicodePassword[i * 2] = (u_char)secret[i];
+	
+	MDbegin(&md4Context);
+	MDupdate(&md4Context, unicodePassword, secret_len * 2 * 8);	/* Unicode is 2 bytes/char, *8 for bit count */
+	
+	if (low_byte_first == -1)
+		low_byte_first = (htons((unsigned short int)1) != 1);
+	if (low_byte_first == 0)
+		MDreverse((u_long *)&md4Context);  /*  sfb 961105 */
+	
+	MDupdate(&md4Context, NULL, 0);	/* Tell MD4 we're done */
+	
+	ChallengeResponse(rchallenge, (char *)md4Context.buffer, response->NTResp);
+}
+
+#ifdef MSLANMAN
+static u_char *StdText = (u_char *)"KGS!@#$%"; /* key from rasapi32.dll */
+
+static ChapMS_LANMan(
+	char *rchallenge,
+	int rchallenge_len,
+	char *secret,
+	int secret_len,
+	MS_ChapResponse	*response
+)
+{
+	int			i;
+	u_char		UcasePassword[MAX_NT_PASSWORD]; /* max is actually 14 */
+	u_char		PasswordHash[16];
+	
+	/* LANMan password is case insensitive */
+	BZERO(UcasePassword, sizeof(UcasePassword));
+	for (i = 0; i < secret_len; i++)
+		UcasePassword[i] = (u_char)toupper(secret[i]);
+	DesEncrypt( StdText, UcasePassword + 0, PasswordHash + 0 );
+	DesEncrypt( StdText, UcasePassword + 7, PasswordHash + 8 );
+	ChallengeResponse(rchallenge, PasswordHash, response->LANManResp);
+}
+#endif
+
+#endif /* MSCHAP_SUPPORT */
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/chpms.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/chpms.h
new file mode 100644
index 000000000..0b30c6554
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/chpms.h
@@ -0,0 +1,64 @@
+/*****************************************************************************
+* chpms.h - Network Microsoft Challenge Handshake Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1998 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 98-01-30 Guy Lancaster , Global Election Systems Inc.
+*	Original built from BSD network code.
+******************************************************************************/
+/*
+ * chap.h - Challenge Handshake Authentication Protocol definitions.
+ *
+ * Copyright (c) 1995 Eric Rosenquist, Strata Software Limited.
+ * http://www.strataware.com/
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Eric Rosenquist.  The name of the author may not be used to
+ * endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * $Id: chpms.h,v 1.3 2004/02/07 00:30:03 likewise Exp $
+ */
+
+#ifndef CHPMS_H
+#define CHPMS_H
+
+#define MAX_NT_PASSWORD	256	/* Maximum number of (Unicode) chars in an NT password */
+
+void ChapMS (chap_state *, char *, int, char *, int);
+
+#endif /* CHPMS_H */
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/fsm.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/fsm.c
new file mode 100644
index 000000000..6cad71525
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/fsm.c
@@ -0,0 +1,838 @@
+/*****************************************************************************
+* fsm.c - Network Control Protocol Finite State Machine program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-01 Guy Lancaster , Global Election Systems Inc.
+*	Original based on BSD fsm.c.
+*****************************************************************************/
+/*
+ * fsm.c - {Link, IP} Control Protocol Finite State Machine.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+
+/*
+ * TODO:
+ * Randomize fsm id on link/init.
+ * Deal with variable outgoing MTU.
+ */
+
+#include "ppp.h"
+#if PPP_SUPPORT > 0
+#include "fsm.h"
+#include "pppdebug.h"
+
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+
+
+/************************/
+/*** LOCAL DATA TYPES ***/
+/************************/
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+static void fsm_timeout (void *);
+static void fsm_rconfreq (fsm *, u_char, u_char *, int);
+static void fsm_rconfack (fsm *, int, u_char *, int);
+static void fsm_rconfnakrej (fsm *, int, int, u_char *, int);
+static void fsm_rtermreq (fsm *, int, u_char *, int);
+static void fsm_rtermack (fsm *);
+static void fsm_rcoderej (fsm *, u_char *, int);
+static void fsm_sconfreq (fsm *, int);
+
+#define PROTO_NAME(f)	((f)->callbacks->proto_name)
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+int peer_mru[NUM_PPP];
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+
+/*
+ * fsm_init - Initialize fsm.
+ *
+ * Initialize fsm state.
+ */
+void fsm_init(fsm *f)
+{
+	f->state = INITIAL;
+	f->flags = 0;
+	f->id = 0;				/* XXX Start with random id? */
+	f->timeouttime = FSM_DEFTIMEOUT;
+	f->maxconfreqtransmits = FSM_DEFMAXCONFREQS;
+	f->maxtermtransmits = FSM_DEFMAXTERMREQS;
+	f->maxnakloops = FSM_DEFMAXNAKLOOPS;
+	f->term_reason_len = 0;
+}
+
+
+/*
+ * fsm_lowerup - The lower layer is up.
+ */
+void fsm_lowerup(fsm *f)
+{
+	int oldState = f->state;
+
+	switch( f->state ){
+	case INITIAL:
+		f->state = CLOSED;
+		break;
+	
+	case STARTING:
+		if( f->flags & OPT_SILENT )
+			f->state = STOPPED;
+		else {
+			/* Send an initial configure-request */
+			fsm_sconfreq(f, 0);
+			f->state = REQSENT;
+		}
+	break;
+	
+	default:
+		FSMDEBUG((LOG_INFO, "%s: Up event in state %d!\n",
+				PROTO_NAME(f), f->state));
+	}
+	
+	FSMDEBUG((LOG_INFO, "%s: lowerup state %d -> %d\n",
+			PROTO_NAME(f), oldState, f->state));
+}
+
+
+/*
+ * fsm_lowerdown - The lower layer is down.
+ *
+ * Cancel all timeouts and inform upper layers.
+ */
+void fsm_lowerdown(fsm *f)
+{
+	int oldState = f->state;
+	
+	switch( f->state ){
+	case CLOSED:
+		f->state = INITIAL;
+		break;
+	
+	case STOPPED:
+		f->state = STARTING;
+		if( f->callbacks->starting )
+			(*f->callbacks->starting)(f);
+		break;
+	
+	case CLOSING:
+		f->state = INITIAL;
+		UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+		break;
+	
+	case STOPPING:
+	case REQSENT:
+	case ACKRCVD:
+	case ACKSENT:
+		f->state = STARTING;
+		UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+		break;
+	
+	case OPENED:
+		if( f->callbacks->down )
+			(*f->callbacks->down)(f);
+		f->state = STARTING;
+		break;
+	
+	default:
+		FSMDEBUG((LOG_INFO, "%s: Down event in state %d!\n",
+				PROTO_NAME(f), f->state));
+	}
+	
+	FSMDEBUG((LOG_INFO, "%s: lowerdown state %d -> %d\n",
+			PROTO_NAME(f), oldState, f->state));
+}
+
+
+/*
+ * fsm_open - Link is allowed to come up.
+ */
+void fsm_open(fsm *f)
+{
+	int oldState = f->state;
+	
+	switch( f->state ){
+		case INITIAL:
+			f->state = STARTING;
+			if( f->callbacks->starting )
+				(*f->callbacks->starting)(f);
+			break;
+		
+		case CLOSED:
+		if( f->flags & OPT_SILENT )
+			f->state = STOPPED;
+		else {
+			/* Send an initial configure-request */
+			fsm_sconfreq(f, 0);
+			f->state = REQSENT;
+		}
+		break;
+	
+	case CLOSING:
+		f->state = STOPPING;
+		/* fall through */
+	case STOPPED:
+	case OPENED:
+		if( f->flags & OPT_RESTART ){
+			fsm_lowerdown(f);
+			fsm_lowerup(f);
+		}
+		break;
+	}
+	
+	FSMDEBUG((LOG_INFO, "%s: open state %d -> %d\n",
+			PROTO_NAME(f), oldState, f->state));
+}
+
+
+/*
+ * fsm_close - Start closing connection.
+ *
+ * Cancel timeouts and either initiate close or possibly go directly to
+ * the CLOSED state.
+ */
+void fsm_close(fsm *f, char *reason)
+{
+	int oldState = f->state;
+	
+	f->term_reason = reason;
+	f->term_reason_len = (reason == NULL? 0: strlen(reason));
+	switch( f->state ){
+	case STARTING:
+		f->state = INITIAL;
+		break;
+	case STOPPED:
+		f->state = CLOSED;
+		break;
+	case STOPPING:
+		f->state = CLOSING;
+		break;
+	
+	case REQSENT:
+	case ACKRCVD:
+	case ACKSENT:
+	case OPENED:
+		if( f->state != OPENED )
+			UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+		else if( f->callbacks->down )
+			(*f->callbacks->down)(f);	/* Inform upper layers we're down */
+		
+		/* Init restart counter, send Terminate-Request */
+		f->retransmits = f->maxtermtransmits;
+		fsm_sdata(f, TERMREQ, f->reqid = ++f->id,
+					(u_char *) f->term_reason, f->term_reason_len);
+		TIMEOUT(fsm_timeout, f, f->timeouttime);
+		--f->retransmits;
+		
+		f->state = CLOSING;
+		break;
+	}
+	
+	FSMDEBUG((LOG_INFO, "%s: close reason=%s state %d -> %d\n",
+			PROTO_NAME(f), reason, oldState, f->state));
+}
+
+
+/*
+ * fsm_sdata - Send some data.
+ *
+ * Used for all packets sent to our peer by this module.
+ */
+void fsm_sdata(
+	fsm *f,
+	u_char code, 
+	u_char id,
+	u_char *data,
+	int datalen
+)
+{
+	u_char *outp;
+	int outlen;
+	
+	/* Adjust length to be smaller than MTU */
+	outp = outpacket_buf[f->unit];
+	if (datalen > peer_mru[f->unit] - (int)HEADERLEN)
+		datalen = peer_mru[f->unit] - HEADERLEN;
+	if (datalen && data != outp + PPP_HDRLEN + HEADERLEN)
+		BCOPY(data, outp + PPP_HDRLEN + HEADERLEN, datalen);
+	outlen = datalen + HEADERLEN;
+	MAKEHEADER(outp, f->protocol);
+	PUTCHAR(code, outp);
+	PUTCHAR(id, outp);
+	PUTSHORT(outlen, outp);
+	pppWrite(f->unit, outpacket_buf[f->unit], outlen + PPP_HDRLEN);
+	FSMDEBUG((LOG_INFO, "fsm_sdata(%s): Sent code %d,%d,%d.\n",
+				PROTO_NAME(f), code, id, outlen));
+}
+
+
+/*
+ * fsm_input - Input packet.
+ */
+void fsm_input(fsm *f, u_char *inpacket, int l)
+{
+	u_char *inp = inpacket;
+	u_char code, id;
+	int len;
+	
+	/*
+	* Parse header (code, id and length).
+	* If packet too short, drop it.
+	*/
+	if (l < HEADERLEN) {
+		FSMDEBUG((LOG_WARNING, "fsm_input(%x): Rcvd short header.\n",
+					f->protocol));
+		return;
+	}
+	GETCHAR(code, inp);
+	GETCHAR(id, inp);
+	GETSHORT(len, inp);
+	if (len < HEADERLEN) {
+		FSMDEBUG((LOG_INFO, "fsm_input(%x): Rcvd illegal length.\n",
+				f->protocol));
+		return;
+	}
+	if (len > l) {
+		FSMDEBUG((LOG_INFO, "fsm_input(%x): Rcvd short packet.\n",
+				f->protocol));
+		return;
+	}
+	len -= HEADERLEN;		/* subtract header length */
+	
+	if( f->state == INITIAL || f->state == STARTING ){
+		FSMDEBUG((LOG_INFO, "fsm_input(%x): Rcvd packet in state %d.\n",
+				f->protocol, f->state));
+		return;
+	}
+	FSMDEBUG((LOG_INFO, "fsm_input(%s):%d,%d,%d\n", PROTO_NAME(f), code, id, l));
+	/*
+	 * Action depends on code.
+	 */
+	switch (code) {
+	case CONFREQ:
+		fsm_rconfreq(f, id, inp, len);
+		break;
+	
+	case CONFACK:
+		fsm_rconfack(f, id, inp, len);
+		break;
+	
+	case CONFNAK:
+	case CONFREJ:
+		fsm_rconfnakrej(f, code, id, inp, len);
+		break;
+	
+	case TERMREQ:
+		fsm_rtermreq(f, id, inp, len);
+		break;
+	
+	case TERMACK:
+		fsm_rtermack(f);
+		break;
+	
+	case CODEREJ:
+		fsm_rcoderej(f, inp, len);
+		break;
+	
+	default:
+		if( !f->callbacks->extcode
+				|| !(*f->callbacks->extcode)(f, code, id, inp, len) )
+			fsm_sdata(f, CODEREJ, ++f->id, inpacket, len + HEADERLEN);
+		break;
+	}
+}
+
+
+/*
+ * fsm_protreject - Peer doesn't speak this protocol.
+ *
+ * Treat this as a catastrophic error (RXJ-).
+ */
+void fsm_protreject(fsm *f)
+{
+	switch( f->state ){
+	case CLOSING:
+		UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+		/* fall through */
+	case CLOSED:
+		f->state = CLOSED;
+		if( f->callbacks->finished )
+			(*f->callbacks->finished)(f);
+		break;
+	
+	case STOPPING:
+	case REQSENT:
+	case ACKRCVD:
+	case ACKSENT:
+		UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+		/* fall through */
+	case STOPPED:
+		f->state = STOPPED;
+		if( f->callbacks->finished )
+			(*f->callbacks->finished)(f);
+		break;
+	
+	case OPENED:
+		if( f->callbacks->down )
+			(*f->callbacks->down)(f);
+		
+		/* Init restart counter, send Terminate-Request */
+		f->retransmits = f->maxtermtransmits;
+		fsm_sdata(f, TERMREQ, f->reqid = ++f->id,
+					(u_char *) f->term_reason, f->term_reason_len);
+		TIMEOUT(fsm_timeout, f, f->timeouttime);
+		--f->retransmits;
+		
+		f->state = STOPPING;
+		break;
+	
+	default:
+		FSMDEBUG((LOG_INFO, "%s: Protocol-reject event in state %d!\n",
+					PROTO_NAME(f), f->state));
+	}
+}
+
+
+
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+
+/*
+ * fsm_timeout - Timeout expired.
+ */
+static void fsm_timeout(void *arg)
+{
+    fsm *f = (fsm *) arg;
+
+    switch (f->state) {
+    case CLOSING:
+    case STOPPING:
+		if( f->retransmits <= 0 ){
+		    FSMDEBUG((LOG_WARNING, "%s: timeout sending Terminate-Request state=%d\n",
+					   PROTO_NAME(f), f->state));
+		    /*
+		     * We've waited for an ack long enough.  Peer probably heard us.
+		     */
+		    f->state = (f->state == CLOSING)? CLOSED: STOPPED;
+		    if( f->callbacks->finished )
+			(*f->callbacks->finished)(f);
+		} else {
+		    FSMDEBUG((LOG_WARNING, "%s: timeout resending Terminate-Requests state=%d\n",
+					   PROTO_NAME(f), f->state));
+		    /* Send Terminate-Request */
+		    fsm_sdata(f, TERMREQ, f->reqid = ++f->id,
+			      (u_char *) f->term_reason, f->term_reason_len);
+		    TIMEOUT(fsm_timeout, f, f->timeouttime);
+		    --f->retransmits;
+		}
+		break;
+
+    case REQSENT:
+    case ACKRCVD:
+    case ACKSENT:
+		if (f->retransmits <= 0) {
+		    FSMDEBUG((LOG_WARNING, "%s: timeout sending Config-Requests state=%d\n",
+			   PROTO_NAME(f), f->state));
+		    f->state = STOPPED;
+		    if( (f->flags & OPT_PASSIVE) == 0 && f->callbacks->finished )
+				(*f->callbacks->finished)(f);
+	
+		} else {
+		    FSMDEBUG((LOG_WARNING, "%s: timeout resending Config-Request state=%d\n",
+			   PROTO_NAME(f), f->state));
+		    /* Retransmit the configure-request */
+		    if (f->callbacks->retransmit)
+				(*f->callbacks->retransmit)(f);
+		    fsm_sconfreq(f, 1);		/* Re-send Configure-Request */
+		    if( f->state == ACKRCVD )
+				f->state = REQSENT;
+		}
+		break;
+
+    default:
+		FSMDEBUG((LOG_INFO, "%s: Timeout event in state %d!\n",
+				  PROTO_NAME(f), f->state));
+	    }
+}
+
+
+/*
+ * fsm_rconfreq - Receive Configure-Request.
+ */
+static void fsm_rconfreq(fsm *f, u_char id, u_char *inp, int len)
+{
+	int code, reject_if_disagree;
+	
+	FSMDEBUG((LOG_INFO, "fsm_rconfreq(%s): Rcvd id %d state=%d\n", 
+				PROTO_NAME(f), id, f->state));
+	switch( f->state ){
+	case CLOSED:
+		/* Go away, we're closed */
+		fsm_sdata(f, TERMACK, id, NULL, 0);
+		return;
+	case CLOSING:
+	case STOPPING:
+		return;
+	
+	case OPENED:
+		/* Go down and restart negotiation */
+		if( f->callbacks->down )
+			(*f->callbacks->down)(f);	/* Inform upper layers */
+		fsm_sconfreq(f, 0);		/* Send initial Configure-Request */
+		break;
+	
+	case STOPPED:
+		/* Negotiation started by our peer */
+		fsm_sconfreq(f, 0);		/* Send initial Configure-Request */
+		f->state = REQSENT;
+		break;
+	}
+	
+	/*
+	* Pass the requested configuration options
+	* to protocol-specific code for checking.
+	*/
+	if (f->callbacks->reqci){		/* Check CI */
+		reject_if_disagree = (f->nakloops >= f->maxnakloops);
+		code = (*f->callbacks->reqci)(f, inp, &len, reject_if_disagree);
+	} 
+	else if (len)
+		code = CONFREJ;			/* Reject all CI */
+	else
+		code = CONFACK;
+	
+	/* send the Ack, Nak or Rej to the peer */
+	fsm_sdata(f, (u_char)code, id, inp, len);
+	
+	if (code == CONFACK) {
+		if (f->state == ACKRCVD) {
+			UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+			f->state = OPENED;
+			if (f->callbacks->up)
+				(*f->callbacks->up)(f);	/* Inform upper layers */
+		} 
+		else
+			f->state = ACKSENT;
+		f->nakloops = 0;
+	} 
+	else {
+		/* we sent CONFACK or CONFREJ */
+		if (f->state != ACKRCVD)
+			f->state = REQSENT;
+		if( code == CONFNAK )
+			++f->nakloops;
+	}
+}
+
+
+/*
+ * fsm_rconfack - Receive Configure-Ack.
+ */
+static void fsm_rconfack(fsm *f, int id, u_char *inp, int len)
+{
+	FSMDEBUG((LOG_INFO, "fsm_rconfack(%s): Rcvd id %d state=%d\n",
+				PROTO_NAME(f), id, f->state));
+	
+	if (id != f->reqid || f->seen_ack)		/* Expected id? */
+		return;					/* Nope, toss... */
+	if( !(f->callbacks->ackci? (*f->callbacks->ackci)(f, inp, len):
+								(len == 0)) ){
+		/* Ack is bad - ignore it */
+		FSMDEBUG((LOG_INFO, "%s: received bad Ack (length %d)\n",
+					PROTO_NAME(f), len));
+		return;
+	}
+	f->seen_ack = 1;
+	
+	switch (f->state) {
+	case CLOSED:
+	case STOPPED:
+		fsm_sdata(f, TERMACK, (u_char)id, NULL, 0);
+		break;
+	
+	case REQSENT:
+		f->state = ACKRCVD;
+		f->retransmits = f->maxconfreqtransmits;
+		break;
+	
+	case ACKRCVD:
+		/* Huh? an extra valid Ack? oh well... */
+		UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+		fsm_sconfreq(f, 0);
+		f->state = REQSENT;
+		break;
+	
+	case ACKSENT:
+		UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+		f->state = OPENED;
+		f->retransmits = f->maxconfreqtransmits;
+		if (f->callbacks->up)
+			(*f->callbacks->up)(f);	/* Inform upper layers */
+		break;
+	
+	case OPENED:
+		/* Go down and restart negotiation */
+		if (f->callbacks->down)
+			(*f->callbacks->down)(f);	/* Inform upper layers */
+		fsm_sconfreq(f, 0);		/* Send initial Configure-Request */
+		f->state = REQSENT;
+		break;
+	}
+}
+
+
+/*
+ * fsm_rconfnakrej - Receive Configure-Nak or Configure-Reject.
+ */
+static void fsm_rconfnakrej(fsm *f, int code, int id, u_char *inp, int len)
+{
+	int (*proc) (fsm *, u_char *, int);
+	int ret;
+	
+	FSMDEBUG((LOG_INFO, "fsm_rconfnakrej(%s): Rcvd id %d state=%d\n",
+				PROTO_NAME(f), id, f->state));
+	
+	if (id != f->reqid || f->seen_ack)	/* Expected id? */
+		return;				/* Nope, toss... */
+	proc = (code == CONFNAK)? f->callbacks->nakci: f->callbacks->rejci;
+	if (!proc || !(ret = proc(f, inp, len))) {
+		/* Nak/reject is bad - ignore it */
+		FSMDEBUG((LOG_INFO, "%s: received bad %s (length %d)\n",
+					PROTO_NAME(f), (code==CONFNAK? "Nak": "reject"), len));
+		return;
+	}
+	f->seen_ack = 1;
+	
+	switch (f->state) {
+	case CLOSED:
+	case STOPPED:
+		fsm_sdata(f, TERMACK, (u_char)id, NULL, 0);
+		break;
+	
+	case REQSENT:
+	case ACKSENT:
+		/* They didn't agree to what we wanted - try another request */
+		UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+		if (ret < 0)
+			f->state = STOPPED;		/* kludge for stopping CCP */
+		else
+			fsm_sconfreq(f, 0);		/* Send Configure-Request */
+		break;
+	
+	case ACKRCVD:
+		/* Got a Nak/reject when we had already had an Ack?? oh well... */
+		UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+		fsm_sconfreq(f, 0);
+		f->state = REQSENT;
+		break;
+	
+	case OPENED:
+		/* Go down and restart negotiation */
+		if (f->callbacks->down)
+			(*f->callbacks->down)(f);	/* Inform upper layers */
+		fsm_sconfreq(f, 0);		/* Send initial Configure-Request */
+		f->state = REQSENT;
+		break;
+	}
+}
+
+
+/*
+ * fsm_rtermreq - Receive Terminate-Req.
+ */
+static void fsm_rtermreq(fsm *f, int id, u_char *p, int len)
+{
+	FSMDEBUG((LOG_INFO, "fsm_rtermreq(%s): Rcvd id %d state=%d\n",
+				PROTO_NAME(f), id, f->state));
+	
+	switch (f->state) {
+	case ACKRCVD:
+	case ACKSENT:
+		f->state = REQSENT;		/* Start over but keep trying */
+		break;
+	
+	case OPENED:
+		if (len > 0) {
+			FSMDEBUG((LOG_INFO, "%s terminated by peer (%x)\n", PROTO_NAME(f), p));
+		} else {
+			FSMDEBUG((LOG_INFO, "%s terminated by peer\n", PROTO_NAME(f)));
+		}
+		if (f->callbacks->down)
+			(*f->callbacks->down)(f);	/* Inform upper layers */
+		f->retransmits = 0;
+		f->state = STOPPING;
+		TIMEOUT(fsm_timeout, f, f->timeouttime);
+		break;
+	}
+	
+	fsm_sdata(f, TERMACK, (u_char)id, NULL, 0);
+}
+
+
+/*
+ * fsm_rtermack - Receive Terminate-Ack.
+ */
+static void fsm_rtermack(fsm *f)
+{
+	FSMDEBUG((LOG_INFO, "fsm_rtermack(%s): state=%d\n", 
+				PROTO_NAME(f), f->state));
+	
+	switch (f->state) {
+	case CLOSING:
+		UNTIMEOUT(fsm_timeout, f);
+		f->state = CLOSED;
+		if( f->callbacks->finished )
+			(*f->callbacks->finished)(f);
+		break;
+	case STOPPING:
+		UNTIMEOUT(fsm_timeout, f);
+		f->state = STOPPED;
+		if( f->callbacks->finished )
+			(*f->callbacks->finished)(f);
+		break;
+	
+	case ACKRCVD:
+		f->state = REQSENT;
+		break;
+	
+	case OPENED:
+		if (f->callbacks->down)
+			(*f->callbacks->down)(f);	/* Inform upper layers */
+		fsm_sconfreq(f, 0);
+		break;
+	}
+}
+
+
+/*
+ * fsm_rcoderej - Receive an Code-Reject.
+ */
+static void fsm_rcoderej(fsm *f, u_char *inp, int len)
+{
+	u_char code, id;
+	
+	FSMDEBUG((LOG_INFO, "fsm_rcoderej(%s): state=%d\n", 
+				PROTO_NAME(f), f->state));
+	
+	if (len < HEADERLEN) {
+		FSMDEBUG((LOG_INFO, "fsm_rcoderej: Rcvd short Code-Reject packet!\n"));
+		return;
+	}
+	GETCHAR(code, inp);
+	GETCHAR(id, inp);
+	FSMDEBUG((LOG_WARNING, "%s: Rcvd Code-Reject for code %d, id %d\n",
+				PROTO_NAME(f), code, id));
+	
+	if( f->state == ACKRCVD )
+		f->state = REQSENT;
+}
+
+
+/*
+ * fsm_sconfreq - Send a Configure-Request.
+ */
+static void fsm_sconfreq(fsm *f, int retransmit)
+{
+	u_char *outp;
+	int cilen;
+	
+	if( f->state != REQSENT && f->state != ACKRCVD && f->state != ACKSENT ){
+		/* Not currently negotiating - reset options */
+		if( f->callbacks->resetci )
+			(*f->callbacks->resetci)(f);
+		f->nakloops = 0;
+		}
+	
+	if( !retransmit ){
+		/* New request - reset retransmission counter, use new ID */
+		f->retransmits = f->maxconfreqtransmits;
+		f->reqid = ++f->id;
+	}
+	
+	f->seen_ack = 0;
+	
+	/*
+	 * Make up the request packet
+	 */
+	outp = outpacket_buf[f->unit] + PPP_HDRLEN + HEADERLEN;
+	if( f->callbacks->cilen && f->callbacks->addci ){
+		cilen = (*f->callbacks->cilen)(f);
+		if( cilen > peer_mru[f->unit] - (int)HEADERLEN )
+			cilen = peer_mru[f->unit] - HEADERLEN;
+		if (f->callbacks->addci)
+			(*f->callbacks->addci)(f, outp, &cilen);
+	} else
+		cilen = 0;
+	
+	/* send the request to our peer */
+	fsm_sdata(f, CONFREQ, f->reqid, outp, cilen);
+	
+	/* start the retransmit timer */
+	--f->retransmits;
+	TIMEOUT(fsm_timeout, f, f->timeouttime);
+	
+	FSMDEBUG((LOG_INFO, "%s: sending Configure-Request, id %d\n",
+				PROTO_NAME(f), f->reqid));
+}
+
+#endif /* PPP_SUPPORT */
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/fsm.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/fsm.h
new file mode 100644
index 000000000..4cca402e0
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/fsm.h
@@ -0,0 +1,187 @@
+/*****************************************************************************
+* fsm.h - Network Control Protocol Finite State Machine header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-11-05 Guy Lancaster , Global Election Systems Inc.
+*	Original based on BSD code.
+*****************************************************************************/
+/*
+ * fsm.h - {Link, IP} Control Protocol Finite State Machine definitions.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * $Id: fsm.h,v 1.1 2003/05/27 14:37:56 jani Exp $
+ */
+
+#ifndef FSM_H
+#define FSM_H
+
+
+/*****************************************************************************
+************************* PUBLIC DEFINITIONS *********************************
+*****************************************************************************/
+/*
+ * LCP Packet header = Code, id, length.
+ */
+#define HEADERLEN	(sizeof (u_char) + sizeof (u_char) + sizeof (u_short))
+
+
+/*
+ *  CP (LCP, IPCP, etc.) codes.
+ */
+#define CONFREQ		1		/* Configuration Request */
+#define CONFACK		2		/* Configuration Ack */
+#define CONFNAK		3		/* Configuration Nak */
+#define CONFREJ		4		/* Configuration Reject */
+#define TERMREQ		5		/* Termination Request */
+#define TERMACK		6		/* Termination Ack */
+#define CODEREJ		7		/* Code Reject */
+
+/*
+ * Link states.
+ */
+#define INITIAL		0		/* Down, hasn't been opened */
+#define STARTING	1		/* Down, been opened */
+#define CLOSED		2		/* Up, hasn't been opened */
+#define STOPPED		3		/* Open, waiting for down event */
+#define CLOSING		4		/* Terminating the connection, not open */
+#define STOPPING	5		/* Terminating, but open */
+#define REQSENT		6		/* We've sent a Config Request */
+#define ACKRCVD		7		/* We've received a Config Ack */
+#define ACKSENT		8		/* We've sent a Config Ack */
+#define OPENED		9		/* Connection available */
+
+
+/*
+ * Flags - indicate options controlling FSM operation
+ */
+#define OPT_PASSIVE	1		/* Don't die if we don't get a response */
+#define OPT_RESTART	2		/* Treat 2nd OPEN as DOWN, UP */
+#define OPT_SILENT	4		/* Wait for peer to speak first */
+
+
+/*****************************************************************************
+************************* PUBLIC DATA TYPES **********************************
+*****************************************************************************/
+/*
+ * Each FSM is described by an fsm structure and fsm callbacks.
+ */
+typedef struct fsm {
+    int unit;				/* Interface unit number */
+    u_short protocol;		/* Data Link Layer Protocol field value */
+    int state;				/* State */
+    int flags;				/* Contains option bits */
+    u_char id;				/* Current id */
+    u_char reqid;			/* Current request id */
+    u_char seen_ack;		/* Have received valid Ack/Nak/Rej to Req */
+    int timeouttime;		/* Timeout time in milliseconds */
+    int maxconfreqtransmits;/* Maximum Configure-Request transmissions */
+    int retransmits;		/* Number of retransmissions left */
+    int maxtermtransmits;	/* Maximum Terminate-Request transmissions */
+    int nakloops;			/* Number of nak loops since last ack */
+    int maxnakloops;		/* Maximum number of nak loops tolerated */
+    struct fsm_callbacks* callbacks;/* Callback routines */
+    char* term_reason;		/* Reason for closing protocol */
+    int term_reason_len;	/* Length of term_reason */
+} fsm;
+
+
+typedef struct fsm_callbacks {
+    void (*resetci)			/* Reset our Configuration Information */
+		(fsm*);
+    int  (*cilen)			/* Length of our Configuration Information */
+		(fsm*);
+    void (*addci) 			/* Add our Configuration Information */
+		(fsm*, u_char*, int*);
+    int  (*ackci)			/* ACK our Configuration Information */
+		(fsm*, u_char*, int);
+    int  (*nakci)			/* NAK our Configuration Information */
+		(fsm*, u_char*, int);
+    int  (*rejci)			/* Reject our Configuration Information */
+		(fsm*, u_char*, int);
+    int  (*reqci)			/* Request peer's Configuration Information */
+		(fsm*, u_char*, int*, int);
+    void (*up)				/* Called when fsm reaches OPENED state */
+		(fsm*);
+    void (*down)			/* Called when fsm leaves OPENED state */
+		(fsm*);
+    void (*starting)		/* Called when we want the lower layer */
+		(fsm*);
+    void (*finished)		/* Called when we don't want the lower layer */
+		(fsm*);
+    void (*protreject)		/* Called when Protocol-Reject received */
+		(int);
+    void (*retransmit)		/* Retransmission is necessary */
+		(fsm*);
+    int  (*extcode)			/* Called when unknown code received */
+		(fsm*, int, u_char, u_char*, int);
+    char *proto_name;		/* String name for protocol (for messages) */
+} fsm_callbacks;
+
+
+/*****************************************************************************
+*********************** PUBLIC DATA STRUCTURES *******************************
+*****************************************************************************/
+/*
+ * Variables
+ */
+extern int peer_mru[];		/* currently negotiated peer MRU (per unit) */
+
+
+/*****************************************************************************
+************************** PUBLIC FUNCTIONS **********************************
+*****************************************************************************/
+
+/*
+ * Prototypes
+ */
+void fsm_init (fsm*);
+void fsm_lowerup (fsm*);
+void fsm_lowerdown (fsm*);
+void fsm_open (fsm*);
+void fsm_close (fsm*, char*);
+void fsm_input (fsm*, u_char*, int);
+void fsm_protreject (fsm*);
+void fsm_sdata (fsm*, u_char, u_char, u_char*, int);
+
+
+#endif /* FSM_H */
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/ipcp.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/ipcp.c
new file mode 100644
index 000000000..ec3207a0c
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/ipcp.c
@@ -0,0 +1,1377 @@
+/*****************************************************************************
+* ipcp.c - Network PPP IP Control Protocol program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-08 Guy Lancaster , Global Election Systems Inc.
+*	Original.
+*****************************************************************************/
+/*
+ * ipcp.c - PPP IP Control Protocol.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include 
+
+#include "ppp.h"
+#if PPP_SUPPORT > 0
+#include "auth.h"
+#include "fsm.h"
+#include "vj.h"
+#include "ipcp.h"
+#include "pppdebug.h"
+
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+/* #define OLD_CI_ADDRS 1 */	/* Support deprecated address negotiation. */
+
+/*
+ * Lengths of configuration options.
+ */
+#define CILEN_VOID	2
+#define CILEN_COMPRESS	4	/* min length for compression protocol opt. */
+#define CILEN_VJ	6	/* length for RFC1332 Van-Jacobson opt. */
+#define CILEN_ADDR	6	/* new-style single address option */
+#define CILEN_ADDRS	10	/* old-style dual address option */
+
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+/*
+ * Callbacks for fsm code.  (CI = Configuration Information)
+ */
+static void ipcp_resetci (fsm *);	/* Reset our CI */
+static int  ipcp_cilen (fsm *);	        /* Return length of our CI */
+static void ipcp_addci (fsm *, u_char *, int *); /* Add our CI */
+static int  ipcp_ackci (fsm *, u_char *, int);	/* Peer ack'd our CI */
+static int  ipcp_nakci (fsm *, u_char *, int);	/* Peer nak'd our CI */
+static int  ipcp_rejci (fsm *, u_char *, int);	/* Peer rej'd our CI */
+static int  ipcp_reqci (fsm *, u_char *, int *, int); /* Rcv CI */
+static void ipcp_up (fsm *);		/* We're UP */
+static void ipcp_down (fsm *);		/* We're DOWN */
+#if 0
+static void ipcp_script (fsm *, char *); /* Run an up/down script */
+#endif
+static void ipcp_finished (fsm *);	/* Don't need lower layer */
+
+/*
+ * Protocol entry points from main code.
+ */
+static void ipcp_init (int);
+static void ipcp_open (int);
+static void ipcp_close (int, char *);
+static void ipcp_lowerup (int);
+static void ipcp_lowerdown (int);
+static void ipcp_input (int, u_char *, int);
+static void ipcp_protrej (int);
+
+static void ipcp_clear_addrs (int);
+
+#define CODENAME(x)	((x) == CONFACK ? "ACK" : \
+			 (x) == CONFNAK ? "NAK" : "REJ")
+
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+/* global vars */
+ipcp_options ipcp_wantoptions[NUM_PPP];	/* Options that we want to request */
+ipcp_options ipcp_gotoptions[NUM_PPP];	/* Options that peer ack'd */
+ipcp_options ipcp_allowoptions[NUM_PPP];	/* Options we allow peer to request */
+ipcp_options ipcp_hisoptions[NUM_PPP];	/* Options that we ack'd */
+
+fsm ipcp_fsm[NUM_PPP];		/* IPCP fsm structure */
+
+struct protent ipcp_protent = {
+    PPP_IPCP,
+    ipcp_init,
+    ipcp_input,
+    ipcp_protrej,
+    ipcp_lowerup,
+    ipcp_lowerdown,
+    ipcp_open,
+    ipcp_close,
+#if 0
+    ipcp_printpkt,
+    NULL,
+#endif
+    1,
+    "IPCP",
+#if 0
+    ip_check_options,
+    NULL,
+    ip_active_pkt
+#endif
+};
+
+
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+/* local vars */
+static int cis_received[NUM_PPP];		/* # Conf-Reqs received */
+static int default_route_set[NUM_PPP];	/* Have set up a default route */
+
+static fsm_callbacks ipcp_callbacks = { /* IPCP callback routines */
+    ipcp_resetci,		/* Reset our Configuration Information */
+    ipcp_cilen,			/* Length of our Configuration Information */
+    ipcp_addci,			/* Add our Configuration Information */
+    ipcp_ackci,			/* ACK our Configuration Information */
+    ipcp_nakci,			/* NAK our Configuration Information */
+    ipcp_rejci,			/* Reject our Configuration Information */
+    ipcp_reqci,			/* Request peer's Configuration Information */
+    ipcp_up,			/* Called when fsm reaches OPENED state */
+    ipcp_down,			/* Called when fsm leaves OPENED state */
+    NULL,				/* Called when we want the lower layer up */
+    ipcp_finished,		/* Called when we want the lower layer down */
+    NULL,				/* Called when Protocol-Reject received */
+    NULL,				/* Retransmission is necessary */
+    NULL,				/* Called to handle protocol-specific codes */
+    "IPCP"				/* String name of protocol */
+};
+
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+
+/*
+ * Non-standard inet_ntoa left here for compat with original ppp
+ * sources. Assumes u32_t instead of struct in_addr.
+ */ 
+
+char * _inet_ntoa(u32_t n)
+{
+	struct in_addr ia;
+	ia.s_addr = n;
+	return inet_ntoa(ia);
+}
+
+#define inet_ntoa _inet_ntoa
+
+/*
+ * ipcp_init - Initialize IPCP.
+ */
+static void ipcp_init(int unit)
+{
+	fsm *f = &ipcp_fsm[unit];
+	ipcp_options *wo = &ipcp_wantoptions[unit];
+	ipcp_options *ao = &ipcp_allowoptions[unit];
+	
+	f->unit = unit;
+	f->protocol = PPP_IPCP;
+	f->callbacks = &ipcp_callbacks;
+	fsm_init(&ipcp_fsm[unit]);
+	
+	memset(wo, 0, sizeof(*wo));
+	memset(ao, 0, sizeof(*ao));
+	
+	wo->neg_addr = 1;
+	wo->ouraddr = 0;
+#if VJ_SUPPORT > 0
+	wo->neg_vj = 1;
+#else
+	wo->neg_vj = 0;
+#endif
+	wo->vj_protocol = IPCP_VJ_COMP;
+	wo->maxslotindex = MAX_SLOTS - 1;
+	wo->cflag = 0;
+	
+	wo->default_route = 1;
+	
+	ao->neg_addr = 1;
+#if VJ_SUPPORT > 0
+	ao->neg_vj = 1;
+#else
+	ao->neg_vj = 0;
+#endif
+	ao->maxslotindex = MAX_SLOTS - 1;
+	ao->cflag = 1;
+	
+	ao->default_route = 1;
+}
+
+
+/*
+ * ipcp_open - IPCP is allowed to come up.
+ */
+static void ipcp_open(int unit)
+{
+	fsm_open(&ipcp_fsm[unit]);
+}
+
+
+/*
+ * ipcp_close - Take IPCP down.
+ */
+static void ipcp_close(int unit, char *reason)
+{
+	fsm_close(&ipcp_fsm[unit], reason);
+}
+
+
+/*
+ * ipcp_lowerup - The lower layer is up.
+ */
+static void ipcp_lowerup(int unit)
+{
+	fsm_lowerup(&ipcp_fsm[unit]);
+}
+
+
+/*
+ * ipcp_lowerdown - The lower layer is down.
+ */
+static void ipcp_lowerdown(int unit)
+{
+	fsm_lowerdown(&ipcp_fsm[unit]);
+}
+
+
+/*
+ * ipcp_input - Input IPCP packet.
+ */
+static void ipcp_input(int unit, u_char *p, int len)
+{
+	fsm_input(&ipcp_fsm[unit], p, len);
+}
+
+
+/*
+ * ipcp_protrej - A Protocol-Reject was received for IPCP.
+ *
+ * Pretend the lower layer went down, so we shut up.
+ */
+static void ipcp_protrej(int unit)
+{
+	fsm_lowerdown(&ipcp_fsm[unit]);
+}
+
+
+/*
+ * ipcp_resetci - Reset our CI.
+ */
+static void ipcp_resetci(fsm *f)
+{
+	ipcp_options *wo = &ipcp_wantoptions[f->unit];
+	
+	wo->req_addr = wo->neg_addr && ipcp_allowoptions[f->unit].neg_addr;
+	if (wo->ouraddr == 0)
+		wo->accept_local = 1;
+	if (wo->hisaddr == 0)
+		wo->accept_remote = 1;
+	/* Request DNS addresses from the peer */
+	wo->req_dns1 = ppp_settings.usepeerdns;
+	wo->req_dns2 = ppp_settings.usepeerdns;
+	ipcp_gotoptions[f->unit] = *wo;
+	cis_received[f->unit] = 0;
+}
+
+
+/*
+ * ipcp_cilen - Return length of our CI.
+ */
+static int ipcp_cilen(fsm *f)
+{
+	ipcp_options *go = &ipcp_gotoptions[f->unit];
+	ipcp_options *wo = &ipcp_wantoptions[f->unit];
+	ipcp_options *ho = &ipcp_hisoptions[f->unit];
+	
+#define LENCIVJ(neg, old)	(neg ? (old? CILEN_COMPRESS : CILEN_VJ) : 0)
+#define LENCIADDR(neg, old)	(neg ? (old? CILEN_ADDRS : CILEN_ADDR) : 0)
+#define LENCIDNS(neg)		(neg ? (CILEN_ADDR) : 0)
+	
+	/*
+	 * First see if we want to change our options to the old
+	 * forms because we have received old forms from the peer.
+	 */
+	if (wo->neg_addr && !go->neg_addr && !go->old_addrs) {
+		/* use the old style of address negotiation */
+		go->neg_addr = 1;
+		go->old_addrs = 1;
+	}
+	if (wo->neg_vj && !go->neg_vj && !go->old_vj) {
+		/* try an older style of VJ negotiation */
+		if (cis_received[f->unit] == 0) {
+			/* keep trying the new style until we see some CI from the peer */
+			go->neg_vj = 1;
+		} else {
+			/* use the old style only if the peer did */
+			if (ho->neg_vj && ho->old_vj) {
+				go->neg_vj = 1;
+				go->old_vj = 1;
+				go->vj_protocol = ho->vj_protocol;
+			}
+		}
+	}
+	
+	return (LENCIADDR(go->neg_addr, go->old_addrs)
+			+ LENCIVJ(go->neg_vj, go->old_vj) +
+			LENCIDNS(go->req_dns1) +
+			LENCIDNS(go->req_dns2));
+}
+
+
+/*
+ * ipcp_addci - Add our desired CIs to a packet.
+ */
+static void ipcp_addci(fsm *f, u_char *ucp, int *lenp)
+{
+	ipcp_options *go = &ipcp_gotoptions[f->unit];
+	int len = *lenp;
+	
+#define ADDCIVJ(opt, neg, val, old, maxslotindex, cflag) \
+	if (neg) { \
+		int vjlen = old? CILEN_COMPRESS : CILEN_VJ; \
+		if (len >= vjlen) { \
+			PUTCHAR(opt, ucp); \
+			PUTCHAR(vjlen, ucp); \
+			PUTSHORT(val, ucp); \
+			if (!old) { \
+				PUTCHAR(maxslotindex, ucp); \
+				PUTCHAR(cflag, ucp); \
+			} \
+			len -= vjlen; \
+		} else \
+			neg = 0; \
+	}
+	
+#define ADDCIADDR(opt, neg, old, val1, val2) \
+	if (neg) { \
+		int addrlen = (old? CILEN_ADDRS: CILEN_ADDR); \
+		if (len >= addrlen) { \
+			u32_t l; \
+			PUTCHAR(opt, ucp); \
+			PUTCHAR(addrlen, ucp); \
+			l = ntohl(val1); \
+			PUTLONG(l, ucp); \
+			if (old) { \
+				l = ntohl(val2); \
+				PUTLONG(l, ucp); \
+			} \
+			len -= addrlen; \
+		} else \
+			neg = 0; \
+	}
+
+#define ADDCIDNS(opt, neg, addr) \
+	if (neg) { \
+		if (len >= CILEN_ADDR) { \
+			u32_t l; \
+			PUTCHAR(opt, ucp); \
+			PUTCHAR(CILEN_ADDR, ucp); \
+			l = ntohl(addr); \
+			PUTLONG(l, ucp); \
+			len -= CILEN_ADDR; \
+		} else \
+			neg = 0; \
+	}
+	
+	ADDCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), go->neg_addr,
+			  go->old_addrs, go->ouraddr, go->hisaddr);
+	
+	ADDCIVJ(CI_COMPRESSTYPE, go->neg_vj, go->vj_protocol, go->old_vj,
+			go->maxslotindex, go->cflag);
+	
+	ADDCIDNS(CI_MS_DNS1, go->req_dns1, go->dnsaddr[0]);
+
+	ADDCIDNS(CI_MS_DNS2, go->req_dns2, go->dnsaddr[1]);
+
+	*lenp -= len;
+}
+
+
+/*
+ * ipcp_ackci - Ack our CIs.
+ *
+ * Returns:
+ *	0 - Ack was bad.
+ *	1 - Ack was good.
+ */
+static int ipcp_ackci(fsm *f, u_char *p, int len)
+{
+	ipcp_options *go = &ipcp_gotoptions[f->unit];
+	u_short cilen, citype, cishort;
+	u32_t cilong;
+	u_char cimaxslotindex, cicflag;
+	
+	/*
+	 * CIs must be in exactly the same order that we sent...
+	 * Check packet length and CI length at each step.
+	 * If we find any deviations, then this packet is bad.
+	 */
+	
+#define ACKCIVJ(opt, neg, val, old, maxslotindex, cflag) \
+	if (neg) { \
+		int vjlen = old? CILEN_COMPRESS : CILEN_VJ; \
+		if ((len -= vjlen) < 0) \
+			goto bad; \
+		GETCHAR(citype, p); \
+		GETCHAR(cilen, p); \
+		if (cilen != vjlen || \
+				citype != opt)  \
+			goto bad; \
+		GETSHORT(cishort, p); \
+		if (cishort != val) \
+			goto bad; \
+		if (!old) { \
+			GETCHAR(cimaxslotindex, p); \
+			if (cimaxslotindex != maxslotindex) \
+				goto bad; \
+			GETCHAR(cicflag, p); \
+			if (cicflag != cflag) \
+				goto bad; \
+		} \
+	}
+	
+#define ACKCIADDR(opt, neg, old, val1, val2) \
+	if (neg) { \
+		int addrlen = (old? CILEN_ADDRS: CILEN_ADDR); \
+		u32_t l; \
+		if ((len -= addrlen) < 0) \
+			goto bad; \
+		GETCHAR(citype, p); \
+		GETCHAR(cilen, p); \
+		if (cilen != addrlen || \
+				citype != opt) \
+			goto bad; \
+		GETLONG(l, p); \
+		cilong = htonl(l); \
+		if (val1 != cilong) \
+			goto bad; \
+		if (old) { \
+			GETLONG(l, p); \
+			cilong = htonl(l); \
+			if (val2 != cilong) \
+				goto bad; \
+		} \
+	}
+
+#define ACKCIDNS(opt, neg, addr) \
+	if (neg) { \
+		u32_t l; \
+		if ((len -= CILEN_ADDR) < 0) \
+			goto bad; \
+		GETCHAR(citype, p); \
+		GETCHAR(cilen, p); \
+		if (cilen != CILEN_ADDR || \
+				citype != opt) \
+			goto bad; \
+		GETLONG(l, p); \
+		cilong = htonl(l); \
+		if (addr != cilong) \
+			goto bad; \
+	}
+	
+	ACKCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), go->neg_addr,
+			  go->old_addrs, go->ouraddr, go->hisaddr);
+	
+	ACKCIVJ(CI_COMPRESSTYPE, go->neg_vj, go->vj_protocol, go->old_vj,
+			go->maxslotindex, go->cflag);
+	
+	ACKCIDNS(CI_MS_DNS1, go->req_dns1, go->dnsaddr[0]);
+
+	ACKCIDNS(CI_MS_DNS2, go->req_dns2, go->dnsaddr[1]);
+
+	/*
+	 * If there are any remaining CIs, then this packet is bad.
+	 */
+	if (len != 0)
+		goto bad;
+	return (1);
+	
+bad:
+	IPCPDEBUG((LOG_INFO, "ipcp_ackci: received bad Ack!\n"));
+	return (0);
+}
+
+/*
+ * ipcp_nakci - Peer has sent a NAK for some of our CIs.
+ * This should not modify any state if the Nak is bad
+ * or if IPCP is in the OPENED state.
+ *
+ * Returns:
+ *	0 - Nak was bad.
+ *	1 - Nak was good.
+ */
+static int ipcp_nakci(fsm *f, u_char *p, int len)
+{
+	ipcp_options *go = &ipcp_gotoptions[f->unit];
+	u_char cimaxslotindex, cicflag;
+	u_char citype, cilen, *next;
+	u_short cishort;
+	u32_t ciaddr1, ciaddr2, l, cidnsaddr;
+	ipcp_options no;		/* options we've seen Naks for */
+	ipcp_options try;		/* options to request next time */
+	
+	BZERO(&no, sizeof(no));
+	try = *go;
+	
+	/*
+	 * Any Nak'd CIs must be in exactly the same order that we sent.
+	 * Check packet length and CI length at each step.
+	 * If we find any deviations, then this packet is bad.
+	 */
+#define NAKCIADDR(opt, neg, old, code) \
+	if (go->neg && \
+			len >= (cilen = (old? CILEN_ADDRS: CILEN_ADDR)) && \
+			p[1] == cilen && \
+			p[0] == opt) { \
+		len -= cilen; \
+		INCPTR(2, p); \
+		GETLONG(l, p); \
+		ciaddr1 = htonl(l); \
+		if (old) { \
+			GETLONG(l, p); \
+			ciaddr2 = htonl(l); \
+			no.old_addrs = 1; \
+		} else \
+			ciaddr2 = 0; \
+		no.neg = 1; \
+		code \
+	}
+	
+#define NAKCIVJ(opt, neg, code) \
+	if (go->neg && \
+			((cilen = p[1]) == CILEN_COMPRESS || cilen == CILEN_VJ) && \
+			len >= cilen && \
+			p[0] == opt) { \
+		len -= cilen; \
+		INCPTR(2, p); \
+		GETSHORT(cishort, p); \
+		no.neg = 1; \
+		code \
+	}
+	
+#define NAKCIDNS(opt, neg, code) \
+	if (go->neg && \
+			((cilen = p[1]) == CILEN_ADDR) && \
+			len >= cilen && \
+			p[0] == opt) { \
+		len -= cilen; \
+		INCPTR(2, p); \
+		GETLONG(l, p); \
+		cidnsaddr = htonl(l); \
+		no.neg = 1; \
+		code \
+	}
+	
+	/*
+	 * Accept the peer's idea of {our,his} address, if different
+	 * from our idea, only if the accept_{local,remote} flag is set.
+	 */
+	NAKCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), neg_addr, go->old_addrs,
+	  if (go->accept_local && ciaddr1) { /* Do we know our address? */
+		  try.ouraddr = ciaddr1;
+		  IPCPDEBUG((LOG_INFO, "local IP address %s\n",
+			     inet_ntoa(ciaddr1)));
+	  }
+	  if (go->accept_remote && ciaddr2) { /* Does he know his? */
+		  try.hisaddr = ciaddr2;
+		  IPCPDEBUG((LOG_INFO, "remote IP address %s\n",
+			     inet_ntoa(ciaddr2)));
+	  }
+	);
+	
+	/*
+	 * Accept the peer's value of maxslotindex provided that it
+	 * is less than what we asked for.  Turn off slot-ID compression
+	 * if the peer wants.  Send old-style compress-type option if
+	 * the peer wants.
+	 */
+	NAKCIVJ(CI_COMPRESSTYPE, neg_vj,
+		if (cilen == CILEN_VJ) {
+			GETCHAR(cimaxslotindex, p);
+			GETCHAR(cicflag, p);
+			if (cishort == IPCP_VJ_COMP) {
+				try.old_vj = 0;
+				if (cimaxslotindex < go->maxslotindex)
+					try.maxslotindex = cimaxslotindex;
+				if (!cicflag)
+					try.cflag = 0;
+			} else {
+				try.neg_vj = 0;
+			}
+		} else {
+			if (cishort == IPCP_VJ_COMP || cishort == IPCP_VJ_COMP_OLD) {
+				try.old_vj = 1;
+				try.vj_protocol = cishort;
+			} else {
+				try.neg_vj = 0;
+			}
+		}
+	);
+	
+	NAKCIDNS(CI_MS_DNS1, req_dns1,
+			try.dnsaddr[0] = cidnsaddr;
+		  	IPCPDEBUG((LOG_INFO, "primary DNS address %s\n", inet_ntoa(cidnsaddr)));
+			);
+
+	NAKCIDNS(CI_MS_DNS2, req_dns2,
+			try.dnsaddr[1] = cidnsaddr;
+		  	IPCPDEBUG((LOG_INFO, "secondary DNS address %s\n", inet_ntoa(cidnsaddr)));
+			);
+
+	/*
+	* There may be remaining CIs, if the peer is requesting negotiation
+	* on an option that we didn't include in our request packet.
+	* If they want to negotiate about IP addresses, we comply.
+	* If they want us to ask for compression, we refuse.
+	*/
+	while (len > CILEN_VOID) {
+		GETCHAR(citype, p);
+		GETCHAR(cilen, p);
+		if( (len -= cilen) < 0 )
+			goto bad;
+		next = p + cilen - 2;
+		
+		switch (citype) {
+		case CI_COMPRESSTYPE:
+			if (go->neg_vj || no.neg_vj ||
+					(cilen != CILEN_VJ && cilen != CILEN_COMPRESS))
+				goto bad;
+			no.neg_vj = 1;
+			break;
+		case CI_ADDRS:
+			if ((go->neg_addr && go->old_addrs) || no.old_addrs
+					|| cilen != CILEN_ADDRS)
+				goto bad;
+			try.neg_addr = 1;
+			try.old_addrs = 1;
+			GETLONG(l, p);
+			ciaddr1 = htonl(l);
+			if (ciaddr1 && go->accept_local)
+				try.ouraddr = ciaddr1;
+			GETLONG(l, p);
+			ciaddr2 = htonl(l);
+			if (ciaddr2 && go->accept_remote)
+				try.hisaddr = ciaddr2;
+			no.old_addrs = 1;
+			break;
+		case CI_ADDR:
+			if (go->neg_addr || no.neg_addr || cilen != CILEN_ADDR)
+				goto bad;
+			try.old_addrs = 0;
+			GETLONG(l, p);
+			ciaddr1 = htonl(l);
+			if (ciaddr1 && go->accept_local)
+				try.ouraddr = ciaddr1;
+			if (try.ouraddr != 0)
+				try.neg_addr = 1;
+			no.neg_addr = 1;
+			break;
+		}
+		p = next;
+	}
+	
+	/* If there is still anything left, this packet is bad. */
+	if (len != 0)
+		goto bad;
+	
+	/*
+	 * OK, the Nak is good.  Now we can update state.
+	 */
+	if (f->state != OPENED)
+		*go = try;
+	
+	return 1;
+	
+bad:
+	IPCPDEBUG((LOG_INFO, "ipcp_nakci: received bad Nak!\n"));
+	return 0;
+}
+
+
+/*
+ * ipcp_rejci - Reject some of our CIs.
+ */
+static int ipcp_rejci(fsm *f, u_char *p, int len)
+{
+	ipcp_options *go = &ipcp_gotoptions[f->unit];
+	u_char cimaxslotindex, ciflag, cilen;
+	u_short cishort;
+	u32_t cilong;
+	ipcp_options try;		/* options to request next time */
+	
+	try = *go;
+	/*
+	 * Any Rejected CIs must be in exactly the same order that we sent.
+	 * Check packet length and CI length at each step.
+	 * If we find any deviations, then this packet is bad.
+	 */
+#define REJCIADDR(opt, neg, old, val1, val2) \
+	if (go->neg && \
+			len >= (cilen = old? CILEN_ADDRS: CILEN_ADDR) && \
+			p[1] == cilen && \
+			p[0] == opt) { \
+		u32_t l; \
+		len -= cilen; \
+		INCPTR(2, p); \
+		GETLONG(l, p); \
+		cilong = htonl(l); \
+		/* Check rejected value. */ \
+		if (cilong != val1) \
+			goto bad; \
+		if (old) { \
+			GETLONG(l, p); \
+			cilong = htonl(l); \
+			/* Check rejected value. */ \
+			if (cilong != val2) \
+				goto bad; \
+		} \
+		try.neg = 0; \
+	}
+	
+#define REJCIVJ(opt, neg, val, old, maxslot, cflag) \
+	if (go->neg && \
+			p[1] == (old? CILEN_COMPRESS : CILEN_VJ) && \
+			len >= p[1] && \
+			p[0] == opt) { \
+		len -= p[1]; \
+		INCPTR(2, p); \
+		GETSHORT(cishort, p); \
+		/* Check rejected value. */  \
+		if (cishort != val) \
+			goto bad; \
+		if (!old) { \
+			GETCHAR(cimaxslotindex, p); \
+			if (cimaxslotindex != maxslot) \
+				goto bad; \
+			GETCHAR(ciflag, p); \
+			if (ciflag != cflag) \
+				goto bad; \
+		} \
+		try.neg = 0; \
+	}
+	
+#define REJCIDNS(opt, neg, dnsaddr) \
+	if (go->neg && \
+			((cilen = p[1]) == CILEN_ADDR) && \
+			len >= cilen && \
+			p[0] == opt) { \
+		u32_t l; \
+		len -= cilen; \
+		INCPTR(2, p); \
+		GETLONG(l, p); \
+		cilong = htonl(l); \
+		/* Check rejected value. */ \
+		if (cilong != dnsaddr) \
+			goto bad; \
+		try.neg = 0; \
+	}
+
+	REJCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), neg_addr,
+			  go->old_addrs, go->ouraddr, go->hisaddr);
+	
+	REJCIVJ(CI_COMPRESSTYPE, neg_vj, go->vj_protocol, go->old_vj,
+			go->maxslotindex, go->cflag);
+	
+	REJCIDNS(CI_MS_DNS1, req_dns1, go->dnsaddr[0]);
+
+	REJCIDNS(CI_MS_DNS2, req_dns2, go->dnsaddr[1]);
+
+	/*
+	 * If there are any remaining CIs, then this packet is bad.
+	 */
+	if (len != 0)
+		goto bad;
+	/*
+	 * Now we can update state.
+	 */
+	if (f->state != OPENED)
+		*go = try;
+	return 1;
+	
+bad:
+	IPCPDEBUG((LOG_INFO, "ipcp_rejci: received bad Reject!\n"));
+	return 0;
+}
+
+
+/*
+ * ipcp_reqci - Check the peer's requested CIs and send appropriate response.
+ *
+ * Returns: CONFACK, CONFNAK or CONFREJ and input packet modified
+ * appropriately.  If reject_if_disagree is non-zero, doesn't return
+ * CONFNAK; returns CONFREJ if it can't return CONFACK.
+ */
+static int ipcp_reqci(
+	fsm *f,
+	u_char *inp,		/* Requested CIs */
+	int *len,			/* Length of requested CIs */
+	int reject_if_disagree
+)
+{
+	ipcp_options *wo = &ipcp_wantoptions[f->unit];
+	ipcp_options *ho = &ipcp_hisoptions[f->unit];
+	ipcp_options *ao = &ipcp_allowoptions[f->unit];
+#ifdef OLD_CI_ADDRS
+	ipcp_options *go = &ipcp_gotoptions[f->unit];
+#endif
+	u_char *cip, *next;				/* Pointer to current and next CIs */
+	u_short cilen, citype;			/* Parsed len, type */
+	u_short cishort;				/* Parsed short value */
+	u32_t tl, ciaddr1;			/* Parsed address values */
+#ifdef OLD_CI_ADDRS
+	u32_t ciaddr2;				/* Parsed address values */
+#endif
+	int rc = CONFACK;				/* Final packet return code */
+	int orc;						/* Individual option return code */
+	u_char *p;						/* Pointer to next char to parse */
+	u_char *ucp = inp;				/* Pointer to current output char */
+	int l = *len;					/* Length left */
+	u_char maxslotindex, cflag;
+	int d;
+	
+	cis_received[f->unit] = 1;
+	
+	/*
+	 * Reset all his options.
+	 */
+	BZERO(ho, sizeof(*ho));
+	
+	/*
+	 * Process all his options.
+	 */
+	next = inp;
+	while (l) {
+		orc = CONFACK;				/* Assume success */
+		cip = p = next;				/* Remember begining of CI */
+		if (l < 2 ||				/* Not enough data for CI header or */
+				p[1] < 2 ||			/*  CI length too small or */
+				p[1] > l) {			/*  CI length too big? */
+			IPCPDEBUG((LOG_INFO, "ipcp_reqci: bad CI length!\n"));
+			orc = CONFREJ;			/* Reject bad CI */
+			cilen = l;				/* Reject till end of packet */
+			l = 0;					/* Don't loop again */
+			goto endswitch;
+		}
+		GETCHAR(citype, p);			/* Parse CI type */
+		GETCHAR(cilen, p);			/* Parse CI length */
+		l -= cilen;					/* Adjust remaining length */
+		next += cilen;				/* Step to next CI */
+
+		switch (citype) {			/* Check CI type */
+#ifdef OLD_CI_ADDRS /* Need to save space... */
+		case CI_ADDRS:
+			IPCPDEBUG((LOG_INFO, "ipcp_reqci: received ADDRS\n"));
+			if (!ao->neg_addr ||
+					cilen != CILEN_ADDRS) {	/* Check CI length */
+				orc = CONFREJ;		/* Reject CI */
+				break;
+			}
+			
+			/*
+			 * If he has no address, or if we both have his address but
+			 * disagree about it, then NAK it with our idea.
+			 * In particular, if we don't know his address, but he does,
+			 * then accept it.
+			 */
+			GETLONG(tl, p);		/* Parse source address (his) */
+			ciaddr1 = htonl(tl);
+			IPCPDEBUG((LOG_INFO, "his addr %s\n", inet_ntoa(ciaddr1)));
+			if (ciaddr1 != wo->hisaddr
+					&& (ciaddr1 == 0 || !wo->accept_remote)) {
+				orc = CONFNAK;
+				if (!reject_if_disagree) {
+					DECPTR(sizeof(u32_t), p);
+					tl = ntohl(wo->hisaddr);
+					PUTLONG(tl, p);
+				}
+			} else if (ciaddr1 == 0 && wo->hisaddr == 0) {
+				/*
+				 * If neither we nor he knows his address, reject the option.
+				 */
+				orc = CONFREJ;
+				wo->req_addr = 0;	/* don't NAK with 0.0.0.0 later */
+				break;
+			}
+			
+			/*
+			 * If he doesn't know our address, or if we both have our address
+			 * but disagree about it, then NAK it with our idea.
+			 */
+			GETLONG(tl, p);		/* Parse desination address (ours) */
+			ciaddr2 = htonl(tl);
+			IPCPDEBUG((LOG_INFO, "our addr %s\n", inet_ntoa(ciaddr2)));
+			if (ciaddr2 != wo->ouraddr) {
+				if (ciaddr2 == 0 || !wo->accept_local) {
+					orc = CONFNAK;
+					if (!reject_if_disagree) {
+						DECPTR(sizeof(u32_t), p);
+						tl = ntohl(wo->ouraddr);
+						PUTLONG(tl, p);
+					}
+				} else {
+					go->ouraddr = ciaddr2;	/* accept peer's idea */
+				}
+			}
+			
+			ho->neg_addr = 1;
+			ho->old_addrs = 1;
+			ho->hisaddr = ciaddr1;
+			ho->ouraddr = ciaddr2;
+			break;
+#endif
+		
+		case CI_ADDR:
+			if (!ao->neg_addr) {
+				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Reject ADDR not allowed\n"));
+				orc = CONFREJ;				/* Reject CI */
+				break;
+			} else if (cilen != CILEN_ADDR) {	/* Check CI length */
+				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Reject ADDR bad len\n"));
+				orc = CONFREJ;				/* Reject CI */
+				break;
+			}
+			
+			/*
+			 * If he has no address, or if we both have his address but
+			 * disagree about it, then NAK it with our idea.
+			 * In particular, if we don't know his address, but he does,
+			 * then accept it.
+			 */
+			GETLONG(tl, p);	/* Parse source address (his) */
+			ciaddr1 = htonl(tl);
+			if (ciaddr1 != wo->hisaddr
+					&& (ciaddr1 == 0 || !wo->accept_remote)) {
+				orc = CONFNAK;
+				if (!reject_if_disagree) {
+					DECPTR(sizeof(u32_t), p);
+					tl = ntohl(wo->hisaddr);
+					PUTLONG(tl, p);
+				}
+				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Nak ADDR %s\n", inet_ntoa(ciaddr1)));
+			} else if (ciaddr1 == 0 && wo->hisaddr == 0) {
+				/*
+				 * Don't ACK an address of 0.0.0.0 - reject it instead.
+				 */
+				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Reject ADDR %s\n", inet_ntoa(ciaddr1)));
+				orc = CONFREJ;
+				wo->req_addr = 0;	/* don't NAK with 0.0.0.0 later */
+				break;
+			}
+			
+			ho->neg_addr = 1;
+			ho->hisaddr = ciaddr1;
+			IPCPDEBUG((LOG_INFO, "ipcp_reqci: ADDR %s\n", inet_ntoa(ciaddr1)));
+			break;
+		
+		case CI_MS_DNS1:
+		case CI_MS_DNS2:
+			/* Microsoft primary or secondary DNS request */
+			d = citype == CI_MS_DNS2;
+			
+			/* If we do not have a DNS address then we cannot send it */
+			if (ao->dnsaddr[d] == 0 ||
+					cilen != CILEN_ADDR) {	/* Check CI length */
+				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting DNS%d Request\n", d+1));
+				orc = CONFREJ;				/* Reject CI */
+				break;
+			}
+			GETLONG(tl, p);
+			if (htonl(tl) != ao->dnsaddr[d]) {
+				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Naking DNS%d Request %d\n",
+							d+1, inet_ntoa(tl)));
+				DECPTR(sizeof(u32_t), p);
+				tl = ntohl(ao->dnsaddr[d]);
+				PUTLONG(tl, p);
+				orc = CONFNAK;
+			}
+			IPCPDEBUG((LOG_INFO, "ipcp_reqci: received DNS%d Request\n", d+1));
+			break;
+		
+		case CI_MS_WINS1:
+		case CI_MS_WINS2:
+			/* Microsoft primary or secondary WINS request */
+			d = citype == CI_MS_WINS2;
+			IPCPDEBUG((LOG_INFO, "ipcp_reqci: received WINS%d Request\n", d+1));
+			
+			/* If we do not have a DNS address then we cannot send it */
+			if (ao->winsaddr[d] == 0 ||
+				cilen != CILEN_ADDR) {	/* Check CI length */
+				orc = CONFREJ;			/* Reject CI */
+				break;
+			}
+			GETLONG(tl, p);
+			if (htonl(tl) != ao->winsaddr[d]) {
+				DECPTR(sizeof(u32_t), p);
+				tl = ntohl(ao->winsaddr[d]);
+				PUTLONG(tl, p);
+				orc = CONFNAK;
+			}
+			break;
+		
+		case CI_COMPRESSTYPE:
+			if (!ao->neg_vj) {
+				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting COMPRESSTYPE not allowed\n"));
+				orc = CONFREJ;
+				break;
+			} else if (cilen != CILEN_VJ && cilen != CILEN_COMPRESS) {
+				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting COMPRESSTYPE len=%d\n", cilen));
+				orc = CONFREJ;
+				break;
+			}
+			GETSHORT(cishort, p);
+			
+			if (!(cishort == IPCP_VJ_COMP ||
+					(cishort == IPCP_VJ_COMP_OLD && cilen == CILEN_COMPRESS))) {
+				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting COMPRESSTYPE %d\n", cishort));
+				orc = CONFREJ;
+				break;
+			}
+			
+			ho->neg_vj = 1;
+			ho->vj_protocol = cishort;
+			if (cilen == CILEN_VJ) {
+				GETCHAR(maxslotindex, p);
+				if (maxslotindex > ao->maxslotindex) { 
+					IPCPDEBUG((LOG_INFO, "ipcp_reqci: Naking VJ max slot %d\n", maxslotindex));
+					orc = CONFNAK;
+					if (!reject_if_disagree){
+						DECPTR(1, p);
+						PUTCHAR(ao->maxslotindex, p);
+					}
+				}
+				GETCHAR(cflag, p);
+				if (cflag && !ao->cflag) {
+					IPCPDEBUG((LOG_INFO, "ipcp_reqci: Naking VJ cflag %d\n", cflag));
+					orc = CONFNAK;
+					if (!reject_if_disagree){
+						DECPTR(1, p);
+						PUTCHAR(wo->cflag, p);
+					}
+				}
+				ho->maxslotindex = maxslotindex;
+				ho->cflag = cflag;
+			} else {
+				ho->old_vj = 1;
+				ho->maxslotindex = MAX_SLOTS - 1;
+				ho->cflag = 1;
+			}
+			IPCPDEBUG((LOG_INFO, 
+						"ipcp_reqci: received COMPRESSTYPE p=%d old=%d maxslot=%d cflag=%d\n",
+						ho->vj_protocol, ho->old_vj, ho->maxslotindex, ho->cflag));
+			break;
+			
+		default:
+			IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting unknown CI type %d\n", citype));
+			orc = CONFREJ;
+			break;
+		}
+		
+endswitch:
+		if (orc == CONFACK &&		/* Good CI */
+				rc != CONFACK)		/*  but prior CI wasnt? */
+			continue;				/* Don't send this one */
+		
+		if (orc == CONFNAK) {		/* Nak this CI? */
+			if (reject_if_disagree) {	/* Getting fed up with sending NAKs? */
+				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting too many naks\n"));
+				orc = CONFREJ;		/* Get tough if so */
+			} else {
+				if (rc == CONFREJ)	/* Rejecting prior CI? */
+					continue;		/* Don't send this one */
+				if (rc == CONFACK) {	/* Ack'd all prior CIs? */
+					rc = CONFNAK;	/* Not anymore... */
+					ucp = inp;		/* Backup */
+				}
+			}
+		}
+		
+		if (orc == CONFREJ &&		/* Reject this CI */
+				rc != CONFREJ) {	/*  but no prior ones? */
+			rc = CONFREJ;
+			ucp = inp;				/* Backup */
+		}
+		
+		/* Need to move CI? */
+		if (ucp != cip)
+			BCOPY(cip, ucp, cilen);	/* Move it */
+		
+		/* Update output pointer */
+		INCPTR(cilen, ucp);
+	}
+	
+	/*
+	 * If we aren't rejecting this packet, and we want to negotiate
+	 * their address, and they didn't send their address, then we
+	 * send a NAK with a CI_ADDR option appended.  We assume the
+	 * input buffer is long enough that we can append the extra
+	 * option safely.
+	 */
+	if (rc != CONFREJ && !ho->neg_addr &&
+			wo->req_addr && !reject_if_disagree) {
+		IPCPDEBUG((LOG_INFO, "ipcp_reqci: Requesting peer address\n"));
+		if (rc == CONFACK) {
+			rc = CONFNAK;
+			ucp = inp;				/* reset pointer */
+			wo->req_addr = 0;		/* don't ask again */
+		}
+		PUTCHAR(CI_ADDR, ucp);
+		PUTCHAR(CILEN_ADDR, ucp);
+		tl = ntohl(wo->hisaddr);
+		PUTLONG(tl, ucp);
+	}
+	
+	*len = (int)(ucp - inp);		/* Compute output length */
+	IPCPDEBUG((LOG_INFO, "ipcp_reqci: returning Configure-%s\n", CODENAME(rc)));
+	return (rc);			/* Return final code */
+}
+
+
+#if 0
+/*
+ * ip_check_options - check that any IP-related options are OK,
+ * and assign appropriate defaults.
+ */
+static void ip_check_options(u_long localAddr)
+{
+	ipcp_options *wo = &ipcp_wantoptions[0];
+
+	/*
+	 * Load our default IP address but allow the remote host to give us
+	 * a new address.
+	 */
+	if (wo->ouraddr == 0 && !ppp_settings.disable_defaultip) {
+		wo->accept_local = 1;	/* don't insist on this default value */
+		wo->ouraddr = htonl(localAddr);
+	}
+}
+#endif
+
+
+/*
+ * ipcp_up - IPCP has come UP.
+ *
+ * Configure the IP network interface appropriately and bring it up.
+ */
+static void ipcp_up(fsm *f)
+{
+	u32_t mask;
+	ipcp_options *ho = &ipcp_hisoptions[f->unit];
+	ipcp_options *go = &ipcp_gotoptions[f->unit];
+	ipcp_options *wo = &ipcp_wantoptions[f->unit];
+	
+	np_up(f->unit, PPP_IP);
+	IPCPDEBUG((LOG_INFO, "ipcp: up\n"));
+	
+	/*
+	 * We must have a non-zero IP address for both ends of the link.
+	 */
+	if (!ho->neg_addr)
+		ho->hisaddr = wo->hisaddr;
+	
+	if (ho->hisaddr == 0) {
+		IPCPDEBUG((LOG_ERR, "Could not determine remote IP address\n"));
+		ipcp_close(f->unit, "Could not determine remote IP address");
+		return;
+	}
+	if (go->ouraddr == 0) {
+		IPCPDEBUG((LOG_ERR, "Could not determine local IP address\n"));
+		ipcp_close(f->unit, "Could not determine local IP address");
+		return;
+	}
+	
+	if (ppp_settings.usepeerdns && (go->dnsaddr[0] || go->dnsaddr[1])) {
+		/*pppGotDNSAddrs(go->dnsaddr[0], go->dnsaddr[1]);*/
+	}
+
+	/*
+	 * Check that the peer is allowed to use the IP address it wants.
+	 */
+	if (!auth_ip_addr(f->unit, ho->hisaddr)) {
+		IPCPDEBUG((LOG_ERR, "Peer is not authorized to use remote address %s\n",
+				inet_ntoa(ho->hisaddr)));
+		ipcp_close(f->unit, "Unauthorized remote IP address");
+		return;
+	}
+	
+	/* set tcp compression */
+	sifvjcomp(f->unit, ho->neg_vj, ho->cflag, ho->maxslotindex);
+	
+	/*
+	 * Set IP addresses and (if specified) netmask.
+	 */
+	mask = GetMask(go->ouraddr);
+	
+	if (!sifaddr(f->unit, go->ouraddr, ho->hisaddr, mask, go->dnsaddr[0], go->dnsaddr[1])) {
+		IPCPDEBUG((LOG_WARNING, "sifaddr failed\n"));
+		ipcp_close(f->unit, "Interface configuration failed");
+		return;
+	}
+	
+	/* bring the interface up for IP */
+	if (!sifup(f->unit)) {
+		IPCPDEBUG((LOG_WARNING, "sifup failed\n"));
+		ipcp_close(f->unit, "Interface configuration failed");
+		return;
+	}
+	
+	sifnpmode(f->unit, PPP_IP, NPMODE_PASS);
+	
+	/* assign a default route through the interface if required */
+	if (ipcp_wantoptions[f->unit].default_route) 
+		if (sifdefaultroute(f->unit, go->ouraddr, ho->hisaddr))
+			default_route_set[f->unit] = 1;
+	
+	IPCPDEBUG((LOG_NOTICE, "local  IP address %s\n", inet_ntoa(go->ouraddr)));
+	IPCPDEBUG((LOG_NOTICE, "remote IP address %s\n", inet_ntoa(ho->hisaddr)));
+	if (go->dnsaddr[0]) {
+		IPCPDEBUG((LOG_NOTICE, "primary   DNS address %s\n", inet_ntoa(go->dnsaddr[0])));
+	}
+	if (go->dnsaddr[1]) {
+		IPCPDEBUG((LOG_NOTICE, "secondary DNS address %s\n", inet_ntoa(go->dnsaddr[1])));
+	}
+}
+
+
+/*
+ * ipcp_down - IPCP has gone DOWN.
+ *
+ * Take the IP network interface down, clear its addresses
+ * and delete routes through it.
+ */
+static void ipcp_down(fsm *f)
+{
+	IPCPDEBUG((LOG_INFO, "ipcp: down\n"));
+	np_down(f->unit, PPP_IP);
+	sifvjcomp(f->unit, 0, 0, 0);
+	
+	sifdown(f->unit);
+	ipcp_clear_addrs(f->unit);
+}
+
+
+/*
+ * ipcp_clear_addrs() - clear the interface addresses, routes, etc.
+ */
+static void ipcp_clear_addrs(int unit)
+{
+	u32_t ouraddr, hisaddr;
+	
+	ouraddr = ipcp_gotoptions[unit].ouraddr;
+	hisaddr = ipcp_hisoptions[unit].hisaddr;
+	if (default_route_set[unit]) {
+		cifdefaultroute(unit, ouraddr, hisaddr);
+		default_route_set[unit] = 0;
+	}
+	cifaddr(unit, ouraddr, hisaddr);
+}
+
+
+/*
+ * ipcp_finished - possibly shut down the lower layers.
+ */
+static void ipcp_finished(fsm *f)
+{
+	np_finished(f->unit, PPP_IP);
+}
+
+#if 0
+static int ipcp_printpkt(
+	u_char *p,
+	int plen,
+	void (*printer) (void *, char *, ...),
+	void *arg
+)
+{
+	(void)p;
+	(void)plen;
+	(void)printer;
+	(void)arg;
+	return 0;
+}
+
+/*
+ * ip_active_pkt - see if this IP packet is worth bringing the link up for.
+ * We don't bring the link up for IP fragments or for TCP FIN packets
+ * with no data.
+ */
+#define IP_HDRLEN	20	/* bytes */
+#define IP_OFFMASK	0x1fff
+#define IPPROTO_TCP	6
+#define TCP_HDRLEN	20
+#define TH_FIN		0x01
+
+/*
+ * We use these macros because the IP header may be at an odd address,
+ * and some compilers might use word loads to get th_off or ip_hl.
+ */
+
+#define net_short(x)	(((x)[0] << 8) + (x)[1])
+#define get_iphl(x)	(((unsigned char *)(x))[0] & 0xF)
+#define get_ipoff(x)	net_short((unsigned char *)(x) + 6)
+#define get_ipproto(x)	(((unsigned char *)(x))[9])
+#define get_tcpoff(x)	(((unsigned char *)(x))[12] >> 4)
+#define get_tcpflags(x)	(((unsigned char *)(x))[13])
+
+static int ip_active_pkt(u_char *pkt, int len)
+{
+	u_char *tcp;
+	int hlen;
+	
+	len -= PPP_HDRLEN;
+	pkt += PPP_HDRLEN;
+	if (len < IP_HDRLEN)
+		return 0;
+	if ((get_ipoff(pkt) & IP_OFFMASK) != 0)
+		return 0;
+	if (get_ipproto(pkt) != IPPROTO_TCP)
+		return 1;
+	hlen = get_iphl(pkt) * 4;
+	if (len < hlen + TCP_HDRLEN)
+		return 0;
+	tcp = pkt + hlen;
+	if ((get_tcpflags(tcp) & TH_FIN) != 0 && len == hlen + get_tcpoff(tcp) * 4)
+		return 0;
+	return 1;
+}
+#endif
+
+#endif /* PPP_SUPPORT */
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/ipcp.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/ipcp.h
new file mode 100644
index 000000000..28fc36ed8
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/ipcp.h
@@ -0,0 +1,126 @@
+/*****************************************************************************
+* ipcp.h -  PPP IP NCP: Internet Protocol Network Control Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-04 Guy Lancaster , Global Election Systems Inc.
+*	Original derived from BSD codes.
+*****************************************************************************/
+/*
+ * ipcp.h - IP Control Protocol definitions.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * $Id: ipcp.h,v 1.1 2003/05/27 14:37:56 jani Exp $
+ */
+
+#ifndef IPCP_H
+#define IPCP_H
+
+/*************************
+*** PUBLIC DEFINITIONS ***
+*************************/
+/*
+ * Options.
+ */
+#define CI_ADDRS	1			/* IP Addresses */
+#define CI_COMPRESSTYPE	2		/* Compression Type */
+#define	CI_ADDR		3
+
+#define CI_MS_WINS1	128			/* Primary WINS value */
+#define CI_MS_DNS1	129			/* Primary DNS value */
+#define CI_MS_WINS2	130			/* Secondary WINS value */
+#define CI_MS_DNS2	131			/* Secondary DNS value */
+
+#define IPCP_VJMODE_OLD 1		/* "old" mode (option # = 0x0037) */
+#define IPCP_VJMODE_RFC1172 2	/* "old-rfc"mode (option # = 0x002d) */
+#define IPCP_VJMODE_RFC1332 3	/* "new-rfc"mode (option # = 0x002d, */
+                                /*  maxslot and slot number compression) */
+
+#define IPCP_VJ_COMP 0x002d		/* current value for VJ compression option*/
+#define IPCP_VJ_COMP_OLD 0x0037	/* "old" (i.e, broken) value for VJ */
+								/* compression option*/ 
+
+
+/************************
+*** PUBLIC DATA TYPES ***
+************************/
+
+typedef struct ipcp_options {
+    u_int neg_addr : 1;			/* Negotiate IP Address? */
+    u_int old_addrs : 1;			/* Use old (IP-Addresses) option? */
+    u_int req_addr : 1;			/* Ask peer to send IP address? */
+    u_int default_route : 1;		/* Assign default route through interface? */
+    u_int proxy_arp : 1;			/* Make proxy ARP entry for peer? */
+    u_int neg_vj : 1;				/* Van Jacobson Compression? */
+    u_int old_vj : 1;				/* use old (short) form of VJ option? */
+    u_int accept_local : 1;		/* accept peer's value for ouraddr */
+    u_int accept_remote : 1;		/* accept peer's value for hisaddr */
+    u_int req_dns1 : 1;			/* Ask peer to send primary DNS address? */
+    u_int req_dns2 : 1;			/* Ask peer to send secondary DNS address? */
+    u_short vj_protocol;		/* protocol value to use in VJ option */
+    u_char maxslotindex;		/* VJ slots - 1. */
+    u_char cflag;				/* VJ slot compression flag. */
+    u32_t ouraddr, hisaddr;	/* Addresses in NETWORK BYTE ORDER */
+    u32_t dnsaddr[2];		/* Primary and secondary MS DNS entries */
+    u32_t winsaddr[2];		/* Primary and secondary MS WINS entries */
+} ipcp_options;
+
+
+/*****************************
+*** PUBLIC DATA STRUCTURES ***
+*****************************/
+
+extern fsm ipcp_fsm[];
+extern ipcp_options ipcp_wantoptions[];
+extern ipcp_options ipcp_gotoptions[];
+extern ipcp_options ipcp_allowoptions[];
+extern ipcp_options ipcp_hisoptions[];
+
+extern struct protent ipcp_protent;
+
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+
+
+#endif /* IPCP_H */
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/lcp.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/lcp.c
new file mode 100644
index 000000000..22ba078a3
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/lcp.c
@@ -0,0 +1,1991 @@
+/*****************************************************************************
+* lcp.c - Network Link Control Protocol program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-01 Guy Lancaster , Global Election Systems Inc.
+*	Original.
+*****************************************************************************/
+
+/*
+ * lcp.c - PPP Link Control Protocol.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+ 
+#include 
+ 
+#include "ppp.h"
+#if PPP_SUPPORT > 0
+#include "fsm.h"
+#include "chap.h"
+#include "magic.h"
+#include "auth.h"
+#include "lcp.h"
+#include "pppdebug.h"
+
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+/*
+ * Length of each type of configuration option (in octets)
+ */
+#define CILEN_VOID	2
+#define CILEN_CHAR	3
+#define CILEN_SHORT	4	/* CILEN_VOID + sizeof(short) */
+#define CILEN_CHAP	5	/* CILEN_VOID + sizeof(short) + 1 */
+#define CILEN_LONG	6	/* CILEN_VOID + sizeof(long) */
+#define CILEN_LQR	8	/* CILEN_VOID + sizeof(short) + sizeof(long) */
+#define CILEN_CBCP	3
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+/*
+ * Callbacks for fsm code.  (CI = Configuration Information)
+ */
+static void lcp_resetci (fsm*);	        /* Reset our CI */
+static int  lcp_cilen (fsm*);		        /* Return length of our CI */
+static void lcp_addci (fsm*, u_char*, int*);       /* Add our CI to pkt */
+static int  lcp_ackci (fsm*, u_char*, int);/* Peer ack'd our CI */
+static int  lcp_nakci (fsm*, u_char*, int);/* Peer nak'd our CI */
+static int  lcp_rejci (fsm*, u_char*, int);/* Peer rej'd our CI */
+static int  lcp_reqci (fsm*, u_char*, int*, int);  /* Rcv peer CI */
+static void lcp_up (fsm*);		            /* We're UP */
+static void lcp_down (fsm*);	    	    /* We're DOWN */
+static void lcp_starting (fsm*);   	    /* We need lower layer up */
+static void lcp_finished (fsm*);	        /* We need lower layer down */
+static int  lcp_extcode (fsm*, int, u_char, u_char*, int);
+
+static void lcp_rprotrej (fsm*, u_char*, int);
+
+/*
+ * routines to send LCP echos to peer
+ */
+static void lcp_echo_lowerup (int);
+static void lcp_echo_lowerdown (int);
+static void LcpEchoTimeout (void*);
+static void lcp_received_echo_reply (fsm*, int, u_char*, int);
+static void LcpSendEchoRequest (fsm*);
+static void LcpLinkFailure (fsm*);
+static void LcpEchoCheck (fsm*);
+
+/*
+ * Protocol entry points.
+ * Some of these are called directly.
+ */
+static void lcp_input (int, u_char *, int);
+static void lcp_protrej (int);
+
+#define CODENAME(x)	((x) == CONFACK ? "ACK" : \
+			 (x) == CONFNAK ? "NAK" : "REJ")
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+/* global vars */
+LinkPhase lcp_phase[NUM_PPP];			/* Phase of link session (RFC 1661) */
+lcp_options lcp_wantoptions[NUM_PPP];	/* Options that we want to request */
+lcp_options lcp_gotoptions[NUM_PPP];	/* Options that peer ack'd */
+lcp_options lcp_allowoptions[NUM_PPP];	/* Options we allow peer to request */
+lcp_options lcp_hisoptions[NUM_PPP];	/* Options that we ack'd */
+ext_accm xmit_accm[NUM_PPP];			/* extended transmit ACCM */
+
+
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+static fsm lcp_fsm[NUM_PPP];			/* LCP fsm structure (global)*/
+static u_int	 lcp_echo_interval = LCP_ECHOINTERVAL; /* Interval between LCP echo-requests */
+static u_int	 lcp_echo_fails = LCP_MAXECHOFAILS; /* Tolerance to unanswered echo-requests */
+static u32_t lcp_echos_pending = 0;	/* Number of outstanding echo msgs */
+static u32_t lcp_echo_number   = 0;	/* ID number of next echo frame */
+static u32_t lcp_echo_timer_running = 0;  /* TRUE if a timer is running */
+
+static u_char nak_buffer[PPP_MRU];	/* where we construct a nak packet */
+
+static fsm_callbacks lcp_callbacks = {	/* LCP callback routines */
+    lcp_resetci,		/* Reset our Configuration Information */
+    lcp_cilen,			/* Length of our Configuration Information */
+    lcp_addci,			/* Add our Configuration Information */
+    lcp_ackci,			/* ACK our Configuration Information */
+    lcp_nakci,			/* NAK our Configuration Information */
+    lcp_rejci,			/* Reject our Configuration Information */
+    lcp_reqci,			/* Request peer's Configuration Information */
+    lcp_up,				/* Called when fsm reaches OPENED state */
+    lcp_down,			/* Called when fsm leaves OPENED state */
+    lcp_starting,		/* Called when we want the lower layer up */
+    lcp_finished,		/* Called when we want the lower layer down */
+    NULL,				/* Called when Protocol-Reject received */
+    NULL,				/* Retransmission is necessary */
+    lcp_extcode,		/* Called to handle LCP-specific codes */
+    "LCP"				/* String name of protocol */
+};
+
+struct protent lcp_protent = {
+    PPP_LCP,
+    lcp_init,
+    lcp_input,
+    lcp_protrej,
+    lcp_lowerup,
+    lcp_lowerdown,
+    lcp_open,
+    lcp_close,
+#if 0
+    lcp_printpkt,
+    NULL,
+#endif
+    1,
+    "LCP",
+#if 0
+    NULL,
+    NULL,
+    NULL
+#endif
+};
+
+int lcp_loopbackfail = DEFLOOPBACKFAIL;
+
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ * lcp_init - Initialize LCP.
+ */
+void lcp_init(int unit)
+{
+	fsm *f = &lcp_fsm[unit];
+	lcp_options *wo = &lcp_wantoptions[unit];
+	lcp_options *ao = &lcp_allowoptions[unit];
+	
+	f->unit = unit;
+	f->protocol = PPP_LCP;
+	f->callbacks = &lcp_callbacks;
+	
+	fsm_init(f);
+	
+	wo->passive = 0;
+	wo->silent = 0;
+	wo->restart = 0;			/* Set to 1 in kernels or multi-line
+								 * implementations */
+	wo->neg_mru = 1;
+	wo->mru = PPP_DEFMRU;
+	wo->neg_asyncmap = 1;
+	wo->asyncmap = 0x00000000l;	/* Assume don't need to escape any ctl chars. */
+	wo->neg_chap = 0;			/* Set to 1 on server */
+	wo->neg_upap = 0;			/* Set to 1 on server */
+	wo->chap_mdtype = CHAP_DIGEST_MD5;
+	wo->neg_magicnumber = 1;
+	wo->neg_pcompression = 1;
+	wo->neg_accompression = 1;
+	wo->neg_lqr = 0;			/* no LQR implementation yet */
+	wo->neg_cbcp = 0;
+	
+	ao->neg_mru = 1;
+	ao->mru = PPP_MAXMRU;
+	ao->neg_asyncmap = 1;
+	ao->asyncmap = 0x00000000l;	/* Assume don't need to escape any ctl chars. */
+	ao->neg_chap = (CHAP_SUPPORT != 0);
+	ao->chap_mdtype = CHAP_DIGEST_MD5;
+	ao->neg_upap = (PAP_SUPPORT != 0);
+	ao->neg_magicnumber = 1;
+	ao->neg_pcompression = 1;
+	ao->neg_accompression = 1;
+	ao->neg_lqr = 0;			/* no LQR implementation yet */
+	ao->neg_cbcp = (CBCP_SUPPORT != 0);
+
+	/* 
+	 * Set transmit escape for the flag and escape characters plus anything
+	 * set for the allowable options.
+	 */
+	memset(xmit_accm[unit], 0, sizeof(xmit_accm[0]));
+	xmit_accm[unit][15] = 0x60;
+	xmit_accm[unit][0] = (u_char)(ao->asyncmap & 0xFF);
+	xmit_accm[unit][1] = (u_char)((ao->asyncmap >> 8) & 0xFF);
+	xmit_accm[unit][2] = (u_char)((ao->asyncmap >> 16) & 0xFF);
+	xmit_accm[unit][3] = (u_char)((ao->asyncmap >> 24) & 0xFF);
+	LCPDEBUG((LOG_INFO, "lcp_init: xmit_accm=%X %X %X %X\n",
+				xmit_accm[unit][0],
+				xmit_accm[unit][1],
+				xmit_accm[unit][2],
+				xmit_accm[unit][3]));
+	
+	lcp_phase[unit] = PHASE_INITIALIZE;
+}
+
+
+/*
+ * lcp_open - LCP is allowed to come up.
+ */
+void lcp_open(int unit)
+{
+	fsm *f = &lcp_fsm[unit];
+	lcp_options *wo = &lcp_wantoptions[unit];
+	
+	f->flags = 0;
+	if (wo->passive)
+		f->flags |= OPT_PASSIVE;
+	if (wo->silent)
+		f->flags |= OPT_SILENT;
+	fsm_open(f);
+	
+	lcp_phase[unit] = PHASE_ESTABLISH; 
+}
+
+
+/*
+ * lcp_close - Take LCP down.
+ */
+void lcp_close(int unit, char *reason)
+{
+	fsm *f = &lcp_fsm[unit];
+	
+	if (lcp_phase[unit] != PHASE_DEAD)
+		lcp_phase[unit] = PHASE_TERMINATE;
+	if (f->state == STOPPED && f->flags & (OPT_PASSIVE|OPT_SILENT)) {
+		/*
+		 * This action is not strictly according to the FSM in RFC1548,
+		 * but it does mean that the program terminates if you do an
+		 * lcp_close() in passive/silent mode when a connection hasn't
+		 * been established.
+		 */
+		f->state = CLOSED;
+		lcp_finished(f);
+	}
+	else
+		fsm_close(&lcp_fsm[unit], reason);
+}
+
+
+/*
+ * lcp_lowerup - The lower layer is up.
+ */
+void lcp_lowerup(int unit)
+{
+	lcp_options *wo = &lcp_wantoptions[unit];
+	
+	/*
+	* Don't use A/C or protocol compression on transmission,
+	* but accept A/C and protocol compressed packets
+	* if we are going to ask for A/C and protocol compression.
+	*/
+	ppp_set_xaccm(unit, &xmit_accm[unit]);
+	ppp_send_config(unit, PPP_MRU, 0xffffffffl, 0, 0);
+	ppp_recv_config(unit, PPP_MRU, 0x00000000l,
+					wo->neg_pcompression, wo->neg_accompression);
+	peer_mru[unit] = PPP_MRU;
+	lcp_allowoptions[unit].asyncmap 
+		= (u_long)xmit_accm[unit][0]
+			| ((u_long)xmit_accm[unit][1] << 8)
+			| ((u_long)xmit_accm[unit][2] << 16)
+			| ((u_long)xmit_accm[unit][3] << 24);
+	LCPDEBUG((LOG_INFO, "lcp_lowerup: asyncmap=%X %X %X %X\n",
+				xmit_accm[unit][3],
+				xmit_accm[unit][2],
+				xmit_accm[unit][1],
+				xmit_accm[unit][0]));
+	
+	fsm_lowerup(&lcp_fsm[unit]);
+}
+
+
+/*
+ * lcp_lowerdown - The lower layer is down.
+ */
+void lcp_lowerdown(int unit)
+{
+	fsm_lowerdown(&lcp_fsm[unit]);
+}
+
+/*
+ * lcp_sprotrej - Send a Protocol-Reject for some protocol.
+ */
+void lcp_sprotrej(int unit, u_char *p, int len)
+{
+	/*
+	* Send back the protocol and the information field of the
+	* rejected packet.  We only get here if LCP is in the OPENED state.
+	*/
+
+	fsm_sdata(&lcp_fsm[unit], PROTREJ, ++lcp_fsm[unit].id,
+				p, len);
+}
+
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+/*
+ * lcp_input - Input LCP packet.
+ */
+static void lcp_input(int unit, u_char *p, int len)
+{
+	fsm *f = &lcp_fsm[unit];
+	
+	fsm_input(f, p, len);
+}
+
+
+/*
+ * lcp_extcode - Handle a LCP-specific code.
+ */
+static int lcp_extcode(fsm *f, int code, u_char id, u_char *inp, int len)
+{
+	u_char *magp;
+	
+	switch( code ){
+	case PROTREJ:
+		lcp_rprotrej(f, inp, len);
+		break;
+	
+	case ECHOREQ:
+		if (f->state != OPENED)
+			break;
+		LCPDEBUG((LOG_INFO, "lcp: Echo-Request, Rcvd id %d\n", id));
+		magp = inp;
+		PUTLONG(lcp_gotoptions[f->unit].magicnumber, magp);
+		fsm_sdata(f, ECHOREP, id, inp, len);
+		break;
+	
+	case ECHOREP:
+		lcp_received_echo_reply(f, id, inp, len);
+		break;
+	
+	case DISCREQ:
+		break;
+	
+	default:
+		return 0;
+	}
+	return 1;
+}
+
+    
+/*
+ * lcp_rprotrej - Receive an Protocol-Reject.
+ *
+ * Figure out which protocol is rejected and inform it.
+ */
+static void lcp_rprotrej(fsm *f, u_char *inp, int len)
+{
+	int i;
+	struct protent *protp;
+	u_short prot;
+	
+	if (len < sizeof (u_short)) {
+		LCPDEBUG((LOG_INFO,
+				"lcp_rprotrej: Rcvd short Protocol-Reject packet!\n"));
+		return;
+	}
+	
+	GETSHORT(prot, inp);
+	
+	LCPDEBUG((LOG_INFO,
+			"lcp_rprotrej: Rcvd Protocol-Reject packet for %x!\n",
+			prot));
+	
+	/*
+	* Protocol-Reject packets received in any state other than the LCP
+	* OPENED state SHOULD be silently discarded.
+	*/
+	if( f->state != OPENED ){
+		LCPDEBUG((LOG_INFO, "Protocol-Reject discarded: LCP in state %d\n",
+				f->state));
+		return;
+	}
+	
+	/*
+	* Upcall the proper Protocol-Reject routine.
+	*/
+	for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i)
+		if (protp->protocol == prot && protp->enabled_flag) {
+			(*protp->protrej)(f->unit);
+			return;
+		}
+	
+	LCPDEBUG((LOG_WARNING, "Protocol-Reject for unsupported protocol 0x%x\n",
+			prot));
+}
+
+
+/*
+ * lcp_protrej - A Protocol-Reject was received.
+ */
+static void lcp_protrej(int unit)
+{
+	(void)unit;
+	/*
+	* Can't reject LCP!
+	*/
+	LCPDEBUG((LOG_WARNING,
+			"lcp_protrej: Received Protocol-Reject for LCP!\n"));
+	fsm_protreject(&lcp_fsm[unit]);
+}
+
+
+/*
+ * lcp_resetci - Reset our CI.
+ */
+static void lcp_resetci(fsm *f)
+{
+	lcp_wantoptions[f->unit].magicnumber = magic();
+	lcp_wantoptions[f->unit].numloops = 0;
+	lcp_gotoptions[f->unit] = lcp_wantoptions[f->unit];
+	peer_mru[f->unit] = PPP_MRU;
+	auth_reset(f->unit);
+}
+
+
+/*
+ * lcp_cilen - Return length of our CI.
+ */
+static int lcp_cilen(fsm *f)
+{
+	lcp_options *go = &lcp_gotoptions[f->unit];
+
+#define LENCIVOID(neg)	((neg) ? CILEN_VOID : 0)
+#define LENCICHAP(neg)	((neg) ? CILEN_CHAP : 0)
+#define LENCISHORT(neg)	((neg) ? CILEN_SHORT : 0)
+#define LENCILONG(neg)	((neg) ? CILEN_LONG : 0)
+#define LENCILQR(neg)	((neg) ? CILEN_LQR: 0)
+#define LENCICBCP(neg)	((neg) ? CILEN_CBCP: 0)
+	/*
+	* NB: we only ask for one of CHAP and UPAP, even if we will
+	* accept either.
+	*/
+	return (LENCISHORT(go->neg_mru && go->mru != PPP_DEFMRU) +
+		LENCILONG(go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl) +
+		LENCICHAP(go->neg_chap) +
+		LENCISHORT(!go->neg_chap && go->neg_upap) +
+		LENCILQR(go->neg_lqr) +
+		LENCICBCP(go->neg_cbcp) +
+		LENCILONG(go->neg_magicnumber) +
+		LENCIVOID(go->neg_pcompression) +
+		LENCIVOID(go->neg_accompression));
+}
+
+
+/*
+ * lcp_addci - Add our desired CIs to a packet.
+ */
+static void lcp_addci(fsm *f, u_char *ucp, int *lenp)
+{
+	lcp_options *go = &lcp_gotoptions[f->unit];
+	u_char *start_ucp = ucp;
+	
+#define ADDCIVOID(opt, neg) \
+	if (neg) { \
+	    LCPDEBUG((LOG_INFO, "lcp_addci: opt=%d\n", opt)); \
+		PUTCHAR(opt, ucp); \
+		PUTCHAR(CILEN_VOID, ucp); \
+	}
+#define ADDCISHORT(opt, neg, val) \
+	if (neg) { \
+	    LCPDEBUG((LOG_INFO, "lcp_addci: INT opt=%d %X\n", opt, val)); \
+		PUTCHAR(opt, ucp); \
+		PUTCHAR(CILEN_SHORT, ucp); \
+		PUTSHORT(val, ucp); \
+	}
+#define ADDCICHAP(opt, neg, val, digest) \
+	if (neg) { \
+	    LCPDEBUG((LOG_INFO, "lcp_addci: CHAP opt=%d %X\n", opt, val)); \
+		PUTCHAR(opt, ucp); \
+		PUTCHAR(CILEN_CHAP, ucp); \
+		PUTSHORT(val, ucp); \
+		PUTCHAR(digest, ucp); \
+	}
+#define ADDCILONG(opt, neg, val) \
+	if (neg) { \
+	    LCPDEBUG((LOG_INFO, "lcp_addci: L opt=%d %lX\n", opt, val)); \
+		PUTCHAR(opt, ucp); \
+		PUTCHAR(CILEN_LONG, ucp); \
+		PUTLONG(val, ucp); \
+	}
+#define ADDCILQR(opt, neg, val) \
+	if (neg) { \
+	    LCPDEBUG((LOG_INFO, "lcp_addci: LQR opt=%d %lX\n", opt, val)); \
+		PUTCHAR(opt, ucp); \
+		PUTCHAR(CILEN_LQR, ucp); \
+		PUTSHORT(PPP_LQR, ucp); \
+		PUTLONG(val, ucp); \
+	}
+#define ADDCICHAR(opt, neg, val) \
+	if (neg) { \
+	    LCPDEBUG((LOG_INFO, "lcp_addci: CHAR opt=%d %X '%z'\n", opt, val, val)); \
+		PUTCHAR(opt, ucp); \
+		PUTCHAR(CILEN_CHAR, ucp); \
+		PUTCHAR(val, ucp); \
+	}
+	
+	ADDCISHORT(CI_MRU, go->neg_mru && go->mru != PPP_DEFMRU, go->mru);
+	ADDCILONG(CI_ASYNCMAP, go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl,
+			go->asyncmap);
+	ADDCICHAP(CI_AUTHTYPE, go->neg_chap, PPP_CHAP, go->chap_mdtype);
+	ADDCISHORT(CI_AUTHTYPE, !go->neg_chap && go->neg_upap, PPP_PAP);
+	ADDCILQR(CI_QUALITY, go->neg_lqr, go->lqr_period);
+	ADDCICHAR(CI_CALLBACK, go->neg_cbcp, CBCP_OPT);
+	ADDCILONG(CI_MAGICNUMBER, go->neg_magicnumber, go->magicnumber);
+	ADDCIVOID(CI_PCOMPRESSION, go->neg_pcompression);
+	ADDCIVOID(CI_ACCOMPRESSION, go->neg_accompression);
+	
+	if (ucp - start_ucp != *lenp) {
+		/* this should never happen, because peer_mtu should be 1500 */
+		LCPDEBUG((LOG_ERR, "Bug in lcp_addci: wrong length\n"));
+	}
+}
+
+
+/*
+ * lcp_ackci - Ack our CIs.
+ * This should not modify any state if the Ack is bad.
+ *
+ * Returns:
+ *	0 - Ack was bad.
+ *	1 - Ack was good.
+ */
+static int lcp_ackci(fsm *f, u_char *p, int len)
+{
+	lcp_options *go = &lcp_gotoptions[f->unit];
+	u_char cilen, citype, cichar;
+	u_short cishort;
+	u32_t cilong;
+	
+	/*
+	* CIs must be in exactly the same order that we sent.
+	* Check packet length and CI length at each step.
+	* If we find any deviations, then this packet is bad.
+	*/
+#define ACKCIVOID(opt, neg) \
+	if (neg) { \
+		if ((len -= CILEN_VOID) < 0) \
+			goto bad; \
+		GETCHAR(citype, p); \
+		GETCHAR(cilen, p); \
+		if (cilen != CILEN_VOID || \
+				citype != opt) \
+			goto bad; \
+	}
+#define ACKCISHORT(opt, neg, val) \
+	if (neg) { \
+		if ((len -= CILEN_SHORT) < 0) \
+			goto bad; \
+		GETCHAR(citype, p); \
+		GETCHAR(cilen, p); \
+		if (cilen != CILEN_SHORT || \
+				citype != opt) \
+			goto bad; \
+		GETSHORT(cishort, p); \
+		if (cishort != val) \
+			goto bad; \
+	}
+#define ACKCICHAR(opt, neg, val) \
+	if (neg) { \
+		if ((len -= CILEN_CHAR) < 0) \
+			goto bad; \
+		GETCHAR(citype, p); \
+		GETCHAR(cilen, p); \
+		if (cilen != CILEN_CHAR || \
+				citype != opt) \
+			goto bad; \
+		GETCHAR(cichar, p); \
+		if (cichar != val) \
+			goto bad; \
+	}
+#define ACKCICHAP(opt, neg, val, digest) \
+	if (neg) { \
+		if ((len -= CILEN_CHAP) < 0) \
+			goto bad; \
+		GETCHAR(citype, p); \
+		GETCHAR(cilen, p); \
+		if (cilen != CILEN_CHAP || \
+				citype != opt) \
+			goto bad; \
+		GETSHORT(cishort, p); \
+		if (cishort != val) \
+			goto bad; \
+		GETCHAR(cichar, p); \
+		if (cichar != digest) \
+			goto bad; \
+	}
+#define ACKCILONG(opt, neg, val) \
+	if (neg) { \
+		if ((len -= CILEN_LONG) < 0) \
+			goto bad; \
+		GETCHAR(citype, p); \
+		GETCHAR(cilen, p); \
+		if (cilen != CILEN_LONG || \
+				citype != opt) \
+			goto bad; \
+		GETLONG(cilong, p); \
+		if (cilong != val) \
+			goto bad; \
+	}
+#define ACKCILQR(opt, neg, val) \
+	if (neg) { \
+		if ((len -= CILEN_LQR) < 0) \
+			goto bad; \
+		GETCHAR(citype, p); \
+		GETCHAR(cilen, p); \
+		if (cilen != CILEN_LQR || \
+				citype != opt) \
+			goto bad; \
+		GETSHORT(cishort, p); \
+		if (cishort != PPP_LQR) \
+			goto bad; \
+		GETLONG(cilong, p); \
+		if (cilong != val) \
+			goto bad; \
+	}
+	
+	ACKCISHORT(CI_MRU, go->neg_mru && go->mru != PPP_DEFMRU, go->mru);
+	ACKCILONG(CI_ASYNCMAP, go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl,
+			go->asyncmap);
+	ACKCICHAP(CI_AUTHTYPE, go->neg_chap, PPP_CHAP, go->chap_mdtype);
+	ACKCISHORT(CI_AUTHTYPE, !go->neg_chap && go->neg_upap, PPP_PAP);
+	ACKCILQR(CI_QUALITY, go->neg_lqr, go->lqr_period);
+	ACKCICHAR(CI_CALLBACK, go->neg_cbcp, CBCP_OPT);
+	ACKCILONG(CI_MAGICNUMBER, go->neg_magicnumber, go->magicnumber);
+	ACKCIVOID(CI_PCOMPRESSION, go->neg_pcompression);
+	ACKCIVOID(CI_ACCOMPRESSION, go->neg_accompression);
+	
+	/*
+	 * If there are any remaining CIs, then this packet is bad.
+	 */
+	if (len != 0)
+		goto bad;
+	LCPDEBUG((LOG_INFO, "lcp_acki: Ack\n"));
+	return (1);
+bad:
+	LCPDEBUG((LOG_WARNING, "lcp_acki: received bad Ack!\n"));
+	return (0);
+}
+
+
+/*
+ * lcp_nakci - Peer has sent a NAK for some of our CIs.
+ * This should not modify any state if the Nak is bad
+ * or if LCP is in the OPENED state.
+ *
+ * Returns:
+ *	0 - Nak was bad.
+ *	1 - Nak was good.
+ */
+static int lcp_nakci(fsm *f, u_char *p, int len)
+{
+	lcp_options *go = &lcp_gotoptions[f->unit];
+	lcp_options *wo = &lcp_wantoptions[f->unit];
+	u_char citype, cichar, *next;
+	u_short cishort;
+	u32_t cilong;
+	lcp_options no;		/* options we've seen Naks for */
+	lcp_options try;		/* options to request next time */
+	int looped_back = 0;
+	int cilen;
+	
+	BZERO(&no, sizeof(no));
+	try = *go;
+	
+	/*
+	* Any Nak'd CIs must be in exactly the same order that we sent.
+	* Check packet length and CI length at each step.
+	* If we find any deviations, then this packet is bad.
+	*/
+#define NAKCIVOID(opt, neg, code) \
+	if (go->neg && \
+			len >= CILEN_VOID && \
+			p[1] == CILEN_VOID && \
+			p[0] == opt) { \
+		len -= CILEN_VOID; \
+		INCPTR(CILEN_VOID, p); \
+		no.neg = 1; \
+		code \
+	}
+#define NAKCICHAP(opt, neg, code) \
+	if (go->neg && \
+			len >= CILEN_CHAP && \
+			p[1] == CILEN_CHAP && \
+			p[0] == opt) { \
+		len -= CILEN_CHAP; \
+		INCPTR(2, p); \
+		GETSHORT(cishort, p); \
+		GETCHAR(cichar, p); \
+		no.neg = 1; \
+		code \
+	}
+#define NAKCICHAR(opt, neg, code) \
+	if (go->neg && \
+			len >= CILEN_CHAR && \
+			p[1] == CILEN_CHAR && \
+			p[0] == opt) { \
+		len -= CILEN_CHAR; \
+		INCPTR(2, p); \
+		GETCHAR(cichar, p); \
+		no.neg = 1; \
+		code \
+	}
+#define NAKCISHORT(opt, neg, code) \
+	if (go->neg && \
+			len >= CILEN_SHORT && \
+			p[1] == CILEN_SHORT && \
+			p[0] == opt) { \
+		len -= CILEN_SHORT; \
+		INCPTR(2, p); \
+		GETSHORT(cishort, p); \
+		no.neg = 1; \
+		code \
+	}
+#define NAKCILONG(opt, neg, code) \
+	if (go->neg && \
+			len >= CILEN_LONG && \
+			p[1] == CILEN_LONG && \
+			p[0] == opt) { \
+		len -= CILEN_LONG; \
+		INCPTR(2, p); \
+		GETLONG(cilong, p); \
+		no.neg = 1; \
+		code \
+	}
+#define NAKCILQR(opt, neg, code) \
+	if (go->neg && \
+			len >= CILEN_LQR && \
+			p[1] == CILEN_LQR && \
+			p[0] == opt) { \
+		len -= CILEN_LQR; \
+		INCPTR(2, p); \
+		GETSHORT(cishort, p); \
+		GETLONG(cilong, p); \
+		no.neg = 1; \
+		code \
+	}
+	
+	/*
+	* We don't care if they want to send us smaller packets than
+	* we want.  Therefore, accept any MRU less than what we asked for,
+	* but then ignore the new value when setting the MRU in the kernel.
+	* If they send us a bigger MRU than what we asked, accept it, up to
+	* the limit of the default MRU we'd get if we didn't negotiate.
+	*/
+	if (go->neg_mru && go->mru != PPP_DEFMRU) {
+		NAKCISHORT(CI_MRU, neg_mru,
+			if (cishort <= wo->mru || cishort < PPP_DEFMRU)
+				try.mru = cishort;
+		);
+	}
+	
+	/*
+	* Add any characters they want to our (receive-side) asyncmap.
+	*/
+	if (go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl) {
+		NAKCILONG(CI_ASYNCMAP, neg_asyncmap,
+			try.asyncmap = go->asyncmap | cilong;
+		);
+	}
+	
+	/*
+	* If they've nak'd our authentication-protocol, check whether
+	* they are proposing a different protocol, or a different
+	* hash algorithm for CHAP.
+	*/
+	if ((go->neg_chap || go->neg_upap)
+			&& len >= CILEN_SHORT
+			&& p[0] == CI_AUTHTYPE && p[1] >= CILEN_SHORT && p[1] <= len) {
+		cilen = p[1];
+	len -= cilen;
+	no.neg_chap = go->neg_chap;
+	no.neg_upap = go->neg_upap;
+	INCPTR(2, p);
+	GETSHORT(cishort, p);
+	if (cishort == PPP_PAP && cilen == CILEN_SHORT) {
+		/*
+		 * If we were asking for CHAP, they obviously don't want to do it.
+		 * If we weren't asking for CHAP, then we were asking for PAP,
+		 * in which case this Nak is bad.
+		 */
+		if (!go->neg_chap)
+			goto bad;
+		try.neg_chap = 0;
+	
+	} else if (cishort == PPP_CHAP && cilen == CILEN_CHAP) {
+		GETCHAR(cichar, p);
+		if (go->neg_chap) {
+			/*
+			 * We were asking for CHAP/MD5; they must want a different
+			 * algorithm.  If they can't do MD5, we'll have to stop
+			 * asking for CHAP.
+			 */
+			if (cichar != go->chap_mdtype)
+				try.neg_chap = 0;
+		} else {
+			/*
+			 * Stop asking for PAP if we were asking for it.
+			 */
+			try.neg_upap = 0;
+		}
+	
+	} else {
+		/*
+		 * We don't recognize what they're suggesting.
+		 * Stop asking for what we were asking for.
+		 */
+		if (go->neg_chap)
+			try.neg_chap = 0;
+		else
+			try.neg_upap = 0;
+		p += cilen - CILEN_SHORT;
+	}
+	}
+	
+	/*
+	* If they can't cope with our link quality protocol, we'll have
+	* to stop asking for LQR.  We haven't got any other protocol.
+	* If they Nak the reporting period, take their value XXX ?
+	*/
+	NAKCILQR(CI_QUALITY, neg_lqr,
+		if (cishort != PPP_LQR)
+			try.neg_lqr = 0;
+		else
+			try.lqr_period = cilong;
+	);
+	
+	/*
+	* Only implementing CBCP...not the rest of the callback options
+	*/
+	NAKCICHAR(CI_CALLBACK, neg_cbcp,
+		try.neg_cbcp = 0;
+	);
+	
+	/*
+	* Check for a looped-back line.
+	*/
+	NAKCILONG(CI_MAGICNUMBER, neg_magicnumber,
+		try.magicnumber = magic();
+		looped_back = 1;
+	);
+	
+	/*
+	* Peer shouldn't send Nak for protocol compression or
+	* address/control compression requests; they should send
+	* a Reject instead.  If they send a Nak, treat it as a Reject.
+	*/
+	NAKCIVOID(CI_PCOMPRESSION, neg_pcompression,
+		try.neg_pcompression = 0;
+	);
+	NAKCIVOID(CI_ACCOMPRESSION, neg_accompression,
+		try.neg_accompression = 0;
+	);
+	
+	/*
+	* There may be remaining CIs, if the peer is requesting negotiation
+	* on an option that we didn't include in our request packet.
+	* If we see an option that we requested, or one we've already seen
+	* in this packet, then this packet is bad.
+	* If we wanted to respond by starting to negotiate on the requested
+	* option(s), we could, but we don't, because except for the
+	* authentication type and quality protocol, if we are not negotiating
+	* an option, it is because we were told not to.
+	* For the authentication type, the Nak from the peer means
+	* `let me authenticate myself with you' which is a bit pointless.
+	* For the quality protocol, the Nak means `ask me to send you quality
+	* reports', but if we didn't ask for them, we don't want them.
+	* An option we don't recognize represents the peer asking to
+	* negotiate some option we don't support, so ignore it.
+	*/
+	while (len > CILEN_VOID) {
+		GETCHAR(citype, p);
+		GETCHAR(cilen, p);
+		if (cilen < CILEN_VOID || (len -= cilen) < 0)
+			goto bad;
+		next = p + cilen - 2;
+		
+		switch (citype) {
+		case CI_MRU:
+			if ((go->neg_mru && go->mru != PPP_DEFMRU)
+					|| no.neg_mru || cilen != CILEN_SHORT)
+				goto bad;
+			GETSHORT(cishort, p);
+			if (cishort < PPP_DEFMRU)
+				try.mru = cishort;
+			break;
+		case CI_ASYNCMAP:
+			if ((go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl)
+					|| no.neg_asyncmap || cilen != CILEN_LONG)
+				goto bad;
+			break;
+		case CI_AUTHTYPE:
+			if (go->neg_chap || no.neg_chap || go->neg_upap || no.neg_upap)
+				goto bad;
+			break;
+		case CI_MAGICNUMBER:
+			if (go->neg_magicnumber || no.neg_magicnumber ||
+					cilen != CILEN_LONG)
+				goto bad;
+			break;
+		case CI_PCOMPRESSION:
+			if (go->neg_pcompression || no.neg_pcompression
+					|| cilen != CILEN_VOID)
+				goto bad;
+			break;
+		case CI_ACCOMPRESSION:
+			if (go->neg_accompression || no.neg_accompression
+					|| cilen != CILEN_VOID)
+				goto bad;
+			break;
+		case CI_QUALITY:
+			if (go->neg_lqr || no.neg_lqr || cilen != CILEN_LQR)
+				goto bad;
+			break;
+		}
+		p = next;
+	}
+	
+	/* If there is still anything left, this packet is bad. */
+	if (len != 0)
+		goto bad;
+	
+	/*
+	* OK, the Nak is good.  Now we can update state.
+	*/
+	if (f->state != OPENED) {
+		if (looped_back) {
+			if (++try.numloops >= lcp_loopbackfail) {
+				LCPDEBUG((LOG_NOTICE, "Serial line is looped back.\n"));
+				lcp_close(f->unit, "Loopback detected");
+			}
+		} 
+		else
+			try.numloops = 0;
+		*go = try;
+	}
+	
+	return 1;
+	
+bad:
+	LCPDEBUG((LOG_WARNING, "lcp_nakci: received bad Nak!\n"));
+	return 0;
+}
+
+
+/*
+ * lcp_rejci - Peer has Rejected some of our CIs.
+ * This should not modify any state if the Reject is bad
+ * or if LCP is in the OPENED state.
+ *
+ * Returns:
+ *	0 - Reject was bad.
+ *	1 - Reject was good.
+ */
+static int lcp_rejci(fsm *f, u_char *p, int len)
+{
+	lcp_options *go = &lcp_gotoptions[f->unit];
+	u_char cichar;
+	u_short cishort;
+	u32_t cilong;
+	lcp_options try;		/* options to request next time */
+	
+	try = *go;
+	
+	/*
+	* Any Rejected CIs must be in exactly the same order that we sent.
+	* Check packet length and CI length at each step.
+	* If we find any deviations, then this packet is bad.
+	*/
+#define REJCIVOID(opt, neg) \
+	if (go->neg && \
+			len >= CILEN_VOID && \
+			p[1] == CILEN_VOID && \
+			p[0] == opt) { \
+		len -= CILEN_VOID; \
+		INCPTR(CILEN_VOID, p); \
+		try.neg = 0; \
+		LCPDEBUG((LOG_INFO, "lcp_rejci: void opt %d rejected\n", opt)); \
+	}
+#define REJCISHORT(opt, neg, val) \
+	if (go->neg && \
+			len >= CILEN_SHORT && \
+			p[1] == CILEN_SHORT && \
+			p[0] == opt) { \
+		len -= CILEN_SHORT; \
+		INCPTR(2, p); \
+		GETSHORT(cishort, p); \
+		/* Check rejected value. */ \
+		if (cishort != val) \
+			goto bad; \
+		try.neg = 0; \
+		LCPDEBUG((LOG_INFO,"lcp_rejci: short opt %d rejected\n", opt)); \
+	}
+#define REJCICHAP(opt, neg, val, digest) \
+	if (go->neg && \
+			len >= CILEN_CHAP && \
+			p[1] == CILEN_CHAP && \
+			p[0] == opt) { \
+		len -= CILEN_CHAP; \
+		INCPTR(2, p); \
+		GETSHORT(cishort, p); \
+		GETCHAR(cichar, p); \
+		/* Check rejected value. */ \
+		if (cishort != val || cichar != digest) \
+			goto bad; \
+		try.neg = 0; \
+		try.neg_upap = 0; \
+		LCPDEBUG((LOG_INFO,"lcp_rejci: chap opt %d rejected\n", opt)); \
+	}
+#define REJCILONG(opt, neg, val) \
+	if (go->neg && \
+			len >= CILEN_LONG && \
+			p[1] == CILEN_LONG && \
+			p[0] == opt) { \
+		len -= CILEN_LONG; \
+		INCPTR(2, p); \
+		GETLONG(cilong, p); \
+		/* Check rejected value. */ \
+		if (cilong != val) \
+			goto bad; \
+		try.neg = 0; \
+		LCPDEBUG((LOG_INFO,"lcp_rejci: long opt %d rejected\n", opt)); \
+	}
+#define REJCILQR(opt, neg, val) \
+	if (go->neg && \
+			len >= CILEN_LQR && \
+			p[1] == CILEN_LQR && \
+			p[0] == opt) { \
+		len -= CILEN_LQR; \
+		INCPTR(2, p); \
+		GETSHORT(cishort, p); \
+		GETLONG(cilong, p); \
+		/* Check rejected value. */ \
+		if (cishort != PPP_LQR || cilong != val) \
+			goto bad; \
+		try.neg = 0; \
+		LCPDEBUG((LOG_INFO,"lcp_rejci: LQR opt %d rejected\n", opt)); \
+	}
+#define REJCICBCP(opt, neg, val) \
+	if (go->neg && \
+			len >= CILEN_CBCP && \
+			p[1] == CILEN_CBCP && \
+			p[0] == opt) { \
+		len -= CILEN_CBCP; \
+		INCPTR(2, p); \
+		GETCHAR(cichar, p); \
+		/* Check rejected value. */ \
+		if (cichar != val) \
+			goto bad; \
+		try.neg = 0; \
+		LCPDEBUG((LOG_INFO,"lcp_rejci: Callback opt %d rejected\n", opt)); \
+	}
+	
+	REJCISHORT(CI_MRU, neg_mru, go->mru);
+	REJCILONG(CI_ASYNCMAP, neg_asyncmap, go->asyncmap);
+	REJCICHAP(CI_AUTHTYPE, neg_chap, PPP_CHAP, go->chap_mdtype);
+	if (!go->neg_chap) {
+		REJCISHORT(CI_AUTHTYPE, neg_upap, PPP_PAP);
+	}
+	REJCILQR(CI_QUALITY, neg_lqr, go->lqr_period);
+	REJCICBCP(CI_CALLBACK, neg_cbcp, CBCP_OPT);
+	REJCILONG(CI_MAGICNUMBER, neg_magicnumber, go->magicnumber);
+	REJCIVOID(CI_PCOMPRESSION, neg_pcompression);
+	REJCIVOID(CI_ACCOMPRESSION, neg_accompression);
+	
+	/*
+	* If there are any remaining CIs, then this packet is bad.
+	*/
+	if (len != 0)
+		goto bad;
+	/*
+	* Now we can update state.
+	*/
+	if (f->state != OPENED)
+		*go = try;
+	return 1;
+	
+bad:
+	LCPDEBUG((LOG_WARNING, "lcp_rejci: received bad Reject!\n"));
+	return 0;
+}
+
+
+/*
+ * lcp_reqci - Check the peer's requested CIs and send appropriate response.
+ *
+ * Returns: CONFACK, CONFNAK or CONFREJ and input packet modified
+ * appropriately.  If reject_if_disagree is non-zero, doesn't return
+ * CONFNAK; returns CONFREJ if it can't return CONFACK.
+ */
+static int lcp_reqci(fsm *f, 
+						u_char *inp,		/* Requested CIs */
+						int *lenp,			/* Length of requested CIs */
+						int reject_if_disagree)
+{
+	lcp_options *go = &lcp_gotoptions[f->unit];
+	lcp_options *ho = &lcp_hisoptions[f->unit];
+	lcp_options *ao = &lcp_allowoptions[f->unit];
+	u_char *cip, *next;			/* Pointer to current and next CIs */
+	int cilen, citype, cichar;	/* Parsed len, type, char value */
+	u_short cishort;			/* Parsed short value */
+	u32_t cilong;			/* Parse long value */
+	int rc = CONFACK;			/* Final packet return code */
+	int orc;					/* Individual option return code */
+	u_char *p;					/* Pointer to next char to parse */
+	u_char *rejp;				/* Pointer to next char in reject frame */
+	u_char *nakp;				/* Pointer to next char in Nak frame */
+	int l = *lenp;				/* Length left */
+#if TRACELCP > 0
+	char traceBuf[80];
+	int traceNdx = 0;
+#endif
+	
+	/*
+	 * Reset all his options.
+	 */
+	BZERO(ho, sizeof(*ho));
+	
+	/*
+	 * Process all his options.
+	 */
+	next = inp;
+	nakp = nak_buffer;
+	rejp = inp;
+	while (l) {
+		orc = CONFACK;			/* Assume success */
+		cip = p = next;			/* Remember begining of CI */
+		if (l < 2 ||			/* Not enough data for CI header or */
+				p[1] < 2 ||			/*  CI length too small or */
+				p[1] > l) {			/*  CI length too big? */
+			LCPDEBUG((LOG_WARNING, "lcp_reqci: bad CI length!\n"));
+			orc = CONFREJ;		/* Reject bad CI */
+			cilen = l;			/* Reject till end of packet */
+			l = 0;			/* Don't loop again */
+			citype = 0;
+			goto endswitch;
+		}
+		GETCHAR(citype, p);		/* Parse CI type */
+		GETCHAR(cilen, p);		/* Parse CI length */
+		l -= cilen;			/* Adjust remaining length */
+		next += cilen;			/* Step to next CI */
+		
+		switch (citype) {		/* Check CI type */
+		case CI_MRU:
+			if (!ao->neg_mru) {		/* Allow option? */
+				LCPDEBUG((LOG_INFO, "lcp_reqci: Reject MRU - not allowed\n"));
+				orc = CONFREJ;		/* Reject CI */
+				break;
+			} else if (cilen != CILEN_SHORT) {	/* Check CI length */
+				LCPDEBUG((LOG_INFO, "lcp_reqci: Reject MRU - bad length\n"));
+				orc = CONFREJ;		/* Reject CI */
+				break;
+			}
+			GETSHORT(cishort, p);	/* Parse MRU */
+			
+			/*
+			 * He must be able to receive at least our minimum.
+			 * No need to check a maximum.  If he sends a large number,
+			 * we'll just ignore it.
+			 */
+			if (cishort < PPP_MINMRU) {
+				LCPDEBUG((LOG_INFO, "lcp_reqci: Nak - MRU too small\n"));
+				orc = CONFNAK;		/* Nak CI */
+				PUTCHAR(CI_MRU, nakp);
+				PUTCHAR(CILEN_SHORT, nakp);
+				PUTSHORT(PPP_MINMRU, nakp);	/* Give him a hint */
+				break;
+			}
+			ho->neg_mru = 1;		/* Remember he sent MRU */
+			ho->mru = cishort;		/* And remember value */
+#if TRACELCP > 0
+			sprintf(&traceBuf[traceNdx], " MRU %d", cishort);
+			traceNdx = strlen(traceBuf);
+#endif
+			break;
+		
+		case CI_ASYNCMAP:
+			if (!ao->neg_asyncmap) {
+				LCPDEBUG((LOG_INFO, "lcp_reqci: Reject ASYNCMAP not allowed\n"));
+				orc = CONFREJ;
+				break;
+			} else if (cilen != CILEN_LONG) {
+				LCPDEBUG((LOG_INFO, "lcp_reqci: Reject ASYNCMAP bad length\n"));
+				orc = CONFREJ;
+				break;
+			}
+			GETLONG(cilong, p);
+			
+			/*
+			 * Asyncmap must have set at least the bits
+			 * which are set in lcp_allowoptions[unit].asyncmap.
+			 */
+			if ((ao->asyncmap & ~cilong) != 0) {
+				LCPDEBUG((LOG_INFO, "lcp_reqci: Nak ASYNCMAP %lX missing %lX\n", 
+							cilong, ao->asyncmap));
+				orc = CONFNAK;
+				PUTCHAR(CI_ASYNCMAP, nakp);
+				PUTCHAR(CILEN_LONG, nakp);
+				PUTLONG(ao->asyncmap | cilong, nakp);
+				break;
+			}
+			ho->neg_asyncmap = 1;
+			ho->asyncmap = cilong;
+#if TRACELCP > 0
+			sprintf(&traceBuf[traceNdx], " ASYNCMAP=%lX", cilong);
+			traceNdx = strlen(traceBuf);
+#endif
+			break;
+		
+		case CI_AUTHTYPE:
+			if (cilen < CILEN_SHORT) {
+				LCPDEBUG((LOG_INFO, "lcp_reqci: Reject AUTHTYPE missing arg\n"));
+				orc = CONFREJ;
+				break;
+			} else if (!(ao->neg_upap || ao->neg_chap)) {
+				/*
+				 * Reject the option if we're not willing to authenticate.
+				 */
+				LCPDEBUG((LOG_INFO, "lcp_reqci: Reject AUTHTYPE not allowed\n"));
+				orc = CONFREJ;
+				break;
+			}
+			GETSHORT(cishort, p);
+			
+			/*
+			 * Authtype must be UPAP or CHAP.
+			 *
+			 * Note: if both ao->neg_upap and ao->neg_chap are set,
+			 * and the peer sends a Configure-Request with two
+			 * authenticate-protocol requests, one for CHAP and one
+			 * for UPAP, then we will reject the second request.
+			 * Whether we end up doing CHAP or UPAP depends then on
+			 * the ordering of the CIs in the peer's Configure-Request.
+			 */
+			
+			if (cishort == PPP_PAP) {
+				if (ho->neg_chap) {	/* we've already accepted CHAP */
+					LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE PAP already accepted\n"));
+					orc = CONFREJ;
+					break;
+				} else if (cilen != CILEN_SHORT) {
+					LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE PAP bad len\n"));
+					orc = CONFREJ;
+					break;
+				}
+				if (!ao->neg_upap) {	/* we don't want to do PAP */
+					LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE PAP not allowed\n"));
+					orc = CONFNAK;	/* NAK it and suggest CHAP */
+					PUTCHAR(CI_AUTHTYPE, nakp);
+					PUTCHAR(CILEN_CHAP, nakp);
+					PUTSHORT(PPP_CHAP, nakp);
+					PUTCHAR(ao->chap_mdtype, nakp);
+					break;
+				}
+				ho->neg_upap = 1;
+#if TRACELCP > 0
+				sprintf(&traceBuf[traceNdx], " PAP (%X)", cishort);
+				traceNdx = strlen(traceBuf);
+#endif
+				break;
+			}
+			if (cishort == PPP_CHAP) {
+				if (ho->neg_upap) {	/* we've already accepted PAP */
+					LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE CHAP accepted PAP\n"));
+					orc = CONFREJ;
+					break;
+				} else if (cilen != CILEN_CHAP) {
+					LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE CHAP bad len\n"));
+					orc = CONFREJ;
+					break;
+				}
+				if (!ao->neg_chap) {	/* we don't want to do CHAP */
+					LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE CHAP not allowed\n"));
+					orc = CONFNAK;	/* NAK it and suggest PAP */
+					PUTCHAR(CI_AUTHTYPE, nakp);
+					PUTCHAR(CILEN_SHORT, nakp);
+					PUTSHORT(PPP_PAP, nakp);
+					break;
+				}
+				GETCHAR(cichar, p);	/* get digest type*/
+				if (cichar != CHAP_DIGEST_MD5
+#ifdef CHAPMS
+						&& cichar != CHAP_MICROSOFT
+#endif
+				) {
+					LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE CHAP digest=%d\n", cichar));
+					orc = CONFNAK;
+					PUTCHAR(CI_AUTHTYPE, nakp);
+					PUTCHAR(CILEN_CHAP, nakp);
+					PUTSHORT(PPP_CHAP, nakp);
+					PUTCHAR(ao->chap_mdtype, nakp);
+					break;
+				}
+#if TRACELCP > 0
+				sprintf(&traceBuf[traceNdx], " CHAP %X,%d", cishort, cichar);
+				traceNdx = strlen(traceBuf);
+#endif
+				ho->chap_mdtype = cichar; /* save md type */
+				ho->neg_chap = 1;
+				break;
+			}
+			
+			/*
+			 * We don't recognize the protocol they're asking for.
+			 * Nak it with something we're willing to do.
+			 * (At this point we know ao->neg_upap || ao->neg_chap.)
+			 */
+			orc = CONFNAK;
+			PUTCHAR(CI_AUTHTYPE, nakp);
+			if (ao->neg_chap) {
+				LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE %d req CHAP\n", cishort));
+				PUTCHAR(CILEN_CHAP, nakp);
+				PUTSHORT(PPP_CHAP, nakp);
+				PUTCHAR(ao->chap_mdtype, nakp);
+			} 
+			else {
+				LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE %d req PAP\n", cishort));
+				PUTCHAR(CILEN_SHORT, nakp);
+				PUTSHORT(PPP_PAP, nakp);
+			}
+			break;
+		
+		case CI_QUALITY:
+			GETSHORT(cishort, p);
+			GETLONG(cilong, p);
+#if TRACELCP > 0
+			sprintf(&traceBuf[traceNdx], " QUALITY (%x %x)", cishort, (unsigned int) cilong);
+			traceNdx = strlen(traceBuf);
+#endif
+
+			if (!ao->neg_lqr ||
+					cilen != CILEN_LQR) {
+				orc = CONFREJ;
+				break;
+			}
+			
+			/*
+			 * Check the protocol and the reporting period.
+			 * XXX When should we Nak this, and what with?
+			 */
+			if (cishort != PPP_LQR) {
+				orc = CONFNAK;
+				PUTCHAR(CI_QUALITY, nakp);
+				PUTCHAR(CILEN_LQR, nakp);
+				PUTSHORT(PPP_LQR, nakp);
+				PUTLONG(ao->lqr_period, nakp);
+				break;
+			}
+			break;
+		
+		case CI_MAGICNUMBER:
+			if (!(ao->neg_magicnumber || go->neg_magicnumber) ||
+					cilen != CILEN_LONG) {
+				orc = CONFREJ;
+				break;
+			}
+			GETLONG(cilong, p);
+#if TRACELCP > 0
+			sprintf(&traceBuf[traceNdx], " MAGICNUMBER (%lX)", cilong);
+			traceNdx = strlen(traceBuf);
+#endif
+
+			/*
+			 * He must have a different magic number.
+			 */
+			if (go->neg_magicnumber &&
+					cilong == go->magicnumber) {
+				cilong = magic();	/* Don't put magic() inside macro! */
+				orc = CONFNAK;
+				PUTCHAR(CI_MAGICNUMBER, nakp);
+				PUTCHAR(CILEN_LONG, nakp);
+				PUTLONG(cilong, nakp);
+				break;
+			}
+			ho->neg_magicnumber = 1;
+			ho->magicnumber = cilong;
+			break;
+		
+		
+		case CI_PCOMPRESSION:
+#if TRACELCP > 0
+			sprintf(&traceBuf[traceNdx], " PCOMPRESSION");
+			traceNdx = strlen(traceBuf);
+#endif
+			if (!ao->neg_pcompression ||
+					cilen != CILEN_VOID) {
+				orc = CONFREJ;
+				break;
+			}
+			ho->neg_pcompression = 1;
+			break;
+		
+		case CI_ACCOMPRESSION:
+#if TRACELCP > 0
+			sprintf(&traceBuf[traceNdx], " ACCOMPRESSION");
+			traceNdx = strlen(traceBuf);
+#endif
+			if (!ao->neg_accompression ||
+					cilen != CILEN_VOID) {
+				orc = CONFREJ;
+				break;
+			}
+			ho->neg_accompression = 1;
+			break;
+		
+		case CI_MRRU:
+#if TRACELCP > 0
+			sprintf(&traceBuf[traceNdx], " CI_MRRU");
+			traceNdx = strlen(traceBuf);
+#endif
+			orc = CONFREJ;
+			break;
+		
+		case CI_SSNHF:
+#if TRACELCP > 0
+			sprintf(&traceBuf[traceNdx], " CI_SSNHF");
+			traceNdx = strlen(traceBuf);
+#endif
+			orc = CONFREJ;
+			break;
+		
+		case CI_EPDISC:
+#if TRACELCP > 0
+			sprintf(&traceBuf[traceNdx], " CI_EPDISC");
+			traceNdx = strlen(traceBuf);
+#endif
+			orc = CONFREJ;
+			break;
+		
+		default:
+#if TRACELCP
+			sprintf(&traceBuf[traceNdx], " unknown %d", citype);
+			traceNdx = strlen(traceBuf);
+#endif
+			orc = CONFREJ;
+			break;
+		}
+		
+	endswitch:
+#if TRACELCP
+		if (traceNdx >= 80 - 32) {
+			LCPDEBUG((LOG_INFO, "lcp_reqci: rcvd%s\n", traceBuf));
+			traceNdx = 0;
+		}
+#endif
+		if (orc == CONFACK &&		/* Good CI */
+				rc != CONFACK)		/*  but prior CI wasnt? */
+			continue;			/* Don't send this one */
+		
+		if (orc == CONFNAK) {		/* Nak this CI? */
+			if (reject_if_disagree	/* Getting fed up with sending NAKs? */
+					&& citype != CI_MAGICNUMBER) {
+				orc = CONFREJ;		/* Get tough if so */
+			} 
+			else {
+				if (rc == CONFREJ)	/* Rejecting prior CI? */
+					continue;		/* Don't send this one */
+				rc = CONFNAK;
+			}
+		}
+		if (orc == CONFREJ) {		/* Reject this CI */
+			rc = CONFREJ;
+			if (cip != rejp)		/* Need to move rejected CI? */
+				BCOPY(cip, rejp, cilen); /* Move it */
+			INCPTR(cilen, rejp);	/* Update output pointer */
+		}
+	}
+	
+	/*
+	 * If we wanted to send additional NAKs (for unsent CIs), the
+	 * code would go here.  The extra NAKs would go at *nakp.
+	 * At present there are no cases where we want to ask the
+	 * peer to negotiate an option.
+	 */
+	
+	switch (rc) {
+	case CONFACK:
+		*lenp = (int)(next - inp);
+		break;
+	case CONFNAK:
+		/*
+		 * Copy the Nak'd options from the nak_buffer to the caller's buffer.
+		 */
+		*lenp = (int)(nakp - nak_buffer);
+		BCOPY(nak_buffer, inp, *lenp);
+		break;
+	case CONFREJ:
+		*lenp = (int)(rejp - inp);
+		break;
+	}
+	
+#if TRACELCP > 0
+	if (traceNdx > 0) {
+		LCPDEBUG((LOG_INFO, "lcp_reqci: %s\n", traceBuf));
+	}
+#endif
+	LCPDEBUG((LOG_INFO, "lcp_reqci: returning CONF%s.\n", CODENAME(rc)));
+	return (rc);			/* Return final code */
+}
+
+
+/*
+ * lcp_up - LCP has come UP.
+ */
+static void lcp_up(fsm *f)
+{
+	lcp_options *wo = &lcp_wantoptions[f->unit];
+	lcp_options *ho = &lcp_hisoptions[f->unit];
+	lcp_options *go = &lcp_gotoptions[f->unit];
+	lcp_options *ao = &lcp_allowoptions[f->unit];
+	
+	if (!go->neg_magicnumber)
+		go->magicnumber = 0;
+	if (!ho->neg_magicnumber)
+		ho->magicnumber = 0;
+	
+	/*
+	* Set our MTU to the smaller of the MTU we wanted and
+	* the MRU our peer wanted.  If we negotiated an MRU,
+	* set our MRU to the larger of value we wanted and
+	* the value we got in the negotiation.
+	*/
+	ppp_send_config(f->unit, LWIP_MIN(ao->mru, (ho->neg_mru? ho->mru: PPP_MRU)),
+				(ho->neg_asyncmap? ho->asyncmap: 0xffffffffl),
+				ho->neg_pcompression, ho->neg_accompression);
+	/*
+	* If the asyncmap hasn't been negotiated, we really should
+	* set the receive asyncmap to ffffffff, but we set it to 0
+	* for backwards contemptibility.
+	*/
+	ppp_recv_config(f->unit, (go->neg_mru? LWIP_MAX(wo->mru, go->mru): PPP_MRU),
+				(go->neg_asyncmap? go->asyncmap: 0x00000000),
+				go->neg_pcompression, go->neg_accompression);
+	
+	if (ho->neg_mru)
+		peer_mru[f->unit] = ho->mru;
+	
+	lcp_echo_lowerup(f->unit);  /* Enable echo messages */
+	
+	link_established(f->unit);
+}
+
+
+/*
+ * lcp_down - LCP has gone DOWN.
+ *
+ * Alert other protocols.
+ */
+static void lcp_down(fsm *f)
+{
+	lcp_options *go = &lcp_gotoptions[f->unit];
+	
+	lcp_echo_lowerdown(f->unit);
+	
+	link_down(f->unit);
+	
+	ppp_send_config(f->unit, PPP_MRU, 0xffffffffl, 0, 0);
+	ppp_recv_config(f->unit, PPP_MRU,
+				(go->neg_asyncmap? go->asyncmap: 0x00000000),
+				go->neg_pcompression, go->neg_accompression);
+	peer_mru[f->unit] = PPP_MRU;
+}
+
+
+/*
+ * lcp_starting - LCP needs the lower layer up.
+ */
+static void lcp_starting(fsm *f)
+{
+	link_required(f->unit);
+}
+
+
+/*
+ * lcp_finished - LCP has finished with the lower layer.
+ */
+static void lcp_finished(fsm *f)
+{
+	link_terminated(f->unit);
+}
+
+
+#if 0
+/*
+ * print_string - print a readable representation of a string using
+ * printer.
+ */
+static void print_string(
+    char *p,
+    int len,
+    void (*printer) (void *, char *, ...),
+    void *arg
+)
+{
+    int c;
+    
+    printer(arg, "\"");
+    for (; len > 0; --len) {
+        c = *p++;
+        if (' ' <= c && c <= '~') {
+            if (c == '\\' || c == '"')
+                printer(arg, "\\");
+            printer(arg, "%c", c);
+        } else {
+            switch (c) {
+            case '\n':
+                printer(arg, "\\n");
+                break;
+            case '\r':
+                printer(arg, "\\r");
+                break;
+            case '\t':
+                printer(arg, "\\t");
+                break;
+            default:
+                printer(arg, "\\%.3o", c);
+            }
+        }
+    }
+    printer(arg, "\"");
+}
+
+
+/*
+ * lcp_printpkt - print the contents of an LCP packet.
+ */
+static char *lcp_codenames[] = {
+	"ConfReq", "ConfAck", "ConfNak", "ConfRej",
+	"TermReq", "TermAck", "CodeRej", "ProtRej",
+	"EchoReq", "EchoRep", "DiscReq"
+};
+
+static int lcp_printpkt(
+	u_char *p,
+	int plen,
+	void (*printer) (void *, char *, ...),
+	void *arg
+)
+{
+	int code, id, len, olen;
+	u_char *pstart, *optend;
+	u_short cishort;
+	u32_t cilong;
+	
+	if (plen < HEADERLEN)
+		return 0;
+	pstart = p;
+	GETCHAR(code, p);
+	GETCHAR(id, p);
+	GETSHORT(len, p);
+	if (len < HEADERLEN || len > plen)
+		return 0;
+	
+	if (code >= 1 && code <= sizeof(lcp_codenames) / sizeof(char *))
+		printer(arg, " %s", lcp_codenames[code-1]);
+	else
+		printer(arg, " code=0x%x", code);
+	printer(arg, " id=0x%x", id);
+	len -= HEADERLEN;
+	switch (code) {
+	case CONFREQ:
+	case CONFACK:
+	case CONFNAK:
+	case CONFREJ:
+		/* print option list */
+		while (len >= 2) {
+			GETCHAR(code, p);
+			GETCHAR(olen, p);
+			p -= 2;
+			if (olen < 2 || olen > len) {
+				break;
+			}
+			printer(arg, " <");
+			len -= olen;
+			optend = p + olen;
+			switch (code) {
+			case CI_MRU:
+				if (olen == CILEN_SHORT) {
+					p += 2;
+					GETSHORT(cishort, p);
+					printer(arg, "mru %d", cishort);
+				}
+				break;
+			case CI_ASYNCMAP:
+				if (olen == CILEN_LONG) {
+					p += 2;
+					GETLONG(cilong, p);
+					printer(arg, "asyncmap 0x%lx", cilong);
+				}
+				break;
+			case CI_AUTHTYPE:
+				if (olen >= CILEN_SHORT) {
+					p += 2;
+					printer(arg, "auth ");
+					GETSHORT(cishort, p);
+					switch (cishort) {
+					case PPP_PAP:
+						printer(arg, "pap");
+						break;
+					case PPP_CHAP:
+						printer(arg, "chap");
+						break;
+					default:
+						printer(arg, "0x%x", cishort);
+					}
+				}
+				break;
+			case CI_QUALITY:
+				if (olen >= CILEN_SHORT) {
+					p += 2;
+					printer(arg, "quality ");
+					GETSHORT(cishort, p);
+					switch (cishort) {
+					case PPP_LQR:
+						printer(arg, "lqr");
+						break;
+					default:
+						printer(arg, "0x%x", cishort);
+					}
+				}
+				break;
+			case CI_CALLBACK:
+				if (olen >= CILEN_CHAR) {
+					p += 2;
+					printer(arg, "callback ");
+					GETSHORT(cishort, p);
+					switch (cishort) {
+					case CBCP_OPT:
+						printer(arg, "CBCP");
+						break;
+					default:
+						printer(arg, "0x%x", cishort);
+					}
+				}
+				break;
+			case CI_MAGICNUMBER:
+				if (olen == CILEN_LONG) {
+					p += 2;
+					GETLONG(cilong, p);
+					printer(arg, "magic 0x%x", cilong);
+				}
+				break;
+			case CI_PCOMPRESSION:
+				if (olen == CILEN_VOID) {
+					p += 2;
+					printer(arg, "pcomp");
+				}
+				break;
+			case CI_ACCOMPRESSION:
+				if (olen == CILEN_VOID) {
+					p += 2;
+					printer(arg, "accomp");
+				}
+				break;
+			}
+			while (p < optend) {
+				GETCHAR(code, p);
+				printer(arg, " %.2x", code);
+			}
+			printer(arg, ">");
+		}
+		break;
+	
+	case TERMACK:
+	case TERMREQ:
+		if (len > 0 && *p >= ' ' && *p < 0x7f) {
+			printer(arg, " ");
+			print_string((char*)p, len, printer, arg);
+			p += len;
+			len = 0;
+		}
+		break;
+	
+	case ECHOREQ:
+	case ECHOREP:
+	case DISCREQ:
+		if (len >= 4) {
+			GETLONG(cilong, p);
+			printer(arg, " magic=0x%x", cilong);
+			p += 4;
+			len -= 4;
+		}
+		break;
+	}
+	
+	/* print the rest of the bytes in the packet */
+	for (; len > 0; --len) {
+		GETCHAR(code, p);
+		printer(arg, " %.2x", code);
+	}
+	
+	return (int)(p - pstart);
+}
+#endif
+
+/*
+ * Time to shut down the link because there is nothing out there.
+ */
+
+static void LcpLinkFailure (fsm *f)
+{
+	if (f->state == OPENED) {
+		LCPDEBUG((LOG_INFO, "No response to %d echo-requests\n", lcp_echos_pending));
+		LCPDEBUG((LOG_NOTICE, "Serial link appears to be disconnected.\n"));
+		lcp_close(f->unit, "Peer not responding");
+	}
+}
+
+/*
+ * Timer expired for the LCP echo requests from this process.
+ */
+
+static void LcpEchoCheck (fsm *f)
+{
+	LcpSendEchoRequest (f);
+	
+	/*
+	 * Start the timer for the next interval.
+	 */
+	LWIP_ASSERT("lcp_echo_timer_running == 0", lcp_echo_timer_running == 0);
+
+	TIMEOUT (LcpEchoTimeout, f, lcp_echo_interval);
+	lcp_echo_timer_running = 1;
+}
+
+/*
+ * LcpEchoTimeout - Timer expired on the LCP echo
+ */
+
+static void LcpEchoTimeout (void *arg)
+{
+	if (lcp_echo_timer_running != 0) {
+		lcp_echo_timer_running = 0;
+		LcpEchoCheck ((fsm *) arg);
+	}
+}
+
+/*
+ * LcpEchoReply - LCP has received a reply to the echo
+ */
+static void lcp_received_echo_reply (fsm *f, int id, u_char *inp, int len)
+{
+	u32_t magic;
+	
+	(void)id;
+
+	/* Check the magic number - don't count replies from ourselves. */
+	if (len < 4) {
+		LCPDEBUG((LOG_WARNING, "lcp: received short Echo-Reply, length %d\n", len));
+		return;
+	}
+	GETLONG(magic, inp);
+	if (lcp_gotoptions[f->unit].neg_magicnumber
+			&& magic == lcp_gotoptions[f->unit].magicnumber) {
+		LCPDEBUG((LOG_WARNING, "appear to have received our own echo-reply!\n"));
+		return;
+	}
+	
+	/* Reset the number of outstanding echo frames */
+	lcp_echos_pending = 0;
+}
+
+/*
+ * LcpSendEchoRequest - Send an echo request frame to the peer
+ */
+
+static void LcpSendEchoRequest (fsm *f)
+{
+	u32_t lcp_magic;
+	u_char pkt[4], *pktp;
+	
+	/*
+	* Detect the failure of the peer at this point.
+	*/
+	if (lcp_echo_fails != 0) {
+		if (lcp_echos_pending++ >= lcp_echo_fails) {
+			LcpLinkFailure(f);
+			lcp_echos_pending = 0;
+		}
+	}
+	
+	/*
+	* Make and send the echo request frame.
+	*/
+	if (f->state == OPENED) {
+		lcp_magic = lcp_gotoptions[f->unit].magicnumber;
+		pktp = pkt;
+		PUTLONG(lcp_magic, pktp);
+		fsm_sdata(f, ECHOREQ, (u_char)(lcp_echo_number++ & 0xFF), pkt, (int)(pktp - pkt));
+	}
+}
+
+/*
+ * lcp_echo_lowerup - Start the timer for the LCP frame
+ */
+
+static void lcp_echo_lowerup (int unit)
+{
+	fsm *f = &lcp_fsm[unit];
+	
+	/* Clear the parameters for generating echo frames */
+	lcp_echos_pending      = 0;
+	lcp_echo_number        = 0;
+	lcp_echo_timer_running = 0;
+	
+	/* If a timeout interval is specified then start the timer */
+	if (lcp_echo_interval != 0)
+		LcpEchoCheck (f);
+}
+
+/*
+ * lcp_echo_lowerdown - Stop the timer for the LCP frame
+ */
+
+static void lcp_echo_lowerdown (int unit)
+{
+	fsm *f = &lcp_fsm[unit];
+	
+	if (lcp_echo_timer_running != 0) {
+		UNTIMEOUT (LcpEchoTimeout, f);
+		lcp_echo_timer_running = 0;
+	}
+}
+
+#endif /* PPP_SUPPORT */
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/lcp.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/lcp.h
new file mode 100644
index 000000000..2c0c34007
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/lcp.h
@@ -0,0 +1,169 @@
+/*****************************************************************************
+* lcp.h - Network Link Control Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-11-05 Guy Lancaster , Global Election Systems Inc.
+*	Original derived from BSD codes.
+*****************************************************************************/
+/*
+ * lcp.h - Link Control Protocol definitions.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * $Id: lcp.h,v 1.1 2003/05/27 14:37:56 jani Exp $
+ */
+
+#ifndef LCP_H
+#define LCP_H
+
+
+/*************************
+*** PUBLIC DEFINITIONS ***
+*************************/
+/*
+ * Options.
+ */
+#define CI_MRU		1	/* Maximum Receive Unit */
+#define CI_ASYNCMAP	2	/* Async Control Character Map */
+#define CI_AUTHTYPE	3	/* Authentication Type */
+#define CI_QUALITY	4	/* Quality Protocol */
+#define CI_MAGICNUMBER	5	/* Magic Number */
+#define CI_PCOMPRESSION	7	/* Protocol Field Compression */
+#define CI_ACCOMPRESSION 8	/* Address/Control Field Compression */
+#define CI_CALLBACK	13	/* callback */
+#define CI_MRRU		17	/* max reconstructed receive unit; multilink */
+#define CI_SSNHF	18	/* short sequence numbers for multilink */
+#define CI_EPDISC	19	/* endpoint discriminator */
+
+/*
+ * LCP-specific packet types.
+ */
+#define PROTREJ		8	/* Protocol Reject */
+#define ECHOREQ		9	/* Echo Request */
+#define ECHOREP		10	/* Echo Reply */
+#define DISCREQ		11	/* Discard Request */
+#define CBCP_OPT	6	/* Use callback control protocol */
+
+
+/************************
+*** PUBLIC DATA TYPES ***
+************************/
+
+/*
+ * The state of options is described by an lcp_options structure.
+ */
+typedef struct lcp_options {
+    u_int passive : 1;			/* Don't die if we don't get a response */
+    u_int silent : 1;				/* Wait for the other end to start first */
+    u_int restart : 1;			/* Restart vs. exit after close */
+    u_int neg_mru : 1;			/* Negotiate the MRU? */
+    u_int neg_asyncmap : 1;		/* Negotiate the async map? */
+    u_int neg_upap : 1;			/* Ask for UPAP authentication? */
+    u_int neg_chap : 1;			/* Ask for CHAP authentication? */
+    u_int neg_magicnumber : 1;	/* Ask for magic number? */
+    u_int neg_pcompression : 1;	/* HDLC Protocol Field Compression? */
+    u_int neg_accompression : 1;	/* HDLC Address/Control Field Compression? */
+    u_int neg_lqr : 1;			/* Negotiate use of Link Quality Reports */
+    u_int neg_cbcp : 1;			/* Negotiate use of CBCP */
+#ifdef PPP_MULTILINK
+    u_int neg_mrru : 1;			/* Negotiate multilink MRRU */
+    u_int neg_ssnhf : 1;		/* Negotiate short sequence numbers */
+    u_int neg_endpoint : 1;		/* Negotiate endpoint discriminator */
+#endif
+    u_short mru;			/* Value of MRU */
+#ifdef PPP_MULTILINK
+    u_short mrru;			/* Value of MRRU, and multilink enable */
+#endif
+    u_char chap_mdtype;			/* which MD type (hashing algorithm) */
+    u32_t asyncmap;			/* Value of async map */
+    u32_t magicnumber;
+    int numloops;				/* Number of loops during magic number neg. */
+    u32_t lqr_period;		/* Reporting period for LQR 1/100ths second */
+#ifdef PPP_MULTILINK
+    struct epdisc endpoint;	/* endpoint discriminator */
+#endif
+} lcp_options;
+
+/*
+ * Values for phase from BSD pppd.h based on RFC 1661.
+ */
+typedef enum {
+	PHASE_DEAD = 0,
+	PHASE_INITIALIZE,
+	PHASE_ESTABLISH,
+	PHASE_AUTHENTICATE,
+	PHASE_CALLBACK,
+	PHASE_NETWORK,
+	PHASE_TERMINATE
+} LinkPhase;
+
+
+/*****************************
+*** PUBLIC DATA STRUCTURES ***
+*****************************/
+
+extern LinkPhase lcp_phase[NUM_PPP];	/* Phase of link session (RFC 1661) */
+extern lcp_options lcp_wantoptions[];
+extern lcp_options lcp_gotoptions[];
+extern lcp_options lcp_allowoptions[];
+extern lcp_options lcp_hisoptions[];
+extern ext_accm xmit_accm[];
+
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+
+void lcp_init (int);
+void lcp_open (int);
+void lcp_close (int, char *);
+void lcp_lowerup (int);
+void lcp_lowerdown (int);
+void lcp_sprotrej (int, u_char *, int);	/* send protocol reject */
+
+extern struct protent lcp_protent;
+
+/* Default number of times we receive our magic number from the peer
+   before deciding the link is looped-back. */
+#define DEFLOOPBACKFAIL	10
+
+#endif /* LCP_H */
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/magic.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/magic.c
new file mode 100644
index 000000000..6e9d47538
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/magic.c
@@ -0,0 +1,79 @@
+/*****************************************************************************
+* magic.c - Network Random Number Generator program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-04 Guy Lancaster , Global Election Systems Inc.
+*	Original based on BSD magic.c.
+*****************************************************************************/
+/*
+ * magic.c - PPP Magic Number routines.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include "ppp.h"
+#include "randm.h"
+#include "magic.h"
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ * magicInit - Initialize the magic number generator.
+ *
+ * Since we use another random number generator that has its own
+ * initialization, we do nothing here.
+ */
+void magicInit()
+{
+	return;
+}
+
+/*
+ * magic - Returns the next magic number.
+ */
+u32_t magic()
+{
+    return avRandom();
+}
+
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/magic.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/magic.h
new file mode 100644
index 000000000..6e9b10b58
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/magic.h
@@ -0,0 +1,64 @@
+/*****************************************************************************
+* magic.h - Network Random Number Generator header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-04 Guy Lancaster , Global Election Systems Inc.
+*   Original derived from BSD codes.
+*****************************************************************************/
+/*
+ * magic.h - PPP Magic Number definitions.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * $Id: magic.h,v 1.1 2003/05/27 14:37:56 jani Exp $
+ */
+
+#ifndef MAGIC_H
+#define MAGIC_H
+
+/*****************************************************************************
+************************** PUBLIC FUNCTIONS **********************************
+*****************************************************************************/
+
+void magicInit(void);   /* Initialize the magic number generator */
+u32_t magic(void);  /* Returns the next magic number */
+
+#endif /* MAGIC_H */
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/md5.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/md5.c
new file mode 100644
index 000000000..488d64af5
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/md5.c
@@ -0,0 +1,306 @@
+/*
+ ***********************************************************************
+ ** md5.c -- the source code for MD5 routines                         **
+ ** RSA Data Security, Inc. MD5 Message-Digest Algorithm              **
+ ** Created: 2/17/90 RLR                                              **
+ ** Revised: 1/91 SRD,AJ,BSK,JT Reference C ver., 7/10 constant corr. **
+ ***********************************************************************
+ */
+
+/*
+ ***********************************************************************
+ ** Copyright (C) 1990, RSA Data Security, Inc. All rights reserved.  **
+ **                                                                   **
+ ** License to copy and use this software is granted provided that    **
+ ** it is identified as the "RSA Data Security, Inc. MD5 Message-     **
+ ** Digest Algorithm" in all material mentioning or referencing this  **
+ ** software or this function.                                        **
+ **                                                                   **
+ ** License is also granted to make and use derivative works          **
+ ** provided that such works are identified as "derived from the RSA  **
+ ** Data Security, Inc. MD5 Message-Digest Algorithm" in all          **
+ ** material mentioning or referencing the derived work.              **
+ **                                                                   **
+ ** RSA Data Security, Inc. makes no representations concerning       **
+ ** either the merchantability of this software or the suitability    **
+ ** of this software for any particular purpose.  It is provided "as  **
+ ** is" without express or implied warranty of any kind.              **
+ **                                                                   **
+ ** These notices must be retained in any copies of any part of this  **
+ ** documentation and/or software.                                    **
+ ***********************************************************************
+ */
+
+#include "ppp.h"
+#include "md5.h"
+#include "pppdebug.h"
+
+#if CHAP_SUPPORT > 0 || MD5_SUPPORT > 0
+
+/*
+ ***********************************************************************
+ **  Message-digest routines:                                         **
+ **  To form the message digest for a message M                       **
+ **    (1) Initialize a context buffer mdContext using MD5Init        **
+ **    (2) Call MD5Update on mdContext and M                          **
+ **    (3) Call MD5Final on mdContext                                 **
+ **  The message digest is now in mdContext->digest[0...15]           **
+ ***********************************************************************
+ */
+
+/* forward declaration */
+static void Transform (u32_t *buf, u32_t *in);
+
+static unsigned char PADDING[64] = {
+  0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+/* F, G, H and I are basic MD5 functions */
+#define F(x, y, z) (((x) & (y)) | ((~x) & (z)))
+#define G(x, y, z) (((x) & (z)) | ((y) & (~z)))
+#define H(x, y, z) ((x) ^ (y) ^ (z))
+#define I(x, y, z) ((y) ^ ((x) | (~z)))
+
+/* ROTATE_LEFT rotates x left n bits */
+#define ROTATE_LEFT(x, n) (((x) << (n)) | ((x) >> (32-(n))))
+
+/* FF, GG, HH, and II transformations for rounds 1, 2, 3, and 4 */
+/* Rotation is separate from addition to prevent recomputation */
+#define FF(a, b, c, d, x, s, ac) \
+  {(a) += F ((b), (c), (d)) + (x) + (u32_t)(ac); \
+   (a) = ROTATE_LEFT ((a), (s)); \
+   (a) += (b); \
+  }
+#define GG(a, b, c, d, x, s, ac) \
+  {(a) += G ((b), (c), (d)) + (x) + (u32_t)(ac); \
+   (a) = ROTATE_LEFT ((a), (s)); \
+   (a) += (b); \
+  }
+#define HH(a, b, c, d, x, s, ac) \
+  {(a) += H ((b), (c), (d)) + (x) + (u32_t)(ac); \
+   (a) = ROTATE_LEFT ((a), (s)); \
+   (a) += (b); \
+  }
+#define II(a, b, c, d, x, s, ac) \
+  {(a) += I ((b), (c), (d)) + (x) + (u32_t)(ac); \
+   (a) = ROTATE_LEFT ((a), (s)); \
+   (a) += (b); \
+  }
+
+#ifdef __STDC__
+#define UL(x)	x##UL
+#else
+#ifdef WIN32
+#define UL(x)	x##UL
+#else
+#define UL(x)	x
+#endif
+#endif
+
+/* The routine MD5Init initializes the message-digest context
+   mdContext. All fields are set to zero.
+ */
+void MD5Init (MD5_CTX *mdContext)
+{
+  mdContext->i[0] = mdContext->i[1] = (u32_t)0;
+
+  /* Load magic initialization constants.
+   */
+  mdContext->buf[0] = (u32_t)0x67452301UL;
+  mdContext->buf[1] = (u32_t)0xefcdab89UL;
+  mdContext->buf[2] = (u32_t)0x98badcfeUL;
+  mdContext->buf[3] = (u32_t)0x10325476UL;
+}
+
+/* The routine MD5Update updates the message-digest context to
+   account for the presence of each of the characters inBuf[0..inLen-1]
+   in the message whose digest is being computed.
+ */
+void MD5Update(MD5_CTX *mdContext, unsigned char *inBuf, unsigned int inLen)
+{
+  u32_t in[16];
+  int mdi;
+  unsigned int i, ii;
+
+#if 0
+  ppp_trace(LOG_INFO, "MD5Update: %u:%.*H\n", inLen, MIN(inLen, 20) * 2, inBuf);
+  ppp_trace(LOG_INFO, "MD5Update: %u:%s\n", inLen, inBuf);
+#endif
+  
+  /* compute number of bytes mod 64 */
+  mdi = (int)((mdContext->i[0] >> 3) & 0x3F);
+
+  /* update number of bits */
+  if ((mdContext->i[0] + ((u32_t)inLen << 3)) < mdContext->i[0])
+    mdContext->i[1]++;
+  mdContext->i[0] += ((u32_t)inLen << 3);
+  mdContext->i[1] += ((u32_t)inLen >> 29);
+
+  while (inLen--) {
+    /* add new character to buffer, increment mdi */
+    mdContext->in[mdi++] = *inBuf++;
+
+    /* transform if necessary */
+    if (mdi == 0x40) {
+      for (i = 0, ii = 0; i < 16; i++, ii += 4)
+        in[i] = (((u32_t)mdContext->in[ii+3]) << 24) |
+                (((u32_t)mdContext->in[ii+2]) << 16) |
+				(((u32_t)mdContext->in[ii+1]) << 8) |
+                ((u32_t)mdContext->in[ii]);
+      Transform (mdContext->buf, in);
+      mdi = 0;
+    }
+  }
+}
+
+/* The routine MD5Final terminates the message-digest computation and
+   ends with the desired message digest in mdContext->digest[0...15].
+ */
+void MD5Final (unsigned char hash[], MD5_CTX *mdContext)
+{
+  u32_t in[16];
+  int mdi;
+  unsigned int i, ii;
+  unsigned int padLen;
+
+  /* save number of bits */
+  in[14] = mdContext->i[0];
+  in[15] = mdContext->i[1];
+
+  /* compute number of bytes mod 64 */
+  mdi = (int)((mdContext->i[0] >> 3) & 0x3F);
+
+  /* pad out to 56 mod 64 */
+  padLen = (mdi < 56) ? (56 - mdi) : (120 - mdi);
+  MD5Update (mdContext, PADDING, padLen);
+
+  /* append length in bits and transform */
+  for (i = 0, ii = 0; i < 14; i++, ii += 4)
+    in[i] = (((u32_t)mdContext->in[ii+3]) << 24) |
+            (((u32_t)mdContext->in[ii+2]) << 16) |
+            (((u32_t)mdContext->in[ii+1]) << 8) |
+            ((u32_t)mdContext->in[ii]);
+  Transform (mdContext->buf, in);
+
+  /* store buffer in digest */
+  for (i = 0, ii = 0; i < 4; i++, ii += 4) {
+    mdContext->digest[ii] = (unsigned char)(mdContext->buf[i] & 0xFF);
+	mdContext->digest[ii+1] =
+      (unsigned char)((mdContext->buf[i] >> 8) & 0xFF);
+    mdContext->digest[ii+2] =
+      (unsigned char)((mdContext->buf[i] >> 16) & 0xFF);
+    mdContext->digest[ii+3] =
+      (unsigned char)((mdContext->buf[i] >> 24) & 0xFF);
+  }
+  memcpy(hash, mdContext->digest, 16);
+}
+
+/* Basic MD5 step. Transforms buf based on in.
+ */
+static void Transform (u32_t *buf, u32_t *in)
+{
+  u32_t a = buf[0], b = buf[1], c = buf[2], d = buf[3];
+
+  /* Round 1 */
+#define S11 7
+#define S12 12
+#define S13 17
+#define S14 22
+  FF ( a, b, c, d, in[ 0], S11, UL(3614090360)); /* 1 */
+  FF ( d, a, b, c, in[ 1], S12, UL(3905402710)); /* 2 */
+  FF ( c, d, a, b, in[ 2], S13, UL( 606105819)); /* 3 */
+  FF ( b, c, d, a, in[ 3], S14, UL(3250441966)); /* 4 */
+  FF ( a, b, c, d, in[ 4], S11, UL(4118548399)); /* 5 */
+  FF ( d, a, b, c, in[ 5], S12, UL(1200080426)); /* 6 */
+  FF ( c, d, a, b, in[ 6], S13, UL(2821735955)); /* 7 */
+  FF ( b, c, d, a, in[ 7], S14, UL(4249261313)); /* 8 */
+  FF ( a, b, c, d, in[ 8], S11, UL(1770035416)); /* 9 */
+  FF ( d, a, b, c, in[ 9], S12, UL(2336552879)); /* 10 */
+  FF ( c, d, a, b, in[10], S13, UL(4294925233)); /* 11 */
+  FF ( b, c, d, a, in[11], S14, UL(2304563134)); /* 12 */
+  FF ( a, b, c, d, in[12], S11, UL(1804603682)); /* 13 */
+  FF ( d, a, b, c, in[13], S12, UL(4254626195)); /* 14 */
+  FF ( c, d, a, b, in[14], S13, UL(2792965006)); /* 15 */
+  FF ( b, c, d, a, in[15], S14, UL(1236535329)); /* 16 */
+
+  /* Round 2 */
+#define S21 5
+#define S22 9
+#define S23 14
+#define S24 20
+  GG ( a, b, c, d, in[ 1], S21, UL(4129170786)); /* 17 */
+  GG ( d, a, b, c, in[ 6], S22, UL(3225465664)); /* 18 */
+  GG ( c, d, a, b, in[11], S23, UL( 643717713)); /* 19 */
+  GG ( b, c, d, a, in[ 0], S24, UL(3921069994)); /* 20 */
+  GG ( a, b, c, d, in[ 5], S21, UL(3593408605)); /* 21 */
+  GG ( d, a, b, c, in[10], S22, UL(  38016083)); /* 22 */
+  GG ( c, d, a, b, in[15], S23, UL(3634488961)); /* 23 */
+  GG ( b, c, d, a, in[ 4], S24, UL(3889429448)); /* 24 */
+  GG ( a, b, c, d, in[ 9], S21, UL( 568446438)); /* 25 */
+  GG ( d, a, b, c, in[14], S22, UL(3275163606)); /* 26 */
+  GG ( c, d, a, b, in[ 3], S23, UL(4107603335)); /* 27 */
+  GG ( b, c, d, a, in[ 8], S24, UL(1163531501)); /* 28 */
+  GG ( a, b, c, d, in[13], S21, UL(2850285829)); /* 29 */
+  GG ( d, a, b, c, in[ 2], S22, UL(4243563512)); /* 30 */
+  GG ( c, d, a, b, in[ 7], S23, UL(1735328473)); /* 31 */
+  GG ( b, c, d, a, in[12], S24, UL(2368359562)); /* 32 */
+
+  /* Round 3 */
+#define S31 4
+#define S32 11
+#define S33 16
+#define S34 23
+  HH ( a, b, c, d, in[ 5], S31, UL(4294588738)); /* 33 */
+  HH ( d, a, b, c, in[ 8], S32, UL(2272392833)); /* 34 */
+  HH ( c, d, a, b, in[11], S33, UL(1839030562)); /* 35 */
+  HH ( b, c, d, a, in[14], S34, UL(4259657740)); /* 36 */
+  HH ( a, b, c, d, in[ 1], S31, UL(2763975236)); /* 37 */
+  HH ( d, a, b, c, in[ 4], S32, UL(1272893353)); /* 38 */
+  HH ( c, d, a, b, in[ 7], S33, UL(4139469664)); /* 39 */
+  HH ( b, c, d, a, in[10], S34, UL(3200236656)); /* 40 */
+  HH ( a, b, c, d, in[13], S31, UL( 681279174)); /* 41 */
+  HH ( d, a, b, c, in[ 0], S32, UL(3936430074)); /* 42 */
+  HH ( c, d, a, b, in[ 3], S33, UL(3572445317)); /* 43 */
+  HH ( b, c, d, a, in[ 6], S34, UL(  76029189)); /* 44 */
+  HH ( a, b, c, d, in[ 9], S31, UL(3654602809)); /* 45 */
+  HH ( d, a, b, c, in[12], S32, UL(3873151461)); /* 46 */
+  HH ( c, d, a, b, in[15], S33, UL( 530742520)); /* 47 */
+  HH ( b, c, d, a, in[ 2], S34, UL(3299628645)); /* 48 */
+
+  /* Round 4 */
+#define S41 6
+#define S42 10
+#define S43 15
+#define S44 21
+  II ( a, b, c, d, in[ 0], S41, UL(4096336452)); /* 49 */
+  II ( d, a, b, c, in[ 7], S42, UL(1126891415)); /* 50 */
+  II ( c, d, a, b, in[14], S43, UL(2878612391)); /* 51 */
+  II ( b, c, d, a, in[ 5], S44, UL(4237533241)); /* 52 */
+  II ( a, b, c, d, in[12], S41, UL(1700485571)); /* 53 */
+  II ( d, a, b, c, in[ 3], S42, UL(2399980690)); /* 54 */
+  II ( c, d, a, b, in[10], S43, UL(4293915773)); /* 55 */
+  II ( b, c, d, a, in[ 1], S44, UL(2240044497)); /* 56 */
+  II ( a, b, c, d, in[ 8], S41, UL(1873313359)); /* 57 */
+  II ( d, a, b, c, in[15], S42, UL(4264355552)); /* 58 */
+  II ( c, d, a, b, in[ 6], S43, UL(2734768916)); /* 59 */
+  II ( b, c, d, a, in[13], S44, UL(1309151649)); /* 60 */
+  II ( a, b, c, d, in[ 4], S41, UL(4149444226)); /* 61 */
+  II ( d, a, b, c, in[11], S42, UL(3174756917)); /* 62 */
+  II ( c, d, a, b, in[ 2], S43, UL( 718787259)); /* 63 */
+  II ( b, c, d, a, in[ 9], S44, UL(3951481745)); /* 64 */
+
+  buf[0] += a;
+  buf[1] += b;
+  buf[2] += c;
+  buf[3] += d;
+}
+
+#endif
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/md5.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/md5.h
new file mode 100644
index 000000000..83d318cfb
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/md5.h
@@ -0,0 +1,55 @@
+/*
+ ***********************************************************************
+ ** md5.h -- header file for implementation of MD5                    **
+ ** RSA Data Security, Inc. MD5 Message-Digest Algorithm              **
+ ** Created: 2/17/90 RLR                                              **
+ ** Revised: 12/27/90 SRD,AJ,BSK,JT Reference C version               **
+ ** Revised (for MD5): RLR 4/27/91                                    **
+ **   -- G modified to have y&~z instead of y&z                       **
+ **   -- FF, GG, HH modified to add in last register done             **
+ **   -- Access pattern: round 2 works mod 5, round 3 works mod 3     **
+ **   -- distinct additive constant for each step                     **
+ **   -- round 4 added, working mod 7                                 **
+ ***********************************************************************
+ */
+
+/*
+ ***********************************************************************
+ ** Copyright (C) 1990, RSA Data Security, Inc. All rights reserved.  **
+ **                                                                   **
+ ** License to copy and use this software is granted provided that    **
+ ** it is identified as the "RSA Data Security, Inc. MD5 Message-     **
+ ** Digest Algorithm" in all material mentioning or referencing this  **
+ ** software or this function.                                        **
+ **                                                                   **
+ ** License is also granted to make and use derivative works          **
+ ** provided that such works are identified as "derived from the RSA  **
+ ** Data Security, Inc. MD5 Message-Digest Algorithm" in all          **
+ ** material mentioning or referencing the derived work.              **
+ **                                                                   **
+ ** RSA Data Security, Inc. makes no representations concerning       **
+ ** either the merchantability of this software or the suitability    **
+ ** of this software for any particular purpose.  It is provided "as  **
+ ** is" without express or implied warranty of any kind.              **
+ **                                                                   **
+ ** These notices must be retained in any copies of any part of this  **
+ ** documentation and/or software.                                    **
+ ***********************************************************************
+ */
+
+#ifndef MD5_H
+#define MD5_H
+
+/* Data structure for MD5 (Message-Digest) computation */
+typedef struct {
+  u32_t i[2];                   /* number of _bits_ handled mod 2^64 */
+  u32_t buf[4];                                    /* scratch buffer */
+  unsigned char in[64];                              /* input buffer */
+  unsigned char digest[16];     /* actual digest after MD5Final call */
+} MD5_CTX;
+
+void MD5Init (MD5_CTX *mdContext);
+void MD5Update (MD5_CTX *mdContext, unsigned char *inBuf, unsigned int inLen);
+void MD5Final (unsigned char hash[], MD5_CTX *mdContext);
+
+#endif /* MD5_H */
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/pap.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/pap.c
new file mode 100644
index 000000000..4b105ef3e
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/pap.c
@@ -0,0 +1,608 @@
+/*****************************************************************************
+* pap.c - Network Password Authentication Protocol program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-12 Guy Lancaster , Global Election Systems Inc.
+*	Original.
+*****************************************************************************/
+/*
+ * upap.c - User/Password Authentication Protocol.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include "ppp.h"
+#include "auth.h"
+#include "pap.h"
+#include "pppdebug.h"
+
+
+#if PAP_SUPPORT > 0
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+/*
+ * Protocol entry points.
+ */
+static void upap_init (int);
+static void upap_lowerup (int);
+static void upap_lowerdown (int);
+static void upap_input (int, u_char *, int);
+static void upap_protrej (int);
+
+static void upap_timeout (void *);
+static void upap_reqtimeout (void *);
+static void upap_rauthreq (upap_state *, u_char *, int, int);
+static void upap_rauthack (upap_state *, u_char *, int, int);
+static void upap_rauthnak (upap_state *, u_char *, int, int);
+static void upap_sauthreq (upap_state *);
+static void upap_sresp (upap_state *, u_char, u_char, char *, int);
+
+
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+struct protent pap_protent = {
+    PPP_PAP,
+    upap_init,
+    upap_input,
+    upap_protrej,
+    upap_lowerup,
+    upap_lowerdown,
+    NULL,
+    NULL,
+#if 0
+    upap_printpkt,
+    NULL,
+#endif
+    1,
+    "PAP",
+#if 0
+    NULL,
+    NULL,
+    NULL
+#endif
+};
+
+upap_state upap[NUM_PPP];		/* UPAP state; one for each unit */
+
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ *  Set the default login name and password for the pap sessions
+ */
+void upap_setloginpasswd(int unit, const char *luser, const char *lpassword)
+{
+	upap_state *u = &upap[unit];
+	
+	/* Save the username and password we're given */
+	u->us_user = luser;
+	u->us_userlen = strlen(luser);
+	u->us_passwd = lpassword;
+	u->us_passwdlen = strlen(lpassword);
+}
+
+
+/*
+ * upap_authwithpeer - Authenticate us with our peer (start client).
+ *
+ * Set new state and send authenticate's.
+ */
+void upap_authwithpeer(int unit, char *user, char *password)
+{
+	upap_state *u = &upap[unit];
+	
+	UPAPDEBUG((LOG_INFO, "upap_authwithpeer: %d user=%s password=%s s=%d\n",
+				unit, user, password, u->us_clientstate));
+	
+	upap_setloginpasswd(unit, user, password);
+
+	u->us_transmits = 0;
+	
+	/* Lower layer up yet? */
+	if (u->us_clientstate == UPAPCS_INITIAL ||
+			u->us_clientstate == UPAPCS_PENDING) {
+		u->us_clientstate = UPAPCS_PENDING;
+		return;
+	}
+	
+	upap_sauthreq(u);			/* Start protocol */
+}
+
+
+/*
+ * upap_authpeer - Authenticate our peer (start server).
+ *
+ * Set new state.
+ */
+void upap_authpeer(int unit)
+{
+	upap_state *u = &upap[unit];
+	
+	/* Lower layer up yet? */
+	if (u->us_serverstate == UPAPSS_INITIAL ||
+			u->us_serverstate == UPAPSS_PENDING) {
+		u->us_serverstate = UPAPSS_PENDING;
+		return;
+	}
+	
+	u->us_serverstate = UPAPSS_LISTEN;
+	if (u->us_reqtimeout > 0)
+		TIMEOUT(upap_reqtimeout, u, u->us_reqtimeout);
+}
+
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+/*
+ * upap_init - Initialize a UPAP unit.
+ */
+static void upap_init(int unit)
+{
+	upap_state *u = &upap[unit];
+
+	UPAPDEBUG((LOG_INFO, "upap_init: %d\n", unit));	
+	u->us_unit = unit;
+	u->us_user = NULL;
+	u->us_userlen = 0;
+	u->us_passwd = NULL;
+	u->us_passwdlen = 0;
+	u->us_clientstate = UPAPCS_INITIAL;
+	u->us_serverstate = UPAPSS_INITIAL;
+	u->us_id = 0;
+	u->us_timeouttime = UPAP_DEFTIMEOUT;
+	u->us_maxtransmits = 10;
+	u->us_reqtimeout = UPAP_DEFREQTIME;
+}
+
+/*
+ * upap_timeout - Retransmission timer for sending auth-reqs expired.
+ */
+static void upap_timeout(void *arg)
+{
+	upap_state *u = (upap_state *) arg;
+	
+	UPAPDEBUG((LOG_INFO, "upap_timeout: %d timeout %d expired s=%d\n", 
+				u->us_unit, u->us_timeouttime, u->us_clientstate));
+	
+	if (u->us_clientstate != UPAPCS_AUTHREQ)
+		return;
+	
+	if (u->us_transmits >= u->us_maxtransmits) {
+		/* give up in disgust */
+		UPAPDEBUG((LOG_ERR, "No response to PAP authenticate-requests\n"));
+		u->us_clientstate = UPAPCS_BADAUTH;
+		auth_withpeer_fail(u->us_unit, PPP_PAP);
+		return;
+	}
+	
+	upap_sauthreq(u);		/* Send Authenticate-Request */
+}
+
+
+/*
+ * upap_reqtimeout - Give up waiting for the peer to send an auth-req.
+ */
+static void upap_reqtimeout(void *arg)
+{
+	upap_state *u = (upap_state *) arg;
+	
+	if (u->us_serverstate != UPAPSS_LISTEN)
+		return;			/* huh?? */
+	
+	auth_peer_fail(u->us_unit, PPP_PAP);
+	u->us_serverstate = UPAPSS_BADAUTH;
+}
+
+
+/*
+ * upap_lowerup - The lower layer is up.
+ *
+ * Start authenticating if pending.
+ */
+static void upap_lowerup(int unit)
+{
+	upap_state *u = &upap[unit];
+	
+	UPAPDEBUG((LOG_INFO, "upap_lowerup: %d s=%d\n", unit, u->us_clientstate));
+	
+	if (u->us_clientstate == UPAPCS_INITIAL)
+		u->us_clientstate = UPAPCS_CLOSED;
+	else if (u->us_clientstate == UPAPCS_PENDING) {
+		upap_sauthreq(u);	/* send an auth-request */
+	}
+	
+	if (u->us_serverstate == UPAPSS_INITIAL)
+		u->us_serverstate = UPAPSS_CLOSED;
+	else if (u->us_serverstate == UPAPSS_PENDING) {
+		u->us_serverstate = UPAPSS_LISTEN;
+		if (u->us_reqtimeout > 0)
+			TIMEOUT(upap_reqtimeout, u, u->us_reqtimeout);
+	}
+}
+
+
+/*
+ * upap_lowerdown - The lower layer is down.
+ *
+ * Cancel all timeouts.
+ */
+static void upap_lowerdown(int unit)
+{
+	upap_state *u = &upap[unit];
+	
+	UPAPDEBUG((LOG_INFO, "upap_lowerdown: %d s=%d\n", unit, u->us_clientstate));
+	
+	if (u->us_clientstate == UPAPCS_AUTHREQ)	/* Timeout pending? */
+		UNTIMEOUT(upap_timeout, u);		/* Cancel timeout */
+	if (u->us_serverstate == UPAPSS_LISTEN && u->us_reqtimeout > 0)
+		UNTIMEOUT(upap_reqtimeout, u);
+	
+	u->us_clientstate = UPAPCS_INITIAL;
+	u->us_serverstate = UPAPSS_INITIAL;
+}
+
+
+/*
+ * upap_protrej - Peer doesn't speak this protocol.
+ *
+ * This shouldn't happen.  In any case, pretend lower layer went down.
+ */
+static void upap_protrej(int unit)
+{
+	upap_state *u = &upap[unit];
+	
+	if (u->us_clientstate == UPAPCS_AUTHREQ) {
+		UPAPDEBUG((LOG_ERR, "PAP authentication failed due to protocol-reject\n"));
+		auth_withpeer_fail(unit, PPP_PAP);
+	}
+	if (u->us_serverstate == UPAPSS_LISTEN) {
+		UPAPDEBUG((LOG_ERR, "PAP authentication of peer failed (protocol-reject)\n"));
+		auth_peer_fail(unit, PPP_PAP);
+	}
+	upap_lowerdown(unit);
+}
+
+
+/*
+ * upap_input - Input UPAP packet.
+ */
+static void upap_input(int unit, u_char *inpacket, int l)
+{
+	upap_state *u = &upap[unit];
+	u_char *inp;
+	u_char code, id;
+	int len;
+	
+	/*
+	 * Parse header (code, id and length).
+	 * If packet too short, drop it.
+	 */
+	inp = inpacket;
+	if (l < UPAP_HEADERLEN) {
+		UPAPDEBUG((LOG_INFO, "pap_input: rcvd short header.\n"));
+		return;
+	}
+	GETCHAR(code, inp);
+	GETCHAR(id, inp);
+	GETSHORT(len, inp);
+	if (len < UPAP_HEADERLEN) {
+		UPAPDEBUG((LOG_INFO, "pap_input: rcvd illegal length.\n"));
+		return;
+	}
+	if (len > l) {
+		UPAPDEBUG((LOG_INFO, "pap_input: rcvd short packet.\n"));
+		return;
+	}
+	len -= UPAP_HEADERLEN;
+	
+	/*
+	 * Action depends on code.
+	 */
+	switch (code) {
+	case UPAP_AUTHREQ:
+		upap_rauthreq(u, inp, id, len);
+		break;
+	
+	case UPAP_AUTHACK:
+		upap_rauthack(u, inp, id, len);
+		break;
+	
+	case UPAP_AUTHNAK:
+		upap_rauthnak(u, inp, id, len);
+		break;
+	
+	default:				/* XXX Need code reject */
+		break;
+	}
+}
+
+
+/*
+ * upap_rauth - Receive Authenticate.
+ */
+static void upap_rauthreq(
+	upap_state *u, 
+	u_char *inp, 
+	int id,
+	int len
+)
+{
+	u_char ruserlen, rpasswdlen;
+	char *ruser, *rpasswd;
+	int retcode;
+	char *msg;
+	int msglen;
+	
+	UPAPDEBUG((LOG_INFO, "pap_rauth: Rcvd id %d.\n", id));
+	
+	if (u->us_serverstate < UPAPSS_LISTEN)
+		return;
+	
+	/*
+	 * If we receive a duplicate authenticate-request, we are
+	 * supposed to return the same status as for the first request.
+	 */
+	if (u->us_serverstate == UPAPSS_OPEN) {
+		upap_sresp(u, UPAP_AUTHACK, id, "", 0);	/* return auth-ack */
+		return;
+	}
+	if (u->us_serverstate == UPAPSS_BADAUTH) {
+		upap_sresp(u, UPAP_AUTHNAK, id, "", 0);	/* return auth-nak */
+		return;
+	}
+	
+	/*
+	 * Parse user/passwd.
+	 */
+	if (len < sizeof (u_char)) {
+		UPAPDEBUG((LOG_INFO, "pap_rauth: rcvd short packet.\n"));
+		return;
+	}
+	GETCHAR(ruserlen, inp);
+	len -= sizeof (u_char) + ruserlen + sizeof (u_char);
+	if (len < 0) {
+		UPAPDEBUG((LOG_INFO, "pap_rauth: rcvd short packet.\n"));
+		return;
+	}
+	ruser = (char *) inp;
+	INCPTR(ruserlen, inp);
+	GETCHAR(rpasswdlen, inp);
+	if (len < rpasswdlen) {
+		UPAPDEBUG((LOG_INFO, "pap_rauth: rcvd short packet.\n"));
+		return;
+	}
+	rpasswd = (char *) inp;
+	
+	/*
+	 * Check the username and password given.
+	 */
+	retcode = check_passwd(u->us_unit, ruser, ruserlen, rpasswd,
+			   rpasswdlen, &msg, &msglen);
+	BZERO(rpasswd, rpasswdlen);
+	
+	upap_sresp(u, retcode, id, msg, msglen);
+	
+	if (retcode == UPAP_AUTHACK) {
+		u->us_serverstate = UPAPSS_OPEN;
+		auth_peer_success(u->us_unit, PPP_PAP, ruser, ruserlen);
+	} else {
+		u->us_serverstate = UPAPSS_BADAUTH;
+		auth_peer_fail(u->us_unit, PPP_PAP);
+	}
+	
+	if (u->us_reqtimeout > 0)
+		UNTIMEOUT(upap_reqtimeout, u);
+}
+
+
+/*
+ * upap_rauthack - Receive Authenticate-Ack.
+ */
+static void upap_rauthack(
+	upap_state *u,
+	u_char *inp,
+	int id,
+	int len
+)
+{
+	u_char msglen;
+	char *msg;
+	
+	UPAPDEBUG((LOG_INFO, "pap_rauthack: Rcvd id %d s=%d\n", id, u->us_clientstate));
+	
+	if (u->us_clientstate != UPAPCS_AUTHREQ) /* XXX */
+		return;
+	
+	/*
+	 * Parse message.
+	 */
+	if (len < sizeof (u_char)) {
+		UPAPDEBUG((LOG_INFO, "pap_rauthack: rcvd short packet.\n"));
+		return;
+	}
+	GETCHAR(msglen, inp);
+	len -= sizeof (u_char);
+	if (len < msglen) {
+		UPAPDEBUG((LOG_INFO, "pap_rauthack: rcvd short packet.\n"));
+		return;
+	}
+	msg = (char *) inp;
+	PRINTMSG(msg, msglen);
+	
+	u->us_clientstate = UPAPCS_OPEN;
+	
+	auth_withpeer_success(u->us_unit, PPP_PAP);
+}
+
+
+/*
+ * upap_rauthnak - Receive Authenticate-Nakk.
+ */
+static void upap_rauthnak(
+	upap_state *u,
+	u_char *inp,
+	int id,
+	int len
+)
+{
+	u_char msglen;
+	char *msg;
+	
+	UPAPDEBUG((LOG_INFO, "pap_rauthnak: Rcvd id %d s=%d\n", id, u->us_clientstate));
+	
+	if (u->us_clientstate != UPAPCS_AUTHREQ) /* XXX */
+		return;
+	
+	/*
+	 * Parse message.
+	 */
+	if (len < sizeof (u_char)) {
+		UPAPDEBUG((LOG_INFO, "pap_rauthnak: rcvd short packet.\n"));
+		return;
+	}
+	GETCHAR(msglen, inp);
+	len -= sizeof (u_char);
+	if (len < msglen) {
+		UPAPDEBUG((LOG_INFO, "pap_rauthnak: rcvd short packet.\n"));
+		return;
+	}
+	msg = (char *) inp;
+	PRINTMSG(msg, msglen);
+	
+	u->us_clientstate = UPAPCS_BADAUTH;
+	
+	UPAPDEBUG((LOG_ERR, "PAP authentication failed\n"));
+	auth_withpeer_fail(u->us_unit, PPP_PAP);
+}
+
+
+/*
+ * upap_sauthreq - Send an Authenticate-Request.
+ */
+static void upap_sauthreq(upap_state *u)
+{
+	u_char *outp;
+	int outlen;
+	
+	outlen = UPAP_HEADERLEN + 2 * sizeof (u_char) 
+			+ u->us_userlen + u->us_passwdlen;
+	outp = outpacket_buf[u->us_unit];
+	
+	MAKEHEADER(outp, PPP_PAP);
+	
+	PUTCHAR(UPAP_AUTHREQ, outp);
+	PUTCHAR(++u->us_id, outp);
+	PUTSHORT(outlen, outp);
+	PUTCHAR(u->us_userlen, outp);
+	BCOPY(u->us_user, outp, u->us_userlen);
+	INCPTR(u->us_userlen, outp);
+	PUTCHAR(u->us_passwdlen, outp);
+	BCOPY(u->us_passwd, outp, u->us_passwdlen);
+	
+	pppWrite(u->us_unit, outpacket_buf[u->us_unit], outlen + PPP_HDRLEN);
+	
+	UPAPDEBUG((LOG_INFO, "pap_sauth: Sent id %d\n", u->us_id));
+	
+	TIMEOUT(upap_timeout, u, u->us_timeouttime);
+	++u->us_transmits;
+	u->us_clientstate = UPAPCS_AUTHREQ;
+}
+
+
+/*
+ * upap_sresp - Send a response (ack or nak).
+ */
+static void upap_sresp(
+	upap_state *u,
+	u_char code, 
+	u_char id,
+	char *msg,
+	int msglen
+)
+{
+	u_char *outp;
+	int outlen;
+	
+	outlen = UPAP_HEADERLEN + sizeof (u_char) + msglen;
+	outp = outpacket_buf[u->us_unit];
+	MAKEHEADER(outp, PPP_PAP);
+	
+	PUTCHAR(code, outp);
+	PUTCHAR(id, outp);
+	PUTSHORT(outlen, outp);
+	PUTCHAR(msglen, outp);
+	BCOPY(msg, outp, msglen);
+	pppWrite(u->us_unit, outpacket_buf[u->us_unit], outlen + PPP_HDRLEN);
+	
+	UPAPDEBUG((LOG_INFO, "pap_sresp: Sent code %d, id %d s=%d\n", 
+				code, id, u->us_clientstate));
+}
+
+#if 0
+/*
+ * upap_printpkt - print the contents of a PAP packet.
+ */
+static int upap_printpkt(
+	u_char *p,
+	int plen,
+	void (*printer) (void *, char *, ...),
+	void *arg
+)
+{
+	(void)p;
+	(void)plen;
+	(void)printer;
+	(void)arg;
+	return 0;
+}
+#endif
+
+#endif /* PAP_SUPPORT */
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/pap.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/pap.h
new file mode 100644
index 000000000..59eb2c71e
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/pap.h
@@ -0,0 +1,129 @@
+/*****************************************************************************
+* pap.h -  PPP Password Authentication Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-04 Guy Lancaster , Global Election Systems Inc.
+*	Original derived from BSD codes.
+*****************************************************************************/
+/*
+ * upap.h - User/Password Authentication Protocol definitions.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+
+#ifndef PAP_H
+#define PAP_H
+
+/*************************
+*** PUBLIC DEFINITIONS ***
+*************************/
+/*
+ * Packet header = Code, id, length.
+ */
+#define UPAP_HEADERLEN	(sizeof (u_char) + sizeof (u_char) + sizeof (u_short))
+
+
+/*
+ * UPAP codes.
+ */
+#define UPAP_AUTHREQ	1	/* Authenticate-Request */
+#define UPAP_AUTHACK	2	/* Authenticate-Ack */
+#define UPAP_AUTHNAK	3	/* Authenticate-Nak */
+
+/*
+ * Client states.
+ */
+#define UPAPCS_INITIAL	0	/* Connection down */
+#define UPAPCS_CLOSED	1	/* Connection up, haven't requested auth */
+#define UPAPCS_PENDING	2	/* Connection down, have requested auth */
+#define UPAPCS_AUTHREQ	3	/* We've sent an Authenticate-Request */
+#define UPAPCS_OPEN		4	/* We've received an Ack */
+#define UPAPCS_BADAUTH	5	/* We've received a Nak */
+
+/*
+ * Server states.
+ */
+#define UPAPSS_INITIAL	0	/* Connection down */
+#define UPAPSS_CLOSED	1	/* Connection up, haven't requested auth */
+#define UPAPSS_PENDING	2	/* Connection down, have requested auth */
+#define UPAPSS_LISTEN	3	/* Listening for an Authenticate */
+#define UPAPSS_OPEN		4	/* We've sent an Ack */
+#define UPAPSS_BADAUTH	5	/* We've sent a Nak */
+
+
+/************************
+*** PUBLIC DATA TYPES ***
+************************/
+
+/*
+ * Each interface is described by upap structure.
+ */
+typedef struct upap_state {
+    int us_unit;			/* Interface unit number */
+    const char *us_user;	/* User */
+    int us_userlen;			/* User length */
+    const char *us_passwd;	/* Password */
+    int us_passwdlen;		/* Password length */
+    int us_clientstate;		/* Client state */
+    int us_serverstate;		/* Server state */
+    u_char us_id;			/* Current id */
+    int us_timeouttime;		/* Timeout (seconds) for auth-req retrans. */
+    int us_transmits;		/* Number of auth-reqs sent */
+    int us_maxtransmits;	/* Maximum number of auth-reqs to send */
+    int us_reqtimeout;		/* Time to wait for auth-req from peer */
+} upap_state;
+
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+
+extern upap_state upap[];
+
+void upap_setloginpasswd(int unit, const char *luser, const char *lpassword);
+void upap_authwithpeer (int, char *, char *);
+void upap_authpeer (int);
+
+extern struct protent pap_protent;
+
+#endif /* PAP_H */
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/ppp.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/ppp.c
new file mode 100644
index 000000000..00a7956df
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/ppp.c
@@ -0,0 +1,1623 @@
+/*****************************************************************************
+* ppp.c - Network Point to Point Protocol program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-11-05 Guy Lancaster , Global Election Systems Inc.
+*   Original.
+*****************************************************************************/
+
+/*
+ * ppp_defs.h - PPP definitions.
+ *
+ * if_pppvar.h - private structures and declarations for PPP.
+ *
+ * Copyright (c) 1994 The Australian National University.
+ * All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, provided that the above copyright
+ * notice appears in all copies.  This software is provided without any
+ * warranty, express or implied. The Australian National University
+ * makes no representations about the suitability of this software for
+ * any purpose.
+ *
+ * IN NO EVENT SHALL THE AUSTRALIAN NATIONAL UNIVERSITY BE LIABLE TO ANY
+ * PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES
+ * ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF
+ * THE AUSTRALIAN NATIONAL UNIVERSITY HAVE BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * THE AUSTRALIAN NATIONAL UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE.  THE SOFTWARE PROVIDED HEREUNDER IS
+ * ON AN "AS IS" BASIS, AND THE AUSTRALIAN NATIONAL UNIVERSITY HAS NO
+ * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS,
+ * OR MODIFICATIONS.
+ */
+
+/*
+ * if_ppp.h - Point-to-Point Protocol definitions.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+ 
+#include 
+ 
+#include "ppp.h"
+#if PPP_SUPPORT > 0
+#include "randm.h"
+#include "fsm.h"
+#if PAP_SUPPORT > 0
+#include "pap.h"
+#endif
+#if CHAP_SUPPORT > 0
+#include "chap.h"
+#endif
+#include "ipcp.h"
+#include "lcp.h"
+#include "magic.h"
+#include "auth.h"
+#if VJ_SUPPORT > 0
+#include "vj.h"
+#endif
+
+#include "pppdebug.h"
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+
+/*
+ * The basic PPP frame.
+ */
+#define PPP_ADDRESS(p)  (((u_char *)(p))[0])
+#define PPP_CONTROL(p)  (((u_char *)(p))[1])
+#define PPP_PROTOCOL(p) ((((u_char *)(p))[2] << 8) + ((u_char *)(p))[3])
+
+/* PPP packet parser states.  Current state indicates operation yet to be
+ * completed. */
+typedef enum {
+    PDIDLE = 0,                 /* Idle state - waiting. */
+    PDSTART,                    /* Process start flag. */
+    PDADDRESS,                  /* Process address field. */
+    PDCONTROL,                  /* Process control field. */
+    PDPROTOCOL1,                /* Process protocol field 1. */
+    PDPROTOCOL2,                /* Process protocol field 2. */
+    PDDATA                      /* Process data byte. */
+} PPPDevStates;
+
+#define ESCAPE_P(accm, c) ((accm)[(c) >> 3] & pppACCMMask[c & 0x07])
+
+/************************/
+/*** LOCAL DATA TYPES ***/
+/************************/
+/*
+ * PPP interface control block.
+ */
+typedef struct PPPControl_s {
+    char openFlag;                      /* True when in use. */
+    char oldFrame;                      /* Old framing character for fd. */
+    sio_fd_t fd;                    /* File device ID of port. */
+    int  kill_link;                     /* Shut the link down. */
+    int  sig_hup;                       /* Carrier lost. */
+    int  if_up;                         /* True when the interface is up. */
+    int  errCode;                       /* Code indicating why interface is down. */
+    struct pbuf *inHead, *inTail;       /* The input packet. */
+    PPPDevStates inState;               /* The input process state. */
+    char inEscaped;                     /* Escape next character. */
+    u16_t inProtocol;                   /* The input protocol code. */
+    u16_t inFCS;                        /* Input Frame Check Sequence value. */
+    int  mtu;                           /* Peer's mru */
+    int  pcomp;                         /* Does peer accept protocol compression? */
+    int  accomp;                        /* Does peer accept addr/ctl compression? */
+    u_long lastXMit;                    /* Time of last transmission. */
+    ext_accm inACCM;                    /* Async-Ctl-Char-Map for input. */
+    ext_accm outACCM;                   /* Async-Ctl-Char-Map for output. */
+#if VJ_SUPPORT > 0
+    int  vjEnabled;                     /* Flag indicating VJ compression enabled. */
+    struct vjcompress vjComp;           /* Van Jabobsen compression header. */
+#endif
+
+    struct netif netif;
+
+    struct ppp_addrs addrs;
+
+    void (*linkStatusCB)(void *ctx, int errCode, void *arg);
+    void *linkStatusCtx;
+
+} PPPControl;
+
+
+/*
+ * Ioctl definitions.
+ */
+
+struct npioctl {
+    int     protocol;           /* PPP procotol, e.g. PPP_IP */
+    enum NPmode mode;
+};
+
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+static void pppMain(void *pd);
+static void pppDrop(PPPControl *pc);
+static void pppInProc(int pd, u_char *s, int l);
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+u_long subnetMask;
+
+static PPPControl pppControl[NUM_PPP]; /* The PPP interface control blocks. */
+
+/*
+ * PPP Data Link Layer "protocol" table.
+ * One entry per supported protocol.
+ * The last entry must be NULL.
+ */
+struct protent *ppp_protocols[] = {
+    &lcp_protent,
+#if PAP_SUPPORT > 0
+    &pap_protent,
+#endif
+#if CHAP_SUPPORT > 0
+    &chap_protent,
+#endif
+#if CBCP_SUPPORT > 0
+    &cbcp_protent,
+#endif
+    &ipcp_protent,
+#if CCP_SUPPORT > 0
+    &ccp_protent,
+#endif
+    NULL
+};
+
+
+/*
+ * Buffers for outgoing packets.  This must be accessed only from the appropriate
+ * PPP task so that it doesn't need to be protected to avoid collisions.
+ */
+u_char outpacket_buf[NUM_PPP][PPP_MRU+PPP_HDRLEN];  
+
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+
+/*
+ * FCS lookup table as calculated by genfcstab.
+ */
+static const u_short fcstab[256] = {
+    0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf,
+    0x8c48, 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7,
+    0x1081, 0x0108, 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e,
+    0x9cc9, 0x8d40, 0xbfdb, 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876,
+    0x2102, 0x308b, 0x0210, 0x1399, 0x6726, 0x76af, 0x4434, 0x55bd,
+    0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, 0xfae7, 0xc87c, 0xd9f5,
+    0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, 0x54b5, 0x453c,
+    0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, 0xc974,
+    0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb,
+    0xce4c, 0xdfc5, 0xed5e, 0xfcd7, 0x8868, 0x99e1, 0xab7a, 0xbaf3,
+    0x5285, 0x430c, 0x7197, 0x601e, 0x14a1, 0x0528, 0x37b3, 0x263a,
+    0xdecd, 0xcf44, 0xfddf, 0xec56, 0x98e9, 0x8960, 0xbbfb, 0xaa72,
+    0x6306, 0x728f, 0x4014, 0x519d, 0x2522, 0x34ab, 0x0630, 0x17b9,
+    0xef4e, 0xfec7, 0xcc5c, 0xddd5, 0xa96a, 0xb8e3, 0x8a78, 0x9bf1,
+    0x7387, 0x620e, 0x5095, 0x411c, 0x35a3, 0x242a, 0x16b1, 0x0738,
+    0xffcf, 0xee46, 0xdcdd, 0xcd54, 0xb9eb, 0xa862, 0x9af9, 0x8b70,
+    0x8408, 0x9581, 0xa71a, 0xb693, 0xc22c, 0xd3a5, 0xe13e, 0xf0b7,
+    0x0840, 0x19c9, 0x2b52, 0x3adb, 0x4e64, 0x5fed, 0x6d76, 0x7cff,
+    0x9489, 0x8500, 0xb79b, 0xa612, 0xd2ad, 0xc324, 0xf1bf, 0xe036,
+    0x18c1, 0x0948, 0x3bd3, 0x2a5a, 0x5ee5, 0x4f6c, 0x7df7, 0x6c7e,
+    0xa50a, 0xb483, 0x8618, 0x9791, 0xe32e, 0xf2a7, 0xc03c, 0xd1b5,
+    0x2942, 0x38cb, 0x0a50, 0x1bd9, 0x6f66, 0x7eef, 0x4c74, 0x5dfd,
+    0xb58b, 0xa402, 0x9699, 0x8710, 0xf3af, 0xe226, 0xd0bd, 0xc134,
+    0x39c3, 0x284a, 0x1ad1, 0x0b58, 0x7fe7, 0x6e6e, 0x5cf5, 0x4d7c,
+    0xc60c, 0xd785, 0xe51e, 0xf497, 0x8028, 0x91a1, 0xa33a, 0xb2b3,
+    0x4a44, 0x5bcd, 0x6956, 0x78df, 0x0c60, 0x1de9, 0x2f72, 0x3efb,
+    0xd68d, 0xc704, 0xf59f, 0xe416, 0x90a9, 0x8120, 0xb3bb, 0xa232,
+    0x5ac5, 0x4b4c, 0x79d7, 0x685e, 0x1ce1, 0x0d68, 0x3ff3, 0x2e7a,
+    0xe70e, 0xf687, 0xc41c, 0xd595, 0xa12a, 0xb0a3, 0x8238, 0x93b1,
+    0x6b46, 0x7acf, 0x4854, 0x59dd, 0x2d62, 0x3ceb, 0x0e70, 0x1ff9,
+    0xf78f, 0xe606, 0xd49d, 0xc514, 0xb1ab, 0xa022, 0x92b9, 0x8330,
+    0x7bc7, 0x6a4e, 0x58d5, 0x495c, 0x3de3, 0x2c6a, 0x1ef1, 0x0f78
+};
+
+/* PPP's Asynchronous-Control-Character-Map.  The mask array is used
+ * to select the specific bit for a character. */
+static u_char pppACCMMask[] = {
+    0x01,
+    0x02,
+    0x04,
+    0x08,
+    0x10,
+    0x20,
+    0x40,
+    0x80
+};
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/* Initialize the PPP subsystem. */
+
+struct ppp_settings ppp_settings;
+
+void pppInit(void)
+{
+    struct protent *protp;
+    int i, j;
+    
+	memset(&ppp_settings, 0, sizeof(ppp_settings));
+	ppp_settings.usepeerdns = 1;
+	pppSetAuth(PPPAUTHTYPE_NONE, NULL, NULL);
+
+	magicInit();
+
+    for (i = 0; i < NUM_PPP; i++) {
+        pppControl[i].openFlag = 0;
+
+		subnetMask = htonl(0xffffff00);
+    
+        /*
+         * Initialize to the standard option set.
+         */
+        for (j = 0; (protp = ppp_protocols[j]) != NULL; ++j)
+            (*protp->init)(i);
+    }
+
+#if LINK_STATS
+    /* Clear the statistics. */
+    memset(&lwip_stats.link, 0, sizeof(lwip_stats.link));
+#endif
+}
+
+void pppSetAuth(enum pppAuthType authType, const char *user, const char *passwd)
+{
+    switch(authType) {
+	case PPPAUTHTYPE_NONE:
+	default:
+#ifdef LWIP_PPP_STRICT_PAP_REJECT
+	    ppp_settings.refuse_pap = 1;
+#else
+	    /* some providers request pap and accept an empty login/pw */
+	    ppp_settings.refuse_pap = 0;
+#endif
+	    ppp_settings.refuse_chap = 1;
+	    break;
+	case PPPAUTHTYPE_ANY:
+/* Warning: Using PPPAUTHTYPE_ANY might have security consequences.
+ * RFC 1994 says:
+ *
+ * In practice, within or associated with each PPP server, there is a
+ * database which associates "user" names with authentication
+ * information ("secrets").  It is not anticipated that a particular
+ * named user would be authenticated by multiple methods.  This would
+ * make the user vulnerable to attacks which negotiate the least secure
+ * method from among a set (such as PAP rather than CHAP).  If the same
+ * secret was used, PAP would reveal the secret to be used later with
+ * CHAP.
+ *
+ * Instead, for each user name there should be an indication of exactly
+ * one method used to authenticate that user name.  If a user needs to
+ * make use of different authentication methods under different
+ * circumstances, then distinct user names SHOULD be employed, each of
+ * which identifies exactly one authentication method.
+ *
+ */
+	    ppp_settings.refuse_pap = 0;
+	    ppp_settings.refuse_chap = 0;
+	    break;
+	case PPPAUTHTYPE_PAP:
+	    ppp_settings.refuse_pap = 0;
+	    ppp_settings.refuse_chap = 1;
+	    break;
+	case PPPAUTHTYPE_CHAP:
+	    ppp_settings.refuse_pap = 1;
+	    ppp_settings.refuse_chap = 0;
+	    break;
+    }
+
+    if(user) {
+	strncpy(ppp_settings.user, user, sizeof(ppp_settings.user)-1);
+	ppp_settings.user[sizeof(ppp_settings.user)-1] = '\0';
+    } else
+	ppp_settings.user[0] = '\0';
+
+    if(passwd) {
+	strncpy(ppp_settings.passwd, passwd, sizeof(ppp_settings.passwd)-1);
+	ppp_settings.passwd[sizeof(ppp_settings.passwd)-1] = '\0';
+    } else
+	ppp_settings.passwd[0] = '\0';
+}
+
+/* Open a new PPP connection using the given I/O device.
+ * This initializes the PPP control block but does not
+ * attempt to negotiate the LCP session.  If this port
+ * connects to a modem, the modem connection must be
+ * established before calling this.
+ * Return a new PPP connection descriptor on success or
+ * an error code (negative) on failure. */
+int pppOpen(sio_fd_t fd, void (*linkStatusCB)(void *ctx, int errCode, void *arg), void *linkStatusCtx)
+{
+    PPPControl *pc;
+    int pd;
+
+    /* Find a free PPP session descriptor. Critical region? */
+    for (pd = 0; pd < NUM_PPP && pppControl[pd].openFlag != 0; pd++);
+    if (pd >= NUM_PPP)
+        pd = PPPERR_OPEN;
+    else
+        pppControl[pd].openFlag = !0;
+
+    /* Launch a deamon thread. */
+    if (pd >= 0) {
+
+        pppControl[pd].openFlag = 1;
+
+        lcp_init(pd);
+        pc = &pppControl[pd];
+        pc->fd = fd;
+        pc->kill_link = 0;
+        pc->sig_hup = 0;
+        pc->if_up = 0;
+        pc->errCode = 0;
+        pc->inState = PDIDLE;
+        pc->inHead = NULL;
+        pc->inTail = NULL;
+        pc->inEscaped = 0;
+        pc->lastXMit = 0;
+
+#if VJ_SUPPORT > 0
+        pc->vjEnabled = 0;
+        vj_compress_init(&pc->vjComp);
+#endif
+
+        /* 
+         * Default the in and out accm so that escape and flag characters
+         * are always escaped. 
+         */
+        memset(pc->inACCM, 0, sizeof(ext_accm));
+        pc->inACCM[15] = 0x60;
+        memset(pc->outACCM, 0, sizeof(ext_accm));
+        pc->outACCM[15] = 0x60;
+
+	pc->linkStatusCB = linkStatusCB;
+	pc->linkStatusCtx = linkStatusCtx;
+
+	sys_thread_new(pppMain, (void*)pd, PPP_THREAD_PRIO);
+	if(!linkStatusCB) {
+		while(pd >= 0 && !pc->if_up) {
+			sys_msleep(500);
+			if (lcp_phase[pd] == PHASE_DEAD) {
+				pppClose(pd);
+				if (pc->errCode)
+					pd = pc->errCode;
+				else
+					pd = PPPERR_CONNECT;
+			}
+		}
+	}
+    }
+    return pd;
+}
+
+/* Close a PPP connection and release the descriptor. 
+ * Any outstanding packets in the queues are dropped.
+ * Return 0 on success, an error code on failure. */
+int pppClose(int pd)
+{
+    PPPControl *pc = &pppControl[pd];
+    int st = 0;
+
+    /* Disconnect */
+    pc->kill_link = !0;
+    pppMainWakeup(pd);
+    
+    if(!pc->linkStatusCB) {
+	    while(st >= 0 && lcp_phase[pd] != PHASE_DEAD) {
+		    sys_msleep(500);
+		    break;
+	    }
+    }
+    return st;
+}
+
+/* This function is called when carrier is lost on the PPP channel. */
+void pppSigHUP(int pd)
+{
+    PPPControl *pc = &pppControl[pd];
+
+    pc->sig_hup = 1;
+    pppMainWakeup(pd);
+}
+
+static void nPut(PPPControl *pc, struct pbuf *nb)
+{
+	struct pbuf *b;
+	int c;
+
+	for(b = nb; b != NULL; b = b->next) {
+	    if((c = sio_write(pc->fd, b->payload, b->len)) != b->len) {
+		PPPDEBUG((LOG_WARNING,
+			    "PPP nPut: incomplete sio_write(%d,, %u) = %d\n", pc->fd, b->len, c));
+#if LINK_STATS
+		lwip_stats.link.err++;
+#endif /* LINK_STATS */
+		pc->lastXMit = 0; /* prepend PPP_FLAG to next packet */
+		break;
+	    }
+	}
+	pbuf_free(nb);
+
+#if LINK_STATS
+	lwip_stats.link.xmit++;
+#endif /* LINK_STATS */
+}
+
+/* 
+ * pppAppend - append given character to end of given pbuf.  If outACCM
+ * is not NULL and the character needs to be escaped, do so.
+ * If pbuf is full, append another.
+ * Return the current pbuf.
+ */
+static struct pbuf *pppAppend(u_char c, struct pbuf *nb, ext_accm *outACCM)
+{
+    struct pbuf *tb = nb;
+    
+    /* Make sure there is room for the character and an escape code.
+     * Sure we don't quite fill the buffer if the character doesn't
+     * get escaped but is one character worth complicating this? */
+    /* Note: We assume no packet header. */
+    if (nb && (PBUF_POOL_BUFSIZE - nb->len) < 2) {
+	tb = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL);
+	if (tb) {
+	    nb->next = tb;
+        }
+#if LINK_STATS
+	else {
+	    lwip_stats.link.memerr++;
+	}
+#endif /* LINK_STATS */
+	nb = tb;
+    }
+    if (nb) {
+	if (outACCM && ESCAPE_P(*outACCM, c)) {
+            *((u_char*)nb->payload + nb->len++) = PPP_ESCAPE;
+            *((u_char*)nb->payload + nb->len++) = c ^ PPP_TRANS;
+        }
+        else
+            *((u_char*)nb->payload + nb->len++) = c;
+    }
+        
+    return tb;
+}
+
+/* Send a packet on the given connection. */
+static err_t pppifOutput(struct netif *netif, struct pbuf *pb, struct ip_addr *ipaddr)
+{
+    int pd = (int)netif->state;
+    u_short protocol = PPP_IP;
+    PPPControl *pc = &pppControl[pd];
+    u_int fcsOut = PPP_INITFCS;
+    struct pbuf *headMB = NULL, *tailMB = NULL, *p;
+    u_char c;
+
+    (void)ipaddr;
+
+    /* Validate parameters. */
+    /* We let any protocol value go through - it can't hurt us
+     * and the peer will just drop it if it's not accepting it. */
+	if (pd < 0 || pd >= NUM_PPP || !pc->openFlag || !pb) {
+        PPPDEBUG((LOG_WARNING, "pppifOutput[%d]: bad parms prot=%d pb=%p\n",
+                    pd, protocol, pb));
+#if LINK_STATS
+		lwip_stats.link.opterr++;
+		lwip_stats.link.drop++;
+#endif
+		return ERR_ARG;
+	}
+
+    /* Check that the link is up. */
+	if (lcp_phase[pd] == PHASE_DEAD) {
+        PPPDEBUG((LOG_ERR, "pppifOutput[%d]: link not up\n", pd));
+#if LINK_STATS
+		lwip_stats.link.rterr++;
+		lwip_stats.link.drop++;
+#endif
+		return ERR_RTE;
+	}
+
+    /* Grab an output buffer. */
+	headMB = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL);
+    if (headMB == NULL) {
+        PPPDEBUG((LOG_WARNING, "pppifOutput[%d]: first alloc fail\n", pd));
+#if LINK_STATS
+		lwip_stats.link.memerr++;
+		lwip_stats.link.drop++;
+#endif /* LINK_STATS */
+        return ERR_MEM;
+    }
+        
+#if VJ_SUPPORT > 0
+    /* 
+     * Attempt Van Jacobson header compression if VJ is configured and
+     * this is an IP packet. 
+     */
+    if (protocol == PPP_IP && pc->vjEnabled) {
+        switch (vj_compress_tcp(&pc->vjComp, pb)) {
+        case TYPE_IP:
+            /* No change...
+            protocol = PPP_IP_PROTOCOL;
+             */
+            break;
+        case TYPE_COMPRESSED_TCP:
+            protocol = PPP_VJC_COMP;
+            break;
+        case TYPE_UNCOMPRESSED_TCP:
+            protocol = PPP_VJC_UNCOMP;
+            break;
+        default:
+            PPPDEBUG((LOG_WARNING, "pppifOutput[%d]: bad IP packet\n", pd));
+#if LINK_STATS
+			lwip_stats.link.proterr++;
+			lwip_stats.link.drop++;
+#endif
+        	pbuf_free(headMB);
+            return ERR_VAL;
+        }
+    }
+#endif
+        
+    tailMB = headMB;
+        
+    /* Build the PPP header. */
+    if ((sys_jiffies() - pc->lastXMit) >= PPP_MAXIDLEFLAG)
+        tailMB = pppAppend(PPP_FLAG, tailMB, NULL);
+    pc->lastXMit = sys_jiffies();
+    if (!pc->accomp) {
+        fcsOut = PPP_FCS(fcsOut, PPP_ALLSTATIONS);
+        tailMB = pppAppend(PPP_ALLSTATIONS, tailMB, &pc->outACCM);
+        fcsOut = PPP_FCS(fcsOut, PPP_UI);
+        tailMB = pppAppend(PPP_UI, tailMB, &pc->outACCM);
+    }
+    if (!pc->pcomp || protocol > 0xFF) {
+        c = (protocol >> 8) & 0xFF;
+        fcsOut = PPP_FCS(fcsOut, c);
+        tailMB = pppAppend(c, tailMB, &pc->outACCM);
+    }
+    c = protocol & 0xFF;
+    fcsOut = PPP_FCS(fcsOut, c);
+    tailMB = pppAppend(c, tailMB, &pc->outACCM);
+    
+    /* Load packet. */
+	for(p = pb; p; p = p->next) {
+    	int n;
+    	u_char *sPtr;
+
+        sPtr = (u_char*)p->payload;
+        n = p->len;
+        while (n-- > 0) {
+            c = *sPtr++;
+            
+            /* Update FCS before checking for special characters. */
+            fcsOut = PPP_FCS(fcsOut, c);
+            
+            /* Copy to output buffer escaping special characters. */
+            tailMB = pppAppend(c, tailMB, &pc->outACCM);
+        }
+    }
+
+    /* Add FCS and trailing flag. */
+    c = ~fcsOut & 0xFF;
+    tailMB = pppAppend(c, tailMB, &pc->outACCM);
+    c = (~fcsOut >> 8) & 0xFF;
+    tailMB = pppAppend(c, tailMB, &pc->outACCM);
+    tailMB = pppAppend(PPP_FLAG, tailMB, NULL);
+        
+    /* If we failed to complete the packet, throw it away. */
+    if (!tailMB) {
+        PPPDEBUG((LOG_WARNING,
+                    "pppifOutput[%d]: Alloc err - dropping proto=%d\n", 
+                    pd, protocol));
+        pbuf_free(headMB);
+#if LINK_STATS
+		lwip_stats.link.memerr++;
+		lwip_stats.link.drop++;
+#endif
+        return ERR_MEM;
+    }
+
+	/* Send it. */
+    PPPDEBUG((LOG_INFO, "pppifOutput[%d]: proto=0x%04X\n", pd, protocol));
+
+    nPut(pc, headMB);
+
+    return ERR_OK;
+}
+
+/* Get and set parameters for the given connection.
+ * Return 0 on success, an error code on failure. */
+int  pppIOCtl(int pd, int cmd, void *arg)
+{
+    PPPControl *pc = &pppControl[pd];
+    int st = 0;
+
+    if (pd < 0 || pd >= NUM_PPP)
+        st = PPPERR_PARAM;
+    else {
+        switch(cmd) {
+        case PPPCTLG_UPSTATUS:      /* Get the PPP up status. */
+            if (arg) 
+                *(int *)arg = (int)(pc->if_up);
+            else
+                st = PPPERR_PARAM;
+            break;
+        case PPPCTLS_ERRCODE:       /* Set the PPP error code. */
+            if (arg) 
+                pc->errCode = *(int *)arg;
+            else
+                st = PPPERR_PARAM;
+            break;
+        case PPPCTLG_ERRCODE:       /* Get the PPP error code. */
+            if (arg) 
+                *(int *)arg = (int)(pc->errCode);
+            else
+                st = PPPERR_PARAM;
+            break;
+        case PPPCTLG_FD:
+            if (arg) 
+                *(sio_fd_t *)arg = pc->fd;
+            else
+                st = PPPERR_PARAM;
+            break;
+        default:
+            st = PPPERR_PARAM;
+            break;
+        }
+    }
+    
+    return st;
+}
+
+/*
+ * Return the Maximum Transmission Unit for the given PPP connection.
+ */
+u_int pppMTU(int pd)
+{
+    PPPControl *pc = &pppControl[pd];
+    u_int st;
+    
+    /* Validate parameters. */
+    if (pd < 0 || pd >= NUM_PPP || !pc->openFlag)
+        st = 0;
+    else
+        st = pc->mtu;
+        
+    return st;
+}
+
+/*
+ * Write n characters to a ppp link.
+ *  RETURN: >= 0 Number of characters written
+ *           -1 Failed to write to device
+ */
+int pppWrite(int pd, const u_char *s, int n)
+{
+    PPPControl *pc = &pppControl[pd];
+    u_char c;
+    u_int fcsOut = PPP_INITFCS;
+    struct pbuf *headMB = NULL, *tailMB;
+	headMB = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL);
+    if (headMB == NULL) {
+#if LINK_STATS
+		lwip_stats.link.memerr++;
+		lwip_stats.link.proterr++;
+#endif /* LINK_STATS */
+		return PPPERR_ALLOC;
+    }
+
+    tailMB = headMB;
+        
+    /* If the link has been idle, we'll send a fresh flag character to
+     * flush any noise. */
+    if ((sys_jiffies() - pc->lastXMit) >= PPP_MAXIDLEFLAG)
+        tailMB = pppAppend(PPP_FLAG, tailMB, NULL);
+    pc->lastXMit = sys_jiffies();
+     
+    /* Load output buffer. */
+    while (n-- > 0) {
+        c = *s++;
+        
+        /* Update FCS before checking for special characters. */
+        fcsOut = PPP_FCS(fcsOut, c);
+        
+        /* Copy to output buffer escaping special characters. */
+        tailMB = pppAppend(c, tailMB, &pc->outACCM);
+    }
+    
+    /* Add FCS and trailing flag. */
+    c = ~fcsOut & 0xFF;
+    tailMB = pppAppend(c, tailMB, &pc->outACCM);
+    c = (~fcsOut >> 8) & 0xFF;
+    tailMB = pppAppend(c, tailMB, &pc->outACCM);
+    tailMB = pppAppend(PPP_FLAG, tailMB, NULL);
+        
+    /* If we failed to complete the packet, throw it away.
+     * Otherwise send it. */
+    if (!tailMB) {
+		PPPDEBUG((LOG_WARNING,
+                "pppWrite[%d]: Alloc err - dropping pbuf len=%d\n", pd, headMB->len));
+/*                "pppWrite[%d]: Alloc err - dropping %d:%.*H", pd, headMB->len, LWIP_MIN(headMB->len * 2, 40), headMB->payload)); */
+		pbuf_free(headMB);
+#if LINK_STATS
+		lwip_stats.link.memerr++;
+		lwip_stats.link.proterr++;
+#endif /* LINK_STATS */
+		return PPPERR_ALLOC;
+	}
+
+    PPPDEBUG((LOG_INFO, "pppWrite[%d]: len=%d\n", pd, headMB->len));
+/*     "pppWrite[%d]: %d:%.*H", pd, headMB->len, LWIP_MIN(headMB->len * 2, 40), headMB->payload)); */
+    nPut(pc, headMB);
+
+    return PPPERR_NONE;
+}
+
+/*
+ * ppp_send_config - configure the transmit characteristics of
+ * the ppp interface.
+ */
+void ppp_send_config(
+    int unit, 
+    int mtu,
+    u32_t asyncmap,
+    int pcomp, 
+    int accomp
+)
+{
+    PPPControl *pc = &pppControl[unit];
+    int i;
+    
+    pc->mtu = mtu;
+    pc->pcomp = pcomp;
+    pc->accomp = accomp;
+    
+    /* Load the ACCM bits for the 32 control codes. */
+    for (i = 0; i < 32/8; i++)
+        pc->outACCM[i] = (u_char)((asyncmap >> (8 * i)) & 0xFF);
+    PPPDEBUG((LOG_INFO, "ppp_send_config[%d]: outACCM=%X %X %X %X\n",
+                unit,
+                pc->outACCM[0], pc->outACCM[1], pc->outACCM[2], pc->outACCM[3]));
+}
+
+
+/*
+ * ppp_set_xaccm - set the extended transmit ACCM for the interface.
+ */
+void ppp_set_xaccm(int unit, ext_accm *accm)
+{
+    memcpy(pppControl[unit].outACCM, accm, sizeof(ext_accm));
+    PPPDEBUG((LOG_INFO, "ppp_set_xaccm[%d]: outACCM=%X %X %X %X\n",
+                unit,
+                pppControl[unit].outACCM[0],
+                pppControl[unit].outACCM[1],
+                pppControl[unit].outACCM[2],
+                pppControl[unit].outACCM[3]));
+}
+
+
+/*
+ * ppp_recv_config - configure the receive-side characteristics of
+ * the ppp interface.
+ */
+void ppp_recv_config(
+    int unit, 
+    int mru,
+    u32_t asyncmap,
+    int pcomp, 
+    int accomp
+)
+{
+    PPPControl *pc = &pppControl[unit];
+    int i;
+    
+	(void)accomp;
+	(void)pcomp;
+	(void)mru;
+
+    /* Load the ACCM bits for the 32 control codes. */
+    for (i = 0; i < 32 / 8; i++)
+        pc->inACCM[i] = (u_char)(asyncmap >> (i * 8));
+    PPPDEBUG((LOG_INFO, "ppp_recv_config[%d]: inACCM=%X %X %X %X\n",
+                unit,
+                pc->inACCM[0], pc->inACCM[1], pc->inACCM[2], pc->inACCM[3]));
+}
+
+#if 0
+/*
+ * ccp_test - ask kernel whether a given compression method
+ * is acceptable for use.  Returns 1 if the method and parameters
+ * are OK, 0 if the method is known but the parameters are not OK
+ * (e.g. code size should be reduced), or -1 if the method is unknown.
+ */
+int ccp_test(
+    int unit, 
+    int opt_len, 
+    int for_transmit,
+    u_char *opt_ptr
+)
+{
+    return 0;   /* XXX Currently no compression. */
+}
+
+/*
+ * ccp_flags_set - inform kernel about the current state of CCP.
+ */
+void ccp_flags_set(int unit, int isopen, int isup)
+{
+    /* XXX */
+}
+
+/*
+ * ccp_fatal_error - returns 1 if decompression was disabled as a
+ * result of an error detected after decompression of a packet,
+ * 0 otherwise.  This is necessary because of patent nonsense.
+ */
+int ccp_fatal_error(int unit)
+{
+    /* XXX */
+    return 0;
+}
+#endif
+
+/*
+ * get_idle_time - return how long the link has been idle.
+ */
+int get_idle_time(int u, struct ppp_idle *ip)
+{   
+    /* XXX */
+	(void)u;
+	(void)ip;
+
+    return 0;
+}
+
+
+/*
+ * Return user specified netmask, modified by any mask we might determine
+ * for address `addr' (in network byte order).
+ * Here we scan through the system's list of interfaces, looking for
+ * any non-point-to-point interfaces which might appear to be on the same
+ * network as `addr'.  If we find any, we OR in their netmask to the
+ * user-specified netmask.
+ */
+u32_t GetMask(u32_t addr)
+{
+    u32_t mask, nmask;
+    
+    htonl(addr);
+    if (IN_CLASSA(addr))    /* determine network mask for address class */
+        nmask = IN_CLASSA_NET;
+    else if (IN_CLASSB(addr))
+        nmask = IN_CLASSB_NET;
+    else
+        nmask = IN_CLASSC_NET;
+    /* class D nets are disallowed by bad_ip_adrs */
+    mask = subnetMask | htonl(nmask);
+    
+    /* XXX
+     * Scan through the system's network interfaces.
+     * Get each netmask and OR them into our mask.
+     */
+    
+    return mask;
+}
+
+/*
+ * sifvjcomp - config tcp header compression
+ */
+int sifvjcomp(
+    int pd, 
+    int vjcomp, 
+    int cidcomp, 
+    int maxcid
+)
+{
+#if VJ_SUPPORT > 0
+    PPPControl *pc = &pppControl[pd];
+    
+    pc->vjEnabled = vjcomp;
+    pc->vjComp.compressSlot = cidcomp;
+    pc->vjComp.maxSlotIndex = maxcid;
+    PPPDEBUG((LOG_INFO, "sifvjcomp: VJ compress enable=%d slot=%d max slot=%d\n",
+                vjcomp, cidcomp, maxcid));
+#endif
+
+    return 0;
+}
+
+/*
+ * pppifNetifInit - netif init callback
+ */
+static err_t pppifNetifInit(struct netif *netif)
+{
+	netif->name[0] = 'p';
+	netif->name[1] = 'p';
+	netif->output = pppifOutput;
+	netif->mtu = pppMTU((int)netif->state);
+	return ERR_OK;
+}
+
+
+/*
+ * sifup - Config the interface up and enable IP packets to pass.
+ */
+int sifup(int pd)
+{
+    PPPControl *pc = &pppControl[pd];
+    int st = 1;
+    
+    if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+        st = 0;
+        PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd));
+    } else {
+		netif_remove(&pc->netif);
+		if (netif_add(&pc->netif, &pc->addrs.our_ipaddr, &pc->addrs.netmask, &pc->addrs.his_ipaddr, (void *)pd, pppifNetifInit, ip_input)) {
+        		pc->if_up = 1;
+        		pc->errCode = PPPERR_NONE;
+
+			PPPDEBUG((LOG_DEBUG, "sifup: unit %d: linkStatusCB=%lx errCode=%d\n", pd, pc->linkStatusCB, pc->errCode));
+			if(pc->linkStatusCB)
+				pc->linkStatusCB(pc->linkStatusCtx, pc->errCode, &pc->addrs);
+		} else {
+        	st = 0;
+        	PPPDEBUG((LOG_ERR, "sifup[%d]: netif_add failed\n", pd));
+		}
+    }
+
+    return st;
+}
+
+/*
+ * sifnpmode - Set the mode for handling packets for a given NP.
+ */
+int sifnpmode(int u, int proto, enum NPmode mode)
+{
+	(void)u;
+	(void)proto;
+	(void)mode;
+    return 0;
+}
+
+/*
+ * sifdown - Config the interface down and disable IP.
+ */
+int sifdown(int pd)
+{
+    PPPControl *pc = &pppControl[pd];
+    int st = 1;
+    
+    if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+        st = 0;
+        PPPDEBUG((LOG_WARNING, "sifdown[%d]: bad parms\n", pd));
+    } else {
+        pc->if_up = 0;
+	netif_remove(&pc->netif);
+	PPPDEBUG((LOG_DEBUG, "sifdown: unit %d: linkStatusCB=%lx errCode=%d\n", pd, pc->linkStatusCB, pc->errCode));
+	if(pc->linkStatusCB)
+		pc->linkStatusCB(pc->linkStatusCtx, PPPERR_CONNECT, NULL);
+	}
+    return st;
+}
+
+/*
+ * sifaddr - Config the interface IP addresses and netmask.
+ */
+int sifaddr(
+    int pd,             /* Interface unit ??? */
+    u32_t o,        /* Our IP address ??? */
+    u32_t h,        /* His IP address ??? */
+    u32_t m,        /* IP subnet mask ??? */
+    u32_t ns1,      /* Primary DNS */
+    u32_t ns2       /* Secondary DNS */
+)
+{
+    PPPControl *pc = &pppControl[pd];
+    int st = 1;
+    
+    if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+        st = 0;
+        PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd));
+    } else {
+		memcpy(&pc->addrs.our_ipaddr, &o, sizeof(o));
+		memcpy(&pc->addrs.his_ipaddr, &h, sizeof(h));
+		memcpy(&pc->addrs.netmask, &m, sizeof(m));
+		memcpy(&pc->addrs.dns1, &ns1, sizeof(ns1));
+		memcpy(&pc->addrs.dns2, &ns2, sizeof(ns2));
+    }
+    return st;
+}
+
+/*
+ * cifaddr - Clear the interface IP addresses, and delete routes
+ * through the interface if possible.
+ */
+int cifaddr(
+    int pd,         /* Interface unit ??? */
+    u32_t o,    /* Our IP address ??? */
+    u32_t h     /* IP broadcast address ??? */
+)
+{
+    PPPControl *pc = &pppControl[pd];
+    int st = 1;
+    
+	(void)o;
+	(void)h;
+    if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+        st = 0;
+        PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd));
+    } else {
+		IP4_ADDR(&pc->addrs.our_ipaddr, 0,0,0,0);
+		IP4_ADDR(&pc->addrs.his_ipaddr, 0,0,0,0);
+		IP4_ADDR(&pc->addrs.netmask, 255,255,255,0);
+		IP4_ADDR(&pc->addrs.dns1, 0,0,0,0);
+		IP4_ADDR(&pc->addrs.dns2, 0,0,0,0);
+    }
+    return st;
+}
+
+/*
+ * sifdefaultroute - assign a default route through the address given.
+ */
+int sifdefaultroute(int pd, u32_t l, u32_t g)
+{
+    PPPControl *pc = &pppControl[pd];
+    int st = 1;
+    
+	(void)l;
+	(void)g;
+    if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+        st = 0;
+        PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd));
+    } else {
+		netif_set_default(&pc->netif);
+    }
+
+    /* TODO: check how PPP handled the netMask, previously not set by ipSetDefault */
+
+    return st;
+}
+
+/*
+ * cifdefaultroute - delete a default route through the address given.
+ */
+int cifdefaultroute(int pd, u32_t l, u32_t g)
+{
+    PPPControl *pc = &pppControl[pd];
+    int st = 1;
+    
+	(void)l;
+	(void)g;
+    if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+        st = 0;
+        PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd));
+    } else {
+		netif_set_default(NULL);
+    }
+
+    return st;
+}
+
+void
+pppMainWakeup(int pd)
+{
+	PPPDEBUG((LOG_DEBUG, "pppMainWakeup: unit %d\n", pd));
+	sio_read_abort(pppControl[pd].fd);
+}
+
+/* these callbacks are necessary because lcp_* functions
+   must be called in the same context as pppInput(),
+   namely the tcpip_thread(), essentially because
+   they manipulate timeouts which are thread-private
+*/
+
+static void
+pppStartCB(void *arg)
+{
+    int pd = (int)arg;
+
+	PPPDEBUG((LOG_DEBUG, "pppStartCB: unit %d\n", pd));
+    lcp_lowerup(pd);
+    lcp_open(pd);      /* Start protocol */
+}
+
+static void
+pppStopCB(void *arg)
+{
+    int pd = (int)arg;
+
+	PPPDEBUG((LOG_DEBUG, "pppStopCB: unit %d\n", pd));
+    lcp_close(pd, "User request");
+}
+
+static void
+pppHupCB(void *arg)
+{
+    int pd = (int)arg;
+
+	PPPDEBUG((LOG_DEBUG, "pppHupCB: unit %d\n", pd));
+    lcp_lowerdown(pd);
+    link_terminated(pd);
+}
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+/* The main PPP process function.  This implements the state machine according
+ * to section 4 of RFC 1661: The Point-To-Point Protocol. */
+static void pppMain(void *arg)
+{
+    int pd = (int)arg;
+    struct pbuf *p;
+    PPPControl* pc;
+
+    pc = &pppControl[pd];
+
+    p = pbuf_alloc(PBUF_RAW, PPP_MRU+PPP_HDRLEN, PBUF_RAM);
+    if(!p) {
+		LWIP_ASSERT("p != NULL", p);
+		pc->errCode = PPPERR_ALLOC;
+		goto out;
+    }
+
+    /*
+     * Start the connection and handle incoming events (packet or timeout).
+     */
+	PPPDEBUG((LOG_INFO, "pppMain: unit %d: Connecting\n", pd));
+    tcpip_callback(pppStartCB, arg);
+    while (lcp_phase[pd] != PHASE_DEAD) {
+        if (pc->kill_link) {
+	    	PPPDEBUG((LOG_DEBUG, "pppMainWakeup: unit %d kill_link -> pppStopCB\n", pd));
+		pc->errCode = PPPERR_USER;
+		/* This will leave us at PHASE_DEAD. */
+    		tcpip_callback(pppStopCB, arg);
+		pc->kill_link = 0;
+        }
+        else if (pc->sig_hup) {
+	    	PPPDEBUG((LOG_DEBUG, "pppMainWakeup: unit %d sig_hup -> pppHupCB\n", pd));
+		pc->sig_hup = 0;
+    		tcpip_callback(pppHupCB, arg);
+        } else {
+		int c = sio_read(pc->fd, p->payload, p->len);
+		if(c > 0) {
+			pppInProc(pd, p->payload, c);
+		} else {
+		    PPPDEBUG((LOG_DEBUG, "pppMainWakeup: unit %d sio_read len=%d returned %d\n", pd, p->len, c));
+		    sys_msleep(1); /* give other tasks a chance to run */
+		}
+        }
+    }
+	PPPDEBUG((LOG_INFO, "pppMain: unit %d: PHASE_DEAD\n", pd));
+    pbuf_free(p);
+
+out:
+	PPPDEBUG((LOG_DEBUG, "pppMain: unit %d: linkStatusCB=%lx errCode=%d\n", pd, pc->linkStatusCB, pc->errCode));
+    if(pc->linkStatusCB)
+	    pc->linkStatusCB(pc->linkStatusCtx, pc->errCode ? pc->errCode : PPPERR_PROTOCOL, NULL);
+
+    pc->openFlag = 0;
+}
+
+static struct pbuf *pppSingleBuf(struct pbuf *p)
+{
+	struct pbuf *q, *b;
+	u_char *pl;
+
+	if(p->tot_len == p->len)
+		return p;
+
+	q = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM);
+	if(!q) {
+		PPPDEBUG((LOG_ERR,
+                        "pppSingleBuf: unable to alloc new buf (%d)\n", p->tot_len));
+		return p; /* live dangerously */
+	}
+
+	for(b = p, pl = q->payload; b != NULL; b = b->next) {
+		memcpy(pl, b->payload, b->len);
+		pl += b->len;
+	}
+
+	pbuf_free(p);
+
+	return q;
+}
+
+struct pppInputHeader {
+	int unit;
+	u16_t proto;
+};
+
+/*
+ * Pass the processed input packet to the appropriate handler.
+ * This function and all handlers run in the context of the tcpip_thread
+ */
+static void pppInput(void *arg)
+{
+	struct pbuf *nb = (struct pbuf *)arg;
+    u16_t protocol;
+    int pd;
+
+	pd = ((struct pppInputHeader *)nb->payload)->unit;
+	protocol = ((struct pppInputHeader *)nb->payload)->proto;
+
+    pbuf_header(nb, -(int)sizeof(struct pppInputHeader));
+
+#if LINK_STATS
+    lwip_stats.link.recv++;
+#endif /* LINK_STATS */
+
+    /*
+     * Toss all non-LCP packets unless LCP is OPEN.
+     * Until we get past the authentication phase, toss all packets
+     * except LCP, LQR and authentication packets.
+     */
+    if((lcp_phase[pd] <= PHASE_AUTHENTICATE) && (protocol != PPP_LCP)) {
+	    if(!((protocol == PPP_LQR) || (protocol == PPP_PAP) || (protocol == PPP_CHAP)) ||
+			(lcp_phase[pd] != PHASE_AUTHENTICATE)) {
+		PPPDEBUG((LOG_INFO, "pppInput: discarding proto 0x%04X in phase %d\n", protocol, lcp_phase[pd]));
+		goto drop;
+	    }
+    }
+
+    switch(protocol) {
+    case PPP_VJC_COMP:      /* VJ compressed TCP */
+#if VJ_SUPPORT > 0
+        PPPDEBUG((LOG_INFO, "pppInput[%d]: vj_comp in pbuf len=%d\n", pd, nb->len));
+        /*
+         * Clip off the VJ header and prepend the rebuilt TCP/IP header and
+         * pass the result to IP.
+         */
+        if (vj_uncompress_tcp(&nb, &pppControl[pd].vjComp) >= 0) {
+            pppControl[pd].netif.input(nb, &pppControl[pd].netif);
+			return;
+        }
+	/* Something's wrong so drop it. */
+	PPPDEBUG((LOG_WARNING, "pppInput[%d]: Dropping VJ compressed\n", pd));
+#else
+        /* No handler for this protocol so drop the packet. */
+        PPPDEBUG((LOG_INFO, "pppInput[%d]: drop VJ Comp in %d:%s\n", pd, nb->len, nb->payload));
+#endif /* VJ_SUPPORT > 0 */
+	break;
+    case PPP_VJC_UNCOMP:    /* VJ uncompressed TCP */
+#if VJ_SUPPORT > 0
+        PPPDEBUG((LOG_INFO, "pppInput[%d]: vj_un in pbuf len=%d\n", pd, nb->len));
+        /*
+         * Process the TCP/IP header for VJ header compression and then pass
+         * the packet to IP.
+         */
+        if (vj_uncompress_uncomp(nb, &pppControl[pd].vjComp) >= 0) {
+            pppControl[pd].netif.input(nb, &pppControl[pd].netif);
+			return;
+        }
+	/* Something's wrong so drop it. */
+	PPPDEBUG((LOG_WARNING, "pppInput[%d]: Dropping VJ uncompressed\n", pd));
+#else
+        /* No handler for this protocol so drop the packet. */
+        PPPDEBUG((LOG_INFO,
+                    "pppInput[%d]: drop VJ UnComp in %d:.*H\n", 
+                    pd, nb->len, LWIP_MIN(nb->len * 2, 40), nb->payload));
+#endif /* VJ_SUPPORT > 0 */
+	break;
+    case PPP_IP:            /* Internet Protocol */
+        PPPDEBUG((LOG_INFO, "pppInput[%d]: ip in pbuf len=%d\n", pd, nb->len));
+        pppControl[pd].netif.input(nb, &pppControl[pd].netif);
+		return;
+    default:
+	{
+		struct protent *protp;
+		int i;
+
+		/*
+		 * Upcall the proper protocol input routine.
+		 */
+		for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) {
+			if (protp->protocol == protocol && protp->enabled_flag) {
+				PPPDEBUG((LOG_INFO, "pppInput[%d]: %s len=%d\n", pd, protp->name, nb->len));
+				nb = pppSingleBuf(nb);
+				(*protp->input)(pd, nb->payload, nb->len);
+				goto out;
+			}
+		}
+
+		/* No handler for this protocol so reject the packet. */
+		PPPDEBUG((LOG_INFO, "pppInput[%d]: rejecting unsupported proto 0x%04X len=%d\n", pd, protocol, nb->len));
+		pbuf_header(nb, sizeof(protocol));
+#if BYTE_ORDER == LITTLE_ENDIAN
+		protocol = htons(protocol);
+		memcpy(nb->payload, &protocol, sizeof(protocol));
+#endif
+		lcp_sprotrej(pd, nb->payload, nb->len);
+	}
+	break;
+    }
+
+drop:
+#if LINK_STATS
+    lwip_stats.link.drop++;
+#endif
+
+out:
+    pbuf_free(nb);
+    return;
+}
+
+
+/*
+ * Drop the input packet.
+ */
+static void pppDrop(PPPControl *pc)
+{
+    if (pc->inHead != NULL) {
+#if 0	    
+        PPPDEBUG((LOG_INFO, "pppDrop: %d:%.*H\n", pc->inHead->len, min(60, pc->inHead->len * 2), pc->inHead->payload));
+#endif	
+        PPPDEBUG((LOG_INFO, "pppDrop: pbuf len=%d\n", pc->inHead->len));
+	if (pc->inTail && (pc->inTail != pc->inHead))
+	    pbuf_free(pc->inTail);
+        pbuf_free(pc->inHead);
+        pc->inHead = NULL;
+        pc->inTail = NULL;
+    }
+#if VJ_SUPPORT > 0
+    vj_uncompress_err(&pc->vjComp);
+#endif
+
+#if LINK_STATS
+    lwip_stats.link.drop++;
+#endif /* LINK_STATS */
+}
+
+
+/*
+ * Process a received octet string.
+ */
+static void pppInProc(int pd, u_char *s, int l)
+{
+    PPPControl *pc = &pppControl[pd];
+    struct pbuf *nextNBuf;
+    u_char curChar;
+
+    PPPDEBUG((LOG_DEBUG, "pppInProc[%d]: got %d bytes\n", pd, l));
+    while (l-- > 0) {
+        curChar = *s++;
+        
+        /* Handle special characters. */
+        if (ESCAPE_P(pc->inACCM, curChar)) {
+            /* Check for escape sequences. */
+            /* XXX Note that this does not handle an escaped 0x5d character which
+             * would appear as an escape character.  Since this is an ASCII ']'
+             * and there is no reason that I know of to escape it, I won't complicate
+             * the code to handle this case. GLL */
+            if (curChar == PPP_ESCAPE)
+                pc->inEscaped = 1;
+            /* Check for the flag character. */
+            else if (curChar == PPP_FLAG) {
+                /* If this is just an extra flag character, ignore it. */
+                if (pc->inState <= PDADDRESS)
+                    ;
+                /* If we haven't received the packet header, drop what has come in. */
+                else if (pc->inState < PDDATA) {
+                    PPPDEBUG((LOG_WARNING,
+                                "pppInProc[%d]: Dropping incomplete packet %d\n", 
+                                pd, pc->inState));
+#if LINK_STATS
+					lwip_stats.link.lenerr++;
+#endif
+                    pppDrop(pc);
+                }
+                /* If the fcs is invalid, drop the packet. */
+                else if (pc->inFCS != PPP_GOODFCS) {
+                    PPPDEBUG((LOG_INFO,
+                                "pppInProc[%d]: Dropping bad fcs 0x%04X proto=0x%04X\n", 
+                                pd, pc->inFCS, pc->inProtocol));
+#if LINK_STATS
+					lwip_stats.link.chkerr++;
+#endif
+                    pppDrop(pc);
+                }
+                /* Otherwise it's a good packet so pass it on. */
+                else {
+                    
+                    /* Trim off the checksum. */
+		    if(pc->inTail->len >= 2) {
+			pc->inTail->len -= 2;
+
+			pc->inTail->tot_len = pc->inTail->len;
+			if (pc->inTail != pc->inHead) {
+			    pbuf_cat(pc->inHead, pc->inTail);
+			}
+		    } else {
+			pc->inTail->tot_len = pc->inTail->len;
+			if (pc->inTail != pc->inHead) {
+			    pbuf_cat(pc->inHead, pc->inTail);
+			}
+
+			pbuf_realloc(pc->inHead, pc->inHead->tot_len - 2);
+		    }
+
+                    /* Dispatch the packet thereby consuming it. */
+		    if(tcpip_callback(pppInput, pc->inHead) != ERR_OK) {
+                    	PPPDEBUG((LOG_ERR,
+				    "pppInProc[%d]: tcpip_callback() failed, dropping packet\n", pd));
+			pbuf_free(pc->inHead);
+#if LINK_STATS
+			lwip_stats.link.drop++;
+#endif
+		    }
+                    pc->inHead = NULL;
+                    pc->inTail = NULL;
+                }
+                    
+                /* Prepare for a new packet. */
+                pc->inFCS = PPP_INITFCS;
+                pc->inState = PDADDRESS;
+                pc->inEscaped = 0;
+            }
+            /* Other characters are usually control characters that may have
+             * been inserted by the physical layer so here we just drop them. */
+            else {
+                PPPDEBUG((LOG_WARNING,
+                            "pppInProc[%d]: Dropping ACCM char <%d>\n", pd, curChar));
+            }
+        }
+        /* Process other characters. */
+        else {
+            /* Unencode escaped characters. */
+            if (pc->inEscaped) {
+                pc->inEscaped = 0;
+                curChar ^= PPP_TRANS;
+            }
+            
+            /* Process character relative to current state. */
+            switch(pc->inState) {
+            case PDIDLE:                    /* Idle state - waiting. */
+                /* Drop the character if it's not 0xff
+                 * we would have processed a flag character above. */
+                if (curChar != PPP_ALLSTATIONS) {
+                	break;
+				}
+
+				/* Fall through */
+            case PDSTART:                   /* Process start flag. */
+                /* Prepare for a new packet. */
+                pc->inFCS = PPP_INITFCS;
+
+				/* Fall through */
+            case PDADDRESS:                 /* Process address field. */
+                if (curChar == PPP_ALLSTATIONS) {
+                    pc->inState = PDCONTROL;
+                    break;
+                }
+                /* Else assume compressed address and control fields so
+                 * fall through to get the protocol... */
+            case PDCONTROL:                 /* Process control field. */
+                /* If we don't get a valid control code, restart. */
+                if (curChar == PPP_UI) {
+                    pc->inState = PDPROTOCOL1;
+                	break;
+                }
+#if 0
+                else {
+                    PPPDEBUG((LOG_WARNING,
+                                "pppInProc[%d]: Invalid control <%d>\n", pd, curChar));
+                    pc->inState = PDSTART;
+                }
+#endif
+            case PDPROTOCOL1:               /* Process protocol field 1. */
+                /* If the lower bit is set, this is the end of the protocol
+                 * field. */
+                if (curChar & 1) {
+                    pc->inProtocol = curChar;
+                    pc->inState = PDDATA;
+                }
+                else {
+                    pc->inProtocol = (u_int)curChar << 8;
+                    pc->inState = PDPROTOCOL2;
+                }
+                break;
+            case PDPROTOCOL2:               /* Process protocol field 2. */
+                pc->inProtocol |= curChar;
+                pc->inState = PDDATA;
+                break;
+            case PDDATA:                    /* Process data byte. */
+                /* Make space to receive processed data. */
+                if (pc->inTail == NULL || pc->inTail->len == PBUF_POOL_BUFSIZE) {
+		    if(pc->inTail) {
+			pc->inTail->tot_len = pc->inTail->len;
+			if (pc->inTail != pc->inHead) {
+			    pbuf_cat(pc->inHead, pc->inTail);
+			}
+		    }
+                    /* If we haven't started a packet, we need a packet header. */
+                    nextNBuf = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL);
+                    if (nextNBuf == NULL) {
+                        /* No free buffers.  Drop the input packet and let the
+                         * higher layers deal with it.  Continue processing
+                         * the received pbuf chain in case a new packet starts. */
+                        PPPDEBUG((LOG_ERR, "pppInProc[%d]: NO FREE MBUFS!\n", pd));
+#if LINK_STATS
+						lwip_stats.link.memerr++;
+#endif /* LINK_STATS */
+                        pppDrop(pc);
+                        pc->inState = PDSTART;  /* Wait for flag sequence. */
+			break;
+                    }
+		    if (pc->inHead == NULL) {
+			struct pppInputHeader *pih = nextNBuf->payload;
+
+			pih->unit = pd;
+			pih->proto = pc->inProtocol;
+
+			nextNBuf->len += sizeof(*pih);
+
+			pc->inHead = nextNBuf;
+		    }
+		    pc->inTail = nextNBuf;
+                }
+                /* Load character into buffer. */
+                ((u_char*)pc->inTail->payload)[pc->inTail->len++] = curChar;
+                break;
+            }
+
+            /* update the frame check sequence number. */
+            pc->inFCS = PPP_FCS(pc->inFCS, curChar);
+        }
+    }
+	avRandomize();
+}
+
+#endif /* PPP_SUPPORT */
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/ppp.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/ppp.h
new file mode 100644
index 000000000..bd45a3c1d
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/ppp.h
@@ -0,0 +1,446 @@
+/*****************************************************************************
+* ppp.h - Network Point to Point Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-11-05 Guy Lancaster , Global Election Systems Inc.
+*	Original derived from BSD codes.
+*****************************************************************************/
+
+#ifndef PPP_H
+#define PPP_H
+
+#include "lwip/opt.h"
+
+#if PPP_SUPPORT > 0
+#include "lwip/sio.h"
+#include "lwip/api.h"
+#include "lwip/sockets.h"
+#include "lwip/stats.h"
+#include "lwip/mem.h"
+#include "lwip/tcpip.h"
+#include "lwip/netif.h"
+
+/*
+ * pppd.h - PPP daemon global declarations.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ */
+/*
+ * ppp_defs.h - PPP definitions.
+ *
+ * Copyright (c) 1994 The Australian National University.
+ * All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, provided that the above copyright
+ * notice appears in all copies.  This software is provided without any
+ * warranty, express or implied. The Australian National University
+ * makes no representations about the suitability of this software for
+ * any purpose.
+ *
+ * IN NO EVENT SHALL THE AUSTRALIAN NATIONAL UNIVERSITY BE LIABLE TO ANY
+ * PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES
+ * ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF
+ * THE AUSTRALIAN NATIONAL UNIVERSITY HAVE BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * THE AUSTRALIAN NATIONAL UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE.  THE SOFTWARE PROVIDED HEREUNDER IS
+ * ON AN "AS IS" BASIS, AND THE AUSTRALIAN NATIONAL UNIVERSITY HAS NO
+ * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS,
+ * OR MODIFICATIONS.
+ */
+
+#define TIMEOUT(f, a, t)    sys_untimeout((f), (a)), sys_timeout((t)*1000, (f), (a))
+#define UNTIMEOUT(f, a)     sys_untimeout((f), (a))
+
+
+# ifndef __u_char_defined
+
+/* Type definitions for BSD code. */
+typedef unsigned long u_long;
+typedef unsigned int u_int;
+typedef unsigned short u_short;
+typedef unsigned char u_char;
+
+#endif
+
+/*
+ * Constants and structures defined by the internet system,
+ * Per RFC 790, September 1981, and numerous additions.
+ */
+
+/*
+ * The basic PPP frame.
+ */
+#define PPP_HDRLEN  4       /* octets for standard ppp header */
+#define PPP_FCSLEN  2       /* octets for FCS */
+
+
+/*
+ * Significant octet values.
+ */
+#define PPP_ALLSTATIONS 0xff    /* All-Stations broadcast address */
+#define PPP_UI          0x03    /* Unnumbered Information */
+#define PPP_FLAG        0x7e    /* Flag Sequence */
+#define PPP_ESCAPE      0x7d    /* Asynchronous Control Escape */
+#define PPP_TRANS       0x20    /* Asynchronous transparency modifier */
+
+/*
+ * Protocol field values.
+ */
+#define PPP_IP          0x21    /* Internet Protocol */
+#define PPP_AT          0x29    /* AppleTalk Protocol */
+#define PPP_VJC_COMP    0x2d    /* VJ compressed TCP */
+#define PPP_VJC_UNCOMP  0x2f    /* VJ uncompressed TCP */
+#define PPP_COMP        0xfd    /* compressed packet */
+#define PPP_IPCP        0x8021  /* IP Control Protocol */
+#define PPP_ATCP        0x8029  /* AppleTalk Control Protocol */
+#define PPP_CCP         0x80fd  /* Compression Control Protocol */
+#define PPP_LCP         0xc021  /* Link Control Protocol */
+#define PPP_PAP         0xc023  /* Password Authentication Protocol */
+#define PPP_LQR         0xc025  /* Link Quality Report protocol */
+#define PPP_CHAP        0xc223  /* Cryptographic Handshake Auth. Protocol */
+#define PPP_CBCP        0xc029  /* Callback Control Protocol */
+
+/*
+ * Values for FCS calculations.
+ */
+#define PPP_INITFCS 0xffff  /* Initial FCS value */
+#define PPP_GOODFCS 0xf0b8  /* Good final FCS value */
+#define PPP_FCS(fcs, c) (((fcs) >> 8) ^ fcstab[((fcs) ^ (c)) & 0xff])
+
+/*
+ * Extended asyncmap - allows any character to be escaped.
+ */
+typedef u_char  ext_accm[32];
+
+/*
+ * What to do with network protocol (NP) packets.
+ */
+enum NPmode {
+    NPMODE_PASS,        /* pass the packet through */
+    NPMODE_DROP,        /* silently drop the packet */
+    NPMODE_ERROR,       /* return an error */
+    NPMODE_QUEUE        /* save it up for later. */
+};
+
+/*
+ * Inline versions of get/put char/short/long.
+ * Pointer is advanced; we assume that both arguments
+ * are lvalues and will already be in registers.
+ * cp MUST be u_char *.
+ */
+#define GETCHAR(c, cp) { \
+    (c) = *(cp)++; \
+}
+#define PUTCHAR(c, cp) { \
+    *(cp)++ = (u_char) (c); \
+}
+
+
+#define GETSHORT(s, cp) { \
+    (s) = *(cp)++ << 8; \
+    (s) |= *(cp)++; \
+}
+#define PUTSHORT(s, cp) { \
+    *(cp)++ = (u_char) ((s) >> 8); \
+    *(cp)++ = (u_char) (s); \
+}
+
+#define GETLONG(l, cp) { \
+    (l) = *(cp)++ << 8; \
+    (l) |= *(cp)++; (l) <<= 8; \
+    (l) |= *(cp)++; (l) <<= 8; \
+    (l) |= *(cp)++; \
+}
+#define PUTLONG(l, cp) { \
+    *(cp)++ = (u_char) ((l) >> 24); \
+    *(cp)++ = (u_char) ((l) >> 16); \
+    *(cp)++ = (u_char) ((l) >> 8); \
+    *(cp)++ = (u_char) (l); \
+}
+
+
+#define INCPTR(n, cp)   ((cp) += (n))
+#define DECPTR(n, cp)   ((cp) -= (n))
+
+#define BCMP(s0, s1, l)     memcmp((u_char *)(s0), (u_char *)(s1), (l))
+#define BCOPY(s, d, l)      memcpy((d), (s), (l))
+#define BZERO(s, n)         memset(s, 0, n)
+#if PPP_DEBUG
+#define PRINTMSG(m, l)  { m[l] = '\0'; ppp_trace(LOG_INFO, "Remote message: %s\n", m); }
+#else
+#define PRINTMSG(m, l)
+#endif
+
+/*
+ * MAKEHEADER - Add PPP Header fields to a packet.
+ */
+#define MAKEHEADER(p, t) { \
+    PUTCHAR(PPP_ALLSTATIONS, p); \
+    PUTCHAR(PPP_UI, p); \
+    PUTSHORT(t, p); }
+
+/*************************
+*** PUBLIC DEFINITIONS ***
+*************************/
+
+/* Error codes. */
+#define PPPERR_NONE 0				/* No error. */
+#define PPPERR_PARAM -1				/* Invalid parameter. */
+#define PPPERR_OPEN -2				/* Unable to open PPP session. */
+#define PPPERR_DEVICE -3			/* Invalid I/O device for PPP. */
+#define PPPERR_ALLOC -4				/* Unable to allocate resources. */
+#define PPPERR_USER -5				/* User interrupt. */
+#define PPPERR_CONNECT -6			/* Connection lost. */
+#define PPPERR_AUTHFAIL -7			/* Failed authentication challenge. */
+#define PPPERR_PROTOCOL -8			/* Failed to meet protocol. */
+
+/*
+ * PPP IOCTL commands.
+ */
+/*
+ * Get the up status - 0 for down, non-zero for up.  The argument must
+ * point to an int.
+ */
+#define PPPCTLG_UPSTATUS 100	/* Get the up status - 0 down else up */
+#define PPPCTLS_ERRCODE 101		/* Set the error code */
+#define PPPCTLG_ERRCODE 102		/* Get the error code */
+#define	PPPCTLG_FD		103		/* Get the fd associated with the ppp */
+
+/************************
+*** PUBLIC DATA TYPES ***
+************************/
+
+/*
+ * The following struct gives the addresses of procedures to call
+ * for a particular protocol.
+ */
+struct protent {
+    u_short protocol;       /* PPP protocol number */
+    /* Initialization procedure */
+    void (*init) (int unit);
+    /* Process a received packet */
+    void (*input) (int unit, u_char *pkt, int len);
+    /* Process a received protocol-reject */
+    void (*protrej) (int unit);
+    /* Lower layer has come up */
+    void (*lowerup) (int unit);
+    /* Lower layer has gone down */
+    void (*lowerdown) (int unit);
+    /* Open the protocol */
+    void (*open) (int unit);
+    /* Close the protocol */
+    void (*close) (int unit, char *reason);
+#if 0
+    /* Print a packet in readable form */
+    int  (*printpkt) (u_char *pkt, int len,
+              void (*printer) (void *, char *, ...),
+              void *arg);
+    /* Process a received data packet */
+    void (*datainput) (int unit, u_char *pkt, int len);
+#endif
+    int  enabled_flag;      /* 0 iff protocol is disabled */
+    char *name;         /* Text name of protocol */
+#if 0
+    /* Check requested options, assign defaults */
+    void (*check_options) (u_long);
+    /* Configure interface for demand-dial */
+    int  (*demand_conf) (int unit);
+    /* Say whether to bring up link for this pkt */
+    int  (*active_pkt) (u_char *pkt, int len);
+#endif
+};
+
+/*
+ * The following structure records the time in seconds since
+ * the last NP packet was sent or received.
+ */
+struct ppp_idle {
+    u_short xmit_idle;      /* seconds since last NP packet sent */
+    u_short recv_idle;      /* seconds since last NP packet received */
+};
+
+struct ppp_settings {
+
+	u_int  disable_defaultip : 1;   /* Don't use hostname for default IP addrs */
+	u_int  auth_required : 1;      /* Peer is required to authenticate */
+	u_int  explicit_remote : 1;    /* remote_name specified with remotename opt */
+	u_int  refuse_pap : 1;         /* Don't wanna auth. ourselves with PAP */
+	u_int  refuse_chap : 1;        /* Don't wanna auth. ourselves with CHAP */
+	u_int  usehostname : 1;        /* Use hostname for our_name */
+	u_int  usepeerdns : 1;         /* Ask peer for DNS adds */
+
+	u_short idle_time_limit; /* Shut down link if idle for this long */
+	int  maxconnect;         /* Maximum connect time (seconds) */
+
+	char user[MAXNAMELEN + 1];/* Username for PAP */
+	char passwd[MAXSECRETLEN + 1];           /* Password for PAP, secret for CHAP */
+	char our_name[MAXNAMELEN + 1];         /* Our name for authentication purposes */
+	char remote_name[MAXNAMELEN + 1];      /* Peer's name for authentication */
+};
+
+struct ppp_addrs {
+    struct ip_addr our_ipaddr, his_ipaddr, netmask, dns1, dns2;
+};
+
+/*****************************
+*** PUBLIC DATA STRUCTURES ***
+*****************************/
+/* Buffers for outgoing packets. */
+extern u_char outpacket_buf[NUM_PPP][PPP_MRU+PPP_HDRLEN];
+
+extern struct ppp_settings ppp_settings;
+
+extern struct protent *ppp_protocols[];/* Table of pointers to supported protocols */
+
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+
+/* Initialize the PPP subsystem. */
+void pppInit(void);
+
+/* Warning: Using PPPAUTHTYPE_ANY might have security consequences.
+ * RFC 1994 says:
+ *
+ * In practice, within or associated with each PPP server, there is a
+ * database which associates "user" names with authentication
+ * information ("secrets").  It is not anticipated that a particular
+ * named user would be authenticated by multiple methods.  This would
+ * make the user vulnerable to attacks which negotiate the least secure
+ * method from among a set (such as PAP rather than CHAP).  If the same
+ * secret was used, PAP would reveal the secret to be used later with
+ * CHAP.
+ *
+ * Instead, for each user name there should be an indication of exactly
+ * one method used to authenticate that user name.  If a user needs to
+ * make use of different authentication methods under different
+ * circumstances, then distinct user names SHOULD be employed, each of
+ * which identifies exactly one authentication method.
+ *
+ */
+enum pppAuthType {
+    PPPAUTHTYPE_NONE,
+    PPPAUTHTYPE_ANY,
+    PPPAUTHTYPE_PAP,
+    PPPAUTHTYPE_CHAP
+};
+
+void pppSetAuth(enum pppAuthType authType, const char *user, const char *passwd);
+
+/*
+ * Open a new PPP connection using the given I/O device.
+ * This initializes the PPP control block but does not
+ * attempt to negotiate the LCP session.
+ * Return a new PPP connection descriptor on success or
+ * an error code (negative) on failure. 
+ */
+int pppOpen(sio_fd_t fd, void (*linkStatusCB)(void *ctx, int errCode, void *arg), void *linkStatusCtx);
+
+/*
+ * Close a PPP connection and release the descriptor. 
+ * Any outstanding packets in the queues are dropped.
+ * Return 0 on success, an error code on failure. 
+ */
+int pppClose(int pd);
+
+/*
+ * Indicate to the PPP process that the line has disconnected.
+ */
+void pppSigHUP(int pd);
+
+/*
+ * Get and set parameters for the given connection.
+ * Return 0 on success, an error code on failure. 
+ */
+int  pppIOCtl(int pd, int cmd, void *arg);
+
+/*
+ * Return the Maximum Transmission Unit for the given PPP connection.
+ */
+u_int pppMTU(int pd);
+
+/*
+ * Write n characters to a ppp link.
+ *	RETURN: >= 0 Number of characters written
+ *		 	 -1 Failed to write to device
+ */
+int pppWrite(int pd, const u_char *s, int n);
+
+void pppMainWakeup(int pd);
+
+/* Configure i/f transmit parameters */
+void ppp_send_config (int, int, u32_t, int, int);
+/* Set extended transmit ACCM */
+void ppp_set_xaccm (int, ext_accm *);
+/* Configure i/f receive parameters */
+void ppp_recv_config (int, int, u32_t, int, int);
+/* Find out how long link has been idle */
+int  get_idle_time (int, struct ppp_idle *);
+
+/* Configure VJ TCP header compression */
+int  sifvjcomp (int, int, int, int);
+/* Configure i/f down (for IP) */
+int  sifup (int);		
+/* Set mode for handling packets for proto */
+int  sifnpmode (int u, int proto, enum NPmode mode);
+/* Configure i/f down (for IP) */
+int  sifdown (int);	
+/* Configure IP addresses for i/f */
+int  sifaddr (int, u32_t, u32_t, u32_t, u32_t, u32_t);
+/* Reset i/f IP addresses */
+int  cifaddr (int, u32_t, u32_t);
+/* Create default route through i/f */
+int  sifdefaultroute (int, u32_t, u32_t);
+/* Delete default route through i/f */
+int  cifdefaultroute (int, u32_t, u32_t);
+
+/* Get appropriate netmask for address */
+u32_t GetMask (u32_t); 
+
+#endif /* PPP_SUPPORT */
+
+#endif /* PPP_H */
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/pppdebug.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/pppdebug.h
new file mode 100644
index 000000000..e4cf25a39
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/pppdebug.h
@@ -0,0 +1,89 @@
+/*****************************************************************************
+* pppdebug.h - System debugging utilities.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1998 Global Election Systems Inc.
+* portions Copyright (c) 2001 by Cognizant Pty Ltd.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY (please don't use tabs!)
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 98-07-29 Guy Lancaster , Global Election Systems Inc.
+*	Original.
+*
+*****************************************************************************
+*/
+#ifndef PPPDEBUG_H
+#define PPPDEBUG_H
+
+/************************
+*** PUBLIC DATA TYPES ***
+************************/
+/* Trace levels. */
+typedef enum {
+	LOG_CRITICAL = 0,
+	LOG_ERR = 1,
+	LOG_NOTICE = 2,
+	LOG_WARNING = 3,
+	LOG_INFO = 5,
+	LOG_DETAIL = 6,
+	LOG_DEBUG = 7
+} LogCodes;
+
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+/*
+ *	ppp_trace - a form of printf to send tracing information to stderr
+ */
+void ppp_trace(int level, const char *format,...);
+
+#if PPP_DEBUG > 0
+
+#define AUTHDEBUG(a) ppp_trace a
+#define IPCPDEBUG(a) ppp_trace a
+#define UPAPDEBUG(a) ppp_trace a
+#define LCPDEBUG(a) ppp_trace a
+#define FSMDEBUG(a) ppp_trace a
+#define CHAPDEBUG(a) ppp_trace a
+#define PPPDEBUG(a) ppp_trace a
+
+#define TRACELCP 1
+
+#else
+
+#define AUTHDEBUG(a)
+#define IPCPDEBUG(a)
+#define UPAPDEBUG(a)
+#define LCPDEBUG(a)
+#define FSMDEBUG(a)
+#define CHAPDEBUG(a)
+
+#define PPPDEBUG(a)
+
+#define TRACELCP 0
+
+#endif
+
+#endif /* PPPDEBUG_H */
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/randm.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/randm.c
new file mode 100644
index 000000000..d4431dd8e
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/randm.c
@@ -0,0 +1,242 @@
+/*****************************************************************************
+* randm.c - Random number generator program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* Copyright (c) 1998 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 98-06-03 Guy Lancaster , Global Election Systems Inc.
+*   Extracted from avos.
+*****************************************************************************/
+
+#include "ppp.h"
+#if PPP_SUPPORT > 0
+#include "md5.h"
+#include "randm.h"
+
+#include "pppdebug.h"
+
+
+#if MD5_SUPPORT>0   /* this module depends on MD5 */
+#define RANDPOOLSZ 16   /* Bytes stored in the pool of randomness. */
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+static char randPool[RANDPOOLSZ];   /* Pool of randomness. */
+static long randCount = 0;      /* Pseudo-random incrementer */
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ * Initialize the random number generator.
+ *
+ * Since this is to be called on power up, we don't have much
+ *  system randomess to work with.  Here all we use is the
+ *  real-time clock.  We'll accumulate more randomness as soon
+ *  as things start happening.
+ */
+void avRandomInit()
+{
+    avChurnRand(NULL, 0);
+}
+
+/*
+ * Churn the randomness pool on a random event.  Call this early and often
+ *  on random and semi-random system events to build randomness in time for
+ *  usage.  For randomly timed events, pass a null pointer and a zero length
+ *  and this will use the system timer and other sources to add randomness.
+ *  If new random data is available, pass a pointer to that and it will be
+ *  included.
+ *
+ * Ref: Applied Cryptography 2nd Ed. by Bruce Schneier p. 427
+ */
+void avChurnRand(char *randData, u32_t randLen)
+{
+    MD5_CTX md5;
+
+/*  ppp_trace(LOG_INFO, "churnRand: %u@%P\n", randLen, randData); */
+    MD5Init(&md5);
+    MD5Update(&md5, (u_char *)randPool, sizeof(randPool));
+    if (randData)
+        MD5Update(&md5, (u_char *)randData, randLen);
+    else {
+        struct {
+            /* INCLUDE fields for any system sources of randomness */
+            char foobar;
+        } sysData;
+
+        /* Load sysData fields here. */
+        ;
+        MD5Update(&md5, (u_char *)&sysData, sizeof(sysData));
+    }
+    MD5Final((u_char *)randPool, &md5);
+/*  ppp_trace(LOG_INFO, "churnRand: -> 0\n"); */
+}
+
+/*
+ * Use the random pool to generate random data.  This degrades to pseudo
+ *  random when used faster than randomness is supplied using churnRand().
+ * Note: It's important that there be sufficient randomness in randPool
+ *  before this is called for otherwise the range of the result may be
+ *  narrow enough to make a search feasible.
+ *
+ * Ref: Applied Cryptography 2nd Ed. by Bruce Schneier p. 427
+ *
+ * XXX Why does he not just call churnRand() for each block?  Probably
+ *  so that you don't ever publish the seed which could possibly help
+ *  predict future values.
+ * XXX Why don't we preserve md5 between blocks and just update it with
+ *  randCount each time?  Probably there is a weakness but I wish that
+ *  it was documented.
+ */
+void avGenRand(char *buf, u32_t bufLen)
+{
+    MD5_CTX md5;
+    u_char tmp[16];
+    u32_t n;
+
+    while (bufLen > 0) {
+        n = LWIP_MIN(bufLen, RANDPOOLSZ);
+        MD5Init(&md5);
+        MD5Update(&md5, (u_char *)randPool, sizeof(randPool));
+        MD5Update(&md5, (u_char *)&randCount, sizeof(randCount));
+        MD5Final(tmp, &md5);
+        randCount++;
+        memcpy(buf, tmp, n);
+        buf += n;
+        bufLen -= n;
+    }
+}
+
+/*
+ * Return a new random number.
+ */
+u32_t avRandom()
+{
+    u32_t newRand;
+
+    avGenRand((char *)&newRand, sizeof(newRand));
+
+    return newRand;
+}
+
+#else /* MD5_SUPPORT */
+
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+static int  avRandomized = 0;       /* Set when truely randomized. */
+static u32_t avRandomSeed = 0;      /* Seed used for random number generation. */
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ * Initialize the random number generator.
+ *
+ * Here we attempt to compute a random number seed but even if
+ * it isn't random, we'll randomize it later.
+ *
+ * The current method uses the fields from the real time clock,
+ * the idle process counter, the millisecond counter, and the
+ * hardware timer tick counter.  When this is invoked
+ * in startup(), then the idle counter and timer values may
+ * repeat after each boot and the real time clock may not be
+ * operational.  Thus we call it again on the first random
+ * event.
+ */
+void avRandomInit()
+{
+#if 0
+    /* Get a pointer into the last 4 bytes of clockBuf. */
+    u32_t *lptr1 = (u32_t *)((char *)&clockBuf[3]);
+
+    /*
+     * Initialize our seed using the real-time clock, the idle
+     * counter, the millisecond timer, and the hardware timer
+     * tick counter.  The real-time clock and the hardware
+     * tick counter are the best sources of randomness but
+     * since the tick counter is only 16 bit (and truncated
+     * at that), the idle counter and millisecond timer
+     * (which may be small values) are added to help
+     * randomize the lower 16 bits of the seed.
+     */
+    readClk();
+    avRandomSeed += *(u32_t *)clockBuf + *lptr1 + OSIdleCtr
+             + ppp_mtime() + ((u32_t)TM1 << 16) + TM1;
+#else
+    avRandomSeed += sys_jiffies(); /* XXX */
+#endif
+        
+    /* Initialize the Borland random number generator. */
+    srand((unsigned)avRandomSeed);
+}
+
+/*
+ * Randomize our random seed value.  Here we use the fact that
+ * this function is called at *truely random* times by the polling
+ * and network functions.  Here we only get 16 bits of new random
+ * value but we use the previous value to randomize the other 16
+ * bits.
+ */
+void avRandomize(void)
+{
+    static u32_t last_jiffies;
+
+    if (!avRandomized) {
+        avRandomized = !0;
+        avRandomInit();
+        /* The initialization function also updates the seed. */
+    } else {
+/*        avRandomSeed += (avRandomSeed << 16) + TM1; */
+    	avRandomSeed += (sys_jiffies() - last_jiffies); /* XXX */
+    }
+    last_jiffies = sys_jiffies();
+}
+
+/*
+ * Return a new random number.
+ * Here we use the Borland rand() function to supply a pseudo random
+ * number which we make truely random by combining it with our own
+ * seed which is randomized by truely random events. 
+ * Thus the numbers will be truely random unless there have been no
+ * operator or network events in which case it will be pseudo random
+ * seeded by the real time clock.
+ */
+u32_t avRandom()
+{
+    return ((((u32_t)rand() << 16) + rand()) + avRandomSeed);
+}
+
+
+
+#endif /* MD5_SUPPORT */
+#endif /* PPP_SUPPORT */
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/randm.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/randm.h
new file mode 100644
index 000000000..2563d8976
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/randm.h
@@ -0,0 +1,81 @@
+/*****************************************************************************
+* randm.h - Random number generator header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* Copyright (c) 1998 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 98-05-29 Guy Lancaster , Global Election Systems Inc.
+*	Extracted from avos.
+*****************************************************************************/
+
+#ifndef RANDM_H
+#define RANDM_H
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+/*
+ * Initialize the random number generator.
+ */
+void avRandomInit(void);
+
+/*
+ * Churn the randomness pool on a random event.  Call this early and often
+ *	on random and semi-random system events to build randomness in time for
+ *	usage.  For randomly timed events, pass a null pointer and a zero length
+ *	and this will use the system timer and other sources to add randomness.
+ *	If new random data is available, pass a pointer to that and it will be
+ *	included.
+ */
+void avChurnRand(char *randData, u32_t randLen);
+
+/*
+ * Randomize our random seed value.  To be called for truely random events
+ * such as user operations and network traffic.
+ */
+#if MD5_SUPPORT
+#define avRandomize()	avChurnRand(NULL, 0)
+#else
+void avRandomize(void);
+#endif
+
+/*
+ * Use the random pool to generate random data.  This degrades to pseudo
+ *	random when used faster than randomness is supplied using churnRand().
+ *	Thus it's important to make sure that the results of this are not
+ *	published directly because one could predict the next result to at
+ *	least some degree.  Also, it's important to get a good seed before
+ *	the first use.
+ */
+void avGenRand(char *buf, u32_t bufLen);
+
+/*
+ * Return a new random number.
+ */
+u32_t avRandom(void);
+
+
+#endif /* RANDM_H */
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/vj.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/vj.c
new file mode 100644
index 000000000..2c11affe3
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/vj.c
@@ -0,0 +1,633 @@
+/*
+ * Routines to compress and uncompess tcp packets (for transmission
+ * over low speed serial lines.
+ *
+ * Copyright (c) 1989 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the University of California, Berkeley.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *	Van Jacobson (van@helios.ee.lbl.gov), Dec 31, 1989:
+ *	- Initial distribution.
+ *
+ * Modified June 1993 by Paul Mackerras, paulus@cs.anu.edu.au,
+ * so that the entire packet being decompressed doesn't have
+ * to be in contiguous memory (just the compressed header).
+ *
+ * Modified March 1998 by Guy Lancaster, glanca@gesn.com,
+ * for a 16 bit processor.
+ */
+
+#include 
+
+#include "ppp.h"
+#include "vj.h"
+#include "pppdebug.h"
+
+#if VJ_SUPPORT > 0
+
+#if LINK_STATS
+#define INCR(counter) ++comp->stats.counter
+#else
+#define INCR(counter)
+#endif
+
+#if defined(NO_CHAR_BITFIELDS)
+#define getip_hl(base)	((base).ip_hl_v&0xf)
+#define getth_off(base)	(((base).th_x2_off&0xf0)>>4)
+#else
+#define getip_hl(base)	((base).ip_hl)
+#define getth_off(base)	((base).th_off)
+#endif
+
+void vj_compress_init(struct vjcompress *comp)
+{
+	register u_int i;
+	register struct cstate *tstate = comp->tstate;
+	
+#if MAX_SLOTS == 0
+	memset((char *)comp, 0, sizeof(*comp));
+#endif
+	comp->maxSlotIndex = MAX_SLOTS - 1;
+	comp->compressSlot = 0;		/* Disable slot ID compression by default. */
+	for (i = MAX_SLOTS - 1; i > 0; --i) {
+		tstate[i].cs_id = i;
+		tstate[i].cs_next = &tstate[i - 1];
+	}
+	tstate[0].cs_next = &tstate[MAX_SLOTS - 1];
+	tstate[0].cs_id = 0;
+	comp->last_cs = &tstate[0];
+	comp->last_recv = 255;
+	comp->last_xmit = 255;
+	comp->flags = VJF_TOSS;
+}
+
+
+/* ENCODE encodes a number that is known to be non-zero.  ENCODEZ
+ * checks for zero (since zero has to be encoded in the long, 3 byte
+ * form).
+ */
+#define ENCODE(n) { \
+	if ((u_short)(n) >= 256) { \
+		*cp++ = 0; \
+		cp[1] = (n); \
+		cp[0] = (n) >> 8; \
+		cp += 2; \
+	} else { \
+		*cp++ = (n); \
+	} \
+}
+#define ENCODEZ(n) { \
+	if ((u_short)(n) >= 256 || (u_short)(n) == 0) { \
+		*cp++ = 0; \
+		cp[1] = (n); \
+		cp[0] = (n) >> 8; \
+		cp += 2; \
+	} else { \
+		*cp++ = (n); \
+	} \
+}
+
+#define DECODEL(f) { \
+	if (*cp == 0) {\
+		u32_t tmp = ntohl(f) + ((cp[1] << 8) | cp[2]); \
+		(f) = htonl(tmp); \
+		cp += 3; \
+	} else { \
+		u32_t tmp = ntohl(f) + (u32_t)*cp++; \
+		(f) = htonl(tmp); \
+	} \
+}
+
+#define DECODES(f) { \
+	if (*cp == 0) {\
+		u_short tmp = ntohs(f) + (((u_short)cp[1] << 8) | cp[2]); \
+		(f) = htons(tmp); \
+		cp += 3; \
+	} else { \
+		u_short tmp = ntohs(f) + (u_short)*cp++; \
+		(f) = htons(tmp); \
+	} \
+}
+
+#define DECODEU(f) { \
+	if (*cp == 0) {\
+		(f) = htons(((u_short)cp[1] << 8) | cp[2]); \
+		cp += 3; \
+	} else { \
+		(f) = htons((u_short)*cp++); \
+	} \
+}
+
+/*
+ * vj_compress_tcp - Attempt to do Van Jacobsen header compression on a
+ * packet.  This assumes that nb and comp are not null and that the first
+ * buffer of the chain contains a valid IP header.
+ * Return the VJ type code indicating whether or not the packet was
+ * compressed.
+ */
+u_int vj_compress_tcp(
+	struct vjcompress *comp,
+	struct pbuf *pb
+)
+{
+	register struct ip *ip = (struct ip *)pb->payload;
+	register struct cstate *cs = comp->last_cs->cs_next;
+	register u_short hlen = getip_hl(*ip);
+	register struct tcphdr *oth;
+	register struct tcphdr *th;
+	register u_short deltaS, deltaA;
+	register u_long deltaL;
+	register u_int changes = 0;
+	u_char new_seq[16];
+	register u_char *cp = new_seq;
+
+	/*	
+	 * Check that the packet is IP proto TCP.
+	 */
+	if (ip->ip_p != IPPROTO_TCP)
+		return (TYPE_IP);
+		
+	/*
+	 * Bail if this is an IP fragment or if the TCP packet isn't
+	 * `compressible' (i.e., ACK isn't set or some other control bit is
+	 * set).  
+	 */
+	if ((ip->ip_off & htons(0x3fff)) || pb->tot_len < 40)
+		return (TYPE_IP);
+	th = (struct tcphdr *)&((long *)ip)[hlen];
+	if ((th->th_flags & (TCP_SYN|TCP_FIN|TCP_RST|TCP_ACK)) != TCP_ACK)
+		return (TYPE_IP);
+		
+	/*
+	 * Packet is compressible -- we're going to send either a
+	 * COMPRESSED_TCP or UNCOMPRESSED_TCP packet.  Either way we need
+	 * to locate (or create) the connection state.  Special case the
+	 * most recently used connection since it's most likely to be used
+	 * again & we don't have to do any reordering if it's used.
+	 */
+	INCR(vjs_packets);
+	if (ip->ip_src.s_addr != cs->cs_ip.ip_src.s_addr 
+			|| ip->ip_dst.s_addr != cs->cs_ip.ip_dst.s_addr 
+			|| *(long *)th != ((long *)&cs->cs_ip)[getip_hl(cs->cs_ip)]) {
+		/*
+		 * Wasn't the first -- search for it.
+		 *
+		 * States are kept in a circularly linked list with
+		 * last_cs pointing to the end of the list.  The
+		 * list is kept in lru order by moving a state to the
+		 * head of the list whenever it is referenced.  Since
+		 * the list is short and, empirically, the connection
+		 * we want is almost always near the front, we locate
+		 * states via linear search.  If we don't find a state
+		 * for the datagram, the oldest state is (re-)used.
+		 */
+		register struct cstate *lcs;
+		register struct cstate *lastcs = comp->last_cs;
+		
+		do {
+			lcs = cs; cs = cs->cs_next;
+			INCR(vjs_searches);
+			if (ip->ip_src.s_addr == cs->cs_ip.ip_src.s_addr
+					&& ip->ip_dst.s_addr == cs->cs_ip.ip_dst.s_addr
+					&& *(long *)th == ((long *)&cs->cs_ip)[getip_hl(cs->cs_ip)])
+				goto found;
+		} while (cs != lastcs);
+		
+		/*
+		 * Didn't find it -- re-use oldest cstate.  Send an
+		 * uncompressed packet that tells the other side what
+		 * connection number we're using for this conversation.
+		 * Note that since the state list is circular, the oldest
+		 * state points to the newest and we only need to set
+		 * last_cs to update the lru linkage.
+		 */
+		INCR(vjs_misses);
+		comp->last_cs = lcs;
+		hlen += getth_off(*th);
+		hlen <<= 2;
+		/* Check that the IP/TCP headers are contained in the first buffer. */
+		if (hlen > pb->len)
+			return (TYPE_IP);
+		goto uncompressed;
+		
+		found:
+		/*
+		 * Found it -- move to the front on the connection list.
+		 */
+		if (cs == lastcs)
+			comp->last_cs = lcs;
+		else {
+			lcs->cs_next = cs->cs_next;
+			cs->cs_next = lastcs->cs_next;
+			lastcs->cs_next = cs;
+		}
+	}
+	
+	oth = (struct tcphdr *)&((long *)&cs->cs_ip)[hlen];
+	deltaS = hlen;
+	hlen += getth_off(*th);
+	hlen <<= 2;
+	/* Check that the IP/TCP headers are contained in the first buffer. */
+	if (hlen > pb->len) {
+		PPPDEBUG((LOG_INFO, "vj_compress_tcp: header len %d spans buffers\n", 
+					hlen));
+		return (TYPE_IP);
+	}
+	
+	/*
+	 * Make sure that only what we expect to change changed. The first
+	 * line of the `if' checks the IP protocol version, header length &
+	 * type of service.  The 2nd line checks the "Don't fragment" bit.
+	 * The 3rd line checks the time-to-live and protocol (the protocol
+	 * check is unnecessary but costless).  The 4th line checks the TCP
+	 * header length.  The 5th line checks IP options, if any.  The 6th
+	 * line checks TCP options, if any.  If any of these things are
+	 * different between the previous & current datagram, we send the
+	 * current datagram `uncompressed'.
+	 */
+	if (((u_short *)ip)[0] != ((u_short *)&cs->cs_ip)[0] 
+			|| ((u_short *)ip)[3] != ((u_short *)&cs->cs_ip)[3] 
+			|| ((u_short *)ip)[4] != ((u_short *)&cs->cs_ip)[4] 
+			|| getth_off(*th) != getth_off(*oth) 
+			|| (deltaS > 5 && BCMP(ip + 1, &cs->cs_ip + 1, (deltaS - 5) << 2)) 
+			|| (getth_off(*th) > 5 && BCMP(th + 1, oth + 1, (getth_off(*th) - 5) << 2)))
+		goto uncompressed;
+	
+	/*
+	 * Figure out which of the changing fields changed.  The
+	 * receiver expects changes in the order: urgent, window,
+	 * ack, seq (the order minimizes the number of temporaries
+	 * needed in this section of code).
+	 */
+	if (th->th_flags & TCP_URG) {
+		deltaS = ntohs(th->th_urp);
+		ENCODEZ(deltaS);
+		changes |= NEW_U;
+	} else if (th->th_urp != oth->th_urp)
+		/* argh! URG not set but urp changed -- a sensible
+		 * implementation should never do this but RFC793
+		 * doesn't prohibit the change so we have to deal
+		 * with it. */
+		goto uncompressed;
+	
+	if ((deltaS = (u_short)(ntohs(th->th_win) - ntohs(oth->th_win))) != 0) {
+		ENCODE(deltaS);
+		changes |= NEW_W;
+	}
+	
+	if ((deltaL = ntohl(th->th_ack) - ntohl(oth->th_ack)) != 0) {
+		if (deltaL > 0xffff)
+			goto uncompressed;
+		deltaA = (u_short)deltaL;
+		ENCODE(deltaA);
+		changes |= NEW_A;
+	}
+	
+	if ((deltaL = ntohl(th->th_seq) - ntohl(oth->th_seq)) != 0) {
+		if (deltaL > 0xffff)
+			goto uncompressed;
+		deltaS = (u_short)deltaL;
+		ENCODE(deltaS);
+		changes |= NEW_S;
+	}
+	
+	switch(changes) {
+	
+	case 0:
+		/*
+		 * Nothing changed. If this packet contains data and the
+		 * last one didn't, this is probably a data packet following
+		 * an ack (normal on an interactive connection) and we send
+		 * it compressed.  Otherwise it's probably a retransmit,
+		 * retransmitted ack or window probe.  Send it uncompressed
+		 * in case the other side missed the compressed version.
+		 */
+		if (ip->ip_len != cs->cs_ip.ip_len &&
+			ntohs(cs->cs_ip.ip_len) == hlen)
+		break;
+	
+	/* (fall through) */
+	
+	case SPECIAL_I:
+	case SPECIAL_D:
+		/*
+		 * actual changes match one of our special case encodings --
+		 * send packet uncompressed.
+		 */
+		goto uncompressed;
+	
+	case NEW_S|NEW_A:
+		if (deltaS == deltaA && deltaS == ntohs(cs->cs_ip.ip_len) - hlen) {
+			/* special case for echoed terminal traffic */
+			changes = SPECIAL_I;
+			cp = new_seq;
+		}
+		break;
+	
+	case NEW_S:
+		if (deltaS == ntohs(cs->cs_ip.ip_len) - hlen) {
+			/* special case for data xfer */
+			changes = SPECIAL_D;
+			cp = new_seq;
+		}
+		break;
+	}
+	
+	deltaS = (u_short)(ntohs(ip->ip_id) - ntohs(cs->cs_ip.ip_id));
+	if (deltaS != 1) {
+		ENCODEZ(deltaS);
+		changes |= NEW_I;
+	}
+	if (th->th_flags & TCP_PSH)
+	changes |= TCP_PUSH_BIT;
+	/*
+	 * Grab the cksum before we overwrite it below.  Then update our
+	 * state with this packet's header.
+	 */
+	deltaA = ntohs(th->th_sum);
+	BCOPY(ip, &cs->cs_ip, hlen);
+	
+	/*
+	 * We want to use the original packet as our compressed packet.
+	 * (cp - new_seq) is the number of bytes we need for compressed
+	 * sequence numbers.  In addition we need one byte for the change
+	 * mask, one for the connection id and two for the tcp checksum.
+	 * So, (cp - new_seq) + 4 bytes of header are needed.  hlen is how
+	 * many bytes of the original packet to toss so subtract the two to
+	 * get the new packet size.
+	 */
+	deltaS = (u_short)(cp - new_seq);
+	if (!comp->compressSlot || comp->last_xmit != cs->cs_id) {
+		comp->last_xmit = cs->cs_id;
+		hlen -= deltaS + 4;
+		pbuf_header(pb, -hlen);
+		cp = (u_char *)pb->payload;
+		*cp++ = changes | NEW_C;
+		*cp++ = cs->cs_id;
+	} else {
+		hlen -= deltaS + 3;
+		pbuf_header(pb, -hlen);
+		cp = (u_char *)pb->payload;
+		*cp++ = changes;
+	}
+	*cp++ = deltaA >> 8;
+	*cp++ = deltaA;
+	BCOPY(new_seq, cp, deltaS);
+	INCR(vjs_compressed);
+	return (TYPE_COMPRESSED_TCP);
+
+	/*
+	 * Update connection state cs & send uncompressed packet (that is,
+	 * a regular ip/tcp packet but with the 'conversation id' we hope
+	 * to use on future compressed packets in the protocol field).
+	 */
+uncompressed:
+	BCOPY(ip, &cs->cs_ip, hlen);
+	ip->ip_p = cs->cs_id;
+	comp->last_xmit = cs->cs_id;
+	return (TYPE_UNCOMPRESSED_TCP);
+}
+
+/*
+ * Called when we may have missed a packet.
+ */
+void vj_uncompress_err(struct vjcompress *comp)
+{
+    comp->flags |= VJF_TOSS;
+	INCR(vjs_errorin);
+}
+
+/*
+ * "Uncompress" a packet of type TYPE_UNCOMPRESSED_TCP.
+ * Return 0 on success, -1 on failure.
+ */
+int vj_uncompress_uncomp(
+	struct pbuf *nb,
+	struct vjcompress *comp
+)
+{
+	register u_int hlen;
+	register struct cstate *cs;
+	register struct ip *ip;
+	
+	ip = (struct ip *)nb->payload;
+	hlen = getip_hl(*ip) << 2;
+	if (ip->ip_p >= MAX_SLOTS
+			|| hlen + sizeof(struct tcphdr) > nb->len
+			|| (hlen += getth_off(*((struct tcphdr *)&((char *)ip)[hlen])) << 2)
+			    > nb->len
+			|| hlen > MAX_HDR) {
+		PPPDEBUG((LOG_INFO, "vj_uncompress_uncomp: bad cid=%d, hlen=%d buflen=%d\n", 
+					ip->ip_p, hlen, nb->len));
+		comp->flags |= VJF_TOSS;
+		INCR(vjs_errorin);
+		return -1;
+	}
+	cs = &comp->rstate[comp->last_recv = ip->ip_p];
+	comp->flags &=~ VJF_TOSS;
+	ip->ip_p = IPPROTO_TCP;
+	BCOPY(ip, &cs->cs_ip, hlen);
+	cs->cs_hlen = hlen;
+	INCR(vjs_uncompressedin);
+	return 0;
+}
+
+/*
+ * Uncompress a packet of type TYPE_COMPRESSED_TCP.
+ * The packet is composed of a buffer chain and the first buffer
+ * must contain an accurate chain length.
+ * The first buffer must include the entire compressed TCP/IP header. 
+ * This procedure replaces the compressed header with the uncompressed
+ * header and returns the length of the VJ header.
+ */
+int vj_uncompress_tcp(
+	struct pbuf **nb,
+	struct vjcompress *comp
+)
+{
+	u_char *cp;
+	struct tcphdr *th;
+	struct cstate *cs;
+	u_short *bp;
+	struct pbuf *n0 = *nb;
+	u32_t tmp;
+	u_int vjlen, hlen, changes;
+	
+	INCR(vjs_compressedin);
+	cp = (u_char *)n0->payload;
+	changes = *cp++;
+	if (changes & NEW_C) {
+		/* 
+		 * Make sure the state index is in range, then grab the state.
+		 * If we have a good state index, clear the 'discard' flag. 
+		 */
+		if (*cp >= MAX_SLOTS) {
+			PPPDEBUG((LOG_INFO, "vj_uncompress_tcp: bad cid=%d\n", *cp));
+			goto bad;
+		}
+		
+		comp->flags &=~ VJF_TOSS;
+		comp->last_recv = *cp++;
+	} else {
+		/* 
+		 * this packet has an implicit state index.  If we've
+		 * had a line error since the last time we got an
+		 * explicit state index, we have to toss the packet. 
+		 */
+		if (comp->flags & VJF_TOSS) {
+			PPPDEBUG((LOG_INFO, "vj_uncompress_tcp: tossing\n"));
+			INCR(vjs_tossed);
+			return (-1);
+		}
+	}
+	cs = &comp->rstate[comp->last_recv];
+	hlen = getip_hl(cs->cs_ip) << 2;
+	th = (struct tcphdr *)&((u_char *)&cs->cs_ip)[hlen];
+	th->th_sum = htons((*cp << 8) | cp[1]);
+	cp += 2;
+	if (changes & TCP_PUSH_BIT)
+		th->th_flags |= TCP_PSH;
+	else
+		th->th_flags &=~ TCP_PSH;
+	
+	switch (changes & SPECIALS_MASK) {
+	case SPECIAL_I:
+		{
+			register u32_t i = ntohs(cs->cs_ip.ip_len) - cs->cs_hlen;
+			/* some compilers can't nest inline assembler.. */
+			tmp = ntohl(th->th_ack) + i;
+			th->th_ack = htonl(tmp);
+			tmp = ntohl(th->th_seq) + i;
+			th->th_seq = htonl(tmp);
+		}
+		break;
+	
+	case SPECIAL_D:
+		/* some compilers can't nest inline assembler.. */
+		tmp = ntohl(th->th_seq) + ntohs(cs->cs_ip.ip_len) - cs->cs_hlen;
+		th->th_seq = htonl(tmp);
+		break;
+	
+	default:
+		if (changes & NEW_U) {
+			th->th_flags |= TCP_URG;
+			DECODEU(th->th_urp);
+		} else
+			th->th_flags &=~ TCP_URG;
+		if (changes & NEW_W)
+			DECODES(th->th_win);
+		if (changes & NEW_A)
+			DECODEL(th->th_ack);
+		if (changes & NEW_S)
+			DECODEL(th->th_seq);
+		break;
+	}
+	if (changes & NEW_I) {
+		DECODES(cs->cs_ip.ip_id);
+	} else {
+		cs->cs_ip.ip_id = ntohs(cs->cs_ip.ip_id) + 1;
+		cs->cs_ip.ip_id = htons(cs->cs_ip.ip_id);
+	}
+	
+	/*
+	 * At this point, cp points to the first byte of data in the
+	 * packet.  Fill in the IP total length and update the IP
+	 * header checksum.
+	 */
+	vjlen = (u_short)(cp - (u_char*)n0->payload);
+	if (n0->len < vjlen) {
+		/* 
+		 * We must have dropped some characters (crc should detect
+		 * this but the old slip framing won't) 
+		 */
+		PPPDEBUG((LOG_INFO, "vj_uncompress_tcp: head buffer %d too short %d\n", 
+				  n0->len, vjlen));
+		goto bad;
+	}
+	
+#if BYTE_ORDER == LITTLE_ENDIAN
+	tmp = n0->tot_len - vjlen + cs->cs_hlen;
+	cs->cs_ip.ip_len = htons(tmp);
+#else
+	cs->cs_ip.ip_len = htons(n0->tot_len - vjlen + cs->cs_hlen);
+#endif
+	
+	/* recompute the ip header checksum */
+	bp = (u_short *) &cs->cs_ip;
+	cs->cs_ip.ip_sum = 0;
+	for (tmp = 0; hlen > 0; hlen -= 2)
+		tmp += *bp++;
+	tmp = (tmp & 0xffff) + (tmp >> 16);
+	tmp = (tmp & 0xffff) + (tmp >> 16);
+	cs->cs_ip.ip_sum = (u_short)(~tmp);
+	
+	/* Remove the compressed header and prepend the uncompressed header. */
+	pbuf_header(n0, -vjlen);
+
+	if(MEM_ALIGN(n0->payload) != n0->payload) {
+		struct pbuf *np, *q;
+		u8_t *bufptr;
+
+		np = pbuf_alloc(PBUF_RAW, n0->len + cs->cs_hlen, PBUF_POOL);
+		if(!np) {
+			PPPDEBUG((LOG_WARNING, "vj_uncompress_tcp: realign failed\n"));
+			*nb = NULL;
+			goto bad;
+		}
+
+		pbuf_header(np, -cs->cs_hlen);
+
+		bufptr = n0->payload;
+		for(q = np; q != NULL; q = q->next) {
+			memcpy(q->payload, bufptr, q->len);
+			bufptr += q->len;
+		}
+
+		if(n0->next) {
+			pbuf_chain(np, n0->next);
+			pbuf_dechain(n0);
+		}
+		pbuf_free(n0);
+		n0 = np;
+	}
+
+	if(pbuf_header(n0, cs->cs_hlen)) {
+		struct pbuf *np;
+
+		LWIP_ASSERT("vj_uncompress_tcp: cs->cs_hlen <= PBUF_POOL_BUFSIZE", cs->cs_hlen <= PBUF_POOL_BUFSIZE);
+		np = pbuf_alloc(PBUF_RAW, cs->cs_hlen, PBUF_POOL);
+		if(!np) {
+			PPPDEBUG((LOG_WARNING, "vj_uncompress_tcp: prepend failed\n"));
+			*nb = NULL;
+			goto bad;
+		}
+		pbuf_cat(np, n0);
+		n0 = np;
+	}
+	LWIP_ASSERT("n0->len >= cs->cs_hlen", n0->len >= cs->cs_hlen);
+	memcpy(n0->payload, &cs->cs_ip, cs->cs_hlen);
+
+	*nb = n0;
+
+	return vjlen;
+	
+bad:
+	comp->flags |= VJF_TOSS;
+	INCR(vjs_errorin);
+	return (-1);
+}
+
+#endif
+
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/vj.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/vj.h
new file mode 100644
index 000000000..9da271481
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/vj.h
@@ -0,0 +1,155 @@
+/*
+ * Definitions for tcp compression routines.
+ *
+ * $Id: vj.h,v 1.4 2004/02/07 00:30:03 likewise Exp $
+ *
+ * Copyright (c) 1989 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the University of California, Berkeley.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *	Van Jacobson (van@helios.ee.lbl.gov), Dec 31, 1989:
+ *	- Initial distribution.
+ */
+
+#ifndef VJ_H
+#define VJ_H
+
+#include "vjbsdhdr.h"
+
+#define MAX_SLOTS	16			/* must be > 2 and < 256 */
+#define MAX_HDR		128
+
+/*
+ * Compressed packet format:
+ *
+ * The first octet contains the packet type (top 3 bits), TCP
+ * 'push' bit, and flags that indicate which of the 4 TCP sequence
+ * numbers have changed (bottom 5 bits).  The next octet is a
+ * conversation number that associates a saved IP/TCP header with
+ * the compressed packet.  The next two octets are the TCP checksum
+ * from the original datagram.  The next 0 to 15 octets are
+ * sequence number changes, one change per bit set in the header
+ * (there may be no changes and there are two special cases where
+ * the receiver implicitly knows what changed -- see below).
+ * 
+ * There are 5 numbers which can change (they are always inserted
+ * in the following order): TCP urgent pointer, window,
+ * acknowlegement, sequence number and IP ID.  (The urgent pointer
+ * is different from the others in that its value is sent, not the
+ * change in value.)  Since typical use of SLIP links is biased
+ * toward small packets (see comments on MTU/MSS below), changes
+ * use a variable length coding with one octet for numbers in the
+ * range 1 - 255 and 3 octets (0, MSB, LSB) for numbers in the
+ * range 256 - 65535 or 0.  (If the change in sequence number or
+ * ack is more than 65535, an uncompressed packet is sent.)
+ */
+
+/*
+ * Packet types (must not conflict with IP protocol version)
+ *
+ * The top nibble of the first octet is the packet type.  There are
+ * three possible types: IP (not proto TCP or tcp with one of the
+ * control flags set); uncompressed TCP (a normal IP/TCP packet but
+ * with the 8-bit protocol field replaced by an 8-bit connection id --
+ * this type of packet syncs the sender & receiver); and compressed
+ * TCP (described above).
+ *
+ * LSB of 4-bit field is TCP "PUSH" bit (a worthless anachronism) and
+ * is logically part of the 4-bit "changes" field that follows.  Top
+ * three bits are actual packet type.  For backward compatibility
+ * and in the interest of conserving bits, numbers are chosen so the
+ * IP protocol version number (4) which normally appears in this nibble
+ * means "IP packet".
+ */
+
+/* packet types */
+#define TYPE_IP 0x40
+#define TYPE_UNCOMPRESSED_TCP 0x70
+#define TYPE_COMPRESSED_TCP 0x80
+#define TYPE_ERROR 0x00
+
+/* Bits in first octet of compressed packet */
+#define NEW_C	0x40	/* flag bits for what changed in a packet */
+#define NEW_I	0x20
+#define NEW_S	0x08
+#define NEW_A	0x04
+#define NEW_W	0x02
+#define NEW_U	0x01
+
+/* reserved, special-case values of above */
+#define SPECIAL_I (NEW_S|NEW_W|NEW_U)		/* echoed interactive traffic */
+#define SPECIAL_D (NEW_S|NEW_A|NEW_W|NEW_U)	/* unidirectional data */
+#define SPECIALS_MASK (NEW_S|NEW_A|NEW_W|NEW_U)
+
+#define TCP_PUSH_BIT 0x10
+
+
+/*
+ * "state" data for each active tcp conversation on the wire.  This is
+ * basically a copy of the entire IP/TCP header from the last packet
+ * we saw from the conversation together with a small identifier
+ * the transmit & receive ends of the line use to locate saved header.
+ */
+struct cstate {
+    struct cstate *cs_next;	/* next most recently used state (xmit only) */
+    u_short cs_hlen;		/* size of hdr (receive only) */
+    u_char cs_id;			/* connection # associated with this state */
+    u_char cs_filler;
+    union {
+		char csu_hdr[MAX_HDR];
+		struct ip csu_ip;	/* ip/tcp hdr from most recent packet */
+    } vjcs_u;
+};
+#define cs_ip vjcs_u.csu_ip
+#define cs_hdr vjcs_u.csu_hdr
+
+
+struct vjstat {
+    unsigned long vjs_packets;			/* outbound packets */
+    unsigned long vjs_compressed;		/* outbound compressed packets */
+    unsigned long vjs_searches;			/* searches for connection state */
+    unsigned long vjs_misses;			/* times couldn't find conn. state */
+    unsigned long vjs_uncompressedin;	/* inbound uncompressed packets */
+    unsigned long vjs_compressedin;		/* inbound compressed packets */
+    unsigned long vjs_errorin;			/* inbound unknown type packets */
+    unsigned long vjs_tossed;			/* inbound packets tossed because of error */
+};
+
+/*
+ * all the state data for one serial line (we need one of these per line).
+ */
+struct vjcompress {
+    struct cstate *last_cs;	/* most recently used tstate */
+    u_char last_recv;		/* last rcvd conn. id */
+    u_char last_xmit;		/* last sent conn. id */
+    u_short flags;
+    u_char maxSlotIndex;
+    u_char compressSlot;	/* Flag indicating OK to compress slot ID. */
+#if LINK_STATS
+    struct vjstat stats;
+#endif
+    struct cstate tstate[MAX_SLOTS];	/* xmit connection states */
+    struct cstate rstate[MAX_SLOTS];	/* receive connection states */
+};
+
+/* flag values */
+#define VJF_TOSS 1U		/* tossing rcvd frames because of input err */
+
+extern void  vj_compress_init (struct vjcompress *comp);
+extern u_int vj_compress_tcp (struct vjcompress *comp, struct pbuf *pb);
+extern void  vj_uncompress_err (struct vjcompress *comp);
+extern int vj_uncompress_uncomp(struct pbuf *nb, struct vjcompress *comp);
+extern int vj_uncompress_tcp(struct pbuf **nb, struct vjcompress *comp);
+
+#endif /* VJ_H */
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/vjbsdhdr.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/vjbsdhdr.h
new file mode 100644
index 000000000..a7d180c16
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/vjbsdhdr.h
@@ -0,0 +1,76 @@
+#ifndef VJBSDHDR_H
+#define VJBSDHDR_H
+
+#include "lwip/tcp.h"
+
+
+/*
+ * Structure of an internet header, naked of options.
+ *
+ * We declare ip_len and ip_off to be short, rather than u_short
+ * pragmatically since otherwise unsigned comparisons can result
+ * against negative integers quite easily, and fail in subtle ways.
+ */
+PACK_STRUCT_BEGIN
+struct ip
+{
+#if defined(NO_CHAR_BITFIELDS)
+	u_char ip_hl_v;	/* bug in GCC for mips means the bitfield stuff will sometimes break - so we use a char for both and get round it with macro's instead... */
+#else
+#if BYTE_ORDER == LITTLE_ENDIAN
+	unsigned ip_hl:4,				/* header length */
+		ip_v:4;						/* version */
+#elif BYTE_ORDER == BIG_ENDIAN 
+	unsigned ip_v:4,					/* version */
+		ip_hl:4;					/* header length */
+#else
+	COMPLAIN - NO BYTE ORDER SELECTED!
+#endif
+#endif
+	u_char	ip_tos;					/* type of service */
+	u_short	ip_len;					/* total length */
+	u_short	ip_id;					/* identification */
+	u_short	ip_off;					/* fragment offset field */
+#define	IP_DF 0x4000				/* dont fragment flag */
+#define	IP_MF 0x2000				/* more fragments flag */
+#define	IP_OFFMASK 0x1fff			/* mask for fragmenting bits */
+	u_char	ip_ttl;					/* time to live */
+	u_char	ip_p;					/* protocol */
+	u_short	ip_sum;					/* checksum */
+	struct	in_addr ip_src,ip_dst;	/* source and dest address */
+};
+PACK_STRUCT_END
+
+typedef u32_t tcp_seq;
+
+/*
+ * TCP header.
+ * Per RFC 793, September, 1981.
+ */
+PACK_STRUCT_BEGIN
+struct tcphdr  
+{
+	u_short	th_sport;		/* source port */
+	u_short	th_dport;		/* destination port */
+	tcp_seq	th_seq;			/* sequence number */
+	tcp_seq	th_ack;			/* acknowledgement number */
+#if defined(NO_CHAR_BITFIELDS)
+	u_char th_x2_off;
+#else
+#if BYTE_ORDER == LITTLE_ENDIAN
+	unsigned	th_x2:4,		/* (unused) */
+			th_off:4;		/* data offset */
+#endif
+#if BYTE_ORDER == BIG_ENDIAN 
+	unsigned	th_off:4,		/* data offset */
+			th_x2:4;		/* (unused) */
+#endif
+#endif
+	u_char	th_flags;
+	u_short	th_win;			/* window */
+	u_short	th_sum;			/* checksum */
+	u_short	th_urp;			/* urgent pointer */
+};
+PACK_STRUCT_END
+
+#endif /* VJBSDHDR_H */
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/slipif.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/slipif.c
new file mode 100644
index 000000000..1dca4cadd
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/slipif.c
@@ -0,0 +1,210 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. Neither the name of the Institute nor the names of its contributors 
+ *    may be used to endorse or promote products derived from this software 
+ *    without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
+ * SUCH DAMAGE. 
+ *
+ * This file is built upon the file: src/arch/rtxc/netif/sioslip.c
+ *
+ * Author: Magnus Ivarsson  
+ */
+
+/* 
+ * This is an arch independent SLIP netif. The specific serial hooks must be provided 
+ * by another file.They are sio_open, sio_recv and sio_send
+ */ 
+
+#include "netif/slipif.h"
+#include "lwip/opt.h"
+#include "lwip/def.h"
+#include "lwip/pbuf.h"
+#include "lwip/sys.h"
+#include "lwip/stats.h"
+#include "lwip/sio.h"
+
+#define SLIP_END     0300
+#define SLIP_ESC     0333
+#define SLIP_ESC_END 0334
+#define SLIP_ESC_ESC 0335
+
+#define MAX_SIZE     1500
+
+/**
+ * Send a pbuf doing the necessary SLIP encapsulation
+ *
+ * Uses the serial layer's sio_send() 
+ */ 
+err_t
+slipif_output(struct netif *netif, struct pbuf *p, struct ip_addr *ipaddr)
+{
+  struct pbuf *q;
+  int i;
+  u8_t c;
+
+  /* Send pbuf out on the serial I/O device. */
+  sio_send(SLIP_END, netif->state);
+
+  for(q = p; q != NULL; q = q->next) {
+    for(i = 0; i < q->len; i++) {
+      c = ((u8_t *)q->payload)[i];
+      switch (c) {
+      case SLIP_END:
+  sio_send(SLIP_ESC, netif->state);
+  sio_send(SLIP_ESC_END, netif->state);
+  break;
+      case SLIP_ESC:
+  sio_send(SLIP_ESC, netif->state);
+  sio_send(SLIP_ESC_ESC, netif->state);
+  break;
+      default:
+  sio_send(c, netif->state);
+  break;
+      }
+    }
+  }
+  sio_send(SLIP_END, netif->state);
+  return 0;
+}
+
+/**
+ * Handle the incoming SLIP stream character by character
+ *
+ * Poll the serial layer by calling sio_recv()
+ * 
+ * @return The IP packet when SLIP_END is received 
+ */ 
+static struct pbuf *
+slipif_input( struct netif * netif )
+{
+  u8_t c;
+  struct pbuf *p, *q;
+  int recved;
+  int i;
+
+  q = p = NULL;
+  recved = i = 0;
+  c = 0;
+
+  while (1) {
+    c = sio_recv(netif->state);
+    switch (c) {
+    case SLIP_END:
+      if (recved > 0) {
+  /* Received whole packet. */
+  pbuf_realloc(q, recved);
+  
+  LINK_STATS_INC(link.recv);
+  
+  LWIP_DEBUGF(SLIP_DEBUG, ("slipif: Got packet\n"));
+  return q;
+      }
+      break;
+
+    case SLIP_ESC:
+      c = sio_recv(netif->state);
+      switch (c) {
+      case SLIP_ESC_END:
+  c = SLIP_END;
+  break;
+      case SLIP_ESC_ESC:
+  c = SLIP_ESC;
+  break;
+      }
+      /* FALLTHROUGH */
+      
+    default:
+      if (p == NULL) {
+  LWIP_DEBUGF(SLIP_DEBUG, ("slipif_input: alloc\n"));
+  p = pbuf_alloc(PBUF_LINK, PBUF_POOL_BUFSIZE, PBUF_POOL);
+
+  if (p == NULL) {
+    LINK_STATS_INC(link.drop);
+    LWIP_DEBUGF(SLIP_DEBUG, ("slipif_input: no new pbuf! (DROP)\n"));
+  }
+  
+  if (q != NULL) {
+    pbuf_cat(q, p);
+  } else {
+    q = p;
+  }
+      }
+      if (p != NULL && recved < MAX_SIZE) {
+  ((u8_t *)p->payload)[i] = c;
+  recved++;
+  i++;
+  if (i >= p->len) {
+    i = 0;
+    p = NULL;
+  }
+      }
+      break;
+    }
+    
+  }
+  return NULL;
+}
+
+/**
+ * The SLIP input thread 
+ *
+ * Feed the IP layer with incoming packets
+ */ 
+static void
+slipif_loop(void *nf)
+{
+  struct pbuf *p;
+  struct netif *netif = (struct netif *)nf;
+
+  while (1) {
+    p = slipif_input(netif);
+    netif->input(p, netif);
+  }
+}
+
+/**
+ * SLIP netif initialization
+ *
+ * Call the arch specific sio_open and remember
+ * the opened device in the state field of the netif.
+ */ 
+err_t
+slipif_init(struct netif *netif)
+{
+  
+  LWIP_DEBUGF(SLIP_DEBUG, ("slipif_init: netif->num=%x\n", (int)netif->num));
+
+  netif->name[0] = 's';
+  netif->name[1] = 'l';
+  netif->output = slipif_output;
+  netif->mtu = 1500;  
+  netif->flags = NETIF_FLAG_POINTTOPOINT;
+
+  netif->state = sio_open(netif->num);
+  if (!netif->state)
+      return ERR_IF;
+
+  sys_thread_new(slipif_loop, netif, SLIPIF_THREAD_PRIO);
+  return ERR_OK;
+}
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwipopts.h b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwipopts.h
new file mode 100644
index 000000000..f58fe2e1a
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/lwipopts.h
@@ -0,0 +1,179 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIPOPTS_H__
+#define __LWIPOPTS_H__
+
+#define LWIP_NOASSERT 1 // To suppress some errors for now (no debug output)
+#define SYS_LIGHTWEIGHT_PROT            1
+
+#define TCPIP_THREAD_PRIO	3
+
+/* ---------- Memory options ---------- */
+/* MEM_ALIGNMENT: should be set to the alignment of the CPU for which
+   lwIP is compiled. 4 byte alignment -> define MEM_ALIGNMENT to 4, 2
+   byte alignment -> define MEM_ALIGNMENT to 2. */
+#define MEM_ALIGNMENT           4
+
+/* MEM_SIZE: the size of the heap memory. If the application will send
+a lot of data that needs to be copied, this should be set high. */
+#define MEM_SIZE                2000
+
+/* MEMP_NUM_PBUF: the number of memp struct pbufs. If the application
+   sends a lot of data out of ROM (or other static memory), this
+   should be set high. */
+#define MEMP_NUM_PBUF           20
+/* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One
+   per active UDP "connection". */
+#define MEMP_NUM_UDP_PCB        4
+/* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP
+   connections. */
+#define MEMP_NUM_TCP_PCB        10
+/* MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP
+   connections. */
+#define MEMP_NUM_TCP_PCB_LISTEN 8
+/* MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP
+   segments. */
+#define MEMP_NUM_TCP_SEG        8
+/* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active
+   timeouts. */
+#define MEMP_NUM_SYS_TIMEOUT    3
+
+
+/* The following four are used only with the sequential API and can be
+   set to 0 if the application only will use the raw API. */
+/* MEMP_NUM_NETBUF: the number of struct netbufs. */
+#define MEMP_NUM_NETBUF         4
+/* MEMP_NUM_NETCONN: the number of struct netconns. */
+#define MEMP_NUM_NETCONN        4
+/* MEMP_NUM_APIMSG: the number of struct api_msg, used for
+   communication between the TCP/IP stack and the sequential
+   programs. */
+#define MEMP_NUM_API_MSG        8
+/* MEMP_NUM_TCPIPMSG: the number of struct tcpip_msg, which is used
+   for sequential API communication and incoming packets. Used in
+   src/api/tcpip.c. */
+#define MEMP_NUM_TCPIP_MSG      8
+
+/* These two control is reclaimer functions should be compiled
+   in. Should always be turned on (1). */
+#define MEM_RECLAIM             1
+#define MEMP_RECLAIM            1
+
+/* ---------- Pbuf options ---------- */
+/* PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */
+#define PBUF_POOL_SIZE          4
+
+/* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */
+#define PBUF_POOL_BUFSIZE       1500
+
+/* PBUF_LINK_HLEN: the number of bytes that should be allocated for a
+   link level header. */
+#define PBUF_LINK_HLEN          16
+
+/* ---------- TCP options ---------- */
+#define LWIP_TCP                1
+#define TCP_TTL                 255
+
+/* Controls if TCP should queue segments that arrive out of
+   order. Define to 0 if your device is low on memory. */
+#define TCP_QUEUE_OOSEQ         1
+
+/* TCP Maximum segment size. */
+#define TCP_MSS                 1500
+
+/* TCP sender buffer space (bytes). */
+#define TCP_SND_BUF             1500
+
+/* TCP sender buffer space (pbufs). This must be at least = 2 *
+   TCP_SND_BUF/TCP_MSS for things to work. */
+#define TCP_SND_QUEUELEN        6 * TCP_SND_BUF/TCP_MSS
+
+/* TCP receive window. */
+#define TCP_WND                 1500
+
+/* Maximum number of retransmissions of data segments. */
+#define TCP_MAXRTX              12
+
+/* Maximum number of retransmissions of SYN segments. */
+#define TCP_SYNMAXRTX           4
+
+/* ---------- ARP options ---------- */
+#define ARP_TABLE_SIZE 10
+#define ARP_QUEUEING 1
+
+/* ---------- IP options ---------- */
+/* Define IP_FORWARD to 1 if you wish to have the ability to forward
+   IP packets across network interfaces. If you are going to run lwIP
+   on a device with only one network interface, define this to 0. */
+#define IP_FORWARD              1
+
+/* If defined to 1, IP options are allowed (but not parsed). If
+   defined to 0, all packets with IP options are dropped. */
+#define IP_OPTIONS              1
+
+/* ---------- ICMP options ---------- */
+#define ICMP_TTL                255
+
+
+/* ---------- DHCP options ---------- */
+/* Define LWIP_DHCP to 1 if you want DHCP configuration of
+   interfaces. DHCP is not implemented in lwIP 0.5.1, however, so
+   turning this on does currently not work. */
+#define LWIP_DHCP               0
+
+/* 1 if you want to do an ARP check on the offered address
+   (recommended). */
+#define DHCP_DOES_ARP_CHECK     1
+
+/* ---------- UDP options ---------- */
+#define LWIP_UDP                1
+#define UDP_TTL                 255
+
+
+/* ---------- Statistics options ---------- */
+#define STATS
+
+#ifdef STATS
+#define LINK_STATS 1
+#define IP_STATS   1
+#define ICMP_STATS 1
+#define UDP_STATS  1
+#define TCP_STATS  1
+#define MEM_STATS  1
+#define MEMP_STATS 1
+#define PBUF_STATS 1
+#define SYS_STATS  1
+#endif /* STATS */
+
+#define LWIP_PROVIDE_ERRNO 1
+
+#endif /* __LWIPOPTS_H__ */
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/main.c b/20080212/Demo/lwIP_Demo_Rowley_ARM7/main.c
new file mode 100644
index 000000000..eb09f4ddd
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/main.c
@@ -0,0 +1,308 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+/* 
+	NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.
+	The processor MUST be in supervisor mode when vTaskStartScheduler is 
+	called.  The demo applications included in the FreeRTOS.org download switch
+	to supervisor mode prior to main being called.  If you are not using one of
+	these demo application projects then ensure Supervisor mode is used.
+*/
+
+
+/*
+ * Creates all the application tasks, then starts the scheduler.
+ *
+ * A task defined by the function vBasicWEBServer is created.  This executes 
+ * the lwIP stack and basic WEB server sample.  A task defined by the function
+ * vUSBCDCTask.  This executes the USB to serial CDC example.  All the other 
+ * tasks are from the set of standard demo tasks.  The WEB documentation 
+ * provides more details of the standard demo application tasks.
+ *
+ * Main.c also creates a task called "Check".  This only executes every three
+ * seconds but has the highest priority so is guaranteed to get processor time.
+ * Its main function is to check the status of all the other demo application
+ * tasks.  LED mainCHECK_LED is toggled every three seconds by the check task
+ * should no error conditions be detected in any of the standard demo tasks.
+ * The toggle rate increasing to 500ms indicates that at least one error has
+ * been detected.
+ *
+ * Main.c includes an idle hook function that simply periodically sends data
+ * to the USB task for transmission.
+ */
+
+/*
+	Changes from V3.2.2
+
+	+ Modified the stack sizes used by some tasks to permit use of the 
+	  command line GCC tools.
+*/
+
+/* Library includes. */
+#include 
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Demo application includes. */
+#include "partest.h"
+#include "PollQ.h"
+#include "semtest.h"
+#include "flash.h"
+#include "integer.h"
+#include "BlockQ.h"
+#include "BasicWEB.h"
+#include "USB-CDC.h"
+
+/* lwIP includes. */
+#include "lwip/api.h" 
+
+/* Hardware specific headers. */
+#include "Board.h"
+#include "AT91SAM7X256.h"
+
+/* Priorities/stacks for the various tasks within the demo application. */
+#define mainQUEUE_POLL_PRIORITY		( tskIDLE_PRIORITY + 1 )
+#define mainCHECK_TASK_PRIORITY		( tskIDLE_PRIORITY + 3 )
+#define mainSEM_TEST_PRIORITY		( tskIDLE_PRIORITY + 1 )
+#define mainFLASH_PRIORITY			( tskIDLE_PRIORITY + 2 )
+#define mainBLOCK_Q_PRIORITY		( tskIDLE_PRIORITY + 1 )
+#define mainWEBSERVER_PRIORITY      ( tskIDLE_PRIORITY + 2 )
+#define mainUSB_PRIORITY			( tskIDLE_PRIORITY + 1 )
+#define mainUSB_TASK_STACK			( 200 )
+
+/* The rate at which the on board LED will toggle when there is/is not an
+error. */
+#define mainNO_ERROR_FLASH_PERIOD	( ( portTickType ) 3000 / portTICK_RATE_MS  )
+#define mainERROR_FLASH_PERIOD		( ( portTickType ) 500 / portTICK_RATE_MS  )
+
+/* The rate at which the idle hook sends data to the USB port. */
+#define mainUSB_TX_FREQUENCY		( 100 / portTICK_RATE_MS )
+
+/* The string that is transmitted down the USB port. */
+#define mainFIRST_TX_CHAR			'a'
+#define mainLAST_TX_CHAR			'z'
+
+/* The LED used by the check task to indicate the system status. */
+#define mainCHECK_LED 				( 3 )
+/*-----------------------------------------------------------*/
+
+/*
+ * Checks that all the demo application tasks are still executing without error
+ * - as described at the top of the file.
+ */
+static portLONG prvCheckOtherTasksAreStillRunning( void );
+
+/*
+ * The task that executes at the highest priority and calls
+ * prvCheckOtherTasksAreStillRunning().  See the description at the top
+ * of the file.
+ */
+static void vErrorChecks( void *pvParameters );
+
+/*
+ * Configure the processor for use with the Atmel demo board.  This is very
+ * minimal as most of the setup is performed in the startup code.
+ */
+static void prvSetupHardware( void );
+
+/*
+ * The idle hook is just used to stream data to the USB port.
+ */
+void vApplicationIdleHook( void );
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup hardware then start all the demo application tasks.
+ */
+int main( void )
+{
+	/* Setup the ports. */
+	prvSetupHardware();
+
+	/* Setup the IO required for the LED's. */
+	vParTestInitialise();
+
+	/* Setup lwIP. */
+    vlwIPInit();
+
+	/* Create the lwIP task.  This uses the lwIP RTOS abstraction layer.*/
+    sys_thread_new( vBasicWEBServer, ( void * ) NULL, mainWEBSERVER_PRIORITY );
+
+	/* Create the demo USB CDC task. */
+	xTaskCreate( vUSBCDCTask, ( signed portCHAR * ) "USB", mainUSB_TASK_STACK, NULL, mainUSB_PRIORITY, NULL );
+
+	/* Create the standard demo application tasks. */
+	vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
+	vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
+	vStartLEDFlashTasks( mainFLASH_PRIORITY );
+	vStartIntegerMathTasks( tskIDLE_PRIORITY );
+	vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
+
+	/* Start the check task - which is defined in this file. */	
+    xTaskCreate( vErrorChecks, ( signed portCHAR * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
+
+	/* Finally, start the scheduler. 
+
+	NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.
+	The processor MUST be in supervisor mode when vTaskStartScheduler is 
+	called.  The demo applications included in the FreeRTOS.org download switch
+	to supervisor mode prior to main being called.  If you are not using one of
+	these demo application projects then ensure Supervisor mode is used here. */
+	vTaskStartScheduler();
+
+	/* Should never get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+
+static void prvSetupHardware( void )
+{
+	/* When using the JTAG debugger the hardware is not always initialised to
+	the correct default state.  This line just ensures that this does not
+	cause all interrupts to be masked at the start. */
+	AT91C_BASE_AIC->AIC_EOICR = 0;
+	
+	/* Most setup is performed by the low level init function called from the
+	startup asm file.
+
+	Configure the PIO Lines corresponding to LED1 to LED4 to be outputs as
+	well as the UART Tx line. */
+	AT91C_BASE_PIOB->PIO_PER = LED_MASK; // Set in PIO mode
+	AT91C_BASE_PIOB->PIO_OER = LED_MASK; // Configure in Output
+
+
+	/* Enable the peripheral clock. */
+    AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOA;
+    AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOB;
+	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_EMAC;
+}
+/*-----------------------------------------------------------*/
+
+static void vErrorChecks( void *pvParameters )
+{
+portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD;
+portTickType xLastWakeTime;
+
+	/* The parameters are not used. */
+	( void ) pvParameters;
+
+	/* Initialise xLastWakeTime to ensure the first call to vTaskDelayUntil()
+	functions correctly. */
+	xLastWakeTime = xTaskGetTickCount();
+
+	/* Cycle for ever, delaying then checking all the other tasks are still
+	operating without error.  If an error is detected then the delay period
+	is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so
+	the Check LED flash rate will increase. */
+	for( ;; )
+	{
+		/* Delay until it is time to execute again.  The delay period is
+		shorter following an error. */
+		vTaskDelayUntil( &xLastWakeTime, xDelayPeriod );
+	
+		/* Check all the standard demo application tasks are executing without
+		error.  */
+		if( prvCheckOtherTasksAreStillRunning() != pdPASS )
+		{
+			/* An error has been detected in one of the tasks - flash faster. */
+			xDelayPeriod = mainERROR_FLASH_PERIOD;
+		}
+
+		vParTestToggleLED( mainCHECK_LED );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static portLONG prvCheckOtherTasksAreStillRunning( void )
+{
+portLONG lReturn = ( portLONG ) pdPASS;
+
+	/* Check all the demo tasks (other than the flash tasks) to ensure
+	that they are all still running, and that none of them have detected
+	an error. */
+
+	if( xArePollingQueuesStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	if( xAreSemaphoreTasksStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	if( xAreBlockingQueuesStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	return lReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationIdleHook( void )
+{
+static portTickType xLastTx = 0;
+portCHAR cTxByte;
+
+	/* The idle hook simply sends a string of characters to the USB port.
+	The characters will be buffered and sent once the port is connected. */
+	if( ( xTaskGetTickCount() - xLastTx ) > mainUSB_TX_FREQUENCY )
+	{
+		xLastTx = xTaskGetTickCount();
+		for( cTxByte = mainFIRST_TX_CHAR; cTxByte <= mainLAST_TX_CHAR; cTxByte++ )
+		{
+			vUSBSendByte( cTxByte );
+		}		
+	}
+}
+
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/makefile b/20080212/Demo/lwIP_Demo_Rowley_ARM7/makefile
new file mode 100644
index 000000000..f7c167fac
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/makefile
@@ -0,0 +1,159 @@
+#	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+#
+#	This file is part of the FreeRTOS.org distribution.
+#
+#	FreeRTOS.org is free software; you can redistribute it and/or modify
+#	it under the terms of the GNU General Public License as published by
+#	the Free Software Foundation; either version 2 of the License, or
+#	(at your option) any later version.
+#
+#	FreeRTOS.org is distributed in the hope that it will be useful,
+#	but WITHOUT ANY WARRANTY; without even the implied warranty of
+#	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#	GNU General Public License for more details.
+#
+#	You should have received a copy of the GNU General Public License
+#	along with FreeRTOS.org; if not, write to the Free Software
+#	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+#	A special exception to the GPL can be applied should you wish to distribute
+#	a combined work that includes FreeRTOS.org, without being obliged to provide
+#	the source code for any proprietary components.  See the licensing section 
+#	of http://www.FreeRTOS.org for full details of how and when the exception
+#	can be applied.
+#
+#	***************************************************************************
+#	See http://www.FreeRTOS.org for documentation, latest information, license 
+#	and contact details.  Please ensure to read the configuration and relevant 
+#	port sections of the online documentation.
+#	***************************************************************************
+
+CC=arm-elf-gcc
+OBJCOPY=arm-elf-objcopy
+ARCH=arm-elf-ar
+CRT0=boot.s
+DEBUG=-g
+OPTIM=-O0
+LDSCRIPT=atmel-rom.ld
+
+#
+# CFLAGS common to both the THUMB and ARM mode builds
+#
+
+CFLAGS= \
+-I.  \
+-I./EMAC  \
+-I../Common/include  \
+-I./USB  \
+-I./lwip-1.1.0/src/include  \
+-I./lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X  \
+-I../../Source/include  \
+-I../../Source/portable/GCC/ARM7_AT91SAM7S  \
+-I./lwip-1.1.0/src/include/ipv4 \
+-Wall  \
+-Wextra  \
+-Wstrict-prototypes  \
+-Wmissing-prototypes  \
+-Wmissing-declarations  \
+-Wno-strict-aliasing  \
+-D SAM7_GCC  \
+-D THUMB_INTERWORK \
+-mthumb-interwork \
+-mcpu=arm7tdmi  \
+-T$(LDSCRIPT) \
+$(DEBUG)  \
+$(OPTIM) \
+-fomit-frame-pointer
+
+THUMB_FLAGS=-mthumb
+LINKER_FLAGS=-Xlinker -ortosdemo.elf -Xlinker -M -Xlinker -Map=rtosdemo.map
+
+#
+# Source files that can be built to THUMB mode.
+#
+FREERTOS_THUMB_SRC= \
+  ../../Source/tasks.c \
+  ../../Source/queue.c \
+  ../../Source/list.c \
+  ../../Source/portable/GCC/ARM7_AT91SAM7S/port.c
+
+DEMO_APP_THMUB_SRC= \
+  ../../Source/portable/MemMang/heap_2.c \
+  ParTest/ParTest.c \
+  main.c \
+  ../Common/Minimal/flash.c \
+  ../Common/Minimal/BlockQ.c \
+  ../Common/Minimal/integer.c \
+  ../Common/Minimal/PollQ.c \
+  ../Common/Minimal/semtest.c \
+  BasicWEB.c \
+  USB/USB-CDC.c 
+
+LWIP_THUMB_SRC= \
+  lwip-1.1.0/src/core/tcp_out.c \
+  lwip-1.1.0/src/core/inet.c \
+  lwip-1.1.0/src/core/mem.c \
+  lwip-1.1.0/src/core/memp.c \
+  lwip-1.1.0/src/core/netif.c \
+  lwip-1.1.0/src/core/pbuf.c \
+  lwip-1.1.0/src/core/raw.c \
+  lwip-1.1.0/src/core/stats.c \
+  lwip-1.1.0/src/core/sys.c \
+  lwip-1.1.0/src/core/tcp.c \
+  lwip-1.1.0/src/core/tcp_in.c \
+  lwip-1.1.0/src/core/ipv4/ip.c \
+  lwip-1.1.0/src/core/ipv4/ip_addr.c \
+  lwip-1.1.0/src/core/ipv4/icmp.c \
+  lwip-1.1.0/src/api/tcpip.c \
+  lwip-1.1.0/src/api/api_msg.c \
+  lwip-1.1.0/src/api/err.c \
+  lwip-1.1.0/src/api/api_lib.c \
+  lwip-1.1.0/src/netif/etharp.c \
+  lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/sys_arch.c \
+  lwip-1.1.0/src/netif/ethernetif.c \
+  EMAC/SAM7_EMAC.c \
+  lwip-1.1.0/src/core/udp.c \
+  lwip-1.1.0/src/core/ipv4/ip_frag.c
+
+#
+# Source files that must be built to ARM mode.
+#
+ARM_SRC= \
+  ../../Source/portable/GCC/ARM7_AT91SAM7S/portISR.c \
+  EMAC/SAM7_EMAC_ISR.c \
+  USB/USBIsr.c \
+  Cstartup_SAM7.c  
+
+
+#
+# Define all object files.
+#
+ARM_OBJ = $(ARM_SRC:.c=.o)
+FREERTOS_THUMB_OBJ = $(FREERTOS_THUMB_SRC:.c=.o)
+DEMO_APP_THMUB_OBJ = $(DEMO_APP_THMUB_SRC:.c=.o)
+LWIP_THUMB_OBJ = $(LWIP_THUMB_SRC:.c=.o)
+
+rtosdemo.bin : rtosdemo.elf
+	$(OBJCOPY) rtosdemo.elf -O binary rtosdemo.bin
+
+rtosdemo.hex : rtosdemo.elf
+	$(OBJCOPY) rtosdemo.elf -O ihex rtosdemo.hex
+
+rtosdemo.elf : $(ARM_OBJ) $(DEMO_APP_THMUB_OBJ) $(LWIP_THUMB_OBJ) $(FREERTOS_THUMB_OBJ) $(CRT0) Makefile FreeRTOSConfig.h
+	$(CC) $(CFLAGS) $(ARM_OBJ) $(DEMO_APP_THMUB_OBJ) $(LWIP_THUMB_OBJ) $(FREERTOS_THUMB_OBJ) -nostartfiles $(CRT0) $(LINKER_FLAGS)
+
+$(DEMO_APP_THMUB_OBJ)  : %.o : %.c $(LDSCRIPT) Makefile FreeRTOSConfig.h
+	$(CC) -c $(THUMB_FLAGS) $(CFLAGS) $< -o $@
+
+$(LWIP_THUMB_OBJ)  : %.o : %.c $(LDSCRIPT) Makefile FreeRTOSConfig.h
+	$(CC) -c $(THUMB_FLAGS) $(CFLAGS) $< -o $@
+
+$(FREERTOS_THUMB_OBJ)  : %.o : %.c $(LDSCRIPT) Makefile FreeRTOSConfig.h
+	$(CC) -c $(THUMB_FLAGS) $(CFLAGS) $< -o $@
+
+$(ARM_OBJ) : %.o : %.c $(LDSCRIPT) Makefile FreeRTOSConfig.h
+	$(CC) -c $(CFLAGS) $< -o $@
+
+clean :
+	touch Makefile
+
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/rtosdemo.hzp b/20080212/Demo/lwIP_Demo_Rowley_ARM7/rtosdemo.hzp
new file mode 100644
index 000000000..0c26e03ef
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/rtosdemo.hzp
@@ -0,0 +1,86 @@
+
+
+  
+    
+    
+    
+    
+      
+      
+        
+        
+        
+        
+          
+        
+        
+      
+      
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+          
+          
+        
+        
+      
+      
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+          
+        
+        
+        
+      
+    
+    
+      
+      
+      
+        
+      
+      
+      
+        
+      
+      
+    
+    
+    
+  
+  
+  
diff --git a/20080212/Demo/lwIP_Demo_Rowley_ARM7/rtosdemo.hzs b/20080212/Demo/lwIP_Demo_Rowley_ARM7/rtosdemo.hzs
new file mode 100644
index 000000000..b663f77b7
--- /dev/null
+++ b/20080212/Demo/lwIP_Demo_Rowley_ARM7/rtosdemo.hzs
@@ -0,0 +1,82 @@
+
+
+ 
+  
+ 
+ 
+ 
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+ 
+ 
+ 
+  
+ 
+ 
+  
+ 
+ 
+  
+ 
+ 
+  
+ 
+ 
+  
+  
+  
+ 
+ 
+  
+  
+  
+ 
+ 
+  
+ 
+ 
+  
+ 
+ 
+  
+ 
+ 
+  
+ 
+ 
+ 
+  
+ 
+ 
+  
+   
+   
+   
+   
+  
+ 
+ 
+  
+ 
+ 
+  
+ 
+ 
+  
+ 
+ 
+ 
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/Changelog.txt b/20080212/Demo/lwIP_MCF5235_GCC/Changelog.txt
new file mode 100644
index 000000000..4aa9892f2
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/Changelog.txt
@@ -0,0 +1,46 @@
+
+2006-08-31 (REL_1_3) Christian Walter :
+ Notes: Fixed some bugs in the lwIP porting layer. This includes a 
+   memory leak, wrong tasknames and an unnecessary lock of the
+   scheduler.
+
+ Detailed notes:
+   - BUG: Sys_arch_thread_remove did not free the memory from
+       the TCB.
+   - BUG: Unnecessary call to vTaskSuspendAll removed.
+   - BUG: Bug with counting variable. The first to lwIP tasks
+       got the same name (lwIP0).
+
+2006-08-31 (REL_1_2) Christian Walter :
+ Notes: Added HTML documentation used for FreeRTOS. Fixed copyright
+   issues.
+
+2006-08-30 (REL_1_2) Christian Walter :
+ Notes: Fixed bug in serial transmission function vSerialPutString which
+   gives unintended behaviour. 
+
+ Detailed notes:
+   - BUG: vSerialPutString should call xSerialPutChar with a small timeout
+       such that a retransmission is tried rather fast. The previous 
+       port uses portMAX_DELAY which blocked it to long. 
+
+2006-08-29 (REL_1_1) Christian Walter :
+ Notes: Updated lwip to 1.1.1 and fixed bugs in FEC driver as well as in
+   the FreeRTOS porting layer (sys_arch.c)
+
+ Detailed notes:
+   - BUG: Fixed thread creation in sys_thread_new which needs the scheduler
+       disabled because otherwise a task could ge started immediately by
+       portYIELD( ) leaving the lwIP thread datatstructures uninitialized.
+   - BUG: The FEC driver must guard the ARP layer with a semaphore because
+       it is not thread safe.
+   - BUG: Repaired sys_mbox_free to work around an lwIP bug with a non empty
+       mbox. An assertion is only triggered if a real memory leak is detected.
+   - BUG: Timeouts are now correctly converted to ticks within the sys_arch 
+       layer.
+   - FEATURES: General improvements in the sys_arch layer.
+       author in this project.
+
+2006-08-28 (REL_1_0) Christian Walter :
+ Notes: Initial version of FreeRTOS/lwIP port for MCF5235.
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/FreeRTOSConfig.h b/20080212/Demo/lwIP_MCF5235_GCC/FreeRTOSConfig.h
new file mode 100644
index 000000000..a5b4c095b
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/FreeRTOSConfig.h
@@ -0,0 +1,85 @@
+/*
+    FreeRTOS V4.6.1 - Copyright (C) 2003-2006 Richard Barry.
+    MCF5235 Port - Copyright (C) 2006 Christian Walter.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    FreeRTOS is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with FreeRTOS; if not, write to the Free Software
+    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+    A special exception to the GPL can be applied should you wish to distribute
+    a combined work that includes FreeRTOS, without being obliged to provide
+    the source code for any proprietary components.  See the licensing section
+    of http://www.FreeRTOS.org for full details of how and when the exception
+    can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *----------------------------------------------------------*/
+
+#define configUSE_PREEMPTION        1
+#define configUSE_IDLE_HOOK         0
+#define configUSE_TICK_HOOK         0
+#define configCPU_CLOCK_HZ          ( ( unsigned portLONG ) 25000000 )
+#define configTICK_RATE_HZ          ( ( portTickType ) 1000 )
+#define configMAX_PRIORITIES        ( ( unsigned portBASE_TYPE ) 5 )
+#define configMINIMAL_STACK_SIZE    ( ( unsigned portSHORT ) 128 )
+#define configMAX_TASK_NAME_LEN     ( 16 )
+#define configUSE_TRACE_FACILITY    1
+#define configUSE_16_BIT_TICKS      0
+#define configIDLE_SHOULD_YIELD     1
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES       0 
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+
+#define INCLUDE_vTaskPrioritySet            1
+#define INCLUDE_uxTaskPriorityGet           1
+#define INCLUDE_vTaskDelete                 1
+#define INCLUDE_vTaskCleanUpResources       0
+#define INCLUDE_vTaskSuspend                1
+#define INCLUDE_vTaskDelayUntil             1
+#define INCLUDE_vTaskDelay                  1
+#define INCLUDE_xTaskGetCurrentTaskHandle   1
+
+#endif  /* FREERTOS_CONFIG_H */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/LICENSE_FREESCALE.TXT b/20080212/Demo/lwIP_MCF5235_GCC/LICENSE_FREESCALE.TXT
new file mode 100644
index 000000000..7e58b1174
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/LICENSE_FREESCALE.TXT
@@ -0,0 +1,35 @@
+MCF523x example code
+	
+IMPORTANT. Read the following Freescale Semiconductor Software License Agreement (“Agreementâ€) completely. By selecting the "I Accept" button at the end of this page, you indicate that you accept the terms of this Agreement. You may then download the file.
+
+FREESCALE SEMICONDUCTOR SOFTWARE LICENSE AGREEMENT
+
+This is a legal agreement between you (either as an individual or as an authorized representative of your employer) and Freescale Semiconductor, Inc. ("Freescale"). It concerns your rights to use this file and any accompanying written materials (the "Software"). In consideration for Freescale allowing you to access the Software, you are agreeing to be bound by the terms of this Agreement. If you do not agree to all of the terms of this Agreement, do not download the Software. If you change your mind later, stop using the Software and delete all copies of the Software in your possession or control. Any copies of the Software that you have already distributed, where permitted, and do not destroy will continue to be governed by this Agreement. Your prior use will also continue to be governed by this Agreement.
+
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+
+COPYRIGHT.  The Software is licensed to you, not sold. Freescale owns the Software, and United States copyright laws and international treaty provisions protect the Software. Therefore, you must treat the Software like any other copyrighted material (e.g. a book or musical recording). You may not use or copy the Software for any other purpose than what is described in this Agreement. Except as expressly provided herein, Freescale does not grant to you any express or implied rights under any Freescale or third-party patents, copyrights, trademarks, or trade secrets. Additionally, you must reproduce and apply any copyright or other proprietary rights notices included on or embedded in the Software to any copies or derivative works made thereof, in whole or in part, if any.
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+
+GOVERNMENT USE.  Use of the Software and any corresponding documentation, if any, is provided with RESTRICTED RIGHTS. Use, duplication or disclosure by the Government is subject to restrictions as set forth in subparagraph (c)(1)(ii) of The Rights in Technical Data and Computer Software clause at DFARS 252.227-7013 or subparagraphs (c)(l) and (2) of the Commercial Computer Software--Restricted Rights at 48 CFR 52.227-19, as applicable. Manufacturer is Freescale Semiconductor, Inc., 6501 William Cannon Drive West, Austin, TX, 78735.
+
+HIGH RISK ACTIVITIES.  You acknowledge that the Software is not fault tolerant and is not designed, manufactured or intended by Freescale for incorporation into products intended for use or resale in on-line control equipment in hazardous, dangerous to life or potentially life-threatening environments requiring fail-safe performance, such as in the operation of nuclear facilities, aircraft navigation or communication systems, air traffic control, direct life support machines or weapons systems, in which the failure of products could lead directly to death, personal injury or severe physical or environmental damage (“High Risk Activitiesâ€). You specifically represent and warrant that you will not use the Software or any derivative work of the Software for High Risk Activities.
+
+CHOICE OF LAW; VENUE; LIMITATIONS.  You agree that the statutes and laws of the United States and the State of Texas, USA, without regard to conflicts of laws principles, will apply to all matters relating to this Agreement or the Software, and you agree that any litigation will be subject to the exclusive jurisdiction of the state or federal courts in Texas, USA. You agree that regardless of any statute or law to the contrary, any claim or cause of action arising out of or related to this Agreement or the Software must be filed within one (1) year after such claim or cause of action arose or be forever barred.
+
+PRODUCT LABELING.  You are not authorized to use any Freescale trademarks, brand names, or logos.
+
+ENTIRE AGREEMENT.  This Agreement constitutes the entire agreement between you and Freescale regarding the subject matter of this Agreement, and supersedes all prior communications, negotiations, understandings, agreements or representations, either written or oral, if any. This Agreement may only be amended in written form, executed by you and Freescale.
+
+SEVERABILITY.  If any provision of this Agreement is held for any reason to be invalid or unenforceable, then the remaining provisions of this Agreement will be unimpaired and, unless a modification or replacement of the invalid or unenforceable provision is further held to deprive you or Freescale of a material benefit, in which case the Agreement will immediately terminate, the invalid or unenforceable provision will be replaced with a provision that is valid and enforceable and that comes closest to the intention underlying the invalid or unenforceable provision.
+
+NO WAIVER.  The waiver by Freescale of any breach of any provision of this Agreement will not operate or be construed as a waiver of any other or a subsequent breach of the same or a different provision.
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/Makefile b/20080212/Demo/lwIP_MCF5235_GCC/Makefile
new file mode 100644
index 000000000..a76e61176
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/Makefile
@@ -0,0 +1,94 @@
+#
+# FreeRTOS 4.1.0 - MCF5235 Coldfire Port
+#
+# Copyright (c) 2006 Christian Walter, Vienna 2006.
+#
+# $Id: Makefile,v 1.4 2006/09/06 19:55:07 wolti Exp $
+#
+# ---------------------------------------------------------------------------
+BASE        = /opt/gcc-m68k/bin
+CC	        = $(BASE)/m68k-elf-gcc
+CXX	        = $(BASE)/m68k-elf-g++
+OBJCOPY	    = $(BASE)/m68k-elf-objcopy
+SIZE	    = $(BASE)/m68k-elf-size
+INSIGHT     = $(BASE)/m68k-bdm-elf-insight
+BDMFLASH    = $(BASE)/bdmflash
+
+#CFLAGS	    = -MD -gdwarf-2 -g3 -m528x -Wall 
+CFLAGS	    = -MD -O2 -m528x -Wall \
+			  -D'GCC_MCF5235=1' -D'_GCC_USES_FP=1' \
+			  -D'__IPSBAR=((vuint8 *) 0x40000000)' -D'FSYS_2=25000000UL' \
+			  -I. -Iinclude -Iinclude/arch -Ifec \
+			  -I../../Source/include -I../Common/include \
+              -Ilwip/src/include -Ilwip/src/include/ipv4 \
+              -Ilwip/contrib/port/FreeRTOS/MCF5235 \
+              -Ilwip/contrib/port/FreeRTOS/MCF5235/netif
+
+ASFLAGS     = -MD -gdwarf-2 -g3 -m528x -Wa,--register-prefix-optional \
+              -Wa,--bitwise-or -Wa,--defsym,IPSBAR=0x40000000
+LDSCRIPT    = m5235-ram.ld
+LDFLAGS	    = -nostartfiles -m528x -Wl,--script=$(LDSCRIPT)
+
+TGT         = demo
+OTHER_CSRC  = 
+OTHER_ASRC  = $(addprefix system/, crt0.S vector.S)
+CSRC        = demo.c web.c \
+              $(addprefix system/, init.c newlib.c serial.c) \
+              $(addprefix ../Common/Minimal/, PollQ.c integer.c flop.c BlockQ.c semtest.c dynamic.c ) \
+			  $(addprefix ../../Source/, tasks.c queue.c list.c) \
+			  $(addprefix ../../Source/portable/MemMang/, heap_3.c) \
+			  $(addprefix ../../Source/portable/GCC/MCF5235/, port.c) \
+              $(addprefix lwip/src/core/, tcp_out.c inet.c mem.c memp.c netif.c pbuf.c raw.c stats.c sys.c tcp.c tcp_in.c udp.c ipv4/ip.c ipv4/ip_addr.c ipv4/icmp.c ipv4/ip_frag.c) \
+              $(addprefix lwip/src/api/, tcpip.c api_msg.c err.c api_lib.c ) \
+              $(addprefix lwip/src/netif/, etharp.c ) \
+              $(addprefix lwip/contrib/port/FreeRTOS/MCF5235/, sys_arch.c netif/fec.c netif/nbuf.c) 
+
+ASRC        = $(addprefix system/, mcf5xxx.S ) 
+OBJS        = $(CSRC:.c=.o) $(ASRC:.S=.o)
+NOLINK_OBJS = $(OTHER_CSRC:.c=.o) $(OTHER_ASRC:.S=.o)
+DEPS        = $(OBJS:.o=.d) $(NOLINK_OBJS:.o=.d)
+BIN         = $(TGT).elf
+
+.PHONY: clean all
+
+all: $(BIN)
+
+flash-programm: $(TGT).elf
+	$(OBJCOPY) -O binary $(TGT).elf $(TGT).bin
+	@BIN_SIZE=`du -b $(TGT).bin | awk '//{ print $$1; }'`; \
+	echo "programming $(TGT).bin with size $$BIN_SIZE to flash..."; \
+	$(BDMFLASH) /dev/bdmcf20 0x00000000 1 2 write $(TGT).bin 0
+
+flash-verify:
+	@BIN_SIZE=`du -b $(TGT).bin | awk '//{ print $$1; }'`; \
+	echo "loading $$BIN_SIZE bytes from target into $(TGT).vrf..."; \
+	$(BDMFLASH) /dev/bdmcf20 0x00000000 1 2 read $(TGT).vrf 0 $$BIN_SIZE
+
+flash-erase:
+	$(BDMFLASH) /dev/bdmcf20 0x00000000 1 2 erase
+
+debug:
+	$(INSIGHT) --command=m5235.gdb --se=$(TGT).elf
+
+$(BIN): $(OBJS) $(NOLINK_OBJS)
+	$(CC) $(LDFLAGS) -Wl,-Map=$(TGT).map $(OBJS) $(LDLIBS) -o $@
+
+clean:
+	rm -f $(DEPS)
+	rm -f $(OBJS) $(NOLINK_OBJS)
+	rm -f $(BIN) $(TGT).map
+
+# ---------------------------------------------------------------------------
+# rules for code generation
+# ---------------------------------------------------------------------------
+%.o:    %.c
+	$(CC) $(CFLAGS) -o $@ -c $<
+
+%.o:    %.S
+	$(CC) $(ASFLAGS) -o $@ -c $<
+
+# ---------------------------------------------------------------------------
+#  # compiler generated dependencies
+# ---------------------------------------------------------------------------
+-include $(DEPS)
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/README.txt b/20080212/Demo/lwIP_MCF5235_GCC/README.txt
new file mode 100644
index 000000000..eedebc902
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/README.txt
@@ -0,0 +1,56 @@
+
+                FREERTOS COLDFIRE MCF523x PORT with lwIP
+
+REQUIREMENTS
+============
+
+The FreeRTOS port is designed for the MCF523x processor where the hardware
+dependent part consists of the CPU and the peripherals used in this  port.
+This includes a programmable timer  (PIT)  for  the  preemptive  scheduler
+and a UART for the demo application.  The Coldfire specific part  includes
+the number and type of processor registers, the  stack  frame  layout  and
+the usage of a software interrupt (trap) for the yield call.
+
+The development environment used is  based  on  the  GNU  C  Compiler  for
+a m68k-elf target as well as the insight debugger with  some  patches  for
+the BDM interface[1].  GDB startup and linker scripts  are  supplied  with
+the demo for the M5235BCC evaluation kit from Freescale.
+
+ [1] ... BDM tools: http://sourceforge.net/projects/bdm/
+
+USAGE
+=====
+
+A makefile is supplied with the demo  application  and  a  binary  can  be
+produced by calling 'make all'.  A  special  target  'debug'  is  provided
+which executes the insight  debugger.   At  the  insight  debugger  prompt
+one should select the  appropriate  target  interface  (either  BDM/Direct
+or BDM/TCP)  and  should  download  the  application  to  the  development
+board.  It is important that the GDB  script  setup-and-load  is  executed
+prior to downloading to  initialize  the  SDRAM.   After  downloading  one
+should call the GDB function 'execute' and the PC  is  set  to  the  start
+of the executable.  Execution can  be  started  by  typing  'continue'  at
+the Insight console interface.
+After this  startup phase the  insight debugger should work as usual, i.e.
+no grayed out buttons, ...
+
+
+COMMON PROBLEMS
+===============
+ 
+Most of the problems have  their  origin  in  the  startup  scripts.   The
+following list should serve as  a  checklist  where  each  point  must  be
+satisfied for the port to work.
+
+ - The FreeRTOS port only works correctly in the supervisor mode.   There-
+   fore the Coldfire CPU must run in the supervisor mode.
+
+ - portVECTOR_TABLE does not point to the currently active  vector  table.
+   Please also note that the vector table must be in  RAM  such  that  the
+   FreeRTOS port can install a traphandler for the portYIELD() call.
+
+
+$Id: README.txt,v 1.1 2006/08/29 02:24:03 wolti Exp $
+
+MCF5235 + lwIP port - Copyright (c) 2006 Christian Walter.
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/demo.c b/20080212/Demo/lwIP_MCF5235_GCC/demo.c
new file mode 100644
index 000000000..450289b09
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/demo.c
@@ -0,0 +1,297 @@
+/*
+    FreeRTOS V4.6.1 - copyright (C) 2003-2006 Richard Barry.
+    MCF5235 Port - Copyright (C) 2006 Christian Walter.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    FreeRTOS is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with FreeRTOS; if not, write to the Free Software
+    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+    A special exception to the GPL can be applied should you wish to distribute
+    a combined work that includes FreeRTOS, without being obliged to provide
+    the source code for any proprietary components.  See the licensing section
+    of http://www.FreeRTOS.org for full details of how and when the exception
+    can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+/* ------------------------ System includes ------------------------------- */
+#include 
+#include 
+#include 
+#include 
+
+/* ------------------------ FreeRTOS includes ----------------------------- */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* ------------------------ LWIP includes --------------------------------- */
+#include "lwip/api.h"
+#include "lwip/tcpip.h"
+#include "lwip/memp.h"
+
+/* ------------------------ Project includes ------------------------------ */
+#include "mcf5xxx.h"
+#include "mcf523x.h"
+#include "serial.h"
+
+#include "web.h"
+#include "integer.h"
+#include "PollQ.h"
+#include "semtest.h"
+#include "BlockQ.h"
+#include "dynamic.h"
+#include "flop.h"
+
+/* ------------------------ Defines --------------------------------------- */
+#define mainCOM_TEST_BAUD_RATE      ( ( unsigned portLONG ) 38400 )
+
+/* Priorities for the demo application tasks. */
+#define mainLED_TASK_PRIORITY       ( tskIDLE_PRIORITY + 3 )
+#define mainCOM_TEST_PRIORITY       ( tskIDLE_PRIORITY + 2 )
+#define mainQUEUE_POLL_PRIORITY     ( tskIDLE_PRIORITY + 2 )
+#define mainCHECK_TASK_PRIORITY     ( tskIDLE_PRIORITY + 4 )
+#define mainSEM_TEST_PRIORITY       ( tskIDLE_PRIORITY + 1 )
+#define mainBLOCK_Q_PRIORITY        ( tskIDLE_PRIORITY + 2 )
+#define mainWEB_TASK_PRIORITY       ( tskIDLE_PRIORITY + 3 )
+#define STACK_DEFAULT               ( 1024 )
+
+/* Interval in which tasks are checked. */
+#define mainCHECK_PERIOD            ( ( portTickType ) 2000 / portTICK_RATE_MS  )
+
+/* Constants used by the vMemCheckTask() task. */
+#define mainCOUNT_INITIAL_VALUE     ( ( unsigned portLONG ) 0 )
+#define mainNO_TASK                 ( 0 )
+
+/* The size of the memory blocks allocated by the vMemCheckTask() task. */
+#define mainMEM_CHECK_SIZE_1        ( ( size_t ) 51 )
+#define mainMEM_CHECK_SIZE_2        ( ( size_t ) 52 )
+#define mainMEM_CHECK_SIZE_3        ( ( size_t ) 151 )
+
+/* ------------------------ Static variables ------------------------------ */
+xComPortHandle  xSTDComPort = NULL;
+
+/* ------------------------ Static functions ------------------------------ */
+static          portTASK_FUNCTION( vErrorChecks, pvParameters );
+static portLONG prvCheckOtherTasksAreStillRunning( unsigned portLONG
+                                                   ulMemCheckTaskCount );
+static          portTASK_FUNCTION( vMemCheckTask, pvParameters );
+
+/* ------------------------ Implementation -------------------------------- */
+int
+main( int argc, char *argv[] )
+{
+    asm volatile    ( "move.w  #0x2000, %sr\n\t" );
+
+    xSTDComPort = xSerialPortInitMinimal( 38400, 8 );
+    vlwIPInit(  );
+
+    /* Start the demo/test application tasks. */
+    vStartIntegerMathTasks( tskIDLE_PRIORITY );
+    vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
+    //vStartMathTasks( tskIDLE_PRIORITY );
+    vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
+    vStartDynamicPriorityTasks(  );
+    vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
+
+    /* Start the webserver. */
+    ( void )sys_thread_new( vBasicWEBServer, NULL, mainWEB_TASK_PRIORITY );
+
+    /* Start the check task - which is defined in this file. */
+    xTaskCreate( vErrorChecks, ( signed portCHAR * )"Check", 512, NULL,
+                 mainCHECK_TASK_PRIORITY, NULL );
+        /* Now all the tasks have been started - start the scheduler. */
+    vTaskStartScheduler(  );
+
+    /* Should never get here! */
+    return 0;
+}
+
+static
+portTASK_FUNCTION( vErrorChecks, pvParameters )
+{
+    unsigned portLONG ulMemCheckTaskRunningCount;
+    xTaskHandle     xCreatedTask;
+
+    /* The parameters are not used in this function. */
+    ( void )pvParameters;
+
+    for( ;; )
+    {
+        ulMemCheckTaskRunningCount = mainCOUNT_INITIAL_VALUE;
+        xCreatedTask = mainNO_TASK;
+        if( xTaskCreate( vMemCheckTask, ( signed portCHAR * )"MEM",
+                         configMINIMAL_STACK_SIZE, ( void * )&ulMemCheckTaskRunningCount,
+                         tskIDLE_PRIORITY, &xCreatedTask ) != pdPASS )
+        {
+            xSerialPutChar( xSTDComPort, 'E', portMAX_DELAY );
+        }
+        /* Delay until it is time to execute again. */
+        vTaskDelay( mainCHECK_PERIOD );
+
+        /* Delete the dynamically created task. */
+        if( xCreatedTask != mainNO_TASK )
+        {
+            vTaskDelete( xCreatedTask );
+        }
+
+        if( prvCheckOtherTasksAreStillRunning( ulMemCheckTaskRunningCount ) != pdPASS )
+        {
+            xSerialPutChar( xSTDComPort, 'E', portMAX_DELAY );
+        }
+        else
+        {
+            xSerialPutChar( xSTDComPort, '.', portMAX_DELAY );
+        }
+    }
+}
+
+static portLONG
+prvCheckOtherTasksAreStillRunning( unsigned portLONG ulMemCheckTaskCount )
+{
+    portLONG        lReturn = ( portLONG ) pdPASS;
+
+    /* Check all the demo tasks (other than the flash tasks) to ensure
+     * that they are all still running, and that none of them have detected
+     * an error.
+     */
+    if( xAreIntegerMathsTaskStillRunning(  ) != pdTRUE )
+    {
+        lReturn = ( portLONG ) pdFAIL;
+    }
+
+    if( xArePollingQueuesStillRunning(  ) != pdTRUE )
+    {
+        lReturn = ( portLONG ) pdFAIL;
+    }
+
+    if( xAreSemaphoreTasksStillRunning(  ) != pdTRUE )
+    {
+        lReturn = ( portLONG ) pdFAIL;
+    }
+
+    if( xAreDynamicPriorityTasksStillRunning(  ) != pdTRUE )
+    {
+        lReturn = ( portLONG ) pdFAIL;
+    }
+
+    if( xAreBlockingQueuesStillRunning(  ) != pdTRUE )
+    {
+        lReturn = ( portLONG ) pdFAIL;
+    }
+
+    if( ulMemCheckTaskCount == mainCOUNT_INITIAL_VALUE )
+    {
+        /* The vMemCheckTask did not increment the counter - it must
+         * have failed.
+         */
+        lReturn = ( portLONG ) pdFAIL;
+    }
+    return lReturn;
+}
+
+static void
+vMemCheckTask( void *pvParameters )
+{
+    unsigned portLONG *pulMemCheckTaskRunningCounter;
+    void           *pvMem1, *pvMem2, *pvMem3;
+    static portLONG lErrorOccurred = pdFALSE;
+
+    /* This task is dynamically created then deleted during each cycle of the
+       vErrorChecks task to check the operation of the memory allocator.  Each time
+       the task is created memory is allocated for the stack and TCB.  Each time
+       the task is deleted this memory is returned to the heap.  This task itself
+       exercises the allocator by allocating and freeing blocks.
+
+       The task executes at the idle priority so does not require a delay.
+
+       pulMemCheckTaskRunningCounter is incremented each cycle to indicate to the
+       vErrorChecks() task that this task is still executing without error. */
+
+    pulMemCheckTaskRunningCounter = ( unsigned portLONG * )pvParameters;
+
+    for( ;; )
+    {
+        if( lErrorOccurred == pdFALSE )
+        {
+            /* We have never seen an error so increment the counter. */
+            ( *pulMemCheckTaskRunningCounter )++;
+        }
+
+        /* Allocate some memory - just to give the allocator some extra
+           exercise.  This has to be in a critical section to ensure the
+           task does not get deleted while it has memory allocated. */
+        vTaskSuspendAll(  );
+        {
+            pvMem1 = pvPortMalloc( mainMEM_CHECK_SIZE_1 );
+            if( pvMem1 == NULL )
+            {
+                lErrorOccurred = pdTRUE;
+            }
+            else
+            {
+                memset( pvMem1, 0xaa, mainMEM_CHECK_SIZE_1 );
+                vPortFree( pvMem1 );
+            }
+        }
+        xTaskResumeAll(  );
+
+        /* Again - with a different size block. */
+        vTaskSuspendAll(  );
+        {
+            pvMem2 = pvPortMalloc( mainMEM_CHECK_SIZE_2 );
+            if( pvMem2 == NULL )
+            {
+                lErrorOccurred = pdTRUE;
+            }
+            else
+            {
+                memset( pvMem2, 0xaa, mainMEM_CHECK_SIZE_2 );
+                vPortFree( pvMem2 );
+            }
+        }
+        xTaskResumeAll(  );
+
+        /* Again - with a different size block. */
+        vTaskSuspendAll(  );
+        {
+            pvMem3 = pvPortMalloc( mainMEM_CHECK_SIZE_3 );
+            if( pvMem3 == NULL )
+            {
+                lErrorOccurred = pdTRUE;
+            }
+            else
+            {
+                memset( pvMem3, 0xaa, mainMEM_CHECK_SIZE_3 );
+                vPortFree( pvMem3 );
+            }
+        }
+        xTaskResumeAll(  );
+    }
+}
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x.h b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x.h
new file mode 100644
index 000000000..ae9dd63f6
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x.h
@@ -0,0 +1,46 @@
+/*
+ * These files are taken from the MCF523X source code example package
+ * which is available on the Freescale website. Freescale explicitly 
+ * grants the redistribution and modification of these source files.
+ * The complete licensing information is available in the file 
+ * LICENSE_FREESCALE.TXT.
+ *
+ * File:	mcf523x.h
+ * Purpose:	Register and bit definitions for the MCF523X
+ *
+ * Notes:	
+ *	
+ */
+
+#ifndef __MCF523X_H__
+#define __MCF523X_H__
+
+/*********************************************************************/
+
+#include "mcf523x/mcf523x_fec.h"
+#include "mcf523x/mcf523x_rng.h"
+#include "mcf523x/mcf523x_fmpll.h"
+#include "mcf523x/mcf523x_cs.h"
+#include "mcf523x/mcf523x_intc0.h"
+#include "mcf523x/mcf523x_intc1.h"
+#include "mcf523x/mcf523x_sdramc.h"
+#include "mcf523x/mcf523x_sram.h"
+#include "mcf523x/mcf523x_uart.h"
+#include "mcf523x/mcf523x_timer.h"
+#include "mcf523x/mcf523x_qspi.h"
+#include "mcf523x/mcf523x_eport.h"
+#include "mcf523x/mcf523x_i2c.h"
+#include "mcf523x/mcf523x_scm.h"
+#include "mcf523x/mcf523x_pit.h"
+#include "mcf523x/mcf523x_can.h"
+#include "mcf523x/mcf523x_wtm.h"
+#include "mcf523x/mcf523x_gpio.h"
+#include "mcf523x/mcf523x_mdha.h"
+#include "mcf523x/mcf523x_ccm.h"
+#include "mcf523x/mcf523x_rcm.h"
+#include "mcf523x/mcf523x_etpu.h"
+
+
+/********************************************************************/
+
+#endif /* __MCF523X_H__ */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_can.h b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_can.h
new file mode 100644
index 000000000..a193ba6fd
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_can.h
@@ -0,0 +1,325 @@
+/*
+ * These files are taken from the MCF523X source code example package
+ * which is available on the Freescale website. Freescale explicitly 
+ * grants the redistribution and modification of these source files.
+ * The complete licensing information is available in the file 
+ * LICENSE_FREESCALE.TXT.
+ *
+ * File:	mcf523x_can.h
+ * Purpose:	Register and bit definitions for the MCF523X
+ *
+ * Notes:	
+ *	
+ */
+
+#ifndef __MCF523X_CAN_H__
+#define __MCF523X_CAN_H__
+
+/*********************************************************************
+*
+* FlexCAN Module (CAN)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_CAN_CANMCR0        (*(vuint32*)(void*)(&__IPSBAR[0x1C0000]))
+#define MCF_CAN_CANCTRL0       (*(vuint32*)(void*)(&__IPSBAR[0x1C0004]))
+#define MCF_CAN_TIMER0         (*(vuint32*)(void*)(&__IPSBAR[0x1C0008]))
+#define MCF_CAN_RXGMASK0       (*(vuint32*)(void*)(&__IPSBAR[0x1C0010]))
+#define MCF_CAN_RX14MASK0      (*(vuint32*)(void*)(&__IPSBAR[0x1C0014]))
+#define MCF_CAN_RX15MASK0      (*(vuint32*)(void*)(&__IPSBAR[0x1C0018]))
+#define MCF_CAN_ERRCNT0        (*(vuint32*)(void*)(&__IPSBAR[0x1C001C]))
+#define MCF_CAN_ERRSTAT0       (*(vuint32*)(void*)(&__IPSBAR[0x1C0020]))
+#define MCF_CAN_IMASK0         (*(vuint16*)(void*)(&__IPSBAR[0x1C002A]))
+#define MCF_CAN_IFLAG0         (*(vuint16*)(void*)(&__IPSBAR[0x1C0032]))
+#define MCF_CAN_CANMCR1        (*(vuint32*)(void*)(&__IPSBAR[0x1F0000]))
+#define MCF_CAN_CANCTRL1       (*(vuint32*)(void*)(&__IPSBAR[0x1F0004]))
+#define MCF_CAN_TIMER1         (*(vuint32*)(void*)(&__IPSBAR[0x1F0008]))
+#define MCF_CAN_RXGMASK1       (*(vuint32*)(void*)(&__IPSBAR[0x1F0010]))
+#define MCF_CAN_RX14MASK1      (*(vuint32*)(void*)(&__IPSBAR[0x1F0014]))
+#define MCF_CAN_RX15MASK1      (*(vuint32*)(void*)(&__IPSBAR[0x1F0018]))
+#define MCF_CAN_ERRCNT1        (*(vuint32*)(void*)(&__IPSBAR[0x1F001C]))
+#define MCF_CAN_ERRSTAT1       (*(vuint32*)(void*)(&__IPSBAR[0x1F0020]))
+#define MCF_CAN_IMASK1         (*(vuint16*)(void*)(&__IPSBAR[0x1F002A]))
+#define MCF_CAN_IFLAG1         (*(vuint16*)(void*)(&__IPSBAR[0x1F0032]))
+#define MCF_CAN_CANMCR(x)      (*(vuint32*)(void*)(&__IPSBAR[0x1C0000+((x)*0x30000)]))
+#define MCF_CAN_CANCTRL(x)     (*(vuint32*)(void*)(&__IPSBAR[0x1C0004+((x)*0x30000)]))
+#define MCF_CAN_TIMER(x)       (*(vuint32*)(void*)(&__IPSBAR[0x1C0008+((x)*0x30000)]))
+#define MCF_CAN_RXGMASK(x)     (*(vuint32*)(void*)(&__IPSBAR[0x1C0010+((x)*0x30000)]))
+#define MCF_CAN_RX14MASK(x)    (*(vuint32*)(void*)(&__IPSBAR[0x1C0014+((x)*0x30000)]))
+#define MCF_CAN_RX15MASK(x)    (*(vuint32*)(void*)(&__IPSBAR[0x1C0018+((x)*0x30000)]))
+#define MCF_CAN_ERRCNT(x)      (*(vuint32*)(void*)(&__IPSBAR[0x1C001C+((x)*0x30000)]))
+#define MCF_CAN_ERRSTAT(x)     (*(vuint32*)(void*)(&__IPSBAR[0x1C0020+((x)*0x30000)]))
+#define MCF_CAN_IMASK(x)       (*(vuint16*)(void*)(&__IPSBAR[0x1C002A+((x)*0x30000)]))
+#define MCF_CAN_IFLAG(x)       (*(vuint16*)(void*)(&__IPSBAR[0x1C0032+((x)*0x30000)]))
+
+#define MCF_CAN_MBUF0_CTRL(x)		(*(vuint16 *)(void *)(&__IPSBAR[0x1C0080+((x)*0x30000)]))
+#define MCF_CAN_MBUF0_TMSTP(x)		(*(vuint16 *)(void *)(&__IPSBAR[0x1C0082+((x)*0x30000)]))
+#define MCF_CAN_MBUF0_ID(x) 	    (*(vuint32 *)(void *)(&__IPSBAR[0x1C0084+((x)*0x30000)]))
+#define MCF_CAN_MBUF0_BYTE0(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C0088+((x)*0x30000)]))
+#define MCF_CAN_MBUF0_BYTE1(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C0089+((x)*0x30000)]))
+#define MCF_CAN_MBUF0_BYTE2(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C008A+((x)*0x30000)]))
+#define MCF_CAN_MBUF0_BYTE3(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C008B+((x)*0x30000)]))
+#define MCF_CAN_MBUF0_BYTE4(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C008C+((x)*0x30000)]))
+#define MCF_CAN_MBUF0_BYTE5(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C008D+((x)*0x30000)]))
+#define MCF_CAN_MBUF0_BYTE6(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C008E+((x)*0x30000)]))
+#define MCF_CAN_MBUF0_BYTE7(x)      (*(vuint8  *)(void *)(&__IPSBAR[0x1C008F+((x)*0x30000)]))
+#define MCF_CAN_MBUF1_CTRL(x)		(*(vuint16 *)(void *)(&__IPSBAR[0x1C0090+((x)*0x30000)]))
+#define MCF_CAN_MBUF1_TMSTP(x)		(*(vuint16 *)(void *)(&__IPSBAR[0x1C0092+((x)*0x30000)]))
+#define MCF_CAN_MBUF1_ID(x)			(*(vuint32 *)(void *)(&__IPSBAR[0x1C0094+((x)*0x30000)]))
+#define MCF_CAN_MBUF1_BYTE0(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C0098+((x)*0x30000)]))
+#define MCF_CAN_MBUF1_BYTE1(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C0099+((x)*0x30000)]))
+#define MCF_CAN_MBUF1_BYTE2(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C009A+((x)*0x30000)]))
+#define MCF_CAN_MBUF1_BYTE3(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C009B+((x)*0x30000)]))
+#define MCF_CAN_MBUF1_BYTE4(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C009C+((x)*0x30000)]))
+#define MCF_CAN_MBUF1_BYTE5(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C009D+((x)*0x30000)]))
+#define MCF_CAN_MBUF1_BYTE6(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C009E+((x)*0x30000)]))
+#define MCF_CAN_MBUF1_BYTE7(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C009F+((x)*0x30000)]))
+#define MCF_CAN_MBUF2_CTRL(x)		(*(vuint16 *)(void *)(&__IPSBAR[0x1C00A0+((x)*0x30000)]))
+#define MCF_CAN_MBUF2_ID(x) 	    (*(vuint32 *)(void *)(&__IPSBAR[0x1C00A4+((x)*0x30000)]))
+#define MCF_CAN_MBUF2_BYTE0(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C00A8+((x)*0x30000)]))
+#define MCF_CAN_MBUF2_BYTE1(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C00A9+((x)*0x30000)]))
+#define MCF_CAN_MBUF2_BYTE2(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C00AA+((x)*0x30000)]))
+#define MCF_CAN_MBUF2_BYTE3(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C00AB+((x)*0x30000)]))
+#define MCF_CAN_MBUF2_BYTE4(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C00AC+((x)*0x30000)]))
+#define MCF_CAN_MBUF2_BYTE5(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C00AD+((x)*0x30000)]))
+#define MCF_CAN_MBUF2_BYTE6(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C00AE+((x)*0x30000)]))
+#define MCF_CAN_MBUF2_BYTE7(x)      (*(vuint8  *)(void *)(&__IPSBAR[0x1C00AF+((x)*0x30000)]))
+#define MCF_CAN_MBUF3_CTRL(x)		(*(vuint16 *)(void *)(&__IPSBAR[0x1C00B0+((x)*0x30000)]))
+#define MCF_CAN_MBUF3_ID(x)			(*(vuint32 *)(void *)(&__IPSBAR[0x1C00B4+((x)*0x30000)]))
+#define MCF_CAN_MBUF3_BYTE0(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C00B8+((x)*0x30000)]))
+#define MCF_CAN_MBUF3_BYTE1(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C00B9+((x)*0x30000)]))
+#define MCF_CAN_MBUF3_BYTE2(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C00BA+((x)*0x30000)]))
+#define MCF_CAN_MBUF3_BYTE3(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C00BB+((x)*0x30000)]))
+#define MCF_CAN_MBUF3_BYTE4(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C00BC+((x)*0x30000)]))
+#define MCF_CAN_MBUF3_BYTE5(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C00BD+((x)*0x30000)]))
+#define MCF_CAN_MBUF3_BYTE6(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C00BE+((x)*0x30000)]))
+#define MCF_CAN_MBUF3_BYTE7(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C00BF+((x)*0x30000)]))
+#define MCF_CAN_MBUF4_CTRL(x)		(*(vuint16 *)(void *)(&__IPSBAR[0x1C00C0+((x)*0x30000)]))
+#define MCF_CAN_MBUF4_ID(x) 	    (*(vuint32 *)(void *)(&__IPSBAR[0x1C00C4+((x)*0x30000)]))
+#define MCF_CAN_MBUF4_BYTE0(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C00C8+((x)*0x30000)]))
+#define MCF_CAN_MBUF4_BYTE1(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C00C9+((x)*0x30000)]))
+#define MCF_CAN_MBUF4_BYTE2(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C00CA+((x)*0x30000)]))
+#define MCF_CAN_MBUF4_BYTE3(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C00CB+((x)*0x30000)]))
+#define MCF_CAN_MBUF4_BYTE4(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C00CC+((x)*0x30000)]))
+#define MCF_CAN_MBUF4_BYTE5(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C00CD+((x)*0x30000)]))
+#define MCF_CAN_MBUF4_BYTE6(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C00CE+((x)*0x30000)]))
+#define MCF_CAN_MBUF4_BYTE7(x)      (*(vuint8  *)(void *)(&__IPSBAR[0x1C00CF+((x)*0x30000)]))
+#define MCF_CAN_MBUF5_CTRL(x)		(*(vuint16 *)(void *)(&__IPSBAR[0x1C00D0+((x)*0x30000)]))
+#define MCF_CAN_MBUF5_ID(x)			(*(vuint32 *)(void *)(&__IPSBAR[0x1C00D4+((x)*0x30000)]))
+#define MCF_CAN_MBUF5_BYTE0(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C00D8+((x)*0x30000)]))
+#define MCF_CAN_MBUF5_BYTE1(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C00D9+((x)*0x30000)]))
+#define MCF_CAN_MBUF5_BYTE2(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C00DA+((x)*0x30000)]))
+#define MCF_CAN_MBUF5_BYTE3(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C00DB+((x)*0x30000)]))
+#define MCF_CAN_MBUF5_BYTE4(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C00DC+((x)*0x30000)]))
+#define MCF_CAN_MBUF5_BYTE5(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C00DD+((x)*0x30000)]))
+#define MCF_CAN_MBUF5_BYTE6(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C00DE+((x)*0x30000)]))
+#define MCF_CAN_MBUF5_BYTE7(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C00DF+((x)*0x30000)]))
+#define MCF_CAN_MBUF6_CTRL(x)		(*(vuint16 *)(void *)(&__IPSBAR[0x1C00E0+((x)*0x30000)]))
+#define MCF_CAN_MBUF6_ID(x) 	    (*(vuint32 *)(void *)(&__IPSBAR[0x1C00E4+((x)*0x30000)]))
+#define MCF_CAN_MBUF6_BYTE0(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C00E8+((x)*0x30000)]))
+#define MCF_CAN_MBUF6_BYTE1(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C00E9+((x)*0x30000)]))
+#define MCF_CAN_MBUF6_BYTE2(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C00EA+((x)*0x30000)]))
+#define MCF_CAN_MBUF6_BYTE3(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C00EB+((x)*0x30000)]))
+#define MCF_CAN_MBUF6_BYTE4(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C00EC+((x)*0x30000)]))
+#define MCF_CAN_MBUF6_BYTE5(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C00ED+((x)*0x30000)]))
+#define MCF_CAN_MBUF6_BYTE6(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C00EE+((x)*0x30000)]))
+#define MCF_CAN_MBUF6_BYTE7(x)      (*(vuint8  *)(void *)(&__IPSBAR[0x1C00EF+((x)*0x30000)]))
+#define MCF_CAN_MBUF7_CTRL(x)		(*(vuint16 *)(void *)(&__IPSBAR[0x1C00F0+((x)*0x30000)]))
+#define MCF_CAN_MBUF7_ID(x)			(*(vuint32 *)(void *)(&__IPSBAR[0x1C00F4+((x)*0x30000)]))
+#define MCF_CAN_MBUF7_BYTE0(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C00F8+((x)*0x30000)]))
+#define MCF_CAN_MBUF7_BYTE1(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C00F9+((x)*0x30000)]))
+#define MCF_CAN_MBUF7_BYTE2(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C00FA+((x)*0x30000)]))
+#define MCF_CAN_MBUF7_BYTE3(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C00FB+((x)*0x30000)]))
+#define MCF_CAN_MBUF7_BYTE4(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C00FC+((x)*0x30000)]))
+#define MCF_CAN_MBUF7_BYTE5(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C00FD+((x)*0x30000)]))
+#define MCF_CAN_MBUF7_BYTE6(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C00FE+((x)*0x30000)]))
+#define MCF_CAN_MBUF7_BYTE7(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C00FF+((x)*0x30000)]))
+#define MCF_CAN_MBUF8_CTRL(x)		(*(vuint16 *)(void *)(&__IPSBAR[0x1C0100+((x)*0x30000)]))
+#define MCF_CAN_MBUF8_ID(x) 	    (*(vuint32 *)(void *)(&__IPSBAR[0x1C0104+((x)*0x30000)]))
+#define MCF_CAN_MBUF8_BYTE0(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C0108+((x)*0x30000)]))
+#define MCF_CAN_MBUF8_BYTE1(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C0109+((x)*0x30000)]))
+#define MCF_CAN_MBUF8_BYTE2(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C010A+((x)*0x30000)]))
+#define MCF_CAN_MBUF8_BYTE3(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C010B+((x)*0x30000)]))
+#define MCF_CAN_MBUF8_BYTE4(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C010C+((x)*0x30000)]))
+#define MCF_CAN_MBUF8_BYTE5(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C010D+((x)*0x30000)]))
+#define MCF_CAN_MBUF8_BYTE6(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C010E+((x)*0x30000)]))
+#define MCF_CAN_MBUF8_BYTE7(x)      (*(vuint8  *)(void *)(&__IPSBAR[0x1C010F+((x)*0x30000)]))
+#define MCF_CAN_MBUF9_CTRL(x)		(*(vuint16 *)(void *)(&__IPSBAR[0x1C0100+((x)*0x30000)]))
+#define MCF_CAN_MBUF9_ID(x)			(*(vuint32 *)(void *)(&__IPSBAR[0x1C0114+((x)*0x30000)]))
+#define MCF_CAN_MBUF9_BYTE0(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C0118+((x)*0x30000)]))
+#define MCF_CAN_MBUF9_BYTE1(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C0119+((x)*0x30000)]))
+#define MCF_CAN_MBUF9_BYTE2(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C011A+((x)*0x30000)]))
+#define MCF_CAN_MBUF9_BYTE3(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C011B+((x)*0x30000)]))
+#define MCF_CAN_MBUF9_BYTE4(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C011C+((x)*0x30000)]))
+#define MCF_CAN_MBUF9_BYTE5(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C011D+((x)*0x30000)]))
+#define MCF_CAN_MBUF9_BYTE6(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C011E+((x)*0x30000)]))
+#define MCF_CAN_MBUF9_BYTE7(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C011F+((x)*0x30000)]))
+#define MCF_CAN_MBUF10_CTRL(x)		(*(vuint16 *)(void *)(&__IPSBAR[0x1C0120+((x)*0x30000)]))
+#define MCF_CAN_MBUF10_ID(x) 	    (*(vuint32 *)(void *)(&__IPSBAR[0x1C0124+((x)*0x30000)]))
+#define MCF_CAN_MBUF10_BYTE0(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C0128+((x)*0x30000)]))
+#define MCF_CAN_MBUF10_BYTE1(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C0129+((x)*0x30000)]))
+#define MCF_CAN_MBUF10_BYTE2(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C012A+((x)*0x30000)]))
+#define MCF_CAN_MBUF10_BYTE3(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C012B+((x)*0x30000)]))
+#define MCF_CAN_MBUF10_BYTE4(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C012C+((x)*0x30000)]))
+#define MCF_CAN_MBUF10_BYTE5(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C012D+((x)*0x30000)]))
+#define MCF_CAN_MBUF10_BYTE6(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C012E+((x)*0x30000)]))
+#define MCF_CAN_MBUF10_BYTE7(x)     (*(vuint8  *)(void *)(&__IPSBAR[0x1C012F+((x)*0x30000)]))
+#define MCF_CAN_MBUF11_CTRL(x)		(*(vuint16 *)(void *)(&__IPSBAR[0x1C0130+((x)*0x30000)]))
+#define MCF_CAN_MBUF11_ID(x)		(*(vuint32 *)(void *)(&__IPSBAR[0x1C0134+((x)*0x30000)]))
+#define MCF_CAN_MBUF11_BYTE0(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C0138+((x)*0x30000)]))
+#define MCF_CAN_MBUF11_BYTE1(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C0139+((x)*0x30000)]))
+#define MCF_CAN_MBUF11_BYTE2(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C013A+((x)*0x30000)]))
+#define MCF_CAN_MBUF11_BYTE3(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C013B+((x)*0x30000)]))
+#define MCF_CAN_MBUF11_BYTE4(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C013C+((x)*0x30000)]))
+#define MCF_CAN_MBUF11_BYTE5(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C013D+((x)*0x30000)]))
+#define MCF_CAN_MBUF11_BYTE6(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C013E+((x)*0x30000)]))
+#define MCF_CAN_MBUF11_BYTE7(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C013F+((x)*0x30000)]))
+#define MCF_CAN_MBUF12_CTRL(x)		(*(vuint16 *)(void *)(&__IPSBAR[0x1C0140+((x)*0x30000)]))
+#define MCF_CAN_MBUF12_ID(x) 	    (*(vuint32 *)(void *)(&__IPSBAR[0x1C0144+((x)*0x30000)]))
+#define MCF_CAN_MBUF12_BYTE0(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C0148+((x)*0x30000)]))
+#define MCF_CAN_MBUF12_BYTE1(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C0149+((x)*0x30000)]))
+#define MCF_CAN_MBUF12_BYTE2(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C014A+((x)*0x30000)]))
+#define MCF_CAN_MBUF12_BYTE3(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C014B+((x)*0x30000)]))
+#define MCF_CAN_MBUF12_BYTE4(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C014C+((x)*0x30000)]))
+#define MCF_CAN_MBUF12_BYTE5(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C014D+((x)*0x30000)]))
+#define MCF_CAN_MBUF12_BYTE6(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C014E+((x)*0x30000)]))
+#define MCF_CAN_MBUF12_BYTE7(x)     (*(vuint8  *)(void *)(&__IPSBAR[0x1C014F+((x)*0x30000)]))
+#define MCF_CAN_MBUF13_CTRL(x)		(*(vuint16 *)(void *)(&__IPSBAR[0x1C0150+((x)*0x30000)]))
+#define MCF_CAN_MBUF13_ID(x)		(*(vuint32 *)(void *)(&__IPSBAR[0x1C0154+((x)*0x30000)]))
+#define MCF_CAN_MBUF13_BYTE0(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C0158+((x)*0x30000)]))
+#define MCF_CAN_MBUF13_BYTE1(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C0159+((x)*0x30000)]))
+#define MCF_CAN_MBUF13_BYTE2(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C015A+((x)*0x30000)]))
+#define MCF_CAN_MBUF13_BYTE3(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C015B+((x)*0x30000)]))
+#define MCF_CAN_MBUF13_BYTE4(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C015C+((x)*0x30000)]))
+#define MCF_CAN_MBUF13_BYTE5(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C015D+((x)*0x30000)]))
+#define MCF_CAN_MBUF13_BYTE6(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C015E+((x)*0x30000)]))
+#define MCF_CAN_MBUF13_BYTE7(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C015F+((x)*0x30000)]))
+#define MCF_CAN_MBUF14_CTRL(x)		(*(vuint16 *)(void *)(&__IPSBAR[0x1C0160+((x)*0x30000)]))
+#define MCF_CAN_MBUF14_ID(x) 	    (*(vuint32 *)(void *)(&__IPSBAR[0x1C0164+((x)*0x30000)]))
+#define MCF_CAN_MBUF14_BYTE0(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C0168+((x)*0x30000)]))
+#define MCF_CAN_MBUF14_BYTE1(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C0169+((x)*0x30000)]))
+#define MCF_CAN_MBUF14_BYTE2(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C016A+((x)*0x30000)]))
+#define MCF_CAN_MBUF14_BYTE3(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C016B+((x)*0x30000)]))
+#define MCF_CAN_MBUF14_BYTE4(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C016C+((x)*0x30000)]))
+#define MCF_CAN_MBUF14_BYTE5(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C016D+((x)*0x30000)]))
+#define MCF_CAN_MBUF14_BYTE6(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C016E+((x)*0x30000)]))
+#define MCF_CAN_MBUF14_BYTE7(x)     (*(vuint8  *)(void *)(&__IPSBAR[0x1C016F+((x)*0x30000)]))
+#define MCF_CAN_MBUF15_CTRL(x)		(*(vuint16 *)(void *)(&__IPSBAR[0x1C0170+((x)*0x30000)]))
+#define MCF_CAN_MBUF15_ID(x)		(*(vuint32 *)(void *)(&__IPSBAR[0x1C0174+((x)*0x30000)]))
+#define MCF_CAN_MBUF15_BYTE0(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C0178+((x)*0x30000)]))
+#define MCF_CAN_MBUF15_BYTE1(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C0179+((x)*0x30000)]))
+#define MCF_CAN_MBUF15_BYTE2(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C017A+((x)*0x30000)]))
+#define MCF_CAN_MBUF15_BYTE3(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C017B+((x)*0x30000)]))
+#define MCF_CAN_MBUF15_BYTE4(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C017C+((x)*0x30000)]))
+#define MCF_CAN_MBUF15_BYTE5(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C017D+((x)*0x30000)]))
+#define MCF_CAN_MBUF15_BYTE6(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C017E+((x)*0x30000)]))
+#define MCF_CAN_MBUF15_BYTE7(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C017F+((x)*0x30000)]))
+																				  
+																				  
+#define MCF_CAN_MBUF0_DATAL(x)	    (*(vuint32  *)(void *)(&__IPSBAR[0x1C0088+((x)*0x30000)]))
+#define MCF_CAN_MBUF0_DATAH(x)	    (*(vuint32  *)(void *)(&__IPSBAR[0x1C008C+((x)*0x30000)]))
+#define MCF_CAN_MBUF1_DATAL(x)		(*(vuint32  *)(void *)(&__IPSBAR[0x1C0098+((x)*0x30000)]))
+#define MCF_CAN_MBUF1_DATAH(x)		(*(vuint32  *)(void *)(&__IPSBAR[0x1C009C+((x)*0x30000)]))
+#define MCF_CAN_MBUF2_DATAL(x)	    (*(vuint32  *)(void *)(&__IPSBAR[0x1C00A8+((x)*0x30000)]))
+#define MCF_CAN_MBUF2_DATAH(x)	    (*(vuint32  *)(void *)(&__IPSBAR[0x1C00AC+((x)*0x30000)]))
+																				  
+																				  
+/* Bit definitions and macros for MCF_CAN_CANMCR */								  
+#define MCF_CAN_CANMCR_MAXMB(x)            (((x)&0x0000000F)<<0)				  
+#define MCF_CAN_CANMCR_SUPV                (0x00800000)							  
+#define MCF_CAN_CANMCR_FRZACK              (0x01000000)							  
+#define MCF_CAN_CANMCR_SOFTRST             (0x02000000)							  
+#define MCF_CAN_CANMCR_HALT                (0x10000000)							  
+#define MCF_CAN_CANMCR_FRZ                 (0x40000000)							  
+#define MCF_CAN_CANMCR_MDIS                (0x80000000)							  
+
+/* Bit definitions and macros for MCF_CAN_CANCTRL */
+#define MCF_CAN_CANCTRL_PROPSEG(x)         (((x)&0x00000007)<<0)
+#define MCF_CAN_CANCTRL_LOM                (0x00000008)
+#define MCF_CAN_CANCTRL_LBUF               (0x00000010)
+#define MCF_CAN_CANCTRL_TSYNC              (0x00000020)
+#define MCF_CAN_CANCTRL_BOFFREC            (0x00000040)
+#define MCF_CAN_CANCTRL_SAMP               (0x00000080)
+#define MCF_CAN_CANCTRL_LPB                (0x00001000)
+#define MCF_CAN_CANCTRL_CLKSRC             (0x00002000)
+#define MCF_CAN_CANCTRL_ERRMSK             (0x00004000)
+#define MCF_CAN_CANCTRL_BOFFMSK            (0x00008000)
+#define MCF_CAN_CANCTRL_PSEG2(x)           (((x)&0x00000007)<<16)
+#define MCF_CAN_CANCTRL_PSEG1(x)           (((x)&0x00000007)<<19)
+#define MCF_CAN_CANCTRL_RJW(x)             (((x)&0x00000003)<<22)
+#define MCF_CAN_CANCTRL_PRESDIV(x)         (((x)&0x000000FF)<<24)
+
+/* Bit definitions and macros for MCF_CAN_TIMER */
+#define MCF_CAN_TIMER_TIMER(x)             (((x)&0x0000FFFF)<<0)
+
+/* Bit definitions and macros for MCF_CAN_RXGMASK */
+#define MCF_CAN_RXGMASK_MI(x)              (((x)&0x1FFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_CAN_RX14MASK */
+#define MCF_CAN_RX14MASK_MI(x)             (((x)&0x1FFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_CAN_RX15MASK */
+#define MCF_CAN_RX15MASK_MI(x)             (((x)&0x1FFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_CAN_ERRCNT */
+#define MCF_CAN_ERRCNT_TXECTR(x)           (((x)&0x000000FF)<<0)
+#define MCF_CAN_ERRCNT_RXECTR(x)           (((x)&0x000000FF)<<8)
+
+/* Bit definitions and macros for MCF_CAN_ERRSTAT */
+#define MCF_CAN_ERRSTAT_WAKINT             (0x00000001)
+#define MCF_CAN_ERRSTAT_ERRINT             (0x00000002)
+#define MCF_CAN_ERRSTAT_BOFFINT            (0x00000004)
+#define MCF_CAN_ERRSTAT_FLTCONF(x)         (((x)&0x00000003)<<4)
+#define MCF_CAN_ERRSTAT_TXRX               (0x00000040)
+#define MCF_CAN_ERRSTAT_IDLE               (0x00000080)
+#define MCF_CAN_ERRSTAT_RXWRN              (0x00000100)
+#define MCF_CAN_ERRSTAT_TXWRN              (0x00000200)
+#define MCF_CAN_ERRSTAT_STFERR             (0x00000400)
+#define MCF_CAN_ERRSTAT_FRMERR             (0x00000800)
+#define MCF_CAN_ERRSTAT_CRCERR             (0x00001000)
+#define MCF_CAN_ERRSTAT_ACKERR             (0x00002000)
+#define MCF_CAN_ERRSTAT_BITERR(x)          (((x)&0x00000003)<<14)
+#define MCF_CAN_ERRSTAT_FLTCONF_ACTIVE     (0x00000000)
+#define MCF_CAN_ERRSTAT_FLTCONF_PASSIVE    (0x00000010)
+#define MCF_CAN_ERRSTAT_FLTCONF_BUSOFF     (0x00000020)
+
+/* Bit definitions and macros for MCF_CAN_IMASK */
+#define MCF_CAN_IMASK_BUF0M                (0x0001)
+#define MCF_CAN_IMASK_BUF1M                (0x0002)
+#define MCF_CAN_IMASK_BUF2M                (0x0004)
+#define MCF_CAN_IMASK_BUF3M                (0x0008)
+#define MCF_CAN_IMASK_BUF4M                (0x0010)
+#define MCF_CAN_IMASK_BUF5M                (0x0020)
+#define MCF_CAN_IMASK_BUF6M                (0x0040)
+#define MCF_CAN_IMASK_BUF7M                (0x0080)
+#define MCF_CAN_IMASK_BUF8M                (0x0100)
+#define MCF_CAN_IMASK_BUF9M                (0x0200)
+#define MCF_CAN_IMASK_BUF10M               (0x0400)
+#define MCF_CAN_IMASK_BUF11M               (0x0800)
+#define MCF_CAN_IMASK_BUF12M               (0x1000)
+#define MCF_CAN_IMASK_BUF13M               (0x2000)
+#define MCF_CAN_IMASK_BUF14M               (0x4000)
+#define MCF_CAN_IMASK_BUF15M               (0x8000)
+
+/* Bit definitions and macros for MCF_CAN_IFLAG */
+#define MCF_CAN_IFLAG_BUF0I                (0x0001)
+#define MCF_CAN_IFLAG_BUF1I                (0x0002)
+#define MCF_CAN_IFLAG_BUF2I                (0x0004)
+#define MCF_CAN_IFLAG_BUF3I                (0x0008)
+#define MCF_CAN_IFLAG_BUF4I                (0x0010)
+#define MCF_CAN_IFLAG_BUF5I                (0x0020)
+#define MCF_CAN_IFLAG_BUF6I                (0x0040)
+#define MCF_CAN_IFLAG_BUF7I                (0x0080)
+#define MCF_CAN_IFLAG_BUF8I                (0x0100)
+#define MCF_CAN_IFLAG_BUF9I                (0x0200)
+#define MCF_CAN_IFLAG_BUF10I               (0x0400)
+#define MCF_CAN_IFLAG_BUF11I               (0x0800)
+#define MCF_CAN_IFLAG_BUF12I               (0x1000)
+#define MCF_CAN_IFLAG_BUF13I               (0x2000)
+#define MCF_CAN_IFLAG_BUF14I               (0x4000)
+#define MCF_CAN_IFLAG_BUF15I               (0x8000)
+
+/********************************************************************/
+
+#endif /* __MCF523X_CAN_H__ */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_ccm.h b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_ccm.h
new file mode 100644
index 000000000..dd3b71c64
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_ccm.h
@@ -0,0 +1,56 @@
+/*
+ * These files are taken from the MCF523X source code example package
+ * which is available on the Freescale website. Freescale explicitly 
+ * grants the redistribution and modification of these source files.
+ * The complete licensing information is available in the file 
+ * LICENSE_FREESCALE.TXT.
+ *
+ * File:	mcf523x_ccm.h
+ * Purpose:	Register and bit definitions for the MCF523X
+ *
+ * Notes:	
+ *	
+ */
+
+#ifndef __MCF523X_CCM_H__
+#define __MCF523X_CCM_H__
+
+/*********************************************************************
+*
+* Chip Configuration Module (CCM)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_CCM_CCR     (*(vuint16*)(void*)(&__IPSBAR[0x110004]))
+#define MCF_CCM_LPCR    (*(vuint8 *)(void*)(&__IPSBAR[0x110007]))
+#define MCF_CCM_CIR     (*(vuint16*)(void*)(&__IPSBAR[0x11000A]))
+#define MCF_CCM_RCON    (*(vuint16*)(void*)(&__IPSBAR[0x110008]))
+
+/* Bit definitions and macros for MCF_CCM_CCR */
+#define MCF_CCM_CCR_BMT(x)        (((x)&0x0007)<<0)
+#define MCF_CCM_CCR_BME           (0x0008)
+#define MCF_CCM_CCR_SZEN          (0x0040)
+#define MCF_CCM_CCR_MODE(x)       (((x)&0x0007)<<8)
+
+/* Bit definitions and macros for MCF_CCM_LPCR */
+#define MCF_CCM_LPCR_STPMD(x)     (((x)&0x03)<<3)
+#define MCF_CCM_LPCR_LPMD(x)      (((x)&0x03)<<6)
+#define MCF_CCM_LPCR_LPMD_STOP    (0xC0)
+#define MCF_CCM_LPCR_LPMD_WAIT    (0x80)
+#define MCF_CCM_LPCR_LPMD_DOZE    (0x40)
+#define MCF_CCM_LPCR_LPMD_RUN     (0x00)
+
+/* Bit definitions and macros for MCF_CCM_CIR */
+#define MCF_CCM_CIR_PRN(x)        (((x)&0x003F)<<0)
+#define MCF_CCM_CIR_PIN(x)        (((x)&0x03FF)<<6)
+
+/* Bit definitions and macros for MCF_CCM_RCON */
+#define MCF_CCM_RCON_MODE         (0x0001)
+#define MCF_CCM_RCON_BOOTPS(x)    (((x)&0x0003)<<3)
+#define MCF_CCM_RCON_RLOAD        (0x0020)
+#define MCF_CCM_RCON_RCSC(x)      (((x)&0x0003)<<8)
+
+/********************************************************************/
+
+#endif /* __MCF523X_CCM_H__ */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_cs.h b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_cs.h
new file mode 100644
index 000000000..240cdf214
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_cs.h
@@ -0,0 +1,101 @@
+/*
+ * These files are taken from the MCF523X source code example package
+ * which is available on the Freescale website. Freescale explicitly 
+ * grants the redistribution and modification of these source files.
+ * The complete licensing information is available in the file 
+ * LICENSE_FREESCALE.TXT.
+ *
+ * File:	mcf523x_cs.h
+ * Purpose:	Register and bit definitions for the MCF523X
+ *
+ * Notes:	
+ *	
+ */
+
+#ifndef __MCF523X_CS_H__
+#define __MCF523X_CS_H__
+
+/*********************************************************************
+*
+* Chip Selects (CS)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_CS_CSAR0      (*(vuint16*)(void*)(&__IPSBAR[0x000080]))
+#define MCF_CS_CSMR0      (*(vuint32*)(void*)(&__IPSBAR[0x000084]))
+#define MCF_CS_CSCR0      (*(vuint16*)(void*)(&__IPSBAR[0x00008A]))
+#define MCF_CS_CSAR1      (*(vuint16*)(void*)(&__IPSBAR[0x00008C]))
+#define MCF_CS_CSMR1      (*(vuint32*)(void*)(&__IPSBAR[0x000090]))
+#define MCF_CS_CSCR1      (*(vuint16*)(void*)(&__IPSBAR[0x000096]))
+#define MCF_CS_CSAR2      (*(vuint16*)(void*)(&__IPSBAR[0x000098]))
+#define MCF_CS_CSMR2      (*(vuint32*)(void*)(&__IPSBAR[0x00009C]))
+#define MCF_CS_CSCR2      (*(vuint16*)(void*)(&__IPSBAR[0x0000A2]))
+#define MCF_CS_CSAR3      (*(vuint16*)(void*)(&__IPSBAR[0x0000A4]))
+#define MCF_CS_CSMR3      (*(vuint32*)(void*)(&__IPSBAR[0x0000A8]))
+#define MCF_CS_CSCR3      (*(vuint16*)(void*)(&__IPSBAR[0x0000AE]))
+#define MCF_CS_CSAR4      (*(vuint16*)(void*)(&__IPSBAR[0x0000B0]))
+#define MCF_CS_CSMR4      (*(vuint32*)(void*)(&__IPSBAR[0x0000B4]))
+#define MCF_CS_CSCR4      (*(vuint16*)(void*)(&__IPSBAR[0x0000BA]))
+#define MCF_CS_CSAR5      (*(vuint16*)(void*)(&__IPSBAR[0x0000BC]))
+#define MCF_CS_CSMR5      (*(vuint32*)(void*)(&__IPSBAR[0x0000C0]))
+#define MCF_CS_CSCR5      (*(vuint16*)(void*)(&__IPSBAR[0x0000C6]))
+#define MCF_CS_CSAR6      (*(vuint16*)(void*)(&__IPSBAR[0x0000C8]))
+#define MCF_CS_CSMR6      (*(vuint32*)(void*)(&__IPSBAR[0x0000CC]))
+#define MCF_CS_CSCR6      (*(vuint16*)(void*)(&__IPSBAR[0x0000D2]))
+#define MCF_CS_CSAR7      (*(vuint16*)(void*)(&__IPSBAR[0x0000D4]))
+#define MCF_CS_CSMR7      (*(vuint32*)(void*)(&__IPSBAR[0x0000D8]))
+#define MCF_CS_CSCR7      (*(vuint16*)(void*)(&__IPSBAR[0x0000DE]))
+#define MCF_CS_CSAR(x)    (*(vuint16*)(void*)(&__IPSBAR[0x000080+((x)*0x00C)]))
+#define MCF_CS_CSMR(x)    (*(vuint32*)(void*)(&__IPSBAR[0x000084+((x)*0x00C)]))
+#define MCF_CS_CSCR(x)    (*(vuint16*)(void*)(&__IPSBAR[0x00008A+((x)*0x00C)]))
+
+/* Bit definitions and macros for MCF_CS_CSAR */
+#define MCF_CS_CSAR_BA(x)        ((uint16)(((x)&0xFFFF0000)>>16))
+
+/* Bit definitions and macros for MCF_CS_CSMR */
+#define MCF_CS_CSMR_V            (0x00000001)
+#define MCF_CS_CSMR_UD           (0x00000002)
+#define MCF_CS_CSMR_UC           (0x00000004)
+#define MCF_CS_CSMR_SD           (0x00000008)
+#define MCF_CS_CSMR_SC           (0x00000010)
+#define MCF_CS_CSMR_CI           (0x00000020)
+#define MCF_CS_CSMR_AM           (0x00000040)
+#define MCF_CS_CSMR_WP           (0x00000100)
+#define MCF_CS_CSMR_BAM(x)       (((x)&0x0000FFFF)<<16)
+#define MCF_CS_CSMR_BAM_4G       (0xFFFF0000)
+#define MCF_CS_CSMR_BAM_2G       (0x7FFF0000)
+#define MCF_CS_CSMR_BAM_1G       (0x3FFF0000)
+#define MCF_CS_CSMR_BAM_1024M    (0x3FFF0000)
+#define MCF_CS_CSMR_BAM_512M     (0x1FFF0000)
+#define MCF_CS_CSMR_BAM_256M     (0x0FFF0000)
+#define MCF_CS_CSMR_BAM_128M     (0x07FF0000)
+#define MCF_CS_CSMR_BAM_64M      (0x03FF0000)
+#define MCF_CS_CSMR_BAM_32M      (0x01FF0000)
+#define MCF_CS_CSMR_BAM_16M      (0x00FF0000)
+#define MCF_CS_CSMR_BAM_8M       (0x007F0000)
+#define MCF_CS_CSMR_BAM_4M       (0x003F0000)
+#define MCF_CS_CSMR_BAM_2M       (0x001F0000)
+#define MCF_CS_CSMR_BAM_1M       (0x000F0000)
+#define MCF_CS_CSMR_BAM_1024K    (0x000F0000)
+#define MCF_CS_CSMR_BAM_512K     (0x00070000)
+#define MCF_CS_CSMR_BAM_256K     (0x00030000)
+#define MCF_CS_CSMR_BAM_128K     (0x00010000)
+#define MCF_CS_CSMR_BAM_64K      (0x00000000)
+
+/* Bit definitions and macros for MCF_CS_CSCR */
+#define MCF_CS_CSCR_SWWS(x)      (((x)&0x0007)<<0)
+#define MCF_CS_CSCR_BSTW         (0x0008)
+#define MCF_CS_CSCR_BSTR         (0x0010)
+#define MCF_CS_CSCR_BEM          (0x0020)
+#define MCF_CS_CSCR_PS(x)        (((x)&0x0003)<<6)
+#define MCF_CS_CSCR_AA           (0x0100)
+#define MCF_CS_CSCR_IWS(x)       (((x)&0x000F)<<10)
+#define MCF_CS_CSCR_SRWS(x)      (((x)&0x0003)<<14)
+#define MCF_CS_CSCR_PS_8         (0x0040)
+#define MCF_CS_CSCR_PS_16        (0x0080)
+#define MCF_CS_CSCR_PS_32        (0x0000)
+
+/********************************************************************/
+
+#endif /* __MCF523X_CS_H__ */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_eport.h b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_eport.h
new file mode 100644
index 000000000..9ee8d7c1c
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_eport.h
@@ -0,0 +1,92 @@
+/*
+ * These files are taken from the MCF523X source code example package
+ * which is available on the Freescale website. Freescale explicitly 
+ * grants the redistribution and modification of these source files.
+ * The complete licensing information is available in the file 
+ * LICENSE_FREESCALE.TXT.
+ *
+ * File:	mcf523x_eport.h
+ * Purpose:	Register and bit definitions for the MCF523X
+ *
+ * Notes:	
+ *	
+ */
+
+#ifndef __MCF523X_EPORT_H__
+#define __MCF523X_EPORT_H__
+
+/*********************************************************************
+*
+* Edge Port Module (EPORT)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_EPORT_EPPAR    (*(vuint16*)(void*)(&__IPSBAR[0x130000]))
+#define MCF_EPORT_EPDDR    (*(vuint8 *)(void*)(&__IPSBAR[0x130002]))
+#define MCF_EPORT_EPIER    (*(vuint8 *)(void*)(&__IPSBAR[0x130003]))
+#define MCF_EPORT_EPDR     (*(vuint8 *)(void*)(&__IPSBAR[0x130004]))
+#define MCF_EPORT_EPPDR    (*(vuint8 *)(void*)(&__IPSBAR[0x130005]))
+#define MCF_EPORT_EPFR     (*(vuint8 *)(void*)(&__IPSBAR[0x130006]))
+
+/* Bit definitions and macros for MCF_EPORT_EPPAR */
+#define MCF_EPORT_EPPAR_EPPA1(x)         (((x)&0x0003)<<2)
+#define MCF_EPORT_EPPAR_EPPA2(x)         (((x)&0x0003)<<4)
+#define MCF_EPORT_EPPAR_EPPA3(x)         (((x)&0x0003)<<6)
+#define MCF_EPORT_EPPAR_EPPA4(x)         (((x)&0x0003)<<8)
+#define MCF_EPORT_EPPAR_EPPA5(x)         (((x)&0x0003)<<10)
+#define MCF_EPORT_EPPAR_EPPA6(x)         (((x)&0x0003)<<12)
+#define MCF_EPORT_EPPAR_EPPA7(x)         (((x)&0x0003)<<14)
+#define MCF_EPORT_EPPAR_EPPAx_LEVEL      (0)
+#define MCF_EPORT_EPPAR_EPPAx_RISING     (1)
+#define MCF_EPORT_EPPAR_EPPAx_FALLING    (2)
+#define MCF_EPORT_EPPAR_EPPAx_BOTH       (3)
+
+/* Bit definitions and macros for MCF_EPORT_EPDDR */
+#define MCF_EPORT_EPDDR_EPDD1            (0x02)
+#define MCF_EPORT_EPDDR_EPDD2            (0x04)
+#define MCF_EPORT_EPDDR_EPDD3            (0x08)
+#define MCF_EPORT_EPDDR_EPDD4            (0x10)
+#define MCF_EPORT_EPDDR_EPDD5            (0x20)
+#define MCF_EPORT_EPDDR_EPDD6            (0x40)
+#define MCF_EPORT_EPDDR_EPDD7            (0x80)
+
+/* Bit definitions and macros for MCF_EPORT_EPIER */
+#define MCF_EPORT_EPIER_EPIE1            (0x02)
+#define MCF_EPORT_EPIER_EPIE2            (0x04)
+#define MCF_EPORT_EPIER_EPIE3            (0x08)
+#define MCF_EPORT_EPIER_EPIE4            (0x10)
+#define MCF_EPORT_EPIER_EPIE5            (0x20)
+#define MCF_EPORT_EPIER_EPIE6            (0x40)
+#define MCF_EPORT_EPIER_EPIE7            (0x80)
+
+/* Bit definitions and macros for MCF_EPORT_EPDR */
+#define MCF_EPORT_EPDR_EPD1              (0x02)
+#define MCF_EPORT_EPDR_EPD2              (0x04)
+#define MCF_EPORT_EPDR_EPD3              (0x08)
+#define MCF_EPORT_EPDR_EPD4              (0x10)
+#define MCF_EPORT_EPDR_EPD5              (0x20)
+#define MCF_EPORT_EPDR_EPD6              (0x40)
+#define MCF_EPORT_EPDR_EPD7              (0x80)
+
+/* Bit definitions and macros for MCF_EPORT_EPPDR */
+#define MCF_EPORT_EPPDR_EPPD1            (0x02)
+#define MCF_EPORT_EPPDR_EPPD2            (0x04)
+#define MCF_EPORT_EPPDR_EPPD3            (0x08)
+#define MCF_EPORT_EPPDR_EPPD4            (0x10)
+#define MCF_EPORT_EPPDR_EPPD5            (0x20)
+#define MCF_EPORT_EPPDR_EPPD6            (0x40)
+#define MCF_EPORT_EPPDR_EPPD7            (0x80)
+
+/* Bit definitions and macros for MCF_EPORT_EPFR */
+#define MCF_EPORT_EPFR_EPF1              (0x02)
+#define MCF_EPORT_EPFR_EPF2              (0x04)
+#define MCF_EPORT_EPFR_EPF3              (0x08)
+#define MCF_EPORT_EPFR_EPF4              (0x10)
+#define MCF_EPORT_EPFR_EPF5              (0x20)
+#define MCF_EPORT_EPFR_EPF6              (0x40)
+#define MCF_EPORT_EPFR_EPF7              (0x80)
+
+/********************************************************************/
+
+#endif /* __MCF523X_EPORT_H__ */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_etpu.h b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_etpu.h
new file mode 100644
index 000000000..5a0d9ca74
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_etpu.h
@@ -0,0 +1,493 @@
+/*
+ * These files are taken from the MCF523X source code example package
+ * which is available on the Freescale website. Freescale explicitly 
+ * grants the redistribution and modification of these source files.
+ * The complete licensing information is available in the file 
+ * LICENSE_FREESCALE.TXT.
+ *
+ * File:	mcf523x_etpu.h
+ * Purpose:	Register and bit definitions for the MCF523X
+ *
+ * Notes:	
+ *	
+ */
+
+#ifndef __MCF523X_ETPU_H__
+#define __MCF523X_ETPU_H__
+
+/*********************************************************************
+*
+* enhanced Time Processor Unit (ETPU)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_ETPU_EMCR          (*(vuint32*)(void*)(&__IPSBAR[0x1D0000]))
+#define MCF_ETPU_ECDCR         (*(vuint32*)(void*)(&__IPSBAR[0x1D0004]))
+#define MCF_ETPU_EMISCCR       (*(vuint32*)(void*)(&__IPSBAR[0x1D000C]))
+#define MCF_ETPU_ESCMODR       (*(vuint32*)(void*)(&__IPSBAR[0x1D0010]))
+#define MCF_ETPU_EECR          (*(vuint32*)(void*)(&__IPSBAR[0x1D0014]))
+#define MCF_ETPU_ETBCR         (*(vuint32*)(void*)(&__IPSBAR[0x1D0020]))
+#define MCF_ETPU_ETB1R         (*(vuint32*)(void*)(&__IPSBAR[0x1D0024]))
+#define MCF_ETPU_ETB2R         (*(vuint32*)(void*)(&__IPSBAR[0x1D0028]))
+#define MCF_ETPU_EREDCR        (*(vuint32*)(void*)(&__IPSBAR[0x1D002C]))
+#define MCF_ETPU_ECISR         (*(vuint32*)(void*)(&__IPSBAR[0x1D0200]))
+#define MCF_ETPU_ECDTRSR       (*(vuint32*)(void*)(&__IPSBAR[0x1D0210]))
+#define MCF_ETPU_ECIOSR        (*(vuint32*)(void*)(&__IPSBAR[0x1D0220]))
+#define MCF_ETPU_ECDTROSR      (*(vuint32*)(void*)(&__IPSBAR[0x1D0230]))
+#define MCF_ETPU_ECIER         (*(vuint32*)(void*)(&__IPSBAR[0x1D0240]))
+#define MCF_ETPU_ECDTRER       (*(vuint32*)(void*)(&__IPSBAR[0x1D0250]))
+#define MCF_ETPU_ECPSSR        (*(vuint32*)(void*)(&__IPSBAR[0x1D0280]))
+#define MCF_ETPU_ECSSR         (*(vuint32*)(void*)(&__IPSBAR[0x1D0290]))
+#define MCF_ETPU_EC0SCR        (*(vuint32*)(void*)(&__IPSBAR[0x1D0404]))
+#define MCF_ETPU_EC1SCR        (*(vuint32*)(void*)(&__IPSBAR[0x1D0414]))
+#define MCF_ETPU_EC2SCR        (*(vuint32*)(void*)(&__IPSBAR[0x1D0424]))
+#define MCF_ETPU_EC3SCR        (*(vuint32*)(void*)(&__IPSBAR[0x1D0434]))
+#define MCF_ETPU_EC4SCR        (*(vuint32*)(void*)(&__IPSBAR[0x1D0444]))
+#define MCF_ETPU_EC5SCR        (*(vuint32*)(void*)(&__IPSBAR[0x1D0454]))
+#define MCF_ETPU_EC6SCR        (*(vuint32*)(void*)(&__IPSBAR[0x1D0464]))
+#define MCF_ETPU_EC7SCR        (*(vuint32*)(void*)(&__IPSBAR[0x1D0474]))
+#define MCF_ETPU_EC8SCR        (*(vuint32*)(void*)(&__IPSBAR[0x1D0484]))
+#define MCF_ETPU_EC9SCR        (*(vuint32*)(void*)(&__IPSBAR[0x1D0494]))
+#define MCF_ETPU_EC10SCR       (*(vuint32*)(void*)(&__IPSBAR[0x1D04A4]))
+#define MCF_ETPU_EC11SCR       (*(vuint32*)(void*)(&__IPSBAR[0x1D04B4]))
+#define MCF_ETPU_EC12SCR       (*(vuint32*)(void*)(&__IPSBAR[0x1D04C4]))
+#define MCF_ETPU_EC13SCR       (*(vuint32*)(void*)(&__IPSBAR[0x1D04D4]))
+#define MCF_ETPU_EC14SCR       (*(vuint32*)(void*)(&__IPSBAR[0x1D04E4]))
+#define MCF_ETPU_EC15SCR       (*(vuint32*)(void*)(&__IPSBAR[0x1D04F4]))
+#define MCF_ETPU_EC16SCR       (*(vuint32*)(void*)(&__IPSBAR[0x1D0504]))
+#define MCF_ETPU_EC17SCR       (*(vuint32*)(void*)(&__IPSBAR[0x1D0514]))
+#define MCF_ETPU_EC18SCR       (*(vuint32*)(void*)(&__IPSBAR[0x1D0524]))
+#define MCF_ETPU_EC19SCR       (*(vuint32*)(void*)(&__IPSBAR[0x1D0534]))
+#define MCF_ETPU_EC20SCR       (*(vuint32*)(void*)(&__IPSBAR[0x1D0544]))
+#define MCF_ETPU_EC21SCR       (*(vuint32*)(void*)(&__IPSBAR[0x1D0554]))
+#define MCF_ETPU_EC22SCR       (*(vuint32*)(void*)(&__IPSBAR[0x1D0564]))
+#define MCF_ETPU_EC23SCR       (*(vuint32*)(void*)(&__IPSBAR[0x1D0574]))
+#define MCF_ETPU_EC24SCR       (*(vuint32*)(void*)(&__IPSBAR[0x1D0584]))
+#define MCF_ETPU_EC25SCR       (*(vuint32*)(void*)(&__IPSBAR[0x1D0594]))
+#define MCF_ETPU_EC26SCR       (*(vuint32*)(void*)(&__IPSBAR[0x1D05A4]))
+#define MCF_ETPU_EC27SCR       (*(vuint32*)(void*)(&__IPSBAR[0x1D05B4]))
+#define MCF_ETPU_EC28SCR       (*(vuint32*)(void*)(&__IPSBAR[0x1D05C4]))
+#define MCF_ETPU_EC29SCR       (*(vuint32*)(void*)(&__IPSBAR[0x1D05D4]))
+#define MCF_ETPU_EC30SCR       (*(vuint32*)(void*)(&__IPSBAR[0x1D05E4]))
+#define MCF_ETPU_EC31SCR       (*(vuint32*)(void*)(&__IPSBAR[0x1D05F4]))
+#define MCF_ETPU_ECnSCR(x)     (*(vuint32*)(void*)(&__IPSBAR[0x1D0404+((x)*0x010)]))
+#define MCF_ETPU_EC0CR         (*(vuint32*)(void*)(&__IPSBAR[0x1D0400]))
+#define MCF_ETPU_EC1CR         (*(vuint32*)(void*)(&__IPSBAR[0x1D0410]))
+#define MCF_ETPU_EC2CR         (*(vuint32*)(void*)(&__IPSBAR[0x1D0420]))
+#define MCF_ETPU_EC3CR         (*(vuint32*)(void*)(&__IPSBAR[0x1D0430]))
+#define MCF_ETPU_EC4CR         (*(vuint32*)(void*)(&__IPSBAR[0x1D0440]))
+#define MCF_ETPU_EC5CR         (*(vuint32*)(void*)(&__IPSBAR[0x1D0450]))
+#define MCF_ETPU_EC6CR         (*(vuint32*)(void*)(&__IPSBAR[0x1D0460]))
+#define MCF_ETPU_EC7CR         (*(vuint32*)(void*)(&__IPSBAR[0x1D0470]))
+#define MCF_ETPU_EC8CR         (*(vuint32*)(void*)(&__IPSBAR[0x1D0480]))
+#define MCF_ETPU_EC9CR         (*(vuint32*)(void*)(&__IPSBAR[0x1D0490]))
+#define MCF_ETPU_EC10CR        (*(vuint32*)(void*)(&__IPSBAR[0x1D04A0]))
+#define MCF_ETPU_EC11CR        (*(vuint32*)(void*)(&__IPSBAR[0x1D04B0]))
+#define MCF_ETPU_EC12CR        (*(vuint32*)(void*)(&__IPSBAR[0x1D04C0]))
+#define MCF_ETPU_EC13CR        (*(vuint32*)(void*)(&__IPSBAR[0x1D04D0]))
+#define MCF_ETPU_EC14CR        (*(vuint32*)(void*)(&__IPSBAR[0x1D04E0]))
+#define MCF_ETPU_EC15CR        (*(vuint32*)(void*)(&__IPSBAR[0x1D04F0]))
+#define MCF_ETPU_EC16CR        (*(vuint32*)(void*)(&__IPSBAR[0x1D0500]))
+#define MCF_ETPU_EC17CR        (*(vuint32*)(void*)(&__IPSBAR[0x1D0510]))
+#define MCF_ETPU_EC18CR        (*(vuint32*)(void*)(&__IPSBAR[0x1D0520]))
+#define MCF_ETPU_EC19CR        (*(vuint32*)(void*)(&__IPSBAR[0x1D0530]))
+#define MCF_ETPU_EC20CR        (*(vuint32*)(void*)(&__IPSBAR[0x1D0540]))
+#define MCF_ETPU_EC21CR        (*(vuint32*)(void*)(&__IPSBAR[0x1D0550]))
+#define MCF_ETPU_EC22CR        (*(vuint32*)(void*)(&__IPSBAR[0x1D0560]))
+#define MCF_ETPU_EC23CR        (*(vuint32*)(void*)(&__IPSBAR[0x1D0570]))
+#define MCF_ETPU_EC24CR        (*(vuint32*)(void*)(&__IPSBAR[0x1D0580]))
+#define MCF_ETPU_EC25CR        (*(vuint32*)(void*)(&__IPSBAR[0x1D0590]))
+#define MCF_ETPU_EC26CR        (*(vuint32*)(void*)(&__IPSBAR[0x1D05A0]))
+#define MCF_ETPU_EC27CR        (*(vuint32*)(void*)(&__IPSBAR[0x1D05B0]))
+#define MCF_ETPU_EC28CR        (*(vuint32*)(void*)(&__IPSBAR[0x1D05C0]))
+#define MCF_ETPU_EC29CR        (*(vuint32*)(void*)(&__IPSBAR[0x1D05D0]))
+#define MCF_ETPU_EC30CR        (*(vuint32*)(void*)(&__IPSBAR[0x1D05E0]))
+#define MCF_ETPU_EC31CR        (*(vuint32*)(void*)(&__IPSBAR[0x1D05F0]))
+#define MCF_ETPU_ECnCR(x)      (*(vuint32*)(void*)(&__IPSBAR[0x1D0400+((x)*0x010)]))
+#define MCF_ETPU_EC0HSSR       (*(vuint32*)(void*)(&__IPSBAR[0x1D0408]))
+#define MCF_ETPU_EC1HSSR       (*(vuint32*)(void*)(&__IPSBAR[0x1D0418]))
+#define MCF_ETPU_EC2HSSR       (*(vuint32*)(void*)(&__IPSBAR[0x1D0428]))
+#define MCF_ETPU_EC3HSSR       (*(vuint32*)(void*)(&__IPSBAR[0x1D0438]))
+#define MCF_ETPU_EC4HSSR       (*(vuint32*)(void*)(&__IPSBAR[0x1D0448]))
+#define MCF_ETPU_EC5HSSR       (*(vuint32*)(void*)(&__IPSBAR[0x1D0458]))
+#define MCF_ETPU_EC6HSSR       (*(vuint32*)(void*)(&__IPSBAR[0x1D0468]))
+#define MCF_ETPU_EC7HSSR       (*(vuint32*)(void*)(&__IPSBAR[0x1D0478]))
+#define MCF_ETPU_EC8HSSR       (*(vuint32*)(void*)(&__IPSBAR[0x1D0488]))
+#define MCF_ETPU_EC9HSSR       (*(vuint32*)(void*)(&__IPSBAR[0x1D0498]))
+#define MCF_ETPU_EC10HSSR      (*(vuint32*)(void*)(&__IPSBAR[0x1D04A8]))
+#define MCF_ETPU_EC11HSSR      (*(vuint32*)(void*)(&__IPSBAR[0x1D04B8]))
+#define MCF_ETPU_EC12HSSR      (*(vuint32*)(void*)(&__IPSBAR[0x1D04C8]))
+#define MCF_ETPU_EC13HSSR      (*(vuint32*)(void*)(&__IPSBAR[0x1D04D8]))
+#define MCF_ETPU_EC14HSSR      (*(vuint32*)(void*)(&__IPSBAR[0x1D04E8]))
+#define MCF_ETPU_EC15HSSR      (*(vuint32*)(void*)(&__IPSBAR[0x1D04F8]))
+#define MCF_ETPU_EC16HSSR      (*(vuint32*)(void*)(&__IPSBAR[0x1D0508]))
+#define MCF_ETPU_EC17HSSR      (*(vuint32*)(void*)(&__IPSBAR[0x1D0518]))
+#define MCF_ETPU_EC18HSSR      (*(vuint32*)(void*)(&__IPSBAR[0x1D0528]))
+#define MCF_ETPU_EC19HSSR      (*(vuint32*)(void*)(&__IPSBAR[0x1D0538]))
+#define MCF_ETPU_EC20HSSR      (*(vuint32*)(void*)(&__IPSBAR[0x1D0548]))
+#define MCF_ETPU_EC21HSSR      (*(vuint32*)(void*)(&__IPSBAR[0x1D0558]))
+#define MCF_ETPU_EC22HSSR      (*(vuint32*)(void*)(&__IPSBAR[0x1D0568]))
+#define MCF_ETPU_EC23HSSR      (*(vuint32*)(void*)(&__IPSBAR[0x1D0578]))
+#define MCF_ETPU_EC24HSSR      (*(vuint32*)(void*)(&__IPSBAR[0x1D0588]))
+#define MCF_ETPU_EC25HSSR      (*(vuint32*)(void*)(&__IPSBAR[0x1D0598]))
+#define MCF_ETPU_EC26HSSR      (*(vuint32*)(void*)(&__IPSBAR[0x1D05A8]))
+#define MCF_ETPU_EC27HSSR      (*(vuint32*)(void*)(&__IPSBAR[0x1D05B8]))
+#define MCF_ETPU_EC28HSSR      (*(vuint32*)(void*)(&__IPSBAR[0x1D05C8]))
+#define MCF_ETPU_EC29HSSR      (*(vuint32*)(void*)(&__IPSBAR[0x1D05D8]))
+#define MCF_ETPU_EC30HSSR      (*(vuint32*)(void*)(&__IPSBAR[0x1D05E8]))
+#define MCF_ETPU_EC31HSSR      (*(vuint32*)(void*)(&__IPSBAR[0x1D05F8]))
+#define MCF_ETPU_ECnHSSR(x)    (*(vuint32*)(void*)(&__IPSBAR[0x1D0408+((x)*0x010)]))
+
+/* Bit definitions and macros for MCF_ETPU_EMCR */
+#define MCF_ETPU_EMCR_GTBE               (0x00000001)
+#define MCF_ETPU_EMCR_VIS                (0x00000040)
+#define MCF_ETPU_EMCR_SCMMISEN           (0x00000200)
+#define MCF_ETPU_EMCR_SCMMISF            (0x00000400)
+#define MCF_ETPU_EMCR_SCMSIZE(x)         (((x)&0x0000001F)<<16)
+#define MCF_ETPU_EMCR_ILF2               (0x01000000)
+#define MCF_ETPU_EMCR_ILF1               (0x02000000)
+#define MCF_ETPU_EMCR_MGE2               (0x04000000)
+#define MCF_ETPU_EMCR_MGE1               (0x08000000)
+#define MCF_ETPU_EMCR_GEC                (0x80000000)
+
+/* Bit definitions and macros for MCF_ETPU_ECDCR */
+#define MCF_ETPU_ECDCR_PARM1(x)          (((x)&0x0000007F)<<0)
+#define MCF_ETPU_ECDCR_WR                (0x00000080)
+#define MCF_ETPU_ECDCR_PARM0(x)          (((x)&0x0000007F)<<8)
+#define MCF_ETPU_ECDCR_PWIDTH            (0x00008000)
+#define MCF_ETPU_ECDCR_PBASE(x)          (((x)&0x000003FF)<<16)
+#define MCF_ETPU_ECDCR_CTBASE(x)         (((x)&0x0000001F)<<26)
+#define MCF_ETPU_ECDCR_STS               (0x80000000)
+
+/* Bit definitions and macros for MCF_ETPU_EECR */
+#define MCF_ETPU_EECR_ETB(x)             (((x)&0x0000001F)<<0)
+#define MCF_ETPU_EECR_CDFC(x)            (((x)&0x00000003)<<14)
+#define MCF_ETPU_EECR_FPSK(x)            (((x)&0x00000007)<<16)
+#define MCF_ETPU_EECR_HLTF               (0x00800000)
+#define MCF_ETPU_EECR_STF                (0x10000000)
+#define MCF_ETPU_EECR_MDIS               (0x40000000)
+#define MCF_ETPU_EECR_FEND               (0x80000000)
+
+/* Bit definitions and macros for MCF_ETPU_ETBCR */
+#define MCF_ETPU_ETBCR_TCR1P(x)          (((x)&0x000000FF)<<0)
+#define MCF_ETPU_ETBCR_TCR1CTL(x)        (((x)&0x00000003)<<14)
+#define MCF_ETPU_ETBCR_TCR2P(x)          (((x)&0x0000003F)<<16)
+#define MCF_ETPU_ETBCR_AM                (0x02000000)
+#define MCF_ETPU_ETBCR_TCRCF(x)          (((x)&0x00000003)<<27)
+#define MCF_ETPU_ETBCR_TCR2CTL(x)        (((x)&0x00000007)<<29)
+
+/* Bit definitions and macros for MCF_ETPU_ETB1R */
+#define MCF_ETPU_ETB1R_TCR1(x)           (((x)&0x00FFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_ETPU_ETB2R */
+#define MCF_ETPU_ETB2R_TCR2(x)           (((x)&0x00FFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_ETPU_EREDCR */
+#define MCF_ETPU_EREDCR_SRV2(x)          (((x)&0x0000000F)<<0)
+#define MCF_ETPU_EREDCR_SERVER_ID2(x)    (((x)&0x0000000F)<<8)
+#define MCF_ETPU_EREDCR_RSC2             (0x00004000)
+#define MCF_ETPU_EREDCR_REN2             (0x00008000)
+#define MCF_ETPU_EREDCR_SRV1(x)          (((x)&0x0000000F)<<16)
+#define MCF_ETPU_EREDCR_SERVER_ID1(x)    (((x)&0x0000000F)<<24)
+#define MCF_ETPU_EREDCR_RSC1             (0x40000000)
+#define MCF_ETPU_EREDCR_REN1             (0x80000000)
+
+/* Bit definitions and macros for MCF_ETPU_ECISR */
+#define MCF_ETPU_ECISR_CIS0              (0x00000001)
+#define MCF_ETPU_ECISR_CIS1              (0x00000002)
+#define MCF_ETPU_ECISR_CIS2              (0x00000004)
+#define MCF_ETPU_ECISR_CIS3              (0x00000008)
+#define MCF_ETPU_ECISR_CIS4              (0x00000010)
+#define MCF_ETPU_ECISR_CIS5              (0x00000020)
+#define MCF_ETPU_ECISR_CIS6              (0x00000040)
+#define MCF_ETPU_ECISR_CIS7              (0x00000080)
+#define MCF_ETPU_ECISR_CIS8              (0x00000100)
+#define MCF_ETPU_ECISR_CIS9              (0x00000200)
+#define MCF_ETPU_ECISR_CIS10             (0x00000400)
+#define MCF_ETPU_ECISR_CIS11             (0x00000800)
+#define MCF_ETPU_ECISR_CIS12             (0x00001000)
+#define MCF_ETPU_ECISR_CIS13             (0x00002000)
+#define MCF_ETPU_ECISR_CIS14             (0x00004000)
+#define MCF_ETPU_ECISR_CIS15             (0x00008000)
+#define MCF_ETPU_ECISR_CIS16             (0x00010000)
+#define MCF_ETPU_ECISR_CIS17             (0x00020000)
+#define MCF_ETPU_ECISR_CIS18             (0x00040000)
+#define MCF_ETPU_ECISR_CIS19             (0x00080000)
+#define MCF_ETPU_ECISR_CIS20             (0x00100000)
+#define MCF_ETPU_ECISR_CIS21             (0x00200000)
+#define MCF_ETPU_ECISR_CIS22             (0x00400000)
+#define MCF_ETPU_ECISR_CIS23             (0x00800000)
+#define MCF_ETPU_ECISR_CIS24             (0x01000000)
+#define MCF_ETPU_ECISR_CIS25             (0x02000000)
+#define MCF_ETPU_ECISR_CIS26             (0x04000000)
+#define MCF_ETPU_ECISR_CIS27             (0x08000000)
+#define MCF_ETPU_ECISR_CIS28             (0x10000000)
+#define MCF_ETPU_ECISR_CIS29             (0x20000000)
+#define MCF_ETPU_ECISR_CIS30             (0x40000000)
+#define MCF_ETPU_ECISR_CIS31             (0x80000000)
+
+/* Bit definitions and macros for MCF_ETPU_ECDTRSR */
+#define MCF_ETPU_ECDTRSR_DTRS0           (0x00000001)
+#define MCF_ETPU_ECDTRSR_DTRS1           (0x00000002)
+#define MCF_ETPU_ECDTRSR_DTRS2           (0x00000004)
+#define MCF_ETPU_ECDTRSR_DTRS3           (0x00000008)
+#define MCF_ETPU_ECDTRSR_DTRS4           (0x00000010)
+#define MCF_ETPU_ECDTRSR_DTRS5           (0x00000020)
+#define MCF_ETPU_ECDTRSR_DTRS6           (0x00000040)
+#define MCF_ETPU_ECDTRSR_DTRS7           (0x00000080)
+#define MCF_ETPU_ECDTRSR_DTRS8           (0x00000100)
+#define MCF_ETPU_ECDTRSR_DTRS9           (0x00000200)
+#define MCF_ETPU_ECDTRSR_DTRS10          (0x00000400)
+#define MCF_ETPU_ECDTRSR_DTRS11          (0x00000800)
+#define MCF_ETPU_ECDTRSR_DTRS12          (0x00001000)
+#define MCF_ETPU_ECDTRSR_DTRS13          (0x00002000)
+#define MCF_ETPU_ECDTRSR_DTRS14          (0x00004000)
+#define MCF_ETPU_ECDTRSR_DTRS15          (0x00008000)
+#define MCF_ETPU_ECDTRSR_DTRS16          (0x00010000)
+#define MCF_ETPU_ECDTRSR_DTRS17          (0x00020000)
+#define MCF_ETPU_ECDTRSR_DTRS18          (0x00040000)
+#define MCF_ETPU_ECDTRSR_DTRS19          (0x00080000)
+#define MCF_ETPU_ECDTRSR_DTRS20          (0x00100000)
+#define MCF_ETPU_ECDTRSR_DTRS21          (0x00200000)
+#define MCF_ETPU_ECDTRSR_DTRS22          (0x00400000)
+#define MCF_ETPU_ECDTRSR_DTRS23          (0x00800000)
+#define MCF_ETPU_ECDTRSR_DTRS24          (0x01000000)
+#define MCF_ETPU_ECDTRSR_DTRS25          (0x02000000)
+#define MCF_ETPU_ECDTRSR_DTRS26          (0x04000000)
+#define MCF_ETPU_ECDTRSR_DTRS27          (0x08000000)
+#define MCF_ETPU_ECDTRSR_DTRS28          (0x10000000)
+#define MCF_ETPU_ECDTRSR_DTRS29          (0x20000000)
+#define MCF_ETPU_ECDTRSR_DTRS30          (0x40000000)
+#define MCF_ETPU_ECDTRSR_DTRS31          (0x80000000)
+
+/* Bit definitions and macros for MCF_ETPU_ECIOSR */
+#define MCF_ETPU_ECIOSR_CIOS0            (0x00000001)
+#define MCF_ETPU_ECIOSR_CIOS1            (0x00000002)
+#define MCF_ETPU_ECIOSR_CIOS2            (0x00000004)
+#define MCF_ETPU_ECIOSR_CIOS3            (0x00000008)
+#define MCF_ETPU_ECIOSR_CIOS4            (0x00000010)
+#define MCF_ETPU_ECIOSR_CIOS5            (0x00000020)
+#define MCF_ETPU_ECIOSR_CIOS6            (0x00000040)
+#define MCF_ETPU_ECIOSR_CIOS7            (0x00000080)
+#define MCF_ETPU_ECIOSR_CIOS8            (0x00000100)
+#define MCF_ETPU_ECIOSR_CIOS9            (0x00000200)
+#define MCF_ETPU_ECIOSR_CIOS10           (0x00000400)
+#define MCF_ETPU_ECIOSR_CIOS11           (0x00000800)
+#define MCF_ETPU_ECIOSR_CIOS12           (0x00001000)
+#define MCF_ETPU_ECIOSR_CIOS13           (0x00002000)
+#define MCF_ETPU_ECIOSR_CIOS14           (0x00004000)
+#define MCF_ETPU_ECIOSR_CIOS15           (0x00008000)
+#define MCF_ETPU_ECIOSR_CIOS16           (0x00010000)
+#define MCF_ETPU_ECIOSR_CIOS17           (0x00020000)
+#define MCF_ETPU_ECIOSR_CIOS18           (0x00040000)
+#define MCF_ETPU_ECIOSR_CIOS19           (0x00080000)
+#define MCF_ETPU_ECIOSR_CIOS20           (0x00100000)
+#define MCF_ETPU_ECIOSR_CIOS21           (0x00200000)
+#define MCF_ETPU_ECIOSR_CIOS22           (0x00400000)
+#define MCF_ETPU_ECIOSR_CIOS23           (0x00800000)
+#define MCF_ETPU_ECIOSR_CIOS24           (0x01000000)
+#define MCF_ETPU_ECIOSR_CIOS25           (0x02000000)
+#define MCF_ETPU_ECIOSR_CIOS26           (0x04000000)
+#define MCF_ETPU_ECIOSR_CIOS27           (0x08000000)
+#define MCF_ETPU_ECIOSR_CIOS28           (0x10000000)
+#define MCF_ETPU_ECIOSR_CIOS29           (0x20000000)
+#define MCF_ETPU_ECIOSR_CIOS30           (0x40000000)
+#define MCF_ETPU_ECIOSR_CIOS31           (0x80000000)
+
+/* Bit definitions and macros for MCF_ETPU_ECDTROSR */
+#define MCF_ETPU_ECDTROSR_DTROS0         (0x00000001)
+#define MCF_ETPU_ECDTROSR_DTROS1         (0x00000002)
+#define MCF_ETPU_ECDTROSR_DTROS2         (0x00000004)
+#define MCF_ETPU_ECDTROSR_DTROS3         (0x00000008)
+#define MCF_ETPU_ECDTROSR_DTROS4         (0x00000010)
+#define MCF_ETPU_ECDTROSR_DTROS5         (0x00000020)
+#define MCF_ETPU_ECDTROSR_DTROS6         (0x00000040)
+#define MCF_ETPU_ECDTROSR_DTROS7         (0x00000080)
+#define MCF_ETPU_ECDTROSR_DTROS8         (0x00000100)
+#define MCF_ETPU_ECDTROSR_DTROS9         (0x00000200)
+#define MCF_ETPU_ECDTROSR_DTROS10        (0x00000400)
+#define MCF_ETPU_ECDTROSR_DTROS11        (0x00000800)
+#define MCF_ETPU_ECDTROSR_DTROS12        (0x00001000)
+#define MCF_ETPU_ECDTROSR_DTROS13        (0x00002000)
+#define MCF_ETPU_ECDTROSR_DTROS14        (0x00004000)
+#define MCF_ETPU_ECDTROSR_DTROS15        (0x00008000)
+#define MCF_ETPU_ECDTROSR_DTROS16        (0x00010000)
+#define MCF_ETPU_ECDTROSR_DTROS17        (0x00020000)
+#define MCF_ETPU_ECDTROSR_DTROS18        (0x00040000)
+#define MCF_ETPU_ECDTROSR_DTROS19        (0x00080000)
+#define MCF_ETPU_ECDTROSR_DTROS20        (0x00100000)
+#define MCF_ETPU_ECDTROSR_DTROS21        (0x00200000)
+#define MCF_ETPU_ECDTROSR_DTROS22        (0x00400000)
+#define MCF_ETPU_ECDTROSR_DTROS23        (0x00800000)
+#define MCF_ETPU_ECDTROSR_DTROS24        (0x01000000)
+#define MCF_ETPU_ECDTROSR_DTROS25        (0x02000000)
+#define MCF_ETPU_ECDTROSR_DTROS26        (0x04000000)
+#define MCF_ETPU_ECDTROSR_DTROS27        (0x08000000)
+#define MCF_ETPU_ECDTROSR_DTROS28        (0x10000000)
+#define MCF_ETPU_ECDTROSR_DTROS29        (0x20000000)
+#define MCF_ETPU_ECDTROSR_DTROS30        (0x40000000)
+#define MCF_ETPU_ECDTROSR_DTROS31        (0x80000000)
+
+/* Bit definitions and macros for MCF_ETPU_ECIER */
+#define MCF_ETPU_ECIER_CIE0              (0x00000001)
+#define MCF_ETPU_ECIER_CIE1              (0x00000002)
+#define MCF_ETPU_ECIER_CIE2              (0x00000004)
+#define MCF_ETPU_ECIER_CIE3              (0x00000008)
+#define MCF_ETPU_ECIER_CIE4              (0x00000010)
+#define MCF_ETPU_ECIER_CIE5              (0x00000020)
+#define MCF_ETPU_ECIER_CIE6              (0x00000040)
+#define MCF_ETPU_ECIER_CIE7              (0x00000080)
+#define MCF_ETPU_ECIER_CIE8              (0x00000100)
+#define MCF_ETPU_ECIER_CIE9              (0x00000200)
+#define MCF_ETPU_ECIER_CIE10             (0x00000400)
+#define MCF_ETPU_ECIER_CIE11             (0x00000800)
+#define MCF_ETPU_ECIER_CIE12             (0x00001000)
+#define MCF_ETPU_ECIER_CIE13             (0x00002000)
+#define MCF_ETPU_ECIER_CIE14             (0x00004000)
+#define MCF_ETPU_ECIER_CIE15             (0x00008000)
+#define MCF_ETPU_ECIER_CIE16             (0x00010000)
+#define MCF_ETPU_ECIER_CIE17             (0x00020000)
+#define MCF_ETPU_ECIER_CIE18             (0x00040000)
+#define MCF_ETPU_ECIER_CIE19             (0x00080000)
+#define MCF_ETPU_ECIER_CIE20             (0x00100000)
+#define MCF_ETPU_ECIER_CIE21             (0x00200000)
+#define MCF_ETPU_ECIER_CIE22             (0x00400000)
+#define MCF_ETPU_ECIER_CIE23             (0x00800000)
+#define MCF_ETPU_ECIER_CIE24             (0x01000000)
+#define MCF_ETPU_ECIER_CIE25             (0x02000000)
+#define MCF_ETPU_ECIER_CIE26             (0x04000000)
+#define MCF_ETPU_ECIER_CIE27             (0x08000000)
+#define MCF_ETPU_ECIER_CIE28             (0x10000000)
+#define MCF_ETPU_ECIER_CIE29             (0x20000000)
+#define MCF_ETPU_ECIER_CIE30             (0x40000000)
+#define MCF_ETPU_ECIER_CIE31             (0x80000000)
+
+/* Bit definitions and macros for MCF_ETPU_ECDTRER */
+#define MCF_ETPU_ECDTRER_DTRE0           (0x00000001)
+#define MCF_ETPU_ECDTRER_DTRE1           (0x00000002)
+#define MCF_ETPU_ECDTRER_DTRE2           (0x00000004)
+#define MCF_ETPU_ECDTRER_DTRE3           (0x00000008)
+#define MCF_ETPU_ECDTRER_DTRE4           (0x00000010)
+#define MCF_ETPU_ECDTRER_DTRE5           (0x00000020)
+#define MCF_ETPU_ECDTRER_DTRE6           (0x00000040)
+#define MCF_ETPU_ECDTRER_DTRE7           (0x00000080)
+#define MCF_ETPU_ECDTRER_DTRE8           (0x00000100)
+#define MCF_ETPU_ECDTRER_DTRE9           (0x00000200)
+#define MCF_ETPU_ECDTRER_DTRE10          (0x00000400)
+#define MCF_ETPU_ECDTRER_DTRE11          (0x00000800)
+#define MCF_ETPU_ECDTRER_DTRE12          (0x00001000)
+#define MCF_ETPU_ECDTRER_DTRE13          (0x00002000)
+#define MCF_ETPU_ECDTRER_DTRE14          (0x00004000)
+#define MCF_ETPU_ECDTRER_DTRE15          (0x00008000)
+#define MCF_ETPU_ECDTRER_DTRE16          (0x00010000)
+#define MCF_ETPU_ECDTRER_DTRE17          (0x00020000)
+#define MCF_ETPU_ECDTRER_DTRE18          (0x00040000)
+#define MCF_ETPU_ECDTRER_DTRE19          (0x00080000)
+#define MCF_ETPU_ECDTRER_DTRE20          (0x00100000)
+#define MCF_ETPU_ECDTRER_DTRE21          (0x00200000)
+#define MCF_ETPU_ECDTRER_DTRE22          (0x00400000)
+#define MCF_ETPU_ECDTRER_DTRE23          (0x00800000)
+#define MCF_ETPU_ECDTRER_DTRE24          (0x01000000)
+#define MCF_ETPU_ECDTRER_DTRE25          (0x02000000)
+#define MCF_ETPU_ECDTRER_DTRE26          (0x04000000)
+#define MCF_ETPU_ECDTRER_DTRE27          (0x08000000)
+#define MCF_ETPU_ECDTRER_DTRE28          (0x10000000)
+#define MCF_ETPU_ECDTRER_DTRE29          (0x20000000)
+#define MCF_ETPU_ECDTRER_DTRE30          (0x40000000)
+#define MCF_ETPU_ECDTRER_DTRE31          (0x80000000)
+
+/* Bit definitions and macros for MCF_ETPU_ECPSSR */
+#define MCF_ETPU_ECPSSR_SR0              (0x00000001)
+#define MCF_ETPU_ECPSSR_SR1              (0x00000002)
+#define MCF_ETPU_ECPSSR_SR2              (0x00000004)
+#define MCF_ETPU_ECPSSR_SR3              (0x00000008)
+#define MCF_ETPU_ECPSSR_SR4              (0x00000010)
+#define MCF_ETPU_ECPSSR_SR5              (0x00000020)
+#define MCF_ETPU_ECPSSR_SR6              (0x00000040)
+#define MCF_ETPU_ECPSSR_SR7              (0x00000080)
+#define MCF_ETPU_ECPSSR_SR8              (0x00000100)
+#define MCF_ETPU_ECPSSR_SR9              (0x00000200)
+#define MCF_ETPU_ECPSSR_SR10             (0x00000400)
+#define MCF_ETPU_ECPSSR_SR11             (0x00000800)
+#define MCF_ETPU_ECPSSR_SR12             (0x00001000)
+#define MCF_ETPU_ECPSSR_SR13             (0x00002000)
+#define MCF_ETPU_ECPSSR_SR14             (0x00004000)
+#define MCF_ETPU_ECPSSR_SR15             (0x00008000)
+#define MCF_ETPU_ECPSSR_SR16             (0x00010000)
+#define MCF_ETPU_ECPSSR_SR17             (0x00020000)
+#define MCF_ETPU_ECPSSR_SR18             (0x00040000)
+#define MCF_ETPU_ECPSSR_SR19             (0x00080000)
+#define MCF_ETPU_ECPSSR_SR20             (0x00100000)
+#define MCF_ETPU_ECPSSR_SR21             (0x00200000)
+#define MCF_ETPU_ECPSSR_SR22             (0x00400000)
+#define MCF_ETPU_ECPSSR_SR23             (0x00800000)
+#define MCF_ETPU_ECPSSR_SR24             (0x01000000)
+#define MCF_ETPU_ECPSSR_SR25             (0x02000000)
+#define MCF_ETPU_ECPSSR_SR26             (0x04000000)
+#define MCF_ETPU_ECPSSR_SR27             (0x08000000)
+#define MCF_ETPU_ECPSSR_SR28             (0x10000000)
+#define MCF_ETPU_ECPSSR_SR29             (0x20000000)
+#define MCF_ETPU_ECPSSR_SR30             (0x40000000)
+#define MCF_ETPU_ECPSSR_SR31             (0x80000000)
+
+/* Bit definitions and macros for MCF_ETPU_ECSSR */
+#define MCF_ETPU_ECSSR_SS0               (0x00000001)
+#define MCF_ETPU_ECSSR_SS1               (0x00000002)
+#define MCF_ETPU_ECSSR_SS2               (0x00000004)
+#define MCF_ETPU_ECSSR_SS3               (0x00000008)
+#define MCF_ETPU_ECSSR_SS4               (0x00000010)
+#define MCF_ETPU_ECSSR_SS5               (0x00000020)
+#define MCF_ETPU_ECSSR_SS6               (0x00000040)
+#define MCF_ETPU_ECSSR_SS7               (0x00000080)
+#define MCF_ETPU_ECSSR_SS8               (0x00000100)
+#define MCF_ETPU_ECSSR_SS9               (0x00000200)
+#define MCF_ETPU_ECSSR_SS10              (0x00000400)
+#define MCF_ETPU_ECSSR_SS11              (0x00000800)
+#define MCF_ETPU_ECSSR_SS12              (0x00001000)
+#define MCF_ETPU_ECSSR_SS13              (0x00002000)
+#define MCF_ETPU_ECSSR_SS14              (0x00004000)
+#define MCF_ETPU_ECSSR_SS15              (0x00008000)
+#define MCF_ETPU_ECSSR_SS16              (0x00010000)
+#define MCF_ETPU_ECSSR_SS17              (0x00020000)
+#define MCF_ETPU_ECSSR_SS18              (0x00040000)
+#define MCF_ETPU_ECSSR_SS19              (0x00080000)
+#define MCF_ETPU_ECSSR_SS20              (0x00100000)
+#define MCF_ETPU_ECSSR_SS21              (0x00200000)
+#define MCF_ETPU_ECSSR_SS22              (0x00400000)
+#define MCF_ETPU_ECSSR_SS23              (0x00800000)
+#define MCF_ETPU_ECSSR_SS24              (0x01000000)
+#define MCF_ETPU_ECSSR_SS25              (0x02000000)
+#define MCF_ETPU_ECSSR_SS26              (0x04000000)
+#define MCF_ETPU_ECSSR_SS27              (0x08000000)
+#define MCF_ETPU_ECSSR_SS28              (0x10000000)
+#define MCF_ETPU_ECSSR_SS29              (0x20000000)
+#define MCF_ETPU_ECSSR_SS30              (0x40000000)
+#define MCF_ETPU_ECSSR_SS31              (0x80000000)
+
+/* Bit definitions and macros for MCF_ETPU_ECnSCR */
+#define MCF_ETPU_ECnSCR_FM(x)            (((x)&0x00000003)<<0)
+#define MCF_ETPU_ECnSCR_OBE              (0x00002000)
+#define MCF_ETPU_ECnSCR_OPS              (0x00004000)
+#define MCF_ETPU_ECnSCR_IPS              (0x00008000)
+#define MCF_ETPU_ECnSCR_DTROS            (0x00400000)
+#define MCF_ETPU_ECnSCR_DTRS             (0x00800000)
+#define MCF_ETPU_ECnSCR_CIOS             (0x40000000)
+#define MCF_ETPU_ECnSCR_CIS              (0x80000000)
+
+/* Bit definitions and macros for MCF_ETPU_ECnCR */
+#define MCF_ETPU_ECnCR_CPBA(x)           (((x)&0x000007FF)<<0)
+#define MCF_ETPU_ECnCR_OPOL              (0x00004000)
+#define MCF_ETPU_ECnCR_ODIS              (0x00008000)
+#define MCF_ETPU_ECnCR_CFS(x)            (((x)&0x0000001F)<<16)
+#define MCF_ETPU_ECnCR_ETCS              (0x01000000)
+#define MCF_ETPU_ECnCR_CPR(x)            (((x)&0x00000003)<<28)
+#define MCF_ETPU_ECnCR_DTRE              (0x40000000)
+#define MCF_ETPU_ECnCR_CIE               (0x80000000)
+
+/* Bit definitions and macros for MCF_ETPU_ECnHSSR */
+#define MCF_ETPU_ECnHSSR_HSR(x)          (((x)&0x00000007)<<0)
+
+/********************************************************************/
+
+#endif /* __MCF523X_ETPU_H__ */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_fec.h b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_fec.h
new file mode 100644
index 000000000..a4a209d50
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_fec.h
@@ -0,0 +1,208 @@
+/*
+ * These files are taken from the MCF523X source code example package
+ * which is available on the Freescale website. Freescale explicitly 
+ * grants the redistribution and modification of these source files.
+ * The complete licensing information is available in the file 
+ * LICENSE_FREESCALE.TXT.
+ *
+ * File:	mcf523x_fec.h
+ * Purpose:	Register and bit definitions for the MCF523X
+ *
+ * Notes:	
+ *	
+ */
+
+#ifndef __MCF523X_FEC_H__
+#define __MCF523X_FEC_H__
+
+/*********************************************************************
+*
+* Fast Ethernet Controller (FEC)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_FEC_EIR                   (*(vuint32*)(void*)(&__IPSBAR[0x001004]))
+#define MCF_FEC_EIMR                  (*(vuint32*)(void*)(&__IPSBAR[0x001008]))
+#define MCF_FEC_RDAR                  (*(vuint32*)(void*)(&__IPSBAR[0x001010]))
+#define MCF_FEC_TDAR                  (*(vuint32*)(void*)(&__IPSBAR[0x001014]))
+#define MCF_FEC_ECR                   (*(vuint32*)(void*)(&__IPSBAR[0x001024]))
+#define MCF_FEC_MMFR                  (*(vuint32*)(void*)(&__IPSBAR[0x001040]))
+#define MCF_FEC_MSCR                  (*(vuint32*)(void*)(&__IPSBAR[0x001044]))
+#define MCF_FEC_MIBC                  (*(vuint32*)(void*)(&__IPSBAR[0x001064]))
+#define MCF_FEC_RCR                   (*(vuint32*)(void*)(&__IPSBAR[0x001084]))
+#define MCF_FEC_TCR                   (*(vuint32*)(void*)(&__IPSBAR[0x0010C4]))
+#define MCF_FEC_PALR                  (*(vuint32*)(void*)(&__IPSBAR[0x0010E4]))
+#define MCF_FEC_PAUR                  (*(vuint32*)(void*)(&__IPSBAR[0x0010E8]))
+#define MCF_FEC_OPD                   (*(vuint32*)(void*)(&__IPSBAR[0x0010EC]))
+#define MCF_FEC_IAUR                  (*(vuint32*)(void*)(&__IPSBAR[0x001118]))
+#define MCF_FEC_IALR                  (*(vuint32*)(void*)(&__IPSBAR[0x00111C]))
+#define MCF_FEC_GAUR                  (*(vuint32*)(void*)(&__IPSBAR[0x001120]))
+#define MCF_FEC_GALR                  (*(vuint32*)(void*)(&__IPSBAR[0x001124]))
+#define MCF_FEC_TFWR                  (*(vuint32*)(void*)(&__IPSBAR[0x001144]))
+#define MCF_FEC_FRBR                  (*(vuint32*)(void*)(&__IPSBAR[0x00114C]))
+#define MCF_FEC_FRSR                  (*(vuint32*)(void*)(&__IPSBAR[0x001150]))
+#define MCF_FEC_ERDSR                 (*(vuint32*)(void*)(&__IPSBAR[0x001180]))
+#define MCF_FEC_ETDSR                 (*(vuint32*)(void*)(&__IPSBAR[0x001184]))
+#define MCF_FEC_EMRBR                 (*(vuint32*)(void*)(&__IPSBAR[0x001188]))
+#define MCF_FEC_RMON_T_DROP           (*(vuint32*)(void*)(&__IPSBAR[0x001200]))
+#define MCF_FEC_RMON_T_PACKETS        (*(vuint32*)(void*)(&__IPSBAR[0x001204]))
+#define MCF_FEC_RMON_T_BC_PKT         (*(vuint32*)(void*)(&__IPSBAR[0x001208]))
+#define MCF_FEC_RMON_T_MC_PKT         (*(vuint32*)(void*)(&__IPSBAR[0x00120C]))
+#define MCF_FEC_RMON_T_CRC_ALIGN      (*(vuint32*)(void*)(&__IPSBAR[0x001210]))
+#define MCF_FEC_RMON_T_UNDERSIZE      (*(vuint32*)(void*)(&__IPSBAR[0x001214]))
+#define MCF_FEC_RMON_T_OVERSIZE       (*(vuint32*)(void*)(&__IPSBAR[0x001218]))
+#define MCF_FEC_RMON_T_FRAG           (*(vuint32*)(void*)(&__IPSBAR[0x00121C]))
+#define MCF_FEC_RMON_T_JAB            (*(vuint32*)(void*)(&__IPSBAR[0x001220]))
+#define MCF_FEC_RMON_T_COL            (*(vuint32*)(void*)(&__IPSBAR[0x001224]))
+#define MCF_FEC_RMON_T_P64            (*(vuint32*)(void*)(&__IPSBAR[0x001228]))
+#define MCF_FEC_RMON_T_P65TO127       (*(vuint32*)(void*)(&__IPSBAR[0x00122C]))
+#define MCF_FEC_RMON_T_P128TO255      (*(vuint32*)(void*)(&__IPSBAR[0x001230]))
+#define MCF_FEC_RMON_T_P256TO511      (*(vuint32*)(void*)(&__IPSBAR[0x001234]))
+#define MCF_FEC_RMON_T_P512TO1023     (*(vuint32*)(void*)(&__IPSBAR[0x001238]))
+#define MCF_FEC_RMON_T_P1024TO2047    (*(vuint32*)(void*)(&__IPSBAR[0x00123C]))
+#define MCF_FEC_RMON_T_P_GTE2048      (*(vuint32*)(void*)(&__IPSBAR[0x001240]))
+#define MCF_FEC_RMON_T_OCTETS         (*(vuint32*)(void*)(&__IPSBAR[0x001244]))
+#define MCF_FEC_IEEE_T_DROP           (*(vuint32*)(void*)(&__IPSBAR[0x001248]))
+#define MCF_FEC_IEEE_T_FRAME_OK       (*(vuint32*)(void*)(&__IPSBAR[0x00124C]))
+#define MCF_FEC_IEEE_T_1COL           (*(vuint32*)(void*)(&__IPSBAR[0x001250]))
+#define MCF_FEC_IEEE_T_MCOL           (*(vuint32*)(void*)(&__IPSBAR[0x001254]))
+#define MCF_FEC_IEEE_T_DEF            (*(vuint32*)(void*)(&__IPSBAR[0x001258]))
+#define MCF_FEC_IEEE_T_LCOL           (*(vuint32*)(void*)(&__IPSBAR[0x00125C]))
+#define MCF_FEC_IEEE_T_EXCOL          (*(vuint32*)(void*)(&__IPSBAR[0x001260]))
+#define MCF_FEC_IEEE_T_MACERR         (*(vuint32*)(void*)(&__IPSBAR[0x001264]))
+#define MCF_FEC_IEEE_T_CSERR          (*(vuint32*)(void*)(&__IPSBAR[0x001268]))
+#define MCF_FEC_IEEE_T_SQE            (*(vuint32*)(void*)(&__IPSBAR[0x00126C]))
+#define MCF_FEC_IEEE_T_FDXFC          (*(vuint32*)(void*)(&__IPSBAR[0x001270]))
+#define MCF_FEC_IEEE_T_OCTETS_OK      (*(vuint32*)(void*)(&__IPSBAR[0x001274]))
+#define MCF_FEC_RMON_R_PACKETS        (*(vuint32*)(void*)(&__IPSBAR[0x001284]))
+#define MCF_FEC_RMON_R_BC_PKT         (*(vuint32*)(void*)(&__IPSBAR[0x001288]))
+#define MCF_FEC_RMON_R_MC_PKT         (*(vuint32*)(void*)(&__IPSBAR[0x00128C]))
+#define MCF_FEC_RMON_R_CRC_ALIGN      (*(vuint32*)(void*)(&__IPSBAR[0x001290]))
+#define MCF_FEC_RMON_R_UNDERSIZE      (*(vuint32*)(void*)(&__IPSBAR[0x001294]))
+#define MCF_FEC_RMON_R_OVERSIZE       (*(vuint32*)(void*)(&__IPSBAR[0x001298]))
+#define MCF_FEC_RMON_R_FRAG           (*(vuint32*)(void*)(&__IPSBAR[0x00129C]))
+#define MCF_FEC_RMON_R_JAB            (*(vuint32*)(void*)(&__IPSBAR[0x0012A0]))
+#define MCF_FEC_RMON_R_RESVD_0        (*(vuint32*)(void*)(&__IPSBAR[0x0012A4]))
+#define MCF_FEC_RMON_R_P64            (*(vuint32*)(void*)(&__IPSBAR[0x0012A8]))
+#define MCF_FEC_RMON_R_P65TO127       (*(vuint32*)(void*)(&__IPSBAR[0x0012AC]))
+#define MCF_FEC_RMON_R_P128TO255      (*(vuint32*)(void*)(&__IPSBAR[0x0012B0]))
+#define MCF_FEC_RMON_R_P256TO511      (*(vuint32*)(void*)(&__IPSBAR[0x0012B4]))
+#define MCF_FEC_RMON_R_512TO1023      (*(vuint32*)(void*)(&__IPSBAR[0x0012B8]))
+#define MCF_FEC_RMON_R_P_GTE2048      (*(vuint32*)(void*)(&__IPSBAR[0x0012C0]))
+#define MCF_FEC_RMON_R_1024TO2047     (*(vuint32*)(void*)(&__IPSBAR[0x0012BC]))
+#define MCF_FEC_RMON_R_OCTETS         (*(vuint32*)(void*)(&__IPSBAR[0x0012C4]))
+#define MCF_FEC_IEEE_R_DROP           (*(vuint32*)(void*)(&__IPSBAR[0x0012C8]))
+#define MCF_FEC_IEEE_R_FRAME_OK       (*(vuint32*)(void*)(&__IPSBAR[0x0012CC]))
+#define MCF_FEC_IEEE_R_CRC            (*(vuint32*)(void*)(&__IPSBAR[0x0012D0]))
+#define MCF_FEC_IEEE_R_ALIGN          (*(vuint32*)(void*)(&__IPSBAR[0x0012D4]))
+#define MCF_FEC_IEEE_R_MACERR         (*(vuint32*)(void*)(&__IPSBAR[0x0012D8]))
+#define MCF_FEC_IEEE_R_FDXFC          (*(vuint32*)(void*)(&__IPSBAR[0x0012DC]))
+#define MCF_FEC_IEEE_R_OCTETS_OK      (*(vuint32*)(void*)(&__IPSBAR[0x0012E0]))
+
+/* Bit definitions and macros for MCF_FEC_EIR */
+#define MCF_FEC_EIR_UN                  (0x00080000)
+#define MCF_FEC_EIR_RL                  (0x00100000)
+#define MCF_FEC_EIR_LC                  (0x00200000)
+#define MCF_FEC_EIR_EBERR               (0x00400000)
+#define MCF_FEC_EIR_MII                 (0x00800000)
+#define MCF_FEC_EIR_RXB                 (0x01000000)
+#define MCF_FEC_EIR_RXF                 (0x02000000)
+#define MCF_FEC_EIR_TXB                 (0x04000000)
+#define MCF_FEC_EIR_TXF                 (0x08000000)
+#define MCF_FEC_EIR_GRA                 (0x10000000)
+#define MCF_FEC_EIR_BABT                (0x20000000)
+#define MCF_FEC_EIR_BABR                (0x40000000)
+#define MCF_FEC_EIR_HBERR               (0x80000000)
+
+/* Bit definitions and macros for MCF_FEC_EIMR */
+#define MCF_FEC_EIMR_UN                 (0x00080000)
+#define MCF_FEC_EIMR_RL                 (0x00100000)
+#define MCF_FEC_EIMR_LC                 (0x00200000)
+#define MCF_FEC_EIMR_EBERR              (0x00400000)
+#define MCF_FEC_EIMR_MII                (0x00800000)
+#define MCF_FEC_EIMR_RXB                (0x01000000)
+#define MCF_FEC_EIMR_RXF                (0x02000000)
+#define MCF_FEC_EIMR_TXB                (0x04000000)
+#define MCF_FEC_EIMR_TXF                (0x08000000)
+#define MCF_FEC_EIMR_GRA                (0x10000000)
+#define MCF_FEC_EIMR_BABT               (0x20000000)
+#define MCF_FEC_EIMR_BABR               (0x40000000)
+#define MCF_FEC_EIMR_HBERR              (0x80000000)
+
+/* Bit definitions and macros for MCF_FEC_RDAR */
+#define MCF_FEC_RDAR_R_DES_ACTIVE       (0x01000000)
+
+/* Bit definitions and macros for MCF_FEC_TDAR */
+#define MCF_FEC_TDAR_X_DES_ACTIVE       (0x01000000)
+
+/* Bit definitions and macros for MCF_FEC_ECR */
+#define MCF_FEC_ECR_RESET               (0x00000001)
+#define MCF_FEC_ECR_ETHER_EN            (0x00000002)
+
+/* Bit definitions and macros for MCF_FEC_MMFR */
+#define MCF_FEC_MMFR_DATA(x)            (((x)&0x0000FFFF)<<0)
+#define MCF_FEC_MMFR_TA(x)              (((x)&0x00000003)<<16)
+#define MCF_FEC_MMFR_RA(x)              (((x)&0x0000001F)<<18)
+#define MCF_FEC_MMFR_PA(x)              (((x)&0x0000001F)<<23)
+#define MCF_FEC_MMFR_OP(x)              (((x)&0x00000003)<<28)
+#define MCF_FEC_MMFR_ST(x)              (((x)&0x00000003)<<30)
+#define MCF_FEC_MMFR_ST_01             (0x40000000)
+#define MCF_FEC_MMFR_OP_READ           (0x20000000)
+#define MCF_FEC_MMFR_OP_WRITE          (0x10000000)
+#define MCF_FEC_MMFR_TA_10             (0x00020000)
+
+
+/* Bit definitions and macros for MCF_FEC_MSCR */
+#define MCF_FEC_MSCR_MII_SPEED(x)       (((x)&0x0000003F)<<1)
+#define MCF_FEC_MSCR_DIS_PREAMBLE       (0x00000080)
+
+/* Bit definitions and macros for MCF_FEC_MIBC */
+#define MCF_FEC_MIBC_MIB_IDLE           (0x40000000)
+#define MCF_FEC_MIBC_MIB_DISABLE        (0x80000000)
+
+/* Bit definitions and macros for MCF_FEC_RCR */
+#define MCF_FEC_RCR_LOOP                (0x00000001)
+#define MCF_FEC_RCR_DRT                 (0x00000002)
+#define MCF_FEC_RCR_MII_MODE            (0x00000004)
+#define MCF_FEC_RCR_PROM                (0x00000008)
+#define MCF_FEC_RCR_BC_REJ              (0x00000010)
+#define MCF_FEC_RCR_FCE                 (0x00000020)
+#define MCF_FEC_RCR_MAX_FL(x)           (((x)&0x000007FF)<<16)
+
+/* Bit definitions and macros for MCF_FEC_TCR */
+#define MCF_FEC_TCR_GTS                 (0x00000001)
+#define MCF_FEC_TCR_HBC                 (0x00000002)
+#define MCF_FEC_TCR_FDEN                (0x00000004)
+#define MCF_FEC_TCR_TFC_PAUSE           (0x00000008)
+#define MCF_FEC_TCR_RFC_PAUSE           (0x00000010)
+
+/* Bit definitions and macros for MCF_FEC_PAUR */
+#define MCF_FEC_PAUR_TYPE(x)            (((x)&0x0000FFFF)<<0)
+#define MCF_FEC_PAUR_PADDR2(x)          (((x)&0x0000FFFF)<<16)
+
+/* Bit definitions and macros for MCF_FEC_OPD */
+#define MCF_FEC_OPD_PAUSE_DUR(x)        (((x)&0x0000FFFF)<<0)
+#define MCF_FEC_OPD_OPCODE(x)           (((x)&0x0000FFFF)<<16)
+
+/* Bit definitions and macros for MCF_FEC_TFWR */
+#define MCF_FEC_TFWR_X_WMRK(x)          (((x)&0x00000003)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FRBR */
+#define MCF_FEC_FRBR_R_BOUND(x)         (((x)&0x000000FF)<<2)
+
+/* Bit definitions and macros for MCF_FEC_FRSR */
+#define MCF_FEC_FRSR_R_FSTART(x)        (((x)&0x000000FF)<<2)
+
+/* Bit definitions and macros for MCF_FEC_ERDSR */
+#define MCF_FEC_ERDSR_R_DES_START(x)    (((x)&0x3FFFFFFF)<<2)
+
+/* Bit definitions and macros for MCF_FEC_ETDSR */
+#define MCF_FEC_ETDSR_X_DES_START(x)    (((x)&0x3FFFFFFF)<<2)
+
+/* Bit definitions and macros for MCF_FEC_EMRBR */
+#define MCF_FEC_EMRBR_R_BUF_SIZE(x)     (((x)&0x0000007F)<<4)
+
+/********************************************************************/
+
+#endif /* __MCF523X_FEC_H__ */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_fmpll.h b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_fmpll.h
new file mode 100644
index 000000000..3f132e896
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_fmpll.h
@@ -0,0 +1,55 @@
+/*
+ * These files are taken from the MCF523X source code example package
+ * which is available on the Freescale website. Freescale explicitly 
+ * grants the redistribution and modification of these source files.
+ * The complete licensing information is available in the file 
+ * LICENSE_FREESCALE.TXT.
+ *
+ * File:	mcf523x_fmpll.h
+ * Purpose:	Register and bit definitions for the MCF523X
+ *
+ * Notes:	
+ *	
+ */
+
+#ifndef __MCF523X_FMPLL_H__
+#define __MCF523X_FMPLL_H__
+
+/*********************************************************************
+*
+* Frequency Modulated Phase Locked Loop (FMPLL)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_FMPLL_SYNCR    (*(vuint32*)(void*)(&__IPSBAR[0x120000]))
+#define MCF_FMPLL_SYNSR    (*(vuint32*)(void*)(&__IPSBAR[0x120004]))
+
+/* Bit definitions and macros for MCF_FMPLL_SYNCR */
+#define MCF_FMPLL_SYNCR_EXP(x)       (((x)&0x000003FF)<<0)
+#define MCF_FMPLL_SYNCR_DEPTH(x)     (((x)&0x00000003)<<10)
+#define MCF_FMPLL_SYNCR_RATE         (0x00001000)
+#define MCF_FMPLL_SYNCR_LOCIRQ       (0x00002000)
+#define MCF_FMPLL_SYNCR_LOLIRQ       (0x00004000)
+#define MCF_FMPLL_SYNCR_DISCLK       (0x00008000)
+#define MCF_FMPLL_SYNCR_LOCRE        (0x00010000)
+#define MCF_FMPLL_SYNCR_LOLRE        (0x00020000)
+#define MCF_FMPLL_SYNCR_LOCEN        (0x00040000)
+#define MCF_FMPLL_SYNCR_RFD(x)       (((x)&0x00000007)<<19)
+#define MCF_FMPLL_SYNCR_MFD(x)       (((x)&0x00000007)<<24)
+
+/* Bit definitions and macros for MCF_FMPLL_SYNSR */
+#define MCF_FMPLL_SYNSR_CALPASS      (0x00000001)
+#define MCF_FMPLL_SYNSR_CALDONE      (0x00000002)
+#define MCF_FMPLL_SYNSR_LOCF         (0x00000004)
+#define MCF_FMPLL_SYNSR_LOCK         (0x00000008)
+#define MCF_FMPLL_SYNSR_LOCKS        (0x00000010)
+#define MCF_FMPLL_SYNSR_PLLREF       (0x00000020)
+#define MCF_FMPLL_SYNSR_PLLSEL       (0x00000040)
+#define MCF_FMPLL_SYNSR_MODE         (0x00000080)
+#define MCF_FMPLL_SYNSR_LOC          (0x00000100)
+#define MCF_FMPLL_SYNSR_LOLF         (0x00000200)
+
+/********************************************************************/
+
+#endif /* __MCF523X_FMPLL_H__ */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_gpio.h b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_gpio.h
new file mode 100644
index 000000000..df8c36600
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_gpio.h
@@ -0,0 +1,676 @@
+/*
+ * These files are taken from the MCF523X source code example package
+ * which is available on the Freescale website. Freescale explicitly 
+ * grants the redistribution and modification of these source files.
+ * The complete licensing information is available in the file 
+ * LICENSE_FREESCALE.TXT.
+ *
+ * File:	mcf523x_gpio.h
+ * Purpose:	Register and bit definitions for the MCF523X
+ *
+ * Notes:	
+ *	
+ */
+
+#ifndef __MCF523X_GPIO_H__
+#define __MCF523X_GPIO_H__
+
+/*********************************************************************
+*
+* General Purpose I/O (GPIO)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_GPIO_PODR_ADDR        (*(vuint8 *)(void*)(&__IPSBAR[0x100000]))
+#define MCF_GPIO_PODR_DATAH       (*(vuint8 *)(void*)(&__IPSBAR[0x100001]))
+#define MCF_GPIO_PODR_DATAL       (*(vuint8 *)(void*)(&__IPSBAR[0x100002]))
+#define MCF_GPIO_PODR_BUSCTL      (*(vuint8 *)(void*)(&__IPSBAR[0x100003]))
+#define MCF_GPIO_PODR_BS          (*(vuint8 *)(void*)(&__IPSBAR[0x100004]))
+#define MCF_GPIO_PODR_CS          (*(vuint8 *)(void*)(&__IPSBAR[0x100005]))
+#define MCF_GPIO_PODR_SDRAM       (*(vuint8 *)(void*)(&__IPSBAR[0x100006]))
+#define MCF_GPIO_PODR_FECI2C      (*(vuint8 *)(void*)(&__IPSBAR[0x100007]))
+#define MCF_GPIO_PODR_UARTH       (*(vuint8 *)(void*)(&__IPSBAR[0x100008]))
+#define MCF_GPIO_PODR_UARTL       (*(vuint8 *)(void*)(&__IPSBAR[0x100009]))
+#define MCF_GPIO_PODR_QSPI        (*(vuint8 *)(void*)(&__IPSBAR[0x10000A]))
+#define MCF_GPIO_PODR_TIMER       (*(vuint8 *)(void*)(&__IPSBAR[0x10000B]))
+#define MCF_GPIO_PODR_ETPU        (*(vuint8 *)(void*)(&__IPSBAR[0x10000C]))
+#define MCF_GPIO_PDDR_APDDR       (*(vuint8 *)(void*)(&__IPSBAR[0x100010]))
+#define MCF_GPIO_PDDR_DATAH       (*(vuint8 *)(void*)(&__IPSBAR[0x100011]))
+#define MCF_GPIO_PDDR_DATAL       (*(vuint8 *)(void*)(&__IPSBAR[0x100012]))
+#define MCF_GPIO_PDDR_BUSCTL      (*(vuint8 *)(void*)(&__IPSBAR[0x100013]))
+#define MCF_GPIO_PDDR_BS          (*(vuint8 *)(void*)(&__IPSBAR[0x100014]))
+#define MCF_GPIO_PDDR_CS          (*(vuint8 *)(void*)(&__IPSBAR[0x100015]))
+#define MCF_GPIO_PDDR_SDRAM       (*(vuint8 *)(void*)(&__IPSBAR[0x100016]))
+#define MCF_GPIO_PDDR_FECI2C      (*(vuint8 *)(void*)(&__IPSBAR[0x100017]))
+#define MCF_GPIO_PDDR_UARTH       (*(vuint8 *)(void*)(&__IPSBAR[0x100018]))
+#define MCF_GPIO_PDDR_UARTL       (*(vuint8 *)(void*)(&__IPSBAR[0x100019]))
+#define MCF_GPIO_PDDR_QSPI        (*(vuint8 *)(void*)(&__IPSBAR[0x10001A]))
+#define MCF_GPIO_PDDR_TIMER       (*(vuint8 *)(void*)(&__IPSBAR[0x10001B]))
+#define MCF_GPIO_PDDR_ETPU        (*(vuint8 *)(void*)(&__IPSBAR[0x10001C]))
+#define MCF_GPIO_PPDSDR_ADDR      (*(vuint8 *)(void*)(&__IPSBAR[0x100020]))
+#define MCF_GPIO_PPDSDR_DATAH     (*(vuint8 *)(void*)(&__IPSBAR[0x100021]))
+#define MCF_GPIO_PPDSDR_DATAL     (*(vuint8 *)(void*)(&__IPSBAR[0x100022]))
+#define MCF_GPIO_PPDSDR_BUSCTL    (*(vuint8 *)(void*)(&__IPSBAR[0x100023]))
+#define MCF_GPIO_PPDSDR_BS        (*(vuint8 *)(void*)(&__IPSBAR[0x100024]))
+#define MCF_GPIO_PPDSDR_FECI2C    (*(vuint8 *)(void*)(&__IPSBAR[0x100027]))
+#define MCF_GPIO_PPDSDR_CS        (*(vuint8 *)(void*)(&__IPSBAR[0x100025]))
+#define MCF_GPIO_PPDSDR_SDRAM     (*(vuint8 *)(void*)(&__IPSBAR[0x100026]))
+#define MCF_GPIO_PPDSDR_UARTH     (*(vuint8 *)(void*)(&__IPSBAR[0x100028]))
+#define MCF_GPIO_PPDSDR_UARTL     (*(vuint8 *)(void*)(&__IPSBAR[0x100029]))
+#define MCF_GPIO_PPDSDR_QSPI      (*(vuint8 *)(void*)(&__IPSBAR[0x10002A]))
+#define MCF_GPIO_PPDSDR_TIMER     (*(vuint8 *)(void*)(&__IPSBAR[0x10002B]))
+#define MCF_GPIO_PPDSDR_ETPU      (*(vuint8 *)(void*)(&__IPSBAR[0x10002C]))
+#define MCF_GPIO_PCLRR_ADDR       (*(vuint8 *)(void*)(&__IPSBAR[0x100030]))
+#define MCF_GPIO_PCLRR_DATAH      (*(vuint8 *)(void*)(&__IPSBAR[0x100031]))
+#define MCF_GPIO_PCLRR_DATAL      (*(vuint8 *)(void*)(&__IPSBAR[0x100032]))
+#define MCF_GPIO_PCLRR_BUSCTL     (*(vuint8 *)(void*)(&__IPSBAR[0x100033]))
+#define MCF_GPIO_PCLRR_BS         (*(vuint8 *)(void*)(&__IPSBAR[0x100034]))
+#define MCF_GPIO_PCLRR_CS         (*(vuint8 *)(void*)(&__IPSBAR[0x100035]))
+#define MCF_GPIO_PCLRR_SDRAM      (*(vuint8 *)(void*)(&__IPSBAR[0x100036]))
+#define MCF_GPIO_PCLRR_FECI2C     (*(vuint8 *)(void*)(&__IPSBAR[0x100037]))
+#define MCF_GPIO_PCLRR_UARTH      (*(vuint8 *)(void*)(&__IPSBAR[0x100038]))
+#define MCF_GPIO_PCLRR_UARTL      (*(vuint8 *)(void*)(&__IPSBAR[0x100039]))
+#define MCF_GPIO_PCLRR_QSPI       (*(vuint8 *)(void*)(&__IPSBAR[0x10003A]))
+#define MCF_GPIO_PCLRR_TIMER      (*(vuint8 *)(void*)(&__IPSBAR[0x10003B]))
+#define MCF_GPIO_PCLRR_ETPU       (*(vuint8 *)(void*)(&__IPSBAR[0x10003C]))
+#define MCF_GPIO_PAR_AD           (*(vuint8 *)(void*)(&__IPSBAR[0x100040]))
+#define MCF_GPIO_PAR_BUSCTL       (*(vuint16*)(void*)(&__IPSBAR[0x100042]))
+#define MCF_GPIO_PAR_BS           (*(vuint8 *)(void*)(&__IPSBAR[0x100044]))
+#define MCF_GPIO_PAR_CS           (*(vuint8 *)(void*)(&__IPSBAR[0x100045]))
+#define MCF_GPIO_PAR_SDRAM        (*(vuint8 *)(void*)(&__IPSBAR[0x100046]))
+#define MCF_GPIO_PAR_FECI2C       (*(vuint8 *)(void*)(&__IPSBAR[0x100047]))
+#define MCF_GPIO_PAR_UART         (*(vuint16*)(void*)(&__IPSBAR[0x100048]))
+#define MCF_GPIO_PAR_QSPI         (*(vuint8 *)(void*)(&__IPSBAR[0x10004A]))
+#define MCF_GPIO_PAR_TIMER        (*(vuint16*)(void*)(&__IPSBAR[0x10004C]))
+#define MCF_GPIO_PAR_ETPU         (*(vuint8 *)(void*)(&__IPSBAR[0x10004E]))
+#define MCF_GPIO_DSCR_EIM         (*(vuint8 *)(void*)(&__IPSBAR[0x100050]))
+#define MCF_GPIO_DSCR_ETPU        (*(vuint8 *)(void*)(&__IPSBAR[0x100051]))
+#define MCF_GPIO_DSCR_FECI2C      (*(vuint8 *)(void*)(&__IPSBAR[0x100052]))
+#define MCF_GPIO_DSCR_UART        (*(vuint8 *)(void*)(&__IPSBAR[0x100053]))
+#define MCF_GPIO_DSCR_QSPI        (*(vuint8 *)(void*)(&__IPSBAR[0x100054]))
+#define MCF_GPIO_DSCR_TIMER       (*(vuint8 *)(void*)(&__IPSBAR[0x100055]))
+
+/* Bit definitions and macros for MCF_GPIO_PODR_ADDR */
+#define MCF_GPIO_PODR_ADDR_PODR_ADDR5            (0x20)
+#define MCF_GPIO_PODR_ADDR_PODR_ADDR6            (0x40)
+#define MCF_GPIO_PODR_ADDR_PODR_ADDR7            (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_DATAH */
+#define MCF_GPIO_PODR_DATAH_PODR_DATAH0          (0x01)
+#define MCF_GPIO_PODR_DATAH_PODR_DATAH1          (0x02)
+#define MCF_GPIO_PODR_DATAH_PODR_DATAH2          (0x04)
+#define MCF_GPIO_PODR_DATAH_PODR_DATAH3          (0x08)
+#define MCF_GPIO_PODR_DATAH_PODR_DATAH4          (0x10)
+#define MCF_GPIO_PODR_DATAH_PODR_DATAH5          (0x20)
+#define MCF_GPIO_PODR_DATAH_PODR_DATAH6          (0x40)
+#define MCF_GPIO_PODR_DATAH_PODR_DATAH7          (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_DATAL */
+#define MCF_GPIO_PODR_DATAL_PODR_DATAL0          (0x01)
+#define MCF_GPIO_PODR_DATAL_PODR_DATAL1          (0x02)
+#define MCF_GPIO_PODR_DATAL_PODR_DATAL2          (0x04)
+#define MCF_GPIO_PODR_DATAL_PODR_DATAL3          (0x08)
+#define MCF_GPIO_PODR_DATAL_PODR_DATAL4          (0x10)
+#define MCF_GPIO_PODR_DATAL_PODR_DATAL5          (0x20)
+#define MCF_GPIO_PODR_DATAL_PODR_DATAL6          (0x40)
+#define MCF_GPIO_PODR_DATAL_PODR_DATAL7          (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_BUSCTL */
+#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL0        (0x01)
+#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL1        (0x02)
+#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL2        (0x04)
+#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL3        (0x08)
+#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL4        (0x10)
+#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL5        (0x20)
+#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL6        (0x40)
+#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL7        (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_BS */
+#define MCF_GPIO_PODR_BS_PODR_BS0                (0x01)
+#define MCF_GPIO_PODR_BS_PODR_BS1                (0x02)
+#define MCF_GPIO_PODR_BS_PODR_BS2                (0x04)
+#define MCF_GPIO_PODR_BS_PODR_BS3                (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_CS */
+#define MCF_GPIO_PODR_CS_PODR_CS1                (0x02)
+#define MCF_GPIO_PODR_CS_PODR_CS2                (0x04)
+#define MCF_GPIO_PODR_CS_PODR_CS3                (0x08)
+#define MCF_GPIO_PODR_CS_PODR_CS4                (0x10)
+#define MCF_GPIO_PODR_CS_PODR_CS5                (0x20)
+#define MCF_GPIO_PODR_CS_PODR_CS6                (0x40)
+#define MCF_GPIO_PODR_CS_PODR_CS7                (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_SDRAM */
+#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM0          (0x01)
+#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM1          (0x02)
+#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM2          (0x04)
+#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM3          (0x08)
+#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM4          (0x10)
+#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM5          (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */
+#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0        (0x01)
+#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1        (0x02)
+#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2        (0x04)
+#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3        (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_UARTH */
+#define MCF_GPIO_PODR_UARTH_PODR_UARTH0          (0x01)
+#define MCF_GPIO_PODR_UARTH_PODR_UARTH1          (0x02)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_UARTL */
+#define MCF_GPIO_PODR_UARTL_PODR_UARTL0          (0x01)
+#define MCF_GPIO_PODR_UARTL_PODR_UARTL1          (0x02)
+#define MCF_GPIO_PODR_UARTL_PODR_UARTL2          (0x04)
+#define MCF_GPIO_PODR_UARTL_PODR_UARTL3          (0x08)
+#define MCF_GPIO_PODR_UARTL_PODR_UARTL4          (0x10)
+#define MCF_GPIO_PODR_UARTL_PODR_UARTL5          (0x20)
+#define MCF_GPIO_PODR_UARTL_PODR_UARTL6          (0x40)
+#define MCF_GPIO_PODR_UARTL_PODR_UARTL7          (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_QSPI */
+#define MCF_GPIO_PODR_QSPI_PODR_QSPI0            (0x01)
+#define MCF_GPIO_PODR_QSPI_PODR_QSPI1            (0x02)
+#define MCF_GPIO_PODR_QSPI_PODR_QSPI2            (0x04)
+#define MCF_GPIO_PODR_QSPI_PODR_QSPI3            (0x08)
+#define MCF_GPIO_PODR_QSPI_PODR_QSPI4            (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_TIMER */
+#define MCF_GPIO_PODR_TIMER_PODR_TIMER0          (0x01)
+#define MCF_GPIO_PODR_TIMER_PODR_TIMER1          (0x02)
+#define MCF_GPIO_PODR_TIMER_PODR_TIMER2          (0x04)
+#define MCF_GPIO_PODR_TIMER_PODR_TIMER3          (0x08)
+#define MCF_GPIO_PODR_TIMER_PODR_TIMER4          (0x10)
+#define MCF_GPIO_PODR_TIMER_PODR_TIMER5          (0x20)
+#define MCF_GPIO_PODR_TIMER_PODR_TIMER6          (0x40)
+#define MCF_GPIO_PODR_TIMER_PODR_TIMER7          (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_ETPU */
+#define MCF_GPIO_PODR_ETPU_PODR_ETPU0            (0x01)
+#define MCF_GPIO_PODR_ETPU_PODR_ETPU1            (0x02)
+#define MCF_GPIO_PODR_ETPU_PODR_ETPU2            (0x04)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_APDDR */
+#define MCF_GPIO_PDDR_APDDR_PDDR_APDDR5          (0x20)
+#define MCF_GPIO_PDDR_APDDR_PDDR_APDDR6          (0x40)
+#define MCF_GPIO_PDDR_APDDR_PDDR_APDDR7          (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_DATAH */
+#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH0          (0x01)
+#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH1          (0x02)
+#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH2          (0x04)
+#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH3          (0x08)
+#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH4          (0x10)
+#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH5          (0x20)
+#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH6          (0x40)
+#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH7          (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_DATAL */
+#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL0          (0x01)
+#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL1          (0x02)
+#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL2          (0x04)
+#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL3          (0x08)
+#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL4          (0x10)
+#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL5          (0x20)
+#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL6          (0x40)
+#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL7          (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_BUSCTL */
+#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL0        (0x01)
+#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL1        (0x02)
+#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL2        (0x04)
+#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL3        (0x08)
+#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL4        (0x10)
+#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL5        (0x20)
+#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL6        (0x40)
+#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL7        (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_BS */
+#define MCF_GPIO_PDDR_BS_PDDR_BS0                (0x01)
+#define MCF_GPIO_PDDR_BS_PDDR_BS3(x)             (((x)&0x07)<<1)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_CS */
+#define MCF_GPIO_PDDR_CS_PDDR_CS1                (0x02)
+#define MCF_GPIO_PDDR_CS_PDDR_CS2                (0x04)
+#define MCF_GPIO_PDDR_CS_PDDR_CS3                (0x08)
+#define MCF_GPIO_PDDR_CS_PDDR_CS4                (0x10)
+#define MCF_GPIO_PDDR_CS_PDDR_CS5                (0x20)
+#define MCF_GPIO_PDDR_CS_PDDR_CS6                (0x40)
+#define MCF_GPIO_PDDR_CS_PDDR_CS7                (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_SDRAM */
+#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM0          (0x01)
+#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM1          (0x02)
+#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM2          (0x04)
+#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM3          (0x08)
+#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM4          (0x10)
+#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM5          (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */
+#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0        (0x01)
+#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1        (0x02)
+#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2        (0x04)
+#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3        (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_UARTH */
+#define MCF_GPIO_PDDR_UARTH_PDDR_UARTH0          (0x01)
+#define MCF_GPIO_PDDR_UARTH_PDDR_UARTH1          (0x02)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_UARTL */
+#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL0          (0x01)
+#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL1          (0x02)
+#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL2          (0x04)
+#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL3          (0x08)
+#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL4          (0x10)
+#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL5          (0x20)
+#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL6          (0x40)
+#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL7          (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_QSPI */
+#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI0            (0x01)
+#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI1            (0x02)
+#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI2            (0x04)
+#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI3            (0x08)
+#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI4            (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_TIMER */
+#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER0          (0x01)
+#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER1          (0x02)
+#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER2          (0x04)
+#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER3          (0x08)
+#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER4          (0x10)
+#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER5          (0x20)
+#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER6          (0x40)
+#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER7          (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_ETPU */
+#define MCF_GPIO_PDDR_ETPU_PDDR_ETPU0            (0x01)
+#define MCF_GPIO_PDDR_ETPU_PDDR_ETPU1            (0x02)
+#define MCF_GPIO_PDDR_ETPU_PDDR_ETPU2            (0x04)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_ADDR */
+#define MCF_GPIO_PPDSDR_ADDR_PPDSDR_ADDR5        (0x20)
+#define MCF_GPIO_PPDSDR_ADDR_PPDSDR_ADDR6        (0x40)
+#define MCF_GPIO_PPDSDR_ADDR_PPDSDR_ADDR7        (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_DATAH */
+#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH0      (0x01)
+#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH1      (0x02)
+#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH2      (0x04)
+#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH3      (0x08)
+#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH4      (0x10)
+#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH5      (0x20)
+#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH6      (0x40)
+#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_DATAL */
+#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL0      (0x01)
+#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL1      (0x02)
+#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL2      (0x04)
+#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL3      (0x08)
+#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL4      (0x10)
+#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL5      (0x20)
+#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL6      (0x40)
+#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_BUSCTL */
+#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL0    (0x01)
+#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL1    (0x02)
+#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL2    (0x04)
+#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL3    (0x08)
+#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL4    (0x10)
+#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL5    (0x20)
+#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL6    (0x40)
+#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL7    (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_BS */
+#define MCF_GPIO_PPDSDR_BS_PPDSDR_BS0            (0x01)
+#define MCF_GPIO_PPDSDR_BS_PPDSDR_BS1            (0x02)
+#define MCF_GPIO_PPDSDR_BS_PPDSDR_BS2            (0x04)
+#define MCF_GPIO_PPDSDR_BS_PPDSDR_BS3            (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */
+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0    (0x01)
+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1    (0x02)
+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2    (0x04)
+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3    (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_CS */
+#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS1            (0x02)
+#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS2            (0x04)
+#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS3            (0x08)
+#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS4            (0x10)
+#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS5            (0x20)
+#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS6            (0x40)
+#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS7            (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_SDRAM */
+#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM0      (0x01)
+#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM1      (0x02)
+#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM2      (0x04)
+#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM3      (0x08)
+#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM4      (0x10)
+#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM5      (0x20)
+#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM6      (0x40)
+#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_UARTH */
+#define MCF_GPIO_PPDSDR_UARTH_PPDSDR_UARTH0      (0x01)
+#define MCF_GPIO_PPDSDR_UARTH_PPDSDR_UARTH1      (0x02)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_UARTL */
+#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL0      (0x01)
+#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL1      (0x02)
+#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL2      (0x04)
+#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL3      (0x08)
+#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL4      (0x10)
+#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL5      (0x20)
+#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL6      (0x40)
+#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_QSPI */
+#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI0        (0x01)
+#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI1        (0x02)
+#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI2        (0x04)
+#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI3        (0x08)
+#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI4        (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_TIMER */
+#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER0      (0x01)
+#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER1      (0x02)
+#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER2      (0x04)
+#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER3      (0x08)
+#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER4      (0x10)
+#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER5      (0x20)
+#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER6      (0x40)
+#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_ETPU */
+#define MCF_GPIO_PPDSDR_ETPU_PPDSDR_ETPU0        (0x01)
+#define MCF_GPIO_PPDSDR_ETPU_PPDSDR_ETPU1        (0x02)
+#define MCF_GPIO_PPDSDR_ETPU_PPDSDR_ETPU2        (0x04)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_ADDR */
+#define MCF_GPIO_PCLRR_ADDR_PCLRR_ADDR5          (0x20)
+#define MCF_GPIO_PCLRR_ADDR_PCLRR_ADDR6          (0x40)
+#define MCF_GPIO_PCLRR_ADDR_PCLRR_ADDR7          (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_DATAH */
+#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH0        (0x01)
+#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH1        (0x02)
+#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH2        (0x04)
+#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH3        (0x08)
+#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH4        (0x10)
+#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH5        (0x20)
+#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH6        (0x40)
+#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH7        (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_DATAL */
+#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL0        (0x01)
+#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL1        (0x02)
+#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL2        (0x04)
+#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL3        (0x08)
+#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL4        (0x10)
+#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL5        (0x20)
+#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL6        (0x40)
+#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL7        (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_BUSCTL */
+#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL0      (0x01)
+#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL1      (0x02)
+#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL2      (0x04)
+#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL3      (0x08)
+#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL4      (0x10)
+#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL5      (0x20)
+#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL6      (0x40)
+#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_BS */
+#define MCF_GPIO_PCLRR_BS_PCLRR_BS0              (0x01)
+#define MCF_GPIO_PCLRR_BS_PCLRR_BS1              (0x02)
+#define MCF_GPIO_PCLRR_BS_PCLRR_BS2              (0x04)
+#define MCF_GPIO_PCLRR_BS_PCLRR_BS3              (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_CS */
+#define MCF_GPIO_PCLRR_CS_PCLRR_CS1              (0x02)
+#define MCF_GPIO_PCLRR_CS_PCLRR_CS2              (0x04)
+#define MCF_GPIO_PCLRR_CS_PCLRR_CS3              (0x08)
+#define MCF_GPIO_PCLRR_CS_PCLRR_CS4              (0x10)
+#define MCF_GPIO_PCLRR_CS_PCLRR_CS5              (0x20)
+#define MCF_GPIO_PCLRR_CS_PCLRR_CS6              (0x40)
+#define MCF_GPIO_PCLRR_CS_PCLRR_CS7              (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_SDRAM */
+#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM0        (0x01)
+#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM1        (0x02)
+#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM2        (0x04)
+#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM3        (0x08)
+#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM4        (0x10)
+#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM5        (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0      (0x01)
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1      (0x02)
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2      (0x04)
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3      (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_UARTH */
+#define MCF_GPIO_PCLRR_UARTH_PCLRR_UARTH0        (0x01)
+#define MCF_GPIO_PCLRR_UARTH_PCLRR_UARTH1        (0x02)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_UARTL */
+#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL0        (0x01)
+#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL1        (0x02)
+#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL2        (0x04)
+#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL3        (0x08)
+#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL4        (0x10)
+#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL5        (0x20)
+#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL6        (0x40)
+#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL7        (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_QSPI */
+#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI0          (0x01)
+#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI1          (0x02)
+#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI2          (0x04)
+#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI3          (0x08)
+#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI4          (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_TIMER */
+#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER0        (0x01)
+#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER1        (0x02)
+#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER2        (0x04)
+#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER3        (0x08)
+#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER4        (0x10)
+#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER5        (0x20)
+#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER6        (0x40)
+#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER7        (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_ETPU */
+#define MCF_GPIO_PCLRR_ETPU_PCLRR_ETPU0          (0x01)
+#define MCF_GPIO_PCLRR_ETPU_PCLRR_ETPU1          (0x02)
+#define MCF_GPIO_PCLRR_ETPU_PCLRR_ETPU2          (0x04)
+
+/* Bit definitions and macros for MCF_GPIO_PAR_AD */
+#define MCF_GPIO_PAR_AD_PAR_DATAL                (0x01)
+#define MCF_GPIO_PAR_AD_PAR_ADDR21               (0x20)
+#define MCF_GPIO_PAR_AD_PAR_ADDR22               (0x40)
+#define MCF_GPIO_PAR_AD_PAR_ADDR23               (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PAR_BUSCTL */
+#define MCF_GPIO_PAR_BUSCTL_PAR_TIP(x)           (((x)&0x0003)<<0)
+#define MCF_GPIO_PAR_BUSCTL_PAR_TS(x)            (((x)&0x0003)<<2)
+#define MCF_GPIO_PAR_BUSCTL_PAR_TSIZ0            (0x0010)
+#define MCF_GPIO_PAR_BUSCTL_PAR_TSIZ1            (0x0040)
+#define MCF_GPIO_PAR_BUSCTL_PAR_RWB              (0x0100)
+#define MCF_GPIO_PAR_BUSCTL_PAR_TEA(x)           (((x)&0x0003)<<10)
+#define MCF_GPIO_PAR_BUSCTL_PAR_TA               (0x1000)
+#define MCF_GPIO_PAR_BUSCTL_PAR_OE               (0x4000)
+#define MCF_GPIO_PAR_BUSCTL_PAR_TEA_GPIO         (0x0000)
+#define MCF_GPIO_PAR_BUSCTL_PAR_TEA_DMA          (0x0800)
+#define MCF_GPIO_PAR_BUSCTL_PAR_TEA_TEA          (0x0C00)
+#define MCF_GPIO_PAR_BUSCTL_PAR_TS_GPIO          (0x0000)
+#define MCF_GPIO_PAR_BUSCTL_PAR_TS_DMA           (0x0080)
+#define MCF_GPIO_PAR_BUSCTL_PAR_TS_TS            (0x00C0)
+#define MCF_GPIO_PAR_BUSCTL_PAR_TIP_GPIO         (0x0000)
+#define MCF_GPIO_PAR_BUSCTL_PAR_TIP_DMA          (0x0002)
+#define MCF_GPIO_PAR_BUSCTL_PAR_TIP_TEA          (0x0003)
+
+/* Bit definitions and macros for MCF_GPIO_PAR_BS */
+#define MCF_GPIO_PAR_BS_PAR_BS0                  (0x01)
+#define MCF_GPIO_PAR_BS_PAR_BS1                  (0x02)
+#define MCF_GPIO_PAR_BS_PAR_BS2                  (0x04)
+#define MCF_GPIO_PAR_BS_PAR_BS3                  (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PAR_CS */
+#define MCF_GPIO_PAR_CS_PAR_CS1                  (0x02)
+#define MCF_GPIO_PAR_CS_PAR_CS2                  (0x04)
+#define MCF_GPIO_PAR_CS_PAR_CS3                  (0x08)
+#define MCF_GPIO_PAR_CS_PAR_CS4                  (0x10)
+#define MCF_GPIO_PAR_CS_PAR_CS5                  (0x20)
+#define MCF_GPIO_PAR_CS_PAR_CS6                  (0x40)
+#define MCF_GPIO_PAR_CS_PAR_CS7                  (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PAR_SDRAM */
+#define MCF_GPIO_PAR_SDRAM_PAR_SDCS0             (0x01)
+#define MCF_GPIO_PAR_SDRAM_PAR_SDCS1             (0x02)
+#define MCF_GPIO_PAR_SDRAM_PAR_SCKE              (0x04)
+#define MCF_GPIO_PAR_SDRAM_PAR_SRAS              (0x08)
+#define MCF_GPIO_PAR_SDRAM_PAR_SCAS              (0x10)
+#define MCF_GPIO_PAR_SDRAM_PAR_SDWE              (0x20)
+#define MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(x)         (((x)&0x03)<<6)
+
+/* Bit definitions and macros for MCF_GPIO_PAR_FECI2C */
+#define MCF_GPIO_PAR_FECI2C_PAR_SDA(x)           (((x)&0x03)<<0)
+#define MCF_GPIO_PAR_FECI2C_PAR_SCL(x)           (((x)&0x03)<<2)
+#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO(x)         (((x)&0x03)<<4)
+#define MCF_GPIO_PAR_FECI2C_PAR_EMDC(x)          (((x)&0x03)<<6)
+#define MCF_GPIO_PAR_FECI2C_PAR_EMDC_GPIO        (0x00)
+#define MCF_GPIO_PAR_FECI2C_PAR_EMDC_UART2       (0x40)
+#define MCF_GPIO_PAR_FECI2C_PAR_EMDC_I2C         (0x80)
+#define MCF_GPIO_PAR_FECI2C_PAR_EMDC_FEC         (0xC0)
+#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO_GPIO       (0x00)
+#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO_UART2      (0x10)
+#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO_I2C        (0x20)
+#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO_FEC        (0x30)
+#define MCF_GPIO_PAR_FECI2C_PAR_SCL_GPIO         (0x00)
+#define MCF_GPIO_PAR_FECI2C_PAR_SCL_FLEX         (0x08)
+#define MCF_GPIO_PAR_FECI2C_PAR_SCL_I2C          (0x0C)
+#define MCF_GPIO_PAR_FECI2C_PAR_SDA_GPIO         (0x00)
+#define MCF_GPIO_PAR_FECI2C_PAR_SDA_FLEX         (0x02)
+#define MCF_GPIO_PAR_FECI2C_PAR_SDA_I2C          (0x03)
+
+/* Bit definitions and macros for MCF_GPIO_PAR_UART */
+#define MCF_GPIO_PAR_UART_PAR_U0RTS              (0x0001)
+#define MCF_GPIO_PAR_UART_PAR_U0CTS              (0x0002)
+#define MCF_GPIO_PAR_UART_PAR_U0TXD              (0x0004)
+#define MCF_GPIO_PAR_UART_PAR_U0RXD              (0x0008)
+#define MCF_GPIO_PAR_UART_PAR_U1RTS(x)           (((x)&0x0003)<<4)
+#define MCF_GPIO_PAR_UART_PAR_U1CTS(x)           (((x)&0x0003)<<6)
+#define MCF_GPIO_PAR_UART_PAR_U1TXD(x)           (((x)&0x0003)<<8)
+#define MCF_GPIO_PAR_UART_PAR_U1RXD(x)           (((x)&0x0003)<<10)
+#define MCF_GPIO_PAR_UART_PAR_U2TXD              (0x1000)
+#define MCF_GPIO_PAR_UART_PAR_U2RXD              (0x2000)
+#define MCF_GPIO_PAR_UART_PAR_CAN1EN             (0x4000)
+#define MCF_GPIO_PAR_UART_PAR_DREQ2              (0x8000)
+#define MCF_GPIO_PAR_UART_PAR_U1RXD_GPIO         (0x0000)
+#define MCF_GPIO_PAR_UART_PAR_U1RXD_FLEX         (0x0800)
+#define MCF_GPIO_PAR_UART_PAR_U1RXD_UART1        (0x0C00)
+#define MCF_GPIO_PAR_UART_PAR_U1TXD_GPIO         (0x0000)
+#define MCF_GPIO_PAR_UART_PAR_U1TXD_FLEX         (0x0200)
+#define MCF_GPIO_PAR_UART_PAR_U1TXD_UART1        (0x0300)
+#define MCF_GPIO_PAR_UART_PAR_U1CTS_GPIO         (0x0000)
+#define MCF_GPIO_PAR_UART_PAR_U1CTS_UART2        (0x0080)
+#define MCF_GPIO_PAR_UART_PAR_U1CTS_UART1        (0x00C0)
+#define MCF_GPIO_PAR_UART_PAR_U1RTS_GPIO         (0x0000)
+#define MCF_GPIO_PAR_UART_PAR_U1RTS_UART2        (0x0020)
+#define MCF_GPIO_PAR_UART_PAR_U1RTS_UART1        (0x0030)
+
+/* Bit definitions and macros for MCF_GPIO_PAR_QSPI */
+#define MCF_GPIO_PAR_QSPI_PAR_SCK(x)             (((x)&0x03)<<0)
+#define MCF_GPIO_PAR_QSPI_PAR_DOUT               (0x04)
+#define MCF_GPIO_PAR_QSPI_PAR_DIN(x)             (((x)&0x03)<<3)
+#define MCF_GPIO_PAR_QSPI_PAR_PCS0               (0x20)
+#define MCF_GPIO_PAR_QSPI_PAR_PCS1(x)            (((x)&0x03)<<6)
+#define MCF_GPIO_PAR_QSPI_PAR_PCS1_GPIO          (0x00)
+#define MCF_GPIO_PAR_QSPI_PAR_PCS1_SDRAMC        (0x80)
+#define MCF_GPIO_PAR_QSPI_PAR_PCS1_QSPI          (0xC0)
+#define MCF_GPIO_PAR_QSPI_PAR_DIN_GPIO           (0x00)
+#define MCF_GPIO_PAR_QSPI_PAR_DIN_I2C            (0x10)
+#define MCF_GPIO_PAR_QSPI_PAR_DIN_QSPI           (0x1C)
+#define MCF_GPIO_PAR_QSPI_PAR_SCK_GPIO           (0x00)
+#define MCF_GPIO_PAR_QSPI_PAR_SCK_I2C            (0x02)
+#define MCF_GPIO_PAR_QSPI_PAR_SCK_QSPI           (0x03)
+
+/* Bit definitions and macros for MCF_GPIO_PAR_TIMER */
+#define MCF_GPIO_PAR_TIMER_PAR_T0OUT(x)          (((x)&0x0003)<<0)
+#define MCF_GPIO_PAR_TIMER_PAR_T1OUT(x)          (((x)&0x0003)<<2)
+#define MCF_GPIO_PAR_TIMER_PAR_T2OUT(x)          (((x)&0x0003)<<4)
+#define MCF_GPIO_PAR_TIMER_PAR_T3OUT(x)          (((x)&0x0003)<<6)
+#define MCF_GPIO_PAR_TIMER_PAR_T0IN(x)           (((x)&0x0003)<<8)
+#define MCF_GPIO_PAR_TIMER_PAR_T1IN(x)           (((x)&0x0003)<<10)
+#define MCF_GPIO_PAR_TIMER_PAR_T2IN(x)           (((x)&0x0003)<<12)
+#define MCF_GPIO_PAR_TIMER_PAR_T3IN(x)           (((x)&0x0003)<<14)
+#define MCF_GPIO_PAR_TIMER_PAR_T3IN_GPIO         (0x0000)
+#define MCF_GPIO_PAR_TIMER_PAR_T3IN_QSPI         (0x4000)
+#define MCF_GPIO_PAR_TIMER_PAR_T3IN_UART2        (0x8000)
+#define MCF_GPIO_PAR_TIMER_PAR_T3IN_T3IN         (0xC000)
+#define MCF_GPIO_PAR_TIMER_PAR_T2IN_GPIO         (0x0000)
+#define MCF_GPIO_PAR_TIMER_PAR_T2IN_T2OUT        (0x1000)
+#define MCF_GPIO_PAR_TIMER_PAR_T2IN_DMA          (0x2000)
+#define MCF_GPIO_PAR_TIMER_PAR_T2IN_T2IN         (0x3000)
+#define MCF_GPIO_PAR_TIMER_PAR_T1IN_GPIO         (0x0000)
+#define MCF_GPIO_PAR_TIMER_PAR_T1IN_T1OUT        (0x0400)
+#define MCF_GPIO_PAR_TIMER_PAR_T1IN_DMA          (0x0800)
+#define MCF_GPIO_PAR_TIMER_PAR_T1IN_T1IN         (0x0C00)
+#define MCF_GPIO_PAR_TIMER_PAR_T0IN_GPIO         (0x0000)
+#define MCF_GPIO_PAR_TIMER_PAR_T0IN_DMA          (0x0200)
+#define MCF_GPIO_PAR_TIMER_PAR_T0IN_T0IN         (0x0300)
+#define MCF_GPIO_PAR_TIMER_PAR_T3OUT_GPIO        (0x0000)
+#define MCF_GPIO_PAR_TIMER_PAR_T3OUT_QSPI        (0x0040)
+#define MCF_GPIO_PAR_TIMER_PAR_T3OUT_UART2       (0x0080)
+#define MCF_GPIO_PAR_TIMER_PAR_T3OUT_T3OUT       (0x00C0)
+#define MCF_GPIO_PAR_TIMER_PAR_T2OUT_GPIO        (0x0000)
+#define MCF_GPIO_PAR_TIMER_PAR_T2OUT_DMA         (0x0020)
+#define MCF_GPIO_PAR_TIMER_PAR_T2OUT_T2OUT       (0x0030)
+#define MCF_GPIO_PAR_TIMER_PAR_T1OUT_GPIO        (0x0000)
+#define MCF_GPIO_PAR_TIMER_PAR_T1OUT_DMA         (0x0008)
+#define MCF_GPIO_PAR_TIMER_PAR_T1OUT_T1OUT       (0x000C)
+#define MCF_GPIO_PAR_TIMER_PAR_T0OUT_GPIO        (0x0000)
+#define MCF_GPIO_PAR_TIMER_PAR_T0OUT_DMA         (0x0002)
+#define MCF_GPIO_PAR_TIMER_PAR_T0OUT_T0OUT       (0x0003)
+
+/* Bit definitions and macros for MCF_GPIO_PAR_ETPU */
+#define MCF_GPIO_PAR_ETPU_PAR_LTPU_ODIS          (0x01)
+#define MCF_GPIO_PAR_ETPU_PAR_UTPU_ODIS          (0x02)
+#define MCF_GPIO_PAR_ETPU_PAR_TCRCLK             (0x04)
+
+/* Bit definitions and macros for MCF_GPIO_DSCR_EIM */
+#define MCF_GPIO_DSCR_EIM_DSCR_EIM0              (0x01)
+#define MCF_GPIO_DSCR_EIM_DSCR_EIM1              (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_DSCR_ETPU */
+#define MCF_GPIO_DSCR_ETPU_DSCR_ETPU_7_0         (0x01)
+#define MCF_GPIO_DSCR_ETPU_DSCR_ETPU_15_8        (0x04)
+#define MCF_GPIO_DSCR_ETPU_DSCR_ETPU_23_16       (0x10)
+#define MCF_GPIO_DSCR_ETPU_DSCR_ETPU_31_24       (0x40)
+
+/* Bit definitions and macros for MCF_GPIO_DSCR_FECI2C */
+#define MCF_GPIO_DSCR_FECI2C_DSCR_I2C            (0x01)
+#define MCF_GPIO_DSCR_FECI2C_DSCR_FEC            (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_DSCR_UART */
+#define MCF_GPIO_DSCR_UART_DSCR_UART0            (0x01)
+#define MCF_GPIO_DSCR_UART_DSCR_UART1            (0x04)
+#define MCF_GPIO_DSCR_UART_DSCR_UART2            (0x10)
+#define MCF_GPIO_DSCR_UART_DSCR_IRQ              (0x40)
+
+/* Bit definitions and macros for MCF_GPIO_DSCR_QSPI */
+#define MCF_GPIO_DSCR_QSPI_DSCR_QSPI             (0x01)
+
+/* Bit definitions and macros for MCF_GPIO_DSCR_TIMER */
+#define MCF_GPIO_DSCR_TIMER_DSCR_TIMER           (0x01)
+
+/********************************************************************/
+
+#endif /* __MCF523X_GPIO_H__ */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_i2c.h b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_i2c.h
new file mode 100644
index 000000000..3bb780b82
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_i2c.h
@@ -0,0 +1,63 @@
+/*
+ * These files are taken from the MCF523X source code example package
+ * which is available on the Freescale website. Freescale explicitly 
+ * grants the redistribution and modification of these source files.
+ * The complete licensing information is available in the file 
+ * LICENSE_FREESCALE.TXT.
+ *
+ * File:	mcf523x_i2c.h
+ * Purpose:	Register and bit definitions for the MCF523X
+ *
+ * Notes:	
+ *	
+ */
+
+#ifndef __MCF523X_I2C_H__
+#define __MCF523X_I2C_H__
+
+/*********************************************************************
+*
+* I2C Module (I2C)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_I2C_I2AR     (*(vuint8 *)(void*)(&__IPSBAR[0x000300]))
+#define MCF_I2C_I2FDR    (*(vuint8 *)(void*)(&__IPSBAR[0x000304]))
+#define MCF_I2C_I2CR     (*(vuint8 *)(void*)(&__IPSBAR[0x000308]))
+#define MCF_I2C_I2SR     (*(vuint8 *)(void*)(&__IPSBAR[0x00030C]))
+#define MCF_I2C_I2DR     (*(vuint8 *)(void*)(&__IPSBAR[0x000310]))
+#define MCF_I2C_I2ICR    (*(vuint8 *)(void*)(&__IPSBAR[0x000320]))
+
+/* Bit definitions and macros for MCF_I2C_I2AR */
+#define MCF_I2C_I2AR_ADR(x)    (((x)&0x7F)<<1)
+
+/* Bit definitions and macros for MCF_I2C_I2FDR */
+#define MCF_I2C_I2FDR_IC(x)    (((x)&0x3F)<<0)
+
+/* Bit definitions and macros for MCF_I2C_I2CR */
+#define MCF_I2C_I2CR_RSTA      (0x04)
+#define MCF_I2C_I2CR_TXAK      (0x08)
+#define MCF_I2C_I2CR_MTX       (0x10)
+#define MCF_I2C_I2CR_MSTA      (0x20)
+#define MCF_I2C_I2CR_IIEN      (0x40)
+#define MCF_I2C_I2CR_IEN       (0x80)
+
+/* Bit definitions and macros for MCF_I2C_I2SR */
+#define MCF_I2C_I2SR_RXAK      (0x01)
+#define MCF_I2C_I2SR_IIF       (0x02)
+#define MCF_I2C_I2SR_SRW       (0x04)
+#define MCF_I2C_I2SR_IAL       (0x10)
+#define MCF_I2C_I2SR_IBB       (0x20)
+#define MCF_I2C_I2SR_IAAS      (0x40)
+#define MCF_I2C_I2SR_ICF       (0x80)
+
+/* Bit definitions and macros for MCF_I2C_I2ICR */
+#define MCF_I2C_I2ICR_IE       (0x01)
+#define MCF_I2C_I2ICR_RE       (0x02)
+#define MCF_I2C_I2ICR_TE       (0x04)
+#define MCF_I2C_I2ICR_BNBE     (0x08)
+
+/********************************************************************/
+
+#endif /* __MCF523X_I2C_H__ */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_intc0.h b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_intc0.h
new file mode 100644
index 000000000..2e06524f4
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_intc0.h
@@ -0,0 +1,323 @@
+/*
+ * These files are taken from the MCF523X source code example package
+ * which is available on the Freescale website. Freescale explicitly 
+ * grants the redistribution and modification of these source files.
+ * The complete licensing information is available in the file 
+ * LICENSE_FREESCALE.TXT.
+ *
+ * File:	mcf523x_intc0.h
+ * Purpose:	Register and bit definitions for the MCF523X
+ *
+ * Notes:	
+ *	
+ */
+
+#ifndef __MCF523X_INTC0_H__
+#define __MCF523X_INTC0_H__
+
+/*********************************************************************
+*
+* Interrupt Controller 0 (INTC0)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_INTC0_IPRH         (*(vuint32*)(void*)(&__IPSBAR[0x000C00]))
+#define MCF_INTC0_IPRL         (*(vuint32*)(void*)(&__IPSBAR[0x000C04]))
+#define MCF_INTC0_IMRH         (*(vuint32*)(void*)(&__IPSBAR[0x000C08]))
+#define MCF_INTC0_IMRL         (*(vuint32*)(void*)(&__IPSBAR[0x000C0C]))
+#define MCF_INTC0_INTFRCH      (*(vuint32*)(void*)(&__IPSBAR[0x000C10]))
+#define MCF_INTC0_INTFRCL      (*(vuint32*)(void*)(&__IPSBAR[0x000C14]))
+#define MCF_INTC0_IRLR         (*(vuint8 *)(void*)(&__IPSBAR[0x000C18]))
+#define MCF_INTC0_IACKLPR      (*(vuint8 *)(void*)(&__IPSBAR[0x000C19]))
+#define MCF_INTC0_ICR0         (*(vuint8 *)(void*)(&__IPSBAR[0x000C40]))
+#define MCF_INTC0_ICR1         (*(vuint8 *)(void*)(&__IPSBAR[0x000C41]))
+#define MCF_INTC0_ICR2         (*(vuint8 *)(void*)(&__IPSBAR[0x000C42]))
+#define MCF_INTC0_ICR3         (*(vuint8 *)(void*)(&__IPSBAR[0x000C43]))
+#define MCF_INTC0_ICR4         (*(vuint8 *)(void*)(&__IPSBAR[0x000C44]))
+#define MCF_INTC0_ICR5         (*(vuint8 *)(void*)(&__IPSBAR[0x000C45]))
+#define MCF_INTC0_ICR6         (*(vuint8 *)(void*)(&__IPSBAR[0x000C46]))
+#define MCF_INTC0_ICR7         (*(vuint8 *)(void*)(&__IPSBAR[0x000C47]))
+#define MCF_INTC0_ICR8         (*(vuint8 *)(void*)(&__IPSBAR[0x000C48]))
+#define MCF_INTC0_ICR9         (*(vuint8 *)(void*)(&__IPSBAR[0x000C49]))
+#define MCF_INTC0_ICR10        (*(vuint8 *)(void*)(&__IPSBAR[0x000C4A]))
+#define MCF_INTC0_ICR11        (*(vuint8 *)(void*)(&__IPSBAR[0x000C4B]))
+#define MCF_INTC0_ICR12        (*(vuint8 *)(void*)(&__IPSBAR[0x000C4C]))
+#define MCF_INTC0_ICR13        (*(vuint8 *)(void*)(&__IPSBAR[0x000C4D]))
+#define MCF_INTC0_ICR14        (*(vuint8 *)(void*)(&__IPSBAR[0x000C4E]))
+#define MCF_INTC0_ICR15        (*(vuint8 *)(void*)(&__IPSBAR[0x000C4F]))
+#define MCF_INTC0_ICR16        (*(vuint8 *)(void*)(&__IPSBAR[0x000C50]))
+#define MCF_INTC0_ICR17        (*(vuint8 *)(void*)(&__IPSBAR[0x000C51]))
+#define MCF_INTC0_ICR18        (*(vuint8 *)(void*)(&__IPSBAR[0x000C52]))
+#define MCF_INTC0_ICR19        (*(vuint8 *)(void*)(&__IPSBAR[0x000C53]))
+#define MCF_INTC0_ICR20        (*(vuint8 *)(void*)(&__IPSBAR[0x000C54]))
+#define MCF_INTC0_ICR21        (*(vuint8 *)(void*)(&__IPSBAR[0x000C55]))
+#define MCF_INTC0_ICR22        (*(vuint8 *)(void*)(&__IPSBAR[0x000C56]))
+#define MCF_INTC0_ICR23        (*(vuint8 *)(void*)(&__IPSBAR[0x000C57]))
+#define MCF_INTC0_ICR24        (*(vuint8 *)(void*)(&__IPSBAR[0x000C58]))
+#define MCF_INTC0_ICR25        (*(vuint8 *)(void*)(&__IPSBAR[0x000C59]))
+#define MCF_INTC0_ICR26        (*(vuint8 *)(void*)(&__IPSBAR[0x000C5A]))
+#define MCF_INTC0_ICR27        (*(vuint8 *)(void*)(&__IPSBAR[0x000C5B]))
+#define MCF_INTC0_ICR28        (*(vuint8 *)(void*)(&__IPSBAR[0x000C5C]))
+#define MCF_INTC0_ICR29        (*(vuint8 *)(void*)(&__IPSBAR[0x000C5D]))
+#define MCF_INTC0_ICR30        (*(vuint8 *)(void*)(&__IPSBAR[0x000C5E]))
+#define MCF_INTC0_ICR31        (*(vuint8 *)(void*)(&__IPSBAR[0x000C5F]))
+#define MCF_INTC0_ICR32        (*(vuint8 *)(void*)(&__IPSBAR[0x000C60]))
+#define MCF_INTC0_ICR33        (*(vuint8 *)(void*)(&__IPSBAR[0x000C61]))
+#define MCF_INTC0_ICR34        (*(vuint8 *)(void*)(&__IPSBAR[0x000C62]))
+#define MCF_INTC0_ICR35        (*(vuint8 *)(void*)(&__IPSBAR[0x000C63]))
+#define MCF_INTC0_ICR36        (*(vuint8 *)(void*)(&__IPSBAR[0x000C64]))
+#define MCF_INTC0_ICR37        (*(vuint8 *)(void*)(&__IPSBAR[0x000C65]))
+#define MCF_INTC0_ICR38        (*(vuint8 *)(void*)(&__IPSBAR[0x000C66]))
+#define MCF_INTC0_ICR39        (*(vuint8 *)(void*)(&__IPSBAR[0x000C67]))
+#define MCF_INTC0_ICR40        (*(vuint8 *)(void*)(&__IPSBAR[0x000C68]))
+#define MCF_INTC0_ICR41        (*(vuint8 *)(void*)(&__IPSBAR[0x000C69]))
+#define MCF_INTC0_ICR42        (*(vuint8 *)(void*)(&__IPSBAR[0x000C6A]))
+#define MCF_INTC0_ICR43        (*(vuint8 *)(void*)(&__IPSBAR[0x000C6B]))
+#define MCF_INTC0_ICR44        (*(vuint8 *)(void*)(&__IPSBAR[0x000C6C]))
+#define MCF_INTC0_ICR45        (*(vuint8 *)(void*)(&__IPSBAR[0x000C6D]))
+#define MCF_INTC0_ICR46        (*(vuint8 *)(void*)(&__IPSBAR[0x000C6E]))
+#define MCF_INTC0_ICR47        (*(vuint8 *)(void*)(&__IPSBAR[0x000C6F]))
+#define MCF_INTC0_ICR48        (*(vuint8 *)(void*)(&__IPSBAR[0x000C70]))
+#define MCF_INTC0_ICR49        (*(vuint8 *)(void*)(&__IPSBAR[0x000C71]))
+#define MCF_INTC0_ICR50        (*(vuint8 *)(void*)(&__IPSBAR[0x000C72]))
+#define MCF_INTC0_ICR51        (*(vuint8 *)(void*)(&__IPSBAR[0x000C73]))
+#define MCF_INTC0_ICR52        (*(vuint8 *)(void*)(&__IPSBAR[0x000C74]))
+#define MCF_INTC0_ICR53        (*(vuint8 *)(void*)(&__IPSBAR[0x000C75]))
+#define MCF_INTC0_ICR54        (*(vuint8 *)(void*)(&__IPSBAR[0x000C76]))
+#define MCF_INTC0_ICR55        (*(vuint8 *)(void*)(&__IPSBAR[0x000C77]))
+#define MCF_INTC0_ICR56        (*(vuint8 *)(void*)(&__IPSBAR[0x000C78]))
+#define MCF_INTC0_ICR57        (*(vuint8 *)(void*)(&__IPSBAR[0x000C79]))
+#define MCF_INTC0_ICR58        (*(vuint8 *)(void*)(&__IPSBAR[0x000C7A]))
+#define MCF_INTC0_ICR59        (*(vuint8 *)(void*)(&__IPSBAR[0x000C7B]))
+#define MCF_INTC0_ICR60        (*(vuint8 *)(void*)(&__IPSBAR[0x000C7C]))
+#define MCF_INTC0_ICR61        (*(vuint8 *)(void*)(&__IPSBAR[0x000C7D]))
+#define MCF_INTC0_ICR62        (*(vuint8 *)(void*)(&__IPSBAR[0x000C7E]))
+#define MCF_INTC0_ICR63        (*(vuint8 *)(void*)(&__IPSBAR[0x000C7F]))
+#define MCF_INTC0_ICRn(x)      (*(vuint8 *)(void*)(&__IPSBAR[0x000C40+((x)*0x001)]))
+#define MCF_INTC0_SWIACK       (*(vuint8 *)(void*)(&__IPSBAR[0x000CE0]))
+#define MCF_INTC0_L1IACK       (*(vuint8 *)(void*)(&__IPSBAR[0x000CE4]))
+#define MCF_INTC0_L2IACK       (*(vuint8 *)(void*)(&__IPSBAR[0x000CE8]))
+#define MCF_INTC0_L3IACK       (*(vuint8 *)(void*)(&__IPSBAR[0x000CEC]))
+#define MCF_INTC0_L4IACK       (*(vuint8 *)(void*)(&__IPSBAR[0x000CF0]))
+#define MCF_INTC0_L5IACK       (*(vuint8 *)(void*)(&__IPSBAR[0x000CF4]))
+#define MCF_INTC0_L6IACK       (*(vuint8 *)(void*)(&__IPSBAR[0x000CF8]))
+#define MCF_INTC0_L7IACK       (*(vuint8 *)(void*)(&__IPSBAR[0x000CFC]))
+#define MCF_INTC0_LnIACK(x)    (*(vuint8 *)(void*)(&__IPSBAR[0x000CE4+((x)*0x004)]))
+
+/* Bit definitions and macros for MCF_INTC0_IPRH */
+#define MCF_INTC0_IPRH_INT32          (0x00000001)
+#define MCF_INTC0_IPRH_INT33          (0x00000002)
+#define MCF_INTC0_IPRH_INT34          (0x00000004)
+#define MCF_INTC0_IPRH_INT35          (0x00000008)
+#define MCF_INTC0_IPRH_INT36          (0x00000010)
+#define MCF_INTC0_IPRH_INT37          (0x00000020)
+#define MCF_INTC0_IPRH_INT38          (0x00000040)
+#define MCF_INTC0_IPRH_INT39          (0x00000080)
+#define MCF_INTC0_IPRH_INT40          (0x00000100)
+#define MCF_INTC0_IPRH_INT41          (0x00000200)
+#define MCF_INTC0_IPRH_INT42          (0x00000400)
+#define MCF_INTC0_IPRH_INT43          (0x00000800)
+#define MCF_INTC0_IPRH_INT44          (0x00001000)
+#define MCF_INTC0_IPRH_INT45          (0x00002000)
+#define MCF_INTC0_IPRH_INT46          (0x00004000)
+#define MCF_INTC0_IPRH_INT47          (0x00008000)
+#define MCF_INTC0_IPRH_INT48          (0x00010000)
+#define MCF_INTC0_IPRH_INT49          (0x00020000)
+#define MCF_INTC0_IPRH_INT50          (0x00040000)
+#define MCF_INTC0_IPRH_INT51          (0x00080000)
+#define MCF_INTC0_IPRH_INT52          (0x00100000)
+#define MCF_INTC0_IPRH_INT53          (0x00200000)
+#define MCF_INTC0_IPRH_INT54          (0x00400000)
+#define MCF_INTC0_IPRH_INT55          (0x00800000)
+#define MCF_INTC0_IPRH_INT56          (0x01000000)
+#define MCF_INTC0_IPRH_INT57          (0x02000000)
+#define MCF_INTC0_IPRH_INT58          (0x04000000)
+#define MCF_INTC0_IPRH_INT59          (0x08000000)
+#define MCF_INTC0_IPRH_INT60          (0x10000000)
+#define MCF_INTC0_IPRH_INT61          (0x20000000)
+#define MCF_INTC0_IPRH_INT62          (0x40000000)
+#define MCF_INTC0_IPRH_INT63          (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC0_IPRL */
+#define MCF_INTC0_IPRL_INT1           (0x00000002)
+#define MCF_INTC0_IPRL_INT2           (0x00000004)
+#define MCF_INTC0_IPRL_INT3           (0x00000008)
+#define MCF_INTC0_IPRL_INT4           (0x00000010)
+#define MCF_INTC0_IPRL_INT5           (0x00000020)
+#define MCF_INTC0_IPRL_INT6           (0x00000040)
+#define MCF_INTC0_IPRL_INT7           (0x00000080)
+#define MCF_INTC0_IPRL_INT8           (0x00000100)
+#define MCF_INTC0_IPRL_INT9           (0x00000200)
+#define MCF_INTC0_IPRL_INT10          (0x00000400)
+#define MCF_INTC0_IPRL_INT11          (0x00000800)
+#define MCF_INTC0_IPRL_INT12          (0x00001000)
+#define MCF_INTC0_IPRL_INT13          (0x00002000)
+#define MCF_INTC0_IPRL_INT14          (0x00004000)
+#define MCF_INTC0_IPRL_INT15          (0x00008000)
+#define MCF_INTC0_IPRL_INT16          (0x00010000)
+#define MCF_INTC0_IPRL_INT17          (0x00020000)
+#define MCF_INTC0_IPRL_INT18          (0x00040000)
+#define MCF_INTC0_IPRL_INT19          (0x00080000)
+#define MCF_INTC0_IPRL_INT20          (0x00100000)
+#define MCF_INTC0_IPRL_INT21          (0x00200000)
+#define MCF_INTC0_IPRL_INT22          (0x00400000)
+#define MCF_INTC0_IPRL_INT23          (0x00800000)
+#define MCF_INTC0_IPRL_INT24          (0x01000000)
+#define MCF_INTC0_IPRL_INT25          (0x02000000)
+#define MCF_INTC0_IPRL_INT26          (0x04000000)
+#define MCF_INTC0_IPRL_INT27          (0x08000000)
+#define MCF_INTC0_IPRL_INT28          (0x10000000)
+#define MCF_INTC0_IPRL_INT29          (0x20000000)
+#define MCF_INTC0_IPRL_INT30          (0x40000000)
+#define MCF_INTC0_IPRL_INT31          (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC0_IMRH */
+#define MCF_INTC0_IMRH_INT_MASK32     (0x00000001)
+#define MCF_INTC0_IMRH_INT_MASK33     (0x00000002)
+#define MCF_INTC0_IMRH_INT_MASK34     (0x00000004)
+#define MCF_INTC0_IMRH_INT_MASK35     (0x00000008)
+#define MCF_INTC0_IMRH_INT_MASK36     (0x00000010)
+#define MCF_INTC0_IMRH_INT_MASK37     (0x00000020)
+#define MCF_INTC0_IMRH_INT_MASK38     (0x00000040)
+#define MCF_INTC0_IMRH_INT_MASK39     (0x00000080)
+#define MCF_INTC0_IMRH_INT_MASK40     (0x00000100)
+#define MCF_INTC0_IMRH_INT_MASK41     (0x00000200)
+#define MCF_INTC0_IMRH_INT_MASK42     (0x00000400)
+#define MCF_INTC0_IMRH_INT_MASK43     (0x00000800)
+#define MCF_INTC0_IMRH_INT_MASK44     (0x00001000)
+#define MCF_INTC0_IMRH_INT_MASK45     (0x00002000)
+#define MCF_INTC0_IMRH_INT_MASK46     (0x00004000)
+#define MCF_INTC0_IMRH_INT_MASK47     (0x00008000)
+#define MCF_INTC0_IMRH_INT_MASK48     (0x00010000)
+#define MCF_INTC0_IMRH_INT_MASK49     (0x00020000)
+#define MCF_INTC0_IMRH_INT_MASK50     (0x00040000)
+#define MCF_INTC0_IMRH_INT_MASK51     (0x00080000)
+#define MCF_INTC0_IMRH_INT_MASK52     (0x00100000)
+#define MCF_INTC0_IMRH_INT_MASK53     (0x00200000)
+#define MCF_INTC0_IMRH_INT_MASK54     (0x00400000)
+#define MCF_INTC0_IMRH_INT_MASK55     (0x00800000)
+#define MCF_INTC0_IMRH_INT_MASK56     (0x01000000)
+#define MCF_INTC0_IMRH_INT_MASK57     (0x02000000)
+#define MCF_INTC0_IMRH_INT_MASK58     (0x04000000)
+#define MCF_INTC0_IMRH_INT_MASK59     (0x08000000)
+#define MCF_INTC0_IMRH_INT_MASK60     (0x10000000)
+#define MCF_INTC0_IMRH_INT_MASK61     (0x20000000)
+#define MCF_INTC0_IMRH_INT_MASK62     (0x40000000)
+#define MCF_INTC0_IMRH_INT_MASK63     (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC0_IMRL */
+#define MCF_INTC0_IMRL_MASKALL        (0x00000001)
+#define MCF_INTC0_IMRL_INT_MASK1      (0x00000002)
+#define MCF_INTC0_IMRL_INT_MASK2      (0x00000004)
+#define MCF_INTC0_IMRL_INT_MASK3      (0x00000008)
+#define MCF_INTC0_IMRL_INT_MASK4      (0x00000010)
+#define MCF_INTC0_IMRL_INT_MASK5      (0x00000020)
+#define MCF_INTC0_IMRL_INT_MASK6      (0x00000040)
+#define MCF_INTC0_IMRL_INT_MASK7      (0x00000080)
+#define MCF_INTC0_IMRL_INT_MASK8      (0x00000100)
+#define MCF_INTC0_IMRL_INT_MASK9      (0x00000200)
+#define MCF_INTC0_IMRL_INT_MASK10     (0x00000400)
+#define MCF_INTC0_IMRL_INT_MASK11     (0x00000800)
+#define MCF_INTC0_IMRL_INT_MASK12     (0x00001000)
+#define MCF_INTC0_IMRL_INT_MASK13     (0x00002000)
+#define MCF_INTC0_IMRL_INT_MASK14     (0x00004000)
+#define MCF_INTC0_IMRL_INT_MASK15     (0x00008000)
+#define MCF_INTC0_IMRL_INT_MASK16     (0x00010000)
+#define MCF_INTC0_IMRL_INT_MASK17     (0x00020000)
+#define MCF_INTC0_IMRL_INT_MASK18     (0x00040000)
+#define MCF_INTC0_IMRL_INT_MASK19     (0x00080000)
+#define MCF_INTC0_IMRL_INT_MASK20     (0x00100000)
+#define MCF_INTC0_IMRL_INT_MASK21     (0x00200000)
+#define MCF_INTC0_IMRL_INT_MASK22     (0x00400000)
+#define MCF_INTC0_IMRL_INT_MASK23     (0x00800000)
+#define MCF_INTC0_IMRL_INT_MASK24     (0x01000000)
+#define MCF_INTC0_IMRL_INT_MASK25     (0x02000000)
+#define MCF_INTC0_IMRL_INT_MASK26     (0x04000000)
+#define MCF_INTC0_IMRL_INT_MASK27     (0x08000000)
+#define MCF_INTC0_IMRL_INT_MASK28     (0x10000000)
+#define MCF_INTC0_IMRL_INT_MASK29     (0x20000000)
+#define MCF_INTC0_IMRL_INT_MASK30     (0x40000000)
+#define MCF_INTC0_IMRL_INT_MASK31     (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC0_INTFRCH */
+#define MCF_INTC0_INTFRCH_INTFRC32    (0x00000001)
+#define MCF_INTC0_INTFRCH_INTFRC33    (0x00000002)
+#define MCF_INTC0_INTFRCH_INTFRC34    (0x00000004)
+#define MCF_INTC0_INTFRCH_INTFRC35    (0x00000008)
+#define MCF_INTC0_INTFRCH_INTFRC36    (0x00000010)
+#define MCF_INTC0_INTFRCH_INTFRC37    (0x00000020)
+#define MCF_INTC0_INTFRCH_INTFRC38    (0x00000040)
+#define MCF_INTC0_INTFRCH_INTFRC39    (0x00000080)
+#define MCF_INTC0_INTFRCH_INTFRC40    (0x00000100)
+#define MCF_INTC0_INTFRCH_INTFRC41    (0x00000200)
+#define MCF_INTC0_INTFRCH_INTFRC42    (0x00000400)
+#define MCF_INTC0_INTFRCH_INTFRC43    (0x00000800)
+#define MCF_INTC0_INTFRCH_INTFRC44    (0x00001000)
+#define MCF_INTC0_INTFRCH_INTFRC45    (0x00002000)
+#define MCF_INTC0_INTFRCH_INTFRC46    (0x00004000)
+#define MCF_INTC0_INTFRCH_INTFRC47    (0x00008000)
+#define MCF_INTC0_INTFRCH_INTFRC48    (0x00010000)
+#define MCF_INTC0_INTFRCH_INTFRC49    (0x00020000)
+#define MCF_INTC0_INTFRCH_INTFRC50    (0x00040000)
+#define MCF_INTC0_INTFRCH_INTFRC51    (0x00080000)
+#define MCF_INTC0_INTFRCH_INTFRC52    (0x00100000)
+#define MCF_INTC0_INTFRCH_INTFRC53    (0x00200000)
+#define MCF_INTC0_INTFRCH_INTFRC54    (0x00400000)
+#define MCF_INTC0_INTFRCH_INTFRC55    (0x00800000)
+#define MCF_INTC0_INTFRCH_INTFRC56    (0x01000000)
+#define MCF_INTC0_INTFRCH_INTFRC57    (0x02000000)
+#define MCF_INTC0_INTFRCH_INTFRC58    (0x04000000)
+#define MCF_INTC0_INTFRCH_INTFRC59    (0x08000000)
+#define MCF_INTC0_INTFRCH_INTFRC60    (0x10000000)
+#define MCF_INTC0_INTFRCH_INTFRC61    (0x20000000)
+#define MCF_INTC0_INTFRCH_INTFRC62    (0x40000000)
+#define MCF_INTC0_INTFRCH_INTFRC63    (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC0_INTFRCL */
+#define MCF_INTC0_INTFRCL_INTFRC1     (0x00000002)
+#define MCF_INTC0_INTFRCL_INTFRC2     (0x00000004)
+#define MCF_INTC0_INTFRCL_INTFRC3     (0x00000008)
+#define MCF_INTC0_INTFRCL_INTFRC4     (0x00000010)
+#define MCF_INTC0_INTFRCL_INTFRC5     (0x00000020)
+#define MCF_INTC0_INTFRCL_INT6        (0x00000040)
+#define MCF_INTC0_INTFRCL_INT7        (0x00000080)
+#define MCF_INTC0_INTFRCL_INT8        (0x00000100)
+#define MCF_INTC0_INTFRCL_INT9        (0x00000200)
+#define MCF_INTC0_INTFRCL_INT10       (0x00000400)
+#define MCF_INTC0_INTFRCL_INTFRC11    (0x00000800)
+#define MCF_INTC0_INTFRCL_INTFRC12    (0x00001000)
+#define MCF_INTC0_INTFRCL_INTFRC13    (0x00002000)
+#define MCF_INTC0_INTFRCL_INTFRC14    (0x00004000)
+#define MCF_INTC0_INTFRCL_INT15       (0x00008000)
+#define MCF_INTC0_INTFRCL_INTFRC16    (0x00010000)
+#define MCF_INTC0_INTFRCL_INTFRC17    (0x00020000)
+#define MCF_INTC0_INTFRCL_INTFRC18    (0x00040000)
+#define MCF_INTC0_INTFRCL_INTFRC19    (0x00080000)
+#define MCF_INTC0_INTFRCL_INTFRC20    (0x00100000)
+#define MCF_INTC0_INTFRCL_INTFRC21    (0x00200000)
+#define MCF_INTC0_INTFRCL_INTFRC22    (0x00400000)
+#define MCF_INTC0_INTFRCL_INTFRC23    (0x00800000)
+#define MCF_INTC0_INTFRCL_INTFRC24    (0x01000000)
+#define MCF_INTC0_INTFRCL_INTFRC25    (0x02000000)
+#define MCF_INTC0_INTFRCL_INTFRC26    (0x04000000)
+#define MCF_INTC0_INTFRCL_INTFRC27    (0x08000000)
+#define MCF_INTC0_INTFRCL_INTFRC28    (0x10000000)
+#define MCF_INTC0_INTFRCL_INTFRC29    (0x20000000)
+#define MCF_INTC0_INTFRCL_INTFRC30    (0x40000000)
+#define MCF_INTC0_INTFRCL_INTFRC31    (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC0_IRLR */
+#define MCF_INTC0_IRLR_IRQ(x)         (((x)&0x7F)<<1)
+
+/* Bit definitions and macros for MCF_INTC0_IACKLPR */
+#define MCF_INTC0_IACKLPR_PRI(x)      (((x)&0x0F)<<0)
+#define MCF_INTC0_IACKLPR_LEVEL(x)    (((x)&0x07)<<4)
+
+/* Bit definitions and macros for MCF_INTC0_ICRn */
+#define MCF_INTC0_ICRn_IP(x)          (((x)&0x07)<<0)
+#define MCF_INTC0_ICRn_IL(x)          (((x)&0x07)<<3)
+
+/********************************************************************/
+
+#endif /* __MCF523X_INTC0_H__ */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_intc1.h b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_intc1.h
new file mode 100644
index 000000000..7e8972c07
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_intc1.h
@@ -0,0 +1,323 @@
+/*
+ * These files are taken from the MCF523X source code example package
+ * which is available on the Freescale website. Freescale explicitly 
+ * grants the redistribution and modification of these source files.
+ * The complete licensing information is available in the file 
+ * LICENSE_FREESCALE.TXT.
+ *
+ * File:	mcf523x_intc1.h
+ * Purpose:	Register and bit definitions for the MCF523X
+ *
+ * Notes:	
+ *	
+ */
+
+#ifndef __MCF523X_INTC1_H__
+#define __MCF523X_INTC1_H__
+
+/*********************************************************************
+*
+* Interrupt Controller 1 (INTC1)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_INTC1_IPRH         (*(vuint32*)(void*)(&__IPSBAR[0x000D00]))
+#define MCF_INTC1_IPRL         (*(vuint32*)(void*)(&__IPSBAR[0x000D04]))
+#define MCF_INTC1_IMRH         (*(vuint32*)(void*)(&__IPSBAR[0x000D08]))
+#define MCF_INTC1_IMRL         (*(vuint32*)(void*)(&__IPSBAR[0x000D0C]))
+#define MCF_INTC1_INTFRCH      (*(vuint32*)(void*)(&__IPSBAR[0x000D10]))
+#define MCF_INTC1_INTFRCL      (*(vuint32*)(void*)(&__IPSBAR[0x000D14]))
+#define MCF_INTC1_IRLR         (*(vuint8 *)(void*)(&__IPSBAR[0x000D18]))
+#define MCF_INTC1_IACKLPR      (*(vuint8 *)(void*)(&__IPSBAR[0x000D19]))
+#define MCF_INTC1_ICR0         (*(vuint8 *)(void*)(&__IPSBAR[0x000D40]))
+#define MCF_INTC1_ICR1         (*(vuint8 *)(void*)(&__IPSBAR[0x000D41]))
+#define MCF_INTC1_ICR2         (*(vuint8 *)(void*)(&__IPSBAR[0x000D42]))
+#define MCF_INTC1_ICR3         (*(vuint8 *)(void*)(&__IPSBAR[0x000D43]))
+#define MCF_INTC1_ICR4         (*(vuint8 *)(void*)(&__IPSBAR[0x000D44]))
+#define MCF_INTC1_ICR5         (*(vuint8 *)(void*)(&__IPSBAR[0x000D45]))
+#define MCF_INTC1_ICR6         (*(vuint8 *)(void*)(&__IPSBAR[0x000D46]))
+#define MCF_INTC1_ICR7         (*(vuint8 *)(void*)(&__IPSBAR[0x000D47]))
+#define MCF_INTC1_ICR8         (*(vuint8 *)(void*)(&__IPSBAR[0x000D48]))
+#define MCF_INTC1_ICR9         (*(vuint8 *)(void*)(&__IPSBAR[0x000D49]))
+#define MCF_INTC1_ICR10        (*(vuint8 *)(void*)(&__IPSBAR[0x000D4A]))
+#define MCF_INTC1_ICR11        (*(vuint8 *)(void*)(&__IPSBAR[0x000D4B]))
+#define MCF_INTC1_ICR12        (*(vuint8 *)(void*)(&__IPSBAR[0x000D4C]))
+#define MCF_INTC1_ICR13        (*(vuint8 *)(void*)(&__IPSBAR[0x000D4D]))
+#define MCF_INTC1_ICR14        (*(vuint8 *)(void*)(&__IPSBAR[0x000D4E]))
+#define MCF_INTC1_ICR15        (*(vuint8 *)(void*)(&__IPSBAR[0x000D4F]))
+#define MCF_INTC1_ICR16        (*(vuint8 *)(void*)(&__IPSBAR[0x000D50]))
+#define MCF_INTC1_ICR17        (*(vuint8 *)(void*)(&__IPSBAR[0x000D51]))
+#define MCF_INTC1_ICR18        (*(vuint8 *)(void*)(&__IPSBAR[0x000D52]))
+#define MCF_INTC1_ICR19        (*(vuint8 *)(void*)(&__IPSBAR[0x000D53]))
+#define MCF_INTC1_ICR20        (*(vuint8 *)(void*)(&__IPSBAR[0x000D54]))
+#define MCF_INTC1_ICR21        (*(vuint8 *)(void*)(&__IPSBAR[0x000D55]))
+#define MCF_INTC1_ICR22        (*(vuint8 *)(void*)(&__IPSBAR[0x000D56]))
+#define MCF_INTC1_ICR23        (*(vuint8 *)(void*)(&__IPSBAR[0x000D57]))
+#define MCF_INTC1_ICR24        (*(vuint8 *)(void*)(&__IPSBAR[0x000D58]))
+#define MCF_INTC1_ICR25        (*(vuint8 *)(void*)(&__IPSBAR[0x000D59]))
+#define MCF_INTC1_ICR26        (*(vuint8 *)(void*)(&__IPSBAR[0x000D5A]))
+#define MCF_INTC1_ICR27        (*(vuint8 *)(void*)(&__IPSBAR[0x000D5B]))
+#define MCF_INTC1_ICR28        (*(vuint8 *)(void*)(&__IPSBAR[0x000D5C]))
+#define MCF_INTC1_ICR29        (*(vuint8 *)(void*)(&__IPSBAR[0x000D5D]))
+#define MCF_INTC1_ICR30        (*(vuint8 *)(void*)(&__IPSBAR[0x000D5E]))
+#define MCF_INTC1_ICR31        (*(vuint8 *)(void*)(&__IPSBAR[0x000D5F]))
+#define MCF_INTC1_ICR32        (*(vuint8 *)(void*)(&__IPSBAR[0x000D60]))
+#define MCF_INTC1_ICR33        (*(vuint8 *)(void*)(&__IPSBAR[0x000D61]))
+#define MCF_INTC1_ICR34        (*(vuint8 *)(void*)(&__IPSBAR[0x000D62]))
+#define MCF_INTC1_ICR35        (*(vuint8 *)(void*)(&__IPSBAR[0x000D63]))
+#define MCF_INTC1_ICR36        (*(vuint8 *)(void*)(&__IPSBAR[0x000D64]))
+#define MCF_INTC1_ICR37        (*(vuint8 *)(void*)(&__IPSBAR[0x000D65]))
+#define MCF_INTC1_ICR38        (*(vuint8 *)(void*)(&__IPSBAR[0x000D66]))
+#define MCF_INTC1_ICR39        (*(vuint8 *)(void*)(&__IPSBAR[0x000D67]))
+#define MCF_INTC1_ICR40        (*(vuint8 *)(void*)(&__IPSBAR[0x000D68]))
+#define MCF_INTC1_ICR41        (*(vuint8 *)(void*)(&__IPSBAR[0x000D69]))
+#define MCF_INTC1_ICR42        (*(vuint8 *)(void*)(&__IPSBAR[0x000D6A]))
+#define MCF_INTC1_ICR43        (*(vuint8 *)(void*)(&__IPSBAR[0x000D6B]))
+#define MCF_INTC1_ICR44        (*(vuint8 *)(void*)(&__IPSBAR[0x000D6C]))
+#define MCF_INTC1_ICR45        (*(vuint8 *)(void*)(&__IPSBAR[0x000D6D]))
+#define MCF_INTC1_ICR46        (*(vuint8 *)(void*)(&__IPSBAR[0x000D6E]))
+#define MCF_INTC1_ICR47        (*(vuint8 *)(void*)(&__IPSBAR[0x000D6F]))
+#define MCF_INTC1_ICR48        (*(vuint8 *)(void*)(&__IPSBAR[0x000D70]))
+#define MCF_INTC1_ICR49        (*(vuint8 *)(void*)(&__IPSBAR[0x000D71]))
+#define MCF_INTC1_ICR50        (*(vuint8 *)(void*)(&__IPSBAR[0x000D72]))
+#define MCF_INTC1_ICR51        (*(vuint8 *)(void*)(&__IPSBAR[0x000D73]))
+#define MCF_INTC1_ICR52        (*(vuint8 *)(void*)(&__IPSBAR[0x000D74]))
+#define MCF_INTC1_ICR53        (*(vuint8 *)(void*)(&__IPSBAR[0x000D75]))
+#define MCF_INTC1_ICR54        (*(vuint8 *)(void*)(&__IPSBAR[0x000D76]))
+#define MCF_INTC1_ICR55        (*(vuint8 *)(void*)(&__IPSBAR[0x000D77]))
+#define MCF_INTC1_ICR56        (*(vuint8 *)(void*)(&__IPSBAR[0x000D78]))
+#define MCF_INTC1_ICR57        (*(vuint8 *)(void*)(&__IPSBAR[0x000D79]))
+#define MCF_INTC1_ICR58        (*(vuint8 *)(void*)(&__IPSBAR[0x000D7A]))
+#define MCF_INTC1_ICR59        (*(vuint8 *)(void*)(&__IPSBAR[0x000D7B]))
+#define MCF_INTC1_ICR60        (*(vuint8 *)(void*)(&__IPSBAR[0x000D7C]))
+#define MCF_INTC1_ICR61        (*(vuint8 *)(void*)(&__IPSBAR[0x000D7D]))
+#define MCF_INTC1_ICR62        (*(vuint8 *)(void*)(&__IPSBAR[0x000D7E]))
+#define MCF_INTC1_ICR63        (*(vuint8 *)(void*)(&__IPSBAR[0x000D7F]))
+#define MCF_INTC1_ICRn(x)      (*(vuint8 *)(void*)(&__IPSBAR[0x000D40+((x)*0x001)]))
+#define MCF_INTC1_SWIACK       (*(vuint8 *)(void*)(&__IPSBAR[0x000DE0]))
+#define MCF_INTC1_L1IACK       (*(vuint8 *)(void*)(&__IPSBAR[0x000DE4]))
+#define MCF_INTC1_L2IACK       (*(vuint8 *)(void*)(&__IPSBAR[0x000DE8]))
+#define MCF_INTC1_L3IACK       (*(vuint8 *)(void*)(&__IPSBAR[0x000DEC]))
+#define MCF_INTC1_L4IACK       (*(vuint8 *)(void*)(&__IPSBAR[0x000DF0]))
+#define MCF_INTC1_L5IACK       (*(vuint8 *)(void*)(&__IPSBAR[0x000DF4]))
+#define MCF_INTC1_L6IACK       (*(vuint8 *)(void*)(&__IPSBAR[0x000DF8]))
+#define MCF_INTC1_L7IACK       (*(vuint8 *)(void*)(&__IPSBAR[0x000DFC]))
+#define MCF_INTC1_LnIACK(x)    (*(vuint8 *)(void*)(&__IPSBAR[0x000DE4+((x)*0x004)]))
+
+/* Bit definitions and macros for MCF_INTC1_IPRH */
+#define MCF_INTC1_IPRH_INT32          (0x00000001)
+#define MCF_INTC1_IPRH_INT33          (0x00000002)
+#define MCF_INTC1_IPRH_INT34          (0x00000004)
+#define MCF_INTC1_IPRH_INT35          (0x00000008)
+#define MCF_INTC1_IPRH_INT36          (0x00000010)
+#define MCF_INTC1_IPRH_INT37          (0x00000020)
+#define MCF_INTC1_IPRH_INT38          (0x00000040)
+#define MCF_INTC1_IPRH_INT39          (0x00000080)
+#define MCF_INTC1_IPRH_INT40          (0x00000100)
+#define MCF_INTC1_IPRH_INT41          (0x00000200)
+#define MCF_INTC1_IPRH_INT42          (0x00000400)
+#define MCF_INTC1_IPRH_INT43          (0x00000800)
+#define MCF_INTC1_IPRH_INT44          (0x00001000)
+#define MCF_INTC1_IPRH_INT45          (0x00002000)
+#define MCF_INTC1_IPRH_INT46          (0x00004000)
+#define MCF_INTC1_IPRH_INT47          (0x00008000)
+#define MCF_INTC1_IPRH_INT48          (0x00010000)
+#define MCF_INTC1_IPRH_INT49          (0x00020000)
+#define MCF_INTC1_IPRH_INT50          (0x00040000)
+#define MCF_INTC1_IPRH_INT51          (0x00080000)
+#define MCF_INTC1_IPRH_INT52          (0x00100000)
+#define MCF_INTC1_IPRH_INT53          (0x00200000)
+#define MCF_INTC1_IPRH_INT54          (0x00400000)
+#define MCF_INTC1_IPRH_INT55          (0x00800000)
+#define MCF_INTC1_IPRH_INT56          (0x01000000)
+#define MCF_INTC1_IPRH_INT57          (0x02000000)
+#define MCF_INTC1_IPRH_INT58          (0x04000000)
+#define MCF_INTC1_IPRH_INT59          (0x08000000)
+#define MCF_INTC1_IPRH_INT60          (0x10000000)
+#define MCF_INTC1_IPRH_INT61          (0x20000000)
+#define MCF_INTC1_IPRH_INT62          (0x40000000)
+#define MCF_INTC1_IPRH_INT63          (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC1_IPRL */
+#define MCF_INTC1_IPRL_INT1           (0x00000002)
+#define MCF_INTC1_IPRL_INT2           (0x00000004)
+#define MCF_INTC1_IPRL_INT3           (0x00000008)
+#define MCF_INTC1_IPRL_INT4           (0x00000010)
+#define MCF_INTC1_IPRL_INT5           (0x00000020)
+#define MCF_INTC1_IPRL_INT6           (0x00000040)
+#define MCF_INTC1_IPRL_INT7           (0x00000080)
+#define MCF_INTC1_IPRL_INT8           (0x00000100)
+#define MCF_INTC1_IPRL_INT9           (0x00000200)
+#define MCF_INTC1_IPRL_INT10          (0x00000400)
+#define MCF_INTC1_IPRL_INT11          (0x00000800)
+#define MCF_INTC1_IPRL_INT12          (0x00001000)
+#define MCF_INTC1_IPRL_INT13          (0x00002000)
+#define MCF_INTC1_IPRL_INT14          (0x00004000)
+#define MCF_INTC1_IPRL_INT15          (0x00008000)
+#define MCF_INTC1_IPRL_INT16          (0x00010000)
+#define MCF_INTC1_IPRL_INT17          (0x00020000)
+#define MCF_INTC1_IPRL_INT18          (0x00040000)
+#define MCF_INTC1_IPRL_INT19          (0x00080000)
+#define MCF_INTC1_IPRL_INT20          (0x00100000)
+#define MCF_INTC1_IPRL_INT21          (0x00200000)
+#define MCF_INTC1_IPRL_INT22          (0x00400000)
+#define MCF_INTC1_IPRL_INT23          (0x00800000)
+#define MCF_INTC1_IPRL_INT24          (0x01000000)
+#define MCF_INTC1_IPRL_INT25          (0x02000000)
+#define MCF_INTC1_IPRL_INT26          (0x04000000)
+#define MCF_INTC1_IPRL_INT27          (0x08000000)
+#define MCF_INTC1_IPRL_INT28          (0x10000000)
+#define MCF_INTC1_IPRL_INT29          (0x20000000)
+#define MCF_INTC1_IPRL_INT30          (0x40000000)
+#define MCF_INTC1_IPRL_INT31          (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC1_IMRH */
+#define MCF_INTC1_IMRH_INT_MASK32     (0x00000001)
+#define MCF_INTC1_IMRH_INT_MASK33     (0x00000002)
+#define MCF_INTC1_IMRH_INT_MASK34     (0x00000004)
+#define MCF_INTC1_IMRH_INT_MASK35     (0x00000008)
+#define MCF_INTC1_IMRH_INT_MASK36     (0x00000010)
+#define MCF_INTC1_IMRH_INT_MASK37     (0x00000020)
+#define MCF_INTC1_IMRH_INT_MASK38     (0x00000040)
+#define MCF_INTC1_IMRH_INT_MASK39     (0x00000080)
+#define MCF_INTC1_IMRH_INT_MASK40     (0x00000100)
+#define MCF_INTC1_IMRH_INT_MASK41     (0x00000200)
+#define MCF_INTC1_IMRH_INT_MASK42     (0x00000400)
+#define MCF_INTC1_IMRH_INT_MASK43     (0x00000800)
+#define MCF_INTC1_IMRH_INT_MASK44     (0x00001000)
+#define MCF_INTC1_IMRH_INT_MASK45     (0x00002000)
+#define MCF_INTC1_IMRH_INT_MASK46     (0x00004000)
+#define MCF_INTC1_IMRH_INT_MASK47     (0x00008000)
+#define MCF_INTC1_IMRH_INT_MASK48     (0x00010000)
+#define MCF_INTC1_IMRH_INT_MASK49     (0x00020000)
+#define MCF_INTC1_IMRH_INT_MASK50     (0x00040000)
+#define MCF_INTC1_IMRH_INT_MASK51     (0x00080000)
+#define MCF_INTC1_IMRH_INT_MASK52     (0x00100000)
+#define MCF_INTC1_IMRH_INT_MASK53     (0x00200000)
+#define MCF_INTC1_IMRH_INT_MASK54     (0x00400000)
+#define MCF_INTC1_IMRH_INT_MASK55     (0x00800000)
+#define MCF_INTC1_IMRH_INT_MASK56     (0x01000000)
+#define MCF_INTC1_IMRH_INT_MASK57     (0x02000000)
+#define MCF_INTC1_IMRH_INT_MASK58     (0x04000000)
+#define MCF_INTC1_IMRH_INT_MASK59     (0x08000000)
+#define MCF_INTC1_IMRH_INT_MASK60     (0x10000000)
+#define MCF_INTC1_IMRH_INT_MASK61     (0x20000000)
+#define MCF_INTC1_IMRH_INT_MASK62     (0x40000000)
+#define MCF_INTC1_IMRH_INT_MASK63     (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC1_IMRL */
+#define MCF_INTC1_IMRL_MASKALL        (0x00000001)
+#define MCF_INTC1_IMRL_INT_MASK1      (0x00000002)
+#define MCF_INTC1_IMRL_INT_MASK2      (0x00000004)
+#define MCF_INTC1_IMRL_INT_MASK3      (0x00000008)
+#define MCF_INTC1_IMRL_INT_MASK4      (0x00000010)
+#define MCF_INTC1_IMRL_INT_MASK5      (0x00000020)
+#define MCF_INTC1_IMRL_INT_MASK6      (0x00000040)
+#define MCF_INTC1_IMRL_INT_MASK7      (0x00000080)
+#define MCF_INTC1_IMRL_INT_MASK8      (0x00000100)
+#define MCF_INTC1_IMRL_INT_MASK9      (0x00000200)
+#define MCF_INTC1_IMRL_INT_MASK10     (0x00000400)
+#define MCF_INTC1_IMRL_INT_MASK11     (0x00000800)
+#define MCF_INTC1_IMRL_INT_MASK12     (0x00001000)
+#define MCF_INTC1_IMRL_INT_MASK13     (0x00002000)
+#define MCF_INTC1_IMRL_INT_MASK14     (0x00004000)
+#define MCF_INTC1_IMRL_INT_MASK15     (0x00008000)
+#define MCF_INTC1_IMRL_INT_MASK16     (0x00010000)
+#define MCF_INTC1_IMRL_INT_MASK17     (0x00020000)
+#define MCF_INTC1_IMRL_INT_MASK18     (0x00040000)
+#define MCF_INTC1_IMRL_INT_MASK19     (0x00080000)
+#define MCF_INTC1_IMRL_INT_MASK20     (0x00100000)
+#define MCF_INTC1_IMRL_INT_MASK21     (0x00200000)
+#define MCF_INTC1_IMRL_INT_MASK22     (0x00400000)
+#define MCF_INTC1_IMRL_INT_MASK23     (0x00800000)
+#define MCF_INTC1_IMRL_INT_MASK24     (0x01000000)
+#define MCF_INTC1_IMRL_INT_MASK25     (0x02000000)
+#define MCF_INTC1_IMRL_INT_MASK26     (0x04000000)
+#define MCF_INTC1_IMRL_INT_MASK27     (0x08000000)
+#define MCF_INTC1_IMRL_INT_MASK28     (0x10000000)
+#define MCF_INTC1_IMRL_INT_MASK29     (0x20000000)
+#define MCF_INTC1_IMRL_INT_MASK30     (0x40000000)
+#define MCF_INTC1_IMRL_INT_MASK31     (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC1_INTFRCH */
+#define MCF_INTC1_INTFRCH_INTFRC32    (0x00000001)
+#define MCF_INTC1_INTFRCH_INTFRC33    (0x00000002)
+#define MCF_INTC1_INTFRCH_INTFRC34    (0x00000004)
+#define MCF_INTC1_INTFRCH_INTFRC35    (0x00000008)
+#define MCF_INTC1_INTFRCH_INTFRC36    (0x00000010)
+#define MCF_INTC1_INTFRCH_INTFRC37    (0x00000020)
+#define MCF_INTC1_INTFRCH_INTFRC38    (0x00000040)
+#define MCF_INTC1_INTFRCH_INTFRC39    (0x00000080)
+#define MCF_INTC1_INTFRCH_INTFRC40    (0x00000100)
+#define MCF_INTC1_INTFRCH_INTFRC41    (0x00000200)
+#define MCF_INTC1_INTFRCH_INTFRC42    (0x00000400)
+#define MCF_INTC1_INTFRCH_INTFRC43    (0x00000800)
+#define MCF_INTC1_INTFRCH_INTFRC44    (0x00001000)
+#define MCF_INTC1_INTFRCH_INTFRC45    (0x00002000)
+#define MCF_INTC1_INTFRCH_INTFRC46    (0x00004000)
+#define MCF_INTC1_INTFRCH_INTFRC47    (0x00008000)
+#define MCF_INTC1_INTFRCH_INTFRC48    (0x00010000)
+#define MCF_INTC1_INTFRCH_INTFRC49    (0x00020000)
+#define MCF_INTC1_INTFRCH_INTFRC50    (0x00040000)
+#define MCF_INTC1_INTFRCH_INTFRC51    (0x00080000)
+#define MCF_INTC1_INTFRCH_INTFRC52    (0x00100000)
+#define MCF_INTC1_INTFRCH_INTFRC53    (0x00200000)
+#define MCF_INTC1_INTFRCH_INTFRC54    (0x00400000)
+#define MCF_INTC1_INTFRCH_INTFRC55    (0x00800000)
+#define MCF_INTC1_INTFRCH_INTFRC56    (0x01000000)
+#define MCF_INTC1_INTFRCH_INTFRC57    (0x02000000)
+#define MCF_INTC1_INTFRCH_INTFRC58    (0x04000000)
+#define MCF_INTC1_INTFRCH_INTFRC59    (0x08000000)
+#define MCF_INTC1_INTFRCH_INTFRC60    (0x10000000)
+#define MCF_INTC1_INTFRCH_INTFRC61    (0x20000000)
+#define MCF_INTC1_INTFRCH_INTFRC62    (0x40000000)
+#define MCF_INTC1_INTFRCH_INTFRC63    (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC1_INTFRCL */
+#define MCF_INTC1_INTFRCL_INTFRC1     (0x00000002)
+#define MCF_INTC1_INTFRCL_INTFRC2     (0x00000004)
+#define MCF_INTC1_INTFRCL_INTFRC3     (0x00000008)
+#define MCF_INTC1_INTFRCL_INTFRC4     (0x00000010)
+#define MCF_INTC1_INTFRCL_INTFRC5     (0x00000020)
+#define MCF_INTC1_INTFRCL_INT6        (0x00000040)
+#define MCF_INTC1_INTFRCL_INT7        (0x00000080)
+#define MCF_INTC1_INTFRCL_INT8        (0x00000100)
+#define MCF_INTC1_INTFRCL_INT9        (0x00000200)
+#define MCF_INTC1_INTFRCL_INT10       (0x00000400)
+#define MCF_INTC1_INTFRCL_INTFRC11    (0x00000800)
+#define MCF_INTC1_INTFRCL_INTFRC12    (0x00001000)
+#define MCF_INTC1_INTFRCL_INTFRC13    (0x00002000)
+#define MCF_INTC1_INTFRCL_INTFRC14    (0x00004000)
+#define MCF_INTC1_INTFRCL_INT15       (0x00008000)
+#define MCF_INTC1_INTFRCL_INTFRC16    (0x00010000)
+#define MCF_INTC1_INTFRCL_INTFRC17    (0x00020000)
+#define MCF_INTC1_INTFRCL_INTFRC18    (0x00040000)
+#define MCF_INTC1_INTFRCL_INTFRC19    (0x00080000)
+#define MCF_INTC1_INTFRCL_INTFRC20    (0x00100000)
+#define MCF_INTC1_INTFRCL_INTFRC21    (0x00200000)
+#define MCF_INTC1_INTFRCL_INTFRC22    (0x00400000)
+#define MCF_INTC1_INTFRCL_INTFRC23    (0x00800000)
+#define MCF_INTC1_INTFRCL_INTFRC24    (0x01000000)
+#define MCF_INTC1_INTFRCL_INTFRC25    (0x02000000)
+#define MCF_INTC1_INTFRCL_INTFRC26    (0x04000000)
+#define MCF_INTC1_INTFRCL_INTFRC27    (0x08000000)
+#define MCF_INTC1_INTFRCL_INTFRC28    (0x10000000)
+#define MCF_INTC1_INTFRCL_INTFRC29    (0x20000000)
+#define MCF_INTC1_INTFRCL_INTFRC30    (0x40000000)
+#define MCF_INTC1_INTFRCL_INTFRC31    (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC1_IRLR */
+#define MCF_INTC1_IRLR_IRQ(x)         (((x)&0x7F)<<1)
+
+/* Bit definitions and macros for MCF_INTC1_IACKLPR */
+#define MCF_INTC1_IACKLPR_PRI(x)      (((x)&0x0F)<<0)
+#define MCF_INTC1_IACKLPR_LEVEL(x)    (((x)&0x07)<<4)
+
+/* Bit definitions and macros for MCF_INTC1_ICRn */
+#define MCF_INTC1_ICRn_IP(x)          (((x)&0x07)<<0)
+#define MCF_INTC1_ICRn_IL(x)          (((x)&0x07)<<3)
+
+/********************************************************************/
+
+#endif /* __MCF523X_INTC1_H__ */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_mdha.h b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_mdha.h
new file mode 100644
index 000000000..cc2ff2710
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_mdha.h
@@ -0,0 +1,101 @@
+/*
+ * These files are taken from the MCF523X source code example package
+ * which is available on the Freescale website. Freescale explicitly 
+ * grants the redistribution and modification of these source files.
+ * The complete licensing information is available in the file 
+ * LICENSE_FREESCALE.TXT.
+ *
+ * File:	mcf523x_mdha.h
+ * Purpose:	Register and bit definitions for the MCF523X
+ *
+ * Notes:	
+ *	
+ */
+
+#ifndef __MCF523X_MDHA_H__
+#define __MCF523X_MDHA_H__
+
+/*********************************************************************
+*
+* Message Digest Hardware Accelerator (MDHA)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_MDHA_MDMR     (*(vuint32*)(void*)(&__IPSBAR[0x190000]))
+#define MCF_MDHA_MDCR     (*(vuint32*)(void*)(&__IPSBAR[0x190004]))
+#define MCF_MDHA_MDCMR    (*(vuint32*)(void*)(&__IPSBAR[0x190008]))
+#define MCF_MDHA_MDSR     (*(vuint32*)(void*)(&__IPSBAR[0x19000C]))
+#define MCF_MDHA_MDISR     (*(vuint32*)(void*)(&__IPSBAR[0x190010]))
+#define MCF_MDHA_MDIMR    (*(vuint32*)(void*)(&__IPSBAR[0x190014]))
+#define MCF_MDHA_MDDSR    (*(vuint32*)(void*)(&__IPSBAR[0x19001C]))
+#define MCF_MDHA_MDIN     (*(vuint32*)(void*)(&__IPSBAR[0x190020]))
+#define MCF_MDHA_MDA0     (*(vuint32*)(void*)(&__IPSBAR[0x190030]))
+#define MCF_MDHA_MDB0     (*(vuint32*)(void*)(&__IPSBAR[0x190034]))
+#define MCF_MDHA_MDC0     (*(vuint32*)(void*)(&__IPSBAR[0x190038]))
+#define MCF_MDHA_MDD0     (*(vuint32*)(void*)(&__IPSBAR[0x19003C]))
+#define MCF_MDHA_MDE0     (*(vuint32*)(void*)(&__IPSBAR[0x190040]))
+#define MCF_MDHA_MDMDS    (*(vuint32*)(void*)(&__IPSBAR[0x190044]))
+#define MCF_MDHA_MDA1     (*(vuint32*)(void*)(&__IPSBAR[0x190070]))
+#define MCF_MDHA_MDB1     (*(vuint32*)(void*)(&__IPSBAR[0x190074]))
+#define MCF_MDHA_MDC1     (*(vuint32*)(void*)(&__IPSBAR[0x190078]))
+#define MCF_MDHA_MDD1     (*(vuint32*)(void*)(&__IPSBAR[0x19007C]))
+#define MCF_MDHA_MDE1     (*(vuint32*)(void*)(&__IPSBAR[0x190080]))
+
+/* Bit definitions and macros for MCF_MDHA_MDMR */
+#define MCF_MDHA_MDMR_ALG             (0x00000001)
+#define MCF_MDHA_MDMR_PDATA           (0x00000004)
+#define MCF_MDHA_MDMR_MAC(x)          (((x)&0x00000003)<<3)
+#define MCF_MDHA_MDMR_INIT            (0x00000020)
+#define MCF_MDHA_MDMR_IPAD            (0x00000040)
+#define MCF_MDHA_MDMR_OPAD            (0x00000080)
+#define MCF_MDHA_MDMR_SWAP            (0x00000100)
+#define MCF_MDHA_MDMR_MACFULL         (0x00000200)
+#define MCF_MDHA_MDMR_SSL             (0x00000400)
+
+/* Bit definitions and macros for MCF_MDHA_MDCR */
+#define MCF_MDHA_MDCR_IE              (0x00000001)
+
+/* Bit definitions and macros for MCF_MDHA_MDCMR */
+#define MCF_MDHA_MDCMR_SWR             (0x00000001)
+#define MCF_MDHA_MDCMR_RI             (0x00000002)
+#define MCF_MDHA_MDCMR_CI             (0x00000004)
+#define MCF_MDHA_MDCMR_GO             (0x00000008)
+
+/* Bit definitions and macros for MCF_MDHA_MDSR */
+#define MCF_MDHA_MDSR_INT             (0x00000001)
+#define MCF_MDHA_MDSR_DONE            (0x00000002)
+#define MCF_MDHA_MDSR_ERR             (0x00000004)
+#define MCF_MDHA_MDSR_RD              (0x00000008)
+#define MCF_MDHA_MDSR_BUSY            (0x00000010)
+#define MCF_MDHA_MDSR_END             (0x00000020)
+#define MCF_MDHA_MDSR_HSH             (0x00000040)
+#define MCF_MDHA_MDSR_GNW             (0x00000080)
+#define MCF_MDHA_MDSR_FS(x)           (((x)&0x00000007)<<8)
+#define MCF_MDHA_MDSR_APD(x)          (((x)&0x00000007)<<13)
+#define MCF_MDHA_MDSR_IFL(x)          (((x)&0x000000FF)<<16)
+
+/* Bit definitions and macros for MCF_MDHA_MDIR */
+#define MCF_MDHA_MDIR_IFO             (0x00000001)
+#define MCF_MDHA_MDIR_NON             (0x00000004)
+#define MCF_MDHA_MDIR_IME             (0x00000010)
+#define MCF_MDHA_MDIR_IDS             (0x00000020)
+#define MCF_MDHA_MDIR_RMDP            (0x00000080)
+#define MCF_MDHA_MDIR_ERE             (0x00000100)
+#define MCF_MDHA_MDIR_GTDS            (0x00000200)
+
+/* Bit definitions and macros for MCF_MDHA_MDIMR */
+#define MCF_MDHA_MDIMR_IFO            (0x00000001)
+#define MCF_MDHA_MDIMR_NON            (0x00000004)
+#define MCF_MDHA_MDIMR_IME            (0x00000010)
+#define MCF_MDHA_MDIMR_IDS            (0x00000020)
+#define MCF_MDHA_MDIMR_RMDP           (0x00000080)
+#define MCF_MDHA_MDIMR_ERE            (0x00000100)
+#define MCF_MDHA_MDIMR_GTDS           (0x00000200)
+
+/* Bit definitions and macros for MCF_MDHA_MDDSR */
+#define MCF_MDHA_MDDSR_DATASIZE(x)    (((x)&0x1FFFFFFF)<<0)
+
+/********************************************************************/
+
+#endif /* __MCF523X_MDHA_H__ */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_pit.h b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_pit.h
new file mode 100644
index 000000000..a3798f070
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_pit.h
@@ -0,0 +1,89 @@
+/*
+ * These files are taken from the MCF523X source code example package
+ * which is available on the Freescale website. Freescale explicitly 
+ * grants the redistribution and modification of these source files.
+ * The complete licensing information is available in the file 
+ * LICENSE_FREESCALE.TXT.
+ *
+ * File:	mcf523x_pit.h
+ * Purpose:	Register and bit definitions for the MCF523X
+ *
+ * Notes:	
+ *	
+ */
+
+#ifndef __MCF523X_PIT_H__
+#define __MCF523X_PIT_H__
+
+/*********************************************************************
+*
+* Programmable Interrupt Timer Modules (PIT)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_PIT_PCSR0       (*(vuint16*)(void*)(&__IPSBAR[0x150000]))
+#define MCF_PIT_PMR0        (*(vuint16*)(void*)(&__IPSBAR[0x150002]))
+#define MCF_PIT_PCNTR0      (*(vuint16*)(void*)(&__IPSBAR[0x150004]))
+#define MCF_PIT_PCSR1       (*(vuint16*)(void*)(&__IPSBAR[0x160000]))
+#define MCF_PIT_PMR1        (*(vuint16*)(void*)(&__IPSBAR[0x160002]))
+#define MCF_PIT_PCNTR1      (*(vuint16*)(void*)(&__IPSBAR[0x160004]))
+#define MCF_PIT_PCSR2       (*(vuint16*)(void*)(&__IPSBAR[0x170000]))
+#define MCF_PIT_PMR2        (*(vuint16*)(void*)(&__IPSBAR[0x170002]))
+#define MCF_PIT_PCNTR2      (*(vuint16*)(void*)(&__IPSBAR[0x170004]))
+#define MCF_PIT_PCSR3       (*(vuint16*)(void*)(&__IPSBAR[0x180000]))
+#define MCF_PIT_PMR3        (*(vuint16*)(void*)(&__IPSBAR[0x180002]))
+#define MCF_PIT_PCNTR3      (*(vuint16*)(void*)(&__IPSBAR[0x180004]))
+#define MCF_PIT_PCSR(x)     (*(vuint16*)(void*)(&__IPSBAR[0x150000+((x)*0x10000)]))
+#define MCF_PIT_PMR(x)      (*(vuint16*)(void*)(&__IPSBAR[0x150002+((x)*0x10000)]))
+#define MCF_PIT_PCNTR(x)    (*(vuint16*)(void*)(&__IPSBAR[0x150004+((x)*0x10000)]))
+
+/* Bit definitions and macros for MCF_PIT_PCSR */
+#define MCF_PIT_PCSR_EN        (0x0001)
+#define MCF_PIT_PCSR_RLD       (0x0002)
+#define MCF_PIT_PCSR_PIF       (0x0004)
+#define MCF_PIT_PCSR_PIE       (0x0008)
+#define MCF_PIT_PCSR_OVW       (0x0010)
+#define MCF_PIT_PCSR_HALTED    (0x0020)
+#define MCF_PIT_PCSR_DOZE      (0x0040)
+#define MCF_PIT_PCSR_PRE(x)    (((x)&0x000F)<<8)
+
+/* Bit definitions and macros for MCF_PIT_PMR */
+#define MCF_PIT_PMR_PM0        (0x0001)
+#define MCF_PIT_PMR_PM1        (0x0002)
+#define MCF_PIT_PMR_PM2        (0x0004)
+#define MCF_PIT_PMR_PM3        (0x0008)
+#define MCF_PIT_PMR_PM4        (0x0010)
+#define MCF_PIT_PMR_PM5        (0x0020)
+#define MCF_PIT_PMR_PM6        (0x0040)
+#define MCF_PIT_PMR_PM7        (0x0080)
+#define MCF_PIT_PMR_PM8        (0x0100)
+#define MCF_PIT_PMR_PM9        (0x0200)
+#define MCF_PIT_PMR_PM10       (0x0400)
+#define MCF_PIT_PMR_PM11       (0x0800)
+#define MCF_PIT_PMR_PM12       (0x1000)
+#define MCF_PIT_PMR_PM13       (0x2000)
+#define MCF_PIT_PMR_PM14       (0x4000)
+#define MCF_PIT_PMR_PM15       (0x8000)
+
+/* Bit definitions and macros for MCF_PIT_PCNTR */
+#define MCF_PIT_PCNTR_PC0      (0x0001)
+#define MCF_PIT_PCNTR_PC1      (0x0002)
+#define MCF_PIT_PCNTR_PC2      (0x0004)
+#define MCF_PIT_PCNTR_PC3      (0x0008)
+#define MCF_PIT_PCNTR_PC4      (0x0010)
+#define MCF_PIT_PCNTR_PC5      (0x0020)
+#define MCF_PIT_PCNTR_PC6      (0x0040)
+#define MCF_PIT_PCNTR_PC7      (0x0080)
+#define MCF_PIT_PCNTR_PC8      (0x0100)
+#define MCF_PIT_PCNTR_PC9      (0x0200)
+#define MCF_PIT_PCNTR_PC10     (0x0400)
+#define MCF_PIT_PCNTR_PC11     (0x0800)
+#define MCF_PIT_PCNTR_PC12     (0x1000)
+#define MCF_PIT_PCNTR_PC13     (0x2000)
+#define MCF_PIT_PCNTR_PC14     (0x4000)
+#define MCF_PIT_PCNTR_PC15     (0x8000)
+
+/********************************************************************/
+
+#endif /* __MCF523X_PIT_H__ */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_qspi.h b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_qspi.h
new file mode 100644
index 000000000..9f05ada61
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_qspi.h
@@ -0,0 +1,69 @@
+/*
+ * These files are taken from the MCF523X source code example package
+ * which is available on the Freescale website. Freescale explicitly 
+ * grants the redistribution and modification of these source files.
+ * The complete licensing information is available in the file 
+ * LICENSE_FREESCALE.TXT.
+ *
+ * File:	mcf523x_qspi.h
+ * Purpose:	Register and bit definitions for the MCF523X
+ *
+ * Notes:	
+ *	
+ */
+
+#ifndef __MCF523X_QSPI_H__
+#define __MCF523X_QSPI_H__
+
+/*********************************************************************
+*
+* Queued Serial Peripheral Interface (QSPI)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_QSPI_QMR      (*(vuint16*)(void*)(&__IPSBAR[0x000340]))
+#define MCF_QSPI_QDLYR    (*(vuint16*)(void*)(&__IPSBAR[0x000344]))
+#define MCF_QSPI_QWR      (*(vuint16*)(void*)(&__IPSBAR[0x000348]))
+#define MCF_QSPI_QIR      (*(vuint16*)(void*)(&__IPSBAR[0x00034C]))
+#define MCF_QSPI_QAR      (*(vuint16*)(void*)(&__IPSBAR[0x000350]))
+#define MCF_QSPI_QDR      (*(vuint16*)(void*)(&__IPSBAR[0x000354]))
+
+/* Bit definitions and macros for MCF_QSPI_QMR */
+#define MCF_QSPI_QMR_BAUD(x)     (((x)&0x00FF)<<0)
+#define MCF_QSPI_QMR_CPHA        (0x0100)
+#define MCF_QSPI_QMR_CPOL        (0x0200)
+#define MCF_QSPI_QMR_BITS(x)     (((x)&0x000F)<<10)
+#define MCF_QSPI_QMR_DOHIE       (0x4000)
+#define MCF_QSPI_QMR_MSTR        (0x8000)
+
+/* Bit definitions and macros for MCF_QSPI_QDLYR */
+#define MCF_QSPI_QDLYR_DTL(x)    (((x)&0x00FF)<<0)
+#define MCF_QSPI_QDLYR_QCD(x)    (((x)&0x007F)<<8)
+#define MCF_QSPI_QDLYR_SPE       (0x8000)
+
+/* Bit definitions and macros for MCF_QSPI_QWR */
+#define MCF_QSPI_QWR_NEWQP(x)    (((x)&0x000F)<<0)
+#define MCF_QSPI_QWR_ENDQP(x)    (((x)&0x000F)<<8)
+#define MCF_QSPI_QWR_CSIV        (0x1000)
+#define MCF_QSPI_QWR_WRTO        (0x2000)
+#define MCF_QSPI_QWR_WREN        (0x4000)
+#define MCF_QSPI_QWR_HALT        (0x8000)
+
+/* Bit definitions and macros for MCF_QSPI_QIR */
+#define MCF_QSPI_QIR_SPIF        (0x0001)
+#define MCF_QSPI_QIR_ABRT        (0x0004)
+#define MCF_QSPI_QIR_WCEF        (0x0008)
+#define MCF_QSPI_QIR_SPIFE       (0x0100)
+#define MCF_QSPI_QIR_ABRTE       (0x0400)
+#define MCF_QSPI_QIR_WCEFE       (0x0800)
+#define MCF_QSPI_QIR_ABRTL       (0x1000)
+#define MCF_QSPI_QIR_ABRTB       (0x4000)
+#define MCF_QSPI_QIR_WCEFB       (0x8000)
+
+/* Bit definitions and macros for MCF_QSPI_QAR */
+#define MCF_QSPI_QAR_ADDR(x)     (((x)&0x003F)<<0)
+
+/********************************************************************/
+
+#endif /* __MCF523X_QSPI_H__ */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_rcm.h b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_rcm.h
new file mode 100644
index 000000000..cae92d22b
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_rcm.h
@@ -0,0 +1,42 @@
+/*
+ * These files are taken from the MCF523X source code example package
+ * which is available on the Freescale website. Freescale explicitly 
+ * grants the redistribution and modification of these source files.
+ * The complete licensing information is available in the file 
+ * LICENSE_FREESCALE.TXT.
+ *
+ * File:	mcf523x_rcm.h
+ * Purpose:	Register and bit definitions for the MCF523X
+ *
+ * Notes:	
+ *	
+ */
+
+#ifndef __MCF523X_RCM_H__
+#define __MCF523X_RCM_H__
+
+/*********************************************************************
+*
+* Reset Configuration Module (RCM)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_RCM_RCR    (*(vuint8 *)(void*)(&__IPSBAR[0x110000]))
+#define MCF_RCM_RSR    (*(vuint8 *)(void*)(&__IPSBAR[0x110001]))
+
+/* Bit definitions and macros for MCF_RCM_RCR */
+#define MCF_RCM_RCR_FRCRSTOUT    (0x40)
+#define MCF_RCM_RCR_SOFTRST      (0x80)
+
+/* Bit definitions and macros for MCF_RCM_RSR */
+#define MCF_RCM_RSR_LOL          (0x01)
+#define MCF_RCM_RSR_LOC          (0x02)
+#define MCF_RCM_RSR_EXT          (0x04)
+#define MCF_RCM_RSR_POR          (0x08)
+#define MCF_RCM_RSR_WDR          (0x10)
+#define MCF_RCM_RSR_SOFT         (0x20)
+
+/********************************************************************/
+
+#endif /* __MCF523X_RCM_H__ */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_rng.h b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_rng.h
new file mode 100644
index 000000000..4bfca3d6c
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_rng.h
@@ -0,0 +1,46 @@
+/*
+ * These files are taken from the MCF523X source code example package
+ * which is available on the Freescale website. Freescale explicitly 
+ * grants the redistribution and modification of these source files.
+ * The complete licensing information is available in the file 
+ * LICENSE_FREESCALE.TXT.
+ *
+ * File:	mcf523x_rng.h
+ * Purpose:	Register and bit definitions for the MCF523X
+ *
+ * Notes:	
+ *	
+ */
+
+#ifndef __MCF523X_RNG_H__
+#define __MCF523X_RNG_H__
+
+/*********************************************************************
+*
+* Random Number Generator (RNG)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_RNG_RNGCR     (*(vuint32*)(void*)(&__IPSBAR[0x1A0000]))
+#define MCF_RNG_RNGSR     (*(vuint32*)(void*)(&__IPSBAR[0x1A0004]))
+#define MCF_RNG_RNGER     (*(vuint32*)(void*)(&__IPSBAR[0x1A0008]))
+#define MCF_RNG_RNGOUT    (*(vuint32*)(void*)(&__IPSBAR[0x1A000C]))
+
+/* Bit definitions and macros for MCF_RNG_RNGCR */
+#define MCF_RNG_RNGCR_GO        (0x00000001)
+#define MCF_RNG_RNGCR_HA        (0x00000002)
+#define MCF_RNG_RNGCR_IM        (0x00000004)
+#define MCF_RNG_RNGCR_CI        (0x00000008)
+
+/* Bit definitions and macros for MCF_RNG_RNGSR */
+#define MCF_RNG_RNGSR_SV        (0x00000001)
+#define MCF_RNG_RNGSR_LRS       (0x00000002)
+#define MCF_RNG_RNGSR_FUF       (0x00000004)
+#define MCF_RNG_RNGSR_EI        (0x00000008)
+#define MCF_RNG_RNGSR_OFL(x)    (((x)&0x000000FF)<<8)
+#define MCF_RNG_RNGSR_OFS(x)    (((x)&0x000000FF)<<16)
+
+/********************************************************************/
+
+#endif /* __MCF523X_RNG_H__ */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_scm.h b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_scm.h
new file mode 100644
index 000000000..e330ee990
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_scm.h
@@ -0,0 +1,150 @@
+/*
+ * These files are taken from the MCF523X source code example package
+ * which is available on the Freescale website. Freescale explicitly 
+ * grants the redistribution and modification of these source files.
+ * The complete licensing information is available in the file 
+ * LICENSE_FREESCALE.TXT.
+ *
+ * File:	mcf523x_scm.h
+ * Purpose:	Register and bit definitions for the MCF523X
+ *
+ * Notes:	
+ *	
+ */
+
+#ifndef __MCF523X_SCM_H__
+#define __MCF523X_SCM_H__
+
+/*********************************************************************
+*
+* System Control Module (SCM)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_SCM_IPSBAR     (*(vuint32*)(void*)(&__IPSBAR[0x000000]))
+#define MCF_SCM_RAMBAR     (*(vuint32*)(void*)(&__IPSBAR[0x000008]))
+#define MCF_SCM_CRSR       (*(vuint8 *)(void*)(&__IPSBAR[0x000010]))
+#define MCF_SCM_CWCR       (*(vuint8 *)(void*)(&__IPSBAR[0x000011]))
+#define MCF_SCM_LPICR      (*(vuint8 *)(void*)(&__IPSBAR[0x000012]))
+#define MCF_SCM_CWSR       (*(vuint8 *)(void*)(&__IPSBAR[0x000013]))
+#define MCF_SCM_DMAREQC    (*(vuint32*)(void*)(&__IPSBAR[0x000014]))
+#define MCF_SCM_MPARK      (*(vuint32*)(void*)(&__IPSBAR[0x00001C]))
+#define MCF_SCM_MPR        (*(vuint8 *)(void*)(&__IPSBAR[0x000020]))
+#define MCF_SCM_PACR0      (*(vuint8 *)(void*)(&__IPSBAR[0x000024]))
+#define MCF_SCM_PACR1      (*(vuint8 *)(void*)(&__IPSBAR[0x000025]))
+#define MCF_SCM_PACR2      (*(vuint8 *)(void*)(&__IPSBAR[0x000026]))
+#define MCF_SCM_PACR3      (*(vuint8 *)(void*)(&__IPSBAR[0x000027]))
+#define MCF_SCM_PACR4      (*(vuint8 *)(void*)(&__IPSBAR[0x000028]))
+#define MCF_SCM_PACR5      (*(vuint8 *)(void*)(&__IPSBAR[0x00002A]))
+#define MCF_SCM_PACR6      (*(vuint8 *)(void*)(&__IPSBAR[0x00002B]))
+#define MCF_SCM_PACR7      (*(vuint8 *)(void*)(&__IPSBAR[0x00002C]))
+#define MCF_SCM_PACR8      (*(vuint8 *)(void*)(&__IPSBAR[0x00002E]))
+#define MCF_SCM_GPACR0     (*(vuint8 *)(void*)(&__IPSBAR[0x000030]))
+
+/* Bit definitions and macros for MCF_SCM_IPSBAR */
+#define MCF_SCM_IPSBAR_V                 (0x00000001)
+#define MCF_SCM_IPSBAR_BA(x)             (((x)&0x00000003)<<30)
+
+/* Bit definitions and macros for MCF_SCM_RAMBAR */
+#define MCF_SCM_RAMBAR_BDE               (0x00000200)
+#define MCF_SCM_RAMBAR_BA(x)             (((x)&0x0000FFFF)<<16)
+
+/* Bit definitions and macros for MCF_SCM_CRSR */
+#define MCF_SCM_CRSR_CWDR                (0x20)
+#define MCF_SCM_CRSR_EXT                 (0x80)
+
+/* Bit definitions and macros for MCF_SCM_CWCR */
+#define MCF_SCM_CWCR_CWTIC               (0x01)
+#define MCF_SCM_CWCR_CWTAVAL             (0x02)
+#define MCF_SCM_CWCR_CWTA                (0x04)
+#define MCF_SCM_CWCR_CWT(x)              (((x)&0x07)<<3)
+#define MCF_SCM_CWCR_CWRI                (0x40)
+#define MCF_SCM_CWCR_CWE                 (0x80)
+
+/* Bit definitions and macros for MCF_SCM_LPICR */
+#define MCF_SCM_LPICR_XLPM_IPL(x)        (((x)&0x07)<<4)
+#define MCF_SCM_LPICR_ENBSTOP            (0x80)
+
+/* Bit definitions and macros for MCF_SCM_DMAREQC */
+#define MCF_SCM_DMAREQC_DMAC0(x)         (((x)&0x0000000F)<<0)
+#define MCF_SCM_DMAREQC_DMAC1(x)         (((x)&0x0000000F)<<4)
+#define MCF_SCM_DMAREQC_DMAC2(x)         (((x)&0x0000000F)<<8)
+#define MCF_SCM_DMAREQC_DMAC3(x)         (((x)&0x0000000F)<<12)
+
+/* Bit definitions and macros for MCF_SCM_MPARK */
+#define MCF_SCM_MPARK_LCKOUT_TIME(x)     (((x)&0x0000000F)<<8)
+#define MCF_SCM_MPARK_PRKLAST            (0x00001000)
+#define MCF_SCM_MPARK_TIMEOUT            (0x00002000)
+#define MCF_SCM_MPARK_FIXED              (0x00004000)
+#define MCF_SCM_MPARK_M1_PRTY(x)         (((x)&0x00000003)<<16)
+#define MCF_SCM_MPARK_M0_PRTY(x)         (((x)&0x00000003)<<18)
+#define MCF_SCM_MPARK_M2_PRTY(x)         (((x)&0x00000003)<<20)
+#define MCF_SCM_MPARK_M3_PRTY(x)         (((x)&0x00000003)<<22)
+#define MCF_SCM_MPARK_BCR24BIT           (0x01000000)
+#define MCF_SCM_MPARK_M2_P_EN            (0x02000000)
+
+/* Bit definitions and macros for MCF_SCM_MPR */
+#define MCF_SCM_MPR_MPR(x)               (((x)&0x0F)<<0)
+
+/* Bit definitions and macros for MCF_SCM_PACR0 */
+#define MCF_SCM_PACR0_ACCESS_CTRL0(x)    (((x)&0x07)<<0)
+#define MCF_SCM_PACR0_LOCK0              (0x08)
+#define MCF_SCM_PACR0_ACCESS_CTRL1(x)    (((x)&0x07)<<4)
+#define MCF_SCM_PACR0_LOCK1              (0x80)
+
+/* Bit definitions and macros for MCF_SCM_PACR1 */
+#define MCF_SCM_PACR1_ACCESS_CTRL0(x)    (((x)&0x07)<<0)
+#define MCF_SCM_PACR1_LOCK0              (0x08)
+#define MCF_SCM_PACR1_ACCESS_CTRL1(x)    (((x)&0x07)<<4)
+#define MCF_SCM_PACR1_LOCK1              (0x80)
+
+/* Bit definitions and macros for MCF_SCM_PACR2 */
+#define MCF_SCM_PACR2_ACCESS_CTRL0(x)    (((x)&0x07)<<0)
+#define MCF_SCM_PACR2_LOCK0              (0x08)
+#define MCF_SCM_PACR2_ACCESS_CTRL1(x)    (((x)&0x07)<<4)
+#define MCF_SCM_PACR2_LOCK1              (0x80)
+
+/* Bit definitions and macros for MCF_SCM_PACR3 */
+#define MCF_SCM_PACR3_ACCESS_CTRL0(x)    (((x)&0x07)<<0)
+#define MCF_SCM_PACR3_LOCK0              (0x08)
+#define MCF_SCM_PACR3_ACCESS_CTRL1(x)    (((x)&0x07)<<4)
+#define MCF_SCM_PACR3_LOCK1              (0x80)
+
+/* Bit definitions and macros for MCF_SCM_PACR4 */
+#define MCF_SCM_PACR4_ACCESS_CTRL0(x)    (((x)&0x07)<<0)
+#define MCF_SCM_PACR4_LOCK0              (0x08)
+#define MCF_SCM_PACR4_ACCESS_CTRL1(x)    (((x)&0x07)<<4)
+#define MCF_SCM_PACR4_LOCK1              (0x80)
+
+/* Bit definitions and macros for MCF_SCM_PACR5 */
+#define MCF_SCM_PACR5_ACCESS_CTRL0(x)    (((x)&0x07)<<0)
+#define MCF_SCM_PACR5_LOCK0              (0x08)
+#define MCF_SCM_PACR5_ACCESS_CTRL1(x)    (((x)&0x07)<<4)
+#define MCF_SCM_PACR5_LOCK1              (0x80)
+
+/* Bit definitions and macros for MCF_SCM_PACR6 */
+#define MCF_SCM_PACR6_ACCESS_CTRL0(x)    (((x)&0x07)<<0)
+#define MCF_SCM_PACR6_LOCK0              (0x08)
+#define MCF_SCM_PACR6_ACCESS_CTRL1(x)    (((x)&0x07)<<4)
+#define MCF_SCM_PACR6_LOCK1              (0x80)
+
+/* Bit definitions and macros for MCF_SCM_PACR7 */
+#define MCF_SCM_PACR7_ACCESS_CTRL0(x)    (((x)&0x07)<<0)
+#define MCF_SCM_PACR7_LOCK0              (0x08)
+#define MCF_SCM_PACR7_ACCESS_CTRL1(x)    (((x)&0x07)<<4)
+#define MCF_SCM_PACR7_LOCK1              (0x80)
+
+/* Bit definitions and macros for MCF_SCM_PACR8 */
+#define MCF_SCM_PACR8_ACCESS_CTRL0(x)    (((x)&0x07)<<0)
+#define MCF_SCM_PACR8_LOCK0              (0x08)
+#define MCF_SCM_PACR8_ACCESS_CTRL1(x)    (((x)&0x07)<<4)
+#define MCF_SCM_PACR8_LOCK1              (0x80)
+
+/* Bit definitions and macros for MCF_SCM_GPACR0 */
+#define MCF_SCM_GPACR0_ACCESS_CTRL(x)    (((x)&0x0F)<<0)
+#define MCF_SCM_GPACR0_LOCK              (0x80)
+
+/********************************************************************/
+
+#endif /* __MCF523X_SCM_H__ */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_sdramc.h b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_sdramc.h
new file mode 100644
index 000000000..87eb0acef
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_sdramc.h
@@ -0,0 +1,94 @@
+/*
+ * These files are taken from the MCF523X source code example package
+ * which is available on the Freescale website. Freescale explicitly 
+ * grants the redistribution and modification of these source files.
+ * The complete licensing information is available in the file 
+ * LICENSE_FREESCALE.TXT.
+ *
+ * File:	mcf523x_sdramc.h
+ * Purpose:	Register and bit definitions for the MCF523X
+ *
+ * Notes:	
+ *	
+ */
+
+#ifndef __MCF523X_SDRAMC_H__
+#define __MCF523X_SDRAMC_H__
+
+/*********************************************************************
+*
+* SDRAM Controller (SDRAMC)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_SDRAMC_DCR      (*(vuint16*)(void*)(&__IPSBAR[0x000040]))
+#define MCF_SDRAMC_DACR0    (*(vuint32*)(void*)(&__IPSBAR[0x000048]))
+#define MCF_SDRAMC_DMR0     (*(vuint32*)(void*)(&__IPSBAR[0x00004C]))
+#define MCF_SDRAMC_DACR1    (*(vuint32*)(void*)(&__IPSBAR[0x000050]))
+#define MCF_SDRAMC_DMR1     (*(vuint32*)(void*)(&__IPSBAR[0x000054]))
+
+/* Bit definitions and macros for MCF_SDRAMC_DCR */
+#define MCF_SDRAMC_DCR_RC(x)        (((x)&0x01FF)<<0)
+#define MCF_SDRAMC_DCR_RTIM(x)      (((x)&0x0003)<<9)
+#define MCF_SDRAMC_DCR_IS           (0x0800)
+#define MCF_SDRAMC_DCR_COC          (0x1000)
+#define MCF_SDRAMC_DCR_NAM          (0x2000)
+
+/* Bit definitions and macros for MCF_SDRAMC_DACR0 */
+#define MCF_SDRAMC_DACR0_IP         (0x00000008)
+#define MCF_SDRAMC_DACR0_PS(x)      (((x)&0x00000003)<<4)
+#define MCF_SDRAMC_DACR0_MRS        (0x00000040)
+#define MCF_SDRAMC_DACR0_CBM(x)     (((x)&0x00000007)<<8)
+#define MCF_SDRAMC_DACR0_CASL(x)    (((x)&0x00000003)<<12)
+#define MCF_SDRAMC_DACR0_RE         (0x00008000)
+#define MCF_SDRAMC_DACR0_BA(x)      (((x)&0x00003FFF)<<18)
+
+/* Bit definitions and macros for MCF_SDRAMC_DMR0 */
+#define MCF_SDRAMC_DMR0_V           (0x00000001)
+#define MCF_SDRAMC_DMR0_WP          (0x00000100)
+#define MCF_SDRAMC_DMR0_BAM(x)      (((x)&0x00003FFF)<<18)
+
+/* Bit definitions and macros for MCF_SDRAMC_DACR1 */
+#define MCF_SDRAMC_DACR1_IP         (0x00000008)
+#define MCF_SDRAMC_DACR1_PS(x)      (((x)&0x00000003)<<4)
+#define MCF_SDRAMC_DACR1_MRS        (0x00000040)
+#define MCF_SDRAMC_DACR1_CBM(x)     (((x)&0x00000007)<<8)
+#define MCF_SDRAMC_DACR1_CASL(x)    (((x)&0x00000003)<<12)
+#define MCF_SDRAMC_DACR1_RE         (0x00008000)
+#define MCF_SDRAMC_DACR1_BA(x)      (((x)&0x00003FFF)<<18)
+
+/* Bit definitions and macros for MCF_SDRAMC_DMR1 */
+#define MCF_SDRAMC_DMR1_V           (0x00000001)
+#define MCF_SDRAMC_DMR1_WP          (0x00000100)
+#define MCF_SDRAMC_DMR1_BAM(x)      (((x)&0x00003FFF)<<18)
+
+/********************************************************************/
+
+#define MCF_SDRAMC_DMR_BAM_4G			(0xFFFC0000)
+#define MCF_SDRAMC_DMR_BAM_2G			(0x7FFC0000)
+#define MCF_SDRAMC_DMR_BAM_1G			(0x3FFC0000)
+#define MCF_SDRAMC_DMR_BAM_1024M		(0x3FFC0000)
+#define MCF_SDRAMC_DMR_BAM_512M			(0x1FFC0000)
+#define MCF_SDRAMC_DMR_BAM_256M			(0x0FFC0000)
+#define MCF_SDRAMC_DMR_BAM_128M			(0x07FC0000)
+#define MCF_SDRAMC_DMR_BAM_64M			(0x03FC0000)
+#define MCF_SDRAMC_DMR_BAM_32M			(0x01FC0000)
+#define MCF_SDRAMC_DMR_BAM_16M			(0x00FC0000)
+#define MCF_SDRAMC_DMR_BAM_8M			(0x007C0000)
+#define MCF_SDRAMC_DMR_BAM_4M			(0x003C0000)
+#define MCF_SDRAMC_DMR_BAM_2M			(0x001C0000)
+#define MCF_SDRAMC_DMR_BAM_1M			(0x000C0000)
+#define MCF_SDRAMC_DMR_BAM_1024K		(0x000C0000)
+#define MCF_SDRAMC_DMR_BAM_512K			(0x00040000)
+#define MCF_SDRAMC_DMR_BAM_256K			(0x00000000)
+#define MCF_SDRAMC_DMR_WP				(0x00000100)
+#define MCF_SDRAMC_DMR_CI				(0x00000040)
+#define MCF_SDRAMC_DMR_AM				(0x00000020)
+#define MCF_SDRAMC_DMR_SC				(0x00000010)
+#define MCF_SDRAMC_DMR_SD				(0x00000008)
+#define MCF_SDRAMC_DMR_UC				(0x00000004)
+#define MCF_SDRAMC_DMR_UD				(0x00000002)
+#define MCF_SDRAMC_DMR_V				(0x00000001)
+
+#endif /* __MCF523X_SDRAMC_H__ */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_skha.h b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_skha.h
new file mode 100644
index 000000000..ae4dc57ab
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_skha.h
@@ -0,0 +1,120 @@
+/*
+ * These files are taken from the MCF523X source code example package
+ * which is available on the Freescale website. Freescale explicitly 
+ * grants the redistribution and modification of these source files.
+ * The complete licensing information is available in the file 
+ * LICENSE_FREESCALE.TXT.
+ *
+ * File:	mcf523x_skha.h
+ * Purpose:	Register and bit definitions for the MCF523X
+ *
+ * Notes:	
+ *	
+ */
+
+#ifndef __MCF523X_SKHA_H__
+#define __MCF523X_SKHA_H__
+
+/*********************************************************************
+*
+* Symmetric Key Hardware Accelerator (SKHA)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_SKHA_SKMR         (*(vuint32*)(void*)(&__IPSBAR[0x1B0000]))
+#define MCF_SKHA_SKCR         (*(vuint32*)(void*)(&__IPSBAR[0x1B0004]))
+#define MCF_SKHA_SKCMR        (*(vuint32*)(void*)(&__IPSBAR[0x1B0008]))
+#define MCF_SKHA_SKSR         (*(vuint32*)(void*)(&__IPSBAR[0x1B000C]))
+#define MCF_SKHA_SKIR         (*(vuint32*)(void*)(&__IPSBAR[0x1B0010]))
+#define MCF_SKHA_SKIMR        (*(vuint32*)(void*)(&__IPSBAR[0x1B0014]))
+#define MCF_SKHA_SKKSR        (*(vuint32*)(void*)(&__IPSBAR[0x1B0018]))
+#define MCF_SKHA_SKDSR        (*(vuint32*)(void*)(&__IPSBAR[0x1B001C]))
+#define MCF_SKHA_SKIN         (*(vuint32*)(void*)(&__IPSBAR[0x1B0020]))
+#define MCF_SKHA_SKOUT        (*(vuint32*)(void*)(&__IPSBAR[0x1B0024]))
+#define MCF_SKHA_SKKDR0       (*(vuint32*)(void*)(&__IPSBAR[0x1B0030]))
+#define MCF_SKHA_SKKDR1       (*(vuint32*)(void*)(&__IPSBAR[0x1B0034]))
+#define MCF_SKHA_SKKDR2       (*(vuint32*)(void*)(&__IPSBAR[0x1B0038]))
+#define MCF_SKHA_SKKDR3       (*(vuint32*)(void*)(&__IPSBAR[0x1B003C]))
+#define MCF_SKHA_SKKDR4       (*(vuint32*)(void*)(&__IPSBAR[0x1B0040]))
+#define MCF_SKHA_SKKDR5       (*(vuint32*)(void*)(&__IPSBAR[0x1B0044]))
+#define MCF_SKHA_SKKDRn(x)    (*(vuint32*)(void*)(&__IPSBAR[0x1B0030+((x)*0x004)]))
+#define MCF_SKHA_SKCR0        (*(vuint32*)(void*)(&__IPSBAR[0x1B0070]))
+#define MCF_SKHA_SKCR1        (*(vuint32*)(void*)(&__IPSBAR[0x1B0074]))
+#define MCF_SKHA_SKCR2        (*(vuint32*)(void*)(&__IPSBAR[0x1B0078]))
+#define MCF_SKHA_SKCR3        (*(vuint32*)(void*)(&__IPSBAR[0x1B007C]))
+#define MCF_SKHA_SKCR4        (*(vuint32*)(void*)(&__IPSBAR[0x1B0080]))
+#define MCF_SKHA_SKCR5        (*(vuint32*)(void*)(&__IPSBAR[0x1B0084]))
+#define MCF_SKHA_SKCR6        (*(vuint32*)(void*)(&__IPSBAR[0x1B0088]))
+#define MCF_SKHA_SKCR7        (*(vuint32*)(void*)(&__IPSBAR[0x1B008C]))
+#define MCF_SKHA_SKCR8        (*(vuint32*)(void*)(&__IPSBAR[0x1B0090]))
+#define MCF_SKHA_SKCR9        (*(vuint32*)(void*)(&__IPSBAR[0x1B0094]))
+#define MCF_SKHA_SKCR10       (*(vuint32*)(void*)(&__IPSBAR[0x1B0098]))
+#define MCF_SKHA_SKCR11       (*(vuint32*)(void*)(&__IPSBAR[0x1B009C]))
+#define MCF_SKHA_SKCRn(x)     (*(vuint32*)(void*)(&__IPSBAR[0x1B0070+((x)*0x004)]))
+
+/* Bit definitions and macros for MCF_SKHA_SKMR */
+#define MCF_SKHA_SKMR_ALG(x)         (((x)&0x00000003)<<0)
+#define MCF_SKHA_SKMR_DIR            (0x00000004)
+#define MCF_SKHA_SKMR_CM(x)          (((x)&0x00000003)<<3)
+#define MCF_SKHA_SKMR_DKP            (0x00000100)
+#define MCF_SKHA_SKMR_CTRM(x)        (((x)&0x0000000F)<<9)
+#define MCF_SKHA_SKMR_CM_ECB         (0x00000000)
+#define MCF_SKHA_SKMR_CM_CBC         (0x00000008)
+#define MCF_SKHA_SKMR_CM_CTR         (0x00000018)
+#define MCF_SKHA_SKMR_DIR_DEC        (0x00000000)
+#define MCF_SKHA_SKMR_DIR_ENC        (0x00000004)
+#define MCF_SKHA_SKMR_ALG_AES        (0x00000000)
+#define MCF_SKHA_SKMR_ALG_DES        (0x00000001)
+#define MCF_SKHA_SKMR_ALG_TDES       (0x00000002)
+
+/* Bit definitions and macros for MCF_SKHA_SKCR */
+#define MCF_SKHA_SKCR_IE             (0x00000001)
+
+/* Bit definitions and macros for MCF_SKHA_SKCMR */
+#define MCF_SKHA_SKCMR_SWR           (0x00000001)
+#define MCF_SKHA_SKCMR_RI            (0x00000002)
+#define MCF_SKHA_SKCMR_CI            (0x00000004)
+#define MCF_SKHA_SKCMR_GO            (0x00000008)
+
+/* Bit definitions and macros for MCF_SKHA_SKSR */
+#define MCF_SKHA_SKSR_INT            (0x00000001)
+#define MCF_SKHA_SKSR_DONE           (0x00000002)
+#define MCF_SKHA_SKSR_ERR            (0x00000004)
+#define MCF_SKHA_SKSR_RD             (0x00000008)
+#define MCF_SKHA_SKSR_BUSY           (0x00000010)
+#define MCF_SKHA_SKSR_IFL(x)         (((x)&0x000000FF)<<16)
+#define MCF_SKHA_SKSR_OFL(x)         (((x)&0x000000FF)<<24)
+
+/* Bit definitions and macros for MCF_SKHA_SKIR */
+#define MCF_SKHA_SKIR_IFO            (0x00000001)
+#define MCF_SKHA_SKIR_OFU            (0x00000002)
+#define MCF_SKHA_SKIR_NEIF           (0x00000004)
+#define MCF_SKHA_SKIR_NEOF           (0x00000008)
+#define MCF_SKHA_SKIR_IME            (0x00000010)
+#define MCF_SKHA_SKIR_DSE            (0x00000020)
+#define MCF_SKHA_SKIR_KSE            (0x00000040)
+#define MCF_SKHA_SKIR_RMDP           (0x00000080)
+#define MCF_SKHA_SKIR_ERE            (0x00000100)
+#define MCF_SKHA_SKIR_KPE            (0x00000200)
+#define MCF_SKHA_SKIR_KRE            (0x00000400)
+
+/* Bit definitions and macros for MCF_SKHA_SKIMR */
+#define MCF_SKHA_SKIMR_IFO           (0x00000001)
+#define MCF_SKHA_SKIMR_OFU           (0x00000002)
+#define MCF_SKHA_SKIMR_NEIF          (0x00000004)
+#define MCF_SKHA_SKIMR_NEOF          (0x00000008)
+#define MCF_SKHA_SKIMR_IME           (0x00000010)
+#define MCF_SKHA_SKIMR_DSE           (0x00000020)
+#define MCF_SKHA_SKIMR_KSE           (0x00000040)
+#define MCF_SKHA_SKIMR_RMDP          (0x00000080)
+#define MCF_SKHA_SKIMR_ERE           (0x00000100)
+#define MCF_SKHA_SKIMR_KPE           (0x00000200)
+#define MCF_SKHA_SKIMR_KRE           (0x00000400)
+
+/* Bit definitions and macros for MCF_SKHA_SKKSR */
+#define MCF_SKHA_SKKSR_KEYSIZE(x)    (((x)&0x0000003F)<<0)
+
+/********************************************************************/
+
+#endif /* __MCF523X_SKHA_H__ */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_sram.h b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_sram.h
new file mode 100644
index 000000000..74626c2be
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_sram.h
@@ -0,0 +1,42 @@
+/*
+ * These files are taken from the MCF523X source code example package
+ * which is available on the Freescale website. Freescale explicitly 
+ * grants the redistribution and modification of these source files.
+ * The complete licensing information is available in the file 
+ * LICENSE_FREESCALE.TXT.
+ *
+ * File:	mcf523x_sram.h
+ * Purpose:	Register and bit definitions for the MCF523X
+ *
+ * Notes:	
+ *	
+ */
+
+#ifndef __MCF523X_SRAM_H__
+#define __MCF523X_SRAM_H__
+
+/*********************************************************************
+*
+* 64KByte System SRAM (SRAM)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_SRAM_RAMBAR    (*(vuint32*)(void*)(&__IPSBAR[0x20000000]))
+
+/* Bit definitions and macros for MCF_SRAM_RAMBAR */
+#define MCF_SRAM_RAMBAR_V        (0x00000001)
+#define MCF_SRAM_RAMBAR_UD       (0x00000002)
+#define MCF_SRAM_RAMBAR_UC       (0x00000004)
+#define MCF_SRAM_RAMBAR_SD       (0x00000008)
+#define MCF_SRAM_RAMBAR_SC       (0x00000010)
+#define MCF_SRAM_RAMBAR_CI       (0x00000020)
+#define MCF_SRAM_RAMBAR_WP       (0x00000100)
+#define MCF_SRAM_RAMBAR_SPV      (0x00000200)
+#define MCF_SRAM_RAMBAR_PRI2     (0x00000400)
+#define MCF_SRAM_RAMBAR_PRI1     (0x00000800)
+#define MCF_SRAM_RAMBAR_BA(x)    (((x)&0x0000FFFF)<<16)
+
+/********************************************************************/
+
+#endif /* __MCF523X_SRAM_H__ */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_timer.h b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_timer.h
new file mode 100644
index 000000000..359e895f7
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_timer.h
@@ -0,0 +1,83 @@
+/*
+ * These files are taken from the MCF523X source code example package
+ * which is available on the Freescale website. Freescale explicitly 
+ * grants the redistribution and modification of these source files.
+ * The complete licensing information is available in the file 
+ * LICENSE_FREESCALE.TXT.
+ *
+ * File:	mcf523x_timer.h
+ * Purpose:	Register and bit definitions for the MCF523X
+ *
+ * Notes:	
+ *	
+ */
+
+#ifndef __MCF523X_TIMER_H__
+#define __MCF523X_TIMER_H__
+
+/*********************************************************************
+*
+* DMA Timers (TIMER)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_TIMER_DTMR0       (*(vuint16*)(void*)(&__IPSBAR[0x000400]))
+#define MCF_TIMER_DTXMR0      (*(vuint8 *)(void*)(&__IPSBAR[0x000402]))
+#define MCF_TIMER_DTER0       (*(vuint8 *)(void*)(&__IPSBAR[0x000403]))
+#define MCF_TIMER_DTRR0       (*(vuint32*)(void*)(&__IPSBAR[0x000404]))
+#define MCF_TIMER_DTCR0       (*(vuint32*)(void*)(&__IPSBAR[0x000408]))
+#define MCF_TIMER_DTCN0       (*(vuint32*)(void*)(&__IPSBAR[0x00040C]))
+#define MCF_TIMER_DTMR1       (*(vuint16*)(void*)(&__IPSBAR[0x000440]))
+#define MCF_TIMER_DTXMR1      (*(vuint8 *)(void*)(&__IPSBAR[0x000442]))
+#define MCF_TIMER_DTER1       (*(vuint8 *)(void*)(&__IPSBAR[0x000443]))
+#define MCF_TIMER_DTRR1       (*(vuint32*)(void*)(&__IPSBAR[0x000444]))
+#define MCF_TIMER_DTCR1       (*(vuint32*)(void*)(&__IPSBAR[0x000448]))
+#define MCF_TIMER_DTCN1       (*(vuint32*)(void*)(&__IPSBAR[0x00044C]))
+#define MCF_TIMER_DTMR2       (*(vuint16*)(void*)(&__IPSBAR[0x000480]))
+#define MCF_TIMER_DTXMR2      (*(vuint8 *)(void*)(&__IPSBAR[0x000482]))
+#define MCF_TIMER_DTER2       (*(vuint8 *)(void*)(&__IPSBAR[0x000483]))
+#define MCF_TIMER_DTRR2       (*(vuint32*)(void*)(&__IPSBAR[0x000484]))
+#define MCF_TIMER_DTCR2       (*(vuint32*)(void*)(&__IPSBAR[0x000488]))
+#define MCF_TIMER_DTCN2       (*(vuint32*)(void*)(&__IPSBAR[0x00048C]))
+#define MCF_TIMER_DTMR3       (*(vuint16*)(void*)(&__IPSBAR[0x0004C0]))
+#define MCF_TIMER_DTXMR3      (*(vuint8 *)(void*)(&__IPSBAR[0x0004C2]))
+#define MCF_TIMER_DTER3       (*(vuint8 *)(void*)(&__IPSBAR[0x0004C3]))
+#define MCF_TIMER_DTRR3       (*(vuint32*)(void*)(&__IPSBAR[0x0004C4]))
+#define MCF_TIMER_DTCR3       (*(vuint32*)(void*)(&__IPSBAR[0x0004C8]))
+#define MCF_TIMER_DTCN3       (*(vuint32*)(void*)(&__IPSBAR[0x0004CC]))
+#define MCF_TIMER_DTMR(x)     (*(vuint16*)(void*)(&__IPSBAR[0x000400+((x)*0x040)]))
+#define MCF_TIMER_DTXMR(x)    (*(vuint8 *)(void*)(&__IPSBAR[0x000402+((x)*0x040)]))
+#define MCF_TIMER_DTER(x)     (*(vuint8 *)(void*)(&__IPSBAR[0x000403+((x)*0x040)]))
+#define MCF_TIMER_DTRR(x)     (*(vuint32*)(void*)(&__IPSBAR[0x000404+((x)*0x040)]))
+#define MCF_TIMER_DTCR(x)     (*(vuint32*)(void*)(&__IPSBAR[0x000408+((x)*0x040)]))
+#define MCF_TIMER_DTCN(x)     (*(vuint32*)(void*)(&__IPSBAR[0x00040C+((x)*0x040)]))
+
+/* Bit definitions and macros for MCF_TIMER_DTMR */
+#define MCF_TIMER_DTMR_RST          (0x0001)
+#define MCF_TIMER_DTMR_CLK(x)       (((x)&0x0003)<<1)
+#define MCF_TIMER_DTMR_FRR          (0x0008)
+#define MCF_TIMER_DTMR_ORRI         (0x0010)
+#define MCF_TIMER_DTMR_OM           (0x0020)
+#define MCF_TIMER_DTMR_CE(x)        (((x)&0x0003)<<6)
+#define MCF_TIMER_DTMR_PS(x)        (((x)&0x00FF)<<8)
+#define MCF_TIMER_DTMR_CE_ANY       (0x00C0)
+#define MCF_TIMER_DTMR_CE_FALL      (0x0080)
+#define MCF_TIMER_DTMR_CE_RISE      (0x0040)
+#define MCF_TIMER_DTMR_CE_NONE      (0x0000)
+#define MCF_TIMER_DTMR_CLK_DTIN     (0x0006)
+#define MCF_TIMER_DTMR_CLK_DIV16    (0x0004)
+#define MCF_TIMER_DTMR_CLK_DIV1     (0x0002)
+#define MCF_TIMER_DTMR_CLK_STOP     (0x0000)
+
+/* Bit definitions and macros for MCF_TIMER_DTXMR */
+#define MCF_TIMER_DTXMR_MODE16      (0x01)
+#define MCF_TIMER_DTXMR_DMAEN       (0x80)
+
+/* Bit definitions and macros for MCF_TIMER_DTER */
+#define MCF_TIMER_DTER_CAP          (0x01)
+#define MCF_TIMER_DTER_REF          (0x02)
+
+/********************************************************************/
+
+#endif /* __MCF523X_TIMER_H__ */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_uart.h b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_uart.h
new file mode 100644
index 000000000..f70a71c4e
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_uart.h
@@ -0,0 +1,186 @@
+/*
+ * These files are taken from the MCF523X source code example package
+ * which is available on the Freescale website. Freescale explicitly 
+ * grants the redistribution and modification of these source files.
+ * The complete licensing information is available in the file 
+ * LICENSE_FREESCALE.TXT.
+ *
+ * File:	mcf523x_uart.h
+ * Purpose:	Register and bit definitions for the MCF523X
+ *
+ * Notes:	
+ *	
+ */
+
+#ifndef __MCF523X_UART_H__
+#define __MCF523X_UART_H__
+
+/*********************************************************************
+*
+* Universal Asynchronous Receiver Transmitter (UART)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_UART_UMR0        (*(vuint8 *)(void*)(&__IPSBAR[0x000200]))
+#define MCF_UART_USR0        (*(vuint8 *)(void*)(&__IPSBAR[0x000204]))
+#define MCF_UART_UCSR0       (*(vuint8 *)(void*)(&__IPSBAR[0x000204]))
+#define MCF_UART_UCR0        (*(vuint8 *)(void*)(&__IPSBAR[0x000208]))
+#define MCF_UART_URB0        (*(vuint8 *)(void*)(&__IPSBAR[0x00020C]))
+#define MCF_UART_UTB0        (*(vuint8 *)(void*)(&__IPSBAR[0x00020C]))
+#define MCF_UART_UIPCR0      (*(vuint8 *)(void*)(&__IPSBAR[0x000210]))
+#define MCF_UART_UACR0       (*(vuint8 *)(void*)(&__IPSBAR[0x000210]))
+#define MCF_UART_UISR0       (*(vuint8 *)(void*)(&__IPSBAR[0x000214]))
+#define MCF_UART_UIMR0       (*(vuint8 *)(void*)(&__IPSBAR[0x000214]))
+#define MCF_UART_UBG10       (*(vuint8 *)(void*)(&__IPSBAR[0x000218]))
+#define MCF_UART_UBG20       (*(vuint8 *)(void*)(&__IPSBAR[0x00021C]))
+#define MCF_UART_UIP0        (*(vuint8 *)(void*)(&__IPSBAR[0x000234]))
+#define MCF_UART_UOP10       (*(vuint8 *)(void*)(&__IPSBAR[0x000238]))
+#define MCF_UART_UOP00       (*(vuint8 *)(void*)(&__IPSBAR[0x00023C]))
+#define MCF_UART_UMR1        (*(vuint8 *)(void*)(&__IPSBAR[0x000240]))
+#define MCF_UART_USR1        (*(vuint8 *)(void*)(&__IPSBAR[0x000244]))
+#define MCF_UART_UCSR1       (*(vuint8 *)(void*)(&__IPSBAR[0x000244]))
+#define MCF_UART_UCR1        (*(vuint8 *)(void*)(&__IPSBAR[0x000248]))
+#define MCF_UART_URB1        (*(vuint8 *)(void*)(&__IPSBAR[0x00024C]))
+#define MCF_UART_UTB1        (*(vuint8 *)(void*)(&__IPSBAR[0x00024C]))
+#define MCF_UART_UIPCR1      (*(vuint8 *)(void*)(&__IPSBAR[0x000250]))
+#define MCF_UART_UACR1       (*(vuint8 *)(void*)(&__IPSBAR[0x000250]))
+#define MCF_UART_UISR1       (*(vuint8 *)(void*)(&__IPSBAR[0x000254]))
+#define MCF_UART_UIMR1       (*(vuint8 *)(void*)(&__IPSBAR[0x000254]))
+#define MCF_UART_UBG11       (*(vuint8 *)(void*)(&__IPSBAR[0x000258]))
+#define MCF_UART_UBG21       (*(vuint8 *)(void*)(&__IPSBAR[0x00025C]))
+#define MCF_UART_UIP1        (*(vuint8 *)(void*)(&__IPSBAR[0x000274]))
+#define MCF_UART_UOP11       (*(vuint8 *)(void*)(&__IPSBAR[0x000278]))
+#define MCF_UART_UOP01       (*(vuint8 *)(void*)(&__IPSBAR[0x00027C]))
+#define MCF_UART_UMR2        (*(vuint8 *)(void*)(&__IPSBAR[0x000280]))
+#define MCF_UART_USR2        (*(vuint8 *)(void*)(&__IPSBAR[0x000284]))
+#define MCF_UART_UCSR2       (*(vuint8 *)(void*)(&__IPSBAR[0x000284]))
+#define MCF_UART_UCR2        (*(vuint8 *)(void*)(&__IPSBAR[0x000288]))
+#define MCF_UART_URB2        (*(vuint8 *)(void*)(&__IPSBAR[0x00028C]))
+#define MCF_UART_UTB2        (*(vuint8 *)(void*)(&__IPSBAR[0x00028C]))
+#define MCF_UART_UIPCR2      (*(vuint8 *)(void*)(&__IPSBAR[0x000290]))
+#define MCF_UART_UACR2       (*(vuint8 *)(void*)(&__IPSBAR[0x000290]))
+#define MCF_UART_UISR2       (*(vuint8 *)(void*)(&__IPSBAR[0x000294]))
+#define MCF_UART_UIMR2       (*(vuint8 *)(void*)(&__IPSBAR[0x000294]))
+#define MCF_UART_UBG12       (*(vuint8 *)(void*)(&__IPSBAR[0x000298]))
+#define MCF_UART_UBG22       (*(vuint8 *)(void*)(&__IPSBAR[0x00029C]))
+#define MCF_UART_UIP2        (*(vuint8 *)(void*)(&__IPSBAR[0x0002B4]))
+#define MCF_UART_UOP12       (*(vuint8 *)(void*)(&__IPSBAR[0x0002B8]))
+#define MCF_UART_UOP02       (*(vuint8 *)(void*)(&__IPSBAR[0x0002BC]))
+#define MCF_UART_UMR(x)      (*(vuint8 *)(void*)(&__IPSBAR[0x000200+((x)*0x040)]))
+#define MCF_UART_USR(x)      (*(vuint8 *)(void*)(&__IPSBAR[0x000204+((x)*0x040)]))
+#define MCF_UART_UCSR(x)     (*(vuint8 *)(void*)(&__IPSBAR[0x000204+((x)*0x040)]))
+#define MCF_UART_UCR(x)      (*(vuint8 *)(void*)(&__IPSBAR[0x000208+((x)*0x040)]))
+#define MCF_UART_URB(x)      (*(vuint8 *)(void*)(&__IPSBAR[0x00020C+((x)*0x040)]))
+#define MCF_UART_UTB(x)      (*(vuint8 *)(void*)(&__IPSBAR[0x00020C+((x)*0x040)]))
+#define MCF_UART_UIPCR(x)    (*(vuint8 *)(void*)(&__IPSBAR[0x000210+((x)*0x040)]))
+#define MCF_UART_UACR(x)     (*(vuint8 *)(void*)(&__IPSBAR[0x000210+((x)*0x040)]))
+#define MCF_UART_UISR(x)     (*(vuint8 *)(void*)(&__IPSBAR[0x000214+((x)*0x040)]))
+#define MCF_UART_UIMR(x)     (*(vuint8 *)(void*)(&__IPSBAR[0x000214+((x)*0x040)]))
+#define MCF_UART_UBG1(x)     (*(vuint8 *)(void*)(&__IPSBAR[0x000218+((x)*0x040)]))
+#define MCF_UART_UBG2(x)     (*(vuint8 *)(void*)(&__IPSBAR[0x00021C+((x)*0x040)]))
+#define MCF_UART_UIP(x)      (*(vuint8 *)(void*)(&__IPSBAR[0x000234+((x)*0x040)]))
+#define MCF_UART_UOP1(x)     (*(vuint8 *)(void*)(&__IPSBAR[0x000238+((x)*0x040)]))
+#define MCF_UART_UOP0(x)     (*(vuint8 *)(void*)(&__IPSBAR[0x00023C+((x)*0x040)]))
+
+/* Bit definitions and macros for MCF_UART_UMR */
+#define MCF_UART_UMR_BC(x)              (((x)&0x03)<<0)
+#define MCF_UART_UMR_PT                 (0x04)
+#define MCF_UART_UMR_PM(x)              (((x)&0x03)<<3)
+#define MCF_UART_UMR_ERR                (0x20)
+#define MCF_UART_UMR_RXIRQ              (0x40)
+#define MCF_UART_UMR_RXRTS              (0x80)
+#define MCF_UART_UMR_SB(x)              (((x)&0x0F)<<0)
+#define MCF_UART_UMR_TXCTS              (0x10)
+#define MCF_UART_UMR_TXRTS              (0x20)
+#define MCF_UART_UMR_CM(x)              (((x)&0x03)<<6)
+#define MCF_UART_UMR_PM_MULTI_ADDR      (0x1C)
+#define MCF_UART_UMR_PM_MULTI_DATA      (0x18)
+#define MCF_UART_UMR_PM_NONE            (0x10)
+#define MCF_UART_UMR_PM_FORCE_HI        (0x0C)
+#define MCF_UART_UMR_PM_FORCE_LO        (0x08)
+#define MCF_UART_UMR_PM_ODD             (0x04)
+#define MCF_UART_UMR_PM_EVEN            (0x00)
+#define MCF_UART_UMR_BC_5               (0x00)
+#define MCF_UART_UMR_BC_6               (0x01)
+#define MCF_UART_UMR_BC_7               (0x02)
+#define MCF_UART_UMR_BC_8               (0x03)
+#define MCF_UART_UMR_CM_NORMAL          (0x00)
+#define MCF_UART_UMR_CM_ECHO            (0x40)
+#define MCF_UART_UMR_CM_LOCAL_LOOP      (0x80)
+#define MCF_UART_UMR_CM_REMOTE_LOOP     (0xC0)
+#define MCF_UART_UMR_SB_STOP_BITS_1     (0x07)
+#define MCF_UART_UMR_SB_STOP_BITS_15    (0x08)
+#define MCF_UART_UMR_SB_STOP_BITS_2     (0x0F)
+
+/* Bit definitions and macros for MCF_UART_USR */
+#define MCF_UART_USR_RXRDY              (0x01)
+#define MCF_UART_USR_FFULL              (0x02)
+#define MCF_UART_USR_TXRDY              (0x04)
+#define MCF_UART_USR_TXEMP              (0x08)
+#define MCF_UART_USR_OE                 (0x10)
+#define MCF_UART_USR_PE                 (0x20)
+#define MCF_UART_USR_FE                 (0x40)
+#define MCF_UART_USR_RB                 (0x80)
+
+/* Bit definitions and macros for MCF_UART_UCSR */
+#define MCF_UART_UCSR_TCS(x)            (((x)&0x0F)<<0)
+#define MCF_UART_UCSR_RCS(x)            (((x)&0x0F)<<4)
+#define MCF_UART_UCSR_RCS_SYS_CLK       (0xD0)
+#define MCF_UART_UCSR_RCS_CTM16         (0xE0)
+#define MCF_UART_UCSR_RCS_CTM           (0xF0)
+#define MCF_UART_UCSR_TCS_SYS_CLK       (0x0D)
+#define MCF_UART_UCSR_TCS_CTM16         (0x0E)
+#define MCF_UART_UCSR_TCS_CTM           (0x0F)
+
+/* Bit definitions and macros for MCF_UART_UCR */
+#define MCF_UART_UCR_RXC(x)             (((x)&0x03)<<0)
+#define MCF_UART_UCR_TXC(x)             (((x)&0x03)<<2)
+#define MCF_UART_UCR_MISC(x)            (((x)&0x07)<<4)
+#define MCF_UART_UCR_NONE               (0x00)
+#define MCF_UART_UCR_STOP_BREAK         (0x70)
+#define MCF_UART_UCR_START_BREAK        (0x60)
+#define MCF_UART_UCR_BKCHGINT           (0x50)
+#define MCF_UART_UCR_RESET_ERROR        (0x40)
+#define MCF_UART_UCR_RESET_TX           (0x30)
+#define MCF_UART_UCR_RESET_RX           (0x20)
+#define MCF_UART_UCR_RESET_MR           (0x10)
+#define MCF_UART_UCR_TX_DISABLED        (0x08)
+#define MCF_UART_UCR_TX_ENABLED         (0x04)
+#define MCF_UART_UCR_RX_DISABLED        (0x02)
+#define MCF_UART_UCR_RX_ENABLED         (0x01)
+
+/* Bit definitions and macros for MCF_UART_UIPCR */
+#define MCF_UART_UIPCR_CTS              (0x01)
+#define MCF_UART_UIPCR_COS              (0x10)
+
+/* Bit definitions and macros for MCF_UART_UACR */
+#define MCF_UART_UACR_IEC               (0x01)
+
+/* Bit definitions and macros for MCF_UART_UISR */
+#define MCF_UART_UISR_TXRDY             (0x01)
+#define MCF_UART_UISR_RXRDY_FU          (0x02)
+#define MCF_UART_UISR_DB                (0x04)
+#define MCF_UART_UISR_RXFTO             (0x08)
+#define MCF_UART_UISR_TXFIFO            (0x10)
+#define MCF_UART_UISR_RXFIFO            (0x20)
+#define MCF_UART_UISR_COS               (0x80)
+
+/* Bit definitions and macros for MCF_UART_UIMR */
+#define MCF_UART_UIMR_TXRDY             (0x01)
+#define MCF_UART_UIMR_RXRDY_FU          (0x02)
+#define MCF_UART_UIMR_DB                (0x04)
+#define MCF_UART_UIMR_COS               (0x80)
+
+/* Bit definitions and macros for MCF_UART_UIP */
+#define MCF_UART_UIP_CTS                (0x01)
+
+/* Bit definitions and macros for MCF_UART_UOP1 */
+#define MCF_UART_UOP1_RTS               (0x01)
+
+/* Bit definitions and macros for MCF_UART_UOP0 */
+#define MCF_UART_UOP0_RTS               (0x01)
+
+/********************************************************************/
+
+#endif /* __MCF523X_UART_H__ */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_wtm.h b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_wtm.h
new file mode 100644
index 000000000..1e5f9f97f
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_wtm.h
@@ -0,0 +1,92 @@
+/*
+ * These files are taken from the MCF523X source code example package
+ * which is available on the Freescale website. Freescale explicitly 
+ * grants the redistribution and modification of these source files.
+ * The complete licensing information is available in the file 
+ * LICENSE_FREESCALE.TXT.
+ *
+ * File:	mcf523x_wtm.h
+ * Purpose:	Register and bit definitions for the MCF523X
+ *
+ * Notes:	
+ *	
+ */
+
+#ifndef __MCF523X_WTM_H__
+#define __MCF523X_WTM_H__
+
+/*********************************************************************
+*
+* Watchdog Timer Modules (WTM)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_WTM_WCR      (*(vuint16*)(void*)(&__IPSBAR[0x140000]))
+#define MCF_WTM_WMR      (*(vuint16*)(void*)(&__IPSBAR[0x140002]))
+#define MCF_WTM_WCNTR    (*(vuint16*)(void*)(&__IPSBAR[0x140004]))
+#define MCF_WTM_WSR      (*(vuint16*)(void*)(&__IPSBAR[0x140006]))
+
+/* Bit definitions and macros for MCF_WTM_WCR */
+#define MCF_WTM_WCR_EN        (0x0001)
+#define MCF_WTM_WCR_HALTED    (0x0002)
+#define MCF_WTM_WCR_DOZE      (0x0004)
+#define MCF_WTM_WCR_WAIT      (0x0008)
+
+/* Bit definitions and macros for MCF_WTM_WMR */
+#define MCF_WTM_WMR_WM0       (0x0001)
+#define MCF_WTM_WMR_WM1       (0x0002)
+#define MCF_WTM_WMR_WM2       (0x0004)
+#define MCF_WTM_WMR_WM3       (0x0008)
+#define MCF_WTM_WMR_WM4       (0x0010)
+#define MCF_WTM_WMR_WM5       (0x0020)
+#define MCF_WTM_WMR_WM6       (0x0040)
+#define MCF_WTM_WMR_WM7       (0x0080)
+#define MCF_WTM_WMR_WM8       (0x0100)
+#define MCF_WTM_WMR_WM9       (0x0200)
+#define MCF_WTM_WMR_WM10      (0x0400)
+#define MCF_WTM_WMR_WM11      (0x0800)
+#define MCF_WTM_WMR_WM12      (0x1000)
+#define MCF_WTM_WMR_WM13      (0x2000)
+#define MCF_WTM_WMR_WM14      (0x4000)
+#define MCF_WTM_WMR_WM15      (0x8000)
+
+/* Bit definitions and macros for MCF_WTM_WCNTR */
+#define MCF_WTM_WCNTR_WC0     (0x0001)
+#define MCF_WTM_WCNTR_WC1     (0x0002)
+#define MCF_WTM_WCNTR_WC2     (0x0004)
+#define MCF_WTM_WCNTR_WC3     (0x0008)
+#define MCF_WTM_WCNTR_WC4     (0x0010)
+#define MCF_WTM_WCNTR_WC5     (0x0020)
+#define MCF_WTM_WCNTR_WC6     (0x0040)
+#define MCF_WTM_WCNTR_WC7     (0x0080)
+#define MCF_WTM_WCNTR_WC8     (0x0100)
+#define MCF_WTM_WCNTR_WC9     (0x0200)
+#define MCF_WTM_WCNTR_WC10    (0x0400)
+#define MCF_WTM_WCNTR_WC11    (0x0800)
+#define MCF_WTM_WCNTR_WC12    (0x1000)
+#define MCF_WTM_WCNTR_WC13    (0x2000)
+#define MCF_WTM_WCNTR_WC14    (0x4000)
+#define MCF_WTM_WCNTR_WC15    (0x8000)
+
+/* Bit definitions and macros for MCF_WTM_WSR */
+#define MCF_WTM_WSR_WS0       (0x0001)
+#define MCF_WTM_WSR_WS1       (0x0002)
+#define MCF_WTM_WSR_WS2       (0x0004)
+#define MCF_WTM_WSR_WS3       (0x0008)
+#define MCF_WTM_WSR_WS4       (0x0010)
+#define MCF_WTM_WSR_WS5       (0x0020)
+#define MCF_WTM_WSR_WS6       (0x0040)
+#define MCF_WTM_WSR_WS7       (0x0080)
+#define MCF_WTM_WSR_WS8       (0x0100)
+#define MCF_WTM_WSR_WS9       (0x0200)
+#define MCF_WTM_WSR_WS10      (0x0400)
+#define MCF_WTM_WSR_WS11      (0x0800)
+#define MCF_WTM_WSR_WS12      (0x1000)
+#define MCF_WTM_WSR_WS13      (0x2000)
+#define MCF_WTM_WSR_WS14      (0x4000)
+#define MCF_WTM_WSR_WS15      (0x8000)
+
+/********************************************************************/
+
+#endif /* __MCF523X_WTM_H__ */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf5xxx.h b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf5xxx.h
new file mode 100644
index 000000000..01153e409
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/include/arch/mcf5xxx.h
@@ -0,0 +1,196 @@
+/*
+ * These files are taken from the MCF523X source code example package
+ * which is available on the Freescale website. Freescale explicitly 
+ * grants the redistribution and modification of these source files.
+ * The complete licensing information is available in the file 
+ * LICENSE_FREESCALE.TXT.
+ *
+ * File:		mcf5xxx.h
+ * Purpose:		Definitions common to all ColdFire processors
+ *
+ * Notes:
+ */
+
+#ifndef _CPU_MCF5XXX_H
+#define _CPU_MCF5XXX_H
+
+/***********************************************************************/
+/*
+ * Misc. Defines
+ */
+
+#ifdef	FALSE
+#undef	FALSE
+#endif
+#define FALSE	(0)
+
+#ifdef	TRUE
+#undef	TRUE
+#endif
+#define	TRUE	(1)
+
+#ifdef	NULL
+#undef	NULL
+#endif
+#define NULL	(0)
+
+/***********************************************************************/
+/*
+ * The basic data types
+ */
+
+typedef unsigned char		uint8;  /*  8 bits */
+typedef unsigned short int	uint16; /* 16 bits */
+typedef unsigned long int	uint32; /* 32 bits */
+
+typedef signed char			int8;   /*  8 bits */
+typedef signed short int	int16;  /* 16 bits */
+typedef signed long int		int32;  /* 32 bits */
+
+typedef volatile uint8		vuint8;  /*  8 bits */
+typedef volatile uint16		vuint16; /* 16 bits */
+typedef volatile uint32		vuint32; /* 32 bits */
+
+/***********************************************************************/
+/*
+ * Common M68K & ColdFire definitions
+ */
+
+#define ADDRESS			uint32
+#define INSTRUCTION		uint16
+#define ILLEGAL			0x4AFC
+#define CPU_WORD_SIZE	16
+
+#define MCF5XXX_SR_T		(0x8000)
+#define MCF5XXX_SR_S		(0x2000)
+#define MCF5XXX_SR_M		(0x1000)
+#define MCF5XXX_SR_IPL		(0x0700)
+#define MCF5XXX_SR_IPL_0	(0x0000)
+#define MCF5XXX_SR_IPL_1	(0x0100)
+#define MCF5XXX_SR_IPL_2	(0x0200)
+#define MCF5XXX_SR_IPL_3	(0x0300)
+#define MCF5XXX_SR_IPL_4	(0x0400)
+#define MCF5XXX_SR_IPL_5	(0x0500)
+#define MCF5XXX_SR_IPL_6	(0x0600)
+#define MCF5XXX_SR_IPL_7	(0x0700)
+#define MCF5XXX_SR_X		(0x0010)
+#define MCF5XXX_SR_N		(0x0008)
+#define MCF5XXX_SR_Z		(0x0004)
+#define MCF5XXX_SR_V		(0x0002)
+#define MCF5XXX_SR_C		(0x0001)
+
+#define MCF5XXX_CACR_CENB		(0x80000000)
+#define MCF5XXX_CACR_CPDI		(0x10000000)
+#define MCF5XXX_CACR_CPD		(0x10000000)
+#define MCF5XXX_CACR_CFRZ		(0x08000000)
+#define MCF5XXX_CACR_CINV		(0x01000000)
+#define MCF5XXX_CACR_DIDI		(0x00800000)
+#define MCF5XXX_CACR_DISD		(0x00400000)
+#define MCF5XXX_CACR_INVI		(0x00200000)
+#define MCF5XXX_CACR_INVD		(0x00100000)
+#define MCF5XXX_CACR_CEIB		(0x00000400)
+#define MCF5XXX_CACR_DCM_WR		(0x00000000)
+#define MCF5XXX_CACR_DCM_CB		(0x00000100)
+#define MCF5XXX_CACR_DCM_IP		(0x00000200)
+#define MCF5XXX_CACR_DCM		(0x00000200)
+#define MCF5XXX_CACR_DCM_II		(0x00000300)
+#define MCF5XXX_CACR_DBWE		(0x00000100)
+#define MCF5XXX_CACR_DWP		(0x00000020)
+#define MCF5XXX_CACR_EUST		(0x00000010)
+#define MCF5XXX_CACR_CLNF_00	(0x00000000)
+#define MCF5XXX_CACR_CLNF_01	(0x00000002)
+#define MCF5XXX_CACR_CLNF_10	(0x00000004)
+#define MCF5XXX_CACR_CLNF_11	(0x00000006)
+
+#define MCF5XXX_ACR_AB(a)		((a)&0xFF000000)
+#define MCF5XXX_ACR_AM(a)		(((a)&0xFF000000) >> 8)
+#define MCF5XXX_ACR_EN			(0x00008000)
+#define MCF5XXX_ACR_SM_USER		(0x00000000)
+#define MCF5XXX_ACR_SM_SUPER	(0x00002000)
+#define MCF5XXX_ACR_SM_IGNORE	(0x00006000)
+#define MCF5XXX_ACR_ENIB		(0x00000080)
+#define MCF5XXX_ACR_CM			(0x00000040)
+#define MCF5XXX_ACR_DCM_WR		(0x00000000)
+#define MCF5XXX_ACR_DCM_CB		(0x00000020)
+#define MCF5XXX_ACR_DCM_IP		(0x00000040)
+#define MCF5XXX_ACR_DCM_II		(0x00000060)
+#define MCF5XXX_ACR_CM			(0x00000040)
+#define MCF5XXX_ACR_BWE			(0x00000020)
+#define MCF5XXX_ACR_WP			(0x00000004)
+
+#define MCF5XXX_RAMBAR_BA(a)	((a)&0xFFFFC000)
+#define MCF5XXX_RAMBAR_PRI_00	(0x00000000)
+#define MCF5XXX_RAMBAR_PRI_01	(0x00004000)
+#define MCF5XXX_RAMBAR_PRI_10	(0x00008000)
+#define MCF5XXX_RAMBAR_PRI_11	(0x0000C000)
+#define MCF5XXX_RAMBAR_WP		(0x00000100)
+#define MCF5XXX_RAMBAR_CI		(0x00000020)
+#define MCF5XXX_RAMBAR_SC		(0x00000010)
+#define MCF5XXX_RAMBAR_SD		(0x00000008)
+#define MCF5XXX_RAMBAR_UC		(0x00000004)
+#define MCF5XXX_RAMBAR_UD		(0x00000002)
+#define MCF5XXX_RAMBAR_V		(0x00000001)
+
+/***********************************************************************/
+/*
+ * The ColdFire family of processors has a simplified exception stack
+ * frame that looks like the following:
+ *
+ *              3322222222221111 111111
+ *              1098765432109876 5432109876543210
+ *           8 +----------------+----------------+
+ *             |         Program Counter         |
+ *           4 +----------------+----------------+
+ *             |FS/Fmt/Vector/FS|      SR        |
+ *   SP -->  0 +----------------+----------------+
+ *
+ * The stack self-aligns to a 4-byte boundary at an exception, with
+ * the FS/Fmt/Vector/FS field indicating the size of the adjustment
+ * (SP += 0,1,2,3 bytes).
+ */
+
+#define MCF5XXX_RD_SF_FORMAT(PTR)	\
+	((*((uint16 *)(PTR)) >> 12) & 0x00FF)
+
+#define MCF5XXX_RD_SF_VECTOR(PTR)	\
+	((*((uint16 *)(PTR)) >>  2) & 0x00FF)
+
+#define MCF5XXX_RD_SF_FS(PTR)		\
+	( ((*((uint16 *)(PTR)) & 0x0C00) >> 8) | (*((uint16 *)(PTR)) & 0x0003) )
+
+#define MCF5XXX_SF_SR(PTR)	*((uint16 *)(PTR)+1)
+#define MCF5XXX_SF_PC(PTR)	*((uint32 *)(PTR)+1)
+
+/********************************************************************/
+/*
+ * Functions provided by mcf5xxx.s
+ */
+ 
+int 	asm_set_ipl (uint32);
+void	mcf5xxx_wr_cacr (uint32);
+void	mcf5xxx_wr_acr0 (uint32);
+void	mcf5xxx_wr_acr1 (uint32);
+void	mcf5xxx_wr_acr2 (uint32);
+void	mcf5xxx_wr_acr3 (uint32);
+void	mcf5xxx_wr_other_a7 (uint32);
+void	mcf5xxx_wr_other_sp (uint32);
+void	mcf5xxx_wr_vbr (uint32);
+void	mcf5xxx_wr_macsr (uint32);
+void	mcf5xxx_wr_mask (uint32);
+void	mcf5xxx_wr_acc0 (uint32);
+void	mcf5xxx_wr_accext01 (uint32);
+void	mcf5xxx_wr_accext23 (uint32);
+void	mcf5xxx_wr_acc1 (uint32);
+void	mcf5xxx_wr_acc2 (uint32);
+void	mcf5xxx_wr_acc3 (uint32);
+void	mcf5xxx_wr_sr (uint32);
+void	mcf5xxx_wr_rambar0 (uint32);
+void	mcf5xxx_wr_rambar1 (uint32);
+void	mcf5xxx_wr_mbar (uint32);
+void	mcf5xxx_wr_mbar0 (uint32);
+void	mcf5xxx_wr_mbar1 (uint32);
+
+/********************************************************************/
+
+#endif	/* _CPU_MCF5XXX_H */
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/CHANGELOG b/20080212/Demo/lwIP_MCF5235_GCC/lwip/CHANGELOG
new file mode 100644
index 000000000..0bf28ac56
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/CHANGELOG
@@ -0,0 +1,596 @@
+FUTURE
+
+  * TODO: The lwIP source code makes some invalid assumptions on processor
+    word-length, storage sizes and alignment. See the mailing lists for
+    problems with exoteric (/DSP) architectures showing these problems.
+    We still have to fix some of these issues neatly.
+
+  * TODO: the ARP layer is not protected against concurrent access. If
+    you run from a multitasking OS, serialize access to ARP (called from
+    your network device driver and from a timeout thread.)
+
+  * TODO: the PPP code is broken in a few ways. There are namespace
+    collisions on BSD systems and many assumptions on word-length
+    (sizeof(int)). In ppp.c an assumption is made on the availability of
+    a thread subsystem. Either PPP needs to be moved to contrib/ports/???
+    or rearranged to be more generic.
+
+HISTORY
+
+(CVS HEAD)
+
+  * [New changes go here]
+
+(STABLE-1_1_1)
+
+  2006-03-03  Christiaan Simons
+  * ipv4/ip_frag.c: Added bound-checking assertions on ip_reassbitmap
+    access and added pbuf_alloc() return value checks.
+
+  2006-01-01  Leon Woestenberg 
+  * tcp_{in,out}.c, tcp_out.c: Removed 'even sndbuf' fix in TCP, which is
+    now handled by the checksum routine properly.
+
+  2006-02-27  Leon Woestenberg 
+   * pbuf.c: Fix alignment; pbuf_init() would not work unless
+     pbuf_pool_memory[] was properly aligned. (Patch by Curt McDowell.)
+
+  2005-12-20  Leon Woestenberg 
+  * tcp.c: Remove PCBs which stay in LAST_ACK state too long. Patch
+    submitted by Mitrani Hiroshi.
+    
+  2005-12-15  Christiaan Simons
+  * inet.c: Disabled the added summing routine to preserve code space.
+
+  2005-12-14  Leon Woestenberg 
+  * tcp_in.c: Duplicate FIN ACK race condition fix by Kelvin Lawson.
+    Added Curt McDowell's optimized checksumming routine for future
+    inclusion. Need to create test case for unaliged, aligned, odd,
+    even length combination of cases on various endianess machines.
+
+  2005-12-09  Christiaan Simons
+  * inet.c: Rewrote standard checksum routine in proper portable C.
+
+  2005-11-25  Christiaan Simons
+  * udp.c tcp.c: Removed SO_REUSE hack. Should reside in socket code only.
+  * *.c: introduced cc.h LWIP_DEBUG formatters matching the u16_t, s16_t,
+    u32_t, s32_t typedefs. This solves most debug word-length assumes.  
+
+  2005-07-17 Leon Woestenberg 
+  * inet.c: Fixed unaligned 16-bit access in the standard checksum
+    routine by Peter Jolasson.
+  * slipif.c: Fixed implementation assumption of single-pbuf datagrams.
+
+  2005-02-04 Leon Woestenberg 
+  * tcp_out.c: Fixed uninitialized 'queue' referenced in memerr branch.
+  * tcp_{out|in}.c: Applied patch fixing unaligned access.
+
+  2005-01-04 Leon Woestenberg 
+  * pbuf.c: Fixed missing semicolon after LWIP_DEBUG statement.
+
+  2005-01-03 Leon Woestenberg 
+  * udp.c: UDP pcb->recv() was called even when it was NULL.
+
+(STABLE-1_1_0)
+
+  2004-12-28 Leon Woestenberg 
+  * etharp.*: Disabled multiple packets on the ARP queue.
+    This clashes with TCP queueing.
+
+  2004-11-28 Leon Woestenberg 
+  * etharp.*: Fixed race condition from ARP request to ARP timeout.
+    Halved the ARP period, doubled the period counts.
+    ETHARP_MAX_PENDING now should be at least 2. This prevents
+    the counter from reaching 0 right away (which would allow
+    too little time for ARP responses to be received).
+    
+  2004-11-25 Leon Woestenberg 
+  * dhcp.c: Decline messages were not multicast but unicast.
+  * etharp.c: ETHARP_CREATE is renamed to ETHARP_TRY_HARD.
+    Do not try hard to insert arbitrary packet's source address,
+    etharp_ip_input() now calls etharp_update() without ETHARP_TRY_HARD. 
+    etharp_query() now always DOES call ETHARP_TRY_HARD so that users
+    querying an address will see it appear in the cache (DHCP could
+    suffer from this when a server invalidly gave an in-use address.)
+  * ipv4/ip_addr.h: Renamed ip_addr_maskcmp() to _netcmp() as we are
+    comparing network addresses (identifiers), not the network masks
+    themselves.
+  * ipv4/ip_addr.c: ip_addr_isbroadcast() now checks that the given
+    IP address actually belongs to the network of the given interface.
+
+  2004-11-24 Kieran Mansley 
+  * tcp.c: Increment pcb->snd_buf when ACK is received in SYN_SENT state.
+
+(STABLE-1_1_0-RC1)
+
+  2004-10-16 Kieran Mansley 
+  * tcp.c: Add code to tcp_recved() to send an ACK (window update) immediately,
+	even if one is already pending, if the rcv_wnd is above a threshold
+	(currently TCP_WND/2). This avoids waiting for a timer to expire to send a
+	delayed ACK in order to open the window if the stack is only receiving data.
+
+  2004-09-12 Kieran Mansley 
+  * tcp*.*: Retransmit time-out handling improvement by Sam Jansen.
+
+  2004-08-20 Tony Mountifield 
+  * etharp.c: Make sure the first pbuf queued on an ARP entry
+    is properly ref counted.
+
+  2004-07-27 Tony Mountifield 
+  * debug.h: Added (int) cast in LWIP_DEBUGF() to avoid compiler
+    warnings about comparison.
+  * pbuf.c: Stopped compiler complaining of empty if statement
+    when LWIP_DEBUGF() empty.  Closed an unclosed comment.
+  * tcp.c: Stopped compiler complaining of empty if statement
+    when LWIP_DEBUGF() empty.
+  * ip.h Corrected IPH_TOS() macro: returns a byte, so doesn't need htons().
+  * inet.c: Added a couple of casts to quiet the compiler.
+    No need to test isascii(c) before isdigit(c) or isxdigit(c).
+
+  2004-07-22 Tony Mountifield 
+  * inet.c: Made data types consistent in inet_ntoa().
+    Added casts for return values of checksum routines, to pacify compiler.
+  * ip_frag.c, tcp_out.c, sockets.c, pbuf.c
+    Small corrections to some debugging statements, to pacify compiler.
+
+  2004-07-21 Tony Mountifield 
+  * etharp.c: Removed spurious semicolon and added missing end-of-comment.
+  * ethernetif.c Updated low_level_output() to match prototype for
+    netif->linkoutput and changed low_level_input() similarly for consistency.
+  * api_msg.c: Changed recv_raw() from int to u8_t, to match prototype
+    of raw_recv() in raw.h and so avoid compiler error.
+  * sockets.c: Added trivial (int) cast to keep compiler happier.
+  * ip.c, netif.c Changed debug statements to use the tidier ip4_addrN() macros.
+  
+(STABLE-1_0_0)
+
+  ++ Changes:
+
+  2004-07-05 Leon Woestenberg 
+  * sockets.*: Restructured LWIP_PRIVATE_TIMEVAL. Make sure
+    your cc.h file defines this either 1 or 0. If non-defined,
+    defaults to 1.
+  * .c: Added  and  includes where used.
+  * etharp.c: Made some array indices unsigned.
+
+  2004-06-27 Leon Woestenberg 
+  * netif.*: Added netif_set_up()/down().
+  * dhcp.c: Changes to restart program flow.
+
+  2004-05-07 Leon Woestenberg 
+  * etharp.c: In find_entry(), instead of a list traversal per candidate, do a
+    single-pass lookup for different candidates. Should exploit locality.
+
+  2004-04-29 Leon Woestenberg 
+  * tcp*.c: Cleaned up source comment documentation for Doxygen processing.
+  * opt.h: ETHARP_ALWAYS_INSERT option removed to comply with ARP RFC.
+  * etharp.c: update_arp_entry() only adds new ARP entries when adviced to by
+    the caller. This deprecates the ETHARP_ALWAYS_INSERT overrule option.
+
+  ++ Bug fixes:
+
+  2004-04-27 Leon Woestenberg 
+  * etharp.c: Applied patch of bug #8708 by Toni Mountifield with a solution
+    suggested by Timmy Brolin. Fix for 32-bit processors that cannot access
+    non-aligned 32-bit words, such as soms 32-bit TCP/IP header fields. Fix
+    is to prefix the 14-bit Ethernet headers with two padding bytes.
+
+  2004-04-23 Leon Woestenberg 
+  * ip_addr.c: Fix in the ip_addr_isbroadcast() check.
+  * etharp.c: Fixed the case where the packet that initiates the ARP request
+    is not queued, and gets lost. Fixed the case where the packets destination
+    address is already known; we now always queue the packet and perform an ARP
+    request.
+  
+(STABLE-0_7_0)
+
+  ++ Bug fixes:
+
+  * Fixed TCP bug for SYN_SENT to ESTABLISHED state transition.
+  * Fixed TCP bug in dequeueing of FIN from out of order segment queue.
+  * Fixed two possible NULL references in rare cases.
+
+(STABLE-0_6_6)
+
+  ++ Bug fixes:
+
+  * Fixed DHCP which did not include the IP address in DECLINE messages.
+
+  ++ Changes:
+
+  * etharp.c has been hauled over a bit.
+
+(STABLE-0_6_5)
+
+  ++ Bug fixes:
+
+  * Fixed TCP bug induced by bad window resizing with unidirectional TCP traffic.
+  * Packets sent from ARP queue had invalid source hardware address.
+
+  ++ Changes:
+
+  * Pass-by ARP requests do now update the cache.
+
+  ++ New features:
+
+  * No longer dependent on ctype.h.
+  * New socket options.
+  * Raw IP pcb support.
+
+(STABLE-0_6_4)
+
+  ++ Bug fixes:
+
+  * Some debug formatters and casts fixed.
+  * Numereous fixes in PPP.
+
+  ++ Changes:
+
+  * DEBUGF now is LWIP_DEBUGF
+  * pbuf_dechain() has been re-enabled.
+  * Mentioned the changed use of CVS branches in README.
+
+(STABLE-0_6_3)
+
+  ++ Bug fixes:
+
+  * Fixed pool pbuf memory leak in pbuf_alloc().
+    Occured if not enough PBUF_POOL pbufs for a packet pbuf chain.
+    Reported by Savin Zlobec.
+
+  * PBUF_POOL chains had their tot_len field not set for non-first
+    pbufs. Fixed in pbuf_alloc().
+
+  ++ New features:
+
+  * Added PPP stack contributed by Marc Boucher
+
+  ++ Changes:
+
+  * Now drops short packets for ICMP/UDP/TCP protocols. More robust.
+
+  * ARP queueuing now queues the latest packet instead of the first.
+    This is the RFC recommended behaviour, but can be overridden in
+    lwipopts.h.
+
+(0.6.2)
+
+  ++ Bugfixes:
+
+  * TCP has been fixed to deal with the new use of the pbuf->ref
+    counter.
+
+  * DHCP dhcp_inform() crash bug fixed.
+
+  ++ Changes:
+
+  * Removed pbuf_pool_free_cache and pbuf_pool_alloc_cache. Also removed
+    pbuf_refresh(). This has sped up pbuf pool operations considerably.
+    Implemented by David Haas.
+
+(0.6.1)
+
+  ++ New features:
+
+  * The packet buffer implementation has been enhanced to support
+    zero-copy and copy-on-demand for packet buffers which have their
+    payloads in application-managed memory.
+    Implemented by David Haas.
+
+    Use PBUF_REF to make a pbuf refer to RAM. lwIP will use zero-copy
+    if an outgoing packet can be directly sent on the link, or perform
+    a copy-on-demand when necessary.
+
+    The application can safely assume the packet is sent, and the RAM
+    is available to the application directly after calling udp_send()
+    or similar function.
+
+  ++ Bugfixes:
+
+  * ARP_QUEUEING should now correctly work for all cases, including
+    PBUF_REF.
+    Implemented by Leon Woestenberg.
+
+  ++ Changes:
+
+  * IP_ADDR_ANY is no longer a NULL pointer. Instead, it is a pointer
+    to a '0.0.0.0' IP address.
+
+  * The packet buffer implementation is changed. The pbuf->ref counter
+    meaning has changed, and several pbuf functions have been
+    adapted accordingly.
+
+  * netif drivers have to be changed to set the hardware address length field
+    that must be initialized correctly by the driver (hint: 6 for Ethernet MAC).
+    See the contrib/ports/c16x cs8900 driver as a driver example.
+
+  * netif's have a dhcp field that must be initialized to NULL by the driver.
+    See the contrib/ports/c16x cs8900 driver as a driver example.
+
+(0.5.x) This file has been unmaintained up to 0.6.1. All changes are
+  logged in CVS but have not been explained here.
+
+(0.5.3) Changes since version 0.5.2
+
+  ++ Bugfixes:
+
+  * memp_malloc(MEMP_API_MSG) could fail with multiple application
+    threads because it wasn't protected by semaphores.
+
+  ++ Other changes:
+
+  * struct ip_addr now packed.
+
+  * The name of the time variable in arp.c has been changed to ctime
+    to avoid conflicts with the time() function.
+
+(0.5.2) Changes since version 0.5.1
+
+  ++ New features:
+
+  * A new TCP function, tcp_tmr(), now handles both TCP timers.
+
+  ++ Bugfixes:
+
+  * A bug in tcp_parseopt() could cause the stack to hang because of a
+    malformed TCP option.
+
+  * The address of new connections in the accept() function in the BSD
+    socket library was not handled correctly.
+
+  * pbuf_dechain() did not update the ->tot_len field of the tail.
+
+  * Aborted TCP connections were not handled correctly in all
+    situations.
+
+  ++ Other changes:
+
+  * All protocol header structs are now packed.
+
+  * The ->len field in the tcp_seg structure now counts the actual
+    amount of data, and does not add one for SYN and FIN segments.
+
+(0.5.1) Changes since version 0.5.0
+
+  ++ New features:
+
+  * Possible to run as a user process under Linux.
+
+  * Preliminary support for cross platform packed structs.
+
+  * ARP timer now implemented.
+
+  ++ Bugfixes:
+
+  * TCP output queue length was badly initialized when opening
+    connections.
+
+  * TCP delayed ACKs were not sent correctly.
+
+  * Explicit initialization of BSS segment variables.
+
+  * read() in BSD socket library could drop data.
+
+  * Problems with memory alignment.
+
+  * Situations when all TCP buffers were used could lead to
+    starvation.
+
+  * TCP MSS option wasn't parsed correctly.
+
+  * Problems with UDP checksum calculation.
+
+  * IP multicast address tests had endianess problems.
+
+  * ARP requests had wrong destination hardware address.
+
+  ++ Other changes:
+
+  * struct eth_addr changed from u16_t[3] array to u8_t[6].
+
+  * A ->linkoutput() member was added to struct netif.
+
+  * TCP and UDP ->dest_* struct members where changed to ->remote_*.
+
+  * ntoh* macros are now null definitions for big endian CPUs.
+
+(0.5.0) Changes since version 0.4.2
+
+  ++ New features:
+
+  * Redesigned operating system emulation layer to make porting easier.
+
+  * Better control over TCP output buffers.
+
+  * Documenation added.
+
+  ++ Bugfixes:
+
+  * Locking issues in buffer management.
+
+  * Bugfixes in the sequential API.
+
+  * IP forwarding could cause memory leakage. This has been fixed.
+
+  ++ Other changes:
+
+  * Directory structure somewhat changed; the core/ tree has been
+    collapsed.
+
+(0.4.2) Changes since version 0.4.1
+
+  ++ New features:
+
+  * Experimental ARP implementation added.
+
+  * Skeleton Ethernet driver added.
+
+  * Experimental BSD socket API library added.
+
+  ++ Bugfixes:
+
+  * In very intense situations, memory leakage could occur. This has
+    been fixed.
+
+  ++ Other changes:
+
+  * Variables named "data" and "code" have been renamed in order to
+    avoid name conflicts in certain compilers.
+
+  * Variable++ have in appliciable cases been translated to ++variable
+    since some compilers generate better code in the latter case.
+
+(0.4.1) Changes since version 0.4
+
+  ++ New features:
+
+  * TCP: Connection attempts time out earlier than data
+    transmissions. Nagle algorithm implemented. Push flag set on the
+    last segment in a burst.
+
+  * UDP: experimental support for UDP-Lite extensions.
+
+  ++ Bugfixes:
+
+  * TCP: out of order segments were in some cases handled incorrectly,
+    and this has now been fixed. Delayed acknowledgements was broken
+    in 0.4, has now been fixed. Binding to an address that is in use
+    now results in an error. Reset connections sometimes hung an
+    application; this has been fixed.
+
+  * Checksum calculation sometimes failed for chained pbufs with odd
+    lengths. This has been fixed.
+
+  * API: a lot of bug fixes in the API. The UDP API has been improved
+    and tested. Error reporting and handling has been
+    improved. Logical flaws and race conditions for incoming TCP
+    connections has been found and removed.
+
+  * Memory manager: alignment issues. Reallocating memory sometimes
+    failed, this has been fixed.
+
+  * Generic library: bcopy was flawed and has been fixed.
+
+  ++ Other changes:
+
+  * API: all datatypes has been changed from generic ones such as
+    ints, to specified ones such as u16_t. Functions that return
+    errors now have the correct type (err_t).
+
+  * General: A lot of code cleaned up and debugging code removed. Many
+    portability issues have been fixed.
+
+  * The license was changed; the advertising clause was removed.
+
+  * C64 port added.
+
+  * Thanks: Huge thanks go to Dagan Galarneau, Horst Garnetzke, Petri
+    Kosunen, Mikael Caleres, and Frits Wilmink for reporting and
+    fixing bugs!
+
+(0.4) Changes since version 0.3.1
+
+  * Memory management has been radically changed; instead of
+    allocating memory from a shared heap, memory for objects that are
+    rapidly allocated and deallocated is now kept in pools. Allocation
+    and deallocation from those memory pools is very fast. The shared
+    heap is still present but is used less frequently.
+
+  * The memory, memory pool, and packet buffer subsystems now support
+    4-, 2-, or 1-byte alignment.
+
+  * "Out of memory" situations are handled in a more robust way.
+
+  * Stack usage has been reduced.
+
+  * Easier configuration of lwIP parameters such as memory usage,
+    TTLs, statistics gathering, etc. All configuration parameters are
+    now kept in a single header file "lwipopts.h".
+
+  * The directory structure has been changed slightly so that all
+    architecture specific files are kept under the src/arch
+    hierarchy.
+
+  * Error propagation has been improved, both in the protocol modules
+    and in the API.
+
+  * The code for the RTXC architecture has been implemented, tested
+    and put to use.
+
+  * Bugs have been found and corrected in the TCP, UDP, IP, API, and
+    the Internet checksum modules.
+
+  * Bugs related to porting between a 32-bit and a 16-bit architecture
+    have been found and corrected.
+
+  * The license has been changed slightly to conform more with the
+    original BSD license, including the advertisement clause.
+
+(0.3.1) Changes since version 0.3
+
+  * Fix of a fatal bug in the buffer management. Pbufs with allocated
+    RAM never returned the RAM when the pbuf was deallocated.
+
+  * TCP congestion control, window updates and retransmissions did not
+    work correctly. This has now been fixed.
+
+  * Bugfixes in the API.
+
+(0.3) Changes since version 0.2
+
+  * New and improved directory structure. All include files are now
+    kept in a dedicated include/ directory.
+
+  * The API now has proper error handling. A new function,
+    netconn_err(), now returns an error code for the connection in
+    case of errors.
+
+  * Improvements in the memory management subsystem. The system now
+    keeps a pointer to the lowest free memory block. A new function,
+    mem_malloc2() tries to allocate memory once, and if it fails tries
+    to free some memory and retry the allocation.
+
+  * Much testing has been done with limited memory
+    configurations. lwIP now does a better job when overloaded.
+
+  * Some bugfixes and improvements to the buffer (pbuf) subsystem.
+
+  * Many bugfixes in the TCP code:
+
+    - Fixed a bug in tcp_close().
+
+    - The TCP receive window was incorrectly closed when out of
+      sequence segments was received. This has been fixed.
+
+    - Connections are now timed-out of the FIN-WAIT-2 state.
+
+    - The initial congestion window could in some cases be too
+      large. This has been fixed.
+
+    - The retransmission queue could in some cases be screwed up. This
+      has been fixed.
+
+    - TCP RST flag now handled correctly.
+
+    - Out of sequence data was in some cases never delivered to the
+      application. This has been fixed.
+
+    - Retransmitted segments now contain the correct acknowledgment
+      number and advertised window.
+
+    - TCP retransmission timeout backoffs are not correctly computed
+      (ala BSD). After a number of retransmissions, TCP now gives up
+      the connection.
+
+  * TCP connections now are kept on three lists, one for active
+    connections, one for listening connections, and one for
+    connections that are in TIME-WAIT. This greatly speeds up the fast
+    timeout processing for sending delayed ACKs.
+
+  * TCP now provides proper feedback to the application when a
+    connection has been successfully set up.
+
+  * More comments have been added to the code. The code has also been
+    somewhat cleaned up.
+
+(0.2) Initial public release.
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/COPYING b/20080212/Demo/lwIP_MCF5235_GCC/lwip/COPYING
new file mode 100644
index 000000000..e23898b5e
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/COPYING
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2001, 2002 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/FILES b/20080212/Demo/lwIP_MCF5235_GCC/lwip/FILES
new file mode 100644
index 000000000..66253196f
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/FILES
@@ -0,0 +1,4 @@
+src/      - The source code for the lwIP TCP/IP stack.
+doc/      - The documentation for lwIP.
+
+See also the FILES file in each subdirectory.
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/README b/20080212/Demo/lwIP_MCF5235_GCC/lwip/README
new file mode 100644
index 000000000..d9102826f
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/README
@@ -0,0 +1,74 @@
+INTRODUCTION
+
+lwIP is a small independent implementation of the TCP/IP protocol
+suite that has been developed by Adam Dunkels at the Computer and
+Networks Architectures (CNA) lab at the Swedish Institute of Computer
+Science (SICS).
+
+The focus of the lwIP TCP/IP implementation is to reduce the RAM usage
+while still having a full scale TCP. This making lwIP suitable for use
+in embedded systems with tens of kilobytes of free RAM and room for
+around 40 kilobytes of code ROM.
+
+FEATURES
+
+ * IP (Internet Protocol) including packet forwarding over multiple
+   network interfaces
+ * ICMP (Internet Control Message Protocol) for network maintenance
+   and debugging
+ * UDP (User Datagram Protocol) including experimental UDP-lite
+   extensions
+ * TCP (Transmission Control Protocol) with congestion control, RTT
+   estimation and fast recovery/fast retransmit
+ * Specialized API for enhanced performance
+ * Optional Berkeley socket API
+
+LICENSE
+
+lwIP is freely available under a BSD license.
+
+DEVELOPMENT
+
+lwIP has grown into an excellent TCP/IP stack for embedded devices,
+and developers using the stack often submit bug fixes, improvements,
+and additions to the stack to further increase its usefulness.
+
+Development of lwIP is hosted on Savannah, a central point for
+software development, maintenance and distribution. Everyone can
+help improve lwIP by use of Savannah's interface, CVS and the
+mailing list. A core team of developers will commit changes to the
+CVS source tree.
+
+The lwIP TCP/IP stack is maintained in the 'lwip' CVS module and
+contributions (such as platform ports) are in the 'contrib' module.
+
+See doc/savannah.txt for details on CVS server access for users and
+developers.
+
+Last night's CVS tar ball can be downloaded from:
+  http://savannah.gnu.org/cvs.backups/lwip.tar.gz [CHANGED - NEEDS FIXING]
+
+The current CVS trees are web-browsable:
+  http://savannah.nongnu.org/cgi-bin/viewcvs/lwip/lwip/
+  http://savannah.nongnu.org/cgi-bin/viewcvs/lwip/contrib/
+
+Submit patches and bugs via the lwIP project page:
+  http://savannah.nongnu.org/projects/lwip/
+
+
+DOCUMENTATION
+
+The original out-dated homepage of lwIP and Adam Dunkels' papers on
+lwIP are at the official lwIP home page:
+  http://www.sics.se/~adam/lwip/
+
+Self documentation of the source code is regularly extracted from the
+current CVS sources and is available from this web page:
+  http://www.nongnu.org/lwip/
+
+Reading Adam's papers, the files in docs/, browsing the source code
+documentation and browsing the mailing list archives is a good way to
+become familiar with the design of lwIP.
+
+Adam Dunkels 
+Leon Woestenberg 		    
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/arch/cc.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/arch/cc.h
new file mode 100644
index 000000000..f1a83ffd6
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/arch/cc.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ * Modifcations: Christian Walter 
+ */
+#ifndef __CC_H__
+#define __CC_H__
+
+/* ------------------------ System includes ------------------------------- */
+#include 
+
+/* ------------------------ Project includes ------------------------------ */
+#include "cpu.h"
+#include "sys_arch.h"
+
+/* ------------------------ Defines --------------------------------------- */
+
+#define PACK_STRUCT_BEGIN
+#define PACK_STRUCT_STRUCT      __attribute__ ((__packed__))
+#define PACK_STRUCT_END
+
+#define PACK_STRUCT_FIELD( x )  x
+
+#define ALIGN_STRUCT_8_BEGIN
+#define ALIGN_STRUCT_8          __attribute__ ((aligned (8)))
+#define ALIGN_STRUCT_8_END
+
+#define LWIP_PLATFORM_ASSERT( x ) sys_assert( x )
+#define LWIP_PLATFORM_DIAG( x, ... ) do{ sys_debug x; } while( 0 );
+
+/* Define (sn)printf formatters for these lwIP types */
+#define U16_F                   "hu"
+#define S16_F                   "hd"
+#define X16_F                   "hx"
+#define U32_F                   "lu"
+#define S32_F                   "ld"
+#define X32_F                   "lx"
+
+/* ------------------------ Type definitions (lwIP) ----------------------- */
+typedef unsigned char u8_t;
+typedef signed char s8_t;
+typedef unsigned short u16_t;
+typedef signed short s16_t;
+typedef unsigned long u32_t;
+typedef signed long s32_t;
+typedef u32_t   mem_ptr_t;
+typedef int     sys_prot_t;
+
+/* ------------------------ Prototypes ------------------------------------ */
+
+#endif
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/arch/cpu.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/arch/cpu.h
new file mode 100644
index 000000000..fcdb1bc1d
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/arch/cpu.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __CPU_H__
+#define __CPU_H__
+
+/* ------------------------ Defines --------------------------------------- */
+#define BYTE_ORDER BIG_ENDIAN
+
+#endif
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/arch/perf.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/arch/perf.h
new file mode 100644
index 000000000..5c58a6512
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/arch/perf.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __PERF_H__
+#define __PERF_H__
+
+/* ------------------------ Defines --------------------------------------- */
+#define PERF_START              /* null definition */
+#define PERF_STOP(x)            /* null definition */
+
+#endif
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/arch/sys_arch.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/arch/sys_arch.h
new file mode 100644
index 000000000..e1ea31da8
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/arch/sys_arch.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __SYS_ARCH_H__
+#define __SYS_ARCH_H__
+
+/* ------------------------ Project includes ------------------------------ */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "semphr.h"
+
+/* ------------------------ Defines --------------------------------------- */
+#define SYS_MBOX_NULL           ( xQueueHandle )0
+#define SYS_THREAD_NULL         NULL
+#define SYS_SEM_NULL            ( xSemaphoreHandle )0
+#define SIO_FD_NULL             ( sio_fd_t )NULL
+
+/* ------------------------ Type definitions ------------------------------ */
+
+
+typedef xSemaphoreHandle sys_sem_t;
+typedef xQueueHandle sys_mbox_t;
+typedef void   *sys_thread_t;
+
+/* ------------------------ Prototypes ------------------------------------ */
+sys_thread_t    sys_arch_thread_new( void ( *thread ) ( void *arg ), void *arg,
+                                     int prio, size_t ssize );
+sys_thread_t    sys_arch_thread_current( void );
+void            sys_arch_thread_remove( sys_thread_t hdl );
+void            sys_assert( const char *const msg );
+void            sys_debug( const char *const fmt, ... );
+
+#endif
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/netif/fec.c b/20080212/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/netif/fec.c
new file mode 100644
index 000000000..a1c7605e3
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/netif/fec.c
@@ -0,0 +1,582 @@
+/*
+ * Copyright (c) 2006 Christian Walter
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Christian Walter 
+ *
+ * TODO:
+ *  - Introduce another task create function in the sys_arch layer which allows
+ *    for passing the stack size.
+ *  - Avoid copying the buffers - this requires changeing the nbuf driver code
+ *    to use the lwIP pbuf buffer implementation.
+ *
+ * File: $Id: fec.c,v 1.3 2006/08/29 18:53:46 wolti Exp $
+ */
+
+/* ------------------------ System includes ------------------------------- */
+#include 
+
+/* ------------------------ Platform includes ----------------------------- */
+#include "mcf5xxx.h"
+#include "mcf523x.h"
+
+#include "nbuf.h"
+
+/* ------------------------ lwIP includes --------------------------------- */
+#include "lwip/opt.h"
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/pbuf.h"
+#include "lwip/sys.h"
+#include "lwip/stats.h"
+#include "lwip/debug.h"
+#include "netif/etharp.h"
+
+/* ------------------------ Defines --------------------------------------- */
+#ifdef FEC_DEBUG
+#define FEC_DEBUG_INIT \
+    do \
+    { \
+        MCF_GPIO_PDDR_FECI2C = ( MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 | \
+                                 MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 ); \
+    } while( 0 )
+
+#define FEC_DEBUG_RX_TIMING( x ) \
+    do \
+    { \
+        if( x ) \
+            MCF_GPIO_PPDSDR_FECI2C = MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0; \
+        else \
+            MCF_GPIO_PCLRR_FECI2C = ~( MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 ); \
+    } while( 0 )
+
+#define FEC_DEBUG_TX_TIMING( x ) \
+    do \
+    { \
+        if( x ) \
+            MCF_GPIO_PPDSDR_FECI2C = MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1; \
+        else \
+            MCF_GPIO_PCLRR_FECI2C = ~( MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 ); \
+    } while( 0 )
+
+#else
+#define FEC_DEBUG               DBG_OFF
+#define FEC_DEBUG_INIT
+#define FEC_DEBUG_RX_TIMING( x )
+#define FEC_DEBUG_TX_TIMING( x )
+#endif
+
+#define MCF_FEC_INT_LEVEL       ( 6 )
+#define MCF_FEC_INT_PRIORITY    ( 0 )
+#define MCF_FEC_VEC_RXF         ( 64 + 27 )
+#define MCF_FEC_MTU             ( 1518 )
+
+#define ETH_ADDR_LEN            ( 6 )
+
+#define TASK_PRIORITY           ( configMAX_PRIORITIES - 1 )
+
+/* ------------------------ Type definitions ------------------------------ */
+typedef struct
+{
+    struct netif   *netif;      /* lwIP network interface. */
+    struct eth_addr *self;      /* MAC address of FEC interface. */
+    sys_sem_t       tx_sem;     /* Control access to transmitter. */
+    sys_sem_t       rx_sem;     /* Semaphore to signal receive thread. */
+} mcf523xfec_if_t;
+
+/* ------------------------ Static variables ------------------------------ */
+static mcf523xfec_if_t *fecif_g;
+
+/* ------------------------ Static functions ------------------------------ */
+static err_t    mcf523xfec_output( struct netif *, struct pbuf *, struct ip_addr * );
+static err_t    mcf523xfec_output_raw( struct netif *, struct pbuf * );
+
+static void     mcf523xfec_reset( mcf523xfec_if_t * fecif );
+static void     mcf523xfec_enable( mcf523xfec_if_t * fecif );
+static void     mcf523xfec_disable( mcf523xfec_if_t * fecif );
+static void     mcf523xfec_get_mac( mcf523xfec_if_t * fecif, struct eth_addr *mac );
+static void     mcf523xfec_rx_irq( void );
+static void     mcf523xfec_rx_task( void *arg );
+
+static void     arp_timer( void *arg );
+static void     eth_input( struct netif *netif, struct pbuf *p );
+
+/* ------------------------ Start implementation -------------------------- */
+
+static void
+arp_timer( void *arg )
+{
+    ( void )arg;
+    etharp_tmr(  );
+    sys_timeout( ARP_TMR_INTERVAL, arp_timer, NULL );
+}
+
+err_t
+mcf523xfec_output_raw( struct netif *netif, struct pbuf *p )
+{
+    err_t           res;
+    nbuf_t         *pNBuf;
+    mcf523xfec_if_t *fecif = netif->state;
+    int             i;
+    struct pbuf    *q;
+
+#if ETH_PAD_SIZE
+    pbuf_header( p, -ETH_PAD_SIZE );    /* drop the padding word */
+#endif
+
+
+    /* Test if we can handle such big frames. If not drop it. */
+    if( p->tot_len > MCF_FEC_MTU )
+    {
+#if LINK_STATS
+        lwip_stats.link.lenerr++;
+#endif
+        res = ERR_BUF;
+    }
+    /* Test if our network buffer scheme can handle a packet of this size. If
+     * not drop it and return a memory error. */
+    else if( p->tot_len > TX_BUFFER_SIZE )
+    {
+#ifdef LINK_STATS
+        lwip_stats.link.memerr++;
+#endif
+        res = ERR_MEM;
+    }
+    /* Allocate a transmit buffer. If no buffer is available drop the frame. */
+    else if( ( pNBuf = nbuf_tx_allocate(  ) ) == NULL )
+    {
+        LWIP_ASSERT( "mcf523xfec_output_raw: pNBuf != NULL\n", pNBuf != NULL );
+#ifdef LINK_STATS
+        lwip_stats.link.memerr++;
+#endif
+        res = ERR_MEM;
+    }
+    else
+    {
+        q = p;
+        i = 0;
+        do
+        {
+            memcpy( &pNBuf->data[i], q->payload, q->len );
+            i += q->len;
+        }
+        while( ( q = q->next ) != NULL );
+        pNBuf->length = p->tot_len;
+
+        /* Set Frame ready for transmission. */
+        pNBuf->status |= TX_BD_R;
+        /* Mark the buffer as not in use so the FEC can take it. */
+        nbuf_tx_release( pNBuf );
+        /* Indicate that a new transmit buffer has been produced. */
+        MCF_FEC_TDAR = 1;
+#if LINK_STATS
+        lwip_stats.link.xmit++;
+#endif
+        res = ERR_OK;
+    }
+
+    sys_sem_signal( fecif->tx_sem );
+#if ETH_PAD_SIZE
+    buf_header( p, ETH_PAD_SIZE );
+#endif
+
+    return res;
+}
+
+/* This function is called by the TCP/IP stack when an IP packet should be
+ * sent. It uses the ethernet ARP module provided by lwIP to resolve the
+ * destination MAC address. The ARP module will later call our low level
+ * output function mcf523xfec_output_raw.
+ */
+err_t
+mcf523xfec_output( struct netif * netif, struct pbuf * p, struct ip_addr * ipaddr )
+{
+    err_t           res;
+    mcf523xfec_if_t *fecif = netif->state;
+
+    FEC_DEBUG_TX_TIMING( 1 );
+    /* Make sure only one thread is in this function. */
+    sys_sem_wait( fecif->tx_sem );
+    res = etharp_output( netif, ipaddr, p );
+    FEC_DEBUG_TX_TIMING( 0 );
+    return res;
+}
+
+void
+mcf523xfec_rx_task( void *arg )
+{
+    mcf523xfec_if_t *fecif = arg;
+    struct pbuf    *p, *q;
+    nbuf_t         *pNBuf;
+    uint8          *pPayLoad;
+
+    do
+    {
+        sys_sem_wait( fecif->rx_sem );
+        while( nbuf_rx_next_ready(  ) )
+        {
+            pNBuf = nbuf_rx_allocate(  );
+            if( pNBuf != NULL )
+            {
+                LWIP_ASSERT( "mcf523xfec_rx_task: pNBuf->status & RX_BD_L ",
+                             pNBuf->status & RX_BD_L );
+
+                /* This flags indicate that the frame has been damaged. In
+                 * this case we must update the link stats if enabled and
+                 * remove the frame from the FEC. */
+                if ( pNBuf->status & ( RX_BD_LG | RX_BD_NO |
+                                       RX_BD_CR | RX_BD_OV ) )
+                {
+#ifdef LINK_STATS
+                    lwip_stats.link.drop++;
+                    if ( pNBuf->status & RX_BD_LG)
+                    {
+                        lwip_stats.link.lenerr++;
+                    }
+                    else if ( pNBuf->status & ( RX_BD_NO | RX_BD_OV ) )
+                    {
+                        lwip_stats.link.err++;
+                    }
+                    else
+                    {
+                        lwip_stats.link.chkerr++;
+                    }
+#endif
+                }
+                else
+                {
+                    /* The frame must no be valid. Perform some checks to see if the FEC
+                     * driver is working correctly.
+                     */
+                    LWIP_ASSERT( "mcf523xfec_rx_task: pNBuf->length != 0", pNBuf->length != 0 );
+                    p = pbuf_alloc( PBUF_RAW, pNBuf->length, PBUF_POOL );
+                    if( p != NULL )
+                    {
+#if ETH_PAD_SIZE
+                        pbuf_header( p, -ETH_PAD_SIZE );
+#endif
+                        pPayLoad = pNBuf->data;
+                        for( q = p; q != NULL; q = q->next )
+                        {
+                            memcpy( q->payload, pPayLoad, q->len );
+                            pPayLoad += q->len;
+                        }
+#if ETH_PAD_SIZE
+                        pbuf_header( p, ETH_PAD_SIZE );
+#endif
+
+                        /* Ethernet frame received. Handling it is not device
+                         * dependent and therefore done in another function.
+                         */
+                        eth_input( fecif->netif, p );
+                    }
+                }
+                nbuf_rx_release( pNBuf );
+
+                /* Tell the HW that there are new free RX buffers. */
+                MCF_FEC_RDAR = 1;
+            }
+            else
+            {
+#if LINK_STATS
+                lwip_stats.link.memerr++;
+                lwip_stats.link.drop++;
+#endif
+            }
+        }
+        /* Set RX Debug PIN to low since handling of next frame is possible. */
+        FEC_DEBUG_RX_TIMING( 0 );
+    }
+    while( 1 );
+}
+
+void
+eth_input( struct netif *netif, struct pbuf *p )
+{
+    struct eth_hdr *eth_hdr = p->payload;
+
+    LWIP_ASSERT( "eth_input: p != NULL ", p != NULL );
+
+    switch ( htons( eth_hdr->type ) )
+    {
+    case ETHTYPE_IP:
+        /* Pass to ARP layer. */
+        etharp_ip_input( netif, p );
+
+        /* Skip Ethernet header. */
+        pbuf_header( p, ( s16_t ) - sizeof( struct eth_hdr ) );
+
+        /* Pass to network layer. */
+        netif->input( p, netif );
+        break;
+
+    case ETHTYPE_ARP:
+        /* Pass to ARP layer. */
+        etharp_arp_input( netif, ( struct eth_addr * )netif->hwaddr, p );
+        break;
+
+    default:
+        pbuf_free( p );
+        break;
+    }
+}
+
+void
+mcf523xfec_rx_irq( void )
+{
+    static portBASE_TYPE xNeedSwitch = pdFALSE;
+
+    /* Workaround GCC if frame pointers are enabled. This is an ISR and
+     * we must not modify the stack before portENTER_SWITCHING_ISR( )
+     * has been called. */
+#if _GCC_USES_FP == 1
+    asm volatile    ( "unlk %fp\n\t" );
+#endif
+
+    /* This ISR can cause a context switch, so the first statement must be
+     * a call to the portENTER_SWITCHING_ISR() macro.
+     */
+    portENTER_SWITCHING_ISR(  );
+
+    /* Set Debug PIN to high to measure RX latency. */
+    FEC_DEBUG_RX_TIMING( 1 );
+
+    /* Clear FEC RX Event from the Event Register (by writing 1) */
+    if( MCF_FEC_EIR & ( MCF_FEC_EIR_RXB | MCF_FEC_EIR_RXF ) )
+    {
+        /* Clear interrupt from EIR register immediately */
+        MCF_FEC_EIR = ( MCF_FEC_EIR_RXB | MCF_FEC_EIR_RXF );
+        xNeedSwitch = xSemaphoreGiveFromISR( fecif_g->rx_sem, pdFALSE );
+    }
+    portEXIT_SWITCHING_ISR( xNeedSwitch );
+}
+
+void
+mcf523xfec_reset( mcf523xfec_if_t * fecif )
+{
+    extern void     ( *__RAMVEC[] ) (  );
+
+    int             old_ipl = asm_set_ipl( 7 );
+
+    /* Reset the FEC - equivalent to a hard reset */
+    MCF_FEC_ECR = MCF_FEC_ECR_RESET;
+
+    /* Wait for the reset sequence to complete */
+    while( MCF_FEC_ECR & MCF_FEC_ECR_RESET );
+
+    /* Disable all FEC interrupts by clearing the EIMR register */
+    MCF_FEC_EIMR = 0;
+
+    /* Clear any interrupts by setting all bits in the EIR register */
+    MCF_FEC_EIR = 0xFFFFFFFFUL;
+
+    /* Configure Interrupt vectors. */
+    __RAMVEC[MCF_FEC_VEC_RXF] = mcf523xfec_rx_irq;
+
+    /* Set the source address for the controller */
+    MCF_FEC_PALR =
+        ( fecif->self->addr[0] << 24U ) | ( fecif->self->addr[1] << 16U ) |
+        ( fecif->self->addr[2] << 8U ) | ( fecif->self->addr[3] << 0U );
+    MCF_FEC_PAUR = ( fecif->self->addr[4] << 24U ) | ( fecif->self->addr[5] << 16U );
+
+    /* Initialize the hash table registers */
+    MCF_FEC_IAUR = 0;
+    MCF_FEC_IALR = 0;
+
+    /* Set Receive Buffer Size */
+#if RX_BUFFER_SIZE != 2048
+#error "RX_BUFFER_SIZE must be set to 2048 for safe FEC operation."
+#endif
+    MCF_FEC_EMRBR = RX_BUFFER_SIZE - 1;
+
+    /* Point to the start of the circular Rx buffer descriptor queue */
+    MCF_FEC_ERDSR = nbuf_get_start( NBUF_RX );
+
+    /* Point to the start of the circular Tx buffer descriptor queue */
+    MCF_FEC_ETDSR = nbuf_get_start( NBUF_TX );
+
+    /* Set the tranceiver interface to MII mode */
+    MCF_FEC_RCR = MCF_FEC_RCR_MAX_FL( MCF_FEC_MTU ) | MCF_FEC_RCR_MII_MODE;
+
+    /* Set MII Speed Control Register for 2.5Mhz */
+    MCF_FEC_MSCR = MCF_FEC_MSCR_MII_SPEED( FSYS_2 / ( 2UL * 2500000UL ) );
+
+    /* Only operate in half-duplex, no heart beat control */
+    MCF_FEC_TCR = 0;
+
+    /* Enable Debug support */
+    FEC_DEBUG_INIT;
+    FEC_DEBUG_RX_TIMING( 0 );
+    FEC_DEBUG_TX_TIMING( 0 );
+    ( void )asm_set_ipl( old_ipl );
+}
+
+void
+mcf523xfec_get_mac( mcf523xfec_if_t * hw, struct eth_addr *mac )
+{
+    int             i;
+    static const struct eth_addr mac_default = {
+        {0x00, 0xCF, 0x52, 0x35, 0x00, 0x01}
+    };
+
+    ( void )hw;
+
+    for( i = 0; i < ETH_ADDR_LEN; i++ )
+    {
+        mac->addr[i] = mac_default.addr[i];
+    }
+}
+
+void
+mcf523xfec_enable( mcf523xfec_if_t * fecif )
+{
+    ( void )fecif;
+
+    int             old_ipl = asm_set_ipl( 7 );
+
+    /* Configure I/O pins for the FEC. */
+    MCF_GPIO_PAR_FECI2C = ( MCF_GPIO_PAR_FECI2C_PAR_EMDC_FEC | MCF_GPIO_PAR_FECI2C_PAR_EMDIO_FEC );
+
+    /* Allow interrupts by setting IMR register */
+    MCF_FEC_EIMR = MCF_FEC_EIMR_RXF;
+
+    /* Configure the interrupt controller. */
+    MCF_INTC0_ICR27 = ( MCF_INTC0_ICRn_IL( MCF_FEC_INT_LEVEL ) |
+                        MCF_INTC0_ICRn_IP( MCF_FEC_INT_PRIORITY ) );
+    MCF_INTC0_IMRL &= ~( MCF_INTC0_IMRL_INT_MASK27 | MCF_INTC0_IMRL_MASKALL );
+
+    /* Enable FEC */
+    MCF_FEC_ECR = MCF_FEC_ECR_ETHER_EN;
+
+    /* Indicate that there have been empty receive buffers produced */
+    MCF_FEC_RDAR = 1;
+    ( void )asm_set_ipl( old_ipl );
+}
+
+void
+mcf523xfec_disable( mcf523xfec_if_t * fecif )
+{
+    ( void )fecif;
+
+    int             old_ipl = asm_set_ipl( 7 );
+
+    /* Set the Graceful Transmit Stop bit */
+    MCF_FEC_TCR = ( MCF_FEC_TCR | MCF_FEC_TCR_GTS );
+
+    /* Wait for the current transmission to complete */
+    while( !( MCF_FEC_EIR & MCF_FEC_EIR_GRA ) );
+
+    /* Clear the GRA event */
+    MCF_FEC_EIR = MCF_FEC_EIR_GRA;
+
+    /* Disable the FEC */
+    MCF_FEC_ECR = 0;
+
+    /* Disable all FEC interrupts by clearing the IMR register */
+    MCF_FEC_EIMR = 0;
+
+    /* Unconfigure the interrupt controller. */
+    MCF_INTC0_ICR27 = MCF_INTC0_ICRn_IL( 0 ) | MCF_INTC0_ICRn_IP( 0 );
+    MCF_INTC0_IMRL |= MCF_INTC0_IMRL_INT_MASK27;
+
+    /* Clear the GTS bit so frames can be tranmitted when restarted */
+    MCF_FEC_TCR = ( MCF_FEC_TCR & ~MCF_FEC_TCR_GTS );
+
+    /* Disable I/O pins used by the FEC. */
+    MCF_GPIO_PAR_FECI2C &= ~( MCF_GPIO_PAR_FECI2C_PAR_EMDC_FEC |
+                              MCF_GPIO_PAR_FECI2C_PAR_EMDIO_FEC );
+    ( void )asm_set_ipl( old_ipl );
+}
+
+err_t
+mcf523xfec_init( struct netif *netif )
+{
+    err_t           res;
+
+    mcf523xfec_if_t *fecif = mem_malloc( sizeof( mcf523xfec_if_t ) );
+
+    if( fecif != NULL )
+    {
+        /* Global copy used in ISR. */
+        fecif_g = fecif;
+        fecif->self = ( struct eth_addr * )&netif->hwaddr[0];
+        fecif->netif = netif;
+        fecif->tx_sem = NULL;
+        fecif->rx_sem = NULL;
+
+        if( ( fecif->tx_sem = sys_sem_new( 1 ) ) == NULL )
+        {
+            res = ERR_MEM;
+        }
+        else if( ( fecif->rx_sem = sys_sem_new( 0 ) ) == NULL )
+        {
+            res = ERR_MEM;
+        }
+        else if( sys_thread_new( mcf523xfec_rx_task, fecif, TASK_PRIORITY ) == NULL )
+        {
+            res = ERR_MEM;
+        }
+        else
+        {
+            netif->state = fecif;
+            netif->name[0] = 'C';
+            netif->name[1] = 'F';
+            netif->hwaddr_len = ETH_ADDR_LEN;
+            netif->mtu = MCF_FEC_MTU;
+            netif->flags = NETIF_FLAG_BROADCAST;
+            netif->output = mcf523xfec_output;
+            netif->linkoutput = mcf523xfec_output_raw;
+
+            nbuf_init(  );
+            mcf523xfec_get_mac( fecif, fecif->self );
+            mcf523xfec_reset( fecif );
+            mcf523xfec_enable( fecif );
+
+            etharp_init(  );
+            sys_timeout( ARP_TMR_INTERVAL, arp_timer, NULL );
+
+            res = ERR_OK;
+        }
+
+        if( res != ERR_OK )
+        {
+            free( fecif );
+            if( fecif->tx_sem != NULL )
+            {
+                mem_free( fecif->tx_sem );
+            }
+            if( fecif->rx_sem != NULL )
+            {
+                mem_free( fecif->rx_sem );
+            }
+        }
+    }
+    else
+    {
+        res = ERR_MEM;
+    }
+
+    return res;
+}
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/netif/fec.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/netif/fec.h
new file mode 100644
index 000000000..d2f717c80
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/netif/fec.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2006 Christian Walter
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Christian Walter 
+ *
+ * File: $Id: fec.h,v 1.1 2006/08/29 00:04:06 wolti Exp $
+ */
+
+#ifndef _FEC_H
+#define _FEC_H
+
+/* ------------------------ Defines --------------------------------------- */
+
+/* ------------------------ Prototypes ------------------------------------ */
+err_t           mcf523xfec_init( struct netif *netif );
+
+#endif
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/netif/nbuf.c b/20080212/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/netif/nbuf.c
new file mode 100644
index 000000000..5c97159ee
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/netif/nbuf.c
@@ -0,0 +1,186 @@
+/*
+ * Network buffer code based on the MCF523x examples from Freescale.
+ *
+ * File: $Id: nbuf.c,v 1.2 2006/08/31 22:28:21 wolti Exp $
+ */
+
+/* ------------------------ Platform includes ----------------------------- */
+#include "mcf5xxx.h"
+#include "mcf523x.h"
+
+#include "nbuf.h"
+
+/* ------------------------ Static variables ------------------------------ */
+
+/* Buffer descriptor indexes */
+static uint8    tx_bd_idx;
+static uint8    rx_bd_idx;
+
+/* Buffer Descriptors -- must be aligned on a 4-byte boundary but a
+ * 16-byte boundary is recommended. */
+static nbuf_t   tx_nbuf[sizeof( nbuf_t ) * NUM_TXBDS] ATTR_FECMEM;
+static nbuf_t   rx_nbuf[sizeof( nbuf_t ) * NUM_RXBDS] ATTR_FECMEM;
+
+/* Data Buffers -- must be aligned on a 16-byte boundary. */
+static uint8    tx_buf[TX_BUFFER_SIZE * NUM_TXBDS] ATTR_FECMEM;
+static uint8    rx_buf[RX_BUFFER_SIZE * NUM_RXBDS] ATTR_FECMEM;
+
+/* ------------------------ Start implementation -------------------------- */
+void
+nbuf_init(  )
+{
+
+    uint8           i;
+
+    /* Initialize receive descriptor ring */
+    for( i = 0; i < NUM_RXBDS; i++ )
+    {
+        rx_nbuf[i].status = RX_BD_E;
+        rx_nbuf[i].length = 0;
+        rx_nbuf[i].data = &rx_buf[i * RX_BUFFER_SIZE];
+    }
+
+    /* Set the Wrap bit on the last one in the ring */
+    rx_nbuf[NUM_RXBDS - 1].status |= RX_BD_W;
+
+    /* Initialize transmit descriptor ring */
+    for( i = 0; i < NUM_TXBDS; i++ )
+    {
+        tx_nbuf[i].status = TX_BD_L | TX_BD_TC;
+        tx_nbuf[i].length = 0;
+        tx_nbuf[i].data = &tx_buf[i * TX_BUFFER_SIZE];
+    }
+
+    /* Set the Wrap bit on the last one in the ring */
+    tx_nbuf[NUM_TXBDS - 1].status |= TX_BD_W;
+
+    /* Initialize the buffer descriptor indexes */
+    tx_bd_idx = rx_bd_idx = 0;
+
+    return;
+}
+
+
+/********************************************************************/
+uint32
+nbuf_get_start( uint8 direction )
+{
+    /*
+     * Return the address of the first buffer descriptor in the ring.
+     * This routine is needed by the FEC of the MPC860T , MCF5282, and MCF523x
+     * in order to write the Rx/Tx descriptor ring start registers
+     */
+    switch ( direction )
+    {
+    case NBUF_RX:
+        return ( uint32 ) rx_nbuf;
+    case NBUF_TX:
+    default:
+        return ( uint32 ) tx_nbuf;
+    }
+}
+
+
+/********************************************************************/
+nbuf_t         *
+nbuf_rx_allocate(  )
+{
+    /* This routine alters shared data. Disable interrupts! */
+    int             old_ipl = asm_set_ipl( 6 );
+
+    /* Return a pointer to the next empty Rx Buffer Descriptor */
+    int             i = rx_bd_idx;
+
+
+    /* Check to see if the ring of BDs is full */
+    if( rx_nbuf[i].status & RX_BD_INUSE )
+        return NULL;
+
+    /* Mark the buffer as in use */
+    rx_nbuf[i].status |= RX_BD_INUSE;
+
+    /* increment the circular index */
+    rx_bd_idx = ( uint8 ) ( ( rx_bd_idx + 1 ) % NUM_RXBDS );
+
+    /* Restore previous IPL */
+    asm_set_ipl( old_ipl );
+
+    return &rx_nbuf[i];
+}
+
+
+/********************************************************************/
+nbuf_t         *
+nbuf_tx_allocate(  )
+{
+    /* This routine alters shared data. Disable interrupts! */
+    int             old_ipl = asm_set_ipl( 6 );
+
+    /* Return a pointer to the next empty Tx Buffer Descriptor */
+    int             i = tx_bd_idx;
+
+    /* Check to see if ring of BDs is full */
+    if( ( tx_nbuf[i].status & TX_BD_INUSE ) || ( tx_nbuf[i].status & TX_BD_R ) )
+        return NULL;
+
+    /* Mark the buffer as Ready (in use) */
+    /* FEC must set R bit in transmit routine */
+    tx_nbuf[i].status |= TX_BD_INUSE;
+
+    /* increment the circular index */
+    tx_bd_idx = ( uint8 ) ( ( tx_bd_idx + 1 ) % NUM_TXBDS );
+
+    /* Restore previous IPL */
+    asm_set_ipl( old_ipl );
+
+    return &tx_nbuf[i];
+}
+
+
+/********************************************************************/
+void
+nbuf_rx_release( nbuf_t * pNbuf )
+{
+    /* This routine alters shared data. Disable interrupts! */
+    int             old_ipl = asm_set_ipl( 6 );
+
+    /* Mark the buffer as empty and not in use */
+    pNbuf->status |= RX_BD_E;
+    pNbuf->status &= ~RX_BD_INUSE;
+
+    /* Restore previous IPL */
+    asm_set_ipl( old_ipl );
+}
+
+/********************************************************************/
+void
+nbuf_tx_release( nbuf_t * pNbuf )
+{
+    /* This routine alters shared data. Disable interrupts! */
+    int             old_ipl = asm_set_ipl( 6 );
+
+    /* Mark the buffer as not in use */
+    pNbuf->status &= ~TX_BD_INUSE;
+
+    /* Restore previous IPL */
+    asm_set_ipl( old_ipl );
+}
+
+/********************************************************************/
+int
+nbuf_rx_next_ready(  )
+{
+    /****************************************************************
+ This function checks the EMPTY bit of the next Rx buffer to be
+ allocated. If the EMPTY bit is cleared, then the next buffer in
+ the ring has been filled by the FEC and has not already been
+ allocated and passed up the stack. In this case, the next buffer
+ in the ring is ready to be allocated. Otherwise, the  buffer is
+ either empty or not empty but still in use by a higher level
+ protocol. The FEC receive routine uses this function to determine
+ if multiple buffers where filled by the FEC during a single
+ interrupt event.
+ ****************************************************************/
+
+    return ( !( rx_nbuf[rx_bd_idx].status & RX_BD_E ) );
+}
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/netif/nbuf.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/netif/nbuf.h
new file mode 100644
index 000000000..cbd074951
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/netif/nbuf.h
@@ -0,0 +1,95 @@
+/*
+ * Network buffer code based on the MCF523x examples from Freescale.
+ *
+ * Freescale explicitly grants the redistribution and modification
+ * of these source files. The complete licensing information is
+ * available in the file LICENSE_FREESCALE.TXT.
+ *
+ * Modifications Copyright (c) 2006 Christian Walter 
+ *
+ * File: $Id: nbuf.h,v 1.3 2006/09/24 22:50:23 wolti Exp $
+ */
+
+#ifndef _NBUF_H
+#define _NBUF_H
+
+/* ------------------------ Defines --------------------------------------- */
+
+#ifdef __GNUC__
+#define ATTR_FECMEM             \
+    __attribute__((section(".nbuf"),aligned(16)))
+#endif
+
+#define NBUF_RX                 ( 1 )
+#define NBUF_TX                 ( 0 )
+
+/* We set the receiver buffers to the maximum size the FEC supports ( See
+ * MCF5235 reference manual 19.2.5.1.2 - Driver/DMA Operation with Receive
+ * BDs). This gives us the benefit that any frame fits into one buffer. A
+ * maximum size of 2047 is guaranteed by the FEC and 2048 is therefore a
+ * safe value.
+ * Note: The value MUST be dividable by 16!
+ */
+#define RX_BUFFER_SIZE          ( 2048 )
+
+/* Size of the transmit buffers. If you set this value to small all frames
+ * greater than this size will be dropped. The value 1520 was choosen because
+ * it is bigger than the FEC MTU (1518) and is dividable by 16.
+ * Note: The value MUST be dividable by 16! */
+#define TX_BUFFER_SIZE          ( 1520 )
+
+/* Number of Receive and Transmit Buffers and Buffer Descriptors */
+#define NUM_RXBDS               ( 2 )
+#define NUM_TXBDS               ( 2 )
+
+/* ------------------------ Defines ( Buffer Descriptor Flags )------------ */
+
+#define TX_BD_R                 ( 0x8000 )
+#define TX_BD_INUSE             ( 0x4000 )
+#define TX_BD_TO1               ( 0x4000 )
+#define TX_BD_W                 ( 0x2000 )
+#define TX_BD_TO2               ( 0x1000 )
+#define TX_BD_L                 ( 0x0800 )
+#define TX_BD_TC                ( 0x0400 )
+#define TX_BD_DEF               ( 0x0200 )
+#define TX_BD_HB                ( 0x0100 )
+#define TX_BD_LC                ( 0x0080 )
+#define TX_BD_RL                ( 0x0040 )
+#define TX_BD_UN                ( 0x0002 )
+#define TX_BD_CSL               ( 0x0001 )
+
+#define RX_BD_E                 ( 0x8000 )
+#define RX_BD_INUSE             ( 0x4000 )
+#define RX_BD_R01               ( 0x4000 )
+#define RX_BD_W                 ( 0x2000 )
+#define RX_BD_R02               ( 0x1000 )
+#define RX_BD_L                 ( 0x0800 )
+#define RX_BD_M                 ( 0x0100 )
+#define RX_BD_BC                ( 0x0080 )
+#define RX_BD_MC                ( 0x0040 )
+#define RX_BD_LG                ( 0x0020 )
+#define RX_BD_NO                ( 0x0010 )
+#define RX_BD_SH                ( 0x0008 )
+#define RX_BD_CR                ( 0x0004 )
+#define RX_BD_OV                ( 0x0002 )
+#define RX_BD_TR                ( 0x0001 )
+
+/* ------------------------ Type definitions ------------------------------ */
+typedef struct
+{
+    uint16          status;     /* control and status */
+    uint16          length;     /* transfer length */
+    uint8          *data;       /* buffer address */
+} nbuf_t;
+
+/* ------------------------ Prototypes ------------------------------------ */
+
+void            nbuf_init( void );
+uint32          nbuf_get_start( uint8 );
+nbuf_t         *nbuf_rx_allocate( void );
+nbuf_t         *nbuf_tx_allocate( void );
+void            nbuf_rx_release( nbuf_t * );
+void            nbuf_tx_release( nbuf_t * );
+int             nbuf_rx_next_ready( void );
+
+#endif
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/sys_arch.c b/20080212/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/sys_arch.c
new file mode 100644
index 000000000..218e91db0
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/sys_arch.c
@@ -0,0 +1,561 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * Modifications Copyright (c) 2006 Christian Walter 
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ * Modifcations: Christian Walter 
+ *
+ * $Id: sys_arch.c,v 1.6 2006/09/24 22:04:53 wolti Exp $
+ */
+
+/* ------------------------ System includes ------------------------------- */
+#include 
+#include 
+#include 
+#include 
+
+/* ------------------------ FreeRTOS includes ----------------------------- */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "semphr.h"
+
+/* ------------------------ lwIP includes --------------------------------- */
+#include "lwip/debug.h"
+#include "lwip/def.h"
+#include "lwip/sys.h"
+#include "lwip/mem.h"
+#include "lwip/sio.h"
+#include "lwip/stats.h"
+
+/* ------------------------ Project includes ------------------------------ */
+
+/* ------------------------ Defines --------------------------------------- */
+/* This is the number of threads that can be started with sys_thead_new() */
+#define SYS_MBOX_SIZE               ( 16 )
+#define MS_TO_TICKS( ms )           \
+    ( portTickType )( ( portTickType ) ( ms ) / portTICK_RATE_MS )
+#define TICKS_TO_MS( ticks )        \
+    ( unsigned portLONG )( ( portTickType ) ( ticks ) * portTICK_RATE_MS )
+#define THREAD_STACK_SIZE           ( 1024 )
+#define THREAD_NAME                 "lwIP"
+
+#define THREAD_INIT( tcb ) \
+    do { \
+        tcb->next = NULL; \
+        tcb->pid = ( xTaskHandle )0; \
+        tcb->timeouts.next = NULL; \
+    } while( 0 )
+
+/* ------------------------ Type definitions ------------------------------ */
+typedef struct sys_tcb
+{
+    struct sys_tcb *next;
+    struct sys_timeouts timeouts;
+    xTaskHandle     pid;
+} sys_tcb_t;
+
+/* ------------------------ Prototypes ------------------------------------ */
+
+/* ------------------------ Static functions ------------------------------ */
+sys_tcb_t      *sys_thread_current( void );
+
+/* ------------------------ Static variables ------------------------------ */
+static sys_tcb_t *tasks = NULL;
+
+/* ------------------------ Start implementation -------------------------- */
+void
+sys_init( void )
+{
+    LWIP_ASSERT( "sys_init: not called first", tasks == NULL );
+    tasks = NULL;
+}
+
+/*
+ * This optional function does a "fast" critical region protection and returns
+ * the previous protection level. This function is only called during very short
+ * critical regions. An embedded system which supports ISR-based drivers might
+ * want to implement this function by disabling interrupts. Task-based systems
+ * might want to implement this by using a mutex or disabling tasking. This
+ * function should support recursive calls from the same task or interrupt. In
+ * other words, sys_arch_protect() could be called while already protected. In
+ * that case the return value indicates that it is already protected.
+ *
+ * sys_arch_protect() is only required if your port is supporting an operating
+ * system.
+ */
+sys_prot_t
+sys_arch_protect( void )
+{
+    vPortEnterCritical(  );
+    return 1;
+}
+
+/*
+ * This optional function does a "fast" set of critical region protection to the
+ * value specified by pval. See the documentation for sys_arch_protect() for
+ * more information. This function is only required if your port is supporting
+ * an operating system.
+ */
+void
+sys_arch_unprotect( sys_prot_t pval )
+{
+    ( void )pval;
+    vPortExitCritical(  );
+}
+
+/*
+ * Prints an assertion messages and aborts execution.
+ */
+void
+sys_assert( const char *msg )
+{
+	fputs( msg, stderr );
+	fputs( "\n\r", stderr );
+    vPortEnterCritical(  );
+    for( ;; );
+}
+
+void
+sys_debug( const char *const fmt, ... )
+{
+    va_list         ap;
+
+    va_start( ap, fmt );
+    ( void )vprintf( fmt, ap );
+    ( void )putchar( '\r' );
+    va_end( ap );
+}
+
+/* ------------------------ Start implementation ( Threads ) -------------- */
+
+sys_thread_t
+sys_thread_new( void ( *thread ) ( void *arg ), void *arg, int prio )
+{
+    return sys_arch_thread_new( thread, arg, prio, THREAD_STACK_SIZE );
+}
+
+/*
+ * Starts a new thread with priority "prio" that will begin its execution in the
+ * function "thread()". The "arg" argument will be passed as an argument to the
+ * thread() function. The argument "ssize" is the requested stack size for the
+ * new thread. The id of the new thread is returned. Both the id and the
+  * priority are system dependent.
+ */
+sys_thread_t
+sys_arch_thread_new( void ( *thread ) ( void *arg ), void *arg, int prio, size_t ssize )
+{
+    sys_thread_t    thread_hdl = SYS_THREAD_NULL;
+    int             i;
+    sys_tcb_t      *p;
+    char            thread_name[ configMAX_TASK_NAME_LEN ];
+
+    /* We disable the FreeRTOS scheduler because it might be the case that the new
+     * tasks gets scheduled inside the xTaskCreate function. To prevent this we
+     * disable the scheduling. Note that this can happen although we have interrupts
+     * disabled because xTaskCreate contains a call to taskYIELD( ).
+     */
+    vPortEnterCritical(  );
+
+    p = tasks;
+    i = 0;
+    /* We are called the first time. Initialize it. */
+    if( p == NULL )
+    {
+        p = pvPortMalloc( sizeof( sys_tcb_t ) );
+        if( p != NULL )
+        {
+            tasks = p;
+        }
+    }
+    else
+    {
+        /* First task already counter. */
+        i++;
+        /* Cycle to the end of the list. */
+        while( p->next != NULL )
+        {
+            i++;
+            p = p->next;
+        }
+        p->next = pvPortMalloc( sizeof( sys_tcb_t ) );
+        p = p->next;
+    }
+
+    if( p != NULL )
+    {
+        /* Memory allocated. Initialize the data structure. */
+        THREAD_INIT( p );
+        ( void )snprintf( thread_name, configMAX_TASK_NAME_LEN, "lwIP%d", i );
+
+        /* Now q points to a free element in the list. */
+        if( xTaskCreate( thread, thread_name, ssize, arg, prio, &p->pid ) == pdPASS )
+        {
+            thread_hdl = p;
+        }
+        else
+        {
+            vPortFree( p );
+        }
+    }
+
+    vPortExitCritical(  );
+    return thread_hdl;
+}
+
+void
+sys_arch_thread_remove( sys_thread_t hdl )
+{
+    sys_tcb_t      *current = tasks, *prev;
+    sys_tcb_t      *toremove = hdl;
+    xTaskHandle     pid = ( xTaskHandle ) 0;
+
+    LWIP_ASSERT( "sys_arch_thread_remove: assertion hdl != NULL failed!", hdl != NULL );
+
+    /* If we have to remove the first task we must update the global "tasks"
+     * variable. */
+    vPortEnterCritical(  );
+    if( hdl != NULL )
+    {
+        prev = NULL;
+        while( ( current != NULL ) && ( current != toremove ) )
+        {
+            prev = current;
+            current = current->next;
+        }
+        /* Found it. */
+        if( current == toremove )
+        {
+            /* Not the first entry in the list. */
+            if( prev != NULL )
+            {
+                prev->next = toremove->next;
+            }
+            else
+            {
+                tasks = toremove->next;
+            }
+            LWIP_ASSERT( "sys_arch_thread_remove: can't remove thread with timeouts!",
+                         toremove->timeouts.next == NULL );
+            pid = toremove->pid;
+            THREAD_INIT( toremove );
+            vPortFree( toremove );
+        }
+    }
+    /* We are done with accessing the shared datastructure. Release the 
+     * resources.
+     */
+    vPortExitCritical(  );
+    if( pid != ( xTaskHandle ) 0 )
+    {
+        vTaskDelete( pid );
+        /* not reached. */
+    }
+}
+
+/*
+ * Returns the thread control block for the currently active task. In case
+ * of an error the functions returns NULL.
+ */
+sys_thread_t
+sys_arch_thread_current( void )
+{
+    sys_tcb_t      *p = tasks;
+    xTaskHandle     pid = xTaskGetCurrentTaskHandle(  );
+
+    vPortEnterCritical(  );
+    while( ( p != NULL ) && ( p->pid != pid ) )
+    {
+        p = p->next;
+    }
+    vPortExitCritical(  );
+    return p;
+}
+
+/*
+ * Returns a pointer to the per-thread sys_timeouts structure. In lwIP,
+ * each thread has a list of timeouts which is represented as a linked
+ * list of sys_timeout structures. The sys_timeouts structure holds a
+ * pointer to a linked list of timeouts. This function is called by
+ * the lwIP timeout scheduler and must not return a NULL value.
+ *
+ * In a single threaded sys_arch implementation, this function will
+ * simply return a pointer to a global sys_timeouts variable stored in
+ * the sys_arch module.
+ */
+struct sys_timeouts *
+sys_arch_timeouts( void )
+{
+    sys_tcb_t      *ptask;
+
+    ptask = sys_arch_thread_current(  );
+    LWIP_ASSERT( "sys_arch_timeouts: ptask != NULL", ptask != NULL );
+    return ptask != NULL ? &( ptask->timeouts ) : NULL;
+}
+
+/* ------------------------ Start implementation ( Semaphores ) ----------- */
+
+/* Creates and returns a new semaphore. The "count" argument specifies
+ * the initial state of the semaphore.
+ */
+sys_sem_t
+sys_sem_new( u8_t count )
+{
+    xSemaphoreHandle xSemaphore;
+
+    vSemaphoreCreateBinary( xSemaphore );
+    if( xSemaphore != SYS_SEM_NULL )
+    {
+        if( count == 0 )
+        {
+            xSemaphoreTake( xSemaphore, 1 );
+        }
+#ifdef SYS_STATS
+        vPortEnterCritical(  );
+        lwip_stats.sys.sem.used++;
+        if( lwip_stats.sys.sem.used > lwip_stats.sys.sem.max )
+        {
+            lwip_stats.sys.sem.max = lwip_stats.sys.sem.used;
+        }
+        vPortExitCritical(  );
+#endif
+    }
+    else
+    {
+        LWIP_ASSERT( "sys_sem_new: xSemaphore == SYS_SEM_NULL", xSemaphore != SYS_SEM_NULL );
+    }
+
+    return xSemaphore;
+}
+
+/* Deallocates a semaphore */
+void
+sys_sem_free( sys_sem_t sem )
+{
+    LWIP_ASSERT( "sys_sem_free: sem != SYS_SEM_NULL", sem != SYS_SEM_NULL );
+    if( sem != SYS_SEM_NULL )
+    {
+#ifdef SYS_STATS
+        vPortEnterCritical(  );
+        lwip_stats.sys.sem.used--;
+        vPortExitCritical(  );
+#endif
+        vQueueDelete( sem );
+    }
+}
+
+/* Signals a semaphore */
+void
+sys_sem_signal( sys_sem_t sem )
+{
+    LWIP_ASSERT( "sys_sem_signal: sem != SYS_SEM_NULL", sem != SYS_SEM_NULL );
+    xSemaphoreGive( sem );
+}
+
+/*
+ * Blocks the thread while waiting for the semaphore to be
+ * signaled. If the "timeout" argument is non-zero, the thread should
+ * only be blocked for the specified time (measured in
+ * milliseconds).
+ *
+ * If the timeout argument is non-zero, the return value is the number of
+ * milliseconds spent waiting for the semaphore to be signaled. If the
+ * semaphore wasn't signaled within the specified time, the return value is
+ * SYS_ARCH_TIMEOUT. If the thread didn't have to wait for the semaphore
+ * (i.e., it was already signaled), the function may return zero.
+ *
+ * Notice that lwIP implements a function with a similar name,
+ * sys_sem_wait(), that uses the sys_arch_sem_wait() function.
+ */
+u32_t
+sys_arch_sem_wait( sys_sem_t sem, u32_t timeout )
+{
+    portBASE_TYPE   xStatus;
+    portTickType    xTicksStart, xTicksEnd, xTicksElapsed;
+    u32_t           timespent;
+
+    LWIP_ASSERT( "sys_arch_sem_wait: sem != SYS_SEM_NULL", sem != SYS_SEM_NULL );
+    xTicksStart = xTaskGetTickCount(  );
+    if( timeout == 0 )
+    {
+        do
+        {
+            xStatus = xSemaphoreTake( sem, MS_TO_TICKS( 100 ) );
+        }
+        while( xStatus != pdTRUE );
+    }
+    else
+    {
+        xStatus = xSemaphoreTake( sem, MS_TO_TICKS( timeout ) );
+    }
+
+    /* Semaphore was signaled. */
+    if( xStatus == pdTRUE )
+    {
+        xTicksEnd = xTaskGetTickCount(  );
+        xTicksElapsed = xTicksEnd - xTicksStart;
+        timespent = TICKS_TO_MS( xTicksElapsed );
+    }
+    else
+    {
+        timespent = SYS_ARCH_TIMEOUT;
+    }
+    return timespent;
+}
+
+
+/* ------------------------ Start implementation ( Mailboxes ) ------------ */
+
+/* Creates an empty mailbox. */
+sys_mbox_t
+sys_mbox_new( void )
+{
+    xQueueHandle    mbox;
+
+    mbox = xQueueCreate( SYS_MBOX_SIZE, sizeof( void * ) );
+    if( mbox != SYS_MBOX_NULL )
+    {
+#ifdef SYS_STATS
+        vPortEnterCritical(  );
+        lwip_stats.sys.mbox.used++;
+        if( lwip_stats.sys.mbox.used > lwip_stats.sys.mbox.max )
+        {
+            lwip_stats.sys.mbox.max = lwip_stats.sys.mbox.used;
+        }
+        vPortExitCritical(  );
+#endif
+    }
+    return mbox;
+}
+
+/*
+  Deallocates a mailbox. If there are messages still present in the
+  mailbox when the mailbox is deallocated, it is an indication of a
+  programming error in lwIP and the developer should be notified.
+*/
+void
+sys_mbox_free( sys_mbox_t mbox )
+{
+    void           *msg;
+
+    LWIP_ASSERT( "sys_mbox_free: mbox != SYS_MBOX_NULL", mbox != SYS_MBOX_NULL );
+    if( mbox != SYS_MBOX_NULL )
+    {
+        while( uxQueueMessagesWaiting( mbox ) != 0 )
+        {
+            if( sys_arch_mbox_fetch( mbox, &msg, 1 ) != SYS_ARCH_TIMEOUT )
+            {
+                LWIP_ASSERT( "sys_mbox_free: memory leak (msg != NULL)", msg == NULL );
+            }
+        }
+        vQueueDelete( mbox );
+#ifdef SYS_STATS
+        vPortEnterCritical(  );
+        lwip_stats.sys.mbox.used--;
+        vPortExitCritical(  );
+#endif
+    }
+}
+
+/*
+ * This function sends a message to a mailbox. It is unusual in that no error
+ * return is made. This is because the caller is responsible for ensuring that
+ * the mailbox queue will not fail. The caller does this by limiting the number
+ * of msg structures which exist for a given mailbox.
+ */
+void
+sys_mbox_post( sys_mbox_t mbox, void *data )
+{
+    portBASE_TYPE   xQueueSent;
+
+    /* Queue must not be full - Otherwise it is an error. */
+    xQueueSent = xQueueSend( mbox, &data, 0 );
+    LWIP_ASSERT( "sys_mbox_post: xQueueSent == pdPASS", xQueueSent == pdPASS );
+}
+
+/*
+ * Blocks the thread until a message arrives in the mailbox, but does
+ * not block the thread longer than "timeout" milliseconds (similar to
+ * the sys_arch_sem_wait() function). The "msg" argument is a result
+ * parameter that is set by the function (i.e., by doing "*msg =
+ * ptr"). The "msg" parameter maybe NULL to indicate that the message
+ * should be dropped.
+ *
+ * Note that a function with a similar name, sys_mbox_fetch(), is
+ * implemented by lwIP.
+ */
+u32_t
+sys_arch_mbox_fetch( sys_mbox_t mbox, void **msg, u32_t timeout )
+{
+    void           *ret_msg;
+    portBASE_TYPE   xStatus;
+    portTickType    xTicksStart, xTicksEnd, xTicksElapsed;
+    u32_t           timespent;
+
+    LWIP_ASSERT( "sys_arch_mbox_fetch: mbox != SYS_MBOX_NULL", mbox != SYS_MBOX_NULL );
+    xTicksStart = xTaskGetTickCount(  );
+    if( timeout == 0 )
+    {
+        do
+        {
+            xStatus = xQueueReceive( mbox, &ret_msg, MS_TO_TICKS( 100 ) );
+        }
+        while( xStatus != pdTRUE );
+    }
+    else
+    {
+        xStatus = xQueueReceive( mbox, &ret_msg, MS_TO_TICKS( timeout ) );
+    }
+
+    if( xStatus == pdTRUE )
+    {
+        if( msg )
+        {
+            *msg = ret_msg;
+        }
+        xTicksEnd = xTaskGetTickCount(  );
+        xTicksElapsed = xTicksEnd - xTicksStart;
+        timespent = TICKS_TO_MS( xTicksElapsed );
+    }
+    else
+    {
+        if( msg )
+        {
+            *msg = NULL;
+        }
+        timespent = SYS_ARCH_TIMEOUT;
+    }
+    return timespent;
+}
+
+u32_t
+sys_jiffies( void )
+{
+    portTickType    xTicks = xTaskGetTickCount(  );
+
+    return ( u32_t )TICKS_TO_MS( xTicks );
+}
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/doc/contrib.txt b/20080212/Demo/lwIP_MCF5235_GCC/lwip/doc/contrib.txt
new file mode 100644
index 000000000..7c99b9be2
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/doc/contrib.txt
@@ -0,0 +1,62 @@
+1 Introduction
+
+This document describes some guidelines for people participating
+in lwIP development.
+
+2 How to contribute to lwIP
+
+Here is a short list of suggestions to anybody working with lwIP and 
+trying to contribute bug reports, fixes, enhancements, platform ports etc.
+First of all as you may already know lwIP is a volunteer project so feedback
+to fixes or questions might often come late. Hopefully the bug and patch tracking 
+features of Savannah help us not lose users' input.
+
+2.1 Source code style:
+
+1. do not use tabs.
+2. indentation is two spaces per level (i.e. per tab).
+3. end debug messages with a trailing newline (\n).
+4. one space between keyword and opening bracket.
+5. no space between function and opening bracket.
+6. one space and no newline before opening curly braces of a block.
+7. closing curly brace on a single line.
+8. spaces surrounding assignment and comparisons.
+9. use current source code style as further reference.
+
+2.2 Source code documentation style:
+
+1. JavaDoc compliant and Doxygen compatible.
+2. Function documentation above functions in .c files, not .h files.
+   (This forces you to synchronize documentation and implementation.)
+3. Use current documentation style as further reference.
+ 
+2.3 Bug reports and patches:
+
+1. Make sure you are reporting bugs or send patches against the latest
+   sources. (From the latest release and/or the current CVS sources.)
+2. If you think you found a bug make sure it's not already filed in the
+   bugtracker at Savannah.
+3. If you have a fix put the patch on Savannah. If it is a patch that affects
+   both core and arch specific stuff please separate them so that the core can
+   be applied separately while leaving the other patch 'open'. The prefered way
+   is to NOT touch archs you can't test and let maintainers take care of them.
+   This is a good way to see if they are used at all - the same goes for unix
+   netifs except tapif.
+4. Do not file a bug and post a fix to it to the patch area. Either a bug report
+   or a patch will be enough.
+   If you correct an existing bug then attach the patch to the bug rather than creating a new entry in the patch area.
+5. Trivial patches (compiler warning, indentation and spelling fixes or anything obvious which takes a line or two)
+   can go to the lwip-users list. This is still the fastest way of interaction and the list is not so crowded
+   as to allow for loss of fixes. Putting bugs on Savannah and subsequently closing them is too much an overhead
+   for reporting a compiler warning fix.
+6. Patches should be specific to a single change or to related changes.Do not mix bugfixes with spelling and other
+   trivial fixes unless the bugfix is trivial too.Do not reorganize code and rename identifiers in the same patch you
+   change behaviour if not necessary.A patch is easier to read and understand if it's to the point and short than
+   if it's not to the point and long :) so the chances for it to be applied are greater. 
+
+2.4 Platform porters:
+
+1. If you have ported lwIP to a platform (an OS, a uC/processor or a combination of these) and
+   you think it could benefit others[1] you might want discuss this on the mailing list. You
+   can also ask for CVS access to submit and maintain your port in the contrib CVS module.
+   
\ No newline at end of file
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/doc/rawapi.txt b/20080212/Demo/lwIP_MCF5235_GCC/lwip/doc/rawapi.txt
new file mode 100644
index 000000000..f84e0d2eb
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/doc/rawapi.txt
@@ -0,0 +1,386 @@
+Raw TCP/IP interface for lwIP
+
+Authors: Adam Dunkels, Leon Woestenberg, Christiaan Simons
+
+lwIP provides two Application Program's Interfaces (APIs) for programs
+to use for communication with the TCP/IP code:
+* low-level "core" / "callback" or "raw" API.
+* higher-level "sequential" API.
+
+The sequential API provides a way for ordinary, sequential, programs
+to use the lwIP stack. It is quite similar to the BSD socket API. The
+model of execution is based on the blocking open-read-write-close
+paradigm. Since the TCP/IP stack is event based by nature, the TCP/IP
+code and the application program must reside in different execution
+contexts (threads).
+
+** The remainder of this document discusses the "raw" API. **
+
+The raw TCP/IP interface allows the application program to integrate
+better with the TCP/IP code. Program execution is event based by
+having callback functions being called from within the TCP/IP
+code. The TCP/IP code and the application program both run in the same
+thread. The sequential API has a much higher overhead and is not very
+well suited for small systems since it forces a multithreaded paradigm
+on the application.
+
+The raw TCP/IP interface is not only faster in terms of code execution
+time but is also less memory intensive. The drawback is that program
+development is somewhat harder and application programs written for
+the raw TCP/IP interface are more difficult to understand. Still, this
+is the preferred way of writing applications that should be small in
+code size and memory usage.
+
+Both APIs can be used simultaneously by different application
+programs. In fact, the sequential API is implemented as an application
+program using the raw TCP/IP interface.
+
+--- Callbacks
+
+Program execution is driven by callbacks. Each callback is an ordinary
+C function that is called from within the TCP/IP code. Every callback
+function is passed the current TCP or UDP connection state as an
+argument. Also, in order to be able to keep program specific state,
+the callback functions are called with a program specified argument
+that is independent of the TCP/IP state.
+
+The function for setting the application connection state is:
+
+- void tcp_arg(struct tcp_pcb *pcb, void *arg)
+
+  Specifies the program specific state that should be passed to all
+  other callback functions. The "pcb" argument is the current TCP
+  connection control block, and the "arg" argument is the argument
+  that will be passed to the callbacks.
+
+  
+--- TCP connection setup
+
+The functions used for setting up connections is similar to that of
+the sequential API and of the BSD socket API. A new TCP connection
+identifier (i.e., a protocol control block - PCB) is created with the
+tcp_new() function. This PCB can then be either set to listen for new
+incoming connections or be explicitly connected to another host.
+
+- struct tcp_pcb *tcp_new(void)
+
+  Creates a new connection identifier (PCB). If memory is not
+  available for creating the new pcb, NULL is returned.
+
+- err_t tcp_bind(struct tcp_pcb *pcb, struct ip_addr *ipaddr,
+                 u16_t port)
+
+  Binds the pcb to a local IP address and port number. The IP address
+  can be specified as IP_ADDR_ANY in order to bind the connection to
+  all local IP addresses.
+
+  If another connection is bound to the same port, the function will
+  return ERR_USE, otherwise ERR_OK is returned.
+
+- struct tcp_pcb *tcp_listen(struct tcp_pcb *pcb)
+
+  Commands a pcb to start listening for incoming connections. When an
+  incoming connection is accepted, the function specified with the
+  tcp_accept() function will be called. The pcb will have to be bound
+  to a local port with the tcp_bind() function.
+
+  The tcp_listen() function returns a new connection identifier, and
+  the one passed as an argument to the function will be
+  deallocated. The reason for this behavior is that less memory is
+  needed for a connection that is listening, so tcp_listen() will
+  reclaim the memory needed for the original connection and allocate a
+  new smaller memory block for the listening connection.
+
+  tcp_listen() may return NULL if no memory was available for the
+  listening connection. If so, the memory associated with the pcb
+  passed as an argument to tcp_listen() will not be deallocated.
+
+- void tcp_accept(struct tcp_pcb *pcb,
+                  err_t (* accept)(void *arg, struct tcp_pcb *newpcb,
+                                   err_t err))
+
+  Specified the callback function that should be called when a new
+  connection arrives on a listening connection.
+      
+- err_t tcp_connect(struct tcp_pcb *pcb, struct ip_addr *ipaddr,
+                    u16_t port, err_t (* connected)(void *arg,
+                                                    struct tcp_pcb *tpcb,
+                                                    err_t err));
+
+  Sets up the pcb to connect to the remote host and sends the
+  initial SYN segment which opens the connection. 
+
+  The tcp_connect() function returns immediately; it does not wait for
+  the connection to be properly setup. Instead, it will call the
+  function specified as the fourth argument (the "connected" argument)
+  when the connection is established. If the connection could not be
+  properly established, either because the other host refused the
+  connection or because the other host didn't answer, the "connected"
+  function will be called with an the "err" argument set accordingly.
+
+  The tcp_connect() function can return ERR_MEM if no memory is
+  available for enqueueing the SYN segment. If the SYN indeed was
+  enqueued successfully, the tcp_connect() function returns ERR_OK.
+
+  
+--- Sending TCP data
+
+TCP data is sent by enqueueing the data with a call to
+tcp_write(). When the data is successfully transmitted to the remote
+host, the application will be notified with a call to a specified
+callback function.
+
+- err_t tcp_write(struct tcp_pcb *pcb, void *dataptr, u16_t len,
+                  u8_t copy)
+
+  Enqueues the data pointed to by the argument dataptr. The length of
+  the data is passed as the len parameter. The copy argument is either
+  0 or 1 and indicates whether the new memory should be allocated for
+  the data to be copied into. If the argument is 0, no new memory
+  should be allocated and the data should only be referenced by
+  pointer.
+
+  The tcp_write() function will fail and return ERR_MEM if the length
+  of the data exceeds the current send buffer size or if the length of
+  the queue of outgoing segment is larger than the upper limit defined
+  in lwipopts.h. The number of bytes available in the output queue can
+  be retrieved with the tcp_sndbuf() function.
+
+  The proper way to use this function is to call the function with at
+  most tcp_sndbuf() bytes of data. If the function returns ERR_MEM,
+  the application should wait until some of the currently enqueued
+  data has been successfully received by the other host and try again.
+
+- void tcp_sent(struct tcp_pcb *pcb,
+                err_t (* sent)(void *arg, struct tcp_pcb *tpcb,
+		               u16_t len))
+
+  Specifies the callback function that should be called when data has
+  successfully been received (i.e., acknowledged) by the remote
+  host. The len argument passed to the callback function gives the
+  amount bytes that was acknowledged by the last acknowledgment.
+
+  
+--- Receiving TCP data
+
+TCP data reception is callback based - an application specified
+callback function is called when new data arrives. When the
+application has taken the data, it has to call the tcp_recved()
+function to indicate that TCP can advertise increase the receive
+window.
+
+- void tcp_recv(struct tcp_pcb *pcb,
+                err_t (* recv)(void *arg, struct tcp_pcb *tpcb,
+                               struct pbuf *p, err_t err))
+
+  Sets the callback function that will be called when new data
+  arrives. The callback function will be passed a NULL pbuf to
+  indicate that the remote host has closed the connection.
+
+- void tcp_recved(struct tcp_pcb *pcb, u16_t len)
+
+  Must be called when the application has received the data. The len
+  argument indicates the length of the received data.
+    
+
+--- Application polling
+
+When a connection is idle (i.e., no data is either transmitted or
+received), lwIP will repeatedly poll the application by calling a
+specified callback function. This can be used either as a watchdog
+timer for killing connections that have stayed idle for too long, or
+as a method of waiting for memory to become available. For instance,
+if a call to tcp_write() has failed because memory wasn't available,
+the application may use the polling functionality to call tcp_write()
+again when the connection has been idle for a while.
+
+- void tcp_poll(struct tcp_pcb *pcb, u8_t interval,
+                err_t (* poll)(void *arg, struct tcp_pcb *tpcb))
+
+  Specifies the polling interval and the callback function that should
+  be called to poll the application. The interval is specified in
+  number of TCP coarse grained timer shots, which typically occurs
+  twice a second. An interval of 10 means that the application would
+  be polled every 5 seconds.
+
+
+--- Closing and aborting connections
+
+- err_t tcp_close(struct tcp_pcb *pcb)
+
+  Closes the connection. The function may return ERR_MEM if no memory
+  was available for closing the connection. If so, the application
+  should wait and try again either by using the acknowledgment
+  callback or the polling functionality. If the close succeeds, the
+  function returns ERR_OK.
+
+  The pcb is deallocated by the TCP code after a call to tcp_close(). 
+
+- void tcp_abort(struct tcp_pcb *pcb)
+
+  Aborts the connection by sending a RST (reset) segment to the remote
+  host. The pcb is deallocated. This function never fails.
+
+If a connection is aborted because of an error, the application is
+alerted of this event by the err callback. Errors that might abort a
+connection are when there is a shortage of memory. The callback
+function to be called is set using the tcp_err() function.
+
+- void tcp_err(struct tcp_pcb *pcb, void (* err)(void *arg,
+	       err_t err))
+
+  The error callback function does not get the pcb passed to it as a
+  parameter since the pcb may already have been deallocated.
+
+
+--- Lower layer TCP interface
+
+TCP provides a simple interface to the lower layers of the
+system. During system initialization, the function tcp_init() has
+to be called before any other TCP function is called. When the system
+is running, the two timer functions tcp_fasttmr() and tcp_slowtmr()
+must be called with regular intervals. The tcp_fasttmr() should be
+called every TCP_FAST_INTERVAL milliseconds (defined in tcp.h) and
+tcp_slowtmr() should be called every TCP_SLOW_INTERVAL milliseconds. 
+
+
+--- UDP interface
+
+The UDP interface is similar to that of TCP, but due to the lower
+level of complexity of UDP, the interface is significantly simpler.
+
+- struct udp_pcb *udp_new(void)
+
+  Creates a new UDP pcb which can be used for UDP communication. The
+  pcb is not active until it has either been bound to a local address
+  or connected to a remote address.
+
+- void udp_remove(struct udp_pcb *pcb)
+
+  Removes and deallocates the pcb.  
+  
+- err_t udp_bind(struct udp_pcb *pcb, struct ip_addr *ipaddr,
+                 u16_t port)
+
+  Binds the pcb to a local address. The IP-address argument "ipaddr"
+  can be IP_ADDR_ANY to indicate that it should listen to any local IP
+  address. The function currently always return ERR_OK.
+
+- err_t udp_connect(struct udp_pcb *pcb, struct ip_addr *ipaddr,
+                    u16_t port)
+
+  Sets the remote end of the pcb. This function does not generate any
+  network traffic, but only set the remote address of the pcb.
+
+- err_t udp_disconnect(struct udp_pcb *pcb)
+
+  Remove the remote end of the pcb. This function does not generate
+  any network traffic, but only removes the remote address of the pcb.
+
+- err_t udp_send(struct udp_pcb *pcb, struct pbuf *p)
+
+  Sends the pbuf p. The pbuf is not deallocated.
+
+- void udp_recv(struct udp_pcb *pcb,
+                void (* recv)(void *arg, struct udp_pcb *upcb,
+                                         struct pbuf *p,
+                                         struct ip_addr *addr,
+                                         u16_t port),
+                              void *recv_arg)
+
+  Specifies a callback function that should be called when a UDP
+  datagram is received.
+  
+
+--- System initalization
+
+A truly complete and generic sequence for initializing the lwip stack
+cannot be given because it depends on the build configuration (lwipopts.h)
+and additional initializations for your runtime environment (e.g. timers).
+
+We can give you some idea on how to proceed when using the raw API.
+We assume a configuration using a single Ethernet netif and the
+UDP and TCP transport layers, IPv4 and the DHCP client.
+
+Call these functions in the order of appearance:
+
+- stats_init()
+
+  Clears the structure where runtime statistics are gathered.
+
+- sys_init()
+  
+  Not of much use since we set the NO_SYS 1 option in lwipopts.h,
+  to be called for easy configuration changes.
+
+- mem_init()
+
+  Initializes the dynamic memory heap defined by MEM_SIZE.
+
+- memp_init()
+
+  Initializes the memory pools defined by MEMP_NUM_x.
+
+- pbuf_init()
+
+  Initializes the pbuf memory pool defined by PBUF_POOL_SIZE.
+  
+- etharp_init()
+
+  Initializes the ARP table and queue.
+  Note: you must call etharp_tmr at a 10 second regular interval
+  after this initialization.
+
+- ip_init()
+
+  Doesn't do much, it should be called to handle future changes.
+
+- udp_init()
+
+  Clears the UDP PCB list.
+
+- tcp_init()
+
+  Clears the TCP PCB list and clears some internal TCP timers.
+  Note: you must call tcp_fasttmr() and tcp_slowtmr() at the
+  predefined regular intervals after this initialization. 
+  
+- netif_add(struct netif *netif, struct ip_addr *ipaddr,
+            struct ip_addr *netmask, struct ip_addr *gw,
+            void *state, err_t (* init)(struct netif *netif),
+            err_t (* input)(struct pbuf *p, struct netif *netif))
+
+  Adds your network interface to the netif_list. Allocate a struct
+  netif and pass a pointer to this structure as the first argument.
+  Give pointers to cleared ip_addr structures when using DHCP,
+  or fill them with sane numbers otherwise. The state pointer may be NULL.
+
+  The init function pointer must point to a initialization function for
+  your ethernet netif interface. The following code illustrates it's use.
+  
+  err_t netif_if_init(struct netif *netif)
+  {
+    u8_t i;
+    
+    for(i = 0; i < 6; i++) netif->hwaddr[i] = some_eth_addr[i];
+    init_my_eth_device();
+    return ERR_OK;
+  }
+  
+  The input function pointer must point to the lwip ip_input().
+  
+- netif_set_default(struct netif *netif)
+
+  Registers the default network interface.
+
+- netif_set_up(struct netif *netif)
+
+  When the netif is fully configured this function must be called.
+
+- dhcp_start(struct netif *netif)
+
+  Creates a new DHCP client for this interface on the first call.
+  Note: you must call dhcp_fine_tmr() and dhcp_coarse_tmr() at
+  the predefined regular intervals after starting the client.
+  
+  You can peek in the netif->dhcp struct for the actual DHCP status.
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/doc/savannah.txt b/20080212/Demo/lwIP_MCF5235_GCC/lwip/doc/savannah.txt
new file mode 100644
index 000000000..409905b10
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/doc/savannah.txt
@@ -0,0 +1,135 @@
+Daily Use Guide for using Savannah for lwIP
+
+Table of Contents:
+
+1 - Obtaining lwIP from the CVS repository
+2 - Committers/developers CVS access using SSH (to be written)
+3 - Merging from DEVEL branch to main trunk (stable branch)
+4 - How to release lwIP
+
+
+
+1 Obtaining lwIP from the CVS repository
+----------------------------------------
+
+To perform an anonymous CVS checkout of the main trunk (this is where
+bug fixes and incremental enhancements occur), do this:
+
+cvs -z3 -d:pserver:anonymous@cvs.sv.gnu.org:/sources/lwip checkout lwip
+ 
+Or, obtain a stable branch (updated with bug fixes only) as follows:
+cvs -z3 -d:pserver:anonymous@cvs.sv.gnu.org:/sources/lwip checkout \
+  -r STABLE-0_7 -d lwip-0.7 lwip
+
+Or, obtain a specific (fixed) release as follows:
+cvs -z3 -d:pserver:anonymous@cvs.sv.gnu.org:/sources/lwip checkout \
+  -r STABLE-0_7_0 -d lwip-0.7.0 lwip
+
+3 Committers/developers CVS access using SSH
+--------------------------------------------
+
+The Savannah server uses SSH (Secure Shell) protocol 2 authentication and encryption.
+As such, CVS commits to the server occur through a SSH tunnel for project members.
+To create a SSH2 key pair in UNIX-like environments, do this:
+
+ssh-keygen -t dsa
+
+Under Windows, a recommended SSH client is "PuTTY", freely available with good
+documentation and a graphic user interface. Use its key generator.
+
+Now paste the id_dsa.pub contents into your Savannah account public key list. Wait
+a while so that Savannah can update its configuration (This can take minutes).
+
+Try to login using SSH:
+
+ssh -v your_login@cvs.sv.gnu.org
+
+If it tells you:
+
+Authenticating with public key "your_key_name"...
+Server refused to allocate pty
+
+then you could login; Savannah refuses to give you a shell - which is OK, as we
+are allowed to use SSH for CVS only. Now, you should be able to do this:
+
+export CVS_RSH=ssh
+cvs -z3 -d:ext:your_login@cvs.sv.gnu.org:/sources/lwip co lwip
+ 
+after which you can edit your local files with bug fixes or new features and
+commit them. Make sure you know what you are doing when using CVS to make
+changes on the repository. If in doubt, ask on the lwip-members mailing list.
+
+(If SSH asks about authenticity of the host, you can check the key
+ fingerprint against http://savannah.nongnu.org/cvs/?group=lwip)
+
+
+3 Merging from DEVEL branch to main trunk (stable)
+--------------------------------------------------
+
+Merging is a delicate process in CVS and requires the
+following disciplined steps in order to prevent conflicts
+in the future. Conflicts can be hard to solve!
+
+Merging from branch A to branch B requires that the A branch
+has a tag indicating the previous merger. This tag is called
+'merged_from_A_to_B'. After merging, the tag is moved in the
+A branch to remember this merger for future merge actions.
+
+IMPORTANT: AFTER COMMITTING A SUCCESFUL MERGE IN THE
+REPOSITORY, THE TAG MUST BE SET ON THE SOURCE BRANCH OF THE
+MERGE ACTION (REPLACING EXISTING TAGS WITH THE SAME NAME).
+
+Merge all changes in DEVEL since our last merge to main:
+
+In the working copy of the main trunk:
+cvs update -P -jmerged_from_DEVEL_to_main -jDEVEL 
+
+(This will apply the changes between 'merged_from_DEVEL_to_main'
+and 'DEVEL' to your work set of files)
+
+We can now commit the merge result.
+cvs commit -R -m "Merged from DEVEL to main." 
+
+If this worked out OK, we now move the tag in the DEVEL branch
+to this merge point, so we can use this point for future merges:
+
+cvs rtag -F -r DEVEL merged_from_DEVEL_to_main lwip 
+
+4 How to release lwIP
+---------------------
+
+First, checkout a clean copy of the branch to be released. Tag this set with
+tag name "STABLE-0_6_3". (I use release number 0.6.3 throughout this example).
+
+Login CVS using pserver authentication, then export a clean copy of the
+tagged tree. Export is similar to a checkout, except that the CVS metadata
+is not created locally. 
+
+export CVS_RSH=ssh
+cvs -z3 -d:pserver:anonymous@cvs.sv.gnu.org:/sources/lwip checkout \
+  -r STABLE-0_6_3 -d lwip-0.6.3 lwip
+
+Archive this directory using tar, gzip'd, bzip2'd and zip'd.
+
+tar czvf lwip-0.6.3.tar.gz lwip-0.6.3
+tar cjvf lwip-0.6.3.tar.bz2 lwip-0.6.3
+zip -r lwip-0.6.3.zip lwip-0.6.3
+
+Now, sign the archives with a detached GPG binary signature as follows:
+
+gpg -b lwip-0.6.3.tar.gz
+gpg -b lwip-0.6.3.tar.bz2
+gpg -b lwip-0.6.3.zip
+
+Upload these files using anonymous FTP:
+ncftp ftp://savannah.gnu.org/incoming/savannah/lwip
+
+ncftp>mput *0.6.3.*
+
+Additionally, you may post a news item on Savannah, like this:
+
+A new 0.6.3 release is now available here:
+http://savannah.nongnu.org/files/?group=lwip&highlight=0.6.3
+
+You will have to submit this via the user News interface, then approve
+this via the Administrator News interface.
\ No newline at end of file
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/doc/sys_arch.txt b/20080212/Demo/lwIP_MCF5235_GCC/lwip/doc/sys_arch.txt
new file mode 100644
index 000000000..95d0add73
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/doc/sys_arch.txt
@@ -0,0 +1,194 @@
+sys_arch interface for lwIP 0.6++
+
+Author: Adam Dunkels
+
+The operating system emulation layer provides a common interface
+between the lwIP code and the underlying operating system kernel. The
+general idea is that porting lwIP to new architectures requires only
+small changes to a few header files and a new sys_arch
+implementation. It is also possible to do a sys_arch implementation
+that does not rely on any underlying operating system.
+
+The sys_arch provides semaphores and mailboxes to lwIP. For the full
+lwIP functionality, multiple threads support can be implemented in the
+sys_arch, but this is not required for the basic lwIP
+functionality. Previous versions of lwIP required the sys_arch to
+implement timer scheduling as well but as of lwIP 0.5 this is
+implemented in a higher layer.
+
+In addition to the source file providing the functionality of sys_arch,
+the OS emulation layer must provide several header files defining
+macros used throughout lwip.  The files required and the macros they
+must define are listed below the sys_arch description.
+
+Semaphores can be either counting or binary - lwIP works with both
+kinds. Mailboxes are used for message passing and can be implemented
+either as a queue which allows multiple messages to be posted to a
+mailbox, or as a rendez-vous point where only one message can be
+posted at a time. lwIP works with both kinds, but the former type will
+be more efficient. A message in a mailbox is just a pointer, nothing
+more. 
+
+Semaphores are represented by the type "sys_sem_t" which is typedef'd
+in the sys_arch.h file. Mailboxes are equivalently represented by the
+type "sys_mbox_t". lwIP does not place any restrictions on how
+sys_sem_t or sys_mbox_t are represented internally.
+
+The following functions must be implemented by the sys_arch:
+
+- void sys_init(void)
+
+  Is called to initialize the sys_arch layer.
+
+- sys_sem_t sys_sem_new(u8_t count)
+
+  Creates and returns a new semaphore. The "count" argument specifies
+  the initial state of the semaphore.
+
+- void sys_sem_free(sys_sem_t sem)
+
+  Deallocates a semaphore.
+
+- void sys_sem_signal(sys_sem_t sem)
+
+  Signals a semaphore.
+
+- u32_t sys_arch_sem_wait(sys_sem_t sem, u32_t timeout)
+
+  Blocks the thread while waiting for the semaphore to be
+  signaled. If the "timeout" argument is non-zero, the thread should
+  only be blocked for the specified time (measured in
+  milliseconds).
+
+  If the timeout argument is non-zero, the return value is the number of
+  milliseconds spent waiting for the semaphore to be signaled. If the
+  semaphore wasn't signaled within the specified time, the return value is
+  SYS_ARCH_TIMEOUT. If the thread didn't have to wait for the semaphore
+  (i.e., it was already signaled), the function may return zero.
+
+  Notice that lwIP implements a function with a similar name,
+  sys_sem_wait(), that uses the sys_arch_sem_wait() function.
+
+- sys_mbox_t sys_mbox_new(void)
+
+  Creates an empty mailbox.
+
+- void sys_mbox_free(sys_mbox_t mbox)
+
+  Deallocates a mailbox. If there are messages still present in the
+  mailbox when the mailbox is deallocated, it is an indication of a
+  programming error in lwIP and the developer should be notified.
+
+- void sys_mbox_post(sys_mbox_t mbox, void *msg)
+
+  Posts the "msg" to the mailbox.
+
+- u32_t sys_arch_mbox_fetch(sys_mbox_t mbox, void **msg, u32_t timeout)
+
+  Blocks the thread until a message arrives in the mailbox, but does
+  not block the thread longer than "timeout" milliseconds (similar to
+  the sys_arch_sem_wait() function). The "msg" argument is a result
+  parameter that is set by the function (i.e., by doing "*msg =
+  ptr"). The "msg" parameter maybe NULL to indicate that the message
+  should be dropped.
+
+  The return values are the same as for the sys_arch_sem_wait() function:
+  Number of milliseconds spent waiting or SYS_ARCH_TIMEOUT if there was a
+  timeout.
+
+  Note that a function with a similar name, sys_mbox_fetch(), is
+  implemented by lwIP. 
+  
+- struct sys_timeouts *sys_arch_timeouts(void)
+
+  Returns a pointer to the per-thread sys_timeouts structure. In lwIP,
+  each thread has a list of timeouts which is repressented as a linked
+  list of sys_timeout structures. The sys_timeouts structure holds a
+  pointer to a linked list of timeouts. This function is called by
+  the lwIP timeout scheduler and must not return a NULL value. 
+
+  In a single threadd sys_arch implementation, this function will
+  simply return a pointer to a global sys_timeouts variable stored in
+  the sys_arch module.
+  
+If threads are supported by the underlying operating system and if
+such functionality is needed in lwIP, the following function will have
+to be implemented as well:
+
+- sys_thread_t sys_thread_new(void (* thread)(void *arg), void *arg, int prio)
+
+  Starts a new thread with priority "prio" that will begin its execution in the
+  function "thread()". The "arg" argument will be passed as an argument to the
+  thread() function. The id of the new thread is returned. Both the id and
+  the priority are system dependent.
+
+- sys_prot_t sys_arch_protect(void)
+
+  This optional function does a "fast" critical region protection and returns
+  the previous protection level. This function is only called during very short
+  critical regions. An embedded system which supports ISR-based drivers might
+  want to implement this function by disabling interrupts. Task-based systems
+  might want to implement this by using a mutex or disabling tasking. This
+  function should support recursive calls from the same task or interrupt. In
+  other words, sys_arch_protect() could be called while already protected. In
+  that case the return value indicates that it is already protected.
+
+  sys_arch_protect() is only required if your port is supporting an operating
+  system.
+
+- void sys_arch_unprotect(sys_prot_t pval)
+
+  This optional function does a "fast" set of critical region protection to the
+  value specified by pval. See the documentation for sys_arch_protect() for
+  more information. This function is only required if your port is supporting
+  an operating system.
+
+-------------------------------------------------------------------------------
+Additional files required for the "OS support" emulation layer:
+-------------------------------------------------------------------------------
+
+cc.h       - Architecture environment, some compiler specific, some
+             environment specific (probably should move env stuff 
+             to sys_arch.h.)
+
+  Typedefs for the types used by lwip -
+    u8_t, s8_t, u16_t, s16_t, u32_t, s32_t, mem_ptr_t
+
+  Compiler hints for packing lwip's structures -
+    PACK_STRUCT_FIELD(x)
+    PACK_STRUCT_STRUCT
+    PACK_STRUCT_BEGIN
+    PACK_STRUCT_END
+
+  Platform specific diagnostic output -
+    LWIP_PLATFORM_DIAG(x)    - non-fatal, print a message.
+    LWIP_PLATFORM_ASSERT(x)  - fatal, print message and abandon execution.
+
+  "lightweight" synchronization mechanisms -
+    SYS_ARCH_DECL_PROTECT(x) - declare a protection state variable.
+    SYS_ARCH_PROTECT(x)      - enter protection mode.
+    SYS_ARCH_UNPROTECT(x)    - leave protection mode.
+
+  If the compiler does not provide memset() this file must include a
+  definition of it, or include a file which defines it.
+
+  This file must either include a system-local  which defines
+  the standard *nix error codes, or it should #define LWIP_PROVIDE_ERRNO
+  to make lwip/arch.h define the codes which are used throughout.
+
+
+perf.h     - Architecture specific performance measurement.
+  Measurement calls made throughout lwip, these can be defined to nothing.
+    PERF_START               - start measuring something.
+    PERF_STOP(x)             - stop measuring something, and record the result.
+
+sys_arch.h - Tied to sys_arch.c
+
+  Arch dependent types for the following objects:
+    sys_sem_t, sys_mbox_t, sys_thread_t,
+  And, optionally:
+    sys_prot_t
+
+  Defines to set vars of sys_mbox_t and sys_sem_t to NULL.
+    SYS_MBOX_NULL NULL
+    SYS_SEM_NULL NULL
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/FILES b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/FILES
new file mode 100644
index 000000000..2b6573185
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/FILES
@@ -0,0 +1,13 @@
+api/      - The code for the high-level wrapper API. Not needed if
+            you use the lowel-level call-back/raw API.
+
+core/     - The core of the TPC/IP stack; protocol implementations,
+            memory and buffer management, and the low-level raw API.
+	    
+include/  - lwIP include files.
+
+netif/    - Generic network interface device drivers are kept here,
+            as well as the ARP module.
+
+For more information on the various subdirectories, check the FILES
+file in each directory.
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/api/api_lib.c b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/api/api_lib.c
new file mode 100644
index 000000000..d9cf7efbe
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/api/api_lib.c
@@ -0,0 +1,729 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+/* This is the part of the API that is linked with
+   the application */
+
+#include "lwip/opt.h"
+#include "lwip/api.h"
+#include "lwip/api_msg.h"
+#include "lwip/memp.h"
+
+
+struct
+netbuf *netbuf_new(void)
+{
+  struct netbuf *buf;
+
+  buf = memp_malloc(MEMP_NETBUF);
+  if (buf != NULL) {
+    buf->p = NULL;
+    buf->ptr = NULL;
+    return buf;
+  } else {
+    return NULL;
+  }
+}
+
+void
+netbuf_delete(struct netbuf *buf)
+{
+  if (buf != NULL) {
+    if (buf->p != NULL) {
+      pbuf_free(buf->p);
+      buf->p = buf->ptr = NULL;
+    }
+    memp_free(MEMP_NETBUF, buf);
+  }
+}
+
+void *
+netbuf_alloc(struct netbuf *buf, u16_t size)
+{
+  /* Deallocate any previously allocated memory. */
+  if (buf->p != NULL) {
+    pbuf_free(buf->p);
+  }
+  buf->p = pbuf_alloc(PBUF_TRANSPORT, size, PBUF_RAM);
+  if (buf->p == NULL) {
+     return NULL;
+  }
+  buf->ptr = buf->p;
+  return buf->p->payload;
+}
+
+void
+netbuf_free(struct netbuf *buf)
+{
+  if (buf->p != NULL) {
+    pbuf_free(buf->p);
+  }
+  buf->p = buf->ptr = NULL;
+}
+
+void
+netbuf_ref(struct netbuf *buf, void *dataptr, u16_t size)
+{
+  if (buf->p != NULL) {
+    pbuf_free(buf->p);
+  }
+  buf->p = pbuf_alloc(PBUF_TRANSPORT, 0, PBUF_REF);
+  buf->p->payload = dataptr;
+  buf->p->len = buf->p->tot_len = size;
+  buf->ptr = buf->p;
+}
+
+void
+netbuf_chain(struct netbuf *head, struct netbuf *tail)
+{
+  pbuf_chain(head->p, tail->p);
+  head->ptr = head->p;
+  memp_free(MEMP_NETBUF, tail);
+}
+
+u16_t
+netbuf_len(struct netbuf *buf)
+{
+  return buf->p->tot_len;
+}
+
+err_t
+netbuf_data(struct netbuf *buf, void **dataptr, u16_t *len)
+{
+  if (buf->ptr == NULL) {
+    return ERR_BUF;
+  }
+  *dataptr = buf->ptr->payload;
+  *len = buf->ptr->len;
+  return ERR_OK;
+}
+
+s8_t
+netbuf_next(struct netbuf *buf)
+{
+  if (buf->ptr->next == NULL) {
+    return -1;
+  }
+  buf->ptr = buf->ptr->next;
+  if (buf->ptr->next == NULL) {
+    return 1;
+  }
+  return 0;
+}
+
+void
+netbuf_first(struct netbuf *buf)
+{
+  buf->ptr = buf->p;
+}
+
+void
+netbuf_copy_partial(struct netbuf *buf, void *dataptr, u16_t len, u16_t offset)
+{
+  struct pbuf *p;
+  u16_t i, left;
+
+  left = 0;
+
+  if(buf == NULL || dataptr == NULL) {
+    return;
+  }
+  
+  /* This implementation is bad. It should use bcopy
+     instead. */
+  for(p = buf->p; left < len && p != NULL; p = p->next) {
+    if (offset != 0 && offset >= p->len) {
+      offset -= p->len;
+    } else {    
+      for(i = offset; i < p->len; ++i) {
+  ((u8_t *)dataptr)[left] = ((u8_t *)p->payload)[i];
+  if (++left >= len) {
+    return;
+  }
+      }
+      offset = 0;
+    }
+  }
+}
+
+void
+netbuf_copy(struct netbuf *buf, void *dataptr, u16_t len)
+{
+  netbuf_copy_partial(buf, dataptr, len, 0);
+}
+
+struct ip_addr *
+netbuf_fromaddr(struct netbuf *buf)
+{
+  return buf->fromaddr;
+}
+
+u16_t
+netbuf_fromport(struct netbuf *buf)
+{
+  return buf->fromport;
+}
+
+struct
+netconn *netconn_new_with_proto_and_callback(enum netconn_type t, u16_t proto,
+                                   void (*callback)(struct netconn *, enum netconn_evt, u16_t len))
+{
+  struct netconn *conn;
+  struct api_msg *msg;
+
+  conn = memp_malloc(MEMP_NETCONN);
+  if (conn == NULL) {
+    return NULL;
+  }
+  
+  conn->err = ERR_OK;
+  conn->type = t;
+  conn->pcb.tcp = NULL;
+
+  if ((conn->mbox = sys_mbox_new()) == SYS_MBOX_NULL) {
+    memp_free(MEMP_NETCONN, conn);
+    return NULL;
+  }
+  conn->recvmbox = SYS_MBOX_NULL;
+  conn->acceptmbox = SYS_MBOX_NULL;
+  conn->sem = SYS_SEM_NULL;
+  conn->state = NETCONN_NONE;
+  conn->socket = 0;
+  conn->callback = callback;
+  conn->recv_avail = 0;
+
+  if((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+    memp_free(MEMP_NETCONN, conn);
+    return NULL;
+  }
+  
+  msg->type = API_MSG_NEWCONN;
+  msg->msg.msg.bc.port = proto; /* misusing the port field */
+  msg->msg.conn = conn;
+  api_msg_post(msg);  
+  sys_mbox_fetch(conn->mbox, NULL);
+  memp_free(MEMP_API_MSG, msg);
+
+  if ( conn->err != ERR_OK ) {
+    memp_free(MEMP_NETCONN, conn);
+    return NULL;
+  }
+
+  return conn;
+}
+
+
+struct
+netconn *netconn_new(enum netconn_type t)
+{
+  return netconn_new_with_proto_and_callback(t,0,NULL);
+}
+
+struct
+netconn *netconn_new_with_callback(enum netconn_type t,
+                                   void (*callback)(struct netconn *, enum netconn_evt, u16_t len))
+{
+  return netconn_new_with_proto_and_callback(t,0,callback);
+}
+
+
+err_t
+netconn_delete(struct netconn *conn)
+{
+  struct api_msg *msg;
+  void *mem;
+  
+  if (conn == NULL) {
+    return ERR_OK;
+  }
+  
+  if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+    return ERR_MEM;
+  }
+  
+  msg->type = API_MSG_DELCONN;
+  msg->msg.conn = conn;
+  api_msg_post(msg);  
+  sys_mbox_fetch(conn->mbox, NULL);
+  memp_free(MEMP_API_MSG, msg);
+
+  /* Drain the recvmbox. */
+  if (conn->recvmbox != SYS_MBOX_NULL) {
+    while (sys_arch_mbox_fetch(conn->recvmbox, &mem, 1) != SYS_ARCH_TIMEOUT) {
+      if (conn->type == NETCONN_TCP) {
+        if(mem != NULL)
+          pbuf_free((struct pbuf *)mem);
+      } else {
+        netbuf_delete((struct netbuf *)mem);
+      }
+    }
+    sys_mbox_free(conn->recvmbox);
+    conn->recvmbox = SYS_MBOX_NULL;
+  }
+ 
+
+  /* Drain the acceptmbox. */
+  if (conn->acceptmbox != SYS_MBOX_NULL) {
+    while (sys_arch_mbox_fetch(conn->acceptmbox, &mem, 1) != SYS_ARCH_TIMEOUT) {
+      netconn_delete((struct netconn *)mem);
+    }
+    
+    sys_mbox_free(conn->acceptmbox);
+    conn->acceptmbox = SYS_MBOX_NULL;
+  }
+
+  sys_mbox_free(conn->mbox);
+  conn->mbox = SYS_MBOX_NULL;
+  if (conn->sem != SYS_SEM_NULL) {
+    sys_sem_free(conn->sem);
+  }
+  /*  conn->sem = SYS_SEM_NULL;*/
+  memp_free(MEMP_NETCONN, conn);
+  return ERR_OK;
+}
+
+enum netconn_type
+netconn_type(struct netconn *conn)
+{
+  return conn->type;
+}
+
+err_t
+netconn_peer(struct netconn *conn, struct ip_addr *addr,
+       u16_t *port)
+{
+  switch (conn->type) {
+  case NETCONN_RAW:
+    /* return an error as connecting is only a helper for upper layers */
+    return ERR_CONN;
+  case NETCONN_UDPLITE:
+  case NETCONN_UDPNOCHKSUM:
+  case NETCONN_UDP:
+    if (conn->pcb.udp == NULL ||
+  ((conn->pcb.udp->flags & UDP_FLAGS_CONNECTED) == 0))
+     return ERR_CONN;
+    *addr = (conn->pcb.udp->remote_ip);
+    *port = conn->pcb.udp->remote_port;
+    break;
+  case NETCONN_TCP:
+    if (conn->pcb.tcp == NULL)
+      return ERR_CONN;
+    *addr = (conn->pcb.tcp->remote_ip);
+    *port = conn->pcb.tcp->remote_port;
+    break;
+  }
+  return (conn->err = ERR_OK);
+}
+
+err_t
+netconn_addr(struct netconn *conn, struct ip_addr **addr,
+       u16_t *port)
+{
+  switch (conn->type) {
+  case NETCONN_RAW:
+    *addr = &(conn->pcb.raw->local_ip);
+    *port = conn->pcb.raw->protocol;
+    break;
+  case NETCONN_UDPLITE:
+  case NETCONN_UDPNOCHKSUM:
+  case NETCONN_UDP:
+    *addr = &(conn->pcb.udp->local_ip);
+    *port = conn->pcb.udp->local_port;
+    break;
+  case NETCONN_TCP:
+    *addr = &(conn->pcb.tcp->local_ip);
+    *port = conn->pcb.tcp->local_port;
+    break;
+  }
+  return (conn->err = ERR_OK);
+}
+
+err_t
+netconn_bind(struct netconn *conn, struct ip_addr *addr,
+      u16_t port)
+{
+  struct api_msg *msg;
+
+  if (conn == NULL) {
+    return ERR_VAL;
+  }
+
+  if (conn->type != NETCONN_TCP &&
+     conn->recvmbox == SYS_MBOX_NULL) {
+    if ((conn->recvmbox = sys_mbox_new()) == SYS_MBOX_NULL) {
+      return ERR_MEM;
+    }
+  }
+  
+  if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+    return (conn->err = ERR_MEM);
+  }
+  msg->type = API_MSG_BIND;
+  msg->msg.conn = conn;
+  msg->msg.msg.bc.ipaddr = addr;
+  msg->msg.msg.bc.port = port;
+  api_msg_post(msg);
+  sys_mbox_fetch(conn->mbox, NULL);
+  memp_free(MEMP_API_MSG, msg);
+  return conn->err;
+}
+
+
+err_t
+netconn_connect(struct netconn *conn, struct ip_addr *addr,
+       u16_t port)
+{
+  struct api_msg *msg;
+  
+  if (conn == NULL) {
+    return ERR_VAL;
+  }
+
+
+  if (conn->recvmbox == SYS_MBOX_NULL) {
+    if ((conn->recvmbox = sys_mbox_new()) == SYS_MBOX_NULL) {
+      return ERR_MEM;
+    }
+  }
+  
+  if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+    return ERR_MEM;
+  }
+  msg->type = API_MSG_CONNECT;
+  msg->msg.conn = conn;  
+  msg->msg.msg.bc.ipaddr = addr;
+  msg->msg.msg.bc.port = port;
+  api_msg_post(msg);
+  sys_mbox_fetch(conn->mbox, NULL);
+  memp_free(MEMP_API_MSG, msg);
+  return conn->err;
+}
+
+err_t
+netconn_disconnect(struct netconn *conn)
+{
+  struct api_msg *msg;
+  
+  if (conn == NULL) {
+    return ERR_VAL;
+  }
+
+  if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+    return ERR_MEM;
+  }
+  msg->type = API_MSG_DISCONNECT;
+  msg->msg.conn = conn;  
+  api_msg_post(msg);
+  sys_mbox_fetch(conn->mbox, NULL);
+  memp_free(MEMP_API_MSG, msg);
+  return conn->err;
+
+}
+
+err_t
+netconn_listen(struct netconn *conn)
+{
+  struct api_msg *msg;
+
+  if (conn == NULL) {
+    return ERR_VAL;
+  }
+
+  if (conn->acceptmbox == SYS_MBOX_NULL) {
+    conn->acceptmbox = sys_mbox_new();
+    if (conn->acceptmbox == SYS_MBOX_NULL) {
+      return ERR_MEM;
+    }
+  }
+  
+  if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+    return (conn->err = ERR_MEM);
+  }
+  msg->type = API_MSG_LISTEN;
+  msg->msg.conn = conn;
+  api_msg_post(msg);
+  sys_mbox_fetch(conn->mbox, NULL);
+  memp_free(MEMP_API_MSG, msg);
+  return conn->err;
+}
+
+struct netconn *
+netconn_accept(struct netconn *conn)
+{
+  struct netconn *newconn;
+  
+  if (conn == NULL) {
+    return NULL;
+  }
+  
+  sys_mbox_fetch(conn->acceptmbox, (void **)&newconn);
+  /* Register event with callback */
+  if (conn->callback)
+      (*conn->callback)(conn, NETCONN_EVT_RCVMINUS, 0);
+  
+  return newconn;
+}
+
+struct netbuf *
+netconn_recv(struct netconn *conn)
+{
+  struct api_msg *msg;
+  struct netbuf *buf;
+  struct pbuf *p;
+  u16_t len;
+    
+  if (conn == NULL) {
+    return NULL;
+  }
+  
+  if (conn->recvmbox == SYS_MBOX_NULL) {
+    conn->err = ERR_CONN;
+    return NULL;
+  }
+
+  if (conn->err != ERR_OK) {
+    return NULL;
+  }
+
+  if (conn->type == NETCONN_TCP) {
+    if (conn->pcb.tcp->state == LISTEN) {
+      conn->err = ERR_CONN;
+      return NULL;
+    }
+
+
+    buf = memp_malloc(MEMP_NETBUF);
+
+    if (buf == NULL) {
+      conn->err = ERR_MEM;
+      return NULL;
+    }
+    
+    sys_mbox_fetch(conn->recvmbox, (void **)&p);
+
+    if (p != NULL)
+    {
+        len = p->tot_len;
+        conn->recv_avail -= len;
+    }
+    else
+        len = 0;
+    
+    /* Register event with callback */
+      if (conn->callback)
+        (*conn->callback)(conn, NETCONN_EVT_RCVMINUS, len);
+
+    /* If we are closed, we indicate that we no longer wish to receive
+       data by setting conn->recvmbox to SYS_MBOX_NULL. */
+    if (p == NULL) {
+      memp_free(MEMP_NETBUF, buf);
+      sys_mbox_free(conn->recvmbox);
+      conn->recvmbox = SYS_MBOX_NULL;
+      return NULL;
+    }
+
+    buf->p = p;
+    buf->ptr = p;
+    buf->fromport = 0;
+    buf->fromaddr = NULL;
+
+    /* Let the stack know that we have taken the data. */
+    if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+      conn->err = ERR_MEM;
+      return buf;
+    }
+    msg->type = API_MSG_RECV;
+    msg->msg.conn = conn;
+    if (buf != NULL) {
+      msg->msg.msg.len = buf->p->tot_len;
+    } else {
+      msg->msg.msg.len = 1;
+    }
+    api_msg_post(msg);
+
+    sys_mbox_fetch(conn->mbox, NULL);
+    memp_free(MEMP_API_MSG, msg);
+  } else {
+    sys_mbox_fetch(conn->recvmbox, (void **)&buf);
+  conn->recv_avail -= buf->p->tot_len;
+    /* Register event with callback */
+    if (conn->callback)
+        (*conn->callback)(conn, NETCONN_EVT_RCVMINUS, buf->p->tot_len);
+  }
+
+  
+
+    
+  LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_recv: received %p (err %d)\n", (void *)buf, conn->err));
+
+
+  return buf;
+}
+
+err_t
+netconn_send(struct netconn *conn, struct netbuf *buf)
+{
+  struct api_msg *msg;
+
+  if (conn == NULL) {
+    return ERR_VAL;
+  }
+
+  if (conn->err != ERR_OK) {
+    return conn->err;
+  }
+
+  if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+    return (conn->err = ERR_MEM);
+  }
+
+  LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_send: sending %d bytes\n", buf->p->tot_len));
+  msg->type = API_MSG_SEND;
+  msg->msg.conn = conn;
+  msg->msg.msg.p = buf->p;
+  api_msg_post(msg);
+
+  sys_mbox_fetch(conn->mbox, NULL);
+  memp_free(MEMP_API_MSG, msg);
+  return conn->err;
+}
+
+err_t
+netconn_write(struct netconn *conn, void *dataptr, u16_t size, u8_t copy)
+{
+  struct api_msg *msg;
+  u16_t len;
+  
+  if (conn == NULL) {
+    return ERR_VAL;
+  }
+
+  if (conn->err != ERR_OK) {
+    return conn->err;
+  }
+  
+  if (conn->sem == SYS_SEM_NULL) {
+    conn->sem = sys_sem_new(0);
+    if (conn->sem == SYS_SEM_NULL) {
+      return ERR_MEM;
+    }
+  }
+
+  if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+    return (conn->err = ERR_MEM);
+  }
+  msg->type = API_MSG_WRITE;
+  msg->msg.conn = conn;
+        
+
+  conn->state = NETCONN_WRITE;
+  while (conn->err == ERR_OK && size > 0) {
+    msg->msg.msg.w.dataptr = dataptr;
+    msg->msg.msg.w.copy = copy;
+    
+    if (conn->type == NETCONN_TCP) {
+      if (tcp_sndbuf(conn->pcb.tcp) == 0) {
+  sys_sem_wait(conn->sem);
+  if (conn->err != ERR_OK) {
+    goto ret;
+  }
+      }
+      if (size > tcp_sndbuf(conn->pcb.tcp)) {
+  /* We cannot send more than one send buffer's worth of data at a
+     time. */
+  len = tcp_sndbuf(conn->pcb.tcp);
+      } else {
+  len = size;
+      }
+    } else {
+      len = size;
+    }
+    
+    LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_write: writing %d bytes (%d)\n", len, copy));
+    msg->msg.msg.w.len = len;
+    api_msg_post(msg);
+    sys_mbox_fetch(conn->mbox, NULL);    
+    if (conn->err == ERR_OK) {
+      dataptr = (void *)((u8_t *)dataptr + len);
+      size -= len;
+    } else if (conn->err == ERR_MEM) {
+      conn->err = ERR_OK;
+      sys_sem_wait(conn->sem);
+    } else {
+      goto ret;
+    }
+  }
+ ret:
+  memp_free(MEMP_API_MSG, msg);
+  conn->state = NETCONN_NONE;
+  if (conn->sem != SYS_SEM_NULL) {
+    sys_sem_free(conn->sem);
+    conn->sem = SYS_SEM_NULL;
+  }
+  
+  return conn->err;
+}
+
+err_t
+netconn_close(struct netconn *conn)
+{
+  struct api_msg *msg;
+
+  if (conn == NULL) {
+    return ERR_VAL;
+  }
+  if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
+    return (conn->err = ERR_MEM);
+  }
+
+  conn->state = NETCONN_CLOSE;
+ again:
+  msg->type = API_MSG_CLOSE;
+  msg->msg.conn = conn;
+  api_msg_post(msg);
+  sys_mbox_fetch(conn->mbox, NULL);
+  if (conn->err == ERR_MEM &&
+     conn->sem != SYS_SEM_NULL) {
+    sys_sem_wait(conn->sem);
+    goto again;
+  }
+  conn->state = NETCONN_NONE;
+  memp_free(MEMP_API_MSG, msg);
+  return conn->err;
+}
+
+err_t
+netconn_err(struct netconn *conn)
+{
+  return conn->err;
+}
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/api/api_msg.c b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/api/api_msg.c
new file mode 100644
index 000000000..9b9bf9c91
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/api/api_msg.c
@@ -0,0 +1,800 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+#include "lwip/arch.h"
+#include "lwip/api_msg.h"
+#include "lwip/memp.h"
+#include "lwip/sys.h"
+#include "lwip/tcpip.h"
+
+#if LWIP_RAW
+static u8_t
+recv_raw(void *arg, struct raw_pcb *pcb, struct pbuf *p,
+    struct ip_addr *addr)
+{
+  struct netbuf *buf;
+  struct netconn *conn;
+
+  conn = arg;
+  if (!conn) return 0;
+
+  if (conn->recvmbox != SYS_MBOX_NULL) {
+    if (!(buf = memp_malloc(MEMP_NETBUF))) {
+      return 0;
+    }
+    pbuf_ref(p);
+    buf->p = p;
+    buf->ptr = p;
+    buf->fromaddr = addr;
+    buf->fromport = pcb->protocol;
+
+    conn->recv_avail += p->tot_len;
+    /* Register event with callback */
+    if (conn->callback)
+        (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, p->tot_len);
+    sys_mbox_post(conn->recvmbox, buf);
+  }
+
+  return 0; /* do not eat the packet */
+}
+#endif
+#if LWIP_UDP
+static void
+recv_udp(void *arg, struct udp_pcb *pcb, struct pbuf *p,
+   struct ip_addr *addr, u16_t port)
+{
+  struct netbuf *buf;
+  struct netconn *conn;
+
+  conn = arg;
+  
+  if (conn == NULL) {
+    pbuf_free(p);
+    return;
+  }
+  if (conn->recvmbox != SYS_MBOX_NULL) {
+    buf = memp_malloc(MEMP_NETBUF);
+    if (buf == NULL) {
+      pbuf_free(p);
+      return;
+    } else {
+      buf->p = p;
+      buf->ptr = p;
+      buf->fromaddr = addr;
+      buf->fromport = port;
+    }
+
+  conn->recv_avail += p->tot_len;
+    /* Register event with callback */
+    if (conn->callback)
+        (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, p->tot_len);
+    sys_mbox_post(conn->recvmbox, buf);
+  }
+}
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+
+static err_t
+recv_tcp(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err)
+{
+  struct netconn *conn;
+  u16_t len;
+  
+  conn = arg;
+
+  if (conn == NULL) {
+    pbuf_free(p);
+    return ERR_VAL;
+  }
+
+  if (conn->recvmbox != SYS_MBOX_NULL) {
+        
+    conn->err = err;
+    if (p != NULL) {
+        len = p->tot_len;
+        conn->recv_avail += len;
+    }
+    else
+        len = 0;
+    /* Register event with callback */
+    if (conn->callback)
+        (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, len);
+    sys_mbox_post(conn->recvmbox, p);
+  }  
+  return ERR_OK;
+}
+
+
+static err_t
+poll_tcp(void *arg, struct tcp_pcb *pcb)
+{
+  struct netconn *conn;
+
+  conn = arg;
+  if (conn != NULL &&
+     (conn->state == NETCONN_WRITE || conn->state == NETCONN_CLOSE) &&
+     conn->sem != SYS_SEM_NULL) {
+    sys_sem_signal(conn->sem);
+  }
+  return ERR_OK;
+}
+
+static err_t
+sent_tcp(void *arg, struct tcp_pcb *pcb, u16_t len)
+{
+  struct netconn *conn;
+
+  conn = arg;
+  if (conn != NULL && conn->sem != SYS_SEM_NULL) {
+    sys_sem_signal(conn->sem);
+  }
+
+  if (conn && conn->callback)
+      if (tcp_sndbuf(conn->pcb.tcp) > TCP_SNDLOWAT)
+          (*conn->callback)(conn, NETCONN_EVT_SENDPLUS, len);
+  
+  return ERR_OK;
+}
+
+static void
+err_tcp(void *arg, err_t err)
+{
+  struct netconn *conn;
+
+  conn = arg;
+
+  conn->pcb.tcp = NULL;
+
+  
+  conn->err = err;
+  if (conn->recvmbox != SYS_MBOX_NULL) {
+    /* Register event with callback */
+    if (conn->callback)
+      (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, 0);
+    sys_mbox_post(conn->recvmbox, NULL);
+  }
+  if (conn->mbox != SYS_MBOX_NULL) {
+    sys_mbox_post(conn->mbox, NULL);
+  }
+  if (conn->acceptmbox != SYS_MBOX_NULL) {
+     /* Register event with callback */
+    if (conn->callback)
+      (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, 0);
+    sys_mbox_post(conn->acceptmbox, NULL);
+  }
+  if (conn->sem != SYS_SEM_NULL) {
+    sys_sem_signal(conn->sem);
+  }
+}
+
+static void
+setup_tcp(struct netconn *conn)
+{
+  struct tcp_pcb *pcb;
+  
+  pcb = conn->pcb.tcp;
+  tcp_arg(pcb, conn);
+  tcp_recv(pcb, recv_tcp);
+  tcp_sent(pcb, sent_tcp);
+  tcp_poll(pcb, poll_tcp, 4);
+  tcp_err(pcb, err_tcp);
+}
+
+static err_t
+accept_function(void *arg, struct tcp_pcb *newpcb, err_t err)
+{
+  sys_mbox_t mbox;
+  struct netconn *newconn;
+  struct netconn *conn;
+  
+#if API_MSG_DEBUG
+#if TCP_DEBUG
+  tcp_debug_print_state(newpcb->state);
+#endif /* TCP_DEBUG */
+#endif /* API_MSG_DEBUG */
+  conn = (struct netconn *)arg;
+  mbox = conn->acceptmbox;
+  newconn = memp_malloc(MEMP_NETCONN);
+  if (newconn == NULL) {
+    return ERR_MEM;
+  }
+  newconn->type = NETCONN_TCP;
+  newconn->pcb.tcp = newpcb;
+  setup_tcp(newconn);
+  newconn->recvmbox = sys_mbox_new();
+  if (newconn->recvmbox == SYS_MBOX_NULL) {
+    memp_free(MEMP_NETCONN, newconn);
+    return ERR_MEM;
+  }
+  newconn->mbox = sys_mbox_new();
+  if (newconn->mbox == SYS_MBOX_NULL) {
+    sys_mbox_free(newconn->recvmbox);
+    memp_free(MEMP_NETCONN, newconn);
+    return ERR_MEM;
+  }
+  newconn->sem = sys_sem_new(0);
+  if (newconn->sem == SYS_SEM_NULL) {
+    sys_mbox_free(newconn->recvmbox);
+    sys_mbox_free(newconn->mbox);
+    memp_free(MEMP_NETCONN, newconn);
+    return ERR_MEM;
+  }
+  newconn->acceptmbox = SYS_MBOX_NULL;
+  newconn->err = err;
+  /* Register event with callback */
+  if (conn->callback)
+  {
+    (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, 0);
+    /* We have to set the callback here even though
+     * the new socket is unknown. Mark the socket as -1. */
+    newconn->callback = conn->callback;
+    newconn->socket = -1;
+  }
+  
+  sys_mbox_post(mbox, newconn);
+  return ERR_OK;
+}
+#endif /* LWIP_TCP */
+
+static void
+do_newconn(struct api_msg_msg *msg)
+{
+   if(msg->conn->pcb.tcp != NULL) {
+   /* This "new" connection already has a PCB allocated. */
+   /* Is this an error condition? Should it be deleted? 
+      We currently just are happy and return. */
+     sys_mbox_post(msg->conn->mbox, NULL);
+     return;
+   }
+
+   msg->conn->err = ERR_OK;
+
+   /* Allocate a PCB for this connection */
+   switch(msg->conn->type) {
+#if LWIP_RAW
+   case NETCONN_RAW:
+      msg->conn->pcb.raw = raw_new(msg->msg.bc.port); /* misusing the port field */
+      raw_recv(msg->conn->pcb.raw, recv_raw, msg->conn);
+     break;
+#endif
+#if LWIP_UDP
+   case NETCONN_UDPLITE:
+      msg->conn->pcb.udp = udp_new();
+      if(msg->conn->pcb.udp == NULL) {
+         msg->conn->err = ERR_MEM;
+         break;
+      }
+      udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_UDPLITE);
+      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
+      break;
+   case NETCONN_UDPNOCHKSUM:
+      msg->conn->pcb.udp = udp_new();
+      if(msg->conn->pcb.udp == NULL) {
+         msg->conn->err = ERR_MEM;
+         break;
+      }
+      udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_NOCHKSUM);
+      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
+      break;
+   case NETCONN_UDP:
+      msg->conn->pcb.udp = udp_new();
+      if(msg->conn->pcb.udp == NULL) {
+         msg->conn->err = ERR_MEM;
+         break;
+      }
+      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
+      break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+   case NETCONN_TCP:
+      msg->conn->pcb.tcp = tcp_new();
+      if(msg->conn->pcb.tcp == NULL) {
+         msg->conn->err = ERR_MEM;
+         break;
+      }
+      setup_tcp(msg->conn);
+      break;
+#endif
+   }
+   
+  
+  sys_mbox_post(msg->conn->mbox, NULL);
+}
+
+
+static void
+do_delconn(struct api_msg_msg *msg)
+{
+  if (msg->conn->pcb.tcp != NULL) {
+    switch (msg->conn->type) {
+#if LWIP_RAW
+    case NETCONN_RAW:
+      raw_remove(msg->conn->pcb.raw);
+      break;
+#endif
+#if LWIP_UDP
+    case NETCONN_UDPLITE:
+      /* FALLTHROUGH */
+    case NETCONN_UDPNOCHKSUM:
+      /* FALLTHROUGH */
+    case NETCONN_UDP:
+      msg->conn->pcb.udp->recv_arg = NULL;
+      udp_remove(msg->conn->pcb.udp);
+      break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP      
+    case NETCONN_TCP:
+      if (msg->conn->pcb.tcp->state == LISTEN) {
+  tcp_arg(msg->conn->pcb.tcp, NULL);
+  tcp_accept(msg->conn->pcb.tcp, NULL);  
+  tcp_close(msg->conn->pcb.tcp);
+      } else {
+  tcp_arg(msg->conn->pcb.tcp, NULL);
+  tcp_sent(msg->conn->pcb.tcp, NULL);
+  tcp_recv(msg->conn->pcb.tcp, NULL);  
+  tcp_poll(msg->conn->pcb.tcp, NULL, 0);
+  tcp_err(msg->conn->pcb.tcp, NULL);
+  if (tcp_close(msg->conn->pcb.tcp) != ERR_OK) {
+    tcp_abort(msg->conn->pcb.tcp);
+  }
+      }
+#endif
+    default:  
+    break;
+    }
+  }
+  /* Trigger select() in socket layer */
+  if (msg->conn->callback)
+  {
+      (*msg->conn->callback)(msg->conn, NETCONN_EVT_RCVPLUS, 0);
+      (*msg->conn->callback)(msg->conn, NETCONN_EVT_SENDPLUS, 0);
+  }
+  
+  if (msg->conn->mbox != SYS_MBOX_NULL) {
+    sys_mbox_post(msg->conn->mbox, NULL);
+  }
+}
+
+static void
+do_bind(struct api_msg_msg *msg)
+{
+  if (msg->conn->pcb.tcp == NULL) {
+    switch (msg->conn->type) {
+#if LWIP_RAW
+    case NETCONN_RAW:
+      msg->conn->pcb.raw = raw_new(msg->msg.bc.port); /* misusing the port field as protocol */
+      raw_recv(msg->conn->pcb.raw, recv_raw, msg->conn);
+      break;
+#endif
+#if LWIP_UDP
+    case NETCONN_UDPLITE:
+      msg->conn->pcb.udp = udp_new();
+      udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_UDPLITE);
+      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
+      break;
+    case NETCONN_UDPNOCHKSUM:
+      msg->conn->pcb.udp = udp_new();
+      udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_NOCHKSUM);
+      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
+      break;
+    case NETCONN_UDP:
+      msg->conn->pcb.udp = udp_new();
+      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
+      break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP      
+    case NETCONN_TCP:
+      msg->conn->pcb.tcp = tcp_new();
+      setup_tcp(msg->conn);
+#endif /* LWIP_TCP */
+    default:  
+    break;
+    }
+  }
+  switch (msg->conn->type) {
+#if LWIP_RAW
+  case NETCONN_RAW:
+    msg->conn->err = raw_bind(msg->conn->pcb.raw,msg->msg.bc.ipaddr);
+    break;
+#endif
+#if LWIP_UDP
+  case NETCONN_UDPLITE:
+    /* FALLTHROUGH */
+  case NETCONN_UDPNOCHKSUM:
+    /* FALLTHROUGH */
+  case NETCONN_UDP:
+    msg->conn->err = udp_bind(msg->conn->pcb.udp, msg->msg.bc.ipaddr, msg->msg.bc.port);
+    break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+  case NETCONN_TCP:
+    msg->conn->err = tcp_bind(msg->conn->pcb.tcp,
+            msg->msg.bc.ipaddr, msg->msg.bc.port);
+#endif /* LWIP_TCP */
+  default:
+    break;
+  }
+  sys_mbox_post(msg->conn->mbox, NULL);
+}
+#if LWIP_TCP
+
+static err_t
+do_connected(void *arg, struct tcp_pcb *pcb, err_t err)
+{
+  struct netconn *conn;
+
+  conn = arg;
+
+  if (conn == NULL) {
+    return ERR_VAL;
+  }
+  
+  conn->err = err;
+  if (conn->type == NETCONN_TCP && err == ERR_OK) {
+    setup_tcp(conn);
+  }    
+  sys_mbox_post(conn->mbox, NULL);
+  return ERR_OK;
+}
+#endif  
+
+static void
+do_connect(struct api_msg_msg *msg)
+{
+  if (msg->conn->pcb.tcp == NULL) {
+    switch (msg->conn->type) {
+#if LWIP_RAW
+    case NETCONN_RAW:
+      msg->conn->pcb.raw = raw_new(msg->msg.bc.port); /* misusing the port field as protocol */
+      raw_recv(msg->conn->pcb.raw, recv_raw, msg->conn);
+      break;
+#endif
+#if LWIP_UDP
+    case NETCONN_UDPLITE:
+      msg->conn->pcb.udp = udp_new();
+      if (msg->conn->pcb.udp == NULL) {
+  msg->conn->err = ERR_MEM;
+  sys_mbox_post(msg->conn->mbox, NULL);
+  return;
+      }
+      udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_UDPLITE);
+      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
+      break;
+    case NETCONN_UDPNOCHKSUM:
+      msg->conn->pcb.udp = udp_new();
+      if (msg->conn->pcb.udp == NULL) {
+  msg->conn->err = ERR_MEM;
+  sys_mbox_post(msg->conn->mbox, NULL);
+  return;
+      }
+      udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_NOCHKSUM);
+      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
+      break;
+    case NETCONN_UDP:
+      msg->conn->pcb.udp = udp_new();
+      if (msg->conn->pcb.udp == NULL) {
+  msg->conn->err = ERR_MEM;
+  sys_mbox_post(msg->conn->mbox, NULL);
+  return;
+      }
+      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
+      break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP      
+    case NETCONN_TCP:
+      msg->conn->pcb.tcp = tcp_new();      
+      if (msg->conn->pcb.tcp == NULL) {
+  msg->conn->err = ERR_MEM;
+  sys_mbox_post(msg->conn->mbox, NULL);
+  return;
+      }
+#endif
+    default:
+      break;
+    }
+  }
+  switch (msg->conn->type) {
+#if LWIP_RAW
+  case NETCONN_RAW:
+    raw_connect(msg->conn->pcb.raw, msg->msg.bc.ipaddr);
+    sys_mbox_post(msg->conn->mbox, NULL);
+    break;
+#endif
+#if LWIP_UDP
+  case NETCONN_UDPLITE:
+    /* FALLTHROUGH */
+  case NETCONN_UDPNOCHKSUM:
+    /* FALLTHROUGH */
+  case NETCONN_UDP:
+    udp_connect(msg->conn->pcb.udp, msg->msg.bc.ipaddr, msg->msg.bc.port);
+    sys_mbox_post(msg->conn->mbox, NULL);
+    break;
+#endif 
+#if LWIP_TCP      
+  case NETCONN_TCP:
+    /*    tcp_arg(msg->conn->pcb.tcp, msg->conn);*/
+    setup_tcp(msg->conn);
+    tcp_connect(msg->conn->pcb.tcp, msg->msg.bc.ipaddr, msg->msg.bc.port,
+    do_connected);
+    /*tcp_output(msg->conn->pcb.tcp);*/
+#endif
+
+  default:
+    break;
+  }
+}
+
+static void
+do_disconnect(struct api_msg_msg *msg)
+{
+
+  switch (msg->conn->type) {
+#if LWIP_RAW
+  case NETCONN_RAW:
+    /* Do nothing as connecting is only a helper for upper lwip layers */
+    break;
+#endif
+#if LWIP_UDP
+  case NETCONN_UDPLITE:
+    /* FALLTHROUGH */
+  case NETCONN_UDPNOCHKSUM:
+    /* FALLTHROUGH */
+  case NETCONN_UDP:
+    udp_disconnect(msg->conn->pcb.udp);
+    break;
+#endif 
+  case NETCONN_TCP:
+    break;
+  }
+  sys_mbox_post(msg->conn->mbox, NULL);
+}
+
+
+static void
+do_listen(struct api_msg_msg *msg)
+{
+  if (msg->conn->pcb.tcp != NULL) {
+    switch (msg->conn->type) {
+#if LWIP_RAW
+    case NETCONN_RAW:
+      LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: listen RAW: cannot listen for RAW.\n"));
+      break;
+#endif
+#if LWIP_UDP
+    case NETCONN_UDPLITE:
+      /* FALLTHROUGH */
+    case NETCONN_UDPNOCHKSUM:
+      /* FALLTHROUGH */
+    case NETCONN_UDP:
+      LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: listen UDP: cannot listen for UDP.\n"));
+      break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP      
+    case NETCONN_TCP:
+      msg->conn->pcb.tcp = tcp_listen(msg->conn->pcb.tcp);
+      if (msg->conn->pcb.tcp == NULL) {
+  msg->conn->err = ERR_MEM;
+      } else {
+  if (msg->conn->acceptmbox == SYS_MBOX_NULL) {
+    msg->conn->acceptmbox = sys_mbox_new();
+    if (msg->conn->acceptmbox == SYS_MBOX_NULL) {
+      msg->conn->err = ERR_MEM;
+      break;
+    }
+  }
+  tcp_arg(msg->conn->pcb.tcp, msg->conn);
+  tcp_accept(msg->conn->pcb.tcp, accept_function);
+      }
+#endif
+    default:
+      break;
+    }
+  }
+  sys_mbox_post(msg->conn->mbox, NULL);
+}
+
+static void
+do_accept(struct api_msg_msg *msg)
+{
+  if (msg->conn->pcb.tcp != NULL) {
+    switch (msg->conn->type) {
+#if LWIP_RAW
+    case NETCONN_RAW:
+      LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: accept RAW: cannot accept for RAW.\n"));
+      break;
+#endif
+#if LWIP_UDP
+    case NETCONN_UDPLITE:
+      /* FALLTHROUGH */
+    case NETCONN_UDPNOCHKSUM:
+      /* FALLTHROUGH */
+    case NETCONN_UDP:    
+      LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: accept UDP: cannot accept for UDP.\n"));
+      break;
+#endif /* LWIP_UDP */
+    case NETCONN_TCP:
+      break;
+    }
+  }
+}
+
+static void
+do_send(struct api_msg_msg *msg)
+{
+  if (msg->conn->pcb.tcp != NULL) {
+    switch (msg->conn->type) {
+#if LWIP_RAW
+    case NETCONN_RAW:
+      raw_send(msg->conn->pcb.raw, msg->msg.p);
+      break;
+#endif
+#if LWIP_UDP
+    case NETCONN_UDPLITE:
+      /* FALLTHROUGH */
+    case NETCONN_UDPNOCHKSUM:
+      /* FALLTHROUGH */
+    case NETCONN_UDP:
+      udp_send(msg->conn->pcb.udp, msg->msg.p);
+      break;
+#endif /* LWIP_UDP */
+    case NETCONN_TCP:
+      break;
+    }
+  }
+  sys_mbox_post(msg->conn->mbox, NULL);
+}
+
+static void
+do_recv(struct api_msg_msg *msg)
+{
+#if LWIP_TCP
+  if (msg->conn->pcb.tcp != NULL) {
+    if (msg->conn->type == NETCONN_TCP) {
+      tcp_recved(msg->conn->pcb.tcp, msg->msg.len);
+    }
+  }
+#endif  
+  sys_mbox_post(msg->conn->mbox, NULL);
+}
+
+static void
+do_write(struct api_msg_msg *msg)
+{
+#if LWIP_TCP  
+  err_t err;
+#endif  
+  if (msg->conn->pcb.tcp != NULL) {
+    switch (msg->conn->type) {
+#if LWIP_RAW
+    case NETCONN_RAW:
+      msg->conn->err = ERR_VAL;
+      break;
+#endif
+#if LWIP_UDP 
+    case NETCONN_UDPLITE:
+      /* FALLTHROUGH */
+    case NETCONN_UDPNOCHKSUM:
+      /* FALLTHROUGH */
+    case NETCONN_UDP:
+      msg->conn->err = ERR_VAL;
+      break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP 
+    case NETCONN_TCP:      
+      err = tcp_write(msg->conn->pcb.tcp, msg->msg.w.dataptr,
+                      msg->msg.w.len, msg->msg.w.copy);
+      /* This is the Nagle algorithm: inhibit the sending of new TCP
+   segments when new outgoing data arrives from the user if any
+   previously transmitted data on the connection remains
+   unacknowledged. */
+      if(err == ERR_OK && (msg->conn->pcb.tcp->unacked == NULL || (msg->conn->pcb.tcp->flags & TF_NODELAY)) ) {
+  tcp_output(msg->conn->pcb.tcp);
+      }
+      msg->conn->err = err;
+      if (msg->conn->callback)
+          if (err == ERR_OK)
+          {
+              if (tcp_sndbuf(msg->conn->pcb.tcp) <= TCP_SNDLOWAT)
+                  (*msg->conn->callback)(msg->conn, NETCONN_EVT_SENDMINUS, msg->msg.w.len);
+          }
+#endif
+    default:
+      break;
+    }
+  }
+  sys_mbox_post(msg->conn->mbox, NULL);
+}
+
+static void
+do_close(struct api_msg_msg *msg)
+{
+  err_t err;
+
+  err = ERR_OK;
+
+  if (msg->conn->pcb.tcp != NULL) {
+    switch (msg->conn->type) {
+#if LWIP_RAW
+    case NETCONN_RAW:
+      break;
+#endif
+#if LWIP_UDP
+    case NETCONN_UDPLITE:
+      /* FALLTHROUGH */
+    case NETCONN_UDPNOCHKSUM:
+      /* FALLTHROUGH */
+    case NETCONN_UDP:
+      break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+    case NETCONN_TCP:
+      if (msg->conn->pcb.tcp->state == LISTEN) {
+  err = tcp_close(msg->conn->pcb.tcp);
+      }
+      msg->conn->err = err;      
+#endif
+    default:      
+      break;
+    }
+  }
+  sys_mbox_post(msg->conn->mbox, NULL);
+}
+
+typedef void (* api_msg_decode)(struct api_msg_msg *msg);
+static api_msg_decode decode[API_MSG_MAX] = {
+  do_newconn,
+  do_delconn,
+  do_bind,
+  do_connect,
+  do_disconnect,
+  do_listen,
+  do_accept,
+  do_send,
+  do_recv,
+  do_write,
+  do_close
+  };
+void
+api_msg_input(struct api_msg *msg)
+{  
+  decode[msg->type](&(msg->msg));
+}
+
+void
+api_msg_post(struct api_msg *msg)
+{
+  tcpip_apimsg(msg);
+}
+
+
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/api/err.c b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/api/err.c
new file mode 100644
index 000000000..cc6367814
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/api/err.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/err.h"
+
+#ifdef LWIP_DEBUG
+
+static char *err_strerr[] = {"Ok.",
+           "Out of memory error.",
+           "Buffer error.",
+           "Connection aborted.",
+           "Connection reset.",
+           "Connection closed.",
+           "Not connected.",
+           "Illegal value.",
+           "Illegal argument.",
+           "Routing problem.",
+           "Address in use."
+};
+
+
+char *
+lwip_strerr(err_t err)
+{
+  return err_strerr[-err];
+
+}
+
+
+#endif /* LWIP_DEBUG */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/api/sockets.c b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/api/sockets.c
new file mode 100644
index 000000000..26e6d8630
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/api/sockets.c
@@ -0,0 +1,1362 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ * Improved by Marc Boucher  and David Haas 
+ *
+ */
+
+#include 
+#include 
+
+#include "lwip/opt.h"
+#include "lwip/api.h"
+#include "lwip/arch.h"
+#include "lwip/sys.h"
+
+#include "lwip/sockets.h"
+
+#define NUM_SOCKETS MEMP_NUM_NETCONN
+
+struct lwip_socket {
+  struct netconn *conn;
+  struct netbuf *lastdata;
+  u16_t lastoffset;
+  u16_t rcvevent;
+  u16_t sendevent;
+  u16_t  flags;
+  int err;
+};
+
+struct lwip_select_cb
+{
+    struct lwip_select_cb *next;
+    fd_set *readset;
+    fd_set *writeset;
+    fd_set *exceptset;
+    int sem_signalled;
+    sys_sem_t sem;
+};
+
+static struct lwip_socket sockets[NUM_SOCKETS];
+static struct lwip_select_cb *select_cb_list = 0;
+
+static sys_sem_t socksem = 0;
+static sys_sem_t selectsem = 0;
+
+static void
+event_callback(struct netconn *conn, enum netconn_evt evt, u16_t len);
+
+static int err_to_errno_table[11] = {
+    0,      /* ERR_OK    0      No error, everything OK. */
+    ENOMEM,    /* ERR_MEM  -1      Out of memory error.     */
+    ENOBUFS,    /* ERR_BUF  -2      Buffer error.            */
+    ECONNABORTED,  /* ERR_ABRT -3      Connection aborted.      */
+    ECONNRESET,    /* ERR_RST  -4      Connection reset.        */
+    ESHUTDOWN,    /* ERR_CLSD -5      Connection closed.       */
+    ENOTCONN,    /* ERR_CONN -6      Not connected.           */
+    EINVAL,    /* ERR_VAL  -7      Illegal value.           */
+    EIO,    /* ERR_ARG  -8      Illegal argument.        */
+    EHOSTUNREACH,  /* ERR_RTE  -9      Routing problem.         */
+    EADDRINUSE    /* ERR_USE  -10     Address in use.          */
+};
+
+#define ERR_TO_ERRNO_TABLE_SIZE \
+  (sizeof(err_to_errno_table)/sizeof(err_to_errno_table[0]))
+
+#define err_to_errno(err) \
+  (-(err) >= 0 && -(err) < ERR_TO_ERRNO_TABLE_SIZE ? \
+    err_to_errno_table[-(err)] : EIO)
+
+#ifdef ERRNO
+#define set_errno(err) errno = (err)
+#else
+#define set_errno(err)
+#endif
+
+#define sock_set_errno(sk, e) do { \
+      sk->err = (e); \
+      set_errno(sk->err); \
+} while (0)
+
+
+static struct lwip_socket *
+get_socket(int s)
+{
+  struct lwip_socket *sock;
+
+  if ((s < 0) || (s > NUM_SOCKETS)) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("get_socket(%d): invalid\n", s));
+    set_errno(EBADF);
+    return NULL;
+  }
+
+  sock = &sockets[s];
+
+  if (!sock->conn) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("get_socket(%d): not active\n", s));
+    set_errno(EBADF);
+    return NULL;
+  }
+
+  return sock;
+}
+
+static int
+alloc_socket(struct netconn *newconn)
+{
+  int i;
+
+  if (!socksem)
+      socksem = sys_sem_new(1);
+
+  /* Protect socket array */
+  sys_sem_wait(socksem);
+
+  /* allocate a new socket identifier */
+  for(i = 0; i < NUM_SOCKETS; ++i) {
+    if (!sockets[i].conn) {
+      sockets[i].conn = newconn;
+      sockets[i].lastdata = NULL;
+      sockets[i].lastoffset = 0;
+      sockets[i].rcvevent = 0;
+      sockets[i].sendevent = 1; /* TCP send buf is empty */
+      sockets[i].flags = 0;
+      sockets[i].err = 0;
+      sys_sem_signal(socksem);
+      return i;
+    }
+  }
+  sys_sem_signal(socksem);
+  return -1;
+}
+
+int
+lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen)
+{
+  struct lwip_socket *sock;
+  struct netconn *newconn;
+  struct ip_addr naddr;
+  u16_t port;
+  int newsock;
+  struct sockaddr_in sin;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d)...\n", s));
+  sock = get_socket(s);
+  if (!sock) {
+    set_errno(EBADF);
+    return -1;
+  }
+
+  newconn = netconn_accept(sock->conn);
+
+  /* get the IP address and port of the remote host */
+  netconn_peer(newconn, &naddr, &port);
+
+  memset(&sin, 0, sizeof(sin));
+  sin.sin_len = sizeof(sin);
+  sin.sin_family = AF_INET;
+  sin.sin_port = htons(port);
+  sin.sin_addr.s_addr = naddr.addr;
+
+  if (*addrlen > sizeof(sin))
+      *addrlen = sizeof(sin);
+
+  memcpy(addr, &sin, *addrlen);
+
+  newsock = alloc_socket(newconn);
+  if (newsock == -1) {
+    netconn_delete(newconn);
+  sock_set_errno(sock, ENOBUFS);
+  return -1;
+  }
+  newconn->callback = event_callback;
+  sock = get_socket(newsock);
+
+  sys_sem_wait(socksem);
+  sock->rcvevent += -1 - newconn->socket;
+  newconn->socket = newsock;
+  sys_sem_signal(socksem);
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d) returning new sock=%d addr=", s, newsock));
+  ip_addr_debug_print(SOCKETS_DEBUG, &naddr);
+  LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u\n", port));
+
+  sock_set_errno(sock, 0);
+  return newsock;
+}
+
+int
+lwip_bind(int s, struct sockaddr *name, socklen_t namelen)
+{
+  struct lwip_socket *sock;
+  struct ip_addr local_addr;
+  u16_t local_port;
+  err_t err;
+
+  sock = get_socket(s);
+  if (!sock) {
+    set_errno(EBADF);
+    return -1;
+  }
+
+  local_addr.addr = ((struct sockaddr_in *)name)->sin_addr.s_addr;
+  local_port = ((struct sockaddr_in *)name)->sin_port;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d, addr=", s));
+  ip_addr_debug_print(SOCKETS_DEBUG, &local_addr);
+  LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u)\n", ntohs(local_port)));
+
+  err = netconn_bind(sock->conn, &local_addr, ntohs(local_port));
+
+  if (err != ERR_OK) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d) failed, err=%d\n", s, err));
+    sock_set_errno(sock, err_to_errno(err));
+    return -1;
+  }
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d) succeeded\n", s));
+  sock_set_errno(sock, 0);
+  return 0;
+}
+
+int
+lwip_close(int s)
+{
+  struct lwip_socket *sock;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_close(%d)\n", s));
+  if (!socksem)
+      socksem = sys_sem_new(1);
+
+  /* We cannot allow multiple closes of the same socket. */
+  sys_sem_wait(socksem);
+
+  sock = get_socket(s);
+  if (!sock) {
+      sys_sem_signal(socksem);
+      set_errno(EBADF);
+      return -1;
+  }
+
+  netconn_delete(sock->conn);
+  if (sock->lastdata) {
+    netbuf_delete(sock->lastdata);
+  }
+  sock->lastdata = NULL;
+  sock->lastoffset = 0;
+  sock->conn = NULL;
+  sys_sem_signal(socksem);
+  sock_set_errno(sock, 0);
+  return 0;
+}
+
+int
+lwip_connect(int s, struct sockaddr *name, socklen_t namelen)
+{
+  struct lwip_socket *sock;
+  err_t err;
+
+  sock = get_socket(s);
+  if (!sock) {
+    set_errno(EBADF);
+    return -1;
+  }
+
+  if (((struct sockaddr_in *)name)->sin_family == AF_UNSPEC) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d, AF_UNSPEC)\n", s));
+    err = netconn_disconnect(sock->conn);
+  } else {
+    struct ip_addr remote_addr;
+    u16_t remote_port;
+
+    remote_addr.addr = ((struct sockaddr_in *)name)->sin_addr.s_addr;
+    remote_port = ((struct sockaddr_in *)name)->sin_port;
+
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d, addr=", s));
+    ip_addr_debug_print(SOCKETS_DEBUG, &remote_addr);
+    LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u)\n", ntohs(remote_port)));
+
+    err = netconn_connect(sock->conn, &remote_addr, ntohs(remote_port));
+   }
+
+  if (err != ERR_OK) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d) failed, err=%d\n", s, err));
+    sock_set_errno(sock, err_to_errno(err));
+    return -1;
+  }
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d) succeeded\n", s));
+  sock_set_errno(sock, 0);
+  return 0;
+}
+
+int
+lwip_listen(int s, int backlog)
+{
+  struct lwip_socket *sock;
+  err_t err;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_listen(%d, backlog=%d)\n", s, backlog));
+  sock = get_socket(s);
+  if (!sock) {
+    set_errno(EBADF);
+    return -1;
+  }
+
+  err = netconn_listen(sock->conn);
+
+  if (err != ERR_OK) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_listen(%d) failed, err=%d\n", s, err));
+    sock_set_errno(sock, err_to_errno(err));
+    return -1;
+  }
+
+  sock_set_errno(sock, 0);
+  return 0;
+}
+
+int
+lwip_recvfrom(int s, void *mem, int len, unsigned int flags,
+        struct sockaddr *from, socklen_t *fromlen)
+{
+  struct lwip_socket *sock;
+  struct netbuf *buf;
+  u16_t buflen, copylen;
+  struct ip_addr *addr;
+  u16_t port;
+
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d, %p, %d, 0x%x, ..)\n", s, mem, len, flags));
+  sock = get_socket(s);
+  if (!sock) {
+    set_errno(EBADF);
+    return -1;
+  }
+
+  /* Check if there is data left from the last recv operation. */
+  if (sock->lastdata) {
+    buf = sock->lastdata;
+  } else {
+    /* If this is non-blocking call, then check first */
+    if (((flags & MSG_DONTWAIT) || (sock->flags & O_NONBLOCK))
+  && !sock->rcvevent)
+    {
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): returning EWOULDBLOCK\n", s));
+      sock_set_errno(sock, EWOULDBLOCK);
+      return -1;
+    }
+
+    /* No data was left from the previous operation, so we try to get
+       some from the network. */
+    buf = netconn_recv(sock->conn);
+
+    if (!buf) {
+      /* We should really do some error checking here. */
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): buf == NULL!\n", s));
+      sock_set_errno(sock, 0);
+      return 0;
+    }
+  }
+
+  buflen = netbuf_len(buf);
+
+  buflen -= sock->lastoffset;
+
+  if (len > buflen) {
+    copylen = buflen;
+  } else {
+    copylen = len;
+  }
+
+  /* copy the contents of the received buffer into
+     the supplied memory pointer mem */
+  netbuf_copy_partial(buf, mem, copylen, sock->lastoffset);
+
+  /* Check to see from where the data was. */
+  if (from && fromlen) {
+    struct sockaddr_in sin;
+
+    addr = netbuf_fromaddr(buf);
+    port = netbuf_fromport(buf);
+
+    memset(&sin, 0, sizeof(sin));
+    sin.sin_len = sizeof(sin);
+    sin.sin_family = AF_INET;
+    sin.sin_port = htons(port);
+    sin.sin_addr.s_addr = addr->addr;
+
+    if (*fromlen > sizeof(sin))
+      *fromlen = sizeof(sin);
+
+    memcpy(from, &sin, *fromlen);
+
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): addr=", s));
+    ip_addr_debug_print(SOCKETS_DEBUG, addr);
+    LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u len=%u\n", port, copylen));
+  } else {
+#if SOCKETS_DEBUG
+    addr = netbuf_fromaddr(buf);
+    port = netbuf_fromport(buf);
+
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): addr=", s));
+    ip_addr_debug_print(SOCKETS_DEBUG, addr);
+    LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u len=%u\n", port, copylen));
+#endif
+
+  }
+
+  /* If this is a TCP socket, check if there is data left in the
+     buffer. If so, it should be saved in the sock structure for next
+     time around. */
+  if (netconn_type(sock->conn) == NETCONN_TCP && buflen - copylen > 0) {
+    sock->lastdata = buf;
+    sock->lastoffset += copylen;
+  } else {
+    sock->lastdata = NULL;
+    sock->lastoffset = 0;
+    netbuf_delete(buf);
+  }
+
+
+  sock_set_errno(sock, 0);
+  return copylen;
+}
+
+int
+lwip_read(int s, void *mem, int len)
+{
+  return lwip_recvfrom(s, mem, len, 0, NULL, NULL);
+}
+
+int
+lwip_recv(int s, void *mem, int len, unsigned int flags)
+{
+  return lwip_recvfrom(s, mem, len, flags, NULL, NULL);
+}
+
+int
+lwip_send(int s, void *data, int size, unsigned int flags)
+{
+  struct lwip_socket *sock;
+  struct netbuf *buf;
+  err_t err;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d, data=%p, size=%d, flags=0x%x)\n", s, data, size, flags));
+
+  sock = get_socket(s);
+  if (!sock) {
+    set_errno(EBADF);
+    return -1;
+  }
+
+  switch (netconn_type(sock->conn)) {
+  case NETCONN_RAW:
+  case NETCONN_UDP:
+  case NETCONN_UDPLITE:
+  case NETCONN_UDPNOCHKSUM:
+    /* create a buffer */
+    buf = netbuf_new();
+
+    if (!buf) {
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d) ENOBUFS\n", s));
+      sock_set_errno(sock, ENOBUFS);
+      return -1;
+    }
+
+    /* make the buffer point to the data that should
+       be sent */
+    netbuf_ref(buf, data, size);
+
+    /* send the data */
+    err = netconn_send(sock->conn, buf);
+
+    /* deallocated the buffer */
+    netbuf_delete(buf);
+    break;
+  case NETCONN_TCP:
+    err = netconn_write(sock->conn, data, size, NETCONN_COPY);
+    break;
+  default:
+    err = ERR_ARG;
+    break;
+  }
+  if (err != ERR_OK) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d) err=%d\n", s, err));
+    sock_set_errno(sock, err_to_errno(err));
+    return -1;
+  }
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d) ok size=%d\n", s, size));
+  sock_set_errno(sock, 0);
+  return size;
+}
+
+int
+lwip_sendto(int s, void *data, int size, unsigned int flags,
+       struct sockaddr *to, socklen_t tolen)
+{
+  struct lwip_socket *sock;
+  struct ip_addr remote_addr, addr;
+  u16_t remote_port, port;
+  int ret,connected;
+
+  sock = get_socket(s);
+  if (!sock) {
+    set_errno(EBADF);
+    return -1;
+  }
+
+  /* get the peer if currently connected */
+  connected = (netconn_peer(sock->conn, &addr, &port) == ERR_OK);
+
+  remote_addr.addr = ((struct sockaddr_in *)to)->sin_addr.s_addr;
+  remote_port = ((struct sockaddr_in *)to)->sin_port;
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_sendto(%d, data=%p, size=%d, flags=0x%x to=", s, data, size, flags));
+  ip_addr_debug_print(SOCKETS_DEBUG, &remote_addr);
+  LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u\n", ntohs(remote_port)));
+
+  netconn_connect(sock->conn, &remote_addr, ntohs(remote_port));
+
+  ret = lwip_send(s, data, size, flags);
+
+  /* reset the remote address and port number
+     of the connection */
+  if (connected)
+    netconn_connect(sock->conn, &addr, port);
+  else
+  netconn_disconnect(sock->conn);
+  return ret;
+}
+
+int
+lwip_socket(int domain, int type, int protocol)
+{
+  struct netconn *conn;
+  int i;
+
+  /* create a netconn */
+  switch (type) {
+  case SOCK_RAW:
+    conn = netconn_new_with_proto_and_callback(NETCONN_RAW, protocol, event_callback);
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_RAW, %d) = ", domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol));
+    break;
+  case SOCK_DGRAM:
+    conn = netconn_new_with_callback(NETCONN_UDP, event_callback);
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_DGRAM, %d) = ", domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol));
+    break;
+  case SOCK_STREAM:
+    conn = netconn_new_with_callback(NETCONN_TCP, event_callback);
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_STREAM, %d) = ", domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol));
+    break;
+  default:
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%d, %d/UNKNOWN, %d) = -1\n", domain, type, protocol));
+    set_errno(EINVAL);
+    return -1;
+  }
+
+  if (!conn) {
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("-1 / ENOBUFS (could not create netconn)\n"));
+    set_errno(ENOBUFS);
+    return -1;
+  }
+
+  i = alloc_socket(conn);
+
+  if (i == -1) {
+    netconn_delete(conn);
+  set_errno(ENOBUFS);
+  return -1;
+  }
+  conn->socket = i;
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("%d\n", i));
+  set_errno(0);
+  return i;
+}
+
+int
+lwip_write(int s, void *data, int size)
+{
+   return lwip_send(s, data, size, 0);
+}
+
+
+static int
+lwip_selscan(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset)
+{
+    int i, nready = 0;
+    fd_set lreadset, lwriteset, lexceptset;
+    struct lwip_socket *p_sock;
+
+    FD_ZERO(&lreadset);
+    FD_ZERO(&lwriteset);
+    FD_ZERO(&lexceptset);
+
+    /* Go through each socket in each list to count number of sockets which
+       currently match */
+    for(i = 0; i < maxfdp1; i++)
+    {
+        if (FD_ISSET(i, readset))
+        {
+            /* See if netconn of this socket is ready for read */
+            p_sock = get_socket(i);
+            if (p_sock && (p_sock->lastdata || p_sock->rcvevent))
+            {
+                FD_SET(i, &lreadset);
+		LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_selscan: fd=%d ready for reading\n", i));
+                nready++;
+            }
+        }
+        if (FD_ISSET(i, writeset))
+        {
+            /* See if netconn of this socket is ready for write */
+            p_sock = get_socket(i);
+            if (p_sock && p_sock->sendevent)
+            {
+                FD_SET(i, &lwriteset);
+		LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_selscan: fd=%d ready for writing\n", i));
+                nready++;
+            }
+        }
+    }
+    *readset = lreadset;
+    *writeset = lwriteset;
+    FD_ZERO(exceptset);
+
+    return nready;
+}
+
+
+
+int
+lwip_select(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset,
+               struct timeval *timeout)
+{
+    int i;
+    int nready;
+    fd_set lreadset, lwriteset, lexceptset;
+    u32_t msectimeout;
+    struct lwip_select_cb select_cb;
+    struct lwip_select_cb *p_selcb;
+
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select(%d, %p, %p, %p, tvsec=%ld tvusec=%ld)\n", maxfdp1, (void *)readset, (void *) writeset, (void *) exceptset, timeout ? timeout->tv_sec : -1L, timeout ? timeout->tv_usec : -1L));
+
+    select_cb.next = 0;
+    select_cb.readset = readset;
+    select_cb.writeset = writeset;
+    select_cb.exceptset = exceptset;
+    select_cb.sem_signalled = 0;
+
+    /* Protect ourselves searching through the list */
+    if (!selectsem)
+        selectsem = sys_sem_new(1);
+    sys_sem_wait(selectsem);
+
+    if (readset)
+        lreadset = *readset;
+    else
+        FD_ZERO(&lreadset);
+    if (writeset)
+        lwriteset = *writeset;
+    else
+        FD_ZERO(&lwriteset);
+    if (exceptset)
+        lexceptset = *exceptset;
+    else
+        FD_ZERO(&lexceptset);
+
+    /* Go through each socket in each list to count number of sockets which
+       currently match */
+    nready = lwip_selscan(maxfdp1, &lreadset, &lwriteset, &lexceptset);
+
+    /* If we don't have any current events, then suspend if we are supposed to */
+    if (!nready)
+    {
+        if (timeout && timeout->tv_sec == 0 && timeout->tv_usec == 0)
+        {
+            sys_sem_signal(selectsem);
+            if (readset)
+                FD_ZERO(readset);
+            if (writeset)
+                FD_ZERO(writeset);
+            if (exceptset)
+                FD_ZERO(exceptset);
+
+	    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: no timeout, returning 0\n"));
+	    set_errno(0);
+
+            return 0;
+        }
+
+        /* add our semaphore to list */
+        /* We don't actually need any dynamic memory. Our entry on the
+         * list is only valid while we are in this function, so it's ok
+         * to use local variables */
+
+        select_cb.sem = sys_sem_new(0);
+        /* Note that we are still protected */
+        /* Put this select_cb on top of list */
+        select_cb.next = select_cb_list;
+        select_cb_list = &select_cb;
+
+        /* Now we can safely unprotect */
+        sys_sem_signal(selectsem);
+
+        /* Now just wait to be woken */
+        if (timeout == 0)
+            /* Wait forever */
+            msectimeout = 0;
+        else
+            msectimeout =  ((timeout->tv_sec * 1000) + ((timeout->tv_usec + 500)/1000));
+
+        i = sys_sem_wait_timeout(select_cb.sem, msectimeout);
+
+        /* Take us off the list */
+        sys_sem_wait(selectsem);
+        if (select_cb_list == &select_cb)
+            select_cb_list = select_cb.next;
+        else
+            for (p_selcb = select_cb_list; p_selcb; p_selcb = p_selcb->next)
+                if (p_selcb->next == &select_cb)
+                {
+                    p_selcb->next = select_cb.next;
+                    break;
+                }
+
+        sys_sem_signal(selectsem);
+
+        sys_sem_free(select_cb.sem);
+        if (i == 0)             /* Timeout */
+        {
+            if (readset)
+                FD_ZERO(readset);
+            if (writeset)
+                FD_ZERO(writeset);
+            if (exceptset)
+                FD_ZERO(exceptset);
+
+	    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: timeout expired\n"));
+	    set_errno(0);
+
+            return 0;
+        }
+
+        if (readset)
+            lreadset = *readset;
+        else
+            FD_ZERO(&lreadset);
+        if (writeset)
+            lwriteset = *writeset;
+        else
+            FD_ZERO(&lwriteset);
+        if (exceptset)
+            lexceptset = *exceptset;
+        else
+            FD_ZERO(&lexceptset);
+
+        /* See what's set */
+        nready = lwip_selscan(maxfdp1, &lreadset, &lwriteset, &lexceptset);
+    }
+    else
+        sys_sem_signal(selectsem);
+
+    if (readset)
+        *readset = lreadset;
+    if (writeset)
+        *writeset = lwriteset;
+    if (exceptset)
+        *exceptset = lexceptset;
+
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: nready=%d\n", nready));
+    set_errno(0);
+
+    return nready;
+}
+
+
+static void
+event_callback(struct netconn *conn, enum netconn_evt evt, u16_t len)
+{
+    int s;
+    struct lwip_socket *sock;
+    struct lwip_select_cb *scb;
+
+    /* Get socket */
+    if (conn)
+    {
+        s = conn->socket;
+        if (s < 0)
+        {
+            /* Data comes in right away after an accept, even though
+             * the server task might not have created a new socket yet.
+             * Just count down (or up) if that's the case and we
+             * will use the data later. Note that only receive events
+             * can happen before the new socket is set up. */
+            if (evt == NETCONN_EVT_RCVPLUS)
+                conn->socket--;
+            return;
+        }
+
+        sock = get_socket(s);
+        if (!sock)
+            return;
+    }
+    else
+        return;
+
+    if (!selectsem)
+        selectsem = sys_sem_new(1);
+
+    sys_sem_wait(selectsem);
+    /* Set event as required */
+    switch (evt)
+    {
+      case NETCONN_EVT_RCVPLUS:
+        sock->rcvevent++;
+        break;
+      case NETCONN_EVT_RCVMINUS:
+        sock->rcvevent--;
+        break;
+      case NETCONN_EVT_SENDPLUS:
+        sock->sendevent = 1;
+        break;
+      case NETCONN_EVT_SENDMINUS:
+        sock->sendevent = 0;
+        break;
+    }
+    sys_sem_signal(selectsem);
+
+    /* Now decide if anyone is waiting for this socket */
+    /* NOTE: This code is written this way to protect the select link list
+       but to avoid a deadlock situation by releasing socksem before
+       signalling for the select. This means we need to go through the list
+       multiple times ONLY IF a select was actually waiting. We go through
+       the list the number of waiting select calls + 1. This list is
+       expected to be small. */
+    while (1)
+    {
+        sys_sem_wait(selectsem);
+        for (scb = select_cb_list; scb; scb = scb->next)
+        {
+            if (scb->sem_signalled == 0)
+            {
+                /* Test this select call for our socket */
+                if (scb->readset && FD_ISSET(s, scb->readset))
+                    if (sock->rcvevent)
+                        break;
+                if (scb->writeset && FD_ISSET(s, scb->writeset))
+                    if (sock->sendevent)
+                        break;
+            }
+        }
+        if (scb)
+        {
+            scb->sem_signalled = 1;
+            sys_sem_signal(selectsem);
+            sys_sem_signal(scb->sem);
+        } else {
+            sys_sem_signal(selectsem);
+            break;
+        }
+    }
+
+}
+
+
+
+
+int lwip_shutdown(int s, int how)
+{
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_shutdown(%d, how=%d)\n", s, how));
+  return lwip_close(s); /* XXX temporary hack until proper implementation */
+}
+
+int lwip_getpeername (int s, struct sockaddr *name, socklen_t *namelen)
+{
+  struct lwip_socket *sock;
+  struct sockaddr_in sin;
+  struct ip_addr naddr;
+
+  sock = get_socket(s);
+  if (!sock) {
+    set_errno(EBADF);
+    return -1;
+  }
+
+  memset(&sin, 0, sizeof(sin));
+  sin.sin_len = sizeof(sin);
+  sin.sin_family = AF_INET;
+
+  /* get the IP address and port of the remote host */
+  netconn_peer(sock->conn, &naddr, &sin.sin_port);
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getpeername(%d, addr=", s));
+  ip_addr_debug_print(SOCKETS_DEBUG, &naddr);
+  LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%d)\n", sin.sin_port));
+
+  sin.sin_port = htons(sin.sin_port);
+  sin.sin_addr.s_addr = naddr.addr;
+
+  if (*namelen > sizeof(sin))
+      *namelen = sizeof(sin);
+
+  memcpy(name, &sin, *namelen);
+  sock_set_errno(sock, 0);
+  return 0;
+}
+
+int lwip_getsockname (int s, struct sockaddr *name, socklen_t *namelen)
+{
+  struct lwip_socket *sock;
+  struct sockaddr_in sin;
+  struct ip_addr *naddr;
+
+  sock = get_socket(s);
+  if (!sock) {
+    set_errno(EBADF);
+    return -1;
+  }
+
+  memset(&sin, 0, sizeof(sin));
+  sin.sin_len = sizeof(sin);
+  sin.sin_family = AF_INET;
+
+  /* get the IP address and port of the remote host */
+  netconn_addr(sock->conn, &naddr, &sin.sin_port);
+
+  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockname(%d, addr=", s));
+  ip_addr_debug_print(SOCKETS_DEBUG, naddr);
+  LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%d)\n", sin.sin_port));
+
+  sin.sin_port = htons(sin.sin_port);
+  sin.sin_addr.s_addr = naddr->addr;
+
+  if (*namelen > sizeof(sin))
+      *namelen = sizeof(sin);
+
+  memcpy(name, &sin, *namelen);
+  sock_set_errno(sock, 0);
+  return 0;
+}
+
+int lwip_getsockopt (int s, int level, int optname, void *optval, socklen_t *optlen)
+{
+  int err = 0;
+  struct lwip_socket *sock = get_socket(s);
+
+  if(!sock) {
+   	set_errno(EBADF);
+    return -1;
+  }
+
+  if( NULL == optval || NULL == optlen ) {
+    sock_set_errno( sock, EFAULT );
+    return -1;
+  }
+
+  /* Do length and type checks for the various options first, to keep it readable. */
+  switch( level ) {
+   
+/* Level: SOL_SOCKET */
+  case SOL_SOCKET:
+      switch(optname) {
+         
+      case SO_ACCEPTCONN:
+      case SO_BROADCAST:
+      /* UNIMPL case SO_DEBUG: */
+      /* UNIMPL case SO_DONTROUTE: */
+      case SO_ERROR:
+      case SO_KEEPALIVE:
+      /* UNIMPL case SO_OOBINLINE: */
+      /* UNIMPL case SO_RCVBUF: */
+      /* UNIMPL case SO_SNDBUF: */
+      /* UNIMPL case SO_RCVLOWAT: */
+      /* UNIMPL case SO_SNDLOWAT: */
+#if SO_REUSE
+      case SO_REUSEADDR:
+      case SO_REUSEPORT:
+#endif /* SO_REUSE */
+      case SO_TYPE:
+      /* UNIMPL case SO_USELOOPBACK: */
+        if( *optlen < sizeof(int) ) {
+          err = EINVAL;
+        }
+          break;
+
+      default:
+        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, UNIMPL: optname=0x%x, ..)\n", s, optname));
+        err = ENOPROTOOPT;
+      }  /* switch */
+      break;
+                     
+/* Level: IPPROTO_IP */
+  case IPPROTO_IP:
+      switch(optname) {
+      /* UNIMPL case IP_HDRINCL: */
+      /* UNIMPL case IP_RCVDSTADDR: */
+      /* UNIMPL case IP_RCVIF: */
+      case IP_TTL:
+      case IP_TOS:
+        if( *optlen < sizeof(int) ) {
+          err = EINVAL;
+        }
+        break;
+
+      default:
+        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, UNIMPL: optname=0x%x, ..)\n", s, optname));
+        err = ENOPROTOOPT;
+      }  /* switch */
+      break;
+         
+/* Level: IPPROTO_TCP */
+  case IPPROTO_TCP:
+      if( *optlen < sizeof(int) ) {
+        err = EINVAL;
+        break;
+    }
+      
+      /* If this is no TCP socket, ignore any options. */
+      if ( sock->conn->type != NETCONN_TCP ) return 0;
+
+      switch( optname ) {
+      case TCP_NODELAY:
+      case TCP_KEEPALIVE:
+        break;
+         
+      default:
+        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, UNIMPL: optname=0x%x, ..)\n", s, optname));
+        err = ENOPROTOOPT;
+      }  /* switch */
+      break;
+
+/* UNDEFINED LEVEL */
+  default:
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, level=0x%x, UNIMPL: optname=0x%x, ..)\n", s, level, optname));
+      err = ENOPROTOOPT;
+  }  /* switch */
+
+   
+  if( 0 != err ) {
+    sock_set_errno(sock, err);
+    return -1;
+  }
+   
+
+
+  /* Now do the actual option processing */
+
+  switch(level) {
+   
+/* Level: SOL_SOCKET */
+  case SOL_SOCKET:
+    switch( optname ) {
+
+    /* The option flags */
+    case SO_ACCEPTCONN:
+    case SO_BROADCAST:
+    /* UNIMPL case SO_DEBUG: */
+    /* UNIMPL case SO_DONTROUTE: */
+    case SO_KEEPALIVE:
+    /* UNIMPL case SO_OOBINCLUDE: */
+#if SO_REUSE
+    case SO_REUSEADDR:
+    case SO_REUSEPORT:
+#endif /* SO_REUSE */
+    /*case SO_USELOOPBACK: UNIMPL */
+      *(int*)optval = sock->conn->pcb.tcp->so_options & optname;
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, optname=0x%x, ..) = %s\n", s, optname, (*(int*)optval?"on":"off")));
+      break;
+
+    case SO_TYPE:
+      switch (sock->conn->type) {
+      case NETCONN_RAW:
+        *(int*)optval = SOCK_RAW;
+        break;
+      case NETCONN_TCP:
+        *(int*)optval = SOCK_STREAM;
+        break;
+      case NETCONN_UDP:
+      case NETCONN_UDPLITE:
+      case NETCONN_UDPNOCHKSUM:
+        *(int*)optval = SOCK_DGRAM;
+        break;
+      default: /* unrecognized socket type */
+        *(int*)optval = sock->conn->type;
+        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_TYPE): unrecognized socket type %d\n", s, *(int *)optval));
+      }  /* switch */
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_TYPE) = %d\n", s, *(int *)optval));
+      break;
+
+    case SO_ERROR:
+      *(int *)optval = sock->err;
+      sock->err = 0;
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_ERROR) = %d\n", s, *(int *)optval));
+      break;
+    }  /* switch */
+    break;
+
+/* Level: IPPROTO_IP */
+  case IPPROTO_IP:
+    switch( optname ) {
+    case IP_TTL:
+      *(int*)optval = sock->conn->pcb.tcp->ttl;
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_TTL) = %d\n", s, *(int *)optval));
+      break;
+    case IP_TOS:
+      *(int*)optval = sock->conn->pcb.tcp->tos;
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_TOS) = %d\n", s, *(int *)optval));
+      break;
+    }  /* switch */
+    break;
+
+/* Level: IPPROTO_TCP */
+  case IPPROTO_TCP:
+    switch( optname ) {
+    case TCP_NODELAY:
+      *(int*)optval = (sock->conn->pcb.tcp->flags & TF_NODELAY);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, TCP_NODELAY) = %s\n", s, (*(int*)optval)?"on":"off") );
+      break;
+    case TCP_KEEPALIVE:
+      *(int*)optval = (int)sock->conn->pcb.tcp->keepalive;
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, TCP_KEEPALIVE) = %d\n", s, *(int *)optval));
+      break;
+    }  /* switch */
+    break;
+  }
+
+
+  sock_set_errno(sock, err);
+  return err ? -1 : 0;
+}
+
+int lwip_setsockopt (int s, int level, int optname, const void *optval, socklen_t optlen)
+{
+  struct lwip_socket *sock = get_socket(s);
+  int err = 0;
+
+  if(!sock) {
+   	set_errno(EBADF);
+    return -1;
+  }
+
+  if( NULL == optval ) {
+    sock_set_errno( sock, EFAULT );
+    return -1;
+  }
+
+
+  /* Do length and type checks for the various options first, to keep it readable. */
+  switch( level ) {
+
+/* Level: SOL_SOCKET */
+  case SOL_SOCKET:
+    switch(optname) {
+
+    case SO_BROADCAST:
+    /* UNIMPL case SO_DEBUG: */
+    /* UNIMPL case SO_DONTROUTE: */
+    case SO_KEEPALIVE:
+    /* UNIMPL case SO_OOBINLINE: */
+    /* UNIMPL case SO_RCVBUF: */
+    /* UNIMPL case SO_SNDBUF: */
+    /* UNIMPL case SO_RCVLOWAT: */
+    /* UNIMPL case SO_SNDLOWAT: */
+#if SO_REUSE
+    case SO_REUSEADDR:
+    case SO_REUSEPORT:
+#endif /* SO_REUSE */
+    /* UNIMPL case SO_USELOOPBACK: */
+      if( optlen < sizeof(int) ) {
+        err = EINVAL;
+      }
+      break;
+    default:
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, SOL_SOCKET, UNIMPL: optname=0x%x, ..)\n", s, optname));
+      err = ENOPROTOOPT;
+    }  /* switch */
+    break;
+
+/* Level: IPPROTO_IP */
+  case IPPROTO_IP:
+    switch(optname) {
+    /* UNIMPL case IP_HDRINCL: */
+    /* UNIMPL case IP_RCVDSTADDR: */
+    /* UNIMPL case IP_RCVIF: */
+    case IP_TTL:
+    case IP_TOS:
+      if( optlen < sizeof(int) ) {
+        err = EINVAL;
+      }
+        break;
+      default:
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, UNIMPL: optname=0x%x, ..)\n", s, optname));
+      err = ENOPROTOOPT;
+    }  /* switch */
+    break;
+
+/* Level: IPPROTO_TCP */
+  case IPPROTO_TCP:
+    if( optlen < sizeof(int) ) {
+      err = EINVAL;
+        break;
+    }
+
+    /* If this is no TCP socket, ignore any options. */
+    if ( sock->conn->type != NETCONN_TCP ) return 0;
+
+    switch( optname ) {
+    case TCP_NODELAY:
+    case TCP_KEEPALIVE:
+      break;
+
+    default:
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, UNIMPL: optname=0x%x, ..)\n", s, optname));
+      err = ENOPROTOOPT;
+    }  /* switch */
+    break;
+
+/* UNDEFINED LEVEL */      
+  default:
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, level=0x%x, UNIMPL: optname=0x%x, ..)\n", s, level, optname));
+    err = ENOPROTOOPT;
+  }  /* switch */
+
+
+  if( 0 != err ) {
+    sock_set_errno(sock, err);
+    return -1;
+  }
+
+
+
+  /* Now do the actual option processing */
+
+  switch(level) {
+
+/* Level: SOL_SOCKET */
+  case SOL_SOCKET:
+    switch(optname) {
+
+    /* The option flags */
+    case SO_BROADCAST:
+    /* UNIMPL case SO_DEBUG: */
+    /* UNIMPL case SO_DONTROUTE: */
+    case SO_KEEPALIVE:
+    /* UNIMPL case SO_OOBINCLUDE: */
+#if SO_REUSE
+    case SO_REUSEADDR:
+    case SO_REUSEPORT:
+#endif /* SO_REUSE */
+    /* UNIMPL case SO_USELOOPBACK: */
+      if ( *(int*)optval ) {
+        sock->conn->pcb.tcp->so_options |= optname;
+      } else {
+        sock->conn->pcb.tcp->so_options &= ~optname;
+      }
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, SOL_SOCKET, optname=0x%x, ..) -> %s\n", s, optname, (*(int*)optval?"on":"off")));
+      break;
+    }  /* switch */
+    break;
+
+/* Level: IPPROTO_IP */
+  case IPPROTO_IP:
+    switch( optname ) {
+    case IP_TTL:
+      sock->conn->pcb.tcp->ttl = (u8_t)(*(int*)optval);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, IP_TTL, ..) -> %u\n", s, sock->conn->pcb.tcp->ttl));
+      break;
+    case IP_TOS:
+      sock->conn->pcb.tcp->tos = (u8_t)(*(int*)optval);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, IP_TOS, ..)-> %u\n", s, sock->conn->pcb.tcp->tos));
+      break;
+    }  /* switch */
+    break;
+
+/* Level: IPPROTO_TCP */
+  case IPPROTO_TCP:
+    switch( optname ) {
+    case TCP_NODELAY:
+      if ( *(int*)optval ) {
+        sock->conn->pcb.tcp->flags |= TF_NODELAY;
+      } else {
+        sock->conn->pcb.tcp->flags &= ~TF_NODELAY;
+      }
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_NODELAY) -> %s\n", s, (*(int *)optval)?"on":"off") );
+      break;
+    case TCP_KEEPALIVE:
+      sock->conn->pcb.tcp->keepalive = (u32_t)(*(int*)optval);
+      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPALIVE) -> %lu\n", s, sock->conn->pcb.tcp->keepalive));
+      break;
+    }  /* switch */
+    break;
+  }  /* switch */
+
+  sock_set_errno(sock, err);
+  return err ? -1 : 0;
+}
+
+int lwip_ioctl(int s, long cmd, void *argp)
+{
+  struct lwip_socket *sock = get_socket(s);
+
+  if(!sock) {
+   	set_errno(EBADF);
+    return -1;
+  }
+
+  switch (cmd) {
+  case FIONREAD:
+    if (!argp) {
+      sock_set_errno(sock, EINVAL);
+      return -1;
+    }
+
+    *((u16_t*)argp) = sock->conn->recv_avail;
+
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, FIONREAD, %p) = %u\n", s, argp, *((u16_t*)argp)));
+    sock_set_errno(sock, 0);
+    return 0;
+
+  case FIONBIO:
+    if (argp && *(u32_t*)argp)
+      sock->flags |= O_NONBLOCK;
+    else
+      sock->flags &= ~O_NONBLOCK;
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, FIONBIO, %d)\n", s, !!(sock->flags & O_NONBLOCK)));
+    sock_set_errno(sock, 0);
+    return 0;
+
+  default:
+    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, UNIMPL: 0x%lx, %p)\n", s, cmd, argp));
+    sock_set_errno(sock, ENOSYS); /* not yet implemented */
+    return -1;
+  }
+}
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/api/tcpip.c b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/api/tcpip.c
new file mode 100644
index 000000000..db86cf4ca
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/api/tcpip.c
@@ -0,0 +1,198 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/sys.h"
+
+#include "lwip/memp.h"
+#include "lwip/pbuf.h"
+
+#include "lwip/ip.h"
+#include "lwip/ip_frag.h"
+#include "lwip/udp.h"
+#include "lwip/tcp.h"
+
+#include "lwip/tcpip.h"
+
+static void (* tcpip_init_done)(void *arg) = NULL;
+static void *tcpip_init_done_arg;
+static sys_mbox_t mbox;
+
+#if LWIP_TCP
+static int tcpip_tcp_timer_active = 0;
+
+static void
+tcpip_tcp_timer(void *arg)
+{
+  (void)arg;
+
+  /* call TCP timer handler */
+  tcp_tmr();
+  /* timer still needed? */
+  if (tcp_active_pcbs || tcp_tw_pcbs) {
+    /* restart timer */
+    sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL);
+  } else {
+    /* disable timer */
+    tcpip_tcp_timer_active = 0;
+  }
+}
+
+#if !NO_SYS
+void
+tcp_timer_needed(void)
+{
+  /* timer is off but needed again? */
+  if (!tcpip_tcp_timer_active && (tcp_active_pcbs || tcp_tw_pcbs)) {
+    /* enable and start timer */
+    tcpip_tcp_timer_active = 1;
+    sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL);
+  }
+}
+#endif /* !NO_SYS */
+#endif /* LWIP_TCP */
+
+#if IP_REASSEMBLY
+static void
+ip_timer(void *data)
+{
+  LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip: ip_reass_tmr()\n"));
+  ip_reass_tmr();
+  sys_timeout(1000, ip_timer, NULL);
+}
+#endif
+
+static void
+tcpip_thread(void *arg)
+{
+  struct tcpip_msg *msg;
+
+  (void)arg;
+
+  ip_init();
+#if LWIP_UDP  
+  udp_init();
+#endif
+#if LWIP_TCP
+  tcp_init();
+#endif
+#if IP_REASSEMBLY
+  sys_timeout(1000, ip_timer, NULL);
+#endif
+  if (tcpip_init_done != NULL) {
+    tcpip_init_done(tcpip_init_done_arg);
+  }
+
+  while (1) {                          /* MAIN Loop */
+    sys_mbox_fetch(mbox, (void *)&msg);
+    switch (msg->type) {
+    case TCPIP_MSG_API:
+      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: API message %p\n", (void *)msg));
+      api_msg_input(msg->msg.apimsg);
+      break;
+    case TCPIP_MSG_INPUT:
+      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: IP packet %p\n", (void *)msg));
+      ip_input(msg->msg.inp.p, msg->msg.inp.netif);
+      break;
+    case TCPIP_MSG_CALLBACK:
+      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: CALLBACK %p\n", (void *)msg));
+      msg->msg.cb.f(msg->msg.cb.ctx);
+      break;
+    default:
+      break;
+    }
+    memp_free(MEMP_TCPIP_MSG, msg);
+  }
+}
+
+err_t
+tcpip_input(struct pbuf *p, struct netif *inp)
+{
+  struct tcpip_msg *msg;
+  
+  msg = memp_malloc(MEMP_TCPIP_MSG);
+  if (msg == NULL) {
+    pbuf_free(p);    
+    return ERR_MEM;  
+  }
+  
+  msg->type = TCPIP_MSG_INPUT;
+  msg->msg.inp.p = p;
+  msg->msg.inp.netif = inp;
+  sys_mbox_post(mbox, msg);
+  return ERR_OK;
+}
+
+err_t
+tcpip_callback(void (*f)(void *ctx), void *ctx)
+{
+  struct tcpip_msg *msg;
+  
+  msg = memp_malloc(MEMP_TCPIP_MSG);
+  if (msg == NULL) {
+    return ERR_MEM;  
+  }
+  
+  msg->type = TCPIP_MSG_CALLBACK;
+  msg->msg.cb.f = f;
+  msg->msg.cb.ctx = ctx;
+  sys_mbox_post(mbox, msg);
+  return ERR_OK;
+}
+
+void
+tcpip_apimsg(struct api_msg *apimsg)
+{
+  struct tcpip_msg *msg;
+  msg = memp_malloc(MEMP_TCPIP_MSG);
+  if (msg == NULL) {
+    memp_free(MEMP_API_MSG, apimsg);
+    return;
+  }
+  msg->type = TCPIP_MSG_API;
+  msg->msg.apimsg = apimsg;
+  sys_mbox_post(mbox, msg);
+}
+
+void
+tcpip_init(void (* initfunc)(void *), void *arg)
+{
+  tcpip_init_done = initfunc;
+  tcpip_init_done_arg = arg;
+  mbox = sys_mbox_new();
+  sys_thread_new(tcpip_thread, NULL, TCPIP_THREAD_PRIO);
+}
+
+
+
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/dhcp.c b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/dhcp.c
new file mode 100644
index 000000000..ad292d23b
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/dhcp.c
@@ -0,0 +1,1455 @@
+/**
+ * @file
+ *
+ * Dynamic Host Configuration Protocol client
+ */
+
+/*
+ *
+ * Copyright (c) 2001-2004 Leon Woestenberg 
+ * Copyright (c) 2001-2004 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is a contribution to the lwIP TCP/IP stack.
+ * The Swedish Institute of Computer Science and Adam Dunkels
+ * are specifically granted permission to redistribute this
+ * source code.
+ *
+ * Author: Leon Woestenberg 
+ *
+ * This is a DHCP client for the lwIP TCP/IP stack. It aims to conform
+ * with RFC 2131 and RFC 2132.
+ *
+ * TODO:
+ * - Proper parsing of DHCP messages exploiting file/sname field overloading.
+ * - Add JavaDoc style documentation (API, internals).
+ * - Support for interfaces other than Ethernet (SLIP, PPP, ...)
+ *
+ * Please coordinate changes and requests with Leon Woestenberg
+ * 
+ *
+ * Integration with your code:
+ *
+ * In lwip/dhcp.h
+ * #define DHCP_COARSE_TIMER_SECS (recommended 60 which is a minute)
+ * #define DHCP_FINE_TIMER_MSECS (recommended 500 which equals TCP coarse timer)
+ *
+ * Then have your application call dhcp_coarse_tmr() and
+ * dhcp_fine_tmr() on the defined intervals.
+ *
+ * dhcp_start(struct netif *netif);
+ * starts a DHCP client instance which configures the interface by
+ * obtaining an IP address lease and maintaining it.
+ *
+ * Use dhcp_release(netif) to end the lease and use dhcp_stop(netif)
+ * to remove the DHCP client.
+ *
+ */
+ 
+#include 
+ 
+#include "lwip/stats.h"
+#include "lwip/mem.h"
+#include "lwip/udp.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/inet.h"
+#include "netif/etharp.h"
+
+#include "lwip/sys.h"
+#include "lwip/opt.h"
+#include "lwip/dhcp.h"
+
+#if LWIP_DHCP /* don't build if not configured for use in lwipopt.h */
+
+/** global transaction identifier, must be
+ *  unique for each DHCP request. We simply increment, starting
+ *  with this value (easy to match with a packet analyzer) */
+static u32_t xid = 0xABCD0000;
+
+/** DHCP client state machine functions */
+static void dhcp_handle_ack(struct netif *netif);
+static void dhcp_handle_nak(struct netif *netif);
+static void dhcp_handle_offer(struct netif *netif);
+
+static err_t dhcp_discover(struct netif *netif);
+static err_t dhcp_select(struct netif *netif);
+static void dhcp_check(struct netif *netif);
+static void dhcp_bind(struct netif *netif);
+static err_t dhcp_decline(struct netif *netif);
+static err_t dhcp_rebind(struct netif *netif);
+static void dhcp_set_state(struct dhcp *dhcp, u8_t new_state);
+
+/** receive, unfold, parse and free incoming messages */
+static void dhcp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *addr, u16_t port);
+static err_t dhcp_unfold_reply(struct dhcp *dhcp);
+static u8_t *dhcp_get_option_ptr(struct dhcp *dhcp, u8_t option_type);
+static u8_t dhcp_get_option_byte(u8_t *ptr);
+static u16_t dhcp_get_option_short(u8_t *ptr);
+static u32_t dhcp_get_option_long(u8_t *ptr);
+static void dhcp_free_reply(struct dhcp *dhcp);
+
+/** set the DHCP timers */
+static void dhcp_timeout(struct netif *netif);
+static void dhcp_t1_timeout(struct netif *netif);
+static void dhcp_t2_timeout(struct netif *netif);
+
+/** build outgoing messages */
+/** create a DHCP request, fill in common headers */
+static err_t dhcp_create_request(struct netif *netif);
+/** free a DHCP request */
+static void dhcp_delete_request(struct netif *netif);
+/** add a DHCP option (type, then length in bytes) */
+static void dhcp_option(struct dhcp *dhcp, u8_t option_type, u8_t option_len);
+/** add option values */
+static void dhcp_option_byte(struct dhcp *dhcp, u8_t value);
+static void dhcp_option_short(struct dhcp *dhcp, u16_t value);
+static void dhcp_option_long(struct dhcp *dhcp, u32_t value);
+/** always add the DHCP options trailer to end and pad */
+static void dhcp_option_trailer(struct dhcp *dhcp);
+
+/**
+ * Back-off the DHCP client (because of a received NAK response).
+ *
+ * Back-off the DHCP client because of a received NAK. Receiving a
+ * NAK means the client asked for something non-sensible, for
+ * example when it tries to renew a lease obtained on another network.
+ *
+ * We back-off and will end up restarting a fresh DHCP negotiation later.
+ *
+ * @param state pointer to DHCP state structure
+ */
+static void dhcp_handle_nak(struct netif *netif) {
+  struct dhcp *dhcp = netif->dhcp;
+  u16_t msecs = 10 * 1000;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_handle_nak(netif=%p) %c%c%"U16_F"\n", 
+    (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_handle_nak(): set request timeout %"U16_F" msecs\n", msecs));
+  dhcp_set_state(dhcp, DHCP_BACKING_OFF);
+}
+
+/**
+ * Checks if the offered IP address is already in use.
+ *
+ * It does so by sending an ARP request for the offered address and
+ * entering CHECKING state. If no ARP reply is received within a small
+ * interval, the address is assumed to be free for use by us.
+ */
+static void dhcp_check(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result;
+  u16_t msecs;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_check(netif=%p) %c%c\n", (void *)netif, (s16_t)netif->name[0],
+    (s16_t)netif->name[1]));
+  /* create an ARP query for the offered IP address, expecting that no host
+     responds, as the IP address should not be in use. */
+  result = etharp_query(netif, &dhcp->offered_ip_addr, NULL);
+  if (result != ERR_OK) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_check: could not perform ARP query\n"));
+  }
+  dhcp->tries++;
+  msecs = 500;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_check(): set request timeout %"U16_F" msecs\n", msecs));
+  dhcp_set_state(dhcp, DHCP_CHECKING);
+}
+
+/**
+ * Remember the configuration offered by a DHCP server.
+ *
+ * @param state pointer to DHCP state structure
+ */
+static void dhcp_handle_offer(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  /* obtain the server address */
+  u8_t *option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_SERVER_ID);
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_handle_offer(netif=%p) %c%c%"U16_F"\n",
+    (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
+  if (option_ptr != NULL)
+  {
+    dhcp->server_ip_addr.addr = htonl(dhcp_get_option_long(&option_ptr[2]));
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_handle_offer(): server 0x%08"X32_F"\n", dhcp->server_ip_addr.addr));
+    /* remember offered address */
+    ip_addr_set(&dhcp->offered_ip_addr, (struct ip_addr *)&dhcp->msg_in->yiaddr);
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_handle_offer(): offer for 0x%08"X32_F"\n", dhcp->offered_ip_addr.addr));
+
+    dhcp_select(netif);
+  }
+}
+
+/**
+ * Select a DHCP server offer out of all offers.
+ *
+ * Simply select the first offer received.
+ *
+ * @param netif the netif under DHCP control
+ * @return lwIP specific error (see error.h)
+ */
+static err_t dhcp_select(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result;
+  u32_t msecs;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_select(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
+
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_request(netif);
+  if (result == ERR_OK)
+  {
+    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+    dhcp_option_byte(dhcp, DHCP_REQUEST);
+
+    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+    dhcp_option_short(dhcp, 576);
+
+    /* MUST request the offered IP address */
+    dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4);
+    dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr));
+
+    dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4);
+    dhcp_option_long(dhcp, ntohl(dhcp->server_ip_addr.addr));
+
+    dhcp_option(dhcp, DHCP_OPTION_PARAMETER_REQUEST_LIST, 4/*num options*/);
+    dhcp_option_byte(dhcp, DHCP_OPTION_SUBNET_MASK);
+    dhcp_option_byte(dhcp, DHCP_OPTION_ROUTER);
+    dhcp_option_byte(dhcp, DHCP_OPTION_BROADCAST);
+    dhcp_option_byte(dhcp, DHCP_OPTION_DNS_SERVER);
+
+    dhcp_option_trailer(dhcp);
+    /* shrink the pbuf to the actual content length */
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+    /* TODO: we really should bind to a specific local interface here
+       but we cannot specify an unconfigured netif as it is addressless */
+    udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
+    /* send broadcast to any DHCP server */
+    udp_connect(dhcp->pcb, IP_ADDR_BROADCAST, DHCP_SERVER_PORT);
+    udp_send(dhcp->pcb, dhcp->p_out);
+    /* reconnect to any (or to server here?!) */
+    udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT);
+    dhcp_delete_request(netif);
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_select: REQUESTING\n"));
+    dhcp_set_state(dhcp, DHCP_REQUESTING);
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_select: could not allocate DHCP request\n"));
+  }
+  dhcp->tries++;
+  msecs = dhcp->tries < 4 ? dhcp->tries * 1000 : 4 * 1000;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_select(): set request timeout %"U32_F" msecs\n", msecs));
+  return result;
+}
+
+/**
+ * The DHCP timer that checks for lease renewal/rebind timeouts.
+ *
+ */
+void dhcp_coarse_tmr()
+{
+  struct netif *netif = netif_list;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_coarse_tmr()\n"));
+  /* iterate through all network interfaces */
+  while (netif != NULL) {
+    /* only act on DHCP configured interfaces */
+    if (netif->dhcp != NULL) {
+      /* timer is active (non zero), and triggers (zeroes) now? */
+      if (netif->dhcp->t2_timeout-- == 1) {
+        LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_coarse_tmr(): t2 timeout\n"));
+        /* this clients' rebind timeout triggered */
+        dhcp_t2_timeout(netif);
+      /* timer is active (non zero), and triggers (zeroes) now */
+      } else if (netif->dhcp->t1_timeout-- == 1) {
+        LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_coarse_tmr(): t1 timeout\n"));
+        /* this clients' renewal timeout triggered */
+        dhcp_t1_timeout(netif);
+      }
+    }
+    /* proceed to next netif */
+    netif = netif->next;
+  }
+}
+
+/**
+ * DHCP transaction timeout handling
+ *
+ * A DHCP server is expected to respond within a short period of time.
+ * This timer checks whether an outstanding DHCP request is timed out.
+ * 
+ */
+void dhcp_fine_tmr()
+{
+  struct netif *netif = netif_list;
+  /* loop through netif's */
+  while (netif != NULL) {
+    /* only act on DHCP configured interfaces */
+    if (netif->dhcp != NULL) {
+      /* timer is active (non zero), and is about to trigger now */
+      if (netif->dhcp->request_timeout-- == 1) {
+        /* { netif->dhcp->request_timeout == 0 } */
+        LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_fine_tmr(): request timeout\n"));
+        /* this clients' request timeout triggered */
+        dhcp_timeout(netif);
+      }
+    }
+    /* proceed to next network interface */
+    netif = netif->next;
+  }
+}
+
+/**
+ * A DHCP negotiation transaction, or ARP request, has timed out.
+ *
+ * The timer that was started with the DHCP or ARP request has
+ * timed out, indicating no response was received in time.
+ *
+ * @param netif the netif under DHCP control
+ *
+ */
+static void dhcp_timeout(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_timeout()\n"));
+  /* back-off period has passed, or server selection timed out */
+  if ((dhcp->state == DHCP_BACKING_OFF) || (dhcp->state == DHCP_SELECTING)) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_timeout(): restarting discovery\n"));
+    dhcp_discover(netif);
+  /* receiving the requested lease timed out */
+  } else if (dhcp->state == DHCP_REQUESTING) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): REQUESTING, DHCP request timed out\n"));
+    if (dhcp->tries <= 5) {
+      dhcp_select(netif);
+    } else {
+      LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): REQUESTING, releasing, restarting\n"));
+      dhcp_release(netif);
+      dhcp_discover(netif);
+    }
+  /* received no ARP reply for the offered address (which is good) */
+  } else if (dhcp->state == DHCP_CHECKING) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): CHECKING, ARP request timed out\n"));
+    if (dhcp->tries <= 1) {
+      dhcp_check(netif);
+    /* no ARP replies on the offered address,
+       looks like the IP address is indeed free */
+    } else {
+      /* bind the interface to the offered address */
+      dhcp_bind(netif);
+    }
+  }
+  /* did not get response to renew request? */
+  else if (dhcp->state == DHCP_RENEWING) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): RENEWING, DHCP request timed out\n"));
+    /* just retry renewal */
+    /* note that the rebind timer will eventually time-out if renew does not work */
+    dhcp_renew(netif);
+  /* did not get response to rebind request? */
+  } else if (dhcp->state == DHCP_REBINDING) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): REBINDING, DHCP request timed out\n"));
+    if (dhcp->tries <= 8) {
+      dhcp_rebind(netif);
+    } else {
+      LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): RELEASING, DISCOVERING\n"));
+      dhcp_release(netif);
+      dhcp_discover(netif);
+    }
+  }
+}
+
+/**
+ * The renewal period has timed out.
+ *
+ * @param netif the netif under DHCP control
+ */
+static void dhcp_t1_timeout(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_t1_timeout()\n"));
+  if ((dhcp->state == DHCP_REQUESTING) || (dhcp->state == DHCP_BOUND) || (dhcp->state == DHCP_RENEWING)) {
+    /* just retry to renew - note that the rebind timer (t2) will
+     * eventually time-out if renew tries fail. */
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_t1_timeout(): must renew\n"));
+    dhcp_renew(netif);
+  }
+}
+
+/**
+ * The rebind period has timed out.
+ *
+ */
+static void dhcp_t2_timeout(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_t2_timeout()\n"));
+  if ((dhcp->state == DHCP_REQUESTING) || (dhcp->state == DHCP_BOUND) || (dhcp->state == DHCP_RENEWING)) {
+    /* just retry to rebind */
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_t2_timeout(): must rebind\n"));
+    dhcp_rebind(netif);
+  }
+}
+
+/**
+ *
+ * @param netif the netif under DHCP control
+ */
+static void dhcp_handle_ack(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  u8_t *option_ptr;
+  /* clear options we might not get from the ACK */
+  dhcp->offered_sn_mask.addr = 0;
+  dhcp->offered_gw_addr.addr = 0;
+  dhcp->offered_bc_addr.addr = 0;
+
+  /* lease time given? */
+  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_LEASE_TIME);
+  if (option_ptr != NULL) {
+    /* remember offered lease time */
+    dhcp->offered_t0_lease = dhcp_get_option_long(option_ptr + 2);
+  }
+  /* renewal period given? */
+  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_T1);
+  if (option_ptr != NULL) {
+    /* remember given renewal period */
+    dhcp->offered_t1_renew = dhcp_get_option_long(option_ptr + 2);
+  } else {
+    /* calculate safe periods for renewal */
+    dhcp->offered_t1_renew = dhcp->offered_t0_lease / 2;
+  }
+
+  /* renewal period given? */
+  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_T2);
+  if (option_ptr != NULL) {
+    /* remember given rebind period */
+    dhcp->offered_t2_rebind = dhcp_get_option_long(option_ptr + 2);
+  } else {
+    /* calculate safe periods for rebinding */
+    dhcp->offered_t2_rebind = dhcp->offered_t0_lease;
+  }
+
+  /* (y)our internet address */
+  ip_addr_set(&dhcp->offered_ip_addr, &dhcp->msg_in->yiaddr);
+
+/**
+ * Patch #1308
+ * TODO: we must check if the file field is not overloaded by DHCP options!
+ */
+#if 0
+  /* boot server address */
+  ip_addr_set(&dhcp->offered_si_addr, &dhcp->msg_in->siaddr);
+  /* boot file name */
+  if (dhcp->msg_in->file[0]) {
+    dhcp->boot_file_name = mem_malloc(strlen(dhcp->msg_in->file) + 1);
+    strcpy(dhcp->boot_file_name, dhcp->msg_in->file);
+  }
+#endif
+
+  /* subnet mask */
+  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_SUBNET_MASK);
+  /* subnet mask given? */
+  if (option_ptr != NULL) {
+    dhcp->offered_sn_mask.addr = htonl(dhcp_get_option_long(&option_ptr[2]));
+  }
+
+  /* gateway router */
+  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_ROUTER);
+  if (option_ptr != NULL) {
+    dhcp->offered_gw_addr.addr = htonl(dhcp_get_option_long(&option_ptr[2]));
+  }
+
+  /* broadcast address */
+  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_BROADCAST);
+  if (option_ptr != NULL) {
+    dhcp->offered_bc_addr.addr = htonl(dhcp_get_option_long(&option_ptr[2]));
+  }
+  
+  /* DNS servers */
+  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_DNS_SERVER);
+  if (option_ptr != NULL) {
+    u8_t n;
+    dhcp->dns_count = dhcp_get_option_byte(&option_ptr[1]);
+    /* limit to at most DHCP_MAX_DNS DNS servers */
+    if (dhcp->dns_count > DHCP_MAX_DNS) dhcp->dns_count = DHCP_MAX_DNS;
+    for (n = 0; n < dhcp->dns_count; n++)
+    {
+      dhcp->offered_dns_addr[n].addr = htonl(dhcp_get_option_long(&option_ptr[2+(n<<2)]));
+    }
+  }
+}
+
+/**
+ * Start DHCP negotiation for a network interface.
+ *
+ * If no DHCP client instance was attached to this interface,
+ * a new client is created first. If a DHCP client instance
+ * was already present, it restarts negotiation.
+ *
+ * @param netif The lwIP network interface
+ * @return lwIP error code
+ * - ERR_OK - No error
+ * - ERR_MEM - Out of memory
+ *
+ */
+err_t dhcp_start(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result = ERR_OK;
+
+  LWIP_ASSERT("netif != NULL", netif != NULL);
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_start(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
+  netif->flags &= ~NETIF_FLAG_DHCP;
+
+  /* no DHCP client attached yet? */
+  if (dhcp == NULL) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): starting new DHCP client\n"));
+    dhcp = mem_malloc(sizeof(struct dhcp));
+    if (dhcp == NULL) {
+      LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): could not allocate dhcp\n"));
+      return ERR_MEM;
+    }
+    /* store this dhcp client in the netif */
+    netif->dhcp = dhcp;
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): allocated dhcp"));
+  /* already has DHCP client attached */
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE | 3, ("dhcp_start(): restarting DHCP configuration\n"));
+  }
+  	
+	/* clear data structure */
+	memset(dhcp, 0, sizeof(struct dhcp));
+  /* allocate UDP PCB */
+	dhcp->pcb = udp_new();
+	if (dhcp->pcb == NULL) {
+	  LWIP_DEBUGF(DHCP_DEBUG  | DBG_TRACE, ("dhcp_start(): could not obtain pcb\n"));
+	  mem_free((void *)dhcp);
+	  netif->dhcp = dhcp = NULL;
+	  return ERR_MEM;
+	}
+	LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): starting DHCP configuration\n"));
+  /* (re)start the DHCP negotiation */
+  result = dhcp_discover(netif);
+  if (result != ERR_OK) {
+    /* free resources allocated above */
+    dhcp_stop(netif);
+    return ERR_MEM;
+  }
+  netif->flags |= NETIF_FLAG_DHCP;
+  return result;
+}
+
+/**
+ * Inform a DHCP server of our manual configuration.
+ *
+ * This informs DHCP servers of our fixed IP address configuration
+ * by sending an INFORM message. It does not involve DHCP address
+ * configuration, it is just here to be nice to the network.
+ *
+ * @param netif The lwIP network interface
+ *
+ */
+void dhcp_inform(struct netif *netif)
+{
+  struct dhcp *dhcp;
+  err_t result = ERR_OK;
+  dhcp = mem_malloc(sizeof(struct dhcp));
+  if (dhcp == NULL) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_inform(): could not allocate dhcp\n"));
+    return;
+  }
+  netif->dhcp = dhcp;
+  memset(dhcp, 0, sizeof(struct dhcp));
+
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_inform(): allocated dhcp\n"));
+  dhcp->pcb = udp_new();
+  if (dhcp->pcb == NULL) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_inform(): could not obtain pcb"));
+    mem_free((void *)dhcp);
+    return;
+  }
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_inform(): created new udp pcb\n"));
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_request(netif);
+  if (result == ERR_OK) {
+
+    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+    dhcp_option_byte(dhcp, DHCP_INFORM);
+
+    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+    /* TODO: use netif->mtu ?! */
+    dhcp_option_short(dhcp, 576);
+
+    dhcp_option_trailer(dhcp);
+
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+    udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
+    udp_connect(dhcp->pcb, IP_ADDR_BROADCAST, DHCP_SERVER_PORT);
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_inform: INFORMING\n"));
+    udp_send(dhcp->pcb, dhcp->p_out);
+    udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT);
+    dhcp_delete_request(netif);
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_inform: could not allocate DHCP request\n"));
+  }
+
+  if (dhcp != NULL)
+  {
+    if (dhcp->pcb != NULL) udp_remove(dhcp->pcb);
+    dhcp->pcb = NULL;
+    mem_free((void *)dhcp);
+    netif->dhcp = NULL;
+  }
+}
+
+#if DHCP_DOES_ARP_CHECK
+/**
+ * Match an ARP reply with the offered IP address.
+ *
+ * @param addr The IP address we received a reply from
+ *
+ */
+void dhcp_arp_reply(struct netif *netif, struct ip_addr *addr)
+{
+  LWIP_ASSERT("netif != NULL", netif != NULL);
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_arp_reply()\n"));
+  /* is a DHCP client doing an ARP check? */
+  if ((netif->dhcp != NULL) && (netif->dhcp->state == DHCP_CHECKING)) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_arp_reply(): CHECKING, arp reply for 0x%08"X32_F"\n", addr->addr));
+    /* did a host respond with the address we
+       were offered by the DHCP server? */
+    if (ip_addr_cmp(addr, &netif->dhcp->offered_ip_addr)) {
+      /* we will not accept the offered address */
+      LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE | 1, ("dhcp_arp_reply(): arp reply matched with offered address, declining\n"));
+      dhcp_decline(netif);
+    }
+  }
+}
+
+/**
+ * Decline an offered lease.
+ *
+ * Tell the DHCP server we do not accept the offered address.
+ * One reason to decline the lease is when we find out the address
+ * is already in use by another host (through ARP).
+ */
+static err_t dhcp_decline(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result = ERR_OK;
+  u16_t msecs;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_decline()\n"));
+  dhcp_set_state(dhcp, DHCP_BACKING_OFF);
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_request(netif);
+  if (result == ERR_OK)
+  {
+    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+    dhcp_option_byte(dhcp, DHCP_DECLINE);
+
+    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+    dhcp_option_short(dhcp, 576);
+
+    dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4);
+    dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr));
+
+    dhcp_option_trailer(dhcp);
+    /* resize pbuf to reflect true size of options */
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+    udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
+    /* @todo: should we really connect here? we are performing sendto() */
+    udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT);
+    /* per section 4.4.4, broadcast DECLINE messages */
+    udp_sendto(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT);
+    dhcp_delete_request(netif);
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_decline: BACKING OFF\n"));
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_decline: could not allocate DHCP request\n"));
+  }
+  dhcp->tries++;
+  msecs = 10*1000;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+   LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_decline(): set request timeout %"U16_F" msecs\n", msecs));
+  return result;
+}
+#endif
+
+
+/**
+ * Start the DHCP process, discover a DHCP server.
+ *
+ */
+static err_t dhcp_discover(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result = ERR_OK;
+  u16_t msecs;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_discover()\n"));
+  ip_addr_set(&dhcp->offered_ip_addr, IP_ADDR_ANY);
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_request(netif);
+  if (result == ERR_OK)
+  {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_discover: making request\n"));
+    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+    dhcp_option_byte(dhcp, DHCP_DISCOVER);
+
+    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+    dhcp_option_short(dhcp, 576);
+
+    dhcp_option(dhcp, DHCP_OPTION_PARAMETER_REQUEST_LIST, 4/*num options*/);
+    dhcp_option_byte(dhcp, DHCP_OPTION_SUBNET_MASK);
+    dhcp_option_byte(dhcp, DHCP_OPTION_ROUTER);
+    dhcp_option_byte(dhcp, DHCP_OPTION_BROADCAST);
+    dhcp_option_byte(dhcp, DHCP_OPTION_DNS_SERVER);
+
+    dhcp_option_trailer(dhcp);
+
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_discover: realloc()ing\n"));
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+    /* set receive callback function with netif as user data */
+    udp_recv(dhcp->pcb, dhcp_recv, netif);
+    udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
+    udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT);
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_discover: sendto(DISCOVER, IP_ADDR_BROADCAST, DHCP_SERVER_PORT)\n"));
+    udp_sendto(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT);
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_discover: deleting()ing\n"));
+    dhcp_delete_request(netif);
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_discover: SELECTING\n"));
+    dhcp_set_state(dhcp, DHCP_SELECTING);
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_discover: could not allocate DHCP request\n"));
+  }
+  dhcp->tries++;
+  msecs = dhcp->tries < 4 ? (dhcp->tries + 1) * 1000 : 10 * 1000;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_discover(): set request timeout %"U16_F" msecs\n", msecs));
+  return result;
+}
+
+
+/**
+ * Bind the interface to the offered IP address.
+ *
+ * @param netif network interface to bind to the offered address
+ */
+static void dhcp_bind(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  struct ip_addr sn_mask, gw_addr;
+  LWIP_ASSERT("dhcp_bind: netif != NULL", netif != NULL);
+  LWIP_ASSERT("dhcp_bind: dhcp != NULL", dhcp != NULL);
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_bind(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
+
+  /* temporary DHCP lease? */
+  if (dhcp->offered_t1_renew != 0xffffffffUL) {
+    /* set renewal period timer */
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_bind(): t1 renewal timer %"U32_F" secs\n", dhcp->offered_t1_renew));
+    dhcp->t1_timeout = (dhcp->offered_t1_renew + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS;
+    if (dhcp->t1_timeout == 0) dhcp->t1_timeout = 1;
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t1_renew*1000));
+  }
+  /* set renewal period timer */
+  if (dhcp->offered_t2_rebind != 0xffffffffUL) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_bind(): t2 rebind timer %"U32_F" secs\n", dhcp->offered_t2_rebind));
+    dhcp->t2_timeout = (dhcp->offered_t2_rebind + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS;
+    if (dhcp->t2_timeout == 0) dhcp->t2_timeout = 1;
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t2_rebind*1000));
+  }
+  /* copy offered network mask */
+  ip_addr_set(&sn_mask, &dhcp->offered_sn_mask);
+
+  /* subnet mask not given? */
+  /* TODO: this is not a valid check. what if the network mask is 0? */
+  if (sn_mask.addr == 0) {
+    /* choose a safe subnet mask given the network class */
+    u8_t first_octet = ip4_addr1(&sn_mask);
+    if (first_octet <= 127) sn_mask.addr = htonl(0xff000000);
+    else if (first_octet >= 192) sn_mask.addr = htonl(0xffffff00);
+    else sn_mask.addr = htonl(0xffff0000);
+  }
+
+  ip_addr_set(&gw_addr, &dhcp->offered_gw_addr);
+  /* gateway address not given? */
+  if (gw_addr.addr == 0) {
+    /* copy network address */
+    gw_addr.addr = (dhcp->offered_ip_addr.addr & sn_mask.addr);
+    /* use first host address on network as gateway */
+    gw_addr.addr |= htonl(0x00000001);
+  }
+
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_bind(): IP: 0x%08"X32_F"\n", dhcp->offered_ip_addr.addr));
+  netif_set_ipaddr(netif, &dhcp->offered_ip_addr);
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_bind(): SN: 0x%08"X32_F"\n", sn_mask.addr));
+  netif_set_netmask(netif, &sn_mask);
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_bind(): GW: 0x%08"X32_F"\n", gw_addr.addr));
+  netif_set_gw(netif, &gw_addr);
+  /* bring the interface up */
+  netif_set_up(netif);
+  /* netif is now bound to DHCP leased address */
+  dhcp_set_state(dhcp, DHCP_BOUND);
+}
+
+/**
+ * Renew an existing DHCP lease at the involved DHCP server.
+ *
+ * @param netif network interface which must renew its lease
+ */
+err_t dhcp_renew(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result;
+  u16_t msecs;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_renew()\n"));
+  dhcp_set_state(dhcp, DHCP_RENEWING);
+
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_request(netif);
+  if (result == ERR_OK) {
+
+    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+    dhcp_option_byte(dhcp, DHCP_REQUEST);
+
+    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+    /* TODO: use netif->mtu in some way */
+    dhcp_option_short(dhcp, 576);
+
+#if 0
+    dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4);
+    dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr));
+#endif
+
+#if 0
+    dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4);
+    dhcp_option_long(dhcp, ntohl(dhcp->server_ip_addr.addr));
+#endif
+    /* append DHCP message trailer */
+    dhcp_option_trailer(dhcp);
+
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+    udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
+    udp_connect(dhcp->pcb, &dhcp->server_ip_addr, DHCP_SERVER_PORT);
+    udp_send(dhcp->pcb, dhcp->p_out);
+    dhcp_delete_request(netif);
+
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_renew: RENEWING\n"));
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_renew: could not allocate DHCP request\n"));
+  }
+  dhcp->tries++;
+  /* back-off on retries, but to a maximum of 20 seconds */
+  msecs = dhcp->tries < 10 ? dhcp->tries * 2000 : 20 * 1000;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+   LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_renew(): set request timeout %"U16_F" msecs\n", msecs));
+  return result;
+}
+
+/**
+ * Rebind with a DHCP server for an existing DHCP lease.
+ *
+ * @param netif network interface which must rebind with a DHCP server
+ */
+static err_t dhcp_rebind(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result;
+  u16_t msecs;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_rebind()\n"));
+  dhcp_set_state(dhcp, DHCP_REBINDING);
+
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_request(netif);
+  if (result == ERR_OK)
+  {
+
+    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+    dhcp_option_byte(dhcp, DHCP_REQUEST);
+
+    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
+    dhcp_option_short(dhcp, 576);
+
+#if 0
+    dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4);
+    dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr));
+
+    dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4);
+    dhcp_option_long(dhcp, ntohl(dhcp->server_ip_addr.addr));
+#endif
+
+    dhcp_option_trailer(dhcp);
+
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+    /* set remote IP association to any DHCP server */
+    udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
+    udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT);
+    /* broadcast to server */
+    udp_sendto(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT);
+    dhcp_delete_request(netif);
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_rebind: REBINDING\n"));
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_rebind: could not allocate DHCP request\n"));
+  }
+  dhcp->tries++;
+  msecs = dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+   LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_rebind(): set request timeout %"U16_F" msecs\n", msecs));
+  return result;
+}
+
+/**
+ * Release a DHCP lease.
+ *
+ * @param netif network interface which must release its lease
+ */
+err_t dhcp_release(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  err_t result;
+  u16_t msecs;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_release()\n"));
+
+  /* idle DHCP client */
+  dhcp_set_state(dhcp, DHCP_OFF);
+  /* clean old DHCP offer */
+  dhcp->server_ip_addr.addr = 0;
+  dhcp->offered_ip_addr.addr = dhcp->offered_sn_mask.addr = 0;
+  dhcp->offered_gw_addr.addr = dhcp->offered_bc_addr.addr = 0;
+  dhcp->offered_t0_lease = dhcp->offered_t1_renew = dhcp->offered_t2_rebind = 0;
+  dhcp->dns_count = 0;
+  
+  /* create and initialize the DHCP message header */
+  result = dhcp_create_request(netif);
+  if (result == ERR_OK) {
+    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
+    dhcp_option_byte(dhcp, DHCP_RELEASE);
+
+    dhcp_option_trailer(dhcp);
+
+    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
+
+    udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
+    udp_connect(dhcp->pcb, &dhcp->server_ip_addr, DHCP_SERVER_PORT);
+    udp_send(dhcp->pcb, dhcp->p_out);
+    dhcp_delete_request(netif);
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_release: RELEASED, DHCP_OFF\n"));
+  } else {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_release: could not allocate DHCP request\n"));
+  }
+  dhcp->tries++;
+  msecs = dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000;
+  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_release(): set request timeout %"U16_F" msecs\n", msecs));
+  /* bring the interface down */
+  netif_set_down(netif);
+  /* remove IP address from interface */
+  netif_set_ipaddr(netif, IP_ADDR_ANY);
+  netif_set_gw(netif, IP_ADDR_ANY);
+  netif_set_netmask(netif, IP_ADDR_ANY);
+  
+  /* TODO: netif_down(netif); */
+  return result;
+}
+/**
+ * Remove the DHCP client from the interface.
+ *
+ * @param netif The network interface to stop DHCP on
+ */
+void dhcp_stop(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  LWIP_ASSERT("dhcp_stop: netif != NULL", netif != NULL);
+
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_stop()\n"));
+  /* netif is DHCP configured? */
+  if (dhcp != NULL)
+  {
+    if (dhcp->pcb != NULL)
+    {
+      udp_remove(dhcp->pcb);
+      dhcp->pcb = NULL;
+    }
+    if (dhcp->p != NULL)
+    {
+      pbuf_free(dhcp->p);
+      dhcp->p = NULL;
+    }
+    /* free unfolded reply */
+    dhcp_free_reply(dhcp);
+    mem_free((void *)dhcp);
+    netif->dhcp = NULL;
+  }
+}
+
+/*
+ * Set the DHCP state of a DHCP client.
+ *
+ * If the state changed, reset the number of tries.
+ *
+ * TODO: we might also want to reset the timeout here?
+ */
+static void dhcp_set_state(struct dhcp *dhcp, u8_t new_state)
+{
+  if (new_state != dhcp->state)
+  {
+    dhcp->state = new_state;
+    dhcp->tries = 0;
+  }
+}
+
+/*
+ * Concatenate an option type and length field to the outgoing
+ * DHCP message.
+ *
+ */
+static void dhcp_option(struct dhcp *dhcp, u8_t option_type, u8_t option_len)
+{
+  LWIP_ASSERT("dhcp_option_short: dhcp->options_out_len + 2 + option_len <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 2 + option_len <= DHCP_OPTIONS_LEN);
+  dhcp->msg_out->options[dhcp->options_out_len++] = option_type;
+  dhcp->msg_out->options[dhcp->options_out_len++] = option_len;
+}
+/*
+ * Concatenate a single byte to the outgoing DHCP message.
+ *
+ */
+static void dhcp_option_byte(struct dhcp *dhcp, u8_t value)
+{
+  LWIP_ASSERT("dhcp_option_short: dhcp->options_out_len < DHCP_OPTIONS_LEN", dhcp->options_out_len < DHCP_OPTIONS_LEN);
+  dhcp->msg_out->options[dhcp->options_out_len++] = value;
+}
+static void dhcp_option_short(struct dhcp *dhcp, u16_t value)
+{
+  LWIP_ASSERT("dhcp_option_short: dhcp->options_out_len + 2 <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 2 <= DHCP_OPTIONS_LEN);
+  dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0xff00U) >> 8;
+  dhcp->msg_out->options[dhcp->options_out_len++] =  value & 0x00ffU;
+}
+static void dhcp_option_long(struct dhcp *dhcp, u32_t value)
+{
+  LWIP_ASSERT("dhcp_option_long: dhcp->options_out_len + 4 <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 4 <= DHCP_OPTIONS_LEN);
+  dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0xff000000UL) >> 24;
+  dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0x00ff0000UL) >> 16;
+  dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0x0000ff00UL) >> 8;
+  dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0x000000ffUL);
+}
+
+/**
+ * Extract the DHCP message and the DHCP options.
+ *
+ * Extract the DHCP message and the DHCP options, each into a contiguous
+ * piece of memory. As a DHCP message is variable sized by its options,
+ * and also allows overriding some fields for options, the easy approach
+ * is to first unfold the options into a conitguous piece of memory, and
+ * use that further on.
+ *
+ */
+static err_t dhcp_unfold_reply(struct dhcp *dhcp)
+{
+  struct pbuf *p = dhcp->p;
+  u8_t *ptr;
+  u16_t i;
+  u16_t j = 0;
+  LWIP_ASSERT("dhcp->p != NULL", dhcp->p != NULL);
+  /* free any left-overs from previous unfolds */
+  dhcp_free_reply(dhcp);
+  /* options present? */
+  if (dhcp->p->tot_len > (sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN))
+  {
+    dhcp->options_in_len = dhcp->p->tot_len - (sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN);
+    dhcp->options_in = mem_malloc(dhcp->options_in_len);
+    if (dhcp->options_in == NULL)
+    {
+      LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_unfold_reply(): could not allocate dhcp->options\n"));
+      return ERR_MEM;
+    }
+  }
+  dhcp->msg_in = mem_malloc(sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN);
+  if (dhcp->msg_in == NULL)
+  {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_unfold_reply(): could not allocate dhcp->msg_in\n"));
+    mem_free((void *)dhcp->options_in);
+    dhcp->options_in = NULL;
+    return ERR_MEM;
+  }
+
+  ptr = (u8_t *)dhcp->msg_in;
+  /* proceed through struct dhcp_msg */
+  for (i = 0; i < sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN; i++)
+  {
+    *ptr++ = ((u8_t *)p->payload)[j++];
+    /* reached end of pbuf? */
+    if (j == p->len)
+    {
+      /* proceed to next pbuf in chain */
+      p = p->next;
+      j = 0;
+    }
+  }
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_unfold_reply(): copied %"U16_F" bytes into dhcp->msg_in[]\n", i));
+  if (dhcp->options_in != NULL) {
+    ptr = (u8_t *)dhcp->options_in;
+    /* proceed through options */
+    for (i = 0; i < dhcp->options_in_len; i++) {
+      *ptr++ = ((u8_t *)p->payload)[j++];
+      /* reached end of pbuf? */
+      if (j == p->len) {
+        /* proceed to next pbuf in chain */
+        p = p->next;
+        j = 0;
+      }
+    }
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_unfold_reply(): copied %"U16_F" bytes to dhcp->options_in[]\n", i));
+  }
+  return ERR_OK;
+}
+
+/**
+ * Free the incoming DHCP message including contiguous copy of
+ * its DHCP options.
+ *
+ */
+static void dhcp_free_reply(struct dhcp *dhcp)
+{
+  if (dhcp->msg_in != NULL) {
+    mem_free((void *)dhcp->msg_in);
+    dhcp->msg_in = NULL;
+  }
+  if (dhcp->options_in) {
+    mem_free((void *)dhcp->options_in);
+    dhcp->options_in = NULL;
+    dhcp->options_in_len = 0;
+  }
+  LWIP_DEBUGF(DHCP_DEBUG, ("dhcp_free_reply(): free'd\n"));
+}
+
+
+/**
+ * If an incoming DHCP message is in response to us, then trigger the state machine
+ */
+static void dhcp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *addr, u16_t port)
+{
+  struct netif *netif = (struct netif *)arg;
+  struct dhcp *dhcp = netif->dhcp;
+  struct dhcp_msg *reply_msg = (struct dhcp_msg *)p->payload;
+  u8_t *options_ptr;
+  u8_t msg_type;
+  u8_t i;
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_recv(pbuf = %p) from DHCP server %"U16_F".%"U16_F".%"U16_F".%"U16_F" port %"U16_F"\n", (void*)p,
+    (u16_t)(ntohl(addr->addr) >> 24 & 0xff), (u16_t)(ntohl(addr->addr) >> 16 & 0xff),
+    (u16_t)(ntohl(addr->addr) >>  8 & 0xff), (u16_t)(ntohl(addr->addr) & 0xff), port));
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("pbuf->len = %"U16_F"\n", p->len));
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("pbuf->tot_len = %"U16_F"\n", p->tot_len));
+  /* prevent warnings about unused arguments */
+  (void)pcb; (void)addr; (void)port;
+  dhcp->p = p;
+  /* TODO: check packet length before reading them */
+  if (reply_msg->op != DHCP_BOOTREPLY) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("not a DHCP reply message, but type %"U16_F"\n", (u16_t)reply_msg->op));
+    pbuf_free(p);
+    dhcp->p = NULL;
+    return;
+  }
+  /* iterate through hardware address and match against DHCP message */
+  for (i = 0; i < netif->hwaddr_len; i++) {
+    if (netif->hwaddr[i] != reply_msg->chaddr[i]) {
+      LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("netif->hwaddr[%"U16_F"]==%02"X16_F" != reply_msg->chaddr[%"U16_F"]==%02"X16_F"\n",
+        (u16_t)i, (u16_t)netif->hwaddr[i], (u16_t)i, (u16_t)reply_msg->chaddr[i]));
+      pbuf_free(p);
+      dhcp->p = NULL;
+      return;
+    }
+  }
+  /* match transaction ID against what we expected */
+  if (ntohl(reply_msg->xid) != dhcp->xid) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("transaction id mismatch\n"));
+    pbuf_free(p);
+    dhcp->p = NULL;
+    return;
+  }
+  /* option fields could be unfold? */
+  if (dhcp_unfold_reply(dhcp) != ERR_OK) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("problem unfolding DHCP message - too short on memory?\n"));
+    pbuf_free(p);
+    dhcp->p = NULL;
+    return;
+  }
+
+  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("searching DHCP_OPTION_MESSAGE_TYPE\n"));
+  /* obtain pointer to DHCP message type */
+  options_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_MESSAGE_TYPE);
+  if (options_ptr == NULL) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("DHCP_OPTION_MESSAGE_TYPE option not found\n"));
+    pbuf_free(p);
+    dhcp->p = NULL;
+    return;
+  }
+
+  /* read DHCP message type */
+  msg_type = dhcp_get_option_byte(options_ptr + 2);
+  /* message type is DHCP ACK? */
+  if (msg_type == DHCP_ACK) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("DHCP_ACK received\n"));
+    /* in requesting state? */
+    if (dhcp->state == DHCP_REQUESTING) {
+      dhcp_handle_ack(netif);
+      dhcp->request_timeout = 0;
+#if DHCP_DOES_ARP_CHECK
+      /* check if the acknowledged lease address is already in use */
+      dhcp_check(netif);
+#else
+      /* bind interface to the acknowledged lease address */
+      dhcp_bind(netif);
+#endif
+    }
+    /* already bound to the given lease address? */
+    else if ((dhcp->state == DHCP_REBOOTING) || (dhcp->state == DHCP_REBINDING) || (dhcp->state == DHCP_RENEWING)) {
+      dhcp->request_timeout = 0;
+      dhcp_bind(netif);
+    }
+  }
+  /* received a DHCP_NAK in appropriate state? */
+  else if ((msg_type == DHCP_NAK) &&
+    ((dhcp->state == DHCP_REBOOTING) || (dhcp->state == DHCP_REQUESTING) ||
+     (dhcp->state == DHCP_REBINDING) || (dhcp->state == DHCP_RENEWING  ))) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("DHCP_NAK received\n"));
+    dhcp->request_timeout = 0;
+    dhcp_handle_nak(netif);
+  }
+  /* received a DHCP_OFFER in DHCP_SELECTING state? */
+  else if ((msg_type == DHCP_OFFER) && (dhcp->state == DHCP_SELECTING)) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("DHCP_OFFER received in DHCP_SELECTING state\n"));
+    dhcp->request_timeout = 0;
+    /* remember offered lease */
+    dhcp_handle_offer(netif);
+  }
+  pbuf_free(p);
+  dhcp->p = NULL;
+}
+
+
+static err_t dhcp_create_request(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  u16_t i;
+  LWIP_ASSERT("dhcp_create_request: dhcp->p_out == NULL", dhcp->p_out == NULL);
+  LWIP_ASSERT("dhcp_create_request: dhcp->msg_out == NULL", dhcp->msg_out == NULL);
+  dhcp->p_out = pbuf_alloc(PBUF_TRANSPORT, sizeof(struct dhcp_msg), PBUF_RAM);
+  if (dhcp->p_out == NULL) {
+    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_create_request(): could not allocate pbuf\n"));
+    return ERR_MEM;
+  }
+  /* give unique transaction identifier to this request */
+  dhcp->xid = xid++;
+
+  dhcp->msg_out = (struct dhcp_msg *)dhcp->p_out->payload;
+
+  dhcp->msg_out->op = DHCP_BOOTREQUEST;
+  /* TODO: make link layer independent */
+  dhcp->msg_out->htype = DHCP_HTYPE_ETH;
+  /* TODO: make link layer independent */
+  dhcp->msg_out->hlen = DHCP_HLEN_ETH;
+  dhcp->msg_out->hops = 0;
+  dhcp->msg_out->xid = htonl(dhcp->xid);
+  dhcp->msg_out->secs = 0;
+  dhcp->msg_out->flags = 0;
+  dhcp->msg_out->ciaddr.addr = netif->ip_addr.addr;
+  dhcp->msg_out->yiaddr.addr = 0;
+  dhcp->msg_out->siaddr.addr = 0;
+  dhcp->msg_out->giaddr.addr = 0;
+  for (i = 0; i < DHCP_CHADDR_LEN; i++) {
+    /* copy netif hardware address, pad with zeroes */
+    dhcp->msg_out->chaddr[i] = (i < netif->hwaddr_len) ? netif->hwaddr[i] : 0/* pad byte*/;
+  }
+  for (i = 0; i < DHCP_SNAME_LEN; i++) dhcp->msg_out->sname[i] = 0;
+  for (i = 0; i < DHCP_FILE_LEN; i++) dhcp->msg_out->file[i] = 0;
+  dhcp->msg_out->cookie = htonl(0x63825363UL);
+  dhcp->options_out_len = 0;
+  /* fill options field with an incrementing array (for debugging purposes) */
+  for (i = 0; i < DHCP_OPTIONS_LEN; i++) dhcp->msg_out->options[i] = i;
+  return ERR_OK;
+}
+
+static void dhcp_delete_request(struct netif *netif)
+{
+  struct dhcp *dhcp = netif->dhcp;
+  LWIP_ASSERT("dhcp_free_msg: dhcp->p_out != NULL", dhcp->p_out != NULL);
+  LWIP_ASSERT("dhcp_free_msg: dhcp->msg_out != NULL", dhcp->msg_out != NULL);
+  pbuf_free(dhcp->p_out);
+  dhcp->p_out = NULL;
+  dhcp->msg_out = NULL;
+}
+
+/**
+ * Add a DHCP message trailer
+ *
+ * Adds the END option to the DHCP message, and if
+ * necessary, up to three padding bytes.
+ */
+
+static void dhcp_option_trailer(struct dhcp *dhcp)
+{
+  LWIP_ASSERT("dhcp_option_trailer: dhcp->msg_out != NULL\n", dhcp->msg_out != NULL);
+  LWIP_ASSERT("dhcp_option_trailer: dhcp->options_out_len < DHCP_OPTIONS_LEN\n", dhcp->options_out_len < DHCP_OPTIONS_LEN);
+  dhcp->msg_out->options[dhcp->options_out_len++] = DHCP_OPTION_END;
+  /* packet is too small, or not 4 byte aligned? */
+  while ((dhcp->options_out_len < DHCP_MIN_OPTIONS_LEN) || (dhcp->options_out_len & 3)) {
+    /* LWIP_DEBUGF(DHCP_DEBUG,("dhcp_option_trailer:dhcp->options_out_len=%"U16_F", DHCP_OPTIONS_LEN=%"U16_F, dhcp->options_out_len, DHCP_OPTIONS_LEN)); */
+    LWIP_ASSERT("dhcp_option_trailer: dhcp->options_out_len < DHCP_OPTIONS_LEN\n", dhcp->options_out_len < DHCP_OPTIONS_LEN);
+    /* add a fill/padding byte */
+    dhcp->msg_out->options[dhcp->options_out_len++] = 0;
+  }
+}
+
+/**
+ * Find the offset of a DHCP option inside the DHCP message.
+ *
+ * @param client DHCP client
+ * @param option_type
+ *
+ * @return a byte offset into the UDP message where the option was found, or
+ * zero if the given option was not found.
+ */
+static u8_t *dhcp_get_option_ptr(struct dhcp *dhcp, u8_t option_type)
+{
+  u8_t overload = DHCP_OVERLOAD_NONE;
+
+  /* options available? */
+  if ((dhcp->options_in != NULL) && (dhcp->options_in_len > 0)) {
+    /* start with options field */
+    u8_t *options = (u8_t *)dhcp->options_in;
+    u16_t offset = 0;
+    /* at least 1 byte to read and no end marker, then at least 3 bytes to read? */
+    while ((offset < dhcp->options_in_len) && (options[offset] != DHCP_OPTION_END)) {
+      /* LWIP_DEBUGF(DHCP_DEBUG, ("msg_offset=%"U16_F", q->len=%"U16_F, msg_offset, q->len)); */
+      /* are the sname and/or file field overloaded with options? */
+      if (options[offset] == DHCP_OPTION_OVERLOAD) {
+        LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("overloaded message detected\n"));
+        /* skip option type and length */
+        offset += 2;
+        overload = options[offset++];
+      }
+      /* requested option found */
+      else if (options[offset] == option_type) {
+        LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("option found at offset %"U16_F" in options\n", offset));
+        return &options[offset];
+      /* skip option */
+      } else {
+         LWIP_DEBUGF(DHCP_DEBUG, ("skipping option %"U16_F" in options\n", options[offset]));
+        /* skip option type */
+        offset++;
+        /* skip option length, and then length bytes */
+        offset += 1 + options[offset];
+      }
+    }
+    /* is this an overloaded message? */
+    if (overload != DHCP_OVERLOAD_NONE) {
+      u16_t field_len;
+      if (overload == DHCP_OVERLOAD_FILE) {
+        LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("overloaded file field\n"));
+        options = (u8_t *)&dhcp->msg_in->file;
+        field_len = DHCP_FILE_LEN;
+      } else if (overload == DHCP_OVERLOAD_SNAME) {
+        LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("overloaded sname field\n"));
+        options = (u8_t *)&dhcp->msg_in->sname;
+        field_len = DHCP_SNAME_LEN;
+      /* TODO: check if else if () is necessary */
+      } else {
+        LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("overloaded sname and file field\n"));
+        options = (u8_t *)&dhcp->msg_in->sname;
+        field_len = DHCP_FILE_LEN + DHCP_SNAME_LEN;
+      }
+      offset = 0;
+
+      /* at least 1 byte to read and no end marker */
+      while ((offset < field_len) && (options[offset] != DHCP_OPTION_END)) {
+        if (options[offset] == option_type) {
+           LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("option found at offset=%"U16_F"\n", offset));
+          return &options[offset];
+        /* skip option */
+        } else {
+          LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("skipping option %"U16_F"\n", options[offset]));
+          /* skip option type */
+          offset++;
+          offset += 1 + options[offset];
+        }
+      }
+    }
+  }
+  return 0;
+}
+
+/**
+ * Return the byte of DHCP option data.
+ *
+ * @param client DHCP client.
+ * @param ptr pointer obtained by dhcp_get_option_ptr().
+ *
+ * @return byte value at the given address.
+ */
+static u8_t dhcp_get_option_byte(u8_t *ptr)
+{
+  LWIP_DEBUGF(DHCP_DEBUG, ("option byte value=%"U16_F"\n", (u16_t)(*ptr)));
+  return *ptr;
+}
+
+/**
+ * Return the 16-bit value of DHCP option data.
+ *
+ * @param client DHCP client.
+ * @param ptr pointer obtained by dhcp_get_option_ptr().
+ *
+ * @return byte value at the given address.
+ */
+static u16_t dhcp_get_option_short(u8_t *ptr)
+{
+  u16_t value;
+  value = *ptr++ << 8;
+  value |= *ptr;
+  LWIP_DEBUGF(DHCP_DEBUG, ("option short value=%"U16_F"\n", value));
+  return value;
+}
+
+/**
+ * Return the 32-bit value of DHCP option data.
+ *
+ * @param client DHCP client.
+ * @param ptr pointer obtained by dhcp_get_option_ptr().
+ *
+ * @return byte value at the given address.
+ */
+static u32_t dhcp_get_option_long(u8_t *ptr)
+{
+  u32_t value;
+  value = (u32_t)(*ptr++) << 24;
+  value |= (u32_t)(*ptr++) << 16;
+  value |= (u32_t)(*ptr++) << 8;
+  value |= (u32_t)(*ptr++);
+  LWIP_DEBUGF(DHCP_DEBUG, ("option long value=%"U32_F"\n", value));
+  return value;
+}
+
+#endif /* LWIP_DHCP */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/inet.c b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/inet.c
new file mode 100644
index 000000000..baeee51c3
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/inet.c
@@ -0,0 +1,525 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+
+/* inet.c
+ *
+ * Functions common to all TCP/IP modules, such as the Internet checksum and the
+ * byte order functions.
+ *
+ */
+
+
+#include "lwip/opt.h"
+
+#include "lwip/arch.h"
+
+#include "lwip/def.h"
+#include "lwip/inet.h"
+
+#include "lwip/sys.h"
+
+/* This is a reference implementation of the checksum algorithm, with the
+ * aim of being simple, correct and fully portable. Checksumming is the
+ * first thing you would want to optimize for your platform. You will
+ * need to port it to your architecture and in your sys_arch.h:
+ * 
+ * #define LWIP_CHKSUM  
+*/
+#ifndef LWIP_CHKSUM
+#define LWIP_CHKSUM lwip_standard_chksum
+
+/**
+ * lwip checksum
+ *
+ * @param dataptr points to start of data to be summed at any boundary
+ * @param len length of data to be summed
+ * @return host order (!) lwip checksum (non-inverted Internet sum) 
+ *
+ * @note accumulator size limits summable lenght to 64k
+ * @note host endianess is irrelevant (p3 RFC1071)
+ */
+static u16_t
+lwip_standard_chksum(void *dataptr, u16_t len)
+{
+  u32_t acc;
+  u16_t src;
+  u8_t *octetptr;
+
+  acc = 0;
+  /* dataptr may be at odd or even addresses */
+  octetptr = (u8_t*)dataptr;
+  while (len > 1)
+  {
+    /* declare first octet as most significant
+       thus assume network order, ignoring host order */
+    src = (*octetptr) << 8;
+    octetptr++;
+    /* declare second octet as least significant */
+    src |= (*octetptr);
+    octetptr++;
+    acc += src;
+    len -= 2;
+  }
+  if (len > 0)
+  {
+    /* accumulate remaining octet */
+    src = (*octetptr) << 8;
+    acc += src;
+  }
+  /* add deferred carry bits */
+  acc = (acc >> 16) + (acc & 0x0000ffffUL);
+  if ((acc & 0xffff0000) != 0) {
+    acc = (acc >> 16) + (acc & 0x0000ffffUL);
+  }
+  /* This maybe a little confusing: reorder sum using htons()
+     instead of ntohs() since it has a little less call overhead.
+     The caller must invert bits for Internet sum ! */
+  return htons((u16_t)acc);
+}
+
+#endif
+
+#if 0
+/*
+ * Curt McDowell
+ * Broadcom Corp.
+ * csm@broadcom.com
+ *
+ * IP checksum two bytes at a time with support for
+ * unaligned buffer.
+ * Works for len up to and including 0x20000.
+ * by Curt McDowell, Broadcom Corp. 12/08/2005
+ */
+
+static u16_t
+lwip_standard_chksum2(void *dataptr, int len)
+{
+  u8_t *pb = dataptr;
+  u16_t *ps, t = 0;
+  u32_t sum = 0;
+  int odd = ((u32_t)pb & 1);
+
+  /* Get aligned to u16_t */
+  if (odd && len > 0) {
+    ((u8_t *)&t)[1] = *pb++;
+    len--;
+  }
+
+  /* Add the bulk of the data */
+  ps = (u16_t *)pb;
+  while (len > 1) {
+    sum += *ps++;
+    len -= 2;
+  }
+
+  /* Consume left-over byte, if any */
+  if (len > 0)
+    ((u8_t *)&t)[0] = *(u8_t *)ps;;
+
+  /* Add end bytes */
+  sum += t;
+
+  /*  Fold 32-bit sum to 16 bits */
+  while (sum >> 16)
+    sum = (sum & 0xffff) + (sum >> 16);
+
+  /* Swap if alignment was odd */
+  if (odd)
+    sum = ((sum & 0xff) << 8) | ((sum & 0xff00) >> 8);
+
+  return sum;
+}
+
+/**
+ * An optimized checksum routine. Basically, it uses loop-unrolling on
+ * the checksum loop, treating the head and tail bytes specially, whereas
+ * the inner loop acts on 8 bytes at a time. 
+ *
+ * @arg start of buffer to be checksummed. May be an odd byte address.
+ * @len number of bytes in the buffer to be checksummed.
+ * 
+ * @todo First argument type conflicts with generic checksum routine.
+ * 
+ * by Curt McDowell, Broadcom Corp. December 8th, 2005
+ */
+
+static u16_t
+lwip_standard_chksum4(u8_t *pb, int len)
+{
+  u16_t *ps, t = 0;
+  u32_t *pl;
+  u32_t sum = 0, tmp;
+  /* starts at odd byte address? */
+  int odd = ((u32_t)pb & 1);
+
+  if (odd && len > 0) {
+    ((u8_t *)&t)[1] = *pb++;
+    len--;
+  }
+
+  ps = (u16_t *)pb;
+
+  if (((u32_t)ps & 3) && len > 1) {
+    sum += *ps++;
+    len -= 2;
+  }
+
+  pl = (u32_t *)ps;
+
+  while (len > 7)  {
+    tmp = sum + *pl++;          /* ping */
+    if (tmp < sum)
+      tmp++;                    /* add back carry */
+
+    sum = tmp + *pl++;          /* pong */
+    if (sum < tmp)
+      sum++;                    /* add back carry */
+
+    len -= 8;
+  }
+
+  /* make room in upper bits */
+  sum = (sum >> 16) + (sum & 0xffff);
+
+  ps = (u16_t *)pl;
+
+  /* 16-bit aligned word remaining? */
+  while (len > 1) {
+    sum += *ps++;
+    len -= 2;
+  }
+
+  /* dangling tail byte remaining? */
+  if (len > 0)                  /* include odd byte */
+    ((u8_t *)&t)[0] = *(u8_t *)ps;
+
+  sum += t;                     /* add end bytes */
+
+  while (sum >> 16)             /* combine halves */
+    sum = (sum >> 16) + (sum & 0xffff);
+
+  if (odd)
+    sum = ((sum & 0xff) << 8) | ((sum & 0xff00) >> 8);
+
+  return sum;
+}
+#endif
+
+/* inet_chksum_pseudo:
+ *
+ * Calculates the pseudo Internet checksum used by TCP and UDP for a pbuf chain.
+ */
+
+u16_t
+inet_chksum_pseudo(struct pbuf *p,
+       struct ip_addr *src, struct ip_addr *dest,
+       u8_t proto, u16_t proto_len)
+{
+  u32_t acc;
+  struct pbuf *q;
+  u8_t swapped;
+
+  acc = 0;
+  swapped = 0;
+  /* iterate through all pbuf in chain */
+  for(q = p; q != NULL; q = q->next) {
+    LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): checksumming pbuf %p (has next %p) \n",
+      (void *)q, (void *)q->next));
+    acc += LWIP_CHKSUM(q->payload, q->len);
+    /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): unwrapped lwip_chksum()=%"X32_F" \n", acc));*/
+    while (acc >> 16) {
+      acc = (acc & 0xffffUL) + (acc >> 16);
+    }
+    if (q->len % 2 != 0) {
+      swapped = 1 - swapped;
+      acc = ((acc & 0xff) << 8) | ((acc & 0xff00UL) >> 8);
+    }
+    /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): wrapped lwip_chksum()=%"X32_F" \n", acc));*/
+  }
+
+  if (swapped) {
+    acc = ((acc & 0xff) << 8) | ((acc & 0xff00UL) >> 8);
+  }
+  acc += (src->addr & 0xffffUL);
+  acc += ((src->addr >> 16) & 0xffffUL);
+  acc += (dest->addr & 0xffffUL);
+  acc += ((dest->addr >> 16) & 0xffffUL);
+  acc += (u32_t)htons((u16_t)proto);
+  acc += (u32_t)htons(proto_len);
+
+  while (acc >> 16) {
+    acc = (acc & 0xffffUL) + (acc >> 16);
+  }
+  LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): pbuf chain lwip_chksum()=%"X32_F"\n", acc));
+  return (u16_t)~(acc & 0xffffUL);
+}
+
+/* inet_chksum:
+ *
+ * Calculates the Internet checksum over a portion of memory. Used primarely for IP
+ * and ICMP.
+ */
+
+u16_t
+inet_chksum(void *dataptr, u16_t len)
+{
+  u32_t acc;
+
+  acc = LWIP_CHKSUM(dataptr, len);
+  while (acc >> 16) {
+    acc = (acc & 0xffff) + (acc >> 16);
+  }
+  return (u16_t)~(acc & 0xffff);
+}
+
+u16_t
+inet_chksum_pbuf(struct pbuf *p)
+{
+  u32_t acc;
+  struct pbuf *q;
+  u8_t swapped;
+
+  acc = 0;
+  swapped = 0;
+  for(q = p; q != NULL; q = q->next) {
+    acc += LWIP_CHKSUM(q->payload, q->len);
+    while (acc >> 16) {
+      acc = (acc & 0xffffUL) + (acc >> 16);
+    }
+    if (q->len % 2 != 0) {
+      swapped = 1 - swapped;
+      acc = (acc & 0x00ffUL << 8) | (acc & 0xff00UL >> 8);
+    }
+  }
+
+  if (swapped) {
+    acc = ((acc & 0x00ffUL) << 8) | ((acc & 0xff00UL) >> 8);
+  }
+  return (u16_t)~(acc & 0xffffUL);
+}
+
+/* Here for now until needed in other places in lwIP */
+#ifndef isascii
+#define in_range(c, lo, up)  ((u8_t)c >= lo && (u8_t)c <= up)
+#define isascii(c)           in_range(c, 0x20, 0x7f)
+#define isdigit(c)           in_range(c, '0', '9')
+#define isxdigit(c)          (isdigit(c) || in_range(c, 'a', 'f') || in_range(c, 'A', 'F'))
+#define islower(c)           in_range(c, 'a', 'z')
+#define isspace(c)           (c == ' ' || c == '\f' || c == '\n' || c == '\r' || c == '\t' || c == '\v')
+#endif		
+		
+
+ /*
+  * Ascii internet address interpretation routine.
+  * The value returned is in network order.
+  */
+
+ /*  */
+ /* inet_addr */
+ u32_t inet_addr(const char *cp)
+ {
+     struct in_addr val;
+
+     if (inet_aton(cp, &val)) {
+         return (val.s_addr);
+     }
+     return (INADDR_NONE);
+ }
+
+ /*
+  * Check whether "cp" is a valid ascii representation
+  * of an Internet address and convert to a binary address.
+  * Returns 1 if the address is valid, 0 if not.
+  * This replaces inet_addr, the return value from which
+  * cannot distinguish between failure and a local broadcast address.
+  */
+ /*  */
+ /* inet_aton */
+ s8_t
+ inet_aton(const char *cp, struct in_addr *addr)
+ {
+     u32_t val;
+     s32_t base, n;
+     char c;
+     u32_t parts[4];
+     u32_t* pp = parts;
+
+     c = *cp;
+     for (;;) {
+         /*
+          * Collect number up to ``.''.
+          * Values are specified as for C:
+          * 0x=hex, 0=octal, isdigit=decimal.
+          */
+         if (!isdigit(c))
+             return (0);
+         val = 0; base = 10;
+         if (c == '0') {
+             c = *++cp;
+             if (c == 'x' || c == 'X')
+                 base = 16, c = *++cp;
+             else
+                 base = 8;
+         }
+         for (;;) {
+             if (isdigit(c)) {
+                 val = (val * base) + (s16_t)(c - '0');
+                 c = *++cp;
+             } else if (base == 16 && isxdigit(c)) {
+                 val = (val << 4) |
+                     (s16_t)(c + 10 - (islower(c) ? 'a' : 'A'));
+                 c = *++cp;
+             } else
+             break;
+         }
+         if (c == '.') {
+             /*
+              * Internet format:
+              *  a.b.c.d
+              *  a.b.c   (with c treated as 16 bits)
+              *  a.b (with b treated as 24 bits)
+              */
+             if (pp >= parts + 3)
+                 return (0);
+             *pp++ = val;
+             c = *++cp;
+         } else
+             break;
+     }
+     /*
+      * Check for trailing characters.
+      */
+     if (c != '\0' && (!isascii(c) || !isspace(c)))
+         return (0);
+     /*
+      * Concoct the address according to
+      * the number of parts specified.
+      */
+     n = pp - parts + 1;
+     switch (n) {
+
+     case 0:
+         return (0);     /* initial nondigit */
+
+     case 1:             /* a -- 32 bits */
+         break;
+
+     case 2:             /* a.b -- 8.24 bits */
+         if (val > 0xffffff)
+             return (0);
+         val |= parts[0] << 24;
+         break;
+
+     case 3:             /* a.b.c -- 8.8.16 bits */
+         if (val > 0xffff)
+             return (0);
+         val |= (parts[0] << 24) | (parts[1] << 16);
+         break;
+
+     case 4:             /* a.b.c.d -- 8.8.8.8 bits */
+         if (val > 0xff)
+             return (0);
+         val |= (parts[0] << 24) | (parts[1] << 16) | (parts[2] << 8);
+         break;
+     }
+     if (addr)
+         addr->s_addr = htonl(val);
+     return (1);
+ }
+
+/* Convert numeric IP address into decimal dotted ASCII representation.
+ * returns ptr to static buffer; not reentrant!
+ */
+char *inet_ntoa(struct in_addr addr)
+{
+  static char str[16];
+  u32_t s_addr = addr.s_addr;
+  char inv[3];
+  char *rp;
+  u8_t *ap;
+  u8_t rem;
+  u8_t n;
+  u8_t i;
+
+  rp = str;
+  ap = (u8_t *)&s_addr;
+  for(n = 0; n < 4; n++) {
+    i = 0;
+    do {
+      rem = *ap % (u8_t)10;
+      *ap /= (u8_t)10;
+      inv[i++] = '0' + rem;
+    } while(*ap);
+    while(i--)
+      *rp++ = inv[i];
+    *rp++ = '.';
+    ap++;
+  }
+  *--rp = 0;
+  return str;
+}
+
+
+#ifndef BYTE_ORDER
+#error BYTE_ORDER is not defined
+#endif
+#if BYTE_ORDER == LITTLE_ENDIAN
+
+u16_t
+htons(u16_t n)
+{
+  return ((n & 0xff) << 8) | ((n & 0xff00) >> 8);
+}
+
+u16_t
+ntohs(u16_t n)
+{
+  return htons(n);
+}
+
+u32_t
+htonl(u32_t n)
+{
+  return ((n & 0xff) << 24) |
+    ((n & 0xff00) << 8) |
+    ((n & 0xff0000) >> 8) |
+    ((n & 0xff000000) >> 24);
+}
+
+u32_t
+ntohl(u32_t n)
+{
+  return htonl(n);
+}
+
+#endif /* BYTE_ORDER == LITTLE_ENDIAN */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/inet6.c b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/inet6.c
new file mode 100644
index 000000000..aebc6f381
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/inet6.c
@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+
+/* inet6.c
+ *
+ * Functions common to all TCP/IP modules, such as the Internet checksum and the
+ * byte order functions.
+ *
+ */
+
+
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+#include "lwip/inet.h"
+
+
+
+/* chksum:
+ *
+ * Sums up all 16 bit words in a memory portion. Also includes any odd byte.
+ * This function is used by the other checksum functions.
+ *
+ * For now, this is not optimized. Must be optimized for the particular processor
+ * arcitecture on which it is to run. Preferebly coded in assembler.
+ */
+
+static u32_t
+chksum(void *dataptr, u16_t len)
+{
+  u16_t *sdataptr = dataptr;
+  u32_t acc;
+  
+  
+  for(acc = 0; len > 1; len -= 2) {
+    acc += *sdataptr++;
+  }
+
+  /* add up any odd byte */
+  if (len == 1) {
+    acc += htons((u16_t)(*(u8_t *)dataptr) << 8);
+  }
+
+  return acc;
+
+}
+
+/* inet_chksum_pseudo:
+ *
+ * Calculates the pseudo Internet checksum used by TCP and UDP for a pbuf chain.
+ */
+
+u16_t
+inet_chksum_pseudo(struct pbuf *p,
+       struct ip_addr *src, struct ip_addr *dest,
+       u8_t proto, u32_t proto_len)
+{
+  u32_t acc;
+  struct pbuf *q;
+  u8_t swapped, i;
+
+  acc = 0;
+  swapped = 0;
+  for(q = p; q != NULL; q = q->next) {    
+    acc += chksum(q->payload, q->len);
+    while (acc >> 16) {
+      acc = (acc & 0xffff) + (acc >> 16);
+    }
+    if (q->len % 2 != 0) {
+      swapped = 1 - swapped;
+      acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8);
+    }
+  }
+
+  if (swapped) {
+    acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8);
+  }
+  
+  for(i = 0; i < 8; i++) {
+    acc += ((u16_t *)src->addr)[i] & 0xffff;
+    acc += ((u16_t *)dest->addr)[i] & 0xffff;
+    while (acc >> 16) {
+      acc = (acc & 0xffff) + (acc >> 16);
+    }
+  }
+  acc += (u16_t)htons((u16_t)proto);
+  acc += ((u16_t *)&proto_len)[0] & 0xffff;
+  acc += ((u16_t *)&proto_len)[1] & 0xffff;
+
+  while (acc >> 16) {
+    acc = (acc & 0xffff) + (acc >> 16);
+  }
+  return ~(acc & 0xffff);
+}
+
+/* inet_chksum:
+ *
+ * Calculates the Internet checksum over a portion of memory. Used primarely for IP
+ * and ICMP.
+ */
+
+u16_t
+inet_chksum(void *dataptr, u16_t len)
+{
+  u32_t acc, sum;
+
+  acc = chksum(dataptr, len);
+  sum = (acc & 0xffff) + (acc >> 16);
+  sum += (sum >> 16);
+  return ~(sum & 0xffff);
+}
+
+u16_t
+inet_chksum_pbuf(struct pbuf *p)
+{
+  u32_t acc;
+  struct pbuf *q;
+  u8_t swapped;
+  
+  acc = 0;
+  swapped = 0;
+  for(q = p; q != NULL; q = q->next) {
+    acc += chksum(q->payload, q->len);
+    while (acc >> 16) {
+      acc = (acc & 0xffff) + (acc >> 16);
+    }    
+    if (q->len % 2 != 0) {
+      swapped = 1 - swapped;
+      acc = (acc & 0xff << 8) | (acc & 0xff00 >> 8);
+    }
+  }
+ 
+  if (swapped) {
+    acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8);
+  }
+  return ~(acc & 0xffff);
+}
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/ipv4/icmp.c b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/ipv4/icmp.c
new file mode 100644
index 000000000..c67ccbcf3
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/ipv4/icmp.c
@@ -0,0 +1,202 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+/* Some ICMP messages should be passed to the transport protocols. This
+   is not implemented. */
+
+#include 
+
+#include "lwip/opt.h"
+#include "lwip/icmp.h"
+#include "lwip/inet.h"
+#include "lwip/ip.h"
+#include "lwip/def.h"
+#include "lwip/stats.h"
+#include "lwip/snmp.h"
+
+void
+icmp_input(struct pbuf *p, struct netif *inp)
+{
+  u8_t type;
+  u8_t code;
+  struct icmp_echo_hdr *iecho;
+  struct ip_hdr *iphdr;
+  struct ip_addr tmpaddr;
+  u16_t hlen;
+
+  ICMP_STATS_INC(icmp.recv);
+  snmp_inc_icmpinmsgs();
+
+
+  iphdr = p->payload;
+  hlen = IPH_HL(iphdr) * 4;
+  if (pbuf_header(p, -((s16_t)hlen)) || (p->tot_len < sizeof(u16_t)*2)) {
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: short ICMP (%"U16_F" bytes) received\n", p->tot_len));
+    pbuf_free(p);
+    ICMP_STATS_INC(icmp.lenerr);
+    snmp_inc_icmpinerrors();
+    return;
+  }
+
+  type = *((u8_t *)p->payload);
+  code = *(((u8_t *)p->payload)+1);
+  switch (type) {
+  case ICMP_ECHO:
+    /* broadcast or multicast destination address? */
+    if (ip_addr_isbroadcast(&iphdr->dest, inp) || ip_addr_ismulticast(&iphdr->dest)) {
+      LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: Not echoing to multicast or broadcast pings\n"));
+      ICMP_STATS_INC(icmp.err);
+      pbuf_free(p);
+      return;
+    }
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ping\n"));
+    if (p->tot_len < sizeof(struct icmp_echo_hdr)) {
+      LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: bad ICMP echo received\n"));
+      pbuf_free(p);
+      ICMP_STATS_INC(icmp.lenerr);
+      snmp_inc_icmpinerrors();
+
+      return;
+    }
+    iecho = p->payload;
+    if (inet_chksum_pbuf(p) != 0) {
+      LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo\n"));
+      pbuf_free(p);
+      ICMP_STATS_INC(icmp.chkerr);
+      snmp_inc_icmpinerrors();
+      return;
+    }
+    tmpaddr.addr = iphdr->src.addr;
+    iphdr->src.addr = iphdr->dest.addr;
+    iphdr->dest.addr = tmpaddr.addr;
+    ICMPH_TYPE_SET(iecho, ICMP_ER);
+    /* adjust the checksum */
+    if (iecho->chksum >= htons(0xffff - (ICMP_ECHO << 8))) {
+      iecho->chksum += htons(ICMP_ECHO << 8) + 1;
+    } else {
+      iecho->chksum += htons(ICMP_ECHO << 8);
+    }
+    ICMP_STATS_INC(icmp.xmit);
+    /* increase number of messages attempted to send */
+    snmp_inc_icmpoutmsgs();
+    /* increase number of echo replies attempted to send */
+    snmp_inc_icmpoutechoreps();
+
+    pbuf_header(p, hlen);
+    ip_output_if(p, &(iphdr->src), IP_HDRINCL,
+		 IPH_TTL(iphdr), 0, IP_PROTO_ICMP, inp);
+    break;
+  default:
+  LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ICMP type %"S16_F" code %"S16_F" not supported.\n", (s16_t)type, (s16_t)code));
+    ICMP_STATS_INC(icmp.proterr);
+    ICMP_STATS_INC(icmp.drop);
+  }
+  pbuf_free(p);
+}
+
+void
+icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t)
+{
+  struct pbuf *q;
+  struct ip_hdr *iphdr;
+  struct icmp_dur_hdr *idur;
+
+  q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM);
+  /* ICMP header + IP header + 8 bytes of data */
+
+  iphdr = p->payload;
+
+  idur = q->payload;
+  ICMPH_TYPE_SET(idur, ICMP_DUR);
+  ICMPH_CODE_SET(idur, t);
+
+  memcpy((u8_t *)q->payload + 8, p->payload, IP_HLEN + 8);
+
+  /* calculate checksum */
+  idur->chksum = 0;
+  idur->chksum = inet_chksum(idur, q->len);
+  ICMP_STATS_INC(icmp.xmit);
+  /* increase number of messages attempted to send */
+  snmp_inc_icmpoutmsgs();
+  /* increase number of destination unreachable messages attempted to send */
+  snmp_inc_icmpoutdestunreachs();
+
+  ip_output(q, NULL, &(iphdr->src),
+	    ICMP_TTL, 0, IP_PROTO_ICMP);
+  pbuf_free(q);
+}
+
+#if IP_FORWARD
+void
+icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t)
+{
+  struct pbuf *q;
+  struct ip_hdr *iphdr;
+  struct icmp_te_hdr *tehdr;
+
+  q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM);
+
+  iphdr = p->payload;
+  LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded from "));
+  ip_addr_debug_print(ICMP_DEBUG, &(iphdr->src));
+  LWIP_DEBUGF(ICMP_DEBUG, (" to "));
+  ip_addr_debug_print(ICMP_DEBUG, &(iphdr->dest));
+  LWIP_DEBUGF(ICMP_DEBUG, ("\n"));
+
+  tehdr = q->payload;
+  ICMPH_TYPE_SET(tehdr, ICMP_TE);
+  ICMPH_CODE_SET(tehdr, t);
+
+  /* copy fields from original packet */
+  memcpy((u8_t *)q->payload + 8, (u8_t *)p->payload, IP_HLEN + 8);
+
+  /* calculate checksum */
+  tehdr->chksum = 0;
+  tehdr->chksum = inet_chksum(tehdr, q->len);
+  ICMP_STATS_INC(icmp.xmit);
+  /* increase number of messages attempted to send */
+  snmp_inc_icmpoutmsgs();
+  /* increase number of destination unreachable messages attempted to send */
+  snmp_inc_icmpouttimeexcds();
+  ip_output(q, NULL, &(iphdr->src),
+	    ICMP_TTL, 0, IP_PROTO_ICMP);
+  pbuf_free(q);
+}
+
+#endif /* IP_FORWARD */
+
+
+
+
+
+
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/ipv4/ip.c b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/ipv4/ip.c
new file mode 100644
index 000000000..1a6d7bd22
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/ipv4/ip.c
@@ -0,0 +1,508 @@
+/* @file
+ *
+ * This is the IP layer implementation for incoming and outgoing IP traffic.
+ * 
+ * @see ip_frag.c
+ *
+ */
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/ip.h"
+#include "lwip/ip_frag.h"
+#include "lwip/inet.h"
+#include "lwip/netif.h"
+#include "lwip/icmp.h"
+#include "lwip/raw.h"
+#include "lwip/udp.h"
+#include "lwip/tcp.h"
+
+#include "lwip/stats.h"
+
+#include "arch/perf.h"
+
+#include "lwip/snmp.h"
+#if LWIP_DHCP
+#  include "lwip/dhcp.h"
+#endif /* LWIP_DHCP */
+
+
+/**
+ * Initializes the IP layer.
+ */
+
+void
+ip_init(void)
+{
+  /* no initializations as of yet */
+}
+
+/**
+ * Finds the appropriate network interface for a given IP address. It
+ * searches the list of network interfaces linearly. A match is found
+ * if the masked IP address of the network interface equals the masked
+ * IP address given to the function.
+ */
+
+struct netif *
+ip_route(struct ip_addr *dest)
+{
+  struct netif *netif;
+
+  /* iterate through netifs */
+  for(netif = netif_list; netif != NULL; netif = netif->next) {
+    /* network mask matches? */
+    if (ip_addr_netcmp(dest, &(netif->ip_addr), &(netif->netmask))) {
+      /* return netif on which to forward IP packet */
+      return netif;
+    }
+  }
+  /* no matching netif found, use default netif */
+  return netif_default;
+}
+#if IP_FORWARD
+
+/**
+ * Forwards an IP packet. It finds an appropriate route for the
+ * packet, decrements the TTL value of the packet, adjusts the
+ * checksum and outputs the packet on the appropriate interface.
+ */
+
+static struct netif *
+ip_forward(struct pbuf *p, struct ip_hdr *iphdr, struct netif *inp)
+{
+  struct netif *netif;
+
+  PERF_START;
+  /* Find network interface where to forward this IP packet to. */
+  netif = ip_route((struct ip_addr *)&(iphdr->dest));
+  if (netif == NULL) {
+    LWIP_DEBUGF(IP_DEBUG, ("ip_forward: no forwarding route for 0x%"X32_F" found\n",
+                      iphdr->dest.addr));
+    snmp_inc_ipnoroutes();
+    return (struct netif *)NULL;
+  }
+  /* Do not forward packets onto the same network interface on which
+   * they arrived. */
+  if (netif == inp) {
+    LWIP_DEBUGF(IP_DEBUG, ("ip_forward: not bouncing packets back on incoming interface.\n"));
+    snmp_inc_ipnoroutes();
+    return (struct netif *)NULL;
+  }
+
+  /* decrement TTL */
+  IPH_TTL_SET(iphdr, IPH_TTL(iphdr) - 1);
+  /* send ICMP if TTL == 0 */
+  if (IPH_TTL(iphdr) == 0) {
+    /* Don't send ICMP messages in response to ICMP messages */
+    if (IPH_PROTO(iphdr) != IP_PROTO_ICMP) {
+      icmp_time_exceeded(p, ICMP_TE_TTL);
+      snmp_inc_icmpouttimeexcds();
+    }
+    return (struct netif *)NULL;
+  }
+
+  /* Incrementally update the IP checksum. */
+  if (IPH_CHKSUM(iphdr) >= htons(0xffff - 0x100)) {
+    IPH_CHKSUM_SET(iphdr, IPH_CHKSUM(iphdr) + htons(0x100) + 1);
+  } else {
+    IPH_CHKSUM_SET(iphdr, IPH_CHKSUM(iphdr) + htons(0x100));
+  }
+
+  LWIP_DEBUGF(IP_DEBUG, ("ip_forward: forwarding packet to 0x%"X32_F"\n",
+                    iphdr->dest.addr));
+
+  IP_STATS_INC(ip.fw);
+  IP_STATS_INC(ip.xmit);
+    snmp_inc_ipforwdatagrams();
+
+  PERF_STOP("ip_forward");
+  /* transmit pbuf on chosen interface */
+  netif->output(netif, p, (struct ip_addr *)&(iphdr->dest));
+  return netif;
+}
+#endif /* IP_FORWARD */
+
+/**
+ * This function is called by the network interface device driver when
+ * an IP packet is received. The function does the basic checks of the
+ * IP header such as packet size being at least larger than the header
+ * size etc. If the packet was not destined for us, the packet is
+ * forwarded (using ip_forward). The IP checksum is always checked.
+ *
+ * Finally, the packet is sent to the upper layer protocol input function.
+ * 
+ * 
+ * 
+ */
+
+err_t
+ip_input(struct pbuf *p, struct netif *inp) {
+  struct ip_hdr *iphdr;
+  struct netif *netif;
+  u16_t iphdrlen;
+
+  IP_STATS_INC(ip.recv);
+  snmp_inc_ipinreceives();
+
+  /* identify the IP header */
+  iphdr = p->payload;
+  if (IPH_V(iphdr) != 4) {
+    LWIP_DEBUGF(IP_DEBUG | 1, ("IP packet dropped due to bad version number %"U16_F"\n", IPH_V(iphdr)));
+    ip_debug_print(p);
+    pbuf_free(p);
+    IP_STATS_INC(ip.err);
+    IP_STATS_INC(ip.drop);
+    snmp_inc_ipunknownprotos();
+    return ERR_OK;
+  }
+  /* obtain IP header length in number of 32-bit words */
+  iphdrlen = IPH_HL(iphdr);
+  /* calculate IP header length in bytes */
+  iphdrlen *= 4;
+
+  /* header length exceeds first pbuf length? */
+  if (iphdrlen > p->len) {
+    LWIP_DEBUGF(IP_DEBUG | 2, ("IP header (len %"U16_F") does not fit in first pbuf (len %"U16_F"), IP packet droppped.\n",
+      iphdrlen, p->len));
+    /* free (drop) packet pbufs */
+    pbuf_free(p);
+    IP_STATS_INC(ip.lenerr);
+    IP_STATS_INC(ip.drop);
+    snmp_inc_ipindiscards();
+    return ERR_OK;
+  }
+
+  /* verify checksum */
+#if CHECKSUM_CHECK_IP
+  if (inet_chksum(iphdr, iphdrlen) != 0) {
+
+    LWIP_DEBUGF(IP_DEBUG | 2, ("Checksum (0x%"X16_F") failed, IP packet dropped.\n", inet_chksum(iphdr, iphdrlen)));
+    ip_debug_print(p);
+    pbuf_free(p);
+    IP_STATS_INC(ip.chkerr);
+    IP_STATS_INC(ip.drop);
+    snmp_inc_ipindiscards();
+    return ERR_OK;
+  }
+#endif
+
+  /* Trim pbuf. This should have been done at the netif layer,
+   * but we'll do it anyway just to be sure that its done. */
+  pbuf_realloc(p, ntohs(IPH_LEN(iphdr)));
+
+  /* match packet against an interface, i.e. is this packet for us? */
+  for (netif = netif_list; netif != NULL; netif = netif->next) {
+
+    LWIP_DEBUGF(IP_DEBUG, ("ip_input: iphdr->dest 0x%"X32_F" netif->ip_addr 0x%"X32_F" (0x%"X32_F", 0x%"X32_F", 0x%"X32_F")\n",
+      iphdr->dest.addr, netif->ip_addr.addr,
+      iphdr->dest.addr & netif->netmask.addr,
+      netif->ip_addr.addr & netif->netmask.addr,
+      iphdr->dest.addr & ~(netif->netmask.addr)));
+
+    /* interface is up and configured? */
+    if ((netif_is_up(netif)) && (!ip_addr_isany(&(netif->ip_addr))))
+    {
+      /* unicast to this interface address? */
+      if (ip_addr_cmp(&(iphdr->dest), &(netif->ip_addr)) ||
+         /* or broadcast on this interface network address? */
+         ip_addr_isbroadcast(&(iphdr->dest), netif)) {
+        LWIP_DEBUGF(IP_DEBUG, ("ip_input: packet accepted on interface %c%c\n",
+          netif->name[0], netif->name[1]));
+        /* break out of for loop */
+        break;
+      }
+    }
+  }
+#if LWIP_DHCP
+  /* Pass DHCP messages regardless of destination address. DHCP traffic is addressed
+   * using link layer addressing (such as Ethernet MAC) so we must not filter on IP.
+   * According to RFC 1542 section 3.1.1, referred by RFC 2131).
+   */
+  if (netif == NULL) {
+    /* remote port is DHCP server? */
+    if (IPH_PROTO(iphdr) == IP_PROTO_UDP) {
+      LWIP_DEBUGF(IP_DEBUG | DBG_TRACE | 1, ("ip_input: UDP packet to DHCP client port %"U16_F"\n",
+        ntohs(((struct udp_hdr *)((u8_t *)iphdr + iphdrlen))->dest)));
+      if (ntohs(((struct udp_hdr *)((u8_t *)iphdr + iphdrlen))->dest) == DHCP_CLIENT_PORT) {
+        LWIP_DEBUGF(IP_DEBUG | DBG_TRACE | 1, ("ip_input: DHCP packet accepted.\n"));
+        netif = inp;
+      }
+    }
+  }
+#endif /* LWIP_DHCP */
+  /* packet not for us? */
+  if (netif == NULL) {
+    /* packet not for us, route or discard */
+    LWIP_DEBUGF(IP_DEBUG | DBG_TRACE | 1, ("ip_input: packet not for us.\n"));
+#if IP_FORWARD
+    /* non-broadcast packet? */
+    if (!ip_addr_isbroadcast(&(iphdr->dest), inp)) {
+      /* try to forward IP packet on (other) interfaces */
+      ip_forward(p, iphdr, inp);
+    }
+    else
+#endif /* IP_FORWARD */
+    {
+      snmp_inc_ipindiscards();
+    }
+    pbuf_free(p);
+    return ERR_OK;
+  }
+  /* packet consists of multiple fragments? */
+  if ((IPH_OFFSET(iphdr) & htons(IP_OFFMASK | IP_MF)) != 0) {
+#if IP_REASSEMBLY /* packet fragment reassembly code present? */
+    LWIP_DEBUGF(IP_DEBUG, ("IP packet is a fragment (id=0x%04"X16_F" tot_len=%"U16_F" len=%"U16_F" MF=%"U16_F" offset=%"U16_F"), calling ip_reass()\n",
+      ntohs(IPH_ID(iphdr)), p->tot_len, ntohs(IPH_LEN(iphdr)), !!(IPH_OFFSET(iphdr) & htons(IP_MF)), (ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK)*8));
+    /* reassemble the packet*/
+    p = ip_reass(p);
+    /* packet not fully reassembled yet? */
+    if (p == NULL) {
+      return ERR_OK;
+    }
+    iphdr = p->payload;
+#else /* IP_REASSEMBLY == 0, no packet fragment reassembly code present */
+    pbuf_free(p);
+    LWIP_DEBUGF(IP_DEBUG | 2, ("IP packet dropped since it was fragmented (0x%"X16_F") (while IP_REASSEMBLY == 0).\n",
+      ntohs(IPH_OFFSET(iphdr))));
+    IP_STATS_INC(ip.opterr);
+    IP_STATS_INC(ip.drop);
+    snmp_inc_ipunknownprotos();
+    return ERR_OK;
+#endif /* IP_REASSEMBLY */
+  }
+
+#if IP_OPTIONS == 0 /* no support for IP options in the IP header? */
+  if (iphdrlen > IP_HLEN) {
+    LWIP_DEBUGF(IP_DEBUG | 2, ("IP packet dropped since there were IP options (while IP_OPTIONS == 0).\n"));
+    pbuf_free(p);
+    IP_STATS_INC(ip.opterr);
+    IP_STATS_INC(ip.drop);
+    snmp_inc_ipunknownprotos();
+    return ERR_OK;
+  }
+#endif /* IP_OPTIONS == 0 */
+
+  /* send to upper layers */
+  LWIP_DEBUGF(IP_DEBUG, ("ip_input: \n"));
+  ip_debug_print(p);
+  LWIP_DEBUGF(IP_DEBUG, ("ip_input: p->len %"U16_F" p->tot_len %"U16_F"\n", p->len, p->tot_len));
+
+#if LWIP_RAW
+  /* raw input did not eat the packet? */
+  if (raw_input(p, inp) == 0) {
+#endif /* LWIP_RAW */
+
+  switch (IPH_PROTO(iphdr)) {
+#if LWIP_UDP
+  case IP_PROTO_UDP:
+  case IP_PROTO_UDPLITE:
+    snmp_inc_ipindelivers();
+    udp_input(p, inp);
+    break;
+#endif /* LWIP_UDP */
+#if LWIP_TCP
+  case IP_PROTO_TCP:
+    snmp_inc_ipindelivers();
+    tcp_input(p, inp);
+    break;
+#endif /* LWIP_TCP */
+  case IP_PROTO_ICMP:
+    snmp_inc_ipindelivers();
+    icmp_input(p, inp);
+    break;
+  default:
+    /* send ICMP destination protocol unreachable unless is was a broadcast */
+    if (!ip_addr_isbroadcast(&(iphdr->dest), inp) &&
+        !ip_addr_ismulticast(&(iphdr->dest))) {
+      p->payload = iphdr;
+      icmp_dest_unreach(p, ICMP_DUR_PROTO);
+    }
+    pbuf_free(p);
+
+    LWIP_DEBUGF(IP_DEBUG | 2, ("Unsupported transport protocol %"U16_F"\n", IPH_PROTO(iphdr)));
+
+    IP_STATS_INC(ip.proterr);
+    IP_STATS_INC(ip.drop);
+    snmp_inc_ipunknownprotos();
+  }
+#if LWIP_RAW
+  } /* LWIP_RAW */
+#endif
+  return ERR_OK;
+}
+
+/**
+ * Sends an IP packet on a network interface. This function constructs
+ * the IP header and calculates the IP header checksum. If the source
+ * IP address is NULL, the IP address of the outgoing network
+ * interface is filled in as source address.
+ */
+
+err_t
+ip_output_if(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+             u8_t ttl, u8_t tos,
+             u8_t proto, struct netif *netif)
+{
+  struct ip_hdr *iphdr;
+  u16_t ip_id = 0;
+
+  snmp_inc_ipoutrequests();
+
+  if (dest != IP_HDRINCL) {
+    if (pbuf_header(p, IP_HLEN)) {
+      LWIP_DEBUGF(IP_DEBUG | 2, ("ip_output: not enough room for IP header in pbuf\n"));
+
+      IP_STATS_INC(ip.err);
+      snmp_inc_ipoutdiscards();
+      return ERR_BUF;
+    }
+
+    iphdr = p->payload;
+
+    IPH_TTL_SET(iphdr, ttl);
+    IPH_PROTO_SET(iphdr, proto);
+
+    ip_addr_set(&(iphdr->dest), dest);
+
+    IPH_VHLTOS_SET(iphdr, 4, IP_HLEN / 4, tos);
+    IPH_LEN_SET(iphdr, htons(p->tot_len));
+    IPH_OFFSET_SET(iphdr, htons(IP_DF));
+    IPH_ID_SET(iphdr, htons(ip_id));
+    ++ip_id;
+
+    if (ip_addr_isany(src)) {
+      ip_addr_set(&(iphdr->src), &(netif->ip_addr));
+    } else {
+      ip_addr_set(&(iphdr->src), src);
+    }
+
+    IPH_CHKSUM_SET(iphdr, 0);
+#if CHECKSUM_GEN_IP
+    IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN));
+#endif
+  } else {
+    iphdr = p->payload;
+    dest = &(iphdr->dest);
+  }
+
+#if IP_FRAG
+  /* don't fragment if interface has mtu set to 0 [loopif] */
+  if (netif->mtu && (p->tot_len > netif->mtu))
+    return ip_frag(p,netif,dest);
+#endif
+
+  IP_STATS_INC(ip.xmit);
+
+  LWIP_DEBUGF(IP_DEBUG, ("ip_output_if: %c%c%"U16_F"\n", netif->name[0], netif->name[1], netif->num));
+  ip_debug_print(p);
+
+  LWIP_DEBUGF(IP_DEBUG, ("netif->output()"));
+
+  return netif->output(netif, p, dest);
+}
+
+/**
+ * Simple interface to ip_output_if. It finds the outgoing network
+ * interface and calls upon ip_output_if to do the actual work.
+ */
+
+err_t
+ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+          u8_t ttl, u8_t tos, u8_t proto)
+{
+  struct netif *netif;
+
+  if ((netif = ip_route(dest)) == NULL) {
+    LWIP_DEBUGF(IP_DEBUG | 2, ("ip_output: No route to 0x%"X32_F"\n", dest->addr));
+
+    IP_STATS_INC(ip.rterr);
+    snmp_inc_ipoutdiscards();
+    return ERR_RTE;
+  }
+
+  return ip_output_if(p, src, dest, ttl, tos, proto, netif);
+}
+
+#if IP_DEBUG
+void
+ip_debug_print(struct pbuf *p)
+{
+  struct ip_hdr *iphdr = p->payload;
+  u8_t *payload;
+
+  payload = (u8_t *)iphdr + IP_HLEN;
+
+  LWIP_DEBUGF(IP_DEBUG, ("IP header:\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|%2"S16_F" |%2"S16_F" |  0x%02"X16_F" |     %5"U16_F"     | (v, hl, tos, len)\n",
+                    IPH_V(iphdr),
+                    IPH_HL(iphdr),
+                    IPH_TOS(iphdr),
+                    ntohs(IPH_LEN(iphdr))));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|    %5"U16_F"      |%"U16_F"%"U16_F"%"U16_F"|    %4"U16_F"   | (id, flags, offset)\n",
+                    ntohs(IPH_ID(iphdr)),
+                    ntohs(IPH_OFFSET(iphdr)) >> 15 & 1,
+                    ntohs(IPH_OFFSET(iphdr)) >> 14 & 1,
+                    ntohs(IPH_OFFSET(iphdr)) >> 13 & 1,
+                    ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|  %3"U16_F"  |  %3"U16_F"  |    0x%04"X16_F"     | (ttl, proto, chksum)\n",
+                    IPH_TTL(iphdr),
+                    IPH_PROTO(iphdr),
+                    ntohs(IPH_CHKSUM(iphdr))));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|  %3"U16_F"  |  %3"U16_F"  |  %3"U16_F"  |  %3"U16_F"  | (src)\n",
+                    ip4_addr1(&iphdr->src),
+                    ip4_addr2(&iphdr->src),
+                    ip4_addr3(&iphdr->src),
+                    ip4_addr4(&iphdr->src)));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|  %3"U16_F"  |  %3"U16_F"  |  %3"U16_F"  |  %3"U16_F"  | (dest)\n",
+                    ip4_addr1(&iphdr->dest),
+                    ip4_addr2(&iphdr->dest),
+                    ip4_addr3(&iphdr->dest),
+                    ip4_addr4(&iphdr->dest)));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+}
+#endif /* IP_DEBUG */
+
+
+
+
+
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/ipv4/ip_addr.c b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/ipv4/ip_addr.c
new file mode 100644
index 000000000..cb465eef2
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/ipv4/ip_addr.c
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/ip_addr.h"
+#include "lwip/inet.h"
+#include "lwip/netif.h"
+
+/* used by IP_ADDR_ANY and IP_ADDR_BROADCAST in ip_addr.h */
+const struct ip_addr ip_addr_any = { 0x00000000UL };
+const struct ip_addr ip_addr_broadcast = { 0xffffffffUL };
+
+/* Determine if an address is a broadcast address on a network interface 
+ * 
+ * @param addr address to be checked
+ * @param netif the network interface against which the address is checked
+ * @return returns non-zero if the address is a broadcast address
+ *
+ */
+
+u8_t ip_addr_isbroadcast(struct ip_addr *addr, struct netif *netif)
+{
+  /* all ones (broadcast) or all zeroes (old skool broadcast) */
+  if ((addr->addr == ip_addr_broadcast.addr) ||
+      (addr->addr == ip_addr_any.addr))
+    return 1;
+  /* no broadcast support on this network interface? */
+  else if ((netif->flags & NETIF_FLAG_BROADCAST) == 0)
+    /* the given address cannot be a broadcast address
+     * nor can we check against any broadcast addresses */
+    return 0;
+  /* address matches network interface address exactly? => no broadcast */
+  else if (addr->addr == netif->ip_addr.addr)
+    return 0;
+  /*  on the same (sub) network... */
+  else if (ip_addr_netcmp(addr, &(netif->ip_addr), &(netif->netmask))
+         /* ...and host identifier bits are all ones? =>... */
+          && ((addr->addr & ~netif->netmask.addr) ==
+           (ip_addr_broadcast.addr & ~netif->netmask.addr)))
+    /* => network broadcast address */
+    return 1;
+  else
+    return 0;
+}
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/ipv4/ip_frag.c b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/ipv4/ip_frag.c
new file mode 100644
index 000000000..a233674d1
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/ipv4/ip_frag.c
@@ -0,0 +1,366 @@
+/* @file
+ * 
+ * This is the IP packet segmentation and reassembly implementation.
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Jani Monoses  
+ * original reassembly code by Adam Dunkels 
+ * 
+ */
+
+#include 
+
+#include "lwip/opt.h"
+/* #include "lwip/sys.h" */
+#include "lwip/ip.h"
+#include "lwip/ip_frag.h"
+#include "lwip/netif.h"
+#include "lwip/stats.h"
+
+
+/*
+ * Copy len bytes from offset in pbuf to buffer 
+ *
+ * helper used by both ip_reass and ip_frag
+ */
+static struct pbuf *
+copy_from_pbuf(struct pbuf *p, u16_t * offset,
+           u8_t * buffer, u16_t len)
+{
+  u16_t l;
+
+  p->payload = (u8_t *)p->payload + *offset;
+  p->len -= *offset;
+  while (len) {
+    l = len < p->len ? len : p->len;
+    memcpy(buffer, p->payload, l);
+    buffer += l;
+    len -= l;
+    if (len)
+      p = p->next;
+    else
+      *offset = l;
+  }
+  return p;
+}
+
+#define IP_REASS_BUFSIZE 5760
+#define IP_REASS_MAXAGE 30
+#define IP_REASS_TMO 1000
+
+static u8_t ip_reassbuf[IP_HLEN + IP_REASS_BUFSIZE];
+static u8_t ip_reassbitmap[IP_REASS_BUFSIZE / (8 * 8) + 1];
+static const u8_t bitmap_bits[8] = { 0xff, 0x7f, 0x3f, 0x1f,
+  0x0f, 0x07, 0x03, 0x01
+};
+static u16_t ip_reasslen;
+static u8_t ip_reassflags;
+#define IP_REASS_FLAG_LASTFRAG 0x01
+
+static u8_t ip_reasstmr;
+
+/**
+ * Reassembly timer base function
+ * for both NO_SYS == 0 and 1 (!).
+ *
+ * Should be called every 1000 msec.
+ */
+void
+ip_reass_tmr(void)
+{
+  if (ip_reasstmr > 0) {
+    ip_reasstmr--;
+  }
+}
+
+/**
+ * Reassembles incoming IP fragments into an IP datagram.
+ *
+ * @param p points to a pbuf chain of the fragment
+ * @return NULL if reassembly is incomplete, ? otherwise
+ */
+struct pbuf *
+ip_reass(struct pbuf *p)
+{
+  struct pbuf *q;
+  struct ip_hdr *fraghdr, *iphdr;
+  u16_t offset, len;
+  u16_t i;
+
+  IPFRAG_STATS_INC(ip_frag.recv);
+
+  iphdr = (struct ip_hdr *) ip_reassbuf;
+  fraghdr = (struct ip_hdr *) p->payload;
+  /* If ip_reasstmr is zero, no packet is present in the buffer, so we
+     write the IP header of the fragment into the reassembly
+     buffer. The timer is updated with the maximum age. */
+  if (ip_reasstmr == 0) {
+    LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass: new packet\n"));
+    memcpy(iphdr, fraghdr, IP_HLEN);
+    ip_reasstmr = IP_REASS_MAXAGE;
+    ip_reassflags = 0;
+    /* Clear the bitmap. */
+    memset(ip_reassbitmap, 0, sizeof(ip_reassbitmap));
+  }
+
+  /* Check if the incoming fragment matches the one currently present
+     in the reasembly buffer. If so, we proceed with copying the
+     fragment into the buffer. */
+  if (ip_addr_cmp(&iphdr->src, &fraghdr->src) &&
+      ip_addr_cmp(&iphdr->dest, &fraghdr->dest) &&
+      IPH_ID(iphdr) == IPH_ID(fraghdr)) {
+    LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass: matching previous fragment ID=%"X16_F"\n",
+      ntohs(IPH_ID(fraghdr))));
+    IPFRAG_STATS_INC(ip_frag.cachehit);
+    /* Find out the offset in the reassembly buffer where we should
+       copy the fragment. */
+    len = ntohs(IPH_LEN(fraghdr)) - IPH_HL(fraghdr) * 4;
+    offset = (ntohs(IPH_OFFSET(fraghdr)) & IP_OFFMASK) * 8;
+
+    /* If the offset or the offset + fragment length overflows the
+       reassembly buffer, we discard the entire packet. */
+    if (offset > IP_REASS_BUFSIZE || offset + len > IP_REASS_BUFSIZE) {
+      LWIP_DEBUGF(IP_REASS_DEBUG,
+       ("ip_reass: fragment outside of buffer (%"S16_F":%"S16_F"/%"S16_F").\n", offset,
+        offset + len, IP_REASS_BUFSIZE));
+      ip_reasstmr = 0;
+      goto nullreturn;
+    }
+
+    /* Copy the fragment into the reassembly buffer, at the right
+       offset. */
+    LWIP_DEBUGF(IP_REASS_DEBUG,
+     ("ip_reass: copying with offset %"S16_F" into %"S16_F":%"S16_F"\n", offset,
+      IP_HLEN + offset, IP_HLEN + offset + len));
+    i = IPH_HL(fraghdr) * 4;
+    copy_from_pbuf(p, &i, &ip_reassbuf[IP_HLEN + offset], len);
+
+    /* Update the bitmap. */
+    if (offset / (8 * 8) == (offset + len) / (8 * 8)) {
+      LWIP_DEBUGF(IP_REASS_DEBUG,
+       ("ip_reass: updating single byte in bitmap.\n"));
+      /* If the two endpoints are in the same byte, we only update that byte. */
+      LWIP_ASSERT("offset / (8 * 8) < sizeof(ip_reassbitmap)",
+                   offset / (8 * 8) < sizeof(ip_reassbitmap));
+      ip_reassbitmap[offset / (8 * 8)] |=
+        bitmap_bits[(offset / 8) & 7] &
+        ~bitmap_bits[((offset + len) / 8) & 7];
+    } else {
+      /* If the two endpoints are in different bytes, we update the
+         bytes in the endpoints and fill the stuff inbetween with
+         0xff. */
+      LWIP_ASSERT("offset / (8 * 8) < sizeof(ip_reassbitmap)",
+                   offset / (8 * 8) < sizeof(ip_reassbitmap));
+      ip_reassbitmap[offset / (8 * 8)] |= bitmap_bits[(offset / 8) & 7];
+      LWIP_DEBUGF(IP_REASS_DEBUG,
+       ("ip_reass: updating many bytes in bitmap (%"S16_F":%"S16_F").\n",
+        1 + offset / (8 * 8), (offset + len) / (8 * 8)));
+      for (i = 1 + offset / (8 * 8); i < (offset + len) / (8 * 8); ++i) {
+        ip_reassbitmap[i] = 0xff;
+      }
+      LWIP_ASSERT("(offset + len) / (8 * 8) < sizeof(ip_reassbitmap)",
+                   (offset + len) / (8 * 8) < sizeof(ip_reassbitmap));
+      ip_reassbitmap[(offset + len) / (8 * 8)] |=
+        ~bitmap_bits[((offset + len) / 8) & 7];
+    }
+
+    /* If this fragment has the More Fragments flag set to zero, we
+       know that this is the last fragment, so we can calculate the
+       size of the entire packet. We also set the
+       IP_REASS_FLAG_LASTFRAG flag to indicate that we have received
+       the final fragment. */
+
+    if ((ntohs(IPH_OFFSET(fraghdr)) & IP_MF) == 0) {
+      ip_reassflags |= IP_REASS_FLAG_LASTFRAG;
+      ip_reasslen = offset + len;
+      LWIP_DEBUGF(IP_REASS_DEBUG,
+       ("ip_reass: last fragment seen, total len %"S16_F"\n",
+        ip_reasslen));
+    }
+
+    /* Finally, we check if we have a full packet in the buffer. We do
+       this by checking if we have the last fragment and if all bits
+       in the bitmap are set. */
+    if (ip_reassflags & IP_REASS_FLAG_LASTFRAG) {
+      /* Check all bytes up to and including all but the last byte in
+         the bitmap. */
+      LWIP_ASSERT("ip_reasslen / (8 * 8) - 1 < sizeof(ip_reassbitmap)",
+                   ip_reasslen / (8 * 8) - 1 < sizeof(ip_reassbitmap));
+      for (i = 0; i < ip_reasslen / (8 * 8) - 1; ++i) {
+        if (ip_reassbitmap[i] != 0xff) {
+          LWIP_DEBUGF(IP_REASS_DEBUG,
+           ("ip_reass: last fragment seen, bitmap %"S16_F"/%"S16_F" failed (%"X16_F")\n",
+            i, ip_reasslen / (8 * 8) - 1, ip_reassbitmap[i]));
+          goto nullreturn;
+        }
+      }
+      /* Check the last byte in the bitmap. It should contain just the
+         right amount of bits. */
+      LWIP_ASSERT("ip_reasslen / (8 * 8) < sizeof(ip_reassbitmap)",
+                   ip_reasslen / (8 * 8) < sizeof(ip_reassbitmap));
+      if (ip_reassbitmap[ip_reasslen / (8 * 8)] !=
+        (u8_t) ~ bitmap_bits[ip_reasslen / 8 & 7]) {
+         LWIP_DEBUGF(IP_REASS_DEBUG,
+          ("ip_reass: last fragment seen, bitmap %"S16_F" didn't contain %"X16_F" (%"X16_F")\n",
+        ip_reasslen / (8 * 8), ~bitmap_bits[ip_reasslen / 8 & 7],
+        ip_reassbitmap[ip_reasslen / (8 * 8)]));
+        goto nullreturn;
+      }
+
+      /* Pretend to be a "normal" (i.e., not fragmented) IP packet
+         from now on. */
+      ip_reasslen += IP_HLEN;
+
+      IPH_LEN_SET(iphdr, htons(ip_reasslen));
+      IPH_OFFSET_SET(iphdr, 0);
+      IPH_CHKSUM_SET(iphdr, 0);
+      IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN));
+
+      /* If we have come this far, we have a full packet in the
+         buffer, so we allocate a pbuf and copy the packet into it. We
+         also reset the timer. */
+      ip_reasstmr = 0;
+      pbuf_free(p);
+      p = pbuf_alloc(PBUF_LINK, ip_reasslen, PBUF_POOL);
+      if (p != NULL) {
+        i = 0;
+        for (q = p; q != NULL; q = q->next) {
+          /* Copy enough bytes to fill this pbuf in the chain. The
+             available data in the pbuf is given by the q->len variable. */
+          LWIP_DEBUGF(IP_REASS_DEBUG,
+           ("ip_reass: memcpy from %p (%"S16_F") to %p, %"S16_F" bytes\n",
+            (void *)&ip_reassbuf[i], i, q->payload,
+            q->len > ip_reasslen - i ? ip_reasslen - i : q->len));
+          memcpy(q->payload, &ip_reassbuf[i],
+            q->len > ip_reasslen - i ? ip_reasslen - i : q->len);
+          i += q->len;
+        }
+        IPFRAG_STATS_INC(ip_frag.fw);
+      } else {
+        IPFRAG_STATS_INC(ip_frag.memerr);
+      }
+      LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass: p %p\n", (void*)p));
+      return p;
+    }
+  }
+
+nullreturn:
+  IPFRAG_STATS_INC(ip_frag.drop);
+  pbuf_free(p);
+  return NULL;
+}
+
+#define MAX_MTU 1500
+static u8_t buf[MEM_ALIGN_SIZE(MAX_MTU)];
+
+/**
+ * Fragment an IP datagram if too large for the netif.
+ *
+ * Chop the datagram in MTU sized chunks and send them in order
+ * by using a fixed size static memory buffer (PBUF_ROM)
+ */
+err_t 
+ip_frag(struct pbuf *p, struct netif *netif, struct ip_addr *dest)
+{
+  struct pbuf *rambuf;
+  struct pbuf *header;
+  struct ip_hdr *iphdr;
+  u16_t nfb = 0;
+  u16_t left, cop;
+  u16_t mtu = netif->mtu;
+  u16_t ofo, omf;
+  u16_t last;
+  u16_t poff = IP_HLEN;
+  u16_t tmp;
+
+  /* Get a RAM based MTU sized pbuf */
+  rambuf = pbuf_alloc(PBUF_LINK, 0, PBUF_REF);
+  if (rambuf == NULL) {
+    return ERR_MEM;
+  }
+  rambuf->tot_len = rambuf->len = mtu;
+  rambuf->payload = MEM_ALIGN((void *)buf);
+
+  /* Copy the IP header in it */
+  iphdr = rambuf->payload;
+  memcpy(iphdr, p->payload, IP_HLEN);
+
+  /* Save original offset */
+  tmp = ntohs(IPH_OFFSET(iphdr));
+  ofo = tmp & IP_OFFMASK;
+  omf = tmp & IP_MF;
+
+  left = p->tot_len - IP_HLEN;
+
+  while (left) {
+    last = (left <= mtu - IP_HLEN);
+
+    /* Set new offset and MF flag */
+    ofo += nfb;
+    tmp = omf | (IP_OFFMASK & (ofo));
+    if (!last)
+      tmp = tmp | IP_MF;
+    IPH_OFFSET_SET(iphdr, htons(tmp));
+
+    /* Fill this fragment */
+    nfb = (mtu - IP_HLEN) / 8;
+    cop = last ? left : nfb * 8;
+
+    p = copy_from_pbuf(p, &poff, (u8_t *) iphdr + IP_HLEN, cop);
+
+    /* Correct header */
+    IPH_LEN_SET(iphdr, htons(cop + IP_HLEN));
+    IPH_CHKSUM_SET(iphdr, 0);
+    IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN));
+
+    if (last)
+      pbuf_realloc(rambuf, left + IP_HLEN);
+    /* This part is ugly: we alloc a RAM based pbuf for 
+     * the link level header for each chunk and then 
+     * free it.A PBUF_ROM style pbuf for which pbuf_header
+     * worked would make things simpler.
+     */
+    header = pbuf_alloc(PBUF_LINK, 0, PBUF_RAM);
+    if (header != NULL) {
+      pbuf_chain(header, rambuf);
+      netif->output(netif, header, dest);
+      IPFRAG_STATS_INC(ip_frag.xmit);
+      pbuf_free(header);
+    } else {
+      pbuf_free(rambuf);      
+      return ERR_MEM;    
+    }
+    left -= cop;
+  }
+  pbuf_free(rambuf);
+  return ERR_OK;
+}
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/ipv6/README b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/ipv6/README
new file mode 100644
index 000000000..362000486
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/ipv6/README
@@ -0,0 +1 @@
+IPv6 support in lwIP is very experimental.
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/ipv6/icmp6.c b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/ipv6/icmp6.c
new file mode 100644
index 000000000..e22dfc3e8
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/ipv6/icmp6.c
@@ -0,0 +1,184 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+/* Some ICMP messages should be passed to the transport protocols. This
+   is not implemented. */
+
+#include "lwip/opt.h"
+
+#include "lwip/icmp.h"
+#include "lwip/inet.h"
+#include "lwip/ip.h"
+#include "lwip/def.h"
+
+#include "lwip/stats.h"
+
+
+void
+icmp_input(struct pbuf *p, struct netif *inp)
+{
+  u8_t type;
+  struct icmp_echo_hdr *iecho;
+  struct ip_hdr *iphdr;
+  struct ip_addr tmpaddr;
+
+#ifdef ICMP_STATS
+  ++lwip_stats.icmp.recv;
+#endif /* ICMP_STATS */
+
+  /* TODO: check length before accessing payload! */
+
+  type = ((u8_t *)p->payload)[0];
+
+  switch (type) {
+  case ICMP6_ECHO:
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ping\n"));
+
+    if (p->tot_len < sizeof(struct icmp_echo_hdr)) {
+      LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: bad ICMP echo received\n"));
+
+      pbuf_free(p);
+#ifdef ICMP_STATS
+      ++lwip_stats.icmp.lenerr;
+#endif /* ICMP_STATS */
+
+      return;
+    }
+    iecho = p->payload;
+    iphdr = (struct ip_hdr *)((u8_t *)p->payload - IP_HLEN);
+    if (inet_chksum_pbuf(p) != 0) {
+      LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo (%"X16_F")\n", inet_chksum_pseudo(p, &(iphdr->src), &(iphdr->dest), IP_PROTO_ICMP, p->tot_len)));
+
+#ifdef ICMP_STATS
+      ++lwip_stats.icmp.chkerr;
+#endif /* ICMP_STATS */
+    /*      return;*/
+    }
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp: p->len %"S16_F" p->tot_len %"S16_F"\n", p->len, p->tot_len));
+    ip_addr_set(&tmpaddr, &(iphdr->src));
+    ip_addr_set(&(iphdr->src), &(iphdr->dest));
+    ip_addr_set(&(iphdr->dest), &tmpaddr);
+    iecho->type = ICMP6_ER;
+    /* adjust the checksum */
+    if (iecho->chksum >= htons(0xffff - (ICMP6_ECHO << 8))) {
+      iecho->chksum += htons(ICMP6_ECHO << 8) + 1;
+    } else {
+      iecho->chksum += htons(ICMP6_ECHO << 8);
+    }
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo (%"X16_F")\n", inet_chksum_pseudo(p, &(iphdr->src), &(iphdr->dest), IP_PROTO_ICMP, p->tot_len)));
+#ifdef ICMP_STATS
+    ++lwip_stats.icmp.xmit;
+#endif /* ICMP_STATS */
+
+    /*    LWIP_DEBUGF("icmp: p->len %"U16_F" p->tot_len %"U16_F"\n", p->len, p->tot_len);*/
+    ip_output_if (p, &(iphdr->src), IP_HDRINCL,
+     iphdr->hoplim, IP_PROTO_ICMP, inp);
+    break;
+  default:
+    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ICMP type %"S16_F" not supported.\n", (s16_t)type));
+#ifdef ICMP_STATS
+    ++lwip_stats.icmp.proterr;
+    ++lwip_stats.icmp.drop;
+#endif /* ICMP_STATS */
+  }
+
+  pbuf_free(p);
+}
+
+void
+icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t)
+{
+  struct pbuf *q;
+  struct ip_hdr *iphdr;
+  struct icmp_dur_hdr *idur;
+
+  q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM);
+  /* ICMP header + IP header + 8 bytes of data */
+
+  iphdr = p->payload;
+
+  idur = q->payload;
+  idur->type = (u8_t)ICMP6_DUR;
+  idur->icode = (u8_t)t;
+
+  memcpy((u8_t *)q->payload + 8, p->payload, IP_HLEN + 8);
+
+  /* calculate checksum */
+  idur->chksum = 0;
+  idur->chksum = inet_chksum(idur, q->len);
+#ifdef ICMP_STATS
+  ++lwip_stats.icmp.xmit;
+#endif /* ICMP_STATS */
+
+  ip_output(q, NULL,
+      (struct ip_addr *)&(iphdr->src), ICMP_TTL, IP_PROTO_ICMP);
+  pbuf_free(q);
+}
+
+void
+icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t)
+{
+  struct pbuf *q;
+  struct ip_hdr *iphdr;
+  struct icmp_te_hdr *tehdr;
+
+  LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded\n"));
+
+  q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM);
+
+  iphdr = p->payload;
+
+  tehdr = q->payload;
+  tehdr->type = (u8_t)ICMP6_TE;
+  tehdr->icode = (u8_t)t;
+
+  /* copy fields from original packet */
+  memcpy((u8_t *)q->payload + 8, (u8_t *)p->payload, IP_HLEN + 8);
+
+  /* calculate checksum */
+  tehdr->chksum = 0;
+  tehdr->chksum = inet_chksum(tehdr, q->len);
+#ifdef ICMP_STATS
+  ++lwip_stats.icmp.xmit;
+#endif /* ICMP_STATS */
+  ip_output(q, NULL,
+      (struct ip_addr *)&(iphdr->src), ICMP_TTL, IP_PROTO_ICMP);
+  pbuf_free(q);
+}
+
+
+
+
+
+
+
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/ipv6/ip6.c b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/ipv6/ip6.c
new file mode 100644
index 000000000..4d97f78c0
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/ipv6/ip6.c
@@ -0,0 +1,386 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+
+
+/* ip.c
+ *
+ * This is the code for the IP layer for IPv6.
+ *
+ */
+
+
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/ip.h"
+#include "lwip/inet.h"
+#include "lwip/netif.h"
+#include "lwip/icmp.h"
+#include "lwip/udp.h"
+#include "lwip/tcp.h"
+
+#include "lwip/stats.h"
+
+#include "arch/perf.h"
+
+/* ip_init:
+ *
+ * Initializes the IP layer.
+ */
+
+void
+ip_init(void)
+{
+}
+
+/* ip_route:
+ *
+ * Finds the appropriate network interface for a given IP address. It searches the
+ * list of network interfaces linearly. A match is found if the masked IP address of
+ * the network interface equals the masked IP address given to the function.
+ */
+
+struct netif *
+ip_route(struct ip_addr *dest)
+{
+  struct netif *netif;
+
+  for(netif = netif_list; netif != NULL; netif = netif->next) {
+    if (ip_addr_netcmp(dest, &(netif->ip_addr), &(netif->netmask))) {
+      return netif;
+    }
+  }
+
+  return netif_default;
+}
+
+/* ip_forward:
+ *
+ * Forwards an IP packet. It finds an appropriate route for the packet, decrements
+ * the TTL value of the packet, adjusts the checksum and outputs the packet on the
+ * appropriate interface.
+ */
+
+static void
+ip_forward(struct pbuf *p, struct ip_hdr *iphdr)
+{
+  struct netif *netif;
+
+  PERF_START;
+
+  if ((netif = ip_route((struct ip_addr *)&(iphdr->dest))) == NULL) {
+
+    LWIP_DEBUGF(IP_DEBUG, ("ip_input: no forwarding route found for "));
+#if IP_DEBUG
+    ip_addr_debug_print(IP_DEBUG, &(iphdr->dest));
+#endif /* IP_DEBUG */
+    LWIP_DEBUGF(IP_DEBUG, ("\n"));
+    pbuf_free(p);
+    return;
+  }
+  /* Decrement TTL and send ICMP if ttl == 0. */
+  if (--iphdr->hoplim == 0) {
+    /* Don't send ICMP messages in response to ICMP messages */
+    if (iphdr->nexthdr != IP_PROTO_ICMP) {
+      icmp_time_exceeded(p, ICMP_TE_TTL);
+    }
+    pbuf_free(p);
+    return;
+  }
+
+  /* Incremental update of the IP checksum. */
+  /*  if (iphdr->chksum >= htons(0xffff - 0x100)) {
+    iphdr->chksum += htons(0x100) + 1;
+  } else {
+    iphdr->chksum += htons(0x100);
+    }*/
+
+
+  LWIP_DEBUGF(IP_DEBUG, ("ip_forward: forwarding packet to "));
+#if IP_DEBUG
+  ip_addr_debug_print(IP_DEBUG, &(iphdr->dest));
+#endif /* IP_DEBUG */
+  LWIP_DEBUGF(IP_DEBUG, ("\n"));
+
+#ifdef IP_STATS
+  ++lwip_stats.ip.fw;
+  ++lwip_stats.ip.xmit;
+#endif /* IP_STATS */
+
+  PERF_STOP("ip_forward");
+
+  netif->output(netif, p, (struct ip_addr *)&(iphdr->dest));
+}
+
+/* ip_input:
+ *
+ * This function is called by the network interface device driver when an IP packet is
+ * received. The function does the basic checks of the IP header such as packet size
+ * being at least larger than the header size etc. If the packet was not destined for
+ * us, the packet is forwarded (using ip_forward). The IP checksum is always checked.
+ *
+ * Finally, the packet is sent to the upper layer protocol input function.
+ */
+
+void
+ip_input(struct pbuf *p, struct netif *inp) {
+  struct ip_hdr *iphdr;
+  struct netif *netif;
+
+
+  PERF_START;
+
+#if IP_DEBUG
+  ip_debug_print(p);
+#endif /* IP_DEBUG */
+
+
+#ifdef IP_STATS
+  ++lwip_stats.ip.recv;
+#endif /* IP_STATS */
+
+  /* identify the IP header */
+  iphdr = p->payload;
+
+
+  if (iphdr->v != 6) {
+    LWIP_DEBUGF(IP_DEBUG, ("IP packet dropped due to bad version number\n"));
+#if IP_DEBUG
+    ip_debug_print(p);
+#endif /* IP_DEBUG */
+    pbuf_free(p);
+#ifdef IP_STATS
+    ++lwip_stats.ip.err;
+    ++lwip_stats.ip.drop;
+#endif /* IP_STATS */
+    return;
+  }
+
+  /* is this packet for us? */
+  for(netif = netif_list; netif != NULL; netif = netif->next) {
+#if IP_DEBUG
+    LWIP_DEBUGF(IP_DEBUG, ("ip_input: iphdr->dest "));
+    ip_addr_debug_print(IP_DEBUG, &(iphdr->dest));
+    LWIP_DEBUGF(IP_DEBUG, ("netif->ip_addr "));
+    ip_addr_debug_print(IP_DEBUG, &(netif->ip_addr));
+    LWIP_DEBUGF(IP_DEBUG, ("\n"));
+#endif /* IP_DEBUG */
+    if (ip_addr_cmp(&(iphdr->dest), &(netif->ip_addr))) {
+      break;
+    }
+  }
+
+
+  if (netif == NULL) {
+    /* packet not for us, route or discard */
+#ifdef IP_FORWARD
+    ip_forward(p, iphdr);
+#endif
+    pbuf_free(p);
+    return;
+  }
+
+  pbuf_realloc(p, IP_HLEN + ntohs(iphdr->len));
+
+  /* send to upper layers */
+#if IP_DEBUG
+  /*  LWIP_DEBUGF("ip_input: \n");
+  ip_debug_print(p);
+  LWIP_DEBUGF("ip_input: p->len %"U16_F" p->tot_len %"U16_F"\n", p->len, p->tot_len);*/
+#endif /* IP_DEBUG */
+
+
+  pbuf_header(p, -IP_HLEN);
+
+  switch (iphdr->nexthdr) {
+  case IP_PROTO_UDP:
+    udp_input(p);
+    break;
+  case IP_PROTO_TCP:
+    tcp_input(p);
+    break;
+  case IP_PROTO_ICMP:
+    icmp_input(p, inp);
+    break;
+  default:
+    /* send ICMP destination protocol unreachable */
+    icmp_dest_unreach(p, ICMP_DUR_PROTO);
+    pbuf_free(p);
+    LWIP_DEBUGF(IP_DEBUG, ("Unsupported transport protocol %"U16_F"\n",
+          iphdr->nexthdr));
+
+#ifdef IP_STATS
+    ++lwip_stats.ip.proterr;
+    ++lwip_stats.ip.drop;
+#endif /* IP_STATS */
+
+  }
+  PERF_STOP("ip_input");
+}
+
+
+/* ip_output_if:
+ *
+ * Sends an IP packet on a network interface. This function constructs the IP header
+ * and calculates the IP header checksum. If the source IP address is NULL,
+ * the IP address of the outgoing network interface is filled in as source address.
+ */
+
+err_t
+ip_output_if (struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+       u8_t ttl,
+       u8_t proto, struct netif *netif)
+{
+  struct ip_hdr *iphdr;
+
+  PERF_START;
+
+  printf("len %"U16_F" tot_len %"U16_F"\n", p->len, p->tot_len);
+  if (pbuf_header(p, IP_HLEN)) {
+    LWIP_DEBUGF(IP_DEBUG, ("ip_output: not enough room for IP header in pbuf\n"));
+#ifdef IP_STATS
+    ++lwip_stats.ip.err;
+#endif /* IP_STATS */
+
+    return ERR_BUF;
+  }
+  printf("len %"U16_F" tot_len %"U16_F"\n", p->len, p->tot_len);
+
+  iphdr = p->payload;
+
+
+  if (dest != IP_HDRINCL) {
+    printf("!IP_HDRLINCL\n");
+    iphdr->hoplim = ttl;
+    iphdr->nexthdr = proto;
+    iphdr->len = htons(p->tot_len - IP_HLEN);
+    ip_addr_set(&(iphdr->dest), dest);
+
+    iphdr->v = 6;
+
+    if (ip_addr_isany(src)) {
+      ip_addr_set(&(iphdr->src), &(netif->ip_addr));
+    } else {
+      ip_addr_set(&(iphdr->src), src);
+    }
+
+  } else {
+    dest = &(iphdr->dest);
+  }
+
+#ifdef IP_STATS
+  ++lwip_stats.ip.xmit;
+#endif /* IP_STATS */
+
+  LWIP_DEBUGF(IP_DEBUG, ("ip_output_if: %c%c (len %"U16_F")\n", netif->name[0], netif->name[1], p->tot_len));
+#if IP_DEBUG
+  ip_debug_print(p);
+#endif /* IP_DEBUG */
+
+  PERF_STOP("ip_output_if");
+  return netif->output(netif, p, dest);
+}
+
+/* ip_output:
+ *
+ * Simple interface to ip_output_if. It finds the outgoing network interface and
+ * calls upon ip_output_if to do the actual work.
+ */
+
+err_t
+ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+    u8_t ttl, u8_t proto)
+{
+  struct netif *netif;
+  if ((netif = ip_route(dest)) == NULL) {
+    LWIP_DEBUGF(IP_DEBUG, ("ip_output: No route to 0x%"X32_F"\n", dest->addr));
+#ifdef IP_STATS
+    ++lwip_stats.ip.rterr;
+#endif /* IP_STATS */
+    return ERR_RTE;
+  }
+
+  return ip_output_if (p, src, dest, ttl, proto, netif);
+}
+
+#if IP_DEBUG
+void
+ip_debug_print(struct pbuf *p)
+{
+  struct ip_hdr *iphdr = p->payload;
+  u8_t *payload;
+
+  payload = (u8_t *)iphdr + IP_HLEN;
+
+  LWIP_DEBUGF(IP_DEBUG, ("IP header:\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|%2"S16_F" |  %"X16_F"%"X16_F"  |      %"X16_F"%"X16_F"           | (v, traffic class, flow label)\n",
+        iphdr->v,
+        iphdr->tclass1, iphdr->tclass2,
+        iphdr->flow1, iphdr->flow2));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|    %5"U16_F"      | %2"U16_F"  |  %2"U16_F"   | (len, nexthdr, hoplim)\n",
+        ntohs(iphdr->len),
+        iphdr->nexthdr,
+        iphdr->hoplim));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|       %4"X32_F"      |       %4"X32_F"     | (src)\n",
+        ntohl(iphdr->src.addr[0]) >> 16 & 0xffff,
+        ntohl(iphdr->src.addr[0]) & 0xffff));
+  LWIP_DEBUGF(IP_DEBUG, ("|       %4"X32_F"      |       %4"X32_F"     | (src)\n",
+        ntohl(iphdr->src.addr[1]) >> 16 & 0xffff,
+        ntohl(iphdr->src.addr[1]) & 0xffff));
+  LWIP_DEBUGF(IP_DEBUG, ("|       %4"X32_F"      |       %4"X32_F"     | (src)\n",
+        ntohl(iphdr->src.addr[2]) >> 16 & 0xffff,
+        ntohl(iphdr->src.addr[2]) & 0xffff));
+  LWIP_DEBUGF(IP_DEBUG, ("|       %4"X32_F"      |       %4"X32_F"     | (src)\n",
+        ntohl(iphdr->src.addr[3]) >> 16 & 0xffff,
+        ntohl(iphdr->src.addr[3]) & 0xffff));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(IP_DEBUG, ("|       %4"X32_F"      |       %4"X32_F"     | (dest)\n",
+        ntohl(iphdr->dest.addr[0]) >> 16 & 0xffff,
+        ntohl(iphdr->dest.addr[0]) & 0xffff));
+  LWIP_DEBUGF(IP_DEBUG, ("|       %4"X32_F"      |       %4"X32_F"     | (dest)\n",
+        ntohl(iphdr->dest.addr[1]) >> 16 & 0xffff,
+        ntohl(iphdr->dest.addr[1]) & 0xffff));
+  LWIP_DEBUGF(IP_DEBUG, ("|       %4"X32_F"      |       %4"X32_F"     | (dest)\n",
+        ntohl(iphdr->dest.addr[2]) >> 16 & 0xffff,
+        ntohl(iphdr->dest.addr[2]) & 0xffff));
+  LWIP_DEBUGF(IP_DEBUG, ("|       %4"X32_F"      |       %4"X32_F"     | (dest)\n",
+        ntohl(iphdr->dest.addr[3]) >> 16 & 0xffff,
+        ntohl(iphdr->dest.addr[3]) & 0xffff));
+  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
+}
+#endif /* IP_DEBUG */
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/ipv6/ip6_addr.c b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/ipv6/ip6_addr.c
new file mode 100644
index 000000000..5341dedfd
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/ipv6/ip6_addr.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/ip_addr.h"
+#include "lwip/inet.h"
+
+
+u8_t
+ip_addr_netcmp(struct ip_addr *addr1, struct ip_addr *addr2,
+                struct ip_addr *mask)
+{
+  return((addr1->addr[0] & mask->addr[0]) == (addr2->addr[0] & mask->addr[0]) &&
+         (addr1->addr[1] & mask->addr[1]) == (addr2->addr[1] & mask->addr[1]) &&
+         (addr1->addr[2] & mask->addr[2]) == (addr2->addr[2] & mask->addr[2]) &&
+         (addr1->addr[3] & mask->addr[3]) == (addr2->addr[3] & mask->addr[3]));
+        
+}
+
+u8_t
+ip_addr_cmp(struct ip_addr *addr1, struct ip_addr *addr2)
+{
+  return(addr1->addr[0] == addr2->addr[0] &&
+         addr1->addr[1] == addr2->addr[1] &&
+         addr1->addr[2] == addr2->addr[2] &&
+         addr1->addr[3] == addr2->addr[3]);
+}
+
+void
+ip_addr_set(struct ip_addr *dest, struct ip_addr *src)
+{
+  memcpy(dest, src, sizeof(struct ip_addr));
+  /*  dest->addr[0] = src->addr[0];
+  dest->addr[1] = src->addr[1];
+  dest->addr[2] = src->addr[2];
+  dest->addr[3] = src->addr[3];*/
+}
+
+u8_t
+ip_addr_isany(struct ip_addr *addr)
+{
+  if (addr == NULL) return 1;
+  return((addr->addr[0] | addr->addr[1] | addr->addr[2] | addr->addr[3]) == 0);
+}
+
+
+/*#if IP_DEBUG*/
+void
+ip_addr_debug_print(struct ip_addr *addr)
+{
+  printf("%"X32_F":%"X32_F":%"X32_F":%"X32_F":%"X32_F":%"X32_F":%"X32_F":%"X32_F",
+         ntohl(addr->addr[0]) >> 16 & 0xffff,
+         ntohl(addr->addr[0]) & 0xffff,
+         ntohl(addr->addr[1]) >> 16 & 0xffff,
+         ntohl(addr->addr[1]) & 0xffff,
+         ntohl(addr->addr[2]) >> 16 & 0xffff,
+         ntohl(addr->addr[2]) & 0xffff,
+         ntohl(addr->addr[3]) >> 16 & 0xffff,
+         ntohl(addr->addr[3]) & 0xffff);
+}
+/*#endif*/ /* IP_DEBUG */
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/mem.c b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/mem.c
new file mode 100644
index 000000000..d37c4c075
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/mem.c
@@ -0,0 +1,310 @@
+/** @file
+ *
+ * Dynamic memory manager
+ *
+ */
+
+/* 
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include 
+
+#include "lwip/arch.h"
+#include "lwip/opt.h"
+#include "lwip/def.h"
+#include "lwip/mem.h"
+
+#include "lwip/sys.h"
+
+#include "lwip/stats.h"
+
+struct mem {
+  mem_size_t next, prev;
+#if MEM_ALIGNMENT == 1
+  u8_t used;
+#elif MEM_ALIGNMENT == 2
+  u16_t used;
+#elif MEM_ALIGNMENT == 4
+  u32_t used;
+#elif MEM_ALIGNMENT == 8
+  u64_t used;
+#else
+#error "unhandled MEM_ALIGNMENT size"
+#endif /* MEM_ALIGNMENT */
+}; 
+
+static struct mem *ram_end;
+static u8_t ram[MEM_SIZE + sizeof(struct mem) + MEM_ALIGNMENT];
+
+#define MIN_SIZE 12
+#if 0 /* this one does not align correctly for some, resulting in crashes */
+#define SIZEOF_STRUCT_MEM (unsigned int)MEM_ALIGN_SIZE(sizeof(struct mem))
+#else
+#define SIZEOF_STRUCT_MEM (sizeof(struct mem) + \
+                          (((sizeof(struct mem) % MEM_ALIGNMENT) == 0)? 0 : \
+                          (4 - (sizeof(struct mem) % MEM_ALIGNMENT))))
+#endif
+
+static struct mem *lfree;   /* pointer to the lowest free block */
+
+static sys_sem_t mem_sem;
+
+static void
+plug_holes(struct mem *mem)
+{
+  struct mem *nmem;
+  struct mem *pmem;
+
+  LWIP_ASSERT("plug_holes: mem >= ram", (u8_t *)mem >= ram);
+  LWIP_ASSERT("plug_holes: mem < ram_end", (u8_t *)mem < (u8_t *)ram_end);
+  LWIP_ASSERT("plug_holes: mem->used == 0", mem->used == 0);
+  
+  /* plug hole forward */
+  LWIP_ASSERT("plug_holes: mem->next <= MEM_SIZE", mem->next <= MEM_SIZE);
+  
+  nmem = (struct mem *)&ram[mem->next];
+  if (mem != nmem && nmem->used == 0 && (u8_t *)nmem != (u8_t *)ram_end) {
+    if (lfree == nmem) {
+      lfree = mem;
+    }
+    mem->next = nmem->next;
+    ((struct mem *)&ram[nmem->next])->prev = (u8_t *)mem - ram;
+  }
+
+  /* plug hole backward */
+  pmem = (struct mem *)&ram[mem->prev];
+  if (pmem != mem && pmem->used == 0) {
+    if (lfree == mem) {
+      lfree = pmem;
+    }
+    pmem->next = mem->next;
+    ((struct mem *)&ram[mem->next])->prev = (u8_t *)pmem - ram;
+  }
+
+}
+void
+mem_init(void)
+{
+  struct mem *mem;
+
+  memset(ram, 0, MEM_SIZE);
+  mem = (struct mem *)ram;
+  mem->next = MEM_SIZE;
+  mem->prev = 0;
+  mem->used = 0;
+  ram_end = (struct mem *)&ram[MEM_SIZE];
+  ram_end->used = 1;
+  ram_end->next = MEM_SIZE;
+  ram_end->prev = MEM_SIZE;
+
+  mem_sem = sys_sem_new(1);
+
+  lfree = (struct mem *)ram;
+
+#if MEM_STATS
+  lwip_stats.mem.avail = MEM_SIZE;
+#endif /* MEM_STATS */
+}
+void
+mem_free(void *rmem)
+{
+  struct mem *mem;
+
+  if (rmem == NULL) {
+    LWIP_DEBUGF(MEM_DEBUG | DBG_TRACE | 2, ("mem_free(p == NULL) was called.\n"));
+    return;
+  }
+  
+  sys_sem_wait(mem_sem);
+
+  LWIP_ASSERT("mem_free: legal memory", (u8_t *)rmem >= (u8_t *)ram &&
+    (u8_t *)rmem < (u8_t *)ram_end);
+  
+  if ((u8_t *)rmem < (u8_t *)ram || (u8_t *)rmem >= (u8_t *)ram_end) {
+    LWIP_DEBUGF(MEM_DEBUG | 3, ("mem_free: illegal memory\n"));
+#if MEM_STATS
+    ++lwip_stats.mem.err;
+#endif /* MEM_STATS */
+    sys_sem_signal(mem_sem);
+    return;
+  }
+  mem = (struct mem *)((u8_t *)rmem - SIZEOF_STRUCT_MEM);
+
+  LWIP_ASSERT("mem_free: mem->used", mem->used);
+  
+  mem->used = 0;
+
+  if (mem < lfree) {
+    lfree = mem;
+  }
+  
+#if MEM_STATS
+  lwip_stats.mem.used -= mem->next - ((u8_t *)mem - ram);
+  
+#endif /* MEM_STATS */
+  plug_holes(mem);
+  sys_sem_signal(mem_sem);
+}
+void *
+mem_reallocm(void *rmem, mem_size_t newsize)
+{
+  void *nmem;
+  nmem = mem_malloc(newsize);
+  if (nmem == NULL) {
+    return mem_realloc(rmem, newsize);
+  }
+  memcpy(nmem, rmem, newsize);
+  mem_free(rmem);
+  return nmem;
+}
+
+void *
+mem_realloc(void *rmem, mem_size_t newsize)
+{
+  mem_size_t size;
+  mem_size_t ptr, ptr2;
+  struct mem *mem, *mem2;
+
+  /* Expand the size of the allocated memory region so that we can
+     adjust for alignment. */
+  if ((newsize % MEM_ALIGNMENT) != 0) {
+   newsize += MEM_ALIGNMENT - ((newsize + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT);
+  }
+  
+  if (newsize > MEM_SIZE) {
+    return NULL;
+  }
+  
+  sys_sem_wait(mem_sem);
+  
+  LWIP_ASSERT("mem_realloc: legal memory", (u8_t *)rmem >= (u8_t *)ram &&
+   (u8_t *)rmem < (u8_t *)ram_end);
+  
+  if ((u8_t *)rmem < (u8_t *)ram || (u8_t *)rmem >= (u8_t *)ram_end) {
+    LWIP_DEBUGF(MEM_DEBUG | 3, ("mem_realloc: illegal memory\n"));
+    return rmem;
+  }
+  mem = (struct mem *)((u8_t *)rmem - SIZEOF_STRUCT_MEM);
+
+  ptr = (u8_t *)mem - ram;
+
+  size = mem->next - ptr - SIZEOF_STRUCT_MEM;
+#if MEM_STATS
+  lwip_stats.mem.used -= (size - newsize);
+#endif /* MEM_STATS */
+  
+  if (newsize + SIZEOF_STRUCT_MEM + MIN_SIZE < size) {
+    ptr2 = ptr + SIZEOF_STRUCT_MEM + newsize;
+    mem2 = (struct mem *)&ram[ptr2];
+    mem2->used = 0;
+    mem2->next = mem->next;
+    mem2->prev = ptr;
+    mem->next = ptr2;
+    if (mem2->next != MEM_SIZE) {
+      ((struct mem *)&ram[mem2->next])->prev = ptr2;
+    }
+
+    plug_holes(mem2);
+  }
+  sys_sem_signal(mem_sem);  
+  return rmem;
+}
+void *
+mem_malloc(mem_size_t size)
+{
+  mem_size_t ptr, ptr2;
+  struct mem *mem, *mem2;
+
+  if (size == 0) {
+    return NULL;
+  }
+
+  /* Expand the size of the allocated memory region so that we can
+     adjust for alignment. */
+  if ((size % MEM_ALIGNMENT) != 0) {
+    size += MEM_ALIGNMENT - ((size + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT);
+  }
+  
+  if (size > MEM_SIZE) {
+    return NULL;
+  }
+  
+  sys_sem_wait(mem_sem);
+
+  for (ptr = (u8_t *)lfree - ram; ptr < MEM_SIZE; ptr = ((struct mem *)&ram[ptr])->next) {
+    mem = (struct mem *)&ram[ptr];
+    if (!mem->used &&
+       mem->next - (ptr + SIZEOF_STRUCT_MEM) >= size + SIZEOF_STRUCT_MEM) {
+      ptr2 = ptr + SIZEOF_STRUCT_MEM + size;
+      mem2 = (struct mem *)&ram[ptr2];
+
+      mem2->prev = ptr;      
+      mem2->next = mem->next;
+      mem->next = ptr2;      
+      if (mem2->next != MEM_SIZE) {
+        ((struct mem *)&ram[mem2->next])->prev = ptr2;
+      }
+      
+      mem2->used = 0;      
+      mem->used = 1;
+#if MEM_STATS
+      lwip_stats.mem.used += (size + SIZEOF_STRUCT_MEM);
+      /*      if (lwip_stats.mem.max < lwip_stats.mem.used) {
+        lwip_stats.mem.max = lwip_stats.mem.used;
+  } */
+      if (lwip_stats.mem.max < ptr2) {
+        lwip_stats.mem.max = ptr2;
+      }      
+#endif /* MEM_STATS */
+
+      if (mem == lfree) {
+  /* Find next free block after mem */
+        while (lfree->used && lfree != ram_end) {
+    lfree = (struct mem *)&ram[lfree->next];
+        }
+        LWIP_ASSERT("mem_malloc: !lfree->used", !lfree->used);
+      }
+      sys_sem_signal(mem_sem);
+      LWIP_ASSERT("mem_malloc: allocated memory not above ram_end.",
+       (mem_ptr_t)mem + SIZEOF_STRUCT_MEM + size <= (mem_ptr_t)ram_end);
+      LWIP_ASSERT("mem_malloc: allocated memory properly aligned.",
+       (unsigned long)((u8_t *)mem + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT == 0);
+      return (u8_t *)mem + SIZEOF_STRUCT_MEM;
+    }    
+  }
+  LWIP_DEBUGF(MEM_DEBUG | 2, ("mem_malloc: could not allocate %"S16_F" bytes\n", (s16_t)size));
+#if MEM_STATS
+  ++lwip_stats.mem.err;
+#endif /* MEM_STATS */  
+  sys_sem_signal(mem_sem);
+  return NULL;
+}
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/memp.c b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/memp.c
new file mode 100644
index 000000000..f31b60190
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/memp.c
@@ -0,0 +1,274 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/memp.h"
+
+#include "lwip/pbuf.h"
+#include "lwip/udp.h"
+#include "lwip/raw.h"
+#include "lwip/tcp.h"
+#include "lwip/api.h"
+#include "lwip/api_msg.h"
+#include "lwip/tcpip.h"
+
+#include "lwip/sys.h"
+#include "lwip/stats.h"
+
+struct memp {
+  struct memp *next;
+};
+
+
+
+static struct memp *memp_tab[MEMP_MAX];
+
+static const u16_t memp_sizes[MEMP_MAX] = {
+  sizeof(struct pbuf),
+  sizeof(struct raw_pcb),
+  sizeof(struct udp_pcb),
+  sizeof(struct tcp_pcb),
+  sizeof(struct tcp_pcb_listen),
+  sizeof(struct tcp_seg),
+  sizeof(struct netbuf),
+  sizeof(struct netconn),
+  sizeof(struct api_msg),
+  sizeof(struct tcpip_msg),
+  sizeof(struct sys_timeout)
+};
+
+static const u16_t memp_num[MEMP_MAX] = {
+  MEMP_NUM_PBUF,
+  MEMP_NUM_RAW_PCB,
+  MEMP_NUM_UDP_PCB,
+  MEMP_NUM_TCP_PCB,
+  MEMP_NUM_TCP_PCB_LISTEN,
+  MEMP_NUM_TCP_SEG,
+  MEMP_NUM_NETBUF,
+  MEMP_NUM_NETCONN,
+  MEMP_NUM_API_MSG,
+  MEMP_NUM_TCPIP_MSG,
+  MEMP_NUM_SYS_TIMEOUT
+};
+
+static u8_t memp_memory[(MEMP_NUM_PBUF *
+       MEM_ALIGN_SIZE(sizeof(struct pbuf) +
+          sizeof(struct memp)) +
+      MEMP_NUM_RAW_PCB *
+       MEM_ALIGN_SIZE(sizeof(struct raw_pcb) +
+          sizeof(struct memp)) +
+      MEMP_NUM_UDP_PCB *
+       MEM_ALIGN_SIZE(sizeof(struct udp_pcb) +
+          sizeof(struct memp)) +
+      MEMP_NUM_TCP_PCB *
+       MEM_ALIGN_SIZE(sizeof(struct tcp_pcb) +
+          sizeof(struct memp)) +
+      MEMP_NUM_TCP_PCB_LISTEN *
+       MEM_ALIGN_SIZE(sizeof(struct tcp_pcb_listen) +
+          sizeof(struct memp)) +
+      MEMP_NUM_TCP_SEG *
+       MEM_ALIGN_SIZE(sizeof(struct tcp_seg) +
+          sizeof(struct memp)) +
+      MEMP_NUM_NETBUF *
+       MEM_ALIGN_SIZE(sizeof(struct netbuf) +
+          sizeof(struct memp)) +
+      MEMP_NUM_NETCONN *
+       MEM_ALIGN_SIZE(sizeof(struct netconn) +
+          sizeof(struct memp)) +
+      MEMP_NUM_API_MSG *
+       MEM_ALIGN_SIZE(sizeof(struct api_msg) +
+          sizeof(struct memp)) +
+      MEMP_NUM_TCPIP_MSG *
+       MEM_ALIGN_SIZE(sizeof(struct tcpip_msg) +
+          sizeof(struct memp)) +
+      MEMP_NUM_SYS_TIMEOUT *
+       MEM_ALIGN_SIZE(sizeof(struct sys_timeout) +
+          sizeof(struct memp)))];
+
+
+#if !SYS_LIGHTWEIGHT_PROT
+static sys_sem_t mutex;
+#endif
+
+#if MEMP_SANITY_CHECK
+static int
+memp_sanity(void)
+{
+  s16_t i, c;
+  struct memp *m, *n;
+
+  for(i = 0; i < MEMP_MAX; i++) {
+    for(m = memp_tab[i]; m != NULL; m = m->next) {
+      c = 1;
+      for(n = memp_tab[i]; n != NULL; n = n->next) {
+         if (n == m) {
+          --c;
+        }
+        if (c < 0) return 0; /* LW was: abort(); */
+      }
+    }
+  }
+  return 1;
+}
+#endif /* MEMP_SANITY_CHECK*/
+
+void
+memp_init(void)
+{
+  struct memp *m, *memp;
+  u16_t i, j;
+  u16_t size;
+      
+#if MEMP_STATS
+  for(i = 0; i < MEMP_MAX; ++i) {
+    lwip_stats.memp[i].used = lwip_stats.memp[i].max =
+      lwip_stats.memp[i].err = 0;
+    lwip_stats.memp[i].avail = memp_num[i];
+  }
+#endif /* MEMP_STATS */
+
+  memp = (struct memp *)&memp_memory[0];
+  for(i = 0; i < MEMP_MAX; ++i) {
+    size = MEM_ALIGN_SIZE(memp_sizes[i] + sizeof(struct memp));
+    if (memp_num[i] > 0) {
+      memp_tab[i] = memp;
+      m = memp;
+      
+      for(j = 0; j < memp_num[i]; ++j) {
+  m->next = (struct memp *)MEM_ALIGN((u8_t *)m + size);
+  memp = m;
+  m = m->next;
+      }
+      memp->next = NULL;
+      memp = m;
+    } else {
+      memp_tab[i] = NULL;
+    }
+  }
+
+#if !SYS_LIGHTWEIGHT_PROT
+  mutex = sys_sem_new(1);
+#endif
+
+  
+}
+
+void *
+memp_malloc(memp_t type)
+{
+  struct memp *memp;
+  void *mem;
+#if SYS_LIGHTWEIGHT_PROT
+  SYS_ARCH_DECL_PROTECT(old_level);
+#endif
+ 
+  LWIP_ASSERT("memp_malloc: type < MEMP_MAX", type < MEMP_MAX);
+
+#if SYS_LIGHTWEIGHT_PROT
+  SYS_ARCH_PROTECT(old_level);
+#else /* SYS_LIGHTWEIGHT_PROT */  
+  sys_sem_wait(mutex);
+#endif /* SYS_LIGHTWEIGHT_PROT */  
+
+  memp = memp_tab[type];
+  
+  if (memp != NULL) {    
+    memp_tab[type] = memp->next;    
+    memp->next = NULL;
+#if MEMP_STATS
+    ++lwip_stats.memp[type].used;
+    if (lwip_stats.memp[type].used > lwip_stats.memp[type].max) {
+      lwip_stats.memp[type].max = lwip_stats.memp[type].used;
+    }
+#endif /* MEMP_STATS */
+#if SYS_LIGHTWEIGHT_PROT
+    SYS_ARCH_UNPROTECT(old_level);
+#else /* SYS_LIGHTWEIGHT_PROT */
+    sys_sem_signal(mutex);
+#endif /* SYS_LIGHTWEIGHT_PROT */  
+    LWIP_ASSERT("memp_malloc: memp properly aligned",
+     ((mem_ptr_t)MEM_ALIGN((u8_t *)memp + sizeof(struct memp)) % MEM_ALIGNMENT) == 0);
+
+    mem = MEM_ALIGN((u8_t *)memp + sizeof(struct memp));
+    return mem;
+  } else {
+    LWIP_DEBUGF(MEMP_DEBUG | 2, ("memp_malloc: out of memory in pool %"S16_F"\n", type));
+#if MEMP_STATS
+    ++lwip_stats.memp[type].err;
+#endif /* MEMP_STATS */
+#if SYS_LIGHTWEIGHT_PROT
+  SYS_ARCH_UNPROTECT(old_level);
+#else /* SYS_LIGHTWEIGHT_PROT */
+  sys_sem_signal(mutex);
+#endif /* SYS_LIGHTWEIGHT_PROT */  
+    return NULL;
+  }
+}
+
+void
+memp_free(memp_t type, void *mem)
+{
+  struct memp *memp;
+#if SYS_LIGHTWEIGHT_PROT
+  SYS_ARCH_DECL_PROTECT(old_level);
+#endif /* SYS_LIGHTWEIGHT_PROT */  
+
+  if (mem == NULL) {
+    return;
+  }
+  memp = (struct memp *)((u8_t *)mem - sizeof(struct memp));
+
+#if SYS_LIGHTWEIGHT_PROT
+    SYS_ARCH_PROTECT(old_level);
+#else /* SYS_LIGHTWEIGHT_PROT */  
+  sys_sem_wait(mutex);
+#endif /* SYS_LIGHTWEIGHT_PROT */  
+
+#if MEMP_STATS
+  lwip_stats.memp[type].used--; 
+#endif /* MEMP_STATS */
+  
+  memp->next = memp_tab[type]; 
+  memp_tab[type] = memp;
+
+#if MEMP_SANITY_CHECK
+  LWIP_ASSERT("memp sanity", memp_sanity());
+#endif  
+
+#if SYS_LIGHTWEIGHT_PROT
+  SYS_ARCH_UNPROTECT(old_level);
+#else /* SYS_LIGHTWEIGHT_PROT */
+  sys_sem_signal(mutex);
+#endif /* SYS_LIGHTWEIGHT_PROT */  
+}
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/netif.c b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/netif.c
new file mode 100644
index 000000000..b831b7aba
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/netif.c
@@ -0,0 +1,288 @@
+/**
+ * @file
+ *
+ * lwIP network interface abstraction
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/tcp.h"
+
+struct netif *netif_list = NULL;
+struct netif *netif_default = NULL;
+
+/**
+ * Add a network interface to the list of lwIP netifs.
+ *
+ * @param netif a pre-allocated netif structure
+ * @param ipaddr IP address for the new netif
+ * @param netmask network mask for the new netif
+ * @param gw default gateway IP address for the new netif
+ * @param state opaque data passed to the new netif
+ * @param init callback function that initializes the interface
+ * @param input callback function that is called to pass
+ * ingress packets up in the protocol layer stack.
+ *
+ * @return netif, or NULL if failed.
+ */
+struct netif *
+netif_add(struct netif *netif, struct ip_addr *ipaddr, struct ip_addr *netmask,
+  struct ip_addr *gw,
+  void *state,
+  err_t (* init)(struct netif *netif),
+  err_t (* input)(struct pbuf *p, struct netif *netif))
+{
+  static s16_t netifnum = 0;
+  
+#if LWIP_DHCP
+  /* netif not under DHCP control by default */
+  netif->dhcp = NULL;
+#endif
+  /* remember netif specific state information data */
+  netif->state = state;
+  netif->num = netifnum++;
+  netif->input = input;
+
+  netif_set_addr(netif, ipaddr, netmask, gw);
+
+  /* call user specified initialization function for netif */
+  if (init(netif) != ERR_OK) {
+    return NULL;
+  }
+
+  /* add this netif to the list */
+  netif->next = netif_list;
+  netif_list = netif;
+  LWIP_DEBUGF(NETIF_DEBUG, ("netif: added interface %c%c IP addr ",
+    netif->name[0], netif->name[1]));
+  ip_addr_debug_print(NETIF_DEBUG, ipaddr);
+  LWIP_DEBUGF(NETIF_DEBUG, (" netmask "));
+  ip_addr_debug_print(NETIF_DEBUG, netmask);
+  LWIP_DEBUGF(NETIF_DEBUG, (" gw "));
+  ip_addr_debug_print(NETIF_DEBUG, gw);
+  LWIP_DEBUGF(NETIF_DEBUG, ("\n"));
+  return netif;
+}
+
+void
+netif_set_addr(struct netif *netif,struct ip_addr *ipaddr, struct ip_addr *netmask,
+    struct ip_addr *gw)
+{
+  netif_set_ipaddr(netif, ipaddr);
+  netif_set_netmask(netif, netmask);
+  netif_set_gw(netif, gw);
+}
+
+void netif_remove(struct netif * netif)
+{
+  if ( netif == NULL ) return;
+
+  /*  is it the first netif? */
+  if (netif_list == netif) {
+    netif_list = netif->next;
+  }
+  else {
+    /*  look for netif further down the list */
+    struct netif * tmpNetif;
+    for (tmpNetif = netif_list; tmpNetif != NULL; tmpNetif = tmpNetif->next) {
+      if (tmpNetif->next == netif) {
+        tmpNetif->next = netif->next;
+        break;
+        }
+    }
+    if (tmpNetif == NULL)
+      return; /*  we didn't find any netif today */
+  }
+  /* this netif is default? */
+  if (netif_default == netif)
+    /* reset default netif */
+    netif_default = NULL;
+  LWIP_DEBUGF( NETIF_DEBUG, ("netif_remove: removed netif\n") );
+}
+
+struct netif *
+netif_find(char *name)
+{
+  struct netif *netif;
+  u8_t num;
+
+  if (name == NULL) {
+    return NULL;
+  }
+
+  num = name[2] - '0';
+
+  for(netif = netif_list; netif != NULL; netif = netif->next) {
+    if (num == netif->num &&
+       name[0] == netif->name[0] &&
+       name[1] == netif->name[1]) {
+      LWIP_DEBUGF(NETIF_DEBUG, ("netif_find: found %c%c\n", name[0], name[1]));
+      return netif;
+    }
+  }
+  LWIP_DEBUGF(NETIF_DEBUG, ("netif_find: didn't find %c%c\n", name[0], name[1]));
+  return NULL;
+}
+
+void
+netif_set_ipaddr(struct netif *netif, struct ip_addr *ipaddr)
+{
+  /* TODO: Handling of obsolete pcbs */
+  /* See:  http://mail.gnu.org/archive/html/lwip-users/2003-03/msg00118.html */
+#if LWIP_TCP
+  struct tcp_pcb *pcb;
+  struct tcp_pcb_listen *lpcb;
+
+  /* address is actually being changed? */
+  if ((ip_addr_cmp(ipaddr, &(netif->ip_addr))) == 0)
+  {
+    /* extern struct tcp_pcb *tcp_active_pcbs; defined by tcp.h */
+    LWIP_DEBUGF(NETIF_DEBUG | 1, ("netif_set_ipaddr: netif address being changed\n"));
+    pcb = tcp_active_pcbs;
+    while (pcb != NULL) {
+      /* PCB bound to current local interface address? */
+      if (ip_addr_cmp(&(pcb->local_ip), &(netif->ip_addr))) {
+        /* this connection must be aborted */
+        struct tcp_pcb *next = pcb->next;
+        LWIP_DEBUGF(NETIF_DEBUG | 1, ("netif_set_ipaddr: aborting TCP pcb %p\n", (void *)pcb));
+        tcp_abort(pcb);
+        pcb = next;
+      } else {
+        pcb = pcb->next;
+      }
+    }
+    for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
+      /* PCB bound to current local interface address? */
+      if (ip_addr_cmp(&(lpcb->local_ip), &(netif->ip_addr))) {
+        /* The PCB is listening to the old ipaddr and
+         * is set to listen to the new one instead */
+        ip_addr_set(&(lpcb->local_ip), ipaddr);
+      }
+    }
+  }
+#endif
+  ip_addr_set(&(netif->ip_addr), ipaddr);
+#if 0 /* only allowed for Ethernet interfaces TODO: how can we check? */
+  /** For Ethernet network interfaces, we would like to send a
+   *  "gratuitous ARP"; this is an ARP packet sent by a node in order
+   *  to spontaneously cause other nodes to update an entry in their
+   *  ARP cache. From RFC 3220 "IP Mobility Support for IPv4" section 4.6.
+   */ 
+  etharp_query(netif, ipaddr, NULL);
+#endif
+  LWIP_DEBUGF(NETIF_DEBUG | DBG_TRACE | DBG_STATE | 3, ("netif: IP address of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+    netif->name[0], netif->name[1],
+    ip4_addr1(&netif->ip_addr),
+    ip4_addr2(&netif->ip_addr),
+    ip4_addr3(&netif->ip_addr),
+    ip4_addr4(&netif->ip_addr)));
+}
+
+void
+netif_set_gw(struct netif *netif, struct ip_addr *gw)
+{
+  ip_addr_set(&(netif->gw), gw);
+  LWIP_DEBUGF(NETIF_DEBUG | DBG_TRACE | DBG_STATE | 3, ("netif: GW address of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+    netif->name[0], netif->name[1],
+    ip4_addr1(&netif->gw),
+    ip4_addr2(&netif->gw),
+    ip4_addr3(&netif->gw),
+    ip4_addr4(&netif->gw)));
+}
+
+void
+netif_set_netmask(struct netif *netif, struct ip_addr *netmask)
+{
+  ip_addr_set(&(netif->netmask), netmask);
+  LWIP_DEBUGF(NETIF_DEBUG | DBG_TRACE | DBG_STATE | 3, ("netif: netmask of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+    netif->name[0], netif->name[1],
+    ip4_addr1(&netif->netmask),
+    ip4_addr2(&netif->netmask),
+    ip4_addr3(&netif->netmask),
+    ip4_addr4(&netif->netmask)));
+}
+
+void
+netif_set_default(struct netif *netif)
+{
+  netif_default = netif;
+  LWIP_DEBUGF(NETIF_DEBUG, ("netif: setting default interface %c%c\n",
+           netif ? netif->name[0] : '\'', netif ? netif->name[1] : '\''));
+}
+
+/**
+ * Bring an interface up, available for processing
+ * traffic.
+ * 
+ * @note: Enabling DHCP on a down interface will make it come
+ * up once configured.
+ * 
+ * @see dhcp_start()
+ */ 
+void netif_set_up(struct netif *netif)
+{
+  netif->flags |= NETIF_FLAG_UP;
+}
+
+/**
+ * Ask if an interface is up
+ */ 
+u8_t netif_is_up(struct netif *netif)
+{
+  return (netif->flags & NETIF_FLAG_UP)?1:0;
+}
+
+/**
+ * Bring an interface down, disabling any traffic processing.
+ *
+ * @note: Enabling DHCP on a down interface will make it come
+ * up once configured.
+ * 
+ * @see dhcp_start()
+ */ 
+void netif_set_down(struct netif *netif)
+{
+  netif->flags &= ~NETIF_FLAG_UP;
+}
+
+void
+netif_init(void)
+{
+  netif_list = netif_default = NULL;
+}
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/pbuf.c b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/pbuf.c
new file mode 100644
index 000000000..c8e6e2288
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/pbuf.c
@@ -0,0 +1,957 @@
+/**
+ * @file
+ * Packet buffer management
+ *
+ * Packets are built from the pbuf data structure. It supports dynamic
+ * memory allocation for packet contents or can reference externally
+ * managed packet contents both in RAM and ROM. Quick allocation for
+ * incoming packets is provided through pools with fixed sized pbufs.
+ *
+ * A packet may span over multiple pbufs, chained as a singly linked
+ * list. This is called a "pbuf chain".
+ *
+ * Multiple packets may be queued, also using this singly linked list.
+ * This is called a "packet queue".
+ * 
+ * So, a packet queue consists of one or more pbuf chains, each of
+ * which consist of one or more pbufs. Currently, queues are only
+ * supported in a limited section of lwIP, this is the etharp queueing
+ * code. Outside of this section no packet queues are supported yet.
+ * 
+ * The differences between a pbuf chain and a packet queue are very
+ * precise but subtle. 
+ *
+ * The last pbuf of a packet has a ->tot_len field that equals the
+ * ->len field. It can be found by traversing the list. If the last
+ * pbuf of a packet has a ->next field other than NULL, more packets
+ * are on the queue.
+ *
+ * Therefore, looping through a pbuf of a single packet, has an
+ * loop end condition (tot_len == p->len), NOT (next == NULL).
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include 
+
+#include "lwip/opt.h"
+#include "lwip/stats.h"
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+#include "lwip/pbuf.h"
+#include "lwip/sys.h"
+#include "arch/perf.h"
+
+static u8_t pbuf_pool_memory[MEM_ALIGNMENT - 1 + PBUF_POOL_SIZE * MEM_ALIGN_SIZE(PBUF_POOL_BUFSIZE + sizeof(struct pbuf))];
+
+#if !SYS_LIGHTWEIGHT_PROT
+static volatile u8_t pbuf_pool_free_lock, pbuf_pool_alloc_lock;
+static sys_sem_t pbuf_pool_free_sem;
+#endif
+
+static struct pbuf *pbuf_pool = NULL;
+
+/**
+ * Initializes the pbuf module.
+ *
+ * A large part of memory is allocated for holding the pool of pbufs.
+ * The size of the individual pbufs in the pool is given by the size
+ * parameter, and the number of pbufs in the pool by the num parameter.
+ *
+ * After the memory has been allocated, the pbufs are set up. The
+ * ->next pointer in each pbuf is set up to point to the next pbuf in
+ * the pool.
+ *
+ */
+void
+pbuf_init(void)
+{
+  struct pbuf *p, *q = NULL;
+  u16_t i;
+
+  pbuf_pool = (struct pbuf *)MEM_ALIGN(pbuf_pool_memory);
+
+#if PBUF_STATS
+  lwip_stats.pbuf.avail = PBUF_POOL_SIZE;
+#endif /* PBUF_STATS */
+
+  /* Set up ->next pointers to link the pbufs of the pool together */
+  p = pbuf_pool;
+
+  for(i = 0; i < PBUF_POOL_SIZE; ++i) {
+    p->next = (struct pbuf *)((u8_t *)p + PBUF_POOL_BUFSIZE + sizeof(struct pbuf));
+    p->len = p->tot_len = PBUF_POOL_BUFSIZE;
+    p->payload = MEM_ALIGN((void *)((u8_t *)p + sizeof(struct pbuf)));
+    p->flags = PBUF_FLAG_POOL;
+    q = p;
+    p = p->next;
+  }
+
+  /* The ->next pointer of last pbuf is NULL to indicate that there
+     are no more pbufs in the pool */
+  q->next = NULL;
+
+#if !SYS_LIGHTWEIGHT_PROT
+  pbuf_pool_alloc_lock = 0;
+  pbuf_pool_free_lock = 0;
+  pbuf_pool_free_sem = sys_sem_new(1);
+#endif
+}
+
+/**
+ * @internal only called from pbuf_alloc()
+ */
+static struct pbuf *
+pbuf_pool_alloc(void)
+{
+  struct pbuf *p = NULL;
+
+  SYS_ARCH_DECL_PROTECT(old_level);
+  SYS_ARCH_PROTECT(old_level);
+
+#if !SYS_LIGHTWEIGHT_PROT
+  /* Next, check the actual pbuf pool, but if the pool is locked, we
+     pretend to be out of buffers and return NULL. */
+  if (pbuf_pool_free_lock) {
+#if PBUF_STATS
+    ++lwip_stats.pbuf.alloc_locked;
+#endif /* PBUF_STATS */
+    return NULL;
+  }
+  pbuf_pool_alloc_lock = 1;
+  if (!pbuf_pool_free_lock) {
+#endif /* SYS_LIGHTWEIGHT_PROT */
+    p = pbuf_pool;
+    if (p) {
+      pbuf_pool = p->next;
+    }
+#if !SYS_LIGHTWEIGHT_PROT
+#if PBUF_STATS
+  } else {
+    ++lwip_stats.pbuf.alloc_locked;
+#endif /* PBUF_STATS */
+  }
+  pbuf_pool_alloc_lock = 0;
+#endif /* SYS_LIGHTWEIGHT_PROT */
+
+#if PBUF_STATS
+  if (p != NULL) {
+    ++lwip_stats.pbuf.used;
+    if (lwip_stats.pbuf.used > lwip_stats.pbuf.max) {
+      lwip_stats.pbuf.max = lwip_stats.pbuf.used;
+    }
+  }
+#endif /* PBUF_STATS */
+
+  SYS_ARCH_UNPROTECT(old_level);
+  return p;
+}
+
+
+/**
+ * Allocates a pbuf of the given type (possibly a chain for PBUF_POOL type).
+ *
+ * The actual memory allocated for the pbuf is determined by the
+ * layer at which the pbuf is allocated and the requested size
+ * (from the size parameter).
+ *
+ * @param flag this parameter decides how and where the pbuf
+ * should be allocated as follows:
+ *
+ * - PBUF_RAM: buffer memory for pbuf is allocated as one large
+ *             chunk. This includes protocol headers as well.
+ * - PBUF_ROM: no buffer memory is allocated for the pbuf, even for
+ *             protocol headers. Additional headers must be prepended
+ *             by allocating another pbuf and chain in to the front of
+ *             the ROM pbuf. It is assumed that the memory used is really
+ *             similar to ROM in that it is immutable and will not be
+ *             changed. Memory which is dynamic should generally not
+ *             be attached to PBUF_ROM pbufs. Use PBUF_REF instead.
+ * - PBUF_REF: no buffer memory is allocated for the pbuf, even for
+ *             protocol headers. It is assumed that the pbuf is only
+ *             being used in a single thread. If the pbuf gets queued,
+ *             then pbuf_take should be called to copy the buffer.
+ * - PBUF_POOL: the pbuf is allocated as a pbuf chain, with pbufs from
+ *              the pbuf pool that is allocated during pbuf_init().
+ *
+ * @return the allocated pbuf. If multiple pbufs where allocated, this
+ * is the first pbuf of a pbuf chain.
+ */
+struct pbuf *
+pbuf_alloc(pbuf_layer l, u16_t length, pbuf_flag flag)
+{
+  struct pbuf *p, *q, *r;
+  u16_t offset;
+  s32_t rem_len; /* remaining length */
+  LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_alloc(length=%"U16_F")\n", length));
+
+  /* determine header offset */
+  offset = 0;
+  switch (l) {
+  case PBUF_TRANSPORT:
+    /* add room for transport (often TCP) layer header */
+    offset += PBUF_TRANSPORT_HLEN;
+    /* FALLTHROUGH */
+  case PBUF_IP:
+    /* add room for IP layer header */
+    offset += PBUF_IP_HLEN;
+    /* FALLTHROUGH */
+  case PBUF_LINK:
+    /* add room for link layer header */
+    offset += PBUF_LINK_HLEN;
+    break;
+  case PBUF_RAW:
+    break;
+  default:
+    LWIP_ASSERT("pbuf_alloc: bad pbuf layer", 0);
+    return NULL;
+  }
+
+  switch (flag) {
+  case PBUF_POOL:
+    /* allocate head of pbuf chain into p */
+    p = pbuf_pool_alloc();
+    LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_alloc: allocated pbuf %p\n", (void *)p));
+    if (p == NULL) {
+#if PBUF_STATS
+      ++lwip_stats.pbuf.err;
+#endif /* PBUF_STATS */
+      return NULL;
+    }
+    p->next = NULL;
+
+    /* make the payload pointer point 'offset' bytes into pbuf data memory */
+    p->payload = MEM_ALIGN((void *)((u8_t *)p + (sizeof(struct pbuf) + offset)));
+    LWIP_ASSERT("pbuf_alloc: pbuf p->payload properly aligned",
+            ((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0);
+    /* the total length of the pbuf chain is the requested size */
+    p->tot_len = length;
+    /* set the length of the first pbuf in the chain */
+    p->len = length > PBUF_POOL_BUFSIZE - offset? PBUF_POOL_BUFSIZE - offset: length;
+    /* set reference count (needed here in case we fail) */
+    p->ref = 1;
+
+    /* now allocate the tail of the pbuf chain */
+
+    /* remember first pbuf for linkage in next iteration */
+    r = p;
+    /* remaining length to be allocated */
+    rem_len = length - p->len;
+    /* any remaining pbufs to be allocated? */
+    while (rem_len > 0) {
+      q = pbuf_pool_alloc();
+      if (q == NULL) {
+       LWIP_DEBUGF(PBUF_DEBUG | 2, ("pbuf_alloc: Out of pbufs in pool.\n"));
+#if PBUF_STATS
+        ++lwip_stats.pbuf.err;
+#endif /* PBUF_STATS */
+        /* free chain so far allocated */
+        pbuf_free(p);
+        /* bail out unsuccesfully */
+        return NULL;
+      }
+      q->next = NULL;
+      /* make previous pbuf point to this pbuf */
+      r->next = q;
+      /* set total length of this pbuf and next in chain */
+      q->tot_len = rem_len;
+      /* this pbuf length is pool size, unless smaller sized tail */
+      q->len = rem_len > PBUF_POOL_BUFSIZE? PBUF_POOL_BUFSIZE: rem_len;
+      q->payload = (void *)((u8_t *)q + sizeof(struct pbuf));
+      LWIP_ASSERT("pbuf_alloc: pbuf q->payload properly aligned",
+              ((mem_ptr_t)q->payload % MEM_ALIGNMENT) == 0);
+      q->ref = 1;
+      /* calculate remaining length to be allocated */
+      rem_len -= q->len;
+      /* remember this pbuf for linkage in next iteration */
+      r = q;
+    }
+    /* end of chain */
+    /*r->next = NULL;*/
+
+    break;
+  case PBUF_RAM:
+    /* If pbuf is to be allocated in RAM, allocate memory for it. */
+    p = mem_malloc(MEM_ALIGN_SIZE(sizeof(struct pbuf) + offset) + MEM_ALIGN_SIZE(length));
+    if (p == NULL) {
+      return NULL;
+    }
+    /* Set up internal structure of the pbuf. */
+    p->payload = MEM_ALIGN((void *)((u8_t *)p + sizeof(struct pbuf) + offset));
+    p->len = p->tot_len = length;
+    p->next = NULL;
+    p->flags = PBUF_FLAG_RAM;
+
+    LWIP_ASSERT("pbuf_alloc: pbuf->payload properly aligned",
+           ((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0);
+    break;
+  /* pbuf references existing (non-volatile static constant) ROM payload? */
+  case PBUF_ROM:
+  /* pbuf references existing (externally allocated) RAM payload? */
+  case PBUF_REF:
+    /* only allocate memory for the pbuf structure */
+    p = memp_malloc(MEMP_PBUF);
+    if (p == NULL) {
+      LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_alloc: Could not allocate MEMP_PBUF for PBUF_%s.\n", flag == PBUF_ROM?"ROM":"REF"));
+      return NULL;
+    }
+    /* caller must set this field properly, afterwards */
+    p->payload = NULL;
+    p->len = p->tot_len = length;
+    p->next = NULL;
+    p->flags = (flag == PBUF_ROM? PBUF_FLAG_ROM: PBUF_FLAG_REF);
+    break;
+  default:
+    LWIP_ASSERT("pbuf_alloc: erroneous flag", 0);
+    return NULL;
+  }
+  /* set reference count */
+  p->ref = 1;
+  LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_alloc(length=%"U16_F") == %p\n", length, (void *)p));
+  return p;
+}
+
+
+#if PBUF_STATS
+#define DEC_PBUF_STATS do { --lwip_stats.pbuf.used; } while (0)
+#else /* PBUF_STATS */
+#define DEC_PBUF_STATS
+#endif /* PBUF_STATS */
+
+#define PBUF_POOL_FAST_FREE(p)  do {                                    \
+                                  p->next = pbuf_pool;                  \
+                                  pbuf_pool = p;                        \
+                                  DEC_PBUF_STATS;                       \
+                                } while (0)
+
+#if SYS_LIGHTWEIGHT_PROT
+#define PBUF_POOL_FREE(p)  do {                                         \
+                                SYS_ARCH_DECL_PROTECT(old_level);       \
+                                SYS_ARCH_PROTECT(old_level);            \
+                                PBUF_POOL_FAST_FREE(p);                 \
+                                SYS_ARCH_UNPROTECT(old_level);          \
+                               } while (0)
+#else /* SYS_LIGHTWEIGHT_PROT */
+#define PBUF_POOL_FREE(p)  do {                                         \
+                             sys_sem_wait(pbuf_pool_free_sem);          \
+                             PBUF_POOL_FAST_FREE(p);                    \
+                             sys_sem_signal(pbuf_pool_free_sem);        \
+                           } while (0)
+#endif /* SYS_LIGHTWEIGHT_PROT */
+
+/**
+ * Shrink a pbuf chain to a desired length.
+ *
+ * @param p pbuf to shrink.
+ * @param new_len desired new length of pbuf chain
+ *
+ * Depending on the desired length, the first few pbufs in a chain might
+ * be skipped and left unchanged. The new last pbuf in the chain will be
+ * resized, and any remaining pbufs will be freed.
+ *
+ * @note If the pbuf is ROM/REF, only the ->tot_len and ->len fields are adjusted.
+ * @note May not be called on a packet queue.
+ *
+ * @bug Cannot grow the size of a pbuf (chain) (yet).
+ */
+void
+pbuf_realloc(struct pbuf *p, u16_t new_len)
+{
+  struct pbuf *q;
+  u16_t rem_len; /* remaining length */
+  s16_t grow;
+
+  LWIP_ASSERT("pbuf_realloc: sane p->flags", p->flags == PBUF_FLAG_POOL ||
+              p->flags == PBUF_FLAG_ROM ||
+              p->flags == PBUF_FLAG_RAM ||
+              p->flags == PBUF_FLAG_REF);
+
+  /* desired length larger than current length? */
+  if (new_len >= p->tot_len) {
+    /* enlarging not yet supported */
+    return;
+  }
+
+  /* the pbuf chain grows by (new_len - p->tot_len) bytes
+   * (which may be negative in case of shrinking) */
+  grow = new_len - p->tot_len;
+
+  /* first, step over any pbufs that should remain in the chain */
+  rem_len = new_len;
+  q = p;
+  /* should this pbuf be kept? */
+  while (rem_len > q->len) {
+    /* decrease remaining length by pbuf length */
+    rem_len -= q->len;
+    /* decrease total length indicator */
+    q->tot_len += grow;
+    /* proceed to next pbuf in chain */
+    q = q->next;
+  }
+  /* we have now reached the new last pbuf (in q) */
+  /* rem_len == desired length for pbuf q */
+
+  /* shrink allocated memory for PBUF_RAM */
+  /* (other types merely adjust their length fields */
+  if ((q->flags == PBUF_FLAG_RAM) && (rem_len != q->len)) {
+    /* reallocate and adjust the length of the pbuf that will be split */
+    mem_realloc(q, (u8_t *)q->payload - (u8_t *)q + rem_len);
+  }
+  /* adjust length fields for new last pbuf */
+  q->len = rem_len;
+  q->tot_len = q->len;
+
+  /* any remaining pbufs in chain? */
+  if (q->next != NULL) {
+    /* free remaining pbufs in chain */
+    pbuf_free(q->next);
+  }
+  /* q is last packet in chain */
+  q->next = NULL;
+
+}
+
+/**
+ * Adjusts the payload pointer to hide or reveal headers in the payload.
+ *
+ * Adjusts the ->payload pointer so that space for a header
+ * (dis)appears in the pbuf payload.
+ *
+ * The ->payload, ->tot_len and ->len fields are adjusted.
+ *
+ * @param hdr_size_inc Number of bytes to increment header size which
+ * increases the size of the pbuf. New space is on the front.
+ * (Using a negative value decreases the header size.)
+ * If hdr_size_inc is 0, this function does nothing and returns succesful.
+ *
+ * PBUF_ROM and PBUF_REF type buffers cannot have their sizes increased, so
+ * the call will fail. A check is made that the increase in header size does
+ * not move the payload pointer in front of the start of the buffer.
+ * @return non-zero on failure, zero on success.
+ *
+ */
+u8_t
+pbuf_header(struct pbuf *p, s16_t header_size_increment)
+{
+  void *payload;
+
+  LWIP_ASSERT("p != NULL", p != NULL);
+  if ((header_size_increment == 0) || (p == NULL)) return 0;
+ 
+  /* remember current payload pointer */
+  payload = p->payload;
+
+  /* pbuf types containing payloads? */
+  if (p->flags == PBUF_FLAG_RAM || p->flags == PBUF_FLAG_POOL) {
+    /* set new payload pointer */
+    p->payload = (u8_t *)p->payload - header_size_increment;
+    /* boundary check fails? */
+    if ((u8_t *)p->payload < (u8_t *)p + sizeof(struct pbuf)) {
+      LWIP_DEBUGF( PBUF_DEBUG | 2, ("pbuf_header: failed as %p < %p (not enough space for new header size)\n",
+        (void *)p->payload,
+        (void *)(p + 1)));\
+      /* restore old payload pointer */
+      p->payload = payload;
+      /* bail out unsuccesfully */
+      return 1;
+    }
+  /* pbuf types refering to external payloads? */
+  } else if (p->flags == PBUF_FLAG_REF || p->flags == PBUF_FLAG_ROM) {
+    /* hide a header in the payload? */
+    if ((header_size_increment < 0) && (header_size_increment - p->len <= 0)) {
+      /* increase payload pointer */
+      p->payload = (u8_t *)p->payload - header_size_increment;
+    } else {
+      /* cannot expand payload to front (yet!)
+       * bail out unsuccesfully */
+      return 1;
+    }
+  }
+  /* modify pbuf length fields */
+  p->len += header_size_increment;
+  p->tot_len += header_size_increment;
+
+  LWIP_DEBUGF( PBUF_DEBUG, ("pbuf_header: old %p new %p (%"S16_F")\n",
+    (void *)payload, (void *)p->payload, header_size_increment));
+
+  return 0;
+}
+
+/**
+ * Dereference a pbuf chain or queue and deallocate any no-longer-used
+ * pbufs at the head of this chain or queue.
+ *
+ * Decrements the pbuf reference count. If it reaches zero, the pbuf is
+ * deallocated.
+ *
+ * For a pbuf chain, this is repeated for each pbuf in the chain,
+ * up to the first pbuf which has a non-zero reference count after
+ * decrementing. So, when all reference counts are one, the whole
+ * chain is free'd.
+ *
+ * @param pbuf The pbuf (chain) to be dereferenced.
+ *
+ * @return the number of pbufs that were de-allocated
+ * from the head of the chain.
+ *
+ * @note MUST NOT be called on a packet queue (Not verified to work yet).
+ * @note the reference counter of a pbuf equals the number of pointers
+ * that refer to the pbuf (or into the pbuf).
+ *
+ * @internal examples:
+ *
+ * Assuming existing chains a->b->c with the following reference
+ * counts, calling pbuf_free(a) results in:
+ * 
+ * 1->2->3 becomes ...1->3
+ * 3->3->3 becomes 2->3->3
+ * 1->1->2 becomes ......1
+ * 2->1->1 becomes 1->1->1
+ * 1->1->1 becomes .......
+ *
+ */
+u8_t
+pbuf_free(struct pbuf *p)
+{
+  struct pbuf *q;
+  u8_t count;
+  SYS_ARCH_DECL_PROTECT(old_level);
+
+  LWIP_ASSERT("p != NULL", p != NULL);
+  /* if assertions are disabled, proceed with debug output */
+  if (p == NULL) {
+    LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_free(p == NULL) was called.\n"));
+    return 0;
+  }
+  LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_free(%p)\n", (void *)p));
+
+  PERF_START;
+
+  LWIP_ASSERT("pbuf_free: sane flags",
+    p->flags == PBUF_FLAG_RAM || p->flags == PBUF_FLAG_ROM ||
+    p->flags == PBUF_FLAG_REF || p->flags == PBUF_FLAG_POOL);
+
+  count = 0;
+  /* Since decrementing ref cannot be guaranteed to be a single machine operation
+   * we must protect it. Also, the later test of ref must be protected.
+   */
+  SYS_ARCH_PROTECT(old_level);
+  /* de-allocate all consecutive pbufs from the head of the chain that
+   * obtain a zero reference count after decrementing*/
+  while (p != NULL) {
+    /* all pbufs in a chain are referenced at least once */
+    LWIP_ASSERT("pbuf_free: p->ref > 0", p->ref > 0);
+    /* decrease reference count (number of pointers to pbuf) */
+    p->ref--;
+    /* this pbuf is no longer referenced to? */
+    if (p->ref == 0) {
+      /* remember next pbuf in chain for next iteration */
+      q = p->next;
+      LWIP_DEBUGF( PBUF_DEBUG | 2, ("pbuf_free: deallocating %p\n", (void *)p));
+      /* is this a pbuf from the pool? */
+      if (p->flags == PBUF_FLAG_POOL) {
+        p->len = p->tot_len = PBUF_POOL_BUFSIZE;
+        p->payload = (void *)((u8_t *)p + sizeof(struct pbuf));
+        PBUF_POOL_FREE(p);
+      /* is this a ROM or RAM referencing pbuf? */
+      } else if (p->flags == PBUF_FLAG_ROM || p->flags == PBUF_FLAG_REF) {
+        memp_free(MEMP_PBUF, p);
+      /* p->flags == PBUF_FLAG_RAM */
+      } else {
+        mem_free(p);
+      }
+      count++;
+      /* proceed to next pbuf */
+      p = q;
+    /* p->ref > 0, this pbuf is still referenced to */
+    /* (and so the remaining pbufs in chain as well) */
+    } else {
+      LWIP_DEBUGF( PBUF_DEBUG | 2, ("pbuf_free: %p has ref %"U16_F", ending here.\n", (void *)p, (u16_t)p->ref));
+      /* stop walking through the chain */
+      p = NULL;
+    }
+  }
+  SYS_ARCH_UNPROTECT(old_level);
+  PERF_STOP("pbuf_free");
+  /* return number of de-allocated pbufs */
+  return count;
+}
+
+/**
+ * Count number of pbufs in a chain
+ *
+ * @param p first pbuf of chain
+ * @return the number of pbufs in a chain
+ */
+
+u8_t
+pbuf_clen(struct pbuf *p)
+{
+  u8_t len;
+
+  len = 0;
+  while (p != NULL) {
+    ++len;
+    p = p->next;
+  }
+  return len;
+}
+
+/**
+ * Increment the reference count of the pbuf.
+ *
+ * @param p pbuf to increase reference counter of
+ *
+ */
+void
+pbuf_ref(struct pbuf *p)
+{
+  SYS_ARCH_DECL_PROTECT(old_level);
+  /* pbuf given? */
+  if (p != NULL) {
+    SYS_ARCH_PROTECT(old_level);
+    ++(p->ref);
+    SYS_ARCH_UNPROTECT(old_level);
+  }
+}
+
+/**
+ * Concatenate two pbufs (each may be a pbuf chain) and take over
+ * the caller's reference of the tail pbuf.
+ * 
+ * @note The caller MAY NOT reference the tail pbuf afterwards.
+ * Use pbuf_chain() for that purpose.
+ * 
+ * @see pbuf_chain()
+ */
+
+void
+pbuf_cat(struct pbuf *h, struct pbuf *t)
+{
+  struct pbuf *p;
+
+  LWIP_ASSERT("h != NULL (programmer violates API)", h != NULL);
+  LWIP_ASSERT("t != NULL (programmer violates API)", t != NULL);
+  if ((h == NULL) || (t == NULL)) return;
+
+  /* proceed to last pbuf of chain */
+  for (p = h; p->next != NULL; p = p->next) {
+    /* add total length of second chain to all totals of first chain */
+    p->tot_len += t->tot_len;
+  }
+  /* { p is last pbuf of first h chain, p->next == NULL } */
+  LWIP_ASSERT("p->tot_len == p->len (of last pbuf in chain)", p->tot_len == p->len);
+  LWIP_ASSERT("p->next == NULL", p->next == NULL);
+  /* add total length of second chain to last pbuf total of first chain */
+  p->tot_len += t->tot_len;
+  /* chain last pbuf of head (p) with first of tail (t) */
+  p->next = t;
+  /* p->next now references t, but the caller will drop its reference to t,
+   * so netto there is no change to the reference count of t.
+   */
+}
+
+/**
+ * Chain two pbufs (or pbuf chains) together.
+ * 
+ * The caller MUST call pbuf_free(t) once it has stopped
+ * using it. Use pbuf_cat() instead if you no longer use t.
+ * 
+ * @param h head pbuf (chain)
+ * @param t tail pbuf (chain)
+ * @note The pbufs MUST belong to the same packet.
+ * @note MAY NOT be called on a packet queue.
+ *
+ * The ->tot_len fields of all pbufs of the head chain are adjusted.
+ * The ->next field of the last pbuf of the head chain is adjusted.
+ * The ->ref field of the first pbuf of the tail chain is adjusted.
+ *
+ */
+void
+pbuf_chain(struct pbuf *h, struct pbuf *t)
+{
+  pbuf_cat(h, t);
+  /* t is now referenced by h */
+  pbuf_ref(t);
+  LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2, ("pbuf_chain: %p references %p\n", (void *)h, (void *)t));
+}
+
+/* For packet queueing. Note that queued packets MUST be dequeued first
+ * using pbuf_dequeue() before calling other pbuf_() functions. */
+#if ARP_QUEUEING
+/**
+ * Add a packet to the end of a queue.
+ *
+ * @param q pointer to first packet on the queue
+ * @param n packet to be queued
+ *
+ * Both packets MUST be given, and must be different.
+ */
+void
+pbuf_queue(struct pbuf *p, struct pbuf *n)
+{
+#if PBUF_DEBUG /* remember head of queue */
+  struct pbuf *q = p;
+#endif
+  /* programmer stupidity checks */
+  LWIP_ASSERT("p == NULL in pbuf_queue: this indicates a programmer error\n", p != NULL);
+  LWIP_ASSERT("n == NULL in pbuf_queue: this indicates a programmer error\n", n != NULL);
+  LWIP_ASSERT("p == n in pbuf_queue: this indicates a programmer error\n", p != n);
+  if ((p == NULL) || (n == NULL) || (p == n)){
+    LWIP_DEBUGF(PBUF_DEBUG | DBG_HALT | 3, ("pbuf_queue: programmer argument error\n"));
+    return;
+  }
+
+  /* iterate through all packets on queue */
+  while (p->next != NULL) {
+/* be very picky about pbuf chain correctness */
+#if PBUF_DEBUG
+    /* iterate through all pbufs in packet */
+    while (p->tot_len != p->len) {
+      /* make sure invariant condition holds */
+      LWIP_ASSERT("p->len < p->tot_len", p->len < p->tot_len);
+      /* make sure each packet is complete */
+      LWIP_ASSERT("p->next != NULL", p->next != NULL);
+      p = p->next;
+      /* { p->tot_len == p->len => p is last pbuf of a packet } */
+    }
+    /* { p is last pbuf of a packet } */
+    /* proceed to next packet on queue */
+#endif
+    /* proceed to next pbuf */
+    if (p->next != NULL) p = p->next;
+  }
+  /* { p->tot_len == p->len and p->next == NULL } ==>
+   * { p is last pbuf of last packet on queue } */
+  /* chain last pbuf of queue with n */
+  p->next = n;
+  /* n is now referenced to by the (packet p in the) queue */
+  pbuf_ref(n);
+#if PBUF_DEBUG
+  LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2,
+    ("pbuf_queue: newly queued packet %p sits after packet %p in queue %p\n",
+    (void *)n, (void *)p, (void *)q));
+#endif
+}
+
+/**
+ * Remove a packet from the head of a queue.
+ *
+ * The caller MUST reference the remainder of the queue (as returned). The
+ * caller MUST NOT call pbuf_ref() as it implicitly takes over the reference
+ * from p.
+ * 
+ * @param p pointer to first packet on the queue which will be dequeued.
+ * @return first packet on the remaining queue (NULL if no further packets).
+ *
+ */
+struct pbuf *
+pbuf_dequeue(struct pbuf *p)
+{
+  struct pbuf *q;
+  LWIP_ASSERT("p != NULL", p != NULL);
+
+  /* iterate through all pbufs in packet p */
+  while (p->tot_len != p->len) {
+    /* make sure invariant condition holds */
+    LWIP_ASSERT("p->len < p->tot_len", p->len < p->tot_len);
+    /* make sure each packet is complete */
+    LWIP_ASSERT("p->next != NULL", p->next != NULL);
+    p = p->next;
+  }
+  /* { p->tot_len == p->len } => p is the last pbuf of the first packet */
+  /* remember next packet on queue in q */
+  q = p->next;
+  /* dequeue packet p from queue */
+  p->next = NULL;
+  /* any next packet on queue? */
+  if (q != NULL) {
+    /* although q is no longer referenced by p, it MUST be referenced by
+     * the caller, who is maintaining this packet queue. So, we do not call
+     * pbuf_free(q) here, resulting in an implicit pbuf_ref(q) for the caller. */
+    LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2, ("pbuf_dequeue: first remaining packet on queue is %p\n", (void *)q));
+  } else {
+    LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2, ("pbuf_dequeue: no further packets on queue\n"));
+  }
+  return q;
+}
+#endif
+
+/**
+ *
+ * Create PBUF_POOL (or PBUF_RAM) copies of PBUF_REF pbufs.
+ *
+ * Used to queue packets on behalf of the lwIP stack, such as
+ * ARP based queueing.
+ *
+ * Go through a pbuf chain and replace any PBUF_REF buffers
+ * with PBUF_POOL (or PBUF_RAM) pbufs, each taking a copy of
+ * the referenced data.
+ *
+ * @note You MUST explicitly use p = pbuf_take(p);
+ * The pbuf you give as argument, may have been replaced
+ * by a (differently located) copy through pbuf_take()!
+ *
+ * @note Any replaced pbufs will be freed through pbuf_free().
+ * This may deallocate them if they become no longer referenced.
+ *
+ * @param p Head of pbuf chain to process
+ *
+ * @return Pointer to head of pbuf chain
+ */
+struct pbuf *
+pbuf_take(struct pbuf *p)
+{
+  struct pbuf *q , *prev, *head;
+  LWIP_ASSERT("pbuf_take: p != NULL\n", p != NULL);
+  LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_take(%p)\n", (void*)p));
+
+  prev = NULL;
+  head = p;
+  /* iterate through pbuf chain */
+  do
+  {
+    /* pbuf is of type PBUF_REF? */
+    if (p->flags == PBUF_FLAG_REF) {
+      LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE, ("pbuf_take: encountered PBUF_REF %p\n", (void *)p));
+      /* allocate a pbuf (w/ payload) fully in RAM */
+      /* PBUF_POOL buffers are faster if we can use them */
+      if (p->len <= PBUF_POOL_BUFSIZE) {
+        q = pbuf_alloc(PBUF_RAW, p->len, PBUF_POOL);
+        if (q == NULL) {
+          LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_take: Could not allocate PBUF_POOL\n"));
+        }
+      } else {
+        /* no replacement pbuf yet */
+        q = NULL;
+        LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_take: PBUF_POOL too small to replace PBUF_REF\n"));
+      }
+      /* no (large enough) PBUF_POOL was available? retry with PBUF_RAM */
+      if (q == NULL) {
+        q = pbuf_alloc(PBUF_RAW, p->len, PBUF_RAM);
+        if (q == NULL) {
+          LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_take: Could not allocate PBUF_RAM\n"));
+        }
+      }
+      /* replacement pbuf could be allocated? */
+      if (q != NULL)
+      {
+        /* copy p to q */
+        /* copy successor */
+        q->next = p->next;
+        /* remove linkage from original pbuf */
+        p->next = NULL;
+        /* remove linkage to original pbuf */
+        if (prev != NULL) {
+          /* prev->next == p at this point */
+          LWIP_ASSERT("prev->next == p", prev->next == p);
+          /* break chain and insert new pbuf instead */
+          prev->next = q;
+        /* prev == NULL, so we replaced the head pbuf of the chain */
+        } else {
+          head = q;
+        }
+        /* copy pbuf payload */
+        memcpy(q->payload, p->payload, p->len);
+        q->tot_len = p->tot_len;
+        q->len = p->len;
+        /* in case p was the first pbuf, it is no longer refered to by
+         * our caller, as the caller MUST do p = pbuf_take(p);
+         * in case p was not the first pbuf, it is no longer refered to
+         * by prev. we can safely free the pbuf here.
+         * (note that we have set p->next to NULL already so that
+         * we will not free the rest of the chain by accident.)
+         */
+        pbuf_free(p);
+        /* do not copy ref, since someone else might be using the old buffer */
+        LWIP_DEBUGF(PBUF_DEBUG, ("pbuf_take: replaced PBUF_REF %p with %p\n", (void *)p, (void *)q));
+        p = q;
+      } else {
+        /* deallocate chain */
+        pbuf_free(head);
+        LWIP_DEBUGF(PBUF_DEBUG | 2, ("pbuf_take: failed to allocate replacement pbuf for %p\n", (void *)p));
+        return NULL;
+      }
+    /* p->flags != PBUF_FLAG_REF */
+    } else {
+      LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 1, ("pbuf_take: skipping pbuf not of type PBUF_REF\n"));
+    }
+    /* remember this pbuf */
+    prev = p;
+    /* proceed to next pbuf in original chain */
+    p = p->next;
+  } while (p);
+  LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 1, ("pbuf_take: end of chain reached.\n"));
+
+  return head;
+}
+
+/**
+ * Dechains the first pbuf from its succeeding pbufs in the chain.
+ *
+ * Makes p->tot_len field equal to p->len.
+ * @param p pbuf to dechain
+ * @return remainder of the pbuf chain, or NULL if it was de-allocated.
+ * @note May not be called on a packet queue.
+ */
+struct pbuf *
+pbuf_dechain(struct pbuf *p)
+{
+  struct pbuf *q;
+  u8_t tail_gone = 1;
+  /* tail */
+  q = p->next;
+  /* pbuf has successor in chain? */
+  if (q != NULL) {
+    /* assert tot_len invariant: (p->tot_len == p->len + (p->next? p->next->tot_len: 0) */
+    LWIP_ASSERT("p->tot_len == p->len + q->tot_len", q->tot_len == p->tot_len - p->len);
+    /* enforce invariant if assertion is disabled */
+    q->tot_len = p->tot_len - p->len;
+    /* decouple pbuf from remainder */
+    p->next = NULL;
+    /* total length of pbuf p is its own length only */
+    p->tot_len = p->len;
+    /* q is no longer referenced by p, free it */
+    LWIP_DEBUGF(PBUF_DEBUG | DBG_STATE, ("pbuf_dechain: unreferencing %p\n", (void *)q));
+    tail_gone = pbuf_free(q);
+    if (tail_gone > 0) {
+      LWIP_DEBUGF(PBUF_DEBUG | DBG_STATE,
+                  ("pbuf_dechain: deallocated %p (as it is no longer referenced)\n", (void *)q));
+    }
+    /* return remaining tail or NULL if deallocated */
+  }
+  /* assert tot_len invariant: (p->tot_len == p->len + (p->next? p->next->tot_len: 0) */
+  LWIP_ASSERT("p->tot_len == p->len", p->tot_len == p->len);
+  return (tail_gone > 0? NULL: q);
+}
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/raw.c b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/raw.c
new file mode 100644
index 000000000..b0e18b015
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/raw.c
@@ -0,0 +1,326 @@
+/**
+ * @file
+ * 
+ * Implementation of raw protocol PCBs for low-level handling of
+ * different types of protocols besides (or overriding) those
+ * already available in lwIP.
+ *
+ */
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include 
+
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+#include "lwip/memp.h"
+#include "lwip/inet.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/raw.h"
+
+#include "lwip/stats.h"
+
+#include "arch/perf.h"
+#include "lwip/snmp.h"
+
+#if LWIP_RAW
+
+/** The list of RAW PCBs */
+static struct raw_pcb *raw_pcbs = NULL;
+
+void
+raw_init(void)
+{
+  raw_pcbs = NULL;
+}
+
+/**
+ * Determine if in incoming IP packet is covered by a RAW PCB
+ * and if so, pass it to a user-provided receive callback function.
+ *
+ * Given an incoming IP datagram (as a chain of pbufs) this function
+ * finds a corresponding RAW PCB and calls the corresponding receive
+ * callback function.
+ *
+ * @param pbuf pbuf to be demultiplexed to a RAW PCB.
+ * @param netif network interface on which the datagram was received.
+ * @Return - 1 if the packet has been eaten by a RAW PCB receive
+ *           callback function. The caller MAY NOT not reference the
+ *           packet any longer, and MAY NOT call pbuf_free().
+ * @return - 0 if packet is not eaten (pbuf is still referenced by the
+ *           caller).
+ *
+ */
+u8_t
+raw_input(struct pbuf *p, struct netif *inp)
+{
+  struct raw_pcb *pcb;
+  struct ip_hdr *iphdr;
+  s16_t proto;
+  u8_t eaten = 0;
+
+  iphdr = p->payload;
+  proto = IPH_PROTO(iphdr);
+
+  pcb = raw_pcbs;
+  /* loop through all raw pcbs until the packet is eaten by one */
+  /* this allows multiple pcbs to match against the packet by design */
+  while ((eaten == 0) && (pcb != NULL)) {
+    if (pcb->protocol == proto) {
+      /* receive callback function available? */
+      if (pcb->recv != NULL) {
+        /* the receive callback function did not eat the packet? */
+        if (pcb->recv(pcb->recv_arg, pcb, p, &(iphdr->src)) != 0)
+        {
+          /* receive function ate the packet */
+          p = NULL;
+          eaten = 1;
+        }
+      }
+      /* no receive callback function was set for this raw PCB */
+      /* drop the packet */
+    }
+    pcb = pcb->next;
+  }
+  return eaten;
+}
+
+/**
+ * Bind a RAW PCB.
+ *
+ * @param pcb RAW PCB to be bound with a local address ipaddr.
+ * @param ipaddr local IP address to bind with. Use IP_ADDR_ANY to
+ * bind to all local interfaces.
+ *
+ * @return lwIP error code.
+ * - ERR_OK. Successful. No error occured.
+ * - ERR_USE. The specified IP address is already bound to by
+ * another RAW PCB.
+ *
+ * @see raw_disconnect()
+ */
+err_t
+raw_bind(struct raw_pcb *pcb, struct ip_addr *ipaddr)
+{
+  ip_addr_set(&pcb->local_ip, ipaddr);
+  return ERR_OK;
+}
+
+/**
+ * Connect an RAW PCB. This function is required by upper layers
+ * of lwip. Using the raw api you could use raw_sendto() instead
+ *
+ * This will associate the RAW PCB with the remote address.
+ *
+ * @param pcb RAW PCB to be connected with remote address ipaddr and port.
+ * @param ipaddr remote IP address to connect with.
+ *
+ * @return lwIP error code
+ *
+ * @see raw_disconnect() and raw_sendto()
+ */
+err_t
+raw_connect(struct raw_pcb *pcb, struct ip_addr *ipaddr)
+{
+  ip_addr_set(&pcb->remote_ip, ipaddr);
+  return ERR_OK;
+}
+
+
+/**
+ * Set the callback function for received packets that match the
+ * raw PCB's protocol and binding. 
+ * 
+ * The callback function MUST either
+ * - eat the packet by calling pbuf_free() and returning non-zero. The
+ *   packet will not be passed to other raw PCBs or other protocol layers.
+ * - not free the packet, and return zero. The packet will be matched
+ *   against further PCBs and/or forwarded to another protocol layers.
+ * 
+ * @return non-zero if the packet was free()d, zero if the packet remains
+ * available for others.
+ */
+void
+raw_recv(struct raw_pcb *pcb,
+         u8_t (* recv)(void *arg, struct raw_pcb *upcb, struct pbuf *p,
+                      struct ip_addr *addr),
+         void *recv_arg)
+{
+  /* remember recv() callback and user data */
+  pcb->recv = recv;
+  pcb->recv_arg = recv_arg;
+}
+
+/**
+ * Send the raw IP packet to the given address. Note that actually you cannot
+ * modify the IP headers (this is inconsistent with the receive callback where
+ * you actually get the IP headers), you can only specify the IP payload here.
+ * It requires some more changes in lwIP. (there will be a raw_send() function
+ * then.)
+ *
+ * @param pcb the raw pcb which to send
+ * @param p the IP payload to send
+ * @param ipaddr the destination address of the IP packet
+ *
+ */
+err_t
+raw_sendto(struct raw_pcb *pcb, struct pbuf *p, struct ip_addr *ipaddr)
+{
+  err_t err;
+  struct netif *netif;
+  struct ip_addr *src_ip;
+  struct pbuf *q; /* q will be sent down the stack */
+  
+  LWIP_DEBUGF(RAW_DEBUG | DBG_TRACE | 3, ("raw_sendto\n"));
+  
+  /* not enough space to add an IP header to first pbuf in given p chain? */
+  if (pbuf_header(p, IP_HLEN)) {
+    /* allocate header in new pbuf */
+    q = pbuf_alloc(PBUF_IP, 0, PBUF_RAM);
+    /* new header pbuf could not be allocated? */
+    if (q == NULL) {
+      LWIP_DEBUGF(RAW_DEBUG | DBG_TRACE | 2, ("raw_sendto: could not allocate header\n"));
+      return ERR_MEM;
+    }
+    /* chain header q in front of given pbuf p */
+    pbuf_chain(q, p);
+    /* { first pbuf q points to header pbuf } */
+    LWIP_DEBUGF(RAW_DEBUG, ("raw_sendto: added header pbuf %p before given pbuf %p\n", (void *)q, (void *)p));
+  }  else {
+    /* first pbuf q equals given pbuf */
+    q = p;
+    pbuf_header(q, -IP_HLEN);
+  }
+  
+  if ((netif = ip_route(ipaddr)) == NULL) {
+    LWIP_DEBUGF(RAW_DEBUG | 1, ("raw_sendto: No route to 0x%"X32_F"\n", ipaddr->addr));
+#if RAW_STATS
+    /*    ++lwip_stats.raw.rterr;*/
+#endif /* RAW_STATS */
+    /* free any temporary header pbuf allocated by pbuf_header() */
+    if (q != p) {
+      pbuf_free(q);
+    }
+    return ERR_RTE;
+  }
+
+  if (ip_addr_isany(&pcb->local_ip)) {
+    /* use outgoing network interface IP address as source address */
+    src_ip = &(netif->ip_addr);
+  } else {
+    /* use RAW PCB local IP address as source address */
+    src_ip = &(pcb->local_ip);
+  }
+
+  err = ip_output_if (q, src_ip, ipaddr, pcb->ttl, pcb->tos, pcb->protocol, netif);
+
+  /* did we chain a header earlier? */
+  if (q != p) {
+    /* free the header */
+    pbuf_free(q);
+  }
+  return err;
+}
+
+/**
+ * Send the raw IP packet to the address given by raw_connect()
+ *
+ * @param pcb the raw pcb which to send
+ * @param p the IP payload to send
+ * @param ipaddr the destination address of the IP packet
+ *
+ */
+err_t
+raw_send(struct raw_pcb *pcb, struct pbuf *p)
+{
+  return raw_sendto(pcb, p, &pcb->remote_ip);
+}
+
+/**
+ * Remove an RAW PCB.
+ *
+ * @param pcb RAW PCB to be removed. The PCB is removed from the list of
+ * RAW PCB's and the data structure is freed from memory.
+ *
+ * @see raw_new()
+ */
+void
+raw_remove(struct raw_pcb *pcb)
+{
+  struct raw_pcb *pcb2;
+  /* pcb to be removed is first in list? */
+  if (raw_pcbs == pcb) {
+    /* make list start at 2nd pcb */
+    raw_pcbs = raw_pcbs->next;
+    /* pcb not 1st in list */
+  } else for(pcb2 = raw_pcbs; pcb2 != NULL; pcb2 = pcb2->next) {
+    /* find pcb in raw_pcbs list */
+    if (pcb2->next != NULL && pcb2->next == pcb) {
+      /* remove pcb from list */
+      pcb2->next = pcb->next;
+    }
+  }
+  memp_free(MEMP_RAW_PCB, pcb);
+}
+
+/**
+ * Create a RAW PCB.
+ *
+ * @return The RAW PCB which was created. NULL if the PCB data structure
+ * could not be allocated.
+ *
+ * @param proto the protocol number of the IPs payload (e.g. IP_PROTO_ICMP)
+ *
+ * @see raw_remove()
+ */
+struct raw_pcb *
+raw_new(u16_t proto) {
+  struct raw_pcb *pcb;
+
+  LWIP_DEBUGF(RAW_DEBUG | DBG_TRACE | 3, ("raw_new\n"));
+
+  pcb = memp_malloc(MEMP_RAW_PCB);
+  /* could allocate RAW PCB? */
+  if (pcb != NULL) {
+    /* initialize PCB to all zeroes */
+    memset(pcb, 0, sizeof(struct raw_pcb));
+    pcb->protocol = proto;
+    pcb->ttl = RAW_TTL;
+    pcb->next = raw_pcbs;
+    raw_pcbs = pcb;
+  }
+  return pcb;
+}
+
+#endif /* LWIP_RAW */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/stats.c b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/stats.c
new file mode 100644
index 000000000..148878186
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/stats.c
@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include 
+
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+
+#include "lwip/stats.h"
+#include "lwip/mem.h"
+
+
+#if LWIP_STATS
+struct stats_ lwip_stats;
+
+void
+stats_init(void)
+{
+  memset(&lwip_stats, 0, sizeof(struct stats_));
+}
+#if LWIP_STATS_DISPLAY
+void
+stats_display_proto(struct stats_proto *proto, char *name)
+{
+  LWIP_PLATFORM_DIAG(("\n%s\n\t", name));
+  LWIP_PLATFORM_DIAG(("xmit: %"S16_F"\n\t", proto->xmit)); 
+  LWIP_PLATFORM_DIAG(("rexmit: %"S16_F"\n\t", proto->rexmit)); 
+  LWIP_PLATFORM_DIAG(("recv: %"S16_F"\n\t", proto->recv)); 
+  LWIP_PLATFORM_DIAG(("fw: %"S16_F"\n\t", proto->fw)); 
+  LWIP_PLATFORM_DIAG(("drop: %"S16_F"\n\t", proto->drop)); 
+  LWIP_PLATFORM_DIAG(("chkerr: %"S16_F"\n\t", proto->chkerr)); 
+  LWIP_PLATFORM_DIAG(("lenerr: %"S16_F"\n\t", proto->lenerr)); 
+  LWIP_PLATFORM_DIAG(("memerr: %"S16_F"\n\t", proto->memerr)); 
+  LWIP_PLATFORM_DIAG(("rterr: %"S16_F"\n\t", proto->rterr)); 
+  LWIP_PLATFORM_DIAG(("proterr: %"S16_F"\n\t", proto->proterr)); 
+  LWIP_PLATFORM_DIAG(("opterr: %"S16_F"\n\t", proto->opterr)); 
+  LWIP_PLATFORM_DIAG(("err: %"S16_F"\n\t", proto->err)); 
+  LWIP_PLATFORM_DIAG(("cachehit: %"S16_F"\n", proto->cachehit)); 
+}
+
+void
+stats_display_pbuf(struct stats_pbuf *pbuf)
+{
+  LWIP_PLATFORM_DIAG(("\nPBUF\n\t"));
+  LWIP_PLATFORM_DIAG(("avail: %"S16_F"\n\t", pbuf->avail)); 
+  LWIP_PLATFORM_DIAG(("used: %"S16_F"\n\t", pbuf->used)); 
+  LWIP_PLATFORM_DIAG(("max: %"S16_F"\n\t", pbuf->max)); 
+  LWIP_PLATFORM_DIAG(("err: %"S16_F"\n\t", pbuf->err)); 
+  LWIP_PLATFORM_DIAG(("alloc_locked: %"S16_F"\n\t", pbuf->alloc_locked)); 
+  LWIP_PLATFORM_DIAG(("refresh_locked: %"S16_F"\n", pbuf->refresh_locked)); 
+}
+
+void
+stats_display_mem(struct stats_mem *mem, char *name)
+{
+  LWIP_PLATFORM_DIAG(("\n MEM %s\n\t", name));
+  LWIP_PLATFORM_DIAG(("avail: %"S16_F"\n\t", mem->avail)); 
+  LWIP_PLATFORM_DIAG(("used: %"S16_F"\n\t", mem->used)); 
+  LWIP_PLATFORM_DIAG(("max: %"S16_F"\n\t", mem->max)); 
+  LWIP_PLATFORM_DIAG(("err: %"S16_F"\n", mem->err));
+  
+}
+
+void
+stats_display(void)
+{
+  s16_t i;
+  char * memp_names[] = {"PBUF", "RAW_PCB", "UDP_PCB", "TCP_PCB", "TCP_PCB_LISTEN",
+	  		"TCP_SEG", "NETBUF", "NETCONN", "API_MSG", "TCP_MSG", "TIMEOUT"};
+  stats_display_proto(&lwip_stats.link, "LINK");
+  stats_display_proto(&lwip_stats.ip_frag, "IP_FRAG");
+  stats_display_proto(&lwip_stats.ip, "IP");
+  stats_display_proto(&lwip_stats.icmp, "ICMP");
+  stats_display_proto(&lwip_stats.udp, "UDP");
+  stats_display_proto(&lwip_stats.tcp, "TCP");
+  stats_display_pbuf(&lwip_stats.pbuf);
+  stats_display_mem(&lwip_stats.mem, "HEAP");
+  for (i = 0; i < MEMP_MAX; i++) {
+    stats_display_mem(&lwip_stats.memp[i], memp_names[i]);
+  }
+	
+}
+#endif /* LWIP_STATS_DISPLAY */
+#endif /* LWIP_STATS */
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/sys.c b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/sys.c
new file mode 100644
index 000000000..207808284
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/sys.c
@@ -0,0 +1,294 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/sys.h"
+#include "lwip/opt.h"
+#include "lwip/def.h"
+#include "lwip/memp.h"
+
+#if (NO_SYS == 0)
+
+struct sswt_cb
+{
+    s16_t timeflag;
+    sys_sem_t *psem;
+};
+
+
+
+void
+sys_mbox_fetch(sys_mbox_t mbox, void **msg)
+{
+  u32_t time;
+  struct sys_timeouts *timeouts;
+  struct sys_timeout *tmptimeout;
+  sys_timeout_handler h;
+  void *arg;
+
+
+ again:
+  timeouts = sys_arch_timeouts();
+
+  if (!timeouts || !timeouts->next) {
+    sys_arch_mbox_fetch(mbox, msg, 0);
+  } else {
+    if (timeouts->next->time > 0) {
+      time = sys_arch_mbox_fetch(mbox, msg, timeouts->next->time);
+    } else {
+      time = SYS_ARCH_TIMEOUT;
+    }
+
+    if (time == SYS_ARCH_TIMEOUT) {
+      /* If time == SYS_ARCH_TIMEOUT, a timeout occured before a message
+   could be fetched. We should now call the timeout handler and
+   deallocate the memory allocated for the timeout. */
+      tmptimeout = timeouts->next;
+      timeouts->next = tmptimeout->next;
+      h = tmptimeout->h;
+      arg = tmptimeout->arg;
+      memp_free(MEMP_SYS_TIMEOUT, tmptimeout);
+      if (h != NULL) {
+        LWIP_DEBUGF(SYS_DEBUG, ("smf calling h=%p(%p)\n", (void *)h, (void *)arg));
+      	h(arg);
+      }
+
+      /* We try again to fetch a message from the mbox. */
+      goto again;
+    } else {
+      /* If time != SYS_ARCH_TIMEOUT, a message was received before the timeout
+   occured. The time variable is set to the number of
+   milliseconds we waited for the message. */
+      if (time <= timeouts->next->time) {
+  timeouts->next->time -= time;
+      } else {
+  timeouts->next->time = 0;
+      }
+    }
+
+  }
+}
+
+void
+sys_sem_wait(sys_sem_t sem)
+{
+  u32_t time;
+  struct sys_timeouts *timeouts;
+  struct sys_timeout *tmptimeout;
+  sys_timeout_handler h;
+  void *arg;
+
+  /*  while (sys_arch_sem_wait(sem, 1000) == 0);
+      return;*/
+
+ again:
+
+  timeouts = sys_arch_timeouts();
+
+  if (!timeouts || !timeouts->next) {
+    sys_arch_sem_wait(sem, 0);
+  } else {
+    if (timeouts->next->time > 0) {
+      time = sys_arch_sem_wait(sem, timeouts->next->time);
+    } else {
+      time = SYS_ARCH_TIMEOUT;
+    }
+
+    if (time == SYS_ARCH_TIMEOUT) {
+      /* If time == SYS_ARCH_TIMEOUT, a timeout occured before a message
+   could be fetched. We should now call the timeout handler and
+   deallocate the memory allocated for the timeout. */
+      tmptimeout = timeouts->next;
+      timeouts->next = tmptimeout->next;
+      h = tmptimeout->h;
+      arg = tmptimeout->arg;
+      memp_free(MEMP_SYS_TIMEOUT, tmptimeout);
+      if (h != NULL) {
+        LWIP_DEBUGF(SYS_DEBUG, ("ssw h=%p(%p)\n", (void *)h, (void *)arg));
+        h(arg);
+      }
+
+
+      /* We try again to fetch a message from the mbox. */
+      goto again;
+    } else {
+      /* If time != SYS_ARCH_TIMEOUT, a message was received before the timeout
+   occured. The time variable is set to the number of
+   milliseconds we waited for the message. */
+      if (time <= timeouts->next->time) {
+  timeouts->next->time -= time;
+      } else {
+  timeouts->next->time = 0;
+      }
+    }
+
+  }
+}
+
+void
+sys_timeout(u32_t msecs, sys_timeout_handler h, void *arg)
+{
+  struct sys_timeouts *timeouts;
+  struct sys_timeout *timeout, *t;
+
+  timeout = memp_malloc(MEMP_SYS_TIMEOUT);
+  if (timeout == NULL) {
+    return;
+  }
+  timeout->next = NULL;
+  timeout->h = h;
+  timeout->arg = arg;
+  timeout->time = msecs;
+
+  timeouts = sys_arch_timeouts();
+
+  LWIP_DEBUGF(SYS_DEBUG, ("sys_timeout: %p msecs=%"U32_F" h=%p arg=%p\n",
+    (void *)timeout, msecs, (void *)h, (void *)arg));
+
+  LWIP_ASSERT("sys_timeout: timeouts != NULL", timeouts != NULL);
+
+  if (timeouts->next == NULL) {
+    timeouts->next = timeout;
+    return;
+  }
+
+  if (timeouts->next->time > msecs) {
+    timeouts->next->time -= msecs;
+    timeout->next = timeouts->next;
+    timeouts->next = timeout;
+  } else {
+    for(t = timeouts->next; t != NULL; t = t->next) {
+      timeout->time -= t->time;
+      if (t->next == NULL || t->next->time > timeout->time) {
+        if (t->next != NULL) {
+          t->next->time -= timeout->time;
+        }
+        timeout->next = t->next;
+        t->next = timeout;
+        break;
+      }
+    }
+  }
+
+}
+
+/* Go through timeout list (for this task only) and remove the first matching entry,
+   even though the timeout has not triggered yet.
+*/
+
+void
+sys_untimeout(sys_timeout_handler h, void *arg)
+{
+    struct sys_timeouts *timeouts;
+    struct sys_timeout *prev_t, *t;
+
+    timeouts = sys_arch_timeouts();
+
+    if (timeouts->next == NULL)
+        return;
+
+    for (t = timeouts->next, prev_t = NULL; t != NULL; prev_t = t, t = t->next)
+    {
+        if ((t->h == h) && (t->arg == arg))
+        {
+            /* We have a match */
+            /* Unlink from previous in list */
+            if (prev_t == NULL)
+                timeouts->next = t->next;
+            else
+                prev_t->next = t->next;
+            /* If not the last one, add time of this one back to next */
+            if (t->next != NULL)
+                t->next->time += t->time;
+            memp_free(MEMP_SYS_TIMEOUT, t);
+            return;
+        }
+    }
+    return;
+}
+
+
+
+
+
+static void
+sswt_handler(void *arg)
+{
+    struct sswt_cb *sswt_cb = (struct sswt_cb *) arg;
+
+    /* Timeout. Set flag to TRUE and signal semaphore */
+    sswt_cb->timeflag = 1;
+    sys_sem_signal(*(sswt_cb->psem));
+}
+
+/* Wait for a semaphore with timeout (specified in ms) */
+/* timeout = 0: wait forever */
+/* Returns 0 on timeout. 1 otherwise */
+
+int
+sys_sem_wait_timeout(sys_sem_t sem, u32_t timeout)
+{
+    struct sswt_cb sswt_cb;
+
+    sswt_cb.psem = &sem;
+    sswt_cb.timeflag = 0;
+
+    /* If timeout is zero, then just wait forever */
+    if (timeout > 0)
+        /* Create a timer and pass it the address of our flag */
+        sys_timeout(timeout, sswt_handler, &sswt_cb);
+    sys_sem_wait(sem);
+    /* Was it a timeout? */
+    if (sswt_cb.timeflag)
+    {
+        /* timeout */
+        return 0;
+    } else {
+        /* Not a timeout. Remove timeout entry */
+        sys_untimeout(sswt_handler, &sswt_cb);
+        return 1;
+    }
+
+}
+
+
+void
+sys_msleep(u32_t ms)
+{
+  sys_sem_t delaysem = sys_sem_new(0);
+
+  sys_sem_wait_timeout(delaysem, ms);
+
+  sys_sem_free(delaysem);
+}
+
+
+#endif /* NO_SYS */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/tcp.c b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/tcp.c
new file mode 100644
index 000000000..5ccccabfd
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/tcp.c
@@ -0,0 +1,1171 @@
+/**
+ * @file
+ *
+ * Transmission Control Protocol for IP
+ *
+ * This file contains common functions for the TCP implementation, such as functinos
+ * for manipulating the data structures and the TCP timer functions. TCP functions
+ * related to input and output is found in tcp_in.c and tcp_out.c respectively.
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include 
+
+#include "lwip/opt.h"
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+
+#include "lwip/tcp.h"
+#if LWIP_TCP
+
+/* Incremented every coarse grained timer shot
+   (typically every 500 ms, determined by TCP_COARSE_TIMEOUT). */
+u32_t tcp_ticks;
+const u8_t tcp_backoff[13] =
+    { 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7};
+
+/* The TCP PCB lists. */
+
+/** List of all TCP PCBs in LISTEN state */
+union tcp_listen_pcbs_t tcp_listen_pcbs;
+/** List of all TCP PCBs that are in a state in which
+ * they accept or send data. */
+struct tcp_pcb *tcp_active_pcbs;  
+/** List of all TCP PCBs in TIME-WAIT state */
+struct tcp_pcb *tcp_tw_pcbs;
+
+struct tcp_pcb *tcp_tmp_pcb;
+
+static u8_t tcp_timer;
+static u16_t tcp_new_port(void);
+
+/**
+ * Initializes the TCP layer.
+ */
+void
+tcp_init(void)
+{
+  /* Clear globals. */
+  tcp_listen_pcbs.listen_pcbs = NULL;
+  tcp_active_pcbs = NULL;
+  tcp_tw_pcbs = NULL;
+  tcp_tmp_pcb = NULL;
+  
+  /* initialize timer */
+  tcp_ticks = 0;
+  tcp_timer = 0;
+  
+}
+
+/**
+ * Called periodically to dispatch TCP timers.
+ *
+ */
+void
+tcp_tmr(void)
+{
+  /* Call tcp_fasttmr() every 250 ms */
+  tcp_fasttmr();
+
+  if (++tcp_timer & 1) {
+    /* Call tcp_tmr() every 500 ms, i.e., every other timer
+       tcp_tmr() is called. */
+    tcp_slowtmr();
+  }
+}
+
+/**
+ * Closes the connection held by the PCB.
+ *
+ */
+err_t
+tcp_close(struct tcp_pcb *pcb)
+{
+  err_t err;
+
+#if TCP_DEBUG
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_close: closing in state "));
+  tcp_debug_print_state(pcb->state);
+  LWIP_DEBUGF(TCP_DEBUG, ("\n"));
+#endif /* TCP_DEBUG */
+  switch (pcb->state) {
+  case CLOSED:
+    /* Closing a pcb in the CLOSED state might seem erroneous,
+     * however, it is in this state once allocated and as yet unused
+     * and the user needs some way to free it should the need arise.
+     * Calling tcp_close() with a pcb that has already been closed, (i.e. twice)
+     * or for a pcb that has been used and then entered the CLOSED state 
+     * is erroneous, but this should never happen as the pcb has in those cases
+     * been freed, and so any remaining handles are bogus. */
+    err = ERR_OK;
+    memp_free(MEMP_TCP_PCB, pcb);
+    pcb = NULL;
+    break;
+  case LISTEN:
+    err = ERR_OK;
+    tcp_pcb_remove((struct tcp_pcb **)&tcp_listen_pcbs.pcbs, pcb);
+    memp_free(MEMP_TCP_PCB_LISTEN, pcb);
+    pcb = NULL;
+    break;
+  case SYN_SENT:
+    err = ERR_OK;
+    tcp_pcb_remove(&tcp_active_pcbs, pcb);
+    memp_free(MEMP_TCP_PCB, pcb);
+    pcb = NULL;
+    break;
+  case SYN_RCVD:
+  case ESTABLISHED:
+    err = tcp_send_ctrl(pcb, TCP_FIN);
+    if (err == ERR_OK) {
+      pcb->state = FIN_WAIT_1;
+    }
+    break;
+  case CLOSE_WAIT:
+    err = tcp_send_ctrl(pcb, TCP_FIN);
+    if (err == ERR_OK) {
+      pcb->state = LAST_ACK;
+    }
+    break;
+  default:
+    /* Has already been closed, do nothing. */
+    err = ERR_OK;
+    pcb = NULL;
+    break;
+  }
+
+  if (pcb != NULL && err == ERR_OK) {
+    err = tcp_output(pcb);
+  }
+  return err;
+}
+
+/**
+ * Aborts a connection by sending a RST to the remote host and deletes
+ * the local protocol control block. This is done when a connection is
+ * killed because of shortage of memory.
+ *
+ */
+void
+tcp_abort(struct tcp_pcb *pcb)
+{
+  u32_t seqno, ackno;
+  u16_t remote_port, local_port;
+  struct ip_addr remote_ip, local_ip;
+#if LWIP_CALLBACK_API  
+  void (* errf)(void *arg, err_t err);
+#endif /* LWIP_CALLBACK_API */
+  void *errf_arg;
+
+  
+  /* Figure out on which TCP PCB list we are, and remove us. If we
+     are in an active state, call the receive function associated with
+     the PCB with a NULL argument, and send an RST to the remote end. */
+  if (pcb->state == TIME_WAIT) {
+    tcp_pcb_remove(&tcp_tw_pcbs, pcb);
+    memp_free(MEMP_TCP_PCB, pcb);
+  } else {
+    seqno = pcb->snd_nxt;
+    ackno = pcb->rcv_nxt;
+    ip_addr_set(&local_ip, &(pcb->local_ip));
+    ip_addr_set(&remote_ip, &(pcb->remote_ip));
+    local_port = pcb->local_port;
+    remote_port = pcb->remote_port;
+#if LWIP_CALLBACK_API
+    errf = pcb->errf;
+#endif /* LWIP_CALLBACK_API */
+    errf_arg = pcb->callback_arg;
+    tcp_pcb_remove(&tcp_active_pcbs, pcb);
+    if (pcb->unacked != NULL) {
+      tcp_segs_free(pcb->unacked);
+    }
+    if (pcb->unsent != NULL) {
+      tcp_segs_free(pcb->unsent);
+    }
+#if TCP_QUEUE_OOSEQ    
+    if (pcb->ooseq != NULL) {
+      tcp_segs_free(pcb->ooseq);
+    }
+#endif /* TCP_QUEUE_OOSEQ */
+    memp_free(MEMP_TCP_PCB, pcb);
+    TCP_EVENT_ERR(errf, errf_arg, ERR_ABRT);
+    LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_abort: sending RST\n"));
+    tcp_rst(seqno, ackno, &local_ip, &remote_ip, local_port, remote_port);
+  }
+}
+
+/**
+ * Binds the connection to a local portnumber and IP address. If the
+ * IP address is not given (i.e., ipaddr == NULL), the IP address of
+ * the outgoing network interface is used instead.
+ *
+ */
+
+err_t
+tcp_bind(struct tcp_pcb *pcb, struct ip_addr *ipaddr, u16_t port)
+{
+  struct tcp_pcb *cpcb;
+
+  if (port == 0) {
+    port = tcp_new_port();
+  }
+  /* Check if the address already is in use. */
+  for(cpcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs;
+      cpcb != NULL; cpcb = cpcb->next) {
+    if (cpcb->local_port == port) {
+      if (ip_addr_isany(&(cpcb->local_ip)) ||
+        ip_addr_isany(ipaddr) ||
+        ip_addr_cmp(&(cpcb->local_ip), ipaddr)) {
+          return ERR_USE;
+      }
+    }
+  }
+  for(cpcb = tcp_active_pcbs;
+      cpcb != NULL; cpcb = cpcb->next) {
+    if (cpcb->local_port == port) {
+      if (ip_addr_isany(&(cpcb->local_ip)) ||
+   ip_addr_isany(ipaddr) ||
+   ip_addr_cmp(&(cpcb->local_ip), ipaddr)) {
+  return ERR_USE;
+      }
+    }
+  }
+
+  if (!ip_addr_isany(ipaddr)) {
+    pcb->local_ip = *ipaddr;
+  }
+  pcb->local_port = port;
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: bind to port %"U16_F"\n", port));
+  return ERR_OK;
+}
+#if LWIP_CALLBACK_API
+static err_t
+tcp_accept_null(void *arg, struct tcp_pcb *pcb, err_t err)
+{
+  (void)arg;
+  (void)pcb;
+  (void)err;
+
+  return ERR_ABRT;
+}
+#endif /* LWIP_CALLBACK_API */
+
+/**
+ * Set the state of the connection to be LISTEN, which means that it
+ * is able to accept incoming connections. The protocol control block
+ * is reallocated in order to consume less memory. Setting the
+ * connection to LISTEN is an irreversible process.
+ *
+ */
+struct tcp_pcb *
+tcp_listen(struct tcp_pcb *pcb)
+{
+  struct tcp_pcb_listen *lpcb;
+
+  /* already listening? */
+  if (pcb->state == LISTEN) {
+    return pcb;
+  }
+  lpcb = memp_malloc(MEMP_TCP_PCB_LISTEN);
+  if (lpcb == NULL) {
+    return NULL;
+  }
+  lpcb->callback_arg = pcb->callback_arg;
+  lpcb->local_port = pcb->local_port;
+  lpcb->state = LISTEN;
+  lpcb->so_options = pcb->so_options;
+  lpcb->so_options |= SOF_ACCEPTCONN;
+  lpcb->ttl = pcb->ttl;
+  lpcb->tos = pcb->tos;
+  ip_addr_set(&lpcb->local_ip, &pcb->local_ip);
+  memp_free(MEMP_TCP_PCB, pcb);
+#if LWIP_CALLBACK_API
+  lpcb->accept = tcp_accept_null;
+#endif /* LWIP_CALLBACK_API */
+  TCP_REG(&tcp_listen_pcbs.listen_pcbs, lpcb);
+  return (struct tcp_pcb *)lpcb;
+}
+
+/**
+ * This function should be called by the application when it has
+ * processed the data. The purpose is to advertise a larger window
+ * when the data has been processed.
+ *
+ */
+void
+tcp_recved(struct tcp_pcb *pcb, u16_t len)
+{
+  if ((u32_t)pcb->rcv_wnd + len > TCP_WND) {
+    pcb->rcv_wnd = TCP_WND;
+  } else {
+    pcb->rcv_wnd += len;
+  }
+  if (!(pcb->flags & TF_ACK_DELAY) &&
+     !(pcb->flags & TF_ACK_NOW)) {
+    /*
+     * We send an ACK here (if one is not already pending, hence
+     * the above tests) as tcp_recved() implies that the application
+     * has processed some data, and so we can open the receiver's
+     * window to allow more to be transmitted.  This could result in
+     * two ACKs being sent for each received packet in some limited cases
+     * (where the application is only receiving data, and is slow to
+     * process it) but it is necessary to guarantee that the sender can
+     * continue to transmit.
+     */
+    tcp_ack(pcb);
+  } 
+  else if (pcb->flags & TF_ACK_DELAY && pcb->rcv_wnd >= TCP_WND/2) {
+    /* If we can send a window update such that there is a full
+     * segment available in the window, do so now.  This is sort of
+     * nagle-like in its goals, and tries to hit a compromise between
+     * sending acks each time the window is updated, and only sending
+     * window updates when a timer expires.  The "threshold" used
+     * above (currently TCP_WND/2) can be tuned to be more or less
+     * aggressive  */
+    tcp_ack_now(pcb);
+  }
+
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_recved: recveived %"U16_F" bytes, wnd %"U16_F" (%"U16_F").\n",
+         len, pcb->rcv_wnd, TCP_WND - pcb->rcv_wnd));
+}
+
+/**
+ * A nastly hack featuring 'goto' statements that allocates a
+ * new TCP local port.
+ */
+static u16_t
+tcp_new_port(void)
+{
+  struct tcp_pcb *pcb;
+#ifndef TCP_LOCAL_PORT_RANGE_START
+#define TCP_LOCAL_PORT_RANGE_START 4096
+#define TCP_LOCAL_PORT_RANGE_END   0x7fff
+#endif
+  static u16_t port = TCP_LOCAL_PORT_RANGE_START;
+  
+ again:
+  if (++port > TCP_LOCAL_PORT_RANGE_END) {
+    port = TCP_LOCAL_PORT_RANGE_START;
+  }
+  
+  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+    if (pcb->local_port == port) {
+      goto again;
+    }
+  }
+  for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
+    if (pcb->local_port == port) {
+      goto again;
+    }
+  }
+  for(pcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs; pcb != NULL; pcb = pcb->next) {
+    if (pcb->local_port == port) {
+      goto again;
+    }
+  }
+  return port;
+}
+
+/**
+ * Connects to another host. The function given as the "connected"
+ * argument will be called when the connection has been established.
+ *
+ */
+err_t
+tcp_connect(struct tcp_pcb *pcb, struct ip_addr *ipaddr, u16_t port,
+      err_t (* connected)(void *arg, struct tcp_pcb *tpcb, err_t err))
+{
+  u32_t optdata;
+  err_t ret;
+  u32_t iss;
+
+  LWIP_DEBUGF(TCP_DEBUG, ("tcp_connect to port %"U16_F"\n", port));
+  if (ipaddr != NULL) {
+    pcb->remote_ip = *ipaddr;
+  } else {
+    return ERR_VAL;
+  }
+  pcb->remote_port = port;
+  if (pcb->local_port == 0) {
+    pcb->local_port = tcp_new_port();
+  }
+  iss = tcp_next_iss();
+  pcb->rcv_nxt = 0;
+  pcb->snd_nxt = iss;
+  pcb->lastack = iss - 1;
+  pcb->snd_lbb = iss - 1;
+  pcb->rcv_wnd = TCP_WND;
+  pcb->snd_wnd = TCP_WND;
+  pcb->mss = TCP_MSS;
+  pcb->cwnd = 1;
+  pcb->ssthresh = pcb->mss * 10;
+  pcb->state = SYN_SENT;
+#if LWIP_CALLBACK_API  
+  pcb->connected = connected;
+#endif /* LWIP_CALLBACK_API */  
+  TCP_REG(&tcp_active_pcbs, pcb);
+  
+  /* Build an MSS option */
+  optdata = htonl(((u32_t)2 << 24) | 
+      ((u32_t)4 << 16) | 
+      (((u32_t)pcb->mss / 256) << 8) |
+      (pcb->mss & 255));
+
+  ret = tcp_enqueue(pcb, NULL, 0, TCP_SYN, 0, (u8_t *)&optdata, 4);
+  if (ret == ERR_OK) { 
+    tcp_output(pcb);
+  }
+  return ret;
+} 
+
+/**
+ * Called every 500 ms and implements the retransmission timer and the timer that
+ * removes PCBs that have been in TIME-WAIT for enough time. It also increments
+ * various timers such as the inactivity timer in each PCB.
+ */
+void
+tcp_slowtmr(void)
+{
+  struct tcp_pcb *pcb, *pcb2, *prev;
+  u32_t eff_wnd;
+  u8_t pcb_remove;      /* flag if a PCB should be removed */
+  err_t err;
+
+  err = ERR_OK;
+
+  ++tcp_ticks;
+
+  /* Steps through all of the active PCBs. */
+  prev = NULL;
+  pcb = tcp_active_pcbs;
+  if (pcb == NULL) {
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: no active pcbs\n"));
+  }
+  while (pcb != NULL) {
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: processing active pcb\n"));
+    LWIP_ASSERT("tcp_slowtmr: active pcb->state != CLOSED\n", pcb->state != CLOSED);
+    LWIP_ASSERT("tcp_slowtmr: active pcb->state != LISTEN\n", pcb->state != LISTEN);
+    LWIP_ASSERT("tcp_slowtmr: active pcb->state != TIME-WAIT\n", pcb->state != TIME_WAIT);
+
+    pcb_remove = 0;
+
+    if (pcb->state == SYN_SENT && pcb->nrtx == TCP_SYNMAXRTX) {
+      ++pcb_remove;
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max SYN retries reached\n"));
+    }
+    else if (pcb->nrtx == TCP_MAXRTX) {
+      ++pcb_remove;
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max DATA retries reached\n"));
+    } else {
+      ++pcb->rtime;
+      if (pcb->unacked != NULL && pcb->rtime >= pcb->rto) {
+
+        /* Time for a retransmission. */
+        LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_slowtmr: rtime %"U16_F" pcb->rto %"U16_F"\n",
+          pcb->rtime, pcb->rto));
+
+        /* Double retransmission time-out unless we are trying to
+         * connect to somebody (i.e., we are in SYN_SENT). */
+        if (pcb->state != SYN_SENT) {
+          pcb->rto = ((pcb->sa >> 3) + pcb->sv) << tcp_backoff[pcb->nrtx];
+        }
+        /* Reduce congestion window and ssthresh. */
+        eff_wnd = LWIP_MIN(pcb->cwnd, pcb->snd_wnd);
+        pcb->ssthresh = eff_wnd >> 1;
+        if (pcb->ssthresh < pcb->mss) {
+          pcb->ssthresh = pcb->mss * 2;
+        }
+        pcb->cwnd = pcb->mss;
+        LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: cwnd %"U16_F" ssthresh %"U16_F"\n",
+                                pcb->cwnd, pcb->ssthresh));
+ 
+        /* The following needs to be called AFTER cwnd is set to one mss - STJ */
+        tcp_rexmit_rto(pcb);
+     }
+    }
+    /* Check if this PCB has stayed too long in FIN-WAIT-2 */
+    if (pcb->state == FIN_WAIT_2) {
+      if ((u32_t)(tcp_ticks - pcb->tmr) >
+        TCP_FIN_WAIT_TIMEOUT / TCP_SLOW_INTERVAL) {
+        ++pcb_remove;
+        LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in FIN-WAIT-2\n"));
+      }
+    }
+
+   /* Check if KEEPALIVE should be sent */
+   if((pcb->so_options & SOF_KEEPALIVE) && ((pcb->state == ESTABLISHED) || (pcb->state == CLOSE_WAIT))) {
+      if((u32_t)(tcp_ticks - pcb->tmr) > (pcb->keepalive + TCP_MAXIDLE) / TCP_SLOW_INTERVAL)  {
+         LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: KEEPALIVE timeout. Aborting connection to %"U16_F".%"U16_F".%"U16_F".%"U16_F".\n",
+                                 ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip),
+                                 ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip)));
+
+         tcp_abort(pcb);
+      }
+      else if((u32_t)(tcp_ticks - pcb->tmr) > (pcb->keepalive + pcb->keep_cnt * TCP_KEEPINTVL) / TCP_SLOW_INTERVAL) {
+         tcp_keepalive(pcb);
+         pcb->keep_cnt++;
+      }
+   }
+
+    /* If this PCB has queued out of sequence data, but has been
+       inactive for too long, will drop the data (it will eventually
+       be retransmitted). */
+#if TCP_QUEUE_OOSEQ    
+    if (pcb->ooseq != NULL &&
+       (u32_t)tcp_ticks - pcb->tmr >=
+       pcb->rto * TCP_OOSEQ_TIMEOUT) {
+      tcp_segs_free(pcb->ooseq);
+      pcb->ooseq = NULL;
+      LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: dropping OOSEQ queued data\n"));
+    }
+#endif /* TCP_QUEUE_OOSEQ */
+
+    /* Check if this PCB has stayed too long in SYN-RCVD */
+    if (pcb->state == SYN_RCVD) {
+      if ((u32_t)(tcp_ticks - pcb->tmr) >
+        TCP_SYN_RCVD_TIMEOUT / TCP_SLOW_INTERVAL) {
+        ++pcb_remove;
+        LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in SYN-RCVD\n"));
+      }
+    }
+
+    /* Check if this PCB has stayed too long in LAST-ACK */
+    if (pcb->state == LAST_ACK) {
+      if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) {
+        ++pcb_remove;
+        LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in LAST-ACK\n"));
+      }
+    }
+
+    /* If the PCB should be removed, do it. */
+    if (pcb_remove) {
+      tcp_pcb_purge(pcb);      
+      /* Remove PCB from tcp_active_pcbs list. */
+      if (prev != NULL) {
+  LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_active_pcbs", pcb != tcp_active_pcbs);
+        prev->next = pcb->next;
+      } else {
+        /* This PCB was the first. */
+        LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_active_pcbs", tcp_active_pcbs == pcb);
+        tcp_active_pcbs = pcb->next;
+      }
+
+      TCP_EVENT_ERR(pcb->errf, pcb->callback_arg, ERR_ABRT);
+
+      pcb2 = pcb->next;
+      memp_free(MEMP_TCP_PCB, pcb);
+      pcb = pcb2;
+    } else {
+
+      /* We check if we should poll the connection. */
+      ++pcb->polltmr;
+      if (pcb->polltmr >= pcb->pollinterval) {
+        pcb->polltmr = 0;
+        LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: polling application\n"));
+        TCP_EVENT_POLL(pcb, err);
+        if (err == ERR_OK) {
+          tcp_output(pcb);
+        }
+      }
+      
+      prev = pcb;
+      pcb = pcb->next;
+    }
+  }
+
+  
+  /* Steps through all of the TIME-WAIT PCBs. */
+  prev = NULL;    
+  pcb = tcp_tw_pcbs;
+  while (pcb != NULL) {
+    LWIP_ASSERT("tcp_slowtmr: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT);
+    pcb_remove = 0;
+
+    /* Check if this PCB has stayed long enough in TIME-WAIT */
+    if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) {
+      ++pcb_remove;
+    }
+    
+
+
+    /* If the PCB should be removed, do it. */
+    if (pcb_remove) {
+      tcp_pcb_purge(pcb);      
+      /* Remove PCB from tcp_tw_pcbs list. */
+      if (prev != NULL) {
+  LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_tw_pcbs", pcb != tcp_tw_pcbs);
+        prev->next = pcb->next;
+      } else {
+        /* This PCB was the first. */
+        LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_tw_pcbs", tcp_tw_pcbs == pcb);
+        tcp_tw_pcbs = pcb->next;
+      }
+      pcb2 = pcb->next;
+      memp_free(MEMP_TCP_PCB, pcb);
+      pcb = pcb2;
+    } else {
+      prev = pcb;
+      pcb = pcb->next;
+    }
+  }
+}
+
+/**
+ * Is called every TCP_FAST_INTERVAL (250 ms) and sends delayed ACKs.
+ */
+void
+tcp_fasttmr(void)
+{
+  struct tcp_pcb *pcb;
+
+  /* send delayed ACKs */  
+  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+    if (pcb->flags & TF_ACK_DELAY) {
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_fasttmr: delayed ACK\n"));
+      tcp_ack_now(pcb);
+      pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW);
+    }
+  }
+}
+
+/**
+ * Deallocates a list of TCP segments (tcp_seg structures).
+ *
+ */
+u8_t
+tcp_segs_free(struct tcp_seg *seg)
+{
+  u8_t count = 0;
+  struct tcp_seg *next;
+  while (seg != NULL) {
+    next = seg->next;
+    count += tcp_seg_free(seg);
+    seg = next;
+  }
+  return count;
+}
+
+/**
+ * Frees a TCP segment.
+ *
+ */
+u8_t
+tcp_seg_free(struct tcp_seg *seg)
+{
+  u8_t count = 0;
+  
+  if (seg != NULL) {
+    if (seg->p != NULL) {
+      count = pbuf_free(seg->p);
+#if TCP_DEBUG
+      seg->p = NULL;
+#endif /* TCP_DEBUG */
+    }
+    memp_free(MEMP_TCP_SEG, seg);
+  }
+  return count;
+}
+
+/**
+ * Sets the priority of a connection.
+ *
+ */
+void
+tcp_setprio(struct tcp_pcb *pcb, u8_t prio)
+{
+  pcb->prio = prio;
+}
+#if TCP_QUEUE_OOSEQ
+
+/**
+ * Returns a copy of the given TCP segment.
+ *
+ */ 
+struct tcp_seg *
+tcp_seg_copy(struct tcp_seg *seg)
+{
+  struct tcp_seg *cseg;
+
+  cseg = memp_malloc(MEMP_TCP_SEG);
+  if (cseg == NULL) {
+    return NULL;
+  }
+  memcpy((u8_t *)cseg, (const u8_t *)seg, sizeof(struct tcp_seg)); 
+  pbuf_ref(cseg->p);
+  return cseg;
+}
+#endif
+
+#if LWIP_CALLBACK_API
+static err_t
+tcp_recv_null(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err)
+{
+  arg = arg;
+  if (p != NULL) {
+    pbuf_free(p);
+  } else if (err == ERR_OK) {
+    return tcp_close(pcb);
+  }
+  return ERR_OK;
+}
+#endif /* LWIP_CALLBACK_API */
+
+static void
+tcp_kill_prio(u8_t prio)
+{
+  struct tcp_pcb *pcb, *inactive;
+  u32_t inactivity;
+  u8_t mprio;
+
+
+  mprio = TCP_PRIO_MAX;
+  
+  /* We kill the oldest active connection that has lower priority than
+     prio. */
+  inactivity = 0;
+  inactive = NULL;
+  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+    if (pcb->prio <= prio &&
+       pcb->prio <= mprio &&
+       (u32_t)(tcp_ticks - pcb->tmr) >= inactivity) {
+      inactivity = tcp_ticks - pcb->tmr;
+      inactive = pcb;
+      mprio = pcb->prio;
+    }
+  }
+  if (inactive != NULL) {
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_prio: killing oldest PCB %p (%"S32_F")\n",
+           (void *)inactive, inactivity));
+    tcp_abort(inactive);
+  }      
+}
+
+
+static void
+tcp_kill_timewait(void)
+{
+  struct tcp_pcb *pcb, *inactive;
+  u32_t inactivity;
+
+  inactivity = 0;
+  inactive = NULL;
+  for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
+    if ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity) {
+      inactivity = tcp_ticks - pcb->tmr;
+      inactive = pcb;
+    }
+  }
+  if (inactive != NULL) {
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_timewait: killing oldest TIME-WAIT PCB %p (%"S32_F")\n",
+           (void *)inactive, inactivity));
+    tcp_abort(inactive);
+  }      
+}
+
+
+
+struct tcp_pcb *
+tcp_alloc(u8_t prio)
+{
+  struct tcp_pcb *pcb;
+  u32_t iss;
+  
+  pcb = memp_malloc(MEMP_TCP_PCB);
+  if (pcb == NULL) {
+    /* Try killing oldest connection in TIME-WAIT. */
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest TIME-WAIT connection\n"));
+    tcp_kill_timewait();
+    pcb = memp_malloc(MEMP_TCP_PCB);
+    if (pcb == NULL) {
+      tcp_kill_prio(prio);    
+      pcb = memp_malloc(MEMP_TCP_PCB);
+    }
+  }
+  if (pcb != NULL) {
+    memset(pcb, 0, sizeof(struct tcp_pcb));
+    pcb->prio = TCP_PRIO_NORMAL;
+    pcb->snd_buf = TCP_SND_BUF;
+    pcb->snd_queuelen = 0;
+    pcb->rcv_wnd = TCP_WND;
+    pcb->tos = 0;
+    pcb->ttl = TCP_TTL;
+    pcb->mss = TCP_MSS;
+    pcb->rto = 3000 / TCP_SLOW_INTERVAL;
+    pcb->sa = 0;
+    pcb->sv = 3000 / TCP_SLOW_INTERVAL;
+    pcb->rtime = 0;
+    pcb->cwnd = 1;
+    iss = tcp_next_iss();
+    pcb->snd_wl2 = iss;
+    pcb->snd_nxt = iss;
+    pcb->snd_max = iss;
+    pcb->lastack = iss;
+    pcb->snd_lbb = iss;   
+    pcb->tmr = tcp_ticks;
+
+    pcb->polltmr = 0;
+
+#if LWIP_CALLBACK_API
+    pcb->recv = tcp_recv_null;
+#endif /* LWIP_CALLBACK_API */  
+    
+    /* Init KEEPALIVE timer */
+    pcb->keepalive = TCP_KEEPDEFAULT;
+    pcb->keep_cnt = 0;
+  }
+  return pcb;
+}
+
+/**
+ * Creates a new TCP protocol control block but doesn't place it on
+ * any of the TCP PCB lists.
+ *
+ * @internal: Maybe there should be a idle TCP PCB list where these
+ * PCBs are put on. We can then implement port reservation using
+ * tcp_bind(). Currently, we lack this (BSD socket type of) feature.
+ */
+
+struct tcp_pcb *
+tcp_new(void)
+{
+  return tcp_alloc(TCP_PRIO_NORMAL);
+}
+
+/*
+ * tcp_arg():
+ *
+ * Used to specify the argument that should be passed callback
+ * functions.
+ *
+ */ 
+
+void
+tcp_arg(struct tcp_pcb *pcb, void *arg)
+{  
+  pcb->callback_arg = arg;
+}
+#if LWIP_CALLBACK_API
+
+/**
+ * Used to specify the function that should be called when a TCP
+ * connection receives data.
+ *
+ */ 
+void
+tcp_recv(struct tcp_pcb *pcb,
+   err_t (* recv)(void *arg, struct tcp_pcb *tpcb, struct pbuf *p, err_t err))
+{
+  pcb->recv = recv;
+}
+
+/**
+ * Used to specify the function that should be called when TCP data
+ * has been successfully delivered to the remote host.
+ *
+ */ 
+
+void
+tcp_sent(struct tcp_pcb *pcb,
+   err_t (* sent)(void *arg, struct tcp_pcb *tpcb, u16_t len))
+{
+  pcb->sent = sent;
+}
+
+/**
+ * Used to specify the function that should be called when a fatal error
+ * has occured on the connection.
+ *
+ */ 
+void
+tcp_err(struct tcp_pcb *pcb,
+   void (* errf)(void *arg, err_t err))
+{
+  pcb->errf = errf;
+}
+
+/**
+ * Used for specifying the function that should be called when a
+ * LISTENing connection has been connected to another host.
+ *
+ */ 
+void
+tcp_accept(struct tcp_pcb *pcb,
+     err_t (* accept)(void *arg, struct tcp_pcb *newpcb, err_t err))
+{
+  ((struct tcp_pcb_listen *)pcb)->accept = accept;
+}
+#endif /* LWIP_CALLBACK_API */
+
+
+/**
+ * Used to specify the function that should be called periodically
+ * from TCP. The interval is specified in terms of the TCP coarse
+ * timer interval, which is called twice a second.
+ *
+ */ 
+void
+tcp_poll(struct tcp_pcb *pcb,
+   err_t (* poll)(void *arg, struct tcp_pcb *tpcb), u8_t interval)
+{
+#if LWIP_CALLBACK_API
+  pcb->poll = poll;
+#endif /* LWIP_CALLBACK_API */  
+  pcb->pollinterval = interval;
+}
+
+/**
+ * Purges a TCP PCB. Removes any buffered data and frees the buffer memory.
+ *
+ */
+void
+tcp_pcb_purge(struct tcp_pcb *pcb)
+{
+  if (pcb->state != CLOSED &&
+     pcb->state != TIME_WAIT &&
+     pcb->state != LISTEN) {
+
+    LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge\n"));
+    
+    if (pcb->unsent != NULL) {    
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: not all data sent\n"));
+    }
+    if (pcb->unacked != NULL) {    
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->unacked\n"));
+    }
+#if TCP_QUEUE_OOSEQ /* LW */
+    if (pcb->ooseq != NULL) {    
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->ooseq\n"));
+    }
+    
+    tcp_segs_free(pcb->ooseq);
+    pcb->ooseq = NULL;
+#endif /* TCP_QUEUE_OOSEQ */
+    tcp_segs_free(pcb->unsent);
+    tcp_segs_free(pcb->unacked);
+    pcb->unacked = pcb->unsent = NULL;
+  }
+}
+
+/**
+ * Purges the PCB and removes it from a PCB list. Any delayed ACKs are sent first.
+ *
+ */
+void
+tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb)
+{
+  TCP_RMV(pcblist, pcb);
+
+  tcp_pcb_purge(pcb);
+  
+  /* if there is an outstanding delayed ACKs, send it */
+  if (pcb->state != TIME_WAIT &&
+     pcb->state != LISTEN &&
+     pcb->flags & TF_ACK_DELAY) {
+    pcb->flags |= TF_ACK_NOW;
+    tcp_output(pcb);
+  }  
+  pcb->state = CLOSED;
+
+  LWIP_ASSERT("tcp_pcb_remove: tcp_pcbs_sane()", tcp_pcbs_sane());
+}
+
+/**
+ * Calculates a new initial sequence number for new connections.
+ *
+ */
+u32_t
+tcp_next_iss(void)
+{
+  static u32_t iss = 6510;
+  
+  iss += tcp_ticks;       /* XXX */
+  return iss;
+}
+
+#if TCP_DEBUG || TCP_INPUT_DEBUG || TCP_OUTPUT_DEBUG
+void
+tcp_debug_print(struct tcp_hdr *tcphdr)
+{
+  LWIP_DEBUGF(TCP_DEBUG, ("TCP header:\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("|    %5"U16_F"      |    %5"U16_F"      | (src port, dest port)\n",
+         ntohs(tcphdr->src), ntohs(tcphdr->dest)));
+  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("|           %010"U32_F"          | (seq no)\n",
+          ntohl(tcphdr->seqno)));
+  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("|           %010"U32_F"          | (ack no)\n",
+         ntohl(tcphdr->ackno)));
+  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("| %2"U16_F" |   |%"U16_F"%"U16_F"%"U16_F"%"U16_F"%"U16_F"%"U16_F"|     %5"U16_F"     | (hdrlen, flags (",
+       TCPH_HDRLEN(tcphdr),
+         TCPH_FLAGS(tcphdr) >> 5 & 1,
+         TCPH_FLAGS(tcphdr) >> 4 & 1,
+         TCPH_FLAGS(tcphdr) >> 3 & 1,
+         TCPH_FLAGS(tcphdr) >> 2 & 1,
+         TCPH_FLAGS(tcphdr) >> 1 & 1,
+         TCPH_FLAGS(tcphdr) & 1,
+         ntohs(tcphdr->wnd)));
+  tcp_debug_print_flags(TCPH_FLAGS(tcphdr));
+  LWIP_DEBUGF(TCP_DEBUG, ("), win)\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(TCP_DEBUG, ("|    0x%04"X16_F"     |     %5"U16_F"     | (chksum, urgp)\n",
+         ntohs(tcphdr->chksum), ntohs(tcphdr->urgp)));
+  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
+}
+
+void
+tcp_debug_print_state(enum tcp_state s)
+{
+  LWIP_DEBUGF(TCP_DEBUG, ("State: "));
+  switch (s) {
+  case CLOSED:
+    LWIP_DEBUGF(TCP_DEBUG, ("CLOSED\n"));
+    break;
+ case LISTEN:
+   LWIP_DEBUGF(TCP_DEBUG, ("LISTEN\n"));
+   break;
+  case SYN_SENT:
+    LWIP_DEBUGF(TCP_DEBUG, ("SYN_SENT\n"));
+    break;
+  case SYN_RCVD:
+    LWIP_DEBUGF(TCP_DEBUG, ("SYN_RCVD\n"));
+    break;
+  case ESTABLISHED:
+    LWIP_DEBUGF(TCP_DEBUG, ("ESTABLISHED\n"));
+    break;
+  case FIN_WAIT_1:
+    LWIP_DEBUGF(TCP_DEBUG, ("FIN_WAIT_1\n"));
+    break;
+  case FIN_WAIT_2:
+    LWIP_DEBUGF(TCP_DEBUG, ("FIN_WAIT_2\n"));
+    break;
+  case CLOSE_WAIT:
+    LWIP_DEBUGF(TCP_DEBUG, ("CLOSE_WAIT\n"));
+    break;
+  case CLOSING:
+    LWIP_DEBUGF(TCP_DEBUG, ("CLOSING\n"));
+    break;
+  case LAST_ACK:
+    LWIP_DEBUGF(TCP_DEBUG, ("LAST_ACK\n"));
+    break;
+  case TIME_WAIT:
+    LWIP_DEBUGF(TCP_DEBUG, ("TIME_WAIT\n"));
+   break;
+  }
+}
+
+void
+tcp_debug_print_flags(u8_t flags)
+{
+  if (flags & TCP_FIN) {
+    LWIP_DEBUGF(TCP_DEBUG, ("FIN "));
+  }
+  if (flags & TCP_SYN) {
+    LWIP_DEBUGF(TCP_DEBUG, ("SYN "));
+  }
+  if (flags & TCP_RST) {
+    LWIP_DEBUGF(TCP_DEBUG, ("RST "));
+  }
+  if (flags & TCP_PSH) {
+    LWIP_DEBUGF(TCP_DEBUG, ("PSH "));
+  }
+  if (flags & TCP_ACK) {
+    LWIP_DEBUGF(TCP_DEBUG, ("ACK "));
+  }
+  if (flags & TCP_URG) {
+    LWIP_DEBUGF(TCP_DEBUG, ("URG "));
+  }
+  if (flags & TCP_ECE) {
+    LWIP_DEBUGF(TCP_DEBUG, ("ECE "));
+  }
+  if (flags & TCP_CWR) {
+    LWIP_DEBUGF(TCP_DEBUG, ("CWR "));
+  }
+}
+
+void
+tcp_debug_print_pcbs(void)
+{
+  struct tcp_pcb *pcb;
+  LWIP_DEBUGF(TCP_DEBUG, ("Active PCB states:\n"));
+  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+    LWIP_DEBUGF(TCP_DEBUG, ("Local port %"U16_F", foreign port %"U16_F" snd_nxt %"U32_F" rcv_nxt %"U32_F" ",
+                       pcb->local_port, pcb->remote_port,
+                       pcb->snd_nxt, pcb->rcv_nxt));
+    tcp_debug_print_state(pcb->state);
+  }    
+  LWIP_DEBUGF(TCP_DEBUG, ("Listen PCB states:\n"));
+  for(pcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs; pcb != NULL; pcb = pcb->next) {
+    LWIP_DEBUGF(TCP_DEBUG, ("Local port %"U16_F", foreign port %"U16_F" snd_nxt %"U32_F" rcv_nxt %"U32_F" ",
+                       pcb->local_port, pcb->remote_port,
+                       pcb->snd_nxt, pcb->rcv_nxt));
+    tcp_debug_print_state(pcb->state);
+  }    
+  LWIP_DEBUGF(TCP_DEBUG, ("TIME-WAIT PCB states:\n"));
+  for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
+    LWIP_DEBUGF(TCP_DEBUG, ("Local port %"U16_F", foreign port %"U16_F" snd_nxt %"U32_F" rcv_nxt %"U32_F" ",
+                       pcb->local_port, pcb->remote_port,
+                       pcb->snd_nxt, pcb->rcv_nxt));
+    tcp_debug_print_state(pcb->state);
+  }    
+}
+
+s16_t
+tcp_pcbs_sane(void)
+{
+  struct tcp_pcb *pcb;
+  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+    LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != CLOSED", pcb->state != CLOSED);
+    LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != LISTEN", pcb->state != LISTEN);
+    LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT);
+  }
+  for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
+    LWIP_ASSERT("tcp_pcbs_sane: tw pcb->state == TIME-WAIT", pcb->state == TIME_WAIT);
+  }
+  return 1;
+}
+#endif /* TCP_DEBUG */
+#endif /* LWIP_TCP */
+
+
+
+
+
+
+
+
+
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/tcp_in.c b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/tcp_in.c
new file mode 100644
index 000000000..9b8b99a33
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/tcp_in.c
@@ -0,0 +1,1199 @@
+/**
+ * @file
+ *
+ * Transmission Control Protocol, incoming traffic
+ *
+ * The input processing functions of TCP.
+ *
+ * These functions are generally called in the order (ip_input() ->) tcp_input() ->
+ * tcp_process() -> tcp_receive() (-> application).
+ * 
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include "lwip/def.h"
+#include "lwip/opt.h"
+
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+
+#include "lwip/inet.h"
+#include "lwip/tcp.h"
+
+#include "lwip/stats.h"
+
+#include "arch/perf.h"
+#if LWIP_TCP
+/* These variables are global to all functions involved in the input
+   processing of TCP segments. They are set by the tcp_input()
+   function. */
+static struct tcp_seg inseg;
+static struct tcp_hdr *tcphdr;
+static struct ip_hdr *iphdr;
+static u32_t seqno, ackno;
+static u8_t flags;
+static u16_t tcplen;
+
+static u8_t recv_flags;
+static struct pbuf *recv_data;
+
+struct tcp_pcb *tcp_input_pcb;
+
+/* Forward declarations. */
+static err_t tcp_process(struct tcp_pcb *pcb);
+static void tcp_receive(struct tcp_pcb *pcb);
+static void tcp_parseopt(struct tcp_pcb *pcb);
+
+static err_t tcp_listen_input(struct tcp_pcb_listen *pcb);
+static err_t tcp_timewait_input(struct tcp_pcb *pcb);
+
+
+/* tcp_input:
+ *
+ * The initial input processing of TCP. It verifies the TCP header, demultiplexes
+ * the segment between the PCBs and passes it on to tcp_process(), which implements
+ * the TCP finite state machine. This function is called by the IP layer (in
+ * ip_input()).
+ */
+
+void
+tcp_input(struct pbuf *p, struct netif *inp)
+{
+  struct tcp_pcb *pcb, *prev;
+  struct tcp_pcb_listen *lpcb;
+  u8_t hdrlen;
+  err_t err;
+
+  PERF_START;
+
+  TCP_STATS_INC(tcp.recv);
+
+  iphdr = p->payload;
+  tcphdr = (struct tcp_hdr *)((u8_t *)p->payload + IPH_HL(iphdr) * 4);
+
+#if TCP_INPUT_DEBUG
+  tcp_debug_print(tcphdr);
+#endif
+
+  /* remove header from payload */
+  if (pbuf_header(p, -((s16_t)(IPH_HL(iphdr) * 4))) || (p->tot_len < sizeof(struct tcp_hdr))) {
+    /* drop short packets */
+    LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: short packet (%"U16_F" bytes) discarded\n", p->tot_len));
+    TCP_STATS_INC(tcp.lenerr);
+    TCP_STATS_INC(tcp.drop);
+    pbuf_free(p);
+    return;
+  }
+
+  /* Don't even process incoming broadcasts/multicasts. */
+  if (ip_addr_isbroadcast(&(iphdr->dest), inp) ||
+      ip_addr_ismulticast(&(iphdr->dest))) {
+    pbuf_free(p);
+    return;
+  }
+
+#if CHECKSUM_CHECK_TCP
+  /* Verify TCP checksum. */
+  if (inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src),
+      (struct ip_addr *)&(iphdr->dest),
+      IP_PROTO_TCP, p->tot_len) != 0) {
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packet discarded due to failing checksum 0x%04"X16_F"\n",
+        inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src), (struct ip_addr *)&(iphdr->dest),
+      IP_PROTO_TCP, p->tot_len)));
+#if TCP_DEBUG
+    tcp_debug_print(tcphdr);
+#endif /* TCP_DEBUG */
+    TCP_STATS_INC(tcp.chkerr);
+    TCP_STATS_INC(tcp.drop);
+
+    pbuf_free(p);
+    return;
+  }
+#endif
+
+  /* Move the payload pointer in the pbuf so that it points to the
+     TCP data instead of the TCP header. */
+  hdrlen = TCPH_HDRLEN(tcphdr);
+  pbuf_header(p, -(hdrlen * 4));
+
+  /* Convert fields in TCP header to host byte order. */
+  tcphdr->src = ntohs(tcphdr->src);
+  tcphdr->dest = ntohs(tcphdr->dest);
+  seqno = tcphdr->seqno = ntohl(tcphdr->seqno);
+  ackno = tcphdr->ackno = ntohl(tcphdr->ackno);
+  tcphdr->wnd = ntohs(tcphdr->wnd);
+
+  flags = TCPH_FLAGS(tcphdr) & TCP_FLAGS;
+  tcplen = p->tot_len + ((flags & TCP_FIN || flags & TCP_SYN)? 1: 0);
+
+  /* Demultiplex an incoming segment. First, we check if it is destined
+     for an active connection. */
+  prev = NULL;
+
+  
+  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
+    LWIP_ASSERT("tcp_input: active pcb->state != CLOSED", pcb->state != CLOSED);
+    LWIP_ASSERT("tcp_input: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT);
+    LWIP_ASSERT("tcp_input: active pcb->state != LISTEN", pcb->state != LISTEN);
+    if (pcb->remote_port == tcphdr->src &&
+       pcb->local_port == tcphdr->dest &&
+       ip_addr_cmp(&(pcb->remote_ip), &(iphdr->src)) &&
+       ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest))) {
+
+      /* Move this PCB to the front of the list so that subsequent
+   lookups will be faster (we exploit locality in TCP segment
+   arrivals). */
+      LWIP_ASSERT("tcp_input: pcb->next != pcb (before cache)", pcb->next != pcb);
+      if (prev != NULL) {
+  prev->next = pcb->next;
+  pcb->next = tcp_active_pcbs;
+  tcp_active_pcbs = pcb;
+      }
+      LWIP_ASSERT("tcp_input: pcb->next != pcb (after cache)", pcb->next != pcb);
+      break;
+    }
+    prev = pcb;
+  }
+
+  if (pcb == NULL) {
+    /* If it did not go to an active connection, we check the connections
+       in the TIME-WAIT state. */
+
+    for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
+      LWIP_ASSERT("tcp_input: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT);
+      if (pcb->remote_port == tcphdr->src &&
+   pcb->local_port == tcphdr->dest &&
+   ip_addr_cmp(&(pcb->remote_ip), &(iphdr->src)) &&
+         ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest))) {
+  /* We don't really care enough to move this PCB to the front
+     of the list since we are not very likely to receive that
+     many segments for connections in TIME-WAIT. */
+  LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packed for TIME_WAITing connection.\n"));
+  tcp_timewait_input(pcb);
+  pbuf_free(p);
+  return;
+      }
+    }
+
+  /* Finally, if we still did not get a match, we check all PCBs that
+     are LISTENing for incoming connections. */
+    prev = NULL;
+    for(lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
+      if ((ip_addr_isany(&(lpcb->local_ip)) ||
+    ip_addr_cmp(&(lpcb->local_ip), &(iphdr->dest))) &&
+   lpcb->local_port == tcphdr->dest) {
+  /* Move this PCB to the front of the list so that subsequent
+     lookups will be faster (we exploit locality in TCP segment
+     arrivals). */
+  if (prev != NULL) {
+    ((struct tcp_pcb_listen *)prev)->next = lpcb->next;
+          /* our successor is the remainder of the listening list */
+    lpcb->next = tcp_listen_pcbs.listen_pcbs;
+          /* put this listening pcb at the head of the listening list */
+    tcp_listen_pcbs.listen_pcbs = lpcb;
+  }
+
+  LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packed for LISTENing connection.\n"));
+  tcp_listen_input(lpcb);
+  pbuf_free(p);
+  return;
+      }
+      prev = (struct tcp_pcb *)lpcb;
+    }
+  }
+
+#if TCP_INPUT_DEBUG
+  LWIP_DEBUGF(TCP_INPUT_DEBUG, ("+-+-+-+-+-+-+-+-+-+-+-+-+-+- tcp_input: flags "));
+  tcp_debug_print_flags(TCPH_FLAGS(tcphdr));
+  LWIP_DEBUGF(TCP_INPUT_DEBUG, ("-+-+-+-+-+-+-+-+-+-+-+-+-+-+\n"));
+#endif /* TCP_INPUT_DEBUG */
+
+
+  if (pcb != NULL) {
+    /* The incoming segment belongs to a connection. */
+#if TCP_INPUT_DEBUG
+#if TCP_DEBUG
+    tcp_debug_print_state(pcb->state);
+#endif /* TCP_DEBUG */
+#endif /* TCP_INPUT_DEBUG */
+
+    /* Set up a tcp_seg structure. */
+    inseg.next = NULL;
+    inseg.len = p->tot_len;
+    inseg.dataptr = p->payload;
+    inseg.p = p;
+    inseg.tcphdr = tcphdr;
+
+    recv_data = NULL;
+    recv_flags = 0;
+
+    tcp_input_pcb = pcb;
+    err = tcp_process(pcb);
+    tcp_input_pcb = NULL;
+    /* A return value of ERR_ABRT means that tcp_abort() was called
+       and that the pcb has been freed. If so, we don't do anything. */
+    if (err != ERR_ABRT) {
+      if (recv_flags & TF_RESET) {
+  /* TF_RESET means that the connection was reset by the other
+     end. We then call the error callback to inform the
+     application that the connection is dead before we
+     deallocate the PCB. */
+  TCP_EVENT_ERR(pcb->errf, pcb->callback_arg, ERR_RST);
+  tcp_pcb_remove(&tcp_active_pcbs, pcb);
+  memp_free(MEMP_TCP_PCB, pcb);
+      } else if (recv_flags & TF_CLOSED) {
+  /* The connection has been closed and we will deallocate the
+     PCB. */
+  tcp_pcb_remove(&tcp_active_pcbs, pcb);
+  memp_free(MEMP_TCP_PCB, pcb);
+      } else {
+  err = ERR_OK;
+  /* If the application has registered a "sent" function to be
+     called when new send buffer space is available, we call it
+     now. */
+  if (pcb->acked > 0) {
+    TCP_EVENT_SENT(pcb, pcb->acked, err);
+  }
+
+  if (recv_data != NULL) {
+    /* Notify application that data has been received. */
+    TCP_EVENT_RECV(pcb, recv_data, ERR_OK, err);
+  }
+
+  /* If a FIN segment was received, we call the callback
+     function with a NULL buffer to indicate EOF. */
+  if (recv_flags & TF_GOT_FIN) {
+    TCP_EVENT_RECV(pcb, NULL, ERR_OK, err);
+  }
+  /* If there were no errors, we try to send something out. */
+  if (err == ERR_OK) {
+    tcp_output(pcb);
+  }
+      }
+    }
+
+
+    /* We deallocate the incoming pbuf. If it was buffered by the
+       application, the application should have called pbuf_ref() to
+       increase the reference counter in the pbuf. If so, the buffer
+       isn't actually deallocated by the call to pbuf_free(), only the
+       reference count is decreased. */
+    if (inseg.p != NULL) pbuf_free(inseg.p);
+#if TCP_INPUT_DEBUG
+#if TCP_DEBUG
+    tcp_debug_print_state(pcb->state);
+#endif /* TCP_DEBUG */
+#endif /* TCP_INPUT_DEBUG */
+      
+  } else {
+
+    /* If no matching PCB was found, send a TCP RST (reset) to the
+       sender. */
+    LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_input: no PCB match found, resetting.\n"));
+    if (!(TCPH_FLAGS(tcphdr) & TCP_RST)) {
+      TCP_STATS_INC(tcp.proterr);
+      TCP_STATS_INC(tcp.drop);
+      tcp_rst(ackno, seqno + tcplen,
+        &(iphdr->dest), &(iphdr->src),
+        tcphdr->dest, tcphdr->src);
+    }
+    pbuf_free(p);
+  }
+
+  LWIP_ASSERT("tcp_input: tcp_pcbs_sane()", tcp_pcbs_sane());
+  PERF_STOP("tcp_input");
+}
+
+/* tcp_listen_input():
+ *
+ * Called by tcp_input() when a segment arrives for a listening
+ * connection.
+ */
+
+static err_t
+tcp_listen_input(struct tcp_pcb_listen *pcb)
+{
+  struct tcp_pcb *npcb;
+  u32_t optdata;
+
+  /* In the LISTEN state, we check for incoming SYN segments,
+     creates a new PCB, and responds with a SYN|ACK. */
+  if (flags & TCP_ACK) {
+    /* For incoming segments with the ACK flag set, respond with a
+       RST. */
+    LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_listen_input: ACK in LISTEN, sending reset\n"));
+    tcp_rst(ackno + 1, seqno + tcplen,
+      &(iphdr->dest), &(iphdr->src),
+      tcphdr->dest, tcphdr->src);
+  } else if (flags & TCP_SYN) {
+    LWIP_DEBUGF(TCP_DEBUG, ("TCP connection request %"U16_F" -> %"U16_F".\n", tcphdr->src, tcphdr->dest));
+    npcb = tcp_alloc(pcb->prio);
+    /* If a new PCB could not be created (probably due to lack of memory),
+       we don't do anything, but rely on the sender will retransmit the
+       SYN at a time when we have more memory available. */
+    if (npcb == NULL) {
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_listen_input: could not allocate PCB\n"));
+      TCP_STATS_INC(tcp.memerr);
+      return ERR_MEM;
+    }
+    /* Set up the new PCB. */
+    ip_addr_set(&(npcb->local_ip), &(iphdr->dest));
+    npcb->local_port = pcb->local_port;
+    ip_addr_set(&(npcb->remote_ip), &(iphdr->src));
+    npcb->remote_port = tcphdr->src;
+    npcb->state = SYN_RCVD;
+    npcb->rcv_nxt = seqno + 1;
+    npcb->snd_wnd = tcphdr->wnd;
+    npcb->ssthresh = npcb->snd_wnd;
+    npcb->snd_wl1 = seqno - 1;/* initialise to seqno-1 to force window update */
+    npcb->callback_arg = pcb->callback_arg;
+#if LWIP_CALLBACK_API
+    npcb->accept = pcb->accept;
+#endif /* LWIP_CALLBACK_API */
+    /* inherit socket options */
+    npcb->so_options = pcb->so_options & (SOF_DEBUG|SOF_DONTROUTE|SOF_KEEPALIVE|SOF_OOBINLINE|SOF_LINGER);
+    /* Register the new PCB so that we can begin receiving segments
+       for it. */
+    TCP_REG(&tcp_active_pcbs, npcb);
+
+    /* Parse any options in the SYN. */
+    tcp_parseopt(npcb);
+
+    /* Build an MSS option. */
+    optdata = htonl(((u32_t)2 << 24) |
+        ((u32_t)4 << 16) |
+        (((u32_t)npcb->mss / 256) << 8) |
+        (npcb->mss & 255));
+    /* Send a SYN|ACK together with the MSS option. */
+    tcp_enqueue(npcb, NULL, 0, TCP_SYN | TCP_ACK, 0, (u8_t *)&optdata, 4);
+    return tcp_output(npcb);
+  }
+  return ERR_OK;
+}
+
+/* tcp_timewait_input():
+ *
+ * Called by tcp_input() when a segment arrives for a connection in
+ * TIME_WAIT.
+ */
+
+static err_t
+tcp_timewait_input(struct tcp_pcb *pcb)
+{
+  if (TCP_SEQ_GT(seqno + tcplen, pcb->rcv_nxt)) {
+    pcb->rcv_nxt = seqno + tcplen;
+  }
+  if (tcplen > 0) {
+    tcp_ack_now(pcb);
+  }
+  return tcp_output(pcb);
+}
+
+/* tcp_process
+ *
+ * Implements the TCP state machine. Called by tcp_input. In some
+ * states tcp_receive() is called to receive data. The tcp_seg
+ * argument will be freed by the caller (tcp_input()) unless the
+ * recv_data pointer in the pcb is set.
+ */
+
+static err_t
+tcp_process(struct tcp_pcb *pcb)
+{
+  struct tcp_seg *rseg;
+  u8_t acceptable = 0;
+  err_t err;
+
+
+  err = ERR_OK;
+
+  /* Process incoming RST segments. */
+  if (flags & TCP_RST) {
+    /* First, determine if the reset is acceptable. */
+    if (pcb->state == SYN_SENT) {
+      if (ackno == pcb->snd_nxt) {
+        acceptable = 1;
+      }
+    } else {
+      /*if (TCP_SEQ_GEQ(seqno, pcb->rcv_nxt) &&
+          TCP_SEQ_LEQ(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) {
+      */
+      if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt+pcb->rcv_wnd)) {
+        acceptable = 1;
+      }
+    }
+
+    if (acceptable) {
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: Connection RESET\n"));
+      LWIP_ASSERT("tcp_input: pcb->state != CLOSED", pcb->state != CLOSED);
+      recv_flags = TF_RESET;
+      pcb->flags &= ~TF_ACK_DELAY;
+      return ERR_RST;
+    } else {
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n",
+       seqno, pcb->rcv_nxt));
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n",
+       seqno, pcb->rcv_nxt));
+      return ERR_OK;
+    }
+  }
+
+  /* Update the PCB (in)activity timer. */
+  pcb->tmr = tcp_ticks;
+  pcb->keep_cnt = 0;
+
+  /* Do different things depending on the TCP state. */
+  switch (pcb->state) {
+  case SYN_SENT:
+    LWIP_DEBUGF(TCP_INPUT_DEBUG, ("SYN-SENT: ackno %"U32_F" pcb->snd_nxt %"U32_F" unacked %"U32_F"\n", ackno,
+     pcb->snd_nxt, ntohl(pcb->unacked->tcphdr->seqno)));
+    /* received SYN ACK with expected sequence number? */
+    if ((flags & TCP_ACK) && (flags & TCP_SYN)
+        && ackno == ntohl(pcb->unacked->tcphdr->seqno) + 1) {
+      pcb->snd_buf++;
+      pcb->rcv_nxt = seqno + 1;
+      pcb->lastack = ackno;
+      pcb->snd_wnd = tcphdr->wnd;
+      pcb->snd_wl1 = seqno - 1; /* initialise to seqno - 1 to force window update */
+      pcb->state = ESTABLISHED;
+      pcb->cwnd = pcb->mss;
+      --pcb->snd_queuelen;
+      LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_process: SYN-SENT --queuelen %"U16_F"\n", (u16_t)pcb->snd_queuelen));
+      rseg = pcb->unacked;
+      pcb->unacked = rseg->next;
+      tcp_seg_free(rseg);
+
+      /* Parse any options in the SYNACK. */
+      tcp_parseopt(pcb);
+
+      /* Call the user specified function to call when sucessfully
+       * connected. */
+      TCP_EVENT_CONNECTED(pcb, ERR_OK, err);
+      tcp_ack(pcb);
+    }
+    /* received ACK? possibly a half-open connection */
+    else if (flags & TCP_ACK) {
+      /* send a RST to bring the other side in a non-synchronized state. */
+      tcp_rst(ackno, seqno + tcplen, &(iphdr->dest), &(iphdr->src),
+        tcphdr->dest, tcphdr->src);
+    }
+    break;
+  case SYN_RCVD:
+    if (flags & TCP_ACK &&
+       !(flags & TCP_RST)) {
+      /* expected ACK number? */
+      if (TCP_SEQ_BETWEEN(ackno, pcb->lastack+1, pcb->snd_nxt)) {
+        pcb->state = ESTABLISHED;
+        LWIP_DEBUGF(TCP_DEBUG, ("TCP connection established %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+#if LWIP_CALLBACK_API
+        LWIP_ASSERT("pcb->accept != NULL", pcb->accept != NULL);
+#endif
+        /* Call the accept function. */
+        TCP_EVENT_ACCEPT(pcb, ERR_OK, err);
+        if (err != ERR_OK) {
+          /* If the accept function returns with an error, we abort
+           * the connection. */
+          tcp_abort(pcb);
+          return ERR_ABRT;
+        }
+        /* If there was any data contained within this ACK,
+         * we'd better pass it on to the application as well. */
+        tcp_receive(pcb);
+        pcb->cwnd = pcb->mss;
+      }
+      /* incorrect ACK number */
+      else {
+        /* send RST */
+        tcp_rst(ackno, seqno + tcplen, &(iphdr->dest), &(iphdr->src),
+          tcphdr->dest, tcphdr->src);
+      }
+    }
+    break;
+  case CLOSE_WAIT:
+    /* FALLTHROUGH */
+  case ESTABLISHED:
+    tcp_receive(pcb);
+    if (flags & TCP_FIN) {
+      tcp_ack_now(pcb);
+      pcb->state = CLOSE_WAIT;
+    }
+    break;
+  case FIN_WAIT_1:
+    tcp_receive(pcb);
+    if (flags & TCP_FIN) {
+      if (flags & TCP_ACK && ackno == pcb->snd_nxt) {
+        LWIP_DEBUGF(TCP_DEBUG,
+          ("TCP connection closed %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+        tcp_ack_now(pcb);
+        tcp_pcb_purge(pcb);
+        TCP_RMV(&tcp_active_pcbs, pcb);
+        pcb->state = TIME_WAIT;
+        TCP_REG(&tcp_tw_pcbs, pcb);
+      } else {
+        tcp_ack_now(pcb);
+        pcb->state = CLOSING;
+      }
+    } else if (flags & TCP_ACK && ackno == pcb->snd_nxt) {
+      pcb->state = FIN_WAIT_2;
+    }
+    break;
+  case FIN_WAIT_2:
+    tcp_receive(pcb);
+    if (flags & TCP_FIN) {
+      LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+      tcp_ack_now(pcb);
+      tcp_pcb_purge(pcb);
+      TCP_RMV(&tcp_active_pcbs, pcb);
+      pcb->state = TIME_WAIT;
+      TCP_REG(&tcp_tw_pcbs, pcb);
+    }
+    break;
+  case CLOSING:
+    tcp_receive(pcb);
+    if (flags & TCP_ACK && ackno == pcb->snd_nxt) {
+      LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+      tcp_ack_now(pcb);
+      tcp_pcb_purge(pcb);
+      TCP_RMV(&tcp_active_pcbs, pcb);
+      pcb->state = TIME_WAIT;
+      TCP_REG(&tcp_tw_pcbs, pcb);
+    }
+    break;
+  case LAST_ACK:
+    tcp_receive(pcb);
+    if (flags & TCP_ACK && ackno == pcb->snd_nxt) {
+      LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
+      pcb->state = CLOSED;
+      recv_flags = TF_CLOSED;
+    }
+    break;
+  default:
+    break;
+  }
+  return ERR_OK;
+}
+
+/* tcp_receive:
+ *
+ * Called by tcp_process. Checks if the given segment is an ACK for outstanding
+ * data, and if so frees the memory of the buffered data. Next, is places the
+ * segment on any of the receive queues (pcb->recved or pcb->ooseq). If the segment
+ * is buffered, the pbuf is referenced by pbuf_ref so that it will not be freed until
+ * i it has been removed from the buffer.
+ *
+ * If the incoming segment constitutes an ACK for a segment that was used for RTT
+ * estimation, the RTT is estimated here as well.
+ */
+
+static void
+tcp_receive(struct tcp_pcb *pcb)
+{
+  struct tcp_seg *next;
+#if TCP_QUEUE_OOSEQ
+  struct tcp_seg *prev, *cseg;
+#endif
+  struct pbuf *p;
+  s32_t off;
+  s16_t m;
+  u32_t right_wnd_edge;
+  u16_t new_tot_len;
+
+
+  if (flags & TCP_ACK) {
+    right_wnd_edge = pcb->snd_wnd + pcb->snd_wl1;
+
+    /* Update window. */
+    if (TCP_SEQ_LT(pcb->snd_wl1, seqno) ||
+       (pcb->snd_wl1 == seqno && TCP_SEQ_LT(pcb->snd_wl2, ackno)) ||
+       (pcb->snd_wl2 == ackno && tcphdr->wnd > pcb->snd_wnd)) {
+      pcb->snd_wnd = tcphdr->wnd;
+      pcb->snd_wl1 = seqno;
+      pcb->snd_wl2 = ackno;
+      LWIP_DEBUGF(TCP_WND_DEBUG, ("tcp_receive: window update %"U32_F"\n", pcb->snd_wnd));
+#if TCP_WND_DEBUG
+    } else {
+      if (pcb->snd_wnd != tcphdr->wnd) {
+        LWIP_DEBUGF(TCP_WND_DEBUG, ("tcp_receive: no window update lastack %"U32_F" snd_max %"U32_F" ackno %"U32_F" wl1 %"U32_F" seqno %"U32_F" wl2 %"U32_F"\n",
+                               pcb->lastack, pcb->snd_max, ackno, pcb->snd_wl1, seqno, pcb->snd_wl2));
+      }
+#endif /* TCP_WND_DEBUG */
+    }
+
+
+    if (pcb->lastack == ackno) {
+      pcb->acked = 0;
+
+      if (pcb->snd_wl1 + pcb->snd_wnd == right_wnd_edge){
+        ++pcb->dupacks;
+        if (pcb->dupacks >= 3 && pcb->unacked != NULL) {
+          if (!(pcb->flags & TF_INFR)) {
+            /* This is fast retransmit. Retransmit the first unacked segment. */
+            LWIP_DEBUGF(TCP_FR_DEBUG, ("tcp_receive: dupacks %"U16_F" (%"U32_F"), fast retransmit %"U32_F"\n",
+                                       (u16_t)pcb->dupacks, pcb->lastack,
+                                       ntohl(pcb->unacked->tcphdr->seqno)));
+            tcp_rexmit(pcb);
+            /* Set ssthresh to max (FlightSize / 2, 2*SMSS) */
+            /*pcb->ssthresh = LWIP_MAX((pcb->snd_max -
+                                      pcb->lastack) / 2,
+                                      2 * pcb->mss);*/
+            /* Set ssthresh to half of the minimum of the currenct cwnd and the advertised window */
+            if(pcb->cwnd > pcb->snd_wnd)
+              pcb->ssthresh = pcb->snd_wnd / 2;
+            else
+              pcb->ssthresh = pcb->cwnd / 2;
+
+            pcb->cwnd = pcb->ssthresh + 3 * pcb->mss;
+            pcb->flags |= TF_INFR;
+          } else {
+            /* Inflate the congestion window, but not if it means that
+               the value overflows. */
+            if ((u16_t)(pcb->cwnd + pcb->mss) > pcb->cwnd) {
+              pcb->cwnd += pcb->mss;
+            }
+          }
+        }
+      } else {
+        LWIP_DEBUGF(TCP_FR_DEBUG, ("tcp_receive: dupack averted %"U32_F" %"U32_F"\n",
+                                   pcb->snd_wl1 + pcb->snd_wnd, right_wnd_edge));
+      }
+    } else
+      /*if (TCP_SEQ_LT(pcb->lastack, ackno) &&
+        TCP_SEQ_LEQ(ackno, pcb->snd_max)) { */
+      if(TCP_SEQ_BETWEEN(ackno, pcb->lastack+1, pcb->snd_max)){
+      /* We come here when the ACK acknowledges new data. */
+      
+      /* Reset the "IN Fast Retransmit" flag, since we are no longer
+         in fast retransmit. Also reset the congestion window to the
+         slow start threshold. */
+      if (pcb->flags & TF_INFR) {
+        pcb->flags &= ~TF_INFR;
+        pcb->cwnd = pcb->ssthresh;
+      }
+
+      /* Reset the number of retransmissions. */
+      pcb->nrtx = 0;
+
+      /* Reset the retransmission time-out. */
+      pcb->rto = (pcb->sa >> 3) + pcb->sv;
+
+      /* Update the send buffer space. */
+      pcb->acked = ackno - pcb->lastack;
+
+      pcb->snd_buf += pcb->acked;
+
+      /* Reset the fast retransmit variables. */
+      pcb->dupacks = 0;
+      pcb->lastack = ackno;
+
+      /* Update the congestion control variables (cwnd and
+         ssthresh). */
+      if (pcb->state >= ESTABLISHED) {
+        if (pcb->cwnd < pcb->ssthresh) {
+          if ((u16_t)(pcb->cwnd + pcb->mss) > pcb->cwnd) {
+            pcb->cwnd += pcb->mss;
+          }
+          LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: slow start cwnd %"U16_F"\n", pcb->cwnd));
+        } else {
+          u16_t new_cwnd = (pcb->cwnd + pcb->mss * pcb->mss / pcb->cwnd);
+          if (new_cwnd > pcb->cwnd) {
+            pcb->cwnd = new_cwnd;
+          }
+          LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: congestion avoidance cwnd %"U16_F"\n", pcb->cwnd));
+        }
+      }
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: ACK for %"U32_F", unacked->seqno %"U32_F":%"U32_F"\n",
+                                    ackno,
+                                    pcb->unacked != NULL?
+                                    ntohl(pcb->unacked->tcphdr->seqno): 0,
+                                    pcb->unacked != NULL?
+                                    ntohl(pcb->unacked->tcphdr->seqno) + TCP_TCPLEN(pcb->unacked): 0));
+
+      /* Remove segment from the unacknowledged list if the incoming
+         ACK acknowlegdes them. */
+      while (pcb->unacked != NULL &&
+             TCP_SEQ_LEQ(ntohl(pcb->unacked->tcphdr->seqno) +
+                         TCP_TCPLEN(pcb->unacked), ackno)) {
+        LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %"U32_F":%"U32_F" from pcb->unacked\n",
+                                      ntohl(pcb->unacked->tcphdr->seqno),
+                                      ntohl(pcb->unacked->tcphdr->seqno) +
+                                      TCP_TCPLEN(pcb->unacked)));
+
+        next = pcb->unacked;
+        pcb->unacked = pcb->unacked->next;
+
+        LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %"U16_F" ... ", (u16_t)pcb->snd_queuelen));
+        pcb->snd_queuelen -= pbuf_clen(next->p);
+        tcp_seg_free(next);
+
+        LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%"U16_F" (after freeing unacked)\n", (u16_t)pcb->snd_queuelen));
+        if (pcb->snd_queuelen != 0) {
+          LWIP_ASSERT("tcp_receive: valid queue length", pcb->unacked != NULL ||
+                      pcb->unsent != NULL);
+        }
+      }
+      pcb->polltmr = 0;
+    }
+
+    /* We go through the ->unsent list to see if any of the segments
+       on the list are acknowledged by the ACK. This may seem
+       strange since an "unsent" segment shouldn't be acked. The
+       rationale is that lwIP puts all outstanding segments on the
+       ->unsent list after a retransmission, so these segments may
+       in fact have been sent once. */
+    while (pcb->unsent != NULL &&
+           /*TCP_SEQ_LEQ(ntohl(pcb->unsent->tcphdr->seqno) + TCP_TCPLEN(pcb->unsent), ackno) &&
+             TCP_SEQ_LEQ(ackno, pcb->snd_max)*/
+           TCP_SEQ_BETWEEN(ackno, ntohl(pcb->unsent->tcphdr->seqno) + TCP_TCPLEN(pcb->unsent), pcb->snd_max)
+           ) {
+      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %"U32_F":%"U32_F" from pcb->unsent\n",
+                                    ntohl(pcb->unsent->tcphdr->seqno), ntohl(pcb->unsent->tcphdr->seqno) +
+                                    TCP_TCPLEN(pcb->unsent)));
+
+      next = pcb->unsent;
+      pcb->unsent = pcb->unsent->next;
+      LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %"U16_F" ... ", (u16_t)pcb->snd_queuelen));
+      pcb->snd_queuelen -= pbuf_clen(next->p);
+      tcp_seg_free(next);
+      LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%"U16_F" (after freeing unsent)\n", (u16_t)pcb->snd_queuelen));
+      if (pcb->snd_queuelen != 0) {
+        LWIP_ASSERT("tcp_receive: valid queue length",
+          pcb->unacked != NULL || pcb->unsent != NULL);
+      }
+
+      if (pcb->unsent != NULL) {
+        pcb->snd_nxt = htonl(pcb->unsent->tcphdr->seqno);
+      }
+    }
+    /* End of ACK for new data processing. */
+
+    LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: pcb->rttest %"U32_F" rtseq %"U32_F" ackno %"U32_F"\n",
+                                pcb->rttest, pcb->rtseq, ackno));
+
+    /* RTT estimation calculations. This is done by checking if the
+       incoming segment acknowledges the segment we use to take a
+       round-trip time measurement. */
+    if (pcb->rttest && TCP_SEQ_LT(pcb->rtseq, ackno)) {
+      m = tcp_ticks - pcb->rttest;
+
+      LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: experienced rtt %"U16_F" ticks (%"U16_F" msec).\n",
+                                  m, m * TCP_SLOW_INTERVAL));
+
+      /* This is taken directly from VJs original code in his paper */
+      m = m - (pcb->sa >> 3);
+      pcb->sa += m;
+      if (m < 0) {
+        m = -m;
+      }
+      m = m - (pcb->sv >> 2);
+      pcb->sv += m;
+      pcb->rto = (pcb->sa >> 3) + pcb->sv;
+
+      LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: RTO %"U16_F" (%"U16_F" miliseconds)\n",
+                                  pcb->rto, pcb->rto * TCP_SLOW_INTERVAL));
+
+      pcb->rttest = 0;
+    }
+  }
+
+  /* If the incoming segment contains data, we must process it
+     further. */
+  if (tcplen > 0) {
+    /* This code basically does three things:
+
+    +) If the incoming segment contains data that is the next
+    in-sequence data, this data is passed to the application. This
+    might involve trimming the first edge of the data. The rcv_nxt
+    variable and the advertised window are adjusted.
+
+    +) If the incoming segment has data that is above the next
+    sequence number expected (->rcv_nxt), the segment is placed on
+    the ->ooseq queue. This is done by finding the appropriate
+    place in the ->ooseq queue (which is ordered by sequence
+    number) and trim the segment in both ends if needed. An
+    immediate ACK is sent to indicate that we received an
+    out-of-sequence segment.
+
+    +) Finally, we check if the first segment on the ->ooseq queue
+    now is in sequence (i.e., if rcv_nxt >= ooseq->seqno). If
+    rcv_nxt > ooseq->seqno, we must trim the first edge of the
+    segment on ->ooseq before we adjust rcv_nxt. The data in the
+    segments that are now on sequence are chained onto the
+    incoming segment so that we only need to call the application
+    once.
+    */
+
+    /* First, we check if we must trim the first edge. We have to do
+       this if the sequence number of the incoming segment is less
+       than rcv_nxt, and the sequence number plus the length of the
+       segment is larger than rcv_nxt. */
+    /*    if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)){
+          if (TCP_SEQ_LT(pcb->rcv_nxt, seqno + tcplen)) {*/
+    if(TCP_SEQ_BETWEEN(pcb->rcv_nxt, seqno+1, seqno+tcplen-1)){
+      /* Trimming the first edge is done by pushing the payload
+         pointer in the pbuf downwards. This is somewhat tricky since
+         we do not want to discard the full contents of the pbuf up to
+         the new starting point of the data since we have to keep the
+         TCP header which is present in the first pbuf in the chain.
+         
+         What is done is really quite a nasty hack: the first pbuf in
+         the pbuf chain is pointed to by inseg.p. Since we need to be
+         able to deallocate the whole pbuf, we cannot change this
+         inseg.p pointer to point to any of the later pbufs in the
+         chain. Instead, we point the ->payload pointer in the first
+         pbuf to data in one of the later pbufs. We also set the
+         inseg.data pointer to point to the right place. This way, the
+         ->p pointer will still point to the first pbuf, but the
+         ->p->payload pointer will point to data in another pbuf.
+         
+         After we are done with adjusting the pbuf pointers we must
+         adjust the ->data pointer in the seg and the segment
+         length.*/
+      
+      off = pcb->rcv_nxt - seqno;
+      p = inseg.p;
+      if (inseg.p->len < off) {
+        new_tot_len = inseg.p->tot_len - off;
+        while (p->len < off) {
+          off -= p->len;
+          /* KJM following line changed (with addition of new_tot_len var)
+             to fix bug #9076
+             inseg.p->tot_len -= p->len; */
+          p->tot_len = new_tot_len;
+          p->len = 0;
+          p = p->next;
+        }
+        pbuf_header(p, -off);
+      } else {
+        pbuf_header(inseg.p, -off);
+      }
+      /* KJM following line changed to use p->payload rather than inseg->p->payload
+         to fix bug #9076 */
+      inseg.dataptr = p->payload;
+      inseg.len -= pcb->rcv_nxt - seqno;
+      inseg.tcphdr->seqno = seqno = pcb->rcv_nxt;
+    }
+    else{
+      if(TCP_SEQ_LT(seqno, pcb->rcv_nxt)){
+        /* the whole segment is < rcv_nxt */
+        /* must be a duplicate of a packet that has already been correctly handled */
+        
+        LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: duplicate seqno %"U32_F"\n", seqno));
+        tcp_ack_now(pcb);
+      }
+    }
+
+    /* The sequence number must be within the window (above rcv_nxt
+       and below rcv_nxt + rcv_wnd) in order to be further
+       processed. */
+    /*if (TCP_SEQ_GEQ(seqno, pcb->rcv_nxt) &&
+      TCP_SEQ_LT(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) {*/
+    if(TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd - 1)){
+      if (pcb->rcv_nxt == seqno) {
+        /* The incoming segment is the next in sequence. We check if
+           we have to trim the end of the segment and update rcv_nxt
+           and pass the data to the application. */
+#if TCP_QUEUE_OOSEQ
+        if (pcb->ooseq != NULL &&
+            TCP_SEQ_LEQ(pcb->ooseq->tcphdr->seqno, seqno + inseg.len)) {
+          /* We have to trim the second edge of the incoming
+             segment. */
+          inseg.len = pcb->ooseq->tcphdr->seqno - seqno;
+          pbuf_realloc(inseg.p, inseg.len);
+        }
+#endif /* TCP_QUEUE_OOSEQ */
+
+        tcplen = TCP_TCPLEN(&inseg);
+
+        /* First received FIN will be ACKed +1, on any successive (duplicate)
+         * FINs we are already in CLOSE_WAIT and have already done +1.
+         */
+        if (pcb->state != CLOSE_WAIT) {
+          pcb->rcv_nxt += tcplen;
+        }
+
+        /* Update the receiver's (our) window. */
+        if (pcb->rcv_wnd < tcplen) {
+          pcb->rcv_wnd = 0;
+        } else {
+          pcb->rcv_wnd -= tcplen;
+        }
+
+        /* If there is data in the segment, we make preparations to
+           pass this up to the application. The ->recv_data variable
+           is used for holding the pbuf that goes to the
+           application. The code for reassembling out-of-sequence data
+           chains its data on this pbuf as well.
+
+           If the segment was a FIN, we set the TF_GOT_FIN flag that will
+           be used to indicate to the application that the remote side has
+           closed its end of the connection. */
+        if (inseg.p->tot_len > 0) {
+          recv_data = inseg.p;
+          /* Since this pbuf now is the responsibility of the
+             application, we delete our reference to it so that we won't
+             (mistakingly) deallocate it. */
+          inseg.p = NULL;
+        }
+        if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) {
+          LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: received FIN.\n"));
+          recv_flags = TF_GOT_FIN;
+        }
+
+#if TCP_QUEUE_OOSEQ
+        /* We now check if we have segments on the ->ooseq queue that
+           is now in sequence. */
+        while (pcb->ooseq != NULL &&
+               pcb->ooseq->tcphdr->seqno == pcb->rcv_nxt) {
+
+          cseg = pcb->ooseq;
+          seqno = pcb->ooseq->tcphdr->seqno;
+
+          pcb->rcv_nxt += TCP_TCPLEN(cseg);
+          if (pcb->rcv_wnd < TCP_TCPLEN(cseg)) {
+            pcb->rcv_wnd = 0;
+          } else {
+            pcb->rcv_wnd -= TCP_TCPLEN(cseg);
+          }
+          if (cseg->p->tot_len > 0) {
+            /* Chain this pbuf onto the pbuf that we will pass to
+               the application. */
+            if (recv_data) {
+              pbuf_cat(recv_data, cseg->p);
+            } else {
+              recv_data = cseg->p;
+            }
+            cseg->p = NULL;
+          }
+          if (TCPH_FLAGS(cseg->tcphdr) & TCP_FIN) {
+            LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: dequeued FIN.\n"));
+            recv_flags = TF_GOT_FIN;
+          }
+
+
+          pcb->ooseq = cseg->next;
+          tcp_seg_free(cseg);
+        }
+#endif /* TCP_QUEUE_OOSEQ */
+
+
+        /* Acknowledge the segment(s). */
+        tcp_ack(pcb);
+
+      } else {
+        /* We get here if the incoming segment is out-of-sequence. */
+        tcp_ack_now(pcb);
+#if TCP_QUEUE_OOSEQ
+        /* We queue the segment on the ->ooseq queue. */
+        if (pcb->ooseq == NULL) {
+          pcb->ooseq = tcp_seg_copy(&inseg);
+        } else {
+          /* If the queue is not empty, we walk through the queue and
+             try to find a place where the sequence number of the
+             incoming segment is between the sequence numbers of the
+             previous and the next segment on the ->ooseq queue. That is
+             the place where we put the incoming segment. If needed, we
+             trim the second edges of the previous and the incoming
+             segment so that it will fit into the sequence.
+
+             If the incoming segment has the same sequence number as a
+             segment on the ->ooseq queue, we discard the segment that
+             contains less data. */
+
+          prev = NULL;
+          for(next = pcb->ooseq; next != NULL; next = next->next) {
+            if (seqno == next->tcphdr->seqno) {
+              /* The sequence number of the incoming segment is the
+                 same as the sequence number of the segment on
+                 ->ooseq. We check the lengths to see which one to
+                 discard. */
+              if (inseg.len > next->len) {
+                /* The incoming segment is larger than the old
+                   segment. We replace the old segment with the new
+                   one. */
+                cseg = tcp_seg_copy(&inseg);
+                if (cseg != NULL) {
+                  cseg->next = next->next;
+                  if (prev != NULL) {
+                    prev->next = cseg;
+                  } else {
+                    pcb->ooseq = cseg;
+                  }
+                }
+                break;
+              } else {
+                /* Either the lenghts are the same or the incoming
+                   segment was smaller than the old one; in either
+                   case, we ditch the incoming segment. */
+                break;
+              }
+            } else {
+              if (prev == NULL) {
+                if (TCP_SEQ_LT(seqno, next->tcphdr->seqno)) {
+                  /* The sequence number of the incoming segment is lower
+                     than the sequence number of the first segment on the
+                     queue. We put the incoming segment first on the
+                     queue. */
+
+                  if (TCP_SEQ_GT(seqno + inseg.len, next->tcphdr->seqno)) {
+                    /* We need to trim the incoming segment. */
+                    inseg.len = next->tcphdr->seqno - seqno;
+                    pbuf_realloc(inseg.p, inseg.len);
+                  }
+                  cseg = tcp_seg_copy(&inseg);
+                  if (cseg != NULL) {
+                    cseg->next = next;
+                    pcb->ooseq = cseg;
+                  }
+                  break;
+                }
+              } else 
+                /*if (TCP_SEQ_LT(prev->tcphdr->seqno, seqno) &&
+                  TCP_SEQ_LT(seqno, next->tcphdr->seqno)) {*/
+                if(TCP_SEQ_BETWEEN(seqno, prev->tcphdr->seqno+1, next->tcphdr->seqno-1)){
+                /* The sequence number of the incoming segment is in
+                   between the sequence numbers of the previous and
+                   the next segment on ->ooseq. We trim and insert the
+                   incoming segment and trim the previous segment, if
+                   needed. */
+                if (TCP_SEQ_GT(seqno + inseg.len, next->tcphdr->seqno)) {
+                  /* We need to trim the incoming segment. */
+                  inseg.len = next->tcphdr->seqno - seqno;
+                  pbuf_realloc(inseg.p, inseg.len);
+                }
+
+                cseg = tcp_seg_copy(&inseg);
+                if (cseg != NULL) {
+                  cseg->next = next;
+                  prev->next = cseg;
+                  if (TCP_SEQ_GT(prev->tcphdr->seqno + prev->len, seqno)) {
+                    /* We need to trim the prev segment. */
+                    prev->len = seqno - prev->tcphdr->seqno;
+                    pbuf_realloc(prev->p, prev->len);
+                  }
+                }
+                break;
+              }
+              /* If the "next" segment is the last segment on the
+                 ooseq queue, we add the incoming segment to the end
+                 of the list. */
+              if (next->next == NULL &&
+                  TCP_SEQ_GT(seqno, next->tcphdr->seqno)) {
+                next->next = tcp_seg_copy(&inseg);
+                if (next->next != NULL) {
+                  if (TCP_SEQ_GT(next->tcphdr->seqno + next->len, seqno)) {
+                    /* We need to trim the last segment. */
+                    next->len = seqno - next->tcphdr->seqno;
+                    pbuf_realloc(next->p, next->len);
+                  }
+                }
+                break;
+              }
+            }
+            prev = next;
+          }
+        }
+#endif /* TCP_QUEUE_OOSEQ */
+
+      }
+    } else {
+      /*if (TCP_SEQ_GT(pcb->rcv_nxt, seqno) ||
+        TCP_SEQ_GEQ(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) {*/
+      if(!TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd-1)){
+        tcp_ack_now(pcb);
+      }
+    }
+  } else {
+    /* Segments with length 0 is taken care of here. Segments that
+       fall out of the window are ACKed. */
+    /*if (TCP_SEQ_GT(pcb->rcv_nxt, seqno) ||
+      TCP_SEQ_GEQ(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) {*/
+    if(!TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd-1)){
+      tcp_ack_now(pcb);
+    }
+  }
+}
+
+/*
+ * tcp_parseopt:
+ *
+ * Parses the options contained in the incoming segment. (Code taken
+ * from uIP with only small changes.)
+ *
+ */
+
+static void
+tcp_parseopt(struct tcp_pcb *pcb)
+{
+  u8_t c;
+  u8_t *opts, opt;
+  u16_t mss;
+
+  opts = (u8_t *)tcphdr + TCP_HLEN;
+
+  /* Parse the TCP MSS option, if present. */
+  if(TCPH_HDRLEN(tcphdr) > 0x5) {
+    for(c = 0; c < (TCPH_HDRLEN(tcphdr) - 5) << 2 ;) {
+      opt = opts[c];
+      if (opt == 0x00) {
+        /* End of options. */
+  break;
+      } else if (opt == 0x01) {
+        ++c;
+        /* NOP option. */
+      } else if (opt == 0x02 &&
+        opts[c + 1] == 0x04) {
+        /* An MSS option with the right option length. */
+        mss = (opts[c + 2] << 8) | opts[c + 3];
+        pcb->mss = mss > TCP_MSS? TCP_MSS: mss;
+
+        /* And we are done processing options. */
+        break;
+      } else {
+  if (opts[c + 1] == 0) {
+          /* If the length field is zero, the options are malformed
+             and we don't process them further. */
+          break;
+        }
+        /* All other options have a length field, so that we easily
+           can skip past them. */
+        c += opts[c + 1];
+      }
+    }
+  }
+}
+#endif /* LWIP_TCP */
+
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/tcp_out.c b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/tcp_out.c
new file mode 100644
index 000000000..3e5306e21
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/tcp_out.c
@@ -0,0 +1,721 @@
+/**
+ * @file
+ *
+ * Transmission Control Protocol, outgoing traffic
+ *
+ * The output functions of TCP.
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+#include 
+
+#include "lwip/def.h"
+#include "lwip/opt.h"
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+#include "lwip/sys.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/inet.h"
+#include "lwip/tcp.h"
+#include "lwip/stats.h"
+
+#if LWIP_TCP
+
+/* Forward declarations.*/
+static void tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb);
+
+err_t
+tcp_send_ctrl(struct tcp_pcb *pcb, u8_t flags)
+{
+  /* no data, no length, flags, copy=1, no optdata, no optdatalen */
+  return tcp_enqueue(pcb, NULL, 0, flags, 1, NULL, 0);
+}
+
+/**
+ * Write data for sending (but does not send it immediately).
+ *
+ * It waits in the expectation of more data being sent soon (as
+ * it can send them more efficiently by combining them together).
+ * To prompt the system to send data now, call tcp_output() after
+ * calling tcp_write().
+ * 
+ * @arg pcb Protocol control block of the TCP connection to enqueue data for. 
+ * 
+ * @see tcp_write()
+ */
+
+err_t
+tcp_write(struct tcp_pcb *pcb, const void *arg, u16_t len, u8_t copy)
+{
+  LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_write(pcb=%p, arg=%p, len=%"U16_F", copy=%"U16_F")\n", (void *)pcb,
+    arg, len, (u16_t)copy));
+  /* connection is in valid state for data transmission? */
+  if (pcb->state == ESTABLISHED ||
+     pcb->state == CLOSE_WAIT ||
+     pcb->state == SYN_SENT ||
+     pcb->state == SYN_RCVD) {
+    if (len > 0) {
+      return tcp_enqueue(pcb, (void *)arg, len, 0, copy, NULL, 0);
+    }
+    return ERR_OK;
+  } else {
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | DBG_STATE | 3, ("tcp_write() called in invalid state\n"));
+    return ERR_CONN;
+  }
+}
+
+/**
+ * Enqueue either data or TCP options (but not both) for tranmission
+ * 
+ * 
+ * 
+ * @arg pcb Protocol control block for the TCP connection to enqueue data for.
+ * @arg arg Pointer to the data to be enqueued for sending.
+ * @arg len Data length in bytes
+ * @arg flags
+ * @arg copy 1 if data must be copied, 0 if data is non-volatile and can be
+ * referenced.
+ * @arg optdata
+ * @arg optlen
+ */
+err_t
+tcp_enqueue(struct tcp_pcb *pcb, void *arg, u16_t len,
+  u8_t flags, u8_t copy,
+  u8_t *optdata, u8_t optlen)
+{
+  struct pbuf *p;
+  struct tcp_seg *seg, *useg, *queue;
+  u32_t left, seqno;
+  u16_t seglen;
+  void *ptr;
+  u8_t queuelen;
+
+  LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_enqueue(pcb=%p, arg=%p, len=%"U16_F", flags=%"X16_F", copy=%"U16_F")\n",
+    (void *)pcb, arg, len, (u16_t)flags, (u16_t)copy));
+  LWIP_ASSERT("tcp_enqueue: len == 0 || optlen == 0 (programmer violates API)",
+      len == 0 || optlen == 0);
+  LWIP_ASSERT("tcp_enqueue: arg == NULL || optdata == NULL (programmer violates API)",
+      arg == NULL || optdata == NULL);
+  /* fail on too much data */
+  if (len > pcb->snd_buf) {
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 3, ("tcp_enqueue: too much data (len=%"U16_F" > snd_buf=%"U16_F")\n", len, pcb->snd_buf));
+    return ERR_MEM;
+  }
+  left = len;
+  ptr = arg;
+
+  /* seqno will be the sequence number of the first segment enqueued
+   * by the call to this function. */
+  seqno = pcb->snd_lbb;
+
+  LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue: queuelen: %"U16_F"\n", (u16_t)pcb->snd_queuelen));
+
+  /* If total number of pbufs on the unsent/unacked queues exceeds the
+   * configured maximum, return an error */
+  queuelen = pcb->snd_queuelen;
+  if (queuelen >= TCP_SND_QUEUELEN) {
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 3, ("tcp_enqueue: too long queue %"U16_F" (max %"U16_F")\n", queuelen, TCP_SND_QUEUELEN));
+    TCP_STATS_INC(tcp.memerr);
+    return ERR_MEM;
+  }
+  if (queuelen != 0) {
+    LWIP_ASSERT("tcp_enqueue: pbufs on queue => at least one queue non-empty",
+      pcb->unacked != NULL || pcb->unsent != NULL);
+  } else {
+    LWIP_ASSERT("tcp_enqueue: no pbufs on queue => both queues empty",
+      pcb->unacked == NULL && pcb->unsent == NULL);
+  }
+
+  /* First, break up the data into segments and tuck them together in
+   * the local "queue" variable. */
+  useg = queue = seg = NULL;
+  seglen = 0;
+  while (queue == NULL || left > 0) {
+
+    /* The segment length should be the MSS if the data to be enqueued
+     * is larger than the MSS. */
+    seglen = left > pcb->mss? pcb->mss: left;
+
+    /* Allocate memory for tcp_seg, and fill in fields. */
+    seg = memp_malloc(MEMP_TCP_SEG);
+    if (seg == NULL) {
+      LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: could not allocate memory for tcp_seg\n"));
+      goto memerr;
+    }
+    seg->next = NULL;
+    seg->p = NULL;
+
+    /* first segment of to-be-queued data? */
+    if (queue == NULL) {
+      queue = seg;
+    }
+    /* subsequent segments of to-be-queued data */
+    else {
+      /* Attach the segment to the end of the queued segments */
+      LWIP_ASSERT("useg != NULL", useg != NULL);
+      useg->next = seg;
+    }
+    /* remember last segment of to-be-queued data for next iteration */
+    useg = seg;
+
+    /* If copy is set, memory should be allocated
+     * and data copied into pbuf, otherwise data comes from
+     * ROM or other static memory, and need not be copied. If
+     * optdata is != NULL, we have options instead of data. */
+     
+    /* options? */
+    if (optdata != NULL) {
+      if ((seg->p = pbuf_alloc(PBUF_TRANSPORT, optlen, PBUF_RAM)) == NULL) {
+        goto memerr;
+      }
+      ++queuelen;
+      seg->dataptr = seg->p->payload;
+    }
+    /* copy from volatile memory? */
+    else if (copy) {
+      if ((seg->p = pbuf_alloc(PBUF_TRANSPORT, seglen, PBUF_RAM)) == NULL) {
+        LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue : could not allocate memory for pbuf copy size %"U16_F"\n", seglen));
+        goto memerr;
+      }
+      ++queuelen;
+      if (arg != NULL) {
+        memcpy(seg->p->payload, ptr, seglen);
+      }
+      seg->dataptr = seg->p->payload;
+    }
+    /* do not copy data */
+    else {
+      /* First, allocate a pbuf for holding the data.
+       * since the referenced data is available at least until it is sent out on the
+       * link (as it has to be ACKed by the remote party) we can safely use PBUF_ROM
+       * instead of PBUF_REF here.
+       */
+      if ((p = pbuf_alloc(PBUF_TRANSPORT, seglen, PBUF_ROM)) == NULL) {
+        LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: could not allocate memory for zero-copy pbuf\n"));
+        goto memerr;
+      }
+      ++queuelen;
+      /* reference the non-volatile payload data */
+      p->payload = ptr;
+      seg->dataptr = ptr;
+
+      /* Second, allocate a pbuf for the headers. */
+      if ((seg->p = pbuf_alloc(PBUF_TRANSPORT, 0, PBUF_RAM)) == NULL) {
+        /* If allocation fails, we have to deallocate the data pbuf as
+         * well. */
+        pbuf_free(p);
+        LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: could not allocate memory for header pbuf\n"));
+        goto memerr;
+      }
+      ++queuelen;
+
+      /* Concatenate the headers and data pbufs together. */
+      pbuf_cat(seg->p/*header*/, p/*data*/);
+      p = NULL;
+    }
+
+    /* Now that there are more segments queued, we check again if the
+    length of the queue exceeds the configured maximum. */
+    if (queuelen > TCP_SND_QUEUELEN) {
+      LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: queue too long %"U16_F" (%"U16_F")\n", queuelen, TCP_SND_QUEUELEN));
+      goto memerr;
+    }
+
+    seg->len = seglen;
+
+    /* build TCP header */
+    if (pbuf_header(seg->p, TCP_HLEN)) {
+      LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: no room for TCP header in pbuf.\n"));
+      TCP_STATS_INC(tcp.err);
+      goto memerr;
+    }
+    seg->tcphdr = seg->p->payload;
+    seg->tcphdr->src = htons(pcb->local_port);
+    seg->tcphdr->dest = htons(pcb->remote_port);
+    seg->tcphdr->seqno = htonl(seqno);
+    seg->tcphdr->urgp = 0;
+    TCPH_FLAGS_SET(seg->tcphdr, flags);
+    /* don't fill in tcphdr->ackno and tcphdr->wnd until later */
+
+    /* Copy the options into the header, if they are present. */
+    if (optdata == NULL) {
+      TCPH_HDRLEN_SET(seg->tcphdr, 5);
+    }
+    else {
+      TCPH_HDRLEN_SET(seg->tcphdr, (5 + optlen / 4));
+      /* Copy options into data portion of segment.
+       Options can thus only be sent in non data carrying
+       segments such as SYN|ACK. */
+      memcpy(seg->dataptr, optdata, optlen);
+    }
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | DBG_TRACE, ("tcp_enqueue: queueing %"U32_F":%"U32_F" (0x%"X16_F")\n",
+      ntohl(seg->tcphdr->seqno),
+      ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg),
+      (u16_t)flags));
+
+    left -= seglen;
+    seqno += seglen;
+    ptr = (void *)((u8_t *)ptr + seglen);
+  }
+
+  /* Now that the data to be enqueued has been broken up into TCP
+  segments in the queue variable, we add them to the end of the
+  pcb->unsent queue. */
+  if (pcb->unsent == NULL) {
+    useg = NULL;
+  }
+  else {
+    for (useg = pcb->unsent; useg->next != NULL; useg = useg->next);
+  }
+  /* { useg is last segment on the unsent queue, NULL if list is empty } */
+
+  /* If there is room in the last pbuf on the unsent queue,
+  chain the first pbuf on the queue together with that. */
+  if (useg != NULL &&
+    TCP_TCPLEN(useg) != 0 &&
+    !(TCPH_FLAGS(useg->tcphdr) & (TCP_SYN | TCP_FIN)) &&
+    !(flags & (TCP_SYN | TCP_FIN)) &&
+    /* fit within max seg size */
+    useg->len + queue->len <= pcb->mss) {
+    /* Remove TCP header from first segment of our to-be-queued list */
+    pbuf_header(queue->p, -TCP_HLEN);
+    pbuf_cat(useg->p, queue->p);
+    useg->len += queue->len;
+    useg->next = queue->next;
+
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | DBG_TRACE | DBG_STATE, ("tcp_enqueue: chaining segments, new len %"U16_F"\n", useg->len));
+    if (seg == queue) {
+      seg = NULL;
+    }
+    memp_free(MEMP_TCP_SEG, queue);
+  }
+  else {
+    /* empty list */
+    if (useg == NULL) {
+      /* initialize list with this segment */
+      pcb->unsent = queue;
+    }
+    /* enqueue segment */
+    else {
+      useg->next = queue;
+    }
+  }
+  if ((flags & TCP_SYN) || (flags & TCP_FIN)) {
+    ++len;
+  }
+  pcb->snd_lbb += len;
+
+  pcb->snd_buf -= len;
+
+  /* update number of segments on the queues */
+  pcb->snd_queuelen = queuelen;
+  LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue: %"S16_F" (after enqueued)\n", pcb->snd_queuelen));
+  if (pcb->snd_queuelen != 0) {
+    LWIP_ASSERT("tcp_enqueue: valid queue length",
+      pcb->unacked != NULL || pcb->unsent != NULL);
+  }
+
+  /* Set the PSH flag in the last segment that we enqueued, but only
+  if the segment has data (indicated by seglen > 0). */
+  if (seg != NULL && seglen > 0 && seg->tcphdr != NULL) {
+    TCPH_SET_FLAG(seg->tcphdr, TCP_PSH);
+  }
+
+  return ERR_OK;
+memerr:
+  TCP_STATS_INC(tcp.memerr);
+
+  if (queue != NULL) {
+    tcp_segs_free(queue);
+  }
+  if (pcb->snd_queuelen != 0) {
+    LWIP_ASSERT("tcp_enqueue: valid queue length", pcb->unacked != NULL ||
+      pcb->unsent != NULL);
+  }
+  LWIP_DEBUGF(TCP_QLEN_DEBUG | DBG_STATE, ("tcp_enqueue: %"S16_F" (with mem err)\n", pcb->snd_queuelen));
+  return ERR_MEM;
+}
+
+/* find out what we can send and send it */
+err_t
+tcp_output(struct tcp_pcb *pcb)
+{
+  struct pbuf *p;
+  struct tcp_hdr *tcphdr;
+  struct tcp_seg *seg, *useg;
+  u32_t wnd;
+#if TCP_CWND_DEBUG
+  s16_t i = 0;
+#endif /* TCP_CWND_DEBUG */
+
+  /* First, check if we are invoked by the TCP input processing
+     code. If so, we do not output anything. Instead, we rely on the
+     input processing code to call us when input processing is done
+     with. */
+  if (tcp_input_pcb == pcb) {
+    return ERR_OK;
+  }
+
+  wnd = LWIP_MIN(pcb->snd_wnd, pcb->cwnd);
+
+  seg = pcb->unsent;
+
+  /* useg should point to last segment on unacked queue */
+  useg = pcb->unacked;
+  if (useg != NULL) {
+    for (; useg->next != NULL; useg = useg->next);
+  }                                                                             
+   
+  /* If the TF_ACK_NOW flag is set and no data will be sent (either
+   * because the ->unsent queue is empty or because the window does
+   * not allow it), construct an empty ACK segment and send it.
+   *
+   * If data is to be sent, we will just piggyback the ACK (see below).
+   */
+  if (pcb->flags & TF_ACK_NOW &&
+     (seg == NULL ||
+      ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len > wnd)) {
+    p = pbuf_alloc(PBUF_IP, TCP_HLEN, PBUF_RAM);
+    if (p == NULL) {
+      LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: (ACK) could not allocate pbuf\n"));
+      return ERR_BUF;
+    }
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: sending ACK for %"U32_F"\n", pcb->rcv_nxt));
+    /* remove ACK flags from the PCB, as we send an empty ACK now */
+    pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW);
+
+    tcphdr = p->payload;
+    tcphdr->src = htons(pcb->local_port);
+    tcphdr->dest = htons(pcb->remote_port);
+    tcphdr->seqno = htonl(pcb->snd_nxt);
+    tcphdr->ackno = htonl(pcb->rcv_nxt);
+    TCPH_FLAGS_SET(tcphdr, TCP_ACK);
+    tcphdr->wnd = htons(pcb->rcv_wnd);
+    tcphdr->urgp = 0;
+    TCPH_HDRLEN_SET(tcphdr, 5);
+
+    tcphdr->chksum = 0;
+#if CHECKSUM_GEN_TCP
+    tcphdr->chksum = inet_chksum_pseudo(p, &(pcb->local_ip), &(pcb->remote_ip),
+          IP_PROTO_TCP, p->tot_len);
+#endif
+    ip_output(p, &(pcb->local_ip), &(pcb->remote_ip), pcb->ttl, pcb->tos,
+        IP_PROTO_TCP);
+    pbuf_free(p);
+
+    return ERR_OK;
+  }
+
+#if TCP_OUTPUT_DEBUG
+  if (seg == NULL) {
+    LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: nothing to send (%p)\n", (void*)pcb->unsent));
+  }
+#endif /* TCP_OUTPUT_DEBUG */
+#if TCP_CWND_DEBUG
+  if (seg == NULL) {
+    LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %"U32_F", cwnd %"U16_F", wnd %"U32_F", seg == NULL, ack %"U32_F"\n",
+                            pcb->snd_wnd, pcb->cwnd, wnd,
+                            pcb->lastack));
+  } else {
+    LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %"U32_F", cwnd %"U16_F", wnd %"U32_F", effwnd %"U32_F", seq %"U32_F", ack %"U32_F"\n",
+                            pcb->snd_wnd, pcb->cwnd, wnd,
+                            ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len,
+                            ntohl(seg->tcphdr->seqno), pcb->lastack));
+  }
+#endif /* TCP_CWND_DEBUG */
+  /* data available and window allows it to be sent? */
+  while (seg != NULL &&
+  ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len <= wnd) {
+#if TCP_CWND_DEBUG
+    LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %"U32_F", cwnd %"U16_F", wnd %"U32_F", effwnd %"U32_F", seq %"U32_F", ack %"U32_F", i %"S16_F"\n",
+                            pcb->snd_wnd, pcb->cwnd, wnd,
+                            ntohl(seg->tcphdr->seqno) + seg->len -
+                            pcb->lastack,
+                            ntohl(seg->tcphdr->seqno), pcb->lastack, i));
+    ++i;
+#endif /* TCP_CWND_DEBUG */
+
+    pcb->unsent = seg->next;
+
+    if (pcb->state != SYN_SENT) {
+      TCPH_SET_FLAG(seg->tcphdr, TCP_ACK);
+      pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW);
+    }
+
+    tcp_output_segment(seg, pcb);
+    pcb->snd_nxt = ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg);
+    if (TCP_SEQ_LT(pcb->snd_max, pcb->snd_nxt)) {
+      pcb->snd_max = pcb->snd_nxt;
+    }
+    /* put segment on unacknowledged list if length > 0 */
+    if (TCP_TCPLEN(seg) > 0) {
+      seg->next = NULL;
+      /* unacked list is empty? */
+      if (pcb->unacked == NULL) {
+        pcb->unacked = seg;
+        useg = seg;
+      /* unacked list is not empty? */
+      } else {
+        /* In the case of fast retransmit, the packet should not go to the tail
+         * of the unacked queue, but rather at the head. We need to check for
+         * this case. -STJ Jul 27, 2004 */
+        if (TCP_SEQ_LT(ntohl(seg->tcphdr->seqno), ntohl(useg->tcphdr->seqno))){
+          /* add segment to head of unacked list */
+          seg->next = pcb->unacked;
+          pcb->unacked = seg;
+        } else {
+          /* add segment to tail of unacked list */
+          useg->next = seg;
+          useg = useg->next;
+        }
+      }
+    /* do not queue empty segments on the unacked list */
+    } else {
+      tcp_seg_free(seg);
+    }
+    seg = pcb->unsent;
+  }
+  return ERR_OK;
+}
+
+/**
+ * Actually send a TCP segment over IP
+ */
+static void
+tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb)
+{
+  u16_t len;
+  struct netif *netif;
+
+  /* The TCP header has already been constructed, but the ackno and
+   wnd fields remain. */
+  seg->tcphdr->ackno = htonl(pcb->rcv_nxt);
+
+  /* silly window avoidance */
+  if (pcb->rcv_wnd < pcb->mss) {
+    seg->tcphdr->wnd = 0;
+  } else {
+    /* advertise our receive window size in this TCP segment */
+    seg->tcphdr->wnd = htons(pcb->rcv_wnd);
+  }
+
+  /* If we don't have a local IP address, we get one by
+     calling ip_route(). */
+  if (ip_addr_isany(&(pcb->local_ip))) {
+    netif = ip_route(&(pcb->remote_ip));
+    if (netif == NULL) {
+      return;
+    }
+    ip_addr_set(&(pcb->local_ip), &(netif->ip_addr));
+  }
+
+  pcb->rtime = 0;
+
+  if (pcb->rttest == 0) {
+    pcb->rttest = tcp_ticks;
+    pcb->rtseq = ntohl(seg->tcphdr->seqno);
+
+    LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_output_segment: rtseq %"U32_F"\n", pcb->rtseq));
+  }
+  LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output_segment: %"U32_F":%"U32_F"\n",
+          htonl(seg->tcphdr->seqno), htonl(seg->tcphdr->seqno) +
+          seg->len));
+
+  len = (u16_t)((u8_t *)seg->tcphdr - (u8_t *)seg->p->payload);
+
+  seg->p->len -= len;
+  seg->p->tot_len -= len;
+
+  seg->p->payload = seg->tcphdr;
+
+  seg->tcphdr->chksum = 0;
+#if CHECKSUM_GEN_TCP
+  seg->tcphdr->chksum = inet_chksum_pseudo(seg->p,
+             &(pcb->local_ip),
+             &(pcb->remote_ip),
+             IP_PROTO_TCP, seg->p->tot_len);
+#endif
+  TCP_STATS_INC(tcp.xmit);
+
+  ip_output(seg->p, &(pcb->local_ip), &(pcb->remote_ip), pcb->ttl, pcb->tos,
+      IP_PROTO_TCP);
+}
+
+void
+tcp_rst(u32_t seqno, u32_t ackno,
+  struct ip_addr *local_ip, struct ip_addr *remote_ip,
+  u16_t local_port, u16_t remote_port)
+{
+  struct pbuf *p;
+  struct tcp_hdr *tcphdr;
+  p = pbuf_alloc(PBUF_IP, TCP_HLEN, PBUF_RAM);
+  if (p == NULL) {
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_rst: could not allocate memory for pbuf\n"));
+      return;
+  }
+
+  tcphdr = p->payload;
+  tcphdr->src = htons(local_port);
+  tcphdr->dest = htons(remote_port);
+  tcphdr->seqno = htonl(seqno);
+  tcphdr->ackno = htonl(ackno);
+  TCPH_FLAGS_SET(tcphdr, TCP_RST | TCP_ACK);
+  tcphdr->wnd = htons(TCP_WND);
+  tcphdr->urgp = 0;
+  TCPH_HDRLEN_SET(tcphdr, 5);
+
+  tcphdr->chksum = 0;
+#if CHECKSUM_GEN_TCP
+  tcphdr->chksum = inet_chksum_pseudo(p, local_ip, remote_ip,
+              IP_PROTO_TCP, p->tot_len);
+#endif
+  TCP_STATS_INC(tcp.xmit);
+   /* Send output with hardcoded TTL since we have no access to the pcb */
+  ip_output(p, local_ip, remote_ip, TCP_TTL, 0, IP_PROTO_TCP);
+  pbuf_free(p);
+  LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_rst: seqno %"U32_F" ackno %"U32_F".\n", seqno, ackno));
+}
+
+/* requeue all unacked segments for retransmission */
+void
+tcp_rexmit_rto(struct tcp_pcb *pcb)
+{
+  struct tcp_seg *seg;
+
+  if (pcb->unacked == NULL) {
+    return;
+  }
+
+  /* Move all unacked segments to the head of the unsent queue */
+  for (seg = pcb->unacked; seg->next != NULL; seg = seg->next);
+  /* concatenate unsent queue after unacked queue */
+  seg->next = pcb->unsent;
+  /* unsent queue is the concatenated queue (of unacked, unsent) */
+  pcb->unsent = pcb->unacked;
+  /* unacked queue is now empty */
+  pcb->unacked = NULL;
+
+  pcb->snd_nxt = ntohl(pcb->unsent->tcphdr->seqno);
+  /* increment number of retransmissions */
+  ++pcb->nrtx;
+
+  /* Don't take any RTT measurements after retransmitting. */
+  pcb->rttest = 0;
+
+  /* Do the actual retransmission */
+  tcp_output(pcb);
+}
+
+void
+tcp_rexmit(struct tcp_pcb *pcb)
+{
+  struct tcp_seg *seg;
+
+  if (pcb->unacked == NULL) {
+    return;
+  }
+
+  /* Move the first unacked segment to the unsent queue */
+  seg = pcb->unacked->next;
+  pcb->unacked->next = pcb->unsent;
+  pcb->unsent = pcb->unacked;
+  pcb->unacked = seg;
+
+  pcb->snd_nxt = ntohl(pcb->unsent->tcphdr->seqno);
+
+  ++pcb->nrtx;
+
+  /* Don't take any rtt measurements after retransmitting. */
+  pcb->rttest = 0;
+
+  /* Do the actual retransmission. */
+  tcp_output(pcb);
+
+}
+
+
+void
+tcp_keepalive(struct tcp_pcb *pcb)
+{
+   struct pbuf *p;
+   struct tcp_hdr *tcphdr;
+
+   LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: sending KEEPALIVE probe to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
+                           ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip),
+                           ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip)));
+
+   LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: tcp_ticks %"U32_F"   pcb->tmr %"U32_F"  pcb->keep_cnt %"U16_F"\n", tcp_ticks, pcb->tmr, pcb->keep_cnt));
+   
+   p = pbuf_alloc(PBUF_IP, TCP_HLEN, PBUF_RAM);
+
+   if(p == NULL) {
+      LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: could not allocate memory for pbuf\n"));
+      return;
+   }
+
+   tcphdr = p->payload;
+   tcphdr->src = htons(pcb->local_port);
+   tcphdr->dest = htons(pcb->remote_port);
+   tcphdr->seqno = htonl(pcb->snd_nxt - 1);
+   tcphdr->ackno = htonl(pcb->rcv_nxt);
+   tcphdr->wnd = htons(pcb->rcv_wnd);
+   tcphdr->urgp = 0;
+   TCPH_HDRLEN_SET(tcphdr, 5);
+   
+   tcphdr->chksum = 0;
+#if CHECKSUM_GEN_TCP
+   tcphdr->chksum = inet_chksum_pseudo(p, &pcb->local_ip, &pcb->remote_ip, IP_PROTO_TCP, p->tot_len);
+#endif
+  TCP_STATS_INC(tcp.xmit);
+
+   /* Send output to IP */
+  ip_output(p, &pcb->local_ip, &pcb->remote_ip, pcb->ttl, 0, IP_PROTO_TCP);
+
+  pbuf_free(p);
+
+  LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_keepalive: seqno %"U32_F" ackno %"U32_F".\n", pcb->snd_nxt - 1, pcb->rcv_nxt));
+}
+
+#endif /* LWIP_TCP */
+
+
+
+
+
+
+
+
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/udp.c b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/udp.c
new file mode 100644
index 000000000..76ff59dba
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/core/udp.c
@@ -0,0 +1,655 @@
+/**
+ * @file
+ * User Datagram Protocol module
+ *
+ */
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+
+
+/* udp.c
+ *
+ * The code for the User Datagram Protocol UDP.
+ *
+ */
+
+#include 
+
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+#include "lwip/memp.h"
+#include "lwip/inet.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/udp.h"
+#include "lwip/icmp.h"
+
+#include "lwip/stats.h"
+
+#include "arch/perf.h"
+#include "lwip/snmp.h"
+
+/* The list of UDP PCBs */
+#if LWIP_UDP
+/* was static, but we may want to access this from a socket layer */
+struct udp_pcb *udp_pcbs = NULL;
+
+static struct udp_pcb *pcb_cache = NULL;
+
+void
+udp_init(void)
+{
+  udp_pcbs = pcb_cache = NULL;
+}
+
+/**
+ * Process an incoming UDP datagram.
+ *
+ * Given an incoming UDP datagram (as a chain of pbufs) this function
+ * finds a corresponding UDP PCB and
+ *
+ * @param pbuf pbuf to be demultiplexed to a UDP PCB.
+ * @param netif network interface on which the datagram was received.
+ *
+ */
+void
+udp_input(struct pbuf *p, struct netif *inp)
+{
+  struct udp_hdr *udphdr;
+  struct udp_pcb *pcb;
+  struct udp_pcb *uncon_pcb;
+  struct ip_hdr *iphdr;
+  u16_t src, dest;
+  u8_t local_match;
+
+  PERF_START;
+
+  UDP_STATS_INC(udp.recv);
+
+  iphdr = p->payload;
+
+  if (pbuf_header(p, -((s16_t)(UDP_HLEN + IPH_HL(iphdr) * 4)))) {
+    /* drop short packets */
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_input: short UDP datagram (%"U16_F" bytes) discarded\n", p->tot_len));
+    UDP_STATS_INC(udp.lenerr);
+    UDP_STATS_INC(udp.drop);
+    snmp_inc_udpinerrors();
+    pbuf_free(p);
+    goto end;
+  }
+
+  udphdr = (struct udp_hdr *)((u8_t *)p->payload - UDP_HLEN);
+
+  LWIP_DEBUGF(UDP_DEBUG, ("udp_input: received datagram of length %"U16_F"\n", p->tot_len));
+
+  src = ntohs(udphdr->src);
+  dest = ntohs(udphdr->dest);
+
+  udp_debug_print(udphdr);
+
+  /* print the UDP source and destination */
+  LWIP_DEBUGF(UDP_DEBUG, ("udp (%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F") <-- (%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F")\n",
+    ip4_addr1(&iphdr->dest), ip4_addr2(&iphdr->dest),
+    ip4_addr3(&iphdr->dest), ip4_addr4(&iphdr->dest), ntohs(udphdr->dest),
+    ip4_addr1(&iphdr->src), ip4_addr2(&iphdr->src),
+    ip4_addr3(&iphdr->src), ip4_addr4(&iphdr->src), ntohs(udphdr->src)));
+
+  local_match = 0;
+  uncon_pcb = NULL;
+  /* Iterate through the UDP pcb list for a matching pcb */
+  for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) {
+    /* print the PCB local and remote address */
+    LWIP_DEBUGF(UDP_DEBUG, ("pcb (%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F") --- (%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F")\n",
+      ip4_addr1(&pcb->local_ip), ip4_addr2(&pcb->local_ip),
+      ip4_addr3(&pcb->local_ip), ip4_addr4(&pcb->local_ip), pcb->local_port,
+      ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip),
+      ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip), pcb->remote_port));
+
+    /* compare PCB local addr+port to UDP destination addr+port */
+    if ((pcb->local_port == dest) &&
+       (ip_addr_isany(&pcb->local_ip) ||
+        ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest)))) {
+       local_match = 1;
+       if ((uncon_pcb == NULL) && 
+           ((pcb->flags & UDP_FLAGS_CONNECTED) == 0)) {
+         /* the first unconnected matching PCB */     
+         uncon_pcb = pcb;
+       }
+    }
+    /* compare PCB remote addr+port to UDP source addr+port */
+    if ((local_match != 0) &&
+       (pcb->remote_port == src) &&
+       (ip_addr_isany(&pcb->remote_ip) ||
+       ip_addr_cmp(&(pcb->remote_ip), &(iphdr->src)))) {
+       /* the first fully matching PCB */
+      break;
+    }
+  }
+  /* no fully matching pcb found? then look for an unconnected pcb */
+  if (pcb == NULL) {
+    pcb = uncon_pcb;
+  }
+
+  /* Check checksum if this is a match or if it was directed at us. */
+  if (pcb != NULL  || ip_addr_cmp(&inp->ip_addr, &iphdr->dest))
+    {
+    LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE, ("udp_input: calculating checksum\n"));
+    pbuf_header(p, UDP_HLEN);
+#ifdef IPv6
+    if (iphdr->nexthdr == IP_PROTO_UDPLITE) {
+#else
+    if (IPH_PROTO(iphdr) == IP_PROTO_UDPLITE) {
+#endif /* IPv4 */
+      /* Do the UDP Lite checksum */
+#if CHECKSUM_CHECK_UDP
+      if (inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src),
+         (struct ip_addr *)&(iphdr->dest),
+         IP_PROTO_UDPLITE, ntohs(udphdr->len)) != 0) {
+  LWIP_DEBUGF(UDP_DEBUG | 2, ("udp_input: UDP Lite datagram discarded due to failing checksum\n"));
+  UDP_STATS_INC(udp.chkerr);
+  UDP_STATS_INC(udp.drop);
+  snmp_inc_udpinerrors();
+  pbuf_free(p);
+  goto end;
+      }
+#endif
+    } else {
+#if CHECKSUM_CHECK_UDP
+      if (udphdr->chksum != 0) {
+  if (inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src),
+       (struct ip_addr *)&(iphdr->dest),
+        IP_PROTO_UDP, p->tot_len) != 0) {
+    LWIP_DEBUGF(UDP_DEBUG | 2, ("udp_input: UDP datagram discarded due to failing checksum\n"));
+
+    UDP_STATS_INC(udp.chkerr);
+    UDP_STATS_INC(udp.drop);
+    snmp_inc_udpinerrors();
+    pbuf_free(p);
+    goto end;
+  }
+      }
+#endif
+    }
+    pbuf_header(p, -UDP_HLEN);
+    if (pcb != NULL) {
+      snmp_inc_udpindatagrams();
+      /* callback */
+      if (pcb->recv != NULL)
+      {
+        pcb->recv(pcb->recv_arg, pcb, p, &(iphdr->src), src);
+      }
+        } else {
+      LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE, ("udp_input: not for us.\n"));
+
+      /* No match was found, send ICMP destination port unreachable unless
+      destination address was broadcast/multicast. */
+
+      if (!ip_addr_isbroadcast(&iphdr->dest, inp) &&
+          !ip_addr_ismulticast(&iphdr->dest)) {
+
+  /* adjust pbuf pointer */
+  p->payload = iphdr;
+  icmp_dest_unreach(p, ICMP_DUR_PORT);
+      }
+      UDP_STATS_INC(udp.proterr);
+      UDP_STATS_INC(udp.drop);
+    snmp_inc_udpnoports();
+      pbuf_free(p);
+    }
+  } else {
+    pbuf_free(p);
+  }
+  end:
+
+  PERF_STOP("udp_input");
+}
+
+/**
+ * Send data to a specified address using UDP.
+ *
+ * @param pcb UDP PCB used to send the data.
+ * @param pbuf chain of pbuf's to be sent.
+ * @param dst_ip Destination IP address.
+ * @param dst_port Destination UDP port.
+ *
+ * If the PCB already has a remote address association, it will
+ * be restored after the data is sent.
+ * 
+ * @return lwIP error code.
+ * - ERR_OK. Successful. No error occured.
+ * - ERR_MEM. Out of memory.
+ * - ERR_RTE. Could not find route to destination address.
+ *
+ * @see udp_disconnect() udp_send()
+ */
+err_t
+udp_sendto(struct udp_pcb *pcb, struct pbuf *p,
+  struct ip_addr *dst_ip, u16_t dst_port)
+{
+  err_t err;
+  /* temporary space for current PCB remote address */
+  struct ip_addr pcb_remote_ip;
+  u16_t pcb_remote_port;
+  /* remember current remote peer address of PCB */
+  pcb_remote_ip.addr = pcb->remote_ip.addr;
+  pcb_remote_port = pcb->remote_port;
+  /* copy packet destination address to PCB remote peer address */
+  pcb->remote_ip.addr = dst_ip->addr;
+  pcb->remote_port = dst_port;
+  /* send to the packet destination address */
+  err = udp_send(pcb, p);
+  /* restore PCB remote peer address */
+  pcb->remote_ip.addr = pcb_remote_ip.addr;
+  pcb->remote_port = pcb_remote_port;
+  return err;
+}
+
+/**
+ * Send data using UDP.
+ *
+ * @param pcb UDP PCB used to send the data.
+ * @param pbuf chain of pbuf's to be sent.
+ *
+ * @return lwIP error code.
+ * - ERR_OK. Successful. No error occured.
+ * - ERR_MEM. Out of memory.
+ * - ERR_RTE. Could not find route to destination address.
+ *
+ * @see udp_disconnect() udp_sendto()
+ */
+err_t
+udp_send(struct udp_pcb *pcb, struct pbuf *p)
+{
+  struct udp_hdr *udphdr;
+  struct netif *netif;
+  struct ip_addr *src_ip;
+  err_t err;
+  struct pbuf *q; /* q will be sent down the stack */
+
+  LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 3, ("udp_send\n"));
+
+  /* if the PCB is not yet bound to a port, bind it here */
+  if (pcb->local_port == 0) {
+    LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 2, ("udp_send: not yet bound to a port, binding now\n"));
+    err = udp_bind(pcb, &pcb->local_ip, pcb->local_port);
+    if (err != ERR_OK) {
+      LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 2, ("udp_send: forced port bind failed\n"));
+      return err;
+    }
+  }
+  /* find the outgoing network interface for this packet */
+  netif = ip_route(&(pcb->remote_ip));
+  /* no outgoing network interface could be found? */
+  if (netif == NULL) {
+    LWIP_DEBUGF(UDP_DEBUG | 1, ("udp_send: No route to 0x%"X32_F"\n", pcb->remote_ip.addr));
+    UDP_STATS_INC(udp.rterr);
+    return ERR_RTE;
+  }
+
+  /* not enough space to add an UDP header to first pbuf in given p chain? */
+  if (pbuf_header(p, UDP_HLEN)) {
+    /* allocate header in a seperate new pbuf */
+    q = pbuf_alloc(PBUF_IP, UDP_HLEN, PBUF_RAM);
+    /* new header pbuf could not be allocated? */
+    if (q == NULL) {
+      LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 2, ("udp_send: could not allocate header\n"));
+      return ERR_MEM;
+    }
+    /* chain header q in front of given pbuf p */
+    pbuf_chain(q, p);
+    /* { first pbuf q points to header pbuf } */
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: added header pbuf %p before given pbuf %p\n", (void *)q, (void *)p));
+  /* adding a header within p succeeded */
+  } else {
+    /* first pbuf q equals given pbuf */
+    q = p;
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: added header in given pbuf %p\n", (void *)p));
+  }
+  /* { q now represents the packet to be sent } */
+  udphdr = q->payload;
+  udphdr->src = htons(pcb->local_port);
+  udphdr->dest = htons(pcb->remote_port);
+  /* in UDP, 0 checksum means 'no checksum' */
+  udphdr->chksum = 0x0000; 
+
+  /* PCB local address is IP_ANY_ADDR? */
+  if (ip_addr_isany(&pcb->local_ip)) {
+    /* use outgoing network interface IP address as source address */
+    src_ip = &(netif->ip_addr);
+  } else {
+    /* use UDP PCB local IP address as source address */
+    src_ip = &(pcb->local_ip);
+  }
+
+  LWIP_DEBUGF(UDP_DEBUG, ("udp_send: sending datagram of length %"U16_F"\n", q->tot_len));
+
+  /* UDP Lite protocol? */
+  if (pcb->flags & UDP_FLAGS_UDPLITE) {
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP LITE packet length %"U16_F"\n", q->tot_len));
+    /* set UDP message length in UDP header */
+    udphdr->len = htons(pcb->chksum_len);
+    /* calculate checksum */
+#if CHECKSUM_GEN_UDP
+    udphdr->chksum = inet_chksum_pseudo(q, src_ip, &(pcb->remote_ip),
+          IP_PROTO_UDP, pcb->chksum_len);
+    /* chksum zero must become 0xffff, as zero means 'no checksum' */
+    if (udphdr->chksum == 0x0000) udphdr->chksum = 0xffff;
+#else
+    udphdr->chksum = 0x0000;
+#endif
+    /* output to IP */
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: ip_output_if (,,,,IP_PROTO_UDPLITE,)\n"));
+    err = ip_output_if (q, src_ip, &pcb->remote_ip, pcb->ttl, pcb->tos, IP_PROTO_UDPLITE, netif);    
+  /* UDP */
+  } else {
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP packet length %"U16_F"\n", q->tot_len));
+    udphdr->len = htons(q->tot_len);
+    /* calculate checksum */
+#if CHECKSUM_GEN_UDP
+    if ((pcb->flags & UDP_FLAGS_NOCHKSUM) == 0) {
+      udphdr->chksum = inet_chksum_pseudo(q, src_ip, &pcb->remote_ip, IP_PROTO_UDP, q->tot_len);
+      /* chksum zero must become 0xffff, as zero means 'no checksum' */
+      if (udphdr->chksum == 0x0000) udphdr->chksum = 0xffff;
+    }
+#else
+    udphdr->chksum = 0x0000;
+#endif
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP checksum 0x%04"X16_F"\n", udphdr->chksum));
+    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: ip_output_if (,,,,IP_PROTO_UDP,)\n"));
+    /* output to IP */
+    err = ip_output_if(q, src_ip, &pcb->remote_ip, pcb->ttl, pcb->tos, IP_PROTO_UDP, netif);    
+  }
+  /* TODO: must this be increased even if error occured? */
+  snmp_inc_udpoutdatagrams();
+
+  /* did we chain a seperate header pbuf earlier? */
+  if (q != p) {
+    /* free the header pbuf */
+    pbuf_free(q); q = NULL;
+    /* { p is still referenced by the caller, and will live on } */
+  }
+
+  UDP_STATS_INC(udp.xmit);
+  return err;
+}
+
+/**
+ * Bind an UDP PCB.
+ *
+ * @param pcb UDP PCB to be bound with a local address ipaddr and port.
+ * @param ipaddr local IP address to bind with. Use IP_ADDR_ANY to
+ * bind to all local interfaces.
+ * @param port local UDP port to bind with.
+ *
+ * @return lwIP error code.
+ * - ERR_OK. Successful. No error occured.
+ * - ERR_USE. The specified ipaddr and port are already bound to by
+ * another UDP PCB.
+ *
+ * @see udp_disconnect()
+ */
+err_t
+udp_bind(struct udp_pcb *pcb, struct ip_addr *ipaddr, u16_t port)
+{
+  struct udp_pcb *ipcb;
+  u8_t rebind;
+
+  LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 3, ("udp_bind(ipaddr = "));
+  ip_addr_debug_print(UDP_DEBUG, ipaddr);
+  LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 3, (", port = %"U16_F")\n", port));
+
+  rebind = 0;
+  /* Check for double bind and rebind of the same pcb */
+  for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
+    /* is this UDP PCB already on active list? */
+    if (pcb == ipcb) {
+      /* pcb may occur at most once in active list */
+      LWIP_ASSERT("rebind == 0", rebind == 0);
+      /* pcb already in list, just rebind */
+      rebind = 1;
+    }
+
+/* this code does not allow upper layer to share a UDP port for
+   listening to broadcast or multicast traffic (See SO_REUSE_ADDR and
+   SO_REUSE_PORT under *BSD). TODO: See where it fits instead, OR
+   combine with implementation of UDP PCB flags. Leon Woestenberg. */
+#ifdef LWIP_UDP_TODO
+    /* port matches that of PCB in list? */
+    else if ((ipcb->local_port == port) &&
+       /* IP address matches, or one is IP_ADDR_ANY? */
+       (ip_addr_isany(&(ipcb->local_ip)) ||
+       ip_addr_isany(ipaddr) ||
+       ip_addr_cmp(&(ipcb->local_ip), ipaddr))) {
+      /* other PCB already binds to this local IP and port */
+      LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: local port %"U16_F" already bound by another pcb\n", port));
+      return ERR_USE;
+    }
+#endif
+
+  }
+
+  ip_addr_set(&pcb->local_ip, ipaddr);
+  /* no port specified? */
+  if (port == 0) {
+#ifndef UDP_LOCAL_PORT_RANGE_START
+#define UDP_LOCAL_PORT_RANGE_START 4096
+#define UDP_LOCAL_PORT_RANGE_END   0x7fff
+#endif
+    port = UDP_LOCAL_PORT_RANGE_START;
+    ipcb = udp_pcbs;
+    while ((ipcb != NULL) && (port != UDP_LOCAL_PORT_RANGE_END)) {
+      if (ipcb->local_port == port) {
+        port++;
+        ipcb = udp_pcbs;
+      } else
+        ipcb = ipcb->next;
+    }
+    if (ipcb != NULL) {
+      /* no more ports available in local range */
+      LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: out of free UDP ports\n"));
+      return ERR_USE;
+    }
+  }
+  pcb->local_port = port;
+  /* pcb not active yet? */
+  if (rebind == 0) {
+    /* place the PCB on the active list if not already there */
+    pcb->next = udp_pcbs;
+    udp_pcbs = pcb;
+  }
+  LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | DBG_STATE, ("udp_bind: bound to %"U16_F".%"U16_F".%"U16_F".%"U16_F", port %"U16_F"\n",
+   (u16_t)(ntohl(pcb->local_ip.addr) >> 24 & 0xff),
+   (u16_t)(ntohl(pcb->local_ip.addr) >> 16 & 0xff),
+   (u16_t)(ntohl(pcb->local_ip.addr) >> 8 & 0xff),
+   (u16_t)(ntohl(pcb->local_ip.addr) & 0xff), pcb->local_port));
+  return ERR_OK;
+}
+/**
+ * Connect an UDP PCB.
+ *
+ * This will associate the UDP PCB with the remote address.
+ *
+ * @param pcb UDP PCB to be connected with remote address ipaddr and port.
+ * @param ipaddr remote IP address to connect with.
+ * @param port remote UDP port to connect with.
+ *
+ * @return lwIP error code
+ *
+ * @see udp_disconnect()
+ */
+err_t
+udp_connect(struct udp_pcb *pcb, struct ip_addr *ipaddr, u16_t port)
+{
+  struct udp_pcb *ipcb;
+
+  if (pcb->local_port == 0) {
+    err_t err = udp_bind(pcb, &pcb->local_ip, pcb->local_port);
+    if (err != ERR_OK)
+      return err;
+  }
+
+  ip_addr_set(&pcb->remote_ip, ipaddr);
+  pcb->remote_port = port;
+  pcb->flags |= UDP_FLAGS_CONNECTED;
+/** TODO: this functionality belongs in upper layers */
+#ifdef LWIP_UDP_TODO
+  /* Nail down local IP for netconn_addr()/getsockname() */
+  if (ip_addr_isany(&pcb->local_ip) && !ip_addr_isany(&pcb->remote_ip)) {
+    struct netif *netif;
+
+    if ((netif = ip_route(&(pcb->remote_ip))) == NULL) {
+      LWIP_DEBUGF(UDP_DEBUG, ("udp_connect: No route to 0x%lx\n", pcb->remote_ip.addr));
+        UDP_STATS_INC(udp.rterr);
+      return ERR_RTE;
+    }
+    /** TODO: this will bind the udp pcb locally, to the interface which
+        is used to route output packets to the remote address. However, we
+        might want to accept incoming packets on any interface! */
+    pcb->local_ip = netif->ip_addr;
+  } else if (ip_addr_isany(&pcb->remote_ip)) {
+    pcb->local_ip.addr = 0;
+  }
+#endif
+  LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | DBG_STATE, ("udp_connect: connected to %"U16_F".%"U16_F".%"U16_F".%"U16_F",port %"U16_F"\n",
+   (u16_t)(ntohl(pcb->remote_ip.addr) >> 24 & 0xff),
+   (u16_t)(ntohl(pcb->remote_ip.addr) >> 16 & 0xff),
+   (u16_t)(ntohl(pcb->remote_ip.addr) >> 8 & 0xff),
+   (u16_t)(ntohl(pcb->remote_ip.addr) & 0xff), pcb->remote_port));
+
+  /* Insert UDP PCB into the list of active UDP PCBs. */
+  for(ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
+    if (pcb == ipcb) {
+      /* already on the list, just return */
+      return ERR_OK;
+    }
+  }
+  /* PCB not yet on the list, add PCB now */
+  pcb->next = udp_pcbs;
+  udp_pcbs = pcb;
+  return ERR_OK;
+}
+
+void
+udp_disconnect(struct udp_pcb *pcb)
+{
+  /* reset remote address association */
+  ip_addr_set(&pcb->remote_ip, IP_ADDR_ANY);
+  pcb->remote_port = 0;
+  /* mark PCB as unconnected */
+  pcb->flags &= ~UDP_FLAGS_CONNECTED;
+}
+
+void
+udp_recv(struct udp_pcb *pcb,
+   void (* recv)(void *arg, struct udp_pcb *upcb, struct pbuf *p,
+           struct ip_addr *addr, u16_t port),
+   void *recv_arg)
+{
+  /* remember recv() callback and user data */
+  pcb->recv = recv;
+  pcb->recv_arg = recv_arg;
+}
+/**
+ * Remove an UDP PCB.
+ *
+ * @param pcb UDP PCB to be removed. The PCB is removed from the list of
+ * UDP PCB's and the data structure is freed from memory.
+ *
+ * @see udp_new()
+ */
+void
+udp_remove(struct udp_pcb *pcb)
+{
+  struct udp_pcb *pcb2;
+  /* pcb to be removed is first in list? */
+  if (udp_pcbs == pcb) {
+    /* make list start at 2nd pcb */
+    udp_pcbs = udp_pcbs->next;
+  /* pcb not 1st in list */
+  } else for(pcb2 = udp_pcbs; pcb2 != NULL; pcb2 = pcb2->next) {
+    /* find pcb in udp_pcbs list */
+    if (pcb2->next != NULL && pcb2->next == pcb) {
+      /* remove pcb from list */
+      pcb2->next = pcb->next;
+    }
+  }
+  memp_free(MEMP_UDP_PCB, pcb);
+}
+/**
+ * Create a UDP PCB.
+ *
+ * @return The UDP PCB which was created. NULL if the PCB data structure
+ * could not be allocated.
+ *
+ * @see udp_remove()
+ */
+struct udp_pcb *
+udp_new(void) {
+  struct udp_pcb *pcb;
+  pcb = memp_malloc(MEMP_UDP_PCB);
+  /* could allocate UDP PCB? */
+  if (pcb != NULL) {
+    /* initialize PCB to all zeroes */
+    memset(pcb, 0, sizeof(struct udp_pcb));
+    pcb->ttl = UDP_TTL;
+  }
+  
+  
+  return pcb;
+}
+
+#if UDP_DEBUG
+void
+udp_debug_print(struct udp_hdr *udphdr)
+{
+  LWIP_DEBUGF(UDP_DEBUG, ("UDP header:\n"));
+  LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(UDP_DEBUG, ("|     %5"U16_F"     |     %5"U16_F"     | (src port, dest port)\n",
+         ntohs(udphdr->src), ntohs(udphdr->dest)));
+  LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n"));
+  LWIP_DEBUGF(UDP_DEBUG, ("|     %5"U16_F"     |     0x%04"X16_F"    | (len, chksum)\n",
+         ntohs(udphdr->len), ntohs(udphdr->chksum)));
+  LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n"));
+}
+#endif /* UDP_DEBUG */
+
+#endif /* LWIP_UDP */
+
+
+
+
+
+
+
+
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv4/lwip/icmp.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv4/lwip/icmp.h
new file mode 100644
index 000000000..04307e743
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv4/lwip/icmp.h
@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_ICMP_H__
+#define __LWIP_ICMP_H__
+
+#include "lwip/arch.h"
+
+#include "lwip/opt.h"
+#include "lwip/pbuf.h"
+
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+
+#define ICMP_ER 0      /* echo reply */
+#define ICMP_DUR 3     /* destination unreachable */
+#define ICMP_SQ 4      /* source quench */
+#define ICMP_RD 5      /* redirect */
+#define ICMP_ECHO 8    /* echo */
+#define ICMP_TE 11     /* time exceeded */
+#define ICMP_PP 12     /* parameter problem */
+#define ICMP_TS 13     /* timestamp */
+#define ICMP_TSR 14    /* timestamp reply */
+#define ICMP_IRQ 15    /* information request */
+#define ICMP_IR 16     /* information reply */
+
+enum icmp_dur_type {
+  ICMP_DUR_NET = 0,    /* net unreachable */
+  ICMP_DUR_HOST = 1,   /* host unreachable */
+  ICMP_DUR_PROTO = 2,  /* protocol unreachable */
+  ICMP_DUR_PORT = 3,   /* port unreachable */
+  ICMP_DUR_FRAG = 4,   /* fragmentation needed and DF set */
+  ICMP_DUR_SR = 5      /* source route failed */
+};
+
+enum icmp_te_type {
+  ICMP_TE_TTL = 0,     /* time to live exceeded in transit */
+  ICMP_TE_FRAG = 1     /* fragment reassembly time exceeded */
+};
+
+void icmp_input(struct pbuf *p, struct netif *inp);
+
+void icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t);
+void icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t);
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct icmp_echo_hdr {
+  PACK_STRUCT_FIELD(u16_t _type_code);
+  PACK_STRUCT_FIELD(u16_t chksum);
+  PACK_STRUCT_FIELD(u16_t id);
+  PACK_STRUCT_FIELD(u16_t seqno);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+
+PACK_STRUCT_BEGIN
+struct icmp_dur_hdr {
+  PACK_STRUCT_FIELD(u16_t _type_code);
+  PACK_STRUCT_FIELD(u16_t chksum);
+  PACK_STRUCT_FIELD(u32_t unused);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+
+PACK_STRUCT_BEGIN
+struct icmp_te_hdr {
+  PACK_STRUCT_FIELD(u16_t _type_code);
+  PACK_STRUCT_FIELD(u16_t chksum);
+  PACK_STRUCT_FIELD(u32_t unused);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define ICMPH_TYPE(hdr) (ntohs((hdr)->_type_code) >> 8)
+#define ICMPH_CODE(hdr) (ntohs((hdr)->_type_code) & 0xff)
+
+#define ICMPH_TYPE_SET(hdr, type) ((hdr)->_type_code = htons(ICMPH_CODE(hdr) | ((type) << 8)))
+#define ICMPH_CODE_SET(hdr, code) ((hdr)->_type_code = htons((code) | (ICMPH_TYPE(hdr) << 8)))
+
+#endif /* __LWIP_ICMP_H__ */
+    
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv4/lwip/inet.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv4/lwip/inet.h
new file mode 100644
index 000000000..5428d54fd
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv4/lwip/inet.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_INET_H__
+#define __LWIP_INET_H__
+
+#include "lwip/arch.h"
+
+#include "lwip/opt.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+
+u16_t inet_chksum(void *dataptr, u16_t len);
+#if 0 /* optimized routine */
+u16_t inet_chksum4(u8_t *dataptr, u16_t len);
+#endif
+u16_t inet_chksum_pbuf(struct pbuf *p);
+u16_t inet_chksum_pseudo(struct pbuf *p,
+       struct ip_addr *src, struct ip_addr *dest,
+       u8_t proto, u16_t proto_len);
+
+u32_t inet_addr(const char *cp);
+s8_t inet_aton(const char *cp, struct in_addr *addr);
+char *inet_ntoa(struct in_addr addr); /* returns ptr to static buffer; not reentrant! */
+
+#ifdef htons
+#undef htons
+#endif /* htons */
+#ifdef htonl
+#undef htonl
+#endif /* htonl */
+#ifdef ntohs
+#undef ntohs
+#endif /* ntohs */
+#ifdef ntohl
+#undef ntohl
+#endif /* ntohl */
+
+#if BYTE_ORDER == BIG_ENDIAN
+#define htons(x) (x)
+#define ntohs(x) (x)
+#define htonl(x) (x)
+#define ntohl(x) (x)
+#else
+#ifdef LWIP_PREFIX_BYTEORDER_FUNCS
+/* workaround for naming collisions on some platforms */
+#define htons lwip_htons
+#define ntohs lwip_ntohs
+#define htonl lwip_htonl
+#define ntohl lwip_ntohl
+#endif
+u16_t htons(u16_t x);
+u16_t ntohs(u16_t x);
+u32_t htonl(u32_t x);
+u32_t ntohl(u32_t x);
+#endif
+
+#endif /* __LWIP_INET_H__ */
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv4/lwip/ip.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv4/lwip/ip.h
new file mode 100644
index 000000000..34ca7a8fc
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv4/lwip/ip.h
@@ -0,0 +1,154 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_IP_H__
+#define __LWIP_IP_H__
+
+#include "lwip/arch.h"
+
+#include "lwip/def.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+
+#include "lwip/err.h"
+
+
+void ip_init(void);
+struct netif *ip_route(struct ip_addr *dest);
+err_t ip_input(struct pbuf *p, struct netif *inp);
+err_t ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+		u8_t ttl, u8_t tos, u8_t proto);
+err_t ip_output_if(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+		   u8_t ttl, u8_t tos, u8_t proto,
+       struct netif *netif);
+
+#define IP_HLEN 20
+
+#define IP_PROTO_ICMP 1
+#define IP_PROTO_UDP 17
+#define IP_PROTO_UDPLITE 170
+#define IP_PROTO_TCP 6
+
+/* This is passed as the destination address to ip_output_if (not
+   to ip_output), meaning that an IP header already is constructed
+   in the pbuf. This is used when TCP retransmits. */
+#ifdef IP_HDRINCL
+#undef IP_HDRINCL
+#endif /* IP_HDRINCL */
+#define IP_HDRINCL  NULL
+
+
+/* This is the common part of all PCB types. It needs to be at the
+   beginning of a PCB type definition. It is located here so that
+   changes to this common part are made in one location instead of
+   having to change all PCB structs. */
+#define IP_PCB struct ip_addr local_ip; \
+  struct ip_addr remote_ip; \
+   /* Socket options */  \
+  u16_t so_options;      \
+   /* Type Of Service */ \
+  u8_t tos;              \
+  /* Time To Live */     \
+  u8_t ttl
+
+/*
+ * Option flags per-socket. These are the same like SO_XXX.
+ */
+#define	SOF_DEBUG	    (u16_t)0x0001U		/* turn on debugging info recording */
+#define	SOF_ACCEPTCONN	(u16_t)0x0002U		/* socket has had listen() */
+#define	SOF_REUSEADDR	(u16_t)0x0004U		/* allow local address reuse */
+#define	SOF_KEEPALIVE	(u16_t)0x0008U		/* keep connections alive */
+#define	SOF_DONTROUTE	(u16_t)0x0010U		/* just use interface addresses */
+#define	SOF_BROADCAST	(u16_t)0x0020U		/* permit sending of broadcast msgs */
+#define	SOF_USELOOPBACK	(u16_t)0x0040U		/* bypass hardware when possible */
+#define	SOF_LINGER	    (u16_t)0x0080U		/* linger on close if data present */
+#define	SOF_OOBINLINE	(u16_t)0x0100U		/* leave received OOB data in line */
+#define	SOF_REUSEPORT	(u16_t)0x0200U		/* allow local address & port reuse */
+
+
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip_hdr {
+  /* version / header length / type of service */
+  PACK_STRUCT_FIELD(u16_t _v_hl_tos);
+  /* total length */
+  PACK_STRUCT_FIELD(u16_t _len);
+  /* identification */
+  PACK_STRUCT_FIELD(u16_t _id);
+  /* fragment offset field */
+  PACK_STRUCT_FIELD(u16_t _offset);
+#define IP_RF 0x8000        /* reserved fragment flag */
+#define IP_DF 0x4000        /* dont fragment flag */
+#define IP_MF 0x2000        /* more fragments flag */
+#define IP_OFFMASK 0x1fff   /* mask for fragmenting bits */
+  /* time to live / protocol*/
+  PACK_STRUCT_FIELD(u16_t _ttl_proto);
+  /* checksum */
+  PACK_STRUCT_FIELD(u16_t _chksum);
+  /* source and destination IP addresses */
+  PACK_STRUCT_FIELD(struct ip_addr src);
+  PACK_STRUCT_FIELD(struct ip_addr dest); 
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define IPH_V(hdr)  (ntohs((hdr)->_v_hl_tos) >> 12)
+#define IPH_HL(hdr) ((ntohs((hdr)->_v_hl_tos) >> 8) & 0x0f)
+#define IPH_TOS(hdr) (ntohs((hdr)->_v_hl_tos) & 0xff)
+#define IPH_LEN(hdr) ((hdr)->_len)
+#define IPH_ID(hdr) ((hdr)->_id)
+#define IPH_OFFSET(hdr) ((hdr)->_offset)
+#define IPH_TTL(hdr) (ntohs((hdr)->_ttl_proto) >> 8)
+#define IPH_PROTO(hdr) (ntohs((hdr)->_ttl_proto) & 0xff)
+#define IPH_CHKSUM(hdr) ((hdr)->_chksum)
+
+#define IPH_VHLTOS_SET(hdr, v, hl, tos) (hdr)->_v_hl_tos = (htons(((v) << 12) | ((hl) << 8) | (tos)))
+#define IPH_LEN_SET(hdr, len) (hdr)->_len = (len)
+#define IPH_ID_SET(hdr, id) (hdr)->_id = (id)
+#define IPH_OFFSET_SET(hdr, off) (hdr)->_offset = (off)
+#define IPH_TTL_SET(hdr, ttl) (hdr)->_ttl_proto = (htons(IPH_PROTO(hdr) | ((ttl) << 8)))
+#define IPH_PROTO_SET(hdr, proto) (hdr)->_ttl_proto = (htons((proto) | (IPH_TTL(hdr) << 8)))
+#define IPH_CHKSUM_SET(hdr, chksum) (hdr)->_chksum = (chksum)
+
+#if IP_DEBUG
+void ip_debug_print(struct pbuf *p);
+#else
+#define ip_debug_print(p)
+#endif /* IP_DEBUG */
+
+#endif /* __LWIP_IP_H__ */
+
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv4/lwip/ip_addr.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv4/lwip/ip_addr.h
new file mode 100644
index 000000000..78aba8033
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv4/lwip/ip_addr.h
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_IP_ADDR_H__
+#define __LWIP_IP_ADDR_H__
+
+#include "lwip/arch.h"
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip_addr {
+  PACK_STRUCT_FIELD(u32_t addr);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ip_addr2 {
+  PACK_STRUCT_FIELD(u16_t addrw[2]);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/* For compatibility with BSD code */
+struct in_addr {
+  u32_t s_addr;
+};
+
+struct netif;
+
+extern const struct ip_addr ip_addr_any;
+extern const struct ip_addr ip_addr_broadcast;
+
+/** IP_ADDR_ can be used as a fixed IP address
+ *  for the wildcard and the broadcast address
+ */
+#define IP_ADDR_ANY ((struct ip_addr *)&ip_addr_any)
+#define IP_ADDR_BROADCAST ((struct ip_addr *)&ip_addr_broadcast)
+
+#define INADDR_NONE    ((u32_t) 0xffffffff)  /* 255.255.255.255 */
+#define INADDR_LOOPBACK    ((u32_t) 0x7f000001)  /* 127.0.0.1 */
+
+/* Definitions of the bits in an Internet address integer.
+
+   On subnets, host and network parts are found according to
+   the subnet mask, not these masks.  */
+
+#define  IN_CLASSA(a)    ((((u32_t)(a)) & 0x80000000) == 0)
+#define  IN_CLASSA_NET    0xff000000
+#define  IN_CLASSA_NSHIFT  24
+#define  IN_CLASSA_HOST    (0xffffffff & ~IN_CLASSA_NET)
+#define  IN_CLASSA_MAX    128
+
+#define  IN_CLASSB(a)    ((((u32_t)(a)) & 0xc0000000) == 0x80000000)
+#define  IN_CLASSB_NET    0xffff0000
+#define  IN_CLASSB_NSHIFT  16
+#define  IN_CLASSB_HOST    (0xffffffff & ~IN_CLASSB_NET)
+#define  IN_CLASSB_MAX    65536
+
+#define  IN_CLASSC(a)    ((((u32_t)(a)) & 0xe0000000) == 0xc0000000)
+#define  IN_CLASSC_NET    0xffffff00
+#define  IN_CLASSC_NSHIFT  8
+#define  IN_CLASSC_HOST    (0xffffffff & ~IN_CLASSC_NET)
+
+#define IN_CLASSD(a)        (((u32_t)(a) & 0xf0000000) == 0xe0000000)
+#define IN_CLASSD_NET       0xf0000000  /* These ones aren't really */
+#define IN_CLASSD_NSHIFT    28      /* net and host fields, but */
+#define IN_CLASSD_HOST      0x0fffffff  /* routing needn't know.    */
+#define IN_MULTICAST(a)     IN_CLASSD(a)
+
+#define IN_EXPERIMENTAL(a)  (((u32_t)(a) & 0xf0000000) == 0xf0000000)
+#define IN_BADCLASS(a)      (((u32_t)(a) & 0xf0000000) == 0xf0000000)
+
+#define IN_LOOPBACKNET      127         /* official! */
+
+
+#define IP4_ADDR(ipaddr, a,b,c,d) (ipaddr)->addr = htonl(((u32_t)(a & 0xff) << 24) | ((u32_t)(b & 0xff) << 16) | \
+                                                         ((u32_t)(c & 0xff) << 8) | (u32_t)(d & 0xff))
+
+#define ip_addr_set(dest, src) (dest)->addr = \
+                               ((src) == NULL? 0:\
+                               (src)->addr)
+/**
+ * Determine if two address are on the same network.
+ *
+ * @arg addr1 IP address 1
+ * @arg addr2 IP address 2
+ * @arg mask network identifier mask
+ * @return !0 if the network identifiers of both address match
+ */
+#define ip_addr_netcmp(addr1, addr2, mask) (((addr1)->addr & \
+                                              (mask)->addr) == \
+                                             ((addr2)->addr & \
+                                              (mask)->addr))
+#define ip_addr_cmp(addr1, addr2) ((addr1)->addr == (addr2)->addr)
+
+#define ip_addr_isany(addr1) ((addr1) == NULL || (addr1)->addr == 0)
+
+u8_t ip_addr_isbroadcast(struct ip_addr *, struct netif *);
+
+#define ip_addr_ismulticast(addr1) (((addr1)->addr & ntohl(0xf0000000)) == ntohl(0xe0000000))
+
+
+#define ip_addr_debug_print(debug, ipaddr) LWIP_DEBUGF(debug, ("%"U16_F".%"U16_F".%"U16_F".%"U16_F, \
+        ipaddr?(u16_t)(ntohl((ipaddr)->addr) >> 24) & 0xff:0, \
+        ipaddr?(u16_t)(ntohl((ipaddr)->addr) >> 16) & 0xff:0, \
+        ipaddr?(u16_t)(ntohl((ipaddr)->addr) >> 8) & 0xff:0, \
+        ipaddr?(u16_t)ntohl((ipaddr)->addr) & 0xff:0U))
+
+/* cast to unsigned int, as it is used as argument to printf functions
+ * which expect integer arguments. CSi: use cc.h formatters (conversion chars)! */
+#define ip4_addr1(ipaddr) ((u16_t)(ntohl((ipaddr)->addr) >> 24) & 0xff)
+#define ip4_addr2(ipaddr) ((u16_t)(ntohl((ipaddr)->addr) >> 16) & 0xff)
+#define ip4_addr3(ipaddr) ((u16_t)(ntohl((ipaddr)->addr) >> 8) & 0xff)
+#define ip4_addr4(ipaddr) ((u16_t)(ntohl((ipaddr)->addr)) & 0xff)
+#endif /* __LWIP_IP_ADDR_H__ */
+
+
+
+
+
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv4/lwip/ip_frag.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv4/lwip/ip_frag.h
new file mode 100644
index 000000000..9b88b6948
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv4/lwip/ip_frag.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Jani Monoses 
+ *
+ */
+
+#ifndef __LWIP_IP_FRAG_H__
+#define __LWIP_IP_FRAG_H__
+
+#include "lwip/err.h"
+#include "lwip/pbuf.h"
+#include "lwip/netif.h"
+#include "lwip/ip_addr.h"
+
+void ip_reass_tmr(void);
+struct pbuf * ip_reass(struct pbuf *p);
+err_t ip_frag(struct pbuf *p, struct netif *netif, struct ip_addr *dest);
+
+#endif /* __LWIP_IP_FRAG_H__ */
+
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv6/lwip/icmp.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv6/lwip/icmp.h
new file mode 100644
index 000000000..9c63a3f45
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv6/lwip/icmp.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_ICMP_H__
+#define __LWIP_ICMP_H__
+
+#include "lwip/arch.h"
+
+#include "lwip/opt.h"
+#include "lwip/pbuf.h"
+
+#include "lwip/netif.h"
+
+#define ICMP6_DUR  1
+#define ICMP6_TE   3
+#define ICMP6_ECHO 128    /* echo */
+#define ICMP6_ER   129      /* echo reply */
+
+
+enum icmp_dur_type {
+  ICMP_DUR_NET = 0,    /* net unreachable */
+  ICMP_DUR_HOST = 1,   /* host unreachable */
+  ICMP_DUR_PROTO = 2,  /* protocol unreachable */
+  ICMP_DUR_PORT = 3,   /* port unreachable */
+  ICMP_DUR_FRAG = 4,   /* fragmentation needed and DF set */
+  ICMP_DUR_SR = 5      /* source route failed */
+};
+
+enum icmp_te_type {
+  ICMP_TE_TTL = 0,     /* time to live exceeded in transit */
+  ICMP_TE_FRAG = 1     /* fragment reassembly time exceeded */
+};
+
+void icmp_input(struct pbuf *p, struct netif *inp);
+
+void icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t);
+void icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t);
+
+struct icmp_echo_hdr {
+  u8_t type;
+  u8_t icode;
+  u16_t chksum;
+  u16_t id;
+  u16_t seqno;
+};
+
+struct icmp_dur_hdr {
+  u8_t type;
+  u8_t icode;
+  u16_t chksum;
+  u32_t unused;
+};
+
+struct icmp_te_hdr {
+  u8_t type;
+  u8_t icode;
+  u16_t chksum;
+  u32_t unused;
+};
+
+#endif /* __LWIP_ICMP_H__ */
+    
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv6/lwip/inet.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv6/lwip/inet.h
new file mode 100644
index 000000000..c9d07d7fd
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv6/lwip/inet.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_INET_H__
+#define __LWIP_INET_H__
+
+#include "lwip/arch.h"
+
+#include "lwip/opt.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+
+u16_t inet_chksum(void *data, u16_t len);
+u16_t inet_chksum_pbuf(struct pbuf *p);
+u16_t inet_chksum_pseudo(struct pbuf *p,
+       struct ip_addr *src, struct ip_addr *dest,
+       u8_t proto, u32_t proto_len);
+
+u32_t inet_addr(const char *cp);
+s8_t inet_aton(const char *cp, struct in_addr *addr);
+
+#ifndef _MACHINE_ENDIAN_H_
+#ifndef _NETINET_IN_H
+#ifndef _LINUX_BYTEORDER_GENERIC_H
+u16_t htons(u16_t n);
+u16_t ntohs(u16_t n);
+u32_t htonl(u32_t n);
+u32_t ntohl(u32_t n);
+#endif /* _LINUX_BYTEORDER_GENERIC_H */
+#endif /* _NETINET_IN_H */
+#endif /* _MACHINE_ENDIAN_H_ */
+
+#endif /* __LWIP_INET_H__ */
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv6/lwip/ip.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv6/lwip/ip.h
new file mode 100644
index 000000000..f316ce50a
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv6/lwip/ip.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_IP_H__
+#define __LWIP_IP_H__
+
+#include "lwip/opt.h"
+#include "lwip/def.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+
+#include "lwip/err.h"
+
+#define IP_HLEN 40
+
+#define IP_PROTO_ICMP 58
+#define IP_PROTO_UDP 17
+#define IP_PROTO_UDPLITE 170
+#define IP_PROTO_TCP 6
+
+/* This is passed as the destination address to ip_output_if (not
+   to ip_output), meaning that an IP header already is constructed
+   in the pbuf. This is used when TCP retransmits. */
+#ifdef IP_HDRINCL
+#undef IP_HDRINCL
+#endif /* IP_HDRINCL */
+#define IP_HDRINCL  NULL
+
+
+/* The IPv6 header. */
+struct ip_hdr {
+#if BYTE_ORDER == LITTLE_ENDIAN
+  u8_t tclass1:4, v:4;
+  u8_t flow1:4, tclass2:4;  
+#else
+  u8_t v:4, tclass1:4;
+  u8_t tclass2:8, flow1:4;
+#endif
+  u16_t flow2;
+  u16_t len;                /* payload length */
+  u8_t nexthdr;             /* next header */
+  u8_t hoplim;              /* hop limit (TTL) */
+  struct ip_addr src, dest;          /* source and destination IP addresses */
+};
+
+void ip_init(void);
+
+#include "lwip/netif.h"
+
+struct netif *ip_route(struct ip_addr *dest);
+
+void ip_input(struct pbuf *p, struct netif *inp);
+
+/* source and destination addresses in network byte order, please */
+err_t ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+         u8_t ttl, u8_t proto);
+
+err_t ip_output_if(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
+      u8_t ttl, u8_t proto,
+      struct netif *netif);
+
+#if IP_DEBUG
+void ip_debug_print(struct pbuf *p);
+#endif /* IP_DEBUG */
+
+#endif /* __LWIP_IP_H__ */
+
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv6/lwip/ip_addr.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv6/lwip/ip_addr.h
new file mode 100644
index 000000000..16fa569fa
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv6/lwip/ip_addr.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_IP_ADDR_H__
+#define __LWIP_IP_ADDR_H__
+
+#include "lwip/arch.h"
+
+#define IP_ADDR_ANY 0
+
+struct ip_addr {
+  u32_t addr[4];
+};
+
+#define IP6_ADDR(ipaddr, a,b,c,d,e,f,g,h) do { (ipaddr)->addr[0] = htonl((u32_t)((a & 0xffff) << 16) | (b & 0xffff)); \
+                                               (ipaddr)->addr[1] = htonl(((c & 0xffff) << 16) | (d & 0xffff)); \
+                                               (ipaddr)->addr[2] = htonl(((e & 0xffff) << 16) | (f & 0xffff)); \
+                                               (ipaddr)->addr[3] = htonl(((g & 0xffff) << 16) | (h & 0xffff)); } while(0)
+
+u8_t ip_addr_netcmp(struct ip_addr *addr1, struct ip_addr *addr2,
+        struct ip_addr *mask);
+u8_t ip_addr_cmp(struct ip_addr *addr1, struct ip_addr *addr2);
+void ip_addr_set(struct ip_addr *dest, struct ip_addr *src);
+u8_t ip_addr_isany(struct ip_addr *addr);
+
+
+#if IP_DEBUG
+void ip_addr_debug_print(struct ip_addr *addr);
+#endif /* IP_DEBUG */
+
+#endif /* __LWIP_IP_ADDR_H__ */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/api.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/api.h
new file mode 100644
index 000000000..1059eca2e
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/api.h
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_API_H__
+#define __LWIP_API_H__
+
+#include "lwip/opt.h"
+#include "lwip/pbuf.h"
+#include "lwip/sys.h"
+
+#include "lwip/ip.h"
+
+#include "lwip/raw.h"
+#include "lwip/udp.h"
+#include "lwip/tcp.h"
+
+#include "lwip/err.h"
+
+#define NETCONN_NOCOPY 0x00
+#define NETCONN_COPY   0x01
+
+enum netconn_type {
+  NETCONN_TCP,
+  NETCONN_UDP,
+  NETCONN_UDPLITE,
+  NETCONN_UDPNOCHKSUM,
+  NETCONN_RAW
+};
+
+enum netconn_state {
+  NETCONN_NONE,
+  NETCONN_WRITE,
+  NETCONN_ACCEPT,
+  NETCONN_RECV,
+  NETCONN_CONNECT,
+  NETCONN_CLOSE
+};
+
+enum netconn_evt {
+  NETCONN_EVT_RCVPLUS,
+  NETCONN_EVT_RCVMINUS,
+  NETCONN_EVT_SENDPLUS,
+  NETCONN_EVT_SENDMINUS
+};
+
+struct netbuf {
+  struct pbuf *p, *ptr;
+  struct ip_addr *fromaddr;
+  u16_t fromport;
+  err_t err;
+};
+
+struct netconn {
+  enum netconn_type type;
+  enum netconn_state state;
+  union {
+    struct tcp_pcb *tcp;
+    struct udp_pcb *udp;
+    struct raw_pcb *raw;
+  } pcb;
+  err_t err;
+  sys_mbox_t mbox;
+  sys_mbox_t recvmbox;
+  sys_mbox_t acceptmbox;
+  sys_sem_t sem;
+  int socket;
+  u16_t recv_avail;
+  void (* callback)(struct netconn *, enum netconn_evt, u16_t len);
+};
+
+/* Network buffer functions: */
+struct netbuf *   netbuf_new      (void);
+void              netbuf_delete   (struct netbuf *buf);
+void *            netbuf_alloc    (struct netbuf *buf, u16_t size);
+void              netbuf_free     (struct netbuf *buf);
+void              netbuf_ref      (struct netbuf *buf,
+           void *dataptr, u16_t size);
+void              netbuf_chain    (struct netbuf *head,
+           struct netbuf *tail);
+
+u16_t             netbuf_len      (struct netbuf *buf);
+err_t             netbuf_data     (struct netbuf *buf,
+           void **dataptr, u16_t *len);
+s8_t              netbuf_next     (struct netbuf *buf);
+void              netbuf_first    (struct netbuf *buf);
+
+void              netbuf_copy     (struct netbuf *buf,
+           void *dataptr, u16_t len);
+void              netbuf_copy_partial(struct netbuf *buf, void *dataptr, 
+              u16_t len, u16_t offset);
+struct ip_addr *  netbuf_fromaddr (struct netbuf *buf);
+u16_t             netbuf_fromport (struct netbuf *buf);
+
+/* Network connection functions: */
+struct netconn *  netconn_new     (enum netconn_type type);
+struct
+netconn *netconn_new_with_callback(enum netconn_type t,
+                                   void (*callback)(struct netconn *, enum netconn_evt, u16_t len));
+struct
+netconn *netconn_new_with_proto_and_callback(enum netconn_type t, u16_t proto,
+                                   void (*callback)(struct netconn *, enum netconn_evt, u16_t len));
+err_t             netconn_delete  (struct netconn *conn);
+enum netconn_type netconn_type    (struct netconn *conn);
+err_t             netconn_peer    (struct netconn *conn,
+           struct ip_addr *addr,
+           u16_t *port);
+err_t             netconn_addr    (struct netconn *conn,
+           struct ip_addr **addr,
+           u16_t *port);
+err_t             netconn_bind    (struct netconn *conn,
+           struct ip_addr *addr,
+           u16_t port);
+err_t             netconn_connect (struct netconn *conn,
+           struct ip_addr *addr,
+           u16_t port);
+err_t             netconn_disconnect (struct netconn *conn);
+err_t             netconn_listen  (struct netconn *conn);
+struct netconn *  netconn_accept  (struct netconn *conn);
+struct netbuf *   netconn_recv    (struct netconn *conn);
+err_t             netconn_send    (struct netconn *conn,
+           struct netbuf *buf);
+err_t             netconn_write   (struct netconn *conn,
+           void *dataptr, u16_t size,
+           u8_t copy);
+err_t             netconn_close   (struct netconn *conn);
+
+err_t             netconn_err     (struct netconn *conn);
+
+#endif /* __LWIP_API_H__ */
+
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/api_msg.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/api_msg.h
new file mode 100644
index 000000000..87f3db5f1
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/api_msg.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_API_MSG_H__
+#define __LWIP_API_MSG_H__
+
+#include "lwip/opt.h"
+#include "lwip/pbuf.h"
+#include "lwip/sys.h"
+
+#include "lwip/ip.h"
+
+#include "lwip/udp.h"
+#include "lwip/tcp.h"
+
+#include "lwip/api.h"
+
+enum api_msg_type {
+  API_MSG_NEWCONN,
+  API_MSG_DELCONN,
+  
+  API_MSG_BIND,
+  API_MSG_CONNECT,
+  API_MSG_DISCONNECT,
+
+  API_MSG_LISTEN,
+  API_MSG_ACCEPT,
+
+  API_MSG_SEND,
+  API_MSG_RECV,
+  API_MSG_WRITE,
+
+  API_MSG_CLOSE,
+  
+  API_MSG_MAX
+};
+
+struct api_msg_msg {
+  struct netconn *conn;
+  enum netconn_type conntype;
+  union {
+    struct pbuf *p;   
+    struct  {
+      struct ip_addr *ipaddr;
+      u16_t port;
+    } bc;
+    struct {
+      void *dataptr;
+      u16_t len;
+      u8_t copy;
+    } w;    
+    sys_mbox_t mbox;
+    u16_t len;
+  } msg;
+};
+
+struct api_msg {
+  enum api_msg_type type;
+  struct api_msg_msg msg;
+};
+
+void api_msg_input(struct api_msg *msg);
+void api_msg_post(struct api_msg *msg);
+
+#endif /* __LWIP_API_MSG_H__ */
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/arch.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/arch.h
new file mode 100644
index 000000000..f5e10513f
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/arch.h
@@ -0,0 +1,216 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_ARCH_H__
+#define __LWIP_ARCH_H__
+
+#ifndef LITTLE_ENDIAN
+#define LITTLE_ENDIAN 1234
+#endif
+
+#ifndef BIG_ENDIAN
+#define BIG_ENDIAN 4321
+#endif
+
+#include "arch/cc.h"
+
+#ifndef PACK_STRUCT_BEGIN
+#define PACK_STRUCT_BEGIN
+#endif /* PACK_STRUCT_BEGIN */
+
+#ifndef PACK_STRUCT_END
+#define PACK_STRUCT_END
+#endif /* PACK_STRUCT_END */
+
+#ifndef PACK_STRUCT_FIELD
+#define PACK_STRUCT_FIELD(x) x
+#endif /* PACK_STRUCT_FIELD */
+
+
+
+#ifdef LWIP_PROVIDE_ERRNO
+
+#define  EPERM     1  /* Operation not permitted */
+#define  ENOENT     2  /* No such file or directory */
+#define  ESRCH     3  /* No such process */
+#define  EINTR     4  /* Interrupted system call */
+#define  EIO     5  /* I/O error */
+#define  ENXIO     6  /* No such device or address */
+#define  E2BIG     7  /* Arg list too long */
+#define  ENOEXEC     8  /* Exec format error */
+#define  EBADF     9  /* Bad file number */
+#define  ECHILD    10  /* No child processes */
+#define  EAGAIN    11  /* Try again */
+#define  ENOMEM    12  /* Out of memory */
+#define  EACCES    13  /* Permission denied */
+#define  EFAULT    14  /* Bad address */
+#define  ENOTBLK    15  /* Block device required */
+#define  EBUSY    16  /* Device or resource busy */
+#define  EEXIST    17  /* File exists */
+#define  EXDEV    18  /* Cross-device link */
+#define  ENODEV    19  /* No such device */
+#define  ENOTDIR    20  /* Not a directory */
+#define  EISDIR    21  /* Is a directory */
+#define  EINVAL    22  /* Invalid argument */
+#define  ENFILE    23  /* File table overflow */
+#define  EMFILE    24  /* Too many open files */
+#define  ENOTTY    25  /* Not a typewriter */
+#define  ETXTBSY    26  /* Text file busy */
+#define  EFBIG    27  /* File too large */
+#define  ENOSPC    28  /* No space left on device */
+#define  ESPIPE    29  /* Illegal seek */
+#define  EROFS    30  /* Read-only file system */
+#define  EMLINK    31  /* Too many links */
+#define  EPIPE    32  /* Broken pipe */
+#define  EDOM    33  /* Math argument out of domain of func */
+#define  ERANGE    34  /* Math result not representable */
+#define  EDEADLK    35  /* Resource deadlock would occur */
+#define  ENAMETOOLONG  36  /* File name too long */
+#define  ENOLCK    37  /* No record locks available */
+#define  ENOSYS    38  /* Function not implemented */
+#define  ENOTEMPTY  39  /* Directory not empty */
+#define  ELOOP    40  /* Too many symbolic links encountered */
+#define  EWOULDBLOCK  EAGAIN  /* Operation would block */
+#define  ENOMSG    42  /* No message of desired type */
+#define  EIDRM    43  /* Identifier removed */
+#define  ECHRNG    44  /* Channel number out of range */
+#define  EL2NSYNC  45  /* Level 2 not synchronized */
+#define  EL3HLT    46  /* Level 3 halted */
+#define  EL3RST    47  /* Level 3 reset */
+#define  ELNRNG    48  /* Link number out of range */
+#define  EUNATCH    49  /* Protocol driver not attached */
+#define  ENOCSI    50  /* No CSI structure available */
+#define  EL2HLT    51  /* Level 2 halted */
+#define  EBADE    52  /* Invalid exchange */
+#define  EBADR    53  /* Invalid request descriptor */
+#define  EXFULL    54  /* Exchange full */
+#define  ENOANO    55  /* No anode */
+#define  EBADRQC    56  /* Invalid request code */
+#define  EBADSLT    57  /* Invalid slot */
+
+#define  EDEADLOCK  EDEADLK
+
+#define  EBFONT    59  /* Bad font file format */
+#define  ENOSTR    60  /* Device not a stream */
+#define  ENODATA    61  /* No data available */
+#define  ETIME    62  /* Timer expired */
+#define  ENOSR    63  /* Out of streams resources */
+#define  ENONET    64  /* Machine is not on the network */
+#define  ENOPKG    65  /* Package not installed */
+#define  EREMOTE    66  /* Object is remote */
+#define  ENOLINK    67  /* Link has been severed */
+#define  EADV    68  /* Advertise error */
+#define  ESRMNT    69  /* Srmount error */
+#define  ECOMM    70  /* Communication error on send */
+#define  EPROTO    71  /* Protocol error */
+#define  EMULTIHOP  72  /* Multihop attempted */
+#define  EDOTDOT    73  /* RFS specific error */
+#define  EBADMSG    74  /* Not a data message */
+#define  EOVERFLOW  75  /* Value too large for defined data type */
+#define  ENOTUNIQ  76  /* Name not unique on network */
+#define  EBADFD    77  /* File descriptor in bad state */
+#define  EREMCHG    78  /* Remote address changed */
+#define  ELIBACC    79  /* Can not access a needed shared library */
+#define  ELIBBAD    80  /* Accessing a corrupted shared library */
+#define  ELIBSCN    81  /* .lib section in a.out corrupted */
+#define  ELIBMAX    82  /* Attempting to link in too many shared libraries */
+#define  ELIBEXEC  83  /* Cannot exec a shared library directly */
+#define  EILSEQ    84  /* Illegal byte sequence */
+#define  ERESTART  85  /* Interrupted system call should be restarted */
+#define  ESTRPIPE  86  /* Streams pipe error */
+#define  EUSERS    87  /* Too many users */
+#define  ENOTSOCK  88  /* Socket operation on non-socket */
+#define  EDESTADDRREQ  89  /* Destination address required */
+#define  EMSGSIZE  90  /* Message too long */
+#define  EPROTOTYPE  91  /* Protocol wrong type for socket */
+#define  ENOPROTOOPT  92  /* Protocol not available */
+#define  EPROTONOSUPPORT  93  /* Protocol not supported */
+#define  ESOCKTNOSUPPORT  94  /* Socket type not supported */
+#define  EOPNOTSUPP  95  /* Operation not supported on transport endpoint */
+#define  EPFNOSUPPORT  96  /* Protocol family not supported */
+#define  EAFNOSUPPORT  97  /* Address family not supported by protocol */
+#define  EADDRINUSE  98  /* Address already in use */
+#define  EADDRNOTAVAIL  99  /* Cannot assign requested address */
+#define  ENETDOWN  100  /* Network is down */
+#define  ENETUNREACH  101  /* Network is unreachable */
+#define  ENETRESET  102  /* Network dropped connection because of reset */
+#define  ECONNABORTED  103  /* Software caused connection abort */
+#define  ECONNRESET  104  /* Connection reset by peer */
+#define  ENOBUFS    105  /* No buffer space available */
+#define  EISCONN    106  /* Transport endpoint is already connected */
+#define  ENOTCONN  107  /* Transport endpoint is not connected */
+#define  ESHUTDOWN  108  /* Cannot send after transport endpoint shutdown */
+#define  ETOOMANYREFS  109  /* Too many references: cannot splice */
+#define  ETIMEDOUT  110  /* Connection timed out */
+#define  ECONNREFUSED  111  /* Connection refused */
+#define  EHOSTDOWN  112  /* Host is down */
+#define  EHOSTUNREACH  113  /* No route to host */
+#define  EALREADY  114  /* Operation already in progress */
+#define  EINPROGRESS  115  /* Operation now in progress */
+#define  ESTALE    116  /* Stale NFS file handle */
+#define  EUCLEAN    117  /* Structure needs cleaning */
+#define  ENOTNAM    118  /* Not a XENIX named type file */
+#define  ENAVAIL    119  /* No XENIX semaphores available */
+#define  EISNAM    120  /* Is a named type file */
+#define  EREMOTEIO  121  /* Remote I/O error */
+#define  EDQUOT    122  /* Quota exceeded */
+
+#define  ENOMEDIUM  123  /* No medium found */
+#define  EMEDIUMTYPE  124  /* Wrong medium type */
+
+
+#define	ENSROK		0	/* DNS server returned answer with no data */
+#define	ENSRNODATA	160	/* DNS server returned answer with no data */
+#define	ENSRFORMERR	161	/* DNS server claims query was misformatted */
+#define	ENSRSERVFAIL 162	/* DNS server returned general failure */
+#define	ENSRNOTFOUND 163	/* Domain name not found */
+#define	ENSRNOTIMP	164	/* DNS server does not implement requested operation */
+#define	ENSRREFUSED	165	/* DNS server refused query */
+#define	ENSRBADQUERY 166	/* Misformatted DNS query */
+#define	ENSRBADNAME	167	/* Misformatted domain name */
+#define	ENSRBADFAMILY 168	/* Unsupported address family */
+#define	ENSRBADRESP	169	/* Misformatted DNS reply */
+#define	ENSRCONNREFUSED	170	/* Could not contact DNS servers */
+#define	ENSRTIMEOUT	171	/* Timeout while contacting DNS servers */
+#define	ENSROF		172	/* End of file */
+#define	ENSRFILE	173	/* Error reading file */
+#define	ENSRNOMEM	174	/* Out of memory */
+#define	ENSRDESTRUCTION	175	/* Application terminated lookup */
+#define	ENSRQUERYDOMAINTOOLONG	176	/* Domain name is too long */
+#define	ENSRCNAMELOOP	177	/* Domain name is too long */
+
+#ifndef errno
+extern int errno;
+#endif
+
+#endif /* LWIP_PROVIDE_ERRNO */
+
+#endif /* __LWIP_ARCH_H__ */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/debug.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/debug.h
new file mode 100644
index 000000000..3649cbd6c
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/debug.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_DEBUG_H__
+#define __LWIP_DEBUG_H__
+
+#include "arch/cc.h"
+
+/** lower two bits indicate debug level
+ * - 0 off
+ * - 1 warning
+ * - 2 serious
+ * - 3 severe
+ */
+
+#define DBG_LEVEL_OFF     0
+#define DBG_LEVEL_WARNING 1  /* bad checksums, dropped packets, ... */
+#define DBG_LEVEL_SERIOUS 2  /* memory allocation failures, ... */
+#define DBG_LEVEL_SEVERE  3  /* */ 
+#define DBG_MASK_LEVEL    3
+
+/** flag for LWIP_DEBUGF to enable that debug message */
+#define DBG_ON  0x80U
+/** flag for LWIP_DEBUGF to disable that debug message */
+#define DBG_OFF 0x00U
+
+/** flag for LWIP_DEBUGF indicating a tracing message (to follow program flow) */
+#define DBG_TRACE   0x40U
+/** flag for LWIP_DEBUGF indicating a state debug message (to follow module states) */
+#define DBG_STATE   0x20U
+/** flag for LWIP_DEBUGF indicating newly added code, not thoroughly tested yet */
+#define DBG_FRESH   0x10U
+/** flag for LWIP_DEBUGF to halt after printing this debug message */
+#define DBG_HALT    0x08U
+
+#ifndef LWIP_NOASSERT
+#  define LWIP_ASSERT(x,y) do { if(!(y)) LWIP_PLATFORM_ASSERT(x); } while(0)
+#else
+#  define LWIP_ASSERT(x,y) 
+#endif
+
+#ifdef LWIP_DEBUG
+/** print debug message only if debug message type is enabled...
+ *  AND is of correct type AND is at least DBG_LEVEL
+ */
+#  define LWIP_DEBUGF(debug,x) do { if (((debug) & DBG_ON) && ((debug) & DBG_TYPES_ON) && ((s16_t)((debug) & DBG_MASK_LEVEL) >= DBG_MIN_LEVEL)) { LWIP_PLATFORM_DIAG(x); if ((debug) & DBG_HALT) while(1); } } while(0)
+#  define LWIP_ERROR(x)   do { LWIP_PLATFORM_DIAG(x); } while(0)  
+#else /* LWIP_DEBUG */
+#  define LWIP_DEBUGF(debug,x) 
+#  define LWIP_ERROR(x)  
+#endif /* LWIP_DEBUG */
+
+#endif /* __LWIP_DEBUG_H__ */
+
+
+
+
+
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/def.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/def.h
new file mode 100644
index 000000000..f26bdd040
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/def.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_DEF_H__
+#define __LWIP_DEF_H__
+
+/* this might define NULL already */
+#include "arch/cc.h"
+
+#define LWIP_MAX(x , y)  (x) > (y) ? (x) : (y)
+#define LWIP_MIN(x , y)  (x) < (y) ? (x) : (y)
+
+#ifndef NULL
+#define NULL ((void *)0)
+#endif
+
+
+#endif /* __LWIP_DEF_H__ */
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/dhcp.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/dhcp.h
new file mode 100644
index 000000000..df51bdc96
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/dhcp.h
@@ -0,0 +1,223 @@
+/** @file
+ */
+
+#ifndef __LWIP_DHCP_H__
+#define __LWIP_DHCP_H__
+
+#include "lwip/opt.h"
+#include "lwip/netif.h"
+#include "lwip/udp.h"
+
+/** period (in seconds) of the application calling dhcp_coarse_tmr() */
+#define DHCP_COARSE_TIMER_SECS 60 
+/** period (in milliseconds) of the application calling dhcp_fine_tmr() */
+#define DHCP_FINE_TIMER_MSECS 500 
+
+struct dhcp
+{
+  /** current DHCP state machine state */
+  u8_t state;
+  /** retries of current request */
+  u8_t tries;
+  /** transaction identifier of last sent request */ 
+  u32_t xid;
+  /** our connection to the DHCP server */ 
+  struct udp_pcb *pcb;
+  /** (first) pbuf of incoming msg */
+  struct pbuf *p;
+  /** incoming msg */
+  struct dhcp_msg *msg_in;
+  /** incoming msg options */
+  struct dhcp_msg *options_in; 
+  /** ingoing msg options length */
+  u16_t options_in_len;
+
+  struct pbuf *p_out; /* pbuf of outcoming msg */
+  struct dhcp_msg *msg_out; /* outgoing msg */
+  u16_t options_out_len; /* outgoing msg options length */
+  u16_t request_timeout; /* #ticks with period DHCP_FINE_TIMER_SECS for request timeout */
+  u16_t t1_timeout;  /* #ticks with period DHCP_COARSE_TIMER_SECS for renewal time */
+  u16_t t2_timeout;  /* #ticks with period DHCP_COARSE_TIMER_SECS for rebind time */
+  struct ip_addr server_ip_addr; /* dhcp server address that offered this lease */
+  struct ip_addr offered_ip_addr;
+  struct ip_addr offered_sn_mask;
+  struct ip_addr offered_gw_addr;
+  struct ip_addr offered_bc_addr;
+#define DHCP_MAX_DNS 2
+  u32_t dns_count; /* actual number of DNS servers obtained */
+  struct ip_addr offered_dns_addr[DHCP_MAX_DNS]; /* DNS server addresses */
+ 
+  u32_t offered_t0_lease; /* lease period (in seconds) */
+  u32_t offered_t1_renew; /* recommended renew time (usually 50% of lease period) */
+  u32_t offered_t2_rebind; /* recommended rebind time (usually 66% of lease period)  */
+/** Patch #1308
+ *  TODO: See dhcp.c "TODO"s
+ */
+#if 0
+  struct ip_addr offered_si_addr;
+  u8_t *boot_file_name;
+#endif
+};
+
+/* MUST be compiled with "pack structs" or equivalent! */
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+/** minimum set of fields of any DHCP message */
+struct dhcp_msg
+{
+  PACK_STRUCT_FIELD(u8_t op);
+  PACK_STRUCT_FIELD(u8_t htype);
+  PACK_STRUCT_FIELD(u8_t hlen);
+  PACK_STRUCT_FIELD(u8_t hops);
+  PACK_STRUCT_FIELD(u32_t xid);
+  PACK_STRUCT_FIELD(u16_t secs);
+  PACK_STRUCT_FIELD(u16_t flags);
+  PACK_STRUCT_FIELD(struct ip_addr ciaddr);
+  PACK_STRUCT_FIELD(struct ip_addr yiaddr);
+  PACK_STRUCT_FIELD(struct ip_addr siaddr);
+  PACK_STRUCT_FIELD(struct ip_addr giaddr);
+#define DHCP_CHADDR_LEN 16U
+  PACK_STRUCT_FIELD(u8_t chaddr[DHCP_CHADDR_LEN]);
+#define DHCP_SNAME_LEN 64U
+  PACK_STRUCT_FIELD(u8_t sname[DHCP_SNAME_LEN]);
+#define DHCP_FILE_LEN 128U
+  PACK_STRUCT_FIELD(u8_t file[DHCP_FILE_LEN]);
+  PACK_STRUCT_FIELD(u32_t cookie);
+#define DHCP_MIN_OPTIONS_LEN 68U
+/** make sure user does not configure this too small */
+#if ((defined(DHCP_OPTIONS_LEN)) && (DHCP_OPTIONS_LEN < DHCP_MIN_OPTIONS_LEN))
+#  undef DHCP_OPTIONS_LEN
+#endif
+/** allow this to be configured in lwipopts.h, but not too small */
+#if (!defined(DHCP_OPTIONS_LEN))
+/** set this to be sufficient for your options in outgoing DHCP msgs */
+#  define DHCP_OPTIONS_LEN DHCP_MIN_OPTIONS_LEN
+#endif
+  PACK_STRUCT_FIELD(u8_t options[DHCP_OPTIONS_LEN]);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/** start DHCP configuration */
+err_t dhcp_start(struct netif *netif);
+/** enforce early lease renewal (not needed normally)*/
+err_t dhcp_renew(struct netif *netif);
+/** release the DHCP lease, usually called before dhcp_stop()*/
+err_t dhcp_release(struct netif *netif);
+/** stop DHCP configuration */
+void dhcp_stop(struct netif *netif);
+/** inform server of our manual IP address */
+void dhcp_inform(struct netif *netif);
+
+/** if enabled, check whether the offered IP address is not in use, using ARP */
+#if DHCP_DOES_ARP_CHECK
+void dhcp_arp_reply(struct netif *netif, struct ip_addr *addr);
+#endif
+
+/** to be called every minute */
+void dhcp_coarse_tmr(void);
+/** to be called every half second */
+void dhcp_fine_tmr(void);
+ 
+/** DHCP message item offsets and length */
+#define DHCP_MSG_OFS (UDP_DATA_OFS)  
+  #define DHCP_OP_OFS (DHCP_MSG_OFS + 0)
+  #define DHCP_HTYPE_OFS (DHCP_MSG_OFS + 1)
+  #define DHCP_HLEN_OFS (DHCP_MSG_OFS + 2)
+  #define DHCP_HOPS_OFS (DHCP_MSG_OFS + 3)
+  #define DHCP_XID_OFS (DHCP_MSG_OFS + 4)
+  #define DHCP_SECS_OFS (DHCP_MSG_OFS + 8)
+  #define DHCP_FLAGS_OFS (DHCP_MSG_OFS + 10)
+  #define DHCP_CIADDR_OFS (DHCP_MSG_OFS + 12)
+  #define DHCP_YIADDR_OFS (DHCP_MSG_OFS + 16)
+  #define DHCP_SIADDR_OFS (DHCP_MSG_OFS + 20)
+  #define DHCP_GIADDR_OFS (DHCP_MSG_OFS + 24)
+  #define DHCP_CHADDR_OFS (DHCP_MSG_OFS + 28)
+  #define DHCP_SNAME_OFS (DHCP_MSG_OFS + 44)
+  #define DHCP_FILE_OFS (DHCP_MSG_OFS + 108)
+#define DHCP_MSG_LEN 236
+
+#define DHCP_COOKIE_OFS (DHCP_MSG_OFS + DHCP_MSG_LEN)
+#define DHCP_OPTIONS_OFS (DHCP_MSG_OFS + DHCP_MSG_LEN + 4)
+
+#define DHCP_CLIENT_PORT 68  
+#define DHCP_SERVER_PORT 67
+
+/** DHCP client states */
+#define DHCP_REQUESTING 1
+#define DHCP_INIT 2
+#define DHCP_REBOOTING 3
+#define DHCP_REBINDING 4
+#define DHCP_RENEWING 5
+#define DHCP_SELECTING 6
+#define DHCP_INFORMING 7
+#define DHCP_CHECKING 8
+#define DHCP_PERMANENT 9
+#define DHCP_BOUND 10
+/** not yet implemented #define DHCP_RELEASING 11 */
+#define DHCP_BACKING_OFF 12
+#define DHCP_OFF 13
+ 
+#define DHCP_BOOTREQUEST 1
+#define DHCP_BOOTREPLY 2
+
+#define DHCP_DISCOVER 1
+#define DHCP_OFFER 2
+#define DHCP_REQUEST 3
+#define DHCP_DECLINE 4
+#define DHCP_ACK 5
+#define DHCP_NAK 6
+#define DHCP_RELEASE 7
+#define DHCP_INFORM 8
+
+#define DHCP_HTYPE_ETH 1
+
+#define DHCP_HLEN_ETH 6
+
+#define DHCP_BROADCAST_FLAG 15
+#define DHCP_BROADCAST_MASK (1 << DHCP_FLAG_BROADCAST)
+
+/** BootP options */
+#define DHCP_OPTION_PAD 0
+#define DHCP_OPTION_SUBNET_MASK 1 /* RFC 2132 3.3 */
+#define DHCP_OPTION_ROUTER 3
+#define DHCP_OPTION_DNS_SERVER 6 
+#define DHCP_OPTION_HOSTNAME 12
+#define DHCP_OPTION_IP_TTL 23
+#define DHCP_OPTION_MTU 26
+#define DHCP_OPTION_BROADCAST 28
+#define DHCP_OPTION_TCP_TTL 37
+#define DHCP_OPTION_END 255
+
+/** DHCP options */
+#define DHCP_OPTION_REQUESTED_IP 50 /* RFC 2132 9.1, requested IP address */
+#define DHCP_OPTION_LEASE_TIME 51 /* RFC 2132 9.2, time in seconds, in 4 bytes */
+#define DHCP_OPTION_OVERLOAD 52 /* RFC2132 9.3, use file and/or sname field for options */
+
+#define DHCP_OPTION_MESSAGE_TYPE 53 /* RFC 2132 9.6, important for DHCP */
+#define DHCP_OPTION_MESSAGE_TYPE_LEN 1
+
+
+#define DHCP_OPTION_SERVER_ID 54 /* RFC 2132 9.7, server IP address */
+#define DHCP_OPTION_PARAMETER_REQUEST_LIST 55 /* RFC 2132 9.8, requested option types */
+
+#define DHCP_OPTION_MAX_MSG_SIZE 57 /* RFC 2132 9.10, message size accepted >= 576 */
+#define DHCP_OPTION_MAX_MSG_SIZE_LEN 2
+
+#define DHCP_OPTION_T1 58 /* T1 renewal time */
+#define DHCP_OPTION_T2 59 /* T2 rebinding time */
+#define DHCP_OPTION_CLIENT_ID 61
+#define DHCP_OPTION_TFTP_SERVERNAME 66
+#define DHCP_OPTION_BOOTFILE 67
+
+/** possible combinations of overloading the file and sname fields with options */
+#define DHCP_OVERLOAD_NONE 0
+#define DHCP_OVERLOAD_FILE 1
+#define DHCP_OVERLOAD_SNAME  2
+#define DHCP_OVERLOAD_SNAME_FILE 3
+
+#endif /*__LWIP_DHCP_H__*/
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/err.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/err.h
new file mode 100644
index 000000000..fc90f2eab
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/err.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_ERR_H__
+#define __LWIP_ERR_H__
+
+#include "lwip/opt.h"
+
+#include "arch/cc.h"
+
+typedef s8_t err_t;
+
+/* Definitions for error constants. */
+
+#define ERR_OK    0      /* No error, everything OK. */
+#define ERR_MEM  -1      /* Out of memory error.     */
+#define ERR_BUF  -2      /* Buffer error.            */
+
+
+#define ERR_ABRT -3      /* Connection aborted.      */
+#define ERR_RST  -4      /* Connection reset.        */
+#define ERR_CLSD -5      /* Connection closed.       */
+#define ERR_CONN -6      /* Not connected.           */
+
+#define ERR_VAL  -7      /* Illegal value.           */
+
+#define ERR_ARG  -8      /* Illegal argument.        */
+
+#define ERR_RTE  -9      /* Routing problem.         */
+
+#define ERR_USE  -10     /* Address in use.          */
+
+#define ERR_IF   -11     /* Low-level netif error    */
+#define ERR_ISCONN -12   /* Already connected.       */
+
+
+#ifdef LWIP_DEBUG
+extern char *lwip_strerr(err_t err);
+#else
+#define lwip_strerr(x) ""
+#endif /* LWIP_DEBUG */
+#endif /* __LWIP_ERR_H__ */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/mem.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/mem.h
new file mode 100644
index 000000000..b88ea9c8d
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/mem.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_MEM_H__
+#define __LWIP_MEM_H__
+
+#include "lwip/opt.h"
+#include "lwip/arch.h"
+
+#if MEM_SIZE > 64000l
+typedef u32_t mem_size_t;
+#else
+typedef u16_t mem_size_t;
+#endif /* MEM_SIZE > 64000 */
+
+
+void mem_init(void);
+
+void *mem_malloc(mem_size_t size);
+void mem_free(void *mem);
+void *mem_realloc(void *mem, mem_size_t size);
+void *mem_reallocm(void *mem, mem_size_t size);
+
+#ifndef MEM_ALIGN_SIZE
+#define MEM_ALIGN_SIZE(size) (((size) + MEM_ALIGNMENT - 1) & ~(MEM_ALIGNMENT-1))
+#endif
+
+#ifndef MEM_ALIGN
+#define MEM_ALIGN(addr) ((void *)(((mem_ptr_t)(addr) + MEM_ALIGNMENT - 1) & ~(mem_ptr_t)(MEM_ALIGNMENT-1)))
+#endif
+
+#endif /* __LWIP_MEM_H__ */
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/memp.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/memp.h
new file mode 100644
index 000000000..6da033f27
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/memp.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#ifndef __LWIP_MEMP_H__
+#define __LWIP_MEMP_H__
+
+#include "lwip/opt.h"
+
+typedef enum {
+  MEMP_PBUF,
+  MEMP_RAW_PCB,
+  MEMP_UDP_PCB,
+  MEMP_TCP_PCB,
+  MEMP_TCP_PCB_LISTEN,
+  MEMP_TCP_SEG,
+
+  MEMP_NETBUF,
+  MEMP_NETCONN,
+  MEMP_API_MSG,
+  MEMP_TCPIP_MSG,
+
+  MEMP_SYS_TIMEOUT,
+  
+  MEMP_MAX
+} memp_t;
+
+void memp_init(void);
+
+void *memp_malloc(memp_t type);
+void *memp_realloc(memp_t fromtype, memp_t totype, void *mem);
+void memp_free(memp_t type, void *mem);
+
+#endif /* __LWIP_MEMP_H__  */
+    
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/netif.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/netif.h
new file mode 100644
index 000000000..374aaa5ef
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/netif.h
@@ -0,0 +1,150 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_NETIF_H__
+#define __LWIP_NETIF_H__
+
+#include "lwip/opt.h"
+
+#include "lwip/err.h"
+
+#include "lwip/ip_addr.h"
+
+#include "lwip/inet.h"
+#include "lwip/pbuf.h"
+#if LWIP_DHCP
+#  include "lwip/dhcp.h"
+#endif
+
+/** must be the maximum of all used hardware address lengths
+    across all types of interfaces in use */
+#define NETIF_MAX_HWADDR_LEN 6U
+
+/** TODO: define the use (where, when, whom) of netif flags */
+
+/** whether the network interface is 'up'. this is
+ * a software flag used to control whether this network
+ * interface is enabled and processes traffic.
+ */
+#define NETIF_FLAG_UP 0x1U
+/** if set, the netif has broadcast capability */
+#define NETIF_FLAG_BROADCAST 0x2U
+/** if set, the netif is one end of a point-to-point connection */
+#define NETIF_FLAG_POINTTOPOINT 0x4U
+/** if set, the interface is configured using DHCP */
+#define NETIF_FLAG_DHCP 0x08U
+/** if set, the interface has an active link
+ *  (set by the network interface driver) */
+#define NETIF_FLAG_LINK_UP 0x10U
+
+/** Generic data structure used for all lwIP network interfaces.
+ *  The following fields should be filled in by the initialization
+ *  function for the device driver: hwaddr_len, hwaddr[], mtu, flags */
+
+struct netif {
+  /** pointer to next in linked list */
+  struct netif *next;
+
+  /** IP address configuration in network byte order */
+  struct ip_addr ip_addr;
+  struct ip_addr netmask;
+  struct ip_addr gw;
+
+  /** This function is called by the network device driver
+   *  to pass a packet up the TCP/IP stack. */
+  err_t (* input)(struct pbuf *p, struct netif *inp);
+  /** This function is called by the IP module when it wants
+   *  to send a packet on the interface. This function typically
+   *  first resolves the hardware address, then sends the packet. */
+  err_t (* output)(struct netif *netif, struct pbuf *p,
+       struct ip_addr *ipaddr);
+  /** This function is called by the ARP module when it wants
+   *  to send a packet on the interface. This function outputs
+   *  the pbuf as-is on the link medium. */
+  err_t (* linkoutput)(struct netif *netif, struct pbuf *p);
+  /** This field can be set by the device driver and could point
+   *  to state information for the device. */
+  void *state;
+#if LWIP_DHCP
+  /** the DHCP client state information for this netif */
+  struct dhcp *dhcp;
+#endif
+  /** number of bytes used in hwaddr */
+  u8_t hwaddr_len;
+  /** link level hardware address of this interface */
+  u8_t hwaddr[NETIF_MAX_HWADDR_LEN];
+  /** maximum transfer unit (in bytes) */
+  u16_t mtu;
+  /** flags (see NETIF_FLAG_ above) */
+  u8_t flags;
+  /** link type */
+  u8_t link_type;
+  /** descriptive abbreviation */
+  char name[2];
+  /** number of this interface */
+  u8_t num;
+};
+
+/** The list of network interfaces. */
+extern struct netif *netif_list;
+/** The default network interface. */
+extern struct netif *netif_default;
+
+/* netif_init() must be called first. */
+void netif_init(void);
+
+struct netif *netif_add(struct netif *netif, struct ip_addr *ipaddr, struct ip_addr *netmask,
+      struct ip_addr *gw,
+      void *state,
+      err_t (* init)(struct netif *netif),
+      err_t (* input)(struct pbuf *p, struct netif *netif));
+
+void
+netif_set_addr(struct netif *netif,struct ip_addr *ipaddr, struct ip_addr *netmask,
+    struct ip_addr *gw);
+void netif_remove(struct netif * netif);
+
+/* Returns a network interface given its name. The name is of the form
+   "et0", where the first two letters are the "name" field in the
+   netif structure, and the digit is in the num field in the same
+   structure. */
+struct netif *netif_find(char *name);
+
+void netif_set_default(struct netif *netif);
+
+void netif_set_ipaddr(struct netif *netif, struct ip_addr *ipaddr);
+void netif_set_netmask(struct netif *netif, struct ip_addr *netmast);
+void netif_set_gw(struct netif *netif, struct ip_addr *gw);
+void netif_set_up(struct netif *netif);
+void netif_set_down(struct netif *netif);
+u8_t netif_is_up(struct netif *netif);
+
+#endif /* __LWIP_NETIF_H__ */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/opt.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/opt.h
new file mode 100644
index 000000000..64720a030
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/opt.h
@@ -0,0 +1,671 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_OPT_H__
+#define __LWIP_OPT_H__
+
+/* Include user defined options first */
+#include "lwipopts.h"
+#include "lwip/debug.h"
+
+/* Define default values for unconfigured parameters. */
+
+/* Platform specific locking */
+
+/*
+ * enable SYS_LIGHTWEIGHT_PROT in lwipopts.h if you want inter-task protection
+ * for certain critical regions during buffer allocation, deallocation and memory
+ * allocation and deallocation.
+ */
+#ifndef SYS_LIGHTWEIGHT_PROT
+#define SYS_LIGHTWEIGHT_PROT            0
+#endif
+
+#ifndef NO_SYS
+#define NO_SYS                          0
+#endif
+/* ---------- Memory options ---------- */
+/* MEM_ALIGNMENT: should be set to the alignment of the CPU for which
+   lwIP is compiled. 4 byte alignment -> define MEM_ALIGNMENT to 4, 2
+   byte alignment -> define MEM_ALIGNMENT to 2. */
+
+#ifndef MEM_ALIGNMENT
+#define MEM_ALIGNMENT                   1
+#endif
+
+/* MEM_SIZE: the size of the heap memory. If the application will send
+a lot of data that needs to be copied, this should be set high. */
+#ifndef MEM_SIZE
+#define MEM_SIZE                        1600
+#endif
+
+#ifndef MEMP_SANITY_CHECK
+#define MEMP_SANITY_CHECK       0
+#endif
+
+/* MEMP_NUM_PBUF: the number of memp struct pbufs. If the application
+   sends a lot of data out of ROM (or other static memory), this
+   should be set high. */
+#ifndef MEMP_NUM_PBUF
+#define MEMP_NUM_PBUF                   16
+#endif
+
+/* Number of raw connection PCBs */
+#ifndef MEMP_NUM_RAW_PCB
+#define MEMP_NUM_RAW_PCB                4
+#endif
+
+/* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One
+   per active UDP "connection". */
+#ifndef MEMP_NUM_UDP_PCB
+#define MEMP_NUM_UDP_PCB                4
+#endif
+/* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP
+   connections. */
+#ifndef MEMP_NUM_TCP_PCB
+#define MEMP_NUM_TCP_PCB                5
+#endif
+/* MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP
+   connections. */
+#ifndef MEMP_NUM_TCP_PCB_LISTEN
+#define MEMP_NUM_TCP_PCB_LISTEN         8
+#endif
+/* MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP
+   segments. */
+#ifndef MEMP_NUM_TCP_SEG
+#define MEMP_NUM_TCP_SEG                16
+#endif
+/* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active
+   timeouts. */
+#ifndef MEMP_NUM_SYS_TIMEOUT
+#define MEMP_NUM_SYS_TIMEOUT            3
+#endif
+
+/* The following four are used only with the sequential API and can be
+   set to 0 if the application only will use the raw API. */
+/* MEMP_NUM_NETBUF: the number of struct netbufs. */
+#ifndef MEMP_NUM_NETBUF
+#define MEMP_NUM_NETBUF                 2
+#endif
+/* MEMP_NUM_NETCONN: the number of struct netconns. */
+#ifndef MEMP_NUM_NETCONN
+#define MEMP_NUM_NETCONN                4
+#endif
+/* MEMP_NUM_APIMSG: the number of struct api_msg, used for
+   communication between the TCP/IP stack and the sequential
+   programs. */
+#ifndef MEMP_NUM_API_MSG
+#define MEMP_NUM_API_MSG                8
+#endif
+/* MEMP_NUM_TCPIPMSG: the number of struct tcpip_msg, which is used
+   for sequential API communication and incoming packets. Used in
+   src/api/tcpip.c. */
+#ifndef MEMP_NUM_TCPIP_MSG
+#define MEMP_NUM_TCPIP_MSG              8
+#endif
+
+/* ---------- Pbuf options ---------- */
+/* PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */
+
+#ifndef PBUF_POOL_SIZE
+#define PBUF_POOL_SIZE                  16
+#endif
+
+/* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */
+
+#ifndef PBUF_POOL_BUFSIZE
+#define PBUF_POOL_BUFSIZE               128
+#endif
+
+/* PBUF_LINK_HLEN: the number of bytes that should be allocated for a
+   link level header. Defaults to 14 for Ethernet. */
+
+#ifndef PBUF_LINK_HLEN
+#define PBUF_LINK_HLEN                  14
+#endif
+
+
+
+/* ---------- ARP options ---------- */
+
+/** Number of active hardware address, IP address pairs cached */
+#ifndef ARP_TABLE_SIZE
+#define ARP_TABLE_SIZE                  10
+#endif
+
+/**
+ * If enabled, outgoing packets are queued during hardware address
+ * resolution.
+ *
+ * This feature has not stabilized yet. Single-packet queueing is
+ * believed to be stable, multi-packet queueing is believed to
+ * clash with the TCP segment queueing.
+ * 
+ * As multi-packet-queueing is currently disabled, enabling this
+ * _should_ work, but we need your testing feedback on lwip-users.
+ *
+ */
+#ifndef ARP_QUEUEING
+#define ARP_QUEUEING                    1
+#endif
+
+/* This option is deprecated */
+#ifdef ETHARP_QUEUE_FIRST
+#error ETHARP_QUEUE_FIRST option is deprecated. Remove it from your lwipopts.h.
+#endif
+
+/* This option is removed to comply with the ARP standard */
+#ifdef ETHARP_ALWAYS_INSERT
+#error ETHARP_ALWAYS_INSERT option is deprecated. Remove it from your lwipopts.h.
+#endif
+
+/* ---------- IP options ---------- */
+/* Define IP_FORWARD to 1 if you wish to have the ability to forward
+   IP packets across network interfaces. If you are going to run lwIP
+   on a device with only one network interface, define this to 0. */
+#ifndef IP_FORWARD
+#define IP_FORWARD                      0
+#endif
+
+/* If defined to 1, IP options are allowed (but not parsed). If
+   defined to 0, all packets with IP options are dropped. */
+#ifndef IP_OPTIONS
+#define IP_OPTIONS                      1
+#endif
+
+/** IP reassembly and segmentation. Even if they both deal with IP
+ *  fragments, note that these are orthogonal, one dealing with incoming
+ *  packets, the other with outgoing packets
+ */
+
+/** Reassemble incoming fragmented IP packets */
+#ifndef IP_REASSEMBLY
+#define IP_REASSEMBLY                   1
+#endif
+
+/** Fragment outgoing IP packets if their size exceeds MTU */
+#ifndef IP_FRAG
+#define IP_FRAG                         1
+#endif
+
+/* ---------- ICMP options ---------- */
+
+#ifndef ICMP_TTL
+#define ICMP_TTL                        255
+#endif
+
+/* ---------- RAW options ---------- */
+
+#ifndef LWIP_RAW
+#define LWIP_RAW                        1
+#endif
+
+#ifndef RAW_TTL
+#define RAW_TTL                        255
+#endif
+
+/* ---------- DHCP options ---------- */
+
+#ifndef LWIP_DHCP
+#define LWIP_DHCP                       0
+#endif
+
+/* 1 if you want to do an ARP check on the offered address
+   (recommended). */
+#ifndef DHCP_DOES_ARP_CHECK
+#define DHCP_DOES_ARP_CHECK             1
+#endif
+
+/* ---------- UDP options ---------- */
+#ifndef LWIP_UDP
+#define LWIP_UDP                        1
+#endif
+
+#ifndef UDP_TTL
+#define UDP_TTL                         255
+#endif
+
+/* ---------- TCP options ---------- */
+#ifndef LWIP_TCP
+#define LWIP_TCP                        1
+#endif
+
+#ifndef TCP_TTL
+#define TCP_TTL                         255
+#endif
+
+#ifndef TCP_WND
+#define TCP_WND                         2048
+#endif 
+
+#ifndef TCP_MAXRTX
+#define TCP_MAXRTX                      12
+#endif
+
+#ifndef TCP_SYNMAXRTX
+#define TCP_SYNMAXRTX                   6
+#endif
+
+
+/* Controls if TCP should queue segments that arrive out of
+   order. Define to 0 if your device is low on memory. */
+#ifndef TCP_QUEUE_OOSEQ
+#define TCP_QUEUE_OOSEQ                 1
+#endif
+
+/* TCP Maximum segment size. */
+#ifndef TCP_MSS
+#define TCP_MSS                         128 /* A *very* conservative default. */
+#endif
+
+/* TCP sender buffer space (bytes). */
+#ifndef TCP_SND_BUF
+#define TCP_SND_BUF                     256
+#endif
+
+/* TCP sender buffer space (pbufs). This must be at least = 2 *
+   TCP_SND_BUF/TCP_MSS for things to work. */
+#ifndef TCP_SND_QUEUELEN
+#define TCP_SND_QUEUELEN                4 * TCP_SND_BUF/TCP_MSS
+#endif
+
+
+/* Maximum number of retransmissions of data segments. */
+
+/* Maximum number of retransmissions of SYN segments. */
+
+/* TCP writable space (bytes). This must be less than or equal
+   to TCP_SND_BUF. It is the amount of space which must be
+   available in the tcp snd_buf for select to return writable */
+#ifndef TCP_SNDLOWAT
+#define TCP_SNDLOWAT                    TCP_SND_BUF/2
+#endif
+
+/* Support loop interface (127.0.0.1) */
+#ifndef LWIP_HAVE_LOOPIF
+#define LWIP_HAVE_LOOPIF                0
+#endif
+
+#ifndef LWIP_EVENT_API
+#define LWIP_EVENT_API                  0
+#define LWIP_CALLBACK_API               1
+#else 
+#define LWIP_EVENT_API                  1
+#define LWIP_CALLBACK_API               0
+#endif 
+
+#ifndef LWIP_COMPAT_SOCKETS
+#define LWIP_COMPAT_SOCKETS             1
+#endif
+
+
+#ifndef TCPIP_THREAD_PRIO
+#define TCPIP_THREAD_PRIO               1
+#endif
+
+#ifndef SLIPIF_THREAD_PRIO
+#define SLIPIF_THREAD_PRIO              1
+#endif
+
+#ifndef PPP_THREAD_PRIO
+#define PPP_THREAD_PRIO                 1
+#endif
+
+#ifndef DEFAULT_THREAD_PRIO
+#define DEFAULT_THREAD_PRIO             1
+#endif
+
+
+/* ---------- Socket Options ---------- */
+/* Enable SO_REUSEADDR and SO_REUSEPORT options */ 
+#ifdef SO_REUSE
+/* I removed the lot since this was an ugly hack. It broke the raw-API.
+   It also came with many ugly goto's, Christiaan Simons. */
+#error "SO_REUSE currently unavailable, this was a hack"
+#endif                                                                        
+
+
+/* ---------- Statistics options ---------- */
+#ifndef LWIP_STATS
+#define LWIP_STATS                      1
+#endif
+
+#if LWIP_STATS
+
+#ifndef LWIP_STATS_DISPLAY
+#define LWIP_STATS_DISPLAY 0
+#endif
+
+#ifndef LINK_STATS
+#define LINK_STATS  1
+#endif
+
+#ifndef IP_STATS
+#define IP_STATS    1
+#endif
+
+#ifndef IPFRAG_STATS
+#define IPFRAG_STATS    1
+#endif
+
+#ifndef ICMP_STATS
+#define ICMP_STATS  1
+#endif
+
+#ifndef UDP_STATS
+#define UDP_STATS   1
+#endif
+
+#ifndef TCP_STATS
+#define TCP_STATS   1
+#endif
+
+#ifndef MEM_STATS
+#define MEM_STATS   1
+#endif
+
+#ifndef MEMP_STATS
+#define MEMP_STATS  1
+#endif
+
+#ifndef PBUF_STATS
+#define PBUF_STATS  1
+#endif
+
+#ifndef SYS_STATS
+#define SYS_STATS   1
+#endif
+
+#ifndef RAW_STATS
+#define RAW_STATS   0
+#endif
+
+#else
+
+#define LINK_STATS  0
+#define IP_STATS    0
+#define IPFRAG_STATS    0
+#define ICMP_STATS  0
+#define UDP_STATS   0
+#define TCP_STATS   0
+#define MEM_STATS   0
+#define MEMP_STATS  0
+#define PBUF_STATS  0
+#define SYS_STATS   0
+#define RAW_STATS   0
+#define LWIP_STATS_DISPLAY  0
+
+#endif /* LWIP_STATS */
+
+/* ---------- PPP options ---------- */
+
+#ifndef PPP_SUPPORT
+#define PPP_SUPPORT                     0      /* Set for PPP */
+#endif
+
+#if PPP_SUPPORT 
+
+#define NUM_PPP                         1      /* Max PPP sessions. */
+
+
+
+#ifndef PAP_SUPPORT
+#define PAP_SUPPORT                     0      /* Set for PAP. */
+#endif
+
+#ifndef CHAP_SUPPORT
+#define CHAP_SUPPORT                    0      /* Set for CHAP. */
+#endif
+
+#define MSCHAP_SUPPORT                  0      /* Set for MSCHAP (NOT FUNCTIONAL!) */
+#define CBCP_SUPPORT                    0      /* Set for CBCP (NOT FUNCTIONAL!) */
+#define CCP_SUPPORT                     0      /* Set for CCP (NOT FUNCTIONAL!) */
+
+#ifndef VJ_SUPPORT
+#define VJ_SUPPORT                      0      /* Set for VJ header compression. */
+#endif
+
+#ifndef MD5_SUPPORT
+#define MD5_SUPPORT                     0      /* Set for MD5 (see also CHAP) */
+#endif
+
+
+/*
+ * Timeouts.
+ */
+#define FSM_DEFTIMEOUT                  6       /* Timeout time in seconds */
+#define FSM_DEFMAXTERMREQS              2       /* Maximum Terminate-Request transmissions */
+#define FSM_DEFMAXCONFREQS              10      /* Maximum Configure-Request transmissions */
+#define FSM_DEFMAXNAKLOOPS              5       /* Maximum number of nak loops */
+
+#define UPAP_DEFTIMEOUT                 6       /* Timeout (seconds) for retransmitting req */
+#define UPAP_DEFREQTIME                 30      /* Time to wait for auth-req from peer */
+
+#define CHAP_DEFTIMEOUT                 6       /* Timeout time in seconds */
+#define CHAP_DEFTRANSMITS               10      /* max # times to send challenge */
+
+
+/* Interval in seconds between keepalive echo requests, 0 to disable. */
+#if 1
+#define LCP_ECHOINTERVAL                0
+#else
+#define LCP_ECHOINTERVAL                10
+#endif
+
+/* Number of unanswered echo requests before failure. */
+#define LCP_MAXECHOFAILS                3
+
+/* Max Xmit idle time (in jiffies) before resend flag char. */
+#define PPP_MAXIDLEFLAG                 100
+
+/*
+ * Packet sizes
+ *
+ * Note - lcp shouldn't be allowed to negotiate stuff outside these
+ *    limits.  See lcp.h in the pppd directory.
+ * (XXX - these constants should simply be shared by lcp.c instead
+ *    of living in lcp.h)
+ */
+#define PPP_MTU                         1500     /* Default MTU (size of Info field) */
+#if 0
+#define PPP_MAXMTU  65535 - (PPP_HDRLEN + PPP_FCSLEN)
+#else
+#define PPP_MAXMTU                      1500 /* Largest MTU we allow */
+#endif
+#define PPP_MINMTU                      64
+#define PPP_MRU                         1500     /* default MRU = max length of info field */
+#define PPP_MAXMRU                      1500     /* Largest MRU we allow */
+#define PPP_DEFMRU                      296             /* Try for this */
+#define PPP_MINMRU                      128             /* No MRUs below this */
+
+
+#define MAXNAMELEN                      256     /* max length of hostname or name for auth */
+#define MAXSECRETLEN                    256     /* max length of password or secret */
+
+#endif /* PPP_SUPPORT */
+
+/* checksum options - set to zero for hardware checksum support */
+
+#ifndef CHECKSUM_GEN_IP
+#define CHECKSUM_GEN_IP                 1
+#endif
+ 
+#ifndef CHECKSUM_GEN_UDP
+#define CHECKSUM_GEN_UDP                1
+#endif
+ 
+#ifndef CHECKSUM_GEN_TCP
+#define CHECKSUM_GEN_TCP                1
+#endif
+ 
+#ifndef CHECKSUM_CHECK_IP
+#define CHECKSUM_CHECK_IP               1
+#endif
+ 
+#ifndef CHECKSUM_CHECK_UDP
+#define CHECKSUM_CHECK_UDP              1
+#endif
+
+#ifndef CHECKSUM_CHECK_TCP
+#define CHECKSUM_CHECK_TCP              1
+#endif
+
+/* Debugging options all default to off */
+
+#ifndef DBG_TYPES_ON
+#define DBG_TYPES_ON                    0
+#endif
+
+#ifndef ETHARP_DEBUG
+#define ETHARP_DEBUG                    DBG_OFF
+#endif
+
+#ifndef NETIF_DEBUG
+#define NETIF_DEBUG                     DBG_OFF
+#endif
+
+#ifndef PBUF_DEBUG
+#define PBUF_DEBUG                      DBG_OFF
+#endif
+
+#ifndef API_LIB_DEBUG
+#define API_LIB_DEBUG                   DBG_OFF
+#endif
+
+#ifndef API_MSG_DEBUG
+#define API_MSG_DEBUG                   DBG_OFF
+#endif
+
+#ifndef SOCKETS_DEBUG
+#define SOCKETS_DEBUG                   DBG_OFF
+#endif
+
+#ifndef ICMP_DEBUG
+#define ICMP_DEBUG                      DBG_OFF
+#endif
+
+#ifndef INET_DEBUG
+#define INET_DEBUG                      DBG_OFF
+#endif
+
+#ifndef IP_DEBUG
+#define IP_DEBUG                        DBG_OFF
+#endif
+
+#ifndef IP_REASS_DEBUG
+#define IP_REASS_DEBUG                  DBG_OFF
+#endif
+
+#ifndef RAW_DEBUG
+#define RAW_DEBUG                       DBG_OFF
+#endif
+
+#ifndef MEM_DEBUG
+#define MEM_DEBUG                       DBG_OFF
+#endif
+
+#ifndef MEMP_DEBUG
+#define MEMP_DEBUG                      DBG_OFF
+#endif
+
+#ifndef SYS_DEBUG
+#define SYS_DEBUG                       DBG_OFF
+#endif
+
+#ifndef TCP_DEBUG
+#define TCP_DEBUG                       DBG_OFF
+#endif
+
+#ifndef TCP_INPUT_DEBUG
+#define TCP_INPUT_DEBUG                 DBG_OFF
+#endif
+
+#ifndef TCP_FR_DEBUG
+#define TCP_FR_DEBUG                    DBG_OFF
+#endif
+
+#ifndef TCP_RTO_DEBUG
+#define TCP_RTO_DEBUG                   DBG_OFF
+#endif
+
+#ifndef TCP_REXMIT_DEBUG
+#define TCP_REXMIT_DEBUG                DBG_OFF
+#endif
+
+#ifndef TCP_CWND_DEBUG
+#define TCP_CWND_DEBUG                  DBG_OFF
+#endif
+
+#ifndef TCP_WND_DEBUG
+#define TCP_WND_DEBUG                   DBG_OFF
+#endif
+
+#ifndef TCP_OUTPUT_DEBUG
+#define TCP_OUTPUT_DEBUG                DBG_OFF
+#endif
+
+#ifndef TCP_RST_DEBUG
+#define TCP_RST_DEBUG                   DBG_OFF
+#endif
+
+#ifndef TCP_QLEN_DEBUG
+#define TCP_QLEN_DEBUG                  DBG_OFF
+#endif
+
+#ifndef UDP_DEBUG
+#define UDP_DEBUG                       DBG_OFF
+#endif
+
+#ifndef TCPIP_DEBUG
+#define TCPIP_DEBUG                     DBG_OFF
+#endif
+
+#ifndef PPP_DEBUG 
+#define PPP_DEBUG                       DBG_OFF
+#endif
+
+#ifndef SLIP_DEBUG 
+#define SLIP_DEBUG                      DBG_OFF
+#endif
+
+#ifndef DHCP_DEBUG 
+#define DHCP_DEBUG                      DBG_OFF
+#endif
+
+
+#ifndef DBG_MIN_LEVEL
+#define DBG_MIN_LEVEL                   DBG_LEVEL_OFF
+#endif
+
+#endif /* __LWIP_OPT_H__ */
+
+
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/pbuf.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/pbuf.h
new file mode 100644
index 000000000..0b187e121
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/pbuf.h
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#ifndef __LWIP_PBUF_H__
+#define __LWIP_PBUF_H__
+
+#include "arch/cc.h"
+
+
+#define PBUF_TRANSPORT_HLEN 20
+#define PBUF_IP_HLEN        20
+
+typedef enum {
+  PBUF_TRANSPORT,
+  PBUF_IP,
+  PBUF_LINK,
+  PBUF_RAW
+} pbuf_layer;
+
+typedef enum {
+  PBUF_RAM,
+  PBUF_ROM,
+  PBUF_REF,
+  PBUF_POOL
+} pbuf_flag;
+
+/* Definitions for the pbuf flag field. These are NOT the flags that
+ * are passed to pbuf_alloc(). */
+#define PBUF_FLAG_RAM   0x00U    /* Flags that pbuf data is stored in RAM */
+#define PBUF_FLAG_ROM   0x01U    /* Flags that pbuf data is stored in ROM */
+#define PBUF_FLAG_POOL  0x02U    /* Flags that the pbuf comes from the pbuf pool */
+#define PBUF_FLAG_REF   0x04U    /* Flags thet the pbuf payload refers to RAM */
+
+/** indicates this packet was broadcast on the link */
+#define PBUF_FLAG_LINK_BROADCAST 0x80U
+
+struct pbuf {
+  /** next pbuf in singly linked pbuf chain */
+  struct pbuf *next;
+
+  /** pointer to the actual data in the buffer */
+  void *payload;
+  
+  /**
+   * total length of this buffer and all next buffers in chain
+   * belonging to the same packet.
+   *
+   * For non-queue packet chains this is the invariant:
+   * p->tot_len == p->len + (p->next? p->next->tot_len: 0)
+   */
+  u16_t tot_len;
+  
+  /** length of this buffer */
+  u16_t len;  
+
+  /** flags telling the type of pbuf, see PBUF_FLAG_ */
+  u16_t flags;
+  
+  /**
+   * the reference count always equals the number of pointers
+   * that refer to this pbuf. This can be pointers from an application,
+   * the stack itself, or pbuf->next pointers from a chain.
+   */
+  u16_t ref;
+  
+};
+
+void pbuf_init(void);
+
+struct pbuf *pbuf_alloc(pbuf_layer l, u16_t size, pbuf_flag flag);
+void pbuf_realloc(struct pbuf *p, u16_t size); 
+u8_t pbuf_header(struct pbuf *p, s16_t header_size);
+void pbuf_ref(struct pbuf *p);
+void pbuf_ref_chain(struct pbuf *p);
+u8_t pbuf_free(struct pbuf *p);
+u8_t pbuf_clen(struct pbuf *p);  
+void pbuf_cat(struct pbuf *h, struct pbuf *t);
+void pbuf_chain(struct pbuf *h, struct pbuf *t);
+struct pbuf *pbuf_take(struct pbuf *f);
+struct pbuf *pbuf_dechain(struct pbuf *p);
+void pbuf_queue(struct pbuf *p, struct pbuf *n);
+struct pbuf * pbuf_dequeue(struct pbuf *p);
+
+#endif /* __LWIP_PBUF_H__ */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/raw.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/raw.h
new file mode 100644
index 000000000..83b32da9d
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/raw.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_RAW_H__
+#define __LWIP_RAW_H__
+
+#include "lwip/arch.h"
+
+#include "lwip/pbuf.h"
+#include "lwip/inet.h"
+#include "lwip/ip.h"
+
+struct raw_pcb {
+/* Common members of all PCB types */
+  IP_PCB;
+
+  struct raw_pcb *next;
+
+  u16_t protocol;
+
+  u8_t (* recv)(void *arg, struct raw_pcb *pcb, struct pbuf *p,
+    struct ip_addr *addr);
+  void *recv_arg;
+};
+
+/* The following functions is the application layer interface to the
+   RAW code. */
+struct raw_pcb * raw_new        (u16_t proto);
+void             raw_remove     (struct raw_pcb *pcb);
+err_t            raw_bind       (struct raw_pcb *pcb, struct ip_addr *ipaddr);
+err_t            raw_connect    (struct raw_pcb *pcb, struct ip_addr *ipaddr);
+
+void             raw_recv       (struct raw_pcb *pcb,
+                                 u8_t (* recv)(void *arg, struct raw_pcb *pcb,
+                                              struct pbuf *p,
+                                              struct ip_addr *addr),
+                                 void *recv_arg);
+err_t            raw_sendto    (struct raw_pcb *pcb, struct pbuf *p, struct ip_addr *ipaddr);
+err_t            raw_send       (struct raw_pcb *pcb, struct pbuf *p);
+
+/* The following functions are the lower layer interface to RAW. */
+u8_t              raw_input      (struct pbuf *p, struct netif *inp);
+void             raw_init       (void);
+
+
+#endif /* __LWIP_RAW_H__ */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/sio.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/sio.h
new file mode 100644
index 000000000..5fc28a4d6
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/sio.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ */
+
+/*
+ * This is the interface to the platform specific serial IO module
+ * It needs to be implemented by those platforms which need SLIP or PPP
+ */
+
+#include "arch/cc.h"
+
+#ifndef __sio_fd_t_defined
+typedef void * sio_fd_t;
+#endif
+
+#ifndef sio_open
+sio_fd_t sio_open(u8_t);
+#endif
+
+#ifndef sio_send
+void sio_send(u8_t, sio_fd_t);
+#endif
+
+#ifndef sio_recv
+u8_t sio_recv(sio_fd_t);
+#endif
+
+#ifndef sio_read
+u32_t sio_read(sio_fd_t, u8_t *, u32_t);
+#endif
+
+#ifndef sio_write
+u32_t sio_write(sio_fd_t, u8_t *, u32_t);
+#endif
+
+#ifndef sio_read_abort
+void sio_read_abort(sio_fd_t);
+#endif
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/snmp.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/snmp.h
new file mode 100644
index 000000000..4e806914b
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/snmp.h
@@ -0,0 +1,178 @@
+/*
+ * Copyright (c) 2001, 2002 Leon Woestenberg 
+ * Copyright (c) 2001, 2002 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Leon Woestenberg 
+ *
+ */
+#ifndef __LWIP_SNMP_H__
+#define __LWIP_SNMP_H__
+
+#include "lwip/opt.h"
+
+/* SNMP support available? */
+#if defined(LWIP_SNMP) && (LWIP_SNMP > 0)
+
+/* network interface */
+void snmp_add_ifinoctets(unsigned long value); 
+void snmp_inc_ifinucastpkts(void);
+void snmp_inc_ifinnucastpkts(void);
+void snmp_inc_ifindiscards(void);
+void snmp_add_ifoutoctets(unsigned long value);
+void snmp_inc_ifoutucastpkts(void);
+void snmp_inc_ifoutnucastpkts(void);
+void snmp_inc_ifoutdiscards(void);
+
+/* IP */
+void snmp_inc_ipinreceives(void);
+void snmp_inc_ipindelivers(void);
+void snmp_inc_ipindiscards(void);
+void snmp_inc_ipoutdiscards(void);
+void snmp_inc_ipoutrequests(void);
+void snmp_inc_ipunknownprotos(void);
+void snmp_inc_ipnoroutes(void);
+void snmp_inc_ipforwdatagrams(void);
+
+/* ICMP */
+void snmp_inc_icmpinmsgs(void);
+void snmp_inc_icmpinerrors(void);
+void snmp_inc_icmpindestunreachs(void);
+void snmp_inc_icmpintimeexcds(void);
+void snmp_inc_icmpinparmprobs(void);
+void snmp_inc_icmpinsrcquenchs(void);
+void snmp_inc_icmpinredirects(void);
+void snmp_inc_icmpinechos(void);
+void snmp_inc_icmpinechoreps(void);
+void snmp_inc_icmpintimestamps(void);
+void snmp_inc_icmpintimestampreps(void);
+void snmp_inc_icmpinaddrmasks(void);
+void snmp_inc_icmpinaddrmaskreps(void);
+void snmp_inc_icmpoutmsgs(void);
+void snmp_inc_icmpouterrors(void);
+void snmp_inc_icmpoutdestunreachs(void);
+void snmp_inc_icmpouttimeexcds(void);
+void snmp_inc_icmpoutparmprobs(void);
+void snmp_inc_icmpoutsrcquenchs(void);
+void snmp_inc_icmpoutredirects(void); 
+void snmp_inc_icmpoutechos(void);
+void snmp_inc_icmpoutechoreps(void);
+void snmp_inc_icmpouttimestamps(void);
+void snmp_inc_icmpouttimestampreps(void);
+void snmp_inc_icmpoutaddrmasks(void);
+void snmp_inc_icmpoutaddrmaskreps(void);
+
+/* TCP */
+void snmp_inc_tcpactiveopens(void);
+void snmp_inc_tcppassiveopens(void);
+void snmp_inc_tcpattemptfails(void);
+void snmp_inc_tcpestabresets(void);
+void snmp_inc_tcpcurrestab(void);
+void snmp_inc_tcpinsegs(void);
+void snmp_inc_tcpoutsegs(void);
+void snmp_inc_tcpretranssegs(void);
+void snmp_inc_tcpinerrs(void);
+void snmp_inc_tcpoutrsts(void);
+
+/* UDP */
+void snmp_inc_udpindatagrams(void);
+void snmp_inc_udpnoports(void);
+void snmp_inc_udpinerrors(void);
+void snmp_inc_udpoutdatagrams(void);
+
+/* LWIP_SNMP support not available */
+/* define everything to be empty */
+#else
+
+/* network interface */
+#define snmp_add_ifinoctets(value) 
+#define snmp_inc_ifinucastpkts()
+#define snmp_inc_ifinnucastpkts()
+#define snmp_inc_ifindiscards()
+#define snmp_add_ifoutoctets(value)
+#define snmp_inc_ifoutucastpkts()
+#define snmp_inc_ifoutnucastpkts()
+#define snmp_inc_ifoutdiscards()
+
+/* IP */
+#define snmp_inc_ipinreceives()
+#define snmp_inc_ipindelivers()
+#define snmp_inc_ipindiscards()
+#define snmp_inc_ipoutdiscards()
+#define snmp_inc_ipoutrequests()
+#define snmp_inc_ipunknownprotos()
+#define snmp_inc_ipnoroutes()
+#define snmp_inc_ipforwdatagrams()
+
+/* ICMP */
+#define snmp_inc_icmpinmsgs()
+#define snmp_inc_icmpinerrors() 
+#define snmp_inc_icmpindestunreachs() 
+#define snmp_inc_icmpintimeexcds()
+#define snmp_inc_icmpinparmprobs() 
+#define snmp_inc_icmpinsrcquenchs() 
+#define snmp_inc_icmpinredirects() 
+#define snmp_inc_icmpinechos() 
+#define snmp_inc_icmpinechoreps()
+#define snmp_inc_icmpintimestamps() 
+#define snmp_inc_icmpintimestampreps()
+#define snmp_inc_icmpinaddrmasks()
+#define snmp_inc_icmpinaddrmaskreps()
+#define snmp_inc_icmpoutmsgs()
+#define snmp_inc_icmpouterrors()
+#define snmp_inc_icmpoutdestunreachs() 
+#define snmp_inc_icmpouttimeexcds() 
+#define snmp_inc_icmpoutparmprobs()
+#define snmp_inc_icmpoutsrcquenchs()
+#define snmp_inc_icmpoutredirects() 
+#define snmp_inc_icmpoutechos() 
+#define snmp_inc_icmpoutechoreps()
+#define snmp_inc_icmpouttimestamps()
+#define snmp_inc_icmpouttimestampreps()
+#define snmp_inc_icmpoutaddrmasks()
+#define snmp_inc_icmpoutaddrmaskreps()
+/* TCP */
+#define snmp_inc_tcpactiveopens()
+#define snmp_inc_tcppassiveopens()
+#define snmp_inc_tcpattemptfails()
+#define snmp_inc_tcpestabresets()
+#define snmp_inc_tcpcurrestab()
+#define snmp_inc_tcpinsegs()
+#define snmp_inc_tcpoutsegs()
+#define snmp_inc_tcpretranssegs()
+#define snmp_inc_tcpinerrs()
+#define snmp_inc_tcpoutrsts()
+
+/* UDP */
+#define snmp_inc_udpindatagrams()
+#define snmp_inc_udpnoports()
+#define snmp_inc_udpinerrors()
+#define snmp_inc_udpoutdatagrams()
+
+#endif
+
+#endif /* __LWIP_SNMP_H__ */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/sockets.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/sockets.h
new file mode 100644
index 000000000..9c25035ad
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/sockets.h
@@ -0,0 +1,271 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+
+#ifndef __LWIP_SOCKETS_H__
+#define __LWIP_SOCKETS_H__
+#include "lwip/ip_addr.h"
+
+struct sockaddr_in {
+  u8_t sin_len;
+  u8_t sin_family;
+  u16_t sin_port;
+  struct in_addr sin_addr;
+  char sin_zero[8];
+};
+
+struct sockaddr {
+  u8_t sa_len;
+  u8_t sa_family;
+  char sa_data[14];
+};
+
+#ifndef socklen_t
+#  define socklen_t int
+#endif
+
+
+#define SOCK_STREAM     1
+#define SOCK_DGRAM      2
+#define SOCK_RAW        3
+
+/*
+ * Option flags per-socket.
+ */
+#define  SO_DEBUG  0x0001    /* turn on debugging info recording */
+#define  SO_ACCEPTCONN  0x0002    /* socket has had listen() */
+#define  SO_REUSEADDR  0x0004    /* allow local address reuse */
+#define  SO_KEEPALIVE  0x0008    /* keep connections alive */
+#define  SO_DONTROUTE  0x0010    /* just use interface addresses */
+#define  SO_BROADCAST  0x0020    /* permit sending of broadcast msgs */
+#define  SO_USELOOPBACK  0x0040    /* bypass hardware when possible */
+#define  SO_LINGER  0x0080    /* linger on close if data present */
+#define  SO_OOBINLINE  0x0100    /* leave received OOB data in line */
+#define	 SO_REUSEPORT	0x0200		/* allow local address & port reuse */
+
+#define SO_DONTLINGER   (int)(~SO_LINGER)
+
+/*
+ * Additional options, not kept in so_options.
+ */
+#define SO_SNDBUF  0x1001    /* send buffer size */
+#define SO_RCVBUF  0x1002    /* receive buffer size */
+#define SO_SNDLOWAT  0x1003    /* send low-water mark */
+#define SO_RCVLOWAT  0x1004    /* receive low-water mark */
+#define SO_SNDTIMEO  0x1005    /* send timeout */
+#define SO_RCVTIMEO  0x1006    /* receive timeout */
+#define  SO_ERROR  0x1007    /* get error status and clear */
+#define  SO_TYPE    0x1008    /* get socket type */
+
+
+
+/*
+ * Structure used for manipulating linger option.
+ */
+struct linger {
+       int l_onoff;                /* option on/off */
+       int l_linger;               /* linger time */
+};
+
+/*
+ * Level number for (get/set)sockopt() to apply to socket itself.
+ */
+#define  SOL_SOCKET  0xfff    /* options for socket level */
+
+
+#define AF_UNSPEC       0
+#define AF_INET         2
+#define PF_INET         AF_INET
+#define PF_UNSPEC       AF_UNSPEC
+
+#define IPPROTO_IP      0
+#define IPPROTO_TCP     6
+#define IPPROTO_UDP     17
+
+#define INADDR_ANY      0
+#define INADDR_BROADCAST 0xffffffff
+
+/* Flags we can use with send and recv. */
+#define MSG_DONTWAIT    0x40            /* Nonblocking i/o for this operation only */
+
+
+/*
+ * Options for level IPPROTO_IP
+ */
+#define IP_TOS       1
+#define IP_TTL       2
+
+
+#define IPTOS_TOS_MASK          0x1E
+#define IPTOS_TOS(tos)          ((tos) & IPTOS_TOS_MASK)
+#define IPTOS_LOWDELAY          0x10
+#define IPTOS_THROUGHPUT        0x08
+#define IPTOS_RELIABILITY       0x04
+#define IPTOS_LOWCOST           0x02
+#define IPTOS_MINCOST           IPTOS_LOWCOST
+
+/*
+ * Definitions for IP precedence (also in ip_tos) (hopefully unused)
+ */
+#define IPTOS_PREC_MASK                 0xe0
+#define IPTOS_PREC(tos)                ((tos) & IPTOS_PREC_MASK)
+#define IPTOS_PREC_NETCONTROL           0xe0
+#define IPTOS_PREC_INTERNETCONTROL      0xc0
+#define IPTOS_PREC_CRITIC_ECP           0xa0
+#define IPTOS_PREC_FLASHOVERRIDE        0x80
+#define IPTOS_PREC_FLASH                0x60
+#define IPTOS_PREC_IMMEDIATE            0x40
+#define IPTOS_PREC_PRIORITY             0x20
+#define IPTOS_PREC_ROUTINE              0x00
+
+
+/*
+ * Commands for ioctlsocket(),  taken from the BSD file fcntl.h.
+ *
+ *
+ * Ioctl's have the command encoded in the lower word,
+ * and the size of any in or out parameters in the upper
+ * word.  The high 2 bits of the upper word are used
+ * to encode the in/out status of the parameter; for now
+ * we restrict parameters to at most 128 bytes.
+ */
+#if !defined(FIONREAD) || !defined(FIONBIO)
+#define IOCPARM_MASK    0x7f            /* parameters must be < 128 bytes */
+#define IOC_VOID        0x20000000      /* no parameters */
+#define IOC_OUT         0x40000000      /* copy out parameters */
+#define IOC_IN          0x80000000      /* copy in parameters */
+#define IOC_INOUT       (IOC_IN|IOC_OUT)
+                                        /* 0x20000000 distinguishes new &
+                                           old ioctl's */
+#define _IO(x,y)        (IOC_VOID|((x)<<8)|(y))
+
+#define _IOR(x,y,t)     (IOC_OUT|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y))
+
+#define _IOW(x,y,t)     (IOC_IN|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y))
+#endif
+
+#ifndef FIONREAD
+#define FIONREAD    _IOR('f', 127, unsigned long) /* get # bytes to read */
+#endif
+#ifndef FIONBIO
+#define FIONBIO     _IOW('f', 126, unsigned long) /* set/clear non-blocking i/o */
+#endif
+
+/* Socket I/O Controls */
+#ifndef SIOCSHIWAT
+#define SIOCSHIWAT  _IOW('s',  0, unsigned long)  /* set high watermark */
+#define SIOCGHIWAT  _IOR('s',  1, unsigned long)  /* get high watermark */
+#define SIOCSLOWAT  _IOW('s',  2, unsigned long)  /* set low watermark */
+#define SIOCGLOWAT  _IOR('s',  3, unsigned long)  /* get low watermark */
+#define SIOCATMARK  _IOR('s',  7, unsigned long)  /* at oob mark? */
+#endif
+
+#ifndef O_NONBLOCK
+#define O_NONBLOCK    04000U
+#endif
+
+#ifndef FD_SET
+  #undef  FD_SETSIZE
+  #define FD_SETSIZE    16
+  #define FD_SET(n, p)  ((p)->fd_bits[(n)/8] |=  (1 << ((n) & 7)))
+  #define FD_CLR(n, p)  ((p)->fd_bits[(n)/8] &= ~(1 << ((n) & 7)))
+  #define FD_ISSET(n,p) ((p)->fd_bits[(n)/8] &   (1 << ((n) & 7)))
+  #define FD_ZERO(p)    memset((void*)(p),0,sizeof(*(p)))
+
+  typedef struct fd_set {
+          unsigned char fd_bits [(FD_SETSIZE+7)/8];
+        } fd_set;
+
+/* 
+ * only define this in sockets.c so it does not interfere
+ * with other projects namespaces where timeval is present
+ */ 
+#ifndef LWIP_TIMEVAL_PRIVATE
+#define LWIP_TIMEVAL_PRIVATE 1
+#endif
+
+#if LWIP_TIMEVAL_PRIVATE
+  struct timeval {
+    long    tv_sec;         /* seconds */
+    long    tv_usec;        /* and microseconds */
+  };
+#endif
+
+#endif
+
+int lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen);
+int lwip_bind(int s, struct sockaddr *name, socklen_t namelen);
+int lwip_shutdown(int s, int how);
+int lwip_getpeername (int s, struct sockaddr *name, socklen_t *namelen);
+int lwip_getsockname (int s, struct sockaddr *name, socklen_t *namelen);
+int lwip_getsockopt (int s, int level, int optname, void *optval, socklen_t *optlen);
+int lwip_setsockopt (int s, int level, int optname, const void *optval, socklen_t optlen);
+int lwip_close(int s);
+int lwip_connect(int s, struct sockaddr *name, socklen_t namelen);
+int lwip_listen(int s, int backlog);
+int lwip_recv(int s, void *mem, int len, unsigned int flags);
+int lwip_read(int s, void *mem, int len);
+int lwip_recvfrom(int s, void *mem, int len, unsigned int flags,
+      struct sockaddr *from, socklen_t *fromlen);
+int lwip_send(int s, void *dataptr, int size, unsigned int flags);
+int lwip_sendto(int s, void *dataptr, int size, unsigned int flags,
+    struct sockaddr *to, socklen_t tolen);
+int lwip_socket(int domain, int type, int protocol);
+int lwip_write(int s, void *dataptr, int size);
+int lwip_select(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset,
+                struct timeval *timeout);
+int lwip_ioctl(int s, long cmd, void *argp);
+
+#if LWIP_COMPAT_SOCKETS
+#define accept(a,b,c)         lwip_accept(a,b,c)
+#define bind(a,b,c)           lwip_bind(a,b,c)
+#define shutdown(a,b)         lwip_shutdown(a,b)
+#define close(s)              lwip_close(s)
+#define connect(a,b,c)        lwip_connect(a,b,c)
+#define getsockname(a,b,c)    lwip_getsockname(a,b,c)
+#define getpeername(a,b,c)    lwip_getpeername(a,b,c)
+#define setsockopt(a,b,c,d,e) lwip_setsockopt(a,b,c,d,e)
+#define getsockopt(a,b,c,d,e) lwip_getsockopt(a,b,c,d,e)
+#define listen(a,b)           lwip_listen(a,b)
+#define recv(a,b,c,d)         lwip_recv(a,b,c,d)
+#define read(a,b,c)           lwip_read(a,b,c)
+#define recvfrom(a,b,c,d,e,f) lwip_recvfrom(a,b,c,d,e,f)
+#define send(a,b,c,d)         lwip_send(a,b,c,d)
+#define sendto(a,b,c,d,e,f)   lwip_sendto(a,b,c,d,e,f)
+#define socket(a,b,c)         lwip_socket(a,b,c)
+#define write(a,b,c)          lwip_write(a,b,c)
+#define select(a,b,c,d,e)     lwip_select(a,b,c,d,e)
+#define ioctlsocket(a,b,c)    lwip_ioctl(a,b,c)
+#endif /* LWIP_COMPAT_SOCKETS */
+
+#endif /* __LWIP_SOCKETS_H__ */
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/stats.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/stats.h
new file mode 100644
index 000000000..29dfd5731
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/stats.h
@@ -0,0 +1,158 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_STATS_H__
+#define __LWIP_STATS_H__
+
+#include "lwip/opt.h"
+#include "arch/cc.h"
+
+#include "lwip/mem.h"
+#include "lwip/memp.h"
+
+#if LWIP_STATS
+
+struct stats_proto {
+  u16_t xmit;    /* Transmitted packets. */
+  u16_t rexmit;  /* Retransmitted packets. */
+  u16_t recv;    /* Received packets. */
+  u16_t fw;      /* Forwarded packets. */
+  u16_t drop;    /* Dropped packets. */
+  u16_t chkerr;  /* Checksum error. */
+  u16_t lenerr;  /* Invalid length error. */
+  u16_t memerr;  /* Out of memory error. */
+  u16_t rterr;   /* Routing error. */
+  u16_t proterr; /* Protocol error. */
+  u16_t opterr;  /* Error in options. */
+  u16_t err;     /* Misc error. */
+  u16_t cachehit;
+};
+
+struct stats_mem {
+  mem_size_t avail;
+  mem_size_t used;
+  mem_size_t max;  
+  mem_size_t err;
+};
+
+struct stats_pbuf {
+  u16_t avail;
+  u16_t used;
+  u16_t max;  
+  u16_t err;
+
+  u16_t alloc_locked;
+  u16_t refresh_locked;
+};
+
+struct stats_syselem {
+  u16_t used;
+  u16_t max;
+  u16_t err;
+};
+
+struct stats_sys {
+  struct stats_syselem sem;
+  struct stats_syselem mbox;
+};
+
+struct stats_ {
+  struct stats_proto link;
+  struct stats_proto ip_frag;
+  struct stats_proto ip;
+  struct stats_proto icmp;
+  struct stats_proto udp;
+  struct stats_proto tcp;
+  struct stats_pbuf pbuf;
+  struct stats_mem mem;
+  struct stats_mem memp[MEMP_MAX];
+  struct stats_sys sys;
+};
+
+extern struct stats_ lwip_stats;
+
+
+void stats_init(void);
+
+#define STATS_INC(x) ++lwip_stats.x
+#else
+#define stats_init()
+#define STATS_INC(x)
+#endif /* LWIP_STATS */
+
+#if TCP_STATS
+#define TCP_STATS_INC(x) STATS_INC(x)
+#else
+#define TCP_STATS_INC(x)
+#endif
+
+#if UDP_STATS
+#define UDP_STATS_INC(x) STATS_INC(x)
+#else
+#define UDP_STATS_INC(x)
+#endif
+
+#if ICMP_STATS
+#define ICMP_STATS_INC(x) STATS_INC(x)
+#else
+#define ICMP_STATS_INC(x)
+#endif
+
+#if IP_STATS
+#define IP_STATS_INC(x) STATS_INC(x)
+#else
+#define IP_STATS_INC(x)
+#endif
+
+#if IPFRAG_STATS
+#define IPFRAG_STATS_INC(x) STATS_INC(x)
+#else
+#define IPFRAG_STATS_INC(x)
+#endif
+
+#if LINK_STATS
+#define LINK_STATS_INC(x) STATS_INC(x)
+#else
+#define LINK_STATS_INC(x)
+#endif
+
+/* Display of statistics */
+#if LWIP_STATS_DISPLAY
+void stats_display(void);
+#else
+#define stats_display()
+#endif
+
+#endif /* __LWIP_STATS_H__ */
+
+
+
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/sys.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/sys.h
new file mode 100644
index 000000000..d2328c462
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/sys.h
@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_SYS_H__
+#define __LWIP_SYS_H__
+
+#include "arch/cc.h"
+
+#include "lwip/opt.h"
+
+
+#if NO_SYS
+
+/* For a totally minimal and standalone system, we provide null
+   definitions of the sys_ functions. */
+typedef u8_t sys_sem_t;
+typedef u8_t sys_mbox_t;
+struct sys_timeout {u8_t dummy;};
+
+#define sys_init()
+#define sys_timeout(m,h,a)
+#define sys_untimeout(m,a)
+#define sys_sem_new(c) c
+#define sys_sem_signal(s)
+#define sys_sem_wait(s)
+#define sys_sem_free(s)
+#define sys_mbox_new() 0
+#define sys_mbox_fetch(m,d)
+#define sys_mbox_post(m,d)
+#define sys_mbox_free(m)
+
+#define sys_thread_new(t,a,p)
+
+#else /* NO_SYS */
+
+#include "arch/sys_arch.h"
+
+/** Return code for timeouts from sys_arch_mbox_fetch and sys_arch_sem_wait */
+#define SYS_ARCH_TIMEOUT 0xffffffff
+
+typedef void (* sys_timeout_handler)(void *arg);
+
+struct sys_timeout {
+  struct sys_timeout *next;
+  u32_t time;
+  sys_timeout_handler h;
+  void *arg;
+};
+
+struct sys_timeouts {
+  struct sys_timeout *next;
+};
+
+/* sys_init() must be called before anthing else. */
+void sys_init(void);
+
+/*
+ * sys_timeout():
+ *
+ * Schedule a timeout a specified amount of milliseconds in the
+ * future. When the timeout occurs, the specified timeout handler will
+ * be called. The handler will be passed the "arg" argument when
+ * called.
+ *
+ */
+void sys_timeout(u32_t msecs, sys_timeout_handler h, void *arg);
+void sys_untimeout(sys_timeout_handler h, void *arg);
+struct sys_timeouts *sys_arch_timeouts(void);
+
+/* Semaphore functions. */
+sys_sem_t sys_sem_new(u8_t count);
+void sys_sem_signal(sys_sem_t sem);
+u32_t sys_arch_sem_wait(sys_sem_t sem, u32_t timeout);
+void sys_sem_free(sys_sem_t sem);
+void sys_sem_wait(sys_sem_t sem);
+int sys_sem_wait_timeout(sys_sem_t sem, u32_t timeout);
+
+/* Time functions. */
+#ifndef sys_msleep
+void sys_msleep(u32_t ms); /* only has a (close to) 1 jiffy resolution. */
+#endif
+#ifndef sys_jiffies
+u32_t sys_jiffies(void); /* since power up. */
+#endif
+
+/* Mailbox functions. */
+sys_mbox_t sys_mbox_new(void);
+void sys_mbox_post(sys_mbox_t mbox, void *msg);
+u32_t sys_arch_mbox_fetch(sys_mbox_t mbox, void **msg, u32_t timeout);
+void sys_mbox_free(sys_mbox_t mbox);
+void sys_mbox_fetch(sys_mbox_t mbox, void **msg);
+
+
+/* Thread functions. */
+sys_thread_t sys_thread_new(void (* thread)(void *arg), void *arg, int prio);
+
+/* The following functions are used only in Unix code, and
+   can be omitted when porting the stack. */
+/* Returns the current time in microseconds. */
+unsigned long sys_now(void);
+
+#endif /* NO_SYS */
+
+/* Critical Region Protection */
+/* These functions must be implemented in the sys_arch.c file.
+   In some implementations they can provide a more light-weight protection
+   mechanism than using semaphores. Otherwise semaphores can be used for
+   implementation */
+#ifndef SYS_ARCH_PROTECT
+/** SYS_LIGHTWEIGHT_PROT
+ * define SYS_LIGHTWEIGHT_PROT in lwipopts.h if you want inter-task protection
+ * for certain critical regions during buffer allocation, deallocation and memory
+ * allocation and deallocation.
+ */
+#if SYS_LIGHTWEIGHT_PROT
+
+/** SYS_ARCH_DECL_PROTECT
+ * declare a protection variable. This macro will default to defining a variable of
+ * type sys_prot_t. If a particular port needs a different implementation, then
+ * this macro may be defined in sys_arch.h.
+ */
+#define SYS_ARCH_DECL_PROTECT(lev) sys_prot_t lev
+/** SYS_ARCH_PROTECT
+ * Perform a "fast" protect. This could be implemented by
+ * disabling interrupts for an embedded system or by using a semaphore or
+ * mutex. The implementation should allow calling SYS_ARCH_PROTECT when
+ * already protected. The old protection level is returned in the variable
+ * "lev". This macro will default to calling the sys_arch_protect() function
+ * which should be implemented in sys_arch.c. If a particular port needs a
+ * different implementation, then this macro may be defined in sys_arch.h
+ */
+#define SYS_ARCH_PROTECT(lev) lev = sys_arch_protect()
+/** SYS_ARCH_UNPROTECT
+ * Perform a "fast" set of the protection level to "lev". This could be
+ * implemented by setting the interrupt level to "lev" within the MACRO or by
+ * using a semaphore or mutex.  This macro will default to calling the
+ * sys_arch_unprotect() function which should be implemented in
+ * sys_arch.c. If a particular port needs a different implementation, then
+ * this macro may be defined in sys_arch.h
+ */
+#define SYS_ARCH_UNPROTECT(lev) sys_arch_unprotect(lev)
+sys_prot_t sys_arch_protect(void);
+void sys_arch_unprotect(sys_prot_t pval);
+
+#else
+
+#define SYS_ARCH_DECL_PROTECT(lev)
+#define SYS_ARCH_PROTECT(lev)
+#define SYS_ARCH_UNPROTECT(lev)
+
+#endif /* SYS_LIGHTWEIGHT_PROT */
+
+#endif /* SYS_ARCH_PROTECT */
+
+#endif /* __LWIP_SYS_H__ */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/tcp.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/tcp.h
new file mode 100644
index 000000000..1395e4161
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/tcp.h
@@ -0,0 +1,531 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_TCP_H__
+#define __LWIP_TCP_H__
+
+#include "lwip/sys.h"
+#include "lwip/mem.h"
+
+#include "lwip/pbuf.h"
+#include "lwip/opt.h"
+#include "lwip/ip.h"
+#include "lwip/icmp.h"
+
+#include "lwip/err.h"
+
+struct tcp_pcb;
+
+/* Functions for interfacing with TCP: */
+
+/* Lower layer interface to TCP: */
+void             tcp_init    (void);  /* Must be called first to
+           initialize TCP. */
+void             tcp_tmr     (void);  /* Must be called every
+           TCP_TMR_INTERVAL
+           ms. (Typically 250 ms). */
+/* Application program's interface: */
+struct tcp_pcb * tcp_new     (void);
+struct tcp_pcb * tcp_alloc   (u8_t prio);
+
+void             tcp_arg     (struct tcp_pcb *pcb, void *arg);
+void             tcp_accept  (struct tcp_pcb *pcb,
+            err_t (* accept)(void *arg, struct tcp_pcb *newpcb,
+                 err_t err));
+void             tcp_recv    (struct tcp_pcb *pcb,
+            err_t (* recv)(void *arg, struct tcp_pcb *tpcb,
+          struct pbuf *p, err_t err));
+void             tcp_sent    (struct tcp_pcb *pcb,
+            err_t (* sent)(void *arg, struct tcp_pcb *tpcb,
+               u16_t len));
+void             tcp_poll    (struct tcp_pcb *pcb,
+            err_t (* poll)(void *arg, struct tcp_pcb *tpcb),
+            u8_t interval);
+void             tcp_err     (struct tcp_pcb *pcb,
+            void (* err)(void *arg, err_t err));
+
+#define          tcp_mss(pcb)      ((pcb)->mss)
+#define          tcp_sndbuf(pcb)   ((pcb)->snd_buf)
+
+void             tcp_recved  (struct tcp_pcb *pcb, u16_t len);
+err_t            tcp_bind    (struct tcp_pcb *pcb, struct ip_addr *ipaddr,
+            u16_t port);
+err_t            tcp_connect (struct tcp_pcb *pcb, struct ip_addr *ipaddr,
+            u16_t port, err_t (* connected)(void *arg,
+                    struct tcp_pcb *tpcb,
+                    err_t err));
+struct tcp_pcb * tcp_listen  (struct tcp_pcb *pcb);
+void             tcp_abort   (struct tcp_pcb *pcb);
+err_t            tcp_close   (struct tcp_pcb *pcb);
+err_t            tcp_write   (struct tcp_pcb *pcb, const void *dataptr, u16_t len,
+            u8_t copy);
+
+void             tcp_setprio (struct tcp_pcb *pcb, u8_t prio);
+
+#define TCP_PRIO_MIN    1
+#define TCP_PRIO_NORMAL 64
+#define TCP_PRIO_MAX    127
+
+/* It is also possible to call these two functions at the right
+   intervals (instead of calling tcp_tmr()). */
+void             tcp_slowtmr (void);
+void             tcp_fasttmr (void);
+
+
+/* Only used by IP to pass a TCP segment to TCP: */
+void             tcp_input   (struct pbuf *p, struct netif *inp);
+/* Used within the TCP code only: */
+err_t            tcp_output  (struct tcp_pcb *pcb);
+void             tcp_rexmit  (struct tcp_pcb *pcb);
+void             tcp_rexmit_rto  (struct tcp_pcb *pcb);
+
+
+
+#define TCP_SEQ_LT(a,b)     ((s32_t)((a)-(b)) < 0)
+#define TCP_SEQ_LEQ(a,b)    ((s32_t)((a)-(b)) <= 0)
+#define TCP_SEQ_GT(a,b)     ((s32_t)((a)-(b)) > 0)
+#define TCP_SEQ_GEQ(a,b)    ((s32_t)((a)-(b)) >= 0)
+/* is b<=a<=c? */
+#if 0 /* see bug #10548 */
+#define TCP_SEQ_BETWEEN(a,b,c) ((c)-(b) >= (a)-(b))
+#endif
+#define TCP_SEQ_BETWEEN(a,b,c) (TCP_SEQ_GEQ(a,b) && TCP_SEQ_LEQ(a,c))
+#define TCP_FIN 0x01U
+#define TCP_SYN 0x02U
+#define TCP_RST 0x04U
+#define TCP_PSH 0x08U
+#define TCP_ACK 0x10U
+#define TCP_URG 0x20U
+#define TCP_ECE 0x40U
+#define TCP_CWR 0x80U
+
+#define TCP_FLAGS 0x3fU
+
+/* Length of the TCP header, excluding options. */
+#define TCP_HLEN 20
+
+#ifndef TCP_TMR_INTERVAL
+#define TCP_TMR_INTERVAL       250  /* The TCP timer interval in
+                                       milliseconds. */
+#endif /* TCP_TMR_INTERVAL */
+
+#ifndef TCP_FAST_INTERVAL
+#define TCP_FAST_INTERVAL      TCP_TMR_INTERVAL /* the fine grained timeout in
+                                       milliseconds */
+#endif /* TCP_FAST_INTERVAL */
+
+#ifndef TCP_SLOW_INTERVAL
+#define TCP_SLOW_INTERVAL      (2*TCP_TMR_INTERVAL)  /* the coarse grained timeout in
+                                       milliseconds */
+#endif /* TCP_SLOW_INTERVAL */
+
+#define TCP_FIN_WAIT_TIMEOUT 20000 /* milliseconds */
+#define TCP_SYN_RCVD_TIMEOUT 20000 /* milliseconds */
+
+#define TCP_OOSEQ_TIMEOUT        6 /* x RTO */
+
+#define TCP_MSL 60000  /* The maximum segment lifetime in microseconds */
+
+/*
+ * User-settable options (used with setsockopt).
+ */
+#define	TCP_NODELAY	   0x01	   /* don't delay send to coalesce packets */
+#define TCP_KEEPALIVE  0x02    /* send KEEPALIVE probes when idle for pcb->keepalive miliseconds */
+
+/* Keepalive values */
+#define  TCP_KEEPDEFAULT   7200000                       /* KEEPALIVE timer in miliseconds */
+#define  TCP_KEEPINTVL     75000                         /* Time between KEEPALIVE probes in miliseconds */
+#define  TCP_KEEPCNT       9                             /* Counter for KEEPALIVE probes */
+#define  TCP_MAXIDLE       TCP_KEEPCNT * TCP_KEEPINTVL   /* Maximum KEEPALIVE probe time */
+
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct tcp_hdr {
+  PACK_STRUCT_FIELD(u16_t src);
+  PACK_STRUCT_FIELD(u16_t dest);
+  PACK_STRUCT_FIELD(u32_t seqno);
+  PACK_STRUCT_FIELD(u32_t ackno);
+  PACK_STRUCT_FIELD(u16_t _hdrlen_rsvd_flags);
+  PACK_STRUCT_FIELD(u16_t wnd);
+  PACK_STRUCT_FIELD(u16_t chksum);
+  PACK_STRUCT_FIELD(u16_t urgp);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define TCPH_OFFSET(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) >> 8)
+#define TCPH_HDRLEN(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) >> 12)
+#define TCPH_FLAGS(phdr)  (ntohs((phdr)->_hdrlen_rsvd_flags) & TCP_FLAGS)
+
+#define TCPH_OFFSET_SET(phdr, offset) (phdr)->_hdrlen_rsvd_flags = htons(((offset) << 8) | TCPH_FLAGS(phdr))
+#define TCPH_HDRLEN_SET(phdr, len) (phdr)->_hdrlen_rsvd_flags = htons(((len) << 12) | TCPH_FLAGS(phdr))
+#define TCPH_FLAGS_SET(phdr, flags) (phdr)->_hdrlen_rsvd_flags = htons((ntohs((phdr)->_hdrlen_rsvd_flags) & ~TCP_FLAGS) | (flags))
+#define TCPH_SET_FLAG(phdr, flags ) (phdr)->_hdrlen_rsvd_flags = htons(ntohs((phdr)->_hdrlen_rsvd_flags) | (flags))
+#define TCPH_UNSET_FLAG(phdr, flags) (phdr)->_hdrlen_rsvd_flags = htons(ntohs((phdr)->_hdrlen_rsvd_flags) | (TCPH_FLAGS(phdr) & ~(flags)) )
+
+#define TCP_TCPLEN(seg) ((seg)->len + ((TCPH_FLAGS((seg)->tcphdr) & TCP_FIN || \
+          TCPH_FLAGS((seg)->tcphdr) & TCP_SYN)? 1: 0))
+
+enum tcp_state {
+  CLOSED      = 0,
+  LISTEN      = 1,
+  SYN_SENT    = 2,
+  SYN_RCVD    = 3,
+  ESTABLISHED = 4,
+  FIN_WAIT_1  = 5,
+  FIN_WAIT_2  = 6,
+  CLOSE_WAIT  = 7,
+  CLOSING     = 8,
+  LAST_ACK    = 9,
+  TIME_WAIT   = 10
+};
+
+/* the TCP protocol control block */
+struct tcp_pcb {
+/** common PCB members */
+  IP_PCB;
+/** protocol specific PCB members */
+  struct tcp_pcb *next; /* for the linked list */
+  enum tcp_state state; /* TCP state */
+  u8_t prio;
+  void *callback_arg;
+
+  u16_t local_port;
+  u16_t remote_port;
+  
+  u8_t flags;
+#define TF_ACK_DELAY (u8_t)0x01U   /* Delayed ACK. */
+#define TF_ACK_NOW   (u8_t)0x02U   /* Immediate ACK. */
+#define TF_INFR      (u8_t)0x04U   /* In fast recovery. */
+#define TF_RESET     (u8_t)0x08U   /* Connection was reset. */
+#define TF_CLOSED    (u8_t)0x10U   /* Connection was sucessfully closed. */
+#define TF_GOT_FIN   (u8_t)0x20U   /* Connection was closed by the remote end. */
+#define TF_NODELAY   (u8_t)0x40U   /* Disable Nagle algorithm */
+
+  /* receiver variables */
+  u32_t rcv_nxt;   /* next seqno expected */
+  u16_t rcv_wnd;   /* receiver window */
+  
+  /* Timers */
+  u32_t tmr;
+  u8_t polltmr, pollinterval;
+  
+  /* Retransmission timer. */
+  u16_t rtime;
+  
+  u16_t mss;   /* maximum segment size */
+  
+  /* RTT (round trip time) estimation variables */
+  u32_t rttest; /* RTT estimate in 500ms ticks */
+  u32_t rtseq;  /* sequence number being timed */
+  s16_t sa, sv; /* @todo document this */
+
+  u16_t rto;    /* retransmission time-out */
+  u8_t nrtx;    /* number of retransmissions */
+
+  /* fast retransmit/recovery */
+  u32_t lastack; /* Highest acknowledged seqno. */
+  u8_t dupacks;
+  
+  /* congestion avoidance/control variables */
+  u16_t cwnd;  
+  u16_t ssthresh;
+
+  /* sender variables */
+  u32_t snd_nxt,       /* next seqno to be sent */
+    snd_max,       /* Highest seqno sent. */
+    snd_wnd,       /* sender window */
+    snd_wl1, snd_wl2, /* Sequence and acknowledgement numbers of last
+       window update. */
+    snd_lbb;       /* Sequence number of next byte to be buffered. */
+
+  u16_t acked;
+  
+  u16_t snd_buf;   /* Available buffer space for sending (in bytes). */
+  u8_t snd_queuelen; /* Available buffer space for sending (in tcp_segs). */
+  
+  
+  /* These are ordered by sequence number: */
+  struct tcp_seg *unsent;   /* Unsent (queued) segments. */
+  struct tcp_seg *unacked;  /* Sent but unacknowledged segments. */
+#if TCP_QUEUE_OOSEQ  
+  struct tcp_seg *ooseq;    /* Received out of sequence segments. */
+#endif /* TCP_QUEUE_OOSEQ */
+
+#if LWIP_CALLBACK_API
+  /* Function to be called when more send buffer space is available. */
+  err_t (* sent)(void *arg, struct tcp_pcb *pcb, u16_t space);
+  
+  /* Function to be called when (in-sequence) data has arrived. */
+  err_t (* recv)(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err);
+
+  /* Function to be called when a connection has been set up. */
+  err_t (* connected)(void *arg, struct tcp_pcb *pcb, err_t err);
+
+  /* Function to call when a listener has been connected. */
+  err_t (* accept)(void *arg, struct tcp_pcb *newpcb, err_t err);
+
+  /* Function which is called periodically. */
+  err_t (* poll)(void *arg, struct tcp_pcb *pcb);
+
+  /* Function to be called whenever a fatal error occurs. */
+  void (* errf)(void *arg, err_t err);
+#endif /* LWIP_CALLBACK_API */
+
+  /* idle time before KEEPALIVE is sent */
+  u32_t keepalive;
+  
+  /* KEEPALIVE counter */
+  u8_t keep_cnt;
+};
+
+struct tcp_pcb_listen {  
+/* Common members of all PCB types */
+  IP_PCB;
+
+/* Protocol specific PCB members */
+  struct tcp_pcb_listen *next;   /* for the linked list */
+  
+  /* Even if state is obviously LISTEN this is here for
+   * field compatibility with tpc_pcb to which it is cast sometimes
+   * Until a cleaner solution emerges this is here.FIXME
+   */ 
+  enum tcp_state state;   /* TCP state */
+
+  u8_t prio;
+  void *callback_arg;
+  
+  u16_t local_port; 
+
+#if LWIP_CALLBACK_API
+  /* Function to call when a listener has been connected. */
+  err_t (* accept)(void *arg, struct tcp_pcb *newpcb, err_t err);
+#endif /* LWIP_CALLBACK_API */
+};
+
+#if LWIP_EVENT_API
+
+enum lwip_event {
+  LWIP_EVENT_ACCEPT,
+  LWIP_EVENT_SENT,
+  LWIP_EVENT_RECV,
+  LWIP_EVENT_CONNECTED,
+  LWIP_EVENT_POLL,
+  LWIP_EVENT_ERR
+};
+
+err_t lwip_tcp_event(void *arg, struct tcp_pcb *pcb,
+         enum lwip_event,
+         struct pbuf *p,
+         u16_t size,
+         err_t err);
+
+#define TCP_EVENT_ACCEPT(pcb,err,ret)    ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+                LWIP_EVENT_ACCEPT, NULL, 0, err)
+#define TCP_EVENT_SENT(pcb,space,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+                   LWIP_EVENT_SENT, NULL, space, ERR_OK)
+#define TCP_EVENT_RECV(pcb,p,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+                LWIP_EVENT_RECV, (p), 0, (err))
+#define TCP_EVENT_CONNECTED(pcb,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+                LWIP_EVENT_CONNECTED, NULL, 0, (err))
+#define TCP_EVENT_POLL(pcb,ret)       ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
+                LWIP_EVENT_POLL, NULL, 0, ERR_OK)
+#define TCP_EVENT_ERR(errf,arg,err)  lwip_tcp_event((arg), NULL, \
+                LWIP_EVENT_ERR, NULL, 0, (err))
+#else /* LWIP_EVENT_API */
+#define TCP_EVENT_ACCEPT(pcb,err,ret)     \
+                        if((pcb)->accept != NULL) \
+                        (ret = (pcb)->accept((pcb)->callback_arg,(pcb),(err)))
+#define TCP_EVENT_SENT(pcb,space,ret) \
+                        if((pcb)->sent != NULL) \
+                        (ret = (pcb)->sent((pcb)->callback_arg,(pcb),(space)))
+#define TCP_EVENT_RECV(pcb,p,err,ret) \
+                        if((pcb)->recv != NULL) \
+                        { ret = (pcb)->recv((pcb)->callback_arg,(pcb),(p),(err)); } else { \
+                          if (p) pbuf_free(p); }
+#define TCP_EVENT_CONNECTED(pcb,err,ret) \
+                        if((pcb)->connected != NULL) \
+                        (ret = (pcb)->connected((pcb)->callback_arg,(pcb),(err)))
+#define TCP_EVENT_POLL(pcb,ret) \
+                        if((pcb)->poll != NULL) \
+                        (ret = (pcb)->poll((pcb)->callback_arg,(pcb)))
+#define TCP_EVENT_ERR(errf,arg,err) \
+                        if((errf) != NULL) \
+                        (errf)((arg),(err))
+#endif /* LWIP_EVENT_API */
+
+/* This structure represents a TCP segment on the unsent and unacked queues */
+struct tcp_seg {
+  struct tcp_seg *next;    /* used when putting segements on a queue */
+  struct pbuf *p;          /* buffer containing data + TCP header */
+  void *dataptr;           /* pointer to the TCP data in the pbuf */
+  u16_t len;               /* the TCP length of this segment */
+  struct tcp_hdr *tcphdr;  /* the TCP header */
+};
+
+/* Internal functions and global variables: */
+struct tcp_pcb *tcp_pcb_copy(struct tcp_pcb *pcb);
+void tcp_pcb_purge(struct tcp_pcb *pcb);
+void tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb);
+
+u8_t tcp_segs_free(struct tcp_seg *seg);
+u8_t tcp_seg_free(struct tcp_seg *seg);
+struct tcp_seg *tcp_seg_copy(struct tcp_seg *seg);
+
+#define tcp_ack(pcb)     if((pcb)->flags & TF_ACK_DELAY) { \
+                            (pcb)->flags &= ~TF_ACK_DELAY; \
+                            (pcb)->flags |= TF_ACK_NOW; \
+                            tcp_output(pcb); \
+                         } else { \
+                            (pcb)->flags |= TF_ACK_DELAY; \
+                         }
+
+#define tcp_ack_now(pcb) (pcb)->flags |= TF_ACK_NOW; \
+                         tcp_output(pcb)
+
+err_t tcp_send_ctrl(struct tcp_pcb *pcb, u8_t flags);
+err_t tcp_enqueue(struct tcp_pcb *pcb, void *dataptr, u16_t len,
+    u8_t flags, u8_t copy,
+                u8_t *optdata, u8_t optlen);
+
+void tcp_rexmit_seg(struct tcp_pcb *pcb, struct tcp_seg *seg);
+
+void tcp_rst(u32_t seqno, u32_t ackno,
+       struct ip_addr *local_ip, struct ip_addr *remote_ip,
+       u16_t local_port, u16_t remote_port);
+
+u32_t tcp_next_iss(void);
+
+void tcp_keepalive(struct tcp_pcb *pcb);
+
+extern struct tcp_pcb *tcp_input_pcb;
+extern u32_t tcp_ticks;
+
+#if TCP_DEBUG || TCP_INPUT_DEBUG || TCP_OUTPUT_DEBUG
+void tcp_debug_print(struct tcp_hdr *tcphdr);
+void tcp_debug_print_flags(u8_t flags);
+void tcp_debug_print_state(enum tcp_state s);
+void tcp_debug_print_pcbs(void);
+s16_t tcp_pcbs_sane(void);
+#else
+#  define tcp_debug_print(tcphdr)
+#  define tcp_debug_print_flags(flags)
+#  define tcp_debug_print_state(s)
+#  define tcp_debug_print_pcbs()
+#  define tcp_pcbs_sane() 1
+#endif /* TCP_DEBUG */
+
+#if NO_SYS
+#define tcp_timer_needed()
+#else
+void tcp_timer_needed(void);
+#endif
+
+/* The TCP PCB lists. */
+union tcp_listen_pcbs_t { /* List of all TCP PCBs in LISTEN state. */
+	struct tcp_pcb_listen *listen_pcbs; 
+	struct tcp_pcb *pcbs;
+};
+extern union tcp_listen_pcbs_t tcp_listen_pcbs;
+extern struct tcp_pcb *tcp_active_pcbs;  /* List of all TCP PCBs that are in a
+              state in which they accept or send
+              data. */
+extern struct tcp_pcb *tcp_tw_pcbs;      /* List of all TCP PCBs in TIME-WAIT. */
+
+extern struct tcp_pcb *tcp_tmp_pcb;      /* Only used for temporary storage. */
+
+/* Axioms about the above lists:   
+   1) Every TCP PCB that is not CLOSED is in one of the lists.
+   2) A PCB is only in one of the lists.
+   3) All PCBs in the tcp_listen_pcbs list is in LISTEN state.
+   4) All PCBs in the tcp_tw_pcbs list is in TIME-WAIT state.
+*/
+
+/* Define two macros, TCP_REG and TCP_RMV that registers a TCP PCB
+   with a PCB list or removes a PCB from a list, respectively. */
+#if 0
+#define TCP_REG(pcbs, npcb) do {\
+                            LWIP_DEBUGF(TCP_DEBUG, ("TCP_REG %p local port %d\n", npcb, npcb->local_port)); \
+                            for(tcp_tmp_pcb = *pcbs; \
+          tcp_tmp_pcb != NULL; \
+        tcp_tmp_pcb = tcp_tmp_pcb->next) { \
+                                LWIP_ASSERT("TCP_REG: already registered\n", tcp_tmp_pcb != npcb); \
+                            } \
+                            LWIP_ASSERT("TCP_REG: pcb->state != CLOSED", npcb->state != CLOSED); \
+                            npcb->next = *pcbs; \
+                            LWIP_ASSERT("TCP_REG: npcb->next != npcb", npcb->next != npcb); \
+                            *(pcbs) = npcb; \
+                            LWIP_ASSERT("TCP_RMV: tcp_pcbs sane", tcp_pcbs_sane()); \
+              tcp_timer_needed(); \
+                            } while(0)
+#define TCP_RMV(pcbs, npcb) do { \
+                            LWIP_ASSERT("TCP_RMV: pcbs != NULL", *pcbs != NULL); \
+                            LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removing %p from %p\n", npcb, *pcbs)); \
+                            if(*pcbs == npcb) { \
+                               *pcbs = (*pcbs)->next; \
+                            } else for(tcp_tmp_pcb = *pcbs; tcp_tmp_pcb != NULL; tcp_tmp_pcb = tcp_tmp_pcb->next) { \
+                               if(tcp_tmp_pcb->next != NULL && tcp_tmp_pcb->next == npcb) { \
+                                  tcp_tmp_pcb->next = npcb->next; \
+                                  break; \
+                               } \
+                            } \
+                            npcb->next = NULL; \
+                            LWIP_ASSERT("TCP_RMV: tcp_pcbs sane", tcp_pcbs_sane()); \
+                            LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removed %p from %p\n", npcb, *pcbs)); \
+                            } while(0)
+
+#else /* LWIP_DEBUG */
+#define TCP_REG(pcbs, npcb) do { \
+                            npcb->next = *pcbs; \
+                            *(pcbs) = npcb; \
+              tcp_timer_needed(); \
+                            } while(0)
+#define TCP_RMV(pcbs, npcb) do { \
+                            if(*(pcbs) == npcb) { \
+                               (*(pcbs)) = (*pcbs)->next; \
+                            } else for(tcp_tmp_pcb = *pcbs; tcp_tmp_pcb != NULL; tcp_tmp_pcb = tcp_tmp_pcb->next) { \
+                               if(tcp_tmp_pcb->next != NULL && tcp_tmp_pcb->next == npcb) { \
+                                  tcp_tmp_pcb->next = npcb->next; \
+                                  break; \
+                               } \
+                            } \
+                            npcb->next = NULL; \
+                            } while(0)
+#endif /* LWIP_DEBUG */
+#endif /* __LWIP_TCP_H__ */
+
+
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/tcpip.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/tcpip.h
new file mode 100644
index 000000000..242664ef7
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/tcpip.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_TCPIP_H__
+#define __LWIP_TCPIP_H__
+
+#include "lwip/api_msg.h"
+#include "lwip/pbuf.h"
+
+void tcpip_init(void (* tcpip_init_done)(void *), void *arg);
+void tcpip_apimsg(struct api_msg *apimsg);
+err_t tcpip_input(struct pbuf *p, struct netif *inp);
+err_t tcpip_callback(void (*f)(void *ctx), void *ctx);
+
+void tcpip_tcp_timer_needed(void);
+
+enum tcpip_msg_type {
+  TCPIP_MSG_API,
+  TCPIP_MSG_INPUT,
+  TCPIP_MSG_CALLBACK
+};
+
+struct tcpip_msg {
+  enum tcpip_msg_type type;
+  sys_sem_t *sem;
+  union {
+    struct api_msg *apimsg;
+    struct {
+      struct pbuf *p;
+      struct netif *netif;
+    } inp;
+    struct {
+      void (*f)(void *ctx);
+      void *ctx;
+    } cb;
+  } msg;
+};
+
+
+#endif /* __LWIP_TCPIP_H__ */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/udp.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/udp.h
new file mode 100644
index 000000000..daaeca107
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/udp.h
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_UDP_H__
+#define __LWIP_UDP_H__
+
+#include "lwip/arch.h"
+
+#include "lwip/pbuf.h"
+#include "lwip/inet.h"
+#include "lwip/ip.h"
+
+#define UDP_HLEN 8
+
+struct udp_hdr {
+  PACK_STRUCT_FIELD(u16_t src);
+  PACK_STRUCT_FIELD(u16_t dest);  /* src/dest UDP ports */
+  PACK_STRUCT_FIELD(u16_t len);
+  PACK_STRUCT_FIELD(u16_t chksum);
+} PACK_STRUCT_STRUCT;
+
+#define UDP_FLAGS_NOCHKSUM 0x01U
+#define UDP_FLAGS_UDPLITE  0x02U
+#define UDP_FLAGS_CONNECTED  0x04U
+
+struct udp_pcb {
+/* Common members of all PCB types */
+  IP_PCB;
+
+/* Protocol specific PCB members */
+
+  struct udp_pcb *next;
+
+  u8_t flags;
+  u16_t local_port, remote_port;
+  
+  u16_t chksum_len;
+  
+  void (* recv)(void *arg, struct udp_pcb *pcb, struct pbuf *p,
+    struct ip_addr *addr, u16_t port);
+  void *recv_arg;  
+};
+
+/* The following functions is the application layer interface to the
+   UDP code. */
+struct udp_pcb * udp_new        (void);
+void             udp_remove     (struct udp_pcb *pcb);
+err_t            udp_bind       (struct udp_pcb *pcb, struct ip_addr *ipaddr,
+                 u16_t port);
+err_t            udp_connect    (struct udp_pcb *pcb, struct ip_addr *ipaddr,
+                 u16_t port);
+void             udp_disconnect    (struct udp_pcb *pcb);
+void             udp_recv       (struct udp_pcb *pcb,
+         void (* recv)(void *arg, struct udp_pcb *upcb,
+                 struct pbuf *p,
+                 struct ip_addr *addr,
+                 u16_t port),
+         void *recv_arg);
+err_t            udp_sendto     (struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *dst_ip, u16_t dst_port);
+err_t            udp_send       (struct udp_pcb *pcb, struct pbuf *p);
+
+#define          udp_flags(pcb)  ((pcb)->flags)
+#define          udp_setflags(pcb, f)  ((pcb)->flags = (f))
+
+/* The following functions are the lower layer interface to UDP. */
+void             udp_input      (struct pbuf *p, struct netif *inp);
+void             udp_init       (void);
+
+#if UDP_DEBUG
+void udp_debug_print(struct udp_hdr *udphdr);
+#else
+#define udp_debug_print(udphdr)
+#endif
+#endif /* __LWIP_UDP_H__ */
+
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/netif/etharp.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/netif/etharp.h
new file mode 100644
index 000000000..26fa3effb
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/netif/etharp.h
@@ -0,0 +1,126 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * Copyright (c) 2003-2004 Leon Woestenberg 
+ * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+#ifndef __NETIF_ETHARP_H__
+#define __NETIF_ETHARP_H__
+
+#ifndef ETH_PAD_SIZE
+#define ETH_PAD_SIZE 0
+#endif
+
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+#include "lwip/ip.h"
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct eth_addr {
+  PACK_STRUCT_FIELD(u8_t addr[6]);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct eth_hdr {
+#if ETH_PAD_SIZE
+  PACK_STRUCT_FIELD(u8_t padding[ETH_PAD_SIZE]);
+#endif
+  PACK_STRUCT_FIELD(struct eth_addr dest);
+  PACK_STRUCT_FIELD(struct eth_addr src);
+  PACK_STRUCT_FIELD(u16_t type);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+/** the ARP message */
+struct etharp_hdr {
+  PACK_STRUCT_FIELD(struct eth_hdr ethhdr);
+  PACK_STRUCT_FIELD(u16_t hwtype);
+  PACK_STRUCT_FIELD(u16_t proto);
+  PACK_STRUCT_FIELD(u16_t _hwlen_protolen);
+  PACK_STRUCT_FIELD(u16_t opcode);
+  PACK_STRUCT_FIELD(struct eth_addr shwaddr);
+  PACK_STRUCT_FIELD(struct ip_addr2 sipaddr);
+  PACK_STRUCT_FIELD(struct eth_addr dhwaddr);
+  PACK_STRUCT_FIELD(struct ip_addr2 dipaddr);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+PACK_STRUCT_BEGIN
+struct ethip_hdr {
+  PACK_STRUCT_FIELD(struct eth_hdr eth);
+  PACK_STRUCT_FIELD(struct ip_hdr ip);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+/** 5 seconds period */
+#define ARP_TMR_INTERVAL 5000
+
+#define ETHTYPE_ARP 0x0806
+#define ETHTYPE_IP  0x0800
+
+void etharp_init(void);
+void etharp_tmr(void);
+void etharp_ip_input(struct netif *netif, struct pbuf *p);
+void etharp_arp_input(struct netif *netif, struct eth_addr *ethaddr,
+         struct pbuf *p);
+err_t etharp_output(struct netif *netif, struct ip_addr *ipaddr,
+         struct pbuf *q);
+err_t etharp_query(struct netif *netif, struct ip_addr *ipaddr, struct pbuf *q);
+err_t etharp_request(struct netif *netif, struct ip_addr *ipaddr);
+
+#endif /* __NETIF_ARP_H__ */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/netif/loopif.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/netif/loopif.h
new file mode 100644
index 000000000..7fd548733
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/netif/loopif.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __NETIF_LOOPIF_H__
+#define __NETIF_LOOPIF_H__
+
+#include "lwip/netif.h"
+
+err_t loopif_init(struct netif *netif);
+
+#endif /* __NETIF_LOOPIF_H__ */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/netif/slipif.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/netif/slipif.h
new file mode 100644
index 000000000..d9060fc97
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/include/netif/slipif.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2001, Swedish Institute of Computer Science.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. Neither the name of the Institute nor the names of its contributors 
+ *    may be used to endorse or promote products derived from this software 
+ *    without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
+ * SUCH DAMAGE. 
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __NETIF_SLIPIF_H__
+#define __NETIF_SLIPIF_H__
+
+#include "lwip/netif.h"
+
+err_t slipif_init(struct netif * netif);
+ 
+#endif 
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/FILES b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/FILES
new file mode 100644
index 000000000..825d40715
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/FILES
@@ -0,0 +1,27 @@
+This directory contains generic network interface device drivers that
+do not contain any hardware or architecture specific code. The files
+are:
+
+etharp.c
+          Implements the ARP (Address Resolution Protocol) over
+          Ethernet. The code in this file should be used together with
+          Ethernet device drivers. Note that this module has been
+          largely made Ethernet independent so you should be able to
+          adapt this for other link layers (such as Firewire).
+
+ethernetif.c
+          An example of how an Ethernet device driver could look. This
+          file can be used as a "skeleton" for developing new Ethernet
+          network device drivers. It uses the etharp.c ARP code.
+
+loopif.c
+          An example network interface that shows how a "loopback"
+          interface would work. This is not really intended for actual
+          use, but as a very basic example of how initialization and
+          output functions work.
+
+slipif.c
+          A generic implementation of the SLIP (Serial Line IP)
+          protocol. It requires a sio (serial I/O) module to work.
+	  
+ppp/      Point-to-Point Protocol stack
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/etharp.c b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/etharp.c
new file mode 100644
index 000000000..76a8ac4bf
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/etharp.c
@@ -0,0 +1,831 @@
+/**
+ * @file
+ * Address Resolution Protocol module for IP over Ethernet
+ *
+ * Functionally, ARP is divided into two parts. The first maps an IP address
+ * to a physical address when sending a packet, and the second part answers
+ * requests from other machines for our physical address.
+ *
+ * This implementation complies with RFC 826 (Ethernet ARP). It supports
+ * Gratuitious ARP from RFC3220 (IP Mobility Support for IPv4) section 4.6
+ * if an interface calls etharp_query(our_netif, its_ip_addr, NULL) upon
+ * address change.
+ */
+
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * Copyright (c) 2003-2004 Leon Woestenberg 
+ * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ */
+
+#include "lwip/opt.h"
+#include "lwip/inet.h"
+#include "netif/etharp.h"
+#include "lwip/ip.h"
+#include "lwip/stats.h"
+
+/* ARP needs to inform DHCP of any ARP replies? */
+#if (LWIP_DHCP && DHCP_DOES_ARP_CHECK)
+#  include "lwip/dhcp.h"
+#endif
+
+/** the time an ARP entry stays valid after its last update,
+ * (240 * 5) seconds = 20 minutes.
+ */
+#define ARP_MAXAGE 240
+/** the time an ARP entry stays pending after first request,
+ * (2 * 5) seconds = 10 seconds.
+ * 
+ * @internal Keep this number at least 2, otherwise it might
+ * run out instantly if the timeout occurs directly after a request.
+ */
+#define ARP_MAXPENDING 2
+
+#define HWTYPE_ETHERNET 1
+
+/** ARP message types */
+#define ARP_REQUEST 1
+#define ARP_REPLY 2
+
+#define ARPH_HWLEN(hdr) (ntohs((hdr)->_hwlen_protolen) >> 8)
+#define ARPH_PROTOLEN(hdr) (ntohs((hdr)->_hwlen_protolen) & 0xff)
+
+#define ARPH_HWLEN_SET(hdr, len) (hdr)->_hwlen_protolen = htons(ARPH_PROTOLEN(hdr) | ((len) << 8))
+#define ARPH_PROTOLEN_SET(hdr, len) (hdr)->_hwlen_protolen = htons((len) | (ARPH_HWLEN(hdr) << 8))
+
+enum etharp_state {
+  ETHARP_STATE_EMPTY,
+  ETHARP_STATE_PENDING,
+  ETHARP_STATE_STABLE,
+  /** @internal transitional state used in etharp_tmr() for convenience*/
+  ETHARP_STATE_EXPIRED
+};
+
+struct etharp_entry {
+#if ARP_QUEUEING
+  /** 
+   * Pointer to queue of pending outgoing packets on this ARP entry.
+   */
+   struct pbuf *p;
+#endif
+  struct ip_addr ipaddr;
+  struct eth_addr ethaddr;
+  enum etharp_state state;
+  u8_t ctime;
+};
+
+static const struct eth_addr ethbroadcast = {{0xff,0xff,0xff,0xff,0xff,0xff}};
+static struct etharp_entry arp_table[ARP_TABLE_SIZE];
+
+/**
+ * Try hard to create a new entry - we want the IP address to appear in
+ * the cache (even if this means removing an active entry or so). */
+#define ETHARP_TRY_HARD 1
+
+static s8_t find_entry(struct ip_addr *ipaddr, u8_t flags);
+static err_t update_arp_entry(struct netif *netif, struct ip_addr *ipaddr, struct eth_addr *ethaddr, u8_t flags);
+/**
+ * Initializes ARP module.
+ */
+void
+etharp_init(void)
+{
+  u8_t i;
+  /* clear ARP entries */
+  for(i = 0; i < ARP_TABLE_SIZE; ++i) {
+    arp_table[i].state = ETHARP_STATE_EMPTY;
+#if ARP_QUEUEING
+    arp_table[i].p = NULL;
+#endif
+    arp_table[i].ctime = 0;
+  }
+}
+
+/**
+ * Clears expired entries in the ARP table.
+ *
+ * This function should be called every ETHARP_TMR_INTERVAL microseconds (5 seconds),
+ * in order to expire entries in the ARP table.
+ */
+void
+etharp_tmr(void)
+{
+  u8_t i;
+
+  LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer\n"));
+  /* remove expired entries from the ARP table */
+  for (i = 0; i < ARP_TABLE_SIZE; ++i) {
+    arp_table[i].ctime++;
+    /* stable entry? */
+    if ((arp_table[i].state == ETHARP_STATE_STABLE) &&
+         /* entry has become old? */
+        (arp_table[i].ctime >= ARP_MAXAGE)) {
+      LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: expired stable entry %"U16_F".\n", (u16_t)i));
+      arp_table[i].state = ETHARP_STATE_EXPIRED;
+    /* pending entry? */
+    } else if (arp_table[i].state == ETHARP_STATE_PENDING) {
+      /* entry unresolved/pending for too long? */
+      if (arp_table[i].ctime >= ARP_MAXPENDING) {
+        LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: expired pending entry %"U16_F".\n", (u16_t)i));
+        arp_table[i].state = ETHARP_STATE_EXPIRED;
+#if ARP_QUEUEING
+      } else if (arp_table[i].p != NULL) {
+        /* resend an ARP query here */
+#endif
+      }
+    }
+    /* clean up entries that have just been expired */
+    if (arp_table[i].state == ETHARP_STATE_EXPIRED) {
+#if ARP_QUEUEING
+      /* and empty packet queue */
+      if (arp_table[i].p != NULL) {
+        /* remove all queued packets */
+        LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: freeing entry %"U16_F", packet queue %p.\n", (u16_t)i, (void *)(arp_table[i].p)));
+        pbuf_free(arp_table[i].p);
+        arp_table[i].p = NULL;
+      }
+#endif
+      /* recycle entry for re-use */      
+      arp_table[i].state = ETHARP_STATE_EMPTY;
+    }
+  }
+}
+
+/**
+ * Search the ARP table for a matching or new entry.
+ * 
+ * If an IP address is given, return a pending or stable ARP entry that matches
+ * the address. If no match is found, create a new entry with this address set,
+ * but in state ETHARP_EMPTY. The caller must check and possibly change the
+ * state of the returned entry.
+ * 
+ * If ipaddr is NULL, return a initialized new entry in state ETHARP_EMPTY.
+ * 
+ * In all cases, attempt to create new entries from an empty entry. If no
+ * empty entries are available and ETHARP_TRY_HARD flag is set, recycle
+ * old entries. Heuristic choose the least important entry for recycling.
+ *
+ * @param ipaddr IP address to find in ARP cache, or to add if not found.
+ * @param flags
+ * - ETHARP_TRY_HARD: Try hard to create a entry by allowing recycling of
+ * active (stable or pending) entries.
+ *  
+ * @return The ARP entry index that matched or is created, ERR_MEM if no
+ * entry is found or could be recycled.
+ */
+static s8_t find_entry(struct ip_addr *ipaddr, u8_t flags)
+{
+  s8_t old_pending = ARP_TABLE_SIZE, old_stable = ARP_TABLE_SIZE;
+  s8_t empty = ARP_TABLE_SIZE;
+  u8_t i = 0, age_pending = 0, age_stable = 0;
+#if ARP_QUEUEING
+  /* oldest entry with packets on queue */
+  s8_t old_queue = ARP_TABLE_SIZE;
+  /* its age */
+  u8_t age_queue = 0;
+#endif
+
+  /**
+   * a) do a search through the cache, remember candidates
+   * b) select candidate entry
+   * c) create new entry
+   */
+
+  /* a) in a single search sweep, do all of this
+   * 1) remember the first empty entry (if any)
+   * 2) remember the oldest stable entry (if any)
+   * 3) remember the oldest pending entry without queued packets (if any)
+   * 4) remember the oldest pending entry with queued packets (if any)
+   * 5) search for a matching IP entry, either pending or stable
+   *    until 5 matches, or all entries are searched for.
+   */
+
+  for (i = 0; i < ARP_TABLE_SIZE; ++i) {
+    /* no empty entry found yet and now we do find one? */
+    if ((empty == ARP_TABLE_SIZE) && (arp_table[i].state == ETHARP_STATE_EMPTY)) {
+      LWIP_DEBUGF(ETHARP_DEBUG, ("find_entry: found empty entry %"U16_F"\n", (u16_t)i));
+      /* remember first empty entry */
+      empty = i;
+    }
+    /* pending entry? */
+    else if (arp_table[i].state == ETHARP_STATE_PENDING) {
+      /* if given, does IP address match IP address in ARP entry? */
+      if (ipaddr && ip_addr_cmp(ipaddr, &arp_table[i].ipaddr)) {
+        LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: found matching pending entry %"U16_F"\n", (u16_t)i));
+        /* found exact IP address match, simply bail out */
+        return i;
+#if ARP_QUEUEING
+      /* pending with queued packets? */
+      } else if (arp_table[i].p != NULL) {
+        if (arp_table[i].ctime >= age_queue) {
+          old_queue = i;
+          age_queue = arp_table[i].ctime;
+        }
+#endif
+      /* pending without queued packets? */
+      } else {
+        if (arp_table[i].ctime >= age_pending) {
+          old_pending = i;
+          age_pending = arp_table[i].ctime;
+        }
+      }        
+    }
+    /* stable entry? */
+    else if (arp_table[i].state == ETHARP_STATE_STABLE) {
+      /* if given, does IP address match IP address in ARP entry? */
+      if (ipaddr && ip_addr_cmp(ipaddr, &arp_table[i].ipaddr)) {
+        LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: found matching stable entry %"U16_F"\n", (u16_t)i));
+        /* found exact IP address match, simply bail out */
+        return i;
+      /* remember entry with oldest stable entry in oldest, its age in maxtime */
+      } else if (arp_table[i].ctime >= age_stable) {
+        old_stable = i;
+        age_stable = arp_table[i].ctime;
+      }
+    }
+  }
+  /* { we have no match } => try to create a new entry */
+   
+  /* no empty entry found and not allowed to recycle? */
+  if ((empty == ARP_TABLE_SIZE) && ((flags & ETHARP_TRY_HARD) == 0))
+  {
+  	return (s8_t)ERR_MEM;
+  }
+  
+  /* b) choose the least destructive entry to recycle:
+   * 1) empty entry
+   * 2) oldest stable entry
+   * 3) oldest pending entry without queued packets
+   * 4) oldest pending entry without queued packets
+   * 
+   * { ETHARP_TRY_HARD is set at this point }
+   */ 
+
+  /* 1) empty entry available? */
+  if (empty < ARP_TABLE_SIZE) {
+    i = empty;
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: selecting empty entry %"U16_F"\n", (u16_t)i));
+  }
+  /* 2) found recyclable stable entry? */
+  else if (old_stable < ARP_TABLE_SIZE) {
+    /* recycle oldest stable*/
+    i = old_stable;
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: selecting oldest stable entry %"U16_F"\n", (u16_t)i));
+#if ARP_QUEUEING
+    /* no queued packets should exist on stable entries */
+    LWIP_ASSERT("arp_table[i].p == NULL", arp_table[i].p == NULL);
+#endif
+  /* 3) found recyclable pending entry without queued packets? */
+  } else if (old_pending < ARP_TABLE_SIZE) {
+    /* recycle oldest pending */
+    i = old_pending;
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: selecting oldest pending entry %"U16_F" (without queue)\n", (u16_t)i));
+#if ARP_QUEUEING
+  /* 4) found recyclable pending entry with queued packets? */
+  } else if (old_queue < ARP_TABLE_SIZE) {
+    /* recycle oldest pending */
+    i = old_queue;
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: selecting oldest pending entry %"U16_F", freeing packet queue %p\n", (u16_t)i, (void *)(arp_table[i].p)));
+    pbuf_free(arp_table[i].p);
+    arp_table[i].p = NULL;
+#endif
+    /* no empty or recyclable entries found */
+  } else {
+    return (s8_t)ERR_MEM;
+  }
+
+  /* { empty or recyclable entry found } */
+  LWIP_ASSERT("i < ARP_TABLE_SIZE", i < ARP_TABLE_SIZE);
+
+  /* recycle entry (no-op for an already empty entry) */
+  arp_table[i].state = ETHARP_STATE_EMPTY;
+
+  /* IP address given? */
+  if (ipaddr != NULL) {
+    /* set IP address */
+    ip_addr_set(&arp_table[i].ipaddr, ipaddr);
+  }
+  arp_table[i].ctime = 0;
+  return (err_t)i;
+}
+
+/**
+ * Update (or insert) a IP/MAC address pair in the ARP cache.
+ *
+ * If a pending entry is resolved, any queued packets will be sent
+ * at this point.
+ * 
+ * @param ipaddr IP address of the inserted ARP entry.
+ * @param ethaddr Ethernet address of the inserted ARP entry.
+ * @param flags Defines behaviour:
+ * - ETHARP_TRY_HARD Allows ARP to insert this as a new item. If not specified,
+ * only existing ARP entries will be updated.
+ *
+ * @return
+ * - ERR_OK Succesfully updated ARP cache.
+ * - ERR_MEM If we could not add a new ARP entry when ETHARP_TRY_HARD was set.
+ * - ERR_ARG Non-unicast address given, those will not appear in ARP cache.
+ *
+ * @see pbuf_free()
+ */
+static err_t
+update_arp_entry(struct netif *netif, struct ip_addr *ipaddr, struct eth_addr *ethaddr, u8_t flags)
+{
+  s8_t i, k;
+  LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 3, ("update_arp_entry()\n"));
+  LWIP_ASSERT("netif->hwaddr_len != 0", netif->hwaddr_len != 0);
+  LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: %"U16_F".%"U16_F".%"U16_F".%"U16_F" - %02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F"\n",
+                                        ip4_addr1(ipaddr), ip4_addr2(ipaddr), ip4_addr3(ipaddr), ip4_addr4(ipaddr), 
+                                        ethaddr->addr[0], ethaddr->addr[1], ethaddr->addr[2],
+                                        ethaddr->addr[3], ethaddr->addr[4], ethaddr->addr[5]));
+  /* non-unicast address? */
+  if (ip_addr_isany(ipaddr) ||
+      ip_addr_isbroadcast(ipaddr, netif) ||
+      ip_addr_ismulticast(ipaddr)) {
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: will not add non-unicast IP address to ARP cache\n"));
+    return ERR_ARG;
+  }
+  /* find or create ARP entry */
+  i = find_entry(ipaddr, flags);
+  /* bail out if no entry could be found */
+  if (i < 0) return (err_t)i;
+  
+  /* mark it stable */
+  arp_table[i].state = ETHARP_STATE_STABLE;
+
+  LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: updating stable entry %"S16_F"\n", (s16_t)i));
+  /* update address */
+  for (k = 0; k < netif->hwaddr_len; ++k) {
+    arp_table[i].ethaddr.addr[k] = ethaddr->addr[k];
+  }
+  /* reset time stamp */
+  arp_table[i].ctime = 0;
+/* this is where we will send out queued packets! */
+#if ARP_QUEUEING
+  while (arp_table[i].p != NULL) {
+    /* get the first packet on the queue */
+    struct pbuf *p = arp_table[i].p;
+    /* Ethernet header */
+    struct eth_hdr *ethhdr = p->payload;
+    /* remember (and reference) remainder of queue */
+    /* note: this will also terminate the p pbuf chain */
+    arp_table[i].p = pbuf_dequeue(p);
+    /* fill-in Ethernet header */
+    for (k = 0; k < netif->hwaddr_len; ++k) {
+      ethhdr->dest.addr[k] = ethaddr->addr[k];
+      ethhdr->src.addr[k] = netif->hwaddr[k];
+    }
+    ethhdr->type = htons(ETHTYPE_IP);
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: sending queued IP packet %p.\n", (void *)p));
+    /* send the queued IP packet */
+    netif->linkoutput(netif, p);
+    /* free the queued IP packet */
+    pbuf_free(p);
+  }
+#endif
+  return ERR_OK;
+}
+
+/**
+ * Updates the ARP table using the given IP packet.
+ *
+ * Uses the incoming IP packet's source address to update the
+ * ARP cache for the local network. The function does not alter
+ * or free the packet. This function must be called before the
+ * packet p is passed to the IP layer.
+ *
+ * @param netif The lwIP network interface on which the IP packet pbuf arrived.
+ * @param pbuf The IP packet that arrived on netif.
+ *
+ * @return NULL
+ *
+ * @see pbuf_free()
+ */
+void
+etharp_ip_input(struct netif *netif, struct pbuf *p)
+{
+  struct ethip_hdr *hdr;
+  LWIP_ASSERT("netif != NULL", netif != NULL);
+  /* Only insert an entry if the source IP address of the
+     incoming IP packet comes from a host on the local network. */
+  hdr = p->payload;
+  /* source is not on the local network? */
+  if (!ip_addr_netcmp(&(hdr->ip.src), &(netif->ip_addr), &(netif->netmask))) {
+    /* do nothing */
+    return;
+  }
+
+  LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_ip_input: updating ETHARP table.\n"));
+  /* update ARP table */
+  /* @todo We could use ETHARP_TRY_HARD if we think we are going to talk
+   * back soon (for example, if the destination IP address is ours. */
+  update_arp_entry(netif, &(hdr->ip.src), &(hdr->eth.src), 0);
+}
+
+
+/**
+ * Responds to ARP requests to us. Upon ARP replies to us, add entry to cache  
+ * send out queued IP packets. Updates cache with snooped address pairs.
+ *
+ * Should be called for incoming ARP packets. The pbuf in the argument
+ * is freed by this function.
+ *
+ * @param netif The lwIP network interface on which the ARP packet pbuf arrived.
+ * @param pbuf The ARP packet that arrived on netif. Is freed by this function.
+ * @param ethaddr Ethernet address of netif.
+ *
+ * @return NULL
+ *
+ * @see pbuf_free()
+ */
+void
+etharp_arp_input(struct netif *netif, struct eth_addr *ethaddr, struct pbuf *p)
+{
+  struct etharp_hdr *hdr;
+  /* these are aligned properly, whereas the ARP header fields might not be */
+  struct ip_addr sipaddr, dipaddr;
+  u8_t i;
+  u8_t for_us;
+
+  LWIP_ASSERT("netif != NULL", netif != NULL);
+  
+  /* drop short ARP packets */
+  if (p->tot_len < sizeof(struct etharp_hdr)) {
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 1, ("etharp_arp_input: packet dropped, too short (%"S16_F"/%"S16_F")\n", p->tot_len, sizeof(struct etharp_hdr)));
+    pbuf_free(p);
+    return;
+  }
+
+  hdr = p->payload;
+ 
+  /* get aligned copies of addresses */
+  *(struct ip_addr2 *)&sipaddr = hdr->sipaddr;
+  *(struct ip_addr2 *)&dipaddr = hdr->dipaddr;
+
+  /* this interface is not configured? */
+  if (netif->ip_addr.addr == 0) {
+    for_us = 0;
+  } else {
+    /* ARP packet directed to us? */
+    for_us = ip_addr_cmp(&dipaddr, &(netif->ip_addr));
+  }
+
+  /* ARP message directed to us? */
+  if (for_us) {
+    /* add IP address in ARP cache; assume requester wants to talk to us.
+     * can result in directly sending the queued packets for this host. */
+    update_arp_entry(netif, &sipaddr, &(hdr->shwaddr), ETHARP_TRY_HARD);
+  /* ARP message not directed to us? */
+  } else {
+    /* update the source IP address in the cache, if present */
+    update_arp_entry(netif, &sipaddr, &(hdr->shwaddr), 0);
+  }
+
+  /* now act on the message itself */
+  switch (htons(hdr->opcode)) {
+  /* ARP request? */
+  case ARP_REQUEST:
+    /* ARP request. If it asked for our address, we send out a
+     * reply. In any case, we time-stamp any existing ARP entry,
+     * and possiby send out an IP packet that was queued on it. */
+
+    LWIP_DEBUGF (ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: incoming ARP request\n"));
+    /* ARP request for our address? */
+    if (for_us) {
+
+      LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: replying to ARP request for our IP address\n"));
+      /* re-use pbuf to send ARP reply */
+      hdr->opcode = htons(ARP_REPLY);
+
+      hdr->dipaddr = hdr->sipaddr;
+      hdr->sipaddr = *(struct ip_addr2 *)&netif->ip_addr;
+
+      for(i = 0; i < netif->hwaddr_len; ++i) {
+        hdr->dhwaddr.addr[i] = hdr->shwaddr.addr[i];
+        hdr->shwaddr.addr[i] = ethaddr->addr[i];
+        hdr->ethhdr.dest.addr[i] = hdr->dhwaddr.addr[i];
+        hdr->ethhdr.src.addr[i] = ethaddr->addr[i];
+      }
+
+      hdr->hwtype = htons(HWTYPE_ETHERNET);
+      ARPH_HWLEN_SET(hdr, netif->hwaddr_len);
+
+      hdr->proto = htons(ETHTYPE_IP);
+      ARPH_PROTOLEN_SET(hdr, sizeof(struct ip_addr));
+
+      hdr->ethhdr.type = htons(ETHTYPE_ARP);
+      /* return ARP reply */
+      netif->linkoutput(netif, p);
+    /* we are not configured? */
+    } else if (netif->ip_addr.addr == 0) {
+      /* { for_us == 0 and netif->ip_addr.addr == 0 } */
+      LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: we are unconfigured, ARP request ignored.\n"));
+    /* request was not directed to us */
+    } else {
+      /* { for_us == 0 and netif->ip_addr.addr != 0 } */
+      LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: ARP request was not for us.\n"));
+    }
+    break;
+  case ARP_REPLY:
+    /* ARP reply. We already updated the ARP cache earlier. */
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: incoming ARP reply\n"));
+#if (LWIP_DHCP && DHCP_DOES_ARP_CHECK)
+    /* DHCP wants to know about ARP replies from any host with an
+     * IP address also offered to us by the DHCP server. We do not
+     * want to take a duplicate IP address on a single network.
+     * @todo How should we handle redundant (fail-over) interfaces?
+     * */
+    dhcp_arp_reply(netif, &sipaddr);
+#endif
+    break;
+  default:
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: ARP unknown opcode type %"S16_F"\n", htons(hdr->opcode)));
+    break;
+  }
+  /* free ARP packet */
+  pbuf_free(p);
+}
+
+/**
+ * Resolve and fill-in Ethernet address header for outgoing packet.
+ *
+ * For IP multicast and broadcast, corresponding Ethernet addresses
+ * are selected and the packet is transmitted on the link.
+ *
+ * For unicast addresses, the packet is submitted to etharp_query(). In
+ * case the IP address is outside the local network, the IP address of
+ * the gateway is used.
+ *
+ * @param netif The lwIP network interface which the IP packet will be sent on.
+ * @param ipaddr The IP address of the packet destination.
+ * @param pbuf The pbuf(s) containing the IP packet to be sent.
+ *
+ * @return
+ * - ERR_RTE No route to destination (no gateway to external networks),
+ * or the return type of either etharp_query() or netif->linkoutput().
+ */
+err_t
+etharp_output(struct netif *netif, struct ip_addr *ipaddr, struct pbuf *q)
+{
+  struct eth_addr *dest, *srcaddr, mcastaddr;
+  struct eth_hdr *ethhdr;
+  u8_t i;
+
+  /* make room for Ethernet header - should not fail */
+  if (pbuf_header(q, sizeof(struct eth_hdr)) != 0) {
+    /* bail out */
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 2, ("etharp_output: could not allocate room for header.\n"));
+    LINK_STATS_INC(link.lenerr);
+    return ERR_BUF;
+  }
+
+  /* assume unresolved Ethernet address */
+  dest = NULL;
+  /* Determine on destination hardware address. Broadcasts and multicasts
+   * are special, other IP addresses are looked up in the ARP table. */
+
+  /* broadcast destination IP address? */
+  if (ip_addr_isbroadcast(ipaddr, netif)) {
+    /* broadcast on Ethernet also */
+    dest = (struct eth_addr *)ðbroadcast;
+  /* multicast destination IP address? */
+  } else if (ip_addr_ismulticast(ipaddr)) {
+    /* Hash IP multicast address to MAC address.*/
+    mcastaddr.addr[0] = 0x01;
+    mcastaddr.addr[1] = 0x00;
+    mcastaddr.addr[2] = 0x5e;
+    mcastaddr.addr[3] = ip4_addr2(ipaddr) & 0x7f;
+    mcastaddr.addr[4] = ip4_addr3(ipaddr);
+    mcastaddr.addr[5] = ip4_addr4(ipaddr);
+    /* destination Ethernet address is multicast */
+    dest = &mcastaddr;
+  /* unicast destination IP address? */
+  } else {
+    /* outside local network? */
+    if (!ip_addr_netcmp(ipaddr, &(netif->ip_addr), &(netif->netmask))) {
+      /* interface has default gateway? */
+      if (netif->gw.addr != 0) {
+        /* send to hardware address of default gateway IP address */
+        ipaddr = &(netif->gw);
+      /* no default gateway available */
+      } else {
+        /* no route to destination error (default gateway missing) */
+        return ERR_RTE;
+      }
+    }
+    /* queue on destination Ethernet address belonging to ipaddr */
+    return etharp_query(netif, ipaddr, q);
+  }
+
+  /* continuation for multicast/broadcast destinations */
+  /* obtain source Ethernet address of the given interface */
+  srcaddr = (struct eth_addr *)netif->hwaddr;
+  ethhdr = q->payload;
+  for (i = 0; i < netif->hwaddr_len; i++) {
+    ethhdr->dest.addr[i] = dest->addr[i];
+    ethhdr->src.addr[i] = srcaddr->addr[i];
+  }
+  ethhdr->type = htons(ETHTYPE_IP);
+  /* send packet directly on the link */
+  return netif->linkoutput(netif, q);
+}
+
+/**
+ * Send an ARP request for the given IP address and/or queue a packet.
+ *
+ * If the IP address was not yet in the cache, a pending ARP cache entry
+ * is added and an ARP request is sent for the given address. The packet
+ * is queued on this entry.
+ *
+ * If the IP address was already pending in the cache, a new ARP request
+ * is sent for the given address. The packet is queued on this entry.
+ *
+ * If the IP address was already stable in the cache, and a packet is
+ * given, it is directly sent and no ARP request is sent out. 
+ * 
+ * If the IP address was already stable in the cache, and no packet is
+ * given, an ARP request is sent out.
+ * 
+ * @param netif The lwIP network interface on which ipaddr
+ * must be queried for.
+ * @param ipaddr The IP address to be resolved.
+ * @param q If non-NULL, a pbuf that must be delivered to the IP address.
+ * q is not freed by this function.
+ *
+ * @return
+ * - ERR_BUF Could not make room for Ethernet header.
+ * - ERR_MEM Hardware address unknown, and no more ARP entries available
+ *   to query for address or queue the packet.
+ * - ERR_MEM Could not queue packet due to memory shortage.
+ * - ERR_RTE No route to destination (no gateway to external networks).
+ * - ERR_ARG Non-unicast address given, those will not appear in ARP cache.
+ *
+ */
+err_t etharp_query(struct netif *netif, struct ip_addr *ipaddr, struct pbuf *q)
+{
+  struct eth_addr * srcaddr = (struct eth_addr *)netif->hwaddr;
+  err_t result = ERR_MEM;
+  s8_t i; /* ARP entry index */
+  u8_t k; /* Ethernet address octet index */
+
+  /* non-unicast address? */
+  if (ip_addr_isbroadcast(ipaddr, netif) ||
+      ip_addr_ismulticast(ipaddr) ||
+      ip_addr_isany(ipaddr)) {
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: will not add non-unicast IP address to ARP cache\n"));
+    return ERR_ARG;
+  }
+
+  /* find entry in ARP cache, ask to create entry if queueing packet */
+  i = find_entry(ipaddr, ETHARP_TRY_HARD);
+
+  /* could not find or create entry? */
+  if (i < 0)
+  {
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: could not create ARP entry\n"));
+    if (q) LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: packet dropped\n"));
+    return (err_t)i;
+  }
+
+  /* mark a fresh entry as pending (we just sent a request) */
+  if (arp_table[i].state == ETHARP_STATE_EMPTY) {
+    arp_table[i].state = ETHARP_STATE_PENDING;
+  }
+
+  /* { i is either a STABLE or (new or existing) PENDING entry } */
+  LWIP_ASSERT("arp_table[i].state == PENDING or STABLE",
+  ((arp_table[i].state == ETHARP_STATE_PENDING) ||
+   (arp_table[i].state == ETHARP_STATE_STABLE)));
+
+  /* do we have a pending entry? or an implicit query request? */
+  if ((arp_table[i].state == ETHARP_STATE_PENDING) || (q == NULL)) {
+    /* try to resolve it; send out ARP request */
+    result = etharp_request(netif, ipaddr);
+  }
+  
+  /* packet given? */
+  if (q != NULL) {
+    /* stable entry? */
+    if (arp_table[i].state == ETHARP_STATE_STABLE) {
+      /* we have a valid IP->Ethernet address mapping,
+       * fill in the Ethernet header for the outgoing packet */
+      struct eth_hdr *ethhdr = q->payload;
+      for(k = 0; k < netif->hwaddr_len; k++) {
+        ethhdr->dest.addr[k] = arp_table[i].ethaddr.addr[k];
+        ethhdr->src.addr[k]  = srcaddr->addr[k];
+      }
+      ethhdr->type = htons(ETHTYPE_IP);
+      LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: sending packet %p\n", (void *)q));
+      /* send the packet */
+      result = netif->linkoutput(netif, q);
+    /* pending entry? (either just created or already pending */
+    } else if (arp_table[i].state == ETHARP_STATE_PENDING) {
+#if ARP_QUEUEING /* queue the given q packet */
+      struct pbuf *p;
+      /* copy any PBUF_REF referenced payloads into PBUF_RAM */
+      /* (the caller of lwIP assumes the referenced payload can be
+       * freed after it returns from the lwIP call that brought us here) */
+      p = pbuf_take(q);
+      /* packet could be taken over? */
+      if (p != NULL) {
+        /* queue packet ... */
+        if (arp_table[i].p == NULL) {
+        	/* ... in the empty queue */
+        	pbuf_ref(p);
+        	arp_table[i].p = p;
+#if 0 /* multi-packet-queueing disabled, see bug #11400 */
+        } else {
+        	/* ... at tail of non-empty queue */
+          pbuf_queue(arp_table[i].p, p);
+#endif
+        }
+        LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: queued packet %p on ARP entry %"S16_F"\n", (void *)q, (s16_t)i));
+        result = ERR_OK;
+      } else {
+        LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: could not queue a copy of PBUF_REF packet %p (out of memory)\n", (void *)q));
+        /* { result == ERR_MEM } through initialization */
+      }
+#else /* ARP_QUEUEING == 0 */
+      /* q && state == PENDING && ARP_QUEUEING == 0 => result = ERR_MEM */
+      /* { result == ERR_MEM } through initialization */
+      LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: Ethernet destination address unknown, queueing disabled, packet %p dropped\n", (void *)q));
+#endif
+    }
+  }
+  return result;
+}
+
+err_t etharp_request(struct netif *netif, struct ip_addr *ipaddr)
+{
+  struct pbuf *p;
+  struct eth_addr * srcaddr = (struct eth_addr *)netif->hwaddr;
+  err_t result = ERR_OK;
+  u8_t k; /* ARP entry index */
+
+  /* allocate a pbuf for the outgoing ARP request packet */
+  p = pbuf_alloc(PBUF_LINK, sizeof(struct etharp_hdr), PBUF_RAM);
+  /* could allocate a pbuf for an ARP request? */
+  if (p != NULL) {
+    struct etharp_hdr *hdr = p->payload;
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_request: sending ARP request.\n"));
+    hdr->opcode = htons(ARP_REQUEST);
+    for (k = 0; k < netif->hwaddr_len; k++)
+    {
+      hdr->shwaddr.addr[k] = srcaddr->addr[k];
+      /* the hardware address is what we ask for, in
+       * a request it is a don't-care value, we use zeroes */
+      hdr->dhwaddr.addr[k] = 0x00;
+    }
+    hdr->dipaddr = *(struct ip_addr2 *)ipaddr;
+    hdr->sipaddr = *(struct ip_addr2 *)&netif->ip_addr;
+
+    hdr->hwtype = htons(HWTYPE_ETHERNET);
+    ARPH_HWLEN_SET(hdr, netif->hwaddr_len);
+
+    hdr->proto = htons(ETHTYPE_IP);
+    ARPH_PROTOLEN_SET(hdr, sizeof(struct ip_addr));
+    for (k = 0; k < netif->hwaddr_len; ++k)
+    {
+      /* broadcast to all network interfaces on the local network */
+      hdr->ethhdr.dest.addr[k] = 0xff;
+      hdr->ethhdr.src.addr[k] = srcaddr->addr[k];
+    }
+    hdr->ethhdr.type = htons(ETHTYPE_ARP);
+    /* send ARP query */
+    result = netif->linkoutput(netif, p);
+    /* free ARP query packet */
+    pbuf_free(p);
+    p = NULL;
+  /* could not allocate pbuf for ARP request */
+  } else {
+    result = ERR_MEM;
+    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 2, ("etharp_request: could not allocate pbuf for ARP request.\n"));
+  }
+  return result;
+}
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ethernetif.c b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ethernetif.c
new file mode 100644
index 000000000..3d93fe1e8
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ethernetif.c
@@ -0,0 +1,306 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+/*
+ * This file is a skeleton for developing Ethernet network interface
+ * drivers for lwIP. Add code to the low_level functions and do a
+ * search-and-replace for the word "ethernetif" to replace it with
+ * something that better describes your network interface.
+ */
+
+#include "lwip/opt.h"
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/pbuf.h"
+#include "lwip/sys.h"
+#include 
+
+#include "netif/etharp.h"
+
+/* Define those to better describe your network interface. */
+#define IFNAME0 'e'
+#define IFNAME1 'n'
+
+struct ethernetif {
+  struct eth_addr *ethaddr;
+  /* Add whatever per-interface state that is needed here. */
+};
+
+static const struct eth_addr ethbroadcast = {{0xff,0xff,0xff,0xff,0xff,0xff}};
+
+/* Forward declarations. */
+static void  ethernetif_input(struct netif *netif);
+static err_t ethernetif_output(struct netif *netif, struct pbuf *p,
+             struct ip_addr *ipaddr);
+
+static void
+low_level_init(struct netif *netif)
+{
+  struct ethernetif *ethernetif = netif->state;
+  
+  /* set MAC hardware address length */
+  netif->hwaddr_len = 6;
+
+  /* set MAC hardware address */
+  netif->hwaddr[0] = ;
+  ...
+  netif->hwaddr[5] = ;
+
+  /* maximum transfer unit */
+  netif->mtu = 1500;
+  
+  /* broadcast capability */
+  netif->flags = NETIF_FLAG_BROADCAST;
+ 
+  /* Do whatever else is needed to initialize interface. */  
+}
+
+/*
+ * low_level_output():
+ *
+ * Should do the actual transmission of the packet. The packet is
+ * contained in the pbuf that is passed to the function. This pbuf
+ * might be chained.
+ *
+ */
+
+static err_t
+low_level_output(struct netif *netif, struct pbuf *p)
+{
+  struct ethernetif *ethernetif = netif->state;
+  struct pbuf *q;
+
+  initiate transfer();
+  
+#if ETH_PAD_SIZE
+  pbuf_header(p, -ETH_PAD_SIZE);			/* drop the padding word */
+#endif
+
+  for(q = p; q != NULL; q = q->next) {
+    /* Send the data from the pbuf to the interface, one pbuf at a
+       time. The size of the data in each pbuf is kept in the ->len
+       variable. */
+    send data from(q->payload, q->len);
+  }
+
+  signal that packet should be sent();
+
+#if ETH_PAD_SIZE
+  pbuf_header(p, ETH_PAD_SIZE);			/* reclaim the padding word */
+#endif
+  
+#if LINK_STATS
+  lwip_stats.link.xmit++;
+#endif /* LINK_STATS */      
+
+  return ERR_OK;
+}
+
+/*
+ * low_level_input():
+ *
+ * Should allocate a pbuf and transfer the bytes of the incoming
+ * packet from the interface into the pbuf.
+ *
+ */
+
+static struct pbuf *
+low_level_input(struct netif *netif)
+{
+  struct ethernetif *ethernetif = netif->state;
+  struct pbuf *p, *q;
+  u16_t len;
+
+  /* Obtain the size of the packet and put it into the "len"
+     variable. */
+  len = ;
+
+#if ETH_PAD_SIZE
+  len += ETH_PAD_SIZE;						/* allow room for Ethernet padding */
+#endif
+
+  /* We allocate a pbuf chain of pbufs from the pool. */
+  p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
+  
+  if (p != NULL) {
+
+#if ETH_PAD_SIZE
+    pbuf_header(p, -ETH_PAD_SIZE);			/* drop the padding word */
+#endif
+
+    /* We iterate over the pbuf chain until we have read the entire
+     * packet into the pbuf. */
+    for(q = p; q != NULL; q = q->next) {
+      /* Read enough bytes to fill this pbuf in the chain. The
+       * available data in the pbuf is given by the q->len
+       * variable. */
+      read data into(q->payload, q->len);
+    }
+    acknowledge that packet has been read();
+
+#if ETH_PAD_SIZE
+    pbuf_header(p, ETH_PAD_SIZE);			/* reclaim the padding word */
+#endif
+
+#if LINK_STATS
+    lwip_stats.link.recv++;
+#endif /* LINK_STATS */      
+  } else {
+    drop packet();
+#if LINK_STATS
+    lwip_stats.link.memerr++;
+    lwip_stats.link.drop++;
+#endif /* LINK_STATS */      
+  }
+
+  return p;  
+}
+
+/*
+ * ethernetif_output():
+ *
+ * This function is called by the TCP/IP stack when an IP packet
+ * should be sent. It calls the function called low_level_output() to
+ * do the actual transmission of the packet.
+ *
+ */
+
+static err_t
+ethernetif_output(struct netif *netif, struct pbuf *p,
+      struct ip_addr *ipaddr)
+{
+  
+ /* resolve hardware address, then send (or queue) packet */
+  return etharp_output(netif, ipaddr, p);
+ 
+}
+
+/*
+ * ethernetif_input():
+ *
+ * This function should be called when a packet is ready to be read
+ * from the interface. It uses the function low_level_input() that
+ * should handle the actual reception of bytes from the network
+ * interface.
+ *
+ */
+
+static void
+ethernetif_input(struct netif *netif)
+{
+  struct ethernetif *ethernetif;
+  struct eth_hdr *ethhdr;
+  struct pbuf *p;
+
+  ethernetif = netif->state;
+  
+  /* move received packet into a new pbuf */
+  p = low_level_input(netif);
+  /* no packet could be read, silently ignore this */
+  if (p == NULL) return;
+  /* points to packet payload, which starts with an Ethernet header */
+  ethhdr = p->payload;
+
+#if LINK_STATS
+  lwip_stats.link.recv++;
+#endif /* LINK_STATS */
+
+  ethhdr = p->payload;
+    
+  switch (htons(ethhdr->type)) {
+  /* IP packet? */
+  case ETHTYPE_IP:
+    /* update ARP table */
+    etharp_ip_input(netif, p);
+    /* skip Ethernet header */
+    pbuf_header(p, -sizeof(struct eth_hdr));
+    /* pass to network layer */
+    netif->input(p, netif);
+    break;
+      
+    case ETHTYPE_ARP:
+      /* pass p to ARP module  */
+      etharp_arp_input(netif, ethernetif->ethaddr, p);
+      break;
+    default:
+      pbuf_free(p);
+      p = NULL;
+      break;
+  }
+}
+
+static void
+arp_timer(void *arg)
+{
+  etharp_tmr();
+  sys_timeout(ARP_TMR_INTERVAL, arp_timer, NULL);
+}
+
+/*
+ * ethernetif_init():
+ *
+ * Should be called at the beginning of the program to set up the
+ * network interface. It calls the function low_level_init() to do the
+ * actual setup of the hardware.
+ *
+ */
+
+err_t
+ethernetif_init(struct netif *netif)
+{
+  struct ethernetif *ethernetif;
+    
+  ethernetif = mem_malloc(sizeof(struct ethernetif));
+  
+  if (ethernetif == NULL)
+  {
+  	LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_init: out of memory\n"));
+  	return ERR_MEM;
+  }
+  
+  netif->state = ethernetif;
+  netif->name[0] = IFNAME0;
+  netif->name[1] = IFNAME1;
+  netif->output = ethernetif_output;
+  netif->linkoutput = low_level_output;
+  
+  ethernetif->ethaddr = (struct eth_addr *)&(netif->hwaddr[0]);
+  
+  low_level_init(netif);
+
+  etharp_init();
+
+  sys_timeout(ARP_TMR_INTERVAL, arp_timer, NULL);
+
+  return ERR_OK;
+}
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/loopif.c b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/loopif.c
new file mode 100644
index 000000000..cd523fb03
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/loopif.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#include "lwip/opt.h"
+
+#if LWIP_HAVE_LOOPIF
+
+#include "netif/loopif.h"
+#include "lwip/mem.h"
+
+#if defined(LWIP_DEBUG) && defined(LWIP_TCPDUMP)
+#include "netif/tcpdump.h"
+#endif /* LWIP_DEBUG && LWIP_TCPDUMP */
+
+#include "lwip/tcp.h"
+#include "lwip/ip.h"
+
+static void
+loopif_input( void * arg )
+{
+	struct netif *netif = (struct netif *)( ((void **)arg)[ 0 ] );
+	struct pbuf *r = (struct pbuf *)( ((void **)arg)[ 1 ] );
+
+	mem_free( arg );
+	netif -> input( r, netif );
+}
+
+static err_t
+loopif_output(struct netif *netif, struct pbuf *p,
+       struct ip_addr *ipaddr)
+{
+  struct pbuf *q, *r;
+  u8_t *ptr;
+  void **arg;
+
+#if defined(LWIP_DEBUG) && defined(LWIP_TCPDUMP)
+  tcpdump(p);
+#endif /* LWIP_DEBUG && LWIP_TCPDUMP */
+  
+  r = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM);
+  if (r != NULL) {
+    ptr = r->payload;
+    
+    for(q = p; q != NULL; q = q->next) {
+      memcpy(ptr, q->payload, q->len);
+      ptr += q->len;
+    }
+
+    arg = mem_malloc( sizeof( void *[2]));
+	if( NULL == arg ) {
+		return ERR_MEM;
+	}
+	
+	arg[0] = netif;
+	arg[1] = r;
+	/**
+	 * workaround (patch #1779) to try to prevent bug #2595:
+	 * When connecting to "localhost" with the loopif interface,
+	 * tcp_output doesn't get the opportunity to finnish sending the
+	 * segment before tcp_process gets it, resulting in tcp_process
+	 * referencing pcb->unacked-> which still is NULL.
+	 * 
+	 * TODO: Is there still a race condition here? Leon
+	 */
+	sys_timeout( 1, loopif_input, arg );
+	
+    return ERR_OK;    
+  }
+  return ERR_MEM;
+}
+
+err_t
+loopif_init(struct netif *netif)
+{
+  netif->name[0] = 'l';
+  netif->name[1] = 'o';
+#if 0 /** TODO: I think this should be enabled, or not? Leon */
+  netif->input = loopif_input;
+#endif
+  netif->output = loopif_output;
+  return ERR_OK;
+}
+
+#endif /* LWIP_HAVE_LOOPIF */
+
+
+
+
+
+
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/auth.c b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/auth.c
new file mode 100644
index 000000000..0786a2e81
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/auth.c
@@ -0,0 +1,927 @@
+/*****************************************************************************
+* auth.c - Network Authentication and Phase Control program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* Copyright (c) 1997 by Global Election Systems Inc.  All rights reserved.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-08 Guy Lancaster , Global Election Systems Inc.
+*   Ported from public pppd code.
+*****************************************************************************/
+/*
+ * auth.c - PPP authentication and phase control.
+ *
+ * Copyright (c) 1993 The Australian National University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the Australian National University.  The name of the University
+ * may not be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include "ppp.h"
+#if PPP_SUPPORT > 0
+#include "fsm.h"
+#include "lcp.h"
+#include "pap.h"
+#include "chap.h"
+#include "auth.h"
+#include "ipcp.h"
+
+#if CBCP_SUPPORT > 0
+#include "cbcp.h"
+#endif
+
+#include "pppdebug.h"
+
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+
+/* Bits in auth_pending[] */
+#define PAP_WITHPEER    1
+#define PAP_PEER    2
+#define CHAP_WITHPEER   4
+#define CHAP_PEER   8
+
+
+                                                                    
+/************************/
+/*** LOCAL DATA TYPES ***/
+/************************/
+/* Used for storing a sequence of words.  Usually malloced. */
+struct wordlist {
+    struct wordlist *next;
+    char        word[1];
+};
+
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+extern char *crypt (const char *, const char *);
+
+/* Prototypes for procedures local to this file. */
+
+static void network_phase (int);
+static void check_idle (void *);
+static void connect_time_expired (void *);
+#if 0
+static int  login (char *, char *, char **, int *);
+#endif
+static void logout (void);
+static int  null_login (int);
+static int  get_pap_passwd (int, char *, char *);
+static int  have_pap_secret (void);
+static int  have_chap_secret (char *, char *, u32_t);
+static int  ip_addr_check (u32_t, struct wordlist *);
+#if 0 /* PAP_SUPPORT > 0 || CHAP_SUPPORT > 0 */
+static void set_allowed_addrs(int unit, struct wordlist *addrs);
+static void free_wordlist (struct wordlist *);
+#endif
+#if CBCP_SUPPORT > 0
+static void callback_phase (int);
+#endif
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+#if PAP_SUPPORT > 0 || CHAP_SUPPORT > 0
+/* The name by which the peer authenticated itself to us. */
+static char peer_authname[MAXNAMELEN];
+#endif
+
+/* Records which authentication operations haven't completed yet. */
+static int auth_pending[NUM_PPP];
+
+/* Set if we have successfully called login() */
+static int logged_in;
+
+/* Set if we have run the /etc/ppp/auth-up script. */
+static int did_authup;
+
+/* List of addresses which the peer may use. */
+static struct wordlist *addresses[NUM_PPP];
+
+/* Number of network protocols which we have opened. */
+static int num_np_open;
+
+/* Number of network protocols which have come up. */
+static int num_np_up;
+
+#if PAP_SUPPORT > 0 || CHAP_SUPPORT > 0
+/* Set if we got the contents of passwd[] from the pap-secrets file. */
+static int passwd_from_file;
+#endif
+
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ * An Open on LCP has requested a change from Dead to Establish phase.
+ * Do what's necessary to bring the physical layer up.
+ */
+void link_required(int unit)
+{
+    AUTHDEBUG((LOG_INFO, "link_required: %d\n", unit));
+}
+
+/*
+ * LCP has terminated the link; go to the Dead phase and take the
+ * physical layer down.
+ */
+void link_terminated(int unit)
+{
+    AUTHDEBUG((LOG_INFO, "link_terminated: %d\n", unit));
+    
+    if (lcp_phase[unit] == PHASE_DEAD)
+        return;
+    if (logged_in)
+        logout();
+    lcp_phase[unit] = PHASE_DEAD;
+    AUTHDEBUG((LOG_NOTICE, "Connection terminated.\n"));
+	pppMainWakeup(unit);
+}
+
+/*
+ * LCP has gone down; it will either die or try to re-establish.
+ */
+void link_down(int unit)
+{
+    int i;
+    struct protent *protp;
+    
+    AUTHDEBUG((LOG_INFO, "link_down: %d\n", unit));
+    if (did_authup) {
+        /* XXX Do link down processing. */
+        did_authup = 0;
+    }
+    for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) {
+        if (!protp->enabled_flag)
+            continue;
+        if (protp->protocol != PPP_LCP && protp->lowerdown != NULL)
+            (*protp->lowerdown)(unit);
+        if (protp->protocol < 0xC000 && protp->close != NULL)
+            (*protp->close)(unit, "LCP down");
+    }
+    num_np_open = 0;
+    num_np_up = 0;
+    if (lcp_phase[unit] != PHASE_DEAD)
+        lcp_phase[unit] = PHASE_TERMINATE;
+	pppMainWakeup(unit);
+}
+
+/*
+ * The link is established.
+ * Proceed to the Dead, Authenticate or Network phase as appropriate.
+ */
+void link_established(int unit)
+{
+    int auth;
+    int i;
+    struct protent *protp;
+    lcp_options *wo = &lcp_wantoptions[unit];
+    lcp_options *go = &lcp_gotoptions[unit];
+#if PAP_SUPPORT > 0 || CHAP_SUPPORT > 0
+    lcp_options *ho = &lcp_hisoptions[unit];
+#endif
+    
+    AUTHDEBUG((LOG_INFO, "link_established: %d\n", unit));
+    /*
+     * Tell higher-level protocols that LCP is up.
+     */
+    for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i)
+        if (protp->protocol != PPP_LCP && protp->enabled_flag
+                && protp->lowerup != NULL)
+            (*protp->lowerup)(unit);
+    
+    if (ppp_settings.auth_required && !(go->neg_chap || go->neg_upap)) {
+        /*
+         * We wanted the peer to authenticate itself, and it refused:
+         * treat it as though it authenticated with PAP using a username
+         * of "" and a password of "".  If that's not OK, boot it out.
+         */
+        if (!wo->neg_upap || !null_login(unit)) {
+            AUTHDEBUG((LOG_WARNING, "peer refused to authenticate\n"));
+            lcp_close(unit, "peer refused to authenticate");
+            return;
+        }
+    }
+    
+    lcp_phase[unit] = PHASE_AUTHENTICATE;
+    auth = 0;
+#if CHAP_SUPPORT > 0
+    if (go->neg_chap) {
+        ChapAuthPeer(unit, ppp_settings.our_name, go->chap_mdtype);
+        auth |= CHAP_PEER;
+    } 
+#endif
+#if PAP_SUPPORT > 0 && CHAP_SUPPORT > 0
+    else
+#endif
+#if PAP_SUPPORT > 0
+    if (go->neg_upap) {
+        upap_authpeer(unit);
+        auth |= PAP_PEER;
+    }
+#endif
+#if CHAP_SUPPORT > 0
+    if (ho->neg_chap) {
+        ChapAuthWithPeer(unit, ppp_settings.user, ho->chap_mdtype);
+        auth |= CHAP_WITHPEER;
+    }
+#endif
+#if PAP_SUPPORT > 0 && CHAP_SUPPORT > 0
+    else
+#endif
+#if PAP_SUPPORT > 0
+    if (ho->neg_upap) {
+        if (ppp_settings.passwd[0] == 0) {
+            passwd_from_file = 1;
+            if (!get_pap_passwd(unit, ppp_settings.user, ppp_settings.passwd))
+                AUTHDEBUG((LOG_ERR, "No secret found for PAP login\n"));
+        }
+        upap_authwithpeer(unit, ppp_settings.user, ppp_settings.passwd);
+        auth |= PAP_WITHPEER;
+    }
+#endif
+    auth_pending[unit] = auth;
+    
+    if (!auth)
+        network_phase(unit);
+}
+
+
+/*
+ * The peer has failed to authenticate himself using `protocol'.
+ */
+void auth_peer_fail(int unit, u16_t protocol)
+{
+    AUTHDEBUG((LOG_INFO, "auth_peer_fail: %d proto=%X\n", unit, protocol));
+    /*
+     * Authentication failure: take the link down
+     */
+    lcp_close(unit, "Authentication failed");
+}
+
+
+#if PAP_SUPPORT > 0 || CHAP_SUPPORT > 0
+/*
+ * The peer has been successfully authenticated using `protocol'.
+ */
+void auth_peer_success(int unit, u16_t protocol, char *name, int namelen)
+{
+    int pbit;
+    
+    AUTHDEBUG((LOG_INFO, "auth_peer_success: %d proto=%X\n", unit, protocol));
+    switch (protocol) {
+    case PPP_CHAP:
+        pbit = CHAP_PEER;
+        break;
+    case PPP_PAP:
+        pbit = PAP_PEER;
+        break;
+    default:
+        AUTHDEBUG((LOG_WARNING, "auth_peer_success: unknown protocol %x\n",
+               protocol));
+        return;
+    }
+    
+    /*
+     * Save the authenticated name of the peer for later.
+     */
+    if (namelen > sizeof(peer_authname) - 1)
+        namelen = sizeof(peer_authname) - 1;
+    BCOPY(name, peer_authname, namelen);
+    peer_authname[namelen] = 0;
+    
+    /*
+     * If there is no more authentication still to be done,
+     * proceed to the network (or callback) phase.
+     */
+    if ((auth_pending[unit] &= ~pbit) == 0)
+        network_phase(unit);
+}
+
+/*
+ * We have failed to authenticate ourselves to the peer using `protocol'.
+ */
+void auth_withpeer_fail(int unit, u16_t protocol)
+{
+    int errCode = PPPERR_AUTHFAIL;
+    
+    AUTHDEBUG((LOG_INFO, "auth_withpeer_fail: %d proto=%X\n", unit, protocol));
+    if (passwd_from_file)
+        BZERO(ppp_settings.passwd, MAXSECRETLEN);
+    /* 
+     * XXX Warning: the unit number indicates the interface which is
+     * not necessarily the PPP connection.  It works here as long
+     * as we are only supporting PPP interfaces.
+     */
+    pppIOCtl(unit, PPPCTLS_ERRCODE, &errCode);
+
+    /*
+     * We've failed to authenticate ourselves to our peer.
+     * He'll probably take the link down, and there's not much
+     * we can do except wait for that.
+     */
+}
+
+/*
+ * We have successfully authenticated ourselves with the peer using `protocol'.
+ */
+void auth_withpeer_success(int unit, u16_t protocol)
+{
+    int pbit;
+    
+    AUTHDEBUG((LOG_INFO, "auth_withpeer_success: %d proto=%X\n", unit, protocol));
+    switch (protocol) {
+    case PPP_CHAP:
+        pbit = CHAP_WITHPEER;
+        break;
+    case PPP_PAP:
+        if (passwd_from_file)
+            BZERO(ppp_settings.passwd, MAXSECRETLEN);
+        pbit = PAP_WITHPEER;
+        break;
+    default:
+        AUTHDEBUG((LOG_WARNING, "auth_peer_success: unknown protocol %x\n",
+               protocol));
+        pbit = 0;
+    }
+    
+    /*
+     * If there is no more authentication still being done,
+     * proceed to the network (or callback) phase.
+     */
+    if ((auth_pending[unit] &= ~pbit) == 0)
+        network_phase(unit);
+}
+#endif
+
+
+/*
+ * np_up - a network protocol has come up.
+ */
+void np_up(int unit, u16_t proto)
+{
+    AUTHDEBUG((LOG_INFO, "np_up: %d proto=%X\n", unit, proto));
+    if (num_np_up == 0) {
+	AUTHDEBUG((LOG_INFO, "np_up: maxconnect=%d idle_time_limit=%d\n",ppp_settings.maxconnect,ppp_settings.idle_time_limit));
+        /*
+         * At this point we consider that the link has come up successfully.
+         */
+        if (ppp_settings.idle_time_limit > 0)
+            TIMEOUT(check_idle, NULL, ppp_settings.idle_time_limit);
+        
+        /*
+         * Set a timeout to close the connection once the maximum
+         * connect time has expired.
+         */
+        if (ppp_settings.maxconnect > 0)
+            TIMEOUT(connect_time_expired, 0, ppp_settings.maxconnect);
+    }
+    ++num_np_up;
+}
+
+/*
+ * np_down - a network protocol has gone down.
+ */
+void np_down(int unit, u16_t proto)
+{
+    AUTHDEBUG((LOG_INFO, "np_down: %d proto=%X\n", unit, proto));
+    if (--num_np_up == 0 && ppp_settings.idle_time_limit > 0) {
+        UNTIMEOUT(check_idle, NULL);
+    }
+}
+
+/*
+ * np_finished - a network protocol has finished using the link.
+ */
+void np_finished(int unit, u16_t proto)
+{
+    AUTHDEBUG((LOG_INFO, "np_finished: %d proto=%X\n", unit, proto));
+    if (--num_np_open <= 0) {
+        /* no further use for the link: shut up shop. */
+        lcp_close(0, "No network protocols running");
+    }
+}
+
+/*
+ * auth_reset - called when LCP is starting negotiations to recheck
+ * authentication options, i.e. whether we have appropriate secrets
+ * to use for authenticating ourselves and/or the peer.
+ */
+void auth_reset(int unit)
+{
+    lcp_options *go = &lcp_gotoptions[unit];
+    lcp_options *ao = &lcp_allowoptions[0];
+    ipcp_options *ipwo = &ipcp_wantoptions[0];
+    u32_t remote;
+    
+    AUTHDEBUG((LOG_INFO, "auth_reset: %d\n", unit));
+    ao->neg_upap = !ppp_settings.refuse_pap && (ppp_settings.passwd[0] != 0 || get_pap_passwd(unit, NULL, NULL));
+    ao->neg_chap = !ppp_settings.refuse_chap && ppp_settings.passwd[0] != 0 /*have_chap_secret(ppp_settings.user, ppp_settings.remote_name, (u32_t)0)*/;
+    
+    if (go->neg_upap && !have_pap_secret())
+        go->neg_upap = 0;
+    if (go->neg_chap) {
+        remote = ipwo->accept_remote? 0: ipwo->hisaddr;
+        if (!have_chap_secret(ppp_settings.remote_name, ppp_settings.our_name, remote))
+            go->neg_chap = 0;
+    }
+}
+
+
+#if PAP_SUPPORT > 0
+/*
+ * check_passwd - Check the user name and passwd against the PAP secrets
+ * file.  If requested, also check against the system password database,
+ * and login the user if OK.
+ *
+ * returns:
+ *  UPAP_AUTHNAK: Authentication failed.
+ *  UPAP_AUTHACK: Authentication succeeded.
+ * In either case, msg points to an appropriate message.
+ */
+int check_passwd(
+	int unit,
+	char *auser,
+	int userlen,
+	char *apasswd,
+	int passwdlen,
+	char **msg,
+	int *msglen
+)
+{
+#if 1
+	*msg = (char *) 0;
+	return UPAP_AUTHACK;     /* XXX Assume all entries OK. */
+#else
+    int ret = 0;
+    struct wordlist *addrs = NULL;
+    char passwd[256], user[256];
+    char secret[MAXWORDLEN];
+    static u_short attempts = 0;
+    
+    /*
+     * Make copies of apasswd and auser, then null-terminate them.
+     */
+    BCOPY(apasswd, passwd, passwdlen);
+    passwd[passwdlen] = '\0';
+    BCOPY(auser, user, userlen);
+    user[userlen] = '\0';
+    *msg = (char *) 0;
+
+    /* XXX Validate user name and password. */
+    ret = UPAP_AUTHACK;     /* XXX Assume all entries OK. */
+        
+    if (ret == UPAP_AUTHNAK) {
+        if (*msg == (char *) 0)
+            *msg = "Login incorrect";
+        *msglen = strlen(*msg);
+        /*
+         * Frustrate passwd stealer programs.
+         * Allow 10 tries, but start backing off after 3 (stolen from login).
+         * On 10'th, drop the connection.
+         */
+        if (attempts++ >= 10) {
+            AUTHDEBUG((LOG_WARNING, "%d LOGIN FAILURES BY %s\n", attempts, user));
+            /*ppp_panic("Excess Bad Logins");*/
+        }
+        if (attempts > 3) {
+            sys_msleep((attempts - 3) * 5);
+        }
+        if (addrs != NULL) {
+            free_wordlist(addrs);
+        }
+    } else {
+        attempts = 0;           /* Reset count */
+        if (*msg == (char *) 0)
+            *msg = "Login ok";
+        *msglen = strlen(*msg);
+        set_allowed_addrs(unit, addrs);
+    }
+    
+    BZERO(passwd, sizeof(passwd));
+    BZERO(secret, sizeof(secret));
+    
+    return ret;
+#endif
+}
+#endif
+
+
+/*
+ * auth_ip_addr - check whether the peer is authorized to use
+ * a given IP address.  Returns 1 if authorized, 0 otherwise.
+ */
+int auth_ip_addr(int unit, u32_t addr)
+{
+    return ip_addr_check(addr, addresses[unit]);
+}
+
+/*
+ * bad_ip_adrs - return 1 if the IP address is one we don't want
+ * to use, such as an address in the loopback net or a multicast address.
+ * addr is in network byte order.
+ */
+int bad_ip_adrs(u32_t addr)
+{
+    addr = ntohl(addr);
+    return (addr >> IN_CLASSA_NSHIFT) == IN_LOOPBACKNET
+        || IN_MULTICAST(addr) || IN_BADCLASS(addr);
+}
+
+
+#if CHAP_SUPPORT > 0
+/*
+ * get_secret - open the CHAP secret file and return the secret
+ * for authenticating the given client on the given server.
+ * (We could be either client or server).
+ */
+int get_secret(
+    int unit,
+    char *client,
+    char *server,
+    char *secret,
+    int *secret_len,
+    int save_addrs
+)
+{
+#if 1
+    int len;
+    struct wordlist *addrs;
+    
+    addrs = NULL;
+
+    if(!client || !client[0] || strcmp(client, ppp_settings.user)) {
+	return 0;
+    }
+
+    len = strlen(ppp_settings.passwd);
+    if (len > MAXSECRETLEN) {
+        AUTHDEBUG((LOG_ERR, "Secret for %s on %s is too long\n", client, server));
+        len = MAXSECRETLEN;
+    }
+    BCOPY(ppp_settings.passwd, secret, len);
+    *secret_len = len;
+    
+    return 1;
+#else
+    int ret = 0, len;
+    struct wordlist *addrs;
+    char secbuf[MAXWORDLEN];
+    
+    addrs = NULL;
+    secbuf[0] = 0;
+
+    /* XXX Find secret. */  
+    if (ret < 0)
+        return 0;
+    
+    if (save_addrs)
+        set_allowed_addrs(unit, addrs);
+    
+    len = strlen(secbuf);
+    if (len > MAXSECRETLEN) {
+        AUTHDEBUG((LOG_ERR, "Secret for %s on %s is too long\n", client, server));
+        len = MAXSECRETLEN;
+    }
+    BCOPY(secbuf, secret, len);
+    BZERO(secbuf, sizeof(secbuf));
+    *secret_len = len;
+    
+    return 1;
+#endif
+}
+#endif
+
+
+#if 0 /* UNUSED */
+/*
+ * auth_check_options - called to check authentication options.
+ */
+void auth_check_options(void)
+{
+    lcp_options *wo = &lcp_wantoptions[0];
+    int can_auth;
+    ipcp_options *ipwo = &ipcp_wantoptions[0];
+    u32_t remote;
+    
+    /* Default our_name to hostname, and user to our_name */
+    if (ppp_settings.our_name[0] == 0 || ppp_settings.usehostname)
+        strcpy(ppp_settings.our_name, ppp_settings.hostname);
+    if (ppp_settings.user[0] == 0)
+        strcpy(ppp_settings.user, ppp_settings.our_name);
+    
+    /* If authentication is required, ask peer for CHAP or PAP. */
+    if (ppp_settings.auth_required && !wo->neg_chap && !wo->neg_upap) {
+        wo->neg_chap = 1;
+        wo->neg_upap = 1;
+    }
+    
+    /*
+     * Check whether we have appropriate secrets to use
+     * to authenticate the peer.
+     */
+    can_auth = wo->neg_upap && have_pap_secret();
+    if (!can_auth && wo->neg_chap) {
+        remote = ipwo->accept_remote? 0: ipwo->hisaddr;
+        can_auth = have_chap_secret(ppp_settings.remote_name, ppp_settings.our_name, remote);
+    }
+    
+    if (ppp_settings.auth_required && !can_auth) {
+        ppp_panic("No auth secret");
+    }
+}
+#endif
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+/*
+ * Proceed to the network phase.
+ */
+static void network_phase(int unit)
+{
+    int i;
+    struct protent *protp;
+    lcp_options *go = &lcp_gotoptions[unit];
+    
+    /*
+     * If the peer had to authenticate, run the auth-up script now.
+     */
+    if ((go->neg_chap || go->neg_upap) && !did_authup) {
+        /* XXX Do setup for peer authentication. */
+        did_authup = 1;
+    }
+    
+#if CBCP_SUPPORT > 0
+    /*
+     * If we negotiated callback, do it now.
+     */
+    if (go->neg_cbcp) {
+        lcp_phase[unit] = PHASE_CALLBACK;
+        (*cbcp_protent.open)(unit);
+        return;
+    }
+#endif
+    
+    lcp_phase[unit] = PHASE_NETWORK;
+    for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i)
+        if (protp->protocol < 0xC000 && protp->enabled_flag
+                && protp->open != NULL) {
+            (*protp->open)(unit);
+            if (protp->protocol != PPP_CCP)
+                ++num_np_open;
+        }
+    
+    if (num_np_open == 0)
+        /* nothing to do */
+        lcp_close(0, "No network protocols running");
+}
+
+/*
+ * check_idle - check whether the link has been idle for long
+ * enough that we can shut it down.
+ */
+static void check_idle(void *arg)
+{
+    struct ppp_idle idle;
+    u_short itime;
+    
+	(void)arg;
+    if (!get_idle_time(0, &idle))
+        return;
+    itime = LWIP_MIN(idle.xmit_idle, idle.recv_idle);
+    if (itime >= ppp_settings.idle_time_limit) {
+        /* link is idle: shut it down. */
+        AUTHDEBUG((LOG_INFO, "Terminating connection due to lack of activity.\n"));
+        lcp_close(0, "Link inactive");
+    } else {
+        TIMEOUT(check_idle, NULL, ppp_settings.idle_time_limit - itime);
+    }
+}
+
+/*
+ * connect_time_expired - log a message and close the connection.
+ */
+static void connect_time_expired(void *arg)
+{
+	(void)arg;
+
+    AUTHDEBUG((LOG_INFO, "Connect time expired\n"));
+    lcp_close(0, "Connect time expired");   /* Close connection */
+}
+
+#if 0
+/*
+ * login - Check the user name and password against the system
+ * password database, and login the user if OK.
+ *
+ * returns:
+ *  UPAP_AUTHNAK: Login failed.
+ *  UPAP_AUTHACK: Login succeeded.
+ * In either case, msg points to an appropriate message.
+ */
+static int login(char *user, char *passwd, char **msg, int *msglen)
+{
+    /* XXX Fail until we decide that we want to support logins. */
+    return (UPAP_AUTHNAK);
+}
+#endif
+
+/*
+ * logout - Logout the user.
+ */
+static void logout(void)
+{
+    logged_in = 0;
+}
+
+
+/*
+ * null_login - Check if a username of "" and a password of "" are
+ * acceptable, and iff so, set the list of acceptable IP addresses
+ * and return 1.
+ */
+static int null_login(int unit)
+{
+	(void)unit;
+    /* XXX Fail until we decide that we want to support logins. */
+    return 0;
+}
+
+
+/*
+ * get_pap_passwd - get a password for authenticating ourselves with
+ * our peer using PAP.  Returns 1 on success, 0 if no suitable password
+ * could be found.
+ */
+static int get_pap_passwd(int unit, char *user, char *passwd)
+{
+/* normally we would reject PAP if no password is provided,
+   but this causes problems with some providers (like CHT in Taiwan)
+   who incorrectly request PAP and expect a bogus/empty password, so
+   always provide a default user/passwd of "none"/"none"
+*/
+    if(user)
+    	strcpy(user,   "none");
+    if(passwd)
+    	strcpy(passwd, "none");
+
+    return 1;
+}
+
+
+/*
+ * have_pap_secret - check whether we have a PAP file with any
+ * secrets that we could possibly use for authenticating the peer.
+ */
+static int have_pap_secret(void)
+{
+    /* XXX Fail until we set up our passwords. */
+    return 0;
+}
+
+
+/*
+ * have_chap_secret - check whether we have a CHAP file with a
+ * secret that we could possibly use for authenticating `client'
+ * on `server'.  Either can be the null string, meaning we don't
+ * know the identity yet.
+ */
+static int have_chap_secret(char *client, char *server, u32_t remote)
+{
+	(void)client;
+	(void)server;
+	(void)remote;
+    /* XXX Fail until we set up our passwords. */
+    return 0;
+}
+
+
+#if 0 /* PAP_SUPPORT > 0 || CHAP_SUPPORT > 0 */
+/*
+ * set_allowed_addrs() - set the list of allowed addresses.
+ */
+static void set_allowed_addrs(int unit, struct wordlist *addrs)
+{
+    if (addresses[unit] != NULL)
+        free_wordlist(addresses[unit]);
+    addresses[unit] = addrs;
+
+#if 0
+    /*
+     * If there's only one authorized address we might as well
+     * ask our peer for that one right away
+     */
+    if (addrs != NULL && addrs->next == NULL) {
+        char *p = addrs->word;
+        struct ipcp_options *wo = &ipcp_wantoptions[unit];
+        u32_t a;
+        struct hostent *hp;
+        
+        if (wo->hisaddr == 0 && *p != '!' && *p != '-'
+                && strchr(p, '/') == NULL) {
+            hp = gethostbyname(p);
+            if (hp != NULL && hp->h_addrtype == AF_INET)
+                a = *(u32_t *)hp->h_addr;
+            else
+                a = inet_addr(p);
+            if (a != (u32_t) -1)
+                wo->hisaddr = a;
+        }
+    }
+#endif
+}
+#endif
+
+static int ip_addr_check(u32_t addr, struct wordlist *addrs)
+{
+    
+    /* don't allow loopback or multicast address */
+    if (bad_ip_adrs(addr))
+        return 0;
+    
+    if (addrs == NULL)
+        return !ppp_settings.auth_required;      /* no addresses authorized */
+    
+    /* XXX All other addresses allowed. */
+    return 1;
+}
+
+#if 0 /* PAP_SUPPORT > 0 || CHAP_SUPPORT */
+/*
+ * free_wordlist - release memory allocated for a wordlist.
+ */
+static void free_wordlist(struct wordlist *wp)
+{
+    struct wordlist *next;
+    
+    while (wp != NULL) {
+        next = wp->next;
+        free(wp);
+        wp = next;
+    }
+}
+#endif
+
+#endif /* PPP_SUPPORT */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/auth.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/auth.h
new file mode 100644
index 000000000..58174056c
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/auth.h
@@ -0,0 +1,94 @@
+/*****************************************************************************
+* auth.h -  PPP Authentication and phase control header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1998 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-04 Guy Lancaster , Global Election Systems Inc.
+*	Original derived from BSD pppd.h.
+*****************************************************************************/
+/*
+ * pppd.h - PPP daemon global declarations.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ */
+
+#ifndef AUTH_H
+#define AUTH_H
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+void link_required (int);		/* we are starting to use the link */
+void link_terminated (int);	/* we are finished with the link */
+void link_down (int);			/* the LCP layer has left the Opened state */
+void link_established (int);	/* the link is up; authenticate now */
+void np_up (int, u16_t);			/* a network protocol has come up */
+void np_down (int, u16_t);		/* a network protocol has gone down */
+void np_finished (int, u16_t);	/* a network protocol no longer needs link */
+void auth_peer_fail (int, u16_t);/* peer failed to authenticate itself */
+
+/* peer successfully authenticated itself */
+void auth_peer_success (int, u16_t, char *, int);
+
+/* we failed to authenticate ourselves */
+void auth_withpeer_fail (int, u16_t);
+
+/* we successfully authenticated ourselves */
+void auth_withpeer_success (int, u16_t);
+
+/* check authentication options supplied */
+void auth_check_options (void);
+void auth_reset (int);			/* check what secrets we have */
+
+/* Check peer-supplied username/password */
+int  check_passwd (int, char *, int, char *, int, char **, int *);
+
+/* get "secret" for chap */
+int  get_secret (int, char *, char *, char *, int *, int);
+
+/* check if IP address is authorized */
+int  auth_ip_addr (int, u32_t);
+
+/* check if IP address is unreasonable */
+int  bad_ip_adrs (u32_t);
+
+
+#endif /* AUTH_H */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/chap.c b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/chap.c
new file mode 100644
index 000000000..30441bdc8
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/chap.c
@@ -0,0 +1,872 @@
+/*** WARNING - THIS HAS NEVER BEEN FINISHED ***/
+/*****************************************************************************
+* chap.c - Network Challenge Handshake Authentication Protocol program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-04 Guy Lancaster , Global Election Systems Inc.
+*	Original based on BSD chap.c.
+*****************************************************************************/
+/*
+ * chap.c - Challenge Handshake Authentication Protocol.
+ *
+ * Copyright (c) 1993 The Australian National University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the Australian National University.  The name of the University
+ * may not be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Copyright (c) 1991 Gregory M. Christy.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Gregory M. Christy.  The name of the author may not be used to
+ * endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include "ppp.h"
+#if PPP_SUPPORT > 0
+#include "magic.h"
+
+#if CHAP_SUPPORT > 0
+
+#include "randm.h"
+#include "auth.h"
+#include "md5.h"
+#include "chap.h"
+#include "chpms.h"
+#include "pppdebug.h"
+
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+
+
+/************************/
+/*** LOCAL DATA TYPES ***/
+/************************/
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+/*
+ * Protocol entry points.
+ */
+static void ChapInit (int);
+static void ChapLowerUp (int);
+static void ChapLowerDown (int);
+static void ChapInput (int, u_char *, int);
+static void ChapProtocolReject (int);
+static int  ChapPrintPkt (u_char *, int,
+			      void (*) (void *, char *, ...), void *);
+
+static void ChapChallengeTimeout (void *);
+static void ChapResponseTimeout (void *);
+static void ChapReceiveChallenge (chap_state *, u_char *, int, int);
+static void ChapRechallenge (void *);
+static void ChapReceiveResponse (chap_state *, u_char *, int, int);
+static void ChapReceiveSuccess(chap_state *cstate, u_char *inp, u_char id, int len);
+static void ChapReceiveFailure(chap_state *cstate, u_char *inp, u_char id, int len);
+static void ChapSendStatus (chap_state *, int);
+static void ChapSendChallenge (chap_state *);
+static void ChapSendResponse (chap_state *);
+static void ChapGenChallenge (chap_state *);
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+chap_state chap[NUM_PPP];		/* CHAP state; one for each unit */
+
+struct protent chap_protent = {
+    PPP_CHAP,
+    ChapInit,
+    ChapInput,
+    ChapProtocolReject,
+    ChapLowerUp,
+    ChapLowerDown,
+    NULL,
+    NULL,
+#if 0
+    ChapPrintPkt,
+    NULL,
+#endif
+    1,
+    "CHAP",
+#if 0
+    NULL,
+    NULL,
+    NULL
+#endif
+};
+
+
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+static char *ChapCodenames[] = {
+	"Challenge", "Response", "Success", "Failure"
+};
+
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ * ChapAuthWithPeer - Authenticate us with our peer (start client).
+ *
+ */
+void ChapAuthWithPeer(int unit, char *our_name, int digest)
+{
+	chap_state *cstate = &chap[unit];
+	
+	cstate->resp_name = our_name;
+	cstate->resp_type = digest;
+	
+	if (cstate->clientstate == CHAPCS_INITIAL ||
+			cstate->clientstate == CHAPCS_PENDING) {
+		/* lower layer isn't up - wait until later */
+		cstate->clientstate = CHAPCS_PENDING;
+		return;
+	}
+	
+	/*
+	 * We get here as a result of LCP coming up.
+	 * So even if CHAP was open before, we will 
+	 * have to re-authenticate ourselves.
+	 */
+	cstate->clientstate = CHAPCS_LISTEN;
+}
+
+
+/*
+ * ChapAuthPeer - Authenticate our peer (start server).
+ */
+void ChapAuthPeer(int unit, char *our_name, int digest)
+{
+	chap_state *cstate = &chap[unit];
+	
+	cstate->chal_name = our_name;
+	cstate->chal_type = digest;
+	
+	if (cstate->serverstate == CHAPSS_INITIAL ||
+			cstate->serverstate == CHAPSS_PENDING) {
+		/* lower layer isn't up - wait until later */
+		cstate->serverstate = CHAPSS_PENDING;
+		return;
+	}
+	
+	ChapGenChallenge(cstate);
+	ChapSendChallenge(cstate);		/* crank it up dude! */
+	cstate->serverstate = CHAPSS_INITIAL_CHAL;
+}
+
+
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+/*
+ * ChapInit - Initialize a CHAP unit.
+ */
+static void ChapInit(int unit)
+{
+	chap_state *cstate = &chap[unit];
+	
+	BZERO(cstate, sizeof(*cstate));
+	cstate->unit = unit;
+	cstate->clientstate = CHAPCS_INITIAL;
+	cstate->serverstate = CHAPSS_INITIAL;
+	cstate->timeouttime = CHAP_DEFTIMEOUT;
+	cstate->max_transmits = CHAP_DEFTRANSMITS;
+	/* random number generator is initialized in magic_init */
+}
+
+
+/*
+ * ChapChallengeTimeout - Timeout expired on sending challenge.
+ */
+static void ChapChallengeTimeout(void *arg)
+{
+	chap_state *cstate = (chap_state *) arg;
+	
+	/* if we aren't sending challenges, don't worry.  then again we */
+	/* probably shouldn't be here either */
+	if (cstate->serverstate != CHAPSS_INITIAL_CHAL &&
+			cstate->serverstate != CHAPSS_RECHALLENGE)
+		return;
+	
+	if (cstate->chal_transmits >= cstate->max_transmits) {
+		/* give up on peer */
+		CHAPDEBUG((LOG_ERR, "Peer failed to respond to CHAP challenge\n"));
+		cstate->serverstate = CHAPSS_BADAUTH;
+		auth_peer_fail(cstate->unit, PPP_CHAP);
+		return;
+	}
+	
+	ChapSendChallenge(cstate);		/* Re-send challenge */
+}
+
+
+/*
+ * ChapResponseTimeout - Timeout expired on sending response.
+ */
+static void ChapResponseTimeout(void *arg)
+{
+	chap_state *cstate = (chap_state *) arg;
+	
+	/* if we aren't sending a response, don't worry. */
+	if (cstate->clientstate != CHAPCS_RESPONSE)
+		return;
+	
+	ChapSendResponse(cstate);		/* re-send response */
+}
+
+
+/*
+ * ChapRechallenge - Time to challenge the peer again.
+ */
+static void ChapRechallenge(void *arg)
+{
+	chap_state *cstate = (chap_state *) arg;
+	
+	/* if we aren't sending a response, don't worry. */
+	if (cstate->serverstate != CHAPSS_OPEN)
+		return;
+	
+	ChapGenChallenge(cstate);
+	ChapSendChallenge(cstate);
+	cstate->serverstate = CHAPSS_RECHALLENGE;
+}
+
+
+/*
+ * ChapLowerUp - The lower layer is up.
+ *
+ * Start up if we have pending requests.
+ */
+static void ChapLowerUp(int unit)
+{
+	chap_state *cstate = &chap[unit];
+	
+	if (cstate->clientstate == CHAPCS_INITIAL)
+		cstate->clientstate = CHAPCS_CLOSED;
+	else if (cstate->clientstate == CHAPCS_PENDING)
+		cstate->clientstate = CHAPCS_LISTEN;
+	
+	if (cstate->serverstate == CHAPSS_INITIAL)
+		cstate->serverstate = CHAPSS_CLOSED;
+	else if (cstate->serverstate == CHAPSS_PENDING) {
+		ChapGenChallenge(cstate);
+		ChapSendChallenge(cstate);
+		cstate->serverstate = CHAPSS_INITIAL_CHAL;
+	}
+}
+
+
+/*
+ * ChapLowerDown - The lower layer is down.
+ *
+ * Cancel all timeouts.
+ */
+static void ChapLowerDown(int unit)
+{
+	chap_state *cstate = &chap[unit];
+	
+	/* Timeout(s) pending?  Cancel if so. */
+	if (cstate->serverstate == CHAPSS_INITIAL_CHAL ||
+			cstate->serverstate == CHAPSS_RECHALLENGE)
+		UNTIMEOUT(ChapChallengeTimeout, cstate);
+	else if (cstate->serverstate == CHAPSS_OPEN
+			&& cstate->chal_interval != 0)
+		UNTIMEOUT(ChapRechallenge, cstate);
+	if (cstate->clientstate == CHAPCS_RESPONSE)
+		UNTIMEOUT(ChapResponseTimeout, cstate);
+	
+	cstate->clientstate = CHAPCS_INITIAL;
+	cstate->serverstate = CHAPSS_INITIAL;
+}
+
+
+/*
+ * ChapProtocolReject - Peer doesn't grok CHAP.
+ */
+static void ChapProtocolReject(int unit)
+{
+	chap_state *cstate = &chap[unit];
+	
+	if (cstate->serverstate != CHAPSS_INITIAL &&
+			cstate->serverstate != CHAPSS_CLOSED)
+		auth_peer_fail(unit, PPP_CHAP);
+	if (cstate->clientstate != CHAPCS_INITIAL &&
+			cstate->clientstate != CHAPCS_CLOSED)
+		auth_withpeer_fail(unit, PPP_CHAP);
+	ChapLowerDown(unit);		/* shutdown chap */
+}
+
+
+/*
+ * ChapInput - Input CHAP packet.
+ */
+static void ChapInput(int unit, u_char *inpacket, int packet_len)
+{
+	chap_state *cstate = &chap[unit];
+	u_char *inp;
+	u_char code, id;
+	int len;
+	
+	/*
+	 * Parse header (code, id and length).
+	 * If packet too short, drop it.
+	 */
+	inp = inpacket;
+	if (packet_len < CHAP_HEADERLEN) {
+		CHAPDEBUG((LOG_INFO, "ChapInput: rcvd short header.\n"));
+		return;
+	}
+	GETCHAR(code, inp);
+	GETCHAR(id, inp);
+	GETSHORT(len, inp);
+	if (len < CHAP_HEADERLEN) {
+		CHAPDEBUG((LOG_INFO, "ChapInput: rcvd illegal length.\n"));
+		return;
+	}
+	if (len > packet_len) {
+		CHAPDEBUG((LOG_INFO, "ChapInput: rcvd short packet.\n"));
+		return;
+	}
+	len -= CHAP_HEADERLEN;
+	
+	/*
+	 * Action depends on code (as in fact it usually does :-).
+	 */
+	switch (code) {
+	case CHAP_CHALLENGE:
+		ChapReceiveChallenge(cstate, inp, id, len);
+		break;
+	
+	case CHAP_RESPONSE:
+		ChapReceiveResponse(cstate, inp, id, len);
+		break;
+	
+	case CHAP_FAILURE:
+		ChapReceiveFailure(cstate, inp, id, len);
+		break;
+	
+	case CHAP_SUCCESS:
+		ChapReceiveSuccess(cstate, inp, id, len);
+		break;
+	
+	default:				/* Need code reject? */
+		CHAPDEBUG((LOG_WARNING, "Unknown CHAP code (%d) received.\n", code));
+		break;
+	}
+}
+
+
+/*
+ * ChapReceiveChallenge - Receive Challenge and send Response.
+ */
+static void ChapReceiveChallenge(chap_state *cstate, u_char *inp, int id, int len)
+{
+	int rchallenge_len;
+	u_char *rchallenge;
+	int secret_len;
+	char secret[MAXSECRETLEN];
+	char rhostname[256];
+	MD5_CTX mdContext;
+	u_char hash[MD5_SIGNATURE_SIZE];
+	
+	CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: Rcvd id %d.\n", id));
+	if (cstate->clientstate == CHAPCS_CLOSED ||
+		cstate->clientstate == CHAPCS_PENDING) {
+		CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: in state %d\n",
+			   cstate->clientstate));
+		return;
+	}
+	
+	if (len < 2) {
+		CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: rcvd short packet.\n"));
+		return;
+	}
+	
+	GETCHAR(rchallenge_len, inp);
+	len -= sizeof (u_char) + rchallenge_len;	/* now name field length */
+	if (len < 0) {
+		CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: rcvd short packet.\n"));
+		return;
+	}
+	rchallenge = inp;
+	INCPTR(rchallenge_len, inp);
+	
+	if (len >= sizeof(rhostname))
+		len = sizeof(rhostname) - 1;
+	BCOPY(inp, rhostname, len);
+	rhostname[len] = '\000';
+	
+	CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: received name field '%s'\n",
+	       rhostname));
+	
+	/* Microsoft doesn't send their name back in the PPP packet */
+	if (ppp_settings.remote_name[0] != 0 && (ppp_settings.explicit_remote || rhostname[0] == 0)) {
+		strncpy(rhostname, ppp_settings.remote_name, sizeof(rhostname));
+		rhostname[sizeof(rhostname) - 1] = 0;
+		CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: using '%s' as remote name\n",
+			   rhostname));
+	}
+	
+	/* get secret for authenticating ourselves with the specified host */
+	if (!get_secret(cstate->unit, cstate->resp_name, rhostname,
+			    secret, &secret_len, 0)) {
+		secret_len = 0;		/* assume null secret if can't find one */
+		CHAPDEBUG((LOG_WARNING, "No CHAP secret found for authenticating us to %s\n", rhostname));
+	}
+	
+	/* cancel response send timeout if necessary */
+	if (cstate->clientstate == CHAPCS_RESPONSE)
+		UNTIMEOUT(ChapResponseTimeout, cstate);
+	
+	cstate->resp_id = id;
+	cstate->resp_transmits = 0;
+	
+	/*  generate MD based on negotiated type */
+	switch (cstate->resp_type) { 
+	
+	case CHAP_DIGEST_MD5:
+		MD5Init(&mdContext);
+		MD5Update(&mdContext, &cstate->resp_id, 1);
+		MD5Update(&mdContext, (u_char*)secret, secret_len);
+		MD5Update(&mdContext, rchallenge, rchallenge_len);
+		MD5Final(hash, &mdContext);
+		BCOPY(hash, cstate->response, MD5_SIGNATURE_SIZE);
+		cstate->resp_length = MD5_SIGNATURE_SIZE;
+		break;
+	
+#ifdef CHAPMS
+	case CHAP_MICROSOFT:
+		ChapMS(cstate, rchallenge, rchallenge_len, secret, secret_len);
+		break;
+#endif
+	
+	default:
+		CHAPDEBUG((LOG_INFO, "unknown digest type %d\n", cstate->resp_type));
+		return;
+	}
+	
+	BZERO(secret, sizeof(secret));
+	ChapSendResponse(cstate);
+}
+
+
+/*
+ * ChapReceiveResponse - Receive and process response.
+ */
+static void ChapReceiveResponse(chap_state *cstate, u_char *inp, int id, int len)
+{
+	u_char *remmd, remmd_len;
+	int secret_len, old_state;
+	int code;
+	char rhostname[256];
+	MD5_CTX mdContext;
+	char secret[MAXSECRETLEN];
+	u_char hash[MD5_SIGNATURE_SIZE];
+	
+	CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: Rcvd id %d.\n", id));
+	
+	if (cstate->serverstate == CHAPSS_CLOSED ||
+			cstate->serverstate == CHAPSS_PENDING) {
+		CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: in state %d\n",
+		cstate->serverstate));
+		return;
+	}
+	
+	if (id != cstate->chal_id)
+		return;			/* doesn't match ID of last challenge */
+	
+	/*
+	* If we have received a duplicate or bogus Response,
+	* we have to send the same answer (Success/Failure)
+	* as we did for the first Response we saw.
+	*/
+	if (cstate->serverstate == CHAPSS_OPEN) {
+		ChapSendStatus(cstate, CHAP_SUCCESS);
+		return;
+	}
+	if (cstate->serverstate == CHAPSS_BADAUTH) {
+		ChapSendStatus(cstate, CHAP_FAILURE);
+		return;
+	}
+	
+	if (len < 2) {
+		CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: rcvd short packet.\n"));
+		return;
+	}
+	GETCHAR(remmd_len, inp);		/* get length of MD */
+	remmd = inp;			/* get pointer to MD */
+	INCPTR(remmd_len, inp);
+	
+	len -= sizeof (u_char) + remmd_len;
+	if (len < 0) {
+		CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: rcvd short packet.\n"));
+		return;
+	}
+	
+	UNTIMEOUT(ChapChallengeTimeout, cstate);
+	
+	if (len >= sizeof(rhostname))
+		len = sizeof(rhostname) - 1;
+	BCOPY(inp, rhostname, len);
+	rhostname[len] = '\000';
+	
+	CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: received name field: %s\n",
+				rhostname));
+	
+	/*
+	* Get secret for authenticating them with us,
+	* do the hash ourselves, and compare the result.
+	*/
+	code = CHAP_FAILURE;
+	if (!get_secret(cstate->unit, rhostname, cstate->chal_name,
+	secret, &secret_len, 1)) {
+/*        CHAPDEBUG((LOG_WARNING, TL_CHAP, "No CHAP secret found for authenticating %s\n", rhostname)); */
+		CHAPDEBUG((LOG_WARNING, "No CHAP secret found for authenticating %s\n",
+		rhostname));
+	} else {
+	
+		/*  generate MD based on negotiated type */
+		switch (cstate->chal_type) { 
+		
+		case CHAP_DIGEST_MD5:		/* only MD5 is defined for now */
+			if (remmd_len != MD5_SIGNATURE_SIZE)
+				break;			/* it's not even the right length */
+			MD5Init(&mdContext);
+			MD5Update(&mdContext, &cstate->chal_id, 1);
+			MD5Update(&mdContext, (u_char*)secret, secret_len);
+			MD5Update(&mdContext, cstate->challenge, cstate->chal_len);
+			MD5Final(hash, &mdContext); 
+			
+			/* compare local and remote MDs and send the appropriate status */
+			if (memcmp (hash, remmd, MD5_SIGNATURE_SIZE) == 0)
+				code = CHAP_SUCCESS;	/* they are the same! */
+			break;
+		
+		default:
+			CHAPDEBUG((LOG_INFO, "unknown digest type %d\n", cstate->chal_type));
+		}
+	}
+	
+	BZERO(secret, sizeof(secret));
+	ChapSendStatus(cstate, code);
+	
+	if (code == CHAP_SUCCESS) {
+		old_state = cstate->serverstate;
+		cstate->serverstate = CHAPSS_OPEN;
+		if (old_state == CHAPSS_INITIAL_CHAL) {
+			auth_peer_success(cstate->unit, PPP_CHAP, rhostname, len);
+		}
+		if (cstate->chal_interval != 0)
+			TIMEOUT(ChapRechallenge, cstate, cstate->chal_interval);
+	} else {
+		CHAPDEBUG((LOG_ERR, "CHAP peer authentication failed\n"));
+		cstate->serverstate = CHAPSS_BADAUTH;
+		auth_peer_fail(cstate->unit, PPP_CHAP);
+	}
+}
+
+/*
+ * ChapReceiveSuccess - Receive Success
+ */
+static void ChapReceiveSuccess(chap_state *cstate, u_char *inp, u_char id, int len)
+{
+
+	CHAPDEBUG((LOG_INFO, "ChapReceiveSuccess: Rcvd id %d.\n", id));
+	
+	if (cstate->clientstate == CHAPCS_OPEN)
+		/* presumably an answer to a duplicate response */
+		return;
+	
+	if (cstate->clientstate != CHAPCS_RESPONSE) {
+		/* don't know what this is */
+		CHAPDEBUG((LOG_INFO, "ChapReceiveSuccess: in state %d\n",
+			   cstate->clientstate));
+		return;
+	}
+	
+	UNTIMEOUT(ChapResponseTimeout, cstate);
+	
+	/*
+	 * Print message.
+	 */
+	if (len > 0)
+		PRINTMSG(inp, len);
+	
+	cstate->clientstate = CHAPCS_OPEN;
+	
+	auth_withpeer_success(cstate->unit, PPP_CHAP);
+}
+
+
+/*
+ * ChapReceiveFailure - Receive failure.
+ */
+static void ChapReceiveFailure(chap_state *cstate, u_char *inp, u_char id, int len)
+{
+	CHAPDEBUG((LOG_INFO, "ChapReceiveFailure: Rcvd id %d.\n", id));
+	
+	if (cstate->clientstate != CHAPCS_RESPONSE) {
+		/* don't know what this is */
+		CHAPDEBUG((LOG_INFO, "ChapReceiveFailure: in state %d\n",
+			   cstate->clientstate));
+		return;
+	}
+	
+	UNTIMEOUT(ChapResponseTimeout, cstate);
+	
+	/*
+	 * Print message.
+	 */
+	if (len > 0)
+		PRINTMSG(inp, len);
+	
+	CHAPDEBUG((LOG_ERR, "CHAP authentication failed\n"));
+	auth_withpeer_fail(cstate->unit, PPP_CHAP);
+}
+
+
+/*
+ * ChapSendChallenge - Send an Authenticate challenge.
+ */
+static void ChapSendChallenge(chap_state *cstate)
+{
+	u_char *outp;
+	int chal_len, name_len;
+	int outlen;
+	
+	chal_len = cstate->chal_len;
+	name_len = strlen(cstate->chal_name);
+	outlen = CHAP_HEADERLEN + sizeof (u_char) + chal_len + name_len;
+	outp = outpacket_buf[cstate->unit];
+	
+	MAKEHEADER(outp, PPP_CHAP);		/* paste in a CHAP header */
+	
+	PUTCHAR(CHAP_CHALLENGE, outp);
+	PUTCHAR(cstate->chal_id, outp);
+	PUTSHORT(outlen, outp);
+	
+	PUTCHAR(chal_len, outp);		/* put length of challenge */
+	BCOPY(cstate->challenge, outp, chal_len);
+	INCPTR(chal_len, outp);
+	
+	BCOPY(cstate->chal_name, outp, name_len);	/* append hostname */
+	
+	pppWrite(cstate->unit, outpacket_buf[cstate->unit], outlen + PPP_HDRLEN);
+	
+	CHAPDEBUG((LOG_INFO, "ChapSendChallenge: Sent id %d.\n", cstate->chal_id));
+	
+	TIMEOUT(ChapChallengeTimeout, cstate, cstate->timeouttime);
+	++cstate->chal_transmits;
+}
+
+
+/*
+ * ChapSendStatus - Send a status response (ack or nak).
+ */
+static void ChapSendStatus(chap_state *cstate, int code)
+{
+	u_char *outp;
+	int outlen, msglen;
+	char msg[256];
+	
+	if (code == CHAP_SUCCESS)
+		strcpy(msg, "Welcome!");
+	else
+		strcpy(msg, "I don't like you.  Go 'way.");
+	msglen = strlen(msg);
+	
+	outlen = CHAP_HEADERLEN + msglen;
+	outp = outpacket_buf[cstate->unit];
+	
+	MAKEHEADER(outp, PPP_CHAP);		/* paste in a header */
+	
+	PUTCHAR(code, outp);
+	PUTCHAR(cstate->chal_id, outp);
+	PUTSHORT(outlen, outp);
+	BCOPY(msg, outp, msglen);
+	pppWrite(cstate->unit, outpacket_buf[cstate->unit], outlen + PPP_HDRLEN);
+	
+	CHAPDEBUG((LOG_INFO, "ChapSendStatus: Sent code %d, id %d.\n", code,
+	       cstate->chal_id));
+}
+
+/*
+ * ChapGenChallenge is used to generate a pseudo-random challenge string of
+ * a pseudo-random length between min_len and max_len.  The challenge
+ * string and its length are stored in *cstate, and various other fields of
+ * *cstate are initialized.
+ */
+
+static void ChapGenChallenge(chap_state *cstate)
+{
+	int chal_len;
+	u_char *ptr = cstate->challenge;
+	int i;
+	
+	/* pick a random challenge length between MIN_CHALLENGE_LENGTH and 
+	   MAX_CHALLENGE_LENGTH */  
+	chal_len = (unsigned)
+				((((magic() >> 16) *
+			        (MAX_CHALLENGE_LENGTH - MIN_CHALLENGE_LENGTH)) >> 16)
+			     + MIN_CHALLENGE_LENGTH);
+	cstate->chal_len = chal_len;
+	cstate->chal_id = ++cstate->id;
+	cstate->chal_transmits = 0;
+	
+	/* generate a random string */
+	for (i = 0; i < chal_len; i++ )
+		*ptr++ = (char) (magic() & 0xff);
+}
+
+/*
+ * ChapSendResponse - send a response packet with values as specified
+ * in *cstate.
+ */
+/* ARGSUSED */
+static void ChapSendResponse(chap_state *cstate)
+{
+	u_char *outp;
+	int outlen, md_len, name_len;
+	
+	md_len = cstate->resp_length;
+	name_len = strlen(cstate->resp_name);
+	outlen = CHAP_HEADERLEN + sizeof (u_char) + md_len + name_len;
+	outp = outpacket_buf[cstate->unit];
+	
+	MAKEHEADER(outp, PPP_CHAP);
+	
+	PUTCHAR(CHAP_RESPONSE, outp);	/* we are a response */
+	PUTCHAR(cstate->resp_id, outp);	/* copy id from challenge packet */
+	PUTSHORT(outlen, outp);			/* packet length */
+	
+	PUTCHAR(md_len, outp);			/* length of MD */
+	BCOPY(cstate->response, outp, md_len);		/* copy MD to buffer */
+	INCPTR(md_len, outp);
+	
+	BCOPY(cstate->resp_name, outp, name_len);	/* append our name */
+	
+	/* send the packet */
+	pppWrite(cstate->unit, outpacket_buf[cstate->unit], outlen + PPP_HDRLEN);
+	
+	cstate->clientstate = CHAPCS_RESPONSE;
+	TIMEOUT(ChapResponseTimeout, cstate, cstate->timeouttime);
+	++cstate->resp_transmits;
+}
+
+/*
+ * ChapPrintPkt - print the contents of a CHAP packet.
+ */
+static int ChapPrintPkt(
+	u_char *p,
+	int plen,
+	void (*printer) (void *, char *, ...),
+	void *arg
+)
+{
+	int code, id, len;
+	int clen, nlen;
+	u_char x;
+	
+	if (plen < CHAP_HEADERLEN)
+		return 0;
+	GETCHAR(code, p);
+	GETCHAR(id, p);
+	GETSHORT(len, p);
+	if (len < CHAP_HEADERLEN || len > plen)
+		return 0;
+	
+	if (code >= 1 && code <= sizeof(ChapCodenames) / sizeof(char *))
+		printer(arg, " %s", ChapCodenames[code-1]);
+	else
+		printer(arg, " code=0x%x", code);
+	printer(arg, " id=0x%x", id);
+	len -= CHAP_HEADERLEN;
+	switch (code) {
+	case CHAP_CHALLENGE:
+	case CHAP_RESPONSE:
+		if (len < 1)
+			break;
+		clen = p[0];
+		if (len < clen + 1)
+			break;
+		++p;
+		nlen = len - clen - 1;
+		printer(arg, " <");
+		for (; clen > 0; --clen) {
+			GETCHAR(x, p);
+			printer(arg, "%.2x", x);
+		}
+		printer(arg, ">, name = %.*Z", nlen, p);
+		break;
+	case CHAP_FAILURE:
+	case CHAP_SUCCESS:
+		printer(arg, " %.*Z", len, p);
+		break;
+	default:
+		for (clen = len; clen > 0; --clen) {
+			GETCHAR(x, p);
+			printer(arg, " %.2x", x);
+		}
+	}
+	
+	return len + CHAP_HEADERLEN;
+}
+
+#endif
+
+#endif /* PPP_SUPPORT */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/chap.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/chap.h
new file mode 100644
index 000000000..f20c1736f
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/chap.h
@@ -0,0 +1,167 @@
+/*****************************************************************************
+* chap.h - Network Challenge Handshake Authentication Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1998 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-03 Guy Lancaster , Global Election Systems Inc.
+*	Original built from BSD network code.
+******************************************************************************/
+/*
+ * chap.h - Challenge Handshake Authentication Protocol definitions.
+ *
+ * Copyright (c) 1993 The Australian National University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the Australian National University.  The name of the University
+ * may not be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Copyright (c) 1991 Gregory M. Christy
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the author.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * $Id: chap.h,v 1.2 2006/08/29 18:53:47 wolti Exp $
+ */
+
+#ifndef CHAP_H
+#define CHAP_H
+
+/*************************
+*** PUBLIC DEFINITIONS ***
+*************************/
+
+/* Code + ID + length */
+#define CHAP_HEADERLEN		4
+
+/*
+ * CHAP codes.
+ */
+
+#define CHAP_DIGEST_MD5		5	/* use MD5 algorithm */
+#define MD5_SIGNATURE_SIZE	16	/* 16 bytes in a MD5 message digest */
+#define CHAP_MICROSOFT		0x80	/* use Microsoft-compatible alg. */
+#define MS_CHAP_RESPONSE_LEN	49	/* Response length for MS-CHAP */
+
+#define CHAP_CHALLENGE		1
+#define CHAP_RESPONSE		2
+#define CHAP_SUCCESS		3
+#define CHAP_FAILURE    	4
+
+/*
+ *  Challenge lengths (for challenges we send) and other limits.
+ */
+#define MIN_CHALLENGE_LENGTH	32
+#define MAX_CHALLENGE_LENGTH	64
+#define MAX_RESPONSE_LENGTH	64	/* sufficient for MD5 or MS-CHAP */
+
+/*
+ * Client (peer) states.
+ */
+#define CHAPCS_INITIAL		0	/* Lower layer down, not opened */
+#define CHAPCS_CLOSED		1	/* Lower layer up, not opened */
+#define CHAPCS_PENDING		2	/* Auth us to peer when lower up */
+#define CHAPCS_LISTEN		3	/* Listening for a challenge */
+#define CHAPCS_RESPONSE		4	/* Sent response, waiting for status */
+#define CHAPCS_OPEN		5	/* We've received Success */
+
+/*
+ * Server (authenticator) states.
+ */
+#define CHAPSS_INITIAL		0	/* Lower layer down, not opened */
+#define CHAPSS_CLOSED		1	/* Lower layer up, not opened */
+#define CHAPSS_PENDING		2	/* Auth peer when lower up */
+#define CHAPSS_INITIAL_CHAL	3	/* We've sent the first challenge */
+#define CHAPSS_OPEN		4	/* We've sent a Success msg */
+#define CHAPSS_RECHALLENGE	5	/* We've sent another challenge */
+#define CHAPSS_BADAUTH		6	/* We've sent a Failure msg */
+
+/************************
+*** PUBLIC DATA TYPES ***
+************************/
+
+/*
+ * Each interface is described by a chap structure.
+ */
+
+typedef struct chap_state {
+    int unit;			/* Interface unit number */
+    int clientstate;		/* Client state */
+    int serverstate;		/* Server state */
+    u_char challenge[MAX_CHALLENGE_LENGTH]; /* last challenge string sent */
+    u_char chal_len;		/* challenge length */
+    u_char chal_id;		/* ID of last challenge */
+    u_char chal_type;		/* hash algorithm for challenges */
+    u_char id;			/* Current id */
+    char *chal_name;		/* Our name to use with challenge */
+    int chal_interval;		/* Time until we challenge peer again */
+    int timeouttime;		/* Timeout time in seconds */
+    int max_transmits;		/* Maximum # of challenge transmissions */
+    int chal_transmits;		/* Number of transmissions of challenge */
+    int resp_transmits;		/* Number of transmissions of response */
+    u_char response[MAX_RESPONSE_LENGTH];	/* Response to send */
+    u_char resp_length;		/* length of response */
+    u_char resp_id;		/* ID for response messages */
+    u_char resp_type;		/* hash algorithm for responses */
+    char *resp_name;		/* Our name to send with response */
+} chap_state;
+
+
+/******************
+*** PUBLIC DATA ***
+******************/
+extern chap_state chap[];
+
+extern struct protent chap_protent;
+
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+
+void ChapAuthWithPeer (int, char *, int);
+void ChapAuthPeer (int, char *, int);
+
+#endif /* CHAP_H */
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/chpms.c b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/chpms.c
new file mode 100644
index 000000000..306434460
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/chpms.c
@@ -0,0 +1,398 @@
+/*** WARNING - THIS CODE HAS NOT BEEN FINISHED! ***/
+/*****************************************************************************
+* chpms.c - Network MicroSoft Challenge Handshake Authentication Protocol program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* Copyright (c) 1997 by Global Election Systems Inc.  All rights reserved.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-08 Guy Lancaster , Global Election Systems Inc.
+*	Original based on BSD chap_ms.c.
+*****************************************************************************/
+/*
+ * chap_ms.c - Microsoft MS-CHAP compatible implementation.
+ *
+ * Copyright (c) 1995 Eric Rosenquist, Strata Software Limited.
+ * http://www.strataware.com/
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Eric Rosenquist.  The name of the author may not be used to
+ * endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+/*
+ * Modifications by Lauri Pesonen / lpesonen@clinet.fi, april 1997
+ *
+ *   Implemented LANManager type password response to MS-CHAP challenges.
+ *   Now pppd provides both NT style and LANMan style blocks, and the
+ *   prefered is set by option "ms-lanman". Default is to use NT.
+ *   The hash text (StdText) was taken from Win95 RASAPI32.DLL.
+ *
+ *   You should also use DOMAIN\\USERNAME as described in README.MSCHAP80
+ */
+
+#define USE_CRYPT
+
+
+#include "ppp.h"
+
+#if MSCHAP_SUPPORT > 0
+
+#include "md4.h"
+#ifndef USE_CRYPT
+#include "des.h"
+#endif
+#include "chap.h"
+#include "chpms.h"
+#include "pppdebug.h"
+
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+
+
+/************************/
+/*** LOCAL DATA TYPES ***/
+/************************/
+typedef struct {
+    u_char LANManResp[24];
+    u_char NTResp[24];
+    u_char UseNT;		/* If 1, ignore the LANMan response field */
+} MS_ChapResponse;
+/* We use MS_CHAP_RESPONSE_LEN, rather than sizeof(MS_ChapResponse),
+   in case this struct gets padded. */
+
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+
+/* XXX Don't know what to do with these. */
+extern void setkey(const char *);
+extern void encrypt(char *, int);
+
+static void	DesEncrypt (u_char *, u_char *, u_char *);
+static void	MakeKey (u_char *, u_char *);
+
+#ifdef USE_CRYPT
+static void	Expand (u_char *, u_char *);
+static void	Collapse (u_char *, u_char *);
+#endif
+
+static void ChallengeResponse(
+	u_char *challenge,	/* IN   8 octets */
+	u_char *pwHash,		/* IN  16 octets */
+	u_char *response	/* OUT 24 octets */
+);
+static void ChapMS_NT(
+	char *rchallenge,
+	int rchallenge_len,
+	char *secret,
+	int secret_len,
+	MS_ChapResponse *response
+);
+static u_char Get7Bits(
+	u_char *input,
+	int startBit
+);
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+void ChapMS(
+	chap_state *cstate,
+	char *rchallenge,
+	int rchallenge_len,
+	char *secret,
+	int secret_len
+)
+{
+	MS_ChapResponse	response;
+#ifdef MSLANMAN
+	extern int ms_lanman;
+#endif
+	
+#if 0
+	CHAPDEBUG((LOG_INFO, "ChapMS: secret is '%.*s'\n", secret_len, secret));
+#endif
+	BZERO(&response, sizeof(response));
+	
+	/* Calculate both always */
+	ChapMS_NT(rchallenge, rchallenge_len, secret, secret_len, &response);
+	
+#ifdef MSLANMAN
+	ChapMS_LANMan(rchallenge, rchallenge_len, secret, secret_len, &response);
+	
+	/* prefered method is set by option  */
+	response.UseNT = !ms_lanman;
+#else
+	response.UseNT = 1;
+#endif
+	
+	BCOPY(&response, cstate->response, MS_CHAP_RESPONSE_LEN);
+	cstate->resp_length = MS_CHAP_RESPONSE_LEN;
+}
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+static void ChallengeResponse(
+	u_char *challenge,	/* IN   8 octets */
+	u_char *pwHash,		/* IN  16 octets */
+	u_char *response	/* OUT 24 octets */
+)
+{
+	char    ZPasswordHash[21];
+	
+	BZERO(ZPasswordHash, sizeof(ZPasswordHash));
+	BCOPY(pwHash, ZPasswordHash, 16);
+	
+#if 0
+	log_packet(ZPasswordHash, sizeof(ZPasswordHash), "ChallengeResponse - ZPasswordHash", LOG_DEBUG);
+#endif
+	
+	DesEncrypt(challenge, ZPasswordHash +  0, response + 0);
+	DesEncrypt(challenge, ZPasswordHash +  7, response + 8);
+	DesEncrypt(challenge, ZPasswordHash + 14, response + 16);
+	
+#if 0
+	log_packet(response, 24, "ChallengeResponse - response", LOG_DEBUG);
+#endif
+}
+
+
+#ifdef USE_CRYPT
+static void DesEncrypt(
+	u_char *clear,	/* IN  8 octets */
+	u_char *key,	/* IN  7 octets */
+	u_char *cipher	/* OUT 8 octets */
+)
+{
+	u_char des_key[8];
+	u_char crypt_key[66];
+	u_char des_input[66];
+	
+	MakeKey(key, des_key);
+	
+	Expand(des_key, crypt_key);
+	setkey(crypt_key);
+	
+#if 0
+	CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet input : %02X%02X%02X%02X%02X%02X%02X%02X\n",
+	       clear[0], clear[1], clear[2], clear[3], clear[4], clear[5], clear[6], clear[7]));
+#endif
+	
+	Expand(clear, des_input);
+	encrypt(des_input, 0);
+	Collapse(des_input, cipher);
+	
+#if 0
+	CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet output: %02X%02X%02X%02X%02X%02X%02X%02X\n",
+	       cipher[0], cipher[1], cipher[2], cipher[3], cipher[4], cipher[5], cipher[6], cipher[7]));
+#endif
+}
+
+#else /* USE_CRYPT */
+
+static void DesEncrypt(
+	u_char *clear,	/* IN  8 octets */
+	u_char *key,	/* IN  7 octets */
+	u_char *cipher	/* OUT 8 octets */
+)
+{
+	des_cblock		des_key;
+	des_key_schedule	key_schedule;
+	
+	MakeKey(key, des_key);
+	
+	des_set_key(&des_key, key_schedule);
+	
+#if 0
+	CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet input : %02X%02X%02X%02X%02X%02X%02X%02X\n",
+	       clear[0], clear[1], clear[2], clear[3], clear[4], clear[5], clear[6], clear[7]));
+#endif
+	
+	des_ecb_encrypt((des_cblock *)clear, (des_cblock *)cipher, key_schedule, 1);
+	
+#if 0
+	CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet output: %02X%02X%02X%02X%02X%02X%02X%02X\n",
+	       cipher[0], cipher[1], cipher[2], cipher[3], cipher[4], cipher[5], cipher[6], cipher[7]));
+#endif
+}
+
+#endif /* USE_CRYPT */
+
+
+static u_char Get7Bits(
+	u_char *input,
+	int startBit
+)
+{
+	register unsigned int	word;
+	
+	word  = (unsigned)input[startBit / 8] << 8;
+	word |= (unsigned)input[startBit / 8 + 1];
+	
+	word >>= 15 - (startBit % 8 + 7);
+	
+	return word & 0xFE;
+}
+
+#ifdef USE_CRYPT
+
+/* in == 8-byte string (expanded version of the 56-bit key)
+ * out == 64-byte string where each byte is either 1 or 0
+ * Note that the low-order "bit" is always ignored by by setkey()
+ */
+static void Expand(u_char *in, u_char *out)
+{
+	int j, c;
+	int i;
+	
+	for(i = 0; i < 64; in++){
+		c = *in;
+		for(j = 7; j >= 0; j--)
+			*out++ = (c >> j) & 01;
+		i += 8;
+	}
+}
+
+/* The inverse of Expand
+ */
+static void Collapse(u_char *in, u_char *out)
+{
+	int j;
+	int i;
+	unsigned int c;
+	
+	for (i = 0; i < 64; i += 8, out++) {
+		c = 0;
+		for (j = 7; j >= 0; j--, in++)
+			c |= *in << j;
+		*out = c & 0xff;
+	}
+}
+#endif
+
+static void MakeKey(
+	u_char *key,		/* IN  56 bit DES key missing parity bits */
+	u_char *des_key		/* OUT 64 bit DES key with parity bits added */
+)
+{
+	des_key[0] = Get7Bits(key,  0);
+	des_key[1] = Get7Bits(key,  7);
+	des_key[2] = Get7Bits(key, 14);
+	des_key[3] = Get7Bits(key, 21);
+	des_key[4] = Get7Bits(key, 28);
+	des_key[5] = Get7Bits(key, 35);
+	des_key[6] = Get7Bits(key, 42);
+	des_key[7] = Get7Bits(key, 49);
+	
+#ifndef USE_CRYPT
+	des_set_odd_parity((des_cblock *)des_key);
+#endif
+	
+#if 0
+	CHAPDEBUG((LOG_INFO, "MakeKey: 56-bit input : %02X%02X%02X%02X%02X%02X%02X\n",
+	       key[0], key[1], key[2], key[3], key[4], key[5], key[6]));
+	CHAPDEBUG((LOG_INFO, "MakeKey: 64-bit output: %02X%02X%02X%02X%02X%02X%02X%02X\n",
+	       des_key[0], des_key[1], des_key[2], des_key[3], des_key[4], des_key[5], des_key[6], des_key[7]));
+#endif
+}
+
+static void ChapMS_NT(
+	char *rchallenge,
+	int rchallenge_len,
+	char *secret,
+	int secret_len,
+	MS_ChapResponse *response
+)
+{
+	int			i;
+	MDstruct	md4Context;
+	u_char		unicodePassword[MAX_NT_PASSWORD * 2];
+	static int	low_byte_first = -1;
+	
+	/* Initialize the Unicode version of the secret (== password). */
+	/* This implicitly supports 8-bit ISO8859/1 characters. */
+	BZERO(unicodePassword, sizeof(unicodePassword));
+	for (i = 0; i < secret_len; i++)
+		unicodePassword[i * 2] = (u_char)secret[i];
+	
+	MDbegin(&md4Context);
+	MDupdate(&md4Context, unicodePassword, secret_len * 2 * 8);	/* Unicode is 2 bytes/char, *8 for bit count */
+	
+	if (low_byte_first == -1)
+		low_byte_first = (htons((unsigned short int)1) != 1);
+	if (low_byte_first == 0)
+		MDreverse((u_long *)&md4Context);  /*  sfb 961105 */
+	
+	MDupdate(&md4Context, NULL, 0);	/* Tell MD4 we're done */
+	
+	ChallengeResponse(rchallenge, (char *)md4Context.buffer, response->NTResp);
+}
+
+#ifdef MSLANMAN
+static u_char *StdText = (u_char *)"KGS!@#$%"; /* key from rasapi32.dll */
+
+static ChapMS_LANMan(
+	char *rchallenge,
+	int rchallenge_len,
+	char *secret,
+	int secret_len,
+	MS_ChapResponse	*response
+)
+{
+	int			i;
+	u_char		UcasePassword[MAX_NT_PASSWORD]; /* max is actually 14 */
+	u_char		PasswordHash[16];
+	
+	/* LANMan password is case insensitive */
+	BZERO(UcasePassword, sizeof(UcasePassword));
+	for (i = 0; i < secret_len; i++)
+		UcasePassword[i] = (u_char)toupper(secret[i]);
+	DesEncrypt( StdText, UcasePassword + 0, PasswordHash + 0 );
+	DesEncrypt( StdText, UcasePassword + 7, PasswordHash + 8 );
+	ChallengeResponse(rchallenge, PasswordHash, response->LANManResp);
+}
+#endif
+
+#endif /* MSCHAP_SUPPORT */
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/chpms.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/chpms.h
new file mode 100644
index 000000000..ccc8b4882
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/chpms.h
@@ -0,0 +1,64 @@
+/*****************************************************************************
+* chpms.h - Network Microsoft Challenge Handshake Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1998 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 98-01-30 Guy Lancaster , Global Election Systems Inc.
+*	Original built from BSD network code.
+******************************************************************************/
+/*
+ * chap.h - Challenge Handshake Authentication Protocol definitions.
+ *
+ * Copyright (c) 1995 Eric Rosenquist, Strata Software Limited.
+ * http://www.strataware.com/
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Eric Rosenquist.  The name of the author may not be used to
+ * endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * $Id: chpms.h,v 1.2 2006/08/29 18:53:47 wolti Exp $
+ */
+
+#ifndef CHPMS_H
+#define CHPMS_H
+
+#define MAX_NT_PASSWORD	256	/* Maximum number of (Unicode) chars in an NT password */
+
+void ChapMS (chap_state *, char *, int, char *, int);
+
+#endif /* CHPMS_H */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/fsm.c b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/fsm.c
new file mode 100644
index 000000000..6cad71525
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/fsm.c
@@ -0,0 +1,838 @@
+/*****************************************************************************
+* fsm.c - Network Control Protocol Finite State Machine program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-01 Guy Lancaster , Global Election Systems Inc.
+*	Original based on BSD fsm.c.
+*****************************************************************************/
+/*
+ * fsm.c - {Link, IP} Control Protocol Finite State Machine.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+
+/*
+ * TODO:
+ * Randomize fsm id on link/init.
+ * Deal with variable outgoing MTU.
+ */
+
+#include "ppp.h"
+#if PPP_SUPPORT > 0
+#include "fsm.h"
+#include "pppdebug.h"
+
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+
+
+/************************/
+/*** LOCAL DATA TYPES ***/
+/************************/
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+static void fsm_timeout (void *);
+static void fsm_rconfreq (fsm *, u_char, u_char *, int);
+static void fsm_rconfack (fsm *, int, u_char *, int);
+static void fsm_rconfnakrej (fsm *, int, int, u_char *, int);
+static void fsm_rtermreq (fsm *, int, u_char *, int);
+static void fsm_rtermack (fsm *);
+static void fsm_rcoderej (fsm *, u_char *, int);
+static void fsm_sconfreq (fsm *, int);
+
+#define PROTO_NAME(f)	((f)->callbacks->proto_name)
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+int peer_mru[NUM_PPP];
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+
+/*
+ * fsm_init - Initialize fsm.
+ *
+ * Initialize fsm state.
+ */
+void fsm_init(fsm *f)
+{
+	f->state = INITIAL;
+	f->flags = 0;
+	f->id = 0;				/* XXX Start with random id? */
+	f->timeouttime = FSM_DEFTIMEOUT;
+	f->maxconfreqtransmits = FSM_DEFMAXCONFREQS;
+	f->maxtermtransmits = FSM_DEFMAXTERMREQS;
+	f->maxnakloops = FSM_DEFMAXNAKLOOPS;
+	f->term_reason_len = 0;
+}
+
+
+/*
+ * fsm_lowerup - The lower layer is up.
+ */
+void fsm_lowerup(fsm *f)
+{
+	int oldState = f->state;
+
+	switch( f->state ){
+	case INITIAL:
+		f->state = CLOSED;
+		break;
+	
+	case STARTING:
+		if( f->flags & OPT_SILENT )
+			f->state = STOPPED;
+		else {
+			/* Send an initial configure-request */
+			fsm_sconfreq(f, 0);
+			f->state = REQSENT;
+		}
+	break;
+	
+	default:
+		FSMDEBUG((LOG_INFO, "%s: Up event in state %d!\n",
+				PROTO_NAME(f), f->state));
+	}
+	
+	FSMDEBUG((LOG_INFO, "%s: lowerup state %d -> %d\n",
+			PROTO_NAME(f), oldState, f->state));
+}
+
+
+/*
+ * fsm_lowerdown - The lower layer is down.
+ *
+ * Cancel all timeouts and inform upper layers.
+ */
+void fsm_lowerdown(fsm *f)
+{
+	int oldState = f->state;
+	
+	switch( f->state ){
+	case CLOSED:
+		f->state = INITIAL;
+		break;
+	
+	case STOPPED:
+		f->state = STARTING;
+		if( f->callbacks->starting )
+			(*f->callbacks->starting)(f);
+		break;
+	
+	case CLOSING:
+		f->state = INITIAL;
+		UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+		break;
+	
+	case STOPPING:
+	case REQSENT:
+	case ACKRCVD:
+	case ACKSENT:
+		f->state = STARTING;
+		UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+		break;
+	
+	case OPENED:
+		if( f->callbacks->down )
+			(*f->callbacks->down)(f);
+		f->state = STARTING;
+		break;
+	
+	default:
+		FSMDEBUG((LOG_INFO, "%s: Down event in state %d!\n",
+				PROTO_NAME(f), f->state));
+	}
+	
+	FSMDEBUG((LOG_INFO, "%s: lowerdown state %d -> %d\n",
+			PROTO_NAME(f), oldState, f->state));
+}
+
+
+/*
+ * fsm_open - Link is allowed to come up.
+ */
+void fsm_open(fsm *f)
+{
+	int oldState = f->state;
+	
+	switch( f->state ){
+		case INITIAL:
+			f->state = STARTING;
+			if( f->callbacks->starting )
+				(*f->callbacks->starting)(f);
+			break;
+		
+		case CLOSED:
+		if( f->flags & OPT_SILENT )
+			f->state = STOPPED;
+		else {
+			/* Send an initial configure-request */
+			fsm_sconfreq(f, 0);
+			f->state = REQSENT;
+		}
+		break;
+	
+	case CLOSING:
+		f->state = STOPPING;
+		/* fall through */
+	case STOPPED:
+	case OPENED:
+		if( f->flags & OPT_RESTART ){
+			fsm_lowerdown(f);
+			fsm_lowerup(f);
+		}
+		break;
+	}
+	
+	FSMDEBUG((LOG_INFO, "%s: open state %d -> %d\n",
+			PROTO_NAME(f), oldState, f->state));
+}
+
+
+/*
+ * fsm_close - Start closing connection.
+ *
+ * Cancel timeouts and either initiate close or possibly go directly to
+ * the CLOSED state.
+ */
+void fsm_close(fsm *f, char *reason)
+{
+	int oldState = f->state;
+	
+	f->term_reason = reason;
+	f->term_reason_len = (reason == NULL? 0: strlen(reason));
+	switch( f->state ){
+	case STARTING:
+		f->state = INITIAL;
+		break;
+	case STOPPED:
+		f->state = CLOSED;
+		break;
+	case STOPPING:
+		f->state = CLOSING;
+		break;
+	
+	case REQSENT:
+	case ACKRCVD:
+	case ACKSENT:
+	case OPENED:
+		if( f->state != OPENED )
+			UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+		else if( f->callbacks->down )
+			(*f->callbacks->down)(f);	/* Inform upper layers we're down */
+		
+		/* Init restart counter, send Terminate-Request */
+		f->retransmits = f->maxtermtransmits;
+		fsm_sdata(f, TERMREQ, f->reqid = ++f->id,
+					(u_char *) f->term_reason, f->term_reason_len);
+		TIMEOUT(fsm_timeout, f, f->timeouttime);
+		--f->retransmits;
+		
+		f->state = CLOSING;
+		break;
+	}
+	
+	FSMDEBUG((LOG_INFO, "%s: close reason=%s state %d -> %d\n",
+			PROTO_NAME(f), reason, oldState, f->state));
+}
+
+
+/*
+ * fsm_sdata - Send some data.
+ *
+ * Used for all packets sent to our peer by this module.
+ */
+void fsm_sdata(
+	fsm *f,
+	u_char code, 
+	u_char id,
+	u_char *data,
+	int datalen
+)
+{
+	u_char *outp;
+	int outlen;
+	
+	/* Adjust length to be smaller than MTU */
+	outp = outpacket_buf[f->unit];
+	if (datalen > peer_mru[f->unit] - (int)HEADERLEN)
+		datalen = peer_mru[f->unit] - HEADERLEN;
+	if (datalen && data != outp + PPP_HDRLEN + HEADERLEN)
+		BCOPY(data, outp + PPP_HDRLEN + HEADERLEN, datalen);
+	outlen = datalen + HEADERLEN;
+	MAKEHEADER(outp, f->protocol);
+	PUTCHAR(code, outp);
+	PUTCHAR(id, outp);
+	PUTSHORT(outlen, outp);
+	pppWrite(f->unit, outpacket_buf[f->unit], outlen + PPP_HDRLEN);
+	FSMDEBUG((LOG_INFO, "fsm_sdata(%s): Sent code %d,%d,%d.\n",
+				PROTO_NAME(f), code, id, outlen));
+}
+
+
+/*
+ * fsm_input - Input packet.
+ */
+void fsm_input(fsm *f, u_char *inpacket, int l)
+{
+	u_char *inp = inpacket;
+	u_char code, id;
+	int len;
+	
+	/*
+	* Parse header (code, id and length).
+	* If packet too short, drop it.
+	*/
+	if (l < HEADERLEN) {
+		FSMDEBUG((LOG_WARNING, "fsm_input(%x): Rcvd short header.\n",
+					f->protocol));
+		return;
+	}
+	GETCHAR(code, inp);
+	GETCHAR(id, inp);
+	GETSHORT(len, inp);
+	if (len < HEADERLEN) {
+		FSMDEBUG((LOG_INFO, "fsm_input(%x): Rcvd illegal length.\n",
+				f->protocol));
+		return;
+	}
+	if (len > l) {
+		FSMDEBUG((LOG_INFO, "fsm_input(%x): Rcvd short packet.\n",
+				f->protocol));
+		return;
+	}
+	len -= HEADERLEN;		/* subtract header length */
+	
+	if( f->state == INITIAL || f->state == STARTING ){
+		FSMDEBUG((LOG_INFO, "fsm_input(%x): Rcvd packet in state %d.\n",
+				f->protocol, f->state));
+		return;
+	}
+	FSMDEBUG((LOG_INFO, "fsm_input(%s):%d,%d,%d\n", PROTO_NAME(f), code, id, l));
+	/*
+	 * Action depends on code.
+	 */
+	switch (code) {
+	case CONFREQ:
+		fsm_rconfreq(f, id, inp, len);
+		break;
+	
+	case CONFACK:
+		fsm_rconfack(f, id, inp, len);
+		break;
+	
+	case CONFNAK:
+	case CONFREJ:
+		fsm_rconfnakrej(f, code, id, inp, len);
+		break;
+	
+	case TERMREQ:
+		fsm_rtermreq(f, id, inp, len);
+		break;
+	
+	case TERMACK:
+		fsm_rtermack(f);
+		break;
+	
+	case CODEREJ:
+		fsm_rcoderej(f, inp, len);
+		break;
+	
+	default:
+		if( !f->callbacks->extcode
+				|| !(*f->callbacks->extcode)(f, code, id, inp, len) )
+			fsm_sdata(f, CODEREJ, ++f->id, inpacket, len + HEADERLEN);
+		break;
+	}
+}
+
+
+/*
+ * fsm_protreject - Peer doesn't speak this protocol.
+ *
+ * Treat this as a catastrophic error (RXJ-).
+ */
+void fsm_protreject(fsm *f)
+{
+	switch( f->state ){
+	case CLOSING:
+		UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+		/* fall through */
+	case CLOSED:
+		f->state = CLOSED;
+		if( f->callbacks->finished )
+			(*f->callbacks->finished)(f);
+		break;
+	
+	case STOPPING:
+	case REQSENT:
+	case ACKRCVD:
+	case ACKSENT:
+		UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+		/* fall through */
+	case STOPPED:
+		f->state = STOPPED;
+		if( f->callbacks->finished )
+			(*f->callbacks->finished)(f);
+		break;
+	
+	case OPENED:
+		if( f->callbacks->down )
+			(*f->callbacks->down)(f);
+		
+		/* Init restart counter, send Terminate-Request */
+		f->retransmits = f->maxtermtransmits;
+		fsm_sdata(f, TERMREQ, f->reqid = ++f->id,
+					(u_char *) f->term_reason, f->term_reason_len);
+		TIMEOUT(fsm_timeout, f, f->timeouttime);
+		--f->retransmits;
+		
+		f->state = STOPPING;
+		break;
+	
+	default:
+		FSMDEBUG((LOG_INFO, "%s: Protocol-reject event in state %d!\n",
+					PROTO_NAME(f), f->state));
+	}
+}
+
+
+
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+
+/*
+ * fsm_timeout - Timeout expired.
+ */
+static void fsm_timeout(void *arg)
+{
+    fsm *f = (fsm *) arg;
+
+    switch (f->state) {
+    case CLOSING:
+    case STOPPING:
+		if( f->retransmits <= 0 ){
+		    FSMDEBUG((LOG_WARNING, "%s: timeout sending Terminate-Request state=%d\n",
+					   PROTO_NAME(f), f->state));
+		    /*
+		     * We've waited for an ack long enough.  Peer probably heard us.
+		     */
+		    f->state = (f->state == CLOSING)? CLOSED: STOPPED;
+		    if( f->callbacks->finished )
+			(*f->callbacks->finished)(f);
+		} else {
+		    FSMDEBUG((LOG_WARNING, "%s: timeout resending Terminate-Requests state=%d\n",
+					   PROTO_NAME(f), f->state));
+		    /* Send Terminate-Request */
+		    fsm_sdata(f, TERMREQ, f->reqid = ++f->id,
+			      (u_char *) f->term_reason, f->term_reason_len);
+		    TIMEOUT(fsm_timeout, f, f->timeouttime);
+		    --f->retransmits;
+		}
+		break;
+
+    case REQSENT:
+    case ACKRCVD:
+    case ACKSENT:
+		if (f->retransmits <= 0) {
+		    FSMDEBUG((LOG_WARNING, "%s: timeout sending Config-Requests state=%d\n",
+			   PROTO_NAME(f), f->state));
+		    f->state = STOPPED;
+		    if( (f->flags & OPT_PASSIVE) == 0 && f->callbacks->finished )
+				(*f->callbacks->finished)(f);
+	
+		} else {
+		    FSMDEBUG((LOG_WARNING, "%s: timeout resending Config-Request state=%d\n",
+			   PROTO_NAME(f), f->state));
+		    /* Retransmit the configure-request */
+		    if (f->callbacks->retransmit)
+				(*f->callbacks->retransmit)(f);
+		    fsm_sconfreq(f, 1);		/* Re-send Configure-Request */
+		    if( f->state == ACKRCVD )
+				f->state = REQSENT;
+		}
+		break;
+
+    default:
+		FSMDEBUG((LOG_INFO, "%s: Timeout event in state %d!\n",
+				  PROTO_NAME(f), f->state));
+	    }
+}
+
+
+/*
+ * fsm_rconfreq - Receive Configure-Request.
+ */
+static void fsm_rconfreq(fsm *f, u_char id, u_char *inp, int len)
+{
+	int code, reject_if_disagree;
+	
+	FSMDEBUG((LOG_INFO, "fsm_rconfreq(%s): Rcvd id %d state=%d\n", 
+				PROTO_NAME(f), id, f->state));
+	switch( f->state ){
+	case CLOSED:
+		/* Go away, we're closed */
+		fsm_sdata(f, TERMACK, id, NULL, 0);
+		return;
+	case CLOSING:
+	case STOPPING:
+		return;
+	
+	case OPENED:
+		/* Go down and restart negotiation */
+		if( f->callbacks->down )
+			(*f->callbacks->down)(f);	/* Inform upper layers */
+		fsm_sconfreq(f, 0);		/* Send initial Configure-Request */
+		break;
+	
+	case STOPPED:
+		/* Negotiation started by our peer */
+		fsm_sconfreq(f, 0);		/* Send initial Configure-Request */
+		f->state = REQSENT;
+		break;
+	}
+	
+	/*
+	* Pass the requested configuration options
+	* to protocol-specific code for checking.
+	*/
+	if (f->callbacks->reqci){		/* Check CI */
+		reject_if_disagree = (f->nakloops >= f->maxnakloops);
+		code = (*f->callbacks->reqci)(f, inp, &len, reject_if_disagree);
+	} 
+	else if (len)
+		code = CONFREJ;			/* Reject all CI */
+	else
+		code = CONFACK;
+	
+	/* send the Ack, Nak or Rej to the peer */
+	fsm_sdata(f, (u_char)code, id, inp, len);
+	
+	if (code == CONFACK) {
+		if (f->state == ACKRCVD) {
+			UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+			f->state = OPENED;
+			if (f->callbacks->up)
+				(*f->callbacks->up)(f);	/* Inform upper layers */
+		} 
+		else
+			f->state = ACKSENT;
+		f->nakloops = 0;
+	} 
+	else {
+		/* we sent CONFACK or CONFREJ */
+		if (f->state != ACKRCVD)
+			f->state = REQSENT;
+		if( code == CONFNAK )
+			++f->nakloops;
+	}
+}
+
+
+/*
+ * fsm_rconfack - Receive Configure-Ack.
+ */
+static void fsm_rconfack(fsm *f, int id, u_char *inp, int len)
+{
+	FSMDEBUG((LOG_INFO, "fsm_rconfack(%s): Rcvd id %d state=%d\n",
+				PROTO_NAME(f), id, f->state));
+	
+	if (id != f->reqid || f->seen_ack)		/* Expected id? */
+		return;					/* Nope, toss... */
+	if( !(f->callbacks->ackci? (*f->callbacks->ackci)(f, inp, len):
+								(len == 0)) ){
+		/* Ack is bad - ignore it */
+		FSMDEBUG((LOG_INFO, "%s: received bad Ack (length %d)\n",
+					PROTO_NAME(f), len));
+		return;
+	}
+	f->seen_ack = 1;
+	
+	switch (f->state) {
+	case CLOSED:
+	case STOPPED:
+		fsm_sdata(f, TERMACK, (u_char)id, NULL, 0);
+		break;
+	
+	case REQSENT:
+		f->state = ACKRCVD;
+		f->retransmits = f->maxconfreqtransmits;
+		break;
+	
+	case ACKRCVD:
+		/* Huh? an extra valid Ack? oh well... */
+		UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+		fsm_sconfreq(f, 0);
+		f->state = REQSENT;
+		break;
+	
+	case ACKSENT:
+		UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+		f->state = OPENED;
+		f->retransmits = f->maxconfreqtransmits;
+		if (f->callbacks->up)
+			(*f->callbacks->up)(f);	/* Inform upper layers */
+		break;
+	
+	case OPENED:
+		/* Go down and restart negotiation */
+		if (f->callbacks->down)
+			(*f->callbacks->down)(f);	/* Inform upper layers */
+		fsm_sconfreq(f, 0);		/* Send initial Configure-Request */
+		f->state = REQSENT;
+		break;
+	}
+}
+
+
+/*
+ * fsm_rconfnakrej - Receive Configure-Nak or Configure-Reject.
+ */
+static void fsm_rconfnakrej(fsm *f, int code, int id, u_char *inp, int len)
+{
+	int (*proc) (fsm *, u_char *, int);
+	int ret;
+	
+	FSMDEBUG((LOG_INFO, "fsm_rconfnakrej(%s): Rcvd id %d state=%d\n",
+				PROTO_NAME(f), id, f->state));
+	
+	if (id != f->reqid || f->seen_ack)	/* Expected id? */
+		return;				/* Nope, toss... */
+	proc = (code == CONFNAK)? f->callbacks->nakci: f->callbacks->rejci;
+	if (!proc || !(ret = proc(f, inp, len))) {
+		/* Nak/reject is bad - ignore it */
+		FSMDEBUG((LOG_INFO, "%s: received bad %s (length %d)\n",
+					PROTO_NAME(f), (code==CONFNAK? "Nak": "reject"), len));
+		return;
+	}
+	f->seen_ack = 1;
+	
+	switch (f->state) {
+	case CLOSED:
+	case STOPPED:
+		fsm_sdata(f, TERMACK, (u_char)id, NULL, 0);
+		break;
+	
+	case REQSENT:
+	case ACKSENT:
+		/* They didn't agree to what we wanted - try another request */
+		UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+		if (ret < 0)
+			f->state = STOPPED;		/* kludge for stopping CCP */
+		else
+			fsm_sconfreq(f, 0);		/* Send Configure-Request */
+		break;
+	
+	case ACKRCVD:
+		/* Got a Nak/reject when we had already had an Ack?? oh well... */
+		UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
+		fsm_sconfreq(f, 0);
+		f->state = REQSENT;
+		break;
+	
+	case OPENED:
+		/* Go down and restart negotiation */
+		if (f->callbacks->down)
+			(*f->callbacks->down)(f);	/* Inform upper layers */
+		fsm_sconfreq(f, 0);		/* Send initial Configure-Request */
+		f->state = REQSENT;
+		break;
+	}
+}
+
+
+/*
+ * fsm_rtermreq - Receive Terminate-Req.
+ */
+static void fsm_rtermreq(fsm *f, int id, u_char *p, int len)
+{
+	FSMDEBUG((LOG_INFO, "fsm_rtermreq(%s): Rcvd id %d state=%d\n",
+				PROTO_NAME(f), id, f->state));
+	
+	switch (f->state) {
+	case ACKRCVD:
+	case ACKSENT:
+		f->state = REQSENT;		/* Start over but keep trying */
+		break;
+	
+	case OPENED:
+		if (len > 0) {
+			FSMDEBUG((LOG_INFO, "%s terminated by peer (%x)\n", PROTO_NAME(f), p));
+		} else {
+			FSMDEBUG((LOG_INFO, "%s terminated by peer\n", PROTO_NAME(f)));
+		}
+		if (f->callbacks->down)
+			(*f->callbacks->down)(f);	/* Inform upper layers */
+		f->retransmits = 0;
+		f->state = STOPPING;
+		TIMEOUT(fsm_timeout, f, f->timeouttime);
+		break;
+	}
+	
+	fsm_sdata(f, TERMACK, (u_char)id, NULL, 0);
+}
+
+
+/*
+ * fsm_rtermack - Receive Terminate-Ack.
+ */
+static void fsm_rtermack(fsm *f)
+{
+	FSMDEBUG((LOG_INFO, "fsm_rtermack(%s): state=%d\n", 
+				PROTO_NAME(f), f->state));
+	
+	switch (f->state) {
+	case CLOSING:
+		UNTIMEOUT(fsm_timeout, f);
+		f->state = CLOSED;
+		if( f->callbacks->finished )
+			(*f->callbacks->finished)(f);
+		break;
+	case STOPPING:
+		UNTIMEOUT(fsm_timeout, f);
+		f->state = STOPPED;
+		if( f->callbacks->finished )
+			(*f->callbacks->finished)(f);
+		break;
+	
+	case ACKRCVD:
+		f->state = REQSENT;
+		break;
+	
+	case OPENED:
+		if (f->callbacks->down)
+			(*f->callbacks->down)(f);	/* Inform upper layers */
+		fsm_sconfreq(f, 0);
+		break;
+	}
+}
+
+
+/*
+ * fsm_rcoderej - Receive an Code-Reject.
+ */
+static void fsm_rcoderej(fsm *f, u_char *inp, int len)
+{
+	u_char code, id;
+	
+	FSMDEBUG((LOG_INFO, "fsm_rcoderej(%s): state=%d\n", 
+				PROTO_NAME(f), f->state));
+	
+	if (len < HEADERLEN) {
+		FSMDEBUG((LOG_INFO, "fsm_rcoderej: Rcvd short Code-Reject packet!\n"));
+		return;
+	}
+	GETCHAR(code, inp);
+	GETCHAR(id, inp);
+	FSMDEBUG((LOG_WARNING, "%s: Rcvd Code-Reject for code %d, id %d\n",
+				PROTO_NAME(f), code, id));
+	
+	if( f->state == ACKRCVD )
+		f->state = REQSENT;
+}
+
+
+/*
+ * fsm_sconfreq - Send a Configure-Request.
+ */
+static void fsm_sconfreq(fsm *f, int retransmit)
+{
+	u_char *outp;
+	int cilen;
+	
+	if( f->state != REQSENT && f->state != ACKRCVD && f->state != ACKSENT ){
+		/* Not currently negotiating - reset options */
+		if( f->callbacks->resetci )
+			(*f->callbacks->resetci)(f);
+		f->nakloops = 0;
+		}
+	
+	if( !retransmit ){
+		/* New request - reset retransmission counter, use new ID */
+		f->retransmits = f->maxconfreqtransmits;
+		f->reqid = ++f->id;
+	}
+	
+	f->seen_ack = 0;
+	
+	/*
+	 * Make up the request packet
+	 */
+	outp = outpacket_buf[f->unit] + PPP_HDRLEN + HEADERLEN;
+	if( f->callbacks->cilen && f->callbacks->addci ){
+		cilen = (*f->callbacks->cilen)(f);
+		if( cilen > peer_mru[f->unit] - (int)HEADERLEN )
+			cilen = peer_mru[f->unit] - HEADERLEN;
+		if (f->callbacks->addci)
+			(*f->callbacks->addci)(f, outp, &cilen);
+	} else
+		cilen = 0;
+	
+	/* send the request to our peer */
+	fsm_sdata(f, CONFREQ, f->reqid, outp, cilen);
+	
+	/* start the retransmit timer */
+	--f->retransmits;
+	TIMEOUT(fsm_timeout, f, f->timeouttime);
+	
+	FSMDEBUG((LOG_INFO, "%s: sending Configure-Request, id %d\n",
+				PROTO_NAME(f), f->reqid));
+}
+
+#endif /* PPP_SUPPORT */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/fsm.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/fsm.h
new file mode 100644
index 000000000..9edd4d29e
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/fsm.h
@@ -0,0 +1,187 @@
+/*****************************************************************************
+* fsm.h - Network Control Protocol Finite State Machine header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-11-05 Guy Lancaster , Global Election Systems Inc.
+*	Original based on BSD code.
+*****************************************************************************/
+/*
+ * fsm.h - {Link, IP} Control Protocol Finite State Machine definitions.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * $Id: fsm.h,v 1.2 2006/08/29 18:53:47 wolti Exp $
+ */
+
+#ifndef FSM_H
+#define FSM_H
+
+
+/*****************************************************************************
+************************* PUBLIC DEFINITIONS *********************************
+*****************************************************************************/
+/*
+ * LCP Packet header = Code, id, length.
+ */
+#define HEADERLEN	(sizeof (u_char) + sizeof (u_char) + sizeof (u_short))
+
+
+/*
+ *  CP (LCP, IPCP, etc.) codes.
+ */
+#define CONFREQ		1		/* Configuration Request */
+#define CONFACK		2		/* Configuration Ack */
+#define CONFNAK		3		/* Configuration Nak */
+#define CONFREJ		4		/* Configuration Reject */
+#define TERMREQ		5		/* Termination Request */
+#define TERMACK		6		/* Termination Ack */
+#define CODEREJ		7		/* Code Reject */
+
+/*
+ * Link states.
+ */
+#define INITIAL		0		/* Down, hasn't been opened */
+#define STARTING	1		/* Down, been opened */
+#define CLOSED		2		/* Up, hasn't been opened */
+#define STOPPED		3		/* Open, waiting for down event */
+#define CLOSING		4		/* Terminating the connection, not open */
+#define STOPPING	5		/* Terminating, but open */
+#define REQSENT		6		/* We've sent a Config Request */
+#define ACKRCVD		7		/* We've received a Config Ack */
+#define ACKSENT		8		/* We've sent a Config Ack */
+#define OPENED		9		/* Connection available */
+
+
+/*
+ * Flags - indicate options controlling FSM operation
+ */
+#define OPT_PASSIVE	1		/* Don't die if we don't get a response */
+#define OPT_RESTART	2		/* Treat 2nd OPEN as DOWN, UP */
+#define OPT_SILENT	4		/* Wait for peer to speak first */
+
+
+/*****************************************************************************
+************************* PUBLIC DATA TYPES **********************************
+*****************************************************************************/
+/*
+ * Each FSM is described by an fsm structure and fsm callbacks.
+ */
+typedef struct fsm {
+    int unit;				/* Interface unit number */
+    u_short protocol;		/* Data Link Layer Protocol field value */
+    int state;				/* State */
+    int flags;				/* Contains option bits */
+    u_char id;				/* Current id */
+    u_char reqid;			/* Current request id */
+    u_char seen_ack;		/* Have received valid Ack/Nak/Rej to Req */
+    int timeouttime;		/* Timeout time in milliseconds */
+    int maxconfreqtransmits;/* Maximum Configure-Request transmissions */
+    int retransmits;		/* Number of retransmissions left */
+    int maxtermtransmits;	/* Maximum Terminate-Request transmissions */
+    int nakloops;			/* Number of nak loops since last ack */
+    int maxnakloops;		/* Maximum number of nak loops tolerated */
+    struct fsm_callbacks* callbacks;/* Callback routines */
+    char* term_reason;		/* Reason for closing protocol */
+    int term_reason_len;	/* Length of term_reason */
+} fsm;
+
+
+typedef struct fsm_callbacks {
+    void (*resetci)			/* Reset our Configuration Information */
+		(fsm*);
+    int  (*cilen)			/* Length of our Configuration Information */
+		(fsm*);
+    void (*addci) 			/* Add our Configuration Information */
+		(fsm*, u_char*, int*);
+    int  (*ackci)			/* ACK our Configuration Information */
+		(fsm*, u_char*, int);
+    int  (*nakci)			/* NAK our Configuration Information */
+		(fsm*, u_char*, int);
+    int  (*rejci)			/* Reject our Configuration Information */
+		(fsm*, u_char*, int);
+    int  (*reqci)			/* Request peer's Configuration Information */
+		(fsm*, u_char*, int*, int);
+    void (*up)				/* Called when fsm reaches OPENED state */
+		(fsm*);
+    void (*down)			/* Called when fsm leaves OPENED state */
+		(fsm*);
+    void (*starting)		/* Called when we want the lower layer */
+		(fsm*);
+    void (*finished)		/* Called when we don't want the lower layer */
+		(fsm*);
+    void (*protreject)		/* Called when Protocol-Reject received */
+		(int);
+    void (*retransmit)		/* Retransmission is necessary */
+		(fsm*);
+    int  (*extcode)			/* Called when unknown code received */
+		(fsm*, int, u_char, u_char*, int);
+    char *proto_name;		/* String name for protocol (for messages) */
+} fsm_callbacks;
+
+
+/*****************************************************************************
+*********************** PUBLIC DATA STRUCTURES *******************************
+*****************************************************************************/
+/*
+ * Variables
+ */
+extern int peer_mru[];		/* currently negotiated peer MRU (per unit) */
+
+
+/*****************************************************************************
+************************** PUBLIC FUNCTIONS **********************************
+*****************************************************************************/
+
+/*
+ * Prototypes
+ */
+void fsm_init (fsm*);
+void fsm_lowerup (fsm*);
+void fsm_lowerdown (fsm*);
+void fsm_open (fsm*);
+void fsm_close (fsm*, char*);
+void fsm_input (fsm*, u_char*, int);
+void fsm_protreject (fsm*);
+void fsm_sdata (fsm*, u_char, u_char, u_char*, int);
+
+
+#endif /* FSM_H */
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/ipcp.c b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/ipcp.c
new file mode 100644
index 000000000..ec3207a0c
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/ipcp.c
@@ -0,0 +1,1377 @@
+/*****************************************************************************
+* ipcp.c - Network PPP IP Control Protocol program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-08 Guy Lancaster , Global Election Systems Inc.
+*	Original.
+*****************************************************************************/
+/*
+ * ipcp.c - PPP IP Control Protocol.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include 
+
+#include "ppp.h"
+#if PPP_SUPPORT > 0
+#include "auth.h"
+#include "fsm.h"
+#include "vj.h"
+#include "ipcp.h"
+#include "pppdebug.h"
+
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+/* #define OLD_CI_ADDRS 1 */	/* Support deprecated address negotiation. */
+
+/*
+ * Lengths of configuration options.
+ */
+#define CILEN_VOID	2
+#define CILEN_COMPRESS	4	/* min length for compression protocol opt. */
+#define CILEN_VJ	6	/* length for RFC1332 Van-Jacobson opt. */
+#define CILEN_ADDR	6	/* new-style single address option */
+#define CILEN_ADDRS	10	/* old-style dual address option */
+
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+/*
+ * Callbacks for fsm code.  (CI = Configuration Information)
+ */
+static void ipcp_resetci (fsm *);	/* Reset our CI */
+static int  ipcp_cilen (fsm *);	        /* Return length of our CI */
+static void ipcp_addci (fsm *, u_char *, int *); /* Add our CI */
+static int  ipcp_ackci (fsm *, u_char *, int);	/* Peer ack'd our CI */
+static int  ipcp_nakci (fsm *, u_char *, int);	/* Peer nak'd our CI */
+static int  ipcp_rejci (fsm *, u_char *, int);	/* Peer rej'd our CI */
+static int  ipcp_reqci (fsm *, u_char *, int *, int); /* Rcv CI */
+static void ipcp_up (fsm *);		/* We're UP */
+static void ipcp_down (fsm *);		/* We're DOWN */
+#if 0
+static void ipcp_script (fsm *, char *); /* Run an up/down script */
+#endif
+static void ipcp_finished (fsm *);	/* Don't need lower layer */
+
+/*
+ * Protocol entry points from main code.
+ */
+static void ipcp_init (int);
+static void ipcp_open (int);
+static void ipcp_close (int, char *);
+static void ipcp_lowerup (int);
+static void ipcp_lowerdown (int);
+static void ipcp_input (int, u_char *, int);
+static void ipcp_protrej (int);
+
+static void ipcp_clear_addrs (int);
+
+#define CODENAME(x)	((x) == CONFACK ? "ACK" : \
+			 (x) == CONFNAK ? "NAK" : "REJ")
+
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+/* global vars */
+ipcp_options ipcp_wantoptions[NUM_PPP];	/* Options that we want to request */
+ipcp_options ipcp_gotoptions[NUM_PPP];	/* Options that peer ack'd */
+ipcp_options ipcp_allowoptions[NUM_PPP];	/* Options we allow peer to request */
+ipcp_options ipcp_hisoptions[NUM_PPP];	/* Options that we ack'd */
+
+fsm ipcp_fsm[NUM_PPP];		/* IPCP fsm structure */
+
+struct protent ipcp_protent = {
+    PPP_IPCP,
+    ipcp_init,
+    ipcp_input,
+    ipcp_protrej,
+    ipcp_lowerup,
+    ipcp_lowerdown,
+    ipcp_open,
+    ipcp_close,
+#if 0
+    ipcp_printpkt,
+    NULL,
+#endif
+    1,
+    "IPCP",
+#if 0
+    ip_check_options,
+    NULL,
+    ip_active_pkt
+#endif
+};
+
+
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+/* local vars */
+static int cis_received[NUM_PPP];		/* # Conf-Reqs received */
+static int default_route_set[NUM_PPP];	/* Have set up a default route */
+
+static fsm_callbacks ipcp_callbacks = { /* IPCP callback routines */
+    ipcp_resetci,		/* Reset our Configuration Information */
+    ipcp_cilen,			/* Length of our Configuration Information */
+    ipcp_addci,			/* Add our Configuration Information */
+    ipcp_ackci,			/* ACK our Configuration Information */
+    ipcp_nakci,			/* NAK our Configuration Information */
+    ipcp_rejci,			/* Reject our Configuration Information */
+    ipcp_reqci,			/* Request peer's Configuration Information */
+    ipcp_up,			/* Called when fsm reaches OPENED state */
+    ipcp_down,			/* Called when fsm leaves OPENED state */
+    NULL,				/* Called when we want the lower layer up */
+    ipcp_finished,		/* Called when we want the lower layer down */
+    NULL,				/* Called when Protocol-Reject received */
+    NULL,				/* Retransmission is necessary */
+    NULL,				/* Called to handle protocol-specific codes */
+    "IPCP"				/* String name of protocol */
+};
+
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+
+/*
+ * Non-standard inet_ntoa left here for compat with original ppp
+ * sources. Assumes u32_t instead of struct in_addr.
+ */ 
+
+char * _inet_ntoa(u32_t n)
+{
+	struct in_addr ia;
+	ia.s_addr = n;
+	return inet_ntoa(ia);
+}
+
+#define inet_ntoa _inet_ntoa
+
+/*
+ * ipcp_init - Initialize IPCP.
+ */
+static void ipcp_init(int unit)
+{
+	fsm *f = &ipcp_fsm[unit];
+	ipcp_options *wo = &ipcp_wantoptions[unit];
+	ipcp_options *ao = &ipcp_allowoptions[unit];
+	
+	f->unit = unit;
+	f->protocol = PPP_IPCP;
+	f->callbacks = &ipcp_callbacks;
+	fsm_init(&ipcp_fsm[unit]);
+	
+	memset(wo, 0, sizeof(*wo));
+	memset(ao, 0, sizeof(*ao));
+	
+	wo->neg_addr = 1;
+	wo->ouraddr = 0;
+#if VJ_SUPPORT > 0
+	wo->neg_vj = 1;
+#else
+	wo->neg_vj = 0;
+#endif
+	wo->vj_protocol = IPCP_VJ_COMP;
+	wo->maxslotindex = MAX_SLOTS - 1;
+	wo->cflag = 0;
+	
+	wo->default_route = 1;
+	
+	ao->neg_addr = 1;
+#if VJ_SUPPORT > 0
+	ao->neg_vj = 1;
+#else
+	ao->neg_vj = 0;
+#endif
+	ao->maxslotindex = MAX_SLOTS - 1;
+	ao->cflag = 1;
+	
+	ao->default_route = 1;
+}
+
+
+/*
+ * ipcp_open - IPCP is allowed to come up.
+ */
+static void ipcp_open(int unit)
+{
+	fsm_open(&ipcp_fsm[unit]);
+}
+
+
+/*
+ * ipcp_close - Take IPCP down.
+ */
+static void ipcp_close(int unit, char *reason)
+{
+	fsm_close(&ipcp_fsm[unit], reason);
+}
+
+
+/*
+ * ipcp_lowerup - The lower layer is up.
+ */
+static void ipcp_lowerup(int unit)
+{
+	fsm_lowerup(&ipcp_fsm[unit]);
+}
+
+
+/*
+ * ipcp_lowerdown - The lower layer is down.
+ */
+static void ipcp_lowerdown(int unit)
+{
+	fsm_lowerdown(&ipcp_fsm[unit]);
+}
+
+
+/*
+ * ipcp_input - Input IPCP packet.
+ */
+static void ipcp_input(int unit, u_char *p, int len)
+{
+	fsm_input(&ipcp_fsm[unit], p, len);
+}
+
+
+/*
+ * ipcp_protrej - A Protocol-Reject was received for IPCP.
+ *
+ * Pretend the lower layer went down, so we shut up.
+ */
+static void ipcp_protrej(int unit)
+{
+	fsm_lowerdown(&ipcp_fsm[unit]);
+}
+
+
+/*
+ * ipcp_resetci - Reset our CI.
+ */
+static void ipcp_resetci(fsm *f)
+{
+	ipcp_options *wo = &ipcp_wantoptions[f->unit];
+	
+	wo->req_addr = wo->neg_addr && ipcp_allowoptions[f->unit].neg_addr;
+	if (wo->ouraddr == 0)
+		wo->accept_local = 1;
+	if (wo->hisaddr == 0)
+		wo->accept_remote = 1;
+	/* Request DNS addresses from the peer */
+	wo->req_dns1 = ppp_settings.usepeerdns;
+	wo->req_dns2 = ppp_settings.usepeerdns;
+	ipcp_gotoptions[f->unit] = *wo;
+	cis_received[f->unit] = 0;
+}
+
+
+/*
+ * ipcp_cilen - Return length of our CI.
+ */
+static int ipcp_cilen(fsm *f)
+{
+	ipcp_options *go = &ipcp_gotoptions[f->unit];
+	ipcp_options *wo = &ipcp_wantoptions[f->unit];
+	ipcp_options *ho = &ipcp_hisoptions[f->unit];
+	
+#define LENCIVJ(neg, old)	(neg ? (old? CILEN_COMPRESS : CILEN_VJ) : 0)
+#define LENCIADDR(neg, old)	(neg ? (old? CILEN_ADDRS : CILEN_ADDR) : 0)
+#define LENCIDNS(neg)		(neg ? (CILEN_ADDR) : 0)
+	
+	/*
+	 * First see if we want to change our options to the old
+	 * forms because we have received old forms from the peer.
+	 */
+	if (wo->neg_addr && !go->neg_addr && !go->old_addrs) {
+		/* use the old style of address negotiation */
+		go->neg_addr = 1;
+		go->old_addrs = 1;
+	}
+	if (wo->neg_vj && !go->neg_vj && !go->old_vj) {
+		/* try an older style of VJ negotiation */
+		if (cis_received[f->unit] == 0) {
+			/* keep trying the new style until we see some CI from the peer */
+			go->neg_vj = 1;
+		} else {
+			/* use the old style only if the peer did */
+			if (ho->neg_vj && ho->old_vj) {
+				go->neg_vj = 1;
+				go->old_vj = 1;
+				go->vj_protocol = ho->vj_protocol;
+			}
+		}
+	}
+	
+	return (LENCIADDR(go->neg_addr, go->old_addrs)
+			+ LENCIVJ(go->neg_vj, go->old_vj) +
+			LENCIDNS(go->req_dns1) +
+			LENCIDNS(go->req_dns2));
+}
+
+
+/*
+ * ipcp_addci - Add our desired CIs to a packet.
+ */
+static void ipcp_addci(fsm *f, u_char *ucp, int *lenp)
+{
+	ipcp_options *go = &ipcp_gotoptions[f->unit];
+	int len = *lenp;
+	
+#define ADDCIVJ(opt, neg, val, old, maxslotindex, cflag) \
+	if (neg) { \
+		int vjlen = old? CILEN_COMPRESS : CILEN_VJ; \
+		if (len >= vjlen) { \
+			PUTCHAR(opt, ucp); \
+			PUTCHAR(vjlen, ucp); \
+			PUTSHORT(val, ucp); \
+			if (!old) { \
+				PUTCHAR(maxslotindex, ucp); \
+				PUTCHAR(cflag, ucp); \
+			} \
+			len -= vjlen; \
+		} else \
+			neg = 0; \
+	}
+	
+#define ADDCIADDR(opt, neg, old, val1, val2) \
+	if (neg) { \
+		int addrlen = (old? CILEN_ADDRS: CILEN_ADDR); \
+		if (len >= addrlen) { \
+			u32_t l; \
+			PUTCHAR(opt, ucp); \
+			PUTCHAR(addrlen, ucp); \
+			l = ntohl(val1); \
+			PUTLONG(l, ucp); \
+			if (old) { \
+				l = ntohl(val2); \
+				PUTLONG(l, ucp); \
+			} \
+			len -= addrlen; \
+		} else \
+			neg = 0; \
+	}
+
+#define ADDCIDNS(opt, neg, addr) \
+	if (neg) { \
+		if (len >= CILEN_ADDR) { \
+			u32_t l; \
+			PUTCHAR(opt, ucp); \
+			PUTCHAR(CILEN_ADDR, ucp); \
+			l = ntohl(addr); \
+			PUTLONG(l, ucp); \
+			len -= CILEN_ADDR; \
+		} else \
+			neg = 0; \
+	}
+	
+	ADDCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), go->neg_addr,
+			  go->old_addrs, go->ouraddr, go->hisaddr);
+	
+	ADDCIVJ(CI_COMPRESSTYPE, go->neg_vj, go->vj_protocol, go->old_vj,
+			go->maxslotindex, go->cflag);
+	
+	ADDCIDNS(CI_MS_DNS1, go->req_dns1, go->dnsaddr[0]);
+
+	ADDCIDNS(CI_MS_DNS2, go->req_dns2, go->dnsaddr[1]);
+
+	*lenp -= len;
+}
+
+
+/*
+ * ipcp_ackci - Ack our CIs.
+ *
+ * Returns:
+ *	0 - Ack was bad.
+ *	1 - Ack was good.
+ */
+static int ipcp_ackci(fsm *f, u_char *p, int len)
+{
+	ipcp_options *go = &ipcp_gotoptions[f->unit];
+	u_short cilen, citype, cishort;
+	u32_t cilong;
+	u_char cimaxslotindex, cicflag;
+	
+	/*
+	 * CIs must be in exactly the same order that we sent...
+	 * Check packet length and CI length at each step.
+	 * If we find any deviations, then this packet is bad.
+	 */
+	
+#define ACKCIVJ(opt, neg, val, old, maxslotindex, cflag) \
+	if (neg) { \
+		int vjlen = old? CILEN_COMPRESS : CILEN_VJ; \
+		if ((len -= vjlen) < 0) \
+			goto bad; \
+		GETCHAR(citype, p); \
+		GETCHAR(cilen, p); \
+		if (cilen != vjlen || \
+				citype != opt)  \
+			goto bad; \
+		GETSHORT(cishort, p); \
+		if (cishort != val) \
+			goto bad; \
+		if (!old) { \
+			GETCHAR(cimaxslotindex, p); \
+			if (cimaxslotindex != maxslotindex) \
+				goto bad; \
+			GETCHAR(cicflag, p); \
+			if (cicflag != cflag) \
+				goto bad; \
+		} \
+	}
+	
+#define ACKCIADDR(opt, neg, old, val1, val2) \
+	if (neg) { \
+		int addrlen = (old? CILEN_ADDRS: CILEN_ADDR); \
+		u32_t l; \
+		if ((len -= addrlen) < 0) \
+			goto bad; \
+		GETCHAR(citype, p); \
+		GETCHAR(cilen, p); \
+		if (cilen != addrlen || \
+				citype != opt) \
+			goto bad; \
+		GETLONG(l, p); \
+		cilong = htonl(l); \
+		if (val1 != cilong) \
+			goto bad; \
+		if (old) { \
+			GETLONG(l, p); \
+			cilong = htonl(l); \
+			if (val2 != cilong) \
+				goto bad; \
+		} \
+	}
+
+#define ACKCIDNS(opt, neg, addr) \
+	if (neg) { \
+		u32_t l; \
+		if ((len -= CILEN_ADDR) < 0) \
+			goto bad; \
+		GETCHAR(citype, p); \
+		GETCHAR(cilen, p); \
+		if (cilen != CILEN_ADDR || \
+				citype != opt) \
+			goto bad; \
+		GETLONG(l, p); \
+		cilong = htonl(l); \
+		if (addr != cilong) \
+			goto bad; \
+	}
+	
+	ACKCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), go->neg_addr,
+			  go->old_addrs, go->ouraddr, go->hisaddr);
+	
+	ACKCIVJ(CI_COMPRESSTYPE, go->neg_vj, go->vj_protocol, go->old_vj,
+			go->maxslotindex, go->cflag);
+	
+	ACKCIDNS(CI_MS_DNS1, go->req_dns1, go->dnsaddr[0]);
+
+	ACKCIDNS(CI_MS_DNS2, go->req_dns2, go->dnsaddr[1]);
+
+	/*
+	 * If there are any remaining CIs, then this packet is bad.
+	 */
+	if (len != 0)
+		goto bad;
+	return (1);
+	
+bad:
+	IPCPDEBUG((LOG_INFO, "ipcp_ackci: received bad Ack!\n"));
+	return (0);
+}
+
+/*
+ * ipcp_nakci - Peer has sent a NAK for some of our CIs.
+ * This should not modify any state if the Nak is bad
+ * or if IPCP is in the OPENED state.
+ *
+ * Returns:
+ *	0 - Nak was bad.
+ *	1 - Nak was good.
+ */
+static int ipcp_nakci(fsm *f, u_char *p, int len)
+{
+	ipcp_options *go = &ipcp_gotoptions[f->unit];
+	u_char cimaxslotindex, cicflag;
+	u_char citype, cilen, *next;
+	u_short cishort;
+	u32_t ciaddr1, ciaddr2, l, cidnsaddr;
+	ipcp_options no;		/* options we've seen Naks for */
+	ipcp_options try;		/* options to request next time */
+	
+	BZERO(&no, sizeof(no));
+	try = *go;
+	
+	/*
+	 * Any Nak'd CIs must be in exactly the same order that we sent.
+	 * Check packet length and CI length at each step.
+	 * If we find any deviations, then this packet is bad.
+	 */
+#define NAKCIADDR(opt, neg, old, code) \
+	if (go->neg && \
+			len >= (cilen = (old? CILEN_ADDRS: CILEN_ADDR)) && \
+			p[1] == cilen && \
+			p[0] == opt) { \
+		len -= cilen; \
+		INCPTR(2, p); \
+		GETLONG(l, p); \
+		ciaddr1 = htonl(l); \
+		if (old) { \
+			GETLONG(l, p); \
+			ciaddr2 = htonl(l); \
+			no.old_addrs = 1; \
+		} else \
+			ciaddr2 = 0; \
+		no.neg = 1; \
+		code \
+	}
+	
+#define NAKCIVJ(opt, neg, code) \
+	if (go->neg && \
+			((cilen = p[1]) == CILEN_COMPRESS || cilen == CILEN_VJ) && \
+			len >= cilen && \
+			p[0] == opt) { \
+		len -= cilen; \
+		INCPTR(2, p); \
+		GETSHORT(cishort, p); \
+		no.neg = 1; \
+		code \
+	}
+	
+#define NAKCIDNS(opt, neg, code) \
+	if (go->neg && \
+			((cilen = p[1]) == CILEN_ADDR) && \
+			len >= cilen && \
+			p[0] == opt) { \
+		len -= cilen; \
+		INCPTR(2, p); \
+		GETLONG(l, p); \
+		cidnsaddr = htonl(l); \
+		no.neg = 1; \
+		code \
+	}
+	
+	/*
+	 * Accept the peer's idea of {our,his} address, if different
+	 * from our idea, only if the accept_{local,remote} flag is set.
+	 */
+	NAKCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), neg_addr, go->old_addrs,
+	  if (go->accept_local && ciaddr1) { /* Do we know our address? */
+		  try.ouraddr = ciaddr1;
+		  IPCPDEBUG((LOG_INFO, "local IP address %s\n",
+			     inet_ntoa(ciaddr1)));
+	  }
+	  if (go->accept_remote && ciaddr2) { /* Does he know his? */
+		  try.hisaddr = ciaddr2;
+		  IPCPDEBUG((LOG_INFO, "remote IP address %s\n",
+			     inet_ntoa(ciaddr2)));
+	  }
+	);
+	
+	/*
+	 * Accept the peer's value of maxslotindex provided that it
+	 * is less than what we asked for.  Turn off slot-ID compression
+	 * if the peer wants.  Send old-style compress-type option if
+	 * the peer wants.
+	 */
+	NAKCIVJ(CI_COMPRESSTYPE, neg_vj,
+		if (cilen == CILEN_VJ) {
+			GETCHAR(cimaxslotindex, p);
+			GETCHAR(cicflag, p);
+			if (cishort == IPCP_VJ_COMP) {
+				try.old_vj = 0;
+				if (cimaxslotindex < go->maxslotindex)
+					try.maxslotindex = cimaxslotindex;
+				if (!cicflag)
+					try.cflag = 0;
+			} else {
+				try.neg_vj = 0;
+			}
+		} else {
+			if (cishort == IPCP_VJ_COMP || cishort == IPCP_VJ_COMP_OLD) {
+				try.old_vj = 1;
+				try.vj_protocol = cishort;
+			} else {
+				try.neg_vj = 0;
+			}
+		}
+	);
+	
+	NAKCIDNS(CI_MS_DNS1, req_dns1,
+			try.dnsaddr[0] = cidnsaddr;
+		  	IPCPDEBUG((LOG_INFO, "primary DNS address %s\n", inet_ntoa(cidnsaddr)));
+			);
+
+	NAKCIDNS(CI_MS_DNS2, req_dns2,
+			try.dnsaddr[1] = cidnsaddr;
+		  	IPCPDEBUG((LOG_INFO, "secondary DNS address %s\n", inet_ntoa(cidnsaddr)));
+			);
+
+	/*
+	* There may be remaining CIs, if the peer is requesting negotiation
+	* on an option that we didn't include in our request packet.
+	* If they want to negotiate about IP addresses, we comply.
+	* If they want us to ask for compression, we refuse.
+	*/
+	while (len > CILEN_VOID) {
+		GETCHAR(citype, p);
+		GETCHAR(cilen, p);
+		if( (len -= cilen) < 0 )
+			goto bad;
+		next = p + cilen - 2;
+		
+		switch (citype) {
+		case CI_COMPRESSTYPE:
+			if (go->neg_vj || no.neg_vj ||
+					(cilen != CILEN_VJ && cilen != CILEN_COMPRESS))
+				goto bad;
+			no.neg_vj = 1;
+			break;
+		case CI_ADDRS:
+			if ((go->neg_addr && go->old_addrs) || no.old_addrs
+					|| cilen != CILEN_ADDRS)
+				goto bad;
+			try.neg_addr = 1;
+			try.old_addrs = 1;
+			GETLONG(l, p);
+			ciaddr1 = htonl(l);
+			if (ciaddr1 && go->accept_local)
+				try.ouraddr = ciaddr1;
+			GETLONG(l, p);
+			ciaddr2 = htonl(l);
+			if (ciaddr2 && go->accept_remote)
+				try.hisaddr = ciaddr2;
+			no.old_addrs = 1;
+			break;
+		case CI_ADDR:
+			if (go->neg_addr || no.neg_addr || cilen != CILEN_ADDR)
+				goto bad;
+			try.old_addrs = 0;
+			GETLONG(l, p);
+			ciaddr1 = htonl(l);
+			if (ciaddr1 && go->accept_local)
+				try.ouraddr = ciaddr1;
+			if (try.ouraddr != 0)
+				try.neg_addr = 1;
+			no.neg_addr = 1;
+			break;
+		}
+		p = next;
+	}
+	
+	/* If there is still anything left, this packet is bad. */
+	if (len != 0)
+		goto bad;
+	
+	/*
+	 * OK, the Nak is good.  Now we can update state.
+	 */
+	if (f->state != OPENED)
+		*go = try;
+	
+	return 1;
+	
+bad:
+	IPCPDEBUG((LOG_INFO, "ipcp_nakci: received bad Nak!\n"));
+	return 0;
+}
+
+
+/*
+ * ipcp_rejci - Reject some of our CIs.
+ */
+static int ipcp_rejci(fsm *f, u_char *p, int len)
+{
+	ipcp_options *go = &ipcp_gotoptions[f->unit];
+	u_char cimaxslotindex, ciflag, cilen;
+	u_short cishort;
+	u32_t cilong;
+	ipcp_options try;		/* options to request next time */
+	
+	try = *go;
+	/*
+	 * Any Rejected CIs must be in exactly the same order that we sent.
+	 * Check packet length and CI length at each step.
+	 * If we find any deviations, then this packet is bad.
+	 */
+#define REJCIADDR(opt, neg, old, val1, val2) \
+	if (go->neg && \
+			len >= (cilen = old? CILEN_ADDRS: CILEN_ADDR) && \
+			p[1] == cilen && \
+			p[0] == opt) { \
+		u32_t l; \
+		len -= cilen; \
+		INCPTR(2, p); \
+		GETLONG(l, p); \
+		cilong = htonl(l); \
+		/* Check rejected value. */ \
+		if (cilong != val1) \
+			goto bad; \
+		if (old) { \
+			GETLONG(l, p); \
+			cilong = htonl(l); \
+			/* Check rejected value. */ \
+			if (cilong != val2) \
+				goto bad; \
+		} \
+		try.neg = 0; \
+	}
+	
+#define REJCIVJ(opt, neg, val, old, maxslot, cflag) \
+	if (go->neg && \
+			p[1] == (old? CILEN_COMPRESS : CILEN_VJ) && \
+			len >= p[1] && \
+			p[0] == opt) { \
+		len -= p[1]; \
+		INCPTR(2, p); \
+		GETSHORT(cishort, p); \
+		/* Check rejected value. */  \
+		if (cishort != val) \
+			goto bad; \
+		if (!old) { \
+			GETCHAR(cimaxslotindex, p); \
+			if (cimaxslotindex != maxslot) \
+				goto bad; \
+			GETCHAR(ciflag, p); \
+			if (ciflag != cflag) \
+				goto bad; \
+		} \
+		try.neg = 0; \
+	}
+	
+#define REJCIDNS(opt, neg, dnsaddr) \
+	if (go->neg && \
+			((cilen = p[1]) == CILEN_ADDR) && \
+			len >= cilen && \
+			p[0] == opt) { \
+		u32_t l; \
+		len -= cilen; \
+		INCPTR(2, p); \
+		GETLONG(l, p); \
+		cilong = htonl(l); \
+		/* Check rejected value. */ \
+		if (cilong != dnsaddr) \
+			goto bad; \
+		try.neg = 0; \
+	}
+
+	REJCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), neg_addr,
+			  go->old_addrs, go->ouraddr, go->hisaddr);
+	
+	REJCIVJ(CI_COMPRESSTYPE, neg_vj, go->vj_protocol, go->old_vj,
+			go->maxslotindex, go->cflag);
+	
+	REJCIDNS(CI_MS_DNS1, req_dns1, go->dnsaddr[0]);
+
+	REJCIDNS(CI_MS_DNS2, req_dns2, go->dnsaddr[1]);
+
+	/*
+	 * If there are any remaining CIs, then this packet is bad.
+	 */
+	if (len != 0)
+		goto bad;
+	/*
+	 * Now we can update state.
+	 */
+	if (f->state != OPENED)
+		*go = try;
+	return 1;
+	
+bad:
+	IPCPDEBUG((LOG_INFO, "ipcp_rejci: received bad Reject!\n"));
+	return 0;
+}
+
+
+/*
+ * ipcp_reqci - Check the peer's requested CIs and send appropriate response.
+ *
+ * Returns: CONFACK, CONFNAK or CONFREJ and input packet modified
+ * appropriately.  If reject_if_disagree is non-zero, doesn't return
+ * CONFNAK; returns CONFREJ if it can't return CONFACK.
+ */
+static int ipcp_reqci(
+	fsm *f,
+	u_char *inp,		/* Requested CIs */
+	int *len,			/* Length of requested CIs */
+	int reject_if_disagree
+)
+{
+	ipcp_options *wo = &ipcp_wantoptions[f->unit];
+	ipcp_options *ho = &ipcp_hisoptions[f->unit];
+	ipcp_options *ao = &ipcp_allowoptions[f->unit];
+#ifdef OLD_CI_ADDRS
+	ipcp_options *go = &ipcp_gotoptions[f->unit];
+#endif
+	u_char *cip, *next;				/* Pointer to current and next CIs */
+	u_short cilen, citype;			/* Parsed len, type */
+	u_short cishort;				/* Parsed short value */
+	u32_t tl, ciaddr1;			/* Parsed address values */
+#ifdef OLD_CI_ADDRS
+	u32_t ciaddr2;				/* Parsed address values */
+#endif
+	int rc = CONFACK;				/* Final packet return code */
+	int orc;						/* Individual option return code */
+	u_char *p;						/* Pointer to next char to parse */
+	u_char *ucp = inp;				/* Pointer to current output char */
+	int l = *len;					/* Length left */
+	u_char maxslotindex, cflag;
+	int d;
+	
+	cis_received[f->unit] = 1;
+	
+	/*
+	 * Reset all his options.
+	 */
+	BZERO(ho, sizeof(*ho));
+	
+	/*
+	 * Process all his options.
+	 */
+	next = inp;
+	while (l) {
+		orc = CONFACK;				/* Assume success */
+		cip = p = next;				/* Remember begining of CI */
+		if (l < 2 ||				/* Not enough data for CI header or */
+				p[1] < 2 ||			/*  CI length too small or */
+				p[1] > l) {			/*  CI length too big? */
+			IPCPDEBUG((LOG_INFO, "ipcp_reqci: bad CI length!\n"));
+			orc = CONFREJ;			/* Reject bad CI */
+			cilen = l;				/* Reject till end of packet */
+			l = 0;					/* Don't loop again */
+			goto endswitch;
+		}
+		GETCHAR(citype, p);			/* Parse CI type */
+		GETCHAR(cilen, p);			/* Parse CI length */
+		l -= cilen;					/* Adjust remaining length */
+		next += cilen;				/* Step to next CI */
+
+		switch (citype) {			/* Check CI type */
+#ifdef OLD_CI_ADDRS /* Need to save space... */
+		case CI_ADDRS:
+			IPCPDEBUG((LOG_INFO, "ipcp_reqci: received ADDRS\n"));
+			if (!ao->neg_addr ||
+					cilen != CILEN_ADDRS) {	/* Check CI length */
+				orc = CONFREJ;		/* Reject CI */
+				break;
+			}
+			
+			/*
+			 * If he has no address, or if we both have his address but
+			 * disagree about it, then NAK it with our idea.
+			 * In particular, if we don't know his address, but he does,
+			 * then accept it.
+			 */
+			GETLONG(tl, p);		/* Parse source address (his) */
+			ciaddr1 = htonl(tl);
+			IPCPDEBUG((LOG_INFO, "his addr %s\n", inet_ntoa(ciaddr1)));
+			if (ciaddr1 != wo->hisaddr
+					&& (ciaddr1 == 0 || !wo->accept_remote)) {
+				orc = CONFNAK;
+				if (!reject_if_disagree) {
+					DECPTR(sizeof(u32_t), p);
+					tl = ntohl(wo->hisaddr);
+					PUTLONG(tl, p);
+				}
+			} else if (ciaddr1 == 0 && wo->hisaddr == 0) {
+				/*
+				 * If neither we nor he knows his address, reject the option.
+				 */
+				orc = CONFREJ;
+				wo->req_addr = 0;	/* don't NAK with 0.0.0.0 later */
+				break;
+			}
+			
+			/*
+			 * If he doesn't know our address, or if we both have our address
+			 * but disagree about it, then NAK it with our idea.
+			 */
+			GETLONG(tl, p);		/* Parse desination address (ours) */
+			ciaddr2 = htonl(tl);
+			IPCPDEBUG((LOG_INFO, "our addr %s\n", inet_ntoa(ciaddr2)));
+			if (ciaddr2 != wo->ouraddr) {
+				if (ciaddr2 == 0 || !wo->accept_local) {
+					orc = CONFNAK;
+					if (!reject_if_disagree) {
+						DECPTR(sizeof(u32_t), p);
+						tl = ntohl(wo->ouraddr);
+						PUTLONG(tl, p);
+					}
+				} else {
+					go->ouraddr = ciaddr2;	/* accept peer's idea */
+				}
+			}
+			
+			ho->neg_addr = 1;
+			ho->old_addrs = 1;
+			ho->hisaddr = ciaddr1;
+			ho->ouraddr = ciaddr2;
+			break;
+#endif
+		
+		case CI_ADDR:
+			if (!ao->neg_addr) {
+				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Reject ADDR not allowed\n"));
+				orc = CONFREJ;				/* Reject CI */
+				break;
+			} else if (cilen != CILEN_ADDR) {	/* Check CI length */
+				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Reject ADDR bad len\n"));
+				orc = CONFREJ;				/* Reject CI */
+				break;
+			}
+			
+			/*
+			 * If he has no address, or if we both have his address but
+			 * disagree about it, then NAK it with our idea.
+			 * In particular, if we don't know his address, but he does,
+			 * then accept it.
+			 */
+			GETLONG(tl, p);	/* Parse source address (his) */
+			ciaddr1 = htonl(tl);
+			if (ciaddr1 != wo->hisaddr
+					&& (ciaddr1 == 0 || !wo->accept_remote)) {
+				orc = CONFNAK;
+				if (!reject_if_disagree) {
+					DECPTR(sizeof(u32_t), p);
+					tl = ntohl(wo->hisaddr);
+					PUTLONG(tl, p);
+				}
+				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Nak ADDR %s\n", inet_ntoa(ciaddr1)));
+			} else if (ciaddr1 == 0 && wo->hisaddr == 0) {
+				/*
+				 * Don't ACK an address of 0.0.0.0 - reject it instead.
+				 */
+				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Reject ADDR %s\n", inet_ntoa(ciaddr1)));
+				orc = CONFREJ;
+				wo->req_addr = 0;	/* don't NAK with 0.0.0.0 later */
+				break;
+			}
+			
+			ho->neg_addr = 1;
+			ho->hisaddr = ciaddr1;
+			IPCPDEBUG((LOG_INFO, "ipcp_reqci: ADDR %s\n", inet_ntoa(ciaddr1)));
+			break;
+		
+		case CI_MS_DNS1:
+		case CI_MS_DNS2:
+			/* Microsoft primary or secondary DNS request */
+			d = citype == CI_MS_DNS2;
+			
+			/* If we do not have a DNS address then we cannot send it */
+			if (ao->dnsaddr[d] == 0 ||
+					cilen != CILEN_ADDR) {	/* Check CI length */
+				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting DNS%d Request\n", d+1));
+				orc = CONFREJ;				/* Reject CI */
+				break;
+			}
+			GETLONG(tl, p);
+			if (htonl(tl) != ao->dnsaddr[d]) {
+				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Naking DNS%d Request %d\n",
+							d+1, inet_ntoa(tl)));
+				DECPTR(sizeof(u32_t), p);
+				tl = ntohl(ao->dnsaddr[d]);
+				PUTLONG(tl, p);
+				orc = CONFNAK;
+			}
+			IPCPDEBUG((LOG_INFO, "ipcp_reqci: received DNS%d Request\n", d+1));
+			break;
+		
+		case CI_MS_WINS1:
+		case CI_MS_WINS2:
+			/* Microsoft primary or secondary WINS request */
+			d = citype == CI_MS_WINS2;
+			IPCPDEBUG((LOG_INFO, "ipcp_reqci: received WINS%d Request\n", d+1));
+			
+			/* If we do not have a DNS address then we cannot send it */
+			if (ao->winsaddr[d] == 0 ||
+				cilen != CILEN_ADDR) {	/* Check CI length */
+				orc = CONFREJ;			/* Reject CI */
+				break;
+			}
+			GETLONG(tl, p);
+			if (htonl(tl) != ao->winsaddr[d]) {
+				DECPTR(sizeof(u32_t), p);
+				tl = ntohl(ao->winsaddr[d]);
+				PUTLONG(tl, p);
+				orc = CONFNAK;
+			}
+			break;
+		
+		case CI_COMPRESSTYPE:
+			if (!ao->neg_vj) {
+				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting COMPRESSTYPE not allowed\n"));
+				orc = CONFREJ;
+				break;
+			} else if (cilen != CILEN_VJ && cilen != CILEN_COMPRESS) {
+				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting COMPRESSTYPE len=%d\n", cilen));
+				orc = CONFREJ;
+				break;
+			}
+			GETSHORT(cishort, p);
+			
+			if (!(cishort == IPCP_VJ_COMP ||
+					(cishort == IPCP_VJ_COMP_OLD && cilen == CILEN_COMPRESS))) {
+				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting COMPRESSTYPE %d\n", cishort));
+				orc = CONFREJ;
+				break;
+			}
+			
+			ho->neg_vj = 1;
+			ho->vj_protocol = cishort;
+			if (cilen == CILEN_VJ) {
+				GETCHAR(maxslotindex, p);
+				if (maxslotindex > ao->maxslotindex) { 
+					IPCPDEBUG((LOG_INFO, "ipcp_reqci: Naking VJ max slot %d\n", maxslotindex));
+					orc = CONFNAK;
+					if (!reject_if_disagree){
+						DECPTR(1, p);
+						PUTCHAR(ao->maxslotindex, p);
+					}
+				}
+				GETCHAR(cflag, p);
+				if (cflag && !ao->cflag) {
+					IPCPDEBUG((LOG_INFO, "ipcp_reqci: Naking VJ cflag %d\n", cflag));
+					orc = CONFNAK;
+					if (!reject_if_disagree){
+						DECPTR(1, p);
+						PUTCHAR(wo->cflag, p);
+					}
+				}
+				ho->maxslotindex = maxslotindex;
+				ho->cflag = cflag;
+			} else {
+				ho->old_vj = 1;
+				ho->maxslotindex = MAX_SLOTS - 1;
+				ho->cflag = 1;
+			}
+			IPCPDEBUG((LOG_INFO, 
+						"ipcp_reqci: received COMPRESSTYPE p=%d old=%d maxslot=%d cflag=%d\n",
+						ho->vj_protocol, ho->old_vj, ho->maxslotindex, ho->cflag));
+			break;
+			
+		default:
+			IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting unknown CI type %d\n", citype));
+			orc = CONFREJ;
+			break;
+		}
+		
+endswitch:
+		if (orc == CONFACK &&		/* Good CI */
+				rc != CONFACK)		/*  but prior CI wasnt? */
+			continue;				/* Don't send this one */
+		
+		if (orc == CONFNAK) {		/* Nak this CI? */
+			if (reject_if_disagree) {	/* Getting fed up with sending NAKs? */
+				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting too many naks\n"));
+				orc = CONFREJ;		/* Get tough if so */
+			} else {
+				if (rc == CONFREJ)	/* Rejecting prior CI? */
+					continue;		/* Don't send this one */
+				if (rc == CONFACK) {	/* Ack'd all prior CIs? */
+					rc = CONFNAK;	/* Not anymore... */
+					ucp = inp;		/* Backup */
+				}
+			}
+		}
+		
+		if (orc == CONFREJ &&		/* Reject this CI */
+				rc != CONFREJ) {	/*  but no prior ones? */
+			rc = CONFREJ;
+			ucp = inp;				/* Backup */
+		}
+		
+		/* Need to move CI? */
+		if (ucp != cip)
+			BCOPY(cip, ucp, cilen);	/* Move it */
+		
+		/* Update output pointer */
+		INCPTR(cilen, ucp);
+	}
+	
+	/*
+	 * If we aren't rejecting this packet, and we want to negotiate
+	 * their address, and they didn't send their address, then we
+	 * send a NAK with a CI_ADDR option appended.  We assume the
+	 * input buffer is long enough that we can append the extra
+	 * option safely.
+	 */
+	if (rc != CONFREJ && !ho->neg_addr &&
+			wo->req_addr && !reject_if_disagree) {
+		IPCPDEBUG((LOG_INFO, "ipcp_reqci: Requesting peer address\n"));
+		if (rc == CONFACK) {
+			rc = CONFNAK;
+			ucp = inp;				/* reset pointer */
+			wo->req_addr = 0;		/* don't ask again */
+		}
+		PUTCHAR(CI_ADDR, ucp);
+		PUTCHAR(CILEN_ADDR, ucp);
+		tl = ntohl(wo->hisaddr);
+		PUTLONG(tl, ucp);
+	}
+	
+	*len = (int)(ucp - inp);		/* Compute output length */
+	IPCPDEBUG((LOG_INFO, "ipcp_reqci: returning Configure-%s\n", CODENAME(rc)));
+	return (rc);			/* Return final code */
+}
+
+
+#if 0
+/*
+ * ip_check_options - check that any IP-related options are OK,
+ * and assign appropriate defaults.
+ */
+static void ip_check_options(u_long localAddr)
+{
+	ipcp_options *wo = &ipcp_wantoptions[0];
+
+	/*
+	 * Load our default IP address but allow the remote host to give us
+	 * a new address.
+	 */
+	if (wo->ouraddr == 0 && !ppp_settings.disable_defaultip) {
+		wo->accept_local = 1;	/* don't insist on this default value */
+		wo->ouraddr = htonl(localAddr);
+	}
+}
+#endif
+
+
+/*
+ * ipcp_up - IPCP has come UP.
+ *
+ * Configure the IP network interface appropriately and bring it up.
+ */
+static void ipcp_up(fsm *f)
+{
+	u32_t mask;
+	ipcp_options *ho = &ipcp_hisoptions[f->unit];
+	ipcp_options *go = &ipcp_gotoptions[f->unit];
+	ipcp_options *wo = &ipcp_wantoptions[f->unit];
+	
+	np_up(f->unit, PPP_IP);
+	IPCPDEBUG((LOG_INFO, "ipcp: up\n"));
+	
+	/*
+	 * We must have a non-zero IP address for both ends of the link.
+	 */
+	if (!ho->neg_addr)
+		ho->hisaddr = wo->hisaddr;
+	
+	if (ho->hisaddr == 0) {
+		IPCPDEBUG((LOG_ERR, "Could not determine remote IP address\n"));
+		ipcp_close(f->unit, "Could not determine remote IP address");
+		return;
+	}
+	if (go->ouraddr == 0) {
+		IPCPDEBUG((LOG_ERR, "Could not determine local IP address\n"));
+		ipcp_close(f->unit, "Could not determine local IP address");
+		return;
+	}
+	
+	if (ppp_settings.usepeerdns && (go->dnsaddr[0] || go->dnsaddr[1])) {
+		/*pppGotDNSAddrs(go->dnsaddr[0], go->dnsaddr[1]);*/
+	}
+
+	/*
+	 * Check that the peer is allowed to use the IP address it wants.
+	 */
+	if (!auth_ip_addr(f->unit, ho->hisaddr)) {
+		IPCPDEBUG((LOG_ERR, "Peer is not authorized to use remote address %s\n",
+				inet_ntoa(ho->hisaddr)));
+		ipcp_close(f->unit, "Unauthorized remote IP address");
+		return;
+	}
+	
+	/* set tcp compression */
+	sifvjcomp(f->unit, ho->neg_vj, ho->cflag, ho->maxslotindex);
+	
+	/*
+	 * Set IP addresses and (if specified) netmask.
+	 */
+	mask = GetMask(go->ouraddr);
+	
+	if (!sifaddr(f->unit, go->ouraddr, ho->hisaddr, mask, go->dnsaddr[0], go->dnsaddr[1])) {
+		IPCPDEBUG((LOG_WARNING, "sifaddr failed\n"));
+		ipcp_close(f->unit, "Interface configuration failed");
+		return;
+	}
+	
+	/* bring the interface up for IP */
+	if (!sifup(f->unit)) {
+		IPCPDEBUG((LOG_WARNING, "sifup failed\n"));
+		ipcp_close(f->unit, "Interface configuration failed");
+		return;
+	}
+	
+	sifnpmode(f->unit, PPP_IP, NPMODE_PASS);
+	
+	/* assign a default route through the interface if required */
+	if (ipcp_wantoptions[f->unit].default_route) 
+		if (sifdefaultroute(f->unit, go->ouraddr, ho->hisaddr))
+			default_route_set[f->unit] = 1;
+	
+	IPCPDEBUG((LOG_NOTICE, "local  IP address %s\n", inet_ntoa(go->ouraddr)));
+	IPCPDEBUG((LOG_NOTICE, "remote IP address %s\n", inet_ntoa(ho->hisaddr)));
+	if (go->dnsaddr[0]) {
+		IPCPDEBUG((LOG_NOTICE, "primary   DNS address %s\n", inet_ntoa(go->dnsaddr[0])));
+	}
+	if (go->dnsaddr[1]) {
+		IPCPDEBUG((LOG_NOTICE, "secondary DNS address %s\n", inet_ntoa(go->dnsaddr[1])));
+	}
+}
+
+
+/*
+ * ipcp_down - IPCP has gone DOWN.
+ *
+ * Take the IP network interface down, clear its addresses
+ * and delete routes through it.
+ */
+static void ipcp_down(fsm *f)
+{
+	IPCPDEBUG((LOG_INFO, "ipcp: down\n"));
+	np_down(f->unit, PPP_IP);
+	sifvjcomp(f->unit, 0, 0, 0);
+	
+	sifdown(f->unit);
+	ipcp_clear_addrs(f->unit);
+}
+
+
+/*
+ * ipcp_clear_addrs() - clear the interface addresses, routes, etc.
+ */
+static void ipcp_clear_addrs(int unit)
+{
+	u32_t ouraddr, hisaddr;
+	
+	ouraddr = ipcp_gotoptions[unit].ouraddr;
+	hisaddr = ipcp_hisoptions[unit].hisaddr;
+	if (default_route_set[unit]) {
+		cifdefaultroute(unit, ouraddr, hisaddr);
+		default_route_set[unit] = 0;
+	}
+	cifaddr(unit, ouraddr, hisaddr);
+}
+
+
+/*
+ * ipcp_finished - possibly shut down the lower layers.
+ */
+static void ipcp_finished(fsm *f)
+{
+	np_finished(f->unit, PPP_IP);
+}
+
+#if 0
+static int ipcp_printpkt(
+	u_char *p,
+	int plen,
+	void (*printer) (void *, char *, ...),
+	void *arg
+)
+{
+	(void)p;
+	(void)plen;
+	(void)printer;
+	(void)arg;
+	return 0;
+}
+
+/*
+ * ip_active_pkt - see if this IP packet is worth bringing the link up for.
+ * We don't bring the link up for IP fragments or for TCP FIN packets
+ * with no data.
+ */
+#define IP_HDRLEN	20	/* bytes */
+#define IP_OFFMASK	0x1fff
+#define IPPROTO_TCP	6
+#define TCP_HDRLEN	20
+#define TH_FIN		0x01
+
+/*
+ * We use these macros because the IP header may be at an odd address,
+ * and some compilers might use word loads to get th_off or ip_hl.
+ */
+
+#define net_short(x)	(((x)[0] << 8) + (x)[1])
+#define get_iphl(x)	(((unsigned char *)(x))[0] & 0xF)
+#define get_ipoff(x)	net_short((unsigned char *)(x) + 6)
+#define get_ipproto(x)	(((unsigned char *)(x))[9])
+#define get_tcpoff(x)	(((unsigned char *)(x))[12] >> 4)
+#define get_tcpflags(x)	(((unsigned char *)(x))[13])
+
+static int ip_active_pkt(u_char *pkt, int len)
+{
+	u_char *tcp;
+	int hlen;
+	
+	len -= PPP_HDRLEN;
+	pkt += PPP_HDRLEN;
+	if (len < IP_HDRLEN)
+		return 0;
+	if ((get_ipoff(pkt) & IP_OFFMASK) != 0)
+		return 0;
+	if (get_ipproto(pkt) != IPPROTO_TCP)
+		return 1;
+	hlen = get_iphl(pkt) * 4;
+	if (len < hlen + TCP_HDRLEN)
+		return 0;
+	tcp = pkt + hlen;
+	if ((get_tcpflags(tcp) & TH_FIN) != 0 && len == hlen + get_tcpoff(tcp) * 4)
+		return 0;
+	return 1;
+}
+#endif
+
+#endif /* PPP_SUPPORT */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/ipcp.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/ipcp.h
new file mode 100644
index 000000000..0ee2edbbd
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/ipcp.h
@@ -0,0 +1,126 @@
+/*****************************************************************************
+* ipcp.h -  PPP IP NCP: Internet Protocol Network Control Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-04 Guy Lancaster , Global Election Systems Inc.
+*	Original derived from BSD codes.
+*****************************************************************************/
+/*
+ * ipcp.h - IP Control Protocol definitions.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * $Id: ipcp.h,v 1.2 2006/08/29 18:53:47 wolti Exp $
+ */
+
+#ifndef IPCP_H
+#define IPCP_H
+
+/*************************
+*** PUBLIC DEFINITIONS ***
+*************************/
+/*
+ * Options.
+ */
+#define CI_ADDRS	1			/* IP Addresses */
+#define CI_COMPRESSTYPE	2		/* Compression Type */
+#define	CI_ADDR		3
+
+#define CI_MS_WINS1	128			/* Primary WINS value */
+#define CI_MS_DNS1	129			/* Primary DNS value */
+#define CI_MS_WINS2	130			/* Secondary WINS value */
+#define CI_MS_DNS2	131			/* Secondary DNS value */
+
+#define IPCP_VJMODE_OLD 1		/* "old" mode (option # = 0x0037) */
+#define IPCP_VJMODE_RFC1172 2	/* "old-rfc"mode (option # = 0x002d) */
+#define IPCP_VJMODE_RFC1332 3	/* "new-rfc"mode (option # = 0x002d, */
+                                /*  maxslot and slot number compression) */
+
+#define IPCP_VJ_COMP 0x002d		/* current value for VJ compression option*/
+#define IPCP_VJ_COMP_OLD 0x0037	/* "old" (i.e, broken) value for VJ */
+								/* compression option*/ 
+
+
+/************************
+*** PUBLIC DATA TYPES ***
+************************/
+
+typedef struct ipcp_options {
+    u_int neg_addr : 1;			/* Negotiate IP Address? */
+    u_int old_addrs : 1;			/* Use old (IP-Addresses) option? */
+    u_int req_addr : 1;			/* Ask peer to send IP address? */
+    u_int default_route : 1;		/* Assign default route through interface? */
+    u_int proxy_arp : 1;			/* Make proxy ARP entry for peer? */
+    u_int neg_vj : 1;				/* Van Jacobson Compression? */
+    u_int old_vj : 1;				/* use old (short) form of VJ option? */
+    u_int accept_local : 1;		/* accept peer's value for ouraddr */
+    u_int accept_remote : 1;		/* accept peer's value for hisaddr */
+    u_int req_dns1 : 1;			/* Ask peer to send primary DNS address? */
+    u_int req_dns2 : 1;			/* Ask peer to send secondary DNS address? */
+    u_short vj_protocol;		/* protocol value to use in VJ option */
+    u_char maxslotindex;		/* VJ slots - 1. */
+    u_char cflag;				/* VJ slot compression flag. */
+    u32_t ouraddr, hisaddr;	/* Addresses in NETWORK BYTE ORDER */
+    u32_t dnsaddr[2];		/* Primary and secondary MS DNS entries */
+    u32_t winsaddr[2];		/* Primary and secondary MS WINS entries */
+} ipcp_options;
+
+
+/*****************************
+*** PUBLIC DATA STRUCTURES ***
+*****************************/
+
+extern fsm ipcp_fsm[];
+extern ipcp_options ipcp_wantoptions[];
+extern ipcp_options ipcp_gotoptions[];
+extern ipcp_options ipcp_allowoptions[];
+extern ipcp_options ipcp_hisoptions[];
+
+extern struct protent ipcp_protent;
+
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+
+
+#endif /* IPCP_H */
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/lcp.c b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/lcp.c
new file mode 100644
index 000000000..41dbc5dd2
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/lcp.c
@@ -0,0 +1,1991 @@
+/*****************************************************************************
+* lcp.c - Network Link Control Protocol program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-01 Guy Lancaster , Global Election Systems Inc.
+*	Original.
+*****************************************************************************/
+
+/*
+ * lcp.c - PPP Link Control Protocol.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+ 
+#include 
+ 
+#include "ppp.h"
+#if PPP_SUPPORT > 0
+#include "fsm.h"
+#include "chap.h"
+#include "magic.h"
+#include "auth.h"
+#include "lcp.h"
+#include "pppdebug.h"
+
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+/*
+ * Length of each type of configuration option (in octets)
+ */
+#define CILEN_VOID	2
+#define CILEN_CHAR	3
+#define CILEN_SHORT	4	/* CILEN_VOID + sizeof(short) */
+#define CILEN_CHAP	5	/* CILEN_VOID + sizeof(short) + 1 */
+#define CILEN_LONG	6	/* CILEN_VOID + sizeof(long) */
+#define CILEN_LQR	8	/* CILEN_VOID + sizeof(short) + sizeof(long) */
+#define CILEN_CBCP	3
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+/*
+ * Callbacks for fsm code.  (CI = Configuration Information)
+ */
+static void lcp_resetci (fsm*);	        /* Reset our CI */
+static int  lcp_cilen (fsm*);		        /* Return length of our CI */
+static void lcp_addci (fsm*, u_char*, int*);       /* Add our CI to pkt */
+static int  lcp_ackci (fsm*, u_char*, int);/* Peer ack'd our CI */
+static int  lcp_nakci (fsm*, u_char*, int);/* Peer nak'd our CI */
+static int  lcp_rejci (fsm*, u_char*, int);/* Peer rej'd our CI */
+static int  lcp_reqci (fsm*, u_char*, int*, int);  /* Rcv peer CI */
+static void lcp_up (fsm*);		            /* We're UP */
+static void lcp_down (fsm*);	    	    /* We're DOWN */
+static void lcp_starting (fsm*);   	    /* We need lower layer up */
+static void lcp_finished (fsm*);	        /* We need lower layer down */
+static int  lcp_extcode (fsm*, int, u_char, u_char*, int);
+
+static void lcp_rprotrej (fsm*, u_char*, int);
+
+/*
+ * routines to send LCP echos to peer
+ */
+static void lcp_echo_lowerup (int);
+static void lcp_echo_lowerdown (int);
+static void LcpEchoTimeout (void*);
+static void lcp_received_echo_reply (fsm*, int, u_char*, int);
+static void LcpSendEchoRequest (fsm*);
+static void LcpLinkFailure (fsm*);
+static void LcpEchoCheck (fsm*);
+
+/*
+ * Protocol entry points.
+ * Some of these are called directly.
+ */
+static void lcp_input (int, u_char *, int);
+static void lcp_protrej (int);
+
+#define CODENAME(x)	((x) == CONFACK ? "ACK" : \
+			 (x) == CONFNAK ? "NAK" : "REJ")
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+/* global vars */
+LinkPhase lcp_phase[NUM_PPP];			/* Phase of link session (RFC 1661) */
+lcp_options lcp_wantoptions[NUM_PPP];	/* Options that we want to request */
+lcp_options lcp_gotoptions[NUM_PPP];	/* Options that peer ack'd */
+lcp_options lcp_allowoptions[NUM_PPP];	/* Options we allow peer to request */
+lcp_options lcp_hisoptions[NUM_PPP];	/* Options that we ack'd */
+ext_accm xmit_accm[NUM_PPP];			/* extended transmit ACCM */
+
+
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+static fsm lcp_fsm[NUM_PPP];			/* LCP fsm structure (global)*/
+static u_int	 lcp_echo_interval = LCP_ECHOINTERVAL; /* Interval between LCP echo-requests */
+static u_int	 lcp_echo_fails = LCP_MAXECHOFAILS; /* Tolerance to unanswered echo-requests */
+static u32_t lcp_echos_pending = 0;	/* Number of outstanding echo msgs */
+static u32_t lcp_echo_number   = 0;	/* ID number of next echo frame */
+static u32_t lcp_echo_timer_running = 0;  /* TRUE if a timer is running */
+
+static u_char nak_buffer[PPP_MRU];	/* where we construct a nak packet */
+
+static fsm_callbacks lcp_callbacks = {	/* LCP callback routines */
+    lcp_resetci,		/* Reset our Configuration Information */
+    lcp_cilen,			/* Length of our Configuration Information */
+    lcp_addci,			/* Add our Configuration Information */
+    lcp_ackci,			/* ACK our Configuration Information */
+    lcp_nakci,			/* NAK our Configuration Information */
+    lcp_rejci,			/* Reject our Configuration Information */
+    lcp_reqci,			/* Request peer's Configuration Information */
+    lcp_up,				/* Called when fsm reaches OPENED state */
+    lcp_down,			/* Called when fsm leaves OPENED state */
+    lcp_starting,		/* Called when we want the lower layer up */
+    lcp_finished,		/* Called when we want the lower layer down */
+    NULL,				/* Called when Protocol-Reject received */
+    NULL,				/* Retransmission is necessary */
+    lcp_extcode,		/* Called to handle LCP-specific codes */
+    "LCP"				/* String name of protocol */
+};
+
+struct protent lcp_protent = {
+    PPP_LCP,
+    lcp_init,
+    lcp_input,
+    lcp_protrej,
+    lcp_lowerup,
+    lcp_lowerdown,
+    lcp_open,
+    lcp_close,
+#if 0
+    lcp_printpkt,
+    NULL,
+#endif
+    1,
+    "LCP",
+#if 0
+    NULL,
+    NULL,
+    NULL
+#endif
+};
+
+int lcp_loopbackfail = DEFLOOPBACKFAIL;
+
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ * lcp_init - Initialize LCP.
+ */
+void lcp_init(int unit)
+{
+	fsm *f = &lcp_fsm[unit];
+	lcp_options *wo = &lcp_wantoptions[unit];
+	lcp_options *ao = &lcp_allowoptions[unit];
+	
+	f->unit = unit;
+	f->protocol = PPP_LCP;
+	f->callbacks = &lcp_callbacks;
+	
+	fsm_init(f);
+	
+	wo->passive = 0;
+	wo->silent = 0;
+	wo->restart = 0;			/* Set to 1 in kernels or multi-line
+								 * implementations */
+	wo->neg_mru = 1;
+	wo->mru = PPP_DEFMRU;
+	wo->neg_asyncmap = 1;
+	wo->asyncmap = 0x00000000l;	/* Assume don't need to escape any ctl chars. */
+	wo->neg_chap = 0;			/* Set to 1 on server */
+	wo->neg_upap = 0;			/* Set to 1 on server */
+	wo->chap_mdtype = CHAP_DIGEST_MD5;
+	wo->neg_magicnumber = 1;
+	wo->neg_pcompression = 1;
+	wo->neg_accompression = 1;
+	wo->neg_lqr = 0;			/* no LQR implementation yet */
+	wo->neg_cbcp = 0;
+	
+	ao->neg_mru = 1;
+	ao->mru = PPP_MAXMRU;
+	ao->neg_asyncmap = 1;
+	ao->asyncmap = 0x00000000l;	/* Assume don't need to escape any ctl chars. */
+	ao->neg_chap = (CHAP_SUPPORT != 0);
+	ao->chap_mdtype = CHAP_DIGEST_MD5;
+	ao->neg_upap = (PAP_SUPPORT != 0);
+	ao->neg_magicnumber = 1;
+	ao->neg_pcompression = 1;
+	ao->neg_accompression = 1;
+	ao->neg_lqr = 0;			/* no LQR implementation yet */
+	ao->neg_cbcp = (CBCP_SUPPORT != 0);
+
+	/* 
+	 * Set transmit escape for the flag and escape characters plus anything
+	 * set for the allowable options.
+	 */
+	memset(xmit_accm[unit], 0, sizeof(xmit_accm[0]));
+	xmit_accm[unit][15] = 0x60;
+	xmit_accm[unit][0] = (u_char)(ao->asyncmap & 0xFF);
+	xmit_accm[unit][1] = (u_char)((ao->asyncmap >> 8) & 0xFF);
+	xmit_accm[unit][2] = (u_char)((ao->asyncmap >> 16) & 0xFF);
+	xmit_accm[unit][3] = (u_char)((ao->asyncmap >> 24) & 0xFF);
+	LCPDEBUG((LOG_INFO, "lcp_init: xmit_accm=%X %X %X %X\n",
+				xmit_accm[unit][0],
+				xmit_accm[unit][1],
+				xmit_accm[unit][2],
+				xmit_accm[unit][3]));
+	
+	lcp_phase[unit] = PHASE_INITIALIZE;
+}
+
+
+/*
+ * lcp_open - LCP is allowed to come up.
+ */
+void lcp_open(int unit)
+{
+	fsm *f = &lcp_fsm[unit];
+	lcp_options *wo = &lcp_wantoptions[unit];
+	
+	f->flags = 0;
+	if (wo->passive)
+		f->flags |= OPT_PASSIVE;
+	if (wo->silent)
+		f->flags |= OPT_SILENT;
+	fsm_open(f);
+	
+	lcp_phase[unit] = PHASE_ESTABLISH; 
+}
+
+
+/*
+ * lcp_close - Take LCP down.
+ */
+void lcp_close(int unit, char *reason)
+{
+	fsm *f = &lcp_fsm[unit];
+	
+	if (lcp_phase[unit] != PHASE_DEAD)
+		lcp_phase[unit] = PHASE_TERMINATE;
+	if (f->state == STOPPED && f->flags & (OPT_PASSIVE|OPT_SILENT)) {
+		/*
+		 * This action is not strictly according to the FSM in RFC1548,
+		 * but it does mean that the program terminates if you do an
+		 * lcp_close() in passive/silent mode when a connection hasn't
+		 * been established.
+		 */
+		f->state = CLOSED;
+		lcp_finished(f);
+	}
+	else
+		fsm_close(&lcp_fsm[unit], reason);
+}
+
+
+/*
+ * lcp_lowerup - The lower layer is up.
+ */
+void lcp_lowerup(int unit)
+{
+	lcp_options *wo = &lcp_wantoptions[unit];
+	
+	/*
+	* Don't use A/C or protocol compression on transmission,
+	* but accept A/C and protocol compressed packets
+	* if we are going to ask for A/C and protocol compression.
+	*/
+	ppp_set_xaccm(unit, &xmit_accm[unit]);
+	ppp_send_config(unit, PPP_MRU, 0xffffffffl, 0, 0);
+	ppp_recv_config(unit, PPP_MRU, 0x00000000l,
+					wo->neg_pcompression, wo->neg_accompression);
+	peer_mru[unit] = PPP_MRU;
+	lcp_allowoptions[unit].asyncmap 
+		= (u_long)xmit_accm[unit][0]
+			| ((u_long)xmit_accm[unit][1] << 8)
+			| ((u_long)xmit_accm[unit][2] << 16)
+			| ((u_long)xmit_accm[unit][3] << 24);
+	LCPDEBUG((LOG_INFO, "lcp_lowerup: asyncmap=%X %X %X %X\n",
+				xmit_accm[unit][3],
+				xmit_accm[unit][2],
+				xmit_accm[unit][1],
+				xmit_accm[unit][0]));
+	
+	fsm_lowerup(&lcp_fsm[unit]);
+}
+
+
+/*
+ * lcp_lowerdown - The lower layer is down.
+ */
+void lcp_lowerdown(int unit)
+{
+	fsm_lowerdown(&lcp_fsm[unit]);
+}
+
+/*
+ * lcp_sprotrej - Send a Protocol-Reject for some protocol.
+ */
+void lcp_sprotrej(int unit, u_char *p, int len)
+{
+	/*
+	* Send back the protocol and the information field of the
+	* rejected packet.  We only get here if LCP is in the OPENED state.
+	*/
+
+	fsm_sdata(&lcp_fsm[unit], PROTREJ, ++lcp_fsm[unit].id,
+				p, len);
+}
+
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+/*
+ * lcp_input - Input LCP packet.
+ */
+static void lcp_input(int unit, u_char *p, int len)
+{
+	fsm *f = &lcp_fsm[unit];
+	
+	fsm_input(f, p, len);
+}
+
+
+/*
+ * lcp_extcode - Handle a LCP-specific code.
+ */
+static int lcp_extcode(fsm *f, int code, u_char id, u_char *inp, int len)
+{
+	u_char *magp;
+	
+	switch( code ){
+	case PROTREJ:
+		lcp_rprotrej(f, inp, len);
+		break;
+	
+	case ECHOREQ:
+		if (f->state != OPENED)
+			break;
+		LCPDEBUG((LOG_INFO, "lcp: Echo-Request, Rcvd id %d\n", id));
+		magp = inp;
+		PUTLONG(lcp_gotoptions[f->unit].magicnumber, magp);
+		fsm_sdata(f, ECHOREP, id, inp, len);
+		break;
+	
+	case ECHOREP:
+		lcp_received_echo_reply(f, id, inp, len);
+		break;
+	
+	case DISCREQ:
+		break;
+	
+	default:
+		return 0;
+	}
+	return 1;
+}
+
+    
+/*
+ * lcp_rprotrej - Receive an Protocol-Reject.
+ *
+ * Figure out which protocol is rejected and inform it.
+ */
+static void lcp_rprotrej(fsm *f, u_char *inp, int len)
+{
+	int i;
+	struct protent *protp;
+	u_short prot;
+	
+	if (len < sizeof (u_short)) {
+		LCPDEBUG((LOG_INFO,
+				"lcp_rprotrej: Rcvd short Protocol-Reject packet!\n"));
+		return;
+	}
+	
+	GETSHORT(prot, inp);
+	
+	LCPDEBUG((LOG_INFO,
+			"lcp_rprotrej: Rcvd Protocol-Reject packet for %x!\n",
+			prot));
+	
+	/*
+	* Protocol-Reject packets received in any state other than the LCP
+	* OPENED state SHOULD be silently discarded.
+	*/
+	if( f->state != OPENED ){
+		LCPDEBUG((LOG_INFO, "Protocol-Reject discarded: LCP in state %d\n",
+				f->state));
+		return;
+	}
+	
+	/*
+	* Upcall the proper Protocol-Reject routine.
+	*/
+	for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i)
+		if (protp->protocol == prot && protp->enabled_flag) {
+			(*protp->protrej)(f->unit);
+			return;
+		}
+	
+	LCPDEBUG((LOG_WARNING, "Protocol-Reject for unsupported protocol 0x%x\n",
+			prot));
+}
+
+
+/*
+ * lcp_protrej - A Protocol-Reject was received.
+ */
+static void lcp_protrej(int unit)
+{
+	(void)unit;
+	/*
+	* Can't reject LCP!
+	*/
+	LCPDEBUG((LOG_WARNING,
+			"lcp_protrej: Received Protocol-Reject for LCP!\n"));
+	fsm_protreject(&lcp_fsm[unit]);
+}
+
+
+/*
+ * lcp_resetci - Reset our CI.
+ */
+static void lcp_resetci(fsm *f)
+{
+	lcp_wantoptions[f->unit].magicnumber = magic();
+	lcp_wantoptions[f->unit].numloops = 0;
+	lcp_gotoptions[f->unit] = lcp_wantoptions[f->unit];
+	peer_mru[f->unit] = PPP_MRU;
+	auth_reset(f->unit);
+}
+
+
+/*
+ * lcp_cilen - Return length of our CI.
+ */
+static int lcp_cilen(fsm *f)
+{
+	lcp_options *go = &lcp_gotoptions[f->unit];
+
+#define LENCIVOID(neg)	((neg) ? CILEN_VOID : 0)
+#define LENCICHAP(neg)	((neg) ? CILEN_CHAP : 0)
+#define LENCISHORT(neg)	((neg) ? CILEN_SHORT : 0)
+#define LENCILONG(neg)	((neg) ? CILEN_LONG : 0)
+#define LENCILQR(neg)	((neg) ? CILEN_LQR: 0)
+#define LENCICBCP(neg)	((neg) ? CILEN_CBCP: 0)
+	/*
+	* NB: we only ask for one of CHAP and UPAP, even if we will
+	* accept either.
+	*/
+	return (LENCISHORT(go->neg_mru && go->mru != PPP_DEFMRU) +
+		LENCILONG(go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl) +
+		LENCICHAP(go->neg_chap) +
+		LENCISHORT(!go->neg_chap && go->neg_upap) +
+		LENCILQR(go->neg_lqr) +
+		LENCICBCP(go->neg_cbcp) +
+		LENCILONG(go->neg_magicnumber) +
+		LENCIVOID(go->neg_pcompression) +
+		LENCIVOID(go->neg_accompression));
+}
+
+
+/*
+ * lcp_addci - Add our desired CIs to a packet.
+ */
+static void lcp_addci(fsm *f, u_char *ucp, int *lenp)
+{
+	lcp_options *go = &lcp_gotoptions[f->unit];
+	u_char *start_ucp = ucp;
+	
+#define ADDCIVOID(opt, neg) \
+	if (neg) { \
+	    LCPDEBUG((LOG_INFO, "lcp_addci: opt=%d\n", opt)); \
+		PUTCHAR(opt, ucp); \
+		PUTCHAR(CILEN_VOID, ucp); \
+	}
+#define ADDCISHORT(opt, neg, val) \
+	if (neg) { \
+	    LCPDEBUG((LOG_INFO, "lcp_addci: INT opt=%d %X\n", opt, val)); \
+		PUTCHAR(opt, ucp); \
+		PUTCHAR(CILEN_SHORT, ucp); \
+		PUTSHORT(val, ucp); \
+	}
+#define ADDCICHAP(opt, neg, val, digest) \
+	if (neg) { \
+	    LCPDEBUG((LOG_INFO, "lcp_addci: CHAP opt=%d %X\n", opt, val)); \
+		PUTCHAR(opt, ucp); \
+		PUTCHAR(CILEN_CHAP, ucp); \
+		PUTSHORT(val, ucp); \
+		PUTCHAR(digest, ucp); \
+	}
+#define ADDCILONG(opt, neg, val) \
+	if (neg) { \
+	    LCPDEBUG((LOG_INFO, "lcp_addci: L opt=%d %lX\n", opt, val)); \
+		PUTCHAR(opt, ucp); \
+		PUTCHAR(CILEN_LONG, ucp); \
+		PUTLONG(val, ucp); \
+	}
+#define ADDCILQR(opt, neg, val) \
+	if (neg) { \
+	    LCPDEBUG((LOG_INFO, "lcp_addci: LQR opt=%d %lX\n", opt, val)); \
+		PUTCHAR(opt, ucp); \
+		PUTCHAR(CILEN_LQR, ucp); \
+		PUTSHORT(PPP_LQR, ucp); \
+		PUTLONG(val, ucp); \
+	}
+#define ADDCICHAR(opt, neg, val) \
+	if (neg) { \
+	    LCPDEBUG((LOG_INFO, "lcp_addci: CHAR opt=%d %X '%z'\n", opt, val, val)); \
+		PUTCHAR(opt, ucp); \
+		PUTCHAR(CILEN_CHAR, ucp); \
+		PUTCHAR(val, ucp); \
+	}
+	
+	ADDCISHORT(CI_MRU, go->neg_mru && go->mru != PPP_DEFMRU, go->mru);
+	ADDCILONG(CI_ASYNCMAP, go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl,
+			go->asyncmap);
+	ADDCICHAP(CI_AUTHTYPE, go->neg_chap, PPP_CHAP, go->chap_mdtype);
+	ADDCISHORT(CI_AUTHTYPE, !go->neg_chap && go->neg_upap, PPP_PAP);
+	ADDCILQR(CI_QUALITY, go->neg_lqr, go->lqr_period);
+	ADDCICHAR(CI_CALLBACK, go->neg_cbcp, CBCP_OPT);
+	ADDCILONG(CI_MAGICNUMBER, go->neg_magicnumber, go->magicnumber);
+	ADDCIVOID(CI_PCOMPRESSION, go->neg_pcompression);
+	ADDCIVOID(CI_ACCOMPRESSION, go->neg_accompression);
+	
+	if (ucp - start_ucp != *lenp) {
+		/* this should never happen, because peer_mtu should be 1500 */
+		LCPDEBUG((LOG_ERR, "Bug in lcp_addci: wrong length\n"));
+	}
+}
+
+
+/*
+ * lcp_ackci - Ack our CIs.
+ * This should not modify any state if the Ack is bad.
+ *
+ * Returns:
+ *	0 - Ack was bad.
+ *	1 - Ack was good.
+ */
+static int lcp_ackci(fsm *f, u_char *p, int len)
+{
+	lcp_options *go = &lcp_gotoptions[f->unit];
+	u_char cilen, citype, cichar;
+	u_short cishort;
+	u32_t cilong;
+	
+	/*
+	* CIs must be in exactly the same order that we sent.
+	* Check packet length and CI length at each step.
+	* If we find any deviations, then this packet is bad.
+	*/
+#define ACKCIVOID(opt, neg) \
+	if (neg) { \
+		if ((len -= CILEN_VOID) < 0) \
+			goto bad; \
+		GETCHAR(citype, p); \
+		GETCHAR(cilen, p); \
+		if (cilen != CILEN_VOID || \
+				citype != opt) \
+			goto bad; \
+	}
+#define ACKCISHORT(opt, neg, val) \
+	if (neg) { \
+		if ((len -= CILEN_SHORT) < 0) \
+			goto bad; \
+		GETCHAR(citype, p); \
+		GETCHAR(cilen, p); \
+		if (cilen != CILEN_SHORT || \
+				citype != opt) \
+			goto bad; \
+		GETSHORT(cishort, p); \
+		if (cishort != val) \
+			goto bad; \
+	}
+#define ACKCICHAR(opt, neg, val) \
+	if (neg) { \
+		if ((len -= CILEN_CHAR) < 0) \
+			goto bad; \
+		GETCHAR(citype, p); \
+		GETCHAR(cilen, p); \
+		if (cilen != CILEN_CHAR || \
+				citype != opt) \
+			goto bad; \
+		GETCHAR(cichar, p); \
+		if (cichar != val) \
+			goto bad; \
+	}
+#define ACKCICHAP(opt, neg, val, digest) \
+	if (neg) { \
+		if ((len -= CILEN_CHAP) < 0) \
+			goto bad; \
+		GETCHAR(citype, p); \
+		GETCHAR(cilen, p); \
+		if (cilen != CILEN_CHAP || \
+				citype != opt) \
+			goto bad; \
+		GETSHORT(cishort, p); \
+		if (cishort != val) \
+			goto bad; \
+		GETCHAR(cichar, p); \
+		if (cichar != digest) \
+			goto bad; \
+	}
+#define ACKCILONG(opt, neg, val) \
+	if (neg) { \
+		if ((len -= CILEN_LONG) < 0) \
+			goto bad; \
+		GETCHAR(citype, p); \
+		GETCHAR(cilen, p); \
+		if (cilen != CILEN_LONG || \
+				citype != opt) \
+			goto bad; \
+		GETLONG(cilong, p); \
+		if (cilong != val) \
+			goto bad; \
+	}
+#define ACKCILQR(opt, neg, val) \
+	if (neg) { \
+		if ((len -= CILEN_LQR) < 0) \
+			goto bad; \
+		GETCHAR(citype, p); \
+		GETCHAR(cilen, p); \
+		if (cilen != CILEN_LQR || \
+				citype != opt) \
+			goto bad; \
+		GETSHORT(cishort, p); \
+		if (cishort != PPP_LQR) \
+			goto bad; \
+		GETLONG(cilong, p); \
+		if (cilong != val) \
+			goto bad; \
+	}
+	
+	ACKCISHORT(CI_MRU, go->neg_mru && go->mru != PPP_DEFMRU, go->mru);
+	ACKCILONG(CI_ASYNCMAP, go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl,
+			go->asyncmap);
+	ACKCICHAP(CI_AUTHTYPE, go->neg_chap, PPP_CHAP, go->chap_mdtype);
+	ACKCISHORT(CI_AUTHTYPE, !go->neg_chap && go->neg_upap, PPP_PAP);
+	ACKCILQR(CI_QUALITY, go->neg_lqr, go->lqr_period);
+	ACKCICHAR(CI_CALLBACK, go->neg_cbcp, CBCP_OPT);
+	ACKCILONG(CI_MAGICNUMBER, go->neg_magicnumber, go->magicnumber);
+	ACKCIVOID(CI_PCOMPRESSION, go->neg_pcompression);
+	ACKCIVOID(CI_ACCOMPRESSION, go->neg_accompression);
+	
+	/*
+	 * If there are any remaining CIs, then this packet is bad.
+	 */
+	if (len != 0)
+		goto bad;
+	LCPDEBUG((LOG_INFO, "lcp_acki: Ack\n"));
+	return (1);
+bad:
+	LCPDEBUG((LOG_WARNING, "lcp_acki: received bad Ack!\n"));
+	return (0);
+}
+
+
+/*
+ * lcp_nakci - Peer has sent a NAK for some of our CIs.
+ * This should not modify any state if the Nak is bad
+ * or if LCP is in the OPENED state.
+ *
+ * Returns:
+ *	0 - Nak was bad.
+ *	1 - Nak was good.
+ */
+static int lcp_nakci(fsm *f, u_char *p, int len)
+{
+	lcp_options *go = &lcp_gotoptions[f->unit];
+	lcp_options *wo = &lcp_wantoptions[f->unit];
+	u_char citype, cichar, *next;
+	u_short cishort;
+	u32_t cilong;
+	lcp_options no;		/* options we've seen Naks for */
+	lcp_options try;		/* options to request next time */
+	int looped_back = 0;
+	int cilen;
+	
+	BZERO(&no, sizeof(no));
+	try = *go;
+	
+	/*
+	* Any Nak'd CIs must be in exactly the same order that we sent.
+	* Check packet length and CI length at each step.
+	* If we find any deviations, then this packet is bad.
+	*/
+#define NAKCIVOID(opt, neg, code) \
+	if (go->neg && \
+			len >= CILEN_VOID && \
+			p[1] == CILEN_VOID && \
+			p[0] == opt) { \
+		len -= CILEN_VOID; \
+		INCPTR(CILEN_VOID, p); \
+		no.neg = 1; \
+		code \
+	}
+#define NAKCICHAP(opt, neg, code) \
+	if (go->neg && \
+			len >= CILEN_CHAP && \
+			p[1] == CILEN_CHAP && \
+			p[0] == opt) { \
+		len -= CILEN_CHAP; \
+		INCPTR(2, p); \
+		GETSHORT(cishort, p); \
+		GETCHAR(cichar, p); \
+		no.neg = 1; \
+		code \
+	}
+#define NAKCICHAR(opt, neg, code) \
+	if (go->neg && \
+			len >= CILEN_CHAR && \
+			p[1] == CILEN_CHAR && \
+			p[0] == opt) { \
+		len -= CILEN_CHAR; \
+		INCPTR(2, p); \
+		GETCHAR(cichar, p); \
+		no.neg = 1; \
+		code \
+	}
+#define NAKCISHORT(opt, neg, code) \
+	if (go->neg && \
+			len >= CILEN_SHORT && \
+			p[1] == CILEN_SHORT && \
+			p[0] == opt) { \
+		len -= CILEN_SHORT; \
+		INCPTR(2, p); \
+		GETSHORT(cishort, p); \
+		no.neg = 1; \
+		code \
+	}
+#define NAKCILONG(opt, neg, code) \
+	if (go->neg && \
+			len >= CILEN_LONG && \
+			p[1] == CILEN_LONG && \
+			p[0] == opt) { \
+		len -= CILEN_LONG; \
+		INCPTR(2, p); \
+		GETLONG(cilong, p); \
+		no.neg = 1; \
+		code \
+	}
+#define NAKCILQR(opt, neg, code) \
+	if (go->neg && \
+			len >= CILEN_LQR && \
+			p[1] == CILEN_LQR && \
+			p[0] == opt) { \
+		len -= CILEN_LQR; \
+		INCPTR(2, p); \
+		GETSHORT(cishort, p); \
+		GETLONG(cilong, p); \
+		no.neg = 1; \
+		code \
+	}
+	
+	/*
+	* We don't care if they want to send us smaller packets than
+	* we want.  Therefore, accept any MRU less than what we asked for,
+	* but then ignore the new value when setting the MRU in the kernel.
+	* If they send us a bigger MRU than what we asked, accept it, up to
+	* the limit of the default MRU we'd get if we didn't negotiate.
+	*/
+	if (go->neg_mru && go->mru != PPP_DEFMRU) {
+		NAKCISHORT(CI_MRU, neg_mru,
+			if (cishort <= wo->mru || cishort < PPP_DEFMRU)
+				try.mru = cishort;
+		);
+	}
+	
+	/*
+	* Add any characters they want to our (receive-side) asyncmap.
+	*/
+	if (go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl) {
+		NAKCILONG(CI_ASYNCMAP, neg_asyncmap,
+			try.asyncmap = go->asyncmap | cilong;
+		);
+	}
+	
+	/*
+	* If they've nak'd our authentication-protocol, check whether
+	* they are proposing a different protocol, or a different
+	* hash algorithm for CHAP.
+	*/
+	if ((go->neg_chap || go->neg_upap)
+			&& len >= CILEN_SHORT
+			&& p[0] == CI_AUTHTYPE && p[1] >= CILEN_SHORT && p[1] <= len) {
+		cilen = p[1];
+	len -= cilen;
+	no.neg_chap = go->neg_chap;
+	no.neg_upap = go->neg_upap;
+	INCPTR(2, p);
+	GETSHORT(cishort, p);
+	if (cishort == PPP_PAP && cilen == CILEN_SHORT) {
+		/*
+		 * If we were asking for CHAP, they obviously don't want to do it.
+		 * If we weren't asking for CHAP, then we were asking for PAP,
+		 * in which case this Nak is bad.
+		 */
+		if (!go->neg_chap)
+			goto bad;
+		try.neg_chap = 0;
+	
+	} else if (cishort == PPP_CHAP && cilen == CILEN_CHAP) {
+		GETCHAR(cichar, p);
+		if (go->neg_chap) {
+			/*
+			 * We were asking for CHAP/MD5; they must want a different
+			 * algorithm.  If they can't do MD5, we'll have to stop
+			 * asking for CHAP.
+			 */
+			if (cichar != go->chap_mdtype)
+				try.neg_chap = 0;
+		} else {
+			/*
+			 * Stop asking for PAP if we were asking for it.
+			 */
+			try.neg_upap = 0;
+		}
+	
+	} else {
+		/*
+		 * We don't recognize what they're suggesting.
+		 * Stop asking for what we were asking for.
+		 */
+		if (go->neg_chap)
+			try.neg_chap = 0;
+		else
+			try.neg_upap = 0;
+		p += cilen - CILEN_SHORT;
+	}
+	}
+	
+	/*
+	* If they can't cope with our link quality protocol, we'll have
+	* to stop asking for LQR.  We haven't got any other protocol.
+	* If they Nak the reporting period, take their value XXX ?
+	*/
+	NAKCILQR(CI_QUALITY, neg_lqr,
+		if (cishort != PPP_LQR)
+			try.neg_lqr = 0;
+		else
+			try.lqr_period = cilong;
+	);
+	
+	/*
+	* Only implementing CBCP...not the rest of the callback options
+	*/
+	NAKCICHAR(CI_CALLBACK, neg_cbcp,
+		try.neg_cbcp = 0;
+	);
+	
+	/*
+	* Check for a looped-back line.
+	*/
+	NAKCILONG(CI_MAGICNUMBER, neg_magicnumber,
+		try.magicnumber = magic();
+		looped_back = 1;
+	);
+	
+	/*
+	* Peer shouldn't send Nak for protocol compression or
+	* address/control compression requests; they should send
+	* a Reject instead.  If they send a Nak, treat it as a Reject.
+	*/
+	NAKCIVOID(CI_PCOMPRESSION, neg_pcompression,
+		try.neg_pcompression = 0;
+	);
+	NAKCIVOID(CI_ACCOMPRESSION, neg_accompression,
+		try.neg_accompression = 0;
+	);
+	
+	/*
+	* There may be remaining CIs, if the peer is requesting negotiation
+	* on an option that we didn't include in our request packet.
+	* If we see an option that we requested, or one we've already seen
+	* in this packet, then this packet is bad.
+	* If we wanted to respond by starting to negotiate on the requested
+	* option(s), we could, but we don't, because except for the
+	* authentication type and quality protocol, if we are not negotiating
+	* an option, it is because we were told not to.
+	* For the authentication type, the Nak from the peer means
+	* `let me authenticate myself with you' which is a bit pointless.
+	* For the quality protocol, the Nak means `ask me to send you quality
+	* reports', but if we didn't ask for them, we don't want them.
+	* An option we don't recognize represents the peer asking to
+	* negotiate some option we don't support, so ignore it.
+	*/
+	while (len > CILEN_VOID) {
+		GETCHAR(citype, p);
+		GETCHAR(cilen, p);
+		if (cilen < CILEN_VOID || (len -= cilen) < 0)
+			goto bad;
+		next = p + cilen - 2;
+		
+		switch (citype) {
+		case CI_MRU:
+			if ((go->neg_mru && go->mru != PPP_DEFMRU)
+					|| no.neg_mru || cilen != CILEN_SHORT)
+				goto bad;
+			GETSHORT(cishort, p);
+			if (cishort < PPP_DEFMRU)
+				try.mru = cishort;
+			break;
+		case CI_ASYNCMAP:
+			if ((go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl)
+					|| no.neg_asyncmap || cilen != CILEN_LONG)
+				goto bad;
+			break;
+		case CI_AUTHTYPE:
+			if (go->neg_chap || no.neg_chap || go->neg_upap || no.neg_upap)
+				goto bad;
+			break;
+		case CI_MAGICNUMBER:
+			if (go->neg_magicnumber || no.neg_magicnumber ||
+					cilen != CILEN_LONG)
+				goto bad;
+			break;
+		case CI_PCOMPRESSION:
+			if (go->neg_pcompression || no.neg_pcompression
+					|| cilen != CILEN_VOID)
+				goto bad;
+			break;
+		case CI_ACCOMPRESSION:
+			if (go->neg_accompression || no.neg_accompression
+					|| cilen != CILEN_VOID)
+				goto bad;
+			break;
+		case CI_QUALITY:
+			if (go->neg_lqr || no.neg_lqr || cilen != CILEN_LQR)
+				goto bad;
+			break;
+		}
+		p = next;
+	}
+	
+	/* If there is still anything left, this packet is bad. */
+	if (len != 0)
+		goto bad;
+	
+	/*
+	* OK, the Nak is good.  Now we can update state.
+	*/
+	if (f->state != OPENED) {
+		if (looped_back) {
+			if (++try.numloops >= lcp_loopbackfail) {
+				LCPDEBUG((LOG_NOTICE, "Serial line is looped back.\n"));
+				lcp_close(f->unit, "Loopback detected");
+			}
+		} 
+		else
+			try.numloops = 0;
+		*go = try;
+	}
+	
+	return 1;
+	
+bad:
+	LCPDEBUG((LOG_WARNING, "lcp_nakci: received bad Nak!\n"));
+	return 0;
+}
+
+
+/*
+ * lcp_rejci - Peer has Rejected some of our CIs.
+ * This should not modify any state if the Reject is bad
+ * or if LCP is in the OPENED state.
+ *
+ * Returns:
+ *	0 - Reject was bad.
+ *	1 - Reject was good.
+ */
+static int lcp_rejci(fsm *f, u_char *p, int len)
+{
+	lcp_options *go = &lcp_gotoptions[f->unit];
+	u_char cichar;
+	u_short cishort;
+	u32_t cilong;
+	lcp_options try;		/* options to request next time */
+	
+	try = *go;
+	
+	/*
+	* Any Rejected CIs must be in exactly the same order that we sent.
+	* Check packet length and CI length at each step.
+	* If we find any deviations, then this packet is bad.
+	*/
+#define REJCIVOID(opt, neg) \
+	if (go->neg && \
+			len >= CILEN_VOID && \
+			p[1] == CILEN_VOID && \
+			p[0] == opt) { \
+		len -= CILEN_VOID; \
+		INCPTR(CILEN_VOID, p); \
+		try.neg = 0; \
+		LCPDEBUG((LOG_INFO, "lcp_rejci: void opt %d rejected\n", opt)); \
+	}
+#define REJCISHORT(opt, neg, val) \
+	if (go->neg && \
+			len >= CILEN_SHORT && \
+			p[1] == CILEN_SHORT && \
+			p[0] == opt) { \
+		len -= CILEN_SHORT; \
+		INCPTR(2, p); \
+		GETSHORT(cishort, p); \
+		/* Check rejected value. */ \
+		if (cishort != val) \
+			goto bad; \
+		try.neg = 0; \
+		LCPDEBUG((LOG_INFO,"lcp_rejci: short opt %d rejected\n", opt)); \
+	}
+#define REJCICHAP(opt, neg, val, digest) \
+	if (go->neg && \
+			len >= CILEN_CHAP && \
+			p[1] == CILEN_CHAP && \
+			p[0] == opt) { \
+		len -= CILEN_CHAP; \
+		INCPTR(2, p); \
+		GETSHORT(cishort, p); \
+		GETCHAR(cichar, p); \
+		/* Check rejected value. */ \
+		if (cishort != val || cichar != digest) \
+			goto bad; \
+		try.neg = 0; \
+		try.neg_upap = 0; \
+		LCPDEBUG((LOG_INFO,"lcp_rejci: chap opt %d rejected\n", opt)); \
+	}
+#define REJCILONG(opt, neg, val) \
+	if (go->neg && \
+			len >= CILEN_LONG && \
+			p[1] == CILEN_LONG && \
+			p[0] == opt) { \
+		len -= CILEN_LONG; \
+		INCPTR(2, p); \
+		GETLONG(cilong, p); \
+		/* Check rejected value. */ \
+		if (cilong != val) \
+			goto bad; \
+		try.neg = 0; \
+		LCPDEBUG((LOG_INFO,"lcp_rejci: long opt %d rejected\n", opt)); \
+	}
+#define REJCILQR(opt, neg, val) \
+	if (go->neg && \
+			len >= CILEN_LQR && \
+			p[1] == CILEN_LQR && \
+			p[0] == opt) { \
+		len -= CILEN_LQR; \
+		INCPTR(2, p); \
+		GETSHORT(cishort, p); \
+		GETLONG(cilong, p); \
+		/* Check rejected value. */ \
+		if (cishort != PPP_LQR || cilong != val) \
+			goto bad; \
+		try.neg = 0; \
+		LCPDEBUG((LOG_INFO,"lcp_rejci: LQR opt %d rejected\n", opt)); \
+	}
+#define REJCICBCP(opt, neg, val) \
+	if (go->neg && \
+			len >= CILEN_CBCP && \
+			p[1] == CILEN_CBCP && \
+			p[0] == opt) { \
+		len -= CILEN_CBCP; \
+		INCPTR(2, p); \
+		GETCHAR(cichar, p); \
+		/* Check rejected value. */ \
+		if (cichar != val) \
+			goto bad; \
+		try.neg = 0; \
+		LCPDEBUG((LOG_INFO,"lcp_rejci: Callback opt %d rejected\n", opt)); \
+	}
+	
+	REJCISHORT(CI_MRU, neg_mru, go->mru);
+	REJCILONG(CI_ASYNCMAP, neg_asyncmap, go->asyncmap);
+	REJCICHAP(CI_AUTHTYPE, neg_chap, PPP_CHAP, go->chap_mdtype);
+	if (!go->neg_chap) {
+		REJCISHORT(CI_AUTHTYPE, neg_upap, PPP_PAP);
+	}
+	REJCILQR(CI_QUALITY, neg_lqr, go->lqr_period);
+	REJCICBCP(CI_CALLBACK, neg_cbcp, CBCP_OPT);
+	REJCILONG(CI_MAGICNUMBER, neg_magicnumber, go->magicnumber);
+	REJCIVOID(CI_PCOMPRESSION, neg_pcompression);
+	REJCIVOID(CI_ACCOMPRESSION, neg_accompression);
+	
+	/*
+	* If there are any remaining CIs, then this packet is bad.
+	*/
+	if (len != 0)
+		goto bad;
+	/*
+	* Now we can update state.
+	*/
+	if (f->state != OPENED)
+		*go = try;
+	return 1;
+	
+bad:
+	LCPDEBUG((LOG_WARNING, "lcp_rejci: received bad Reject!\n"));
+	return 0;
+}
+
+
+/*
+ * lcp_reqci - Check the peer's requested CIs and send appropriate response.
+ *
+ * Returns: CONFACK, CONFNAK or CONFREJ and input packet modified
+ * appropriately.  If reject_if_disagree is non-zero, doesn't return
+ * CONFNAK; returns CONFREJ if it can't return CONFACK.
+ */
+static int lcp_reqci(fsm *f, 
+						u_char *inp,		/* Requested CIs */
+						int *lenp,			/* Length of requested CIs */
+						int reject_if_disagree)
+{
+	lcp_options *go = &lcp_gotoptions[f->unit];
+	lcp_options *ho = &lcp_hisoptions[f->unit];
+	lcp_options *ao = &lcp_allowoptions[f->unit];
+	u_char *cip, *next;			/* Pointer to current and next CIs */
+	int cilen, citype, cichar;	/* Parsed len, type, char value */
+	u_short cishort;			/* Parsed short value */
+	u32_t cilong;			/* Parse long value */
+	int rc = CONFACK;			/* Final packet return code */
+	int orc;					/* Individual option return code */
+	u_char *p;					/* Pointer to next char to parse */
+	u_char *rejp;				/* Pointer to next char in reject frame */
+	u_char *nakp;				/* Pointer to next char in Nak frame */
+	int l = *lenp;				/* Length left */
+#if TRACELCP > 0
+	char traceBuf[80];
+	int traceNdx = 0;
+#endif
+	
+	/*
+	 * Reset all his options.
+	 */
+	BZERO(ho, sizeof(*ho));
+	
+	/*
+	 * Process all his options.
+	 */
+	next = inp;
+	nakp = nak_buffer;
+	rejp = inp;
+	while (l) {
+		orc = CONFACK;			/* Assume success */
+		cip = p = next;			/* Remember begining of CI */
+		if (l < 2 ||			/* Not enough data for CI header or */
+				p[1] < 2 ||			/*  CI length too small or */
+				p[1] > l) {			/*  CI length too big? */
+			LCPDEBUG((LOG_WARNING, "lcp_reqci: bad CI length!\n"));
+			orc = CONFREJ;		/* Reject bad CI */
+			cilen = l;			/* Reject till end of packet */
+			l = 0;			/* Don't loop again */
+			citype = 0;
+			goto endswitch;
+		}
+		GETCHAR(citype, p);		/* Parse CI type */
+		GETCHAR(cilen, p);		/* Parse CI length */
+		l -= cilen;			/* Adjust remaining length */
+		next += cilen;			/* Step to next CI */
+		
+		switch (citype) {		/* Check CI type */
+		case CI_MRU:
+			if (!ao->neg_mru) {		/* Allow option? */
+				LCPDEBUG((LOG_INFO, "lcp_reqci: Reject MRU - not allowed\n"));
+				orc = CONFREJ;		/* Reject CI */
+				break;
+			} else if (cilen != CILEN_SHORT) {	/* Check CI length */
+				LCPDEBUG((LOG_INFO, "lcp_reqci: Reject MRU - bad length\n"));
+				orc = CONFREJ;		/* Reject CI */
+				break;
+			}
+			GETSHORT(cishort, p);	/* Parse MRU */
+			
+			/*
+			 * He must be able to receive at least our minimum.
+			 * No need to check a maximum.  If he sends a large number,
+			 * we'll just ignore it.
+			 */
+			if (cishort < PPP_MINMRU) {
+				LCPDEBUG((LOG_INFO, "lcp_reqci: Nak - MRU too small\n"));
+				orc = CONFNAK;		/* Nak CI */
+				PUTCHAR(CI_MRU, nakp);
+				PUTCHAR(CILEN_SHORT, nakp);
+				PUTSHORT(PPP_MINMRU, nakp);	/* Give him a hint */
+				break;
+			}
+			ho->neg_mru = 1;		/* Remember he sent MRU */
+			ho->mru = cishort;		/* And remember value */
+#if TRACELCP > 0
+			snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " MRU %d", cishort);
+			traceNdx = strlen(traceBuf);
+#endif
+			break;
+		
+		case CI_ASYNCMAP:
+			if (!ao->neg_asyncmap) {
+				LCPDEBUG((LOG_INFO, "lcp_reqci: Reject ASYNCMAP not allowed\n"));
+				orc = CONFREJ;
+				break;
+			} else if (cilen != CILEN_LONG) {
+				LCPDEBUG((LOG_INFO, "lcp_reqci: Reject ASYNCMAP bad length\n"));
+				orc = CONFREJ;
+				break;
+			}
+			GETLONG(cilong, p);
+			
+			/*
+			 * Asyncmap must have set at least the bits
+			 * which are set in lcp_allowoptions[unit].asyncmap.
+			 */
+			if ((ao->asyncmap & ~cilong) != 0) {
+				LCPDEBUG((LOG_INFO, "lcp_reqci: Nak ASYNCMAP %lX missing %lX\n", 
+							cilong, ao->asyncmap));
+				orc = CONFNAK;
+				PUTCHAR(CI_ASYNCMAP, nakp);
+				PUTCHAR(CILEN_LONG, nakp);
+				PUTLONG(ao->asyncmap | cilong, nakp);
+				break;
+			}
+			ho->neg_asyncmap = 1;
+			ho->asyncmap = cilong;
+#if TRACELCP > 0
+			snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " ASYNCMAP=%lX", cilong);
+			traceNdx = strlen(traceBuf);
+#endif
+			break;
+		
+		case CI_AUTHTYPE:
+			if (cilen < CILEN_SHORT) {
+				LCPDEBUG((LOG_INFO, "lcp_reqci: Reject AUTHTYPE missing arg\n"));
+				orc = CONFREJ;
+				break;
+			} else if (!(ao->neg_upap || ao->neg_chap)) {
+				/*
+				 * Reject the option if we're not willing to authenticate.
+				 */
+				LCPDEBUG((LOG_INFO, "lcp_reqci: Reject AUTHTYPE not allowed\n"));
+				orc = CONFREJ;
+				break;
+			}
+			GETSHORT(cishort, p);
+			
+			/*
+			 * Authtype must be UPAP or CHAP.
+			 *
+			 * Note: if both ao->neg_upap and ao->neg_chap are set,
+			 * and the peer sends a Configure-Request with two
+			 * authenticate-protocol requests, one for CHAP and one
+			 * for UPAP, then we will reject the second request.
+			 * Whether we end up doing CHAP or UPAP depends then on
+			 * the ordering of the CIs in the peer's Configure-Request.
+			 */
+			
+			if (cishort == PPP_PAP) {
+				if (ho->neg_chap) {	/* we've already accepted CHAP */
+					LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE PAP already accepted\n"));
+					orc = CONFREJ;
+					break;
+				} else if (cilen != CILEN_SHORT) {
+					LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE PAP bad len\n"));
+					orc = CONFREJ;
+					break;
+				}
+				if (!ao->neg_upap) {	/* we don't want to do PAP */
+					LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE PAP not allowed\n"));
+					orc = CONFNAK;	/* NAK it and suggest CHAP */
+					PUTCHAR(CI_AUTHTYPE, nakp);
+					PUTCHAR(CILEN_CHAP, nakp);
+					PUTSHORT(PPP_CHAP, nakp);
+					PUTCHAR(ao->chap_mdtype, nakp);
+					break;
+				}
+				ho->neg_upap = 1;
+#if TRACELCP > 0
+				snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " PAP (%X)", cishort);
+				traceNdx = strlen(traceBuf);
+#endif
+				break;
+			}
+			if (cishort == PPP_CHAP) {
+				if (ho->neg_upap) {	/* we've already accepted PAP */
+					LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE CHAP accepted PAP\n"));
+					orc = CONFREJ;
+					break;
+				} else if (cilen != CILEN_CHAP) {
+					LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE CHAP bad len\n"));
+					orc = CONFREJ;
+					break;
+				}
+				if (!ao->neg_chap) {	/* we don't want to do CHAP */
+					LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE CHAP not allowed\n"));
+					orc = CONFNAK;	/* NAK it and suggest PAP */
+					PUTCHAR(CI_AUTHTYPE, nakp);
+					PUTCHAR(CILEN_SHORT, nakp);
+					PUTSHORT(PPP_PAP, nakp);
+					break;
+				}
+				GETCHAR(cichar, p);	/* get digest type*/
+				if (cichar != CHAP_DIGEST_MD5
+#ifdef CHAPMS
+						&& cichar != CHAP_MICROSOFT
+#endif
+				) {
+					LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE CHAP digest=%d\n", cichar));
+					orc = CONFNAK;
+					PUTCHAR(CI_AUTHTYPE, nakp);
+					PUTCHAR(CILEN_CHAP, nakp);
+					PUTSHORT(PPP_CHAP, nakp);
+					PUTCHAR(ao->chap_mdtype, nakp);
+					break;
+				}
+#if TRACELCP > 0
+				snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CHAP %X,%d", cishort, cichar);
+				traceNdx = strlen(traceBuf);
+#endif
+				ho->chap_mdtype = cichar; /* save md type */
+				ho->neg_chap = 1;
+				break;
+			}
+			
+			/*
+			 * We don't recognize the protocol they're asking for.
+			 * Nak it with something we're willing to do.
+			 * (At this point we know ao->neg_upap || ao->neg_chap.)
+			 */
+			orc = CONFNAK;
+			PUTCHAR(CI_AUTHTYPE, nakp);
+			if (ao->neg_chap) {
+				LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE %d req CHAP\n", cishort));
+				PUTCHAR(CILEN_CHAP, nakp);
+				PUTSHORT(PPP_CHAP, nakp);
+				PUTCHAR(ao->chap_mdtype, nakp);
+			} 
+			else {
+				LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE %d req PAP\n", cishort));
+				PUTCHAR(CILEN_SHORT, nakp);
+				PUTSHORT(PPP_PAP, nakp);
+			}
+			break;
+		
+		case CI_QUALITY:
+			GETSHORT(cishort, p);
+			GETLONG(cilong, p);
+#if TRACELCP > 0
+			snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " QUALITY (%x %x)", cishort, (unsigned int) cilong);
+			traceNdx = strlen(traceBuf);
+#endif
+
+			if (!ao->neg_lqr ||
+					cilen != CILEN_LQR) {
+				orc = CONFREJ;
+				break;
+			}
+			
+			/*
+			 * Check the protocol and the reporting period.
+			 * XXX When should we Nak this, and what with?
+			 */
+			if (cishort != PPP_LQR) {
+				orc = CONFNAK;
+				PUTCHAR(CI_QUALITY, nakp);
+				PUTCHAR(CILEN_LQR, nakp);
+				PUTSHORT(PPP_LQR, nakp);
+				PUTLONG(ao->lqr_period, nakp);
+				break;
+			}
+			break;
+		
+		case CI_MAGICNUMBER:
+			if (!(ao->neg_magicnumber || go->neg_magicnumber) ||
+					cilen != CILEN_LONG) {
+				orc = CONFREJ;
+				break;
+			}
+			GETLONG(cilong, p);
+#if TRACELCP > 0
+			snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " MAGICNUMBER (%lX)", cilong);
+			traceNdx = strlen(traceBuf);
+#endif
+
+			/*
+			 * He must have a different magic number.
+			 */
+			if (go->neg_magicnumber &&
+					cilong == go->magicnumber) {
+				cilong = magic();	/* Don't put magic() inside macro! */
+				orc = CONFNAK;
+				PUTCHAR(CI_MAGICNUMBER, nakp);
+				PUTCHAR(CILEN_LONG, nakp);
+				PUTLONG(cilong, nakp);
+				break;
+			}
+			ho->neg_magicnumber = 1;
+			ho->magicnumber = cilong;
+			break;
+		
+		
+		case CI_PCOMPRESSION:
+#if TRACELCP > 0
+			snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " PCOMPRESSION");
+			traceNdx = strlen(traceBuf);
+#endif
+			if (!ao->neg_pcompression ||
+					cilen != CILEN_VOID) {
+				orc = CONFREJ;
+				break;
+			}
+			ho->neg_pcompression = 1;
+			break;
+		
+		case CI_ACCOMPRESSION:
+#if TRACELCP > 0
+			snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " ACCOMPRESSION");
+			traceNdx = strlen(traceBuf);
+#endif
+			if (!ao->neg_accompression ||
+					cilen != CILEN_VOID) {
+				orc = CONFREJ;
+				break;
+			}
+			ho->neg_accompression = 1;
+			break;
+		
+		case CI_MRRU:
+#if TRACELCP > 0
+			snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CI_MRRU");
+			traceNdx = strlen(traceBuf);
+#endif
+			orc = CONFREJ;
+			break;
+		
+		case CI_SSNHF:
+#if TRACELCP > 0
+			snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CI_SSNHF");
+			traceNdx = strlen(traceBuf);
+#endif
+			orc = CONFREJ;
+			break;
+		
+		case CI_EPDISC:
+#if TRACELCP > 0
+			snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CI_EPDISC");
+			traceNdx = strlen(traceBuf);
+#endif
+			orc = CONFREJ;
+			break;
+		
+		default:
+#if TRACELCP
+			snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " unknown %d", citype);
+			traceNdx = strlen(traceBuf);
+#endif
+			orc = CONFREJ;
+			break;
+		}
+		
+	endswitch:
+#if TRACELCP
+		if (traceNdx >= 80 - 32) {
+			LCPDEBUG((LOG_INFO, "lcp_reqci: rcvd%s\n", traceBuf));
+			traceNdx = 0;
+		}
+#endif
+		if (orc == CONFACK &&		/* Good CI */
+				rc != CONFACK)		/*  but prior CI wasnt? */
+			continue;			/* Don't send this one */
+		
+		if (orc == CONFNAK) {		/* Nak this CI? */
+			if (reject_if_disagree	/* Getting fed up with sending NAKs? */
+					&& citype != CI_MAGICNUMBER) {
+				orc = CONFREJ;		/* Get tough if so */
+			} 
+			else {
+				if (rc == CONFREJ)	/* Rejecting prior CI? */
+					continue;		/* Don't send this one */
+				rc = CONFNAK;
+			}
+		}
+		if (orc == CONFREJ) {		/* Reject this CI */
+			rc = CONFREJ;
+			if (cip != rejp)		/* Need to move rejected CI? */
+				BCOPY(cip, rejp, cilen); /* Move it */
+			INCPTR(cilen, rejp);	/* Update output pointer */
+		}
+	}
+	
+	/*
+	 * If we wanted to send additional NAKs (for unsent CIs), the
+	 * code would go here.  The extra NAKs would go at *nakp.
+	 * At present there are no cases where we want to ask the
+	 * peer to negotiate an option.
+	 */
+	
+	switch (rc) {
+	case CONFACK:
+		*lenp = (int)(next - inp);
+		break;
+	case CONFNAK:
+		/*
+		 * Copy the Nak'd options from the nak_buffer to the caller's buffer.
+		 */
+		*lenp = (int)(nakp - nak_buffer);
+		BCOPY(nak_buffer, inp, *lenp);
+		break;
+	case CONFREJ:
+		*lenp = (int)(rejp - inp);
+		break;
+	}
+	
+#if TRACELCP > 0
+	if (traceNdx > 0) {
+		LCPDEBUG((LOG_INFO, "lcp_reqci: %s\n", traceBuf));
+	}
+#endif
+	LCPDEBUG((LOG_INFO, "lcp_reqci: returning CONF%s.\n", CODENAME(rc)));
+	return (rc);			/* Return final code */
+}
+
+
+/*
+ * lcp_up - LCP has come UP.
+ */
+static void lcp_up(fsm *f)
+{
+	lcp_options *wo = &lcp_wantoptions[f->unit];
+	lcp_options *ho = &lcp_hisoptions[f->unit];
+	lcp_options *go = &lcp_gotoptions[f->unit];
+	lcp_options *ao = &lcp_allowoptions[f->unit];
+	
+	if (!go->neg_magicnumber)
+		go->magicnumber = 0;
+	if (!ho->neg_magicnumber)
+		ho->magicnumber = 0;
+	
+	/*
+	* Set our MTU to the smaller of the MTU we wanted and
+	* the MRU our peer wanted.  If we negotiated an MRU,
+	* set our MRU to the larger of value we wanted and
+	* the value we got in the negotiation.
+	*/
+	ppp_send_config(f->unit, LWIP_MIN(ao->mru, (ho->neg_mru? ho->mru: PPP_MRU)),
+				(ho->neg_asyncmap? ho->asyncmap: 0xffffffffl),
+				ho->neg_pcompression, ho->neg_accompression);
+	/*
+	* If the asyncmap hasn't been negotiated, we really should
+	* set the receive asyncmap to ffffffff, but we set it to 0
+	* for backwards contemptibility.
+	*/
+	ppp_recv_config(f->unit, (go->neg_mru? LWIP_MAX(wo->mru, go->mru): PPP_MRU),
+				(go->neg_asyncmap? go->asyncmap: 0x00000000),
+				go->neg_pcompression, go->neg_accompression);
+	
+	if (ho->neg_mru)
+		peer_mru[f->unit] = ho->mru;
+	
+	lcp_echo_lowerup(f->unit);  /* Enable echo messages */
+	
+	link_established(f->unit);
+}
+
+
+/*
+ * lcp_down - LCP has gone DOWN.
+ *
+ * Alert other protocols.
+ */
+static void lcp_down(fsm *f)
+{
+	lcp_options *go = &lcp_gotoptions[f->unit];
+	
+	lcp_echo_lowerdown(f->unit);
+	
+	link_down(f->unit);
+	
+	ppp_send_config(f->unit, PPP_MRU, 0xffffffffl, 0, 0);
+	ppp_recv_config(f->unit, PPP_MRU,
+				(go->neg_asyncmap? go->asyncmap: 0x00000000),
+				go->neg_pcompression, go->neg_accompression);
+	peer_mru[f->unit] = PPP_MRU;
+}
+
+
+/*
+ * lcp_starting - LCP needs the lower layer up.
+ */
+static void lcp_starting(fsm *f)
+{
+	link_required(f->unit);
+}
+
+
+/*
+ * lcp_finished - LCP has finished with the lower layer.
+ */
+static void lcp_finished(fsm *f)
+{
+	link_terminated(f->unit);
+}
+
+
+#if 0
+/*
+ * print_string - print a readable representation of a string using
+ * printer.
+ */
+static void print_string(
+    char *p,
+    int len,
+    void (*printer) (void *, char *, ...),
+    void *arg
+)
+{
+    int c;
+    
+    printer(arg, "\"");
+    for (; len > 0; --len) {
+        c = *p++;
+        if (' ' <= c && c <= '~') {
+            if (c == '\\' || c == '"')
+                printer(arg, "\\");
+            printer(arg, "%c", c);
+        } else {
+            switch (c) {
+            case '\n':
+                printer(arg, "\\n");
+                break;
+            case '\r':
+                printer(arg, "\\r");
+                break;
+            case '\t':
+                printer(arg, "\\t");
+                break;
+            default:
+                printer(arg, "\\%.3o", c);
+            }
+        }
+    }
+    printer(arg, "\"");
+}
+
+
+/*
+ * lcp_printpkt - print the contents of an LCP packet.
+ */
+static char *lcp_codenames[] = {
+	"ConfReq", "ConfAck", "ConfNak", "ConfRej",
+	"TermReq", "TermAck", "CodeRej", "ProtRej",
+	"EchoReq", "EchoRep", "DiscReq"
+};
+
+static int lcp_printpkt(
+	u_char *p,
+	int plen,
+	void (*printer) (void *, char *, ...),
+	void *arg
+)
+{
+	int code, id, len, olen;
+	u_char *pstart, *optend;
+	u_short cishort;
+	u32_t cilong;
+	
+	if (plen < HEADERLEN)
+		return 0;
+	pstart = p;
+	GETCHAR(code, p);
+	GETCHAR(id, p);
+	GETSHORT(len, p);
+	if (len < HEADERLEN || len > plen)
+		return 0;
+	
+	if (code >= 1 && code <= sizeof(lcp_codenames) / sizeof(char *))
+		printer(arg, " %s", lcp_codenames[code-1]);
+	else
+		printer(arg, " code=0x%x", code);
+	printer(arg, " id=0x%x", id);
+	len -= HEADERLEN;
+	switch (code) {
+	case CONFREQ:
+	case CONFACK:
+	case CONFNAK:
+	case CONFREJ:
+		/* print option list */
+		while (len >= 2) {
+			GETCHAR(code, p);
+			GETCHAR(olen, p);
+			p -= 2;
+			if (olen < 2 || olen > len) {
+				break;
+			}
+			printer(arg, " <");
+			len -= olen;
+			optend = p + olen;
+			switch (code) {
+			case CI_MRU:
+				if (olen == CILEN_SHORT) {
+					p += 2;
+					GETSHORT(cishort, p);
+					printer(arg, "mru %d", cishort);
+				}
+				break;
+			case CI_ASYNCMAP:
+				if (olen == CILEN_LONG) {
+					p += 2;
+					GETLONG(cilong, p);
+					printer(arg, "asyncmap 0x%lx", cilong);
+				}
+				break;
+			case CI_AUTHTYPE:
+				if (olen >= CILEN_SHORT) {
+					p += 2;
+					printer(arg, "auth ");
+					GETSHORT(cishort, p);
+					switch (cishort) {
+					case PPP_PAP:
+						printer(arg, "pap");
+						break;
+					case PPP_CHAP:
+						printer(arg, "chap");
+						break;
+					default:
+						printer(arg, "0x%x", cishort);
+					}
+				}
+				break;
+			case CI_QUALITY:
+				if (olen >= CILEN_SHORT) {
+					p += 2;
+					printer(arg, "quality ");
+					GETSHORT(cishort, p);
+					switch (cishort) {
+					case PPP_LQR:
+						printer(arg, "lqr");
+						break;
+					default:
+						printer(arg, "0x%x", cishort);
+					}
+				}
+				break;
+			case CI_CALLBACK:
+				if (olen >= CILEN_CHAR) {
+					p += 2;
+					printer(arg, "callback ");
+					GETSHORT(cishort, p);
+					switch (cishort) {
+					case CBCP_OPT:
+						printer(arg, "CBCP");
+						break;
+					default:
+						printer(arg, "0x%x", cishort);
+					}
+				}
+				break;
+			case CI_MAGICNUMBER:
+				if (olen == CILEN_LONG) {
+					p += 2;
+					GETLONG(cilong, p);
+					printer(arg, "magic 0x%x", cilong);
+				}
+				break;
+			case CI_PCOMPRESSION:
+				if (olen == CILEN_VOID) {
+					p += 2;
+					printer(arg, "pcomp");
+				}
+				break;
+			case CI_ACCOMPRESSION:
+				if (olen == CILEN_VOID) {
+					p += 2;
+					printer(arg, "accomp");
+				}
+				break;
+			}
+			while (p < optend) {
+				GETCHAR(code, p);
+				printer(arg, " %.2x", code);
+			}
+			printer(arg, ">");
+		}
+		break;
+	
+	case TERMACK:
+	case TERMREQ:
+		if (len > 0 && *p >= ' ' && *p < 0x7f) {
+			printer(arg, " ");
+			print_string((char*)p, len, printer, arg);
+			p += len;
+			len = 0;
+		}
+		break;
+	
+	case ECHOREQ:
+	case ECHOREP:
+	case DISCREQ:
+		if (len >= 4) {
+			GETLONG(cilong, p);
+			printer(arg, " magic=0x%x", cilong);
+			p += 4;
+			len -= 4;
+		}
+		break;
+	}
+	
+	/* print the rest of the bytes in the packet */
+	for (; len > 0; --len) {
+		GETCHAR(code, p);
+		printer(arg, " %.2x", code);
+	}
+	
+	return (int)(p - pstart);
+}
+#endif
+
+/*
+ * Time to shut down the link because there is nothing out there.
+ */
+
+static void LcpLinkFailure (fsm *f)
+{
+	if (f->state == OPENED) {
+		LCPDEBUG((LOG_INFO, "No response to %d echo-requests\n", lcp_echos_pending));
+		LCPDEBUG((LOG_NOTICE, "Serial link appears to be disconnected.\n"));
+		lcp_close(f->unit, "Peer not responding");
+	}
+}
+
+/*
+ * Timer expired for the LCP echo requests from this process.
+ */
+
+static void LcpEchoCheck (fsm *f)
+{
+	LcpSendEchoRequest (f);
+	
+	/*
+	 * Start the timer for the next interval.
+	 */
+	LWIP_ASSERT("lcp_echo_timer_running == 0", lcp_echo_timer_running == 0);
+
+	TIMEOUT (LcpEchoTimeout, f, lcp_echo_interval);
+	lcp_echo_timer_running = 1;
+}
+
+/*
+ * LcpEchoTimeout - Timer expired on the LCP echo
+ */
+
+static void LcpEchoTimeout (void *arg)
+{
+	if (lcp_echo_timer_running != 0) {
+		lcp_echo_timer_running = 0;
+		LcpEchoCheck ((fsm *) arg);
+	}
+}
+
+/*
+ * LcpEchoReply - LCP has received a reply to the echo
+ */
+static void lcp_received_echo_reply (fsm *f, int id, u_char *inp, int len)
+{
+	u32_t magic;
+	
+	(void)id;
+
+	/* Check the magic number - don't count replies from ourselves. */
+	if (len < 4) {
+		LCPDEBUG((LOG_WARNING, "lcp: received short Echo-Reply, length %d\n", len));
+		return;
+	}
+	GETLONG(magic, inp);
+	if (lcp_gotoptions[f->unit].neg_magicnumber
+			&& magic == lcp_gotoptions[f->unit].magicnumber) {
+		LCPDEBUG((LOG_WARNING, "appear to have received our own echo-reply!\n"));
+		return;
+	}
+	
+	/* Reset the number of outstanding echo frames */
+	lcp_echos_pending = 0;
+}
+
+/*
+ * LcpSendEchoRequest - Send an echo request frame to the peer
+ */
+
+static void LcpSendEchoRequest (fsm *f)
+{
+	u32_t lcp_magic;
+	u_char pkt[4], *pktp;
+	
+	/*
+	* Detect the failure of the peer at this point.
+	*/
+	if (lcp_echo_fails != 0) {
+		if (lcp_echos_pending++ >= lcp_echo_fails) {
+			LcpLinkFailure(f);
+			lcp_echos_pending = 0;
+		}
+	}
+	
+	/*
+	* Make and send the echo request frame.
+	*/
+	if (f->state == OPENED) {
+		lcp_magic = lcp_gotoptions[f->unit].magicnumber;
+		pktp = pkt;
+		PUTLONG(lcp_magic, pktp);
+		fsm_sdata(f, ECHOREQ, (u_char)(lcp_echo_number++ & 0xFF), pkt, (int)(pktp - pkt));
+	}
+}
+
+/*
+ * lcp_echo_lowerup - Start the timer for the LCP frame
+ */
+
+static void lcp_echo_lowerup (int unit)
+{
+	fsm *f = &lcp_fsm[unit];
+	
+	/* Clear the parameters for generating echo frames */
+	lcp_echos_pending      = 0;
+	lcp_echo_number        = 0;
+	lcp_echo_timer_running = 0;
+	
+	/* If a timeout interval is specified then start the timer */
+	if (lcp_echo_interval != 0)
+		LcpEchoCheck (f);
+}
+
+/*
+ * lcp_echo_lowerdown - Stop the timer for the LCP frame
+ */
+
+static void lcp_echo_lowerdown (int unit)
+{
+	fsm *f = &lcp_fsm[unit];
+	
+	if (lcp_echo_timer_running != 0) {
+		UNTIMEOUT (LcpEchoTimeout, f);
+		lcp_echo_timer_running = 0;
+	}
+}
+
+#endif /* PPP_SUPPORT */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/lcp.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/lcp.h
new file mode 100644
index 000000000..a8877086e
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/lcp.h
@@ -0,0 +1,169 @@
+/*****************************************************************************
+* lcp.h - Network Link Control Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-11-05 Guy Lancaster , Global Election Systems Inc.
+*	Original derived from BSD codes.
+*****************************************************************************/
+/*
+ * lcp.h - Link Control Protocol definitions.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * $Id: lcp.h,v 1.2 2006/08/29 18:53:47 wolti Exp $
+ */
+
+#ifndef LCP_H
+#define LCP_H
+
+
+/*************************
+*** PUBLIC DEFINITIONS ***
+*************************/
+/*
+ * Options.
+ */
+#define CI_MRU		1	/* Maximum Receive Unit */
+#define CI_ASYNCMAP	2	/* Async Control Character Map */
+#define CI_AUTHTYPE	3	/* Authentication Type */
+#define CI_QUALITY	4	/* Quality Protocol */
+#define CI_MAGICNUMBER	5	/* Magic Number */
+#define CI_PCOMPRESSION	7	/* Protocol Field Compression */
+#define CI_ACCOMPRESSION 8	/* Address/Control Field Compression */
+#define CI_CALLBACK	13	/* callback */
+#define CI_MRRU		17	/* max reconstructed receive unit; multilink */
+#define CI_SSNHF	18	/* short sequence numbers for multilink */
+#define CI_EPDISC	19	/* endpoint discriminator */
+
+/*
+ * LCP-specific packet types.
+ */
+#define PROTREJ		8	/* Protocol Reject */
+#define ECHOREQ		9	/* Echo Request */
+#define ECHOREP		10	/* Echo Reply */
+#define DISCREQ		11	/* Discard Request */
+#define CBCP_OPT	6	/* Use callback control protocol */
+
+
+/************************
+*** PUBLIC DATA TYPES ***
+************************/
+
+/*
+ * The state of options is described by an lcp_options structure.
+ */
+typedef struct lcp_options {
+    u_int passive : 1;			/* Don't die if we don't get a response */
+    u_int silent : 1;				/* Wait for the other end to start first */
+    u_int restart : 1;			/* Restart vs. exit after close */
+    u_int neg_mru : 1;			/* Negotiate the MRU? */
+    u_int neg_asyncmap : 1;		/* Negotiate the async map? */
+    u_int neg_upap : 1;			/* Ask for UPAP authentication? */
+    u_int neg_chap : 1;			/* Ask for CHAP authentication? */
+    u_int neg_magicnumber : 1;	/* Ask for magic number? */
+    u_int neg_pcompression : 1;	/* HDLC Protocol Field Compression? */
+    u_int neg_accompression : 1;	/* HDLC Address/Control Field Compression? */
+    u_int neg_lqr : 1;			/* Negotiate use of Link Quality Reports */
+    u_int neg_cbcp : 1;			/* Negotiate use of CBCP */
+#ifdef PPP_MULTILINK
+    u_int neg_mrru : 1;			/* Negotiate multilink MRRU */
+    u_int neg_ssnhf : 1;		/* Negotiate short sequence numbers */
+    u_int neg_endpoint : 1;		/* Negotiate endpoint discriminator */
+#endif
+    u_short mru;			/* Value of MRU */
+#ifdef PPP_MULTILINK
+    u_short mrru;			/* Value of MRRU, and multilink enable */
+#endif
+    u_char chap_mdtype;			/* which MD type (hashing algorithm) */
+    u32_t asyncmap;			/* Value of async map */
+    u32_t magicnumber;
+    int numloops;				/* Number of loops during magic number neg. */
+    u32_t lqr_period;		/* Reporting period for LQR 1/100ths second */
+#ifdef PPP_MULTILINK
+    struct epdisc endpoint;	/* endpoint discriminator */
+#endif
+} lcp_options;
+
+/*
+ * Values for phase from BSD pppd.h based on RFC 1661.
+ */
+typedef enum {
+	PHASE_DEAD = 0,
+	PHASE_INITIALIZE,
+	PHASE_ESTABLISH,
+	PHASE_AUTHENTICATE,
+	PHASE_CALLBACK,
+	PHASE_NETWORK,
+	PHASE_TERMINATE
+} LinkPhase;
+
+
+/*****************************
+*** PUBLIC DATA STRUCTURES ***
+*****************************/
+
+extern LinkPhase lcp_phase[NUM_PPP];	/* Phase of link session (RFC 1661) */
+extern lcp_options lcp_wantoptions[];
+extern lcp_options lcp_gotoptions[];
+extern lcp_options lcp_allowoptions[];
+extern lcp_options lcp_hisoptions[];
+extern ext_accm xmit_accm[];
+
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+
+void lcp_init (int);
+void lcp_open (int);
+void lcp_close (int, char *);
+void lcp_lowerup (int);
+void lcp_lowerdown (int);
+void lcp_sprotrej (int, u_char *, int);	/* send protocol reject */
+
+extern struct protent lcp_protent;
+
+/* Default number of times we receive our magic number from the peer
+   before deciding the link is looped-back. */
+#define DEFLOOPBACKFAIL	10
+
+#endif /* LCP_H */
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/magic.c b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/magic.c
new file mode 100644
index 000000000..6e9d47538
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/magic.c
@@ -0,0 +1,79 @@
+/*****************************************************************************
+* magic.c - Network Random Number Generator program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-04 Guy Lancaster , Global Election Systems Inc.
+*	Original based on BSD magic.c.
+*****************************************************************************/
+/*
+ * magic.c - PPP Magic Number routines.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include "ppp.h"
+#include "randm.h"
+#include "magic.h"
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ * magicInit - Initialize the magic number generator.
+ *
+ * Since we use another random number generator that has its own
+ * initialization, we do nothing here.
+ */
+void magicInit()
+{
+	return;
+}
+
+/*
+ * magic - Returns the next magic number.
+ */
+u32_t magic()
+{
+    return avRandom();
+}
+
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/magic.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/magic.h
new file mode 100644
index 000000000..067235eae
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/magic.h
@@ -0,0 +1,64 @@
+/*****************************************************************************
+* magic.h - Network Random Number Generator header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-04 Guy Lancaster , Global Election Systems Inc.
+*   Original derived from BSD codes.
+*****************************************************************************/
+/*
+ * magic.h - PPP Magic Number definitions.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * $Id: magic.h,v 1.2 2006/08/29 18:53:47 wolti Exp $
+ */
+
+#ifndef MAGIC_H
+#define MAGIC_H
+
+/*****************************************************************************
+************************** PUBLIC FUNCTIONS **********************************
+*****************************************************************************/
+
+void magicInit(void);   /* Initialize the magic number generator */
+u32_t magic(void);  /* Returns the next magic number */
+
+#endif /* MAGIC_H */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/md5.c b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/md5.c
new file mode 100644
index 000000000..488d64af5
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/md5.c
@@ -0,0 +1,306 @@
+/*
+ ***********************************************************************
+ ** md5.c -- the source code for MD5 routines                         **
+ ** RSA Data Security, Inc. MD5 Message-Digest Algorithm              **
+ ** Created: 2/17/90 RLR                                              **
+ ** Revised: 1/91 SRD,AJ,BSK,JT Reference C ver., 7/10 constant corr. **
+ ***********************************************************************
+ */
+
+/*
+ ***********************************************************************
+ ** Copyright (C) 1990, RSA Data Security, Inc. All rights reserved.  **
+ **                                                                   **
+ ** License to copy and use this software is granted provided that    **
+ ** it is identified as the "RSA Data Security, Inc. MD5 Message-     **
+ ** Digest Algorithm" in all material mentioning or referencing this  **
+ ** software or this function.                                        **
+ **                                                                   **
+ ** License is also granted to make and use derivative works          **
+ ** provided that such works are identified as "derived from the RSA  **
+ ** Data Security, Inc. MD5 Message-Digest Algorithm" in all          **
+ ** material mentioning or referencing the derived work.              **
+ **                                                                   **
+ ** RSA Data Security, Inc. makes no representations concerning       **
+ ** either the merchantability of this software or the suitability    **
+ ** of this software for any particular purpose.  It is provided "as  **
+ ** is" without express or implied warranty of any kind.              **
+ **                                                                   **
+ ** These notices must be retained in any copies of any part of this  **
+ ** documentation and/or software.                                    **
+ ***********************************************************************
+ */
+
+#include "ppp.h"
+#include "md5.h"
+#include "pppdebug.h"
+
+#if CHAP_SUPPORT > 0 || MD5_SUPPORT > 0
+
+/*
+ ***********************************************************************
+ **  Message-digest routines:                                         **
+ **  To form the message digest for a message M                       **
+ **    (1) Initialize a context buffer mdContext using MD5Init        **
+ **    (2) Call MD5Update on mdContext and M                          **
+ **    (3) Call MD5Final on mdContext                                 **
+ **  The message digest is now in mdContext->digest[0...15]           **
+ ***********************************************************************
+ */
+
+/* forward declaration */
+static void Transform (u32_t *buf, u32_t *in);
+
+static unsigned char PADDING[64] = {
+  0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+/* F, G, H and I are basic MD5 functions */
+#define F(x, y, z) (((x) & (y)) | ((~x) & (z)))
+#define G(x, y, z) (((x) & (z)) | ((y) & (~z)))
+#define H(x, y, z) ((x) ^ (y) ^ (z))
+#define I(x, y, z) ((y) ^ ((x) | (~z)))
+
+/* ROTATE_LEFT rotates x left n bits */
+#define ROTATE_LEFT(x, n) (((x) << (n)) | ((x) >> (32-(n))))
+
+/* FF, GG, HH, and II transformations for rounds 1, 2, 3, and 4 */
+/* Rotation is separate from addition to prevent recomputation */
+#define FF(a, b, c, d, x, s, ac) \
+  {(a) += F ((b), (c), (d)) + (x) + (u32_t)(ac); \
+   (a) = ROTATE_LEFT ((a), (s)); \
+   (a) += (b); \
+  }
+#define GG(a, b, c, d, x, s, ac) \
+  {(a) += G ((b), (c), (d)) + (x) + (u32_t)(ac); \
+   (a) = ROTATE_LEFT ((a), (s)); \
+   (a) += (b); \
+  }
+#define HH(a, b, c, d, x, s, ac) \
+  {(a) += H ((b), (c), (d)) + (x) + (u32_t)(ac); \
+   (a) = ROTATE_LEFT ((a), (s)); \
+   (a) += (b); \
+  }
+#define II(a, b, c, d, x, s, ac) \
+  {(a) += I ((b), (c), (d)) + (x) + (u32_t)(ac); \
+   (a) = ROTATE_LEFT ((a), (s)); \
+   (a) += (b); \
+  }
+
+#ifdef __STDC__
+#define UL(x)	x##UL
+#else
+#ifdef WIN32
+#define UL(x)	x##UL
+#else
+#define UL(x)	x
+#endif
+#endif
+
+/* The routine MD5Init initializes the message-digest context
+   mdContext. All fields are set to zero.
+ */
+void MD5Init (MD5_CTX *mdContext)
+{
+  mdContext->i[0] = mdContext->i[1] = (u32_t)0;
+
+  /* Load magic initialization constants.
+   */
+  mdContext->buf[0] = (u32_t)0x67452301UL;
+  mdContext->buf[1] = (u32_t)0xefcdab89UL;
+  mdContext->buf[2] = (u32_t)0x98badcfeUL;
+  mdContext->buf[3] = (u32_t)0x10325476UL;
+}
+
+/* The routine MD5Update updates the message-digest context to
+   account for the presence of each of the characters inBuf[0..inLen-1]
+   in the message whose digest is being computed.
+ */
+void MD5Update(MD5_CTX *mdContext, unsigned char *inBuf, unsigned int inLen)
+{
+  u32_t in[16];
+  int mdi;
+  unsigned int i, ii;
+
+#if 0
+  ppp_trace(LOG_INFO, "MD5Update: %u:%.*H\n", inLen, MIN(inLen, 20) * 2, inBuf);
+  ppp_trace(LOG_INFO, "MD5Update: %u:%s\n", inLen, inBuf);
+#endif
+  
+  /* compute number of bytes mod 64 */
+  mdi = (int)((mdContext->i[0] >> 3) & 0x3F);
+
+  /* update number of bits */
+  if ((mdContext->i[0] + ((u32_t)inLen << 3)) < mdContext->i[0])
+    mdContext->i[1]++;
+  mdContext->i[0] += ((u32_t)inLen << 3);
+  mdContext->i[1] += ((u32_t)inLen >> 29);
+
+  while (inLen--) {
+    /* add new character to buffer, increment mdi */
+    mdContext->in[mdi++] = *inBuf++;
+
+    /* transform if necessary */
+    if (mdi == 0x40) {
+      for (i = 0, ii = 0; i < 16; i++, ii += 4)
+        in[i] = (((u32_t)mdContext->in[ii+3]) << 24) |
+                (((u32_t)mdContext->in[ii+2]) << 16) |
+				(((u32_t)mdContext->in[ii+1]) << 8) |
+                ((u32_t)mdContext->in[ii]);
+      Transform (mdContext->buf, in);
+      mdi = 0;
+    }
+  }
+}
+
+/* The routine MD5Final terminates the message-digest computation and
+   ends with the desired message digest in mdContext->digest[0...15].
+ */
+void MD5Final (unsigned char hash[], MD5_CTX *mdContext)
+{
+  u32_t in[16];
+  int mdi;
+  unsigned int i, ii;
+  unsigned int padLen;
+
+  /* save number of bits */
+  in[14] = mdContext->i[0];
+  in[15] = mdContext->i[1];
+
+  /* compute number of bytes mod 64 */
+  mdi = (int)((mdContext->i[0] >> 3) & 0x3F);
+
+  /* pad out to 56 mod 64 */
+  padLen = (mdi < 56) ? (56 - mdi) : (120 - mdi);
+  MD5Update (mdContext, PADDING, padLen);
+
+  /* append length in bits and transform */
+  for (i = 0, ii = 0; i < 14; i++, ii += 4)
+    in[i] = (((u32_t)mdContext->in[ii+3]) << 24) |
+            (((u32_t)mdContext->in[ii+2]) << 16) |
+            (((u32_t)mdContext->in[ii+1]) << 8) |
+            ((u32_t)mdContext->in[ii]);
+  Transform (mdContext->buf, in);
+
+  /* store buffer in digest */
+  for (i = 0, ii = 0; i < 4; i++, ii += 4) {
+    mdContext->digest[ii] = (unsigned char)(mdContext->buf[i] & 0xFF);
+	mdContext->digest[ii+1] =
+      (unsigned char)((mdContext->buf[i] >> 8) & 0xFF);
+    mdContext->digest[ii+2] =
+      (unsigned char)((mdContext->buf[i] >> 16) & 0xFF);
+    mdContext->digest[ii+3] =
+      (unsigned char)((mdContext->buf[i] >> 24) & 0xFF);
+  }
+  memcpy(hash, mdContext->digest, 16);
+}
+
+/* Basic MD5 step. Transforms buf based on in.
+ */
+static void Transform (u32_t *buf, u32_t *in)
+{
+  u32_t a = buf[0], b = buf[1], c = buf[2], d = buf[3];
+
+  /* Round 1 */
+#define S11 7
+#define S12 12
+#define S13 17
+#define S14 22
+  FF ( a, b, c, d, in[ 0], S11, UL(3614090360)); /* 1 */
+  FF ( d, a, b, c, in[ 1], S12, UL(3905402710)); /* 2 */
+  FF ( c, d, a, b, in[ 2], S13, UL( 606105819)); /* 3 */
+  FF ( b, c, d, a, in[ 3], S14, UL(3250441966)); /* 4 */
+  FF ( a, b, c, d, in[ 4], S11, UL(4118548399)); /* 5 */
+  FF ( d, a, b, c, in[ 5], S12, UL(1200080426)); /* 6 */
+  FF ( c, d, a, b, in[ 6], S13, UL(2821735955)); /* 7 */
+  FF ( b, c, d, a, in[ 7], S14, UL(4249261313)); /* 8 */
+  FF ( a, b, c, d, in[ 8], S11, UL(1770035416)); /* 9 */
+  FF ( d, a, b, c, in[ 9], S12, UL(2336552879)); /* 10 */
+  FF ( c, d, a, b, in[10], S13, UL(4294925233)); /* 11 */
+  FF ( b, c, d, a, in[11], S14, UL(2304563134)); /* 12 */
+  FF ( a, b, c, d, in[12], S11, UL(1804603682)); /* 13 */
+  FF ( d, a, b, c, in[13], S12, UL(4254626195)); /* 14 */
+  FF ( c, d, a, b, in[14], S13, UL(2792965006)); /* 15 */
+  FF ( b, c, d, a, in[15], S14, UL(1236535329)); /* 16 */
+
+  /* Round 2 */
+#define S21 5
+#define S22 9
+#define S23 14
+#define S24 20
+  GG ( a, b, c, d, in[ 1], S21, UL(4129170786)); /* 17 */
+  GG ( d, a, b, c, in[ 6], S22, UL(3225465664)); /* 18 */
+  GG ( c, d, a, b, in[11], S23, UL( 643717713)); /* 19 */
+  GG ( b, c, d, a, in[ 0], S24, UL(3921069994)); /* 20 */
+  GG ( a, b, c, d, in[ 5], S21, UL(3593408605)); /* 21 */
+  GG ( d, a, b, c, in[10], S22, UL(  38016083)); /* 22 */
+  GG ( c, d, a, b, in[15], S23, UL(3634488961)); /* 23 */
+  GG ( b, c, d, a, in[ 4], S24, UL(3889429448)); /* 24 */
+  GG ( a, b, c, d, in[ 9], S21, UL( 568446438)); /* 25 */
+  GG ( d, a, b, c, in[14], S22, UL(3275163606)); /* 26 */
+  GG ( c, d, a, b, in[ 3], S23, UL(4107603335)); /* 27 */
+  GG ( b, c, d, a, in[ 8], S24, UL(1163531501)); /* 28 */
+  GG ( a, b, c, d, in[13], S21, UL(2850285829)); /* 29 */
+  GG ( d, a, b, c, in[ 2], S22, UL(4243563512)); /* 30 */
+  GG ( c, d, a, b, in[ 7], S23, UL(1735328473)); /* 31 */
+  GG ( b, c, d, a, in[12], S24, UL(2368359562)); /* 32 */
+
+  /* Round 3 */
+#define S31 4
+#define S32 11
+#define S33 16
+#define S34 23
+  HH ( a, b, c, d, in[ 5], S31, UL(4294588738)); /* 33 */
+  HH ( d, a, b, c, in[ 8], S32, UL(2272392833)); /* 34 */
+  HH ( c, d, a, b, in[11], S33, UL(1839030562)); /* 35 */
+  HH ( b, c, d, a, in[14], S34, UL(4259657740)); /* 36 */
+  HH ( a, b, c, d, in[ 1], S31, UL(2763975236)); /* 37 */
+  HH ( d, a, b, c, in[ 4], S32, UL(1272893353)); /* 38 */
+  HH ( c, d, a, b, in[ 7], S33, UL(4139469664)); /* 39 */
+  HH ( b, c, d, a, in[10], S34, UL(3200236656)); /* 40 */
+  HH ( a, b, c, d, in[13], S31, UL( 681279174)); /* 41 */
+  HH ( d, a, b, c, in[ 0], S32, UL(3936430074)); /* 42 */
+  HH ( c, d, a, b, in[ 3], S33, UL(3572445317)); /* 43 */
+  HH ( b, c, d, a, in[ 6], S34, UL(  76029189)); /* 44 */
+  HH ( a, b, c, d, in[ 9], S31, UL(3654602809)); /* 45 */
+  HH ( d, a, b, c, in[12], S32, UL(3873151461)); /* 46 */
+  HH ( c, d, a, b, in[15], S33, UL( 530742520)); /* 47 */
+  HH ( b, c, d, a, in[ 2], S34, UL(3299628645)); /* 48 */
+
+  /* Round 4 */
+#define S41 6
+#define S42 10
+#define S43 15
+#define S44 21
+  II ( a, b, c, d, in[ 0], S41, UL(4096336452)); /* 49 */
+  II ( d, a, b, c, in[ 7], S42, UL(1126891415)); /* 50 */
+  II ( c, d, a, b, in[14], S43, UL(2878612391)); /* 51 */
+  II ( b, c, d, a, in[ 5], S44, UL(4237533241)); /* 52 */
+  II ( a, b, c, d, in[12], S41, UL(1700485571)); /* 53 */
+  II ( d, a, b, c, in[ 3], S42, UL(2399980690)); /* 54 */
+  II ( c, d, a, b, in[10], S43, UL(4293915773)); /* 55 */
+  II ( b, c, d, a, in[ 1], S44, UL(2240044497)); /* 56 */
+  II ( a, b, c, d, in[ 8], S41, UL(1873313359)); /* 57 */
+  II ( d, a, b, c, in[15], S42, UL(4264355552)); /* 58 */
+  II ( c, d, a, b, in[ 6], S43, UL(2734768916)); /* 59 */
+  II ( b, c, d, a, in[13], S44, UL(1309151649)); /* 60 */
+  II ( a, b, c, d, in[ 4], S41, UL(4149444226)); /* 61 */
+  II ( d, a, b, c, in[11], S42, UL(3174756917)); /* 62 */
+  II ( c, d, a, b, in[ 2], S43, UL( 718787259)); /* 63 */
+  II ( b, c, d, a, in[ 9], S44, UL(3951481745)); /* 64 */
+
+  buf[0] += a;
+  buf[1] += b;
+  buf[2] += c;
+  buf[3] += d;
+}
+
+#endif
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/md5.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/md5.h
new file mode 100644
index 000000000..83d318cfb
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/md5.h
@@ -0,0 +1,55 @@
+/*
+ ***********************************************************************
+ ** md5.h -- header file for implementation of MD5                    **
+ ** RSA Data Security, Inc. MD5 Message-Digest Algorithm              **
+ ** Created: 2/17/90 RLR                                              **
+ ** Revised: 12/27/90 SRD,AJ,BSK,JT Reference C version               **
+ ** Revised (for MD5): RLR 4/27/91                                    **
+ **   -- G modified to have y&~z instead of y&z                       **
+ **   -- FF, GG, HH modified to add in last register done             **
+ **   -- Access pattern: round 2 works mod 5, round 3 works mod 3     **
+ **   -- distinct additive constant for each step                     **
+ **   -- round 4 added, working mod 7                                 **
+ ***********************************************************************
+ */
+
+/*
+ ***********************************************************************
+ ** Copyright (C) 1990, RSA Data Security, Inc. All rights reserved.  **
+ **                                                                   **
+ ** License to copy and use this software is granted provided that    **
+ ** it is identified as the "RSA Data Security, Inc. MD5 Message-     **
+ ** Digest Algorithm" in all material mentioning or referencing this  **
+ ** software or this function.                                        **
+ **                                                                   **
+ ** License is also granted to make and use derivative works          **
+ ** provided that such works are identified as "derived from the RSA  **
+ ** Data Security, Inc. MD5 Message-Digest Algorithm" in all          **
+ ** material mentioning or referencing the derived work.              **
+ **                                                                   **
+ ** RSA Data Security, Inc. makes no representations concerning       **
+ ** either the merchantability of this software or the suitability    **
+ ** of this software for any particular purpose.  It is provided "as  **
+ ** is" without express or implied warranty of any kind.              **
+ **                                                                   **
+ ** These notices must be retained in any copies of any part of this  **
+ ** documentation and/or software.                                    **
+ ***********************************************************************
+ */
+
+#ifndef MD5_H
+#define MD5_H
+
+/* Data structure for MD5 (Message-Digest) computation */
+typedef struct {
+  u32_t i[2];                   /* number of _bits_ handled mod 2^64 */
+  u32_t buf[4];                                    /* scratch buffer */
+  unsigned char in[64];                              /* input buffer */
+  unsigned char digest[16];     /* actual digest after MD5Final call */
+} MD5_CTX;
+
+void MD5Init (MD5_CTX *mdContext);
+void MD5Update (MD5_CTX *mdContext, unsigned char *inBuf, unsigned int inLen);
+void MD5Final (unsigned char hash[], MD5_CTX *mdContext);
+
+#endif /* MD5_H */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/pap.c b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/pap.c
new file mode 100644
index 000000000..4b105ef3e
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/pap.c
@@ -0,0 +1,608 @@
+/*****************************************************************************
+* pap.c - Network Password Authentication Protocol program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-12 Guy Lancaster , Global Election Systems Inc.
+*	Original.
+*****************************************************************************/
+/*
+ * upap.c - User/Password Authentication Protocol.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include "ppp.h"
+#include "auth.h"
+#include "pap.h"
+#include "pppdebug.h"
+
+
+#if PAP_SUPPORT > 0
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+/*
+ * Protocol entry points.
+ */
+static void upap_init (int);
+static void upap_lowerup (int);
+static void upap_lowerdown (int);
+static void upap_input (int, u_char *, int);
+static void upap_protrej (int);
+
+static void upap_timeout (void *);
+static void upap_reqtimeout (void *);
+static void upap_rauthreq (upap_state *, u_char *, int, int);
+static void upap_rauthack (upap_state *, u_char *, int, int);
+static void upap_rauthnak (upap_state *, u_char *, int, int);
+static void upap_sauthreq (upap_state *);
+static void upap_sresp (upap_state *, u_char, u_char, char *, int);
+
+
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+struct protent pap_protent = {
+    PPP_PAP,
+    upap_init,
+    upap_input,
+    upap_protrej,
+    upap_lowerup,
+    upap_lowerdown,
+    NULL,
+    NULL,
+#if 0
+    upap_printpkt,
+    NULL,
+#endif
+    1,
+    "PAP",
+#if 0
+    NULL,
+    NULL,
+    NULL
+#endif
+};
+
+upap_state upap[NUM_PPP];		/* UPAP state; one for each unit */
+
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ *  Set the default login name and password for the pap sessions
+ */
+void upap_setloginpasswd(int unit, const char *luser, const char *lpassword)
+{
+	upap_state *u = &upap[unit];
+	
+	/* Save the username and password we're given */
+	u->us_user = luser;
+	u->us_userlen = strlen(luser);
+	u->us_passwd = lpassword;
+	u->us_passwdlen = strlen(lpassword);
+}
+
+
+/*
+ * upap_authwithpeer - Authenticate us with our peer (start client).
+ *
+ * Set new state and send authenticate's.
+ */
+void upap_authwithpeer(int unit, char *user, char *password)
+{
+	upap_state *u = &upap[unit];
+	
+	UPAPDEBUG((LOG_INFO, "upap_authwithpeer: %d user=%s password=%s s=%d\n",
+				unit, user, password, u->us_clientstate));
+	
+	upap_setloginpasswd(unit, user, password);
+
+	u->us_transmits = 0;
+	
+	/* Lower layer up yet? */
+	if (u->us_clientstate == UPAPCS_INITIAL ||
+			u->us_clientstate == UPAPCS_PENDING) {
+		u->us_clientstate = UPAPCS_PENDING;
+		return;
+	}
+	
+	upap_sauthreq(u);			/* Start protocol */
+}
+
+
+/*
+ * upap_authpeer - Authenticate our peer (start server).
+ *
+ * Set new state.
+ */
+void upap_authpeer(int unit)
+{
+	upap_state *u = &upap[unit];
+	
+	/* Lower layer up yet? */
+	if (u->us_serverstate == UPAPSS_INITIAL ||
+			u->us_serverstate == UPAPSS_PENDING) {
+		u->us_serverstate = UPAPSS_PENDING;
+		return;
+	}
+	
+	u->us_serverstate = UPAPSS_LISTEN;
+	if (u->us_reqtimeout > 0)
+		TIMEOUT(upap_reqtimeout, u, u->us_reqtimeout);
+}
+
+
+
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+/*
+ * upap_init - Initialize a UPAP unit.
+ */
+static void upap_init(int unit)
+{
+	upap_state *u = &upap[unit];
+
+	UPAPDEBUG((LOG_INFO, "upap_init: %d\n", unit));	
+	u->us_unit = unit;
+	u->us_user = NULL;
+	u->us_userlen = 0;
+	u->us_passwd = NULL;
+	u->us_passwdlen = 0;
+	u->us_clientstate = UPAPCS_INITIAL;
+	u->us_serverstate = UPAPSS_INITIAL;
+	u->us_id = 0;
+	u->us_timeouttime = UPAP_DEFTIMEOUT;
+	u->us_maxtransmits = 10;
+	u->us_reqtimeout = UPAP_DEFREQTIME;
+}
+
+/*
+ * upap_timeout - Retransmission timer for sending auth-reqs expired.
+ */
+static void upap_timeout(void *arg)
+{
+	upap_state *u = (upap_state *) arg;
+	
+	UPAPDEBUG((LOG_INFO, "upap_timeout: %d timeout %d expired s=%d\n", 
+				u->us_unit, u->us_timeouttime, u->us_clientstate));
+	
+	if (u->us_clientstate != UPAPCS_AUTHREQ)
+		return;
+	
+	if (u->us_transmits >= u->us_maxtransmits) {
+		/* give up in disgust */
+		UPAPDEBUG((LOG_ERR, "No response to PAP authenticate-requests\n"));
+		u->us_clientstate = UPAPCS_BADAUTH;
+		auth_withpeer_fail(u->us_unit, PPP_PAP);
+		return;
+	}
+	
+	upap_sauthreq(u);		/* Send Authenticate-Request */
+}
+
+
+/*
+ * upap_reqtimeout - Give up waiting for the peer to send an auth-req.
+ */
+static void upap_reqtimeout(void *arg)
+{
+	upap_state *u = (upap_state *) arg;
+	
+	if (u->us_serverstate != UPAPSS_LISTEN)
+		return;			/* huh?? */
+	
+	auth_peer_fail(u->us_unit, PPP_PAP);
+	u->us_serverstate = UPAPSS_BADAUTH;
+}
+
+
+/*
+ * upap_lowerup - The lower layer is up.
+ *
+ * Start authenticating if pending.
+ */
+static void upap_lowerup(int unit)
+{
+	upap_state *u = &upap[unit];
+	
+	UPAPDEBUG((LOG_INFO, "upap_lowerup: %d s=%d\n", unit, u->us_clientstate));
+	
+	if (u->us_clientstate == UPAPCS_INITIAL)
+		u->us_clientstate = UPAPCS_CLOSED;
+	else if (u->us_clientstate == UPAPCS_PENDING) {
+		upap_sauthreq(u);	/* send an auth-request */
+	}
+	
+	if (u->us_serverstate == UPAPSS_INITIAL)
+		u->us_serverstate = UPAPSS_CLOSED;
+	else if (u->us_serverstate == UPAPSS_PENDING) {
+		u->us_serverstate = UPAPSS_LISTEN;
+		if (u->us_reqtimeout > 0)
+			TIMEOUT(upap_reqtimeout, u, u->us_reqtimeout);
+	}
+}
+
+
+/*
+ * upap_lowerdown - The lower layer is down.
+ *
+ * Cancel all timeouts.
+ */
+static void upap_lowerdown(int unit)
+{
+	upap_state *u = &upap[unit];
+	
+	UPAPDEBUG((LOG_INFO, "upap_lowerdown: %d s=%d\n", unit, u->us_clientstate));
+	
+	if (u->us_clientstate == UPAPCS_AUTHREQ)	/* Timeout pending? */
+		UNTIMEOUT(upap_timeout, u);		/* Cancel timeout */
+	if (u->us_serverstate == UPAPSS_LISTEN && u->us_reqtimeout > 0)
+		UNTIMEOUT(upap_reqtimeout, u);
+	
+	u->us_clientstate = UPAPCS_INITIAL;
+	u->us_serverstate = UPAPSS_INITIAL;
+}
+
+
+/*
+ * upap_protrej - Peer doesn't speak this protocol.
+ *
+ * This shouldn't happen.  In any case, pretend lower layer went down.
+ */
+static void upap_protrej(int unit)
+{
+	upap_state *u = &upap[unit];
+	
+	if (u->us_clientstate == UPAPCS_AUTHREQ) {
+		UPAPDEBUG((LOG_ERR, "PAP authentication failed due to protocol-reject\n"));
+		auth_withpeer_fail(unit, PPP_PAP);
+	}
+	if (u->us_serverstate == UPAPSS_LISTEN) {
+		UPAPDEBUG((LOG_ERR, "PAP authentication of peer failed (protocol-reject)\n"));
+		auth_peer_fail(unit, PPP_PAP);
+	}
+	upap_lowerdown(unit);
+}
+
+
+/*
+ * upap_input - Input UPAP packet.
+ */
+static void upap_input(int unit, u_char *inpacket, int l)
+{
+	upap_state *u = &upap[unit];
+	u_char *inp;
+	u_char code, id;
+	int len;
+	
+	/*
+	 * Parse header (code, id and length).
+	 * If packet too short, drop it.
+	 */
+	inp = inpacket;
+	if (l < UPAP_HEADERLEN) {
+		UPAPDEBUG((LOG_INFO, "pap_input: rcvd short header.\n"));
+		return;
+	}
+	GETCHAR(code, inp);
+	GETCHAR(id, inp);
+	GETSHORT(len, inp);
+	if (len < UPAP_HEADERLEN) {
+		UPAPDEBUG((LOG_INFO, "pap_input: rcvd illegal length.\n"));
+		return;
+	}
+	if (len > l) {
+		UPAPDEBUG((LOG_INFO, "pap_input: rcvd short packet.\n"));
+		return;
+	}
+	len -= UPAP_HEADERLEN;
+	
+	/*
+	 * Action depends on code.
+	 */
+	switch (code) {
+	case UPAP_AUTHREQ:
+		upap_rauthreq(u, inp, id, len);
+		break;
+	
+	case UPAP_AUTHACK:
+		upap_rauthack(u, inp, id, len);
+		break;
+	
+	case UPAP_AUTHNAK:
+		upap_rauthnak(u, inp, id, len);
+		break;
+	
+	default:				/* XXX Need code reject */
+		break;
+	}
+}
+
+
+/*
+ * upap_rauth - Receive Authenticate.
+ */
+static void upap_rauthreq(
+	upap_state *u, 
+	u_char *inp, 
+	int id,
+	int len
+)
+{
+	u_char ruserlen, rpasswdlen;
+	char *ruser, *rpasswd;
+	int retcode;
+	char *msg;
+	int msglen;
+	
+	UPAPDEBUG((LOG_INFO, "pap_rauth: Rcvd id %d.\n", id));
+	
+	if (u->us_serverstate < UPAPSS_LISTEN)
+		return;
+	
+	/*
+	 * If we receive a duplicate authenticate-request, we are
+	 * supposed to return the same status as for the first request.
+	 */
+	if (u->us_serverstate == UPAPSS_OPEN) {
+		upap_sresp(u, UPAP_AUTHACK, id, "", 0);	/* return auth-ack */
+		return;
+	}
+	if (u->us_serverstate == UPAPSS_BADAUTH) {
+		upap_sresp(u, UPAP_AUTHNAK, id, "", 0);	/* return auth-nak */
+		return;
+	}
+	
+	/*
+	 * Parse user/passwd.
+	 */
+	if (len < sizeof (u_char)) {
+		UPAPDEBUG((LOG_INFO, "pap_rauth: rcvd short packet.\n"));
+		return;
+	}
+	GETCHAR(ruserlen, inp);
+	len -= sizeof (u_char) + ruserlen + sizeof (u_char);
+	if (len < 0) {
+		UPAPDEBUG((LOG_INFO, "pap_rauth: rcvd short packet.\n"));
+		return;
+	}
+	ruser = (char *) inp;
+	INCPTR(ruserlen, inp);
+	GETCHAR(rpasswdlen, inp);
+	if (len < rpasswdlen) {
+		UPAPDEBUG((LOG_INFO, "pap_rauth: rcvd short packet.\n"));
+		return;
+	}
+	rpasswd = (char *) inp;
+	
+	/*
+	 * Check the username and password given.
+	 */
+	retcode = check_passwd(u->us_unit, ruser, ruserlen, rpasswd,
+			   rpasswdlen, &msg, &msglen);
+	BZERO(rpasswd, rpasswdlen);
+	
+	upap_sresp(u, retcode, id, msg, msglen);
+	
+	if (retcode == UPAP_AUTHACK) {
+		u->us_serverstate = UPAPSS_OPEN;
+		auth_peer_success(u->us_unit, PPP_PAP, ruser, ruserlen);
+	} else {
+		u->us_serverstate = UPAPSS_BADAUTH;
+		auth_peer_fail(u->us_unit, PPP_PAP);
+	}
+	
+	if (u->us_reqtimeout > 0)
+		UNTIMEOUT(upap_reqtimeout, u);
+}
+
+
+/*
+ * upap_rauthack - Receive Authenticate-Ack.
+ */
+static void upap_rauthack(
+	upap_state *u,
+	u_char *inp,
+	int id,
+	int len
+)
+{
+	u_char msglen;
+	char *msg;
+	
+	UPAPDEBUG((LOG_INFO, "pap_rauthack: Rcvd id %d s=%d\n", id, u->us_clientstate));
+	
+	if (u->us_clientstate != UPAPCS_AUTHREQ) /* XXX */
+		return;
+	
+	/*
+	 * Parse message.
+	 */
+	if (len < sizeof (u_char)) {
+		UPAPDEBUG((LOG_INFO, "pap_rauthack: rcvd short packet.\n"));
+		return;
+	}
+	GETCHAR(msglen, inp);
+	len -= sizeof (u_char);
+	if (len < msglen) {
+		UPAPDEBUG((LOG_INFO, "pap_rauthack: rcvd short packet.\n"));
+		return;
+	}
+	msg = (char *) inp;
+	PRINTMSG(msg, msglen);
+	
+	u->us_clientstate = UPAPCS_OPEN;
+	
+	auth_withpeer_success(u->us_unit, PPP_PAP);
+}
+
+
+/*
+ * upap_rauthnak - Receive Authenticate-Nakk.
+ */
+static void upap_rauthnak(
+	upap_state *u,
+	u_char *inp,
+	int id,
+	int len
+)
+{
+	u_char msglen;
+	char *msg;
+	
+	UPAPDEBUG((LOG_INFO, "pap_rauthnak: Rcvd id %d s=%d\n", id, u->us_clientstate));
+	
+	if (u->us_clientstate != UPAPCS_AUTHREQ) /* XXX */
+		return;
+	
+	/*
+	 * Parse message.
+	 */
+	if (len < sizeof (u_char)) {
+		UPAPDEBUG((LOG_INFO, "pap_rauthnak: rcvd short packet.\n"));
+		return;
+	}
+	GETCHAR(msglen, inp);
+	len -= sizeof (u_char);
+	if (len < msglen) {
+		UPAPDEBUG((LOG_INFO, "pap_rauthnak: rcvd short packet.\n"));
+		return;
+	}
+	msg = (char *) inp;
+	PRINTMSG(msg, msglen);
+	
+	u->us_clientstate = UPAPCS_BADAUTH;
+	
+	UPAPDEBUG((LOG_ERR, "PAP authentication failed\n"));
+	auth_withpeer_fail(u->us_unit, PPP_PAP);
+}
+
+
+/*
+ * upap_sauthreq - Send an Authenticate-Request.
+ */
+static void upap_sauthreq(upap_state *u)
+{
+	u_char *outp;
+	int outlen;
+	
+	outlen = UPAP_HEADERLEN + 2 * sizeof (u_char) 
+			+ u->us_userlen + u->us_passwdlen;
+	outp = outpacket_buf[u->us_unit];
+	
+	MAKEHEADER(outp, PPP_PAP);
+	
+	PUTCHAR(UPAP_AUTHREQ, outp);
+	PUTCHAR(++u->us_id, outp);
+	PUTSHORT(outlen, outp);
+	PUTCHAR(u->us_userlen, outp);
+	BCOPY(u->us_user, outp, u->us_userlen);
+	INCPTR(u->us_userlen, outp);
+	PUTCHAR(u->us_passwdlen, outp);
+	BCOPY(u->us_passwd, outp, u->us_passwdlen);
+	
+	pppWrite(u->us_unit, outpacket_buf[u->us_unit], outlen + PPP_HDRLEN);
+	
+	UPAPDEBUG((LOG_INFO, "pap_sauth: Sent id %d\n", u->us_id));
+	
+	TIMEOUT(upap_timeout, u, u->us_timeouttime);
+	++u->us_transmits;
+	u->us_clientstate = UPAPCS_AUTHREQ;
+}
+
+
+/*
+ * upap_sresp - Send a response (ack or nak).
+ */
+static void upap_sresp(
+	upap_state *u,
+	u_char code, 
+	u_char id,
+	char *msg,
+	int msglen
+)
+{
+	u_char *outp;
+	int outlen;
+	
+	outlen = UPAP_HEADERLEN + sizeof (u_char) + msglen;
+	outp = outpacket_buf[u->us_unit];
+	MAKEHEADER(outp, PPP_PAP);
+	
+	PUTCHAR(code, outp);
+	PUTCHAR(id, outp);
+	PUTSHORT(outlen, outp);
+	PUTCHAR(msglen, outp);
+	BCOPY(msg, outp, msglen);
+	pppWrite(u->us_unit, outpacket_buf[u->us_unit], outlen + PPP_HDRLEN);
+	
+	UPAPDEBUG((LOG_INFO, "pap_sresp: Sent code %d, id %d s=%d\n", 
+				code, id, u->us_clientstate));
+}
+
+#if 0
+/*
+ * upap_printpkt - print the contents of a PAP packet.
+ */
+static int upap_printpkt(
+	u_char *p,
+	int plen,
+	void (*printer) (void *, char *, ...),
+	void *arg
+)
+{
+	(void)p;
+	(void)plen;
+	(void)printer;
+	(void)arg;
+	return 0;
+}
+#endif
+
+#endif /* PAP_SUPPORT */
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/pap.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/pap.h
new file mode 100644
index 000000000..59eb2c71e
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/pap.h
@@ -0,0 +1,129 @@
+/*****************************************************************************
+* pap.h -  PPP Password Authentication Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-12-04 Guy Lancaster , Global Election Systems Inc.
+*	Original derived from BSD codes.
+*****************************************************************************/
+/*
+ * upap.h - User/Password Authentication Protocol definitions.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+
+#ifndef PAP_H
+#define PAP_H
+
+/*************************
+*** PUBLIC DEFINITIONS ***
+*************************/
+/*
+ * Packet header = Code, id, length.
+ */
+#define UPAP_HEADERLEN	(sizeof (u_char) + sizeof (u_char) + sizeof (u_short))
+
+
+/*
+ * UPAP codes.
+ */
+#define UPAP_AUTHREQ	1	/* Authenticate-Request */
+#define UPAP_AUTHACK	2	/* Authenticate-Ack */
+#define UPAP_AUTHNAK	3	/* Authenticate-Nak */
+
+/*
+ * Client states.
+ */
+#define UPAPCS_INITIAL	0	/* Connection down */
+#define UPAPCS_CLOSED	1	/* Connection up, haven't requested auth */
+#define UPAPCS_PENDING	2	/* Connection down, have requested auth */
+#define UPAPCS_AUTHREQ	3	/* We've sent an Authenticate-Request */
+#define UPAPCS_OPEN		4	/* We've received an Ack */
+#define UPAPCS_BADAUTH	5	/* We've received a Nak */
+
+/*
+ * Server states.
+ */
+#define UPAPSS_INITIAL	0	/* Connection down */
+#define UPAPSS_CLOSED	1	/* Connection up, haven't requested auth */
+#define UPAPSS_PENDING	2	/* Connection down, have requested auth */
+#define UPAPSS_LISTEN	3	/* Listening for an Authenticate */
+#define UPAPSS_OPEN		4	/* We've sent an Ack */
+#define UPAPSS_BADAUTH	5	/* We've sent a Nak */
+
+
+/************************
+*** PUBLIC DATA TYPES ***
+************************/
+
+/*
+ * Each interface is described by upap structure.
+ */
+typedef struct upap_state {
+    int us_unit;			/* Interface unit number */
+    const char *us_user;	/* User */
+    int us_userlen;			/* User length */
+    const char *us_passwd;	/* Password */
+    int us_passwdlen;		/* Password length */
+    int us_clientstate;		/* Client state */
+    int us_serverstate;		/* Server state */
+    u_char us_id;			/* Current id */
+    int us_timeouttime;		/* Timeout (seconds) for auth-req retrans. */
+    int us_transmits;		/* Number of auth-reqs sent */
+    int us_maxtransmits;	/* Maximum number of auth-reqs to send */
+    int us_reqtimeout;		/* Time to wait for auth-req from peer */
+} upap_state;
+
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+
+extern upap_state upap[];
+
+void upap_setloginpasswd(int unit, const char *luser, const char *lpassword);
+void upap_authwithpeer (int, char *, char *);
+void upap_authpeer (int);
+
+extern struct protent pap_protent;
+
+#endif /* PAP_H */
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/ppp.c b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/ppp.c
new file mode 100644
index 000000000..00a7956df
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/ppp.c
@@ -0,0 +1,1623 @@
+/*****************************************************************************
+* ppp.c - Network Point to Point Protocol program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-11-05 Guy Lancaster , Global Election Systems Inc.
+*   Original.
+*****************************************************************************/
+
+/*
+ * ppp_defs.h - PPP definitions.
+ *
+ * if_pppvar.h - private structures and declarations for PPP.
+ *
+ * Copyright (c) 1994 The Australian National University.
+ * All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, provided that the above copyright
+ * notice appears in all copies.  This software is provided without any
+ * warranty, express or implied. The Australian National University
+ * makes no representations about the suitability of this software for
+ * any purpose.
+ *
+ * IN NO EVENT SHALL THE AUSTRALIAN NATIONAL UNIVERSITY BE LIABLE TO ANY
+ * PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES
+ * ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF
+ * THE AUSTRALIAN NATIONAL UNIVERSITY HAVE BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * THE AUSTRALIAN NATIONAL UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE.  THE SOFTWARE PROVIDED HEREUNDER IS
+ * ON AN "AS IS" BASIS, AND THE AUSTRALIAN NATIONAL UNIVERSITY HAS NO
+ * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS,
+ * OR MODIFICATIONS.
+ */
+
+/*
+ * if_ppp.h - Point-to-Point Protocol definitions.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+ 
+#include 
+ 
+#include "ppp.h"
+#if PPP_SUPPORT > 0
+#include "randm.h"
+#include "fsm.h"
+#if PAP_SUPPORT > 0
+#include "pap.h"
+#endif
+#if CHAP_SUPPORT > 0
+#include "chap.h"
+#endif
+#include "ipcp.h"
+#include "lcp.h"
+#include "magic.h"
+#include "auth.h"
+#if VJ_SUPPORT > 0
+#include "vj.h"
+#endif
+
+#include "pppdebug.h"
+
+/*************************/
+/*** LOCAL DEFINITIONS ***/
+/*************************/
+
+/*
+ * The basic PPP frame.
+ */
+#define PPP_ADDRESS(p)  (((u_char *)(p))[0])
+#define PPP_CONTROL(p)  (((u_char *)(p))[1])
+#define PPP_PROTOCOL(p) ((((u_char *)(p))[2] << 8) + ((u_char *)(p))[3])
+
+/* PPP packet parser states.  Current state indicates operation yet to be
+ * completed. */
+typedef enum {
+    PDIDLE = 0,                 /* Idle state - waiting. */
+    PDSTART,                    /* Process start flag. */
+    PDADDRESS,                  /* Process address field. */
+    PDCONTROL,                  /* Process control field. */
+    PDPROTOCOL1,                /* Process protocol field 1. */
+    PDPROTOCOL2,                /* Process protocol field 2. */
+    PDDATA                      /* Process data byte. */
+} PPPDevStates;
+
+#define ESCAPE_P(accm, c) ((accm)[(c) >> 3] & pppACCMMask[c & 0x07])
+
+/************************/
+/*** LOCAL DATA TYPES ***/
+/************************/
+/*
+ * PPP interface control block.
+ */
+typedef struct PPPControl_s {
+    char openFlag;                      /* True when in use. */
+    char oldFrame;                      /* Old framing character for fd. */
+    sio_fd_t fd;                    /* File device ID of port. */
+    int  kill_link;                     /* Shut the link down. */
+    int  sig_hup;                       /* Carrier lost. */
+    int  if_up;                         /* True when the interface is up. */
+    int  errCode;                       /* Code indicating why interface is down. */
+    struct pbuf *inHead, *inTail;       /* The input packet. */
+    PPPDevStates inState;               /* The input process state. */
+    char inEscaped;                     /* Escape next character. */
+    u16_t inProtocol;                   /* The input protocol code. */
+    u16_t inFCS;                        /* Input Frame Check Sequence value. */
+    int  mtu;                           /* Peer's mru */
+    int  pcomp;                         /* Does peer accept protocol compression? */
+    int  accomp;                        /* Does peer accept addr/ctl compression? */
+    u_long lastXMit;                    /* Time of last transmission. */
+    ext_accm inACCM;                    /* Async-Ctl-Char-Map for input. */
+    ext_accm outACCM;                   /* Async-Ctl-Char-Map for output. */
+#if VJ_SUPPORT > 0
+    int  vjEnabled;                     /* Flag indicating VJ compression enabled. */
+    struct vjcompress vjComp;           /* Van Jabobsen compression header. */
+#endif
+
+    struct netif netif;
+
+    struct ppp_addrs addrs;
+
+    void (*linkStatusCB)(void *ctx, int errCode, void *arg);
+    void *linkStatusCtx;
+
+} PPPControl;
+
+
+/*
+ * Ioctl definitions.
+ */
+
+struct npioctl {
+    int     protocol;           /* PPP procotol, e.g. PPP_IP */
+    enum NPmode mode;
+};
+
+
+
+/***********************************/
+/*** LOCAL FUNCTION DECLARATIONS ***/
+/***********************************/
+static void pppMain(void *pd);
+static void pppDrop(PPPControl *pc);
+static void pppInProc(int pd, u_char *s, int l);
+
+
+/******************************/
+/*** PUBLIC DATA STRUCTURES ***/
+/******************************/
+u_long subnetMask;
+
+static PPPControl pppControl[NUM_PPP]; /* The PPP interface control blocks. */
+
+/*
+ * PPP Data Link Layer "protocol" table.
+ * One entry per supported protocol.
+ * The last entry must be NULL.
+ */
+struct protent *ppp_protocols[] = {
+    &lcp_protent,
+#if PAP_SUPPORT > 0
+    &pap_protent,
+#endif
+#if CHAP_SUPPORT > 0
+    &chap_protent,
+#endif
+#if CBCP_SUPPORT > 0
+    &cbcp_protent,
+#endif
+    &ipcp_protent,
+#if CCP_SUPPORT > 0
+    &ccp_protent,
+#endif
+    NULL
+};
+
+
+/*
+ * Buffers for outgoing packets.  This must be accessed only from the appropriate
+ * PPP task so that it doesn't need to be protected to avoid collisions.
+ */
+u_char outpacket_buf[NUM_PPP][PPP_MRU+PPP_HDRLEN];  
+
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+
+/*
+ * FCS lookup table as calculated by genfcstab.
+ */
+static const u_short fcstab[256] = {
+    0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf,
+    0x8c48, 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7,
+    0x1081, 0x0108, 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e,
+    0x9cc9, 0x8d40, 0xbfdb, 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876,
+    0x2102, 0x308b, 0x0210, 0x1399, 0x6726, 0x76af, 0x4434, 0x55bd,
+    0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, 0xfae7, 0xc87c, 0xd9f5,
+    0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, 0x54b5, 0x453c,
+    0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, 0xc974,
+    0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb,
+    0xce4c, 0xdfc5, 0xed5e, 0xfcd7, 0x8868, 0x99e1, 0xab7a, 0xbaf3,
+    0x5285, 0x430c, 0x7197, 0x601e, 0x14a1, 0x0528, 0x37b3, 0x263a,
+    0xdecd, 0xcf44, 0xfddf, 0xec56, 0x98e9, 0x8960, 0xbbfb, 0xaa72,
+    0x6306, 0x728f, 0x4014, 0x519d, 0x2522, 0x34ab, 0x0630, 0x17b9,
+    0xef4e, 0xfec7, 0xcc5c, 0xddd5, 0xa96a, 0xb8e3, 0x8a78, 0x9bf1,
+    0x7387, 0x620e, 0x5095, 0x411c, 0x35a3, 0x242a, 0x16b1, 0x0738,
+    0xffcf, 0xee46, 0xdcdd, 0xcd54, 0xb9eb, 0xa862, 0x9af9, 0x8b70,
+    0x8408, 0x9581, 0xa71a, 0xb693, 0xc22c, 0xd3a5, 0xe13e, 0xf0b7,
+    0x0840, 0x19c9, 0x2b52, 0x3adb, 0x4e64, 0x5fed, 0x6d76, 0x7cff,
+    0x9489, 0x8500, 0xb79b, 0xa612, 0xd2ad, 0xc324, 0xf1bf, 0xe036,
+    0x18c1, 0x0948, 0x3bd3, 0x2a5a, 0x5ee5, 0x4f6c, 0x7df7, 0x6c7e,
+    0xa50a, 0xb483, 0x8618, 0x9791, 0xe32e, 0xf2a7, 0xc03c, 0xd1b5,
+    0x2942, 0x38cb, 0x0a50, 0x1bd9, 0x6f66, 0x7eef, 0x4c74, 0x5dfd,
+    0xb58b, 0xa402, 0x9699, 0x8710, 0xf3af, 0xe226, 0xd0bd, 0xc134,
+    0x39c3, 0x284a, 0x1ad1, 0x0b58, 0x7fe7, 0x6e6e, 0x5cf5, 0x4d7c,
+    0xc60c, 0xd785, 0xe51e, 0xf497, 0x8028, 0x91a1, 0xa33a, 0xb2b3,
+    0x4a44, 0x5bcd, 0x6956, 0x78df, 0x0c60, 0x1de9, 0x2f72, 0x3efb,
+    0xd68d, 0xc704, 0xf59f, 0xe416, 0x90a9, 0x8120, 0xb3bb, 0xa232,
+    0x5ac5, 0x4b4c, 0x79d7, 0x685e, 0x1ce1, 0x0d68, 0x3ff3, 0x2e7a,
+    0xe70e, 0xf687, 0xc41c, 0xd595, 0xa12a, 0xb0a3, 0x8238, 0x93b1,
+    0x6b46, 0x7acf, 0x4854, 0x59dd, 0x2d62, 0x3ceb, 0x0e70, 0x1ff9,
+    0xf78f, 0xe606, 0xd49d, 0xc514, 0xb1ab, 0xa022, 0x92b9, 0x8330,
+    0x7bc7, 0x6a4e, 0x58d5, 0x495c, 0x3de3, 0x2c6a, 0x1ef1, 0x0f78
+};
+
+/* PPP's Asynchronous-Control-Character-Map.  The mask array is used
+ * to select the specific bit for a character. */
+static u_char pppACCMMask[] = {
+    0x01,
+    0x02,
+    0x04,
+    0x08,
+    0x10,
+    0x20,
+    0x40,
+    0x80
+};
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/* Initialize the PPP subsystem. */
+
+struct ppp_settings ppp_settings;
+
+void pppInit(void)
+{
+    struct protent *protp;
+    int i, j;
+    
+	memset(&ppp_settings, 0, sizeof(ppp_settings));
+	ppp_settings.usepeerdns = 1;
+	pppSetAuth(PPPAUTHTYPE_NONE, NULL, NULL);
+
+	magicInit();
+
+    for (i = 0; i < NUM_PPP; i++) {
+        pppControl[i].openFlag = 0;
+
+		subnetMask = htonl(0xffffff00);
+    
+        /*
+         * Initialize to the standard option set.
+         */
+        for (j = 0; (protp = ppp_protocols[j]) != NULL; ++j)
+            (*protp->init)(i);
+    }
+
+#if LINK_STATS
+    /* Clear the statistics. */
+    memset(&lwip_stats.link, 0, sizeof(lwip_stats.link));
+#endif
+}
+
+void pppSetAuth(enum pppAuthType authType, const char *user, const char *passwd)
+{
+    switch(authType) {
+	case PPPAUTHTYPE_NONE:
+	default:
+#ifdef LWIP_PPP_STRICT_PAP_REJECT
+	    ppp_settings.refuse_pap = 1;
+#else
+	    /* some providers request pap and accept an empty login/pw */
+	    ppp_settings.refuse_pap = 0;
+#endif
+	    ppp_settings.refuse_chap = 1;
+	    break;
+	case PPPAUTHTYPE_ANY:
+/* Warning: Using PPPAUTHTYPE_ANY might have security consequences.
+ * RFC 1994 says:
+ *
+ * In practice, within or associated with each PPP server, there is a
+ * database which associates "user" names with authentication
+ * information ("secrets").  It is not anticipated that a particular
+ * named user would be authenticated by multiple methods.  This would
+ * make the user vulnerable to attacks which negotiate the least secure
+ * method from among a set (such as PAP rather than CHAP).  If the same
+ * secret was used, PAP would reveal the secret to be used later with
+ * CHAP.
+ *
+ * Instead, for each user name there should be an indication of exactly
+ * one method used to authenticate that user name.  If a user needs to
+ * make use of different authentication methods under different
+ * circumstances, then distinct user names SHOULD be employed, each of
+ * which identifies exactly one authentication method.
+ *
+ */
+	    ppp_settings.refuse_pap = 0;
+	    ppp_settings.refuse_chap = 0;
+	    break;
+	case PPPAUTHTYPE_PAP:
+	    ppp_settings.refuse_pap = 0;
+	    ppp_settings.refuse_chap = 1;
+	    break;
+	case PPPAUTHTYPE_CHAP:
+	    ppp_settings.refuse_pap = 1;
+	    ppp_settings.refuse_chap = 0;
+	    break;
+    }
+
+    if(user) {
+	strncpy(ppp_settings.user, user, sizeof(ppp_settings.user)-1);
+	ppp_settings.user[sizeof(ppp_settings.user)-1] = '\0';
+    } else
+	ppp_settings.user[0] = '\0';
+
+    if(passwd) {
+	strncpy(ppp_settings.passwd, passwd, sizeof(ppp_settings.passwd)-1);
+	ppp_settings.passwd[sizeof(ppp_settings.passwd)-1] = '\0';
+    } else
+	ppp_settings.passwd[0] = '\0';
+}
+
+/* Open a new PPP connection using the given I/O device.
+ * This initializes the PPP control block but does not
+ * attempt to negotiate the LCP session.  If this port
+ * connects to a modem, the modem connection must be
+ * established before calling this.
+ * Return a new PPP connection descriptor on success or
+ * an error code (negative) on failure. */
+int pppOpen(sio_fd_t fd, void (*linkStatusCB)(void *ctx, int errCode, void *arg), void *linkStatusCtx)
+{
+    PPPControl *pc;
+    int pd;
+
+    /* Find a free PPP session descriptor. Critical region? */
+    for (pd = 0; pd < NUM_PPP && pppControl[pd].openFlag != 0; pd++);
+    if (pd >= NUM_PPP)
+        pd = PPPERR_OPEN;
+    else
+        pppControl[pd].openFlag = !0;
+
+    /* Launch a deamon thread. */
+    if (pd >= 0) {
+
+        pppControl[pd].openFlag = 1;
+
+        lcp_init(pd);
+        pc = &pppControl[pd];
+        pc->fd = fd;
+        pc->kill_link = 0;
+        pc->sig_hup = 0;
+        pc->if_up = 0;
+        pc->errCode = 0;
+        pc->inState = PDIDLE;
+        pc->inHead = NULL;
+        pc->inTail = NULL;
+        pc->inEscaped = 0;
+        pc->lastXMit = 0;
+
+#if VJ_SUPPORT > 0
+        pc->vjEnabled = 0;
+        vj_compress_init(&pc->vjComp);
+#endif
+
+        /* 
+         * Default the in and out accm so that escape and flag characters
+         * are always escaped. 
+         */
+        memset(pc->inACCM, 0, sizeof(ext_accm));
+        pc->inACCM[15] = 0x60;
+        memset(pc->outACCM, 0, sizeof(ext_accm));
+        pc->outACCM[15] = 0x60;
+
+	pc->linkStatusCB = linkStatusCB;
+	pc->linkStatusCtx = linkStatusCtx;
+
+	sys_thread_new(pppMain, (void*)pd, PPP_THREAD_PRIO);
+	if(!linkStatusCB) {
+		while(pd >= 0 && !pc->if_up) {
+			sys_msleep(500);
+			if (lcp_phase[pd] == PHASE_DEAD) {
+				pppClose(pd);
+				if (pc->errCode)
+					pd = pc->errCode;
+				else
+					pd = PPPERR_CONNECT;
+			}
+		}
+	}
+    }
+    return pd;
+}
+
+/* Close a PPP connection and release the descriptor. 
+ * Any outstanding packets in the queues are dropped.
+ * Return 0 on success, an error code on failure. */
+int pppClose(int pd)
+{
+    PPPControl *pc = &pppControl[pd];
+    int st = 0;
+
+    /* Disconnect */
+    pc->kill_link = !0;
+    pppMainWakeup(pd);
+    
+    if(!pc->linkStatusCB) {
+	    while(st >= 0 && lcp_phase[pd] != PHASE_DEAD) {
+		    sys_msleep(500);
+		    break;
+	    }
+    }
+    return st;
+}
+
+/* This function is called when carrier is lost on the PPP channel. */
+void pppSigHUP(int pd)
+{
+    PPPControl *pc = &pppControl[pd];
+
+    pc->sig_hup = 1;
+    pppMainWakeup(pd);
+}
+
+static void nPut(PPPControl *pc, struct pbuf *nb)
+{
+	struct pbuf *b;
+	int c;
+
+	for(b = nb; b != NULL; b = b->next) {
+	    if((c = sio_write(pc->fd, b->payload, b->len)) != b->len) {
+		PPPDEBUG((LOG_WARNING,
+			    "PPP nPut: incomplete sio_write(%d,, %u) = %d\n", pc->fd, b->len, c));
+#if LINK_STATS
+		lwip_stats.link.err++;
+#endif /* LINK_STATS */
+		pc->lastXMit = 0; /* prepend PPP_FLAG to next packet */
+		break;
+	    }
+	}
+	pbuf_free(nb);
+
+#if LINK_STATS
+	lwip_stats.link.xmit++;
+#endif /* LINK_STATS */
+}
+
+/* 
+ * pppAppend - append given character to end of given pbuf.  If outACCM
+ * is not NULL and the character needs to be escaped, do so.
+ * If pbuf is full, append another.
+ * Return the current pbuf.
+ */
+static struct pbuf *pppAppend(u_char c, struct pbuf *nb, ext_accm *outACCM)
+{
+    struct pbuf *tb = nb;
+    
+    /* Make sure there is room for the character and an escape code.
+     * Sure we don't quite fill the buffer if the character doesn't
+     * get escaped but is one character worth complicating this? */
+    /* Note: We assume no packet header. */
+    if (nb && (PBUF_POOL_BUFSIZE - nb->len) < 2) {
+	tb = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL);
+	if (tb) {
+	    nb->next = tb;
+        }
+#if LINK_STATS
+	else {
+	    lwip_stats.link.memerr++;
+	}
+#endif /* LINK_STATS */
+	nb = tb;
+    }
+    if (nb) {
+	if (outACCM && ESCAPE_P(*outACCM, c)) {
+            *((u_char*)nb->payload + nb->len++) = PPP_ESCAPE;
+            *((u_char*)nb->payload + nb->len++) = c ^ PPP_TRANS;
+        }
+        else
+            *((u_char*)nb->payload + nb->len++) = c;
+    }
+        
+    return tb;
+}
+
+/* Send a packet on the given connection. */
+static err_t pppifOutput(struct netif *netif, struct pbuf *pb, struct ip_addr *ipaddr)
+{
+    int pd = (int)netif->state;
+    u_short protocol = PPP_IP;
+    PPPControl *pc = &pppControl[pd];
+    u_int fcsOut = PPP_INITFCS;
+    struct pbuf *headMB = NULL, *tailMB = NULL, *p;
+    u_char c;
+
+    (void)ipaddr;
+
+    /* Validate parameters. */
+    /* We let any protocol value go through - it can't hurt us
+     * and the peer will just drop it if it's not accepting it. */
+	if (pd < 0 || pd >= NUM_PPP || !pc->openFlag || !pb) {
+        PPPDEBUG((LOG_WARNING, "pppifOutput[%d]: bad parms prot=%d pb=%p\n",
+                    pd, protocol, pb));
+#if LINK_STATS
+		lwip_stats.link.opterr++;
+		lwip_stats.link.drop++;
+#endif
+		return ERR_ARG;
+	}
+
+    /* Check that the link is up. */
+	if (lcp_phase[pd] == PHASE_DEAD) {
+        PPPDEBUG((LOG_ERR, "pppifOutput[%d]: link not up\n", pd));
+#if LINK_STATS
+		lwip_stats.link.rterr++;
+		lwip_stats.link.drop++;
+#endif
+		return ERR_RTE;
+	}
+
+    /* Grab an output buffer. */
+	headMB = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL);
+    if (headMB == NULL) {
+        PPPDEBUG((LOG_WARNING, "pppifOutput[%d]: first alloc fail\n", pd));
+#if LINK_STATS
+		lwip_stats.link.memerr++;
+		lwip_stats.link.drop++;
+#endif /* LINK_STATS */
+        return ERR_MEM;
+    }
+        
+#if VJ_SUPPORT > 0
+    /* 
+     * Attempt Van Jacobson header compression if VJ is configured and
+     * this is an IP packet. 
+     */
+    if (protocol == PPP_IP && pc->vjEnabled) {
+        switch (vj_compress_tcp(&pc->vjComp, pb)) {
+        case TYPE_IP:
+            /* No change...
+            protocol = PPP_IP_PROTOCOL;
+             */
+            break;
+        case TYPE_COMPRESSED_TCP:
+            protocol = PPP_VJC_COMP;
+            break;
+        case TYPE_UNCOMPRESSED_TCP:
+            protocol = PPP_VJC_UNCOMP;
+            break;
+        default:
+            PPPDEBUG((LOG_WARNING, "pppifOutput[%d]: bad IP packet\n", pd));
+#if LINK_STATS
+			lwip_stats.link.proterr++;
+			lwip_stats.link.drop++;
+#endif
+        	pbuf_free(headMB);
+            return ERR_VAL;
+        }
+    }
+#endif
+        
+    tailMB = headMB;
+        
+    /* Build the PPP header. */
+    if ((sys_jiffies() - pc->lastXMit) >= PPP_MAXIDLEFLAG)
+        tailMB = pppAppend(PPP_FLAG, tailMB, NULL);
+    pc->lastXMit = sys_jiffies();
+    if (!pc->accomp) {
+        fcsOut = PPP_FCS(fcsOut, PPP_ALLSTATIONS);
+        tailMB = pppAppend(PPP_ALLSTATIONS, tailMB, &pc->outACCM);
+        fcsOut = PPP_FCS(fcsOut, PPP_UI);
+        tailMB = pppAppend(PPP_UI, tailMB, &pc->outACCM);
+    }
+    if (!pc->pcomp || protocol > 0xFF) {
+        c = (protocol >> 8) & 0xFF;
+        fcsOut = PPP_FCS(fcsOut, c);
+        tailMB = pppAppend(c, tailMB, &pc->outACCM);
+    }
+    c = protocol & 0xFF;
+    fcsOut = PPP_FCS(fcsOut, c);
+    tailMB = pppAppend(c, tailMB, &pc->outACCM);
+    
+    /* Load packet. */
+	for(p = pb; p; p = p->next) {
+    	int n;
+    	u_char *sPtr;
+
+        sPtr = (u_char*)p->payload;
+        n = p->len;
+        while (n-- > 0) {
+            c = *sPtr++;
+            
+            /* Update FCS before checking for special characters. */
+            fcsOut = PPP_FCS(fcsOut, c);
+            
+            /* Copy to output buffer escaping special characters. */
+            tailMB = pppAppend(c, tailMB, &pc->outACCM);
+        }
+    }
+
+    /* Add FCS and trailing flag. */
+    c = ~fcsOut & 0xFF;
+    tailMB = pppAppend(c, tailMB, &pc->outACCM);
+    c = (~fcsOut >> 8) & 0xFF;
+    tailMB = pppAppend(c, tailMB, &pc->outACCM);
+    tailMB = pppAppend(PPP_FLAG, tailMB, NULL);
+        
+    /* If we failed to complete the packet, throw it away. */
+    if (!tailMB) {
+        PPPDEBUG((LOG_WARNING,
+                    "pppifOutput[%d]: Alloc err - dropping proto=%d\n", 
+                    pd, protocol));
+        pbuf_free(headMB);
+#if LINK_STATS
+		lwip_stats.link.memerr++;
+		lwip_stats.link.drop++;
+#endif
+        return ERR_MEM;
+    }
+
+	/* Send it. */
+    PPPDEBUG((LOG_INFO, "pppifOutput[%d]: proto=0x%04X\n", pd, protocol));
+
+    nPut(pc, headMB);
+
+    return ERR_OK;
+}
+
+/* Get and set parameters for the given connection.
+ * Return 0 on success, an error code on failure. */
+int  pppIOCtl(int pd, int cmd, void *arg)
+{
+    PPPControl *pc = &pppControl[pd];
+    int st = 0;
+
+    if (pd < 0 || pd >= NUM_PPP)
+        st = PPPERR_PARAM;
+    else {
+        switch(cmd) {
+        case PPPCTLG_UPSTATUS:      /* Get the PPP up status. */
+            if (arg) 
+                *(int *)arg = (int)(pc->if_up);
+            else
+                st = PPPERR_PARAM;
+            break;
+        case PPPCTLS_ERRCODE:       /* Set the PPP error code. */
+            if (arg) 
+                pc->errCode = *(int *)arg;
+            else
+                st = PPPERR_PARAM;
+            break;
+        case PPPCTLG_ERRCODE:       /* Get the PPP error code. */
+            if (arg) 
+                *(int *)arg = (int)(pc->errCode);
+            else
+                st = PPPERR_PARAM;
+            break;
+        case PPPCTLG_FD:
+            if (arg) 
+                *(sio_fd_t *)arg = pc->fd;
+            else
+                st = PPPERR_PARAM;
+            break;
+        default:
+            st = PPPERR_PARAM;
+            break;
+        }
+    }
+    
+    return st;
+}
+
+/*
+ * Return the Maximum Transmission Unit for the given PPP connection.
+ */
+u_int pppMTU(int pd)
+{
+    PPPControl *pc = &pppControl[pd];
+    u_int st;
+    
+    /* Validate parameters. */
+    if (pd < 0 || pd >= NUM_PPP || !pc->openFlag)
+        st = 0;
+    else
+        st = pc->mtu;
+        
+    return st;
+}
+
+/*
+ * Write n characters to a ppp link.
+ *  RETURN: >= 0 Number of characters written
+ *           -1 Failed to write to device
+ */
+int pppWrite(int pd, const u_char *s, int n)
+{
+    PPPControl *pc = &pppControl[pd];
+    u_char c;
+    u_int fcsOut = PPP_INITFCS;
+    struct pbuf *headMB = NULL, *tailMB;
+	headMB = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL);
+    if (headMB == NULL) {
+#if LINK_STATS
+		lwip_stats.link.memerr++;
+		lwip_stats.link.proterr++;
+#endif /* LINK_STATS */
+		return PPPERR_ALLOC;
+    }
+
+    tailMB = headMB;
+        
+    /* If the link has been idle, we'll send a fresh flag character to
+     * flush any noise. */
+    if ((sys_jiffies() - pc->lastXMit) >= PPP_MAXIDLEFLAG)
+        tailMB = pppAppend(PPP_FLAG, tailMB, NULL);
+    pc->lastXMit = sys_jiffies();
+     
+    /* Load output buffer. */
+    while (n-- > 0) {
+        c = *s++;
+        
+        /* Update FCS before checking for special characters. */
+        fcsOut = PPP_FCS(fcsOut, c);
+        
+        /* Copy to output buffer escaping special characters. */
+        tailMB = pppAppend(c, tailMB, &pc->outACCM);
+    }
+    
+    /* Add FCS and trailing flag. */
+    c = ~fcsOut & 0xFF;
+    tailMB = pppAppend(c, tailMB, &pc->outACCM);
+    c = (~fcsOut >> 8) & 0xFF;
+    tailMB = pppAppend(c, tailMB, &pc->outACCM);
+    tailMB = pppAppend(PPP_FLAG, tailMB, NULL);
+        
+    /* If we failed to complete the packet, throw it away.
+     * Otherwise send it. */
+    if (!tailMB) {
+		PPPDEBUG((LOG_WARNING,
+                "pppWrite[%d]: Alloc err - dropping pbuf len=%d\n", pd, headMB->len));
+/*                "pppWrite[%d]: Alloc err - dropping %d:%.*H", pd, headMB->len, LWIP_MIN(headMB->len * 2, 40), headMB->payload)); */
+		pbuf_free(headMB);
+#if LINK_STATS
+		lwip_stats.link.memerr++;
+		lwip_stats.link.proterr++;
+#endif /* LINK_STATS */
+		return PPPERR_ALLOC;
+	}
+
+    PPPDEBUG((LOG_INFO, "pppWrite[%d]: len=%d\n", pd, headMB->len));
+/*     "pppWrite[%d]: %d:%.*H", pd, headMB->len, LWIP_MIN(headMB->len * 2, 40), headMB->payload)); */
+    nPut(pc, headMB);
+
+    return PPPERR_NONE;
+}
+
+/*
+ * ppp_send_config - configure the transmit characteristics of
+ * the ppp interface.
+ */
+void ppp_send_config(
+    int unit, 
+    int mtu,
+    u32_t asyncmap,
+    int pcomp, 
+    int accomp
+)
+{
+    PPPControl *pc = &pppControl[unit];
+    int i;
+    
+    pc->mtu = mtu;
+    pc->pcomp = pcomp;
+    pc->accomp = accomp;
+    
+    /* Load the ACCM bits for the 32 control codes. */
+    for (i = 0; i < 32/8; i++)
+        pc->outACCM[i] = (u_char)((asyncmap >> (8 * i)) & 0xFF);
+    PPPDEBUG((LOG_INFO, "ppp_send_config[%d]: outACCM=%X %X %X %X\n",
+                unit,
+                pc->outACCM[0], pc->outACCM[1], pc->outACCM[2], pc->outACCM[3]));
+}
+
+
+/*
+ * ppp_set_xaccm - set the extended transmit ACCM for the interface.
+ */
+void ppp_set_xaccm(int unit, ext_accm *accm)
+{
+    memcpy(pppControl[unit].outACCM, accm, sizeof(ext_accm));
+    PPPDEBUG((LOG_INFO, "ppp_set_xaccm[%d]: outACCM=%X %X %X %X\n",
+                unit,
+                pppControl[unit].outACCM[0],
+                pppControl[unit].outACCM[1],
+                pppControl[unit].outACCM[2],
+                pppControl[unit].outACCM[3]));
+}
+
+
+/*
+ * ppp_recv_config - configure the receive-side characteristics of
+ * the ppp interface.
+ */
+void ppp_recv_config(
+    int unit, 
+    int mru,
+    u32_t asyncmap,
+    int pcomp, 
+    int accomp
+)
+{
+    PPPControl *pc = &pppControl[unit];
+    int i;
+    
+	(void)accomp;
+	(void)pcomp;
+	(void)mru;
+
+    /* Load the ACCM bits for the 32 control codes. */
+    for (i = 0; i < 32 / 8; i++)
+        pc->inACCM[i] = (u_char)(asyncmap >> (i * 8));
+    PPPDEBUG((LOG_INFO, "ppp_recv_config[%d]: inACCM=%X %X %X %X\n",
+                unit,
+                pc->inACCM[0], pc->inACCM[1], pc->inACCM[2], pc->inACCM[3]));
+}
+
+#if 0
+/*
+ * ccp_test - ask kernel whether a given compression method
+ * is acceptable for use.  Returns 1 if the method and parameters
+ * are OK, 0 if the method is known but the parameters are not OK
+ * (e.g. code size should be reduced), or -1 if the method is unknown.
+ */
+int ccp_test(
+    int unit, 
+    int opt_len, 
+    int for_transmit,
+    u_char *opt_ptr
+)
+{
+    return 0;   /* XXX Currently no compression. */
+}
+
+/*
+ * ccp_flags_set - inform kernel about the current state of CCP.
+ */
+void ccp_flags_set(int unit, int isopen, int isup)
+{
+    /* XXX */
+}
+
+/*
+ * ccp_fatal_error - returns 1 if decompression was disabled as a
+ * result of an error detected after decompression of a packet,
+ * 0 otherwise.  This is necessary because of patent nonsense.
+ */
+int ccp_fatal_error(int unit)
+{
+    /* XXX */
+    return 0;
+}
+#endif
+
+/*
+ * get_idle_time - return how long the link has been idle.
+ */
+int get_idle_time(int u, struct ppp_idle *ip)
+{   
+    /* XXX */
+	(void)u;
+	(void)ip;
+
+    return 0;
+}
+
+
+/*
+ * Return user specified netmask, modified by any mask we might determine
+ * for address `addr' (in network byte order).
+ * Here we scan through the system's list of interfaces, looking for
+ * any non-point-to-point interfaces which might appear to be on the same
+ * network as `addr'.  If we find any, we OR in their netmask to the
+ * user-specified netmask.
+ */
+u32_t GetMask(u32_t addr)
+{
+    u32_t mask, nmask;
+    
+    htonl(addr);
+    if (IN_CLASSA(addr))    /* determine network mask for address class */
+        nmask = IN_CLASSA_NET;
+    else if (IN_CLASSB(addr))
+        nmask = IN_CLASSB_NET;
+    else
+        nmask = IN_CLASSC_NET;
+    /* class D nets are disallowed by bad_ip_adrs */
+    mask = subnetMask | htonl(nmask);
+    
+    /* XXX
+     * Scan through the system's network interfaces.
+     * Get each netmask and OR them into our mask.
+     */
+    
+    return mask;
+}
+
+/*
+ * sifvjcomp - config tcp header compression
+ */
+int sifvjcomp(
+    int pd, 
+    int vjcomp, 
+    int cidcomp, 
+    int maxcid
+)
+{
+#if VJ_SUPPORT > 0
+    PPPControl *pc = &pppControl[pd];
+    
+    pc->vjEnabled = vjcomp;
+    pc->vjComp.compressSlot = cidcomp;
+    pc->vjComp.maxSlotIndex = maxcid;
+    PPPDEBUG((LOG_INFO, "sifvjcomp: VJ compress enable=%d slot=%d max slot=%d\n",
+                vjcomp, cidcomp, maxcid));
+#endif
+
+    return 0;
+}
+
+/*
+ * pppifNetifInit - netif init callback
+ */
+static err_t pppifNetifInit(struct netif *netif)
+{
+	netif->name[0] = 'p';
+	netif->name[1] = 'p';
+	netif->output = pppifOutput;
+	netif->mtu = pppMTU((int)netif->state);
+	return ERR_OK;
+}
+
+
+/*
+ * sifup - Config the interface up and enable IP packets to pass.
+ */
+int sifup(int pd)
+{
+    PPPControl *pc = &pppControl[pd];
+    int st = 1;
+    
+    if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+        st = 0;
+        PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd));
+    } else {
+		netif_remove(&pc->netif);
+		if (netif_add(&pc->netif, &pc->addrs.our_ipaddr, &pc->addrs.netmask, &pc->addrs.his_ipaddr, (void *)pd, pppifNetifInit, ip_input)) {
+        		pc->if_up = 1;
+        		pc->errCode = PPPERR_NONE;
+
+			PPPDEBUG((LOG_DEBUG, "sifup: unit %d: linkStatusCB=%lx errCode=%d\n", pd, pc->linkStatusCB, pc->errCode));
+			if(pc->linkStatusCB)
+				pc->linkStatusCB(pc->linkStatusCtx, pc->errCode, &pc->addrs);
+		} else {
+        	st = 0;
+        	PPPDEBUG((LOG_ERR, "sifup[%d]: netif_add failed\n", pd));
+		}
+    }
+
+    return st;
+}
+
+/*
+ * sifnpmode - Set the mode for handling packets for a given NP.
+ */
+int sifnpmode(int u, int proto, enum NPmode mode)
+{
+	(void)u;
+	(void)proto;
+	(void)mode;
+    return 0;
+}
+
+/*
+ * sifdown - Config the interface down and disable IP.
+ */
+int sifdown(int pd)
+{
+    PPPControl *pc = &pppControl[pd];
+    int st = 1;
+    
+    if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+        st = 0;
+        PPPDEBUG((LOG_WARNING, "sifdown[%d]: bad parms\n", pd));
+    } else {
+        pc->if_up = 0;
+	netif_remove(&pc->netif);
+	PPPDEBUG((LOG_DEBUG, "sifdown: unit %d: linkStatusCB=%lx errCode=%d\n", pd, pc->linkStatusCB, pc->errCode));
+	if(pc->linkStatusCB)
+		pc->linkStatusCB(pc->linkStatusCtx, PPPERR_CONNECT, NULL);
+	}
+    return st;
+}
+
+/*
+ * sifaddr - Config the interface IP addresses and netmask.
+ */
+int sifaddr(
+    int pd,             /* Interface unit ??? */
+    u32_t o,        /* Our IP address ??? */
+    u32_t h,        /* His IP address ??? */
+    u32_t m,        /* IP subnet mask ??? */
+    u32_t ns1,      /* Primary DNS */
+    u32_t ns2       /* Secondary DNS */
+)
+{
+    PPPControl *pc = &pppControl[pd];
+    int st = 1;
+    
+    if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+        st = 0;
+        PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd));
+    } else {
+		memcpy(&pc->addrs.our_ipaddr, &o, sizeof(o));
+		memcpy(&pc->addrs.his_ipaddr, &h, sizeof(h));
+		memcpy(&pc->addrs.netmask, &m, sizeof(m));
+		memcpy(&pc->addrs.dns1, &ns1, sizeof(ns1));
+		memcpy(&pc->addrs.dns2, &ns2, sizeof(ns2));
+    }
+    return st;
+}
+
+/*
+ * cifaddr - Clear the interface IP addresses, and delete routes
+ * through the interface if possible.
+ */
+int cifaddr(
+    int pd,         /* Interface unit ??? */
+    u32_t o,    /* Our IP address ??? */
+    u32_t h     /* IP broadcast address ??? */
+)
+{
+    PPPControl *pc = &pppControl[pd];
+    int st = 1;
+    
+	(void)o;
+	(void)h;
+    if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+        st = 0;
+        PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd));
+    } else {
+		IP4_ADDR(&pc->addrs.our_ipaddr, 0,0,0,0);
+		IP4_ADDR(&pc->addrs.his_ipaddr, 0,0,0,0);
+		IP4_ADDR(&pc->addrs.netmask, 255,255,255,0);
+		IP4_ADDR(&pc->addrs.dns1, 0,0,0,0);
+		IP4_ADDR(&pc->addrs.dns2, 0,0,0,0);
+    }
+    return st;
+}
+
+/*
+ * sifdefaultroute - assign a default route through the address given.
+ */
+int sifdefaultroute(int pd, u32_t l, u32_t g)
+{
+    PPPControl *pc = &pppControl[pd];
+    int st = 1;
+    
+	(void)l;
+	(void)g;
+    if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+        st = 0;
+        PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd));
+    } else {
+		netif_set_default(&pc->netif);
+    }
+
+    /* TODO: check how PPP handled the netMask, previously not set by ipSetDefault */
+
+    return st;
+}
+
+/*
+ * cifdefaultroute - delete a default route through the address given.
+ */
+int cifdefaultroute(int pd, u32_t l, u32_t g)
+{
+    PPPControl *pc = &pppControl[pd];
+    int st = 1;
+    
+	(void)l;
+	(void)g;
+    if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
+        st = 0;
+        PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd));
+    } else {
+		netif_set_default(NULL);
+    }
+
+    return st;
+}
+
+void
+pppMainWakeup(int pd)
+{
+	PPPDEBUG((LOG_DEBUG, "pppMainWakeup: unit %d\n", pd));
+	sio_read_abort(pppControl[pd].fd);
+}
+
+/* these callbacks are necessary because lcp_* functions
+   must be called in the same context as pppInput(),
+   namely the tcpip_thread(), essentially because
+   they manipulate timeouts which are thread-private
+*/
+
+static void
+pppStartCB(void *arg)
+{
+    int pd = (int)arg;
+
+	PPPDEBUG((LOG_DEBUG, "pppStartCB: unit %d\n", pd));
+    lcp_lowerup(pd);
+    lcp_open(pd);      /* Start protocol */
+}
+
+static void
+pppStopCB(void *arg)
+{
+    int pd = (int)arg;
+
+	PPPDEBUG((LOG_DEBUG, "pppStopCB: unit %d\n", pd));
+    lcp_close(pd, "User request");
+}
+
+static void
+pppHupCB(void *arg)
+{
+    int pd = (int)arg;
+
+	PPPDEBUG((LOG_DEBUG, "pppHupCB: unit %d\n", pd));
+    lcp_lowerdown(pd);
+    link_terminated(pd);
+}
+/**********************************/
+/*** LOCAL FUNCTION DEFINITIONS ***/
+/**********************************/
+/* The main PPP process function.  This implements the state machine according
+ * to section 4 of RFC 1661: The Point-To-Point Protocol. */
+static void pppMain(void *arg)
+{
+    int pd = (int)arg;
+    struct pbuf *p;
+    PPPControl* pc;
+
+    pc = &pppControl[pd];
+
+    p = pbuf_alloc(PBUF_RAW, PPP_MRU+PPP_HDRLEN, PBUF_RAM);
+    if(!p) {
+		LWIP_ASSERT("p != NULL", p);
+		pc->errCode = PPPERR_ALLOC;
+		goto out;
+    }
+
+    /*
+     * Start the connection and handle incoming events (packet or timeout).
+     */
+	PPPDEBUG((LOG_INFO, "pppMain: unit %d: Connecting\n", pd));
+    tcpip_callback(pppStartCB, arg);
+    while (lcp_phase[pd] != PHASE_DEAD) {
+        if (pc->kill_link) {
+	    	PPPDEBUG((LOG_DEBUG, "pppMainWakeup: unit %d kill_link -> pppStopCB\n", pd));
+		pc->errCode = PPPERR_USER;
+		/* This will leave us at PHASE_DEAD. */
+    		tcpip_callback(pppStopCB, arg);
+		pc->kill_link = 0;
+        }
+        else if (pc->sig_hup) {
+	    	PPPDEBUG((LOG_DEBUG, "pppMainWakeup: unit %d sig_hup -> pppHupCB\n", pd));
+		pc->sig_hup = 0;
+    		tcpip_callback(pppHupCB, arg);
+        } else {
+		int c = sio_read(pc->fd, p->payload, p->len);
+		if(c > 0) {
+			pppInProc(pd, p->payload, c);
+		} else {
+		    PPPDEBUG((LOG_DEBUG, "pppMainWakeup: unit %d sio_read len=%d returned %d\n", pd, p->len, c));
+		    sys_msleep(1); /* give other tasks a chance to run */
+		}
+        }
+    }
+	PPPDEBUG((LOG_INFO, "pppMain: unit %d: PHASE_DEAD\n", pd));
+    pbuf_free(p);
+
+out:
+	PPPDEBUG((LOG_DEBUG, "pppMain: unit %d: linkStatusCB=%lx errCode=%d\n", pd, pc->linkStatusCB, pc->errCode));
+    if(pc->linkStatusCB)
+	    pc->linkStatusCB(pc->linkStatusCtx, pc->errCode ? pc->errCode : PPPERR_PROTOCOL, NULL);
+
+    pc->openFlag = 0;
+}
+
+static struct pbuf *pppSingleBuf(struct pbuf *p)
+{
+	struct pbuf *q, *b;
+	u_char *pl;
+
+	if(p->tot_len == p->len)
+		return p;
+
+	q = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM);
+	if(!q) {
+		PPPDEBUG((LOG_ERR,
+                        "pppSingleBuf: unable to alloc new buf (%d)\n", p->tot_len));
+		return p; /* live dangerously */
+	}
+
+	for(b = p, pl = q->payload; b != NULL; b = b->next) {
+		memcpy(pl, b->payload, b->len);
+		pl += b->len;
+	}
+
+	pbuf_free(p);
+
+	return q;
+}
+
+struct pppInputHeader {
+	int unit;
+	u16_t proto;
+};
+
+/*
+ * Pass the processed input packet to the appropriate handler.
+ * This function and all handlers run in the context of the tcpip_thread
+ */
+static void pppInput(void *arg)
+{
+	struct pbuf *nb = (struct pbuf *)arg;
+    u16_t protocol;
+    int pd;
+
+	pd = ((struct pppInputHeader *)nb->payload)->unit;
+	protocol = ((struct pppInputHeader *)nb->payload)->proto;
+
+    pbuf_header(nb, -(int)sizeof(struct pppInputHeader));
+
+#if LINK_STATS
+    lwip_stats.link.recv++;
+#endif /* LINK_STATS */
+
+    /*
+     * Toss all non-LCP packets unless LCP is OPEN.
+     * Until we get past the authentication phase, toss all packets
+     * except LCP, LQR and authentication packets.
+     */
+    if((lcp_phase[pd] <= PHASE_AUTHENTICATE) && (protocol != PPP_LCP)) {
+	    if(!((protocol == PPP_LQR) || (protocol == PPP_PAP) || (protocol == PPP_CHAP)) ||
+			(lcp_phase[pd] != PHASE_AUTHENTICATE)) {
+		PPPDEBUG((LOG_INFO, "pppInput: discarding proto 0x%04X in phase %d\n", protocol, lcp_phase[pd]));
+		goto drop;
+	    }
+    }
+
+    switch(protocol) {
+    case PPP_VJC_COMP:      /* VJ compressed TCP */
+#if VJ_SUPPORT > 0
+        PPPDEBUG((LOG_INFO, "pppInput[%d]: vj_comp in pbuf len=%d\n", pd, nb->len));
+        /*
+         * Clip off the VJ header and prepend the rebuilt TCP/IP header and
+         * pass the result to IP.
+         */
+        if (vj_uncompress_tcp(&nb, &pppControl[pd].vjComp) >= 0) {
+            pppControl[pd].netif.input(nb, &pppControl[pd].netif);
+			return;
+        }
+	/* Something's wrong so drop it. */
+	PPPDEBUG((LOG_WARNING, "pppInput[%d]: Dropping VJ compressed\n", pd));
+#else
+        /* No handler for this protocol so drop the packet. */
+        PPPDEBUG((LOG_INFO, "pppInput[%d]: drop VJ Comp in %d:%s\n", pd, nb->len, nb->payload));
+#endif /* VJ_SUPPORT > 0 */
+	break;
+    case PPP_VJC_UNCOMP:    /* VJ uncompressed TCP */
+#if VJ_SUPPORT > 0
+        PPPDEBUG((LOG_INFO, "pppInput[%d]: vj_un in pbuf len=%d\n", pd, nb->len));
+        /*
+         * Process the TCP/IP header for VJ header compression and then pass
+         * the packet to IP.
+         */
+        if (vj_uncompress_uncomp(nb, &pppControl[pd].vjComp) >= 0) {
+            pppControl[pd].netif.input(nb, &pppControl[pd].netif);
+			return;
+        }
+	/* Something's wrong so drop it. */
+	PPPDEBUG((LOG_WARNING, "pppInput[%d]: Dropping VJ uncompressed\n", pd));
+#else
+        /* No handler for this protocol so drop the packet. */
+        PPPDEBUG((LOG_INFO,
+                    "pppInput[%d]: drop VJ UnComp in %d:.*H\n", 
+                    pd, nb->len, LWIP_MIN(nb->len * 2, 40), nb->payload));
+#endif /* VJ_SUPPORT > 0 */
+	break;
+    case PPP_IP:            /* Internet Protocol */
+        PPPDEBUG((LOG_INFO, "pppInput[%d]: ip in pbuf len=%d\n", pd, nb->len));
+        pppControl[pd].netif.input(nb, &pppControl[pd].netif);
+		return;
+    default:
+	{
+		struct protent *protp;
+		int i;
+
+		/*
+		 * Upcall the proper protocol input routine.
+		 */
+		for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) {
+			if (protp->protocol == protocol && protp->enabled_flag) {
+				PPPDEBUG((LOG_INFO, "pppInput[%d]: %s len=%d\n", pd, protp->name, nb->len));
+				nb = pppSingleBuf(nb);
+				(*protp->input)(pd, nb->payload, nb->len);
+				goto out;
+			}
+		}
+
+		/* No handler for this protocol so reject the packet. */
+		PPPDEBUG((LOG_INFO, "pppInput[%d]: rejecting unsupported proto 0x%04X len=%d\n", pd, protocol, nb->len));
+		pbuf_header(nb, sizeof(protocol));
+#if BYTE_ORDER == LITTLE_ENDIAN
+		protocol = htons(protocol);
+		memcpy(nb->payload, &protocol, sizeof(protocol));
+#endif
+		lcp_sprotrej(pd, nb->payload, nb->len);
+	}
+	break;
+    }
+
+drop:
+#if LINK_STATS
+    lwip_stats.link.drop++;
+#endif
+
+out:
+    pbuf_free(nb);
+    return;
+}
+
+
+/*
+ * Drop the input packet.
+ */
+static void pppDrop(PPPControl *pc)
+{
+    if (pc->inHead != NULL) {
+#if 0	    
+        PPPDEBUG((LOG_INFO, "pppDrop: %d:%.*H\n", pc->inHead->len, min(60, pc->inHead->len * 2), pc->inHead->payload));
+#endif	
+        PPPDEBUG((LOG_INFO, "pppDrop: pbuf len=%d\n", pc->inHead->len));
+	if (pc->inTail && (pc->inTail != pc->inHead))
+	    pbuf_free(pc->inTail);
+        pbuf_free(pc->inHead);
+        pc->inHead = NULL;
+        pc->inTail = NULL;
+    }
+#if VJ_SUPPORT > 0
+    vj_uncompress_err(&pc->vjComp);
+#endif
+
+#if LINK_STATS
+    lwip_stats.link.drop++;
+#endif /* LINK_STATS */
+}
+
+
+/*
+ * Process a received octet string.
+ */
+static void pppInProc(int pd, u_char *s, int l)
+{
+    PPPControl *pc = &pppControl[pd];
+    struct pbuf *nextNBuf;
+    u_char curChar;
+
+    PPPDEBUG((LOG_DEBUG, "pppInProc[%d]: got %d bytes\n", pd, l));
+    while (l-- > 0) {
+        curChar = *s++;
+        
+        /* Handle special characters. */
+        if (ESCAPE_P(pc->inACCM, curChar)) {
+            /* Check for escape sequences. */
+            /* XXX Note that this does not handle an escaped 0x5d character which
+             * would appear as an escape character.  Since this is an ASCII ']'
+             * and there is no reason that I know of to escape it, I won't complicate
+             * the code to handle this case. GLL */
+            if (curChar == PPP_ESCAPE)
+                pc->inEscaped = 1;
+            /* Check for the flag character. */
+            else if (curChar == PPP_FLAG) {
+                /* If this is just an extra flag character, ignore it. */
+                if (pc->inState <= PDADDRESS)
+                    ;
+                /* If we haven't received the packet header, drop what has come in. */
+                else if (pc->inState < PDDATA) {
+                    PPPDEBUG((LOG_WARNING,
+                                "pppInProc[%d]: Dropping incomplete packet %d\n", 
+                                pd, pc->inState));
+#if LINK_STATS
+					lwip_stats.link.lenerr++;
+#endif
+                    pppDrop(pc);
+                }
+                /* If the fcs is invalid, drop the packet. */
+                else if (pc->inFCS != PPP_GOODFCS) {
+                    PPPDEBUG((LOG_INFO,
+                                "pppInProc[%d]: Dropping bad fcs 0x%04X proto=0x%04X\n", 
+                                pd, pc->inFCS, pc->inProtocol));
+#if LINK_STATS
+					lwip_stats.link.chkerr++;
+#endif
+                    pppDrop(pc);
+                }
+                /* Otherwise it's a good packet so pass it on. */
+                else {
+                    
+                    /* Trim off the checksum. */
+		    if(pc->inTail->len >= 2) {
+			pc->inTail->len -= 2;
+
+			pc->inTail->tot_len = pc->inTail->len;
+			if (pc->inTail != pc->inHead) {
+			    pbuf_cat(pc->inHead, pc->inTail);
+			}
+		    } else {
+			pc->inTail->tot_len = pc->inTail->len;
+			if (pc->inTail != pc->inHead) {
+			    pbuf_cat(pc->inHead, pc->inTail);
+			}
+
+			pbuf_realloc(pc->inHead, pc->inHead->tot_len - 2);
+		    }
+
+                    /* Dispatch the packet thereby consuming it. */
+		    if(tcpip_callback(pppInput, pc->inHead) != ERR_OK) {
+                    	PPPDEBUG((LOG_ERR,
+				    "pppInProc[%d]: tcpip_callback() failed, dropping packet\n", pd));
+			pbuf_free(pc->inHead);
+#if LINK_STATS
+			lwip_stats.link.drop++;
+#endif
+		    }
+                    pc->inHead = NULL;
+                    pc->inTail = NULL;
+                }
+                    
+                /* Prepare for a new packet. */
+                pc->inFCS = PPP_INITFCS;
+                pc->inState = PDADDRESS;
+                pc->inEscaped = 0;
+            }
+            /* Other characters are usually control characters that may have
+             * been inserted by the physical layer so here we just drop them. */
+            else {
+                PPPDEBUG((LOG_WARNING,
+                            "pppInProc[%d]: Dropping ACCM char <%d>\n", pd, curChar));
+            }
+        }
+        /* Process other characters. */
+        else {
+            /* Unencode escaped characters. */
+            if (pc->inEscaped) {
+                pc->inEscaped = 0;
+                curChar ^= PPP_TRANS;
+            }
+            
+            /* Process character relative to current state. */
+            switch(pc->inState) {
+            case PDIDLE:                    /* Idle state - waiting. */
+                /* Drop the character if it's not 0xff
+                 * we would have processed a flag character above. */
+                if (curChar != PPP_ALLSTATIONS) {
+                	break;
+				}
+
+				/* Fall through */
+            case PDSTART:                   /* Process start flag. */
+                /* Prepare for a new packet. */
+                pc->inFCS = PPP_INITFCS;
+
+				/* Fall through */
+            case PDADDRESS:                 /* Process address field. */
+                if (curChar == PPP_ALLSTATIONS) {
+                    pc->inState = PDCONTROL;
+                    break;
+                }
+                /* Else assume compressed address and control fields so
+                 * fall through to get the protocol... */
+            case PDCONTROL:                 /* Process control field. */
+                /* If we don't get a valid control code, restart. */
+                if (curChar == PPP_UI) {
+                    pc->inState = PDPROTOCOL1;
+                	break;
+                }
+#if 0
+                else {
+                    PPPDEBUG((LOG_WARNING,
+                                "pppInProc[%d]: Invalid control <%d>\n", pd, curChar));
+                    pc->inState = PDSTART;
+                }
+#endif
+            case PDPROTOCOL1:               /* Process protocol field 1. */
+                /* If the lower bit is set, this is the end of the protocol
+                 * field. */
+                if (curChar & 1) {
+                    pc->inProtocol = curChar;
+                    pc->inState = PDDATA;
+                }
+                else {
+                    pc->inProtocol = (u_int)curChar << 8;
+                    pc->inState = PDPROTOCOL2;
+                }
+                break;
+            case PDPROTOCOL2:               /* Process protocol field 2. */
+                pc->inProtocol |= curChar;
+                pc->inState = PDDATA;
+                break;
+            case PDDATA:                    /* Process data byte. */
+                /* Make space to receive processed data. */
+                if (pc->inTail == NULL || pc->inTail->len == PBUF_POOL_BUFSIZE) {
+		    if(pc->inTail) {
+			pc->inTail->tot_len = pc->inTail->len;
+			if (pc->inTail != pc->inHead) {
+			    pbuf_cat(pc->inHead, pc->inTail);
+			}
+		    }
+                    /* If we haven't started a packet, we need a packet header. */
+                    nextNBuf = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL);
+                    if (nextNBuf == NULL) {
+                        /* No free buffers.  Drop the input packet and let the
+                         * higher layers deal with it.  Continue processing
+                         * the received pbuf chain in case a new packet starts. */
+                        PPPDEBUG((LOG_ERR, "pppInProc[%d]: NO FREE MBUFS!\n", pd));
+#if LINK_STATS
+						lwip_stats.link.memerr++;
+#endif /* LINK_STATS */
+                        pppDrop(pc);
+                        pc->inState = PDSTART;  /* Wait for flag sequence. */
+			break;
+                    }
+		    if (pc->inHead == NULL) {
+			struct pppInputHeader *pih = nextNBuf->payload;
+
+			pih->unit = pd;
+			pih->proto = pc->inProtocol;
+
+			nextNBuf->len += sizeof(*pih);
+
+			pc->inHead = nextNBuf;
+		    }
+		    pc->inTail = nextNBuf;
+                }
+                /* Load character into buffer. */
+                ((u_char*)pc->inTail->payload)[pc->inTail->len++] = curChar;
+                break;
+            }
+
+            /* update the frame check sequence number. */
+            pc->inFCS = PPP_FCS(pc->inFCS, curChar);
+        }
+    }
+	avRandomize();
+}
+
+#endif /* PPP_SUPPORT */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/ppp.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/ppp.h
new file mode 100644
index 000000000..bd45a3c1d
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/ppp.h
@@ -0,0 +1,446 @@
+/*****************************************************************************
+* ppp.h - Network Point to Point Protocol header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1997 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 97-11-05 Guy Lancaster , Global Election Systems Inc.
+*	Original derived from BSD codes.
+*****************************************************************************/
+
+#ifndef PPP_H
+#define PPP_H
+
+#include "lwip/opt.h"
+
+#if PPP_SUPPORT > 0
+#include "lwip/sio.h"
+#include "lwip/api.h"
+#include "lwip/sockets.h"
+#include "lwip/stats.h"
+#include "lwip/mem.h"
+#include "lwip/tcpip.h"
+#include "lwip/netif.h"
+
+/*
+ * pppd.h - PPP daemon global declarations.
+ *
+ * Copyright (c) 1989 Carnegie Mellon University.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by Carnegie Mellon University.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ */
+/*
+ * ppp_defs.h - PPP definitions.
+ *
+ * Copyright (c) 1994 The Australian National University.
+ * All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, provided that the above copyright
+ * notice appears in all copies.  This software is provided without any
+ * warranty, express or implied. The Australian National University
+ * makes no representations about the suitability of this software for
+ * any purpose.
+ *
+ * IN NO EVENT SHALL THE AUSTRALIAN NATIONAL UNIVERSITY BE LIABLE TO ANY
+ * PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES
+ * ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF
+ * THE AUSTRALIAN NATIONAL UNIVERSITY HAVE BEEN ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * THE AUSTRALIAN NATIONAL UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE.  THE SOFTWARE PROVIDED HEREUNDER IS
+ * ON AN "AS IS" BASIS, AND THE AUSTRALIAN NATIONAL UNIVERSITY HAS NO
+ * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS,
+ * OR MODIFICATIONS.
+ */
+
+#define TIMEOUT(f, a, t)    sys_untimeout((f), (a)), sys_timeout((t)*1000, (f), (a))
+#define UNTIMEOUT(f, a)     sys_untimeout((f), (a))
+
+
+# ifndef __u_char_defined
+
+/* Type definitions for BSD code. */
+typedef unsigned long u_long;
+typedef unsigned int u_int;
+typedef unsigned short u_short;
+typedef unsigned char u_char;
+
+#endif
+
+/*
+ * Constants and structures defined by the internet system,
+ * Per RFC 790, September 1981, and numerous additions.
+ */
+
+/*
+ * The basic PPP frame.
+ */
+#define PPP_HDRLEN  4       /* octets for standard ppp header */
+#define PPP_FCSLEN  2       /* octets for FCS */
+
+
+/*
+ * Significant octet values.
+ */
+#define PPP_ALLSTATIONS 0xff    /* All-Stations broadcast address */
+#define PPP_UI          0x03    /* Unnumbered Information */
+#define PPP_FLAG        0x7e    /* Flag Sequence */
+#define PPP_ESCAPE      0x7d    /* Asynchronous Control Escape */
+#define PPP_TRANS       0x20    /* Asynchronous transparency modifier */
+
+/*
+ * Protocol field values.
+ */
+#define PPP_IP          0x21    /* Internet Protocol */
+#define PPP_AT          0x29    /* AppleTalk Protocol */
+#define PPP_VJC_COMP    0x2d    /* VJ compressed TCP */
+#define PPP_VJC_UNCOMP  0x2f    /* VJ uncompressed TCP */
+#define PPP_COMP        0xfd    /* compressed packet */
+#define PPP_IPCP        0x8021  /* IP Control Protocol */
+#define PPP_ATCP        0x8029  /* AppleTalk Control Protocol */
+#define PPP_CCP         0x80fd  /* Compression Control Protocol */
+#define PPP_LCP         0xc021  /* Link Control Protocol */
+#define PPP_PAP         0xc023  /* Password Authentication Protocol */
+#define PPP_LQR         0xc025  /* Link Quality Report protocol */
+#define PPP_CHAP        0xc223  /* Cryptographic Handshake Auth. Protocol */
+#define PPP_CBCP        0xc029  /* Callback Control Protocol */
+
+/*
+ * Values for FCS calculations.
+ */
+#define PPP_INITFCS 0xffff  /* Initial FCS value */
+#define PPP_GOODFCS 0xf0b8  /* Good final FCS value */
+#define PPP_FCS(fcs, c) (((fcs) >> 8) ^ fcstab[((fcs) ^ (c)) & 0xff])
+
+/*
+ * Extended asyncmap - allows any character to be escaped.
+ */
+typedef u_char  ext_accm[32];
+
+/*
+ * What to do with network protocol (NP) packets.
+ */
+enum NPmode {
+    NPMODE_PASS,        /* pass the packet through */
+    NPMODE_DROP,        /* silently drop the packet */
+    NPMODE_ERROR,       /* return an error */
+    NPMODE_QUEUE        /* save it up for later. */
+};
+
+/*
+ * Inline versions of get/put char/short/long.
+ * Pointer is advanced; we assume that both arguments
+ * are lvalues and will already be in registers.
+ * cp MUST be u_char *.
+ */
+#define GETCHAR(c, cp) { \
+    (c) = *(cp)++; \
+}
+#define PUTCHAR(c, cp) { \
+    *(cp)++ = (u_char) (c); \
+}
+
+
+#define GETSHORT(s, cp) { \
+    (s) = *(cp)++ << 8; \
+    (s) |= *(cp)++; \
+}
+#define PUTSHORT(s, cp) { \
+    *(cp)++ = (u_char) ((s) >> 8); \
+    *(cp)++ = (u_char) (s); \
+}
+
+#define GETLONG(l, cp) { \
+    (l) = *(cp)++ << 8; \
+    (l) |= *(cp)++; (l) <<= 8; \
+    (l) |= *(cp)++; (l) <<= 8; \
+    (l) |= *(cp)++; \
+}
+#define PUTLONG(l, cp) { \
+    *(cp)++ = (u_char) ((l) >> 24); \
+    *(cp)++ = (u_char) ((l) >> 16); \
+    *(cp)++ = (u_char) ((l) >> 8); \
+    *(cp)++ = (u_char) (l); \
+}
+
+
+#define INCPTR(n, cp)   ((cp) += (n))
+#define DECPTR(n, cp)   ((cp) -= (n))
+
+#define BCMP(s0, s1, l)     memcmp((u_char *)(s0), (u_char *)(s1), (l))
+#define BCOPY(s, d, l)      memcpy((d), (s), (l))
+#define BZERO(s, n)         memset(s, 0, n)
+#if PPP_DEBUG
+#define PRINTMSG(m, l)  { m[l] = '\0'; ppp_trace(LOG_INFO, "Remote message: %s\n", m); }
+#else
+#define PRINTMSG(m, l)
+#endif
+
+/*
+ * MAKEHEADER - Add PPP Header fields to a packet.
+ */
+#define MAKEHEADER(p, t) { \
+    PUTCHAR(PPP_ALLSTATIONS, p); \
+    PUTCHAR(PPP_UI, p); \
+    PUTSHORT(t, p); }
+
+/*************************
+*** PUBLIC DEFINITIONS ***
+*************************/
+
+/* Error codes. */
+#define PPPERR_NONE 0				/* No error. */
+#define PPPERR_PARAM -1				/* Invalid parameter. */
+#define PPPERR_OPEN -2				/* Unable to open PPP session. */
+#define PPPERR_DEVICE -3			/* Invalid I/O device for PPP. */
+#define PPPERR_ALLOC -4				/* Unable to allocate resources. */
+#define PPPERR_USER -5				/* User interrupt. */
+#define PPPERR_CONNECT -6			/* Connection lost. */
+#define PPPERR_AUTHFAIL -7			/* Failed authentication challenge. */
+#define PPPERR_PROTOCOL -8			/* Failed to meet protocol. */
+
+/*
+ * PPP IOCTL commands.
+ */
+/*
+ * Get the up status - 0 for down, non-zero for up.  The argument must
+ * point to an int.
+ */
+#define PPPCTLG_UPSTATUS 100	/* Get the up status - 0 down else up */
+#define PPPCTLS_ERRCODE 101		/* Set the error code */
+#define PPPCTLG_ERRCODE 102		/* Get the error code */
+#define	PPPCTLG_FD		103		/* Get the fd associated with the ppp */
+
+/************************
+*** PUBLIC DATA TYPES ***
+************************/
+
+/*
+ * The following struct gives the addresses of procedures to call
+ * for a particular protocol.
+ */
+struct protent {
+    u_short protocol;       /* PPP protocol number */
+    /* Initialization procedure */
+    void (*init) (int unit);
+    /* Process a received packet */
+    void (*input) (int unit, u_char *pkt, int len);
+    /* Process a received protocol-reject */
+    void (*protrej) (int unit);
+    /* Lower layer has come up */
+    void (*lowerup) (int unit);
+    /* Lower layer has gone down */
+    void (*lowerdown) (int unit);
+    /* Open the protocol */
+    void (*open) (int unit);
+    /* Close the protocol */
+    void (*close) (int unit, char *reason);
+#if 0
+    /* Print a packet in readable form */
+    int  (*printpkt) (u_char *pkt, int len,
+              void (*printer) (void *, char *, ...),
+              void *arg);
+    /* Process a received data packet */
+    void (*datainput) (int unit, u_char *pkt, int len);
+#endif
+    int  enabled_flag;      /* 0 iff protocol is disabled */
+    char *name;         /* Text name of protocol */
+#if 0
+    /* Check requested options, assign defaults */
+    void (*check_options) (u_long);
+    /* Configure interface for demand-dial */
+    int  (*demand_conf) (int unit);
+    /* Say whether to bring up link for this pkt */
+    int  (*active_pkt) (u_char *pkt, int len);
+#endif
+};
+
+/*
+ * The following structure records the time in seconds since
+ * the last NP packet was sent or received.
+ */
+struct ppp_idle {
+    u_short xmit_idle;      /* seconds since last NP packet sent */
+    u_short recv_idle;      /* seconds since last NP packet received */
+};
+
+struct ppp_settings {
+
+	u_int  disable_defaultip : 1;   /* Don't use hostname for default IP addrs */
+	u_int  auth_required : 1;      /* Peer is required to authenticate */
+	u_int  explicit_remote : 1;    /* remote_name specified with remotename opt */
+	u_int  refuse_pap : 1;         /* Don't wanna auth. ourselves with PAP */
+	u_int  refuse_chap : 1;        /* Don't wanna auth. ourselves with CHAP */
+	u_int  usehostname : 1;        /* Use hostname for our_name */
+	u_int  usepeerdns : 1;         /* Ask peer for DNS adds */
+
+	u_short idle_time_limit; /* Shut down link if idle for this long */
+	int  maxconnect;         /* Maximum connect time (seconds) */
+
+	char user[MAXNAMELEN + 1];/* Username for PAP */
+	char passwd[MAXSECRETLEN + 1];           /* Password for PAP, secret for CHAP */
+	char our_name[MAXNAMELEN + 1];         /* Our name for authentication purposes */
+	char remote_name[MAXNAMELEN + 1];      /* Peer's name for authentication */
+};
+
+struct ppp_addrs {
+    struct ip_addr our_ipaddr, his_ipaddr, netmask, dns1, dns2;
+};
+
+/*****************************
+*** PUBLIC DATA STRUCTURES ***
+*****************************/
+/* Buffers for outgoing packets. */
+extern u_char outpacket_buf[NUM_PPP][PPP_MRU+PPP_HDRLEN];
+
+extern struct ppp_settings ppp_settings;
+
+extern struct protent *ppp_protocols[];/* Table of pointers to supported protocols */
+
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+
+/* Initialize the PPP subsystem. */
+void pppInit(void);
+
+/* Warning: Using PPPAUTHTYPE_ANY might have security consequences.
+ * RFC 1994 says:
+ *
+ * In practice, within or associated with each PPP server, there is a
+ * database which associates "user" names with authentication
+ * information ("secrets").  It is not anticipated that a particular
+ * named user would be authenticated by multiple methods.  This would
+ * make the user vulnerable to attacks which negotiate the least secure
+ * method from among a set (such as PAP rather than CHAP).  If the same
+ * secret was used, PAP would reveal the secret to be used later with
+ * CHAP.
+ *
+ * Instead, for each user name there should be an indication of exactly
+ * one method used to authenticate that user name.  If a user needs to
+ * make use of different authentication methods under different
+ * circumstances, then distinct user names SHOULD be employed, each of
+ * which identifies exactly one authentication method.
+ *
+ */
+enum pppAuthType {
+    PPPAUTHTYPE_NONE,
+    PPPAUTHTYPE_ANY,
+    PPPAUTHTYPE_PAP,
+    PPPAUTHTYPE_CHAP
+};
+
+void pppSetAuth(enum pppAuthType authType, const char *user, const char *passwd);
+
+/*
+ * Open a new PPP connection using the given I/O device.
+ * This initializes the PPP control block but does not
+ * attempt to negotiate the LCP session.
+ * Return a new PPP connection descriptor on success or
+ * an error code (negative) on failure. 
+ */
+int pppOpen(sio_fd_t fd, void (*linkStatusCB)(void *ctx, int errCode, void *arg), void *linkStatusCtx);
+
+/*
+ * Close a PPP connection and release the descriptor. 
+ * Any outstanding packets in the queues are dropped.
+ * Return 0 on success, an error code on failure. 
+ */
+int pppClose(int pd);
+
+/*
+ * Indicate to the PPP process that the line has disconnected.
+ */
+void pppSigHUP(int pd);
+
+/*
+ * Get and set parameters for the given connection.
+ * Return 0 on success, an error code on failure. 
+ */
+int  pppIOCtl(int pd, int cmd, void *arg);
+
+/*
+ * Return the Maximum Transmission Unit for the given PPP connection.
+ */
+u_int pppMTU(int pd);
+
+/*
+ * Write n characters to a ppp link.
+ *	RETURN: >= 0 Number of characters written
+ *		 	 -1 Failed to write to device
+ */
+int pppWrite(int pd, const u_char *s, int n);
+
+void pppMainWakeup(int pd);
+
+/* Configure i/f transmit parameters */
+void ppp_send_config (int, int, u32_t, int, int);
+/* Set extended transmit ACCM */
+void ppp_set_xaccm (int, ext_accm *);
+/* Configure i/f receive parameters */
+void ppp_recv_config (int, int, u32_t, int, int);
+/* Find out how long link has been idle */
+int  get_idle_time (int, struct ppp_idle *);
+
+/* Configure VJ TCP header compression */
+int  sifvjcomp (int, int, int, int);
+/* Configure i/f down (for IP) */
+int  sifup (int);		
+/* Set mode for handling packets for proto */
+int  sifnpmode (int u, int proto, enum NPmode mode);
+/* Configure i/f down (for IP) */
+int  sifdown (int);	
+/* Configure IP addresses for i/f */
+int  sifaddr (int, u32_t, u32_t, u32_t, u32_t, u32_t);
+/* Reset i/f IP addresses */
+int  cifaddr (int, u32_t, u32_t);
+/* Create default route through i/f */
+int  sifdefaultroute (int, u32_t, u32_t);
+/* Delete default route through i/f */
+int  cifdefaultroute (int, u32_t, u32_t);
+
+/* Get appropriate netmask for address */
+u32_t GetMask (u32_t); 
+
+#endif /* PPP_SUPPORT */
+
+#endif /* PPP_H */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/pppdebug.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/pppdebug.h
new file mode 100644
index 000000000..e4cf25a39
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/pppdebug.h
@@ -0,0 +1,89 @@
+/*****************************************************************************
+* pppdebug.h - System debugging utilities.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* portions Copyright (c) 1998 Global Election Systems Inc.
+* portions Copyright (c) 2001 by Cognizant Pty Ltd.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY (please don't use tabs!)
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 98-07-29 Guy Lancaster , Global Election Systems Inc.
+*	Original.
+*
+*****************************************************************************
+*/
+#ifndef PPPDEBUG_H
+#define PPPDEBUG_H
+
+/************************
+*** PUBLIC DATA TYPES ***
+************************/
+/* Trace levels. */
+typedef enum {
+	LOG_CRITICAL = 0,
+	LOG_ERR = 1,
+	LOG_NOTICE = 2,
+	LOG_WARNING = 3,
+	LOG_INFO = 5,
+	LOG_DETAIL = 6,
+	LOG_DEBUG = 7
+} LogCodes;
+
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+/*
+ *	ppp_trace - a form of printf to send tracing information to stderr
+ */
+void ppp_trace(int level, const char *format,...);
+
+#if PPP_DEBUG > 0
+
+#define AUTHDEBUG(a) ppp_trace a
+#define IPCPDEBUG(a) ppp_trace a
+#define UPAPDEBUG(a) ppp_trace a
+#define LCPDEBUG(a) ppp_trace a
+#define FSMDEBUG(a) ppp_trace a
+#define CHAPDEBUG(a) ppp_trace a
+#define PPPDEBUG(a) ppp_trace a
+
+#define TRACELCP 1
+
+#else
+
+#define AUTHDEBUG(a)
+#define IPCPDEBUG(a)
+#define UPAPDEBUG(a)
+#define LCPDEBUG(a)
+#define FSMDEBUG(a)
+#define CHAPDEBUG(a)
+
+#define PPPDEBUG(a)
+
+#define TRACELCP 0
+
+#endif
+
+#endif /* PPPDEBUG_H */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/randm.c b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/randm.c
new file mode 100644
index 000000000..d4431dd8e
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/randm.c
@@ -0,0 +1,242 @@
+/*****************************************************************************
+* randm.c - Random number generator program file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* Copyright (c) 1998 by Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 98-06-03 Guy Lancaster , Global Election Systems Inc.
+*   Extracted from avos.
+*****************************************************************************/
+
+#include "ppp.h"
+#if PPP_SUPPORT > 0
+#include "md5.h"
+#include "randm.h"
+
+#include "pppdebug.h"
+
+
+#if MD5_SUPPORT>0   /* this module depends on MD5 */
+#define RANDPOOLSZ 16   /* Bytes stored in the pool of randomness. */
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+static char randPool[RANDPOOLSZ];   /* Pool of randomness. */
+static long randCount = 0;      /* Pseudo-random incrementer */
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ * Initialize the random number generator.
+ *
+ * Since this is to be called on power up, we don't have much
+ *  system randomess to work with.  Here all we use is the
+ *  real-time clock.  We'll accumulate more randomness as soon
+ *  as things start happening.
+ */
+void avRandomInit()
+{
+    avChurnRand(NULL, 0);
+}
+
+/*
+ * Churn the randomness pool on a random event.  Call this early and often
+ *  on random and semi-random system events to build randomness in time for
+ *  usage.  For randomly timed events, pass a null pointer and a zero length
+ *  and this will use the system timer and other sources to add randomness.
+ *  If new random data is available, pass a pointer to that and it will be
+ *  included.
+ *
+ * Ref: Applied Cryptography 2nd Ed. by Bruce Schneier p. 427
+ */
+void avChurnRand(char *randData, u32_t randLen)
+{
+    MD5_CTX md5;
+
+/*  ppp_trace(LOG_INFO, "churnRand: %u@%P\n", randLen, randData); */
+    MD5Init(&md5);
+    MD5Update(&md5, (u_char *)randPool, sizeof(randPool));
+    if (randData)
+        MD5Update(&md5, (u_char *)randData, randLen);
+    else {
+        struct {
+            /* INCLUDE fields for any system sources of randomness */
+            char foobar;
+        } sysData;
+
+        /* Load sysData fields here. */
+        ;
+        MD5Update(&md5, (u_char *)&sysData, sizeof(sysData));
+    }
+    MD5Final((u_char *)randPool, &md5);
+/*  ppp_trace(LOG_INFO, "churnRand: -> 0\n"); */
+}
+
+/*
+ * Use the random pool to generate random data.  This degrades to pseudo
+ *  random when used faster than randomness is supplied using churnRand().
+ * Note: It's important that there be sufficient randomness in randPool
+ *  before this is called for otherwise the range of the result may be
+ *  narrow enough to make a search feasible.
+ *
+ * Ref: Applied Cryptography 2nd Ed. by Bruce Schneier p. 427
+ *
+ * XXX Why does he not just call churnRand() for each block?  Probably
+ *  so that you don't ever publish the seed which could possibly help
+ *  predict future values.
+ * XXX Why don't we preserve md5 between blocks and just update it with
+ *  randCount each time?  Probably there is a weakness but I wish that
+ *  it was documented.
+ */
+void avGenRand(char *buf, u32_t bufLen)
+{
+    MD5_CTX md5;
+    u_char tmp[16];
+    u32_t n;
+
+    while (bufLen > 0) {
+        n = LWIP_MIN(bufLen, RANDPOOLSZ);
+        MD5Init(&md5);
+        MD5Update(&md5, (u_char *)randPool, sizeof(randPool));
+        MD5Update(&md5, (u_char *)&randCount, sizeof(randCount));
+        MD5Final(tmp, &md5);
+        randCount++;
+        memcpy(buf, tmp, n);
+        buf += n;
+        bufLen -= n;
+    }
+}
+
+/*
+ * Return a new random number.
+ */
+u32_t avRandom()
+{
+    u32_t newRand;
+
+    avGenRand((char *)&newRand, sizeof(newRand));
+
+    return newRand;
+}
+
+#else /* MD5_SUPPORT */
+
+
+/*****************************/
+/*** LOCAL DATA STRUCTURES ***/
+/*****************************/
+static int  avRandomized = 0;       /* Set when truely randomized. */
+static u32_t avRandomSeed = 0;      /* Seed used for random number generation. */
+
+
+/***********************************/
+/*** PUBLIC FUNCTION DEFINITIONS ***/
+/***********************************/
+/*
+ * Initialize the random number generator.
+ *
+ * Here we attempt to compute a random number seed but even if
+ * it isn't random, we'll randomize it later.
+ *
+ * The current method uses the fields from the real time clock,
+ * the idle process counter, the millisecond counter, and the
+ * hardware timer tick counter.  When this is invoked
+ * in startup(), then the idle counter and timer values may
+ * repeat after each boot and the real time clock may not be
+ * operational.  Thus we call it again on the first random
+ * event.
+ */
+void avRandomInit()
+{
+#if 0
+    /* Get a pointer into the last 4 bytes of clockBuf. */
+    u32_t *lptr1 = (u32_t *)((char *)&clockBuf[3]);
+
+    /*
+     * Initialize our seed using the real-time clock, the idle
+     * counter, the millisecond timer, and the hardware timer
+     * tick counter.  The real-time clock and the hardware
+     * tick counter are the best sources of randomness but
+     * since the tick counter is only 16 bit (and truncated
+     * at that), the idle counter and millisecond timer
+     * (which may be small values) are added to help
+     * randomize the lower 16 bits of the seed.
+     */
+    readClk();
+    avRandomSeed += *(u32_t *)clockBuf + *lptr1 + OSIdleCtr
+             + ppp_mtime() + ((u32_t)TM1 << 16) + TM1;
+#else
+    avRandomSeed += sys_jiffies(); /* XXX */
+#endif
+        
+    /* Initialize the Borland random number generator. */
+    srand((unsigned)avRandomSeed);
+}
+
+/*
+ * Randomize our random seed value.  Here we use the fact that
+ * this function is called at *truely random* times by the polling
+ * and network functions.  Here we only get 16 bits of new random
+ * value but we use the previous value to randomize the other 16
+ * bits.
+ */
+void avRandomize(void)
+{
+    static u32_t last_jiffies;
+
+    if (!avRandomized) {
+        avRandomized = !0;
+        avRandomInit();
+        /* The initialization function also updates the seed. */
+    } else {
+/*        avRandomSeed += (avRandomSeed << 16) + TM1; */
+    	avRandomSeed += (sys_jiffies() - last_jiffies); /* XXX */
+    }
+    last_jiffies = sys_jiffies();
+}
+
+/*
+ * Return a new random number.
+ * Here we use the Borland rand() function to supply a pseudo random
+ * number which we make truely random by combining it with our own
+ * seed which is randomized by truely random events. 
+ * Thus the numbers will be truely random unless there have been no
+ * operator or network events in which case it will be pseudo random
+ * seeded by the real time clock.
+ */
+u32_t avRandom()
+{
+    return ((((u32_t)rand() << 16) + rand()) + avRandomSeed);
+}
+
+
+
+#endif /* MD5_SUPPORT */
+#endif /* PPP_SUPPORT */
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/randm.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/randm.h
new file mode 100644
index 000000000..2563d8976
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/randm.h
@@ -0,0 +1,81 @@
+/*****************************************************************************
+* randm.h - Random number generator header file.
+*
+* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
+* Copyright (c) 1998 Global Election Systems Inc.
+*
+* The authors hereby grant permission to use, copy, modify, distribute,
+* and license this software and its documentation for any purpose, provided
+* that existing copyright notices are retained in all copies and that this
+* notice and the following disclaimer are included verbatim in any 
+* distributions. No written agreement, license, or royalty fee is required
+* for any of the authorized uses.
+*
+* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************
+* REVISION HISTORY
+*
+* 03-01-01 Marc Boucher 
+*   Ported to lwIP.
+* 98-05-29 Guy Lancaster , Global Election Systems Inc.
+*	Extracted from avos.
+*****************************************************************************/
+
+#ifndef RANDM_H
+#define RANDM_H
+
+/***********************
+*** PUBLIC FUNCTIONS ***
+***********************/
+/*
+ * Initialize the random number generator.
+ */
+void avRandomInit(void);
+
+/*
+ * Churn the randomness pool on a random event.  Call this early and often
+ *	on random and semi-random system events to build randomness in time for
+ *	usage.  For randomly timed events, pass a null pointer and a zero length
+ *	and this will use the system timer and other sources to add randomness.
+ *	If new random data is available, pass a pointer to that and it will be
+ *	included.
+ */
+void avChurnRand(char *randData, u32_t randLen);
+
+/*
+ * Randomize our random seed value.  To be called for truely random events
+ * such as user operations and network traffic.
+ */
+#if MD5_SUPPORT
+#define avRandomize()	avChurnRand(NULL, 0)
+#else
+void avRandomize(void);
+#endif
+
+/*
+ * Use the random pool to generate random data.  This degrades to pseudo
+ *	random when used faster than randomness is supplied using churnRand().
+ *	Thus it's important to make sure that the results of this are not
+ *	published directly because one could predict the next result to at
+ *	least some degree.  Also, it's important to get a good seed before
+ *	the first use.
+ */
+void avGenRand(char *buf, u32_t bufLen);
+
+/*
+ * Return a new random number.
+ */
+u32_t avRandom(void);
+
+
+#endif /* RANDM_H */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/vj.c b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/vj.c
new file mode 100644
index 000000000..2c11affe3
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/vj.c
@@ -0,0 +1,633 @@
+/*
+ * Routines to compress and uncompess tcp packets (for transmission
+ * over low speed serial lines.
+ *
+ * Copyright (c) 1989 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the University of California, Berkeley.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *	Van Jacobson (van@helios.ee.lbl.gov), Dec 31, 1989:
+ *	- Initial distribution.
+ *
+ * Modified June 1993 by Paul Mackerras, paulus@cs.anu.edu.au,
+ * so that the entire packet being decompressed doesn't have
+ * to be in contiguous memory (just the compressed header).
+ *
+ * Modified March 1998 by Guy Lancaster, glanca@gesn.com,
+ * for a 16 bit processor.
+ */
+
+#include 
+
+#include "ppp.h"
+#include "vj.h"
+#include "pppdebug.h"
+
+#if VJ_SUPPORT > 0
+
+#if LINK_STATS
+#define INCR(counter) ++comp->stats.counter
+#else
+#define INCR(counter)
+#endif
+
+#if defined(NO_CHAR_BITFIELDS)
+#define getip_hl(base)	((base).ip_hl_v&0xf)
+#define getth_off(base)	(((base).th_x2_off&0xf0)>>4)
+#else
+#define getip_hl(base)	((base).ip_hl)
+#define getth_off(base)	((base).th_off)
+#endif
+
+void vj_compress_init(struct vjcompress *comp)
+{
+	register u_int i;
+	register struct cstate *tstate = comp->tstate;
+	
+#if MAX_SLOTS == 0
+	memset((char *)comp, 0, sizeof(*comp));
+#endif
+	comp->maxSlotIndex = MAX_SLOTS - 1;
+	comp->compressSlot = 0;		/* Disable slot ID compression by default. */
+	for (i = MAX_SLOTS - 1; i > 0; --i) {
+		tstate[i].cs_id = i;
+		tstate[i].cs_next = &tstate[i - 1];
+	}
+	tstate[0].cs_next = &tstate[MAX_SLOTS - 1];
+	tstate[0].cs_id = 0;
+	comp->last_cs = &tstate[0];
+	comp->last_recv = 255;
+	comp->last_xmit = 255;
+	comp->flags = VJF_TOSS;
+}
+
+
+/* ENCODE encodes a number that is known to be non-zero.  ENCODEZ
+ * checks for zero (since zero has to be encoded in the long, 3 byte
+ * form).
+ */
+#define ENCODE(n) { \
+	if ((u_short)(n) >= 256) { \
+		*cp++ = 0; \
+		cp[1] = (n); \
+		cp[0] = (n) >> 8; \
+		cp += 2; \
+	} else { \
+		*cp++ = (n); \
+	} \
+}
+#define ENCODEZ(n) { \
+	if ((u_short)(n) >= 256 || (u_short)(n) == 0) { \
+		*cp++ = 0; \
+		cp[1] = (n); \
+		cp[0] = (n) >> 8; \
+		cp += 2; \
+	} else { \
+		*cp++ = (n); \
+	} \
+}
+
+#define DECODEL(f) { \
+	if (*cp == 0) {\
+		u32_t tmp = ntohl(f) + ((cp[1] << 8) | cp[2]); \
+		(f) = htonl(tmp); \
+		cp += 3; \
+	} else { \
+		u32_t tmp = ntohl(f) + (u32_t)*cp++; \
+		(f) = htonl(tmp); \
+	} \
+}
+
+#define DECODES(f) { \
+	if (*cp == 0) {\
+		u_short tmp = ntohs(f) + (((u_short)cp[1] << 8) | cp[2]); \
+		(f) = htons(tmp); \
+		cp += 3; \
+	} else { \
+		u_short tmp = ntohs(f) + (u_short)*cp++; \
+		(f) = htons(tmp); \
+	} \
+}
+
+#define DECODEU(f) { \
+	if (*cp == 0) {\
+		(f) = htons(((u_short)cp[1] << 8) | cp[2]); \
+		cp += 3; \
+	} else { \
+		(f) = htons((u_short)*cp++); \
+	} \
+}
+
+/*
+ * vj_compress_tcp - Attempt to do Van Jacobsen header compression on a
+ * packet.  This assumes that nb and comp are not null and that the first
+ * buffer of the chain contains a valid IP header.
+ * Return the VJ type code indicating whether or not the packet was
+ * compressed.
+ */
+u_int vj_compress_tcp(
+	struct vjcompress *comp,
+	struct pbuf *pb
+)
+{
+	register struct ip *ip = (struct ip *)pb->payload;
+	register struct cstate *cs = comp->last_cs->cs_next;
+	register u_short hlen = getip_hl(*ip);
+	register struct tcphdr *oth;
+	register struct tcphdr *th;
+	register u_short deltaS, deltaA;
+	register u_long deltaL;
+	register u_int changes = 0;
+	u_char new_seq[16];
+	register u_char *cp = new_seq;
+
+	/*	
+	 * Check that the packet is IP proto TCP.
+	 */
+	if (ip->ip_p != IPPROTO_TCP)
+		return (TYPE_IP);
+		
+	/*
+	 * Bail if this is an IP fragment or if the TCP packet isn't
+	 * `compressible' (i.e., ACK isn't set or some other control bit is
+	 * set).  
+	 */
+	if ((ip->ip_off & htons(0x3fff)) || pb->tot_len < 40)
+		return (TYPE_IP);
+	th = (struct tcphdr *)&((long *)ip)[hlen];
+	if ((th->th_flags & (TCP_SYN|TCP_FIN|TCP_RST|TCP_ACK)) != TCP_ACK)
+		return (TYPE_IP);
+		
+	/*
+	 * Packet is compressible -- we're going to send either a
+	 * COMPRESSED_TCP or UNCOMPRESSED_TCP packet.  Either way we need
+	 * to locate (or create) the connection state.  Special case the
+	 * most recently used connection since it's most likely to be used
+	 * again & we don't have to do any reordering if it's used.
+	 */
+	INCR(vjs_packets);
+	if (ip->ip_src.s_addr != cs->cs_ip.ip_src.s_addr 
+			|| ip->ip_dst.s_addr != cs->cs_ip.ip_dst.s_addr 
+			|| *(long *)th != ((long *)&cs->cs_ip)[getip_hl(cs->cs_ip)]) {
+		/*
+		 * Wasn't the first -- search for it.
+		 *
+		 * States are kept in a circularly linked list with
+		 * last_cs pointing to the end of the list.  The
+		 * list is kept in lru order by moving a state to the
+		 * head of the list whenever it is referenced.  Since
+		 * the list is short and, empirically, the connection
+		 * we want is almost always near the front, we locate
+		 * states via linear search.  If we don't find a state
+		 * for the datagram, the oldest state is (re-)used.
+		 */
+		register struct cstate *lcs;
+		register struct cstate *lastcs = comp->last_cs;
+		
+		do {
+			lcs = cs; cs = cs->cs_next;
+			INCR(vjs_searches);
+			if (ip->ip_src.s_addr == cs->cs_ip.ip_src.s_addr
+					&& ip->ip_dst.s_addr == cs->cs_ip.ip_dst.s_addr
+					&& *(long *)th == ((long *)&cs->cs_ip)[getip_hl(cs->cs_ip)])
+				goto found;
+		} while (cs != lastcs);
+		
+		/*
+		 * Didn't find it -- re-use oldest cstate.  Send an
+		 * uncompressed packet that tells the other side what
+		 * connection number we're using for this conversation.
+		 * Note that since the state list is circular, the oldest
+		 * state points to the newest and we only need to set
+		 * last_cs to update the lru linkage.
+		 */
+		INCR(vjs_misses);
+		comp->last_cs = lcs;
+		hlen += getth_off(*th);
+		hlen <<= 2;
+		/* Check that the IP/TCP headers are contained in the first buffer. */
+		if (hlen > pb->len)
+			return (TYPE_IP);
+		goto uncompressed;
+		
+		found:
+		/*
+		 * Found it -- move to the front on the connection list.
+		 */
+		if (cs == lastcs)
+			comp->last_cs = lcs;
+		else {
+			lcs->cs_next = cs->cs_next;
+			cs->cs_next = lastcs->cs_next;
+			lastcs->cs_next = cs;
+		}
+	}
+	
+	oth = (struct tcphdr *)&((long *)&cs->cs_ip)[hlen];
+	deltaS = hlen;
+	hlen += getth_off(*th);
+	hlen <<= 2;
+	/* Check that the IP/TCP headers are contained in the first buffer. */
+	if (hlen > pb->len) {
+		PPPDEBUG((LOG_INFO, "vj_compress_tcp: header len %d spans buffers\n", 
+					hlen));
+		return (TYPE_IP);
+	}
+	
+	/*
+	 * Make sure that only what we expect to change changed. The first
+	 * line of the `if' checks the IP protocol version, header length &
+	 * type of service.  The 2nd line checks the "Don't fragment" bit.
+	 * The 3rd line checks the time-to-live and protocol (the protocol
+	 * check is unnecessary but costless).  The 4th line checks the TCP
+	 * header length.  The 5th line checks IP options, if any.  The 6th
+	 * line checks TCP options, if any.  If any of these things are
+	 * different between the previous & current datagram, we send the
+	 * current datagram `uncompressed'.
+	 */
+	if (((u_short *)ip)[0] != ((u_short *)&cs->cs_ip)[0] 
+			|| ((u_short *)ip)[3] != ((u_short *)&cs->cs_ip)[3] 
+			|| ((u_short *)ip)[4] != ((u_short *)&cs->cs_ip)[4] 
+			|| getth_off(*th) != getth_off(*oth) 
+			|| (deltaS > 5 && BCMP(ip + 1, &cs->cs_ip + 1, (deltaS - 5) << 2)) 
+			|| (getth_off(*th) > 5 && BCMP(th + 1, oth + 1, (getth_off(*th) - 5) << 2)))
+		goto uncompressed;
+	
+	/*
+	 * Figure out which of the changing fields changed.  The
+	 * receiver expects changes in the order: urgent, window,
+	 * ack, seq (the order minimizes the number of temporaries
+	 * needed in this section of code).
+	 */
+	if (th->th_flags & TCP_URG) {
+		deltaS = ntohs(th->th_urp);
+		ENCODEZ(deltaS);
+		changes |= NEW_U;
+	} else if (th->th_urp != oth->th_urp)
+		/* argh! URG not set but urp changed -- a sensible
+		 * implementation should never do this but RFC793
+		 * doesn't prohibit the change so we have to deal
+		 * with it. */
+		goto uncompressed;
+	
+	if ((deltaS = (u_short)(ntohs(th->th_win) - ntohs(oth->th_win))) != 0) {
+		ENCODE(deltaS);
+		changes |= NEW_W;
+	}
+	
+	if ((deltaL = ntohl(th->th_ack) - ntohl(oth->th_ack)) != 0) {
+		if (deltaL > 0xffff)
+			goto uncompressed;
+		deltaA = (u_short)deltaL;
+		ENCODE(deltaA);
+		changes |= NEW_A;
+	}
+	
+	if ((deltaL = ntohl(th->th_seq) - ntohl(oth->th_seq)) != 0) {
+		if (deltaL > 0xffff)
+			goto uncompressed;
+		deltaS = (u_short)deltaL;
+		ENCODE(deltaS);
+		changes |= NEW_S;
+	}
+	
+	switch(changes) {
+	
+	case 0:
+		/*
+		 * Nothing changed. If this packet contains data and the
+		 * last one didn't, this is probably a data packet following
+		 * an ack (normal on an interactive connection) and we send
+		 * it compressed.  Otherwise it's probably a retransmit,
+		 * retransmitted ack or window probe.  Send it uncompressed
+		 * in case the other side missed the compressed version.
+		 */
+		if (ip->ip_len != cs->cs_ip.ip_len &&
+			ntohs(cs->cs_ip.ip_len) == hlen)
+		break;
+	
+	/* (fall through) */
+	
+	case SPECIAL_I:
+	case SPECIAL_D:
+		/*
+		 * actual changes match one of our special case encodings --
+		 * send packet uncompressed.
+		 */
+		goto uncompressed;
+	
+	case NEW_S|NEW_A:
+		if (deltaS == deltaA && deltaS == ntohs(cs->cs_ip.ip_len) - hlen) {
+			/* special case for echoed terminal traffic */
+			changes = SPECIAL_I;
+			cp = new_seq;
+		}
+		break;
+	
+	case NEW_S:
+		if (deltaS == ntohs(cs->cs_ip.ip_len) - hlen) {
+			/* special case for data xfer */
+			changes = SPECIAL_D;
+			cp = new_seq;
+		}
+		break;
+	}
+	
+	deltaS = (u_short)(ntohs(ip->ip_id) - ntohs(cs->cs_ip.ip_id));
+	if (deltaS != 1) {
+		ENCODEZ(deltaS);
+		changes |= NEW_I;
+	}
+	if (th->th_flags & TCP_PSH)
+	changes |= TCP_PUSH_BIT;
+	/*
+	 * Grab the cksum before we overwrite it below.  Then update our
+	 * state with this packet's header.
+	 */
+	deltaA = ntohs(th->th_sum);
+	BCOPY(ip, &cs->cs_ip, hlen);
+	
+	/*
+	 * We want to use the original packet as our compressed packet.
+	 * (cp - new_seq) is the number of bytes we need for compressed
+	 * sequence numbers.  In addition we need one byte for the change
+	 * mask, one for the connection id and two for the tcp checksum.
+	 * So, (cp - new_seq) + 4 bytes of header are needed.  hlen is how
+	 * many bytes of the original packet to toss so subtract the two to
+	 * get the new packet size.
+	 */
+	deltaS = (u_short)(cp - new_seq);
+	if (!comp->compressSlot || comp->last_xmit != cs->cs_id) {
+		comp->last_xmit = cs->cs_id;
+		hlen -= deltaS + 4;
+		pbuf_header(pb, -hlen);
+		cp = (u_char *)pb->payload;
+		*cp++ = changes | NEW_C;
+		*cp++ = cs->cs_id;
+	} else {
+		hlen -= deltaS + 3;
+		pbuf_header(pb, -hlen);
+		cp = (u_char *)pb->payload;
+		*cp++ = changes;
+	}
+	*cp++ = deltaA >> 8;
+	*cp++ = deltaA;
+	BCOPY(new_seq, cp, deltaS);
+	INCR(vjs_compressed);
+	return (TYPE_COMPRESSED_TCP);
+
+	/*
+	 * Update connection state cs & send uncompressed packet (that is,
+	 * a regular ip/tcp packet but with the 'conversation id' we hope
+	 * to use on future compressed packets in the protocol field).
+	 */
+uncompressed:
+	BCOPY(ip, &cs->cs_ip, hlen);
+	ip->ip_p = cs->cs_id;
+	comp->last_xmit = cs->cs_id;
+	return (TYPE_UNCOMPRESSED_TCP);
+}
+
+/*
+ * Called when we may have missed a packet.
+ */
+void vj_uncompress_err(struct vjcompress *comp)
+{
+    comp->flags |= VJF_TOSS;
+	INCR(vjs_errorin);
+}
+
+/*
+ * "Uncompress" a packet of type TYPE_UNCOMPRESSED_TCP.
+ * Return 0 on success, -1 on failure.
+ */
+int vj_uncompress_uncomp(
+	struct pbuf *nb,
+	struct vjcompress *comp
+)
+{
+	register u_int hlen;
+	register struct cstate *cs;
+	register struct ip *ip;
+	
+	ip = (struct ip *)nb->payload;
+	hlen = getip_hl(*ip) << 2;
+	if (ip->ip_p >= MAX_SLOTS
+			|| hlen + sizeof(struct tcphdr) > nb->len
+			|| (hlen += getth_off(*((struct tcphdr *)&((char *)ip)[hlen])) << 2)
+			    > nb->len
+			|| hlen > MAX_HDR) {
+		PPPDEBUG((LOG_INFO, "vj_uncompress_uncomp: bad cid=%d, hlen=%d buflen=%d\n", 
+					ip->ip_p, hlen, nb->len));
+		comp->flags |= VJF_TOSS;
+		INCR(vjs_errorin);
+		return -1;
+	}
+	cs = &comp->rstate[comp->last_recv = ip->ip_p];
+	comp->flags &=~ VJF_TOSS;
+	ip->ip_p = IPPROTO_TCP;
+	BCOPY(ip, &cs->cs_ip, hlen);
+	cs->cs_hlen = hlen;
+	INCR(vjs_uncompressedin);
+	return 0;
+}
+
+/*
+ * Uncompress a packet of type TYPE_COMPRESSED_TCP.
+ * The packet is composed of a buffer chain and the first buffer
+ * must contain an accurate chain length.
+ * The first buffer must include the entire compressed TCP/IP header. 
+ * This procedure replaces the compressed header with the uncompressed
+ * header and returns the length of the VJ header.
+ */
+int vj_uncompress_tcp(
+	struct pbuf **nb,
+	struct vjcompress *comp
+)
+{
+	u_char *cp;
+	struct tcphdr *th;
+	struct cstate *cs;
+	u_short *bp;
+	struct pbuf *n0 = *nb;
+	u32_t tmp;
+	u_int vjlen, hlen, changes;
+	
+	INCR(vjs_compressedin);
+	cp = (u_char *)n0->payload;
+	changes = *cp++;
+	if (changes & NEW_C) {
+		/* 
+		 * Make sure the state index is in range, then grab the state.
+		 * If we have a good state index, clear the 'discard' flag. 
+		 */
+		if (*cp >= MAX_SLOTS) {
+			PPPDEBUG((LOG_INFO, "vj_uncompress_tcp: bad cid=%d\n", *cp));
+			goto bad;
+		}
+		
+		comp->flags &=~ VJF_TOSS;
+		comp->last_recv = *cp++;
+	} else {
+		/* 
+		 * this packet has an implicit state index.  If we've
+		 * had a line error since the last time we got an
+		 * explicit state index, we have to toss the packet. 
+		 */
+		if (comp->flags & VJF_TOSS) {
+			PPPDEBUG((LOG_INFO, "vj_uncompress_tcp: tossing\n"));
+			INCR(vjs_tossed);
+			return (-1);
+		}
+	}
+	cs = &comp->rstate[comp->last_recv];
+	hlen = getip_hl(cs->cs_ip) << 2;
+	th = (struct tcphdr *)&((u_char *)&cs->cs_ip)[hlen];
+	th->th_sum = htons((*cp << 8) | cp[1]);
+	cp += 2;
+	if (changes & TCP_PUSH_BIT)
+		th->th_flags |= TCP_PSH;
+	else
+		th->th_flags &=~ TCP_PSH;
+	
+	switch (changes & SPECIALS_MASK) {
+	case SPECIAL_I:
+		{
+			register u32_t i = ntohs(cs->cs_ip.ip_len) - cs->cs_hlen;
+			/* some compilers can't nest inline assembler.. */
+			tmp = ntohl(th->th_ack) + i;
+			th->th_ack = htonl(tmp);
+			tmp = ntohl(th->th_seq) + i;
+			th->th_seq = htonl(tmp);
+		}
+		break;
+	
+	case SPECIAL_D:
+		/* some compilers can't nest inline assembler.. */
+		tmp = ntohl(th->th_seq) + ntohs(cs->cs_ip.ip_len) - cs->cs_hlen;
+		th->th_seq = htonl(tmp);
+		break;
+	
+	default:
+		if (changes & NEW_U) {
+			th->th_flags |= TCP_URG;
+			DECODEU(th->th_urp);
+		} else
+			th->th_flags &=~ TCP_URG;
+		if (changes & NEW_W)
+			DECODES(th->th_win);
+		if (changes & NEW_A)
+			DECODEL(th->th_ack);
+		if (changes & NEW_S)
+			DECODEL(th->th_seq);
+		break;
+	}
+	if (changes & NEW_I) {
+		DECODES(cs->cs_ip.ip_id);
+	} else {
+		cs->cs_ip.ip_id = ntohs(cs->cs_ip.ip_id) + 1;
+		cs->cs_ip.ip_id = htons(cs->cs_ip.ip_id);
+	}
+	
+	/*
+	 * At this point, cp points to the first byte of data in the
+	 * packet.  Fill in the IP total length and update the IP
+	 * header checksum.
+	 */
+	vjlen = (u_short)(cp - (u_char*)n0->payload);
+	if (n0->len < vjlen) {
+		/* 
+		 * We must have dropped some characters (crc should detect
+		 * this but the old slip framing won't) 
+		 */
+		PPPDEBUG((LOG_INFO, "vj_uncompress_tcp: head buffer %d too short %d\n", 
+				  n0->len, vjlen));
+		goto bad;
+	}
+	
+#if BYTE_ORDER == LITTLE_ENDIAN
+	tmp = n0->tot_len - vjlen + cs->cs_hlen;
+	cs->cs_ip.ip_len = htons(tmp);
+#else
+	cs->cs_ip.ip_len = htons(n0->tot_len - vjlen + cs->cs_hlen);
+#endif
+	
+	/* recompute the ip header checksum */
+	bp = (u_short *) &cs->cs_ip;
+	cs->cs_ip.ip_sum = 0;
+	for (tmp = 0; hlen > 0; hlen -= 2)
+		tmp += *bp++;
+	tmp = (tmp & 0xffff) + (tmp >> 16);
+	tmp = (tmp & 0xffff) + (tmp >> 16);
+	cs->cs_ip.ip_sum = (u_short)(~tmp);
+	
+	/* Remove the compressed header and prepend the uncompressed header. */
+	pbuf_header(n0, -vjlen);
+
+	if(MEM_ALIGN(n0->payload) != n0->payload) {
+		struct pbuf *np, *q;
+		u8_t *bufptr;
+
+		np = pbuf_alloc(PBUF_RAW, n0->len + cs->cs_hlen, PBUF_POOL);
+		if(!np) {
+			PPPDEBUG((LOG_WARNING, "vj_uncompress_tcp: realign failed\n"));
+			*nb = NULL;
+			goto bad;
+		}
+
+		pbuf_header(np, -cs->cs_hlen);
+
+		bufptr = n0->payload;
+		for(q = np; q != NULL; q = q->next) {
+			memcpy(q->payload, bufptr, q->len);
+			bufptr += q->len;
+		}
+
+		if(n0->next) {
+			pbuf_chain(np, n0->next);
+			pbuf_dechain(n0);
+		}
+		pbuf_free(n0);
+		n0 = np;
+	}
+
+	if(pbuf_header(n0, cs->cs_hlen)) {
+		struct pbuf *np;
+
+		LWIP_ASSERT("vj_uncompress_tcp: cs->cs_hlen <= PBUF_POOL_BUFSIZE", cs->cs_hlen <= PBUF_POOL_BUFSIZE);
+		np = pbuf_alloc(PBUF_RAW, cs->cs_hlen, PBUF_POOL);
+		if(!np) {
+			PPPDEBUG((LOG_WARNING, "vj_uncompress_tcp: prepend failed\n"));
+			*nb = NULL;
+			goto bad;
+		}
+		pbuf_cat(np, n0);
+		n0 = np;
+	}
+	LWIP_ASSERT("n0->len >= cs->cs_hlen", n0->len >= cs->cs_hlen);
+	memcpy(n0->payload, &cs->cs_ip, cs->cs_hlen);
+
+	*nb = n0;
+
+	return vjlen;
+	
+bad:
+	comp->flags |= VJF_TOSS;
+	INCR(vjs_errorin);
+	return (-1);
+}
+
+#endif
+
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/vj.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/vj.h
new file mode 100644
index 000000000..3765aa6aa
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/vj.h
@@ -0,0 +1,155 @@
+/*
+ * Definitions for tcp compression routines.
+ *
+ * $Id: vj.h,v 1.2 2006/08/29 18:53:47 wolti Exp $
+ *
+ * Copyright (c) 1989 Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the University of California, Berkeley.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *	Van Jacobson (van@helios.ee.lbl.gov), Dec 31, 1989:
+ *	- Initial distribution.
+ */
+
+#ifndef VJ_H
+#define VJ_H
+
+#include "vjbsdhdr.h"
+
+#define MAX_SLOTS	16			/* must be > 2 and < 256 */
+#define MAX_HDR		128
+
+/*
+ * Compressed packet format:
+ *
+ * The first octet contains the packet type (top 3 bits), TCP
+ * 'push' bit, and flags that indicate which of the 4 TCP sequence
+ * numbers have changed (bottom 5 bits).  The next octet is a
+ * conversation number that associates a saved IP/TCP header with
+ * the compressed packet.  The next two octets are the TCP checksum
+ * from the original datagram.  The next 0 to 15 octets are
+ * sequence number changes, one change per bit set in the header
+ * (there may be no changes and there are two special cases where
+ * the receiver implicitly knows what changed -- see below).
+ * 
+ * There are 5 numbers which can change (they are always inserted
+ * in the following order): TCP urgent pointer, window,
+ * acknowlegement, sequence number and IP ID.  (The urgent pointer
+ * is different from the others in that its value is sent, not the
+ * change in value.)  Since typical use of SLIP links is biased
+ * toward small packets (see comments on MTU/MSS below), changes
+ * use a variable length coding with one octet for numbers in the
+ * range 1 - 255 and 3 octets (0, MSB, LSB) for numbers in the
+ * range 256 - 65535 or 0.  (If the change in sequence number or
+ * ack is more than 65535, an uncompressed packet is sent.)
+ */
+
+/*
+ * Packet types (must not conflict with IP protocol version)
+ *
+ * The top nibble of the first octet is the packet type.  There are
+ * three possible types: IP (not proto TCP or tcp with one of the
+ * control flags set); uncompressed TCP (a normal IP/TCP packet but
+ * with the 8-bit protocol field replaced by an 8-bit connection id --
+ * this type of packet syncs the sender & receiver); and compressed
+ * TCP (described above).
+ *
+ * LSB of 4-bit field is TCP "PUSH" bit (a worthless anachronism) and
+ * is logically part of the 4-bit "changes" field that follows.  Top
+ * three bits are actual packet type.  For backward compatibility
+ * and in the interest of conserving bits, numbers are chosen so the
+ * IP protocol version number (4) which normally appears in this nibble
+ * means "IP packet".
+ */
+
+/* packet types */
+#define TYPE_IP 0x40
+#define TYPE_UNCOMPRESSED_TCP 0x70
+#define TYPE_COMPRESSED_TCP 0x80
+#define TYPE_ERROR 0x00
+
+/* Bits in first octet of compressed packet */
+#define NEW_C	0x40	/* flag bits for what changed in a packet */
+#define NEW_I	0x20
+#define NEW_S	0x08
+#define NEW_A	0x04
+#define NEW_W	0x02
+#define NEW_U	0x01
+
+/* reserved, special-case values of above */
+#define SPECIAL_I (NEW_S|NEW_W|NEW_U)		/* echoed interactive traffic */
+#define SPECIAL_D (NEW_S|NEW_A|NEW_W|NEW_U)	/* unidirectional data */
+#define SPECIALS_MASK (NEW_S|NEW_A|NEW_W|NEW_U)
+
+#define TCP_PUSH_BIT 0x10
+
+
+/*
+ * "state" data for each active tcp conversation on the wire.  This is
+ * basically a copy of the entire IP/TCP header from the last packet
+ * we saw from the conversation together with a small identifier
+ * the transmit & receive ends of the line use to locate saved header.
+ */
+struct cstate {
+    struct cstate *cs_next;	/* next most recently used state (xmit only) */
+    u_short cs_hlen;		/* size of hdr (receive only) */
+    u_char cs_id;			/* connection # associated with this state */
+    u_char cs_filler;
+    union {
+		char csu_hdr[MAX_HDR];
+		struct ip csu_ip;	/* ip/tcp hdr from most recent packet */
+    } vjcs_u;
+};
+#define cs_ip vjcs_u.csu_ip
+#define cs_hdr vjcs_u.csu_hdr
+
+
+struct vjstat {
+    unsigned long vjs_packets;			/* outbound packets */
+    unsigned long vjs_compressed;		/* outbound compressed packets */
+    unsigned long vjs_searches;			/* searches for connection state */
+    unsigned long vjs_misses;			/* times couldn't find conn. state */
+    unsigned long vjs_uncompressedin;	/* inbound uncompressed packets */
+    unsigned long vjs_compressedin;		/* inbound compressed packets */
+    unsigned long vjs_errorin;			/* inbound unknown type packets */
+    unsigned long vjs_tossed;			/* inbound packets tossed because of error */
+};
+
+/*
+ * all the state data for one serial line (we need one of these per line).
+ */
+struct vjcompress {
+    struct cstate *last_cs;	/* most recently used tstate */
+    u_char last_recv;		/* last rcvd conn. id */
+    u_char last_xmit;		/* last sent conn. id */
+    u_short flags;
+    u_char maxSlotIndex;
+    u_char compressSlot;	/* Flag indicating OK to compress slot ID. */
+#if LINK_STATS
+    struct vjstat stats;
+#endif
+    struct cstate tstate[MAX_SLOTS];	/* xmit connection states */
+    struct cstate rstate[MAX_SLOTS];	/* receive connection states */
+};
+
+/* flag values */
+#define VJF_TOSS 1U		/* tossing rcvd frames because of input err */
+
+extern void  vj_compress_init (struct vjcompress *comp);
+extern u_int vj_compress_tcp (struct vjcompress *comp, struct pbuf *pb);
+extern void  vj_uncompress_err (struct vjcompress *comp);
+extern int vj_uncompress_uncomp(struct pbuf *nb, struct vjcompress *comp);
+extern int vj_uncompress_tcp(struct pbuf **nb, struct vjcompress *comp);
+
+#endif /* VJ_H */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/vjbsdhdr.h b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/vjbsdhdr.h
new file mode 100644
index 000000000..a7d180c16
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/vjbsdhdr.h
@@ -0,0 +1,76 @@
+#ifndef VJBSDHDR_H
+#define VJBSDHDR_H
+
+#include "lwip/tcp.h"
+
+
+/*
+ * Structure of an internet header, naked of options.
+ *
+ * We declare ip_len and ip_off to be short, rather than u_short
+ * pragmatically since otherwise unsigned comparisons can result
+ * against negative integers quite easily, and fail in subtle ways.
+ */
+PACK_STRUCT_BEGIN
+struct ip
+{
+#if defined(NO_CHAR_BITFIELDS)
+	u_char ip_hl_v;	/* bug in GCC for mips means the bitfield stuff will sometimes break - so we use a char for both and get round it with macro's instead... */
+#else
+#if BYTE_ORDER == LITTLE_ENDIAN
+	unsigned ip_hl:4,				/* header length */
+		ip_v:4;						/* version */
+#elif BYTE_ORDER == BIG_ENDIAN 
+	unsigned ip_v:4,					/* version */
+		ip_hl:4;					/* header length */
+#else
+	COMPLAIN - NO BYTE ORDER SELECTED!
+#endif
+#endif
+	u_char	ip_tos;					/* type of service */
+	u_short	ip_len;					/* total length */
+	u_short	ip_id;					/* identification */
+	u_short	ip_off;					/* fragment offset field */
+#define	IP_DF 0x4000				/* dont fragment flag */
+#define	IP_MF 0x2000				/* more fragments flag */
+#define	IP_OFFMASK 0x1fff			/* mask for fragmenting bits */
+	u_char	ip_ttl;					/* time to live */
+	u_char	ip_p;					/* protocol */
+	u_short	ip_sum;					/* checksum */
+	struct	in_addr ip_src,ip_dst;	/* source and dest address */
+};
+PACK_STRUCT_END
+
+typedef u32_t tcp_seq;
+
+/*
+ * TCP header.
+ * Per RFC 793, September, 1981.
+ */
+PACK_STRUCT_BEGIN
+struct tcphdr  
+{
+	u_short	th_sport;		/* source port */
+	u_short	th_dport;		/* destination port */
+	tcp_seq	th_seq;			/* sequence number */
+	tcp_seq	th_ack;			/* acknowledgement number */
+#if defined(NO_CHAR_BITFIELDS)
+	u_char th_x2_off;
+#else
+#if BYTE_ORDER == LITTLE_ENDIAN
+	unsigned	th_x2:4,		/* (unused) */
+			th_off:4;		/* data offset */
+#endif
+#if BYTE_ORDER == BIG_ENDIAN 
+	unsigned	th_off:4,		/* data offset */
+			th_x2:4;		/* (unused) */
+#endif
+#endif
+	u_char	th_flags;
+	u_short	th_win;			/* window */
+	u_short	th_sum;			/* checksum */
+	u_short	th_urp;			/* urgent pointer */
+};
+PACK_STRUCT_END
+
+#endif /* VJBSDHDR_H */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/slipif.c b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/slipif.c
new file mode 100644
index 000000000..ba8510b0d
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwip/src/netif/slipif.c
@@ -0,0 +1,213 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. Neither the name of the Institute nor the names of its contributors 
+ *    may be used to endorse or promote products derived from this software 
+ *    without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
+ * SUCH DAMAGE. 
+ *
+ * This file is built upon the file: src/arch/rtxc/netif/sioslip.c
+ *
+ * Author: Magnus Ivarsson  
+ */
+
+/* 
+ * This is an arch independent SLIP netif. The specific serial hooks must be
+ * provided by another file. They are sio_open, sio_recv and sio_send
+ */
+
+#include "netif/slipif.h"
+#include "lwip/opt.h"
+#include "lwip/def.h"
+#include "lwip/pbuf.h"
+#include "lwip/sys.h"
+#include "lwip/stats.h"
+#include "lwip/sio.h"
+
+#define SLIP_END     0300
+#define SLIP_ESC     0333
+#define SLIP_ESC_END 0334
+#define SLIP_ESC_ESC 0335
+
+#define MAX_SIZE     1500
+
+/**
+ * Send a pbuf doing the necessary SLIP encapsulation
+ *
+ * Uses the serial layer's sio_send() 
+ */
+err_t
+slipif_output(struct netif *netif, struct pbuf *p, struct ip_addr *ipaddr)
+{
+  struct pbuf *q;
+  u16_t i;
+  u8_t c;
+
+  /* Send pbuf out on the serial I/O device. */
+  sio_send(SLIP_END, netif->state);
+
+  for (q = p; q != NULL; q = q->next) {
+    for (i = 0; i < q->len; i++) {
+      c = ((u8_t *)q->payload)[i];
+      switch (c) {
+      case SLIP_END:
+        sio_send(SLIP_ESC, netif->state);
+        sio_send(SLIP_ESC_END, netif->state);
+        break;
+      case SLIP_ESC:
+        sio_send(SLIP_ESC, netif->state);
+        sio_send(SLIP_ESC_ESC, netif->state);
+        break;
+      default:
+        sio_send(c, netif->state);
+        break;
+      }
+    }
+  }
+  sio_send(SLIP_END, netif->state);
+  return 0;
+}
+
+/**
+ * Handle the incoming SLIP stream character by character
+ *
+ * Poll the serial layer by calling sio_recv()
+ * 
+ * @return The IP packet when SLIP_END is received 
+ */
+static struct pbuf *
+slipif_input(struct netif *netif)
+{
+  u8_t c;
+  struct pbuf *p, *q;
+  u16_t recved;
+  u16_t i;
+
+  q = p = NULL;
+  recved = i = 0;
+  c = 0;
+
+  while (1) {
+    c = sio_recv(netif->state);
+    switch (c) {
+    case SLIP_END:
+      if (recved > 0) {
+        /* Received whole packet. */
+        pbuf_realloc(q, recved);
+        
+        LINK_STATS_INC(link.recv);
+        
+        LWIP_DEBUGF(SLIP_DEBUG, ("slipif: Got packet\n"));
+        return q;
+      }
+      break;
+
+    case SLIP_ESC:
+      c = sio_recv(netif->state);
+      switch (c) {
+      case SLIP_ESC_END:
+        c = SLIP_END;
+        break;
+      case SLIP_ESC_ESC:
+        c = SLIP_ESC;
+        break;
+      }
+      /* FALLTHROUGH */
+
+    default:
+      if (p == NULL) {
+        LWIP_DEBUGF(SLIP_DEBUG, ("slipif_input: alloc\n"));
+        p = pbuf_alloc(PBUF_LINK, PBUF_POOL_BUFSIZE, PBUF_POOL);
+
+        if (p == NULL) {
+          LINK_STATS_INC(link.drop);
+          LWIP_DEBUGF(SLIP_DEBUG, ("slipif_input: no new pbuf! (DROP)\n"));
+        }
+
+        if (q != NULL) {
+          pbuf_cat(q, p);
+        } else {
+          q = p;
+        }
+      }
+      if (p != NULL && recved < MAX_SIZE) {
+        ((u8_t *)p->payload)[i] = c;
+        recved++;
+        i++;
+        if (i >= p->len) {
+          i = 0;
+          if (p->next != NULL && p->next->len > 0)
+            p = p->next;
+          else
+            p = NULL;
+        }
+      }
+      break;
+    }
+
+  }
+  return NULL;
+}
+
+/**
+ * The SLIP input thread.
+ *
+ * Feed the IP layer with incoming packets
+ */
+static void
+slipif_loop(void *nf)
+{
+  struct pbuf *p;
+  struct netif *netif = (struct netif *)nf;
+
+  while (1) {
+    p = slipif_input(netif);
+    netif->input(p, netif);
+  }
+}
+
+/**
+ * SLIP netif initialization
+ *
+ * Call the arch specific sio_open and remember
+ * the opened device in the state field of the netif.
+ */
+err_t
+slipif_init(struct netif *netif)
+{
+
+  LWIP_DEBUGF(SLIP_DEBUG, ("slipif_init: netif->num=%"U16_F"\n", (u16_t)netif->num));
+
+  netif->name[0] = 's';
+  netif->name[1] = 'l';
+  netif->output = slipif_output;
+  netif->mtu = 1500;
+  netif->flags = NETIF_FLAG_POINTTOPOINT;
+
+  netif->state = sio_open(netif->num);
+  if (!netif->state)
+    return ERR_IF;
+
+  sys_thread_new(slipif_loop, netif, SLIPIF_THREAD_PRIO);
+  return ERR_OK;
+}
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/lwipopts.h b/20080212/Demo/lwIP_MCF5235_GCC/lwipopts.h
new file mode 100644
index 000000000..f759ea1ce
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/lwipopts.h
@@ -0,0 +1,182 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels 
+ * Modifications: Christian Walter 
+ */
+#ifndef __LWIPOPTS_H__
+#define __LWIPOPTS_H__
+
+/* ------------------------ Generic options ------------------------------- */
+#undef  LWIP_NOASSERT
+
+#define SYS_LIGHTWEIGHT_PROT    1
+#define TCPIP_THREAD_PRIO       3
+
+#define LWIP_DEBUG              1
+#define DBG_TYPES_ON            ( DBG_LEVEL_WARNING | DBG_LEVEL_SEVERE | DBG_LEVEL_SERIOUS )
+#define FEC_DEBUG               ( DBG_LEVEL_WARNING | DBG_ON )
+
+/* ------------------------ Memory options -------------------------------- */
+/* MEM_ALIGNMENT: should be set to the alignment of the CPU for which
+   lwIP is compiled. 4 byte alignment -> define MEM_ALIGNMENT to 4, 2
+   byte alignment -> define MEM_ALIGNMENT to 2. */
+#define MEM_ALIGNMENT           4
+
+/* MEM_SIZE: the size of the heap memory. If the application will send
+a lot of data that needs to be copied, this should be set high. */
+#define MEM_SIZE                2000
+
+/* MEMP_NUM_PBUF: the number of memp struct pbufs. If the application
+   sends a lot of data out of ROM (or other static memory), this
+   should be set high. */
+#define MEMP_NUM_PBUF           20
+/* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One
+   per active UDP "connection". */
+#define MEMP_NUM_UDP_PCB        4
+/* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP
+   connections. */
+#define MEMP_NUM_TCP_PCB        10
+/* MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP
+   connections. */
+#define MEMP_NUM_TCP_PCB_LISTEN 8
+/* MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP
+   segments. */
+#define MEMP_NUM_TCP_SEG        8
+/* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active
+   timeouts. */
+#define MEMP_NUM_SYS_TIMEOUT    3
+
+/* The following four are used only with the sequential API and can be
+   set to 0 if the application only will use the raw API. */
+/* MEMP_NUM_NETBUF: the number of struct netbufs. */
+#define MEMP_NUM_NETBUF         4
+/* MEMP_NUM_NETCONN: the number of struct netconns. */
+#define MEMP_NUM_NETCONN        4
+/* MEMP_NUM_APIMSG: the number of struct api_msg, used for
+   communication between the TCP/IP stack and the sequential
+   programs. */
+#define MEMP_NUM_API_MSG        8
+/* MEMP_NUM_TCPIPMSG: the number of struct tcpip_msg, which is used
+   for sequential API communication and incoming packets. Used in
+   src/api/tcpip.c. */
+#define MEMP_NUM_TCPIP_MSG      8
+
+/* These two control is reclaimer functions should be compiled
+   in. Should always be turned on (1). */
+#define MEM_RECLAIM             1
+#define MEMP_RECLAIM            1
+
+/* ---------- Pbuf options ---------- */
+/* PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */
+#define PBUF_POOL_SIZE          16
+
+/* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */
+#define PBUF_POOL_BUFSIZE       512
+
+/* PBUF_LINK_HLEN: the number of bytes that should be allocated for a
+   link level header. */
+#define PBUF_LINK_HLEN          16
+
+/* ------------------------ TCP options ----------------------------------- */
+#define LWIP_TCP                1
+#define TCP_TTL                 255
+
+/* Controls if TCP should queue segments that arrive out of
+   order. Define to 0 if your device is low on memory. */
+#define TCP_QUEUE_OOSEQ         1
+
+/* TCP Maximum segment size. */
+#define TCP_MSS                 512
+
+/* TCP sender buffer space (bytes). */
+#define TCP_SND_BUF             512
+
+/* TCP sender buffer space (pbufs). This must be at least = 2 *
+   TCP_SND_BUF/TCP_MSS for things to work. */
+#define TCP_SND_QUEUELEN        6 * TCP_SND_BUF/TCP_MSS
+
+/* TCP receive window. */
+#define TCP_WND                 512
+
+/* Maximum number of retransmissions of data segments. */
+#define TCP_MAXRTX              12
+
+/* Maximum number of retransmissions of SYN segments. */
+#define TCP_SYNMAXRTX           4
+
+/* ------------------------ ARP options ----------------------------------- */
+#define ARP_TABLE_SIZE          10
+#define ARP_QUEUEING            1
+
+/* ------------------------ IP options ------------------------------------ */
+/* Define IP_FORWARD to 1 if you wish to have the ability to forward
+   IP packets across network interfaces. If you are going to run lwIP
+   on a device with only one network interface, define this to 0. */
+#define IP_FORWARD              1
+
+/* If defined to 1, IP options are allowed (but not parsed). If
+   defined to 0, all packets with IP options are dropped. */
+#define IP_OPTIONS              1
+
+/* ------------------------ ICMP options ---------------------------------- */
+#define ICMP_TTL                255
+
+
+/* ------------------------ DHCP options ---------------------------------- */
+/* Define LWIP_DHCP to 1 if you want DHCP configuration of
+   interfaces. DHCP is not implemented in lwIP 0.5.1, however, so
+   turning this on does currently not work. */
+#define LWIP_DHCP               0
+
+/* 1 if you want to do an ARP check on the offered address
+   (recommended). */
+#define DHCP_DOES_ARP_CHECK     1
+
+/* ------------------------ UDP options ----------------------------------- */
+#define LWIP_UDP                1
+#define UDP_TTL                 255
+
+/* ------------------------ Statistics options ---------------------------- */
+#define STATS
+
+#ifdef STATS
+#define LINK_STATS              1
+#define IP_STATS                1
+#define ICMP_STATS              1
+#define UDP_STATS               1
+#define TCP_STATS               1
+#define MEM_STATS               1
+#define MEMP_STATS              1
+#define PBUF_STATS              1
+#define SYS_STATS               1
+#endif /* STATS */
+
+#define LWIP_PROVIDE_ERRNO      1
+
+#endif /* __LWIPOPTS_H__ */
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/m5235-ram.ld b/20080212/Demo/lwIP_MCF5235_GCC/m5235-ram.ld
new file mode 100644
index 000000000..7119d3f51
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/m5235-ram.ld
@@ -0,0 +1,119 @@
+STARTUP(system/crt0.o)
+INPUT(system/vector.o)
+OUTPUT_ARCH(m68k)
+SEARCH_DIR(.)
+GROUP(-lc -lgcc)
+
+__DYNAMIC  =  0;
+
+MEMORY
+{
+  sdram  (rwx) : ORIGIN = 0x00000000, LENGTH = 0x01000000
+  sram   (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000
+  ipsbar (rwx) : ORIGIN = 0x40000000, LENGTH = 0x40000000
+  flash  (rwx) : ORIGIN = 0x80000000, LENGTH = 0x00080000
+}
+
+PROVIDE (__stack = 0x2000FFFC);
+
+SECTIONS
+{
+  .sdram      : {} > sdram
+  .ipsbar     : {} > ipsbar
+  .sram (NOLOAD) : { *(.vector_ram); *(.nbuf) } > sram
+  .flash      : {} > flash
+
+  .text :
+  {
+    __text_start = . ;
+    *(.vector_rom)
+    . = ALIGN (0x100);
+    *(.text)
+    . = ALIGN (16);
+
+    *(.eh_frame)
+    . = ALIGN (16);
+
+    *(.gnu.linkonce.t.*) 
+
+    . = ALIGN(0x4);
+     __CTOR_LIST__ = .;
+    ___CTOR_LIST__ = .;
+    LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
+    *(.ctors)
+    LONG(0)
+    __CTOR_END__ = .;
+    __DTOR_LIST__ = .;
+    ___DTOR_LIST__ = .;
+    LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)
+    *(.dtors)
+     LONG(0)
+    __DTOR_END__ = .;
+    *(.rodata)
+    *(.rodata.*)
+    *(.gcc_except_table) 
+
+    . = ALIGN(0x2);
+    __INIT_SECTION__ = . ;
+    LONG (0x4e560000)	/* linkw %fp,#0 */
+    *(.init)
+    SHORT (0x4e5e)	/* unlk %fp */
+    SHORT (0x4e75)	/* rts */
+
+    __FINI_SECTION__ = . ;
+    LONG (0x4e560000)	/* linkw %fp,#0 */
+    *(.fini)
+    SHORT (0x4e5e)	/* unlk %fp */
+    SHORT (0x4e75)	/* rts */
+
+    *(.lit)
+    . = ALIGN(16);
+    _etext = .;
+    etext = .;
+  } > sdram
+
+  .data :
+  {
+    copy_start = .;
+    *(.shdata)
+    *(.data)
+    *(.gnu.linkonce.d.*)
+    . = ALIGN (16);
+    _edata = .;
+    copy_end = .;
+  } > sdram
+  __data_load_start = LOADADDR(.data);
+  __data_load_end = __data_load_start + SIZEOF(.data);
+
+  .bss :
+  {
+    . = ALIGN(0x4);
+    __bss_start = . ;
+    *(.shbss)
+    *(.bss)
+    *(COMMON)
+    _end =  ALIGN (0x8);
+    __end = _end;
+  } > sdram
+
+  .stab 0 (NOLOAD) :
+  {
+    *(.stab)
+  }
+
+  .stabstr 0 (NOLOAD) :
+  {
+    *(.stabstr)
+  }
+}
+
+__IPSBAR            = ADDR(.ipsbar);
+
+__SDRAM             = ADDR(.sdram);
+__SDRAM_SIZE        = SIZEOF(.sdram);
+
+__SRAM              = ADDR(.sram);
+__SRAM_SIZE         = SIZEOF(.sram);
+
+__FLASH             = ADDR(.flash);
+__FLASH_SIZE        = SIZEOF(.flash);
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/m5235-rom.ld b/20080212/Demo/lwIP_MCF5235_GCC/m5235-rom.ld
new file mode 100644
index 000000000..333d28e1f
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/m5235-rom.ld
@@ -0,0 +1,121 @@
+STARTUP(system/crt0.o)
+INPUT(system/vector.o)
+OUTPUT_ARCH(m68k)
+SEARCH_DIR(.)
+GROUP(-lc -lgcc)
+
+__DYNAMIC  =  0;
+
+MEMORY
+{
+  flash  (rwx) : ORIGIN = 0x00000000, LENGTH = 0x00200000
+  sdram  (rwx) : ORIGIN = 0x01000000, LENGTH = 0x01000000
+  sram   (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000
+  ipsbar (rwx) : ORIGIN = 0x40000000, LENGTH = 0x40000000
+}
+
+PROVIDE (__stack = 0x2000FFFC);
+
+SECTIONS
+{
+  .sdram      : {} > sdram
+  .ipsbar     : {} > ipsbar
+  .sram (NOLOAD) : { *(.vector_ram); *(.nbuf) } > sram
+  .flash      : {} > flash
+
+  .text :
+  {
+    __text_start = . ;
+    *(.vector_rom)
+    . = ALIGN (0x100);
+    *(.text)
+    . = ALIGN (16);
+
+    *(.eh_frame)
+    . = ALIGN (16);
+
+    *(.gnu.linkonce.t.*) 
+
+    . = ALIGN(0x4);
+     __CTOR_LIST__ = .;
+    ___CTOR_LIST__ = .;
+    LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
+    *(.ctors)
+    LONG(0)
+    __CTOR_END__ = .;
+    __DTOR_LIST__ = .;
+    ___DTOR_LIST__ = .;
+    LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)
+    *(.dtors)
+     LONG(0)
+    __DTOR_END__ = .;
+    *(.rodata)
+    *(.rodata.*)
+    *(.gcc_except_table) 
+
+    . = ALIGN(0x2);
+    __INIT_SECTION__ = . ;
+    LONG (0x4e560000)	/* linkw %fp,#0 */
+    *(.init)
+    SHORT (0x4e5e)	/* unlk %fp */
+    SHORT (0x4e75)	/* rts */
+
+    __FINI_SECTION__ = . ;
+    LONG (0x4e560000)	/* linkw %fp,#0 */
+    *(.fini)
+    SHORT (0x4e5e)	/* unlk %fp */
+    SHORT (0x4e75)	/* rts */
+
+    *(.lit)
+    . = ALIGN(16);
+    _etext = .;
+    etext = .;
+
+  } > flash
+  . = ALIGN(2);
+
+  .data : AT (ADDR (.text) + SIZEOF (.text))
+  {
+    copy_start = .;
+    *(.shdata)
+    *(.data)
+    *(.gnu.linkonce.d.*)
+    . = ALIGN (16);
+    _edata = .;
+    copy_end = .;
+  } > sdram
+  __data_load_start = LOADADDR(.data);
+  __data_load_end = __data_load_start + SIZEOF(.data);
+
+  .bss :
+  {
+    . = ALIGN(0x4);
+    __bss_start = . ;
+    *(.shbss)
+    *(.bss)
+    *(COMMON)
+    _end =  ALIGN (0x8);
+    __end = _end;
+  } > sdram
+
+  .stab 0 (NOLOAD) :
+  {
+    *(.stab)
+  }
+
+  .stabstr 0 (NOLOAD) :
+  {
+    *(.stabstr)
+  }
+}
+
+__IPSBAR            = ADDR(.ipsbar);
+
+__SDRAM             = ADDR(.sdram);
+__SDRAM_SIZE        = SIZEOF(.sdram);
+
+__SRAM              = ADDR(.sram);
+__SRAM_SIZE         = SIZEOF(.sram);
+
+__FLASH             = ADDR(.flash);
+__FLASH_SIZE        = SIZEOF(.flash);
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/m5235.gdb b/20080212/Demo/lwIP_MCF5235_GCC/m5235.gdb
new file mode 100644
index 000000000..545fbea31
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/m5235.gdb
@@ -0,0 +1,134 @@
+set $IPSBAR = 0x40000000
+
+set $DCR    = $IPSBAR + 0x000040
+set $DACR0  = $IPSBAR + 0x000048
+set $DMR0   = $IPSBAR + 0x00004C
+
+set $CSAR0  = $IPSBAR + 0x000080
+set $CSMR0  = $IPSBAR + 0x000084
+set $CSCR0  = $IPSBAR + 0x00008A
+
+set $PAR_SDRAM = $IPSBAR + 0x100046
+set $PAR_AD    = $IPSBAR + 0x100040
+
+set $WCR    = $IPSBAR + 0x140000
+
+define delay
+  set $delay = 0
+  while ($delay < 20000)
+    set $delay += 1
+  end  
+end
+
+define delay_memsync
+  set $delay = 0
+  while ($delay < 10000)
+    set $delay += 1
+  end  
+end
+
+define setup-cs
+  # 2MB FLASH on CS0 at 0x80000000
+  set *(unsigned short *)$CSAR0 = 0x00008000
+  set *(unsigned long  *)$CSMR0 = 0x001F0101
+  set *(unsigned short *)$CSCR0 = 0x00001980
+end
+
+define setup-sdram
+  # Set PAR_SDRAM to allow SDRAM signals to be enable
+  set *(unsigned char *)$PAR_SDRAM = 0x3F
+  # Set PAR_AD to allow 32-bit SDRAM if the external boot device is 16-bit
+  set *(unsigned char *)$PAR_AD = 0xE1
+
+  # SDRAM
+  set *(unsigned short *)$DCR   = 0x0446
+  set *(unsigned long *)$DACR0  = 0x00001300
+  set *(unsigned long *)$DMR0   = 0x00FC0001
+
+  # Set IP in DACR and init precharge.
+  set *(unsigned long *)$DACR0 |= 0x00000008
+  set *(0x00000000)             = 0xAA55AA55
+  delay
+
+  # Set RE in DACR
+  set *(unsigned long *)$DACR0 |= 0x00008000
+  # Issue IMRS
+  set *(unsigned long *)$DACR0 |= 0x00000040
+  set *(0x00000400)             = 0xAA55AA55
+  delay
+end
+
+define setup-other
+  # Turn Off WCR
+  set *(unsigned char *)$WCR = 0x00
+end
+
+define setup-and-load
+  bdm-reset
+
+  # Set VBR to the vector table.
+  set $vbr = 0x00000000
+  # Set internal SRAM to start at 0x20000000
+  set $rambar = 0x20000001
+
+  setup-other
+  setup-cs
+  setup-sdram
+end
+
+define debug-sramtest
+  set $srambase = 0x20000000
+  set $sramsize = 0x00010000
+  set $j = 0
+  printf "Testing SRAM : 0x%08X - 0x%08X\n", $srambase, ($srambase + $sramsize)
+  set $i = $srambase
+  while $i < ($srambase + $sramsize)
+    set *(unsigned long *)($i) = 0xAA55AA55
+    delay_memsync
+    if 0xAA55AA55 != *(unsigned long *)$i
+      printf "  0x%08X = FAIL\n", $i
+    else
+      printf "  0x%08X = OK", $i
+      if $j % 4 == 3
+        printf "\n"
+      end
+      set $j = $j + 1
+    end
+    set $i = $i + 0x400
+  end
+en
+
+define debug-ramtest
+  set $sdrambase = 0x00000000
+  set $sdramsize = 0x01000000
+  set $j = 0
+  printf "Testing SDRAM : 0x%08X - 0x%08X\n", $sdrambase, ($sdrambase + $sdramsize)
+  set $i = $sdrambase 
+  while $i < ($sdrambase + $sdramsize)
+    set *(unsigned long *)($i) = 0xAA55AA55
+    delay_memsync
+    if 0xAA55AA55 != *(unsigned long *)$i
+      printf "  0x%08X = FAIL\n", $i
+    else
+      printf "  0x%08X = OK", $i
+      if $j % 4 == 3
+        printf "\n"
+      end
+      set $j = $j + 1
+    end
+    set $i = $i + 0x10000
+  end
+  printf "\n"
+end
+
+define execute
+  set $pc = *(long *)0x00000004
+  tbreak main
+  tk gdbtk_update
+end
+
+define debug-printexception
+  printf "vector: %d", *(unsigned short *)$sp >> 2 &0x1F
+  printf "old pc: 0x%08x", *(unsigned long *)($sp + 4)
+  printf "old sr: 0x%02x", *(unsigned short *)($sp + 2)
+end
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/system/crt0.S b/20080212/Demo/lwIP_MCF5235_GCC/system/crt0.S
new file mode 100644
index 000000000..5e8c06615
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/system/crt0.S
@@ -0,0 +1,125 @@
+/*
+    FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    FreeRTOS is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with FreeRTOS; if not, write to the Free Software
+    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+    A special exception to the GPL can be applied should you wish to distribute
+    a combined work that includes FreeRTOS, without being obliged to provide
+    the source code for any proprietary components.  See the licensing section
+    of http://www.FreeRTOS.org for full details of how and when the exception
+    can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+  .title "crt0.S"
+
+  .extern main
+  .extern __stack
+  .extern __bss_start
+  .extern __text_start
+  .extern init_main
+
+  .equ    MCF5XXX_RAMBAR_SPV,   0x00000200
+  .equ    MCF5XXX_RAMBAR_V,     0x00000001
+  .global start
+
+  .align  4
+debug:
+  .word   0x2C80    /* write to CSR */
+  .word   0x0010
+  .word   0x0400
+  .word   0x0000
+
+start:
+  /* disable all interrupts on startup. */
+  move.w  #0x2700, sr
+
+  /* prepare internal SRAM. */
+  move.l  #__SRAM, d0
+  ori.l   #( MCF5XXX_RAMBAR_SPV | MCF5XXX_RAMBAR_V ), d0
+  movec   d0, rambar
+
+  /* prepare stack and frame pointer. */
+  move.l  #__stack, sp
+  link    a6, #-8
+
+  /* initialize hardware. */
+  jsr     init_main
+
+  /* zero out the bss section. */
+  move.l  #__bss_start, d1
+  move.l  #_end, d0
+  cmp.l   d0, d1
+  jbeq    3f
+  move.l  d1, a0
+  sub.l   d1, d0
+  subq.l  #1, d0
+2:
+  clr.b   (a0)+
+  subq.l  #1, d0
+  jbpl    2b
+3:
+
+  /* Relocate the data section. */
+  move.l  #__data_load_start, %a0         /* .data in ROM */
+  move.l  #copy_start, %a1                /* .data in RAM */
+
+  /* Test if the two sections overlap. This is the case when we are working
+   * with the debugger and the debugger loads the .data section.
+   */
+  cmpa.l  %a0, %a1
+  beq     2f
+1:
+  /* Have we already copied everything. */
+  cmpa.l  #__data_load_end, %a0
+  beq     2f
+  move.b  (%a0)+, (%a1)+
+  bra     1b
+
+2:
+
+  /* C library */
+  move.l  #__FINI_SECTION__, -(%sp)
+  jsr     atexit
+  jsr     __INIT_SECTION__
+
+  /* call main(int argc, char *argv[] */
+  move.l  #0, -(sp)
+  move.l  #0, -(sp)
+  move.l  #0, -(sp)
+  jsr     main
+  lea     (sp, 12), %sp
+
+  /* stop on exit from main. */
+1:
+  halt
+
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/system/init.c b/20080212/Demo/lwIP_MCF5235_GCC/system/init.c
new file mode 100644
index 000000000..51f75f65c
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/system/init.c
@@ -0,0 +1,753 @@
+/*
+    FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    FreeRTOS is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with FreeRTOS; if not, write to the Free Software
+    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+    A special exception to the GPL can be applied should you wish to distribute
+    a combined work that includes FreeRTOS, without being obliged to provide
+    the source code for any proprietary components.  See the licensing section
+    of http://www.FreeRTOS.org for full details of how and when the exception
+    can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+#include "mcf5xxx.h"
+#include "mcf523x.h"
+
+/* Function prototypes */
+void            init_main( void );
+static void     disable_interrupts( void );
+static void     disable_watchdog_timer( void );
+static void     disable_cache( void );
+static void     init_ipsbar( void );
+static void     init_basics( void );
+static void     init_clock_config( void );
+static void     init_chip_selects( void );
+static void     init_bus_config( void );
+static void     init_cache( void );
+static void     init_eport( void );
+static void     init_flexcan( void );
+static void     init_power_management( void );
+static void     init_dma_timers( void );
+static void     init_interrupt_timers( void );
+static void     init_watchdog_timers( void );
+static void     init_pin_assignments( void );
+static void     init_sdram_controller( void );
+static void     init_interrupt_controller( void );
+
+
+/*********************************************************************
+* init_main - Main entry point for initialisation code               *
+**********************************************************************/
+void
+init_main( void )
+{
+
+    /* Initialise base address of peripherals, VBR, etc */
+    init_ipsbar(  );
+    init_basics(  );
+    init_clock_config(  );
+
+    /* Disable interrupts, watchdog timer, cache */
+    disable_interrupts(  );
+    disable_watchdog_timer(  );
+    disable_cache(  );
+
+    /* Initialise individual modules */
+    init_chip_selects(  );
+    init_bus_config(  );
+    init_cache(  );
+    init_eport(  );
+    init_flexcan(  );
+    init_power_management(  );
+    init_dma_timers(  );
+    init_interrupt_timers(  );
+    init_watchdog_timers(  );
+    init_pin_assignments(  );
+    init_sdram_controller(  );
+
+    /* Initialise interrupt controller */
+    init_interrupt_controller(  );
+}
+
+/*********************************************************************
+* disable_interrupts - Disable all interrupt sources                 *
+**********************************************************************/
+static void
+disable_interrupts( void )
+{
+    vuint8         *p;
+    int             i;
+
+
+    /* Set ICR008-ICR063 to 0x0 */
+    p = ( vuint8 * ) & MCF_INTC0_ICR8;
+    for( i = 8; i <= 63; i++ )
+        *p++ = 0x0;
+
+    /* Set ICR108-ICR163 to 0x0 */
+    p = ( vuint8 * ) & MCF_INTC1_ICR8;
+    for( i = 108; i <= 163; i++ )
+        *p++ = 0x0;
+}
+
+
+/*********************************************************************
+* disable_watchdog_timer - Disable system watchdog timer             *
+**********************************************************************/
+static void
+disable_watchdog_timer( void )
+{
+
+    /* Disable Core Watchdog Timer */
+    MCF_SCM_CWCR = 0;
+}
+
+/*********************************************************************
+* disable_cache - Disable and invalidate cache                       *
+**********************************************************************/
+static void
+disable_cache( void )
+{
+    asm ( "move.l   #0x01000000, %d0" );
+    asm ( "movec    %d0, %CACR" );
+}
+
+/*********************************************************************
+* init_basics - Configuration Information & VBR                      *
+**********************************************************************/
+static void
+init_basics( void )
+{
+    int             i;
+    extern uint32   __RAMVEC[];
+    extern uint32   __ROMVEC[];
+
+    /* Transfer size not driven on SIZ[1:0] pins during external cycles
+       Processor Status (PST) and Debug Data (DDATA) functions disabled
+       Bus monitor disabled
+       Output pads configured for full strength
+     */
+    MCF_CCM_CCR = ( 0x1 << 15 ) | MCF_CCM_CCR_BME;
+
+    /* Set up RAM vectors */
+    for( i = 0; i < 256; i++ )
+
+    {
+        __RAMVEC[i] = __ROMVEC[i];
+    }
+    asm( "move.l   %0,%%d0": :"i"( __RAMVEC ) );
+    asm( "movec    %d0,%vbr" );
+}
+
+
+/*********************************************************************
+* init_clock_config - Clock Module                                   *
+**********************************************************************/
+static void
+init_clock_config( void )
+{
+    /* Clock module uses normal PLL mode with 25.0000 MHz external reference (Fref)
+       MFD = 0, RFD = 1
+       Bus clock frequency = 25.00 MHz
+       Processor clock frequency = 2 x bus clock = 50.00 MHz
+       Frequency Modulation disabled
+       Loss of clock detection disabled
+       Reset/Interrupt on loss of lock disabled
+     */
+    MCF_FMPLL_SYNCR = 0x00100000;       /* Set RFD=RFD+1 to avoid frequency overshoot */
+    while( ( MCF_FMPLL_SYNSR & 0x08 ) == 0 )    /* Wait for PLL to lock */
+        ;
+    MCF_FMPLL_SYNCR = 0x00080000;       /* Set desired RFD */
+    while( ( MCF_FMPLL_SYNSR & 0x08 ) == 0 )    /* Wait for PLL to lock */
+        ;
+}
+
+
+/*********************************************************************
+* init_ipsbar - Internal Peripheral System Base Address (IPSBAR)     *
+**********************************************************************/
+static void
+init_ipsbar( void )
+{
+    extern int  __SRAM;
+
+    /* Base address of internal peripherals (IPSBAR) = 0x40000000
+
+       Note: Processor powers up with IPS base address = 0x40000000
+       Write to IPS base + 0x00000000 to set new value
+     */
+    *( vuint32 * ) 0x40000000 = ( vuint32 ) __IPSBAR + 1;
+
+    /* Configure RAMBAR in SCM module and allow dual-ported access. */
+    MCF_SCM_RAMBAR = ( uint32 ) &__SRAM | MCF_SCM_RAMBAR_BDE;
+}
+
+/*********************************************************************
+* init_chip_selects - Chip Select Module                             *
+**********************************************************************/
+static void
+init_chip_selects( void )
+{
+    extern void __FLASH;
+    uint32 FLASH_ADDR = (uint32)&__FLASH;
+
+    /* Chip Select 0 - External Flash */
+    MCF_CS_CSAR0 = MCF_CS_CSAR_BA( FLASH_ADDR );
+    MCF_CS_CSCR0 = ( 0
+                     | MCF_CS_CSCR_IWS( 6 )
+                     | MCF_CS_CSCR_AA | MCF_CS_CSCR_PS_16 );
+    MCF_CS_CSMR0 = MCF_CS_CSMR_BAM_2M | MCF_CS_CSMR_V;
+
+    /* Chip Select 1 disabled (CSMR1[V] = 0) */
+    MCF_CS_CSAR1 = 0;
+    MCF_CS_CSMR1 = 0;
+    MCF_CS_CSCR1 = 0;
+
+    /* Chip Select 2 disabled (CSMR2[V] = 0) */
+    MCF_CS_CSAR2 = 0;
+    MCF_CS_CSMR2 = 0;
+    MCF_CS_CSCR2 = 0;
+
+    /* Chip Select 3 disabled (CSMR3[V] = 0) */
+    MCF_CS_CSAR3 = 0;
+    MCF_CS_CSMR3 = 0;
+    MCF_CS_CSCR3 = 0;
+
+    /* Chip Select 4 disabled (CSMR4[V] = 0) */
+    MCF_CS_CSAR4 = 0;
+    MCF_CS_CSMR4 = 0;
+    MCF_CS_CSCR4 = 0;
+
+    /* Chip Select 5 disabled (CSMR5[V] = 0) */
+    MCF_CS_CSAR5 = 0;
+    MCF_CS_CSMR5 = 0;
+    MCF_CS_CSCR5 = 0;
+
+    /* Chip Select 6 disabled (CSMR6[V] = 0) */
+    MCF_CS_CSAR6 = 0;
+    MCF_CS_CSMR6 = 0;
+    MCF_CS_CSCR6 = 0;
+
+    /* Chip Select 7 disabled (CSMR7[V] = 0) */
+    MCF_CS_CSAR7 = 0;
+    MCF_CS_CSMR7 = 0;
+    MCF_CS_CSCR7 = 0;
+}
+
+/*********************************************************************
+* init_bus_config - Internal Bus Arbitration                         *
+**********************************************************************/
+static void
+init_bus_config( void )
+{
+
+    /* Use round robin arbitration scheme
+       Assigned priorities (highest first):
+       Ethernet
+       DMA Controller
+       ColdFire Core
+       DMA bandwidth control disabled
+       Park on last active bus master
+     */
+    MCF_SCM_MPARK =
+        MCF_SCM_MPARK_M3_PRTY( 0x3 ) | MCF_SCM_MPARK_M2_PRTY( 0x2 ) |
+        MCF_SCM_MPARK_M1_PRTY( 0x1 );
+}
+
+/*********************************************************************
+* init_cache - Instruction/Data Cache                                *
+**********************************************************************/
+static void
+init_cache( void )
+{
+    /* Configured as split cache: 4 KByte instruction cache and 4 Kbyte data cache
+       ACR0: Don't cache accesses to 16 MB memory region at address $20000000
+       ACR1: Don't cache accesses to 1 GB memory region at address $40000000
+       CACR: Cache accesses to the rest of memory
+    */
+    asm("move.l   #0x80000000,%d0");
+    asm("movec    %d0,%CACR");
+    asm("move.l   #0x2000c040,%d0");
+    asm("movec    %d0,%ACR0");
+    asm("move.l   #0x403fc040,%d0");
+    asm("movec    %d0,%ACR1");
+
+    /* Instruction/Data cache disabled. */
+    //asm( "move.l   #0x00000000, %d0" );
+    //asm( "movec    %d0,%cacr" );
+}
+
+/*********************************************************************
+* init_eport - Edge Port Module (EPORT)                              *
+**********************************************************************/
+static void
+init_eport( void )
+{
+
+    /* Pins 1-7 configured as GPIO inputs */
+    MCF_EPORT_EPPAR = 0;
+    MCF_EPORT_EPDDR = 0;
+    MCF_EPORT_EPIER = 0;
+}
+
+/*********************************************************************
+* init_flexcan - FlexCAN Module                                      *
+**********************************************************************/
+static void
+init_flexcan( void )
+{
+
+    /* FlexCAN controller 0 disabled (CANMCR0[MDIS]=1) */
+    MCF_CAN_IMASK0 = 0;
+    MCF_CAN_RXGMASK0 = MCF_CAN_RXGMASK_MI( 0x1fffffff );
+    MCF_CAN_RX14MASK0 = MCF_CAN_RX14MASK_MI( 0x1fffffff );
+    MCF_CAN_RX15MASK0 = MCF_CAN_RX15MASK_MI( 0x1fffffff );
+    MCF_CAN_CANCTRL0 = 0;
+    MCF_CAN_CANMCR0 =
+        MCF_CAN_CANMCR_MDIS | MCF_CAN_CANMCR_FRZ | MCF_CAN_CANMCR_HALT |
+        MCF_CAN_CANMCR_SUPV | MCF_CAN_CANMCR_MAXMB( 0xf );
+
+    /* FlexCAN controller 1 disabled (CANMCR1[MDIS]=1) */
+    MCF_CAN_IMASK1 = 0;
+    MCF_CAN_RXGMASK1 = MCF_CAN_RXGMASK_MI( 0x1fffffff );
+    MCF_CAN_RX14MASK1 = MCF_CAN_RX14MASK_MI( 0x1fffffff );
+    MCF_CAN_RX15MASK1 = MCF_CAN_RX15MASK_MI( 0x1fffffff );
+    MCF_CAN_CANCTRL1 = 0;
+    MCF_CAN_CANMCR1 =
+        MCF_CAN_CANMCR_MDIS | MCF_CAN_CANMCR_FRZ | MCF_CAN_CANMCR_HALT |
+        MCF_CAN_CANMCR_SUPV | MCF_CAN_CANMCR_MAXMB( 0xf );
+}
+
+/*********************************************************************
+* init_power_management - Power Management                           *
+**********************************************************************/
+static void
+init_power_management( void )
+{
+
+    /* On executing STOP instruction, processor enters RUN mode
+       Mode is exited when an interrupt of level 1 or higher is received
+     */
+    MCF_SCM_LPICR = MCF_SCM_LPICR_ENBSTOP;
+    MCF_CCM_LPCR = 0;
+}
+
+/*********************************************************************
+* init_sdram_controller - SDRAM Controller                           *
+**********************************************************************/
+static void
+init_sdram_controller( void )
+{
+    extern void __SDRAM;
+    uint32 SDRAM_ADDR = (uint32)&__SDRAM;
+    int             i;
+
+
+    /*
+     * Check to see if the SDRAM has already been initialized
+     * by a run control tool
+     */
+    if( !( MCF_SDRAMC_DACR0 & MCF_SDRAMC_DACR0_RE ) )
+    {
+        /* Initialize DRAM Control Register: DCR */
+        MCF_SDRAMC_DCR = ( MCF_SDRAMC_DCR_RTIM( 1 ) |
+                           MCF_SDRAMC_DCR_RC( ( 15 * FSYS_2 ) >> 4 ) );
+
+        /* Initialize DACR0 */
+        MCF_SDRAMC_DACR0 = ( MCF_SDRAMC_DACR0_BA( SDRAM_ADDR >> 18UL ) |
+                             MCF_SDRAMC_DACR0_CASL( 1 ) |
+                             MCF_SDRAMC_DACR0_CBM( 3 ) |
+                             MCF_SDRAMC_DACR0_PS( 0 ) );
+
+        /* Initialize DMR0 */
+        MCF_SDRAMC_DMR0 = ( MCF_SDRAMC_DMR_BAM_16M | MCF_SDRAMC_DMR0_V );
+
+        /* Set IP (bit 3) in DACR */
+        MCF_SDRAMC_DACR0 |= MCF_SDRAMC_DACR0_IP;
+
+        /* Wait 30ns to allow banks to precharge */
+        for( i = 0; i < 5; i++ )
+        {
+            asm volatile    ( " nop" );
+        }
+        /* Write to this block to initiate precharge */
+        *( uint32 * ) ( SDRAM_ADDR ) = 0xA5A59696;
+
+        /* Set RE (bit 15) in DACR */
+        MCF_SDRAMC_DACR0 |= MCF_SDRAMC_DACR0_RE;
+
+        /* Wait for at least 8 auto refresh cycles to occur */
+        for( i = 0; i < 2000; i++ )
+        {
+            asm volatile    ( "nop" );
+        }
+        /* Finish the configuration by issuing the IMRS. */
+        MCF_SDRAMC_DACR0 |= MCF_SDRAMC_DACR0_MRS;
+
+        /* Write to the SDRAM Mode Register */
+        *( uint32 * ) ( SDRAM_ADDR + 0x400 ) = 0xA5A59696;
+    }
+}
+
+/*********************************************************************
+* init_dma_timers - DMA Timer Modules                                *
+**********************************************************************/
+static void
+init_dma_timers( void )
+{
+
+    /* DMA Timer 0 disabled (DTMR0[RST] = 0) */
+    MCF_TIMER_DTMR0 = 0;
+    MCF_TIMER_DTXMR0 = 0;
+    MCF_TIMER_DTRR0 = 0xffffffff;
+
+    /* DMA Timer 1 disabled (DTMR1[RST] = 0) */
+    MCF_TIMER_DTMR1 = 0;
+    MCF_TIMER_DTXMR1 = 0;
+    MCF_TIMER_DTRR1 = 0xffffffff;
+
+    /* DMA Timer 2 disabled (DTMR2[RST] = 0) */
+    MCF_TIMER_DTMR2 = 0;
+    MCF_TIMER_DTXMR2 = 0;
+    MCF_TIMER_DTRR2 = 0xffffffff;
+
+    /* DMA Timer 3 disabled (DTMR3[RST] = 0) */
+    MCF_TIMER_DTMR3 = 0;
+    MCF_TIMER_DTXMR3 = 0;
+    MCF_TIMER_DTRR3 = 0xffffffff;
+}
+
+/**********************************************************************
+* init_interrupt_timers - Programmable Interrupt Timer (PIT) Modules  *
+***********************************************************************/
+static void
+init_interrupt_timers( void )
+{
+
+    /* PIT0 disabled (PCSR0[EN]=0) */
+    MCF_PIT_PCSR0 = 0;
+
+    /* PIT1 disabled (PCSR1[EN]=0) */
+    MCF_PIT_PCSR1 = 0;
+
+    /* PIT2 disabled (PCSR2[EN]=0) */
+    MCF_PIT_PCSR2 = 0;
+
+    /* PIT3 disabled (PCSR3[EN]=0) */
+    MCF_PIT_PCSR3 = 0;
+}
+
+/*********************************************************************
+* init_watchdog_timers - Watchdog Timer Modules                      *
+**********************************************************************/
+static void
+init_watchdog_timers( void )
+{
+
+    /* Watchdog Timer disabled (WCR[EN]=0)
+       NOTE: WCR and WMR cannot be written again until after the
+       processor is reset.
+     */
+    MCF_WTM_WCR = MCF_WTM_WCR_WAIT | MCF_WTM_WCR_DOZE | MCF_WTM_WCR_HALTED;
+    MCF_WTM_WMR = 0xffff;
+
+    /* Core Watchdog Timer disabled (CWCR[CWE]=0) */
+    MCF_SCM_CWCR = 0;
+}
+
+/*********************************************************************
+* init_interrupt_controller - Interrupt Controller                   *
+**********************************************************************/
+static void
+init_interrupt_controller( void )
+{
+
+    /* Configured interrupt sources in order of priority...
+       Level 7:  External interrupt /IRQ7, (initially masked)
+       Level 6:  External interrupt /IRQ6, (initially masked)
+       Level 5:  External interrupt /IRQ5, (initially masked)
+       Level 4:  External interrupt /IRQ4, (initially masked)
+       Level 3:  External interrupt /IRQ3, (initially masked)
+       Level 2:  External interrupt /IRQ2, (initially masked)
+       Level 1:  External interrupt /IRQ1, (initially masked)
+     */
+    MCF_INTC0_ICR1 = 0;
+    MCF_INTC0_ICR2 = 0;
+    MCF_INTC0_ICR3 = 0;
+    MCF_INTC0_ICR4 = 0;
+    MCF_INTC0_ICR5 = 0;
+    MCF_INTC0_ICR6 = 0;
+    MCF_INTC0_ICR7 = 0;
+    MCF_INTC0_ICR8 = 0;
+    MCF_INTC0_ICR9 = 0;
+    MCF_INTC0_ICR10 = 0;
+    MCF_INTC0_ICR11 = 0;
+    MCF_INTC0_ICR12 = 0;
+    MCF_INTC0_ICR13 = 0;
+    MCF_INTC0_ICR14 = 0;
+    MCF_INTC0_ICR15 = 0;
+    MCF_INTC0_ICR17 = 0;
+    MCF_INTC0_ICR18 = 0;
+    MCF_INTC0_ICR19 = 0;
+    MCF_INTC0_ICR20 = 0;
+    MCF_INTC0_ICR21 = 0;
+    MCF_INTC0_ICR22 = 0;
+    MCF_INTC0_ICR23 = 0;
+    MCF_INTC0_ICR24 = 0;
+    MCF_INTC0_ICR25 = 0;
+    MCF_INTC0_ICR26 = 0;
+    MCF_INTC0_ICR27 = 0;
+    MCF_INTC0_ICR28 = 0;
+    MCF_INTC0_ICR29 = 0;
+    MCF_INTC0_ICR30 = 0;
+    MCF_INTC0_ICR31 = 0;
+    MCF_INTC0_ICR32 = 0;
+    MCF_INTC0_ICR33 = 0;
+    MCF_INTC0_ICR34 = 0;
+    MCF_INTC0_ICR35 = 0;
+    MCF_INTC0_ICR36 = 0;
+    MCF_INTC0_ICR37 = 0;
+    MCF_INTC0_ICR38 = 0;
+    MCF_INTC0_ICR39 = 0;
+    MCF_INTC0_ICR40 = 0;
+    MCF_INTC0_ICR41 = 0;
+    MCF_INTC0_ICR42 = 0;
+    MCF_INTC0_ICR43 = 0;
+    MCF_INTC0_ICR44 = 0;
+    MCF_INTC0_ICR45 = 0;
+    MCF_INTC0_ICR46 = 0;
+    MCF_INTC0_ICR47 = 0;
+    MCF_INTC0_ICR48 = 0;
+    MCF_INTC0_ICR49 = 0;
+    MCF_INTC0_ICR50 = 0;
+    MCF_INTC0_ICR51 = 0;
+    MCF_INTC0_ICR52 = 0;
+    MCF_INTC0_ICR53 = 0;
+    MCF_INTC0_ICR54 = 0;
+    MCF_INTC0_ICR55 = 0;
+    MCF_INTC0_ICR56 = 0;
+    MCF_INTC0_ICR57 = 0;
+    MCF_INTC0_ICR58 = 0;
+    MCF_INTC0_ICR59 = 0;
+    MCF_INTC0_ICR60 = 0;
+    MCF_INTC1_ICR8 = 0;
+    MCF_INTC1_ICR9 = 0;
+    MCF_INTC1_ICR10 = 0;
+    MCF_INTC1_ICR11 = 0;
+    MCF_INTC1_ICR12 = 0;
+    MCF_INTC1_ICR13 = 0;
+    MCF_INTC1_ICR14 = 0;
+    MCF_INTC1_ICR15 = 0;
+    MCF_INTC1_ICR16 = 0;
+    MCF_INTC1_ICR17 = 0;
+    MCF_INTC1_ICR18 = 0;
+    MCF_INTC1_ICR19 = 0;
+    MCF_INTC1_ICR20 = 0;
+    MCF_INTC1_ICR21 = 0;
+    MCF_INTC1_ICR22 = 0;
+    MCF_INTC1_ICR23 = 0;
+    MCF_INTC1_ICR24 = 0;
+    MCF_INTC1_ICR25 = 0;
+    MCF_INTC1_ICR27 = 0;
+    MCF_INTC1_ICR28 = 0;
+    MCF_INTC1_ICR29 = 0;
+    MCF_INTC1_ICR30 = 0;
+    MCF_INTC1_ICR31 = 0;
+    MCF_INTC1_ICR32 = 0;
+    MCF_INTC1_ICR33 = 0;
+    MCF_INTC1_ICR34 = 0;
+    MCF_INTC1_ICR35 = 0;
+    MCF_INTC1_ICR36 = 0;
+    MCF_INTC1_ICR37 = 0;
+    MCF_INTC1_ICR38 = 0;
+    MCF_INTC1_ICR39 = 0;
+    MCF_INTC1_ICR40 = 0;
+    MCF_INTC1_ICR41 = 0;
+    MCF_INTC1_ICR42 = 0;
+    MCF_INTC1_ICR59 = 0;
+    MCF_INTC0_IMRH = 0xffffffff;
+    MCF_INTC0_IMRL =
+        MCF_INTC0_IMRL_INT_MASK31 | MCF_INTC0_IMRL_INT_MASK30 |
+        MCF_INTC0_IMRL_INT_MASK29 | MCF_INTC0_IMRL_INT_MASK28 |
+        MCF_INTC0_IMRL_INT_MASK27 | MCF_INTC0_IMRL_INT_MASK26 |
+        MCF_INTC0_IMRL_INT_MASK25 | MCF_INTC0_IMRL_INT_MASK24 |
+        MCF_INTC0_IMRL_INT_MASK23 | MCF_INTC0_IMRL_INT_MASK22 |
+        MCF_INTC0_IMRL_INT_MASK21 | MCF_INTC0_IMRL_INT_MASK20 |
+        MCF_INTC0_IMRL_INT_MASK19 | MCF_INTC0_IMRL_INT_MASK18 |
+        MCF_INTC0_IMRL_INT_MASK17 | MCF_INTC0_IMRL_INT_MASK16 |
+        MCF_INTC0_IMRL_INT_MASK15 | MCF_INTC0_IMRL_INT_MASK14 |
+        MCF_INTC0_IMRL_INT_MASK13 | MCF_INTC0_IMRL_INT_MASK12 |
+        MCF_INTC0_IMRL_INT_MASK11 | MCF_INTC0_IMRL_INT_MASK10 |
+        MCF_INTC0_IMRL_INT_MASK9 | MCF_INTC0_IMRL_INT_MASK8 |
+        MCF_INTC0_IMRL_INT_MASK7 | MCF_INTC0_IMRL_INT_MASK6 |
+        MCF_INTC0_IMRL_INT_MASK5 | MCF_INTC0_IMRL_INT_MASK4 |
+        MCF_INTC0_IMRL_INT_MASK3 | MCF_INTC0_IMRL_INT_MASK2 |
+        MCF_INTC0_IMRL_INT_MASK1;
+    MCF_INTC1_IMRH = 0xffffffff;
+    MCF_INTC1_IMRL =
+        MCF_INTC1_IMRL_INT_MASK31 | MCF_INTC1_IMRL_INT_MASK30 |
+        MCF_INTC1_IMRL_INT_MASK29 | MCF_INTC1_IMRL_INT_MASK28 |
+        MCF_INTC1_IMRL_INT_MASK27 | MCF_INTC1_IMRL_INT_MASK26 |
+        MCF_INTC1_IMRL_INT_MASK25 | MCF_INTC1_IMRL_INT_MASK24 |
+        MCF_INTC1_IMRL_INT_MASK23 | MCF_INTC1_IMRL_INT_MASK22 |
+        MCF_INTC1_IMRL_INT_MASK21 | MCF_INTC1_IMRL_INT_MASK20 |
+        MCF_INTC1_IMRL_INT_MASK19 | MCF_INTC1_IMRL_INT_MASK18 |
+        MCF_INTC1_IMRL_INT_MASK17 | MCF_INTC1_IMRL_INT_MASK16 |
+        MCF_INTC1_IMRL_INT_MASK15 | MCF_INTC1_IMRL_INT_MASK14 |
+        MCF_INTC1_IMRL_INT_MASK13 | MCF_INTC1_IMRL_INT_MASK12 |
+        MCF_INTC1_IMRL_INT_MASK11 | MCF_INTC1_IMRL_INT_MASK10 |
+        MCF_INTC1_IMRL_INT_MASK9 | MCF_INTC1_IMRL_INT_MASK8 |
+        MCF_INTC1_IMRL_INT_MASK7 | MCF_INTC1_IMRL_INT_MASK6 |
+        MCF_INTC1_IMRL_INT_MASK5 | MCF_INTC1_IMRL_INT_MASK4 |
+        MCF_INTC1_IMRL_INT_MASK3 | MCF_INTC1_IMRL_INT_MASK2 |
+        MCF_INTC1_IMRL_INT_MASK1;
+}
+
+/*********************************************************************
+* init_pin_assignments - Pin Assignment and General Purpose I/O      *
+**********************************************************************/
+static void
+init_pin_assignments( void )
+{
+
+    /* Pin assignments for port ADDR
+       Pins are all GPIO inputs
+     */
+    MCF_GPIO_PDDR_APDDR = 0;
+    MCF_GPIO_PAR_AD = MCF_GPIO_PAR_AD_PAR_ADDR23
+        | MCF_GPIO_PAR_AD_PAR_ADDR22
+        | MCF_GPIO_PAR_AD_PAR_ADDR21 | MCF_GPIO_PAR_AD_PAR_DATAL;
+
+    /* Pin assignments for ports DATAH and DATAL
+       Pins are all GPIO inputs
+     */
+    MCF_GPIO_PDDR_DATAH = 0;
+    MCF_GPIO_PDDR_DATAL = 0;
+
+    /* Pin assignments for port BUSCTL
+       Pin /OE        : External bus output enable, /OE
+       Pin /TA        : External bus transfer acknowledge, /TA
+       Pin /TEA       : External bus transfer error acknowledge, /TEA
+       Pin R/W        : External bus read/write indication, R/W
+       Pin TSIZ1      : External bus transfer size TSIZ1 or DMA acknowledge /DACK1
+       Pin TSIZ0      : External bus transfer size TSIZ0 or DMA acknowledge /DACK0
+       Pin /TS        : External bus transfer start, /TS
+       Pin /TIP       : External bus transfer in progess, /TIP
+     */
+    MCF_GPIO_PDDR_BUSCTL = 0;
+    MCF_GPIO_PAR_BUSCTL =
+        MCF_GPIO_PAR_BUSCTL_PAR_OE | MCF_GPIO_PAR_BUSCTL_PAR_TA |
+        MCF_GPIO_PAR_BUSCTL_PAR_TEA( 0x3 ) | MCF_GPIO_PAR_BUSCTL_PAR_RWB |
+        MCF_GPIO_PAR_BUSCTL_PAR_TSIZ1 | MCF_GPIO_PAR_BUSCTL_PAR_TSIZ0 |
+        MCF_GPIO_PAR_BUSCTL_PAR_TS( 0x3 ) |
+        MCF_GPIO_PAR_BUSCTL_PAR_TIP( 0x3 );
+
+    /* Pin assignments for port BS
+       Pin /BS3       : External byte strobe /BS3
+       Pin /BS2       : External byte strobe /BS2
+       Pin /BS1       : External byte strobe /BS1
+       Pin /BS0       : External byte strobe /BS0
+     */
+    MCF_GPIO_PDDR_BS = 0;
+    MCF_GPIO_PAR_BS =
+        MCF_GPIO_PAR_BS_PAR_BS3 | MCF_GPIO_PAR_BS_PAR_BS2 |
+        MCF_GPIO_PAR_BS_PAR_BS1 | MCF_GPIO_PAR_BS_PAR_BS0;
+
+    /* Pin assignments for port CS
+       Pin /CS7       : Chip select /CS7
+       Pin /CS6       : Chip select /CS6
+       Pin /CS5       : Chip select /CS5
+       Pin /CS4       : Chip select /CS4
+       Pin /CS3       : Chip select /CS3
+       Pin /CS2       : Chip select /CS2
+       Pin /CS1       : Chip select /CS1
+     */
+    MCF_GPIO_PDDR_CS = 0;
+    MCF_GPIO_PAR_CS =
+        MCF_GPIO_PAR_CS_PAR_CS7 | MCF_GPIO_PAR_CS_PAR_CS6 |
+        MCF_GPIO_PAR_CS_PAR_CS5 | MCF_GPIO_PAR_CS_PAR_CS4 |
+        MCF_GPIO_PAR_CS_PAR_CS3 | MCF_GPIO_PAR_CS_PAR_CS2 |
+        MCF_GPIO_PAR_CS_PAR_CS1;
+
+    /* Pin assignments for port SDRAM
+       Pin /SD_WE     : SDRAM controller /SD_WE
+       Pin /SD_SCAS   : SDRAM controller /SD_SCAS
+       Pin /SD_SRAS   : SDRAM controller /SD_SRAS
+       Pin /SD_SCKE   : SDRAM controller /SD_SCKE
+       Pin /SD_CS1    : SDRAM controller /SD_CS1
+       Pin /SD_CS0    : SDRAM controller /SD_CS0
+     */
+    MCF_GPIO_PDDR_SDRAM = 0;
+    MCF_GPIO_PAR_SDRAM =
+        MCF_GPIO_PAR_SDRAM_PAR_SDWE | MCF_GPIO_PAR_SDRAM_PAR_SCAS |
+        MCF_GPIO_PAR_SDRAM_PAR_SRAS | MCF_GPIO_PAR_SDRAM_PAR_SCKE |
+        MCF_GPIO_PAR_SDRAM_PAR_SDCS1 | MCF_GPIO_PAR_SDRAM_PAR_SDCS0;
+
+    /* Pin assignments for port FECI2C
+       Pins are all GPIO inputs
+     */
+    MCF_GPIO_PDDR_FECI2C = 0;
+    MCF_GPIO_PAR_FECI2C =
+        MCF_GPIO_PAR_FECI2C_PAR_EMDC_FEC | MCF_GPIO_PAR_FECI2C_PAR_EMDIO_FEC;
+
+    /* Pin assignments for port UARTL
+       Pins are all GPIO inputs
+     */
+    MCF_GPIO_PDDR_UARTL = 0;
+    MCF_GPIO_PAR_UART = 0;
+
+    /* Pin assignments for port UARTH
+       Pin U2TXD      : GPIO input
+       Pin U2RXD      : GPIO input
+       Pin /IRQ2      : Interrupt request /IRQ2 or GPIO
+     */
+    MCF_GPIO_PDDR_UARTH = 0;
+
+    /* Pin assignments for port QSPI
+       Pins are all GPIO inputs
+     */
+    MCF_GPIO_PDDR_QSPI = 0;
+    MCF_GPIO_PAR_QSPI = 0;
+
+    /* Pin assignments for port TIMER
+       Pins are all GPIO inputs
+     */
+    MCF_GPIO_PDDR_TIMER = 0;
+    MCF_GPIO_PAR_TIMER = 0;
+
+    /* Pin assignments for port ETPU
+       Pins are all GPIO inputs
+     */
+    MCF_GPIO_PDDR_ETPU = 0;
+    MCF_GPIO_PAR_ETPU = 0;
+}
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/system/mcf5xxx.S b/20080212/Demo/lwIP_MCF5235_GCC/system/mcf5xxx.S
new file mode 100644
index 000000000..d810a2fdc
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/system/mcf5xxx.S
@@ -0,0 +1,249 @@
+/*
+ * Lowest level routines for all ColdFire processors. Based on the
+ * MCF523x examples from Freescale.
+ *
+ * Freescale explicitly grants the redistribution and modification
+ * of these source files. The complete licensing information is
+ * available in the file LICENSE_FREESCALE.TXT.
+ *
+ * Modifications Copyright (c) 2006 Christian Walter 
+ *
+ * File: $Id: mcf5xxx.S,v 1.3 2006/09/24 22:50:23 wolti Exp $
+ */
+
+  .global asm_set_ipl
+  .global _asm_set_ipl
+  .global mcf5xxx_wr_cacr
+  .global _mcf5xxx_wr_cacr
+  .global mcf5xxx_wr_acr0
+  .global _mcf5xxx_wr_acr0
+  .global mcf5xxx_wr_acr1
+  .global _mcf5xxx_wr_acr1
+  .global mcf5xxx_wr_acr2
+  .global _mcf5xxx_wr_acr2
+  .global mcf5xxx_wr_acr3
+  .global _mcf5xxx_wr_acr3
+  .global mcf5xxx_wr_other_sp
+  .global _mcf5xxx_wr_other_sp
+  .global mcf5xxx_wr_other_a7
+  .global _mcf5xxx_wr_other_a7
+  .global mcf5xxx_wr_vbr
+  .global _mcf5xxx_wr_vbr
+  .global mcf5xxx_wr_macsr
+  .global _mcf5xxx_wr_macsr
+  .global mcf5xxx_wr_mask
+  .global _mcf5xxx_wr_mask
+  .global mcf5xxx_wr_acc0
+  .global _mcf5xxx_wr_acc0
+  .global mcf5xxx_wr_accext01
+  .global _mcf5xxx_wr_accext01
+  .global mcf5xxx_wr_accext23
+  .global _mcf5xxx_wr_accext23
+  .global mcf5xxx_wr_acc1
+  .global _mcf5xxx_wr_acc1
+  .global mcf5xxx_wr_acc2
+  .global _mcf5xxx_wr_acc2
+  .global mcf5xxx_wr_acc3
+  .global _mcf5xxx_wr_acc3
+  .global mcf5xxx_wr_sr
+  .global _mcf5xxx_wr_sr
+  .global mcf5xxx_wr_rambar0
+  .global _mcf5xxx_wr_rambar0
+  .global mcf5xxx_wr_rambar1
+  .global _mcf5xxx_wr_rambar1
+  .global mcf5xxx_wr_mbar
+  .global _mcf5xxx_wr_mbar
+  .global mcf5xxx_wr_mbar0
+  .global _mcf5xxx_wr_mbar0
+  .global mcf5xxx_wr_mbar1
+  .global _mcf5xxx_wr_mbar1
+
+  .text
+
+/********************************************************************/
+/*
+ * This routines changes the IPL to the value passed into the routine.
+ * It also returns the old IPL value back.
+ * Calling convention from C:
+ *   old_ipl = asm_set_ipl(new_ipl);
+ * For the Diab Data C compiler, it passes return value thru D0.
+ * Note that only the least significant three bits of the passed
+ * value are used.
+ */
+
+asm_set_ipl:
+_asm_set_ipl:
+  link  a6,#-8
+  movem.l d6-d7,(sp)
+
+  move.w  sr,d7   /* current sr  */
+
+  move.l  d7,d0   /* prepare return value  */
+  andi.l  #0x0700,d0  /* mask out IPL  */
+  lsr.l #8,d0   /* IPL   */
+
+  move.l  8(a6),d6  /* get argument  */
+  andi.l  #0x07,d6    /* least significant three bits  */
+  lsl.l #8,d6   /* move over to make mask  */
+
+  andi.l  #0x0000F8FF,d7  /* zero out current IPL  */
+  or.l  d6,d7     /* place new IPL in sr   */
+  move.w  d7,sr
+
+  movem.l (sp),d6-d7
+  lea   8(sp),sp
+  unlk  a6
+  rts
+
+/********************************************************************/
+/*
+ * These routines write to the special purpose registers in the ColdFire
+ * core.  Since these registers are write-only in the supervisor model,
+ * no corresponding read routines exist.
+ */
+
+mcf5xxx_wr_cacr:
+_mcf5xxx_wr_cacr:
+    move.l  4(sp),d0
+    .long   0x4e7b0002      /* movec d0,cacr   */
+    nop
+    rts
+
+mcf5xxx_wr_acr0:
+_mcf5xxx_wr_acr0:
+    move.l  4(sp),d0
+    .long   0x4e7b0004      /* movec d0,ACR0  */
+    nop
+    rts
+
+mcf5xxx_wr_acr1:
+_mcf5xxx_wr_acr1:
+    move.l  4(sp),d0
+    .long   0x4e7b0005      /* movec d0,ACR1  */
+    nop
+    rts
+
+mcf5xxx_wr_acr2:
+_mcf5xxx_wr_acr2:
+    move.l  4(sp),d0
+    .long   0x4e7b0006      /* movec d0,ACR2  */
+    nop
+    rts
+
+mcf5xxx_wr_acr3:
+_mcf5xxx_wr_acr3:
+    move.l  4(sp),d0
+    .long   0x4e7b0007      /* movec d0,ACR3  */
+    nop
+    rts
+
+mcf5xxx_wr_other_sp:
+_mcf5xxx_wr_other_sp:
+mcf5xxx_wr_other_a7:
+_mcf5xxx_wr_other_a7:
+  move.l  4(sp),d0
+  .long 0x4e7b0800    /* movec d0,OTHER_A7 */
+  nop
+  rts
+
+mcf5xxx_wr_vbr:
+_mcf5xxx_wr_vbr:
+  move.l  4(sp),d0
+  .long 0x4e7b0801    /* movec d0,VBR */
+  nop
+  rts
+
+mcf5xxx_wr_macsr:
+_mcf5xxx_wr_macsr:
+    move.l  4(sp),d0
+    .long   0x4e7b0804      /* movec d0,MACSR */
+    nop
+    rts
+
+mcf5xxx_wr_mask:
+_mcf5xxx_wr_mask:
+    move.l  4(sp),d0
+    .long   0x4e7b0805      /* movec d0,MASK  */
+    nop
+    rts
+
+mcf5xxx_wr_acc0:
+_mcf5xxx_wr_acc0:
+    move.l  4(sp),d0
+    .long   0x4e7b0806      /* movec d0,ACC0  */
+    nop
+    rts
+
+mcf5xxx_wr_accext01:
+_mcf5xxx_wr_accext01:
+    move.l  4(sp),d0
+    .long   0x4e7b0807      /* movec d0,ACCEXT01  */
+    nop
+    rts
+
+mcf5xxx_wr_accext23:
+_mcf5xxx_wr_accext23:
+    move.l  4(sp),d0
+    .long   0x4e7b0808      /* movec d0,ACCEXT23  */
+    nop
+    rts
+
+mcf5xxx_wr_acc1:
+_mcf5xxx_wr_acc1:
+    move.l  4(sp),d0
+    .long   0x4e7b0809      /* movec d0,ACC1  */
+    nop
+    rts
+
+mcf5xxx_wr_acc2:
+_mcf5xxx_wr_acc2:
+    move.l  4(sp),d0
+    .long   0x4e7b080A      /* movec d0,ACC2  */
+    nop
+    rts
+
+mcf5xxx_wr_acc3:
+_mcf5xxx_wr_acc3:
+    move.l  4(sp),d0
+    .long   0x4e7b080B      /* movec d0,ACC3  */
+    nop
+    rts
+
+mcf5xxx_wr_sr:
+_mcf5xxx_wr_sr:
+  move.l  4(sp),d0
+  move.w  d0,SR
+  rts
+
+mcf5xxx_wr_rambar0:
+_mcf5xxx_wr_rambar0:
+    move.l  4(sp),d0
+    .long   0x4e7b0C04      /* movec d0,RAMBAR0 */
+    nop
+    rts
+
+mcf5xxx_wr_rambar1:
+_mcf5xxx_wr_rambar1:
+    move.l  4(sp),d0
+    .long   0x4e7b0C05      /* movec d0,RAMBAR1 */
+    nop
+    rts
+
+mcf5xxx_wr_mbar:
+_mcf5xxx_wr_mbar:
+mcf5xxx_wr_mbar0:
+_mcf5xxx_wr_mbar0:
+    move.l  4(sp),d0
+    .long   0x4e7b0C0F      /* movec d0,MBAR0 */
+    nop
+    rts
+
+mcf5xxx_wr_mbar1:
+_mcf5xxx_wr_mbar1:
+    move.l  4(sp),d0
+    .long   0x4e7b0C0E      /* movec d0,MBAR1 */
+    nop
+    rts
+
+  .end
+/********************************************************************/
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/system/newlib.c b/20080212/Demo/lwIP_MCF5235_GCC/system/newlib.c
new file mode 100644
index 000000000..665e1eda2
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/system/newlib.c
@@ -0,0 +1,156 @@
+/*
+    FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    FreeRTOS is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with FreeRTOS; if not, write to the Free Software
+    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+    A special exception to the GPL can be applied should you wish to distribute
+    a combined work that includes FreeRTOS, without being obliged to provide
+    the source code for any proprietary components.  See the licensing section
+    of http://www.FreeRTOS.org for full details of how and when the exception
+    can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+/* ------------------------ System includes ------------------------------- */
+#include 
+#include 
+#include 
+#include 
+
+/* ------------------------ FreeRTOS includes ----------------------------- */
+#include 
+#include 
+
+/* ------------------------ Prototypes ------------------------------------ */
+void vSerialPutStringNOISR( xComPortHandle pxPort,
+                            const signed portCHAR * const pcString,
+                            unsigned portSHORT usStringLength );
+
+/* ------------------------ Start implementation -------------------------- */
+void
+_exit( int status )
+{
+    asm volatile    ( "halt" );
+
+    for( ;; );
+}
+
+pid_t
+getpid( void )
+{
+    return 0;
+}
+
+int
+kill( pid_t pid, int sig )
+{
+    _exit( 0 );
+}
+
+int
+close( int fd )
+{
+    return 0;
+}
+
+int
+fstat( int fd, struct stat *buf )
+{
+    buf->st_mode = S_IFCHR;
+    buf->st_blksize = 0;
+    return 0;
+}
+
+ssize_t
+write( int fd, const void *buf, size_t nbytes )
+{
+    ssize_t res = nbytes;
+    extern xComPortHandle xSTDComPort;
+    switch ( fd )
+    {
+        case STDERR_FILENO:
+            vSerialPutStringNOISR( xSTDComPort,
+                                   ( const signed portCHAR * const )buf,
+                                   ( unsigned portSHORT )nbytes );
+            break;
+        case STDOUT_FILENO:
+            vSerialPutString( xSTDComPort,
+                              ( const signed portCHAR * const)buf,
+                              ( unsigned portSHORT )nbytes );
+            break;
+        default:
+            errno = EIO;
+            res = -1;
+            break;
+    }
+    return res;
+}
+
+int
+read( int fd, void *buf, size_t nbytes )
+{
+    switch ( fd )
+    {
+        default:
+            errno = EIO;
+            return -1;
+    }
+}
+
+int
+isatty( int fd )
+{
+    return 0;
+}
+
+off_t
+lseek( int fd, off_t offset, int whence )
+{
+    errno = EIO;
+    return ( off_t ) - 1;
+}
+
+extern char     _end[];
+char           *heap_ptr;
+
+void           *
+sbrk( ptrdiff_t nbytes )
+{
+    char           *base;
+
+    if( !heap_ptr )
+        heap_ptr = ( char * )&_end;
+    base = heap_ptr;
+    heap_ptr += nbytes;
+
+    return base;
+}
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/system/serial.c b/20080212/Demo/lwIP_MCF5235_GCC/system/serial.c
new file mode 100644
index 000000000..24fafdf5a
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/system/serial.c
@@ -0,0 +1,308 @@
+/*
+    FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    FreeRTOS is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with FreeRTOS; if not, write to the Free Software
+    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+    A special exception to the GPL can be applied should you wish to distribute
+    a combined work that includes FreeRTOS, without being obliged to provide
+    the source code for any proprietary components.  See the licensing section
+    of http://www.FreeRTOS.org for full details of how and when the exception
+    can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+/* ------------------------ MCF523x includes ------------------------------ */
+#include "mcf5xxx.h"
+#include "mcf523x.h"
+
+/* ------------------------ FreeRTOS includes ----------------------------- */
+#include "FreeRTOS.h"
+#include "queue.h"
+#include "task.h"
+
+#include "serial.h"
+
+/* ----------------------- Defines ----------------------------------------- */
+#define BAUDRATE_VALUE(fsys, baud)      ( ( fsys )/(32UL * baud) )
+#define MCF_UART_VECTOR                 ( 64 + 13 )
+#define COM_NIFACE                      1
+#define COM_BLOCK_RETRYTIME             10
+
+/* ------------------------ Static functions ------------------------------ */
+static void     prvSerialISR( void );
+
+/* ------------------------ Static variables ------------------------------ */
+typedef struct
+{
+    portBASE_TYPE xInitialized;
+    xQueueHandle xRXChars;
+    xQueueHandle xTXChars;
+} xComPortIF_t;
+
+static xComPortIF_t xComPortIF[ COM_NIFACE ];
+
+/* ------------------------ Begin implementation -------------------------- */
+xComPortHandle
+xSerialPortInitMinimal( unsigned portLONG ulWantedBaud,
+                        unsigned portBASE_TYPE uxQueueLength )
+{
+    extern void     ( *__RAMVEC[] ) (  );
+    xComPortHandle xReturn;
+    portBASE_TYPE xOldIPL;
+
+    /* Create the queues used to hold Rx and Tx characters. */
+    xComPortIF[ 0 ].xRXChars =
+        xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE )sizeof( signed portCHAR ) );
+    xComPortIF[ 0 ].xTXChars =
+        xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE )sizeof( signed portCHAR ) );
+
+    /* If the queues were created correctly then setup the serial port hardware. */
+    if( ( xComPortIF[ 0 ].xRXChars != 0 ) && ( xComPortIF[ 0 ].xTXChars != 0 ) )
+    {
+        xOldIPL = portSET_IPL( portIPL_MAX );
+
+        /* UART 0: Reset transmitter, receiver and mode register pointer */
+        MCF_UART_UCR0 = MCF_UART_UCR_MISC( 0x3 );
+        MCF_UART_UCR0 = MCF_UART_UCR_MISC( 0x2 );
+        MCF_UART_UCR0 = MCF_UART_UCR_MISC( 0x1 );
+
+        /* Enable receive interrupts. */
+        MCF_UART_UIMR0 = MCF_UART_UIMR_RXRDY_FU;
+
+        /* 8 Databits, 1 Stopbit and no parity */
+        MCF_UART_UMR0 = MCF_UART_UMR_PM( 0x3 ) | MCF_UART_UMR_SB( 0x7 ) | MCF_UART_UMR_BC( 0x3 );
+
+        /* UART 0 Clocking */
+        MCF_UART_UCSR0 = MCF_UART_UCSR_RCS( 0xd ) | MCF_UART_UCSR_TCS( 0xd );
+        MCF_UART_UBG10 = BAUDRATE_VALUE( FSYS_2, ulWantedBaud ) >> 8U;
+        MCF_UART_UBG20 = BAUDRATE_VALUE( FSYS_2, ulWantedBaud ) & 0xFFU;
+
+        /* UART 0: Enable interrupts */
+        __RAMVEC[MCF_UART_VECTOR] = prvSerialISR;
+        MCF_INTC0_ICR13 = MCF_INTC0_ICRn_IL( 0x2 ) | MCF_INTC0_ICRn_IP( 0x1 );
+        MCF_INTC0_IMRL &= ~MCF_INTC0_IMRL_INT_MASK13;
+
+        /* UART 0 Miscellaneous */
+        MCF_UART_UACR0 = 0;
+
+        /* UART 0: Enable pins */
+        MCF_GPIO_PAR_UART = MCF_GPIO_PAR_UART_PAR_U0RXD | MCF_GPIO_PAR_UART_PAR_U0TXD;
+
+        /* Enable the UART. */
+        MCF_UART_UCR0 = MCF_UART_UCR_RXC( 0x1 ) | MCF_UART_UCR_TXC( 0x1 );
+
+        xComPortIF[ 0 ].xInitialized = TRUE;
+        xReturn = ( xComPortHandle ) &xComPortIF[ 0 ];
+
+        ( void )portSET_IPL( xOldIPL );
+    }
+    else
+    {
+        xReturn = ( xComPortHandle ) 0;
+    }
+
+    return xReturn;
+}
+
+signed          portBASE_TYPE
+xSerialGetChar( xComPortHandle pxPort, signed portCHAR * pcRxedChar,
+                portTickType xBlockTime )
+{
+    int i;
+    portBASE_TYPE xResult = pdFALSE;
+    /* Lookup the correct interface. */
+    for( i = 0; i < COM_NIFACE; i++ )
+    {
+        if( pxPort == ( xComPortHandle ) &xComPortIF[ i ] )
+        {
+            break;
+        }
+    }
+    /* This COM port is available. */
+    if( ( i != COM_NIFACE ) && xComPortIF[ i ].xInitialized )
+    {
+        /* Get the next character from the buffer.  Return false if no characters
+         * are available, or arrive before xBlockTime expires.
+         */
+        if( xQueueReceive( xComPortIF[ i ].xRXChars, pcRxedChar, xBlockTime ) )
+        {
+            xResult = pdTRUE;
+        }
+    }
+    return xResult;
+}
+
+void
+vSerialPutString( xComPortHandle pxPort, const signed portCHAR *
+                  const pcString, unsigned portSHORT usStringLength )
+{
+    int i;
+    signed portCHAR *pChNext;
+
+    /* Send each character in the string, one at a time. */
+    pChNext = ( signed portCHAR * )pcString;
+    for( i = 0; i < usStringLength; i++ )
+    {
+        /* Block until character has been transmitted. */
+        while( xSerialPutChar( pxPort, *pChNext, COM_BLOCK_RETRYTIME ) != pdTRUE ); pChNext++;
+    }
+}
+
+signed          portBASE_TYPE
+xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar,
+                portTickType xBlockTime )
+{
+    int i;
+    portBASE_TYPE xResult = pdFALSE;
+    portBASE_TYPE xOldIPL;
+    /* Lookup the correct interface. */
+    for( i = 0; i < COM_NIFACE; i++ )
+    {
+        if( pxPort == ( xComPortHandle ) &xComPortIF[ i ] )
+        {
+            break;
+        }
+    }
+    /* This COM port is available. */
+    if( ( i != COM_NIFACE ) && xComPortIF[ i ].xInitialized )
+    {
+        /* Place the character in the queue of characters to be transmitted. */
+        if( xQueueSend( xComPortIF[ i ].xTXChars, &cOutChar, xBlockTime ) == pdPASS )
+        {
+            /* Turn on the Tx interrupt so the ISR will remove the character from the
+             * queue and send it. */
+            MCF_UART_UIMR0 = MCF_UART_UIMR_TXRDY | MCF_UART_UIMR_RXRDY_FU;
+            xResult = pdTRUE;
+        }
+    }
+    return xResult;
+}
+
+signed          portBASE_TYPE
+xSerialPutCharNOISR( xComPortHandle pxPort, signed portCHAR cOutChar )
+{
+    int i;
+    portBASE_TYPE xResult = pdFALSE;
+    portBASE_TYPE xOldIPL = portSET_IPL( portIPL_MAX );
+    /* Lookup the correct interface. */
+    for( i = 0; i < COM_NIFACE; i++ )
+    {
+        if( pxPort == ( xComPortHandle ) &xComPortIF[ i ] )
+        {
+            break;
+        }
+    }
+    /* This COM port is available. Support for this only available for COM1 right now. */
+    if( ( i != COM_NIFACE ) && ( i == 0 ) )
+    {
+        /* Wait until the transmit buffer is ready. */
+        while( !( MCF_UART_USR0 & MCF_UART_USR_TXRDY ) );
+        /* Place the character in the transmit buffer. */
+        MCF_UART_UTB0 = cOutChar;
+        xResult = pdTRUE;
+    }
+    ( void )portSET_IPL( xOldIPL );
+    return xResult;
+}
+
+void
+vSerialPutStringNOISR( xComPortHandle pxPort, const signed portCHAR *
+                       const pcString, unsigned portSHORT usStringLength )
+{
+    int i;
+    signed portCHAR *pChNext;
+    portBASE_TYPE xOldIPL = portSET_IPL( portIPL_MAX );
+
+    /* Send each character in the string, one at a time. */
+    pChNext = ( signed portCHAR * )pcString;
+    for( i = 0; i < usStringLength; i++ )
+    {
+        /* Block until character has been transmitted. */
+        while( xSerialPutCharNOISR( pxPort, *pChNext ) != pdTRUE );
+        pChNext++;
+    }
+    ( void )portSET_IPL( xOldIPL );
+}
+
+void
+vSerialClose( xComPortHandle xPort )
+{
+    /* Not supported as not required by the demo application. */
+}
+
+void
+prvSerialISR( void )
+{
+    static signed portCHAR cChar;
+    static portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByRx = pdFALSE;
+
+    /* We have to remvoe the effect of the GCC. Please note that the
+     * __attribute__ ((interrupt_handler)) does not work here because we
+     * have to do the storing of the registers ourself. Another problem
+     * is the usage of a frame pointer which is unlinked on entry.
+     */
+#if _GCC_USES_FP == 1
+    asm volatile ( "unlk %fp\n\t" );
+#endif
+    /* This ISR can cause a context switch, so the first statement must be
+     * a call to the portENTER_SWITCHING_ISR() macro. This must be BEFORE any
+     * variable declarations.
+     */
+    portENTER_SWITCHING_ISR();
+
+    /* Ready to send a character from the buffer. */
+    if( MCF_UART_USR0 & MCF_UART_USR_TXRDY )
+    {
+        /* Transmit buffer is ready. Test if there are characters available. */
+        if( xQueueReceiveFromISR( xComPortIF[ 0 ].xTXChars, &cChar, &xTaskWokenByTx ) ==
+            pdTRUE )
+        {
+            /* A character was retrieved from the queue so can be sent. */
+            MCF_UART_UTB0 = cChar;
+        }
+        else
+        {
+            /* Leave only receiver enabled. */
+            MCF_UART_UIMR0 = MCF_UART_UIMR_RXRDY_FU;
+        }
+    }
+    if( MCF_UART_USR0 & MCF_UART_USR_RXRDY )
+    {
+        cChar = MCF_UART_URB0;
+        xTaskWokenByRx =
+            xQueueSendFromISR( xComPortIF[ 0].xRXChars, &cChar, xTaskWokenByRx );
+    }
+    /* Exit the ISR.  If a task was woken by either a character being
+     * or transmitted then a context switch will occur.
+     */
+    portEXIT_SWITCHING_ISR( ( xTaskWokenByTx || xTaskWokenByRx ) );
+}
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/system/vector.S b/20080212/Demo/lwIP_MCF5235_GCC/system/vector.S
new file mode 100644
index 000000000..debbac3c0
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/system/vector.S
@@ -0,0 +1,312 @@
+/*
+    FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    FreeRTOS is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with FreeRTOS; if not, write to the Free Software
+    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+    A special exception to the GPL can be applied should you wish to distribute
+    a combined work that includes FreeRTOS, without being obliged to provide
+    the source code for any proprietary components.  See the licensing section
+    of http://www.FreeRTOS.org for full details of how and when the exception
+    can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+  .extern __stack
+  .extern start
+  .extern fec_handler
+  .extern fec_if
+  .extern decrement_timers
+  .global __RAMVEC
+  .global __ROMVEC
+
+  .equ    MCF_PIT_PCSR0, IPSBAR + 0x150000
+  .equ    MCF_PIT_PCSR_PIF, 0x0004
+
+  .section  .vector_rom, "x"
+__ROMVEC:
+  .long   __stack               /* Reset: Initial Stack Pointer */
+  .long   start                 /* Reset: Initial Program Counter */
+  .long   VecDefault            /* Bus Error */
+  .long   VecDefault            /* Address Error */
+  .long   VecDefault            /* Illegal Instruction */
+  .long   VecDefault            /* Zero Divison */
+  .space  4                     /* reserved */
+  .space  4                     /* reserved */
+  .long   VecDefault            /* Privilege Violation */
+  .long   VecDefault            /* Trace */
+  .long   VecDefault            /* Unimplemented line-a opcode */
+  .long   VecDefault            /* Unimplemented line-b opcode */
+  .long   VecDefault            /* Non-PC breakpoint debug interrupt */
+  .long   VecDefault            /* PC breakpoint debug interrupt */
+  .long   VecDefault            /* Format Error */
+  .long   VecDefault            /* Uninitialized Interrupt */
+  .org    0x60
+  .long   IRQSpurious           /* Spurious Interrupt */
+  .long   IRQDefault            /* Level 1 Interrupt */
+  .long   IRQDefault            /* Level 2 Interrupt */
+  .long   IRQDefault            /* Level 3 Interrupt */
+  .long   IRQDefault            /* Level 4 Interrupt */
+  .long   IRQDefault            /* Level 5 Interrupt */
+  .long   IRQDefault            /* Level 6 Interrupt */
+  .long   IRQDefault            /* Level 7 Interrupt */
+  .org    0x80
+  .long   TrapDefault           /* TRAP 0 */
+  .long   TrapDefault           /* TRAP 1 */
+  .long   TrapDefault           /* TRAP 2 */
+  .long   TrapDefault           /* TRAP 3 */
+  .long   TrapDefault           /* TRAP 4 */
+  .long   TrapDefault           /* TRAP 5 */
+  .long   TrapDefault           /* TRAP 6 */
+  .long   TrapDefault           /* TRAP 7 */
+  .long   TrapDefault           /* TRAP 8 */
+  .long   TrapDefault           /* TRAP 9 */
+  .long   TrapDefault           /* TRAP 10 */
+  .long   TrapDefault           /* TRAP 11 */
+  .long   TrapDefault           /* TRAP 12 */
+  .long   TrapDefault           /* TRAP 13 */
+  .long   TrapDefault           /* TRAP 14 */
+  .long   TrapDefault           /* TRAP 15 */
+  .org    0x100
+  .long   IRQDefault            /* User-Defined Interrupt 0 */
+  .long   IRQDefault            /* User-Defined Interrupt 1 */
+  .long   IRQDefault            /* User-Defined Interrupt 2 */
+  .long   IRQDefault            /* User-Defined Interrupt 3 */
+  .long   IRQDefault            /* User-Defined Interrupt 4 */
+  .long   IRQDefault            /* User-Defined Interrupt 5 */
+  .long   IRQDefault            /* User-Defined Interrupt 6 */
+  .long   IRQDefault            /* User-Defined Interrupt 7 */
+  .long   IRQDefault            /* User-Defined Interrupt 8 */
+  .long   IRQDefault            /* User-Defined Interrupt 9 */
+  .long   IRQDefault            /* User-Defined Interrupt 10 */
+  .long   IRQDefault            /* User-Defined Interrupt 11 */
+  .long   IRQDefault            /* User-Defined Interrupt 12 */
+  .long   IRQDefault            /* User-Defined Interrupt 13 */
+  .long   IRQDefault            /* User-Defined Interrupt 14 */
+  .long   IRQDefault            /* User-Defined Interrupt 15 */
+  .long   IRQDefault            /* User-Defined Interrupt 16 */
+  .long   IRQDefault            /* User-Defined Interrupt 17 */
+  .long   IRQDefault            /* User-Defined Interrupt 18 */
+  .long   IRQDefault            /* User-Defined Interrupt 19 */
+  .long   IRQDefault            /* User-Defined Interrupt 20 */
+  .long   IRQDefault            /* User-Defined Interrupt 21 */
+  .long   IRQDefault            /* User-Defined Interrupt 22 */
+  .long   IRQDefault            /* Transmit frame interrupt */
+  .long   IRQDefault            /* Transmit buffer interrupt */
+  .long   IRQDefault            /* Transmit FIFO underrun */
+  .long   IRQDefault            /* Collision retry limit */
+  .long   IRQDefault            /* Receive frame interrupt */
+  .long   IRQDefault            /* Receive buffer interrupt */
+  .long   IRQDefault            /* MII interrupt */
+  .long   IRQDefault            /* Late collision */
+  .long   IRQDefault            /* Heartbeat error */
+  .long   IRQDefault            /* Graceful stop complete */
+  .long   IRQDefault            /* Ethernet bus error */
+  .long   IRQDefault            /* Babbling transmit error */
+  .long   IRQDefault            /* Babbling receive error */
+  .long   IRQDefault            /* Timer interrupt */
+  .long   IRQDefault            /* User-Defined Interrupt 37 */
+  .long   IRQDefault            /* User-Defined Interrupt 38 */
+  .long   IRQDefault            /* User-Defined Interrupt 39 */
+  .long   IRQDefault            /* User-Defined Interrupt 40 */
+  .long   IRQDefault            /* User-Defined Interrupt 41 */
+  .long   IRQDefault            /* User-Defined Interrupt 42 */
+  .long   IRQDefault            /* User-Defined Interrupt 43 */
+  .long   IRQDefault            /* User-Defined Interrupt 44 */
+  .long   IRQDefault            /* User-Defined Interrupt 45 */
+  .long   IRQDefault            /* User-Defined Interrupt 46 */
+  .long   IRQDefault            /* User-Defined Interrupt 47 */
+  .long   IRQDefault            /* User-Defined Interrupt 48 */
+  .long   IRQDefault            /* User-Defined Interrupt 49 */
+  .long   IRQDefault            /* User-Defined Interrupt 50 */
+  .long   IRQDefault            /* User-Defined Interrupt 51 */
+  .long   IRQDefault            /* User-Defined Interrupt 52 */
+  .long   IRQDefault            /* User-Defined Interrupt 53 */
+  .long   IRQDefault            /* User-Defined Interrupt 54 */
+  .long   IRQDefault            /* User-Defined Interrupt 55 */
+  .long   IRQDefault            /* User-Defined Interrupt 56 */
+  .long   IRQDefault            /* User-Defined Interrupt 57 */
+  .long   IRQDefault            /* User-Defined Interrupt 58 */
+  .long   IRQDefault            /* User-Defined Interrupt 59 */
+  .long   IRQDefault            /* User-Defined Interrupt 60 */
+  .long   IRQDefault            /* User-Defined Interrupt 61 */
+  .long   IRQDefault            /* User-Defined Interrupt 62 */
+  .long   IRQDefault            /* User-Defined Interrupt 63 */
+  .long   IRQDefault            /* User-Defined Interrupt 64 */
+  .long   IRQDefault            /* User-Defined Interrupt 65 */
+  .long   IRQDefault            /* User-Defined Interrupt 66 */
+  .long   IRQDefault            /* User-Defined Interrupt 67 */
+  .long   IRQDefault            /* User-Defined Interrupt 68 */
+  .long   IRQDefault            /* User-Defined Interrupt 69 */
+  .long   IRQDefault            /* User-Defined Interrupt 70 */
+  .long   IRQDefault            /* User-Defined Interrupt 71 */
+  .long   IRQDefault            /* User-Defined Interrupt 72 */
+  .long   IRQDefault            /* User-Defined Interrupt 73 */
+  .long   IRQDefault            /* User-Defined Interrupt 74 */
+  .long   IRQDefault            /* User-Defined Interrupt 75 */
+  .long   IRQDefault            /* User-Defined Interrupt 76 */
+  .long   IRQDefault            /* User-Defined Interrupt 77 */
+  .long   IRQDefault            /* User-Defined Interrupt 78 */
+  .long   IRQDefault            /* User-Defined Interrupt 79 */
+  .long   IRQDefault            /* User-Defined Interrupt 80 */
+  .long   IRQDefault            /* User-Defined Interrupt 81 */
+  .long   IRQDefault            /* User-Defined Interrupt 82 */
+  .long   IRQDefault            /* User-Defined Interrupt 83 */
+  .long   IRQDefault            /* User-Defined Interrupt 84 */
+  .long   IRQDefault            /* User-Defined Interrupt 85 */
+  .long   IRQDefault            /* User-Defined Interrupt 86 */
+  .long   IRQDefault            /* User-Defined Interrupt 87 */
+  .long   IRQDefault            /* User-Defined Interrupt 88 */
+  .long   IRQDefault            /* User-Defined Interrupt 89 */
+  .long   IRQDefault            /* User-Defined Interrupt 90 */
+  .long   IRQDefault            /* User-Defined Interrupt 91 */
+  .long   IRQDefault            /* User-Defined Interrupt 92 */
+  .long   IRQDefault            /* User-Defined Interrupt 93 */
+  .long   IRQDefault            /* User-Defined Interrupt 94 */
+  .long   IRQDefault            /* User-Defined Interrupt 95 */
+  .long   IRQDefault            /* User-Defined Interrupt 96 */
+  .long   IRQDefault            /* User-Defined Interrupt 97 */
+  .long   IRQDefault            /* User-Defined Interrupt 98 */
+  .long   IRQDefault            /* User-Defined Interrupt 99 */
+  .long   IRQDefault            /* User-Defined Interrupt 100 */
+  .long   IRQDefault            /* User-Defined Interrupt 101 */
+  .long   IRQDefault            /* User-Defined Interrupt 102 */
+  .long   IRQDefault            /* User-Defined Interrupt 103 */
+  .long   IRQDefault            /* User-Defined Interrupt 104 */
+  .long   IRQDefault            /* User-Defined Interrupt 105 */
+  .long   IRQDefault            /* User-Defined Interrupt 106 */
+  .long   IRQDefault            /* User-Defined Interrupt 107 */
+  .long   IRQDefault            /* User-Defined Interrupt 108 */
+  .long   IRQDefault            /* User-Defined Interrupt 109 */
+  .long   IRQDefault            /* User-Defined Interrupt 110 */
+  .long   IRQDefault            /* User-Defined Interrupt 111 */
+  .long   IRQDefault            /* User-Defined Interrupt 112 */
+  .long   IRQDefault            /* User-Defined Interrupt 113 */
+  .long   IRQDefault            /* User-Defined Interrupt 114 */
+  .long   IRQDefault            /* User-Defined Interrupt 115 */
+  .long   IRQDefault            /* User-Defined Interrupt 116 */
+  .long   IRQDefault            /* User-Defined Interrupt 117 */
+  .long   IRQDefault            /* User-Defined Interrupt 118 */
+  .long   IRQDefault            /* User-Defined Interrupt 119 */
+  .long   IRQDefault            /* User-Defined Interrupt 120 */
+  .long   IRQDefault            /* User-Defined Interrupt 121 */
+  .long   IRQDefault            /* User-Defined Interrupt 122 */
+  .long   IRQDefault            /* User-Defined Interrupt 123 */
+  .long   IRQDefault            /* User-Defined Interrupt 124 */
+  .long   IRQDefault            /* User-Defined Interrupt 125 */
+  .long   IRQDefault            /* User-Defined Interrupt 126 */
+  .long   IRQDefault            /* User-Defined Interrupt 127 */
+  .long   IRQDefault            /* User-Defined Interrupt 128 */
+  .long   IRQDefault            /* User-Defined Interrupt 129 */
+  .long   IRQDefault            /* User-Defined Interrupt 130 */
+  .long   IRQDefault            /* User-Defined Interrupt 131 */
+  .long   IRQDefault            /* User-Defined Interrupt 132 */
+  .long   IRQDefault            /* User-Defined Interrupt 133 */
+  .long   IRQDefault            /* User-Defined Interrupt 134 */
+  .long   IRQDefault            /* User-Defined Interrupt 135 */
+  .long   IRQDefault            /* User-Defined Interrupt 136 */
+  .long   IRQDefault            /* User-Defined Interrupt 137 */
+  .long   IRQDefault            /* User-Defined Interrupt 138 */
+  .long   IRQDefault            /* User-Defined Interrupt 139 */
+  .long   IRQDefault            /* User-Defined Interrupt 140 */
+  .long   IRQDefault            /* User-Defined Interrupt 141 */
+  .long   IRQDefault            /* User-Defined Interrupt 142 */
+  .long   IRQDefault            /* User-Defined Interrupt 143 */
+  .long   IRQDefault            /* User-Defined Interrupt 144 */
+  .long   IRQDefault            /* User-Defined Interrupt 145 */
+  .long   IRQDefault            /* User-Defined Interrupt 146 */
+  .long   IRQDefault            /* User-Defined Interrupt 147 */
+  .long   IRQDefault            /* User-Defined Interrupt 148 */
+  .long   IRQDefault            /* User-Defined Interrupt 149 */
+  .long   IRQDefault            /* User-Defined Interrupt 150 */
+  .long   IRQDefault            /* User-Defined Interrupt 151 */
+  .long   IRQDefault            /* User-Defined Interrupt 152 */
+  .long   IRQDefault            /* User-Defined Interrupt 153 */
+  .long   IRQDefault            /* User-Defined Interrupt 154 */
+  .long   IRQDefault            /* User-Defined Interrupt 155 */
+  .long   IRQDefault            /* User-Defined Interrupt 156 */
+  .long   IRQDefault            /* User-Defined Interrupt 157 */
+  .long   IRQDefault            /* User-Defined Interrupt 158 */
+  .long   IRQDefault            /* User-Defined Interrupt 159 */
+  .long   IRQDefault            /* User-Defined Interrupt 160 */
+  .long   IRQDefault            /* User-Defined Interrupt 161 */
+  .long   IRQDefault            /* User-Defined Interrupt 162 */
+  .long   IRQDefault            /* User-Defined Interrupt 163 */
+  .long   IRQDefault            /* User-Defined Interrupt 164 */
+  .long   IRQDefault            /* User-Defined Interrupt 165 */
+  .long   IRQDefault            /* User-Defined Interrupt 166 */
+  .long   IRQDefault            /* User-Defined Interrupt 167 */
+  .long   IRQDefault            /* User-Defined Interrupt 168 */
+  .long   IRQDefault            /* User-Defined Interrupt 169 */
+  .long   IRQDefault            /* User-Defined Interrupt 170 */
+  .long   IRQDefault            /* User-Defined Interrupt 171 */
+  .long   IRQDefault            /* User-Defined Interrupt 172 */
+  .long   IRQDefault            /* User-Defined Interrupt 173 */
+  .long   IRQDefault            /* User-Defined Interrupt 174 */
+  .long   IRQDefault            /* User-Defined Interrupt 175 */
+  .long   IRQDefault            /* User-Defined Interrupt 176 */
+  .long   IRQDefault            /* User-Defined Interrupt 177 */
+  .long   IRQDefault            /* User-Defined Interrupt 178 */
+  .long   IRQDefault            /* User-Defined Interrupt 179 */
+  .long   IRQDefault            /* User-Defined Interrupt 180 */
+  .long   IRQDefault            /* User-Defined Interrupt 181 */
+  .long   IRQDefault            /* User-Defined Interrupt 182 */
+  .long   IRQDefault            /* User-Defined Interrupt 183 */
+  .long   IRQDefault            /* User-Defined Interrupt 184 */
+  .long   IRQDefault            /* User-Defined Interrupt 185 */
+  .long   IRQDefault            /* User-Defined Interrupt 186 */
+  .long   IRQDefault            /* User-Defined Interrupt 187 */
+  .long   IRQDefault            /* User-Defined Interrupt 188 */
+  .long   IRQDefault            /* User-Defined Interrupt 189 */
+  .long   IRQDefault            /* User-Defined Interrupt 190 */
+  .long   IRQDefault            /* User-Defined Interrupt 191 */
+  .org    0x00000400
+
+  .section  .vector_ram
+__RAMVEC:
+  .space  0x400
+
+  .section  .text
+VecDefault:
+  halt
+  bra VecDefault
+
+IRQDefault:
+  halt
+  bra IRQDefault
+
+IRQSpurious:
+  halt
+  bra IRQSpurious
+
+TrapDefault:
+  halt
+  bra TrapDefault
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/tools/indent.sh b/20080212/Demo/lwIP_MCF5235_GCC/tools/indent.sh
new file mode 100644
index 000000000..140fd04d7
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/tools/indent.sh
@@ -0,0 +1,25 @@
+#!/bin/sh
+
+indent \
+    --declaration-indentation16 \
+    --procnames-start-lines \
+    --blank-lines-after-declarations \
+    --blank-lines-after-procedures \
+    --break-before-boolean-operator \
+    --braces-after-if-line \
+    --braces-after-struct-decl-line \
+    --brace-indent0 \
+    --case-indentation0 \
+    --no-space-after-function-call-names \
+    --no-space-after-for \
+    --no-space-after-if \
+    --no-space-after-while \
+    --no-space-after-casts \
+    --space-after-parentheses \
+    --dont-format-comments \
+    --indent-level4 \
+    --honour-newlines \
+    --no-tabs \
+    --line-length100 \
+    $@
+    
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/tools/mcf5235-http.png b/20080212/Demo/lwIP_MCF5235_GCC/tools/mcf5235-http.png
new file mode 100644
index 0000000000000000000000000000000000000000..fd5c1d5a2676bb14a1bb40367ee1936f8717f0ed
GIT binary patch
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diff --git a/20080212/Demo/lwIP_MCF5235_GCC/tools/mcf5235-icmp-frame-len1024.png b/20080212/Demo/lwIP_MCF5235_GCC/tools/mcf5235-icmp-frame-len1024.png
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diff --git a/20080212/Demo/lwIP_MCF5235_GCC/web.c b/20080212/Demo/lwIP_MCF5235_GCC/web.c
new file mode 100644
index 000000000..81be9d257
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/web.c
@@ -0,0 +1,228 @@
+/*
+    FreeRTOS V4.6.1 - copyright (C) 2003-2006 Richard Barry.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    FreeRTOS is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with FreeRTOS; if not, write to the Free Software
+    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+    A special exception to the GPL can be applied should you wish to distribute
+    a combined work that includes FreeRTOS, without being obliged to provide
+    the source code for any proprietary components.  See the licensing section
+    of http://www.FreeRTOS.org for full details of how and when the exception
+    can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+/*
+    Implements a simplistic WEB server.  Every time a connection is made and
+    data is received a dynamic page that shows the current TCP/IP statistics
+    is generated and returned.  The connection is then closed.
+
+    This file was adapted from a FreeRTOS lwIP slip demo supplied by a third
+    party.
+*/
+
+/* ------------------------ System includes ------------------------------- */
+#include 
+#include 
+
+/* ------------------------ FreeRTOS includes ----------------------------- */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "semphr.h"
+
+/* ------------------------ lwIP includes --------------------------------- */
+#include "lwip/api.h"
+#include "lwip/tcpip.h"
+#include "lwip/memp.h"
+#include "lwip/stats.h"
+#include "netif/loopif.h"
+
+/* ------------------------ Project includes ------------------------------ */
+#include "mcf5xxx.h"
+#include "mcf523x.h"
+#include "netif/fec.h"
+
+#include "web.h"
+
+/* ------------------------ Defines --------------------------------------- */
+/* The size of the buffer in which the dynamic WEB page is created. */
+#define webMAX_PAGE_SIZE        ( 2048 )
+
+/* Standard GET response. */
+#define webHTTP_OK  "HTTP/1.0 200 OK\r\nContent-type: text/html\r\n\r\n"
+
+/* The port on which we listen. */
+#define webHTTP_PORT            ( 80 )
+
+/* Delay on close error. */
+#define webSHORT_DELAY          ( 10 )
+
+/* Format of the dynamic page that is returned on each connection. */
+#define webHTML_START \
+"\
+\
+\
+\
+\r\nPage Hits = "
+
+#define webHTML_END \
+"\r\n" \
+"FreeRTOS MCF5235 port (c) 2006 by Christian Walter <wolti@sil.at>\r\n" \
+"
    \r\n" \ +"\r\n" \ +"" + +/* ------------------------ Prototypes ------------------------------------ */ +static void vProcessConnection( struct netconn *pxNetCon ); + +/*------------------------------------------------------------*/ + +/* + * Process an incoming connection on port 80. + * + * This simply checks to see if the incoming data contains a GET request, and + * if so sends back a single dynamically created page. The connection is then + * closed. A more complete implementation could create a task for each + * connection. + */ +static void +vProcessConnection( struct netconn *pxNetCon ) +{ + static portCHAR cDynamicPage[webMAX_PAGE_SIZE], cPageHits[11]; + struct netbuf *pxRxBuffer; + portCHAR *pcRxString; + unsigned portSHORT usLength; + static unsigned portLONG ulPageHits = 0; + + /* We expect to immediately get data. */ + pxRxBuffer = netconn_recv( pxNetCon ); + + if( pxRxBuffer != NULL ) + { + /* Where is the data? */ + netbuf_data( pxRxBuffer, ( void * )&pcRxString, &usLength ); + + /* Is this a GET? We don't handle anything else. */ + if( !strncmp( pcRxString, "GET", 3 ) ) + { + pcRxString = cDynamicPage; + + /* Update the hit count. */ + ulPageHits++; + sprintf( cPageHits, "%lu", ulPageHits ); + + /* Write out the HTTP OK header. */ + netconn_write( pxNetCon, webHTTP_OK, ( u16_t ) strlen( webHTTP_OK ), NETCONN_COPY ); + + /* Generate the dynamic page... + + ... First the page header. */ + strcpy( cDynamicPage, webHTML_START ); + /* ... Then the hit count... */ + strcat( cDynamicPage, cPageHits ); + strcat( cDynamicPage, + "

    Task          State  Priority  Stack #
    ************************************************
    " );
+            /* ... Then the list of tasks and their status... */
+            vTaskList( ( signed portCHAR * )cDynamicPage + strlen( cDynamicPage ) );
+            /* ... Finally the page footer. */
+            strcat( cDynamicPage, webHTML_END );
+
+            /* Write out the dynamically generated page. */
+            netconn_write( pxNetCon, cDynamicPage, ( u16_t ) strlen( cDynamicPage ), NETCONN_COPY );
+        }
+
+        netbuf_delete( pxRxBuffer );
+    }
+
+    netconn_close( pxNetCon );
+}
+
+/*------------------------------------------------------------*/
+
+void
+vlwIPInit( void )
+{
+    /* Initialize lwIP and its interface layer. */
+    sys_init(  );
+    mem_init(  );
+    memp_init(  );
+    pbuf_init(  );
+    netif_init(  );
+    ip_init(  );
+    tcpip_init( NULL, NULL );
+}
+
+/*------------------------------------------------------------*/
+
+void
+vBasicWEBServer( void *pvParameters )
+{
+    struct netconn *pxHTTPListener, *pxNewConnection;
+    struct ip_addr  xIpAddr, xNetMast, xGateway;
+    static struct netif fec523x_if;
+
+    /* Parameters are not used - suppress compiler error. */
+    ( void )pvParameters;
+
+    /* Create and configure the EMAC interface. */
+    IP4_ADDR( &xIpAddr, 10, 0, 10, 2 );
+    IP4_ADDR( &xNetMast, 255, 255, 255, 0 );
+    IP4_ADDR( &xGateway, 10, 0, 10, 1 );
+    netif_add( &fec523x_if, &xIpAddr, &xNetMast, &xGateway, NULL, mcf523xfec_init, tcpip_input );
+
+    /* make it the default interface */
+    netif_set_default( &fec523x_if );
+
+    /* bring it up */
+    netif_set_up( &fec523x_if );
+
+    /* Create a new tcp connection handle */
+    pxHTTPListener = netconn_new( NETCONN_TCP );
+    netconn_bind( pxHTTPListener, NULL, webHTTP_PORT );
+    netconn_listen( pxHTTPListener );
+
+    /* Loop forever */
+    for( ;; )
+    {
+        /* Wait for connection. */
+        pxNewConnection = netconn_accept( pxHTTPListener );
+
+        if( pxNewConnection != NULL )
+        {
+            /* Service connection. */
+            vProcessConnection( pxNewConnection );
+            while( netconn_delete( pxNewConnection ) != ERR_OK )
+            {
+                vTaskDelay( webSHORT_DELAY );
+            }
+        }
+    }
+}
diff --git a/20080212/Demo/lwIP_MCF5235_GCC/web.h b/20080212/Demo/lwIP_MCF5235_GCC/web.h
new file mode 100644
index 000000000..9444a388c
--- /dev/null
+++ b/20080212/Demo/lwIP_MCF5235_GCC/web.h
@@ -0,0 +1,56 @@
+/*
+    FreeRTOS V4.6.1 - copyright (C) 2003-2006 Richard Barry.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    FreeRTOS is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with FreeRTOS; if not, write to the Free Software
+    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+    A special exception to the GPL can be applied should you wish to distribute
+    a combined work that includes FreeRTOS, without being obliged to provide
+    the source code for any proprietary components.  See the licensing section
+    of http://www.FreeRTOS.org for full details of how and when the exception
+    can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+#ifndef BASIC_WEB_SERVER_H
+#define BASIC_WEB_SERVER_H
+
+/* The function that implements the WEB server task. */
+void            vBasicWEBServer( void *pvParameters );
+
+ 
+/* Initialisation required by lwIP. */
+void            vlwIPInit( void );
+
+ 
+#endif  /* 
+ */
+
diff --git a/20080212/Demo/msp430_CrossWorks/FreeRTOSConfig.h b/20080212/Demo/msp430_CrossWorks/FreeRTOSConfig.h
new file mode 100644
index 000000000..c3e5cd2e1
--- /dev/null
+++ b/20080212/Demo/msp430_CrossWorks/FreeRTOSConfig.h
@@ -0,0 +1,87 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+#include 
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. 
+ *----------------------------------------------------------*/
+
+#define configUSE_PREEMPTION		1
+#define configUSE_IDLE_HOOK			1
+#define configUSE_TICK_HOOK			0
+#define configCPU_CLOCK_HZ			( ( unsigned portLONG ) 7995392 ) /* Clock setup from main.c in the demo application. */
+#define configTICK_RATE_HZ			( ( portTickType ) 1000 )
+#define configMAX_PRIORITIES		( ( unsigned portBASE_TYPE ) 4 )
+#define configMINIMAL_STACK_SIZE	( ( unsigned portSHORT ) 50 )
+#define configTOTAL_HEAP_SIZE		( ( size_t ) ( 1800 ) )
+#define configMAX_TASK_NAME_LEN		( 8 )
+#define configUSE_TRACE_FACILITY	0
+#define configUSE_16_BIT_TICKS		1
+#define configIDLE_SHOULD_YIELD		1
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 		0
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+
+#define INCLUDE_vTaskPrioritySet		0
+#define INCLUDE_uxTaskPriorityGet		0
+#define INCLUDE_vTaskDelete				1
+#define INCLUDE_vTaskCleanUpResources	0
+#define INCLUDE_vTaskSuspend			0
+#define INCLUDE_vTaskDelayUntil			1
+#define INCLUDE_vTaskDelay				1
+
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/20080212/Demo/msp430_CrossWorks/ParTest/ParTest.c b/20080212/Demo/msp430_CrossWorks/ParTest/ParTest.c
new file mode 100644
index 000000000..14e898797
--- /dev/null
+++ b/20080212/Demo/msp430_CrossWorks/ParTest/ParTest.c
@@ -0,0 +1,220 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+/*-----------------------------------------------------------
+ * Characters on the LCD are used to simulate LED's.  In this case the 'ParTest'
+ * is really operating on the LCD display.
+ *-----------------------------------------------------------*/
+
+/*
+ * This demo is configured to execute on the ES449 prototyping board from
+ * SoftBaugh. The ES449 has a built in LCD display and a single built in user
+ * LED.  Therefore, in place of flashing an LED, the 'flash' and 'check' tasks
+ * toggle '*' characters on the LCD.  The left most '*' represents LED 0, the
+ * next LED 1, etc.
+ *
+ * There is a single genuine on board LED referenced as LED 10.
+ */
+
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Demo application includes. */
+#include "partest.h"
+
+/* Constants required to setup the LCD. */
+#define LCD_DIV_64 5
+
+/* Constants required to access the "LED's".  The LED segments are turned on
+and off to generate '*' characters. */
+#define partstNUM_LEDS			( ( unsigned portCHAR ) 6 )
+#define partstSEGMENTS_ON		( ( unsigned portCHAR ) 0x0f )
+#define partstSEGMENTS_OFF		( ( unsigned portCHAR ) 0x00 )
+
+/* The LED number of the real on board LED, rather than a simulated LED. */
+#define partstON_BOARD_LED		( ( unsigned portBASE_TYPE ) 10 )
+#define mainON_BOARD_LED_BIT	( ( unsigned portCHAR ) 0x01 )
+
+/* The LCD segments used to generate the '*' characters for LED's 0 to 5. */
+unsigned portCHAR * const ucRHSSegments[ partstNUM_LEDS ] = {	( unsigned portCHAR * )0xa4, 
+																( unsigned portCHAR * )0xa2, 
+																( unsigned portCHAR * )0xa0, 
+																( unsigned portCHAR * )0x9e,
+																( unsigned portCHAR * )0x9c,
+																( unsigned portCHAR * )0x9a };
+
+unsigned portCHAR * const ucLHSSegments[ partstNUM_LEDS ] = {	( unsigned portCHAR * )0xa3, 
+																( unsigned portCHAR * )0xa1, 
+																( unsigned portCHAR * )0x9f, 
+																( unsigned portCHAR * )0x9d,
+																( unsigned portCHAR * )0x9b,
+																( unsigned portCHAR * )0x99 };
+
+/*
+ * Toggle the single genuine built in LED.
+ */
+static void prvToggleOnBoardLED( void );
+
+/*-----------------------------------------------------------*/
+
+void vParTestInitialise( void )
+{
+	/* Initialise the LCD hardware. */
+
+	/* Used for the onboard LED. */
+	P1DIR = 0x01;
+
+	// Setup Basic Timer for LCD operation
+	BTCTL = (LCD_DIV_64+0x23);
+
+	// Setup port functions
+	P1SEL = 0x32;
+	P2SEL = 0x00;
+	P3SEL = 0x00;
+	P4SEL = 0xFC;
+	P5SEL = 0xFF;
+	
+	/* Initialise all segments to off. */
+	LCDM1 = partstSEGMENTS_OFF;	
+	LCDM2 = partstSEGMENTS_OFF;	
+	LCDM3 = partstSEGMENTS_OFF;	
+	LCDM4 = partstSEGMENTS_OFF;	
+	LCDM5 = partstSEGMENTS_OFF;	
+	LCDM6 = partstSEGMENTS_OFF;	
+	LCDM7 = partstSEGMENTS_OFF;	
+	LCDM8 = partstSEGMENTS_OFF;	
+	LCDM9 = partstSEGMENTS_OFF;	
+	LCDM10 = partstSEGMENTS_OFF;	
+	LCDM11 = partstSEGMENTS_OFF;	
+	LCDM12 = partstSEGMENTS_OFF;	
+	LCDM13 = partstSEGMENTS_OFF;	
+	LCDM14 = partstSEGMENTS_OFF;	
+	LCDM15 = partstSEGMENTS_OFF;	
+	LCDM16 = partstSEGMENTS_OFF;	
+	LCDM17 = partstSEGMENTS_OFF;	
+	LCDM18 = partstSEGMENTS_OFF;	
+	LCDM19 = partstSEGMENTS_OFF;	
+	LCDM20 = partstSEGMENTS_OFF;	
+
+	/* Setup LCD control. */
+	LCDCTL = (LCDSG0_7|LCD4MUX|LCDON);
+}
+/*-----------------------------------------------------------*/
+
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
+{
+	/* Set or clear the output [in this case show or hide the '*' character. */
+	if( uxLED < ( portBASE_TYPE ) partstNUM_LEDS )
+	{
+		vTaskSuspendAll();
+		{
+			if( xValue )
+			{
+				/* Turn on the segments required to show the '*'. */
+				*( ucRHSSegments[ uxLED ] ) = partstSEGMENTS_ON;
+				*( ucLHSSegments[ uxLED ] ) = partstSEGMENTS_ON;
+			}
+			else
+			{
+				/* Turn off all the segments. */
+				*( ucRHSSegments[ uxLED ] ) = partstSEGMENTS_OFF;
+				*( ucLHSSegments[ uxLED ] ) = partstSEGMENTS_OFF;
+			}
+		}
+		xTaskResumeAll();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
+{
+	if( uxLED < ( portBASE_TYPE ) partstNUM_LEDS )
+	{
+		vTaskSuspendAll();
+		{
+			/* If the '*' is already showing - hide it.  If it is not already
+			showing then show it. */
+			if( *( ucRHSSegments[ uxLED ] ) )
+			{
+				*( ucRHSSegments[ uxLED ] ) = partstSEGMENTS_OFF;
+				*( ucLHSSegments[ uxLED ] ) = partstSEGMENTS_OFF;
+			}
+			else
+			{
+				*( ucRHSSegments[ uxLED ] ) = partstSEGMENTS_ON;
+				*( ucLHSSegments[ uxLED ] ) = partstSEGMENTS_ON;
+			}
+		}
+		xTaskResumeAll();
+	}
+	else
+	{
+		if( uxLED == partstON_BOARD_LED )
+		{
+			/* The request related to the genuine on board LED. */
+			prvToggleOnBoardLED();
+		}
+	}	
+}
+/*-----------------------------------------------------------*/
+
+static void prvToggleOnBoardLED( void )
+{
+static unsigned portSHORT sState = pdFALSE;
+
+	/* Toggle the state of the single genuine on board LED. */
+	if( sState )	
+	{
+		P1OUT |= mainON_BOARD_LED_BIT;
+	}
+	else
+	{
+		P1OUT &= ~mainON_BOARD_LED_BIT;
+	}
+
+	sState = !sState;
+}
+/*-----------------------------------------------------------*/
+
+
diff --git a/20080212/Demo/msp430_CrossWorks/RTOSDemo.hzp b/20080212/Demo/msp430_CrossWorks/RTOSDemo.hzp
new file mode 100644
index 000000000..94acc5011
--- /dev/null
+++ b/20080212/Demo/msp430_CrossWorks/RTOSDemo.hzp
@@ -0,0 +1,34 @@
+
+
+  
+    
+    
+      
+      
+        
+      
+      
+      
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+      
+      
+      
+      
+    
+  
+  
+  
+  
+
diff --git a/20080212/Demo/msp430_CrossWorks/RTOSDemo.hzs b/20080212/Demo/msp430_CrossWorks/RTOSDemo.hzs
new file mode 100644
index 000000000..c4dc21923
--- /dev/null
+++ b/20080212/Demo/msp430_CrossWorks/RTOSDemo.hzs
@@ -0,0 +1,57 @@
+
+
+ 
+ 
+ 
+  
+ 
+ 
+  
+ 
+ 
+  
+ 
+ 
+  
+ 
+ 
+  
+  
+  
+  
+  
+ 
+ 
+  
+ 
+ 
+  
+ 
+ 
+  
+ 
+ 
+  
+ 
+ 
+ 
+  
+ 
+ 
+  
+ 
+ 
+  
+ 
+ 
+  
+ 
+ 
+  
+ 
+ 
+  
+  
+ 
+ 
+
diff --git a/20080212/Demo/msp430_CrossWorks/main.c b/20080212/Demo/msp430_CrossWorks/main.c
new file mode 100644
index 000000000..926eb06ec
--- /dev/null
+++ b/20080212/Demo/msp430_CrossWorks/main.c
@@ -0,0 +1,303 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+/*
+ * Creates all the demo application tasks, then starts the scheduler.  The WEB
+ * documentation provides more details of the demo application tasks.
+ * 
+ * This demo is configured to execute on the ES449 prototyping board from
+ * SoftBaugh. The ES449 has a built in LCD display and a single built in user
+ * LED.  Therefore, in place of flashing an LED, the 'flash' and 'check' tasks
+ * toggle '*' characters on the LCD.  The left most '*' represents LED 0, the
+ * next LED 1, etc.
+ *
+ * Main. c also creates a task called 'Check'.  This only executes every three 
+ * seconds but has the highest priority so is guaranteed to get processor time.  
+ * Its main function is to check that all the other tasks are still operational.  
+ * Each task that does not flash an LED maintains a unique count that is 
+ * incremented each time the task successfully completes its function.  Should 
+ * any error occur within such a task the count is permanently halted.  The 
+ * 'check' task inspects the count of each task to ensure it has changed since
+ * the last time the check task executed.  If all the count variables have 
+ * changed all the tasks are still executing error free, and the check task
+ * toggles an LED with a three second period.  Should any task contain an error 
+ * at any time the LED toggle rate will increase to 500ms.
+ *
+ * Please read the documentation for the MSP430 port available on
+ * http://www.FreeRTOS.org.
+ */
+
+/* Standard includes. */
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Demo application includes. */
+#include "partest.h"
+#include "flash.h"
+#include "integer.h"
+#include "comtest2.h"
+#include "PollQ.h"
+
+/* Constants required for hardware setup. */
+#define mainALL_BITS_OUTPUT		( ( unsigned portCHAR ) 0xff )
+#define mainMAX_FREQUENCY		( ( unsigned portCHAR ) 121 )
+
+/* Constants that define the LED's used by the various tasks. [in this case
+the '*' characters on the LCD represent LED's] */
+#define mainCHECK_LED			( 4 )
+#define mainCOM_TEST_LED		( 10 )
+
+/* Demo task priorities. */
+#define mainCHECK_TASK_PRIORITY			( tskIDLE_PRIORITY + 3 )
+#define mainCOM_TEST_PRIORITY			( tskIDLE_PRIORITY + 2 )
+#define mainQUEUE_POLL_PRIORITY			( tskIDLE_PRIORITY + 2 )
+#define mainLED_TASK_PRIORITY			( tskIDLE_PRIORITY + 1 )
+
+/* Baud rate used by the COM test tasks. */
+#define mainCOM_TEST_BAUD_RATE			( ( unsigned portLONG ) 19200 )
+
+/* The frequency at which the 'Check' tasks executes.  See the comments at the 
+top of the page.  When the system is operating error free the 'Check' task
+toggles an LED every three seconds.  If an error is discovered in any task the
+rate is increased to 500 milliseconds.  [in this case the '*' characters on the 
+LCD represent LED's]*/
+#define mainNO_ERROR_CHECK_DELAY		( ( portTickType ) 3000 / portTICK_RATE_MS  )
+#define mainERROR_CHECK_DELAY			( ( portTickType ) 500 / portTICK_RATE_MS  )
+
+/* The constants used in the calculation. */
+#define intgCONST1				( ( portLONG ) 123 )
+#define intgCONST2				( ( portLONG ) 234567 )
+#define intgCONST3				( ( portLONG ) -3 )
+#define intgCONST4				( ( portLONG ) 7 )
+#define intgEXPECTED_ANSWER		( ( ( intgCONST1 + intgCONST2 ) * intgCONST3 ) / intgCONST4 )
+
+/* 
+ * The function that implements the Check task.  See the comments at the head
+ * of the page for implementation details.
+ */ 
+static void vErrorChecks( void *pvParameters );
+
+/*
+ * Called by the Check task.  Returns pdPASS if all the other tasks are found
+ * to be operating without error - otherwise returns pdFAIL.
+ */
+static portSHORT prvCheckOtherTasksAreStillRunning( void );
+
+/* 
+ * Perform the hardware setup required by the ES449 in order to run the demo
+ * application.
+ */
+static void prvSetupHardware( void );
+
+
+portBASE_TYPE xLocalError = pdFALSE;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Start the demo application tasks - then start the real time scheduler.
+ */
+int main( void )
+{
+	/* Setup the hardware ready for the demo. */
+	prvSetupHardware();
+	vParTestInitialise();
+
+	/* Start the standard demo application tasks. */
+	vStartLEDFlashTasks( mainLED_TASK_PRIORITY );
+	vStartIntegerMathTasks( tskIDLE_PRIORITY );
+	vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED - 1 );
+	vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
+
+	/* Start the 'Check' task which is defined in this file. */
+	xTaskCreate( vErrorChecks, ( const signed portCHAR * const ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );	
+
+	/* Start the scheduler. */
+	vTaskStartScheduler();
+
+	/* As the scheduler has been started the demo applications tasks will be
+	executing and we should never get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+static portTASK_FUNCTION( vErrorChecks, pvParameters )
+{
+portTickType xDelayPeriod = mainNO_ERROR_CHECK_DELAY;
+
+	/* Cycle for ever, delaying then checking all the other tasks are still
+	operating without error. */
+	for( ;; )
+	{
+		/* Wait until it is time to check again.  The time we wait here depends
+		on whether an error has been detected or not.  When an error is 
+		detected the time is shortened resulting in a faster LED flash rate. */
+		vTaskDelay( xDelayPeriod );
+
+		/* See if the other tasks are all ok. */
+		if( prvCheckOtherTasksAreStillRunning() != pdPASS )
+		{
+			/* An error occurred in one of the tasks so shorten the delay 
+			period - which has the effect of increasing the frequency of the
+			LED toggle. */
+			xDelayPeriod = mainERROR_CHECK_DELAY;
+		}
+
+		/* Flash! */
+		vParTestToggleLED( mainCHECK_LED );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static portSHORT prvCheckOtherTasksAreStillRunning( void )
+{
+static portSHORT sNoErrorFound = pdTRUE;
+
+	/* The demo tasks maintain a count that increments every cycle of the task
+	provided that the task has never encountered an error.  This function 
+	checks the counts maintained by the tasks to ensure they are still being
+	incremented.  A count remaining at the same value between calls therefore
+	indicates that an error has been detected.  Only tasks that do not flash
+	an LED are checked. */
+
+	if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
+	{
+		sNoErrorFound = pdFALSE;
+	}
+
+	if( xAreComTestTasksStillRunning() != pdTRUE )
+	{
+		sNoErrorFound = pdFALSE;
+	}
+
+	if( xArePollingQueuesStillRunning() != pdTRUE )
+	{
+		sNoErrorFound = pdFALSE;
+	}
+
+	if( xLocalError == pdTRUE )
+	{
+		sNoErrorFound = pdFALSE;
+	}
+	
+	return sNoErrorFound;
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupHardware( void )
+{
+	/* Stop the watchdog. */
+	WDTCTL = WDTPW + WDTHOLD;
+
+	/* Setup DCO+ for ( xtal * D * (N + 1) ) operation. */
+	FLL_CTL0 |= DCOPLUS + XCAP18PF; 
+
+	/* X2 DCO frequency, 8MHz nominal DCO */
+	SCFI0 |= FN_4;                  
+
+	/* (121+1) x 32768 x 2 = 7.99 Mhz */
+	SCFQCTL = mainMAX_FREQUENCY;
+
+	/* Setup the IO.  This is just copied from the demo supplied by SoftBaugh
+	 for the ES449 demo board. */
+	P1SEL = 0x32;
+	P2SEL = 0x00;
+	P3SEL = 0x00;
+	P4SEL = 0xFC;
+	P5SEL = 0xFF;
+}
+/*-----------------------------------------------------------*/
+
+/* The idle hook is just a copy of the standard integer maths tasks.  See
+Demo/Common/integer.c for rationale. */
+
+void vApplicationIdleHook( void ) __toplevel
+{
+/* These variables are all effectively set to constants so they are volatile to
+ensure the compiler does not just get rid of them. */
+volatile portLONG lValue;
+volatile signed portBASE_TYPE *pxTaskHasExecuted;
+
+	/* Keep performing a calculation and checking the result against a constant. */
+	for( ;; )
+	{
+		/* Perform the calculation.  This will store partial value in
+		registers, resulting in a good test of the context switch mechanism. */
+		lValue = intgCONST1;
+		lValue += intgCONST2;
+
+		/* Yield in case cooperative scheduling is being used. */
+		#if configUSE_PREEMPTION == 0
+		{
+			taskYIELD();
+		}
+		#endif
+
+		/* Finish off the calculation. */
+		lValue *= intgCONST3;
+		lValue /= intgCONST4;
+
+		/* If the calculation is found to be incorrect we stop setting the 
+		TaskHasExecuted variable so the check task can see an error has 
+		occurred. */
+		if( lValue != intgEXPECTED_ANSWER ) /*lint !e774 volatile used to prevent this being optimised out. */
+		{
+			/* Don't bother with mutual exclusion - it is only read from the
+			check task and never written. */
+			xLocalError = pdTRUE;
+		}
+		/* Yield in case cooperative scheduling is being used. */
+		#if configUSE_PREEMPTION == 0
+		{
+			taskYIELD();
+		}
+		#endif
+	}
+}
+
+
+
+
+
diff --git a/20080212/Demo/msp430_CrossWorks/serial/serial.c b/20080212/Demo/msp430_CrossWorks/serial/serial.c
new file mode 100644
index 000000000..2af3d170a
--- /dev/null
+++ b/20080212/Demo/msp430_CrossWorks/serial/serial.c
@@ -0,0 +1,290 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+
+/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER.   
+ * 
+ * This file only supports UART 1
+ */
+
+/* Standard includes. */
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "queue.h"
+#include "task.h"
+
+/* Demo application includes. */
+#include "serial.h"
+
+/* Constants required to setup the hardware. */
+#define serTX_AND_RX			( ( unsigned portCHAR ) 0x03 )
+
+/* Misc. constants. */
+#define serNO_BLOCK				( ( portTickType ) 0 )
+
+/* Enable the UART Tx interrupt. */
+#define vInterruptOn() IFG2 |= UTXIFG1
+
+/* The queue used to hold received characters. */
+static xQueueHandle xRxedChars; 
+
+/* The queue used to hold characters waiting transmission. */
+static xQueueHandle xCharsForTx; 
+
+static volatile portSHORT sTHREEmpty;
+
+/*-----------------------------------------------------------*/
+
+xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
+{
+unsigned portLONG ulBaudRateCount;
+
+	/* Initialise the hardware. */
+
+	/* Generate the baud rate constants for the wanted baud rate. */
+	ulBaudRateCount = configCPU_CLOCK_HZ / ulWantedBaud;
+
+	portENTER_CRITICAL();
+	{
+		/* Create the queues used by the com test task. */
+		xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
+		xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
+
+		/* Reset UART. */
+		UCTL1 |= SWRST;
+
+		/* Set pin function. */
+		P4SEL |= serTX_AND_RX;
+
+		/* All other bits remain at zero for n, 8, 1 interrupt driven operation. 
+		LOOPBACK MODE!*/
+		U1CTL |= CHAR + LISTEN;
+		U1TCTL |= SSEL1;
+
+		/* Setup baud rate low byte. */
+		U1BR0 = ( unsigned portCHAR ) ( ulBaudRateCount & ( unsigned portLONG ) 0xff );
+
+		/* Setup baud rate high byte. */
+		ulBaudRateCount >>= 8UL;
+		U1BR1 = ( unsigned portCHAR ) ( ulBaudRateCount & ( unsigned portLONG ) 0xff );
+
+		/* Enable ports. */
+		ME2 |= UTXE1 + URXE1;
+
+		/* Set. */
+		UCTL1 &= ~SWRST;
+
+		/* Nothing in the buffer yet. */
+		sTHREEmpty = pdTRUE;
+
+		/* Enable interrupts. */
+		IE2 |= URXIE1 + UTXIE1;
+	}
+	portEXIT_CRITICAL();
+	
+	/* Unlike other ports, this serial code does not allow for more than one
+	com port.  We therefore don't return a pointer to a port structure and can
+	instead just return NULL. */
+	return NULL;
+}
+/*-----------------------------------------------------------*/
+
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )
+{
+	/* Get the next character from the buffer.  Return false if no characters
+	are available, or arrive before xBlockTime expires. */
+	if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
+	{
+		return pdTRUE;
+	}
+	else
+	{
+		return pdFALSE;
+	}
+}
+/*-----------------------------------------------------------*/
+
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )
+{
+signed portBASE_TYPE xReturn;
+
+	/* Transmit a character. */
+
+	portENTER_CRITICAL();
+	{
+		if( sTHREEmpty == pdTRUE )
+		{
+			/* If sTHREEmpty is true then the UART Tx ISR has indicated that 
+			there are no characters queued to be transmitted - so we can
+			write the character directly to the shift Tx register. */
+			sTHREEmpty = pdFALSE;
+			U1TXBUF = cOutChar;
+			xReturn = pdPASS;
+		}
+		else
+		{
+			/* sTHREEmpty is false, so there are still characters waiting to be
+			transmitted.  We have to queue this character so it gets 
+			transmitted	in turn. */
+
+			/* Return false if after the block time there is no room on the Tx 
+			queue.  It is ok to block inside a critical section as each task
+			maintains it's own critical section status. */
+			xReturn = xQueueSend( xCharsForTx, &cOutChar, xBlockTime );
+
+			/* Depending on queue sizing and task prioritisation:  While we 
+			were blocked waiting to post on the queue interrupts were not 
+			disabled.  It is possible that the serial ISR has emptied the 
+			Tx queue, in which case we need to start the Tx off again
+			writing directly to the Tx register. */
+			if( ( sTHREEmpty == pdTRUE ) && ( xReturn == pdPASS ) )
+			{
+				/* Get back the character we just posted. */
+				xQueueReceive( xCharsForTx, &cOutChar, serNO_BLOCK );
+				sTHREEmpty = pdFALSE;
+				U1TXBUF = cOutChar;
+			}
+		}
+	}
+	portEXIT_CRITICAL();
+
+	return pdPASS;
+}
+/*-----------------------------------------------------------*/
+
+#ifdef MSP_ROWLEY_RB_PORT
+
+/* Serial interrupt service routines for the RB port. */
+
+	/*
+	 * UART RX interrupt service routine.
+	 */
+	void vRxISR( void ) __interrupt[ UART1RX_VECTOR ]
+	{
+	signed portCHAR cChar;
+	
+		/* Get the character from the UART and post it on the queue of Rxed 
+		characters. */
+		cChar = U1RXBUF;
+	
+		if( xQueueSendFromISR( xRxedChars, &cChar, pdFALSE ) )
+		{
+			/*If the post causes a task to wake force a context switch 
+			as the woken task may have a higher priority than the task we have 
+			interrupted. */
+			taskYIELD();
+		}
+	}
+	/*-----------------------------------------------------------*/
+	
+	/*
+	 * UART Tx interrupt service routine.
+	 */
+	void vTxISR( void ) __interrupt[ UART1TX_VECTOR ]
+	{
+	signed portCHAR cChar;
+	portBASE_TYPE xTaskWoken;
+	
+		/* The previous character has been transmitted.  See if there are any
+		further characters waiting transmission. */
+	
+		if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWoken ) == pdTRUE )
+		{
+			/* There was another character queued - transmit it now. */
+			U1TXBUF = cChar;
+		}
+		else
+		{
+			/* There were no other characters to transmit. */
+			sTHREEmpty = pdTRUE;
+		}
+	}
+
+#endif
+/*-----------------------------------------------------------*/
+
+#ifdef MSP_ROWLEY_MP_PORT
+
+/* Serial port interrupts for the alternative port code. */
+
+	void ISRCom1Rx( void )
+	{
+	signed portCHAR cChar;
+	
+		/* Get the character from the UART and post it on the queue of Rxed 
+		characters. */
+		cChar = U1RXBUF;
+	
+		if( xQueueSendFromISR( xRxedChars, &cChar, pdFALSE ) )
+		{
+			/*If the post causes a task to wake force a context switch 
+			as the woken task may have a higher priority than the task we have 
+			interrupted. */
+			portEXIT_SWITCHING_ISR( pdTRUE );
+		}
+	}
+	/*-----------------------------------------------------------*/
+	
+	void ISRCom1Tx( void )
+	{
+	signed portCHAR cChar;
+	portBASE_TYPE xTaskWoken;
+	
+		/* The previous character has been transmitted.  See if there are any
+		further characters waiting transmission. */
+	
+		if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWoken ) == pdTRUE )
+		{
+			/* There was another character queued - transmit it now. */
+			U1TXBUF = cChar;
+		}
+		else
+		{
+			/* There were no other characters to transmit. */
+			sTHREEmpty = pdTRUE;
+		}
+	}
+
+#endif
+/*-----------------------------------------------------------*/
diff --git a/20080212/Demo/msp430_GCC/FreeRTOSConfig.h b/20080212/Demo/msp430_GCC/FreeRTOSConfig.h
new file mode 100644
index 000000000..d00e2addc
--- /dev/null
+++ b/20080212/Demo/msp430_GCC/FreeRTOSConfig.h
@@ -0,0 +1,92 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+#include 
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. 
+ *----------------------------------------------------------*/
+
+#define configUSE_PREEMPTION		1
+#define configUSE_IDLE_HOOK			0
+#define configUSE_TICK_HOOK			0
+#define configCPU_CLOCK_HZ			( ( unsigned portLONG ) 7995392 ) /* Clock setup from main.c in the demo application. */
+#define configTICK_RATE_HZ			( ( portTickType ) 1000 )
+#define configMAX_PRIORITIES		( ( unsigned portBASE_TYPE ) 4 )
+#define configMINIMAL_STACK_SIZE	( ( unsigned portSHORT ) 50 )
+#define configTOTAL_HEAP_SIZE		( ( size_t ) ( 1800 ) )
+#define configMAX_TASK_NAME_LEN		( 8 )
+#define configUSE_TRACE_FACILITY	0
+#define configUSE_16_BIT_TICKS		1
+#define configIDLE_SHOULD_YIELD		1
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 		0
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+
+#define INCLUDE_vTaskPrioritySet		0
+#define INCLUDE_uxTaskPriorityGet		0
+#define INCLUDE_vTaskDelete				1
+#define INCLUDE_vTaskCleanUpResources	0
+#define INCLUDE_vTaskSuspend			0
+#define INCLUDE_vTaskDelayUntil			1
+#define INCLUDE_vTaskDelay				1
+
+
+
+
+
+
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/20080212/Demo/msp430_GCC/ParTest/ParTest.c b/20080212/Demo/msp430_GCC/ParTest/ParTest.c
new file mode 100644
index 000000000..445cf95f3
--- /dev/null
+++ b/20080212/Demo/msp430_GCC/ParTest/ParTest.c
@@ -0,0 +1,222 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+/*-----------------------------------------------------------
+ * Characters on the LCD are used to simulate LED's.  In this case the 'ParTest'
+ * is really operating on the LCD display.
+ *-----------------------------------------------------------*/
+
+/*
+ * This demo is configured to execute on the ES449 prototyping board from
+ * SoftBaugh. The ES449 has a built in LCD display and a single built in user
+ * LED.  Therefore, in place of flashing an LED, the 'flash' and 'check' tasks
+ * toggle '*' characters on the LCD.  The left most '*' represents LED 0, the
+ * next LED 1, etc.
+ *
+ * There is a single genuine on board LED referenced as LED 10.
+ */
+
+/* Standard includes. */
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Demo application includes. */
+#include "partest.h"
+
+/* Constants required to setup the LCD. */
+#define LCD_DIV_64 5
+
+/* Constants required to access the "LED's".  The LED segments are turned on
+and off to generate '*' characters. */
+#define partstNUM_LEDS			( ( unsigned portCHAR ) 6 )
+#define partstSEGMENTS_ON		( ( unsigned portCHAR ) 0x0f )
+#define partstSEGMENTS_OFF		( ( unsigned portCHAR ) 0x00 )
+
+/* The LED number of the real on board LED, rather than a simulated LED. */
+#define partstON_BOARD_LED		( ( unsigned portBASE_TYPE ) 10 )
+#define mainON_BOARD_LED_BIT	( ( unsigned portCHAR ) 0x01 )
+
+/* The LCD segments used to generate the '*' characters for LED's 0 to 5. */
+unsigned portCHAR * const ucRHSSegments[ partstNUM_LEDS ] = {	( unsigned portCHAR * )0xa4, 
+																( unsigned portCHAR * )0xa2, 
+																( unsigned portCHAR * )0xa0, 
+																( unsigned portCHAR * )0x9e,
+																( unsigned portCHAR * )0x9c,
+																( unsigned portCHAR * )0x9a };
+
+unsigned portCHAR * const ucLHSSegments[ partstNUM_LEDS ] = {	( unsigned portCHAR * )0xa3, 
+																( unsigned portCHAR * )0xa1, 
+																( unsigned portCHAR * )0x9f, 
+																( unsigned portCHAR * )0x9d,
+																( unsigned portCHAR * )0x9b,
+																( unsigned portCHAR * )0x99 };
+
+/*
+ * Toggle the single genuine built in LED.
+ */
+static void prvToggleOnBoardLED( void );
+
+/*-----------------------------------------------------------*/
+
+void vParTestInitialise( void )
+{
+	/* Initialise the LCD hardware. */
+
+	/* Used for the onboard LED. */
+	P1DIR = 0x01;
+
+	// Setup Basic Timer for LCD operation
+	BTCTL = (LCD_DIV_64+0x23);
+
+	// Setup port functions
+	P1SEL = 0x32;
+	P2SEL = 0x00;
+	P3SEL = 0x00;
+	P4SEL = 0xFC;
+	P5SEL = 0xFF;
+	
+	/* Initialise all segments to off. */
+	LCDM1 = partstSEGMENTS_OFF;	
+	LCDM2 = partstSEGMENTS_OFF;	
+	LCDM3 = partstSEGMENTS_OFF;	
+	LCDM4 = partstSEGMENTS_OFF;	
+	LCDM5 = partstSEGMENTS_OFF;	
+	LCDM6 = partstSEGMENTS_OFF;	
+	LCDM7 = partstSEGMENTS_OFF;	
+	LCDM8 = partstSEGMENTS_OFF;	
+	LCDM9 = partstSEGMENTS_OFF;	
+	LCDM10 = partstSEGMENTS_OFF;	
+	LCDM11 = partstSEGMENTS_OFF;	
+	LCDM12 = partstSEGMENTS_OFF;	
+	LCDM13 = partstSEGMENTS_OFF;	
+	LCDM14 = partstSEGMENTS_OFF;	
+	LCDM15 = partstSEGMENTS_OFF;	
+	LCDM16 = partstSEGMENTS_OFF;	
+	LCDM17 = partstSEGMENTS_OFF;	
+	LCDM18 = partstSEGMENTS_OFF;	
+	LCDM19 = partstSEGMENTS_OFF;	
+	LCDM20 = partstSEGMENTS_OFF;	
+
+	/* Setup LCD control. */
+	LCDCTL = (LCDSG0_7|LCD4MUX|LCDON);
+}
+/*-----------------------------------------------------------*/
+
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
+{
+	/* Set or clear the output [in this case show or hide the '*' character. */
+	if( uxLED < ( portBASE_TYPE ) partstNUM_LEDS )
+	{
+		vTaskSuspendAll();
+		{
+			if( xValue )
+			{
+				/* Turn on the segments required to show the '*'. */
+				*( ucRHSSegments[ uxLED ] ) = partstSEGMENTS_ON;
+				*( ucLHSSegments[ uxLED ] ) = partstSEGMENTS_ON;
+			}
+			else
+			{
+				/* Turn off all the segments. */
+				*( ucRHSSegments[ uxLED ] ) = partstSEGMENTS_OFF;
+				*( ucLHSSegments[ uxLED ] ) = partstSEGMENTS_OFF;
+			}
+		}
+		xTaskResumeAll();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
+{
+	if( uxLED < ( portBASE_TYPE ) partstNUM_LEDS )
+	{
+		vTaskSuspendAll();
+		{
+			/* If the '*' is already showing - hide it.  If it is not already
+			showing then show it. */
+			if( *( ucRHSSegments[ uxLED ] ) )
+			{
+				*( ucRHSSegments[ uxLED ] ) = partstSEGMENTS_OFF;
+				*( ucLHSSegments[ uxLED ] ) = partstSEGMENTS_OFF;
+			}
+			else
+			{
+				*( ucRHSSegments[ uxLED ] ) = partstSEGMENTS_ON;
+				*( ucLHSSegments[ uxLED ] ) = partstSEGMENTS_ON;
+			}
+		}
+		xTaskResumeAll();
+	}
+	else
+	{
+		if( uxLED == partstON_BOARD_LED )
+		{
+			/* The request related to the genuine on board LED. */
+			prvToggleOnBoardLED();
+		}
+	}	
+}
+/*-----------------------------------------------------------*/
+
+static void prvToggleOnBoardLED( void )
+{
+static unsigned portSHORT sState = pdFALSE;
+
+	/* Toggle the state of the single genuine on board LED. */
+	if( sState )	
+	{
+		P1OUT |= mainON_BOARD_LED_BIT;
+	}
+	else
+	{
+		P1OUT &= ~mainON_BOARD_LED_BIT;
+	}
+
+	sState = !sState;
+}
+/*-----------------------------------------------------------*/
+
+
diff --git a/20080212/Demo/msp430_GCC/gdb.ini b/20080212/Demo/msp430_GCC/gdb.ini
new file mode 100644
index 000000000..ff3ac1401
--- /dev/null
+++ b/20080212/Demo/msp430_GCC/gdb.ini
@@ -0,0 +1,8 @@
+target remote localhost:3333
+kill
+target remote localhost:3333
+b main
+c
+
+
+
diff --git a/20080212/Demo/msp430_GCC/main.c b/20080212/Demo/msp430_GCC/main.c
new file mode 100644
index 000000000..5d6f1c76c
--- /dev/null
+++ b/20080212/Demo/msp430_GCC/main.c
@@ -0,0 +1,252 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+/*
+ * Creates all the demo application tasks, then starts the scheduler.  The WEB
+ * documentation provides more details of the demo application tasks.
+ * 
+ * This demo is configured to execute on the ES449 prototyping board from
+ * SoftBaugh. The ES449 has a built in LCD display and a single built in user
+ * LED.  Therefore, in place of flashing an LED, the 'flash' and 'check' tasks
+ * toggle '*' characters on the LCD.  The left most '*' represents LED 0, the
+ * next LED 1, etc.
+ *
+ * Main. c also creates a task called 'Check'.  This only executes every three 
+ * seconds but has the highest priority so is guaranteed to get processor time.  
+ * Its main function is to check that all the other tasks are still operational.  
+ * Each task that does not flash an LED maintains a unique count that is 
+ * incremented each time the task successfully completes its function.  Should 
+ * any error occur within such a task the count is permanently halted.  The 
+ * 'check' task inspects the count of each task to ensure it has changed since
+ * the last time the check task executed.  If all the count variables have 
+ * changed all the tasks are still executing error free, and the check task
+ * toggles an LED with a three second period.  Should any task contain an error 
+ * at any time the LED toggle rate will increase to 500ms.
+ *
+ * Please read the documentation for the MSP430 port available on
+ * http://www.FreeRTOS.org.
+ */
+
+/* Standard includes. */
+#include 
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Demo application includes. */
+#include "partest.h"
+#include "flash.h"
+#include "integer.h"
+#include "comtest2.h"
+#include "PollQ.h"
+
+/* Constants required for hardware setup. */
+#define mainALL_BITS_OUTPUT		( ( unsigned portCHAR ) 0xff )
+#define mainMAX_FREQUENCY		( ( unsigned portCHAR ) 121 )
+
+/* Constants that define the LED's used by the various tasks. [in this case
+the '*' characters on the LCD represent LED's] */
+#define mainCHECK_LED			( 4 )
+#define mainCOM_TEST_LED		( 10 )
+
+/* Demo task priorities. */
+#define mainCHECK_TASK_PRIORITY			( tskIDLE_PRIORITY + 3 )
+#define mainCOM_TEST_PRIORITY			( tskIDLE_PRIORITY + 2 )
+#define mainQUEUE_POLL_PRIORITY			( tskIDLE_PRIORITY + 2 )
+#define mainLED_TASK_PRIORITY			( tskIDLE_PRIORITY + 1 )
+
+/* Baud rate used by the COM test tasks. */
+#define mainCOM_TEST_BAUD_RATE			( ( unsigned portLONG ) 19200 )
+
+/* The frequency at which the 'Check' tasks executes.  See the comments at the 
+top of the page.  When the system is operating error free the 'Check' task
+toggles an LED every three seconds.  If an error is discovered in any task the
+rate is increased to 500 milliseconds.  [in this case the '*' characters on the 
+LCD represent LED's]*/
+#define mainNO_ERROR_CHECK_DELAY		( ( portTickType ) 3000 / portTICK_RATE_MS  )
+#define mainERROR_CHECK_DELAY			( ( portTickType ) 500 / portTICK_RATE_MS  )
+
+/* 
+ * The function that implements the Check task.  See the comments at the head
+ * of the page for implementation details.
+ */ 
+static void vErrorChecks( void *pvParameters );
+
+/*
+ * Called by the Check task.  Returns pdPASS if all the other tasks are found
+ * to be operating without error - otherwise returns pdFAIL.
+ */
+static portSHORT prvCheckOtherTasksAreStillRunning( void );
+
+/* 
+ * Perform the hardware setup required by the ES449 in order to run the demo
+ * application.
+ */
+static void prvSetupHardware( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Start the demo application tasks - then start the real time scheduler.
+ */
+int main( void )
+{
+	/* Setup the hardware ready for the demo. */
+	prvSetupHardware();
+	vParTestInitialise();
+
+	/* Start the standard demo application tasks. */
+	vStartLEDFlashTasks( mainLED_TASK_PRIORITY );
+	vStartIntegerMathTasks( tskIDLE_PRIORITY );
+	vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED - 1 );
+	vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
+
+	/* Start the 'Check' task which is defined in this file. */
+	xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );	
+
+	/* Start the scheduler. */
+	vTaskStartScheduler();
+
+	/* As the scheduler has been started the demo applications tasks will be
+	executing and we should never get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+static void vErrorChecks( void *pvParameters )
+{
+static volatile unsigned portLONG ulDummyVariable = 3UL;
+portTickType xDelayPeriod = mainNO_ERROR_CHECK_DELAY;
+
+	/* Cycle for ever, delaying then checking all the other tasks are still
+	operating without error. */
+	for( ;; )
+	{
+		/* Wait until it is time to check again.  The time we wait here depends
+		on whether an error has been detected or not.  When an error is 
+		detected the time is shortened resulting in a faster LED flash rate. */
+		vTaskDelay( xDelayPeriod );
+
+		/* Perform a bit of 32bit maths to ensure the registers used by the 
+		integer tasks get some exercise outside of the integer tasks 
+		themselves. The result here is not important we are just deliberately
+		changing registers used by other tasks to ensure that their context
+		switch is operating as required. - see the demo application 
+		documentation for more info. */
+		ulDummyVariable *= 3UL;
+		
+		/* See if the other tasks are all ok. */
+		if( prvCheckOtherTasksAreStillRunning() != pdPASS )
+		{
+			/* An error occurred in one of the tasks so shorten the delay 
+			period - which has the effect of increasing the frequency of the
+			LED toggle. */
+			xDelayPeriod = mainERROR_CHECK_DELAY;
+		}
+
+		/* Flash! */
+		vParTestToggleLED( mainCHECK_LED );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static portSHORT prvCheckOtherTasksAreStillRunning( void )
+{
+static portSHORT sNoErrorFound = pdTRUE;
+
+	/* The demo tasks maintain a count that increments every cycle of the task
+	provided that the task has never encountered an error.  This function 
+	checks the counts maintained by the tasks to ensure they are still being
+	incremented.  A count remaining at the same value between calls therefore
+	indicates that an error has been detected.  Only tasks that do not flash
+	an LED are checked. */
+
+	if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
+	{
+		sNoErrorFound = pdFALSE;
+	}
+
+	if( xAreComTestTasksStillRunning() != pdTRUE )
+	{
+		sNoErrorFound = pdFALSE;
+	}
+	
+	if( xArePollingQueuesStillRunning() != pdTRUE )
+	{
+		sNoErrorFound = pdFALSE;
+	}
+	
+	return sNoErrorFound;
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupHardware( void )
+{
+	/* Stop the watchdog. */
+	WDTCTL = WDTPW + WDTHOLD;
+
+	/* Setup DCO+ for ( xtal * D * (N + 1) ) operation. */
+	FLL_CTL0 |= DCOPLUS + XCAP18PF; 
+
+	/* X2 DCO frequency, 8MHz nominal DCO */
+	SCFI0 |= FN_4;                  
+
+	/* (121+1) x 32768 x 2 = 7.99 Mhz */
+	SCFQCTL = mainMAX_FREQUENCY;
+
+	/* Setup the IO as per the SoftBaugh demo for the same target hardware. */
+	P1SEL = 0x32;
+	P2SEL = 0x00;
+	P3SEL = 0x00;
+	P4SEL = 0xFC;
+	P5SEL = 0xFF;
+}
+/*-----------------------------------------------------------*/
+
+
+
+
+
+
+
diff --git a/20080212/Demo/msp430_GCC/makefile b/20080212/Demo/msp430_GCC/makefile
new file mode 100644
index 000000000..749673fc5
--- /dev/null
+++ b/20080212/Demo/msp430_GCC/makefile
@@ -0,0 +1,87 @@
+#	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+#
+#	This file is part of the FreeRTOS.org distribution.
+#
+#	FreeRTOS.org is free software; you can redistribute it and/or modify
+#	it under the terms of the GNU General Public License as published by
+#	the Free Software Foundation; either version 2 of the License, or
+#	(at your option) any later version.
+#
+#	FreeRTOS.org is distributed in the hope that it will be useful,
+#	but WITHOUT ANY WARRANTY; without even the implied warranty of
+#	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#	GNU General Public License for more details.
+#
+#	You should have received a copy of the GNU General Public License
+#	along with FreeRTOS.org; if not, write to the Free Software
+#	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+#
+#	A special exception to the GPL can be applied should you wish to distribute
+#	a combined work that includes FreeRTOS.org, without being obliged to provide
+#	the source code for any proprietary components.  See the licensing section 
+#	of http://www.FreeRTOS.org for full details of how and when the exception
+#	can be applied.
+#
+#	***************************************************************************
+#	See http://www.FreeRTOS.org for documentation, latest information, license 
+#	and contact details.  Please ensure to read the configuration and relevant 
+#	port sections of the online documentation.
+#	***************************************************************************
+
+
+CC=msp430-gcc
+OBJCOPY=msp430-objcopy
+DEBUG=-g
+OPT=-Os
+WARNINGS=-Wall -Wshadow -Wpointer-arith -Wbad-function-cast -Wcast-align -Wsign-compare \
+		-Waggregate-return -Wstrict-prototypes -Wmissing-prototypes -Wmissing-declarations -Wunused
+
+CFLAGS=-mmcu=msp430x449 $(OPT) $(DEBUG) -I. -I../../Source/include -I../Common/include -DGCC_MSP430 $(WARNINGS)
+
+# Setup paths to source code
+SOURCE_PATH = ../../Source
+PORT_PATH = ../../Source/portable/GCC/MSP430F449
+DEMO_PATH = ../Common/Minimal
+
+#
+# Source files that can be built to THUMB mode.
+#
+SRC = \
+main.c \
+ParTest/ParTest.c \
+serial/serial.c \
+$(SOURCE_PATH)/tasks.c \
+$(SOURCE_PATH)/list.c \
+$(SOURCE_PATH)/queue.c \
+$(SOURCE_PATH)/portable/MemMang/heap_1.c \
+$(PORT_PATH)/port.c \
+$(DEMO_PATH)/flash.c \
+$(DEMO_PATH)/integer.c \
+$(DEMO_PATH)/comtest.c \
+$(DEMO_PATH)/PollQ.c
+
+#
+# Define all object files.
+#
+OBJ = $(SRC:.c=.o)
+
+a.out : $(OBJ) makefile
+	$(CC) $(OBJ) $(CFLAGS)
+
+$(OBJ) : %.o : %.c makefile
+	$(CC) -c $(CFLAGS) $< -o $@	
+	
+clean :
+	touch makefile
+	
+
+
+
+
+
+
+
+
+	
+
+
diff --git a/20080212/Demo/msp430_GCC/serial/serial.c b/20080212/Demo/msp430_GCC/serial/serial.c
new file mode 100644
index 000000000..067fb61fa
--- /dev/null
+++ b/20080212/Demo/msp430_GCC/serial/serial.c
@@ -0,0 +1,244 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section 
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+
+/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER.   
+ * 
+ * This file only supports UART 1
+ */
+
+/* Standard includes. */
+#include 
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "queue.h"
+#include "task.h"
+
+/* Demo application includes. */
+#include "serial.h"
+
+/* Constants required to setup the hardware. */
+#define serTX_AND_RX			( ( unsigned portCHAR ) 0x03 )
+
+/* Misc. constants. */
+#define serNO_BLOCK				( ( portTickType ) 0 )
+
+/* Enable the UART Tx interrupt. */
+#define vInterruptOn() IFG2 |= UTXIFG1
+
+/* The queue used to hold received characters. */
+static xQueueHandle xRxedChars; 
+
+/* The queue used to hold characters waiting transmission. */
+static xQueueHandle xCharsForTx; 
+
+static volatile portSHORT sTHREEmpty;
+
+/* Interrupt service routines. */
+interrupt (UART1RX_VECTOR) vRxISR( void );
+interrupt (UART1TX_VECTOR) vTxISR( void );
+
+/*-----------------------------------------------------------*/
+
+xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
+{
+unsigned portLONG ulBaudRateCount;
+
+	/* Initialise the hardware. */
+
+	/* Generate the baud rate constants for the wanted baud rate. */
+	ulBaudRateCount = configCPU_CLOCK_HZ / ulWantedBaud;
+
+	portENTER_CRITICAL();
+	{
+		/* Create the queues used by the com test task. */
+		xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
+		xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
+
+		/* Reset UART. */
+		UCTL1 |= SWRST;
+
+		/* Set pin function. */
+		P4SEL |= serTX_AND_RX;
+
+		/* All other bits remain at zero for n, 8, 1 interrupt driven operation. 
+		LOOPBACK MODE!*/
+		U1CTL |= CHAR + LISTEN;
+		U1TCTL |= SSEL1;
+
+		/* Setup baud rate low byte. */
+		U1BR0 = ( unsigned portCHAR ) ( ulBaudRateCount & ( unsigned portLONG ) 0xff );
+
+		/* Setup baud rate high byte. */
+		ulBaudRateCount >>= 8UL;
+		U1BR1 = ( unsigned portCHAR ) ( ulBaudRateCount & ( unsigned portLONG ) 0xff );
+
+		/* Enable ports. */
+		ME2 |= UTXE1 + URXE1;
+
+		/* Set. */
+		UCTL1 &= ~SWRST;
+
+		/* Nothing in the buffer yet. */
+		sTHREEmpty = pdTRUE;
+
+		/* Enable interrupts. */
+		IE2 |= URXIE1 + UTXIE1;
+	}
+	portEXIT_CRITICAL();
+	
+	/* Unlike other ports, this serial code does not allow for more than one
+	com port.  We therefore don't return a pointer to a port structure and can
+	instead just return NULL. */
+	return NULL;
+}
+/*-----------------------------------------------------------*/
+
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )
+{
+	/* Get the next character from the buffer.  Return false if no characters
+	are available, or arrive before xBlockTime expires. */
+	if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
+	{
+		return pdTRUE;
+	}
+	else
+	{
+		return pdFALSE;
+	}
+}
+/*-----------------------------------------------------------*/
+
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )
+{
+signed portBASE_TYPE xReturn;
+
+	/* Transmit a character. */
+
+	portENTER_CRITICAL();
+	{
+		if( sTHREEmpty == pdTRUE )
+		{
+			/* If sTHREEmpty is true then the UART Tx ISR has indicated that 
+			there are no characters queued to be transmitted - so we can
+			write the character directly to the shift Tx register. */
+			sTHREEmpty = pdFALSE;
+			U1TXBUF = cOutChar;
+			xReturn = pdPASS;
+		}
+		else
+		{
+			/* sTHREEmpty is false, so there are still characters waiting to be
+			transmitted.  We have to queue this character so it gets 
+			transmitted	in turn. */
+
+			/* Return false if after the block time there is no room on the Tx 
+			queue.  It is ok to block inside a critical section as each task
+			maintains it's own critical section status. */
+			xReturn = xQueueSend( xCharsForTx, &cOutChar, xBlockTime );
+
+			/* Depending on queue sizing and task prioritisation:  While we 
+			were blocked waiting to post on the queue interrupts were not 
+			disabled.  It is possible that the serial ISR has emptied the 
+			Tx queue, in which case we need to start the Tx off again
+			writing directly to the Tx register. */
+			if( ( sTHREEmpty == pdTRUE ) && ( xReturn == pdPASS ) )
+			{
+				/* Get back the character we just posted. */
+				xQueueReceive( xCharsForTx, &cOutChar, serNO_BLOCK );
+				sTHREEmpty = pdFALSE;
+				U1TXBUF = cOutChar;
+			}
+		}
+	}
+	portEXIT_CRITICAL();
+
+	return pdPASS;
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * UART RX interrupt service routine.
+ */
+interrupt (UART1RX_VECTOR) vRxISR( void )
+{
+signed portCHAR cChar;
+
+	/* Get the character from the UART and post it on the queue of Rxed 
+	characters. */
+	cChar = U1RXBUF;
+
+	if( xQueueSendFromISR( xRxedChars, &cChar, pdFALSE ) )
+	{
+		/*If the post causes a task to wake force a context switch 
+		as the woken task may have a higher priority than the task we have 
+		interrupted. */
+		taskYIELD();
+	}
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * UART Tx interrupt service routine.
+ */
+interrupt (UART1TX_VECTOR) vTxISR( void )
+{
+signed portCHAR cChar;
+portBASE_TYPE xTaskWoken;
+
+	/* The previous character has been transmitted.  See if there are any
+	further characters waiting transmission. */
+
+	if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWoken ) == pdTRUE )
+	{
+		/* There was another character queued - transmit it now. */
+		U1TXBUF = cChar;
+	}
+	else
+	{
+		/* There were no other characters to transmit. */
+		sTHREEmpty = pdTRUE;
+	}
+}
+
diff --git a/20080212/Demo/readme.txt b/20080212/Demo/readme.txt
new file mode 100644
index 000000000..813c257cc
--- /dev/null
+++ b/20080212/Demo/readme.txt
@@ -0,0 +1,16 @@
+Each RTOS port has a demo application to demonstrate it's use.
+
++ The Demo/Common directory contains the demo application files as described on 
+the http://www.FreeRTOS.org WEB site.  Each file creates one or more tasks.
+The files in the Demo/Common directory are used by every demo application for
+every port.
+
++ All the other directories contain a project or makefile for the demo
+application targeted at a particular microcontroller.  
+
+
+For example, if you are interested in the ATMega323 demo application for
+the WinAVR tools then the AVR_ATMega323_WinAVR directory contains the 
+relevant makefile.  The makefile includes files from the Demo/ATMega323 
+and the Demo/Common directories.  If this is the only port you are 
+interested in then all the other directories can be ignored.
diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/EMAC/EMAClISR.s79 b/20080212/Demo/uIP_Demo_IAR_ARM7/EMAC/EMAClISR.s79
new file mode 100644
index 000000000..551ce6757
--- /dev/null
+++ b/20080212/Demo/uIP_Demo_IAR_ARM7/EMAC/EMAClISR.s79
@@ -0,0 +1,66 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+		RSEG ICODE:CODE
+		CODE32
+
+		EXTERN vEMACISR
+		PUBLIC vEMACISREntry
+
+; Wrapper for the EMAC interrupt service routine.  This can cause a
+; context switch so requires an assembly wrapper.
+
+; Defines the portSAVE_CONTEXT and portRESTORE_CONTEXT macros.
+#include "ISR_Support.h"
+
+vEMACISREntry:
+
+	portSAVE_CONTEXT			; Save the context of the current task.
+
+	bl	vEMACISR				; Call the ISR routine.
+
+	portRESTORE_CONTEXT			; Restore the context of the current task -
+								; which may be different to the task that
+								; was interrupted.
+
+		END
+
diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/EMAC/SAM7_EMAC.c b/20080212/Demo/uIP_Demo_IAR_ARM7/EMAC/SAM7_EMAC.c
new file mode 100644
index 000000000..459978f2a
--- /dev/null
+++ b/20080212/Demo/uIP_Demo_IAR_ARM7/EMAC/SAM7_EMAC.c
@@ -0,0 +1,711 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+/*
+ * Basic interrupt driven driver for the EMAC peripheral.  This driver is not
+ * reentrant as with uIP the buffers are only ever accessed from a single task.
+ *
+ * The simple buffer management used within uIP allows the EMAC driver to also
+ * be simplistic.  The driver contained within the lwIP demo is more
+ * comprehensive.
+ */
+
+
+/*
+Changes from V3.2.2
+
+	+ Corrected the byte order when writing the MAC address to the MAC.
+	+ Support added for MII interfaces.  Previously only RMII was supported.
+
+Changes from V3.2.3
+
+	+ The MII interface is now the default.
+	+ Modified the initialisation sequence slightly to allow auto init more
+	  time to complete.
+
+Changes from V3.2.4
+
+	+ Also read the EMAC_RSR register in the EMAC ISR as a work around the 
+	  the EMAC bug that can reset the RX bit in EMAC_ISR register before the
+	  bit has been read.
+
+Changes from V4.0.4
+
+	+ Corrected the Rx frame length mask when obtaining the length from the
+	  rx descriptor.
+
+*/
+
+/* Standard includes. */
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "semphr.h"
+#include "task.h"
+
+/* uIP includes. */
+#include "uip.h"
+
+/* Hardware specific includes. */
+#include "Emac.h"
+#include "mii.h"
+
+
+/* USE_RMII_INTERFACE must be defined as 1 to use an RMII interface, or 0
+to use an MII interface. */
+#define USE_RMII_INTERFACE 0
+
+/* The buffer addresses written into the descriptors must be aligned so the
+last few bits are zero.  These bits have special meaning for the EMAC
+peripheral and cannot be used as part of the address. */
+#define emacADDRESS_MASK			( ( unsigned portLONG ) 0xFFFFFFFC )
+
+/* Bit used within the address stored in the descriptor to mark the last
+descriptor in the array. */
+#define emacRX_WRAP_BIT				( ( unsigned portLONG ) 0x02 )
+
+/* Bit used within the Tx descriptor status to indicate whether the
+descriptor is under the control of the EMAC or the software. */
+#define emacTX_BUF_USED				( ( unsigned portLONG ) 0x80000000 )
+
+/* A short delay is used to wait for a buffer to become available, should
+one not be immediately available when trying to transmit a frame. */
+#define emacBUFFER_WAIT_DELAY		( 2 )
+#define emacMAX_WAIT_CYCLES			( configTICK_RATE_HZ / 40 )
+
+/* Misc defines. */
+#define emacINTERRUPT_LEVEL			( 5 )
+#define emacNO_DELAY				( 0 )
+#define emacTOTAL_FRAME_HEADER_SIZE	( 54 )
+#define emacPHY_INIT_DELAY			( 5000 / portTICK_RATE_MS )
+#define emacRESET_KEY				( ( unsigned portLONG ) 0xA5000000 )
+#define emacRESET_LENGTH			( ( unsigned portLONG ) ( 0x01 << 8 ) )
+
+/* The Atmel header file only defines the TX frame length mask. */
+#define emacRX_LENGTH_FRAME			( 0xfff )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Prototype for the EMAC interrupt asm wrapper.
+ */
+extern void vEMACISREntry( void );
+
+/*
+ * Prototype for the EMAC interrupt function - called by the asm wrapper.
+ */
+__arm void vEMACISR( void );
+
+/*
+ * Initialise both the Tx and Rx descriptors used by the EMAC.
+ */
+static void prvSetupDescriptors(void);
+
+/*
+ * Write our MAC address into the EMAC.  The MAC address is set as one of the
+ * uip options.
+ */
+static void prvSetupMACAddress( void );
+
+/*
+ * Configure the EMAC and AIC for EMAC interrupts.
+ */
+static void prvSetupEMACInterrupt( void );
+
+/*
+ * Some initialisation functions taken from the Atmel EMAC sample code.
+ */
+static void vReadPHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG *pulValue );
+#if USE_RMII_INTERFACE != 1
+	static void vWritePHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG ulValue);
+#endif
+static portBASE_TYPE xGetLinkSpeed( void );
+static portBASE_TYPE prvProbePHY( void );
+
+/*-----------------------------------------------------------*/
+
+/* Buffer written to by the EMAC DMA.  Must be aligned as described by the
+comment above the emacADDRESS_MASK definition. */
+#pragma data_alignment=8
+static volatile portCHAR pcRxBuffer[ NB_RX_BUFFERS * ETH_RX_BUFFER_SIZE ];
+
+/* Buffer read by the EMAC DMA.  Must be aligned as described by he comment
+above the emacADDRESS_MASK definition. */
+#pragma data_alignment=8
+static portCHAR pcTxBuffer[ NB_TX_BUFFERS * ETH_TX_BUFFER_SIZE ];
+
+/* Descriptors used to communicate between the program and the EMAC peripheral.
+These descriptors hold the locations and state of the Rx and Tx buffers. */
+static volatile AT91S_TxTdDescriptor xTxDescriptors[ NB_TX_BUFFERS ];
+static volatile AT91S_RxTdDescriptor xRxDescriptors[ NB_RX_BUFFERS ];
+
+/* The IP and Ethernet addresses are read from the uIP setup. */
+const portCHAR cMACAddress[ 6 ] = { UIP_ETHADDR0, UIP_ETHADDR1, UIP_ETHADDR2, UIP_ETHADDR3, UIP_ETHADDR4, UIP_ETHADDR5 };
+const unsigned char ucIPAddress[ 4 ]  = { UIP_IPADDR0, UIP_IPADDR1, UIP_IPADDR2, UIP_IPADDR3 };
+
+/* The semaphore used by the EMAC ISR to wake the EMAC task. */
+static xSemaphoreHandle xSemaphore = NULL;
+
+/*-----------------------------------------------------------*/
+
+xSemaphoreHandle xEMACInit( void )
+{
+	/* Code supplied by Atmel (modified) --------------------*/
+
+	/* disable pull up on RXDV => PHY normal mode (not in test mode),
+	PHY has internal pull down. */
+	AT91C_BASE_PIOB->PIO_PPUDR = 1 << 15;
+
+	#if USE_RMII_INTERFACE != 1
+	  	/* PHY has internal pull down : set MII mode. */
+	  	AT91C_BASE_PIOB->PIO_PPUDR= 1 << 16;
+	#endif
+
+	/* clear PB18 <=> PHY powerdown. */
+	AT91F_PIO_CfgOutput( AT91C_BASE_PIOB, 1 << 18 ) ;
+	AT91F_PIO_ClearOutput( AT91C_BASE_PIOB,  1 << 18) ;
+
+	/* After PHY power up, hardware reset. */
+	AT91C_BASE_RSTC->RSTC_RMR = emacRESET_KEY | emacRESET_LENGTH;
+	AT91C_BASE_RSTC->RSTC_RCR = emacRESET_KEY | AT91C_RSTC_EXTRST;
+	
+	/* Wait for hardware reset end. */
+	while( !( AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL ) )
+	{
+		__asm( "NOP" );
+	}
+	__asm( "NOP" );
+  	
+	/* EMAC IO init for EMAC-PHY com. Remove EF100 config. */
+	AT91F_EMAC_CfgPIO();
+
+	/* Enable com between EMAC PHY.
+
+	Enable management port. */
+	AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;	
+
+	/* MDC = MCK/32. */
+	AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10;	
+
+	/* Wait for PHY auto init end (rather crude delay!). */
+	vTaskDelay( emacPHY_INIT_DELAY );
+
+	/* PHY configuration. */
+	#if USE_RMII_INTERFACE != 1
+	{
+		unsigned portLONG ulControl;
+
+		/* PHY has internal pull down : disable MII isolate. */
+		vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );
+		vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );
+		ulControl &= ~BMCR_ISOLATE;
+		vWritePHY( AT91C_PHY_ADDR, MII_BMCR, ulControl );
+	}
+	#endif
+
+	/* Disable management port again. */
+	AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
+
+	#if USE_RMII_INTERFACE != 1
+		/* Enable EMAC in MII mode, enable clock ERXCK and ETXCK. */
+		AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_CLKEN ;
+	#else
+		/* Enable EMAC in RMII mode, enable RMII clock (50MHz from oscillator
+		on ERFCK). */
+		AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_RMII | AT91C_EMAC_CLKEN ;
+	#endif
+
+	/* End of code supplied by Atmel ------------------------*/
+
+	/* Setup the buffers and descriptors. */
+	prvSetupDescriptors();
+	
+	/* Load our MAC address into the EMAC. */
+	prvSetupMACAddress();
+
+	/* Try to connect. */
+	if( prvProbePHY() )
+	{
+		/* Enable the interrupt! */
+		prvSetupEMACInterrupt();
+	}
+
+	return xSemaphore;
+}
+/*-----------------------------------------------------------*/
+
+portLONG lEMACSend( void )
+{
+static unsigned portBASE_TYPE uxTxBufferIndex = 0;
+portBASE_TYPE xWaitCycles = 0;
+portLONG lReturn = pdPASS;
+portCHAR *pcBuffer;
+
+	/* Is a buffer available? */
+	while( !( xTxDescriptors[ uxTxBufferIndex ].U_Status.status & AT91C_TRANSMIT_OK ) )
+	{
+		/* There is no room to write the Tx data to the Tx buffer.  Wait a
+		short while, then try again. */
+		xWaitCycles++;
+		if( xWaitCycles > emacMAX_WAIT_CYCLES )
+		{
+			/* Give up. */
+			lReturn = pdFAIL;
+			break;
+		}
+		else
+		{
+			vTaskDelay( emacBUFFER_WAIT_DELAY );
+		}
+	}
+
+	/* lReturn will only be pdPASS if a buffer is available. */
+	if( lReturn == pdPASS )
+	{
+		/* Copy the headers into the Tx buffer.  These will be in the uIP buffer. */
+		pcBuffer = ( portCHAR * ) xTxDescriptors[ uxTxBufferIndex ].addr;
+		memcpy( ( void * ) pcBuffer, ( void * ) uip_buf, emacTOTAL_FRAME_HEADER_SIZE );
+		if( uip_len > emacTOTAL_FRAME_HEADER_SIZE )
+		{
+			memcpy( ( void * ) &( pcBuffer[ emacTOTAL_FRAME_HEADER_SIZE ] ), ( void * ) uip_appdata, ( uip_len - emacTOTAL_FRAME_HEADER_SIZE ) );
+		}
+
+		/* Send. */	
+		portENTER_CRITICAL();
+		{
+			if( uxTxBufferIndex >= ( NB_TX_BUFFERS - 1 ) )
+			{
+				/* Fill out the necessary in the descriptor to get the data sent. */
+				xTxDescriptors[ uxTxBufferIndex ].U_Status.status = 	( uip_len & ( unsigned portLONG ) AT91C_LENGTH_FRAME )
+																		| AT91C_LAST_BUFFER
+																		| AT91C_TRANSMIT_WRAP;
+				uxTxBufferIndex = 0;
+			}
+			else
+			{
+				/* Fill out the necessary in the descriptor to get the data sent. */
+				xTxDescriptors[ uxTxBufferIndex ].U_Status.status = 	( uip_len & ( unsigned portLONG ) AT91C_LENGTH_FRAME )
+																		| AT91C_LAST_BUFFER;
+				uxTxBufferIndex++;
+			}
+	
+			AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TSTART;
+		}
+		portEXIT_CRITICAL();
+	}
+
+	return lReturn;
+}
+/*-----------------------------------------------------------*/
+
+unsigned portLONG ulEMACPoll( void )
+{
+static unsigned portBASE_TYPE ulNextRxBuffer = 0;
+unsigned portLONG ulSectionLength = 0, ulLengthSoFar = 0, ulEOF = pdFALSE;
+portCHAR *pcSource;
+
+	/* Skip any fragments. */
+	while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AT91C_OWNERSHIP_BIT ) && !( xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AT91C_SOF ) )
+	{
+		/* Mark the buffer as free again. */
+		xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );		
+		ulNextRxBuffer++;
+		if( ulNextRxBuffer >= NB_RX_BUFFERS )
+		{
+			ulNextRxBuffer = 0;
+		}
+	}
+
+	/* Is there a packet ready? */
+
+	while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AT91C_OWNERSHIP_BIT ) && !ulSectionLength )
+	{
+		pcSource = ( portCHAR * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );
+		ulSectionLength = xRxDescriptors[ ulNextRxBuffer ].U_Status.status & emacRX_LENGTH_FRAME;
+
+		if( ulSectionLength == 0 )
+		{
+			/* The frame is longer than the buffer pointed to by this
+			descriptor so copy the entire buffer to uIP - then move onto
+			the next descriptor to get the rest of the frame. */
+			if( ( ulLengthSoFar + ETH_RX_BUFFER_SIZE ) <= UIP_BUFSIZE )
+			{
+				memcpy( &( uip_buf[ ulLengthSoFar ] ), pcSource, ETH_RX_BUFFER_SIZE );
+				ulLengthSoFar += ETH_RX_BUFFER_SIZE;
+			}			
+		}
+		else
+		{
+			/* This is the last section of the frame.  Copy the section to
+			uIP. */
+			if( ulSectionLength < UIP_BUFSIZE )
+			{
+				/* The section length holds the length of the entire frame.
+				ulLengthSoFar holds the length of the frame sections already
+				copied to uIP, so the length of the final section is
+				ulSectionLength - ulLengthSoFar; */
+				if( ulSectionLength > ulLengthSoFar )
+				{
+					memcpy( &( uip_buf[ ulLengthSoFar ] ), pcSource, ( ulSectionLength - ulLengthSoFar ) );
+				}
+			}			
+
+			/* Is this the last buffer for the frame?  If not why? */
+			ulEOF = xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AT91C_EOF;
+		}
+
+		/* Mark the buffer as free again. */
+		xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
+
+		/* Increment to the next buffer, wrapping if necessary. */
+		ulNextRxBuffer++;
+		if( ulNextRxBuffer >= NB_RX_BUFFERS )
+		{
+			ulNextRxBuffer = 0;
+		}
+	}
+
+	/* If we obtained data but for some reason did not find the end of the
+	frame then discard the data as it must contain an error. */
+	if( !ulEOF )
+	{
+		ulSectionLength = 0;
+	}
+
+	return ulSectionLength;
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupDescriptors(void)
+{
+unsigned portBASE_TYPE xIndex;
+unsigned portLONG ulAddress;
+
+	/* Initialise xRxDescriptors descriptor. */
+	for( xIndex = 0; xIndex < NB_RX_BUFFERS; ++xIndex )
+	{
+		/* Calculate the address of the nth buffer within the array. */
+		ulAddress = ( unsigned portLONG )( pcRxBuffer + ( xIndex * ETH_RX_BUFFER_SIZE ) );
+
+		/* Write the buffer address into the descriptor.  The DMA will place
+		the data at this address when this descriptor is being used.  Mask off
+		the bottom bits of the address as these have special meaning. */
+		xRxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;
+	}	
+
+	/* The last buffer has the wrap bit set so the EMAC knows to wrap back
+	to the first buffer. */
+	xRxDescriptors[ NB_RX_BUFFERS - 1 ].addr |= emacRX_WRAP_BIT;
+
+	/* Initialise xTxDescriptors. */
+	for( xIndex = 0; xIndex < NB_TX_BUFFERS; ++xIndex )
+	{
+		/* Calculate the address of the nth buffer within the array. */
+		ulAddress = ( unsigned portLONG )( pcTxBuffer + ( xIndex * ETH_TX_BUFFER_SIZE ) );
+
+		/* Write the buffer address into the descriptor.  The DMA will read
+		data from here when the descriptor is being used. */
+		xTxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;
+		xTxDescriptors[ xIndex ].U_Status.status = AT91C_TRANSMIT_OK;
+	}	
+
+	/* The last buffer has the wrap bit set so the EMAC knows to wrap back
+	to the first buffer. */
+	xTxDescriptors[ NB_TX_BUFFERS - 1 ].U_Status.status = AT91C_TRANSMIT_WRAP | AT91C_TRANSMIT_OK;
+
+	/* Tell the EMAC where to find the descriptors. */
+	AT91C_BASE_EMAC->EMAC_RBQP = ( unsigned portLONG ) xRxDescriptors;
+	AT91C_BASE_EMAC->EMAC_TBQP = ( unsigned portLONG ) xTxDescriptors;
+	
+	/* Clear all the bits in the receive status register. */
+	AT91C_BASE_EMAC->EMAC_RSR = ( AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA );
+
+	/* Enable the copy of data into the buffers, ignore broadcasts,
+	and don't copy FCS. */
+	AT91C_BASE_EMAC->EMAC_NCFGR |= ( AT91C_EMAC_CAF | AT91C_EMAC_NBC | AT91C_EMAC_DRFCS);
+
+	/* Enable Rx and Tx, plus the stats register. */
+	AT91C_BASE_EMAC->EMAC_NCR |= ( AT91C_EMAC_TE | AT91C_EMAC_RE | AT91C_EMAC_WESTAT );
+}	
+/*-----------------------------------------------------------*/
+
+static void prvSetupMACAddress( void )
+{
+	/* Must be written SA1L then SA1H. */
+	AT91C_BASE_EMAC->EMAC_SA1L =	( ( unsigned portLONG ) cMACAddress[ 3 ] << 24 ) |
+									( ( unsigned portLONG ) cMACAddress[ 2 ] << 16 ) |
+									( ( unsigned portLONG ) cMACAddress[ 1 ] << 8  ) |
+									cMACAddress[ 0 ];
+
+	AT91C_BASE_EMAC->EMAC_SA1H =	( ( unsigned portLONG ) cMACAddress[ 5 ] << 8 ) |
+									cMACAddress[ 4 ];
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupEMACInterrupt( void )
+{
+	/* Create the semaphore used to trigger the EMAC task. */
+	vSemaphoreCreateBinary( xSemaphore );
+	if( xSemaphore )
+	{
+		/* We start by 'taking' the semaphore so the ISR can 'give' it when the
+		first interrupt occurs. */
+		xSemaphoreTake( xSemaphore, emacNO_DELAY );
+		portENTER_CRITICAL();
+		{
+			/* We want to interrupt on Rx events. */
+			AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RCOMP;
+
+			/* Enable the interrupts in the AIC. */
+			AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_EMAC, emacINTERRUPT_LEVEL, AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, ( void (*)( void ) ) vEMACISREntry );
+			AT91F_AIC_EnableIt( AT91C_BASE_AIC, AT91C_ID_EMAC );
+		}
+		portEXIT_CRITICAL();
+	}
+}
+/*-----------------------------------------------------------*/
+
+__arm void vEMACISR( void )
+{
+volatile unsigned portLONG ulIntStatus, ulRxStatus;
+portBASE_TYPE xSwitchRequired = pdFALSE;
+
+	ulIntStatus = AT91C_BASE_EMAC->EMAC_ISR;
+	ulRxStatus = AT91C_BASE_EMAC->EMAC_RSR;
+
+	if( ( ulIntStatus & AT91C_EMAC_RCOMP ) || ( ulRxStatus & AT91C_EMAC_REC ) )
+	{
+		/* A frame has been received, signal the uIP task so it can process
+		the Rx descriptors. */
+		xSwitchRequired = xSemaphoreGiveFromISR( xSemaphore, pdFALSE );
+		AT91C_BASE_EMAC->EMAC_RSR = AT91C_EMAC_REC;
+	}
+
+	/* If a task was woken by either a character being received or a character
+	being transmitted then we may need to switch to another task. */
+	portEND_SWITCHING_ISR( xSwitchRequired );
+
+	/* Clear the interrupt. */
+	AT91C_BASE_AIC->AIC_EOICR = 0;
+}
+/*-----------------------------------------------------------*/
+
+
+
+/*
+ * The following functions are initialisation functions taken from the Atmel
+ * EMAC sample code.
+ */
+
+static portBASE_TYPE prvProbePHY( void )
+{
+unsigned portLONG ulPHYId1, ulPHYId2, ulStatus;
+portBASE_TYPE xReturn = pdPASS;
+	
+	/* Code supplied by Atmel (reformatted) -----------------*/
+
+	/* Enable management port */
+	AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;	
+	AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10;
+
+	/* Read the PHY ID. */
+	vReadPHY( AT91C_PHY_ADDR, MII_PHYSID1, &ulPHYId1 );
+	vReadPHY( AT91C_PHY_ADDR, MII_PHYSID2, &ulPHYId2 );
+
+	/* AMD AM79C875:
+			PHY_ID1 = 0x0022
+			PHY_ID2 = 0x5541
+			Bits 3:0 Revision Number Four bit manufacturer’s revision number.
+				0001 stands for Rev. A, etc.
+	*/
+	if( ( ( ulPHYId1 << 16 ) | ( ulPHYId2 & 0xfff0 ) ) != MII_DM9161_ID )
+	{
+		/* Did not expect this ID. */
+		xReturn = pdFAIL;
+	}
+	else
+	{
+		ulStatus = xGetLinkSpeed();
+
+		if( ulStatus != pdPASS )
+		{
+			xReturn = pdFAIL;
+		}
+	}
+
+	/* Disable management port */
+	AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;	
+
+	/* End of code supplied by Atmel ------------------------*/
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static void vReadPHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG *pulValue )
+{
+	/* Code supplied by Atmel (reformatted) ----------------------*/
+
+	AT91C_BASE_EMAC->EMAC_MAN = 	(AT91C_EMAC_SOF & (0x01<<30))
+									| (2 << 16) | (2 << 28)
+									| ((ucPHYAddress & 0x1f) << 23)
+									| (ucAddress << 18);
+
+	/* Wait until IDLE bit in Network Status register is cleared. */
+	while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )
+	{
+		__asm( "NOP" );
+	}
+
+	*pulValue = ( AT91C_BASE_EMAC->EMAC_MAN & 0x0000ffff );	
+
+	/* End of code supplied by Atmel ------------------------*/
+}
+/*-----------------------------------------------------------*/
+
+#if USE_RMII_INTERFACE != 1
+static void vWritePHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG ulValue )
+{
+	/* Code supplied by Atmel (reformatted) ----------------------*/
+
+	AT91C_BASE_EMAC->EMAC_MAN = (( AT91C_EMAC_SOF & (0x01<<30))
+								| (2 << 16) | (1 << 28)
+								| ((ucPHYAddress & 0x1f) << 23)
+								| (ucAddress << 18))
+								| (ulValue & 0xffff);
+
+	/* Wait until IDLE bit in Network Status register is cleared */
+	while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )
+	{
+		__asm( "NOP" );
+	};
+
+	/* End of code supplied by Atmel ------------------------*/
+}
+#endif
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE xGetLinkSpeed( void )
+{
+	unsigned portLONG ulBMSR, ulBMCR, ulLPA, ulMACCfg, ulSpeed, ulDuplex;
+
+	/* Code supplied by Atmel (reformatted) -----------------*/
+
+	/* Link status is latched, so read twice to get current value */
+	vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);
+	vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);
+
+	if( !( ulBMSR & BMSR_LSTATUS ) )
+	{	
+		/* No Link. */
+		return pdFAIL;
+	}
+
+	vReadPHY(AT91C_PHY_ADDR, MII_BMCR, &ulBMCR);
+	if (ulBMCR & BMCR_ANENABLE)
+	{				
+		/* AutoNegotiation is enabled. */
+		if (!(ulBMSR & BMSR_ANEGCOMPLETE))
+		{
+			/* Auto-negotiation in progress. */
+			return pdFAIL;				
+		}		
+
+		vReadPHY(AT91C_PHY_ADDR, MII_LPA, &ulLPA);
+		if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_100HALF ) )
+		{
+			ulSpeed = SPEED_100;
+		}
+		else
+		{
+			ulSpeed = SPEED_10;
+		}
+
+		if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_10FULL ) )
+		{
+			ulDuplex = DUPLEX_FULL;
+		}
+		else
+		{
+			ulDuplex = DUPLEX_HALF;
+		}
+	}
+	else
+	{
+		ulSpeed = ( ulBMCR & BMCR_SPEED100 ) ? SPEED_100 : SPEED_10;
+		ulDuplex = ( ulBMCR & BMCR_FULLDPLX ) ? DUPLEX_FULL : DUPLEX_HALF;
+	}
+
+	/* Update the MAC */
+	ulMACCfg = AT91C_BASE_EMAC->EMAC_NCFGR & ~( AT91C_EMAC_SPD | AT91C_EMAC_FD );
+	if( ulSpeed == SPEED_100 )
+	{
+		if( ulDuplex == DUPLEX_FULL )
+		{
+			/* 100 Full Duplex */
+			AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD | AT91C_EMAC_FD;
+		}
+		else
+		{					
+			/* 100 Half Duplex */
+			AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD;
+		}
+	}
+	else
+	{
+		if (ulDuplex == DUPLEX_FULL)
+		{
+			/* 10 Full Duplex */
+			AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_FD;
+		}
+		else
+		{
+			/* 10 Half Duplex */
+			AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg;
+		}
+	}
+
+	/* End of code supplied by Atmel ------------------------*/
+
+	return pdPASS;
+}
diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/EMAC/SAM7_EMAC.h b/20080212/Demo/uIP_Demo_IAR_ARM7/EMAC/SAM7_EMAC.h
new file mode 100644
index 000000000..36d6a05bc
--- /dev/null
+++ b/20080212/Demo/uIP_Demo_IAR_ARM7/EMAC/SAM7_EMAC.h
@@ -0,0 +1,24 @@
+#ifndef SAM_7_EMAC_H
+#define SAM_7_EMAC_H
+
+
+/*
+ * Initialise the EMAC driver.  If successful a semaphore is returned that
+ * is used by the EMAC ISR to indicate that Rx packets have been received.
+ * If the initialisation fails then NULL is returned.
+ */
+xSemaphoreHandle xEMACInit( void );
+
+/*
+ * Send the current uIP buffer.  This copies the uIP buffer to one of the
+ * EMAC Tx buffers, then indicates to the EMAC that the buffer is ready.
+ */
+portLONG lEMACSend( void );
+
+/*
+ * Called in response to an EMAC Rx interrupt.  Copies the received frame
+ * into the uIP buffer.
+ */
+unsigned portLONG ulEMACPoll( void );
+
+#endif
diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/FreeRTOSConfig.h b/20080212/Demo/uIP_Demo_IAR_ARM7/FreeRTOSConfig.h
new file mode 100644
index 000000000..cf284df26
--- /dev/null
+++ b/20080212/Demo/uIP_Demo_IAR_ARM7/FreeRTOSConfig.h
@@ -0,0 +1,88 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+#include 
+#include "Board.h"
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *----------------------------------------------------------*/
+
+#define configUSE_PREEMPTION		1
+#define configUSE_IDLE_HOOK			0
+#define configUSE_TICK_HOOK			0
+#define configCPU_CLOCK_HZ			( ( unsigned portLONG ) 47923200 )
+#define configTICK_RATE_HZ			( ( portTickType ) 1000 )
+#define configMAX_PRIORITIES		( ( unsigned portBASE_TYPE ) 5 )
+#define configMINIMAL_STACK_SIZE	( ( unsigned portSHORT ) 100 )
+#define configTOTAL_HEAP_SIZE		( ( size_t ) 22000 )
+#define configMAX_TASK_NAME_LEN		( 16 )
+#define configUSE_TRACE_FACILITY	1
+#define configUSE_16_BIT_TICKS		0
+#define configIDLE_SHOULD_YIELD		0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 		0
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+
+#define INCLUDE_vTaskPrioritySet		1
+#define INCLUDE_uxTaskPriorityGet		1
+#define INCLUDE_vTaskDelete				1
+#define INCLUDE_vTaskCleanUpResources	0
+#define INCLUDE_vTaskSuspend			1
+#define INCLUDE_vTaskDelayUntil			1
+#define INCLUDE_vTaskDelay				1
+
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/ParTest/ParTest.c b/20080212/Demo/uIP_Demo_IAR_ARM7/ParTest/ParTest.c
new file mode 100644
index 000000000..4ec8c0f95
--- /dev/null
+++ b/20080212/Demo/uIP_Demo_IAR_ARM7/ParTest/ParTest.c
@@ -0,0 +1,91 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+#include "FreeRTOS.h"
+#include "partest.h"
+#include "board.h"
+
+/*-----------------------------------------------------------
+ * Simple parallel port IO routines for the LED's.  LED's can be set, cleared
+ * or toggled.
+ *-----------------------------------------------------------*/
+const unsigned portLONG ulLED_MASK[ NB_LED ]= { LED1, LED2, LED3, LED4 };
+
+void vParTestInitialise( void )
+{	
+	/* Start with all LED's off. */
+	AT91F_PIO_SetOutput( AT91C_BASE_PIOB, LED_MASK );	
+}
+/*-----------------------------------------------------------*/
+
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
+{
+	if( uxLED < ( portBASE_TYPE ) NB_LED )
+	{
+		if( xValue )
+		{
+			AT91F_PIO_SetOutput( AT91C_BASE_PIOB, ulLED_MASK[ uxLED ] );
+		}
+		else
+		{
+			AT91F_PIO_ClearOutput( AT91C_BASE_PIOB, ulLED_MASK[ uxLED ]);
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
+{
+	if( uxLED < ( portBASE_TYPE ) NB_LED )
+	{
+		if( AT91F_PIO_GetInput( AT91C_BASE_PIOB ) & ulLED_MASK[ uxLED ] )
+		{
+			AT91F_PIO_ClearOutput( AT91C_BASE_PIOB, ulLED_MASK[ uxLED ]);
+		}
+		else
+		{
+			AT91F_PIO_SetOutput( AT91C_BASE_PIOB, ulLED_MASK[ uxLED ] );					
+		}
+	}
+}
+
+
diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Board.h b/20080212/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Board.h
new file mode 100644
index 000000000..0313bfdc6
--- /dev/null
+++ b/20080212/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Board.h
@@ -0,0 +1,69 @@
+/*----------------------------------------------------------------------------
+*         ATMEL Microcontroller Software Support  -  ROUSSET  -
+*----------------------------------------------------------------------------
+* The software is delivered "AS IS" without warranty or condition of any
+* kind, either express, implied or statutory. This includes without
+* limitation any warranty or condition with respect to merchantability or
+* fitness for any particular purpose, or against the infringements of
+* intellectual property rights of others.
+*----------------------------------------------------------------------------
+* File Name           : Board.h
+* Object              : AT91SAM7X Evaluation Board Features Definition File.
+*
+* Creation            : JG   20/Jun/2005
+*----------------------------------------------------------------------------
+*/
+#ifndef Board_h
+#define Board_h
+
+#include 
+#define __inline inline
+#include 
+
+#define true	-1
+#define false	0
+
+/*-------------------------------*/
+/* SAM7Board Memories Definition */
+/*-------------------------------*/
+// The AT91SAM7X128 embeds a 32-Kbyte SRAM bank, and 128K-Byte Flash
+
+#define  FLASH_PAGE_NB		256
+#define  FLASH_PAGE_SIZE	128
+
+/*-----------------*/
+/* Leds Definition */
+/*-----------------*/
+#define LED1            (1<<19)	// PB19
+#define LED2            (1<<20)	// PB20
+#define LED3            (1<<21)	// PB21
+#define LED4            (1<<22)	// PB22
+#define NB_LED			4
+
+#define LED_MASK        (LED1|LED2|LED3|LED4)
+
+/*-------------------------*/
+/* Push Buttons Definition */
+/*-------------------------*/
+
+#define SW1_MASK        (1<<21)	// PA21
+#define SW2_MASK        (1<<22)	// PA22
+#define SW3_MASK        (1<<23)	// PA23
+#define SW4_MASK        (1<<24)	// PA24
+#define SW_MASK         (SW1_MASK|SW2_MASK|SW3_MASK|SW4_MASK)
+
+
+#define SW1 	(1<<21)	// PA21
+#define SW2 	(1<<22)	// PA22
+#define SW3 	(1<<23)	// PA23
+#define SW4 	(1<<24)	// PA24
+
+/*--------------*/
+/* Master Clock */
+/*--------------*/
+
+#define EXT_OC          18432000   // Exetrnal ocilator MAINCK
+#define MCK             47923200   // MCK (PLLRC div by 2)
+#define MCKKHz          (MCK/1000) //
+
+#endif /* Board_h */
diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Cstartup.s b/20080212/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Cstartup.s
new file mode 100644
index 000000000..12842e137
--- /dev/null
+++ b/20080212/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Cstartup.s
@@ -0,0 +1,302 @@
+;* ----------------------------------------------------------------------------
+;*         ATMEL Microcontroller Software Support  -  ROUSSET  -
+;* ----------------------------------------------------------------------------
+;* Copyright (c) 2006, Atmel Corporation
+;
+;* All rights reserved.
+;*
+;* Redistribution and use in source and binary forms, with or without
+;* modification, are permitted provided that the following conditions are met:
+;*
+;* - Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the disclaimer below.
+;*
+;* - Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the disclaimer below in the documentation and/or
+;* other materials provided with the distribution.
+;*
+;* Atmel's name may not be used to endorse or promote products derived from
+;* this software without specific prior written permission.
+;*
+;* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+;* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+;* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+;* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+;* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+;* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+;* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+;* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+;* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+;* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;* ----------------------------------------------------------------------------
+
+;------------------------------------------------------------------------------
+; Include your AT91 Library files
+;------------------------------------------------------------------------------
+#include "AT91SAM7X256_inc.h"
+;------------------------------------------------------------------------------
+
+#define TOP_OF_MEMORY    (AT91C_ISRAM + AT91C_ISRAM_SIZE)
+#define IRQ_STACK_SIZE   200
+     ; 3 words to be saved per interrupt priority level
+
+; Mode, correspords to bits 0-5 in CPSR
+MODE_BITS DEFINE  0x1F    ; Bit mask for mode bits in CPSR
+USR_MODE  DEFINE  0x10    ; User mode
+FIQ_MODE  DEFINE  0x11    ; Fast Interrupt Request mode
+IRQ_MODE  DEFINE  0x12    ; Interrupt Request mode
+SVC_MODE  DEFINE  0x13    ; Supervisor mode
+ABT_MODE  DEFINE  0x17    ; Abort mode
+UND_MODE  DEFINE  0x1B    ; Undefined Instruction mode
+SYS_MODE  DEFINE  0x1F    ; System mode
+
+I_BIT     DEFINE  0x80
+F_BIT     DEFINE  0x40
+
+;------------------------------------------------------------------------------
+; ?RESET
+; Reset Vector.
+; Normally, segment INTVEC is linked at address 0.
+; For debugging purposes, INTVEC may be placed at other addresses.
+; A debugger that honors the entry point will start the
+; program in a normal way even if INTVEC is not at address 0.
+;------------------------------------------------------------------------------
+        SECTION .intvec:CODE:NOROOT(2)
+        PUBLIC  __vector
+        PUBLIC  __iar_program_start
+		EXTERN	vPortYieldProcessor
+
+		ARM
+__vector:
+        ldr  pc,[pc,#+24]             ;; Reset
+__und_handler:
+        ldr  pc,[pc,#+24]             ;; Undefined instructions
+__swi_handler:
+        ldr  pc,[pc,#+24]             ;; Software interrupt (SWI/SVC)
+__prefetch_handler:
+        ldr  pc,[pc,#+24]             ;; Prefetch abort
+__data_handler:
+        ldr  pc,[pc,#+24]             ;; Data abort
+        DC32  0xFFFFFFFF              ;; RESERVED
+__irq_handler:
+        LDR			PC, [PC, #-0xF20]
+__fiq_handler:
+        ldr  pc,[pc,#+24]             ;; FIQ
+
+        DC32  __iar_program_start
+        DC32  __und_handler
+        DC32  vPortYieldProcessor
+        DC32  __prefetch_handler
+        DC32  __data_handler
+        B .
+        DC32  IRQ_Handler_Entry
+        DC32  FIQ_Handler_Entry
+
+;------------------------------------------------------------------------------
+;- Manage exception: The exception must be ensure in ARM mode
+;------------------------------------------------------------------------------
+        SECTION text:CODE:NOROOT(2)
+        ARM
+;------------------------------------------------------------------------------
+;- Function             : FIQ_Handler_Entry
+;- Treatments           : FIQ Controller Interrupt Handler.
+;-                        R8 is initialize in Cstartup
+;- Called Functions     : None only by FIQ
+;------------------------------------------------------------------------------
+FIQ_Handler_Entry:
+
+;- Switch in SVC/User Mode to allow User Stack access for C code
+; because the FIQ is not yet acknowledged
+
+;- Save and r0 in FIQ_Register
+        mov         r9,r0
+        ldr         r0 , [r8, #AIC_FVR]
+        msr         CPSR_c,#I_BIT | F_BIT | SVC_MODE
+;- Save scratch/used registers and LR in User Stack
+        stmfd       sp!, { r1-r3, r12, lr}
+
+;- Branch to the routine pointed by the AIC_FVR
+        mov         r14, pc
+        bx          r0
+
+;- Restore scratch/used registers and LR from User Stack
+        ldmia       sp!, { r1-r3, r12, lr}
+
+;- Leave Interrupts disabled and switch back in FIQ mode
+        msr         CPSR_c, #I_BIT | F_BIT | FIQ_MODE
+
+;- Restore the R0 ARM_MODE_SVC register
+        mov         r0,r9
+
+;- Restore the Program Counter using the LR_fiq directly in the PC
+        subs        pc,lr,#4
+;------------------------------------------------------------------------------
+;- Function             : IRQ_Handler_Entry
+;- Treatments           : IRQ Controller Interrupt Handler.
+;- Called Functions     : AIC_IVR[interrupt]
+;------------------------------------------------------------------------------
+IRQ_Handler_Entry:
+;-------------------------
+;- Manage Exception Entry
+;-------------------------
+;- Adjust and save LR_irq in IRQ stack
+    sub         lr, lr, #4
+    stmfd       sp!, {lr}
+
+;- Save r0 and SPSR (need to be saved for nested interrupt)
+    mrs         r14, SPSR
+    stmfd       sp!, {r0,r14}
+
+;- Write in the IVR to support Protect Mode
+;- No effect in Normal Mode
+;- De-assert the NIRQ and clear the source in Protect Mode
+    ldr         r14, =AT91C_BASE_AIC
+    ldr         r0 , [r14, #AIC_IVR]
+    str         r14, [r14, #AIC_IVR]
+
+;- Enable Interrupt and Switch in Supervisor Mode
+    msr         CPSR_c, #SVC_MODE
+
+;- Save scratch/used registers and LR in User Stack
+    stmfd       sp!, { r1-r3, r12, r14}
+
+;----------------------------------------------
+;- Branch to the routine pointed by the AIC_IVR
+;----------------------------------------------
+    mov         r14, pc
+    bx          r0
+
+;----------------------------------------------
+;- Manage Exception Exit
+;----------------------------------------------
+;- Restore scratch/used registers and LR from User Stack
+    ldmia       sp!, { r1-r3, r12, r14}
+
+;- Disable Interrupt and switch back in IRQ mode
+    msr         CPSR_c, #I_BIT | IRQ_MODE
+
+;- Mark the End of Interrupt on the AIC
+    ldr         r14, =AT91C_BASE_AIC
+    str         r14, [r14, #AIC_EOICR]
+
+;- Restore SPSR_irq and r0 from IRQ stack
+    ldmia       sp!, {r0,r14}
+    msr         SPSR_cxsf, r14
+
+;- Restore adjusted  LR_irq from IRQ stack directly in the PC
+    ldmia       sp!, {pc}^
+
+;------------------------------------------------------------------------------
+;- Exception Vectors
+;------------------------------------------------------------------------------
+    PUBLIC    AT91F_Default_FIQ_handler
+    PUBLIC    AT91F_Default_IRQ_handler
+    PUBLIC    AT91F_Spurious_handler
+
+    ARM      ; Always ARM mode after exeption
+
+AT91F_Default_FIQ_handler
+    b         AT91F_Default_FIQ_handler
+
+AT91F_Default_IRQ_handler
+    b         AT91F_Default_IRQ_handler
+
+AT91F_Spurious_handler
+    b         AT91F_Spurious_handler
+
+
+;------------------------------------------------------------------------------
+; ?INIT
+; Program entry.
+;------------------------------------------------------------------------------
+
+    SECTION FIQ_STACK:DATA:NOROOT(3)
+    SECTION IRQ_STACK:DATA:NOROOT(3)
+    SECTION SVC_STACK:DATA:NOROOT(3)
+    SECTION ABT_STACK:DATA:NOROOT(3)
+    SECTION UND_STACK:DATA:NOROOT(3)
+    SECTION CSTACK:DATA:NOROOT(3)
+    SECTION text:CODE:NOROOT(2)
+    REQUIRE __vector
+    EXTERN  ?main
+    PUBLIC  __iar_program_start
+    EXTERN  AT91F_LowLevelInit
+
+
+__iar_program_start:
+
+;------------------------------------------------------------------------------
+;- Low level Init is performed in a C function: AT91F_LowLevelInit
+;- Init Stack Pointer to a valid memory area before calling AT91F_LowLevelInit
+;------------------------------------------------------------------------------
+
+;- Retrieve end of RAM address
+
+                ldr     r13,=TOP_OF_MEMORY          ;- Temporary stack in internal RAM for Low Level Init execution
+                ldr     r0,=AT91F_LowLevelInit
+                mov     lr, pc
+                bx      r0                          ;- Branch on C function (with interworking)
+
+; Initialize the stack pointers.
+; The pattern below can be used for any of the exception stacks:
+; FIQ, IRQ, SVC, ABT, UND, SYS.
+; The USR mode uses the same stack as SYS.
+; The stack segments must be defined in the linker command file,
+; and be declared above.
+
+                mrs     r0,cpsr                             ; Original PSR value
+                bic     r0,r0,#MODE_BITS                    ; Clear the mode bits
+                orr     r0,r0,#SVC_MODE                     ; Set SVC mode bits
+                msr     cpsr_c,r0                           ; Change the mode
+                ldr     sp,=SFE(SVC_STACK)                  ; End of SVC_STACK
+
+				bic     r0,r0,#MODE_BITS                    ; Clear the mode bits
+                orr     r0,r0,#UND_MODE                     ; Set UND mode bits
+                msr     cpsr_c,r0                           ; Change the mode
+                ldr     sp,=SFE(UND_STACK)                  ; End of UND_STACK
+
+                bic     r0,r0,#MODE_BITS                    ; Clear the mode bits
+                orr     r0,r0,#ABT_MODE                     ; Set ABT mode bits
+                msr     cpsr_c,r0                           ; Change the mode
+                ldr     sp,=SFE(ABT_STACK)                  ; End of ABT_STACK
+
+                bic     r0,r0,#MODE_BITS                    ; Clear the mode bits
+                orr     r0,r0,#FIQ_MODE                     ; Set FIQ mode bits
+                msr     cpsr_c,r0                           ; Change the mode
+                ldr     sp,=SFE(FIQ_STACK)                  ; End of FIQ_STACK
+                ;- Init the FIQ register
+                ldr     r8, =AT91C_BASE_AIC
+
+                bic     r0,r0,#MODE_BITS                    ; Clear the mode bits
+                orr     r0,r0,#IRQ_MODE                     ; Set IRQ mode bits
+                msr     cpsr_c,r0                           ; Change the mode
+                ldr     sp,=SFE(IRQ_STACK)                  ; End of IRQ_STACK
+
+                bic     r0,r0,#MODE_BITS                    ; Clear the mode bits
+                orr     r0,r0,#SYS_MODE                     ; Set System mode bits
+                msr     cpsr_c,r0                           ; Change the mode
+                ldr     sp,=SFE(CSTACK)                     ; End of CSTACK
+
+
+#ifdef __ARMVFP__
+; Enable the VFP coprocessor.
+                mov     r0, #0x40000000                 ; Set EN bit in VFP
+                fmxr    fpexc, r0                       ; FPEXC, clear others.
+
+; Disable underflow exceptions by setting flush to zero mode.
+; For full IEEE 754 underflow compliance this code should be removed
+; and the appropriate exception handler installed.
+                mov     r0, #0x01000000		        ; Set FZ bit in VFP
+                fmxr    fpscr, r0                       ; FPSCR, clear others.
+#endif
+
+; Add more initialization here
+		        msr   CPSR_c,#I_BIT | F_BIT | SVC_MODE
+
+
+; Continue to ?main for more IAR specific system startup
+
+                ldr     r0,=?main
+                bx      r0
+
+    END         ;- Terminates the assembly of the last module in a file
diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Cstartup_SAM7.c b/20080212/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Cstartup_SAM7.c
new file mode 100644
index 000000000..0b48391b3
--- /dev/null
+++ b/20080212/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Cstartup_SAM7.c
@@ -0,0 +1,97 @@
+//-----------------------------------------------------------------------------
+//         ATMEL Microcontroller Software Support  -  ROUSSET  -
+//-----------------------------------------------------------------------------
+// DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//-----------------------------------------------------------------------------
+// File Name           : Cstartup_SAM7.c
+// Object              : Low level initialisations written in C for Tools
+//                       For AT91SAM7X256 with 2 flash plane
+// Creation            : JPP  14-Sep-2006
+//-----------------------------------------------------------------------------
+
+
+#include "Board.h"
+//  The following functions must be write in ARM mode this function called
+// directly by exception vector
+extern void AT91F_Spurious_handler(void);
+extern void AT91F_Default_IRQ_handler(void);
+extern void AT91F_Default_FIQ_handler(void);
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_LowLevelInit
+//* \brief This function performs very low level HW initialization
+//*        this function can use a Stack, depending the compilation
+//*        optimization mode
+//*----------------------------------------------------------------------------
+void AT91F_LowLevelInit(void) @ "ICODE"
+{
+    unsigned char i;
+    ///////////////////////////////////////////////////////////////////////////
+    // EFC Init
+    ///////////////////////////////////////////////////////////////////////////
+    AT91C_BASE_MC->MC_FMR = AT91C_MC_FWS_1FWS ;
+
+    ///////////////////////////////////////////////////////////////////////////
+    // Init PMC Step 1. Enable Main Oscillator
+    // Main Oscillator startup time is board specific:
+    // Main Oscillator Startup Time worst case (3MHz) corresponds to 15ms
+    // (0x40 for AT91C_CKGR_OSCOUNT field)
+    ///////////////////////////////////////////////////////////////////////////
+    AT91C_BASE_PMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x40 <<8) | AT91C_CKGR_MOSCEN ));
+    // Wait Main Oscillator stabilization
+    while(!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS));
+
+    ///////////////////////////////////////////////////////////////////////////
+    // Init PMC Step 2.
+    // Set PLL to 96MHz (96,109MHz) and UDP Clock to 48MHz
+    // PLL Startup time depends on PLL RC filter: worst case is choosen
+    // UDP Clock (48,058MHz) is compliant with the Universal Serial Bus
+    // Specification (+/- 0.25% for full speed)
+    ///////////////////////////////////////////////////////////////////////////
+    AT91C_BASE_PMC->PMC_PLLR = AT91C_CKGR_USBDIV_1           |
+    						   (16 << 8)                     |
+                               (AT91C_CKGR_MUL & (72 << 16)) |
+                               (AT91C_CKGR_DIV & 14);
+    // Wait for PLL stabilization
+    while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK) );
+    // Wait until the master clock is established for the case we already
+    // turn on the PLL
+    while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) );
+
+    ///////////////////////////////////////////////////////////////////////////
+    // Init PMC Step 3.
+    // Selection of Master Clock MCK equal to (Processor Clock PCK) PLL/2=48MHz
+    // The PMC_MCKR register must not be programmed in a single write operation
+    // (see. Product Errata Sheet)
+    ///////////////////////////////////////////////////////////////////////////
+    AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2;
+    // Wait until the master clock is established
+    while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) );
+
+    AT91C_BASE_PMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK;
+    // Wait until the master clock is established
+    while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) );
+
+    ///////////////////////////////////////////////////////////////////////////
+    //  Disable Watchdog (write once register)
+    ///////////////////////////////////////////////////////////////////////////
+    AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS;
+
+    ///////////////////////////////////////////////////////////////////////////
+    //  Init AIC: assign corresponding handler for each interrupt source
+    ///////////////////////////////////////////////////////////////////////////
+    AT91C_BASE_AIC->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler ;
+    for (i = 1; i < 31; i++) {
+        AT91C_BASE_AIC->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler ;
+    }
+    AT91C_BASE_AIC->AIC_SPU = (unsigned int) AT91F_Spurious_handler;
+}
diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Emac.h b/20080212/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Emac.h
new file mode 100644
index 000000000..7551a3648
--- /dev/null
+++ b/20080212/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Emac.h
@@ -0,0 +1,195 @@
+//*----------------------------------------------------------------------------
+//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
+//*----------------------------------------------------------------------------
+//* The software is delivered "AS IS" without warranty or condition of any
+//* kind, either express, implied or statutory. This includes without
+//* limitation any warranty or condition with respect to merchantability or
+//* fitness for any particular purpose, or against the infringements of
+//* intellectual property rights of others.
+//*----------------------------------------------------------------------------
+//* File Name           : Emac.h
+//* Object              : Emac header file
+//* Creation            : Hi   11/18/2002
+//*
+//*----------------------------------------------------------------------------
+#ifndef AT91C_EMAC_H
+#define AT91C_EMAC_H
+
+
+//* Allows to display all IP header in the main.c
+//* If not defined, only ICMP packets are displayed
+#define AT91C_DISPLAY_ALL_IPHEADER		0
+
+#define NB_RX_BUFFERS			25			//* Number of receive buffers
+#define ETH_RX_BUFFER_SIZE		128         //*
+
+#define NB_TX_BUFFERS			2		//* Number of Transmit buffers
+#define ETH_TX_BUFFER_SIZE		UIP_BUFSIZE       //*
+
+#define AT91C_NO_IPPACKET		0
+#define AT91C_IPPACKET	        1
+
+#define ARP_REQUEST				0x0001
+#define ARP_REPLY				0x0002
+#define PROT_ARP				0x0806
+#define PROT_IP					0x0800
+#define PROT_ICMP				0x01
+#define ICMP_ECHO_REQUEST		0x08
+#define ICMP_ECHO_REPLY			0x00
+
+#define AT91C_EMAC_CLKEN 0x2
+#define SWAP16(x)	(((x & 0xff) << 8) | (x >> 8))
+
+#if 0
+//* Transfer descriptor structure
+typedef struct _AT91S_TdDescriptor {
+	unsigned int addr;
+	unsigned int status;
+}AT91S_TdDescriptor, *AT91PS_TdDescriptor;
+#endif
+
+//* Receive Transfer descriptor structure
+typedef struct  _AT91S_RxTdDescriptor {
+	unsigned int addr;
+	union
+	{
+		unsigned int status;
+		struct {
+			unsigned int Length:11;
+			unsigned int Res0:1;
+			unsigned int Rxbuf_off:2;
+			unsigned int StartOfFrame:1;
+			unsigned int EndOfFrame:1;
+			unsigned int Cfi:1;
+			unsigned int VlanPriority:3;
+			unsigned int PriorityTag:1;
+			unsigned int VlanTag:1;
+			unsigned int TypeID:1;
+			unsigned int Sa4Match:1;
+			unsigned int Sa3Match:1;
+			unsigned int Sa2Match:1;
+			unsigned int Sa1Match:1;
+			unsigned int Res1:1;
+			unsigned int ExternalAdd:1;
+			unsigned int UniCast:1;
+			unsigned int MultiCast:1;
+			unsigned int BroadCast:1;
+		}S_Status;		
+	}U_Status;
+}AT91S_RxTdDescriptor, *AT91PS_RxTdDescriptor;
+
+
+//* Transmit Transfer descriptor structure
+typedef struct _AT91S_TxTdDescriptor {
+	unsigned int addr;
+	union
+	{
+		unsigned int status;
+		struct {
+			unsigned int Length:11;
+			unsigned int Res0:4;
+			unsigned int LastBuff:1;
+			unsigned int NoCrc:1;
+			unsigned int Res1:10;
+			unsigned int BufExhausted:1;
+			unsigned int TransmitUnderrun:1;
+			unsigned int TransmitError:1;
+			unsigned int Wrap:1;
+			unsigned int BuffUsed:1;
+		}S_Status;		
+	}U_Status;
+}AT91S_TxTdDescriptor, *AT91PS_TxTdDescriptor;
+
+#define AT91C_OWNERSHIP_BIT		0x00000001
+
+/* Receive status defintion */
+#define AT91C_BROADCAST_ADDR	((unsigned int) (1 << 31))	//* Broadcat address detected
+#define AT91C_MULTICAST_HASH 	((unsigned int) (1 << 30))	//* MultiCast hash match
+#define AT91C_UNICAST_HASH 	    ((unsigned int) (1 << 29))	//* UniCast hash match
+#define AT91C_EXTERNAL_ADDR	    ((unsigned int) (1 << 28))	//* External Address match
+#define AT91C_SA1_ADDR	    	((unsigned int) (1 << 26))	//* Specific address 1 match
+#define AT91C_SA2_ADDR	    	((unsigned int) (1 << 25))	//* Specific address 2 match
+#define AT91C_SA3_ADDR	    	((unsigned int) (1 << 24))	//* Specific address 3 match
+#define AT91C_SA4_ADDR	    	((unsigned int) (1 << 23))	//* Specific address 4 match
+#define AT91C_TYPE_ID	    	((unsigned int) (1 << 22))	//* Type ID match
+#define AT91C_VLAN_TAG	    	((unsigned int) (1 << 21))	//* VLAN tag detected
+#define AT91C_PRIORITY_TAG    	((unsigned int) (1 << 20))	//* PRIORITY tag detected
+#define AT91C_VLAN_PRIORITY    	((unsigned int) (7 << 17))  //* PRIORITY Mask
+#define AT91C_CFI_IND        	((unsigned int) (1 << 16))  //* CFI indicator
+#define AT91C_EOF           	((unsigned int) (1 << 15))  //* EOF
+#define AT91C_SOF           	((unsigned int) (1 << 14))  //* SOF
+#define AT91C_RBF_OFFSET     	((unsigned int) (3 << 12))  //* Receive Buffer Offset Mask
+#define AT91C_LENGTH_FRAME     	((unsigned int) 0x07FF)     //* Length of frame
+
+/* Transmit Status definition */
+#define AT91C_TRANSMIT_OK		((unsigned int) (1 << 31))	//*
+#define AT91C_TRANSMIT_WRAP		((unsigned int) (1 << 30))	//* Wrap bit: mark the last descriptor
+#define AT91C_TRANSMIT_ERR		((unsigned int) (1 << 29))	//* RLE:transmit error
+#define AT91C_TRANSMIT_UND		((unsigned int) (1 << 28))	//* Transmit Underrun
+#define AT91C_BUF_EX     		((unsigned int) (1 << 27))	//* Buffers exhausted in mid frame
+#define AT91C_TRANSMIT_NO_CRC	((unsigned int) (1 << 16))	//* No CRC will be appended to the current frame
+#define AT91C_LAST_BUFFER    	((unsigned int) (1 << 15))	//*
+
+#define ARP_ETHER	 		1		/* Ethernet  hardware address	*/
+#define ARPOP_REQUEST    	1		/* Request  to resolve  address	*/
+#define ARPOP_REPLY	    	2		/* Response to previous request	*/
+#define RARPOP_REQUEST   	3		/* Request  to resolve  address	*/
+#define RARPOP_REPLY	    4		/* Response to previous request */
+
+
+typedef struct _AT91S_EthHdr
+{
+	unsigned char		et_dest[6];	/* Destination node		*/
+	unsigned char		et_src[6];	/* Source node			*/
+	unsigned short		et_protlen;	/* Protocol or length		*/
+} AT91S_EthHdr, *AT91PS_EthHdr;
+
+typedef struct _AT91S_ArpHdr
+{
+	unsigned short		ar_hrd;		/* Format of hardware address	*/
+	unsigned short		ar_pro;		/* Format of protocol address	*/
+	unsigned char		ar_hln;		/* Length of hardware address	*/
+	unsigned char		ar_pln;		/* Length of protocol address	*/
+	unsigned short		ar_op;		/* Operation			*/
+	unsigned char		ar_sha[6];	/* Sender hardware address	*/
+	unsigned char		ar_spa[4];	/* Sender protocol address	*/
+	unsigned char		ar_tha[6];	/* Target hardware address	*/
+	unsigned char		ar_tpa[4];	/* Target protocol address	*/
+} AT91S_ArpHdr, *AT91PS_ArpHdr;
+
+//* IP Header structure
+typedef struct _AT91S_IPheader {
+	unsigned char	ip_hl_v;	/* header length and version	*/
+	unsigned char	ip_tos;		/* type of service		*/
+	unsigned short	ip_len;		/* total length			*/
+	unsigned short	ip_id;		/* identification		*/
+	unsigned short	ip_off;		/* fragment offset field	*/
+	unsigned char	ip_ttl;		/* time to live			*/
+	unsigned char	ip_p;		/* protocol			*/
+	unsigned short	ip_sum;		/* checksum			*/
+	unsigned char	ip_src[4];	/* Source IP address		*/
+	unsigned char	ip_dst[4];	/* Destination IP address	*/
+	unsigned short	udp_src;	/* UDP source port		*/
+	unsigned short	udp_dst;	/* UDP destination port		*/
+	unsigned short	udp_len;	/* Length of UDP packet		*/
+	unsigned short	udp_xsum;	/* Checksum			*/
+} AT91S_IPheader, *AT91PS_IPheader;
+
+//* ICMP echo header structure
+typedef struct _AT91S_IcmpEchoHdr {
+    unsigned char   type;       /* type of message */
+    unsigned char   code;       /* type subcode */
+    unsigned short  cksum;      /* ones complement cksum of struct */
+    unsigned short  id;         /* identifier */
+    unsigned short  seq;        /* sequence number */
+}AT91S_IcmpEchoHdr, *AT91PS_IcmpEchoHdr;
+
+
+typedef struct _AT91S_EthPack
+{
+	AT91S_EthHdr	EthHdr;
+	AT91S_ArpHdr	ArpHdr;
+} AT91S_EthPack, *AT91PS_EthPack;
+
+
+#endif //* AT91C_EMAC_H
diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/SrcIAR/dbgu.c b/20080212/Demo/uIP_Demo_IAR_ARM7/SrcIAR/dbgu.c
new file mode 100644
index 000000000..cee31b1d5
--- /dev/null
+++ b/20080212/Demo/uIP_Demo_IAR_ARM7/SrcIAR/dbgu.c
@@ -0,0 +1,95 @@
+//*----------------------------------------------------------------------------
+//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
+//*----------------------------------------------------------------------------
+//* The software is delivered "AS IS" without warranty or condition of any
+//* kind, either express, implied or statutory. This includes without
+//* limitation any warranty or condition with respect to merchantability or
+//* fitness for any particular purpose, or against the infringements of
+//* intellectual property rights of others.
+//*----------------------------------------------------------------------------
+//* File Name           : dbgu.c
+//* Object              : DBGU routines written in C
+//* Creation            : JG   16/Aug/2004
+//*----------------------------------------------------------------------------
+
+// Include Standard files
+#include "Board.h"
+
+//*--------------------------1--------------------------------------------------
+//* \fn    AT91F_DBGU_Printk
+//* \brief This function is used to send a string through the DBGU channel (Very low level debugging)
+//*----------------------------------------------------------------------------
+void AT91F_DBGU_Printk(	char *buffer)
+{
+    AT91PS_DBGU pDbgu = AT91C_BASE_DBGU ; 
+    unsigned int temp;
+    
+    while(*buffer != '\0') 
+    {
+        temp=0;
+        
+	while (temp==0)
+	{
+	  if ( (pDbgu->DBGU_CSR & 0x0200) == 0)
+	    temp=0;
+	  else
+	    temp=1;
+	}
+
+        pDbgu->DBGU_THR = *buffer;
+        buffer++;
+    }
+}
+
+
+void Init_DBGU_CLK(void)
+{
+  AT91F_PMC_EnablePeriphClock(AT91C_BASE_PMC, ((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+void Init_DBGU_BGR(unsigned short baud)
+{
+  AT91PS_DBGU pDbgu = AT91C_BASE_DBGU ; 
+  
+  pDbgu->DBGU_BRGR = (unsigned short)baud;
+}
+
+void DBGU_TX_Enable(void)
+{
+  AT91PS_DBGU pDbgu = AT91C_BASE_DBGU ; 
+  
+  pDbgu->DBGU_CR = 0x00000040;
+}
+
+void DBGU_RX_Enable(void)
+{
+  AT91PS_DBGU pDbgu = AT91C_BASE_DBGU ; 
+  
+  pDbgu->DBGU_CR = 0x00000010;
+}
+
+void DBGU_RX_TX_RST_DIS(void)
+{
+  AT91PS_DBGU pDbgu = AT91C_BASE_DBGU ; 
+  pDbgu->DBGU_CR = 0x000000AC;
+}
+
+void DBGU_Parity_Cfg(unsigned int par)
+{
+  AT91PS_DBGU pDbgu = AT91C_BASE_DBGU ; 
+  
+  pDbgu->DBGU_MR = par << 9;
+}
+
+
+void Init_DBGU(void)
+{ 
+  AT91F_DBGU_CfgPIO();
+  DBGU_RX_TX_RST_DIS();
+  Init_DBGU_BGR(26);  //26 <=> 115kBd
+  DBGU_Parity_Cfg(4);
+  DBGU_TX_Enable();   
+  DBGU_RX_Enable();
+}
+
+
diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/SrcIAR/dbgu.h b/20080212/Demo/uIP_Demo_IAR_ARM7/SrcIAR/dbgu.h
new file mode 100644
index 000000000..58f50a046
--- /dev/null
+++ b/20080212/Demo/uIP_Demo_IAR_ARM7/SrcIAR/dbgu.h
@@ -0,0 +1,22 @@
+//*----------------------------------------------------------------------------
+//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
+//*----------------------------------------------------------------------------
+//* The software is delivered "AS IS" without warranty or condition of any
+//* kind, either express, implied or statutory. This includes without
+//* limitation any warranty or condition with respect to merchantability or
+//* fitness for any particular purpose, or against the infringements of
+//* intellectual property rights of others.
+//*----------------------------------------------------------------------------
+//* File Name           : dbgu.c
+//* Object              : DBGU routines written in C
+//* Creation            : JG   16/Aug/2004
+//*----------------------------------------------------------------------------
+
+// Include Standard files
+extern void APPLI_DBGU(void);   
+extern void D1_TEST_REGISTER_RESET_VALUES(void);
+extern void D2_CHIP_ID_VALUES(void);
+
+
+
+
diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/SrcIAR/init.c b/20080212/Demo/uIP_Demo_IAR_ARM7/SrcIAR/init.c
new file mode 100644
index 000000000..cbb1ee48e
--- /dev/null
+++ b/20080212/Demo/uIP_Demo_IAR_ARM7/SrcIAR/init.c
@@ -0,0 +1,31 @@
+//*----------------------------------------------------------------------------
+//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
+//*----------------------------------------------------------------------------
+//* The software is delivered "AS IS" without warranty or condition of any
+//* kind, either express, implied or statutory. This includes without
+//* limitation any warranty or condition with respect to merchantability or
+//* fitness for any particular purpose, or against the infringements of
+//* intellectual property rights of others.
+//*----------------------------------------------------------------------------
+//* File Name           : init.c
+//* Object              : Low level initialisations written in C
+//* Creation            : ODi   06/26/2002
+//*
+//*----------------------------------------------------------------------------
+#include "board.h"
+//#include "init.h"
+#include 
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_Printk
+//* \brief This function is used to send a string through the DBGU channel (Very low level debugging)
+//*----------------------------------------------------------------------------
+void AT91F_DBGU_Printk(
+	char *buffer) // \arg pointer to a string ending by \0
+{
+	while(*buffer != '\0') {
+		while (!AT91F_US_TxReady((AT91PS_USART)AT91C_BASE_DBGU));
+		AT91F_US_PutChar((AT91PS_USART)AT91C_BASE_DBGU, *buffer++);
+	}
+}
+
diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/SrcIAR/ioat91sam7x128.h b/20080212/Demo/uIP_Demo_IAR_ARM7/SrcIAR/ioat91sam7x128.h
new file mode 100644
index 000000000..df9caccb5
--- /dev/null
+++ b/20080212/Demo/uIP_Demo_IAR_ARM7/SrcIAR/ioat91sam7x128.h
@@ -0,0 +1,4700 @@
+// - ----------------------------------------------------------------------------
+// -          ATMEL Microcontroller Software Support  -  ROUSSET  -
+// - ----------------------------------------------------------------------------
+// -  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+// -  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// -  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+// -  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+// -  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// -  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+// -  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// -  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// -  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+// -  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// - ----------------------------------------------------------------------------
+// - File Name           : AT91SAM7X128.h
+// - Object              : AT91SAM7X128 definitions
+// - Generated           : AT91 SW Application Group  05/20/2005 (16:22:23)
+// - 
+// - CVS Reference       : /AT91SAM7X128.pl/1.14/Tue May 10 12:12:05 2005//
+// - CVS Reference       : /SYS_SAM7X.pl/1.3/Tue Feb  1 17:01:43 2005//
+// - CVS Reference       : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
+// - CVS Reference       : /PMC_SAM7X.pl/1.4/Tue Feb  8 13:58:10 2005//
+// - CVS Reference       : /RSTC_SAM7X.pl/1.1/Tue Feb  1 16:16:26 2005//
+// - CVS Reference       : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
+// - CVS Reference       : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
+// - CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
+// - CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:18:28 2005//
+// - CVS Reference       : /RTTC_6081A.pl/1.2/Tue Nov  9 14:43:58 2004//
+// - CVS Reference       : /PITC_6079A.pl/1.2/Tue Nov  9 14:43:56 2004//
+// - CVS Reference       : /WDTC_6080A.pl/1.3/Tue Nov  9 14:44:00 2004//
+// - CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:05:48 2005//
+// - CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 08:48:54 2005//
+// - CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
+// - CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
+// - CVS Reference       : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
+// - CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
+// - CVS Reference       : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
+// - CVS Reference       : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
+// - CVS Reference       : /CAN_6019B.pl/1.1/Tue Mar  8 12:42:22 2005//
+// - CVS Reference       : /EMACB_6119A.pl/1.5/Thu Feb  3 15:52:04 2005//
+// - CVS Reference       : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
+// - CVS Reference       : /AES_6149A.pl/1.10/Mon Feb  7 09:44:25 2005//
+// - CVS Reference       : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//
+// - ----------------------------------------------------------------------------
+
+#ifndef AT91SAM7X128_H
+#define AT91SAM7X128_H
+
+#ifdef __IAR_SYSTEMS_ICC__
+
+typedef volatile unsigned int AT91_REG;// Hardware register definition
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR System Peripherals
+// *****************************************************************************
+typedef struct _AT91S_SYS {
+	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
+	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
+	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
+	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
+	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
+	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
+	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
+	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
+	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
+	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
+	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
+	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
+	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
+	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
+	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
+	AT91_REG	 Reserved2[45]; 	// 
+	AT91_REG	 DBGU_CR; 	// Control Register
+	AT91_REG	 DBGU_MR; 	// Mode Register
+	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
+	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
+	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
+	AT91_REG	 DBGU_CSR; 	// Channel Status Register
+	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
+	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
+	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 Reserved3[7]; 	// 
+	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
+	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
+	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
+	AT91_REG	 Reserved4[45]; 	// 
+	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
+	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
+	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
+	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
+	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
+	AT91_REG	 Reserved5[54]; 	// 
+	AT91_REG	 PIOA_PER; 	// PIO Enable Register
+	AT91_REG	 PIOA_PDR; 	// PIO Disable Register
+	AT91_REG	 PIOA_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved6[1]; 	// 
+	AT91_REG	 PIOA_OER; 	// Output Enable Register
+	AT91_REG	 PIOA_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIOA_OSR; 	// Output Status Register
+	AT91_REG	 Reserved7[1]; 	// 
+	AT91_REG	 PIOA_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIOA_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIOA_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved8[1]; 	// 
+	AT91_REG	 PIOA_SODR; 	// Set Output Data Register
+	AT91_REG	 PIOA_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIOA_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIOA_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIOA_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIOA_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIOA_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIOA_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIOA_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIOA_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIOA_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved9[1]; 	// 
+	AT91_REG	 PIOA_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIOA_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIOA_PPUSR; 	// Pull-up Status Register
+	AT91_REG	 Reserved10[1]; 	// 
+	AT91_REG	 PIOA_ASR; 	// Select A Register
+	AT91_REG	 PIOA_BSR; 	// Select B Register
+	AT91_REG	 PIOA_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved11[9]; 	// 
+	AT91_REG	 PIOA_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIOA_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIOA_OWSR; 	// Output Write Status Register
+	AT91_REG	 Reserved12[85]; 	// 
+	AT91_REG	 PIOB_PER; 	// PIO Enable Register
+	AT91_REG	 PIOB_PDR; 	// PIO Disable Register
+	AT91_REG	 PIOB_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved13[1]; 	// 
+	AT91_REG	 PIOB_OER; 	// Output Enable Register
+	AT91_REG	 PIOB_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIOB_OSR; 	// Output Status Register
+	AT91_REG	 Reserved14[1]; 	// 
+	AT91_REG	 PIOB_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIOB_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIOB_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved15[1]; 	// 
+	AT91_REG	 PIOB_SODR; 	// Set Output Data Register
+	AT91_REG	 PIOB_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIOB_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIOB_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIOB_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIOB_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIOB_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIOB_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIOB_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIOB_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIOB_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved16[1]; 	// 
+	AT91_REG	 PIOB_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIOB_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIOB_PPUSR; 	// Pull-up Status Register
+	AT91_REG	 Reserved17[1]; 	// 
+	AT91_REG	 PIOB_ASR; 	// Select A Register
+	AT91_REG	 PIOB_BSR; 	// Select B Register
+	AT91_REG	 PIOB_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved18[9]; 	// 
+	AT91_REG	 PIOB_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIOB_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIOB_OWSR; 	// Output Write Status Register
+	AT91_REG	 Reserved19[341]; 	// 
+	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
+	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
+	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
+	AT91_REG	 Reserved20[1]; 	// 
+	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
+	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
+	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
+	AT91_REG	 Reserved21[1]; 	// 
+	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
+	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 Reserved22[1]; 	// 
+	AT91_REG	 PMC_PLLR; 	// PLL Register
+	AT91_REG	 PMC_MCKR; 	// Master Clock Register
+	AT91_REG	 Reserved23[3]; 	// 
+	AT91_REG	 PMC_PCKR[4]; 	// Programmable Clock Register
+	AT91_REG	 Reserved24[4]; 	// 
+	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
+	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PMC_SR; 	// Status Register
+	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved25[36]; 	// 
+	AT91_REG	 RSTC_RCR; 	// Reset Control Register
+	AT91_REG	 RSTC_RSR; 	// Reset Status Register
+	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
+	AT91_REG	 Reserved26[5]; 	// 
+	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
+	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
+	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
+	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
+	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
+	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
+	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
+	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
+	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
+	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
+	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
+	AT91_REG	 Reserved27[5]; 	// 
+	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
+} AT91S_SYS, *AT91PS_SYS;
+
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
+// *****************************************************************************
+typedef struct _AT91S_AIC {
+	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
+	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
+	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
+	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
+	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
+	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
+	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
+	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
+	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
+	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
+	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
+	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
+	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
+	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
+	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
+} AT91S_AIC, *AT91PS_AIC;
+
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
+#define AT91C_AIC_PRIOR       ((unsigned int) 0x7 <<  0) // (AIC) Priority Level
+#define 	AT91C_AIC_PRIOR_LOWEST               ((unsigned int) 0x0) // (AIC) Lowest priority level
+#define 	AT91C_AIC_PRIOR_HIGHEST              ((unsigned int) 0x7) // (AIC) Highest priority level
+#define AT91C_AIC_SRCTYPE     ((unsigned int) 0x3 <<  5) // (AIC) Interrupt Source Type
+#define 	AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       ((unsigned int) 0x0 <<  5) // (AIC) Internal Sources Code Label High-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        ((unsigned int) 0x0 <<  5) // (AIC) External Sources Code Label Low-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    ((unsigned int) 0x1 <<  5) // (AIC) Internal Sources Code Label Positive Edge triggered
+#define 	AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    ((unsigned int) 0x1 <<  5) // (AIC) External Sources Code Label Negative Edge triggered
+#define 	AT91C_AIC_SRCTYPE_HIGH_LEVEL           ((unsigned int) 0x2 <<  5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_POSITIVE_EDGE        ((unsigned int) 0x3 <<  5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
+#define AT91C_AIC_NFIQ        ((unsigned int) 0x1 <<  0) // (AIC) NFIQ Status
+#define AT91C_AIC_NIRQ        ((unsigned int) 0x1 <<  1) // (AIC) NIRQ Status
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
+#define AT91C_AIC_DCR_PROT    ((unsigned int) 0x1 <<  0) // (AIC) Protection Mode
+#define AT91C_AIC_DCR_GMSK    ((unsigned int) 0x1 <<  1) // (AIC) General Mask
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
+// *****************************************************************************
+typedef struct _AT91S_PDC {
+	AT91_REG	 PDC_RPR; 	// Receive Pointer Register
+	AT91_REG	 PDC_RCR; 	// Receive Counter Register
+	AT91_REG	 PDC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 PDC_TCR; 	// Transmit Counter Register
+	AT91_REG	 PDC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 PDC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 PDC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 PDC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 PDC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 PDC_PTSR; 	// PDC Transfer Status Register
+} AT91S_PDC, *AT91PS_PDC;
+
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
+#define AT91C_PDC_RXTEN       ((unsigned int) 0x1 <<  0) // (PDC) Receiver Transfer Enable
+#define AT91C_PDC_RXTDIS      ((unsigned int) 0x1 <<  1) // (PDC) Receiver Transfer Disable
+#define AT91C_PDC_TXTEN       ((unsigned int) 0x1 <<  8) // (PDC) Transmitter Transfer Enable
+#define AT91C_PDC_TXTDIS      ((unsigned int) 0x1 <<  9) // (PDC) Transmitter Transfer Disable
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Debug Unit
+// *****************************************************************************
+typedef struct _AT91S_DBGU {
+	AT91_REG	 DBGU_CR; 	// Control Register
+	AT91_REG	 DBGU_MR; 	// Mode Register
+	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
+	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
+	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
+	AT91_REG	 DBGU_CSR; 	// Channel Status Register
+	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
+	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
+	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 Reserved0[7]; 	// 
+	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
+	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
+	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
+	AT91_REG	 Reserved1[45]; 	// 
+	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
+	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
+	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
+	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
+	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
+} AT91S_DBGU, *AT91PS_DBGU;
+
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
+#define AT91C_US_RSTRX        ((unsigned int) 0x1 <<  2) // (DBGU) Reset Receiver
+#define AT91C_US_RSTTX        ((unsigned int) 0x1 <<  3) // (DBGU) Reset Transmitter
+#define AT91C_US_RXEN         ((unsigned int) 0x1 <<  4) // (DBGU) Receiver Enable
+#define AT91C_US_RXDIS        ((unsigned int) 0x1 <<  5) // (DBGU) Receiver Disable
+#define AT91C_US_TXEN         ((unsigned int) 0x1 <<  6) // (DBGU) Transmitter Enable
+#define AT91C_US_TXDIS        ((unsigned int) 0x1 <<  7) // (DBGU) Transmitter Disable
+#define AT91C_US_RSTSTA       ((unsigned int) 0x1 <<  8) // (DBGU) Reset Status Bits
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
+#define AT91C_US_PAR          ((unsigned int) 0x7 <<  9) // (DBGU) Parity type
+#define 	AT91C_US_PAR_EVEN                 ((unsigned int) 0x0 <<  9) // (DBGU) Even Parity
+#define 	AT91C_US_PAR_ODD                  ((unsigned int) 0x1 <<  9) // (DBGU) Odd Parity
+#define 	AT91C_US_PAR_SPACE                ((unsigned int) 0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
+#define 	AT91C_US_PAR_MARK                 ((unsigned int) 0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
+#define 	AT91C_US_PAR_NONE                 ((unsigned int) 0x4 <<  9) // (DBGU) No Parity
+#define 	AT91C_US_PAR_MULTI_DROP           ((unsigned int) 0x6 <<  9) // (DBGU) Multi-drop mode
+#define AT91C_US_CHMODE       ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode
+#define 	AT91C_US_CHMODE_NORMAL               ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+#define 	AT91C_US_CHMODE_AUTO                 ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+#define 	AT91C_US_CHMODE_LOCAL                ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+#define 	AT91C_US_CHMODE_REMOTE               ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+#define AT91C_US_RXRDY        ((unsigned int) 0x1 <<  0) // (DBGU) RXRDY Interrupt
+#define AT91C_US_TXRDY        ((unsigned int) 0x1 <<  1) // (DBGU) TXRDY Interrupt
+#define AT91C_US_ENDRX        ((unsigned int) 0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
+#define AT91C_US_ENDTX        ((unsigned int) 0x1 <<  4) // (DBGU) End of Transmit Interrupt
+#define AT91C_US_OVRE         ((unsigned int) 0x1 <<  5) // (DBGU) Overrun Interrupt
+#define AT91C_US_FRAME        ((unsigned int) 0x1 <<  6) // (DBGU) Framing Error Interrupt
+#define AT91C_US_PARE         ((unsigned int) 0x1 <<  7) // (DBGU) Parity Error Interrupt
+#define AT91C_US_TXEMPTY      ((unsigned int) 0x1 <<  9) // (DBGU) TXEMPTY Interrupt
+#define AT91C_US_TXBUFE       ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt
+#define AT91C_US_RXBUFF       ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt
+#define AT91C_US_COMM_TX      ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt
+#define AT91C_US_COMM_RX      ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
+#define AT91C_US_FORCE_NTRST  ((unsigned int) 0x1 <<  0) // (DBGU) Force NTRST in JTAG
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
+// *****************************************************************************
+typedef struct _AT91S_PIO {
+	AT91_REG	 PIO_PER; 	// PIO Enable Register
+	AT91_REG	 PIO_PDR; 	// PIO Disable Register
+	AT91_REG	 PIO_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 PIO_OER; 	// Output Enable Register
+	AT91_REG	 PIO_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIO_OSR; 	// Output Status Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 PIO_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIO_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIO_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved2[1]; 	// 
+	AT91_REG	 PIO_SODR; 	// Set Output Data Register
+	AT91_REG	 PIO_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIO_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIO_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIO_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIO_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIO_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIO_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIO_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIO_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIO_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved3[1]; 	// 
+	AT91_REG	 PIO_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIO_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIO_PPUSR; 	// Pull-up Status Register
+	AT91_REG	 Reserved4[1]; 	// 
+	AT91_REG	 PIO_ASR; 	// Select A Register
+	AT91_REG	 PIO_BSR; 	// Select B Register
+	AT91_REG	 PIO_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved5[9]; 	// 
+	AT91_REG	 PIO_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIO_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIO_OWSR; 	// Output Write Status Register
+} AT91S_PIO, *AT91PS_PIO;
+
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
+// *****************************************************************************
+typedef struct _AT91S_CKGR {
+	AT91_REG	 CKGR_MOR; 	// Main Oscillator Register
+	AT91_REG	 CKGR_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 CKGR_PLLR; 	// PLL Register
+} AT91S_CKGR, *AT91PS_CKGR;
+
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 
+#define AT91C_CKGR_MOSCEN     ((unsigned int) 0x1 <<  0) // (CKGR) Main Oscillator Enable
+#define AT91C_CKGR_OSCBYPASS  ((unsigned int) 0x1 <<  1) // (CKGR) Main Oscillator Bypass
+#define AT91C_CKGR_OSCOUNT    ((unsigned int) 0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 
+#define AT91C_CKGR_MAINF      ((unsigned int) 0xFFFF <<  0) // (CKGR) Main Clock Frequency
+#define AT91C_CKGR_MAINRDY    ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
+// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- 
+#define AT91C_CKGR_DIV        ((unsigned int) 0xFF <<  0) // (CKGR) Divider Selected
+#define 	AT91C_CKGR_DIV_0                    ((unsigned int) 0x0) // (CKGR) Divider output is 0
+#define 	AT91C_CKGR_DIV_BYPASS               ((unsigned int) 0x1) // (CKGR) Divider is bypassed
+#define AT91C_CKGR_PLLCOUNT   ((unsigned int) 0x3F <<  8) // (CKGR) PLL Counter
+#define AT91C_CKGR_OUT        ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range
+#define 	AT91C_CKGR_OUT_0                    ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_1                    ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_2                    ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_3                    ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_MUL        ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier
+#define AT91C_CKGR_USBDIV     ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks
+#define 	AT91C_CKGR_USBDIV_0                    ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output
+#define 	AT91C_CKGR_USBDIV_1                    ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
+#define 	AT91C_CKGR_USBDIV_2                    ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Power Management Controler
+// *****************************************************************************
+typedef struct _AT91S_PMC {
+	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
+	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
+	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
+	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
+	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
+	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 Reserved2[1]; 	// 
+	AT91_REG	 PMC_PLLR; 	// PLL Register
+	AT91_REG	 PMC_MCKR; 	// Master Clock Register
+	AT91_REG	 Reserved3[3]; 	// 
+	AT91_REG	 PMC_PCKR[4]; 	// Programmable Clock Register
+	AT91_REG	 Reserved4[4]; 	// 
+	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
+	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PMC_SR; 	// Status Register
+	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
+} AT91S_PMC, *AT91PS_PMC;
+
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
+#define AT91C_PMC_PCK         ((unsigned int) 0x1 <<  0) // (PMC) Processor Clock
+#define AT91C_PMC_UDP         ((unsigned int) 0x1 <<  7) // (PMC) USB Device Port Clock
+#define AT91C_PMC_PCK0        ((unsigned int) 0x1 <<  8) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK1        ((unsigned int) 0x1 <<  9) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK2        ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK3        ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 
+// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- 
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
+#define AT91C_PMC_CSS         ((unsigned int) 0x3 <<  0) // (PMC) Programmable Clock Selection
+#define 	AT91C_PMC_CSS_SLOW_CLK             ((unsigned int) 0x0) // (PMC) Slow Clock is selected
+#define 	AT91C_PMC_CSS_MAIN_CLK             ((unsigned int) 0x1) // (PMC) Main Clock is selected
+#define 	AT91C_PMC_CSS_PLL_CLK              ((unsigned int) 0x3) // (PMC) Clock from PLL is selected
+#define AT91C_PMC_PRES        ((unsigned int) 0x7 <<  2) // (PMC) Programmable Clock Prescaler
+#define 	AT91C_PMC_PRES_CLK                  ((unsigned int) 0x0 <<  2) // (PMC) Selected clock
+#define 	AT91C_PMC_PRES_CLK_2                ((unsigned int) 0x1 <<  2) // (PMC) Selected clock divided by 2
+#define 	AT91C_PMC_PRES_CLK_4                ((unsigned int) 0x2 <<  2) // (PMC) Selected clock divided by 4
+#define 	AT91C_PMC_PRES_CLK_8                ((unsigned int) 0x3 <<  2) // (PMC) Selected clock divided by 8
+#define 	AT91C_PMC_PRES_CLK_16               ((unsigned int) 0x4 <<  2) // (PMC) Selected clock divided by 16
+#define 	AT91C_PMC_PRES_CLK_32               ((unsigned int) 0x5 <<  2) // (PMC) Selected clock divided by 32
+#define 	AT91C_PMC_PRES_CLK_64               ((unsigned int) 0x6 <<  2) // (PMC) Selected clock divided by 64
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
+#define AT91C_PMC_MOSCS       ((unsigned int) 0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCK        ((unsigned int) 0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask
+#define AT91C_PMC_MCKRDY      ((unsigned int) 0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK0RDY     ((unsigned int) 0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK1RDY     ((unsigned int) 0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK2RDY     ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK3RDY     ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_RSTC {
+	AT91_REG	 RSTC_RCR; 	// Reset Control Register
+	AT91_REG	 RSTC_RSR; 	// Reset Status Register
+	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
+} AT91S_RSTC, *AT91PS_RSTC;
+
+// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 
+#define AT91C_RSTC_PROCRST    ((unsigned int) 0x1 <<  0) // (RSTC) Processor Reset
+#define AT91C_RSTC_PERRST     ((unsigned int) 0x1 <<  2) // (RSTC) Peripheral Reset
+#define AT91C_RSTC_EXTRST     ((unsigned int) 0x1 <<  3) // (RSTC) External Reset
+#define AT91C_RSTC_KEY        ((unsigned int) 0xFF << 24) // (RSTC) Password
+// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 
+#define AT91C_RSTC_URSTS      ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Status
+#define AT91C_RSTC_BODSTS     ((unsigned int) 0x1 <<  1) // (RSTC) Brownout Detection Status
+#define AT91C_RSTC_RSTTYP     ((unsigned int) 0x7 <<  8) // (RSTC) Reset Type
+#define 	AT91C_RSTC_RSTTYP_POWERUP              ((unsigned int) 0x0 <<  8) // (RSTC) Power-up Reset. VDDCORE rising.
+#define 	AT91C_RSTC_RSTTYP_WAKEUP               ((unsigned int) 0x1 <<  8) // (RSTC) WakeUp Reset. VDDCORE rising.
+#define 	AT91C_RSTC_RSTTYP_WATCHDOG             ((unsigned int) 0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
+#define 	AT91C_RSTC_RSTTYP_SOFTWARE             ((unsigned int) 0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
+#define 	AT91C_RSTC_RSTTYP_USER                 ((unsigned int) 0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
+#define 	AT91C_RSTC_RSTTYP_BROWNOUT             ((unsigned int) 0x5 <<  8) // (RSTC) Brownout Reset occured.
+#define AT91C_RSTC_NRSTL      ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level
+#define AT91C_RSTC_SRCMP      ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.
+// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 
+#define AT91C_RSTC_URSTEN     ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Enable
+#define AT91C_RSTC_URSTIEN    ((unsigned int) 0x1 <<  4) // (RSTC) User Reset Interrupt Enable
+#define AT91C_RSTC_ERSTL      ((unsigned int) 0xF <<  8) // (RSTC) User Reset Enable
+#define AT91C_RSTC_BODIEN     ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_RTTC {
+	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
+	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
+	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
+	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
+} AT91S_RTTC, *AT91PS_RTTC;
+
+// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 
+#define AT91C_RTTC_RTPRES     ((unsigned int) 0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
+#define AT91C_RTTC_ALMIEN     ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable
+#define AT91C_RTTC_RTTINCIEN  ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
+#define AT91C_RTTC_RTTRST     ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart
+// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 
+#define AT91C_RTTC_ALMV       ((unsigned int) 0x0 <<  0) // (RTTC) Alarm Value
+// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 
+#define AT91C_RTTC_CRTV       ((unsigned int) 0x0 <<  0) // (RTTC) Current Real-time Value
+// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 
+#define AT91C_RTTC_ALMS       ((unsigned int) 0x1 <<  0) // (RTTC) Real-time Alarm Status
+#define AT91C_RTTC_RTTINC     ((unsigned int) 0x1 <<  1) // (RTTC) Real-time Timer Increment
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_PITC {
+	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
+	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
+	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
+	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
+} AT91S_PITC, *AT91PS_PITC;
+
+// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
+#define AT91C_PITC_PIV        ((unsigned int) 0xFFFFF <<  0) // (PITC) Periodic Interval Value
+#define AT91C_PITC_PITEN      ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled
+#define AT91C_PITC_PITIEN     ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
+// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
+#define AT91C_PITC_PITS       ((unsigned int) 0x1 <<  0) // (PITC) Periodic Interval Timer Status
+// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
+#define AT91C_PITC_CPIV       ((unsigned int) 0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
+#define AT91C_PITC_PICNT      ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter
+// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_WDTC {
+	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
+	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
+	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
+} AT91S_WDTC, *AT91PS_WDTC;
+
+// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 
+#define AT91C_WDTC_WDRSTT     ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Restart
+#define AT91C_WDTC_KEY        ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password
+// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 
+#define AT91C_WDTC_WDV        ((unsigned int) 0xFFF <<  0) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDFIEN     ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
+#define AT91C_WDTC_WDRSTEN    ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable
+#define AT91C_WDTC_WDRPROC    ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDDIS      ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable
+#define AT91C_WDTC_WDD        ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value
+#define AT91C_WDTC_WDDBGHLT   ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt
+#define AT91C_WDTC_WDIDLEHLT  ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt
+// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 
+#define AT91C_WDTC_WDUNF      ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Underflow
+#define AT91C_WDTC_WDERR      ((unsigned int) 0x1 <<  1) // (WDTC) Watchdog Error
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_VREG {
+	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
+} AT91S_VREG, *AT91PS_VREG;
+
+// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- 
+#define AT91C_VREG_PSTDBY     ((unsigned int) 0x1 <<  0) // (VREG) Voltage Regulator Power Standby Mode
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_MC {
+	AT91_REG	 MC_RCR; 	// MC Remap Control Register
+	AT91_REG	 MC_ASR; 	// MC Abort Status Register
+	AT91_REG	 MC_AASR; 	// MC Abort Address Status Register
+	AT91_REG	 Reserved0[21]; 	// 
+	AT91_REG	 MC_FMR; 	// MC Flash Mode Register
+	AT91_REG	 MC_FCR; 	// MC Flash Command Register
+	AT91_REG	 MC_FSR; 	// MC Flash Status Register
+} AT91S_MC, *AT91PS_MC;
+
+// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 
+#define AT91C_MC_RCB          ((unsigned int) 0x1 <<  0) // (MC) Remap Command Bit
+// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 
+#define AT91C_MC_UNDADD       ((unsigned int) 0x1 <<  0) // (MC) Undefined Addess Abort Status
+#define AT91C_MC_MISADD       ((unsigned int) 0x1 <<  1) // (MC) Misaligned Addess Abort Status
+#define AT91C_MC_ABTSZ        ((unsigned int) 0x3 <<  8) // (MC) Abort Size Status
+#define 	AT91C_MC_ABTSZ_BYTE                 ((unsigned int) 0x0 <<  8) // (MC) Byte
+#define 	AT91C_MC_ABTSZ_HWORD                ((unsigned int) 0x1 <<  8) // (MC) Half-word
+#define 	AT91C_MC_ABTSZ_WORD                 ((unsigned int) 0x2 <<  8) // (MC) Word
+#define AT91C_MC_ABTTYP       ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
+#define 	AT91C_MC_ABTTYP_DATAR                ((unsigned int) 0x0 << 10) // (MC) Data Read
+#define 	AT91C_MC_ABTTYP_DATAW                ((unsigned int) 0x1 << 10) // (MC) Data Write
+#define 	AT91C_MC_ABTTYP_FETCH                ((unsigned int) 0x2 << 10) // (MC) Code Fetch
+#define AT91C_MC_MST0         ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
+#define AT91C_MC_MST1         ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
+#define AT91C_MC_SVMST0       ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
+#define AT91C_MC_SVMST1       ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
+// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- 
+#define AT91C_MC_FRDY         ((unsigned int) 0x1 <<  0) // (MC) Flash Ready
+#define AT91C_MC_LOCKE        ((unsigned int) 0x1 <<  2) // (MC) Lock Error
+#define AT91C_MC_PROGE        ((unsigned int) 0x1 <<  3) // (MC) Programming Error
+#define AT91C_MC_NEBP         ((unsigned int) 0x1 <<  7) // (MC) No Erase Before Programming
+#define AT91C_MC_FWS          ((unsigned int) 0x3 <<  8) // (MC) Flash Wait State
+#define 	AT91C_MC_FWS_0FWS                 ((unsigned int) 0x0 <<  8) // (MC) 1 cycle for Read, 2 for Write operations
+#define 	AT91C_MC_FWS_1FWS                 ((unsigned int) 0x1 <<  8) // (MC) 2 cycles for Read, 3 for Write operations
+#define 	AT91C_MC_FWS_2FWS                 ((unsigned int) 0x2 <<  8) // (MC) 3 cycles for Read, 4 for Write operations
+#define 	AT91C_MC_FWS_3FWS                 ((unsigned int) 0x3 <<  8) // (MC) 4 cycles for Read, 4 for Write operations
+#define AT91C_MC_FMCN         ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number
+// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- 
+#define AT91C_MC_FCMD         ((unsigned int) 0xF <<  0) // (MC) Flash Command
+#define 	AT91C_MC_FCMD_START_PROG           ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.
+#define 	AT91C_MC_FCMD_LOCK                 ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define 	AT91C_MC_FCMD_PROG_AND_LOCK        ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
+#define 	AT91C_MC_FCMD_UNLOCK               ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define 	AT91C_MC_FCMD_ERASE_ALL            ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
+#define 	AT91C_MC_FCMD_SET_GP_NVM           ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.
+#define 	AT91C_MC_FCMD_CLR_GP_NVM           ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.
+#define 	AT91C_MC_FCMD_SET_SECURITY         ((unsigned int) 0xF) // (MC) Set Security Bit.
+#define AT91C_MC_PAGEN        ((unsigned int) 0x3FF <<  8) // (MC) Page Number
+#define AT91C_MC_KEY          ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key
+// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- 
+#define AT91C_MC_SECURITY     ((unsigned int) 0x1 <<  4) // (MC) Security Bit Status
+#define AT91C_MC_GPNVM0       ((unsigned int) 0x1 <<  8) // (MC) Sector 0 Lock Status
+#define AT91C_MC_GPNVM1       ((unsigned int) 0x1 <<  9) // (MC) Sector 1 Lock Status
+#define AT91C_MC_GPNVM2       ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status
+#define AT91C_MC_GPNVM3       ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status
+#define AT91C_MC_GPNVM4       ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status
+#define AT91C_MC_GPNVM5       ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status
+#define AT91C_MC_GPNVM6       ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status
+#define AT91C_MC_GPNVM7       ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS0       ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status
+#define AT91C_MC_LOCKS1       ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status
+#define AT91C_MC_LOCKS2       ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status
+#define AT91C_MC_LOCKS3       ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status
+#define AT91C_MC_LOCKS4       ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status
+#define AT91C_MC_LOCKS5       ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status
+#define AT91C_MC_LOCKS6       ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status
+#define AT91C_MC_LOCKS7       ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS8       ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status
+#define AT91C_MC_LOCKS9       ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status
+#define AT91C_MC_LOCKS10      ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status
+#define AT91C_MC_LOCKS11      ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status
+#define AT91C_MC_LOCKS12      ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status
+#define AT91C_MC_LOCKS13      ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status
+#define AT91C_MC_LOCKS14      ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status
+#define AT91C_MC_LOCKS15      ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
+// *****************************************************************************
+typedef struct _AT91S_SPI {
+	AT91_REG	 SPI_CR; 	// Control Register
+	AT91_REG	 SPI_MR; 	// Mode Register
+	AT91_REG	 SPI_RDR; 	// Receive Data Register
+	AT91_REG	 SPI_TDR; 	// Transmit Data Register
+	AT91_REG	 SPI_SR; 	// Status Register
+	AT91_REG	 SPI_IER; 	// Interrupt Enable Register
+	AT91_REG	 SPI_IDR; 	// Interrupt Disable Register
+	AT91_REG	 SPI_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved0[4]; 	// 
+	AT91_REG	 SPI_CSR[4]; 	// Chip Select Register
+	AT91_REG	 Reserved1[48]; 	// 
+	AT91_REG	 SPI_RPR; 	// Receive Pointer Register
+	AT91_REG	 SPI_RCR; 	// Receive Counter Register
+	AT91_REG	 SPI_TPR; 	// Transmit Pointer Register
+	AT91_REG	 SPI_TCR; 	// Transmit Counter Register
+	AT91_REG	 SPI_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 SPI_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 SPI_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 SPI_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 SPI_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 SPI_PTSR; 	// PDC Transfer Status Register
+} AT91S_SPI, *AT91PS_SPI;
+
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
+#define AT91C_SPI_SPIEN       ((unsigned int) 0x1 <<  0) // (SPI) SPI Enable
+#define AT91C_SPI_SPIDIS      ((unsigned int) 0x1 <<  1) // (SPI) SPI Disable
+#define AT91C_SPI_SWRST       ((unsigned int) 0x1 <<  7) // (SPI) SPI Software reset
+#define AT91C_SPI_LASTXFER    ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
+#define AT91C_SPI_MSTR        ((unsigned int) 0x1 <<  0) // (SPI) Master/Slave Mode
+#define AT91C_SPI_PS          ((unsigned int) 0x1 <<  1) // (SPI) Peripheral Select
+#define 	AT91C_SPI_PS_FIXED                ((unsigned int) 0x0 <<  1) // (SPI) Fixed Peripheral Select
+#define 	AT91C_SPI_PS_VARIABLE             ((unsigned int) 0x1 <<  1) // (SPI) Variable Peripheral Select
+#define AT91C_SPI_PCSDEC      ((unsigned int) 0x1 <<  2) // (SPI) Chip Select Decode
+#define AT91C_SPI_FDIV        ((unsigned int) 0x1 <<  3) // (SPI) Clock Selection
+#define AT91C_SPI_MODFDIS     ((unsigned int) 0x1 <<  4) // (SPI) Mode Fault Detection
+#define AT91C_SPI_LLB         ((unsigned int) 0x1 <<  7) // (SPI) Clock Selection
+#define AT91C_SPI_PCS         ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
+#define AT91C_SPI_DLYBCS      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
+#define AT91C_SPI_RD          ((unsigned int) 0xFFFF <<  0) // (SPI) Receive Data
+#define AT91C_SPI_RPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
+#define AT91C_SPI_TD          ((unsigned int) 0xFFFF <<  0) // (SPI) Transmit Data
+#define AT91C_SPI_TPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
+#define AT91C_SPI_RDRF        ((unsigned int) 0x1 <<  0) // (SPI) Receive Data Register Full
+#define AT91C_SPI_TDRE        ((unsigned int) 0x1 <<  1) // (SPI) Transmit Data Register Empty
+#define AT91C_SPI_MODF        ((unsigned int) 0x1 <<  2) // (SPI) Mode Fault Error
+#define AT91C_SPI_OVRES       ((unsigned int) 0x1 <<  3) // (SPI) Overrun Error Status
+#define AT91C_SPI_ENDRX       ((unsigned int) 0x1 <<  4) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_ENDTX       ((unsigned int) 0x1 <<  5) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_RXBUFF      ((unsigned int) 0x1 <<  6) // (SPI) RXBUFF Interrupt
+#define AT91C_SPI_TXBUFE      ((unsigned int) 0x1 <<  7) // (SPI) TXBUFE Interrupt
+#define AT91C_SPI_NSSR        ((unsigned int) 0x1 <<  8) // (SPI) NSSR Interrupt
+#define AT91C_SPI_TXEMPTY     ((unsigned int) 0x1 <<  9) // (SPI) TXEMPTY Interrupt
+#define AT91C_SPI_SPIENS      ((unsigned int) 0x1 << 16) // (SPI) Enable Status
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
+#define AT91C_SPI_CPOL        ((unsigned int) 0x1 <<  0) // (SPI) Clock Polarity
+#define AT91C_SPI_NCPHA       ((unsigned int) 0x1 <<  1) // (SPI) Clock Phase
+#define AT91C_SPI_CSAAT       ((unsigned int) 0x1 <<  3) // (SPI) Chip Select Active After Transfer
+#define AT91C_SPI_BITS        ((unsigned int) 0xF <<  4) // (SPI) Bits Per Transfer
+#define 	AT91C_SPI_BITS_8                    ((unsigned int) 0x0 <<  4) // (SPI) 8 Bits Per transfer
+#define 	AT91C_SPI_BITS_9                    ((unsigned int) 0x1 <<  4) // (SPI) 9 Bits Per transfer
+#define 	AT91C_SPI_BITS_10                   ((unsigned int) 0x2 <<  4) // (SPI) 10 Bits Per transfer
+#define 	AT91C_SPI_BITS_11                   ((unsigned int) 0x3 <<  4) // (SPI) 11 Bits Per transfer
+#define 	AT91C_SPI_BITS_12                   ((unsigned int) 0x4 <<  4) // (SPI) 12 Bits Per transfer
+#define 	AT91C_SPI_BITS_13                   ((unsigned int) 0x5 <<  4) // (SPI) 13 Bits Per transfer
+#define 	AT91C_SPI_BITS_14                   ((unsigned int) 0x6 <<  4) // (SPI) 14 Bits Per transfer
+#define 	AT91C_SPI_BITS_15                   ((unsigned int) 0x7 <<  4) // (SPI) 15 Bits Per transfer
+#define 	AT91C_SPI_BITS_16                   ((unsigned int) 0x8 <<  4) // (SPI) 16 Bits Per transfer
+#define AT91C_SPI_SCBR        ((unsigned int) 0xFF <<  8) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBS       ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK
+#define AT91C_SPI_DLYBCT      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Usart
+// *****************************************************************************
+typedef struct _AT91S_USART {
+	AT91_REG	 US_CR; 	// Control Register
+	AT91_REG	 US_MR; 	// Mode Register
+	AT91_REG	 US_IER; 	// Interrupt Enable Register
+	AT91_REG	 US_IDR; 	// Interrupt Disable Register
+	AT91_REG	 US_IMR; 	// Interrupt Mask Register
+	AT91_REG	 US_CSR; 	// Channel Status Register
+	AT91_REG	 US_RHR; 	// Receiver Holding Register
+	AT91_REG	 US_THR; 	// Transmitter Holding Register
+	AT91_REG	 US_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 US_RTOR; 	// Receiver Time-out Register
+	AT91_REG	 US_TTGR; 	// Transmitter Time-guard Register
+	AT91_REG	 Reserved0[5]; 	// 
+	AT91_REG	 US_FIDI; 	// FI_DI_Ratio Register
+	AT91_REG	 US_NER; 	// Nb Errors Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 US_IF; 	// IRDA_FILTER Register
+	AT91_REG	 Reserved2[44]; 	// 
+	AT91_REG	 US_RPR; 	// Receive Pointer Register
+	AT91_REG	 US_RCR; 	// Receive Counter Register
+	AT91_REG	 US_TPR; 	// Transmit Pointer Register
+	AT91_REG	 US_TCR; 	// Transmit Counter Register
+	AT91_REG	 US_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 US_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 US_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 US_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 US_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 US_PTSR; 	// PDC Transfer Status Register
+} AT91S_USART, *AT91PS_USART;
+
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
+#define AT91C_US_STTBRK       ((unsigned int) 0x1 <<  9) // (USART) Start Break
+#define AT91C_US_STPBRK       ((unsigned int) 0x1 << 10) // (USART) Stop Break
+#define AT91C_US_STTTO        ((unsigned int) 0x1 << 11) // (USART) Start Time-out
+#define AT91C_US_SENDA        ((unsigned int) 0x1 << 12) // (USART) Send Address
+#define AT91C_US_RSTIT        ((unsigned int) 0x1 << 13) // (USART) Reset Iterations
+#define AT91C_US_RSTNACK      ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge
+#define AT91C_US_RETTO        ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out
+#define AT91C_US_DTREN        ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable
+#define AT91C_US_DTRDIS       ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable
+#define AT91C_US_RTSEN        ((unsigned int) 0x1 << 18) // (USART) Request to Send enable
+#define AT91C_US_RTSDIS       ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
+#define AT91C_US_USMODE       ((unsigned int) 0xF <<  0) // (USART) Usart mode
+#define 	AT91C_US_USMODE_NORMAL               ((unsigned int) 0x0) // (USART) Normal
+#define 	AT91C_US_USMODE_RS485                ((unsigned int) 0x1) // (USART) RS485
+#define 	AT91C_US_USMODE_HWHSH                ((unsigned int) 0x2) // (USART) Hardware Handshaking
+#define 	AT91C_US_USMODE_MODEM                ((unsigned int) 0x3) // (USART) Modem
+#define 	AT91C_US_USMODE_ISO7816_0            ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0
+#define 	AT91C_US_USMODE_ISO7816_1            ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1
+#define 	AT91C_US_USMODE_IRDA                 ((unsigned int) 0x8) // (USART) IrDA
+#define 	AT91C_US_USMODE_SWHSH                ((unsigned int) 0xC) // (USART) Software Handshaking
+#define AT91C_US_CLKS         ((unsigned int) 0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CLKS_CLOCK                ((unsigned int) 0x0 <<  4) // (USART) Clock
+#define 	AT91C_US_CLKS_FDIV1                ((unsigned int) 0x1 <<  4) // (USART) fdiv1
+#define 	AT91C_US_CLKS_SLOW                 ((unsigned int) 0x2 <<  4) // (USART) slow_clock (ARM)
+#define 	AT91C_US_CLKS_EXT                  ((unsigned int) 0x3 <<  4) // (USART) External (SCK)
+#define AT91C_US_CHRL         ((unsigned int) 0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CHRL_5_BITS               ((unsigned int) 0x0 <<  6) // (USART) Character Length: 5 bits
+#define 	AT91C_US_CHRL_6_BITS               ((unsigned int) 0x1 <<  6) // (USART) Character Length: 6 bits
+#define 	AT91C_US_CHRL_7_BITS               ((unsigned int) 0x2 <<  6) // (USART) Character Length: 7 bits
+#define 	AT91C_US_CHRL_8_BITS               ((unsigned int) 0x3 <<  6) // (USART) Character Length: 8 bits
+#define AT91C_US_SYNC         ((unsigned int) 0x1 <<  8) // (USART) Synchronous Mode Select
+#define AT91C_US_NBSTOP       ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
+#define 	AT91C_US_NBSTOP_1_BIT                ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
+#define 	AT91C_US_NBSTOP_15_BIT               ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+#define 	AT91C_US_NBSTOP_2_BIT                ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
+#define AT91C_US_MSBF         ((unsigned int) 0x1 << 16) // (USART) Bit Order
+#define AT91C_US_MODE9        ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
+#define AT91C_US_CKLO         ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
+#define AT91C_US_OVER         ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode
+#define AT91C_US_INACK        ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge
+#define AT91C_US_DSNACK       ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK
+#define AT91C_US_MAX_ITER     ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions
+#define AT91C_US_FILTER       ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+#define AT91C_US_RXBRK        ((unsigned int) 0x1 <<  2) // (USART) Break Received/End of Break
+#define AT91C_US_TIMEOUT      ((unsigned int) 0x1 <<  8) // (USART) Receiver Time-out
+#define AT91C_US_ITERATION    ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached
+#define AT91C_US_NACK         ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge
+#define AT91C_US_RIIC         ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag
+#define AT91C_US_DSRIC        ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag
+#define AT91C_US_DCDIC        ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag
+#define AT91C_US_CTSIC        ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 
+#define AT91C_US_RI           ((unsigned int) 0x1 << 20) // (USART) Image of RI Input
+#define AT91C_US_DSR          ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input
+#define AT91C_US_DCD          ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input
+#define AT91C_US_CTS          ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_SSC {
+	AT91_REG	 SSC_CR; 	// Control Register
+	AT91_REG	 SSC_CMR; 	// Clock Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 SSC_RCMR; 	// Receive Clock ModeRegister
+	AT91_REG	 SSC_RFMR; 	// Receive Frame Mode Register
+	AT91_REG	 SSC_TCMR; 	// Transmit Clock Mode Register
+	AT91_REG	 SSC_TFMR; 	// Transmit Frame Mode Register
+	AT91_REG	 SSC_RHR; 	// Receive Holding Register
+	AT91_REG	 SSC_THR; 	// Transmit Holding Register
+	AT91_REG	 Reserved1[2]; 	// 
+	AT91_REG	 SSC_RSHR; 	// Receive Sync Holding Register
+	AT91_REG	 SSC_TSHR; 	// Transmit Sync Holding Register
+	AT91_REG	 Reserved2[2]; 	// 
+	AT91_REG	 SSC_SR; 	// Status Register
+	AT91_REG	 SSC_IER; 	// Interrupt Enable Register
+	AT91_REG	 SSC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 SSC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved3[44]; 	// 
+	AT91_REG	 SSC_RPR; 	// Receive Pointer Register
+	AT91_REG	 SSC_RCR; 	// Receive Counter Register
+	AT91_REG	 SSC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 SSC_TCR; 	// Transmit Counter Register
+	AT91_REG	 SSC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 SSC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 SSC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 SSC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 SSC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 SSC_PTSR; 	// PDC Transfer Status Register
+} AT91S_SSC, *AT91PS_SSC;
+
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
+#define AT91C_SSC_RXEN        ((unsigned int) 0x1 <<  0) // (SSC) Receive Enable
+#define AT91C_SSC_RXDIS       ((unsigned int) 0x1 <<  1) // (SSC) Receive Disable
+#define AT91C_SSC_TXEN        ((unsigned int) 0x1 <<  8) // (SSC) Transmit Enable
+#define AT91C_SSC_TXDIS       ((unsigned int) 0x1 <<  9) // (SSC) Transmit Disable
+#define AT91C_SSC_SWRST       ((unsigned int) 0x1 << 15) // (SSC) Software Reset
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
+#define AT91C_SSC_CKS         ((unsigned int) 0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
+#define 	AT91C_SSC_CKS_DIV                  ((unsigned int) 0x0) // (SSC) Divided Clock
+#define 	AT91C_SSC_CKS_TK                   ((unsigned int) 0x1) // (SSC) TK Clock signal
+#define 	AT91C_SSC_CKS_RK                   ((unsigned int) 0x2) // (SSC) RK pin
+#define AT91C_SSC_CKO         ((unsigned int) 0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
+#define 	AT91C_SSC_CKO_NONE                 ((unsigned int) 0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+#define 	AT91C_SSC_CKO_CONTINOUS            ((unsigned int) 0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
+#define 	AT91C_SSC_CKO_DATA_TX              ((unsigned int) 0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+#define AT91C_SSC_CKI         ((unsigned int) 0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
+#define AT91C_SSC_START       ((unsigned int) 0xF <<  8) // (SSC) Receive/Transmit Start Selection
+#define 	AT91C_SSC_START_CONTINOUS            ((unsigned int) 0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+#define 	AT91C_SSC_START_TX                   ((unsigned int) 0x1 <<  8) // (SSC) Transmit/Receive start
+#define 	AT91C_SSC_START_LOW_RF               ((unsigned int) 0x2 <<  8) // (SSC) Detection of a low level on RF input
+#define 	AT91C_SSC_START_HIGH_RF              ((unsigned int) 0x3 <<  8) // (SSC) Detection of a high level on RF input
+#define 	AT91C_SSC_START_FALL_RF              ((unsigned int) 0x4 <<  8) // (SSC) Detection of a falling edge on RF input
+#define 	AT91C_SSC_START_RISE_RF              ((unsigned int) 0x5 <<  8) // (SSC) Detection of a rising edge on RF input
+#define 	AT91C_SSC_START_LEVEL_RF             ((unsigned int) 0x6 <<  8) // (SSC) Detection of any level change on RF input
+#define 	AT91C_SSC_START_EDGE_RF              ((unsigned int) 0x7 <<  8) // (SSC) Detection of any edge on RF input
+#define 	AT91C_SSC_START_0                    ((unsigned int) 0x8 <<  8) // (SSC) Compare 0
+#define AT91C_SSC_STTDLY      ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay
+#define AT91C_SSC_PERIOD      ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
+#define AT91C_SSC_DATLEN      ((unsigned int) 0x1F <<  0) // (SSC) Data Length
+#define AT91C_SSC_LOOP        ((unsigned int) 0x1 <<  5) // (SSC) Loop Mode
+#define AT91C_SSC_MSBF        ((unsigned int) 0x1 <<  7) // (SSC) Most Significant Bit First
+#define AT91C_SSC_DATNB       ((unsigned int) 0xF <<  8) // (SSC) Data Number per Frame
+#define AT91C_SSC_FSLEN       ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
+#define AT91C_SSC_FSOS        ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
+#define 	AT91C_SSC_FSOS_NONE                 ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+#define 	AT91C_SSC_FSOS_NEGATIVE             ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+#define 	AT91C_SSC_FSOS_POSITIVE             ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+#define 	AT91C_SSC_FSOS_LOW                  ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+#define 	AT91C_SSC_FSOS_HIGH                 ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+#define 	AT91C_SSC_FSOS_TOGGLE               ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+#define AT91C_SSC_FSEDGE      ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
+#define AT91C_SSC_DATDEF      ((unsigned int) 0x1 <<  5) // (SSC) Data Default Value
+#define AT91C_SSC_FSDEN       ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
+#define AT91C_SSC_TXRDY       ((unsigned int) 0x1 <<  0) // (SSC) Transmit Ready
+#define AT91C_SSC_TXEMPTY     ((unsigned int) 0x1 <<  1) // (SSC) Transmit Empty
+#define AT91C_SSC_ENDTX       ((unsigned int) 0x1 <<  2) // (SSC) End Of Transmission
+#define AT91C_SSC_TXBUFE      ((unsigned int) 0x1 <<  3) // (SSC) Transmit Buffer Empty
+#define AT91C_SSC_RXRDY       ((unsigned int) 0x1 <<  4) // (SSC) Receive Ready
+#define AT91C_SSC_OVRUN       ((unsigned int) 0x1 <<  5) // (SSC) Receive Overrun
+#define AT91C_SSC_ENDRX       ((unsigned int) 0x1 <<  6) // (SSC) End of Reception
+#define AT91C_SSC_RXBUFF      ((unsigned int) 0x1 <<  7) // (SSC) Receive Buffer Full
+#define AT91C_SSC_TXSYN       ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync
+#define AT91C_SSC_RXSYN       ((unsigned int) 0x1 << 11) // (SSC) Receive Sync
+#define AT91C_SSC_TXENA       ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable
+#define AT91C_SSC_RXENA       ((unsigned int) 0x1 << 17) // (SSC) Receive Enable
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Two-wire Interface
+// *****************************************************************************
+typedef struct _AT91S_TWI {
+	AT91_REG	 TWI_CR; 	// Control Register
+	AT91_REG	 TWI_MMR; 	// Master Mode Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 TWI_IADR; 	// Internal Address Register
+	AT91_REG	 TWI_CWGR; 	// Clock Waveform Generator Register
+	AT91_REG	 Reserved1[3]; 	// 
+	AT91_REG	 TWI_SR; 	// Status Register
+	AT91_REG	 TWI_IER; 	// Interrupt Enable Register
+	AT91_REG	 TWI_IDR; 	// Interrupt Disable Register
+	AT91_REG	 TWI_IMR; 	// Interrupt Mask Register
+	AT91_REG	 TWI_RHR; 	// Receive Holding Register
+	AT91_REG	 TWI_THR; 	// Transmit Holding Register
+} AT91S_TWI, *AT91PS_TWI;
+
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
+#define AT91C_TWI_START       ((unsigned int) 0x1 <<  0) // (TWI) Send a START Condition
+#define AT91C_TWI_STOP        ((unsigned int) 0x1 <<  1) // (TWI) Send a STOP Condition
+#define AT91C_TWI_MSEN        ((unsigned int) 0x1 <<  2) // (TWI) TWI Master Transfer Enabled
+#define AT91C_TWI_MSDIS       ((unsigned int) 0x1 <<  3) // (TWI) TWI Master Transfer Disabled
+#define AT91C_TWI_SWRST       ((unsigned int) 0x1 <<  7) // (TWI) Software Reset
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
+#define AT91C_TWI_IADRSZ      ((unsigned int) 0x3 <<  8) // (TWI) Internal Device Address Size
+#define 	AT91C_TWI_IADRSZ_NO                   ((unsigned int) 0x0 <<  8) // (TWI) No internal device address
+#define 	AT91C_TWI_IADRSZ_1_BYTE               ((unsigned int) 0x1 <<  8) // (TWI) One-byte internal device address
+#define 	AT91C_TWI_IADRSZ_2_BYTE               ((unsigned int) 0x2 <<  8) // (TWI) Two-byte internal device address
+#define 	AT91C_TWI_IADRSZ_3_BYTE               ((unsigned int) 0x3 <<  8) // (TWI) Three-byte internal device address
+#define AT91C_TWI_MREAD       ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction
+#define AT91C_TWI_DADR        ((unsigned int) 0x7F << 16) // (TWI) Device Address
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
+#define AT91C_TWI_CLDIV       ((unsigned int) 0xFF <<  0) // (TWI) Clock Low Divider
+#define AT91C_TWI_CHDIV       ((unsigned int) 0xFF <<  8) // (TWI) Clock High Divider
+#define AT91C_TWI_CKDIV       ((unsigned int) 0x7 << 16) // (TWI) Clock Divider
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
+#define AT91C_TWI_TXCOMP      ((unsigned int) 0x1 <<  0) // (TWI) Transmission Completed
+#define AT91C_TWI_RXRDY       ((unsigned int) 0x1 <<  1) // (TWI) Receive holding register ReaDY
+#define AT91C_TWI_TXRDY       ((unsigned int) 0x1 <<  2) // (TWI) Transmit holding register ReaDY
+#define AT91C_TWI_OVRE        ((unsigned int) 0x1 <<  6) // (TWI) Overrun Error
+#define AT91C_TWI_UNRE        ((unsigned int) 0x1 <<  7) // (TWI) Underrun Error
+#define AT91C_TWI_NACK        ((unsigned int) 0x1 <<  8) // (TWI) Not Acknowledged
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
+// *****************************************************************************
+typedef struct _AT91S_PWMC_CH {
+	AT91_REG	 PWMC_CMR; 	// Channel Mode Register
+	AT91_REG	 PWMC_CDTYR; 	// Channel Duty Cycle Register
+	AT91_REG	 PWMC_CPRDR; 	// Channel Period Register
+	AT91_REG	 PWMC_CCNTR; 	// Channel Counter Register
+	AT91_REG	 PWMC_CUPDR; 	// Channel Update Register
+	AT91_REG	 PWMC_Reserved[3]; 	// Reserved
+} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
+
+// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- 
+#define AT91C_PWMC_CPRE       ((unsigned int) 0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
+#define 	AT91C_PWMC_CPRE_MCK                  ((unsigned int) 0x0) // (PWMC_CH) 
+#define 	AT91C_PWMC_CPRE_MCKA                 ((unsigned int) 0xB) // (PWMC_CH) 
+#define 	AT91C_PWMC_CPRE_MCKB                 ((unsigned int) 0xC) // (PWMC_CH) 
+#define AT91C_PWMC_CALG       ((unsigned int) 0x1 <<  8) // (PWMC_CH) Channel Alignment
+#define AT91C_PWMC_CPOL       ((unsigned int) 0x1 <<  9) // (PWMC_CH) Channel Polarity
+#define AT91C_PWMC_CPD        ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period
+// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- 
+#define AT91C_PWMC_CDTY       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Duty Cycle
+// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- 
+#define AT91C_PWMC_CPRD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Period
+// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- 
+#define AT91C_PWMC_CCNT       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Counter
+// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- 
+#define AT91C_PWMC_CUPD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Update
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_PWMC {
+	AT91_REG	 PWMC_MR; 	// PWMC Mode Register
+	AT91_REG	 PWMC_ENA; 	// PWMC Enable Register
+	AT91_REG	 PWMC_DIS; 	// PWMC Disable Register
+	AT91_REG	 PWMC_SR; 	// PWMC Status Register
+	AT91_REG	 PWMC_IER; 	// PWMC Interrupt Enable Register
+	AT91_REG	 PWMC_IDR; 	// PWMC Interrupt Disable Register
+	AT91_REG	 PWMC_IMR; 	// PWMC Interrupt Mask Register
+	AT91_REG	 PWMC_ISR; 	// PWMC Interrupt Status Register
+	AT91_REG	 Reserved0[55]; 	// 
+	AT91_REG	 PWMC_VR; 	// PWMC Version Register
+	AT91_REG	 Reserved1[64]; 	// 
+	AT91S_PWMC_CH	 PWMC_CH[4]; 	// PWMC Channel
+} AT91S_PWMC, *AT91PS_PWMC;
+
+// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- 
+#define AT91C_PWMC_DIVA       ((unsigned int) 0xFF <<  0) // (PWMC) CLKA divide factor.
+#define AT91C_PWMC_PREA       ((unsigned int) 0xF <<  8) // (PWMC) Divider Input Clock Prescaler A
+#define 	AT91C_PWMC_PREA_MCK                  ((unsigned int) 0x0 <<  8) // (PWMC) 
+#define AT91C_PWMC_DIVB       ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.
+#define AT91C_PWMC_PREB       ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B
+#define 	AT91C_PWMC_PREB_MCK                  ((unsigned int) 0x0 << 24) // (PWMC) 
+// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- 
+#define AT91C_PWMC_CHID0      ((unsigned int) 0x1 <<  0) // (PWMC) Channel ID 0
+#define AT91C_PWMC_CHID1      ((unsigned int) 0x1 <<  1) // (PWMC) Channel ID 1
+#define AT91C_PWMC_CHID2      ((unsigned int) 0x1 <<  2) // (PWMC) Channel ID 2
+#define AT91C_PWMC_CHID3      ((unsigned int) 0x1 <<  3) // (PWMC) Channel ID 3
+// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- 
+// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- 
+// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- 
+// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- 
+// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- 
+// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR USB Device Interface
+// *****************************************************************************
+typedef struct _AT91S_UDP {
+	AT91_REG	 UDP_NUM; 	// Frame Number Register
+	AT91_REG	 UDP_GLBSTATE; 	// Global State Register
+	AT91_REG	 UDP_FADDR; 	// Function Address Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 UDP_IER; 	// Interrupt Enable Register
+	AT91_REG	 UDP_IDR; 	// Interrupt Disable Register
+	AT91_REG	 UDP_IMR; 	// Interrupt Mask Register
+	AT91_REG	 UDP_ISR; 	// Interrupt Status Register
+	AT91_REG	 UDP_ICR; 	// Interrupt Clear Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 UDP_RSTEP; 	// Reset Endpoint Register
+	AT91_REG	 Reserved2[1]; 	// 
+	AT91_REG	 UDP_CSR[6]; 	// Endpoint Control and Status Register
+	AT91_REG	 Reserved3[2]; 	// 
+	AT91_REG	 UDP_FDR[6]; 	// Endpoint FIFO Data Register
+	AT91_REG	 Reserved4[3]; 	// 
+	AT91_REG	 UDP_TXVC; 	// Transceiver Control Register
+} AT91S_UDP, *AT91PS_UDP;
+
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
+#define AT91C_UDP_FRM_NUM     ((unsigned int) 0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
+#define AT91C_UDP_FRM_ERR     ((unsigned int) 0x1 << 16) // (UDP) Frame Error
+#define AT91C_UDP_FRM_OK      ((unsigned int) 0x1 << 17) // (UDP) Frame OK
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
+#define AT91C_UDP_FADDEN      ((unsigned int) 0x1 <<  0) // (UDP) Function Address Enable
+#define AT91C_UDP_CONFG       ((unsigned int) 0x1 <<  1) // (UDP) Configured
+#define AT91C_UDP_ESR         ((unsigned int) 0x1 <<  2) // (UDP) Enable Send Resume
+#define AT91C_UDP_RSMINPR     ((unsigned int) 0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
+#define AT91C_UDP_RMWUPE      ((unsigned int) 0x1 <<  4) // (UDP) Remote Wake Up Enable
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
+#define AT91C_UDP_FADD        ((unsigned int) 0xFF <<  0) // (UDP) Function Address Value
+#define AT91C_UDP_FEN         ((unsigned int) 0x1 <<  8) // (UDP) Function Enable
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 
+#define AT91C_UDP_EPINT0      ((unsigned int) 0x1 <<  0) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT1      ((unsigned int) 0x1 <<  1) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT2      ((unsigned int) 0x1 <<  2) // (UDP) Endpoint 2 Interrupt
+#define AT91C_UDP_EPINT3      ((unsigned int) 0x1 <<  3) // (UDP) Endpoint 3 Interrupt
+#define AT91C_UDP_EPINT4      ((unsigned int) 0x1 <<  4) // (UDP) Endpoint 4 Interrupt
+#define AT91C_UDP_EPINT5      ((unsigned int) 0x1 <<  5) // (UDP) Endpoint 5 Interrupt
+#define AT91C_UDP_RXSUSP      ((unsigned int) 0x1 <<  8) // (UDP) USB Suspend Interrupt
+#define AT91C_UDP_RXRSM       ((unsigned int) 0x1 <<  9) // (UDP) USB Resume Interrupt
+#define AT91C_UDP_EXTRSM      ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt
+#define AT91C_UDP_SOFINT      ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt
+#define AT91C_UDP_WAKEUP      ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 
+#define AT91C_UDP_ENDBUSRES   ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 
+#define AT91C_UDP_EP0         ((unsigned int) 0x1 <<  0) // (UDP) Reset Endpoint 0
+#define AT91C_UDP_EP1         ((unsigned int) 0x1 <<  1) // (UDP) Reset Endpoint 1
+#define AT91C_UDP_EP2         ((unsigned int) 0x1 <<  2) // (UDP) Reset Endpoint 2
+#define AT91C_UDP_EP3         ((unsigned int) 0x1 <<  3) // (UDP) Reset Endpoint 3
+#define AT91C_UDP_EP4         ((unsigned int) 0x1 <<  4) // (UDP) Reset Endpoint 4
+#define AT91C_UDP_EP5         ((unsigned int) 0x1 <<  5) // (UDP) Reset Endpoint 5
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 
+#define AT91C_UDP_TXCOMP      ((unsigned int) 0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
+#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 <<  1) // (UDP) Receive Data Bank 0
+#define AT91C_UDP_RXSETUP     ((unsigned int) 0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
+#define AT91C_UDP_ISOERROR    ((unsigned int) 0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
+#define AT91C_UDP_TXPKTRDY    ((unsigned int) 0x1 <<  4) // (UDP) Transmit Packet Ready
+#define AT91C_UDP_FORCESTALL  ((unsigned int) 0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
+#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
+#define AT91C_UDP_DIR         ((unsigned int) 0x1 <<  7) // (UDP) Transfer Direction
+#define AT91C_UDP_EPTYPE      ((unsigned int) 0x7 <<  8) // (UDP) Endpoint type
+#define 	AT91C_UDP_EPTYPE_CTRL                 ((unsigned int) 0x0 <<  8) // (UDP) Control
+#define 	AT91C_UDP_EPTYPE_ISO_OUT              ((unsigned int) 0x1 <<  8) // (UDP) Isochronous OUT
+#define 	AT91C_UDP_EPTYPE_BULK_OUT             ((unsigned int) 0x2 <<  8) // (UDP) Bulk OUT
+#define 	AT91C_UDP_EPTYPE_INT_OUT              ((unsigned int) 0x3 <<  8) // (UDP) Interrupt OUT
+#define 	AT91C_UDP_EPTYPE_ISO_IN               ((unsigned int) 0x5 <<  8) // (UDP) Isochronous IN
+#define 	AT91C_UDP_EPTYPE_BULK_IN              ((unsigned int) 0x6 <<  8) // (UDP) Bulk IN
+#define 	AT91C_UDP_EPTYPE_INT_IN               ((unsigned int) 0x7 <<  8) // (UDP) Interrupt IN
+#define AT91C_UDP_DTGLE       ((unsigned int) 0x1 << 11) // (UDP) Data Toggle
+#define AT91C_UDP_EPEDS       ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable
+#define AT91C_UDP_RXBYTECNT   ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
+// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- 
+#define AT91C_UDP_TXVDIS      ((unsigned int) 0x1 <<  8) // (UDP) 
+#define AT91C_UDP_PUON        ((unsigned int) 0x1 <<  9) // (UDP) Pull-up ON
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
+// *****************************************************************************
+typedef struct _AT91S_TC {
+	AT91_REG	 TC_CCR; 	// Channel Control Register
+	AT91_REG	 TC_CMR; 	// Channel Mode Register (Capture Mode / Waveform Mode)
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 TC_CV; 	// Counter Value
+	AT91_REG	 TC_RA; 	// Register A
+	AT91_REG	 TC_RB; 	// Register B
+	AT91_REG	 TC_RC; 	// Register C
+	AT91_REG	 TC_SR; 	// Status Register
+	AT91_REG	 TC_IER; 	// Interrupt Enable Register
+	AT91_REG	 TC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 TC_IMR; 	// Interrupt Mask Register
+} AT91S_TC, *AT91PS_TC;
+
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
+#define AT91C_TC_CLKEN        ((unsigned int) 0x1 <<  0) // (TC) Counter Clock Enable Command
+#define AT91C_TC_CLKDIS       ((unsigned int) 0x1 <<  1) // (TC) Counter Clock Disable Command
+#define AT91C_TC_SWTRG        ((unsigned int) 0x1 <<  2) // (TC) Software Trigger Command
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
+#define AT91C_TC_CLKS         ((unsigned int) 0x7 <<  0) // (TC) Clock Selection
+#define 	AT91C_TC_CLKS_TIMER_DIV1_CLOCK     ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV2_CLOCK     ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV3_CLOCK     ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV4_CLOCK     ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV5_CLOCK     ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
+#define 	AT91C_TC_CLKS_XC0                  ((unsigned int) 0x5) // (TC) Clock selected: XC0
+#define 	AT91C_TC_CLKS_XC1                  ((unsigned int) 0x6) // (TC) Clock selected: XC1
+#define 	AT91C_TC_CLKS_XC2                  ((unsigned int) 0x7) // (TC) Clock selected: XC2
+#define AT91C_TC_CLKI         ((unsigned int) 0x1 <<  3) // (TC) Clock Invert
+#define AT91C_TC_BURST        ((unsigned int) 0x3 <<  4) // (TC) Burst Signal Selection
+#define 	AT91C_TC_BURST_NONE                 ((unsigned int) 0x0 <<  4) // (TC) The clock is not gated by an external signal
+#define 	AT91C_TC_BURST_XC0                  ((unsigned int) 0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
+#define 	AT91C_TC_BURST_XC1                  ((unsigned int) 0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
+#define 	AT91C_TC_BURST_XC2                  ((unsigned int) 0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
+#define AT91C_TC_CPCSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
+#define AT91C_TC_LDBSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
+#define AT91C_TC_CPCDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
+#define AT91C_TC_LDBDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
+#define AT91C_TC_ETRGEDG      ((unsigned int) 0x3 <<  8) // (TC) External Trigger Edge Selection
+#define 	AT91C_TC_ETRGEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_ETRGEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_ETRGEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_ETRGEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_EEVTEDG      ((unsigned int) 0x3 <<  8) // (TC) External Event Edge Selection
+#define 	AT91C_TC_EEVTEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_EEVTEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_EEVTEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_EEVTEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_EEVT         ((unsigned int) 0x3 << 10) // (TC) External Event  Selection
+#define 	AT91C_TC_EEVT_TIOB                 ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
+#define 	AT91C_TC_EEVT_XC0                  ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
+#define 	AT91C_TC_EEVT_XC1                  ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
+#define 	AT91C_TC_EEVT_XC2                  ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
+#define AT91C_TC_ABETRG       ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
+#define AT91C_TC_ENETRG       ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
+#define AT91C_TC_WAVESEL      ((unsigned int) 0x3 << 13) // (TC) Waveform  Selection
+#define 	AT91C_TC_WAVESEL_UP                   ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN               ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UP_AUTO              ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN_AUTO          ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
+#define AT91C_TC_CPCTRG       ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
+#define AT91C_TC_WAVE         ((unsigned int) 0x1 << 15) // (TC) 
+#define AT91C_TC_ACPA         ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
+#define 	AT91C_TC_ACPA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Effect: none
+#define 	AT91C_TC_ACPA_SET                  ((unsigned int) 0x1 << 16) // (TC) Effect: set
+#define 	AT91C_TC_ACPA_CLEAR                ((unsigned int) 0x2 << 16) // (TC) Effect: clear
+#define 	AT91C_TC_ACPA_TOGGLE               ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
+#define AT91C_TC_LDRA         ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection
+#define 	AT91C_TC_LDRA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Edge: None
+#define 	AT91C_TC_LDRA_RISING               ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA
+#define 	AT91C_TC_LDRA_FALLING              ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA
+#define 	AT91C_TC_LDRA_BOTH                 ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_ACPC         ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
+#define 	AT91C_TC_ACPC_NONE                 ((unsigned int) 0x0 << 18) // (TC) Effect: none
+#define 	AT91C_TC_ACPC_SET                  ((unsigned int) 0x1 << 18) // (TC) Effect: set
+#define 	AT91C_TC_ACPC_CLEAR                ((unsigned int) 0x2 << 18) // (TC) Effect: clear
+#define 	AT91C_TC_ACPC_TOGGLE               ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
+#define AT91C_TC_LDRB         ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection
+#define 	AT91C_TC_LDRB_NONE                 ((unsigned int) 0x0 << 18) // (TC) Edge: None
+#define 	AT91C_TC_LDRB_RISING               ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA
+#define 	AT91C_TC_LDRB_FALLING              ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA
+#define 	AT91C_TC_LDRB_BOTH                 ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_AEEVT        ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
+#define 	AT91C_TC_AEEVT_NONE                 ((unsigned int) 0x0 << 20) // (TC) Effect: none
+#define 	AT91C_TC_AEEVT_SET                  ((unsigned int) 0x1 << 20) // (TC) Effect: set
+#define 	AT91C_TC_AEEVT_CLEAR                ((unsigned int) 0x2 << 20) // (TC) Effect: clear
+#define 	AT91C_TC_AEEVT_TOGGLE               ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
+#define AT91C_TC_ASWTRG       ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
+#define 	AT91C_TC_ASWTRG_NONE                 ((unsigned int) 0x0 << 22) // (TC) Effect: none
+#define 	AT91C_TC_ASWTRG_SET                  ((unsigned int) 0x1 << 22) // (TC) Effect: set
+#define 	AT91C_TC_ASWTRG_CLEAR                ((unsigned int) 0x2 << 22) // (TC) Effect: clear
+#define 	AT91C_TC_ASWTRG_TOGGLE               ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
+#define AT91C_TC_BCPB         ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
+#define 	AT91C_TC_BCPB_NONE                 ((unsigned int) 0x0 << 24) // (TC) Effect: none
+#define 	AT91C_TC_BCPB_SET                  ((unsigned int) 0x1 << 24) // (TC) Effect: set
+#define 	AT91C_TC_BCPB_CLEAR                ((unsigned int) 0x2 << 24) // (TC) Effect: clear
+#define 	AT91C_TC_BCPB_TOGGLE               ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
+#define AT91C_TC_BCPC         ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
+#define 	AT91C_TC_BCPC_NONE                 ((unsigned int) 0x0 << 26) // (TC) Effect: none
+#define 	AT91C_TC_BCPC_SET                  ((unsigned int) 0x1 << 26) // (TC) Effect: set
+#define 	AT91C_TC_BCPC_CLEAR                ((unsigned int) 0x2 << 26) // (TC) Effect: clear
+#define 	AT91C_TC_BCPC_TOGGLE               ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
+#define AT91C_TC_BEEVT        ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
+#define 	AT91C_TC_BEEVT_NONE                 ((unsigned int) 0x0 << 28) // (TC) Effect: none
+#define 	AT91C_TC_BEEVT_SET                  ((unsigned int) 0x1 << 28) // (TC) Effect: set
+#define 	AT91C_TC_BEEVT_CLEAR                ((unsigned int) 0x2 << 28) // (TC) Effect: clear
+#define 	AT91C_TC_BEEVT_TOGGLE               ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
+#define AT91C_TC_BSWTRG       ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
+#define 	AT91C_TC_BSWTRG_NONE                 ((unsigned int) 0x0 << 30) // (TC) Effect: none
+#define 	AT91C_TC_BSWTRG_SET                  ((unsigned int) 0x1 << 30) // (TC) Effect: set
+#define 	AT91C_TC_BSWTRG_CLEAR                ((unsigned int) 0x2 << 30) // (TC) Effect: clear
+#define 	AT91C_TC_BSWTRG_TOGGLE               ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
+#define AT91C_TC_COVFS        ((unsigned int) 0x1 <<  0) // (TC) Counter Overflow
+#define AT91C_TC_LOVRS        ((unsigned int) 0x1 <<  1) // (TC) Load Overrun
+#define AT91C_TC_CPAS         ((unsigned int) 0x1 <<  2) // (TC) RA Compare
+#define AT91C_TC_CPBS         ((unsigned int) 0x1 <<  3) // (TC) RB Compare
+#define AT91C_TC_CPCS         ((unsigned int) 0x1 <<  4) // (TC) RC Compare
+#define AT91C_TC_LDRAS        ((unsigned int) 0x1 <<  5) // (TC) RA Loading
+#define AT91C_TC_LDRBS        ((unsigned int) 0x1 <<  6) // (TC) RB Loading
+#define AT91C_TC_ETRGS        ((unsigned int) 0x1 <<  7) // (TC) External Trigger
+#define AT91C_TC_CLKSTA       ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
+#define AT91C_TC_MTIOA        ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
+#define AT91C_TC_MTIOB        ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
+// *****************************************************************************
+typedef struct _AT91S_TCB {
+	AT91S_TC	 TCB_TC0; 	// TC Channel 0
+	AT91_REG	 Reserved0[4]; 	// 
+	AT91S_TC	 TCB_TC1; 	// TC Channel 1
+	AT91_REG	 Reserved1[4]; 	// 
+	AT91S_TC	 TCB_TC2; 	// TC Channel 2
+	AT91_REG	 Reserved2[4]; 	// 
+	AT91_REG	 TCB_BCR; 	// TC Block Control Register
+	AT91_REG	 TCB_BMR; 	// TC Block Mode Register
+} AT91S_TCB, *AT91PS_TCB;
+
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
+#define AT91C_TCB_SYNC        ((unsigned int) 0x1 <<  0) // (TCB) Synchro Command
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
+#define AT91C_TCB_TC0XC0S     ((unsigned int) 0x3 <<  0) // (TCB) External Clock Signal 0 Selection
+#define 	AT91C_TCB_TC0XC0S_TCLK0                ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_NONE                 ((unsigned int) 0x1) // (TCB) None signal connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA1                ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA2                ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
+#define AT91C_TCB_TC1XC1S     ((unsigned int) 0x3 <<  2) // (TCB) External Clock Signal 1 Selection
+#define 	AT91C_TCB_TC1XC1S_TCLK1                ((unsigned int) 0x0 <<  2) // (TCB) TCLK1 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_NONE                 ((unsigned int) 0x1 <<  2) // (TCB) None signal connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA0                ((unsigned int) 0x2 <<  2) // (TCB) TIOA0 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA2                ((unsigned int) 0x3 <<  2) // (TCB) TIOA2 connected to XC1
+#define AT91C_TCB_TC2XC2S     ((unsigned int) 0x3 <<  4) // (TCB) External Clock Signal 2 Selection
+#define 	AT91C_TCB_TC2XC2S_TCLK2                ((unsigned int) 0x0 <<  4) // (TCB) TCLK2 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_NONE                 ((unsigned int) 0x1 <<  4) // (TCB) None signal connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA0                ((unsigned int) 0x2 <<  4) // (TCB) TIOA0 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA1                ((unsigned int) 0x3 <<  4) // (TCB) TIOA2 connected to XC2
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface
+// *****************************************************************************
+typedef struct _AT91S_CAN_MB {
+	AT91_REG	 CAN_MB_MMR; 	// MailBox Mode Register
+	AT91_REG	 CAN_MB_MAM; 	// MailBox Acceptance Mask Register
+	AT91_REG	 CAN_MB_MID; 	// MailBox ID Register
+	AT91_REG	 CAN_MB_MFID; 	// MailBox Family ID Register
+	AT91_REG	 CAN_MB_MSR; 	// MailBox Status Register
+	AT91_REG	 CAN_MB_MDL; 	// MailBox Data Low Register
+	AT91_REG	 CAN_MB_MDH; 	// MailBox Data High Register
+	AT91_REG	 CAN_MB_MCR; 	// MailBox Control Register
+} AT91S_CAN_MB, *AT91PS_CAN_MB;
+
+// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- 
+#define AT91C_CAN_MTIMEMARK   ((unsigned int) 0xFFFF <<  0) // (CAN_MB) Mailbox Timemark
+#define AT91C_CAN_PRIOR       ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority
+#define AT91C_CAN_MOT         ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type
+#define 	AT91C_CAN_MOT_DIS                  ((unsigned int) 0x0 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_RX                   ((unsigned int) 0x1 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_RXOVERWRITE          ((unsigned int) 0x2 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_TX                   ((unsigned int) 0x3 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_CONSUMER             ((unsigned int) 0x4 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_PRODUCER             ((unsigned int) 0x5 << 24) // (CAN_MB) 
+// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- 
+#define AT91C_CAN_MIDvB       ((unsigned int) 0x3FFFF <<  0) // (CAN_MB) Complementary bits for identifier in extended mode
+#define AT91C_CAN_MIDvA       ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
+#define AT91C_CAN_MIDE        ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version
+// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- 
+// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- 
+// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- 
+#define AT91C_CAN_MTIMESTAMP  ((unsigned int) 0xFFFF <<  0) // (CAN_MB) Timer Value
+#define AT91C_CAN_MDLC        ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code
+#define AT91C_CAN_MRTR        ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
+#define AT91C_CAN_MABT        ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort
+#define AT91C_CAN_MRDY        ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready
+#define AT91C_CAN_MMI         ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored
+// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- 
+// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- 
+// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- 
+#define AT91C_CAN_MACR        ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox
+#define AT91C_CAN_MTCR        ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Control Area Network Interface
+// *****************************************************************************
+typedef struct _AT91S_CAN {
+	AT91_REG	 CAN_MR; 	// Mode Register
+	AT91_REG	 CAN_IER; 	// Interrupt Enable Register
+	AT91_REG	 CAN_IDR; 	// Interrupt Disable Register
+	AT91_REG	 CAN_IMR; 	// Interrupt Mask Register
+	AT91_REG	 CAN_SR; 	// Status Register
+	AT91_REG	 CAN_BR; 	// Baudrate Register
+	AT91_REG	 CAN_TIM; 	// Timer Register
+	AT91_REG	 CAN_TIMESTP; 	// Time Stamp Register
+	AT91_REG	 CAN_ECR; 	// Error Counter Register
+	AT91_REG	 CAN_TCR; 	// Transfer Command Register
+	AT91_REG	 CAN_ACR; 	// Abort Command Register
+	AT91_REG	 Reserved0[52]; 	// 
+	AT91_REG	 CAN_VR; 	// Version Register
+	AT91_REG	 Reserved1[64]; 	// 
+	AT91S_CAN_MB	 CAN_MB0; 	// CAN Mailbox 0
+	AT91S_CAN_MB	 CAN_MB1; 	// CAN Mailbox 1
+	AT91S_CAN_MB	 CAN_MB2; 	// CAN Mailbox 2
+	AT91S_CAN_MB	 CAN_MB3; 	// CAN Mailbox 3
+	AT91S_CAN_MB	 CAN_MB4; 	// CAN Mailbox 4
+	AT91S_CAN_MB	 CAN_MB5; 	// CAN Mailbox 5
+	AT91S_CAN_MB	 CAN_MB6; 	// CAN Mailbox 6
+	AT91S_CAN_MB	 CAN_MB7; 	// CAN Mailbox 7
+	AT91S_CAN_MB	 CAN_MB8; 	// CAN Mailbox 8
+	AT91S_CAN_MB	 CAN_MB9; 	// CAN Mailbox 9
+	AT91S_CAN_MB	 CAN_MB10; 	// CAN Mailbox 10
+	AT91S_CAN_MB	 CAN_MB11; 	// CAN Mailbox 11
+	AT91S_CAN_MB	 CAN_MB12; 	// CAN Mailbox 12
+	AT91S_CAN_MB	 CAN_MB13; 	// CAN Mailbox 13
+	AT91S_CAN_MB	 CAN_MB14; 	// CAN Mailbox 14
+	AT91S_CAN_MB	 CAN_MB15; 	// CAN Mailbox 15
+} AT91S_CAN, *AT91PS_CAN;
+
+// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- 
+#define AT91C_CAN_CANEN       ((unsigned int) 0x1 <<  0) // (CAN) CAN Controller Enable
+#define AT91C_CAN_LPM         ((unsigned int) 0x1 <<  1) // (CAN) Disable/Enable Low Power Mode
+#define AT91C_CAN_ABM         ((unsigned int) 0x1 <<  2) // (CAN) Disable/Enable Autobaud/Listen Mode
+#define AT91C_CAN_OVL         ((unsigned int) 0x1 <<  3) // (CAN) Disable/Enable Overload Frame
+#define AT91C_CAN_TEOF        ((unsigned int) 0x1 <<  4) // (CAN) Time Stamp messages at each end of Frame
+#define AT91C_CAN_TTM         ((unsigned int) 0x1 <<  5) // (CAN) Disable/Enable Time Trigger Mode
+#define AT91C_CAN_TIMFRZ      ((unsigned int) 0x1 <<  6) // (CAN) Enable Timer Freeze
+#define AT91C_CAN_DRPT        ((unsigned int) 0x1 <<  7) // (CAN) Disable Repeat
+// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- 
+#define AT91C_CAN_MB0         ((unsigned int) 0x1 <<  0) // (CAN) Mailbox 0 Flag
+#define AT91C_CAN_MB1         ((unsigned int) 0x1 <<  1) // (CAN) Mailbox 1 Flag
+#define AT91C_CAN_MB2         ((unsigned int) 0x1 <<  2) // (CAN) Mailbox 2 Flag
+#define AT91C_CAN_MB3         ((unsigned int) 0x1 <<  3) // (CAN) Mailbox 3 Flag
+#define AT91C_CAN_MB4         ((unsigned int) 0x1 <<  4) // (CAN) Mailbox 4 Flag
+#define AT91C_CAN_MB5         ((unsigned int) 0x1 <<  5) // (CAN) Mailbox 5 Flag
+#define AT91C_CAN_MB6         ((unsigned int) 0x1 <<  6) // (CAN) Mailbox 6 Flag
+#define AT91C_CAN_MB7         ((unsigned int) 0x1 <<  7) // (CAN) Mailbox 7 Flag
+#define AT91C_CAN_MB8         ((unsigned int) 0x1 <<  8) // (CAN) Mailbox 8 Flag
+#define AT91C_CAN_MB9         ((unsigned int) 0x1 <<  9) // (CAN) Mailbox 9 Flag
+#define AT91C_CAN_MB10        ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag
+#define AT91C_CAN_MB11        ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag
+#define AT91C_CAN_MB12        ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag
+#define AT91C_CAN_MB13        ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag
+#define AT91C_CAN_MB14        ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag
+#define AT91C_CAN_MB15        ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag
+#define AT91C_CAN_ERRA        ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag
+#define AT91C_CAN_WARN        ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag
+#define AT91C_CAN_ERRP        ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag
+#define AT91C_CAN_BOFF        ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag
+#define AT91C_CAN_SLEEP       ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag
+#define AT91C_CAN_WAKEUP      ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag
+#define AT91C_CAN_TOVF        ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag
+#define AT91C_CAN_TSTP        ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag
+#define AT91C_CAN_CERR        ((unsigned int) 0x1 << 24) // (CAN) CRC Error
+#define AT91C_CAN_SERR        ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error
+#define AT91C_CAN_AERR        ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error
+#define AT91C_CAN_FERR        ((unsigned int) 0x1 << 27) // (CAN) Form Error
+#define AT91C_CAN_BERR        ((unsigned int) 0x1 << 28) // (CAN) Bit Error
+// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- 
+// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- 
+// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- 
+#define AT91C_CAN_RBSY        ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy
+#define AT91C_CAN_TBSY        ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy
+#define AT91C_CAN_OVLY        ((unsigned int) 0x1 << 31) // (CAN) Overload Busy
+// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- 
+#define AT91C_CAN_PHASE2      ((unsigned int) 0x7 <<  0) // (CAN) Phase 2 segment
+#define AT91C_CAN_PHASE1      ((unsigned int) 0x7 <<  4) // (CAN) Phase 1 segment
+#define AT91C_CAN_PROPAG      ((unsigned int) 0x7 <<  8) // (CAN) Programmation time segment
+#define AT91C_CAN_SYNC        ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment
+#define AT91C_CAN_BRP         ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler
+#define AT91C_CAN_SMP         ((unsigned int) 0x1 << 24) // (CAN) Sampling mode
+// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- 
+#define AT91C_CAN_TIMER       ((unsigned int) 0xFFFF <<  0) // (CAN) Timer field
+// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- 
+// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- 
+#define AT91C_CAN_REC         ((unsigned int) 0xFF <<  0) // (CAN) Receive Error Counter
+#define AT91C_CAN_TEC         ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter
+// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- 
+#define AT91C_CAN_TIMRST      ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field
+// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100
+// *****************************************************************************
+typedef struct _AT91S_EMAC {
+	AT91_REG	 EMAC_NCR; 	// Network Control Register
+	AT91_REG	 EMAC_NCFGR; 	// Network Configuration Register
+	AT91_REG	 EMAC_NSR; 	// Network Status Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 EMAC_TSR; 	// Transmit Status Register
+	AT91_REG	 EMAC_RBQP; 	// Receive Buffer Queue Pointer
+	AT91_REG	 EMAC_TBQP; 	// Transmit Buffer Queue Pointer
+	AT91_REG	 EMAC_RSR; 	// Receive Status Register
+	AT91_REG	 EMAC_ISR; 	// Interrupt Status Register
+	AT91_REG	 EMAC_IER; 	// Interrupt Enable Register
+	AT91_REG	 EMAC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 EMAC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 EMAC_MAN; 	// PHY Maintenance Register
+	AT91_REG	 EMAC_PTR; 	// Pause Time Register
+	AT91_REG	 EMAC_PFR; 	// Pause Frames received Register
+	AT91_REG	 EMAC_FTO; 	// Frames Transmitted OK Register
+	AT91_REG	 EMAC_SCF; 	// Single Collision Frame Register
+	AT91_REG	 EMAC_MCF; 	// Multiple Collision Frame Register
+	AT91_REG	 EMAC_FRO; 	// Frames Received OK Register
+	AT91_REG	 EMAC_FCSE; 	// Frame Check Sequence Error Register
+	AT91_REG	 EMAC_ALE; 	// Alignment Error Register
+	AT91_REG	 EMAC_DTF; 	// Deferred Transmission Frame Register
+	AT91_REG	 EMAC_LCOL; 	// Late Collision Register
+	AT91_REG	 EMAC_ECOL; 	// Excessive Collision Register
+	AT91_REG	 EMAC_TUND; 	// Transmit Underrun Error Register
+	AT91_REG	 EMAC_CSE; 	// Carrier Sense Error Register
+	AT91_REG	 EMAC_RRE; 	// Receive Ressource Error Register
+	AT91_REG	 EMAC_ROV; 	// Receive Overrun Errors Register
+	AT91_REG	 EMAC_RSE; 	// Receive Symbol Errors Register
+	AT91_REG	 EMAC_ELE; 	// Excessive Length Errors Register
+	AT91_REG	 EMAC_RJA; 	// Receive Jabbers Register
+	AT91_REG	 EMAC_USF; 	// Undersize Frames Register
+	AT91_REG	 EMAC_STE; 	// SQE Test Error Register
+	AT91_REG	 EMAC_RLE; 	// Receive Length Field Mismatch Register
+	AT91_REG	 EMAC_TPF; 	// Transmitted Pause Frames Register
+	AT91_REG	 EMAC_HRB; 	// Hash Address Bottom[31:0]
+	AT91_REG	 EMAC_HRT; 	// Hash Address Top[63:32]
+	AT91_REG	 EMAC_SA1L; 	// Specific Address 1 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA1H; 	// Specific Address 1 Top, Last 2 bytes
+	AT91_REG	 EMAC_SA2L; 	// Specific Address 2 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA2H; 	// Specific Address 2 Top, Last 2 bytes
+	AT91_REG	 EMAC_SA3L; 	// Specific Address 3 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA3H; 	// Specific Address 3 Top, Last 2 bytes
+	AT91_REG	 EMAC_SA4L; 	// Specific Address 4 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA4H; 	// Specific Address 4 Top, Last 2 bytes
+	AT91_REG	 EMAC_TID; 	// Type ID Checking Register
+	AT91_REG	 EMAC_TPQ; 	// Transmit Pause Quantum Register
+	AT91_REG	 EMAC_USRIO; 	// USER Input/Output Register
+	AT91_REG	 EMAC_WOL; 	// Wake On LAN Register
+	AT91_REG	 Reserved1[13]; 	// 
+	AT91_REG	 EMAC_REV; 	// Revision Register
+} AT91S_EMAC, *AT91PS_EMAC;
+
+// -------- EMAC_NCR : (EMAC Offset: 0x0)  -------- 
+#define AT91C_EMAC_LB         ((unsigned int) 0x1 <<  0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
+#define AT91C_EMAC_LLB        ((unsigned int) 0x1 <<  1) // (EMAC) Loopback local. 
+#define AT91C_EMAC_RE         ((unsigned int) 0x1 <<  2) // (EMAC) Receive enable. 
+#define AT91C_EMAC_TE         ((unsigned int) 0x1 <<  3) // (EMAC) Transmit enable. 
+#define AT91C_EMAC_MPE        ((unsigned int) 0x1 <<  4) // (EMAC) Management port enable. 
+#define AT91C_EMAC_CLRSTAT    ((unsigned int) 0x1 <<  5) // (EMAC) Clear statistics registers. 
+#define AT91C_EMAC_INCSTAT    ((unsigned int) 0x1 <<  6) // (EMAC) Increment statistics registers. 
+#define AT91C_EMAC_WESTAT     ((unsigned int) 0x1 <<  7) // (EMAC) Write enable for statistics registers. 
+#define AT91C_EMAC_BP         ((unsigned int) 0x1 <<  8) // (EMAC) Back pressure. 
+#define AT91C_EMAC_TSTART     ((unsigned int) 0x1 <<  9) // (EMAC) Start Transmission. 
+#define AT91C_EMAC_THALT      ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. 
+#define AT91C_EMAC_TPFR       ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame 
+#define AT91C_EMAC_TZQ        ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame
+// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- 
+#define AT91C_EMAC_SPD        ((unsigned int) 0x1 <<  0) // (EMAC) Speed. 
+#define AT91C_EMAC_FD         ((unsigned int) 0x1 <<  1) // (EMAC) Full duplex. 
+#define AT91C_EMAC_JFRAME     ((unsigned int) 0x1 <<  3) // (EMAC) Jumbo Frames. 
+#define AT91C_EMAC_CAF        ((unsigned int) 0x1 <<  4) // (EMAC) Copy all frames. 
+#define AT91C_EMAC_NBC        ((unsigned int) 0x1 <<  5) // (EMAC) No broadcast. 
+#define AT91C_EMAC_MTI        ((unsigned int) 0x1 <<  6) // (EMAC) Multicast hash event enable
+#define AT91C_EMAC_UNI        ((unsigned int) 0x1 <<  7) // (EMAC) Unicast hash enable. 
+#define AT91C_EMAC_BIG        ((unsigned int) 0x1 <<  8) // (EMAC) Receive 1522 bytes. 
+#define AT91C_EMAC_EAE        ((unsigned int) 0x1 <<  9) // (EMAC) External address match enable. 
+#define AT91C_EMAC_CLK        ((unsigned int) 0x3 << 10) // (EMAC) 
+#define 	AT91C_EMAC_CLK_HCLK_8               ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8
+#define 	AT91C_EMAC_CLK_HCLK_16              ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16
+#define 	AT91C_EMAC_CLK_HCLK_32              ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32
+#define 	AT91C_EMAC_CLK_HCLK_64              ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64
+#define AT91C_EMAC_RTY        ((unsigned int) 0x1 << 12) // (EMAC) 
+#define AT91C_EMAC_PAE        ((unsigned int) 0x1 << 13) // (EMAC) 
+#define AT91C_EMAC_RBOF       ((unsigned int) 0x3 << 14) // (EMAC) 
+#define 	AT91C_EMAC_RBOF_OFFSET_0             ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_1             ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_2             ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_3             ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
+#define AT91C_EMAC_RLCE       ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable
+#define AT91C_EMAC_DRFCS      ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS
+#define AT91C_EMAC_EFRHD      ((unsigned int) 0x1 << 18) // (EMAC) 
+#define AT91C_EMAC_IRXFCS     ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS
+// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- 
+#define AT91C_EMAC_LINKR      ((unsigned int) 0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_MDIO       ((unsigned int) 0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_IDLE       ((unsigned int) 0x1 <<  2) // (EMAC) 
+// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- 
+#define AT91C_EMAC_UBR        ((unsigned int) 0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_COL        ((unsigned int) 0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_RLES       ((unsigned int) 0x1 <<  2) // (EMAC) 
+#define AT91C_EMAC_TGO        ((unsigned int) 0x1 <<  3) // (EMAC) Transmit Go
+#define AT91C_EMAC_BEX        ((unsigned int) 0x1 <<  4) // (EMAC) Buffers exhausted mid frame
+#define AT91C_EMAC_COMP       ((unsigned int) 0x1 <<  5) // (EMAC) 
+#define AT91C_EMAC_UND        ((unsigned int) 0x1 <<  6) // (EMAC) 
+// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- 
+#define AT91C_EMAC_BNA        ((unsigned int) 0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_REC        ((unsigned int) 0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_OVR        ((unsigned int) 0x1 <<  2) // (EMAC) 
+// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- 
+#define AT91C_EMAC_MFD        ((unsigned int) 0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_RCOMP      ((unsigned int) 0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_RXUBR      ((unsigned int) 0x1 <<  2) // (EMAC) 
+#define AT91C_EMAC_TXUBR      ((unsigned int) 0x1 <<  3) // (EMAC) 
+#define AT91C_EMAC_TUNDR      ((unsigned int) 0x1 <<  4) // (EMAC) 
+#define AT91C_EMAC_RLEX       ((unsigned int) 0x1 <<  5) // (EMAC) 
+#define AT91C_EMAC_TXERR      ((unsigned int) 0x1 <<  6) // (EMAC) 
+#define AT91C_EMAC_TCOMP      ((unsigned int) 0x1 <<  7) // (EMAC) 
+#define AT91C_EMAC_LINK       ((unsigned int) 0x1 <<  9) // (EMAC) 
+#define AT91C_EMAC_ROVR       ((unsigned int) 0x1 << 10) // (EMAC) 
+#define AT91C_EMAC_HRESP      ((unsigned int) 0x1 << 11) // (EMAC) 
+#define AT91C_EMAC_PFRE       ((unsigned int) 0x1 << 12) // (EMAC) 
+#define AT91C_EMAC_PTZ        ((unsigned int) 0x1 << 13) // (EMAC) 
+// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- 
+// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- 
+// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- 
+// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- 
+#define AT91C_EMAC_DATA       ((unsigned int) 0xFFFF <<  0) // (EMAC) 
+#define AT91C_EMAC_CODE       ((unsigned int) 0x3 << 16) // (EMAC) 
+#define AT91C_EMAC_REGA       ((unsigned int) 0x1F << 18) // (EMAC) 
+#define AT91C_EMAC_PHYA       ((unsigned int) 0x1F << 23) // (EMAC) 
+#define AT91C_EMAC_RW         ((unsigned int) 0x3 << 28) // (EMAC) 
+#define AT91C_EMAC_SOF        ((unsigned int) 0x3 << 30) // (EMAC) 
+// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- 
+#define AT91C_EMAC_RMII       ((unsigned int) 0x1 <<  0) // (EMAC) Reduce MII
+// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- 
+#define AT91C_EMAC_IP         ((unsigned int) 0xFFFF <<  0) // (EMAC) ARP request IP address
+#define AT91C_EMAC_MAG        ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable
+#define AT91C_EMAC_ARP        ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable
+#define AT91C_EMAC_SA1        ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable
+// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- 
+#define AT91C_EMAC_REVREF     ((unsigned int) 0xFFFF <<  0) // (EMAC) 
+#define AT91C_EMAC_PARTREF    ((unsigned int) 0xFFFF << 16) // (EMAC) 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
+// *****************************************************************************
+typedef struct _AT91S_ADC {
+	AT91_REG	 ADC_CR; 	// ADC Control Register
+	AT91_REG	 ADC_MR; 	// ADC Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 ADC_CHER; 	// ADC Channel Enable Register
+	AT91_REG	 ADC_CHDR; 	// ADC Channel Disable Register
+	AT91_REG	 ADC_CHSR; 	// ADC Channel Status Register
+	AT91_REG	 ADC_SR; 	// ADC Status Register
+	AT91_REG	 ADC_LCDR; 	// ADC Last Converted Data Register
+	AT91_REG	 ADC_IER; 	// ADC Interrupt Enable Register
+	AT91_REG	 ADC_IDR; 	// ADC Interrupt Disable Register
+	AT91_REG	 ADC_IMR; 	// ADC Interrupt Mask Register
+	AT91_REG	 ADC_CDR0; 	// ADC Channel Data Register 0
+	AT91_REG	 ADC_CDR1; 	// ADC Channel Data Register 1
+	AT91_REG	 ADC_CDR2; 	// ADC Channel Data Register 2
+	AT91_REG	 ADC_CDR3; 	// ADC Channel Data Register 3
+	AT91_REG	 ADC_CDR4; 	// ADC Channel Data Register 4
+	AT91_REG	 ADC_CDR5; 	// ADC Channel Data Register 5
+	AT91_REG	 ADC_CDR6; 	// ADC Channel Data Register 6
+	AT91_REG	 ADC_CDR7; 	// ADC Channel Data Register 7
+	AT91_REG	 Reserved1[44]; 	// 
+	AT91_REG	 ADC_RPR; 	// Receive Pointer Register
+	AT91_REG	 ADC_RCR; 	// Receive Counter Register
+	AT91_REG	 ADC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 ADC_TCR; 	// Transmit Counter Register
+	AT91_REG	 ADC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 ADC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 ADC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 ADC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 ADC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 ADC_PTSR; 	// PDC Transfer Status Register
+} AT91S_ADC, *AT91PS_ADC;
+
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- 
+#define AT91C_ADC_SWRST       ((unsigned int) 0x1 <<  0) // (ADC) Software Reset
+#define AT91C_ADC_START       ((unsigned int) 0x1 <<  1) // (ADC) Start Conversion
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- 
+#define AT91C_ADC_TRGEN       ((unsigned int) 0x1 <<  0) // (ADC) Trigger Enable
+#define 	AT91C_ADC_TRGEN_DIS                  ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
+#define 	AT91C_ADC_TRGEN_EN                   ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
+#define AT91C_ADC_TRGSEL      ((unsigned int) 0x7 <<  1) // (ADC) Trigger Selection
+#define 	AT91C_ADC_TRGSEL_TIOA0                ((unsigned int) 0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
+#define 	AT91C_ADC_TRGSEL_TIOA1                ((unsigned int) 0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
+#define 	AT91C_ADC_TRGSEL_TIOA2                ((unsigned int) 0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
+#define 	AT91C_ADC_TRGSEL_TIOA3                ((unsigned int) 0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
+#define 	AT91C_ADC_TRGSEL_TIOA4                ((unsigned int) 0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
+#define 	AT91C_ADC_TRGSEL_TIOA5                ((unsigned int) 0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
+#define 	AT91C_ADC_TRGSEL_EXT                  ((unsigned int) 0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
+#define AT91C_ADC_LOWRES      ((unsigned int) 0x1 <<  4) // (ADC) Resolution.
+#define 	AT91C_ADC_LOWRES_10_BIT               ((unsigned int) 0x0 <<  4) // (ADC) 10-bit resolution
+#define 	AT91C_ADC_LOWRES_8_BIT                ((unsigned int) 0x1 <<  4) // (ADC) 8-bit resolution
+#define AT91C_ADC_SLEEP       ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
+#define 	AT91C_ADC_SLEEP_NORMAL_MODE          ((unsigned int) 0x0 <<  5) // (ADC) Normal Mode
+#define 	AT91C_ADC_SLEEP_MODE                 ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
+#define AT91C_ADC_PRESCAL     ((unsigned int) 0x3F <<  8) // (ADC) Prescaler rate selection
+#define AT91C_ADC_STARTUP     ((unsigned int) 0x1F << 16) // (ADC) Startup Time
+#define AT91C_ADC_SHTIM       ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time
+// -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- 
+#define AT91C_ADC_CH0         ((unsigned int) 0x1 <<  0) // (ADC) Channel 0
+#define AT91C_ADC_CH1         ((unsigned int) 0x1 <<  1) // (ADC) Channel 1
+#define AT91C_ADC_CH2         ((unsigned int) 0x1 <<  2) // (ADC) Channel 2
+#define AT91C_ADC_CH3         ((unsigned int) 0x1 <<  3) // (ADC) Channel 3
+#define AT91C_ADC_CH4         ((unsigned int) 0x1 <<  4) // (ADC) Channel 4
+#define AT91C_ADC_CH5         ((unsigned int) 0x1 <<  5) // (ADC) Channel 5
+#define AT91C_ADC_CH6         ((unsigned int) 0x1 <<  6) // (ADC) Channel 6
+#define AT91C_ADC_CH7         ((unsigned int) 0x1 <<  7) // (ADC) Channel 7
+// -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- 
+// -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- 
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- 
+#define AT91C_ADC_EOC0        ((unsigned int) 0x1 <<  0) // (ADC) End of Conversion
+#define AT91C_ADC_EOC1        ((unsigned int) 0x1 <<  1) // (ADC) End of Conversion
+#define AT91C_ADC_EOC2        ((unsigned int) 0x1 <<  2) // (ADC) End of Conversion
+#define AT91C_ADC_EOC3        ((unsigned int) 0x1 <<  3) // (ADC) End of Conversion
+#define AT91C_ADC_EOC4        ((unsigned int) 0x1 <<  4) // (ADC) End of Conversion
+#define AT91C_ADC_EOC5        ((unsigned int) 0x1 <<  5) // (ADC) End of Conversion
+#define AT91C_ADC_EOC6        ((unsigned int) 0x1 <<  6) // (ADC) End of Conversion
+#define AT91C_ADC_EOC7        ((unsigned int) 0x1 <<  7) // (ADC) End of Conversion
+#define AT91C_ADC_OVRE0       ((unsigned int) 0x1 <<  8) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE1       ((unsigned int) 0x1 <<  9) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE2       ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE3       ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE4       ((unsigned int) 0x1 << 12) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE5       ((unsigned int) 0x1 << 13) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE6       ((unsigned int) 0x1 << 14) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE7       ((unsigned int) 0x1 << 15) // (ADC) Overrun Error
+#define AT91C_ADC_DRDY        ((unsigned int) 0x1 << 16) // (ADC) Data Ready
+#define AT91C_ADC_GOVRE       ((unsigned int) 0x1 << 17) // (ADC) General Overrun
+#define AT91C_ADC_ENDRX       ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer
+#define AT91C_ADC_RXBUFF      ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- 
+#define AT91C_ADC_LDATA       ((unsigned int) 0x3FF <<  0) // (ADC) Last Data Converted
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- 
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- 
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- 
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- 
+#define AT91C_ADC_DATA        ((unsigned int) 0x3FF <<  0) // (ADC) Converted Data
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- 
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- 
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- 
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- 
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- 
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- 
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Advanced  Encryption Standard
+// *****************************************************************************
+typedef struct _AT91S_AES {
+	AT91_REG	 AES_CR; 	// Control Register
+	AT91_REG	 AES_MR; 	// Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 AES_IER; 	// Interrupt Enable Register
+	AT91_REG	 AES_IDR; 	// Interrupt Disable Register
+	AT91_REG	 AES_IMR; 	// Interrupt Mask Register
+	AT91_REG	 AES_ISR; 	// Interrupt Status Register
+	AT91_REG	 AES_KEYWxR[4]; 	// Key Word x Register
+	AT91_REG	 Reserved1[4]; 	// 
+	AT91_REG	 AES_IDATAxR[4]; 	// Input Data x Register
+	AT91_REG	 AES_ODATAxR[4]; 	// Output Data x Register
+	AT91_REG	 AES_IVxR[4]; 	// Initialization Vector x Register
+	AT91_REG	 Reserved2[35]; 	// 
+	AT91_REG	 AES_VR; 	// AES Version Register
+	AT91_REG	 AES_RPR; 	// Receive Pointer Register
+	AT91_REG	 AES_RCR; 	// Receive Counter Register
+	AT91_REG	 AES_TPR; 	// Transmit Pointer Register
+	AT91_REG	 AES_TCR; 	// Transmit Counter Register
+	AT91_REG	 AES_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 AES_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 AES_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 AES_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 AES_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 AES_PTSR; 	// PDC Transfer Status Register
+} AT91S_AES, *AT91PS_AES;
+
+// -------- AES_CR : (AES Offset: 0x0) Control Register -------- 
+#define AT91C_AES_START       ((unsigned int) 0x1 <<  0) // (AES) Starts Processing
+#define AT91C_AES_SWRST       ((unsigned int) 0x1 <<  8) // (AES) Software Reset
+#define AT91C_AES_LOADSEED    ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading
+// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- 
+#define AT91C_AES_CIPHER      ((unsigned int) 0x1 <<  0) // (AES) Processing Mode
+#define AT91C_AES_PROCDLY     ((unsigned int) 0xF <<  4) // (AES) Processing Delay
+#define AT91C_AES_SMOD        ((unsigned int) 0x3 <<  8) // (AES) Start Mode
+#define 	AT91C_AES_SMOD_MANUAL               ((unsigned int) 0x0 <<  8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
+#define 	AT91C_AES_SMOD_AUTO                 ((unsigned int) 0x1 <<  8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
+#define 	AT91C_AES_SMOD_PDC                  ((unsigned int) 0x2 <<  8) // (AES) PDC Mode (cf datasheet).
+#define AT91C_AES_OPMOD       ((unsigned int) 0x7 << 12) // (AES) Operation Mode
+#define 	AT91C_AES_OPMOD_ECB                  ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode.
+#define 	AT91C_AES_OPMOD_CBC                  ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode.
+#define 	AT91C_AES_OPMOD_OFB                  ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode.
+#define 	AT91C_AES_OPMOD_CFB                  ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode.
+#define 	AT91C_AES_OPMOD_CTR                  ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode.
+#define AT91C_AES_LOD         ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode
+#define AT91C_AES_CFBS        ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size
+#define 	AT91C_AES_CFBS_128_BIT              ((unsigned int) 0x0 << 16) // (AES) 128-bit.
+#define 	AT91C_AES_CFBS_64_BIT               ((unsigned int) 0x1 << 16) // (AES) 64-bit.
+#define 	AT91C_AES_CFBS_32_BIT               ((unsigned int) 0x2 << 16) // (AES) 32-bit.
+#define 	AT91C_AES_CFBS_16_BIT               ((unsigned int) 0x3 << 16) // (AES) 16-bit.
+#define 	AT91C_AES_CFBS_8_BIT                ((unsigned int) 0x4 << 16) // (AES) 8-bit.
+#define AT91C_AES_CKEY        ((unsigned int) 0xF << 20) // (AES) Countermeasure Key
+#define AT91C_AES_CTYPE       ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type
+#define 	AT91C_AES_CTYPE_TYPE1_EN             ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE2_EN             ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE3_EN             ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE4_EN             ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE5_EN             ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled.
+// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- 
+#define AT91C_AES_DATRDY      ((unsigned int) 0x1 <<  0) // (AES) DATRDY
+#define AT91C_AES_ENDRX       ((unsigned int) 0x1 <<  1) // (AES) PDC Read Buffer End
+#define AT91C_AES_ENDTX       ((unsigned int) 0x1 <<  2) // (AES) PDC Write Buffer End
+#define AT91C_AES_RXBUFF      ((unsigned int) 0x1 <<  3) // (AES) PDC Read Buffer Full
+#define AT91C_AES_TXBUFE      ((unsigned int) 0x1 <<  4) // (AES) PDC Write Buffer Empty
+#define AT91C_AES_URAD        ((unsigned int) 0x1 <<  8) // (AES) Unspecified Register Access Detection
+// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- 
+// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- 
+// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- 
+#define AT91C_AES_URAT        ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status
+#define 	AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.
+#define 	AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing.
+#define 	AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing.
+#define 	AT91C_AES_URAT_OUT_DAT_READ_SUBKEY  ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation.
+#define 	AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation.
+#define 	AT91C_AES_URAT_WO_REG_READ          ((unsigned int) 0x5 << 12) // (AES) Write-only register read access.
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Triple Data Encryption Standard
+// *****************************************************************************
+typedef struct _AT91S_TDES {
+	AT91_REG	 TDES_CR; 	// Control Register
+	AT91_REG	 TDES_MR; 	// Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 TDES_IER; 	// Interrupt Enable Register
+	AT91_REG	 TDES_IDR; 	// Interrupt Disable Register
+	AT91_REG	 TDES_IMR; 	// Interrupt Mask Register
+	AT91_REG	 TDES_ISR; 	// Interrupt Status Register
+	AT91_REG	 TDES_KEY1WxR[2]; 	// Key 1 Word x Register
+	AT91_REG	 TDES_KEY2WxR[2]; 	// Key 2 Word x Register
+	AT91_REG	 TDES_KEY3WxR[2]; 	// Key 3 Word x Register
+	AT91_REG	 Reserved1[2]; 	// 
+	AT91_REG	 TDES_IDATAxR[2]; 	// Input Data x Register
+	AT91_REG	 Reserved2[2]; 	// 
+	AT91_REG	 TDES_ODATAxR[2]; 	// Output Data x Register
+	AT91_REG	 Reserved3[2]; 	// 
+	AT91_REG	 TDES_IVxR[2]; 	// Initialization Vector x Register
+	AT91_REG	 Reserved4[37]; 	// 
+	AT91_REG	 TDES_VR; 	// TDES Version Register
+	AT91_REG	 TDES_RPR; 	// Receive Pointer Register
+	AT91_REG	 TDES_RCR; 	// Receive Counter Register
+	AT91_REG	 TDES_TPR; 	// Transmit Pointer Register
+	AT91_REG	 TDES_TCR; 	// Transmit Counter Register
+	AT91_REG	 TDES_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 TDES_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 TDES_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 TDES_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 TDES_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 TDES_PTSR; 	// PDC Transfer Status Register
+} AT91S_TDES, *AT91PS_TDES;
+
+// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- 
+#define AT91C_TDES_START      ((unsigned int) 0x1 <<  0) // (TDES) Starts Processing
+#define AT91C_TDES_SWRST      ((unsigned int) 0x1 <<  8) // (TDES) Software Reset
+// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- 
+#define AT91C_TDES_CIPHER     ((unsigned int) 0x1 <<  0) // (TDES) Processing Mode
+#define AT91C_TDES_TDESMOD    ((unsigned int) 0x1 <<  1) // (TDES) Single or Triple DES Mode
+#define AT91C_TDES_KEYMOD     ((unsigned int) 0x1 <<  4) // (TDES) Key Mode
+#define AT91C_TDES_SMOD       ((unsigned int) 0x3 <<  8) // (TDES) Start Mode
+#define 	AT91C_TDES_SMOD_MANUAL               ((unsigned int) 0x0 <<  8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
+#define 	AT91C_TDES_SMOD_AUTO                 ((unsigned int) 0x1 <<  8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
+#define 	AT91C_TDES_SMOD_PDC                  ((unsigned int) 0x2 <<  8) // (TDES) PDC Mode (cf datasheet).
+#define AT91C_TDES_OPMOD      ((unsigned int) 0x3 << 12) // (TDES) Operation Mode
+#define 	AT91C_TDES_OPMOD_ECB                  ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode.
+#define 	AT91C_TDES_OPMOD_CBC                  ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.
+#define 	AT91C_TDES_OPMOD_OFB                  ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode.
+#define 	AT91C_TDES_OPMOD_CFB                  ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode.
+#define AT91C_TDES_LOD        ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode
+#define AT91C_TDES_CFBS       ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size
+#define 	AT91C_TDES_CFBS_64_BIT               ((unsigned int) 0x0 << 16) // (TDES) 64-bit.
+#define 	AT91C_TDES_CFBS_32_BIT               ((unsigned int) 0x1 << 16) // (TDES) 32-bit.
+#define 	AT91C_TDES_CFBS_16_BIT               ((unsigned int) 0x2 << 16) // (TDES) 16-bit.
+#define 	AT91C_TDES_CFBS_8_BIT                ((unsigned int) 0x3 << 16) // (TDES) 8-bit.
+// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- 
+#define AT91C_TDES_DATRDY     ((unsigned int) 0x1 <<  0) // (TDES) DATRDY
+#define AT91C_TDES_ENDRX      ((unsigned int) 0x1 <<  1) // (TDES) PDC Read Buffer End
+#define AT91C_TDES_ENDTX      ((unsigned int) 0x1 <<  2) // (TDES) PDC Write Buffer End
+#define AT91C_TDES_RXBUFF     ((unsigned int) 0x1 <<  3) // (TDES) PDC Read Buffer Full
+#define AT91C_TDES_TXBUFE     ((unsigned int) 0x1 <<  4) // (TDES) PDC Write Buffer Empty
+#define AT91C_TDES_URAD       ((unsigned int) 0x1 <<  8) // (TDES) Unspecified Register Access Detection
+// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- 
+// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- 
+// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- 
+#define AT91C_TDES_URAT       ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status
+#define 	AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.
+#define 	AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing.
+#define 	AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing.
+#define 	AT91C_TDES_URAT_WO_REG_READ          ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access.
+
+// *****************************************************************************
+//               REGISTER ADDRESS DEFINITION FOR AT91SAM7X128
+// *****************************************************************************
+// ========== Register definition for SYS peripheral ========== 
+// ========== Register definition for AIC peripheral ========== 
+#define AT91C_AIC_IVR   ((AT91_REG *) 	0xFFFFF100) // (AIC) IRQ Vector Register
+#define AT91C_AIC_SMR   ((AT91_REG *) 	0xFFFFF000) // (AIC) Source Mode Register
+#define AT91C_AIC_FVR   ((AT91_REG *) 	0xFFFFF104) // (AIC) FIQ Vector Register
+#define AT91C_AIC_DCR   ((AT91_REG *) 	0xFFFFF138) // (AIC) Debug Control Register (Protect)
+#define AT91C_AIC_EOICR ((AT91_REG *) 	0xFFFFF130) // (AIC) End of Interrupt Command Register
+#define AT91C_AIC_SVR   ((AT91_REG *) 	0xFFFFF080) // (AIC) Source Vector Register
+#define AT91C_AIC_FFSR  ((AT91_REG *) 	0xFFFFF148) // (AIC) Fast Forcing Status Register
+#define AT91C_AIC_ICCR  ((AT91_REG *) 	0xFFFFF128) // (AIC) Interrupt Clear Command Register
+#define AT91C_AIC_ISR   ((AT91_REG *) 	0xFFFFF108) // (AIC) Interrupt Status Register
+#define AT91C_AIC_IMR   ((AT91_REG *) 	0xFFFFF110) // (AIC) Interrupt Mask Register
+#define AT91C_AIC_IPR   ((AT91_REG *) 	0xFFFFF10C) // (AIC) Interrupt Pending Register
+#define AT91C_AIC_FFER  ((AT91_REG *) 	0xFFFFF140) // (AIC) Fast Forcing Enable Register
+#define AT91C_AIC_IECR  ((AT91_REG *) 	0xFFFFF120) // (AIC) Interrupt Enable Command Register
+#define AT91C_AIC_ISCR  ((AT91_REG *) 	0xFFFFF12C) // (AIC) Interrupt Set Command Register
+#define AT91C_AIC_FFDR  ((AT91_REG *) 	0xFFFFF144) // (AIC) Fast Forcing Disable Register
+#define AT91C_AIC_CISR  ((AT91_REG *) 	0xFFFFF114) // (AIC) Core Interrupt Status Register
+#define AT91C_AIC_IDCR  ((AT91_REG *) 	0xFFFFF124) // (AIC) Interrupt Disable Command Register
+#define AT91C_AIC_SPU   ((AT91_REG *) 	0xFFFFF134) // (AIC) Spurious Vector Register
+// ========== Register definition for PDC_DBGU peripheral ========== 
+#define AT91C_DBGU_TCR  ((AT91_REG *) 	0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
+#define AT91C_DBGU_RNPR ((AT91_REG *) 	0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
+#define AT91C_DBGU_TNPR ((AT91_REG *) 	0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
+#define AT91C_DBGU_TPR  ((AT91_REG *) 	0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
+#define AT91C_DBGU_RPR  ((AT91_REG *) 	0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
+#define AT91C_DBGU_RCR  ((AT91_REG *) 	0xFFFFF304) // (PDC_DBGU) Receive Counter Register
+#define AT91C_DBGU_RNCR ((AT91_REG *) 	0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
+#define AT91C_DBGU_PTCR ((AT91_REG *) 	0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
+#define AT91C_DBGU_PTSR ((AT91_REG *) 	0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
+#define AT91C_DBGU_TNCR ((AT91_REG *) 	0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
+// ========== Register definition for DBGU peripheral ========== 
+#define AT91C_DBGU_EXID ((AT91_REG *) 	0xFFFFF244) // (DBGU) Chip ID Extension Register
+#define AT91C_DBGU_BRGR ((AT91_REG *) 	0xFFFFF220) // (DBGU) Baud Rate Generator Register
+#define AT91C_DBGU_IDR  ((AT91_REG *) 	0xFFFFF20C) // (DBGU) Interrupt Disable Register
+#define AT91C_DBGU_CSR  ((AT91_REG *) 	0xFFFFF214) // (DBGU) Channel Status Register
+#define AT91C_DBGU_CIDR ((AT91_REG *) 	0xFFFFF240) // (DBGU) Chip ID Register
+#define AT91C_DBGU_MR   ((AT91_REG *) 	0xFFFFF204) // (DBGU) Mode Register
+#define AT91C_DBGU_IMR  ((AT91_REG *) 	0xFFFFF210) // (DBGU) Interrupt Mask Register
+#define AT91C_DBGU_CR   ((AT91_REG *) 	0xFFFFF200) // (DBGU) Control Register
+#define AT91C_DBGU_FNTR ((AT91_REG *) 	0xFFFFF248) // (DBGU) Force NTRST Register
+#define AT91C_DBGU_THR  ((AT91_REG *) 	0xFFFFF21C) // (DBGU) Transmitter Holding Register
+#define AT91C_DBGU_RHR  ((AT91_REG *) 	0xFFFFF218) // (DBGU) Receiver Holding Register
+#define AT91C_DBGU_IER  ((AT91_REG *) 	0xFFFFF208) // (DBGU) Interrupt Enable Register
+// ========== Register definition for PIOA peripheral ========== 
+#define AT91C_PIOA_ODR  ((AT91_REG *) 	0xFFFFF414) // (PIOA) Output Disable Registerr
+#define AT91C_PIOA_SODR ((AT91_REG *) 	0xFFFFF430) // (PIOA) Set Output Data Register
+#define AT91C_PIOA_ISR  ((AT91_REG *) 	0xFFFFF44C) // (PIOA) Interrupt Status Register
+#define AT91C_PIOA_ABSR ((AT91_REG *) 	0xFFFFF478) // (PIOA) AB Select Status Register
+#define AT91C_PIOA_IER  ((AT91_REG *) 	0xFFFFF440) // (PIOA) Interrupt Enable Register
+#define AT91C_PIOA_PPUDR ((AT91_REG *) 	0xFFFFF460) // (PIOA) Pull-up Disable Register
+#define AT91C_PIOA_IMR  ((AT91_REG *) 	0xFFFFF448) // (PIOA) Interrupt Mask Register
+#define AT91C_PIOA_PER  ((AT91_REG *) 	0xFFFFF400) // (PIOA) PIO Enable Register
+#define AT91C_PIOA_IFDR ((AT91_REG *) 	0xFFFFF424) // (PIOA) Input Filter Disable Register
+#define AT91C_PIOA_OWDR ((AT91_REG *) 	0xFFFFF4A4) // (PIOA) Output Write Disable Register
+#define AT91C_PIOA_MDSR ((AT91_REG *) 	0xFFFFF458) // (PIOA) Multi-driver Status Register
+#define AT91C_PIOA_IDR  ((AT91_REG *) 	0xFFFFF444) // (PIOA) Interrupt Disable Register
+#define AT91C_PIOA_ODSR ((AT91_REG *) 	0xFFFFF438) // (PIOA) Output Data Status Register
+#define AT91C_PIOA_PPUSR ((AT91_REG *) 	0xFFFFF468) // (PIOA) Pull-up Status Register
+#define AT91C_PIOA_OWSR ((AT91_REG *) 	0xFFFFF4A8) // (PIOA) Output Write Status Register
+#define AT91C_PIOA_BSR  ((AT91_REG *) 	0xFFFFF474) // (PIOA) Select B Register
+#define AT91C_PIOA_OWER ((AT91_REG *) 	0xFFFFF4A0) // (PIOA) Output Write Enable Register
+#define AT91C_PIOA_IFER ((AT91_REG *) 	0xFFFFF420) // (PIOA) Input Filter Enable Register
+#define AT91C_PIOA_PDSR ((AT91_REG *) 	0xFFFFF43C) // (PIOA) Pin Data Status Register
+#define AT91C_PIOA_PPUER ((AT91_REG *) 	0xFFFFF464) // (PIOA) Pull-up Enable Register
+#define AT91C_PIOA_OSR  ((AT91_REG *) 	0xFFFFF418) // (PIOA) Output Status Register
+#define AT91C_PIOA_ASR  ((AT91_REG *) 	0xFFFFF470) // (PIOA) Select A Register
+#define AT91C_PIOA_MDDR ((AT91_REG *) 	0xFFFFF454) // (PIOA) Multi-driver Disable Register
+#define AT91C_PIOA_CODR ((AT91_REG *) 	0xFFFFF434) // (PIOA) Clear Output Data Register
+#define AT91C_PIOA_MDER ((AT91_REG *) 	0xFFFFF450) // (PIOA) Multi-driver Enable Register
+#define AT91C_PIOA_PDR  ((AT91_REG *) 	0xFFFFF404) // (PIOA) PIO Disable Register
+#define AT91C_PIOA_IFSR ((AT91_REG *) 	0xFFFFF428) // (PIOA) Input Filter Status Register
+#define AT91C_PIOA_OER  ((AT91_REG *) 	0xFFFFF410) // (PIOA) Output Enable Register
+#define AT91C_PIOA_PSR  ((AT91_REG *) 	0xFFFFF408) // (PIOA) PIO Status Register
+// ========== Register definition for PIOB peripheral ========== 
+#define AT91C_PIOB_OWDR ((AT91_REG *) 	0xFFFFF6A4) // (PIOB) Output Write Disable Register
+#define AT91C_PIOB_MDER ((AT91_REG *) 	0xFFFFF650) // (PIOB) Multi-driver Enable Register
+#define AT91C_PIOB_PPUSR ((AT91_REG *) 	0xFFFFF668) // (PIOB) Pull-up Status Register
+#define AT91C_PIOB_IMR  ((AT91_REG *) 	0xFFFFF648) // (PIOB) Interrupt Mask Register
+#define AT91C_PIOB_ASR  ((AT91_REG *) 	0xFFFFF670) // (PIOB) Select A Register
+#define AT91C_PIOB_PPUDR ((AT91_REG *) 	0xFFFFF660) // (PIOB) Pull-up Disable Register
+#define AT91C_PIOB_PSR  ((AT91_REG *) 	0xFFFFF608) // (PIOB) PIO Status Register
+#define AT91C_PIOB_IER  ((AT91_REG *) 	0xFFFFF640) // (PIOB) Interrupt Enable Register
+#define AT91C_PIOB_CODR ((AT91_REG *) 	0xFFFFF634) // (PIOB) Clear Output Data Register
+#define AT91C_PIOB_OWER ((AT91_REG *) 	0xFFFFF6A0) // (PIOB) Output Write Enable Register
+#define AT91C_PIOB_ABSR ((AT91_REG *) 	0xFFFFF678) // (PIOB) AB Select Status Register
+#define AT91C_PIOB_IFDR ((AT91_REG *) 	0xFFFFF624) // (PIOB) Input Filter Disable Register
+#define AT91C_PIOB_PDSR ((AT91_REG *) 	0xFFFFF63C) // (PIOB) Pin Data Status Register
+#define AT91C_PIOB_IDR  ((AT91_REG *) 	0xFFFFF644) // (PIOB) Interrupt Disable Register
+#define AT91C_PIOB_OWSR ((AT91_REG *) 	0xFFFFF6A8) // (PIOB) Output Write Status Register
+#define AT91C_PIOB_PDR  ((AT91_REG *) 	0xFFFFF604) // (PIOB) PIO Disable Register
+#define AT91C_PIOB_ODR  ((AT91_REG *) 	0xFFFFF614) // (PIOB) Output Disable Registerr
+#define AT91C_PIOB_IFSR ((AT91_REG *) 	0xFFFFF628) // (PIOB) Input Filter Status Register
+#define AT91C_PIOB_PPUER ((AT91_REG *) 	0xFFFFF664) // (PIOB) Pull-up Enable Register
+#define AT91C_PIOB_SODR ((AT91_REG *) 	0xFFFFF630) // (PIOB) Set Output Data Register
+#define AT91C_PIOB_ISR  ((AT91_REG *) 	0xFFFFF64C) // (PIOB) Interrupt Status Register
+#define AT91C_PIOB_ODSR ((AT91_REG *) 	0xFFFFF638) // (PIOB) Output Data Status Register
+#define AT91C_PIOB_OSR  ((AT91_REG *) 	0xFFFFF618) // (PIOB) Output Status Register
+#define AT91C_PIOB_MDSR ((AT91_REG *) 	0xFFFFF658) // (PIOB) Multi-driver Status Register
+#define AT91C_PIOB_IFER ((AT91_REG *) 	0xFFFFF620) // (PIOB) Input Filter Enable Register
+#define AT91C_PIOB_BSR  ((AT91_REG *) 	0xFFFFF674) // (PIOB) Select B Register
+#define AT91C_PIOB_MDDR ((AT91_REG *) 	0xFFFFF654) // (PIOB) Multi-driver Disable Register
+#define AT91C_PIOB_OER  ((AT91_REG *) 	0xFFFFF610) // (PIOB) Output Enable Register
+#define AT91C_PIOB_PER  ((AT91_REG *) 	0xFFFFF600) // (PIOB) PIO Enable Register
+// ========== Register definition for CKGR peripheral ========== 
+#define AT91C_CKGR_MOR  ((AT91_REG *) 	0xFFFFFC20) // (CKGR) Main Oscillator Register
+#define AT91C_CKGR_PLLR ((AT91_REG *) 	0xFFFFFC2C) // (CKGR) PLL Register
+#define AT91C_CKGR_MCFR ((AT91_REG *) 	0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
+// ========== Register definition for PMC peripheral ========== 
+#define AT91C_PMC_IDR   ((AT91_REG *) 	0xFFFFFC64) // (PMC) Interrupt Disable Register
+#define AT91C_PMC_MOR   ((AT91_REG *) 	0xFFFFFC20) // (PMC) Main Oscillator Register
+#define AT91C_PMC_PLLR  ((AT91_REG *) 	0xFFFFFC2C) // (PMC) PLL Register
+#define AT91C_PMC_PCER  ((AT91_REG *) 	0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
+#define AT91C_PMC_PCKR  ((AT91_REG *) 	0xFFFFFC40) // (PMC) Programmable Clock Register
+#define AT91C_PMC_MCKR  ((AT91_REG *) 	0xFFFFFC30) // (PMC) Master Clock Register
+#define AT91C_PMC_SCDR  ((AT91_REG *) 	0xFFFFFC04) // (PMC) System Clock Disable Register
+#define AT91C_PMC_PCDR  ((AT91_REG *) 	0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
+#define AT91C_PMC_SCSR  ((AT91_REG *) 	0xFFFFFC08) // (PMC) System Clock Status Register
+#define AT91C_PMC_PCSR  ((AT91_REG *) 	0xFFFFFC18) // (PMC) Peripheral Clock Status Register
+#define AT91C_PMC_MCFR  ((AT91_REG *) 	0xFFFFFC24) // (PMC) Main Clock  Frequency Register
+#define AT91C_PMC_SCER  ((AT91_REG *) 	0xFFFFFC00) // (PMC) System Clock Enable Register
+#define AT91C_PMC_IMR   ((AT91_REG *) 	0xFFFFFC6C) // (PMC) Interrupt Mask Register
+#define AT91C_PMC_IER   ((AT91_REG *) 	0xFFFFFC60) // (PMC) Interrupt Enable Register
+#define AT91C_PMC_SR    ((AT91_REG *) 	0xFFFFFC68) // (PMC) Status Register
+// ========== Register definition for RSTC peripheral ========== 
+#define AT91C_RSTC_RCR  ((AT91_REG *) 	0xFFFFFD00) // (RSTC) Reset Control Register
+#define AT91C_RSTC_RMR  ((AT91_REG *) 	0xFFFFFD08) // (RSTC) Reset Mode Register
+#define AT91C_RSTC_RSR  ((AT91_REG *) 	0xFFFFFD04) // (RSTC) Reset Status Register
+// ========== Register definition for RTTC peripheral ========== 
+#define AT91C_RTTC_RTSR ((AT91_REG *) 	0xFFFFFD2C) // (RTTC) Real-time Status Register
+#define AT91C_RTTC_RTMR ((AT91_REG *) 	0xFFFFFD20) // (RTTC) Real-time Mode Register
+#define AT91C_RTTC_RTVR ((AT91_REG *) 	0xFFFFFD28) // (RTTC) Real-time Value Register
+#define AT91C_RTTC_RTAR ((AT91_REG *) 	0xFFFFFD24) // (RTTC) Real-time Alarm Register
+// ========== Register definition for PITC peripheral ========== 
+#define AT91C_PITC_PIVR ((AT91_REG *) 	0xFFFFFD38) // (PITC) Period Interval Value Register
+#define AT91C_PITC_PISR ((AT91_REG *) 	0xFFFFFD34) // (PITC) Period Interval Status Register
+#define AT91C_PITC_PIIR ((AT91_REG *) 	0xFFFFFD3C) // (PITC) Period Interval Image Register
+#define AT91C_PITC_PIMR ((AT91_REG *) 	0xFFFFFD30) // (PITC) Period Interval Mode Register
+// ========== Register definition for WDTC peripheral ========== 
+#define AT91C_WDTC_WDCR ((AT91_REG *) 	0xFFFFFD40) // (WDTC) Watchdog Control Register
+#define AT91C_WDTC_WDSR ((AT91_REG *) 	0xFFFFFD48) // (WDTC) Watchdog Status Register
+#define AT91C_WDTC_WDMR ((AT91_REG *) 	0xFFFFFD44) // (WDTC) Watchdog Mode Register
+// ========== Register definition for VREG peripheral ========== 
+#define AT91C_VREG_MR   ((AT91_REG *) 	0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
+// ========== Register definition for MC peripheral ========== 
+#define AT91C_MC_ASR    ((AT91_REG *) 	0xFFFFFF04) // (MC) MC Abort Status Register
+#define AT91C_MC_RCR    ((AT91_REG *) 	0xFFFFFF00) // (MC) MC Remap Control Register
+#define AT91C_MC_FCR    ((AT91_REG *) 	0xFFFFFF64) // (MC) MC Flash Command Register
+#define AT91C_MC_AASR   ((AT91_REG *) 	0xFFFFFF08) // (MC) MC Abort Address Status Register
+#define AT91C_MC_FSR    ((AT91_REG *) 	0xFFFFFF68) // (MC) MC Flash Status Register
+#define AT91C_MC_FMR    ((AT91_REG *) 	0xFFFFFF60) // (MC) MC Flash Mode Register
+// ========== Register definition for PDC_SPI1 peripheral ========== 
+#define AT91C_SPI1_PTCR ((AT91_REG *) 	0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
+#define AT91C_SPI1_RPR  ((AT91_REG *) 	0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
+#define AT91C_SPI1_TNCR ((AT91_REG *) 	0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
+#define AT91C_SPI1_TPR  ((AT91_REG *) 	0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
+#define AT91C_SPI1_TNPR ((AT91_REG *) 	0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
+#define AT91C_SPI1_TCR  ((AT91_REG *) 	0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
+#define AT91C_SPI1_RCR  ((AT91_REG *) 	0xFFFE4104) // (PDC_SPI1) Receive Counter Register
+#define AT91C_SPI1_RNPR ((AT91_REG *) 	0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
+#define AT91C_SPI1_RNCR ((AT91_REG *) 	0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
+#define AT91C_SPI1_PTSR ((AT91_REG *) 	0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
+// ========== Register definition for SPI1 peripheral ========== 
+#define AT91C_SPI1_IMR  ((AT91_REG *) 	0xFFFE401C) // (SPI1) Interrupt Mask Register
+#define AT91C_SPI1_IER  ((AT91_REG *) 	0xFFFE4014) // (SPI1) Interrupt Enable Register
+#define AT91C_SPI1_MR   ((AT91_REG *) 	0xFFFE4004) // (SPI1) Mode Register
+#define AT91C_SPI1_RDR  ((AT91_REG *) 	0xFFFE4008) // (SPI1) Receive Data Register
+#define AT91C_SPI1_IDR  ((AT91_REG *) 	0xFFFE4018) // (SPI1) Interrupt Disable Register
+#define AT91C_SPI1_SR   ((AT91_REG *) 	0xFFFE4010) // (SPI1) Status Register
+#define AT91C_SPI1_TDR  ((AT91_REG *) 	0xFFFE400C) // (SPI1) Transmit Data Register
+#define AT91C_SPI1_CR   ((AT91_REG *) 	0xFFFE4000) // (SPI1) Control Register
+#define AT91C_SPI1_CSR  ((AT91_REG *) 	0xFFFE4030) // (SPI1) Chip Select Register
+// ========== Register definition for PDC_SPI0 peripheral ========== 
+#define AT91C_SPI0_PTCR ((AT91_REG *) 	0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
+#define AT91C_SPI0_TPR  ((AT91_REG *) 	0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
+#define AT91C_SPI0_TCR  ((AT91_REG *) 	0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
+#define AT91C_SPI0_RCR  ((AT91_REG *) 	0xFFFE0104) // (PDC_SPI0) Receive Counter Register
+#define AT91C_SPI0_PTSR ((AT91_REG *) 	0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
+#define AT91C_SPI0_RNPR ((AT91_REG *) 	0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
+#define AT91C_SPI0_RPR  ((AT91_REG *) 	0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
+#define AT91C_SPI0_TNCR ((AT91_REG *) 	0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
+#define AT91C_SPI0_RNCR ((AT91_REG *) 	0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
+#define AT91C_SPI0_TNPR ((AT91_REG *) 	0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
+// ========== Register definition for SPI0 peripheral ========== 
+#define AT91C_SPI0_IER  ((AT91_REG *) 	0xFFFE0014) // (SPI0) Interrupt Enable Register
+#define AT91C_SPI0_SR   ((AT91_REG *) 	0xFFFE0010) // (SPI0) Status Register
+#define AT91C_SPI0_IDR  ((AT91_REG *) 	0xFFFE0018) // (SPI0) Interrupt Disable Register
+#define AT91C_SPI0_CR   ((AT91_REG *) 	0xFFFE0000) // (SPI0) Control Register
+#define AT91C_SPI0_MR   ((AT91_REG *) 	0xFFFE0004) // (SPI0) Mode Register
+#define AT91C_SPI0_IMR  ((AT91_REG *) 	0xFFFE001C) // (SPI0) Interrupt Mask Register
+#define AT91C_SPI0_TDR  ((AT91_REG *) 	0xFFFE000C) // (SPI0) Transmit Data Register
+#define AT91C_SPI0_RDR  ((AT91_REG *) 	0xFFFE0008) // (SPI0) Receive Data Register
+#define AT91C_SPI0_CSR  ((AT91_REG *) 	0xFFFE0030) // (SPI0) Chip Select Register
+// ========== Register definition for PDC_US1 peripheral ========== 
+#define AT91C_US1_RNCR  ((AT91_REG *) 	0xFFFC4114) // (PDC_US1) Receive Next Counter Register
+#define AT91C_US1_PTCR  ((AT91_REG *) 	0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
+#define AT91C_US1_TCR   ((AT91_REG *) 	0xFFFC410C) // (PDC_US1) Transmit Counter Register
+#define AT91C_US1_PTSR  ((AT91_REG *) 	0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
+#define AT91C_US1_TNPR  ((AT91_REG *) 	0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
+#define AT91C_US1_RCR   ((AT91_REG *) 	0xFFFC4104) // (PDC_US1) Receive Counter Register
+#define AT91C_US1_RNPR  ((AT91_REG *) 	0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
+#define AT91C_US1_RPR   ((AT91_REG *) 	0xFFFC4100) // (PDC_US1) Receive Pointer Register
+#define AT91C_US1_TNCR  ((AT91_REG *) 	0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
+#define AT91C_US1_TPR   ((AT91_REG *) 	0xFFFC4108) // (PDC_US1) Transmit Pointer Register
+// ========== Register definition for US1 peripheral ========== 
+#define AT91C_US1_IF    ((AT91_REG *) 	0xFFFC404C) // (US1) IRDA_FILTER Register
+#define AT91C_US1_NER   ((AT91_REG *) 	0xFFFC4044) // (US1) Nb Errors Register
+#define AT91C_US1_RTOR  ((AT91_REG *) 	0xFFFC4024) // (US1) Receiver Time-out Register
+#define AT91C_US1_CSR   ((AT91_REG *) 	0xFFFC4014) // (US1) Channel Status Register
+#define AT91C_US1_IDR   ((AT91_REG *) 	0xFFFC400C) // (US1) Interrupt Disable Register
+#define AT91C_US1_IER   ((AT91_REG *) 	0xFFFC4008) // (US1) Interrupt Enable Register
+#define AT91C_US1_THR   ((AT91_REG *) 	0xFFFC401C) // (US1) Transmitter Holding Register
+#define AT91C_US1_TTGR  ((AT91_REG *) 	0xFFFC4028) // (US1) Transmitter Time-guard Register
+#define AT91C_US1_RHR   ((AT91_REG *) 	0xFFFC4018) // (US1) Receiver Holding Register
+#define AT91C_US1_BRGR  ((AT91_REG *) 	0xFFFC4020) // (US1) Baud Rate Generator Register
+#define AT91C_US1_IMR   ((AT91_REG *) 	0xFFFC4010) // (US1) Interrupt Mask Register
+#define AT91C_US1_FIDI  ((AT91_REG *) 	0xFFFC4040) // (US1) FI_DI_Ratio Register
+#define AT91C_US1_CR    ((AT91_REG *) 	0xFFFC4000) // (US1) Control Register
+#define AT91C_US1_MR    ((AT91_REG *) 	0xFFFC4004) // (US1) Mode Register
+// ========== Register definition for PDC_US0 peripheral ========== 
+#define AT91C_US0_TNPR  ((AT91_REG *) 	0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
+#define AT91C_US0_RNPR  ((AT91_REG *) 	0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
+#define AT91C_US0_TCR   ((AT91_REG *) 	0xFFFC010C) // (PDC_US0) Transmit Counter Register
+#define AT91C_US0_PTCR  ((AT91_REG *) 	0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
+#define AT91C_US0_PTSR  ((AT91_REG *) 	0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
+#define AT91C_US0_TNCR  ((AT91_REG *) 	0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
+#define AT91C_US0_TPR   ((AT91_REG *) 	0xFFFC0108) // (PDC_US0) Transmit Pointer Register
+#define AT91C_US0_RCR   ((AT91_REG *) 	0xFFFC0104) // (PDC_US0) Receive Counter Register
+#define AT91C_US0_RPR   ((AT91_REG *) 	0xFFFC0100) // (PDC_US0) Receive Pointer Register
+#define AT91C_US0_RNCR  ((AT91_REG *) 	0xFFFC0114) // (PDC_US0) Receive Next Counter Register
+// ========== Register definition for US0 peripheral ========== 
+#define AT91C_US0_BRGR  ((AT91_REG *) 	0xFFFC0020) // (US0) Baud Rate Generator Register
+#define AT91C_US0_NER   ((AT91_REG *) 	0xFFFC0044) // (US0) Nb Errors Register
+#define AT91C_US0_CR    ((AT91_REG *) 	0xFFFC0000) // (US0) Control Register
+#define AT91C_US0_IMR   ((AT91_REG *) 	0xFFFC0010) // (US0) Interrupt Mask Register
+#define AT91C_US0_FIDI  ((AT91_REG *) 	0xFFFC0040) // (US0) FI_DI_Ratio Register
+#define AT91C_US0_TTGR  ((AT91_REG *) 	0xFFFC0028) // (US0) Transmitter Time-guard Register
+#define AT91C_US0_MR    ((AT91_REG *) 	0xFFFC0004) // (US0) Mode Register
+#define AT91C_US0_RTOR  ((AT91_REG *) 	0xFFFC0024) // (US0) Receiver Time-out Register
+#define AT91C_US0_CSR   ((AT91_REG *) 	0xFFFC0014) // (US0) Channel Status Register
+#define AT91C_US0_RHR   ((AT91_REG *) 	0xFFFC0018) // (US0) Receiver Holding Register
+#define AT91C_US0_IDR   ((AT91_REG *) 	0xFFFC000C) // (US0) Interrupt Disable Register
+#define AT91C_US0_THR   ((AT91_REG *) 	0xFFFC001C) // (US0) Transmitter Holding Register
+#define AT91C_US0_IF    ((AT91_REG *) 	0xFFFC004C) // (US0) IRDA_FILTER Register
+#define AT91C_US0_IER   ((AT91_REG *) 	0xFFFC0008) // (US0) Interrupt Enable Register
+// ========== Register definition for PDC_SSC peripheral ========== 
+#define AT91C_SSC_TNCR  ((AT91_REG *) 	0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
+#define AT91C_SSC_RPR   ((AT91_REG *) 	0xFFFD4100) // (PDC_SSC) Receive Pointer Register
+#define AT91C_SSC_RNCR  ((AT91_REG *) 	0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
+#define AT91C_SSC_TPR   ((AT91_REG *) 	0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
+#define AT91C_SSC_PTCR  ((AT91_REG *) 	0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
+#define AT91C_SSC_TCR   ((AT91_REG *) 	0xFFFD410C) // (PDC_SSC) Transmit Counter Register
+#define AT91C_SSC_RCR   ((AT91_REG *) 	0xFFFD4104) // (PDC_SSC) Receive Counter Register
+#define AT91C_SSC_RNPR  ((AT91_REG *) 	0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
+#define AT91C_SSC_TNPR  ((AT91_REG *) 	0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
+#define AT91C_SSC_PTSR  ((AT91_REG *) 	0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
+// ========== Register definition for SSC peripheral ========== 
+#define AT91C_SSC_RHR   ((AT91_REG *) 	0xFFFD4020) // (SSC) Receive Holding Register
+#define AT91C_SSC_RSHR  ((AT91_REG *) 	0xFFFD4030) // (SSC) Receive Sync Holding Register
+#define AT91C_SSC_TFMR  ((AT91_REG *) 	0xFFFD401C) // (SSC) Transmit Frame Mode Register
+#define AT91C_SSC_IDR   ((AT91_REG *) 	0xFFFD4048) // (SSC) Interrupt Disable Register
+#define AT91C_SSC_THR   ((AT91_REG *) 	0xFFFD4024) // (SSC) Transmit Holding Register
+#define AT91C_SSC_RCMR  ((AT91_REG *) 	0xFFFD4010) // (SSC) Receive Clock ModeRegister
+#define AT91C_SSC_IER   ((AT91_REG *) 	0xFFFD4044) // (SSC) Interrupt Enable Register
+#define AT91C_SSC_TSHR  ((AT91_REG *) 	0xFFFD4034) // (SSC) Transmit Sync Holding Register
+#define AT91C_SSC_SR    ((AT91_REG *) 	0xFFFD4040) // (SSC) Status Register
+#define AT91C_SSC_CMR   ((AT91_REG *) 	0xFFFD4004) // (SSC) Clock Mode Register
+#define AT91C_SSC_TCMR  ((AT91_REG *) 	0xFFFD4018) // (SSC) Transmit Clock Mode Register
+#define AT91C_SSC_CR    ((AT91_REG *) 	0xFFFD4000) // (SSC) Control Register
+#define AT91C_SSC_IMR   ((AT91_REG *) 	0xFFFD404C) // (SSC) Interrupt Mask Register
+#define AT91C_SSC_RFMR  ((AT91_REG *) 	0xFFFD4014) // (SSC) Receive Frame Mode Register
+// ========== Register definition for TWI peripheral ========== 
+#define AT91C_TWI_IER   ((AT91_REG *) 	0xFFFB8024) // (TWI) Interrupt Enable Register
+#define AT91C_TWI_CR    ((AT91_REG *) 	0xFFFB8000) // (TWI) Control Register
+#define AT91C_TWI_SR    ((AT91_REG *) 	0xFFFB8020) // (TWI) Status Register
+#define AT91C_TWI_IMR   ((AT91_REG *) 	0xFFFB802C) // (TWI) Interrupt Mask Register
+#define AT91C_TWI_THR   ((AT91_REG *) 	0xFFFB8034) // (TWI) Transmit Holding Register
+#define AT91C_TWI_IDR   ((AT91_REG *) 	0xFFFB8028) // (TWI) Interrupt Disable Register
+#define AT91C_TWI_IADR  ((AT91_REG *) 	0xFFFB800C) // (TWI) Internal Address Register
+#define AT91C_TWI_MMR   ((AT91_REG *) 	0xFFFB8004) // (TWI) Master Mode Register
+#define AT91C_TWI_CWGR  ((AT91_REG *) 	0xFFFB8010) // (TWI) Clock Waveform Generator Register
+#define AT91C_TWI_RHR   ((AT91_REG *) 	0xFFFB8030) // (TWI) Receive Holding Register
+// ========== Register definition for PWMC_CH3 peripheral ========== 
+#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 	0xFFFCC270) // (PWMC_CH3) Channel Update Register
+#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 	0xFFFCC274) // (PWMC_CH3) Reserved
+#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 	0xFFFCC268) // (PWMC_CH3) Channel Period Register
+#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 	0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
+#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 	0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
+#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 	0xFFFCC260) // (PWMC_CH3) Channel Mode Register
+// ========== Register definition for PWMC_CH2 peripheral ========== 
+#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 	0xFFFCC254) // (PWMC_CH2) Reserved
+#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 	0xFFFCC240) // (PWMC_CH2) Channel Mode Register
+#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 	0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
+#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 	0xFFFCC248) // (PWMC_CH2) Channel Period Register
+#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 	0xFFFCC250) // (PWMC_CH2) Channel Update Register
+#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 	0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
+// ========== Register definition for PWMC_CH1 peripheral ========== 
+#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 	0xFFFCC234) // (PWMC_CH1) Reserved
+#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 	0xFFFCC230) // (PWMC_CH1) Channel Update Register
+#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 	0xFFFCC228) // (PWMC_CH1) Channel Period Register
+#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 	0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
+#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 	0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
+#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 	0xFFFCC220) // (PWMC_CH1) Channel Mode Register
+// ========== Register definition for PWMC_CH0 peripheral ========== 
+#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 	0xFFFCC214) // (PWMC_CH0) Reserved
+#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 	0xFFFCC208) // (PWMC_CH0) Channel Period Register
+#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 	0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
+#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 	0xFFFCC200) // (PWMC_CH0) Channel Mode Register
+#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 	0xFFFCC210) // (PWMC_CH0) Channel Update Register
+#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 	0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
+// ========== Register definition for PWMC peripheral ========== 
+#define AT91C_PWMC_IDR  ((AT91_REG *) 	0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
+#define AT91C_PWMC_DIS  ((AT91_REG *) 	0xFFFCC008) // (PWMC) PWMC Disable Register
+#define AT91C_PWMC_IER  ((AT91_REG *) 	0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
+#define AT91C_PWMC_VR   ((AT91_REG *) 	0xFFFCC0FC) // (PWMC) PWMC Version Register
+#define AT91C_PWMC_ISR  ((AT91_REG *) 	0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
+#define AT91C_PWMC_SR   ((AT91_REG *) 	0xFFFCC00C) // (PWMC) PWMC Status Register
+#define AT91C_PWMC_IMR  ((AT91_REG *) 	0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
+#define AT91C_PWMC_MR   ((AT91_REG *) 	0xFFFCC000) // (PWMC) PWMC Mode Register
+#define AT91C_PWMC_ENA  ((AT91_REG *) 	0xFFFCC004) // (PWMC) PWMC Enable Register
+// ========== Register definition for UDP peripheral ========== 
+#define AT91C_UDP_IMR   ((AT91_REG *) 	0xFFFB0018) // (UDP) Interrupt Mask Register
+#define AT91C_UDP_FADDR ((AT91_REG *) 	0xFFFB0008) // (UDP) Function Address Register
+#define AT91C_UDP_NUM   ((AT91_REG *) 	0xFFFB0000) // (UDP) Frame Number Register
+#define AT91C_UDP_FDR   ((AT91_REG *) 	0xFFFB0050) // (UDP) Endpoint FIFO Data Register
+#define AT91C_UDP_ISR   ((AT91_REG *) 	0xFFFB001C) // (UDP) Interrupt Status Register
+#define AT91C_UDP_CSR   ((AT91_REG *) 	0xFFFB0030) // (UDP) Endpoint Control and Status Register
+#define AT91C_UDP_IDR   ((AT91_REG *) 	0xFFFB0014) // (UDP) Interrupt Disable Register
+#define AT91C_UDP_ICR   ((AT91_REG *) 	0xFFFB0020) // (UDP) Interrupt Clear Register
+#define AT91C_UDP_RSTEP ((AT91_REG *) 	0xFFFB0028) // (UDP) Reset Endpoint Register
+#define AT91C_UDP_TXVC  ((AT91_REG *) 	0xFFFB0074) // (UDP) Transceiver Control Register
+#define AT91C_UDP_GLBSTATE ((AT91_REG *) 	0xFFFB0004) // (UDP) Global State Register
+#define AT91C_UDP_IER   ((AT91_REG *) 	0xFFFB0010) // (UDP) Interrupt Enable Register
+// ========== Register definition for TC0 peripheral ========== 
+#define AT91C_TC0_SR    ((AT91_REG *) 	0xFFFA0020) // (TC0) Status Register
+#define AT91C_TC0_RC    ((AT91_REG *) 	0xFFFA001C) // (TC0) Register C
+#define AT91C_TC0_RB    ((AT91_REG *) 	0xFFFA0018) // (TC0) Register B
+#define AT91C_TC0_CCR   ((AT91_REG *) 	0xFFFA0000) // (TC0) Channel Control Register
+#define AT91C_TC0_CMR   ((AT91_REG *) 	0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC0_IER   ((AT91_REG *) 	0xFFFA0024) // (TC0) Interrupt Enable Register
+#define AT91C_TC0_RA    ((AT91_REG *) 	0xFFFA0014) // (TC0) Register A
+#define AT91C_TC0_IDR   ((AT91_REG *) 	0xFFFA0028) // (TC0) Interrupt Disable Register
+#define AT91C_TC0_CV    ((AT91_REG *) 	0xFFFA0010) // (TC0) Counter Value
+#define AT91C_TC0_IMR   ((AT91_REG *) 	0xFFFA002C) // (TC0) Interrupt Mask Register
+// ========== Register definition for TC1 peripheral ========== 
+#define AT91C_TC1_RB    ((AT91_REG *) 	0xFFFA0058) // (TC1) Register B
+#define AT91C_TC1_CCR   ((AT91_REG *) 	0xFFFA0040) // (TC1) Channel Control Register
+#define AT91C_TC1_IER   ((AT91_REG *) 	0xFFFA0064) // (TC1) Interrupt Enable Register
+#define AT91C_TC1_IDR   ((AT91_REG *) 	0xFFFA0068) // (TC1) Interrupt Disable Register
+#define AT91C_TC1_SR    ((AT91_REG *) 	0xFFFA0060) // (TC1) Status Register
+#define AT91C_TC1_CMR   ((AT91_REG *) 	0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC1_RA    ((AT91_REG *) 	0xFFFA0054) // (TC1) Register A
+#define AT91C_TC1_RC    ((AT91_REG *) 	0xFFFA005C) // (TC1) Register C
+#define AT91C_TC1_IMR   ((AT91_REG *) 	0xFFFA006C) // (TC1) Interrupt Mask Register
+#define AT91C_TC1_CV    ((AT91_REG *) 	0xFFFA0050) // (TC1) Counter Value
+// ========== Register definition for TC2 peripheral ========== 
+#define AT91C_TC2_CMR   ((AT91_REG *) 	0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC2_CCR   ((AT91_REG *) 	0xFFFA0080) // (TC2) Channel Control Register
+#define AT91C_TC2_CV    ((AT91_REG *) 	0xFFFA0090) // (TC2) Counter Value
+#define AT91C_TC2_RA    ((AT91_REG *) 	0xFFFA0094) // (TC2) Register A
+#define AT91C_TC2_RB    ((AT91_REG *) 	0xFFFA0098) // (TC2) Register B
+#define AT91C_TC2_IDR   ((AT91_REG *) 	0xFFFA00A8) // (TC2) Interrupt Disable Register
+#define AT91C_TC2_IMR   ((AT91_REG *) 	0xFFFA00AC) // (TC2) Interrupt Mask Register
+#define AT91C_TC2_RC    ((AT91_REG *) 	0xFFFA009C) // (TC2) Register C
+#define AT91C_TC2_IER   ((AT91_REG *) 	0xFFFA00A4) // (TC2) Interrupt Enable Register
+#define AT91C_TC2_SR    ((AT91_REG *) 	0xFFFA00A0) // (TC2) Status Register
+// ========== Register definition for TCB peripheral ========== 
+#define AT91C_TCB_BMR   ((AT91_REG *) 	0xFFFA00C4) // (TCB) TC Block Mode Register
+#define AT91C_TCB_BCR   ((AT91_REG *) 	0xFFFA00C0) // (TCB) TC Block Control Register
+// ========== Register definition for CAN_MB0 peripheral ========== 
+#define AT91C_CAN_MB0_MDL ((AT91_REG *) 	0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
+#define AT91C_CAN_MB0_MAM ((AT91_REG *) 	0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB0_MCR ((AT91_REG *) 	0xFFFD021C) // (CAN_MB0) MailBox Control Register
+#define AT91C_CAN_MB0_MID ((AT91_REG *) 	0xFFFD0208) // (CAN_MB0) MailBox ID Register
+#define AT91C_CAN_MB0_MSR ((AT91_REG *) 	0xFFFD0210) // (CAN_MB0) MailBox Status Register
+#define AT91C_CAN_MB0_MFID ((AT91_REG *) 	0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
+#define AT91C_CAN_MB0_MDH ((AT91_REG *) 	0xFFFD0218) // (CAN_MB0) MailBox Data High Register
+#define AT91C_CAN_MB0_MMR ((AT91_REG *) 	0xFFFD0200) // (CAN_MB0) MailBox Mode Register
+// ========== Register definition for CAN_MB1 peripheral ========== 
+#define AT91C_CAN_MB1_MDL ((AT91_REG *) 	0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
+#define AT91C_CAN_MB1_MID ((AT91_REG *) 	0xFFFD0228) // (CAN_MB1) MailBox ID Register
+#define AT91C_CAN_MB1_MMR ((AT91_REG *) 	0xFFFD0220) // (CAN_MB1) MailBox Mode Register
+#define AT91C_CAN_MB1_MSR ((AT91_REG *) 	0xFFFD0230) // (CAN_MB1) MailBox Status Register
+#define AT91C_CAN_MB1_MAM ((AT91_REG *) 	0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB1_MDH ((AT91_REG *) 	0xFFFD0238) // (CAN_MB1) MailBox Data High Register
+#define AT91C_CAN_MB1_MCR ((AT91_REG *) 	0xFFFD023C) // (CAN_MB1) MailBox Control Register
+#define AT91C_CAN_MB1_MFID ((AT91_REG *) 	0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
+// ========== Register definition for CAN_MB2 peripheral ========== 
+#define AT91C_CAN_MB2_MCR ((AT91_REG *) 	0xFFFD025C) // (CAN_MB2) MailBox Control Register
+#define AT91C_CAN_MB2_MDH ((AT91_REG *) 	0xFFFD0258) // (CAN_MB2) MailBox Data High Register
+#define AT91C_CAN_MB2_MID ((AT91_REG *) 	0xFFFD0248) // (CAN_MB2) MailBox ID Register
+#define AT91C_CAN_MB2_MDL ((AT91_REG *) 	0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
+#define AT91C_CAN_MB2_MMR ((AT91_REG *) 	0xFFFD0240) // (CAN_MB2) MailBox Mode Register
+#define AT91C_CAN_MB2_MAM ((AT91_REG *) 	0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB2_MFID ((AT91_REG *) 	0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
+#define AT91C_CAN_MB2_MSR ((AT91_REG *) 	0xFFFD0250) // (CAN_MB2) MailBox Status Register
+// ========== Register definition for CAN_MB3 peripheral ========== 
+#define AT91C_CAN_MB3_MFID ((AT91_REG *) 	0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
+#define AT91C_CAN_MB3_MAM ((AT91_REG *) 	0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB3_MID ((AT91_REG *) 	0xFFFD0268) // (CAN_MB3) MailBox ID Register
+#define AT91C_CAN_MB3_MCR ((AT91_REG *) 	0xFFFD027C) // (CAN_MB3) MailBox Control Register
+#define AT91C_CAN_MB3_MMR ((AT91_REG *) 	0xFFFD0260) // (CAN_MB3) MailBox Mode Register
+#define AT91C_CAN_MB3_MSR ((AT91_REG *) 	0xFFFD0270) // (CAN_MB3) MailBox Status Register
+#define AT91C_CAN_MB3_MDL ((AT91_REG *) 	0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
+#define AT91C_CAN_MB3_MDH ((AT91_REG *) 	0xFFFD0278) // (CAN_MB3) MailBox Data High Register
+// ========== Register definition for CAN_MB4 peripheral ========== 
+#define AT91C_CAN_MB4_MID ((AT91_REG *) 	0xFFFD0288) // (CAN_MB4) MailBox ID Register
+#define AT91C_CAN_MB4_MMR ((AT91_REG *) 	0xFFFD0280) // (CAN_MB4) MailBox Mode Register
+#define AT91C_CAN_MB4_MDH ((AT91_REG *) 	0xFFFD0298) // (CAN_MB4) MailBox Data High Register
+#define AT91C_CAN_MB4_MFID ((AT91_REG *) 	0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
+#define AT91C_CAN_MB4_MSR ((AT91_REG *) 	0xFFFD0290) // (CAN_MB4) MailBox Status Register
+#define AT91C_CAN_MB4_MCR ((AT91_REG *) 	0xFFFD029C) // (CAN_MB4) MailBox Control Register
+#define AT91C_CAN_MB4_MDL ((AT91_REG *) 	0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
+#define AT91C_CAN_MB4_MAM ((AT91_REG *) 	0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
+// ========== Register definition for CAN_MB5 peripheral ========== 
+#define AT91C_CAN_MB5_MSR ((AT91_REG *) 	0xFFFD02B0) // (CAN_MB5) MailBox Status Register
+#define AT91C_CAN_MB5_MCR ((AT91_REG *) 	0xFFFD02BC) // (CAN_MB5) MailBox Control Register
+#define AT91C_CAN_MB5_MFID ((AT91_REG *) 	0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
+#define AT91C_CAN_MB5_MDH ((AT91_REG *) 	0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
+#define AT91C_CAN_MB5_MID ((AT91_REG *) 	0xFFFD02A8) // (CAN_MB5) MailBox ID Register
+#define AT91C_CAN_MB5_MMR ((AT91_REG *) 	0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
+#define AT91C_CAN_MB5_MDL ((AT91_REG *) 	0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
+#define AT91C_CAN_MB5_MAM ((AT91_REG *) 	0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
+// ========== Register definition for CAN_MB6 peripheral ========== 
+#define AT91C_CAN_MB6_MFID ((AT91_REG *) 	0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
+#define AT91C_CAN_MB6_MID ((AT91_REG *) 	0xFFFD02C8) // (CAN_MB6) MailBox ID Register
+#define AT91C_CAN_MB6_MAM ((AT91_REG *) 	0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB6_MSR ((AT91_REG *) 	0xFFFD02D0) // (CAN_MB6) MailBox Status Register
+#define AT91C_CAN_MB6_MDL ((AT91_REG *) 	0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
+#define AT91C_CAN_MB6_MCR ((AT91_REG *) 	0xFFFD02DC) // (CAN_MB6) MailBox Control Register
+#define AT91C_CAN_MB6_MDH ((AT91_REG *) 	0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
+#define AT91C_CAN_MB6_MMR ((AT91_REG *) 	0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
+// ========== Register definition for CAN_MB7 peripheral ========== 
+#define AT91C_CAN_MB7_MCR ((AT91_REG *) 	0xFFFD02FC) // (CAN_MB7) MailBox Control Register
+#define AT91C_CAN_MB7_MDH ((AT91_REG *) 	0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
+#define AT91C_CAN_MB7_MFID ((AT91_REG *) 	0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
+#define AT91C_CAN_MB7_MDL ((AT91_REG *) 	0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
+#define AT91C_CAN_MB7_MID ((AT91_REG *) 	0xFFFD02E8) // (CAN_MB7) MailBox ID Register
+#define AT91C_CAN_MB7_MMR ((AT91_REG *) 	0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
+#define AT91C_CAN_MB7_MAM ((AT91_REG *) 	0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB7_MSR ((AT91_REG *) 	0xFFFD02F0) // (CAN_MB7) MailBox Status Register
+// ========== Register definition for CAN peripheral ========== 
+#define AT91C_CAN_TCR   ((AT91_REG *) 	0xFFFD0024) // (CAN) Transfer Command Register
+#define AT91C_CAN_IMR   ((AT91_REG *) 	0xFFFD000C) // (CAN) Interrupt Mask Register
+#define AT91C_CAN_IER   ((AT91_REG *) 	0xFFFD0004) // (CAN) Interrupt Enable Register
+#define AT91C_CAN_ECR   ((AT91_REG *) 	0xFFFD0020) // (CAN) Error Counter Register
+#define AT91C_CAN_TIMESTP ((AT91_REG *) 	0xFFFD001C) // (CAN) Time Stamp Register
+#define AT91C_CAN_MR    ((AT91_REG *) 	0xFFFD0000) // (CAN) Mode Register
+#define AT91C_CAN_IDR   ((AT91_REG *) 	0xFFFD0008) // (CAN) Interrupt Disable Register
+#define AT91C_CAN_ACR   ((AT91_REG *) 	0xFFFD0028) // (CAN) Abort Command Register
+#define AT91C_CAN_TIM   ((AT91_REG *) 	0xFFFD0018) // (CAN) Timer Register
+#define AT91C_CAN_SR    ((AT91_REG *) 	0xFFFD0010) // (CAN) Status Register
+#define AT91C_CAN_BR    ((AT91_REG *) 	0xFFFD0014) // (CAN) Baudrate Register
+#define AT91C_CAN_VR    ((AT91_REG *) 	0xFFFD00FC) // (CAN) Version Register
+// ========== Register definition for EMAC peripheral ========== 
+#define AT91C_EMAC_ISR  ((AT91_REG *) 	0xFFFDC024) // (EMAC) Interrupt Status Register
+#define AT91C_EMAC_SA4H ((AT91_REG *) 	0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
+#define AT91C_EMAC_SA1L ((AT91_REG *) 	0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
+#define AT91C_EMAC_ELE  ((AT91_REG *) 	0xFFFDC078) // (EMAC) Excessive Length Errors Register
+#define AT91C_EMAC_LCOL ((AT91_REG *) 	0xFFFDC05C) // (EMAC) Late Collision Register
+#define AT91C_EMAC_RLE  ((AT91_REG *) 	0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
+#define AT91C_EMAC_WOL  ((AT91_REG *) 	0xFFFDC0C4) // (EMAC) Wake On LAN Register
+#define AT91C_EMAC_DTF  ((AT91_REG *) 	0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
+#define AT91C_EMAC_TUND ((AT91_REG *) 	0xFFFDC064) // (EMAC) Transmit Underrun Error Register
+#define AT91C_EMAC_NCR  ((AT91_REG *) 	0xFFFDC000) // (EMAC) Network Control Register
+#define AT91C_EMAC_SA4L ((AT91_REG *) 	0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
+#define AT91C_EMAC_RSR  ((AT91_REG *) 	0xFFFDC020) // (EMAC) Receive Status Register
+#define AT91C_EMAC_SA3L ((AT91_REG *) 	0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
+#define AT91C_EMAC_TSR  ((AT91_REG *) 	0xFFFDC014) // (EMAC) Transmit Status Register
+#define AT91C_EMAC_IDR  ((AT91_REG *) 	0xFFFDC02C) // (EMAC) Interrupt Disable Register
+#define AT91C_EMAC_RSE  ((AT91_REG *) 	0xFFFDC074) // (EMAC) Receive Symbol Errors Register
+#define AT91C_EMAC_ECOL ((AT91_REG *) 	0xFFFDC060) // (EMAC) Excessive Collision Register
+#define AT91C_EMAC_TID  ((AT91_REG *) 	0xFFFDC0B8) // (EMAC) Type ID Checking Register
+#define AT91C_EMAC_HRB  ((AT91_REG *) 	0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
+#define AT91C_EMAC_TBQP ((AT91_REG *) 	0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
+#define AT91C_EMAC_USRIO ((AT91_REG *) 	0xFFFDC0C0) // (EMAC) USER Input/Output Register
+#define AT91C_EMAC_PTR  ((AT91_REG *) 	0xFFFDC038) // (EMAC) Pause Time Register
+#define AT91C_EMAC_SA2H ((AT91_REG *) 	0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
+#define AT91C_EMAC_ROV  ((AT91_REG *) 	0xFFFDC070) // (EMAC) Receive Overrun Errors Register
+#define AT91C_EMAC_ALE  ((AT91_REG *) 	0xFFFDC054) // (EMAC) Alignment Error Register
+#define AT91C_EMAC_RJA  ((AT91_REG *) 	0xFFFDC07C) // (EMAC) Receive Jabbers Register
+#define AT91C_EMAC_RBQP ((AT91_REG *) 	0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
+#define AT91C_EMAC_TPF  ((AT91_REG *) 	0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
+#define AT91C_EMAC_NCFGR ((AT91_REG *) 	0xFFFDC004) // (EMAC) Network Configuration Register
+#define AT91C_EMAC_HRT  ((AT91_REG *) 	0xFFFDC094) // (EMAC) Hash Address Top[63:32]
+#define AT91C_EMAC_USF  ((AT91_REG *) 	0xFFFDC080) // (EMAC) Undersize Frames Register
+#define AT91C_EMAC_FCSE ((AT91_REG *) 	0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
+#define AT91C_EMAC_TPQ  ((AT91_REG *) 	0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
+#define AT91C_EMAC_MAN  ((AT91_REG *) 	0xFFFDC034) // (EMAC) PHY Maintenance Register
+#define AT91C_EMAC_FTO  ((AT91_REG *) 	0xFFFDC040) // (EMAC) Frames Transmitted OK Register
+#define AT91C_EMAC_REV  ((AT91_REG *) 	0xFFFDC0FC) // (EMAC) Revision Register
+#define AT91C_EMAC_IMR  ((AT91_REG *) 	0xFFFDC030) // (EMAC) Interrupt Mask Register
+#define AT91C_EMAC_SCF  ((AT91_REG *) 	0xFFFDC044) // (EMAC) Single Collision Frame Register
+#define AT91C_EMAC_PFR  ((AT91_REG *) 	0xFFFDC03C) // (EMAC) Pause Frames received Register
+#define AT91C_EMAC_MCF  ((AT91_REG *) 	0xFFFDC048) // (EMAC) Multiple Collision Frame Register
+#define AT91C_EMAC_NSR  ((AT91_REG *) 	0xFFFDC008) // (EMAC) Network Status Register
+#define AT91C_EMAC_SA2L ((AT91_REG *) 	0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
+#define AT91C_EMAC_FRO  ((AT91_REG *) 	0xFFFDC04C) // (EMAC) Frames Received OK Register
+#define AT91C_EMAC_IER  ((AT91_REG *) 	0xFFFDC028) // (EMAC) Interrupt Enable Register
+#define AT91C_EMAC_SA1H ((AT91_REG *) 	0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
+#define AT91C_EMAC_CSE  ((AT91_REG *) 	0xFFFDC068) // (EMAC) Carrier Sense Error Register
+#define AT91C_EMAC_SA3H ((AT91_REG *) 	0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
+#define AT91C_EMAC_RRE  ((AT91_REG *) 	0xFFFDC06C) // (EMAC) Receive Ressource Error Register
+#define AT91C_EMAC_STE  ((AT91_REG *) 	0xFFFDC084) // (EMAC) SQE Test Error Register
+// ========== Register definition for PDC_ADC peripheral ========== 
+#define AT91C_ADC_PTSR  ((AT91_REG *) 	0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
+#define AT91C_ADC_PTCR  ((AT91_REG *) 	0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
+#define AT91C_ADC_TNPR  ((AT91_REG *) 	0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
+#define AT91C_ADC_TNCR  ((AT91_REG *) 	0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
+#define AT91C_ADC_RNPR  ((AT91_REG *) 	0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
+#define AT91C_ADC_RNCR  ((AT91_REG *) 	0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
+#define AT91C_ADC_RPR   ((AT91_REG *) 	0xFFFD8100) // (PDC_ADC) Receive Pointer Register
+#define AT91C_ADC_TCR   ((AT91_REG *) 	0xFFFD810C) // (PDC_ADC) Transmit Counter Register
+#define AT91C_ADC_TPR   ((AT91_REG *) 	0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
+#define AT91C_ADC_RCR   ((AT91_REG *) 	0xFFFD8104) // (PDC_ADC) Receive Counter Register
+// ========== Register definition for ADC peripheral ========== 
+#define AT91C_ADC_CDR2  ((AT91_REG *) 	0xFFFD8038) // (ADC) ADC Channel Data Register 2
+#define AT91C_ADC_CDR3  ((AT91_REG *) 	0xFFFD803C) // (ADC) ADC Channel Data Register 3
+#define AT91C_ADC_CDR0  ((AT91_REG *) 	0xFFFD8030) // (ADC) ADC Channel Data Register 0
+#define AT91C_ADC_CDR5  ((AT91_REG *) 	0xFFFD8044) // (ADC) ADC Channel Data Register 5
+#define AT91C_ADC_CHDR  ((AT91_REG *) 	0xFFFD8014) // (ADC) ADC Channel Disable Register
+#define AT91C_ADC_SR    ((AT91_REG *) 	0xFFFD801C) // (ADC) ADC Status Register
+#define AT91C_ADC_CDR4  ((AT91_REG *) 	0xFFFD8040) // (ADC) ADC Channel Data Register 4
+#define AT91C_ADC_CDR1  ((AT91_REG *) 	0xFFFD8034) // (ADC) ADC Channel Data Register 1
+#define AT91C_ADC_LCDR  ((AT91_REG *) 	0xFFFD8020) // (ADC) ADC Last Converted Data Register
+#define AT91C_ADC_IDR   ((AT91_REG *) 	0xFFFD8028) // (ADC) ADC Interrupt Disable Register
+#define AT91C_ADC_CR    ((AT91_REG *) 	0xFFFD8000) // (ADC) ADC Control Register
+#define AT91C_ADC_CDR7  ((AT91_REG *) 	0xFFFD804C) // (ADC) ADC Channel Data Register 7
+#define AT91C_ADC_CDR6  ((AT91_REG *) 	0xFFFD8048) // (ADC) ADC Channel Data Register 6
+#define AT91C_ADC_IER   ((AT91_REG *) 	0xFFFD8024) // (ADC) ADC Interrupt Enable Register
+#define AT91C_ADC_CHER  ((AT91_REG *) 	0xFFFD8010) // (ADC) ADC Channel Enable Register
+#define AT91C_ADC_CHSR  ((AT91_REG *) 	0xFFFD8018) // (ADC) ADC Channel Status Register
+#define AT91C_ADC_MR    ((AT91_REG *) 	0xFFFD8004) // (ADC) ADC Mode Register
+#define AT91C_ADC_IMR   ((AT91_REG *) 	0xFFFD802C) // (ADC) ADC Interrupt Mask Register
+// ========== Register definition for PDC_AES peripheral ========== 
+#define AT91C_AES_TPR   ((AT91_REG *) 	0xFFFA4108) // (PDC_AES) Transmit Pointer Register
+#define AT91C_AES_PTCR  ((AT91_REG *) 	0xFFFA4120) // (PDC_AES) PDC Transfer Control Register
+#define AT91C_AES_RNPR  ((AT91_REG *) 	0xFFFA4110) // (PDC_AES) Receive Next Pointer Register
+#define AT91C_AES_TNCR  ((AT91_REG *) 	0xFFFA411C) // (PDC_AES) Transmit Next Counter Register
+#define AT91C_AES_TCR   ((AT91_REG *) 	0xFFFA410C) // (PDC_AES) Transmit Counter Register
+#define AT91C_AES_RCR   ((AT91_REG *) 	0xFFFA4104) // (PDC_AES) Receive Counter Register
+#define AT91C_AES_RNCR  ((AT91_REG *) 	0xFFFA4114) // (PDC_AES) Receive Next Counter Register
+#define AT91C_AES_TNPR  ((AT91_REG *) 	0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register
+#define AT91C_AES_RPR   ((AT91_REG *) 	0xFFFA4100) // (PDC_AES) Receive Pointer Register
+#define AT91C_AES_PTSR  ((AT91_REG *) 	0xFFFA4124) // (PDC_AES) PDC Transfer Status Register
+// ========== Register definition for AES peripheral ========== 
+#define AT91C_AES_IVxR  ((AT91_REG *) 	0xFFFA4060) // (AES) Initialization Vector x Register
+#define AT91C_AES_MR    ((AT91_REG *) 	0xFFFA4004) // (AES) Mode Register
+#define AT91C_AES_VR    ((AT91_REG *) 	0xFFFA40FC) // (AES) AES Version Register
+#define AT91C_AES_ODATAxR ((AT91_REG *) 	0xFFFA4050) // (AES) Output Data x Register
+#define AT91C_AES_IDATAxR ((AT91_REG *) 	0xFFFA4040) // (AES) Input Data x Register
+#define AT91C_AES_CR    ((AT91_REG *) 	0xFFFA4000) // (AES) Control Register
+#define AT91C_AES_IDR   ((AT91_REG *) 	0xFFFA4014) // (AES) Interrupt Disable Register
+#define AT91C_AES_IMR   ((AT91_REG *) 	0xFFFA4018) // (AES) Interrupt Mask Register
+#define AT91C_AES_IER   ((AT91_REG *) 	0xFFFA4010) // (AES) Interrupt Enable Register
+#define AT91C_AES_KEYWxR ((AT91_REG *) 	0xFFFA4020) // (AES) Key Word x Register
+#define AT91C_AES_ISR   ((AT91_REG *) 	0xFFFA401C) // (AES) Interrupt Status Register
+// ========== Register definition for PDC_TDES peripheral ========== 
+#define AT91C_TDES_RNCR ((AT91_REG *) 	0xFFFA8114) // (PDC_TDES) Receive Next Counter Register
+#define AT91C_TDES_TCR  ((AT91_REG *) 	0xFFFA810C) // (PDC_TDES) Transmit Counter Register
+#define AT91C_TDES_RCR  ((AT91_REG *) 	0xFFFA8104) // (PDC_TDES) Receive Counter Register
+#define AT91C_TDES_TNPR ((AT91_REG *) 	0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register
+#define AT91C_TDES_RNPR ((AT91_REG *) 	0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register
+#define AT91C_TDES_RPR  ((AT91_REG *) 	0xFFFA8100) // (PDC_TDES) Receive Pointer Register
+#define AT91C_TDES_TNCR ((AT91_REG *) 	0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register
+#define AT91C_TDES_TPR  ((AT91_REG *) 	0xFFFA8108) // (PDC_TDES) Transmit Pointer Register
+#define AT91C_TDES_PTSR ((AT91_REG *) 	0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register
+#define AT91C_TDES_PTCR ((AT91_REG *) 	0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register
+// ========== Register definition for TDES peripheral ========== 
+#define AT91C_TDES_KEY2WxR ((AT91_REG *) 	0xFFFA8028) // (TDES) Key 2 Word x Register
+#define AT91C_TDES_KEY3WxR ((AT91_REG *) 	0xFFFA8030) // (TDES) Key 3 Word x Register
+#define AT91C_TDES_IDR  ((AT91_REG *) 	0xFFFA8014) // (TDES) Interrupt Disable Register
+#define AT91C_TDES_VR   ((AT91_REG *) 	0xFFFA80FC) // (TDES) TDES Version Register
+#define AT91C_TDES_IVxR ((AT91_REG *) 	0xFFFA8060) // (TDES) Initialization Vector x Register
+#define AT91C_TDES_ODATAxR ((AT91_REG *) 	0xFFFA8050) // (TDES) Output Data x Register
+#define AT91C_TDES_IMR  ((AT91_REG *) 	0xFFFA8018) // (TDES) Interrupt Mask Register
+#define AT91C_TDES_MR   ((AT91_REG *) 	0xFFFA8004) // (TDES) Mode Register
+#define AT91C_TDES_CR   ((AT91_REG *) 	0xFFFA8000) // (TDES) Control Register
+#define AT91C_TDES_IER  ((AT91_REG *) 	0xFFFA8010) // (TDES) Interrupt Enable Register
+#define AT91C_TDES_ISR  ((AT91_REG *) 	0xFFFA801C) // (TDES) Interrupt Status Register
+#define AT91C_TDES_IDATAxR ((AT91_REG *) 	0xFFFA8040) // (TDES) Input Data x Register
+#define AT91C_TDES_KEY1WxR ((AT91_REG *) 	0xFFFA8020) // (TDES) Key 1 Word x Register
+
+// *****************************************************************************
+//               PIO DEFINITIONS FOR AT91SAM7X128
+// *****************************************************************************
+#define AT91C_PIO_PA0        ((unsigned int) 1 <<  0) // Pin Controlled by PA0
+#define AT91C_PA0_RXD0     ((unsigned int) AT91C_PIO_PA0) //  USART 0 Receive Data
+#define AT91C_PIO_PA1        ((unsigned int) 1 <<  1) // Pin Controlled by PA1
+#define AT91C_PA1_TXD0     ((unsigned int) AT91C_PIO_PA1) //  USART 0 Transmit Data
+#define AT91C_PIO_PA10       ((unsigned int) 1 << 10) // Pin Controlled by PA10
+#define AT91C_PA10_TWD      ((unsigned int) AT91C_PIO_PA10) //  TWI Two-wire Serial Data
+#define AT91C_PIO_PA11       ((unsigned int) 1 << 11) // Pin Controlled by PA11
+#define AT91C_PA11_TWCK     ((unsigned int) AT91C_PIO_PA11) //  TWI Two-wire Serial Clock
+#define AT91C_PIO_PA12       ((unsigned int) 1 << 12) // Pin Controlled by PA12
+#define AT91C_PA12_NPCS00   ((unsigned int) AT91C_PIO_PA12) //  SPI 0 Peripheral Chip Select 0
+#define AT91C_PIO_PA13       ((unsigned int) 1 << 13) // Pin Controlled by PA13
+#define AT91C_PA13_NPCS01   ((unsigned int) AT91C_PIO_PA13) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PA13_PCK1     ((unsigned int) AT91C_PIO_PA13) //  PMC Programmable Clock Output 1
+#define AT91C_PIO_PA14       ((unsigned int) 1 << 14) // Pin Controlled by PA14
+#define AT91C_PA14_NPCS02   ((unsigned int) AT91C_PIO_PA14) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PA14_IRQ1     ((unsigned int) AT91C_PIO_PA14) //  External Interrupt 1
+#define AT91C_PIO_PA15       ((unsigned int) 1 << 15) // Pin Controlled by PA15
+#define AT91C_PA15_NPCS03   ((unsigned int) AT91C_PIO_PA15) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PA15_TCLK2    ((unsigned int) AT91C_PIO_PA15) //  Timer Counter 2 external clock input
+#define AT91C_PIO_PA16       ((unsigned int) 1 << 16) // Pin Controlled by PA16
+#define AT91C_PA16_MISO0    ((unsigned int) AT91C_PIO_PA16) //  SPI 0 Master In Slave
+#define AT91C_PIO_PA17       ((unsigned int) 1 << 17) // Pin Controlled by PA17
+#define AT91C_PA17_MOSI0    ((unsigned int) AT91C_PIO_PA17) //  SPI 0 Master Out Slave
+#define AT91C_PIO_PA18       ((unsigned int) 1 << 18) // Pin Controlled by PA18
+#define AT91C_PA18_SPCK0    ((unsigned int) AT91C_PIO_PA18) //  SPI 0 Serial Clock
+#define AT91C_PIO_PA19       ((unsigned int) 1 << 19) // Pin Controlled by PA19
+#define AT91C_PA19_CANRX    ((unsigned int) AT91C_PIO_PA19) //  CAN Receive
+#define AT91C_PIO_PA2        ((unsigned int) 1 <<  2) // Pin Controlled by PA2
+#define AT91C_PA2_SCK0     ((unsigned int) AT91C_PIO_PA2) //  USART 0 Serial Clock
+#define AT91C_PA2_NPCS11   ((unsigned int) AT91C_PIO_PA2) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA20       ((unsigned int) 1 << 20) // Pin Controlled by PA20
+#define AT91C_PA20_CANTX    ((unsigned int) AT91C_PIO_PA20) //  CAN Transmit
+#define AT91C_PIO_PA21       ((unsigned int) 1 << 21) // Pin Controlled by PA21
+#define AT91C_PA21_TF       ((unsigned int) AT91C_PIO_PA21) //  SSC Transmit Frame Sync
+#define AT91C_PA21_NPCS10   ((unsigned int) AT91C_PIO_PA21) //  SPI 1 Peripheral Chip Select 0
+#define AT91C_PIO_PA22       ((unsigned int) 1 << 22) // Pin Controlled by PA22
+#define AT91C_PA22_TK       ((unsigned int) AT91C_PIO_PA22) //  SSC Transmit Clock
+#define AT91C_PA22_SPCK1    ((unsigned int) AT91C_PIO_PA22) //  SPI 1 Serial Clock
+#define AT91C_PIO_PA23       ((unsigned int) 1 << 23) // Pin Controlled by PA23
+#define AT91C_PA23_TD       ((unsigned int) AT91C_PIO_PA23) //  SSC Transmit data
+#define AT91C_PA23_MOSI1    ((unsigned int) AT91C_PIO_PA23) //  SPI 1 Master Out Slave
+#define AT91C_PIO_PA24       ((unsigned int) 1 << 24) // Pin Controlled by PA24
+#define AT91C_PA24_RD       ((unsigned int) AT91C_PIO_PA24) //  SSC Receive Data
+#define AT91C_PA24_MISO1    ((unsigned int) AT91C_PIO_PA24) //  SPI 1 Master In Slave
+#define AT91C_PIO_PA25       ((unsigned int) 1 << 25) // Pin Controlled by PA25
+#define AT91C_PA25_RK       ((unsigned int) AT91C_PIO_PA25) //  SSC Receive Clock
+#define AT91C_PA25_NPCS11   ((unsigned int) AT91C_PIO_PA25) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA26       ((unsigned int) 1 << 26) // Pin Controlled by PA26
+#define AT91C_PA26_RF       ((unsigned int) AT91C_PIO_PA26) //  SSC Receive Frame Sync
+#define AT91C_PA26_NPCS12   ((unsigned int) AT91C_PIO_PA26) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA27       ((unsigned int) 1 << 27) // Pin Controlled by PA27
+#define AT91C_PA27_DRXD     ((unsigned int) AT91C_PIO_PA27) //  DBGU Debug Receive Data
+#define AT91C_PA27_PCK3     ((unsigned int) AT91C_PIO_PA27) //  PMC Programmable Clock Output 3
+#define AT91C_PIO_PA28       ((unsigned int) 1 << 28) // Pin Controlled by PA28
+#define AT91C_PA28_DTXD     ((unsigned int) AT91C_PIO_PA28) //  DBGU Debug Transmit Data
+#define AT91C_PIO_PA29       ((unsigned int) 1 << 29) // Pin Controlled by PA29
+#define AT91C_PA29_FIQ      ((unsigned int) AT91C_PIO_PA29) //  AIC Fast Interrupt Input
+#define AT91C_PA29_NPCS13   ((unsigned int) AT91C_PIO_PA29) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA3        ((unsigned int) 1 <<  3) // Pin Controlled by PA3
+#define AT91C_PA3_RTS0     ((unsigned int) AT91C_PIO_PA3) //  USART 0 Ready To Send
+#define AT91C_PA3_NPCS12   ((unsigned int) AT91C_PIO_PA3) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA30       ((unsigned int) 1 << 30) // Pin Controlled by PA30
+#define AT91C_PA30_IRQ0     ((unsigned int) AT91C_PIO_PA30) //  External Interrupt 0
+#define AT91C_PA30_PCK2     ((unsigned int) AT91C_PIO_PA30) //  PMC Programmable Clock Output 2
+#define AT91C_PIO_PA4        ((unsigned int) 1 <<  4) // Pin Controlled by PA4
+#define AT91C_PA4_CTS0     ((unsigned int) AT91C_PIO_PA4) //  USART 0 Clear To Send
+#define AT91C_PA4_NPCS13   ((unsigned int) AT91C_PIO_PA4) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA5        ((unsigned int) 1 <<  5) // Pin Controlled by PA5
+#define AT91C_PA5_RXD1     ((unsigned int) AT91C_PIO_PA5) //  USART 1 Receive Data
+#define AT91C_PIO_PA6        ((unsigned int) 1 <<  6) // Pin Controlled by PA6
+#define AT91C_PA6_TXD1     ((unsigned int) AT91C_PIO_PA6) //  USART 1 Transmit Data
+#define AT91C_PIO_PA7        ((unsigned int) 1 <<  7) // Pin Controlled by PA7
+#define AT91C_PA7_SCK1     ((unsigned int) AT91C_PIO_PA7) //  USART 1 Serial Clock
+#define AT91C_PA7_NPCS01   ((unsigned int) AT91C_PIO_PA7) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PA8        ((unsigned int) 1 <<  8) // Pin Controlled by PA8
+#define AT91C_PA8_RTS1     ((unsigned int) AT91C_PIO_PA8) //  USART 1 Ready To Send
+#define AT91C_PA8_NPCS02   ((unsigned int) AT91C_PIO_PA8) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PA9        ((unsigned int) 1 <<  9) // Pin Controlled by PA9
+#define AT91C_PA9_CTS1     ((unsigned int) AT91C_PIO_PA9) //  USART 1 Clear To Send
+#define AT91C_PA9_NPCS03   ((unsigned int) AT91C_PIO_PA9) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB0        ((unsigned int) 1 <<  0) // Pin Controlled by PB0
+#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) //  Ethernet MAC Transmit Clock/Reference Clock
+#define AT91C_PB0_PCK0     ((unsigned int) AT91C_PIO_PB0) //  PMC Programmable Clock Output 0
+#define AT91C_PIO_PB1        ((unsigned int) 1 <<  1) // Pin Controlled by PB1
+#define AT91C_PB1_ETXEN    ((unsigned int) AT91C_PIO_PB1) //  Ethernet MAC Transmit Enable
+#define AT91C_PIO_PB10       ((unsigned int) 1 << 10) // Pin Controlled by PB10
+#define AT91C_PB10_ETX2     ((unsigned int) AT91C_PIO_PB10) //  Ethernet MAC Transmit Data 2
+#define AT91C_PB10_NPCS11   ((unsigned int) AT91C_PIO_PB10) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PB11       ((unsigned int) 1 << 11) // Pin Controlled by PB11
+#define AT91C_PB11_ETX3     ((unsigned int) AT91C_PIO_PB11) //  Ethernet MAC Transmit Data 3
+#define AT91C_PB11_NPCS12   ((unsigned int) AT91C_PIO_PB11) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PB12       ((unsigned int) 1 << 12) // Pin Controlled by PB12
+#define AT91C_PB12_ETXER    ((unsigned int) AT91C_PIO_PB12) //  Ethernet MAC Transmikt Coding Error
+#define AT91C_PB12_TCLK0    ((unsigned int) AT91C_PIO_PB12) //  Timer Counter 0 external clock input
+#define AT91C_PIO_PB13       ((unsigned int) 1 << 13) // Pin Controlled by PB13
+#define AT91C_PB13_ERX2     ((unsigned int) AT91C_PIO_PB13) //  Ethernet MAC Receive Data 2
+#define AT91C_PB13_NPCS01   ((unsigned int) AT91C_PIO_PB13) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PB14       ((unsigned int) 1 << 14) // Pin Controlled by PB14
+#define AT91C_PB14_ERX3     ((unsigned int) AT91C_PIO_PB14) //  Ethernet MAC Receive Data 3
+#define AT91C_PB14_NPCS02   ((unsigned int) AT91C_PIO_PB14) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PB15       ((unsigned int) 1 << 15) // Pin Controlled by PB15
+#define AT91C_PB15_ERXDV    ((unsigned int) AT91C_PIO_PB15) //  Ethernet MAC Receive Data Valid
+#define AT91C_PIO_PB16       ((unsigned int) 1 << 16) // Pin Controlled by PB16
+#define AT91C_PB16_ECOL     ((unsigned int) AT91C_PIO_PB16) //  Ethernet MAC Collision Detected
+#define AT91C_PB16_NPCS13   ((unsigned int) AT91C_PIO_PB16) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PB17       ((unsigned int) 1 << 17) // Pin Controlled by PB17
+#define AT91C_PB17_ERXCK    ((unsigned int) AT91C_PIO_PB17) //  Ethernet MAC Receive Clock
+#define AT91C_PB17_NPCS03   ((unsigned int) AT91C_PIO_PB17) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB18       ((unsigned int) 1 << 18) // Pin Controlled by PB18
+#define AT91C_PB18_EF100    ((unsigned int) AT91C_PIO_PB18) //  Ethernet MAC Force 100 Mbits/sec
+#define AT91C_PB18_ADTRG    ((unsigned int) AT91C_PIO_PB18) //  ADC External Trigger
+#define AT91C_PIO_PB19       ((unsigned int) 1 << 19) // Pin Controlled by PB19
+#define AT91C_PB19_PWM0     ((unsigned int) AT91C_PIO_PB19) //  PWM Channel 0
+#define AT91C_PB19_TCLK1    ((unsigned int) AT91C_PIO_PB19) //  Timer Counter 1 external clock input
+#define AT91C_PIO_PB2        ((unsigned int) 1 <<  2) // Pin Controlled by PB2
+#define AT91C_PB2_ETX0     ((unsigned int) AT91C_PIO_PB2) //  Ethernet MAC Transmit Data 0
+#define AT91C_PIO_PB20       ((unsigned int) 1 << 20) // Pin Controlled by PB20
+#define AT91C_PB20_PWM1     ((unsigned int) AT91C_PIO_PB20) //  PWM Channel 1
+#define AT91C_PB20_PCK0     ((unsigned int) AT91C_PIO_PB20) //  PMC Programmable Clock Output 0
+#define AT91C_PIO_PB21       ((unsigned int) 1 << 21) // Pin Controlled by PB21
+#define AT91C_PB21_PWM2     ((unsigned int) AT91C_PIO_PB21) //  PWM Channel 2
+#define AT91C_PB21_PCK1     ((unsigned int) AT91C_PIO_PB21) //  PMC Programmable Clock Output 1
+#define AT91C_PIO_PB22       ((unsigned int) 1 << 22) // Pin Controlled by PB22
+#define AT91C_PB22_PWM3     ((unsigned int) AT91C_PIO_PB22) //  PWM Channel 3
+#define AT91C_PB22_PCK2     ((unsigned int) AT91C_PIO_PB22) //  PMC Programmable Clock Output 2
+#define AT91C_PIO_PB23       ((unsigned int) 1 << 23) // Pin Controlled by PB23
+#define AT91C_PB23_TIOA0    ((unsigned int) AT91C_PIO_PB23) //  Timer Counter 0 Multipurpose Timer I/O Pin A
+#define AT91C_PB23_DCD1     ((unsigned int) AT91C_PIO_PB23) //  USART 1 Data Carrier Detect
+#define AT91C_PIO_PB24       ((unsigned int) 1 << 24) // Pin Controlled by PB24
+#define AT91C_PB24_TIOB0    ((unsigned int) AT91C_PIO_PB24) //  Timer Counter 0 Multipurpose Timer I/O Pin B
+#define AT91C_PB24_DSR1     ((unsigned int) AT91C_PIO_PB24) //  USART 1 Data Set ready
+#define AT91C_PIO_PB25       ((unsigned int) 1 << 25) // Pin Controlled by PB25
+#define AT91C_PB25_TIOA1    ((unsigned int) AT91C_PIO_PB25) //  Timer Counter 1 Multipurpose Timer I/O Pin A
+#define AT91C_PB25_DTR1     ((unsigned int) AT91C_PIO_PB25) //  USART 1 Data Terminal ready
+#define AT91C_PIO_PB26       ((unsigned int) 1 << 26) // Pin Controlled by PB26
+#define AT91C_PB26_TIOB1    ((unsigned int) AT91C_PIO_PB26) //  Timer Counter 1 Multipurpose Timer I/O Pin B
+#define AT91C_PB26_RI1      ((unsigned int) AT91C_PIO_PB26) //  USART 1 Ring Indicator
+#define AT91C_PIO_PB27       ((unsigned int) 1 << 27) // Pin Controlled by PB27
+#define AT91C_PB27_TIOA2    ((unsigned int) AT91C_PIO_PB27) //  Timer Counter 2 Multipurpose Timer I/O Pin A
+#define AT91C_PB27_PWM0     ((unsigned int) AT91C_PIO_PB27) //  PWM Channel 0
+#define AT91C_PIO_PB28       ((unsigned int) 1 << 28) // Pin Controlled by PB28
+#define AT91C_PB28_TIOB2    ((unsigned int) AT91C_PIO_PB28) //  Timer Counter 2 Multipurpose Timer I/O Pin B
+#define AT91C_PB28_PWM1     ((unsigned int) AT91C_PIO_PB28) //  PWM Channel 1
+#define AT91C_PIO_PB29       ((unsigned int) 1 << 29) // Pin Controlled by PB29
+#define AT91C_PB29_PCK1     ((unsigned int) AT91C_PIO_PB29) //  PMC Programmable Clock Output 1
+#define AT91C_PB29_PWM2     ((unsigned int) AT91C_PIO_PB29) //  PWM Channel 2
+#define AT91C_PIO_PB3        ((unsigned int) 1 <<  3) // Pin Controlled by PB3
+#define AT91C_PB3_ETX1     ((unsigned int) AT91C_PIO_PB3) //  Ethernet MAC Transmit Data 1
+#define AT91C_PIO_PB30       ((unsigned int) 1 << 30) // Pin Controlled by PB30
+#define AT91C_PB30_PCK2     ((unsigned int) AT91C_PIO_PB30) //  PMC Programmable Clock Output 2
+#define AT91C_PB30_PWM3     ((unsigned int) AT91C_PIO_PB30) //  PWM Channel 3
+#define AT91C_PIO_PB4        ((unsigned int) 1 <<  4) // Pin Controlled by PB4
+#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) //  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
+#define AT91C_PIO_PB5        ((unsigned int) 1 <<  5) // Pin Controlled by PB5
+#define AT91C_PB5_ERX0     ((unsigned int) AT91C_PIO_PB5) //  Ethernet MAC Receive Data 0
+#define AT91C_PIO_PB6        ((unsigned int) 1 <<  6) // Pin Controlled by PB6
+#define AT91C_PB6_ERX1     ((unsigned int) AT91C_PIO_PB6) //  Ethernet MAC Receive Data 1
+#define AT91C_PIO_PB7        ((unsigned int) 1 <<  7) // Pin Controlled by PB7
+#define AT91C_PB7_ERXER    ((unsigned int) AT91C_PIO_PB7) //  Ethernet MAC Receive Error
+#define AT91C_PIO_PB8        ((unsigned int) 1 <<  8) // Pin Controlled by PB8
+#define AT91C_PB8_EMDC     ((unsigned int) AT91C_PIO_PB8) //  Ethernet MAC Management Data Clock
+#define AT91C_PIO_PB9        ((unsigned int) 1 <<  9) // Pin Controlled by PB9
+#define AT91C_PB9_EMDIO    ((unsigned int) AT91C_PIO_PB9) //  Ethernet MAC Management Data Input/Output
+
+// *****************************************************************************
+//               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X128
+// *****************************************************************************
+#define AT91C_ID_FIQ    ((unsigned int)  0) // Advanced Interrupt Controller (FIQ)
+#define AT91C_ID_SYS    ((unsigned int)  1) // System Peripheral
+#define AT91C_ID_PIOA   ((unsigned int)  2) // Parallel IO Controller A
+#define AT91C_ID_PIOB   ((unsigned int)  3) // Parallel IO Controller B
+#define AT91C_ID_SPI0   ((unsigned int)  4) // Serial Peripheral Interface 0
+#define AT91C_ID_SPI1   ((unsigned int)  5) // Serial Peripheral Interface 1
+#define AT91C_ID_US0    ((unsigned int)  6) // USART 0
+#define AT91C_ID_US1    ((unsigned int)  7) // USART 1
+#define AT91C_ID_SSC    ((unsigned int)  8) // Serial Synchronous Controller
+#define AT91C_ID_TWI    ((unsigned int)  9) // Two-Wire Interface
+#define AT91C_ID_PWMC   ((unsigned int) 10) // PWM Controller
+#define AT91C_ID_UDP    ((unsigned int) 11) // USB Device Port
+#define AT91C_ID_TC0    ((unsigned int) 12) // Timer Counter 0
+#define AT91C_ID_TC1    ((unsigned int) 13) // Timer Counter 1
+#define AT91C_ID_TC2    ((unsigned int) 14) // Timer Counter 2
+#define AT91C_ID_CAN    ((unsigned int) 15) // Control Area Network Controller
+#define AT91C_ID_EMAC   ((unsigned int) 16) // Ethernet MAC
+#define AT91C_ID_ADC    ((unsigned int) 17) // Analog-to-Digital Converter
+#define AT91C_ID_AES    ((unsigned int) 18) // Advanced Encryption Standard 128-bit
+#define AT91C_ID_TDES   ((unsigned int) 19) // Triple Data Encryption Standard
+#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved
+#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved
+#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved
+#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved
+#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved
+#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved
+#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved
+#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved
+#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved
+#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved
+#define AT91C_ID_IRQ0   ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)
+#define AT91C_ID_IRQ1   ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)
+
+// *****************************************************************************
+//               BASE ADDRESS DEFINITIONS FOR AT91SAM7X128
+// *****************************************************************************
+#define AT91C_BASE_SYS       ((AT91PS_SYS) 	0xFFFFF000) // (SYS) Base Address
+#define AT91C_BASE_AIC       ((AT91PS_AIC) 	0xFFFFF000) // (AIC) Base Address
+#define AT91C_BASE_PDC_DBGU  ((AT91PS_PDC) 	0xFFFFF300) // (PDC_DBGU) Base Address
+#define AT91C_BASE_DBGU      ((AT91PS_DBGU) 	0xFFFFF200) // (DBGU) Base Address
+#define AT91C_BASE_PIOA      ((AT91PS_PIO) 	0xFFFFF400) // (PIOA) Base Address
+#define AT91C_BASE_PIOB      ((AT91PS_PIO) 	0xFFFFF600) // (PIOB) Base Address
+#define AT91C_BASE_CKGR      ((AT91PS_CKGR) 	0xFFFFFC20) // (CKGR) Base Address
+#define AT91C_BASE_PMC       ((AT91PS_PMC) 	0xFFFFFC00) // (PMC) Base Address
+#define AT91C_BASE_RSTC      ((AT91PS_RSTC) 	0xFFFFFD00) // (RSTC) Base Address
+#define AT91C_BASE_RTTC      ((AT91PS_RTTC) 	0xFFFFFD20) // (RTTC) Base Address
+#define AT91C_BASE_PITC      ((AT91PS_PITC) 	0xFFFFFD30) // (PITC) Base Address
+#define AT91C_BASE_WDTC      ((AT91PS_WDTC) 	0xFFFFFD40) // (WDTC) Base Address
+#define AT91C_BASE_VREG      ((AT91PS_VREG) 	0xFFFFFD60) // (VREG) Base Address
+#define AT91C_BASE_MC        ((AT91PS_MC) 	0xFFFFFF00) // (MC) Base Address
+#define AT91C_BASE_PDC_SPI1  ((AT91PS_PDC) 	0xFFFE4100) // (PDC_SPI1) Base Address
+#define AT91C_BASE_SPI1      ((AT91PS_SPI) 	0xFFFE4000) // (SPI1) Base Address
+#define AT91C_BASE_PDC_SPI0  ((AT91PS_PDC) 	0xFFFE0100) // (PDC_SPI0) Base Address
+#define AT91C_BASE_SPI0      ((AT91PS_SPI) 	0xFFFE0000) // (SPI0) Base Address
+#define AT91C_BASE_PDC_US1   ((AT91PS_PDC) 	0xFFFC4100) // (PDC_US1) Base Address
+#define AT91C_BASE_US1       ((AT91PS_USART) 	0xFFFC4000) // (US1) Base Address
+#define AT91C_BASE_PDC_US0   ((AT91PS_PDC) 	0xFFFC0100) // (PDC_US0) Base Address
+#define AT91C_BASE_US0       ((AT91PS_USART) 	0xFFFC0000) // (US0) Base Address
+#define AT91C_BASE_PDC_SSC   ((AT91PS_PDC) 	0xFFFD4100) // (PDC_SSC) Base Address
+#define AT91C_BASE_SSC       ((AT91PS_SSC) 	0xFFFD4000) // (SSC) Base Address
+#define AT91C_BASE_TWI       ((AT91PS_TWI) 	0xFFFB8000) // (TWI) Base Address
+#define AT91C_BASE_PWMC_CH3  ((AT91PS_PWMC_CH) 	0xFFFCC260) // (PWMC_CH3) Base Address
+#define AT91C_BASE_PWMC_CH2  ((AT91PS_PWMC_CH) 	0xFFFCC240) // (PWMC_CH2) Base Address
+#define AT91C_BASE_PWMC_CH1  ((AT91PS_PWMC_CH) 	0xFFFCC220) // (PWMC_CH1) Base Address
+#define AT91C_BASE_PWMC_CH0  ((AT91PS_PWMC_CH) 	0xFFFCC200) // (PWMC_CH0) Base Address
+#define AT91C_BASE_PWMC      ((AT91PS_PWMC) 	0xFFFCC000) // (PWMC) Base Address
+#define AT91C_BASE_UDP       ((AT91PS_UDP) 	0xFFFB0000) // (UDP) Base Address
+#define AT91C_BASE_TC0       ((AT91PS_TC) 	0xFFFA0000) // (TC0) Base Address
+#define AT91C_BASE_TC1       ((AT91PS_TC) 	0xFFFA0040) // (TC1) Base Address
+#define AT91C_BASE_TC2       ((AT91PS_TC) 	0xFFFA0080) // (TC2) Base Address
+#define AT91C_BASE_TCB       ((AT91PS_TCB) 	0xFFFA0000) // (TCB) Base Address
+#define AT91C_BASE_CAN_MB0   ((AT91PS_CAN_MB) 	0xFFFD0200) // (CAN_MB0) Base Address
+#define AT91C_BASE_CAN_MB1   ((AT91PS_CAN_MB) 	0xFFFD0220) // (CAN_MB1) Base Address
+#define AT91C_BASE_CAN_MB2   ((AT91PS_CAN_MB) 	0xFFFD0240) // (CAN_MB2) Base Address
+#define AT91C_BASE_CAN_MB3   ((AT91PS_CAN_MB) 	0xFFFD0260) // (CAN_MB3) Base Address
+#define AT91C_BASE_CAN_MB4   ((AT91PS_CAN_MB) 	0xFFFD0280) // (CAN_MB4) Base Address
+#define AT91C_BASE_CAN_MB5   ((AT91PS_CAN_MB) 	0xFFFD02A0) // (CAN_MB5) Base Address
+#define AT91C_BASE_CAN_MB6   ((AT91PS_CAN_MB) 	0xFFFD02C0) // (CAN_MB6) Base Address
+#define AT91C_BASE_CAN_MB7   ((AT91PS_CAN_MB) 	0xFFFD02E0) // (CAN_MB7) Base Address
+#define AT91C_BASE_CAN       ((AT91PS_CAN) 	0xFFFD0000) // (CAN) Base Address
+#define AT91C_BASE_EMAC      ((AT91PS_EMAC) 	0xFFFDC000) // (EMAC) Base Address
+#define AT91C_BASE_PDC_ADC   ((AT91PS_PDC) 	0xFFFD8100) // (PDC_ADC) Base Address
+#define AT91C_BASE_ADC       ((AT91PS_ADC) 	0xFFFD8000) // (ADC) Base Address
+#define AT91C_BASE_PDC_AES   ((AT91PS_PDC) 	0xFFFA4100) // (PDC_AES) Base Address
+#define AT91C_BASE_AES       ((AT91PS_AES) 	0xFFFA4000) // (AES) Base Address
+#define AT91C_BASE_PDC_TDES  ((AT91PS_PDC) 	0xFFFA8100) // (PDC_TDES) Base Address
+#define AT91C_BASE_TDES      ((AT91PS_TDES) 	0xFFFA8000) // (TDES) Base Address
+
+// *****************************************************************************
+//               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X128
+// *****************************************************************************
+#define AT91C_ISRAM	 ((char *) 	0x00200000) // Internal SRAM base address
+#define AT91C_ISRAM_SIZE	 ((unsigned int) 0x00008000) // Internal SRAM size in byte (32 Kbyte)
+#define AT91C_IFLASH	 ((char *) 	0x00100000) // Internal ROM base address
+#define AT91C_IFLASH_SIZE	 ((unsigned int) 0x00020000) // Internal ROM size in byte (128 Kbyte)
+#endif /* __IAR_SYSTEMS_ICC__ */
+
+#ifdef __IAR_SYSTEMS_ASM__
+
+// - Hardware register definition
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR System Peripherals
+// - *****************************************************************************
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
+// - *****************************************************************************
+// - -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
+AT91C_AIC_PRIOR           EQU (0x7 <<  0) ;- (AIC) Priority Level
+AT91C_AIC_PRIOR_LOWEST    EQU (0x0) ;- (AIC) Lowest priority level
+AT91C_AIC_PRIOR_HIGHEST   EQU (0x7) ;- (AIC) Highest priority level
+AT91C_AIC_SRCTYPE         EQU (0x3 <<  5) ;- (AIC) Interrupt Source Type
+AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL EQU (0x0 <<  5) ;- (AIC) Internal Sources Code Label High-level Sensitive
+AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL EQU (0x0 <<  5) ;- (AIC) External Sources Code Label Low-level Sensitive
+AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE EQU (0x1 <<  5) ;- (AIC) Internal Sources Code Label Positive Edge triggered
+AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE EQU (0x1 <<  5) ;- (AIC) External Sources Code Label Negative Edge triggered
+AT91C_AIC_SRCTYPE_HIGH_LEVEL EQU (0x2 <<  5) ;- (AIC) Internal Or External Sources Code Label High-level Sensitive
+AT91C_AIC_SRCTYPE_POSITIVE_EDGE EQU (0x3 <<  5) ;- (AIC) Internal Or External Sources Code Label Positive Edge triggered
+// - -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
+AT91C_AIC_NFIQ            EQU (0x1 <<  0) ;- (AIC) NFIQ Status
+AT91C_AIC_NIRQ            EQU (0x1 <<  1) ;- (AIC) NIRQ Status
+// - -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
+AT91C_AIC_DCR_PROT        EQU (0x1 <<  0) ;- (AIC) Protection Mode
+AT91C_AIC_DCR_GMSK        EQU (0x1 <<  1) ;- (AIC) General Mask
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
+// - *****************************************************************************
+// - -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
+AT91C_PDC_RXTEN           EQU (0x1 <<  0) ;- (PDC) Receiver Transfer Enable
+AT91C_PDC_RXTDIS          EQU (0x1 <<  1) ;- (PDC) Receiver Transfer Disable
+AT91C_PDC_TXTEN           EQU (0x1 <<  8) ;- (PDC) Transmitter Transfer Enable
+AT91C_PDC_TXTDIS          EQU (0x1 <<  9) ;- (PDC) Transmitter Transfer Disable
+// - -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Debug Unit
+// - *****************************************************************************
+// - -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
+AT91C_US_RSTRX            EQU (0x1 <<  2) ;- (DBGU) Reset Receiver
+AT91C_US_RSTTX            EQU (0x1 <<  3) ;- (DBGU) Reset Transmitter
+AT91C_US_RXEN             EQU (0x1 <<  4) ;- (DBGU) Receiver Enable
+AT91C_US_RXDIS            EQU (0x1 <<  5) ;- (DBGU) Receiver Disable
+AT91C_US_TXEN             EQU (0x1 <<  6) ;- (DBGU) Transmitter Enable
+AT91C_US_TXDIS            EQU (0x1 <<  7) ;- (DBGU) Transmitter Disable
+AT91C_US_RSTSTA           EQU (0x1 <<  8) ;- (DBGU) Reset Status Bits
+// - -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
+AT91C_US_PAR              EQU (0x7 <<  9) ;- (DBGU) Parity type
+AT91C_US_PAR_EVEN         EQU (0x0 <<  9) ;- (DBGU) Even Parity
+AT91C_US_PAR_ODD          EQU (0x1 <<  9) ;- (DBGU) Odd Parity
+AT91C_US_PAR_SPACE        EQU (0x2 <<  9) ;- (DBGU) Parity forced to 0 (Space)
+AT91C_US_PAR_MARK         EQU (0x3 <<  9) ;- (DBGU) Parity forced to 1 (Mark)
+AT91C_US_PAR_NONE         EQU (0x4 <<  9) ;- (DBGU) No Parity
+AT91C_US_PAR_MULTI_DROP   EQU (0x6 <<  9) ;- (DBGU) Multi-drop mode
+AT91C_US_CHMODE           EQU (0x3 << 14) ;- (DBGU) Channel Mode
+AT91C_US_CHMODE_NORMAL    EQU (0x0 << 14) ;- (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+AT91C_US_CHMODE_AUTO      EQU (0x1 << 14) ;- (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+AT91C_US_CHMODE_LOCAL     EQU (0x2 << 14) ;- (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+AT91C_US_CHMODE_REMOTE    EQU (0x3 << 14) ;- (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+// - -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+AT91C_US_RXRDY            EQU (0x1 <<  0) ;- (DBGU) RXRDY Interrupt
+AT91C_US_TXRDY            EQU (0x1 <<  1) ;- (DBGU) TXRDY Interrupt
+AT91C_US_ENDRX            EQU (0x1 <<  3) ;- (DBGU) End of Receive Transfer Interrupt
+AT91C_US_ENDTX            EQU (0x1 <<  4) ;- (DBGU) End of Transmit Interrupt
+AT91C_US_OVRE             EQU (0x1 <<  5) ;- (DBGU) Overrun Interrupt
+AT91C_US_FRAME            EQU (0x1 <<  6) ;- (DBGU) Framing Error Interrupt
+AT91C_US_PARE             EQU (0x1 <<  7) ;- (DBGU) Parity Error Interrupt
+AT91C_US_TXEMPTY          EQU (0x1 <<  9) ;- (DBGU) TXEMPTY Interrupt
+AT91C_US_TXBUFE           EQU (0x1 << 11) ;- (DBGU) TXBUFE Interrupt
+AT91C_US_RXBUFF           EQU (0x1 << 12) ;- (DBGU) RXBUFF Interrupt
+AT91C_US_COMM_TX          EQU (0x1 << 30) ;- (DBGU) COMM_TX Interrupt
+AT91C_US_COMM_RX          EQU (0x1 << 31) ;- (DBGU) COMM_RX Interrupt
+// - -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// - -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// - -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
+// - -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
+AT91C_US_FORCE_NTRST      EQU (0x1 <<  0) ;- (DBGU) Force NTRST in JTAG
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
+// - *****************************************************************************
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Clock Generator Controler
+// - *****************************************************************************
+// - -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 
+AT91C_CKGR_MOSCEN         EQU (0x1 <<  0) ;- (CKGR) Main Oscillator Enable
+AT91C_CKGR_OSCBYPASS      EQU (0x1 <<  1) ;- (CKGR) Main Oscillator Bypass
+AT91C_CKGR_OSCOUNT        EQU (0xFF <<  8) ;- (CKGR) Main Oscillator Start-up Time
+// - -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 
+AT91C_CKGR_MAINF          EQU (0xFFFF <<  0) ;- (CKGR) Main Clock Frequency
+AT91C_CKGR_MAINRDY        EQU (0x1 << 16) ;- (CKGR) Main Clock Ready
+// - -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- 
+AT91C_CKGR_DIV            EQU (0xFF <<  0) ;- (CKGR) Divider Selected
+AT91C_CKGR_DIV_0          EQU (0x0) ;- (CKGR) Divider output is 0
+AT91C_CKGR_DIV_BYPASS     EQU (0x1) ;- (CKGR) Divider is bypassed
+AT91C_CKGR_PLLCOUNT       EQU (0x3F <<  8) ;- (CKGR) PLL Counter
+AT91C_CKGR_OUT            EQU (0x3 << 14) ;- (CKGR) PLL Output Frequency Range
+AT91C_CKGR_OUT_0          EQU (0x0 << 14) ;- (CKGR) Please refer to the PLL datasheet
+AT91C_CKGR_OUT_1          EQU (0x1 << 14) ;- (CKGR) Please refer to the PLL datasheet
+AT91C_CKGR_OUT_2          EQU (0x2 << 14) ;- (CKGR) Please refer to the PLL datasheet
+AT91C_CKGR_OUT_3          EQU (0x3 << 14) ;- (CKGR) Please refer to the PLL datasheet
+AT91C_CKGR_MUL            EQU (0x7FF << 16) ;- (CKGR) PLL Multiplier
+AT91C_CKGR_USBDIV         EQU (0x3 << 28) ;- (CKGR) Divider for USB Clocks
+AT91C_CKGR_USBDIV_0       EQU (0x0 << 28) ;- (CKGR) Divider output is PLL clock output
+AT91C_CKGR_USBDIV_1       EQU (0x1 << 28) ;- (CKGR) Divider output is PLL clock output divided by 2
+AT91C_CKGR_USBDIV_2       EQU (0x2 << 28) ;- (CKGR) Divider output is PLL clock output divided by 4
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Power Management Controler
+// - *****************************************************************************
+// - -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
+AT91C_PMC_PCK             EQU (0x1 <<  0) ;- (PMC) Processor Clock
+AT91C_PMC_UDP             EQU (0x1 <<  7) ;- (PMC) USB Device Port Clock
+AT91C_PMC_PCK0            EQU (0x1 <<  8) ;- (PMC) Programmable Clock Output
+AT91C_PMC_PCK1            EQU (0x1 <<  9) ;- (PMC) Programmable Clock Output
+AT91C_PMC_PCK2            EQU (0x1 << 10) ;- (PMC) Programmable Clock Output
+AT91C_PMC_PCK3            EQU (0x1 << 11) ;- (PMC) Programmable Clock Output
+// - -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
+// - -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
+// - -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 
+// - -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 
+// - -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- 
+// - -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
+AT91C_PMC_CSS             EQU (0x3 <<  0) ;- (PMC) Programmable Clock Selection
+AT91C_PMC_CSS_SLOW_CLK    EQU (0x0) ;- (PMC) Slow Clock is selected
+AT91C_PMC_CSS_MAIN_CLK    EQU (0x1) ;- (PMC) Main Clock is selected
+AT91C_PMC_CSS_PLL_CLK     EQU (0x3) ;- (PMC) Clock from PLL is selected
+AT91C_PMC_PRES            EQU (0x7 <<  2) ;- (PMC) Programmable Clock Prescaler
+AT91C_PMC_PRES_CLK        EQU (0x0 <<  2) ;- (PMC) Selected clock
+AT91C_PMC_PRES_CLK_2      EQU (0x1 <<  2) ;- (PMC) Selected clock divided by 2
+AT91C_PMC_PRES_CLK_4      EQU (0x2 <<  2) ;- (PMC) Selected clock divided by 4
+AT91C_PMC_PRES_CLK_8      EQU (0x3 <<  2) ;- (PMC) Selected clock divided by 8
+AT91C_PMC_PRES_CLK_16     EQU (0x4 <<  2) ;- (PMC) Selected clock divided by 16
+AT91C_PMC_PRES_CLK_32     EQU (0x5 <<  2) ;- (PMC) Selected clock divided by 32
+AT91C_PMC_PRES_CLK_64     EQU (0x6 <<  2) ;- (PMC) Selected clock divided by 64
+// - -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
+// - -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
+AT91C_PMC_MOSCS           EQU (0x1 <<  0) ;- (PMC) MOSC Status/Enable/Disable/Mask
+AT91C_PMC_LOCK            EQU (0x1 <<  2) ;- (PMC) PLL Status/Enable/Disable/Mask
+AT91C_PMC_MCKRDY          EQU (0x1 <<  3) ;- (PMC) MCK_RDY Status/Enable/Disable/Mask
+AT91C_PMC_PCK0RDY         EQU (0x1 <<  8) ;- (PMC) PCK0_RDY Status/Enable/Disable/Mask
+AT91C_PMC_PCK1RDY         EQU (0x1 <<  9) ;- (PMC) PCK1_RDY Status/Enable/Disable/Mask
+AT91C_PMC_PCK2RDY         EQU (0x1 << 10) ;- (PMC) PCK2_RDY Status/Enable/Disable/Mask
+AT91C_PMC_PCK3RDY         EQU (0x1 << 11) ;- (PMC) PCK3_RDY Status/Enable/Disable/Mask
+// - -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
+// - -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
+// - -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Reset Controller Interface
+// - *****************************************************************************
+// - -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 
+AT91C_RSTC_PROCRST        EQU (0x1 <<  0) ;- (RSTC) Processor Reset
+AT91C_RSTC_PERRST         EQU (0x1 <<  2) ;- (RSTC) Peripheral Reset
+AT91C_RSTC_EXTRST         EQU (0x1 <<  3) ;- (RSTC) External Reset
+AT91C_RSTC_KEY            EQU (0xFF << 24) ;- (RSTC) Password
+// - -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 
+AT91C_RSTC_URSTS          EQU (0x1 <<  0) ;- (RSTC) User Reset Status
+AT91C_RSTC_BODSTS         EQU (0x1 <<  1) ;- (RSTC) Brownout Detection Status
+AT91C_RSTC_RSTTYP         EQU (0x7 <<  8) ;- (RSTC) Reset Type
+AT91C_RSTC_RSTTYP_POWERUP EQU (0x0 <<  8) ;- (RSTC) Power-up Reset. VDDCORE rising.
+AT91C_RSTC_RSTTYP_WAKEUP  EQU (0x1 <<  8) ;- (RSTC) WakeUp Reset. VDDCORE rising.
+AT91C_RSTC_RSTTYP_WATCHDOG EQU (0x2 <<  8) ;- (RSTC) Watchdog Reset. Watchdog overflow occured.
+AT91C_RSTC_RSTTYP_SOFTWARE EQU (0x3 <<  8) ;- (RSTC) Software Reset. Processor reset required by the software.
+AT91C_RSTC_RSTTYP_USER    EQU (0x4 <<  8) ;- (RSTC) User Reset. NRST pin detected low.
+AT91C_RSTC_RSTTYP_BROWNOUT EQU (0x5 <<  8) ;- (RSTC) Brownout Reset occured.
+AT91C_RSTC_NRSTL          EQU (0x1 << 16) ;- (RSTC) NRST pin level
+AT91C_RSTC_SRCMP          EQU (0x1 << 17) ;- (RSTC) Software Reset Command in Progress.
+// - -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 
+AT91C_RSTC_URSTEN         EQU (0x1 <<  0) ;- (RSTC) User Reset Enable
+AT91C_RSTC_URSTIEN        EQU (0x1 <<  4) ;- (RSTC) User Reset Interrupt Enable
+AT91C_RSTC_ERSTL          EQU (0xF <<  8) ;- (RSTC) User Reset Enable
+AT91C_RSTC_BODIEN         EQU (0x1 << 16) ;- (RSTC) Brownout Detection Interrupt Enable
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
+// - *****************************************************************************
+// - -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 
+AT91C_RTTC_RTPRES         EQU (0xFFFF <<  0) ;- (RTTC) Real-time Timer Prescaler Value
+AT91C_RTTC_ALMIEN         EQU (0x1 << 16) ;- (RTTC) Alarm Interrupt Enable
+AT91C_RTTC_RTTINCIEN      EQU (0x1 << 17) ;- (RTTC) Real Time Timer Increment Interrupt Enable
+AT91C_RTTC_RTTRST         EQU (0x1 << 18) ;- (RTTC) Real Time Timer Restart
+// - -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 
+AT91C_RTTC_ALMV           EQU (0x0 <<  0) ;- (RTTC) Alarm Value
+// - -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 
+AT91C_RTTC_CRTV           EQU (0x0 <<  0) ;- (RTTC) Current Real-time Value
+// - -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 
+AT91C_RTTC_ALMS           EQU (0x1 <<  0) ;- (RTTC) Real-time Alarm Status
+AT91C_RTTC_RTTINC         EQU (0x1 <<  1) ;- (RTTC) Real-time Timer Increment
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
+// - *****************************************************************************
+// - -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
+AT91C_PITC_PIV            EQU (0xFFFFF <<  0) ;- (PITC) Periodic Interval Value
+AT91C_PITC_PITEN          EQU (0x1 << 24) ;- (PITC) Periodic Interval Timer Enabled
+AT91C_PITC_PITIEN         EQU (0x1 << 25) ;- (PITC) Periodic Interval Timer Interrupt Enable
+// - -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
+AT91C_PITC_PITS           EQU (0x1 <<  0) ;- (PITC) Periodic Interval Timer Status
+// - -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
+AT91C_PITC_CPIV           EQU (0xFFFFF <<  0) ;- (PITC) Current Periodic Interval Value
+AT91C_PITC_PICNT          EQU (0xFFF << 20) ;- (PITC) Periodic Interval Counter
+// - -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
+// - *****************************************************************************
+// - -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 
+AT91C_WDTC_WDRSTT         EQU (0x1 <<  0) ;- (WDTC) Watchdog Restart
+AT91C_WDTC_KEY            EQU (0xFF << 24) ;- (WDTC) Watchdog KEY Password
+// - -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 
+AT91C_WDTC_WDV            EQU (0xFFF <<  0) ;- (WDTC) Watchdog Timer Restart
+AT91C_WDTC_WDFIEN         EQU (0x1 << 12) ;- (WDTC) Watchdog Fault Interrupt Enable
+AT91C_WDTC_WDRSTEN        EQU (0x1 << 13) ;- (WDTC) Watchdog Reset Enable
+AT91C_WDTC_WDRPROC        EQU (0x1 << 14) ;- (WDTC) Watchdog Timer Restart
+AT91C_WDTC_WDDIS          EQU (0x1 << 15) ;- (WDTC) Watchdog Disable
+AT91C_WDTC_WDD            EQU (0xFFF << 16) ;- (WDTC) Watchdog Delta Value
+AT91C_WDTC_WDDBGHLT       EQU (0x1 << 28) ;- (WDTC) Watchdog Debug Halt
+AT91C_WDTC_WDIDLEHLT      EQU (0x1 << 29) ;- (WDTC) Watchdog Idle Halt
+// - -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 
+AT91C_WDTC_WDUNF          EQU (0x1 <<  0) ;- (WDTC) Watchdog Underflow
+AT91C_WDTC_WDERR          EQU (0x1 <<  1) ;- (WDTC) Watchdog Error
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface
+// - *****************************************************************************
+// - -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- 
+AT91C_VREG_PSTDBY         EQU (0x1 <<  0) ;- (VREG) Voltage Regulator Power Standby Mode
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Memory Controller Interface
+// - *****************************************************************************
+// - -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 
+AT91C_MC_RCB              EQU (0x1 <<  0) ;- (MC) Remap Command Bit
+// - -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 
+AT91C_MC_UNDADD           EQU (0x1 <<  0) ;- (MC) Undefined Addess Abort Status
+AT91C_MC_MISADD           EQU (0x1 <<  1) ;- (MC) Misaligned Addess Abort Status
+AT91C_MC_ABTSZ            EQU (0x3 <<  8) ;- (MC) Abort Size Status
+AT91C_MC_ABTSZ_BYTE       EQU (0x0 <<  8) ;- (MC) Byte
+AT91C_MC_ABTSZ_HWORD      EQU (0x1 <<  8) ;- (MC) Half-word
+AT91C_MC_ABTSZ_WORD       EQU (0x2 <<  8) ;- (MC) Word
+AT91C_MC_ABTTYP           EQU (0x3 << 10) ;- (MC) Abort Type Status
+AT91C_MC_ABTTYP_DATAR     EQU (0x0 << 10) ;- (MC) Data Read
+AT91C_MC_ABTTYP_DATAW     EQU (0x1 << 10) ;- (MC) Data Write
+AT91C_MC_ABTTYP_FETCH     EQU (0x2 << 10) ;- (MC) Code Fetch
+AT91C_MC_MST0             EQU (0x1 << 16) ;- (MC) Master 0 Abort Source
+AT91C_MC_MST1             EQU (0x1 << 17) ;- (MC) Master 1 Abort Source
+AT91C_MC_SVMST0           EQU (0x1 << 24) ;- (MC) Saved Master 0 Abort Source
+AT91C_MC_SVMST1           EQU (0x1 << 25) ;- (MC) Saved Master 1 Abort Source
+// - -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- 
+AT91C_MC_FRDY             EQU (0x1 <<  0) ;- (MC) Flash Ready
+AT91C_MC_LOCKE            EQU (0x1 <<  2) ;- (MC) Lock Error
+AT91C_MC_PROGE            EQU (0x1 <<  3) ;- (MC) Programming Error
+AT91C_MC_NEBP             EQU (0x1 <<  7) ;- (MC) No Erase Before Programming
+AT91C_MC_FWS              EQU (0x3 <<  8) ;- (MC) Flash Wait State
+AT91C_MC_FWS_0FWS         EQU (0x0 <<  8) ;- (MC) 1 cycle for Read, 2 for Write operations
+AT91C_MC_FWS_1FWS         EQU (0x1 <<  8) ;- (MC) 2 cycles for Read, 3 for Write operations
+AT91C_MC_FWS_2FWS         EQU (0x2 <<  8) ;- (MC) 3 cycles for Read, 4 for Write operations
+AT91C_MC_FWS_3FWS         EQU (0x3 <<  8) ;- (MC) 4 cycles for Read, 4 for Write operations
+AT91C_MC_FMCN             EQU (0xFF << 16) ;- (MC) Flash Microsecond Cycle Number
+// - -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- 
+AT91C_MC_FCMD             EQU (0xF <<  0) ;- (MC) Flash Command
+AT91C_MC_FCMD_START_PROG  EQU (0x1) ;- (MC) Starts the programming of th epage specified by PAGEN.
+AT91C_MC_FCMD_LOCK        EQU (0x2) ;- (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+AT91C_MC_FCMD_PROG_AND_LOCK EQU (0x3) ;- (MC) The lock sequence automatically happens after the programming sequence is completed.
+AT91C_MC_FCMD_UNLOCK      EQU (0x4) ;- (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+AT91C_MC_FCMD_ERASE_ALL   EQU (0x8) ;- (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
+AT91C_MC_FCMD_SET_GP_NVM  EQU (0xB) ;- (MC) Set General Purpose NVM bits.
+AT91C_MC_FCMD_CLR_GP_NVM  EQU (0xD) ;- (MC) Clear General Purpose NVM bits.
+AT91C_MC_FCMD_SET_SECURITY EQU (0xF) ;- (MC) Set Security Bit.
+AT91C_MC_PAGEN            EQU (0x3FF <<  8) ;- (MC) Page Number
+AT91C_MC_KEY              EQU (0xFF << 24) ;- (MC) Writing Protect Key
+// - -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- 
+AT91C_MC_SECURITY         EQU (0x1 <<  4) ;- (MC) Security Bit Status
+AT91C_MC_GPNVM0           EQU (0x1 <<  8) ;- (MC) Sector 0 Lock Status
+AT91C_MC_GPNVM1           EQU (0x1 <<  9) ;- (MC) Sector 1 Lock Status
+AT91C_MC_GPNVM2           EQU (0x1 << 10) ;- (MC) Sector 2 Lock Status
+AT91C_MC_GPNVM3           EQU (0x1 << 11) ;- (MC) Sector 3 Lock Status
+AT91C_MC_GPNVM4           EQU (0x1 << 12) ;- (MC) Sector 4 Lock Status
+AT91C_MC_GPNVM5           EQU (0x1 << 13) ;- (MC) Sector 5 Lock Status
+AT91C_MC_GPNVM6           EQU (0x1 << 14) ;- (MC) Sector 6 Lock Status
+AT91C_MC_GPNVM7           EQU (0x1 << 15) ;- (MC) Sector 7 Lock Status
+AT91C_MC_LOCKS0           EQU (0x1 << 16) ;- (MC) Sector 0 Lock Status
+AT91C_MC_LOCKS1           EQU (0x1 << 17) ;- (MC) Sector 1 Lock Status
+AT91C_MC_LOCKS2           EQU (0x1 << 18) ;- (MC) Sector 2 Lock Status
+AT91C_MC_LOCKS3           EQU (0x1 << 19) ;- (MC) Sector 3 Lock Status
+AT91C_MC_LOCKS4           EQU (0x1 << 20) ;- (MC) Sector 4 Lock Status
+AT91C_MC_LOCKS5           EQU (0x1 << 21) ;- (MC) Sector 5 Lock Status
+AT91C_MC_LOCKS6           EQU (0x1 << 22) ;- (MC) Sector 6 Lock Status
+AT91C_MC_LOCKS7           EQU (0x1 << 23) ;- (MC) Sector 7 Lock Status
+AT91C_MC_LOCKS8           EQU (0x1 << 24) ;- (MC) Sector 8 Lock Status
+AT91C_MC_LOCKS9           EQU (0x1 << 25) ;- (MC) Sector 9 Lock Status
+AT91C_MC_LOCKS10          EQU (0x1 << 26) ;- (MC) Sector 10 Lock Status
+AT91C_MC_LOCKS11          EQU (0x1 << 27) ;- (MC) Sector 11 Lock Status
+AT91C_MC_LOCKS12          EQU (0x1 << 28) ;- (MC) Sector 12 Lock Status
+AT91C_MC_LOCKS13          EQU (0x1 << 29) ;- (MC) Sector 13 Lock Status
+AT91C_MC_LOCKS14          EQU (0x1 << 30) ;- (MC) Sector 14 Lock Status
+AT91C_MC_LOCKS15          EQU (0x1 << 31) ;- (MC) Sector 15 Lock Status
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
+// - *****************************************************************************
+// - -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
+AT91C_SPI_SPIEN           EQU (0x1 <<  0) ;- (SPI) SPI Enable
+AT91C_SPI_SPIDIS          EQU (0x1 <<  1) ;- (SPI) SPI Disable
+AT91C_SPI_SWRST           EQU (0x1 <<  7) ;- (SPI) SPI Software reset
+AT91C_SPI_LASTXFER        EQU (0x1 << 24) ;- (SPI) SPI Last Transfer
+// - -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
+AT91C_SPI_MSTR            EQU (0x1 <<  0) ;- (SPI) Master/Slave Mode
+AT91C_SPI_PS              EQU (0x1 <<  1) ;- (SPI) Peripheral Select
+AT91C_SPI_PS_FIXED        EQU (0x0 <<  1) ;- (SPI) Fixed Peripheral Select
+AT91C_SPI_PS_VARIABLE     EQU (0x1 <<  1) ;- (SPI) Variable Peripheral Select
+AT91C_SPI_PCSDEC          EQU (0x1 <<  2) ;- (SPI) Chip Select Decode
+AT91C_SPI_FDIV            EQU (0x1 <<  3) ;- (SPI) Clock Selection
+AT91C_SPI_MODFDIS         EQU (0x1 <<  4) ;- (SPI) Mode Fault Detection
+AT91C_SPI_LLB             EQU (0x1 <<  7) ;- (SPI) Clock Selection
+AT91C_SPI_PCS             EQU (0xF << 16) ;- (SPI) Peripheral Chip Select
+AT91C_SPI_DLYBCS          EQU (0xFF << 24) ;- (SPI) Delay Between Chip Selects
+// - -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
+AT91C_SPI_RD              EQU (0xFFFF <<  0) ;- (SPI) Receive Data
+AT91C_SPI_RPCS            EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status
+// - -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
+AT91C_SPI_TD              EQU (0xFFFF <<  0) ;- (SPI) Transmit Data
+AT91C_SPI_TPCS            EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status
+// - -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
+AT91C_SPI_RDRF            EQU (0x1 <<  0) ;- (SPI) Receive Data Register Full
+AT91C_SPI_TDRE            EQU (0x1 <<  1) ;- (SPI) Transmit Data Register Empty
+AT91C_SPI_MODF            EQU (0x1 <<  2) ;- (SPI) Mode Fault Error
+AT91C_SPI_OVRES           EQU (0x1 <<  3) ;- (SPI) Overrun Error Status
+AT91C_SPI_ENDRX           EQU (0x1 <<  4) ;- (SPI) End of Receiver Transfer
+AT91C_SPI_ENDTX           EQU (0x1 <<  5) ;- (SPI) End of Receiver Transfer
+AT91C_SPI_RXBUFF          EQU (0x1 <<  6) ;- (SPI) RXBUFF Interrupt
+AT91C_SPI_TXBUFE          EQU (0x1 <<  7) ;- (SPI) TXBUFE Interrupt
+AT91C_SPI_NSSR            EQU (0x1 <<  8) ;- (SPI) NSSR Interrupt
+AT91C_SPI_TXEMPTY         EQU (0x1 <<  9) ;- (SPI) TXEMPTY Interrupt
+AT91C_SPI_SPIENS          EQU (0x1 << 16) ;- (SPI) Enable Status
+// - -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
+// - -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
+// - -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
+// - -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
+AT91C_SPI_CPOL            EQU (0x1 <<  0) ;- (SPI) Clock Polarity
+AT91C_SPI_NCPHA           EQU (0x1 <<  1) ;- (SPI) Clock Phase
+AT91C_SPI_CSAAT           EQU (0x1 <<  3) ;- (SPI) Chip Select Active After Transfer
+AT91C_SPI_BITS            EQU (0xF <<  4) ;- (SPI) Bits Per Transfer
+AT91C_SPI_BITS_8          EQU (0x0 <<  4) ;- (SPI) 8 Bits Per transfer
+AT91C_SPI_BITS_9          EQU (0x1 <<  4) ;- (SPI) 9 Bits Per transfer
+AT91C_SPI_BITS_10         EQU (0x2 <<  4) ;- (SPI) 10 Bits Per transfer
+AT91C_SPI_BITS_11         EQU (0x3 <<  4) ;- (SPI) 11 Bits Per transfer
+AT91C_SPI_BITS_12         EQU (0x4 <<  4) ;- (SPI) 12 Bits Per transfer
+AT91C_SPI_BITS_13         EQU (0x5 <<  4) ;- (SPI) 13 Bits Per transfer
+AT91C_SPI_BITS_14         EQU (0x6 <<  4) ;- (SPI) 14 Bits Per transfer
+AT91C_SPI_BITS_15         EQU (0x7 <<  4) ;- (SPI) 15 Bits Per transfer
+AT91C_SPI_BITS_16         EQU (0x8 <<  4) ;- (SPI) 16 Bits Per transfer
+AT91C_SPI_SCBR            EQU (0xFF <<  8) ;- (SPI) Serial Clock Baud Rate
+AT91C_SPI_DLYBS           EQU (0xFF << 16) ;- (SPI) Delay Before SPCK
+AT91C_SPI_DLYBCT          EQU (0xFF << 24) ;- (SPI) Delay Between Consecutive Transfers
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Usart
+// - *****************************************************************************
+// - -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
+AT91C_US_STTBRK           EQU (0x1 <<  9) ;- (USART) Start Break
+AT91C_US_STPBRK           EQU (0x1 << 10) ;- (USART) Stop Break
+AT91C_US_STTTO            EQU (0x1 << 11) ;- (USART) Start Time-out
+AT91C_US_SENDA            EQU (0x1 << 12) ;- (USART) Send Address
+AT91C_US_RSTIT            EQU (0x1 << 13) ;- (USART) Reset Iterations
+AT91C_US_RSTNACK          EQU (0x1 << 14) ;- (USART) Reset Non Acknowledge
+AT91C_US_RETTO            EQU (0x1 << 15) ;- (USART) Rearm Time-out
+AT91C_US_DTREN            EQU (0x1 << 16) ;- (USART) Data Terminal ready Enable
+AT91C_US_DTRDIS           EQU (0x1 << 17) ;- (USART) Data Terminal ready Disable
+AT91C_US_RTSEN            EQU (0x1 << 18) ;- (USART) Request to Send enable
+AT91C_US_RTSDIS           EQU (0x1 << 19) ;- (USART) Request to Send Disable
+// - -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
+AT91C_US_USMODE           EQU (0xF <<  0) ;- (USART) Usart mode
+AT91C_US_USMODE_NORMAL    EQU (0x0) ;- (USART) Normal
+AT91C_US_USMODE_RS485     EQU (0x1) ;- (USART) RS485
+AT91C_US_USMODE_HWHSH     EQU (0x2) ;- (USART) Hardware Handshaking
+AT91C_US_USMODE_MODEM     EQU (0x3) ;- (USART) Modem
+AT91C_US_USMODE_ISO7816_0 EQU (0x4) ;- (USART) ISO7816 protocol: T = 0
+AT91C_US_USMODE_ISO7816_1 EQU (0x6) ;- (USART) ISO7816 protocol: T = 1
+AT91C_US_USMODE_IRDA      EQU (0x8) ;- (USART) IrDA
+AT91C_US_USMODE_SWHSH     EQU (0xC) ;- (USART) Software Handshaking
+AT91C_US_CLKS             EQU (0x3 <<  4) ;- (USART) Clock Selection (Baud Rate generator Input Clock
+AT91C_US_CLKS_CLOCK       EQU (0x0 <<  4) ;- (USART) Clock
+AT91C_US_CLKS_FDIV1       EQU (0x1 <<  4) ;- (USART) fdiv1
+AT91C_US_CLKS_SLOW        EQU (0x2 <<  4) ;- (USART) slow_clock (ARM)
+AT91C_US_CLKS_EXT         EQU (0x3 <<  4) ;- (USART) External (SCK)
+AT91C_US_CHRL             EQU (0x3 <<  6) ;- (USART) Clock Selection (Baud Rate generator Input Clock
+AT91C_US_CHRL_5_BITS      EQU (0x0 <<  6) ;- (USART) Character Length: 5 bits
+AT91C_US_CHRL_6_BITS      EQU (0x1 <<  6) ;- (USART) Character Length: 6 bits
+AT91C_US_CHRL_7_BITS      EQU (0x2 <<  6) ;- (USART) Character Length: 7 bits
+AT91C_US_CHRL_8_BITS      EQU (0x3 <<  6) ;- (USART) Character Length: 8 bits
+AT91C_US_SYNC             EQU (0x1 <<  8) ;- (USART) Synchronous Mode Select
+AT91C_US_NBSTOP           EQU (0x3 << 12) ;- (USART) Number of Stop bits
+AT91C_US_NBSTOP_1_BIT     EQU (0x0 << 12) ;- (USART) 1 stop bit
+AT91C_US_NBSTOP_15_BIT    EQU (0x1 << 12) ;- (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+AT91C_US_NBSTOP_2_BIT     EQU (0x2 << 12) ;- (USART) 2 stop bits
+AT91C_US_MSBF             EQU (0x1 << 16) ;- (USART) Bit Order
+AT91C_US_MODE9            EQU (0x1 << 17) ;- (USART) 9-bit Character length
+AT91C_US_CKLO             EQU (0x1 << 18) ;- (USART) Clock Output Select
+AT91C_US_OVER             EQU (0x1 << 19) ;- (USART) Over Sampling Mode
+AT91C_US_INACK            EQU (0x1 << 20) ;- (USART) Inhibit Non Acknowledge
+AT91C_US_DSNACK           EQU (0x1 << 21) ;- (USART) Disable Successive NACK
+AT91C_US_MAX_ITER         EQU (0x1 << 24) ;- (USART) Number of Repetitions
+AT91C_US_FILTER           EQU (0x1 << 28) ;- (USART) Receive Line Filter
+// - -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+AT91C_US_RXBRK            EQU (0x1 <<  2) ;- (USART) Break Received/End of Break
+AT91C_US_TIMEOUT          EQU (0x1 <<  8) ;- (USART) Receiver Time-out
+AT91C_US_ITERATION        EQU (0x1 << 10) ;- (USART) Max number of Repetitions Reached
+AT91C_US_NACK             EQU (0x1 << 13) ;- (USART) Non Acknowledge
+AT91C_US_RIIC             EQU (0x1 << 16) ;- (USART) Ring INdicator Input Change Flag
+AT91C_US_DSRIC            EQU (0x1 << 17) ;- (USART) Data Set Ready Input Change Flag
+AT91C_US_DCDIC            EQU (0x1 << 18) ;- (USART) Data Carrier Flag
+AT91C_US_CTSIC            EQU (0x1 << 19) ;- (USART) Clear To Send Input Change Flag
+// - -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// - -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// - -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 
+AT91C_US_RI               EQU (0x1 << 20) ;- (USART) Image of RI Input
+AT91C_US_DSR              EQU (0x1 << 21) ;- (USART) Image of DSR Input
+AT91C_US_DCD              EQU (0x1 << 22) ;- (USART) Image of DCD Input
+AT91C_US_CTS              EQU (0x1 << 23) ;- (USART) Image of CTS Input
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
+// - *****************************************************************************
+// - -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
+AT91C_SSC_RXEN            EQU (0x1 <<  0) ;- (SSC) Receive Enable
+AT91C_SSC_RXDIS           EQU (0x1 <<  1) ;- (SSC) Receive Disable
+AT91C_SSC_TXEN            EQU (0x1 <<  8) ;- (SSC) Transmit Enable
+AT91C_SSC_TXDIS           EQU (0x1 <<  9) ;- (SSC) Transmit Disable
+AT91C_SSC_SWRST           EQU (0x1 << 15) ;- (SSC) Software Reset
+// - -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
+AT91C_SSC_CKS             EQU (0x3 <<  0) ;- (SSC) Receive/Transmit Clock Selection
+AT91C_SSC_CKS_DIV         EQU (0x0) ;- (SSC) Divided Clock
+AT91C_SSC_CKS_TK          EQU (0x1) ;- (SSC) TK Clock signal
+AT91C_SSC_CKS_RK          EQU (0x2) ;- (SSC) RK pin
+AT91C_SSC_CKO             EQU (0x7 <<  2) ;- (SSC) Receive/Transmit Clock Output Mode Selection
+AT91C_SSC_CKO_NONE        EQU (0x0 <<  2) ;- (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+AT91C_SSC_CKO_CONTINOUS   EQU (0x1 <<  2) ;- (SSC) Continuous Receive/Transmit Clock RK pin: Output
+AT91C_SSC_CKO_DATA_TX     EQU (0x2 <<  2) ;- (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+AT91C_SSC_CKI             EQU (0x1 <<  5) ;- (SSC) Receive/Transmit Clock Inversion
+AT91C_SSC_START           EQU (0xF <<  8) ;- (SSC) Receive/Transmit Start Selection
+AT91C_SSC_START_CONTINOUS EQU (0x0 <<  8) ;- (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+AT91C_SSC_START_TX        EQU (0x1 <<  8) ;- (SSC) Transmit/Receive start
+AT91C_SSC_START_LOW_RF    EQU (0x2 <<  8) ;- (SSC) Detection of a low level on RF input
+AT91C_SSC_START_HIGH_RF   EQU (0x3 <<  8) ;- (SSC) Detection of a high level on RF input
+AT91C_SSC_START_FALL_RF   EQU (0x4 <<  8) ;- (SSC) Detection of a falling edge on RF input
+AT91C_SSC_START_RISE_RF   EQU (0x5 <<  8) ;- (SSC) Detection of a rising edge on RF input
+AT91C_SSC_START_LEVEL_RF  EQU (0x6 <<  8) ;- (SSC) Detection of any level change on RF input
+AT91C_SSC_START_EDGE_RF   EQU (0x7 <<  8) ;- (SSC) Detection of any edge on RF input
+AT91C_SSC_START_0         EQU (0x8 <<  8) ;- (SSC) Compare 0
+AT91C_SSC_STTDLY          EQU (0xFF << 16) ;- (SSC) Receive/Transmit Start Delay
+AT91C_SSC_PERIOD          EQU (0xFF << 24) ;- (SSC) Receive/Transmit Period Divider Selection
+// - -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
+AT91C_SSC_DATLEN          EQU (0x1F <<  0) ;- (SSC) Data Length
+AT91C_SSC_LOOP            EQU (0x1 <<  5) ;- (SSC) Loop Mode
+AT91C_SSC_MSBF            EQU (0x1 <<  7) ;- (SSC) Most Significant Bit First
+AT91C_SSC_DATNB           EQU (0xF <<  8) ;- (SSC) Data Number per Frame
+AT91C_SSC_FSLEN           EQU (0xF << 16) ;- (SSC) Receive/Transmit Frame Sync length
+AT91C_SSC_FSOS            EQU (0x7 << 20) ;- (SSC) Receive/Transmit Frame Sync Output Selection
+AT91C_SSC_FSOS_NONE       EQU (0x0 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+AT91C_SSC_FSOS_NEGATIVE   EQU (0x1 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+AT91C_SSC_FSOS_POSITIVE   EQU (0x2 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+AT91C_SSC_FSOS_LOW        EQU (0x3 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+AT91C_SSC_FSOS_HIGH       EQU (0x4 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+AT91C_SSC_FSOS_TOGGLE     EQU (0x5 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+AT91C_SSC_FSEDGE          EQU (0x1 << 24) ;- (SSC) Frame Sync Edge Detection
+// - -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
+// - -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
+AT91C_SSC_DATDEF          EQU (0x1 <<  5) ;- (SSC) Data Default Value
+AT91C_SSC_FSDEN           EQU (0x1 << 23) ;- (SSC) Frame Sync Data Enable
+// - -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
+AT91C_SSC_TXRDY           EQU (0x1 <<  0) ;- (SSC) Transmit Ready
+AT91C_SSC_TXEMPTY         EQU (0x1 <<  1) ;- (SSC) Transmit Empty
+AT91C_SSC_ENDTX           EQU (0x1 <<  2) ;- (SSC) End Of Transmission
+AT91C_SSC_TXBUFE          EQU (0x1 <<  3) ;- (SSC) Transmit Buffer Empty
+AT91C_SSC_RXRDY           EQU (0x1 <<  4) ;- (SSC) Receive Ready
+AT91C_SSC_OVRUN           EQU (0x1 <<  5) ;- (SSC) Receive Overrun
+AT91C_SSC_ENDRX           EQU (0x1 <<  6) ;- (SSC) End of Reception
+AT91C_SSC_RXBUFF          EQU (0x1 <<  7) ;- (SSC) Receive Buffer Full
+AT91C_SSC_TXSYN           EQU (0x1 << 10) ;- (SSC) Transmit Sync
+AT91C_SSC_RXSYN           EQU (0x1 << 11) ;- (SSC) Receive Sync
+AT91C_SSC_TXENA           EQU (0x1 << 16) ;- (SSC) Transmit Enable
+AT91C_SSC_RXENA           EQU (0x1 << 17) ;- (SSC) Receive Enable
+// - -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
+// - -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
+// - -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Two-wire Interface
+// - *****************************************************************************
+// - -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
+AT91C_TWI_START           EQU (0x1 <<  0) ;- (TWI) Send a START Condition
+AT91C_TWI_STOP            EQU (0x1 <<  1) ;- (TWI) Send a STOP Condition
+AT91C_TWI_MSEN            EQU (0x1 <<  2) ;- (TWI) TWI Master Transfer Enabled
+AT91C_TWI_MSDIS           EQU (0x1 <<  3) ;- (TWI) TWI Master Transfer Disabled
+AT91C_TWI_SWRST           EQU (0x1 <<  7) ;- (TWI) Software Reset
+// - -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
+AT91C_TWI_IADRSZ          EQU (0x3 <<  8) ;- (TWI) Internal Device Address Size
+AT91C_TWI_IADRSZ_NO       EQU (0x0 <<  8) ;- (TWI) No internal device address
+AT91C_TWI_IADRSZ_1_BYTE   EQU (0x1 <<  8) ;- (TWI) One-byte internal device address
+AT91C_TWI_IADRSZ_2_BYTE   EQU (0x2 <<  8) ;- (TWI) Two-byte internal device address
+AT91C_TWI_IADRSZ_3_BYTE   EQU (0x3 <<  8) ;- (TWI) Three-byte internal device address
+AT91C_TWI_MREAD           EQU (0x1 << 12) ;- (TWI) Master Read Direction
+AT91C_TWI_DADR            EQU (0x7F << 16) ;- (TWI) Device Address
+// - -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
+AT91C_TWI_CLDIV           EQU (0xFF <<  0) ;- (TWI) Clock Low Divider
+AT91C_TWI_CHDIV           EQU (0xFF <<  8) ;- (TWI) Clock High Divider
+AT91C_TWI_CKDIV           EQU (0x7 << 16) ;- (TWI) Clock Divider
+// - -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
+AT91C_TWI_TXCOMP          EQU (0x1 <<  0) ;- (TWI) Transmission Completed
+AT91C_TWI_RXRDY           EQU (0x1 <<  1) ;- (TWI) Receive holding register ReaDY
+AT91C_TWI_TXRDY           EQU (0x1 <<  2) ;- (TWI) Transmit holding register ReaDY
+AT91C_TWI_OVRE            EQU (0x1 <<  6) ;- (TWI) Overrun Error
+AT91C_TWI_UNRE            EQU (0x1 <<  7) ;- (TWI) Underrun Error
+AT91C_TWI_NACK            EQU (0x1 <<  8) ;- (TWI) Not Acknowledged
+// - -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
+// - -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
+// - -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
+// - *****************************************************************************
+// - -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- 
+AT91C_PWMC_CPRE           EQU (0xF <<  0) ;- (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
+AT91C_PWMC_CPRE_MCK       EQU (0x0) ;- (PWMC_CH) 
+AT91C_PWMC_CPRE_MCKA      EQU (0xB) ;- (PWMC_CH) 
+AT91C_PWMC_CPRE_MCKB      EQU (0xC) ;- (PWMC_CH) 
+AT91C_PWMC_CALG           EQU (0x1 <<  8) ;- (PWMC_CH) Channel Alignment
+AT91C_PWMC_CPOL           EQU (0x1 <<  9) ;- (PWMC_CH) Channel Polarity
+AT91C_PWMC_CPD            EQU (0x1 << 10) ;- (PWMC_CH) Channel Update Period
+// - -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- 
+AT91C_PWMC_CDTY           EQU (0x0 <<  0) ;- (PWMC_CH) Channel Duty Cycle
+// - -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- 
+AT91C_PWMC_CPRD           EQU (0x0 <<  0) ;- (PWMC_CH) Channel Period
+// - -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- 
+AT91C_PWMC_CCNT           EQU (0x0 <<  0) ;- (PWMC_CH) Channel Counter
+// - -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- 
+AT91C_PWMC_CUPD           EQU (0x0 <<  0) ;- (PWMC_CH) Channel Update
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
+// - *****************************************************************************
+// - -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- 
+AT91C_PWMC_DIVA           EQU (0xFF <<  0) ;- (PWMC) CLKA divide factor.
+AT91C_PWMC_PREA           EQU (0xF <<  8) ;- (PWMC) Divider Input Clock Prescaler A
+AT91C_PWMC_PREA_MCK       EQU (0x0 <<  8) ;- (PWMC) 
+AT91C_PWMC_DIVB           EQU (0xFF << 16) ;- (PWMC) CLKB divide factor.
+AT91C_PWMC_PREB           EQU (0xF << 24) ;- (PWMC) Divider Input Clock Prescaler B
+AT91C_PWMC_PREB_MCK       EQU (0x0 << 24) ;- (PWMC) 
+// - -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- 
+AT91C_PWMC_CHID0          EQU (0x1 <<  0) ;- (PWMC) Channel ID 0
+AT91C_PWMC_CHID1          EQU (0x1 <<  1) ;- (PWMC) Channel ID 1
+AT91C_PWMC_CHID2          EQU (0x1 <<  2) ;- (PWMC) Channel ID 2
+AT91C_PWMC_CHID3          EQU (0x1 <<  3) ;- (PWMC) Channel ID 3
+// - -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- 
+// - -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- 
+// - -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- 
+// - -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- 
+// - -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- 
+// - -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR USB Device Interface
+// - *****************************************************************************
+// - -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
+AT91C_UDP_FRM_NUM         EQU (0x7FF <<  0) ;- (UDP) Frame Number as Defined in the Packet Field Formats
+AT91C_UDP_FRM_ERR         EQU (0x1 << 16) ;- (UDP) Frame Error
+AT91C_UDP_FRM_OK          EQU (0x1 << 17) ;- (UDP) Frame OK
+// - -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
+AT91C_UDP_FADDEN          EQU (0x1 <<  0) ;- (UDP) Function Address Enable
+AT91C_UDP_CONFG           EQU (0x1 <<  1) ;- (UDP) Configured
+AT91C_UDP_ESR             EQU (0x1 <<  2) ;- (UDP) Enable Send Resume
+AT91C_UDP_RSMINPR         EQU (0x1 <<  3) ;- (UDP) A Resume Has Been Sent to the Host
+AT91C_UDP_RMWUPE          EQU (0x1 <<  4) ;- (UDP) Remote Wake Up Enable
+// - -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
+AT91C_UDP_FADD            EQU (0xFF <<  0) ;- (UDP) Function Address Value
+AT91C_UDP_FEN             EQU (0x1 <<  8) ;- (UDP) Function Enable
+// - -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 
+AT91C_UDP_EPINT0          EQU (0x1 <<  0) ;- (UDP) Endpoint 0 Interrupt
+AT91C_UDP_EPINT1          EQU (0x1 <<  1) ;- (UDP) Endpoint 0 Interrupt
+AT91C_UDP_EPINT2          EQU (0x1 <<  2) ;- (UDP) Endpoint 2 Interrupt
+AT91C_UDP_EPINT3          EQU (0x1 <<  3) ;- (UDP) Endpoint 3 Interrupt
+AT91C_UDP_EPINT4          EQU (0x1 <<  4) ;- (UDP) Endpoint 4 Interrupt
+AT91C_UDP_EPINT5          EQU (0x1 <<  5) ;- (UDP) Endpoint 5 Interrupt
+AT91C_UDP_RXSUSP          EQU (0x1 <<  8) ;- (UDP) USB Suspend Interrupt
+AT91C_UDP_RXRSM           EQU (0x1 <<  9) ;- (UDP) USB Resume Interrupt
+AT91C_UDP_EXTRSM          EQU (0x1 << 10) ;- (UDP) USB External Resume Interrupt
+AT91C_UDP_SOFINT          EQU (0x1 << 11) ;- (UDP) USB Start Of frame Interrupt
+AT91C_UDP_WAKEUP          EQU (0x1 << 13) ;- (UDP) USB Resume Interrupt
+// - -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 
+// - -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 
+// - -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 
+AT91C_UDP_ENDBUSRES       EQU (0x1 << 12) ;- (UDP) USB End Of Bus Reset Interrupt
+// - -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 
+// - -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 
+AT91C_UDP_EP0             EQU (0x1 <<  0) ;- (UDP) Reset Endpoint 0
+AT91C_UDP_EP1             EQU (0x1 <<  1) ;- (UDP) Reset Endpoint 1
+AT91C_UDP_EP2             EQU (0x1 <<  2) ;- (UDP) Reset Endpoint 2
+AT91C_UDP_EP3             EQU (0x1 <<  3) ;- (UDP) Reset Endpoint 3
+AT91C_UDP_EP4             EQU (0x1 <<  4) ;- (UDP) Reset Endpoint 4
+AT91C_UDP_EP5             EQU (0x1 <<  5) ;- (UDP) Reset Endpoint 5
+// - -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 
+AT91C_UDP_TXCOMP          EQU (0x1 <<  0) ;- (UDP) Generates an IN packet with data previously written in the DPR
+AT91C_UDP_RX_DATA_BK0     EQU (0x1 <<  1) ;- (UDP) Receive Data Bank 0
+AT91C_UDP_RXSETUP         EQU (0x1 <<  2) ;- (UDP) Sends STALL to the Host (Control endpoints)
+AT91C_UDP_ISOERROR        EQU (0x1 <<  3) ;- (UDP) Isochronous error (Isochronous endpoints)
+AT91C_UDP_TXPKTRDY        EQU (0x1 <<  4) ;- (UDP) Transmit Packet Ready
+AT91C_UDP_FORCESTALL      EQU (0x1 <<  5) ;- (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
+AT91C_UDP_RX_DATA_BK1     EQU (0x1 <<  6) ;- (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
+AT91C_UDP_DIR             EQU (0x1 <<  7) ;- (UDP) Transfer Direction
+AT91C_UDP_EPTYPE          EQU (0x7 <<  8) ;- (UDP) Endpoint type
+AT91C_UDP_EPTYPE_CTRL     EQU (0x0 <<  8) ;- (UDP) Control
+AT91C_UDP_EPTYPE_ISO_OUT  EQU (0x1 <<  8) ;- (UDP) Isochronous OUT
+AT91C_UDP_EPTYPE_BULK_OUT EQU (0x2 <<  8) ;- (UDP) Bulk OUT
+AT91C_UDP_EPTYPE_INT_OUT  EQU (0x3 <<  8) ;- (UDP) Interrupt OUT
+AT91C_UDP_EPTYPE_ISO_IN   EQU (0x5 <<  8) ;- (UDP) Isochronous IN
+AT91C_UDP_EPTYPE_BULK_IN  EQU (0x6 <<  8) ;- (UDP) Bulk IN
+AT91C_UDP_EPTYPE_INT_IN   EQU (0x7 <<  8) ;- (UDP) Interrupt IN
+AT91C_UDP_DTGLE           EQU (0x1 << 11) ;- (UDP) Data Toggle
+AT91C_UDP_EPEDS           EQU (0x1 << 15) ;- (UDP) Endpoint Enable Disable
+AT91C_UDP_RXBYTECNT       EQU (0x7FF << 16) ;- (UDP) Number Of Bytes Available in the FIFO
+// - -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- 
+AT91C_UDP_TXVDIS          EQU (0x1 <<  8) ;- (UDP) 
+AT91C_UDP_PUON            EQU (0x1 <<  9) ;- (UDP) Pull-up ON
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
+// - *****************************************************************************
+// - -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
+AT91C_TC_CLKEN            EQU (0x1 <<  0) ;- (TC) Counter Clock Enable Command
+AT91C_TC_CLKDIS           EQU (0x1 <<  1) ;- (TC) Counter Clock Disable Command
+AT91C_TC_SWTRG            EQU (0x1 <<  2) ;- (TC) Software Trigger Command
+// - -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
+AT91C_TC_CLKS             EQU (0x7 <<  0) ;- (TC) Clock Selection
+AT91C_TC_CLKS_TIMER_DIV1_CLOCK EQU (0x0) ;- (TC) Clock selected: TIMER_DIV1_CLOCK
+AT91C_TC_CLKS_TIMER_DIV2_CLOCK EQU (0x1) ;- (TC) Clock selected: TIMER_DIV2_CLOCK
+AT91C_TC_CLKS_TIMER_DIV3_CLOCK EQU (0x2) ;- (TC) Clock selected: TIMER_DIV3_CLOCK
+AT91C_TC_CLKS_TIMER_DIV4_CLOCK EQU (0x3) ;- (TC) Clock selected: TIMER_DIV4_CLOCK
+AT91C_TC_CLKS_TIMER_DIV5_CLOCK EQU (0x4) ;- (TC) Clock selected: TIMER_DIV5_CLOCK
+AT91C_TC_CLKS_XC0         EQU (0x5) ;- (TC) Clock selected: XC0
+AT91C_TC_CLKS_XC1         EQU (0x6) ;- (TC) Clock selected: XC1
+AT91C_TC_CLKS_XC2         EQU (0x7) ;- (TC) Clock selected: XC2
+AT91C_TC_CLKI             EQU (0x1 <<  3) ;- (TC) Clock Invert
+AT91C_TC_BURST            EQU (0x3 <<  4) ;- (TC) Burst Signal Selection
+AT91C_TC_BURST_NONE       EQU (0x0 <<  4) ;- (TC) The clock is not gated by an external signal
+AT91C_TC_BURST_XC0        EQU (0x1 <<  4) ;- (TC) XC0 is ANDed with the selected clock
+AT91C_TC_BURST_XC1        EQU (0x2 <<  4) ;- (TC) XC1 is ANDed with the selected clock
+AT91C_TC_BURST_XC2        EQU (0x3 <<  4) ;- (TC) XC2 is ANDed with the selected clock
+AT91C_TC_CPCSTOP          EQU (0x1 <<  6) ;- (TC) Counter Clock Stopped with RC Compare
+AT91C_TC_LDBSTOP          EQU (0x1 <<  6) ;- (TC) Counter Clock Stopped with RB Loading
+AT91C_TC_CPCDIS           EQU (0x1 <<  7) ;- (TC) Counter Clock Disable with RC Compare
+AT91C_TC_LDBDIS           EQU (0x1 <<  7) ;- (TC) Counter Clock Disabled with RB Loading
+AT91C_TC_ETRGEDG          EQU (0x3 <<  8) ;- (TC) External Trigger Edge Selection
+AT91C_TC_ETRGEDG_NONE     EQU (0x0 <<  8) ;- (TC) Edge: None
+AT91C_TC_ETRGEDG_RISING   EQU (0x1 <<  8) ;- (TC) Edge: rising edge
+AT91C_TC_ETRGEDG_FALLING  EQU (0x2 <<  8) ;- (TC) Edge: falling edge
+AT91C_TC_ETRGEDG_BOTH     EQU (0x3 <<  8) ;- (TC) Edge: each edge
+AT91C_TC_EEVTEDG          EQU (0x3 <<  8) ;- (TC) External Event Edge Selection
+AT91C_TC_EEVTEDG_NONE     EQU (0x0 <<  8) ;- (TC) Edge: None
+AT91C_TC_EEVTEDG_RISING   EQU (0x1 <<  8) ;- (TC) Edge: rising edge
+AT91C_TC_EEVTEDG_FALLING  EQU (0x2 <<  8) ;- (TC) Edge: falling edge
+AT91C_TC_EEVTEDG_BOTH     EQU (0x3 <<  8) ;- (TC) Edge: each edge
+AT91C_TC_EEVT             EQU (0x3 << 10) ;- (TC) External Event  Selection
+AT91C_TC_EEVT_TIOB        EQU (0x0 << 10) ;- (TC) Signal selected as external event: TIOB TIOB direction: input
+AT91C_TC_EEVT_XC0         EQU (0x1 << 10) ;- (TC) Signal selected as external event: XC0 TIOB direction: output
+AT91C_TC_EEVT_XC1         EQU (0x2 << 10) ;- (TC) Signal selected as external event: XC1 TIOB direction: output
+AT91C_TC_EEVT_XC2         EQU (0x3 << 10) ;- (TC) Signal selected as external event: XC2 TIOB direction: output
+AT91C_TC_ABETRG           EQU (0x1 << 10) ;- (TC) TIOA or TIOB External Trigger Selection
+AT91C_TC_ENETRG           EQU (0x1 << 12) ;- (TC) External Event Trigger enable
+AT91C_TC_WAVESEL          EQU (0x3 << 13) ;- (TC) Waveform  Selection
+AT91C_TC_WAVESEL_UP       EQU (0x0 << 13) ;- (TC) UP mode without atomatic trigger on RC Compare
+AT91C_TC_WAVESEL_UPDOWN   EQU (0x1 << 13) ;- (TC) UPDOWN mode without automatic trigger on RC Compare
+AT91C_TC_WAVESEL_UP_AUTO  EQU (0x2 << 13) ;- (TC) UP mode with automatic trigger on RC Compare
+AT91C_TC_WAVESEL_UPDOWN_AUTO EQU (0x3 << 13) ;- (TC) UPDOWN mode with automatic trigger on RC Compare
+AT91C_TC_CPCTRG           EQU (0x1 << 14) ;- (TC) RC Compare Trigger Enable
+AT91C_TC_WAVE             EQU (0x1 << 15) ;- (TC) 
+AT91C_TC_ACPA             EQU (0x3 << 16) ;- (TC) RA Compare Effect on TIOA
+AT91C_TC_ACPA_NONE        EQU (0x0 << 16) ;- (TC) Effect: none
+AT91C_TC_ACPA_SET         EQU (0x1 << 16) ;- (TC) Effect: set
+AT91C_TC_ACPA_CLEAR       EQU (0x2 << 16) ;- (TC) Effect: clear
+AT91C_TC_ACPA_TOGGLE      EQU (0x3 << 16) ;- (TC) Effect: toggle
+AT91C_TC_LDRA             EQU (0x3 << 16) ;- (TC) RA Loading Selection
+AT91C_TC_LDRA_NONE        EQU (0x0 << 16) ;- (TC) Edge: None
+AT91C_TC_LDRA_RISING      EQU (0x1 << 16) ;- (TC) Edge: rising edge of TIOA
+AT91C_TC_LDRA_FALLING     EQU (0x2 << 16) ;- (TC) Edge: falling edge of TIOA
+AT91C_TC_LDRA_BOTH        EQU (0x3 << 16) ;- (TC) Edge: each edge of TIOA
+AT91C_TC_ACPC             EQU (0x3 << 18) ;- (TC) RC Compare Effect on TIOA
+AT91C_TC_ACPC_NONE        EQU (0x0 << 18) ;- (TC) Effect: none
+AT91C_TC_ACPC_SET         EQU (0x1 << 18) ;- (TC) Effect: set
+AT91C_TC_ACPC_CLEAR       EQU (0x2 << 18) ;- (TC) Effect: clear
+AT91C_TC_ACPC_TOGGLE      EQU (0x3 << 18) ;- (TC) Effect: toggle
+AT91C_TC_LDRB             EQU (0x3 << 18) ;- (TC) RB Loading Selection
+AT91C_TC_LDRB_NONE        EQU (0x0 << 18) ;- (TC) Edge: None
+AT91C_TC_LDRB_RISING      EQU (0x1 << 18) ;- (TC) Edge: rising edge of TIOA
+AT91C_TC_LDRB_FALLING     EQU (0x2 << 18) ;- (TC) Edge: falling edge of TIOA
+AT91C_TC_LDRB_BOTH        EQU (0x3 << 18) ;- (TC) Edge: each edge of TIOA
+AT91C_TC_AEEVT            EQU (0x3 << 20) ;- (TC) External Event Effect on TIOA
+AT91C_TC_AEEVT_NONE       EQU (0x0 << 20) ;- (TC) Effect: none
+AT91C_TC_AEEVT_SET        EQU (0x1 << 20) ;- (TC) Effect: set
+AT91C_TC_AEEVT_CLEAR      EQU (0x2 << 20) ;- (TC) Effect: clear
+AT91C_TC_AEEVT_TOGGLE     EQU (0x3 << 20) ;- (TC) Effect: toggle
+AT91C_TC_ASWTRG           EQU (0x3 << 22) ;- (TC) Software Trigger Effect on TIOA
+AT91C_TC_ASWTRG_NONE      EQU (0x0 << 22) ;- (TC) Effect: none
+AT91C_TC_ASWTRG_SET       EQU (0x1 << 22) ;- (TC) Effect: set
+AT91C_TC_ASWTRG_CLEAR     EQU (0x2 << 22) ;- (TC) Effect: clear
+AT91C_TC_ASWTRG_TOGGLE    EQU (0x3 << 22) ;- (TC) Effect: toggle
+AT91C_TC_BCPB             EQU (0x3 << 24) ;- (TC) RB Compare Effect on TIOB
+AT91C_TC_BCPB_NONE        EQU (0x0 << 24) ;- (TC) Effect: none
+AT91C_TC_BCPB_SET         EQU (0x1 << 24) ;- (TC) Effect: set
+AT91C_TC_BCPB_CLEAR       EQU (0x2 << 24) ;- (TC) Effect: clear
+AT91C_TC_BCPB_TOGGLE      EQU (0x3 << 24) ;- (TC) Effect: toggle
+AT91C_TC_BCPC             EQU (0x3 << 26) ;- (TC) RC Compare Effect on TIOB
+AT91C_TC_BCPC_NONE        EQU (0x0 << 26) ;- (TC) Effect: none
+AT91C_TC_BCPC_SET         EQU (0x1 << 26) ;- (TC) Effect: set
+AT91C_TC_BCPC_CLEAR       EQU (0x2 << 26) ;- (TC) Effect: clear
+AT91C_TC_BCPC_TOGGLE      EQU (0x3 << 26) ;- (TC) Effect: toggle
+AT91C_TC_BEEVT            EQU (0x3 << 28) ;- (TC) External Event Effect on TIOB
+AT91C_TC_BEEVT_NONE       EQU (0x0 << 28) ;- (TC) Effect: none
+AT91C_TC_BEEVT_SET        EQU (0x1 << 28) ;- (TC) Effect: set
+AT91C_TC_BEEVT_CLEAR      EQU (0x2 << 28) ;- (TC) Effect: clear
+AT91C_TC_BEEVT_TOGGLE     EQU (0x3 << 28) ;- (TC) Effect: toggle
+AT91C_TC_BSWTRG           EQU (0x3 << 30) ;- (TC) Software Trigger Effect on TIOB
+AT91C_TC_BSWTRG_NONE      EQU (0x0 << 30) ;- (TC) Effect: none
+AT91C_TC_BSWTRG_SET       EQU (0x1 << 30) ;- (TC) Effect: set
+AT91C_TC_BSWTRG_CLEAR     EQU (0x2 << 30) ;- (TC) Effect: clear
+AT91C_TC_BSWTRG_TOGGLE    EQU (0x3 << 30) ;- (TC) Effect: toggle
+// - -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
+AT91C_TC_COVFS            EQU (0x1 <<  0) ;- (TC) Counter Overflow
+AT91C_TC_LOVRS            EQU (0x1 <<  1) ;- (TC) Load Overrun
+AT91C_TC_CPAS             EQU (0x1 <<  2) ;- (TC) RA Compare
+AT91C_TC_CPBS             EQU (0x1 <<  3) ;- (TC) RB Compare
+AT91C_TC_CPCS             EQU (0x1 <<  4) ;- (TC) RC Compare
+AT91C_TC_LDRAS            EQU (0x1 <<  5) ;- (TC) RA Loading
+AT91C_TC_LDRBS            EQU (0x1 <<  6) ;- (TC) RB Loading
+AT91C_TC_ETRGS            EQU (0x1 <<  7) ;- (TC) External Trigger
+AT91C_TC_CLKSTA           EQU (0x1 << 16) ;- (TC) Clock Enabling
+AT91C_TC_MTIOA            EQU (0x1 << 17) ;- (TC) TIOA Mirror
+AT91C_TC_MTIOB            EQU (0x1 << 18) ;- (TC) TIOA Mirror
+// - -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
+// - -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
+// - -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Timer Counter Interface
+// - *****************************************************************************
+// - -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
+AT91C_TCB_SYNC            EQU (0x1 <<  0) ;- (TCB) Synchro Command
+// - -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
+AT91C_TCB_TC0XC0S         EQU (0x3 <<  0) ;- (TCB) External Clock Signal 0 Selection
+AT91C_TCB_TC0XC0S_TCLK0   EQU (0x0) ;- (TCB) TCLK0 connected to XC0
+AT91C_TCB_TC0XC0S_NONE    EQU (0x1) ;- (TCB) None signal connected to XC0
+AT91C_TCB_TC0XC0S_TIOA1   EQU (0x2) ;- (TCB) TIOA1 connected to XC0
+AT91C_TCB_TC0XC0S_TIOA2   EQU (0x3) ;- (TCB) TIOA2 connected to XC0
+AT91C_TCB_TC1XC1S         EQU (0x3 <<  2) ;- (TCB) External Clock Signal 1 Selection
+AT91C_TCB_TC1XC1S_TCLK1   EQU (0x0 <<  2) ;- (TCB) TCLK1 connected to XC1
+AT91C_TCB_TC1XC1S_NONE    EQU (0x1 <<  2) ;- (TCB) None signal connected to XC1
+AT91C_TCB_TC1XC1S_TIOA0   EQU (0x2 <<  2) ;- (TCB) TIOA0 connected to XC1
+AT91C_TCB_TC1XC1S_TIOA2   EQU (0x3 <<  2) ;- (TCB) TIOA2 connected to XC1
+AT91C_TCB_TC2XC2S         EQU (0x3 <<  4) ;- (TCB) External Clock Signal 2 Selection
+AT91C_TCB_TC2XC2S_TCLK2   EQU (0x0 <<  4) ;- (TCB) TCLK2 connected to XC2
+AT91C_TCB_TC2XC2S_NONE    EQU (0x1 <<  4) ;- (TCB) None signal connected to XC2
+AT91C_TCB_TC2XC2S_TIOA0   EQU (0x2 <<  4) ;- (TCB) TIOA0 connected to XC2
+AT91C_TCB_TC2XC2S_TIOA1   EQU (0x3 <<  4) ;- (TCB) TIOA2 connected to XC2
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface
+// - *****************************************************************************
+// - -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- 
+AT91C_CAN_MTIMEMARK       EQU (0xFFFF <<  0) ;- (CAN_MB) Mailbox Timemark
+AT91C_CAN_PRIOR           EQU (0xF << 16) ;- (CAN_MB) Mailbox Priority
+AT91C_CAN_MOT             EQU (0x7 << 24) ;- (CAN_MB) Mailbox Object Type
+AT91C_CAN_MOT_DIS         EQU (0x0 << 24) ;- (CAN_MB) 
+AT91C_CAN_MOT_RX          EQU (0x1 << 24) ;- (CAN_MB) 
+AT91C_CAN_MOT_RXOVERWRITE EQU (0x2 << 24) ;- (CAN_MB) 
+AT91C_CAN_MOT_TX          EQU (0x3 << 24) ;- (CAN_MB) 
+AT91C_CAN_MOT_CONSUMER    EQU (0x4 << 24) ;- (CAN_MB) 
+AT91C_CAN_MOT_PRODUCER    EQU (0x5 << 24) ;- (CAN_MB) 
+// - -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- 
+AT91C_CAN_MIDvB           EQU (0x3FFFF <<  0) ;- (CAN_MB) Complementary bits for identifier in extended mode
+AT91C_CAN_MIDvA           EQU (0x7FF << 18) ;- (CAN_MB) Identifier for standard frame mode
+AT91C_CAN_MIDE            EQU (0x1 << 29) ;- (CAN_MB) Identifier Version
+// - -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- 
+// - -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- 
+// - -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- 
+AT91C_CAN_MTIMESTAMP      EQU (0xFFFF <<  0) ;- (CAN_MB) Timer Value
+AT91C_CAN_MDLC            EQU (0xF << 16) ;- (CAN_MB) Mailbox Data Length Code
+AT91C_CAN_MRTR            EQU (0x1 << 20) ;- (CAN_MB) Mailbox Remote Transmission Request
+AT91C_CAN_MABT            EQU (0x1 << 22) ;- (CAN_MB) Mailbox Message Abort
+AT91C_CAN_MRDY            EQU (0x1 << 23) ;- (CAN_MB) Mailbox Ready
+AT91C_CAN_MMI             EQU (0x1 << 24) ;- (CAN_MB) Mailbox Message Ignored
+// - -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- 
+// - -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- 
+// - -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- 
+AT91C_CAN_MACR            EQU (0x1 << 22) ;- (CAN_MB) Abort Request for Mailbox
+AT91C_CAN_MTCR            EQU (0x1 << 23) ;- (CAN_MB) Mailbox Transfer Command
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Control Area Network Interface
+// - *****************************************************************************
+// - -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- 
+AT91C_CAN_CANEN           EQU (0x1 <<  0) ;- (CAN) CAN Controller Enable
+AT91C_CAN_LPM             EQU (0x1 <<  1) ;- (CAN) Disable/Enable Low Power Mode
+AT91C_CAN_ABM             EQU (0x1 <<  2) ;- (CAN) Disable/Enable Autobaud/Listen Mode
+AT91C_CAN_OVL             EQU (0x1 <<  3) ;- (CAN) Disable/Enable Overload Frame
+AT91C_CAN_TEOF            EQU (0x1 <<  4) ;- (CAN) Time Stamp messages at each end of Frame
+AT91C_CAN_TTM             EQU (0x1 <<  5) ;- (CAN) Disable/Enable Time Trigger Mode
+AT91C_CAN_TIMFRZ          EQU (0x1 <<  6) ;- (CAN) Enable Timer Freeze
+AT91C_CAN_DRPT            EQU (0x1 <<  7) ;- (CAN) Disable Repeat
+// - -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- 
+AT91C_CAN_MB0             EQU (0x1 <<  0) ;- (CAN) Mailbox 0 Flag
+AT91C_CAN_MB1             EQU (0x1 <<  1) ;- (CAN) Mailbox 1 Flag
+AT91C_CAN_MB2             EQU (0x1 <<  2) ;- (CAN) Mailbox 2 Flag
+AT91C_CAN_MB3             EQU (0x1 <<  3) ;- (CAN) Mailbox 3 Flag
+AT91C_CAN_MB4             EQU (0x1 <<  4) ;- (CAN) Mailbox 4 Flag
+AT91C_CAN_MB5             EQU (0x1 <<  5) ;- (CAN) Mailbox 5 Flag
+AT91C_CAN_MB6             EQU (0x1 <<  6) ;- (CAN) Mailbox 6 Flag
+AT91C_CAN_MB7             EQU (0x1 <<  7) ;- (CAN) Mailbox 7 Flag
+AT91C_CAN_MB8             EQU (0x1 <<  8) ;- (CAN) Mailbox 8 Flag
+AT91C_CAN_MB9             EQU (0x1 <<  9) ;- (CAN) Mailbox 9 Flag
+AT91C_CAN_MB10            EQU (0x1 << 10) ;- (CAN) Mailbox 10 Flag
+AT91C_CAN_MB11            EQU (0x1 << 11) ;- (CAN) Mailbox 11 Flag
+AT91C_CAN_MB12            EQU (0x1 << 12) ;- (CAN) Mailbox 12 Flag
+AT91C_CAN_MB13            EQU (0x1 << 13) ;- (CAN) Mailbox 13 Flag
+AT91C_CAN_MB14            EQU (0x1 << 14) ;- (CAN) Mailbox 14 Flag
+AT91C_CAN_MB15            EQU (0x1 << 15) ;- (CAN) Mailbox 15 Flag
+AT91C_CAN_ERRA            EQU (0x1 << 16) ;- (CAN) Error Active Mode Flag
+AT91C_CAN_WARN            EQU (0x1 << 17) ;- (CAN) Warning Limit Flag
+AT91C_CAN_ERRP            EQU (0x1 << 18) ;- (CAN) Error Passive Mode Flag
+AT91C_CAN_BOFF            EQU (0x1 << 19) ;- (CAN) Bus Off Mode Flag
+AT91C_CAN_SLEEP           EQU (0x1 << 20) ;- (CAN) Sleep Flag
+AT91C_CAN_WAKEUP          EQU (0x1 << 21) ;- (CAN) Wakeup Flag
+AT91C_CAN_TOVF            EQU (0x1 << 22) ;- (CAN) Timer Overflow Flag
+AT91C_CAN_TSTP            EQU (0x1 << 23) ;- (CAN) Timestamp Flag
+AT91C_CAN_CERR            EQU (0x1 << 24) ;- (CAN) CRC Error
+AT91C_CAN_SERR            EQU (0x1 << 25) ;- (CAN) Stuffing Error
+AT91C_CAN_AERR            EQU (0x1 << 26) ;- (CAN) Acknowledgment Error
+AT91C_CAN_FERR            EQU (0x1 << 27) ;- (CAN) Form Error
+AT91C_CAN_BERR            EQU (0x1 << 28) ;- (CAN) Bit Error
+// - -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- 
+// - -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- 
+// - -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- 
+AT91C_CAN_RBSY            EQU (0x1 << 29) ;- (CAN) Receiver Busy
+AT91C_CAN_TBSY            EQU (0x1 << 30) ;- (CAN) Transmitter Busy
+AT91C_CAN_OVLY            EQU (0x1 << 31) ;- (CAN) Overload Busy
+// - -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- 
+AT91C_CAN_PHASE2          EQU (0x7 <<  0) ;- (CAN) Phase 2 segment
+AT91C_CAN_PHASE1          EQU (0x7 <<  4) ;- (CAN) Phase 1 segment
+AT91C_CAN_PROPAG          EQU (0x7 <<  8) ;- (CAN) Programmation time segment
+AT91C_CAN_SYNC            EQU (0x3 << 12) ;- (CAN) Re-synchronization jump width segment
+AT91C_CAN_BRP             EQU (0x7F << 16) ;- (CAN) Baudrate Prescaler
+AT91C_CAN_SMP             EQU (0x1 << 24) ;- (CAN) Sampling mode
+// - -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- 
+AT91C_CAN_TIMER           EQU (0xFFFF <<  0) ;- (CAN) Timer field
+// - -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- 
+// - -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- 
+AT91C_CAN_REC             EQU (0xFF <<  0) ;- (CAN) Receive Error Counter
+AT91C_CAN_TEC             EQU (0xFF << 16) ;- (CAN) Transmit Error Counter
+// - -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- 
+AT91C_CAN_TIMRST          EQU (0x1 << 31) ;- (CAN) Timer Reset Field
+// - -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100
+// - *****************************************************************************
+// - -------- EMAC_NCR : (EMAC Offset: 0x0)  -------- 
+AT91C_EMAC_LB             EQU (0x1 <<  0) ;- (EMAC) Loopback. Optional. When set, loopback signal is at high level.
+AT91C_EMAC_LLB            EQU (0x1 <<  1) ;- (EMAC) Loopback local. 
+AT91C_EMAC_RE             EQU (0x1 <<  2) ;- (EMAC) Receive enable. 
+AT91C_EMAC_TE             EQU (0x1 <<  3) ;- (EMAC) Transmit enable. 
+AT91C_EMAC_MPE            EQU (0x1 <<  4) ;- (EMAC) Management port enable. 
+AT91C_EMAC_CLRSTAT        EQU (0x1 <<  5) ;- (EMAC) Clear statistics registers. 
+AT91C_EMAC_INCSTAT        EQU (0x1 <<  6) ;- (EMAC) Increment statistics registers. 
+AT91C_EMAC_WESTAT         EQU (0x1 <<  7) ;- (EMAC) Write enable for statistics registers. 
+AT91C_EMAC_BP             EQU (0x1 <<  8) ;- (EMAC) Back pressure. 
+AT91C_EMAC_TSTART         EQU (0x1 <<  9) ;- (EMAC) Start Transmission. 
+AT91C_EMAC_THALT          EQU (0x1 << 10) ;- (EMAC) Transmission Halt. 
+AT91C_EMAC_TPFR           EQU (0x1 << 11) ;- (EMAC) Transmit pause frame 
+AT91C_EMAC_TZQ            EQU (0x1 << 12) ;- (EMAC) Transmit zero quantum pause frame
+// - -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- 
+AT91C_EMAC_SPD            EQU (0x1 <<  0) ;- (EMAC) Speed. 
+AT91C_EMAC_FD             EQU (0x1 <<  1) ;- (EMAC) Full duplex. 
+AT91C_EMAC_JFRAME         EQU (0x1 <<  3) ;- (EMAC) Jumbo Frames. 
+AT91C_EMAC_CAF            EQU (0x1 <<  4) ;- (EMAC) Copy all frames. 
+AT91C_EMAC_NBC            EQU (0x1 <<  5) ;- (EMAC) No broadcast. 
+AT91C_EMAC_MTI            EQU (0x1 <<  6) ;- (EMAC) Multicast hash event enable
+AT91C_EMAC_UNI            EQU (0x1 <<  7) ;- (EMAC) Unicast hash enable. 
+AT91C_EMAC_BIG            EQU (0x1 <<  8) ;- (EMAC) Receive 1522 bytes. 
+AT91C_EMAC_EAE            EQU (0x1 <<  9) ;- (EMAC) External address match enable. 
+AT91C_EMAC_CLK            EQU (0x3 << 10) ;- (EMAC) 
+AT91C_EMAC_CLK_HCLK_8     EQU (0x0 << 10) ;- (EMAC) HCLK divided by 8
+AT91C_EMAC_CLK_HCLK_16    EQU (0x1 << 10) ;- (EMAC) HCLK divided by 16
+AT91C_EMAC_CLK_HCLK_32    EQU (0x2 << 10) ;- (EMAC) HCLK divided by 32
+AT91C_EMAC_CLK_HCLK_64    EQU (0x3 << 10) ;- (EMAC) HCLK divided by 64
+AT91C_EMAC_RTY            EQU (0x1 << 12) ;- (EMAC) 
+AT91C_EMAC_PAE            EQU (0x1 << 13) ;- (EMAC) 
+AT91C_EMAC_RBOF           EQU (0x3 << 14) ;- (EMAC) 
+AT91C_EMAC_RBOF_OFFSET_0  EQU (0x0 << 14) ;- (EMAC) no offset from start of receive buffer
+AT91C_EMAC_RBOF_OFFSET_1  EQU (0x1 << 14) ;- (EMAC) one byte offset from start of receive buffer
+AT91C_EMAC_RBOF_OFFSET_2  EQU (0x2 << 14) ;- (EMAC) two bytes offset from start of receive buffer
+AT91C_EMAC_RBOF_OFFSET_3  EQU (0x3 << 14) ;- (EMAC) three bytes offset from start of receive buffer
+AT91C_EMAC_RLCE           EQU (0x1 << 16) ;- (EMAC) Receive Length field Checking Enable
+AT91C_EMAC_DRFCS          EQU (0x1 << 17) ;- (EMAC) Discard Receive FCS
+AT91C_EMAC_EFRHD          EQU (0x1 << 18) ;- (EMAC) 
+AT91C_EMAC_IRXFCS         EQU (0x1 << 19) ;- (EMAC) Ignore RX FCS
+// - -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- 
+AT91C_EMAC_LINKR          EQU (0x1 <<  0) ;- (EMAC) 
+AT91C_EMAC_MDIO           EQU (0x1 <<  1) ;- (EMAC) 
+AT91C_EMAC_IDLE           EQU (0x1 <<  2) ;- (EMAC) 
+// - -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- 
+AT91C_EMAC_UBR            EQU (0x1 <<  0) ;- (EMAC) 
+AT91C_EMAC_COL            EQU (0x1 <<  1) ;- (EMAC) 
+AT91C_EMAC_RLES           EQU (0x1 <<  2) ;- (EMAC) 
+AT91C_EMAC_TGO            EQU (0x1 <<  3) ;- (EMAC) Transmit Go
+AT91C_EMAC_BEX            EQU (0x1 <<  4) ;- (EMAC) Buffers exhausted mid frame
+AT91C_EMAC_COMP           EQU (0x1 <<  5) ;- (EMAC) 
+AT91C_EMAC_UND            EQU (0x1 <<  6) ;- (EMAC) 
+// - -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- 
+AT91C_EMAC_BNA            EQU (0x1 <<  0) ;- (EMAC) 
+AT91C_EMAC_REC            EQU (0x1 <<  1) ;- (EMAC) 
+AT91C_EMAC_OVR            EQU (0x1 <<  2) ;- (EMAC) 
+// - -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- 
+AT91C_EMAC_MFD            EQU (0x1 <<  0) ;- (EMAC) 
+AT91C_EMAC_RCOMP          EQU (0x1 <<  1) ;- (EMAC) 
+AT91C_EMAC_RXUBR          EQU (0x1 <<  2) ;- (EMAC) 
+AT91C_EMAC_TXUBR          EQU (0x1 <<  3) ;- (EMAC) 
+AT91C_EMAC_TUNDR          EQU (0x1 <<  4) ;- (EMAC) 
+AT91C_EMAC_RLEX           EQU (0x1 <<  5) ;- (EMAC) 
+AT91C_EMAC_TXERR          EQU (0x1 <<  6) ;- (EMAC) 
+AT91C_EMAC_TCOMP          EQU (0x1 <<  7) ;- (EMAC) 
+AT91C_EMAC_LINK           EQU (0x1 <<  9) ;- (EMAC) 
+AT91C_EMAC_ROVR           EQU (0x1 << 10) ;- (EMAC) 
+AT91C_EMAC_HRESP          EQU (0x1 << 11) ;- (EMAC) 
+AT91C_EMAC_PFRE           EQU (0x1 << 12) ;- (EMAC) 
+AT91C_EMAC_PTZ            EQU (0x1 << 13) ;- (EMAC) 
+// - -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- 
+// - -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- 
+// - -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- 
+// - -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- 
+AT91C_EMAC_DATA           EQU (0xFFFF <<  0) ;- (EMAC) 
+AT91C_EMAC_CODE           EQU (0x3 << 16) ;- (EMAC) 
+AT91C_EMAC_REGA           EQU (0x1F << 18) ;- (EMAC) 
+AT91C_EMAC_PHYA           EQU (0x1F << 23) ;- (EMAC) 
+AT91C_EMAC_RW             EQU (0x3 << 28) ;- (EMAC) 
+AT91C_EMAC_SOF            EQU (0x3 << 30) ;- (EMAC) 
+// - -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- 
+AT91C_EMAC_RMII           EQU (0x1 <<  0) ;- (EMAC) Reduce MII
+// - -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- 
+AT91C_EMAC_IP             EQU (0xFFFF <<  0) ;- (EMAC) ARP request IP address
+AT91C_EMAC_MAG            EQU (0x1 << 16) ;- (EMAC) Magic packet event enable
+AT91C_EMAC_ARP            EQU (0x1 << 17) ;- (EMAC) ARP request event enable
+AT91C_EMAC_SA1            EQU (0x1 << 18) ;- (EMAC) Specific address register 1 event enable
+// - -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- 
+AT91C_EMAC_REVREF         EQU (0xFFFF <<  0) ;- (EMAC) 
+AT91C_EMAC_PARTREF        EQU (0xFFFF << 16) ;- (EMAC) 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
+// - *****************************************************************************
+// - -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- 
+AT91C_ADC_SWRST           EQU (0x1 <<  0) ;- (ADC) Software Reset
+AT91C_ADC_START           EQU (0x1 <<  1) ;- (ADC) Start Conversion
+// - -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- 
+AT91C_ADC_TRGEN           EQU (0x1 <<  0) ;- (ADC) Trigger Enable
+AT91C_ADC_TRGEN_DIS       EQU (0x0) ;- (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
+AT91C_ADC_TRGEN_EN        EQU (0x1) ;- (ADC) Hardware trigger selected by TRGSEL field is enabled.
+AT91C_ADC_TRGSEL          EQU (0x7 <<  1) ;- (ADC) Trigger Selection
+AT91C_ADC_TRGSEL_TIOA0    EQU (0x0 <<  1) ;- (ADC) Selected TRGSEL = TIAO0
+AT91C_ADC_TRGSEL_TIOA1    EQU (0x1 <<  1) ;- (ADC) Selected TRGSEL = TIAO1
+AT91C_ADC_TRGSEL_TIOA2    EQU (0x2 <<  1) ;- (ADC) Selected TRGSEL = TIAO2
+AT91C_ADC_TRGSEL_TIOA3    EQU (0x3 <<  1) ;- (ADC) Selected TRGSEL = TIAO3
+AT91C_ADC_TRGSEL_TIOA4    EQU (0x4 <<  1) ;- (ADC) Selected TRGSEL = TIAO4
+AT91C_ADC_TRGSEL_TIOA5    EQU (0x5 <<  1) ;- (ADC) Selected TRGSEL = TIAO5
+AT91C_ADC_TRGSEL_EXT      EQU (0x6 <<  1) ;- (ADC) Selected TRGSEL = External Trigger
+AT91C_ADC_LOWRES          EQU (0x1 <<  4) ;- (ADC) Resolution.
+AT91C_ADC_LOWRES_10_BIT   EQU (0x0 <<  4) ;- (ADC) 10-bit resolution
+AT91C_ADC_LOWRES_8_BIT    EQU (0x1 <<  4) ;- (ADC) 8-bit resolution
+AT91C_ADC_SLEEP           EQU (0x1 <<  5) ;- (ADC) Sleep Mode
+AT91C_ADC_SLEEP_NORMAL_MODE EQU (0x0 <<  5) ;- (ADC) Normal Mode
+AT91C_ADC_SLEEP_MODE      EQU (0x1 <<  5) ;- (ADC) Sleep Mode
+AT91C_ADC_PRESCAL         EQU (0x3F <<  8) ;- (ADC) Prescaler rate selection
+AT91C_ADC_STARTUP         EQU (0x1F << 16) ;- (ADC) Startup Time
+AT91C_ADC_SHTIM           EQU (0xF << 24) ;- (ADC) Sample & Hold Time
+// - -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- 
+AT91C_ADC_CH0             EQU (0x1 <<  0) ;- (ADC) Channel 0
+AT91C_ADC_CH1             EQU (0x1 <<  1) ;- (ADC) Channel 1
+AT91C_ADC_CH2             EQU (0x1 <<  2) ;- (ADC) Channel 2
+AT91C_ADC_CH3             EQU (0x1 <<  3) ;- (ADC) Channel 3
+AT91C_ADC_CH4             EQU (0x1 <<  4) ;- (ADC) Channel 4
+AT91C_ADC_CH5             EQU (0x1 <<  5) ;- (ADC) Channel 5
+AT91C_ADC_CH6             EQU (0x1 <<  6) ;- (ADC) Channel 6
+AT91C_ADC_CH7             EQU (0x1 <<  7) ;- (ADC) Channel 7
+// - -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- 
+// - -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- 
+// - -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- 
+AT91C_ADC_EOC0            EQU (0x1 <<  0) ;- (ADC) End of Conversion
+AT91C_ADC_EOC1            EQU (0x1 <<  1) ;- (ADC) End of Conversion
+AT91C_ADC_EOC2            EQU (0x1 <<  2) ;- (ADC) End of Conversion
+AT91C_ADC_EOC3            EQU (0x1 <<  3) ;- (ADC) End of Conversion
+AT91C_ADC_EOC4            EQU (0x1 <<  4) ;- (ADC) End of Conversion
+AT91C_ADC_EOC5            EQU (0x1 <<  5) ;- (ADC) End of Conversion
+AT91C_ADC_EOC6            EQU (0x1 <<  6) ;- (ADC) End of Conversion
+AT91C_ADC_EOC7            EQU (0x1 <<  7) ;- (ADC) End of Conversion
+AT91C_ADC_OVRE0           EQU (0x1 <<  8) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE1           EQU (0x1 <<  9) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE2           EQU (0x1 << 10) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE3           EQU (0x1 << 11) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE4           EQU (0x1 << 12) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE5           EQU (0x1 << 13) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE6           EQU (0x1 << 14) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE7           EQU (0x1 << 15) ;- (ADC) Overrun Error
+AT91C_ADC_DRDY            EQU (0x1 << 16) ;- (ADC) Data Ready
+AT91C_ADC_GOVRE           EQU (0x1 << 17) ;- (ADC) General Overrun
+AT91C_ADC_ENDRX           EQU (0x1 << 18) ;- (ADC) End of Receiver Transfer
+AT91C_ADC_RXBUFF          EQU (0x1 << 19) ;- (ADC) RXBUFF Interrupt
+// - -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- 
+AT91C_ADC_LDATA           EQU (0x3FF <<  0) ;- (ADC) Last Data Converted
+// - -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- 
+// - -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- 
+// - -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- 
+// - -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- 
+AT91C_ADC_DATA            EQU (0x3FF <<  0) ;- (ADC) Converted Data
+// - -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- 
+// - -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- 
+// - -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- 
+// - -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- 
+// - -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- 
+// - -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- 
+// - -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Advanced  Encryption Standard
+// - *****************************************************************************
+// - -------- AES_CR : (AES Offset: 0x0) Control Register -------- 
+AT91C_AES_START           EQU (0x1 <<  0) ;- (AES) Starts Processing
+AT91C_AES_SWRST           EQU (0x1 <<  8) ;- (AES) Software Reset
+AT91C_AES_LOADSEED        EQU (0x1 << 16) ;- (AES) Random Number Generator Seed Loading
+// - -------- AES_MR : (AES Offset: 0x4) Mode Register -------- 
+AT91C_AES_CIPHER          EQU (0x1 <<  0) ;- (AES) Processing Mode
+AT91C_AES_PROCDLY         EQU (0xF <<  4) ;- (AES) Processing Delay
+AT91C_AES_SMOD            EQU (0x3 <<  8) ;- (AES) Start Mode
+AT91C_AES_SMOD_MANUAL     EQU (0x0 <<  8) ;- (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
+AT91C_AES_SMOD_AUTO       EQU (0x1 <<  8) ;- (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
+AT91C_AES_SMOD_PDC        EQU (0x2 <<  8) ;- (AES) PDC Mode (cf datasheet).
+AT91C_AES_OPMOD           EQU (0x7 << 12) ;- (AES) Operation Mode
+AT91C_AES_OPMOD_ECB       EQU (0x0 << 12) ;- (AES) ECB Electronic CodeBook mode.
+AT91C_AES_OPMOD_CBC       EQU (0x1 << 12) ;- (AES) CBC Cipher Block Chaining mode.
+AT91C_AES_OPMOD_OFB       EQU (0x2 << 12) ;- (AES) OFB Output Feedback mode.
+AT91C_AES_OPMOD_CFB       EQU (0x3 << 12) ;- (AES) CFB Cipher Feedback mode.
+AT91C_AES_OPMOD_CTR       EQU (0x4 << 12) ;- (AES) CTR Counter mode.
+AT91C_AES_LOD             EQU (0x1 << 15) ;- (AES) Last Output Data Mode
+AT91C_AES_CFBS            EQU (0x7 << 16) ;- (AES) Cipher Feedback Data Size
+AT91C_AES_CFBS_128_BIT    EQU (0x0 << 16) ;- (AES) 128-bit.
+AT91C_AES_CFBS_64_BIT     EQU (0x1 << 16) ;- (AES) 64-bit.
+AT91C_AES_CFBS_32_BIT     EQU (0x2 << 16) ;- (AES) 32-bit.
+AT91C_AES_CFBS_16_BIT     EQU (0x3 << 16) ;- (AES) 16-bit.
+AT91C_AES_CFBS_8_BIT      EQU (0x4 << 16) ;- (AES) 8-bit.
+AT91C_AES_CKEY            EQU (0xF << 20) ;- (AES) Countermeasure Key
+AT91C_AES_CTYPE           EQU (0x1F << 24) ;- (AES) Countermeasure Type
+AT91C_AES_CTYPE_TYPE1_EN  EQU (0x1 << 24) ;- (AES) Countermeasure type 1 is enabled.
+AT91C_AES_CTYPE_TYPE2_EN  EQU (0x2 << 24) ;- (AES) Countermeasure type 2 is enabled.
+AT91C_AES_CTYPE_TYPE3_EN  EQU (0x4 << 24) ;- (AES) Countermeasure type 3 is enabled.
+AT91C_AES_CTYPE_TYPE4_EN  EQU (0x8 << 24) ;- (AES) Countermeasure type 4 is enabled.
+AT91C_AES_CTYPE_TYPE5_EN  EQU (0x10 << 24) ;- (AES) Countermeasure type 5 is enabled.
+// - -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- 
+AT91C_AES_DATRDY          EQU (0x1 <<  0) ;- (AES) DATRDY
+AT91C_AES_ENDRX           EQU (0x1 <<  1) ;- (AES) PDC Read Buffer End
+AT91C_AES_ENDTX           EQU (0x1 <<  2) ;- (AES) PDC Write Buffer End
+AT91C_AES_RXBUFF          EQU (0x1 <<  3) ;- (AES) PDC Read Buffer Full
+AT91C_AES_TXBUFE          EQU (0x1 <<  4) ;- (AES) PDC Write Buffer Empty
+AT91C_AES_URAD            EQU (0x1 <<  8) ;- (AES) Unspecified Register Access Detection
+// - -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- 
+// - -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- 
+// - -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- 
+AT91C_AES_URAT            EQU (0x7 << 12) ;- (AES) Unspecified Register Access Type Status
+AT91C_AES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (AES) Input data register written during the data processing in PDC mode.
+AT91C_AES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (AES) Output data register read during the data processing.
+AT91C_AES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (AES) Mode register written during the data processing.
+AT91C_AES_URAT_OUT_DAT_READ_SUBKEY EQU (0x3 << 12) ;- (AES) Output data register read during the sub-keys generation.
+AT91C_AES_URAT_MODEREG_WRITE_SUBKEY EQU (0x4 << 12) ;- (AES) Mode register written during the sub-keys generation.
+AT91C_AES_URAT_WO_REG_READ EQU (0x5 << 12) ;- (AES) Write-only register read access.
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Triple Data Encryption Standard
+// - *****************************************************************************
+// - -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- 
+AT91C_TDES_START          EQU (0x1 <<  0) ;- (TDES) Starts Processing
+AT91C_TDES_SWRST          EQU (0x1 <<  8) ;- (TDES) Software Reset
+// - -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- 
+AT91C_TDES_CIPHER         EQU (0x1 <<  0) ;- (TDES) Processing Mode
+AT91C_TDES_TDESMOD        EQU (0x1 <<  1) ;- (TDES) Single or Triple DES Mode
+AT91C_TDES_KEYMOD         EQU (0x1 <<  4) ;- (TDES) Key Mode
+AT91C_TDES_SMOD           EQU (0x3 <<  8) ;- (TDES) Start Mode
+AT91C_TDES_SMOD_MANUAL    EQU (0x0 <<  8) ;- (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
+AT91C_TDES_SMOD_AUTO      EQU (0x1 <<  8) ;- (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
+AT91C_TDES_SMOD_PDC       EQU (0x2 <<  8) ;- (TDES) PDC Mode (cf datasheet).
+AT91C_TDES_OPMOD          EQU (0x3 << 12) ;- (TDES) Operation Mode
+AT91C_TDES_OPMOD_ECB      EQU (0x0 << 12) ;- (TDES) ECB Electronic CodeBook mode.
+AT91C_TDES_OPMOD_CBC      EQU (0x1 << 12) ;- (TDES) CBC Cipher Block Chaining mode.
+AT91C_TDES_OPMOD_OFB      EQU (0x2 << 12) ;- (TDES) OFB Output Feedback mode.
+AT91C_TDES_OPMOD_CFB      EQU (0x3 << 12) ;- (TDES) CFB Cipher Feedback mode.
+AT91C_TDES_LOD            EQU (0x1 << 15) ;- (TDES) Last Output Data Mode
+AT91C_TDES_CFBS           EQU (0x3 << 16) ;- (TDES) Cipher Feedback Data Size
+AT91C_TDES_CFBS_64_BIT    EQU (0x0 << 16) ;- (TDES) 64-bit.
+AT91C_TDES_CFBS_32_BIT    EQU (0x1 << 16) ;- (TDES) 32-bit.
+AT91C_TDES_CFBS_16_BIT    EQU (0x2 << 16) ;- (TDES) 16-bit.
+AT91C_TDES_CFBS_8_BIT     EQU (0x3 << 16) ;- (TDES) 8-bit.
+// - -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- 
+AT91C_TDES_DATRDY         EQU (0x1 <<  0) ;- (TDES) DATRDY
+AT91C_TDES_ENDRX          EQU (0x1 <<  1) ;- (TDES) PDC Read Buffer End
+AT91C_TDES_ENDTX          EQU (0x1 <<  2) ;- (TDES) PDC Write Buffer End
+AT91C_TDES_RXBUFF         EQU (0x1 <<  3) ;- (TDES) PDC Read Buffer Full
+AT91C_TDES_TXBUFE         EQU (0x1 <<  4) ;- (TDES) PDC Write Buffer Empty
+AT91C_TDES_URAD           EQU (0x1 <<  8) ;- (TDES) Unspecified Register Access Detection
+// - -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- 
+// - -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- 
+// - -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- 
+AT91C_TDES_URAT           EQU (0x3 << 12) ;- (TDES) Unspecified Register Access Type Status
+AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (TDES) Input data register written during the data processing in PDC mode.
+AT91C_TDES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (TDES) Output data register read during the data processing.
+AT91C_TDES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (TDES) Mode register written during the data processing.
+AT91C_TDES_URAT_WO_REG_READ EQU (0x3 << 12) ;- (TDES) Write-only register read access.
+
+// - *****************************************************************************
+// -               REGISTER ADDRESS DEFINITION FOR AT91SAM7X128
+// - *****************************************************************************
+// - ========== Register definition for SYS peripheral ========== 
+// - ========== Register definition for AIC peripheral ========== 
+AT91C_AIC_IVR             EQU (0xFFFFF100) ;- (AIC) IRQ Vector Register
+AT91C_AIC_SMR             EQU (0xFFFFF000) ;- (AIC) Source Mode Register
+AT91C_AIC_FVR             EQU (0xFFFFF104) ;- (AIC) FIQ Vector Register
+AT91C_AIC_DCR             EQU (0xFFFFF138) ;- (AIC) Debug Control Register (Protect)
+AT91C_AIC_EOICR           EQU (0xFFFFF130) ;- (AIC) End of Interrupt Command Register
+AT91C_AIC_SVR             EQU (0xFFFFF080) ;- (AIC) Source Vector Register
+AT91C_AIC_FFSR            EQU (0xFFFFF148) ;- (AIC) Fast Forcing Status Register
+AT91C_AIC_ICCR            EQU (0xFFFFF128) ;- (AIC) Interrupt Clear Command Register
+AT91C_AIC_ISR             EQU (0xFFFFF108) ;- (AIC) Interrupt Status Register
+AT91C_AIC_IMR             EQU (0xFFFFF110) ;- (AIC) Interrupt Mask Register
+AT91C_AIC_IPR             EQU (0xFFFFF10C) ;- (AIC) Interrupt Pending Register
+AT91C_AIC_FFER            EQU (0xFFFFF140) ;- (AIC) Fast Forcing Enable Register
+AT91C_AIC_IECR            EQU (0xFFFFF120) ;- (AIC) Interrupt Enable Command Register
+AT91C_AIC_ISCR            EQU (0xFFFFF12C) ;- (AIC) Interrupt Set Command Register
+AT91C_AIC_FFDR            EQU (0xFFFFF144) ;- (AIC) Fast Forcing Disable Register
+AT91C_AIC_CISR            EQU (0xFFFFF114) ;- (AIC) Core Interrupt Status Register
+AT91C_AIC_IDCR            EQU (0xFFFFF124) ;- (AIC) Interrupt Disable Command Register
+AT91C_AIC_SPU             EQU (0xFFFFF134) ;- (AIC) Spurious Vector Register
+// - ========== Register definition for PDC_DBGU peripheral ========== 
+AT91C_DBGU_TCR            EQU (0xFFFFF30C) ;- (PDC_DBGU) Transmit Counter Register
+AT91C_DBGU_RNPR           EQU (0xFFFFF310) ;- (PDC_DBGU) Receive Next Pointer Register
+AT91C_DBGU_TNPR           EQU (0xFFFFF318) ;- (PDC_DBGU) Transmit Next Pointer Register
+AT91C_DBGU_TPR            EQU (0xFFFFF308) ;- (PDC_DBGU) Transmit Pointer Register
+AT91C_DBGU_RPR            EQU (0xFFFFF300) ;- (PDC_DBGU) Receive Pointer Register
+AT91C_DBGU_RCR            EQU (0xFFFFF304) ;- (PDC_DBGU) Receive Counter Register
+AT91C_DBGU_RNCR           EQU (0xFFFFF314) ;- (PDC_DBGU) Receive Next Counter Register
+AT91C_DBGU_PTCR           EQU (0xFFFFF320) ;- (PDC_DBGU) PDC Transfer Control Register
+AT91C_DBGU_PTSR           EQU (0xFFFFF324) ;- (PDC_DBGU) PDC Transfer Status Register
+AT91C_DBGU_TNCR           EQU (0xFFFFF31C) ;- (PDC_DBGU) Transmit Next Counter Register
+// - ========== Register definition for DBGU peripheral ========== 
+AT91C_DBGU_EXID           EQU (0xFFFFF244) ;- (DBGU) Chip ID Extension Register
+AT91C_DBGU_BRGR           EQU (0xFFFFF220) ;- (DBGU) Baud Rate Generator Register
+AT91C_DBGU_IDR            EQU (0xFFFFF20C) ;- (DBGU) Interrupt Disable Register
+AT91C_DBGU_CSR            EQU (0xFFFFF214) ;- (DBGU) Channel Status Register
+AT91C_DBGU_CIDR           EQU (0xFFFFF240) ;- (DBGU) Chip ID Register
+AT91C_DBGU_MR             EQU (0xFFFFF204) ;- (DBGU) Mode Register
+AT91C_DBGU_IMR            EQU (0xFFFFF210) ;- (DBGU) Interrupt Mask Register
+AT91C_DBGU_CR             EQU (0xFFFFF200) ;- (DBGU) Control Register
+AT91C_DBGU_FNTR           EQU (0xFFFFF248) ;- (DBGU) Force NTRST Register
+AT91C_DBGU_THR            EQU (0xFFFFF21C) ;- (DBGU) Transmitter Holding Register
+AT91C_DBGU_RHR            EQU (0xFFFFF218) ;- (DBGU) Receiver Holding Register
+AT91C_DBGU_IER            EQU (0xFFFFF208) ;- (DBGU) Interrupt Enable Register
+// - ========== Register definition for PIOA peripheral ========== 
+AT91C_PIOA_ODR            EQU (0xFFFFF414) ;- (PIOA) Output Disable Registerr
+AT91C_PIOA_SODR           EQU (0xFFFFF430) ;- (PIOA) Set Output Data Register
+AT91C_PIOA_ISR            EQU (0xFFFFF44C) ;- (PIOA) Interrupt Status Register
+AT91C_PIOA_ABSR           EQU (0xFFFFF478) ;- (PIOA) AB Select Status Register
+AT91C_PIOA_IER            EQU (0xFFFFF440) ;- (PIOA) Interrupt Enable Register
+AT91C_PIOA_PPUDR          EQU (0xFFFFF460) ;- (PIOA) Pull-up Disable Register
+AT91C_PIOA_IMR            EQU (0xFFFFF448) ;- (PIOA) Interrupt Mask Register
+AT91C_PIOA_PER            EQU (0xFFFFF400) ;- (PIOA) PIO Enable Register
+AT91C_PIOA_IFDR           EQU (0xFFFFF424) ;- (PIOA) Input Filter Disable Register
+AT91C_PIOA_OWDR           EQU (0xFFFFF4A4) ;- (PIOA) Output Write Disable Register
+AT91C_PIOA_MDSR           EQU (0xFFFFF458) ;- (PIOA) Multi-driver Status Register
+AT91C_PIOA_IDR            EQU (0xFFFFF444) ;- (PIOA) Interrupt Disable Register
+AT91C_PIOA_ODSR           EQU (0xFFFFF438) ;- (PIOA) Output Data Status Register
+AT91C_PIOA_PPUSR          EQU (0xFFFFF468) ;- (PIOA) Pull-up Status Register
+AT91C_PIOA_OWSR           EQU (0xFFFFF4A8) ;- (PIOA) Output Write Status Register
+AT91C_PIOA_BSR            EQU (0xFFFFF474) ;- (PIOA) Select B Register
+AT91C_PIOA_OWER           EQU (0xFFFFF4A0) ;- (PIOA) Output Write Enable Register
+AT91C_PIOA_IFER           EQU (0xFFFFF420) ;- (PIOA) Input Filter Enable Register
+AT91C_PIOA_PDSR           EQU (0xFFFFF43C) ;- (PIOA) Pin Data Status Register
+AT91C_PIOA_PPUER          EQU (0xFFFFF464) ;- (PIOA) Pull-up Enable Register
+AT91C_PIOA_OSR            EQU (0xFFFFF418) ;- (PIOA) Output Status Register
+AT91C_PIOA_ASR            EQU (0xFFFFF470) ;- (PIOA) Select A Register
+AT91C_PIOA_MDDR           EQU (0xFFFFF454) ;- (PIOA) Multi-driver Disable Register
+AT91C_PIOA_CODR           EQU (0xFFFFF434) ;- (PIOA) Clear Output Data Register
+AT91C_PIOA_MDER           EQU (0xFFFFF450) ;- (PIOA) Multi-driver Enable Register
+AT91C_PIOA_PDR            EQU (0xFFFFF404) ;- (PIOA) PIO Disable Register
+AT91C_PIOA_IFSR           EQU (0xFFFFF428) ;- (PIOA) Input Filter Status Register
+AT91C_PIOA_OER            EQU (0xFFFFF410) ;- (PIOA) Output Enable Register
+AT91C_PIOA_PSR            EQU (0xFFFFF408) ;- (PIOA) PIO Status Register
+// - ========== Register definition for PIOB peripheral ========== 
+AT91C_PIOB_OWDR           EQU (0xFFFFF6A4) ;- (PIOB) Output Write Disable Register
+AT91C_PIOB_MDER           EQU (0xFFFFF650) ;- (PIOB) Multi-driver Enable Register
+AT91C_PIOB_PPUSR          EQU (0xFFFFF668) ;- (PIOB) Pull-up Status Register
+AT91C_PIOB_IMR            EQU (0xFFFFF648) ;- (PIOB) Interrupt Mask Register
+AT91C_PIOB_ASR            EQU (0xFFFFF670) ;- (PIOB) Select A Register
+AT91C_PIOB_PPUDR          EQU (0xFFFFF660) ;- (PIOB) Pull-up Disable Register
+AT91C_PIOB_PSR            EQU (0xFFFFF608) ;- (PIOB) PIO Status Register
+AT91C_PIOB_IER            EQU (0xFFFFF640) ;- (PIOB) Interrupt Enable Register
+AT91C_PIOB_CODR           EQU (0xFFFFF634) ;- (PIOB) Clear Output Data Register
+AT91C_PIOB_OWER           EQU (0xFFFFF6A0) ;- (PIOB) Output Write Enable Register
+AT91C_PIOB_ABSR           EQU (0xFFFFF678) ;- (PIOB) AB Select Status Register
+AT91C_PIOB_IFDR           EQU (0xFFFFF624) ;- (PIOB) Input Filter Disable Register
+AT91C_PIOB_PDSR           EQU (0xFFFFF63C) ;- (PIOB) Pin Data Status Register
+AT91C_PIOB_IDR            EQU (0xFFFFF644) ;- (PIOB) Interrupt Disable Register
+AT91C_PIOB_OWSR           EQU (0xFFFFF6A8) ;- (PIOB) Output Write Status Register
+AT91C_PIOB_PDR            EQU (0xFFFFF604) ;- (PIOB) PIO Disable Register
+AT91C_PIOB_ODR            EQU (0xFFFFF614) ;- (PIOB) Output Disable Registerr
+AT91C_PIOB_IFSR           EQU (0xFFFFF628) ;- (PIOB) Input Filter Status Register
+AT91C_PIOB_PPUER          EQU (0xFFFFF664) ;- (PIOB) Pull-up Enable Register
+AT91C_PIOB_SODR           EQU (0xFFFFF630) ;- (PIOB) Set Output Data Register
+AT91C_PIOB_ISR            EQU (0xFFFFF64C) ;- (PIOB) Interrupt Status Register
+AT91C_PIOB_ODSR           EQU (0xFFFFF638) ;- (PIOB) Output Data Status Register
+AT91C_PIOB_OSR            EQU (0xFFFFF618) ;- (PIOB) Output Status Register
+AT91C_PIOB_MDSR           EQU (0xFFFFF658) ;- (PIOB) Multi-driver Status Register
+AT91C_PIOB_IFER           EQU (0xFFFFF620) ;- (PIOB) Input Filter Enable Register
+AT91C_PIOB_BSR            EQU (0xFFFFF674) ;- (PIOB) Select B Register
+AT91C_PIOB_MDDR           EQU (0xFFFFF654) ;- (PIOB) Multi-driver Disable Register
+AT91C_PIOB_OER            EQU (0xFFFFF610) ;- (PIOB) Output Enable Register
+AT91C_PIOB_PER            EQU (0xFFFFF600) ;- (PIOB) PIO Enable Register
+// - ========== Register definition for CKGR peripheral ========== 
+AT91C_CKGR_MOR            EQU (0xFFFFFC20) ;- (CKGR) Main Oscillator Register
+AT91C_CKGR_PLLR           EQU (0xFFFFFC2C) ;- (CKGR) PLL Register
+AT91C_CKGR_MCFR           EQU (0xFFFFFC24) ;- (CKGR) Main Clock  Frequency Register
+// - ========== Register definition for PMC peripheral ========== 
+AT91C_PMC_IDR             EQU (0xFFFFFC64) ;- (PMC) Interrupt Disable Register
+AT91C_PMC_MOR             EQU (0xFFFFFC20) ;- (PMC) Main Oscillator Register
+AT91C_PMC_PLLR            EQU (0xFFFFFC2C) ;- (PMC) PLL Register
+AT91C_PMC_PCER            EQU (0xFFFFFC10) ;- (PMC) Peripheral Clock Enable Register
+AT91C_PMC_PCKR            EQU (0xFFFFFC40) ;- (PMC) Programmable Clock Register
+AT91C_PMC_MCKR            EQU (0xFFFFFC30) ;- (PMC) Master Clock Register
+AT91C_PMC_SCDR            EQU (0xFFFFFC04) ;- (PMC) System Clock Disable Register
+AT91C_PMC_PCDR            EQU (0xFFFFFC14) ;- (PMC) Peripheral Clock Disable Register
+AT91C_PMC_SCSR            EQU (0xFFFFFC08) ;- (PMC) System Clock Status Register
+AT91C_PMC_PCSR            EQU (0xFFFFFC18) ;- (PMC) Peripheral Clock Status Register
+AT91C_PMC_MCFR            EQU (0xFFFFFC24) ;- (PMC) Main Clock  Frequency Register
+AT91C_PMC_SCER            EQU (0xFFFFFC00) ;- (PMC) System Clock Enable Register
+AT91C_PMC_IMR             EQU (0xFFFFFC6C) ;- (PMC) Interrupt Mask Register
+AT91C_PMC_IER             EQU (0xFFFFFC60) ;- (PMC) Interrupt Enable Register
+AT91C_PMC_SR              EQU (0xFFFFFC68) ;- (PMC) Status Register
+// - ========== Register definition for RSTC peripheral ========== 
+AT91C_RSTC_RCR            EQU (0xFFFFFD00) ;- (RSTC) Reset Control Register
+AT91C_RSTC_RMR            EQU (0xFFFFFD08) ;- (RSTC) Reset Mode Register
+AT91C_RSTC_RSR            EQU (0xFFFFFD04) ;- (RSTC) Reset Status Register
+// - ========== Register definition for RTTC peripheral ========== 
+AT91C_RTTC_RTSR           EQU (0xFFFFFD2C) ;- (RTTC) Real-time Status Register
+AT91C_RTTC_RTMR           EQU (0xFFFFFD20) ;- (RTTC) Real-time Mode Register
+AT91C_RTTC_RTVR           EQU (0xFFFFFD28) ;- (RTTC) Real-time Value Register
+AT91C_RTTC_RTAR           EQU (0xFFFFFD24) ;- (RTTC) Real-time Alarm Register
+// - ========== Register definition for PITC peripheral ========== 
+AT91C_PITC_PIVR           EQU (0xFFFFFD38) ;- (PITC) Period Interval Value Register
+AT91C_PITC_PISR           EQU (0xFFFFFD34) ;- (PITC) Period Interval Status Register
+AT91C_PITC_PIIR           EQU (0xFFFFFD3C) ;- (PITC) Period Interval Image Register
+AT91C_PITC_PIMR           EQU (0xFFFFFD30) ;- (PITC) Period Interval Mode Register
+// - ========== Register definition for WDTC peripheral ========== 
+AT91C_WDTC_WDCR           EQU (0xFFFFFD40) ;- (WDTC) Watchdog Control Register
+AT91C_WDTC_WDSR           EQU (0xFFFFFD48) ;- (WDTC) Watchdog Status Register
+AT91C_WDTC_WDMR           EQU (0xFFFFFD44) ;- (WDTC) Watchdog Mode Register
+// - ========== Register definition for VREG peripheral ========== 
+AT91C_VREG_MR             EQU (0xFFFFFD60) ;- (VREG) Voltage Regulator Mode Register
+// - ========== Register definition for MC peripheral ========== 
+AT91C_MC_ASR              EQU (0xFFFFFF04) ;- (MC) MC Abort Status Register
+AT91C_MC_RCR              EQU (0xFFFFFF00) ;- (MC) MC Remap Control Register
+AT91C_MC_FCR              EQU (0xFFFFFF64) ;- (MC) MC Flash Command Register
+AT91C_MC_AASR             EQU (0xFFFFFF08) ;- (MC) MC Abort Address Status Register
+AT91C_MC_FSR              EQU (0xFFFFFF68) ;- (MC) MC Flash Status Register
+AT91C_MC_FMR              EQU (0xFFFFFF60) ;- (MC) MC Flash Mode Register
+// - ========== Register definition for PDC_SPI1 peripheral ========== 
+AT91C_SPI1_PTCR           EQU (0xFFFE4120) ;- (PDC_SPI1) PDC Transfer Control Register
+AT91C_SPI1_RPR            EQU (0xFFFE4100) ;- (PDC_SPI1) Receive Pointer Register
+AT91C_SPI1_TNCR           EQU (0xFFFE411C) ;- (PDC_SPI1) Transmit Next Counter Register
+AT91C_SPI1_TPR            EQU (0xFFFE4108) ;- (PDC_SPI1) Transmit Pointer Register
+AT91C_SPI1_TNPR           EQU (0xFFFE4118) ;- (PDC_SPI1) Transmit Next Pointer Register
+AT91C_SPI1_TCR            EQU (0xFFFE410C) ;- (PDC_SPI1) Transmit Counter Register
+AT91C_SPI1_RCR            EQU (0xFFFE4104) ;- (PDC_SPI1) Receive Counter Register
+AT91C_SPI1_RNPR           EQU (0xFFFE4110) ;- (PDC_SPI1) Receive Next Pointer Register
+AT91C_SPI1_RNCR           EQU (0xFFFE4114) ;- (PDC_SPI1) Receive Next Counter Register
+AT91C_SPI1_PTSR           EQU (0xFFFE4124) ;- (PDC_SPI1) PDC Transfer Status Register
+// - ========== Register definition for SPI1 peripheral ========== 
+AT91C_SPI1_IMR            EQU (0xFFFE401C) ;- (SPI1) Interrupt Mask Register
+AT91C_SPI1_IER            EQU (0xFFFE4014) ;- (SPI1) Interrupt Enable Register
+AT91C_SPI1_MR             EQU (0xFFFE4004) ;- (SPI1) Mode Register
+AT91C_SPI1_RDR            EQU (0xFFFE4008) ;- (SPI1) Receive Data Register
+AT91C_SPI1_IDR            EQU (0xFFFE4018) ;- (SPI1) Interrupt Disable Register
+AT91C_SPI1_SR             EQU (0xFFFE4010) ;- (SPI1) Status Register
+AT91C_SPI1_TDR            EQU (0xFFFE400C) ;- (SPI1) Transmit Data Register
+AT91C_SPI1_CR             EQU (0xFFFE4000) ;- (SPI1) Control Register
+AT91C_SPI1_CSR            EQU (0xFFFE4030) ;- (SPI1) Chip Select Register
+// - ========== Register definition for PDC_SPI0 peripheral ========== 
+AT91C_SPI0_PTCR           EQU (0xFFFE0120) ;- (PDC_SPI0) PDC Transfer Control Register
+AT91C_SPI0_TPR            EQU (0xFFFE0108) ;- (PDC_SPI0) Transmit Pointer Register
+AT91C_SPI0_TCR            EQU (0xFFFE010C) ;- (PDC_SPI0) Transmit Counter Register
+AT91C_SPI0_RCR            EQU (0xFFFE0104) ;- (PDC_SPI0) Receive Counter Register
+AT91C_SPI0_PTSR           EQU (0xFFFE0124) ;- (PDC_SPI0) PDC Transfer Status Register
+AT91C_SPI0_RNPR           EQU (0xFFFE0110) ;- (PDC_SPI0) Receive Next Pointer Register
+AT91C_SPI0_RPR            EQU (0xFFFE0100) ;- (PDC_SPI0) Receive Pointer Register
+AT91C_SPI0_TNCR           EQU (0xFFFE011C) ;- (PDC_SPI0) Transmit Next Counter Register
+AT91C_SPI0_RNCR           EQU (0xFFFE0114) ;- (PDC_SPI0) Receive Next Counter Register
+AT91C_SPI0_TNPR           EQU (0xFFFE0118) ;- (PDC_SPI0) Transmit Next Pointer Register
+// - ========== Register definition for SPI0 peripheral ========== 
+AT91C_SPI0_IER            EQU (0xFFFE0014) ;- (SPI0) Interrupt Enable Register
+AT91C_SPI0_SR             EQU (0xFFFE0010) ;- (SPI0) Status Register
+AT91C_SPI0_IDR            EQU (0xFFFE0018) ;- (SPI0) Interrupt Disable Register
+AT91C_SPI0_CR             EQU (0xFFFE0000) ;- (SPI0) Control Register
+AT91C_SPI0_MR             EQU (0xFFFE0004) ;- (SPI0) Mode Register
+AT91C_SPI0_IMR            EQU (0xFFFE001C) ;- (SPI0) Interrupt Mask Register
+AT91C_SPI0_TDR            EQU (0xFFFE000C) ;- (SPI0) Transmit Data Register
+AT91C_SPI0_RDR            EQU (0xFFFE0008) ;- (SPI0) Receive Data Register
+AT91C_SPI0_CSR            EQU (0xFFFE0030) ;- (SPI0) Chip Select Register
+// - ========== Register definition for PDC_US1 peripheral ========== 
+AT91C_US1_RNCR            EQU (0xFFFC4114) ;- (PDC_US1) Receive Next Counter Register
+AT91C_US1_PTCR            EQU (0xFFFC4120) ;- (PDC_US1) PDC Transfer Control Register
+AT91C_US1_TCR             EQU (0xFFFC410C) ;- (PDC_US1) Transmit Counter Register
+AT91C_US1_PTSR            EQU (0xFFFC4124) ;- (PDC_US1) PDC Transfer Status Register
+AT91C_US1_TNPR            EQU (0xFFFC4118) ;- (PDC_US1) Transmit Next Pointer Register
+AT91C_US1_RCR             EQU (0xFFFC4104) ;- (PDC_US1) Receive Counter Register
+AT91C_US1_RNPR            EQU (0xFFFC4110) ;- (PDC_US1) Receive Next Pointer Register
+AT91C_US1_RPR             EQU (0xFFFC4100) ;- (PDC_US1) Receive Pointer Register
+AT91C_US1_TNCR            EQU (0xFFFC411C) ;- (PDC_US1) Transmit Next Counter Register
+AT91C_US1_TPR             EQU (0xFFFC4108) ;- (PDC_US1) Transmit Pointer Register
+// - ========== Register definition for US1 peripheral ========== 
+AT91C_US1_IF              EQU (0xFFFC404C) ;- (US1) IRDA_FILTER Register
+AT91C_US1_NER             EQU (0xFFFC4044) ;- (US1) Nb Errors Register
+AT91C_US1_RTOR            EQU (0xFFFC4024) ;- (US1) Receiver Time-out Register
+AT91C_US1_CSR             EQU (0xFFFC4014) ;- (US1) Channel Status Register
+AT91C_US1_IDR             EQU (0xFFFC400C) ;- (US1) Interrupt Disable Register
+AT91C_US1_IER             EQU (0xFFFC4008) ;- (US1) Interrupt Enable Register
+AT91C_US1_THR             EQU (0xFFFC401C) ;- (US1) Transmitter Holding Register
+AT91C_US1_TTGR            EQU (0xFFFC4028) ;- (US1) Transmitter Time-guard Register
+AT91C_US1_RHR             EQU (0xFFFC4018) ;- (US1) Receiver Holding Register
+AT91C_US1_BRGR            EQU (0xFFFC4020) ;- (US1) Baud Rate Generator Register
+AT91C_US1_IMR             EQU (0xFFFC4010) ;- (US1) Interrupt Mask Register
+AT91C_US1_FIDI            EQU (0xFFFC4040) ;- (US1) FI_DI_Ratio Register
+AT91C_US1_CR              EQU (0xFFFC4000) ;- (US1) Control Register
+AT91C_US1_MR              EQU (0xFFFC4004) ;- (US1) Mode Register
+// - ========== Register definition for PDC_US0 peripheral ========== 
+AT91C_US0_TNPR            EQU (0xFFFC0118) ;- (PDC_US0) Transmit Next Pointer Register
+AT91C_US0_RNPR            EQU (0xFFFC0110) ;- (PDC_US0) Receive Next Pointer Register
+AT91C_US0_TCR             EQU (0xFFFC010C) ;- (PDC_US0) Transmit Counter Register
+AT91C_US0_PTCR            EQU (0xFFFC0120) ;- (PDC_US0) PDC Transfer Control Register
+AT91C_US0_PTSR            EQU (0xFFFC0124) ;- (PDC_US0) PDC Transfer Status Register
+AT91C_US0_TNCR            EQU (0xFFFC011C) ;- (PDC_US0) Transmit Next Counter Register
+AT91C_US0_TPR             EQU (0xFFFC0108) ;- (PDC_US0) Transmit Pointer Register
+AT91C_US0_RCR             EQU (0xFFFC0104) ;- (PDC_US0) Receive Counter Register
+AT91C_US0_RPR             EQU (0xFFFC0100) ;- (PDC_US0) Receive Pointer Register
+AT91C_US0_RNCR            EQU (0xFFFC0114) ;- (PDC_US0) Receive Next Counter Register
+// - ========== Register definition for US0 peripheral ========== 
+AT91C_US0_BRGR            EQU (0xFFFC0020) ;- (US0) Baud Rate Generator Register
+AT91C_US0_NER             EQU (0xFFFC0044) ;- (US0) Nb Errors Register
+AT91C_US0_CR              EQU (0xFFFC0000) ;- (US0) Control Register
+AT91C_US0_IMR             EQU (0xFFFC0010) ;- (US0) Interrupt Mask Register
+AT91C_US0_FIDI            EQU (0xFFFC0040) ;- (US0) FI_DI_Ratio Register
+AT91C_US0_TTGR            EQU (0xFFFC0028) ;- (US0) Transmitter Time-guard Register
+AT91C_US0_MR              EQU (0xFFFC0004) ;- (US0) Mode Register
+AT91C_US0_RTOR            EQU (0xFFFC0024) ;- (US0) Receiver Time-out Register
+AT91C_US0_CSR             EQU (0xFFFC0014) ;- (US0) Channel Status Register
+AT91C_US0_RHR             EQU (0xFFFC0018) ;- (US0) Receiver Holding Register
+AT91C_US0_IDR             EQU (0xFFFC000C) ;- (US0) Interrupt Disable Register
+AT91C_US0_THR             EQU (0xFFFC001C) ;- (US0) Transmitter Holding Register
+AT91C_US0_IF              EQU (0xFFFC004C) ;- (US0) IRDA_FILTER Register
+AT91C_US0_IER             EQU (0xFFFC0008) ;- (US0) Interrupt Enable Register
+// - ========== Register definition for PDC_SSC peripheral ========== 
+AT91C_SSC_TNCR            EQU (0xFFFD411C) ;- (PDC_SSC) Transmit Next Counter Register
+AT91C_SSC_RPR             EQU (0xFFFD4100) ;- (PDC_SSC) Receive Pointer Register
+AT91C_SSC_RNCR            EQU (0xFFFD4114) ;- (PDC_SSC) Receive Next Counter Register
+AT91C_SSC_TPR             EQU (0xFFFD4108) ;- (PDC_SSC) Transmit Pointer Register
+AT91C_SSC_PTCR            EQU (0xFFFD4120) ;- (PDC_SSC) PDC Transfer Control Register
+AT91C_SSC_TCR             EQU (0xFFFD410C) ;- (PDC_SSC) Transmit Counter Register
+AT91C_SSC_RCR             EQU (0xFFFD4104) ;- (PDC_SSC) Receive Counter Register
+AT91C_SSC_RNPR            EQU (0xFFFD4110) ;- (PDC_SSC) Receive Next Pointer Register
+AT91C_SSC_TNPR            EQU (0xFFFD4118) ;- (PDC_SSC) Transmit Next Pointer Register
+AT91C_SSC_PTSR            EQU (0xFFFD4124) ;- (PDC_SSC) PDC Transfer Status Register
+// - ========== Register definition for SSC peripheral ========== 
+AT91C_SSC_RHR             EQU (0xFFFD4020) ;- (SSC) Receive Holding Register
+AT91C_SSC_RSHR            EQU (0xFFFD4030) ;- (SSC) Receive Sync Holding Register
+AT91C_SSC_TFMR            EQU (0xFFFD401C) ;- (SSC) Transmit Frame Mode Register
+AT91C_SSC_IDR             EQU (0xFFFD4048) ;- (SSC) Interrupt Disable Register
+AT91C_SSC_THR             EQU (0xFFFD4024) ;- (SSC) Transmit Holding Register
+AT91C_SSC_RCMR            EQU (0xFFFD4010) ;- (SSC) Receive Clock ModeRegister
+AT91C_SSC_IER             EQU (0xFFFD4044) ;- (SSC) Interrupt Enable Register
+AT91C_SSC_TSHR            EQU (0xFFFD4034) ;- (SSC) Transmit Sync Holding Register
+AT91C_SSC_SR              EQU (0xFFFD4040) ;- (SSC) Status Register
+AT91C_SSC_CMR             EQU (0xFFFD4004) ;- (SSC) Clock Mode Register
+AT91C_SSC_TCMR            EQU (0xFFFD4018) ;- (SSC) Transmit Clock Mode Register
+AT91C_SSC_CR              EQU (0xFFFD4000) ;- (SSC) Control Register
+AT91C_SSC_IMR             EQU (0xFFFD404C) ;- (SSC) Interrupt Mask Register
+AT91C_SSC_RFMR            EQU (0xFFFD4014) ;- (SSC) Receive Frame Mode Register
+// - ========== Register definition for TWI peripheral ========== 
+AT91C_TWI_IER             EQU (0xFFFB8024) ;- (TWI) Interrupt Enable Register
+AT91C_TWI_CR              EQU (0xFFFB8000) ;- (TWI) Control Register
+AT91C_TWI_SR              EQU (0xFFFB8020) ;- (TWI) Status Register
+AT91C_TWI_IMR             EQU (0xFFFB802C) ;- (TWI) Interrupt Mask Register
+AT91C_TWI_THR             EQU (0xFFFB8034) ;- (TWI) Transmit Holding Register
+AT91C_TWI_IDR             EQU (0xFFFB8028) ;- (TWI) Interrupt Disable Register
+AT91C_TWI_IADR            EQU (0xFFFB800C) ;- (TWI) Internal Address Register
+AT91C_TWI_MMR             EQU (0xFFFB8004) ;- (TWI) Master Mode Register
+AT91C_TWI_CWGR            EQU (0xFFFB8010) ;- (TWI) Clock Waveform Generator Register
+AT91C_TWI_RHR             EQU (0xFFFB8030) ;- (TWI) Receive Holding Register
+// - ========== Register definition for PWMC_CH3 peripheral ========== 
+AT91C_PWMC_CH3_CUPDR      EQU (0xFFFCC270) ;- (PWMC_CH3) Channel Update Register
+AT91C_PWMC_CH3_Reserved   EQU (0xFFFCC274) ;- (PWMC_CH3) Reserved
+AT91C_PWMC_CH3_CPRDR      EQU (0xFFFCC268) ;- (PWMC_CH3) Channel Period Register
+AT91C_PWMC_CH3_CDTYR      EQU (0xFFFCC264) ;- (PWMC_CH3) Channel Duty Cycle Register
+AT91C_PWMC_CH3_CCNTR      EQU (0xFFFCC26C) ;- (PWMC_CH3) Channel Counter Register
+AT91C_PWMC_CH3_CMR        EQU (0xFFFCC260) ;- (PWMC_CH3) Channel Mode Register
+// - ========== Register definition for PWMC_CH2 peripheral ========== 
+AT91C_PWMC_CH2_Reserved   EQU (0xFFFCC254) ;- (PWMC_CH2) Reserved
+AT91C_PWMC_CH2_CMR        EQU (0xFFFCC240) ;- (PWMC_CH2) Channel Mode Register
+AT91C_PWMC_CH2_CCNTR      EQU (0xFFFCC24C) ;- (PWMC_CH2) Channel Counter Register
+AT91C_PWMC_CH2_CPRDR      EQU (0xFFFCC248) ;- (PWMC_CH2) Channel Period Register
+AT91C_PWMC_CH2_CUPDR      EQU (0xFFFCC250) ;- (PWMC_CH2) Channel Update Register
+AT91C_PWMC_CH2_CDTYR      EQU (0xFFFCC244) ;- (PWMC_CH2) Channel Duty Cycle Register
+// - ========== Register definition for PWMC_CH1 peripheral ========== 
+AT91C_PWMC_CH1_Reserved   EQU (0xFFFCC234) ;- (PWMC_CH1) Reserved
+AT91C_PWMC_CH1_CUPDR      EQU (0xFFFCC230) ;- (PWMC_CH1) Channel Update Register
+AT91C_PWMC_CH1_CPRDR      EQU (0xFFFCC228) ;- (PWMC_CH1) Channel Period Register
+AT91C_PWMC_CH1_CCNTR      EQU (0xFFFCC22C) ;- (PWMC_CH1) Channel Counter Register
+AT91C_PWMC_CH1_CDTYR      EQU (0xFFFCC224) ;- (PWMC_CH1) Channel Duty Cycle Register
+AT91C_PWMC_CH1_CMR        EQU (0xFFFCC220) ;- (PWMC_CH1) Channel Mode Register
+// - ========== Register definition for PWMC_CH0 peripheral ========== 
+AT91C_PWMC_CH0_Reserved   EQU (0xFFFCC214) ;- (PWMC_CH0) Reserved
+AT91C_PWMC_CH0_CPRDR      EQU (0xFFFCC208) ;- (PWMC_CH0) Channel Period Register
+AT91C_PWMC_CH0_CDTYR      EQU (0xFFFCC204) ;- (PWMC_CH0) Channel Duty Cycle Register
+AT91C_PWMC_CH0_CMR        EQU (0xFFFCC200) ;- (PWMC_CH0) Channel Mode Register
+AT91C_PWMC_CH0_CUPDR      EQU (0xFFFCC210) ;- (PWMC_CH0) Channel Update Register
+AT91C_PWMC_CH0_CCNTR      EQU (0xFFFCC20C) ;- (PWMC_CH0) Channel Counter Register
+// - ========== Register definition for PWMC peripheral ========== 
+AT91C_PWMC_IDR            EQU (0xFFFCC014) ;- (PWMC) PWMC Interrupt Disable Register
+AT91C_PWMC_DIS            EQU (0xFFFCC008) ;- (PWMC) PWMC Disable Register
+AT91C_PWMC_IER            EQU (0xFFFCC010) ;- (PWMC) PWMC Interrupt Enable Register
+AT91C_PWMC_VR             EQU (0xFFFCC0FC) ;- (PWMC) PWMC Version Register
+AT91C_PWMC_ISR            EQU (0xFFFCC01C) ;- (PWMC) PWMC Interrupt Status Register
+AT91C_PWMC_SR             EQU (0xFFFCC00C) ;- (PWMC) PWMC Status Register
+AT91C_PWMC_IMR            EQU (0xFFFCC018) ;- (PWMC) PWMC Interrupt Mask Register
+AT91C_PWMC_MR             EQU (0xFFFCC000) ;- (PWMC) PWMC Mode Register
+AT91C_PWMC_ENA            EQU (0xFFFCC004) ;- (PWMC) PWMC Enable Register
+// - ========== Register definition for UDP peripheral ========== 
+AT91C_UDP_IMR             EQU (0xFFFB0018) ;- (UDP) Interrupt Mask Register
+AT91C_UDP_FADDR           EQU (0xFFFB0008) ;- (UDP) Function Address Register
+AT91C_UDP_NUM             EQU (0xFFFB0000) ;- (UDP) Frame Number Register
+AT91C_UDP_FDR             EQU (0xFFFB0050) ;- (UDP) Endpoint FIFO Data Register
+AT91C_UDP_ISR             EQU (0xFFFB001C) ;- (UDP) Interrupt Status Register
+AT91C_UDP_CSR             EQU (0xFFFB0030) ;- (UDP) Endpoint Control and Status Register
+AT91C_UDP_IDR             EQU (0xFFFB0014) ;- (UDP) Interrupt Disable Register
+AT91C_UDP_ICR             EQU (0xFFFB0020) ;- (UDP) Interrupt Clear Register
+AT91C_UDP_RSTEP           EQU (0xFFFB0028) ;- (UDP) Reset Endpoint Register
+AT91C_UDP_TXVC            EQU (0xFFFB0074) ;- (UDP) Transceiver Control Register
+AT91C_UDP_GLBSTATE        EQU (0xFFFB0004) ;- (UDP) Global State Register
+AT91C_UDP_IER             EQU (0xFFFB0010) ;- (UDP) Interrupt Enable Register
+// - ========== Register definition for TC0 peripheral ========== 
+AT91C_TC0_SR              EQU (0xFFFA0020) ;- (TC0) Status Register
+AT91C_TC0_RC              EQU (0xFFFA001C) ;- (TC0) Register C
+AT91C_TC0_RB              EQU (0xFFFA0018) ;- (TC0) Register B
+AT91C_TC0_CCR             EQU (0xFFFA0000) ;- (TC0) Channel Control Register
+AT91C_TC0_CMR             EQU (0xFFFA0004) ;- (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
+AT91C_TC0_IER             EQU (0xFFFA0024) ;- (TC0) Interrupt Enable Register
+AT91C_TC0_RA              EQU (0xFFFA0014) ;- (TC0) Register A
+AT91C_TC0_IDR             EQU (0xFFFA0028) ;- (TC0) Interrupt Disable Register
+AT91C_TC0_CV              EQU (0xFFFA0010) ;- (TC0) Counter Value
+AT91C_TC0_IMR             EQU (0xFFFA002C) ;- (TC0) Interrupt Mask Register
+// - ========== Register definition for TC1 peripheral ========== 
+AT91C_TC1_RB              EQU (0xFFFA0058) ;- (TC1) Register B
+AT91C_TC1_CCR             EQU (0xFFFA0040) ;- (TC1) Channel Control Register
+AT91C_TC1_IER             EQU (0xFFFA0064) ;- (TC1) Interrupt Enable Register
+AT91C_TC1_IDR             EQU (0xFFFA0068) ;- (TC1) Interrupt Disable Register
+AT91C_TC1_SR              EQU (0xFFFA0060) ;- (TC1) Status Register
+AT91C_TC1_CMR             EQU (0xFFFA0044) ;- (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
+AT91C_TC1_RA              EQU (0xFFFA0054) ;- (TC1) Register A
+AT91C_TC1_RC              EQU (0xFFFA005C) ;- (TC1) Register C
+AT91C_TC1_IMR             EQU (0xFFFA006C) ;- (TC1) Interrupt Mask Register
+AT91C_TC1_CV              EQU (0xFFFA0050) ;- (TC1) Counter Value
+// - ========== Register definition for TC2 peripheral ========== 
+AT91C_TC2_CMR             EQU (0xFFFA0084) ;- (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
+AT91C_TC2_CCR             EQU (0xFFFA0080) ;- (TC2) Channel Control Register
+AT91C_TC2_CV              EQU (0xFFFA0090) ;- (TC2) Counter Value
+AT91C_TC2_RA              EQU (0xFFFA0094) ;- (TC2) Register A
+AT91C_TC2_RB              EQU (0xFFFA0098) ;- (TC2) Register B
+AT91C_TC2_IDR             EQU (0xFFFA00A8) ;- (TC2) Interrupt Disable Register
+AT91C_TC2_IMR             EQU (0xFFFA00AC) ;- (TC2) Interrupt Mask Register
+AT91C_TC2_RC              EQU (0xFFFA009C) ;- (TC2) Register C
+AT91C_TC2_IER             EQU (0xFFFA00A4) ;- (TC2) Interrupt Enable Register
+AT91C_TC2_SR              EQU (0xFFFA00A0) ;- (TC2) Status Register
+// - ========== Register definition for TCB peripheral ========== 
+AT91C_TCB_BMR             EQU (0xFFFA00C4) ;- (TCB) TC Block Mode Register
+AT91C_TCB_BCR             EQU (0xFFFA00C0) ;- (TCB) TC Block Control Register
+// - ========== Register definition for CAN_MB0 peripheral ========== 
+AT91C_CAN_MB0_MDL         EQU (0xFFFD0214) ;- (CAN_MB0) MailBox Data Low Register
+AT91C_CAN_MB0_MAM         EQU (0xFFFD0204) ;- (CAN_MB0) MailBox Acceptance Mask Register
+AT91C_CAN_MB0_MCR         EQU (0xFFFD021C) ;- (CAN_MB0) MailBox Control Register
+AT91C_CAN_MB0_MID         EQU (0xFFFD0208) ;- (CAN_MB0) MailBox ID Register
+AT91C_CAN_MB0_MSR         EQU (0xFFFD0210) ;- (CAN_MB0) MailBox Status Register
+AT91C_CAN_MB0_MFID        EQU (0xFFFD020C) ;- (CAN_MB0) MailBox Family ID Register
+AT91C_CAN_MB0_MDH         EQU (0xFFFD0218) ;- (CAN_MB0) MailBox Data High Register
+AT91C_CAN_MB0_MMR         EQU (0xFFFD0200) ;- (CAN_MB0) MailBox Mode Register
+// - ========== Register definition for CAN_MB1 peripheral ========== 
+AT91C_CAN_MB1_MDL         EQU (0xFFFD0234) ;- (CAN_MB1) MailBox Data Low Register
+AT91C_CAN_MB1_MID         EQU (0xFFFD0228) ;- (CAN_MB1) MailBox ID Register
+AT91C_CAN_MB1_MMR         EQU (0xFFFD0220) ;- (CAN_MB1) MailBox Mode Register
+AT91C_CAN_MB1_MSR         EQU (0xFFFD0230) ;- (CAN_MB1) MailBox Status Register
+AT91C_CAN_MB1_MAM         EQU (0xFFFD0224) ;- (CAN_MB1) MailBox Acceptance Mask Register
+AT91C_CAN_MB1_MDH         EQU (0xFFFD0238) ;- (CAN_MB1) MailBox Data High Register
+AT91C_CAN_MB1_MCR         EQU (0xFFFD023C) ;- (CAN_MB1) MailBox Control Register
+AT91C_CAN_MB1_MFID        EQU (0xFFFD022C) ;- (CAN_MB1) MailBox Family ID Register
+// - ========== Register definition for CAN_MB2 peripheral ========== 
+AT91C_CAN_MB2_MCR         EQU (0xFFFD025C) ;- (CAN_MB2) MailBox Control Register
+AT91C_CAN_MB2_MDH         EQU (0xFFFD0258) ;- (CAN_MB2) MailBox Data High Register
+AT91C_CAN_MB2_MID         EQU (0xFFFD0248) ;- (CAN_MB2) MailBox ID Register
+AT91C_CAN_MB2_MDL         EQU (0xFFFD0254) ;- (CAN_MB2) MailBox Data Low Register
+AT91C_CAN_MB2_MMR         EQU (0xFFFD0240) ;- (CAN_MB2) MailBox Mode Register
+AT91C_CAN_MB2_MAM         EQU (0xFFFD0244) ;- (CAN_MB2) MailBox Acceptance Mask Register
+AT91C_CAN_MB2_MFID        EQU (0xFFFD024C) ;- (CAN_MB2) MailBox Family ID Register
+AT91C_CAN_MB2_MSR         EQU (0xFFFD0250) ;- (CAN_MB2) MailBox Status Register
+// - ========== Register definition for CAN_MB3 peripheral ========== 
+AT91C_CAN_MB3_MFID        EQU (0xFFFD026C) ;- (CAN_MB3) MailBox Family ID Register
+AT91C_CAN_MB3_MAM         EQU (0xFFFD0264) ;- (CAN_MB3) MailBox Acceptance Mask Register
+AT91C_CAN_MB3_MID         EQU (0xFFFD0268) ;- (CAN_MB3) MailBox ID Register
+AT91C_CAN_MB3_MCR         EQU (0xFFFD027C) ;- (CAN_MB3) MailBox Control Register
+AT91C_CAN_MB3_MMR         EQU (0xFFFD0260) ;- (CAN_MB3) MailBox Mode Register
+AT91C_CAN_MB3_MSR         EQU (0xFFFD0270) ;- (CAN_MB3) MailBox Status Register
+AT91C_CAN_MB3_MDL         EQU (0xFFFD0274) ;- (CAN_MB3) MailBox Data Low Register
+AT91C_CAN_MB3_MDH         EQU (0xFFFD0278) ;- (CAN_MB3) MailBox Data High Register
+// - ========== Register definition for CAN_MB4 peripheral ========== 
+AT91C_CAN_MB4_MID         EQU (0xFFFD0288) ;- (CAN_MB4) MailBox ID Register
+AT91C_CAN_MB4_MMR         EQU (0xFFFD0280) ;- (CAN_MB4) MailBox Mode Register
+AT91C_CAN_MB4_MDH         EQU (0xFFFD0298) ;- (CAN_MB4) MailBox Data High Register
+AT91C_CAN_MB4_MFID        EQU (0xFFFD028C) ;- (CAN_MB4) MailBox Family ID Register
+AT91C_CAN_MB4_MSR         EQU (0xFFFD0290) ;- (CAN_MB4) MailBox Status Register
+AT91C_CAN_MB4_MCR         EQU (0xFFFD029C) ;- (CAN_MB4) MailBox Control Register
+AT91C_CAN_MB4_MDL         EQU (0xFFFD0294) ;- (CAN_MB4) MailBox Data Low Register
+AT91C_CAN_MB4_MAM         EQU (0xFFFD0284) ;- (CAN_MB4) MailBox Acceptance Mask Register
+// - ========== Register definition for CAN_MB5 peripheral ========== 
+AT91C_CAN_MB5_MSR         EQU (0xFFFD02B0) ;- (CAN_MB5) MailBox Status Register
+AT91C_CAN_MB5_MCR         EQU (0xFFFD02BC) ;- (CAN_MB5) MailBox Control Register
+AT91C_CAN_MB5_MFID        EQU (0xFFFD02AC) ;- (CAN_MB5) MailBox Family ID Register
+AT91C_CAN_MB5_MDH         EQU (0xFFFD02B8) ;- (CAN_MB5) MailBox Data High Register
+AT91C_CAN_MB5_MID         EQU (0xFFFD02A8) ;- (CAN_MB5) MailBox ID Register
+AT91C_CAN_MB5_MMR         EQU (0xFFFD02A0) ;- (CAN_MB5) MailBox Mode Register
+AT91C_CAN_MB5_MDL         EQU (0xFFFD02B4) ;- (CAN_MB5) MailBox Data Low Register
+AT91C_CAN_MB5_MAM         EQU (0xFFFD02A4) ;- (CAN_MB5) MailBox Acceptance Mask Register
+// - ========== Register definition for CAN_MB6 peripheral ========== 
+AT91C_CAN_MB6_MFID        EQU (0xFFFD02CC) ;- (CAN_MB6) MailBox Family ID Register
+AT91C_CAN_MB6_MID         EQU (0xFFFD02C8) ;- (CAN_MB6) MailBox ID Register
+AT91C_CAN_MB6_MAM         EQU (0xFFFD02C4) ;- (CAN_MB6) MailBox Acceptance Mask Register
+AT91C_CAN_MB6_MSR         EQU (0xFFFD02D0) ;- (CAN_MB6) MailBox Status Register
+AT91C_CAN_MB6_MDL         EQU (0xFFFD02D4) ;- (CAN_MB6) MailBox Data Low Register
+AT91C_CAN_MB6_MCR         EQU (0xFFFD02DC) ;- (CAN_MB6) MailBox Control Register
+AT91C_CAN_MB6_MDH         EQU (0xFFFD02D8) ;- (CAN_MB6) MailBox Data High Register
+AT91C_CAN_MB6_MMR         EQU (0xFFFD02C0) ;- (CAN_MB6) MailBox Mode Register
+// - ========== Register definition for CAN_MB7 peripheral ========== 
+AT91C_CAN_MB7_MCR         EQU (0xFFFD02FC) ;- (CAN_MB7) MailBox Control Register
+AT91C_CAN_MB7_MDH         EQU (0xFFFD02F8) ;- (CAN_MB7) MailBox Data High Register
+AT91C_CAN_MB7_MFID        EQU (0xFFFD02EC) ;- (CAN_MB7) MailBox Family ID Register
+AT91C_CAN_MB7_MDL         EQU (0xFFFD02F4) ;- (CAN_MB7) MailBox Data Low Register
+AT91C_CAN_MB7_MID         EQU (0xFFFD02E8) ;- (CAN_MB7) MailBox ID Register
+AT91C_CAN_MB7_MMR         EQU (0xFFFD02E0) ;- (CAN_MB7) MailBox Mode Register
+AT91C_CAN_MB7_MAM         EQU (0xFFFD02E4) ;- (CAN_MB7) MailBox Acceptance Mask Register
+AT91C_CAN_MB7_MSR         EQU (0xFFFD02F0) ;- (CAN_MB7) MailBox Status Register
+// - ========== Register definition for CAN peripheral ========== 
+AT91C_CAN_TCR             EQU (0xFFFD0024) ;- (CAN) Transfer Command Register
+AT91C_CAN_IMR             EQU (0xFFFD000C) ;- (CAN) Interrupt Mask Register
+AT91C_CAN_IER             EQU (0xFFFD0004) ;- (CAN) Interrupt Enable Register
+AT91C_CAN_ECR             EQU (0xFFFD0020) ;- (CAN) Error Counter Register
+AT91C_CAN_TIMESTP         EQU (0xFFFD001C) ;- (CAN) Time Stamp Register
+AT91C_CAN_MR              EQU (0xFFFD0000) ;- (CAN) Mode Register
+AT91C_CAN_IDR             EQU (0xFFFD0008) ;- (CAN) Interrupt Disable Register
+AT91C_CAN_ACR             EQU (0xFFFD0028) ;- (CAN) Abort Command Register
+AT91C_CAN_TIM             EQU (0xFFFD0018) ;- (CAN) Timer Register
+AT91C_CAN_SR              EQU (0xFFFD0010) ;- (CAN) Status Register
+AT91C_CAN_BR              EQU (0xFFFD0014) ;- (CAN) Baudrate Register
+AT91C_CAN_VR              EQU (0xFFFD00FC) ;- (CAN) Version Register
+// - ========== Register definition for EMAC peripheral ========== 
+AT91C_EMAC_ISR            EQU (0xFFFDC024) ;- (EMAC) Interrupt Status Register
+AT91C_EMAC_SA4H           EQU (0xFFFDC0B4) ;- (EMAC) Specific Address 4 Top, Last 2 bytes
+AT91C_EMAC_SA1L           EQU (0xFFFDC098) ;- (EMAC) Specific Address 1 Bottom, First 4 bytes
+AT91C_EMAC_ELE            EQU (0xFFFDC078) ;- (EMAC) Excessive Length Errors Register
+AT91C_EMAC_LCOL           EQU (0xFFFDC05C) ;- (EMAC) Late Collision Register
+AT91C_EMAC_RLE            EQU (0xFFFDC088) ;- (EMAC) Receive Length Field Mismatch Register
+AT91C_EMAC_WOL            EQU (0xFFFDC0C4) ;- (EMAC) Wake On LAN Register
+AT91C_EMAC_DTF            EQU (0xFFFDC058) ;- (EMAC) Deferred Transmission Frame Register
+AT91C_EMAC_TUND           EQU (0xFFFDC064) ;- (EMAC) Transmit Underrun Error Register
+AT91C_EMAC_NCR            EQU (0xFFFDC000) ;- (EMAC) Network Control Register
+AT91C_EMAC_SA4L           EQU (0xFFFDC0B0) ;- (EMAC) Specific Address 4 Bottom, First 4 bytes
+AT91C_EMAC_RSR            EQU (0xFFFDC020) ;- (EMAC) Receive Status Register
+AT91C_EMAC_SA3L           EQU (0xFFFDC0A8) ;- (EMAC) Specific Address 3 Bottom, First 4 bytes
+AT91C_EMAC_TSR            EQU (0xFFFDC014) ;- (EMAC) Transmit Status Register
+AT91C_EMAC_IDR            EQU (0xFFFDC02C) ;- (EMAC) Interrupt Disable Register
+AT91C_EMAC_RSE            EQU (0xFFFDC074) ;- (EMAC) Receive Symbol Errors Register
+AT91C_EMAC_ECOL           EQU (0xFFFDC060) ;- (EMAC) Excessive Collision Register
+AT91C_EMAC_TID            EQU (0xFFFDC0B8) ;- (EMAC) Type ID Checking Register
+AT91C_EMAC_HRB            EQU (0xFFFDC090) ;- (EMAC) Hash Address Bottom[31:0]
+AT91C_EMAC_TBQP           EQU (0xFFFDC01C) ;- (EMAC) Transmit Buffer Queue Pointer
+AT91C_EMAC_USRIO          EQU (0xFFFDC0C0) ;- (EMAC) USER Input/Output Register
+AT91C_EMAC_PTR            EQU (0xFFFDC038) ;- (EMAC) Pause Time Register
+AT91C_EMAC_SA2H           EQU (0xFFFDC0A4) ;- (EMAC) Specific Address 2 Top, Last 2 bytes
+AT91C_EMAC_ROV            EQU (0xFFFDC070) ;- (EMAC) Receive Overrun Errors Register
+AT91C_EMAC_ALE            EQU (0xFFFDC054) ;- (EMAC) Alignment Error Register
+AT91C_EMAC_RJA            EQU (0xFFFDC07C) ;- (EMAC) Receive Jabbers Register
+AT91C_EMAC_RBQP           EQU (0xFFFDC018) ;- (EMAC) Receive Buffer Queue Pointer
+AT91C_EMAC_TPF            EQU (0xFFFDC08C) ;- (EMAC) Transmitted Pause Frames Register
+AT91C_EMAC_NCFGR          EQU (0xFFFDC004) ;- (EMAC) Network Configuration Register
+AT91C_EMAC_HRT            EQU (0xFFFDC094) ;- (EMAC) Hash Address Top[63:32]
+AT91C_EMAC_USF            EQU (0xFFFDC080) ;- (EMAC) Undersize Frames Register
+AT91C_EMAC_FCSE           EQU (0xFFFDC050) ;- (EMAC) Frame Check Sequence Error Register
+AT91C_EMAC_TPQ            EQU (0xFFFDC0BC) ;- (EMAC) Transmit Pause Quantum Register
+AT91C_EMAC_MAN            EQU (0xFFFDC034) ;- (EMAC) PHY Maintenance Register
+AT91C_EMAC_FTO            EQU (0xFFFDC040) ;- (EMAC) Frames Transmitted OK Register
+AT91C_EMAC_REV            EQU (0xFFFDC0FC) ;- (EMAC) Revision Register
+AT91C_EMAC_IMR            EQU (0xFFFDC030) ;- (EMAC) Interrupt Mask Register
+AT91C_EMAC_SCF            EQU (0xFFFDC044) ;- (EMAC) Single Collision Frame Register
+AT91C_EMAC_PFR            EQU (0xFFFDC03C) ;- (EMAC) Pause Frames received Register
+AT91C_EMAC_MCF            EQU (0xFFFDC048) ;- (EMAC) Multiple Collision Frame Register
+AT91C_EMAC_NSR            EQU (0xFFFDC008) ;- (EMAC) Network Status Register
+AT91C_EMAC_SA2L           EQU (0xFFFDC0A0) ;- (EMAC) Specific Address 2 Bottom, First 4 bytes
+AT91C_EMAC_FRO            EQU (0xFFFDC04C) ;- (EMAC) Frames Received OK Register
+AT91C_EMAC_IER            EQU (0xFFFDC028) ;- (EMAC) Interrupt Enable Register
+AT91C_EMAC_SA1H           EQU (0xFFFDC09C) ;- (EMAC) Specific Address 1 Top, Last 2 bytes
+AT91C_EMAC_CSE            EQU (0xFFFDC068) ;- (EMAC) Carrier Sense Error Register
+AT91C_EMAC_SA3H           EQU (0xFFFDC0AC) ;- (EMAC) Specific Address 3 Top, Last 2 bytes
+AT91C_EMAC_RRE            EQU (0xFFFDC06C) ;- (EMAC) Receive Ressource Error Register
+AT91C_EMAC_STE            EQU (0xFFFDC084) ;- (EMAC) SQE Test Error Register
+// - ========== Register definition for PDC_ADC peripheral ========== 
+AT91C_ADC_PTSR            EQU (0xFFFD8124) ;- (PDC_ADC) PDC Transfer Status Register
+AT91C_ADC_PTCR            EQU (0xFFFD8120) ;- (PDC_ADC) PDC Transfer Control Register
+AT91C_ADC_TNPR            EQU (0xFFFD8118) ;- (PDC_ADC) Transmit Next Pointer Register
+AT91C_ADC_TNCR            EQU (0xFFFD811C) ;- (PDC_ADC) Transmit Next Counter Register
+AT91C_ADC_RNPR            EQU (0xFFFD8110) ;- (PDC_ADC) Receive Next Pointer Register
+AT91C_ADC_RNCR            EQU (0xFFFD8114) ;- (PDC_ADC) Receive Next Counter Register
+AT91C_ADC_RPR             EQU (0xFFFD8100) ;- (PDC_ADC) Receive Pointer Register
+AT91C_ADC_TCR             EQU (0xFFFD810C) ;- (PDC_ADC) Transmit Counter Register
+AT91C_ADC_TPR             EQU (0xFFFD8108) ;- (PDC_ADC) Transmit Pointer Register
+AT91C_ADC_RCR             EQU (0xFFFD8104) ;- (PDC_ADC) Receive Counter Register
+// - ========== Register definition for ADC peripheral ========== 
+AT91C_ADC_CDR2            EQU (0xFFFD8038) ;- (ADC) ADC Channel Data Register 2
+AT91C_ADC_CDR3            EQU (0xFFFD803C) ;- (ADC) ADC Channel Data Register 3
+AT91C_ADC_CDR0            EQU (0xFFFD8030) ;- (ADC) ADC Channel Data Register 0
+AT91C_ADC_CDR5            EQU (0xFFFD8044) ;- (ADC) ADC Channel Data Register 5
+AT91C_ADC_CHDR            EQU (0xFFFD8014) ;- (ADC) ADC Channel Disable Register
+AT91C_ADC_SR              EQU (0xFFFD801C) ;- (ADC) ADC Status Register
+AT91C_ADC_CDR4            EQU (0xFFFD8040) ;- (ADC) ADC Channel Data Register 4
+AT91C_ADC_CDR1            EQU (0xFFFD8034) ;- (ADC) ADC Channel Data Register 1
+AT91C_ADC_LCDR            EQU (0xFFFD8020) ;- (ADC) ADC Last Converted Data Register
+AT91C_ADC_IDR             EQU (0xFFFD8028) ;- (ADC) ADC Interrupt Disable Register
+AT91C_ADC_CR              EQU (0xFFFD8000) ;- (ADC) ADC Control Register
+AT91C_ADC_CDR7            EQU (0xFFFD804C) ;- (ADC) ADC Channel Data Register 7
+AT91C_ADC_CDR6            EQU (0xFFFD8048) ;- (ADC) ADC Channel Data Register 6
+AT91C_ADC_IER             EQU (0xFFFD8024) ;- (ADC) ADC Interrupt Enable Register
+AT91C_ADC_CHER            EQU (0xFFFD8010) ;- (ADC) ADC Channel Enable Register
+AT91C_ADC_CHSR            EQU (0xFFFD8018) ;- (ADC) ADC Channel Status Register
+AT91C_ADC_MR              EQU (0xFFFD8004) ;- (ADC) ADC Mode Register
+AT91C_ADC_IMR             EQU (0xFFFD802C) ;- (ADC) ADC Interrupt Mask Register
+// - ========== Register definition for PDC_AES peripheral ========== 
+AT91C_AES_TPR             EQU (0xFFFA4108) ;- (PDC_AES) Transmit Pointer Register
+AT91C_AES_PTCR            EQU (0xFFFA4120) ;- (PDC_AES) PDC Transfer Control Register
+AT91C_AES_RNPR            EQU (0xFFFA4110) ;- (PDC_AES) Receive Next Pointer Register
+AT91C_AES_TNCR            EQU (0xFFFA411C) ;- (PDC_AES) Transmit Next Counter Register
+AT91C_AES_TCR             EQU (0xFFFA410C) ;- (PDC_AES) Transmit Counter Register
+AT91C_AES_RCR             EQU (0xFFFA4104) ;- (PDC_AES) Receive Counter Register
+AT91C_AES_RNCR            EQU (0xFFFA4114) ;- (PDC_AES) Receive Next Counter Register
+AT91C_AES_TNPR            EQU (0xFFFA4118) ;- (PDC_AES) Transmit Next Pointer Register
+AT91C_AES_RPR             EQU (0xFFFA4100) ;- (PDC_AES) Receive Pointer Register
+AT91C_AES_PTSR            EQU (0xFFFA4124) ;- (PDC_AES) PDC Transfer Status Register
+// - ========== Register definition for AES peripheral ========== 
+AT91C_AES_IVxR            EQU (0xFFFA4060) ;- (AES) Initialization Vector x Register
+AT91C_AES_MR              EQU (0xFFFA4004) ;- (AES) Mode Register
+AT91C_AES_VR              EQU (0xFFFA40FC) ;- (AES) AES Version Register
+AT91C_AES_ODATAxR         EQU (0xFFFA4050) ;- (AES) Output Data x Register
+AT91C_AES_IDATAxR         EQU (0xFFFA4040) ;- (AES) Input Data x Register
+AT91C_AES_CR              EQU (0xFFFA4000) ;- (AES) Control Register
+AT91C_AES_IDR             EQU (0xFFFA4014) ;- (AES) Interrupt Disable Register
+AT91C_AES_IMR             EQU (0xFFFA4018) ;- (AES) Interrupt Mask Register
+AT91C_AES_IER             EQU (0xFFFA4010) ;- (AES) Interrupt Enable Register
+AT91C_AES_KEYWxR          EQU (0xFFFA4020) ;- (AES) Key Word x Register
+AT91C_AES_ISR             EQU (0xFFFA401C) ;- (AES) Interrupt Status Register
+// - ========== Register definition for PDC_TDES peripheral ========== 
+AT91C_TDES_RNCR           EQU (0xFFFA8114) ;- (PDC_TDES) Receive Next Counter Register
+AT91C_TDES_TCR            EQU (0xFFFA810C) ;- (PDC_TDES) Transmit Counter Register
+AT91C_TDES_RCR            EQU (0xFFFA8104) ;- (PDC_TDES) Receive Counter Register
+AT91C_TDES_TNPR           EQU (0xFFFA8118) ;- (PDC_TDES) Transmit Next Pointer Register
+AT91C_TDES_RNPR           EQU (0xFFFA8110) ;- (PDC_TDES) Receive Next Pointer Register
+AT91C_TDES_RPR            EQU (0xFFFA8100) ;- (PDC_TDES) Receive Pointer Register
+AT91C_TDES_TNCR           EQU (0xFFFA811C) ;- (PDC_TDES) Transmit Next Counter Register
+AT91C_TDES_TPR            EQU (0xFFFA8108) ;- (PDC_TDES) Transmit Pointer Register
+AT91C_TDES_PTSR           EQU (0xFFFA8124) ;- (PDC_TDES) PDC Transfer Status Register
+AT91C_TDES_PTCR           EQU (0xFFFA8120) ;- (PDC_TDES) PDC Transfer Control Register
+// - ========== Register definition for TDES peripheral ========== 
+AT91C_TDES_KEY2WxR        EQU (0xFFFA8028) ;- (TDES) Key 2 Word x Register
+AT91C_TDES_KEY3WxR        EQU (0xFFFA8030) ;- (TDES) Key 3 Word x Register
+AT91C_TDES_IDR            EQU (0xFFFA8014) ;- (TDES) Interrupt Disable Register
+AT91C_TDES_VR             EQU (0xFFFA80FC) ;- (TDES) TDES Version Register
+AT91C_TDES_IVxR           EQU (0xFFFA8060) ;- (TDES) Initialization Vector x Register
+AT91C_TDES_ODATAxR        EQU (0xFFFA8050) ;- (TDES) Output Data x Register
+AT91C_TDES_IMR            EQU (0xFFFA8018) ;- (TDES) Interrupt Mask Register
+AT91C_TDES_MR             EQU (0xFFFA8004) ;- (TDES) Mode Register
+AT91C_TDES_CR             EQU (0xFFFA8000) ;- (TDES) Control Register
+AT91C_TDES_IER            EQU (0xFFFA8010) ;- (TDES) Interrupt Enable Register
+AT91C_TDES_ISR            EQU (0xFFFA801C) ;- (TDES) Interrupt Status Register
+AT91C_TDES_IDATAxR        EQU (0xFFFA8040) ;- (TDES) Input Data x Register
+AT91C_TDES_KEY1WxR        EQU (0xFFFA8020) ;- (TDES) Key 1 Word x Register
+
+// - *****************************************************************************
+// -               PIO DEFINITIONS FOR AT91SAM7X128
+// - *****************************************************************************
+AT91C_PIO_PA0             EQU (1 <<  0) ;- Pin Controlled by PA0
+AT91C_PA0_RXD0            EQU (AT91C_PIO_PA0) ;-  USART 0 Receive Data
+AT91C_PIO_PA1             EQU (1 <<  1) ;- Pin Controlled by PA1
+AT91C_PA1_TXD0            EQU (AT91C_PIO_PA1) ;-  USART 0 Transmit Data
+AT91C_PIO_PA10            EQU (1 << 10) ;- Pin Controlled by PA10
+AT91C_PA10_TWD            EQU (AT91C_PIO_PA10) ;-  TWI Two-wire Serial Data
+AT91C_PIO_PA11            EQU (1 << 11) ;- Pin Controlled by PA11
+AT91C_PA11_TWCK           EQU (AT91C_PIO_PA11) ;-  TWI Two-wire Serial Clock
+AT91C_PIO_PA12            EQU (1 << 12) ;- Pin Controlled by PA12
+AT91C_PA12_NPCS00         EQU (AT91C_PIO_PA12) ;-  SPI 0 Peripheral Chip Select 0
+AT91C_PIO_PA13            EQU (1 << 13) ;- Pin Controlled by PA13
+AT91C_PA13_NPCS01         EQU (AT91C_PIO_PA13) ;-  SPI 0 Peripheral Chip Select 1
+AT91C_PA13_PCK1           EQU (AT91C_PIO_PA13) ;-  PMC Programmable Clock Output 1
+AT91C_PIO_PA14            EQU (1 << 14) ;- Pin Controlled by PA14
+AT91C_PA14_NPCS02         EQU (AT91C_PIO_PA14) ;-  SPI 0 Peripheral Chip Select 2
+AT91C_PA14_IRQ1           EQU (AT91C_PIO_PA14) ;-  External Interrupt 1
+AT91C_PIO_PA15            EQU (1 << 15) ;- Pin Controlled by PA15
+AT91C_PA15_NPCS03         EQU (AT91C_PIO_PA15) ;-  SPI 0 Peripheral Chip Select 3
+AT91C_PA15_TCLK2          EQU (AT91C_PIO_PA15) ;-  Timer Counter 2 external clock input
+AT91C_PIO_PA16            EQU (1 << 16) ;- Pin Controlled by PA16
+AT91C_PA16_MISO0          EQU (AT91C_PIO_PA16) ;-  SPI 0 Master In Slave
+AT91C_PIO_PA17            EQU (1 << 17) ;- Pin Controlled by PA17
+AT91C_PA17_MOSI0          EQU (AT91C_PIO_PA17) ;-  SPI 0 Master Out Slave
+AT91C_PIO_PA18            EQU (1 << 18) ;- Pin Controlled by PA18
+AT91C_PA18_SPCK0          EQU (AT91C_PIO_PA18) ;-  SPI 0 Serial Clock
+AT91C_PIO_PA19            EQU (1 << 19) ;- Pin Controlled by PA19
+AT91C_PA19_CANRX          EQU (AT91C_PIO_PA19) ;-  CAN Receive
+AT91C_PIO_PA2             EQU (1 <<  2) ;- Pin Controlled by PA2
+AT91C_PA2_SCK0            EQU (AT91C_PIO_PA2) ;-  USART 0 Serial Clock
+AT91C_PA2_NPCS11          EQU (AT91C_PIO_PA2) ;-  SPI 1 Peripheral Chip Select 1
+AT91C_PIO_PA20            EQU (1 << 20) ;- Pin Controlled by PA20
+AT91C_PA20_CANTX          EQU (AT91C_PIO_PA20) ;-  CAN Transmit
+AT91C_PIO_PA21            EQU (1 << 21) ;- Pin Controlled by PA21
+AT91C_PA21_TF             EQU (AT91C_PIO_PA21) ;-  SSC Transmit Frame Sync
+AT91C_PA21_NPCS10         EQU (AT91C_PIO_PA21) ;-  SPI 1 Peripheral Chip Select 0
+AT91C_PIO_PA22            EQU (1 << 22) ;- Pin Controlled by PA22
+AT91C_PA22_TK             EQU (AT91C_PIO_PA22) ;-  SSC Transmit Clock
+AT91C_PA22_SPCK1          EQU (AT91C_PIO_PA22) ;-  SPI 1 Serial Clock
+AT91C_PIO_PA23            EQU (1 << 23) ;- Pin Controlled by PA23
+AT91C_PA23_TD             EQU (AT91C_PIO_PA23) ;-  SSC Transmit data
+AT91C_PA23_MOSI1          EQU (AT91C_PIO_PA23) ;-  SPI 1 Master Out Slave
+AT91C_PIO_PA24            EQU (1 << 24) ;- Pin Controlled by PA24
+AT91C_PA24_RD             EQU (AT91C_PIO_PA24) ;-  SSC Receive Data
+AT91C_PA24_MISO1          EQU (AT91C_PIO_PA24) ;-  SPI 1 Master In Slave
+AT91C_PIO_PA25            EQU (1 << 25) ;- Pin Controlled by PA25
+AT91C_PA25_RK             EQU (AT91C_PIO_PA25) ;-  SSC Receive Clock
+AT91C_PA25_NPCS11         EQU (AT91C_PIO_PA25) ;-  SPI 1 Peripheral Chip Select 1
+AT91C_PIO_PA26            EQU (1 << 26) ;- Pin Controlled by PA26
+AT91C_PA26_RF             EQU (AT91C_PIO_PA26) ;-  SSC Receive Frame Sync
+AT91C_PA26_NPCS12         EQU (AT91C_PIO_PA26) ;-  SPI 1 Peripheral Chip Select 2
+AT91C_PIO_PA27            EQU (1 << 27) ;- Pin Controlled by PA27
+AT91C_PA27_DRXD           EQU (AT91C_PIO_PA27) ;-  DBGU Debug Receive Data
+AT91C_PA27_PCK3           EQU (AT91C_PIO_PA27) ;-  PMC Programmable Clock Output 3
+AT91C_PIO_PA28            EQU (1 << 28) ;- Pin Controlled by PA28
+AT91C_PA28_DTXD           EQU (AT91C_PIO_PA28) ;-  DBGU Debug Transmit Data
+AT91C_PIO_PA29            EQU (1 << 29) ;- Pin Controlled by PA29
+AT91C_PA29_FIQ            EQU (AT91C_PIO_PA29) ;-  AIC Fast Interrupt Input
+AT91C_PA29_NPCS13         EQU (AT91C_PIO_PA29) ;-  SPI 1 Peripheral Chip Select 3
+AT91C_PIO_PA3             EQU (1 <<  3) ;- Pin Controlled by PA3
+AT91C_PA3_RTS0            EQU (AT91C_PIO_PA3) ;-  USART 0 Ready To Send
+AT91C_PA3_NPCS12          EQU (AT91C_PIO_PA3) ;-  SPI 1 Peripheral Chip Select 2
+AT91C_PIO_PA30            EQU (1 << 30) ;- Pin Controlled by PA30
+AT91C_PA30_IRQ0           EQU (AT91C_PIO_PA30) ;-  External Interrupt 0
+AT91C_PA30_PCK2           EQU (AT91C_PIO_PA30) ;-  PMC Programmable Clock Output 2
+AT91C_PIO_PA4             EQU (1 <<  4) ;- Pin Controlled by PA4
+AT91C_PA4_CTS0            EQU (AT91C_PIO_PA4) ;-  USART 0 Clear To Send
+AT91C_PA4_NPCS13          EQU (AT91C_PIO_PA4) ;-  SPI 1 Peripheral Chip Select 3
+AT91C_PIO_PA5             EQU (1 <<  5) ;- Pin Controlled by PA5
+AT91C_PA5_RXD1            EQU (AT91C_PIO_PA5) ;-  USART 1 Receive Data
+AT91C_PIO_PA6             EQU (1 <<  6) ;- Pin Controlled by PA6
+AT91C_PA6_TXD1            EQU (AT91C_PIO_PA6) ;-  USART 1 Transmit Data
+AT91C_PIO_PA7             EQU (1 <<  7) ;- Pin Controlled by PA7
+AT91C_PA7_SCK1            EQU (AT91C_PIO_PA7) ;-  USART 1 Serial Clock
+AT91C_PA7_NPCS01          EQU (AT91C_PIO_PA7) ;-  SPI 0 Peripheral Chip Select 1
+AT91C_PIO_PA8             EQU (1 <<  8) ;- Pin Controlled by PA8
+AT91C_PA8_RTS1            EQU (AT91C_PIO_PA8) ;-  USART 1 Ready To Send
+AT91C_PA8_NPCS02          EQU (AT91C_PIO_PA8) ;-  SPI 0 Peripheral Chip Select 2
+AT91C_PIO_PA9             EQU (1 <<  9) ;- Pin Controlled by PA9
+AT91C_PA9_CTS1            EQU (AT91C_PIO_PA9) ;-  USART 1 Clear To Send
+AT91C_PA9_NPCS03          EQU (AT91C_PIO_PA9) ;-  SPI 0 Peripheral Chip Select 3
+AT91C_PIO_PB0             EQU (1 <<  0) ;- Pin Controlled by PB0
+AT91C_PB0_ETXCK_EREFCK    EQU (AT91C_PIO_PB0) ;-  Ethernet MAC Transmit Clock/Reference Clock
+AT91C_PB0_PCK0            EQU (AT91C_PIO_PB0) ;-  PMC Programmable Clock Output 0
+AT91C_PIO_PB1             EQU (1 <<  1) ;- Pin Controlled by PB1
+AT91C_PB1_ETXEN           EQU (AT91C_PIO_PB1) ;-  Ethernet MAC Transmit Enable
+AT91C_PIO_PB10            EQU (1 << 10) ;- Pin Controlled by PB10
+AT91C_PB10_ETX2           EQU (AT91C_PIO_PB10) ;-  Ethernet MAC Transmit Data 2
+AT91C_PB10_NPCS11         EQU (AT91C_PIO_PB10) ;-  SPI 1 Peripheral Chip Select 1
+AT91C_PIO_PB11            EQU (1 << 11) ;- Pin Controlled by PB11
+AT91C_PB11_ETX3           EQU (AT91C_PIO_PB11) ;-  Ethernet MAC Transmit Data 3
+AT91C_PB11_NPCS12         EQU (AT91C_PIO_PB11) ;-  SPI 1 Peripheral Chip Select 2
+AT91C_PIO_PB12            EQU (1 << 12) ;- Pin Controlled by PB12
+AT91C_PB12_ETXER          EQU (AT91C_PIO_PB12) ;-  Ethernet MAC Transmikt Coding Error
+AT91C_PB12_TCLK0          EQU (AT91C_PIO_PB12) ;-  Timer Counter 0 external clock input
+AT91C_PIO_PB13            EQU (1 << 13) ;- Pin Controlled by PB13
+AT91C_PB13_ERX2           EQU (AT91C_PIO_PB13) ;-  Ethernet MAC Receive Data 2
+AT91C_PB13_NPCS01         EQU (AT91C_PIO_PB13) ;-  SPI 0 Peripheral Chip Select 1
+AT91C_PIO_PB14            EQU (1 << 14) ;- Pin Controlled by PB14
+AT91C_PB14_ERX3           EQU (AT91C_PIO_PB14) ;-  Ethernet MAC Receive Data 3
+AT91C_PB14_NPCS02         EQU (AT91C_PIO_PB14) ;-  SPI 0 Peripheral Chip Select 2
+AT91C_PIO_PB15            EQU (1 << 15) ;- Pin Controlled by PB15
+AT91C_PB15_ERXDV          EQU (AT91C_PIO_PB15) ;-  Ethernet MAC Receive Data Valid
+AT91C_PIO_PB16            EQU (1 << 16) ;- Pin Controlled by PB16
+AT91C_PB16_ECOL           EQU (AT91C_PIO_PB16) ;-  Ethernet MAC Collision Detected
+AT91C_PB16_NPCS13         EQU (AT91C_PIO_PB16) ;-  SPI 1 Peripheral Chip Select 3
+AT91C_PIO_PB17            EQU (1 << 17) ;- Pin Controlled by PB17
+AT91C_PB17_ERXCK          EQU (AT91C_PIO_PB17) ;-  Ethernet MAC Receive Clock
+AT91C_PB17_NPCS03         EQU (AT91C_PIO_PB17) ;-  SPI 0 Peripheral Chip Select 3
+AT91C_PIO_PB18            EQU (1 << 18) ;- Pin Controlled by PB18
+AT91C_PB18_EF100          EQU (AT91C_PIO_PB18) ;-  Ethernet MAC Force 100 Mbits/sec
+AT91C_PB18_ADTRG          EQU (AT91C_PIO_PB18) ;-  ADC External Trigger
+AT91C_PIO_PB19            EQU (1 << 19) ;- Pin Controlled by PB19
+AT91C_PB19_PWM0           EQU (AT91C_PIO_PB19) ;-  PWM Channel 0
+AT91C_PB19_TCLK1          EQU (AT91C_PIO_PB19) ;-  Timer Counter 1 external clock input
+AT91C_PIO_PB2             EQU (1 <<  2) ;- Pin Controlled by PB2
+AT91C_PB2_ETX0            EQU (AT91C_PIO_PB2) ;-  Ethernet MAC Transmit Data 0
+AT91C_PIO_PB20            EQU (1 << 20) ;- Pin Controlled by PB20
+AT91C_PB20_PWM1           EQU (AT91C_PIO_PB20) ;-  PWM Channel 1
+AT91C_PB20_PCK0           EQU (AT91C_PIO_PB20) ;-  PMC Programmable Clock Output 0
+AT91C_PIO_PB21            EQU (1 << 21) ;- Pin Controlled by PB21
+AT91C_PB21_PWM2           EQU (AT91C_PIO_PB21) ;-  PWM Channel 2
+AT91C_PB21_PCK1           EQU (AT91C_PIO_PB21) ;-  PMC Programmable Clock Output 1
+AT91C_PIO_PB22            EQU (1 << 22) ;- Pin Controlled by PB22
+AT91C_PB22_PWM3           EQU (AT91C_PIO_PB22) ;-  PWM Channel 3
+AT91C_PB22_PCK2           EQU (AT91C_PIO_PB22) ;-  PMC Programmable Clock Output 2
+AT91C_PIO_PB23            EQU (1 << 23) ;- Pin Controlled by PB23
+AT91C_PB23_TIOA0          EQU (AT91C_PIO_PB23) ;-  Timer Counter 0 Multipurpose Timer I/O Pin A
+AT91C_PB23_DCD1           EQU (AT91C_PIO_PB23) ;-  USART 1 Data Carrier Detect
+AT91C_PIO_PB24            EQU (1 << 24) ;- Pin Controlled by PB24
+AT91C_PB24_TIOB0          EQU (AT91C_PIO_PB24) ;-  Timer Counter 0 Multipurpose Timer I/O Pin B
+AT91C_PB24_DSR1           EQU (AT91C_PIO_PB24) ;-  USART 1 Data Set ready
+AT91C_PIO_PB25            EQU (1 << 25) ;- Pin Controlled by PB25
+AT91C_PB25_TIOA1          EQU (AT91C_PIO_PB25) ;-  Timer Counter 1 Multipurpose Timer I/O Pin A
+AT91C_PB25_DTR1           EQU (AT91C_PIO_PB25) ;-  USART 1 Data Terminal ready
+AT91C_PIO_PB26            EQU (1 << 26) ;- Pin Controlled by PB26
+AT91C_PB26_TIOB1          EQU (AT91C_PIO_PB26) ;-  Timer Counter 1 Multipurpose Timer I/O Pin B
+AT91C_PB26_RI1            EQU (AT91C_PIO_PB26) ;-  USART 1 Ring Indicator
+AT91C_PIO_PB27            EQU (1 << 27) ;- Pin Controlled by PB27
+AT91C_PB27_TIOA2          EQU (AT91C_PIO_PB27) ;-  Timer Counter 2 Multipurpose Timer I/O Pin A
+AT91C_PB27_PWM0           EQU (AT91C_PIO_PB27) ;-  PWM Channel 0
+AT91C_PIO_PB28            EQU (1 << 28) ;- Pin Controlled by PB28
+AT91C_PB28_TIOB2          EQU (AT91C_PIO_PB28) ;-  Timer Counter 2 Multipurpose Timer I/O Pin B
+AT91C_PB28_PWM1           EQU (AT91C_PIO_PB28) ;-  PWM Channel 1
+AT91C_PIO_PB29            EQU (1 << 29) ;- Pin Controlled by PB29
+AT91C_PB29_PCK1           EQU (AT91C_PIO_PB29) ;-  PMC Programmable Clock Output 1
+AT91C_PB29_PWM2           EQU (AT91C_PIO_PB29) ;-  PWM Channel 2
+AT91C_PIO_PB3             EQU (1 <<  3) ;- Pin Controlled by PB3
+AT91C_PB3_ETX1            EQU (AT91C_PIO_PB3) ;-  Ethernet MAC Transmit Data 1
+AT91C_PIO_PB30            EQU (1 << 30) ;- Pin Controlled by PB30
+AT91C_PB30_PCK2           EQU (AT91C_PIO_PB30) ;-  PMC Programmable Clock Output 2
+AT91C_PB30_PWM3           EQU (AT91C_PIO_PB30) ;-  PWM Channel 3
+AT91C_PIO_PB4             EQU (1 <<  4) ;- Pin Controlled by PB4
+AT91C_PB4_ECRS_ECRSDV     EQU (AT91C_PIO_PB4) ;-  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
+AT91C_PIO_PB5             EQU (1 <<  5) ;- Pin Controlled by PB5
+AT91C_PB5_ERX0            EQU (AT91C_PIO_PB5) ;-  Ethernet MAC Receive Data 0
+AT91C_PIO_PB6             EQU (1 <<  6) ;- Pin Controlled by PB6
+AT91C_PB6_ERX1            EQU (AT91C_PIO_PB6) ;-  Ethernet MAC Receive Data 1
+AT91C_PIO_PB7             EQU (1 <<  7) ;- Pin Controlled by PB7
+AT91C_PB7_ERXER           EQU (AT91C_PIO_PB7) ;-  Ethernet MAC Receive Error
+AT91C_PIO_PB8             EQU (1 <<  8) ;- Pin Controlled by PB8
+AT91C_PB8_EMDC            EQU (AT91C_PIO_PB8) ;-  Ethernet MAC Management Data Clock
+AT91C_PIO_PB9             EQU (1 <<  9) ;- Pin Controlled by PB9
+AT91C_PB9_EMDIO           EQU (AT91C_PIO_PB9) ;-  Ethernet MAC Management Data Input/Output
+
+// - *****************************************************************************
+// -               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X128
+// - *****************************************************************************
+AT91C_ID_FIQ              EQU ( 0) ;- Advanced Interrupt Controller (FIQ)
+AT91C_ID_SYS              EQU ( 1) ;- System Peripheral
+AT91C_ID_PIOA             EQU ( 2) ;- Parallel IO Controller A
+AT91C_ID_PIOB             EQU ( 3) ;- Parallel IO Controller B
+AT91C_ID_SPI0             EQU ( 4) ;- Serial Peripheral Interface 0
+AT91C_ID_SPI1             EQU ( 5) ;- Serial Peripheral Interface 1
+AT91C_ID_US0              EQU ( 6) ;- USART 0
+AT91C_ID_US1              EQU ( 7) ;- USART 1
+AT91C_ID_SSC              EQU ( 8) ;- Serial Synchronous Controller
+AT91C_ID_TWI              EQU ( 9) ;- Two-Wire Interface
+AT91C_ID_PWMC             EQU (10) ;- PWM Controller
+AT91C_ID_UDP              EQU (11) ;- USB Device Port
+AT91C_ID_TC0              EQU (12) ;- Timer Counter 0
+AT91C_ID_TC1              EQU (13) ;- Timer Counter 1
+AT91C_ID_TC2              EQU (14) ;- Timer Counter 2
+AT91C_ID_CAN              EQU (15) ;- Control Area Network Controller
+AT91C_ID_EMAC             EQU (16) ;- Ethernet MAC
+AT91C_ID_ADC              EQU (17) ;- Analog-to-Digital Converter
+AT91C_ID_AES              EQU (18) ;- Advanced Encryption Standard 128-bit
+AT91C_ID_TDES             EQU (19) ;- Triple Data Encryption Standard
+AT91C_ID_20_Reserved      EQU (20) ;- Reserved
+AT91C_ID_21_Reserved      EQU (21) ;- Reserved
+AT91C_ID_22_Reserved      EQU (22) ;- Reserved
+AT91C_ID_23_Reserved      EQU (23) ;- Reserved
+AT91C_ID_24_Reserved      EQU (24) ;- Reserved
+AT91C_ID_25_Reserved      EQU (25) ;- Reserved
+AT91C_ID_26_Reserved      EQU (26) ;- Reserved
+AT91C_ID_27_Reserved      EQU (27) ;- Reserved
+AT91C_ID_28_Reserved      EQU (28) ;- Reserved
+AT91C_ID_29_Reserved      EQU (29) ;- Reserved
+AT91C_ID_IRQ0             EQU (30) ;- Advanced Interrupt Controller (IRQ0)
+AT91C_ID_IRQ1             EQU (31) ;- Advanced Interrupt Controller (IRQ1)
+
+// - *****************************************************************************
+// -               BASE ADDRESS DEFINITIONS FOR AT91SAM7X128
+// - *****************************************************************************
+AT91C_BASE_SYS            EQU (0xFFFFF000) ;- (SYS) Base Address
+AT91C_BASE_AIC            EQU (0xFFFFF000) ;- (AIC) Base Address
+AT91C_BASE_PDC_DBGU       EQU (0xFFFFF300) ;- (PDC_DBGU) Base Address
+AT91C_BASE_DBGU           EQU (0xFFFFF200) ;- (DBGU) Base Address
+AT91C_BASE_PIOA           EQU (0xFFFFF400) ;- (PIOA) Base Address
+AT91C_BASE_PIOB           EQU (0xFFFFF600) ;- (PIOB) Base Address
+AT91C_BASE_CKGR           EQU (0xFFFFFC20) ;- (CKGR) Base Address
+AT91C_BASE_PMC            EQU (0xFFFFFC00) ;- (PMC) Base Address
+AT91C_BASE_RSTC           EQU (0xFFFFFD00) ;- (RSTC) Base Address
+AT91C_BASE_RTTC           EQU (0xFFFFFD20) ;- (RTTC) Base Address
+AT91C_BASE_PITC           EQU (0xFFFFFD30) ;- (PITC) Base Address
+AT91C_BASE_WDTC           EQU (0xFFFFFD40) ;- (WDTC) Base Address
+AT91C_BASE_VREG           EQU (0xFFFFFD60) ;- (VREG) Base Address
+AT91C_BASE_MC             EQU (0xFFFFFF00) ;- (MC) Base Address
+AT91C_BASE_PDC_SPI1       EQU (0xFFFE4100) ;- (PDC_SPI1) Base Address
+AT91C_BASE_SPI1           EQU (0xFFFE4000) ;- (SPI1) Base Address
+AT91C_BASE_PDC_SPI0       EQU (0xFFFE0100) ;- (PDC_SPI0) Base Address
+AT91C_BASE_SPI0           EQU (0xFFFE0000) ;- (SPI0) Base Address
+AT91C_BASE_PDC_US1        EQU (0xFFFC4100) ;- (PDC_US1) Base Address
+AT91C_BASE_US1            EQU (0xFFFC4000) ;- (US1) Base Address
+AT91C_BASE_PDC_US0        EQU (0xFFFC0100) ;- (PDC_US0) Base Address
+AT91C_BASE_US0            EQU (0xFFFC0000) ;- (US0) Base Address
+AT91C_BASE_PDC_SSC        EQU (0xFFFD4100) ;- (PDC_SSC) Base Address
+AT91C_BASE_SSC            EQU (0xFFFD4000) ;- (SSC) Base Address
+AT91C_BASE_TWI            EQU (0xFFFB8000) ;- (TWI) Base Address
+AT91C_BASE_PWMC_CH3       EQU (0xFFFCC260) ;- (PWMC_CH3) Base Address
+AT91C_BASE_PWMC_CH2       EQU (0xFFFCC240) ;- (PWMC_CH2) Base Address
+AT91C_BASE_PWMC_CH1       EQU (0xFFFCC220) ;- (PWMC_CH1) Base Address
+AT91C_BASE_PWMC_CH0       EQU (0xFFFCC200) ;- (PWMC_CH0) Base Address
+AT91C_BASE_PWMC           EQU (0xFFFCC000) ;- (PWMC) Base Address
+AT91C_BASE_UDP            EQU (0xFFFB0000) ;- (UDP) Base Address
+AT91C_BASE_TC0            EQU (0xFFFA0000) ;- (TC0) Base Address
+AT91C_BASE_TC1            EQU (0xFFFA0040) ;- (TC1) Base Address
+AT91C_BASE_TC2            EQU (0xFFFA0080) ;- (TC2) Base Address
+AT91C_BASE_TCB            EQU (0xFFFA0000) ;- (TCB) Base Address
+AT91C_BASE_CAN_MB0        EQU (0xFFFD0200) ;- (CAN_MB0) Base Address
+AT91C_BASE_CAN_MB1        EQU (0xFFFD0220) ;- (CAN_MB1) Base Address
+AT91C_BASE_CAN_MB2        EQU (0xFFFD0240) ;- (CAN_MB2) Base Address
+AT91C_BASE_CAN_MB3        EQU (0xFFFD0260) ;- (CAN_MB3) Base Address
+AT91C_BASE_CAN_MB4        EQU (0xFFFD0280) ;- (CAN_MB4) Base Address
+AT91C_BASE_CAN_MB5        EQU (0xFFFD02A0) ;- (CAN_MB5) Base Address
+AT91C_BASE_CAN_MB6        EQU (0xFFFD02C0) ;- (CAN_MB6) Base Address
+AT91C_BASE_CAN_MB7        EQU (0xFFFD02E0) ;- (CAN_MB7) Base Address
+AT91C_BASE_CAN            EQU (0xFFFD0000) ;- (CAN) Base Address
+AT91C_BASE_EMAC           EQU (0xFFFDC000) ;- (EMAC) Base Address
+AT91C_BASE_PDC_ADC        EQU (0xFFFD8100) ;- (PDC_ADC) Base Address
+AT91C_BASE_ADC            EQU (0xFFFD8000) ;- (ADC) Base Address
+AT91C_BASE_PDC_AES        EQU (0xFFFA4100) ;- (PDC_AES) Base Address
+AT91C_BASE_AES            EQU (0xFFFA4000) ;- (AES) Base Address
+AT91C_BASE_PDC_TDES       EQU (0xFFFA8100) ;- (PDC_TDES) Base Address
+AT91C_BASE_TDES           EQU (0xFFFA8000) ;- (TDES) Base Address
+
+// - *****************************************************************************
+// -               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X128
+// - *****************************************************************************
+AT91C_ISRAM               EQU (0x00200000) ;- Internal SRAM base address
+AT91C_ISRAM_SIZE          EQU (0x00008000) ;- Internal SRAM size in byte (32 Kbyte)
+AT91C_IFLASH              EQU (0x00100000) ;- Internal ROM base address
+AT91C_IFLASH_SIZE         EQU (0x00020000) ;- Internal ROM size in byte (128 Kbyte)
+#endif /* __IAR_SYSTEMS_ASM__ */
+
+
+#endif /* AT91SAM7X128_H */
diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/SrcIAR/ioat91sam7x256.h b/20080212/Demo/uIP_Demo_IAR_ARM7/SrcIAR/ioat91sam7x256.h
new file mode 100644
index 000000000..742f25c6c
--- /dev/null
+++ b/20080212/Demo/uIP_Demo_IAR_ARM7/SrcIAR/ioat91sam7x256.h
@@ -0,0 +1,4700 @@
+// - ----------------------------------------------------------------------------
+// -          ATMEL Microcontroller Software Support  -  ROUSSET  -
+// - ----------------------------------------------------------------------------
+// -  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+// -  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// -  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+// -  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+// -  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// -  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+// -  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// -  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// -  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+// -  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// - ----------------------------------------------------------------------------
+// - File Name           : AT91SAM7X256.h
+// - Object              : AT91SAM7X256 definitions
+// - Generated           : AT91 SW Application Group  05/20/2005 (16:22:29)
+// - 
+// - CVS Reference       : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005//
+// - CVS Reference       : /SYS_SAM7X.pl/1.3/Tue Feb  1 17:01:43 2005//
+// - CVS Reference       : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
+// - CVS Reference       : /PMC_SAM7X.pl/1.4/Tue Feb  8 13:58:10 2005//
+// - CVS Reference       : /RSTC_SAM7X.pl/1.1/Tue Feb  1 16:16:26 2005//
+// - CVS Reference       : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
+// - CVS Reference       : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
+// - CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
+// - CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:18:28 2005//
+// - CVS Reference       : /RTTC_6081A.pl/1.2/Tue Nov  9 14:43:58 2004//
+// - CVS Reference       : /PITC_6079A.pl/1.2/Tue Nov  9 14:43:56 2004//
+// - CVS Reference       : /WDTC_6080A.pl/1.3/Tue Nov  9 14:44:00 2004//
+// - CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:05:48 2005//
+// - CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 08:48:54 2005//
+// - CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
+// - CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
+// - CVS Reference       : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
+// - CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
+// - CVS Reference       : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
+// - CVS Reference       : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
+// - CVS Reference       : /CAN_6019B.pl/1.1/Tue Mar  8 12:42:22 2005//
+// - CVS Reference       : /EMACB_6119A.pl/1.5/Thu Feb  3 15:52:04 2005//
+// - CVS Reference       : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
+// - CVS Reference       : /AES_6149A.pl/1.10/Mon Feb  7 09:44:25 2005//
+// - CVS Reference       : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//
+// - ----------------------------------------------------------------------------
+
+#ifndef AT91SAM7X256_H
+#define AT91SAM7X256_H
+
+#ifdef __IAR_SYSTEMS_ICC__
+
+typedef volatile unsigned int AT91_REG;// Hardware register definition
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR System Peripherals
+// *****************************************************************************
+typedef struct _AT91S_SYS {
+	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
+	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
+	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
+	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
+	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
+	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
+	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
+	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
+	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
+	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
+	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
+	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
+	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
+	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
+	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
+	AT91_REG	 Reserved2[45]; 	// 
+	AT91_REG	 DBGU_CR; 	// Control Register
+	AT91_REG	 DBGU_MR; 	// Mode Register
+	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
+	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
+	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
+	AT91_REG	 DBGU_CSR; 	// Channel Status Register
+	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
+	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
+	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 Reserved3[7]; 	// 
+	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
+	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
+	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
+	AT91_REG	 Reserved4[45]; 	// 
+	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
+	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
+	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
+	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
+	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
+	AT91_REG	 Reserved5[54]; 	// 
+	AT91_REG	 PIOA_PER; 	// PIO Enable Register
+	AT91_REG	 PIOA_PDR; 	// PIO Disable Register
+	AT91_REG	 PIOA_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved6[1]; 	// 
+	AT91_REG	 PIOA_OER; 	// Output Enable Register
+	AT91_REG	 PIOA_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIOA_OSR; 	// Output Status Register
+	AT91_REG	 Reserved7[1]; 	// 
+	AT91_REG	 PIOA_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIOA_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIOA_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved8[1]; 	// 
+	AT91_REG	 PIOA_SODR; 	// Set Output Data Register
+	AT91_REG	 PIOA_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIOA_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIOA_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIOA_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIOA_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIOA_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIOA_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIOA_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIOA_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIOA_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved9[1]; 	// 
+	AT91_REG	 PIOA_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIOA_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIOA_PPUSR; 	// Pull-up Status Register
+	AT91_REG	 Reserved10[1]; 	// 
+	AT91_REG	 PIOA_ASR; 	// Select A Register
+	AT91_REG	 PIOA_BSR; 	// Select B Register
+	AT91_REG	 PIOA_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved11[9]; 	// 
+	AT91_REG	 PIOA_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIOA_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIOA_OWSR; 	// Output Write Status Register
+	AT91_REG	 Reserved12[85]; 	// 
+	AT91_REG	 PIOB_PER; 	// PIO Enable Register
+	AT91_REG	 PIOB_PDR; 	// PIO Disable Register
+	AT91_REG	 PIOB_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved13[1]; 	// 
+	AT91_REG	 PIOB_OER; 	// Output Enable Register
+	AT91_REG	 PIOB_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIOB_OSR; 	// Output Status Register
+	AT91_REG	 Reserved14[1]; 	// 
+	AT91_REG	 PIOB_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIOB_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIOB_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved15[1]; 	// 
+	AT91_REG	 PIOB_SODR; 	// Set Output Data Register
+	AT91_REG	 PIOB_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIOB_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIOB_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIOB_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIOB_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIOB_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIOB_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIOB_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIOB_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIOB_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved16[1]; 	// 
+	AT91_REG	 PIOB_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIOB_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIOB_PPUSR; 	// Pull-up Status Register
+	AT91_REG	 Reserved17[1]; 	// 
+	AT91_REG	 PIOB_ASR; 	// Select A Register
+	AT91_REG	 PIOB_BSR; 	// Select B Register
+	AT91_REG	 PIOB_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved18[9]; 	// 
+	AT91_REG	 PIOB_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIOB_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIOB_OWSR; 	// Output Write Status Register
+	AT91_REG	 Reserved19[341]; 	// 
+	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
+	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
+	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
+	AT91_REG	 Reserved20[1]; 	// 
+	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
+	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
+	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
+	AT91_REG	 Reserved21[1]; 	// 
+	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
+	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 Reserved22[1]; 	// 
+	AT91_REG	 PMC_PLLR; 	// PLL Register
+	AT91_REG	 PMC_MCKR; 	// Master Clock Register
+	AT91_REG	 Reserved23[3]; 	// 
+	AT91_REG	 PMC_PCKR[4]; 	// Programmable Clock Register
+	AT91_REG	 Reserved24[4]; 	// 
+	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
+	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PMC_SR; 	// Status Register
+	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved25[36]; 	// 
+	AT91_REG	 RSTC_RCR; 	// Reset Control Register
+	AT91_REG	 RSTC_RSR; 	// Reset Status Register
+	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
+	AT91_REG	 Reserved26[5]; 	// 
+	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
+	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
+	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
+	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
+	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
+	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
+	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
+	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
+	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
+	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
+	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
+	AT91_REG	 Reserved27[5]; 	// 
+	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
+} AT91S_SYS, *AT91PS_SYS;
+
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
+// *****************************************************************************
+typedef struct _AT91S_AIC {
+	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
+	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
+	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
+	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
+	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
+	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
+	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
+	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
+	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
+	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
+	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
+	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
+	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
+	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
+	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
+} AT91S_AIC, *AT91PS_AIC;
+
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
+#define AT91C_AIC_PRIOR       ((unsigned int) 0x7 <<  0) // (AIC) Priority Level
+#define 	AT91C_AIC_PRIOR_LOWEST               ((unsigned int) 0x0) // (AIC) Lowest priority level
+#define 	AT91C_AIC_PRIOR_HIGHEST              ((unsigned int) 0x7) // (AIC) Highest priority level
+#define AT91C_AIC_SRCTYPE     ((unsigned int) 0x3 <<  5) // (AIC) Interrupt Source Type
+#define 	AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       ((unsigned int) 0x0 <<  5) // (AIC) Internal Sources Code Label High-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        ((unsigned int) 0x0 <<  5) // (AIC) External Sources Code Label Low-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    ((unsigned int) 0x1 <<  5) // (AIC) Internal Sources Code Label Positive Edge triggered
+#define 	AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    ((unsigned int) 0x1 <<  5) // (AIC) External Sources Code Label Negative Edge triggered
+#define 	AT91C_AIC_SRCTYPE_HIGH_LEVEL           ((unsigned int) 0x2 <<  5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_POSITIVE_EDGE        ((unsigned int) 0x3 <<  5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
+#define AT91C_AIC_NFIQ        ((unsigned int) 0x1 <<  0) // (AIC) NFIQ Status
+#define AT91C_AIC_NIRQ        ((unsigned int) 0x1 <<  1) // (AIC) NIRQ Status
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
+#define AT91C_AIC_DCR_PROT    ((unsigned int) 0x1 <<  0) // (AIC) Protection Mode
+#define AT91C_AIC_DCR_GMSK    ((unsigned int) 0x1 <<  1) // (AIC) General Mask
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
+// *****************************************************************************
+typedef struct _AT91S_PDC {
+	AT91_REG	 PDC_RPR; 	// Receive Pointer Register
+	AT91_REG	 PDC_RCR; 	// Receive Counter Register
+	AT91_REG	 PDC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 PDC_TCR; 	// Transmit Counter Register
+	AT91_REG	 PDC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 PDC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 PDC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 PDC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 PDC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 PDC_PTSR; 	// PDC Transfer Status Register
+} AT91S_PDC, *AT91PS_PDC;
+
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
+#define AT91C_PDC_RXTEN       ((unsigned int) 0x1 <<  0) // (PDC) Receiver Transfer Enable
+#define AT91C_PDC_RXTDIS      ((unsigned int) 0x1 <<  1) // (PDC) Receiver Transfer Disable
+#define AT91C_PDC_TXTEN       ((unsigned int) 0x1 <<  8) // (PDC) Transmitter Transfer Enable
+#define AT91C_PDC_TXTDIS      ((unsigned int) 0x1 <<  9) // (PDC) Transmitter Transfer Disable
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Debug Unit
+// *****************************************************************************
+typedef struct _AT91S_DBGU {
+	AT91_REG	 DBGU_CR; 	// Control Register
+	AT91_REG	 DBGU_MR; 	// Mode Register
+	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
+	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
+	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
+	AT91_REG	 DBGU_CSR; 	// Channel Status Register
+	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
+	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
+	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 Reserved0[7]; 	// 
+	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
+	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
+	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
+	AT91_REG	 Reserved1[45]; 	// 
+	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
+	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
+	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
+	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
+	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
+} AT91S_DBGU, *AT91PS_DBGU;
+
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
+#define AT91C_US_RSTRX        ((unsigned int) 0x1 <<  2) // (DBGU) Reset Receiver
+#define AT91C_US_RSTTX        ((unsigned int) 0x1 <<  3) // (DBGU) Reset Transmitter
+#define AT91C_US_RXEN         ((unsigned int) 0x1 <<  4) // (DBGU) Receiver Enable
+#define AT91C_US_RXDIS        ((unsigned int) 0x1 <<  5) // (DBGU) Receiver Disable
+#define AT91C_US_TXEN         ((unsigned int) 0x1 <<  6) // (DBGU) Transmitter Enable
+#define AT91C_US_TXDIS        ((unsigned int) 0x1 <<  7) // (DBGU) Transmitter Disable
+#define AT91C_US_RSTSTA       ((unsigned int) 0x1 <<  8) // (DBGU) Reset Status Bits
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
+#define AT91C_US_PAR          ((unsigned int) 0x7 <<  9) // (DBGU) Parity type
+#define 	AT91C_US_PAR_EVEN                 ((unsigned int) 0x0 <<  9) // (DBGU) Even Parity
+#define 	AT91C_US_PAR_ODD                  ((unsigned int) 0x1 <<  9) // (DBGU) Odd Parity
+#define 	AT91C_US_PAR_SPACE                ((unsigned int) 0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
+#define 	AT91C_US_PAR_MARK                 ((unsigned int) 0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
+#define 	AT91C_US_PAR_NONE                 ((unsigned int) 0x4 <<  9) // (DBGU) No Parity
+#define 	AT91C_US_PAR_MULTI_DROP           ((unsigned int) 0x6 <<  9) // (DBGU) Multi-drop mode
+#define AT91C_US_CHMODE       ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode
+#define 	AT91C_US_CHMODE_NORMAL               ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+#define 	AT91C_US_CHMODE_AUTO                 ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+#define 	AT91C_US_CHMODE_LOCAL                ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+#define 	AT91C_US_CHMODE_REMOTE               ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+#define AT91C_US_RXRDY        ((unsigned int) 0x1 <<  0) // (DBGU) RXRDY Interrupt
+#define AT91C_US_TXRDY        ((unsigned int) 0x1 <<  1) // (DBGU) TXRDY Interrupt
+#define AT91C_US_ENDRX        ((unsigned int) 0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
+#define AT91C_US_ENDTX        ((unsigned int) 0x1 <<  4) // (DBGU) End of Transmit Interrupt
+#define AT91C_US_OVRE         ((unsigned int) 0x1 <<  5) // (DBGU) Overrun Interrupt
+#define AT91C_US_FRAME        ((unsigned int) 0x1 <<  6) // (DBGU) Framing Error Interrupt
+#define AT91C_US_PARE         ((unsigned int) 0x1 <<  7) // (DBGU) Parity Error Interrupt
+#define AT91C_US_TXEMPTY      ((unsigned int) 0x1 <<  9) // (DBGU) TXEMPTY Interrupt
+#define AT91C_US_TXBUFE       ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt
+#define AT91C_US_RXBUFF       ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt
+#define AT91C_US_COMM_TX      ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt
+#define AT91C_US_COMM_RX      ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
+#define AT91C_US_FORCE_NTRST  ((unsigned int) 0x1 <<  0) // (DBGU) Force NTRST in JTAG
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
+// *****************************************************************************
+typedef struct _AT91S_PIO {
+	AT91_REG	 PIO_PER; 	// PIO Enable Register
+	AT91_REG	 PIO_PDR; 	// PIO Disable Register
+	AT91_REG	 PIO_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 PIO_OER; 	// Output Enable Register
+	AT91_REG	 PIO_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIO_OSR; 	// Output Status Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 PIO_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIO_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIO_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved2[1]; 	// 
+	AT91_REG	 PIO_SODR; 	// Set Output Data Register
+	AT91_REG	 PIO_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIO_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIO_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIO_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIO_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIO_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIO_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIO_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIO_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIO_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved3[1]; 	// 
+	AT91_REG	 PIO_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIO_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIO_PPUSR; 	// Pull-up Status Register
+	AT91_REG	 Reserved4[1]; 	// 
+	AT91_REG	 PIO_ASR; 	// Select A Register
+	AT91_REG	 PIO_BSR; 	// Select B Register
+	AT91_REG	 PIO_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved5[9]; 	// 
+	AT91_REG	 PIO_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIO_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIO_OWSR; 	// Output Write Status Register
+} AT91S_PIO, *AT91PS_PIO;
+
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
+// *****************************************************************************
+typedef struct _AT91S_CKGR {
+	AT91_REG	 CKGR_MOR; 	// Main Oscillator Register
+	AT91_REG	 CKGR_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 CKGR_PLLR; 	// PLL Register
+} AT91S_CKGR, *AT91PS_CKGR;
+
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 
+#define AT91C_CKGR_MOSCEN     ((unsigned int) 0x1 <<  0) // (CKGR) Main Oscillator Enable
+#define AT91C_CKGR_OSCBYPASS  ((unsigned int) 0x1 <<  1) // (CKGR) Main Oscillator Bypass
+#define AT91C_CKGR_OSCOUNT    ((unsigned int) 0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 
+#define AT91C_CKGR_MAINF      ((unsigned int) 0xFFFF <<  0) // (CKGR) Main Clock Frequency
+#define AT91C_CKGR_MAINRDY    ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
+// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- 
+#define AT91C_CKGR_DIV        ((unsigned int) 0xFF <<  0) // (CKGR) Divider Selected
+#define 	AT91C_CKGR_DIV_0                    ((unsigned int) 0x0) // (CKGR) Divider output is 0
+#define 	AT91C_CKGR_DIV_BYPASS               ((unsigned int) 0x1) // (CKGR) Divider is bypassed
+#define AT91C_CKGR_PLLCOUNT   ((unsigned int) 0x3F <<  8) // (CKGR) PLL Counter
+#define AT91C_CKGR_OUT        ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range
+#define 	AT91C_CKGR_OUT_0                    ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_1                    ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_2                    ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_3                    ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_MUL        ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier
+#define AT91C_CKGR_USBDIV     ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks
+#define 	AT91C_CKGR_USBDIV_0                    ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output
+#define 	AT91C_CKGR_USBDIV_1                    ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
+#define 	AT91C_CKGR_USBDIV_2                    ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Power Management Controler
+// *****************************************************************************
+typedef struct _AT91S_PMC {
+	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
+	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
+	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
+	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
+	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
+	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 Reserved2[1]; 	// 
+	AT91_REG	 PMC_PLLR; 	// PLL Register
+	AT91_REG	 PMC_MCKR; 	// Master Clock Register
+	AT91_REG	 Reserved3[3]; 	// 
+	AT91_REG	 PMC_PCKR[4]; 	// Programmable Clock Register
+	AT91_REG	 Reserved4[4]; 	// 
+	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
+	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PMC_SR; 	// Status Register
+	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
+} AT91S_PMC, *AT91PS_PMC;
+
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
+#define AT91C_PMC_PCK         ((unsigned int) 0x1 <<  0) // (PMC) Processor Clock
+#define AT91C_PMC_UDP         ((unsigned int) 0x1 <<  7) // (PMC) USB Device Port Clock
+#define AT91C_PMC_PCK0        ((unsigned int) 0x1 <<  8) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK1        ((unsigned int) 0x1 <<  9) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK2        ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK3        ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 
+// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- 
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
+#define AT91C_PMC_CSS         ((unsigned int) 0x3 <<  0) // (PMC) Programmable Clock Selection
+#define 	AT91C_PMC_CSS_SLOW_CLK             ((unsigned int) 0x0) // (PMC) Slow Clock is selected
+#define 	AT91C_PMC_CSS_MAIN_CLK             ((unsigned int) 0x1) // (PMC) Main Clock is selected
+#define 	AT91C_PMC_CSS_PLL_CLK              ((unsigned int) 0x3) // (PMC) Clock from PLL is selected
+#define AT91C_PMC_PRES        ((unsigned int) 0x7 <<  2) // (PMC) Programmable Clock Prescaler
+#define 	AT91C_PMC_PRES_CLK                  ((unsigned int) 0x0 <<  2) // (PMC) Selected clock
+#define 	AT91C_PMC_PRES_CLK_2                ((unsigned int) 0x1 <<  2) // (PMC) Selected clock divided by 2
+#define 	AT91C_PMC_PRES_CLK_4                ((unsigned int) 0x2 <<  2) // (PMC) Selected clock divided by 4
+#define 	AT91C_PMC_PRES_CLK_8                ((unsigned int) 0x3 <<  2) // (PMC) Selected clock divided by 8
+#define 	AT91C_PMC_PRES_CLK_16               ((unsigned int) 0x4 <<  2) // (PMC) Selected clock divided by 16
+#define 	AT91C_PMC_PRES_CLK_32               ((unsigned int) 0x5 <<  2) // (PMC) Selected clock divided by 32
+#define 	AT91C_PMC_PRES_CLK_64               ((unsigned int) 0x6 <<  2) // (PMC) Selected clock divided by 64
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
+#define AT91C_PMC_MOSCS       ((unsigned int) 0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCK        ((unsigned int) 0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask
+#define AT91C_PMC_MCKRDY      ((unsigned int) 0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK0RDY     ((unsigned int) 0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK1RDY     ((unsigned int) 0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK2RDY     ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK3RDY     ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_RSTC {
+	AT91_REG	 RSTC_RCR; 	// Reset Control Register
+	AT91_REG	 RSTC_RSR; 	// Reset Status Register
+	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
+} AT91S_RSTC, *AT91PS_RSTC;
+
+// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 
+#define AT91C_RSTC_PROCRST    ((unsigned int) 0x1 <<  0) // (RSTC) Processor Reset
+#define AT91C_RSTC_PERRST     ((unsigned int) 0x1 <<  2) // (RSTC) Peripheral Reset
+#define AT91C_RSTC_EXTRST     ((unsigned int) 0x1 <<  3) // (RSTC) External Reset
+#define AT91C_RSTC_KEY        ((unsigned int) 0xFF << 24) // (RSTC) Password
+// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 
+#define AT91C_RSTC_URSTS      ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Status
+#define AT91C_RSTC_BODSTS     ((unsigned int) 0x1 <<  1) // (RSTC) Brownout Detection Status
+#define AT91C_RSTC_RSTTYP     ((unsigned int) 0x7 <<  8) // (RSTC) Reset Type
+#define 	AT91C_RSTC_RSTTYP_POWERUP              ((unsigned int) 0x0 <<  8) // (RSTC) Power-up Reset. VDDCORE rising.
+#define 	AT91C_RSTC_RSTTYP_WAKEUP               ((unsigned int) 0x1 <<  8) // (RSTC) WakeUp Reset. VDDCORE rising.
+#define 	AT91C_RSTC_RSTTYP_WATCHDOG             ((unsigned int) 0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
+#define 	AT91C_RSTC_RSTTYP_SOFTWARE             ((unsigned int) 0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
+#define 	AT91C_RSTC_RSTTYP_USER                 ((unsigned int) 0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
+#define 	AT91C_RSTC_RSTTYP_BROWNOUT             ((unsigned int) 0x5 <<  8) // (RSTC) Brownout Reset occured.
+#define AT91C_RSTC_NRSTL      ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level
+#define AT91C_RSTC_SRCMP      ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.
+// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 
+#define AT91C_RSTC_URSTEN     ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Enable
+#define AT91C_RSTC_URSTIEN    ((unsigned int) 0x1 <<  4) // (RSTC) User Reset Interrupt Enable
+#define AT91C_RSTC_ERSTL      ((unsigned int) 0xF <<  8) // (RSTC) User Reset Enable
+#define AT91C_RSTC_BODIEN     ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_RTTC {
+	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
+	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
+	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
+	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
+} AT91S_RTTC, *AT91PS_RTTC;
+
+// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 
+#define AT91C_RTTC_RTPRES     ((unsigned int) 0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
+#define AT91C_RTTC_ALMIEN     ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable
+#define AT91C_RTTC_RTTINCIEN  ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
+#define AT91C_RTTC_RTTRST     ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart
+// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 
+#define AT91C_RTTC_ALMV       ((unsigned int) 0x0 <<  0) // (RTTC) Alarm Value
+// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 
+#define AT91C_RTTC_CRTV       ((unsigned int) 0x0 <<  0) // (RTTC) Current Real-time Value
+// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 
+#define AT91C_RTTC_ALMS       ((unsigned int) 0x1 <<  0) // (RTTC) Real-time Alarm Status
+#define AT91C_RTTC_RTTINC     ((unsigned int) 0x1 <<  1) // (RTTC) Real-time Timer Increment
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_PITC {
+	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
+	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
+	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
+	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
+} AT91S_PITC, *AT91PS_PITC;
+
+// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
+#define AT91C_PITC_PIV        ((unsigned int) 0xFFFFF <<  0) // (PITC) Periodic Interval Value
+#define AT91C_PITC_PITEN      ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled
+#define AT91C_PITC_PITIEN     ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
+// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
+#define AT91C_PITC_PITS       ((unsigned int) 0x1 <<  0) // (PITC) Periodic Interval Timer Status
+// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
+#define AT91C_PITC_CPIV       ((unsigned int) 0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
+#define AT91C_PITC_PICNT      ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter
+// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_WDTC {
+	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
+	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
+	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
+} AT91S_WDTC, *AT91PS_WDTC;
+
+// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 
+#define AT91C_WDTC_WDRSTT     ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Restart
+#define AT91C_WDTC_KEY        ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password
+// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 
+#define AT91C_WDTC_WDV        ((unsigned int) 0xFFF <<  0) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDFIEN     ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
+#define AT91C_WDTC_WDRSTEN    ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable
+#define AT91C_WDTC_WDRPROC    ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDDIS      ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable
+#define AT91C_WDTC_WDD        ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value
+#define AT91C_WDTC_WDDBGHLT   ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt
+#define AT91C_WDTC_WDIDLEHLT  ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt
+// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 
+#define AT91C_WDTC_WDUNF      ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Underflow
+#define AT91C_WDTC_WDERR      ((unsigned int) 0x1 <<  1) // (WDTC) Watchdog Error
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_VREG {
+	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
+} AT91S_VREG, *AT91PS_VREG;
+
+// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- 
+#define AT91C_VREG_PSTDBY     ((unsigned int) 0x1 <<  0) // (VREG) Voltage Regulator Power Standby Mode
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_MC {
+	AT91_REG	 MC_RCR; 	// MC Remap Control Register
+	AT91_REG	 MC_ASR; 	// MC Abort Status Register
+	AT91_REG	 MC_AASR; 	// MC Abort Address Status Register
+	AT91_REG	 Reserved0[21]; 	// 
+	AT91_REG	 MC_FMR; 	// MC Flash Mode Register
+	AT91_REG	 MC_FCR; 	// MC Flash Command Register
+	AT91_REG	 MC_FSR; 	// MC Flash Status Register
+} AT91S_MC, *AT91PS_MC;
+
+// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 
+#define AT91C_MC_RCB          ((unsigned int) 0x1 <<  0) // (MC) Remap Command Bit
+// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 
+#define AT91C_MC_UNDADD       ((unsigned int) 0x1 <<  0) // (MC) Undefined Addess Abort Status
+#define AT91C_MC_MISADD       ((unsigned int) 0x1 <<  1) // (MC) Misaligned Addess Abort Status
+#define AT91C_MC_ABTSZ        ((unsigned int) 0x3 <<  8) // (MC) Abort Size Status
+#define 	AT91C_MC_ABTSZ_BYTE                 ((unsigned int) 0x0 <<  8) // (MC) Byte
+#define 	AT91C_MC_ABTSZ_HWORD                ((unsigned int) 0x1 <<  8) // (MC) Half-word
+#define 	AT91C_MC_ABTSZ_WORD                 ((unsigned int) 0x2 <<  8) // (MC) Word
+#define AT91C_MC_ABTTYP       ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
+#define 	AT91C_MC_ABTTYP_DATAR                ((unsigned int) 0x0 << 10) // (MC) Data Read
+#define 	AT91C_MC_ABTTYP_DATAW                ((unsigned int) 0x1 << 10) // (MC) Data Write
+#define 	AT91C_MC_ABTTYP_FETCH                ((unsigned int) 0x2 << 10) // (MC) Code Fetch
+#define AT91C_MC_MST0         ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
+#define AT91C_MC_MST1         ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
+#define AT91C_MC_SVMST0       ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
+#define AT91C_MC_SVMST1       ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
+// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- 
+#define AT91C_MC_FRDY         ((unsigned int) 0x1 <<  0) // (MC) Flash Ready
+#define AT91C_MC_LOCKE        ((unsigned int) 0x1 <<  2) // (MC) Lock Error
+#define AT91C_MC_PROGE        ((unsigned int) 0x1 <<  3) // (MC) Programming Error
+#define AT91C_MC_NEBP         ((unsigned int) 0x1 <<  7) // (MC) No Erase Before Programming
+#define AT91C_MC_FWS          ((unsigned int) 0x3 <<  8) // (MC) Flash Wait State
+#define 	AT91C_MC_FWS_0FWS                 ((unsigned int) 0x0 <<  8) // (MC) 1 cycle for Read, 2 for Write operations
+#define 	AT91C_MC_FWS_1FWS                 ((unsigned int) 0x1 <<  8) // (MC) 2 cycles for Read, 3 for Write operations
+#define 	AT91C_MC_FWS_2FWS                 ((unsigned int) 0x2 <<  8) // (MC) 3 cycles for Read, 4 for Write operations
+#define 	AT91C_MC_FWS_3FWS                 ((unsigned int) 0x3 <<  8) // (MC) 4 cycles for Read, 4 for Write operations
+#define AT91C_MC_FMCN         ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number
+// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- 
+#define AT91C_MC_FCMD         ((unsigned int) 0xF <<  0) // (MC) Flash Command
+#define 	AT91C_MC_FCMD_START_PROG           ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.
+#define 	AT91C_MC_FCMD_LOCK                 ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define 	AT91C_MC_FCMD_PROG_AND_LOCK        ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
+#define 	AT91C_MC_FCMD_UNLOCK               ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define 	AT91C_MC_FCMD_ERASE_ALL            ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
+#define 	AT91C_MC_FCMD_SET_GP_NVM           ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.
+#define 	AT91C_MC_FCMD_CLR_GP_NVM           ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.
+#define 	AT91C_MC_FCMD_SET_SECURITY         ((unsigned int) 0xF) // (MC) Set Security Bit.
+#define AT91C_MC_PAGEN        ((unsigned int) 0x3FF <<  8) // (MC) Page Number
+#define AT91C_MC_KEY          ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key
+// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- 
+#define AT91C_MC_SECURITY     ((unsigned int) 0x1 <<  4) // (MC) Security Bit Status
+#define AT91C_MC_GPNVM0       ((unsigned int) 0x1 <<  8) // (MC) Sector 0 Lock Status
+#define AT91C_MC_GPNVM1       ((unsigned int) 0x1 <<  9) // (MC) Sector 1 Lock Status
+#define AT91C_MC_GPNVM2       ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status
+#define AT91C_MC_GPNVM3       ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status
+#define AT91C_MC_GPNVM4       ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status
+#define AT91C_MC_GPNVM5       ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status
+#define AT91C_MC_GPNVM6       ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status
+#define AT91C_MC_GPNVM7       ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS0       ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status
+#define AT91C_MC_LOCKS1       ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status
+#define AT91C_MC_LOCKS2       ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status
+#define AT91C_MC_LOCKS3       ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status
+#define AT91C_MC_LOCKS4       ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status
+#define AT91C_MC_LOCKS5       ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status
+#define AT91C_MC_LOCKS6       ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status
+#define AT91C_MC_LOCKS7       ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS8       ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status
+#define AT91C_MC_LOCKS9       ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status
+#define AT91C_MC_LOCKS10      ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status
+#define AT91C_MC_LOCKS11      ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status
+#define AT91C_MC_LOCKS12      ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status
+#define AT91C_MC_LOCKS13      ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status
+#define AT91C_MC_LOCKS14      ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status
+#define AT91C_MC_LOCKS15      ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
+// *****************************************************************************
+typedef struct _AT91S_SPI {
+	AT91_REG	 SPI_CR; 	// Control Register
+	AT91_REG	 SPI_MR; 	// Mode Register
+	AT91_REG	 SPI_RDR; 	// Receive Data Register
+	AT91_REG	 SPI_TDR; 	// Transmit Data Register
+	AT91_REG	 SPI_SR; 	// Status Register
+	AT91_REG	 SPI_IER; 	// Interrupt Enable Register
+	AT91_REG	 SPI_IDR; 	// Interrupt Disable Register
+	AT91_REG	 SPI_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved0[4]; 	// 
+	AT91_REG	 SPI_CSR[4]; 	// Chip Select Register
+	AT91_REG	 Reserved1[48]; 	// 
+	AT91_REG	 SPI_RPR; 	// Receive Pointer Register
+	AT91_REG	 SPI_RCR; 	// Receive Counter Register
+	AT91_REG	 SPI_TPR; 	// Transmit Pointer Register
+	AT91_REG	 SPI_TCR; 	// Transmit Counter Register
+	AT91_REG	 SPI_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 SPI_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 SPI_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 SPI_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 SPI_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 SPI_PTSR; 	// PDC Transfer Status Register
+} AT91S_SPI, *AT91PS_SPI;
+
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
+#define AT91C_SPI_SPIEN       ((unsigned int) 0x1 <<  0) // (SPI) SPI Enable
+#define AT91C_SPI_SPIDIS      ((unsigned int) 0x1 <<  1) // (SPI) SPI Disable
+#define AT91C_SPI_SWRST       ((unsigned int) 0x1 <<  7) // (SPI) SPI Software reset
+#define AT91C_SPI_LASTXFER    ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
+#define AT91C_SPI_MSTR        ((unsigned int) 0x1 <<  0) // (SPI) Master/Slave Mode
+#define AT91C_SPI_PS          ((unsigned int) 0x1 <<  1) // (SPI) Peripheral Select
+#define 	AT91C_SPI_PS_FIXED                ((unsigned int) 0x0 <<  1) // (SPI) Fixed Peripheral Select
+#define 	AT91C_SPI_PS_VARIABLE             ((unsigned int) 0x1 <<  1) // (SPI) Variable Peripheral Select
+#define AT91C_SPI_PCSDEC      ((unsigned int) 0x1 <<  2) // (SPI) Chip Select Decode
+#define AT91C_SPI_FDIV        ((unsigned int) 0x1 <<  3) // (SPI) Clock Selection
+#define AT91C_SPI_MODFDIS     ((unsigned int) 0x1 <<  4) // (SPI) Mode Fault Detection
+#define AT91C_SPI_LLB         ((unsigned int) 0x1 <<  7) // (SPI) Clock Selection
+#define AT91C_SPI_PCS         ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
+#define AT91C_SPI_DLYBCS      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
+#define AT91C_SPI_RD          ((unsigned int) 0xFFFF <<  0) // (SPI) Receive Data
+#define AT91C_SPI_RPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
+#define AT91C_SPI_TD          ((unsigned int) 0xFFFF <<  0) // (SPI) Transmit Data
+#define AT91C_SPI_TPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
+#define AT91C_SPI_RDRF        ((unsigned int) 0x1 <<  0) // (SPI) Receive Data Register Full
+#define AT91C_SPI_TDRE        ((unsigned int) 0x1 <<  1) // (SPI) Transmit Data Register Empty
+#define AT91C_SPI_MODF        ((unsigned int) 0x1 <<  2) // (SPI) Mode Fault Error
+#define AT91C_SPI_OVRES       ((unsigned int) 0x1 <<  3) // (SPI) Overrun Error Status
+#define AT91C_SPI_ENDRX       ((unsigned int) 0x1 <<  4) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_ENDTX       ((unsigned int) 0x1 <<  5) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_RXBUFF      ((unsigned int) 0x1 <<  6) // (SPI) RXBUFF Interrupt
+#define AT91C_SPI_TXBUFE      ((unsigned int) 0x1 <<  7) // (SPI) TXBUFE Interrupt
+#define AT91C_SPI_NSSR        ((unsigned int) 0x1 <<  8) // (SPI) NSSR Interrupt
+#define AT91C_SPI_TXEMPTY     ((unsigned int) 0x1 <<  9) // (SPI) TXEMPTY Interrupt
+#define AT91C_SPI_SPIENS      ((unsigned int) 0x1 << 16) // (SPI) Enable Status
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
+#define AT91C_SPI_CPOL        ((unsigned int) 0x1 <<  0) // (SPI) Clock Polarity
+#define AT91C_SPI_NCPHA       ((unsigned int) 0x1 <<  1) // (SPI) Clock Phase
+#define AT91C_SPI_CSAAT       ((unsigned int) 0x1 <<  3) // (SPI) Chip Select Active After Transfer
+#define AT91C_SPI_BITS        ((unsigned int) 0xF <<  4) // (SPI) Bits Per Transfer
+#define 	AT91C_SPI_BITS_8                    ((unsigned int) 0x0 <<  4) // (SPI) 8 Bits Per transfer
+#define 	AT91C_SPI_BITS_9                    ((unsigned int) 0x1 <<  4) // (SPI) 9 Bits Per transfer
+#define 	AT91C_SPI_BITS_10                   ((unsigned int) 0x2 <<  4) // (SPI) 10 Bits Per transfer
+#define 	AT91C_SPI_BITS_11                   ((unsigned int) 0x3 <<  4) // (SPI) 11 Bits Per transfer
+#define 	AT91C_SPI_BITS_12                   ((unsigned int) 0x4 <<  4) // (SPI) 12 Bits Per transfer
+#define 	AT91C_SPI_BITS_13                   ((unsigned int) 0x5 <<  4) // (SPI) 13 Bits Per transfer
+#define 	AT91C_SPI_BITS_14                   ((unsigned int) 0x6 <<  4) // (SPI) 14 Bits Per transfer
+#define 	AT91C_SPI_BITS_15                   ((unsigned int) 0x7 <<  4) // (SPI) 15 Bits Per transfer
+#define 	AT91C_SPI_BITS_16                   ((unsigned int) 0x8 <<  4) // (SPI) 16 Bits Per transfer
+#define AT91C_SPI_SCBR        ((unsigned int) 0xFF <<  8) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBS       ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK
+#define AT91C_SPI_DLYBCT      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Usart
+// *****************************************************************************
+typedef struct _AT91S_USART {
+	AT91_REG	 US_CR; 	// Control Register
+	AT91_REG	 US_MR; 	// Mode Register
+	AT91_REG	 US_IER; 	// Interrupt Enable Register
+	AT91_REG	 US_IDR; 	// Interrupt Disable Register
+	AT91_REG	 US_IMR; 	// Interrupt Mask Register
+	AT91_REG	 US_CSR; 	// Channel Status Register
+	AT91_REG	 US_RHR; 	// Receiver Holding Register
+	AT91_REG	 US_THR; 	// Transmitter Holding Register
+	AT91_REG	 US_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 US_RTOR; 	// Receiver Time-out Register
+	AT91_REG	 US_TTGR; 	// Transmitter Time-guard Register
+	AT91_REG	 Reserved0[5]; 	// 
+	AT91_REG	 US_FIDI; 	// FI_DI_Ratio Register
+	AT91_REG	 US_NER; 	// Nb Errors Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 US_IF; 	// IRDA_FILTER Register
+	AT91_REG	 Reserved2[44]; 	// 
+	AT91_REG	 US_RPR; 	// Receive Pointer Register
+	AT91_REG	 US_RCR; 	// Receive Counter Register
+	AT91_REG	 US_TPR; 	// Transmit Pointer Register
+	AT91_REG	 US_TCR; 	// Transmit Counter Register
+	AT91_REG	 US_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 US_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 US_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 US_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 US_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 US_PTSR; 	// PDC Transfer Status Register
+} AT91S_USART, *AT91PS_USART;
+
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
+#define AT91C_US_STTBRK       ((unsigned int) 0x1 <<  9) // (USART) Start Break
+#define AT91C_US_STPBRK       ((unsigned int) 0x1 << 10) // (USART) Stop Break
+#define AT91C_US_STTTO        ((unsigned int) 0x1 << 11) // (USART) Start Time-out
+#define AT91C_US_SENDA        ((unsigned int) 0x1 << 12) // (USART) Send Address
+#define AT91C_US_RSTIT        ((unsigned int) 0x1 << 13) // (USART) Reset Iterations
+#define AT91C_US_RSTNACK      ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge
+#define AT91C_US_RETTO        ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out
+#define AT91C_US_DTREN        ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable
+#define AT91C_US_DTRDIS       ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable
+#define AT91C_US_RTSEN        ((unsigned int) 0x1 << 18) // (USART) Request to Send enable
+#define AT91C_US_RTSDIS       ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
+#define AT91C_US_USMODE       ((unsigned int) 0xF <<  0) // (USART) Usart mode
+#define 	AT91C_US_USMODE_NORMAL               ((unsigned int) 0x0) // (USART) Normal
+#define 	AT91C_US_USMODE_RS485                ((unsigned int) 0x1) // (USART) RS485
+#define 	AT91C_US_USMODE_HWHSH                ((unsigned int) 0x2) // (USART) Hardware Handshaking
+#define 	AT91C_US_USMODE_MODEM                ((unsigned int) 0x3) // (USART) Modem
+#define 	AT91C_US_USMODE_ISO7816_0            ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0
+#define 	AT91C_US_USMODE_ISO7816_1            ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1
+#define 	AT91C_US_USMODE_IRDA                 ((unsigned int) 0x8) // (USART) IrDA
+#define 	AT91C_US_USMODE_SWHSH                ((unsigned int) 0xC) // (USART) Software Handshaking
+#define AT91C_US_CLKS         ((unsigned int) 0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CLKS_CLOCK                ((unsigned int) 0x0 <<  4) // (USART) Clock
+#define 	AT91C_US_CLKS_FDIV1                ((unsigned int) 0x1 <<  4) // (USART) fdiv1
+#define 	AT91C_US_CLKS_SLOW                 ((unsigned int) 0x2 <<  4) // (USART) slow_clock (ARM)
+#define 	AT91C_US_CLKS_EXT                  ((unsigned int) 0x3 <<  4) // (USART) External (SCK)
+#define AT91C_US_CHRL         ((unsigned int) 0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CHRL_5_BITS               ((unsigned int) 0x0 <<  6) // (USART) Character Length: 5 bits
+#define 	AT91C_US_CHRL_6_BITS               ((unsigned int) 0x1 <<  6) // (USART) Character Length: 6 bits
+#define 	AT91C_US_CHRL_7_BITS               ((unsigned int) 0x2 <<  6) // (USART) Character Length: 7 bits
+#define 	AT91C_US_CHRL_8_BITS               ((unsigned int) 0x3 <<  6) // (USART) Character Length: 8 bits
+#define AT91C_US_SYNC         ((unsigned int) 0x1 <<  8) // (USART) Synchronous Mode Select
+#define AT91C_US_NBSTOP       ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
+#define 	AT91C_US_NBSTOP_1_BIT                ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
+#define 	AT91C_US_NBSTOP_15_BIT               ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+#define 	AT91C_US_NBSTOP_2_BIT                ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
+#define AT91C_US_MSBF         ((unsigned int) 0x1 << 16) // (USART) Bit Order
+#define AT91C_US_MODE9        ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
+#define AT91C_US_CKLO         ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
+#define AT91C_US_OVER         ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode
+#define AT91C_US_INACK        ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge
+#define AT91C_US_DSNACK       ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK
+#define AT91C_US_MAX_ITER     ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions
+#define AT91C_US_FILTER       ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+#define AT91C_US_RXBRK        ((unsigned int) 0x1 <<  2) // (USART) Break Received/End of Break
+#define AT91C_US_TIMEOUT      ((unsigned int) 0x1 <<  8) // (USART) Receiver Time-out
+#define AT91C_US_ITERATION    ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached
+#define AT91C_US_NACK         ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge
+#define AT91C_US_RIIC         ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag
+#define AT91C_US_DSRIC        ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag
+#define AT91C_US_DCDIC        ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag
+#define AT91C_US_CTSIC        ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 
+#define AT91C_US_RI           ((unsigned int) 0x1 << 20) // (USART) Image of RI Input
+#define AT91C_US_DSR          ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input
+#define AT91C_US_DCD          ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input
+#define AT91C_US_CTS          ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_SSC {
+	AT91_REG	 SSC_CR; 	// Control Register
+	AT91_REG	 SSC_CMR; 	// Clock Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 SSC_RCMR; 	// Receive Clock ModeRegister
+	AT91_REG	 SSC_RFMR; 	// Receive Frame Mode Register
+	AT91_REG	 SSC_TCMR; 	// Transmit Clock Mode Register
+	AT91_REG	 SSC_TFMR; 	// Transmit Frame Mode Register
+	AT91_REG	 SSC_RHR; 	// Receive Holding Register
+	AT91_REG	 SSC_THR; 	// Transmit Holding Register
+	AT91_REG	 Reserved1[2]; 	// 
+	AT91_REG	 SSC_RSHR; 	// Receive Sync Holding Register
+	AT91_REG	 SSC_TSHR; 	// Transmit Sync Holding Register
+	AT91_REG	 Reserved2[2]; 	// 
+	AT91_REG	 SSC_SR; 	// Status Register
+	AT91_REG	 SSC_IER; 	// Interrupt Enable Register
+	AT91_REG	 SSC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 SSC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved3[44]; 	// 
+	AT91_REG	 SSC_RPR; 	// Receive Pointer Register
+	AT91_REG	 SSC_RCR; 	// Receive Counter Register
+	AT91_REG	 SSC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 SSC_TCR; 	// Transmit Counter Register
+	AT91_REG	 SSC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 SSC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 SSC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 SSC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 SSC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 SSC_PTSR; 	// PDC Transfer Status Register
+} AT91S_SSC, *AT91PS_SSC;
+
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
+#define AT91C_SSC_RXEN        ((unsigned int) 0x1 <<  0) // (SSC) Receive Enable
+#define AT91C_SSC_RXDIS       ((unsigned int) 0x1 <<  1) // (SSC) Receive Disable
+#define AT91C_SSC_TXEN        ((unsigned int) 0x1 <<  8) // (SSC) Transmit Enable
+#define AT91C_SSC_TXDIS       ((unsigned int) 0x1 <<  9) // (SSC) Transmit Disable
+#define AT91C_SSC_SWRST       ((unsigned int) 0x1 << 15) // (SSC) Software Reset
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
+#define AT91C_SSC_CKS         ((unsigned int) 0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
+#define 	AT91C_SSC_CKS_DIV                  ((unsigned int) 0x0) // (SSC) Divided Clock
+#define 	AT91C_SSC_CKS_TK                   ((unsigned int) 0x1) // (SSC) TK Clock signal
+#define 	AT91C_SSC_CKS_RK                   ((unsigned int) 0x2) // (SSC) RK pin
+#define AT91C_SSC_CKO         ((unsigned int) 0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
+#define 	AT91C_SSC_CKO_NONE                 ((unsigned int) 0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+#define 	AT91C_SSC_CKO_CONTINOUS            ((unsigned int) 0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
+#define 	AT91C_SSC_CKO_DATA_TX              ((unsigned int) 0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+#define AT91C_SSC_CKI         ((unsigned int) 0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
+#define AT91C_SSC_START       ((unsigned int) 0xF <<  8) // (SSC) Receive/Transmit Start Selection
+#define 	AT91C_SSC_START_CONTINOUS            ((unsigned int) 0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+#define 	AT91C_SSC_START_TX                   ((unsigned int) 0x1 <<  8) // (SSC) Transmit/Receive start
+#define 	AT91C_SSC_START_LOW_RF               ((unsigned int) 0x2 <<  8) // (SSC) Detection of a low level on RF input
+#define 	AT91C_SSC_START_HIGH_RF              ((unsigned int) 0x3 <<  8) // (SSC) Detection of a high level on RF input
+#define 	AT91C_SSC_START_FALL_RF              ((unsigned int) 0x4 <<  8) // (SSC) Detection of a falling edge on RF input
+#define 	AT91C_SSC_START_RISE_RF              ((unsigned int) 0x5 <<  8) // (SSC) Detection of a rising edge on RF input
+#define 	AT91C_SSC_START_LEVEL_RF             ((unsigned int) 0x6 <<  8) // (SSC) Detection of any level change on RF input
+#define 	AT91C_SSC_START_EDGE_RF              ((unsigned int) 0x7 <<  8) // (SSC) Detection of any edge on RF input
+#define 	AT91C_SSC_START_0                    ((unsigned int) 0x8 <<  8) // (SSC) Compare 0
+#define AT91C_SSC_STTDLY      ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay
+#define AT91C_SSC_PERIOD      ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
+#define AT91C_SSC_DATLEN      ((unsigned int) 0x1F <<  0) // (SSC) Data Length
+#define AT91C_SSC_LOOP        ((unsigned int) 0x1 <<  5) // (SSC) Loop Mode
+#define AT91C_SSC_MSBF        ((unsigned int) 0x1 <<  7) // (SSC) Most Significant Bit First
+#define AT91C_SSC_DATNB       ((unsigned int) 0xF <<  8) // (SSC) Data Number per Frame
+#define AT91C_SSC_FSLEN       ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
+#define AT91C_SSC_FSOS        ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
+#define 	AT91C_SSC_FSOS_NONE                 ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+#define 	AT91C_SSC_FSOS_NEGATIVE             ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+#define 	AT91C_SSC_FSOS_POSITIVE             ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+#define 	AT91C_SSC_FSOS_LOW                  ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+#define 	AT91C_SSC_FSOS_HIGH                 ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+#define 	AT91C_SSC_FSOS_TOGGLE               ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+#define AT91C_SSC_FSEDGE      ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
+#define AT91C_SSC_DATDEF      ((unsigned int) 0x1 <<  5) // (SSC) Data Default Value
+#define AT91C_SSC_FSDEN       ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
+#define AT91C_SSC_TXRDY       ((unsigned int) 0x1 <<  0) // (SSC) Transmit Ready
+#define AT91C_SSC_TXEMPTY     ((unsigned int) 0x1 <<  1) // (SSC) Transmit Empty
+#define AT91C_SSC_ENDTX       ((unsigned int) 0x1 <<  2) // (SSC) End Of Transmission
+#define AT91C_SSC_TXBUFE      ((unsigned int) 0x1 <<  3) // (SSC) Transmit Buffer Empty
+#define AT91C_SSC_RXRDY       ((unsigned int) 0x1 <<  4) // (SSC) Receive Ready
+#define AT91C_SSC_OVRUN       ((unsigned int) 0x1 <<  5) // (SSC) Receive Overrun
+#define AT91C_SSC_ENDRX       ((unsigned int) 0x1 <<  6) // (SSC) End of Reception
+#define AT91C_SSC_RXBUFF      ((unsigned int) 0x1 <<  7) // (SSC) Receive Buffer Full
+#define AT91C_SSC_TXSYN       ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync
+#define AT91C_SSC_RXSYN       ((unsigned int) 0x1 << 11) // (SSC) Receive Sync
+#define AT91C_SSC_TXENA       ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable
+#define AT91C_SSC_RXENA       ((unsigned int) 0x1 << 17) // (SSC) Receive Enable
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Two-wire Interface
+// *****************************************************************************
+typedef struct _AT91S_TWI {
+	AT91_REG	 TWI_CR; 	// Control Register
+	AT91_REG	 TWI_MMR; 	// Master Mode Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 TWI_IADR; 	// Internal Address Register
+	AT91_REG	 TWI_CWGR; 	// Clock Waveform Generator Register
+	AT91_REG	 Reserved1[3]; 	// 
+	AT91_REG	 TWI_SR; 	// Status Register
+	AT91_REG	 TWI_IER; 	// Interrupt Enable Register
+	AT91_REG	 TWI_IDR; 	// Interrupt Disable Register
+	AT91_REG	 TWI_IMR; 	// Interrupt Mask Register
+	AT91_REG	 TWI_RHR; 	// Receive Holding Register
+	AT91_REG	 TWI_THR; 	// Transmit Holding Register
+} AT91S_TWI, *AT91PS_TWI;
+
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
+#define AT91C_TWI_START       ((unsigned int) 0x1 <<  0) // (TWI) Send a START Condition
+#define AT91C_TWI_STOP        ((unsigned int) 0x1 <<  1) // (TWI) Send a STOP Condition
+#define AT91C_TWI_MSEN        ((unsigned int) 0x1 <<  2) // (TWI) TWI Master Transfer Enabled
+#define AT91C_TWI_MSDIS       ((unsigned int) 0x1 <<  3) // (TWI) TWI Master Transfer Disabled
+#define AT91C_TWI_SWRST       ((unsigned int) 0x1 <<  7) // (TWI) Software Reset
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
+#define AT91C_TWI_IADRSZ      ((unsigned int) 0x3 <<  8) // (TWI) Internal Device Address Size
+#define 	AT91C_TWI_IADRSZ_NO                   ((unsigned int) 0x0 <<  8) // (TWI) No internal device address
+#define 	AT91C_TWI_IADRSZ_1_BYTE               ((unsigned int) 0x1 <<  8) // (TWI) One-byte internal device address
+#define 	AT91C_TWI_IADRSZ_2_BYTE               ((unsigned int) 0x2 <<  8) // (TWI) Two-byte internal device address
+#define 	AT91C_TWI_IADRSZ_3_BYTE               ((unsigned int) 0x3 <<  8) // (TWI) Three-byte internal device address
+#define AT91C_TWI_MREAD       ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction
+#define AT91C_TWI_DADR        ((unsigned int) 0x7F << 16) // (TWI) Device Address
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
+#define AT91C_TWI_CLDIV       ((unsigned int) 0xFF <<  0) // (TWI) Clock Low Divider
+#define AT91C_TWI_CHDIV       ((unsigned int) 0xFF <<  8) // (TWI) Clock High Divider
+#define AT91C_TWI_CKDIV       ((unsigned int) 0x7 << 16) // (TWI) Clock Divider
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
+#define AT91C_TWI_TXCOMP      ((unsigned int) 0x1 <<  0) // (TWI) Transmission Completed
+#define AT91C_TWI_RXRDY       ((unsigned int) 0x1 <<  1) // (TWI) Receive holding register ReaDY
+#define AT91C_TWI_TXRDY       ((unsigned int) 0x1 <<  2) // (TWI) Transmit holding register ReaDY
+#define AT91C_TWI_OVRE        ((unsigned int) 0x1 <<  6) // (TWI) Overrun Error
+#define AT91C_TWI_UNRE        ((unsigned int) 0x1 <<  7) // (TWI) Underrun Error
+#define AT91C_TWI_NACK        ((unsigned int) 0x1 <<  8) // (TWI) Not Acknowledged
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
+// *****************************************************************************
+typedef struct _AT91S_PWMC_CH {
+	AT91_REG	 PWMC_CMR; 	// Channel Mode Register
+	AT91_REG	 PWMC_CDTYR; 	// Channel Duty Cycle Register
+	AT91_REG	 PWMC_CPRDR; 	// Channel Period Register
+	AT91_REG	 PWMC_CCNTR; 	// Channel Counter Register
+	AT91_REG	 PWMC_CUPDR; 	// Channel Update Register
+	AT91_REG	 PWMC_Reserved[3]; 	// Reserved
+} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
+
+// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- 
+#define AT91C_PWMC_CPRE       ((unsigned int) 0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
+#define 	AT91C_PWMC_CPRE_MCK                  ((unsigned int) 0x0) // (PWMC_CH) 
+#define 	AT91C_PWMC_CPRE_MCKA                 ((unsigned int) 0xB) // (PWMC_CH) 
+#define 	AT91C_PWMC_CPRE_MCKB                 ((unsigned int) 0xC) // (PWMC_CH) 
+#define AT91C_PWMC_CALG       ((unsigned int) 0x1 <<  8) // (PWMC_CH) Channel Alignment
+#define AT91C_PWMC_CPOL       ((unsigned int) 0x1 <<  9) // (PWMC_CH) Channel Polarity
+#define AT91C_PWMC_CPD        ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period
+// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- 
+#define AT91C_PWMC_CDTY       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Duty Cycle
+// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- 
+#define AT91C_PWMC_CPRD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Period
+// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- 
+#define AT91C_PWMC_CCNT       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Counter
+// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- 
+#define AT91C_PWMC_CUPD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Update
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_PWMC {
+	AT91_REG	 PWMC_MR; 	// PWMC Mode Register
+	AT91_REG	 PWMC_ENA; 	// PWMC Enable Register
+	AT91_REG	 PWMC_DIS; 	// PWMC Disable Register
+	AT91_REG	 PWMC_SR; 	// PWMC Status Register
+	AT91_REG	 PWMC_IER; 	// PWMC Interrupt Enable Register
+	AT91_REG	 PWMC_IDR; 	// PWMC Interrupt Disable Register
+	AT91_REG	 PWMC_IMR; 	// PWMC Interrupt Mask Register
+	AT91_REG	 PWMC_ISR; 	// PWMC Interrupt Status Register
+	AT91_REG	 Reserved0[55]; 	// 
+	AT91_REG	 PWMC_VR; 	// PWMC Version Register
+	AT91_REG	 Reserved1[64]; 	// 
+	AT91S_PWMC_CH	 PWMC_CH[4]; 	// PWMC Channel
+} AT91S_PWMC, *AT91PS_PWMC;
+
+// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- 
+#define AT91C_PWMC_DIVA       ((unsigned int) 0xFF <<  0) // (PWMC) CLKA divide factor.
+#define AT91C_PWMC_PREA       ((unsigned int) 0xF <<  8) // (PWMC) Divider Input Clock Prescaler A
+#define 	AT91C_PWMC_PREA_MCK                  ((unsigned int) 0x0 <<  8) // (PWMC) 
+#define AT91C_PWMC_DIVB       ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.
+#define AT91C_PWMC_PREB       ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B
+#define 	AT91C_PWMC_PREB_MCK                  ((unsigned int) 0x0 << 24) // (PWMC) 
+// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- 
+#define AT91C_PWMC_CHID0      ((unsigned int) 0x1 <<  0) // (PWMC) Channel ID 0
+#define AT91C_PWMC_CHID1      ((unsigned int) 0x1 <<  1) // (PWMC) Channel ID 1
+#define AT91C_PWMC_CHID2      ((unsigned int) 0x1 <<  2) // (PWMC) Channel ID 2
+#define AT91C_PWMC_CHID3      ((unsigned int) 0x1 <<  3) // (PWMC) Channel ID 3
+// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- 
+// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- 
+// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- 
+// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- 
+// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- 
+// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR USB Device Interface
+// *****************************************************************************
+typedef struct _AT91S_UDP {
+	AT91_REG	 UDP_NUM; 	// Frame Number Register
+	AT91_REG	 UDP_GLBSTATE; 	// Global State Register
+	AT91_REG	 UDP_FADDR; 	// Function Address Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 UDP_IER; 	// Interrupt Enable Register
+	AT91_REG	 UDP_IDR; 	// Interrupt Disable Register
+	AT91_REG	 UDP_IMR; 	// Interrupt Mask Register
+	AT91_REG	 UDP_ISR; 	// Interrupt Status Register
+	AT91_REG	 UDP_ICR; 	// Interrupt Clear Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 UDP_RSTEP; 	// Reset Endpoint Register
+	AT91_REG	 Reserved2[1]; 	// 
+	AT91_REG	 UDP_CSR[6]; 	// Endpoint Control and Status Register
+	AT91_REG	 Reserved3[2]; 	// 
+	AT91_REG	 UDP_FDR[6]; 	// Endpoint FIFO Data Register
+	AT91_REG	 Reserved4[3]; 	// 
+	AT91_REG	 UDP_TXVC; 	// Transceiver Control Register
+} AT91S_UDP, *AT91PS_UDP;
+
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
+#define AT91C_UDP_FRM_NUM     ((unsigned int) 0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
+#define AT91C_UDP_FRM_ERR     ((unsigned int) 0x1 << 16) // (UDP) Frame Error
+#define AT91C_UDP_FRM_OK      ((unsigned int) 0x1 << 17) // (UDP) Frame OK
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
+#define AT91C_UDP_FADDEN      ((unsigned int) 0x1 <<  0) // (UDP) Function Address Enable
+#define AT91C_UDP_CONFG       ((unsigned int) 0x1 <<  1) // (UDP) Configured
+#define AT91C_UDP_ESR         ((unsigned int) 0x1 <<  2) // (UDP) Enable Send Resume
+#define AT91C_UDP_RSMINPR     ((unsigned int) 0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
+#define AT91C_UDP_RMWUPE      ((unsigned int) 0x1 <<  4) // (UDP) Remote Wake Up Enable
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
+#define AT91C_UDP_FADD        ((unsigned int) 0xFF <<  0) // (UDP) Function Address Value
+#define AT91C_UDP_FEN         ((unsigned int) 0x1 <<  8) // (UDP) Function Enable
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 
+#define AT91C_UDP_EPINT0      ((unsigned int) 0x1 <<  0) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT1      ((unsigned int) 0x1 <<  1) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT2      ((unsigned int) 0x1 <<  2) // (UDP) Endpoint 2 Interrupt
+#define AT91C_UDP_EPINT3      ((unsigned int) 0x1 <<  3) // (UDP) Endpoint 3 Interrupt
+#define AT91C_UDP_EPINT4      ((unsigned int) 0x1 <<  4) // (UDP) Endpoint 4 Interrupt
+#define AT91C_UDP_EPINT5      ((unsigned int) 0x1 <<  5) // (UDP) Endpoint 5 Interrupt
+#define AT91C_UDP_RXSUSP      ((unsigned int) 0x1 <<  8) // (UDP) USB Suspend Interrupt
+#define AT91C_UDP_RXRSM       ((unsigned int) 0x1 <<  9) // (UDP) USB Resume Interrupt
+#define AT91C_UDP_EXTRSM      ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt
+#define AT91C_UDP_SOFINT      ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt
+#define AT91C_UDP_WAKEUP      ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 
+#define AT91C_UDP_ENDBUSRES   ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 
+#define AT91C_UDP_EP0         ((unsigned int) 0x1 <<  0) // (UDP) Reset Endpoint 0
+#define AT91C_UDP_EP1         ((unsigned int) 0x1 <<  1) // (UDP) Reset Endpoint 1
+#define AT91C_UDP_EP2         ((unsigned int) 0x1 <<  2) // (UDP) Reset Endpoint 2
+#define AT91C_UDP_EP3         ((unsigned int) 0x1 <<  3) // (UDP) Reset Endpoint 3
+#define AT91C_UDP_EP4         ((unsigned int) 0x1 <<  4) // (UDP) Reset Endpoint 4
+#define AT91C_UDP_EP5         ((unsigned int) 0x1 <<  5) // (UDP) Reset Endpoint 5
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 
+#define AT91C_UDP_TXCOMP      ((unsigned int) 0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
+#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 <<  1) // (UDP) Receive Data Bank 0
+#define AT91C_UDP_RXSETUP     ((unsigned int) 0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
+#define AT91C_UDP_ISOERROR    ((unsigned int) 0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
+#define AT91C_UDP_TXPKTRDY    ((unsigned int) 0x1 <<  4) // (UDP) Transmit Packet Ready
+#define AT91C_UDP_FORCESTALL  ((unsigned int) 0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
+#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
+#define AT91C_UDP_DIR         ((unsigned int) 0x1 <<  7) // (UDP) Transfer Direction
+#define AT91C_UDP_EPTYPE      ((unsigned int) 0x7 <<  8) // (UDP) Endpoint type
+#define 	AT91C_UDP_EPTYPE_CTRL                 ((unsigned int) 0x0 <<  8) // (UDP) Control
+#define 	AT91C_UDP_EPTYPE_ISO_OUT              ((unsigned int) 0x1 <<  8) // (UDP) Isochronous OUT
+#define 	AT91C_UDP_EPTYPE_BULK_OUT             ((unsigned int) 0x2 <<  8) // (UDP) Bulk OUT
+#define 	AT91C_UDP_EPTYPE_INT_OUT              ((unsigned int) 0x3 <<  8) // (UDP) Interrupt OUT
+#define 	AT91C_UDP_EPTYPE_ISO_IN               ((unsigned int) 0x5 <<  8) // (UDP) Isochronous IN
+#define 	AT91C_UDP_EPTYPE_BULK_IN              ((unsigned int) 0x6 <<  8) // (UDP) Bulk IN
+#define 	AT91C_UDP_EPTYPE_INT_IN               ((unsigned int) 0x7 <<  8) // (UDP) Interrupt IN
+#define AT91C_UDP_DTGLE       ((unsigned int) 0x1 << 11) // (UDP) Data Toggle
+#define AT91C_UDP_EPEDS       ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable
+#define AT91C_UDP_RXBYTECNT   ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
+// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- 
+#define AT91C_UDP_TXVDIS      ((unsigned int) 0x1 <<  8) // (UDP) 
+#define AT91C_UDP_PUON        ((unsigned int) 0x1 <<  9) // (UDP) Pull-up ON
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
+// *****************************************************************************
+typedef struct _AT91S_TC {
+	AT91_REG	 TC_CCR; 	// Channel Control Register
+	AT91_REG	 TC_CMR; 	// Channel Mode Register (Capture Mode / Waveform Mode)
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 TC_CV; 	// Counter Value
+	AT91_REG	 TC_RA; 	// Register A
+	AT91_REG	 TC_RB; 	// Register B
+	AT91_REG	 TC_RC; 	// Register C
+	AT91_REG	 TC_SR; 	// Status Register
+	AT91_REG	 TC_IER; 	// Interrupt Enable Register
+	AT91_REG	 TC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 TC_IMR; 	// Interrupt Mask Register
+} AT91S_TC, *AT91PS_TC;
+
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
+#define AT91C_TC_CLKEN        ((unsigned int) 0x1 <<  0) // (TC) Counter Clock Enable Command
+#define AT91C_TC_CLKDIS       ((unsigned int) 0x1 <<  1) // (TC) Counter Clock Disable Command
+#define AT91C_TC_SWTRG        ((unsigned int) 0x1 <<  2) // (TC) Software Trigger Command
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
+#define AT91C_TC_CLKS         ((unsigned int) 0x7 <<  0) // (TC) Clock Selection
+#define 	AT91C_TC_CLKS_TIMER_DIV1_CLOCK     ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV2_CLOCK     ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV3_CLOCK     ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV4_CLOCK     ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV5_CLOCK     ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
+#define 	AT91C_TC_CLKS_XC0                  ((unsigned int) 0x5) // (TC) Clock selected: XC0
+#define 	AT91C_TC_CLKS_XC1                  ((unsigned int) 0x6) // (TC) Clock selected: XC1
+#define 	AT91C_TC_CLKS_XC2                  ((unsigned int) 0x7) // (TC) Clock selected: XC2
+#define AT91C_TC_CLKI         ((unsigned int) 0x1 <<  3) // (TC) Clock Invert
+#define AT91C_TC_BURST        ((unsigned int) 0x3 <<  4) // (TC) Burst Signal Selection
+#define 	AT91C_TC_BURST_NONE                 ((unsigned int) 0x0 <<  4) // (TC) The clock is not gated by an external signal
+#define 	AT91C_TC_BURST_XC0                  ((unsigned int) 0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
+#define 	AT91C_TC_BURST_XC1                  ((unsigned int) 0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
+#define 	AT91C_TC_BURST_XC2                  ((unsigned int) 0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
+#define AT91C_TC_CPCSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
+#define AT91C_TC_LDBSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
+#define AT91C_TC_CPCDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
+#define AT91C_TC_LDBDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
+#define AT91C_TC_ETRGEDG      ((unsigned int) 0x3 <<  8) // (TC) External Trigger Edge Selection
+#define 	AT91C_TC_ETRGEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_ETRGEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_ETRGEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_ETRGEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_EEVTEDG      ((unsigned int) 0x3 <<  8) // (TC) External Event Edge Selection
+#define 	AT91C_TC_EEVTEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_EEVTEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_EEVTEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_EEVTEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_EEVT         ((unsigned int) 0x3 << 10) // (TC) External Event  Selection
+#define 	AT91C_TC_EEVT_TIOB                 ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
+#define 	AT91C_TC_EEVT_XC0                  ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
+#define 	AT91C_TC_EEVT_XC1                  ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
+#define 	AT91C_TC_EEVT_XC2                  ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
+#define AT91C_TC_ABETRG       ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
+#define AT91C_TC_ENETRG       ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
+#define AT91C_TC_WAVESEL      ((unsigned int) 0x3 << 13) // (TC) Waveform  Selection
+#define 	AT91C_TC_WAVESEL_UP                   ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN               ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UP_AUTO              ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN_AUTO          ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
+#define AT91C_TC_CPCTRG       ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
+#define AT91C_TC_WAVE         ((unsigned int) 0x1 << 15) // (TC) 
+#define AT91C_TC_ACPA         ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
+#define 	AT91C_TC_ACPA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Effect: none
+#define 	AT91C_TC_ACPA_SET                  ((unsigned int) 0x1 << 16) // (TC) Effect: set
+#define 	AT91C_TC_ACPA_CLEAR                ((unsigned int) 0x2 << 16) // (TC) Effect: clear
+#define 	AT91C_TC_ACPA_TOGGLE               ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
+#define AT91C_TC_LDRA         ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection
+#define 	AT91C_TC_LDRA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Edge: None
+#define 	AT91C_TC_LDRA_RISING               ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA
+#define 	AT91C_TC_LDRA_FALLING              ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA
+#define 	AT91C_TC_LDRA_BOTH                 ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_ACPC         ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
+#define 	AT91C_TC_ACPC_NONE                 ((unsigned int) 0x0 << 18) // (TC) Effect: none
+#define 	AT91C_TC_ACPC_SET                  ((unsigned int) 0x1 << 18) // (TC) Effect: set
+#define 	AT91C_TC_ACPC_CLEAR                ((unsigned int) 0x2 << 18) // (TC) Effect: clear
+#define 	AT91C_TC_ACPC_TOGGLE               ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
+#define AT91C_TC_LDRB         ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection
+#define 	AT91C_TC_LDRB_NONE                 ((unsigned int) 0x0 << 18) // (TC) Edge: None
+#define 	AT91C_TC_LDRB_RISING               ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA
+#define 	AT91C_TC_LDRB_FALLING              ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA
+#define 	AT91C_TC_LDRB_BOTH                 ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_AEEVT        ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
+#define 	AT91C_TC_AEEVT_NONE                 ((unsigned int) 0x0 << 20) // (TC) Effect: none
+#define 	AT91C_TC_AEEVT_SET                  ((unsigned int) 0x1 << 20) // (TC) Effect: set
+#define 	AT91C_TC_AEEVT_CLEAR                ((unsigned int) 0x2 << 20) // (TC) Effect: clear
+#define 	AT91C_TC_AEEVT_TOGGLE               ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
+#define AT91C_TC_ASWTRG       ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
+#define 	AT91C_TC_ASWTRG_NONE                 ((unsigned int) 0x0 << 22) // (TC) Effect: none
+#define 	AT91C_TC_ASWTRG_SET                  ((unsigned int) 0x1 << 22) // (TC) Effect: set
+#define 	AT91C_TC_ASWTRG_CLEAR                ((unsigned int) 0x2 << 22) // (TC) Effect: clear
+#define 	AT91C_TC_ASWTRG_TOGGLE               ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
+#define AT91C_TC_BCPB         ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
+#define 	AT91C_TC_BCPB_NONE                 ((unsigned int) 0x0 << 24) // (TC) Effect: none
+#define 	AT91C_TC_BCPB_SET                  ((unsigned int) 0x1 << 24) // (TC) Effect: set
+#define 	AT91C_TC_BCPB_CLEAR                ((unsigned int) 0x2 << 24) // (TC) Effect: clear
+#define 	AT91C_TC_BCPB_TOGGLE               ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
+#define AT91C_TC_BCPC         ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
+#define 	AT91C_TC_BCPC_NONE                 ((unsigned int) 0x0 << 26) // (TC) Effect: none
+#define 	AT91C_TC_BCPC_SET                  ((unsigned int) 0x1 << 26) // (TC) Effect: set
+#define 	AT91C_TC_BCPC_CLEAR                ((unsigned int) 0x2 << 26) // (TC) Effect: clear
+#define 	AT91C_TC_BCPC_TOGGLE               ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
+#define AT91C_TC_BEEVT        ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
+#define 	AT91C_TC_BEEVT_NONE                 ((unsigned int) 0x0 << 28) // (TC) Effect: none
+#define 	AT91C_TC_BEEVT_SET                  ((unsigned int) 0x1 << 28) // (TC) Effect: set
+#define 	AT91C_TC_BEEVT_CLEAR                ((unsigned int) 0x2 << 28) // (TC) Effect: clear
+#define 	AT91C_TC_BEEVT_TOGGLE               ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
+#define AT91C_TC_BSWTRG       ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
+#define 	AT91C_TC_BSWTRG_NONE                 ((unsigned int) 0x0 << 30) // (TC) Effect: none
+#define 	AT91C_TC_BSWTRG_SET                  ((unsigned int) 0x1 << 30) // (TC) Effect: set
+#define 	AT91C_TC_BSWTRG_CLEAR                ((unsigned int) 0x2 << 30) // (TC) Effect: clear
+#define 	AT91C_TC_BSWTRG_TOGGLE               ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
+#define AT91C_TC_COVFS        ((unsigned int) 0x1 <<  0) // (TC) Counter Overflow
+#define AT91C_TC_LOVRS        ((unsigned int) 0x1 <<  1) // (TC) Load Overrun
+#define AT91C_TC_CPAS         ((unsigned int) 0x1 <<  2) // (TC) RA Compare
+#define AT91C_TC_CPBS         ((unsigned int) 0x1 <<  3) // (TC) RB Compare
+#define AT91C_TC_CPCS         ((unsigned int) 0x1 <<  4) // (TC) RC Compare
+#define AT91C_TC_LDRAS        ((unsigned int) 0x1 <<  5) // (TC) RA Loading
+#define AT91C_TC_LDRBS        ((unsigned int) 0x1 <<  6) // (TC) RB Loading
+#define AT91C_TC_ETRGS        ((unsigned int) 0x1 <<  7) // (TC) External Trigger
+#define AT91C_TC_CLKSTA       ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
+#define AT91C_TC_MTIOA        ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
+#define AT91C_TC_MTIOB        ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
+// *****************************************************************************
+typedef struct _AT91S_TCB {
+	AT91S_TC	 TCB_TC0; 	// TC Channel 0
+	AT91_REG	 Reserved0[4]; 	// 
+	AT91S_TC	 TCB_TC1; 	// TC Channel 1
+	AT91_REG	 Reserved1[4]; 	// 
+	AT91S_TC	 TCB_TC2; 	// TC Channel 2
+	AT91_REG	 Reserved2[4]; 	// 
+	AT91_REG	 TCB_BCR; 	// TC Block Control Register
+	AT91_REG	 TCB_BMR; 	// TC Block Mode Register
+} AT91S_TCB, *AT91PS_TCB;
+
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
+#define AT91C_TCB_SYNC        ((unsigned int) 0x1 <<  0) // (TCB) Synchro Command
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
+#define AT91C_TCB_TC0XC0S     ((unsigned int) 0x3 <<  0) // (TCB) External Clock Signal 0 Selection
+#define 	AT91C_TCB_TC0XC0S_TCLK0                ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_NONE                 ((unsigned int) 0x1) // (TCB) None signal connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA1                ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA2                ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
+#define AT91C_TCB_TC1XC1S     ((unsigned int) 0x3 <<  2) // (TCB) External Clock Signal 1 Selection
+#define 	AT91C_TCB_TC1XC1S_TCLK1                ((unsigned int) 0x0 <<  2) // (TCB) TCLK1 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_NONE                 ((unsigned int) 0x1 <<  2) // (TCB) None signal connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA0                ((unsigned int) 0x2 <<  2) // (TCB) TIOA0 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA2                ((unsigned int) 0x3 <<  2) // (TCB) TIOA2 connected to XC1
+#define AT91C_TCB_TC2XC2S     ((unsigned int) 0x3 <<  4) // (TCB) External Clock Signal 2 Selection
+#define 	AT91C_TCB_TC2XC2S_TCLK2                ((unsigned int) 0x0 <<  4) // (TCB) TCLK2 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_NONE                 ((unsigned int) 0x1 <<  4) // (TCB) None signal connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA0                ((unsigned int) 0x2 <<  4) // (TCB) TIOA0 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA1                ((unsigned int) 0x3 <<  4) // (TCB) TIOA2 connected to XC2
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface
+// *****************************************************************************
+typedef struct _AT91S_CAN_MB {
+	AT91_REG	 CAN_MB_MMR; 	// MailBox Mode Register
+	AT91_REG	 CAN_MB_MAM; 	// MailBox Acceptance Mask Register
+	AT91_REG	 CAN_MB_MID; 	// MailBox ID Register
+	AT91_REG	 CAN_MB_MFID; 	// MailBox Family ID Register
+	AT91_REG	 CAN_MB_MSR; 	// MailBox Status Register
+	AT91_REG	 CAN_MB_MDL; 	// MailBox Data Low Register
+	AT91_REG	 CAN_MB_MDH; 	// MailBox Data High Register
+	AT91_REG	 CAN_MB_MCR; 	// MailBox Control Register
+} AT91S_CAN_MB, *AT91PS_CAN_MB;
+
+// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- 
+#define AT91C_CAN_MTIMEMARK   ((unsigned int) 0xFFFF <<  0) // (CAN_MB) Mailbox Timemark
+#define AT91C_CAN_PRIOR       ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority
+#define AT91C_CAN_MOT         ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type
+#define 	AT91C_CAN_MOT_DIS                  ((unsigned int) 0x0 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_RX                   ((unsigned int) 0x1 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_RXOVERWRITE          ((unsigned int) 0x2 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_TX                   ((unsigned int) 0x3 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_CONSUMER             ((unsigned int) 0x4 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_PRODUCER             ((unsigned int) 0x5 << 24) // (CAN_MB) 
+// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- 
+#define AT91C_CAN_MIDvB       ((unsigned int) 0x3FFFF <<  0) // (CAN_MB) Complementary bits for identifier in extended mode
+#define AT91C_CAN_MIDvA       ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
+#define AT91C_CAN_MIDE        ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version
+// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- 
+// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- 
+// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- 
+#define AT91C_CAN_MTIMESTAMP  ((unsigned int) 0xFFFF <<  0) // (CAN_MB) Timer Value
+#define AT91C_CAN_MDLC        ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code
+#define AT91C_CAN_MRTR        ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
+#define AT91C_CAN_MABT        ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort
+#define AT91C_CAN_MRDY        ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready
+#define AT91C_CAN_MMI         ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored
+// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- 
+// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- 
+// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- 
+#define AT91C_CAN_MACR        ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox
+#define AT91C_CAN_MTCR        ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Control Area Network Interface
+// *****************************************************************************
+typedef struct _AT91S_CAN {
+	AT91_REG	 CAN_MR; 	// Mode Register
+	AT91_REG	 CAN_IER; 	// Interrupt Enable Register
+	AT91_REG	 CAN_IDR; 	// Interrupt Disable Register
+	AT91_REG	 CAN_IMR; 	// Interrupt Mask Register
+	AT91_REG	 CAN_SR; 	// Status Register
+	AT91_REG	 CAN_BR; 	// Baudrate Register
+	AT91_REG	 CAN_TIM; 	// Timer Register
+	AT91_REG	 CAN_TIMESTP; 	// Time Stamp Register
+	AT91_REG	 CAN_ECR; 	// Error Counter Register
+	AT91_REG	 CAN_TCR; 	// Transfer Command Register
+	AT91_REG	 CAN_ACR; 	// Abort Command Register
+	AT91_REG	 Reserved0[52]; 	// 
+	AT91_REG	 CAN_VR; 	// Version Register
+	AT91_REG	 Reserved1[64]; 	// 
+	AT91S_CAN_MB	 CAN_MB0; 	// CAN Mailbox 0
+	AT91S_CAN_MB	 CAN_MB1; 	// CAN Mailbox 1
+	AT91S_CAN_MB	 CAN_MB2; 	// CAN Mailbox 2
+	AT91S_CAN_MB	 CAN_MB3; 	// CAN Mailbox 3
+	AT91S_CAN_MB	 CAN_MB4; 	// CAN Mailbox 4
+	AT91S_CAN_MB	 CAN_MB5; 	// CAN Mailbox 5
+	AT91S_CAN_MB	 CAN_MB6; 	// CAN Mailbox 6
+	AT91S_CAN_MB	 CAN_MB7; 	// CAN Mailbox 7
+	AT91S_CAN_MB	 CAN_MB8; 	// CAN Mailbox 8
+	AT91S_CAN_MB	 CAN_MB9; 	// CAN Mailbox 9
+	AT91S_CAN_MB	 CAN_MB10; 	// CAN Mailbox 10
+	AT91S_CAN_MB	 CAN_MB11; 	// CAN Mailbox 11
+	AT91S_CAN_MB	 CAN_MB12; 	// CAN Mailbox 12
+	AT91S_CAN_MB	 CAN_MB13; 	// CAN Mailbox 13
+	AT91S_CAN_MB	 CAN_MB14; 	// CAN Mailbox 14
+	AT91S_CAN_MB	 CAN_MB15; 	// CAN Mailbox 15
+} AT91S_CAN, *AT91PS_CAN;
+
+// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- 
+#define AT91C_CAN_CANEN       ((unsigned int) 0x1 <<  0) // (CAN) CAN Controller Enable
+#define AT91C_CAN_LPM         ((unsigned int) 0x1 <<  1) // (CAN) Disable/Enable Low Power Mode
+#define AT91C_CAN_ABM         ((unsigned int) 0x1 <<  2) // (CAN) Disable/Enable Autobaud/Listen Mode
+#define AT91C_CAN_OVL         ((unsigned int) 0x1 <<  3) // (CAN) Disable/Enable Overload Frame
+#define AT91C_CAN_TEOF        ((unsigned int) 0x1 <<  4) // (CAN) Time Stamp messages at each end of Frame
+#define AT91C_CAN_TTM         ((unsigned int) 0x1 <<  5) // (CAN) Disable/Enable Time Trigger Mode
+#define AT91C_CAN_TIMFRZ      ((unsigned int) 0x1 <<  6) // (CAN) Enable Timer Freeze
+#define AT91C_CAN_DRPT        ((unsigned int) 0x1 <<  7) // (CAN) Disable Repeat
+// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- 
+#define AT91C_CAN_MB0         ((unsigned int) 0x1 <<  0) // (CAN) Mailbox 0 Flag
+#define AT91C_CAN_MB1         ((unsigned int) 0x1 <<  1) // (CAN) Mailbox 1 Flag
+#define AT91C_CAN_MB2         ((unsigned int) 0x1 <<  2) // (CAN) Mailbox 2 Flag
+#define AT91C_CAN_MB3         ((unsigned int) 0x1 <<  3) // (CAN) Mailbox 3 Flag
+#define AT91C_CAN_MB4         ((unsigned int) 0x1 <<  4) // (CAN) Mailbox 4 Flag
+#define AT91C_CAN_MB5         ((unsigned int) 0x1 <<  5) // (CAN) Mailbox 5 Flag
+#define AT91C_CAN_MB6         ((unsigned int) 0x1 <<  6) // (CAN) Mailbox 6 Flag
+#define AT91C_CAN_MB7         ((unsigned int) 0x1 <<  7) // (CAN) Mailbox 7 Flag
+#define AT91C_CAN_MB8         ((unsigned int) 0x1 <<  8) // (CAN) Mailbox 8 Flag
+#define AT91C_CAN_MB9         ((unsigned int) 0x1 <<  9) // (CAN) Mailbox 9 Flag
+#define AT91C_CAN_MB10        ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag
+#define AT91C_CAN_MB11        ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag
+#define AT91C_CAN_MB12        ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag
+#define AT91C_CAN_MB13        ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag
+#define AT91C_CAN_MB14        ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag
+#define AT91C_CAN_MB15        ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag
+#define AT91C_CAN_ERRA        ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag
+#define AT91C_CAN_WARN        ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag
+#define AT91C_CAN_ERRP        ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag
+#define AT91C_CAN_BOFF        ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag
+#define AT91C_CAN_SLEEP       ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag
+#define AT91C_CAN_WAKEUP      ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag
+#define AT91C_CAN_TOVF        ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag
+#define AT91C_CAN_TSTP        ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag
+#define AT91C_CAN_CERR        ((unsigned int) 0x1 << 24) // (CAN) CRC Error
+#define AT91C_CAN_SERR        ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error
+#define AT91C_CAN_AERR        ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error
+#define AT91C_CAN_FERR        ((unsigned int) 0x1 << 27) // (CAN) Form Error
+#define AT91C_CAN_BERR        ((unsigned int) 0x1 << 28) // (CAN) Bit Error
+// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- 
+// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- 
+// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- 
+#define AT91C_CAN_RBSY        ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy
+#define AT91C_CAN_TBSY        ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy
+#define AT91C_CAN_OVLY        ((unsigned int) 0x1 << 31) // (CAN) Overload Busy
+// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- 
+#define AT91C_CAN_PHASE2      ((unsigned int) 0x7 <<  0) // (CAN) Phase 2 segment
+#define AT91C_CAN_PHASE1      ((unsigned int) 0x7 <<  4) // (CAN) Phase 1 segment
+#define AT91C_CAN_PROPAG      ((unsigned int) 0x7 <<  8) // (CAN) Programmation time segment
+#define AT91C_CAN_SYNC        ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment
+#define AT91C_CAN_BRP         ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler
+#define AT91C_CAN_SMP         ((unsigned int) 0x1 << 24) // (CAN) Sampling mode
+// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- 
+#define AT91C_CAN_TIMER       ((unsigned int) 0xFFFF <<  0) // (CAN) Timer field
+// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- 
+// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- 
+#define AT91C_CAN_REC         ((unsigned int) 0xFF <<  0) // (CAN) Receive Error Counter
+#define AT91C_CAN_TEC         ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter
+// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- 
+#define AT91C_CAN_TIMRST      ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field
+// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100
+// *****************************************************************************
+typedef struct _AT91S_EMAC {
+	AT91_REG	 EMAC_NCR; 	// Network Control Register
+	AT91_REG	 EMAC_NCFGR; 	// Network Configuration Register
+	AT91_REG	 EMAC_NSR; 	// Network Status Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 EMAC_TSR; 	// Transmit Status Register
+	AT91_REG	 EMAC_RBQP; 	// Receive Buffer Queue Pointer
+	AT91_REG	 EMAC_TBQP; 	// Transmit Buffer Queue Pointer
+	AT91_REG	 EMAC_RSR; 	// Receive Status Register
+	AT91_REG	 EMAC_ISR; 	// Interrupt Status Register
+	AT91_REG	 EMAC_IER; 	// Interrupt Enable Register
+	AT91_REG	 EMAC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 EMAC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 EMAC_MAN; 	// PHY Maintenance Register
+	AT91_REG	 EMAC_PTR; 	// Pause Time Register
+	AT91_REG	 EMAC_PFR; 	// Pause Frames received Register
+	AT91_REG	 EMAC_FTO; 	// Frames Transmitted OK Register
+	AT91_REG	 EMAC_SCF; 	// Single Collision Frame Register
+	AT91_REG	 EMAC_MCF; 	// Multiple Collision Frame Register
+	AT91_REG	 EMAC_FRO; 	// Frames Received OK Register
+	AT91_REG	 EMAC_FCSE; 	// Frame Check Sequence Error Register
+	AT91_REG	 EMAC_ALE; 	// Alignment Error Register
+	AT91_REG	 EMAC_DTF; 	// Deferred Transmission Frame Register
+	AT91_REG	 EMAC_LCOL; 	// Late Collision Register
+	AT91_REG	 EMAC_ECOL; 	// Excessive Collision Register
+	AT91_REG	 EMAC_TUND; 	// Transmit Underrun Error Register
+	AT91_REG	 EMAC_CSE; 	// Carrier Sense Error Register
+	AT91_REG	 EMAC_RRE; 	// Receive Ressource Error Register
+	AT91_REG	 EMAC_ROV; 	// Receive Overrun Errors Register
+	AT91_REG	 EMAC_RSE; 	// Receive Symbol Errors Register
+	AT91_REG	 EMAC_ELE; 	// Excessive Length Errors Register
+	AT91_REG	 EMAC_RJA; 	// Receive Jabbers Register
+	AT91_REG	 EMAC_USF; 	// Undersize Frames Register
+	AT91_REG	 EMAC_STE; 	// SQE Test Error Register
+	AT91_REG	 EMAC_RLE; 	// Receive Length Field Mismatch Register
+	AT91_REG	 EMAC_TPF; 	// Transmitted Pause Frames Register
+	AT91_REG	 EMAC_HRB; 	// Hash Address Bottom[31:0]
+	AT91_REG	 EMAC_HRT; 	// Hash Address Top[63:32]
+	AT91_REG	 EMAC_SA1L; 	// Specific Address 1 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA1H; 	// Specific Address 1 Top, Last 2 bytes
+	AT91_REG	 EMAC_SA2L; 	// Specific Address 2 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA2H; 	// Specific Address 2 Top, Last 2 bytes
+	AT91_REG	 EMAC_SA3L; 	// Specific Address 3 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA3H; 	// Specific Address 3 Top, Last 2 bytes
+	AT91_REG	 EMAC_SA4L; 	// Specific Address 4 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA4H; 	// Specific Address 4 Top, Last 2 bytes
+	AT91_REG	 EMAC_TID; 	// Type ID Checking Register
+	AT91_REG	 EMAC_TPQ; 	// Transmit Pause Quantum Register
+	AT91_REG	 EMAC_USRIO; 	// USER Input/Output Register
+	AT91_REG	 EMAC_WOL; 	// Wake On LAN Register
+	AT91_REG	 Reserved1[13]; 	// 
+	AT91_REG	 EMAC_REV; 	// Revision Register
+} AT91S_EMAC, *AT91PS_EMAC;
+
+// -------- EMAC_NCR : (EMAC Offset: 0x0)  -------- 
+#define AT91C_EMAC_LB         ((unsigned int) 0x1 <<  0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
+#define AT91C_EMAC_LLB        ((unsigned int) 0x1 <<  1) // (EMAC) Loopback local. 
+#define AT91C_EMAC_RE         ((unsigned int) 0x1 <<  2) // (EMAC) Receive enable. 
+#define AT91C_EMAC_TE         ((unsigned int) 0x1 <<  3) // (EMAC) Transmit enable. 
+#define AT91C_EMAC_MPE        ((unsigned int) 0x1 <<  4) // (EMAC) Management port enable. 
+#define AT91C_EMAC_CLRSTAT    ((unsigned int) 0x1 <<  5) // (EMAC) Clear statistics registers. 
+#define AT91C_EMAC_INCSTAT    ((unsigned int) 0x1 <<  6) // (EMAC) Increment statistics registers. 
+#define AT91C_EMAC_WESTAT     ((unsigned int) 0x1 <<  7) // (EMAC) Write enable for statistics registers. 
+#define AT91C_EMAC_BP         ((unsigned int) 0x1 <<  8) // (EMAC) Back pressure. 
+#define AT91C_EMAC_TSTART     ((unsigned int) 0x1 <<  9) // (EMAC) Start Transmission. 
+#define AT91C_EMAC_THALT      ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. 
+#define AT91C_EMAC_TPFR       ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame 
+#define AT91C_EMAC_TZQ        ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame
+// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- 
+#define AT91C_EMAC_SPD        ((unsigned int) 0x1 <<  0) // (EMAC) Speed. 
+#define AT91C_EMAC_FD         ((unsigned int) 0x1 <<  1) // (EMAC) Full duplex. 
+#define AT91C_EMAC_JFRAME     ((unsigned int) 0x1 <<  3) // (EMAC) Jumbo Frames. 
+#define AT91C_EMAC_CAF        ((unsigned int) 0x1 <<  4) // (EMAC) Copy all frames. 
+#define AT91C_EMAC_NBC        ((unsigned int) 0x1 <<  5) // (EMAC) No broadcast. 
+#define AT91C_EMAC_MTI        ((unsigned int) 0x1 <<  6) // (EMAC) Multicast hash event enable
+#define AT91C_EMAC_UNI        ((unsigned int) 0x1 <<  7) // (EMAC) Unicast hash enable. 
+#define AT91C_EMAC_BIG        ((unsigned int) 0x1 <<  8) // (EMAC) Receive 1522 bytes. 
+#define AT91C_EMAC_EAE        ((unsigned int) 0x1 <<  9) // (EMAC) External address match enable. 
+#define AT91C_EMAC_CLK        ((unsigned int) 0x3 << 10) // (EMAC) 
+#define 	AT91C_EMAC_CLK_HCLK_8               ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8
+#define 	AT91C_EMAC_CLK_HCLK_16              ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16
+#define 	AT91C_EMAC_CLK_HCLK_32              ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32
+#define 	AT91C_EMAC_CLK_HCLK_64              ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64
+#define AT91C_EMAC_RTY        ((unsigned int) 0x1 << 12) // (EMAC) 
+#define AT91C_EMAC_PAE        ((unsigned int) 0x1 << 13) // (EMAC) 
+#define AT91C_EMAC_RBOF       ((unsigned int) 0x3 << 14) // (EMAC) 
+#define 	AT91C_EMAC_RBOF_OFFSET_0             ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_1             ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_2             ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_3             ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
+#define AT91C_EMAC_RLCE       ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable
+#define AT91C_EMAC_DRFCS      ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS
+#define AT91C_EMAC_EFRHD      ((unsigned int) 0x1 << 18) // (EMAC) 
+#define AT91C_EMAC_IRXFCS     ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS
+// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- 
+#define AT91C_EMAC_LINKR      ((unsigned int) 0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_MDIO       ((unsigned int) 0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_IDLE       ((unsigned int) 0x1 <<  2) // (EMAC) 
+// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- 
+#define AT91C_EMAC_UBR        ((unsigned int) 0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_COL        ((unsigned int) 0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_RLES       ((unsigned int) 0x1 <<  2) // (EMAC) 
+#define AT91C_EMAC_TGO        ((unsigned int) 0x1 <<  3) // (EMAC) Transmit Go
+#define AT91C_EMAC_BEX        ((unsigned int) 0x1 <<  4) // (EMAC) Buffers exhausted mid frame
+#define AT91C_EMAC_COMP       ((unsigned int) 0x1 <<  5) // (EMAC) 
+#define AT91C_EMAC_UND        ((unsigned int) 0x1 <<  6) // (EMAC) 
+// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- 
+#define AT91C_EMAC_BNA        ((unsigned int) 0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_REC        ((unsigned int) 0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_OVR        ((unsigned int) 0x1 <<  2) // (EMAC) 
+// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- 
+#define AT91C_EMAC_MFD        ((unsigned int) 0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_RCOMP      ((unsigned int) 0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_RXUBR      ((unsigned int) 0x1 <<  2) // (EMAC) 
+#define AT91C_EMAC_TXUBR      ((unsigned int) 0x1 <<  3) // (EMAC) 
+#define AT91C_EMAC_TUNDR      ((unsigned int) 0x1 <<  4) // (EMAC) 
+#define AT91C_EMAC_RLEX       ((unsigned int) 0x1 <<  5) // (EMAC) 
+#define AT91C_EMAC_TXERR      ((unsigned int) 0x1 <<  6) // (EMAC) 
+#define AT91C_EMAC_TCOMP      ((unsigned int) 0x1 <<  7) // (EMAC) 
+#define AT91C_EMAC_LINK       ((unsigned int) 0x1 <<  9) // (EMAC) 
+#define AT91C_EMAC_ROVR       ((unsigned int) 0x1 << 10) // (EMAC) 
+#define AT91C_EMAC_HRESP      ((unsigned int) 0x1 << 11) // (EMAC) 
+#define AT91C_EMAC_PFRE       ((unsigned int) 0x1 << 12) // (EMAC) 
+#define AT91C_EMAC_PTZ        ((unsigned int) 0x1 << 13) // (EMAC) 
+// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- 
+// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- 
+// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- 
+// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- 
+#define AT91C_EMAC_DATA       ((unsigned int) 0xFFFF <<  0) // (EMAC) 
+#define AT91C_EMAC_CODE       ((unsigned int) 0x3 << 16) // (EMAC) 
+#define AT91C_EMAC_REGA       ((unsigned int) 0x1F << 18) // (EMAC) 
+#define AT91C_EMAC_PHYA       ((unsigned int) 0x1F << 23) // (EMAC) 
+#define AT91C_EMAC_RW         ((unsigned int) 0x3 << 28) // (EMAC) 
+#define AT91C_EMAC_SOF        ((unsigned int) 0x3 << 30) // (EMAC) 
+// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- 
+#define AT91C_EMAC_RMII       ((unsigned int) 0x1 <<  0) // (EMAC) Reduce MII
+// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- 
+#define AT91C_EMAC_IP         ((unsigned int) 0xFFFF <<  0) // (EMAC) ARP request IP address
+#define AT91C_EMAC_MAG        ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable
+#define AT91C_EMAC_ARP        ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable
+#define AT91C_EMAC_SA1        ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable
+// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- 
+#define AT91C_EMAC_REVREF     ((unsigned int) 0xFFFF <<  0) // (EMAC) 
+#define AT91C_EMAC_PARTREF    ((unsigned int) 0xFFFF << 16) // (EMAC) 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
+// *****************************************************************************
+typedef struct _AT91S_ADC {
+	AT91_REG	 ADC_CR; 	// ADC Control Register
+	AT91_REG	 ADC_MR; 	// ADC Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 ADC_CHER; 	// ADC Channel Enable Register
+	AT91_REG	 ADC_CHDR; 	// ADC Channel Disable Register
+	AT91_REG	 ADC_CHSR; 	// ADC Channel Status Register
+	AT91_REG	 ADC_SR; 	// ADC Status Register
+	AT91_REG	 ADC_LCDR; 	// ADC Last Converted Data Register
+	AT91_REG	 ADC_IER; 	// ADC Interrupt Enable Register
+	AT91_REG	 ADC_IDR; 	// ADC Interrupt Disable Register
+	AT91_REG	 ADC_IMR; 	// ADC Interrupt Mask Register
+	AT91_REG	 ADC_CDR0; 	// ADC Channel Data Register 0
+	AT91_REG	 ADC_CDR1; 	// ADC Channel Data Register 1
+	AT91_REG	 ADC_CDR2; 	// ADC Channel Data Register 2
+	AT91_REG	 ADC_CDR3; 	// ADC Channel Data Register 3
+	AT91_REG	 ADC_CDR4; 	// ADC Channel Data Register 4
+	AT91_REG	 ADC_CDR5; 	// ADC Channel Data Register 5
+	AT91_REG	 ADC_CDR6; 	// ADC Channel Data Register 6
+	AT91_REG	 ADC_CDR7; 	// ADC Channel Data Register 7
+	AT91_REG	 Reserved1[44]; 	// 
+	AT91_REG	 ADC_RPR; 	// Receive Pointer Register
+	AT91_REG	 ADC_RCR; 	// Receive Counter Register
+	AT91_REG	 ADC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 ADC_TCR; 	// Transmit Counter Register
+	AT91_REG	 ADC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 ADC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 ADC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 ADC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 ADC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 ADC_PTSR; 	// PDC Transfer Status Register
+} AT91S_ADC, *AT91PS_ADC;
+
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- 
+#define AT91C_ADC_SWRST       ((unsigned int) 0x1 <<  0) // (ADC) Software Reset
+#define AT91C_ADC_START       ((unsigned int) 0x1 <<  1) // (ADC) Start Conversion
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- 
+#define AT91C_ADC_TRGEN       ((unsigned int) 0x1 <<  0) // (ADC) Trigger Enable
+#define 	AT91C_ADC_TRGEN_DIS                  ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
+#define 	AT91C_ADC_TRGEN_EN                   ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
+#define AT91C_ADC_TRGSEL      ((unsigned int) 0x7 <<  1) // (ADC) Trigger Selection
+#define 	AT91C_ADC_TRGSEL_TIOA0                ((unsigned int) 0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
+#define 	AT91C_ADC_TRGSEL_TIOA1                ((unsigned int) 0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
+#define 	AT91C_ADC_TRGSEL_TIOA2                ((unsigned int) 0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
+#define 	AT91C_ADC_TRGSEL_TIOA3                ((unsigned int) 0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
+#define 	AT91C_ADC_TRGSEL_TIOA4                ((unsigned int) 0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
+#define 	AT91C_ADC_TRGSEL_TIOA5                ((unsigned int) 0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
+#define 	AT91C_ADC_TRGSEL_EXT                  ((unsigned int) 0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
+#define AT91C_ADC_LOWRES      ((unsigned int) 0x1 <<  4) // (ADC) Resolution.
+#define 	AT91C_ADC_LOWRES_10_BIT               ((unsigned int) 0x0 <<  4) // (ADC) 10-bit resolution
+#define 	AT91C_ADC_LOWRES_8_BIT                ((unsigned int) 0x1 <<  4) // (ADC) 8-bit resolution
+#define AT91C_ADC_SLEEP       ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
+#define 	AT91C_ADC_SLEEP_NORMAL_MODE          ((unsigned int) 0x0 <<  5) // (ADC) Normal Mode
+#define 	AT91C_ADC_SLEEP_MODE                 ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
+#define AT91C_ADC_PRESCAL     ((unsigned int) 0x3F <<  8) // (ADC) Prescaler rate selection
+#define AT91C_ADC_STARTUP     ((unsigned int) 0x1F << 16) // (ADC) Startup Time
+#define AT91C_ADC_SHTIM       ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time
+// -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- 
+#define AT91C_ADC_CH0         ((unsigned int) 0x1 <<  0) // (ADC) Channel 0
+#define AT91C_ADC_CH1         ((unsigned int) 0x1 <<  1) // (ADC) Channel 1
+#define AT91C_ADC_CH2         ((unsigned int) 0x1 <<  2) // (ADC) Channel 2
+#define AT91C_ADC_CH3         ((unsigned int) 0x1 <<  3) // (ADC) Channel 3
+#define AT91C_ADC_CH4         ((unsigned int) 0x1 <<  4) // (ADC) Channel 4
+#define AT91C_ADC_CH5         ((unsigned int) 0x1 <<  5) // (ADC) Channel 5
+#define AT91C_ADC_CH6         ((unsigned int) 0x1 <<  6) // (ADC) Channel 6
+#define AT91C_ADC_CH7         ((unsigned int) 0x1 <<  7) // (ADC) Channel 7
+// -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- 
+// -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- 
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- 
+#define AT91C_ADC_EOC0        ((unsigned int) 0x1 <<  0) // (ADC) End of Conversion
+#define AT91C_ADC_EOC1        ((unsigned int) 0x1 <<  1) // (ADC) End of Conversion
+#define AT91C_ADC_EOC2        ((unsigned int) 0x1 <<  2) // (ADC) End of Conversion
+#define AT91C_ADC_EOC3        ((unsigned int) 0x1 <<  3) // (ADC) End of Conversion
+#define AT91C_ADC_EOC4        ((unsigned int) 0x1 <<  4) // (ADC) End of Conversion
+#define AT91C_ADC_EOC5        ((unsigned int) 0x1 <<  5) // (ADC) End of Conversion
+#define AT91C_ADC_EOC6        ((unsigned int) 0x1 <<  6) // (ADC) End of Conversion
+#define AT91C_ADC_EOC7        ((unsigned int) 0x1 <<  7) // (ADC) End of Conversion
+#define AT91C_ADC_OVRE0       ((unsigned int) 0x1 <<  8) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE1       ((unsigned int) 0x1 <<  9) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE2       ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE3       ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE4       ((unsigned int) 0x1 << 12) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE5       ((unsigned int) 0x1 << 13) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE6       ((unsigned int) 0x1 << 14) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE7       ((unsigned int) 0x1 << 15) // (ADC) Overrun Error
+#define AT91C_ADC_DRDY        ((unsigned int) 0x1 << 16) // (ADC) Data Ready
+#define AT91C_ADC_GOVRE       ((unsigned int) 0x1 << 17) // (ADC) General Overrun
+#define AT91C_ADC_ENDRX       ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer
+#define AT91C_ADC_RXBUFF      ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- 
+#define AT91C_ADC_LDATA       ((unsigned int) 0x3FF <<  0) // (ADC) Last Data Converted
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- 
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- 
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- 
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- 
+#define AT91C_ADC_DATA        ((unsigned int) 0x3FF <<  0) // (ADC) Converted Data
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- 
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- 
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- 
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- 
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- 
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- 
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Advanced  Encryption Standard
+// *****************************************************************************
+typedef struct _AT91S_AES {
+	AT91_REG	 AES_CR; 	// Control Register
+	AT91_REG	 AES_MR; 	// Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 AES_IER; 	// Interrupt Enable Register
+	AT91_REG	 AES_IDR; 	// Interrupt Disable Register
+	AT91_REG	 AES_IMR; 	// Interrupt Mask Register
+	AT91_REG	 AES_ISR; 	// Interrupt Status Register
+	AT91_REG	 AES_KEYWxR[4]; 	// Key Word x Register
+	AT91_REG	 Reserved1[4]; 	// 
+	AT91_REG	 AES_IDATAxR[4]; 	// Input Data x Register
+	AT91_REG	 AES_ODATAxR[4]; 	// Output Data x Register
+	AT91_REG	 AES_IVxR[4]; 	// Initialization Vector x Register
+	AT91_REG	 Reserved2[35]; 	// 
+	AT91_REG	 AES_VR; 	// AES Version Register
+	AT91_REG	 AES_RPR; 	// Receive Pointer Register
+	AT91_REG	 AES_RCR; 	// Receive Counter Register
+	AT91_REG	 AES_TPR; 	// Transmit Pointer Register
+	AT91_REG	 AES_TCR; 	// Transmit Counter Register
+	AT91_REG	 AES_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 AES_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 AES_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 AES_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 AES_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 AES_PTSR; 	// PDC Transfer Status Register
+} AT91S_AES, *AT91PS_AES;
+
+// -------- AES_CR : (AES Offset: 0x0) Control Register -------- 
+#define AT91C_AES_START       ((unsigned int) 0x1 <<  0) // (AES) Starts Processing
+#define AT91C_AES_SWRST       ((unsigned int) 0x1 <<  8) // (AES) Software Reset
+#define AT91C_AES_LOADSEED    ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading
+// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- 
+#define AT91C_AES_CIPHER      ((unsigned int) 0x1 <<  0) // (AES) Processing Mode
+#define AT91C_AES_PROCDLY     ((unsigned int) 0xF <<  4) // (AES) Processing Delay
+#define AT91C_AES_SMOD        ((unsigned int) 0x3 <<  8) // (AES) Start Mode
+#define 	AT91C_AES_SMOD_MANUAL               ((unsigned int) 0x0 <<  8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
+#define 	AT91C_AES_SMOD_AUTO                 ((unsigned int) 0x1 <<  8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
+#define 	AT91C_AES_SMOD_PDC                  ((unsigned int) 0x2 <<  8) // (AES) PDC Mode (cf datasheet).
+#define AT91C_AES_OPMOD       ((unsigned int) 0x7 << 12) // (AES) Operation Mode
+#define 	AT91C_AES_OPMOD_ECB                  ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode.
+#define 	AT91C_AES_OPMOD_CBC                  ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode.
+#define 	AT91C_AES_OPMOD_OFB                  ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode.
+#define 	AT91C_AES_OPMOD_CFB                  ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode.
+#define 	AT91C_AES_OPMOD_CTR                  ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode.
+#define AT91C_AES_LOD         ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode
+#define AT91C_AES_CFBS        ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size
+#define 	AT91C_AES_CFBS_128_BIT              ((unsigned int) 0x0 << 16) // (AES) 128-bit.
+#define 	AT91C_AES_CFBS_64_BIT               ((unsigned int) 0x1 << 16) // (AES) 64-bit.
+#define 	AT91C_AES_CFBS_32_BIT               ((unsigned int) 0x2 << 16) // (AES) 32-bit.
+#define 	AT91C_AES_CFBS_16_BIT               ((unsigned int) 0x3 << 16) // (AES) 16-bit.
+#define 	AT91C_AES_CFBS_8_BIT                ((unsigned int) 0x4 << 16) // (AES) 8-bit.
+#define AT91C_AES_CKEY        ((unsigned int) 0xF << 20) // (AES) Countermeasure Key
+#define AT91C_AES_CTYPE       ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type
+#define 	AT91C_AES_CTYPE_TYPE1_EN             ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE2_EN             ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE3_EN             ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE4_EN             ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE5_EN             ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled.
+// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- 
+#define AT91C_AES_DATRDY      ((unsigned int) 0x1 <<  0) // (AES) DATRDY
+#define AT91C_AES_ENDRX       ((unsigned int) 0x1 <<  1) // (AES) PDC Read Buffer End
+#define AT91C_AES_ENDTX       ((unsigned int) 0x1 <<  2) // (AES) PDC Write Buffer End
+#define AT91C_AES_RXBUFF      ((unsigned int) 0x1 <<  3) // (AES) PDC Read Buffer Full
+#define AT91C_AES_TXBUFE      ((unsigned int) 0x1 <<  4) // (AES) PDC Write Buffer Empty
+#define AT91C_AES_URAD        ((unsigned int) 0x1 <<  8) // (AES) Unspecified Register Access Detection
+// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- 
+// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- 
+// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- 
+#define AT91C_AES_URAT        ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status
+#define 	AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.
+#define 	AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing.
+#define 	AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing.
+#define 	AT91C_AES_URAT_OUT_DAT_READ_SUBKEY  ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation.
+#define 	AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation.
+#define 	AT91C_AES_URAT_WO_REG_READ          ((unsigned int) 0x5 << 12) // (AES) Write-only register read access.
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Triple Data Encryption Standard
+// *****************************************************************************
+typedef struct _AT91S_TDES {
+	AT91_REG	 TDES_CR; 	// Control Register
+	AT91_REG	 TDES_MR; 	// Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 TDES_IER; 	// Interrupt Enable Register
+	AT91_REG	 TDES_IDR; 	// Interrupt Disable Register
+	AT91_REG	 TDES_IMR; 	// Interrupt Mask Register
+	AT91_REG	 TDES_ISR; 	// Interrupt Status Register
+	AT91_REG	 TDES_KEY1WxR[2]; 	// Key 1 Word x Register
+	AT91_REG	 TDES_KEY2WxR[2]; 	// Key 2 Word x Register
+	AT91_REG	 TDES_KEY3WxR[2]; 	// Key 3 Word x Register
+	AT91_REG	 Reserved1[2]; 	// 
+	AT91_REG	 TDES_IDATAxR[2]; 	// Input Data x Register
+	AT91_REG	 Reserved2[2]; 	// 
+	AT91_REG	 TDES_ODATAxR[2]; 	// Output Data x Register
+	AT91_REG	 Reserved3[2]; 	// 
+	AT91_REG	 TDES_IVxR[2]; 	// Initialization Vector x Register
+	AT91_REG	 Reserved4[37]; 	// 
+	AT91_REG	 TDES_VR; 	// TDES Version Register
+	AT91_REG	 TDES_RPR; 	// Receive Pointer Register
+	AT91_REG	 TDES_RCR; 	// Receive Counter Register
+	AT91_REG	 TDES_TPR; 	// Transmit Pointer Register
+	AT91_REG	 TDES_TCR; 	// Transmit Counter Register
+	AT91_REG	 TDES_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 TDES_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 TDES_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 TDES_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 TDES_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 TDES_PTSR; 	// PDC Transfer Status Register
+} AT91S_TDES, *AT91PS_TDES;
+
+// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- 
+#define AT91C_TDES_START      ((unsigned int) 0x1 <<  0) // (TDES) Starts Processing
+#define AT91C_TDES_SWRST      ((unsigned int) 0x1 <<  8) // (TDES) Software Reset
+// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- 
+#define AT91C_TDES_CIPHER     ((unsigned int) 0x1 <<  0) // (TDES) Processing Mode
+#define AT91C_TDES_TDESMOD    ((unsigned int) 0x1 <<  1) // (TDES) Single or Triple DES Mode
+#define AT91C_TDES_KEYMOD     ((unsigned int) 0x1 <<  4) // (TDES) Key Mode
+#define AT91C_TDES_SMOD       ((unsigned int) 0x3 <<  8) // (TDES) Start Mode
+#define 	AT91C_TDES_SMOD_MANUAL               ((unsigned int) 0x0 <<  8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
+#define 	AT91C_TDES_SMOD_AUTO                 ((unsigned int) 0x1 <<  8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
+#define 	AT91C_TDES_SMOD_PDC                  ((unsigned int) 0x2 <<  8) // (TDES) PDC Mode (cf datasheet).
+#define AT91C_TDES_OPMOD      ((unsigned int) 0x3 << 12) // (TDES) Operation Mode
+#define 	AT91C_TDES_OPMOD_ECB                  ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode.
+#define 	AT91C_TDES_OPMOD_CBC                  ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.
+#define 	AT91C_TDES_OPMOD_OFB                  ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode.
+#define 	AT91C_TDES_OPMOD_CFB                  ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode.
+#define AT91C_TDES_LOD        ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode
+#define AT91C_TDES_CFBS       ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size
+#define 	AT91C_TDES_CFBS_64_BIT               ((unsigned int) 0x0 << 16) // (TDES) 64-bit.
+#define 	AT91C_TDES_CFBS_32_BIT               ((unsigned int) 0x1 << 16) // (TDES) 32-bit.
+#define 	AT91C_TDES_CFBS_16_BIT               ((unsigned int) 0x2 << 16) // (TDES) 16-bit.
+#define 	AT91C_TDES_CFBS_8_BIT                ((unsigned int) 0x3 << 16) // (TDES) 8-bit.
+// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- 
+#define AT91C_TDES_DATRDY     ((unsigned int) 0x1 <<  0) // (TDES) DATRDY
+#define AT91C_TDES_ENDRX      ((unsigned int) 0x1 <<  1) // (TDES) PDC Read Buffer End
+#define AT91C_TDES_ENDTX      ((unsigned int) 0x1 <<  2) // (TDES) PDC Write Buffer End
+#define AT91C_TDES_RXBUFF     ((unsigned int) 0x1 <<  3) // (TDES) PDC Read Buffer Full
+#define AT91C_TDES_TXBUFE     ((unsigned int) 0x1 <<  4) // (TDES) PDC Write Buffer Empty
+#define AT91C_TDES_URAD       ((unsigned int) 0x1 <<  8) // (TDES) Unspecified Register Access Detection
+// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- 
+// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- 
+// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- 
+#define AT91C_TDES_URAT       ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status
+#define 	AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.
+#define 	AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing.
+#define 	AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing.
+#define 	AT91C_TDES_URAT_WO_REG_READ          ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access.
+
+// *****************************************************************************
+//               REGISTER ADDRESS DEFINITION FOR AT91SAM7X256
+// *****************************************************************************
+// ========== Register definition for SYS peripheral ========== 
+// ========== Register definition for AIC peripheral ========== 
+#define AT91C_AIC_IVR   ((AT91_REG *) 	0xFFFFF100) // (AIC) IRQ Vector Register
+#define AT91C_AIC_SMR   ((AT91_REG *) 	0xFFFFF000) // (AIC) Source Mode Register
+#define AT91C_AIC_FVR   ((AT91_REG *) 	0xFFFFF104) // (AIC) FIQ Vector Register
+#define AT91C_AIC_DCR   ((AT91_REG *) 	0xFFFFF138) // (AIC) Debug Control Register (Protect)
+#define AT91C_AIC_EOICR ((AT91_REG *) 	0xFFFFF130) // (AIC) End of Interrupt Command Register
+#define AT91C_AIC_SVR   ((AT91_REG *) 	0xFFFFF080) // (AIC) Source Vector Register
+#define AT91C_AIC_FFSR  ((AT91_REG *) 	0xFFFFF148) // (AIC) Fast Forcing Status Register
+#define AT91C_AIC_ICCR  ((AT91_REG *) 	0xFFFFF128) // (AIC) Interrupt Clear Command Register
+#define AT91C_AIC_ISR   ((AT91_REG *) 	0xFFFFF108) // (AIC) Interrupt Status Register
+#define AT91C_AIC_IMR   ((AT91_REG *) 	0xFFFFF110) // (AIC) Interrupt Mask Register
+#define AT91C_AIC_IPR   ((AT91_REG *) 	0xFFFFF10C) // (AIC) Interrupt Pending Register
+#define AT91C_AIC_FFER  ((AT91_REG *) 	0xFFFFF140) // (AIC) Fast Forcing Enable Register
+#define AT91C_AIC_IECR  ((AT91_REG *) 	0xFFFFF120) // (AIC) Interrupt Enable Command Register
+#define AT91C_AIC_ISCR  ((AT91_REG *) 	0xFFFFF12C) // (AIC) Interrupt Set Command Register
+#define AT91C_AIC_FFDR  ((AT91_REG *) 	0xFFFFF144) // (AIC) Fast Forcing Disable Register
+#define AT91C_AIC_CISR  ((AT91_REG *) 	0xFFFFF114) // (AIC) Core Interrupt Status Register
+#define AT91C_AIC_IDCR  ((AT91_REG *) 	0xFFFFF124) // (AIC) Interrupt Disable Command Register
+#define AT91C_AIC_SPU   ((AT91_REG *) 	0xFFFFF134) // (AIC) Spurious Vector Register
+// ========== Register definition for PDC_DBGU peripheral ========== 
+#define AT91C_DBGU_TCR  ((AT91_REG *) 	0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
+#define AT91C_DBGU_RNPR ((AT91_REG *) 	0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
+#define AT91C_DBGU_TNPR ((AT91_REG *) 	0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
+#define AT91C_DBGU_TPR  ((AT91_REG *) 	0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
+#define AT91C_DBGU_RPR  ((AT91_REG *) 	0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
+#define AT91C_DBGU_RCR  ((AT91_REG *) 	0xFFFFF304) // (PDC_DBGU) Receive Counter Register
+#define AT91C_DBGU_RNCR ((AT91_REG *) 	0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
+#define AT91C_DBGU_PTCR ((AT91_REG *) 	0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
+#define AT91C_DBGU_PTSR ((AT91_REG *) 	0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
+#define AT91C_DBGU_TNCR ((AT91_REG *) 	0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
+// ========== Register definition for DBGU peripheral ========== 
+#define AT91C_DBGU_EXID ((AT91_REG *) 	0xFFFFF244) // (DBGU) Chip ID Extension Register
+#define AT91C_DBGU_BRGR ((AT91_REG *) 	0xFFFFF220) // (DBGU) Baud Rate Generator Register
+#define AT91C_DBGU_IDR  ((AT91_REG *) 	0xFFFFF20C) // (DBGU) Interrupt Disable Register
+#define AT91C_DBGU_CSR  ((AT91_REG *) 	0xFFFFF214) // (DBGU) Channel Status Register
+#define AT91C_DBGU_CIDR ((AT91_REG *) 	0xFFFFF240) // (DBGU) Chip ID Register
+#define AT91C_DBGU_MR   ((AT91_REG *) 	0xFFFFF204) // (DBGU) Mode Register
+#define AT91C_DBGU_IMR  ((AT91_REG *) 	0xFFFFF210) // (DBGU) Interrupt Mask Register
+#define AT91C_DBGU_CR   ((AT91_REG *) 	0xFFFFF200) // (DBGU) Control Register
+#define AT91C_DBGU_FNTR ((AT91_REG *) 	0xFFFFF248) // (DBGU) Force NTRST Register
+#define AT91C_DBGU_THR  ((AT91_REG *) 	0xFFFFF21C) // (DBGU) Transmitter Holding Register
+#define AT91C_DBGU_RHR  ((AT91_REG *) 	0xFFFFF218) // (DBGU) Receiver Holding Register
+#define AT91C_DBGU_IER  ((AT91_REG *) 	0xFFFFF208) // (DBGU) Interrupt Enable Register
+// ========== Register definition for PIOA peripheral ========== 
+#define AT91C_PIOA_ODR  ((AT91_REG *) 	0xFFFFF414) // (PIOA) Output Disable Registerr
+#define AT91C_PIOA_SODR ((AT91_REG *) 	0xFFFFF430) // (PIOA) Set Output Data Register
+#define AT91C_PIOA_ISR  ((AT91_REG *) 	0xFFFFF44C) // (PIOA) Interrupt Status Register
+#define AT91C_PIOA_ABSR ((AT91_REG *) 	0xFFFFF478) // (PIOA) AB Select Status Register
+#define AT91C_PIOA_IER  ((AT91_REG *) 	0xFFFFF440) // (PIOA) Interrupt Enable Register
+#define AT91C_PIOA_PPUDR ((AT91_REG *) 	0xFFFFF460) // (PIOA) Pull-up Disable Register
+#define AT91C_PIOA_IMR  ((AT91_REG *) 	0xFFFFF448) // (PIOA) Interrupt Mask Register
+#define AT91C_PIOA_PER  ((AT91_REG *) 	0xFFFFF400) // (PIOA) PIO Enable Register
+#define AT91C_PIOA_IFDR ((AT91_REG *) 	0xFFFFF424) // (PIOA) Input Filter Disable Register
+#define AT91C_PIOA_OWDR ((AT91_REG *) 	0xFFFFF4A4) // (PIOA) Output Write Disable Register
+#define AT91C_PIOA_MDSR ((AT91_REG *) 	0xFFFFF458) // (PIOA) Multi-driver Status Register
+#define AT91C_PIOA_IDR  ((AT91_REG *) 	0xFFFFF444) // (PIOA) Interrupt Disable Register
+#define AT91C_PIOA_ODSR ((AT91_REG *) 	0xFFFFF438) // (PIOA) Output Data Status Register
+#define AT91C_PIOA_PPUSR ((AT91_REG *) 	0xFFFFF468) // (PIOA) Pull-up Status Register
+#define AT91C_PIOA_OWSR ((AT91_REG *) 	0xFFFFF4A8) // (PIOA) Output Write Status Register
+#define AT91C_PIOA_BSR  ((AT91_REG *) 	0xFFFFF474) // (PIOA) Select B Register
+#define AT91C_PIOA_OWER ((AT91_REG *) 	0xFFFFF4A0) // (PIOA) Output Write Enable Register
+#define AT91C_PIOA_IFER ((AT91_REG *) 	0xFFFFF420) // (PIOA) Input Filter Enable Register
+#define AT91C_PIOA_PDSR ((AT91_REG *) 	0xFFFFF43C) // (PIOA) Pin Data Status Register
+#define AT91C_PIOA_PPUER ((AT91_REG *) 	0xFFFFF464) // (PIOA) Pull-up Enable Register
+#define AT91C_PIOA_OSR  ((AT91_REG *) 	0xFFFFF418) // (PIOA) Output Status Register
+#define AT91C_PIOA_ASR  ((AT91_REG *) 	0xFFFFF470) // (PIOA) Select A Register
+#define AT91C_PIOA_MDDR ((AT91_REG *) 	0xFFFFF454) // (PIOA) Multi-driver Disable Register
+#define AT91C_PIOA_CODR ((AT91_REG *) 	0xFFFFF434) // (PIOA) Clear Output Data Register
+#define AT91C_PIOA_MDER ((AT91_REG *) 	0xFFFFF450) // (PIOA) Multi-driver Enable Register
+#define AT91C_PIOA_PDR  ((AT91_REG *) 	0xFFFFF404) // (PIOA) PIO Disable Register
+#define AT91C_PIOA_IFSR ((AT91_REG *) 	0xFFFFF428) // (PIOA) Input Filter Status Register
+#define AT91C_PIOA_OER  ((AT91_REG *) 	0xFFFFF410) // (PIOA) Output Enable Register
+#define AT91C_PIOA_PSR  ((AT91_REG *) 	0xFFFFF408) // (PIOA) PIO Status Register
+// ========== Register definition for PIOB peripheral ========== 
+#define AT91C_PIOB_OWDR ((AT91_REG *) 	0xFFFFF6A4) // (PIOB) Output Write Disable Register
+#define AT91C_PIOB_MDER ((AT91_REG *) 	0xFFFFF650) // (PIOB) Multi-driver Enable Register
+#define AT91C_PIOB_PPUSR ((AT91_REG *) 	0xFFFFF668) // (PIOB) Pull-up Status Register
+#define AT91C_PIOB_IMR  ((AT91_REG *) 	0xFFFFF648) // (PIOB) Interrupt Mask Register
+#define AT91C_PIOB_ASR  ((AT91_REG *) 	0xFFFFF670) // (PIOB) Select A Register
+#define AT91C_PIOB_PPUDR ((AT91_REG *) 	0xFFFFF660) // (PIOB) Pull-up Disable Register
+#define AT91C_PIOB_PSR  ((AT91_REG *) 	0xFFFFF608) // (PIOB) PIO Status Register
+#define AT91C_PIOB_IER  ((AT91_REG *) 	0xFFFFF640) // (PIOB) Interrupt Enable Register
+#define AT91C_PIOB_CODR ((AT91_REG *) 	0xFFFFF634) // (PIOB) Clear Output Data Register
+#define AT91C_PIOB_OWER ((AT91_REG *) 	0xFFFFF6A0) // (PIOB) Output Write Enable Register
+#define AT91C_PIOB_ABSR ((AT91_REG *) 	0xFFFFF678) // (PIOB) AB Select Status Register
+#define AT91C_PIOB_IFDR ((AT91_REG *) 	0xFFFFF624) // (PIOB) Input Filter Disable Register
+#define AT91C_PIOB_PDSR ((AT91_REG *) 	0xFFFFF63C) // (PIOB) Pin Data Status Register
+#define AT91C_PIOB_IDR  ((AT91_REG *) 	0xFFFFF644) // (PIOB) Interrupt Disable Register
+#define AT91C_PIOB_OWSR ((AT91_REG *) 	0xFFFFF6A8) // (PIOB) Output Write Status Register
+#define AT91C_PIOB_PDR  ((AT91_REG *) 	0xFFFFF604) // (PIOB) PIO Disable Register
+#define AT91C_PIOB_ODR  ((AT91_REG *) 	0xFFFFF614) // (PIOB) Output Disable Registerr
+#define AT91C_PIOB_IFSR ((AT91_REG *) 	0xFFFFF628) // (PIOB) Input Filter Status Register
+#define AT91C_PIOB_PPUER ((AT91_REG *) 	0xFFFFF664) // (PIOB) Pull-up Enable Register
+#define AT91C_PIOB_SODR ((AT91_REG *) 	0xFFFFF630) // (PIOB) Set Output Data Register
+#define AT91C_PIOB_ISR  ((AT91_REG *) 	0xFFFFF64C) // (PIOB) Interrupt Status Register
+#define AT91C_PIOB_ODSR ((AT91_REG *) 	0xFFFFF638) // (PIOB) Output Data Status Register
+#define AT91C_PIOB_OSR  ((AT91_REG *) 	0xFFFFF618) // (PIOB) Output Status Register
+#define AT91C_PIOB_MDSR ((AT91_REG *) 	0xFFFFF658) // (PIOB) Multi-driver Status Register
+#define AT91C_PIOB_IFER ((AT91_REG *) 	0xFFFFF620) // (PIOB) Input Filter Enable Register
+#define AT91C_PIOB_BSR  ((AT91_REG *) 	0xFFFFF674) // (PIOB) Select B Register
+#define AT91C_PIOB_MDDR ((AT91_REG *) 	0xFFFFF654) // (PIOB) Multi-driver Disable Register
+#define AT91C_PIOB_OER  ((AT91_REG *) 	0xFFFFF610) // (PIOB) Output Enable Register
+#define AT91C_PIOB_PER  ((AT91_REG *) 	0xFFFFF600) // (PIOB) PIO Enable Register
+// ========== Register definition for CKGR peripheral ========== 
+#define AT91C_CKGR_MOR  ((AT91_REG *) 	0xFFFFFC20) // (CKGR) Main Oscillator Register
+#define AT91C_CKGR_PLLR ((AT91_REG *) 	0xFFFFFC2C) // (CKGR) PLL Register
+#define AT91C_CKGR_MCFR ((AT91_REG *) 	0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
+// ========== Register definition for PMC peripheral ========== 
+#define AT91C_PMC_IDR   ((AT91_REG *) 	0xFFFFFC64) // (PMC) Interrupt Disable Register
+#define AT91C_PMC_MOR   ((AT91_REG *) 	0xFFFFFC20) // (PMC) Main Oscillator Register
+#define AT91C_PMC_PLLR  ((AT91_REG *) 	0xFFFFFC2C) // (PMC) PLL Register
+#define AT91C_PMC_PCER  ((AT91_REG *) 	0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
+#define AT91C_PMC_PCKR  ((AT91_REG *) 	0xFFFFFC40) // (PMC) Programmable Clock Register
+#define AT91C_PMC_MCKR  ((AT91_REG *) 	0xFFFFFC30) // (PMC) Master Clock Register
+#define AT91C_PMC_SCDR  ((AT91_REG *) 	0xFFFFFC04) // (PMC) System Clock Disable Register
+#define AT91C_PMC_PCDR  ((AT91_REG *) 	0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
+#define AT91C_PMC_SCSR  ((AT91_REG *) 	0xFFFFFC08) // (PMC) System Clock Status Register
+#define AT91C_PMC_PCSR  ((AT91_REG *) 	0xFFFFFC18) // (PMC) Peripheral Clock Status Register
+#define AT91C_PMC_MCFR  ((AT91_REG *) 	0xFFFFFC24) // (PMC) Main Clock  Frequency Register
+#define AT91C_PMC_SCER  ((AT91_REG *) 	0xFFFFFC00) // (PMC) System Clock Enable Register
+#define AT91C_PMC_IMR   ((AT91_REG *) 	0xFFFFFC6C) // (PMC) Interrupt Mask Register
+#define AT91C_PMC_IER   ((AT91_REG *) 	0xFFFFFC60) // (PMC) Interrupt Enable Register
+#define AT91C_PMC_SR    ((AT91_REG *) 	0xFFFFFC68) // (PMC) Status Register
+// ========== Register definition for RSTC peripheral ========== 
+#define AT91C_RSTC_RCR  ((AT91_REG *) 	0xFFFFFD00) // (RSTC) Reset Control Register
+#define AT91C_RSTC_RMR  ((AT91_REG *) 	0xFFFFFD08) // (RSTC) Reset Mode Register
+#define AT91C_RSTC_RSR  ((AT91_REG *) 	0xFFFFFD04) // (RSTC) Reset Status Register
+// ========== Register definition for RTTC peripheral ========== 
+#define AT91C_RTTC_RTSR ((AT91_REG *) 	0xFFFFFD2C) // (RTTC) Real-time Status Register
+#define AT91C_RTTC_RTMR ((AT91_REG *) 	0xFFFFFD20) // (RTTC) Real-time Mode Register
+#define AT91C_RTTC_RTVR ((AT91_REG *) 	0xFFFFFD28) // (RTTC) Real-time Value Register
+#define AT91C_RTTC_RTAR ((AT91_REG *) 	0xFFFFFD24) // (RTTC) Real-time Alarm Register
+// ========== Register definition for PITC peripheral ========== 
+#define AT91C_PITC_PIVR ((AT91_REG *) 	0xFFFFFD38) // (PITC) Period Interval Value Register
+#define AT91C_PITC_PISR ((AT91_REG *) 	0xFFFFFD34) // (PITC) Period Interval Status Register
+#define AT91C_PITC_PIIR ((AT91_REG *) 	0xFFFFFD3C) // (PITC) Period Interval Image Register
+#define AT91C_PITC_PIMR ((AT91_REG *) 	0xFFFFFD30) // (PITC) Period Interval Mode Register
+// ========== Register definition for WDTC peripheral ========== 
+#define AT91C_WDTC_WDCR ((AT91_REG *) 	0xFFFFFD40) // (WDTC) Watchdog Control Register
+#define AT91C_WDTC_WDSR ((AT91_REG *) 	0xFFFFFD48) // (WDTC) Watchdog Status Register
+#define AT91C_WDTC_WDMR ((AT91_REG *) 	0xFFFFFD44) // (WDTC) Watchdog Mode Register
+// ========== Register definition for VREG peripheral ========== 
+#define AT91C_VREG_MR   ((AT91_REG *) 	0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
+// ========== Register definition for MC peripheral ========== 
+#define AT91C_MC_ASR    ((AT91_REG *) 	0xFFFFFF04) // (MC) MC Abort Status Register
+#define AT91C_MC_RCR    ((AT91_REG *) 	0xFFFFFF00) // (MC) MC Remap Control Register
+#define AT91C_MC_FCR    ((AT91_REG *) 	0xFFFFFF64) // (MC) MC Flash Command Register
+#define AT91C_MC_AASR   ((AT91_REG *) 	0xFFFFFF08) // (MC) MC Abort Address Status Register
+#define AT91C_MC_FSR    ((AT91_REG *) 	0xFFFFFF68) // (MC) MC Flash Status Register
+#define AT91C_MC_FMR    ((AT91_REG *) 	0xFFFFFF60) // (MC) MC Flash Mode Register
+// ========== Register definition for PDC_SPI1 peripheral ========== 
+#define AT91C_SPI1_PTCR ((AT91_REG *) 	0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
+#define AT91C_SPI1_RPR  ((AT91_REG *) 	0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
+#define AT91C_SPI1_TNCR ((AT91_REG *) 	0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
+#define AT91C_SPI1_TPR  ((AT91_REG *) 	0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
+#define AT91C_SPI1_TNPR ((AT91_REG *) 	0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
+#define AT91C_SPI1_TCR  ((AT91_REG *) 	0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
+#define AT91C_SPI1_RCR  ((AT91_REG *) 	0xFFFE4104) // (PDC_SPI1) Receive Counter Register
+#define AT91C_SPI1_RNPR ((AT91_REG *) 	0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
+#define AT91C_SPI1_RNCR ((AT91_REG *) 	0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
+#define AT91C_SPI1_PTSR ((AT91_REG *) 	0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
+// ========== Register definition for SPI1 peripheral ========== 
+#define AT91C_SPI1_IMR  ((AT91_REG *) 	0xFFFE401C) // (SPI1) Interrupt Mask Register
+#define AT91C_SPI1_IER  ((AT91_REG *) 	0xFFFE4014) // (SPI1) Interrupt Enable Register
+#define AT91C_SPI1_MR   ((AT91_REG *) 	0xFFFE4004) // (SPI1) Mode Register
+#define AT91C_SPI1_RDR  ((AT91_REG *) 	0xFFFE4008) // (SPI1) Receive Data Register
+#define AT91C_SPI1_IDR  ((AT91_REG *) 	0xFFFE4018) // (SPI1) Interrupt Disable Register
+#define AT91C_SPI1_SR   ((AT91_REG *) 	0xFFFE4010) // (SPI1) Status Register
+#define AT91C_SPI1_TDR  ((AT91_REG *) 	0xFFFE400C) // (SPI1) Transmit Data Register
+#define AT91C_SPI1_CR   ((AT91_REG *) 	0xFFFE4000) // (SPI1) Control Register
+#define AT91C_SPI1_CSR  ((AT91_REG *) 	0xFFFE4030) // (SPI1) Chip Select Register
+// ========== Register definition for PDC_SPI0 peripheral ========== 
+#define AT91C_SPI0_PTCR ((AT91_REG *) 	0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
+#define AT91C_SPI0_TPR  ((AT91_REG *) 	0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
+#define AT91C_SPI0_TCR  ((AT91_REG *) 	0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
+#define AT91C_SPI0_RCR  ((AT91_REG *) 	0xFFFE0104) // (PDC_SPI0) Receive Counter Register
+#define AT91C_SPI0_PTSR ((AT91_REG *) 	0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
+#define AT91C_SPI0_RNPR ((AT91_REG *) 	0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
+#define AT91C_SPI0_RPR  ((AT91_REG *) 	0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
+#define AT91C_SPI0_TNCR ((AT91_REG *) 	0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
+#define AT91C_SPI0_RNCR ((AT91_REG *) 	0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
+#define AT91C_SPI0_TNPR ((AT91_REG *) 	0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
+// ========== Register definition for SPI0 peripheral ========== 
+#define AT91C_SPI0_IER  ((AT91_REG *) 	0xFFFE0014) // (SPI0) Interrupt Enable Register
+#define AT91C_SPI0_SR   ((AT91_REG *) 	0xFFFE0010) // (SPI0) Status Register
+#define AT91C_SPI0_IDR  ((AT91_REG *) 	0xFFFE0018) // (SPI0) Interrupt Disable Register
+#define AT91C_SPI0_CR   ((AT91_REG *) 	0xFFFE0000) // (SPI0) Control Register
+#define AT91C_SPI0_MR   ((AT91_REG *) 	0xFFFE0004) // (SPI0) Mode Register
+#define AT91C_SPI0_IMR  ((AT91_REG *) 	0xFFFE001C) // (SPI0) Interrupt Mask Register
+#define AT91C_SPI0_TDR  ((AT91_REG *) 	0xFFFE000C) // (SPI0) Transmit Data Register
+#define AT91C_SPI0_RDR  ((AT91_REG *) 	0xFFFE0008) // (SPI0) Receive Data Register
+#define AT91C_SPI0_CSR  ((AT91_REG *) 	0xFFFE0030) // (SPI0) Chip Select Register
+// ========== Register definition for PDC_US1 peripheral ========== 
+#define AT91C_US1_RNCR  ((AT91_REG *) 	0xFFFC4114) // (PDC_US1) Receive Next Counter Register
+#define AT91C_US1_PTCR  ((AT91_REG *) 	0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
+#define AT91C_US1_TCR   ((AT91_REG *) 	0xFFFC410C) // (PDC_US1) Transmit Counter Register
+#define AT91C_US1_PTSR  ((AT91_REG *) 	0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
+#define AT91C_US1_TNPR  ((AT91_REG *) 	0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
+#define AT91C_US1_RCR   ((AT91_REG *) 	0xFFFC4104) // (PDC_US1) Receive Counter Register
+#define AT91C_US1_RNPR  ((AT91_REG *) 	0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
+#define AT91C_US1_RPR   ((AT91_REG *) 	0xFFFC4100) // (PDC_US1) Receive Pointer Register
+#define AT91C_US1_TNCR  ((AT91_REG *) 	0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
+#define AT91C_US1_TPR   ((AT91_REG *) 	0xFFFC4108) // (PDC_US1) Transmit Pointer Register
+// ========== Register definition for US1 peripheral ========== 
+#define AT91C_US1_IF    ((AT91_REG *) 	0xFFFC404C) // (US1) IRDA_FILTER Register
+#define AT91C_US1_NER   ((AT91_REG *) 	0xFFFC4044) // (US1) Nb Errors Register
+#define AT91C_US1_RTOR  ((AT91_REG *) 	0xFFFC4024) // (US1) Receiver Time-out Register
+#define AT91C_US1_CSR   ((AT91_REG *) 	0xFFFC4014) // (US1) Channel Status Register
+#define AT91C_US1_IDR   ((AT91_REG *) 	0xFFFC400C) // (US1) Interrupt Disable Register
+#define AT91C_US1_IER   ((AT91_REG *) 	0xFFFC4008) // (US1) Interrupt Enable Register
+#define AT91C_US1_THR   ((AT91_REG *) 	0xFFFC401C) // (US1) Transmitter Holding Register
+#define AT91C_US1_TTGR  ((AT91_REG *) 	0xFFFC4028) // (US1) Transmitter Time-guard Register
+#define AT91C_US1_RHR   ((AT91_REG *) 	0xFFFC4018) // (US1) Receiver Holding Register
+#define AT91C_US1_BRGR  ((AT91_REG *) 	0xFFFC4020) // (US1) Baud Rate Generator Register
+#define AT91C_US1_IMR   ((AT91_REG *) 	0xFFFC4010) // (US1) Interrupt Mask Register
+#define AT91C_US1_FIDI  ((AT91_REG *) 	0xFFFC4040) // (US1) FI_DI_Ratio Register
+#define AT91C_US1_CR    ((AT91_REG *) 	0xFFFC4000) // (US1) Control Register
+#define AT91C_US1_MR    ((AT91_REG *) 	0xFFFC4004) // (US1) Mode Register
+// ========== Register definition for PDC_US0 peripheral ========== 
+#define AT91C_US0_TNPR  ((AT91_REG *) 	0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
+#define AT91C_US0_RNPR  ((AT91_REG *) 	0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
+#define AT91C_US0_TCR   ((AT91_REG *) 	0xFFFC010C) // (PDC_US0) Transmit Counter Register
+#define AT91C_US0_PTCR  ((AT91_REG *) 	0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
+#define AT91C_US0_PTSR  ((AT91_REG *) 	0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
+#define AT91C_US0_TNCR  ((AT91_REG *) 	0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
+#define AT91C_US0_TPR   ((AT91_REG *) 	0xFFFC0108) // (PDC_US0) Transmit Pointer Register
+#define AT91C_US0_RCR   ((AT91_REG *) 	0xFFFC0104) // (PDC_US0) Receive Counter Register
+#define AT91C_US0_RPR   ((AT91_REG *) 	0xFFFC0100) // (PDC_US0) Receive Pointer Register
+#define AT91C_US0_RNCR  ((AT91_REG *) 	0xFFFC0114) // (PDC_US0) Receive Next Counter Register
+// ========== Register definition for US0 peripheral ========== 
+#define AT91C_US0_BRGR  ((AT91_REG *) 	0xFFFC0020) // (US0) Baud Rate Generator Register
+#define AT91C_US0_NER   ((AT91_REG *) 	0xFFFC0044) // (US0) Nb Errors Register
+#define AT91C_US0_CR    ((AT91_REG *) 	0xFFFC0000) // (US0) Control Register
+#define AT91C_US0_IMR   ((AT91_REG *) 	0xFFFC0010) // (US0) Interrupt Mask Register
+#define AT91C_US0_FIDI  ((AT91_REG *) 	0xFFFC0040) // (US0) FI_DI_Ratio Register
+#define AT91C_US0_TTGR  ((AT91_REG *) 	0xFFFC0028) // (US0) Transmitter Time-guard Register
+#define AT91C_US0_MR    ((AT91_REG *) 	0xFFFC0004) // (US0) Mode Register
+#define AT91C_US0_RTOR  ((AT91_REG *) 	0xFFFC0024) // (US0) Receiver Time-out Register
+#define AT91C_US0_CSR   ((AT91_REG *) 	0xFFFC0014) // (US0) Channel Status Register
+#define AT91C_US0_RHR   ((AT91_REG *) 	0xFFFC0018) // (US0) Receiver Holding Register
+#define AT91C_US0_IDR   ((AT91_REG *) 	0xFFFC000C) // (US0) Interrupt Disable Register
+#define AT91C_US0_THR   ((AT91_REG *) 	0xFFFC001C) // (US0) Transmitter Holding Register
+#define AT91C_US0_IF    ((AT91_REG *) 	0xFFFC004C) // (US0) IRDA_FILTER Register
+#define AT91C_US0_IER   ((AT91_REG *) 	0xFFFC0008) // (US0) Interrupt Enable Register
+// ========== Register definition for PDC_SSC peripheral ========== 
+#define AT91C_SSC_TNCR  ((AT91_REG *) 	0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
+#define AT91C_SSC_RPR   ((AT91_REG *) 	0xFFFD4100) // (PDC_SSC) Receive Pointer Register
+#define AT91C_SSC_RNCR  ((AT91_REG *) 	0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
+#define AT91C_SSC_TPR   ((AT91_REG *) 	0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
+#define AT91C_SSC_PTCR  ((AT91_REG *) 	0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
+#define AT91C_SSC_TCR   ((AT91_REG *) 	0xFFFD410C) // (PDC_SSC) Transmit Counter Register
+#define AT91C_SSC_RCR   ((AT91_REG *) 	0xFFFD4104) // (PDC_SSC) Receive Counter Register
+#define AT91C_SSC_RNPR  ((AT91_REG *) 	0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
+#define AT91C_SSC_TNPR  ((AT91_REG *) 	0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
+#define AT91C_SSC_PTSR  ((AT91_REG *) 	0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
+// ========== Register definition for SSC peripheral ========== 
+#define AT91C_SSC_RHR   ((AT91_REG *) 	0xFFFD4020) // (SSC) Receive Holding Register
+#define AT91C_SSC_RSHR  ((AT91_REG *) 	0xFFFD4030) // (SSC) Receive Sync Holding Register
+#define AT91C_SSC_TFMR  ((AT91_REG *) 	0xFFFD401C) // (SSC) Transmit Frame Mode Register
+#define AT91C_SSC_IDR   ((AT91_REG *) 	0xFFFD4048) // (SSC) Interrupt Disable Register
+#define AT91C_SSC_THR   ((AT91_REG *) 	0xFFFD4024) // (SSC) Transmit Holding Register
+#define AT91C_SSC_RCMR  ((AT91_REG *) 	0xFFFD4010) // (SSC) Receive Clock ModeRegister
+#define AT91C_SSC_IER   ((AT91_REG *) 	0xFFFD4044) // (SSC) Interrupt Enable Register
+#define AT91C_SSC_TSHR  ((AT91_REG *) 	0xFFFD4034) // (SSC) Transmit Sync Holding Register
+#define AT91C_SSC_SR    ((AT91_REG *) 	0xFFFD4040) // (SSC) Status Register
+#define AT91C_SSC_CMR   ((AT91_REG *) 	0xFFFD4004) // (SSC) Clock Mode Register
+#define AT91C_SSC_TCMR  ((AT91_REG *) 	0xFFFD4018) // (SSC) Transmit Clock Mode Register
+#define AT91C_SSC_CR    ((AT91_REG *) 	0xFFFD4000) // (SSC) Control Register
+#define AT91C_SSC_IMR   ((AT91_REG *) 	0xFFFD404C) // (SSC) Interrupt Mask Register
+#define AT91C_SSC_RFMR  ((AT91_REG *) 	0xFFFD4014) // (SSC) Receive Frame Mode Register
+// ========== Register definition for TWI peripheral ========== 
+#define AT91C_TWI_IER   ((AT91_REG *) 	0xFFFB8024) // (TWI) Interrupt Enable Register
+#define AT91C_TWI_CR    ((AT91_REG *) 	0xFFFB8000) // (TWI) Control Register
+#define AT91C_TWI_SR    ((AT91_REG *) 	0xFFFB8020) // (TWI) Status Register
+#define AT91C_TWI_IMR   ((AT91_REG *) 	0xFFFB802C) // (TWI) Interrupt Mask Register
+#define AT91C_TWI_THR   ((AT91_REG *) 	0xFFFB8034) // (TWI) Transmit Holding Register
+#define AT91C_TWI_IDR   ((AT91_REG *) 	0xFFFB8028) // (TWI) Interrupt Disable Register
+#define AT91C_TWI_IADR  ((AT91_REG *) 	0xFFFB800C) // (TWI) Internal Address Register
+#define AT91C_TWI_MMR   ((AT91_REG *) 	0xFFFB8004) // (TWI) Master Mode Register
+#define AT91C_TWI_CWGR  ((AT91_REG *) 	0xFFFB8010) // (TWI) Clock Waveform Generator Register
+#define AT91C_TWI_RHR   ((AT91_REG *) 	0xFFFB8030) // (TWI) Receive Holding Register
+// ========== Register definition for PWMC_CH3 peripheral ========== 
+#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 	0xFFFCC270) // (PWMC_CH3) Channel Update Register
+#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 	0xFFFCC274) // (PWMC_CH3) Reserved
+#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 	0xFFFCC268) // (PWMC_CH3) Channel Period Register
+#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 	0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
+#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 	0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
+#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 	0xFFFCC260) // (PWMC_CH3) Channel Mode Register
+// ========== Register definition for PWMC_CH2 peripheral ========== 
+#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 	0xFFFCC254) // (PWMC_CH2) Reserved
+#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 	0xFFFCC240) // (PWMC_CH2) Channel Mode Register
+#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 	0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
+#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 	0xFFFCC248) // (PWMC_CH2) Channel Period Register
+#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 	0xFFFCC250) // (PWMC_CH2) Channel Update Register
+#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 	0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
+// ========== Register definition for PWMC_CH1 peripheral ========== 
+#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 	0xFFFCC234) // (PWMC_CH1) Reserved
+#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 	0xFFFCC230) // (PWMC_CH1) Channel Update Register
+#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 	0xFFFCC228) // (PWMC_CH1) Channel Period Register
+#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 	0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
+#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 	0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
+#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 	0xFFFCC220) // (PWMC_CH1) Channel Mode Register
+// ========== Register definition for PWMC_CH0 peripheral ========== 
+#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 	0xFFFCC214) // (PWMC_CH0) Reserved
+#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 	0xFFFCC208) // (PWMC_CH0) Channel Period Register
+#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 	0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
+#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 	0xFFFCC200) // (PWMC_CH0) Channel Mode Register
+#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 	0xFFFCC210) // (PWMC_CH0) Channel Update Register
+#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 	0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
+// ========== Register definition for PWMC peripheral ========== 
+#define AT91C_PWMC_IDR  ((AT91_REG *) 	0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
+#define AT91C_PWMC_DIS  ((AT91_REG *) 	0xFFFCC008) // (PWMC) PWMC Disable Register
+#define AT91C_PWMC_IER  ((AT91_REG *) 	0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
+#define AT91C_PWMC_VR   ((AT91_REG *) 	0xFFFCC0FC) // (PWMC) PWMC Version Register
+#define AT91C_PWMC_ISR  ((AT91_REG *) 	0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
+#define AT91C_PWMC_SR   ((AT91_REG *) 	0xFFFCC00C) // (PWMC) PWMC Status Register
+#define AT91C_PWMC_IMR  ((AT91_REG *) 	0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
+#define AT91C_PWMC_MR   ((AT91_REG *) 	0xFFFCC000) // (PWMC) PWMC Mode Register
+#define AT91C_PWMC_ENA  ((AT91_REG *) 	0xFFFCC004) // (PWMC) PWMC Enable Register
+// ========== Register definition for UDP peripheral ========== 
+#define AT91C_UDP_IMR   ((AT91_REG *) 	0xFFFB0018) // (UDP) Interrupt Mask Register
+#define AT91C_UDP_FADDR ((AT91_REG *) 	0xFFFB0008) // (UDP) Function Address Register
+#define AT91C_UDP_NUM   ((AT91_REG *) 	0xFFFB0000) // (UDP) Frame Number Register
+#define AT91C_UDP_FDR   ((AT91_REG *) 	0xFFFB0050) // (UDP) Endpoint FIFO Data Register
+#define AT91C_UDP_ISR   ((AT91_REG *) 	0xFFFB001C) // (UDP) Interrupt Status Register
+#define AT91C_UDP_CSR   ((AT91_REG *) 	0xFFFB0030) // (UDP) Endpoint Control and Status Register
+#define AT91C_UDP_IDR   ((AT91_REG *) 	0xFFFB0014) // (UDP) Interrupt Disable Register
+#define AT91C_UDP_ICR   ((AT91_REG *) 	0xFFFB0020) // (UDP) Interrupt Clear Register
+#define AT91C_UDP_RSTEP ((AT91_REG *) 	0xFFFB0028) // (UDP) Reset Endpoint Register
+#define AT91C_UDP_TXVC  ((AT91_REG *) 	0xFFFB0074) // (UDP) Transceiver Control Register
+#define AT91C_UDP_GLBSTATE ((AT91_REG *) 	0xFFFB0004) // (UDP) Global State Register
+#define AT91C_UDP_IER   ((AT91_REG *) 	0xFFFB0010) // (UDP) Interrupt Enable Register
+// ========== Register definition for TC0 peripheral ========== 
+#define AT91C_TC0_SR    ((AT91_REG *) 	0xFFFA0020) // (TC0) Status Register
+#define AT91C_TC0_RC    ((AT91_REG *) 	0xFFFA001C) // (TC0) Register C
+#define AT91C_TC0_RB    ((AT91_REG *) 	0xFFFA0018) // (TC0) Register B
+#define AT91C_TC0_CCR   ((AT91_REG *) 	0xFFFA0000) // (TC0) Channel Control Register
+#define AT91C_TC0_CMR   ((AT91_REG *) 	0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC0_IER   ((AT91_REG *) 	0xFFFA0024) // (TC0) Interrupt Enable Register
+#define AT91C_TC0_RA    ((AT91_REG *) 	0xFFFA0014) // (TC0) Register A
+#define AT91C_TC0_IDR   ((AT91_REG *) 	0xFFFA0028) // (TC0) Interrupt Disable Register
+#define AT91C_TC0_CV    ((AT91_REG *) 	0xFFFA0010) // (TC0) Counter Value
+#define AT91C_TC0_IMR   ((AT91_REG *) 	0xFFFA002C) // (TC0) Interrupt Mask Register
+// ========== Register definition for TC1 peripheral ========== 
+#define AT91C_TC1_RB    ((AT91_REG *) 	0xFFFA0058) // (TC1) Register B
+#define AT91C_TC1_CCR   ((AT91_REG *) 	0xFFFA0040) // (TC1) Channel Control Register
+#define AT91C_TC1_IER   ((AT91_REG *) 	0xFFFA0064) // (TC1) Interrupt Enable Register
+#define AT91C_TC1_IDR   ((AT91_REG *) 	0xFFFA0068) // (TC1) Interrupt Disable Register
+#define AT91C_TC1_SR    ((AT91_REG *) 	0xFFFA0060) // (TC1) Status Register
+#define AT91C_TC1_CMR   ((AT91_REG *) 	0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC1_RA    ((AT91_REG *) 	0xFFFA0054) // (TC1) Register A
+#define AT91C_TC1_RC    ((AT91_REG *) 	0xFFFA005C) // (TC1) Register C
+#define AT91C_TC1_IMR   ((AT91_REG *) 	0xFFFA006C) // (TC1) Interrupt Mask Register
+#define AT91C_TC1_CV    ((AT91_REG *) 	0xFFFA0050) // (TC1) Counter Value
+// ========== Register definition for TC2 peripheral ========== 
+#define AT91C_TC2_CMR   ((AT91_REG *) 	0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC2_CCR   ((AT91_REG *) 	0xFFFA0080) // (TC2) Channel Control Register
+#define AT91C_TC2_CV    ((AT91_REG *) 	0xFFFA0090) // (TC2) Counter Value
+#define AT91C_TC2_RA    ((AT91_REG *) 	0xFFFA0094) // (TC2) Register A
+#define AT91C_TC2_RB    ((AT91_REG *) 	0xFFFA0098) // (TC2) Register B
+#define AT91C_TC2_IDR   ((AT91_REG *) 	0xFFFA00A8) // (TC2) Interrupt Disable Register
+#define AT91C_TC2_IMR   ((AT91_REG *) 	0xFFFA00AC) // (TC2) Interrupt Mask Register
+#define AT91C_TC2_RC    ((AT91_REG *) 	0xFFFA009C) // (TC2) Register C
+#define AT91C_TC2_IER   ((AT91_REG *) 	0xFFFA00A4) // (TC2) Interrupt Enable Register
+#define AT91C_TC2_SR    ((AT91_REG *) 	0xFFFA00A0) // (TC2) Status Register
+// ========== Register definition for TCB peripheral ========== 
+#define AT91C_TCB_BMR   ((AT91_REG *) 	0xFFFA00C4) // (TCB) TC Block Mode Register
+#define AT91C_TCB_BCR   ((AT91_REG *) 	0xFFFA00C0) // (TCB) TC Block Control Register
+// ========== Register definition for CAN_MB0 peripheral ========== 
+#define AT91C_CAN_MB0_MDL ((AT91_REG *) 	0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
+#define AT91C_CAN_MB0_MAM ((AT91_REG *) 	0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB0_MCR ((AT91_REG *) 	0xFFFD021C) // (CAN_MB0) MailBox Control Register
+#define AT91C_CAN_MB0_MID ((AT91_REG *) 	0xFFFD0208) // (CAN_MB0) MailBox ID Register
+#define AT91C_CAN_MB0_MSR ((AT91_REG *) 	0xFFFD0210) // (CAN_MB0) MailBox Status Register
+#define AT91C_CAN_MB0_MFID ((AT91_REG *) 	0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
+#define AT91C_CAN_MB0_MDH ((AT91_REG *) 	0xFFFD0218) // (CAN_MB0) MailBox Data High Register
+#define AT91C_CAN_MB0_MMR ((AT91_REG *) 	0xFFFD0200) // (CAN_MB0) MailBox Mode Register
+// ========== Register definition for CAN_MB1 peripheral ========== 
+#define AT91C_CAN_MB1_MDL ((AT91_REG *) 	0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
+#define AT91C_CAN_MB1_MID ((AT91_REG *) 	0xFFFD0228) // (CAN_MB1) MailBox ID Register
+#define AT91C_CAN_MB1_MMR ((AT91_REG *) 	0xFFFD0220) // (CAN_MB1) MailBox Mode Register
+#define AT91C_CAN_MB1_MSR ((AT91_REG *) 	0xFFFD0230) // (CAN_MB1) MailBox Status Register
+#define AT91C_CAN_MB1_MAM ((AT91_REG *) 	0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB1_MDH ((AT91_REG *) 	0xFFFD0238) // (CAN_MB1) MailBox Data High Register
+#define AT91C_CAN_MB1_MCR ((AT91_REG *) 	0xFFFD023C) // (CAN_MB1) MailBox Control Register
+#define AT91C_CAN_MB1_MFID ((AT91_REG *) 	0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
+// ========== Register definition for CAN_MB2 peripheral ========== 
+#define AT91C_CAN_MB2_MCR ((AT91_REG *) 	0xFFFD025C) // (CAN_MB2) MailBox Control Register
+#define AT91C_CAN_MB2_MDH ((AT91_REG *) 	0xFFFD0258) // (CAN_MB2) MailBox Data High Register
+#define AT91C_CAN_MB2_MID ((AT91_REG *) 	0xFFFD0248) // (CAN_MB2) MailBox ID Register
+#define AT91C_CAN_MB2_MDL ((AT91_REG *) 	0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
+#define AT91C_CAN_MB2_MMR ((AT91_REG *) 	0xFFFD0240) // (CAN_MB2) MailBox Mode Register
+#define AT91C_CAN_MB2_MAM ((AT91_REG *) 	0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB2_MFID ((AT91_REG *) 	0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
+#define AT91C_CAN_MB2_MSR ((AT91_REG *) 	0xFFFD0250) // (CAN_MB2) MailBox Status Register
+// ========== Register definition for CAN_MB3 peripheral ========== 
+#define AT91C_CAN_MB3_MFID ((AT91_REG *) 	0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
+#define AT91C_CAN_MB3_MAM ((AT91_REG *) 	0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB3_MID ((AT91_REG *) 	0xFFFD0268) // (CAN_MB3) MailBox ID Register
+#define AT91C_CAN_MB3_MCR ((AT91_REG *) 	0xFFFD027C) // (CAN_MB3) MailBox Control Register
+#define AT91C_CAN_MB3_MMR ((AT91_REG *) 	0xFFFD0260) // (CAN_MB3) MailBox Mode Register
+#define AT91C_CAN_MB3_MSR ((AT91_REG *) 	0xFFFD0270) // (CAN_MB3) MailBox Status Register
+#define AT91C_CAN_MB3_MDL ((AT91_REG *) 	0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
+#define AT91C_CAN_MB3_MDH ((AT91_REG *) 	0xFFFD0278) // (CAN_MB3) MailBox Data High Register
+// ========== Register definition for CAN_MB4 peripheral ========== 
+#define AT91C_CAN_MB4_MID ((AT91_REG *) 	0xFFFD0288) // (CAN_MB4) MailBox ID Register
+#define AT91C_CAN_MB4_MMR ((AT91_REG *) 	0xFFFD0280) // (CAN_MB4) MailBox Mode Register
+#define AT91C_CAN_MB4_MDH ((AT91_REG *) 	0xFFFD0298) // (CAN_MB4) MailBox Data High Register
+#define AT91C_CAN_MB4_MFID ((AT91_REG *) 	0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
+#define AT91C_CAN_MB4_MSR ((AT91_REG *) 	0xFFFD0290) // (CAN_MB4) MailBox Status Register
+#define AT91C_CAN_MB4_MCR ((AT91_REG *) 	0xFFFD029C) // (CAN_MB4) MailBox Control Register
+#define AT91C_CAN_MB4_MDL ((AT91_REG *) 	0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
+#define AT91C_CAN_MB4_MAM ((AT91_REG *) 	0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
+// ========== Register definition for CAN_MB5 peripheral ========== 
+#define AT91C_CAN_MB5_MSR ((AT91_REG *) 	0xFFFD02B0) // (CAN_MB5) MailBox Status Register
+#define AT91C_CAN_MB5_MCR ((AT91_REG *) 	0xFFFD02BC) // (CAN_MB5) MailBox Control Register
+#define AT91C_CAN_MB5_MFID ((AT91_REG *) 	0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
+#define AT91C_CAN_MB5_MDH ((AT91_REG *) 	0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
+#define AT91C_CAN_MB5_MID ((AT91_REG *) 	0xFFFD02A8) // (CAN_MB5) MailBox ID Register
+#define AT91C_CAN_MB5_MMR ((AT91_REG *) 	0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
+#define AT91C_CAN_MB5_MDL ((AT91_REG *) 	0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
+#define AT91C_CAN_MB5_MAM ((AT91_REG *) 	0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
+// ========== Register definition for CAN_MB6 peripheral ========== 
+#define AT91C_CAN_MB6_MFID ((AT91_REG *) 	0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
+#define AT91C_CAN_MB6_MID ((AT91_REG *) 	0xFFFD02C8) // (CAN_MB6) MailBox ID Register
+#define AT91C_CAN_MB6_MAM ((AT91_REG *) 	0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB6_MSR ((AT91_REG *) 	0xFFFD02D0) // (CAN_MB6) MailBox Status Register
+#define AT91C_CAN_MB6_MDL ((AT91_REG *) 	0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
+#define AT91C_CAN_MB6_MCR ((AT91_REG *) 	0xFFFD02DC) // (CAN_MB6) MailBox Control Register
+#define AT91C_CAN_MB6_MDH ((AT91_REG *) 	0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
+#define AT91C_CAN_MB6_MMR ((AT91_REG *) 	0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
+// ========== Register definition for CAN_MB7 peripheral ========== 
+#define AT91C_CAN_MB7_MCR ((AT91_REG *) 	0xFFFD02FC) // (CAN_MB7) MailBox Control Register
+#define AT91C_CAN_MB7_MDH ((AT91_REG *) 	0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
+#define AT91C_CAN_MB7_MFID ((AT91_REG *) 	0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
+#define AT91C_CAN_MB7_MDL ((AT91_REG *) 	0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
+#define AT91C_CAN_MB7_MID ((AT91_REG *) 	0xFFFD02E8) // (CAN_MB7) MailBox ID Register
+#define AT91C_CAN_MB7_MMR ((AT91_REG *) 	0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
+#define AT91C_CAN_MB7_MAM ((AT91_REG *) 	0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB7_MSR ((AT91_REG *) 	0xFFFD02F0) // (CAN_MB7) MailBox Status Register
+// ========== Register definition for CAN peripheral ========== 
+#define AT91C_CAN_TCR   ((AT91_REG *) 	0xFFFD0024) // (CAN) Transfer Command Register
+#define AT91C_CAN_IMR   ((AT91_REG *) 	0xFFFD000C) // (CAN) Interrupt Mask Register
+#define AT91C_CAN_IER   ((AT91_REG *) 	0xFFFD0004) // (CAN) Interrupt Enable Register
+#define AT91C_CAN_ECR   ((AT91_REG *) 	0xFFFD0020) // (CAN) Error Counter Register
+#define AT91C_CAN_TIMESTP ((AT91_REG *) 	0xFFFD001C) // (CAN) Time Stamp Register
+#define AT91C_CAN_MR    ((AT91_REG *) 	0xFFFD0000) // (CAN) Mode Register
+#define AT91C_CAN_IDR   ((AT91_REG *) 	0xFFFD0008) // (CAN) Interrupt Disable Register
+#define AT91C_CAN_ACR   ((AT91_REG *) 	0xFFFD0028) // (CAN) Abort Command Register
+#define AT91C_CAN_TIM   ((AT91_REG *) 	0xFFFD0018) // (CAN) Timer Register
+#define AT91C_CAN_SR    ((AT91_REG *) 	0xFFFD0010) // (CAN) Status Register
+#define AT91C_CAN_BR    ((AT91_REG *) 	0xFFFD0014) // (CAN) Baudrate Register
+#define AT91C_CAN_VR    ((AT91_REG *) 	0xFFFD00FC) // (CAN) Version Register
+// ========== Register definition for EMAC peripheral ========== 
+#define AT91C_EMAC_ISR  ((AT91_REG *) 	0xFFFDC024) // (EMAC) Interrupt Status Register
+#define AT91C_EMAC_SA4H ((AT91_REG *) 	0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
+#define AT91C_EMAC_SA1L ((AT91_REG *) 	0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
+#define AT91C_EMAC_ELE  ((AT91_REG *) 	0xFFFDC078) // (EMAC) Excessive Length Errors Register
+#define AT91C_EMAC_LCOL ((AT91_REG *) 	0xFFFDC05C) // (EMAC) Late Collision Register
+#define AT91C_EMAC_RLE  ((AT91_REG *) 	0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
+#define AT91C_EMAC_WOL  ((AT91_REG *) 	0xFFFDC0C4) // (EMAC) Wake On LAN Register
+#define AT91C_EMAC_DTF  ((AT91_REG *) 	0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
+#define AT91C_EMAC_TUND ((AT91_REG *) 	0xFFFDC064) // (EMAC) Transmit Underrun Error Register
+#define AT91C_EMAC_NCR  ((AT91_REG *) 	0xFFFDC000) // (EMAC) Network Control Register
+#define AT91C_EMAC_SA4L ((AT91_REG *) 	0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
+#define AT91C_EMAC_RSR  ((AT91_REG *) 	0xFFFDC020) // (EMAC) Receive Status Register
+#define AT91C_EMAC_SA3L ((AT91_REG *) 	0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
+#define AT91C_EMAC_TSR  ((AT91_REG *) 	0xFFFDC014) // (EMAC) Transmit Status Register
+#define AT91C_EMAC_IDR  ((AT91_REG *) 	0xFFFDC02C) // (EMAC) Interrupt Disable Register
+#define AT91C_EMAC_RSE  ((AT91_REG *) 	0xFFFDC074) // (EMAC) Receive Symbol Errors Register
+#define AT91C_EMAC_ECOL ((AT91_REG *) 	0xFFFDC060) // (EMAC) Excessive Collision Register
+#define AT91C_EMAC_TID  ((AT91_REG *) 	0xFFFDC0B8) // (EMAC) Type ID Checking Register
+#define AT91C_EMAC_HRB  ((AT91_REG *) 	0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
+#define AT91C_EMAC_TBQP ((AT91_REG *) 	0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
+#define AT91C_EMAC_USRIO ((AT91_REG *) 	0xFFFDC0C0) // (EMAC) USER Input/Output Register
+#define AT91C_EMAC_PTR  ((AT91_REG *) 	0xFFFDC038) // (EMAC) Pause Time Register
+#define AT91C_EMAC_SA2H ((AT91_REG *) 	0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
+#define AT91C_EMAC_ROV  ((AT91_REG *) 	0xFFFDC070) // (EMAC) Receive Overrun Errors Register
+#define AT91C_EMAC_ALE  ((AT91_REG *) 	0xFFFDC054) // (EMAC) Alignment Error Register
+#define AT91C_EMAC_RJA  ((AT91_REG *) 	0xFFFDC07C) // (EMAC) Receive Jabbers Register
+#define AT91C_EMAC_RBQP ((AT91_REG *) 	0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
+#define AT91C_EMAC_TPF  ((AT91_REG *) 	0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
+#define AT91C_EMAC_NCFGR ((AT91_REG *) 	0xFFFDC004) // (EMAC) Network Configuration Register
+#define AT91C_EMAC_HRT  ((AT91_REG *) 	0xFFFDC094) // (EMAC) Hash Address Top[63:32]
+#define AT91C_EMAC_USF  ((AT91_REG *) 	0xFFFDC080) // (EMAC) Undersize Frames Register
+#define AT91C_EMAC_FCSE ((AT91_REG *) 	0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
+#define AT91C_EMAC_TPQ  ((AT91_REG *) 	0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
+#define AT91C_EMAC_MAN  ((AT91_REG *) 	0xFFFDC034) // (EMAC) PHY Maintenance Register
+#define AT91C_EMAC_FTO  ((AT91_REG *) 	0xFFFDC040) // (EMAC) Frames Transmitted OK Register
+#define AT91C_EMAC_REV  ((AT91_REG *) 	0xFFFDC0FC) // (EMAC) Revision Register
+#define AT91C_EMAC_IMR  ((AT91_REG *) 	0xFFFDC030) // (EMAC) Interrupt Mask Register
+#define AT91C_EMAC_SCF  ((AT91_REG *) 	0xFFFDC044) // (EMAC) Single Collision Frame Register
+#define AT91C_EMAC_PFR  ((AT91_REG *) 	0xFFFDC03C) // (EMAC) Pause Frames received Register
+#define AT91C_EMAC_MCF  ((AT91_REG *) 	0xFFFDC048) // (EMAC) Multiple Collision Frame Register
+#define AT91C_EMAC_NSR  ((AT91_REG *) 	0xFFFDC008) // (EMAC) Network Status Register
+#define AT91C_EMAC_SA2L ((AT91_REG *) 	0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
+#define AT91C_EMAC_FRO  ((AT91_REG *) 	0xFFFDC04C) // (EMAC) Frames Received OK Register
+#define AT91C_EMAC_IER  ((AT91_REG *) 	0xFFFDC028) // (EMAC) Interrupt Enable Register
+#define AT91C_EMAC_SA1H ((AT91_REG *) 	0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
+#define AT91C_EMAC_CSE  ((AT91_REG *) 	0xFFFDC068) // (EMAC) Carrier Sense Error Register
+#define AT91C_EMAC_SA3H ((AT91_REG *) 	0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
+#define AT91C_EMAC_RRE  ((AT91_REG *) 	0xFFFDC06C) // (EMAC) Receive Ressource Error Register
+#define AT91C_EMAC_STE  ((AT91_REG *) 	0xFFFDC084) // (EMAC) SQE Test Error Register
+// ========== Register definition for PDC_ADC peripheral ========== 
+#define AT91C_ADC_PTSR  ((AT91_REG *) 	0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
+#define AT91C_ADC_PTCR  ((AT91_REG *) 	0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
+#define AT91C_ADC_TNPR  ((AT91_REG *) 	0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
+#define AT91C_ADC_TNCR  ((AT91_REG *) 	0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
+#define AT91C_ADC_RNPR  ((AT91_REG *) 	0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
+#define AT91C_ADC_RNCR  ((AT91_REG *) 	0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
+#define AT91C_ADC_RPR   ((AT91_REG *) 	0xFFFD8100) // (PDC_ADC) Receive Pointer Register
+#define AT91C_ADC_TCR   ((AT91_REG *) 	0xFFFD810C) // (PDC_ADC) Transmit Counter Register
+#define AT91C_ADC_TPR   ((AT91_REG *) 	0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
+#define AT91C_ADC_RCR   ((AT91_REG *) 	0xFFFD8104) // (PDC_ADC) Receive Counter Register
+// ========== Register definition for ADC peripheral ========== 
+#define AT91C_ADC_CDR2  ((AT91_REG *) 	0xFFFD8038) // (ADC) ADC Channel Data Register 2
+#define AT91C_ADC_CDR3  ((AT91_REG *) 	0xFFFD803C) // (ADC) ADC Channel Data Register 3
+#define AT91C_ADC_CDR0  ((AT91_REG *) 	0xFFFD8030) // (ADC) ADC Channel Data Register 0
+#define AT91C_ADC_CDR5  ((AT91_REG *) 	0xFFFD8044) // (ADC) ADC Channel Data Register 5
+#define AT91C_ADC_CHDR  ((AT91_REG *) 	0xFFFD8014) // (ADC) ADC Channel Disable Register
+#define AT91C_ADC_SR    ((AT91_REG *) 	0xFFFD801C) // (ADC) ADC Status Register
+#define AT91C_ADC_CDR4  ((AT91_REG *) 	0xFFFD8040) // (ADC) ADC Channel Data Register 4
+#define AT91C_ADC_CDR1  ((AT91_REG *) 	0xFFFD8034) // (ADC) ADC Channel Data Register 1
+#define AT91C_ADC_LCDR  ((AT91_REG *) 	0xFFFD8020) // (ADC) ADC Last Converted Data Register
+#define AT91C_ADC_IDR   ((AT91_REG *) 	0xFFFD8028) // (ADC) ADC Interrupt Disable Register
+#define AT91C_ADC_CR    ((AT91_REG *) 	0xFFFD8000) // (ADC) ADC Control Register
+#define AT91C_ADC_CDR7  ((AT91_REG *) 	0xFFFD804C) // (ADC) ADC Channel Data Register 7
+#define AT91C_ADC_CDR6  ((AT91_REG *) 	0xFFFD8048) // (ADC) ADC Channel Data Register 6
+#define AT91C_ADC_IER   ((AT91_REG *) 	0xFFFD8024) // (ADC) ADC Interrupt Enable Register
+#define AT91C_ADC_CHER  ((AT91_REG *) 	0xFFFD8010) // (ADC) ADC Channel Enable Register
+#define AT91C_ADC_CHSR  ((AT91_REG *) 	0xFFFD8018) // (ADC) ADC Channel Status Register
+#define AT91C_ADC_MR    ((AT91_REG *) 	0xFFFD8004) // (ADC) ADC Mode Register
+#define AT91C_ADC_IMR   ((AT91_REG *) 	0xFFFD802C) // (ADC) ADC Interrupt Mask Register
+// ========== Register definition for PDC_AES peripheral ========== 
+#define AT91C_AES_TPR   ((AT91_REG *) 	0xFFFA4108) // (PDC_AES) Transmit Pointer Register
+#define AT91C_AES_PTCR  ((AT91_REG *) 	0xFFFA4120) // (PDC_AES) PDC Transfer Control Register
+#define AT91C_AES_RNPR  ((AT91_REG *) 	0xFFFA4110) // (PDC_AES) Receive Next Pointer Register
+#define AT91C_AES_TNCR  ((AT91_REG *) 	0xFFFA411C) // (PDC_AES) Transmit Next Counter Register
+#define AT91C_AES_TCR   ((AT91_REG *) 	0xFFFA410C) // (PDC_AES) Transmit Counter Register
+#define AT91C_AES_RCR   ((AT91_REG *) 	0xFFFA4104) // (PDC_AES) Receive Counter Register
+#define AT91C_AES_RNCR  ((AT91_REG *) 	0xFFFA4114) // (PDC_AES) Receive Next Counter Register
+#define AT91C_AES_TNPR  ((AT91_REG *) 	0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register
+#define AT91C_AES_RPR   ((AT91_REG *) 	0xFFFA4100) // (PDC_AES) Receive Pointer Register
+#define AT91C_AES_PTSR  ((AT91_REG *) 	0xFFFA4124) // (PDC_AES) PDC Transfer Status Register
+// ========== Register definition for AES peripheral ========== 
+#define AT91C_AES_IVxR  ((AT91_REG *) 	0xFFFA4060) // (AES) Initialization Vector x Register
+#define AT91C_AES_MR    ((AT91_REG *) 	0xFFFA4004) // (AES) Mode Register
+#define AT91C_AES_VR    ((AT91_REG *) 	0xFFFA40FC) // (AES) AES Version Register
+#define AT91C_AES_ODATAxR ((AT91_REG *) 	0xFFFA4050) // (AES) Output Data x Register
+#define AT91C_AES_IDATAxR ((AT91_REG *) 	0xFFFA4040) // (AES) Input Data x Register
+#define AT91C_AES_CR    ((AT91_REG *) 	0xFFFA4000) // (AES) Control Register
+#define AT91C_AES_IDR   ((AT91_REG *) 	0xFFFA4014) // (AES) Interrupt Disable Register
+#define AT91C_AES_IMR   ((AT91_REG *) 	0xFFFA4018) // (AES) Interrupt Mask Register
+#define AT91C_AES_IER   ((AT91_REG *) 	0xFFFA4010) // (AES) Interrupt Enable Register
+#define AT91C_AES_KEYWxR ((AT91_REG *) 	0xFFFA4020) // (AES) Key Word x Register
+#define AT91C_AES_ISR   ((AT91_REG *) 	0xFFFA401C) // (AES) Interrupt Status Register
+// ========== Register definition for PDC_TDES peripheral ========== 
+#define AT91C_TDES_RNCR ((AT91_REG *) 	0xFFFA8114) // (PDC_TDES) Receive Next Counter Register
+#define AT91C_TDES_TCR  ((AT91_REG *) 	0xFFFA810C) // (PDC_TDES) Transmit Counter Register
+#define AT91C_TDES_RCR  ((AT91_REG *) 	0xFFFA8104) // (PDC_TDES) Receive Counter Register
+#define AT91C_TDES_TNPR ((AT91_REG *) 	0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register
+#define AT91C_TDES_RNPR ((AT91_REG *) 	0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register
+#define AT91C_TDES_RPR  ((AT91_REG *) 	0xFFFA8100) // (PDC_TDES) Receive Pointer Register
+#define AT91C_TDES_TNCR ((AT91_REG *) 	0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register
+#define AT91C_TDES_TPR  ((AT91_REG *) 	0xFFFA8108) // (PDC_TDES) Transmit Pointer Register
+#define AT91C_TDES_PTSR ((AT91_REG *) 	0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register
+#define AT91C_TDES_PTCR ((AT91_REG *) 	0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register
+// ========== Register definition for TDES peripheral ========== 
+#define AT91C_TDES_KEY2WxR ((AT91_REG *) 	0xFFFA8028) // (TDES) Key 2 Word x Register
+#define AT91C_TDES_KEY3WxR ((AT91_REG *) 	0xFFFA8030) // (TDES) Key 3 Word x Register
+#define AT91C_TDES_IDR  ((AT91_REG *) 	0xFFFA8014) // (TDES) Interrupt Disable Register
+#define AT91C_TDES_VR   ((AT91_REG *) 	0xFFFA80FC) // (TDES) TDES Version Register
+#define AT91C_TDES_IVxR ((AT91_REG *) 	0xFFFA8060) // (TDES) Initialization Vector x Register
+#define AT91C_TDES_ODATAxR ((AT91_REG *) 	0xFFFA8050) // (TDES) Output Data x Register
+#define AT91C_TDES_IMR  ((AT91_REG *) 	0xFFFA8018) // (TDES) Interrupt Mask Register
+#define AT91C_TDES_MR   ((AT91_REG *) 	0xFFFA8004) // (TDES) Mode Register
+#define AT91C_TDES_CR   ((AT91_REG *) 	0xFFFA8000) // (TDES) Control Register
+#define AT91C_TDES_IER  ((AT91_REG *) 	0xFFFA8010) // (TDES) Interrupt Enable Register
+#define AT91C_TDES_ISR  ((AT91_REG *) 	0xFFFA801C) // (TDES) Interrupt Status Register
+#define AT91C_TDES_IDATAxR ((AT91_REG *) 	0xFFFA8040) // (TDES) Input Data x Register
+#define AT91C_TDES_KEY1WxR ((AT91_REG *) 	0xFFFA8020) // (TDES) Key 1 Word x Register
+
+// *****************************************************************************
+//               PIO DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_PIO_PA0        ((unsigned int) 1 <<  0) // Pin Controlled by PA0
+#define AT91C_PA0_RXD0     ((unsigned int) AT91C_PIO_PA0) //  USART 0 Receive Data
+#define AT91C_PIO_PA1        ((unsigned int) 1 <<  1) // Pin Controlled by PA1
+#define AT91C_PA1_TXD0     ((unsigned int) AT91C_PIO_PA1) //  USART 0 Transmit Data
+#define AT91C_PIO_PA10       ((unsigned int) 1 << 10) // Pin Controlled by PA10
+#define AT91C_PA10_TWD      ((unsigned int) AT91C_PIO_PA10) //  TWI Two-wire Serial Data
+#define AT91C_PIO_PA11       ((unsigned int) 1 << 11) // Pin Controlled by PA11
+#define AT91C_PA11_TWCK     ((unsigned int) AT91C_PIO_PA11) //  TWI Two-wire Serial Clock
+#define AT91C_PIO_PA12       ((unsigned int) 1 << 12) // Pin Controlled by PA12
+#define AT91C_PA12_NPCS00   ((unsigned int) AT91C_PIO_PA12) //  SPI 0 Peripheral Chip Select 0
+#define AT91C_PIO_PA13       ((unsigned int) 1 << 13) // Pin Controlled by PA13
+#define AT91C_PA13_NPCS01   ((unsigned int) AT91C_PIO_PA13) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PA13_PCK1     ((unsigned int) AT91C_PIO_PA13) //  PMC Programmable Clock Output 1
+#define AT91C_PIO_PA14       ((unsigned int) 1 << 14) // Pin Controlled by PA14
+#define AT91C_PA14_NPCS02   ((unsigned int) AT91C_PIO_PA14) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PA14_IRQ1     ((unsigned int) AT91C_PIO_PA14) //  External Interrupt 1
+#define AT91C_PIO_PA15       ((unsigned int) 1 << 15) // Pin Controlled by PA15
+#define AT91C_PA15_NPCS03   ((unsigned int) AT91C_PIO_PA15) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PA15_TCLK2    ((unsigned int) AT91C_PIO_PA15) //  Timer Counter 2 external clock input
+#define AT91C_PIO_PA16       ((unsigned int) 1 << 16) // Pin Controlled by PA16
+#define AT91C_PA16_MISO0    ((unsigned int) AT91C_PIO_PA16) //  SPI 0 Master In Slave
+#define AT91C_PIO_PA17       ((unsigned int) 1 << 17) // Pin Controlled by PA17
+#define AT91C_PA17_MOSI0    ((unsigned int) AT91C_PIO_PA17) //  SPI 0 Master Out Slave
+#define AT91C_PIO_PA18       ((unsigned int) 1 << 18) // Pin Controlled by PA18
+#define AT91C_PA18_SPCK0    ((unsigned int) AT91C_PIO_PA18) //  SPI 0 Serial Clock
+#define AT91C_PIO_PA19       ((unsigned int) 1 << 19) // Pin Controlled by PA19
+#define AT91C_PA19_CANRX    ((unsigned int) AT91C_PIO_PA19) //  CAN Receive
+#define AT91C_PIO_PA2        ((unsigned int) 1 <<  2) // Pin Controlled by PA2
+#define AT91C_PA2_SCK0     ((unsigned int) AT91C_PIO_PA2) //  USART 0 Serial Clock
+#define AT91C_PA2_NPCS11   ((unsigned int) AT91C_PIO_PA2) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA20       ((unsigned int) 1 << 20) // Pin Controlled by PA20
+#define AT91C_PA20_CANTX    ((unsigned int) AT91C_PIO_PA20) //  CAN Transmit
+#define AT91C_PIO_PA21       ((unsigned int) 1 << 21) // Pin Controlled by PA21
+#define AT91C_PA21_TF       ((unsigned int) AT91C_PIO_PA21) //  SSC Transmit Frame Sync
+#define AT91C_PA21_NPCS10   ((unsigned int) AT91C_PIO_PA21) //  SPI 1 Peripheral Chip Select 0
+#define AT91C_PIO_PA22       ((unsigned int) 1 << 22) // Pin Controlled by PA22
+#define AT91C_PA22_TK       ((unsigned int) AT91C_PIO_PA22) //  SSC Transmit Clock
+#define AT91C_PA22_SPCK1    ((unsigned int) AT91C_PIO_PA22) //  SPI 1 Serial Clock
+#define AT91C_PIO_PA23       ((unsigned int) 1 << 23) // Pin Controlled by PA23
+#define AT91C_PA23_TD       ((unsigned int) AT91C_PIO_PA23) //  SSC Transmit data
+#define AT91C_PA23_MOSI1    ((unsigned int) AT91C_PIO_PA23) //  SPI 1 Master Out Slave
+#define AT91C_PIO_PA24       ((unsigned int) 1 << 24) // Pin Controlled by PA24
+#define AT91C_PA24_RD       ((unsigned int) AT91C_PIO_PA24) //  SSC Receive Data
+#define AT91C_PA24_MISO1    ((unsigned int) AT91C_PIO_PA24) //  SPI 1 Master In Slave
+#define AT91C_PIO_PA25       ((unsigned int) 1 << 25) // Pin Controlled by PA25
+#define AT91C_PA25_RK       ((unsigned int) AT91C_PIO_PA25) //  SSC Receive Clock
+#define AT91C_PA25_NPCS11   ((unsigned int) AT91C_PIO_PA25) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA26       ((unsigned int) 1 << 26) // Pin Controlled by PA26
+#define AT91C_PA26_RF       ((unsigned int) AT91C_PIO_PA26) //  SSC Receive Frame Sync
+#define AT91C_PA26_NPCS12   ((unsigned int) AT91C_PIO_PA26) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA27       ((unsigned int) 1 << 27) // Pin Controlled by PA27
+#define AT91C_PA27_DRXD     ((unsigned int) AT91C_PIO_PA27) //  DBGU Debug Receive Data
+#define AT91C_PA27_PCK3     ((unsigned int) AT91C_PIO_PA27) //  PMC Programmable Clock Output 3
+#define AT91C_PIO_PA28       ((unsigned int) 1 << 28) // Pin Controlled by PA28
+#define AT91C_PA28_DTXD     ((unsigned int) AT91C_PIO_PA28) //  DBGU Debug Transmit Data
+#define AT91C_PIO_PA29       ((unsigned int) 1 << 29) // Pin Controlled by PA29
+#define AT91C_PA29_FIQ      ((unsigned int) AT91C_PIO_PA29) //  AIC Fast Interrupt Input
+#define AT91C_PA29_NPCS13   ((unsigned int) AT91C_PIO_PA29) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA3        ((unsigned int) 1 <<  3) // Pin Controlled by PA3
+#define AT91C_PA3_RTS0     ((unsigned int) AT91C_PIO_PA3) //  USART 0 Ready To Send
+#define AT91C_PA3_NPCS12   ((unsigned int) AT91C_PIO_PA3) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA30       ((unsigned int) 1 << 30) // Pin Controlled by PA30
+#define AT91C_PA30_IRQ0     ((unsigned int) AT91C_PIO_PA30) //  External Interrupt 0
+#define AT91C_PA30_PCK2     ((unsigned int) AT91C_PIO_PA30) //  PMC Programmable Clock Output 2
+#define AT91C_PIO_PA4        ((unsigned int) 1 <<  4) // Pin Controlled by PA4
+#define AT91C_PA4_CTS0     ((unsigned int) AT91C_PIO_PA4) //  USART 0 Clear To Send
+#define AT91C_PA4_NPCS13   ((unsigned int) AT91C_PIO_PA4) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA5        ((unsigned int) 1 <<  5) // Pin Controlled by PA5
+#define AT91C_PA5_RXD1     ((unsigned int) AT91C_PIO_PA5) //  USART 1 Receive Data
+#define AT91C_PIO_PA6        ((unsigned int) 1 <<  6) // Pin Controlled by PA6
+#define AT91C_PA6_TXD1     ((unsigned int) AT91C_PIO_PA6) //  USART 1 Transmit Data
+#define AT91C_PIO_PA7        ((unsigned int) 1 <<  7) // Pin Controlled by PA7
+#define AT91C_PA7_SCK1     ((unsigned int) AT91C_PIO_PA7) //  USART 1 Serial Clock
+#define AT91C_PA7_NPCS01   ((unsigned int) AT91C_PIO_PA7) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PA8        ((unsigned int) 1 <<  8) // Pin Controlled by PA8
+#define AT91C_PA8_RTS1     ((unsigned int) AT91C_PIO_PA8) //  USART 1 Ready To Send
+#define AT91C_PA8_NPCS02   ((unsigned int) AT91C_PIO_PA8) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PA9        ((unsigned int) 1 <<  9) // Pin Controlled by PA9
+#define AT91C_PA9_CTS1     ((unsigned int) AT91C_PIO_PA9) //  USART 1 Clear To Send
+#define AT91C_PA9_NPCS03   ((unsigned int) AT91C_PIO_PA9) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB0        ((unsigned int) 1 <<  0) // Pin Controlled by PB0
+#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) //  Ethernet MAC Transmit Clock/Reference Clock
+#define AT91C_PB0_PCK0     ((unsigned int) AT91C_PIO_PB0) //  PMC Programmable Clock Output 0
+#define AT91C_PIO_PB1        ((unsigned int) 1 <<  1) // Pin Controlled by PB1
+#define AT91C_PB1_ETXEN    ((unsigned int) AT91C_PIO_PB1) //  Ethernet MAC Transmit Enable
+#define AT91C_PIO_PB10       ((unsigned int) 1 << 10) // Pin Controlled by PB10
+#define AT91C_PB10_ETX2     ((unsigned int) AT91C_PIO_PB10) //  Ethernet MAC Transmit Data 2
+#define AT91C_PB10_NPCS11   ((unsigned int) AT91C_PIO_PB10) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PB11       ((unsigned int) 1 << 11) // Pin Controlled by PB11
+#define AT91C_PB11_ETX3     ((unsigned int) AT91C_PIO_PB11) //  Ethernet MAC Transmit Data 3
+#define AT91C_PB11_NPCS12   ((unsigned int) AT91C_PIO_PB11) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PB12       ((unsigned int) 1 << 12) // Pin Controlled by PB12
+#define AT91C_PB12_ETXER    ((unsigned int) AT91C_PIO_PB12) //  Ethernet MAC Transmikt Coding Error
+#define AT91C_PB12_TCLK0    ((unsigned int) AT91C_PIO_PB12) //  Timer Counter 0 external clock input
+#define AT91C_PIO_PB13       ((unsigned int) 1 << 13) // Pin Controlled by PB13
+#define AT91C_PB13_ERX2     ((unsigned int) AT91C_PIO_PB13) //  Ethernet MAC Receive Data 2
+#define AT91C_PB13_NPCS01   ((unsigned int) AT91C_PIO_PB13) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PB14       ((unsigned int) 1 << 14) // Pin Controlled by PB14
+#define AT91C_PB14_ERX3     ((unsigned int) AT91C_PIO_PB14) //  Ethernet MAC Receive Data 3
+#define AT91C_PB14_NPCS02   ((unsigned int) AT91C_PIO_PB14) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PB15       ((unsigned int) 1 << 15) // Pin Controlled by PB15
+#define AT91C_PB15_ERXDV    ((unsigned int) AT91C_PIO_PB15) //  Ethernet MAC Receive Data Valid
+#define AT91C_PIO_PB16       ((unsigned int) 1 << 16) // Pin Controlled by PB16
+#define AT91C_PB16_ECOL     ((unsigned int) AT91C_PIO_PB16) //  Ethernet MAC Collision Detected
+#define AT91C_PB16_NPCS13   ((unsigned int) AT91C_PIO_PB16) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PB17       ((unsigned int) 1 << 17) // Pin Controlled by PB17
+#define AT91C_PB17_ERXCK    ((unsigned int) AT91C_PIO_PB17) //  Ethernet MAC Receive Clock
+#define AT91C_PB17_NPCS03   ((unsigned int) AT91C_PIO_PB17) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB18       ((unsigned int) 1 << 18) // Pin Controlled by PB18
+#define AT91C_PB18_EF100    ((unsigned int) AT91C_PIO_PB18) //  Ethernet MAC Force 100 Mbits/sec
+#define AT91C_PB18_ADTRG    ((unsigned int) AT91C_PIO_PB18) //  ADC External Trigger
+#define AT91C_PIO_PB19       ((unsigned int) 1 << 19) // Pin Controlled by PB19
+#define AT91C_PB19_PWM0     ((unsigned int) AT91C_PIO_PB19) //  PWM Channel 0
+#define AT91C_PB19_TCLK1    ((unsigned int) AT91C_PIO_PB19) //  Timer Counter 1 external clock input
+#define AT91C_PIO_PB2        ((unsigned int) 1 <<  2) // Pin Controlled by PB2
+#define AT91C_PB2_ETX0     ((unsigned int) AT91C_PIO_PB2) //  Ethernet MAC Transmit Data 0
+#define AT91C_PIO_PB20       ((unsigned int) 1 << 20) // Pin Controlled by PB20
+#define AT91C_PB20_PWM1     ((unsigned int) AT91C_PIO_PB20) //  PWM Channel 1
+#define AT91C_PB20_PCK0     ((unsigned int) AT91C_PIO_PB20) //  PMC Programmable Clock Output 0
+#define AT91C_PIO_PB21       ((unsigned int) 1 << 21) // Pin Controlled by PB21
+#define AT91C_PB21_PWM2     ((unsigned int) AT91C_PIO_PB21) //  PWM Channel 2
+#define AT91C_PB21_PCK1     ((unsigned int) AT91C_PIO_PB21) //  PMC Programmable Clock Output 1
+#define AT91C_PIO_PB22       ((unsigned int) 1 << 22) // Pin Controlled by PB22
+#define AT91C_PB22_PWM3     ((unsigned int) AT91C_PIO_PB22) //  PWM Channel 3
+#define AT91C_PB22_PCK2     ((unsigned int) AT91C_PIO_PB22) //  PMC Programmable Clock Output 2
+#define AT91C_PIO_PB23       ((unsigned int) 1 << 23) // Pin Controlled by PB23
+#define AT91C_PB23_TIOA0    ((unsigned int) AT91C_PIO_PB23) //  Timer Counter 0 Multipurpose Timer I/O Pin A
+#define AT91C_PB23_DCD1     ((unsigned int) AT91C_PIO_PB23) //  USART 1 Data Carrier Detect
+#define AT91C_PIO_PB24       ((unsigned int) 1 << 24) // Pin Controlled by PB24
+#define AT91C_PB24_TIOB0    ((unsigned int) AT91C_PIO_PB24) //  Timer Counter 0 Multipurpose Timer I/O Pin B
+#define AT91C_PB24_DSR1     ((unsigned int) AT91C_PIO_PB24) //  USART 1 Data Set ready
+#define AT91C_PIO_PB25       ((unsigned int) 1 << 25) // Pin Controlled by PB25
+#define AT91C_PB25_TIOA1    ((unsigned int) AT91C_PIO_PB25) //  Timer Counter 1 Multipurpose Timer I/O Pin A
+#define AT91C_PB25_DTR1     ((unsigned int) AT91C_PIO_PB25) //  USART 1 Data Terminal ready
+#define AT91C_PIO_PB26       ((unsigned int) 1 << 26) // Pin Controlled by PB26
+#define AT91C_PB26_TIOB1    ((unsigned int) AT91C_PIO_PB26) //  Timer Counter 1 Multipurpose Timer I/O Pin B
+#define AT91C_PB26_RI1      ((unsigned int) AT91C_PIO_PB26) //  USART 1 Ring Indicator
+#define AT91C_PIO_PB27       ((unsigned int) 1 << 27) // Pin Controlled by PB27
+#define AT91C_PB27_TIOA2    ((unsigned int) AT91C_PIO_PB27) //  Timer Counter 2 Multipurpose Timer I/O Pin A
+#define AT91C_PB27_PWM0     ((unsigned int) AT91C_PIO_PB27) //  PWM Channel 0
+#define AT91C_PIO_PB28       ((unsigned int) 1 << 28) // Pin Controlled by PB28
+#define AT91C_PB28_TIOB2    ((unsigned int) AT91C_PIO_PB28) //  Timer Counter 2 Multipurpose Timer I/O Pin B
+#define AT91C_PB28_PWM1     ((unsigned int) AT91C_PIO_PB28) //  PWM Channel 1
+#define AT91C_PIO_PB29       ((unsigned int) 1 << 29) // Pin Controlled by PB29
+#define AT91C_PB29_PCK1     ((unsigned int) AT91C_PIO_PB29) //  PMC Programmable Clock Output 1
+#define AT91C_PB29_PWM2     ((unsigned int) AT91C_PIO_PB29) //  PWM Channel 2
+#define AT91C_PIO_PB3        ((unsigned int) 1 <<  3) // Pin Controlled by PB3
+#define AT91C_PB3_ETX1     ((unsigned int) AT91C_PIO_PB3) //  Ethernet MAC Transmit Data 1
+#define AT91C_PIO_PB30       ((unsigned int) 1 << 30) // Pin Controlled by PB30
+#define AT91C_PB30_PCK2     ((unsigned int) AT91C_PIO_PB30) //  PMC Programmable Clock Output 2
+#define AT91C_PB30_PWM3     ((unsigned int) AT91C_PIO_PB30) //  PWM Channel 3
+#define AT91C_PIO_PB4        ((unsigned int) 1 <<  4) // Pin Controlled by PB4
+#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) //  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
+#define AT91C_PIO_PB5        ((unsigned int) 1 <<  5) // Pin Controlled by PB5
+#define AT91C_PB5_ERX0     ((unsigned int) AT91C_PIO_PB5) //  Ethernet MAC Receive Data 0
+#define AT91C_PIO_PB6        ((unsigned int) 1 <<  6) // Pin Controlled by PB6
+#define AT91C_PB6_ERX1     ((unsigned int) AT91C_PIO_PB6) //  Ethernet MAC Receive Data 1
+#define AT91C_PIO_PB7        ((unsigned int) 1 <<  7) // Pin Controlled by PB7
+#define AT91C_PB7_ERXER    ((unsigned int) AT91C_PIO_PB7) //  Ethernet MAC Receive Error
+#define AT91C_PIO_PB8        ((unsigned int) 1 <<  8) // Pin Controlled by PB8
+#define AT91C_PB8_EMDC     ((unsigned int) AT91C_PIO_PB8) //  Ethernet MAC Management Data Clock
+#define AT91C_PIO_PB9        ((unsigned int) 1 <<  9) // Pin Controlled by PB9
+#define AT91C_PB9_EMDIO    ((unsigned int) AT91C_PIO_PB9) //  Ethernet MAC Management Data Input/Output
+
+// *****************************************************************************
+//               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_ID_FIQ    ((unsigned int)  0) // Advanced Interrupt Controller (FIQ)
+#define AT91C_ID_SYS    ((unsigned int)  1) // System Peripheral
+#define AT91C_ID_PIOA   ((unsigned int)  2) // Parallel IO Controller A
+#define AT91C_ID_PIOB   ((unsigned int)  3) // Parallel IO Controller B
+#define AT91C_ID_SPI0   ((unsigned int)  4) // Serial Peripheral Interface 0
+#define AT91C_ID_SPI1   ((unsigned int)  5) // Serial Peripheral Interface 1
+#define AT91C_ID_US0    ((unsigned int)  6) // USART 0
+#define AT91C_ID_US1    ((unsigned int)  7) // USART 1
+#define AT91C_ID_SSC    ((unsigned int)  8) // Serial Synchronous Controller
+#define AT91C_ID_TWI    ((unsigned int)  9) // Two-Wire Interface
+#define AT91C_ID_PWMC   ((unsigned int) 10) // PWM Controller
+#define AT91C_ID_UDP    ((unsigned int) 11) // USB Device Port
+#define AT91C_ID_TC0    ((unsigned int) 12) // Timer Counter 0
+#define AT91C_ID_TC1    ((unsigned int) 13) // Timer Counter 1
+#define AT91C_ID_TC2    ((unsigned int) 14) // Timer Counter 2
+#define AT91C_ID_CAN    ((unsigned int) 15) // Control Area Network Controller
+#define AT91C_ID_EMAC   ((unsigned int) 16) // Ethernet MAC
+#define AT91C_ID_ADC    ((unsigned int) 17) // Analog-to-Digital Converter
+#define AT91C_ID_AES    ((unsigned int) 18) // Advanced Encryption Standard 128-bit
+#define AT91C_ID_TDES   ((unsigned int) 19) // Triple Data Encryption Standard
+#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved
+#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved
+#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved
+#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved
+#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved
+#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved
+#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved
+#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved
+#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved
+#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved
+#define AT91C_ID_IRQ0   ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)
+#define AT91C_ID_IRQ1   ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)
+
+// *****************************************************************************
+//               BASE ADDRESS DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_BASE_SYS       ((AT91PS_SYS) 	0xFFFFF000) // (SYS) Base Address
+#define AT91C_BASE_AIC       ((AT91PS_AIC) 	0xFFFFF000) // (AIC) Base Address
+#define AT91C_BASE_PDC_DBGU  ((AT91PS_PDC) 	0xFFFFF300) // (PDC_DBGU) Base Address
+#define AT91C_BASE_DBGU      ((AT91PS_DBGU) 	0xFFFFF200) // (DBGU) Base Address
+#define AT91C_BASE_PIOA      ((AT91PS_PIO) 	0xFFFFF400) // (PIOA) Base Address
+#define AT91C_BASE_PIOB      ((AT91PS_PIO) 	0xFFFFF600) // (PIOB) Base Address
+#define AT91C_BASE_CKGR      ((AT91PS_CKGR) 	0xFFFFFC20) // (CKGR) Base Address
+#define AT91C_BASE_PMC       ((AT91PS_PMC) 	0xFFFFFC00) // (PMC) Base Address
+#define AT91C_BASE_RSTC      ((AT91PS_RSTC) 	0xFFFFFD00) // (RSTC) Base Address
+#define AT91C_BASE_RTTC      ((AT91PS_RTTC) 	0xFFFFFD20) // (RTTC) Base Address
+#define AT91C_BASE_PITC      ((AT91PS_PITC) 	0xFFFFFD30) // (PITC) Base Address
+#define AT91C_BASE_WDTC      ((AT91PS_WDTC) 	0xFFFFFD40) // (WDTC) Base Address
+#define AT91C_BASE_VREG      ((AT91PS_VREG) 	0xFFFFFD60) // (VREG) Base Address
+#define AT91C_BASE_MC        ((AT91PS_MC) 	0xFFFFFF00) // (MC) Base Address
+#define AT91C_BASE_PDC_SPI1  ((AT91PS_PDC) 	0xFFFE4100) // (PDC_SPI1) Base Address
+#define AT91C_BASE_SPI1      ((AT91PS_SPI) 	0xFFFE4000) // (SPI1) Base Address
+#define AT91C_BASE_PDC_SPI0  ((AT91PS_PDC) 	0xFFFE0100) // (PDC_SPI0) Base Address
+#define AT91C_BASE_SPI0      ((AT91PS_SPI) 	0xFFFE0000) // (SPI0) Base Address
+#define AT91C_BASE_PDC_US1   ((AT91PS_PDC) 	0xFFFC4100) // (PDC_US1) Base Address
+#define AT91C_BASE_US1       ((AT91PS_USART) 	0xFFFC4000) // (US1) Base Address
+#define AT91C_BASE_PDC_US0   ((AT91PS_PDC) 	0xFFFC0100) // (PDC_US0) Base Address
+#define AT91C_BASE_US0       ((AT91PS_USART) 	0xFFFC0000) // (US0) Base Address
+#define AT91C_BASE_PDC_SSC   ((AT91PS_PDC) 	0xFFFD4100) // (PDC_SSC) Base Address
+#define AT91C_BASE_SSC       ((AT91PS_SSC) 	0xFFFD4000) // (SSC) Base Address
+#define AT91C_BASE_TWI       ((AT91PS_TWI) 	0xFFFB8000) // (TWI) Base Address
+#define AT91C_BASE_PWMC_CH3  ((AT91PS_PWMC_CH) 	0xFFFCC260) // (PWMC_CH3) Base Address
+#define AT91C_BASE_PWMC_CH2  ((AT91PS_PWMC_CH) 	0xFFFCC240) // (PWMC_CH2) Base Address
+#define AT91C_BASE_PWMC_CH1  ((AT91PS_PWMC_CH) 	0xFFFCC220) // (PWMC_CH1) Base Address
+#define AT91C_BASE_PWMC_CH0  ((AT91PS_PWMC_CH) 	0xFFFCC200) // (PWMC_CH0) Base Address
+#define AT91C_BASE_PWMC      ((AT91PS_PWMC) 	0xFFFCC000) // (PWMC) Base Address
+#define AT91C_BASE_UDP       ((AT91PS_UDP) 	0xFFFB0000) // (UDP) Base Address
+#define AT91C_BASE_TC0       ((AT91PS_TC) 	0xFFFA0000) // (TC0) Base Address
+#define AT91C_BASE_TC1       ((AT91PS_TC) 	0xFFFA0040) // (TC1) Base Address
+#define AT91C_BASE_TC2       ((AT91PS_TC) 	0xFFFA0080) // (TC2) Base Address
+#define AT91C_BASE_TCB       ((AT91PS_TCB) 	0xFFFA0000) // (TCB) Base Address
+#define AT91C_BASE_CAN_MB0   ((AT91PS_CAN_MB) 	0xFFFD0200) // (CAN_MB0) Base Address
+#define AT91C_BASE_CAN_MB1   ((AT91PS_CAN_MB) 	0xFFFD0220) // (CAN_MB1) Base Address
+#define AT91C_BASE_CAN_MB2   ((AT91PS_CAN_MB) 	0xFFFD0240) // (CAN_MB2) Base Address
+#define AT91C_BASE_CAN_MB3   ((AT91PS_CAN_MB) 	0xFFFD0260) // (CAN_MB3) Base Address
+#define AT91C_BASE_CAN_MB4   ((AT91PS_CAN_MB) 	0xFFFD0280) // (CAN_MB4) Base Address
+#define AT91C_BASE_CAN_MB5   ((AT91PS_CAN_MB) 	0xFFFD02A0) // (CAN_MB5) Base Address
+#define AT91C_BASE_CAN_MB6   ((AT91PS_CAN_MB) 	0xFFFD02C0) // (CAN_MB6) Base Address
+#define AT91C_BASE_CAN_MB7   ((AT91PS_CAN_MB) 	0xFFFD02E0) // (CAN_MB7) Base Address
+#define AT91C_BASE_CAN       ((AT91PS_CAN) 	0xFFFD0000) // (CAN) Base Address
+#define AT91C_BASE_EMAC      ((AT91PS_EMAC) 	0xFFFDC000) // (EMAC) Base Address
+#define AT91C_BASE_PDC_ADC   ((AT91PS_PDC) 	0xFFFD8100) // (PDC_ADC) Base Address
+#define AT91C_BASE_ADC       ((AT91PS_ADC) 	0xFFFD8000) // (ADC) Base Address
+#define AT91C_BASE_PDC_AES   ((AT91PS_PDC) 	0xFFFA4100) // (PDC_AES) Base Address
+#define AT91C_BASE_AES       ((AT91PS_AES) 	0xFFFA4000) // (AES) Base Address
+#define AT91C_BASE_PDC_TDES  ((AT91PS_PDC) 	0xFFFA8100) // (PDC_TDES) Base Address
+#define AT91C_BASE_TDES      ((AT91PS_TDES) 	0xFFFA8000) // (TDES) Base Address
+
+// *****************************************************************************
+//               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_ISRAM	 ((char *) 	0x00200000) // Internal SRAM base address
+#define AT91C_ISRAM_SIZE	 ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte)
+#define AT91C_IFLASH	 ((char *) 	0x00100000) // Internal ROM base address
+#define AT91C_IFLASH_SIZE	 ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte)
+#endif /* __IAR_SYSTEMS_ICC__ */
+
+#ifdef __IAR_SYSTEMS_ASM__
+
+// - Hardware register definition
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR System Peripherals
+// - *****************************************************************************
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
+// - *****************************************************************************
+// - -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
+AT91C_AIC_PRIOR           EQU (0x7 <<  0) ;- (AIC) Priority Level
+AT91C_AIC_PRIOR_LOWEST    EQU (0x0) ;- (AIC) Lowest priority level
+AT91C_AIC_PRIOR_HIGHEST   EQU (0x7) ;- (AIC) Highest priority level
+AT91C_AIC_SRCTYPE         EQU (0x3 <<  5) ;- (AIC) Interrupt Source Type
+AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL EQU (0x0 <<  5) ;- (AIC) Internal Sources Code Label High-level Sensitive
+AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL EQU (0x0 <<  5) ;- (AIC) External Sources Code Label Low-level Sensitive
+AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE EQU (0x1 <<  5) ;- (AIC) Internal Sources Code Label Positive Edge triggered
+AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE EQU (0x1 <<  5) ;- (AIC) External Sources Code Label Negative Edge triggered
+AT91C_AIC_SRCTYPE_HIGH_LEVEL EQU (0x2 <<  5) ;- (AIC) Internal Or External Sources Code Label High-level Sensitive
+AT91C_AIC_SRCTYPE_POSITIVE_EDGE EQU (0x3 <<  5) ;- (AIC) Internal Or External Sources Code Label Positive Edge triggered
+// - -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
+AT91C_AIC_NFIQ            EQU (0x1 <<  0) ;- (AIC) NFIQ Status
+AT91C_AIC_NIRQ            EQU (0x1 <<  1) ;- (AIC) NIRQ Status
+// - -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
+AT91C_AIC_DCR_PROT        EQU (0x1 <<  0) ;- (AIC) Protection Mode
+AT91C_AIC_DCR_GMSK        EQU (0x1 <<  1) ;- (AIC) General Mask
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
+// - *****************************************************************************
+// - -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
+AT91C_PDC_RXTEN           EQU (0x1 <<  0) ;- (PDC) Receiver Transfer Enable
+AT91C_PDC_RXTDIS          EQU (0x1 <<  1) ;- (PDC) Receiver Transfer Disable
+AT91C_PDC_TXTEN           EQU (0x1 <<  8) ;- (PDC) Transmitter Transfer Enable
+AT91C_PDC_TXTDIS          EQU (0x1 <<  9) ;- (PDC) Transmitter Transfer Disable
+// - -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Debug Unit
+// - *****************************************************************************
+// - -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
+AT91C_US_RSTRX            EQU (0x1 <<  2) ;- (DBGU) Reset Receiver
+AT91C_US_RSTTX            EQU (0x1 <<  3) ;- (DBGU) Reset Transmitter
+AT91C_US_RXEN             EQU (0x1 <<  4) ;- (DBGU) Receiver Enable
+AT91C_US_RXDIS            EQU (0x1 <<  5) ;- (DBGU) Receiver Disable
+AT91C_US_TXEN             EQU (0x1 <<  6) ;- (DBGU) Transmitter Enable
+AT91C_US_TXDIS            EQU (0x1 <<  7) ;- (DBGU) Transmitter Disable
+AT91C_US_RSTSTA           EQU (0x1 <<  8) ;- (DBGU) Reset Status Bits
+// - -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
+AT91C_US_PAR              EQU (0x7 <<  9) ;- (DBGU) Parity type
+AT91C_US_PAR_EVEN         EQU (0x0 <<  9) ;- (DBGU) Even Parity
+AT91C_US_PAR_ODD          EQU (0x1 <<  9) ;- (DBGU) Odd Parity
+AT91C_US_PAR_SPACE        EQU (0x2 <<  9) ;- (DBGU) Parity forced to 0 (Space)
+AT91C_US_PAR_MARK         EQU (0x3 <<  9) ;- (DBGU) Parity forced to 1 (Mark)
+AT91C_US_PAR_NONE         EQU (0x4 <<  9) ;- (DBGU) No Parity
+AT91C_US_PAR_MULTI_DROP   EQU (0x6 <<  9) ;- (DBGU) Multi-drop mode
+AT91C_US_CHMODE           EQU (0x3 << 14) ;- (DBGU) Channel Mode
+AT91C_US_CHMODE_NORMAL    EQU (0x0 << 14) ;- (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+AT91C_US_CHMODE_AUTO      EQU (0x1 << 14) ;- (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+AT91C_US_CHMODE_LOCAL     EQU (0x2 << 14) ;- (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+AT91C_US_CHMODE_REMOTE    EQU (0x3 << 14) ;- (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+// - -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+AT91C_US_RXRDY            EQU (0x1 <<  0) ;- (DBGU) RXRDY Interrupt
+AT91C_US_TXRDY            EQU (0x1 <<  1) ;- (DBGU) TXRDY Interrupt
+AT91C_US_ENDRX            EQU (0x1 <<  3) ;- (DBGU) End of Receive Transfer Interrupt
+AT91C_US_ENDTX            EQU (0x1 <<  4) ;- (DBGU) End of Transmit Interrupt
+AT91C_US_OVRE             EQU (0x1 <<  5) ;- (DBGU) Overrun Interrupt
+AT91C_US_FRAME            EQU (0x1 <<  6) ;- (DBGU) Framing Error Interrupt
+AT91C_US_PARE             EQU (0x1 <<  7) ;- (DBGU) Parity Error Interrupt
+AT91C_US_TXEMPTY          EQU (0x1 <<  9) ;- (DBGU) TXEMPTY Interrupt
+AT91C_US_TXBUFE           EQU (0x1 << 11) ;- (DBGU) TXBUFE Interrupt
+AT91C_US_RXBUFF           EQU (0x1 << 12) ;- (DBGU) RXBUFF Interrupt
+AT91C_US_COMM_TX          EQU (0x1 << 30) ;- (DBGU) COMM_TX Interrupt
+AT91C_US_COMM_RX          EQU (0x1 << 31) ;- (DBGU) COMM_RX Interrupt
+// - -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// - -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// - -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
+// - -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
+AT91C_US_FORCE_NTRST      EQU (0x1 <<  0) ;- (DBGU) Force NTRST in JTAG
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
+// - *****************************************************************************
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Clock Generator Controler
+// - *****************************************************************************
+// - -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 
+AT91C_CKGR_MOSCEN         EQU (0x1 <<  0) ;- (CKGR) Main Oscillator Enable
+AT91C_CKGR_OSCBYPASS      EQU (0x1 <<  1) ;- (CKGR) Main Oscillator Bypass
+AT91C_CKGR_OSCOUNT        EQU (0xFF <<  8) ;- (CKGR) Main Oscillator Start-up Time
+// - -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 
+AT91C_CKGR_MAINF          EQU (0xFFFF <<  0) ;- (CKGR) Main Clock Frequency
+AT91C_CKGR_MAINRDY        EQU (0x1 << 16) ;- (CKGR) Main Clock Ready
+// - -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- 
+AT91C_CKGR_DIV            EQU (0xFF <<  0) ;- (CKGR) Divider Selected
+AT91C_CKGR_DIV_0          EQU (0x0) ;- (CKGR) Divider output is 0
+AT91C_CKGR_DIV_BYPASS     EQU (0x1) ;- (CKGR) Divider is bypassed
+AT91C_CKGR_PLLCOUNT       EQU (0x3F <<  8) ;- (CKGR) PLL Counter
+AT91C_CKGR_OUT            EQU (0x3 << 14) ;- (CKGR) PLL Output Frequency Range
+AT91C_CKGR_OUT_0          EQU (0x0 << 14) ;- (CKGR) Please refer to the PLL datasheet
+AT91C_CKGR_OUT_1          EQU (0x1 << 14) ;- (CKGR) Please refer to the PLL datasheet
+AT91C_CKGR_OUT_2          EQU (0x2 << 14) ;- (CKGR) Please refer to the PLL datasheet
+AT91C_CKGR_OUT_3          EQU (0x3 << 14) ;- (CKGR) Please refer to the PLL datasheet
+AT91C_CKGR_MUL            EQU (0x7FF << 16) ;- (CKGR) PLL Multiplier
+AT91C_CKGR_USBDIV         EQU (0x3 << 28) ;- (CKGR) Divider for USB Clocks
+AT91C_CKGR_USBDIV_0       EQU (0x0 << 28) ;- (CKGR) Divider output is PLL clock output
+AT91C_CKGR_USBDIV_1       EQU (0x1 << 28) ;- (CKGR) Divider output is PLL clock output divided by 2
+AT91C_CKGR_USBDIV_2       EQU (0x2 << 28) ;- (CKGR) Divider output is PLL clock output divided by 4
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Power Management Controler
+// - *****************************************************************************
+// - -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
+AT91C_PMC_PCK             EQU (0x1 <<  0) ;- (PMC) Processor Clock
+AT91C_PMC_UDP             EQU (0x1 <<  7) ;- (PMC) USB Device Port Clock
+AT91C_PMC_PCK0            EQU (0x1 <<  8) ;- (PMC) Programmable Clock Output
+AT91C_PMC_PCK1            EQU (0x1 <<  9) ;- (PMC) Programmable Clock Output
+AT91C_PMC_PCK2            EQU (0x1 << 10) ;- (PMC) Programmable Clock Output
+AT91C_PMC_PCK3            EQU (0x1 << 11) ;- (PMC) Programmable Clock Output
+// - -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
+// - -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
+// - -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 
+// - -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 
+// - -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- 
+// - -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
+AT91C_PMC_CSS             EQU (0x3 <<  0) ;- (PMC) Programmable Clock Selection
+AT91C_PMC_CSS_SLOW_CLK    EQU (0x0) ;- (PMC) Slow Clock is selected
+AT91C_PMC_CSS_MAIN_CLK    EQU (0x1) ;- (PMC) Main Clock is selected
+AT91C_PMC_CSS_PLL_CLK     EQU (0x3) ;- (PMC) Clock from PLL is selected
+AT91C_PMC_PRES            EQU (0x7 <<  2) ;- (PMC) Programmable Clock Prescaler
+AT91C_PMC_PRES_CLK        EQU (0x0 <<  2) ;- (PMC) Selected clock
+AT91C_PMC_PRES_CLK_2      EQU (0x1 <<  2) ;- (PMC) Selected clock divided by 2
+AT91C_PMC_PRES_CLK_4      EQU (0x2 <<  2) ;- (PMC) Selected clock divided by 4
+AT91C_PMC_PRES_CLK_8      EQU (0x3 <<  2) ;- (PMC) Selected clock divided by 8
+AT91C_PMC_PRES_CLK_16     EQU (0x4 <<  2) ;- (PMC) Selected clock divided by 16
+AT91C_PMC_PRES_CLK_32     EQU (0x5 <<  2) ;- (PMC) Selected clock divided by 32
+AT91C_PMC_PRES_CLK_64     EQU (0x6 <<  2) ;- (PMC) Selected clock divided by 64
+// - -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
+// - -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
+AT91C_PMC_MOSCS           EQU (0x1 <<  0) ;- (PMC) MOSC Status/Enable/Disable/Mask
+AT91C_PMC_LOCK            EQU (0x1 <<  2) ;- (PMC) PLL Status/Enable/Disable/Mask
+AT91C_PMC_MCKRDY          EQU (0x1 <<  3) ;- (PMC) MCK_RDY Status/Enable/Disable/Mask
+AT91C_PMC_PCK0RDY         EQU (0x1 <<  8) ;- (PMC) PCK0_RDY Status/Enable/Disable/Mask
+AT91C_PMC_PCK1RDY         EQU (0x1 <<  9) ;- (PMC) PCK1_RDY Status/Enable/Disable/Mask
+AT91C_PMC_PCK2RDY         EQU (0x1 << 10) ;- (PMC) PCK2_RDY Status/Enable/Disable/Mask
+AT91C_PMC_PCK3RDY         EQU (0x1 << 11) ;- (PMC) PCK3_RDY Status/Enable/Disable/Mask
+// - -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
+// - -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
+// - -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Reset Controller Interface
+// - *****************************************************************************
+// - -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 
+AT91C_RSTC_PROCRST        EQU (0x1 <<  0) ;- (RSTC) Processor Reset
+AT91C_RSTC_PERRST         EQU (0x1 <<  2) ;- (RSTC) Peripheral Reset
+AT91C_RSTC_EXTRST         EQU (0x1 <<  3) ;- (RSTC) External Reset
+AT91C_RSTC_KEY            EQU (0xFF << 24) ;- (RSTC) Password
+// - -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 
+AT91C_RSTC_URSTS          EQU (0x1 <<  0) ;- (RSTC) User Reset Status
+AT91C_RSTC_BODSTS         EQU (0x1 <<  1) ;- (RSTC) Brownout Detection Status
+AT91C_RSTC_RSTTYP         EQU (0x7 <<  8) ;- (RSTC) Reset Type
+AT91C_RSTC_RSTTYP_POWERUP EQU (0x0 <<  8) ;- (RSTC) Power-up Reset. VDDCORE rising.
+AT91C_RSTC_RSTTYP_WAKEUP  EQU (0x1 <<  8) ;- (RSTC) WakeUp Reset. VDDCORE rising.
+AT91C_RSTC_RSTTYP_WATCHDOG EQU (0x2 <<  8) ;- (RSTC) Watchdog Reset. Watchdog overflow occured.
+AT91C_RSTC_RSTTYP_SOFTWARE EQU (0x3 <<  8) ;- (RSTC) Software Reset. Processor reset required by the software.
+AT91C_RSTC_RSTTYP_USER    EQU (0x4 <<  8) ;- (RSTC) User Reset. NRST pin detected low.
+AT91C_RSTC_RSTTYP_BROWNOUT EQU (0x5 <<  8) ;- (RSTC) Brownout Reset occured.
+AT91C_RSTC_NRSTL          EQU (0x1 << 16) ;- (RSTC) NRST pin level
+AT91C_RSTC_SRCMP          EQU (0x1 << 17) ;- (RSTC) Software Reset Command in Progress.
+// - -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 
+AT91C_RSTC_URSTEN         EQU (0x1 <<  0) ;- (RSTC) User Reset Enable
+AT91C_RSTC_URSTIEN        EQU (0x1 <<  4) ;- (RSTC) User Reset Interrupt Enable
+AT91C_RSTC_ERSTL          EQU (0xF <<  8) ;- (RSTC) User Reset Enable
+AT91C_RSTC_BODIEN         EQU (0x1 << 16) ;- (RSTC) Brownout Detection Interrupt Enable
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
+// - *****************************************************************************
+// - -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 
+AT91C_RTTC_RTPRES         EQU (0xFFFF <<  0) ;- (RTTC) Real-time Timer Prescaler Value
+AT91C_RTTC_ALMIEN         EQU (0x1 << 16) ;- (RTTC) Alarm Interrupt Enable
+AT91C_RTTC_RTTINCIEN      EQU (0x1 << 17) ;- (RTTC) Real Time Timer Increment Interrupt Enable
+AT91C_RTTC_RTTRST         EQU (0x1 << 18) ;- (RTTC) Real Time Timer Restart
+// - -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 
+AT91C_RTTC_ALMV           EQU (0x0 <<  0) ;- (RTTC) Alarm Value
+// - -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 
+AT91C_RTTC_CRTV           EQU (0x0 <<  0) ;- (RTTC) Current Real-time Value
+// - -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 
+AT91C_RTTC_ALMS           EQU (0x1 <<  0) ;- (RTTC) Real-time Alarm Status
+AT91C_RTTC_RTTINC         EQU (0x1 <<  1) ;- (RTTC) Real-time Timer Increment
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
+// - *****************************************************************************
+// - -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
+AT91C_PITC_PIV            EQU (0xFFFFF <<  0) ;- (PITC) Periodic Interval Value
+AT91C_PITC_PITEN          EQU (0x1 << 24) ;- (PITC) Periodic Interval Timer Enabled
+AT91C_PITC_PITIEN         EQU (0x1 << 25) ;- (PITC) Periodic Interval Timer Interrupt Enable
+// - -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
+AT91C_PITC_PITS           EQU (0x1 <<  0) ;- (PITC) Periodic Interval Timer Status
+// - -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
+AT91C_PITC_CPIV           EQU (0xFFFFF <<  0) ;- (PITC) Current Periodic Interval Value
+AT91C_PITC_PICNT          EQU (0xFFF << 20) ;- (PITC) Periodic Interval Counter
+// - -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
+// - *****************************************************************************
+// - -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 
+AT91C_WDTC_WDRSTT         EQU (0x1 <<  0) ;- (WDTC) Watchdog Restart
+AT91C_WDTC_KEY            EQU (0xFF << 24) ;- (WDTC) Watchdog KEY Password
+// - -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 
+AT91C_WDTC_WDV            EQU (0xFFF <<  0) ;- (WDTC) Watchdog Timer Restart
+AT91C_WDTC_WDFIEN         EQU (0x1 << 12) ;- (WDTC) Watchdog Fault Interrupt Enable
+AT91C_WDTC_WDRSTEN        EQU (0x1 << 13) ;- (WDTC) Watchdog Reset Enable
+AT91C_WDTC_WDRPROC        EQU (0x1 << 14) ;- (WDTC) Watchdog Timer Restart
+AT91C_WDTC_WDDIS          EQU (0x1 << 15) ;- (WDTC) Watchdog Disable
+AT91C_WDTC_WDD            EQU (0xFFF << 16) ;- (WDTC) Watchdog Delta Value
+AT91C_WDTC_WDDBGHLT       EQU (0x1 << 28) ;- (WDTC) Watchdog Debug Halt
+AT91C_WDTC_WDIDLEHLT      EQU (0x1 << 29) ;- (WDTC) Watchdog Idle Halt
+// - -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 
+AT91C_WDTC_WDUNF          EQU (0x1 <<  0) ;- (WDTC) Watchdog Underflow
+AT91C_WDTC_WDERR          EQU (0x1 <<  1) ;- (WDTC) Watchdog Error
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface
+// - *****************************************************************************
+// - -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- 
+AT91C_VREG_PSTDBY         EQU (0x1 <<  0) ;- (VREG) Voltage Regulator Power Standby Mode
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Memory Controller Interface
+// - *****************************************************************************
+// - -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 
+AT91C_MC_RCB              EQU (0x1 <<  0) ;- (MC) Remap Command Bit
+// - -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 
+AT91C_MC_UNDADD           EQU (0x1 <<  0) ;- (MC) Undefined Addess Abort Status
+AT91C_MC_MISADD           EQU (0x1 <<  1) ;- (MC) Misaligned Addess Abort Status
+AT91C_MC_ABTSZ            EQU (0x3 <<  8) ;- (MC) Abort Size Status
+AT91C_MC_ABTSZ_BYTE       EQU (0x0 <<  8) ;- (MC) Byte
+AT91C_MC_ABTSZ_HWORD      EQU (0x1 <<  8) ;- (MC) Half-word
+AT91C_MC_ABTSZ_WORD       EQU (0x2 <<  8) ;- (MC) Word
+AT91C_MC_ABTTYP           EQU (0x3 << 10) ;- (MC) Abort Type Status
+AT91C_MC_ABTTYP_DATAR     EQU (0x0 << 10) ;- (MC) Data Read
+AT91C_MC_ABTTYP_DATAW     EQU (0x1 << 10) ;- (MC) Data Write
+AT91C_MC_ABTTYP_FETCH     EQU (0x2 << 10) ;- (MC) Code Fetch
+AT91C_MC_MST0             EQU (0x1 << 16) ;- (MC) Master 0 Abort Source
+AT91C_MC_MST1             EQU (0x1 << 17) ;- (MC) Master 1 Abort Source
+AT91C_MC_SVMST0           EQU (0x1 << 24) ;- (MC) Saved Master 0 Abort Source
+AT91C_MC_SVMST1           EQU (0x1 << 25) ;- (MC) Saved Master 1 Abort Source
+// - -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- 
+AT91C_MC_FRDY             EQU (0x1 <<  0) ;- (MC) Flash Ready
+AT91C_MC_LOCKE            EQU (0x1 <<  2) ;- (MC) Lock Error
+AT91C_MC_PROGE            EQU (0x1 <<  3) ;- (MC) Programming Error
+AT91C_MC_NEBP             EQU (0x1 <<  7) ;- (MC) No Erase Before Programming
+AT91C_MC_FWS              EQU (0x3 <<  8) ;- (MC) Flash Wait State
+AT91C_MC_FWS_0FWS         EQU (0x0 <<  8) ;- (MC) 1 cycle for Read, 2 for Write operations
+AT91C_MC_FWS_1FWS         EQU (0x1 <<  8) ;- (MC) 2 cycles for Read, 3 for Write operations
+AT91C_MC_FWS_2FWS         EQU (0x2 <<  8) ;- (MC) 3 cycles for Read, 4 for Write operations
+AT91C_MC_FWS_3FWS         EQU (0x3 <<  8) ;- (MC) 4 cycles for Read, 4 for Write operations
+AT91C_MC_FMCN             EQU (0xFF << 16) ;- (MC) Flash Microsecond Cycle Number
+// - -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- 
+AT91C_MC_FCMD             EQU (0xF <<  0) ;- (MC) Flash Command
+AT91C_MC_FCMD_START_PROG  EQU (0x1) ;- (MC) Starts the programming of th epage specified by PAGEN.
+AT91C_MC_FCMD_LOCK        EQU (0x2) ;- (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+AT91C_MC_FCMD_PROG_AND_LOCK EQU (0x3) ;- (MC) The lock sequence automatically happens after the programming sequence is completed.
+AT91C_MC_FCMD_UNLOCK      EQU (0x4) ;- (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+AT91C_MC_FCMD_ERASE_ALL   EQU (0x8) ;- (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
+AT91C_MC_FCMD_SET_GP_NVM  EQU (0xB) ;- (MC) Set General Purpose NVM bits.
+AT91C_MC_FCMD_CLR_GP_NVM  EQU (0xD) ;- (MC) Clear General Purpose NVM bits.
+AT91C_MC_FCMD_SET_SECURITY EQU (0xF) ;- (MC) Set Security Bit.
+AT91C_MC_PAGEN            EQU (0x3FF <<  8) ;- (MC) Page Number
+AT91C_MC_KEY              EQU (0xFF << 24) ;- (MC) Writing Protect Key
+// - -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- 
+AT91C_MC_SECURITY         EQU (0x1 <<  4) ;- (MC) Security Bit Status
+AT91C_MC_GPNVM0           EQU (0x1 <<  8) ;- (MC) Sector 0 Lock Status
+AT91C_MC_GPNVM1           EQU (0x1 <<  9) ;- (MC) Sector 1 Lock Status
+AT91C_MC_GPNVM2           EQU (0x1 << 10) ;- (MC) Sector 2 Lock Status
+AT91C_MC_GPNVM3           EQU (0x1 << 11) ;- (MC) Sector 3 Lock Status
+AT91C_MC_GPNVM4           EQU (0x1 << 12) ;- (MC) Sector 4 Lock Status
+AT91C_MC_GPNVM5           EQU (0x1 << 13) ;- (MC) Sector 5 Lock Status
+AT91C_MC_GPNVM6           EQU (0x1 << 14) ;- (MC) Sector 6 Lock Status
+AT91C_MC_GPNVM7           EQU (0x1 << 15) ;- (MC) Sector 7 Lock Status
+AT91C_MC_LOCKS0           EQU (0x1 << 16) ;- (MC) Sector 0 Lock Status
+AT91C_MC_LOCKS1           EQU (0x1 << 17) ;- (MC) Sector 1 Lock Status
+AT91C_MC_LOCKS2           EQU (0x1 << 18) ;- (MC) Sector 2 Lock Status
+AT91C_MC_LOCKS3           EQU (0x1 << 19) ;- (MC) Sector 3 Lock Status
+AT91C_MC_LOCKS4           EQU (0x1 << 20) ;- (MC) Sector 4 Lock Status
+AT91C_MC_LOCKS5           EQU (0x1 << 21) ;- (MC) Sector 5 Lock Status
+AT91C_MC_LOCKS6           EQU (0x1 << 22) ;- (MC) Sector 6 Lock Status
+AT91C_MC_LOCKS7           EQU (0x1 << 23) ;- (MC) Sector 7 Lock Status
+AT91C_MC_LOCKS8           EQU (0x1 << 24) ;- (MC) Sector 8 Lock Status
+AT91C_MC_LOCKS9           EQU (0x1 << 25) ;- (MC) Sector 9 Lock Status
+AT91C_MC_LOCKS10          EQU (0x1 << 26) ;- (MC) Sector 10 Lock Status
+AT91C_MC_LOCKS11          EQU (0x1 << 27) ;- (MC) Sector 11 Lock Status
+AT91C_MC_LOCKS12          EQU (0x1 << 28) ;- (MC) Sector 12 Lock Status
+AT91C_MC_LOCKS13          EQU (0x1 << 29) ;- (MC) Sector 13 Lock Status
+AT91C_MC_LOCKS14          EQU (0x1 << 30) ;- (MC) Sector 14 Lock Status
+AT91C_MC_LOCKS15          EQU (0x1 << 31) ;- (MC) Sector 15 Lock Status
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
+// - *****************************************************************************
+// - -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
+AT91C_SPI_SPIEN           EQU (0x1 <<  0) ;- (SPI) SPI Enable
+AT91C_SPI_SPIDIS          EQU (0x1 <<  1) ;- (SPI) SPI Disable
+AT91C_SPI_SWRST           EQU (0x1 <<  7) ;- (SPI) SPI Software reset
+AT91C_SPI_LASTXFER        EQU (0x1 << 24) ;- (SPI) SPI Last Transfer
+// - -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
+AT91C_SPI_MSTR            EQU (0x1 <<  0) ;- (SPI) Master/Slave Mode
+AT91C_SPI_PS              EQU (0x1 <<  1) ;- (SPI) Peripheral Select
+AT91C_SPI_PS_FIXED        EQU (0x0 <<  1) ;- (SPI) Fixed Peripheral Select
+AT91C_SPI_PS_VARIABLE     EQU (0x1 <<  1) ;- (SPI) Variable Peripheral Select
+AT91C_SPI_PCSDEC          EQU (0x1 <<  2) ;- (SPI) Chip Select Decode
+AT91C_SPI_FDIV            EQU (0x1 <<  3) ;- (SPI) Clock Selection
+AT91C_SPI_MODFDIS         EQU (0x1 <<  4) ;- (SPI) Mode Fault Detection
+AT91C_SPI_LLB             EQU (0x1 <<  7) ;- (SPI) Clock Selection
+AT91C_SPI_PCS             EQU (0xF << 16) ;- (SPI) Peripheral Chip Select
+AT91C_SPI_DLYBCS          EQU (0xFF << 24) ;- (SPI) Delay Between Chip Selects
+// - -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
+AT91C_SPI_RD              EQU (0xFFFF <<  0) ;- (SPI) Receive Data
+AT91C_SPI_RPCS            EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status
+// - -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
+AT91C_SPI_TD              EQU (0xFFFF <<  0) ;- (SPI) Transmit Data
+AT91C_SPI_TPCS            EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status
+// - -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
+AT91C_SPI_RDRF            EQU (0x1 <<  0) ;- (SPI) Receive Data Register Full
+AT91C_SPI_TDRE            EQU (0x1 <<  1) ;- (SPI) Transmit Data Register Empty
+AT91C_SPI_MODF            EQU (0x1 <<  2) ;- (SPI) Mode Fault Error
+AT91C_SPI_OVRES           EQU (0x1 <<  3) ;- (SPI) Overrun Error Status
+AT91C_SPI_ENDRX           EQU (0x1 <<  4) ;- (SPI) End of Receiver Transfer
+AT91C_SPI_ENDTX           EQU (0x1 <<  5) ;- (SPI) End of Receiver Transfer
+AT91C_SPI_RXBUFF          EQU (0x1 <<  6) ;- (SPI) RXBUFF Interrupt
+AT91C_SPI_TXBUFE          EQU (0x1 <<  7) ;- (SPI) TXBUFE Interrupt
+AT91C_SPI_NSSR            EQU (0x1 <<  8) ;- (SPI) NSSR Interrupt
+AT91C_SPI_TXEMPTY         EQU (0x1 <<  9) ;- (SPI) TXEMPTY Interrupt
+AT91C_SPI_SPIENS          EQU (0x1 << 16) ;- (SPI) Enable Status
+// - -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
+// - -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
+// - -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
+// - -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
+AT91C_SPI_CPOL            EQU (0x1 <<  0) ;- (SPI) Clock Polarity
+AT91C_SPI_NCPHA           EQU (0x1 <<  1) ;- (SPI) Clock Phase
+AT91C_SPI_CSAAT           EQU (0x1 <<  3) ;- (SPI) Chip Select Active After Transfer
+AT91C_SPI_BITS            EQU (0xF <<  4) ;- (SPI) Bits Per Transfer
+AT91C_SPI_BITS_8          EQU (0x0 <<  4) ;- (SPI) 8 Bits Per transfer
+AT91C_SPI_BITS_9          EQU (0x1 <<  4) ;- (SPI) 9 Bits Per transfer
+AT91C_SPI_BITS_10         EQU (0x2 <<  4) ;- (SPI) 10 Bits Per transfer
+AT91C_SPI_BITS_11         EQU (0x3 <<  4) ;- (SPI) 11 Bits Per transfer
+AT91C_SPI_BITS_12         EQU (0x4 <<  4) ;- (SPI) 12 Bits Per transfer
+AT91C_SPI_BITS_13         EQU (0x5 <<  4) ;- (SPI) 13 Bits Per transfer
+AT91C_SPI_BITS_14         EQU (0x6 <<  4) ;- (SPI) 14 Bits Per transfer
+AT91C_SPI_BITS_15         EQU (0x7 <<  4) ;- (SPI) 15 Bits Per transfer
+AT91C_SPI_BITS_16         EQU (0x8 <<  4) ;- (SPI) 16 Bits Per transfer
+AT91C_SPI_SCBR            EQU (0xFF <<  8) ;- (SPI) Serial Clock Baud Rate
+AT91C_SPI_DLYBS           EQU (0xFF << 16) ;- (SPI) Delay Before SPCK
+AT91C_SPI_DLYBCT          EQU (0xFF << 24) ;- (SPI) Delay Between Consecutive Transfers
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Usart
+// - *****************************************************************************
+// - -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
+AT91C_US_STTBRK           EQU (0x1 <<  9) ;- (USART) Start Break
+AT91C_US_STPBRK           EQU (0x1 << 10) ;- (USART) Stop Break
+AT91C_US_STTTO            EQU (0x1 << 11) ;- (USART) Start Time-out
+AT91C_US_SENDA            EQU (0x1 << 12) ;- (USART) Send Address
+AT91C_US_RSTIT            EQU (0x1 << 13) ;- (USART) Reset Iterations
+AT91C_US_RSTNACK          EQU (0x1 << 14) ;- (USART) Reset Non Acknowledge
+AT91C_US_RETTO            EQU (0x1 << 15) ;- (USART) Rearm Time-out
+AT91C_US_DTREN            EQU (0x1 << 16) ;- (USART) Data Terminal ready Enable
+AT91C_US_DTRDIS           EQU (0x1 << 17) ;- (USART) Data Terminal ready Disable
+AT91C_US_RTSEN            EQU (0x1 << 18) ;- (USART) Request to Send enable
+AT91C_US_RTSDIS           EQU (0x1 << 19) ;- (USART) Request to Send Disable
+// - -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
+AT91C_US_USMODE           EQU (0xF <<  0) ;- (USART) Usart mode
+AT91C_US_USMODE_NORMAL    EQU (0x0) ;- (USART) Normal
+AT91C_US_USMODE_RS485     EQU (0x1) ;- (USART) RS485
+AT91C_US_USMODE_HWHSH     EQU (0x2) ;- (USART) Hardware Handshaking
+AT91C_US_USMODE_MODEM     EQU (0x3) ;- (USART) Modem
+AT91C_US_USMODE_ISO7816_0 EQU (0x4) ;- (USART) ISO7816 protocol: T = 0
+AT91C_US_USMODE_ISO7816_1 EQU (0x6) ;- (USART) ISO7816 protocol: T = 1
+AT91C_US_USMODE_IRDA      EQU (0x8) ;- (USART) IrDA
+AT91C_US_USMODE_SWHSH     EQU (0xC) ;- (USART) Software Handshaking
+AT91C_US_CLKS             EQU (0x3 <<  4) ;- (USART) Clock Selection (Baud Rate generator Input Clock
+AT91C_US_CLKS_CLOCK       EQU (0x0 <<  4) ;- (USART) Clock
+AT91C_US_CLKS_FDIV1       EQU (0x1 <<  4) ;- (USART) fdiv1
+AT91C_US_CLKS_SLOW        EQU (0x2 <<  4) ;- (USART) slow_clock (ARM)
+AT91C_US_CLKS_EXT         EQU (0x3 <<  4) ;- (USART) External (SCK)
+AT91C_US_CHRL             EQU (0x3 <<  6) ;- (USART) Clock Selection (Baud Rate generator Input Clock
+AT91C_US_CHRL_5_BITS      EQU (0x0 <<  6) ;- (USART) Character Length: 5 bits
+AT91C_US_CHRL_6_BITS      EQU (0x1 <<  6) ;- (USART) Character Length: 6 bits
+AT91C_US_CHRL_7_BITS      EQU (0x2 <<  6) ;- (USART) Character Length: 7 bits
+AT91C_US_CHRL_8_BITS      EQU (0x3 <<  6) ;- (USART) Character Length: 8 bits
+AT91C_US_SYNC             EQU (0x1 <<  8) ;- (USART) Synchronous Mode Select
+AT91C_US_NBSTOP           EQU (0x3 << 12) ;- (USART) Number of Stop bits
+AT91C_US_NBSTOP_1_BIT     EQU (0x0 << 12) ;- (USART) 1 stop bit
+AT91C_US_NBSTOP_15_BIT    EQU (0x1 << 12) ;- (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+AT91C_US_NBSTOP_2_BIT     EQU (0x2 << 12) ;- (USART) 2 stop bits
+AT91C_US_MSBF             EQU (0x1 << 16) ;- (USART) Bit Order
+AT91C_US_MODE9            EQU (0x1 << 17) ;- (USART) 9-bit Character length
+AT91C_US_CKLO             EQU (0x1 << 18) ;- (USART) Clock Output Select
+AT91C_US_OVER             EQU (0x1 << 19) ;- (USART) Over Sampling Mode
+AT91C_US_INACK            EQU (0x1 << 20) ;- (USART) Inhibit Non Acknowledge
+AT91C_US_DSNACK           EQU (0x1 << 21) ;- (USART) Disable Successive NACK
+AT91C_US_MAX_ITER         EQU (0x1 << 24) ;- (USART) Number of Repetitions
+AT91C_US_FILTER           EQU (0x1 << 28) ;- (USART) Receive Line Filter
+// - -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+AT91C_US_RXBRK            EQU (0x1 <<  2) ;- (USART) Break Received/End of Break
+AT91C_US_TIMEOUT          EQU (0x1 <<  8) ;- (USART) Receiver Time-out
+AT91C_US_ITERATION        EQU (0x1 << 10) ;- (USART) Max number of Repetitions Reached
+AT91C_US_NACK             EQU (0x1 << 13) ;- (USART) Non Acknowledge
+AT91C_US_RIIC             EQU (0x1 << 16) ;- (USART) Ring INdicator Input Change Flag
+AT91C_US_DSRIC            EQU (0x1 << 17) ;- (USART) Data Set Ready Input Change Flag
+AT91C_US_DCDIC            EQU (0x1 << 18) ;- (USART) Data Carrier Flag
+AT91C_US_CTSIC            EQU (0x1 << 19) ;- (USART) Clear To Send Input Change Flag
+// - -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// - -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// - -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 
+AT91C_US_RI               EQU (0x1 << 20) ;- (USART) Image of RI Input
+AT91C_US_DSR              EQU (0x1 << 21) ;- (USART) Image of DSR Input
+AT91C_US_DCD              EQU (0x1 << 22) ;- (USART) Image of DCD Input
+AT91C_US_CTS              EQU (0x1 << 23) ;- (USART) Image of CTS Input
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
+// - *****************************************************************************
+// - -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
+AT91C_SSC_RXEN            EQU (0x1 <<  0) ;- (SSC) Receive Enable
+AT91C_SSC_RXDIS           EQU (0x1 <<  1) ;- (SSC) Receive Disable
+AT91C_SSC_TXEN            EQU (0x1 <<  8) ;- (SSC) Transmit Enable
+AT91C_SSC_TXDIS           EQU (0x1 <<  9) ;- (SSC) Transmit Disable
+AT91C_SSC_SWRST           EQU (0x1 << 15) ;- (SSC) Software Reset
+// - -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
+AT91C_SSC_CKS             EQU (0x3 <<  0) ;- (SSC) Receive/Transmit Clock Selection
+AT91C_SSC_CKS_DIV         EQU (0x0) ;- (SSC) Divided Clock
+AT91C_SSC_CKS_TK          EQU (0x1) ;- (SSC) TK Clock signal
+AT91C_SSC_CKS_RK          EQU (0x2) ;- (SSC) RK pin
+AT91C_SSC_CKO             EQU (0x7 <<  2) ;- (SSC) Receive/Transmit Clock Output Mode Selection
+AT91C_SSC_CKO_NONE        EQU (0x0 <<  2) ;- (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+AT91C_SSC_CKO_CONTINOUS   EQU (0x1 <<  2) ;- (SSC) Continuous Receive/Transmit Clock RK pin: Output
+AT91C_SSC_CKO_DATA_TX     EQU (0x2 <<  2) ;- (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+AT91C_SSC_CKI             EQU (0x1 <<  5) ;- (SSC) Receive/Transmit Clock Inversion
+AT91C_SSC_START           EQU (0xF <<  8) ;- (SSC) Receive/Transmit Start Selection
+AT91C_SSC_START_CONTINOUS EQU (0x0 <<  8) ;- (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+AT91C_SSC_START_TX        EQU (0x1 <<  8) ;- (SSC) Transmit/Receive start
+AT91C_SSC_START_LOW_RF    EQU (0x2 <<  8) ;- (SSC) Detection of a low level on RF input
+AT91C_SSC_START_HIGH_RF   EQU (0x3 <<  8) ;- (SSC) Detection of a high level on RF input
+AT91C_SSC_START_FALL_RF   EQU (0x4 <<  8) ;- (SSC) Detection of a falling edge on RF input
+AT91C_SSC_START_RISE_RF   EQU (0x5 <<  8) ;- (SSC) Detection of a rising edge on RF input
+AT91C_SSC_START_LEVEL_RF  EQU (0x6 <<  8) ;- (SSC) Detection of any level change on RF input
+AT91C_SSC_START_EDGE_RF   EQU (0x7 <<  8) ;- (SSC) Detection of any edge on RF input
+AT91C_SSC_START_0         EQU (0x8 <<  8) ;- (SSC) Compare 0
+AT91C_SSC_STTDLY          EQU (0xFF << 16) ;- (SSC) Receive/Transmit Start Delay
+AT91C_SSC_PERIOD          EQU (0xFF << 24) ;- (SSC) Receive/Transmit Period Divider Selection
+// - -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
+AT91C_SSC_DATLEN          EQU (0x1F <<  0) ;- (SSC) Data Length
+AT91C_SSC_LOOP            EQU (0x1 <<  5) ;- (SSC) Loop Mode
+AT91C_SSC_MSBF            EQU (0x1 <<  7) ;- (SSC) Most Significant Bit First
+AT91C_SSC_DATNB           EQU (0xF <<  8) ;- (SSC) Data Number per Frame
+AT91C_SSC_FSLEN           EQU (0xF << 16) ;- (SSC) Receive/Transmit Frame Sync length
+AT91C_SSC_FSOS            EQU (0x7 << 20) ;- (SSC) Receive/Transmit Frame Sync Output Selection
+AT91C_SSC_FSOS_NONE       EQU (0x0 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+AT91C_SSC_FSOS_NEGATIVE   EQU (0x1 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+AT91C_SSC_FSOS_POSITIVE   EQU (0x2 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+AT91C_SSC_FSOS_LOW        EQU (0x3 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+AT91C_SSC_FSOS_HIGH       EQU (0x4 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+AT91C_SSC_FSOS_TOGGLE     EQU (0x5 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+AT91C_SSC_FSEDGE          EQU (0x1 << 24) ;- (SSC) Frame Sync Edge Detection
+// - -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
+// - -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
+AT91C_SSC_DATDEF          EQU (0x1 <<  5) ;- (SSC) Data Default Value
+AT91C_SSC_FSDEN           EQU (0x1 << 23) ;- (SSC) Frame Sync Data Enable
+// - -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
+AT91C_SSC_TXRDY           EQU (0x1 <<  0) ;- (SSC) Transmit Ready
+AT91C_SSC_TXEMPTY         EQU (0x1 <<  1) ;- (SSC) Transmit Empty
+AT91C_SSC_ENDTX           EQU (0x1 <<  2) ;- (SSC) End Of Transmission
+AT91C_SSC_TXBUFE          EQU (0x1 <<  3) ;- (SSC) Transmit Buffer Empty
+AT91C_SSC_RXRDY           EQU (0x1 <<  4) ;- (SSC) Receive Ready
+AT91C_SSC_OVRUN           EQU (0x1 <<  5) ;- (SSC) Receive Overrun
+AT91C_SSC_ENDRX           EQU (0x1 <<  6) ;- (SSC) End of Reception
+AT91C_SSC_RXBUFF          EQU (0x1 <<  7) ;- (SSC) Receive Buffer Full
+AT91C_SSC_TXSYN           EQU (0x1 << 10) ;- (SSC) Transmit Sync
+AT91C_SSC_RXSYN           EQU (0x1 << 11) ;- (SSC) Receive Sync
+AT91C_SSC_TXENA           EQU (0x1 << 16) ;- (SSC) Transmit Enable
+AT91C_SSC_RXENA           EQU (0x1 << 17) ;- (SSC) Receive Enable
+// - -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
+// - -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
+// - -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Two-wire Interface
+// - *****************************************************************************
+// - -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
+AT91C_TWI_START           EQU (0x1 <<  0) ;- (TWI) Send a START Condition
+AT91C_TWI_STOP            EQU (0x1 <<  1) ;- (TWI) Send a STOP Condition
+AT91C_TWI_MSEN            EQU (0x1 <<  2) ;- (TWI) TWI Master Transfer Enabled
+AT91C_TWI_MSDIS           EQU (0x1 <<  3) ;- (TWI) TWI Master Transfer Disabled
+AT91C_TWI_SWRST           EQU (0x1 <<  7) ;- (TWI) Software Reset
+// - -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
+AT91C_TWI_IADRSZ          EQU (0x3 <<  8) ;- (TWI) Internal Device Address Size
+AT91C_TWI_IADRSZ_NO       EQU (0x0 <<  8) ;- (TWI) No internal device address
+AT91C_TWI_IADRSZ_1_BYTE   EQU (0x1 <<  8) ;- (TWI) One-byte internal device address
+AT91C_TWI_IADRSZ_2_BYTE   EQU (0x2 <<  8) ;- (TWI) Two-byte internal device address
+AT91C_TWI_IADRSZ_3_BYTE   EQU (0x3 <<  8) ;- (TWI) Three-byte internal device address
+AT91C_TWI_MREAD           EQU (0x1 << 12) ;- (TWI) Master Read Direction
+AT91C_TWI_DADR            EQU (0x7F << 16) ;- (TWI) Device Address
+// - -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
+AT91C_TWI_CLDIV           EQU (0xFF <<  0) ;- (TWI) Clock Low Divider
+AT91C_TWI_CHDIV           EQU (0xFF <<  8) ;- (TWI) Clock High Divider
+AT91C_TWI_CKDIV           EQU (0x7 << 16) ;- (TWI) Clock Divider
+// - -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
+AT91C_TWI_TXCOMP          EQU (0x1 <<  0) ;- (TWI) Transmission Completed
+AT91C_TWI_RXRDY           EQU (0x1 <<  1) ;- (TWI) Receive holding register ReaDY
+AT91C_TWI_TXRDY           EQU (0x1 <<  2) ;- (TWI) Transmit holding register ReaDY
+AT91C_TWI_OVRE            EQU (0x1 <<  6) ;- (TWI) Overrun Error
+AT91C_TWI_UNRE            EQU (0x1 <<  7) ;- (TWI) Underrun Error
+AT91C_TWI_NACK            EQU (0x1 <<  8) ;- (TWI) Not Acknowledged
+// - -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
+// - -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
+// - -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
+// - *****************************************************************************
+// - -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- 
+AT91C_PWMC_CPRE           EQU (0xF <<  0) ;- (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
+AT91C_PWMC_CPRE_MCK       EQU (0x0) ;- (PWMC_CH) 
+AT91C_PWMC_CPRE_MCKA      EQU (0xB) ;- (PWMC_CH) 
+AT91C_PWMC_CPRE_MCKB      EQU (0xC) ;- (PWMC_CH) 
+AT91C_PWMC_CALG           EQU (0x1 <<  8) ;- (PWMC_CH) Channel Alignment
+AT91C_PWMC_CPOL           EQU (0x1 <<  9) ;- (PWMC_CH) Channel Polarity
+AT91C_PWMC_CPD            EQU (0x1 << 10) ;- (PWMC_CH) Channel Update Period
+// - -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- 
+AT91C_PWMC_CDTY           EQU (0x0 <<  0) ;- (PWMC_CH) Channel Duty Cycle
+// - -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- 
+AT91C_PWMC_CPRD           EQU (0x0 <<  0) ;- (PWMC_CH) Channel Period
+// - -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- 
+AT91C_PWMC_CCNT           EQU (0x0 <<  0) ;- (PWMC_CH) Channel Counter
+// - -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- 
+AT91C_PWMC_CUPD           EQU (0x0 <<  0) ;- (PWMC_CH) Channel Update
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
+// - *****************************************************************************
+// - -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- 
+AT91C_PWMC_DIVA           EQU (0xFF <<  0) ;- (PWMC) CLKA divide factor.
+AT91C_PWMC_PREA           EQU (0xF <<  8) ;- (PWMC) Divider Input Clock Prescaler A
+AT91C_PWMC_PREA_MCK       EQU (0x0 <<  8) ;- (PWMC) 
+AT91C_PWMC_DIVB           EQU (0xFF << 16) ;- (PWMC) CLKB divide factor.
+AT91C_PWMC_PREB           EQU (0xF << 24) ;- (PWMC) Divider Input Clock Prescaler B
+AT91C_PWMC_PREB_MCK       EQU (0x0 << 24) ;- (PWMC) 
+// - -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- 
+AT91C_PWMC_CHID0          EQU (0x1 <<  0) ;- (PWMC) Channel ID 0
+AT91C_PWMC_CHID1          EQU (0x1 <<  1) ;- (PWMC) Channel ID 1
+AT91C_PWMC_CHID2          EQU (0x1 <<  2) ;- (PWMC) Channel ID 2
+AT91C_PWMC_CHID3          EQU (0x1 <<  3) ;- (PWMC) Channel ID 3
+// - -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- 
+// - -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- 
+// - -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- 
+// - -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- 
+// - -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- 
+// - -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR USB Device Interface
+// - *****************************************************************************
+// - -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
+AT91C_UDP_FRM_NUM         EQU (0x7FF <<  0) ;- (UDP) Frame Number as Defined in the Packet Field Formats
+AT91C_UDP_FRM_ERR         EQU (0x1 << 16) ;- (UDP) Frame Error
+AT91C_UDP_FRM_OK          EQU (0x1 << 17) ;- (UDP) Frame OK
+// - -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
+AT91C_UDP_FADDEN          EQU (0x1 <<  0) ;- (UDP) Function Address Enable
+AT91C_UDP_CONFG           EQU (0x1 <<  1) ;- (UDP) Configured
+AT91C_UDP_ESR             EQU (0x1 <<  2) ;- (UDP) Enable Send Resume
+AT91C_UDP_RSMINPR         EQU (0x1 <<  3) ;- (UDP) A Resume Has Been Sent to the Host
+AT91C_UDP_RMWUPE          EQU (0x1 <<  4) ;- (UDP) Remote Wake Up Enable
+// - -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
+AT91C_UDP_FADD            EQU (0xFF <<  0) ;- (UDP) Function Address Value
+AT91C_UDP_FEN             EQU (0x1 <<  8) ;- (UDP) Function Enable
+// - -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 
+AT91C_UDP_EPINT0          EQU (0x1 <<  0) ;- (UDP) Endpoint 0 Interrupt
+AT91C_UDP_EPINT1          EQU (0x1 <<  1) ;- (UDP) Endpoint 0 Interrupt
+AT91C_UDP_EPINT2          EQU (0x1 <<  2) ;- (UDP) Endpoint 2 Interrupt
+AT91C_UDP_EPINT3          EQU (0x1 <<  3) ;- (UDP) Endpoint 3 Interrupt
+AT91C_UDP_EPINT4          EQU (0x1 <<  4) ;- (UDP) Endpoint 4 Interrupt
+AT91C_UDP_EPINT5          EQU (0x1 <<  5) ;- (UDP) Endpoint 5 Interrupt
+AT91C_UDP_RXSUSP          EQU (0x1 <<  8) ;- (UDP) USB Suspend Interrupt
+AT91C_UDP_RXRSM           EQU (0x1 <<  9) ;- (UDP) USB Resume Interrupt
+AT91C_UDP_EXTRSM          EQU (0x1 << 10) ;- (UDP) USB External Resume Interrupt
+AT91C_UDP_SOFINT          EQU (0x1 << 11) ;- (UDP) USB Start Of frame Interrupt
+AT91C_UDP_WAKEUP          EQU (0x1 << 13) ;- (UDP) USB Resume Interrupt
+// - -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 
+// - -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 
+// - -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 
+AT91C_UDP_ENDBUSRES       EQU (0x1 << 12) ;- (UDP) USB End Of Bus Reset Interrupt
+// - -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 
+// - -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 
+AT91C_UDP_EP0             EQU (0x1 <<  0) ;- (UDP) Reset Endpoint 0
+AT91C_UDP_EP1             EQU (0x1 <<  1) ;- (UDP) Reset Endpoint 1
+AT91C_UDP_EP2             EQU (0x1 <<  2) ;- (UDP) Reset Endpoint 2
+AT91C_UDP_EP3             EQU (0x1 <<  3) ;- (UDP) Reset Endpoint 3
+AT91C_UDP_EP4             EQU (0x1 <<  4) ;- (UDP) Reset Endpoint 4
+AT91C_UDP_EP5             EQU (0x1 <<  5) ;- (UDP) Reset Endpoint 5
+// - -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 
+AT91C_UDP_TXCOMP          EQU (0x1 <<  0) ;- (UDP) Generates an IN packet with data previously written in the DPR
+AT91C_UDP_RX_DATA_BK0     EQU (0x1 <<  1) ;- (UDP) Receive Data Bank 0
+AT91C_UDP_RXSETUP         EQU (0x1 <<  2) ;- (UDP) Sends STALL to the Host (Control endpoints)
+AT91C_UDP_ISOERROR        EQU (0x1 <<  3) ;- (UDP) Isochronous error (Isochronous endpoints)
+AT91C_UDP_TXPKTRDY        EQU (0x1 <<  4) ;- (UDP) Transmit Packet Ready
+AT91C_UDP_FORCESTALL      EQU (0x1 <<  5) ;- (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
+AT91C_UDP_RX_DATA_BK1     EQU (0x1 <<  6) ;- (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
+AT91C_UDP_DIR             EQU (0x1 <<  7) ;- (UDP) Transfer Direction
+AT91C_UDP_EPTYPE          EQU (0x7 <<  8) ;- (UDP) Endpoint type
+AT91C_UDP_EPTYPE_CTRL     EQU (0x0 <<  8) ;- (UDP) Control
+AT91C_UDP_EPTYPE_ISO_OUT  EQU (0x1 <<  8) ;- (UDP) Isochronous OUT
+AT91C_UDP_EPTYPE_BULK_OUT EQU (0x2 <<  8) ;- (UDP) Bulk OUT
+AT91C_UDP_EPTYPE_INT_OUT  EQU (0x3 <<  8) ;- (UDP) Interrupt OUT
+AT91C_UDP_EPTYPE_ISO_IN   EQU (0x5 <<  8) ;- (UDP) Isochronous IN
+AT91C_UDP_EPTYPE_BULK_IN  EQU (0x6 <<  8) ;- (UDP) Bulk IN
+AT91C_UDP_EPTYPE_INT_IN   EQU (0x7 <<  8) ;- (UDP) Interrupt IN
+AT91C_UDP_DTGLE           EQU (0x1 << 11) ;- (UDP) Data Toggle
+AT91C_UDP_EPEDS           EQU (0x1 << 15) ;- (UDP) Endpoint Enable Disable
+AT91C_UDP_RXBYTECNT       EQU (0x7FF << 16) ;- (UDP) Number Of Bytes Available in the FIFO
+// - -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- 
+AT91C_UDP_TXVDIS          EQU (0x1 <<  8) ;- (UDP) 
+AT91C_UDP_PUON            EQU (0x1 <<  9) ;- (UDP) Pull-up ON
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
+// - *****************************************************************************
+// - -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
+AT91C_TC_CLKEN            EQU (0x1 <<  0) ;- (TC) Counter Clock Enable Command
+AT91C_TC_CLKDIS           EQU (0x1 <<  1) ;- (TC) Counter Clock Disable Command
+AT91C_TC_SWTRG            EQU (0x1 <<  2) ;- (TC) Software Trigger Command
+// - -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
+AT91C_TC_CLKS             EQU (0x7 <<  0) ;- (TC) Clock Selection
+AT91C_TC_CLKS_TIMER_DIV1_CLOCK EQU (0x0) ;- (TC) Clock selected: TIMER_DIV1_CLOCK
+AT91C_TC_CLKS_TIMER_DIV2_CLOCK EQU (0x1) ;- (TC) Clock selected: TIMER_DIV2_CLOCK
+AT91C_TC_CLKS_TIMER_DIV3_CLOCK EQU (0x2) ;- (TC) Clock selected: TIMER_DIV3_CLOCK
+AT91C_TC_CLKS_TIMER_DIV4_CLOCK EQU (0x3) ;- (TC) Clock selected: TIMER_DIV4_CLOCK
+AT91C_TC_CLKS_TIMER_DIV5_CLOCK EQU (0x4) ;- (TC) Clock selected: TIMER_DIV5_CLOCK
+AT91C_TC_CLKS_XC0         EQU (0x5) ;- (TC) Clock selected: XC0
+AT91C_TC_CLKS_XC1         EQU (0x6) ;- (TC) Clock selected: XC1
+AT91C_TC_CLKS_XC2         EQU (0x7) ;- (TC) Clock selected: XC2
+AT91C_TC_CLKI             EQU (0x1 <<  3) ;- (TC) Clock Invert
+AT91C_TC_BURST            EQU (0x3 <<  4) ;- (TC) Burst Signal Selection
+AT91C_TC_BURST_NONE       EQU (0x0 <<  4) ;- (TC) The clock is not gated by an external signal
+AT91C_TC_BURST_XC0        EQU (0x1 <<  4) ;- (TC) XC0 is ANDed with the selected clock
+AT91C_TC_BURST_XC1        EQU (0x2 <<  4) ;- (TC) XC1 is ANDed with the selected clock
+AT91C_TC_BURST_XC2        EQU (0x3 <<  4) ;- (TC) XC2 is ANDed with the selected clock
+AT91C_TC_CPCSTOP          EQU (0x1 <<  6) ;- (TC) Counter Clock Stopped with RC Compare
+AT91C_TC_LDBSTOP          EQU (0x1 <<  6) ;- (TC) Counter Clock Stopped with RB Loading
+AT91C_TC_CPCDIS           EQU (0x1 <<  7) ;- (TC) Counter Clock Disable with RC Compare
+AT91C_TC_LDBDIS           EQU (0x1 <<  7) ;- (TC) Counter Clock Disabled with RB Loading
+AT91C_TC_ETRGEDG          EQU (0x3 <<  8) ;- (TC) External Trigger Edge Selection
+AT91C_TC_ETRGEDG_NONE     EQU (0x0 <<  8) ;- (TC) Edge: None
+AT91C_TC_ETRGEDG_RISING   EQU (0x1 <<  8) ;- (TC) Edge: rising edge
+AT91C_TC_ETRGEDG_FALLING  EQU (0x2 <<  8) ;- (TC) Edge: falling edge
+AT91C_TC_ETRGEDG_BOTH     EQU (0x3 <<  8) ;- (TC) Edge: each edge
+AT91C_TC_EEVTEDG          EQU (0x3 <<  8) ;- (TC) External Event Edge Selection
+AT91C_TC_EEVTEDG_NONE     EQU (0x0 <<  8) ;- (TC) Edge: None
+AT91C_TC_EEVTEDG_RISING   EQU (0x1 <<  8) ;- (TC) Edge: rising edge
+AT91C_TC_EEVTEDG_FALLING  EQU (0x2 <<  8) ;- (TC) Edge: falling edge
+AT91C_TC_EEVTEDG_BOTH     EQU (0x3 <<  8) ;- (TC) Edge: each edge
+AT91C_TC_EEVT             EQU (0x3 << 10) ;- (TC) External Event  Selection
+AT91C_TC_EEVT_TIOB        EQU (0x0 << 10) ;- (TC) Signal selected as external event: TIOB TIOB direction: input
+AT91C_TC_EEVT_XC0         EQU (0x1 << 10) ;- (TC) Signal selected as external event: XC0 TIOB direction: output
+AT91C_TC_EEVT_XC1         EQU (0x2 << 10) ;- (TC) Signal selected as external event: XC1 TIOB direction: output
+AT91C_TC_EEVT_XC2         EQU (0x3 << 10) ;- (TC) Signal selected as external event: XC2 TIOB direction: output
+AT91C_TC_ABETRG           EQU (0x1 << 10) ;- (TC) TIOA or TIOB External Trigger Selection
+AT91C_TC_ENETRG           EQU (0x1 << 12) ;- (TC) External Event Trigger enable
+AT91C_TC_WAVESEL          EQU (0x3 << 13) ;- (TC) Waveform  Selection
+AT91C_TC_WAVESEL_UP       EQU (0x0 << 13) ;- (TC) UP mode without atomatic trigger on RC Compare
+AT91C_TC_WAVESEL_UPDOWN   EQU (0x1 << 13) ;- (TC) UPDOWN mode without automatic trigger on RC Compare
+AT91C_TC_WAVESEL_UP_AUTO  EQU (0x2 << 13) ;- (TC) UP mode with automatic trigger on RC Compare
+AT91C_TC_WAVESEL_UPDOWN_AUTO EQU (0x3 << 13) ;- (TC) UPDOWN mode with automatic trigger on RC Compare
+AT91C_TC_CPCTRG           EQU (0x1 << 14) ;- (TC) RC Compare Trigger Enable
+AT91C_TC_WAVE             EQU (0x1 << 15) ;- (TC) 
+AT91C_TC_ACPA             EQU (0x3 << 16) ;- (TC) RA Compare Effect on TIOA
+AT91C_TC_ACPA_NONE        EQU (0x0 << 16) ;- (TC) Effect: none
+AT91C_TC_ACPA_SET         EQU (0x1 << 16) ;- (TC) Effect: set
+AT91C_TC_ACPA_CLEAR       EQU (0x2 << 16) ;- (TC) Effect: clear
+AT91C_TC_ACPA_TOGGLE      EQU (0x3 << 16) ;- (TC) Effect: toggle
+AT91C_TC_LDRA             EQU (0x3 << 16) ;- (TC) RA Loading Selection
+AT91C_TC_LDRA_NONE        EQU (0x0 << 16) ;- (TC) Edge: None
+AT91C_TC_LDRA_RISING      EQU (0x1 << 16) ;- (TC) Edge: rising edge of TIOA
+AT91C_TC_LDRA_FALLING     EQU (0x2 << 16) ;- (TC) Edge: falling edge of TIOA
+AT91C_TC_LDRA_BOTH        EQU (0x3 << 16) ;- (TC) Edge: each edge of TIOA
+AT91C_TC_ACPC             EQU (0x3 << 18) ;- (TC) RC Compare Effect on TIOA
+AT91C_TC_ACPC_NONE        EQU (0x0 << 18) ;- (TC) Effect: none
+AT91C_TC_ACPC_SET         EQU (0x1 << 18) ;- (TC) Effect: set
+AT91C_TC_ACPC_CLEAR       EQU (0x2 << 18) ;- (TC) Effect: clear
+AT91C_TC_ACPC_TOGGLE      EQU (0x3 << 18) ;- (TC) Effect: toggle
+AT91C_TC_LDRB             EQU (0x3 << 18) ;- (TC) RB Loading Selection
+AT91C_TC_LDRB_NONE        EQU (0x0 << 18) ;- (TC) Edge: None
+AT91C_TC_LDRB_RISING      EQU (0x1 << 18) ;- (TC) Edge: rising edge of TIOA
+AT91C_TC_LDRB_FALLING     EQU (0x2 << 18) ;- (TC) Edge: falling edge of TIOA
+AT91C_TC_LDRB_BOTH        EQU (0x3 << 18) ;- (TC) Edge: each edge of TIOA
+AT91C_TC_AEEVT            EQU (0x3 << 20) ;- (TC) External Event Effect on TIOA
+AT91C_TC_AEEVT_NONE       EQU (0x0 << 20) ;- (TC) Effect: none
+AT91C_TC_AEEVT_SET        EQU (0x1 << 20) ;- (TC) Effect: set
+AT91C_TC_AEEVT_CLEAR      EQU (0x2 << 20) ;- (TC) Effect: clear
+AT91C_TC_AEEVT_TOGGLE     EQU (0x3 << 20) ;- (TC) Effect: toggle
+AT91C_TC_ASWTRG           EQU (0x3 << 22) ;- (TC) Software Trigger Effect on TIOA
+AT91C_TC_ASWTRG_NONE      EQU (0x0 << 22) ;- (TC) Effect: none
+AT91C_TC_ASWTRG_SET       EQU (0x1 << 22) ;- (TC) Effect: set
+AT91C_TC_ASWTRG_CLEAR     EQU (0x2 << 22) ;- (TC) Effect: clear
+AT91C_TC_ASWTRG_TOGGLE    EQU (0x3 << 22) ;- (TC) Effect: toggle
+AT91C_TC_BCPB             EQU (0x3 << 24) ;- (TC) RB Compare Effect on TIOB
+AT91C_TC_BCPB_NONE        EQU (0x0 << 24) ;- (TC) Effect: none
+AT91C_TC_BCPB_SET         EQU (0x1 << 24) ;- (TC) Effect: set
+AT91C_TC_BCPB_CLEAR       EQU (0x2 << 24) ;- (TC) Effect: clear
+AT91C_TC_BCPB_TOGGLE      EQU (0x3 << 24) ;- (TC) Effect: toggle
+AT91C_TC_BCPC             EQU (0x3 << 26) ;- (TC) RC Compare Effect on TIOB
+AT91C_TC_BCPC_NONE        EQU (0x0 << 26) ;- (TC) Effect: none
+AT91C_TC_BCPC_SET         EQU (0x1 << 26) ;- (TC) Effect: set
+AT91C_TC_BCPC_CLEAR       EQU (0x2 << 26) ;- (TC) Effect: clear
+AT91C_TC_BCPC_TOGGLE      EQU (0x3 << 26) ;- (TC) Effect: toggle
+AT91C_TC_BEEVT            EQU (0x3 << 28) ;- (TC) External Event Effect on TIOB
+AT91C_TC_BEEVT_NONE       EQU (0x0 << 28) ;- (TC) Effect: none
+AT91C_TC_BEEVT_SET        EQU (0x1 << 28) ;- (TC) Effect: set
+AT91C_TC_BEEVT_CLEAR      EQU (0x2 << 28) ;- (TC) Effect: clear
+AT91C_TC_BEEVT_TOGGLE     EQU (0x3 << 28) ;- (TC) Effect: toggle
+AT91C_TC_BSWTRG           EQU (0x3 << 30) ;- (TC) Software Trigger Effect on TIOB
+AT91C_TC_BSWTRG_NONE      EQU (0x0 << 30) ;- (TC) Effect: none
+AT91C_TC_BSWTRG_SET       EQU (0x1 << 30) ;- (TC) Effect: set
+AT91C_TC_BSWTRG_CLEAR     EQU (0x2 << 30) ;- (TC) Effect: clear
+AT91C_TC_BSWTRG_TOGGLE    EQU (0x3 << 30) ;- (TC) Effect: toggle
+// - -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
+AT91C_TC_COVFS            EQU (0x1 <<  0) ;- (TC) Counter Overflow
+AT91C_TC_LOVRS            EQU (0x1 <<  1) ;- (TC) Load Overrun
+AT91C_TC_CPAS             EQU (0x1 <<  2) ;- (TC) RA Compare
+AT91C_TC_CPBS             EQU (0x1 <<  3) ;- (TC) RB Compare
+AT91C_TC_CPCS             EQU (0x1 <<  4) ;- (TC) RC Compare
+AT91C_TC_LDRAS            EQU (0x1 <<  5) ;- (TC) RA Loading
+AT91C_TC_LDRBS            EQU (0x1 <<  6) ;- (TC) RB Loading
+AT91C_TC_ETRGS            EQU (0x1 <<  7) ;- (TC) External Trigger
+AT91C_TC_CLKSTA           EQU (0x1 << 16) ;- (TC) Clock Enabling
+AT91C_TC_MTIOA            EQU (0x1 << 17) ;- (TC) TIOA Mirror
+AT91C_TC_MTIOB            EQU (0x1 << 18) ;- (TC) TIOA Mirror
+// - -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
+// - -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
+// - -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Timer Counter Interface
+// - *****************************************************************************
+// - -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
+AT91C_TCB_SYNC            EQU (0x1 <<  0) ;- (TCB) Synchro Command
+// - -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
+AT91C_TCB_TC0XC0S         EQU (0x3 <<  0) ;- (TCB) External Clock Signal 0 Selection
+AT91C_TCB_TC0XC0S_TCLK0   EQU (0x0) ;- (TCB) TCLK0 connected to XC0
+AT91C_TCB_TC0XC0S_NONE    EQU (0x1) ;- (TCB) None signal connected to XC0
+AT91C_TCB_TC0XC0S_TIOA1   EQU (0x2) ;- (TCB) TIOA1 connected to XC0
+AT91C_TCB_TC0XC0S_TIOA2   EQU (0x3) ;- (TCB) TIOA2 connected to XC0
+AT91C_TCB_TC1XC1S         EQU (0x3 <<  2) ;- (TCB) External Clock Signal 1 Selection
+AT91C_TCB_TC1XC1S_TCLK1   EQU (0x0 <<  2) ;- (TCB) TCLK1 connected to XC1
+AT91C_TCB_TC1XC1S_NONE    EQU (0x1 <<  2) ;- (TCB) None signal connected to XC1
+AT91C_TCB_TC1XC1S_TIOA0   EQU (0x2 <<  2) ;- (TCB) TIOA0 connected to XC1
+AT91C_TCB_TC1XC1S_TIOA2   EQU (0x3 <<  2) ;- (TCB) TIOA2 connected to XC1
+AT91C_TCB_TC2XC2S         EQU (0x3 <<  4) ;- (TCB) External Clock Signal 2 Selection
+AT91C_TCB_TC2XC2S_TCLK2   EQU (0x0 <<  4) ;- (TCB) TCLK2 connected to XC2
+AT91C_TCB_TC2XC2S_NONE    EQU (0x1 <<  4) ;- (TCB) None signal connected to XC2
+AT91C_TCB_TC2XC2S_TIOA0   EQU (0x2 <<  4) ;- (TCB) TIOA0 connected to XC2
+AT91C_TCB_TC2XC2S_TIOA1   EQU (0x3 <<  4) ;- (TCB) TIOA2 connected to XC2
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface
+// - *****************************************************************************
+// - -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- 
+AT91C_CAN_MTIMEMARK       EQU (0xFFFF <<  0) ;- (CAN_MB) Mailbox Timemark
+AT91C_CAN_PRIOR           EQU (0xF << 16) ;- (CAN_MB) Mailbox Priority
+AT91C_CAN_MOT             EQU (0x7 << 24) ;- (CAN_MB) Mailbox Object Type
+AT91C_CAN_MOT_DIS         EQU (0x0 << 24) ;- (CAN_MB) 
+AT91C_CAN_MOT_RX          EQU (0x1 << 24) ;- (CAN_MB) 
+AT91C_CAN_MOT_RXOVERWRITE EQU (0x2 << 24) ;- (CAN_MB) 
+AT91C_CAN_MOT_TX          EQU (0x3 << 24) ;- (CAN_MB) 
+AT91C_CAN_MOT_CONSUMER    EQU (0x4 << 24) ;- (CAN_MB) 
+AT91C_CAN_MOT_PRODUCER    EQU (0x5 << 24) ;- (CAN_MB) 
+// - -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- 
+AT91C_CAN_MIDvB           EQU (0x3FFFF <<  0) ;- (CAN_MB) Complementary bits for identifier in extended mode
+AT91C_CAN_MIDvA           EQU (0x7FF << 18) ;- (CAN_MB) Identifier for standard frame mode
+AT91C_CAN_MIDE            EQU (0x1 << 29) ;- (CAN_MB) Identifier Version
+// - -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- 
+// - -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- 
+// - -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- 
+AT91C_CAN_MTIMESTAMP      EQU (0xFFFF <<  0) ;- (CAN_MB) Timer Value
+AT91C_CAN_MDLC            EQU (0xF << 16) ;- (CAN_MB) Mailbox Data Length Code
+AT91C_CAN_MRTR            EQU (0x1 << 20) ;- (CAN_MB) Mailbox Remote Transmission Request
+AT91C_CAN_MABT            EQU (0x1 << 22) ;- (CAN_MB) Mailbox Message Abort
+AT91C_CAN_MRDY            EQU (0x1 << 23) ;- (CAN_MB) Mailbox Ready
+AT91C_CAN_MMI             EQU (0x1 << 24) ;- (CAN_MB) Mailbox Message Ignored
+// - -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- 
+// - -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- 
+// - -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- 
+AT91C_CAN_MACR            EQU (0x1 << 22) ;- (CAN_MB) Abort Request for Mailbox
+AT91C_CAN_MTCR            EQU (0x1 << 23) ;- (CAN_MB) Mailbox Transfer Command
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Control Area Network Interface
+// - *****************************************************************************
+// - -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- 
+AT91C_CAN_CANEN           EQU (0x1 <<  0) ;- (CAN) CAN Controller Enable
+AT91C_CAN_LPM             EQU (0x1 <<  1) ;- (CAN) Disable/Enable Low Power Mode
+AT91C_CAN_ABM             EQU (0x1 <<  2) ;- (CAN) Disable/Enable Autobaud/Listen Mode
+AT91C_CAN_OVL             EQU (0x1 <<  3) ;- (CAN) Disable/Enable Overload Frame
+AT91C_CAN_TEOF            EQU (0x1 <<  4) ;- (CAN) Time Stamp messages at each end of Frame
+AT91C_CAN_TTM             EQU (0x1 <<  5) ;- (CAN) Disable/Enable Time Trigger Mode
+AT91C_CAN_TIMFRZ          EQU (0x1 <<  6) ;- (CAN) Enable Timer Freeze
+AT91C_CAN_DRPT            EQU (0x1 <<  7) ;- (CAN) Disable Repeat
+// - -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- 
+AT91C_CAN_MB0             EQU (0x1 <<  0) ;- (CAN) Mailbox 0 Flag
+AT91C_CAN_MB1             EQU (0x1 <<  1) ;- (CAN) Mailbox 1 Flag
+AT91C_CAN_MB2             EQU (0x1 <<  2) ;- (CAN) Mailbox 2 Flag
+AT91C_CAN_MB3             EQU (0x1 <<  3) ;- (CAN) Mailbox 3 Flag
+AT91C_CAN_MB4             EQU (0x1 <<  4) ;- (CAN) Mailbox 4 Flag
+AT91C_CAN_MB5             EQU (0x1 <<  5) ;- (CAN) Mailbox 5 Flag
+AT91C_CAN_MB6             EQU (0x1 <<  6) ;- (CAN) Mailbox 6 Flag
+AT91C_CAN_MB7             EQU (0x1 <<  7) ;- (CAN) Mailbox 7 Flag
+AT91C_CAN_MB8             EQU (0x1 <<  8) ;- (CAN) Mailbox 8 Flag
+AT91C_CAN_MB9             EQU (0x1 <<  9) ;- (CAN) Mailbox 9 Flag
+AT91C_CAN_MB10            EQU (0x1 << 10) ;- (CAN) Mailbox 10 Flag
+AT91C_CAN_MB11            EQU (0x1 << 11) ;- (CAN) Mailbox 11 Flag
+AT91C_CAN_MB12            EQU (0x1 << 12) ;- (CAN) Mailbox 12 Flag
+AT91C_CAN_MB13            EQU (0x1 << 13) ;- (CAN) Mailbox 13 Flag
+AT91C_CAN_MB14            EQU (0x1 << 14) ;- (CAN) Mailbox 14 Flag
+AT91C_CAN_MB15            EQU (0x1 << 15) ;- (CAN) Mailbox 15 Flag
+AT91C_CAN_ERRA            EQU (0x1 << 16) ;- (CAN) Error Active Mode Flag
+AT91C_CAN_WARN            EQU (0x1 << 17) ;- (CAN) Warning Limit Flag
+AT91C_CAN_ERRP            EQU (0x1 << 18) ;- (CAN) Error Passive Mode Flag
+AT91C_CAN_BOFF            EQU (0x1 << 19) ;- (CAN) Bus Off Mode Flag
+AT91C_CAN_SLEEP           EQU (0x1 << 20) ;- (CAN) Sleep Flag
+AT91C_CAN_WAKEUP          EQU (0x1 << 21) ;- (CAN) Wakeup Flag
+AT91C_CAN_TOVF            EQU (0x1 << 22) ;- (CAN) Timer Overflow Flag
+AT91C_CAN_TSTP            EQU (0x1 << 23) ;- (CAN) Timestamp Flag
+AT91C_CAN_CERR            EQU (0x1 << 24) ;- (CAN) CRC Error
+AT91C_CAN_SERR            EQU (0x1 << 25) ;- (CAN) Stuffing Error
+AT91C_CAN_AERR            EQU (0x1 << 26) ;- (CAN) Acknowledgment Error
+AT91C_CAN_FERR            EQU (0x1 << 27) ;- (CAN) Form Error
+AT91C_CAN_BERR            EQU (0x1 << 28) ;- (CAN) Bit Error
+// - -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- 
+// - -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- 
+// - -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- 
+AT91C_CAN_RBSY            EQU (0x1 << 29) ;- (CAN) Receiver Busy
+AT91C_CAN_TBSY            EQU (0x1 << 30) ;- (CAN) Transmitter Busy
+AT91C_CAN_OVLY            EQU (0x1 << 31) ;- (CAN) Overload Busy
+// - -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- 
+AT91C_CAN_PHASE2          EQU (0x7 <<  0) ;- (CAN) Phase 2 segment
+AT91C_CAN_PHASE1          EQU (0x7 <<  4) ;- (CAN) Phase 1 segment
+AT91C_CAN_PROPAG          EQU (0x7 <<  8) ;- (CAN) Programmation time segment
+AT91C_CAN_SYNC            EQU (0x3 << 12) ;- (CAN) Re-synchronization jump width segment
+AT91C_CAN_BRP             EQU (0x7F << 16) ;- (CAN) Baudrate Prescaler
+AT91C_CAN_SMP             EQU (0x1 << 24) ;- (CAN) Sampling mode
+// - -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- 
+AT91C_CAN_TIMER           EQU (0xFFFF <<  0) ;- (CAN) Timer field
+// - -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- 
+// - -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- 
+AT91C_CAN_REC             EQU (0xFF <<  0) ;- (CAN) Receive Error Counter
+AT91C_CAN_TEC             EQU (0xFF << 16) ;- (CAN) Transmit Error Counter
+// - -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- 
+AT91C_CAN_TIMRST          EQU (0x1 << 31) ;- (CAN) Timer Reset Field
+// - -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100
+// - *****************************************************************************
+// - -------- EMAC_NCR : (EMAC Offset: 0x0)  -------- 
+AT91C_EMAC_LB             EQU (0x1 <<  0) ;- (EMAC) Loopback. Optional. When set, loopback signal is at high level.
+AT91C_EMAC_LLB            EQU (0x1 <<  1) ;- (EMAC) Loopback local. 
+AT91C_EMAC_RE             EQU (0x1 <<  2) ;- (EMAC) Receive enable. 
+AT91C_EMAC_TE             EQU (0x1 <<  3) ;- (EMAC) Transmit enable. 
+AT91C_EMAC_MPE            EQU (0x1 <<  4) ;- (EMAC) Management port enable. 
+AT91C_EMAC_CLRSTAT        EQU (0x1 <<  5) ;- (EMAC) Clear statistics registers. 
+AT91C_EMAC_INCSTAT        EQU (0x1 <<  6) ;- (EMAC) Increment statistics registers. 
+AT91C_EMAC_WESTAT         EQU (0x1 <<  7) ;- (EMAC) Write enable for statistics registers. 
+AT91C_EMAC_BP             EQU (0x1 <<  8) ;- (EMAC) Back pressure. 
+AT91C_EMAC_TSTART         EQU (0x1 <<  9) ;- (EMAC) Start Transmission. 
+AT91C_EMAC_THALT          EQU (0x1 << 10) ;- (EMAC) Transmission Halt. 
+AT91C_EMAC_TPFR           EQU (0x1 << 11) ;- (EMAC) Transmit pause frame 
+AT91C_EMAC_TZQ            EQU (0x1 << 12) ;- (EMAC) Transmit zero quantum pause frame
+// - -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- 
+AT91C_EMAC_SPD            EQU (0x1 <<  0) ;- (EMAC) Speed. 
+AT91C_EMAC_FD             EQU (0x1 <<  1) ;- (EMAC) Full duplex. 
+AT91C_EMAC_JFRAME         EQU (0x1 <<  3) ;- (EMAC) Jumbo Frames. 
+AT91C_EMAC_CAF            EQU (0x1 <<  4) ;- (EMAC) Copy all frames. 
+AT91C_EMAC_NBC            EQU (0x1 <<  5) ;- (EMAC) No broadcast. 
+AT91C_EMAC_MTI            EQU (0x1 <<  6) ;- (EMAC) Multicast hash event enable
+AT91C_EMAC_UNI            EQU (0x1 <<  7) ;- (EMAC) Unicast hash enable. 
+AT91C_EMAC_BIG            EQU (0x1 <<  8) ;- (EMAC) Receive 1522 bytes. 
+AT91C_EMAC_EAE            EQU (0x1 <<  9) ;- (EMAC) External address match enable. 
+AT91C_EMAC_CLK            EQU (0x3 << 10) ;- (EMAC) 
+AT91C_EMAC_CLK_HCLK_8     EQU (0x0 << 10) ;- (EMAC) HCLK divided by 8
+AT91C_EMAC_CLK_HCLK_16    EQU (0x1 << 10) ;- (EMAC) HCLK divided by 16
+AT91C_EMAC_CLK_HCLK_32    EQU (0x2 << 10) ;- (EMAC) HCLK divided by 32
+AT91C_EMAC_CLK_HCLK_64    EQU (0x3 << 10) ;- (EMAC) HCLK divided by 64
+AT91C_EMAC_RTY            EQU (0x1 << 12) ;- (EMAC) 
+AT91C_EMAC_PAE            EQU (0x1 << 13) ;- (EMAC) 
+AT91C_EMAC_RBOF           EQU (0x3 << 14) ;- (EMAC) 
+AT91C_EMAC_RBOF_OFFSET_0  EQU (0x0 << 14) ;- (EMAC) no offset from start of receive buffer
+AT91C_EMAC_RBOF_OFFSET_1  EQU (0x1 << 14) ;- (EMAC) one byte offset from start of receive buffer
+AT91C_EMAC_RBOF_OFFSET_2  EQU (0x2 << 14) ;- (EMAC) two bytes offset from start of receive buffer
+AT91C_EMAC_RBOF_OFFSET_3  EQU (0x3 << 14) ;- (EMAC) three bytes offset from start of receive buffer
+AT91C_EMAC_RLCE           EQU (0x1 << 16) ;- (EMAC) Receive Length field Checking Enable
+AT91C_EMAC_DRFCS          EQU (0x1 << 17) ;- (EMAC) Discard Receive FCS
+AT91C_EMAC_EFRHD          EQU (0x1 << 18) ;- (EMAC) 
+AT91C_EMAC_IRXFCS         EQU (0x1 << 19) ;- (EMAC) Ignore RX FCS
+// - -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- 
+AT91C_EMAC_LINKR          EQU (0x1 <<  0) ;- (EMAC) 
+AT91C_EMAC_MDIO           EQU (0x1 <<  1) ;- (EMAC) 
+AT91C_EMAC_IDLE           EQU (0x1 <<  2) ;- (EMAC) 
+// - -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- 
+AT91C_EMAC_UBR            EQU (0x1 <<  0) ;- (EMAC) 
+AT91C_EMAC_COL            EQU (0x1 <<  1) ;- (EMAC) 
+AT91C_EMAC_RLES           EQU (0x1 <<  2) ;- (EMAC) 
+AT91C_EMAC_TGO            EQU (0x1 <<  3) ;- (EMAC) Transmit Go
+AT91C_EMAC_BEX            EQU (0x1 <<  4) ;- (EMAC) Buffers exhausted mid frame
+AT91C_EMAC_COMP           EQU (0x1 <<  5) ;- (EMAC) 
+AT91C_EMAC_UND            EQU (0x1 <<  6) ;- (EMAC) 
+// - -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- 
+AT91C_EMAC_BNA            EQU (0x1 <<  0) ;- (EMAC) 
+AT91C_EMAC_REC            EQU (0x1 <<  1) ;- (EMAC) 
+AT91C_EMAC_OVR            EQU (0x1 <<  2) ;- (EMAC) 
+// - -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- 
+AT91C_EMAC_MFD            EQU (0x1 <<  0) ;- (EMAC) 
+AT91C_EMAC_RCOMP          EQU (0x1 <<  1) ;- (EMAC) 
+AT91C_EMAC_RXUBR          EQU (0x1 <<  2) ;- (EMAC) 
+AT91C_EMAC_TXUBR          EQU (0x1 <<  3) ;- (EMAC) 
+AT91C_EMAC_TUNDR          EQU (0x1 <<  4) ;- (EMAC) 
+AT91C_EMAC_RLEX           EQU (0x1 <<  5) ;- (EMAC) 
+AT91C_EMAC_TXERR          EQU (0x1 <<  6) ;- (EMAC) 
+AT91C_EMAC_TCOMP          EQU (0x1 <<  7) ;- (EMAC) 
+AT91C_EMAC_LINK           EQU (0x1 <<  9) ;- (EMAC) 
+AT91C_EMAC_ROVR           EQU (0x1 << 10) ;- (EMAC) 
+AT91C_EMAC_HRESP          EQU (0x1 << 11) ;- (EMAC) 
+AT91C_EMAC_PFRE           EQU (0x1 << 12) ;- (EMAC) 
+AT91C_EMAC_PTZ            EQU (0x1 << 13) ;- (EMAC) 
+// - -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- 
+// - -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- 
+// - -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- 
+// - -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- 
+AT91C_EMAC_DATA           EQU (0xFFFF <<  0) ;- (EMAC) 
+AT91C_EMAC_CODE           EQU (0x3 << 16) ;- (EMAC) 
+AT91C_EMAC_REGA           EQU (0x1F << 18) ;- (EMAC) 
+AT91C_EMAC_PHYA           EQU (0x1F << 23) ;- (EMAC) 
+AT91C_EMAC_RW             EQU (0x3 << 28) ;- (EMAC) 
+AT91C_EMAC_SOF            EQU (0x3 << 30) ;- (EMAC) 
+// - -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- 
+AT91C_EMAC_RMII           EQU (0x1 <<  0) ;- (EMAC) Reduce MII
+// - -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- 
+AT91C_EMAC_IP             EQU (0xFFFF <<  0) ;- (EMAC) ARP request IP address
+AT91C_EMAC_MAG            EQU (0x1 << 16) ;- (EMAC) Magic packet event enable
+AT91C_EMAC_ARP            EQU (0x1 << 17) ;- (EMAC) ARP request event enable
+AT91C_EMAC_SA1            EQU (0x1 << 18) ;- (EMAC) Specific address register 1 event enable
+// - -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- 
+AT91C_EMAC_REVREF         EQU (0xFFFF <<  0) ;- (EMAC) 
+AT91C_EMAC_PARTREF        EQU (0xFFFF << 16) ;- (EMAC) 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
+// - *****************************************************************************
+// - -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- 
+AT91C_ADC_SWRST           EQU (0x1 <<  0) ;- (ADC) Software Reset
+AT91C_ADC_START           EQU (0x1 <<  1) ;- (ADC) Start Conversion
+// - -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- 
+AT91C_ADC_TRGEN           EQU (0x1 <<  0) ;- (ADC) Trigger Enable
+AT91C_ADC_TRGEN_DIS       EQU (0x0) ;- (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
+AT91C_ADC_TRGEN_EN        EQU (0x1) ;- (ADC) Hardware trigger selected by TRGSEL field is enabled.
+AT91C_ADC_TRGSEL          EQU (0x7 <<  1) ;- (ADC) Trigger Selection
+AT91C_ADC_TRGSEL_TIOA0    EQU (0x0 <<  1) ;- (ADC) Selected TRGSEL = TIAO0
+AT91C_ADC_TRGSEL_TIOA1    EQU (0x1 <<  1) ;- (ADC) Selected TRGSEL = TIAO1
+AT91C_ADC_TRGSEL_TIOA2    EQU (0x2 <<  1) ;- (ADC) Selected TRGSEL = TIAO2
+AT91C_ADC_TRGSEL_TIOA3    EQU (0x3 <<  1) ;- (ADC) Selected TRGSEL = TIAO3
+AT91C_ADC_TRGSEL_TIOA4    EQU (0x4 <<  1) ;- (ADC) Selected TRGSEL = TIAO4
+AT91C_ADC_TRGSEL_TIOA5    EQU (0x5 <<  1) ;- (ADC) Selected TRGSEL = TIAO5
+AT91C_ADC_TRGSEL_EXT      EQU (0x6 <<  1) ;- (ADC) Selected TRGSEL = External Trigger
+AT91C_ADC_LOWRES          EQU (0x1 <<  4) ;- (ADC) Resolution.
+AT91C_ADC_LOWRES_10_BIT   EQU (0x0 <<  4) ;- (ADC) 10-bit resolution
+AT91C_ADC_LOWRES_8_BIT    EQU (0x1 <<  4) ;- (ADC) 8-bit resolution
+AT91C_ADC_SLEEP           EQU (0x1 <<  5) ;- (ADC) Sleep Mode
+AT91C_ADC_SLEEP_NORMAL_MODE EQU (0x0 <<  5) ;- (ADC) Normal Mode
+AT91C_ADC_SLEEP_MODE      EQU (0x1 <<  5) ;- (ADC) Sleep Mode
+AT91C_ADC_PRESCAL         EQU (0x3F <<  8) ;- (ADC) Prescaler rate selection
+AT91C_ADC_STARTUP         EQU (0x1F << 16) ;- (ADC) Startup Time
+AT91C_ADC_SHTIM           EQU (0xF << 24) ;- (ADC) Sample & Hold Time
+// - -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- 
+AT91C_ADC_CH0             EQU (0x1 <<  0) ;- (ADC) Channel 0
+AT91C_ADC_CH1             EQU (0x1 <<  1) ;- (ADC) Channel 1
+AT91C_ADC_CH2             EQU (0x1 <<  2) ;- (ADC) Channel 2
+AT91C_ADC_CH3             EQU (0x1 <<  3) ;- (ADC) Channel 3
+AT91C_ADC_CH4             EQU (0x1 <<  4) ;- (ADC) Channel 4
+AT91C_ADC_CH5             EQU (0x1 <<  5) ;- (ADC) Channel 5
+AT91C_ADC_CH6             EQU (0x1 <<  6) ;- (ADC) Channel 6
+AT91C_ADC_CH7             EQU (0x1 <<  7) ;- (ADC) Channel 7
+// - -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- 
+// - -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- 
+// - -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- 
+AT91C_ADC_EOC0            EQU (0x1 <<  0) ;- (ADC) End of Conversion
+AT91C_ADC_EOC1            EQU (0x1 <<  1) ;- (ADC) End of Conversion
+AT91C_ADC_EOC2            EQU (0x1 <<  2) ;- (ADC) End of Conversion
+AT91C_ADC_EOC3            EQU (0x1 <<  3) ;- (ADC) End of Conversion
+AT91C_ADC_EOC4            EQU (0x1 <<  4) ;- (ADC) End of Conversion
+AT91C_ADC_EOC5            EQU (0x1 <<  5) ;- (ADC) End of Conversion
+AT91C_ADC_EOC6            EQU (0x1 <<  6) ;- (ADC) End of Conversion
+AT91C_ADC_EOC7            EQU (0x1 <<  7) ;- (ADC) End of Conversion
+AT91C_ADC_OVRE0           EQU (0x1 <<  8) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE1           EQU (0x1 <<  9) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE2           EQU (0x1 << 10) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE3           EQU (0x1 << 11) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE4           EQU (0x1 << 12) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE5           EQU (0x1 << 13) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE6           EQU (0x1 << 14) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE7           EQU (0x1 << 15) ;- (ADC) Overrun Error
+AT91C_ADC_DRDY            EQU (0x1 << 16) ;- (ADC) Data Ready
+AT91C_ADC_GOVRE           EQU (0x1 << 17) ;- (ADC) General Overrun
+AT91C_ADC_ENDRX           EQU (0x1 << 18) ;- (ADC) End of Receiver Transfer
+AT91C_ADC_RXBUFF          EQU (0x1 << 19) ;- (ADC) RXBUFF Interrupt
+// - -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- 
+AT91C_ADC_LDATA           EQU (0x3FF <<  0) ;- (ADC) Last Data Converted
+// - -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- 
+// - -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- 
+// - -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- 
+// - -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- 
+AT91C_ADC_DATA            EQU (0x3FF <<  0) ;- (ADC) Converted Data
+// - -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- 
+// - -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- 
+// - -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- 
+// - -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- 
+// - -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- 
+// - -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- 
+// - -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Advanced  Encryption Standard
+// - *****************************************************************************
+// - -------- AES_CR : (AES Offset: 0x0) Control Register -------- 
+AT91C_AES_START           EQU (0x1 <<  0) ;- (AES) Starts Processing
+AT91C_AES_SWRST           EQU (0x1 <<  8) ;- (AES) Software Reset
+AT91C_AES_LOADSEED        EQU (0x1 << 16) ;- (AES) Random Number Generator Seed Loading
+// - -------- AES_MR : (AES Offset: 0x4) Mode Register -------- 
+AT91C_AES_CIPHER          EQU (0x1 <<  0) ;- (AES) Processing Mode
+AT91C_AES_PROCDLY         EQU (0xF <<  4) ;- (AES) Processing Delay
+AT91C_AES_SMOD            EQU (0x3 <<  8) ;- (AES) Start Mode
+AT91C_AES_SMOD_MANUAL     EQU (0x0 <<  8) ;- (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
+AT91C_AES_SMOD_AUTO       EQU (0x1 <<  8) ;- (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
+AT91C_AES_SMOD_PDC        EQU (0x2 <<  8) ;- (AES) PDC Mode (cf datasheet).
+AT91C_AES_OPMOD           EQU (0x7 << 12) ;- (AES) Operation Mode
+AT91C_AES_OPMOD_ECB       EQU (0x0 << 12) ;- (AES) ECB Electronic CodeBook mode.
+AT91C_AES_OPMOD_CBC       EQU (0x1 << 12) ;- (AES) CBC Cipher Block Chaining mode.
+AT91C_AES_OPMOD_OFB       EQU (0x2 << 12) ;- (AES) OFB Output Feedback mode.
+AT91C_AES_OPMOD_CFB       EQU (0x3 << 12) ;- (AES) CFB Cipher Feedback mode.
+AT91C_AES_OPMOD_CTR       EQU (0x4 << 12) ;- (AES) CTR Counter mode.
+AT91C_AES_LOD             EQU (0x1 << 15) ;- (AES) Last Output Data Mode
+AT91C_AES_CFBS            EQU (0x7 << 16) ;- (AES) Cipher Feedback Data Size
+AT91C_AES_CFBS_128_BIT    EQU (0x0 << 16) ;- (AES) 128-bit.
+AT91C_AES_CFBS_64_BIT     EQU (0x1 << 16) ;- (AES) 64-bit.
+AT91C_AES_CFBS_32_BIT     EQU (0x2 << 16) ;- (AES) 32-bit.
+AT91C_AES_CFBS_16_BIT     EQU (0x3 << 16) ;- (AES) 16-bit.
+AT91C_AES_CFBS_8_BIT      EQU (0x4 << 16) ;- (AES) 8-bit.
+AT91C_AES_CKEY            EQU (0xF << 20) ;- (AES) Countermeasure Key
+AT91C_AES_CTYPE           EQU (0x1F << 24) ;- (AES) Countermeasure Type
+AT91C_AES_CTYPE_TYPE1_EN  EQU (0x1 << 24) ;- (AES) Countermeasure type 1 is enabled.
+AT91C_AES_CTYPE_TYPE2_EN  EQU (0x2 << 24) ;- (AES) Countermeasure type 2 is enabled.
+AT91C_AES_CTYPE_TYPE3_EN  EQU (0x4 << 24) ;- (AES) Countermeasure type 3 is enabled.
+AT91C_AES_CTYPE_TYPE4_EN  EQU (0x8 << 24) ;- (AES) Countermeasure type 4 is enabled.
+AT91C_AES_CTYPE_TYPE5_EN  EQU (0x10 << 24) ;- (AES) Countermeasure type 5 is enabled.
+// - -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- 
+AT91C_AES_DATRDY          EQU (0x1 <<  0) ;- (AES) DATRDY
+AT91C_AES_ENDRX           EQU (0x1 <<  1) ;- (AES) PDC Read Buffer End
+AT91C_AES_ENDTX           EQU (0x1 <<  2) ;- (AES) PDC Write Buffer End
+AT91C_AES_RXBUFF          EQU (0x1 <<  3) ;- (AES) PDC Read Buffer Full
+AT91C_AES_TXBUFE          EQU (0x1 <<  4) ;- (AES) PDC Write Buffer Empty
+AT91C_AES_URAD            EQU (0x1 <<  8) ;- (AES) Unspecified Register Access Detection
+// - -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- 
+// - -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- 
+// - -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- 
+AT91C_AES_URAT            EQU (0x7 << 12) ;- (AES) Unspecified Register Access Type Status
+AT91C_AES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (AES) Input data register written during the data processing in PDC mode.
+AT91C_AES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (AES) Output data register read during the data processing.
+AT91C_AES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (AES) Mode register written during the data processing.
+AT91C_AES_URAT_OUT_DAT_READ_SUBKEY EQU (0x3 << 12) ;- (AES) Output data register read during the sub-keys generation.
+AT91C_AES_URAT_MODEREG_WRITE_SUBKEY EQU (0x4 << 12) ;- (AES) Mode register written during the sub-keys generation.
+AT91C_AES_URAT_WO_REG_READ EQU (0x5 << 12) ;- (AES) Write-only register read access.
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Triple Data Encryption Standard
+// - *****************************************************************************
+// - -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- 
+AT91C_TDES_START          EQU (0x1 <<  0) ;- (TDES) Starts Processing
+AT91C_TDES_SWRST          EQU (0x1 <<  8) ;- (TDES) Software Reset
+// - -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- 
+AT91C_TDES_CIPHER         EQU (0x1 <<  0) ;- (TDES) Processing Mode
+AT91C_TDES_TDESMOD        EQU (0x1 <<  1) ;- (TDES) Single or Triple DES Mode
+AT91C_TDES_KEYMOD         EQU (0x1 <<  4) ;- (TDES) Key Mode
+AT91C_TDES_SMOD           EQU (0x3 <<  8) ;- (TDES) Start Mode
+AT91C_TDES_SMOD_MANUAL    EQU (0x0 <<  8) ;- (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
+AT91C_TDES_SMOD_AUTO      EQU (0x1 <<  8) ;- (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
+AT91C_TDES_SMOD_PDC       EQU (0x2 <<  8) ;- (TDES) PDC Mode (cf datasheet).
+AT91C_TDES_OPMOD          EQU (0x3 << 12) ;- (TDES) Operation Mode
+AT91C_TDES_OPMOD_ECB      EQU (0x0 << 12) ;- (TDES) ECB Electronic CodeBook mode.
+AT91C_TDES_OPMOD_CBC      EQU (0x1 << 12) ;- (TDES) CBC Cipher Block Chaining mode.
+AT91C_TDES_OPMOD_OFB      EQU (0x2 << 12) ;- (TDES) OFB Output Feedback mode.
+AT91C_TDES_OPMOD_CFB      EQU (0x3 << 12) ;- (TDES) CFB Cipher Feedback mode.
+AT91C_TDES_LOD            EQU (0x1 << 15) ;- (TDES) Last Output Data Mode
+AT91C_TDES_CFBS           EQU (0x3 << 16) ;- (TDES) Cipher Feedback Data Size
+AT91C_TDES_CFBS_64_BIT    EQU (0x0 << 16) ;- (TDES) 64-bit.
+AT91C_TDES_CFBS_32_BIT    EQU (0x1 << 16) ;- (TDES) 32-bit.
+AT91C_TDES_CFBS_16_BIT    EQU (0x2 << 16) ;- (TDES) 16-bit.
+AT91C_TDES_CFBS_8_BIT     EQU (0x3 << 16) ;- (TDES) 8-bit.
+// - -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- 
+AT91C_TDES_DATRDY         EQU (0x1 <<  0) ;- (TDES) DATRDY
+AT91C_TDES_ENDRX          EQU (0x1 <<  1) ;- (TDES) PDC Read Buffer End
+AT91C_TDES_ENDTX          EQU (0x1 <<  2) ;- (TDES) PDC Write Buffer End
+AT91C_TDES_RXBUFF         EQU (0x1 <<  3) ;- (TDES) PDC Read Buffer Full
+AT91C_TDES_TXBUFE         EQU (0x1 <<  4) ;- (TDES) PDC Write Buffer Empty
+AT91C_TDES_URAD           EQU (0x1 <<  8) ;- (TDES) Unspecified Register Access Detection
+// - -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- 
+// - -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- 
+// - -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- 
+AT91C_TDES_URAT           EQU (0x3 << 12) ;- (TDES) Unspecified Register Access Type Status
+AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (TDES) Input data register written during the data processing in PDC mode.
+AT91C_TDES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (TDES) Output data register read during the data processing.
+AT91C_TDES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (TDES) Mode register written during the data processing.
+AT91C_TDES_URAT_WO_REG_READ EQU (0x3 << 12) ;- (TDES) Write-only register read access.
+
+// - *****************************************************************************
+// -               REGISTER ADDRESS DEFINITION FOR AT91SAM7X256
+// - *****************************************************************************
+// - ========== Register definition for SYS peripheral ========== 
+// - ========== Register definition for AIC peripheral ========== 
+AT91C_AIC_IVR             EQU (0xFFFFF100) ;- (AIC) IRQ Vector Register
+AT91C_AIC_SMR             EQU (0xFFFFF000) ;- (AIC) Source Mode Register
+AT91C_AIC_FVR             EQU (0xFFFFF104) ;- (AIC) FIQ Vector Register
+AT91C_AIC_DCR             EQU (0xFFFFF138) ;- (AIC) Debug Control Register (Protect)
+AT91C_AIC_EOICR           EQU (0xFFFFF130) ;- (AIC) End of Interrupt Command Register
+AT91C_AIC_SVR             EQU (0xFFFFF080) ;- (AIC) Source Vector Register
+AT91C_AIC_FFSR            EQU (0xFFFFF148) ;- (AIC) Fast Forcing Status Register
+AT91C_AIC_ICCR            EQU (0xFFFFF128) ;- (AIC) Interrupt Clear Command Register
+AT91C_AIC_ISR             EQU (0xFFFFF108) ;- (AIC) Interrupt Status Register
+AT91C_AIC_IMR             EQU (0xFFFFF110) ;- (AIC) Interrupt Mask Register
+AT91C_AIC_IPR             EQU (0xFFFFF10C) ;- (AIC) Interrupt Pending Register
+AT91C_AIC_FFER            EQU (0xFFFFF140) ;- (AIC) Fast Forcing Enable Register
+AT91C_AIC_IECR            EQU (0xFFFFF120) ;- (AIC) Interrupt Enable Command Register
+AT91C_AIC_ISCR            EQU (0xFFFFF12C) ;- (AIC) Interrupt Set Command Register
+AT91C_AIC_FFDR            EQU (0xFFFFF144) ;- (AIC) Fast Forcing Disable Register
+AT91C_AIC_CISR            EQU (0xFFFFF114) ;- (AIC) Core Interrupt Status Register
+AT91C_AIC_IDCR            EQU (0xFFFFF124) ;- (AIC) Interrupt Disable Command Register
+AT91C_AIC_SPU             EQU (0xFFFFF134) ;- (AIC) Spurious Vector Register
+// - ========== Register definition for PDC_DBGU peripheral ========== 
+AT91C_DBGU_TCR            EQU (0xFFFFF30C) ;- (PDC_DBGU) Transmit Counter Register
+AT91C_DBGU_RNPR           EQU (0xFFFFF310) ;- (PDC_DBGU) Receive Next Pointer Register
+AT91C_DBGU_TNPR           EQU (0xFFFFF318) ;- (PDC_DBGU) Transmit Next Pointer Register
+AT91C_DBGU_TPR            EQU (0xFFFFF308) ;- (PDC_DBGU) Transmit Pointer Register
+AT91C_DBGU_RPR            EQU (0xFFFFF300) ;- (PDC_DBGU) Receive Pointer Register
+AT91C_DBGU_RCR            EQU (0xFFFFF304) ;- (PDC_DBGU) Receive Counter Register
+AT91C_DBGU_RNCR           EQU (0xFFFFF314) ;- (PDC_DBGU) Receive Next Counter Register
+AT91C_DBGU_PTCR           EQU (0xFFFFF320) ;- (PDC_DBGU) PDC Transfer Control Register
+AT91C_DBGU_PTSR           EQU (0xFFFFF324) ;- (PDC_DBGU) PDC Transfer Status Register
+AT91C_DBGU_TNCR           EQU (0xFFFFF31C) ;- (PDC_DBGU) Transmit Next Counter Register
+// - ========== Register definition for DBGU peripheral ========== 
+AT91C_DBGU_EXID           EQU (0xFFFFF244) ;- (DBGU) Chip ID Extension Register
+AT91C_DBGU_BRGR           EQU (0xFFFFF220) ;- (DBGU) Baud Rate Generator Register
+AT91C_DBGU_IDR            EQU (0xFFFFF20C) ;- (DBGU) Interrupt Disable Register
+AT91C_DBGU_CSR            EQU (0xFFFFF214) ;- (DBGU) Channel Status Register
+AT91C_DBGU_CIDR           EQU (0xFFFFF240) ;- (DBGU) Chip ID Register
+AT91C_DBGU_MR             EQU (0xFFFFF204) ;- (DBGU) Mode Register
+AT91C_DBGU_IMR            EQU (0xFFFFF210) ;- (DBGU) Interrupt Mask Register
+AT91C_DBGU_CR             EQU (0xFFFFF200) ;- (DBGU) Control Register
+AT91C_DBGU_FNTR           EQU (0xFFFFF248) ;- (DBGU) Force NTRST Register
+AT91C_DBGU_THR            EQU (0xFFFFF21C) ;- (DBGU) Transmitter Holding Register
+AT91C_DBGU_RHR            EQU (0xFFFFF218) ;- (DBGU) Receiver Holding Register
+AT91C_DBGU_IER            EQU (0xFFFFF208) ;- (DBGU) Interrupt Enable Register
+// - ========== Register definition for PIOA peripheral ========== 
+AT91C_PIOA_ODR            EQU (0xFFFFF414) ;- (PIOA) Output Disable Registerr
+AT91C_PIOA_SODR           EQU (0xFFFFF430) ;- (PIOA) Set Output Data Register
+AT91C_PIOA_ISR            EQU (0xFFFFF44C) ;- (PIOA) Interrupt Status Register
+AT91C_PIOA_ABSR           EQU (0xFFFFF478) ;- (PIOA) AB Select Status Register
+AT91C_PIOA_IER            EQU (0xFFFFF440) ;- (PIOA) Interrupt Enable Register
+AT91C_PIOA_PPUDR          EQU (0xFFFFF460) ;- (PIOA) Pull-up Disable Register
+AT91C_PIOA_IMR            EQU (0xFFFFF448) ;- (PIOA) Interrupt Mask Register
+AT91C_PIOA_PER            EQU (0xFFFFF400) ;- (PIOA) PIO Enable Register
+AT91C_PIOA_IFDR           EQU (0xFFFFF424) ;- (PIOA) Input Filter Disable Register
+AT91C_PIOA_OWDR           EQU (0xFFFFF4A4) ;- (PIOA) Output Write Disable Register
+AT91C_PIOA_MDSR           EQU (0xFFFFF458) ;- (PIOA) Multi-driver Status Register
+AT91C_PIOA_IDR            EQU (0xFFFFF444) ;- (PIOA) Interrupt Disable Register
+AT91C_PIOA_ODSR           EQU (0xFFFFF438) ;- (PIOA) Output Data Status Register
+AT91C_PIOA_PPUSR          EQU (0xFFFFF468) ;- (PIOA) Pull-up Status Register
+AT91C_PIOA_OWSR           EQU (0xFFFFF4A8) ;- (PIOA) Output Write Status Register
+AT91C_PIOA_BSR            EQU (0xFFFFF474) ;- (PIOA) Select B Register
+AT91C_PIOA_OWER           EQU (0xFFFFF4A0) ;- (PIOA) Output Write Enable Register
+AT91C_PIOA_IFER           EQU (0xFFFFF420) ;- (PIOA) Input Filter Enable Register
+AT91C_PIOA_PDSR           EQU (0xFFFFF43C) ;- (PIOA) Pin Data Status Register
+AT91C_PIOA_PPUER          EQU (0xFFFFF464) ;- (PIOA) Pull-up Enable Register
+AT91C_PIOA_OSR            EQU (0xFFFFF418) ;- (PIOA) Output Status Register
+AT91C_PIOA_ASR            EQU (0xFFFFF470) ;- (PIOA) Select A Register
+AT91C_PIOA_MDDR           EQU (0xFFFFF454) ;- (PIOA) Multi-driver Disable Register
+AT91C_PIOA_CODR           EQU (0xFFFFF434) ;- (PIOA) Clear Output Data Register
+AT91C_PIOA_MDER           EQU (0xFFFFF450) ;- (PIOA) Multi-driver Enable Register
+AT91C_PIOA_PDR            EQU (0xFFFFF404) ;- (PIOA) PIO Disable Register
+AT91C_PIOA_IFSR           EQU (0xFFFFF428) ;- (PIOA) Input Filter Status Register
+AT91C_PIOA_OER            EQU (0xFFFFF410) ;- (PIOA) Output Enable Register
+AT91C_PIOA_PSR            EQU (0xFFFFF408) ;- (PIOA) PIO Status Register
+// - ========== Register definition for PIOB peripheral ========== 
+AT91C_PIOB_OWDR           EQU (0xFFFFF6A4) ;- (PIOB) Output Write Disable Register
+AT91C_PIOB_MDER           EQU (0xFFFFF650) ;- (PIOB) Multi-driver Enable Register
+AT91C_PIOB_PPUSR          EQU (0xFFFFF668) ;- (PIOB) Pull-up Status Register
+AT91C_PIOB_IMR            EQU (0xFFFFF648) ;- (PIOB) Interrupt Mask Register
+AT91C_PIOB_ASR            EQU (0xFFFFF670) ;- (PIOB) Select A Register
+AT91C_PIOB_PPUDR          EQU (0xFFFFF660) ;- (PIOB) Pull-up Disable Register
+AT91C_PIOB_PSR            EQU (0xFFFFF608) ;- (PIOB) PIO Status Register
+AT91C_PIOB_IER            EQU (0xFFFFF640) ;- (PIOB) Interrupt Enable Register
+AT91C_PIOB_CODR           EQU (0xFFFFF634) ;- (PIOB) Clear Output Data Register
+AT91C_PIOB_OWER           EQU (0xFFFFF6A0) ;- (PIOB) Output Write Enable Register
+AT91C_PIOB_ABSR           EQU (0xFFFFF678) ;- (PIOB) AB Select Status Register
+AT91C_PIOB_IFDR           EQU (0xFFFFF624) ;- (PIOB) Input Filter Disable Register
+AT91C_PIOB_PDSR           EQU (0xFFFFF63C) ;- (PIOB) Pin Data Status Register
+AT91C_PIOB_IDR            EQU (0xFFFFF644) ;- (PIOB) Interrupt Disable Register
+AT91C_PIOB_OWSR           EQU (0xFFFFF6A8) ;- (PIOB) Output Write Status Register
+AT91C_PIOB_PDR            EQU (0xFFFFF604) ;- (PIOB) PIO Disable Register
+AT91C_PIOB_ODR            EQU (0xFFFFF614) ;- (PIOB) Output Disable Registerr
+AT91C_PIOB_IFSR           EQU (0xFFFFF628) ;- (PIOB) Input Filter Status Register
+AT91C_PIOB_PPUER          EQU (0xFFFFF664) ;- (PIOB) Pull-up Enable Register
+AT91C_PIOB_SODR           EQU (0xFFFFF630) ;- (PIOB) Set Output Data Register
+AT91C_PIOB_ISR            EQU (0xFFFFF64C) ;- (PIOB) Interrupt Status Register
+AT91C_PIOB_ODSR           EQU (0xFFFFF638) ;- (PIOB) Output Data Status Register
+AT91C_PIOB_OSR            EQU (0xFFFFF618) ;- (PIOB) Output Status Register
+AT91C_PIOB_MDSR           EQU (0xFFFFF658) ;- (PIOB) Multi-driver Status Register
+AT91C_PIOB_IFER           EQU (0xFFFFF620) ;- (PIOB) Input Filter Enable Register
+AT91C_PIOB_BSR            EQU (0xFFFFF674) ;- (PIOB) Select B Register
+AT91C_PIOB_MDDR           EQU (0xFFFFF654) ;- (PIOB) Multi-driver Disable Register
+AT91C_PIOB_OER            EQU (0xFFFFF610) ;- (PIOB) Output Enable Register
+AT91C_PIOB_PER            EQU (0xFFFFF600) ;- (PIOB) PIO Enable Register
+// - ========== Register definition for CKGR peripheral ========== 
+AT91C_CKGR_MOR            EQU (0xFFFFFC20) ;- (CKGR) Main Oscillator Register
+AT91C_CKGR_PLLR           EQU (0xFFFFFC2C) ;- (CKGR) PLL Register
+AT91C_CKGR_MCFR           EQU (0xFFFFFC24) ;- (CKGR) Main Clock  Frequency Register
+// - ========== Register definition for PMC peripheral ========== 
+AT91C_PMC_IDR             EQU (0xFFFFFC64) ;- (PMC) Interrupt Disable Register
+AT91C_PMC_MOR             EQU (0xFFFFFC20) ;- (PMC) Main Oscillator Register
+AT91C_PMC_PLLR            EQU (0xFFFFFC2C) ;- (PMC) PLL Register
+AT91C_PMC_PCER            EQU (0xFFFFFC10) ;- (PMC) Peripheral Clock Enable Register
+AT91C_PMC_PCKR            EQU (0xFFFFFC40) ;- (PMC) Programmable Clock Register
+AT91C_PMC_MCKR            EQU (0xFFFFFC30) ;- (PMC) Master Clock Register
+AT91C_PMC_SCDR            EQU (0xFFFFFC04) ;- (PMC) System Clock Disable Register
+AT91C_PMC_PCDR            EQU (0xFFFFFC14) ;- (PMC) Peripheral Clock Disable Register
+AT91C_PMC_SCSR            EQU (0xFFFFFC08) ;- (PMC) System Clock Status Register
+AT91C_PMC_PCSR            EQU (0xFFFFFC18) ;- (PMC) Peripheral Clock Status Register
+AT91C_PMC_MCFR            EQU (0xFFFFFC24) ;- (PMC) Main Clock  Frequency Register
+AT91C_PMC_SCER            EQU (0xFFFFFC00) ;- (PMC) System Clock Enable Register
+AT91C_PMC_IMR             EQU (0xFFFFFC6C) ;- (PMC) Interrupt Mask Register
+AT91C_PMC_IER             EQU (0xFFFFFC60) ;- (PMC) Interrupt Enable Register
+AT91C_PMC_SR              EQU (0xFFFFFC68) ;- (PMC) Status Register
+// - ========== Register definition for RSTC peripheral ========== 
+AT91C_RSTC_RCR            EQU (0xFFFFFD00) ;- (RSTC) Reset Control Register
+AT91C_RSTC_RMR            EQU (0xFFFFFD08) ;- (RSTC) Reset Mode Register
+AT91C_RSTC_RSR            EQU (0xFFFFFD04) ;- (RSTC) Reset Status Register
+// - ========== Register definition for RTTC peripheral ========== 
+AT91C_RTTC_RTSR           EQU (0xFFFFFD2C) ;- (RTTC) Real-time Status Register
+AT91C_RTTC_RTMR           EQU (0xFFFFFD20) ;- (RTTC) Real-time Mode Register
+AT91C_RTTC_RTVR           EQU (0xFFFFFD28) ;- (RTTC) Real-time Value Register
+AT91C_RTTC_RTAR           EQU (0xFFFFFD24) ;- (RTTC) Real-time Alarm Register
+// - ========== Register definition for PITC peripheral ========== 
+AT91C_PITC_PIVR           EQU (0xFFFFFD38) ;- (PITC) Period Interval Value Register
+AT91C_PITC_PISR           EQU (0xFFFFFD34) ;- (PITC) Period Interval Status Register
+AT91C_PITC_PIIR           EQU (0xFFFFFD3C) ;- (PITC) Period Interval Image Register
+AT91C_PITC_PIMR           EQU (0xFFFFFD30) ;- (PITC) Period Interval Mode Register
+// - ========== Register definition for WDTC peripheral ========== 
+AT91C_WDTC_WDCR           EQU (0xFFFFFD40) ;- (WDTC) Watchdog Control Register
+AT91C_WDTC_WDSR           EQU (0xFFFFFD48) ;- (WDTC) Watchdog Status Register
+AT91C_WDTC_WDMR           EQU (0xFFFFFD44) ;- (WDTC) Watchdog Mode Register
+// - ========== Register definition for VREG peripheral ========== 
+AT91C_VREG_MR             EQU (0xFFFFFD60) ;- (VREG) Voltage Regulator Mode Register
+// - ========== Register definition for MC peripheral ========== 
+AT91C_MC_ASR              EQU (0xFFFFFF04) ;- (MC) MC Abort Status Register
+AT91C_MC_RCR              EQU (0xFFFFFF00) ;- (MC) MC Remap Control Register
+AT91C_MC_FCR              EQU (0xFFFFFF64) ;- (MC) MC Flash Command Register
+AT91C_MC_AASR             EQU (0xFFFFFF08) ;- (MC) MC Abort Address Status Register
+AT91C_MC_FSR              EQU (0xFFFFFF68) ;- (MC) MC Flash Status Register
+AT91C_MC_FMR              EQU (0xFFFFFF60) ;- (MC) MC Flash Mode Register
+// - ========== Register definition for PDC_SPI1 peripheral ========== 
+AT91C_SPI1_PTCR           EQU (0xFFFE4120) ;- (PDC_SPI1) PDC Transfer Control Register
+AT91C_SPI1_RPR            EQU (0xFFFE4100) ;- (PDC_SPI1) Receive Pointer Register
+AT91C_SPI1_TNCR           EQU (0xFFFE411C) ;- (PDC_SPI1) Transmit Next Counter Register
+AT91C_SPI1_TPR            EQU (0xFFFE4108) ;- (PDC_SPI1) Transmit Pointer Register
+AT91C_SPI1_TNPR           EQU (0xFFFE4118) ;- (PDC_SPI1) Transmit Next Pointer Register
+AT91C_SPI1_TCR            EQU (0xFFFE410C) ;- (PDC_SPI1) Transmit Counter Register
+AT91C_SPI1_RCR            EQU (0xFFFE4104) ;- (PDC_SPI1) Receive Counter Register
+AT91C_SPI1_RNPR           EQU (0xFFFE4110) ;- (PDC_SPI1) Receive Next Pointer Register
+AT91C_SPI1_RNCR           EQU (0xFFFE4114) ;- (PDC_SPI1) Receive Next Counter Register
+AT91C_SPI1_PTSR           EQU (0xFFFE4124) ;- (PDC_SPI1) PDC Transfer Status Register
+// - ========== Register definition for SPI1 peripheral ========== 
+AT91C_SPI1_IMR            EQU (0xFFFE401C) ;- (SPI1) Interrupt Mask Register
+AT91C_SPI1_IER            EQU (0xFFFE4014) ;- (SPI1) Interrupt Enable Register
+AT91C_SPI1_MR             EQU (0xFFFE4004) ;- (SPI1) Mode Register
+AT91C_SPI1_RDR            EQU (0xFFFE4008) ;- (SPI1) Receive Data Register
+AT91C_SPI1_IDR            EQU (0xFFFE4018) ;- (SPI1) Interrupt Disable Register
+AT91C_SPI1_SR             EQU (0xFFFE4010) ;- (SPI1) Status Register
+AT91C_SPI1_TDR            EQU (0xFFFE400C) ;- (SPI1) Transmit Data Register
+AT91C_SPI1_CR             EQU (0xFFFE4000) ;- (SPI1) Control Register
+AT91C_SPI1_CSR            EQU (0xFFFE4030) ;- (SPI1) Chip Select Register
+// - ========== Register definition for PDC_SPI0 peripheral ========== 
+AT91C_SPI0_PTCR           EQU (0xFFFE0120) ;- (PDC_SPI0) PDC Transfer Control Register
+AT91C_SPI0_TPR            EQU (0xFFFE0108) ;- (PDC_SPI0) Transmit Pointer Register
+AT91C_SPI0_TCR            EQU (0xFFFE010C) ;- (PDC_SPI0) Transmit Counter Register
+AT91C_SPI0_RCR            EQU (0xFFFE0104) ;- (PDC_SPI0) Receive Counter Register
+AT91C_SPI0_PTSR           EQU (0xFFFE0124) ;- (PDC_SPI0) PDC Transfer Status Register
+AT91C_SPI0_RNPR           EQU (0xFFFE0110) ;- (PDC_SPI0) Receive Next Pointer Register
+AT91C_SPI0_RPR            EQU (0xFFFE0100) ;- (PDC_SPI0) Receive Pointer Register
+AT91C_SPI0_TNCR           EQU (0xFFFE011C) ;- (PDC_SPI0) Transmit Next Counter Register
+AT91C_SPI0_RNCR           EQU (0xFFFE0114) ;- (PDC_SPI0) Receive Next Counter Register
+AT91C_SPI0_TNPR           EQU (0xFFFE0118) ;- (PDC_SPI0) Transmit Next Pointer Register
+// - ========== Register definition for SPI0 peripheral ========== 
+AT91C_SPI0_IER            EQU (0xFFFE0014) ;- (SPI0) Interrupt Enable Register
+AT91C_SPI0_SR             EQU (0xFFFE0010) ;- (SPI0) Status Register
+AT91C_SPI0_IDR            EQU (0xFFFE0018) ;- (SPI0) Interrupt Disable Register
+AT91C_SPI0_CR             EQU (0xFFFE0000) ;- (SPI0) Control Register
+AT91C_SPI0_MR             EQU (0xFFFE0004) ;- (SPI0) Mode Register
+AT91C_SPI0_IMR            EQU (0xFFFE001C) ;- (SPI0) Interrupt Mask Register
+AT91C_SPI0_TDR            EQU (0xFFFE000C) ;- (SPI0) Transmit Data Register
+AT91C_SPI0_RDR            EQU (0xFFFE0008) ;- (SPI0) Receive Data Register
+AT91C_SPI0_CSR            EQU (0xFFFE0030) ;- (SPI0) Chip Select Register
+// - ========== Register definition for PDC_US1 peripheral ========== 
+AT91C_US1_RNCR            EQU (0xFFFC4114) ;- (PDC_US1) Receive Next Counter Register
+AT91C_US1_PTCR            EQU (0xFFFC4120) ;- (PDC_US1) PDC Transfer Control Register
+AT91C_US1_TCR             EQU (0xFFFC410C) ;- (PDC_US1) Transmit Counter Register
+AT91C_US1_PTSR            EQU (0xFFFC4124) ;- (PDC_US1) PDC Transfer Status Register
+AT91C_US1_TNPR            EQU (0xFFFC4118) ;- (PDC_US1) Transmit Next Pointer Register
+AT91C_US1_RCR             EQU (0xFFFC4104) ;- (PDC_US1) Receive Counter Register
+AT91C_US1_RNPR            EQU (0xFFFC4110) ;- (PDC_US1) Receive Next Pointer Register
+AT91C_US1_RPR             EQU (0xFFFC4100) ;- (PDC_US1) Receive Pointer Register
+AT91C_US1_TNCR            EQU (0xFFFC411C) ;- (PDC_US1) Transmit Next Counter Register
+AT91C_US1_TPR             EQU (0xFFFC4108) ;- (PDC_US1) Transmit Pointer Register
+// - ========== Register definition for US1 peripheral ========== 
+AT91C_US1_IF              EQU (0xFFFC404C) ;- (US1) IRDA_FILTER Register
+AT91C_US1_NER             EQU (0xFFFC4044) ;- (US1) Nb Errors Register
+AT91C_US1_RTOR            EQU (0xFFFC4024) ;- (US1) Receiver Time-out Register
+AT91C_US1_CSR             EQU (0xFFFC4014) ;- (US1) Channel Status Register
+AT91C_US1_IDR             EQU (0xFFFC400C) ;- (US1) Interrupt Disable Register
+AT91C_US1_IER             EQU (0xFFFC4008) ;- (US1) Interrupt Enable Register
+AT91C_US1_THR             EQU (0xFFFC401C) ;- (US1) Transmitter Holding Register
+AT91C_US1_TTGR            EQU (0xFFFC4028) ;- (US1) Transmitter Time-guard Register
+AT91C_US1_RHR             EQU (0xFFFC4018) ;- (US1) Receiver Holding Register
+AT91C_US1_BRGR            EQU (0xFFFC4020) ;- (US1) Baud Rate Generator Register
+AT91C_US1_IMR             EQU (0xFFFC4010) ;- (US1) Interrupt Mask Register
+AT91C_US1_FIDI            EQU (0xFFFC4040) ;- (US1) FI_DI_Ratio Register
+AT91C_US1_CR              EQU (0xFFFC4000) ;- (US1) Control Register
+AT91C_US1_MR              EQU (0xFFFC4004) ;- (US1) Mode Register
+// - ========== Register definition for PDC_US0 peripheral ========== 
+AT91C_US0_TNPR            EQU (0xFFFC0118) ;- (PDC_US0) Transmit Next Pointer Register
+AT91C_US0_RNPR            EQU (0xFFFC0110) ;- (PDC_US0) Receive Next Pointer Register
+AT91C_US0_TCR             EQU (0xFFFC010C) ;- (PDC_US0) Transmit Counter Register
+AT91C_US0_PTCR            EQU (0xFFFC0120) ;- (PDC_US0) PDC Transfer Control Register
+AT91C_US0_PTSR            EQU (0xFFFC0124) ;- (PDC_US0) PDC Transfer Status Register
+AT91C_US0_TNCR            EQU (0xFFFC011C) ;- (PDC_US0) Transmit Next Counter Register
+AT91C_US0_TPR             EQU (0xFFFC0108) ;- (PDC_US0) Transmit Pointer Register
+AT91C_US0_RCR             EQU (0xFFFC0104) ;- (PDC_US0) Receive Counter Register
+AT91C_US0_RPR             EQU (0xFFFC0100) ;- (PDC_US0) Receive Pointer Register
+AT91C_US0_RNCR            EQU (0xFFFC0114) ;- (PDC_US0) Receive Next Counter Register
+// - ========== Register definition for US0 peripheral ========== 
+AT91C_US0_BRGR            EQU (0xFFFC0020) ;- (US0) Baud Rate Generator Register
+AT91C_US0_NER             EQU (0xFFFC0044) ;- (US0) Nb Errors Register
+AT91C_US0_CR              EQU (0xFFFC0000) ;- (US0) Control Register
+AT91C_US0_IMR             EQU (0xFFFC0010) ;- (US0) Interrupt Mask Register
+AT91C_US0_FIDI            EQU (0xFFFC0040) ;- (US0) FI_DI_Ratio Register
+AT91C_US0_TTGR            EQU (0xFFFC0028) ;- (US0) Transmitter Time-guard Register
+AT91C_US0_MR              EQU (0xFFFC0004) ;- (US0) Mode Register
+AT91C_US0_RTOR            EQU (0xFFFC0024) ;- (US0) Receiver Time-out Register
+AT91C_US0_CSR             EQU (0xFFFC0014) ;- (US0) Channel Status Register
+AT91C_US0_RHR             EQU (0xFFFC0018) ;- (US0) Receiver Holding Register
+AT91C_US0_IDR             EQU (0xFFFC000C) ;- (US0) Interrupt Disable Register
+AT91C_US0_THR             EQU (0xFFFC001C) ;- (US0) Transmitter Holding Register
+AT91C_US0_IF              EQU (0xFFFC004C) ;- (US0) IRDA_FILTER Register
+AT91C_US0_IER             EQU (0xFFFC0008) ;- (US0) Interrupt Enable Register
+// - ========== Register definition for PDC_SSC peripheral ========== 
+AT91C_SSC_TNCR            EQU (0xFFFD411C) ;- (PDC_SSC) Transmit Next Counter Register
+AT91C_SSC_RPR             EQU (0xFFFD4100) ;- (PDC_SSC) Receive Pointer Register
+AT91C_SSC_RNCR            EQU (0xFFFD4114) ;- (PDC_SSC) Receive Next Counter Register
+AT91C_SSC_TPR             EQU (0xFFFD4108) ;- (PDC_SSC) Transmit Pointer Register
+AT91C_SSC_PTCR            EQU (0xFFFD4120) ;- (PDC_SSC) PDC Transfer Control Register
+AT91C_SSC_TCR             EQU (0xFFFD410C) ;- (PDC_SSC) Transmit Counter Register
+AT91C_SSC_RCR             EQU (0xFFFD4104) ;- (PDC_SSC) Receive Counter Register
+AT91C_SSC_RNPR            EQU (0xFFFD4110) ;- (PDC_SSC) Receive Next Pointer Register
+AT91C_SSC_TNPR            EQU (0xFFFD4118) ;- (PDC_SSC) Transmit Next Pointer Register
+AT91C_SSC_PTSR            EQU (0xFFFD4124) ;- (PDC_SSC) PDC Transfer Status Register
+// - ========== Register definition for SSC peripheral ========== 
+AT91C_SSC_RHR             EQU (0xFFFD4020) ;- (SSC) Receive Holding Register
+AT91C_SSC_RSHR            EQU (0xFFFD4030) ;- (SSC) Receive Sync Holding Register
+AT91C_SSC_TFMR            EQU (0xFFFD401C) ;- (SSC) Transmit Frame Mode Register
+AT91C_SSC_IDR             EQU (0xFFFD4048) ;- (SSC) Interrupt Disable Register
+AT91C_SSC_THR             EQU (0xFFFD4024) ;- (SSC) Transmit Holding Register
+AT91C_SSC_RCMR            EQU (0xFFFD4010) ;- (SSC) Receive Clock ModeRegister
+AT91C_SSC_IER             EQU (0xFFFD4044) ;- (SSC) Interrupt Enable Register
+AT91C_SSC_TSHR            EQU (0xFFFD4034) ;- (SSC) Transmit Sync Holding Register
+AT91C_SSC_SR              EQU (0xFFFD4040) ;- (SSC) Status Register
+AT91C_SSC_CMR             EQU (0xFFFD4004) ;- (SSC) Clock Mode Register
+AT91C_SSC_TCMR            EQU (0xFFFD4018) ;- (SSC) Transmit Clock Mode Register
+AT91C_SSC_CR              EQU (0xFFFD4000) ;- (SSC) Control Register
+AT91C_SSC_IMR             EQU (0xFFFD404C) ;- (SSC) Interrupt Mask Register
+AT91C_SSC_RFMR            EQU (0xFFFD4014) ;- (SSC) Receive Frame Mode Register
+// - ========== Register definition for TWI peripheral ========== 
+AT91C_TWI_IER             EQU (0xFFFB8024) ;- (TWI) Interrupt Enable Register
+AT91C_TWI_CR              EQU (0xFFFB8000) ;- (TWI) Control Register
+AT91C_TWI_SR              EQU (0xFFFB8020) ;- (TWI) Status Register
+AT91C_TWI_IMR             EQU (0xFFFB802C) ;- (TWI) Interrupt Mask Register
+AT91C_TWI_THR             EQU (0xFFFB8034) ;- (TWI) Transmit Holding Register
+AT91C_TWI_IDR             EQU (0xFFFB8028) ;- (TWI) Interrupt Disable Register
+AT91C_TWI_IADR            EQU (0xFFFB800C) ;- (TWI) Internal Address Register
+AT91C_TWI_MMR             EQU (0xFFFB8004) ;- (TWI) Master Mode Register
+AT91C_TWI_CWGR            EQU (0xFFFB8010) ;- (TWI) Clock Waveform Generator Register
+AT91C_TWI_RHR             EQU (0xFFFB8030) ;- (TWI) Receive Holding Register
+// - ========== Register definition for PWMC_CH3 peripheral ========== 
+AT91C_PWMC_CH3_CUPDR      EQU (0xFFFCC270) ;- (PWMC_CH3) Channel Update Register
+AT91C_PWMC_CH3_Reserved   EQU (0xFFFCC274) ;- (PWMC_CH3) Reserved
+AT91C_PWMC_CH3_CPRDR      EQU (0xFFFCC268) ;- (PWMC_CH3) Channel Period Register
+AT91C_PWMC_CH3_CDTYR      EQU (0xFFFCC264) ;- (PWMC_CH3) Channel Duty Cycle Register
+AT91C_PWMC_CH3_CCNTR      EQU (0xFFFCC26C) ;- (PWMC_CH3) Channel Counter Register
+AT91C_PWMC_CH3_CMR        EQU (0xFFFCC260) ;- (PWMC_CH3) Channel Mode Register
+// - ========== Register definition for PWMC_CH2 peripheral ========== 
+AT91C_PWMC_CH2_Reserved   EQU (0xFFFCC254) ;- (PWMC_CH2) Reserved
+AT91C_PWMC_CH2_CMR        EQU (0xFFFCC240) ;- (PWMC_CH2) Channel Mode Register
+AT91C_PWMC_CH2_CCNTR      EQU (0xFFFCC24C) ;- (PWMC_CH2) Channel Counter Register
+AT91C_PWMC_CH2_CPRDR      EQU (0xFFFCC248) ;- (PWMC_CH2) Channel Period Register
+AT91C_PWMC_CH2_CUPDR      EQU (0xFFFCC250) ;- (PWMC_CH2) Channel Update Register
+AT91C_PWMC_CH2_CDTYR      EQU (0xFFFCC244) ;- (PWMC_CH2) Channel Duty Cycle Register
+// - ========== Register definition for PWMC_CH1 peripheral ========== 
+AT91C_PWMC_CH1_Reserved   EQU (0xFFFCC234) ;- (PWMC_CH1) Reserved
+AT91C_PWMC_CH1_CUPDR      EQU (0xFFFCC230) ;- (PWMC_CH1) Channel Update Register
+AT91C_PWMC_CH1_CPRDR      EQU (0xFFFCC228) ;- (PWMC_CH1) Channel Period Register
+AT91C_PWMC_CH1_CCNTR      EQU (0xFFFCC22C) ;- (PWMC_CH1) Channel Counter Register
+AT91C_PWMC_CH1_CDTYR      EQU (0xFFFCC224) ;- (PWMC_CH1) Channel Duty Cycle Register
+AT91C_PWMC_CH1_CMR        EQU (0xFFFCC220) ;- (PWMC_CH1) Channel Mode Register
+// - ========== Register definition for PWMC_CH0 peripheral ========== 
+AT91C_PWMC_CH0_Reserved   EQU (0xFFFCC214) ;- (PWMC_CH0) Reserved
+AT91C_PWMC_CH0_CPRDR      EQU (0xFFFCC208) ;- (PWMC_CH0) Channel Period Register
+AT91C_PWMC_CH0_CDTYR      EQU (0xFFFCC204) ;- (PWMC_CH0) Channel Duty Cycle Register
+AT91C_PWMC_CH0_CMR        EQU (0xFFFCC200) ;- (PWMC_CH0) Channel Mode Register
+AT91C_PWMC_CH0_CUPDR      EQU (0xFFFCC210) ;- (PWMC_CH0) Channel Update Register
+AT91C_PWMC_CH0_CCNTR      EQU (0xFFFCC20C) ;- (PWMC_CH0) Channel Counter Register
+// - ========== Register definition for PWMC peripheral ========== 
+AT91C_PWMC_IDR            EQU (0xFFFCC014) ;- (PWMC) PWMC Interrupt Disable Register
+AT91C_PWMC_DIS            EQU (0xFFFCC008) ;- (PWMC) PWMC Disable Register
+AT91C_PWMC_IER            EQU (0xFFFCC010) ;- (PWMC) PWMC Interrupt Enable Register
+AT91C_PWMC_VR             EQU (0xFFFCC0FC) ;- (PWMC) PWMC Version Register
+AT91C_PWMC_ISR            EQU (0xFFFCC01C) ;- (PWMC) PWMC Interrupt Status Register
+AT91C_PWMC_SR             EQU (0xFFFCC00C) ;- (PWMC) PWMC Status Register
+AT91C_PWMC_IMR            EQU (0xFFFCC018) ;- (PWMC) PWMC Interrupt Mask Register
+AT91C_PWMC_MR             EQU (0xFFFCC000) ;- (PWMC) PWMC Mode Register
+AT91C_PWMC_ENA            EQU (0xFFFCC004) ;- (PWMC) PWMC Enable Register
+// - ========== Register definition for UDP peripheral ========== 
+AT91C_UDP_IMR             EQU (0xFFFB0018) ;- (UDP) Interrupt Mask Register
+AT91C_UDP_FADDR           EQU (0xFFFB0008) ;- (UDP) Function Address Register
+AT91C_UDP_NUM             EQU (0xFFFB0000) ;- (UDP) Frame Number Register
+AT91C_UDP_FDR             EQU (0xFFFB0050) ;- (UDP) Endpoint FIFO Data Register
+AT91C_UDP_ISR             EQU (0xFFFB001C) ;- (UDP) Interrupt Status Register
+AT91C_UDP_CSR             EQU (0xFFFB0030) ;- (UDP) Endpoint Control and Status Register
+AT91C_UDP_IDR             EQU (0xFFFB0014) ;- (UDP) Interrupt Disable Register
+AT91C_UDP_ICR             EQU (0xFFFB0020) ;- (UDP) Interrupt Clear Register
+AT91C_UDP_RSTEP           EQU (0xFFFB0028) ;- (UDP) Reset Endpoint Register
+AT91C_UDP_TXVC            EQU (0xFFFB0074) ;- (UDP) Transceiver Control Register
+AT91C_UDP_GLBSTATE        EQU (0xFFFB0004) ;- (UDP) Global State Register
+AT91C_UDP_IER             EQU (0xFFFB0010) ;- (UDP) Interrupt Enable Register
+// - ========== Register definition for TC0 peripheral ========== 
+AT91C_TC0_SR              EQU (0xFFFA0020) ;- (TC0) Status Register
+AT91C_TC0_RC              EQU (0xFFFA001C) ;- (TC0) Register C
+AT91C_TC0_RB              EQU (0xFFFA0018) ;- (TC0) Register B
+AT91C_TC0_CCR             EQU (0xFFFA0000) ;- (TC0) Channel Control Register
+AT91C_TC0_CMR             EQU (0xFFFA0004) ;- (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
+AT91C_TC0_IER             EQU (0xFFFA0024) ;- (TC0) Interrupt Enable Register
+AT91C_TC0_RA              EQU (0xFFFA0014) ;- (TC0) Register A
+AT91C_TC0_IDR             EQU (0xFFFA0028) ;- (TC0) Interrupt Disable Register
+AT91C_TC0_CV              EQU (0xFFFA0010) ;- (TC0) Counter Value
+AT91C_TC0_IMR             EQU (0xFFFA002C) ;- (TC0) Interrupt Mask Register
+// - ========== Register definition for TC1 peripheral ========== 
+AT91C_TC1_RB              EQU (0xFFFA0058) ;- (TC1) Register B
+AT91C_TC1_CCR             EQU (0xFFFA0040) ;- (TC1) Channel Control Register
+AT91C_TC1_IER             EQU (0xFFFA0064) ;- (TC1) Interrupt Enable Register
+AT91C_TC1_IDR             EQU (0xFFFA0068) ;- (TC1) Interrupt Disable Register
+AT91C_TC1_SR              EQU (0xFFFA0060) ;- (TC1) Status Register
+AT91C_TC1_CMR             EQU (0xFFFA0044) ;- (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
+AT91C_TC1_RA              EQU (0xFFFA0054) ;- (TC1) Register A
+AT91C_TC1_RC              EQU (0xFFFA005C) ;- (TC1) Register C
+AT91C_TC1_IMR             EQU (0xFFFA006C) ;- (TC1) Interrupt Mask Register
+AT91C_TC1_CV              EQU (0xFFFA0050) ;- (TC1) Counter Value
+// - ========== Register definition for TC2 peripheral ========== 
+AT91C_TC2_CMR             EQU (0xFFFA0084) ;- (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
+AT91C_TC2_CCR             EQU (0xFFFA0080) ;- (TC2) Channel Control Register
+AT91C_TC2_CV              EQU (0xFFFA0090) ;- (TC2) Counter Value
+AT91C_TC2_RA              EQU (0xFFFA0094) ;- (TC2) Register A
+AT91C_TC2_RB              EQU (0xFFFA0098) ;- (TC2) Register B
+AT91C_TC2_IDR             EQU (0xFFFA00A8) ;- (TC2) Interrupt Disable Register
+AT91C_TC2_IMR             EQU (0xFFFA00AC) ;- (TC2) Interrupt Mask Register
+AT91C_TC2_RC              EQU (0xFFFA009C) ;- (TC2) Register C
+AT91C_TC2_IER             EQU (0xFFFA00A4) ;- (TC2) Interrupt Enable Register
+AT91C_TC2_SR              EQU (0xFFFA00A0) ;- (TC2) Status Register
+// - ========== Register definition for TCB peripheral ========== 
+AT91C_TCB_BMR             EQU (0xFFFA00C4) ;- (TCB) TC Block Mode Register
+AT91C_TCB_BCR             EQU (0xFFFA00C0) ;- (TCB) TC Block Control Register
+// - ========== Register definition for CAN_MB0 peripheral ========== 
+AT91C_CAN_MB0_MDL         EQU (0xFFFD0214) ;- (CAN_MB0) MailBox Data Low Register
+AT91C_CAN_MB0_MAM         EQU (0xFFFD0204) ;- (CAN_MB0) MailBox Acceptance Mask Register
+AT91C_CAN_MB0_MCR         EQU (0xFFFD021C) ;- (CAN_MB0) MailBox Control Register
+AT91C_CAN_MB0_MID         EQU (0xFFFD0208) ;- (CAN_MB0) MailBox ID Register
+AT91C_CAN_MB0_MSR         EQU (0xFFFD0210) ;- (CAN_MB0) MailBox Status Register
+AT91C_CAN_MB0_MFID        EQU (0xFFFD020C) ;- (CAN_MB0) MailBox Family ID Register
+AT91C_CAN_MB0_MDH         EQU (0xFFFD0218) ;- (CAN_MB0) MailBox Data High Register
+AT91C_CAN_MB0_MMR         EQU (0xFFFD0200) ;- (CAN_MB0) MailBox Mode Register
+// - ========== Register definition for CAN_MB1 peripheral ========== 
+AT91C_CAN_MB1_MDL         EQU (0xFFFD0234) ;- (CAN_MB1) MailBox Data Low Register
+AT91C_CAN_MB1_MID         EQU (0xFFFD0228) ;- (CAN_MB1) MailBox ID Register
+AT91C_CAN_MB1_MMR         EQU (0xFFFD0220) ;- (CAN_MB1) MailBox Mode Register
+AT91C_CAN_MB1_MSR         EQU (0xFFFD0230) ;- (CAN_MB1) MailBox Status Register
+AT91C_CAN_MB1_MAM         EQU (0xFFFD0224) ;- (CAN_MB1) MailBox Acceptance Mask Register
+AT91C_CAN_MB1_MDH         EQU (0xFFFD0238) ;- (CAN_MB1) MailBox Data High Register
+AT91C_CAN_MB1_MCR         EQU (0xFFFD023C) ;- (CAN_MB1) MailBox Control Register
+AT91C_CAN_MB1_MFID        EQU (0xFFFD022C) ;- (CAN_MB1) MailBox Family ID Register
+// - ========== Register definition for CAN_MB2 peripheral ========== 
+AT91C_CAN_MB2_MCR         EQU (0xFFFD025C) ;- (CAN_MB2) MailBox Control Register
+AT91C_CAN_MB2_MDH         EQU (0xFFFD0258) ;- (CAN_MB2) MailBox Data High Register
+AT91C_CAN_MB2_MID         EQU (0xFFFD0248) ;- (CAN_MB2) MailBox ID Register
+AT91C_CAN_MB2_MDL         EQU (0xFFFD0254) ;- (CAN_MB2) MailBox Data Low Register
+AT91C_CAN_MB2_MMR         EQU (0xFFFD0240) ;- (CAN_MB2) MailBox Mode Register
+AT91C_CAN_MB2_MAM         EQU (0xFFFD0244) ;- (CAN_MB2) MailBox Acceptance Mask Register
+AT91C_CAN_MB2_MFID        EQU (0xFFFD024C) ;- (CAN_MB2) MailBox Family ID Register
+AT91C_CAN_MB2_MSR         EQU (0xFFFD0250) ;- (CAN_MB2) MailBox Status Register
+// - ========== Register definition for CAN_MB3 peripheral ========== 
+AT91C_CAN_MB3_MFID        EQU (0xFFFD026C) ;- (CAN_MB3) MailBox Family ID Register
+AT91C_CAN_MB3_MAM         EQU (0xFFFD0264) ;- (CAN_MB3) MailBox Acceptance Mask Register
+AT91C_CAN_MB3_MID         EQU (0xFFFD0268) ;- (CAN_MB3) MailBox ID Register
+AT91C_CAN_MB3_MCR         EQU (0xFFFD027C) ;- (CAN_MB3) MailBox Control Register
+AT91C_CAN_MB3_MMR         EQU (0xFFFD0260) ;- (CAN_MB3) MailBox Mode Register
+AT91C_CAN_MB3_MSR         EQU (0xFFFD0270) ;- (CAN_MB3) MailBox Status Register
+AT91C_CAN_MB3_MDL         EQU (0xFFFD0274) ;- (CAN_MB3) MailBox Data Low Register
+AT91C_CAN_MB3_MDH         EQU (0xFFFD0278) ;- (CAN_MB3) MailBox Data High Register
+// - ========== Register definition for CAN_MB4 peripheral ========== 
+AT91C_CAN_MB4_MID         EQU (0xFFFD0288) ;- (CAN_MB4) MailBox ID Register
+AT91C_CAN_MB4_MMR         EQU (0xFFFD0280) ;- (CAN_MB4) MailBox Mode Register
+AT91C_CAN_MB4_MDH         EQU (0xFFFD0298) ;- (CAN_MB4) MailBox Data High Register
+AT91C_CAN_MB4_MFID        EQU (0xFFFD028C) ;- (CAN_MB4) MailBox Family ID Register
+AT91C_CAN_MB4_MSR         EQU (0xFFFD0290) ;- (CAN_MB4) MailBox Status Register
+AT91C_CAN_MB4_MCR         EQU (0xFFFD029C) ;- (CAN_MB4) MailBox Control Register
+AT91C_CAN_MB4_MDL         EQU (0xFFFD0294) ;- (CAN_MB4) MailBox Data Low Register
+AT91C_CAN_MB4_MAM         EQU (0xFFFD0284) ;- (CAN_MB4) MailBox Acceptance Mask Register
+// - ========== Register definition for CAN_MB5 peripheral ========== 
+AT91C_CAN_MB5_MSR         EQU (0xFFFD02B0) ;- (CAN_MB5) MailBox Status Register
+AT91C_CAN_MB5_MCR         EQU (0xFFFD02BC) ;- (CAN_MB5) MailBox Control Register
+AT91C_CAN_MB5_MFID        EQU (0xFFFD02AC) ;- (CAN_MB5) MailBox Family ID Register
+AT91C_CAN_MB5_MDH         EQU (0xFFFD02B8) ;- (CAN_MB5) MailBox Data High Register
+AT91C_CAN_MB5_MID         EQU (0xFFFD02A8) ;- (CAN_MB5) MailBox ID Register
+AT91C_CAN_MB5_MMR         EQU (0xFFFD02A0) ;- (CAN_MB5) MailBox Mode Register
+AT91C_CAN_MB5_MDL         EQU (0xFFFD02B4) ;- (CAN_MB5) MailBox Data Low Register
+AT91C_CAN_MB5_MAM         EQU (0xFFFD02A4) ;- (CAN_MB5) MailBox Acceptance Mask Register
+// - ========== Register definition for CAN_MB6 peripheral ========== 
+AT91C_CAN_MB6_MFID        EQU (0xFFFD02CC) ;- (CAN_MB6) MailBox Family ID Register
+AT91C_CAN_MB6_MID         EQU (0xFFFD02C8) ;- (CAN_MB6) MailBox ID Register
+AT91C_CAN_MB6_MAM         EQU (0xFFFD02C4) ;- (CAN_MB6) MailBox Acceptance Mask Register
+AT91C_CAN_MB6_MSR         EQU (0xFFFD02D0) ;- (CAN_MB6) MailBox Status Register
+AT91C_CAN_MB6_MDL         EQU (0xFFFD02D4) ;- (CAN_MB6) MailBox Data Low Register
+AT91C_CAN_MB6_MCR         EQU (0xFFFD02DC) ;- (CAN_MB6) MailBox Control Register
+AT91C_CAN_MB6_MDH         EQU (0xFFFD02D8) ;- (CAN_MB6) MailBox Data High Register
+AT91C_CAN_MB6_MMR         EQU (0xFFFD02C0) ;- (CAN_MB6) MailBox Mode Register
+// - ========== Register definition for CAN_MB7 peripheral ========== 
+AT91C_CAN_MB7_MCR         EQU (0xFFFD02FC) ;- (CAN_MB7) MailBox Control Register
+AT91C_CAN_MB7_MDH         EQU (0xFFFD02F8) ;- (CAN_MB7) MailBox Data High Register
+AT91C_CAN_MB7_MFID        EQU (0xFFFD02EC) ;- (CAN_MB7) MailBox Family ID Register
+AT91C_CAN_MB7_MDL         EQU (0xFFFD02F4) ;- (CAN_MB7) MailBox Data Low Register
+AT91C_CAN_MB7_MID         EQU (0xFFFD02E8) ;- (CAN_MB7) MailBox ID Register
+AT91C_CAN_MB7_MMR         EQU (0xFFFD02E0) ;- (CAN_MB7) MailBox Mode Register
+AT91C_CAN_MB7_MAM         EQU (0xFFFD02E4) ;- (CAN_MB7) MailBox Acceptance Mask Register
+AT91C_CAN_MB7_MSR         EQU (0xFFFD02F0) ;- (CAN_MB7) MailBox Status Register
+// - ========== Register definition for CAN peripheral ========== 
+AT91C_CAN_TCR             EQU (0xFFFD0024) ;- (CAN) Transfer Command Register
+AT91C_CAN_IMR             EQU (0xFFFD000C) ;- (CAN) Interrupt Mask Register
+AT91C_CAN_IER             EQU (0xFFFD0004) ;- (CAN) Interrupt Enable Register
+AT91C_CAN_ECR             EQU (0xFFFD0020) ;- (CAN) Error Counter Register
+AT91C_CAN_TIMESTP         EQU (0xFFFD001C) ;- (CAN) Time Stamp Register
+AT91C_CAN_MR              EQU (0xFFFD0000) ;- (CAN) Mode Register
+AT91C_CAN_IDR             EQU (0xFFFD0008) ;- (CAN) Interrupt Disable Register
+AT91C_CAN_ACR             EQU (0xFFFD0028) ;- (CAN) Abort Command Register
+AT91C_CAN_TIM             EQU (0xFFFD0018) ;- (CAN) Timer Register
+AT91C_CAN_SR              EQU (0xFFFD0010) ;- (CAN) Status Register
+AT91C_CAN_BR              EQU (0xFFFD0014) ;- (CAN) Baudrate Register
+AT91C_CAN_VR              EQU (0xFFFD00FC) ;- (CAN) Version Register
+// - ========== Register definition for EMAC peripheral ========== 
+AT91C_EMAC_ISR            EQU (0xFFFDC024) ;- (EMAC) Interrupt Status Register
+AT91C_EMAC_SA4H           EQU (0xFFFDC0B4) ;- (EMAC) Specific Address 4 Top, Last 2 bytes
+AT91C_EMAC_SA1L           EQU (0xFFFDC098) ;- (EMAC) Specific Address 1 Bottom, First 4 bytes
+AT91C_EMAC_ELE            EQU (0xFFFDC078) ;- (EMAC) Excessive Length Errors Register
+AT91C_EMAC_LCOL           EQU (0xFFFDC05C) ;- (EMAC) Late Collision Register
+AT91C_EMAC_RLE            EQU (0xFFFDC088) ;- (EMAC) Receive Length Field Mismatch Register
+AT91C_EMAC_WOL            EQU (0xFFFDC0C4) ;- (EMAC) Wake On LAN Register
+AT91C_EMAC_DTF            EQU (0xFFFDC058) ;- (EMAC) Deferred Transmission Frame Register
+AT91C_EMAC_TUND           EQU (0xFFFDC064) ;- (EMAC) Transmit Underrun Error Register
+AT91C_EMAC_NCR            EQU (0xFFFDC000) ;- (EMAC) Network Control Register
+AT91C_EMAC_SA4L           EQU (0xFFFDC0B0) ;- (EMAC) Specific Address 4 Bottom, First 4 bytes
+AT91C_EMAC_RSR            EQU (0xFFFDC020) ;- (EMAC) Receive Status Register
+AT91C_EMAC_SA3L           EQU (0xFFFDC0A8) ;- (EMAC) Specific Address 3 Bottom, First 4 bytes
+AT91C_EMAC_TSR            EQU (0xFFFDC014) ;- (EMAC) Transmit Status Register
+AT91C_EMAC_IDR            EQU (0xFFFDC02C) ;- (EMAC) Interrupt Disable Register
+AT91C_EMAC_RSE            EQU (0xFFFDC074) ;- (EMAC) Receive Symbol Errors Register
+AT91C_EMAC_ECOL           EQU (0xFFFDC060) ;- (EMAC) Excessive Collision Register
+AT91C_EMAC_TID            EQU (0xFFFDC0B8) ;- (EMAC) Type ID Checking Register
+AT91C_EMAC_HRB            EQU (0xFFFDC090) ;- (EMAC) Hash Address Bottom[31:0]
+AT91C_EMAC_TBQP           EQU (0xFFFDC01C) ;- (EMAC) Transmit Buffer Queue Pointer
+AT91C_EMAC_USRIO          EQU (0xFFFDC0C0) ;- (EMAC) USER Input/Output Register
+AT91C_EMAC_PTR            EQU (0xFFFDC038) ;- (EMAC) Pause Time Register
+AT91C_EMAC_SA2H           EQU (0xFFFDC0A4) ;- (EMAC) Specific Address 2 Top, Last 2 bytes
+AT91C_EMAC_ROV            EQU (0xFFFDC070) ;- (EMAC) Receive Overrun Errors Register
+AT91C_EMAC_ALE            EQU (0xFFFDC054) ;- (EMAC) Alignment Error Register
+AT91C_EMAC_RJA            EQU (0xFFFDC07C) ;- (EMAC) Receive Jabbers Register
+AT91C_EMAC_RBQP           EQU (0xFFFDC018) ;- (EMAC) Receive Buffer Queue Pointer
+AT91C_EMAC_TPF            EQU (0xFFFDC08C) ;- (EMAC) Transmitted Pause Frames Register
+AT91C_EMAC_NCFGR          EQU (0xFFFDC004) ;- (EMAC) Network Configuration Register
+AT91C_EMAC_HRT            EQU (0xFFFDC094) ;- (EMAC) Hash Address Top[63:32]
+AT91C_EMAC_USF            EQU (0xFFFDC080) ;- (EMAC) Undersize Frames Register
+AT91C_EMAC_FCSE           EQU (0xFFFDC050) ;- (EMAC) Frame Check Sequence Error Register
+AT91C_EMAC_TPQ            EQU (0xFFFDC0BC) ;- (EMAC) Transmit Pause Quantum Register
+AT91C_EMAC_MAN            EQU (0xFFFDC034) ;- (EMAC) PHY Maintenance Register
+AT91C_EMAC_FTO            EQU (0xFFFDC040) ;- (EMAC) Frames Transmitted OK Register
+AT91C_EMAC_REV            EQU (0xFFFDC0FC) ;- (EMAC) Revision Register
+AT91C_EMAC_IMR            EQU (0xFFFDC030) ;- (EMAC) Interrupt Mask Register
+AT91C_EMAC_SCF            EQU (0xFFFDC044) ;- (EMAC) Single Collision Frame Register
+AT91C_EMAC_PFR            EQU (0xFFFDC03C) ;- (EMAC) Pause Frames received Register
+AT91C_EMAC_MCF            EQU (0xFFFDC048) ;- (EMAC) Multiple Collision Frame Register
+AT91C_EMAC_NSR            EQU (0xFFFDC008) ;- (EMAC) Network Status Register
+AT91C_EMAC_SA2L           EQU (0xFFFDC0A0) ;- (EMAC) Specific Address 2 Bottom, First 4 bytes
+AT91C_EMAC_FRO            EQU (0xFFFDC04C) ;- (EMAC) Frames Received OK Register
+AT91C_EMAC_IER            EQU (0xFFFDC028) ;- (EMAC) Interrupt Enable Register
+AT91C_EMAC_SA1H           EQU (0xFFFDC09C) ;- (EMAC) Specific Address 1 Top, Last 2 bytes
+AT91C_EMAC_CSE            EQU (0xFFFDC068) ;- (EMAC) Carrier Sense Error Register
+AT91C_EMAC_SA3H           EQU (0xFFFDC0AC) ;- (EMAC) Specific Address 3 Top, Last 2 bytes
+AT91C_EMAC_RRE            EQU (0xFFFDC06C) ;- (EMAC) Receive Ressource Error Register
+AT91C_EMAC_STE            EQU (0xFFFDC084) ;- (EMAC) SQE Test Error Register
+// - ========== Register definition for PDC_ADC peripheral ========== 
+AT91C_ADC_PTSR            EQU (0xFFFD8124) ;- (PDC_ADC) PDC Transfer Status Register
+AT91C_ADC_PTCR            EQU (0xFFFD8120) ;- (PDC_ADC) PDC Transfer Control Register
+AT91C_ADC_TNPR            EQU (0xFFFD8118) ;- (PDC_ADC) Transmit Next Pointer Register
+AT91C_ADC_TNCR            EQU (0xFFFD811C) ;- (PDC_ADC) Transmit Next Counter Register
+AT91C_ADC_RNPR            EQU (0xFFFD8110) ;- (PDC_ADC) Receive Next Pointer Register
+AT91C_ADC_RNCR            EQU (0xFFFD8114) ;- (PDC_ADC) Receive Next Counter Register
+AT91C_ADC_RPR             EQU (0xFFFD8100) ;- (PDC_ADC) Receive Pointer Register
+AT91C_ADC_TCR             EQU (0xFFFD810C) ;- (PDC_ADC) Transmit Counter Register
+AT91C_ADC_TPR             EQU (0xFFFD8108) ;- (PDC_ADC) Transmit Pointer Register
+AT91C_ADC_RCR             EQU (0xFFFD8104) ;- (PDC_ADC) Receive Counter Register
+// - ========== Register definition for ADC peripheral ========== 
+AT91C_ADC_CDR2            EQU (0xFFFD8038) ;- (ADC) ADC Channel Data Register 2
+AT91C_ADC_CDR3            EQU (0xFFFD803C) ;- (ADC) ADC Channel Data Register 3
+AT91C_ADC_CDR0            EQU (0xFFFD8030) ;- (ADC) ADC Channel Data Register 0
+AT91C_ADC_CDR5            EQU (0xFFFD8044) ;- (ADC) ADC Channel Data Register 5
+AT91C_ADC_CHDR            EQU (0xFFFD8014) ;- (ADC) ADC Channel Disable Register
+AT91C_ADC_SR              EQU (0xFFFD801C) ;- (ADC) ADC Status Register
+AT91C_ADC_CDR4            EQU (0xFFFD8040) ;- (ADC) ADC Channel Data Register 4
+AT91C_ADC_CDR1            EQU (0xFFFD8034) ;- (ADC) ADC Channel Data Register 1
+AT91C_ADC_LCDR            EQU (0xFFFD8020) ;- (ADC) ADC Last Converted Data Register
+AT91C_ADC_IDR             EQU (0xFFFD8028) ;- (ADC) ADC Interrupt Disable Register
+AT91C_ADC_CR              EQU (0xFFFD8000) ;- (ADC) ADC Control Register
+AT91C_ADC_CDR7            EQU (0xFFFD804C) ;- (ADC) ADC Channel Data Register 7
+AT91C_ADC_CDR6            EQU (0xFFFD8048) ;- (ADC) ADC Channel Data Register 6
+AT91C_ADC_IER             EQU (0xFFFD8024) ;- (ADC) ADC Interrupt Enable Register
+AT91C_ADC_CHER            EQU (0xFFFD8010) ;- (ADC) ADC Channel Enable Register
+AT91C_ADC_CHSR            EQU (0xFFFD8018) ;- (ADC) ADC Channel Status Register
+AT91C_ADC_MR              EQU (0xFFFD8004) ;- (ADC) ADC Mode Register
+AT91C_ADC_IMR             EQU (0xFFFD802C) ;- (ADC) ADC Interrupt Mask Register
+// - ========== Register definition for PDC_AES peripheral ========== 
+AT91C_AES_TPR             EQU (0xFFFA4108) ;- (PDC_AES) Transmit Pointer Register
+AT91C_AES_PTCR            EQU (0xFFFA4120) ;- (PDC_AES) PDC Transfer Control Register
+AT91C_AES_RNPR            EQU (0xFFFA4110) ;- (PDC_AES) Receive Next Pointer Register
+AT91C_AES_TNCR            EQU (0xFFFA411C) ;- (PDC_AES) Transmit Next Counter Register
+AT91C_AES_TCR             EQU (0xFFFA410C) ;- (PDC_AES) Transmit Counter Register
+AT91C_AES_RCR             EQU (0xFFFA4104) ;- (PDC_AES) Receive Counter Register
+AT91C_AES_RNCR            EQU (0xFFFA4114) ;- (PDC_AES) Receive Next Counter Register
+AT91C_AES_TNPR            EQU (0xFFFA4118) ;- (PDC_AES) Transmit Next Pointer Register
+AT91C_AES_RPR             EQU (0xFFFA4100) ;- (PDC_AES) Receive Pointer Register
+AT91C_AES_PTSR            EQU (0xFFFA4124) ;- (PDC_AES) PDC Transfer Status Register
+// - ========== Register definition for AES peripheral ========== 
+AT91C_AES_IVxR            EQU (0xFFFA4060) ;- (AES) Initialization Vector x Register
+AT91C_AES_MR              EQU (0xFFFA4004) ;- (AES) Mode Register
+AT91C_AES_VR              EQU (0xFFFA40FC) ;- (AES) AES Version Register
+AT91C_AES_ODATAxR         EQU (0xFFFA4050) ;- (AES) Output Data x Register
+AT91C_AES_IDATAxR         EQU (0xFFFA4040) ;- (AES) Input Data x Register
+AT91C_AES_CR              EQU (0xFFFA4000) ;- (AES) Control Register
+AT91C_AES_IDR             EQU (0xFFFA4014) ;- (AES) Interrupt Disable Register
+AT91C_AES_IMR             EQU (0xFFFA4018) ;- (AES) Interrupt Mask Register
+AT91C_AES_IER             EQU (0xFFFA4010) ;- (AES) Interrupt Enable Register
+AT91C_AES_KEYWxR          EQU (0xFFFA4020) ;- (AES) Key Word x Register
+AT91C_AES_ISR             EQU (0xFFFA401C) ;- (AES) Interrupt Status Register
+// - ========== Register definition for PDC_TDES peripheral ========== 
+AT91C_TDES_RNCR           EQU (0xFFFA8114) ;- (PDC_TDES) Receive Next Counter Register
+AT91C_TDES_TCR            EQU (0xFFFA810C) ;- (PDC_TDES) Transmit Counter Register
+AT91C_TDES_RCR            EQU (0xFFFA8104) ;- (PDC_TDES) Receive Counter Register
+AT91C_TDES_TNPR           EQU (0xFFFA8118) ;- (PDC_TDES) Transmit Next Pointer Register
+AT91C_TDES_RNPR           EQU (0xFFFA8110) ;- (PDC_TDES) Receive Next Pointer Register
+AT91C_TDES_RPR            EQU (0xFFFA8100) ;- (PDC_TDES) Receive Pointer Register
+AT91C_TDES_TNCR           EQU (0xFFFA811C) ;- (PDC_TDES) Transmit Next Counter Register
+AT91C_TDES_TPR            EQU (0xFFFA8108) ;- (PDC_TDES) Transmit Pointer Register
+AT91C_TDES_PTSR           EQU (0xFFFA8124) ;- (PDC_TDES) PDC Transfer Status Register
+AT91C_TDES_PTCR           EQU (0xFFFA8120) ;- (PDC_TDES) PDC Transfer Control Register
+// - ========== Register definition for TDES peripheral ========== 
+AT91C_TDES_KEY2WxR        EQU (0xFFFA8028) ;- (TDES) Key 2 Word x Register
+AT91C_TDES_KEY3WxR        EQU (0xFFFA8030) ;- (TDES) Key 3 Word x Register
+AT91C_TDES_IDR            EQU (0xFFFA8014) ;- (TDES) Interrupt Disable Register
+AT91C_TDES_VR             EQU (0xFFFA80FC) ;- (TDES) TDES Version Register
+AT91C_TDES_IVxR           EQU (0xFFFA8060) ;- (TDES) Initialization Vector x Register
+AT91C_TDES_ODATAxR        EQU (0xFFFA8050) ;- (TDES) Output Data x Register
+AT91C_TDES_IMR            EQU (0xFFFA8018) ;- (TDES) Interrupt Mask Register
+AT91C_TDES_MR             EQU (0xFFFA8004) ;- (TDES) Mode Register
+AT91C_TDES_CR             EQU (0xFFFA8000) ;- (TDES) Control Register
+AT91C_TDES_IER            EQU (0xFFFA8010) ;- (TDES) Interrupt Enable Register
+AT91C_TDES_ISR            EQU (0xFFFA801C) ;- (TDES) Interrupt Status Register
+AT91C_TDES_IDATAxR        EQU (0xFFFA8040) ;- (TDES) Input Data x Register
+AT91C_TDES_KEY1WxR        EQU (0xFFFA8020) ;- (TDES) Key 1 Word x Register
+
+// - *****************************************************************************
+// -               PIO DEFINITIONS FOR AT91SAM7X256
+// - *****************************************************************************
+AT91C_PIO_PA0             EQU (1 <<  0) ;- Pin Controlled by PA0
+AT91C_PA0_RXD0            EQU (AT91C_PIO_PA0) ;-  USART 0 Receive Data
+AT91C_PIO_PA1             EQU (1 <<  1) ;- Pin Controlled by PA1
+AT91C_PA1_TXD0            EQU (AT91C_PIO_PA1) ;-  USART 0 Transmit Data
+AT91C_PIO_PA10            EQU (1 << 10) ;- Pin Controlled by PA10
+AT91C_PA10_TWD            EQU (AT91C_PIO_PA10) ;-  TWI Two-wire Serial Data
+AT91C_PIO_PA11            EQU (1 << 11) ;- Pin Controlled by PA11
+AT91C_PA11_TWCK           EQU (AT91C_PIO_PA11) ;-  TWI Two-wire Serial Clock
+AT91C_PIO_PA12            EQU (1 << 12) ;- Pin Controlled by PA12
+AT91C_PA12_NPCS00         EQU (AT91C_PIO_PA12) ;-  SPI 0 Peripheral Chip Select 0
+AT91C_PIO_PA13            EQU (1 << 13) ;- Pin Controlled by PA13
+AT91C_PA13_NPCS01         EQU (AT91C_PIO_PA13) ;-  SPI 0 Peripheral Chip Select 1
+AT91C_PA13_PCK1           EQU (AT91C_PIO_PA13) ;-  PMC Programmable Clock Output 1
+AT91C_PIO_PA14            EQU (1 << 14) ;- Pin Controlled by PA14
+AT91C_PA14_NPCS02         EQU (AT91C_PIO_PA14) ;-  SPI 0 Peripheral Chip Select 2
+AT91C_PA14_IRQ1           EQU (AT91C_PIO_PA14) ;-  External Interrupt 1
+AT91C_PIO_PA15            EQU (1 << 15) ;- Pin Controlled by PA15
+AT91C_PA15_NPCS03         EQU (AT91C_PIO_PA15) ;-  SPI 0 Peripheral Chip Select 3
+AT91C_PA15_TCLK2          EQU (AT91C_PIO_PA15) ;-  Timer Counter 2 external clock input
+AT91C_PIO_PA16            EQU (1 << 16) ;- Pin Controlled by PA16
+AT91C_PA16_MISO0          EQU (AT91C_PIO_PA16) ;-  SPI 0 Master In Slave
+AT91C_PIO_PA17            EQU (1 << 17) ;- Pin Controlled by PA17
+AT91C_PA17_MOSI0          EQU (AT91C_PIO_PA17) ;-  SPI 0 Master Out Slave
+AT91C_PIO_PA18            EQU (1 << 18) ;- Pin Controlled by PA18
+AT91C_PA18_SPCK0          EQU (AT91C_PIO_PA18) ;-  SPI 0 Serial Clock
+AT91C_PIO_PA19            EQU (1 << 19) ;- Pin Controlled by PA19
+AT91C_PA19_CANRX          EQU (AT91C_PIO_PA19) ;-  CAN Receive
+AT91C_PIO_PA2             EQU (1 <<  2) ;- Pin Controlled by PA2
+AT91C_PA2_SCK0            EQU (AT91C_PIO_PA2) ;-  USART 0 Serial Clock
+AT91C_PA2_NPCS11          EQU (AT91C_PIO_PA2) ;-  SPI 1 Peripheral Chip Select 1
+AT91C_PIO_PA20            EQU (1 << 20) ;- Pin Controlled by PA20
+AT91C_PA20_CANTX          EQU (AT91C_PIO_PA20) ;-  CAN Transmit
+AT91C_PIO_PA21            EQU (1 << 21) ;- Pin Controlled by PA21
+AT91C_PA21_TF             EQU (AT91C_PIO_PA21) ;-  SSC Transmit Frame Sync
+AT91C_PA21_NPCS10         EQU (AT91C_PIO_PA21) ;-  SPI 1 Peripheral Chip Select 0
+AT91C_PIO_PA22            EQU (1 << 22) ;- Pin Controlled by PA22
+AT91C_PA22_TK             EQU (AT91C_PIO_PA22) ;-  SSC Transmit Clock
+AT91C_PA22_SPCK1          EQU (AT91C_PIO_PA22) ;-  SPI 1 Serial Clock
+AT91C_PIO_PA23            EQU (1 << 23) ;- Pin Controlled by PA23
+AT91C_PA23_TD             EQU (AT91C_PIO_PA23) ;-  SSC Transmit data
+AT91C_PA23_MOSI1          EQU (AT91C_PIO_PA23) ;-  SPI 1 Master Out Slave
+AT91C_PIO_PA24            EQU (1 << 24) ;- Pin Controlled by PA24
+AT91C_PA24_RD             EQU (AT91C_PIO_PA24) ;-  SSC Receive Data
+AT91C_PA24_MISO1          EQU (AT91C_PIO_PA24) ;-  SPI 1 Master In Slave
+AT91C_PIO_PA25            EQU (1 << 25) ;- Pin Controlled by PA25
+AT91C_PA25_RK             EQU (AT91C_PIO_PA25) ;-  SSC Receive Clock
+AT91C_PA25_NPCS11         EQU (AT91C_PIO_PA25) ;-  SPI 1 Peripheral Chip Select 1
+AT91C_PIO_PA26            EQU (1 << 26) ;- Pin Controlled by PA26
+AT91C_PA26_RF             EQU (AT91C_PIO_PA26) ;-  SSC Receive Frame Sync
+AT91C_PA26_NPCS12         EQU (AT91C_PIO_PA26) ;-  SPI 1 Peripheral Chip Select 2
+AT91C_PIO_PA27            EQU (1 << 27) ;- Pin Controlled by PA27
+AT91C_PA27_DRXD           EQU (AT91C_PIO_PA27) ;-  DBGU Debug Receive Data
+AT91C_PA27_PCK3           EQU (AT91C_PIO_PA27) ;-  PMC Programmable Clock Output 3
+AT91C_PIO_PA28            EQU (1 << 28) ;- Pin Controlled by PA28
+AT91C_PA28_DTXD           EQU (AT91C_PIO_PA28) ;-  DBGU Debug Transmit Data
+AT91C_PIO_PA29            EQU (1 << 29) ;- Pin Controlled by PA29
+AT91C_PA29_FIQ            EQU (AT91C_PIO_PA29) ;-  AIC Fast Interrupt Input
+AT91C_PA29_NPCS13         EQU (AT91C_PIO_PA29) ;-  SPI 1 Peripheral Chip Select 3
+AT91C_PIO_PA3             EQU (1 <<  3) ;- Pin Controlled by PA3
+AT91C_PA3_RTS0            EQU (AT91C_PIO_PA3) ;-  USART 0 Ready To Send
+AT91C_PA3_NPCS12          EQU (AT91C_PIO_PA3) ;-  SPI 1 Peripheral Chip Select 2
+AT91C_PIO_PA30            EQU (1 << 30) ;- Pin Controlled by PA30
+AT91C_PA30_IRQ0           EQU (AT91C_PIO_PA30) ;-  External Interrupt 0
+AT91C_PA30_PCK2           EQU (AT91C_PIO_PA30) ;-  PMC Programmable Clock Output 2
+AT91C_PIO_PA4             EQU (1 <<  4) ;- Pin Controlled by PA4
+AT91C_PA4_CTS0            EQU (AT91C_PIO_PA4) ;-  USART 0 Clear To Send
+AT91C_PA4_NPCS13          EQU (AT91C_PIO_PA4) ;-  SPI 1 Peripheral Chip Select 3
+AT91C_PIO_PA5             EQU (1 <<  5) ;- Pin Controlled by PA5
+AT91C_PA5_RXD1            EQU (AT91C_PIO_PA5) ;-  USART 1 Receive Data
+AT91C_PIO_PA6             EQU (1 <<  6) ;- Pin Controlled by PA6
+AT91C_PA6_TXD1            EQU (AT91C_PIO_PA6) ;-  USART 1 Transmit Data
+AT91C_PIO_PA7             EQU (1 <<  7) ;- Pin Controlled by PA7
+AT91C_PA7_SCK1            EQU (AT91C_PIO_PA7) ;-  USART 1 Serial Clock
+AT91C_PA7_NPCS01          EQU (AT91C_PIO_PA7) ;-  SPI 0 Peripheral Chip Select 1
+AT91C_PIO_PA8             EQU (1 <<  8) ;- Pin Controlled by PA8
+AT91C_PA8_RTS1            EQU (AT91C_PIO_PA8) ;-  USART 1 Ready To Send
+AT91C_PA8_NPCS02          EQU (AT91C_PIO_PA8) ;-  SPI 0 Peripheral Chip Select 2
+AT91C_PIO_PA9             EQU (1 <<  9) ;- Pin Controlled by PA9
+AT91C_PA9_CTS1            EQU (AT91C_PIO_PA9) ;-  USART 1 Clear To Send
+AT91C_PA9_NPCS03          EQU (AT91C_PIO_PA9) ;-  SPI 0 Peripheral Chip Select 3
+AT91C_PIO_PB0             EQU (1 <<  0) ;- Pin Controlled by PB0
+AT91C_PB0_ETXCK_EREFCK    EQU (AT91C_PIO_PB0) ;-  Ethernet MAC Transmit Clock/Reference Clock
+AT91C_PB0_PCK0            EQU (AT91C_PIO_PB0) ;-  PMC Programmable Clock Output 0
+AT91C_PIO_PB1             EQU (1 <<  1) ;- Pin Controlled by PB1
+AT91C_PB1_ETXEN           EQU (AT91C_PIO_PB1) ;-  Ethernet MAC Transmit Enable
+AT91C_PIO_PB10            EQU (1 << 10) ;- Pin Controlled by PB10
+AT91C_PB10_ETX2           EQU (AT91C_PIO_PB10) ;-  Ethernet MAC Transmit Data 2
+AT91C_PB10_NPCS11         EQU (AT91C_PIO_PB10) ;-  SPI 1 Peripheral Chip Select 1
+AT91C_PIO_PB11            EQU (1 << 11) ;- Pin Controlled by PB11
+AT91C_PB11_ETX3           EQU (AT91C_PIO_PB11) ;-  Ethernet MAC Transmit Data 3
+AT91C_PB11_NPCS12         EQU (AT91C_PIO_PB11) ;-  SPI 1 Peripheral Chip Select 2
+AT91C_PIO_PB12            EQU (1 << 12) ;- Pin Controlled by PB12
+AT91C_PB12_ETXER          EQU (AT91C_PIO_PB12) ;-  Ethernet MAC Transmikt Coding Error
+AT91C_PB12_TCLK0          EQU (AT91C_PIO_PB12) ;-  Timer Counter 0 external clock input
+AT91C_PIO_PB13            EQU (1 << 13) ;- Pin Controlled by PB13
+AT91C_PB13_ERX2           EQU (AT91C_PIO_PB13) ;-  Ethernet MAC Receive Data 2
+AT91C_PB13_NPCS01         EQU (AT91C_PIO_PB13) ;-  SPI 0 Peripheral Chip Select 1
+AT91C_PIO_PB14            EQU (1 << 14) ;- Pin Controlled by PB14
+AT91C_PB14_ERX3           EQU (AT91C_PIO_PB14) ;-  Ethernet MAC Receive Data 3
+AT91C_PB14_NPCS02         EQU (AT91C_PIO_PB14) ;-  SPI 0 Peripheral Chip Select 2
+AT91C_PIO_PB15            EQU (1 << 15) ;- Pin Controlled by PB15
+AT91C_PB15_ERXDV          EQU (AT91C_PIO_PB15) ;-  Ethernet MAC Receive Data Valid
+AT91C_PIO_PB16            EQU (1 << 16) ;- Pin Controlled by PB16
+AT91C_PB16_ECOL           EQU (AT91C_PIO_PB16) ;-  Ethernet MAC Collision Detected
+AT91C_PB16_NPCS13         EQU (AT91C_PIO_PB16) ;-  SPI 1 Peripheral Chip Select 3
+AT91C_PIO_PB17            EQU (1 << 17) ;- Pin Controlled by PB17
+AT91C_PB17_ERXCK          EQU (AT91C_PIO_PB17) ;-  Ethernet MAC Receive Clock
+AT91C_PB17_NPCS03         EQU (AT91C_PIO_PB17) ;-  SPI 0 Peripheral Chip Select 3
+AT91C_PIO_PB18            EQU (1 << 18) ;- Pin Controlled by PB18
+AT91C_PB18_EF100          EQU (AT91C_PIO_PB18) ;-  Ethernet MAC Force 100 Mbits/sec
+AT91C_PB18_ADTRG          EQU (AT91C_PIO_PB18) ;-  ADC External Trigger
+AT91C_PIO_PB19            EQU (1 << 19) ;- Pin Controlled by PB19
+AT91C_PB19_PWM0           EQU (AT91C_PIO_PB19) ;-  PWM Channel 0
+AT91C_PB19_TCLK1          EQU (AT91C_PIO_PB19) ;-  Timer Counter 1 external clock input
+AT91C_PIO_PB2             EQU (1 <<  2) ;- Pin Controlled by PB2
+AT91C_PB2_ETX0            EQU (AT91C_PIO_PB2) ;-  Ethernet MAC Transmit Data 0
+AT91C_PIO_PB20            EQU (1 << 20) ;- Pin Controlled by PB20
+AT91C_PB20_PWM1           EQU (AT91C_PIO_PB20) ;-  PWM Channel 1
+AT91C_PB20_PCK0           EQU (AT91C_PIO_PB20) ;-  PMC Programmable Clock Output 0
+AT91C_PIO_PB21            EQU (1 << 21) ;- Pin Controlled by PB21
+AT91C_PB21_PWM2           EQU (AT91C_PIO_PB21) ;-  PWM Channel 2
+AT91C_PB21_PCK1           EQU (AT91C_PIO_PB21) ;-  PMC Programmable Clock Output 1
+AT91C_PIO_PB22            EQU (1 << 22) ;- Pin Controlled by PB22
+AT91C_PB22_PWM3           EQU (AT91C_PIO_PB22) ;-  PWM Channel 3
+AT91C_PB22_PCK2           EQU (AT91C_PIO_PB22) ;-  PMC Programmable Clock Output 2
+AT91C_PIO_PB23            EQU (1 << 23) ;- Pin Controlled by PB23
+AT91C_PB23_TIOA0          EQU (AT91C_PIO_PB23) ;-  Timer Counter 0 Multipurpose Timer I/O Pin A
+AT91C_PB23_DCD1           EQU (AT91C_PIO_PB23) ;-  USART 1 Data Carrier Detect
+AT91C_PIO_PB24            EQU (1 << 24) ;- Pin Controlled by PB24
+AT91C_PB24_TIOB0          EQU (AT91C_PIO_PB24) ;-  Timer Counter 0 Multipurpose Timer I/O Pin B
+AT91C_PB24_DSR1           EQU (AT91C_PIO_PB24) ;-  USART 1 Data Set ready
+AT91C_PIO_PB25            EQU (1 << 25) ;- Pin Controlled by PB25
+AT91C_PB25_TIOA1          EQU (AT91C_PIO_PB25) ;-  Timer Counter 1 Multipurpose Timer I/O Pin A
+AT91C_PB25_DTR1           EQU (AT91C_PIO_PB25) ;-  USART 1 Data Terminal ready
+AT91C_PIO_PB26            EQU (1 << 26) ;- Pin Controlled by PB26
+AT91C_PB26_TIOB1          EQU (AT91C_PIO_PB26) ;-  Timer Counter 1 Multipurpose Timer I/O Pin B
+AT91C_PB26_RI1            EQU (AT91C_PIO_PB26) ;-  USART 1 Ring Indicator
+AT91C_PIO_PB27            EQU (1 << 27) ;- Pin Controlled by PB27
+AT91C_PB27_TIOA2          EQU (AT91C_PIO_PB27) ;-  Timer Counter 2 Multipurpose Timer I/O Pin A
+AT91C_PB27_PWM0           EQU (AT91C_PIO_PB27) ;-  PWM Channel 0
+AT91C_PIO_PB28            EQU (1 << 28) ;- Pin Controlled by PB28
+AT91C_PB28_TIOB2          EQU (AT91C_PIO_PB28) ;-  Timer Counter 2 Multipurpose Timer I/O Pin B
+AT91C_PB28_PWM1           EQU (AT91C_PIO_PB28) ;-  PWM Channel 1
+AT91C_PIO_PB29            EQU (1 << 29) ;- Pin Controlled by PB29
+AT91C_PB29_PCK1           EQU (AT91C_PIO_PB29) ;-  PMC Programmable Clock Output 1
+AT91C_PB29_PWM2           EQU (AT91C_PIO_PB29) ;-  PWM Channel 2
+AT91C_PIO_PB3             EQU (1 <<  3) ;- Pin Controlled by PB3
+AT91C_PB3_ETX1            EQU (AT91C_PIO_PB3) ;-  Ethernet MAC Transmit Data 1
+AT91C_PIO_PB30            EQU (1 << 30) ;- Pin Controlled by PB30
+AT91C_PB30_PCK2           EQU (AT91C_PIO_PB30) ;-  PMC Programmable Clock Output 2
+AT91C_PB30_PWM3           EQU (AT91C_PIO_PB30) ;-  PWM Channel 3
+AT91C_PIO_PB4             EQU (1 <<  4) ;- Pin Controlled by PB4
+AT91C_PB4_ECRS_ECRSDV     EQU (AT91C_PIO_PB4) ;-  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
+AT91C_PIO_PB5             EQU (1 <<  5) ;- Pin Controlled by PB5
+AT91C_PB5_ERX0            EQU (AT91C_PIO_PB5) ;-  Ethernet MAC Receive Data 0
+AT91C_PIO_PB6             EQU (1 <<  6) ;- Pin Controlled by PB6
+AT91C_PB6_ERX1            EQU (AT91C_PIO_PB6) ;-  Ethernet MAC Receive Data 1
+AT91C_PIO_PB7             EQU (1 <<  7) ;- Pin Controlled by PB7
+AT91C_PB7_ERXER           EQU (AT91C_PIO_PB7) ;-  Ethernet MAC Receive Error
+AT91C_PIO_PB8             EQU (1 <<  8) ;- Pin Controlled by PB8
+AT91C_PB8_EMDC            EQU (AT91C_PIO_PB8) ;-  Ethernet MAC Management Data Clock
+AT91C_PIO_PB9             EQU (1 <<  9) ;- Pin Controlled by PB9
+AT91C_PB9_EMDIO           EQU (AT91C_PIO_PB9) ;-  Ethernet MAC Management Data Input/Output
+
+// - *****************************************************************************
+// -               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256
+// - *****************************************************************************
+AT91C_ID_FIQ              EQU ( 0) ;- Advanced Interrupt Controller (FIQ)
+AT91C_ID_SYS              EQU ( 1) ;- System Peripheral
+AT91C_ID_PIOA             EQU ( 2) ;- Parallel IO Controller A
+AT91C_ID_PIOB             EQU ( 3) ;- Parallel IO Controller B
+AT91C_ID_SPI0             EQU ( 4) ;- Serial Peripheral Interface 0
+AT91C_ID_SPI1             EQU ( 5) ;- Serial Peripheral Interface 1
+AT91C_ID_US0              EQU ( 6) ;- USART 0
+AT91C_ID_US1              EQU ( 7) ;- USART 1
+AT91C_ID_SSC              EQU ( 8) ;- Serial Synchronous Controller
+AT91C_ID_TWI              EQU ( 9) ;- Two-Wire Interface
+AT91C_ID_PWMC             EQU (10) ;- PWM Controller
+AT91C_ID_UDP              EQU (11) ;- USB Device Port
+AT91C_ID_TC0              EQU (12) ;- Timer Counter 0
+AT91C_ID_TC1              EQU (13) ;- Timer Counter 1
+AT91C_ID_TC2              EQU (14) ;- Timer Counter 2
+AT91C_ID_CAN              EQU (15) ;- Control Area Network Controller
+AT91C_ID_EMAC             EQU (16) ;- Ethernet MAC
+AT91C_ID_ADC              EQU (17) ;- Analog-to-Digital Converter
+AT91C_ID_AES              EQU (18) ;- Advanced Encryption Standard 128-bit
+AT91C_ID_TDES             EQU (19) ;- Triple Data Encryption Standard
+AT91C_ID_20_Reserved      EQU (20) ;- Reserved
+AT91C_ID_21_Reserved      EQU (21) ;- Reserved
+AT91C_ID_22_Reserved      EQU (22) ;- Reserved
+AT91C_ID_23_Reserved      EQU (23) ;- Reserved
+AT91C_ID_24_Reserved      EQU (24) ;- Reserved
+AT91C_ID_25_Reserved      EQU (25) ;- Reserved
+AT91C_ID_26_Reserved      EQU (26) ;- Reserved
+AT91C_ID_27_Reserved      EQU (27) ;- Reserved
+AT91C_ID_28_Reserved      EQU (28) ;- Reserved
+AT91C_ID_29_Reserved      EQU (29) ;- Reserved
+AT91C_ID_IRQ0             EQU (30) ;- Advanced Interrupt Controller (IRQ0)
+AT91C_ID_IRQ1             EQU (31) ;- Advanced Interrupt Controller (IRQ1)
+
+// - *****************************************************************************
+// -               BASE ADDRESS DEFINITIONS FOR AT91SAM7X256
+// - *****************************************************************************
+AT91C_BASE_SYS            EQU (0xFFFFF000) ;- (SYS) Base Address
+AT91C_BASE_AIC            EQU (0xFFFFF000) ;- (AIC) Base Address
+AT91C_BASE_PDC_DBGU       EQU (0xFFFFF300) ;- (PDC_DBGU) Base Address
+AT91C_BASE_DBGU           EQU (0xFFFFF200) ;- (DBGU) Base Address
+AT91C_BASE_PIOA           EQU (0xFFFFF400) ;- (PIOA) Base Address
+AT91C_BASE_PIOB           EQU (0xFFFFF600) ;- (PIOB) Base Address
+AT91C_BASE_CKGR           EQU (0xFFFFFC20) ;- (CKGR) Base Address
+AT91C_BASE_PMC            EQU (0xFFFFFC00) ;- (PMC) Base Address
+AT91C_BASE_RSTC           EQU (0xFFFFFD00) ;- (RSTC) Base Address
+AT91C_BASE_RTTC           EQU (0xFFFFFD20) ;- (RTTC) Base Address
+AT91C_BASE_PITC           EQU (0xFFFFFD30) ;- (PITC) Base Address
+AT91C_BASE_WDTC           EQU (0xFFFFFD40) ;- (WDTC) Base Address
+AT91C_BASE_VREG           EQU (0xFFFFFD60) ;- (VREG) Base Address
+AT91C_BASE_MC             EQU (0xFFFFFF00) ;- (MC) Base Address
+AT91C_BASE_PDC_SPI1       EQU (0xFFFE4100) ;- (PDC_SPI1) Base Address
+AT91C_BASE_SPI1           EQU (0xFFFE4000) ;- (SPI1) Base Address
+AT91C_BASE_PDC_SPI0       EQU (0xFFFE0100) ;- (PDC_SPI0) Base Address
+AT91C_BASE_SPI0           EQU (0xFFFE0000) ;- (SPI0) Base Address
+AT91C_BASE_PDC_US1        EQU (0xFFFC4100) ;- (PDC_US1) Base Address
+AT91C_BASE_US1            EQU (0xFFFC4000) ;- (US1) Base Address
+AT91C_BASE_PDC_US0        EQU (0xFFFC0100) ;- (PDC_US0) Base Address
+AT91C_BASE_US0            EQU (0xFFFC0000) ;- (US0) Base Address
+AT91C_BASE_PDC_SSC        EQU (0xFFFD4100) ;- (PDC_SSC) Base Address
+AT91C_BASE_SSC            EQU (0xFFFD4000) ;- (SSC) Base Address
+AT91C_BASE_TWI            EQU (0xFFFB8000) ;- (TWI) Base Address
+AT91C_BASE_PWMC_CH3       EQU (0xFFFCC260) ;- (PWMC_CH3) Base Address
+AT91C_BASE_PWMC_CH2       EQU (0xFFFCC240) ;- (PWMC_CH2) Base Address
+AT91C_BASE_PWMC_CH1       EQU (0xFFFCC220) ;- (PWMC_CH1) Base Address
+AT91C_BASE_PWMC_CH0       EQU (0xFFFCC200) ;- (PWMC_CH0) Base Address
+AT91C_BASE_PWMC           EQU (0xFFFCC000) ;- (PWMC) Base Address
+AT91C_BASE_UDP            EQU (0xFFFB0000) ;- (UDP) Base Address
+AT91C_BASE_TC0            EQU (0xFFFA0000) ;- (TC0) Base Address
+AT91C_BASE_TC1            EQU (0xFFFA0040) ;- (TC1) Base Address
+AT91C_BASE_TC2            EQU (0xFFFA0080) ;- (TC2) Base Address
+AT91C_BASE_TCB            EQU (0xFFFA0000) ;- (TCB) Base Address
+AT91C_BASE_CAN_MB0        EQU (0xFFFD0200) ;- (CAN_MB0) Base Address
+AT91C_BASE_CAN_MB1        EQU (0xFFFD0220) ;- (CAN_MB1) Base Address
+AT91C_BASE_CAN_MB2        EQU (0xFFFD0240) ;- (CAN_MB2) Base Address
+AT91C_BASE_CAN_MB3        EQU (0xFFFD0260) ;- (CAN_MB3) Base Address
+AT91C_BASE_CAN_MB4        EQU (0xFFFD0280) ;- (CAN_MB4) Base Address
+AT91C_BASE_CAN_MB5        EQU (0xFFFD02A0) ;- (CAN_MB5) Base Address
+AT91C_BASE_CAN_MB6        EQU (0xFFFD02C0) ;- (CAN_MB6) Base Address
+AT91C_BASE_CAN_MB7        EQU (0xFFFD02E0) ;- (CAN_MB7) Base Address
+AT91C_BASE_CAN            EQU (0xFFFD0000) ;- (CAN) Base Address
+AT91C_BASE_EMAC           EQU (0xFFFDC000) ;- (EMAC) Base Address
+AT91C_BASE_PDC_ADC        EQU (0xFFFD8100) ;- (PDC_ADC) Base Address
+AT91C_BASE_ADC            EQU (0xFFFD8000) ;- (ADC) Base Address
+AT91C_BASE_PDC_AES        EQU (0xFFFA4100) ;- (PDC_AES) Base Address
+AT91C_BASE_AES            EQU (0xFFFA4000) ;- (AES) Base Address
+AT91C_BASE_PDC_TDES       EQU (0xFFFA8100) ;- (PDC_TDES) Base Address
+AT91C_BASE_TDES           EQU (0xFFFA8000) ;- (TDES) Base Address
+
+// - *****************************************************************************
+// -               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256
+// - *****************************************************************************
+AT91C_ISRAM               EQU (0x00200000) ;- Internal SRAM base address
+AT91C_ISRAM_SIZE          EQU (0x00010000) ;- Internal SRAM size in byte (64 Kbyte)
+AT91C_IFLASH              EQU (0x00100000) ;- Internal ROM base address
+AT91C_IFLASH_SIZE         EQU (0x00040000) ;- Internal ROM size in byte (256 Kbyte)
+#endif /* __IAR_SYSTEMS_ASM__ */
+
+
+#endif /* AT91SAM7X256_H */
diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/SrcIAR/mii.h b/20080212/Demo/uIP_Demo_IAR_ARM7/SrcIAR/mii.h
new file mode 100644
index 000000000..29b2f53d5
--- /dev/null
+++ b/20080212/Demo/uIP_Demo_IAR_ARM7/SrcIAR/mii.h
@@ -0,0 +1,105 @@
+/* Generic MII registers. */
+
+#define MII_BMCR            0x00        /* Basic mode control register */
+#define MII_BMSR            0x01        /* Basic mode status register  */
+#define MII_PHYSID1         0x02        /* PHYS ID 1                   */
+#define MII_PHYSID2         0x03        /* PHYS ID 2                   */
+#define MII_ADVERTISE       0x04        /* Advertisement control reg   */
+#define MII_LPA             0x05        /* Link partner ability reg    */
+#define MII_EXPANSION       0x06        /* Expansion register          */
+#define MII_DCOUNTER        0x12        /* Disconnect counter          */
+#define MII_FCSCOUNTER      0x13        /* False carrier counter       */
+#define MII_NWAYTEST        0x14        /* N-way auto-neg test reg     */
+#define MII_RERRCOUNTER     0x15        /* Receive error counter       */
+#define MII_SREVISION       0x16        /* Silicon revision            */
+#define MII_RESV1           0x17        /* Reserved...                 */
+#define MII_LBRERROR        0x18        /* Lpback, rx, bypass error    */
+#define MII_PHYADDR         0x19        /* PHY address                 */
+#define MII_RESV2           0x1a        /* Reserved...                 */
+#define MII_TPISTATUS       0x1b        /* TPI status for 10mbps       */
+#define MII_NCONFIG         0x1c        /* Network interface config    */
+
+/* Basic mode control register. */
+#define BMCR_RESV               0x007f  /* Unused...                   */
+#define BMCR_CTST               0x0080  /* Collision test              */
+#define BMCR_FULLDPLX           0x0100  /* Full duplex                 */
+#define BMCR_ANRESTART          0x0200  /* Auto negotiation restart    */
+#define BMCR_ISOLATE            0x0400  /* Disconnect DP83840 from MII */
+#define BMCR_PDOWN              0x0800  /* Powerdown the DP83840       */
+#define BMCR_ANENABLE           0x1000  /* Enable auto negotiation     */
+#define BMCR_SPEED100           0x2000  /* Select 100Mbps              */
+#define BMCR_LOOPBACK           0x4000  /* TXD loopback bits           */
+#define BMCR_RESET              0x8000  /* Reset the DP83840           */
+
+/* Basic mode status register. */
+#define BMSR_ERCAP              0x0001  /* Ext-reg capability          */
+#define BMSR_JCD                0x0002  /* Jabber detected             */
+#define BMSR_LSTATUS            0x0004  /* Link status                 */
+#define BMSR_ANEGCAPABLE        0x0008  /* Able to do auto-negotiation */
+#define BMSR_RFAULT             0x0010  /* Remote fault detected       */
+#define BMSR_ANEGCOMPLETE       0x0020  /* Auto-negotiation complete   */
+#define BMSR_RESV               0x07c0  /* Unused...                   */
+#define BMSR_10HALF             0x0800  /* Can do 10mbps, half-duplex  */
+#define BMSR_10FULL             0x1000  /* Can do 10mbps, full-duplex  */
+#define BMSR_100HALF            0x2000  /* Can do 100mbps, half-duplex */
+#define BMSR_100FULL            0x4000  /* Can do 100mbps, full-duplex */
+#define BMSR_100BASE4           0x8000  /* Can do 100mbps, 4k packets  */
+
+/* Advertisement control register. */
+#define ADVERTISE_SLCT          0x001f  /* Selector bits               */
+#define ADVERTISE_CSMA          0x0001  /* Only selector supported     */
+#define ADVERTISE_10HALF        0x0020  /* Try for 10mbps half-duplex  */
+#define ADVERTISE_10FULL        0x0040  /* Try for 10mbps full-duplex  */
+#define ADVERTISE_100HALF       0x0080  /* Try for 100mbps half-duplex */
+#define ADVERTISE_100FULL       0x0100  /* Try for 100mbps full-duplex */
+#define ADVERTISE_100BASE4      0x0200  /* Try for 100mbps 4k packets  */
+#define ADVERTISE_RESV          0x1c00  /* Unused...                   */
+#define ADVERTISE_RFAULT        0x2000  /* Say we can detect faults    */
+#define ADVERTISE_LPACK         0x4000  /* Ack link partners response  */
+#define ADVERTISE_NPAGE         0x8000  /* Next page bit               */
+
+#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
+			ADVERTISE_CSMA)
+#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
+                       ADVERTISE_100HALF | ADVERTISE_100FULL)
+
+/* Link partner ability register. */
+#define LPA_SLCT                0x001f  /* Same as advertise selector  */
+#define LPA_10HALF              0x0020  /* Can do 10mbps half-duplex   */
+#define LPA_10FULL              0x0040  /* Can do 10mbps full-duplex   */
+#define LPA_100HALF             0x0080  /* Can do 100mbps half-duplex  */
+#define LPA_100FULL             0x0100  /* Can do 100mbps full-duplex  */
+#define LPA_100BASE4            0x0200  /* Can do 100mbps 4k packets   */
+#define LPA_RESV                0x1c00  /* Unused...                   */
+#define LPA_RFAULT              0x2000  /* Link partner faulted        */
+#define LPA_LPACK               0x4000  /* Link partner acked us       */
+#define LPA_NPAGE               0x8000  /* Next page bit               */
+
+#define LPA_DUPLEX		(LPA_10FULL | LPA_100FULL)
+#define LPA_100			(LPA_100FULL | LPA_100HALF | LPA_100BASE4)
+
+/* Expansion register for auto-negotiation. */
+#define EXPANSION_NWAY          0x0001  /* Can do N-way auto-nego      */
+#define EXPANSION_LCWP          0x0002  /* Got new RX page code word   */
+#define EXPANSION_ENABLENPAGE   0x0004  /* This enables npage words    */
+#define EXPANSION_NPCAPABLE     0x0008  /* Link partner supports npage */
+#define EXPANSION_MFAULTS       0x0010  /* Multiple faults detected    */
+#define EXPANSION_RESV          0xffe0  /* Unused...                   */
+
+/* N-way test register. */
+#define NWAYTEST_RESV1          0x00ff  /* Unused...                   */
+#define NWAYTEST_LOOPBACK       0x0100  /* Enable loopback for N-way   */
+#define NWAYTEST_RESV2          0xfe00  /* Unused...                   */
+
+#define SPEED_10				10
+#define SPEED_100				100
+
+/* Duplex, half or full. */
+#define DUPLEX_HALF				0x00
+#define DUPLEX_FULL				0x01
+
+/* PHY ID */
+#define MII_DM9161_ID     0x0181b8a0
+#define MII_AM79C875_ID   0x00225540	/* 0x00225541 */
+
+#define AT91C_PHY_ADDR	31
diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/main.c b/20080212/Demo/uIP_Demo_IAR_ARM7/main.c
new file mode 100644
index 000000000..1004f78e1
--- /dev/null
+++ b/20080212/Demo/uIP_Demo_IAR_ARM7/main.c
@@ -0,0 +1,262 @@
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
+
+/*
+ * Creates all the application tasks, then starts the scheduler.
+ *
+ * A task is also created called "uIP".  This executes the uIP stack and small
+ * WEB server sample.  All the other tasks are from the set of standard
+ * demo tasks.  The WEB documentation provides more details of the standard
+ * demo application tasks.
+ *
+ * Main.c also creates a task called "Check".  This only executes every three
+ * seconds but has the highest priority so is guaranteed to get processor time.
+ * Its main function is to check the status of all the other demo application
+ * tasks.  LED mainCHECK_LED is toggled every three seconds by the check task
+ * should no error conditions be detected in any of the standard demo tasks.
+ * The toggle rate increasing to 500ms indicates that at least one error has
+ * been detected.
+ */
+
+
+/* Standard includes. */
+#include 
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Demo application includes. */
+#include "partest.h"
+#include "PollQ.h"
+#include "dynamic.h"
+#include "semtest.h"
+#include "flash.h"
+#include "integer.h"
+#include "flop.h"
+#include "BlockQ.h"
+#include "death.h"
+#include "uip_task.h"
+
+/*-----------------------------------------------------------*/
+
+/* Priorities/stacks for the demo application tasks. */
+#define mainQUEUE_POLL_PRIORITY		( tskIDLE_PRIORITY + 1 )
+#define mainCHECK_TASK_PRIORITY		( tskIDLE_PRIORITY + 3 )
+#define mainSEM_TEST_PRIORITY		( tskIDLE_PRIORITY + 1 )
+#define mainUIP_PRIORITY			( tskIDLE_PRIORITY + 3 )
+#define mainFLASH_PRIORITY			( tskIDLE_PRIORITY + 2 )
+#define mainBLOCK_Q_PRIORITY		( tskIDLE_PRIORITY + 1 )
+#define mainDEATH_PRIORITY			( tskIDLE_PRIORITY + 2 )
+#define mainUIP_TASK_STACK_SIZE		( 250 )
+
+/* The rate at which the on board LED will toggle when there is/is not an
+error. */
+#define mainNO_ERROR_FLASH_PERIOD	( ( portTickType ) 3000 / portTICK_RATE_MS  )
+#define mainERROR_FLASH_PERIOD		( ( portTickType ) 500 / portTICK_RATE_MS  )
+
+/* The LED used by the check task to indicate the system status. */
+#define mainCHECK_LED 				( 3 )
+/*-----------------------------------------------------------*/
+
+/*
+ * Checks that all the demo application tasks are still executing without error
+ * - as described at the top of the file.
+ */
+static portLONG prvCheckOtherTasksAreStillRunning( void );
+
+/*
+ * The task that executes at the highest priority and calls
+ * prvCheckOtherTasksAreStillRunning().  See the description at the top
+ * of the file.
+ */
+static void vErrorChecks( void *pvParameters );
+
+/*
+ * Configure the processor for use with the Atmel demo board.  This is very
+ * minimal as most of the setup is performed in the startup code.
+ */
+static void prvSetupHardware( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Starts all the other tasks, then starts the scheduler.
+ */
+int main( void )
+{
+	/* Configure the processor. */
+	prvSetupHardware();
+
+	/* Setup the port used to flash the LED's. */
+	vParTestInitialise();
+
+	/* Start the task that handles the TCP/IP and WEB server functionality. */
+    xTaskCreate( vuIP_TASK, "uIP", mainUIP_TASK_STACK_SIZE, NULL, mainUIP_PRIORITY, NULL );
+	
+	/* Start the demo/test application tasks.  These are created in addition
+	to the TCP/IP task for demonstration and test purposes. */
+	vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
+	vStartDynamicPriorityTasks();
+	vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
+	vStartLEDFlashTasks( mainFLASH_PRIORITY );
+	vStartIntegerMathTasks( tskIDLE_PRIORITY );
+	vStartMathTasks( tskIDLE_PRIORITY );
+	vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
+
+	/* Start the check task - which is defined in this file. */	
+    xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
+
+	/* Must be last to get created. */
+	vCreateSuicidalTasks( mainDEATH_PRIORITY );
+
+	/* Now all the tasks have been started - start the scheduler. */
+	vTaskStartScheduler();
+
+	/* Should never reach here because the tasks should now be executing! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupHardware( void )
+{
+	/* When using the JTAG debugger the hardware is not always initialised to
+	the correct default state.  This line just ensures that this does not
+	cause all interrupts to be masked at the start. */
+	AT91C_BASE_AIC->AIC_EOICR = 0;
+	
+	/* Most setup is performed by the low level init function called from the
+	startup asm file.
+
+	Configure the PIO Lines corresponding to LED1 to LED4 to be outputs as
+	well as the UART Tx line. */
+	AT91F_PIO_CfgOutput( AT91C_BASE_PIOB, LED_MASK );
+
+	/* Enable the peripheral clock. */
+	AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, 1 << AT91C_ID_PIOA );
+	AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, 1 << AT91C_ID_PIOB ) ;
+	AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, 1 << AT91C_ID_EMAC ) ;
+}
+/*-----------------------------------------------------------*/
+
+static void vErrorChecks( void *pvParameters )
+{
+portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD;
+portTickType xLastWakeTime;
+
+	/* Initialise xLastWakeTime to ensure the first call to vTaskDelayUntil()
+	functions correctly. */
+	xLastWakeTime = xTaskGetTickCount();
+
+	/* Cycle for ever, delaying then checking all the other tasks are still
+	operating without error.  If an error is detected then the delay period
+	is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so
+	the Check LED flash rate will increase. */
+	for( ;; )
+	{
+		/* Delay until it is time to execute again.  The delay period is
+		shorter following an error. */
+		vTaskDelayUntil( &xLastWakeTime, xDelayPeriod );
+	
+		/* Check all the standard demo application tasks are executing without
+		error.  */
+		if( prvCheckOtherTasksAreStillRunning() != pdPASS )
+		{
+			/* An error has been detected in one of the tasks - flash faster. */
+			xDelayPeriod = mainERROR_FLASH_PERIOD;
+		}
+
+		vParTestToggleLED( mainCHECK_LED );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static portLONG prvCheckOtherTasksAreStillRunning( void )
+{
+portLONG lReturn = ( portLONG ) pdPASS;
+
+
+	/* Check all the demo tasks (other than the flash tasks) to ensure
+	that they are all still running, and that none of them have detected
+	an error. */
+
+	if( xArePollingQueuesStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	if( xAreSemaphoreTasksStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	if( xAreMathsTaskStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	if( xAreBlockingQueuesStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	if( xIsCreateTaskStillRunning() != pdTRUE )
+	{
+		lReturn = ( portLONG ) pdFAIL;
+	}
+
+	return lReturn;
+}
+
+
+
diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/resource/SAM7.mac b/20080212/Demo/uIP_Demo_IAR_ARM7/resource/SAM7.mac
new file mode 100644
index 000000000..277ca1f94
--- /dev/null
+++ b/20080212/Demo/uIP_Demo_IAR_ARM7/resource/SAM7.mac
@@ -0,0 +1,194 @@
+// ---------------------------------------------------------
+//		 Microcontroller Software Support  -  ROUSSET  -
+// ---------------------------------------------------------
+// The software is delivered "AS IS" without warranty or 
+// condition of any  kind, either express, implied or 
+// statutory. This includes without limitation any warranty 
+// or condition with respect to merchantability or fitness 
+// for any particular purpose, or against the infringements of
+// intellectual property rights of others.
+// ---------------------------------------------------------
+//  File: SAM7.mac
+//
+//  1.0 08/Mar/04 JPP    : Creation
+//  1.1 23/Mar/05 JPP    : Change Variable name
+//
+//  $Revision: 1.5 $
+//
+// ---------------------------------------------------------
+
+__var __mac_i;
+__var __mac_pt;
+
+execUserReset()
+{
+   AIC();
+//*  Watchdog Disable
+   Watchdog();
+}
+
+execUserPreload()
+{
+//*  Set the RAM memory at 0x0020 0000 for code AT 0 flash area 
+     CheckRemap();
+//*  Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R
+    __mac_i =__readMemory32(0xFFFFF240,"Memory");
+    __message " ---------------------------------------- Chip ID   0x",__mac_i:%X;  
+    __mac_i =__readMemory32(0xFFFFF244,"Memory");
+    __message " ---------------------------------------- Extention 0x",__mac_i:%X;  
+//* Get the chip status
+
+//* Init AIC
+   AIC();
+//*  Watchdog Disable
+   Watchdog();
+
+}
+
+
+//-----------------------------------------------------------------------------
+// Watchdog
+//-------------------------------
+// Normally, the Watchdog is enable at the reset for load it's preferable to
+// Disable.
+//-----------------------------------------------------------------------------
+Watchdog()
+{
+//* Watchdog Disable
+//      AT91C_BASE_WDTC->WDTC_WDMR= AT91C_WDTC_WDDIS;
+   __writeMemory32(0x00008000,0xFFFFFD44,"Memory");
+   __message "------------------------------- Watchdog Disable ----------------------------------------";  
+}
+
+
+//-----------------------------------------------------------------------------
+// Check Remap
+//-------------
+//-----------------------------------------------------------------------------
+CheckRemap()
+{
+//* Read the value at 0x0
+    __mac_i =__readMemory32(0x00000000,"Memory");
+    __mac_i =__mac_i+1;
+    __writeMemory32(__mac_i,0x00,"Memory");
+    __mac_pt =__readMemory32(0x00000000,"Memory");
+    
+ if (__mac_i == __mac_pt)  
+ {
+   __message "------------------------------- The Remap is done ----------------------------------------";  
+//*   Toggel RESET The remap
+    __writeMemory32(0x00000001,0xFFFFFF00,"Memory");
+   
+ } else {  
+   __message "------------------------------- The Remap is NOT -----------------------------------------";  
+ }
+
+}
+
+
+execUserSetup()
+{
+ ini();
+     __message "-------------------------------Set PC ----------------------------------------";  
+     __writeMemory32(0x00000000,0xB4,"Register");
+}
+
+//-----------------------------------------------------------------------------
+// Reset the Interrupt Controller
+//-------------------------------
+// Normally, the code is executed only if a reset has been actually performed.
+// So, the AIC initialization resumes at setting up the default vectors.
+//-----------------------------------------------------------------------------
+AIC()
+{
+// Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF;
+    __writeMemory32(0xffffffff,0xFFFFF124,"Memory");
+    __writeMemory32(0xffffffff,0xFFFFF128,"Memory");
+// disable peripheral clock  Peripheral Clock Disable Register
+    __writeMemory32(0xffffffff,0xFFFFFC14,"Memory");
+
+// #define AT91C_TC0_SR    ((AT91_REG *) 	0xFFFA0020) // (TC0) Status Register
+// #define AT91C_TC1_SR    ((AT91_REG *) 	0xFFFA0060) // (TC1) Status Register
+// #define AT91C_TC2_SR    ((AT91_REG *) 	0xFFFA00A0) // (TC2) Status Register
+    __readMemory32(0xFFFA0020,"Memory");
+    __readMemory32(0xFFFA0060,"Memory");
+    __readMemory32(0xFFFA00A0,"Memory");
+
+    for (__mac_i=0;__mac_i < 8; __mac_i++)
+    {
+      // AT91C_BASE_AIC->AIC_EOICR
+      __mac_pt  =  __readMemory32(0xFFFFF130,"Memory");
+    
+    }
+   __message "------------------------------- AIC 2 INIT ---------------------------------------------";  
+}
+
+ini()
+{
+__writeMemory32(0x0,0x00,"Register");
+__writeMemory32(0x0,0x04,"Register");
+__writeMemory32(0x0,0x08,"Register");
+__writeMemory32(0x0,0x0C,"Register");
+__writeMemory32(0x0,0x10,"Register");
+__writeMemory32(0x0,0x14,"Register");
+__writeMemory32(0x0,0x18,"Register");
+__writeMemory32(0x0,0x1C,"Register");
+__writeMemory32(0x0,0x20,"Register");
+__writeMemory32(0x0,0x24,"Register");
+__writeMemory32(0x0,0x28,"Register");
+__writeMemory32(0x0,0x2C,"Register");
+__writeMemory32(0x0,0x30,"Register");
+__writeMemory32(0x0,0x34,"Register");
+__writeMemory32(0x0,0x38,"Register");
+
+// Set CPSR
+__writeMemory32(0x0D3,0x98,"Register");
+
+
+}
+
+RG()
+{
+
+__mac_i =__readMemory32(0x00,"Register");   __message "R00 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x04,"Register");   __message "R01 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x08,"Register");   __message "R02 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x0C,"Register");   __message "R03 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x10,"Register");   __message "R04 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x14,"Register");   __message "R05 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x18,"Register");   __message "R06 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x1C,"Register");   __message "R07 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x20,"Register");   __message "R08 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x24,"Register");   __message "R09 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x28,"Register");   __message "R10 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x2C,"Register");   __message "R11 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x30,"Register");   __message "R12 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x34,"Register");   __message "R13 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x38,"Register");   __message "R14 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x3C,"Register");   __message "R13 SVC 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x40,"Register");   __message "R14 SVC 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x44,"Register");   __message "R13 ABT 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x48,"Register");   __message "R14 ABT 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x4C,"Register");   __message "R13 UND 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x50,"Register");   __message "R14 UND 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x54,"Register");   __message "R13 IRQ 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x58,"Register");   __message "R14 IRQ 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x5C,"Register");   __message "R08 FIQ 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x60,"Register");   __message "R09 FIQ 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x64,"Register");   __message "R10 FIQ 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x68,"Register");   __message "R11 FIQ 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x6C,"Register");   __message "R12 FIQ 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x70,"Register");   __message "R13 FIQ 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x74,"Register");   __message "R14 FIQ0x",__mac_i:%X; 
+__mac_i =__readMemory32(0x98,"Register");   __message "CPSR     ",__mac_i:%X; 
+__mac_i =__readMemory32(0x94,"Register");   __message "SPSR     ",__mac_i:%X; 
+__mac_i =__readMemory32(0x9C,"Register");   __message "SPSR ABT ",__mac_i:%X; 
+__mac_i =__readMemory32(0xA0,"Register");   __message "SPSR ABT ",__mac_i:%X; 
+__mac_i =__readMemory32(0xA4,"Register");   __message "SPSR UND ",__mac_i:%X; 
+__mac_i =__readMemory32(0xA8,"Register");   __message "SPSR IRQ ",__mac_i:%X; 
+__mac_i =__readMemory32(0xAC,"Register");   __message "SPSR FIQ ",__mac_i:%X; 
+
+__mac_i =__readMemory32(0xB4,"Register");   __message "PC 0x",__mac_i:%X;  
+
+}
+
diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/resource/SAM7_RAM.mac b/20080212/Demo/uIP_Demo_IAR_ARM7/resource/SAM7_RAM.mac
new file mode 100644
index 000000000..63228c346
--- /dev/null
+++ b/20080212/Demo/uIP_Demo_IAR_ARM7/resource/SAM7_RAM.mac
@@ -0,0 +1,227 @@
+// ---------------------------------------------------------
+//   ATMEL Microcontroller Software Support  -  ROUSSET  -
+// ---------------------------------------------------------
+// The software is delivered "AS IS" without warranty or 
+// condition of any  kind, either express, implied or 
+// statutory. This includes without limitation any warranty 
+// or condition with respect to merchantability or fitness 
+// for any particular purpose, or against the infringements of
+// intellectual property rights of others.
+// ---------------------------------------------------------
+//  File: SAM7_RAM.mac
+//
+//  1.0 08/Mar/05 JPP    : Creation
+//  1.1 23/Mar/05 JPP    : Change Variable name
+//
+//  $Revision: 1.6 $
+//
+// ---------------------------------------------------------
+
+__var __mac_i;
+__var __mac_pt;
+__var __mac_mem;
+execUserReset()
+{
+     CheckNoRemap();
+     ini();
+     AIC();
+     __message "-------------------------------Set PC Reset ----------------------------------";  
+     __writeMemory32(0x00000000,0xB4,"Register");
+}
+
+execUserPreload()
+{
+//*  __message "-------------------------------Set CPSR  ----------------------------------";  
+     __writeMemory32(0xD3,0x98,"Register"); 
+    __writeMemory32(0xffffffff,0xFFFFFC14,"Memory");
+     PllSetting();
+ //* Init AIC
+     AIC();
+
+//*  Set the RAM memory at 0x0020 0000 for code AT 0 flash area 
+     CheckNoRemap();
+//*  Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R
+    __mac_i=__readMemory32(0xFFFFF240,"Memory");
+    __message " ---------------------------------------- Chip ID   0x",__mac_i:%X;  
+    __mac_i=__readMemory32(0xFFFFF244,"Memory");
+    __message " ---------------------------------------- Extention 0x",__mac_i:%X;  
+    __mac_i=__readMemory32(0xFFFFFF6C,"Memory");
+    __message " ---------------------------------------- Flash Version 0x",__mac_i:%X;  
+
+//*  Watchdog Disable
+    Watchdog();
+//*    RG();
+}
+//-----------------------------------------------------------------------------
+// PllSetting
+//-------------------------------
+// Set PLL
+//-----------------------------------------------------------------------------
+PllSetting()
+{
+// -1- Enabling the Main Oscillator:
+//*#define AT91C_PMC_MOR   ((AT91_REG *) 	0xFFFFFC20) // (PMC) Main Oscillator Register
+//*#define AT91C_PMC_PLLR  ((AT91_REG *) 	0xFFFFFC2C) // (PMC) PLL Register
+//*#define AT91C_PMC_MCKR  ((AT91_REG *) 	0xFFFFFC30) // (PMC) Master Clock Register
+
+//*pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) |    //0x0000 0600
+//                          AT91C_CKGR_MOSCEN ));          //0x0000 0001 
+__writeMemory32(0x00000601,0xFFFFFC20,"Memory");
+
+// -2- Wait
+// -3- Setting PLL and divider:
+// - div by 5 Fin = 3,6864 =(18,432 / 5)
+// - Mul 25+1: Fout =	95,8464 =(3,6864 *26)
+// for 96 MHz the erroe is 0.16%
+// Field out NOT USED = 0
+// PLLCOUNT pll startup time esrtimate at : 0.844 ms
+// PLLCOUNT 28 = 0.000844 /(1/32768)
+//       pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 0x05) |       //0x0000 0005
+//                         (AT91C_CKGR_PLLCOUNT & (28<<8)) //0x0000 1C00
+//                         (AT91C_CKGR_MUL & (25<<16)));   //0x0019 0000 
+__writeMemory32(0x00191C05,0xFFFFFC2C,"Memory");
+// -2- Wait
+// -5- Selection of Master Clock and Processor Clock
+// select the PLL clock divided by 2
+//	    pPMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK |     //0x0000 0003
+//                           AT91C_PMC_PRES_CLK_2 ;      //0x0000 0004
+__writeMemory32(0x00000007,0xFFFFFC30,"Memory");        
+       
+
+   __message "------------------------------- PLL  Enable ----------------------------------------";  
+}
+
+//-----------------------------------------------------------------------------
+// Watchdog
+//-------------------------------
+// Normally, the Watchdog is enable at the reset for load it's preferable to
+// Disable.
+//-----------------------------------------------------------------------------
+Watchdog()
+{
+//* Watchdog Disable
+//      AT91C_BASE_WDTC->WDTC_WDMR= AT91C_WDTC_WDDIS;
+   __writeMemory32(0x00008000,0xFFFFFD44,"Memory");
+   __message "------------------------------- Watchdog Disable ----------------------------------------";  
+}
+
+CheckNoRemap()
+{
+//* Read the value at 0x0
+    __mac_i =__readMemory32(0x00000000,"Memory");
+    __mac_mem = __mac_i;
+    __mac_i=__mac_i+1;
+    __writeMemory32(__mac_i,0x00,"Memory");
+    __mac_pt=__readMemory32(0x00000000,"Memory");
+    
+ if (__mac_i == __mac_pt)  
+ {
+   __message "------------------------------- The Remap is done ----------------------------------------";  
+   __writeMemory32( __mac_mem,0x00000000,"Memory");
+  
+ } else {  
+   __message "------------------------------- The Remap is NOT -----------------------------------------";  
+//*   Toggel RESET The remap
+    __writeMemory32(0x00000001,0xFFFFFF00,"Memory");
+ }
+
+}
+
+//-----------------------------------------------------------------------------
+// Reset the Interrupt Controller
+//-------------------------------
+// Normally, the code is executed only if a reset has been actually performed.
+// So, the AIC initialization resumes at setting up the default vectors.
+//-----------------------------------------------------------------------------
+AIC()
+{
+// Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF;
+    __writeMemory32(0xffffffff,0xFFFFF124,"Memory");
+    __writeMemory32(0xffffffff,0xFFFFF128,"Memory");
+// disable peripheral clock  Peripheral Clock Disable Register
+    __writeMemory32(0xffffffff,0xFFFFFC14,"Memory");
+
+// #define AT91C_TC0_SR    ((AT91_REG *) 	0xFFFA0020) // (TC0) Status Register
+// #define AT91C_TC1_SR    ((AT91_REG *) 	0xFFFA0060) // (TC1) Status Register
+// #define AT91C_TC2_SR    ((AT91_REG *) 	0xFFFA00A0) // (TC2) Status Register
+    __readMemory32(0xFFFA0020,"Memory");
+    __readMemory32(0xFFFA0060,"Memory");
+    __readMemory32(0xFFFA00A0,"Memory");
+    for (__mac_i=0;__mac_i < 8; __mac_i++)
+    {
+      // AT91C_BASE_AIC->AIC_EOICR
+      __mac_pt  =  __readMemory32(0xFFFFF130,"Memory");
+    
+    }
+   __message "------------------------------- AIC 2 INIT ---------------------------------------------";  
+}
+
+ini()
+{
+__writeMemory32(0x0,0x00,"Register");
+__writeMemory32(0x0,0x04,"Register");
+__writeMemory32(0x0,0x08,"Register");
+__writeMemory32(0x0,0x0C,"Register");
+__writeMemory32(0x0,0x10,"Register");
+__writeMemory32(0x0,0x14,"Register");
+__writeMemory32(0x0,0x18,"Register");
+__writeMemory32(0x0,0x1C,"Register");
+__writeMemory32(0x0,0x20,"Register");
+__writeMemory32(0x0,0x24,"Register");
+__writeMemory32(0x0,0x28,"Register");
+__writeMemory32(0x0,0x2C,"Register");
+__writeMemory32(0x0,0x30,"Register");
+__writeMemory32(0x0,0x34,"Register");
+__writeMemory32(0x0,0x38,"Register");
+
+// Set CPSR
+__writeMemory32(0x0D3,0x98,"Register");
+
+
+}
+
+RG()
+{
+
+__mac_i =__readMemory32(0x00,"Register");   __message "R00 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x04,"Register");   __message "R01 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x08,"Register");   __message "R02 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x0C,"Register");   __message "R03 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x10,"Register");   __message "R04 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x14,"Register");   __message "R05 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x18,"Register");   __message "R06 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x1C,"Register");   __message "R07 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x20,"Register");   __message "R08 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x24,"Register");   __message "R09 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x28,"Register");   __message "R10 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x2C,"Register");   __message "R11 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x30,"Register");   __message "R12 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x34,"Register");   __message "R13 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x38,"Register");   __message "R14 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x3C,"Register");   __message "R13 SVC 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x40,"Register");   __message "R14 SVC 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x44,"Register");   __message "R13 ABT 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x48,"Register");   __message "R14 ABT 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x4C,"Register");   __message "R13 UND 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x50,"Register");   __message "R14 UND 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x54,"Register");   __message "R13 IRQ 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x58,"Register");   __message "R14 IRQ 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x5C,"Register");   __message "R08 FIQ 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x60,"Register");   __message "R09 FIQ 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x64,"Register");   __message "R10 FIQ 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x68,"Register");   __message "R11 FIQ 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x6C,"Register");   __message "R12 FIQ 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x70,"Register");   __message "R13 FIQ 0x",__mac_i:%X;  
+__mac_i =__readMemory32(0x74,"Register");   __message "R14 FIQ0x",__mac_i:%X; 
+__mac_i =__readMemory32(0x98,"Register");   __message "CPSR     ",__mac_i:%X; 
+__mac_i =__readMemory32(0x94,"Register");   __message "SPSR     ",__mac_i:%X; 
+__mac_i =__readMemory32(0x9C,"Register");   __message "SPSR ABT ",__mac_i:%X; 
+__mac_i =__readMemory32(0xA0,"Register");   __message "SPSR ABT ",__mac_i:%X; 
+__mac_i =__readMemory32(0xA4,"Register");   __message "SPSR UND ",__mac_i:%X; 
+__mac_i =__readMemory32(0xA8,"Register");   __message "SPSR IRQ ",__mac_i:%X; 
+__mac_i =__readMemory32(0xAC,"Register");   __message "SPSR FIQ ",__mac_i:%X; 
+
+__mac_i =__readMemory32(0xB4,"Register");   __message "PC 0x",__mac_i:%X;  
+
+}
+
diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/resource/at91SAM7X256_FLASH.icf b/20080212/Demo/uIP_Demo_IAR_ARM7/resource/at91SAM7X256_FLASH.icf
new file mode 100644
index 000000000..1cfbb25b9
--- /dev/null
+++ b/20080212/Demo/uIP_Demo_IAR_ARM7/resource/at91SAM7X256_FLASH.icf
@@ -0,0 +1,43 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__      = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__  = 0x00000100;
+define symbol __ICFEDIT_region_ROM_end__    = 0x0003FFFF;
+define symbol __ICFEDIT_region_RAM_start__  = 0x00200000;
+define symbol __ICFEDIT_region_RAM_end__    = 0x0020FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__   = 0x400;
+define symbol __ICFEDIT_size_svcstack__ = 0x100;
+define symbol __ICFEDIT_size_irqstack__ = 0x100;
+define symbol __ICFEDIT_size_fiqstack__ = 0x40;
+define symbol __ICFEDIT_size_undstack__ = 0x40;
+define symbol __ICFEDIT_size_abtstack__ = 0x40;
+define symbol __ICFEDIT_size_heap__     = 0x400;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
+define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
+define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
+define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__    { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,
+                        block UND_STACK, block ABT_STACK, block HEAP };
+
diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/rtosdemo.ewd b/20080212/Demo/uIP_Demo_IAR_ARM7/rtosdemo.ewd
new file mode 100644
index 000000000..4af708171
--- /dev/null
+++ b/20080212/Demo/uIP_Demo_IAR_ARM7/rtosdemo.ewd
@@ -0,0 +1,1225 @@
+
+
+
+  1
+  
+    Flash Debug
+    
+      ARM
+    
+    1
+    
+      C-SPY
+      2
+      
+        15
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ARMSIM_ID
+      2
+      
+        1
+        1
+        1
+        
+        
+        
+        
+      
+    
+    
+      ANGEL_ID
+      2
+      
+        0
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      GDBSERVER_ID
+      2
+      
+        0
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARROM_ID
+      2
+      
+        0
+        1
+        1
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      JLINK_ID
+      2
+      
+        9
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      LMIFTDI_ID
+      2
+      
+        1
+        1
+        1
+        
+        
+        
+        
+      
+    
+    
+      MACRAIGOR_ID
+      2
+      
+        2
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      RDI_ID
+      2
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      THIRDPARTY_ID
+      2
+      
+        0
+        1
+        1
+        
+        
+        
+        
+      
+    
+    
+      
+        $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+        0
+      
+      
+        $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+        0
+      
+      
+        $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+        0
+      
+      
+        $EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin
+        1
+      
+      
+        $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin
+        0
+      
+    
+  
+  
+    Flash Release
+    
+      ARM
+    
+    0
+    
+      C-SPY
+      2
+      
+        15
+        1
+        0
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ARMSIM_ID
+      2
+      
+        1
+        1
+        0
+        
+        
+        
+        
+      
+    
+    
+      ANGEL_ID
+      2
+      
+        0
+        1
+        0
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      GDBSERVER_ID
+      2
+      
+        0
+        1
+        0
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARROM_ID
+      2
+      
+        0
+        1
+        0
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      JLINK_ID
+      2
+      
+        9
+        1
+        0
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      LMIFTDI_ID
+      2
+      
+        1
+        1
+        0
+        
+        
+        
+        
+      
+    
+    
+      MACRAIGOR_ID
+      2
+      
+        2
+        1
+        0
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      RDI_ID
+      2
+      
+        1
+        1
+        0
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      THIRDPARTY_ID
+      2
+      
+        0
+        1
+        0
+        
+        
+        
+        
+      
+    
+    
+      
+        $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+        0
+      
+      
+        $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+        1
+      
+      
+        $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+        0
+      
+      
+        $EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin
+        1
+      
+      
+        $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin
+        1
+      
+    
+  
+
+
+
diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/rtosdemo.ewp b/20080212/Demo/uIP_Demo_IAR_ARM7/rtosdemo.ewp
new file mode 100644
index 000000000..d6d596963
--- /dev/null
+++ b/20080212/Demo/uIP_Demo_IAR_ARM7/rtosdemo.ewp
@@ -0,0 +1,1644 @@
+
+
+
+  1
+  
+    Flash Debug
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        14
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        19
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        7
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        5
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        1
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Flash Release
+    
+      ARM
+    
+    0
+    
+      General
+      3
+      
+        14
+        1
+        0
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        19
+        1
+        0
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        7
+        1
+        0
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      OBJCOPY
+      0
+      
+        1
+        1
+        0
+        
+        
+        
+        
+        
+      
+    
+    
+      CUSTOM
+      3
+      
+        
+        
+      
+    
+    
+      BICOMP
+      0
+      
+    
+    
+      BUILDACTION
+      1
+      
+        
+        
+      
+    
+    
+      ILINK
+      0
+      
+        5
+        1
+        0
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARCHIVE
+      0
+      
+        0
+        1
+        0
+        
+        
+        
+      
+    
+    
+      BILINK
+      0
+      
+    
+  
+  
+    Demo Source
+    
+      $PROJ_DIR$\..\Common\Minimal\BlockQ.c
+    
+    
+      $PROJ_DIR$\..\Common\Minimal\death.c
+    
+    
+      $PROJ_DIR$\..\Common\Minimal\dynamic.c
+    
+    
+      $PROJ_DIR$\EMAC\EMAClISR.s79
+    
+    
+      $PROJ_DIR$\..\Common\Minimal\flash.c
+    
+    
+      $PROJ_DIR$\..\Common\Minimal\flop.c
+    
+    
+      $PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c
+    
+    
+      $PROJ_DIR$\..\Common\Minimal\integer.c
+    
+    
+      $PROJ_DIR$\main.c
+    
+    
+      $PROJ_DIR$\ParTest\ParTest.c
+    
+    
+      $PROJ_DIR$\..\Common\Minimal\PollQ.c
+    
+    
+      $PROJ_DIR$\EMAC\SAM7_EMAC.c
+    
+    
+      $PROJ_DIR$\..\Common\Minimal\semtest.c
+    
+    
+      $PROJ_DIR$\uIP_Task.c
+    
+  
+  
+    FreeRTOS Source
+    
+      $PROJ_DIR$\..\..\Source\list.c
+    
+    
+      $PROJ_DIR$\..\..\Source\portable\IAR\AtmelSAM7S64\port.c
+    
+    
+      $PROJ_DIR$\..\..\Source\portable\IAR\AtmelSAM7S64\portasm.s79
+    
+    
+      $PROJ_DIR$\..\..\Source\queue.c
+    
+    
+      $PROJ_DIR$\..\..\Source\tasks.c
+    
+  
+  
+    uIP Source
+    
+      http
+      
+        $PROJ_DIR$\uip\cgi.c
+      
+      
+        $PROJ_DIR$\uip\fs.c
+      
+      
+        $PROJ_DIR$\uip\httpd.c
+      
+    
+    
+      $PROJ_DIR$\uip\uip.c
+    
+    
+      $PROJ_DIR$\uip\uip_arch.c
+    
+    
+      $PROJ_DIR$\uip\uip_arp.c
+    
+  
+  
+    $PROJ_DIR$\SrcIAR\Cstartup.s
+  
+  
+    $PROJ_DIR$\SrcIAR\Cstartup_SAM7.c
+  
+
+
+
diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/rtosdemo.eww b/20080212/Demo/uIP_Demo_IAR_ARM7/rtosdemo.eww
new file mode 100644
index 000000000..2294aacb5
--- /dev/null
+++ b/20080212/Demo/uIP_Demo_IAR_ARM7/rtosdemo.eww
@@ -0,0 +1,10 @@
+
+
+
+  
+    $WS_DIR$\rtosdemo.ewp
+  
+  
+
+
+
diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/settings/Basic.dbgdt b/20080212/Demo/uIP_Demo_IAR_ARM7/settings/Basic.dbgdt
new file mode 100644
index 000000000..5085f2cdb
--- /dev/null
+++ b/20080212/Demo/uIP_Demo_IAR_ARM7/settings/Basic.dbgdt
@@ -0,0 +1,71 @@
+
+
+
+  
+    
+      
+        
+          
+          
+          
+        1892727
+      
+      
+        
+        
+        
+      200100
+      
+      
+    200188171100100010
+    
+      
+        
+          
+            TabID-23416-30482
+            Workspace
+            Workspace
+            
+              
+            rtosdemo
+          
+        
+        
+      0
+      
+      
+        
+          
+            TabID-12145-30489
+            Debug Log
+            Debug-Log
+            
+          
+          
+            TabID-22894-30492
+            Build
+            Build
+            
+          
+        
+        
+      1
+    TabID-18780-12821MemoryMemory2097764209776410000TabID-23506-14575WatchWatchpxCurrentTCBulCriticalNesting01761001001000TabID-4859-22480DisassemblyDisassembly0TabID-154-22568RegisterRegister0001CPSR0
+    
+      
+      
+      
+      
+    TextEditorE:\Dev\FreeRTOS\Demo\ARM7_Ateml_IAR\main.c010378378TextEditorE:\Dev\FreeRTOS\source\include\task.h07782428324283TextEditorE:\Dev\FreeRTOS\Source\tasks.c09393051130511TextEditorE:\Dev\FreeRTOS\Demo\ARM7_Ateml_IAR\SrcIAR\Cstartup.s7904822262226TextEditorE:\Dev\FreeRTOS\Demo\Common\Minimal\flash.c09840254025TextEditorE:\Dev\FreeRTOS\Source\portable\IAR\AtmelSAM7\portasm.s7904110571079TextEditorE:\Dev\FreeRTOS\Demo\ARM7_Ateml_IAR\srciar\lib_AT91SAM7S64.h02778108450108450TextEditorE:\Dev\FreeRTOS\Source\portable\IAR\AtmelSAM7\port.c0136532653267TextEditorE:\Dev\FreeRTOS\Demo\ARM7_Ateml_IAR\ParTest\ParTest.c03600TextEditorE:\Dev\FreeRTOS\Source\portable\IAR\AtmelSAM7\portmacro.h067000100000010000001
+    
+      
+      
+      
+      
+      
+    IarIdePM1DebuggerGui1-2-2715263-2-215315395625136729165625640750-2-2715647-2-2190190118750169794405625640750-26457151025645-2190190118750169794237500640750-2-21511602-2-21604153100250013672995625136729149-2333669-21496711844193751644321143751635381496673331602667149935184584375164432115000598748
+  
+
+
+
diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/settings/Basic.dni b/20080212/Demo/uIP_Demo_IAR_ARM7/settings/Basic.dni
new file mode 100644
index 000000000..9b68f65a8
--- /dev/null
+++ b/20080212/Demo/uIP_Demo_IAR_ARM7/settings/Basic.dni
@@ -0,0 +1,23 @@
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+Count=1
+[Low Level]
+Pipeline mode=0
+Initialized=0
diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/settings/BasicSAM7.wsdt b/20080212/Demo/uIP_Demo_IAR_ARM7/settings/BasicSAM7.wsdt
new file mode 100644
index 000000000..2ce5c4bb0
--- /dev/null
+++ b/20080212/Demo/uIP_Demo_IAR_ARM7/settings/BasicSAM7.wsdt
@@ -0,0 +1,80 @@
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diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/settings/rtosdemo.dbgdt b/20080212/Demo/uIP_Demo_IAR_ARM7/settings/rtosdemo.dbgdt
new file mode 100644
index 000000000..cf1cb500a
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diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/settings/rtosdemo.dni b/20080212/Demo/uIP_Demo_IAR_ARM7/settings/rtosdemo.dni
new file mode 100644
index 000000000..6bf70e47e
--- /dev/null
+++ b/20080212/Demo/uIP_Demo_IAR_ARM7/settings/rtosdemo.dni
@@ -0,0 +1,39 @@
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diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/settings/rtosdemo.wsdt b/20080212/Demo/uIP_Demo_IAR_ARM7/settings/rtosdemo.wsdt
new file mode 100644
index 000000000..4116e6cae
--- /dev/null
+++ b/20080212/Demo/uIP_Demo_IAR_ARM7/settings/rtosdemo.wsdt
@@ -0,0 +1,71 @@
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diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/uIP_Task.c b/20080212/Demo/uIP_Demo_IAR_ARM7/uIP_Task.c
new file mode 100644
index 000000000..24f0bc3ee
--- /dev/null
+++ b/20080212/Demo/uIP_Demo_IAR_ARM7/uIP_Task.c
@@ -0,0 +1,207 @@
+/*
+ * Modified from an original work that is Copyright (c) 2001-2003, Adam Dunkels.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: main.c,v 1.10.2.4 2003/10/21 21:27:51 adam Exp $
+ *
+ */
+
+/* Standard includes. */
+#include 
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "semphr.h"
+#include "task.h"
+
+/* Demo app includes. */
+#include "SAM7_EMAC.h"
+
+/* uIP includes. */
+#undef HTONS
+#include "uip.h"
+#include "uip_arp.h"
+#include "tapdev.h"
+#include "httpd.h"
+
+/* The start of the uIP buffer, which will contain the frame headers. */
+#define pucUIP_Buffer ( ( struct uip_eth_hdr * ) &uip_buf[ 0 ] )
+
+/* uIP update frequencies. */
+#define RT_CLOCK_SECOND		( configTICK_RATE_HZ  )
+#define uipARP_FREQUENCY	( 20 )
+#define uipMAX_BLOCK_TIME	( RT_CLOCK_SECOND / 4 )
+
+/*-----------------------------------------------------------*/
+
+void vuIP_TASK( void *pvParameters )
+{
+/* The semaphore used by the EMAC ISR to indicate that an Rx frame is ready
+for processing. */
+xSemaphoreHandle xSemaphore = NULL;
+portBASE_TYPE xARPTimer;
+unsigned portBASE_TYPE uxPriority;
+static volatile portTickType xStartTime, xCurrentTime;
+
+	/* Initialize the uIP TCP/IP stack. */
+	uip_init();
+	uip_arp_init();
+	
+	/* Initialize the HTTP server. */
+	httpd_init();
+
+	/* Initialise the local timers. */
+	xStartTime = xTaskGetTickCount();
+	xARPTimer = 0;
+
+	/* Initialise the EMAC.  A semaphore will be returned when this is
+	successful. This routine contains code that polls status bits.  If the
+	Ethernet cable is not plugged in then this can take a considerable time.
+	To prevent this starving lower priority tasks of processing time we
+	lower our priority prior to the call, then raise it back again once the
+	initialisation is complete. */
+	uxPriority = uxTaskPriorityGet( NULL );
+	vTaskPrioritySet( NULL, tskIDLE_PRIORITY );
+	while( xSemaphore == NULL )
+	{
+		xSemaphore = xEMACInit();
+	}
+	vTaskPrioritySet( NULL, uxPriority );
+
+	for( ;; )
+	{
+		/* Let the network device driver read an entire IP packet
+		into the uip_buf. If it returns > 0, there is a packet in the
+		uip_buf buffer. */
+		uip_len = ulEMACPoll();
+
+		/* Was a packet placed in the uIP buffer? */
+		if( uip_len > 0 )
+		{
+			/* A packet is present in the uIP buffer. We call the
+			appropriate ARP functions depending on what kind of packet we
+			have received. If the packet is an IP packet, we should call
+			uip_input() as well. */
+			if( pucUIP_Buffer->type == htons( UIP_ETHTYPE_IP ) )
+			{
+				uip_arp_ipin();
+				uip_input();
+
+				/* If the above function invocation resulted in data that
+				should be sent out on the network, the global variable
+				uip_len is set to a value > 0. */
+				if( uip_len > 0 )
+				{
+					uip_arp_out();
+					lEMACSend();
+				}
+			}
+			else if( pucUIP_Buffer->type == htons( UIP_ETHTYPE_ARP ) )
+			{
+				uip_arp_arpin();
+
+				/* If the above function invocation resulted in data that
+				should be sent out on the network, the global variable
+				uip_len is set to a value > 0. */	
+				if( uip_len > 0 )
+				{	
+					lEMACSend();
+				}
+			}
+		}
+		else
+		{
+			/* The poll function returned 0, so no packet was
+			received. Instead we check if it is time that we do the
+			periodic processing. */
+			xCurrentTime = xTaskGetTickCount();
+
+			if( ( xCurrentTime - xStartTime ) >= RT_CLOCK_SECOND )
+			{
+				portBASE_TYPE i;
+
+				/* Reset the timer. */
+				xStartTime = xCurrentTime;
+
+				/* Periodic check of all connections. */
+				for( i = 0; i < UIP_CONNS; i++ )
+				{
+					uip_periodic( i );
+
+					/* If the above function invocation resulted in data that
+					should be sent out on the network, the global variable
+					uip_len is set to a value > 0. */					
+					if( uip_len > 0 )
+					{
+						uip_arp_out();
+						lEMACSend();
+					}
+				}
+
+				#if UIP_UDP
+					for( i = 0; i < UIP_UDP_CONNS; i++ )
+					{
+						uip_udp_periodic( i );
+
+						/* If the above function invocation resulted in data that
+						should be sent out on the network, the global variable
+						uip_len is set to a value > 0. */
+						if( uip_len > 0 )
+						{
+							uip_arp_out();
+							tapdev_send();
+						}
+					}
+				#endif /* UIP_UDP */
+
+				/* Periodically call the ARP timer function. */
+				if( ++xARPTimer == uipARP_FREQUENCY )
+				{	
+					uip_arp_timer();
+					xARPTimer = 0;
+				}
+			}
+			else
+			{				
+				/* We did not receive a packet, and there was no periodic
+				processing to perform.  Block for a fixed period.  If a packet
+				is received during this period we will be woken by the ISR
+				giving us the Semaphore. */
+				xSemaphoreTake( xSemaphore, uipMAX_BLOCK_TIME );
+			}
+		}
+	}
+}
+/*-----------------------------------------------------------------------------------*/
+
+
+
+
+
diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/uIP_Task.h b/20080212/Demo/uIP_Demo_IAR_ARM7/uIP_Task.h
new file mode 100644
index 000000000..aae424ba0
--- /dev/null
+++ b/20080212/Demo/uIP_Demo_IAR_ARM7/uIP_Task.h
@@ -0,0 +1,8 @@
+#ifndef UIP_TASK_H
+#define UIP_TASK_H
+
+/* The task that handles all uIP data. */
+void vuIP_TASK( void *pvParameters );
+
+#endif
+
diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/uip/Makefile b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/Makefile
new file mode 100644
index 000000000..61d3a06aa
--- /dev/null
+++ b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/Makefile
@@ -0,0 +1,74 @@
+# Copyright (c) 2001, Adam Dunkels.
+# All rights reserved. 
+#
+# Redistribution and use in source and binary forms, with or without 
+# modification, are permitted provided that the following conditions 
+# are met: 
+# 1. Redistributions of source code must retain the above copyright 
+#    notice, this list of conditions and the following disclaimer. 
+# 2. Redistributions in binary form must reproduce the above copyright 
+#    notice, this list of conditions and the following disclaimer in the 
+#    documentation and/or other materials provided with the distribution. 
+# 3. All advertising materials mentioning features or use of this software
+#    must display the following acknowledgement:
+#      This product includes software developed by Adam Dunkels.
+# 4. The name of the author may not be used to endorse or promote
+#    products derived from this software without specific prior
+#    written permission.  
+#
+# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+# OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+# GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
+#
+# This file is part of the uIP TCP/IP stack.
+#
+# $Id: Makefile,v 1.8.2.2 2003/10/04 22:54:17 adam Exp $
+#
+
+CC=gcc
+CFLAGS=-Wall -g -I../uip -I. -I../apps/httpd -I../apps/resolv -I../apps/webclient -I../apps/smtp  -I../apps/telnet -fpack-struct
+
+%.o:
+	$(CC) $(CFLAGS) -c $(<:.o=.c)
+
+
+uip: uip.o uip_arch.o tapdev.o httpd.o main.o fs.o uip_arp.o cgi.o 
+
+tapdev.o: tapdev.c uipopt.h
+main.o: main.c ../uip/uip.h uipopt.h ../apps/httpd/httpd.h \
+ tapdev.h
+uip_arch.o: uip_arch.c ../uip/uip_arch.h ../uip/uip.h uipopt.h \
+ ../apps/httpd/httpd.h 
+uip.o: ../uip/uip.c ../uip/uip.h uipopt.h ../apps/httpd/httpd.h 
+
+uip_arp.o: ../uip/uip_arp.c ../uip/uip_arp.h ../uip/uip.h uipopt.h \
+ ../apps/httpd/httpd.h
+	$(CC) -o uip_arp.o $(CFLAGS) -fpack-struct -c ../uip/uip_arp.c
+
+
+cgi.o: ../apps/httpd/cgi.c ../uip/uip.h uipopt.h ../apps/smtp/smtp.h \
+ ../apps/httpd/cgi.h ../apps/httpd/httpd.h ../apps/httpd/fs.h
+fs.o: ../apps/httpd/fs.c ../uip/uip.h uipopt.h ../apps/smtp/smtp.h \
+ ../apps/httpd/httpd.h ../apps/httpd/fs.h ../apps/httpd/fsdata.h \
+ ../apps/httpd/fsdata.c
+fsdata.o: ../apps/httpd/fsdata.c
+httpd.o: ../apps/httpd/httpd.c ../uip/uip.h uipopt.h \
+ ../apps/smtp/smtp.h ../apps/httpd/httpd.h ../apps/httpd/fs.h \
+ ../apps/httpd/fsdata.h ../apps/httpd/cgi.h
+
+clean:
+	rm -f *.o *~ *core uip
+
+
+
+
+
+
diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/uip/cgi.c b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/cgi.c
new file mode 100644
index 000000000..748cc1b5d
--- /dev/null
+++ b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/cgi.c
@@ -0,0 +1,225 @@
+/**
+ * \addtogroup httpd
+ * @{
+ */
+
+/**
+ * \file
+ * HTTP server script language C functions file.
+ * \author Adam Dunkels 
+ *
+ * This file contains functions that are called by the web server
+ * scripts. The functions takes one argument, and the return value is
+ * interpreted as follows. A zero means that the function did not
+ * complete and should be invoked for the next packet as well. A
+ * non-zero value indicates that the function has completed and that
+ * the web server should move along to the next script line.
+ *
+ */
+
+/*
+ * Copyright (c) 2001, Adam Dunkels.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: cgi.c,v 1.23.2.4 2003/10/07 13:22:27 adam Exp $
+ *
+ */
+
+#include "uip.h"
+#include "cgi.h"
+#include "httpd.h"
+#include "fs.h"
+
+#include 
+#include 
+
+static u8_t print_stats(u8_t next);
+static u8_t file_stats(u8_t next);
+static u8_t tcp_stats(u8_t next);
+static u8_t rtos_stats(u8_t next);
+
+cgifunction cgitab[] = {
+  print_stats,   /* CGI function "a" */
+  file_stats,    /* CGI function "b" */
+  tcp_stats,      /* CGI function "c" */
+  rtos_stats	/* CGI function "d" */
+};
+
+static const char closed[] =   /*  "CLOSED",*/
+{0x43, 0x4c, 0x4f, 0x53, 0x45, 0x44, 0};
+static const char syn_rcvd[] = /*  "SYN-RCVD",*/
+{0x53, 0x59, 0x4e, 0x2d, 0x52, 0x43, 0x56,
+ 0x44,  0};
+static const char syn_sent[] = /*  "SYN-SENT",*/
+{0x53, 0x59, 0x4e, 0x2d, 0x53, 0x45, 0x4e,
+ 0x54,  0};
+static const char established[] = /*  "ESTABLISHED",*/
+{0x45, 0x53, 0x54, 0x41, 0x42, 0x4c, 0x49, 0x53, 0x48,
+ 0x45, 0x44, 0};
+static const char fin_wait_1[] = /*  "FIN-WAIT-1",*/
+{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49,
+ 0x54, 0x2d, 0x31, 0};
+static const char fin_wait_2[] = /*  "FIN-WAIT-2",*/
+{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49,
+ 0x54, 0x2d, 0x32, 0};
+static const char closing[] = /*  "CLOSING",*/
+{0x43, 0x4c, 0x4f, 0x53, 0x49,
+ 0x4e, 0x47, 0};
+static const char time_wait[] = /*  "TIME-WAIT,"*/
+{0x54, 0x49, 0x4d, 0x45, 0x2d, 0x57, 0x41,
+ 0x49, 0x54, 0};
+static const char last_ack[] = /*  "LAST-ACK"*/
+{0x4c, 0x41, 0x53, 0x54, 0x2d, 0x41, 0x43,
+ 0x4b, 0};
+
+static const char *states[] = {
+  closed,
+  syn_rcvd,
+  syn_sent,
+  established,
+  fin_wait_1,
+  fin_wait_2,
+  closing,
+  time_wait,
+  last_ack};
+
+
+/*-----------------------------------------------------------------------------------*/
+/* print_stats:
+ *
+ * Prints out a part of the uIP statistics. The statistics data is
+ * written into the uip_appdata buffer. It overwrites any incoming
+ * packet.
+ */
+static u8_t
+print_stats(u8_t next)
+{
+#if UIP_STATISTICS
+  u16_t i, j;
+  u8_t *buf;
+  u16_t *databytes;
+
+  if(next) {
+    /* If our last data has been acknowledged, we move on the next
+       chunk of statistics. */
+    hs->count = hs->count + 4;
+    if(hs->count >= sizeof(struct uip_stats)/sizeof(u16_t)) {
+      /* We have printed out all statistics, so we return 1 to
+	 indicate that we are done. */
+      return 1;
+    }
+  }
+
+  /* Write part of the statistics into the uip_appdata buffer. */
+  databytes = (u16_t *)&uip_stat + hs->count;
+  buf       = (u8_t *)uip_appdata;
+
+  j = 4 + 1;
+  i = hs->count;
+  while (i < sizeof(struct uip_stats)/sizeof(u16_t) && --j > 0) {
+    sprintf((char *)buf, "%5u\r\n", *databytes);
+    ++databytes;
+    buf += 6;
+    ++i;
+  }
+
+  /* Send the data. */
+  uip_send(uip_appdata, buf - uip_appdata);
+
+  return 0;
+#else
+  return 1;
+#endif /* UIP_STATISTICS */
+}
+/*-----------------------------------------------------------------------------------*/
+static u8_t
+file_stats(u8_t next)
+{
+  /* We use sprintf() to print the number of file accesses to a
+     particular file (given as an argument to the function in the
+     script). We then use uip_send() to actually send the data. */
+  if(next) {
+    return 1;
+  }
+  uip_send(uip_appdata, sprintf((char *)uip_appdata, "%5u", fs_count(&hs->script[4])));
+  return 0;
+}
+/*-----------------------------------------------------------------------------------*/
+static u8_t
+tcp_stats(u8_t next)
+{
+  struct uip_conn *conn;
+
+  if(next) {
+    /* If the previously sent data has been acknowledged, we move
+       forward one connection. */
+    if(++hs->count == UIP_CONNS) {
+      /* If all connections has been printed out, we are done and
+	 return 1. */
+      return 1;
+    }
+  }
+
+  conn = &uip_conns[hs->count];
+  if((conn->tcpstateflags & TS_MASK) == CLOSED) {
+    uip_send(uip_appdata, sprintf((char *)uip_appdata,
+				  "
    \r\n", + conn->nrtx, + conn->timer, + (uip_outstanding(conn))? '*':' ', + (uip_stopped(conn))? '!':' ')); + } else { + uip_send(uip_appdata, sprintf((char *)uip_appdata, + "\r\n", + htons(conn->ripaddr[0]) >> 8, + htons(conn->ripaddr[0]) & 0xff, + htons(conn->ripaddr[1]) >> 8, + htons(conn->ripaddr[1]) & 0xff, + htons(conn->rport), + states[conn->tcpstateflags & TS_MASK], + conn->nrtx, + conn->timer, + (uip_outstanding(conn))? '*':' ', + (uip_stopped(conn))? '!':' ')); + } + return 0; +} +/*-----------------------------------------------------------------------------------*/ + +static u8_t +rtos_stats(u8_t next) +{ +static char cTraceBuffer[ 1024 ]; +extern void ( vTaskList )( char * ); + + vTaskList( cTraceBuffer ); + uip_send( ( void * ) cTraceBuffer, strlen( cTraceBuffer ) ); + + return 1; +} diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/uip/cgi.h b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/cgi.h new file mode 100644 index 000000000..d85389b52 --- /dev/null +++ b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/cgi.h @@ -0,0 +1,57 @@ +/** + * \addtogroup httpd + * @{ + */ + +/** + * \file + * HTTP script language header file. + * \author Adam Dunkels + */ + +/* + * Copyright (c) 2001, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: cgi.h,v 1.3.2.4 2003/10/07 13:22:27 adam Exp $ + * + */ + +#ifndef __CGI_H__ +#define __CGI_H__ + +typedef u8_t (* cgifunction)(u8_t next); + +/** + * A table containing pointers to C functions that can be called from + * a web server script. + */ +extern cgifunction cgitab[]; + +#endif /* __CGI_H__ */ diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/uip/crt0.asm b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/crt0.asm new file mode 100644 index 000000000..ef91f42a8 --- /dev/null +++ b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/crt0.asm @@ -0,0 +1,66 @@ +// Rowley C Compiler, runtime support. +// +// Copyright (c) 2001, 2002, 2003 Rowley Associates Limited. +// +// This file may be distributed under the terms of the License Agreement +// provided with this software. +// +// THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE +// WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. + +; Create sections + .data + .bss + +; Go to code section. + .code + +; Executed upon reset +__reset proc + +; Turn off watchdog. You can enable it in main() if required. + mov.w #0x5a80, &0x120 + +; Set up stack. + mov.w #RAM_Start_Address+RAM_Size, sp + +; Copy from initialised data section to data section. + mov.w #SFB(IDATA0), r15 + mov.w #data_init_begin, r14 + mov.w #data_init_end-data_init_begin, r13 + call #_memcpy + +; Zero the bss. Ensure the stack is not allocated in the bss! + mov.w #SFB(UDATA0), r15 + mov.w #0, r14 + mov.w #SFE(UDATA0)-SFB(UDATA0), r13 + call #_memset + +; Call user entry point void main(void). + call #_main + +; If main() returns, kick off again. + jmp __reset + endproc + +; Heap data structures; removed by the linker if the heap isn't used. + .break + .data + align WORD +___heap_start__:: + DW 0 + DW heap_size + DS heap_size-4 + +; Reset vector + .vectors + .keep + org 0x1e + dw __reset + +; Initialise the IDATA0 section by duplicating the contents into the +; CONST section and copying them on startup. + .const +data_init_begin: + .init "IDATA0" +data_init_end: diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/uip/fs.c b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/fs.c new file mode 100644 index 000000000..a66eb8dc3 --- /dev/null +++ b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/fs.c @@ -0,0 +1,156 @@ +/** + * \addtogroup httpd + * @{ + */ + +/** + * \file + * HTTP server read-only file system code. + * \author Adam Dunkels + * + * A simple read-only filesystem. + */ + +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: fs.c,v 1.7.2.3 2003/10/07 13:22:27 adam Exp $ + */ + +#include "uip.h" +#include "httpd.h" +#include "fs.h" +#include "fsdata.h" + +#define NULL (void *)0 +#include "fsdata.c" + +#ifdef FS_STATISTICS +#if FS_STATISTICS == 1 +static u16_t count[FS_NUMFILES]; +#endif /* FS_STATISTICS */ +#endif /* FS_STATISTICS */ + +/*-----------------------------------------------------------------------------------*/ +static u8_t +fs_strcmp(const char *str1, const char *str2) +{ + u8_t i; + i = 0; + loop: + + if(str2[i] == 0 || + str1[i] == '\r' || + str1[i] == '\n') { + return 0; + } + + if(str1[i] != str2[i]) { + return 1; + } + + + ++i; + goto loop; +} +/*-----------------------------------------------------------------------------------*/ +int +fs_open(const char *name, struct fs_file *file) +{ +#ifdef FS_STATISTICS +#if FS_STATISTICS == 1 + u16_t i = 0; +#endif /* FS_STATISTICS */ +#endif /* FS_STATISTICS */ + struct fsdata_file_noconst *f; + + for(f = (struct fsdata_file_noconst *)FS_ROOT; + f != NULL; + f = (struct fsdata_file_noconst *)f->next) { + + if(fs_strcmp(name, f->name) == 0) { + file->data = f->data; + file->len = f->len; +#ifdef FS_STATISTICS +#if FS_STATISTICS == 1 + ++count[i]; +#endif /* FS_STATISTICS */ +#endif /* FS_STATISTICS */ + + return 1; + } +#ifdef FS_STATISTICS +#if FS_STATISTICS == 1 + ++i; +#endif /* FS_STATISTICS */ +#endif /* FS_STATISTICS */ + + } + return 0; +} +/*-----------------------------------------------------------------------------------*/ +void +fs_init(void) +{ +#ifdef FS_STATISTICS +#if FS_STATISTICS == 1 + u16_t i; + for(i = 0; i < FS_NUMFILES; i++) { + count[i] = 0; + } +#endif /* FS_STATISTICS */ +#endif /* FS_STATISTICS */ +} +/*-----------------------------------------------------------------------------------*/ +#ifdef FS_STATISTICS +#if FS_STATISTICS == 1 +u16_t fs_count +(char *name) +{ + struct fsdata_file_noconst *f; + u16_t i; + + i = 0; + for(f = (struct fsdata_file_noconst *)FS_ROOT; + f != NULL; + f = (struct fsdata_file_noconst *)f->next) { + + if(fs_strcmp(name, f->name) == 0) { + return count[i]; + } + ++i; + } + return 0; +} +#endif /* FS_STATISTICS */ +#endif /* FS_STATISTICS */ +/*-----------------------------------------------------------------------------------*/ diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/uip/fs.h b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/fs.h new file mode 100644 index 000000000..65551ba41 --- /dev/null +++ b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/fs.h @@ -0,0 +1,80 @@ +/** + * \addtogroup httpd + * @{ + */ + +/** + * \file + * HTTP server read-only file system header file. + * \author Adam Dunkels + */ + +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: fs.h,v 1.6.2.3 2003/10/07 13:22:27 adam Exp $ + */ +#ifndef __FS_H__ +#define __FS_H__ + +#include "uip.h" + +/** + * An open file in the read-only file system. + */ +struct fs_file { + char *data; /**< The actual file data. */ + int len; /**< The length of the file data. */ +}; + +/** + * Open a file in the read-only file system. + * + * \param name The name of the file. + * + * \param file The file pointer, which must be allocated by caller and + * will be filled in by the function. + */ +int fs_open(const char *name, struct fs_file *file); + +#ifdef FS_STATISTICS +#if FS_STATISTICS == 1 +u16_t fs_count(char *name); +#endif /* FS_STATISTICS */ +#endif /* FS_STATISTICS */ + +/** + * Initialize the read-only file system. + */ +void fs_init(void); + +#endif /* __FS_H__ */ diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/uip/fs/404.html b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/fs/404.html new file mode 100644 index 000000000..8d6beec83 --- /dev/null +++ b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/fs/404.html @@ -0,0 +1 @@ +

    404 - file not found

    \ No newline at end of file diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/files b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/files new file mode 100644 index 000000000..58c45f30f --- /dev/null +++ b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/files @@ -0,0 +1,26 @@ +# This script shows the access statistics for different files on the +# web server. +# +# First, we include the HTML header. +i /files_header.html +# Print out the name of the file, and call the function that prints +# the access statistics of that file. +t     +# Include the HTML footer. +i /files_footer.plain +# End of script. +. \ No newline at end of file diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/rtos b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/rtos new file mode 100644 index 000000000..7772ea420 --- /dev/null +++ b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/rtos @@ -0,0 +1,6 @@ +t uIP Open Source Embedded TCP/IP Stack On FreeRTOS KernelFreeRTOS Homepage

    AT91SAM7X Embedded WEB Server Demo
    Using uIP and the FreeRTOS real time kernel

    These pages are being served by an Atmel AT91SAM7X256 microcontroller, using Adam Dunkels open source uIP TCP/IP stack.

    The uIP stack is executing from a single task under control of the FreeRTOS real time kernel. The table below shows the statistics for all the tasks in the demo applicaiton.

    Task          State  Priority  Stack	#
    ************************************************
    
+c d
+t
    +. + + diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/stats b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/stats new file mode 100644 index 000000000..2c71c90dc --- /dev/null +++ b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/stats @@ -0,0 +1,4 @@ +i /stats_header.html +c a +i /stats_footer.plain +. diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/tcp b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/tcp new file mode 100644 index 000000000..14efd3700 --- /dev/null +++ b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/tcp @@ -0,0 +1,4 @@ +i /tcp_header.html +c c +i /tcp_footer.plain +. \ No newline at end of file diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/uip/fs/control.html b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/fs/control.html new file mode 100644 index 000000000..0d9352ce7 --- /dev/null +++ b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/fs/control.html @@ -0,0 +1,20 @@ + + +AT91SAM7X Embedded WEB Server using uIP and FreeRTOS + + + + +Tasks | +Connections | +Files | +Statistics
    +
    +     + + + + + + + diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/uip/fs/files_footer.plain b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/fs/files_footer.plain new file mode 100644 index 000000000..0b6dceb4f --- /dev/null +++ b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/fs/files_footer.plain @@ -0,0 +1,3 @@ +
    LocalRemoteStateRetransmissionsTimerFlags
    --%u%u%c %c
    %u.%u.%u.%u:%u%s%u%u%c %c
    /index.html +c b /index.html +t
    /control.html +c b /control.html +t
    /img/logo.png +c b /img/logo.png +t
    /404.html +c b /404.html +t
    /cgi/files +c b /cgi/files +t
    /cgi/stats +c b /cgi/stats +t
    /cgi/tcp +c b /cgi/tcp +t
    + + diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/uip/fs/files_header.html b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/fs/files_header.html new file mode 100644 index 000000000..20cf1c961 --- /dev/null +++ b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/fs/files_header.html @@ -0,0 +1,4 @@ + + +
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    + + diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/uip/fs/stats_header.html b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/fs/stats_header.html new file mode 100644 index 000000000..e819c3449 --- /dev/null +++ b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/fs/stats_header.html @@ -0,0 +1,30 @@ + + +
    + +
    +
    +IP           Packets dropped
+             Packets received
+             Packets sent
+IP errors    IP version/header length
+             IP length, high byte
+             IP length, low byte
+             IP fragments
+             Header checksum
+             Wrong protocol
+ICMP	     Packets dropped
+             Packets received
+             Packets sent
+             Type errors
+TCP          Packets dropped
+             Packets received
+             Packets sent
+             Checksum errors
+             Data packets without ACKs
+             Resets
+             Retransmissions
+	     No connection avaliable
+	     Connection attempts to closed ports
+
    +
    \ No newline at end of file
diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/uip/fs/tcp_footer.plain b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/fs/tcp_footer.plain
new file mode 100644
index 000000000..442c17a58
--- /dev/null
+++ b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/fs/tcp_footer.plain
@@ -0,0 +1,5 @@
+
+
    +
    + + \ No newline at end of file diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/uip/fs/tcp_header.html b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/fs/tcp_header.html new file mode 100644 index 000000000..47bdf302c --- /dev/null +++ b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/fs/tcp_header.html @@ -0,0 +1,6 @@ + + +
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0x2e, 0xa, 0xa, 0xa, }; + +static const char data_index_html[] = { + /* /index.html */ + 0x2f, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0, + 0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x32, + 0x30, 0x30, 0x20, 0x4f, 0x4b, 0xd, 0xa, 0x53, 0x65, 0x72, + 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x30, + 0x2e, 0x39, 0x20, 0x28, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, + 0x2f, 0x64, 0x75, 0x6e, 0x6b, 0x65, 0x6c, 0x73, 0x2e, 0x63, + 0x6f, 0x6d, 0x2f, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, + 0x70, 0x2f, 0x29, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x74, 0x65, + 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, + 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0xd, 0xa, + 0xd, 0xa, 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xd, 0xa, + 0x3c, 0x68, 0x65, 0x61, 0x64, 0x3e, 0xd, 0xa, 0x3c, 0x2f, + 0x68, 0x65, 0x61, 0x64, 0x3e, 0xd, 0xa, 0xd, 0xa, 0x3c, + 0x66, 0x72, 0x61, 0x6d, 0x65, 0x73, 0x65, 0x74, 0x20, 0x63, + 0x6f, 0x6c, 0x73, 0x3d, 0x22, 0x2a, 0x22, 0x20, 0x72, 0x6f, + 0x77, 0x73, 0x3d, 0x22, 0x31, 0x32, 0x30, 0x2c, 0x2a, 0x22, + 0x20, 0x66, 0x72, 0x61, 0x6d, 0x65, 0x62, 0x6f, 0x72, 0x64, + 0x65, 0x72, 0x3d, 0x22, 0x6e, 0x6f, 0x22, 0x3e, 0x20, 0xd, + 0xa, 0x20, 0x20, 0x3c, 0x66, 0x72, 0x61, 0x6d, 0x65, 0x20, + 0x73, 0x72, 0x63, 0x3d, 0x22, 0x63, 0x6f, 0x6e, 0x74, 0x72, + 0x6f, 0x6c, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, 0xd, + 0xa, 0x20, 0x20, 0x3c, 0x66, 0x72, 0x61, 0x6d, 0x65, 0x20, + 0x73, 0x72, 0x63, 0x3d, 0x22, 0x2f, 0x63, 0x67, 0x69, 0x2f, + 0x72, 0x74, 0x6f, 0x73, 0x22, 0x20, 0x6e, 0x61, 0x6d, 0x65, + 0x3d, 0x22, 0x6d, 0x61, 0x69, 0x6e, 0x22, 0x3e, 0xd, 0xa, + 0x3c, 0x2f, 0x66, 0x72, 0x61, 0x6d, 0x65, 0x73, 0x65, 0x74, + 0x3e, 0xd, 0xa, 0xd, 0xa, 0x3c, 0x6e, 0x6f, 0x66, 0x72, + 0x61, 0x6d, 0x65, 0x73, 0x3e, 0xd, 0xa, 0x3c, 0x62, 0x6f, + 0x64, 0x79, 0x3e, 0xd, 0xa, 0x59, 0x6f, 0x75, 0x72, 0x20, + 0x62, 0x72, 0x6f, 0x77, 0x73, 0x65, 0x72, 0x20, 0x6d, 0x75, + 0x73, 0x74, 0x20, 0x73, 0x75, 0x70, 0x70, 0x6f, 0x72, 0x74, + 0x20, 0x66, 0x72, 0x61, 0x6d, 0x65, 0x73, 0xd, 0xa, 0x3c, + 0x2f, 0x62, 0x6f, 0x64, 0x79, 0x3e, 0xd, 0xa, 0x3c, 0x2f, + 0x6e, 0x6f, 0x66, 0x72, 0x61, 0x6d, 0x65, 0x73, 0x3e, 0xd, + 0xa, 0x3c, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x3e, }; + +const struct fsdata_file file_404_html[] = {{NULL, data_404_html, data_404_html + 10, sizeof(data_404_html) - 10}}; + +const struct fsdata_file file_control_html[] = {{file_404_html, data_control_html, data_control_html + 14, sizeof(data_control_html) - 14}}; + +const struct fsdata_file file_files_footer_plain[] = {{file_control_html, data_files_footer_plain, data_files_footer_plain + 20, sizeof(data_files_footer_plain) - 20}}; + +const struct fsdata_file file_files_header_html[] = {{file_files_footer_plain, data_files_header_html, data_files_header_html + 19, sizeof(data_files_header_html) - 19}}; + +const struct fsdata_file file_stats_footer_plain[] = {{file_files_header_html, data_stats_footer_plain, data_stats_footer_plain + 20, sizeof(data_stats_footer_plain) - 20}}; + +const struct fsdata_file file_stats_header_html[] = {{file_stats_footer_plain, data_stats_header_html, data_stats_header_html + 19, sizeof(data_stats_header_html) - 19}}; + +const struct fsdata_file file_tcp_footer_plain[] = {{file_stats_header_html, data_tcp_footer_plain, data_tcp_footer_plain + 18, sizeof(data_tcp_footer_plain) - 18}}; + +const struct fsdata_file file_tcp_header_html[] = {{file_tcp_footer_plain, data_tcp_header_html, data_tcp_header_html + 17, sizeof(data_tcp_header_html) - 17}}; + +const struct fsdata_file file_img_logo_png[] = {{file_tcp_header_html, data_img_logo_png, data_img_logo_png + 14, sizeof(data_img_logo_png) - 14}}; + +const struct fsdata_file file_cgi_files[] = {{file_img_logo_png, data_cgi_files, data_cgi_files + 11, sizeof(data_cgi_files) - 11}}; + +const struct fsdata_file file_cgi_stats[] = {{file_cgi_files, data_cgi_stats, data_cgi_stats + 11, sizeof(data_cgi_stats) - 11}}; + +const struct fsdata_file file_cgi_tcp[] = {{file_cgi_stats, data_cgi_tcp, data_cgi_tcp + 9, sizeof(data_cgi_tcp) - 9}}; + +const struct fsdata_file file_cgi_rtos[] = {{file_cgi_tcp, data_cgi_rtos, data_cgi_rtos + 10, sizeof(data_cgi_rtos) - 10}}; + +const struct fsdata_file file_index_html[] = {{file_cgi_rtos, data_index_html, data_index_html + 12, sizeof(data_index_html) - 12}}; + +#define FS_ROOT file_index_html + +#define FS_NUMFILES 14 diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/uip/fsdata.h b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/fsdata.h new file mode 100644 index 000000000..94086c4df --- /dev/null +++ b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/fsdata.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: fsdata.h,v 1.4.2.1 2003/10/04 22:54:06 adam Exp $ + */ +#ifndef __FSDATA_H__ +#define __FSDATA_H__ + +#include "uipopt.h" + +struct fsdata_file { + const struct fsdata_file *next; + const char *name; + const char *data; + const int len; +#ifdef FS_STATISTICS +#if FS_STATISTICS == 1 + u16_t count; +#endif /* FS_STATISTICS */ +#endif /* FS_STATISTICS */ +}; + +struct fsdata_file_noconst { + struct fsdata_file *next; + char *name; + char *data; + int len; +#ifdef FS_STATISTICS +#if FS_STATISTICS == 1 + u16_t count; +#endif /* FS_STATISTICS */ +#endif /* FS_STATISTICS */ +}; + +#endif /* __FSDATA_H__ */ diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/uip/httpd.c b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/httpd.c new file mode 100644 index 000000000..108fa26e8 --- /dev/null +++ b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/httpd.c @@ -0,0 +1,372 @@ +/** + * \addtogroup exampleapps + * @{ + */ + +/** + * \defgroup httpd Web server + * @{ + * + * The uIP web server is a very simplistic implementation of an HTTP + * server. It can serve web pages and files from a read-only ROM + * filesystem, and provides a very small scripting language. + * + * The script language is very simple and works as follows. Each + * script line starts with a command character, either "i", "t", "c", + * "#" or ".". The "i" command tells the script interpreter to + * "include" a file from the virtual file system and output it to the + * web browser. The "t" command should be followed by a line of text + * that is to be output to the browser. The "c" command is used to + * call one of the C functions from the httpd-cgi.c file. A line that + * starts with a "#" is ignored (i.e., the "#" denotes a comment), and + * the "." denotes the last script line. + * + * The script that produces the file statistics page looks somewhat + * like this: + * + \code +i /header.html +t

    File statistics


    RemoteStateRetransmissionsTimerFlags
    +t
    /index.html +c a /index.html +t
    /cgi/files +c a /cgi/files +t
    /cgi/tcp +c a /cgi/tcp +t
    /404.html +c a /404.html +t
    +i /footer.plain +. + \endcode + * + */ + + +/** + * \file + * HTTP server. + * \author Adam Dunkels + */ + +/* + * Copyright (c) 2001, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: httpd.c,v 1.28.2.6 2003/10/07 13:22:27 adam Exp $ + * + */ + + +#include "uip.h" +#include "httpd.h" +#include "fs.h" +#include "fsdata.h" +#include "cgi.h" + +#define NULL (void *)0 + +/* The HTTP server states: */ +#define HTTP_NOGET 0 +#define HTTP_FILE 1 +#define HTTP_TEXT 2 +#define HTTP_FUNC 3 +#define HTTP_END 4 + +#ifdef DEBUG +#include +#define PRINT(x) +#define PRINTLN(x) +#else /* DEBUG */ +#define PRINT(x) +#define PRINTLN(x) +#endif /* DEBUG */ + +struct httpd_state *hs; + +extern const struct fsdata_file file_index_html; +extern const struct fsdata_file file_404_html; + +static void next_scriptline(void); +static void next_scriptstate(void); + +#define ISO_G 0x47 +#define ISO_E 0x45 +#define ISO_T 0x54 +#define ISO_slash 0x2f +#define ISO_c 0x63 +#define ISO_g 0x67 +#define ISO_i 0x69 +#define ISO_space 0x20 +#define ISO_nl 0x0a +#define ISO_cr 0x0d +#define ISO_a 0x61 +#define ISO_t 0x74 +#define ISO_hash 0x23 +#define ISO_period 0x2e + +#define httpPORT 80 + +/*-----------------------------------------------------------------------------------*/ +/** + * Initialize the web server. + * + * Starts to listen for incoming connection requests on TCP port 80. + */ +/*-----------------------------------------------------------------------------------*/ +void +httpd_init(void) +{ + fs_init(); + + /* Listen to port 80. */ + uip_listen(HTONS(httpPORT)); +} +/*-----------------------------------------------------------------------------------*/ +void +httpd_appcall(void) +{ + struct fs_file fsfile; + + u8_t i; + + switch(uip_conn->lport) { + /* This is the web server: */ + case HTONS(httpPORT): + /* Pick out the application state from the uip_conn structure. */ + hs = (struct httpd_state *)(uip_conn->appstate); + + /* We use the uip_ test functions to deduce why we were + called. If uip_connected() is non-zero, we were called + because a remote host has connected to us. If + uip_newdata() is non-zero, we were called because the + remote host has sent us new data, and if uip_acked() is + non-zero, the remote host has acknowledged the data we + previously sent to it. */ + if(uip_connected()) { + /* Since we have just been connected with the remote host, we + reset the state for this connection. The ->count variable + contains the amount of data that is yet to be sent to the + remote host, and the ->state is set to HTTP_NOGET to signal + that we haven't received any HTTP GET request for this + connection yet. */ + + hs->state = HTTP_NOGET; + hs->count = 0; + return; + + } else if(uip_poll()) { + /* If we are polled ten times, we abort the connection. This is + because we don't want connections lingering indefinately in + the system. */ + if(hs->count++ >= 10) { + uip_abort(); + } + return; + } else if(uip_newdata() && hs->state == HTTP_NOGET) { + /* This is the first data we receive, and it should contain a + GET. */ + + /* Check for GET. */ + if(uip_appdata[0] != ISO_G || + uip_appdata[1] != ISO_E || + uip_appdata[2] != ISO_T || + uip_appdata[3] != ISO_space) { + /* If it isn't a GET, we abort the connection. */ + uip_abort(); + return; + } + + /* Find the file we are looking for. */ + for(i = 4; i < 40; ++i) { + if(uip_appdata[i] == ISO_space || + uip_appdata[i] == ISO_cr || + uip_appdata[i] == ISO_nl) { + uip_appdata[i] = 0; + break; + } + } + + PRINT("request for file "); + PRINTLN(&uip_appdata[4]); + + /* Check for a request for "/". */ + if(uip_appdata[4] == ISO_slash && + uip_appdata[5] == 0) { + fs_open(file_index_html.name, &fsfile); + } else { + if(!fs_open((const char *)&uip_appdata[4], &fsfile)) { + PRINTLN("couldn't open file"); + fs_open(file_404_html.name, &fsfile); + } + } + + + if(uip_appdata[4] == ISO_slash && + uip_appdata[5] == ISO_c && + uip_appdata[6] == ISO_g && + uip_appdata[7] == ISO_i && + uip_appdata[8] == ISO_slash) { + /* If the request is for a file that starts with "/cgi/", we + prepare for invoking a script. */ + hs->script = fsfile.data; + next_scriptstate(); + } else { + hs->script = NULL; + /* The web server is now no longer in the HTTP_NOGET state, but + in the HTTP_FILE state since is has now got the GET from + the client and will start transmitting the file. */ + hs->state = HTTP_FILE; + + /* Point the file pointers in the connection state to point to + the first byte of the file. */ + hs->dataptr = fsfile.data; + hs->count = fsfile.len; + } + } + + + if(hs->state != HTTP_FUNC) { + /* Check if the client (remote end) has acknowledged any data that + we've previously sent. If so, we move the file pointer further + into the file and send back more data. If we are out of data to + send, we close the connection. */ + if(uip_acked()) { + if(hs->count >= uip_conn->len) { + hs->count -= uip_conn->len; + hs->dataptr += uip_conn->len; + } else { + hs->count = 0; + } + + if(hs->count == 0) { + if(hs->script != NULL) { + next_scriptline(); + next_scriptstate(); + } else { + uip_close(); + } + } + } + } else { + /* Call the CGI function. */ + if(cgitab[hs->script[2] - ISO_a](uip_acked())) { + /* If the function returns non-zero, we jump to the next line + in the script. */ + next_scriptline(); + next_scriptstate(); + } + } + + if(hs->state != HTTP_FUNC && !uip_poll()) { + /* Send a piece of data, but not more than the MSS of the + connection. */ + uip_send(( void * ) hs->dataptr, hs->count); + } + + /* Finally, return to uIP. Our outgoing packet will soon be on its + way... */ + return; + + default: + /* Should never happen. */ + uip_abort(); + break; + } +} +/*-----------------------------------------------------------------------------------*/ +/* next_scriptline(): + * + * Reads the script until it finds a newline. */ +static void +next_scriptline(void) +{ + /* Loop until we find a newline character. */ + do { + ++(hs->script); + } while(hs->script[0] != ISO_nl); + + /* Eat up the newline as well. */ + ++(hs->script); +} +/*-----------------------------------------------------------------------------------*/ +/* next_sciptstate: + * + * Reads one line of script and decides what to do next. + */ +static void +next_scriptstate(void) +{ + struct fs_file fsfile; + long i; + + again: + switch(hs->script[0]) { + case ISO_t: + /* Send a text string. */ + hs->state = HTTP_TEXT; + hs->dataptr = &hs->script[2]; + + /* Calculate length of string. */ + for(i = 0; hs->dataptr[i] != ISO_nl; ++i); + hs->count = i; + break; + case ISO_c: + /* Call a function. */ + hs->state = HTTP_FUNC; + hs->dataptr = NULL; + hs->count = 0; + cgitab[hs->script[2] - ISO_a](0); + break; + case ISO_i: + /* Include a file. */ + hs->state = HTTP_FILE; + if(!fs_open(&hs->script[2], &fsfile)) { + uip_abort(); + } + hs->dataptr = fsfile.data; + hs->count = fsfile.len; + break; + case ISO_hash: + /* Comment line. */ + next_scriptline(); + goto again; + case ISO_period: + /* End of script. */ + hs->state = HTTP_END; + uip_close(); + break; + default: + uip_abort(); + break; + } +} +/*-----------------------------------------------------------------------------------*/ +/** @} */ +/** @} */ diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/uip/httpd.c_ b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/httpd.c_ new file mode 100644 index 000000000..fda240826 --- /dev/null +++ b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/httpd.c_ @@ -0,0 +1,380 @@ +/*$T httpd.c GC 1.138 07/23/05 13:10:49 */ + +/* + * \addtogroup exampleapps @{ £ + * \defgroup httpd Web server @{ The uIP web server is a very simplistic + * implementation of an HTTP server. It can serve web pages and files from a + * read-only ROM filesystem, and provides a very small scripting language. The + * script language is very simple and works as follows. Each script line starts + * with a command character, either "i", "t", "c", "#" or ".". The "i" command + * tells the script interpreter to "include" a file from the virtual file system + * and output it to the web browser. The "t" command should be followed by a line + * of text that is to be output to the browser. The "c" command is used to call + * one of the C functions from the httpd-cgi.c file. A line that starts with a "#" + * is ignored (i.e., the "#" denotes a comment), and the "." denotes the last + * script line. The script that produces the file statistics page looks somewhat + * like this: \code i /header.html t

    File statistics


    t
    /index.html c a + * /index.html t
    /cgi/files c + * a /cgi/files t
    /cgi/tcp c a + * /cgi/tcp t
    /404.html c a + * /404.html t
    i /footer.plain . \endcode £ + * \file HTTP server. \author Adam Dunkels £ + * Copyright (c) 2001, Adam Dunkels. All rights reserved. Redistribution and use + * in source and binary forms, with or without modification, are permitted + * provided that the following conditions are met: 1. Redistributions of source + * code must retain the above copyright notice, this list of conditions and the + * following disclaimer. 2. Redistributions in binary form must reproduce the + * above copyright notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the distribution. 3. The + * name of the author may not be used to endorse or promote products derived from + * this software without specific prior written permission. THIS SOFTWARE IS + * PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND + * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This file is part of the uIP TCP/IP stack. $Id: httpd.c,v 1.28.2.6 2003/10/07 + * 13:22:27 adam Exp $ + */ +#include "uip.h" +#include "httpd.h" +#include "fs.h" +#include "fsdata.h" +#include "cgi.h" + +#define NULL ( void * ) 0 + +/* The HTTP server states: */ +#define HTTP_NOGET 0 +#define HTTP_FILE 1 +#define HTTP_TEXT 2 +#define HTTP_FUNC 3 +#define HTTP_END 4 + +#ifdef DEBUG +#include +#define PRINT( x ) +#define PRINTLN( x ) +#else /* DEBUG */ +#define PRINT( x ) +#define PRINTLN( x ) +#endif /* DEBUG */ + +struct httpd_state *hs; + +extern const struct fsdata_file file_index_html; +extern const struct fsdata_file file_404_html; + +static void next_scriptline( void ); +static void next_scriptstate( void ); + +#define ISO_G 0x47 +#define ISO_E 0x45 +#define ISO_T 0x54 +#define ISO_slash 0x2f +#define ISO_c 0x63 +#define ISO_g 0x67 +#define ISO_i 0x69 +#define ISO_space 0x20 +#define ISO_nl 0x0a +#define ISO_cr 0x0d +#define ISO_a 0x61 +#define ISO_t 0x74 +#define ISO_hash 0x23 +#define ISO_period 0x2e + +#define httpPORT 80 + +/* + ======================================================================================================================= + Initialize the web server. Starts to listen for incoming connection requests on TCP port 80. + ======================================================================================================================= + */ +void httpd_init( void ) +{ + fs_init(); + + /* Listen to port 80. */ + uip_listen( HTONS( httpPORT ) ); +} + +/* + ======================================================================================================================= + ======================================================================================================================= + */ +void httpd_appcall( void ) +{ + /*~~~~~~~~~~~~~~~~~~~*/ + struct fs_file fsfile; + u8_t i; + /*~~~~~~~~~~~~~~~~~~~*/ + + switch( uip_conn->lport ) + { + /* This is the web server: */ + case HTONS( httpPORT ): + /* Pick out the application state from the uip_conn structure. */ + hs = ( struct httpd_state * ) ( uip_conn->appstate ); + + /* + * We use the uip_ test functions to deduce why we were called. If uip_connected() + * is non-zero, we were called because a remote host has connected to us. If + * uip_newdata() is non-zero, we were called because the remote host has sent us + * new data, and if uip_acked() is non-zero, the remote host has acknowledged the + * data we previously sent to it. + */ + if( uip_connected() ) + { + /* + * Since we have just been connected with the remote host, we reset the state for + * this connection. The ->count variable contains the amount of data that is yet + * to be sent to the remote host, and the ->state is set to HTTP_NOGET to signal + * that we haven't received any HTTP GET request for this connection yet. + */ + hs->state = HTTP_NOGET; + hs->count = 0; + return; + } + else if( uip_poll() ) + { + /* + * If we are polled ten times, we abort the connection. This is because we don't + * want connections lingering indefinately in the system. + */ + if( hs->count++ >= 10 ) + { + uip_abort(); + } + + return; + } + else if( uip_newdata() && hs->state == HTTP_NOGET ) + { + /* + * This is the first data we receive, and it should contain a GET. £ + * Check for GET. + */ + if + ( + uip_appdata[0] != ISO_G + || uip_appdata[1] != ISO_E + || uip_appdata[2] != ISO_T + || uip_appdata[3] != ISO_space + ) + { + /* If it isn't a GET, we abort the connection. */ + uip_abort(); + return; + } + + /* Find the file we are looking for. */ + for( i = 4; i < 40; ++i ) + { + if( uip_appdata[i] == ISO_space || uip_appdata[i] == ISO_cr || uip_appdata[i] == ISO_nl ) + { + uip_appdata[i] = 0; + break; + } + } + + PRINT( "request for file " ); + PRINTLN( &uip_appdata[4] ); + + /* Check for a request for "/". */ + if( uip_appdata[4] == ISO_slash && uip_appdata[5] == 0 ) + { + fs_open( file_index_html.name, &fsfile ); + } + else + { + if( !fs_open( ( const char * ) &uip_appdata[4], &fsfile ) ) + { + PRINTLN( "couldn't open file" ); + fs_open( file_404_html.name, &fsfile ); + } + } + + if + ( + uip_appdata[4] == ISO_slash + && uip_appdata[5] == ISO_c + && uip_appdata[6] == ISO_g + && uip_appdata[7] == ISO_i + && uip_appdata[8] == ISO_slash + ) + { + /* + * If the request is for a file that starts with "/cgi/", we prepare for invoking + * a script. + */ + hs->script = fsfile.data; + next_scriptstate(); + } + else + { + hs->script = NULL; + + /* + * The web server is now no longer in the HTTP_NOGET state, but in the HTTP_FILE + * state since is has now got the GET from the client and will start transmitting + * the file. + */ + hs->state = HTTP_FILE; + + /* + * Point the file pointers in the connection state to point to the first byte of + * the file. + */ + hs->dataptr = fsfile.data; + hs->count = fsfile.len; + } + } + + if( hs->state != HTTP_FUNC ) + { + /* + * Check if the client (remote end) has acknowledged any data that we've + * previously sent. If so, we move the file pointer further into the file and send + * back more data. If we are out of data to send, we close the connection. + */ + if( uip_acked() ) + { + if( hs->count >= uip_conn->len ) + { + hs->count -= uip_conn->len; + hs->dataptr += uip_conn->len; + } + else + { + hs->count = 0; + } + + if( hs->count == 0 ) + { + if( hs->script != NULL ) + { + next_scriptline(); + next_scriptstate(); + } + else + { + uip_close(); + } + } + } + } + else + { + /* Call the CGI function. */ + if( cgitab[hs->script[2] - ISO_a](uip_acked()) ) + { + /* If the function returns non-zero, we jump to the next line in the script. */ + next_scriptline(); + next_scriptstate(); + } + } + + if( hs->state != HTTP_FUNC && !uip_poll() ) + { + /* Send a piece of data, but not more than the MSS of the connection. */ + uip_send( ( void * ) hs->dataptr, hs->count ); + } + + /* Finally, return to uIP. Our outgoing packet will soon be on its way... */ + return; + + default: + /* Should never happen. */ + uip_abort(); + break; + } +} + +/* + ======================================================================================================================= + next_scriptline(): Reads the script until it finds a newline. + ======================================================================================================================= + */ +static void next_scriptline( void ) +{ + /* Loop until we find a newline character. */ + do + { + ++( hs->script ); + } while( hs->script[0] != ISO_nl ); + + /* Eat up the newline as well. */ + ++( hs->script ); +} + +/* + ======================================================================================================================= + next_sciptstate: Reads one line of script and decides what to do next. + ======================================================================================================================= + */ +static void next_scriptstate( void ) +{ + /*~~~~~~~~~~~~~~~~~~~*/ + struct fs_file fsfile; + u8_t i; + /*~~~~~~~~~~~~~~~~~~~*/ + +again: + switch( hs->script[0] ) + { + case ISO_t: + /* Send a text string. */ + hs->state = HTTP_TEXT; + hs->dataptr = &hs->script[2]; + + /* Calculate length of string. */ + for( i = 0; hs->dataptr[i] != ISO_nl; ++i ); + hs->count = i; + break; + + case ISO_c: + /* Call a function. */ + hs->state = HTTP_FUNC; + hs->dataptr = NULL; + hs->count = 0; + cgitab[hs->script[2] - ISO_a]( 0 ); + break; + + case ISO_i: + /* Include a file. */ + hs->state = HTTP_FILE; + if( !fs_open( &hs->script[2], &fsfile ) ) + { + uip_abort(); + } + + hs->dataptr = fsfile.data; + hs->count = fsfile.len; + break; + + case ISO_hash: + /* Comment line. */ + next_scriptline(); + goto again; + + case ISO_period: + /* End of script. */ + hs->state = HTTP_END; + uip_close(); + break; + + default: + uip_abort(); + break; + } +} + +/* + * @} £ + * @} + */ diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/uip/httpd.h b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/httpd.h new file mode 100644 index 000000000..34d6bb35f --- /dev/null +++ b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/httpd.h @@ -0,0 +1,77 @@ +/** + * \addtogroup httpd + * @{ + */ + +/** + * \file + * HTTP server header file. + * \author Adam Dunkels + */ + +/* + * Copyright (c) 2001, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: httpd.h,v 1.4.2.3 2003/10/06 22:56:44 adam Exp $ + * + */ + +#ifndef __HTTPD_H__ +#define __HTTPD_H__ + +void httpd_init(void); +void httpd_appcall(void); + +/* UIP_APPCALL: the name of the application function. This function + must return void and take no arguments (i.e., C type "void + appfunc(void)"). */ +#ifndef UIP_APPCALL +#define UIP_APPCALL httpd_appcall +#endif + +struct httpd_state { + u8_t state; + u16_t count; + char *dataptr; + char *script; +}; + + +/* UIP_APPSTATE_SIZE: The size of the application-specific state + stored in the uip_conn structure. */ +#ifndef UIP_APPSTATE_SIZE +#define UIP_APPSTATE_SIZE (sizeof(struct httpd_state)) +#endif + +#define FS_STATISTICS 1 + +extern struct httpd_state *hs; + +#endif /* __HTTPD_H__ */ diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/uip/main_led b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/main_led new file mode 100644 index 000000000..8fe01ea6d --- /dev/null +++ b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/main_led @@ -0,0 +1,67 @@ +// Copyright (c) 2001-2004 Rowley Associates Limited. +// +// This file may be distributed under the terms of the License Agreement +// provided with this software. +// +// THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE +// WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. +// +//////////////////////////////////////////////////////////////////////////////// +// +// Olimex LPC-P1 LED Example +// +// Description +// ----------- +// This example demonstrates writing to the programmable peripheral interface. +// +//////////////////////////////////////////////////////////////////////////////// + +#include + +#define LED_RED (1<<8) +#define LED_GREEN (1<<10) +#define LED_YELLOW (1<<11) + +#define LED1 LED_YELLOW + +static void +ledInit() +{ + IODIR |= LED1; + IOSET = LED1; +} + +static void +ledOn(void) +{ + IOCLR = LED1; +} + +static void +ledOff(void) +{ + IOSET = LED1; +} + +void +delay(int d) +{ + for(; d; --d); +} + +int +main(void) +{ + MAMCR = 2; + ledInit(); + while (1) + { + ledOn(); + delay(100000); + ledOff(); + delay(100000); + } + return 0; +} + + diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/uip/makefsdata b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/makefsdata new file mode 100644 index 000000000..f5f75f174 --- /dev/null +++ b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/makefsdata @@ -0,0 +1,93 @@ +#!/usr/bin/perl + +open(OUTPUT, "> fsdata.c"); + +chdir("fs"); +open(FILES, "find . -type f |"); + +while($file = ) { + + # Do not include files in CVS directories nor backup files. + if($file =~ /(CVS|~)/) { + next; + } + + chop($file); + + open(HEADER, "> /tmp/header") || die $!; + if($file =~ /404.html/) { + print(HEADER "HTTP/1.0 404 File not found\r\n"); + } else { + print(HEADER "HTTP/1.0 200 OK\r\n"); + } + print(HEADER "Server: uIP/0.9 (http://dunkels.com/adam/uip/)\r\n"); + if($file =~ /\.html$/) { + print(HEADER "Content-type: text/html\r\n"); + } elsif($file =~ /\.gif$/) { + print(HEADER "Content-type: image/gif\r\n"); + } elsif($file =~ /\.png$/) { + print(HEADER "Content-type: image/png\r\n"); + } elsif($file =~ /\.jpg$/) { + print(HEADER "Content-type: image/jpeg\r\n"); + } else { + print(HEADER "Content-type: text/plain\r\n"); + } + print(HEADER "\r\n"); + close(HEADER); + + unless($file =~ /\.plain$/ || $file =~ /cgi/) { + system("cat /tmp/header $file > /tmp/file"); + } else { + system("cp $file /tmp/file"); + } + + open(FILE, "/tmp/file"); + unlink("/tmp/file"); + unlink("/tmp/header"); + + $file =~ s/\.//; + $fvar = $file; + $fvar =~ s-/-_-g; + $fvar =~ s-\.-_-g; + print(OUTPUT "static const char data".$fvar."[] = {\n"); + print(OUTPUT "\t/* $file */\n\t"); + for($j = 0; $j < length($file); $j++) { + printf(OUTPUT "%#02x, ", unpack("C", substr($file, $j, 1))); + } + printf(OUTPUT "0,\n"); + + + $i = 0; + while(read(FILE, $data, 1)) { + if($i == 0) { + print(OUTPUT "\t"); + } + printf(OUTPUT "%#02x, ", unpack("C", $data)); + $i++; + if($i == 10) { + print(OUTPUT "\n"); + $i = 0; + } + } + print(OUTPUT "};\n\n"); + close(FILE); + push(@fvars, $fvar); + push(@files, $file); +} + +for($i = 0; $i < @fvars; $i++) { + $file = $files[$i]; + $fvar = $fvars[$i]; + + if($i == 0) { + $prevfile = "NULL"; + } else { + $prevfile = "file" . $fvars[$i - 1]; + } + print(OUTPUT "const struct fsdata_file file".$fvar."[] = {{$prevfile, data$fvar, "); + print(OUTPUT "data$fvar + ". (length($file) + 1) .", "); + print(OUTPUT "sizeof(data$fvar) - ". (length($file) + 1) ."}};\n\n"); +} + +print(OUTPUT "#define FS_ROOT file$fvars[$i - 1]\n\n"); +print(OUTPUT "#define FS_NUMFILES $i"); diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/uip/memb.c b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/memb.c new file mode 100644 index 000000000..56e663446 --- /dev/null +++ b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/memb.c @@ -0,0 +1,152 @@ +/** + * \addtogroup exampleapps + * @{ + */ + +/** + * \file + * Memory block allocation routines. + * \author Adam Dunkels + * + * The memory block allocation routines provide a simple yet powerful + * set of functions for managing a set of memory blocks of fixed + * size. A set of memory blocks is statically declared with the + * MEMB() macro. Memory blocks are allocated from the declared + * memory by the memb_alloc() function, and are deallocated with the + * memb_free() function. + * + * \note Because of namespace clashes only one MEMB() can be + * declared per C module, and the name scope of a MEMB() memory + * block is local to each C module. + * + * The following example shows how to declare and use a memory block + * called "cmem" which has 8 chunks of memory with each memory chunk + * being 20 bytes large. + * + \code + MEMB(cmem, 20, 8); + + int main(int argc, char *argv[]) { + char *ptr; + + memb_init(&cmem); + + ptr = memb_alloc(&cmem); + + if(ptr != NULL) { + do_something(ptr); + } else { + printf("Could not allocate memory.\n"); + } + + if(memb_free(ptr) == 0) { + printf("Deallocation succeeded.\n"); + } + } + \endcode + * + */ + +#include + +#include "memb.h" + +/*------------------------------------------------------------------------------*/ +/** + * Initialize a memory block that was declared with MEMB(). + * + * \param m A memory block previosly declared with MEMB(). + */ +/*------------------------------------------------------------------------------*/ +void +memb_init(struct memb_blocks *m) +{ + memset(m->mem, (m->size + 1) * m->num, 0); +} +/*------------------------------------------------------------------------------*/ +/** + * Allocate a memory block from a block of memory declared with MEMB(). + * + * \param m A memory block previosly declared with MEMB(). + */ +/*------------------------------------------------------------------------------*/ +char * +memb_alloc(struct memb_blocks *m) +{ + int i; + char *ptr; + + ptr = m->mem; + for(i = 0; i < m->num; ++i) { + if(*ptr == 0) { + /* If this block was unused, we increase the reference count to + indicate that it now is used and return a pointer to the + first byte following the reference counter. */ + ++*ptr; + return ptr + 1; + } + ptr += m->size + 1; + } + + /* No free block was found, so we return NULL to indicate failure to + allocate block. */ + return NULL; +} +/*------------------------------------------------------------------------------*/ +/** + * Deallocate a memory block from a memory block previously declared + * with MEMB(). + * + * \param m m A memory block previosly declared with MEMB(). + * + * \param ptr A pointer to the memory block that is to be deallocated. + * + * \return The new reference count for the memory block (should be 0 + * if successfully deallocated) or -1 if the pointer "ptr" did not + * point to a legal memory block. + */ +/*------------------------------------------------------------------------------*/ +char +memb_free(struct memb_blocks *m, char *ptr) +{ + int i; + char *ptr2; + + /* Walk through the list of blocks and try to find the block to + which the pointer "ptr" points to. */ + ptr2 = m->mem; + for(i = 0; i < m->num; ++i) { + + if(ptr2 == ptr - 1) { + /* We've found to block to which "ptr" points so we decrease the + reference count and return the new value of it. */ + return --*ptr2; + } + ptr2 += m->size + 1; + } + return -1; +} +/*------------------------------------------------------------------------------*/ +/** + * Increase the reference count for a memory chunk. + * + * \note No sanity checks are currently made. + * + * \param m m A memory block previosly declared with MEMB(). + * + * \param ptr A pointer to the memory chunk for which the reference + * count should be increased. + * + * \return The new reference count. + */ +/*------------------------------------------------------------------------------*/ +char +memb_ref(struct memb_blocks *m, char *ptr) +{ + return ++*(ptr - 1); +} +/*------------------------------------------------------------------------------*/ + + + + diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/uip/memb.h b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/memb.h new file mode 100644 index 000000000..505846f4d --- /dev/null +++ b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/memb.h @@ -0,0 +1,43 @@ +/** + * \addtogroup exampleapps + * @{ + */ + +/** + * \file + * Memory block allocation routines. + * \author Adam Dunkels + * + */ + +#ifndef __MEMB_H__ +#define __MEMB_H__ + +/** + * Declare a memory block. + * + * \param name The name of the memory block (later used with + * memb_init(), memb_alloc() and memb_free()). + * + * \param size The size of each memory chunk, in bytes. + * + * \param num The total number of memory chunks in the block. + * + */ +#define MEMB(name, size, num) \ + static char memb_mem[(size + 1) * num]; \ + static struct memb_blocks name = {size, num, memb_mem} + +struct memb_blocks { + unsigned short size; + unsigned short num; + char *mem; +}; + +void memb_init(struct memb_blocks *m); +char *memb_alloc(struct memb_blocks *m); +char memb_ref(struct memb_blocks *m, char *ptr); +char memb_free(struct memb_blocks *m, char *ptr); + + +#endif /* __MEMB_H__ */ diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/uip/setarp.bat b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/setarp.bat new file mode 100644 index 000000000..7f5babb3f --- /dev/null +++ b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/setarp.bat @@ -0,0 +1 @@ +arp -s 172.25.218.210 00-bd-3b-33-05-72 diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/uip/slipdev.c b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/slipdev.c new file mode 100644 index 000000000..fc968c82e --- /dev/null +++ b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/slipdev.c @@ -0,0 +1,202 @@ +/** + * \addtogroup uip + * @{ + */ + +/** + * \defgroup slip Serial Line IP (SLIP) protocol + * @{ + * + * The SLIP protocol is a very simple way to transmit IP packets over + * a serial line. It does not provide any framing or error control, + * and is therefore not very widely used today. + * + * This SLIP implementation requires two functions for accessing the + * serial device: slipdev_char_poll() and slipdev_char_put(). These + * must be implemented specifically for the system on which the SLIP + * protocol is to be run. + */ + +/** + * \file + * SLIP protocol implementation + * \author Adam Dunkels + */ + +/* + * Copyright (c) 2001, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: slipdev.c,v 1.1.2.3 2003/10/07 13:23:01 adam Exp $ + * + */ + +/* + * This is a generic implementation of the SLIP protocol over an RS232 + * (serial) device. + * + * Huge thanks to Ullrich von Bassewitz of cc65 fame for + * and endless supply of bugfixes, insightsful comments and + * suggestions, and improvements to this code! + */ + +#include "uip.h" + +#define SLIP_END 0300 +#define SLIP_ESC 0333 +#define SLIP_ESC_END 0334 +#define SLIP_ESC_ESC 0335 + +static u8_t slip_buf[UIP_BUFSIZE]; + +static u16_t len, tmplen; +static u8_t lastc; + +/*-----------------------------------------------------------------------------------*/ +/** + * Send the packet in the uip_buf and uip_appdata buffers using the + * SLIP protocol. + * + * The first 40 bytes of the packet (the IP and TCP headers) are read + * from the uip_buf buffer, and the following bytes (the application + * data) are read from the uip_appdata buffer. + * + */ +/*-----------------------------------------------------------------------------------*/ +void +slipdev_send(void) +{ + u16_t i; + u8_t *ptr; + u8_t c; + + slipdev_char_put(SLIP_END); + + ptr = uip_buf; + for(i = 0; i < uip_len; ++i) { + if(i == 40) { + ptr = (u8_t *)uip_appdata; + } + c = *ptr++; + switch(c) { + case SLIP_END: + slipdev_char_put(SLIP_ESC); + slipdev_char_put(SLIP_ESC_END); + break; + case SLIP_ESC: + slipdev_char_put(SLIP_ESC); + slipdev_char_put(SLIP_ESC_ESC); + break; + default: + slipdev_char_put(c); + break; + } + } + slipdev_char_put(SLIP_END); +} +/*-----------------------------------------------------------------------------------*/ +/** + * Poll the SLIP device for an available packet. + * + * This function will poll the SLIP device to see if a packet is + * available. It uses a buffer in which all avaliable bytes from the + * RS232 interface are read into. When a full packet has been read + * into the buffer, the packet is copied into the uip_buf buffer and + * the length of the packet is returned. + * + * \return The length of the packet placed in the uip_buf buffer, or + * zero if no packet is available. + */ +/*-----------------------------------------------------------------------------------*/ +u16_t +slipdev_poll(void) +{ + u8_t c; + + while(slipdev_char_poll(c)) { + switch(c) { + case SLIP_ESC: + lastc = c; + break; + + case SLIP_END: + lastc = c; + /* End marker found, we copy our input buffer to the uip_buf + buffer and return the size of the packet we copied. */ + memcpy(uip_buf, slip_buf, len); + tmplen = len; + len = 0; + return tmplen; + + default: + if(lastc == SLIP_ESC) { + lastc = c; + /* Previous read byte was an escape byte, so this byte will be + interpreted differently from others. */ + switch(c) { + case SLIP_ESC_END: + c = SLIP_END; + break; + case SLIP_ESC_ESC: + c = SLIP_ESC; + break; + } + } else { + lastc = c; + } + + slip_buf[len] = c; + ++len; + + if(len > UIP_BUFSIZE) { + len = 0; + } + + break; + } + } + return 0; +} +/*-----------------------------------------------------------------------------------*/ +/** + * Initialize the SLIP module. + * + * This function does not initialize the underlying RS232 device, but + * only the SLIP part. + */ +/*-----------------------------------------------------------------------------------*/ +void +slipdev_init(void) +{ + lastc = len = 0; +} +/*-----------------------------------------------------------------------------------*/ + +/** @} */ +/** @} */ diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/uip/slipdev.h b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/slipdev.h new file mode 100644 index 000000000..3fbfe2d2d --- /dev/null +++ b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/slipdev.h @@ -0,0 +1,88 @@ +/** + * \addtogroup slip + * @{ + */ + +/** + * \file + * SLIP header file. + * \author Adam Dunkels + */ + +/* + * Copyright (c) 2001, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: slipdev.h,v 1.1.2.3 2003/10/06 22:42:51 adam Exp $ + * + */ + +#ifndef __SLIPDEV_H__ +#define __SLIPDEV_H__ + +#include "uip.h" + +/** + * Put a character on the serial device. + * + * This function is used by the SLIP implementation to put a character + * on the serial device. It must be implemented specifically for the + * system on which the SLIP implementation is to be run. + * + * \param c The character to be put on the serial device. + */ +void slipdev_char_put(u8_t c); + +/** + * Poll the serial device for a character. + * + * This function is used by the SLIP implementation to poll the serial + * device for a character. It must be implemented specifically for the + * system on which the SLIP implementation is to be run. + * + * The function should return immediately regardless if a character is + * available or not. If a character is available it should be placed + * at the memory location pointed to by the pointer supplied by the + * arguement c. + * + * \param c A pointer to a byte that is filled in by the function with + * the received character, if available. + * + * \retval 0 If no character is available. + * \retval Non-zero If a character is available. + */ +u8_t slipdev_char_poll(u8_t *c); + +void slipdev_init(void); +void slipdev_send(void); +u16_t slipdev_poll(void); + +#endif /* __SLIPDEV_H__ */ + +/** @} */ diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/uip/tapdev.c b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/tapdev.c new file mode 100644 index 000000000..0d23fc4d9 --- /dev/null +++ b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/tapdev.c @@ -0,0 +1,171 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * Author: Adam Dunkels + * + * $Id: tapdev.c,v 1.7.2.1 2003/10/07 13:23:19 adam Exp $ + */ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef linux +#include +#include +#include +#define DEVTAP "/dev/net/tun" +#else /* linux */ +#define DEVTAP "/dev/tap0" +#endif /* linux */ + +#include "uip.h" + +static int fd; + +static unsigned long lasttime; +static struct timezone tz; + +/*-----------------------------------------------------------------------------------*/ +void +tapdev_init(void) +{ + char buf[1024]; + + fd = open(DEVTAP, O_RDWR); + if(fd == -1) { + perror("tapdev: tapdev_init: open"); + exit(1); + } + +#ifdef linux + { + struct ifreq ifr; + memset(&ifr, 0, sizeof(ifr)); + ifr.ifr_flags = IFF_TAP|IFF_NO_PI; + if (ioctl(fd, TUNSETIFF, (void *) &ifr) < 0) { + perror(buf); + exit(1); + } + } +#endif /* Linux */ + + snprintf(buf, sizeof(buf), "ifconfig tap0 inet %d.%d.%d.%d", + UIP_DRIPADDR0, UIP_DRIPADDR1, UIP_DRIPADDR2, UIP_DRIPADDR3); + system(buf); + + lasttime = 0; +} +/*-----------------------------------------------------------------------------------*/ +unsigned int +tapdev_read(void) +{ + fd_set fdset; + struct timeval tv, now; + int ret; + + if(lasttime >= 500000) { + lasttime = 0; + return 0; + } + + tv.tv_sec = 0; + tv.tv_usec = 500000 - lasttime; + + + FD_ZERO(&fdset); + FD_SET(fd, &fdset); + + gettimeofday(&now, &tz); + ret = select(fd + 1, &fdset, NULL, NULL, &tv); + if(ret == 0) { + lasttime = 0; + return 0; + } + ret = read(fd, uip_buf, UIP_BUFSIZE); + if(ret == -1) { + perror("tap_dev: tapdev_read: read"); + } + gettimeofday(&tv, &tz); + lasttime += (tv.tv_sec - now.tv_sec) * 1000000 + (tv.tv_usec - now.tv_usec); + + return ret; +} +/*-----------------------------------------------------------------------------------*/ +void +tapdev_send(void) +{ + int ret; + struct iovec iov[2]; + +#ifdef linux + { + char tmpbuf[UIP_BUFSIZE]; + int i; + + for(i = 0; i < 40 + UIP_LLH_LEN; i++) { + tmpbuf[i] = uip_buf[i]; + } + + for(; i < uip_len; i++) { + tmpbuf[i] = uip_appdata[i - 40 - UIP_LLH_LEN]; + } + + ret = write(fd, tmpbuf, uip_len); + } +#else + + if(uip_len < 40 + UIP_LLH_LEN) { + ret = write(fd, uip_buf, uip_len + UIP_LLH_LEN); + } else { + iov[0].iov_base = uip_buf; + iov[0].iov_len = 40 + UIP_LLH_LEN; + iov[1].iov_base = (char *)uip_appdata; + iov[1].iov_len = uip_len - (40 + UIP_LLH_LEN); + + ret = writev(fd, iov, 2); + } +#endif + if(ret == -1) { + perror("tap_dev: tapdev_send: writev"); + exit(1); + } +} +/*-----------------------------------------------------------------------------------*/ diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/uip/tapdev.h b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/tapdev.h new file mode 100644 index 000000000..66f1a4a71 --- /dev/null +++ b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/tapdev.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2001, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: tapdev.h,v 1.1.2.1 2003/10/04 22:54:17 adam Exp $ + * + */ + +#ifndef __TAPDEV_H__ +#define __TAPDEV_H__ + +void tapdev_init(void); +unsigned int tapdev_read(void); +void tapdev_send(void); + +#endif /* __TAPDEV_H__ */ diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/uip/telnetd-shell.c b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/telnetd-shell.c new file mode 100644 index 000000000..7dff714ca --- /dev/null +++ b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/telnetd-shell.c @@ -0,0 +1,181 @@ +/** + * \addtogroup telnetd + * @{ + */ + +/** + * \file + * An example telnet server shell + * \author Adam Dunkels + */ + +/* + * Copyright (c) 2003, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the Contiki desktop OS. + * + * $Id: telnetd-shell.c,v 1.1.2.1 2003/10/06 22:56:22 adam Exp $ + * + */ + +#include "uip.h" +#include "telnetd.h" +#include + +struct ptentry { + char c; + void (* pfunc)(struct telnetd_state *s, char *str); +}; + +/*-----------------------------------------------------------------------------------*/ +static void +parse(struct telnetd_state *s, register char *str, struct ptentry *t) +{ + register struct ptentry *p; + char *sstr; + + sstr = str; + + /* Loop over the parse table entries in t in order to find one that + matches the first character in str. */ + for(p = t; p->c != 0; ++p) { + if(*str == p->c) { + /* Skip rest of the characters up to the first space. */ + while(*str != ' ') { + ++str; + } + + /* Skip all spaces.*/ + while(*str == ' ') { + ++str; + } + + /* Call parse table entry function and return. */ + p->pfunc(s, str); + return; + } + } + + /* Did not find matching entry in parse table. We just call the + default handler supplied by the caller and return. */ + p->pfunc(s, str); +} +/*-----------------------------------------------------------------------------------*/ +static void +exitt(struct telnetd_state *s, char *str) +{ + telnetd_close(s); +} +/*-----------------------------------------------------------------------------------*/ +static void +inttostr(register char *str, unsigned int i) +{ + str[0] = '0' + i / 100; + if(str[0] == '0') { + str[0] = ' '; + } + str[1] = '0' + (i / 10) % 10; + if(str[1] == '0') { + str[1] = ' '; + } + str[2] = '0' + i % 10; + str[3] = ' '; + str[4] = 0; +} +/*-----------------------------------------------------------------------------------*/ +static void +stats(struct telnetd_state *s, char *strr) +{ + char str[10]; + + inttostr(str, uip_stat.ip.recv); + telnetd_output(s, "IP packets received ", str); + inttostr(str, uip_stat.ip.sent); + telnetd_output(s, "IP packets sent ", str); + inttostr(str, uip_stat.ip.drop); + telnetd_output(s, "IP packets dropped ", str); + + inttostr(str, uip_stat.icmp.recv); + telnetd_output(s, "ICMP packets received ", str); + inttostr(str, uip_stat.icmp.sent); + telnetd_output(s, "ICMP packets sent ", str); + inttostr(str, uip_stat.icmp.drop); + telnetd_output(s, "ICMP packets dropped ", str); + + inttostr(str, uip_stat.tcp.recv); + telnetd_output(s, "TCP packets received ", str); + inttostr(str, uip_stat.tcp.sent); + telnetd_output(s, "TCP packets sent ", str); + inttostr(str, uip_stat.tcp.drop); + telnetd_output(s, "TCP packets dropped ", str); + inttostr(str, uip_stat.tcp.rexmit); + telnetd_output(s, "TCP packets retransmitted ", str); + inttostr(str, uip_stat.tcp.synrst); + telnetd_output(s, "TCP connection attempts ", str); +} +/*-----------------------------------------------------------------------------------*/ +static void +help(struct telnetd_state *s, char *str) +{ + telnetd_output(s, "Available commands:", ""); + telnetd_output(s, "stats - show uIP statistics", ""); + telnetd_output(s, "exit - exit shell", ""); + telnetd_output(s, "? - show this help", ""); +} +/*-----------------------------------------------------------------------------------*/ +static void +none(struct telnetd_state *s, char *str) +{ + if(strlen(str) > 0) { + telnetd_output(s, "Unknown command", ""); + } +} +/*-----------------------------------------------------------------------------------*/ +static struct ptentry configparsetab[] = + {{'s', stats}, + {'e', exitt}, + {'?', help}, + + /* Default action */ + {0, none}}; +/*-----------------------------------------------------------------------------------*/ +void +telnetd_connected(struct telnetd_state *s) +{ + telnetd_output(s, "uIP command shell", ""); + telnetd_output(s, "Type '?' for help", ""); + telnetd_prompt(s, "uIP-0.9> "); +} +/*-----------------------------------------------------------------------------------*/ +void +telnetd_input(struct telnetd_state *s, char *cmd) +{ + parse(s, cmd, configparsetab); + telnetd_prompt(s, "uIP-0.9> "); +} +/*-----------------------------------------------------------------------------------*/ diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/uip/telnetd.c b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/telnetd.c new file mode 100644 index 000000000..dba522271 --- /dev/null +++ b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/telnetd.c @@ -0,0 +1,392 @@ +/** + * \addtogroup exampleapps + * @{ + */ + +/** + * \defgroup telnetd Telnet server + * @{ + * + * The uIP telnet server provides a command based interface to uIP. It + * allows using the "telnet" application to access uIP, and implements + * the required telnet option negotiation. + * + * The code is structured in a way which makes it possible to add + * commands without having to rewrite the main telnet code. The main + * telnet code calls two callback functions, telnetd_connected() and + * telnetd_input(), when a telnet connection has been established and + * when a line of text arrives on a telnet connection. These two + * functions can be implemented in a way which suits the particular + * application or environment in which the uIP system is intended to + * be run. + * + * The uIP distribution contains an example telnet shell + * implementation that provides a basic set of commands. + */ + +/** + * \file + * Implementation of the Telnet server. + * \author Adam Dunkels + */ + +/* + * Copyright (c) 2003, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: telnetd.c,v 1.1.2.2 2003/10/07 13:47:50 adam Exp $ + * + */ + +#include "uip.h" +#include "memb.h" +#include "telnetd.h" +#include + +#define ISO_nl 0x0a +#define ISO_cr 0x0d + +MEMB(linemem, TELNETD_LINELEN, TELNETD_NUMLINES); + +static u8_t i; + +#define STATE_NORMAL 0 +#define STATE_IAC 1 +#define STATE_WILL 2 +#define STATE_WONT 3 +#define STATE_DO 4 +#define STATE_DONT 5 +#define STATE_CLOSE 6 + +#define TELNET_IAC 255 +#define TELNET_WILL 251 +#define TELNET_WONT 252 +#define TELNET_DO 253 +#define TELNET_DONT 254 +/*-----------------------------------------------------------------------------------*/ +static char * +alloc_line(void) +{ + return memb_alloc(&linemem); +} +/*-----------------------------------------------------------------------------------*/ +static void +dealloc_line(char *line) +{ + memb_free(&linemem, line); +} +/*-----------------------------------------------------------------------------------*/ +static void +sendline(struct telnetd_state *s, char *line) +{ + static unsigned int i; + for(i = 0; i < TELNETD_NUMLINES; ++i) { + if(s->lines[i] == NULL) { + s->lines[i] = line; + break; + } + } + if(i == TELNETD_NUMLINES) { + dealloc_line(line); + } +} +/*-----------------------------------------------------------------------------------*/ +/** + * Close a telnet session. + * + * This function can be called from a telnet command in order to close + * the connection. + * + * \param s The connection which is to be closed. + * + */ +/*-----------------------------------------------------------------------------------*/ +void +telnetd_close(struct telnetd_state *s) +{ + s->state = STATE_CLOSE; +} +/*-----------------------------------------------------------------------------------*/ +/** + * Print a prompt on a telnet connection. + * + * This function can be called by the telnet command shell in order to + * print out a command prompt. + * + * \param s A telnet connection. + * + * \param str The command prompt. + * + */ +/*-----------------------------------------------------------------------------------*/ +void +telnetd_prompt(struct telnetd_state *s, char *str) +{ + char *line; + line = alloc_line(); + if(line != NULL) { + strncpy(line, str, TELNETD_LINELEN); + sendline(s, line); + } +} +/*-----------------------------------------------------------------------------------*/ +/** + * Print out a string on a telnet connection. + * + * This function can be called from a telnet command parser in order + * to print out a string of text on the connection. The two strings + * given as arguments to the function will be concatenated, a carrige + * return and a new line character will be added, and the line is + * sent. + * + * \param s The telnet connection. + * + * \param str1 The first string. + * + * \param str2 The second string. + * + */ +/*-----------------------------------------------------------------------------------*/ +void +telnetd_output(struct telnetd_state *s, char *str1, char *str2) +{ + static unsigned len; + char *line; + + line = alloc_line(); + if(line != NULL) { + len = strlen(str1); + strncpy(line, str1, TELNETD_LINELEN); + if(len < TELNETD_LINELEN) { + strncpy(line + len, str2, TELNETD_LINELEN - len); + } + len = strlen(line); + if(len < TELNETD_LINELEN - 2) { + line[len] = ISO_cr; + line[len+1] = ISO_nl; + line[len+2] = 0; + } + sendline(s, line); + } +} +/*-----------------------------------------------------------------------------------*/ +/** + * Initialize the telnet server. + * + * This function will perform the necessary initializations and start + * listening on TCP port 23. + */ +/*-----------------------------------------------------------------------------------*/ +void +telnetd_init(void) +{ + memb_init(&linemem); + uip_listen(HTONS(23)); +} +/*-----------------------------------------------------------------------------------*/ +static void +acked(struct telnetd_state *s) +{ + dealloc_line(s->lines[0]); + for(i = 1; i < TELNETD_NUMLINES; ++i) { + s->lines[i - 1] = s->lines[i]; + } +} +/*-----------------------------------------------------------------------------------*/ +static void +senddata(struct telnetd_state *s) +{ + if(s->lines[0] != NULL) { + uip_send(s->lines[0], strlen(s->lines[0])); + } +} +/*-----------------------------------------------------------------------------------*/ +static void +getchar(struct telnetd_state *s, u8_t c) +{ + if(c == ISO_cr) { + return; + } + + s->buf[(int)s->bufptr] = c; + if(s->buf[(int)s->bufptr] == ISO_nl || + s->bufptr == sizeof(s->buf) - 1) { + if(s->bufptr > 0) { + s->buf[(int)s->bufptr] = 0; + } + telnetd_input(s, s->buf); + s->bufptr = 0; + } else { + ++s->bufptr; + } +} +/*-----------------------------------------------------------------------------------*/ +static void +sendopt(struct telnetd_state *s, u8_t option, u8_t value) +{ + char *line; + line = alloc_line(); + if(line != NULL) { + line[0] = TELNET_IAC; + line[1] = option; + line[2] = value; + line[3] = 0; + sendline(s, line); + } +} +/*-----------------------------------------------------------------------------------*/ +static void +newdata(struct telnetd_state *s) +{ + u16_t len; + u8_t c; + + + len = uip_datalen(); + + while(len > 0 && s->bufptr < sizeof(s->buf)) { + c = *uip_appdata; + ++uip_appdata; + --len; + switch(s->state) { + case STATE_IAC: + if(c == TELNET_IAC) { + getchar(s, c); + s->state = STATE_NORMAL; + } else { + switch(c) { + case TELNET_WILL: + s->state = STATE_WILL; + break; + case TELNET_WONT: + s->state = STATE_WONT; + break; + case TELNET_DO: + s->state = STATE_DO; + break; + case TELNET_DONT: + s->state = STATE_DONT; + break; + default: + s->state = STATE_NORMAL; + break; + } + } + break; + case STATE_WILL: + /* Reply with a DONT */ + sendopt(s, TELNET_DONT, c); + s->state = STATE_NORMAL; + break; + + case STATE_WONT: + /* Reply with a DONT */ + sendopt(s, TELNET_DONT, c); + s->state = STATE_NORMAL; + break; + case STATE_DO: + /* Reply with a WONT */ + sendopt(s, TELNET_WONT, c); + s->state = STATE_NORMAL; + break; + case STATE_DONT: + /* Reply with a WONT */ + sendopt(s, TELNET_WONT, c); + s->state = STATE_NORMAL; + break; + case STATE_NORMAL: + if(c == TELNET_IAC) { + s->state = STATE_IAC; + } else { + getchar(s, c); + } + break; + } + + + } + +} +/*-----------------------------------------------------------------------------------*/ +void +telnetd_app(void) +{ + struct telnetd_state *s; + + s = (struct telnetd_state *)uip_conn->appstate; + + if(uip_connected()) { + + for(i = 0; i < TELNETD_NUMLINES; ++i) { + s->lines[i] = NULL; + } + s->bufptr = 0; + s->state = STATE_NORMAL; + + telnetd_connected(s); + senddata(s); + return; + } + + if(s->state == STATE_CLOSE) { + s->state = STATE_NORMAL; + uip_close(); + return; + } + + if(uip_closed()) { + telnetd_output(s, "Connection closed", ""); + } + + + if(uip_aborted()) { + telnetd_output(s, "Connection reset", ""); + } + + if(uip_timedout()) { + telnetd_output(s, "Connection timed out", ""); + } + + if(uip_acked()) { + acked(s); + } + + if(uip_newdata()) { + newdata(s); + } + + if(uip_rexmit() || + uip_newdata() || + uip_acked()) { + senddata(s); + } else if(uip_poll()) { + senddata(s); + } +} +/*-----------------------------------------------------------------------------------*/ diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/uip/telnetd.h b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/telnetd.h new file mode 100644 index 000000000..254e44ff1 --- /dev/null +++ b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/telnetd.h @@ -0,0 +1,114 @@ +/** + * \addtogroup telnetd + * @{ + */ + +/** + * \file + * Header file for the telnet server. + * \author Adam Dunkels + */ + +/* + * Copyright (c) 2002, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: telnetd.h,v 1.1.2.2 2003/10/07 13:22:27 adam Exp $ + * + */ +#ifndef __TELNETD_H__ +#define __TELNETD_H__ + +#include "uip.h" + +/** + * The maximum length of a telnet line. + * + * \hideinitializer + */ +#define TELNETD_LINELEN 36 + +/** + * The number of output lines being buffered for all telnet + * connections. + * + * \hideinitializer + */ +#define TELNETD_NUMLINES 2 + +/** + * A telnet connection structure. + */ +struct telnetd_state { + char *lines[TELNETD_NUMLINES]; + char buf[TELNETD_LINELEN]; + char bufptr; + u8_t state; +}; + + +/** + * Callback function that is called when a telnet connection has been + * established. + * + * \param s The telnet connection. + */ +void telnetd_connected(struct telnetd_state *s); + +/** + * Callback function that is called when a line of text has arrived on + * a telnet connection. + * + * \param s The telnet connection. + * + * \param cmd The line of text. + */ +void telnetd_input(struct telnetd_state *s, char *cmd); + + +void telnetd_close(struct telnetd_state *s); +void telnetd_output(struct telnetd_state *s, char *s1, char *s2); +void telnetd_prompt(struct telnetd_state *s, char *str); + +void telnetd_app(void); + +#ifndef UIP_APPCALL +#define UIP_APPCALL telnetd_app +#endif + +#ifndef UIP_APPSTATE_SIZE +#define UIP_APPSTATE_SIZE (sizeof(struct telnetd_state)) +#endif + +void telnetd_init(void); + + +#endif /* __TELNET_H__ */ + +/** @} */ diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/uip/uip.c b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/uip.c new file mode 100644 index 000000000..37f64facc --- /dev/null +++ b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/uip.c @@ -0,0 +1,1514 @@ +/** + * \addtogroup uip + * @{ + */ + +/** + * \file + * The uIP TCP/IP stack code. + * \author Adam Dunkels + */ + +/* + * Copyright (c) 2001-2003, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: uip.c,v 1.62.2.10 2003/10/07 13:23:01 adam Exp $ + * + */ + +/* +This is a small implementation of the IP and TCP protocols (as well as +some basic ICMP stuff). The implementation couples the IP, TCP and the +application layers very tightly. To keep the size of the compiled code +down, this code also features heavy usage of the goto statement. + +The principle is that we have a small buffer, called the uip_buf, in +which the device driver puts an incoming packet. The TCP/IP stack +parses the headers in the packet, and calls upon the application. If +the remote host has sent data to the application, this data is present +in the uip_buf and the application read the data from there. It is up +to the application to put this data into a byte stream if needed. The +application will not be fed with data that is out of sequence. + +If the application whishes to send data to the peer, it should put its +data into the uip_buf, 40 bytes from the start of the buffer. The +TCP/IP stack will calculate the checksums, and fill in the necessary +header fields and finally send the packet back to the peer. +*/ + +#include "uip.h" +#include "uipopt.h" +#include "uip_arch.h" + +/*-----------------------------------------------------------------------------------*/ +/* Variable definitions. */ + + +/* The IP address of this host. If it is defined to be fixed (by setting UIP_FIXEDADDR to 1 in uipopt.h), the address is set here. Otherwise, the address */ +#if UIP_FIXEDADDR > 0 +const u16_t uip_hostaddr[2] = + {HTONS((UIP_IPADDR0 << 8) | UIP_IPADDR1), + HTONS((UIP_IPADDR2 << 8) | UIP_IPADDR3)}; +const u16_t uip_arp_draddr[2] = + {HTONS((UIP_DRIPADDR0 << 8) | UIP_DRIPADDR1), + HTONS((UIP_DRIPADDR2 << 8) | UIP_DRIPADDR3)}; +const u16_t uip_arp_netmask[2] = + {HTONS((UIP_NETMASK0 << 8) | UIP_NETMASK1), + HTONS((UIP_NETMASK2 << 8) | UIP_NETMASK3)}; +#else +u16_t uip_hostaddr[2]; +u16_t uip_arp_draddr[2], uip_arp_netmask[2]; +#endif /* UIP_FIXEDADDR */ + +u8_t uip_buf[UIP_BUFSIZE+2]; /* The packet buffer that contains + incoming packets. */ +volatile u8_t *uip_appdata; /* The uip_appdata pointer points to + application data. */ +volatile u8_t *uip_sappdata; /* The uip_appdata pointer points to the + application data which is to be sent. */ +#if UIP_URGDATA > 0 +volatile u8_t *uip_urgdata; /* The uip_urgdata pointer points to + urgent data (out-of-band data), if + present. */ +volatile u8_t uip_urglen, uip_surglen; +#endif /* UIP_URGDATA > 0 */ + +volatile u16_t uip_len, uip_slen; + /* The uip_len is either 8 or 16 bits, + depending on the maximum packet + size. */ + +volatile u8_t uip_flags; /* The uip_flags variable is used for + communication between the TCP/IP stack + and the application program. */ +struct uip_conn *uip_conn; /* uip_conn always points to the current + connection. */ + +struct uip_conn uip_conns[UIP_CONNS]; + /* The uip_conns array holds all TCP + connections. */ +u16_t uip_listenports[UIP_LISTENPORTS]; + /* The uip_listenports list all currently + listning ports. */ +#if UIP_UDP +struct uip_udp_conn *uip_udp_conn; +struct uip_udp_conn uip_udp_conns[UIP_UDP_CONNS]; +#endif /* UIP_UDP */ + + +static u16_t ipid; /* Ths ipid variable is an increasing + number that is used for the IP ID + field. */ + +static u8_t iss[4]; /* The iss variable is used for the TCP + initial sequence number. */ + +#if UIP_ACTIVE_OPEN +static u16_t lastport; /* Keeps track of the last port used for + a new connection. */ +#endif /* UIP_ACTIVE_OPEN */ + +/* Temporary variables. */ +volatile u8_t uip_acc32[4]; +static u8_t c, opt; +static u16_t tmp16; + +/* Structures and definitions. */ +#define TCP_FIN 0x01 +#define TCP_SYN 0x02 +#define TCP_RST 0x04 +#define TCP_PSH 0x08 +#define TCP_ACK 0x10 +#define TCP_URG 0x20 +#define TCP_CTL 0x3f + +#define ICMP_ECHO_REPLY 0 +#define ICMP_ECHO 8 + +/* Macros. */ +#define BUF ((uip_tcpip_hdr *)&uip_buf[UIP_LLH_LEN]) +#define FBUF ((uip_tcpip_hdr *)&uip_reassbuf[0]) +#define ICMPBUF ((uip_icmpip_hdr *)&uip_buf[UIP_LLH_LEN]) +#define UDPBUF ((uip_udpip_hdr *)&uip_buf[UIP_LLH_LEN]) + +#if UIP_STATISTICS == 1 +struct uip_stats uip_stat; +#define UIP_STAT(s) s +#else +#define UIP_STAT(s) +#endif /* UIP_STATISTICS == 1 */ + +#if UIP_LOGGING == 1 +#include +void uip_log(char *msg); +#define UIP_LOG(m) uip_log(m) +#else +#define UIP_LOG(m) +#endif /* UIP_LOGGING == 1 */ + +/*-----------------------------------------------------------------------------------*/ +void +uip_init(void) +{ + for(c = 0; c < UIP_LISTENPORTS; ++c) { + uip_listenports[c] = 0; + } + for(c = 0; c < UIP_CONNS; ++c) { + uip_conns[c].tcpstateflags = CLOSED; + } +#if UIP_ACTIVE_OPEN + lastport = 1024; +#endif /* UIP_ACTIVE_OPEN */ + +#if UIP_UDP + for(c = 0; c < UIP_UDP_CONNS; ++c) { + uip_udp_conns[c].lport = 0; + } +#endif /* UIP_UDP */ + + + /* IPv4 initialization. */ +#if UIP_FIXEDADDR == 0 + uip_hostaddr[0] = uip_hostaddr[1] = 0; +#endif /* UIP_FIXEDADDR */ + +} +/*-----------------------------------------------------------------------------------*/ +#if UIP_ACTIVE_OPEN +struct uip_conn * +uip_connect(u16_t *ripaddr, u16_t rport) +{ + register struct uip_conn *conn, *cconn; + + /* Find an unused local port. */ + again: + ++lastport; + + if(lastport >= 32000) { + lastport = 4096; + } + + /* Check if this port is already in use, and if so try to find + another one. */ + for(c = 0; c < UIP_CONNS; ++c) { + conn = &uip_conns[c]; + if(conn->tcpstateflags != CLOSED && + conn->lport == htons(lastport)) { + goto again; + } + } + + + conn = 0; + for(c = 0; c < UIP_CONNS; ++c) { + cconn = &uip_conns[c]; + if(cconn->tcpstateflags == CLOSED) { + conn = cconn; + break; + } + if(cconn->tcpstateflags == TIME_WAIT) { + if(conn == 0 || + cconn->timer > uip_conn->timer) { + conn = cconn; + } + } + } + + if(conn == 0) { + return 0; + } + + conn->tcpstateflags = SYN_SENT; + + conn->snd_nxt[0] = iss[0]; + conn->snd_nxt[1] = iss[1]; + conn->snd_nxt[2] = iss[2]; + conn->snd_nxt[3] = iss[3]; + + conn->initialmss = conn->mss = UIP_TCP_MSS; + + conn->len = 1; /* TCP length of the SYN is one. */ + conn->nrtx = 0; + conn->timer = 1; /* Send the SYN next time around. */ + conn->rto = UIP_RTO; + conn->sa = 0; + conn->sv = 16; + conn->lport = htons(lastport); + conn->rport = rport; + conn->ripaddr[0] = ripaddr[0]; + conn->ripaddr[1] = ripaddr[1]; + + return conn; +} +#endif /* UIP_ACTIVE_OPEN */ +/*-----------------------------------------------------------------------------------*/ +#if UIP_UDP +struct uip_udp_conn * +uip_udp_new(u16_t *ripaddr, u16_t rport) +{ + register struct uip_udp_conn *conn; + + /* Find an unused local port. */ + again: + ++lastport; + + if(lastport >= 32000) { + lastport = 4096; + } + + for(c = 0; c < UIP_UDP_CONNS; ++c) { + if(uip_udp_conns[c].lport == lastport) { + goto again; + } + } + + + conn = 0; + for(c = 0; c < UIP_UDP_CONNS; ++c) { + if(uip_udp_conns[c].lport == 0) { + conn = &uip_udp_conns[c]; + break; + } + } + + if(conn == 0) { + return 0; + } + + conn->lport = HTONS(lastport); + conn->rport = HTONS(rport); + conn->ripaddr[0] = ripaddr[0]; + conn->ripaddr[1] = ripaddr[1]; + + return conn; +} +#endif /* UIP_UDP */ +/*-----------------------------------------------------------------------------------*/ +void +uip_unlisten(u16_t port) +{ + for(c = 0; c < UIP_LISTENPORTS; ++c) { + if(uip_listenports[c] == port) { + uip_listenports[c] = 0; + return; + } + } +} +/*-----------------------------------------------------------------------------------*/ +void +uip_listen(u16_t port) +{ + for(c = 0; c < UIP_LISTENPORTS; ++c) { + if(uip_listenports[c] == 0) { + uip_listenports[c] = port; + return; + } + } +} +/*-----------------------------------------------------------------------------------*/ +/* XXX: IP fragment reassembly: not well-tested. */ + +#if UIP_REASSEMBLY +#define UIP_REASS_BUFSIZE (UIP_BUFSIZE - UIP_LLH_LEN) +static u8_t uip_reassbuf[UIP_REASS_BUFSIZE]; +static u8_t uip_reassbitmap[UIP_REASS_BUFSIZE / (8 * 8)]; +static const u8_t bitmap_bits[8] = {0xff, 0x7f, 0x3f, 0x1f, + 0x0f, 0x07, 0x03, 0x01}; +static u16_t uip_reasslen; +static u8_t uip_reassflags; +#define UIP_REASS_FLAG_LASTFRAG 0x01 +static u8_t uip_reasstmr; + +#define IP_HLEN 20 +#define IP_MF 0x20 + +static u8_t +uip_reass(void) +{ + u16_t offset, len; + u16_t i; + + /* If ip_reasstmr is zero, no packet is present in the buffer, so we + write the IP header of the fragment into the reassembly + buffer. The timer is updated with the maximum age. */ + if(uip_reasstmr == 0) { + memcpy(uip_reassbuf, &BUF->vhl, IP_HLEN); + uip_reasstmr = UIP_REASS_MAXAGE; + uip_reassflags = 0; + /* Clear the bitmap. */ + memset(uip_reassbitmap, sizeof(uip_reassbitmap), 0); + } + + /* Check if the incoming fragment matches the one currently present + in the reasembly buffer. If so, we proceed with copying the + fragment into the buffer. */ + if(BUF->srcipaddr[0] == FBUF->srcipaddr[0] && + BUF->srcipaddr[1] == FBUF->srcipaddr[1] && + BUF->destipaddr[0] == FBUF->destipaddr[0] && + BUF->destipaddr[1] == FBUF->destipaddr[1] && + BUF->ipid[0] == FBUF->ipid[0] && + BUF->ipid[1] == FBUF->ipid[1]) { + + len = (BUF->len[0] << 8) + BUF->len[1] - (BUF->vhl & 0x0f) * 4; + offset = (((BUF->ipoffset[0] & 0x3f) << 8) + BUF->ipoffset[1]) * 8; + + /* If the offset or the offset + fragment length overflows the + reassembly buffer, we discard the entire packet. */ + if(offset > UIP_REASS_BUFSIZE || + offset + len > UIP_REASS_BUFSIZE) { + uip_reasstmr = 0; + goto nullreturn; + } + + /* Copy the fragment into the reassembly buffer, at the right + offset. */ + memcpy(&uip_reassbuf[IP_HLEN + offset], + (char *)BUF + (int)((BUF->vhl & 0x0f) * 4), + len); + + /* Update the bitmap. */ + if(offset / (8 * 8) == (offset + len) / (8 * 8)) { + /* If the two endpoints are in the same byte, we only update + that byte. */ + + uip_reassbitmap[offset / (8 * 8)] |= + bitmap_bits[(offset / 8 ) & 7] & + ~bitmap_bits[((offset + len) / 8 ) & 7]; + } else { + /* If the two endpoints are in different bytes, we update the + bytes in the endpoints and fill the stuff inbetween with + 0xff. */ + uip_reassbitmap[offset / (8 * 8)] |= + bitmap_bits[(offset / 8 ) & 7]; + for(i = 1 + offset / (8 * 8); i < (offset + len) / (8 * 8); ++i) { + uip_reassbitmap[i] = 0xff; + } + uip_reassbitmap[(offset + len) / (8 * 8)] |= + ~bitmap_bits[((offset + len) / 8 ) & 7]; + } + + /* If this fragment has the More Fragments flag set to zero, we + know that this is the last fragment, so we can calculate the + size of the entire packet. We also set the + IP_REASS_FLAG_LASTFRAG flag to indicate that we have received + the final fragment. */ + + if((BUF->ipoffset[0] & IP_MF) == 0) { + uip_reassflags |= UIP_REASS_FLAG_LASTFRAG; + uip_reasslen = offset + len; + } + + /* Finally, we check if we have a full packet in the buffer. We do + this by checking if we have the last fragment and if all bits + in the bitmap are set. */ + if(uip_reassflags & UIP_REASS_FLAG_LASTFRAG) { + /* Check all bytes up to and including all but the last byte in + the bitmap. */ + for(i = 0; i < uip_reasslen / (8 * 8) - 1; ++i) { + if(uip_reassbitmap[i] != 0xff) { + goto nullreturn; + } + } + /* Check the last byte in the bitmap. It should contain just the + right amount of bits. */ + if(uip_reassbitmap[uip_reasslen / (8 * 8)] != + (u8_t)~bitmap_bits[uip_reasslen / 8 & 7]) { + goto nullreturn; + } + + /* If we have come this far, we have a full packet in the + buffer, so we allocate a pbuf and copy the packet into it. We + also reset the timer. */ + uip_reasstmr = 0; + memcpy(BUF, FBUF, uip_reasslen); + + /* Pretend to be a "normal" (i.e., not fragmented) IP packet + from now on. */ + BUF->ipoffset[0] = BUF->ipoffset[1] = 0; + BUF->len[0] = uip_reasslen >> 8; + BUF->len[1] = uip_reasslen & 0xff; + BUF->ipchksum = 0; + BUF->ipchksum = ~(uip_ipchksum()); + + return uip_reasslen; + } + } + + nullreturn: + return 0; +} +#endif /* UIP_REASSEMBL */ +/*-----------------------------------------------------------------------------------*/ +static void +uip_add_rcv_nxt(u16_t n) +{ + uip_add32(uip_conn->rcv_nxt, n); + uip_conn->rcv_nxt[0] = uip_acc32[0]; + uip_conn->rcv_nxt[1] = uip_acc32[1]; + uip_conn->rcv_nxt[2] = uip_acc32[2]; + uip_conn->rcv_nxt[3] = uip_acc32[3]; +} +/*-----------------------------------------------------------------------------------*/ +void +uip_process(u8_t flag) +{ + register struct uip_conn *uip_connr = uip_conn; + + uip_appdata = &uip_buf[40 + UIP_LLH_LEN]; + + + /* Check if we were invoked because of the perodic timer fireing. */ + if(flag == UIP_TIMER) { +#if UIP_REASSEMBLY + if(uip_reasstmr != 0) { + --uip_reasstmr; + } +#endif /* UIP_REASSEMBLY */ + /* Increase the initial sequence number. */ + if(++iss[3] == 0) { + if(++iss[2] == 0) { + if(++iss[1] == 0) { + ++iss[0]; + } + } + } + uip_len = 0; + if(uip_connr->tcpstateflags == TIME_WAIT || + uip_connr->tcpstateflags == FIN_WAIT_2) { + ++(uip_connr->timer); + if(uip_connr->timer == UIP_TIME_WAIT_TIMEOUT) { + uip_connr->tcpstateflags = CLOSED; + } + } else if(uip_connr->tcpstateflags != CLOSED) { + /* If the connection has outstanding data, we increase the + connection's timer and see if it has reached the RTO value + in which case we retransmit. */ + if(uip_outstanding(uip_connr)) { + if(uip_connr->timer-- == 0) { + if(uip_connr->nrtx == UIP_MAXRTX || + ((uip_connr->tcpstateflags == SYN_SENT || + uip_connr->tcpstateflags == SYN_RCVD) && + uip_connr->nrtx == UIP_MAXSYNRTX)) { + uip_connr->tcpstateflags = CLOSED; + + /* We call UIP_APPCALL() with uip_flags set to + UIP_TIMEDOUT to inform the application that the + connection has timed out. */ + uip_flags = UIP_TIMEDOUT; + UIP_APPCALL(); + + /* We also send a reset packet to the remote host. */ + BUF->flags = TCP_RST | TCP_ACK; + goto tcp_send_nodata; + } + + /* Exponential backoff. */ + uip_connr->timer = UIP_RTO << (uip_connr->nrtx > 4? + 4: + uip_connr->nrtx); + ++(uip_connr->nrtx); + + /* Ok, so we need to retransmit. We do this differently + depending on which state we are in. In ESTABLISHED, we + call upon the application so that it may prepare the + data for the retransmit. In SYN_RCVD, we resend the + SYNACK that we sent earlier and in LAST_ACK we have to + retransmit our FINACK. */ + UIP_STAT(++uip_stat.tcp.rexmit); + switch(uip_connr->tcpstateflags & TS_MASK) { + case SYN_RCVD: + /* In the SYN_RCVD state, we should retransmit our + SYNACK. */ + goto tcp_send_synack; + +#if UIP_ACTIVE_OPEN + case SYN_SENT: + /* In the SYN_SENT state, we retransmit out SYN. */ + BUF->flags = 0; + goto tcp_send_syn; +#endif /* UIP_ACTIVE_OPEN */ + + case ESTABLISHED: + /* In the ESTABLISHED state, we call upon the application + to do the actual retransmit after which we jump into + the code for sending out the packet (the apprexmit + label). */ + uip_len = 0; + uip_slen = 0; + uip_flags = UIP_REXMIT; + UIP_APPCALL(); + goto apprexmit; + + case FIN_WAIT_1: + case CLOSING: + case LAST_ACK: + /* In all these states we should retransmit a FINACK. */ + goto tcp_send_finack; + + } + } + } else if((uip_connr->tcpstateflags & TS_MASK) == ESTABLISHED) { + /* If there was no need for a retransmission, we poll the + application for new data. */ + uip_len = 0; + uip_slen = 0; + uip_flags = UIP_POLL; + UIP_APPCALL(); + goto appsend; + } + } + goto drop; + } +#if UIP_UDP + if(flag == UIP_UDP_TIMER) { + if(uip_udp_conn->lport != 0) { + uip_appdata = &uip_buf[UIP_LLH_LEN + 28]; + uip_len = uip_slen = 0; + uip_flags = UIP_POLL; + UIP_UDP_APPCALL(); + goto udp_send; + } else { + goto drop; + } + } +#endif + + /* This is where the input processing starts. */ + UIP_STAT(++uip_stat.ip.recv); + + + /* Start of IPv4 input header processing code. */ + + /* Check validity of the IP header. */ + if(BUF->vhl != 0x45) { /* IP version and header length. */ + UIP_STAT(++uip_stat.ip.drop); + UIP_STAT(++uip_stat.ip.vhlerr); + UIP_LOG("ip: invalid version or header length."); + goto drop; + } + + /* Check the size of the packet. If the size reported to us in + uip_len doesn't match the size reported in the IP header, there + has been a transmission error and we drop the packet. */ + + if(BUF->len[0] != (uip_len >> 8)) { /* IP length, high byte. */ + uip_len = (uip_len & 0xff) | (BUF->len[0] << 8); + } + if(BUF->len[1] != (uip_len & 0xff)) { /* IP length, low byte. */ + uip_len = (uip_len & 0xff00) | BUF->len[1]; + } + + /* Check the fragment flag. */ + if((BUF->ipoffset[0] & 0x3f) != 0 || + BUF->ipoffset[1] != 0) { +#if UIP_REASSEMBLY + uip_len = uip_reass(); + if(uip_len == 0) { + goto drop; + } +#else + UIP_STAT(++uip_stat.ip.drop); + UIP_STAT(++uip_stat.ip.fragerr); + UIP_LOG("ip: fragment dropped."); + goto drop; +#endif /* UIP_REASSEMBLY */ + } + + /* If we are configured to use ping IP address configuration and + hasn't been assigned an IP address yet, we accept all ICMP + packets. */ +#if UIP_PINGADDRCONF + if((uip_hostaddr[0] | uip_hostaddr[1]) == 0) { + if(BUF->proto == UIP_PROTO_ICMP) { + UIP_LOG("ip: possible ping config packet received."); + goto icmp_input; + } else { + UIP_LOG("ip: packet dropped since no address assigned."); + goto drop; + } + } +#endif /* UIP_PINGADDRCONF */ + + /* Check if the packet is destined for our IP address. */ + if(BUF->destipaddr[0] != uip_hostaddr[0]) { + UIP_STAT(++uip_stat.ip.drop); + UIP_LOG("ip: packet not for us."); + goto drop; + } + if(BUF->destipaddr[1] != uip_hostaddr[1]) { + UIP_STAT(++uip_stat.ip.drop); + UIP_LOG("ip: packet not for us."); + goto drop; + } + +#if 0 + // IP checksum is wrong through Netgear DSL router + if (uip_ipchksum() != 0xffff) { /* Compute and check the IP header + checksum. */ + UIP_STAT(++uip_stat.ip.drop); + UIP_STAT(++uip_stat.ip.chkerr); + UIP_LOG("ip: bad checksum."); + goto drop; + } +#endif + + if(BUF->proto == UIP_PROTO_TCP) /* Check for TCP packet. If so, jump + to the tcp_input label. */ + goto tcp_input; + +#if UIP_UDP + if(BUF->proto == UIP_PROTO_UDP) + goto udp_input; +#endif /* UIP_UDP */ + + if(BUF->proto != UIP_PROTO_ICMP) { /* We only allow ICMP packets from + here. */ + UIP_STAT(++uip_stat.ip.drop); + UIP_STAT(++uip_stat.ip.protoerr); + UIP_LOG("ip: neither tcp nor icmp."); + goto drop; + } + +#if UIP_PINGADDRCONF + icmp_input: +#endif + UIP_STAT(++uip_stat.icmp.recv); + + /* ICMP echo (i.e., ping) processing. This is simple, we only change + the ICMP type from ECHO to ECHO_REPLY and adjust the ICMP + checksum before we return the packet. */ + if(ICMPBUF->type != ICMP_ECHO) { + UIP_STAT(++uip_stat.icmp.drop); + UIP_STAT(++uip_stat.icmp.typeerr); + UIP_LOG("icmp: not icmp echo."); + goto drop; + } + + /* If we are configured to use ping IP address assignment, we use + the destination IP address of this ping packet and assign it to + ourself. */ +#if UIP_PINGADDRCONF + if((uip_hostaddr[0] | uip_hostaddr[1]) == 0) { + uip_hostaddr[0] = BUF->destipaddr[0]; + uip_hostaddr[1] = BUF->destipaddr[1]; + } +#endif /* UIP_PINGADDRCONF */ + + ICMPBUF->type = ICMP_ECHO_REPLY; + + if(ICMPBUF->icmpchksum >= HTONS(0xffff - (ICMP_ECHO << 8))) { + ICMPBUF->icmpchksum += HTONS(ICMP_ECHO << 8) + 1; + } else { + ICMPBUF->icmpchksum += HTONS(ICMP_ECHO << 8); + } + + /* Swap IP addresses. */ + tmp16 = BUF->destipaddr[0]; + BUF->destipaddr[0] = BUF->srcipaddr[0]; + BUF->srcipaddr[0] = tmp16; + tmp16 = BUF->destipaddr[1]; + BUF->destipaddr[1] = BUF->srcipaddr[1]; + BUF->srcipaddr[1] = tmp16; + + UIP_STAT(++uip_stat.icmp.sent); + goto send; + + /* End of IPv4 input header processing code. */ + + +#if UIP_UDP + /* UDP input processing. */ + udp_input: + /* UDP processing is really just a hack. We don't do anything to the + UDP/IP headers, but let the UDP application do all the hard + work. If the application sets uip_slen, it has a packet to + send. */ +#if UIP_UDP_CHECKSUMS + if(uip_udpchksum() != 0xffff) { + UIP_STAT(++uip_stat.udp.drop); + UIP_STAT(++uip_stat.udp.chkerr); + UIP_LOG("udp: bad checksum."); + goto drop; + } +#endif /* UIP_UDP_CHECKSUMS */ + + /* Demultiplex this UDP packet between the UDP "connections". */ + for(uip_udp_conn = &uip_udp_conns[0]; + uip_udp_conn < &uip_udp_conns[UIP_UDP_CONNS]; + ++uip_udp_conn) { + if(uip_udp_conn->lport != 0 && + UDPBUF->destport == uip_udp_conn->lport && + (uip_udp_conn->rport == 0 || + UDPBUF->srcport == uip_udp_conn->rport) && + BUF->srcipaddr[0] == uip_udp_conn->ripaddr[0] && + BUF->srcipaddr[1] == uip_udp_conn->ripaddr[1]) { + goto udp_found; + } + } + goto drop; + + udp_found: + uip_len = uip_len - 28; + uip_appdata = &uip_buf[UIP_LLH_LEN + 28]; + uip_flags = UIP_NEWDATA; + uip_slen = 0; + UIP_UDP_APPCALL(); + udp_send: + if(uip_slen == 0) { + goto drop; + } + uip_len = uip_slen + 28; + + BUF->len[0] = (uip_len >> 8); + BUF->len[1] = (uip_len & 0xff); + + BUF->proto = UIP_PROTO_UDP; + + UDPBUF->udplen = HTONS(uip_slen + 8); + UDPBUF->udpchksum = 0; +#if UIP_UDP_CHECKSUMS + /* Calculate UDP checksum. */ + UDPBUF->udpchksum = ~(uip_udpchksum()); + if(UDPBUF->udpchksum == 0) { + UDPBUF->udpchksum = 0xffff; + } +#endif /* UIP_UDP_CHECKSUMS */ + + BUF->srcport = uip_udp_conn->lport; + BUF->destport = uip_udp_conn->rport; + + BUF->srcipaddr[0] = uip_hostaddr[0]; + BUF->srcipaddr[1] = uip_hostaddr[1]; + BUF->destipaddr[0] = uip_udp_conn->ripaddr[0]; + BUF->destipaddr[1] = uip_udp_conn->ripaddr[1]; + + uip_appdata = &uip_buf[UIP_LLH_LEN + 40]; + goto ip_send_nolen; +#endif /* UIP_UDP */ + + /* TCP input processing. */ + tcp_input: + UIP_STAT(++uip_stat.tcp.recv); + + /* Start of TCP input header processing code. */ + +#if 1 // FIXME + if(uip_tcpchksum() != 0xffff) { /* Compute and check the TCP + checksum. */ + UIP_STAT(++uip_stat.tcp.drop); + UIP_STAT(++uip_stat.tcp.chkerr); + UIP_LOG("tcp: bad checksum."); + goto drop; + } +#endif + + /* Demultiplex this segment. */ + /* First check any active connections. */ + for(uip_connr = &uip_conns[0]; uip_connr < &uip_conns[UIP_CONNS]; ++uip_connr) { + if(uip_connr->tcpstateflags != CLOSED && + BUF->destport == uip_connr->lport && + BUF->srcport == uip_connr->rport && + BUF->srcipaddr[0] == uip_connr->ripaddr[0] && + BUF->srcipaddr[1] == uip_connr->ripaddr[1]) { + goto found; + } + } + + /* If we didn't find and active connection that expected the packet, + either this packet is an old duplicate, or this is a SYN packet + destined for a connection in LISTEN. If the SYN flag isn't set, + it is an old packet and we send a RST. */ + if((BUF->flags & TCP_CTL) != TCP_SYN) + goto reset; + + tmp16 = BUF->destport; + /* Next, check listening connections. */ + for(c = 0; c < UIP_LISTENPORTS; ++c) { + if(tmp16 == uip_listenports[c]) + goto found_listen; + } + + /* No matching connection found, so we send a RST packet. */ + UIP_STAT(++uip_stat.tcp.synrst); + reset: + + /* We do not send resets in response to resets. */ + if(BUF->flags & TCP_RST) + goto drop; + + UIP_STAT(++uip_stat.tcp.rst); + + BUF->flags = TCP_RST | TCP_ACK; + uip_len = 40; + BUF->tcpoffset = 5 << 4; + + /* Flip the seqno and ackno fields in the TCP header. */ + c = BUF->seqno[3]; + BUF->seqno[3] = BUF->ackno[3]; + BUF->ackno[3] = c; + + c = BUF->seqno[2]; + BUF->seqno[2] = BUF->ackno[2]; + BUF->ackno[2] = c; + + c = BUF->seqno[1]; + BUF->seqno[1] = BUF->ackno[1]; + BUF->ackno[1] = c; + + c = BUF->seqno[0]; + BUF->seqno[0] = BUF->ackno[0]; + BUF->ackno[0] = c; + + /* We also have to increase the sequence number we are + acknowledging. If the least significant byte overflowed, we need + to propagate the carry to the other bytes as well. */ + if(++BUF->ackno[3] == 0) { + if(++BUF->ackno[2] == 0) { + if(++BUF->ackno[1] == 0) { + ++BUF->ackno[0]; + } + } + } + + /* Swap port numbers. */ + tmp16 = BUF->srcport; + BUF->srcport = BUF->destport; + BUF->destport = tmp16; + + /* Swap IP addresses. */ + tmp16 = BUF->destipaddr[0]; + BUF->destipaddr[0] = BUF->srcipaddr[0]; + BUF->srcipaddr[0] = tmp16; + tmp16 = BUF->destipaddr[1]; + BUF->destipaddr[1] = BUF->srcipaddr[1]; + BUF->srcipaddr[1] = tmp16; + + + /* And send out the RST packet! */ + goto tcp_send_noconn; + + /* This label will be jumped to if we matched the incoming packet + with a connection in LISTEN. In that case, we should create a new + connection and send a SYNACK in return. */ + found_listen: + /* First we check if there are any connections avaliable. Unused + connections are kept in the same table as used connections, but + unused ones have the tcpstate set to CLOSED. Also, connections in + TIME_WAIT are kept track of and we'll use the oldest one if no + CLOSED connections are found. Thanks to Eddie C. Dost for a very + nice algorithm for the TIME_WAIT search. */ + uip_connr = 0; + for(c = 0; c < UIP_CONNS; ++c) { + if(uip_conns[c].tcpstateflags == CLOSED) { + uip_connr = &uip_conns[c]; + break; + } + if(uip_conns[c].tcpstateflags == TIME_WAIT) { + if(uip_connr == 0 || + uip_conns[c].timer > uip_connr->timer) { + uip_connr = &uip_conns[c]; + } + } + } + + if(uip_connr == 0) { + /* All connections are used already, we drop packet and hope that + the remote end will retransmit the packet at a time when we + have more spare connections. */ + UIP_STAT(++uip_stat.tcp.syndrop); + UIP_LOG("tcp: found no unused connections."); + goto drop; + } + uip_conn = uip_connr; + + /* Fill in the necessary fields for the new connection. */ + uip_connr->rto = uip_connr->timer = UIP_RTO; + uip_connr->sa = 0; + uip_connr->sv = 4; + uip_connr->nrtx = 0; + uip_connr->lport = BUF->destport; + uip_connr->rport = BUF->srcport; + uip_connr->ripaddr[0] = BUF->srcipaddr[0]; + uip_connr->ripaddr[1] = BUF->srcipaddr[1]; + uip_connr->tcpstateflags = SYN_RCVD; + + uip_connr->snd_nxt[0] = iss[0]; + uip_connr->snd_nxt[1] = iss[1]; + uip_connr->snd_nxt[2] = iss[2]; + uip_connr->snd_nxt[3] = iss[3]; + uip_connr->len = 1; + + /* rcv_nxt should be the seqno from the incoming packet + 1. */ + uip_connr->rcv_nxt[3] = BUF->seqno[3]; + uip_connr->rcv_nxt[2] = BUF->seqno[2]; + uip_connr->rcv_nxt[1] = BUF->seqno[1]; + uip_connr->rcv_nxt[0] = BUF->seqno[0]; + uip_add_rcv_nxt(1); + + /* Parse the TCP MSS option, if present. */ + if((BUF->tcpoffset & 0xf0) > 0x50) { + for(c = 0; c < ((BUF->tcpoffset >> 4) - 5) << 2 ;) { + opt = uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + c]; + if(opt == 0x00) { + /* End of options. */ + break; + } else if(opt == 0x01) { + ++c; + /* NOP option. */ + } else if(opt == 0x02 && + uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0x04) { + /* An MSS option with the right option length. */ + tmp16 = ((u16_t)uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 2 + c] << 8) | + (u16_t)uip_buf[40 + UIP_LLH_LEN + 3 + c]; + uip_connr->initialmss = uip_connr->mss = + tmp16 > UIP_TCP_MSS? UIP_TCP_MSS: tmp16; + + /* And we are done processing options. */ + break; + } else { + /* All other options have a length field, so that we easily + can skip past them. */ + if(uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0) { + /* If the length field is zero, the options are malformed + and we don't process them further. */ + break; + } + c += uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c]; + } + } + } + + /* Our response will be a SYNACK. */ +#if UIP_ACTIVE_OPEN + tcp_send_synack: + BUF->flags = TCP_ACK; + + tcp_send_syn: + BUF->flags |= TCP_SYN; +#else /* UIP_ACTIVE_OPEN */ + tcp_send_synack: + BUF->flags = TCP_SYN | TCP_ACK; +#endif /* UIP_ACTIVE_OPEN */ + + /* We send out the TCP Maximum Segment Size option with our + SYNACK. */ + BUF->optdata[0] = 2; + BUF->optdata[1] = 4; + BUF->optdata[2] = (UIP_TCP_MSS) / 256; + BUF->optdata[3] = (UIP_TCP_MSS) & 255; + uip_len = 44; + BUF->tcpoffset = 6 << 4; + goto tcp_send; + + /* This label will be jumped to if we found an active connection. */ + found: + uip_conn = uip_connr; + uip_flags = 0; + + /* We do a very naive form of TCP reset processing; we just accept + any RST and kill our connection. We should in fact check if the + sequence number of this reset is wihtin our advertised window + before we accept the reset. */ + if(BUF->flags & TCP_RST) { + uip_connr->tcpstateflags = CLOSED; + UIP_LOG("tcp: got reset, aborting connection."); + uip_flags = UIP_ABORT; + UIP_APPCALL(); + goto drop; + } + /* Calculated the length of the data, if the application has sent + any data to us. */ + c = (BUF->tcpoffset >> 4) << 2; + /* uip_len will contain the length of the actual TCP data. This is + calculated by subtracing the length of the TCP header (in + c) and the length of the IP header (20 bytes). */ + uip_len = uip_len - c - 20; + + /* First, check if the sequence number of the incoming packet is + what we're expecting next. If not, we send out an ACK with the + correct numbers in. */ + if(uip_len > 0 && + (BUF->seqno[0] != uip_connr->rcv_nxt[0] || + BUF->seqno[1] != uip_connr->rcv_nxt[1] || + BUF->seqno[2] != uip_connr->rcv_nxt[2] || + BUF->seqno[3] != uip_connr->rcv_nxt[3])) { + goto tcp_send_ack; + } + + /* Next, check if the incoming segment acknowledges any outstanding + data. If so, we update the sequence number, reset the length of + the outstanding data, calculate RTT estimations, and reset the + retransmission timer. */ + if((BUF->flags & TCP_ACK) && uip_outstanding(uip_connr)) { + uip_add32(uip_connr->snd_nxt, uip_connr->len); + if(BUF->ackno[0] == uip_acc32[0] && + BUF->ackno[1] == uip_acc32[1] && + BUF->ackno[2] == uip_acc32[2] && + BUF->ackno[3] == uip_acc32[3]) { + /* Update sequence number. */ + uip_connr->snd_nxt[0] = uip_acc32[0]; + uip_connr->snd_nxt[1] = uip_acc32[1]; + uip_connr->snd_nxt[2] = uip_acc32[2]; + uip_connr->snd_nxt[3] = uip_acc32[3]; + + + /* Do RTT estimation, unless we have done retransmissions. */ + if(uip_connr->nrtx == 0) { + signed char m; + m = uip_connr->rto - uip_connr->timer; + /* This is taken directly from VJs original code in his paper */ + m = m - (uip_connr->sa >> 3); + uip_connr->sa += m; + if(m < 0) { + m = -m; + } + m = m - (uip_connr->sv >> 2); + uip_connr->sv += m; + uip_connr->rto = (uip_connr->sa >> 3) + uip_connr->sv; + + } + /* Set the acknowledged flag. */ + uip_flags = UIP_ACKDATA; + /* Reset the retransmission timer. */ + uip_connr->timer = uip_connr->rto; + } + + } + + /* Do different things depending on in what state the connection is. */ + switch(uip_connr->tcpstateflags & TS_MASK) { + /* CLOSED and LISTEN are not handled here. CLOSE_WAIT is not + implemented, since we force the application to close when the + peer sends a FIN (hence the application goes directly from + ESTABLISHED to LAST_ACK). */ + case SYN_RCVD: + /* In SYN_RCVD we have sent out a SYNACK in response to a SYN, and + we are waiting for an ACK that acknowledges the data we sent + out the last time. Therefore, we want to have the UIP_ACKDATA + flag set. If so, we enter the ESTABLISHED state. */ + if(uip_flags & UIP_ACKDATA) { + uip_connr->tcpstateflags = ESTABLISHED; + uip_flags = UIP_CONNECTED; + uip_connr->len = 0; + if(uip_len > 0) { + uip_flags |= UIP_NEWDATA; + uip_add_rcv_nxt(uip_len); + } + uip_slen = 0; + UIP_APPCALL(); + goto appsend; + } + goto drop; +#if UIP_ACTIVE_OPEN + case SYN_SENT: + /* In SYN_SENT, we wait for a SYNACK that is sent in response to + our SYN. The rcv_nxt is set to sequence number in the SYNACK + plus one, and we send an ACK. We move into the ESTABLISHED + state. */ + if((uip_flags & UIP_ACKDATA) && + BUF->flags == (TCP_SYN | TCP_ACK)) { + + /* Parse the TCP MSS option, if present. */ + if((BUF->tcpoffset & 0xf0) > 0x50) { + for(c = 0; c < ((BUF->tcpoffset >> 4) - 5) << 2 ;) { + opt = uip_buf[40 + UIP_LLH_LEN + c]; + if(opt == 0x00) { + /* End of options. */ + break; + } else if(opt == 0x01) { + ++c; + /* NOP option. */ + } else if(opt == 0x02 && + uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0x04) { + /* An MSS option with the right option length. */ + tmp16 = (uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 2 + c] << 8) | + uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 3 + c]; + uip_connr->initialmss = + uip_connr->mss = tmp16 > UIP_TCP_MSS? UIP_TCP_MSS: tmp16; + + /* And we are done processing options. */ + break; + } else { + /* All other options have a length field, so that we easily + can skip past them. */ + if(uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0) { + /* If the length field is zero, the options are malformed + and we don't process them further. */ + break; + } + c += uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c]; + } + } + } + uip_connr->tcpstateflags = ESTABLISHED; + uip_connr->rcv_nxt[0] = BUF->seqno[0]; + uip_connr->rcv_nxt[1] = BUF->seqno[1]; + uip_connr->rcv_nxt[2] = BUF->seqno[2]; + uip_connr->rcv_nxt[3] = BUF->seqno[3]; + uip_add_rcv_nxt(1); + uip_flags = UIP_CONNECTED | UIP_NEWDATA; + uip_connr->len = 0; + uip_len = 0; + uip_slen = 0; + UIP_APPCALL(); + goto appsend; + } + goto reset; +#endif /* UIP_ACTIVE_OPEN */ + + case ESTABLISHED: + /* In the ESTABLISHED state, we call upon the application to feed + data into the uip_buf. If the UIP_ACKDATA flag is set, the + application should put new data into the buffer, otherwise we are + retransmitting an old segment, and the application should put that + data into the buffer. + + If the incoming packet is a FIN, we should close the connection on + this side as well, and we send out a FIN and enter the LAST_ACK + state. We require that there is no outstanding data; otherwise the + sequence numbers will be screwed up. */ + + if(BUF->flags & TCP_FIN) { + if(uip_outstanding(uip_connr)) { + goto drop; + } + uip_add_rcv_nxt(1 + uip_len); + uip_flags = UIP_CLOSE; + if(uip_len > 0) { + uip_flags |= UIP_NEWDATA; + } + UIP_APPCALL(); + uip_connr->len = 1; + uip_connr->tcpstateflags = LAST_ACK; + uip_connr->nrtx = 0; + tcp_send_finack: + BUF->flags = TCP_FIN | TCP_ACK; + goto tcp_send_nodata; + } + + /* Check the URG flag. If this is set, the segment carries urgent + data that we must pass to the application. */ + if(BUF->flags & TCP_URG) { +#if UIP_URGDATA > 0 + uip_urglen = (BUF->urgp[0] << 8) | BUF->urgp[1]; + if(uip_urglen > uip_len) { + /* There is more urgent data in the next segment to come. */ + uip_urglen = uip_len; + } + uip_add_rcv_nxt(uip_urglen); + uip_len -= uip_urglen; + uip_urgdata = uip_appdata; + uip_appdata += uip_urglen; + } else { + uip_urglen = 0; +#endif /* UIP_URGDATA > 0 */ + uip_appdata += (BUF->urgp[0] << 8) | BUF->urgp[1]; + uip_len -= (BUF->urgp[0] << 8) | BUF->urgp[1]; + } + + + /* If uip_len > 0 we have TCP data in the packet, and we flag this + by setting the UIP_NEWDATA flag and update the sequence number + we acknowledge. If the application has stopped the dataflow + using uip_stop(), we must not accept any data packets from the + remote host. */ + if(uip_len > 0 && !(uip_connr->tcpstateflags & UIP_STOPPED)) { + uip_flags |= UIP_NEWDATA; + uip_add_rcv_nxt(uip_len); + } + + /* Check if the available buffer space advertised by the other end + is smaller than the initial MSS for this connection. If so, we + set the current MSS to the window size to ensure that the + application does not send more data than the other end can + handle. + + If the remote host advertises a zero window, we set the MSS to + the initial MSS so that the application will send an entire MSS + of data. This data will not be acknowledged by the receiver, + and the application will retransmit it. This is called the + "persistent timer" and uses the retransmission mechanim. + */ + tmp16 = ((u16_t)BUF->wnd[0] << 8) + (u16_t)BUF->wnd[1]; + if(tmp16 > uip_connr->initialmss || + tmp16 == 0) { + tmp16 = uip_connr->initialmss; + } + uip_connr->mss = tmp16; + + /* If this packet constitutes an ACK for outstanding data (flagged + by the UIP_ACKDATA flag, we should call the application since it + might want to send more data. If the incoming packet had data + from the peer (as flagged by the UIP_NEWDATA flag), the + application must also be notified. + + When the application is called, the global variable uip_len + contains the length of the incoming data. The application can + access the incoming data through the global pointer + uip_appdata, which usually points 40 bytes into the uip_buf + array. + + If the application wishes to send any data, this data should be + put into the uip_appdata and the length of the data should be + put into uip_len. If the application don't have any data to + send, uip_len must be set to 0. */ + if(uip_flags & (UIP_NEWDATA | UIP_ACKDATA)) { + uip_slen = 0; + UIP_APPCALL(); + + appsend: + + if(uip_flags & UIP_ABORT) { + uip_slen = 0; + uip_connr->tcpstateflags = CLOSED; + BUF->flags = TCP_RST | TCP_ACK; + goto tcp_send_nodata; + } + + if(uip_flags & UIP_CLOSE) { + uip_slen = 0; + uip_connr->len = 1; + uip_connr->tcpstateflags = FIN_WAIT_1; + uip_connr->nrtx = 0; + BUF->flags = TCP_FIN | TCP_ACK; + goto tcp_send_nodata; + } + + /* If uip_slen > 0, the application has data to be sent. */ + if(uip_slen > 0) { + + /* If the connection has acknowledged data, the contents of + the ->len variable should be discarded. */ + if((uip_flags & UIP_ACKDATA) != 0) { + uip_connr->len = 0; + } + + /* If the ->len variable is non-zero the connection has + already data in transit and cannot send anymore right + now. */ + if(uip_connr->len == 0) { + + /* The application cannot send more than what is allowed by + the mss (the minumum of the MSS and the available + window). */ + if(uip_slen > uip_connr->mss) { + uip_slen = uip_connr->mss; + } + + /* Remember how much data we send out now so that we know + when everything has been acknowledged. */ + uip_connr->len = uip_slen; + } else { + + /* If the application already had unacknowledged data, we + make sure that the application does not send (i.e., + retransmit) out more than it previously sent out. */ + uip_slen = uip_connr->len; + } + } else { + uip_connr->len = 0; + } + uip_connr->nrtx = 0; + apprexmit: + uip_appdata = uip_sappdata; + + /* If the application has data to be sent, or if the incoming + packet had new data in it, we must send out a packet. */ + if(uip_slen > 0 && uip_connr->len > 0) { + /* Add the length of the IP and TCP headers. */ + uip_len = uip_connr->len + UIP_TCPIP_HLEN; + /* We always set the ACK flag in response packets. */ + BUF->flags = TCP_ACK | TCP_PSH; + /* Send the packet. */ + goto tcp_send_noopts; + } + /* If there is no data to send, just send out a pure ACK if + there is newdata. */ + if(uip_flags & UIP_NEWDATA) { + uip_len = UIP_TCPIP_HLEN; + BUF->flags = TCP_ACK; + goto tcp_send_noopts; + } + } + goto drop; + case LAST_ACK: + /* We can close this connection if the peer has acknowledged our + FIN. This is indicated by the UIP_ACKDATA flag. */ + if(uip_flags & UIP_ACKDATA) { + uip_connr->tcpstateflags = CLOSED; + uip_flags = UIP_CLOSE; + UIP_APPCALL(); + } + break; + + case FIN_WAIT_1: + /* The application has closed the connection, but the remote host + hasn't closed its end yet. Thus we do nothing but wait for a + FIN from the other side. */ + if(uip_len > 0) { + uip_add_rcv_nxt(uip_len); + } + if(BUF->flags & TCP_FIN) { + if(uip_flags & UIP_ACKDATA) { + uip_connr->tcpstateflags = TIME_WAIT; + uip_connr->timer = 0; + uip_connr->len = 0; + } else { + uip_connr->tcpstateflags = CLOSING; + } + uip_add_rcv_nxt(1); + uip_flags = UIP_CLOSE; + UIP_APPCALL(); + goto tcp_send_ack; + } else if(uip_flags & UIP_ACKDATA) { + uip_connr->tcpstateflags = FIN_WAIT_2; + uip_connr->len = 0; + goto drop; + } + if(uip_len > 0) { + goto tcp_send_ack; + } + goto drop; + + case FIN_WAIT_2: + if(uip_len > 0) { + uip_add_rcv_nxt(uip_len); + } + if(BUF->flags & TCP_FIN) { + uip_connr->tcpstateflags = TIME_WAIT; + uip_connr->timer = 0; + uip_add_rcv_nxt(1); + uip_flags = UIP_CLOSE; + UIP_APPCALL(); + goto tcp_send_ack; + } + if(uip_len > 0) { + goto tcp_send_ack; + } + goto drop; + + case TIME_WAIT: + goto tcp_send_ack; + + case CLOSING: + if(uip_flags & UIP_ACKDATA) { + uip_connr->tcpstateflags = TIME_WAIT; + uip_connr->timer = 0; + } + } + goto drop; + + + /* We jump here when we are ready to send the packet, and just want + to set the appropriate TCP sequence numbers in the TCP header. */ + tcp_send_ack: + BUF->flags = TCP_ACK; + tcp_send_nodata: + uip_len = 40; + tcp_send_noopts: + BUF->tcpoffset = 5 << 4; + tcp_send: + /* We're done with the input processing. We are now ready to send a + reply. Our job is to fill in all the fields of the TCP and IP + headers before calculating the checksum and finally send the + packet. */ + BUF->ackno[0] = uip_connr->rcv_nxt[0]; + BUF->ackno[1] = uip_connr->rcv_nxt[1]; + BUF->ackno[2] = uip_connr->rcv_nxt[2]; + BUF->ackno[3] = uip_connr->rcv_nxt[3]; + + BUF->seqno[0] = uip_connr->snd_nxt[0]; + BUF->seqno[1] = uip_connr->snd_nxt[1]; + BUF->seqno[2] = uip_connr->snd_nxt[2]; + BUF->seqno[3] = uip_connr->snd_nxt[3]; + + BUF->proto = UIP_PROTO_TCP; + + BUF->srcport = uip_connr->lport; + BUF->destport = uip_connr->rport; + + BUF->srcipaddr[0] = uip_hostaddr[0]; + BUF->srcipaddr[1] = uip_hostaddr[1]; + BUF->destipaddr[0] = uip_connr->ripaddr[0]; + BUF->destipaddr[1] = uip_connr->ripaddr[1]; + + + if(uip_connr->tcpstateflags & UIP_STOPPED) { + /* If the connection has issued uip_stop(), we advertise a zero + window so that the remote host will stop sending data. */ + BUF->wnd[0] = BUF->wnd[1] = 0; + } else { + BUF->wnd[0] = ((UIP_RECEIVE_WINDOW) >> 8); + BUF->wnd[1] = ((UIP_RECEIVE_WINDOW) & 0xff); + } + + tcp_send_noconn: + + BUF->len[0] = (uip_len >> 8); + BUF->len[1] = (uip_len & 0xff); + + /* Calculate TCP checksum. */ + BUF->tcpchksum = 0; + BUF->tcpchksum = ~(uip_tcpchksum()); + + +#if UIP_UDP + ip_send_nolen: +#endif + + BUF->vhl = 0x45; + BUF->tos = 0; + BUF->ipoffset[0] = BUF->ipoffset[1] = 0; + BUF->ttl = UIP_TTL; + ++ipid; + BUF->ipid[0] = ipid >> 8; + BUF->ipid[1] = ipid & 0xff; + + /* Calculate IP checksum. */ + BUF->ipchksum = 0; + BUF->ipchksum = ~(uip_ipchksum()); + + UIP_STAT(++uip_stat.tcp.sent); + send: + UIP_STAT(++uip_stat.ip.sent); + /* Return and let the caller do the actual transmission. */ + return; + drop: + uip_len = 0; + return; +} +/*-----------------------------------------------------------------------------------*/ +u16_t +htons(u16_t val) +{ + return HTONS(val); +} +/*-----------------------------------------------------------------------------------*/ +/** @} */ diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/uip/uip.h b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/uip.h new file mode 100644 index 000000000..0ff1b2a79 --- /dev/null +++ b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/uip.h @@ -0,0 +1,1060 @@ +/** + * \addtogroup uip + * @{ + */ + +/** + * \file + * Header file for the uIP TCP/IP stack. + * \author Adam Dunkels + * + * The uIP TCP/IP stack header file contains definitions for a number + * of C macros that are used by uIP programs as well as internal uIP + * structures, TCP/IP header structures and function declarations. + * + */ + + +/* + * Copyright (c) 2001-2003, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: uip.h,v 1.36.2.7 2003/10/07 13:47:51 adam Exp $ + * + */ + +#ifndef __UIP_H__ +#define __UIP_H__ + +#include "uipopt.h" + +/*-----------------------------------------------------------------------------------*/ +/* First, the functions that should be called from the + * system. Initialization, the periodic timer and incoming packets are + * handled by the following three functions. + */ + +/** + * \defgroup uipconffunc uIP configuration functions + * @{ + * + * The uIP configuration functions are used for setting run-time + * parameters in uIP such as IP addresses. + */ + +/** + * Set the IP address of this host. + * + * The IP address is represented as a 4-byte array where the first + * octet of the IP address is put in the first member of the 4-byte + * array. + * + * \param addr A pointer to a 4-byte representation of the IP address. + * + * \hideinitializer + */ +#define uip_sethostaddr(addr) do { uip_hostaddr[0] = addr[0]; \ + uip_hostaddr[1] = addr[1]; } while(0) + +/** + * Get the IP address of this host. + * + * The IP address is represented as a 4-byte array where the first + * octet of the IP address is put in the first member of the 4-byte + * array. + * + * \param addr A pointer to a 4-byte array that will be filled in with + * the currently configured IP address. + * + * \hideinitializer + */ +#define uip_gethostaddr(addr) do { addr[0] = uip_hostaddr[0]; \ + addr[1] = uip_hostaddr[1]; } while(0) + +/** @} */ + +/** + * \defgroup uipinit uIP initialization functions + * @{ + * + * The uIP initialization functions are used for booting uIP. + */ + +/** + * uIP initialization function. + * + * This function should be called at boot up to initilize the uIP + * TCP/IP stack. + */ +void uip_init(void); + +/** @} */ + +/** + * \defgroup uipdevfunc uIP device driver functions + * @{ + * + * These functions are used by a network device driver for interacting + * with uIP. + */ + +/** + * Process an incoming packet. + * + * This function should be called when the device driver has received + * a packet from the network. The packet from the device driver must + * be present in the uip_buf buffer, and the length of the packet + * should be placed in the uip_len variable. + * + * When the function returns, there may be an outbound packet placed + * in the uip_buf packet buffer. If so, the uip_len variable is set to + * the length of the packet. If no packet is to be sent out, the + * uip_len variable is set to 0. + * + * The usual way of calling the function is presented by the source + * code below. + \code + uip_len = devicedriver_poll(); + if(uip_len > 0) { + uip_input(); + if(uip_len > 0) { + devicedriver_send(); + } + } + \endcode + * + * \note If you are writing a uIP device driver that needs ARP + * (Address Resolution Protocol), e.g., when running uIP over + * Ethernet, you will need to call the uIP ARP code before calling + * this function: + \code + #define BUF ((struct uip_eth_hdr *)&uip_buf[0]) + uip_len = ethernet_devicedrver_poll(); + if(uip_len > 0) { + if(BUF->type == HTONS(UIP_ETHTYPE_IP)) { + uip_arp_ipin(); + uip_input(); + if(uip_len > 0) { + uip_arp_out(); + ethernet_devicedriver_send(); + } + } else if(BUF->type == HTONS(UIP_ETHTYPE_ARP)) { + uip_arp_arpin(); + if(uip_len > 0) { + ethernet_devicedriver_send(); + } + } + \endcode + * + * \hideinitializer + */ +#define uip_input() uip_process(UIP_DATA) + +/** + * Periodic processing for a connection identified by its number. + * + * This function does the necessary periodic processing (timers, + * polling) for a uIP TCP conneciton, and should be called when the + * periodic uIP timer goes off. It should be called for every + * connection, regardless of whether they are open of closed. + * + * When the function returns, it may have an outbound packet waiting + * for service in the uIP packet buffer, and if so the uip_len + * variable is set to a value larger than zero. The device driver + * should be called to send out the packet. + * + * The ususal way of calling the function is through a for() loop like + * this: + \code + for(i = 0; i < UIP_CONNS; ++i) { + uip_periodic(i); + if(uip_len > 0) { + devicedriver_send(); + } + } + \endcode + * + * \note If you are writing a uIP device driver that needs ARP + * (Address Resolution Protocol), e.g., when running uIP over + * Ethernet, you will need to call the uip_arp_out() function before + * calling the device driver: + \code + for(i = 0; i < UIP_CONNS; ++i) { + uip_periodic(i); + if(uip_len > 0) { + uip_arp_out(); + ethernet_devicedriver_send(); + } + } + \endcode + * + * \param conn The number of the connection which is to be periodically polled. + * + * \hideinitializer + */ +#define uip_periodic(conn) do { uip_conn = &uip_conns[conn]; \ + uip_process(UIP_TIMER); } while (0) + +/** + * Periodic processing for a connection identified by a pointer to its structure. + * + * Same as uip_periodic() but takes a pointer to the actual uip_conn + * struct instead of an integer as its argument. This function can be + * used to force periodic processing of a specific connection. + * + * \param conn A pointer to the uip_conn struct for the connection to + * be processed. + * + * \hideinitializer + */ +#define uip_periodic_conn(conn) do { uip_conn = conn; \ + uip_process(UIP_TIMER); } while (0) + +#if UIP_UDP +/** + * Periodic processing for a UDP connection identified by its number. + * + * This function is essentially the same as uip_prerioic(), but for + * UDP connections. It is called in a similar fashion as the + * uip_periodic() function: + \code + for(i = 0; i < UIP_UDP_CONNS; i++) { + uip_udp_periodic(i); + if(uip_len > 0) { + devicedriver_send(); + } + } + \endcode + * + * \note As for the uip_periodic() function, special care has to be + * taken when using uIP together with ARP and Ethernet: + \code + for(i = 0; i < UIP_UDP_CONNS; i++) { + uip_udp_periodic(i); + if(uip_len > 0) { + uip_arp_out(); + ethernet_devicedriver_send(); + } + } + \endcode + * + * \param conn The number of the UDP connection to be processed. + * + * \hideinitializer + */ +#define uip_udp_periodic(conn) do { uip_udp_conn = &uip_udp_conns[conn]; \ + uip_process(UIP_UDP_TIMER); } while (0) + +/** + * Periodic processing for a UDP connection identified by a pointer to + * its structure. + * + * Same as uip_udp_periodic() but takes a pointer to the actual + * uip_conn struct instead of an integer as its argument. This + * function can be used to force periodic processing of a specific + * connection. + * + * \param conn A pointer to the uip_udp_conn struct for the connection + * to be processed. + * + * \hideinitializer + */ +#define uip_udp_periodic_conn(conn) do { uip_udp_conn = conn; \ + uip_process(UIP_UDP_TIMER); } while (0) + + +#endif /* UIP_UDP */ + +/** + * The uIP packet buffer. + * + * The uip_buf array is used to hold incoming and outgoing + * packets. The device driver should place incoming data into this + * buffer. When sending data, the device driver should read the link + * level headers and the TCP/IP headers from this buffer. The size of + * the link level headers is configured by the UIP_LLH_LEN define. + * + * \note The application data need not be placed in this buffer, so + * the device driver must read it from the place pointed to by the + * uip_appdata pointer as illustrated by the following example: + \code + void + devicedriver_send(void) + { + hwsend(&uip_buf[0], UIP_LLH_LEN); + hwsend(&uip_buf[UIP_LLH_LEN], 40); + hwsend(uip_appdata, uip_len - 40 - UIP_LLH_LEN); + } + \endcode + */ +extern u8_t uip_buf[UIP_BUFSIZE+2]; /*_RB_ __attribute__ ((aligned (4)));*/ + +/** @} */ + +/*-----------------------------------------------------------------------------------*/ +/* Functions that are used by the uIP application program. Opening and + * closing connections, sending and receiving data, etc. is all + * handled by the functions below. +*/ +/** + * \defgroup uipappfunc uIP application functions + * @{ + * + * Functions used by an application running of top of uIP. + */ + +/** + * Start listening to the specified port. + * + * \note Since this function expects the port number in network byte + * order, a conversion using HTONS() or htons() is necessary. + * + \code + uip_listen(HTONS(80)); + \endcode + * + * \param port A 16-bit port number in network byte order. + */ +void uip_listen(u16_t port); + +/** + * Stop listening to the specified port. + * + * \note Since this function expects the port number in network byte + * order, a conversion using HTONS() or htons() is necessary. + * + \code + uip_unlisten(HTONS(80)); + \endcode + * + * \param port A 16-bit port number in network byte order. + */ +void uip_unlisten(u16_t port); + +/** + * Connect to a remote host using TCP. + * + * This function is used to start a new connection to the specified + * port on the specied host. It allocates a new connection identifier, + * sets the connection to the SYN_SENT state and sets the + * retransmission timer to 0. This will cause a TCP SYN segment to be + * sent out the next time this connection is periodically processed, + * which usually is done within 0.5 seconds after the call to + * uip_connect(). + * + * \note This function is avaliable only if support for active open + * has been configured by defining UIP_ACTIVE_OPEN to 1 in uipopt.h. + * + * \note Since this function requires the port number to be in network + * byte order, a convertion using HTONS() or htons() is necessary. + * + \code + u16_t ipaddr[2]; + + uip_ipaddr(ipaddr, 192,168,1,2); + uip_connect(ipaddr, HTONS(80)); + \endcode + * + * \param ripaddr A pointer to a 4-byte array representing the IP + * address of the remote hot. + * + * \param port A 16-bit port number in network byte order. + * + * \return A pointer to the uIP connection identifier for the new connection, + * or NULL if no connection could be allocated. + * + */ +struct uip_conn *uip_connect(u16_t *ripaddr, u16_t port); + + + +/** + * \internal + * + * Check if a connection has outstanding (i.e., unacknowledged) data. + * + * \param conn A pointer to the uip_conn structure for the connection. + * + * \hideinitializer + */ +#define uip_outstanding(conn) ((conn)->len) + +/** + * Send data on the current connection. + * + * This function is used to send out a single segment of TCP + * data. Only applications that have been invoked by uIP for event + * processing can send data. + * + * The amount of data that actually is sent out after a call to this + * funcion is determined by the maximum amount of data TCP allows. uIP + * will automatically crop the data so that only the appropriate + * amount of data is sent. The function uip_mss() can be used to query + * uIP for the amount of data that actually will be sent. + * + * \note This function does not guarantee that the sent data will + * arrive at the destination. If the data is lost in the network, the + * application will be invoked with the uip_rexmit() event being + * set. The application will then have to resend the data using this + * function. + * + * \param data A pointer to the data which is to be sent. + * + * \param len The maximum amount of data bytes to be sent. + * + * \hideinitializer + */ +#define uip_send(data, len) do { uip_sappdata = (data); uip_slen = (len);} while(0) + +/** + * The length of any incoming data that is currently avaliable (if avaliable) + * in the uip_appdata buffer. + * + * The test function uip_data() must first be used to check if there + * is any data available at all. + * + * \hideinitializer + */ +#define uip_datalen() uip_len + +/** + * The length of any out-of-band data (urgent data) that has arrived + * on the connection. + * + * \note The configuration parameter UIP_URGDATA must be set for this + * function to be enabled. + * + * \hideinitializer + */ +#define uip_urgdatalen() uip_urglen + +/** + * Close the current connection. + * + * This function will close the current connection in a nice way. + * + * \hideinitializer + */ +#define uip_close() (uip_flags = UIP_CLOSE) + +/** + * Abort the current connection. + * + * This function will abort (reset) the current connection, and is + * usually used when an error has occured that prevents using the + * uip_close() function. + * + * \hideinitializer + */ +#define uip_abort() (uip_flags = UIP_ABORT) + +/** + * Tell the sending host to stop sending data. + * + * This function will close our receiver's window so that we stop + * receiving data for the current connection. + * + * \hideinitializer + */ +#define uip_stop() (uip_conn->tcpstateflags |= UIP_STOPPED) + +/** + * Find out if the current connection has been previously stopped with + * uip_stop(). + * + * \hideinitializer + */ +#define uip_stopped(conn) ((conn)->tcpstateflags & UIP_STOPPED) + +/** + * Restart the current connection, if is has previously been stopped + * with uip_stop(). + * + * This function will open the receiver's window again so that we + * start receiving data for the current connection. + * + * \hideinitializer + */ +#define uip_restart() do { uip_flags |= UIP_NEWDATA; \ + uip_conn->tcpstateflags &= ~UIP_STOPPED; \ + } while(0) + + +/* uIP tests that can be made to determine in what state the current + connection is, and what the application function should do. */ + +/** + * Is new incoming data available? + * + * Will reduce to non-zero if there is new data for the application + * present at the uip_appdata pointer. The size of the data is + * avaliable through the uip_len variable. + * + * \hideinitializer + */ +#define uip_newdata() (uip_flags & UIP_NEWDATA) + +/** + * Has previously sent data been acknowledged? + * + * Will reduce to non-zero if the previously sent data has been + * acknowledged by the remote host. This means that the application + * can send new data. + * + * \hideinitializer + */ +#define uip_acked() (uip_flags & UIP_ACKDATA) + +/** + * Has the connection just been connected? + * + * Reduces to non-zero if the current connection has been connected to + * a remote host. This will happen both if the connection has been + * actively opened (with uip_connect()) or passively opened (with + * uip_listen()). + * + * \hideinitializer + */ +#define uip_connected() (uip_flags & UIP_CONNECTED) + +/** + * Has the connection been closed by the other end? + * + * Is non-zero if the connection has been closed by the remote + * host. The application may then do the necessary clean-ups. + * + * \hideinitializer + */ +#define uip_closed() (uip_flags & UIP_CLOSE) + +/** + * Has the connection been aborted by the other end? + * + * Non-zero if the current connection has been aborted (reset) by the + * remote host. + * + * \hideinitializer + */ +#define uip_aborted() (uip_flags & UIP_ABORT) + +/** + * Has the connection timed out? + * + * Non-zero if the current connection has been aborted due to too many + * retransmissions. + * + * \hideinitializer + */ +#define uip_timedout() (uip_flags & UIP_TIMEDOUT) + +/** + * Do we need to retransmit previously data? + * + * Reduces to non-zero if the previously sent data has been lost in + * the network, and the application should retransmit it. The + * application should send the exact same data as it did the last + * time, using the uip_send() function. + * + * \hideinitializer + */ +#define uip_rexmit() (uip_flags & UIP_REXMIT) + +/** + * Is the connection being polled by uIP? + * + * Is non-zero if the reason the application is invoked is that the + * current connection has been idle for a while and should be + * polled. + * + * The polling event can be used for sending data without having to + * wait for the remote host to send data. + * + * \hideinitializer + */ +#define uip_poll() (uip_flags & UIP_POLL) + +/** + * Get the initial maxium segment size (MSS) of the current + * connection. + * + * \hideinitializer + */ +#define uip_initialmss() (uip_conn->initialmss) + +/** + * Get the current maxium segment size that can be sent on the current + * connection. + * + * The current maxiumum segment size that can be sent on the + * connection is computed from the receiver's window and the MSS of + * the connection (which also is available by calling + * uip_initialmss()). + * + * \hideinitializer + */ +#define uip_mss() (uip_conn->mss) + +/** + * Set up a new UDP connection. + * + * \param ripaddr A pointer to a 4-byte structure representing the IP + * address of the remote host. + * + * \param rport The remote port number in network byte order. + * + * \return The uip_udp_conn structure for the new connection or NULL + * if no connection could be allocated. + */ +struct uip_udp_conn *uip_udp_new(u16_t *ripaddr, u16_t rport); + +/** + * Removed a UDP connection. + * + * \param conn A pointer to the uip_udp_conn structure for the connection. + * + * \hideinitializer + */ +#define uip_udp_remove(conn) (conn)->lport = 0 + +/** + * Send a UDP datagram of length len on the current connection. + * + * This function can only be called in response to a UDP event (poll + * or newdata). The data must be present in the uip_buf buffer, at the + * place pointed to by the uip_appdata pointer. + * + * \param len The length of the data in the uip_buf buffer. + * + * \hideinitializer + */ +#define uip_udp_send(len) uip_slen = (len) + +/** @} */ + +/* uIP convenience and converting functions. */ + +/** + * \defgroup uipconvfunc uIP conversion functions + * @{ + * + * These functions can be used for converting between different data + * formats used by uIP. + */ + +/** + * Pack an IP address into a 4-byte array which is used by uIP to + * represent IP addresses. + * + * Example: + \code + u16_t ipaddr[2]; + + uip_ipaddr(&ipaddr, 192,168,1,2); + \endcode + * + * \param addr A pointer to a 4-byte array that will be filled in with + * the IP addres. + * \param addr0 The first octet of the IP address. + * \param addr1 The second octet of the IP address. + * \param addr2 The third octet of the IP address. + * \param addr3 The forth octet of the IP address. + * + * \hideinitializer + */ +#define uip_ipaddr(addr, addr0,addr1,addr2,addr3) do { \ + (addr)[0] = HTONS(((addr0) << 8) | (addr1)); \ + (addr)[1] = HTONS(((addr2) << 8) | (addr3)); \ + } while(0) + +/** + * Convert 16-bit quantity from host byte order to network byte order. + * + * This macro is primarily used for converting constants from host + * byte order to network byte order. For converting variables to + * network byte order, use the htons() function instead. + * + * \hideinitializer + */ +#ifndef HTONS +# if BYTE_ORDER == BIG_ENDIAN +# define HTONS(n) (n) +# else /* BYTE_ORDER == BIG_ENDIAN */ +# define HTONS(n) ((((u16_t)((n) & 0xff)) << 8) | (((n) & 0xff00) >> 8)) +# endif /* BYTE_ORDER == BIG_ENDIAN */ +#endif /* HTONS */ + +/** + * Convert 16-bit quantity from host byte order to network byte order. + * + * This function is primarily used for converting variables from host + * byte order to network byte order. For converting constants to + * network byte order, use the HTONS() macro instead. + */ +#ifndef htons +u16_t htons(u16_t val); +#endif /* htons */ + +/** @} */ + +/** + * Pointer to the application data in the packet buffer. + * + * This pointer points to the application data when the application is + * called. If the application wishes to send data, the application may + * use this space to write the data into before calling uip_send(). + */ +extern volatile u8_t *uip_appdata; +extern volatile u8_t *uip_sappdata; + +#if UIP_URGDATA > 0 +/* u8_t *uip_urgdata: + * + * This pointer points to any urgent data that has been received. Only + * present if compiled with support for urgent data (UIP_URGDATA). + */ +extern volatile u8_t *uip_urgdata; +#endif /* UIP_URGDATA > 0 */ + + +/* u[8|16]_t uip_len: + * + * When the application is called, uip_len contains the length of any + * new data that has been received from the remote host. The + * application should set this variable to the size of any data that + * the application wishes to send. When the network device driver + * output function is called, uip_len should contain the length of the + * outgoing packet. + */ +extern volatile u16_t uip_len, uip_slen; + +#if UIP_URGDATA > 0 +extern volatile u8_t uip_urglen, uip_surglen; +#endif /* UIP_URGDATA > 0 */ + + +/** + * Representation of a uIP TCP connection. + * + * The uip_conn structure is used for identifying a connection. All + * but one field in the structure are to be considered read-only by an + * application. The only exception is the appstate field whos purpose + * is to let the application store application-specific state (e.g., + * file pointers) for the connection. The size of this field is + * configured in the "uipopt.h" header file. + */ +struct uip_conn { + u16_t ripaddr[2]; /**< The IP address of the remote host. */ + + u16_t lport; /**< The local TCP port, in network byte order. */ + u16_t rport; /**< The local remote TCP port, in network byte + order. */ + + u8_t rcv_nxt[4]; /**< The sequence number that we expect to + receive next. */ + u8_t snd_nxt[4]; /**< The sequence number that was last sent by + us. */ + u16_t len; /**< Length of the data that was previously sent. */ + u16_t mss; /**< Current maximum segment size for the + connection. */ + u16_t initialmss; /**< Initial maximum segment size for the + connection. */ + u8_t sa; /**< Retransmission time-out calculation state + variable. */ + u8_t sv; /**< Retransmission time-out calculation state + variable. */ + u8_t rto; /**< Retransmission time-out. */ + u8_t tcpstateflags; /**< TCP state and flags. */ + u8_t timer; /**< The retransmission timer. */ + u8_t nrtx; /**< The number of retransmissions for the last + segment sent. */ + + /** The application state. */ + u8_t appstate[UIP_APPSTATE_SIZE]; +}; + + +/* Pointer to the current connection. */ +extern struct uip_conn *uip_conn; +/* The array containing all uIP connections. */ +extern struct uip_conn uip_conns[UIP_CONNS]; +/** + * \addtogroup uiparch + * @{ + */ + +/** + * 4-byte array used for the 32-bit sequence number calculations. + */ +extern volatile u8_t uip_acc32[4]; + +/** @} */ + + +#if UIP_UDP +/** + * Representation of a uIP UDP connection. + */ +struct uip_udp_conn { + u16_t ripaddr[2]; /**< The IP address of the remote peer. */ + u16_t lport; /**< The local port number in network byte order. */ + u16_t rport; /**< The remote port number in network byte order. */ +}; + +extern struct uip_udp_conn *uip_udp_conn; +extern struct uip_udp_conn uip_udp_conns[UIP_UDP_CONNS]; +#endif /* UIP_UDP */ + +/** + * The structure holding the TCP/IP statistics that are gathered if + * UIP_STATISTICS is set to 1. + * + */ +struct uip_stats { + struct { + uip_stats_t drop; /**< Number of dropped packets at the IP + layer. */ + uip_stats_t recv; /**< Number of received packets at the IP + layer. */ + uip_stats_t sent; /**< Number of sent packets at the IP + layer. */ + uip_stats_t vhlerr; /**< Number of packets dropped due to wrong + IP version or header length. */ + uip_stats_t hblenerr; /**< Number of packets dropped due to wrong + IP length, high byte. */ + uip_stats_t lblenerr; /**< Number of packets dropped due to wrong + IP length, low byte. */ + uip_stats_t fragerr; /**< Number of packets dropped since they + were IP fragments. */ + uip_stats_t chkerr; /**< Number of packets dropped due to IP + checksum errors. */ + uip_stats_t protoerr; /**< Number of packets dropped since they + were neither ICMP, UDP nor TCP. */ + } ip; /**< IP statistics. */ + struct { + uip_stats_t drop; /**< Number of dropped ICMP packets. */ + uip_stats_t recv; /**< Number of received ICMP packets. */ + uip_stats_t sent; /**< Number of sent ICMP packets. */ + uip_stats_t typeerr; /**< Number of ICMP packets with a wrong + type. */ + } icmp; /**< ICMP statistics. */ + struct { + uip_stats_t drop; /**< Number of dropped TCP segments. */ + uip_stats_t recv; /**< Number of recived TCP segments. */ + uip_stats_t sent; /**< Number of sent TCP segments. */ + uip_stats_t chkerr; /**< Number of TCP segments with a bad + checksum. */ + uip_stats_t ackerr; /**< Number of TCP segments with a bad ACK + number. */ + uip_stats_t rst; /**< Number of recevied TCP RST (reset) segments. */ + uip_stats_t rexmit; /**< Number of retransmitted TCP segments. */ + uip_stats_t syndrop; /**< Number of dropped SYNs due to too few + connections was avaliable. */ + uip_stats_t synrst; /**< Number of SYNs for closed ports, + triggering a RST. */ + } tcp; /**< TCP statistics. */ +}; + +/** + * The uIP TCP/IP statistics. + * + * This is the variable in which the uIP TCP/IP statistics are gathered. + */ +extern struct uip_stats uip_stat; + + +/*-----------------------------------------------------------------------------------*/ +/* All the stuff below this point is internal to uIP and should not be + * used directly by an application or by a device driver. + */ +/*-----------------------------------------------------------------------------------*/ +/* u8_t uip_flags: + * + * When the application is called, uip_flags will contain the flags + * that are defined in this file. Please read below for more + * infomation. + */ +extern volatile u8_t uip_flags; + +/* The following flags may be set in the global variable uip_flags + before calling the application callback. The UIP_ACKDATA and + UIP_NEWDATA flags may both be set at the same time, whereas the + others are mutualy exclusive. Note that these flags should *NOT* be + accessed directly, but through the uIP functions/macros. */ + +#define UIP_ACKDATA 1 /* Signifies that the outstanding data was + acked and the application should send + out new data instead of retransmitting + the last data. */ +#define UIP_NEWDATA 2 /* Flags the fact that the peer has sent + us new data. */ +#define UIP_REXMIT 4 /* Tells the application to retransmit the + data that was last sent. */ +#define UIP_POLL 8 /* Used for polling the application, to + check if the application has data that + it wants to send. */ +#define UIP_CLOSE 16 /* The remote host has closed the + connection, thus the connection has + gone away. Or the application signals + that it wants to close the + connection. */ +#define UIP_ABORT 32 /* The remote host has aborted the + connection, thus the connection has + gone away. Or the application signals + that it wants to abort the + connection. */ +#define UIP_CONNECTED 64 /* We have got a connection from a remote + host and have set up a new connection + for it, or an active connection has + been successfully established. */ + +#define UIP_TIMEDOUT 128 /* The connection has been aborted due to + too many retransmissions. */ + + +/* uip_process(flag): + * + * The actual uIP function which does all the work. + */ +void uip_process(u8_t flag); + +/* The following flags are passed as an argument to the uip_process() + function. They are used to distinguish between the two cases where + uip_process() is called. It can be called either because we have + incoming data that should be processed, or because the periodic + timer has fired. */ + +#define UIP_DATA 1 /* Tells uIP that there is incoming data in + the uip_buf buffer. The length of the + data is stored in the global variable + uip_len. */ +#define UIP_TIMER 2 /* Tells uIP that the periodic timer has + fired. */ +#if UIP_UDP +#define UIP_UDP_TIMER 3 +#endif /* UIP_UDP */ + +/* The TCP states used in the uip_conn->tcpstateflags. */ +#define CLOSED 0 +#define SYN_RCVD 1 +#define SYN_SENT 2 +#define ESTABLISHED 3 +#define FIN_WAIT_1 4 +#define FIN_WAIT_2 5 +#define CLOSING 6 +#define TIME_WAIT 7 +#define LAST_ACK 8 +#define TS_MASK 15 + +#define UIP_STOPPED 16 + +#define UIP_TCPIP_HLEN 40 + +/* The TCP and IP headers. */ +typedef struct { + /* IP header. */ + u8_t vhl, + tos, + len[2], + ipid[2], + ipoffset[2], + ttl, + proto; + u16_t ipchksum; + u16_t srcipaddr[2], + destipaddr[2]; + + /* TCP header. */ + u16_t srcport, + destport; + u8_t seqno[4], + ackno[4], + tcpoffset, + flags, + wnd[2]; + u16_t tcpchksum; + u8_t urgp[2]; + u8_t optdata[4]; +} uip_tcpip_hdr; + +/* The ICMP and IP headers. */ +typedef struct { + /* IP header. */ + u8_t vhl, + tos, + len[2], + ipid[2], + ipoffset[2], + ttl, + proto; + u16_t ipchksum; + u16_t srcipaddr[2], + destipaddr[2]; + /* ICMP (echo) header. */ + u8_t type, icode; + u16_t icmpchksum; + u16_t id, seqno; +} uip_icmpip_hdr; + + +/* The UDP and IP headers. */ +typedef struct { + /* IP header. */ + u8_t vhl, + tos, + len[2], + ipid[2], + ipoffset[2], + ttl, + proto; + u16_t ipchksum; + u16_t srcipaddr[2], + destipaddr[2]; + + /* UDP header. */ + u16_t srcport, + destport; + u16_t udplen; + u16_t udpchksum; +} uip_udpip_hdr; + +#define UIP_PROTO_ICMP 1 +#define UIP_PROTO_TCP 6 +#define UIP_PROTO_UDP 17 + +#if UIP_FIXEDADDR +extern const u16_t uip_hostaddr[2]; +#else /* UIP_FIXEDADDR */ +extern u16_t uip_hostaddr[2]; +#endif /* UIP_FIXEDADDR */ + +#endif /* __UIP_H__ */ + + +/** @} */ + diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/uip/uip_arch.c b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/uip_arch.c new file mode 100644 index 000000000..9dad18cc5 --- /dev/null +++ b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/uip_arch.c @@ -0,0 +1,145 @@ +/* + * Copyright (c) 2001, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: uip_arch.c,v 1.2.2.1 2003/10/04 22:54:17 adam Exp $ + * + */ + + +#include "uip.h" +#include "uip_arch.h" + +#define BUF ((uip_tcpip_hdr *)&uip_buf[UIP_LLH_LEN]) +#define IP_PROTO_TCP 6 + +/*-----------------------------------------------------------------------------------*/ +void +uip_add32(u8_t *op32, u16_t op16) +{ + + uip_acc32[3] = op32[3] + (op16 & 0xff); + uip_acc32[2] = op32[2] + (op16 >> 8); + uip_acc32[1] = op32[1]; + uip_acc32[0] = op32[0]; + + if(uip_acc32[2] < (op16 >> 8)) { + ++uip_acc32[1]; + if(uip_acc32[1] == 0) { + ++uip_acc32[0]; + } + } + + + if(uip_acc32[3] < (op16 & 0xff)) { + ++uip_acc32[2]; + if(uip_acc32[2] == 0) { + ++uip_acc32[1]; + if(uip_acc32[1] == 0) { + ++uip_acc32[0]; + } + } + } +} +/*-----------------------------------------------------------------------------------*/ +u16_t +uip_chksum(u16_t *sdata, u16_t len) +{ + u16_t acc; + + for (acc = 0; len > 1; len -= 2) { + u16_t u = ((unsigned char *)sdata)[0] + (((unsigned char *)sdata)[1] << 8); + if ((acc += u) < u) { + /* Overflow, so we add the carry to acc (i.e., increase by + one). */ + ++acc; + } + ++sdata; + } + + /* add up any odd byte */ + if(len == 1) { + acc += htons(((u16_t)(*(u8_t *)sdata)) << 8); + if(acc < htons(((u16_t)(*(u8_t *)sdata)) << 8)) { + ++acc; + } + } + + return acc; +} +/*-----------------------------------------------------------------------------------*/ +u16_t +uip_ipchksum(void) +{ + return uip_chksum((u16_t *)&uip_buf[UIP_LLH_LEN], 20); +} +/*-----------------------------------------------------------------------------------*/ +u16_t +uip_tcpchksum(void) +{ + u16_t hsum, sum; + + + /* Compute the checksum of the TCP header. */ + hsum = uip_chksum((u16_t *)&uip_buf[20 + UIP_LLH_LEN], 20); + + /* Compute the checksum of the data in the TCP packet and add it to + the TCP header checksum. */ + sum = uip_chksum((u16_t *)uip_appdata, + (u16_t)(((((u16_t)(BUF->len[0]) << 8) + BUF->len[1]) - 40))); + + if((sum += hsum) < hsum) { + ++sum; + } + + if((sum += BUF->srcipaddr[0]) < BUF->srcipaddr[0]) { + ++sum; + } + if((sum += BUF->srcipaddr[1]) < BUF->srcipaddr[1]) { + ++sum; + } + if((sum += BUF->destipaddr[0]) < BUF->destipaddr[0]) { + ++sum; + } + if((sum += BUF->destipaddr[1]) < BUF->destipaddr[1]) { + ++sum; + } + if((sum += (u16_t)htons((u16_t)IP_PROTO_TCP)) < (u16_t)htons((u16_t)IP_PROTO_TCP)) { + ++sum; + } + + hsum = (u16_t)htons((((u16_t)(BUF->len[0]) << 8) + BUF->len[1]) - 20); + + if((sum += hsum) < hsum) { + ++sum; + } + + return sum; +} +/*-----------------------------------------------------------------------------------*/ diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/uip/uip_arch.h b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/uip_arch.h new file mode 100644 index 000000000..b2d133f2e --- /dev/null +++ b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/uip_arch.h @@ -0,0 +1,130 @@ +/** + * \defgroup uiparch Architecture specific uIP functions + * @{ + * + * The functions in the architecture specific module implement the IP + * check sum and 32-bit additions. + * + * The IP checksum calculation is the most computationally expensive + * operation in the TCP/IP stack and it therefore pays off to + * implement this in efficient assembler. The purpose of the uip-arch + * module is to let the checksum functions to be implemented in + * architecture specific assembler. + * + */ + +/** + * \file + * Declarations of architecture specific functions. + * \author Adam Dunkels + */ + +/* + * Copyright (c) 2001, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: uip_arch.h,v 1.1.2.2 2003/10/06 15:10:22 adam Exp $ + * + */ + +#ifndef __UIP_ARCH_H__ +#define __UIP_ARCH_H__ + +#include "uip.h" + +/** + * Carry out a 32-bit addition. + * + * Because not all architectures for which uIP is intended has native + * 32-bit arithmetic, uIP uses an external C function for doing the + * required 32-bit additions in the TCP protocol processing. This + * function should add the two arguments and place the result in the + * global variable uip_acc32. + * + * \note The 32-bit integer pointed to by the op32 parameter and the + * result in the uip_acc32 variable are in network byte order (big + * endian). + * + * \param op32 A pointer to a 4-byte array representing a 32-bit + * integer in network byte order (big endian). + * + * \param op16 A 16-bit integer in host byte order. + */ +void uip_add32(u8_t *op32, u16_t op16); + +/** + * Calculate the Internet checksum over a buffer. + * + * The Internet checksum is the one's complement of the one's + * complement sum of all 16-bit words in the buffer. + * + * See RFC1071. + * + * \note This function is not called in the current version of uIP, + * but future versions might make use of it. + * + * \param buf A pointer to the buffer over which the checksum is to be + * computed. + * + * \param len The length of the buffer over which the checksum is to + * be computed. + * + * \return The Internet checksum of the buffer. + */ +u16_t uip_chksum(u16_t *buf, u16_t len); + +/** + * Calculate the IP header checksum of the packet header in uip_buf. + * + * The IP header checksum is the Internet checksum of the 20 bytes of + * the IP header. + * + * \return The IP header checksum of the IP header in the uip_buf + * buffer. + */ +u16_t uip_ipchksum(void); + +/** + * Calculate the TCP checksum of the packet in uip_buf and uip_appdata. + * + * The TCP checksum is the Internet checksum of data contents of the + * TCP segment, and a pseudo-header as defined in RFC793. + * + * \note The uip_appdata pointer that points to the packet data may + * point anywhere in memory, so it is not possible to simply calculate + * the Internet checksum of the contents of the uip_buf buffer. + * + * \return The TCP checksum of the TCP segment in uip_buf and pointed + * to by uip_appdata. + */ +u16_t uip_tcpchksum(void); + +/** @} */ + +#endif /* __UIP_ARCH_H__ */ diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/uip/uip_arp.c b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/uip_arp.c new file mode 100644 index 000000000..db8d72d8c --- /dev/null +++ b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/uip_arp.c @@ -0,0 +1,429 @@ +/** + * \addtogroup uip + * @{ + */ + +/** + * \defgroup uiparp uIP Address Resolution Protocol + * @{ + * + * The Address Resolution Protocol ARP is used for mapping between IP + * addresses and link level addresses such as the Ethernet MAC + * addresses. ARP uses broadcast queries to ask for the link level + * address of a known IP address and the host which is configured with + * the IP address for which the query was meant, will respond with its + * link level address. + * + * \note This ARP implementation only supports Ethernet. + */ + +/** + * \file + * Implementation of the ARP Address Resolution Protocol. + * \author Adam Dunkels + * + */ + +/* + * Copyright (c) 2001-2003, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: uip_arp.c,v 1.7.2.3 2003/10/06 22:42:30 adam Exp $ + * + */ + + +#include "uip_arp.h" + +#include + +struct arp_hdr { + struct uip_eth_hdr ethhdr; + u16_t hwtype; + u16_t protocol; + u8_t hwlen; + u8_t protolen; + u16_t opcode; + struct uip_eth_addr shwaddr; + u16_t sipaddr[2]; + struct uip_eth_addr dhwaddr; + u16_t dipaddr[2]; +}; + +struct ethip_hdr { + struct uip_eth_hdr ethhdr; + /* IP header. */ + u8_t vhl, + tos, + len[2], + ipid[2], + ipoffset[2], + ttl, + proto; + u16_t ipchksum; + u16_t srcipaddr[2], + destipaddr[2]; +}; + +#define ARP_REQUEST 1 +#define ARP_REPLY 2 + +#define ARP_HWTYPE_ETH 1 + +struct arp_entry { + u16_t ipaddr[2]; + struct uip_eth_addr ethaddr; + u8_t time; +}; + +struct uip_eth_addr uip_ethaddr = {{UIP_ETHADDR0, + UIP_ETHADDR1, + UIP_ETHADDR2, + UIP_ETHADDR3, + UIP_ETHADDR4, + UIP_ETHADDR5}}; + +static struct arp_entry arp_table[UIP_ARPTAB_SIZE]; +static u16_t ipaddr[2]; +static u8_t i, c; + +static u8_t arptime; +static u8_t tmpage; + +#define BUF ((struct arp_hdr *)&uip_buf[0]) +#define IPBUF ((struct ethip_hdr *)&uip_buf[0]) +/*-----------------------------------------------------------------------------------*/ +/** + * Initialize the ARP module. + * + */ +/*-----------------------------------------------------------------------------------*/ +void +uip_arp_init(void) +{ + for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { + memset(arp_table[i].ipaddr, 0, 4); + } +} +/*-----------------------------------------------------------------------------------*/ +/** + * Periodic ARP processing function. + * + * This function performs periodic timer processing in the ARP module + * and should be called at regular intervals. The recommended interval + * is 10 seconds between the calls. + * + */ +/*-----------------------------------------------------------------------------------*/ +void +uip_arp_timer(void) +{ + struct arp_entry *tabptr; + + ++arptime; + for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { + tabptr = &arp_table[i]; + if((tabptr->ipaddr[0] | tabptr->ipaddr[1]) != 0 && + arptime - tabptr->time >= UIP_ARP_MAXAGE) { + memset(tabptr->ipaddr, 0, 4); + } + } + +} +/*-----------------------------------------------------------------------------------*/ +static void +uip_arp_update(u16_t *ipaddr, struct uip_eth_addr *ethaddr) +{ + register struct arp_entry *tabptr; + /* Walk through the ARP mapping table and try to find an entry to + update. If none is found, the IP -> MAC address mapping is + inserted in the ARP table. */ + for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { + + tabptr = &arp_table[i]; + /* Only check those entries that are actually in use. */ + if(tabptr->ipaddr[0] != 0 && + tabptr->ipaddr[1] != 0) { + + /* Check if the source IP address of the incoming packet matches + the IP address in this ARP table entry. */ + if(ipaddr[0] == tabptr->ipaddr[0] && + ipaddr[1] == tabptr->ipaddr[1]) { + + /* An old entry found, update this and return. */ + memcpy(tabptr->ethaddr.addr, ethaddr->addr, 6); + tabptr->time = arptime; + + return; + } + } + } + + /* If we get here, no existing ARP table entry was found, so we + create one. */ + + /* First, we try to find an unused entry in the ARP table. */ + for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { + tabptr = &arp_table[i]; + if(tabptr->ipaddr[0] == 0 && + tabptr->ipaddr[1] == 0) { + break; + } + } + + /* If no unused entry is found, we try to find the oldest entry and + throw it away. */ + if(i == UIP_ARPTAB_SIZE) { + tmpage = 0; + c = 0; + for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { + tabptr = &arp_table[i]; + if(arptime - tabptr->time > tmpage) { + tmpage = arptime - tabptr->time; + c = i; + } + } + i = c; + } + + /* Now, i is the ARP table entry which we will fill with the new + information. */ + memcpy(tabptr->ipaddr, ipaddr, 4); + memcpy(tabptr->ethaddr.addr, ethaddr->addr, 6); + tabptr->time = arptime; +} +/*-----------------------------------------------------------------------------------*/ +/** + * ARP processing for incoming IP packets + * + * This function should be called by the device driver when an IP + * packet has been received. The function will check if the address is + * in the ARP cache, and if so the ARP cache entry will be + * refreshed. If no ARP cache entry was found, a new one is created. + * + * This function expects an IP packet with a prepended Ethernet header + * in the uip_buf[] buffer, and the length of the packet in the global + * variable uip_len. + */ +/*-----------------------------------------------------------------------------------*/ +void +uip_arp_ipin(void) +{ + uip_len -= sizeof(struct uip_eth_hdr); + + /* Only insert/update an entry if the source IP address of the + incoming IP packet comes from a host on the local network. */ + if((IPBUF->srcipaddr[0] & uip_arp_netmask[0]) != + (uip_hostaddr[0] & uip_arp_netmask[0])) { + return; + } + if((IPBUF->srcipaddr[1] & uip_arp_netmask[1]) != + (uip_hostaddr[1] & uip_arp_netmask[1])) { + return; + } + uip_arp_update(IPBUF->srcipaddr, &(IPBUF->ethhdr.src)); + + return; +} +/*-----------------------------------------------------------------------------------*/ +/** + * ARP processing for incoming ARP packets. + * + * This function should be called by the device driver when an ARP + * packet has been received. The function will act differently + * depending on the ARP packet type: if it is a reply for a request + * that we previously sent out, the ARP cache will be filled in with + * the values from the ARP reply. If the incoming ARP packet is an ARP + * request for our IP address, an ARP reply packet is created and put + * into the uip_buf[] buffer. + * + * When the function returns, the value of the global variable uip_len + * indicates whether the device driver should send out a packet or + * not. If uip_len is zero, no packet should be sent. If uip_len is + * non-zero, it contains the length of the outbound packet that is + * present in the uip_buf[] buffer. + * + * This function expects an ARP packet with a prepended Ethernet + * header in the uip_buf[] buffer, and the length of the packet in the + * global variable uip_len. + */ +/*-----------------------------------------------------------------------------------*/ +typedef struct arp_hdr aht; + +void +uip_arp_arpin(void) +{ + int ul; + + if(uip_len < sizeof(struct arp_hdr)) { + uip_len = 0; + return; + } + + uip_len = 0; + + switch(BUF->opcode) { + case HTONS(ARP_REQUEST): + /* ARP request. If it asked for our address, we send out a + reply. */ + if(BUF->dipaddr[0] == uip_hostaddr[0] && + BUF->dipaddr[1] == uip_hostaddr[1]) { + /* The reply opcode is 2. */ + BUF->opcode = HTONS(2); + + memcpy(BUF->dhwaddr.addr, BUF->shwaddr.addr, 6); + memcpy(BUF->shwaddr.addr, uip_ethaddr.addr, 6); + memcpy(BUF->ethhdr.src.addr, uip_ethaddr.addr, 6); + memcpy(BUF->ethhdr.dest.addr, BUF->dhwaddr.addr, 6); + + BUF->dipaddr[0] = BUF->sipaddr[0]; + BUF->dipaddr[1] = BUF->sipaddr[1]; + BUF->sipaddr[0] = uip_hostaddr[0]; + BUF->sipaddr[1] = uip_hostaddr[1]; + + ul = BUF->hwlen; + BUF->ethhdr.type = HTONS(UIP_ETHTYPE_ARP); + uip_len = sizeof(struct arp_hdr); + } + break; + case HTONS(ARP_REPLY): + /* ARP reply. We insert or update the ARP table if it was meant + for us. */ + if(BUF->dipaddr[0] == uip_hostaddr[0] && + BUF->dipaddr[1] == uip_hostaddr[1]) { + + uip_arp_update(BUF->sipaddr, &BUF->shwaddr); + } + break; + } + + ( void ) ul; + + return; +} +/*-----------------------------------------------------------------------------------*/ +/** + * Prepend Ethernet header to an outbound IP packet and see if we need + * to send out an ARP request. + * + * This function should be called before sending out an IP packet. The + * function checks the destination IP address of the IP packet to see + * what Ethernet MAC address that should be used as a destination MAC + * address on the Ethernet. + * + * If the destination IP address is in the local network (determined + * by logical ANDing of netmask and our IP address), the function + * checks the ARP cache to see if an entry for the destination IP + * address is found. If so, an Ethernet header is prepended and the + * function returns. If no ARP cache entry is found for the + * destination IP address, the packet in the uip_buf[] is replaced by + * an ARP request packet for the IP address. The IP packet is dropped + * and it is assumed that they higher level protocols (e.g., TCP) + * eventually will retransmit the dropped packet. + * + * If the destination IP address is not on the local network, the IP + * address of the default router is used instead. + * + * When the function returns, a packet is present in the uip_buf[] + * buffer, and the length of the packet is in the global variable + * uip_len. + */ +/*-----------------------------------------------------------------------------------*/ +void +uip_arp_out(void) +{ + struct arp_entry *tabptr; + /* Find the destination IP address in the ARP table and construct + the Ethernet header. If the destination IP addres isn't on the + local network, we use the default router's IP address instead. + + If not ARP table entry is found, we overwrite the original IP + packet with an ARP request for the IP address. */ + + /* Check if the destination address is on the local network. */ + if((IPBUF->destipaddr[0] & uip_arp_netmask[0]) != + (uip_hostaddr[0] & uip_arp_netmask[0]) || + (IPBUF->destipaddr[1] & uip_arp_netmask[1]) != + (uip_hostaddr[1] & uip_arp_netmask[1])) { + /* Destination address was not on the local network, so we need to + use the default router's IP address instead of the destination + address when determining the MAC address. */ + ipaddr[0] = uip_arp_draddr[0]; + ipaddr[1] = uip_arp_draddr[1]; + } else { + /* Else, we use the destination IP address. */ + ipaddr[0] = IPBUF->destipaddr[0]; + ipaddr[1] = IPBUF->destipaddr[1]; + } + + for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { + tabptr = &arp_table[i]; + if(ipaddr[0] == tabptr->ipaddr[0] && + ipaddr[1] == tabptr->ipaddr[1]) + break; + } + + if(i == UIP_ARPTAB_SIZE) { + /* The destination address was not in our ARP table, so we + overwrite the IP packet with an ARP request. */ + + memset(BUF->ethhdr.dest.addr, 0xff, 6); + memset(BUF->dhwaddr.addr, 0x00, 6); + memcpy(BUF->ethhdr.src.addr, uip_ethaddr.addr, 6); + memcpy(BUF->shwaddr.addr, uip_ethaddr.addr, 6); + + BUF->dipaddr[0] = ipaddr[0]; + BUF->dipaddr[1] = ipaddr[1]; + BUF->sipaddr[0] = uip_hostaddr[0]; + BUF->sipaddr[1] = uip_hostaddr[1]; + BUF->opcode = HTONS(ARP_REQUEST); /* ARP request. */ + BUF->hwtype = HTONS(ARP_HWTYPE_ETH); + BUF->protocol = HTONS(UIP_ETHTYPE_IP); + BUF->hwlen = 6; + BUF->protolen = 4; + BUF->ethhdr.type = HTONS(UIP_ETHTYPE_ARP); + + uip_appdata = &uip_buf[40 + UIP_LLH_LEN]; + + uip_len = sizeof(struct arp_hdr); + return; + } + + /* Build an ethernet header. */ + memcpy(IPBUF->ethhdr.dest.addr, tabptr->ethaddr.addr, 6); + memcpy(IPBUF->ethhdr.src.addr, uip_ethaddr.addr, 6); + + IPBUF->ethhdr.type = HTONS(UIP_ETHTYPE_IP); + + uip_len += sizeof(struct uip_eth_hdr); +} +/*-----------------------------------------------------------------------------------*/ + +/** @} */ +/** @} */ diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/uip/uip_arp.h b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/uip_arp.h new file mode 100644 index 000000000..fadad57bb --- /dev/null +++ b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/uip_arp.h @@ -0,0 +1,201 @@ +/** + * \addtogroup uip + * @{ + */ + +/** + * \addtogroup uiparp + * @{ + */ + +/** + * \file + * Macros and definitions for the ARP module. + * \author Adam Dunkels + */ + + +/* + * Copyright (c) 2001-2003, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: uip_arp.h,v 1.3.2.2 2003/10/06 15:10:22 adam Exp $ + * + */ + +#ifndef __UIP_ARP_H__ +#define __UIP_ARP_H__ + +#include "uip.h" + + +/** + * Representation of a 48-bit Ethernet address. + */ +struct uip_eth_addr { + u8_t addr[6]; +} /*_RB_ __attribute__ ((packed, aligned (1))) */; + +extern struct uip_eth_addr uip_ethaddr; + +/** + * The Ethernet header. + */ +struct uip_eth_hdr { + struct uip_eth_addr dest; + struct uip_eth_addr src; + u16_t type; +} /*_RB_ __attribute__ ((packed)) */; + +#define UIP_ETHTYPE_ARP 0x0806 +#define UIP_ETHTYPE_IP 0x0800 +#define UIP_ETHTYPE_IP6 0x86dd + + +/* The uip_arp_init() function must be called before any of the other + ARP functions. */ +void uip_arp_init(void); + +/* The uip_arp_ipin() function should be called whenever an IP packet + arrives from the Ethernet. This function refreshes the ARP table or + inserts a new mapping if none exists. The function assumes that an + IP packet with an Ethernet header is present in the uip_buf buffer + and that the length of the packet is in the uip_len variable. */ +void uip_arp_ipin(void); + +/* The uip_arp_arpin() should be called when an ARP packet is received + by the Ethernet driver. This function also assumes that the + Ethernet frame is present in the uip_buf buffer. When the + uip_arp_arpin() function returns, the contents of the uip_buf + buffer should be sent out on the Ethernet if the uip_len variable + is > 0. */ +void uip_arp_arpin(void); + +/* The uip_arp_out() function should be called when an IP packet + should be sent out on the Ethernet. This function creates an + Ethernet header before the IP header in the uip_buf buffer. The + Ethernet header will have the correct Ethernet MAC destination + address filled in if an ARP table entry for the destination IP + address (or the IP address of the default router) is present. If no + such table entry is found, the IP packet is overwritten with an ARP + request and we rely on TCP to retransmit the packet that was + overwritten. In any case, the uip_len variable holds the length of + the Ethernet frame that should be transmitted. */ +void uip_arp_out(void); + +/* The uip_arp_timer() function should be called every ten seconds. It + is responsible for flushing old entries in the ARP table. */ +void uip_arp_timer(void); + +/** @} */ + +/** + * \addtogroup uipconffunc + * @{ + */ + +/** + * Set the default router's IP address. + * + * \param addr A pointer to a 4-byte array containing the IP address + * of the default router. + * + * \hideinitializer + */ +#define uip_setdraddr(addr) do { uip_arp_draddr[0] = addr[0]; \ + uip_arp_draddr[1] = addr[1]; } while(0) + +/** + * Set the netmask. + * + * \param addr A pointer to a 4-byte array containing the IP address + * of the netmask. + * + * \hideinitializer + */ +#define uip_setnetmask(addr) do { uip_arp_netmask[0] = addr[0]; \ + uip_arp_netmask[1] = addr[1]; } while(0) + + +/** + * Get the default router's IP address. + * + * \param addr A pointer to a 4-byte array that will be filled in with + * the IP address of the default router. + * + * \hideinitializer + */ +#define uip_getdraddr(addr) do { addr[0] = uip_arp_draddr[0]; \ + addr[1] = uip_arp_draddr[1]; } while(0) + +/** + * Get the netmask. + * + * \param addr A pointer to a 4-byte array that will be filled in with + * the value of the netmask. + * + * \hideinitializer + */ +#define uip_getnetmask(addr) do { addr[0] = uip_arp_netmask[0]; \ + addr[1] = uip_arp_netmask[1]; } while(0) + + +/** + * Specifiy the Ethernet MAC address. + * + * The ARP code needs to know the MAC address of the Ethernet card in + * order to be able to respond to ARP queries and to generate working + * Ethernet headers. + * + * \note This macro only specifies the Ethernet MAC address to the ARP + * code. It cannot be used to change the MAC address of the Ethernet + * card. + * + * \param eaddr A pointer to a struct uip_eth_addr containing the + * Ethernet MAC address of the Ethernet card. + * + * \hideinitializer + */ +#define uip_setethaddr(eaddr) do {uip_ethaddr.addr[0] = eaddr.addr[0]; \ + uip_ethaddr.addr[1] = eaddr.addr[1];\ + uip_ethaddr.addr[2] = eaddr.addr[2];\ + uip_ethaddr.addr[3] = eaddr.addr[3];\ + uip_ethaddr.addr[4] = eaddr.addr[4];\ + uip_ethaddr.addr[5] = eaddr.addr[5];} while(0) + +/** @} */ + +/** + * \internal Internal variables that are set using the macros + * uip_setdraddr and uip_setnetmask. + */ +extern u16_t uip_arp_draddr[2], uip_arp_netmask[2]; +#endif /* __UIP_ARP_H__ */ + + diff --git a/20080212/Demo/uIP_Demo_IAR_ARM7/uip/uipopt.h b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/uipopt.h new file mode 100644 index 000000000..18a578bd2 --- /dev/null +++ b/20080212/Demo/uIP_Demo_IAR_ARM7/uip/uipopt.h @@ -0,0 +1,560 @@ +/** + * \defgroup uipopt Configuration options for uIP + * @{ + * + * uIP is configured using the per-project configuration file + * "uipopt.h". This file contains all compile-time options for uIP and + * should be tweaked to match each specific project. The uIP + * distribution contains a documented example "uipopt.h" that can be + * copied and modified for each project. + */ + +/** + * \file + * Configuration options for uIP. + * \author Adam Dunkels + * + * This file is used for tweaking various configuration options for + * uIP. You should make a copy of this file into one of your project's + * directories instead of editing this example "uipopt.h" file that + * comes with the uIP distribution. + */ + +/* + * Copyright (c) 2001-2003, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: uipopt.h,v 1.16.2.5 2003/10/07 13:22:51 adam Exp $ + * + */ + +#ifndef __UIPOPT_H__ +#define __UIPOPT_H__ + +/*------------------------------------------------------------------------------*/ +/** + * \defgroup uipopttypedef uIP type definitions + * @{ + */ + +/** + * The 8-bit unsigned data type. + * + * This may have to be tweaked for your particular compiler. "unsigned + * char" works for most compilers. + */ +typedef unsigned char u8_t; + +/** + * The 16-bit unsigned data type. + * + * This may have to be tweaked for your particular compiler. "unsigned + * short" works for most compilers. + */ +typedef unsigned short u16_t; + +/** + * The statistics data type. + * + * This datatype determines how high the statistics counters are able + * to count. + */ +typedef unsigned short uip_stats_t; + +/** @} */ + +/*------------------------------------------------------------------------------*/ + +/** + * \defgroup uipoptstaticconf Static configuration options + * @{ + * + * These configuration options can be used for setting the IP address + * settings statically, but only if UIP_FIXEDADDR is set to 1. The + * configuration options for a specific node includes IP address, + * netmask and default router as well as the Ethernet address. The + * netmask, default router and Ethernet address are appliciable only + * if uIP should be run over Ethernet. + * + * All of these should be changed to suit your project. +*/ + +/** + * Determines if uIP should use a fixed IP address or not. + * + * If uIP should use a fixed IP address, the settings are set in the + * uipopt.h file. If not, the macros uip_sethostaddr(), + * uip_setdraddr() and uip_setnetmask() should be used instead. + * + * \hideinitializer + */ +#define UIP_FIXEDADDR 1 + +/** + * Ping IP address asignment. + * + * uIP uses a "ping" packets for setting its own IP address if this + * option is set. If so, uIP will start with an empty IP address and + * the destination IP address of the first incoming "ping" (ICMP echo) + * packet will be used for setting the hosts IP address. + * + * \note This works only if UIP_FIXEDADDR is 0. + * + * \hideinitializer + */ +#define UIP_PINGADDRCONF 0 + + +#define UIP_IPADDR0 172U /**< The first octet of the IP address of + this uIP node, if UIP_FIXEDADDR is + 1. \hideinitializer */ +#define UIP_IPADDR1 25U /**< The second octet of the IP address of + this uIP node, if UIP_FIXEDADDR is + 1. \hideinitializer */ +#define UIP_IPADDR2 218U /**< The third octet of the IP address of + this uIP node, if UIP_FIXEDADDR is + 1. \hideinitializer */ +#define UIP_IPADDR3 11U /**< The fourth octet of the IP address of + this uIP node, if UIP_FIXEDADDR is + 1. \hideinitializer */ + +#define UIP_NETMASK0 255 /**< The first octet of the netmask of + this uIP node, if UIP_FIXEDADDR is + 1. \hideinitializer */ +#define UIP_NETMASK1 255 /**< The second octet of the netmask of + this uIP node, if UIP_FIXEDADDR is + 1. \hideinitializer */ +#define UIP_NETMASK2 0 /**< The third octet of the netmask of + this uIP node, if UIP_FIXEDADDR is + 1. \hideinitializer */ +#define UIP_NETMASK3 0 /**< The fourth octet of the netmask of + this uIP node, if UIP_FIXEDADDR is + 1. \hideinitializer */ + +#define UIP_DRIPADDR0 172 /**< The first octet of the IP address of + the default router, if UIP_FIXEDADDR is + 1. \hideinitializer */ +#define UIP_DRIPADDR1 25 /**< The second octet of the IP address of + the default router, if UIP_FIXEDADDR is + 1. \hideinitializer */ +#define UIP_DRIPADDR2 218 /**< The third octet of the IP address of + the default router, if UIP_FIXEDADDR is + 1. \hideinitializer */ +#define UIP_DRIPADDR3 3 /**< The fourth octet of the IP address of + the default router, if UIP_FIXEDADDR is + 1. \hideinitializer */ + + + +/** + * Specifies if the uIP ARP module should be compiled with a fixed + * Ethernet MAC address or not. + * + * If this configuration option is 0, the macro uip_setethaddr() can + * be used to specify the Ethernet address at run-time. + * + * \hideinitializer + */ +#define UIP_FIXEDETHADDR 0 + +#define UIP_ETHADDR0 0x00 /**< The first octet of the Ethernet + address if UIP_FIXEDETHADDR is + 1. \hideinitializer */ +#define UIP_ETHADDR1 0xbd /**< The second octet of the Ethernet + address if UIP_FIXEDETHADDR is + 1. \hideinitializer */ +#define UIP_ETHADDR2 0x3b /**< The third octet of the Ethernet + address if UIP_FIXEDETHADDR is + 1. \hideinitializer */ +#define UIP_ETHADDR3 0x33 /**< The fourth octet of the Ethernet + address if UIP_FIXEDETHADDR is + 1. \hideinitializer */ +#define UIP_ETHADDR4 0x06 /**< The fifth octet of the Ethernet + address if UIP_FIXEDETHADDR is + 1. \hideinitializer */ +#define UIP_ETHADDR5 0x65 /**< The sixth octet of the Ethernet + address if UIP_FIXEDETHADDR is + 1. \hideinitializer */ + +/** @} */ +/*------------------------------------------------------------------------------*/ +/** + * \defgroup uipoptip IP configuration options + * @{ + * + */ +/** + * The IP TTL (time to live) of IP packets sent by uIP. + * + * This should normally not be changed. + */ +#define UIP_TTL 255 + +/** + * Turn on support for IP packet reassembly. + * + * uIP supports reassembly of fragmented IP packets. This features + * requires an additonal amount of RAM to hold the reassembly buffer + * and the reassembly code size is approximately 700 bytes. The + * reassembly buffer is of the same size as the uip_buf buffer + * (configured by UIP_BUFSIZE). + * + * \note IP packet reassembly is not heavily tested. + * + * \hideinitializer + */ +#define UIP_REASSEMBLY 0 + +/** + * The maximum time an IP fragment should wait in the reassembly + * buffer before it is dropped. + * + */ +#define UIP_REASS_MAXAGE 40 + +/** @} */ + +/*------------------------------------------------------------------------------*/ +/** + * \defgroup uipoptudp UDP configuration options + * @{ + * + * \note The UDP support in uIP is still not entirely complete; there + * is no support for sending or receiving broadcast or multicast + * packets, but it works well enough to support a number of vital + * applications such as DNS queries, though + */ + +/** + * Toggles wether UDP support should be compiled in or not. + * + * \hideinitializer + */ +#define UIP_UDP 0 + +/** + * Toggles if UDP checksums should be used or not. + * + * \note Support for UDP checksums is currently not included in uIP, + * so this option has no function. + * + * \hideinitializer + */ +#define UIP_UDP_CHECKSUMS 0 + +/** + * The maximum amount of concurrent UDP connections. + * + * \hideinitializer + */ +#define UIP_UDP_CONNS 2 + +/** + * The name of the function that should be called when UDP datagrams arrive. + * + * \hideinitializer + */ +#define UIP_UDP_APPCALL udp_appcall + +/** @} */ +/*------------------------------------------------------------------------------*/ +/** + * \defgroup uipopttcp TCP configuration options + * @{ + */ + +/** + * Determines if support for opening connections from uIP should be + * compiled in. + * + * If the applications that are running on top of uIP for this project + * do not need to open outgoing TCP connections, this configration + * option can be turned off to reduce the code size of uIP. + * + * \hideinitializer + */ +#define UIP_ACTIVE_OPEN 0 + +/** + * The maximum number of simultaneously open TCP connections. + * + * Since the TCP connections are statically allocated, turning this + * configuration knob down results in less RAM used. Each TCP + * connection requires approximatly 30 bytes of memory. + * + * \hideinitializer + */ +#define UIP_CONNS 25 + +/** + * The maximum number of simultaneously listening TCP ports. + * + * Each listening TCP port requires 2 bytes of memory. + * + * \hideinitializer + */ +#define UIP_LISTENPORTS 10 + +/** + * The size of the advertised receiver's window. + * + * Should be set low (i.e., to the size of the uip_buf buffer) is the + * application is slow to process incoming data, or high (32768 bytes) + * if the application processes data quickly. + * + * \hideinitializer + */ +#define UIP_RECEIVE_WINDOW 32768 + +/** + * Determines if support for TCP urgent data notification should be + * compiled in. + * + * Urgent data (out-of-band data) is a rarely used TCP feature that + * very seldom would be required. + * + * \hideinitializer + */ +#define UIP_URGDATA 1 + +/** + * The initial retransmission timeout counted in timer pulses. + * + * This should not be changed. + */ +#define UIP_RTO 3 + +/** + * The maximum number of times a segment should be retransmitted + * before the connection should be aborted. + * + * This should not be changed. + */ +#define UIP_MAXRTX 8 + +/** + * The maximum number of times a SYN segment should be retransmitted + * before a connection request should be deemed to have been + * unsuccessful. + * + * This should not need to be changed. + */ +#define UIP_MAXSYNRTX 3 + +/** + * The TCP maximum segment size. + * + * This is should not be to set to more than UIP_BUFSIZE - UIP_LLH_LEN - 40. + */ +#define UIP_TCP_MSS (UIP_BUFSIZE - UIP_LLH_LEN - 40) + +/** + * How long a connection should stay in the TIME_WAIT state. + * + * This configiration option has no real implication, and it should be + * left untouched. + */ +#define UIP_TIME_WAIT_TIMEOUT 120 + + +/** @} */ +/*------------------------------------------------------------------------------*/ +/** + * \defgroup uipoptarp ARP configuration options + * @{ + */ + +/** + * The size of the ARP table. + * + * This option should be set to a larger value if this uIP node will + * have many connections from the local network. + * + * \hideinitializer + */ +#define UIP_ARPTAB_SIZE 8 + +/** + * The maxium age of ARP table entries measured in 10ths of seconds. + * + * An UIP_ARP_MAXAGE of 120 corresponds to 20 minutes (BSD + * default). + */ +#define UIP_ARP_MAXAGE 120 + +/** @} */ + +/*------------------------------------------------------------------------------*/ + +/** + * \defgroup uipoptgeneral General configuration options + * @{ + */ + +/** + * The size of the uIP packet buffer. + * + * The uIP packet buffer should not be smaller than 60 bytes, and does + * not need to be larger than 1500 bytes. Lower size results in lower + * TCP throughput, larger size results in higher TCP throughput. + * + * \hideinitializer + */ +#define UIP_BUFSIZE 1480 + + +/** + * Determines if statistics support should be compiled in. + * + * The statistics is useful for debugging and to show the user. + * + * \hideinitializer + */ +#define UIP_STATISTICS 1 + +/** + * Determines if logging of certain events should be compiled in. + * + * This is useful mostly for debugging. The function uip_log() + * must be implemented to suit the architecture of the project, if + * logging is turned on. + * + * \hideinitializer + */ +#define UIP_LOGGING 0 + +/** + * Print out a uIP log message. + * + * This function must be implemented by the module that uses uIP, and + * is called by uIP whenever a log message is generated. + */ +void uip_log(char *msg); + +/** + * The link level header length. + * + * This is the offset into the uip_buf where the IP header can be + * found. For Ethernet, this should be set to 14. For SLIP, this + * should be set to 0. + * + * \hideinitializer + */ +#define UIP_LLH_LEN 14 + + +/** @} */ +/*------------------------------------------------------------------------------*/ +/** + * \defgroup uipoptcpu CPU architecture configuration + * @{ + * + * The CPU architecture configuration is where the endianess of the + * CPU on which uIP is to be run is specified. Most CPUs today are + * little endian, and the most notable exception are the Motorolas + * which are big endian. The BYTE_ORDER macro should be changed to + * reflect the CPU architecture on which uIP is to be run. + */ +#ifndef LITTLE_ENDIAN +#define LITTLE_ENDIAN 3412 +#endif /* LITTLE_ENDIAN */ +#ifndef BIG_ENDIAN +#define BIG_ENDIAN 1234 +#endif /* BIGE_ENDIAN */ + +/** + * The byte order of the CPU architecture on which uIP is to be run. + * + * This option can be either BIG_ENDIAN (Motorola byte order) or + * LITTLE_ENDIAN (Intel byte order). + * + * \hideinitializer + */ +#ifndef BYTE_ORDER +#define BYTE_ORDER LITTLE_ENDIAN +#endif /* BYTE_ORDER */ + +/** @} */ +/*------------------------------------------------------------------------------*/ + +/** + * \defgroup uipoptapp Appication specific configurations + * @{ + * + * An uIP application is implemented using a single application + * function that is called by uIP whenever a TCP/IP event occurs. The + * name of this function must be registered with uIP at compile time + * using the UIP_APPCALL definition. + * + * uIP applications can store the application state within the + * uip_conn structure by specifying the size of the application + * structure with the UIP_APPSTATE_SIZE macro. + * + * The file containing the definitions must be included in the + * uipopt.h file. + * + * The following example illustrates how this can look. + \code + +void httpd_appcall(void); +#define UIP_APPCALL httpd_appcall + +struct httpd_state { + u8_t state; + u16_t count; + char *dataptr; + char *script; +}; +#define UIP_APPSTATE_SIZE (sizeof(struct httpd_state)) + \endcode + */ + +/** + * \var #define UIP_APPCALL + * + * The name of the application function that uIP should call in + * response to TCP/IP events. + * + */ + +/** + * \var #define UIP_APPSTATE_SIZE + * + * The size of the application state that is to be stored in the + * uip_conn structure. + */ +/** @} */ + +/* Include the header file for the application program that should be + used. If you don't use the example web server, you should change + this. */ +#include "httpd.h" + + +#endif /* __UIPOPT_H__ */ diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/FreeRTOSConfig.h b/20080212/Demo/uIP_Demo_Rowley_ARM7/FreeRTOSConfig.h new file mode 100644 index 000000000..bdf23d26a --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/FreeRTOSConfig.h @@ -0,0 +1,89 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include +#define vPortYieldProcessor swi_handler + + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 58982400 ) /* =14.7456MHz xtal multiplied by 4 using the PLL. */ +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 128 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 10 * 1024 ) ) +#define configMAX_TASK_NAME_LEN ( 16 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/Philips_LPC210X_Startup.s b/20080212/Demo/uIP_Demo_Rowley_ARM7/Philips_LPC210X_Startup.s new file mode 100644 index 000000000..47debb720 --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/Philips_LPC210X_Startup.s @@ -0,0 +1,213 @@ +/***************************************************************************** + * Copyright (c) 2001, 2002 Rowley Associates Limited. * + * * + * This file may be distributed under the terms of the License Agreement * + * provided with this software. * + * * + * THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE * + * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * + *****************************************************************************/ + +/***************************************************************************** + * Preprocessor Definitions + * ------------------------ + * + * VECTORED_IRQ_INTERRUPTS + * + * Enable vectored IRQ interrupts. If defined, the PC register will be loaded + * with the contents of the VICVectAddr register on an IRQ exception. + * + * USE_PLL + * + * If defined, connect PLL as processor clock source. If undefined, the + * oscillator clock will be used. + * + * PLLCFG_VAL + * + * Override the default PLL configuration (multiplier = 5, divider = 2) + * by defining PLLCFG_VAL. + * + * USE_MAM + * + * If defined then the memory accelerator module (MAM) will be enabled. + * + * MAMCR_VAL & MAMTIM_VAL + * + * Override the default MAM configuration (fully enabled, 3 fetch cycles) + * by defining MAMCR_VAL and MAMTIM_VAL. + * + * VPBDIV_VAL + * + * If defined then this value will be used to configure the VPB divider. + * + * SRAM_EXCEPTIONS + * + * If defined, enable copying and re-mapping of interrupt vectors from User + * FLASH to SRAM. If undefined, interrupt vectors will be mapped in User + * FLASH. + * + *****************************************************************************/ + +#ifndef PLLCFG_VAL +#define PLLCFG_VAL 0x24 +#endif + +#ifndef MAMCR_VAL +#define MAMCR_VAL 2 +#endif + +#ifndef MAMTIM_VAL +#define MAMTIM_VAL 3 +#endif + +#define MAMCR_OFFS 0x000 +#define MAMTIM_OFFS 0x004 + +#define PLLCON_OFFS 0x080 +#define PLLCFG_OFFS 0x084 +#define PLLSTAT_OFFS 0x088 +#define PLLFEED_OFFS 0x08C + +#define VPBDIV_OFFS 0x100 + + .section .vectors, "ax" + .code 32 + .align 0 + +/***************************************************************************** + * Exception Vectors * + *****************************************************************************/ +_vectors: + ldr pc, [pc, #reset_handler_address - . - 8] /* reset */ + ldr pc, [pc, #undef_handler_address - . - 8] /* undefined instruction */ + ldr pc, [pc, #swi_handler_address - . - 8] /* swi handler */ + ldr pc, [pc, #pabort_handler_address - . - 8] /* abort prefetch */ + ldr pc, [pc, #dabort_handler_address - . - 8] /* abort data */ +#ifdef VECTORED_IRQ_INTERRUPTS + .word 0xB9205F84 /* boot loader checksum */ + ldr pc, [pc, #-0xFF0] /* irq handler */ +#else + .word 0xB8A06F60 /* boot loader checksum */ + ldr pc, [pc, #irq_handler_address - . - 8] /* irq handler */ +#endif + ldr pc, [pc, #fiq_handler_address - . - 8] /* fiq handler */ + +reset_handler_address: + .word reset_handler +undef_handler_address: + .word undef_handler +swi_handler_address: + .word swi_handler +pabort_handler_address: + .word pabort_handler +dabort_handler_address: + .word dabort_handler +irq_handler_address: + .word irq_handler +fiq_handler_address: + .word fiq_handler + + .section .init, "ax" + .code 32 + .align 0 + +/****************************************************************************** + * * + * Default exception handlers * + * * + ******************************************************************************/ + +reset_handler: +#if defined(USE_PLL) || defined(USE_MAM) || defined(VPBDIV_VAL) + ldr r0, =0xE01FC000 +#endif +#if defined(USE_PLL) + /* Configure PLL Multiplier/Divider */ + ldr r1, =PLLCFG_VAL + str r1, [r0, #PLLCFG_OFFS] + /* Enable PLL */ + mov r1, #0x1 + str r1, [r0, #PLLCON_OFFS] + mov r1, #0xAA + str r1, [r0, #PLLFEED_OFFS] + mov r1, #0x55 + str r1, [r0, #PLLFEED_OFFS] + /* Wait for PLL to lock */ +pll_lock_loop: + ldr r1, [r0, #PLLSTAT_OFFS] + tst r1, #0x400 + beq pll_lock_loop + /* PLL Locked, connect PLL as clock source */ + mov r1, #0x3 + str r1, [r0, #PLLCON_OFFS] + mov r1, #0xAA + str r1, [r0, #PLLFEED_OFFS] + mov r1, #0x55 + str r1, [r0, #PLLFEED_OFFS] +#endif + +#if defined(USE_MAM) + mov r1, #0 + str r1, [r0, #MAMCR_OFFS] + ldr r1, =MAMTIM_VAL + str r1, [r0, #MAMTIM_OFFS] + ldr r1, =MAMCR_VAL + str r1, [r0, #MAMCR_OFFS] +#endif + +#if defined(VPBDIV_VAL) + ldr r1, =VPBDIV_VAL + str r1, [r0, #VPBDIV_OFFS] +#endif + +#if defined(SRAM_EXCEPTIONS) + /* Copy exception vectors into SRAM */ + mov r8, #0x40000000 + ldr r9, =_vectors + ldmia r9!, {r0-r7} + stmia r8!, {r0-r7} + ldmia r9!, {r0-r6} + stmia r8!, {r0-r6} + + /* Re-map interrupt vectors from SRAM */ + ldr r0, MEMMAP + mov r1, #2 /* User RAM Mode. Interrupt vectors are re-mapped from SRAM */ + str r1, [r0] +#endif /* SRAM_EXCEPTIONS */ + + b _start + +#ifdef SRAM_EXCEPTIONS +MEMMAP: + .word 0xE01FC040 +#endif + +/****************************************************************************** + * * + * Default exception handlers * + * These are declared weak symbols so they can be redefined in user code. * + * * + ******************************************************************************/ + +undef_handler: + b undef_handler + +swi_handler: + b swi_handler + +pabort_handler: + b pabort_handler + +dabort_handler: + b dabort_handler + +irq_handler: + b irq_handler + +fiq_handler: + b fiq_handler + + .weak undef_handler, swi_handler, pabort_handler, dabort_handler, irq_handler, fiq_handler + + + diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/flash_placement.xml b/20080212/Demo/uIP_Demo_Rowley_ARM7/flash_placement.xml new file mode 100644 index 000000000..449adf2e4 --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/flash_placement.xml @@ -0,0 +1,29 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/lpc210x.h b/20080212/Demo/uIP_Demo_Rowley_ARM7/lpc210x.h new file mode 100644 index 000000000..3f1e3042d --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/lpc210x.h @@ -0,0 +1,321 @@ +#ifndef lpc210x_h +#define lpc210x_h +/******************************************************************************* +lpc210x.h - Register defs for Philips LPC210X: LPC2104, LPC2105 and LPC2106 + + +THE SOFTWARE IS DELIVERED "AS IS" WITHOUT WARRANTY OR CONDITION OF ANY KIND, +EITHER EXPRESS, IMPLIED OR STATUTORY. THIS INCLUDES WITHOUT LIMITATION ANY +WARRANTY OR CONDITION WITH RESPECT TO MERCHANTABILITY OR FITNESS FOR ANY +PARTICULAR PURPOSE, OR AGAINST THE INFRINGEMENTS OF INTELLECTUAL PROPERTY RIGHTS +OF OTHERS. + +This file may be freely used for commercial and non-commercial applications, +including being redistributed with any tools. + +If you find a problem with the file, please report it so that it can be fixed. + +Created by Sten Larsson (sten_larsson at yahoo com) + +Edited by Richard Barry. +*******************************************************************************/ + +#define REG8 (volatile unsigned char*) +#define REG16 (volatile unsigned short*) +#define REG32 (volatile unsigned int*) + + +/*############################################################################## +## MISC +##############################################################################*/ + + /* Constants for data to put in IRQ/FIQ Exception Vectors */ +#define VECTDATA_IRQ 0xE51FFFF0 /* LDR PC,[PC,#-0xFF0] */ +#define VECTDATA_FIQ /* __TODO */ + + +/*############################################################################## +## VECTORED INTERRUPT CONTROLLER +##############################################################################*/ + +#define VICIRQStatus (*(REG32 (0xFFFFF000))) +#define VICFIQStatus (*(REG32 (0xFFFFF004))) +#define VICRawIntr (*(REG32 (0xFFFFF008))) +#define VICIntSelect (*(REG32 (0xFFFFF00C))) +#define VICIntEnable (*(REG32 (0xFFFFF010))) +#define VICIntEnClear (*(REG32 (0xFFFFF014))) +#define VICSoftInt (*(REG32 (0xFFFFF018))) +#define VICSoftIntClear (*(REG32 (0xFFFFF01C))) +#define VICProtection (*(REG32 (0xFFFFF020))) +#define VICVectAddr (*(REG32 (0xFFFFF030))) +#define VICDefVectAddr (*(REG32 (0xFFFFF034))) + +#define VICVectAddr0 (*(REG32 (0xFFFFF100))) +#define VICVectAddr1 (*(REG32 (0xFFFFF104))) +#define VICVectAddr2 (*(REG32 (0xFFFFF108))) +#define VICVectAddr3 (*(REG32 (0xFFFFF10C))) +#define VICVectAddr4 (*(REG32 (0xFFFFF110))) +#define VICVectAddr5 (*(REG32 (0xFFFFF114))) +#define VICVectAddr6 (*(REG32 (0xFFFFF118))) +#define VICVectAddr7 (*(REG32 (0xFFFFF11C))) +#define VICVectAddr8 (*(REG32 (0xFFFFF120))) +#define VICVectAddr9 (*(REG32 (0xFFFFF124))) +#define VICVectAddr10 (*(REG32 (0xFFFFF128))) +#define VICVectAddr11 (*(REG32 (0xFFFFF12C))) +#define VICVectAddr12 (*(REG32 (0xFFFFF130))) +#define VICVectAddr13 (*(REG32 (0xFFFFF134))) +#define VICVectAddr14 (*(REG32 (0xFFFFF138))) +#define VICVectAddr15 (*(REG32 (0xFFFFF13C))) + +#define VICVectCntl0 (*(REG32 (0xFFFFF200))) +#define VICVectCntl1 (*(REG32 (0xFFFFF204))) +#define VICVectCntl2 (*(REG32 (0xFFFFF208))) +#define VICVectCntl3 (*(REG32 (0xFFFFF20C))) +#define VICVectCntl4 (*(REG32 (0xFFFFF210))) +#define VICVectCntl5 (*(REG32 (0xFFFFF214))) +#define VICVectCntl6 (*(REG32 (0xFFFFF218))) +#define VICVectCntl7 (*(REG32 (0xFFFFF21C))) +#define VICVectCntl8 (*(REG32 (0xFFFFF220))) +#define VICVectCntl9 (*(REG32 (0xFFFFF224))) +#define VICVectCntl10 (*(REG32 (0xFFFFF228))) +#define VICVectCntl11 (*(REG32 (0xFFFFF22C))) +#define VICVectCntl12 (*(REG32 (0xFFFFF230))) +#define VICVectCntl13 (*(REG32 (0xFFFFF234))) +#define VICVectCntl14 (*(REG32 (0xFFFFF238))) +#define VICVectCntl15 (*(REG32 (0xFFFFF23C))) + +#define VICITCR (*(REG32 (0xFFFFF300))) +#define VICITIP1 (*(REG32 (0xFFFFF304))) +#define VICITIP2 (*(REG32 (0xFFFFF308))) +#define VICITOP1 (*(REG32 (0xFFFFF30C))) +#define VICITOP2 (*(REG32 (0xFFFFF310))) +#define VICPeriphID0 (*(REG32 (0xFFFFFFE0))) +#define VICPeriphID1 (*(REG32 (0xFFFFFFE4))) +#define VICPeriphID2 (*(REG32 (0xFFFFFFE8))) +#define VICPeriphID3 (*(REG32 (0xFFFFFFEC))) + +#define VICIntEnClr VICIntEnClear +#define VICSoftIntClr VICSoftIntClear + + +/*############################################################################## +## PCB - Pin Connect Block +##############################################################################*/ + +#define PCB_PINSEL0 (*(REG32 (0xE002C000))) +#define PCB_PINSEL1 (*(REG32 (0xE002C004))) + + +/*############################################################################## +## GPIO - General Purpose I/O +##############################################################################*/ + +#define GPIO_IOPIN (*(REG32 (0xE0028000))) /* ALTERNATE NAME GPIO = GPIO0 */ +#define GPIO_IOSET (*(REG32 (0xE0028004))) +#define GPIO_IODIR (*(REG32 (0xE0028008))) +#define GPIO_IOCLR (*(REG32 (0xE002800C))) + +#define GPIO0_IOPIN (*(REG32 (0xE0028000))) /* ALTERNATE NAME GPIO = GPIO0 */ +#define GPIO0_IOSET (*(REG32 (0xE0028004))) +#define GPIO0_IODIR (*(REG32 (0xE0028008))) +#define GPIO0_IOCLR (*(REG32 (0xE002800C))) + + +/*############################################################################## +## UART0 / UART1 +##############################################################################*/ + +/* ---- UART 0 --------------------------------------------- */ +#define UART0_RBR (*(REG32 (0xE000C000))) +#define UART0_THR (*(REG32 (0xE000C000))) +#define UART0_IER (*(REG32 (0xE000C004))) +#define UART0_IIR (*(REG32 (0xE000C008))) +#define UART0_FCR (*(REG32 (0xE000C008))) +#define UART0_LCR (*(REG32 (0xE000C00C))) +#define UART0_LSR (*(REG32 (0xE000C014))) +#define UART0_SCR (*(REG32 (0xE000C01C))) +#define UART0_DLL (*(REG32 (0xE000C000))) +#define UART0_DLM (*(REG32 (0xE000C004))) + +/* ---- UART 1 --------------------------------------------- */ +#define UART1_RBR (*(REG32 (0xE0010000))) +#define UART1_THR (*(REG32 (0xE0010000))) +#define UART1_IER (*(REG32 (0xE0010004))) +#define UART1_IIR (*(REG32 (0xE0010008))) +#define UART1_FCR (*(REG32 (0xE0010008))) +#define UART1_LCR (*(REG32 (0xE001000C))) +#define UART1_LSR (*(REG32 (0xE0010014))) +#define UART1_SCR (*(REG32 (0xE001001C))) +#define UART1_DLL (*(REG32 (0xE0010000))) +#define UART1_DLM (*(REG32 (0xE0010004))) +#define UART1_MCR (*(REG32 (0xE0010010))) +#define UART1_MSR (*(REG32 (0xE0010018))) + + +/*############################################################################## +## I2C +##############################################################################*/ + +#define I2C_I2CONSET (*(REG32 (0xE001C000))) +#define I2C_I2STAT (*(REG32 (0xE001C004))) +#define I2C_I2DAT (*(REG32 (0xE001C008))) +#define I2C_I2ADR (*(REG32 (0xE001C00C))) +#define I2C_I2SCLH (*(REG32 (0xE001C010))) +#define I2C_I2SCLL (*(REG32 (0xE001C014))) +#define I2C_I2CONCLR (*(REG32 (0xE001C018))) + + +/*############################################################################## +## SPI - Serial Peripheral Interface +##############################################################################*/ + +#define SPI_SPCR (*(REG32 (0xE0020000))) +#define SPI_SPSR (*(REG32 (0xE0020004))) +#define SPI_SPDR (*(REG32 (0xE0020008))) +#define SPI_SPCCR (*(REG32 (0xE002000C))) +#define SPI_SPTCR (*(REG32 (0xE0020010))) +#define SPI_SPTSR (*(REG32 (0xE0020014))) +#define SPI_SPTOR (*(REG32 (0xE0020018))) +#define SPI_SPINT (*(REG32 (0xE002001C))) + + +/*############################################################################## +## Timer 0 and Timer 1 +##############################################################################*/ + +/* ---- Timer 0 -------------------------------------------- */ +#define T0_IR (*(REG32 (0xE0004000))) +#define T0_TCR (*(REG32 (0xE0004004))) +#define T0_TC (*(REG32 (0xE0004008))) +#define T0_PR (*(REG32 (0xE000400C))) +#define T0_PC (*(REG32 (0xE0004010))) +#define T0_MCR (*(REG32 (0xE0004014))) +#define T0_MR0 (*(REG32 (0xE0004018))) +#define T0_MR1 (*(REG32 (0xE000401C))) +#define T0_MR2 (*(REG32 (0xE0004020))) +#define T0_MR3 (*(REG32 (0xE0004024))) +#define T0_CCR (*(REG32 (0xE0004028))) +#define T0_CR0 (*(REG32 (0xE000402C))) +#define T0_CR1 (*(REG32 (0xE0004030))) +#define T0_CR2 (*(REG32 (0xE0004034))) +#define T0_CR3 (*(REG32 (0xE0004038))) +#define T0_EMR (*(REG32 (0xE000403C))) + +/* ---- Timer 1 -------------------------------------------- */ +#define T1_IR (*(REG32 (0xE0008000))) +#define T1_TCR (*(REG32 (0xE0008004))) +#define T1_TC (*(REG32 (0xE0008008))) +#define T1_PR (*(REG32 (0xE000800C))) +#define T1_PC (*(REG32 (0xE0008010))) +#define T1_MCR (*(REG32 (0xE0008014))) +#define T1_MR0 (*(REG32 (0xE0008018))) +#define T1_MR1 (*(REG32 (0xE000801C))) +#define T1_MR2 (*(REG32 (0xE0008020))) +#define T1_MR3 (*(REG32 (0xE0008024))) +#define T1_CCR (*(REG32 (0xE0008028))) +#define T1_CR0 (*(REG32 (0xE000802C))) +#define T1_CR1 (*(REG32 (0xE0008030))) +#define T1_CR2 (*(REG32 (0xE0008034))) +#define T1_CR3 (*(REG32 (0xE0008038))) +#define T1_EMR (*(REG32 (0xE000803C))) + + +/*############################################################################## +## PWM +##############################################################################*/ + +#define PWM_IR (*(REG32 (0xE0014000))) +#define PWM_TCR (*(REG32 (0xE0014004))) +#define PWM_TC (*(REG32 (0xE0014008))) +#define PWM_PR (*(REG32 (0xE001400C))) +#define PWM_PC (*(REG32 (0xE0014010))) +#define PWM_MCR (*(REG32 (0xE0014014))) +#define PWM_MR0 (*(REG32 (0xE0014018))) +#define PWM_MR1 (*(REG32 (0xE001401C))) +#define PWM_MR2 (*(REG32 (0xE0014020))) +#define PWM_MR3 (*(REG32 (0xE0014024))) +#define PWM_MR4 (*(REG32 (0xE0014040))) +#define PWM_MR5 (*(REG32 (0xE0014044))) +#define PWM_MR6 (*(REG32 (0xE0014048))) +#define PWM_EMR (*(REG32 (0xE001403C))) +#define PWM_PCR (*(REG32 (0xE001404C))) +#define PWM_LER (*(REG32 (0xE0014050))) +#define PWM_CCR (*(REG32 (0xE0014028))) +#define PWM_CR0 (*(REG32 (0xE001402C))) +#define PWM_CR1 (*(REG32 (0xE0014030))) +#define PWM_CR2 (*(REG32 (0xE0014034))) +#define PWM_CR3 (*(REG32 (0xE0014038))) + +/*############################################################################## +## RTC +##############################################################################*/ + +/* ---- RTC: Miscellaneous Register Group ------------------ */ +#define RTC_ILR (*(REG32 (0xE0024000))) +#define RTC_CTC (*(REG32 (0xE0024004))) +#define RTC_CCR (*(REG32 (0xE0024008))) +#define RTC_CIIR (*(REG32 (0xE002400C))) +#define RTC_AMR (*(REG32 (0xE0024010))) +#define RTC_CTIME0 (*(REG32 (0xE0024014))) +#define RTC_CTIME1 (*(REG32 (0xE0024018))) +#define RTC_CTIME2 (*(REG32 (0xE002401C))) + +/* ---- RTC: Timer Control Group --------------------------- */ +#define RTC_SEC (*(REG32 (0xE0024020))) +#define RTC_MIN (*(REG32 (0xE0024024))) +#define RTC_HOUR (*(REG32 (0xE0024028))) +#define RTC_DOM (*(REG32 (0xE002402C))) +#define RTC_DOW (*(REG32 (0xE0024030))) +#define RTC_DOY (*(REG32 (0xE0024034))) +#define RTC_MONTH (*(REG32 (0xE0024038))) +#define RTC_YEAR (*(REG32 (0xE002403C))) + +/* ---- RTC: Alarm Control Group --------------------------- */ +#define RTC_ALSEC (*(REG32 (0xE0024060))) +#define RTC_ALMIN (*(REG32 (0xE0024064))) +#define RTC_ALHOUR (*(REG32 (0xE0024068))) +#define RTC_ALDOM (*(REG32 (0xE002406C))) +#define RTC_ALDOW (*(REG32 (0xE0024070))) +#define RTC_ALDOY (*(REG32 (0xE0024074))) +#define RTC_ALMON (*(REG32 (0xE0024078))) +#define RTC_ALYEAR (*(REG32 (0xE002407C))) + +/* ---- RTC: Reference Clock Divider Group ----------------- */ +#define RTC_PREINT (*(REG32 (0xE0024080))) +#define RTC_PREFRAC (*(REG32 (0xE0024084))) + + +/*############################################################################## +## WD - Watchdog +##############################################################################*/ + +#define WD_WDMOD (*(REG32 (0xE0000000))) +#define WD_WDTC (*(REG32 (0xE0000004))) +#define WD_WDFEED (*(REG32 (0xE0000008))) +#define WD_WDTV (*(REG32 (0xE000000C))) + + +/*############################################################################## +## System Control Block +##############################################################################*/ + +#define SCB_EXTINT (*(REG32 (0xE01FC140))) +#define SCB_EXTWAKE (*(REG32 (0xE01FC144))) +#define SCB_MEMMAP (*(REG32 (0xE01FC040))) +#define SCB_PLLCON (*(REG32 (0xE01FC080))) +#define SCB_PLLCFG (*(REG32 (0xE01FC084))) +#define SCB_PLLSTAT (*(REG32 (0xE01FC088))) +#define SCB_PLLFEED (*(REG32 (0xE01FC08C))) +#define SCB_PCON (*(REG32 (0xE01FC0C0))) +#define SCB_PCONP (*(REG32 (0xE01FC0C4))) +#define SCB_VPBDIV (*(REG32 (0xE01FC100))) + +/*############################################################################## +## Memory Accelerator Module (MAM) +##############################################################################*/ + +#define MAM_TIM (*(REG32 (0xE01FC004))) +#define MAM_CR (*(REG32 (0xE01FC000))) + +#endif /* lpc210x_h */ + diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/main.c b/20080212/Demo/uIP_Demo_Rowley_ARM7/main.c new file mode 100644 index 000000000..aaa0307ca --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/main.c @@ -0,0 +1,294 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. + The processor MUST be in supervisor mode when vTaskStartScheduler is + called. The demo applications included in the FreeRTOS.org download switch + to supervisor mode prior to main being called. If you are not using one of + these demo application projects then ensure Supervisor mode is used. +*/ + + +/* + * Creates all the application tasks, then starts the scheduler. + * + * A task is created called "uIP". This executes the uIP stack and small + * WEB server sample. All the other tasks are from the set of standard + * demo tasks. The WEB documentation provides more details of the standard + * demo application tasks. + * + * Main.c also creates a task called "Check". This only executes every three + * seconds but has the highest priority so is guaranteed to get processor time. + * Its main function is to check that all the other tasks are still operational. + * Each standard demo task maintains a unique count that is incremented each + * time the task successfully completes its function. Should any error occur + * within such a task the count is permanently halted. The check task inspects + * the count of each task to ensure it has changed since the last time the + * check task executed. If all the count variables have changed all the tasks + * are still executing error free, and the check task toggles the yellow LED. + * Should any task contain an error at any time the LED toggle rate will change + * from 3 seconds to 500ms. + * + */ + + +/* Standard includes. */ +#include +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo application includes. */ +#include "PollQ.h" +#include "dynamic.h" +#include "semtest.h" + +/*-----------------------------------------------------------*/ + +/* Constants to setup the PLL. */ +#define mainPLL_MUL_4 ( ( unsigned portCHAR ) 0x0003 ) +#define mainPLL_DIV_1 ( ( unsigned portCHAR ) 0x0000 ) +#define mainPLL_ENABLE ( ( unsigned portCHAR ) 0x0001 ) +#define mainPLL_CONNECT ( ( unsigned portCHAR ) 0x0003 ) +#define mainPLL_FEED_BYTE1 ( ( unsigned portCHAR ) 0xaa ) +#define mainPLL_FEED_BYTE2 ( ( unsigned portCHAR ) 0x55 ) +#define mainPLL_LOCK ( ( unsigned portLONG ) 0x0400 ) + +/* Constants to setup the MAM. */ +#define mainMAM_TIM_3 ( ( unsigned portCHAR ) 0x03 ) +#define mainMAM_MODE_FULL ( ( unsigned portCHAR ) 0x02 ) + +/* Constants to setup the peripheral bus. */ +#define mainBUS_CLK_FULL ( ( unsigned portCHAR ) 0x01 ) + +/* Priorities/stacks for the demo application tasks. */ +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainUIP_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainUIP_TASK_STACK_SIZE ( 150 ) + +/* The rate at which the on board LED will toggle when there is/is not an +error. */ +#define mainNO_ERROR_FLASH_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS ) +#define mainERROR_FLASH_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS ) +#define mainON_BOARD_LED_BIT ( ( unsigned portLONG ) 0x80 ) +#define mainYELLOW_LED ( 1 << 11 ) + +/*-----------------------------------------------------------*/ + +/* + * This is the uIP task which is defined within the uip.c file. This has not + * been placed into a header file in order to minimise the changes to the uip + * code. + */ +extern void ( vuIP_TASK ) ( void *pvParameters ); + +/* + * The Yellow LED is under the control of the Check task. All the other LED's + * are under the control of the uIP task. + */ +void prvToggleOnBoardLED( void ); + +/* + * Checks that all the demo application tasks are still executing without error + * - as described at the top of the file. + */ +static portLONG prvCheckOtherTasksAreStillRunning( void ); + +/* + * The task that executes at the highest priority and calls + * prvCheckOtherTasksAreStillRunning(). See the description at the top + * of the file. + */ +static void vErrorChecks( void *pvParameters ); + +/* + * Configure the processor for use with the Olimex demo board. This includes + * setup for the I/O, system clock, and access timings. + */ +static void prvSetupHardware( void ); + +/*-----------------------------------------------------------*/ + +/* + * Starts all the other tasks, then starts the scheduler. + */ +int main( void ) +{ + /* Configure the processor. */ + prvSetupHardware(); + + /* Start the task that handles the TCP/IP functionality. */ + xTaskCreate( vuIP_TASK, "uIP", mainUIP_TASK_STACK_SIZE, NULL, mainUIP_PRIORITY, NULL ); + + /* Start the demo/test application tasks. These are created in addition + to the TCP/IP task for demonstration and test purposes. */ + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartDynamicPriorityTasks(); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + + /* Start the check task - which is defined in this file. */ + xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Now all the tasks have been started - start the scheduler. + + NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. + The processor MUST be in supervisor mode when vTaskStartScheduler is + called. The demo applications included in the FreeRTOS.org download switch + to supervisor mode prior to main being called. If you are not using one of + these demo application projects then ensure Supervisor mode is used here. */ + vTaskStartScheduler(); + + /* Should never reach here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +static void vErrorChecks( void *pvParameters ) +{ +portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD; + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. If an error is detected then the delay period + is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so + the on board LED flash rate will increase. */ + for( ;; ) + { + /* Delay until it is time to execute again. */ + vTaskDelay( xDelayPeriod ); + + /* Check all the standard demo application tasks are executing without + error. */ + if( prvCheckOtherTasksAreStillRunning() != pdPASS ) + { + /* An error has been detected in one of the tasks - flash faster. */ + xDelayPeriod = mainERROR_FLASH_PERIOD; + } + + prvToggleOnBoardLED(); + } +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + #ifdef RUN_FROM_RAM + /* Remap the interrupt vectors to RAM if we are are running from RAM. */ + SCB_MEMMAP = 2; + #endif + + /* Setup the PLL to multiply the XTAL input by 4. */ + SCB_PLLCFG = ( mainPLL_MUL_4 | mainPLL_DIV_1 ); + + /* Activate the PLL by turning it on then feeding the correct sequence of + bytes. */ + SCB_PLLCON = mainPLL_ENABLE; + SCB_PLLFEED = mainPLL_FEED_BYTE1; + SCB_PLLFEED = mainPLL_FEED_BYTE2; + + /* Wait for the PLL to lock... */ + while( !( SCB_PLLSTAT & mainPLL_LOCK ) ); + + /* ...before connecting it using the feed sequence again. */ + SCB_PLLCON = mainPLL_CONNECT; + SCB_PLLFEED = mainPLL_FEED_BYTE1; + SCB_PLLFEED = mainPLL_FEED_BYTE2; + + /* Setup and turn on the MAM. Three cycle access is used due to the fast + PLL used. It is possible faster overall performance could be obtained by + tuning the MAM and PLL settings. */ + MAM_TIM = mainMAM_TIM_3; + MAM_CR = mainMAM_MODE_FULL; + + /* Setup the peripheral bus to be the same as the PLL output. */ + SCB_VPBDIV = mainBUS_CLK_FULL; +} +/*-----------------------------------------------------------*/ + +void prvToggleOnBoardLED( void ) +{ +unsigned portLONG ulState; + + ulState = GPIO0_IOPIN; + if( ulState & mainYELLOW_LED ) + { + GPIO_IOCLR = mainYELLOW_LED; + } + else + { + GPIO_IOSET = mainYELLOW_LED; + } +} +/*-----------------------------------------------------------*/ + +static portLONG prvCheckOtherTasksAreStillRunning( void ) +{ +portLONG lReturn = ( portLONG ) pdPASS; + + /* Check all the demo tasks (other than the flash tasks) to ensure + that they are all still running, and that none of them have detected + an error. */ + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + lReturn = ( portLONG ) pdFAIL; + } + + return lReturn; +} + + + diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/rtosdemo.hzp b/20080212/Demo/uIP_Demo_Rowley_ARM7/rtosdemo.hzp new file mode 100644 index 000000000..e5d235ed2 --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/rtosdemo.hzp @@ -0,0 +1,56 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/rtosdemo.hzs b/20080212/Demo/uIP_Demo_Rowley_ARM7/rtosdemo.hzs new file mode 100644 index 000000000..61e9d913b --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/rtosdemo.hzs @@ -0,0 +1,76 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/Makefile b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/Makefile new file mode 100644 index 000000000..61d3a06aa --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/Makefile @@ -0,0 +1,74 @@ +# Copyright (c) 2001, Adam Dunkels. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# 3. All advertising materials mentioning features or use of this software +# must display the following acknowledgement: +# This product includes software developed by Adam Dunkels. +# 4. The name of the author may not be used to endorse or promote +# products derived from this software without specific prior +# written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS +# OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +# GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# This file is part of the uIP TCP/IP stack. +# +# $Id: Makefile,v 1.8.2.2 2003/10/04 22:54:17 adam Exp $ +# + +CC=gcc +CFLAGS=-Wall -g -I../uip -I. -I../apps/httpd -I../apps/resolv -I../apps/webclient -I../apps/smtp -I../apps/telnet -fpack-struct + +%.o: + $(CC) $(CFLAGS) -c $(<:.o=.c) + + +uip: uip.o uip_arch.o tapdev.o httpd.o main.o fs.o uip_arp.o cgi.o + +tapdev.o: tapdev.c uipopt.h +main.o: main.c ../uip/uip.h uipopt.h ../apps/httpd/httpd.h \ + tapdev.h +uip_arch.o: uip_arch.c ../uip/uip_arch.h ../uip/uip.h uipopt.h \ + ../apps/httpd/httpd.h +uip.o: ../uip/uip.c ../uip/uip.h uipopt.h ../apps/httpd/httpd.h + +uip_arp.o: ../uip/uip_arp.c ../uip/uip_arp.h ../uip/uip.h uipopt.h \ + ../apps/httpd/httpd.h + $(CC) -o uip_arp.o $(CFLAGS) -fpack-struct -c ../uip/uip_arp.c + + +cgi.o: ../apps/httpd/cgi.c ../uip/uip.h uipopt.h ../apps/smtp/smtp.h \ + ../apps/httpd/cgi.h ../apps/httpd/httpd.h ../apps/httpd/fs.h +fs.o: ../apps/httpd/fs.c ../uip/uip.h uipopt.h ../apps/smtp/smtp.h \ + ../apps/httpd/httpd.h ../apps/httpd/fs.h ../apps/httpd/fsdata.h \ + ../apps/httpd/fsdata.c +fsdata.o: ../apps/httpd/fsdata.c +httpd.o: ../apps/httpd/httpd.c ../uip/uip.h uipopt.h \ + ../apps/smtp/smtp.h ../apps/httpd/httpd.h ../apps/httpd/fs.h \ + ../apps/httpd/fsdata.h ../apps/httpd/cgi.h + +clean: + rm -f *.o *~ *core uip + + + + + + diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/cgi.c b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/cgi.c new file mode 100644 index 000000000..06574a156 --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/cgi.c @@ -0,0 +1,211 @@ +/** + * \addtogroup httpd + * @{ + */ + +/** + * \file + * HTTP server script language C functions file. + * \author Adam Dunkels + * + * This file contains functions that are called by the web server + * scripts. The functions takes one argument, and the return value is + * interpreted as follows. A zero means that the function did not + * complete and should be invoked for the next packet as well. A + * non-zero value indicates that the function has completed and that + * the web server should move along to the next script line. + * + */ + +/* + * Copyright (c) 2001, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: cgi.c,v 1.23.2.4 2003/10/07 13:22:27 adam Exp $ + * + */ + +#include "uip.h" +#include "cgi.h" +#include "httpd.h" +#include "fs.h" + +#include +#include + +static u8_t print_stats(u8_t next); +static u8_t file_stats(u8_t next); +static u8_t tcp_stats(u8_t next); + +cgifunction cgitab[] = { + print_stats, /* CGI function "a" */ + file_stats, /* CGI function "b" */ + tcp_stats /* CGI function "c" */ +}; + +static const char closed[] = /* "CLOSED",*/ +{0x43, 0x4c, 0x4f, 0x53, 0x45, 0x44, 0}; +static const char syn_rcvd[] = /* "SYN-RCVD",*/ +{0x53, 0x59, 0x4e, 0x2d, 0x52, 0x43, 0x56, + 0x44, 0}; +static const char syn_sent[] = /* "SYN-SENT",*/ +{0x53, 0x59, 0x4e, 0x2d, 0x53, 0x45, 0x4e, + 0x54, 0}; +static const char established[] = /* "ESTABLISHED",*/ +{0x45, 0x53, 0x54, 0x41, 0x42, 0x4c, 0x49, 0x53, 0x48, + 0x45, 0x44, 0}; +static const char fin_wait_1[] = /* "FIN-WAIT-1",*/ +{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49, + 0x54, 0x2d, 0x31, 0}; +static const char fin_wait_2[] = /* "FIN-WAIT-2",*/ +{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49, + 0x54, 0x2d, 0x32, 0}; +static const char closing[] = /* "CLOSING",*/ +{0x43, 0x4c, 0x4f, 0x53, 0x49, + 0x4e, 0x47, 0}; +static const char time_wait[] = /* "TIME-WAIT,"*/ +{0x54, 0x49, 0x4d, 0x45, 0x2d, 0x57, 0x41, + 0x49, 0x54, 0}; +static const char last_ack[] = /* "LAST-ACK"*/ +{0x4c, 0x41, 0x53, 0x54, 0x2d, 0x41, 0x43, + 0x4b, 0}; + +static const char *states[] = { + closed, + syn_rcvd, + syn_sent, + established, + fin_wait_1, + fin_wait_2, + closing, + time_wait, + last_ack}; + + +/*-----------------------------------------------------------------------------------*/ +/* print_stats: + * + * Prints out a part of the uIP statistics. The statistics data is + * written into the uip_appdata buffer. It overwrites any incoming + * packet. + */ +static u8_t +print_stats(u8_t next) +{ +#if UIP_STATISTICS + u16_t i, j; + u8_t *buf; + u16_t *databytes; + + if(next) { + /* If our last data has been acknowledged, we move on the next + chunk of statistics. */ + hs->count = hs->count + 4; + if(hs->count >= sizeof(struct uip_stats)/sizeof(u16_t)) { + /* We have printed out all statistics, so we return 1 to + indicate that we are done. */ + return 1; + } + } + + /* Write part of the statistics into the uip_appdata buffer. */ + databytes = (u16_t *)&uip_stat + hs->count; + buf = (u8_t *)uip_appdata; + + j = 4 + 1; + i = hs->count; + while (i < sizeof(struct uip_stats)/sizeof(u16_t) && --j > 0) { + sprintf((char *)buf, "%5u\r\n", *databytes); + ++databytes; + buf += 6; + ++i; + } + + /* Send the data. */ + uip_send(uip_appdata, buf - uip_appdata); + + return 0; +#else + return 1; +#endif /* UIP_STATISTICS */ +} +/*-----------------------------------------------------------------------------------*/ +static u8_t +file_stats(u8_t next) +{ + /* We use sprintf() to print the number of file accesses to a + particular file (given as an argument to the function in the + script). We then use uip_send() to actually send the data. */ + if(next) { + return 1; + } + uip_send(uip_appdata, sprintf((char *)uip_appdata, "%5u", fs_count(&hs->script[4]))); + return 0; +} +/*-----------------------------------------------------------------------------------*/ +static u8_t +tcp_stats(u8_t next) +{ + struct uip_conn *conn; + + if(next) { + /* If the previously sent data has been acknowledged, we move + forward one connection. */ + if(++hs->count == UIP_CONNS) { + /* If all connections has been printed out, we are done and + return 1. */ + return 1; + } + } + + conn = &uip_conns[hs->count]; + if((conn->tcpstateflags & TS_MASK) == CLOSED) { + uip_send(uip_appdata, sprintf((char *)uip_appdata, + "--%u%u%c %c\r\n", + conn->nrtx, + conn->timer, + (uip_outstanding(conn))? '*':' ', + (uip_stopped(conn))? '!':' ')); + } else { + uip_send(uip_appdata, sprintf((char *)uip_appdata, + "%u.%u.%u.%u:%u%s%u%u%c %c\r\n", + htons(conn->ripaddr[0]) >> 8, + htons(conn->ripaddr[0]) & 0xff, + htons(conn->ripaddr[1]) >> 8, + htons(conn->ripaddr[1]) & 0xff, + htons(conn->rport), + states[conn->tcpstateflags & TS_MASK], + conn->nrtx, + conn->timer, + (uip_outstanding(conn))? '*':' ', + (uip_stopped(conn))? '!':' ')); + } + return 0; +} +/*-----------------------------------------------------------------------------------*/ diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/cgi.h b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/cgi.h new file mode 100644 index 000000000..d85389b52 --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/cgi.h @@ -0,0 +1,57 @@ +/** + * \addtogroup httpd + * @{ + */ + +/** + * \file + * HTTP script language header file. + * \author Adam Dunkels + */ + +/* + * Copyright (c) 2001, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: cgi.h,v 1.3.2.4 2003/10/07 13:22:27 adam Exp $ + * + */ + +#ifndef __CGI_H__ +#define __CGI_H__ + +typedef u8_t (* cgifunction)(u8_t next); + +/** + * A table containing pointers to C functions that can be called from + * a web server script. + */ +extern cgifunction cgitab[]; + +#endif /* __CGI_H__ */ diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/crt0.asm b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/crt0.asm new file mode 100644 index 000000000..ef91f42a8 --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/crt0.asm @@ -0,0 +1,66 @@ +// Rowley C Compiler, runtime support. +// +// Copyright (c) 2001, 2002, 2003 Rowley Associates Limited. +// +// This file may be distributed under the terms of the License Agreement +// provided with this software. +// +// THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE +// WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. + +; Create sections + .data + .bss + +; Go to code section. + .code + +; Executed upon reset +__reset proc + +; Turn off watchdog. You can enable it in main() if required. + mov.w #0x5a80, &0x120 + +; Set up stack. + mov.w #RAM_Start_Address+RAM_Size, sp + +; Copy from initialised data section to data section. + mov.w #SFB(IDATA0), r15 + mov.w #data_init_begin, r14 + mov.w #data_init_end-data_init_begin, r13 + call #_memcpy + +; Zero the bss. Ensure the stack is not allocated in the bss! + mov.w #SFB(UDATA0), r15 + mov.w #0, r14 + mov.w #SFE(UDATA0)-SFB(UDATA0), r13 + call #_memset + +; Call user entry point void main(void). + call #_main + +; If main() returns, kick off again. + jmp __reset + endproc + +; Heap data structures; removed by the linker if the heap isn't used. + .break + .data + align WORD +___heap_start__:: + DW 0 + DW heap_size + DS heap_size-4 + +; Reset vector + .vectors + .keep + org 0x1e + dw __reset + +; Initialise the IDATA0 section by duplicating the contents into the +; CONST section and copying them on startup. + .const +data_init_begin: + .init "IDATA0" +data_init_end: diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/cs8900a.c b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/cs8900a.c new file mode 100644 index 000000000..331463a78 --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/cs8900a.c @@ -0,0 +1,546 @@ +// cs8900a.c: device driver for the CS8900a chip in 8-bit mode. + +#include + +#include "cs8900a.h" +#include "uip.h" +#include "uip_arp.h" + +#define IOR (1<<12) // CS8900's ISA-bus interface pins +#define IOW (1<<13) + +// definitions for Crystal CS8900 ethernet-controller +// based on linux-header by Russel Nelson + +#define PP_ChipID 0x0000 // offset 0h -> Corp-ID + + // offset 2h -> Model/Product Number +#define LED_RED (1<<8) +#define LED_GREEN (1<<10) +#define LED_YELLOW (1<<11) + +#define PP_ISAIOB 0x0020 // IO base address +#define PP_CS8900_ISAINT 0x0022 // ISA interrupt select +#define PP_CS8900_ISADMA 0x0024 // ISA Rec DMA channel +#define PP_ISASOF 0x0026 // ISA DMA offset +#define PP_DmaFrameCnt 0x0028 // ISA DMA Frame count +#define PP_DmaByteCnt 0x002A // ISA DMA Byte count +#define PP_CS8900_ISAMemB 0x002C // Memory base +#define PP_ISABootBase 0x0030 // Boot Prom base +#define PP_ISABootMask 0x0034 // Boot Prom Mask + +// EEPROM data and command registers +#define PP_EECMD 0x0040 // NVR Interface Command register +#define PP_EEData 0x0042 // NVR Interface Data Register + +// Configuration and control registers +#define PP_RxCFG 0x0102 // Rx Bus config +#define PP_RxCTL 0x0104 // Receive Control Register +#define PP_TxCFG 0x0106 // Transmit Config Register +#define PP_TxCMD 0x0108 // Transmit Command Register +#define PP_BufCFG 0x010A // Bus configuration Register +#define PP_LineCTL 0x0112 // Line Config Register +#define PP_SelfCTL 0x0114 // Self Command Register +#define PP_BusCTL 0x0116 // ISA bus control Register +#define PP_TestCTL 0x0118 // Test Register + +// Status and Event Registers +#define PP_ISQ 0x0120 // Interrupt Status +#define PP_RxEvent 0x0124 // Rx Event Register +#define PP_TxEvent 0x0128 // Tx Event Register +#define PP_BufEvent 0x012C // Bus Event Register +#define PP_RxMiss 0x0130 // Receive Miss Count +#define PP_TxCol 0x0132 // Transmit Collision Count +#define PP_LineST 0x0134 // Line State Register +#define PP_SelfST 0x0136 // Self State register +#define PP_BusST 0x0138 // Bus Status +#define PP_TDR 0x013C // Time Domain Reflectometry + +// Initiate Transmit Registers +#define PP_TxCommand 0x0144 // Tx Command +#define PP_TxLength 0x0146 // Tx Length + +// Adress Filter Registers +#define PP_LAF 0x0150 // Hash Table +#define PP_IA 0x0158 // Physical Address Register + +// Frame Location +#define PP_RxStatus 0x0400 // Receive start of frame +#define PP_RxLength 0x0402 // Receive Length of frame +#define PP_RxFrame 0x0404 // Receive frame pointer +#define PP_TxFrame 0x0A00 // Transmit frame pointer + +// Primary I/O Base Address. If no I/O base is supplied by the user, then this +// can be used as the default I/O base to access the PacketPage Area. +#define DEFAULTIOBASE 0x0300 + +// PP_RxCFG - Receive Configuration and Interrupt Mask bit definition - Read/write +#define SKIP_1 0x0040 +#define RX_STREAM_ENBL 0x0080 +#define RX_OK_ENBL 0x0100 +#define RX_DMA_ONLY 0x0200 +#define AUTO_RX_DMA 0x0400 +#define BUFFER_CRC 0x0800 +#define RX_CRC_ERROR_ENBL 0x1000 +#define RX_RUNT_ENBL 0x2000 +#define RX_EXTRA_DATA_ENBL 0x4000 + +// PP_RxCTL - Receive Control bit definition - Read/write +#define RX_IA_HASH_ACCEPT 0x0040 +#define RX_PROM_ACCEPT 0x0080 +#define RX_OK_ACCEPT 0x0100 +#define RX_MULTCAST_ACCEPT 0x0200 +#define RX_IA_ACCEPT 0x0400 +#define RX_BROADCAST_ACCEPT 0x0800 +#define RX_BAD_CRC_ACCEPT 0x1000 +#define RX_RUNT_ACCEPT 0x2000 +#define RX_EXTRA_DATA_ACCEPT 0x4000 + +// PP_TxCFG - Transmit Configuration Interrupt Mask bit definition - Read/write +#define TX_LOST_CRS_ENBL 0x0040 +#define TX_SQE_ERROR_ENBL 0x0080 +#define TX_OK_ENBL 0x0100 +#define TX_LATE_COL_ENBL 0x0200 +#define TX_JBR_ENBL 0x0400 +#define TX_ANY_COL_ENBL 0x0800 +#define TX_16_COL_ENBL 0x8000 + +// PP_TxCMD - Transmit Command bit definition - Read-only and +// PP_TxCommand - Write-only +#define TX_START_5_BYTES 0x0000 +#define TX_START_381_BYTES 0x0040 +#define TX_START_1021_BYTES 0x0080 +#define TX_START_ALL_BYTES 0x00C0 +#define TX_FORCE 0x0100 +#define TX_ONE_COL 0x0200 +#define TX_NO_CRC 0x1000 +#define TX_RUNT 0x2000 + +// PP_BufCFG - Buffer Configuration Interrupt Mask bit definition - Read/write +#define GENERATE_SW_INTERRUPT 0x0040 +#define RX_DMA_ENBL 0x0080 +#define READY_FOR_TX_ENBL 0x0100 +#define TX_UNDERRUN_ENBL 0x0200 +#define RX_MISS_ENBL 0x0400 +#define RX_128_BYTE_ENBL 0x0800 +#define TX_COL_COUNT_OVRFLOW_ENBL 0x1000 +#define RX_MISS_COUNT_OVRFLOW_ENBL 0x2000 +#define RX_DEST_MATCH_ENBL 0x8000 + +// PP_LineCTL - Line Control bit definition - Read/write +#define SERIAL_RX_ON 0x0040 +#define SERIAL_TX_ON 0x0080 +#define AUI_ONLY 0x0100 +#define AUTO_AUI_10BASET 0x0200 +#define MODIFIED_BACKOFF 0x0800 +#define NO_AUTO_POLARITY 0x1000 +#define TWO_PART_DEFDIS 0x2000 +#define LOW_RX_SQUELCH 0x4000 + +// PP_SelfCTL - Software Self Control bit definition - Read/write +#define POWER_ON_RESET 0x0040 +#define SW_STOP 0x0100 +#define SLEEP_ON 0x0200 +#define AUTO_WAKEUP 0x0400 +#define HCB0_ENBL 0x1000 +#define HCB1_ENBL 0x2000 +#define HCB0 0x4000 +#define HCB1 0x8000 + +// PP_BusCTL - ISA Bus Control bit definition - Read/write +#define RESET_RX_DMA 0x0040 +#define MEMORY_ON 0x0400 +#define DMA_BURST_MODE 0x0800 +#define IO_CHANNEL_READY_ON 0x1000 +#define RX_DMA_SIZE_64K 0x2000 +#define ENABLE_IRQ 0x8000 + +// PP_TestCTL - Test Control bit definition - Read/write +#define LINK_OFF 0x0080 +#define ENDEC_LOOPBACK 0x0200 +#define AUI_LOOPBACK 0x0400 +#define BACKOFF_OFF 0x0800 +#define FDX_8900 0x4000 + +// PP_RxEvent - Receive Event Bit definition - Read-only +#define RX_IA_HASHED 0x0040 +#define RX_DRIBBLE 0x0080 +#define RX_OK 0x0100 +#define RX_HASHED 0x0200 +#define RX_IA 0x0400 +#define RX_BROADCAST 0x0800 +#define RX_CRC_ERROR 0x1000 +#define RX_RUNT 0x2000 +#define RX_EXTRA_DATA 0x4000 +#define HASH_INDEX_MASK 0xFC00 // Hash-Table Index Mask (6 Bit) + +// PP_TxEvent - Transmit Event Bit definition - Read-only +#define TX_LOST_CRS 0x0040 +#define TX_SQE_ERROR 0x0080 +#define TX_OK 0x0100 +#define TX_LATE_COL 0x0200 +#define TX_JBR 0x0400 +#define TX_16_COL 0x8000 +#define TX_COL_COUNT_MASK 0x7800 + +// PP_BufEvent - Buffer Event Bit definition - Read-only +#define SW_INTERRUPT 0x0040 +#define RX_DMA 0x0080 +#define READY_FOR_TX 0x0100 +#define TX_UNDERRUN 0x0200 +#define RX_MISS 0x0400 +#define RX_128_BYTE 0x0800 +#define TX_COL_OVRFLW 0x1000 +#define RX_MISS_OVRFLW 0x2000 +#define RX_DEST_MATCH 0x8000 + +// PP_LineST - Ethernet Line Status bit definition - Read-only +#define LINK_OK 0x0080 +#define AUI_ON 0x0100 +#define TENBASET_ON 0x0200 +#define POLARITY_OK 0x1000 +#define CRS_OK 0x4000 + +// PP_SelfST - Chip Software Status bit definition +#define ACTIVE_33V 0x0040 +#define INIT_DONE 0x0080 +#define SI_BUSY 0x0100 +#define EEPROM_PRESENT 0x0200 +#define EEPROM_OK 0x0400 +#define EL_PRESENT 0x0800 +#define EE_SIZE_64 0x1000 + +// PP_BusST - ISA Bus Status bit definition +#define TX_BID_ERROR 0x0080 +#define READY_FOR_TX_NOW 0x0100 + +// The following block defines the ISQ event types +#define ISQ_RX_EVENT 0x0004 +#define ISQ_TX_EVENT 0x0008 +#define ISQ_BUFFER_EVENT 0x000C +#define ISQ_RX_MISS_EVENT 0x0010 +#define ISQ_TX_COL_EVENT 0x0012 + +#define ISQ_EVENT_MASK 0x003F // ISQ mask to find out type of event + +// Ports for I/O-Mode +#define RX_FRAME_PORT 0x0000 +#define TX_FRAME_PORT 0x0000 +#define TX_CMD_PORT 0x0004 +#define TX_LEN_PORT 0x0006 +#define ISQ_PORT 0x0008 +#define ADD_PORT 0x000A +#define DATA_PORT 0x000C + +#define AUTOINCREMENT 0x8000 // Bit mask to set Bit-15 for autoincrement + +// EEProm Commands +#define EEPROM_WRITE_EN 0x00F0 +#define EEPROM_WRITE_DIS 0x0000 +#define EEPROM_WRITE_CMD 0x0100 +#define EEPROM_READ_CMD 0x0200 + +// Receive Header of each packet in receive area of memory for DMA-Mode +#define RBUF_EVENT_LOW 0x0000 // Low byte of RxEvent +#define RBUF_EVENT_HIGH 0x0001 // High byte of RxEvent +#define RBUF_LEN_LOW 0x0002 // Length of received data - low byte +#define RBUF_LEN_HI 0x0003 // Length of received data - high byte +#define RBUF_HEAD_LEN 0x0004 // Length of this header + +// typedefs +typedef struct { // struct to store CS8900's + unsigned int Addr; // init-sequence + unsigned int Data; +} TInitSeq; + +unsigned short ticks; + +static void skip_frame(void); + +const TInitSeq InitSeq[] = +{ + PP_IA, UIP_ETHADDR0 + (UIP_ETHADDR1 << 8), // set our MAC as Individual Address + PP_IA + 2, UIP_ETHADDR2 + (UIP_ETHADDR3 << 8), + PP_IA + 4, UIP_ETHADDR4 + (UIP_ETHADDR5 << 8), + PP_LineCTL, SERIAL_RX_ON | SERIAL_TX_ON, // configure the Physical Interface + PP_RxCTL, RX_OK_ACCEPT | RX_IA_ACCEPT | RX_BROADCAST_ACCEPT +}; + +// Writes a word in little-endian byte order to a specified port-address +void +cs8900a_write(unsigned addr, unsigned int data) +{ + GPIO_IODIR |= 0xff << 16; // Data port to output + + GPIO_IOCLR = 0xf << 4; // Put address on bus + GPIO_IOSET = addr << 4; + + GPIO_IOCLR = 0xff << 16; // Write low order byte to data bus + GPIO_IOSET = data << 16; + + asm volatile ( "NOP" ); + GPIO_IOCLR = IOW; // Toggle IOW-signal + asm volatile ( "NOP" ); + GPIO_IOSET = IOW; + asm volatile ( "NOP" ); + + GPIO_IOCLR = 0xf << 4; + GPIO_IOSET = ((addr | 1) << 4); // And put next address on bus + + GPIO_IOCLR = 0xff << 16; // Write high order byte to data bus + GPIO_IOSET = data >> 8 << 16; + + asm volatile ( "NOP" ); + GPIO_IOCLR = IOW; // Toggle IOW-signal + asm volatile ( "NOP" ); + GPIO_IOSET = IOW; + asm volatile ( "NOP" ); +} + +// Reads a word in little-endian byte order from a specified port-address +unsigned +cs8900a_read(unsigned addr) +{ + unsigned int value; + + GPIO_IODIR &= ~(0xff << 16); // Data port to input + + GPIO_IOCLR = 0xf << 4; // Put address on bus + GPIO_IOSET = addr << 4; + + asm volatile ( "NOP" ); + GPIO_IOCLR = IOR; // IOR-signal low + asm volatile ( "NOP" ); + value = (GPIO_IOPIN >> 16) & 0xff; // get low order byte from data bus + GPIO_IOSET = IOR; + + GPIO_IOSET = 1 << 4; // IOR high and put next address on bus + + asm volatile ( "NOP" ); + GPIO_IOCLR = IOR; // IOR-signal low + asm volatile ( "NOP" ); + value |= ((GPIO_IOPIN >> 8) & 0xff00); // get high order byte from data bus + GPIO_IOSET = IOR; // IOR-signal low + + return value; +} + +// Reads a word in little-endian byte order from a specified port-address +unsigned +cs8900a_read_addr_high_first(unsigned addr) +{ + unsigned int value; + + GPIO_IODIR &= ~(0xff << 16); // Data port to input + + GPIO_IOCLR = 0xf << 4; // Put address on bus + GPIO_IOSET = (addr+1) << 4; + + asm volatile ( "NOP" ); + GPIO_IOCLR = IOR; // IOR-signal low + asm volatile ( "NOP" ); + value = ((GPIO_IOPIN >> 8) & 0xff00); // get high order byte from data bus + GPIO_IOSET = IOR; // IOR-signal high + + GPIO_IOCLR = 1 << 4; // Put low address on bus + + asm volatile ( "NOP" ); + GPIO_IOCLR = IOR; // IOR-signal low + asm volatile ( "NOP" ); + value |= (GPIO_IOPIN >> 16) & 0xff; // get low order byte from data bus + GPIO_IOSET = IOR; + + return value; +} + +void +cs8900a_init(void) +{ + int i; + + // Reset outputs, control lines high + GPIO_IOSET = IOR | IOW; + + // No LEDs on. + GPIO_IOSET = LED_RED | LED_YELLOW | LED_GREEN; + + // Port 3 as output (all pins but RS232) + GPIO_IODIR = ~0U; // everything to output. + + // Reset outputs + GPIO_IOCLR = 0xff << 16; // clear data outputs + + // Reset the CS8900A + cs8900a_write(ADD_PORT, PP_SelfCTL); + cs8900a_write(DATA_PORT, POWER_ON_RESET); + + // Wait until chip-reset is done + cs8900a_write(ADD_PORT, PP_SelfST); + while ((cs8900a_read(DATA_PORT) & INIT_DONE) == 0) + ; + + // Configure the CS8900A + for (i = 0; i < sizeof InitSeq / sizeof (TInitSeq); ++i) + { + cs8900a_write(ADD_PORT, InitSeq[i].Addr); + cs8900a_write(DATA_PORT, InitSeq[i].Data); + } +} + +void +cs8900a_send(void) +{ + unsigned u; + + GPIO_IOCLR = LED_RED; // Light RED LED when frame starting + + // Transmit command + cs8900a_write(TX_CMD_PORT, TX_START_ALL_BYTES); + cs8900a_write(TX_LEN_PORT, uip_len); + + // Maximum number of retries + u = 8; + for (;;) + { + // Check for avaliable buffer space + cs8900a_write(ADD_PORT, PP_BusST); + if (cs8900a_read(DATA_PORT) & READY_FOR_TX_NOW) + break; + if (u -- == 0) + { + GPIO_IOSET = LED_RED; // Extinguish RED LED on end of frame + return; + } + + // No space avaliable, skip a received frame and try again + skip_frame(); + } + + GPIO_IODIR |= 0xff << 16; // Data port to output + + // Send 40+14=54 bytes of header + for (u = 0; u < 54; u += 2) + { + GPIO_IOCLR = 0xf << 4; // Put address on bus + GPIO_IOSET = TX_FRAME_PORT << 4; + + GPIO_IOCLR = 0xff << 16; // Write low order byte to data bus + GPIO_IOSET = uip_buf[u] << 16; // write low order byte to data bus + + asm volatile ( "NOP" ); + GPIO_IOCLR = IOW; // Toggle IOW-signal + asm volatile ( "NOP" ); + GPIO_IOSET = IOW; + + GPIO_IOCLR = 0xf << 4; // Put address on bus + GPIO_IOSET = (TX_FRAME_PORT | 1) << 4; // and put next address on bus + + GPIO_IOCLR = 0xff << 16; // Write low order byte to data bus + GPIO_IOSET = uip_buf[u+1] << 16; // write low order byte to data bus + + asm volatile ( "NOP" ); + GPIO_IOCLR = IOW; // Toggle IOW-signal + asm volatile ( "NOP" ); + GPIO_IOSET = IOW; + } + + if (uip_len <= 54) + { + GPIO_IOSET = LED_RED; // Extinguish RED LED on end of frame + return; + } + + // Send remainder of packet, the application data + uip_len -= 54; + for (u = 0; u < uip_len; u += 2) + { + + GPIO_IOCLR = 0xf << 4; // Put address on bus + GPIO_IOSET = TX_FRAME_PORT << 4; + + GPIO_IOCLR = 0xff << 16; // Write low order byte to data bus + GPIO_IOSET = uip_appdata[u] << 16; // write low order byte to data bus + + asm volatile ( "NOP" ); + GPIO_IOCLR = IOW; // Toggle IOW-signal + asm volatile ( "NOP" ); + GPIO_IOSET = IOW; + + GPIO_IOCLR = 0xf << 4; // Put address on bus + GPIO_IOSET = (TX_FRAME_PORT | 1) << 4; // and put next address on bus + + GPIO_IOCLR = 0xff << 16; // Write low order byte to data bus + GPIO_IOSET = uip_appdata[u+1] << 16; // write low order byte to data bus + + asm volatile ( "NOP" ); + GPIO_IOCLR = IOW; // Toggle IOW-signal + asm volatile ( "NOP" ); + GPIO_IOSET = IOW; + } + + GPIO_IOSET = LED_RED; // Extinguish RED LED on end of frame +} + +static void +skip_frame(void) +{ + // No space avaliable, skip a received frame and try again + cs8900a_write(ADD_PORT, PP_RxCFG); + cs8900a_write(DATA_PORT, cs8900a_read(DATA_PORT) | SKIP_1); +} + +u8_t +cs8900a_poll(void) +{ + u16_t len, u; + + // Check receiver event register to see if there are any valid frames avaliable + cs8900a_write(ADD_PORT, PP_RxEvent); + if ((cs8900a_read(DATA_PORT) & 0xd00) == 0) + return 0; + + GPIO_IOCLR = LED_GREEN; // Light GREED LED when frame coming in. + + // Read receiver status and discard it. + cs8900a_read_addr_high_first(RX_FRAME_PORT); + + // Read frame length + len = cs8900a_read_addr_high_first(RX_FRAME_PORT); + + // If the frame is too big to handle, throw it away + if (len > UIP_BUFSIZE) + { + skip_frame(); + return 0; + } + + // Data port to input + GPIO_IODIR &= ~(0xff << 16); + + GPIO_IOCLR = 0xf << 4; // put address on bus + GPIO_IOSET = RX_FRAME_PORT << 4; + + // Read bytes into uip_buf + u = 0; + while (u < len) + { + GPIO_IOCLR = 1 << 4; // put address on bus + + GPIO_IOCLR = IOR; // IOR-signal low + uip_buf[u] = GPIO_IOPIN >> 16; // get high order byte from data bus + asm volatile ( "NOP" ); + GPIO_IOSET = IOR; // IOR-signal high + + GPIO_IOSET = 1 << 4; // put address on bus + + GPIO_IOCLR = IOR; // IOR-signal low + asm volatile ( "NOP" ); + uip_buf[u+1] = GPIO_IOPIN >> 16; // get high order byte from data bus + GPIO_IOSET = IOR; // IOR-signal high + u += 2; + } + + GPIO_IOSET = LED_GREEN; // Extinguish GREED LED when frame finished. + return len; +} + diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/cs8900a.h b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/cs8900a.h new file mode 100644 index 000000000..2d4b56fe0 --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/cs8900a.h @@ -0,0 +1,10 @@ +#ifndef __CS8900A_H__ +#define __CS8900A_H__ + +#include "uip_arch.h" + +void cs8900a_init(void); +void cs8900a_send(void); +u8_t cs8900a_poll(void); + +#endif /* __CS8900A_H__ */ diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fs.c b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fs.c new file mode 100644 index 000000000..7e15200b2 --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fs.c @@ -0,0 +1,155 @@ +/** + * \addtogroup httpd + * @{ + */ + +/** + * \file + * HTTP server read-only file system code. + * \author Adam Dunkels + * + * A simple read-only filesystem. + */ + +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: fs.c,v 1.7.2.3 2003/10/07 13:22:27 adam Exp $ + */ + +#include "uip.h" +#include "httpd.h" +#include "fs.h" +#include "fsdata.h" + +#define NULL (void *)0 +#include "fsdata.c" + +#ifdef FS_STATISTICS +#if FS_STATISTICS == 1 +static u16_t count[FS_NUMFILES]; +#endif /* FS_STATISTICS */ +#endif /* FS_STATISTICS */ + +/*-----------------------------------------------------------------------------------*/ +static u8_t +fs_strcmp(const char *str1, const char *str2) +{ + u8_t i; + i = 0; + loop: + + if(str2[i] == 0 || + str1[i] == '\r' || + str1[i] == '\n') { + return 0; + } + + if(str1[i] != str2[i]) { + return 1; + } + + + ++i; + goto loop; +} +/*-----------------------------------------------------------------------------------*/ +int +fs_open(const char *name, struct fs_file *file) +{ +#ifdef FS_STATISTICS +#if FS_STATISTICS == 1 + u16_t i = 0; +#endif /* FS_STATISTICS */ +#endif /* FS_STATISTICS */ + struct fsdata_file_noconst *f; + + for(f = (struct fsdata_file_noconst *)FS_ROOT; + f != NULL; + f = (struct fsdata_file_noconst *)f->next) { + + if(fs_strcmp(name, f->name) == 0) { + file->data = f->data; + file->len = f->len; +#ifdef FS_STATISTICS +#if FS_STATISTICS == 1 + ++count[i]; +#endif /* FS_STATISTICS */ +#endif /* FS_STATISTICS */ + return 1; + } +#ifdef FS_STATISTICS +#if FS_STATISTICS == 1 + ++i; +#endif /* FS_STATISTICS */ +#endif /* FS_STATISTICS */ + + } + return 0; +} +/*-----------------------------------------------------------------------------------*/ +void +fs_init(void) +{ +#ifdef FS_STATISTICS +#if FS_STATISTICS == 1 + u16_t i; + for(i = 0; i < FS_NUMFILES; i++) { + count[i] = 0; + } +#endif /* FS_STATISTICS */ +#endif /* FS_STATISTICS */ +} +/*-----------------------------------------------------------------------------------*/ +#ifdef FS_STATISTICS +#if FS_STATISTICS == 1 +u16_t fs_count +(char *name) +{ + struct fsdata_file_noconst *f; + u16_t i; + + i = 0; + for(f = (struct fsdata_file_noconst *)FS_ROOT; + f != NULL; + f = (struct fsdata_file_noconst *)f->next) { + + if(fs_strcmp(name, f->name) == 0) { + return count[i]; + } + ++i; + } + return 0; +} +#endif /* FS_STATISTICS */ +#endif /* FS_STATISTICS */ +/*-----------------------------------------------------------------------------------*/ diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fs.h b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fs.h new file mode 100644 index 000000000..65551ba41 --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fs.h @@ -0,0 +1,80 @@ +/** + * \addtogroup httpd + * @{ + */ + +/** + * \file + * HTTP server read-only file system header file. + * \author Adam Dunkels + */ + +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: fs.h,v 1.6.2.3 2003/10/07 13:22:27 adam Exp $ + */ +#ifndef __FS_H__ +#define __FS_H__ + +#include "uip.h" + +/** + * An open file in the read-only file system. + */ +struct fs_file { + char *data; /**< The actual file data. */ + int len; /**< The length of the file data. */ +}; + +/** + * Open a file in the read-only file system. + * + * \param name The name of the file. + * + * \param file The file pointer, which must be allocated by caller and + * will be filled in by the function. + */ +int fs_open(const char *name, struct fs_file *file); + +#ifdef FS_STATISTICS +#if FS_STATISTICS == 1 +u16_t fs_count(char *name); +#endif /* FS_STATISTICS */ +#endif /* FS_STATISTICS */ + +/** + * Initialize the read-only file system. + */ +void fs_init(void); + +#endif /* __FS_H__ */ diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fs/404.html b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fs/404.html new file mode 100644 index 000000000..8d6beec83 --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fs/404.html @@ -0,0 +1 @@ +

    404 - file not found

    \ No newline at end of file diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fs/about.html b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fs/about.html new file mode 100644 index 000000000..4c886897b --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fs/about.html @@ -0,0 +1,18 @@ + + +
    +
    +

    Welcome

    +

    +These web pages are served by the small web server running on top of +the uIP TCP/IP +stack. +

    +

    +Click on the links above to see some status information about the web +server and the TCP/IP stack. +

    +
    +
    + + \ No newline at end of file diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fs/cgi/files b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fs/cgi/files new file mode 100644 index 000000000..64e0b5005 --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fs/cgi/files @@ -0,0 +1,28 @@ +# This script shows the access statistics for different files on the +# web server. +# +# First, we include the HTML header. +i /files_header.html +# Print out the name of the file, and call the function that prints +# the access statistics of that file. +t /index.html +c b /index.html +t /about.html +c b /about.html +t /control.html +c b /control.html +t /img/bg.png +c b /img/bg.png +t /404.html +c b /404.html +t /cgi/files +c b /cgi/files +t /cgi/stats +c b /cgi/stats +t /cgi/tcp +c b /cgi/tcp +t +# Include the HTML footer. +i /files_footer.plain +# End of script. +. \ No newline at end of file diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fs/cgi/stats b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fs/cgi/stats new file mode 100644 index 000000000..2c71c90dc --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fs/cgi/stats @@ -0,0 +1,4 @@ +i /stats_header.html +c a +i /stats_footer.plain +. diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fs/cgi/tcp b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fs/cgi/tcp new file mode 100644 index 000000000..14efd3700 --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fs/cgi/tcp @@ -0,0 +1,4 @@ +i /tcp_header.html +c c +i /tcp_footer.plain +. \ No newline at end of file diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fs/control.html b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fs/control.html new file mode 100644 index 000000000..ce28dbe7d --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fs/control.html @@ -0,0 +1,14 @@ + + +
    +
    +

    uIP web server test pages

    +[ About | +Connections | +Files | +Statistics ] +
    +
    + + \ No newline at end of file diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fs/files_footer.plain b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fs/files_footer.plain new file mode 100644 index 000000000..0b6dceb4f --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fs/files_footer.plain @@ -0,0 +1,3 @@ + + + diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fs/files_header.html b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fs/files_header.html new file mode 100644 index 000000000..25d86501e --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fs/files_header.html @@ -0,0 +1,4 @@ + + +
    + diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fs/img/bg.png b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fs/img/bg.png new file mode 100644 index 0000000000000000000000000000000000000000..18533b36947070d5721b7a8f39134a5368d72dff GIT binary patch literal 1084 zcmeAS@N?(olHy`uVBq!ia0y~yV3q~4<2cxWq}$%gGeC+h$=lt9;Xep2*t>i(P=vF< zBeIx*fm;ZK886+f`vVkYFY)wsWxveDDx_qrbfIPzP)N4KHKN2hKQ}iuuY|$5C^fMp zHASI3vm`?yBqLS9-P1SVeTr%x(9Q*(E{-7;x8B}8ST@T+q9IWIIBU+uRH-*FfA4pl zr+jsbccJ86-|1#uY%)y>-``DIVb7ECYoRS?{(AYsGPN^#qVvw}7k^ynvg7Z<$yalu z>kkXRmuuUs8=HIkQ}{HK^54HFl>C2se#_6@zPJ7?Iy33omZuiJD}p*26| ze?g6I)Rdne%Km1WSq9&E?)XPe;^BM8V;^f)+WJ3kmjAO+PW&_r14D)}&`%c`85lbF z7#JK%fE+ku5i?W-g&`ozAj>t4fx(3xDC_<3?N{Y%HNU^HuQ@qGqF?!t?D~|pYPGOO zb>+MAWaXQePUoP-}_I&lT>+gMk z>o#9z@*~UdDhvrmdoE)Qoql=QyZ?UPlvo@Jbmzr`DJ^~SdJ(|11_~Frv*8R-pu!#2 z0CLieT)y(T`(u}%1;*Ht-{Gde??3DJ6-(Xyb9sMk?ziXW9Uo6I*ZeE`ILW$`ae?A{ zP|Seh0T}#1M)I0lHRpgV7xo8{ybM2{b22bAyZ}moEQd3|mSZ@lp>aku(*v>FUl)G+ zt@y>be!JzC-Oe5J_r*-9y!7W)?ftwzCspS?+PVK{>G35$CIT&g(OV9Q1?S7xuhzU~ z0tNKGKEw4}z$pdpDL4Z&5ha*h6l`JzI_)B(vtke<*p&yupG{+sSiI;=)ZKqy9?!j+ zR$tdFvEIgE`|bU|cl+=9|47w;_W$J%|8W0~wRwJj-~WfFQa9Q?i?{tR^qkoT<|0U9 q#bdKWiHYzNQKU2tPu#*E`BfIitaiLHX$dgg7(8A5T-G@yGywp+{Ey54 literal 0 HcmV?d00001 diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fs/index.html b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fs/index.html new file mode 100644 index 000000000..3429ef3af --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fs/index.html @@ -0,0 +1,14 @@ + +uIP web server test page + + + + + + + +<body> +Your browser must support frames +</body> + + \ No newline at end of file diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fs/stats_footer.plain b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fs/stats_footer.plain new file mode 100644 index 000000000..0b6dceb4f --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fs/stats_footer.plain @@ -0,0 +1,3 @@ +
    + + diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fs/stats_header.html b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fs/stats_header.html new file mode 100644 index 000000000..4efaddf5b --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fs/stats_header.html @@ -0,0 +1,30 @@ + + +
    + +
    +
    +IP           Packets dropped
+             Packets received
+             Packets sent
+IP errors    IP version/header length
+             IP length, high byte
+             IP length, low byte
+             IP fragments
+             Header checksum
+             Wrong protocol
+ICMP	     Packets dropped
+             Packets received
+             Packets sent
+             Type errors
+TCP          Packets dropped
+             Packets received
+             Packets sent
+             Checksum errors
+             Data packets without ACKs
+             Resets
+             Retransmissions
+	     No connection avaliable
+	     Connection attempts to closed ports
+
    +
    \ No newline at end of file
diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fs/tcp_footer.plain b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fs/tcp_footer.plain
new file mode 100644
index 000000000..442c17a58
--- /dev/null
+++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fs/tcp_footer.plain
@@ -0,0 +1,5 @@
+
+
    +
    + + \ No newline at end of file diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fs/tcp_header.html b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fs/tcp_header.html new file mode 100644 index 000000000..1a5057167 --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fs/tcp_header.html @@ -0,0 +1,6 @@ + + +
    + + + diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fsdata.c b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fsdata.c new file mode 100644 index 000000000..ff855e7dc --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fsdata.c @@ -0,0 +1,619 @@ +static const char data_cgi_files[] = { + /* /cgi/files */ + 0x2f, 0x63, 0x67, 0x69, 0x2f, 0x66, 0x69, 0x6c, 0x65, 0x73, 0, + 0x23, 0x20, 0x54, 0x68, 0x69, 0x73, 0x20, 0x73, 0x63, 0x72, + 0x69, 0x70, 0x74, 0x20, 0x73, 0x68, 0x6f, 0x77, 0x73, 0x20, + 0x74, 0x68, 0x65, 0x20, 0x61, 0x63, 0x63, 0x65, 0x73, 0x73, + 0x20, 0x73, 0x74, 0x61, 0x74, 0x69, 0x73, 0x74, 0x69, 0x63, + 0x73, 0x20, 0x66, 0x6f, 0x72, 0x20, 0x64, 0x69, 0x66, 0x66, + 0x65, 0x72, 0x65, 0x6e, 0x74, 0x20, 0x66, 0x69, 0x6c, 0x65, + 0x73, 0x20, 0x6f, 0x6e, 0x20, 0x74, 0x68, 0x65, 0xa, 0x23, + 0x20, 0x77, 0x65, 0x62, 0x20, 0x73, 0x65, 0x72, 0x76, 0x65, + 0x72, 0x2e, 0xa, 0x23, 0xa, 0x23, 0x20, 0x46, 0x69, 0x72, + 0x73, 0x74, 0x2c, 0x20, 0x77, 0x65, 0x20, 0x69, 0x6e, 0x63, + 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0x3e, 0x3c, + 0x74, 0x64, 0x3e, 0x3c, 0x70, 0x72, 0x65, 0x3e, }; + +static const char data_tcp_footer_plain[] = { + /* /tcp_footer.plain */ + 0x2f, 0x74, 0x63, 0x70, 0x5f, 0x66, 0x6f, 0x6f, 0x74, 0x65, 0x72, 0x2e, 0x70, 0x6c, 0x61, 0x69, 0x6e, 0, + 0xa, 0x3c, 0x2f, 0x74, 0x64, 0x3e, 0x3c, 0x2f, 0x74, 0x72, + 0x3e, 0x3c, 0x2f, 0x74, 0x61, 0x62, 0x6c, 0x65, 0x3e, 0xa, + 0x3c, 0x2f, 0x63, 0x65, 0x6e, 0x74, 0x65, 0x72, 0x3e, 0xa, + 0x3c, 0x2f, 0x62, 0x6f, 0x64, 0x79, 0x3e, 0xa, 0x3c, 0x2f, + 0x68, 0x74, 0x6d, 0x6c, 0x3e, }; + +static const char data_tcp_header_html[] = { + /* /tcp_header.html */ + 0x2f, 0x74, 0x63, 0x70, 0x5f, 0x68, 0x65, 0x61, 0x64, 0x65, 0x72, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0, + 0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x32, + 0x30, 0x30, 0x20, 0x4f, 0x4b, 0xd, 0xa, 0x53, 0x65, 0x72, + 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x30, + 0x2e, 0x39, 0x20, 0x28, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, + 0x2f, 0x64, 0x75, 0x6e, 0x6b, 0x65, 0x6c, 0x73, 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0x69, 0x6f, 0x6e, 0x73, 0x3c, 0x2f, 0x74, 0x68, 0x3e, 0x3c, + 0x74, 0x68, 0x3e, 0x54, 0x69, 0x6d, 0x65, 0x72, 0x3c, 0x2f, + 0x74, 0x68, 0x3e, 0x3c, 0x74, 0x68, 0x3e, 0x46, 0x6c, 0x61, + 0x67, 0x73, 0x3c, 0x2f, 0x74, 0x68, 0x3e, 0x3c, 0x2f, 0x74, + 0x72, 0x3e, 0xa, 0xa, }; + +const struct fsdata_file file_cgi_files[] = {{NULL, data_cgi_files, data_cgi_files + 11, sizeof(data_cgi_files) - 11}}; + +const struct fsdata_file file_cgi_stats[] = {{file_cgi_files, data_cgi_stats, data_cgi_stats + 11, sizeof(data_cgi_stats) - 11}}; + +const struct fsdata_file file_cgi_tcp[] = {{file_cgi_stats, data_cgi_tcp, data_cgi_tcp + 9, sizeof(data_cgi_tcp) - 9}}; + +const struct fsdata_file file_img_bg_png[] = {{file_cgi_tcp, data_img_bg_png, data_img_bg_png + 12, sizeof(data_img_bg_png) - 12}}; + +const struct fsdata_file file_about_html[] = {{file_img_bg_png, data_about_html, data_about_html + 12, sizeof(data_about_html) - 12}}; + +const struct fsdata_file file_control_html[] = {{file_about_html, data_control_html, data_control_html + 14, sizeof(data_control_html) - 14}}; + +const struct fsdata_file file_404_html[] = {{file_control_html, data_404_html, data_404_html + 10, sizeof(data_404_html) - 10}}; + +const struct fsdata_file file_files_footer_plain[] = {{file_404_html, data_files_footer_plain, data_files_footer_plain + 20, sizeof(data_files_footer_plain) - 20}}; + +const struct fsdata_file file_files_header_html[] = {{file_files_footer_plain, data_files_header_html, data_files_header_html + 19, sizeof(data_files_header_html) - 19}}; + +const struct fsdata_file file_index_html[] = {{file_files_header_html, data_index_html, data_index_html + 12, sizeof(data_index_html) - 12}}; + +const struct fsdata_file file_stats_footer_plain[] = {{file_index_html, data_stats_footer_plain, data_stats_footer_plain + 20, sizeof(data_stats_footer_plain) - 20}}; + +const struct fsdata_file file_stats_header_html[] = {{file_stats_footer_plain, data_stats_header_html, data_stats_header_html + 19, sizeof(data_stats_header_html) - 19}}; + +const struct fsdata_file file_tcp_footer_plain[] = {{file_stats_header_html, data_tcp_footer_plain, data_tcp_footer_plain + 18, sizeof(data_tcp_footer_plain) - 18}}; + +const struct fsdata_file file_tcp_header_html[] = {{file_tcp_footer_plain, data_tcp_header_html, data_tcp_header_html + 17, sizeof(data_tcp_header_html) - 17}}; + +#define FS_ROOT file_tcp_header_html + +#define FS_NUMFILES 14 diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fsdata.h b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fsdata.h new file mode 100644 index 000000000..94086c4df --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/fsdata.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: fsdata.h,v 1.4.2.1 2003/10/04 22:54:06 adam Exp $ + */ +#ifndef __FSDATA_H__ +#define __FSDATA_H__ + +#include "uipopt.h" + +struct fsdata_file { + const struct fsdata_file *next; + const char *name; + const char *data; + const int len; +#ifdef FS_STATISTICS +#if FS_STATISTICS == 1 + u16_t count; +#endif /* FS_STATISTICS */ +#endif /* FS_STATISTICS */ +}; + +struct fsdata_file_noconst { + struct fsdata_file *next; + char *name; + char *data; + int len; +#ifdef FS_STATISTICS +#if FS_STATISTICS == 1 + u16_t count; +#endif /* FS_STATISTICS */ +#endif /* FS_STATISTICS */ +}; + +#endif /* __FSDATA_H__ */ diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/httpd.c b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/httpd.c new file mode 100644 index 000000000..9d2c6e599 --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/httpd.c @@ -0,0 +1,373 @@ +/** + * \addtogroup exampleapps + * @{ + */ + +/** + * \defgroup httpd Web server + * @{ + * + * The uIP web server is a very simplistic implementation of an HTTP + * server. It can serve web pages and files from a read-only ROM + * filesystem, and provides a very small scripting language. + * + * The script language is very simple and works as follows. Each + * script line starts with a command character, either "i", "t", "c", + * "#" or ".". The "i" command tells the script interpreter to + * "include" a file from the virtual file system and output it to the + * web browser. The "t" command should be followed by a line of text + * that is to be output to the browser. The "c" command is used to + * call one of the C functions from the httpd-cgi.c file. A line that + * starts with a "#" is ignored (i.e., the "#" denotes a comment), and + * the "." denotes the last script line. + * + * The script that produces the file statistics page looks somewhat + * like this: + * + \code +i /header.html +t

    File statistics


    RemoteStateRetransmissionsTimerFlags
    +t
    /index.html +c a /index.html +t
    /cgi/files +c a /cgi/files +t
    /cgi/tcp +c a /cgi/tcp +t
    /404.html +c a /404.html +t
    +i /footer.plain +. + \endcode + * + */ + + +/** + * \file + * HTTP server. + * \author Adam Dunkels + */ + +/* + * Copyright (c) 2001, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: httpd.c,v 1.28.2.6 2003/10/07 13:22:27 adam Exp $ + * + */ + + +#include "uip.h" +#include "httpd.h" +#include "fs.h" +#include "fsdata.h" +#include "cgi.h" + +#define NULL (void *)0 + +/* The HTTP server states: */ +#define HTTP_NOGET 0 +#define HTTP_FILE 1 +#define HTTP_TEXT 2 +#define HTTP_FUNC 3 +#define HTTP_END 4 + +#ifdef DEBUG +#include +#define PRINT(x) +#define PRINTLN(x) +#else /* DEBUG */ +#define PRINT(x) +#define PRINTLN(x) +#endif /* DEBUG */ + +struct httpd_state *hs; + +extern const struct fsdata_file file_index_html; +extern const struct fsdata_file file_404_html; + +static void next_scriptline(void); +static void next_scriptstate(void); + +#define ISO_G 0x47 +#define ISO_E 0x45 +#define ISO_T 0x54 +#define ISO_slash 0x2f +#define ISO_c 0x63 +#define ISO_g 0x67 +#define ISO_i 0x69 +#define ISO_space 0x20 +#define ISO_nl 0x0a +#define ISO_cr 0x0d +#define ISO_a 0x61 +#define ISO_t 0x74 +#define ISO_hash 0x23 +#define ISO_period 0x2e + +#define httpPORT 80 + +/*-----------------------------------------------------------------------------------*/ +/** + * Initialize the web server. + * + * Starts to listen for incoming connection requests on TCP port 80. + */ +/*-----------------------------------------------------------------------------------*/ +void +httpd_init(void) +{ + fs_init(); + + /* Listen to port 80. */ + uip_listen(HTONS(httpPORT)); +} +/*-----------------------------------------------------------------------------------*/ +void +httpd_appcall(void) +{ + struct fs_file fsfile; + + u8_t i; + + switch(uip_conn->lport) { + /* This is the web server: */ + case HTONS(httpPORT): + /* Pick out the application state from the uip_conn structure. */ + hs = (struct httpd_state *)(uip_conn->appstate); + + /* We use the uip_ test functions to deduce why we were + called. If uip_connected() is non-zero, we were called + because a remote host has connected to us. If + uip_newdata() is non-zero, we were called because the + remote host has sent us new data, and if uip_acked() is + non-zero, the remote host has acknowledged the data we + previously sent to it. */ + if(uip_connected()) { + /* Since we have just been connected with the remote host, we + reset the state for this connection. The ->count variable + contains the amount of data that is yet to be sent to the + remote host, and the ->state is set to HTTP_NOGET to signal + that we haven't received any HTTP GET request for this + connection yet. */ + + hs->state = HTTP_NOGET; + hs->count = 0; + return; + + } else if(uip_poll()) { + /* If we are polled ten times, we abort the connection. This is + because we don't want connections lingering indefinately in + the system. */ + if(hs->count++ >= 10) { + uip_abort(); + } + return; + } else if(uip_newdata() && hs->state == HTTP_NOGET) { + /* This is the first data we receive, and it should contain a + GET. */ + + /* Check for GET. */ + if(uip_appdata[0] != ISO_G || + uip_appdata[1] != ISO_E || + uip_appdata[2] != ISO_T || + uip_appdata[3] != ISO_space) { + /* If it isn't a GET, we abort the connection. */ + uip_abort(); + return; + } + + /* Find the file we are looking for. */ + for(i = 4; i < 40; ++i) { + if(uip_appdata[i] == ISO_space || + uip_appdata[i] == ISO_cr || + uip_appdata[i] == ISO_nl) { + uip_appdata[i] = 0; + break; + } + } + + PRINT("request for file "); + PRINTLN(&uip_appdata[4]); + + /* Check for a request for "/". */ + if(uip_appdata[4] == ISO_slash && + uip_appdata[5] == 0) { + fs_open(file_index_html.name, &fsfile); + } else { + if(!fs_open((const char *)&uip_appdata[4], &fsfile)) { + PRINTLN("couldn't open file"); + fs_open(file_404_html.name, &fsfile); + } + } + + + if(uip_appdata[4] == ISO_slash && + uip_appdata[5] == ISO_c && + uip_appdata[6] == ISO_g && + uip_appdata[7] == ISO_i && + uip_appdata[8] == ISO_slash) { + /* If the request is for a file that starts with "/cgi/", we + prepare for invoking a script. */ + hs->script = fsfile.data; + next_scriptstate(); + } else { + hs->script = NULL; + /* The web server is now no longer in the HTTP_NOGET state, but + in the HTTP_FILE state since is has now got the GET from + the client and will start transmitting the file. */ + hs->state = HTTP_FILE; + + /* Point the file pointers in the connection state to point to + the first byte of the file. */ + hs->dataptr = fsfile.data; + hs->count = fsfile.len; + } + } + + + if(hs->state != HTTP_FUNC) { + /* Check if the client (remote end) has acknowledged any data that + we've previously sent. If so, we move the file pointer further + into the file and send back more data. If we are out of data to + send, we close the connection. */ + if(uip_acked()) { + if(hs->count >= uip_conn->len) { + hs->count -= uip_conn->len; + hs->dataptr += uip_conn->len; + } else { + hs->count = 0; + } + + if(hs->count == 0) { + if(hs->script != NULL) { + next_scriptline(); + next_scriptstate(); + } else { + uip_close(); + } + } + } + } else { + /* Call the CGI function. */ + if(cgitab[hs->script[2] - ISO_a](uip_acked())) { + /* If the function returns non-zero, we jump to the next line + in the script. */ + next_scriptline(); + next_scriptstate(); + } + } + + if(hs->state != HTTP_FUNC && !uip_poll()) { + /* Send a piece of data, but not more than the MSS of the + connection. */ + uip_send(hs->dataptr, hs->count); + } + + /* Finally, return to uIP. Our outgoing packet will soon be on its + way... */ + return; + + default: + /* Should never happen. */ + uip_abort(); + break; + } +} +/*-----------------------------------------------------------------------------------*/ +/* next_scriptline(): + * + * Reads the script until it finds a newline. */ +static void +next_scriptline(void) +{ + /* Loop until we find a newline character. */ + do { + ++(hs->script); + } while(hs->script[0] != ISO_nl); + + /* Eat up the newline as well. */ + ++(hs->script); +} +/*-----------------------------------------------------------------------------------*/ +/* next_sciptstate: + * + * Reads one line of script and decides what to do next. + */ +static void +next_scriptstate(void) +{ + struct fs_file fsfile; + u8_t i; + + again: + switch(hs->script[0]) { + case ISO_t: + /* Send a text string. */ + hs->state = HTTP_TEXT; + hs->dataptr = &hs->script[2]; + + /* Calculate length of string. */ + for(i = 0; hs->dataptr[i] != ISO_nl; ++i); + hs->count = i; + break; + case ISO_c: + /* Call a function. */ + hs->state = HTTP_FUNC; + hs->dataptr = NULL; + hs->count = 0; + cgitab[hs->script[2] - ISO_a](0); + break; + case ISO_i: + /* Include a file. */ + hs->state = HTTP_FILE; + if(!fs_open(&hs->script[2], &fsfile)) { + uip_abort(); + } + hs->dataptr = fsfile.data; + hs->count = fsfile.len; + break; + case ISO_hash: + /* Comment line. */ + next_scriptline(); + goto again; + break; + case ISO_period: + /* End of script. */ + hs->state = HTTP_END; + uip_close(); + break; + default: + uip_abort(); + break; + } +} +/*-----------------------------------------------------------------------------------*/ +/** @} */ +/** @} */ diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/httpd.h b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/httpd.h new file mode 100644 index 000000000..34d6bb35f --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/httpd.h @@ -0,0 +1,77 @@ +/** + * \addtogroup httpd + * @{ + */ + +/** + * \file + * HTTP server header file. + * \author Adam Dunkels + */ + +/* + * Copyright (c) 2001, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: httpd.h,v 1.4.2.3 2003/10/06 22:56:44 adam Exp $ + * + */ + +#ifndef __HTTPD_H__ +#define __HTTPD_H__ + +void httpd_init(void); +void httpd_appcall(void); + +/* UIP_APPCALL: the name of the application function. This function + must return void and take no arguments (i.e., C type "void + appfunc(void)"). */ +#ifndef UIP_APPCALL +#define UIP_APPCALL httpd_appcall +#endif + +struct httpd_state { + u8_t state; + u16_t count; + char *dataptr; + char *script; +}; + + +/* UIP_APPSTATE_SIZE: The size of the application-specific state + stored in the uip_conn structure. */ +#ifndef UIP_APPSTATE_SIZE +#define UIP_APPSTATE_SIZE (sizeof(struct httpd_state)) +#endif + +#define FS_STATISTICS 1 + +extern struct httpd_state *hs; + +#endif /* __HTTPD_H__ */ diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/main_led b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/main_led new file mode 100644 index 000000000..8fe01ea6d --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/main_led @@ -0,0 +1,67 @@ +// Copyright (c) 2001-2004 Rowley Associates Limited. +// +// This file may be distributed under the terms of the License Agreement +// provided with this software. +// +// THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE +// WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. +// +//////////////////////////////////////////////////////////////////////////////// +// +// Olimex LPC-P1 LED Example +// +// Description +// ----------- +// This example demonstrates writing to the programmable peripheral interface. +// +//////////////////////////////////////////////////////////////////////////////// + +#include + +#define LED_RED (1<<8) +#define LED_GREEN (1<<10) +#define LED_YELLOW (1<<11) + +#define LED1 LED_YELLOW + +static void +ledInit() +{ + IODIR |= LED1; + IOSET = LED1; +} + +static void +ledOn(void) +{ + IOCLR = LED1; +} + +static void +ledOff(void) +{ + IOSET = LED1; +} + +void +delay(int d) +{ + for(; d; --d); +} + +int +main(void) +{ + MAMCR = 2; + ledInit(); + while (1) + { + ledOn(); + delay(100000); + ledOff(); + delay(100000); + } + return 0; +} + + diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/makefsdata b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/makefsdata new file mode 100644 index 000000000..f5f75f174 --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/makefsdata @@ -0,0 +1,93 @@ +#!/usr/bin/perl + +open(OUTPUT, "> fsdata.c"); + +chdir("fs"); +open(FILES, "find . -type f |"); + +while($file = ) { + + # Do not include files in CVS directories nor backup files. + if($file =~ /(CVS|~)/) { + next; + } + + chop($file); + + open(HEADER, "> /tmp/header") || die $!; + if($file =~ /404.html/) { + print(HEADER "HTTP/1.0 404 File not found\r\n"); + } else { + print(HEADER "HTTP/1.0 200 OK\r\n"); + } + print(HEADER "Server: uIP/0.9 (http://dunkels.com/adam/uip/)\r\n"); + if($file =~ /\.html$/) { + print(HEADER "Content-type: text/html\r\n"); + } elsif($file =~ /\.gif$/) { + print(HEADER "Content-type: image/gif\r\n"); + } elsif($file =~ /\.png$/) { + print(HEADER "Content-type: image/png\r\n"); + } elsif($file =~ /\.jpg$/) { + print(HEADER "Content-type: image/jpeg\r\n"); + } else { + print(HEADER "Content-type: text/plain\r\n"); + } + print(HEADER "\r\n"); + close(HEADER); + + unless($file =~ /\.plain$/ || $file =~ /cgi/) { + system("cat /tmp/header $file > /tmp/file"); + } else { + system("cp $file /tmp/file"); + } + + open(FILE, "/tmp/file"); + unlink("/tmp/file"); + unlink("/tmp/header"); + + $file =~ s/\.//; + $fvar = $file; + $fvar =~ s-/-_-g; + $fvar =~ s-\.-_-g; + print(OUTPUT "static const char data".$fvar."[] = {\n"); + print(OUTPUT "\t/* $file */\n\t"); + for($j = 0; $j < length($file); $j++) { + printf(OUTPUT "%#02x, ", unpack("C", substr($file, $j, 1))); + } + printf(OUTPUT "0,\n"); + + + $i = 0; + while(read(FILE, $data, 1)) { + if($i == 0) { + print(OUTPUT "\t"); + } + printf(OUTPUT "%#02x, ", unpack("C", $data)); + $i++; + if($i == 10) { + print(OUTPUT "\n"); + $i = 0; + } + } + print(OUTPUT "};\n\n"); + close(FILE); + push(@fvars, $fvar); + push(@files, $file); +} + +for($i = 0; $i < @fvars; $i++) { + $file = $files[$i]; + $fvar = $fvars[$i]; + + if($i == 0) { + $prevfile = "NULL"; + } else { + $prevfile = "file" . $fvars[$i - 1]; + } + print(OUTPUT "const struct fsdata_file file".$fvar."[] = {{$prevfile, data$fvar, "); + print(OUTPUT "data$fvar + ". (length($file) + 1) .", "); + print(OUTPUT "sizeof(data$fvar) - ". (length($file) + 1) ."}};\n\n"); +} + +print(OUTPUT "#define FS_ROOT file$fvars[$i - 1]\n\n"); +print(OUTPUT "#define FS_NUMFILES $i"); diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/memb.c b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/memb.c new file mode 100644 index 000000000..56e663446 --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/memb.c @@ -0,0 +1,152 @@ +/** + * \addtogroup exampleapps + * @{ + */ + +/** + * \file + * Memory block allocation routines. + * \author Adam Dunkels + * + * The memory block allocation routines provide a simple yet powerful + * set of functions for managing a set of memory blocks of fixed + * size. A set of memory blocks is statically declared with the + * MEMB() macro. Memory blocks are allocated from the declared + * memory by the memb_alloc() function, and are deallocated with the + * memb_free() function. + * + * \note Because of namespace clashes only one MEMB() can be + * declared per C module, and the name scope of a MEMB() memory + * block is local to each C module. + * + * The following example shows how to declare and use a memory block + * called "cmem" which has 8 chunks of memory with each memory chunk + * being 20 bytes large. + * + \code + MEMB(cmem, 20, 8); + + int main(int argc, char *argv[]) { + char *ptr; + + memb_init(&cmem); + + ptr = memb_alloc(&cmem); + + if(ptr != NULL) { + do_something(ptr); + } else { + printf("Could not allocate memory.\n"); + } + + if(memb_free(ptr) == 0) { + printf("Deallocation succeeded.\n"); + } + } + \endcode + * + */ + +#include + +#include "memb.h" + +/*------------------------------------------------------------------------------*/ +/** + * Initialize a memory block that was declared with MEMB(). + * + * \param m A memory block previosly declared with MEMB(). + */ +/*------------------------------------------------------------------------------*/ +void +memb_init(struct memb_blocks *m) +{ + memset(m->mem, (m->size + 1) * m->num, 0); +} +/*------------------------------------------------------------------------------*/ +/** + * Allocate a memory block from a block of memory declared with MEMB(). + * + * \param m A memory block previosly declared with MEMB(). + */ +/*------------------------------------------------------------------------------*/ +char * +memb_alloc(struct memb_blocks *m) +{ + int i; + char *ptr; + + ptr = m->mem; + for(i = 0; i < m->num; ++i) { + if(*ptr == 0) { + /* If this block was unused, we increase the reference count to + indicate that it now is used and return a pointer to the + first byte following the reference counter. */ + ++*ptr; + return ptr + 1; + } + ptr += m->size + 1; + } + + /* No free block was found, so we return NULL to indicate failure to + allocate block. */ + return NULL; +} +/*------------------------------------------------------------------------------*/ +/** + * Deallocate a memory block from a memory block previously declared + * with MEMB(). + * + * \param m m A memory block previosly declared with MEMB(). + * + * \param ptr A pointer to the memory block that is to be deallocated. + * + * \return The new reference count for the memory block (should be 0 + * if successfully deallocated) or -1 if the pointer "ptr" did not + * point to a legal memory block. + */ +/*------------------------------------------------------------------------------*/ +char +memb_free(struct memb_blocks *m, char *ptr) +{ + int i; + char *ptr2; + + /* Walk through the list of blocks and try to find the block to + which the pointer "ptr" points to. */ + ptr2 = m->mem; + for(i = 0; i < m->num; ++i) { + + if(ptr2 == ptr - 1) { + /* We've found to block to which "ptr" points so we decrease the + reference count and return the new value of it. */ + return --*ptr2; + } + ptr2 += m->size + 1; + } + return -1; +} +/*------------------------------------------------------------------------------*/ +/** + * Increase the reference count for a memory chunk. + * + * \note No sanity checks are currently made. + * + * \param m m A memory block previosly declared with MEMB(). + * + * \param ptr A pointer to the memory chunk for which the reference + * count should be increased. + * + * \return The new reference count. + */ +/*------------------------------------------------------------------------------*/ +char +memb_ref(struct memb_blocks *m, char *ptr) +{ + return ++*(ptr - 1); +} +/*------------------------------------------------------------------------------*/ + + + + diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/memb.h b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/memb.h new file mode 100644 index 000000000..505846f4d --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/memb.h @@ -0,0 +1,43 @@ +/** + * \addtogroup exampleapps + * @{ + */ + +/** + * \file + * Memory block allocation routines. + * \author Adam Dunkels + * + */ + +#ifndef __MEMB_H__ +#define __MEMB_H__ + +/** + * Declare a memory block. + * + * \param name The name of the memory block (later used with + * memb_init(), memb_alloc() and memb_free()). + * + * \param size The size of each memory chunk, in bytes. + * + * \param num The total number of memory chunks in the block. + * + */ +#define MEMB(name, size, num) \ + static char memb_mem[(size + 1) * num]; \ + static struct memb_blocks name = {size, num, memb_mem} + +struct memb_blocks { + unsigned short size; + unsigned short num; + char *mem; +}; + +void memb_init(struct memb_blocks *m); +char *memb_alloc(struct memb_blocks *m); +char memb_ref(struct memb_blocks *m, char *ptr); +char memb_free(struct memb_blocks *m, char *ptr); + + +#endif /* __MEMB_H__ */ diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/slipdev.c b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/slipdev.c new file mode 100644 index 000000000..fc968c82e --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/slipdev.c @@ -0,0 +1,202 @@ +/** + * \addtogroup uip + * @{ + */ + +/** + * \defgroup slip Serial Line IP (SLIP) protocol + * @{ + * + * The SLIP protocol is a very simple way to transmit IP packets over + * a serial line. It does not provide any framing or error control, + * and is therefore not very widely used today. + * + * This SLIP implementation requires two functions for accessing the + * serial device: slipdev_char_poll() and slipdev_char_put(). These + * must be implemented specifically for the system on which the SLIP + * protocol is to be run. + */ + +/** + * \file + * SLIP protocol implementation + * \author Adam Dunkels + */ + +/* + * Copyright (c) 2001, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: slipdev.c,v 1.1.2.3 2003/10/07 13:23:01 adam Exp $ + * + */ + +/* + * This is a generic implementation of the SLIP protocol over an RS232 + * (serial) device. + * + * Huge thanks to Ullrich von Bassewitz of cc65 fame for + * and endless supply of bugfixes, insightsful comments and + * suggestions, and improvements to this code! + */ + +#include "uip.h" + +#define SLIP_END 0300 +#define SLIP_ESC 0333 +#define SLIP_ESC_END 0334 +#define SLIP_ESC_ESC 0335 + +static u8_t slip_buf[UIP_BUFSIZE]; + +static u16_t len, tmplen; +static u8_t lastc; + +/*-----------------------------------------------------------------------------------*/ +/** + * Send the packet in the uip_buf and uip_appdata buffers using the + * SLIP protocol. + * + * The first 40 bytes of the packet (the IP and TCP headers) are read + * from the uip_buf buffer, and the following bytes (the application + * data) are read from the uip_appdata buffer. + * + */ +/*-----------------------------------------------------------------------------------*/ +void +slipdev_send(void) +{ + u16_t i; + u8_t *ptr; + u8_t c; + + slipdev_char_put(SLIP_END); + + ptr = uip_buf; + for(i = 0; i < uip_len; ++i) { + if(i == 40) { + ptr = (u8_t *)uip_appdata; + } + c = *ptr++; + switch(c) { + case SLIP_END: + slipdev_char_put(SLIP_ESC); + slipdev_char_put(SLIP_ESC_END); + break; + case SLIP_ESC: + slipdev_char_put(SLIP_ESC); + slipdev_char_put(SLIP_ESC_ESC); + break; + default: + slipdev_char_put(c); + break; + } + } + slipdev_char_put(SLIP_END); +} +/*-----------------------------------------------------------------------------------*/ +/** + * Poll the SLIP device for an available packet. + * + * This function will poll the SLIP device to see if a packet is + * available. It uses a buffer in which all avaliable bytes from the + * RS232 interface are read into. When a full packet has been read + * into the buffer, the packet is copied into the uip_buf buffer and + * the length of the packet is returned. + * + * \return The length of the packet placed in the uip_buf buffer, or + * zero if no packet is available. + */ +/*-----------------------------------------------------------------------------------*/ +u16_t +slipdev_poll(void) +{ + u8_t c; + + while(slipdev_char_poll(c)) { + switch(c) { + case SLIP_ESC: + lastc = c; + break; + + case SLIP_END: + lastc = c; + /* End marker found, we copy our input buffer to the uip_buf + buffer and return the size of the packet we copied. */ + memcpy(uip_buf, slip_buf, len); + tmplen = len; + len = 0; + return tmplen; + + default: + if(lastc == SLIP_ESC) { + lastc = c; + /* Previous read byte was an escape byte, so this byte will be + interpreted differently from others. */ + switch(c) { + case SLIP_ESC_END: + c = SLIP_END; + break; + case SLIP_ESC_ESC: + c = SLIP_ESC; + break; + } + } else { + lastc = c; + } + + slip_buf[len] = c; + ++len; + + if(len > UIP_BUFSIZE) { + len = 0; + } + + break; + } + } + return 0; +} +/*-----------------------------------------------------------------------------------*/ +/** + * Initialize the SLIP module. + * + * This function does not initialize the underlying RS232 device, but + * only the SLIP part. + */ +/*-----------------------------------------------------------------------------------*/ +void +slipdev_init(void) +{ + lastc = len = 0; +} +/*-----------------------------------------------------------------------------------*/ + +/** @} */ +/** @} */ diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/slipdev.h b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/slipdev.h new file mode 100644 index 000000000..3fbfe2d2d --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/slipdev.h @@ -0,0 +1,88 @@ +/** + * \addtogroup slip + * @{ + */ + +/** + * \file + * SLIP header file. + * \author Adam Dunkels + */ + +/* + * Copyright (c) 2001, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: slipdev.h,v 1.1.2.3 2003/10/06 22:42:51 adam Exp $ + * + */ + +#ifndef __SLIPDEV_H__ +#define __SLIPDEV_H__ + +#include "uip.h" + +/** + * Put a character on the serial device. + * + * This function is used by the SLIP implementation to put a character + * on the serial device. It must be implemented specifically for the + * system on which the SLIP implementation is to be run. + * + * \param c The character to be put on the serial device. + */ +void slipdev_char_put(u8_t c); + +/** + * Poll the serial device for a character. + * + * This function is used by the SLIP implementation to poll the serial + * device for a character. It must be implemented specifically for the + * system on which the SLIP implementation is to be run. + * + * The function should return immediately regardless if a character is + * available or not. If a character is available it should be placed + * at the memory location pointed to by the pointer supplied by the + * arguement c. + * + * \param c A pointer to a byte that is filled in by the function with + * the received character, if available. + * + * \retval 0 If no character is available. + * \retval Non-zero If a character is available. + */ +u8_t slipdev_char_poll(u8_t *c); + +void slipdev_init(void); +void slipdev_send(void); +u16_t slipdev_poll(void); + +#endif /* __SLIPDEV_H__ */ + +/** @} */ diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/tapdev.c b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/tapdev.c new file mode 100644 index 000000000..0d23fc4d9 --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/tapdev.c @@ -0,0 +1,171 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * Author: Adam Dunkels + * + * $Id: tapdev.c,v 1.7.2.1 2003/10/07 13:23:19 adam Exp $ + */ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef linux +#include +#include +#include +#define DEVTAP "/dev/net/tun" +#else /* linux */ +#define DEVTAP "/dev/tap0" +#endif /* linux */ + +#include "uip.h" + +static int fd; + +static unsigned long lasttime; +static struct timezone tz; + +/*-----------------------------------------------------------------------------------*/ +void +tapdev_init(void) +{ + char buf[1024]; + + fd = open(DEVTAP, O_RDWR); + if(fd == -1) { + perror("tapdev: tapdev_init: open"); + exit(1); + } + +#ifdef linux + { + struct ifreq ifr; + memset(&ifr, 0, sizeof(ifr)); + ifr.ifr_flags = IFF_TAP|IFF_NO_PI; + if (ioctl(fd, TUNSETIFF, (void *) &ifr) < 0) { + perror(buf); + exit(1); + } + } +#endif /* Linux */ + + snprintf(buf, sizeof(buf), "ifconfig tap0 inet %d.%d.%d.%d", + UIP_DRIPADDR0, UIP_DRIPADDR1, UIP_DRIPADDR2, UIP_DRIPADDR3); + system(buf); + + lasttime = 0; +} +/*-----------------------------------------------------------------------------------*/ +unsigned int +tapdev_read(void) +{ + fd_set fdset; + struct timeval tv, now; + int ret; + + if(lasttime >= 500000) { + lasttime = 0; + return 0; + } + + tv.tv_sec = 0; + tv.tv_usec = 500000 - lasttime; + + + FD_ZERO(&fdset); + FD_SET(fd, &fdset); + + gettimeofday(&now, &tz); + ret = select(fd + 1, &fdset, NULL, NULL, &tv); + if(ret == 0) { + lasttime = 0; + return 0; + } + ret = read(fd, uip_buf, UIP_BUFSIZE); + if(ret == -1) { + perror("tap_dev: tapdev_read: read"); + } + gettimeofday(&tv, &tz); + lasttime += (tv.tv_sec - now.tv_sec) * 1000000 + (tv.tv_usec - now.tv_usec); + + return ret; +} +/*-----------------------------------------------------------------------------------*/ +void +tapdev_send(void) +{ + int ret; + struct iovec iov[2]; + +#ifdef linux + { + char tmpbuf[UIP_BUFSIZE]; + int i; + + for(i = 0; i < 40 + UIP_LLH_LEN; i++) { + tmpbuf[i] = uip_buf[i]; + } + + for(; i < uip_len; i++) { + tmpbuf[i] = uip_appdata[i - 40 - UIP_LLH_LEN]; + } + + ret = write(fd, tmpbuf, uip_len); + } +#else + + if(uip_len < 40 + UIP_LLH_LEN) { + ret = write(fd, uip_buf, uip_len + UIP_LLH_LEN); + } else { + iov[0].iov_base = uip_buf; + iov[0].iov_len = 40 + UIP_LLH_LEN; + iov[1].iov_base = (char *)uip_appdata; + iov[1].iov_len = uip_len - (40 + UIP_LLH_LEN); + + ret = writev(fd, iov, 2); + } +#endif + if(ret == -1) { + perror("tap_dev: tapdev_send: writev"); + exit(1); + } +} +/*-----------------------------------------------------------------------------------*/ diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/tapdev.h b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/tapdev.h new file mode 100644 index 000000000..66f1a4a71 --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/tapdev.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2001, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: tapdev.h,v 1.1.2.1 2003/10/04 22:54:17 adam Exp $ + * + */ + +#ifndef __TAPDEV_H__ +#define __TAPDEV_H__ + +void tapdev_init(void); +unsigned int tapdev_read(void); +void tapdev_send(void); + +#endif /* __TAPDEV_H__ */ diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/telnetd-shell.c b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/telnetd-shell.c new file mode 100644 index 000000000..7dff714ca --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/telnetd-shell.c @@ -0,0 +1,181 @@ +/** + * \addtogroup telnetd + * @{ + */ + +/** + * \file + * An example telnet server shell + * \author Adam Dunkels + */ + +/* + * Copyright (c) 2003, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the Contiki desktop OS. + * + * $Id: telnetd-shell.c,v 1.1.2.1 2003/10/06 22:56:22 adam Exp $ + * + */ + +#include "uip.h" +#include "telnetd.h" +#include + +struct ptentry { + char c; + void (* pfunc)(struct telnetd_state *s, char *str); +}; + +/*-----------------------------------------------------------------------------------*/ +static void +parse(struct telnetd_state *s, register char *str, struct ptentry *t) +{ + register struct ptentry *p; + char *sstr; + + sstr = str; + + /* Loop over the parse table entries in t in order to find one that + matches the first character in str. */ + for(p = t; p->c != 0; ++p) { + if(*str == p->c) { + /* Skip rest of the characters up to the first space. */ + while(*str != ' ') { + ++str; + } + + /* Skip all spaces.*/ + while(*str == ' ') { + ++str; + } + + /* Call parse table entry function and return. */ + p->pfunc(s, str); + return; + } + } + + /* Did not find matching entry in parse table. We just call the + default handler supplied by the caller and return. */ + p->pfunc(s, str); +} +/*-----------------------------------------------------------------------------------*/ +static void +exitt(struct telnetd_state *s, char *str) +{ + telnetd_close(s); +} +/*-----------------------------------------------------------------------------------*/ +static void +inttostr(register char *str, unsigned int i) +{ + str[0] = '0' + i / 100; + if(str[0] == '0') { + str[0] = ' '; + } + str[1] = '0' + (i / 10) % 10; + if(str[1] == '0') { + str[1] = ' '; + } + str[2] = '0' + i % 10; + str[3] = ' '; + str[4] = 0; +} +/*-----------------------------------------------------------------------------------*/ +static void +stats(struct telnetd_state *s, char *strr) +{ + char str[10]; + + inttostr(str, uip_stat.ip.recv); + telnetd_output(s, "IP packets received ", str); + inttostr(str, uip_stat.ip.sent); + telnetd_output(s, "IP packets sent ", str); + inttostr(str, uip_stat.ip.drop); + telnetd_output(s, "IP packets dropped ", str); + + inttostr(str, uip_stat.icmp.recv); + telnetd_output(s, "ICMP packets received ", str); + inttostr(str, uip_stat.icmp.sent); + telnetd_output(s, "ICMP packets sent ", str); + inttostr(str, uip_stat.icmp.drop); + telnetd_output(s, "ICMP packets dropped ", str); + + inttostr(str, uip_stat.tcp.recv); + telnetd_output(s, "TCP packets received ", str); + inttostr(str, uip_stat.tcp.sent); + telnetd_output(s, "TCP packets sent ", str); + inttostr(str, uip_stat.tcp.drop); + telnetd_output(s, "TCP packets dropped ", str); + inttostr(str, uip_stat.tcp.rexmit); + telnetd_output(s, "TCP packets retransmitted ", str); + inttostr(str, uip_stat.tcp.synrst); + telnetd_output(s, "TCP connection attempts ", str); +} +/*-----------------------------------------------------------------------------------*/ +static void +help(struct telnetd_state *s, char *str) +{ + telnetd_output(s, "Available commands:", ""); + telnetd_output(s, "stats - show uIP statistics", ""); + telnetd_output(s, "exit - exit shell", ""); + telnetd_output(s, "? - show this help", ""); +} +/*-----------------------------------------------------------------------------------*/ +static void +none(struct telnetd_state *s, char *str) +{ + if(strlen(str) > 0) { + telnetd_output(s, "Unknown command", ""); + } +} +/*-----------------------------------------------------------------------------------*/ +static struct ptentry configparsetab[] = + {{'s', stats}, + {'e', exitt}, + {'?', help}, + + /* Default action */ + {0, none}}; +/*-----------------------------------------------------------------------------------*/ +void +telnetd_connected(struct telnetd_state *s) +{ + telnetd_output(s, "uIP command shell", ""); + telnetd_output(s, "Type '?' for help", ""); + telnetd_prompt(s, "uIP-0.9> "); +} +/*-----------------------------------------------------------------------------------*/ +void +telnetd_input(struct telnetd_state *s, char *cmd) +{ + parse(s, cmd, configparsetab); + telnetd_prompt(s, "uIP-0.9> "); +} +/*-----------------------------------------------------------------------------------*/ diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/telnetd.c b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/telnetd.c new file mode 100644 index 000000000..dba522271 --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/telnetd.c @@ -0,0 +1,392 @@ +/** + * \addtogroup exampleapps + * @{ + */ + +/** + * \defgroup telnetd Telnet server + * @{ + * + * The uIP telnet server provides a command based interface to uIP. It + * allows using the "telnet" application to access uIP, and implements + * the required telnet option negotiation. + * + * The code is structured in a way which makes it possible to add + * commands without having to rewrite the main telnet code. The main + * telnet code calls two callback functions, telnetd_connected() and + * telnetd_input(), when a telnet connection has been established and + * when a line of text arrives on a telnet connection. These two + * functions can be implemented in a way which suits the particular + * application or environment in which the uIP system is intended to + * be run. + * + * The uIP distribution contains an example telnet shell + * implementation that provides a basic set of commands. + */ + +/** + * \file + * Implementation of the Telnet server. + * \author Adam Dunkels + */ + +/* + * Copyright (c) 2003, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: telnetd.c,v 1.1.2.2 2003/10/07 13:47:50 adam Exp $ + * + */ + +#include "uip.h" +#include "memb.h" +#include "telnetd.h" +#include + +#define ISO_nl 0x0a +#define ISO_cr 0x0d + +MEMB(linemem, TELNETD_LINELEN, TELNETD_NUMLINES); + +static u8_t i; + +#define STATE_NORMAL 0 +#define STATE_IAC 1 +#define STATE_WILL 2 +#define STATE_WONT 3 +#define STATE_DO 4 +#define STATE_DONT 5 +#define STATE_CLOSE 6 + +#define TELNET_IAC 255 +#define TELNET_WILL 251 +#define TELNET_WONT 252 +#define TELNET_DO 253 +#define TELNET_DONT 254 +/*-----------------------------------------------------------------------------------*/ +static char * +alloc_line(void) +{ + return memb_alloc(&linemem); +} +/*-----------------------------------------------------------------------------------*/ +static void +dealloc_line(char *line) +{ + memb_free(&linemem, line); +} +/*-----------------------------------------------------------------------------------*/ +static void +sendline(struct telnetd_state *s, char *line) +{ + static unsigned int i; + for(i = 0; i < TELNETD_NUMLINES; ++i) { + if(s->lines[i] == NULL) { + s->lines[i] = line; + break; + } + } + if(i == TELNETD_NUMLINES) { + dealloc_line(line); + } +} +/*-----------------------------------------------------------------------------------*/ +/** + * Close a telnet session. + * + * This function can be called from a telnet command in order to close + * the connection. + * + * \param s The connection which is to be closed. + * + */ +/*-----------------------------------------------------------------------------------*/ +void +telnetd_close(struct telnetd_state *s) +{ + s->state = STATE_CLOSE; +} +/*-----------------------------------------------------------------------------------*/ +/** + * Print a prompt on a telnet connection. + * + * This function can be called by the telnet command shell in order to + * print out a command prompt. + * + * \param s A telnet connection. + * + * \param str The command prompt. + * + */ +/*-----------------------------------------------------------------------------------*/ +void +telnetd_prompt(struct telnetd_state *s, char *str) +{ + char *line; + line = alloc_line(); + if(line != NULL) { + strncpy(line, str, TELNETD_LINELEN); + sendline(s, line); + } +} +/*-----------------------------------------------------------------------------------*/ +/** + * Print out a string on a telnet connection. + * + * This function can be called from a telnet command parser in order + * to print out a string of text on the connection. The two strings + * given as arguments to the function will be concatenated, a carrige + * return and a new line character will be added, and the line is + * sent. + * + * \param s The telnet connection. + * + * \param str1 The first string. + * + * \param str2 The second string. + * + */ +/*-----------------------------------------------------------------------------------*/ +void +telnetd_output(struct telnetd_state *s, char *str1, char *str2) +{ + static unsigned len; + char *line; + + line = alloc_line(); + if(line != NULL) { + len = strlen(str1); + strncpy(line, str1, TELNETD_LINELEN); + if(len < TELNETD_LINELEN) { + strncpy(line + len, str2, TELNETD_LINELEN - len); + } + len = strlen(line); + if(len < TELNETD_LINELEN - 2) { + line[len] = ISO_cr; + line[len+1] = ISO_nl; + line[len+2] = 0; + } + sendline(s, line); + } +} +/*-----------------------------------------------------------------------------------*/ +/** + * Initialize the telnet server. + * + * This function will perform the necessary initializations and start + * listening on TCP port 23. + */ +/*-----------------------------------------------------------------------------------*/ +void +telnetd_init(void) +{ + memb_init(&linemem); + uip_listen(HTONS(23)); +} +/*-----------------------------------------------------------------------------------*/ +static void +acked(struct telnetd_state *s) +{ + dealloc_line(s->lines[0]); + for(i = 1; i < TELNETD_NUMLINES; ++i) { + s->lines[i - 1] = s->lines[i]; + } +} +/*-----------------------------------------------------------------------------------*/ +static void +senddata(struct telnetd_state *s) +{ + if(s->lines[0] != NULL) { + uip_send(s->lines[0], strlen(s->lines[0])); + } +} +/*-----------------------------------------------------------------------------------*/ +static void +getchar(struct telnetd_state *s, u8_t c) +{ + if(c == ISO_cr) { + return; + } + + s->buf[(int)s->bufptr] = c; + if(s->buf[(int)s->bufptr] == ISO_nl || + s->bufptr == sizeof(s->buf) - 1) { + if(s->bufptr > 0) { + s->buf[(int)s->bufptr] = 0; + } + telnetd_input(s, s->buf); + s->bufptr = 0; + } else { + ++s->bufptr; + } +} +/*-----------------------------------------------------------------------------------*/ +static void +sendopt(struct telnetd_state *s, u8_t option, u8_t value) +{ + char *line; + line = alloc_line(); + if(line != NULL) { + line[0] = TELNET_IAC; + line[1] = option; + line[2] = value; + line[3] = 0; + sendline(s, line); + } +} +/*-----------------------------------------------------------------------------------*/ +static void +newdata(struct telnetd_state *s) +{ + u16_t len; + u8_t c; + + + len = uip_datalen(); + + while(len > 0 && s->bufptr < sizeof(s->buf)) { + c = *uip_appdata; + ++uip_appdata; + --len; + switch(s->state) { + case STATE_IAC: + if(c == TELNET_IAC) { + getchar(s, c); + s->state = STATE_NORMAL; + } else { + switch(c) { + case TELNET_WILL: + s->state = STATE_WILL; + break; + case TELNET_WONT: + s->state = STATE_WONT; + break; + case TELNET_DO: + s->state = STATE_DO; + break; + case TELNET_DONT: + s->state = STATE_DONT; + break; + default: + s->state = STATE_NORMAL; + break; + } + } + break; + case STATE_WILL: + /* Reply with a DONT */ + sendopt(s, TELNET_DONT, c); + s->state = STATE_NORMAL; + break; + + case STATE_WONT: + /* Reply with a DONT */ + sendopt(s, TELNET_DONT, c); + s->state = STATE_NORMAL; + break; + case STATE_DO: + /* Reply with a WONT */ + sendopt(s, TELNET_WONT, c); + s->state = STATE_NORMAL; + break; + case STATE_DONT: + /* Reply with a WONT */ + sendopt(s, TELNET_WONT, c); + s->state = STATE_NORMAL; + break; + case STATE_NORMAL: + if(c == TELNET_IAC) { + s->state = STATE_IAC; + } else { + getchar(s, c); + } + break; + } + + + } + +} +/*-----------------------------------------------------------------------------------*/ +void +telnetd_app(void) +{ + struct telnetd_state *s; + + s = (struct telnetd_state *)uip_conn->appstate; + + if(uip_connected()) { + + for(i = 0; i < TELNETD_NUMLINES; ++i) { + s->lines[i] = NULL; + } + s->bufptr = 0; + s->state = STATE_NORMAL; + + telnetd_connected(s); + senddata(s); + return; + } + + if(s->state == STATE_CLOSE) { + s->state = STATE_NORMAL; + uip_close(); + return; + } + + if(uip_closed()) { + telnetd_output(s, "Connection closed", ""); + } + + + if(uip_aborted()) { + telnetd_output(s, "Connection reset", ""); + } + + if(uip_timedout()) { + telnetd_output(s, "Connection timed out", ""); + } + + if(uip_acked()) { + acked(s); + } + + if(uip_newdata()) { + newdata(s); + } + + if(uip_rexmit() || + uip_newdata() || + uip_acked()) { + senddata(s); + } else if(uip_poll()) { + senddata(s); + } +} +/*-----------------------------------------------------------------------------------*/ diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/telnetd.h b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/telnetd.h new file mode 100644 index 000000000..254e44ff1 --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/telnetd.h @@ -0,0 +1,114 @@ +/** + * \addtogroup telnetd + * @{ + */ + +/** + * \file + * Header file for the telnet server. + * \author Adam Dunkels + */ + +/* + * Copyright (c) 2002, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: telnetd.h,v 1.1.2.2 2003/10/07 13:22:27 adam Exp $ + * + */ +#ifndef __TELNETD_H__ +#define __TELNETD_H__ + +#include "uip.h" + +/** + * The maximum length of a telnet line. + * + * \hideinitializer + */ +#define TELNETD_LINELEN 36 + +/** + * The number of output lines being buffered for all telnet + * connections. + * + * \hideinitializer + */ +#define TELNETD_NUMLINES 2 + +/** + * A telnet connection structure. + */ +struct telnetd_state { + char *lines[TELNETD_NUMLINES]; + char buf[TELNETD_LINELEN]; + char bufptr; + u8_t state; +}; + + +/** + * Callback function that is called when a telnet connection has been + * established. + * + * \param s The telnet connection. + */ +void telnetd_connected(struct telnetd_state *s); + +/** + * Callback function that is called when a line of text has arrived on + * a telnet connection. + * + * \param s The telnet connection. + * + * \param cmd The line of text. + */ +void telnetd_input(struct telnetd_state *s, char *cmd); + + +void telnetd_close(struct telnetd_state *s); +void telnetd_output(struct telnetd_state *s, char *s1, char *s2); +void telnetd_prompt(struct telnetd_state *s, char *str); + +void telnetd_app(void); + +#ifndef UIP_APPCALL +#define UIP_APPCALL telnetd_app +#endif + +#ifndef UIP_APPSTATE_SIZE +#define UIP_APPSTATE_SIZE (sizeof(struct telnetd_state)) +#endif + +void telnetd_init(void); + + +#endif /* __TELNET_H__ */ + +/** @} */ diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/uIP_Task.c b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/uIP_Task.c new file mode 100644 index 000000000..85d2f469e --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/uIP_Task.c @@ -0,0 +1,201 @@ +/* + * Copyright (c) 2001-2003, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: main.c,v 1.10.2.4 2003/10/21 21:27:51 adam Exp $ + * + */ + + +#include /* For system(). */ +#include /* For printf(). */ + +#include "FreeRTOS.h" +#include "task.h" + +#undef HTONS + +#include "cs8900a.h" +#include "uip.h" +#include "uip_arp.h" +#include "tapdev.h" +#include "httpd.h" + +static const struct uip_eth_addr ethaddr = {{0x00,0x00,0xe2,0x58,0xb6,0x6b}}; + +#define BUF ((struct uip_eth_hdr *)&uip_buf[0]) +#define uipSHORT_DELAY ( ( portTickType ) 2 / portTICK_RATE_MS ) + +#ifndef NULL +#define NULL (void *)0 +#endif /* NULL */ + +static volatile portTickType start, current; + +#define RT_CLOCK_SECOND ( configTICK_RATE_HZ / 2 ) + +/*-----------------------------------------------------------------------------------*/ +/** + * \internal + * A real-time clock. + * + * This example main() function uses polling of a real-time clock in + * order to know when the periodic processing should be + * performed. This is implemented using this function - rt_ticks(). In + * this example unix implementation, it simply calls the unix function + * gettimeofday() which returns the current wall clock time. + * + * For a micro-controller, a simple way to implement this function is + * by having a counter that is incremented by a timer interrupt and + * read by this function. + * + * The macro RT_CLOCK_SECOND should be defined as the approximate + * number of ticks that are elapsed during one second. + */ +#define rt_ticks xTaskGetTickCount + +/*-----------------------------------------------------------------------------------*/ +void vuIP_TASK( void *pvParameters ) +{ +u8_t i, arptimer; +u16_t addr[2]; +int z = 3; + + /* Initialize the uIP TCP/IP stack. */ + uip_init(); + uip_arp_init(); + + /* Initialize the device driver. */ + cs8900a_init(); + + /* Initialize the HTTP server. */ + httpd_init(); + + start = rt_ticks(); + arptimer = 0; + + while(1) + { + /* Let the network device driver read an entire IP packet + into the uip_buf. If it returns > 0, there is a packet in the + uip_buf buffer. */ + uip_len = cs8900a_poll(); + + if(uip_len > 0) + { + /* A packet is present in the packet buffer. We call the + appropriate ARP functions depending on what kind of packet we + have received. If the packet is an IP packet, we should call + uip_input() as well. */ + if(BUF->type == htons(UIP_ETHTYPE_IP)) + { + uip_arp_ipin(); + uip_input(); + /* If the above function invocation resulted in data that + should be sent out on the network, the global variable + uip_len is set to a value > 0. */ + if(uip_len > 0) + { + uip_arp_out(); + cs8900a_send(); + } + } + else if(BUF->type == htons(UIP_ETHTYPE_ARP)) + { + uip_arp_arpin(); + /* If the above function invocation resulted in data that + should be sent out on the network, the global variable + uip_len is set to a value > 0. */ + if(uip_len > 0) + { + cs8900a_send(); + } + } + } + else + { + /* The poll function returned 0, so no packet was + received. Instead we check if there is time that we do the + periodic processing. */ + current = rt_ticks(); + + if((u16_t)(current - start) >= (u16_t)RT_CLOCK_SECOND / 2) + { + start = current; + + for(i = 0; i < UIP_CONNS; i++) + { + uip_periodic(i); + + /* If the above function invocation resulted in data that + should be sent out on the network, the global variable + uip_len is set to a value > 0. */ + + if(uip_len > 0) + { + uip_arp_out(); + cs8900a_send(); + } + } + + #if UIP_UDP + for(i = 0; i < UIP_UDP_CONNS; i++) + { + uip_udp_periodic(i); + + /* If the above function invocation resulted in data that + should be sent out on the network, the global variable + uip_len is set to a value > 0. */ + + if(uip_len > 0) + { + uip_arp_out(); + tapdev_send(); + } + } + #endif /* UIP_UDP */ + + /* Call the ARP timer function every 10 seconds. */ + if(++arptimer == 20) + { + uip_arp_timer(); + arptimer = 0; + } + } + else + { + vTaskDelay( uipSHORT_DELAY ); + } } + } +} +/*-----------------------------------------------------------------------------------*/ + + + + diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/uip.c b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/uip.c new file mode 100644 index 000000000..3ef7e8d6c --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/uip.c @@ -0,0 +1,1509 @@ +/** + * \addtogroup uip + * @{ + */ + +/** + * \file + * The uIP TCP/IP stack code. + * \author Adam Dunkels + */ + +/* + * Copyright (c) 2001-2003, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: uip.c,v 1.62.2.10 2003/10/07 13:23:01 adam Exp $ + * + */ + +/* +This is a small implementation of the IP and TCP protocols (as well as +some basic ICMP stuff). The implementation couples the IP, TCP and the +application layers very tightly. To keep the size of the compiled code +down, this code also features heavy usage of the goto statement. + +The principle is that we have a small buffer, called the uip_buf, in +which the device driver puts an incoming packet. The TCP/IP stack +parses the headers in the packet, and calls upon the application. If +the remote host has sent data to the application, this data is present +in the uip_buf and the application read the data from there. It is up +to the application to put this data into a byte stream if needed. The +application will not be fed with data that is out of sequence. + +If the application whishes to send data to the peer, it should put its +data into the uip_buf, 40 bytes from the start of the buffer. The +TCP/IP stack will calculate the checksums, and fill in the necessary +header fields and finally send the packet back to the peer. +*/ + +#include "uip.h" +#include "uipopt.h" +#include "uip_arch.h" + +/*-----------------------------------------------------------------------------------*/ +/* Variable definitions. */ + + +/* The IP address of this host. If it is defined to be fixed (by setting UIP_FIXEDADDR to 1 in uipopt.h), the address is set here. Otherwise, the address */ +#if UIP_FIXEDADDR > 0 +const u16_t uip_hostaddr[2] = + {HTONS((UIP_IPADDR0 << 8) | UIP_IPADDR1), + HTONS((UIP_IPADDR2 << 8) | UIP_IPADDR3)}; +const u16_t uip_arp_draddr[2] = + {HTONS((UIP_DRIPADDR0 << 8) | UIP_DRIPADDR1), + HTONS((UIP_DRIPADDR2 << 8) | UIP_DRIPADDR3)}; +const u16_t uip_arp_netmask[2] = + {HTONS((UIP_NETMASK0 << 8) | UIP_NETMASK1), + HTONS((UIP_NETMASK2 << 8) | UIP_NETMASK3)}; +#else +u16_t uip_hostaddr[2]; +u16_t uip_arp_draddr[2], uip_arp_netmask[2]; +#endif /* UIP_FIXEDADDR */ + +u8_t uip_buf[UIP_BUFSIZE+2]; /* The packet buffer that contains + incoming packets. */ +volatile u8_t *uip_appdata; /* The uip_appdata pointer points to + application data. */ +volatile u8_t *uip_sappdata; /* The uip_appdata pointer points to the + application data which is to be sent. */ +#if UIP_URGDATA > 0 +volatile u8_t *uip_urgdata; /* The uip_urgdata pointer points to + urgent data (out-of-band data), if + present. */ +volatile u8_t uip_urglen, uip_surglen; +#endif /* UIP_URGDATA > 0 */ + +volatile u16_t uip_len, uip_slen; + /* The uip_len is either 8 or 16 bits, + depending on the maximum packet + size. */ + +volatile u8_t uip_flags; /* The uip_flags variable is used for + communication between the TCP/IP stack + and the application program. */ +struct uip_conn *uip_conn; /* uip_conn always points to the current + connection. */ + +struct uip_conn uip_conns[UIP_CONNS]; + /* The uip_conns array holds all TCP + connections. */ +u16_t uip_listenports[UIP_LISTENPORTS]; + /* The uip_listenports list all currently + listning ports. */ +#if UIP_UDP +struct uip_udp_conn *uip_udp_conn; +struct uip_udp_conn uip_udp_conns[UIP_UDP_CONNS]; +#endif /* UIP_UDP */ + + +static u16_t ipid; /* Ths ipid variable is an increasing + number that is used for the IP ID + field. */ + +static u8_t iss[4]; /* The iss variable is used for the TCP + initial sequence number. */ + +#if UIP_ACTIVE_OPEN +static u16_t lastport; /* Keeps track of the last port used for + a new connection. */ +#endif /* UIP_ACTIVE_OPEN */ + +/* Temporary variables. */ +volatile u8_t uip_acc32[4]; +static u8_t c, opt; +static u16_t tmp16; + +/* Structures and definitions. */ +#define TCP_FIN 0x01 +#define TCP_SYN 0x02 +#define TCP_RST 0x04 +#define TCP_PSH 0x08 +#define TCP_ACK 0x10 +#define TCP_URG 0x20 +#define TCP_CTL 0x3f + +#define ICMP_ECHO_REPLY 0 +#define ICMP_ECHO 8 + +/* Macros. */ +#define BUF ((uip_tcpip_hdr *)&uip_buf[UIP_LLH_LEN]) +#define FBUF ((uip_tcpip_hdr *)&uip_reassbuf[0]) +#define ICMPBUF ((uip_icmpip_hdr *)&uip_buf[UIP_LLH_LEN]) +#define UDPBUF ((uip_udpip_hdr *)&uip_buf[UIP_LLH_LEN]) + +#if UIP_STATISTICS == 1 +struct uip_stats uip_stat; +#define UIP_STAT(s) s +#else +#define UIP_STAT(s) +#endif /* UIP_STATISTICS == 1 */ + +#if UIP_LOGGING == 1 +#include +void uip_log(char *msg); +#define UIP_LOG(m) uip_log(m) +#else +#define UIP_LOG(m) +#endif /* UIP_LOGGING == 1 */ + +/*-----------------------------------------------------------------------------------*/ +void +uip_init(void) +{ + for(c = 0; c < UIP_LISTENPORTS; ++c) { + uip_listenports[c] = 0; + } + for(c = 0; c < UIP_CONNS; ++c) { + uip_conns[c].tcpstateflags = CLOSED; + } +#if UIP_ACTIVE_OPEN + lastport = 1024; +#endif /* UIP_ACTIVE_OPEN */ + +#if UIP_UDP + for(c = 0; c < UIP_UDP_CONNS; ++c) { + uip_udp_conns[c].lport = 0; + } +#endif /* UIP_UDP */ + + + /* IPv4 initialization. */ +#if UIP_FIXEDADDR == 0 + uip_hostaddr[0] = uip_hostaddr[1] = 0; +#endif /* UIP_FIXEDADDR */ + +} +/*-----------------------------------------------------------------------------------*/ +#if UIP_ACTIVE_OPEN +struct uip_conn * +uip_connect(u16_t *ripaddr, u16_t rport) +{ + register struct uip_conn *conn, *cconn; + + /* Find an unused local port. */ + again: + ++lastport; + + if(lastport >= 32000) { + lastport = 4096; + } + + /* Check if this port is already in use, and if so try to find + another one. */ + for(c = 0; c < UIP_CONNS; ++c) { + conn = &uip_conns[c]; + if(conn->tcpstateflags != CLOSED && + conn->lport == htons(lastport)) { + goto again; + } + } + + + conn = 0; + for(c = 0; c < UIP_CONNS; ++c) { + cconn = &uip_conns[c]; + if(cconn->tcpstateflags == CLOSED) { + conn = cconn; + break; + } + if(cconn->tcpstateflags == TIME_WAIT) { + if(conn == 0 || + cconn->timer > uip_conn->timer) { + conn = cconn; + } + } + } + + if(conn == 0) { + return 0; + } + + conn->tcpstateflags = SYN_SENT; + + conn->snd_nxt[0] = iss[0]; + conn->snd_nxt[1] = iss[1]; + conn->snd_nxt[2] = iss[2]; + conn->snd_nxt[3] = iss[3]; + + conn->initialmss = conn->mss = UIP_TCP_MSS; + + conn->len = 1; /* TCP length of the SYN is one. */ + conn->nrtx = 0; + conn->timer = 1; /* Send the SYN next time around. */ + conn->rto = UIP_RTO; + conn->sa = 0; + conn->sv = 16; + conn->lport = htons(lastport); + conn->rport = rport; + conn->ripaddr[0] = ripaddr[0]; + conn->ripaddr[1] = ripaddr[1]; + + return conn; +} +#endif /* UIP_ACTIVE_OPEN */ +/*-----------------------------------------------------------------------------------*/ +#if UIP_UDP +struct uip_udp_conn * +uip_udp_new(u16_t *ripaddr, u16_t rport) +{ + register struct uip_udp_conn *conn; + + /* Find an unused local port. */ + again: + ++lastport; + + if(lastport >= 32000) { + lastport = 4096; + } + + for(c = 0; c < UIP_UDP_CONNS; ++c) { + if(uip_udp_conns[c].lport == lastport) { + goto again; + } + } + + + conn = 0; + for(c = 0; c < UIP_UDP_CONNS; ++c) { + if(uip_udp_conns[c].lport == 0) { + conn = &uip_udp_conns[c]; + break; + } + } + + if(conn == 0) { + return 0; + } + + conn->lport = HTONS(lastport); + conn->rport = HTONS(rport); + conn->ripaddr[0] = ripaddr[0]; + conn->ripaddr[1] = ripaddr[1]; + + return conn; +} +#endif /* UIP_UDP */ +/*-----------------------------------------------------------------------------------*/ +void +uip_unlisten(u16_t port) +{ + for(c = 0; c < UIP_LISTENPORTS; ++c) { + if(uip_listenports[c] == port) { + uip_listenports[c] = 0; + return; + } + } +} +/*-----------------------------------------------------------------------------------*/ +void +uip_listen(u16_t port) +{ + for(c = 0; c < UIP_LISTENPORTS; ++c) { + if(uip_listenports[c] == 0) { + uip_listenports[c] = port; + return; + } + } +} +/*-----------------------------------------------------------------------------------*/ +/* XXX: IP fragment reassembly: not well-tested. */ + +#if UIP_REASSEMBLY +#define UIP_REASS_BUFSIZE (UIP_BUFSIZE - UIP_LLH_LEN) +static u8_t uip_reassbuf[UIP_REASS_BUFSIZE]; +static u8_t uip_reassbitmap[UIP_REASS_BUFSIZE / (8 * 8)]; +static const u8_t bitmap_bits[8] = {0xff, 0x7f, 0x3f, 0x1f, + 0x0f, 0x07, 0x03, 0x01}; +static u16_t uip_reasslen; +static u8_t uip_reassflags; +#define UIP_REASS_FLAG_LASTFRAG 0x01 +static u8_t uip_reasstmr; + +#define IP_HLEN 20 +#define IP_MF 0x20 + +static u8_t +uip_reass(void) +{ + u16_t offset, len; + u16_t i; + + /* If ip_reasstmr is zero, no packet is present in the buffer, so we + write the IP header of the fragment into the reassembly + buffer. The timer is updated with the maximum age. */ + if(uip_reasstmr == 0) { + memcpy(uip_reassbuf, &BUF->vhl, IP_HLEN); + uip_reasstmr = UIP_REASS_MAXAGE; + uip_reassflags = 0; + /* Clear the bitmap. */ + memset(uip_reassbitmap, sizeof(uip_reassbitmap), 0); + } + + /* Check if the incoming fragment matches the one currently present + in the reasembly buffer. If so, we proceed with copying the + fragment into the buffer. */ + if(BUF->srcipaddr[0] == FBUF->srcipaddr[0] && + BUF->srcipaddr[1] == FBUF->srcipaddr[1] && + BUF->destipaddr[0] == FBUF->destipaddr[0] && + BUF->destipaddr[1] == FBUF->destipaddr[1] && + BUF->ipid[0] == FBUF->ipid[0] && + BUF->ipid[1] == FBUF->ipid[1]) { + + len = (BUF->len[0] << 8) + BUF->len[1] - (BUF->vhl & 0x0f) * 4; + offset = (((BUF->ipoffset[0] & 0x3f) << 8) + BUF->ipoffset[1]) * 8; + + /* If the offset or the offset + fragment length overflows the + reassembly buffer, we discard the entire packet. */ + if(offset > UIP_REASS_BUFSIZE || + offset + len > UIP_REASS_BUFSIZE) { + uip_reasstmr = 0; + goto nullreturn; + } + + /* Copy the fragment into the reassembly buffer, at the right + offset. */ + memcpy(&uip_reassbuf[IP_HLEN + offset], + (char *)BUF + (int)((BUF->vhl & 0x0f) * 4), + len); + + /* Update the bitmap. */ + if(offset / (8 * 8) == (offset + len) / (8 * 8)) { + /* If the two endpoints are in the same byte, we only update + that byte. */ + + uip_reassbitmap[offset / (8 * 8)] |= + bitmap_bits[(offset / 8 ) & 7] & + ~bitmap_bits[((offset + len) / 8 ) & 7]; + } else { + /* If the two endpoints are in different bytes, we update the + bytes in the endpoints and fill the stuff inbetween with + 0xff. */ + uip_reassbitmap[offset / (8 * 8)] |= + bitmap_bits[(offset / 8 ) & 7]; + for(i = 1 + offset / (8 * 8); i < (offset + len) / (8 * 8); ++i) { + uip_reassbitmap[i] = 0xff; + } + uip_reassbitmap[(offset + len) / (8 * 8)] |= + ~bitmap_bits[((offset + len) / 8 ) & 7]; + } + + /* If this fragment has the More Fragments flag set to zero, we + know that this is the last fragment, so we can calculate the + size of the entire packet. We also set the + IP_REASS_FLAG_LASTFRAG flag to indicate that we have received + the final fragment. */ + + if((BUF->ipoffset[0] & IP_MF) == 0) { + uip_reassflags |= UIP_REASS_FLAG_LASTFRAG; + uip_reasslen = offset + len; + } + + /* Finally, we check if we have a full packet in the buffer. We do + this by checking if we have the last fragment and if all bits + in the bitmap are set. */ + if(uip_reassflags & UIP_REASS_FLAG_LASTFRAG) { + /* Check all bytes up to and including all but the last byte in + the bitmap. */ + for(i = 0; i < uip_reasslen / (8 * 8) - 1; ++i) { + if(uip_reassbitmap[i] != 0xff) { + goto nullreturn; + } + } + /* Check the last byte in the bitmap. It should contain just the + right amount of bits. */ + if(uip_reassbitmap[uip_reasslen / (8 * 8)] != + (u8_t)~bitmap_bits[uip_reasslen / 8 & 7]) { + goto nullreturn; + } + + /* If we have come this far, we have a full packet in the + buffer, so we allocate a pbuf and copy the packet into it. We + also reset the timer. */ + uip_reasstmr = 0; + memcpy(BUF, FBUF, uip_reasslen); + + /* Pretend to be a "normal" (i.e., not fragmented) IP packet + from now on. */ + BUF->ipoffset[0] = BUF->ipoffset[1] = 0; + BUF->len[0] = uip_reasslen >> 8; + BUF->len[1] = uip_reasslen & 0xff; + BUF->ipchksum = 0; + BUF->ipchksum = ~(uip_ipchksum()); + + return uip_reasslen; + } + } + + nullreturn: + return 0; +} +#endif /* UIP_REASSEMBL */ +/*-----------------------------------------------------------------------------------*/ +static void +uip_add_rcv_nxt(u16_t n) +{ + uip_add32(uip_conn->rcv_nxt, n); + uip_conn->rcv_nxt[0] = uip_acc32[0]; + uip_conn->rcv_nxt[1] = uip_acc32[1]; + uip_conn->rcv_nxt[2] = uip_acc32[2]; + uip_conn->rcv_nxt[3] = uip_acc32[3]; +} +/*-----------------------------------------------------------------------------------*/ +void +uip_process(u8_t flag) +{ + register struct uip_conn *uip_connr = uip_conn; + + uip_appdata = &uip_buf[40 + UIP_LLH_LEN]; + + + /* Check if we were invoked because of the perodic timer fireing. */ + if(flag == UIP_TIMER) { +#if UIP_REASSEMBLY + if(uip_reasstmr != 0) { + --uip_reasstmr; + } +#endif /* UIP_REASSEMBLY */ + /* Increase the initial sequence number. */ + if(++iss[3] == 0) { + if(++iss[2] == 0) { + if(++iss[1] == 0) { + ++iss[0]; + } + } + } + uip_len = 0; + if(uip_connr->tcpstateflags == TIME_WAIT || + uip_connr->tcpstateflags == FIN_WAIT_2) { + ++(uip_connr->timer); + if(uip_connr->timer == UIP_TIME_WAIT_TIMEOUT) { + uip_connr->tcpstateflags = CLOSED; + } + } else if(uip_connr->tcpstateflags != CLOSED) { + /* If the connection has outstanding data, we increase the + connection's timer and see if it has reached the RTO value + in which case we retransmit. */ + if(uip_outstanding(uip_connr)) { + if(uip_connr->timer-- == 0) { + if(uip_connr->nrtx == UIP_MAXRTX || + ((uip_connr->tcpstateflags == SYN_SENT || + uip_connr->tcpstateflags == SYN_RCVD) && + uip_connr->nrtx == UIP_MAXSYNRTX)) { + uip_connr->tcpstateflags = CLOSED; + + /* We call UIP_APPCALL() with uip_flags set to + UIP_TIMEDOUT to inform the application that the + connection has timed out. */ + uip_flags = UIP_TIMEDOUT; + UIP_APPCALL(); + + /* We also send a reset packet to the remote host. */ + BUF->flags = TCP_RST | TCP_ACK; + goto tcp_send_nodata; + } + + /* Exponential backoff. */ + uip_connr->timer = UIP_RTO << (uip_connr->nrtx > 4? + 4: + uip_connr->nrtx); + ++(uip_connr->nrtx); + + /* Ok, so we need to retransmit. We do this differently + depending on which state we are in. In ESTABLISHED, we + call upon the application so that it may prepare the + data for the retransmit. In SYN_RCVD, we resend the + SYNACK that we sent earlier and in LAST_ACK we have to + retransmit our FINACK. */ + UIP_STAT(++uip_stat.tcp.rexmit); + switch(uip_connr->tcpstateflags & TS_MASK) { + case SYN_RCVD: + /* In the SYN_RCVD state, we should retransmit our + SYNACK. */ + goto tcp_send_synack; + +#if UIP_ACTIVE_OPEN + case SYN_SENT: + /* In the SYN_SENT state, we retransmit out SYN. */ + BUF->flags = 0; + goto tcp_send_syn; +#endif /* UIP_ACTIVE_OPEN */ + + case ESTABLISHED: + /* In the ESTABLISHED state, we call upon the application + to do the actual retransmit after which we jump into + the code for sending out the packet (the apprexmit + label). */ + uip_len = 0; + uip_slen = 0; + uip_flags = UIP_REXMIT; + UIP_APPCALL(); + goto apprexmit; + + case FIN_WAIT_1: + case CLOSING: + case LAST_ACK: + /* In all these states we should retransmit a FINACK. */ + goto tcp_send_finack; + + } + } + } else if((uip_connr->tcpstateflags & TS_MASK) == ESTABLISHED) { + /* If there was no need for a retransmission, we poll the + application for new data. */ + uip_len = 0; + uip_slen = 0; + uip_flags = UIP_POLL; + UIP_APPCALL(); + goto appsend; + } + } + goto drop; + } +#if UIP_UDP + if(flag == UIP_UDP_TIMER) { + if(uip_udp_conn->lport != 0) { + uip_appdata = &uip_buf[UIP_LLH_LEN + 28]; + uip_len = uip_slen = 0; + uip_flags = UIP_POLL; + UIP_UDP_APPCALL(); + goto udp_send; + } else { + goto drop; + } + } +#endif + + /* This is where the input processing starts. */ + UIP_STAT(++uip_stat.ip.recv); + + + /* Start of IPv4 input header processing code. */ + + /* Check validity of the IP header. */ + if(BUF->vhl != 0x45) { /* IP version and header length. */ + UIP_STAT(++uip_stat.ip.drop); + UIP_STAT(++uip_stat.ip.vhlerr); + UIP_LOG("ip: invalid version or header length."); + goto drop; + } + + /* Check the size of the packet. If the size reported to us in + uip_len doesn't match the size reported in the IP header, there + has been a transmission error and we drop the packet. */ + + if(BUF->len[0] != (uip_len >> 8)) { /* IP length, high byte. */ + uip_len = (uip_len & 0xff) | (BUF->len[0] << 8); + } + if(BUF->len[1] != (uip_len & 0xff)) { /* IP length, low byte. */ + uip_len = (uip_len & 0xff00) | BUF->len[1]; + } + + /* Check the fragment flag. */ + if((BUF->ipoffset[0] & 0x3f) != 0 || + BUF->ipoffset[1] != 0) { +#if UIP_REASSEMBLY + uip_len = uip_reass(); + if(uip_len == 0) { + goto drop; + } +#else + UIP_STAT(++uip_stat.ip.drop); + UIP_STAT(++uip_stat.ip.fragerr); + UIP_LOG("ip: fragment dropped."); + goto drop; +#endif /* UIP_REASSEMBLY */ + } + + /* If we are configured to use ping IP address configuration and + hasn't been assigned an IP address yet, we accept all ICMP + packets. */ +#if UIP_PINGADDRCONF + if((uip_hostaddr[0] | uip_hostaddr[1]) == 0) { + if(BUF->proto == UIP_PROTO_ICMP) { + UIP_LOG("ip: possible ping config packet received."); + goto icmp_input; + } else { + UIP_LOG("ip: packet dropped since no address assigned."); + goto drop; + } + } +#endif /* UIP_PINGADDRCONF */ + + /* Check if the packet is destined for our IP address. */ + if(BUF->destipaddr[0] != uip_hostaddr[0]) { + UIP_STAT(++uip_stat.ip.drop); + UIP_LOG("ip: packet not for us."); + goto drop; + } + if(BUF->destipaddr[1] != uip_hostaddr[1]) { + UIP_STAT(++uip_stat.ip.drop); + UIP_LOG("ip: packet not for us."); + goto drop; + } + +#if 0 + // IP checksum is wrong through Netgear DSL router + if (uip_ipchksum() != 0xffff) { /* Compute and check the IP header + checksum. */ + UIP_STAT(++uip_stat.ip.drop); + UIP_STAT(++uip_stat.ip.chkerr); + UIP_LOG("ip: bad checksum."); + goto drop; + } +#endif + + if(BUF->proto == UIP_PROTO_TCP) /* Check for TCP packet. If so, jump + to the tcp_input label. */ + goto tcp_input; + +#if UIP_UDP + if(BUF->proto == UIP_PROTO_UDP) + goto udp_input; +#endif /* UIP_UDP */ + + if(BUF->proto != UIP_PROTO_ICMP) { /* We only allow ICMP packets from + here. */ + UIP_STAT(++uip_stat.ip.drop); + UIP_STAT(++uip_stat.ip.protoerr); + UIP_LOG("ip: neither tcp nor icmp."); + goto drop; + } + + icmp_input: + UIP_STAT(++uip_stat.icmp.recv); + + /* ICMP echo (i.e., ping) processing. This is simple, we only change + the ICMP type from ECHO to ECHO_REPLY and adjust the ICMP + checksum before we return the packet. */ + if(ICMPBUF->type != ICMP_ECHO) { + UIP_STAT(++uip_stat.icmp.drop); + UIP_STAT(++uip_stat.icmp.typeerr); + UIP_LOG("icmp: not icmp echo."); + goto drop; + } + + /* If we are configured to use ping IP address assignment, we use + the destination IP address of this ping packet and assign it to + ourself. */ +#if UIP_PINGADDRCONF + if((uip_hostaddr[0] | uip_hostaddr[1]) == 0) { + uip_hostaddr[0] = BUF->destipaddr[0]; + uip_hostaddr[1] = BUF->destipaddr[1]; + } +#endif /* UIP_PINGADDRCONF */ + + ICMPBUF->type = ICMP_ECHO_REPLY; + + if(ICMPBUF->icmpchksum >= HTONS(0xffff - (ICMP_ECHO << 8))) { + ICMPBUF->icmpchksum += HTONS(ICMP_ECHO << 8) + 1; + } else { + ICMPBUF->icmpchksum += HTONS(ICMP_ECHO << 8); + } + + /* Swap IP addresses. */ + tmp16 = BUF->destipaddr[0]; + BUF->destipaddr[0] = BUF->srcipaddr[0]; + BUF->srcipaddr[0] = tmp16; + tmp16 = BUF->destipaddr[1]; + BUF->destipaddr[1] = BUF->srcipaddr[1]; + BUF->srcipaddr[1] = tmp16; + + UIP_STAT(++uip_stat.icmp.sent); + goto send; + + /* End of IPv4 input header processing code. */ + + +#if UIP_UDP + /* UDP input processing. */ + udp_input: + /* UDP processing is really just a hack. We don't do anything to the + UDP/IP headers, but let the UDP application do all the hard + work. If the application sets uip_slen, it has a packet to + send. */ +#if UIP_UDP_CHECKSUMS + if(uip_udpchksum() != 0xffff) { + UIP_STAT(++uip_stat.udp.drop); + UIP_STAT(++uip_stat.udp.chkerr); + UIP_LOG("udp: bad checksum."); + goto drop; + } +#endif /* UIP_UDP_CHECKSUMS */ + + /* Demultiplex this UDP packet between the UDP "connections". */ + for(uip_udp_conn = &uip_udp_conns[0]; + uip_udp_conn < &uip_udp_conns[UIP_UDP_CONNS]; + ++uip_udp_conn) { + if(uip_udp_conn->lport != 0 && + UDPBUF->destport == uip_udp_conn->lport && + (uip_udp_conn->rport == 0 || + UDPBUF->srcport == uip_udp_conn->rport) && + BUF->srcipaddr[0] == uip_udp_conn->ripaddr[0] && + BUF->srcipaddr[1] == uip_udp_conn->ripaddr[1]) { + goto udp_found; + } + } + goto drop; + + udp_found: + uip_len = uip_len - 28; + uip_appdata = &uip_buf[UIP_LLH_LEN + 28]; + uip_flags = UIP_NEWDATA; + uip_slen = 0; + UIP_UDP_APPCALL(); + udp_send: + if(uip_slen == 0) { + goto drop; + } + uip_len = uip_slen + 28; + + BUF->len[0] = (uip_len >> 8); + BUF->len[1] = (uip_len & 0xff); + + BUF->proto = UIP_PROTO_UDP; + + UDPBUF->udplen = HTONS(uip_slen + 8); + UDPBUF->udpchksum = 0; +#if UIP_UDP_CHECKSUMS + /* Calculate UDP checksum. */ + UDPBUF->udpchksum = ~(uip_udpchksum()); + if(UDPBUF->udpchksum == 0) { + UDPBUF->udpchksum = 0xffff; + } +#endif /* UIP_UDP_CHECKSUMS */ + + BUF->srcport = uip_udp_conn->lport; + BUF->destport = uip_udp_conn->rport; + + BUF->srcipaddr[0] = uip_hostaddr[0]; + BUF->srcipaddr[1] = uip_hostaddr[1]; + BUF->destipaddr[0] = uip_udp_conn->ripaddr[0]; + BUF->destipaddr[1] = uip_udp_conn->ripaddr[1]; + + uip_appdata = &uip_buf[UIP_LLH_LEN + 40]; + goto ip_send_nolen; +#endif /* UIP_UDP */ + + /* TCP input processing. */ + tcp_input: + UIP_STAT(++uip_stat.tcp.recv); + + /* Start of TCP input header processing code. */ + +#if 1 // FIXME + if(uip_tcpchksum() != 0xffff) { /* Compute and check the TCP + checksum. */ + UIP_STAT(++uip_stat.tcp.drop); + UIP_STAT(++uip_stat.tcp.chkerr); + UIP_LOG("tcp: bad checksum."); + goto drop; + } +#endif + + /* Demultiplex this segment. */ + /* First check any active connections. */ + for(uip_connr = &uip_conns[0]; uip_connr < &uip_conns[UIP_CONNS]; ++uip_connr) { + if(uip_connr->tcpstateflags != CLOSED && + BUF->destport == uip_connr->lport && + BUF->srcport == uip_connr->rport && + BUF->srcipaddr[0] == uip_connr->ripaddr[0] && + BUF->srcipaddr[1] == uip_connr->ripaddr[1]) { + goto found; + } + } + + /* If we didn't find and active connection that expected the packet, + either this packet is an old duplicate, or this is a SYN packet + destined for a connection in LISTEN. If the SYN flag isn't set, + it is an old packet and we send a RST. */ + if((BUF->flags & TCP_CTL) != TCP_SYN) + goto reset; + + tmp16 = BUF->destport; + /* Next, check listening connections. */ + for(c = 0; c < UIP_LISTENPORTS; ++c) { + if(tmp16 == uip_listenports[c]) + goto found_listen; + } + + /* No matching connection found, so we send a RST packet. */ + UIP_STAT(++uip_stat.tcp.synrst); + reset: + + /* We do not send resets in response to resets. */ + if(BUF->flags & TCP_RST) + goto drop; + + UIP_STAT(++uip_stat.tcp.rst); + + BUF->flags = TCP_RST | TCP_ACK; + uip_len = 40; + BUF->tcpoffset = 5 << 4; + + /* Flip the seqno and ackno fields in the TCP header. */ + c = BUF->seqno[3]; + BUF->seqno[3] = BUF->ackno[3]; + BUF->ackno[3] = c; + + c = BUF->seqno[2]; + BUF->seqno[2] = BUF->ackno[2]; + BUF->ackno[2] = c; + + c = BUF->seqno[1]; + BUF->seqno[1] = BUF->ackno[1]; + BUF->ackno[1] = c; + + c = BUF->seqno[0]; + BUF->seqno[0] = BUF->ackno[0]; + BUF->ackno[0] = c; + + /* We also have to increase the sequence number we are + acknowledging. If the least significant byte overflowed, we need + to propagate the carry to the other bytes as well. */ + if(++BUF->ackno[3] == 0) { + if(++BUF->ackno[2] == 0) { + if(++BUF->ackno[1] == 0) { + ++BUF->ackno[0]; + } + } + } + + /* Swap port numbers. */ + tmp16 = BUF->srcport; + BUF->srcport = BUF->destport; + BUF->destport = tmp16; + + /* Swap IP addresses. */ + tmp16 = BUF->destipaddr[0]; + BUF->destipaddr[0] = BUF->srcipaddr[0]; + BUF->srcipaddr[0] = tmp16; + tmp16 = BUF->destipaddr[1]; + BUF->destipaddr[1] = BUF->srcipaddr[1]; + BUF->srcipaddr[1] = tmp16; + + + /* And send out the RST packet! */ + goto tcp_send_noconn; + + /* This label will be jumped to if we matched the incoming packet + with a connection in LISTEN. In that case, we should create a new + connection and send a SYNACK in return. */ + found_listen: + /* First we check if there are any connections avaliable. Unused + connections are kept in the same table as used connections, but + unused ones have the tcpstate set to CLOSED. Also, connections in + TIME_WAIT are kept track of and we'll use the oldest one if no + CLOSED connections are found. Thanks to Eddie C. Dost for a very + nice algorithm for the TIME_WAIT search. */ + uip_connr = 0; + for(c = 0; c < UIP_CONNS; ++c) { + if(uip_conns[c].tcpstateflags == CLOSED) { + uip_connr = &uip_conns[c]; + break; + } + if(uip_conns[c].tcpstateflags == TIME_WAIT) { + if(uip_connr == 0 || + uip_conns[c].timer > uip_connr->timer) { + uip_connr = &uip_conns[c]; + } + } + } + + if(uip_connr == 0) { + /* All connections are used already, we drop packet and hope that + the remote end will retransmit the packet at a time when we + have more spare connections. */ + UIP_STAT(++uip_stat.tcp.syndrop); + UIP_LOG("tcp: found no unused connections."); + goto drop; + } + uip_conn = uip_connr; + + /* Fill in the necessary fields for the new connection. */ + uip_connr->rto = uip_connr->timer = UIP_RTO; + uip_connr->sa = 0; + uip_connr->sv = 4; + uip_connr->nrtx = 0; + uip_connr->lport = BUF->destport; + uip_connr->rport = BUF->srcport; + uip_connr->ripaddr[0] = BUF->srcipaddr[0]; + uip_connr->ripaddr[1] = BUF->srcipaddr[1]; + uip_connr->tcpstateflags = SYN_RCVD; + + uip_connr->snd_nxt[0] = iss[0]; + uip_connr->snd_nxt[1] = iss[1]; + uip_connr->snd_nxt[2] = iss[2]; + uip_connr->snd_nxt[3] = iss[3]; + uip_connr->len = 1; + + /* rcv_nxt should be the seqno from the incoming packet + 1. */ + uip_connr->rcv_nxt[3] = BUF->seqno[3]; + uip_connr->rcv_nxt[2] = BUF->seqno[2]; + uip_connr->rcv_nxt[1] = BUF->seqno[1]; + uip_connr->rcv_nxt[0] = BUF->seqno[0]; + uip_add_rcv_nxt(1); + + /* Parse the TCP MSS option, if present. */ + if((BUF->tcpoffset & 0xf0) > 0x50) { + for(c = 0; c < ((BUF->tcpoffset >> 4) - 5) << 2 ;) { + opt = uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + c]; + if(opt == 0x00) { + /* End of options. */ + break; + } else if(opt == 0x01) { + ++c; + /* NOP option. */ + } else if(opt == 0x02 && + uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0x04) { + /* An MSS option with the right option length. */ + tmp16 = ((u16_t)uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 2 + c] << 8) | + (u16_t)uip_buf[40 + UIP_LLH_LEN + 3 + c]; + uip_connr->initialmss = uip_connr->mss = + tmp16 > UIP_TCP_MSS? UIP_TCP_MSS: tmp16; + + /* And we are done processing options. */ + break; + } else { + /* All other options have a length field, so that we easily + can skip past them. */ + if(uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0) { + /* If the length field is zero, the options are malformed + and we don't process them further. */ + break; + } + c += uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c]; + } + } + } + + /* Our response will be a SYNACK. */ +#if UIP_ACTIVE_OPEN + tcp_send_synack: + BUF->flags = TCP_ACK; + + tcp_send_syn: + BUF->flags |= TCP_SYN; +#else /* UIP_ACTIVE_OPEN */ + tcp_send_synack: + BUF->flags = TCP_SYN | TCP_ACK; +#endif /* UIP_ACTIVE_OPEN */ + + /* We send out the TCP Maximum Segment Size option with our + SYNACK. */ + BUF->optdata[0] = 2; + BUF->optdata[1] = 4; + BUF->optdata[2] = (UIP_TCP_MSS) / 256; + BUF->optdata[3] = (UIP_TCP_MSS) & 255; + uip_len = 44; + BUF->tcpoffset = 6 << 4; + goto tcp_send; + + /* This label will be jumped to if we found an active connection. */ + found: + uip_conn = uip_connr; + uip_flags = 0; + + /* We do a very naive form of TCP reset processing; we just accept + any RST and kill our connection. We should in fact check if the + sequence number of this reset is wihtin our advertised window + before we accept the reset. */ + if(BUF->flags & TCP_RST) { + uip_connr->tcpstateflags = CLOSED; + UIP_LOG("tcp: got reset, aborting connection."); + uip_flags = UIP_ABORT; + UIP_APPCALL(); + goto drop; + } + /* Calculated the length of the data, if the application has sent + any data to us. */ + c = (BUF->tcpoffset >> 4) << 2; + /* uip_len will contain the length of the actual TCP data. This is + calculated by subtracing the length of the TCP header (in + c) and the length of the IP header (20 bytes). */ + uip_len = uip_len - c - 20; + + /* First, check if the sequence number of the incoming packet is + what we're expecting next. If not, we send out an ACK with the + correct numbers in. */ + if(uip_len > 0 && + (BUF->seqno[0] != uip_connr->rcv_nxt[0] || + BUF->seqno[1] != uip_connr->rcv_nxt[1] || + BUF->seqno[2] != uip_connr->rcv_nxt[2] || + BUF->seqno[3] != uip_connr->rcv_nxt[3])) { + goto tcp_send_ack; + } + + /* Next, check if the incoming segment acknowledges any outstanding + data. If so, we update the sequence number, reset the length of + the outstanding data, calculate RTT estimations, and reset the + retransmission timer. */ + if((BUF->flags & TCP_ACK) && uip_outstanding(uip_connr)) { + uip_add32(uip_connr->snd_nxt, uip_connr->len); + if(BUF->ackno[0] == uip_acc32[0] && + BUF->ackno[1] == uip_acc32[1] && + BUF->ackno[2] == uip_acc32[2] && + BUF->ackno[3] == uip_acc32[3]) { + /* Update sequence number. */ + uip_connr->snd_nxt[0] = uip_acc32[0]; + uip_connr->snd_nxt[1] = uip_acc32[1]; + uip_connr->snd_nxt[2] = uip_acc32[2]; + uip_connr->snd_nxt[3] = uip_acc32[3]; + + + /* Do RTT estimation, unless we have done retransmissions. */ + if(uip_connr->nrtx == 0) { + signed char m; + m = uip_connr->rto - uip_connr->timer; + /* This is taken directly from VJs original code in his paper */ + m = m - (uip_connr->sa >> 3); + uip_connr->sa += m; + if(m < 0) { + m = -m; + } + m = m - (uip_connr->sv >> 2); + uip_connr->sv += m; + uip_connr->rto = (uip_connr->sa >> 3) + uip_connr->sv; + + } + /* Set the acknowledged flag. */ + uip_flags = UIP_ACKDATA; + /* Reset the retransmission timer. */ + uip_connr->timer = uip_connr->rto; + } + + } + + /* Do different things depending on in what state the connection is. */ + switch(uip_connr->tcpstateflags & TS_MASK) { + /* CLOSED and LISTEN are not handled here. CLOSE_WAIT is not + implemented, since we force the application to close when the + peer sends a FIN (hence the application goes directly from + ESTABLISHED to LAST_ACK). */ + case SYN_RCVD: + /* In SYN_RCVD we have sent out a SYNACK in response to a SYN, and + we are waiting for an ACK that acknowledges the data we sent + out the last time. Therefore, we want to have the UIP_ACKDATA + flag set. If so, we enter the ESTABLISHED state. */ + if(uip_flags & UIP_ACKDATA) { + uip_connr->tcpstateflags = ESTABLISHED; + uip_flags = UIP_CONNECTED; + uip_connr->len = 0; + if(uip_len > 0) { + uip_flags |= UIP_NEWDATA; + uip_add_rcv_nxt(uip_len); + } + uip_slen = 0; + UIP_APPCALL(); + goto appsend; + } + goto drop; +#if UIP_ACTIVE_OPEN + case SYN_SENT: + /* In SYN_SENT, we wait for a SYNACK that is sent in response to + our SYN. The rcv_nxt is set to sequence number in the SYNACK + plus one, and we send an ACK. We move into the ESTABLISHED + state. */ + if((uip_flags & UIP_ACKDATA) && + BUF->flags == (TCP_SYN | TCP_ACK)) { + + /* Parse the TCP MSS option, if present. */ + if((BUF->tcpoffset & 0xf0) > 0x50) { + for(c = 0; c < ((BUF->tcpoffset >> 4) - 5) << 2 ;) { + opt = uip_buf[40 + UIP_LLH_LEN + c]; + if(opt == 0x00) { + /* End of options. */ + break; + } else if(opt == 0x01) { + ++c; + /* NOP option. */ + } else if(opt == 0x02 && + uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0x04) { + /* An MSS option with the right option length. */ + tmp16 = (uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 2 + c] << 8) | + uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 3 + c]; + uip_connr->initialmss = + uip_connr->mss = tmp16 > UIP_TCP_MSS? UIP_TCP_MSS: tmp16; + + /* And we are done processing options. */ + break; + } else { + /* All other options have a length field, so that we easily + can skip past them. */ + if(uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0) { + /* If the length field is zero, the options are malformed + and we don't process them further. */ + break; + } + c += uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c]; + } + } + } + uip_connr->tcpstateflags = ESTABLISHED; + uip_connr->rcv_nxt[0] = BUF->seqno[0]; + uip_connr->rcv_nxt[1] = BUF->seqno[1]; + uip_connr->rcv_nxt[2] = BUF->seqno[2]; + uip_connr->rcv_nxt[3] = BUF->seqno[3]; + uip_add_rcv_nxt(1); + uip_flags = UIP_CONNECTED | UIP_NEWDATA; + uip_connr->len = 0; + uip_len = 0; + uip_slen = 0; + UIP_APPCALL(); + goto appsend; + } + goto reset; +#endif /* UIP_ACTIVE_OPEN */ + + case ESTABLISHED: + /* In the ESTABLISHED state, we call upon the application to feed + data into the uip_buf. If the UIP_ACKDATA flag is set, the + application should put new data into the buffer, otherwise we are + retransmitting an old segment, and the application should put that + data into the buffer. + + If the incoming packet is a FIN, we should close the connection on + this side as well, and we send out a FIN and enter the LAST_ACK + state. We require that there is no outstanding data; otherwise the + sequence numbers will be screwed up. */ + + if(BUF->flags & TCP_FIN) { + if(uip_outstanding(uip_connr)) { + goto drop; + } + uip_add_rcv_nxt(1 + uip_len); + uip_flags = UIP_CLOSE; + if(uip_len > 0) { + uip_flags |= UIP_NEWDATA; + } + UIP_APPCALL(); + uip_connr->len = 1; + uip_connr->tcpstateflags = LAST_ACK; + uip_connr->nrtx = 0; + tcp_send_finack: + BUF->flags = TCP_FIN | TCP_ACK; + goto tcp_send_nodata; + } + + /* Check the URG flag. If this is set, the segment carries urgent + data that we must pass to the application. */ + if(BUF->flags & TCP_URG) { +#if UIP_URGDATA > 0 + uip_urglen = (BUF->urgp[0] << 8) | BUF->urgp[1]; + if(uip_urglen > uip_len) { + /* There is more urgent data in the next segment to come. */ + uip_urglen = uip_len; + } + uip_add_rcv_nxt(uip_urglen); + uip_len -= uip_urglen; + uip_urgdata = uip_appdata; + uip_appdata += uip_urglen; + } else { + uip_urglen = 0; +#endif /* UIP_URGDATA > 0 */ + uip_appdata += (BUF->urgp[0] << 8) | BUF->urgp[1]; + uip_len -= (BUF->urgp[0] << 8) | BUF->urgp[1]; + } + + + /* If uip_len > 0 we have TCP data in the packet, and we flag this + by setting the UIP_NEWDATA flag and update the sequence number + we acknowledge. If the application has stopped the dataflow + using uip_stop(), we must not accept any data packets from the + remote host. */ + if(uip_len > 0 && !(uip_connr->tcpstateflags & UIP_STOPPED)) { + uip_flags |= UIP_NEWDATA; + uip_add_rcv_nxt(uip_len); + } + + /* Check if the available buffer space advertised by the other end + is smaller than the initial MSS for this connection. If so, we + set the current MSS to the window size to ensure that the + application does not send more data than the other end can + handle. + + If the remote host advertises a zero window, we set the MSS to + the initial MSS so that the application will send an entire MSS + of data. This data will not be acknowledged by the receiver, + and the application will retransmit it. This is called the + "persistent timer" and uses the retransmission mechanim. + */ + tmp16 = ((u16_t)BUF->wnd[0] << 8) + (u16_t)BUF->wnd[1]; + if(tmp16 > uip_connr->initialmss || + tmp16 == 0) { + tmp16 = uip_connr->initialmss; + } + uip_connr->mss = tmp16; + + /* If this packet constitutes an ACK for outstanding data (flagged + by the UIP_ACKDATA flag, we should call the application since it + might want to send more data. If the incoming packet had data + from the peer (as flagged by the UIP_NEWDATA flag), the + application must also be notified. + + When the application is called, the global variable uip_len + contains the length of the incoming data. The application can + access the incoming data through the global pointer + uip_appdata, which usually points 40 bytes into the uip_buf + array. + + If the application wishes to send any data, this data should be + put into the uip_appdata and the length of the data should be + put into uip_len. If the application don't have any data to + send, uip_len must be set to 0. */ + if(uip_flags & (UIP_NEWDATA | UIP_ACKDATA)) { + uip_slen = 0; + UIP_APPCALL(); + + appsend: + + if(uip_flags & UIP_ABORT) { + uip_slen = 0; + uip_connr->tcpstateflags = CLOSED; + BUF->flags = TCP_RST | TCP_ACK; + goto tcp_send_nodata; + } + + if(uip_flags & UIP_CLOSE) { + uip_slen = 0; + uip_connr->len = 1; + uip_connr->tcpstateflags = FIN_WAIT_1; + uip_connr->nrtx = 0; + BUF->flags = TCP_FIN | TCP_ACK; + goto tcp_send_nodata; + } + + /* If uip_slen > 0, the application has data to be sent. */ + if(uip_slen > 0) { + + /* If the connection has acknowledged data, the contents of + the ->len variable should be discarded. */ + if((uip_flags & UIP_ACKDATA) != 0) { + uip_connr->len = 0; + } + + /* If the ->len variable is non-zero the connection has + already data in transit and cannot send anymore right + now. */ + if(uip_connr->len == 0) { + + /* The application cannot send more than what is allowed by + the mss (the minumum of the MSS and the available + window). */ + if(uip_slen > uip_connr->mss) { + uip_slen = uip_connr->mss; + } + + /* Remember how much data we send out now so that we know + when everything has been acknowledged. */ + uip_connr->len = uip_slen; + } else { + + /* If the application already had unacknowledged data, we + make sure that the application does not send (i.e., + retransmit) out more than it previously sent out. */ + uip_slen = uip_connr->len; + } + } else { + uip_connr->len = 0; + } + uip_connr->nrtx = 0; + apprexmit: + uip_appdata = uip_sappdata; + + /* If the application has data to be sent, or if the incoming + packet had new data in it, we must send out a packet. */ + if(uip_slen > 0 && uip_connr->len > 0) { + /* Add the length of the IP and TCP headers. */ + uip_len = uip_connr->len + UIP_TCPIP_HLEN; + /* We always set the ACK flag in response packets. */ + BUF->flags = TCP_ACK | TCP_PSH; + /* Send the packet. */ + goto tcp_send_noopts; + } + /* If there is no data to send, just send out a pure ACK if + there is newdata. */ + if(uip_flags & UIP_NEWDATA) { + uip_len = UIP_TCPIP_HLEN; + BUF->flags = TCP_ACK; + goto tcp_send_noopts; + } + } + goto drop; + case LAST_ACK: + /* We can close this connection if the peer has acknowledged our + FIN. This is indicated by the UIP_ACKDATA flag. */ + if(uip_flags & UIP_ACKDATA) { + uip_connr->tcpstateflags = CLOSED; + uip_flags = UIP_CLOSE; + UIP_APPCALL(); + } + break; + + case FIN_WAIT_1: + /* The application has closed the connection, but the remote host + hasn't closed its end yet. Thus we do nothing but wait for a + FIN from the other side. */ + if(uip_len > 0) { + uip_add_rcv_nxt(uip_len); + } + if(BUF->flags & TCP_FIN) { + if(uip_flags & UIP_ACKDATA) { + uip_connr->tcpstateflags = TIME_WAIT; + uip_connr->timer = 0; + uip_connr->len = 0; + } else { + uip_connr->tcpstateflags = CLOSING; + } + uip_add_rcv_nxt(1); + uip_flags = UIP_CLOSE; + UIP_APPCALL(); + goto tcp_send_ack; + } else if(uip_flags & UIP_ACKDATA) { + uip_connr->tcpstateflags = FIN_WAIT_2; + uip_connr->len = 0; + goto drop; + } + if(uip_len > 0) { + goto tcp_send_ack; + } + goto drop; + + case FIN_WAIT_2: + if(uip_len > 0) { + uip_add_rcv_nxt(uip_len); + } + if(BUF->flags & TCP_FIN) { + uip_connr->tcpstateflags = TIME_WAIT; + uip_connr->timer = 0; + uip_add_rcv_nxt(1); + uip_flags = UIP_CLOSE; + UIP_APPCALL(); + goto tcp_send_ack; + } + if(uip_len > 0) { + goto tcp_send_ack; + } + goto drop; + + case TIME_WAIT: + goto tcp_send_ack; + + case CLOSING: + if(uip_flags & UIP_ACKDATA) { + uip_connr->tcpstateflags = TIME_WAIT; + uip_connr->timer = 0; + } + } + goto drop; + + + /* We jump here when we are ready to send the packet, and just want + to set the appropriate TCP sequence numbers in the TCP header. */ + tcp_send_ack: + BUF->flags = TCP_ACK; + tcp_send_nodata: + uip_len = 40; + tcp_send_noopts: + BUF->tcpoffset = 5 << 4; + tcp_send: + /* We're done with the input processing. We are now ready to send a + reply. Our job is to fill in all the fields of the TCP and IP + headers before calculating the checksum and finally send the + packet. */ + BUF->ackno[0] = uip_connr->rcv_nxt[0]; + BUF->ackno[1] = uip_connr->rcv_nxt[1]; + BUF->ackno[2] = uip_connr->rcv_nxt[2]; + BUF->ackno[3] = uip_connr->rcv_nxt[3]; + + BUF->seqno[0] = uip_connr->snd_nxt[0]; + BUF->seqno[1] = uip_connr->snd_nxt[1]; + BUF->seqno[2] = uip_connr->snd_nxt[2]; + BUF->seqno[3] = uip_connr->snd_nxt[3]; + + BUF->proto = UIP_PROTO_TCP; + + BUF->srcport = uip_connr->lport; + BUF->destport = uip_connr->rport; + + BUF->srcipaddr[0] = uip_hostaddr[0]; + BUF->srcipaddr[1] = uip_hostaddr[1]; + BUF->destipaddr[0] = uip_connr->ripaddr[0]; + BUF->destipaddr[1] = uip_connr->ripaddr[1]; + + + if(uip_connr->tcpstateflags & UIP_STOPPED) { + /* If the connection has issued uip_stop(), we advertise a zero + window so that the remote host will stop sending data. */ + BUF->wnd[0] = BUF->wnd[1] = 0; + } else { + BUF->wnd[0] = ((UIP_RECEIVE_WINDOW) >> 8); + BUF->wnd[1] = ((UIP_RECEIVE_WINDOW) & 0xff); + } + + tcp_send_noconn: + + BUF->len[0] = (uip_len >> 8); + BUF->len[1] = (uip_len & 0xff); + + /* Calculate TCP checksum. */ + BUF->tcpchksum = 0; + BUF->tcpchksum = ~(uip_tcpchksum()); + + ip_send_nolen: + + BUF->vhl = 0x45; + BUF->tos = 0; + BUF->ipoffset[0] = BUF->ipoffset[1] = 0; + BUF->ttl = UIP_TTL; + ++ipid; + BUF->ipid[0] = ipid >> 8; + BUF->ipid[1] = ipid & 0xff; + + /* Calculate IP checksum. */ + BUF->ipchksum = 0; + BUF->ipchksum = ~(uip_ipchksum()); + + UIP_STAT(++uip_stat.tcp.sent); + send: + UIP_STAT(++uip_stat.ip.sent); + /* Return and let the caller do the actual transmission. */ + return; + drop: + uip_len = 0; + return; +} +/*-----------------------------------------------------------------------------------*/ +u16_t +htons(u16_t val) +{ + return HTONS(val); +} +/*-----------------------------------------------------------------------------------*/ +/** @} */ diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/uip.h b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/uip.h new file mode 100644 index 000000000..f6367a261 --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/uip.h @@ -0,0 +1,1060 @@ +/** + * \addtogroup uip + * @{ + */ + +/** + * \file + * Header file for the uIP TCP/IP stack. + * \author Adam Dunkels + * + * The uIP TCP/IP stack header file contains definitions for a number + * of C macros that are used by uIP programs as well as internal uIP + * structures, TCP/IP header structures and function declarations. + * + */ + + +/* + * Copyright (c) 2001-2003, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: uip.h,v 1.36.2.7 2003/10/07 13:47:51 adam Exp $ + * + */ + +#ifndef __UIP_H__ +#define __UIP_H__ + +#include "uipopt.h" + +/*-----------------------------------------------------------------------------------*/ +/* First, the functions that should be called from the + * system. Initialization, the periodic timer and incoming packets are + * handled by the following three functions. + */ + +/** + * \defgroup uipconffunc uIP configuration functions + * @{ + * + * The uIP configuration functions are used for setting run-time + * parameters in uIP such as IP addresses. + */ + +/** + * Set the IP address of this host. + * + * The IP address is represented as a 4-byte array where the first + * octet of the IP address is put in the first member of the 4-byte + * array. + * + * \param addr A pointer to a 4-byte representation of the IP address. + * + * \hideinitializer + */ +#define uip_sethostaddr(addr) do { uip_hostaddr[0] = addr[0]; \ + uip_hostaddr[1] = addr[1]; } while(0) + +/** + * Get the IP address of this host. + * + * The IP address is represented as a 4-byte array where the first + * octet of the IP address is put in the first member of the 4-byte + * array. + * + * \param addr A pointer to a 4-byte array that will be filled in with + * the currently configured IP address. + * + * \hideinitializer + */ +#define uip_gethostaddr(addr) do { addr[0] = uip_hostaddr[0]; \ + addr[1] = uip_hostaddr[1]; } while(0) + +/** @} */ + +/** + * \defgroup uipinit uIP initialization functions + * @{ + * + * The uIP initialization functions are used for booting uIP. + */ + +/** + * uIP initialization function. + * + * This function should be called at boot up to initilize the uIP + * TCP/IP stack. + */ +void uip_init(void); + +/** @} */ + +/** + * \defgroup uipdevfunc uIP device driver functions + * @{ + * + * These functions are used by a network device driver for interacting + * with uIP. + */ + +/** + * Process an incoming packet. + * + * This function should be called when the device driver has received + * a packet from the network. The packet from the device driver must + * be present in the uip_buf buffer, and the length of the packet + * should be placed in the uip_len variable. + * + * When the function returns, there may be an outbound packet placed + * in the uip_buf packet buffer. If so, the uip_len variable is set to + * the length of the packet. If no packet is to be sent out, the + * uip_len variable is set to 0. + * + * The usual way of calling the function is presented by the source + * code below. + \code + uip_len = devicedriver_poll(); + if(uip_len > 0) { + uip_input(); + if(uip_len > 0) { + devicedriver_send(); + } + } + \endcode + * + * \note If you are writing a uIP device driver that needs ARP + * (Address Resolution Protocol), e.g., when running uIP over + * Ethernet, you will need to call the uIP ARP code before calling + * this function: + \code + #define BUF ((struct uip_eth_hdr *)&uip_buf[0]) + uip_len = ethernet_devicedrver_poll(); + if(uip_len > 0) { + if(BUF->type == HTONS(UIP_ETHTYPE_IP)) { + uip_arp_ipin(); + uip_input(); + if(uip_len > 0) { + uip_arp_out(); + ethernet_devicedriver_send(); + } + } else if(BUF->type == HTONS(UIP_ETHTYPE_ARP)) { + uip_arp_arpin(); + if(uip_len > 0) { + ethernet_devicedriver_send(); + } + } + \endcode + * + * \hideinitializer + */ +#define uip_input() uip_process(UIP_DATA) + +/** + * Periodic processing for a connection identified by its number. + * + * This function does the necessary periodic processing (timers, + * polling) for a uIP TCP conneciton, and should be called when the + * periodic uIP timer goes off. It should be called for every + * connection, regardless of whether they are open of closed. + * + * When the function returns, it may have an outbound packet waiting + * for service in the uIP packet buffer, and if so the uip_len + * variable is set to a value larger than zero. The device driver + * should be called to send out the packet. + * + * The ususal way of calling the function is through a for() loop like + * this: + \code + for(i = 0; i < UIP_CONNS; ++i) { + uip_periodic(i); + if(uip_len > 0) { + devicedriver_send(); + } + } + \endcode + * + * \note If you are writing a uIP device driver that needs ARP + * (Address Resolution Protocol), e.g., when running uIP over + * Ethernet, you will need to call the uip_arp_out() function before + * calling the device driver: + \code + for(i = 0; i < UIP_CONNS; ++i) { + uip_periodic(i); + if(uip_len > 0) { + uip_arp_out(); + ethernet_devicedriver_send(); + } + } + \endcode + * + * \param conn The number of the connection which is to be periodically polled. + * + * \hideinitializer + */ +#define uip_periodic(conn) do { uip_conn = &uip_conns[conn]; \ + uip_process(UIP_TIMER); } while (0) + +/** + * Periodic processing for a connection identified by a pointer to its structure. + * + * Same as uip_periodic() but takes a pointer to the actual uip_conn + * struct instead of an integer as its argument. This function can be + * used to force periodic processing of a specific connection. + * + * \param conn A pointer to the uip_conn struct for the connection to + * be processed. + * + * \hideinitializer + */ +#define uip_periodic_conn(conn) do { uip_conn = conn; \ + uip_process(UIP_TIMER); } while (0) + +#if UIP_UDP +/** + * Periodic processing for a UDP connection identified by its number. + * + * This function is essentially the same as uip_prerioic(), but for + * UDP connections. It is called in a similar fashion as the + * uip_periodic() function: + \code + for(i = 0; i < UIP_UDP_CONNS; i++) { + uip_udp_periodic(i); + if(uip_len > 0) { + devicedriver_send(); + } + } + \endcode + * + * \note As for the uip_periodic() function, special care has to be + * taken when using uIP together with ARP and Ethernet: + \code + for(i = 0; i < UIP_UDP_CONNS; i++) { + uip_udp_periodic(i); + if(uip_len > 0) { + uip_arp_out(); + ethernet_devicedriver_send(); + } + } + \endcode + * + * \param conn The number of the UDP connection to be processed. + * + * \hideinitializer + */ +#define uip_udp_periodic(conn) do { uip_udp_conn = &uip_udp_conns[conn]; \ + uip_process(UIP_UDP_TIMER); } while (0) + +/** + * Periodic processing for a UDP connection identified by a pointer to + * its structure. + * + * Same as uip_udp_periodic() but takes a pointer to the actual + * uip_conn struct instead of an integer as its argument. This + * function can be used to force periodic processing of a specific + * connection. + * + * \param conn A pointer to the uip_udp_conn struct for the connection + * to be processed. + * + * \hideinitializer + */ +#define uip_udp_periodic_conn(conn) do { uip_udp_conn = conn; \ + uip_process(UIP_UDP_TIMER); } while (0) + + +#endif /* UIP_UDP */ + +/** + * The uIP packet buffer. + * + * The uip_buf array is used to hold incoming and outgoing + * packets. The device driver should place incoming data into this + * buffer. When sending data, the device driver should read the link + * level headers and the TCP/IP headers from this buffer. The size of + * the link level headers is configured by the UIP_LLH_LEN define. + * + * \note The application data need not be placed in this buffer, so + * the device driver must read it from the place pointed to by the + * uip_appdata pointer as illustrated by the following example: + \code + void + devicedriver_send(void) + { + hwsend(&uip_buf[0], UIP_LLH_LEN); + hwsend(&uip_buf[UIP_LLH_LEN], 40); + hwsend(uip_appdata, uip_len - 40 - UIP_LLH_LEN); + } + \endcode + */ +extern u8_t uip_buf[UIP_BUFSIZE+2] __attribute__ ((aligned (4))); + +/** @} */ + +/*-----------------------------------------------------------------------------------*/ +/* Functions that are used by the uIP application program. Opening and + * closing connections, sending and receiving data, etc. is all + * handled by the functions below. +*/ +/** + * \defgroup uipappfunc uIP application functions + * @{ + * + * Functions used by an application running of top of uIP. + */ + +/** + * Start listening to the specified port. + * + * \note Since this function expects the port number in network byte + * order, a conversion using HTONS() or htons() is necessary. + * + \code + uip_listen(HTONS(80)); + \endcode + * + * \param port A 16-bit port number in network byte order. + */ +void uip_listen(u16_t port); + +/** + * Stop listening to the specified port. + * + * \note Since this function expects the port number in network byte + * order, a conversion using HTONS() or htons() is necessary. + * + \code + uip_unlisten(HTONS(80)); + \endcode + * + * \param port A 16-bit port number in network byte order. + */ +void uip_unlisten(u16_t port); + +/** + * Connect to a remote host using TCP. + * + * This function is used to start a new connection to the specified + * port on the specied host. It allocates a new connection identifier, + * sets the connection to the SYN_SENT state and sets the + * retransmission timer to 0. This will cause a TCP SYN segment to be + * sent out the next time this connection is periodically processed, + * which usually is done within 0.5 seconds after the call to + * uip_connect(). + * + * \note This function is avaliable only if support for active open + * has been configured by defining UIP_ACTIVE_OPEN to 1 in uipopt.h. + * + * \note Since this function requires the port number to be in network + * byte order, a convertion using HTONS() or htons() is necessary. + * + \code + u16_t ipaddr[2]; + + uip_ipaddr(ipaddr, 192,168,1,2); + uip_connect(ipaddr, HTONS(80)); + \endcode + * + * \param ripaddr A pointer to a 4-byte array representing the IP + * address of the remote hot. + * + * \param port A 16-bit port number in network byte order. + * + * \return A pointer to the uIP connection identifier for the new connection, + * or NULL if no connection could be allocated. + * + */ +struct uip_conn *uip_connect(u16_t *ripaddr, u16_t port); + + + +/** + * \internal + * + * Check if a connection has outstanding (i.e., unacknowledged) data. + * + * \param conn A pointer to the uip_conn structure for the connection. + * + * \hideinitializer + */ +#define uip_outstanding(conn) ((conn)->len) + +/** + * Send data on the current connection. + * + * This function is used to send out a single segment of TCP + * data. Only applications that have been invoked by uIP for event + * processing can send data. + * + * The amount of data that actually is sent out after a call to this + * funcion is determined by the maximum amount of data TCP allows. uIP + * will automatically crop the data so that only the appropriate + * amount of data is sent. The function uip_mss() can be used to query + * uIP for the amount of data that actually will be sent. + * + * \note This function does not guarantee that the sent data will + * arrive at the destination. If the data is lost in the network, the + * application will be invoked with the uip_rexmit() event being + * set. The application will then have to resend the data using this + * function. + * + * \param data A pointer to the data which is to be sent. + * + * \param len The maximum amount of data bytes to be sent. + * + * \hideinitializer + */ +#define uip_send(data, len) do { uip_sappdata = (data); uip_slen = (len);} while(0) + +/** + * The length of any incoming data that is currently avaliable (if avaliable) + * in the uip_appdata buffer. + * + * The test function uip_data() must first be used to check if there + * is any data available at all. + * + * \hideinitializer + */ +#define uip_datalen() uip_len + +/** + * The length of any out-of-band data (urgent data) that has arrived + * on the connection. + * + * \note The configuration parameter UIP_URGDATA must be set for this + * function to be enabled. + * + * \hideinitializer + */ +#define uip_urgdatalen() uip_urglen + +/** + * Close the current connection. + * + * This function will close the current connection in a nice way. + * + * \hideinitializer + */ +#define uip_close() (uip_flags = UIP_CLOSE) + +/** + * Abort the current connection. + * + * This function will abort (reset) the current connection, and is + * usually used when an error has occured that prevents using the + * uip_close() function. + * + * \hideinitializer + */ +#define uip_abort() (uip_flags = UIP_ABORT) + +/** + * Tell the sending host to stop sending data. + * + * This function will close our receiver's window so that we stop + * receiving data for the current connection. + * + * \hideinitializer + */ +#define uip_stop() (uip_conn->tcpstateflags |= UIP_STOPPED) + +/** + * Find out if the current connection has been previously stopped with + * uip_stop(). + * + * \hideinitializer + */ +#define uip_stopped(conn) ((conn)->tcpstateflags & UIP_STOPPED) + +/** + * Restart the current connection, if is has previously been stopped + * with uip_stop(). + * + * This function will open the receiver's window again so that we + * start receiving data for the current connection. + * + * \hideinitializer + */ +#define uip_restart() do { uip_flags |= UIP_NEWDATA; \ + uip_conn->tcpstateflags &= ~UIP_STOPPED; \ + } while(0) + + +/* uIP tests that can be made to determine in what state the current + connection is, and what the application function should do. */ + +/** + * Is new incoming data available? + * + * Will reduce to non-zero if there is new data for the application + * present at the uip_appdata pointer. The size of the data is + * avaliable through the uip_len variable. + * + * \hideinitializer + */ +#define uip_newdata() (uip_flags & UIP_NEWDATA) + +/** + * Has previously sent data been acknowledged? + * + * Will reduce to non-zero if the previously sent data has been + * acknowledged by the remote host. This means that the application + * can send new data. + * + * \hideinitializer + */ +#define uip_acked() (uip_flags & UIP_ACKDATA) + +/** + * Has the connection just been connected? + * + * Reduces to non-zero if the current connection has been connected to + * a remote host. This will happen both if the connection has been + * actively opened (with uip_connect()) or passively opened (with + * uip_listen()). + * + * \hideinitializer + */ +#define uip_connected() (uip_flags & UIP_CONNECTED) + +/** + * Has the connection been closed by the other end? + * + * Is non-zero if the connection has been closed by the remote + * host. The application may then do the necessary clean-ups. + * + * \hideinitializer + */ +#define uip_closed() (uip_flags & UIP_CLOSE) + +/** + * Has the connection been aborted by the other end? + * + * Non-zero if the current connection has been aborted (reset) by the + * remote host. + * + * \hideinitializer + */ +#define uip_aborted() (uip_flags & UIP_ABORT) + +/** + * Has the connection timed out? + * + * Non-zero if the current connection has been aborted due to too many + * retransmissions. + * + * \hideinitializer + */ +#define uip_timedout() (uip_flags & UIP_TIMEDOUT) + +/** + * Do we need to retransmit previously data? + * + * Reduces to non-zero if the previously sent data has been lost in + * the network, and the application should retransmit it. The + * application should send the exact same data as it did the last + * time, using the uip_send() function. + * + * \hideinitializer + */ +#define uip_rexmit() (uip_flags & UIP_REXMIT) + +/** + * Is the connection being polled by uIP? + * + * Is non-zero if the reason the application is invoked is that the + * current connection has been idle for a while and should be + * polled. + * + * The polling event can be used for sending data without having to + * wait for the remote host to send data. + * + * \hideinitializer + */ +#define uip_poll() (uip_flags & UIP_POLL) + +/** + * Get the initial maxium segment size (MSS) of the current + * connection. + * + * \hideinitializer + */ +#define uip_initialmss() (uip_conn->initialmss) + +/** + * Get the current maxium segment size that can be sent on the current + * connection. + * + * The current maxiumum segment size that can be sent on the + * connection is computed from the receiver's window and the MSS of + * the connection (which also is available by calling + * uip_initialmss()). + * + * \hideinitializer + */ +#define uip_mss() (uip_conn->mss) + +/** + * Set up a new UDP connection. + * + * \param ripaddr A pointer to a 4-byte structure representing the IP + * address of the remote host. + * + * \param rport The remote port number in network byte order. + * + * \return The uip_udp_conn structure for the new connection or NULL + * if no connection could be allocated. + */ +struct uip_udp_conn *uip_udp_new(u16_t *ripaddr, u16_t rport); + +/** + * Removed a UDP connection. + * + * \param conn A pointer to the uip_udp_conn structure for the connection. + * + * \hideinitializer + */ +#define uip_udp_remove(conn) (conn)->lport = 0 + +/** + * Send a UDP datagram of length len on the current connection. + * + * This function can only be called in response to a UDP event (poll + * or newdata). The data must be present in the uip_buf buffer, at the + * place pointed to by the uip_appdata pointer. + * + * \param len The length of the data in the uip_buf buffer. + * + * \hideinitializer + */ +#define uip_udp_send(len) uip_slen = (len) + +/** @} */ + +/* uIP convenience and converting functions. */ + +/** + * \defgroup uipconvfunc uIP conversion functions + * @{ + * + * These functions can be used for converting between different data + * formats used by uIP. + */ + +/** + * Pack an IP address into a 4-byte array which is used by uIP to + * represent IP addresses. + * + * Example: + \code + u16_t ipaddr[2]; + + uip_ipaddr(&ipaddr, 192,168,1,2); + \endcode + * + * \param addr A pointer to a 4-byte array that will be filled in with + * the IP addres. + * \param addr0 The first octet of the IP address. + * \param addr1 The second octet of the IP address. + * \param addr2 The third octet of the IP address. + * \param addr3 The forth octet of the IP address. + * + * \hideinitializer + */ +#define uip_ipaddr(addr, addr0,addr1,addr2,addr3) do { \ + (addr)[0] = HTONS(((addr0) << 8) | (addr1)); \ + (addr)[1] = HTONS(((addr2) << 8) | (addr3)); \ + } while(0) + +/** + * Convert 16-bit quantity from host byte order to network byte order. + * + * This macro is primarily used for converting constants from host + * byte order to network byte order. For converting variables to + * network byte order, use the htons() function instead. + * + * \hideinitializer + */ +#ifndef HTONS +# if BYTE_ORDER == BIG_ENDIAN +# define HTONS(n) (n) +# else /* BYTE_ORDER == BIG_ENDIAN */ +# define HTONS(n) ((((u16_t)((n) & 0xff)) << 8) | (((n) & 0xff00) >> 8)) +# endif /* BYTE_ORDER == BIG_ENDIAN */ +#endif /* HTONS */ + +/** + * Convert 16-bit quantity from host byte order to network byte order. + * + * This function is primarily used for converting variables from host + * byte order to network byte order. For converting constants to + * network byte order, use the HTONS() macro instead. + */ +#ifndef htons +u16_t htons(u16_t val); +#endif /* htons */ + +/** @} */ + +/** + * Pointer to the application data in the packet buffer. + * + * This pointer points to the application data when the application is + * called. If the application wishes to send data, the application may + * use this space to write the data into before calling uip_send(). + */ +extern volatile u8_t *uip_appdata; +extern volatile u8_t *uip_sappdata; + +#if UIP_URGDATA > 0 +/* u8_t *uip_urgdata: + * + * This pointer points to any urgent data that has been received. Only + * present if compiled with support for urgent data (UIP_URGDATA). + */ +extern volatile u8_t *uip_urgdata; +#endif /* UIP_URGDATA > 0 */ + + +/* u[8|16]_t uip_len: + * + * When the application is called, uip_len contains the length of any + * new data that has been received from the remote host. The + * application should set this variable to the size of any data that + * the application wishes to send. When the network device driver + * output function is called, uip_len should contain the length of the + * outgoing packet. + */ +extern volatile u16_t uip_len, uip_slen; + +#if UIP_URGDATA > 0 +extern volatile u8_t uip_urglen, uip_surglen; +#endif /* UIP_URGDATA > 0 */ + + +/** + * Representation of a uIP TCP connection. + * + * The uip_conn structure is used for identifying a connection. All + * but one field in the structure are to be considered read-only by an + * application. The only exception is the appstate field whos purpose + * is to let the application store application-specific state (e.g., + * file pointers) for the connection. The size of this field is + * configured in the "uipopt.h" header file. + */ +struct uip_conn { + u16_t ripaddr[2]; /**< The IP address of the remote host. */ + + u16_t lport; /**< The local TCP port, in network byte order. */ + u16_t rport; /**< The local remote TCP port, in network byte + order. */ + + u8_t rcv_nxt[4]; /**< The sequence number that we expect to + receive next. */ + u8_t snd_nxt[4]; /**< The sequence number that was last sent by + us. */ + u16_t len; /**< Length of the data that was previously sent. */ + u16_t mss; /**< Current maximum segment size for the + connection. */ + u16_t initialmss; /**< Initial maximum segment size for the + connection. */ + u8_t sa; /**< Retransmission time-out calculation state + variable. */ + u8_t sv; /**< Retransmission time-out calculation state + variable. */ + u8_t rto; /**< Retransmission time-out. */ + u8_t tcpstateflags; /**< TCP state and flags. */ + u8_t timer; /**< The retransmission timer. */ + u8_t nrtx; /**< The number of retransmissions for the last + segment sent. */ + + /** The application state. */ + u8_t appstate[UIP_APPSTATE_SIZE]; +}; + + +/* Pointer to the current connection. */ +extern struct uip_conn *uip_conn; +/* The array containing all uIP connections. */ +extern struct uip_conn uip_conns[UIP_CONNS]; +/** + * \addtogroup uiparch + * @{ + */ + +/** + * 4-byte array used for the 32-bit sequence number calculations. + */ +extern volatile u8_t uip_acc32[4]; + +/** @} */ + + +#if UIP_UDP +/** + * Representation of a uIP UDP connection. + */ +struct uip_udp_conn { + u16_t ripaddr[2]; /**< The IP address of the remote peer. */ + u16_t lport; /**< The local port number in network byte order. */ + u16_t rport; /**< The remote port number in network byte order. */ +}; + +extern struct uip_udp_conn *uip_udp_conn; +extern struct uip_udp_conn uip_udp_conns[UIP_UDP_CONNS]; +#endif /* UIP_UDP */ + +/** + * The structure holding the TCP/IP statistics that are gathered if + * UIP_STATISTICS is set to 1. + * + */ +struct uip_stats { + struct { + uip_stats_t drop; /**< Number of dropped packets at the IP + layer. */ + uip_stats_t recv; /**< Number of received packets at the IP + layer. */ + uip_stats_t sent; /**< Number of sent packets at the IP + layer. */ + uip_stats_t vhlerr; /**< Number of packets dropped due to wrong + IP version or header length. */ + uip_stats_t hblenerr; /**< Number of packets dropped due to wrong + IP length, high byte. */ + uip_stats_t lblenerr; /**< Number of packets dropped due to wrong + IP length, low byte. */ + uip_stats_t fragerr; /**< Number of packets dropped since they + were IP fragments. */ + uip_stats_t chkerr; /**< Number of packets dropped due to IP + checksum errors. */ + uip_stats_t protoerr; /**< Number of packets dropped since they + were neither ICMP, UDP nor TCP. */ + } ip; /**< IP statistics. */ + struct { + uip_stats_t drop; /**< Number of dropped ICMP packets. */ + uip_stats_t recv; /**< Number of received ICMP packets. */ + uip_stats_t sent; /**< Number of sent ICMP packets. */ + uip_stats_t typeerr; /**< Number of ICMP packets with a wrong + type. */ + } icmp; /**< ICMP statistics. */ + struct { + uip_stats_t drop; /**< Number of dropped TCP segments. */ + uip_stats_t recv; /**< Number of recived TCP segments. */ + uip_stats_t sent; /**< Number of sent TCP segments. */ + uip_stats_t chkerr; /**< Number of TCP segments with a bad + checksum. */ + uip_stats_t ackerr; /**< Number of TCP segments with a bad ACK + number. */ + uip_stats_t rst; /**< Number of recevied TCP RST (reset) segments. */ + uip_stats_t rexmit; /**< Number of retransmitted TCP segments. */ + uip_stats_t syndrop; /**< Number of dropped SYNs due to too few + connections was avaliable. */ + uip_stats_t synrst; /**< Number of SYNs for closed ports, + triggering a RST. */ + } tcp; /**< TCP statistics. */ +}; + +/** + * The uIP TCP/IP statistics. + * + * This is the variable in which the uIP TCP/IP statistics are gathered. + */ +extern struct uip_stats uip_stat; + + +/*-----------------------------------------------------------------------------------*/ +/* All the stuff below this point is internal to uIP and should not be + * used directly by an application or by a device driver. + */ +/*-----------------------------------------------------------------------------------*/ +/* u8_t uip_flags: + * + * When the application is called, uip_flags will contain the flags + * that are defined in this file. Please read below for more + * infomation. + */ +extern volatile u8_t uip_flags; + +/* The following flags may be set in the global variable uip_flags + before calling the application callback. The UIP_ACKDATA and + UIP_NEWDATA flags may both be set at the same time, whereas the + others are mutualy exclusive. Note that these flags should *NOT* be + accessed directly, but through the uIP functions/macros. */ + +#define UIP_ACKDATA 1 /* Signifies that the outstanding data was + acked and the application should send + out new data instead of retransmitting + the last data. */ +#define UIP_NEWDATA 2 /* Flags the fact that the peer has sent + us new data. */ +#define UIP_REXMIT 4 /* Tells the application to retransmit the + data that was last sent. */ +#define UIP_POLL 8 /* Used for polling the application, to + check if the application has data that + it wants to send. */ +#define UIP_CLOSE 16 /* The remote host has closed the + connection, thus the connection has + gone away. Or the application signals + that it wants to close the + connection. */ +#define UIP_ABORT 32 /* The remote host has aborted the + connection, thus the connection has + gone away. Or the application signals + that it wants to abort the + connection. */ +#define UIP_CONNECTED 64 /* We have got a connection from a remote + host and have set up a new connection + for it, or an active connection has + been successfully established. */ + +#define UIP_TIMEDOUT 128 /* The connection has been aborted due to + too many retransmissions. */ + + +/* uip_process(flag): + * + * The actual uIP function which does all the work. + */ +void uip_process(u8_t flag); + +/* The following flags are passed as an argument to the uip_process() + function. They are used to distinguish between the two cases where + uip_process() is called. It can be called either because we have + incoming data that should be processed, or because the periodic + timer has fired. */ + +#define UIP_DATA 1 /* Tells uIP that there is incoming data in + the uip_buf buffer. The length of the + data is stored in the global variable + uip_len. */ +#define UIP_TIMER 2 /* Tells uIP that the periodic timer has + fired. */ +#if UIP_UDP +#define UIP_UDP_TIMER 3 +#endif /* UIP_UDP */ + +/* The TCP states used in the uip_conn->tcpstateflags. */ +#define CLOSED 0 +#define SYN_RCVD 1 +#define SYN_SENT 2 +#define ESTABLISHED 3 +#define FIN_WAIT_1 4 +#define FIN_WAIT_2 5 +#define CLOSING 6 +#define TIME_WAIT 7 +#define LAST_ACK 8 +#define TS_MASK 15 + +#define UIP_STOPPED 16 + +#define UIP_TCPIP_HLEN 40 + +/* The TCP and IP headers. */ +typedef struct { + /* IP header. */ + u8_t vhl, + tos, + len[2], + ipid[2], + ipoffset[2], + ttl, + proto; + u16_t ipchksum; + u16_t srcipaddr[2], + destipaddr[2]; + + /* TCP header. */ + u16_t srcport, + destport; + u8_t seqno[4], + ackno[4], + tcpoffset, + flags, + wnd[2]; + u16_t tcpchksum; + u8_t urgp[2]; + u8_t optdata[4]; +} uip_tcpip_hdr; + +/* The ICMP and IP headers. */ +typedef struct { + /* IP header. */ + u8_t vhl, + tos, + len[2], + ipid[2], + ipoffset[2], + ttl, + proto; + u16_t ipchksum; + u16_t srcipaddr[2], + destipaddr[2]; + /* ICMP (echo) header. */ + u8_t type, icode; + u16_t icmpchksum; + u16_t id, seqno; +} uip_icmpip_hdr; + + +/* The UDP and IP headers. */ +typedef struct { + /* IP header. */ + u8_t vhl, + tos, + len[2], + ipid[2], + ipoffset[2], + ttl, + proto; + u16_t ipchksum; + u16_t srcipaddr[2], + destipaddr[2]; + + /* UDP header. */ + u16_t srcport, + destport; + u16_t udplen; + u16_t udpchksum; +} uip_udpip_hdr; + +#define UIP_PROTO_ICMP 1 +#define UIP_PROTO_TCP 6 +#define UIP_PROTO_UDP 17 + +#if UIP_FIXEDADDR +extern const u16_t uip_hostaddr[2]; +#else /* UIP_FIXEDADDR */ +extern u16_t uip_hostaddr[2]; +#endif /* UIP_FIXEDADDR */ + +#endif /* __UIP_H__ */ + + +/** @} */ + diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/uip_arch.c b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/uip_arch.c new file mode 100644 index 000000000..4cd08c3c7 --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/uip_arch.c @@ -0,0 +1,146 @@ +/* + * Copyright (c) 2001, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: uip_arch.c,v 1.2.2.1 2003/10/04 22:54:17 adam Exp $ + * + */ + + +#include "uip.h" +#include "uip_arch.h" +#include <__cross_studio_io.h> + +#define BUF ((uip_tcpip_hdr *)&uip_buf[UIP_LLH_LEN]) +#define IP_PROTO_TCP 6 + +/*-----------------------------------------------------------------------------------*/ +void +uip_add32(u8_t *op32, u16_t op16) +{ + + uip_acc32[3] = op32[3] + (op16 & 0xff); + uip_acc32[2] = op32[2] + (op16 >> 8); + uip_acc32[1] = op32[1]; + uip_acc32[0] = op32[0]; + + if(uip_acc32[2] < (op16 >> 8)) { + ++uip_acc32[1]; + if(uip_acc32[1] == 0) { + ++uip_acc32[0]; + } + } + + + if(uip_acc32[3] < (op16 & 0xff)) { + ++uip_acc32[2]; + if(uip_acc32[2] == 0) { + ++uip_acc32[1]; + if(uip_acc32[1] == 0) { + ++uip_acc32[0]; + } + } + } +} +/*-----------------------------------------------------------------------------------*/ +u16_t +uip_chksum(u16_t *sdata, u16_t len) +{ + u16_t acc; + + for (acc = 0; len > 1; len -= 2) { + u16_t u = ((unsigned char *)sdata)[0] + (((unsigned char *)sdata)[1] << 8); + if ((acc += u) < u) { + /* Overflow, so we add the carry to acc (i.e., increase by + one). */ + ++acc; + } + ++sdata; + } + + /* add up any odd byte */ + if(len == 1) { + acc += htons(((u16_t)(*(u8_t *)sdata)) << 8); + if(acc < htons(((u16_t)(*(u8_t *)sdata)) << 8)) { + ++acc; + } + } + + return acc; +} +/*-----------------------------------------------------------------------------------*/ +u16_t +uip_ipchksum(void) +{ + return uip_chksum((u16_t *)&uip_buf[UIP_LLH_LEN], 20); +} +/*-----------------------------------------------------------------------------------*/ +u16_t +uip_tcpchksum(void) +{ + u16_t hsum, sum; + + + /* Compute the checksum of the TCP header. */ + hsum = uip_chksum((u16_t *)&uip_buf[20 + UIP_LLH_LEN], 20); + + /* Compute the checksum of the data in the TCP packet and add it to + the TCP header checksum. */ + sum = uip_chksum((u16_t *)uip_appdata, + (u16_t)(((((u16_t)(BUF->len[0]) << 8) + BUF->len[1]) - 40))); + + if((sum += hsum) < hsum) { + ++sum; + } + + if((sum += BUF->srcipaddr[0]) < BUF->srcipaddr[0]) { + ++sum; + } + if((sum += BUF->srcipaddr[1]) < BUF->srcipaddr[1]) { + ++sum; + } + if((sum += BUF->destipaddr[0]) < BUF->destipaddr[0]) { + ++sum; + } + if((sum += BUF->destipaddr[1]) < BUF->destipaddr[1]) { + ++sum; + } + if((sum += (u16_t)htons((u16_t)IP_PROTO_TCP)) < (u16_t)htons((u16_t)IP_PROTO_TCP)) { + ++sum; + } + + hsum = (u16_t)htons((((u16_t)(BUF->len[0]) << 8) + BUF->len[1]) - 20); + + if((sum += hsum) < hsum) { + ++sum; + } + + return sum; +} +/*-----------------------------------------------------------------------------------*/ diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/uip_arch.h b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/uip_arch.h new file mode 100644 index 000000000..b2d133f2e --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/uip_arch.h @@ -0,0 +1,130 @@ +/** + * \defgroup uiparch Architecture specific uIP functions + * @{ + * + * The functions in the architecture specific module implement the IP + * check sum and 32-bit additions. + * + * The IP checksum calculation is the most computationally expensive + * operation in the TCP/IP stack and it therefore pays off to + * implement this in efficient assembler. The purpose of the uip-arch + * module is to let the checksum functions to be implemented in + * architecture specific assembler. + * + */ + +/** + * \file + * Declarations of architecture specific functions. + * \author Adam Dunkels + */ + +/* + * Copyright (c) 2001, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: uip_arch.h,v 1.1.2.2 2003/10/06 15:10:22 adam Exp $ + * + */ + +#ifndef __UIP_ARCH_H__ +#define __UIP_ARCH_H__ + +#include "uip.h" + +/** + * Carry out a 32-bit addition. + * + * Because not all architectures for which uIP is intended has native + * 32-bit arithmetic, uIP uses an external C function for doing the + * required 32-bit additions in the TCP protocol processing. This + * function should add the two arguments and place the result in the + * global variable uip_acc32. + * + * \note The 32-bit integer pointed to by the op32 parameter and the + * result in the uip_acc32 variable are in network byte order (big + * endian). + * + * \param op32 A pointer to a 4-byte array representing a 32-bit + * integer in network byte order (big endian). + * + * \param op16 A 16-bit integer in host byte order. + */ +void uip_add32(u8_t *op32, u16_t op16); + +/** + * Calculate the Internet checksum over a buffer. + * + * The Internet checksum is the one's complement of the one's + * complement sum of all 16-bit words in the buffer. + * + * See RFC1071. + * + * \note This function is not called in the current version of uIP, + * but future versions might make use of it. + * + * \param buf A pointer to the buffer over which the checksum is to be + * computed. + * + * \param len The length of the buffer over which the checksum is to + * be computed. + * + * \return The Internet checksum of the buffer. + */ +u16_t uip_chksum(u16_t *buf, u16_t len); + +/** + * Calculate the IP header checksum of the packet header in uip_buf. + * + * The IP header checksum is the Internet checksum of the 20 bytes of + * the IP header. + * + * \return The IP header checksum of the IP header in the uip_buf + * buffer. + */ +u16_t uip_ipchksum(void); + +/** + * Calculate the TCP checksum of the packet in uip_buf and uip_appdata. + * + * The TCP checksum is the Internet checksum of data contents of the + * TCP segment, and a pseudo-header as defined in RFC793. + * + * \note The uip_appdata pointer that points to the packet data may + * point anywhere in memory, so it is not possible to simply calculate + * the Internet checksum of the contents of the uip_buf buffer. + * + * \return The TCP checksum of the TCP segment in uip_buf and pointed + * to by uip_appdata. + */ +u16_t uip_tcpchksum(void); + +/** @} */ + +#endif /* __UIP_ARCH_H__ */ diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/uip_arp.c b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/uip_arp.c new file mode 100644 index 000000000..f2804df95 --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/uip_arp.c @@ -0,0 +1,427 @@ +/** + * \addtogroup uip + * @{ + */ + +/** + * \defgroup uiparp uIP Address Resolution Protocol + * @{ + * + * The Address Resolution Protocol ARP is used for mapping between IP + * addresses and link level addresses such as the Ethernet MAC + * addresses. ARP uses broadcast queries to ask for the link level + * address of a known IP address and the host which is configured with + * the IP address for which the query was meant, will respond with its + * link level address. + * + * \note This ARP implementation only supports Ethernet. + */ + +/** + * \file + * Implementation of the ARP Address Resolution Protocol. + * \author Adam Dunkels + * + */ + +/* + * Copyright (c) 2001-2003, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: uip_arp.c,v 1.7.2.3 2003/10/06 22:42:30 adam Exp $ + * + */ + + +#include "uip_arp.h" + +#include + +struct arp_hdr { + struct uip_eth_hdr ethhdr; + u16_t hwtype; + u16_t protocol; + u8_t hwlen; + u8_t protolen; + u16_t opcode; + struct uip_eth_addr shwaddr; + u16_t sipaddr[2]; + struct uip_eth_addr dhwaddr; + u16_t dipaddr[2]; +}; + +struct ethip_hdr { + struct uip_eth_hdr ethhdr; + /* IP header. */ + u8_t vhl, + tos, + len[2], + ipid[2], + ipoffset[2], + ttl, + proto; + u16_t ipchksum; + u16_t srcipaddr[2], + destipaddr[2]; +}; + +#define ARP_REQUEST 1 +#define ARP_REPLY 2 + +#define ARP_HWTYPE_ETH 1 + +struct arp_entry { + u16_t ipaddr[2]; + struct uip_eth_addr ethaddr; + u8_t time; +}; + +struct uip_eth_addr uip_ethaddr = {{UIP_ETHADDR0, + UIP_ETHADDR1, + UIP_ETHADDR2, + UIP_ETHADDR3, + UIP_ETHADDR4, + UIP_ETHADDR5}}; + +static struct arp_entry arp_table[UIP_ARPTAB_SIZE]; +static u16_t ipaddr[2]; +static u8_t i, c; + +static u8_t arptime; +static u8_t tmpage; + +#define BUF ((struct arp_hdr *)&uip_buf[0]) +#define IPBUF ((struct ethip_hdr *)&uip_buf[0]) +/*-----------------------------------------------------------------------------------*/ +/** + * Initialize the ARP module. + * + */ +/*-----------------------------------------------------------------------------------*/ +void +uip_arp_init(void) +{ + for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { + memset(arp_table[i].ipaddr, 0, 4); + } +} +/*-----------------------------------------------------------------------------------*/ +/** + * Periodic ARP processing function. + * + * This function performs periodic timer processing in the ARP module + * and should be called at regular intervals. The recommended interval + * is 10 seconds between the calls. + * + */ +/*-----------------------------------------------------------------------------------*/ +void +uip_arp_timer(void) +{ + struct arp_entry *tabptr; + + ++arptime; + for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { + tabptr = &arp_table[i]; + if((tabptr->ipaddr[0] | tabptr->ipaddr[1]) != 0 && + arptime - tabptr->time >= UIP_ARP_MAXAGE) { + memset(tabptr->ipaddr, 0, 4); + } + } + +} +/*-----------------------------------------------------------------------------------*/ +static void +uip_arp_update(u16_t *ipaddr, struct uip_eth_addr *ethaddr) +{ + register struct arp_entry *tabptr; + /* Walk through the ARP mapping table and try to find an entry to + update. If none is found, the IP -> MAC address mapping is + inserted in the ARP table. */ + for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { + + tabptr = &arp_table[i]; + /* Only check those entries that are actually in use. */ + if(tabptr->ipaddr[0] != 0 && + tabptr->ipaddr[1] != 0) { + + /* Check if the source IP address of the incoming packet matches + the IP address in this ARP table entry. */ + if(ipaddr[0] == tabptr->ipaddr[0] && + ipaddr[1] == tabptr->ipaddr[1]) { + + /* An old entry found, update this and return. */ + memcpy(tabptr->ethaddr.addr, ethaddr->addr, 6); + tabptr->time = arptime; + + return; + } + } + } + + /* If we get here, no existing ARP table entry was found, so we + create one. */ + + /* First, we try to find an unused entry in the ARP table. */ + for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { + tabptr = &arp_table[i]; + if(tabptr->ipaddr[0] == 0 && + tabptr->ipaddr[1] == 0) { + break; + } + } + + /* If no unused entry is found, we try to find the oldest entry and + throw it away. */ + if(i == UIP_ARPTAB_SIZE) { + tmpage = 0; + c = 0; + for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { + tabptr = &arp_table[i]; + if(arptime - tabptr->time > tmpage) { + tmpage = arptime - tabptr->time; + c = i; + } + } + i = c; + } + + /* Now, i is the ARP table entry which we will fill with the new + information. */ + memcpy(tabptr->ipaddr, ipaddr, 4); + memcpy(tabptr->ethaddr.addr, ethaddr->addr, 6); + tabptr->time = arptime; +} +/*-----------------------------------------------------------------------------------*/ +/** + * ARP processing for incoming IP packets + * + * This function should be called by the device driver when an IP + * packet has been received. The function will check if the address is + * in the ARP cache, and if so the ARP cache entry will be + * refreshed. If no ARP cache entry was found, a new one is created. + * + * This function expects an IP packet with a prepended Ethernet header + * in the uip_buf[] buffer, and the length of the packet in the global + * variable uip_len. + */ +/*-----------------------------------------------------------------------------------*/ +void +uip_arp_ipin(void) +{ + uip_len -= sizeof(struct uip_eth_hdr); + + /* Only insert/update an entry if the source IP address of the + incoming IP packet comes from a host on the local network. */ + if((IPBUF->srcipaddr[0] & uip_arp_netmask[0]) != + (uip_hostaddr[0] & uip_arp_netmask[0])) { + return; + } + if((IPBUF->srcipaddr[1] & uip_arp_netmask[1]) != + (uip_hostaddr[1] & uip_arp_netmask[1])) { + return; + } + uip_arp_update(IPBUF->srcipaddr, &(IPBUF->ethhdr.src)); + + return; +} +/*-----------------------------------------------------------------------------------*/ +/** + * ARP processing for incoming ARP packets. + * + * This function should be called by the device driver when an ARP + * packet has been received. The function will act differently + * depending on the ARP packet type: if it is a reply for a request + * that we previously sent out, the ARP cache will be filled in with + * the values from the ARP reply. If the incoming ARP packet is an ARP + * request for our IP address, an ARP reply packet is created and put + * into the uip_buf[] buffer. + * + * When the function returns, the value of the global variable uip_len + * indicates whether the device driver should send out a packet or + * not. If uip_len is zero, no packet should be sent. If uip_len is + * non-zero, it contains the length of the outbound packet that is + * present in the uip_buf[] buffer. + * + * This function expects an ARP packet with a prepended Ethernet + * header in the uip_buf[] buffer, and the length of the packet in the + * global variable uip_len. + */ +/*-----------------------------------------------------------------------------------*/ +typedef struct arp_hdr aht; + +void +uip_arp_arpin(void) +{ + int ul; + + if(uip_len < sizeof(struct arp_hdr)) { + uip_len = 0; + return; + } + + uip_len = 0; + + switch(BUF->opcode) { + case HTONS(ARP_REQUEST): + /* ARP request. If it asked for our address, we send out a + reply. */ + if(BUF->dipaddr[0] == uip_hostaddr[0] && + BUF->dipaddr[1] == uip_hostaddr[1]) { + /* The reply opcode is 2. */ + BUF->opcode = HTONS(2); + + memcpy(BUF->dhwaddr.addr, BUF->shwaddr.addr, 6); + memcpy(BUF->shwaddr.addr, uip_ethaddr.addr, 6); + memcpy(BUF->ethhdr.src.addr, uip_ethaddr.addr, 6); + memcpy(BUF->ethhdr.dest.addr, BUF->dhwaddr.addr, 6); + + BUF->dipaddr[0] = BUF->sipaddr[0]; + BUF->dipaddr[1] = BUF->sipaddr[1]; + BUF->sipaddr[0] = uip_hostaddr[0]; + BUF->sipaddr[1] = uip_hostaddr[1]; + + ul = BUF->hwlen; + BUF->ethhdr.type = HTONS(UIP_ETHTYPE_ARP); + uip_len = sizeof(struct arp_hdr); + } + break; + case HTONS(ARP_REPLY): + /* ARP reply. We insert or update the ARP table if it was meant + for us. */ + if(BUF->dipaddr[0] == uip_hostaddr[0] && + BUF->dipaddr[1] == uip_hostaddr[1]) { + + uip_arp_update(BUF->sipaddr, &BUF->shwaddr); + } + break; + } + + return; +} +/*-----------------------------------------------------------------------------------*/ +/** + * Prepend Ethernet header to an outbound IP packet and see if we need + * to send out an ARP request. + * + * This function should be called before sending out an IP packet. The + * function checks the destination IP address of the IP packet to see + * what Ethernet MAC address that should be used as a destination MAC + * address on the Ethernet. + * + * If the destination IP address is in the local network (determined + * by logical ANDing of netmask and our IP address), the function + * checks the ARP cache to see if an entry for the destination IP + * address is found. If so, an Ethernet header is prepended and the + * function returns. If no ARP cache entry is found for the + * destination IP address, the packet in the uip_buf[] is replaced by + * an ARP request packet for the IP address. The IP packet is dropped + * and it is assumed that they higher level protocols (e.g., TCP) + * eventually will retransmit the dropped packet. + * + * If the destination IP address is not on the local network, the IP + * address of the default router is used instead. + * + * When the function returns, a packet is present in the uip_buf[] + * buffer, and the length of the packet is in the global variable + * uip_len. + */ +/*-----------------------------------------------------------------------------------*/ +void +uip_arp_out(void) +{ + struct arp_entry *tabptr; + /* Find the destination IP address in the ARP table and construct + the Ethernet header. If the destination IP addres isn't on the + local network, we use the default router's IP address instead. + + If not ARP table entry is found, we overwrite the original IP + packet with an ARP request for the IP address. */ + + /* Check if the destination address is on the local network. */ + if((IPBUF->destipaddr[0] & uip_arp_netmask[0]) != + (uip_hostaddr[0] & uip_arp_netmask[0]) || + (IPBUF->destipaddr[1] & uip_arp_netmask[1]) != + (uip_hostaddr[1] & uip_arp_netmask[1])) { + /* Destination address was not on the local network, so we need to + use the default router's IP address instead of the destination + address when determining the MAC address. */ + ipaddr[0] = uip_arp_draddr[0]; + ipaddr[1] = uip_arp_draddr[1]; + } else { + /* Else, we use the destination IP address. */ + ipaddr[0] = IPBUF->destipaddr[0]; + ipaddr[1] = IPBUF->destipaddr[1]; + } + + for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { + tabptr = &arp_table[i]; + if(ipaddr[0] == tabptr->ipaddr[0] && + ipaddr[1] == tabptr->ipaddr[1]) + break; + } + + if(i == UIP_ARPTAB_SIZE) { + /* The destination address was not in our ARP table, so we + overwrite the IP packet with an ARP request. */ + + memset(BUF->ethhdr.dest.addr, 0xff, 6); + memset(BUF->dhwaddr.addr, 0x00, 6); + memcpy(BUF->ethhdr.src.addr, uip_ethaddr.addr, 6); + memcpy(BUF->shwaddr.addr, uip_ethaddr.addr, 6); + + BUF->dipaddr[0] = ipaddr[0]; + BUF->dipaddr[1] = ipaddr[1]; + BUF->sipaddr[0] = uip_hostaddr[0]; + BUF->sipaddr[1] = uip_hostaddr[1]; + BUF->opcode = HTONS(ARP_REQUEST); /* ARP request. */ + BUF->hwtype = HTONS(ARP_HWTYPE_ETH); + BUF->protocol = HTONS(UIP_ETHTYPE_IP); + BUF->hwlen = 6; + BUF->protolen = 4; + BUF->ethhdr.type = HTONS(UIP_ETHTYPE_ARP); + + uip_appdata = &uip_buf[40 + UIP_LLH_LEN]; + + uip_len = sizeof(struct arp_hdr); + return; + } + + /* Build an ethernet header. */ + memcpy(IPBUF->ethhdr.dest.addr, tabptr->ethaddr.addr, 6); + memcpy(IPBUF->ethhdr.src.addr, uip_ethaddr.addr, 6); + + IPBUF->ethhdr.type = HTONS(UIP_ETHTYPE_IP); + + uip_len += sizeof(struct uip_eth_hdr); +} +/*-----------------------------------------------------------------------------------*/ + +/** @} */ +/** @} */ diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/uip_arp.h b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/uip_arp.h new file mode 100644 index 000000000..bf9049888 --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/uip_arp.h @@ -0,0 +1,201 @@ +/** + * \addtogroup uip + * @{ + */ + +/** + * \addtogroup uiparp + * @{ + */ + +/** + * \file + * Macros and definitions for the ARP module. + * \author Adam Dunkels + */ + + +/* + * Copyright (c) 2001-2003, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: uip_arp.h,v 1.3.2.2 2003/10/06 15:10:22 adam Exp $ + * + */ + +#ifndef __UIP_ARP_H__ +#define __UIP_ARP_H__ + +#include "uip.h" + + +/** + * Representation of a 48-bit Ethernet address. + */ +struct uip_eth_addr { + u8_t addr[6]; +} __attribute__ ((packed, aligned (1))); + +extern struct uip_eth_addr uip_ethaddr; + +/** + * The Ethernet header. + */ +struct uip_eth_hdr { + struct uip_eth_addr dest; + struct uip_eth_addr src; + u16_t type; +} __attribute__ ((packed)); + +#define UIP_ETHTYPE_ARP 0x0806 +#define UIP_ETHTYPE_IP 0x0800 +#define UIP_ETHTYPE_IP6 0x86dd + + +/* The uip_arp_init() function must be called before any of the other + ARP functions. */ +void uip_arp_init(void); + +/* The uip_arp_ipin() function should be called whenever an IP packet + arrives from the Ethernet. This function refreshes the ARP table or + inserts a new mapping if none exists. The function assumes that an + IP packet with an Ethernet header is present in the uip_buf buffer + and that the length of the packet is in the uip_len variable. */ +void uip_arp_ipin(void); + +/* The uip_arp_arpin() should be called when an ARP packet is received + by the Ethernet driver. This function also assumes that the + Ethernet frame is present in the uip_buf buffer. When the + uip_arp_arpin() function returns, the contents of the uip_buf + buffer should be sent out on the Ethernet if the uip_len variable + is > 0. */ +void uip_arp_arpin(void); + +/* The uip_arp_out() function should be called when an IP packet + should be sent out on the Ethernet. This function creates an + Ethernet header before the IP header in the uip_buf buffer. The + Ethernet header will have the correct Ethernet MAC destination + address filled in if an ARP table entry for the destination IP + address (or the IP address of the default router) is present. If no + such table entry is found, the IP packet is overwritten with an ARP + request and we rely on TCP to retransmit the packet that was + overwritten. In any case, the uip_len variable holds the length of + the Ethernet frame that should be transmitted. */ +void uip_arp_out(void); + +/* The uip_arp_timer() function should be called every ten seconds. It + is responsible for flushing old entries in the ARP table. */ +void uip_arp_timer(void); + +/** @} */ + +/** + * \addtogroup uipconffunc + * @{ + */ + +/** + * Set the default router's IP address. + * + * \param addr A pointer to a 4-byte array containing the IP address + * of the default router. + * + * \hideinitializer + */ +#define uip_setdraddr(addr) do { uip_arp_draddr[0] = addr[0]; \ + uip_arp_draddr[1] = addr[1]; } while(0) + +/** + * Set the netmask. + * + * \param addr A pointer to a 4-byte array containing the IP address + * of the netmask. + * + * \hideinitializer + */ +#define uip_setnetmask(addr) do { uip_arp_netmask[0] = addr[0]; \ + uip_arp_netmask[1] = addr[1]; } while(0) + + +/** + * Get the default router's IP address. + * + * \param addr A pointer to a 4-byte array that will be filled in with + * the IP address of the default router. + * + * \hideinitializer + */ +#define uip_getdraddr(addr) do { addr[0] = uip_arp_draddr[0]; \ + addr[1] = uip_arp_draddr[1]; } while(0) + +/** + * Get the netmask. + * + * \param addr A pointer to a 4-byte array that will be filled in with + * the value of the netmask. + * + * \hideinitializer + */ +#define uip_getnetmask(addr) do { addr[0] = uip_arp_netmask[0]; \ + addr[1] = uip_arp_netmask[1]; } while(0) + + +/** + * Specifiy the Ethernet MAC address. + * + * The ARP code needs to know the MAC address of the Ethernet card in + * order to be able to respond to ARP queries and to generate working + * Ethernet headers. + * + * \note This macro only specifies the Ethernet MAC address to the ARP + * code. It cannot be used to change the MAC address of the Ethernet + * card. + * + * \param eaddr A pointer to a struct uip_eth_addr containing the + * Ethernet MAC address of the Ethernet card. + * + * \hideinitializer + */ +#define uip_setethaddr(eaddr) do {uip_ethaddr.addr[0] = eaddr.addr[0]; \ + uip_ethaddr.addr[1] = eaddr.addr[1];\ + uip_ethaddr.addr[2] = eaddr.addr[2];\ + uip_ethaddr.addr[3] = eaddr.addr[3];\ + uip_ethaddr.addr[4] = eaddr.addr[4];\ + uip_ethaddr.addr[5] = eaddr.addr[5];} while(0) + +/** @} */ + +/** + * \internal Internal variables that are set using the macros + * uip_setdraddr and uip_setnetmask. + */ +extern u16_t uip_arp_draddr[2], uip_arp_netmask[2]; +#endif /* __UIP_ARP_H__ */ + + diff --git a/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/uipopt.h b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/uipopt.h new file mode 100644 index 000000000..9d274d534 --- /dev/null +++ b/20080212/Demo/uIP_Demo_Rowley_ARM7/uip/uipopt.h @@ -0,0 +1,602 @@ +/** + * \defgroup uipopt Configuration options for uIP + * @{ + * + * uIP is configured using the per-project configuration file + * "uipopt.h". This file contains all compile-time options for uIP and + * should be tweaked to match each specific project. The uIP + * distribution contains a documented example "uipopt.h" that can be + * copied and modified for each project. + */ + +/** + * \file + * Configuration options for uIP. + * \author Adam Dunkels + * + * This file is used for tweaking various configuration options for + * uIP. You should make a copy of this file into one of your project's + * directories instead of editing this example "uipopt.h" file that + * comes with the uIP distribution. + */ + +/* + * Copyright (c) 2001-2003, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: uipopt.h,v 1.16.2.5 2003/10/07 13:22:51 adam Exp $ + * + */ + +#ifndef __UIPOPT_H__ +#define __UIPOPT_H__ + +/*------------------------------------------------------------------------------*/ +/** + * \defgroup uipopttypedef uIP type definitions + * @{ + */ + +/** + * The 8-bit unsigned data type. + * + * This may have to be tweaked for your particular compiler. "unsigned + * char" works for most compilers. + */ +typedef unsigned char u8_t; + +/** + * The 16-bit unsigned data type. + * + * This may have to be tweaked for your particular compiler. "unsigned + * short" works for most compilers. + */ +typedef unsigned short u16_t; + +/** + * The statistics data type. + * + * This datatype determines how high the statistics counters are able + * to count. + */ +typedef unsigned short uip_stats_t; + +/** @} */ + +/*------------------------------------------------------------------------------*/ + +/** + * \defgroup uipoptstaticconf Static configuration options + * @{ + * + * These configuration options can be used for setting the IP address + * settings statically, but only if UIP_FIXEDADDR is set to 1. The + * configuration options for a specific node includes IP address, + * netmask and default router as well as the Ethernet address. The + * netmask, default router and Ethernet address are appliciable only + * if uIP should be run over Ethernet. + * + * All of these should be changed to suit your project. +*/ + +/** + * Determines if uIP should use a fixed IP address or not. + * + * If uIP should use a fixed IP address, the settings are set in the + * uipopt.h file. If not, the macros uip_sethostaddr(), + * uip_setdraddr() and uip_setnetmask() should be used instead. + * + * \hideinitializer + */ +#define UIP_FIXEDADDR 1 + +/** + * Ping IP address asignment. + * + * uIP uses a "ping" packets for setting its own IP address if this + * option is set. If so, uIP will start with an empty IP address and + * the destination IP address of the first incoming "ping" (ICMP echo) + * packet will be used for setting the hosts IP address. + * + * \note This works only if UIP_FIXEDADDR is 0. + * + * \hideinitializer + */ +#define UIP_PINGADDRCONF 0 + +#if 0 +#define UIP_IPADDR0 172U /**< The first octet of the IP address of + this uIP node, if UIP_FIXEDADDR is + 1. \hideinitializer */ +#define UIP_IPADDR1 25U /**< The second octet of the IP address of + this uIP node, if UIP_FIXEDADDR is + 1. \hideinitializer */ +#define UIP_IPADDR2 218U /**< The third octet of the IP address of + this uIP node, if UIP_FIXEDADDR is + 1. \hideinitializer */ +#define UIP_IPADDR3 202U /**< The fourth octet of the IP address of + this uIP node, if UIP_FIXEDADDR is + 1. \hideinitializer */ + +#define UIP_NETMASK0 255 /**< The first octet of the netmask of + this uIP node, if UIP_FIXEDADDR is + 1. \hideinitializer */ +#define UIP_NETMASK1 255 /**< The second octet of the netmask of + this uIP node, if UIP_FIXEDADDR is + 1. \hideinitializer */ +#define UIP_NETMASK2 255 /**< The third octet of the netmask of + this uIP node, if UIP_FIXEDADDR is + 1. \hideinitializer */ +#define UIP_NETMASK3 0 /**< The fourth octet of the netmask of + this uIP node, if UIP_FIXEDADDR is + 1. \hideinitializer */ + + +#define UIP_DRIPADDR0 192 /**< The first octet of the IP address of + the default router, if UIP_FIXEDADDR is + 1. \hideinitializer */ +#define UIP_DRIPADDR1 168 /**< The second octet of the IP address of + the default router, if UIP_FIXEDADDR is + 1. \hideinitializer */ +#define UIP_DRIPADDR2 0 /**< The third octet of the IP address of + the default router, if UIP_FIXEDADDR is + 1. \hideinitializer */ +#define UIP_DRIPADDR3 1 /**< The fourth octet of the IP address of + the default router, if UIP_FIXEDADDR is + 1. \hideinitializer */ + +#else + +#define UIP_IPADDR0 172U /**< The first octet of the IP address of + this uIP node, if UIP_FIXEDADDR is + 1. \hideinitializer */ +#define UIP_IPADDR1 25U /**< The second octet of the IP address of + this uIP node, if UIP_FIXEDADDR is + 1. \hideinitializer */ +#define UIP_IPADDR2 218U /**< The third octet of the IP address of + this uIP node, if UIP_FIXEDADDR is + 1. \hideinitializer */ +#define UIP_IPADDR3 202U /**< The fourth octet of the IP address of + this uIP node, if UIP_FIXEDADDR is + 1. \hideinitializer */ + +#define UIP_NETMASK0 255 /**< The first octet of the netmask of + this uIP node, if UIP_FIXEDADDR is + 1. \hideinitializer */ +#define UIP_NETMASK1 255 /**< The second octet of the netmask of + this uIP node, if UIP_FIXEDADDR is + 1. \hideinitializer */ +#define UIP_NETMASK2 255 /**< The third octet of the netmask of + this uIP node, if UIP_FIXEDADDR is + 1. \hideinitializer */ +#define UIP_NETMASK3 0 /**< The fourth octet of the netmask of + this uIP node, if UIP_FIXEDADDR is + 1. \hideinitializer */ + +#define UIP_DRIPADDR0 172 /**< The first octet of the IP address of + the default router, if UIP_FIXEDADDR is + 1. \hideinitializer */ +#define UIP_DRIPADDR1 25 /**< The second octet of the IP address of + the default router, if UIP_FIXEDADDR is + 1. \hideinitializer */ +#define UIP_DRIPADDR2 218 /**< The third octet of the IP address of + the default router, if UIP_FIXEDADDR is + 1. \hideinitializer */ +#define UIP_DRIPADDR3 3 /**< The fourth octet of the IP address of + the default router, if UIP_FIXEDADDR is + 1. \hideinitializer */ + +#endif + +/** + * Specifies if the uIP ARP module should be compiled with a fixed + * Ethernet MAC address or not. + * + * If this configuration option is 0, the macro uip_setethaddr() can + * be used to specify the Ethernet address at run-time. + * + * \hideinitializer + */ +#define UIP_FIXEDETHADDR 0 + +#define UIP_ETHADDR0 0x00 /**< The first octet of the Ethernet + address if UIP_FIXEDETHADDR is + 1. \hideinitializer */ +#define UIP_ETHADDR1 0xbd /**< The second octet of the Ethernet + address if UIP_FIXEDETHADDR is + 1. \hideinitializer */ +#define UIP_ETHADDR2 0x3b /**< The third octet of the Ethernet + address if UIP_FIXEDETHADDR is + 1. \hideinitializer */ +#define UIP_ETHADDR3 0x33 /**< The fourth octet of the Ethernet + address if UIP_FIXEDETHADDR is + 1. \hideinitializer */ +#define UIP_ETHADDR4 0x05 /**< The fifth octet of the Ethernet + address if UIP_FIXEDETHADDR is + 1. \hideinitializer */ +#define UIP_ETHADDR5 0x71 /**< The sixth octet of the Ethernet + address if UIP_FIXEDETHADDR is + 1. \hideinitializer */ + +/** @} */ +/*------------------------------------------------------------------------------*/ +/** + * \defgroup uipoptip IP configuration options + * @{ + * + */ +/** + * The IP TTL (time to live) of IP packets sent by uIP. + * + * This should normally not be changed. + */ +#define UIP_TTL 255 + +/** + * Turn on support for IP packet reassembly. + * + * uIP supports reassembly of fragmented IP packets. This features + * requires an additonal amount of RAM to hold the reassembly buffer + * and the reassembly code size is approximately 700 bytes. The + * reassembly buffer is of the same size as the uip_buf buffer + * (configured by UIP_BUFSIZE). + * + * \note IP packet reassembly is not heavily tested. + * + * \hideinitializer + */ +#define UIP_REASSEMBLY 0 + +/** + * The maximum time an IP fragment should wait in the reassembly + * buffer before it is dropped. + * + */ +#define UIP_REASS_MAXAGE 40 + +/** @} */ + +/*------------------------------------------------------------------------------*/ +/** + * \defgroup uipoptudp UDP configuration options + * @{ + * + * \note The UDP support in uIP is still not entirely complete; there + * is no support for sending or receiving broadcast or multicast + * packets, but it works well enough to support a number of vital + * applications such as DNS queries, though + */ + +/** + * Toggles wether UDP support should be compiled in or not. + * + * \hideinitializer + */ +#define UIP_UDP 0 + +/** + * Toggles if UDP checksums should be used or not. + * + * \note Support for UDP checksums is currently not included in uIP, + * so this option has no function. + * + * \hideinitializer + */ +#define UIP_UDP_CHECKSUMS 0 + +/** + * The maximum amount of concurrent UDP connections. + * + * \hideinitializer + */ +#define UIP_UDP_CONNS 2 + +/** + * The name of the function that should be called when UDP datagrams arrive. + * + * \hideinitializer + */ +#define UIP_UDP_APPCALL udp_appcall + +/** @} */ +/*------------------------------------------------------------------------------*/ +/** + * \defgroup uipopttcp TCP configuration options + * @{ + */ + +/** + * Determines if support for opening connections from uIP should be + * compiled in. + * + * If the applications that are running on top of uIP for this project + * do not need to open outgoing TCP connections, this configration + * option can be turned off to reduce the code size of uIP. + * + * \hideinitializer + */ +#define UIP_ACTIVE_OPEN 1 + +/** + * The maximum number of simultaneously open TCP connections. + * + * Since the TCP connections are statically allocated, turning this + * configuration knob down results in less RAM used. Each TCP + * connection requires approximatly 30 bytes of memory. + * + * \hideinitializer + */ +#define UIP_CONNS 20 + +/** + * The maximum number of simultaneously listening TCP ports. + * + * Each listening TCP port requires 2 bytes of memory. + * + * \hideinitializer + */ +#define UIP_LISTENPORTS 10 + +/** + * The size of the advertised receiver's window. + * + * Should be set low (i.e., to the size of the uip_buf buffer) is the + * application is slow to process incoming data, or high (32768 bytes) + * if the application processes data quickly. + * + * \hideinitializer + */ +#define UIP_RECEIVE_WINDOW 32768 + +/** + * Determines if support for TCP urgent data notification should be + * compiled in. + * + * Urgent data (out-of-band data) is a rarely used TCP feature that + * very seldom would be required. + * + * \hideinitializer + */ +#define UIP_URGDATA 1 + +/** + * The initial retransmission timeout counted in timer pulses. + * + * This should not be changed. + */ +#define UIP_RTO 3 + +/** + * The maximum number of times a segment should be retransmitted + * before the connection should be aborted. + * + * This should not be changed. + */ +#define UIP_MAXRTX 8 + +/** + * The maximum number of times a SYN segment should be retransmitted + * before a connection request should be deemed to have been + * unsuccessful. + * + * This should not need to be changed. + */ +#define UIP_MAXSYNRTX 3 + +/** + * The TCP maximum segment size. + * + * This is should not be to set to more than UIP_BUFSIZE - UIP_LLH_LEN - 40. + */ +#define UIP_TCP_MSS (UIP_BUFSIZE - UIP_LLH_LEN - 40) + +/** + * How long a connection should stay in the TIME_WAIT state. + * + * This configiration option has no real implication, and it should be + * left untouched. + */ +#define UIP_TIME_WAIT_TIMEOUT 120 + + +/** @} */ +/*------------------------------------------------------------------------------*/ +/** + * \defgroup uipoptarp ARP configuration options + * @{ + */ + +/** + * The size of the ARP table. + * + * This option should be set to a larger value if this uIP node will + * have many connections from the local network. + * + * \hideinitializer + */ +#define UIP_ARPTAB_SIZE 8 + +/** + * The maxium age of ARP table entries measured in 10ths of seconds. + * + * An UIP_ARP_MAXAGE of 120 corresponds to 20 minutes (BSD + * default). + */ +#define UIP_ARP_MAXAGE 120 + +/** @} */ + +/*------------------------------------------------------------------------------*/ + +/** + * \defgroup uipoptgeneral General configuration options + * @{ + */ + +/** + * The size of the uIP packet buffer. + * + * The uIP packet buffer should not be smaller than 60 bytes, and does + * not need to be larger than 1500 bytes. Lower size results in lower + * TCP throughput, larger size results in higher TCP throughput. + * + * \hideinitializer + */ +#define UIP_BUFSIZE 2048 + + +/** + * Determines if statistics support should be compiled in. + * + * The statistics is useful for debugging and to show the user. + * + * \hideinitializer + */ +#define UIP_STATISTICS 1 + +/** + * Determines if logging of certain events should be compiled in. + * + * This is useful mostly for debugging. The function uip_log() + * must be implemented to suit the architecture of the project, if + * logging is turned on. + * + * \hideinitializer + */ +#define UIP_LOGGING 0 + +/** + * Print out a uIP log message. + * + * This function must be implemented by the module that uses uIP, and + * is called by uIP whenever a log message is generated. + */ +void uip_log(char *msg); + +/** + * The link level header length. + * + * This is the offset into the uip_buf where the IP header can be + * found. For Ethernet, this should be set to 14. For SLIP, this + * should be set to 0. + * + * \hideinitializer + */ +#define UIP_LLH_LEN 14 + + +/** @} */ +/*------------------------------------------------------------------------------*/ +/** + * \defgroup uipoptcpu CPU architecture configuration + * @{ + * + * The CPU architecture configuration is where the endianess of the + * CPU on which uIP is to be run is specified. Most CPUs today are + * little endian, and the most notable exception are the Motorolas + * which are big endian. The BYTE_ORDER macro should be changed to + * reflect the CPU architecture on which uIP is to be run. + */ +#ifndef LITTLE_ENDIAN +#define LITTLE_ENDIAN 3412 +#endif /* LITTLE_ENDIAN */ +#ifndef BIG_ENDIAN +#define BIG_ENDIAN 1234 +#endif /* BIGE_ENDIAN */ + +/** + * The byte order of the CPU architecture on which uIP is to be run. + * + * This option can be either BIG_ENDIAN (Motorola byte order) or + * LITTLE_ENDIAN (Intel byte order). + * + * \hideinitializer + */ +#ifndef BYTE_ORDER +#define BYTE_ORDER LITTLE_ENDIAN +#endif /* BYTE_ORDER */ + +/** @} */ +/*------------------------------------------------------------------------------*/ + +/** + * \defgroup uipoptapp Appication specific configurations + * @{ + * + * An uIP application is implemented using a single application + * function that is called by uIP whenever a TCP/IP event occurs. The + * name of this function must be registered with uIP at compile time + * using the UIP_APPCALL definition. + * + * uIP applications can store the application state within the + * uip_conn structure by specifying the size of the application + * structure with the UIP_APPSTATE_SIZE macro. + * + * The file containing the definitions must be included in the + * uipopt.h file. + * + * The following example illustrates how this can look. + \code + +void httpd_appcall(void); +#define UIP_APPCALL httpd_appcall + +struct httpd_state { + u8_t state; + u16_t count; + char *dataptr; + char *script; +}; +#define UIP_APPSTATE_SIZE (sizeof(struct httpd_state)) + \endcode + */ + +/** + * \var #define UIP_APPCALL + * + * The name of the application function that uIP should call in + * response to TCP/IP events. + * + */ + +/** + * \var #define UIP_APPSTATE_SIZE + * + * The size of the application state that is to be stored in the + * uip_conn structure. + */ +/** @} */ + +/* Include the header file for the application program that should be + used. If you don't use the example web server, you should change + this. */ +#include "httpd.h" + + +#endif /* __UIPOPT_H__ */ diff --git a/20080212/License/license.txt b/20080212/License/license.txt new file mode 100644 index 000000000..1787b6ad1 --- /dev/null +++ b/20080212/License/license.txt @@ -0,0 +1,399 @@ +The FreeRTOS.org source code is licensed by the modified GNU General Public +License (GPL) text provided below. The FreeRTOS download also includes +demo application source code, some of which is provided by third parties +AND IS LICENSED SEPARATELY FROM FREERTOS.ORG. + +For the avoidance of any doubt refer to the comment included at the top +of each source and header file for license and copyright information. + +This is a list of files for which Richard Barry is not the copyright owner +and are NOT COVERED BY THE GPL. + + +1) Various header files provided by silicon manufacturers and tool vendors + that define processor specific memory addresses and utility macros. + Permission has been granted by the various copyright holders for these + files to be included in the FreeRTOS download. Users must ensure license + conditions are adhered to for any use other than compilation of the + FreeRTOS demo application. + +2) The uIP TCP/IP stack the copyright of which is held by Adam Dunkels. + Users must ensure the open source license conditions stated at the top + of each uIP source file is understood and adhered to. + +3) The lwIP TCP/IP stack the copyright of which is held by the Swedish + Institute of Computer Science. Users must ensure the open source license + conditions stated at the top of each lwIP source file is understood and + adhered to. + +4) All files contained within the FreeRTOS\Demo\CORTEX_LM3S102_GCC\hw_include + and FreeRTOS\Demo\CORTEX_LM3S316_IAR\hw_include directories. The + copyright of these files is owned by Luminary Micro. Permission has been + granted by Luminary Micro for these files to be included in the FreeRTOS + download. Users must ensure the license conditions stated in the EULA.txt + file located in the same directories is understood and adhered at all + times for all files in those directories. + +5) The files contained within FreeRTOS\Demo\WizNET_DEMO_TERN_186\tern_code, + which are slightly modified versions of code provided by and copyright to + Tern Inc. + +Errors and omissions should be reported to Richard Barry, contact details for +whom can be obtained from http://www.FreeRTOS.org. + + + + + +The GPL license text follows. + +An exception to this license exists that can be applied should you +wish to use FreeRTOS in a work that includes commercial or +proprietary code without being obliged to provide source code for the +proprietary components. See the licensing section of +http://www.FreeRTOS.org for full details. +-------------------------------------------------------------------- + + + + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc. + 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. By contrast, the GNU General Public +License is intended to guarantee your freedom to share and change free +software--to make sure the software is free for all its users. This +General Public License applies to most of the Free Software +Foundation's software and to any other program whose authors commit to +using it. (Some other Free Software Foundation software is covered by +the GNU Library General Public License instead.) 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You may copy and distribute verbatim copies of the Program's +source code as you receive it, in any medium, provided that you +conspicuously and appropriately publish on each copy an appropriate +copyright notice and disclaimer of warranty; keep intact all the +notices that refer to this License and to the absence of any warranty; +and give any other recipients of the Program a copy of this License +along with the Program. + +You may charge a fee for the physical act of transferring a copy, and +you may at your option offer warranty protection in exchange for a fee. + + 2. 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IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING +WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR +REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, +INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING +OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED +TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY +YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER +PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. + + END OF TERMS AND CONDITIONS + + How to Apply These Terms to Your New Programs + + If you develop a new program, and you want it to be of the greatest +possible use to the public, the best way to achieve this is to make it +free software which everyone can redistribute and change under these terms. + + To do so, attach the following notices to the program. It is safest +to attach them to the start of each source file to most effectively +convey the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + + Copyright (C) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) year name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + , 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Library General +Public License instead of this License. + diff --git a/20080212/Source/croutine.c b/20080212/Source/croutine.c new file mode 100644 index 000000000..c8f0f2403 --- /dev/null +++ b/20080212/Source/croutine.c @@ -0,0 +1,352 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#include "FreeRTOS.h" +#include "task.h" +#include "croutine.h" + +/* Lists for ready and blocked co-routines. --------------------*/ +static xList pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ]; /*< Prioritised ready co-routines. */ +static xList xDelayedCoRoutineList1; /*< Delayed co-routines. */ +static xList xDelayedCoRoutineList2; /*< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */ +static xList * pxDelayedCoRoutineList; /*< Points to the delayed co-routine list currently being used. */ +static xList * pxOverflowDelayedCoRoutineList; /*< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */ +static xList xPendingReadyList; /*< Holds co-routines that have been readied by an external event. They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */ + +/* Other file private variables. --------------------------------*/ +corCRCB * pxCurrentCoRoutine = NULL; +static unsigned portBASE_TYPE uxTopCoRoutineReadyPriority = 0; +static portTickType xCoRoutineTickCount = 0; + +/* The initial state of the co-routine when it is created. */ +#define corINITIAL_STATE ( 0 ) + +/* + * Place the co-routine represented by pxCRCB into the appropriate ready queue + * for the priority. It is inserted at the end of the list. + * + * This macro accesses the co-routine ready lists and therefore must not be + * used from within an ISR. + */ +#define prvAddCoRoutineToReadyQueue( pxCRCB ) \ +{ \ + if( pxCRCB->uxPriority > uxTopCoRoutineReadyPriority ) \ + { \ + uxTopCoRoutineReadyPriority = pxCRCB->uxPriority; \ + } \ + vListInsertEnd( ( xList * ) &( pxReadyCoRoutineLists[ pxCRCB->uxPriority ] ), &( pxCRCB->xGenericListItem ) ); \ +} + +/* + * Utility to ready all the lists used by the scheduler. This is called + * automatically upon the creation of the first co-routine. + */ +static void prvInitialiseCoRoutineLists( void ); + +/* + * Co-routines that are readied by an interrupt cannot be placed directly into + * the ready lists (there is no mutual exclusion). Instead they are placed in + * in the pending ready list in order that they can later be moved to the ready + * list by the co-routine scheduler. + */ +static inline void prvCheckPendingReadyList( void ); + +/* + * Macro that looks at the list of co-routines that are currently delayed to + * see if any require waking. + * + * Co-routines are stored in the queue in the order of their wake time - + * meaning once one co-routine has been found whose timer has not expired + * we need not look any further down the list. + */ +static inline void prvCheckDelayedList( void ); + +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, unsigned portBASE_TYPE uxPriority, unsigned portBASE_TYPE uxIndex ) +{ +signed portBASE_TYPE xReturn; +corCRCB *pxCoRoutine; + + /* Allocate the memory that will store the co-routine control block. */ + pxCoRoutine = ( corCRCB * ) pvPortMalloc( sizeof( corCRCB ) ); + if( pxCoRoutine ) + { + /* If pxCurrentCoRoutine is NULL then this is the first co-routine to + be created and the co-routine data structures need initialising. */ + if( pxCurrentCoRoutine == NULL ) + { + pxCurrentCoRoutine = pxCoRoutine; + prvInitialiseCoRoutineLists(); + } + + /* Check the priority is within limits. */ + if( uxPriority >= configMAX_CO_ROUTINE_PRIORITIES ) + { + uxPriority = configMAX_CO_ROUTINE_PRIORITIES - 1; + } + + /* Fill out the co-routine control block from the function parameters. */ + pxCoRoutine->uxState = corINITIAL_STATE; + pxCoRoutine->uxPriority = uxPriority; + pxCoRoutine->uxIndex = uxIndex; + pxCoRoutine->pxCoRoutineFunction = pxCoRoutineCode; + + /* Initialise all the other co-routine control block parameters. */ + vListInitialiseItem( &( pxCoRoutine->xGenericListItem ) ); + vListInitialiseItem( &( pxCoRoutine->xEventListItem ) ); + + /* Set the co-routine control block as a link back from the xListItem. + This is so we can get back to the containing CRCB from a generic item + in a list. */ + listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xGenericListItem ), pxCoRoutine ); + listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xEventListItem ), pxCoRoutine ); + + /* Event lists are always in priority order. */ + listSET_LIST_ITEM_VALUE( &( pxCoRoutine->xEventListItem ), configMAX_PRIORITIES - ( portTickType ) uxPriority ); + + /* Now the co-routine has been initialised it can be added to the ready + list at the correct priority. */ + prvAddCoRoutineToReadyQueue( pxCoRoutine ); + + xReturn = pdPASS; + } + else + { + xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +void vCoRoutineAddToDelayedList( portTickType xTicksToDelay, xList *pxEventList ) +{ +portTickType xTimeToWake; + + /* Calculate the time to wake - this may overflow but this is + not a problem. */ + xTimeToWake = xCoRoutineTickCount + xTicksToDelay; + + /* We must remove ourselves from the ready list before adding + ourselves to the blocked list as the same list item is used for + both lists. */ + vListRemove( ( xListItem * ) &( pxCurrentCoRoutine->xGenericListItem ) ); + + /* The list item will be inserted in wake time order. */ + listSET_LIST_ITEM_VALUE( &( pxCurrentCoRoutine->xGenericListItem ), xTimeToWake ); + + if( xTimeToWake < xCoRoutineTickCount ) + { + /* Wake time has overflowed. Place this item in the + overflow list. */ + vListInsert( ( xList * ) pxOverflowDelayedCoRoutineList, ( xListItem * ) &( pxCurrentCoRoutine->xGenericListItem ) ); + } + else + { + /* The wake time has not overflowed, so we can use the + current block list. */ + vListInsert( ( xList * ) pxDelayedCoRoutineList, ( xListItem * ) &( pxCurrentCoRoutine->xGenericListItem ) ); + } + + if( pxEventList ) + { + /* Also add the co-routine to an event list. If this is done then the + function must be called with interrupts disabled. */ + vListInsert( pxEventList, &( pxCurrentCoRoutine->xEventListItem ) ); + } +} +/*-----------------------------------------------------------*/ + +static inline void prvCheckPendingReadyList( void ) +{ + /* Are there any co-routines waiting to get moved to the ready list? These + are co-routines that have been readied by an ISR. The ISR cannot access + the ready lists itself. */ + while( !listLIST_IS_EMPTY( &xPendingReadyList ) ) + { + corCRCB *pxUnblockedCRCB; + + /* The pending ready list can be accessed by an ISR. */ + portDISABLE_INTERRUPTS(); + { + pxUnblockedCRCB = ( corCRCB * ) listGET_OWNER_OF_HEAD_ENTRY( (&xPendingReadyList) ); + vListRemove( &( pxUnblockedCRCB->xEventListItem ) ); + } + portENABLE_INTERRUPTS(); + + vListRemove( &( pxUnblockedCRCB->xGenericListItem ) ); + prvAddCoRoutineToReadyQueue( pxUnblockedCRCB ); + } +} +/*-----------------------------------------------------------*/ + +static inline void prvCheckDelayedList( void ) +{ +static portTickType xLastTickCount, xPassedTicks; +corCRCB *pxCRCB; + + xPassedTicks = xTaskGetTickCount() - xLastTickCount; + while( xPassedTicks ) + { + xCoRoutineTickCount++; + xPassedTicks--; + + /* If the tick count has overflowed we need to swap the ready lists. */ + if( xCoRoutineTickCount == 0 ) + { + xList * pxTemp; + + /* Tick count has overflowed so we need to swap the delay lists. If there are + any items in pxDelayedCoRoutineList here then there is an error! */ + pxTemp = pxDelayedCoRoutineList; + pxDelayedCoRoutineList = pxOverflowDelayedCoRoutineList; + pxOverflowDelayedCoRoutineList = pxTemp; + } + + /* See if this tick has made a timeout expire. */ + while( ( pxCRCB = ( corCRCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedCoRoutineList ) ) != NULL ) + { + if( xCoRoutineTickCount < listGET_LIST_ITEM_VALUE( &( pxCRCB->xGenericListItem ) ) ) + { + /* Timeout not yet expired. */ + break; + } + + portDISABLE_INTERRUPTS(); + { + /* The event could have occurred just before this critical + section. If this is the case then the generic list item will + have been moved to the pending ready list and the following + line is still valid. Also the pvContainer parameter will have + been set to NULL so the following lines are also valid. */ + vListRemove( &( pxCRCB->xGenericListItem ) ); + + /* Is the co-routine waiting on an event also? */ + if( pxCRCB->xEventListItem.pvContainer ) + { + vListRemove( &( pxCRCB->xEventListItem ) ); + } + } + portENABLE_INTERRUPTS(); + + prvAddCoRoutineToReadyQueue( pxCRCB ); + } + } + + xLastTickCount = xCoRoutineTickCount; +} +/*-----------------------------------------------------------*/ + +void vCoRoutineSchedule( void ) +{ + /* See if any co-routines readied by events need moving to the ready lists. */ + prvCheckPendingReadyList(); + + /* See if any delayed co-routines have timed out. */ + prvCheckDelayedList(); + + /* Find the highest priority queue that contains ready co-routines. */ + while( listLIST_IS_EMPTY( &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ) ) + { + if( uxTopCoRoutineReadyPriority == 0 ) + { + /* No more co-routines to check. */ + return; + } + --uxTopCoRoutineReadyPriority; + } + + /* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the co-routines + of the same priority get an equal share of the processor time. */ + listGET_OWNER_OF_NEXT_ENTRY( pxCurrentCoRoutine, &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ); + + /* Call the co-routine. */ + ( pxCurrentCoRoutine->pxCoRoutineFunction )( pxCurrentCoRoutine, pxCurrentCoRoutine->uxIndex ); + + return; +} +/*-----------------------------------------------------------*/ + +static void prvInitialiseCoRoutineLists( void ) +{ +unsigned portBASE_TYPE uxPriority; + + for( uxPriority = 0; uxPriority < configMAX_CO_ROUTINE_PRIORITIES; uxPriority++ ) + { + vListInitialise( ( xList * ) &( pxReadyCoRoutineLists[ uxPriority ] ) ); + } + + vListInitialise( ( xList * ) &xDelayedCoRoutineList1 ); + vListInitialise( ( xList * ) &xDelayedCoRoutineList2 ); + vListInitialise( ( xList * ) &xPendingReadyList ); + + /* Start with pxDelayedCoRoutineList using list1 and the + pxOverflowDelayedCoRoutineList using list2. */ + pxDelayedCoRoutineList = &xDelayedCoRoutineList1; + pxOverflowDelayedCoRoutineList = &xDelayedCoRoutineList2; +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xCoRoutineRemoveFromEventList( const xList *pxEventList ) +{ +corCRCB *pxUnblockedCRCB; +signed portBASE_TYPE xReturn; + + /* This function is called from within an interrupt. It can only access + event lists and the pending ready list. */ + pxUnblockedCRCB = ( corCRCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); + vListRemove( &( pxUnblockedCRCB->xEventListItem ) ); + vListInsertEnd( ( xList * ) &( xPendingReadyList ), &( pxUnblockedCRCB->xEventListItem ) ); + + if( pxUnblockedCRCB->uxPriority >= pxCurrentCoRoutine->uxPriority ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + + return xReturn; +} + diff --git a/20080212/Source/include/FreeRTOS.h b/20080212/Source/include/FreeRTOS.h new file mode 100644 index 000000000..b9f4aa26a --- /dev/null +++ b/20080212/Source/include/FreeRTOS.h @@ -0,0 +1,148 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef INC_FREERTOS_H +#define INC_FREERTOS_H + + +/* + * Include the generic headers required for the FreeRTOS port being used. + */ +#include + +/* Basic FreeRTOS definitions. */ +#include "projdefs.h" + +/* Application specific configuration options. */ +#include "FreeRTOSConfig.h" + +/* Definitions specific to the port being used. */ +#include "portable.h" + + + + + + + +/* + * Check all the required application specific macros have been defined. + * These macros are application specific and (as downloaded) are defined + * within FreeRTOSConfig.h. + */ + +#ifndef configUSE_PREEMPTION + #error Missing definition: configUSE_PREEMPTION should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_IDLE_HOOK + #error Missing definition: configUSE_IDLE_HOOK should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_TICK_HOOK + #error Missing definition: configUSE_TICK_HOOK should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_CO_ROUTINES + #error Missing definition: configUSE_CO_ROUTINES should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef INCLUDE_vTaskPrioritySet + #error Missing definition: INCLUDE_vTaskPrioritySet should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef INCLUDE_uxTaskPriorityGet + #error Missing definition: INCLUDE_uxTaskPriorityGet should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef INCLUDE_vTaskDelete + #error Missing definition: INCLUDE_vTaskDelete should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef INCLUDE_vTaskCleanUpResources + #error Missing definition: INCLUDE_vTaskCleanUpResources should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef INCLUDE_vTaskSuspend + #error Missing definition: INCLUDE_vTaskSuspend should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef INCLUDE_vTaskDelayUntil + #error Missing definition: INCLUDE_vTaskDelayUntil should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef INCLUDE_vTaskDelay + #error Missing definition: INCLUDE_vTaskDelay should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_16_BIT_TICKS + #error Missing definition: configUSE_16_BIT_TICKS should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_RECURSIVE_MUTEXES + #define configUSE_RECURSIVE_MUTEXES 0 +#endif + +#ifndef configUSE_MUTEXES + #define configUSE_MUTEXES 0 +#endif + +#ifndef configUSE_COUNTING_SEMAPHORES + #define configUSE_COUNTING_SEMAPHORES 0 +#endif + +#ifndef configUSE_ALTERNATIVE_API + #define configUSE_ALTERNATIVE_API 0 +#endif + +#if ( configUSE_MUTEXES == 1 ) + /* xTaskGetCurrentTaskHandle is used by the priority inheritance mechanism + within the mutex implementation so must be available if mutexes are used. */ + #undef INCLUDE_xTaskGetCurrentTaskHandle + #define INCLUDE_xTaskGetCurrentTaskHandle 1 +#else + #ifndef INCLUDE_xTaskGetCurrentTaskHandle + #define INCLUDE_xTaskGetCurrentTaskHandle 0 + #endif +#endif + +#endif /* INC_FREERTOS_H */ diff --git a/20080212/Source/include/croutine.h b/20080212/Source/include/croutine.h new file mode 100644 index 000000000..07f523083 --- /dev/null +++ b/20080212/Source/include/croutine.h @@ -0,0 +1,730 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ +#ifndef CO_ROUTINE_H +#define CO_ROUTINE_H + +#include "list.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Used to hide the implementation of the co-routine control block. The +control block structure however has to be included in the header due to +the macro implementation of the co-routine functionality. */ +typedef void * xCoRoutineHandle; + +/* Defines the prototype to which co-routine functions must conform. */ +typedef void (*crCOROUTINE_CODE)( xCoRoutineHandle, unsigned portBASE_TYPE ); + +typedef struct corCoRoutineControlBlock +{ + crCOROUTINE_CODE pxCoRoutineFunction; + xListItem xGenericListItem; /*< List item used to place the CRCB in ready and blocked queues. */ + xListItem xEventListItem; /*< List item used to place the CRCB in event lists. */ + unsigned portBASE_TYPE uxPriority; /*< The priority of the co-routine in relation to other co-routines. */ + unsigned portBASE_TYPE uxIndex; /*< Used to distinguish between co-routines when multiple co-routines use the same co-routine function. */ + unsigned portSHORT uxState; /*< Used internally by the co-routine implementation. */ +} corCRCB; /* Co-routine control block. Note must be identical in size down to uxPriority with tskTCB. */ + +/** + * croutine. h + *
    + portBASE_TYPE xCoRoutineCreate(
+                                 crCOROUTINE_CODE pxCoRoutineCode,
+                                 unsigned portBASE_TYPE uxPriority,
+                                 unsigned portBASE_TYPE uxIndex
+                               );
    + * + * Create a new co-routine and add it to the list of co-routines that are + * ready to run. + * + * @param pxCoRoutineCode Pointer to the co-routine function. Co-routine + * functions require special syntax - see the co-routine section of the WEB + * documentation for more information. + * + * @param uxPriority The priority with respect to other co-routines at which + * the co-routine will run. + * + * @param uxIndex Used to distinguish between different co-routines that + * execute the same function. See the example below and the co-routine section + * of the WEB documentation for further information. + * + * @return pdPASS if the co-routine was successfully created and added to a ready + * list, otherwise an error code defined with ProjDefs.h. + * + * Example usage: + 
    + // Co-routine to be created.
+ void vFlashCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ // This may not be necessary for const variables.
+ static const char cLedToFlash[ 2 ] = { 5, 6 };
+ static const portTickType xTimeToDelay[ 2 ] = { 200, 400 };
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+         // This co-routine just delays for a fixed period, then toggles
+         // an LED.  Two co-routines are created using this function, so
+         // the uxIndex parameter is used to tell the co-routine which
+         // LED to flash and how long to delay.  This assumes xQueue has
+         // already been created.
+         vParTestToggleLED( cLedToFlash[ uxIndex ] );
+         crDELAY( xHandle, uxFlashRates[ uxIndex ] );
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }
+
+ // Function that creates two co-routines.
+ void vOtherFunction( void )
+ {
+ unsigned char ucParameterToPass;
+ xTaskHandle xHandle;
+		
+     // Create two co-routines at priority 0.  The first is given index 0
+     // so (from the code above) toggles LED 5 every 200 ticks.  The second
+     // is given index 1 so toggles LED 6 every 400 ticks.
+     for( uxIndex = 0; uxIndex < 2; uxIndex++ )
+     {
+         xCoRoutineCreate( vFlashCoRoutine, 0, uxIndex );
+     }
+ }
+
    + * \defgroup xCoRoutineCreate xCoRoutineCreate + * \ingroup Tasks + */ +signed portBASE_TYPE xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, unsigned portBASE_TYPE uxPriority, unsigned portBASE_TYPE uxIndex ); + + +/** + * croutine. h + *
    + void vCoRoutineSchedule( void );
    + * + * Run a co-routine. + * + * vCoRoutineSchedule() executes the highest priority co-routine that is able + * to run. The co-routine will execute until it either blocks, yields or is + * preempted by a task. Co-routines execute cooperatively so one + * co-routine cannot be preempted by another, but can be preempted by a task. + * + * If an application comprises of both tasks and co-routines then + * vCoRoutineSchedule should be called from the idle task (in an idle task + * hook). + * + * Example usage: + 
    + // This idle task hook will schedule a co-routine each time it is called.
+ // The rest of the idle task will execute between co-routine calls.
+ void vApplicationIdleHook( void )
+ {
+	vCoRoutineSchedule();
+ }
+
+ // Alternatively, if you do not require any other part of the idle task to
+ // execute, the idle task hook can call vCoRoutineScheduler() within an
+ // infinite loop.
+ void vApplicationIdleHook( void )
+ {
+    for( ;; )
+    {
+        vCoRoutineSchedule();
+    }
+ }
+
    + * \defgroup vCoRoutineSchedule vCoRoutineSchedule + * \ingroup Tasks + */ +void vCoRoutineSchedule( void ); + +/** + * croutine. h + * 
    + crSTART( xCoRoutineHandle xHandle );
    + * + * This macro MUST always be called at the start of a co-routine function. + * + * Example usage: + 
    + // Co-routine to be created.
+ void vACoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static portLONG ulAVariable;
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+          // Co-routine functionality goes here.
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }
    + * \defgroup crSTART crSTART + * \ingroup Tasks + */ +#define crSTART( pxCRCB ) switch( ( ( corCRCB * )pxCRCB )->uxState ) { case 0: + +/** + * croutine. h + * 
    + crEND();
    + * + * This macro MUST always be called at the end of a co-routine function. + * + * Example usage: + 
    + // Co-routine to be created.
+ void vACoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static portLONG ulAVariable;
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+          // Co-routine functionality goes here.
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }
    + * \defgroup crSTART crSTART + * \ingroup Tasks + */ +#define crEND() } + +/* + * These macros are intended for internal use by the co-routine implementation + * only. The macros should not be used directly by application writers. + */ +#define crSET_STATE0( xHandle ) ( ( corCRCB * )xHandle)->uxState = (__LINE__ * 2); return; case (__LINE__ * 2): +#define crSET_STATE1( xHandle ) ( ( corCRCB * )xHandle)->uxState = ((__LINE__ * 2)+1); return; case ((__LINE__ * 2)+1): + +/** + * croutine. h + *
    + crDELAY( xCoRoutineHandle xHandle, portTickType xTicksToDelay );
    + * + * Delay a co-routine for a fixed period of time. + * + * crDELAY can only be called from the co-routine function itself - not + * from within a function called by the co-routine function. This is because + * co-routines do not maintain their own stack. + * + * @param xHandle The handle of the co-routine to delay. This is the xHandle + * parameter of the co-routine function. + * + * @param xTickToDelay The number of ticks that the co-routine should delay + * for. The actual amount of time this equates to is defined by + * configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant portTICK_RATE_MS + * can be used to convert ticks to milliseconds. + * + * Example usage: + 
    + // Co-routine to be created.
+ void vACoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ // This may not be necessary for const variables.
+ // We are to delay for 200ms.
+ static const xTickType xDelayTime = 200 / portTICK_RATE_MS;
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+        // Delay for 200ms.
+        crDELAY( xHandle, xDelayTime );
+
+        // Do something here.
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }
    + * \defgroup crDELAY crDELAY + * \ingroup Tasks + */ +#define crDELAY( xHandle, xTicksToDelay ) \ + if( xTicksToDelay > 0 ) \ + { \ + vCoRoutineAddToDelayedList( xTicksToDelay, NULL ); \ + } \ + crSET_STATE0( xHandle ); + +/** + * 
    + crQUEUE_SEND(
+                  xCoRoutineHandle xHandle,
+                  xQueueHandle pxQueue,
+                  void *pvItemToQueue,
+                  portTickType xTicksToWait,
+                  portBASE_TYPE *pxResult
+             )
    + * + * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine + * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks. + * + * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas + * xQueueSend() and xQueueReceive() can only be used from tasks. + * + * crQUEUE_SEND can only be called from the co-routine function itself - not + * from within a function called by the co-routine function. This is because + * co-routines do not maintain their own stack. + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xHandle The handle of the calling co-routine. This is the xHandle + * parameter of the co-routine function. + * + * @param pxQueue The handle of the queue on which the data will be posted. + * The handle is obtained as the return value when the queue is created using + * the xQueueCreate() API function. + * + * @param pvItemToQueue A pointer to the data being posted onto the queue. + * The number of bytes of each queued item is specified when the queue is + * created. This number of bytes is copied from pvItemToQueue into the queue + * itself. + * + * @param xTickToDelay The number of ticks that the co-routine should block + * to wait for space to become available on the queue, should space not be + * available immediately. The actual amount of time this equates to is defined + * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant + * portTICK_RATE_MS can be used to convert ticks to milliseconds (see example + * below). + * + * @param pxResult The variable pointed to by pxResult will be set to pdPASS if + * data was successfully posted onto the queue, otherwise it will be set to an + * error defined within ProjDefs.h. + * + * Example usage: + 
    + // Co-routine function that blocks for a fixed period then posts a number onto
+ // a queue.
+ static void prvCoRoutineFlashTask( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static portBASE_TYPE xNumberToPost = 0;
+ static portBASE_TYPE xResult;
+
+    // Co-routines must begin with a call to crSTART().
+    crSTART( xHandle );
+
+    for( ;; )
+    {
+        // This assumes the queue has already been created.
+        crQUEUE_SEND( xHandle, xCoRoutineQueue, &xNumberToPost, NO_DELAY, &xResult );
+
+        if( xResult != pdPASS )
+        {
+            // The message was not posted!
+        }
+
+        // Increment the number to be posted onto the queue.
+        xNumberToPost++;
+
+        // Delay for 100 ticks.
+        crDELAY( xHandle, 100 );
+    }
+
+    // Co-routines must end with a call to crEND().
+    crEND();
+ }
    + * \defgroup crQUEUE_SEND crQUEUE_SEND + * \ingroup Tasks + */ +#define crQUEUE_SEND( xHandle, pxQueue, pvItemToQueue, xTicksToWait, pxResult ) \ +{ \ + *pxResult = xQueueCRSend( pxQueue, pvItemToQueue, xTicksToWait ); \ + if( *pxResult == errQUEUE_BLOCKED ) \ + { \ + crSET_STATE0( xHandle ); \ + *pxResult = xQueueCRSend( pxQueue, pvItemToQueue, 0 ); \ + } \ + if( *pxResult == errQUEUE_YIELD ) \ + { \ + crSET_STATE1( xHandle ); \ + *pxResult = pdPASS; \ + } \ +} + +/** + * croutine. h + * 
    +  crQUEUE_RECEIVE(
+                     xCoRoutineHandle xHandle,
+                     xQueueHandle pxQueue,
+                     void *pvBuffer,
+                     portTickType xTicksToWait,
+                     portBASE_TYPE *pxResult
+                 )
    + * + * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine + * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks. + * + * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas + * xQueueSend() and xQueueReceive() can only be used from tasks. + * + * crQUEUE_RECEIVE can only be called from the co-routine function itself - not + * from within a function called by the co-routine function. This is because + * co-routines do not maintain their own stack. + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xHandle The handle of the calling co-routine. This is the xHandle + * parameter of the co-routine function. + * + * @param pxQueue The handle of the queue from which the data will be received. + * The handle is obtained as the return value when the queue is created using + * the xQueueCreate() API function. + * + * @param pvBuffer The buffer into which the received item is to be copied. + * The number of bytes of each queued item is specified when the queue is + * created. This number of bytes is copied into pvBuffer. + * + * @param xTickToDelay The number of ticks that the co-routine should block + * to wait for data to become available from the queue, should data not be + * available immediately. The actual amount of time this equates to is defined + * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant + * portTICK_RATE_MS can be used to convert ticks to milliseconds (see the + * crQUEUE_SEND example). + * + * @param pxResult The variable pointed to by pxResult will be set to pdPASS if + * data was successfully retrieved from the queue, otherwise it will be set to + * an error code as defined within ProjDefs.h. + * + * Example usage: + 
    + // A co-routine receives the number of an LED to flash from a queue.  It
+ // blocks on the queue until the number is received.
+ static void prvCoRoutineFlashWorkTask( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static portBASE_TYPE xResult;
+ static unsigned portBASE_TYPE uxLEDToFlash;
+
+    // All co-routines must start with a call to crSTART().
+    crSTART( xHandle );
+
+    for( ;; )
+    {
+        // Wait for data to become available on the queue.
+        crQUEUE_RECEIVE( xHandle, xCoRoutineQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
+
+        if( xResult == pdPASS )
+        {
+            // We received the LED to flash - flash it!
+            vParTestToggleLED( uxLEDToFlash );
+        }
+    }
+
+    crEND();
+ }
    + * \defgroup crQUEUE_RECEIVE crQUEUE_RECEIVE + * \ingroup Tasks + */ +#define crQUEUE_RECEIVE( xHandle, pxQueue, pvBuffer, xTicksToWait, pxResult ) \ +{ \ + *pxResult = xQueueCRReceive( pxQueue, pvBuffer, xTicksToWait ); \ + if( *pxResult == errQUEUE_BLOCKED ) \ + { \ + crSET_STATE0( xHandle ); \ + *pxResult = xQueueCRReceive( pxQueue, pvBuffer, 0 ); \ + } \ + if( *pxResult == errQUEUE_YIELD ) \ + { \ + crSET_STATE1( xHandle ); \ + *pxResult = pdPASS; \ + } \ +} + +/** + * croutine. h + * 
    +  crQUEUE_SEND_FROM_ISR(
+                            xQueueHandle pxQueue,
+                            void *pvItemToQueue,
+                            portBASE_TYPE xCoRoutinePreviouslyWoken
+                       )
    + * + * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the + * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() + * functions used by tasks. + * + * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to + * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and + * xQueueReceiveFromISR() can only be used to pass data between a task and and + * ISR. + * + * crQUEUE_SEND_FROM_ISR can only be called from an ISR to send data to a queue + * that is being used from within a co-routine. + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param xCoRoutinePreviouslyWoken This is included so an ISR can post onto + * the same queue multiple times from a single interrupt. The first call + * should always pass in pdFALSE. Subsequent calls should pass in + * the value returned from the previous call. + * + * @return pdTRUE if a co-routine was woken by posting onto the queue. This is + * used by the ISR to determine if a context switch may be required following + * the ISR. + * + * Example usage: + 
    + // A co-routine that blocks on a queue waiting for characters to be received.
+ static void vReceivingCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
+ {
+ portCHAR cRxedChar;
+ portBASE_TYPE xResult;
+
+     // All co-routines must start with a call to crSTART().
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+         // Wait for data to become available on the queue.  This assumes the
+         // queue xCommsRxQueue has already been created!
+         crQUEUE_RECEIVE( xHandle, xCommsRxQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
+
+         // Was a character received?
+         if( xResult == pdPASS )
+         {
+             // Process the character here.
+         }
+     }
+
+     // All co-routines must end with a call to crEND().
+     crEND();
+ }
+
+ // An ISR that uses a queue to send characters received on a serial port to
+ // a co-routine.
+ void vUART_ISR( void )
+ {
+ portCHAR cRxedChar;
+ portBASE_TYPE xCRWokenByPost = pdFALSE;
+
+     // We loop around reading characters until there are none left in the UART.
+     while( UART_RX_REG_NOT_EMPTY() )
+     {
+         // Obtain the character from the UART.
+         cRxedChar = UART_RX_REG;
+
+         // Post the character onto a queue.  xCRWokenByPost will be pdFALSE
+         // the first time around the loop.  If the post causes a co-routine
+         // to be woken (unblocked) then xCRWokenByPost will be set to pdTRUE.
+         // In this manner we can ensure that if more than one co-routine is
+         // blocked on the queue only one is woken by this ISR no matter how
+         // many characters are posted to the queue.
+         xCRWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsRxQueue, &cRxedChar, xCRWokenByPost );
+     }
+ }
    + * \defgroup crQUEUE_SEND_FROM_ISR crQUEUE_SEND_FROM_ISR + * \ingroup Tasks + */ +#define crQUEUE_SEND_FROM_ISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) xQueueCRSendFromISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) + + +/** + * croutine. h + * 
    +  crQUEUE_SEND_FROM_ISR(
+                            xQueueHandle pxQueue,
+                            void *pvBuffer,
+                            portBASE_TYPE * pxCoRoutineWoken
+                       )
    + * + * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the + * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() + * functions used by tasks. + * + * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to + * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and + * xQueueReceiveFromISR() can only be used to pass data between a task and and + * ISR. + * + * crQUEUE_RECEIVE_FROM_ISR can only be called from an ISR to receive data + * from a queue that is being used from within a co-routine (a co-routine + * posted to the queue). + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvBuffer A pointer to a buffer into which the received item will be + * placed. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from the queue into + * pvBuffer. + * + * @param pxCoRoutineWoken A co-routine may be blocked waiting for space to become + * available on the queue. If crQUEUE_RECEIVE_FROM_ISR causes such a + * co-routine to unblock *pxCoRoutineWoken will get set to pdTRUE, otherwise + * *pxCoRoutineWoken will remain unchanged. + * + * @return pdTRUE an item was successfully received from the queue, otherwise + * pdFALSE. + * + * Example usage: + 
    + // A co-routine that posts a character to a queue then blocks for a fixed
+ // period.  The character is incremented each time.
+ static void vSendingCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
+ {
+ // cChar holds its value while this co-routine is blocked and must therefore
+ // be declared static.
+ static portCHAR cCharToTx = 'a';
+ portBASE_TYPE xResult;
+
+     // All co-routines must start with a call to crSTART().
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+         // Send the next character to the queue.
+         crQUEUE_SEND( xHandle, xCoRoutineQueue, &cCharToTx, NO_DELAY, &xResult );
+
+         if( xResult == pdPASS )
+         {
+             // The character was successfully posted to the queue.
+         }
+		 else
+		 {
+			// Could not post the character to the queue.
+		 }
+
+         // Enable the UART Tx interrupt to cause an interrupt in this
+		 // hypothetical UART.  The interrupt will obtain the character
+		 // from the queue and send it.
+		 ENABLE_RX_INTERRUPT();
+
+		 // Increment to the next character then block for a fixed period.
+		 // cCharToTx will maintain its value across the delay as it is
+		 // declared static.
+		 cCharToTx++;
+		 if( cCharToTx > 'x' )
+		 {
+			cCharToTx = 'a';
+		 }
+		 crDELAY( 100 );
+     }
+
+     // All co-routines must end with a call to crEND().
+     crEND();
+ }
+
+ // An ISR that uses a queue to receive characters to send on a UART.
+ void vUART_ISR( void )
+ {
+ portCHAR cCharToTx;
+ portBASE_TYPE xCRWokenByPost = pdFALSE;
+
+     while( UART_TX_REG_EMPTY() )
+     {
+         // Are there any characters in the queue waiting to be sent?
+		 // xCRWokenByPost will automatically be set to pdTRUE if a co-routine
+		 // is woken by the post - ensuring that only a single co-routine is
+		 // woken no matter how many times we go around this loop.
+         if( crQUEUE_RECEIVE_FROM_ISR( pxQueue, &cCharToTx, &xCRWokenByPost ) )
+		 {
+			 SEND_CHARACTER( cCharToTx );
+		 }
+     }
+ }
    + * \defgroup crQUEUE_RECEIVE_FROM_ISR crQUEUE_RECEIVE_FROM_ISR + * \ingroup Tasks + */ +#define crQUEUE_RECEIVE_FROM_ISR( pxQueue, pvBuffer, pxCoRoutineWoken ) xQueueCRReceiveFromISR( pxQueue, pvBuffer, pxCoRoutineWoken ) + +/* + * This function is intended for internal use by the co-routine macros only. + * The macro nature of the co-routine implementation requires that the + * prototype appears here. The function should not be used by application + * writers. + * + * Removes the current co-routine from its ready list and places it in the + * appropriate delayed list. + */ +void vCoRoutineAddToDelayedList( portTickType xTicksToDelay, xList *pxEventList ); + +/* + * This function is intended for internal use by the queue implementation only. + * The function should not be used by application writers. + * + * Removes the highest priority co-routine from the event list and places it in + * the pending ready list. + */ +signed portBASE_TYPE xCoRoutineRemoveFromEventList( const xList *pxEventList ); + +#ifdef __cplusplus +} +#endif + +#endif /* CO_ROUTINE_H */ diff --git a/20080212/Source/include/list.h b/20080212/Source/include/list.h new file mode 100644 index 000000000..67a9e489e --- /dev/null +++ b/20080212/Source/include/list.h @@ -0,0 +1,294 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + * This is the list implementation used by the scheduler. While it is tailored + * heavily for the schedulers needs, it is also available for use by + * application code. + * + * xLists can only store pointers to xListItems. Each xListItem contains a + * numeric value (xItemValue). Most of the time the lists are sorted in + * descending item value order. + * + * Lists are created already containing one list item. The value of this + * item is the maximum possible that can be stored, it is therefore always at + * the end of the list and acts as a marker. The list member pxHead always + * points to this marker - even though it is at the tail of the list. This + * is because the tail contains a wrap back pointer to the true head of + * the list. + * + * In addition to it's value, each list item contains a pointer to the next + * item in the list (pxNext), a pointer to the list it is in (pxContainer) + * and a pointer to back to the object that contains it. These later two + * pointers are included for efficiency of list manipulation. There is + * effectively a two way link between the object containing the list item and + * the list item itself. + * + * + * \page ListIntroduction List Implementation + * \ingroup FreeRTOSIntro + */ + +/* + Changes from V4.3.1 + + + Included local const within listGET_OWNER_OF_NEXT_ENTRY() to assist + compiler with optimisation. Thanks B.R. +*/ + +#ifndef LIST_H +#define LIST_H + +#ifdef __cplusplus +extern "C" { +#endif +/* + * Definition of the only type of object that a list can contain. + */ +struct xLIST_ITEM +{ + portTickType xItemValue; /*< The value being listed. In most cases this is used to sort the list in descending order. */ + volatile struct xLIST_ITEM * pxNext; /*< Pointer to the next xListItem in the list. */ + volatile struct xLIST_ITEM * pxPrevious;/*< Pointer to the previous xListItem in the list. */ + void * pvOwner; /*< Pointer to the object (normally a TCB) that contains the list item. There is therefore a two way link between the object containing the list item and the list item itself. */ + void * pvContainer; /*< Pointer to the list in which this list item is placed (if any). */ +}; +typedef struct xLIST_ITEM xListItem; /* For some reason lint wants this as two separate definitions. */ + +struct xMINI_LIST_ITEM +{ + portTickType xItemValue; + volatile struct xLIST_ITEM *pxNext; + volatile struct xLIST_ITEM *pxPrevious; +}; +typedef struct xMINI_LIST_ITEM xMiniListItem; + +/* + * Definition of the type of queue used by the scheduler. + */ +typedef struct xLIST +{ + volatile unsigned portBASE_TYPE uxNumberOfItems; + volatile xListItem * pxIndex; /*< Used to walk through the list. Points to the last item returned by a call to pvListGetOwnerOfNextEntry (). */ + volatile xMiniListItem xListEnd; /*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */ +} xList; + +/* + * Access macro to set the owner of a list item. The owner of a list item + * is the object (usually a TCB) that contains the list item. + * + * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER + * \ingroup LinkedList + */ +#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner ) ( pxListItem )->pvOwner = ( void * ) pxOwner + +/* + * Access macro to set the value of the list item. In most cases the value is + * used to sort the list in descending order. + * + * \page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE + * \ingroup LinkedList + */ +#define listSET_LIST_ITEM_VALUE( pxListItem, xValue ) ( pxListItem )->xItemValue = xValue + +/* + * Access macro the retrieve the value of the list item. The value can + * represent anything - for example a the priority of a task, or the time at + * which a task should be unblocked. + * + * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE + * \ingroup LinkedList + */ +#define listGET_LIST_ITEM_VALUE( pxListItem ) ( ( pxListItem )->xItemValue ) + +/* + * Access macro to determine if a list contains any items. The macro will + * only have the value true if the list is empty. + * + * \page listLIST_IS_EMPTY listLIST_IS_EMPTY + * \ingroup LinkedList + */ +#define listLIST_IS_EMPTY( pxList ) ( ( pxList )->uxNumberOfItems == ( unsigned portBASE_TYPE ) 0 ) + +/* + * Access macro to return the number of items in the list. + */ +#define listCURRENT_LIST_LENGTH( pxList ) ( ( pxList )->uxNumberOfItems ) + +/* + * Access function to obtain the owner of the next entry in a list. + * + * The list member pxIndex is used to walk through a list. Calling + * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list + * and returns that entries pxOwner parameter. Using multiple calls to this + * function it is therefore possible to move through every item contained in + * a list. + * + * The pxOwner parameter of a list item is a pointer to the object that owns + * the list item. In the scheduler this is normally a task control block. + * The pxOwner parameter effectively creates a two way link between the list + * item and its owner. + * + * @param pxList The list from which the next item owner is to be returned. + * + * \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY + * \ingroup LinkedList + */ +#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList ) \ +{ \ +xList * const pxConstList = pxList; \ + /* Increment the index to the next item and return the item, ensuring */ \ + /* we don't return the marker used at the end of the list. */ \ + ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \ + if( ( pxConstList )->pxIndex == ( xListItem * ) &( ( pxConstList )->xListEnd ) ) \ + { \ + ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \ + } \ + pxTCB = ( pxConstList )->pxIndex->pvOwner; \ +} + + +/* + * Access function to obtain the owner of the first entry in a list. Lists + * are normally sorted in ascending item value order. + * + * This function returns the pxOwner member of the first item in the list. + * The pxOwner parameter of a list item is a pointer to the object that owns + * the list item. In the scheduler this is normally a task control block. + * The pxOwner parameter effectively creates a two way link between the list + * item and its owner. + * + * @param pxList The list from which the owner of the head item is to be + * returned. + * + * \page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY + * \ingroup LinkedList + */ +#define listGET_OWNER_OF_HEAD_ENTRY( pxList ) ( ( pxList->uxNumberOfItems != ( unsigned portBASE_TYPE ) 0 ) ? ( (&( pxList->xListEnd ))->pxNext->pvOwner ) : ( NULL ) ) + +/* + * Check to see if a list item is within a list. The list item maintains a + * "container" pointer that points to the list it is in. All this macro does + * is check to see if the container and the list match. + * + * @param pxList The list we want to know if the list item is within. + * @param pxListItem The list item we want to know if is in the list. + * @return pdTRUE is the list item is in the list, otherwise pdFALSE. + * pointer against + */ +#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( pxListItem )->pvContainer == ( void * ) pxList ) + +/* + * Must be called before a list is used! This initialises all the members + * of the list structure and inserts the xListEnd item into the list as a + * marker to the back of the list. + * + * @param pxList Pointer to the list being initialised. + * + * \page vListInitialise vListInitialise + * \ingroup LinkedList + */ +void vListInitialise( xList *pxList ); + +/* + * Must be called before a list item is used. This sets the list container to + * null so the item does not think that it is already contained in a list. + * + * @param pxItem Pointer to the list item being initialised. + * + * \page vListInitialiseItem vListInitialiseItem + * \ingroup LinkedList + */ +void vListInitialiseItem( xListItem *pxItem ); + +/* + * Insert a list item into a list. The item will be inserted into the list in + * a position determined by its item value (descending item value order). + * + * @param pxList The list into which the item is to be inserted. + * + * @param pxNewListItem The item to that is to be placed in the list. + * + * \page vListInsert vListInsert + * \ingroup LinkedList + */ +void vListInsert( xList *pxList, xListItem *pxNewListItem ); + +/* + * Insert a list item into a list. The item will be inserted in a position + * such that it will be the last item within the list returned by multiple + * calls to listGET_OWNER_OF_NEXT_ENTRY. + * + * The list member pvIndex is used to walk through a list. Calling + * listGET_OWNER_OF_NEXT_ENTRY increments pvIndex to the next item in the list. + * Placing an item in a list using vListInsertEnd effectively places the item + * in the list position pointed to by pvIndex. This means that every other + * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before + * the pvIndex parameter again points to the item being inserted. + * + * @param pxList The list into which the item is to be inserted. + * + * @param pxNewListItem The list item to be inserted into the list. + * + * \page vListInsertEnd vListInsertEnd + * \ingroup LinkedList + */ +void vListInsertEnd( xList *pxList, xListItem *pxNewListItem ); + +/* + * Remove an item from a list. The list item has a pointer to the list that + * it is in, so only the list item need be passed into the function. + * + * @param vListRemove The item to be removed. The item will remove itself from + * the list pointed to by it's pxContainer parameter. + * + * \page vListRemove vListRemove + * \ingroup LinkedList + */ +void vListRemove( xListItem *pxItemToRemove ); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/20080212/Source/include/portable.h b/20080212/Source/include/portable.h new file mode 100644 index 000000000..04769184b --- /dev/null +++ b/20080212/Source/include/portable.h @@ -0,0 +1,267 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http:www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/*----------------------------------------------------------- + * Portable layer API. Each function must be defined for each port. + *----------------------------------------------------------*/ + +#ifndef PORTABLE_H +#define PORTABLE_H + +/* Include the macro file relevant to the port being used. */ + +#ifdef OPEN_WATCOM_INDUSTRIAL_PC_PORT + #include "..\..\source\portable\owatcom\16bitdos\pc\portmacro.h" + typedef void ( __interrupt __far *pxISR )(); +#endif + +#ifdef OPEN_WATCOM_FLASH_LITE_186_PORT + #include "..\..\source\portable\owatcom\16bitdos\flsh186\portmacro.h" + typedef void ( __interrupt __far *pxISR )(); +#endif + +#ifdef GCC_MEGA_AVR + #include "../portable/GCC/ATMega323/portmacro.h" +#endif + +#ifdef IAR_MEGA_AVR + #include "../portable/IAR/ATMega323/portmacro.h" +#endif + +#ifdef MPLAB_PIC24_PORT + #include "..\..\Source\portable\MPLAB\PIC24_dsPIC\portmacro.h" +#endif + +#ifdef MPLAB_DSPIC_PORT + #include "..\..\Source\portable\MPLAB\PIC24_dsPIC\portmacro.h" +#endif + +#ifdef MPLAB_PIC18F_PORT + #include "..\..\source\portable\MPLAB\PIC18F\portmacro.h" +#endif + +#ifdef MPLAB_PIC32MX_PORT + #include "..\..\Source\portable\MPLAB\PIC32MX\portmacro.h" +#endif + +#ifdef _FEDPICC + #include "libFreeRTOS/Include/portmacro.h" +#endif + +#ifdef SDCC_CYGNAL + #include "../../Source/portable/SDCC/Cygnal/portmacro.h" +#endif + +#ifdef GCC_ARM7 + #include "../../Source/portable/GCC/ARM7_LPC2000/portmacro.h" +#endif + +#ifdef GCC_ARM7_ECLIPSE + #include "portmacro.h" +#endif + +#ifdef ROWLEY_LPC23xx + #include "../../Source/portable/GCC/ARM7_LPC23xx/portmacro.h" +#endif + +#ifdef GCC_MSP430 + #include "../../Source/portable/GCC/MSP430F449/portmacro.h" +#endif + +#ifdef ROWLEY_MSP430 + #include "../../Source/portable/Rowley/MSP430F449/portmacro.h" +#endif + +#ifdef KEIL_ARM7 + #include "..\..\Source\portable\Keil\ARM7\portmacro.h" +#endif + +#ifdef SAM7_GCC + #include "../../Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h" +#endif + +#ifdef SAM7_IAR + #include "..\..\Source\portable\IAR\AtmelSAM7S64\portmacro.h" +#endif + +#ifdef LPC2000_IAR + #include "..\..\Source\portable\IAR\LPC2000\portmacro.h" +#endif + +#ifdef STR71X_IAR + #include "..\..\Source\portable\IAR\STR71x\portmacro.h" +#endif + +#ifdef STR75X_IAR + #include "..\..\Source\portable\IAR\STR75x\portmacro.h" +#endif + +#ifdef STR75X_GCC + #include "..\..\Source\portable\GCC\STR75x\portmacro.h" +#endif + +#ifdef STR91X_IAR + #include "..\..\Source\portable\IAR\STR91x\portmacro.h" +#endif + +#ifdef GCC_H8S + #include "../../Source/portable/GCC/H8S2329/portmacro.h" +#endif + +#ifdef GCC_AT91FR40008 + #include "../../Source/portable/GCC/ARM7_AT91FR40008/portmacro.h" +#endif + +#ifdef RVDS_ARMCM3_LM3S102 + #include "../../Source/portable/RVDS/ARM_CM3/portmacro.h" +#endif + +#ifdef GCC_ARMCM3_LM3S102 + #include "../../Source/portable/GCC/ARM_CM3/portmacro.h" +#endif + +#ifdef GCC_ARMCM3 + #include "../../Source/portable/GCC/ARM_CM3/portmacro.h" +#endif + +#ifdef IAR_ARM_CM3 + #include "../../Source/portable/IAR/ARM_CM3/portmacro.h" +#endif + +#ifdef IAR_ARMCM3_LM + #include "../../Source/portable/IAR/ARM_CM3/portmacro.h" +#endif + +#ifdef HCS12_CODE_WARRIOR + #include "../../Source/portable/CodeWarrior/HCS12/portmacro.h" +#endif + +#ifdef MICROBLAZE_GCC + #include "../../Source/portable/GCC/MicroBlaze/portmacro.h" +#endif + +#ifdef TERN_EE + #include "..\..\Source\portable\Paradigm\Tern_EE\small\portmacro.h" +#endif + +#ifdef GCC_HCS12 + #include "../../Source/portable/GCC/HCS12/portmacro.h" +#endif + +#ifdef GCC_MCF5235 + #include "../../Source/portable/GCC/MCF5235/portmacro.h" +#endif + +#ifdef BCC_INDUSTRIAL_PC_PORT + /* A short file name has to be used in place of the normal + FreeRTOSConfig.h when using the Borland compiler. */ + #include "frconfig.h" + #include "..\portable\BCC\16BitDOS\PC\prtmacro.h" + typedef void ( __interrupt __far *pxISR )(); +#endif + +#ifdef BCC_FLASH_LITE_186_PORT + /* A short file name has to be used in place of the normal + FreeRTOSConfig.h when using the Borland compiler. */ + #include "frconfig.h" + #include "..\portable\BCC\16BitDOS\flsh186\prtmacro.h" + typedef void ( __interrupt __far *pxISR )(); +#endif + +#ifdef __GNUC__ + #ifdef __AVR32_AVR32A__ + #include "portmacro.h" + #endif +#endif + +#ifdef __ICCAVR32__ + #ifdef __CORE__ + #if __CORE__ == __AVR32A__ + #include "portmacro.h" + #endif + #endif +#endif + +#ifdef __91467D + #include "portmacro.h" +#endif + +#ifdef __96340 + #include "portmacro.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif +/* + * Setup the stack of a new task so it is ready to be placed under the + * scheduler control. The registers have to be placed on the stack in + * the order that the port expects to find them. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ); + +/* + * Map to the memory management routines required for the port. + */ +void *pvPortMalloc( size_t xSize ); +void vPortFree( void *pv ); +void vPortInitialiseBlocks( void ); + +/* + * Setup the hardware ready for the scheduler to take control. This generally + * sets up a tick interrupt and sets timers for the correct tick frequency. + */ +portBASE_TYPE xPortStartScheduler( void ); + +/* + * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so + * the hardware is left in its original condition after the scheduler stops + * executing. + */ +void vPortEndScheduler( void ); + +#ifdef __cplusplus +} +#endif + +#endif /* PORTABLE_H */ + diff --git a/20080212/Source/include/projdefs.h b/20080212/Source/include/projdefs.h new file mode 100644 index 000000000..ef3fad881 --- /dev/null +++ b/20080212/Source/include/projdefs.h @@ -0,0 +1,66 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef PROJDEFS_H +#define PROJDEFS_H + +/* Defines to prototype to which task functions must conform. */ +typedef void (*pdTASK_CODE)( void * ); + +#define pdTRUE ( 1 ) +#define pdFALSE ( 0 ) + +#define pdPASS ( 1 ) +#define pdFAIL ( 0 ) +#define errQUEUE_EMPTY ( 0 ) +#define errQUEUE_FULL ( 0 ) + +/* Error definitions. */ +#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ( -1 ) +#define errNO_TASK_TO_RUN ( -2 ) +#define errQUEUE_BLOCKED ( -4 ) +#define errQUEUE_YIELD ( -5 ) + +#endif /* PROJDEFS_H */ + + + diff --git a/20080212/Source/include/queue.h b/20080212/Source/include/queue.h new file mode 100644 index 000000000..f305cb9c5 --- /dev/null +++ b/20080212/Source/include/queue.h @@ -0,0 +1,1222 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef QUEUE_H +#define QUEUE_H + +#ifdef __cplusplus +extern "C" { +#endif +typedef void * xQueueHandle; + +/* For internal use only. */ +#define queueSEND_TO_BACK ( 0 ) +#define queueSEND_TO_FRONT ( 1 ) + + +/** + * queue. h + * 
    + xQueueHandle xQueueCreate(
+                              unsigned portBASE_TYPE uxQueueLength,
+                              unsigned portBASE_TYPE uxItemSize
+                          );
+ *
    + * + * Creates a new queue instance. This allocates the storage required by the + * new queue and returns a handle for the queue. + * + * @param uxQueueLength The maximum number of items that the queue can contain. + * + * @param uxItemSize The number of bytes each item in the queue will require. + * Items are queued by copy, not by reference, so this is the number of bytes + * that will be copied for each posted item. Each item on the queue must be + * the same size. + * + * @return If the queue is successfully create then a handle to the newly + * created queue is returned. If the queue cannot be created then 0 is + * returned. + * + * Example usage: + 
    + struct AMessage
+ {
+    portCHAR ucMessageID;
+    portCHAR ucData[ 20 ];
+ };
+
+ void vATask( void *pvParameters )
+ {
+ xQueueHandle xQueue1, xQueue2;
+
+    // Create a queue capable of containing 10 unsigned long values.
+    xQueue1 = xQueueCreate( 10, sizeof( unsigned portLONG ) );
+    if( xQueue1 == 0 )
+    {
+        // Queue was not created and must not be used.
+    }
+
+    // Create a queue capable of containing 10 pointers to AMessage structures.
+    // These should be passed by pointer as they contain a lot of data.
+    xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+    if( xQueue2 == 0 )
+    {
+        // Queue was not created and must not be used.
+    }
+
+    // ... Rest of task code.
+ }
+
    + * \defgroup xQueueCreate xQueueCreate + * \ingroup QueueManagement + */ +xQueueHandle xQueueCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize ); + +/** + * queue. h + * 
    + portBASE_TYPE xQueueSendToToFront(
+                                   xQueueHandle xQueue,
+                                   const void * pvItemToQueue,
+                                   portTickType xTicksToWait
+                               );
+ *
    + * + * This is a macro that calls xQueueGenericSend(). + * + * Post an item to the front of a queue. The item is queued by copy, not by + * reference. This function must not be called from an interrupt service + * routine. See xQueueSendFromISR () for an alternative which may be used + * in an ISR. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for space to become available on the queue, should it already + * be full. The call will return immediately if this is set to 0. The + * time is defined in tick periods so the constant portTICK_RATE_MS + * should be used to convert to real time if this is required. + * + * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL. + * + * Example usage: + 
    + struct AMessage
+ {
+    portCHAR ucMessageID;
+    portCHAR ucData[ 20 ];
+ } xMessage;
+
+ unsigned portLONG ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ xQueueHandle xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+    // Create a queue capable of containing 10 unsigned long values.
+    xQueue1 = xQueueCreate( 10, sizeof( unsigned portLONG ) );
+
+    // Create a queue capable of containing 10 pointers to AMessage structures.
+    // These should be passed by pointer as they contain a lot of data.
+    xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+    // ...
+
+    if( xQueue1 != 0 )
+    {
+        // Send an unsigned long.  Wait for 10 ticks for space to become
+        // available if necessary.
+        if( xQueueSendToFront( xQueue1, ( void * ) &ulVar, ( portTickType ) 10 ) != pdPASS )
+        {
+            // Failed to post the message, even after 10 ticks.
+        }
+    }
+
+    if( xQueue2 != 0 )
+    {
+        // Send a pointer to a struct AMessage object.  Don't block if the
+        // queue is already full.
+        pxMessage = & xMessage;
+        xQueueSendToFront( xQueue2, ( void * ) &pxMessage, ( portTickType ) 0 );
+    }
+
+	// ... Rest of task code.
+ }
+
    + * \defgroup xQueueSend xQueueSend + * \ingroup QueueManagement + */ +#define xQueueSendToFront( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( xQueue, pvItemToQueue, xTicksToWait, queueSEND_TO_FRONT ) + +/** + * queue. h + * 
    + portBASE_TYPE xQueueSendToBack(
+                                   xQueueHandle xQueue,
+                                   const void * pvItemToQueue,
+                                   portTickType xTicksToWait
+                               );
+ *
    + * + * This is a macro that calls xQueueGenericSend(). + * + * Post an item to the back of a queue. The item is queued by copy, not by + * reference. This function must not be called from an interrupt service + * routine. See xQueueSendFromISR () for an alternative which may be used + * in an ISR. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for space to become available on the queue, should it already + * be full. The call will return immediately if this is set to 0. The + * time is defined in tick periods so the constant portTICK_RATE_MS + * should be used to convert to real time if this is required. + * + * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL. + * + * Example usage: + 
    + struct AMessage
+ {
+    portCHAR ucMessageID;
+    portCHAR ucData[ 20 ];
+ } xMessage;
+
+ unsigned portLONG ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ xQueueHandle xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+    // Create a queue capable of containing 10 unsigned long values.
+    xQueue1 = xQueueCreate( 10, sizeof( unsigned portLONG ) );
+
+    // Create a queue capable of containing 10 pointers to AMessage structures.
+    // These should be passed by pointer as they contain a lot of data.
+    xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+    // ...
+
+    if( xQueue1 != 0 )
+    {
+        // Send an unsigned long.  Wait for 10 ticks for space to become
+        // available if necessary.
+        if( xQueueSendToBack( xQueue1, ( void * ) &ulVar, ( portTickType ) 10 ) != pdPASS )
+        {
+            // Failed to post the message, even after 10 ticks.
+        }
+    }
+
+    if( xQueue2 != 0 )
+    {
+        // Send a pointer to a struct AMessage object.  Don't block if the
+        // queue is already full.
+        pxMessage = & xMessage;
+        xQueueSendToBack( xQueue2, ( void * ) &pxMessage, ( portTickType ) 0 );
+    }
+
+	// ... Rest of task code.
+ }
+
    + * \defgroup xQueueSend xQueueSend + * \ingroup QueueManagement + */ +#define xQueueSendToBack( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( xQueue, pvItemToQueue, xTicksToWait, queueSEND_TO_BACK ) + +/** + * queue. h + * 
    + portBASE_TYPE xQueueSend(
+                              xQueueHandle xQueue,
+                              const void * pvItemToQueue,
+                              portTickType xTicksToWait
+                         );
+ *
    + * + * This is a macro that calls xQueueGenericSend(). It is included for + * backward compatibility with versions of FreeRTOS.org that did not + * include the xQueueSendToFront() and xQueueSendToBack() macros. It is + * equivalent to xQueueSendToBack(). + * + * Post an item on a queue. The item is queued by copy, not by reference. + * This function must not be called from an interrupt service routine. + * See xQueueSendFromISR () for an alternative which may be used in an ISR. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for space to become available on the queue, should it already + * be full. The call will return immediately if this is set to 0. The + * time is defined in tick periods so the constant portTICK_RATE_MS + * should be used to convert to real time if this is required. + * + * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL. + * + * Example usage: + 
    + struct AMessage
+ {
+    portCHAR ucMessageID;
+    portCHAR ucData[ 20 ];
+ } xMessage;
+
+ unsigned portLONG ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ xQueueHandle xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+    // Create a queue capable of containing 10 unsigned long values.
+    xQueue1 = xQueueCreate( 10, sizeof( unsigned portLONG ) );
+
+    // Create a queue capable of containing 10 pointers to AMessage structures.
+    // These should be passed by pointer as they contain a lot of data.
+    xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+    // ...
+
+    if( xQueue1 != 0 )
+    {
+        // Send an unsigned long.  Wait for 10 ticks for space to become
+        // available if necessary.
+        if( xQueueSend( xQueue1, ( void * ) &ulVar, ( portTickType ) 10 ) != pdPASS )
+        {
+            // Failed to post the message, even after 10 ticks.
+        }
+    }
+
+    if( xQueue2 != 0 )
+    {
+        // Send a pointer to a struct AMessage object.  Don't block if the
+        // queue is already full.
+        pxMessage = & xMessage;
+        xQueueSend( xQueue2, ( void * ) &pxMessage, ( portTickType ) 0 );
+    }
+
+	// ... Rest of task code.
+ }
+
    + * \defgroup xQueueSend xQueueSend + * \ingroup QueueManagement + */ +#define xQueueSend( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( xQueue, pvItemToQueue, xTicksToWait, queueSEND_TO_BACK ) + + +/** + * queue. h + * 
    + portBASE_TYPE xQueueGenericSend(
+									xQueueHandle xQueue,
+									const void * pvItemToQueue,
+									portTickType xTicksToWait
+									portBASE_TYPE xCopyPosition
+								);
+ *
    + * + * It is preferred that the macros xQueueSend(), xQueueSendToFront() and + * xQueueSendToBack() are used in place of calling this function directly. + * + * Post an item on a queue. The item is queued by copy, not by reference. + * This function must not be called from an interrupt service routine. + * See xQueueSendFromISR () for an alternative which may be used in an ISR. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for space to become available on the queue, should it already + * be full. The call will return immediately if this is set to 0. The + * time is defined in tick periods so the constant portTICK_RATE_MS + * should be used to convert to real time if this is required. + * + * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the + * item at the back of the queue, or queueSEND_TO_FRONT to place the item + * at the front of the queue (for high priority messages). + * + * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL. + * + * Example usage: + 
    + struct AMessage
+ {
+    portCHAR ucMessageID;
+    portCHAR ucData[ 20 ];
+ } xMessage;
+
+ unsigned portLONG ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ xQueueHandle xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+    // Create a queue capable of containing 10 unsigned long values.
+    xQueue1 = xQueueCreate( 10, sizeof( unsigned portLONG ) );
+
+    // Create a queue capable of containing 10 pointers to AMessage structures.
+    // These should be passed by pointer as they contain a lot of data.
+    xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+    // ...
+
+    if( xQueue1 != 0 )
+    {
+        // Send an unsigned long.  Wait for 10 ticks for space to become
+        // available if necessary.
+        if( xQueueGenericSend( xQueue1, ( void * ) &ulVar, ( portTickType ) 10, queueSEND_TO_BACK ) != pdPASS )
+        {
+            // Failed to post the message, even after 10 ticks.
+        }
+    }
+
+    if( xQueue2 != 0 )
+    {
+        // Send a pointer to a struct AMessage object.  Don't block if the
+        // queue is already full.
+        pxMessage = & xMessage;
+        xQueueGenericSend( xQueue2, ( void * ) &pxMessage, ( portTickType ) 0, queueSEND_TO_BACK );
+    }
+
+	// ... Rest of task code.
+ }
+
    + * \defgroup xQueueSend xQueueSend + * \ingroup QueueManagement + */ +signed portBASE_TYPE xQueueGenericSend( xQueueHandle xQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition ); + +/** + * queue. h + * 
    + portBASE_TYPE xQueuePeek(
+                             xQueueHandle xQueue,
+                             void *pvBuffer,
+                             portTickType xTicksToWait
+                         );
    + * + * This is a macro that calls the xQueueGenericReceive() function. + * + * Receive an item from a queue without removing the item from the queue. + * The item is received by copy so a buffer of adequate size must be + * provided. The number of bytes copied into the buffer was defined when + * the queue was created. + * + * Successfully received items remain on the queue so will be returned again + * by the next call, or a call to xQueueReceive(). + * + * This macro must not be used in an interrupt service routine. + * + * @param pxQueue The handle to the queue from which the item is to be + * received. + * + * @param pvBuffer Pointer to the buffer into which the received item will + * be copied. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for an item to receive should the queue be empty at the time + * of the call. The time is defined in tick periods so the constant + * portTICK_RATE_MS should be used to convert to real time if this is required. + * + * @return pdTRUE if an item was successfully received from the queue, + * otherwise pdFALSE. + * + * Example usage: + 
    + struct AMessage
+ {
+    portCHAR ucMessageID;
+    portCHAR ucData[ 20 ];
+ } xMessage;
+
+ xQueueHandle xQueue;
+
+ // Task to create a queue and post a value.
+ void vATask( void *pvParameters )
+ {
+ struct AMessage *pxMessage;
+
+    // Create a queue capable of containing 10 pointers to AMessage structures.
+    // These should be passed by pointer as they contain a lot of data.
+    xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
+    if( xQueue == 0 )
+    {
+        // Failed to create the queue.
+    }
+
+    // ...
+
+    // Send a pointer to a struct AMessage object.  Don't block if the
+    // queue is already full.
+    pxMessage = & xMessage;
+    xQueueSend( xQueue, ( void * ) &pxMessage, ( portTickType ) 0 );
+
+	// ... Rest of task code.
+ }
+
+ // Task to peek the data from the queue.
+ void vADifferentTask( void *pvParameters )
+ {
+ struct AMessage *pxRxedMessage;
+
+    if( xQueue != 0 )
+    {
+        // Peek a message on the created queue.  Block for 10 ticks if a
+        // message is not immediately available.
+        if( xQueuePeek( xQueue, &( pxRxedMessage ), ( portTickType ) 10 ) )
+        {
+            // pcRxedMessage now points to the struct AMessage variable posted
+            // by vATask, but the item still remains on the queue.
+        }
+    }
+
+	// ... Rest of task code.
+ }
+
    + * \defgroup xQueueReceive xQueueReceive + * \ingroup QueueManagement + */ +#define xQueuePeek( xQueue, pvBuffer, xTicksToWait ) xQueueGenericReceive( xQueue, pvBuffer, xTicksToWait, pdTRUE ) + +/** + * queue. h + * 
    + portBASE_TYPE xQueueReceive(
+                                 xQueueHandle xQueue,
+                                 void *pvBuffer,
+                                 portTickType xTicksToWait
+                            );
    + * + * This is a macro that calls the xQueueGenericReceive() function. + * + * Receive an item from a queue. The item is received by copy so a buffer of + * adequate size must be provided. The number of bytes copied into the buffer + * was defined when the queue was created. + * + * Successfully received items are removed from the queue. + * + * This function must not be used in an interrupt service routine. See + * xQueueReceiveFromISR for an alternative that can. + * + * @param pxQueue The handle to the queue from which the item is to be + * received. + * + * @param pvBuffer Pointer to the buffer into which the received item will + * be copied. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for an item to receive should the queue be empty at the time + * of the call. The time is defined in tick periods so the constant + * portTICK_RATE_MS should be used to convert to real time if this is required. + * + * @return pdTRUE if an item was successfully received from the queue, + * otherwise pdFALSE. + * + * Example usage: + 
    + struct AMessage
+ {
+    portCHAR ucMessageID;
+    portCHAR ucData[ 20 ];
+ } xMessage;
+
+ xQueueHandle xQueue;
+
+ // Task to create a queue and post a value.
+ void vATask( void *pvParameters )
+ {
+ struct AMessage *pxMessage;
+
+    // Create a queue capable of containing 10 pointers to AMessage structures.
+    // These should be passed by pointer as they contain a lot of data.
+    xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
+    if( xQueue == 0 )
+    {
+        // Failed to create the queue.
+    }
+
+    // ...
+
+    // Send a pointer to a struct AMessage object.  Don't block if the
+    // queue is already full.
+    pxMessage = & xMessage;
+    xQueueSend( xQueue, ( void * ) &pxMessage, ( portTickType ) 0 );
+
+	// ... Rest of task code.
+ }
+
+ // Task to receive from the queue.
+ void vADifferentTask( void *pvParameters )
+ {
+ struct AMessage *pxRxedMessage;
+
+    if( xQueue != 0 )
+    {
+        // Receive a message on the created queue.  Block for 10 ticks if a
+        // message is not immediately available.
+        if( xQueueReceive( xQueue, &( pxRxedMessage ), ( portTickType ) 10 ) )
+        {
+            // pcRxedMessage now points to the struct AMessage variable posted
+            // by vATask.
+        }
+    }
+
+	// ... Rest of task code.
+ }
+
    + * \defgroup xQueueReceive xQueueReceive + * \ingroup QueueManagement + */ +#define xQueueReceive( xQueue, pvBuffer, xTicksToWait ) xQueueGenericReceive( xQueue, pvBuffer, xTicksToWait, pdFALSE ) + + +/** + * queue. h + * 
    + portBASE_TYPE xQueueGenericReceive(
+                                       xQueueHandle xQueue,
+                                       void *pvBuffer,
+                                       portTickType xTicksToWait
+                                       portBASE_TYPE xJustPeek
+                                    );
    + * + * It is preferred that the macro xQueueReceive() be used rather than calling + * this function directly. + * + * Receive an item from a queue. The item is received by copy so a buffer of + * adequate size must be provided. The number of bytes copied into the buffer + * was defined when the queue was created. + * + * This function must not be used in an interrupt service routine. See + * xQueueReceiveFromISR for an alternative that can. + * + * @param pxQueue The handle to the queue from which the item is to be + * received. + * + * @param pvBuffer Pointer to the buffer into which the received item will + * be copied. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for an item to receive should the queue be empty at the time + * of the call. The time is defined in tick periods so the constant + * portTICK_RATE_MS should be used to convert to real time if this is required. + * + * @param xJustPeek When set to true, the item received from the queue is not + * actually removed from the queue - meaning a subsequent call to + * xQueueReceive() will return the same item. When set to false, the item + * being received from the queue is also removed from the queue. + * + * @return pdTRUE if an item was successfully received from the queue, + * otherwise pdFALSE. + * + * Example usage: + 
    + struct AMessage
+ {
+    portCHAR ucMessageID;
+    portCHAR ucData[ 20 ];
+ } xMessage;
+
+ xQueueHandle xQueue;
+
+ // Task to create a queue and post a value.
+ void vATask( void *pvParameters )
+ {
+ struct AMessage *pxMessage;
+
+    // Create a queue capable of containing 10 pointers to AMessage structures.
+    // These should be passed by pointer as they contain a lot of data.
+    xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
+    if( xQueue == 0 )
+    {
+        // Failed to create the queue.
+    }
+
+    // ...
+
+    // Send a pointer to a struct AMessage object.  Don't block if the
+    // queue is already full.
+    pxMessage = & xMessage;
+    xQueueSend( xQueue, ( void * ) &pxMessage, ( portTickType ) 0 );
+
+	// ... Rest of task code.
+ }
+
+ // Task to receive from the queue.
+ void vADifferentTask( void *pvParameters )
+ {
+ struct AMessage *pxRxedMessage;
+
+    if( xQueue != 0 )
+    {
+        // Receive a message on the created queue.  Block for 10 ticks if a
+        // message is not immediately available.
+        if( xQueueGenericReceive( xQueue, &( pxRxedMessage ), ( portTickType ) 10 ) )
+        {
+            // pcRxedMessage now points to the struct AMessage variable posted
+            // by vATask.
+        }
+    }
+
+	// ... Rest of task code.
+ }
+
    + * \defgroup xQueueReceive xQueueReceive + * \ingroup QueueManagement + */ +signed portBASE_TYPE xQueueGenericReceive( xQueueHandle xQueue, const void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeek ); + +/** + * queue. h + * 
    unsigned portBASE_TYPE uxQueueMessagesWaiting( const xQueueHandle xQueue );
    + * + * Return the number of messages stored in a queue. + * + * @param xQueue A handle to the queue being queried. + * + * @return The number of messages available in the queue. + * + * \page uxQueueMessagesWaiting uxQueueMessagesWaiting + * \ingroup QueueManagement + */ +unsigned portBASE_TYPE uxQueueMessagesWaiting( const xQueueHandle xQueue ); + +/** + * queue. h + * 
    void vQueueDelete( xQueueHandle xQueue );
    + * + * Delete a queue - freeing all the memory allocated for storing of items + * placed on the queue. + * + * @param xQueue A handle to the queue to be deleted. + * + * \page vQueueDelete vQueueDelete + * \ingroup QueueManagement + */ +void vQueueDelete( xQueueHandle xQueue ); + +/** + * queue. h + * 
    + portBASE_TYPE xQueueSendToFrontFromISR(
+                                         xQueueHandle pxQueue,
+                                         const void *pvItemToQueue,
+                                         portBASE_TYPE xTaskPreviouslyWoken
+                                      );
+
    + * + * This is a macro that calls xQueueGenericSendFromISR(). + * + * Post an item to the front of a queue. It is safe to use this macro from + * within an interrupt service routine. + * + * Items are queued by copy not reference so it is preferable to only + * queue small items, especially when called from an ISR. In most cases + * it would be preferable to store a pointer to the item being queued. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param cTaskPreviouslyWoken This is included so an ISR can post onto + * the same queue multiple times from a single interrupt. The first call + * should always pass in pdFALSE. Subsequent calls should pass in + * the value returned from the previous call. See the file serial .c in the + * PC port for a good example of this mechanism. + * + * @return pdTRUE if a task was woken by posting onto the queue. This is + * used by the ISR to determine if a context switch may be required following + * the ISR. + * + * Example usage for buffered IO (where the ISR can obtain more than one value + * per call): + 
    + void vBufferISR( void )
+ {
+ portCHAR cIn;
+ portBASE_TYPE xTaskWokenByPost;
+
+    // We have not woken a task at the start of the ISR.
+    cTaskWokenByPost = pdFALSE;
+
+    // Loop until the buffer is empty.
+    do
+    {
+        // Obtain a byte from the buffer.
+        cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );						
+
+        // Post the byte.  The first time round the loop cTaskWokenByPost
+        // will be pdFALSE.  If the queue send causes a task to wake we do
+        // not want the task to run until we have finished the ISR, so
+        // xQueueSendFromISR does not cause a context switch.  Also we
+        // don't want subsequent posts to wake any other tasks, so we store
+        // the return value back into cTaskWokenByPost so xQueueSendFromISR
+        // knows not to wake any task the next iteration of the loop.
+        xTaskWokenByPost = xQueueSendToFrontFromISR( xRxQueue, &cIn, cTaskWokenByPost );
+
+    } while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+    // Now the buffer is empty we can switch context if necessary.
+    if( cTaskWokenByPost )
+    {
+        taskYIELD ();
+    }
+ }
+
    + * + * \defgroup xQueueSendFromISR xQueueSendFromISR + * \ingroup QueueManagement + */ +#define xQueueSendToFrontFromISR( pxQueue, pvItemToQueue, xTaskPreviouslyWoken ) xQueueGenericSendFromISR( pxQueue, pvItemToQueue, xTaskPreviouslyWoken, queueSEND_TO_FRONT ) + + +/** + * queue. h + * 
    + portBASE_TYPE xQueueSendToBackFromISR(
+                                         xQueueHandle pxQueue,
+                                         const void *pvItemToQueue,
+                                         portBASE_TYPE xTaskPreviouslyWoken
+                                      );
+
    + * + * This is a macro that calls xQueueGenericSendFromISR(). + * + * Post an item to the back of a queue. It is safe to use this macro from + * within an interrupt service routine. + * + * Items are queued by copy not reference so it is preferable to only + * queue small items, especially when called from an ISR. In most cases + * it would be preferable to store a pointer to the item being queued. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param cTaskPreviouslyWoken This is included so an ISR can post onto + * the same queue multiple times from a single interrupt. The first call + * should always pass in pdFALSE. Subsequent calls should pass in + * the value returned from the previous call. See the file serial .c in the + * PC port for a good example of this mechanism. + * + * @return pdTRUE if a task was woken by posting onto the queue. This is + * used by the ISR to determine if a context switch may be required following + * the ISR. + * + * Example usage for buffered IO (where the ISR can obtain more than one value + * per call): + 
    + void vBufferISR( void )
+ {
+ portCHAR cIn;
+ portBASE_TYPE xTaskWokenByPost;
+
+    // We have not woken a task at the start of the ISR.
+    cTaskWokenByPost = pdFALSE;
+
+    // Loop until the buffer is empty.
+    do
+    {
+        // Obtain a byte from the buffer.
+        cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );						
+
+        // Post the byte.  The first time round the loop cTaskWokenByPost
+        // will be pdFALSE.  If the queue send causes a task to wake we do
+        // not want the task to run until we have finished the ISR, so
+        // xQueueSendFromISR does not cause a context switch.  Also we
+        // don't want subsequent posts to wake any other tasks, so we store
+        // the return value back into cTaskWokenByPost so xQueueSendFromISR
+        // knows not to wake any task the next iteration of the loop.
+        xTaskWokenByPost = xQueueSendToBackFromISR( xRxQueue, &cIn, cTaskWokenByPost );
+
+    } while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+    // Now the buffer is empty we can switch context if necessary.
+    if( cTaskWokenByPost )
+    {
+        taskYIELD ();
+    }
+ }
+
    + * + * \defgroup xQueueSendFromISR xQueueSendFromISR + * \ingroup QueueManagement + */ +#define xQueueSendToBackFromISR( pxQueue, pvItemToQueue, xTaskPreviouslyWoken ) xQueueGenericSendFromISR( pxQueue, pvItemToQueue, xTaskPreviouslyWoken, queueSEND_TO_BACK ) + + +/** + * queue. h + * 
    + portBASE_TYPE xQueueSendFromISR(
+                                     xQueueHandle pxQueue,
+                                     const void *pvItemToQueue,
+                                     portBASE_TYPE xTaskPreviouslyWoken
+                                );
+
    + * + * This is a macro that calls xQueueGenericSendFromISR(). It is included + * for backward compatibility with versions of FreeRTOS.org that did not + * include the xQueueSendToBackFromISR() and xQueueSendToFrontFromISR() + * macros. + * + * Post an item to the back of a queue. It is safe to use this function from + * within an interrupt service routine. + * + * Items are queued by copy not reference so it is preferable to only + * queue small items, especially when called from an ISR. In most cases + * it would be preferable to store a pointer to the item being queued. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param cTaskPreviouslyWoken This is included so an ISR can post onto + * the same queue multiple times from a single interrupt. The first call + * should always pass in pdFALSE. Subsequent calls should pass in + * the value returned from the previous call. See the file serial .c in the + * PC port for a good example of this mechanism. + * + * @return pdTRUE if a task was woken by posting onto the queue. This is + * used by the ISR to determine if a context switch may be required following + * the ISR. + * + * Example usage for buffered IO (where the ISR can obtain more than one value + * per call): + 
    + void vBufferISR( void )
+ {
+ portCHAR cIn;
+ portBASE_TYPE xTaskWokenByPost;
+
+    // We have not woken a task at the start of the ISR.
+    cTaskWokenByPost = pdFALSE;
+
+    // Loop until the buffer is empty.
+    do
+    {
+        // Obtain a byte from the buffer.
+        cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );						
+
+        // Post the byte.  The first time round the loop cTaskWokenByPost
+        // will be pdFALSE.  If the queue send causes a task to wake we do
+        // not want the task to run until we have finished the ISR, so
+        // xQueueSendFromISR does not cause a context switch.  Also we
+        // don't want subsequent posts to wake any other tasks, so we store
+        // the return value back into cTaskWokenByPost so xQueueSendFromISR
+        // knows not to wake any task the next iteration of the loop.
+        xTaskWokenByPost = xQueueSendFromISR( xRxQueue, &cIn, cTaskWokenByPost );
+
+    } while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+    // Now the buffer is empty we can switch context if necessary.
+    if( cTaskWokenByPost )
+    {
+        taskYIELD ();
+    }
+ }
+
    + * + * \defgroup xQueueSendFromISR xQueueSendFromISR + * \ingroup QueueManagement + */ +#define xQueueSendFromISR( pxQueue, pvItemToQueue, xTaskPreviouslyWoken ) xQueueGenericSendFromISR( pxQueue, pvItemToQueue, xTaskPreviouslyWoken, queueSEND_TO_BACK ) + +/** + * queue. h + * 
    + portBASE_TYPE xQueueGenericSendFromISR(
+                                           xQueueHandle pxQueue,
+                                           const void *pvItemToQueue,
+                                           portBASE_TYPE xTaskPreviouslyWoken
+										   portBASE_TYPE xCopyPosition
+                                       );
+
    + * + * It is preferred that the macros xQueueSendFromISR(), + * xQueueSendToFrontFromISR() and xQueueSendToBackFromISR() be used in place + * of calling this function directly. + * + * Post an item on a queue. It is safe to use this function from within an + * interrupt service routine. + * + * Items are queued by copy not reference so it is preferable to only + * queue small items, especially when called from an ISR. In most cases + * it would be preferable to store a pointer to the item being queued. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param cTaskPreviouslyWoken This is included so an ISR can post onto + * the same queue multiple times from a single interrupt. The first call + * should always pass in pdFALSE. Subsequent calls should pass in + * the value returned from the previous call. See the file serial .c in the + * PC port for a good example of this mechanism. + * + * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the + * item at the back of the queue, or queueSEND_TO_FRONT to place the item + * at the front of the queue (for high priority messages). + * + * @return pdTRUE if a task was woken by posting onto the queue. This is + * used by the ISR to determine if a context switch may be required following + * the ISR. + * + * Example usage for buffered IO (where the ISR can obtain more than one value + * per call): + 
    + void vBufferISR( void )
+ {
+ portCHAR cIn;
+ portBASE_TYPE xTaskWokenByPost;
+
+    // We have not woken a task at the start of the ISR.
+    cTaskWokenByPost = pdFALSE;
+
+    // Loop until the buffer is empty.
+    do
+    {
+        // Obtain a byte from the buffer.
+        cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );						
+
+        // Post the byte.  The first time round the loop cTaskWokenByPost
+        // will be pdFALSE.  If the queue send causes a task to wake we do
+        // not want the task to run until we have finished the ISR, so
+        // xQueueSendFromISR does not cause a context switch.  Also we
+        // don't want subsequent posts to wake any other tasks, so we store
+        // the return value back into cTaskWokenByPost so xQueueSendFromISR
+        // knows not to wake any task the next iteration of the loop.
+        xTaskWokenByPost = xQueueGenericSendFromISR( xRxQueue, &cIn, cTaskWokenByPost, queueSEND_TO_BACK );
+
+    } while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+    // Now the buffer is empty we can switch context if necessary.
+    if( cTaskWokenByPost )
+    {
+        taskYIELD ();
+    }
+ }
+
    + * + * \defgroup xQueueSendFromISR xQueueSendFromISR + * \ingroup QueueManagement + */ +signed portBASE_TYPE xQueueGenericSendFromISR( xQueueHandle pxQueue, const void * const pvItemToQueue, signed portBASE_TYPE xTaskPreviouslyWoken, portBASE_TYPE xCopyPosition ); + +/** + * queue. h + * 
    + portBASE_TYPE xQueueReceiveFromISR(
+                                       xQueueHandle pxQueue,
+                                       void *pvBuffer,
+                                       portBASE_TYPE *pxTaskWoken
+                                   );
+ *
    + * + * Receive an item from a queue. It is safe to use this function from within an + * interrupt service routine. + * + * @param pxQueue The handle to the queue from which the item is to be + * received. + * + * @param pvBuffer Pointer to the buffer into which the received item will + * be copied. + * + * @param pxTaskWoken A task may be blocked waiting for space to become + * available on the queue. If xQueueReceiveFromISR causes such a task to + * unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will + * remain unchanged. + * + * @return pdTRUE if an item was successfully received from the queue, + * otherwise pdFALSE. + * + * Example usage: + 
    +
+ xQueueHandle xQueue;
+
+ // Function to create a queue and post some values.
+ void vAFunction( void *pvParameters )
+ {
+ portCHAR cValueToPost;
+ const portTickType xBlockTime = ( portTickType )0xff;
+
+    // Create a queue capable of containing 10 characters.
+    xQueue = xQueueCreate( 10, sizeof( portCHAR ) );
+    if( xQueue == 0 )
+    {
+        // Failed to create the queue.
+    }
+
+    // ...
+
+    // Post some characters that will be used within an ISR.  If the queue
+    // is full then this task will block for xBlockTime ticks.
+    cValueToPost = 'a';
+    xQueueSend( xQueue, ( void * ) &cValueToPost, xBlockTime );
+    cValueToPost = 'b';
+    xQueueSend( xQueue, ( void * ) &cValueToPost, xBlockTime );
+
+    // ... keep posting characters ... this task may block when the queue
+    // becomes full.
+
+    cValueToPost = 'c';
+    xQueueSend( xQueue, ( void * ) &cValueToPost, xBlockTime );
+ }
+
+ // ISR that outputs all the characters received on the queue.
+ void vISR_Routine( void )
+ {
+ portBASE_TYPE xTaskWokenByReceive = pdFALSE;
+ portCHAR cRxedChar;
+
+    while( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xTaskWokenByReceive) )
+    {
+        // A character was received.  Output the character now.
+        vOutputCharacter( cRxedChar );
+
+        // If removing the character from the queue woke the task that was
+        // posting onto the queue cTaskWokenByReceive will have been set to
+        // pdTRUE.  No matter how many times this loop iterates only one
+        // task will be woken.
+    }
+
+    if( cTaskWokenByPost != ( portCHAR ) pdFALSE;
+    {
+        taskYIELD ();
+    }
+ }
+
    + * \defgroup xQueueReceiveFromISR xQueueReceiveFromISR + * \ingroup QueueManagement + */ +signed portBASE_TYPE xQueueReceiveFromISR( xQueueHandle pxQueue, const void * const pvBuffer, signed portBASE_TYPE *pxTaskWoken ); + +/* + * xQueueAltGenericSend() is an alternative version of xQueueGenericSend(). + * Likewise xQueueAltGenericReceive() is an alternative version of + * xQueueGenericReceive(). + * + * The source code that implements the alternative (Alt) API is much + * simpler because it executes everything from within a critical section. + * This is the approach taken by many other RTOSes, but FreeRTOS.org has the + * preferred fully featured API too. The fully featured API has more + * complex code that takes longer to execute, but makes much less use of + * critical sections. Therefore the alternative API sacrifices interrupt + * responsiveness to gain execution speed, whereas the fully featured API + * sacrifices execution speed to ensure better interrupt responsiveness. + */ +signed portBASE_TYPE xQueueAltGenericSend( xQueueHandle pxQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition ); +signed portBASE_TYPE xQueueAltGenericReceive( xQueueHandle pxQueue, const void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking ); +#define xQueueAltSendToFront( xQueue, pvItemToQueue, xTicksToWait ) xQueueAltGenericSend( xQueue, pvItemToQueue, xTicksToWait, queueSEND_TO_FRONT ) +#define xQueueAltSendToBack( xQueue, pvItemToQueue, xTicksToWait ) xQueueAltGenericSend( xQueue, pvItemToQueue, xTicksToWait, queueSEND_TO_BACK ) +#define xQueueAltReceive( xQueue, pvBuffer, xTicksToWait ) xQueueAltGenericReceive( xQueue, pvBuffer, xTicksToWait, pdFALSE ) +#define xQueueAltPeek( xQueue, pvBuffer, xTicksToWait ) xQueueAltGenericReceive( xQueue, pvBuffer, xTicksToWait, pdTRUE ) + +/* + * The functions defined above are for passing data to and from tasks. The + * functions below are the equivalents for passing data to and from + * co-routines. + * + * These functions are called from the co-routine macro implementation and + * should not be called directly from application code. Instead use the macro + * wrappers defined within croutine.h. + */ +signed portBASE_TYPE xQueueCRSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xCoRoutinePreviouslyWoken ); +signed portBASE_TYPE xQueueCRReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken ); +signed portBASE_TYPE xQueueCRSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait ); +signed portBASE_TYPE xQueueCRReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait ); + +/* + * For internal use only. Use xSemaphoreCreateMutex() or + * xSemaphoreCreateCounting() instead of calling these functions directly. + */ +xQueueHandle xQueueCreateMutex( void ); +xQueueHandle xQueueCreateCountingSemaphore( unsigned portBASE_TYPE uxCountValue, unsigned portBASE_TYPE uxInitialCount ); + +/* + * For internal use only. Use xSemaphoreTakeMutexRecursive() or + * xSemaphoreGiveMutexRecursive() instead of calling these functions directly. + */ +portBASE_TYPE xQueueTakeMutexRecursive( xQueueHandle xMutex, portTickType xBlockTime ); +portBASE_TYPE xQueueGiveMutexRecursive( xQueueHandle xMutex ); + +#ifdef __cplusplus +} +#endif + +#endif /* QUEUE_H */ + diff --git a/20080212/Source/include/semphr.h b/20080212/Source/include/semphr.h new file mode 100644 index 000000000..7f7389388 --- /dev/null +++ b/20080212/Source/include/semphr.h @@ -0,0 +1,698 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef SEMAPHORE_H +#define SEMAPHORE_H + +#include "queue.h" + +typedef xQueueHandle xSemaphoreHandle; + +#define semBINARY_SEMAPHORE_QUEUE_LENGTH ( ( unsigned portCHAR ) 1 ) +#define semSEMAPHORE_QUEUE_ITEM_LENGTH ( ( unsigned portCHAR ) 0 ) +#define semGIVE_BLOCK_TIME ( ( portTickType ) 0 ) + + +/** + * semphr. h + * 
    vSemaphoreCreateBinary( xSemaphoreHandle xSemaphore )
    + * + * Macro that implements a semaphore by using the existing queue mechanism. + * The queue length is 1 as this is a binary semaphore. The data size is 0 + * as we don't want to actually store any data - we just want to know if the + * queue is empty or full. + * + * This type of semaphore can be used for pure synchronisation between tasks or + * between an interrupt and a task. The semaphore need not be given back once + * obtained, so one task/interrupt can continuously 'give' the semaphore while + * another continuously 'takes' the semaphore. For this reason this type of + * semaphore does not use a priority inheritance mechanism. For an alternative + * that does use priority inheritance see xSemaphoreCreateMutex(). + * + * @param xSemaphore Handle to the created semaphore. Should be of type xSemaphoreHandle. + * + * Example usage: + 
    + xSemaphoreHandle xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to vSemaphoreCreateBinary ().
+    // This is a macro so pass the variable in directly.
+    vSemaphoreCreateBinary( xSemaphore );
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.  
+    }
+ }
+
    + * \defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary + * \ingroup Semaphores + */ +#define vSemaphoreCreateBinary( xSemaphore ) { \ + xSemaphore = xQueueCreate( ( unsigned portBASE_TYPE ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH ); \ + if( xSemaphore != NULL ) \ + { \ + xSemaphoreGive( xSemaphore ); \ + } \ + } + +/** + * semphr. h + * xSemaphoreTake( + * xSemaphoreHandle xSemaphore, + * portTickType xBlockTime + * ) + * + * Macro to obtain a semaphore. The semaphore must have previously been + * created with a call to vSemaphoreCreateBinary(), xSemaphoreCreateMutex() or + * xSemaphoreCreateCounting(). + * + * @param xSemaphore A handle to the semaphore being taken - obtained when + * the semaphore was created. + * + * @param xBlockTime The time in ticks to wait for the semaphore to become + * available. The macro portTICK_RATE_MS can be used to convert this to a + * real time. A block time of zero can be used to poll the semaphore. A block + * time of portMAX_DELAY can be used to block indefinitely (provided + * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h). + * + * @return pdTRUE if the semaphore was obtained. pdFALSE + * if xBlockTime expired without the semaphore becoming available. + * + * Example usage: + 
    + xSemaphoreHandle xSemaphore = NULL;
+
+ // A task that creates a semaphore.
+ void vATask( void * pvParameters )
+ {
+    // Create the semaphore to guard a shared resource.
+    vSemaphoreCreateBinary( xSemaphore );
+ }
+
+ // A task that uses the semaphore.
+ void vAnotherTask( void * pvParameters )
+ {
+    // ... Do other things.
+
+    if( xSemaphore != NULL )
+    {
+        // See if we can obtain the semaphore.  If the semaphore is not available
+        // wait 10 ticks to see if it becomes free.	
+        if( xSemaphoreTake( xSemaphore, ( portTickType ) 10 ) == pdTRUE )
+        {
+            // We were able to obtain the semaphore and can now access the
+            // shared resource.
+
+            // ...
+
+            // We have finished accessing the shared resource.  Release the 
+            // semaphore.
+            xSemaphoreGive( xSemaphore );
+        }
+        else
+        {
+            // We could not obtain the semaphore and can therefore not access
+            // the shared resource safely.
+        }
+    }
+ }
+
    + * \defgroup xSemaphoreTake xSemaphoreTake + * \ingroup Semaphores + */ +#define xSemaphoreTake( xSemaphore, xBlockTime ) xQueueGenericReceive( ( xQueueHandle ) xSemaphore, NULL, xBlockTime, pdFALSE ) + +/** + * semphr. h + * xSemaphoreTakeRecursive( + * xSemaphoreHandle xMutex, + * portTickType xBlockTime + * ) + * + * Macro to recursively obtain, or 'take', a mutex type semaphore. + * The mutex must have previously been created using a call to + * xSemaphoreCreateRecursiveMutex(); + * + * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this + * macro to be available. + * + * This macro must not be used on mutexes created using xSemaphoreCreateMutex(). + * + * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex + * doesn't become available again until the owner has called + * xSemaphoreGiveRecursive() for each successful 'take' request. For example, + * if a task successfully 'takes' the same mutex 5 times then the mutex will + * not be available to any other task until it has also 'given' the mutex back + * exactly five times. + * + * @param xMutex A handle to the mutex being obtained. This is the + * handle returned by xSemaphoreCreateRecursiveMutex(); + * + * @param xBlockTime The time in ticks to wait for the semaphore to become + * available. The macro portTICK_RATE_MS can be used to convert this to a + * real time. A block time of zero can be used to poll the semaphore. If + * the task already owns the semaphore then xSemaphoreTakeRecursive() will + * return immediately no matter what the value of xBlockTime. + * + * @return pdTRUE if the semaphore was obtained. pdFALSE if xBlockTime + * expired without the semaphore becoming available. + * + * Example usage: + 
    + xSemaphoreHandle xMutex = NULL;
+
+ // A task that creates a mutex.
+ void vATask( void * pvParameters )
+ {
+    // Create the mutex to guard a shared resource.
+    xMutex = xSemaphoreCreateRecursiveMutex();
+ }
+
+ // A task that uses the mutex.
+ void vAnotherTask( void * pvParameters )
+ {
+    // ... Do other things.
+
+    if( xMutex != NULL )
+    {
+        // See if we can obtain the mutex.  If the mutex is not available
+        // wait 10 ticks to see if it becomes free.	
+        if( xSemaphoreTakeRecursive( xSemaphore, ( portTickType ) 10 ) == pdTRUE )
+        {
+            // We were able to obtain the mutex and can now access the
+            // shared resource.
+
+            // ...
+            // For some reason due to the nature of the code further calls to 
+			// xSemaphoreTakeRecursive() are made on the same mutex.  In real
+			// code these would not be just sequential calls as this would make
+			// no sense.  Instead the calls are likely to be buried inside
+			// a more complex call structure.
+            xSemaphoreTakeRecursive( xMutex, ( portTickType ) 10 );
+            xSemaphoreTakeRecursive( xMutex, ( portTickType ) 10 );
+
+            // The mutex has now been 'taken' three times, so will not be 
+			// available to another task until it has also been given back
+			// three times.  Again it is unlikely that real code would have
+			// these calls sequentially, but instead buried in a more complex
+			// call structure.  This is just for illustrative purposes.
+            xSemaphoreGiveRecursive( xMutex );
+			xSemaphoreGiveRecursive( xMutex );
+			xSemaphoreGiveRecursive( xMutex );
+
+			// Now the mutex can be taken by other tasks.
+        }
+        else
+        {
+            // We could not obtain the mutex and can therefore not access
+            // the shared resource safely.
+        }
+    }
+ }
+
    + * \defgroup xSemaphoreTakeRecursive xSemaphoreTakeRecursive + * \ingroup Semaphores + */ +#define xSemaphoreTakeRecursive( xMutex, xBlockTime ) xQueueTakeMutexRecursive( xMutex, xBlockTime ) + + +/* + * xSemaphoreAltTake() is an alternative version of xSemaphoreTake(). + * + * The source code that implements the alternative (Alt) API is much + * simpler because it executes everything from within a critical section. + * This is the approach taken by many other RTOSes, but FreeRTOS.org has the + * preferred fully featured API too. The fully featured API has more + * complex code that takes longer to execute, but makes much less use of + * critical sections. Therefore the alternative API sacrifices interrupt + * responsiveness to gain execution speed, whereas the fully featured API + * sacrifices execution speed to ensure better interrupt responsiveness. + */ +#define xSemaphoreAltTake( xSemaphore, xBlockTime ) xQueueAltGenericReceive( ( xQueueHandle ) xSemaphore, NULL, xBlockTime, pdFALSE ) + +/** + * semphr. h + * 
    xSemaphoreGive( xSemaphoreHandle xSemaphore )
    + * + * Macro to release a semaphore. The semaphore must have previously been + * created with a call to vSemaphoreCreateBinary(), xSemaphoreCreateMutex() or + * xSemaphoreCreateCounting(). and obtained using sSemaphoreTake(). + * + * This macro must not be used from an ISR. See xSemaphoreGiveFromISR () for + * an alternative which can be used from an ISR. + * + * This macro must also not be used on semaphores created using + * xSemaphoreCreateRecursiveMutex(). + * + * @param xSemaphore A handle to the semaphore being released. This is the + * handle returned when the semaphore was created. + * + * @return pdTRUE if the semaphore was released. pdFALSE if an error occurred. + * Semaphores are implemented using queues. An error can occur if there is + * no space on the queue to post a message - indicating that the + * semaphore was not first obtained correctly. + * + * Example usage: + 
    + xSemaphoreHandle xSemaphore = NULL;
+
+ void vATask( void * pvParameters )
+ {
+    // Create the semaphore to guard a shared resource.
+    vSemaphoreCreateBinary( xSemaphore );
+
+    if( xSemaphore != NULL )
+    {
+        if( xSemaphoreGive( xSemaphore ) != pdTRUE )
+        {
+            // We would expect this call to fail because we cannot give
+            // a semaphore without first "taking" it!
+        }
+
+        // Obtain the semaphore - don't block if the semaphore is not
+        // immediately available.
+        if( xSemaphoreTake( xSemaphore, ( portTickType ) 0 ) )
+        {
+            // We now have the semaphore and can access the shared resource.
+
+            // ...
+
+            // We have finished accessing the shared resource so can free the
+            // semaphore.
+            if( xSemaphoreGive( xSemaphore ) != pdTRUE )
+            {
+                // We would not expect this call to fail because we must have
+                // obtained the semaphore to get here.
+            }
+        }
+    }
+ }
+
    + * \defgroup xSemaphoreGive xSemaphoreGive + * \ingroup Semaphores + */ +#define xSemaphoreGive( xSemaphore ) xQueueGenericSend( ( xQueueHandle ) xSemaphore, NULL, semGIVE_BLOCK_TIME, queueSEND_TO_BACK ) + +/** + * semphr. h + * 
    xSemaphoreGiveRecursive( xSemaphoreHandle xMutex )
    + * + * Macro to recursively release, or 'give', a mutex type semaphore. + * The mutex must have previously been created using a call to + * xSemaphoreCreateRecursiveMutex(); + * + * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this + * macro to be available. + * + * This macro must not be used on mutexes created using xSemaphoreCreateMutex(). + * + * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex + * doesn't become available again until the owner has called + * xSemaphoreGiveRecursive() for each successful 'take' request. For example, + * if a task successfully 'takes' the same mutex 5 times then the mutex will + * not be available to any other task until it has also 'given' the mutex back + * exactly five times. + * + * @param xMutex A handle to the mutex being released, or 'given'. This is the + * handle returned by xSemaphoreCreateMutex(); + * + * @return pdTRUE if the semaphore was given. + * + * Example usage: + 
    + xSemaphoreHandle xMutex = NULL;
+
+ // A task that creates a mutex.
+ void vATask( void * pvParameters )
+ {
+    // Create the mutex to guard a shared resource.
+    xMutex = xSemaphoreCreateRecursiveMutex();
+ }
+
+ // A task that uses the mutex.
+ void vAnotherTask( void * pvParameters )
+ {
+    // ... Do other things.
+
+    if( xMutex != NULL )
+    {
+        // See if we can obtain the mutex.  If the mutex is not available
+        // wait 10 ticks to see if it becomes free.	
+        if( xSemaphoreTakeRecursive( xMutex, ( portTickType ) 10 ) == pdTRUE )
+        {
+            // We were able to obtain the mutex and can now access the
+            // shared resource.
+
+            // ...
+            // For some reason due to the nature of the code further calls to 
+			// xSemaphoreTakeRecursive() are made on the same mutex.  In real
+			// code these would not be just sequential calls as this would make
+			// no sense.  Instead the calls are likely to be buried inside
+			// a more complex call structure.
+            xSemaphoreTakeRecursive( xMutex, ( portTickType ) 10 );
+            xSemaphoreTakeRecursive( xMutex, ( portTickType ) 10 );
+
+            // The mutex has now been 'taken' three times, so will not be 
+			// available to another task until it has also been given back
+			// three times.  Again it is unlikely that real code would have
+			// these calls sequentially, it would be more likely that the calls
+			// to xSemaphoreGiveRecursive() would be called as a call stack
+			// unwound.  This is just for demonstrative purposes.
+            xSemaphoreGiveRecursive( xMutex );
+			xSemaphoreGiveRecursive( xMutex );
+			xSemaphoreGiveRecursive( xMutex );
+
+			// Now the mutex can be taken by other tasks.
+        }
+        else
+        {
+            // We could not obtain the mutex and can therefore not access
+            // the shared resource safely.
+        }
+    }
+ }
+
    + * \defgroup xSemaphoreGiveRecursive xSemaphoreGiveRecursive + * \ingroup Semaphores + */ +#define xSemaphoreGiveRecursive( xMutex ) xQueueGiveMutexRecursive( xMutex ) + +/* + * xSemaphoreAltGive() is an alternative version of xSemaphoreGive(). + * + * The source code that implements the alternative (Alt) API is much + * simpler because it executes everything from within a critical section. + * This is the approach taken by many other RTOSes, but FreeRTOS.org has the + * preferred fully featured API too. The fully featured API has more + * complex code that takes longer to execute, but makes much less use of + * critical sections. Therefore the alternative API sacrifices interrupt + * responsiveness to gain execution speed, whereas the fully featured API + * sacrifices execution speed to ensure better interrupt responsiveness. + */ +#define xSemaphoreAltGive( xSemaphore ) xQueueAltGenericSend( ( xQueueHandle ) xSemaphore, NULL, semGIVE_BLOCK_TIME, queueSEND_TO_BACK ) + +/** + * semphr. h + * 
    + xSemaphoreGiveFromISR( 
+                          xSemaphoreHandle xSemaphore, 
+                          portSHORT sTaskPreviouslyWoken 
+                      )
    + * + * Macro to release a semaphore. The semaphore must have previously been + * created with a call to vSemaphoreCreateBinary() or xSemaphoreCreateCounting(). + * + * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex()) + * must not be used with this macro. + * + * This macro can be used from an ISR. + * + * @param xSemaphore A handle to the semaphore being released. This is the + * handle returned when the semaphore was created. + * + * @param sTaskPreviouslyWoken This is included so an ISR can make multiple calls + * to xSemaphoreGiveFromISR () from a single interrupt. The first call + * should always pass in pdFALSE. Subsequent calls should pass in + * the value returned from the previous call. See the file serial .c in the + * PC port for a good example of using xSemaphoreGiveFromISR (). + * + * @return pdTRUE if a task was woken by releasing the semaphore. This is + * used by the ISR to determine if a context switch may be required following + * the ISR. + * + * Example usage: + 
    + #define LONG_TIME 0xffff
+ #define TICKS_TO_WAIT	10
+ xSemaphoreHandle xSemaphore = NULL;
+
+ // Repetitive task.
+ void vATask( void * pvParameters )
+ {
+    for( ;; )
+    {
+        // We want this task to run every 10 ticks of a timer.  The semaphore 
+        // was created before this task was started.
+
+        // Block waiting for the semaphore to become available.
+        if( xSemaphoreTake( xSemaphore, LONG_TIME ) == pdTRUE )
+        {
+            // It is time to execute.
+
+            // ...
+
+            // We have finished our task.  Return to the top of the loop where
+            // we will block on the semaphore until it is time to execute 
+            // again.  Note when using the semaphore for synchronisation with an
+			// ISR in this manner there is no need to 'give' the semaphore back.
+        }
+    }
+ }
+
+ // Timer ISR
+ void vTimerISR( void * pvParameters )
+ {
+ static unsigned portCHAR ucLocalTickCount = 0;
+ static portBASE_TYPE xTaskWoken;
+
+    // A timer tick has occurred.
+
+    // ... Do other time functions.
+
+    // Is it time for vATask () to run?
+	xTaskWoken = pdFALSE;
+    ucLocalTickCount++;
+    if( ucLocalTickCount >= TICKS_TO_WAIT )
+    {
+        // Unblock the task by releasing the semaphore.
+        xTaskWoken = xSemaphoreGiveFromISR( xSemaphore, xTaskWoken );
+
+        // Reset the count so we release the semaphore again in 10 ticks time.
+        ucLocalTickCount = 0;
+    }
+
+    if( xTaskWoken != pdFALSE )
+    {
+        // We can force a context switch here.  Context switching from an
+        // ISR uses port specific syntax.  Check the demo task for your port
+        // to find the syntax required.
+    }
+ }
+
    + * \defgroup xSemaphoreGiveFromISR xSemaphoreGiveFromISR + * \ingroup Semaphores + */ +#define xSemaphoreGiveFromISR( xSemaphore, xTaskPreviouslyWoken ) xQueueGenericSendFromISR( ( xQueueHandle ) xSemaphore, NULL, xTaskPreviouslyWoken, queueSEND_TO_BACK ) + +/** + * semphr. h + * 
    xSemaphoreHandle xSemaphoreCreateMutex( void )
    + * + * Macro that implements a mutex semaphore by using the existing queue + * mechanism. + * + * Mutexes created using this macro can be accessed using the xSemaphoreTake() + * and xSemaphoreGive() macros. The xSemaphoreTakeRecursive() and + * xSemaphoreGiveRecursive() macros should not be used. + * + * This type of semaphore uses a priority inheritance mechanism so a task + * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the + * semaphore it is no longer required. + * + * Mutex type semaphores cannot be used from within interrupt service routines. + * + * See xSemaphoreCreateBinary() for an alternative implementation that can be + * used for pure synchronisation (where one task or interrupt always 'gives' the + * semaphore and another always 'takes' the semaphore) and from within interrupt + * service routines. + * + * @return xSemaphore Handle to the created mutex semaphore. Should be of type + * xSemaphoreHandle. + * + * Example usage: + 
    + xSemaphoreHandle xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
+    // This is a macro so pass the variable in directly.
+    xSemaphore = xSemaphoreCreateMutex();
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.  
+    }
+ }
+
    + * \defgroup vSemaphoreCreateMutex vSemaphoreCreateMutex + * \ingroup Semaphores + */ +#define xSemaphoreCreateMutex() xQueueCreateMutex() + + +/** + * semphr. h + * 
    xSemaphoreHandle xSemaphoreCreateRecursiveMutex( void )
    + * + * Macro that implements a recursive mutex by using the existing queue + * mechanism. + * + * Mutexes created using this macro can be accessed using the + * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros. The + * xSemaphoreTake() and xSemaphoreGive() macros should not be used. + * + * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex + * doesn't become available again until the owner has called + * xSemaphoreGiveRecursive() for each successful 'take' request. For example, + * if a task successfully 'takes' the same mutex 5 times then the mutex will + * not be available to any other task until it has also 'given' the mutex back + * exactly five times. + * + * This type of semaphore uses a priority inheritance mechanism so a task + * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the + * semaphore it is no longer required. + * + * Mutex type semaphores cannot be used from within interrupt service routines. + * + * See xSemaphoreCreateBinary() for an alternative implementation that can be + * used for pure synchronisation (where one task or interrupt always 'gives' the + * semaphore and another always 'takes' the semaphore) and from within interrupt + * service routines. + * + * @return xSemaphore Handle to the created mutex semaphore. Should be of type + * xSemaphoreHandle. + * + * Example usage: + 
    + xSemaphoreHandle xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
+    // This is a macro so pass the variable in directly.
+    xSemaphore = xSemaphoreCreateRecursiveMutex();
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.  
+    }
+ }
+
    + * \defgroup vSemaphoreCreateMutex vSemaphoreCreateMutex + * \ingroup Semaphores + */ +#define xSemaphoreCreateRecursiveMutex() xQueueCreateMutex() + +/** + * semphr. h + * 
    xSemaphoreHandle xSemaphoreCreateCounting( unsigned portBASE_TYPE uxMaxCount, unsigned portBASE_TYPE uxInitialCount )
    + * + * Macro that creates a counting semaphore by using the existing + * queue mechanism. + * + * Counting semaphores are typically used for two things: + * + * 1) Counting events. + * + * In this usage scenario an event handler will 'give' a semaphore each time + * an event occurs (incrementing the semaphore count value), and a handler + * task will 'take' a semaphore each time it processes an event + * (decrementing the semaphore count value). The count value is therefore + * the difference between the number of events that have occurred and the + * number that have been processed. In this case it is desirable for the + * initial count value to be zero. + * + * 2) Resource management. + * + * In this usage scenario the count value indicates the number of resources + * available. To obtain control of a resource a task must first obtain a + * semaphore - decrementing the semaphore count value. When the count value + * reaches zero there are no free resources. When a task finishes with the + * resource it 'gives' the semaphore back - incrementing the semaphore count + * value. In this case it is desirable for the initial count value to be + * equal to the maximum count value, indicating that all resources are free. + * + * @param uxMaxCount The maximum count value that can be reached. When the + * semaphore reaches this value it can no longer be 'given'. + * + * @param uxInitialCount The count value assigned to the semaphore when it is + * created. + * + * @return Handle to the created semaphore. Null if the semaphore could not be + * created. + * + * Example usage: + 
    + xSemaphoreHandle xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+ xSemaphoreHandle xSemaphore = NULL;
+
+    // Semaphore cannot be used before a call to xSemaphoreCreateCounting().
+    // The max value to which the semaphore can count should be 10, and the
+    // initial value assigned to the count should be 0.
+    xSemaphore = xSemaphoreCreateCounting( 10, 0 );
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.  
+    }
+ }
+
    + * \defgroup xSemaphoreCreateCounting xSemaphoreCreateCounting + * \ingroup Semaphores + */ +#define xSemaphoreCreateCounting( uxMaxCount, uxInitialCount ) xQueueCreateCountingSemaphore( uxMaxCount, uxInitialCount ) + + +#endif /* SEMAPHORE_H */ + + diff --git a/20080212/Source/include/task.h b/20080212/Source/include/task.h new file mode 100644 index 000000000..40964e52b --- /dev/null +++ b/20080212/Source/include/task.h @@ -0,0 +1,995 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes since V4.3.1: + + + Added xTaskGetSchedulerState() function. +*/ + +#ifndef TASK_H +#define TASK_H + +#include "portable.h" +#include "list.h" + +#ifdef __cplusplus +extern "C" { +#endif +/*----------------------------------------------------------- + * MACROS AND DEFINITIONS + *----------------------------------------------------------*/ + +#define tskKERNEL_VERSION_NUMBER "V4.7.1" + +/** + * task. h + * + * Type by which tasks are referenced. For example, a call to xTaskCreate + * returns (via a pointer parameter) an xTaskHandle variable that can then + * be used as a parameter to vTaskDelete to delete the task. + * + * \page xTaskHandle xTaskHandle + * \ingroup Tasks + */ +typedef void * xTaskHandle; + +/* + * Used internally only. + */ +typedef struct xTIME_OUT +{ + portBASE_TYPE xOverflowCount; + portTickType xTimeOnEntering; +} xTimeOutType; + +/* + * Defines the priority used by the idle task. This must not be modified. + * + * \ingroup TaskUtils + */ +#define tskIDLE_PRIORITY ( ( unsigned portBASE_TYPE ) 0 ) + +/** + * task. h + * + * Macro for forcing a context switch. + * + * \page taskYIELD taskYIELD + * \ingroup SchedulerControl + */ +#define taskYIELD() portYIELD() + +/** + * task. h + * + * Macro to mark the start of a critical code region. Preemptive context + * switches cannot occur when in a critical region. + * + * NOTE: This may alter the stack (depending on the portable implementation) + * so must be used with care! + * + * \page taskENTER_CRITICAL taskENTER_CRITICAL + * \ingroup SchedulerControl + */ +#define taskENTER_CRITICAL() portENTER_CRITICAL() + +/** + * task. h + * + * Macro to mark the end of a critical code region. Preemptive context + * switches cannot occur when in a critical region. + * + * NOTE: This may alter the stack (depending on the portable implementation) + * so must be used with care! + * + * \page taskEXIT_CRITICAL taskEXIT_CRITICAL + * \ingroup SchedulerControl + */ +#define taskEXIT_CRITICAL() portEXIT_CRITICAL() + +/** + * task. h + * + * Macro to disable all maskable interrupts. + * + * \page taskDISABLE_INTERRUPTS taskDISABLE_INTERRUPTS + * \ingroup SchedulerControl + */ +#define taskDISABLE_INTERRUPTS() portDISABLE_INTERRUPTS() + +/** + * task. h + * + * Macro to enable microcontroller interrupts. + * + * \page taskENABLE_INTERRUPTS taskENABLE_INTERRUPTS + * \ingroup SchedulerControl + */ +#define taskENABLE_INTERRUPTS() portENABLE_INTERRUPTS() + +/* Definitions returned by xTaskGetSchedulerState(). */ +#define taskSCHEDULER_NOT_STARTED 0 +#define taskSCHEDULER_RUNNING 1 +#define taskSCHEDULER_SUSPENDED 2 + +/*----------------------------------------------------------- + * TASK CREATION API + *----------------------------------------------------------*/ + +/** + * task. h + *
    + portBASE_TYPE xTaskCreate(
+                              pdTASK_CODE pvTaskCode,
+                              const portCHAR * const pcName,
+                              unsigned portSHORT usStackDepth,
+                              void *pvParameters,
+                              unsigned portBASE_TYPE uxPriority,
+                              xTaskHandle *pvCreatedTask
+                          );
    + * + * Create a new task and add it to the list of tasks that are ready to run. + * + * @param pvTaskCode Pointer to the task entry function. Tasks + * must be implemented to never return (i.e. continuous loop). + * + * @param pcName A descriptive name for the task. This is mainly used to + * facilitate debugging. Max length defined by tskMAX_TASK_NAME_LEN - default + * is 16. + * + * @param usStackDepth The size of the task stack specified as the number of + * variables the stack can hold - not the number of bytes. For example, if + * the stack is 16 bits wide and usStackDepth is defined as 100, 200 bytes + * will be allocated for stack storage. + * + * @param pvParameters Pointer that will be used as the parameter for the task + * being created. + * + * @param uxPriority The priority at which the task should run. + * + * @param pvCreatedTask Used to pass back a handle by which the created task + * can be referenced. + * + * @return pdPASS if the task was successfully created and added to a ready + * list, otherwise an error code defined in the file errors. h + * + * Example usage: + 
    + // Task to be created.
+ void vTaskCode( void * pvParameters )
+ {
+     for( ;; )
+     {
+         // Task code goes here.
+     }
+ }
+
+ // Function that creates a task.
+ void vOtherFunction( void )
+ {
+ unsigned char ucParameterToPass;
+ xTaskHandle xHandle;
+		
+     // Create the task, storing the handle.
+     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, &ucParameterToPass, tskIDLE_PRIORITY, &xHandle );
+		
+     // Use the handle to delete the task.
+     vTaskDelete( xHandle );
+ }
+
    + * \defgroup xTaskCreate xTaskCreate + * \ingroup Tasks + */ +signed portBASE_TYPE xTaskCreate( pdTASK_CODE pvTaskCode, const signed portCHAR * const pcName, unsigned portSHORT usStackDepth, void *pvParameters, unsigned portBASE_TYPE uxPriority, xTaskHandle *pvCreatedTask ); + +/** + * task. h + * 
    void vTaskDelete( xTaskHandle pxTask );
    + * + * INCLUDE_vTaskDelete must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Remove a task from the RTOS real time kernels management. The task being + * deleted will be removed from all ready, blocked, suspended and event lists. + * + * NOTE: The idle task is responsible for freeing the kernel allocated + * memory from tasks that have been deleted. It is therefore important that + * the idle task is not starved of microcontroller processing time if your + * application makes any calls to vTaskDelete (). Memory allocated by the + * task code is not automatically freed, and should be freed before the task + * is deleted. + * + * See the demo application file death.c for sample code that utilises + * vTaskDelete (). + * + * @param pxTask The handle of the task to be deleted. Passing NULL will + * cause the calling task to be deleted. + * + * Example usage: + 
    + void vOtherFunction( void )
+ {
+ xTaskHandle xHandle;
+		
+     // Create the task, storing the handle.
+     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+		
+     // Use the handle to delete the task.
+     vTaskDelete( xHandle );
+ }
+
    + * \defgroup vTaskDelete vTaskDelete + * \ingroup Tasks + */ +void vTaskDelete( xTaskHandle pxTask ); + + +/*----------------------------------------------------------- + * TASK CONTROL API + *----------------------------------------------------------*/ + +/** + * task. h + * 
    void vTaskDelay( portTickType xTicksToDelay );
    + * + * Delay a task for a given number of ticks. The actual time that the + * task remains blocked depends on the tick rate. The constant + * portTICK_RATE_MS can be used to calculate real time from the tick + * rate - with the resolution of one tick period. + * + * INCLUDE_vTaskDelay must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * @param xTicksToDelay The amount of time, in tick periods, that + * the calling task should block. + * + * Example usage: + 
    + // Wait 10 ticks before performing an action.
+ // NOTE:
+ // This is for demonstration only and would be better achieved
+ // using vTaskDelayUntil ().
+ void vTaskFunction( void * pvParameters )
+ {
+ portTickType xDelay, xNextTime;
+
+     // Calc the time at which we want to perform the action
+     // next.
+     xNextTime = xTaskGetTickCount () + ( portTickType ) 10;
+
+     for( ;; )
+     {
+         xDelay = xNextTime - xTaskGetTickCount ();
+         xNextTime += ( portTickType ) 10;
+
+         // Guard against overflow
+         if( xDelay <= ( portTickType ) 10 )
+         {
+             vTaskDelay( xDelay );
+         }
+
+         // Perform action here.
+     }
+ }
+
    + * \defgroup vTaskDelay vTaskDelay + * \ingroup TaskCtrl + */ +void vTaskDelay( portTickType xTicksToDelay ); + +/** + * task. h + * 
    void vTaskDelayUntil( portTickType *pxPreviousWakeTime, portTickType xTimeIncrement );
    + * + * INCLUDE_vTaskDelayUntil must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Delay a task until a specified time. This function can be used by cyclical + * tasks to ensure a constant execution frequency. + * + * This function differs from vTaskDelay () in one important aspect: vTaskDelay () will + * cause a task to block for the specified number of ticks from the time vTaskDelay () is + * called. It is therefore difficult to use vTaskDelay () by itself to generate a fixed + * execution frequency as the time between a task starting to execute and that task + * calling vTaskDelay () may not be fixed [the task may take a different path though the + * code between calls, or may get interrupted or preempted a different number of times + * each time it executes]. + * + * Whereas vTaskDelay () specifies a wake time relative to the time at which the function + * is called, vTaskDelayUntil () specifies the absolute (exact) time at which it wishes to + * unblock. + * + * The constant portTICK_RATE_MS can be used to calculate real time from the tick + * rate - with the resolution of one tick period. + * + * @param pxPreviousWakeTime Pointer to a variable that holds the time at which the + * task was last unblocked. The variable must be initialised with the current time + * prior to its first use (see the example below). Following this the variable is + * automatically updated within vTaskDelayUntil (). + * + * @param xTimeIncrement The cycle time period. The task will be unblocked at + * time *pxPreviousWakeTime + xTimeIncrement. Calling vTaskDelayUntil with the + * same xTimeIncrement parameter value will cause the task to execute with + * a fixed interface period. + * + * Example usage: + 
    + // Perform an action every 10 ticks.
+ void vTaskFunction( void * pvParameters )
+ {
+ portTickType xLastWakeTime;
+ const portTickType xFrequency = 10;
+
+     // Initialise the xLastWakeTime variable with the current time.
+     xLastWakeTime = xTaskGetTickCount ();
+     for( ;; )
+     {
+         // Wait for the next cycle.
+         vTaskDelayUntil( &xLastWakeTime, xFrequency );
+
+         // Perform action here.
+     }
+ }
+
    + * \defgroup vTaskDelayUntil vTaskDelayUntil + * \ingroup TaskCtrl + */ +void vTaskDelayUntil( portTickType * const pxPreviousWakeTime, portTickType xTimeIncrement ); + +/** + * task. h + * 
    unsigned portBASE_TYPE uxTaskPriorityGet( xTaskHandle pxTask );
    + * + * INCLUDE_xTaskPriorityGet must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Obtain the priority of any task. + * + * @param pxTask Handle of the task to be queried. Passing a NULL + * handle results in the priority of the calling task being returned. + * + * @return The priority of pxTask. + * + * Example usage: + 
    + void vAFunction( void )
+ {
+ xTaskHandle xHandle;
+		
+     // Create a task, storing the handle.
+     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+		
+     // ...
+
+     // Use the handle to obtain the priority of the created task.
+     // It was created with tskIDLE_PRIORITY, but may have changed
+     // it itself.
+     if( uxTaskPriorityGet( xHandle ) != tskIDLE_PRIORITY )
+     {
+         // The task has changed it's priority.
+     }
+
+     // ...
+
+     // Is our priority higher than the created task?
+     if( uxTaskPriorityGet( xHandle ) < uxTaskPriorityGet( NULL ) )
+     {
+         // Our priority (obtained using NULL handle) is higher.
+     }
+ }
+
    + * \defgroup uxTaskPriorityGet uxTaskPriorityGet + * \ingroup TaskCtrl + */ +unsigned portBASE_TYPE uxTaskPriorityGet( xTaskHandle pxTask ); + +/** + * task. h + * 
    void vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority );
    + * + * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Set the priority of any task. + * + * A context switch will occur before the function returns if the priority + * being set is higher than the currently executing task. + * + * @param pxTask Handle to the task for which the priority is being set. + * Passing a NULL handle results in the priority of the calling task being set. + * + * @param uxNewPriority The priority to which the task will be set. + * + * Example usage: + 
    + void vAFunction( void )
+ {
+ xTaskHandle xHandle;
+		
+     // Create a task, storing the handle.
+     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+     // ...
+
+     // Use the handle to raise the priority of the created task.
+     vTaskPrioritySet( xHandle, tskIDLE_PRIORITY + 1 );
+
+     // ...
+
+     // Use a NULL handle to raise our priority to the same value.
+     vTaskPrioritySet( NULL, tskIDLE_PRIORITY + 1 );
+ }
+
    + * \defgroup vTaskPrioritySet vTaskPrioritySet + * \ingroup TaskCtrl + */ +void vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority ); + +/** + * task. h + * 
    void vTaskSuspend( xTaskHandle pxTaskToSuspend );
    + * + * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Suspend any task. When suspended a task will never get any microcontroller + * processing time, no matter what its priority. + * + * Calls to vTaskSuspend are not accumulative - + * i.e. calling vTaskSuspend () twice on the same task still only requires one + * call to vTaskResume () to ready the suspended task. + * + * @param pxTaskToSuspend Handle to the task being suspended. Passing a NULL + * handle will cause the calling task to be suspended. + * + * Example usage: + 
    + void vAFunction( void )
+ {
+ xTaskHandle xHandle;
+		
+     // Create a task, storing the handle.
+     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+		
+     // ...
+
+     // Use the handle to suspend the created task.
+     vTaskSuspend( xHandle );
+
+     // ...
+		
+     // The created task will not run during this period, unless
+     // another task calls vTaskResume( xHandle ).
+		
+     //...
+		
+
+     // Suspend ourselves.
+     vTaskSuspend( NULL );
+
+     // We cannot get here unless another task calls vTaskResume
+     // with our handle as the parameter.
+ }
+
    + * \defgroup vTaskSuspend vTaskSuspend + * \ingroup TaskCtrl + */ +void vTaskSuspend( xTaskHandle pxTaskToSuspend ); + +/** + * task. h + * 
    void vTaskResume( xTaskHandle pxTaskToResume );
    + * + * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Resumes a suspended task. + * + * A task that has been suspended by one of more calls to vTaskSuspend () + * will be made available for running again by a single call to + * vTaskResume (). + * + * @param pxTaskToResume Handle to the task being readied. + * + * Example usage: + 
    + void vAFunction( void )
+ {
+ xTaskHandle xHandle;
+		
+     // Create a task, storing the handle.
+     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+		
+     // ...
+
+     // Use the handle to suspend the created task.
+     vTaskSuspend( xHandle );
+
+     // ...
+	
+     // The created task will not run during this period, unless
+     // another task calls vTaskResume( xHandle ).
+		
+     //...
+		
+
+     // Resume the suspended task ourselves.
+     vTaskResume( xHandle );
+
+     // The created task will once again get microcontroller processing
+     // time in accordance with it priority within the system.
+ }
+
    + * \defgroup vTaskResume vTaskResume + * \ingroup TaskCtrl + */ +void vTaskResume( xTaskHandle pxTaskToResume ); + +/** + * task. h + * 
    void xTaskResumeFromISR( xTaskHandle pxTaskToResume );
    + * + * INCLUDE_xTaskResumeFromISR must be defined as 1 for this function to be + * available. See the configuration section for more information. + * + * An implementation of vTaskResume() that can be called from within an ISR. + * + * A task that has been suspended by one of more calls to vTaskSuspend () + * will be made available for running again by a single call to + * xTaskResumeFromISR (). + * + * @param pxTaskToResume Handle to the task being readied. + * + * \defgroup vTaskResumeFromISR vTaskResumeFromISR + * \ingroup TaskCtrl + */ +portBASE_TYPE xTaskResumeFromISR( xTaskHandle pxTaskToResume ); + +/*----------------------------------------------------------- + * SCHEDULER CONTROL + *----------------------------------------------------------*/ + +/** + * task. h + * 
    void vTaskStartScheduler( void );
    + * + * Starts the real time kernel tick processing. After calling the kernel + * has control over which tasks are executed and when. This function + * does not return until an executing task calls vTaskEndScheduler (). + * + * At least one task should be created via a call to xTaskCreate () + * before calling vTaskStartScheduler (). The idle task is created + * automatically when the first application task is created. + * + * See the demo application file main.c for an example of creating + * tasks and starting the kernel. + * + * Example usage: + 
    + void vAFunction( void )
+ {
+     // Create at least one task before starting the kernel.
+     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+
+     // Start the real time kernel with preemption.
+     vTaskStartScheduler ();
+
+     // Will not get here unless a task calls vTaskEndScheduler ()
+ }
+
    + * + * \defgroup vTaskStartScheduler vTaskStartScheduler + * \ingroup SchedulerControl + */ +void vTaskStartScheduler( void ); + +/** + * task. h + * 
    void vTaskEndScheduler( void );
    + * + * Stops the real time kernel tick. All created tasks will be automatically + * deleted and multitasking (either preemptive or cooperative) will + * stop. Execution then resumes from the point where vTaskStartScheduler () + * was called, as if vTaskStartScheduler () had just returned. + * + * See the demo application file main. c in the demo/PC directory for an + * example that uses vTaskEndScheduler (). + * + * vTaskEndScheduler () requires an exit function to be defined within the + * portable layer (see vPortEndScheduler () in port. c for the PC port). This + * performs hardware specific operations such as stopping the kernel tick. + * + * vTaskEndScheduler () will cause all of the resources allocated by the + * kernel to be freed - but will not free resources allocated by application + * tasks. + * + * Example usage: + 
    + void vTaskCode( void * pvParameters )
+ {
+     for( ;; )
+     {
+         // Task code goes here.
+
+         // At some point we want to end the real time kernel processing
+         // so call ...
+         vTaskEndScheduler ();
+     }
+ }
+
+ void vAFunction( void )
+ {
+     // Create at least one task before starting the kernel.
+     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+
+     // Start the real time kernel with preemption.
+     vTaskStartScheduler ();
+
+     // Will only get here when the vTaskCode () task has called
+     // vTaskEndScheduler ().  When we get here we are back to single task
+     // execution.
+ }
+
    + * + * \defgroup vTaskEndScheduler vTaskEndScheduler + * \ingroup SchedulerControl + */ +void vTaskEndScheduler( void ); + +/** + * task. h + * 
    void vTaskSuspendAll( void );
    + * + * Suspends all real time kernel activity while keeping interrupts (including the + * kernel tick) enabled. + * + * After calling vTaskSuspendAll () the calling task will continue to execute + * without risk of being swapped out until a call to xTaskResumeAll () has been + * made. + * + * Example usage: + 
    + void vTask1( void * pvParameters )
+ {
+     for( ;; )
+     {
+         // Task code goes here.
+
+         // ...
+
+         // At some point the task wants to perform a long operation during
+         // which it does not want to get swapped out.  It cannot use
+         // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
+         // operation may cause interrupts to be missed - including the
+         // ticks.
+
+         // Prevent the real time kernel swapping out the task.
+         vTaskSuspendAll ();
+
+         // Perform the operation here.  There is no need to use critical
+         // sections as we have all the microcontroller processing time.
+         // During this time interrupts will still operate and the kernel
+         // tick count will be maintained.
+
+         // ...
+
+         // The operation is complete.  Restart the kernel.
+         xTaskResumeAll ();
+     }
+ }
+
    + * \defgroup vTaskSuspendAll vTaskSuspendAll + * \ingroup SchedulerControl + */ +void vTaskSuspendAll( void ); + +/** + * task. h + * 
    portCHAR xTaskResumeAll( void );
    + * + * Resumes real time kernel activity following a call to vTaskSuspendAll (). + * After a call to vTaskSuspendAll () the kernel will take control of which + * task is executing at any time. + * + * @return If resuming the scheduler caused a context switch then pdTRUE is + * returned, otherwise pdFALSE is returned. + * + * Example usage: + 
    + void vTask1( void * pvParameters )
+ {
+     for( ;; )
+     {
+         // Task code goes here.
+
+         // ...
+
+         // At some point the task wants to perform a long operation during
+         // which it does not want to get swapped out.  It cannot use
+         // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
+         // operation may cause interrupts to be missed - including the
+         // ticks.
+
+         // Prevent the real time kernel swapping out the task.
+         vTaskSuspendAll ();
+
+         // Perform the operation here.  There is no need to use critical
+         // sections as we have all the microcontroller processing time.
+         // During this time interrupts will still operate and the real
+         // time kernel tick count will be maintained.
+
+         // ...
+
+         // The operation is complete.  Restart the kernel.  We want to force
+         // a context switch - but there is no point if resuming the scheduler
+         // caused a context switch already.
+         if( !xTaskResumeAll () )
+         {
+              taskYIELD ();
+         }
+     }
+ }
+
    + * \defgroup xTaskResumeAll xTaskResumeAll + * \ingroup SchedulerControl + */ +signed portBASE_TYPE xTaskResumeAll( void ); + + +/*----------------------------------------------------------- + * TASK UTILITIES + *----------------------------------------------------------*/ + +/** + * task. h + * 
    volatile portTickType xTaskGetTickCount( void );
    + * + * @return The count of ticks since vTaskStartScheduler was called. + * + * \page xTaskGetTickCount xTaskGetTickCount + * \ingroup TaskUtils + */ +portTickType xTaskGetTickCount( void ); + +/** + * task. h + * 
    unsigned portSHORT uxTaskGetNumberOfTasks( void );
    + * + * @return The number of tasks that the real time kernel is currently managing. + * This includes all ready, blocked and suspended tasks. A task that + * has been deleted but not yet freed by the idle task will also be + * included in the count. + * + * \page uxTaskGetNumberOfTasks uxTaskGetNumberOfTasks + * \ingroup TaskUtils + */ +unsigned portBASE_TYPE uxTaskGetNumberOfTasks( void ); + +/** + * task. h + * 
    void vTaskList( portCHAR *pcWriteBuffer );
    + * + * configUSE_TRACE_FACILITY, INCLUDE_vTaskDelete and INCLUDE_vTaskSuspend + * must all be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * NOTE: This function will disable interrupts for its duration. It is + * not intended for normal application runtime use but as a debug aid. + * + * Lists all the current tasks, along with their current state and stack + * usage high water mark. + * + * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or + * suspended ('S'). + * + * @param pcWriteBuffer A buffer into which the above mentioned details + * will be written, in ascii form. This buffer is assumed to be large + * enough to contain the generated report. Approximately 40 bytes per + * task should be sufficient. + * + * \page vTaskList vTaskList + * \ingroup TaskUtils + */ +void vTaskList( signed portCHAR *pcWriteBuffer ); + +/** + * task. h + * 
    void vTaskStartTrace( portCHAR * pcBuffer, unsigned portBASE_TYPE uxBufferSize );
    + * + * Starts a real time kernel activity trace. The trace logs the identity of + * which task is running when. + * + * The trace file is stored in binary format. A separate DOS utility called + * convtrce.exe is used to convert this into a tab delimited text file which + * can be viewed and plotted in a spread sheet. + * + * @param pcBuffer The buffer into which the trace will be written. + * + * @param ulBufferSize The size of pcBuffer in bytes. The trace will continue + * until either the buffer in full, or ulTaskEndTrace () is called. + * + * \page vTaskStartTrace vTaskStartTrace + * \ingroup TaskUtils + */ +void vTaskStartTrace( signed portCHAR * pcBuffer, unsigned portLONG ulBufferSize ); + +/** + * task. h + * 
    unsigned portLONG ulTaskEndTrace( void );
    + * + * Stops a kernel activity trace. See vTaskStartTrace (). + * + * @return The number of bytes that have been written into the trace buffer. + * + * \page usTaskEndTrace usTaskEndTrace + * \ingroup TaskUtils + */ +unsigned portLONG ulTaskEndTrace( void ); + + +/*----------------------------------------------------------- + * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES + *----------------------------------------------------------*/ + +/* + * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS ONLY + * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS + * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. + * + * Called from the real time kernel tick (either preemptive or cooperative), + * this increments the tick count and checks if any tasks that are blocked + * for a finite period required removing from a blocked list and placing on + * a ready list. + */ +inline void vTaskIncrementTick( void ); + +/* + * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN + * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. + * + * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED. + * + * Removes the calling task from the ready list and places it both + * on the list of tasks waiting for a particular event, and the + * list of delayed tasks. The task will be removed from both lists + * and replaced on the ready list should either the event occur (and + * there be no higher priority tasks waiting on the same event) or + * the delay period expires. + * + * @param pxEventList The list containing tasks that are blocked waiting + * for the event to occur. + * + * @param xTicksToWait The maximum amount of time that the task should wait + * for the event to occur. This is specified in kernel ticks,the constant + * portTICK_RATE_MS can be used to convert kernel ticks into a real time + * period. + */ +void vTaskPlaceOnEventList( const xList * const pxEventList, portTickType xTicksToWait ); + +/* + * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN + * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. + * + * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED. + * + * Removes a task from both the specified event list and the list of blocked + * tasks, and places it on a ready queue. + * + * xTaskRemoveFromEventList () will be called if either an event occurs to + * unblock a task, or the block timeout period expires. + * + * @return pdTRUE if the task being removed has a higher priority than the task + * making the call, otherwise pdFALSE. + */ +signed portBASE_TYPE xTaskRemoveFromEventList( const xList * const pxEventList ); + +/* + * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN + * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. + * + * INCLUDE_vTaskCleanUpResources and INCLUDE_vTaskSuspend must be defined as 1 + * for this function to be available. + * See the configuration section for more information. + * + * Empties the ready and delayed queues of task control blocks, freeing the + * memory allocated for the task control block and task stacks as it goes. + */ +void vTaskCleanUpResources( void ); + +/* + * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS ONLY + * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS + * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. + * + * Sets the pointer to the current TCB to the TCB of the highest priority task + * that is ready to run. + */ +inline void vTaskSwitchContext( void ); + +/* + * Return the handle of the calling task. + */ +xTaskHandle xTaskGetCurrentTaskHandle( void ); + +/* + * Capture the current time status for future reference. + */ +void vTaskSetTimeOutState( xTimeOutType * const pxTimeOut ); + +/* + * Compare the time status now with that previously captured to see if the + * timeout has expired. + */ +portBASE_TYPE xTaskCheckForTimeOut( xTimeOutType * const pxTimeOut, portTickType * const pxTicksToWait ); + +/* + * Shortcut used by the queue implementation to prevent unnecessary call to + * taskYIELD(); + */ +void vTaskMissedYield( void ); + +/* + * Returns the scheduler state as taskSCHEDULER_RUNNING, + * taskSCHEDULER_NOT_STARTED or taskSCHEDULER_SUSPENDED. + */ +portBASE_TYPE xTaskGetSchedulerState( void ); + +/* + * Raises the priority of the mutex holder to that of the calling task should + * the mutex holder have a priority less than the calling task. + */ +void vTaskPriorityInherit( xTaskHandle * const pxMutexHolder ); + +/* + * Set the priority of a task back to its proper priority in the case that it + * inherited a higher priority while it was holding a semaphore. + */ +void vTaskPriorityDisinherit( xTaskHandle * const pxMutexHolder ); + +#ifdef __cplusplus +} +#endif +#endif /* TASK_H */ + + + diff --git a/20080212/Source/list.c b/20080212/Source/list.c new file mode 100644 index 000000000..66cba8333 --- /dev/null +++ b/20080212/Source/list.c @@ -0,0 +1,211 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V1.2.0 + + + Removed the volatile modifier from the function parameters. This was + only ever included to prevent compiler warnings. Now warnings are + removed by casting parameters where the calls are made. + + + prvListGetOwnerOfNextEntry() and prvListGetOwnerOfHeadEntry() have been + removed from the c file and added as macros to the h file. + + + uxNumberOfItems has been added to the list structure. This removes the + need for a pointer comparison when checking if a list is empty, and so + is slightly faster. + + + Removed the NULL check in vListRemove(). This makes the call faster but + necessitates any application code utilising the list implementation to + ensure NULL pointers are not passed. + +Changes from V2.0.0 + + + Double linked the lists to allow faster removal item removal. + +Changes from V2.6.1 + + + Make use of the new portBASE_TYPE definition where ever appropriate. + +Changes from V3.0.0 + + + API changes as described on the FreeRTOS.org WEB site. + +Changes from V3.2.4 + + + Removed the pxHead member of the xList structure. This always pointed + to the same place so has been removed to free a few bytes of RAM. + + + Introduced the xMiniListItem structure that does not include the + xListItem members that are not required by the xListEnd member of a list. + Again this was done to reduce RAM usage. + + + Changed the volatile definitions of some structure members to clean up + the code where the list structures are used. + +Changes from V4.0.4 + + + Optimised vListInsert() in the case when the wake time is the maximum + tick count value. +*/ + +#include +#include "FreeRTOS.h" +#include "list.h" + +/*----------------------------------------------------------- + * PUBLIC LIST API documented in list.h + *----------------------------------------------------------*/ + +void vListInitialise( xList *pxList ) +{ + /* The list structure contains a list item which is used to mark the + end of the list. To initialise the list the list end is inserted + as the only list entry. */ + pxList->pxIndex = ( xListItem * ) &( pxList->xListEnd ); + + /* The list end value is the highest possible value in the list to + ensure it remains at the end of the list. */ + pxList->xListEnd.xItemValue = portMAX_DELAY; + + /* The list end next and previous pointers point to itself so we know + when the list is empty. */ + pxList->xListEnd.pxNext = ( xListItem * ) &( pxList->xListEnd ); + pxList->xListEnd.pxPrevious = ( xListItem * ) &( pxList->xListEnd ); + + pxList->uxNumberOfItems = 0; +} +/*-----------------------------------------------------------*/ + +void vListInitialiseItem( xListItem *pxItem ) +{ + /* Make sure the list item is not recorded as being on a list. */ + pxItem->pvContainer = NULL; +} +/*-----------------------------------------------------------*/ + +void vListInsertEnd( xList *pxList, xListItem *pxNewListItem ) +{ +volatile xListItem * pxIndex; + + /* Insert a new list item into pxList, but rather than sort the list, + makes the new list item the last item to be removed by a call to + pvListGetOwnerOfNextEntry. This means it has to be the item pointed to by + the pxIndex member. */ + pxIndex = pxList->pxIndex; + + pxNewListItem->pxNext = pxIndex->pxNext; + pxNewListItem->pxPrevious = pxList->pxIndex; + pxIndex->pxNext->pxPrevious = ( volatile xListItem * ) pxNewListItem; + pxIndex->pxNext = ( volatile xListItem * ) pxNewListItem; + pxList->pxIndex = ( volatile xListItem * ) pxNewListItem; + + /* Remember which list the item is in. */ + pxNewListItem->pvContainer = ( void * ) pxList; + + ( pxList->uxNumberOfItems )++; +} +/*-----------------------------------------------------------*/ + +void vListInsert( xList *pxList, xListItem *pxNewListItem ) +{ +volatile xListItem *pxIterator; +portTickType xValueOfInsertion; + + /* Insert the new list item into the list, sorted in ulListItem order. */ + xValueOfInsertion = pxNewListItem->xItemValue; + + /* If the list already contains a list item with the same item value then + the new list item should be placed after it. This ensures that TCB's which + are stored in ready lists (all of which have the same ulListItem value) + get an equal share of the CPU. However, if the xItemValue is the same as + the back marker the iteration loop below will not end. This means we need + to guard against this by checking the value first and modifying the + algorithm slightly if necessary. */ + if( xValueOfInsertion == portMAX_DELAY ) + { + pxIterator = pxList->xListEnd.pxPrevious; + } + else + { + for( pxIterator = ( xListItem * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) + { + /* There is nothing to do here, we are just iterating to the + wanted insertion position. */ + } + } + + pxNewListItem->pxNext = pxIterator->pxNext; + pxNewListItem->pxNext->pxPrevious = ( volatile xListItem * ) pxNewListItem; + pxNewListItem->pxPrevious = pxIterator; + pxIterator->pxNext = ( volatile xListItem * ) pxNewListItem; + + /* Remember which list the item is in. This allows fast removal of the + item later. */ + pxNewListItem->pvContainer = ( void * ) pxList; + + ( pxList->uxNumberOfItems )++; +} +/*-----------------------------------------------------------*/ + +void vListRemove( xListItem *pxItemToRemove ) +{ +xList * pxList; + + pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious; + pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext; + + /* The list item knows which list it is in. Obtain the list from the list + item. */ + pxList = ( xList * ) pxItemToRemove->pvContainer; + + /* Make sure the index is left pointing to a valid item. */ + if( pxList->pxIndex == pxItemToRemove ) + { + pxList->pxIndex = pxItemToRemove->pxPrevious; + } + + pxItemToRemove->pvContainer = NULL; + ( pxList->uxNumberOfItems )--; +} +/*-----------------------------------------------------------*/ + diff --git a/20080212/Source/portable/BCC/16BitDOS/Flsh186/port.c b/20080212/Source/portable/BCC/16BitDOS/Flsh186/port.c new file mode 100644 index 000000000..8772388d3 --- /dev/null +++ b/20080212/Source/portable/BCC/16BitDOS/Flsh186/port.c @@ -0,0 +1,263 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V1.00: + + + Call to taskYIELD() from within tick ISR has been replaced by the more + efficient portSWITCH_CONTEXT(). + + ISR function definitions renamed to include the prv prefix. + +Changes from V2.6.1 + + + Replaced the sUsingPreemption variable with the configUSE_PREEMPTION + macro to be consistent with the later ports. +*/ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the Flashlite 186 + * port. + *----------------------------------------------------------*/ + +#include +#include +#include + +#include "FreeRTOS.h" +#include "task.h" +#include "portasm.h" + +/*lint -e950 Non ANSI reserved words okay in this file only. */ + +#define portTIMER_EOI_TYPE ( 8 ) +#define portRESET_PIC() portOUTPUT_WORD( ( unsigned portSHORT ) 0xff22, portTIMER_EOI_TYPE ) +#define portTIMER_INT_NUMBER 0x12 + +#define portTIMER_1_CONTROL_REGISTER ( ( unsigned portSHORT ) 0xff5e ) +#define portTIMER_0_CONTROL_REGISTER ( ( unsigned portSHORT ) 0xff56 ) +#define portTIMER_INTERRUPT_ENABLE ( ( unsigned portSHORT ) 0x2000 ) + +/* Setup the hardware to generate the required tick frequency. */ +static void prvSetTickFrequency( unsigned portLONG ulTickRateHz ); + +/* Set the hardware back to the state as per before the scheduler started. */ +static void prvExitFunction( void ); + +/* The ISR used depends on whether the preemptive or cooperative scheduler +is being used. */ +#if( configUSE_PREEMPTION == 1 ) + /* Tick service routine used by the scheduler when preemptive scheduling is + being used. */ + static void __interrupt __far prvPreemptiveTick( void ); +#else + /* Tick service routine used by the scheduler when cooperative scheduling is + being used. */ + static void __interrupt __far prvNonPreemptiveTick( void ); +#endif + +/* Trap routine used by taskYIELD() to manually cause a context switch. */ +static void __interrupt __far prvYieldProcessor( void ); + +/*lint -e956 File scopes necessary here. */ + +/* Set true when the vectors are set so the scheduler will service the tick. */ +static portBASE_TYPE xSchedulerRunning = pdFALSE; + +/* Points to the original routine installed on the vector we use for manual +context switches. This is then used to restore the original routine during +prvExitFunction(). */ +static void ( __interrupt __far *pxOldSwitchISR )(); + +/* Used to restore the original DOS context when the scheduler is ended. */ +static jmp_buf xJumpBuf; + +/*lint +e956 */ + +/*-----------------------------------------------------------*/ +portBASE_TYPE xPortStartScheduler( void ) +{ + /* This is called with interrupts already disabled. */ + + /* Remember what was on the interrupts we are going to use + so we can put them back later if required. */ + pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER ); + + /* Put our manual switch (yield) function on a known + vector. */ + _dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor ); + + #if( configUSE_PREEMPTION == 1 ) + { + /* Put our tick switch function on the timer interrupt. */ + _dos_setvect( portTIMER_INT_NUMBER, prvPreemptiveTick ); + } + #else + { + /* We want the timer interrupt to just increment the tick count. */ + _dos_setvect( portTIMER_INT_NUMBER, prvNonPreemptiveTick ); + } + #endif + + prvSetTickFrequency( configTICK_RATE_HZ ); + + /* Clean up function if we want to return to DOS. */ + if( setjmp( xJumpBuf ) != 0 ) + { + prvExitFunction(); + xSchedulerRunning = pdFALSE; + } + else + { + xSchedulerRunning = pdTRUE; + + /* Kick off the scheduler by setting up the context of the first task. */ + portFIRST_CONTEXT(); + } + + return xSchedulerRunning; +} +/*-----------------------------------------------------------*/ + +/* The ISR used depends on whether the preemptive or cooperative scheduler +is being used. */ +#if( configUSE_PREEMPTION == 1 ) + static void __interrupt __far prvPreemptiveTick( void ) + { + /* Get the scheduler to update the task states following the tick. */ + vTaskIncrementTick(); + + /* Switch in the context of the next task to be run. */ + portSWITCH_CONTEXT(); + + /* Reset the PIC ready for the next time. */ + portRESET_PIC(); + } +#else + static void __interrupt __far prvNonPreemptiveTick( void ) + { + /* Same as preemptive tick, but the cooperative scheduler is being used + so we don't have to switch in the context of the next task. */ + vTaskIncrementTick(); + portRESET_PIC(); + } +#endif +/*-----------------------------------------------------------*/ + +static void __interrupt __far prvYieldProcessor( void ) +{ + /* Switch in the context of the next task to be run. */ + portSWITCH_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Jump back to the processor state prior to starting the + scheduler. This means we are not going to be using a + task stack frame so the task can be deleted. */ + longjmp( xJumpBuf, 1 ); +} +/*-----------------------------------------------------------*/ + +static void prvExitFunction( void ) +{ +const unsigned portSHORT usTimerDisable = 0x0000; +unsigned portSHORT usTimer0Control; + + /* Interrupts should be disabled here anyway - but no + harm in making sure. */ + portDISABLE_INTERRUPTS(); + if( xSchedulerRunning == pdTRUE ) + { + /* Put back the switch interrupt routines that was in place + before the scheduler started. */ + _dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR ); + } + + /* Disable the timer used for the tick to ensure the scheduler is + not called before restoring interrupts. There was previously nothing + on this timer so there is no old ISR to restore. */ + portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerDisable ); + + /* Restart the DOS tick. */ + usTimer0Control = portINPUT_WORD( portTIMER_0_CONTROL_REGISTER ); + usTimer0Control |= portTIMER_INTERRUPT_ENABLE; + portOUTPUT_WORD( portTIMER_0_CONTROL_REGISTER, usTimer0Control ); + + + portENABLE_INTERRUPTS(); + + /* This will free up all the memory used by the scheduler. + exiting back to dos with INT21 AH=4CH will do this anyway so + it is not necessary to call this. */ + vTaskCleanUpResources(); +} +/*-----------------------------------------------------------*/ + +static void prvSetTickFrequency( unsigned portLONG ulTickRateHz ) +{ +const unsigned portSHORT usMaxCountRegister = 0xff5a; +const unsigned portSHORT usTimerPriorityRegister = 0xff32; +const unsigned portSHORT usTimerEnable = 0xC000; +const unsigned portSHORT usRetrigger = 0x0001; +const unsigned portSHORT usTimerHighPriority = 0x0000; +unsigned portSHORT usTimer0Control; + +/* ( CPU frequency / 4 ) / clock 2 max count [inpw( 0xff62 ) = 7] */ + +const unsigned portLONG ulClockFrequency = ( unsigned portLONG ) 0x7f31a0UL; + +unsigned portLONG ulTimerCount = ulClockFrequency / ulTickRateHz; + + portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerEnable | portTIMER_INTERRUPT_ENABLE | usRetrigger ); + portOUTPUT_WORD( usMaxCountRegister, ( unsigned portSHORT ) ulTimerCount ); + portOUTPUT_WORD( usTimerPriorityRegister, usTimerHighPriority ); + + /* Stop the DOS tick - don't do this if you want to maintain a TOD clock. */ + usTimer0Control = portINPUT_WORD( portTIMER_0_CONTROL_REGISTER ); + usTimer0Control &= ~portTIMER_INTERRUPT_ENABLE; + portOUTPUT_WORD( portTIMER_0_CONTROL_REGISTER, usTimer0Control ); +} + + +/*lint +e950 */ + diff --git a/20080212/Source/portable/BCC/16BitDOS/Flsh186/prtmacro.h b/20080212/Source/portable/BCC/16BitDOS/Flsh186/prtmacro.h new file mode 100644 index 000000000..0ef4a26ba --- /dev/null +++ b/20080212/Source/portable/BCC/16BitDOS/Flsh186/prtmacro.h @@ -0,0 +1,108 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE long +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE unsigned portSHORT +#define portBASE_TYPE portSHORT + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +#define portENTER_CRITICAL() __asm{ pushf } \ + __asm{ cli } \ + +#define portEXIT_CRITICAL() __asm{ popf } + +#define portDISABLE_INTERRUPTS() __asm{ cli } + +#define portENABLE_INTERRUPTS() __asm{ sti } +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portNOP() __asm{ nop } +#define portSTACK_GROWTH ( -1 ) +#define portSWITCH_INT_NUMBER 0x80 +#define portYIELD() __asm{ int portSWITCH_INT_NUMBER } +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 2 +#define portINITIAL_SW ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */ +/*-----------------------------------------------------------*/ + +/* Compiler specifics. */ +#define portINPUT_BYTE( xAddr ) inp( xAddr ) +#define portOUTPUT_BYTE( xAddr, ucValue ) outp( xAddr, ucValue ) +#define portINPUT_WORD( xAddr ) inpw( xAddr ) +#define portOUTPUT_WORD( xAddr, usValue ) outpw( xAddr, usValue ) +#define inline +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters ) +#define portTASK_FUNCTION( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters ) + +#endif /* PORTMACRO_H */ + diff --git a/20080212/Source/portable/BCC/16BitDOS/PC/port.c b/20080212/Source/portable/BCC/16BitDOS/PC/port.c new file mode 100644 index 000000000..d3349ebdc --- /dev/null +++ b/20080212/Source/portable/BCC/16BitDOS/PC/port.c @@ -0,0 +1,307 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V2.6.1 + + + Replaced the sUsingPreemption variable with the configUSE_PREEMPTION + macro to be consistent with the later ports. + +Changes from V4.0.1 + + + Add function prvSetTickFrequencyDefault() to set the DOS tick back to + its proper value when the scheduler exits. +*/ + +#include +#include +#include + +#include "FreeRTOS.h" +#include "task.h" +#include "portasm.h" + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the industrial + * PC port. + *----------------------------------------------------------*/ + +/*lint -e950 Non ANSI reserved words okay in this file only. */ + +#define portTIMER_INT_NUMBER 0x08 + +/* Setup hardware for required tick interrupt rate. */ +static void prvSetTickFrequency( unsigned portLONG ulTickRateHz ); + +/* Restore hardware to as it was prior to starting the scheduler. */ +static void prvExitFunction( void ); + +/* Either chain to the DOS tick (which itself clears the PIC) or clear the PIC +directly. We chain to the DOS tick as close as possible to the standard DOS +tick rate. */ +static void prvPortResetPIC( void ); + +/* The ISR used depends on whether the preemptive or cooperative +scheduler is being used. */ +#if( configUSE_PREEMPTION == 1 ) + /* Tick service routine used by the scheduler when preemptive scheduling is + being used. */ + static void __interrupt __far prvPreemptiveTick( void ); +#else + /* Tick service routine used by the scheduler when cooperative scheduling is + being used. */ + static void __interrupt __far prvNonPreemptiveTick( void ); +#endif + +/* Trap routine used by taskYIELD() to manually cause a context switch. */ +static void __interrupt __far prvYieldProcessor( void ); + +/* Set the tick frequency back so the floppy drive works correctly when the +scheduler exits. */ +static void prvSetTickFrequencyDefault( void ); + +/*lint -e956 File scopes necessary here. */ + +/* Used to signal when to chain to the DOS tick, and when to just clear the PIC ourselves. */ +static portSHORT sDOSTickCounter; + +/* Set true when the vectors are set so the scheduler will service the tick. */ +static portBASE_TYPE xSchedulerRunning = pdFALSE; + +/* Points to the original routine installed on the vector we use for manual context switches. This is then used to restore the original routine during prvExitFunction(). */ +static void ( __interrupt __far *pxOldSwitchISR )(); + +/* Points to the original routine installed on the vector we use to chain to the DOS tick. This is then used to restore the original routine during prvExitFunction(). */ +static void ( __interrupt __far *pxOldSwitchISRPlus1 )(); + +/* Used to restore the original DOS context when the scheduler is ended. */ +static jmp_buf xJumpBuf; + +/*lint +e956 */ + +/*-----------------------------------------------------------*/ +portBASE_TYPE xPortStartScheduler( void ) +{ +pxISR pxOriginalTickISR; + + /* This is called with interrupts already disabled. */ + + /* Remember what was on the interrupts we are going to use + so we can put them back later if required. */ + pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER ); + pxOriginalTickISR = _dos_getvect( portTIMER_INT_NUMBER ); + pxOldSwitchISRPlus1 = _dos_getvect( portSWITCH_INT_NUMBER + 1 ); + + prvSetTickFrequency( configTICK_RATE_HZ ); + + /* Put our manual switch (yield) function on a known + vector. */ + _dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor ); + + /* Put the old tick on a different interrupt number so we can + call it when we want. */ + _dos_setvect( portSWITCH_INT_NUMBER + 1, pxOriginalTickISR ); + + /* The ISR used depends on whether the preemptive or cooperative + scheduler is being used. */ + #if( configUSE_PREEMPTION == 1 ) + { + /* Put our tick switch function on the timer interrupt. */ + _dos_setvect( portTIMER_INT_NUMBER, prvPreemptiveTick ); + } + #else + { + /* We want the timer interrupt to just increment the tick count. */ + _dos_setvect( portTIMER_INT_NUMBER, prvNonPreemptiveTick ); + } + #endif + + /* Setup a counter that is used to call the DOS interrupt as close + to it's original frequency as can be achieved given our chosen tick + frequency. */ + sDOSTickCounter = portTICKS_PER_DOS_TICK; + + /* Clean up function if we want to return to DOS. */ + if( setjmp( xJumpBuf ) != 0 ) + { + prvExitFunction(); + xSchedulerRunning = pdFALSE; + } + else + { + xSchedulerRunning = pdTRUE; + + /* Kick off the scheduler by setting up the context of the first task. */ + portFIRST_CONTEXT(); + } + + return xSchedulerRunning; +} +/*-----------------------------------------------------------*/ + +/* The ISR used depends on whether the preemptive or cooperative +scheduler is being used. */ +#if( configUSE_PREEMPTION == 1 ) + static void __interrupt __far prvPreemptiveTick( void ) + { + /* Get the scheduler to update the task states following the tick. */ + vTaskIncrementTick(); + + /* Switch in the context of the next task to be run. */ + portSWITCH_CONTEXT(); + + /* Reset the PIC ready for the next time. */ + prvPortResetPIC(); + } +#else + static void __interrupt __far prvNonPreemptiveTick( void ) + { + /* Same as preemptive tick, but the cooperative scheduler is being used + so we don't have to switch in the context of the next task. */ + vTaskIncrementTick(); + prvPortResetPIC(); + } +#endif +/*-----------------------------------------------------------*/ + +static void __interrupt __far prvYieldProcessor( void ) +{ + /* Switch in the context of the next task to be run. */ + portSWITCH_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +static void prvPortResetPIC( void ) +{ + /* We are going to call the DOS tick interrupt at as close a + frequency to the normal DOS tick as possible. */ + + /* WE SHOULD NOT DO THIS IF YIELD WAS CALLED. */ + --sDOSTickCounter; + if( sDOSTickCounter <= 0 ) + { + sDOSTickCounter = ( portSHORT ) portTICKS_PER_DOS_TICK; + __asm{ int portSWITCH_INT_NUMBER + 1 }; + } + else + { + /* Reset the PIC as the DOS tick is not being called to + do it. */ + __asm + { + mov al, 20H + out 20H, al + }; + } +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Jump back to the processor state prior to starting the + scheduler. This means we are not going to be using a + task stack frame so the task can be deleted. */ + longjmp( xJumpBuf, 1 ); +} +/*-----------------------------------------------------------*/ + +static void prvExitFunction( void ) +{ +void ( __interrupt __far *pxOriginalTickISR )(); + + /* Interrupts should be disabled here anyway - but no + harm in making sure. */ + portDISABLE_INTERRUPTS(); + if( xSchedulerRunning == pdTRUE ) + { + /* Set the DOS tick back onto the timer ticker. */ + pxOriginalTickISR = _dos_getvect( portSWITCH_INT_NUMBER + 1 ); + _dos_setvect( portTIMER_INT_NUMBER, pxOriginalTickISR ); + prvSetTickFrequencyDefault(); + + /* Put back the switch interrupt routines that was in place + before the scheduler started. */ + _dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR ); + _dos_setvect( portSWITCH_INT_NUMBER + 1, pxOldSwitchISRPlus1 ); + } + /* The tick timer is back how DOS wants it. We can re-enable + interrupts without the scheduler being called. */ + portENABLE_INTERRUPTS(); + + /* This will free up all the memory used by the scheduler. + exiting back to dos with INT21 AH=4CH will do this anyway so + it is not necessary to call this. */ + vTaskCleanUpResources(); +} +/*-----------------------------------------------------------*/ + +static void prvSetTickFrequency( unsigned portLONG ulTickRateHz ) +{ +const unsigned portSHORT usPIT_MODE = ( unsigned portSHORT ) 0x43; +const unsigned portSHORT usPIT0 = ( unsigned portSHORT ) 0x40; +const unsigned portLONG ulPIT_CONST = ( unsigned portLONG ) 1193180UL; +const unsigned portSHORT us8254_CTR0_MODE3 = ( unsigned portSHORT ) 0x36; +unsigned portLONG ulOutput; + + /* Setup the 8245 to tick at the wanted frequency. */ + portOUTPUT_BYTE( usPIT_MODE, us8254_CTR0_MODE3 ); + ulOutput = ulPIT_CONST / ulTickRateHz; + portOUTPUT_BYTE( usPIT0, ( unsigned portSHORT )( ulOutput & ( unsigned portLONG ) 0xff ) ); + ulOutput >>= 8; + portOUTPUT_BYTE( usPIT0, ( unsigned portSHORT ) ( ulOutput & ( unsigned portLONG ) 0xff ) ); +} +/*-----------------------------------------------------------*/ + +static void prvSetTickFrequencyDefault( void ) +{ +const unsigned portSHORT usPIT_MODE = ( unsigned portSHORT ) 0x43; +const unsigned portSHORT usPIT0 = ( unsigned portSHORT ) 0x40; +const unsigned portSHORT us8254_CTR0_MODE3 = ( unsigned portSHORT ) 0x36; + + portOUTPUT_BYTE( usPIT_MODE, us8254_CTR0_MODE3 ); + portOUTPUT_BYTE( usPIT0,0 ); + portOUTPUT_BYTE( usPIT0,0 ); +} + + +/*lint +e950 */ + diff --git a/20080212/Source/portable/BCC/16BitDOS/PC/prtmacro.h b/20080212/Source/portable/BCC/16BitDOS/PC/prtmacro.h new file mode 100644 index 000000000..a2338eb5f --- /dev/null +++ b/20080212/Source/portable/BCC/16BitDOS/PC/prtmacro.h @@ -0,0 +1,107 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT long +#define portDOUBLE long +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE unsigned portSHORT +#define portBASE_TYPE portSHORT + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +#define portENTER_CRITICAL() __asm{ pushf } \ + __asm{ cli } \ + +#define portEXIT_CRITICAL() __asm{ popf } + +#define portDISABLE_INTERRUPTS() __asm{ cli } + +#define portENABLE_INTERRUPTS() __asm{ sti } +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portNOP() __asm{ nop } +#define portSTACK_GROWTH ( -1 ) +#define portSWITCH_INT_NUMBER 0x80 +#define portYIELD() __asm{ int portSWITCH_INT_NUMBER } +#define portDOS_TICK_RATE ( 18.20648 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portTICKS_PER_DOS_TICK ( ( unsigned portSHORT ) ( ( ( portDOUBLE ) configTICK_RATE_HZ / portDOS_TICK_RATE ) + 0.5 ) ) +#define portINITIAL_SW ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */ +/*-----------------------------------------------------------*/ + +/* Compiler specifics. */ +#define portINPUT_BYTE( xAddr ) inp( xAddr ) +#define portOUTPUT_BYTE( xAddr, ucValue ) outp( xAddr, ucValue ) +#define inline +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vTaskFunction, pvParameters ) void vTaskFunction( void *pvParameters ) +#define portTASK_FUNCTION( vTaskFunction, pvParameters ) void vTaskFunction( void *pvParameters ) + +#endif /* PORTMACRO_H */ + diff --git a/20080212/Source/portable/BCC/16BitDOS/common/portasm.h b/20080212/Source/portable/BCC/16BitDOS/common/portasm.h new file mode 100644 index 000000000..9b05ae76b --- /dev/null +++ b/20080212/Source/portable/BCC/16BitDOS/common/portasm.h @@ -0,0 +1,102 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef PORT_ASM_H +#define PORT_ASM_H + +typedef void tskTCB; +extern volatile tskTCB * volatile pxCurrentTCB; +extern void vTaskSwitchContext( void ); + +/* + * Saves the stack pointer for one task into its TCB, calls + * vTaskSwitchContext() to update the TCB being used, then restores the stack + * from the new TCB read to run the task. + */ +void portSWITCH_CONTEXT( void ); + +/* + * Load the stack pointer from the TCB of the task which is going to be first + * to execute. Then force an IRET so the registers and IP are popped off the + * stack. + */ +void portFIRST_CONTEXT( void ); + +/* There are slightly different versions depending on whether you are building +to include debugger information. If debugger information is used then there +are a couple of extra bytes left of the ISR stack (presumably for use by the +debugger). The true stack pointer is then stored in the bp register. We add +2 to the stack pointer to remove the extra bytes before we restore our context. */ + +#define portSWITCH_CONTEXT() \ + asm { mov ax, seg pxCurrentTCB } \ + asm { mov ds, ax } \ + asm { les bx, pxCurrentTCB } /* Save the stack pointer into the TCB. */ \ + asm { mov es:0x2[ bx ], ss } \ + asm { mov es:[ bx ], sp } \ + asm { call far ptr vTaskSwitchContext } /* Perform the switch. */ \ + asm { mov ax, seg pxCurrentTCB } /* Restore the stack pointer from the TCB. */ \ + asm { mov ds, ax } \ + asm { les bx, dword ptr pxCurrentTCB } \ + asm { mov ss, es:[ bx + 2 ] } \ + asm { mov sp, es:[ bx ] } + +#define portFIRST_CONTEXT() \ + __asm { mov ax, seg pxCurrentTCB } \ + __asm { mov ds, ax } \ + __asm { les bx, dword ptr pxCurrentTCB } \ + __asm { mov ss, es:[ bx + 2 ] } \ + __asm { mov sp, es:[ bx ] } \ + __asm { pop bp } \ + __asm { pop di } \ + __asm { pop si } \ + __asm { pop ds } \ + __asm { pop es } \ + __asm { pop dx } \ + __asm { pop cx } \ + __asm { pop bx } \ + __asm { pop ax } \ + __asm { iret } + + +#endif + diff --git a/20080212/Source/portable/BCC/16BitDOS/common/portcomn.c b/20080212/Source/portable/BCC/16BitDOS/common/portcomn.c new file mode 100644 index 000000000..391e0e5ae --- /dev/null +++ b/20080212/Source/portable/BCC/16BitDOS/common/portcomn.c @@ -0,0 +1,135 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V1.00: + + + pxPortInitialiseStack() now initialises the stack of new tasks to the + same format used by the compiler. This allows the compiler generated + interrupt mechanism to be used for context switches. + +Changes from V2.6.1 + + + Move usPortCheckFreeStackSpace() to tasks.c. +*/ + + +#include +#include +#include "FreeRTOS.h" + +/*-----------------------------------------------------------*/ + +/* See header file for description. */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ +portSTACK_TYPE DS_Reg = 0; + + /* Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging. */ + + *pxTopOfStack = 0x1111; + pxTopOfStack--; + *pxTopOfStack = 0x2222; + pxTopOfStack--; + *pxTopOfStack = 0x3333; + pxTopOfStack--; + *pxTopOfStack = 0x4444; + pxTopOfStack--; + *pxTopOfStack = 0x5555; + pxTopOfStack--; + + + /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */ + + /* We are going to start the scheduler using a return from interrupt + instruction to load the program counter, so first there would be the + function call with parameters preamble. */ + + *pxTopOfStack = FP_SEG( pvParameters ); + pxTopOfStack--; + *pxTopOfStack = FP_OFF( pvParameters ); + pxTopOfStack--; + *pxTopOfStack = FP_SEG( pxCode ); + pxTopOfStack--; + *pxTopOfStack = FP_OFF( pxCode ); + pxTopOfStack--; + + /* Next the status register and interrupt return address. */ + *pxTopOfStack = portINITIAL_SW; + pxTopOfStack--; + *pxTopOfStack = FP_SEG( pxCode ); + pxTopOfStack--; + *pxTopOfStack = FP_OFF( pxCode ); + pxTopOfStack--; + + /* The remaining registers would be pushed on the stack by our context + switch function. These are loaded with values simply to make debugging + easier. */ + *pxTopOfStack = ( portSTACK_TYPE ) 0xAAAA; /* AX */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xBBBB; /* BX */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xCCCC; /* CX */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xDDDD; /* DX */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xEEEE; /* ES */ + pxTopOfStack--; + + /* We need the true data segment. */ + __asm{ MOV DS_Reg, DS }; + + *pxTopOfStack = DS_Reg; /* DS */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x0123; /* SI */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xDDDD; /* DI */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xBBBB; /* BP */ + + /*lint +e950 +e611 +e923 */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + diff --git a/20080212/Source/portable/CodeWarrior/HCS12/port.c b/20080212/Source/portable/CodeWarrior/HCS12/port.c new file mode 100644 index 000000000..ca11a866f --- /dev/null +++ b/20080212/Source/portable/CodeWarrior/HCS12/port.c @@ -0,0 +1,253 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the HCS12 port. + *----------------------------------------------------------*/ + + +/* + * Configure a timer to generate the RTOS tick at the frequency specified + * within FreeRTOSConfig.h. + */ +static void prvSetupTimerInterrupt( void ); + +/* Interrupt service routines have to be in non-banked memory - as does the +scheduler startup function. */ +#pragma CODE_SEG __NEAR_SEG NON_BANKED + + /* Manual context switch function. This is the SWI ISR. */ + void interrupt vPortYield( void ); + + /* Tick context switch function. This is the timer ISR. */ + void interrupt vPortTickInterrupt( void ); + + /* Simply called by xPortStartScheduler(). xPortStartScheduler() does not + start the scheduler directly because the header file containing the + xPortStartScheduler() prototype is part of the common kernel code, and + therefore cannot use the CODE_SEG pragma. */ + static portBASE_TYPE xBankedStartScheduler( void ); + +#pragma CODE_SEG DEFAULT + +/* Calls to portENTER_CRITICAL() can be nested. When they are nested the +critical section should not be left (i.e. interrupts should not be re-enabled) +until the nesting depth reaches 0. This variable simply tracks the nesting +depth. Each task maintains it's own critical nesting depth variable so +uxCriticalNesting is saved and restored from the task stack during a context +switch. */ +volatile unsigned portBASE_TYPE uxCriticalNesting = 0xff; + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ + /* + Place a few bytes of known values on the bottom of the stack. + This can be uncommented to provide useful stack markers when debugging. + + *pxTopOfStack = ( portSTACK_TYPE ) 0x11; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x22; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x33; + pxTopOfStack--; + */ + + + + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. In this case the stack as + expected by the HCS12 RTI instruction. */ + + + /* The address of the task function is placed in the stack byte at a time. */ + *pxTopOfStack = ( portSTACK_TYPE ) *( ((portSTACK_TYPE *) (&pxCode) ) + 1 ); + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) *( ((portSTACK_TYPE *) (&pxCode) ) + 0 ); + pxTopOfStack--; + + /* Next are all the registers that form part of the task context. */ + + /* Y register */ + *pxTopOfStack = ( portSTACK_TYPE ) 0xff; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xee; + pxTopOfStack--; + + /* X register */ + *pxTopOfStack = ( portSTACK_TYPE ) 0xdd; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xcc; + pxTopOfStack--; + + /* A register contains parameter high byte. */ + *pxTopOfStack = ( portSTACK_TYPE ) *( ((portSTACK_TYPE *) (&pvParameters) ) + 0 ); + pxTopOfStack--; + + /* B register contains parameter low byte. */ + *pxTopOfStack = ( portSTACK_TYPE ) *( ((portSTACK_TYPE *) (&pvParameters) ) + 1 ); + pxTopOfStack--; + + /* CCR: Note that when the task starts interrupts will be enabled since + "I" bit of CCR is cleared */ + *pxTopOfStack = ( portSTACK_TYPE ) 0x00; + pxTopOfStack--; + + #ifdef BANKED_MODEL + /* The page of the task. */ + *pxTopOfStack = ( portSTACK_TYPE ) ( ( int ) pxCode ); + pxTopOfStack--; + #endif + + /* Finally the critical nesting depth is initialised with 0 (not within + a critical section). */ + *pxTopOfStack = ( portSTACK_TYPE ) 0x00; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the HCS12 port will get stopped. */ +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ + TickTimer_SetFreqHz( configTICK_RATE_HZ ); + TickTimer_Enable(); +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xPortStartScheduler( void ) +{ + /* xPortStartScheduler() does not start the scheduler directly because + the header file containing the xPortStartScheduler() prototype is part + of the common kernel code, and therefore cannot use the CODE_SEG pragma. + Instead it simply calls the locally defined xBankedStartScheduler() - + which does use the CODE_SEG pragma. */ + + return xBankedStartScheduler(); +} +/*-----------------------------------------------------------*/ + +#pragma CODE_SEG __NEAR_SEG NON_BANKED + +static portBASE_TYPE xBankedStartScheduler( void ) +{ + /* Configure the timer that will generate the RTOS tick. Interrupts are + disabled when this function is called. */ + prvSetupTimerInterrupt(); + + /* Restore the context of the first task. */ + portRESTORE_CONTEXT(); + + /* Simulate the end of an interrupt to start the scheduler off. */ + __asm( "rti" ); + + /* Should not get here! */ + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +/* + * Context switch functions. These are both interrupt service routines. + */ + +/* + * Manual context switch forced by calling portYIELD(). This is the SWI + * handler. + */ +void interrupt vPortYield( void ) +{ + portSAVE_CONTEXT(); + vTaskSwitchContext(); + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * RTOS tick interrupt service routine. If the cooperative scheduler is + * being used then this simply increments the tick count. If the + * preemptive scheduler is being used a context switch can occur. + */ +void interrupt vPortTickInterrupt( void ) +{ + #if configUSE_PREEMPTION == 1 + { + /* A context switch might happen so save the context. */ + portSAVE_CONTEXT(); + + /* Increment the tick ... */ + vTaskIncrementTick(); + + /* ... then see if the new tick value has necessitated a + context switch. */ + vTaskSwitchContext(); + + TFLG1 = 1; + + /* Restore the context of a task - which may be a different task + to that interrupted. */ + portRESTORE_CONTEXT(); + } + #else + { + vTaskIncrementTick(); + TFLG1 = 1; + } + #endif +} + +#pragma CODE_SEG DEFAULT + + diff --git a/20080212/Source/portable/CodeWarrior/HCS12/portmacro.h b/20080212/Source/portable/CodeWarrior/HCS12/portmacro.h new file mode 100644 index 000000000..1272a6519 --- /dev/null +++ b/20080212/Source/portable/CodeWarrior/HCS12/portmacro.h @@ -0,0 +1,215 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned portCHAR +#define portBASE_TYPE char + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 1 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portYIELD() __asm( "swi" ); +#define portNOP() __asm( "nop" ); +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +#define portENABLE_INTERRUPTS() __asm( "cli" ) +#define portDISABLE_INTERRUPTS() __asm( "sei" ) + +/* + * Disable interrupts before incrementing the count of critical section nesting. + * The nesting count is maintained so we know when interrupts should be + * re-enabled. Once interrupts are disabled the nesting count can be accessed + * directly. Each task maintains its own nesting count. + */ +#define portENTER_CRITICAL() \ +{ \ + extern volatile unsigned portBASE_TYPE uxCriticalNesting; \ + \ + portDISABLE_INTERRUPTS(); \ + uxCriticalNesting++; \ +} + +/* + * Interrupts are disabled so we can access the nesting count directly. If the + * nesting is found to be 0 (no nesting) then we are leaving the critical + * section and interrupts can be re-enabled. + */ +#define portEXIT_CRITICAL() \ +{ \ + extern volatile unsigned portBASE_TYPE uxCriticalNesting; \ + \ + uxCriticalNesting--; \ + if( uxCriticalNesting == 0 ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ +} +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* + * These macros are very simple as the processor automatically saves and + * restores its registers as interrupts are entered and exited. In + * addition to the (automatically stacked) registers we also stack the + * critical nesting count. Each task maintains its own critical nesting + * count as it is legitimate for a task to yield from within a critical + * section. If the banked memory model is being used then the PPAGE + * register is also stored as part of the tasks context. + */ + +#ifdef BANKED_MODEL + /* + * Load the stack pointer for the task, then pull the critical nesting + * count and PPAGE register from the stack. The remains of the + * context are restored by the RTI instruction. + */ + #define portRESTORE_CONTEXT() \ + { \ + extern volatile void * pxCurrentTCB; \ + extern volatile unsigned portBASE_TYPE uxCriticalNesting; \ + \ + __asm( "ldx pxCurrentTCB" ); \ + __asm( "lds 0, x" ); \ + __asm( "pula" ); \ + __asm( "staa uxCriticalNesting" ); \ + __asm( "pula" ); \ + __asm( "staa 0x30" ); /* 0x30 = PPAGE */ \ + } + + /* + * By the time this macro is called the processor has already stacked the + * registers. Simply stack the nesting count and PPAGE value, then save + * the task stack pointer. + */ + #define portSAVE_CONTEXT() \ + { \ + extern volatile void * pxCurrentTCB; \ + extern volatile unsigned portBASE_TYPE uxCriticalNesting; \ + \ + __asm( "ldaa 0x30" ); /* 0x30 = PPAGE */ \ + __asm( "psha" ); \ + __asm( "ldaa uxCriticalNesting" ); \ + __asm( "psha" ); \ + __asm( "ldx pxCurrentTCB" ); \ + __asm( "sts 0, x" ); \ + } +#else + + /* + * These macros are as per the BANKED versions above, but without saving + * and restoring the PPAGE register. + */ + + #define portRESTORE_CONTEXT() \ + { \ + extern volatile void * pxCurrentTCB; \ + extern volatile unsigned portBASE_TYPE uxCriticalNesting; \ + \ + __asm( "ldx pxCurrentTCB" ); \ + __asm( "lds 0, x" ); \ + __asm( "pula" ); \ + __asm( "staa uxCriticalNesting" ); \ + } + + #define portSAVE_CONTEXT() \ + { \ + extern volatile void * pxCurrentTCB; \ + extern volatile unsigned portBASE_TYPE uxCriticalNesting; \ + \ + __asm( "ldaa uxCriticalNesting" ); \ + __asm( "psha" ); \ + __asm( "ldx pxCurrentTCB" ); \ + __asm( "sts 0, x" ); \ + } +#endif + +/* + * Utility macro to call macros above in correct order in order to perform a + * task switch from within a standard ISR. This macro can only be used if + * the ISR does not use any local (stack) variables. If the ISR uses stack + * variables portYIELD() should be used in it's place. + */ +#define portTASK_SWITCH_FROM_ISR() \ + portSAVE_CONTEXT(); \ + vTaskSwitchContext(); \ + portRESTORE_CONTEXT(); + + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#define inline + +#endif /* PORTMACRO_H */ + diff --git a/20080212/Source/portable/GCC/ARM7_AT91FR40008/port.c b/20080212/Source/portable/GCC/ARM7_AT91FR40008/port.c new file mode 100644 index 000000000..0bfc3c0a7 --- /dev/null +++ b/20080212/Source/portable/GCC/ARM7_AT91FR40008/port.c @@ -0,0 +1,249 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the Atmel AT91R40008 + * port. + * + * Components that can be compiled to either ARM or THUMB mode are + * contained in this file. The ISR routines, which can only be compiled + * to ARM mode are contained in portISR.c. + *----------------------------------------------------------*/ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Hardware specific definitions. */ +#include "AT91R40008.h" +#include "pio.h" +#include "aic.h" +#include "tc.h" + +/* Constants required to setup the task context. */ +#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( portSTACK_TYPE ) 0x20 ) +#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 ) +#define portNO_CRITICAL_SECTION_NESTING ( ( portSTACK_TYPE ) 0 ) +#define portTICK_PRIORITY_6 ( 6 ) +/*-----------------------------------------------------------*/ + +/* Setup the timer to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/* + * The scheduler can only be started from ARM mode, so + * vPortISRStartFirstSTask() is defined in portISR.c. + */ +extern void vPortISRStartFirstTask( void ); + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ +portSTACK_TYPE *pxOriginalTOS; + + pxOriginalTOS = pxTopOfStack; + + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. */ + + /* First on the stack is the return address - which in this case is the + start of the task. The offset is added to make the return address appear + as it would within an IRQ ISR. */ + *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */ + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + R0. */ + *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The last thing onto the stack is the status register, which is set for + system mode, with interrupts enabled. */ + *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR; + + #ifdef THUMB_INTERWORK + { + /* We want the task to start in thumb mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + #endif + + pxTopOfStack--; + + /* Some optimisation levels use the stack differently to others. This + means the interrupt flags cannot always be stored on the stack and will + instead be stored in a variable, which is then saved as part of the + tasks context. */ + *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xPortStartScheduler( void ) +{ + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + vPortISRStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ARM port will require this function as there + is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +/* + * Setup the tick timer to generate the tick interrupts at the required frequency. + */ +static void prvSetupTimerInterrupt( void ) +{ +volatile unsigned portLONG ulDummy; + + /* Enable clock to the tick timer... */ + AT91C_BASE_PS->PS_PCER = portTIMER_CLK_ENABLE_BIT; + + /* Stop the tick timer... */ + portTIMER_REG_BASE_PTR->TC_CCR = TC_CLKDIS; + + /* Start with tick timer interrupts disabled... */ + portTIMER_REG_BASE_PTR->TC_IDR = 0xFFFFFFFF; + + /* Clear any pending tick timer interrupts... */ + ulDummy = portTIMER_REG_BASE_PTR->TC_SR; + + /* Store interrupt handler function address in tick timer vector register... + The ISR installed depends on whether the preemptive or cooperative + scheduler is being used. */ + #if configUSE_PREEMPTION == 1 + { + extern void ( vPreemptiveTick )( void ); + AT91C_BASE_AIC->AIC_SVR[portTIMER_AIC_CHANNEL] = ( unsigned portLONG ) vPreemptiveTick; + } + #else // else use cooperative scheduler + { + extern void ( vNonPreemptiveTick )( void ); + AT91C_BASE_AIC->AIC_SVR[portTIMER_AIC_CHANNEL] = ( unsigned portLONG ) vNonPreemptiveTick; + } + #endif + + /* Tick timer interrupt level-sensitive, priority 6... */ + AT91C_BASE_AIC->AIC_SMR[ portTIMER_AIC_CHANNEL ] = AIC_SRCTYPE_INT_LEVEL_SENSITIVE | portTICK_PRIORITY_6; + + /* Enable the tick timer interrupt... + + First at timer level */ + portTIMER_REG_BASE_PTR->TC_IER = TC_CPCS; + + /* Then at the AIC level. */ + AT91C_BASE_AIC->AIC_IECR = (1 << portTIMER_AIC_CHANNEL); + + /* Calculate timer compare value to achieve the desired tick rate... */ + if( (configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 2) ) <= 0xFFFF ) + { + /* The tick rate is fast enough for us to use the faster timer input + clock (main clock / 2). */ + portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK2 | TC_BURST_NONE | TC_CPCTRG; + portTIMER_REG_BASE_PTR->TC_RC = configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 2); + } + else + { + /* We must use a slower timer input clock (main clock / 8) because the + tick rate is too slow for the faster input clock. */ + portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK8 | TC_BURST_NONE | TC_CPCTRG; + portTIMER_REG_BASE_PTR->TC_RC = configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 8); + } + + /* Start tick timer... */ + portTIMER_REG_BASE_PTR->TC_CCR = TC_SWTRG | TC_CLKEN; +} +/*-----------------------------------------------------------*/ + diff --git a/20080212/Source/portable/GCC/ARM7_AT91FR40008/portISR.c b/20080212/Source/portable/GCC/ARM7_AT91FR40008/portISR.c new file mode 100644 index 000000000..fbecfe548 --- /dev/null +++ b/20080212/Source/portable/GCC/ARM7_AT91FR40008/portISR.c @@ -0,0 +1,246 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +/*----------------------------------------------------------- + * Components that can be compiled to either ARM or THUMB mode are + * contained in port.c The ISR routines, which can only be compiled + * to ARM mode, are contained in this file. + *----------------------------------------------------------*/ + +/* + Changes from V3.2.4 + + + The assembler statements are now included in a single asm block rather + than each line having its own asm block. +*/ + + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to handle interrupts. */ +#define portCLEAR_AIC_INTERRUPT ( ( unsigned portLONG ) 0 ) + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 ) +volatile unsigned portLONG ulCriticalNesting = 9999UL; + +/*-----------------------------------------------------------*/ + +/* ISR to handle manual context switches (from a call to taskYIELD()). */ +void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked)); + +/* + * The scheduler can only be started from ARM mode, hence the inclusion of this + * function here. + */ +void vPortISRStartFirstTask( void ); +/*-----------------------------------------------------------*/ + +void vPortISRStartFirstTask( void ) +{ + /* Simply start the scheduler. This is included here as it can only be + called from ARM mode. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * Called by portYIELD() or taskYIELD() to manually force a context switch. + * + * When a context switch is performed from the task level the saved task + * context is made to look as if it occurred from within the tick ISR. This + * way the same restore context function can be used when restoring the context + * saved from the ISR or that saved from a call to vPortYieldProcessor. + */ +void vPortYieldProcessor( void ) +{ + /* Within an IRQ ISR the link register has an offset from the true return + address, but an SWI ISR does not. Add the offset manually so the same + ISR return code can be used in both cases. */ + asm volatile ( "ADD LR, LR, #4" ); + + /* Perform the context switch. First save the context of the current task. */ + portSAVE_CONTEXT(); + + /* Find the highest priority task that is ready to run. */ + vTaskSwitchContext(); + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * The ISR used for the scheduler tick depends on whether the cooperative or + * the preemptive scheduler is being used. + */ + +#if configUSE_PREEMPTION == 0 + + /* The cooperative scheduler requires a normal IRQ service routine to + simply increment the system tick. */ + void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ"))); + void vNonPreemptiveTick( void ) + { + static volatile unsigned portLONG ulDummy; + + /* Clear tick timer interrupt indication. */ + ulDummy = portTIMER_REG_BASE_PTR->TC_SR; + + vTaskIncrementTick(); + + /* Acknowledge the interrupt at AIC level... */ + AT91C_BASE_AIC->AIC_EOICR = portCLEAR_AIC_INTERRUPT; + } + +#else /* else preemption is turned on */ + + /* The preemptive scheduler is defined as "naked" as the full context is + saved on entry as part of the context switch. */ + void vPreemptiveTick( void ) __attribute__((naked)); + void vPreemptiveTick( void ) + { + /* Save the context of the interrupted task. */ + portSAVE_CONTEXT(); + + /* WARNING - Do not use local (stack) variables here. Use globals + if you must! */ + static volatile unsigned portLONG ulDummy; + + /* Clear tick timer interrupt indication. */ + ulDummy = portTIMER_REG_BASE_PTR->TC_SR; + + /* Increment the RTOS tick count, then look for the highest priority + task that is ready to run. */ + vTaskIncrementTick(); + vTaskSwitchContext(); + + /* Acknowledge the interrupt at AIC level... */ + AT91C_BASE_AIC->AIC_EOICR = portCLEAR_AIC_INTERRUPT; + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT(); + } + +#endif +/*-----------------------------------------------------------*/ + +/* + * The interrupt management utilities can only be called from ARM mode. When + * THUMB_INTERWORK is defined the utilities are defined as functions here to + * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then + * the utilities are defined as macros in portmacro.h - as per other ports. + */ +#ifdef THUMB_INTERWORK + + void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); + void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); + + void vPortDisableInterruptsFromThumb( void ) + { + asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0} \n\t" /* Pop R0. */ + "BX R14" ); /* Return back to thumb. */ + } + + void vPortEnableInterruptsFromThumb( void ) + { + asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0} \n\t" /* Pop R0. */ + "BX R14" ); /* Return back to thumb. */ + } + +#endif /* THUMB_INTERWORK */ + +/* The code generated by the GCC compiler uses the stack in different ways at +different optimisation levels. The interrupt flags can therefore not always +be saved to the stack. Instead the critical section nesting level is stored +in a variable, which is then saved as part of the stack context. */ +void vPortEnterCritical( void ) +{ + /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ + asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0}" ); /* Pop R0. */ + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Enable interrupts as per portEXIT_CRITICAL(). */ + asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0}" ); /* Pop R0. */ + } + } +} + diff --git a/20080212/Source/portable/GCC/ARM7_AT91FR40008/portmacro.h b/20080212/Source/portable/GCC/ARM7_AT91FR40008/portmacro.h new file mode 100644 index 000000000..6cd9dcb0d --- /dev/null +++ b/20080212/Source/portable/GCC/ARM7_AT91FR40008/portmacro.h @@ -0,0 +1,266 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + Changes from V3.2.3 + + + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1. + + Changes from V3.2.4 + + + Removed the use of the %0 parameter within the assembler macros and + replaced them with hard coded registers. This will ensure the + assembler does not select the link register as the temp register as + was occasionally happening previously. + + + The assembler statements are now included in a single asm block rather + than each line having its own asm block. + + Changes from V4.5.0 + + + Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros + and replaced them with portYIELD_FROM_ISR() macro. Application code + should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT() + macros as per the V4.5.1 demo code. +*/ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned portLONG +#define portBASE_TYPE long + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 4 +#define portYIELD() asm volatile ( "SWI" ) +#define portNOP() asm volatile ( "NOP" ) + +/* + * These define the timer to use for generating the tick interrupt. + * They are put in this file so they can be shared between "port.c" + * and "portisr.c". + */ +#define portTIMER_REG_BASE_PTR AT91C_BASE_TC0 +#define portTIMER_CLK_ENABLE_BIT AT91C_PS_TC0 +#define portTIMER_AIC_CHANNEL ( ( unsigned portLONG ) 4 ) +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* + * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR + * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but + * are included here for efficiency. An attempt to call one from + * THUMB mode code will result in a compile time error. + */ + +#define portRESTORE_CONTEXT() \ +{ \ +extern volatile void * volatile pxCurrentTCB; \ +extern volatile unsigned portLONG ulCriticalNesting; \ + \ + /* Set the LR to the task stack. */ \ + asm volatile ( \ + "LDR R0, =pxCurrentTCB \n\t" \ + "LDR R0, [R0] \n\t" \ + "LDR LR, [R0] \n\t" \ + \ + /* The critical nesting depth is the first item on the stack. */ \ + /* Load it into the ulCriticalNesting variable. */ \ + "LDR R0, =ulCriticalNesting \n\t" \ + "LDMFD LR!, {R1} \n\t" \ + "STR R1, [R0] \n\t" \ + \ + /* Get the SPSR from the stack. */ \ + "LDMFD LR!, {R0} \n\t" \ + "MSR SPSR, R0 \n\t" \ + \ + /* Restore all system mode registers for the task. */ \ + "LDMFD LR, {R0-R14}^ \n\t" \ + "NOP \n\t" \ + \ + /* Restore the return address. */ \ + "LDR LR, [LR, #+60] \n\t" \ + \ + /* And return - correcting the offset in the LR to obtain the */ \ + /* correct address. */ \ + "SUBS PC, LR, #4 \n\t" \ + ); \ + ( void ) ulCriticalNesting; \ + ( void ) pxCurrentTCB; \ +} +/*-----------------------------------------------------------*/ + +#define portSAVE_CONTEXT() \ +{ \ +extern volatile void * volatile pxCurrentTCB; \ +extern volatile unsigned portLONG ulCriticalNesting; \ + \ + /* Push R0 as we are going to use the register. */ \ + asm volatile ( \ + "STMDB SP!, {R0} \n\t" \ + \ + /* Set R0 to point to the task stack pointer. */ \ + "STMDB SP,{SP}^ \n\t" \ + "NOP \n\t" \ + "SUB SP, SP, #4 \n\t" \ + "LDMIA SP!,{R0} \n\t" \ + \ + /* Push the return address onto the stack. */ \ + "STMDB R0!, {LR} \n\t" \ + \ + /* Now we have saved LR we can use it instead of R0. */ \ + "MOV LR, R0 \n\t" \ + \ + /* Pop R0 so we can save it onto the system mode stack. */ \ + "LDMIA SP!, {R0} \n\t" \ + \ + /* Push all the system mode registers onto the task stack. */ \ + "STMDB LR,{R0-LR}^ \n\t" \ + "NOP \n\t" \ + "SUB LR, LR, #60 \n\t" \ + \ + /* Push the SPSR onto the task stack. */ \ + "MRS R0, SPSR \n\t" \ + "STMDB LR!, {R0} \n\t" \ + \ + "LDR R0, =ulCriticalNesting \n\t" \ + "LDR R0, [R0] \n\t" \ + "STMDB LR!, {R0} \n\t" \ + \ + /* Store the new top of stack for the task. */ \ + "LDR R0, =pxCurrentTCB \n\t" \ + "LDR R0, [R0] \n\t" \ + "STR LR, [R0] \n\t" \ + ); \ + ( void ) ulCriticalNesting; \ + ( void ) pxCurrentTCB; \ +} + +#define portYIELD_FROM_ISR() vTaskSwitchContext() + +/* Critical section handling. */ + +/* + * The interrupt management utilities can only be called from ARM mode. When + * THUMB_INTERWORK is defined the utilities are defined as functions in + * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not + * defined then the utilities are defined as macros here - as per other ports. + */ + +#ifdef THUMB_INTERWORK + + extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); + extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); + + #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb() + #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb() + +#else + + #define portDISABLE_INTERRUPTS() \ + asm volatile ( \ + "STMDB SP!, {R0} \n\t" /* Push R0. */ \ + "MRS R0, CPSR \n\t" /* Get CPSR. */ \ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ + "LDMIA SP!, {R0} " ) /* Pop R0. */ + + #define portENABLE_INTERRUPTS() \ + asm volatile ( \ + "STMDB SP!, {R0} \n\t" /* Push R0. */ \ + "MRS R0, CPSR \n\t" /* Get CPSR. */ \ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ + "LDMIA SP!, {R0} " ) /* Pop R0. */ + +#endif /* THUMB_INTERWORK */ + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/20080212/Source/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h b/20080212/Source/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h new file mode 100644 index 000000000..a14279e0b --- /dev/null +++ b/20080212/Source/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h @@ -0,0 +1,2731 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM7X256.h +// Object : AT91SAM7X256 definitions +// Generated : AT91 SW Application Group 05/20/2005 (16:22:29) +// +// CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005// +// CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// +// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// +// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// +// CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// +// CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// +// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// +// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// +// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// +// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// +// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// +// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// +// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// +// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// +// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// +// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// +// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// +// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// +// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// +// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// +// CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// +// CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// +// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// +// CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// +// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// +// ---------------------------------------------------------------------------- + +#ifndef AT91SAM7X256_H +#define AT91SAM7X256_H + +typedef volatile unsigned int AT91_REG;// Hardware register definition + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** +typedef struct _AT91S_SYS { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register + AT91_REG Reserved2[45]; // + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved3[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved4[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register + AT91_REG Reserved5[54]; // + AT91_REG PIOA_PER; // PIO Enable Register + AT91_REG PIOA_PDR; // PIO Disable Register + AT91_REG PIOA_PSR; // PIO Status Register + AT91_REG Reserved6[1]; // + AT91_REG PIOA_OER; // Output Enable Register + AT91_REG PIOA_ODR; // Output Disable Registerr + AT91_REG PIOA_OSR; // Output Status Register + AT91_REG Reserved7[1]; // + AT91_REG PIOA_IFER; // Input Filter Enable Register + AT91_REG PIOA_IFDR; // Input Filter Disable Register + AT91_REG PIOA_IFSR; // Input Filter Status Register + AT91_REG Reserved8[1]; // + AT91_REG PIOA_SODR; // Set Output Data Register + AT91_REG PIOA_CODR; // Clear Output Data Register + AT91_REG PIOA_ODSR; // Output Data Status Register + AT91_REG PIOA_PDSR; // Pin Data Status Register + AT91_REG PIOA_IER; // Interrupt Enable Register + AT91_REG PIOA_IDR; // Interrupt Disable Register + AT91_REG PIOA_IMR; // Interrupt Mask Register + AT91_REG PIOA_ISR; // Interrupt Status Register + AT91_REG PIOA_MDER; // Multi-driver Enable Register + AT91_REG PIOA_MDDR; // Multi-driver Disable Register + AT91_REG PIOA_MDSR; // Multi-driver Status Register + AT91_REG Reserved9[1]; // + AT91_REG PIOA_PPUDR; // Pull-up Disable Register + AT91_REG PIOA_PPUER; // Pull-up Enable Register + AT91_REG PIOA_PPUSR; // Pull-up Status Register + AT91_REG Reserved10[1]; // + AT91_REG PIOA_ASR; // Select A Register + AT91_REG PIOA_BSR; // Select B Register + AT91_REG PIOA_ABSR; // AB Select Status Register + AT91_REG Reserved11[9]; // + AT91_REG PIOA_OWER; // Output Write Enable Register + AT91_REG PIOA_OWDR; // Output Write Disable Register + AT91_REG PIOA_OWSR; // Output Write Status Register + AT91_REG Reserved12[85]; // + AT91_REG PIOB_PER; // PIO Enable Register + AT91_REG PIOB_PDR; // PIO Disable Register + AT91_REG PIOB_PSR; // PIO Status Register + AT91_REG Reserved13[1]; // + AT91_REG PIOB_OER; // Output Enable Register + AT91_REG PIOB_ODR; // Output Disable Registerr + AT91_REG PIOB_OSR; // Output Status Register + AT91_REG Reserved14[1]; // + AT91_REG PIOB_IFER; // Input Filter Enable Register + AT91_REG PIOB_IFDR; // Input Filter Disable Register + AT91_REG PIOB_IFSR; // Input Filter Status Register + AT91_REG Reserved15[1]; // + AT91_REG PIOB_SODR; // Set Output Data Register + AT91_REG PIOB_CODR; // Clear Output Data Register + AT91_REG PIOB_ODSR; // Output Data Status Register + AT91_REG PIOB_PDSR; // Pin Data Status Register + AT91_REG PIOB_IER; // Interrupt Enable Register + AT91_REG PIOB_IDR; // Interrupt Disable Register + AT91_REG PIOB_IMR; // Interrupt Mask Register + AT91_REG PIOB_ISR; // Interrupt Status Register + AT91_REG PIOB_MDER; // Multi-driver Enable Register + AT91_REG PIOB_MDDR; // Multi-driver Disable Register + AT91_REG PIOB_MDSR; // Multi-driver Status Register + AT91_REG Reserved16[1]; // + AT91_REG PIOB_PPUDR; // Pull-up Disable Register + AT91_REG PIOB_PPUER; // Pull-up Enable Register + AT91_REG PIOB_PPUSR; // Pull-up Status Register + AT91_REG Reserved17[1]; // + AT91_REG PIOB_ASR; // Select A Register + AT91_REG PIOB_BSR; // Select B Register + AT91_REG PIOB_ABSR; // AB Select Status Register + AT91_REG Reserved18[9]; // + AT91_REG PIOB_OWER; // Output Write Enable Register + AT91_REG PIOB_OWDR; // Output Write Disable Register + AT91_REG PIOB_OWSR; // Output Write Status Register + AT91_REG Reserved19[341]; // + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved20[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved21[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved22[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved23[3]; // + AT91_REG PMC_PCKR[4]; // Programmable Clock Register + AT91_REG Reserved24[4]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register + AT91_REG Reserved25[36]; // + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register + AT91_REG Reserved26[5]; // + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register + AT91_REG Reserved27[5]; // + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_SYS, *AT91PS_SYS; + + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +typedef struct _AT91S_AIC { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register +} AT91S_AIC, *AT91PS_AIC; + +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// ***************************************************************************** +typedef struct _AT91S_PDC { + AT91_REG PDC_RPR; // Receive Pointer Register + AT91_REG PDC_RCR; // Receive Counter Register + AT91_REG PDC_TPR; // Transmit Pointer Register + AT91_REG PDC_TCR; // Transmit Counter Register + AT91_REG PDC_RNPR; // Receive Next Pointer Register + AT91_REG PDC_RNCR; // Receive Next Counter Register + AT91_REG PDC_TNPR; // Transmit Next Pointer Register + AT91_REG PDC_TNCR; // Transmit Next Counter Register + AT91_REG PDC_PTCR; // PDC Transfer Control Register + AT91_REG PDC_PTSR; // PDC Transfer Status Register +} AT91S_PDC, *AT91PS_PDC; + +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +typedef struct _AT91S_DBGU { + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved0[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved1[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register +} AT91S_DBGU, *AT91PS_DBGU; + +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable +#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +typedef struct _AT91S_PIO { + AT91_REG PIO_PER; // PIO Enable Register + AT91_REG PIO_PDR; // PIO Disable Register + AT91_REG PIO_PSR; // PIO Status Register + AT91_REG Reserved0[1]; // + AT91_REG PIO_OER; // Output Enable Register + AT91_REG PIO_ODR; // Output Disable Registerr + AT91_REG PIO_OSR; // Output Status Register + AT91_REG Reserved1[1]; // + AT91_REG PIO_IFER; // Input Filter Enable Register + AT91_REG PIO_IFDR; // Input Filter Disable Register + AT91_REG PIO_IFSR; // Input Filter Status Register + AT91_REG Reserved2[1]; // + AT91_REG PIO_SODR; // Set Output Data Register + AT91_REG PIO_CODR; // Clear Output Data Register + AT91_REG PIO_ODSR; // Output Data Status Register + AT91_REG PIO_PDSR; // Pin Data Status Register + AT91_REG PIO_IER; // Interrupt Enable Register + AT91_REG PIO_IDR; // Interrupt Disable Register + AT91_REG PIO_IMR; // Interrupt Mask Register + AT91_REG PIO_ISR; // Interrupt Status Register + AT91_REG PIO_MDER; // Multi-driver Enable Register + AT91_REG PIO_MDDR; // Multi-driver Disable Register + AT91_REG PIO_MDSR; // Multi-driver Status Register + AT91_REG Reserved3[1]; // + AT91_REG PIO_PPUDR; // Pull-up Disable Register + AT91_REG PIO_PPUER; // Pull-up Enable Register + AT91_REG PIO_PPUSR; // Pull-up Status Register + AT91_REG Reserved4[1]; // + AT91_REG PIO_ASR; // Select A Register + AT91_REG PIO_BSR; // Select B Register + AT91_REG PIO_ABSR; // AB Select Status Register + AT91_REG Reserved5[9]; // + AT91_REG PIO_OWER; // Output Write Enable Register + AT91_REG PIO_OWDR; // Output Write Disable Register + AT91_REG PIO_OWSR; // Output Write Status Register +} AT91S_PIO, *AT91PS_PIO; + + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +typedef struct _AT91S_CKGR { + AT91_REG CKGR_MOR; // Main Oscillator Register + AT91_REG CKGR_MCFR; // Main Clock Frequency Register + AT91_REG Reserved0[1]; // + AT91_REG CKGR_PLLR; // PLL Register +} AT91S_CKGR, *AT91PS_CKGR; + +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +typedef struct _AT91S_PMC { + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved0[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved1[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved2[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved3[3]; // + AT91_REG PMC_PCKR[4]; // Programmable Clock Register + AT91_REG Reserved4[4]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register +} AT91S_PMC, *AT91PS_PMC; + +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +typedef struct _AT91S_RSTC { + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register +} AT91S_RSTC, *AT91PS_RSTC; + +// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset +#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset +#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password +// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status +#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status +#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type +#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured. +#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level +#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable +#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_RTTC { + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register +} AT91S_RTTC, *AT91PS_RTTC; + +// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value +// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value +// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_PITC { + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register +} AT91S_PITC, *AT91PS_PITC; + +// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_WDTC { + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register +} AT91S_WDTC, *AT91PS_WDTC; + +// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart +#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password +// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface +// ***************************************************************************** +typedef struct _AT91S_VREG { + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_VREG, *AT91PS_VREG; + +// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- +#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +typedef struct _AT91S_MC { + AT91_REG MC_RCR; // MC Remap Control Register + AT91_REG MC_ASR; // MC Abort Status Register + AT91_REG MC_AASR; // MC Abort Address Status Register + AT91_REG Reserved0[21]; // + AT91_REG MC_FMR; // MC Flash Mode Register + AT91_REG MC_FCR; // MC Flash Command Register + AT91_REG MC_FSR; // MC Flash Status Register +} AT91S_MC, *AT91PS_MC; + +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready +#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error +#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error +#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming +#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State +#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number +// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command +#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit. +#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number +#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key +// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- +#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status +#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +typedef struct _AT91S_SPI { + AT91_REG SPI_CR; // Control Register + AT91_REG SPI_MR; // Mode Register + AT91_REG SPI_RDR; // Receive Data Register + AT91_REG SPI_TDR; // Transmit Data Register + AT91_REG SPI_SR; // Status Register + AT91_REG SPI_IER; // Interrupt Enable Register + AT91_REG SPI_IDR; // Interrupt Disable Register + AT91_REG SPI_IMR; // Interrupt Mask Register + AT91_REG Reserved0[4]; // + AT91_REG SPI_CSR[4]; // Chip Select Register + AT91_REG Reserved1[48]; // + AT91_REG SPI_RPR; // Receive Pointer Register + AT91_REG SPI_RCR; // Receive Counter Register + AT91_REG SPI_TPR; // Transmit Pointer Register + AT91_REG SPI_TCR; // Transmit Counter Register + AT91_REG SPI_RNPR; // Receive Next Pointer Register + AT91_REG SPI_RNCR; // Receive Next Counter Register + AT91_REG SPI_TNPR; // Transmit Next Pointer Register + AT91_REG SPI_TNCR; // Transmit Next Counter Register + AT91_REG SPI_PTCR; // PDC Transfer Control Register + AT91_REG SPI_PTSR; // PDC Transfer Status Register +} AT91S_SPI, *AT91PS_SPI; + +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK +#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +typedef struct _AT91S_USART { + AT91_REG US_CR; // Control Register + AT91_REG US_MR; // Mode Register + AT91_REG US_IER; // Interrupt Enable Register + AT91_REG US_IDR; // Interrupt Disable Register + AT91_REG US_IMR; // Interrupt Mask Register + AT91_REG US_CSR; // Channel Status Register + AT91_REG US_RHR; // Receiver Holding Register + AT91_REG US_THR; // Transmitter Holding Register + AT91_REG US_BRGR; // Baud Rate Generator Register + AT91_REG US_RTOR; // Receiver Time-out Register + AT91_REG US_TTGR; // Transmitter Time-guard Register + AT91_REG Reserved0[5]; // + AT91_REG US_FIDI; // FI_DI_Ratio Register + AT91_REG US_NER; // Nb Errors Register + AT91_REG Reserved1[1]; // + AT91_REG US_IF; // IRDA_FILTER Register + AT91_REG Reserved2[44]; // + AT91_REG US_RPR; // Receive Pointer Register + AT91_REG US_RCR; // Receive Counter Register + AT91_REG US_TPR; // Transmit Pointer Register + AT91_REG US_TCR; // Transmit Counter Register + AT91_REG US_RNPR; // Receive Next Pointer Register + AT91_REG US_RNCR; // Receive Next Counter Register + AT91_REG US_TNPR; // Transmit Next Pointer Register + AT91_REG US_TNCR; // Transmit Next Counter Register + AT91_REG US_PTCR; // PDC Transfer Control Register + AT91_REG US_PTSR; // PDC Transfer Status Register +} AT91S_USART, *AT91PS_USART; + +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +typedef struct _AT91S_SSC { + AT91_REG SSC_CR; // Control Register + AT91_REG SSC_CMR; // Clock Mode Register + AT91_REG Reserved0[2]; // + AT91_REG SSC_RCMR; // Receive Clock ModeRegister + AT91_REG SSC_RFMR; // Receive Frame Mode Register + AT91_REG SSC_TCMR; // Transmit Clock Mode Register + AT91_REG SSC_TFMR; // Transmit Frame Mode Register + AT91_REG SSC_RHR; // Receive Holding Register + AT91_REG SSC_THR; // Transmit Holding Register + AT91_REG Reserved1[2]; // + AT91_REG SSC_RSHR; // Receive Sync Holding Register + AT91_REG SSC_TSHR; // Transmit Sync Holding Register + AT91_REG Reserved2[2]; // + AT91_REG SSC_SR; // Status Register + AT91_REG SSC_IER; // Interrupt Enable Register + AT91_REG SSC_IDR; // Interrupt Disable Register + AT91_REG SSC_IMR; // Interrupt Mask Register + AT91_REG Reserved3[44]; // + AT91_REG SSC_RPR; // Receive Pointer Register + AT91_REG SSC_RCR; // Receive Counter Register + AT91_REG SSC_TPR; // Transmit Pointer Register + AT91_REG SSC_TCR; // Transmit Counter Register + AT91_REG SSC_RNPR; // Receive Next Pointer Register + AT91_REG SSC_RNCR; // Receive Next Counter Register + AT91_REG SSC_TNPR; // Transmit Next Pointer Register + AT91_REG SSC_TNCR; // Transmit Next Counter Register + AT91_REG SSC_PTCR; // PDC Transfer Control Register + AT91_REG SSC_PTSR; // PDC Transfer Status Register +} AT91S_SSC, *AT91PS_SSC; + +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin +#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +typedef struct _AT91S_TWI { + AT91_REG TWI_CR; // Control Register + AT91_REG TWI_MMR; // Master Mode Register + AT91_REG Reserved0[1]; // + AT91_REG TWI_IADR; // Internal Address Register + AT91_REG TWI_CWGR; // Clock Waveform Generator Register + AT91_REG Reserved1[3]; // + AT91_REG TWI_SR; // Status Register + AT91_REG TWI_IER; // Interrupt Enable Register + AT91_REG TWI_IDR; // Interrupt Disable Register + AT91_REG TWI_IMR; // Interrupt Mask Register + AT91_REG TWI_RHR; // Receive Holding Register + AT91_REG TWI_THR; // Transmit Holding Register +} AT91S_TWI, *AT91PS_TWI; + +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +typedef struct _AT91S_PWMC_CH { + AT91_REG PWMC_CMR; // Channel Mode Register + AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register + AT91_REG PWMC_CPRDR; // Channel Period Register + AT91_REG PWMC_CCNTR; // Channel Counter Register + AT91_REG PWMC_CUPDR; // Channel Update Register + AT91_REG PWMC_Reserved[3]; // Reserved +} AT91S_PWMC_CH, *AT91PS_PWMC_CH; + +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +typedef struct _AT91S_PWMC { + AT91_REG PWMC_MR; // PWMC Mode Register + AT91_REG PWMC_ENA; // PWMC Enable Register + AT91_REG PWMC_DIS; // PWMC Disable Register + AT91_REG PWMC_SR; // PWMC Status Register + AT91_REG PWMC_IER; // PWMC Interrupt Enable Register + AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register + AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register + AT91_REG PWMC_ISR; // PWMC Interrupt Status Register + AT91_REG Reserved0[55]; // + AT91_REG PWMC_VR; // PWMC Version Register + AT91_REG Reserved1[64]; // + AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel +} AT91S_PWMC, *AT91PS_PWMC; + +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +typedef struct _AT91S_UDP { + AT91_REG UDP_NUM; // Frame Number Register + AT91_REG UDP_GLBSTATE; // Global State Register + AT91_REG UDP_FADDR; // Function Address Register + AT91_REG Reserved0[1]; // + AT91_REG UDP_IER; // Interrupt Enable Register + AT91_REG UDP_IDR; // Interrupt Disable Register + AT91_REG UDP_IMR; // Interrupt Mask Register + AT91_REG UDP_ISR; // Interrupt Status Register + AT91_REG UDP_ICR; // Interrupt Clear Register + AT91_REG Reserved1[1]; // + AT91_REG UDP_RSTEP; // Reset Endpoint Register + AT91_REG Reserved2[1]; // + AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register + AT91_REG Reserved3[2]; // + AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register + AT91_REG Reserved4[3]; // + AT91_REG UDP_TXVC; // Transceiver Control Register +} AT91S_UDP, *AT91PS_UDP; + +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured +#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume +#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt +#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt +#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3 +#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4 +#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO +// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP) +#define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +typedef struct _AT91S_TC { + AT91_REG TC_CCR; // Channel Control Register + AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) + AT91_REG Reserved0[2]; // + AT91_REG TC_CV; // Counter Value + AT91_REG TC_RA; // Register A + AT91_REG TC_RB; // Register B + AT91_REG TC_RC; // Register C + AT91_REG TC_SR; // Status Register + AT91_REG TC_IER; // Interrupt Enable Register + AT91_REG TC_IDR; // Interrupt Disable Register + AT91_REG TC_IMR; // Interrupt Mask Register +} AT91S_TC, *AT91PS_TC; + +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) +#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger +#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +typedef struct _AT91S_TCB { + AT91S_TC TCB_TC0; // TC Channel 0 + AT91_REG Reserved0[4]; // + AT91S_TC TCB_TC1; // TC Channel 1 + AT91_REG Reserved1[4]; // + AT91S_TC TCB_TC2; // TC Channel 2 + AT91_REG Reserved2[4]; // + AT91_REG TCB_BCR; // TC Block Control Register + AT91_REG TCB_BMR; // TC Block Mode Register +} AT91S_TCB, *AT91PS_TCB; + +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface +// ***************************************************************************** +typedef struct _AT91S_CAN_MB { + AT91_REG CAN_MB_MMR; // MailBox Mode Register + AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register + AT91_REG CAN_MB_MID; // MailBox ID Register + AT91_REG CAN_MB_MFID; // MailBox Family ID Register + AT91_REG CAN_MB_MSR; // MailBox Status Register + AT91_REG CAN_MB_MDL; // MailBox Data Low Register + AT91_REG CAN_MB_MDH; // MailBox Data High Register + AT91_REG CAN_MB_MCR; // MailBox Control Register +} AT91S_CAN_MB, *AT91PS_CAN_MB; + +// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- +#define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark +#define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority +#define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type +#define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB) +// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- +#define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode +#define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode +#define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version +// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- +// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- +// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- +#define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value +#define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code +#define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request +#define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort +#define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready +#define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored +// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- +// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- +// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- +#define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox +#define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network Interface +// ***************************************************************************** +typedef struct _AT91S_CAN { + AT91_REG CAN_MR; // Mode Register + AT91_REG CAN_IER; // Interrupt Enable Register + AT91_REG CAN_IDR; // Interrupt Disable Register + AT91_REG CAN_IMR; // Interrupt Mask Register + AT91_REG CAN_SR; // Status Register + AT91_REG CAN_BR; // Baudrate Register + AT91_REG CAN_TIM; // Timer Register + AT91_REG CAN_TIMESTP; // Time Stamp Register + AT91_REG CAN_ECR; // Error Counter Register + AT91_REG CAN_TCR; // Transfer Command Register + AT91_REG CAN_ACR; // Abort Command Register + AT91_REG Reserved0[52]; // + AT91_REG CAN_VR; // Version Register + AT91_REG Reserved1[64]; // + AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0 + AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1 + AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2 + AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3 + AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4 + AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5 + AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6 + AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7 + AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8 + AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9 + AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10 + AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11 + AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12 + AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13 + AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14 + AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15 +} AT91S_CAN, *AT91PS_CAN; + +// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- +#define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable +#define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode +#define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode +#define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame +#define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame +#define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode +#define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze +#define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat +// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- +#define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag +#define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag +#define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag +#define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag +#define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag +#define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag +#define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag +#define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag +#define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag +#define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag +#define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag +#define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag +#define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag +#define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag +#define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag +#define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag +#define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag +#define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag +#define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag +#define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag +#define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag +#define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag +#define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag +#define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag +#define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error +#define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error +#define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error +#define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error +#define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error +// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- +// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- +// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- +#define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy +#define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy +#define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy +// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- +#define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment +#define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment +#define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment +#define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment +#define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler +#define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode +// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- +#define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field +// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- +// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- +#define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter +#define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter +// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- +#define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field +// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 +// ***************************************************************************** +typedef struct _AT91S_EMAC { + AT91_REG EMAC_NCR; // Network Control Register + AT91_REG EMAC_NCFGR; // Network Configuration Register + AT91_REG EMAC_NSR; // Network Status Register + AT91_REG Reserved0[2]; // + AT91_REG EMAC_TSR; // Transmit Status Register + AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer + AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer + AT91_REG EMAC_RSR; // Receive Status Register + AT91_REG EMAC_ISR; // Interrupt Status Register + AT91_REG EMAC_IER; // Interrupt Enable Register + AT91_REG EMAC_IDR; // Interrupt Disable Register + AT91_REG EMAC_IMR; // Interrupt Mask Register + AT91_REG EMAC_MAN; // PHY Maintenance Register + AT91_REG EMAC_PTR; // Pause Time Register + AT91_REG EMAC_PFR; // Pause Frames received Register + AT91_REG EMAC_FTO; // Frames Transmitted OK Register + AT91_REG EMAC_SCF; // Single Collision Frame Register + AT91_REG EMAC_MCF; // Multiple Collision Frame Register + AT91_REG EMAC_FRO; // Frames Received OK Register + AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register + AT91_REG EMAC_ALE; // Alignment Error Register + AT91_REG EMAC_DTF; // Deferred Transmission Frame Register + AT91_REG EMAC_LCOL; // Late Collision Register + AT91_REG EMAC_ECOL; // Excessive Collision Register + AT91_REG EMAC_TUND; // Transmit Underrun Error Register + AT91_REG EMAC_CSE; // Carrier Sense Error Register + AT91_REG EMAC_RRE; // Receive Ressource Error Register + AT91_REG EMAC_ROV; // Receive Overrun Errors Register + AT91_REG EMAC_RSE; // Receive Symbol Errors Register + AT91_REG EMAC_ELE; // Excessive Length Errors Register + AT91_REG EMAC_RJA; // Receive Jabbers Register + AT91_REG EMAC_USF; // Undersize Frames Register + AT91_REG EMAC_STE; // SQE Test Error Register + AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register + AT91_REG EMAC_TPF; // Transmitted Pause Frames Register + AT91_REG EMAC_HRB; // Hash Address Bottom[31:0] + AT91_REG EMAC_HRT; // Hash Address Top[63:32] + AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes + AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes + AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes + AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes + AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes + AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes + AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes + AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes + AT91_REG EMAC_TID; // Type ID Checking Register + AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register + AT91_REG EMAC_USRIO; // USER Input/Output Register + AT91_REG EMAC_WOL; // Wake On LAN Register + AT91_REG Reserved1[13]; // + AT91_REG EMAC_REV; // Revision Register +} AT91S_EMAC, *AT91PS_EMAC; + +// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- +#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. +#define AT91C_EMAC_LLB ((unsigned int) 0x1 << 1) // (EMAC) Loopback local. +#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable. +#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable. +#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable. +#define AT91C_EMAC_CLRSTAT ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers. +#define AT91C_EMAC_INCSTAT ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers. +#define AT91C_EMAC_WESTAT ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers. +#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure. +#define AT91C_EMAC_TSTART ((unsigned int) 0x1 << 9) // (EMAC) Start Transmission. +#define AT91C_EMAC_THALT ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. +#define AT91C_EMAC_TPFR ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame +#define AT91C_EMAC_TZQ ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame +// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- +#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed. +#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex. +#define AT91C_EMAC_JFRAME ((unsigned int) 0x1 << 3) // (EMAC) Jumbo Frames. +#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames. +#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast. +#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash event enable +#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable. +#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes. +#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable. +#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC) +#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8 +#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16 +#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32 +#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64 +#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC) +#define AT91C_EMAC_PAE ((unsigned int) 0x1 << 13) // (EMAC) +#define AT91C_EMAC_RBOF ((unsigned int) 0x3 << 14) // (EMAC) +#define AT91C_EMAC_RBOF_OFFSET_0 ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_1 ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_2 ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_3 ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer +#define AT91C_EMAC_RLCE ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable +#define AT91C_EMAC_DRFCS ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS +#define AT91C_EMAC_EFRHD ((unsigned int) 0x1 << 18) // (EMAC) +#define AT91C_EMAC_IRXFCS ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS +// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- +#define AT91C_EMAC_LINKR ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC) +// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- +#define AT91C_EMAC_UBR ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_RLES ((unsigned int) 0x1 << 2) // (EMAC) +#define AT91C_EMAC_TGO ((unsigned int) 0x1 << 3) // (EMAC) Transmit Go +#define AT91C_EMAC_BEX ((unsigned int) 0x1 << 4) // (EMAC) Buffers exhausted mid frame +#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC) +#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC) +// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- +#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 2) // (EMAC) +// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- +#define AT91C_EMAC_MFD ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_RCOMP ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_RXUBR ((unsigned int) 0x1 << 2) // (EMAC) +#define AT91C_EMAC_TXUBR ((unsigned int) 0x1 << 3) // (EMAC) +#define AT91C_EMAC_TUNDR ((unsigned int) 0x1 << 4) // (EMAC) +#define AT91C_EMAC_RLEX ((unsigned int) 0x1 << 5) // (EMAC) +#define AT91C_EMAC_TXERR ((unsigned int) 0x1 << 6) // (EMAC) +#define AT91C_EMAC_TCOMP ((unsigned int) 0x1 << 7) // (EMAC) +#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC) +#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC) +#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC) +#define AT91C_EMAC_PFRE ((unsigned int) 0x1 << 12) // (EMAC) +#define AT91C_EMAC_PTZ ((unsigned int) 0x1 << 13) // (EMAC) +// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- +// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- +// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- +// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- +#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC) +#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC) +#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC) +#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC) +#define AT91C_EMAC_SOF ((unsigned int) 0x3 << 30) // (EMAC) +// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- +#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 0) // (EMAC) Reduce MII +// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- +#define AT91C_EMAC_IP ((unsigned int) 0xFFFF << 0) // (EMAC) ARP request IP address +#define AT91C_EMAC_MAG ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable +#define AT91C_EMAC_ARP ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable +#define AT91C_EMAC_SA1 ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable +// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- +#define AT91C_EMAC_REVREF ((unsigned int) 0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_PARTREF ((unsigned int) 0xFFFF << 16) // (EMAC) + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +typedef struct _AT91S_ADC { + AT91_REG ADC_CR; // ADC Control Register + AT91_REG ADC_MR; // ADC Mode Register + AT91_REG Reserved0[2]; // + AT91_REG ADC_CHER; // ADC Channel Enable Register + AT91_REG ADC_CHDR; // ADC Channel Disable Register + AT91_REG ADC_CHSR; // ADC Channel Status Register + AT91_REG ADC_SR; // ADC Status Register + AT91_REG ADC_LCDR; // ADC Last Converted Data Register + AT91_REG ADC_IER; // ADC Interrupt Enable Register + AT91_REG ADC_IDR; // ADC Interrupt Disable Register + AT91_REG ADC_IMR; // ADC Interrupt Mask Register + AT91_REG ADC_CDR0; // ADC Channel Data Register 0 + AT91_REG ADC_CDR1; // ADC Channel Data Register 1 + AT91_REG ADC_CDR2; // ADC Channel Data Register 2 + AT91_REG ADC_CDR3; // ADC Channel Data Register 3 + AT91_REG ADC_CDR4; // ADC Channel Data Register 4 + AT91_REG ADC_CDR5; // ADC Channel Data Register 5 + AT91_REG ADC_CDR6; // ADC Channel Data Register 6 + AT91_REG ADC_CDR7; // ADC Channel Data Register 7 + AT91_REG Reserved1[44]; // + AT91_REG ADC_RPR; // Receive Pointer Register + AT91_REG ADC_RCR; // Receive Counter Register + AT91_REG ADC_TPR; // Transmit Pointer Register + AT91_REG ADC_TCR; // Transmit Counter Register + AT91_REG ADC_RNPR; // Receive Next Pointer Register + AT91_REG ADC_RNCR; // Receive Next Counter Register + AT91_REG ADC_TNPR; // Transmit Next Pointer Register + AT91_REG ADC_TNCR; // Transmit Next Counter Register + AT91_REG ADC_PTCR; // PDC Transfer Control Register + AT91_REG ADC_PTSR; // PDC Transfer Status Register +} AT91S_ADC, *AT91PS_ADC; + +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Encryption Standard +// ***************************************************************************** +typedef struct _AT91S_AES { + AT91_REG AES_CR; // Control Register + AT91_REG AES_MR; // Mode Register + AT91_REG Reserved0[2]; // + AT91_REG AES_IER; // Interrupt Enable Register + AT91_REG AES_IDR; // Interrupt Disable Register + AT91_REG AES_IMR; // Interrupt Mask Register + AT91_REG AES_ISR; // Interrupt Status Register + AT91_REG AES_KEYWxR[4]; // Key Word x Register + AT91_REG Reserved1[4]; // + AT91_REG AES_IDATAxR[4]; // Input Data x Register + AT91_REG AES_ODATAxR[4]; // Output Data x Register + AT91_REG AES_IVxR[4]; // Initialization Vector x Register + AT91_REG Reserved2[35]; // + AT91_REG AES_VR; // AES Version Register + AT91_REG AES_RPR; // Receive Pointer Register + AT91_REG AES_RCR; // Receive Counter Register + AT91_REG AES_TPR; // Transmit Pointer Register + AT91_REG AES_TCR; // Transmit Counter Register + AT91_REG AES_RNPR; // Receive Next Pointer Register + AT91_REG AES_RNCR; // Receive Next Counter Register + AT91_REG AES_TNPR; // Transmit Next Pointer Register + AT91_REG AES_TNCR; // Transmit Next Counter Register + AT91_REG AES_PTCR; // PDC Transfer Control Register + AT91_REG AES_PTSR; // PDC Transfer Status Register +} AT91S_AES, *AT91PS_AES; + +// -------- AES_CR : (AES Offset: 0x0) Control Register -------- +#define AT91C_AES_START ((unsigned int) 0x1 << 0) // (AES) Starts Processing +#define AT91C_AES_SWRST ((unsigned int) 0x1 << 8) // (AES) Software Reset +#define AT91C_AES_LOADSEED ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading +// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- +#define AT91C_AES_CIPHER ((unsigned int) 0x1 << 0) // (AES) Processing Mode +#define AT91C_AES_PROCDLY ((unsigned int) 0xF << 4) // (AES) Processing Delay +#define AT91C_AES_SMOD ((unsigned int) 0x3 << 8) // (AES) Start Mode +#define AT91C_AES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. +#define AT91C_AES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). +#define AT91C_AES_SMOD_PDC ((unsigned int) 0x2 << 8) // (AES) PDC Mode (cf datasheet). +#define AT91C_AES_OPMOD ((unsigned int) 0x7 << 12) // (AES) Operation Mode +#define AT91C_AES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode. +#define AT91C_AES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode. +#define AT91C_AES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode. +#define AT91C_AES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode. +#define AT91C_AES_OPMOD_CTR ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode. +#define AT91C_AES_LOD ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode +#define AT91C_AES_CFBS ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size +#define AT91C_AES_CFBS_128_BIT ((unsigned int) 0x0 << 16) // (AES) 128-bit. +#define AT91C_AES_CFBS_64_BIT ((unsigned int) 0x1 << 16) // (AES) 64-bit. +#define AT91C_AES_CFBS_32_BIT ((unsigned int) 0x2 << 16) // (AES) 32-bit. +#define AT91C_AES_CFBS_16_BIT ((unsigned int) 0x3 << 16) // (AES) 16-bit. +#define AT91C_AES_CFBS_8_BIT ((unsigned int) 0x4 << 16) // (AES) 8-bit. +#define AT91C_AES_CKEY ((unsigned int) 0xF << 20) // (AES) Countermeasure Key +#define AT91C_AES_CTYPE ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type +#define AT91C_AES_CTYPE_TYPE1_EN ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled. +#define AT91C_AES_CTYPE_TYPE2_EN ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled. +#define AT91C_AES_CTYPE_TYPE3_EN ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled. +#define AT91C_AES_CTYPE_TYPE4_EN ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled. +#define AT91C_AES_CTYPE_TYPE5_EN ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled. +// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- +#define AT91C_AES_DATRDY ((unsigned int) 0x1 << 0) // (AES) DATRDY +#define AT91C_AES_ENDRX ((unsigned int) 0x1 << 1) // (AES) PDC Read Buffer End +#define AT91C_AES_ENDTX ((unsigned int) 0x1 << 2) // (AES) PDC Write Buffer End +#define AT91C_AES_RXBUFF ((unsigned int) 0x1 << 3) // (AES) PDC Read Buffer Full +#define AT91C_AES_TXBUFE ((unsigned int) 0x1 << 4) // (AES) PDC Write Buffer Empty +#define AT91C_AES_URAD ((unsigned int) 0x1 << 8) // (AES) Unspecified Register Access Detection +// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- +// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- +// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- +#define AT91C_AES_URAT ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status +#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode. +#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing. +#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing. +#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation. +#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation. +#define AT91C_AES_URAT_WO_REG_READ ((unsigned int) 0x5 << 12) // (AES) Write-only register read access. + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard +// ***************************************************************************** +typedef struct _AT91S_TDES { + AT91_REG TDES_CR; // Control Register + AT91_REG TDES_MR; // Mode Register + AT91_REG Reserved0[2]; // + AT91_REG TDES_IER; // Interrupt Enable Register + AT91_REG TDES_IDR; // Interrupt Disable Register + AT91_REG TDES_IMR; // Interrupt Mask Register + AT91_REG TDES_ISR; // Interrupt Status Register + AT91_REG TDES_KEY1WxR[2]; // Key 1 Word x Register + AT91_REG TDES_KEY2WxR[2]; // Key 2 Word x Register + AT91_REG TDES_KEY3WxR[2]; // Key 3 Word x Register + AT91_REG Reserved1[2]; // + AT91_REG TDES_IDATAxR[2]; // Input Data x Register + AT91_REG Reserved2[2]; // + AT91_REG TDES_ODATAxR[2]; // Output Data x Register + AT91_REG Reserved3[2]; // + AT91_REG TDES_IVxR[2]; // Initialization Vector x Register + AT91_REG Reserved4[37]; // + AT91_REG TDES_VR; // TDES Version Register + AT91_REG TDES_RPR; // Receive Pointer Register + AT91_REG TDES_RCR; // Receive Counter Register + AT91_REG TDES_TPR; // Transmit Pointer Register + AT91_REG TDES_TCR; // Transmit Counter Register + AT91_REG TDES_RNPR; // Receive Next Pointer Register + AT91_REG TDES_RNCR; // Receive Next Counter Register + AT91_REG TDES_TNPR; // Transmit Next Pointer Register + AT91_REG TDES_TNCR; // Transmit Next Counter Register + AT91_REG TDES_PTCR; // PDC Transfer Control Register + AT91_REG TDES_PTSR; // PDC Transfer Status Register +} AT91S_TDES, *AT91PS_TDES; + +// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- +#define AT91C_TDES_START ((unsigned int) 0x1 << 0) // (TDES) Starts Processing +#define AT91C_TDES_SWRST ((unsigned int) 0x1 << 8) // (TDES) Software Reset +// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- +#define AT91C_TDES_CIPHER ((unsigned int) 0x1 << 0) // (TDES) Processing Mode +#define AT91C_TDES_TDESMOD ((unsigned int) 0x1 << 1) // (TDES) Single or Triple DES Mode +#define AT91C_TDES_KEYMOD ((unsigned int) 0x1 << 4) // (TDES) Key Mode +#define AT91C_TDES_SMOD ((unsigned int) 0x3 << 8) // (TDES) Start Mode +#define AT91C_TDES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. +#define AT91C_TDES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). +#define AT91C_TDES_SMOD_PDC ((unsigned int) 0x2 << 8) // (TDES) PDC Mode (cf datasheet). +#define AT91C_TDES_OPMOD ((unsigned int) 0x3 << 12) // (TDES) Operation Mode +#define AT91C_TDES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode. +#define AT91C_TDES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode. +#define AT91C_TDES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode. +#define AT91C_TDES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode. +#define AT91C_TDES_LOD ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode +#define AT91C_TDES_CFBS ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size +#define AT91C_TDES_CFBS_64_BIT ((unsigned int) 0x0 << 16) // (TDES) 64-bit. +#define AT91C_TDES_CFBS_32_BIT ((unsigned int) 0x1 << 16) // (TDES) 32-bit. +#define AT91C_TDES_CFBS_16_BIT ((unsigned int) 0x2 << 16) // (TDES) 16-bit. +#define AT91C_TDES_CFBS_8_BIT ((unsigned int) 0x3 << 16) // (TDES) 8-bit. +// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- +#define AT91C_TDES_DATRDY ((unsigned int) 0x1 << 0) // (TDES) DATRDY +#define AT91C_TDES_ENDRX ((unsigned int) 0x1 << 1) // (TDES) PDC Read Buffer End +#define AT91C_TDES_ENDTX ((unsigned int) 0x1 << 2) // (TDES) PDC Write Buffer End +#define AT91C_TDES_RXBUFF ((unsigned int) 0x1 << 3) // (TDES) PDC Read Buffer Full +#define AT91C_TDES_TXBUFE ((unsigned int) 0x1 << 4) // (TDES) PDC Write Buffer Empty +#define AT91C_TDES_URAD ((unsigned int) 0x1 << 8) // (TDES) Unspecified Register Access Detection +// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- +// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- +// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- +#define AT91C_TDES_URAT ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status +#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode. +#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing. +#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing. +#define AT91C_TDES_URAT_WO_REG_READ ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access. + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 +// ***************************************************************************** +// ========== Register definition for SYS peripheral ========== +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register +#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register +#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register +#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register +#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register +// ========== Register definition for PIOB peripheral ========== +#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register +#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register +#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register +#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register +#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register +#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register +#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register +#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register +#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register +#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register +#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register +#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register +#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register +#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register +#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register +#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register +#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr +#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register +#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register +#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register +#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register +#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register +#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register +#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register +#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register +#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register +#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register +#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register +#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register +#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register +#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register +#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register +#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register +#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register +// ========== Register definition for VREG peripheral ========== +#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register +#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register +#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register +#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register +// ========== Register definition for PDC_SPI1 peripheral ========== +#define AT91C_SPI1_PTCR ((AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register +#define AT91C_SPI1_RPR ((AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register +#define AT91C_SPI1_TNCR ((AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register +#define AT91C_SPI1_TPR ((AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register +#define AT91C_SPI1_TNPR ((AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register +#define AT91C_SPI1_TCR ((AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register +#define AT91C_SPI1_RCR ((AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register +#define AT91C_SPI1_RNPR ((AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register +#define AT91C_SPI1_RNCR ((AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register +#define AT91C_SPI1_PTSR ((AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register +// ========== Register definition for SPI1 peripheral ========== +#define AT91C_SPI1_IMR ((AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register +#define AT91C_SPI1_IER ((AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register +#define AT91C_SPI1_MR ((AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register +#define AT91C_SPI1_RDR ((AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register +#define AT91C_SPI1_IDR ((AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register +#define AT91C_SPI1_SR ((AT91_REG *) 0xFFFE4010) // (SPI1) Status Register +#define AT91C_SPI1_TDR ((AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register +#define AT91C_SPI1_CR ((AT91_REG *) 0xFFFE4000) // (SPI1) Control Register +#define AT91C_SPI1_CSR ((AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register +// ========== Register definition for PDC_SPI0 peripheral ========== +#define AT91C_SPI0_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register +#define AT91C_SPI0_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register +#define AT91C_SPI0_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register +#define AT91C_SPI0_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register +#define AT91C_SPI0_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register +#define AT91C_SPI0_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register +#define AT91C_SPI0_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register +#define AT91C_SPI0_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register +#define AT91C_SPI0_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register +#define AT91C_SPI0_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register +// ========== Register definition for SPI0 peripheral ========== +#define AT91C_SPI0_IER ((AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register +#define AT91C_SPI0_SR ((AT91_REG *) 0xFFFE0010) // (SPI0) Status Register +#define AT91C_SPI0_IDR ((AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register +#define AT91C_SPI0_CR ((AT91_REG *) 0xFFFE0000) // (SPI0) Control Register +#define AT91C_SPI0_MR ((AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register +#define AT91C_SPI0_IMR ((AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register +#define AT91C_SPI0_TDR ((AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register +#define AT91C_SPI0_RDR ((AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register +#define AT91C_SPI0_CSR ((AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register +#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register +#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register +#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register +#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register +#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register +#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register +#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register +#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register +#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register +#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register +#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register +#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for CAN_MB0 peripheral ========== +#define AT91C_CAN_MB0_MDL ((AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register +#define AT91C_CAN_MB0_MAM ((AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register +#define AT91C_CAN_MB0_MCR ((AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register +#define AT91C_CAN_MB0_MID ((AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register +#define AT91C_CAN_MB0_MSR ((AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register +#define AT91C_CAN_MB0_MFID ((AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register +#define AT91C_CAN_MB0_MDH ((AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register +#define AT91C_CAN_MB0_MMR ((AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register +// ========== Register definition for CAN_MB1 peripheral ========== +#define AT91C_CAN_MB1_MDL ((AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register +#define AT91C_CAN_MB1_MID ((AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register +#define AT91C_CAN_MB1_MMR ((AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register +#define AT91C_CAN_MB1_MSR ((AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register +#define AT91C_CAN_MB1_MAM ((AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register +#define AT91C_CAN_MB1_MDH ((AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register +#define AT91C_CAN_MB1_MCR ((AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register +#define AT91C_CAN_MB1_MFID ((AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register +// ========== Register definition for CAN_MB2 peripheral ========== +#define AT91C_CAN_MB2_MCR ((AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register +#define AT91C_CAN_MB2_MDH ((AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register +#define AT91C_CAN_MB2_MID ((AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register +#define AT91C_CAN_MB2_MDL ((AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register +#define AT91C_CAN_MB2_MMR ((AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register +#define AT91C_CAN_MB2_MAM ((AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register +#define AT91C_CAN_MB2_MFID ((AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register +#define AT91C_CAN_MB2_MSR ((AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register +// ========== Register definition for CAN_MB3 peripheral ========== +#define AT91C_CAN_MB3_MFID ((AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register +#define AT91C_CAN_MB3_MAM ((AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register +#define AT91C_CAN_MB3_MID ((AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register +#define AT91C_CAN_MB3_MCR ((AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register +#define AT91C_CAN_MB3_MMR ((AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register +#define AT91C_CAN_MB3_MSR ((AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register +#define AT91C_CAN_MB3_MDL ((AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register +#define AT91C_CAN_MB3_MDH ((AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register +// ========== Register definition for CAN_MB4 peripheral ========== +#define AT91C_CAN_MB4_MID ((AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register +#define AT91C_CAN_MB4_MMR ((AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register +#define AT91C_CAN_MB4_MDH ((AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register +#define AT91C_CAN_MB4_MFID ((AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register +#define AT91C_CAN_MB4_MSR ((AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register +#define AT91C_CAN_MB4_MCR ((AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register +#define AT91C_CAN_MB4_MDL ((AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register +#define AT91C_CAN_MB4_MAM ((AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB5 peripheral ========== +#define AT91C_CAN_MB5_MSR ((AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register +#define AT91C_CAN_MB5_MCR ((AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register +#define AT91C_CAN_MB5_MFID ((AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register +#define AT91C_CAN_MB5_MDH ((AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register +#define AT91C_CAN_MB5_MID ((AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register +#define AT91C_CAN_MB5_MMR ((AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register +#define AT91C_CAN_MB5_MDL ((AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register +#define AT91C_CAN_MB5_MAM ((AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB6 peripheral ========== +#define AT91C_CAN_MB6_MFID ((AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register +#define AT91C_CAN_MB6_MID ((AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register +#define AT91C_CAN_MB6_MAM ((AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register +#define AT91C_CAN_MB6_MSR ((AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register +#define AT91C_CAN_MB6_MDL ((AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register +#define AT91C_CAN_MB6_MCR ((AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register +#define AT91C_CAN_MB6_MDH ((AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register +#define AT91C_CAN_MB6_MMR ((AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register +// ========== Register definition for CAN_MB7 peripheral ========== +#define AT91C_CAN_MB7_MCR ((AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register +#define AT91C_CAN_MB7_MDH ((AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register +#define AT91C_CAN_MB7_MFID ((AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register +#define AT91C_CAN_MB7_MDL ((AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register +#define AT91C_CAN_MB7_MID ((AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register +#define AT91C_CAN_MB7_MMR ((AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register +#define AT91C_CAN_MB7_MAM ((AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register +#define AT91C_CAN_MB7_MSR ((AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register +// ========== Register definition for CAN peripheral ========== +#define AT91C_CAN_TCR ((AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register +#define AT91C_CAN_IMR ((AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register +#define AT91C_CAN_IER ((AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register +#define AT91C_CAN_ECR ((AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register +#define AT91C_CAN_TIMESTP ((AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register +#define AT91C_CAN_MR ((AT91_REG *) 0xFFFD0000) // (CAN) Mode Register +#define AT91C_CAN_IDR ((AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register +#define AT91C_CAN_ACR ((AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register +#define AT91C_CAN_TIM ((AT91_REG *) 0xFFFD0018) // (CAN) Timer Register +#define AT91C_CAN_SR ((AT91_REG *) 0xFFFD0010) // (CAN) Status Register +#define AT91C_CAN_BR ((AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register +#define AT91C_CAN_VR ((AT91_REG *) 0xFFFD00FC) // (CAN) Version Register +// ========== Register definition for EMAC peripheral ========== +#define AT91C_EMAC_ISR ((AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register +#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes +#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes +#define AT91C_EMAC_ELE ((AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register +#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register +#define AT91C_EMAC_RLE ((AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register +#define AT91C_EMAC_WOL ((AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register +#define AT91C_EMAC_DTF ((AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register +#define AT91C_EMAC_TUND ((AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register +#define AT91C_EMAC_NCR ((AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register +#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes +#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register +#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes +#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register +#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register +#define AT91C_EMAC_RSE ((AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register +#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register +#define AT91C_EMAC_TID ((AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register +#define AT91C_EMAC_HRB ((AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] +#define AT91C_EMAC_TBQP ((AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer +#define AT91C_EMAC_USRIO ((AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register +#define AT91C_EMAC_PTR ((AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register +#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes +#define AT91C_EMAC_ROV ((AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register +#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register +#define AT91C_EMAC_RJA ((AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register +#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer +#define AT91C_EMAC_TPF ((AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register +#define AT91C_EMAC_NCFGR ((AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register +#define AT91C_EMAC_HRT ((AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32] +#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register +#define AT91C_EMAC_FCSE ((AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register +#define AT91C_EMAC_TPQ ((AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register +#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register +#define AT91C_EMAC_FTO ((AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register +#define AT91C_EMAC_REV ((AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register +#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register +#define AT91C_EMAC_SCF ((AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register +#define AT91C_EMAC_PFR ((AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register +#define AT91C_EMAC_MCF ((AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register +#define AT91C_EMAC_NSR ((AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register +#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes +#define AT91C_EMAC_FRO ((AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register +#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register +#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes +#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register +#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes +#define AT91C_EMAC_RRE ((AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register +#define AT91C_EMAC_STE ((AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register +#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register +// ========== Register definition for PDC_AES peripheral ========== +#define AT91C_AES_TPR ((AT91_REG *) 0xFFFA4108) // (PDC_AES) Transmit Pointer Register +#define AT91C_AES_PTCR ((AT91_REG *) 0xFFFA4120) // (PDC_AES) PDC Transfer Control Register +#define AT91C_AES_RNPR ((AT91_REG *) 0xFFFA4110) // (PDC_AES) Receive Next Pointer Register +#define AT91C_AES_TNCR ((AT91_REG *) 0xFFFA411C) // (PDC_AES) Transmit Next Counter Register +#define AT91C_AES_TCR ((AT91_REG *) 0xFFFA410C) // (PDC_AES) Transmit Counter Register +#define AT91C_AES_RCR ((AT91_REG *) 0xFFFA4104) // (PDC_AES) Receive Counter Register +#define AT91C_AES_RNCR ((AT91_REG *) 0xFFFA4114) // (PDC_AES) Receive Next Counter Register +#define AT91C_AES_TNPR ((AT91_REG *) 0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register +#define AT91C_AES_RPR ((AT91_REG *) 0xFFFA4100) // (PDC_AES) Receive Pointer Register +#define AT91C_AES_PTSR ((AT91_REG *) 0xFFFA4124) // (PDC_AES) PDC Transfer Status Register +// ========== Register definition for AES peripheral ========== +#define AT91C_AES_IVxR ((AT91_REG *) 0xFFFA4060) // (AES) Initialization Vector x Register +#define AT91C_AES_MR ((AT91_REG *) 0xFFFA4004) // (AES) Mode Register +#define AT91C_AES_VR ((AT91_REG *) 0xFFFA40FC) // (AES) AES Version Register +#define AT91C_AES_ODATAxR ((AT91_REG *) 0xFFFA4050) // (AES) Output Data x Register +#define AT91C_AES_IDATAxR ((AT91_REG *) 0xFFFA4040) // (AES) Input Data x Register +#define AT91C_AES_CR ((AT91_REG *) 0xFFFA4000) // (AES) Control Register +#define AT91C_AES_IDR ((AT91_REG *) 0xFFFA4014) // (AES) Interrupt Disable Register +#define AT91C_AES_IMR ((AT91_REG *) 0xFFFA4018) // (AES) Interrupt Mask Register +#define AT91C_AES_IER ((AT91_REG *) 0xFFFA4010) // (AES) Interrupt Enable Register +#define AT91C_AES_KEYWxR ((AT91_REG *) 0xFFFA4020) // (AES) Key Word x Register +#define AT91C_AES_ISR ((AT91_REG *) 0xFFFA401C) // (AES) Interrupt Status Register +// ========== Register definition for PDC_TDES peripheral ========== +#define AT91C_TDES_RNCR ((AT91_REG *) 0xFFFA8114) // (PDC_TDES) Receive Next Counter Register +#define AT91C_TDES_TCR ((AT91_REG *) 0xFFFA810C) // (PDC_TDES) Transmit Counter Register +#define AT91C_TDES_RCR ((AT91_REG *) 0xFFFA8104) // (PDC_TDES) Receive Counter Register +#define AT91C_TDES_TNPR ((AT91_REG *) 0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register +#define AT91C_TDES_RNPR ((AT91_REG *) 0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register +#define AT91C_TDES_RPR ((AT91_REG *) 0xFFFA8100) // (PDC_TDES) Receive Pointer Register +#define AT91C_TDES_TNCR ((AT91_REG *) 0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register +#define AT91C_TDES_TPR ((AT91_REG *) 0xFFFA8108) // (PDC_TDES) Transmit Pointer Register +#define AT91C_TDES_PTSR ((AT91_REG *) 0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register +#define AT91C_TDES_PTCR ((AT91_REG *) 0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register +// ========== Register definition for TDES peripheral ========== +#define AT91C_TDES_KEY2WxR ((AT91_REG *) 0xFFFA8028) // (TDES) Key 2 Word x Register +#define AT91C_TDES_KEY3WxR ((AT91_REG *) 0xFFFA8030) // (TDES) Key 3 Word x Register +#define AT91C_TDES_IDR ((AT91_REG *) 0xFFFA8014) // (TDES) Interrupt Disable Register +#define AT91C_TDES_VR ((AT91_REG *) 0xFFFA80FC) // (TDES) TDES Version Register +#define AT91C_TDES_IVxR ((AT91_REG *) 0xFFFA8060) // (TDES) Initialization Vector x Register +#define AT91C_TDES_ODATAxR ((AT91_REG *) 0xFFFA8050) // (TDES) Output Data x Register +#define AT91C_TDES_IMR ((AT91_REG *) 0xFFFA8018) // (TDES) Interrupt Mask Register +#define AT91C_TDES_MR ((AT91_REG *) 0xFFFA8004) // (TDES) Mode Register +#define AT91C_TDES_CR ((AT91_REG *) 0xFFFA8000) // (TDES) Control Register +#define AT91C_TDES_IER ((AT91_REG *) 0xFFFA8010) // (TDES) Interrupt Enable Register +#define AT91C_TDES_ISR ((AT91_REG *) 0xFFFA801C) // (TDES) Interrupt Status Register +#define AT91C_TDES_IDATAxR ((AT91_REG *) 0xFFFA8040) // (TDES) Input Data x Register +#define AT91C_TDES_KEY1WxR ((AT91_REG *) 0xFFFA8020) // (TDES) Key 1 Word x Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data +#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data +#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data +#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock +#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_NPCS00 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 +#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_NPCS01 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_NPCS02 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1 +#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_NPCS03 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input +#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_MISO0 ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave +#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_MOSI0 ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave +#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_SPCK0 ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock +#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive +#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PA2_NPCS11 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit +#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync +#define AT91C_PA21_NPCS10 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 +#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock +#define AT91C_PA22_SPCK1 ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock +#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data +#define AT91C_PA23_MOSI1 ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave +#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data +#define AT91C_PA24_MISO1 ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave +#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock +#define AT91C_PA25_NPCS11 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync +#define AT91C_PA26_NPCS12 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data +#define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3 +#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data +#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input +#define AT91C_PA29_NPCS13 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send +#define AT91C_PA3_NPCS12 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0 +#define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send +#define AT91C_PA4_NPCS13 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data +#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data +#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock +#define AT91C_PA7_NPCS01 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send +#define AT91C_PA8_NPCS02 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send +#define AT91C_PA9_NPCS03 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0 +#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock +#define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1 +#define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable +#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10 +#define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 +#define AT91C_PB10_NPCS11 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11 +#define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 +#define AT91C_PB11_NPCS12 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12 +#define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error +#define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input +#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13 +#define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 +#define AT91C_PB13_NPCS01 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14 +#define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 +#define AT91C_PB14_NPCS02 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15 +#define AT91C_PB15_ERXDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid +#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16 +#define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected +#define AT91C_PB16_NPCS13 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17 +#define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock +#define AT91C_PB17_NPCS03 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18 +#define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec +#define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger +#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19 +#define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0 +#define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input +#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2 +#define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 +#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20 +#define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1 +#define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21 +#define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2 +#define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22 +#define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3 +#define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23 +#define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect +#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24 +#define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready +#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25 +#define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready +#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26 +#define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator +#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27 +#define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0 +#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28 +#define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1 +#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29 +#define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1 +#define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2 +#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3 +#define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 +#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30 +#define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2 +#define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3 +#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4 +#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid +#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5 +#define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 +#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6 +#define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 +#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7 +#define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error +#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8 +#define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock +#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9 +#define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral +#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A +#define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B +#define AT91C_ID_SPI0 ((unsigned int) 4) // Serial Peripheral Interface 0 +#define AT91C_ID_SPI1 ((unsigned int) 5) // Serial Peripheral Interface 1 +#define AT91C_ID_US0 ((unsigned int) 6) // USART 0 +#define AT91C_ID_US1 ((unsigned int) 7) // USART 1 +#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface +#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller +#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port +#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0 +#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1 +#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2 +#define AT91C_ID_CAN ((unsigned int) 15) // Control Area Network Controller +#define AT91C_ID_EMAC ((unsigned int) 16) // Ethernet MAC +#define AT91C_ID_ADC ((unsigned int) 17) // Analog-to-Digital Converter +#define AT91C_ID_AES ((unsigned int) 18) // Advanced Encryption Standard 128-bit +#define AT91C_ID_TDES ((unsigned int) 19) // Triple Data Encryption Standard +#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved +#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved +#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved +#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved +#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved +#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved +#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved +#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved +#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved +#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved +#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1) + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address +#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address +#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address +#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address +#define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address +#define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address +#define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address +#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address +#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_CAN_MB0 ((AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address +#define AT91C_BASE_CAN_MB1 ((AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address +#define AT91C_BASE_CAN_MB2 ((AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address +#define AT91C_BASE_CAN_MB3 ((AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address +#define AT91C_BASE_CAN_MB4 ((AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address +#define AT91C_BASE_CAN_MB5 ((AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address +#define AT91C_BASE_CAN_MB6 ((AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address +#define AT91C_BASE_CAN_MB7 ((AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address +#define AT91C_BASE_CAN ((AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address +#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address +#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address +#define AT91C_BASE_PDC_AES ((AT91PS_PDC) 0xFFFA4100) // (PDC_AES) Base Address +#define AT91C_BASE_AES ((AT91PS_AES) 0xFFFA4000) // (AES) Base Address +#define AT91C_BASE_PDC_TDES ((AT91PS_PDC) 0xFFFA8100) // (PDC_TDES) Base Address +#define AT91C_BASE_TDES ((AT91PS_TDES) 0xFFFA8000) // (TDES) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte) +#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address +#define AT91C_IFLASH_SIZE ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte) + +#define AT91F_AIC_ConfigureIt( irq_id, priority, src_type, newHandler ) \ +{ \ + unsigned int mask ; \ + \ + mask = 0x1 << irq_id; \ + /* Disable the interrupt on the interrupt controller */ \ + AT91C_BASE_AIC->AIC_IDCR = mask ; \ + /* Save the interrupt handler routine pointer and the interrupt priority */ \ + AT91C_BASE_AIC->AIC_SVR[irq_id] = (unsigned int) newHandler ; \ + /* Store the Source Mode Register */ \ + AT91C_BASE_AIC->AIC_SMR[irq_id] = src_type | priority ; \ + /* Clear the interrupt on the interrupt controller */ \ + AT91C_BASE_AIC->AIC_ICCR = mask ; \ +} + + +#endif diff --git a/20080212/Source/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h b/20080212/Source/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h new file mode 100644 index 000000000..8ea721e28 --- /dev/null +++ b/20080212/Source/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h @@ -0,0 +1,4698 @@ +// - ---------------------------------------------------------------------------- +// - ATMEL Microcontroller Software Support - ROUSSET - +// - ---------------------------------------------------------------------------- +// - DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +// - IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +// - DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +// - INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// - LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +// - OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// - LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// - NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// - EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// - ---------------------------------------------------------------------------- +// - File Name : AT91SAM7X256.h +// - Object : AT91SAM7X256 definitions +// - Generated : AT91 SW Application Group 05/20/2005 (16:22:29) +// - +// - CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005// +// - CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// +// - CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// +// - CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// +// - CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// +// - CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// +// - CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// +// - CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// +// - CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// +// - CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// +// - CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// +// - CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// +// - CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// +// - CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// +// - CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// +// - CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// +// - CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// +// - CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// +// - CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// +// - CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// +// - CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// +// - CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// +// - CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// +// - CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// +// - CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// +// - ---------------------------------------------------------------------------- + +#ifndef AT91SAM7X256_H +#define AT91SAM7X256_H + +typedef volatile unsigned int AT91_REG;// Hardware register definition + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** +typedef struct _AT91S_SYS { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register + AT91_REG Reserved2[45]; // + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved3[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved4[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register + AT91_REG Reserved5[54]; // + AT91_REG PIOA_PER; // PIO Enable Register + AT91_REG PIOA_PDR; // PIO Disable Register + AT91_REG PIOA_PSR; // PIO Status Register + AT91_REG Reserved6[1]; // + AT91_REG PIOA_OER; // Output Enable Register + AT91_REG PIOA_ODR; // Output Disable Registerr + AT91_REG PIOA_OSR; // Output Status Register + AT91_REG Reserved7[1]; // + AT91_REG PIOA_IFER; // Input Filter Enable Register + AT91_REG PIOA_IFDR; // Input Filter Disable Register + AT91_REG PIOA_IFSR; // Input Filter Status Register + AT91_REG Reserved8[1]; // + AT91_REG PIOA_SODR; // Set Output Data Register + AT91_REG PIOA_CODR; // Clear Output Data Register + AT91_REG PIOA_ODSR; // Output Data Status Register + AT91_REG PIOA_PDSR; // Pin Data Status Register + AT91_REG PIOA_IER; // Interrupt Enable Register + AT91_REG PIOA_IDR; // Interrupt Disable Register + AT91_REG PIOA_IMR; // Interrupt Mask Register + AT91_REG PIOA_ISR; // Interrupt Status Register + AT91_REG PIOA_MDER; // Multi-driver Enable Register + AT91_REG PIOA_MDDR; // Multi-driver Disable Register + AT91_REG PIOA_MDSR; // Multi-driver Status Register + AT91_REG Reserved9[1]; // + AT91_REG PIOA_PPUDR; // Pull-up Disable Register + AT91_REG PIOA_PPUER; // Pull-up Enable Register + AT91_REG PIOA_PPUSR; // Pull-up Status Register + AT91_REG Reserved10[1]; // + AT91_REG PIOA_ASR; // Select A Register + AT91_REG PIOA_BSR; // Select B Register + AT91_REG PIOA_ABSR; // AB Select Status Register + AT91_REG Reserved11[9]; // + AT91_REG PIOA_OWER; // Output Write Enable Register + AT91_REG PIOA_OWDR; // Output Write Disable Register + AT91_REG PIOA_OWSR; // Output Write Status Register + AT91_REG Reserved12[85]; // + AT91_REG PIOB_PER; // PIO Enable Register + AT91_REG PIOB_PDR; // PIO Disable Register + AT91_REG PIOB_PSR; // PIO Status Register + AT91_REG Reserved13[1]; // + AT91_REG PIOB_OER; // Output Enable Register + AT91_REG PIOB_ODR; // Output Disable Registerr + AT91_REG PIOB_OSR; // Output Status Register + AT91_REG Reserved14[1]; // + AT91_REG PIOB_IFER; // Input Filter Enable Register + AT91_REG PIOB_IFDR; // Input Filter Disable Register + AT91_REG PIOB_IFSR; // Input Filter Status Register + AT91_REG Reserved15[1]; // + AT91_REG PIOB_SODR; // Set Output Data Register + AT91_REG PIOB_CODR; // Clear Output Data Register + AT91_REG PIOB_ODSR; // Output Data Status Register + AT91_REG PIOB_PDSR; // Pin Data Status Register + AT91_REG PIOB_IER; // Interrupt Enable Register + AT91_REG PIOB_IDR; // Interrupt Disable Register + AT91_REG PIOB_IMR; // Interrupt Mask Register + AT91_REG PIOB_ISR; // Interrupt Status Register + AT91_REG PIOB_MDER; // Multi-driver Enable Register + AT91_REG PIOB_MDDR; // Multi-driver Disable Register + AT91_REG PIOB_MDSR; // Multi-driver Status Register + AT91_REG Reserved16[1]; // + AT91_REG PIOB_PPUDR; // Pull-up Disable Register + AT91_REG PIOB_PPUER; // Pull-up Enable Register + AT91_REG PIOB_PPUSR; // Pull-up Status Register + AT91_REG Reserved17[1]; // + AT91_REG PIOB_ASR; // Select A Register + AT91_REG PIOB_BSR; // Select B Register + AT91_REG PIOB_ABSR; // AB Select Status Register + AT91_REG Reserved18[9]; // + AT91_REG PIOB_OWER; // Output Write Enable Register + AT91_REG PIOB_OWDR; // Output Write Disable Register + AT91_REG PIOB_OWSR; // Output Write Status Register + AT91_REG Reserved19[341]; // + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved20[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved21[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved22[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved23[3]; // + AT91_REG PMC_PCKR[4]; // Programmable Clock Register + AT91_REG Reserved24[4]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register + AT91_REG Reserved25[36]; // + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register + AT91_REG Reserved26[5]; // + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register + AT91_REG Reserved27[5]; // + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_SYS, *AT91PS_SYS; + + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +typedef struct _AT91S_AIC { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register +} AT91S_AIC, *AT91PS_AIC; + +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// ***************************************************************************** +typedef struct _AT91S_PDC { + AT91_REG PDC_RPR; // Receive Pointer Register + AT91_REG PDC_RCR; // Receive Counter Register + AT91_REG PDC_TPR; // Transmit Pointer Register + AT91_REG PDC_TCR; // Transmit Counter Register + AT91_REG PDC_RNPR; // Receive Next Pointer Register + AT91_REG PDC_RNCR; // Receive Next Counter Register + AT91_REG PDC_TNPR; // Transmit Next Pointer Register + AT91_REG PDC_TNCR; // Transmit Next Counter Register + AT91_REG PDC_PTCR; // PDC Transfer Control Register + AT91_REG PDC_PTSR; // PDC Transfer Status Register +} AT91S_PDC, *AT91PS_PDC; + +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +typedef struct _AT91S_DBGU { + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved0[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved1[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register +} AT91S_DBGU, *AT91PS_DBGU; + +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable +#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +typedef struct _AT91S_PIO { + AT91_REG PIO_PER; // PIO Enable Register + AT91_REG PIO_PDR; // PIO Disable Register + AT91_REG PIO_PSR; // PIO Status Register + AT91_REG Reserved0[1]; // + AT91_REG PIO_OER; // Output Enable Register + AT91_REG PIO_ODR; // Output Disable Registerr + AT91_REG PIO_OSR; // Output Status Register + AT91_REG Reserved1[1]; // + AT91_REG PIO_IFER; // Input Filter Enable Register + AT91_REG PIO_IFDR; // Input Filter Disable Register + AT91_REG PIO_IFSR; // Input Filter Status Register + AT91_REG Reserved2[1]; // + AT91_REG PIO_SODR; // Set Output Data Register + AT91_REG PIO_CODR; // Clear Output Data Register + AT91_REG PIO_ODSR; // Output Data Status Register + AT91_REG PIO_PDSR; // Pin Data Status Register + AT91_REG PIO_IER; // Interrupt Enable Register + AT91_REG PIO_IDR; // Interrupt Disable Register + AT91_REG PIO_IMR; // Interrupt Mask Register + AT91_REG PIO_ISR; // Interrupt Status Register + AT91_REG PIO_MDER; // Multi-driver Enable Register + AT91_REG PIO_MDDR; // Multi-driver Disable Register + AT91_REG PIO_MDSR; // Multi-driver Status Register + AT91_REG Reserved3[1]; // + AT91_REG PIO_PPUDR; // Pull-up Disable Register + AT91_REG PIO_PPUER; // Pull-up Enable Register + AT91_REG PIO_PPUSR; // Pull-up Status Register + AT91_REG Reserved4[1]; // + AT91_REG PIO_ASR; // Select A Register + AT91_REG PIO_BSR; // Select B Register + AT91_REG PIO_ABSR; // AB Select Status Register + AT91_REG Reserved5[9]; // + AT91_REG PIO_OWER; // Output Write Enable Register + AT91_REG PIO_OWDR; // Output Write Disable Register + AT91_REG PIO_OWSR; // Output Write Status Register +} AT91S_PIO, *AT91PS_PIO; + + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +typedef struct _AT91S_CKGR { + AT91_REG CKGR_MOR; // Main Oscillator Register + AT91_REG CKGR_MCFR; // Main Clock Frequency Register + AT91_REG Reserved0[1]; // + AT91_REG CKGR_PLLR; // PLL Register +} AT91S_CKGR, *AT91PS_CKGR; + +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +typedef struct _AT91S_PMC { + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved0[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved1[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved2[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved3[3]; // + AT91_REG PMC_PCKR[4]; // Programmable Clock Register + AT91_REG Reserved4[4]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register +} AT91S_PMC, *AT91PS_PMC; + +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +typedef struct _AT91S_RSTC { + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register +} AT91S_RSTC, *AT91PS_RSTC; + +// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset +#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset +#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password +// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status +#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status +#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type +#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured. +#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level +#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable +#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_RTTC { + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register +} AT91S_RTTC, *AT91PS_RTTC; + +// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value +// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value +// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_PITC { + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register +} AT91S_PITC, *AT91PS_PITC; + +// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_WDTC { + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register +} AT91S_WDTC, *AT91PS_WDTC; + +// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart +#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password +// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface +// ***************************************************************************** +typedef struct _AT91S_VREG { + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_VREG, *AT91PS_VREG; + +// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- +#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +typedef struct _AT91S_MC { + AT91_REG MC_RCR; // MC Remap Control Register + AT91_REG MC_ASR; // MC Abort Status Register + AT91_REG MC_AASR; // MC Abort Address Status Register + AT91_REG Reserved0[21]; // + AT91_REG MC_FMR; // MC Flash Mode Register + AT91_REG MC_FCR; // MC Flash Command Register + AT91_REG MC_FSR; // MC Flash Status Register +} AT91S_MC, *AT91PS_MC; + +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready +#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error +#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error +#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming +#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State +#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number +// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command +#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit. +#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number +#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key +// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- +#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status +#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +typedef struct _AT91S_SPI { + AT91_REG SPI_CR; // Control Register + AT91_REG SPI_MR; // Mode Register + AT91_REG SPI_RDR; // Receive Data Register + AT91_REG SPI_TDR; // Transmit Data Register + AT91_REG SPI_SR; // Status Register + AT91_REG SPI_IER; // Interrupt Enable Register + AT91_REG SPI_IDR; // Interrupt Disable Register + AT91_REG SPI_IMR; // Interrupt Mask Register + AT91_REG Reserved0[4]; // + AT91_REG SPI_CSR[4]; // Chip Select Register + AT91_REG Reserved1[48]; // + AT91_REG SPI_RPR; // Receive Pointer Register + AT91_REG SPI_RCR; // Receive Counter Register + AT91_REG SPI_TPR; // Transmit Pointer Register + AT91_REG SPI_TCR; // Transmit Counter Register + AT91_REG SPI_RNPR; // Receive Next Pointer Register + AT91_REG SPI_RNCR; // Receive Next Counter Register + AT91_REG SPI_TNPR; // Transmit Next Pointer Register + AT91_REG SPI_TNCR; // Transmit Next Counter Register + AT91_REG SPI_PTCR; // PDC Transfer Control Register + AT91_REG SPI_PTSR; // PDC Transfer Status Register +} AT91S_SPI, *AT91PS_SPI; + +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK +#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +typedef struct _AT91S_USART { + AT91_REG US_CR; // Control Register + AT91_REG US_MR; // Mode Register + AT91_REG US_IER; // Interrupt Enable Register + AT91_REG US_IDR; // Interrupt Disable Register + AT91_REG US_IMR; // Interrupt Mask Register + AT91_REG US_CSR; // Channel Status Register + AT91_REG US_RHR; // Receiver Holding Register + AT91_REG US_THR; // Transmitter Holding Register + AT91_REG US_BRGR; // Baud Rate Generator Register + AT91_REG US_RTOR; // Receiver Time-out Register + AT91_REG US_TTGR; // Transmitter Time-guard Register + AT91_REG Reserved0[5]; // + AT91_REG US_FIDI; // FI_DI_Ratio Register + AT91_REG US_NER; // Nb Errors Register + AT91_REG Reserved1[1]; // + AT91_REG US_IF; // IRDA_FILTER Register + AT91_REG Reserved2[44]; // + AT91_REG US_RPR; // Receive Pointer Register + AT91_REG US_RCR; // Receive Counter Register + AT91_REG US_TPR; // Transmit Pointer Register + AT91_REG US_TCR; // Transmit Counter Register + AT91_REG US_RNPR; // Receive Next Pointer Register + AT91_REG US_RNCR; // Receive Next Counter Register + AT91_REG US_TNPR; // Transmit Next Pointer Register + AT91_REG US_TNCR; // Transmit Next Counter Register + AT91_REG US_PTCR; // PDC Transfer Control Register + AT91_REG US_PTSR; // PDC Transfer Status Register +} AT91S_USART, *AT91PS_USART; + +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +typedef struct _AT91S_SSC { + AT91_REG SSC_CR; // Control Register + AT91_REG SSC_CMR; // Clock Mode Register + AT91_REG Reserved0[2]; // + AT91_REG SSC_RCMR; // Receive Clock ModeRegister + AT91_REG SSC_RFMR; // Receive Frame Mode Register + AT91_REG SSC_TCMR; // Transmit Clock Mode Register + AT91_REG SSC_TFMR; // Transmit Frame Mode Register + AT91_REG SSC_RHR; // Receive Holding Register + AT91_REG SSC_THR; // Transmit Holding Register + AT91_REG Reserved1[2]; // + AT91_REG SSC_RSHR; // Receive Sync Holding Register + AT91_REG SSC_TSHR; // Transmit Sync Holding Register + AT91_REG Reserved2[2]; // + AT91_REG SSC_SR; // Status Register + AT91_REG SSC_IER; // Interrupt Enable Register + AT91_REG SSC_IDR; // Interrupt Disable Register + AT91_REG SSC_IMR; // Interrupt Mask Register + AT91_REG Reserved3[44]; // + AT91_REG SSC_RPR; // Receive Pointer Register + AT91_REG SSC_RCR; // Receive Counter Register + AT91_REG SSC_TPR; // Transmit Pointer Register + AT91_REG SSC_TCR; // Transmit Counter Register + AT91_REG SSC_RNPR; // Receive Next Pointer Register + AT91_REG SSC_RNCR; // Receive Next Counter Register + AT91_REG SSC_TNPR; // Transmit Next Pointer Register + AT91_REG SSC_TNCR; // Transmit Next Counter Register + AT91_REG SSC_PTCR; // PDC Transfer Control Register + AT91_REG SSC_PTSR; // PDC Transfer Status Register +} AT91S_SSC, *AT91PS_SSC; + +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin +#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +typedef struct _AT91S_TWI { + AT91_REG TWI_CR; // Control Register + AT91_REG TWI_MMR; // Master Mode Register + AT91_REG Reserved0[1]; // + AT91_REG TWI_IADR; // Internal Address Register + AT91_REG TWI_CWGR; // Clock Waveform Generator Register + AT91_REG Reserved1[3]; // + AT91_REG TWI_SR; // Status Register + AT91_REG TWI_IER; // Interrupt Enable Register + AT91_REG TWI_IDR; // Interrupt Disable Register + AT91_REG TWI_IMR; // Interrupt Mask Register + AT91_REG TWI_RHR; // Receive Holding Register + AT91_REG TWI_THR; // Transmit Holding Register +} AT91S_TWI, *AT91PS_TWI; + +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +typedef struct _AT91S_PWMC_CH { + AT91_REG PWMC_CMR; // Channel Mode Register + AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register + AT91_REG PWMC_CPRDR; // Channel Period Register + AT91_REG PWMC_CCNTR; // Channel Counter Register + AT91_REG PWMC_CUPDR; // Channel Update Register + AT91_REG PWMC_Reserved[3]; // Reserved +} AT91S_PWMC_CH, *AT91PS_PWMC_CH; + +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +typedef struct _AT91S_PWMC { + AT91_REG PWMC_MR; // PWMC Mode Register + AT91_REG PWMC_ENA; // PWMC Enable Register + AT91_REG PWMC_DIS; // PWMC Disable Register + AT91_REG PWMC_SR; // PWMC Status Register + AT91_REG PWMC_IER; // PWMC Interrupt Enable Register + AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register + AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register + AT91_REG PWMC_ISR; // PWMC Interrupt Status Register + AT91_REG Reserved0[55]; // + AT91_REG PWMC_VR; // PWMC Version Register + AT91_REG Reserved1[64]; // + AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel +} AT91S_PWMC, *AT91PS_PWMC; + +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +typedef struct _AT91S_UDP { + AT91_REG UDP_NUM; // Frame Number Register + AT91_REG UDP_GLBSTATE; // Global State Register + AT91_REG UDP_FADDR; // Function Address Register + AT91_REG Reserved0[1]; // + AT91_REG UDP_IER; // Interrupt Enable Register + AT91_REG UDP_IDR; // Interrupt Disable Register + AT91_REG UDP_IMR; // Interrupt Mask Register + AT91_REG UDP_ISR; // Interrupt Status Register + AT91_REG UDP_ICR; // Interrupt Clear Register + AT91_REG Reserved1[1]; // + AT91_REG UDP_RSTEP; // Reset Endpoint Register + AT91_REG Reserved2[1]; // + AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register + AT91_REG Reserved3[2]; // + AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register + AT91_REG Reserved4[3]; // + AT91_REG UDP_TXVC; // Transceiver Control Register +} AT91S_UDP, *AT91PS_UDP; + +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured +#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume +#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt +#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt +#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3 +#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4 +#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO +// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP) +#define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +typedef struct _AT91S_TC { + AT91_REG TC_CCR; // Channel Control Register + AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) + AT91_REG Reserved0[2]; // + AT91_REG TC_CV; // Counter Value + AT91_REG TC_RA; // Register A + AT91_REG TC_RB; // Register B + AT91_REG TC_RC; // Register C + AT91_REG TC_SR; // Status Register + AT91_REG TC_IER; // Interrupt Enable Register + AT91_REG TC_IDR; // Interrupt Disable Register + AT91_REG TC_IMR; // Interrupt Mask Register +} AT91S_TC, *AT91PS_TC; + +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) +#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger +#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +typedef struct _AT91S_TCB { + AT91S_TC TCB_TC0; // TC Channel 0 + AT91_REG Reserved0[4]; // + AT91S_TC TCB_TC1; // TC Channel 1 + AT91_REG Reserved1[4]; // + AT91S_TC TCB_TC2; // TC Channel 2 + AT91_REG Reserved2[4]; // + AT91_REG TCB_BCR; // TC Block Control Register + AT91_REG TCB_BMR; // TC Block Mode Register +} AT91S_TCB, *AT91PS_TCB; + +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface +// ***************************************************************************** +typedef struct _AT91S_CAN_MB { + AT91_REG CAN_MB_MMR; // MailBox Mode Register + AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register + AT91_REG CAN_MB_MID; // MailBox ID Register + AT91_REG CAN_MB_MFID; // MailBox Family ID Register + AT91_REG CAN_MB_MSR; // MailBox Status Register + AT91_REG CAN_MB_MDL; // MailBox Data Low Register + AT91_REG CAN_MB_MDH; // MailBox Data High Register + AT91_REG CAN_MB_MCR; // MailBox Control Register +} AT91S_CAN_MB, *AT91PS_CAN_MB; + +// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- +#define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark +#define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority +#define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type +#define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB) +// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- +#define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode +#define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode +#define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version +// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- +// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- +// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- +#define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value +#define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code +#define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request +#define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort +#define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready +#define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored +// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- +// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- +// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- +#define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox +#define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network Interface +// ***************************************************************************** +typedef struct _AT91S_CAN { + AT91_REG CAN_MR; // Mode Register + AT91_REG CAN_IER; // Interrupt Enable Register + AT91_REG CAN_IDR; // Interrupt Disable Register + AT91_REG CAN_IMR; // Interrupt Mask Register + AT91_REG CAN_SR; // Status Register + AT91_REG CAN_BR; // Baudrate Register + AT91_REG CAN_TIM; // Timer Register + AT91_REG CAN_TIMESTP; // Time Stamp Register + AT91_REG CAN_ECR; // Error Counter Register + AT91_REG CAN_TCR; // Transfer Command Register + AT91_REG CAN_ACR; // Abort Command Register + AT91_REG Reserved0[52]; // + AT91_REG CAN_VR; // Version Register + AT91_REG Reserved1[64]; // + AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0 + AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1 + AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2 + AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3 + AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4 + AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5 + AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6 + AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7 + AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8 + AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9 + AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10 + AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11 + AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12 + AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13 + AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14 + AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15 +} AT91S_CAN, *AT91PS_CAN; + +// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- +#define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable +#define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode +#define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode +#define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame +#define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame +#define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode +#define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze +#define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat +// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- +#define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag +#define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag +#define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag +#define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag +#define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag +#define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag +#define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag +#define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag +#define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag +#define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag +#define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag +#define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag +#define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag +#define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag +#define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag +#define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag +#define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag +#define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag +#define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag +#define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag +#define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag +#define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag +#define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag +#define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag +#define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error +#define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error +#define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error +#define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error +#define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error +// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- +// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- +// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- +#define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy +#define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy +#define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy +// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- +#define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment +#define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment +#define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment +#define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment +#define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler +#define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode +// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- +#define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field +// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- +// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- +#define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter +#define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter +// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- +#define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field +// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 +// ***************************************************************************** +typedef struct _AT91S_EMAC { + AT91_REG EMAC_NCR; // Network Control Register + AT91_REG EMAC_NCFGR; // Network Configuration Register + AT91_REG EMAC_NSR; // Network Status Register + AT91_REG Reserved0[2]; // + AT91_REG EMAC_TSR; // Transmit Status Register + AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer + AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer + AT91_REG EMAC_RSR; // Receive Status Register + AT91_REG EMAC_ISR; // Interrupt Status Register + AT91_REG EMAC_IER; // Interrupt Enable Register + AT91_REG EMAC_IDR; // Interrupt Disable Register + AT91_REG EMAC_IMR; // Interrupt Mask Register + AT91_REG EMAC_MAN; // PHY Maintenance Register + AT91_REG EMAC_PTR; // Pause Time Register + AT91_REG EMAC_PFR; // Pause Frames received Register + AT91_REG EMAC_FTO; // Frames Transmitted OK Register + AT91_REG EMAC_SCF; // Single Collision Frame Register + AT91_REG EMAC_MCF; // Multiple Collision Frame Register + AT91_REG EMAC_FRO; // Frames Received OK Register + AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register + AT91_REG EMAC_ALE; // Alignment Error Register + AT91_REG EMAC_DTF; // Deferred Transmission Frame Register + AT91_REG EMAC_LCOL; // Late Collision Register + AT91_REG EMAC_ECOL; // Excessive Collision Register + AT91_REG EMAC_TUND; // Transmit Underrun Error Register + AT91_REG EMAC_CSE; // Carrier Sense Error Register + AT91_REG EMAC_RRE; // Receive Ressource Error Register + AT91_REG EMAC_ROV; // Receive Overrun Errors Register + AT91_REG EMAC_RSE; // Receive Symbol Errors Register + AT91_REG EMAC_ELE; // Excessive Length Errors Register + AT91_REG EMAC_RJA; // Receive Jabbers Register + AT91_REG EMAC_USF; // Undersize Frames Register + AT91_REG EMAC_STE; // SQE Test Error Register + AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register + AT91_REG EMAC_TPF; // Transmitted Pause Frames Register + AT91_REG EMAC_HRB; // Hash Address Bottom[31:0] + AT91_REG EMAC_HRT; // Hash Address Top[63:32] + AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes + AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes + AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes + AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes + AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes + AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes + AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes + AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes + AT91_REG EMAC_TID; // Type ID Checking Register + AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register + AT91_REG EMAC_USRIO; // USER Input/Output Register + AT91_REG EMAC_WOL; // Wake On LAN Register + AT91_REG Reserved1[13]; // + AT91_REG EMAC_REV; // Revision Register +} AT91S_EMAC, *AT91PS_EMAC; + +// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- +#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. +#define AT91C_EMAC_LLB ((unsigned int) 0x1 << 1) // (EMAC) Loopback local. +#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable. +#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable. +#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable. +#define AT91C_EMAC_CLRSTAT ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers. +#define AT91C_EMAC_INCSTAT ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers. +#define AT91C_EMAC_WESTAT ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers. +#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure. +#define AT91C_EMAC_TSTART ((unsigned int) 0x1 << 9) // (EMAC) Start Transmission. +#define AT91C_EMAC_THALT ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. +#define AT91C_EMAC_TPFR ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame +#define AT91C_EMAC_TZQ ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame +// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- +#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed. +#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex. +#define AT91C_EMAC_JFRAME ((unsigned int) 0x1 << 3) // (EMAC) Jumbo Frames. +#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames. +#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast. +#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash event enable +#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable. +#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes. +#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable. +#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC) +#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8 +#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16 +#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32 +#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64 +#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC) +#define AT91C_EMAC_PAE ((unsigned int) 0x1 << 13) // (EMAC) +#define AT91C_EMAC_RBOF ((unsigned int) 0x3 << 14) // (EMAC) +#define AT91C_EMAC_RBOF_OFFSET_0 ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_1 ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_2 ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_3 ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer +#define AT91C_EMAC_RLCE ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable +#define AT91C_EMAC_DRFCS ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS +#define AT91C_EMAC_EFRHD ((unsigned int) 0x1 << 18) // (EMAC) +#define AT91C_EMAC_IRXFCS ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS +// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- +#define AT91C_EMAC_LINKR ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC) +// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- +#define AT91C_EMAC_UBR ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_RLES ((unsigned int) 0x1 << 2) // (EMAC) +#define AT91C_EMAC_TGO ((unsigned int) 0x1 << 3) // (EMAC) Transmit Go +#define AT91C_EMAC_BEX ((unsigned int) 0x1 << 4) // (EMAC) Buffers exhausted mid frame +#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC) +#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC) +// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- +#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 2) // (EMAC) +// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- +#define AT91C_EMAC_MFD ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_RCOMP ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_RXUBR ((unsigned int) 0x1 << 2) // (EMAC) +#define AT91C_EMAC_TXUBR ((unsigned int) 0x1 << 3) // (EMAC) +#define AT91C_EMAC_TUNDR ((unsigned int) 0x1 << 4) // (EMAC) +#define AT91C_EMAC_RLEX ((unsigned int) 0x1 << 5) // (EMAC) +#define AT91C_EMAC_TXERR ((unsigned int) 0x1 << 6) // (EMAC) +#define AT91C_EMAC_TCOMP ((unsigned int) 0x1 << 7) // (EMAC) +#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC) +#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC) +#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC) +#define AT91C_EMAC_PFRE ((unsigned int) 0x1 << 12) // (EMAC) +#define AT91C_EMAC_PTZ ((unsigned int) 0x1 << 13) // (EMAC) +// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- +// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- +// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- +// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- +#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC) +#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC) +#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC) +#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC) +#define AT91C_EMAC_SOF ((unsigned int) 0x3 << 30) // (EMAC) +// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- +#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 0) // (EMAC) Reduce MII +// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- +#define AT91C_EMAC_IP ((unsigned int) 0xFFFF << 0) // (EMAC) ARP request IP address +#define AT91C_EMAC_MAG ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable +#define AT91C_EMAC_ARP ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable +#define AT91C_EMAC_SA1 ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable +// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- +#define AT91C_EMAC_REVREF ((unsigned int) 0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_PARTREF ((unsigned int) 0xFFFF << 16) // (EMAC) + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +typedef struct _AT91S_ADC { + AT91_REG ADC_CR; // ADC Control Register + AT91_REG ADC_MR; // ADC Mode Register + AT91_REG Reserved0[2]; // + AT91_REG ADC_CHER; // ADC Channel Enable Register + AT91_REG ADC_CHDR; // ADC Channel Disable Register + AT91_REG ADC_CHSR; // ADC Channel Status Register + AT91_REG ADC_SR; // ADC Status Register + AT91_REG ADC_LCDR; // ADC Last Converted Data Register + AT91_REG ADC_IER; // ADC Interrupt Enable Register + AT91_REG ADC_IDR; // ADC Interrupt Disable Register + AT91_REG ADC_IMR; // ADC Interrupt Mask Register + AT91_REG ADC_CDR0; // ADC Channel Data Register 0 + AT91_REG ADC_CDR1; // ADC Channel Data Register 1 + AT91_REG ADC_CDR2; // ADC Channel Data Register 2 + AT91_REG ADC_CDR3; // ADC Channel Data Register 3 + AT91_REG ADC_CDR4; // ADC Channel Data Register 4 + AT91_REG ADC_CDR5; // ADC Channel Data Register 5 + AT91_REG ADC_CDR6; // ADC Channel Data Register 6 + AT91_REG ADC_CDR7; // ADC Channel Data Register 7 + AT91_REG Reserved1[44]; // + AT91_REG ADC_RPR; // Receive Pointer Register + AT91_REG ADC_RCR; // Receive Counter Register + AT91_REG ADC_TPR; // Transmit Pointer Register + AT91_REG ADC_TCR; // Transmit Counter Register + AT91_REG ADC_RNPR; // Receive Next Pointer Register + AT91_REG ADC_RNCR; // Receive Next Counter Register + AT91_REG ADC_TNPR; // Transmit Next Pointer Register + AT91_REG ADC_TNCR; // Transmit Next Counter Register + AT91_REG ADC_PTCR; // PDC Transfer Control Register + AT91_REG ADC_PTSR; // PDC Transfer Status Register +} AT91S_ADC, *AT91PS_ADC; + +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Encryption Standard +// ***************************************************************************** +typedef struct _AT91S_AES { + AT91_REG AES_CR; // Control Register + AT91_REG AES_MR; // Mode Register + AT91_REG Reserved0[2]; // + AT91_REG AES_IER; // Interrupt Enable Register + AT91_REG AES_IDR; // Interrupt Disable Register + AT91_REG AES_IMR; // Interrupt Mask Register + AT91_REG AES_ISR; // Interrupt Status Register + AT91_REG AES_KEYWxR[4]; // Key Word x Register + AT91_REG Reserved1[4]; // + AT91_REG AES_IDATAxR[4]; // Input Data x Register + AT91_REG AES_ODATAxR[4]; // Output Data x Register + AT91_REG AES_IVxR[4]; // Initialization Vector x Register + AT91_REG Reserved2[35]; // + AT91_REG AES_VR; // AES Version Register + AT91_REG AES_RPR; // Receive Pointer Register + AT91_REG AES_RCR; // Receive Counter Register + AT91_REG AES_TPR; // Transmit Pointer Register + AT91_REG AES_TCR; // Transmit Counter Register + AT91_REG AES_RNPR; // Receive Next Pointer Register + AT91_REG AES_RNCR; // Receive Next Counter Register + AT91_REG AES_TNPR; // Transmit Next Pointer Register + AT91_REG AES_TNCR; // Transmit Next Counter Register + AT91_REG AES_PTCR; // PDC Transfer Control Register + AT91_REG AES_PTSR; // PDC Transfer Status Register +} AT91S_AES, *AT91PS_AES; + +// -------- AES_CR : (AES Offset: 0x0) Control Register -------- +#define AT91C_AES_START ((unsigned int) 0x1 << 0) // (AES) Starts Processing +#define AT91C_AES_SWRST ((unsigned int) 0x1 << 8) // (AES) Software Reset +#define AT91C_AES_LOADSEED ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading +// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- +#define AT91C_AES_CIPHER ((unsigned int) 0x1 << 0) // (AES) Processing Mode +#define AT91C_AES_PROCDLY ((unsigned int) 0xF << 4) // (AES) Processing Delay +#define AT91C_AES_SMOD ((unsigned int) 0x3 << 8) // (AES) Start Mode +#define AT91C_AES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. +#define AT91C_AES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). +#define AT91C_AES_SMOD_PDC ((unsigned int) 0x2 << 8) // (AES) PDC Mode (cf datasheet). +#define AT91C_AES_OPMOD ((unsigned int) 0x7 << 12) // (AES) Operation Mode +#define AT91C_AES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode. +#define AT91C_AES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode. +#define AT91C_AES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode. +#define AT91C_AES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode. +#define AT91C_AES_OPMOD_CTR ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode. +#define AT91C_AES_LOD ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode +#define AT91C_AES_CFBS ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size +#define AT91C_AES_CFBS_128_BIT ((unsigned int) 0x0 << 16) // (AES) 128-bit. +#define AT91C_AES_CFBS_64_BIT ((unsigned int) 0x1 << 16) // (AES) 64-bit. +#define AT91C_AES_CFBS_32_BIT ((unsigned int) 0x2 << 16) // (AES) 32-bit. +#define AT91C_AES_CFBS_16_BIT ((unsigned int) 0x3 << 16) // (AES) 16-bit. +#define AT91C_AES_CFBS_8_BIT ((unsigned int) 0x4 << 16) // (AES) 8-bit. +#define AT91C_AES_CKEY ((unsigned int) 0xF << 20) // (AES) Countermeasure Key +#define AT91C_AES_CTYPE ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type +#define AT91C_AES_CTYPE_TYPE1_EN ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled. +#define AT91C_AES_CTYPE_TYPE2_EN ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled. +#define AT91C_AES_CTYPE_TYPE3_EN ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled. +#define AT91C_AES_CTYPE_TYPE4_EN ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled. +#define AT91C_AES_CTYPE_TYPE5_EN ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled. +// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- +#define AT91C_AES_DATRDY ((unsigned int) 0x1 << 0) // (AES) DATRDY +#define AT91C_AES_ENDRX ((unsigned int) 0x1 << 1) // (AES) PDC Read Buffer End +#define AT91C_AES_ENDTX ((unsigned int) 0x1 << 2) // (AES) PDC Write Buffer End +#define AT91C_AES_RXBUFF ((unsigned int) 0x1 << 3) // (AES) PDC Read Buffer Full +#define AT91C_AES_TXBUFE ((unsigned int) 0x1 << 4) // (AES) PDC Write Buffer Empty +#define AT91C_AES_URAD ((unsigned int) 0x1 << 8) // (AES) Unspecified Register Access Detection +// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- +// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- +// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- +#define AT91C_AES_URAT ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status +#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode. +#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing. +#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing. +#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation. +#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation. +#define AT91C_AES_URAT_WO_REG_READ ((unsigned int) 0x5 << 12) // (AES) Write-only register read access. + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard +// ***************************************************************************** +typedef struct _AT91S_TDES { + AT91_REG TDES_CR; // Control Register + AT91_REG TDES_MR; // Mode Register + AT91_REG Reserved0[2]; // + AT91_REG TDES_IER; // Interrupt Enable Register + AT91_REG TDES_IDR; // Interrupt Disable Register + AT91_REG TDES_IMR; // Interrupt Mask Register + AT91_REG TDES_ISR; // Interrupt Status Register + AT91_REG TDES_KEY1WxR[2]; // Key 1 Word x Register + AT91_REG TDES_KEY2WxR[2]; // Key 2 Word x Register + AT91_REG TDES_KEY3WxR[2]; // Key 3 Word x Register + AT91_REG Reserved1[2]; // + AT91_REG TDES_IDATAxR[2]; // Input Data x Register + AT91_REG Reserved2[2]; // + AT91_REG TDES_ODATAxR[2]; // Output Data x Register + AT91_REG Reserved3[2]; // + AT91_REG TDES_IVxR[2]; // Initialization Vector x Register + AT91_REG Reserved4[37]; // + AT91_REG TDES_VR; // TDES Version Register + AT91_REG TDES_RPR; // Receive Pointer Register + AT91_REG TDES_RCR; // Receive Counter Register + AT91_REG TDES_TPR; // Transmit Pointer Register + AT91_REG TDES_TCR; // Transmit Counter Register + AT91_REG TDES_RNPR; // Receive Next Pointer Register + AT91_REG TDES_RNCR; // Receive Next Counter Register + AT91_REG TDES_TNPR; // Transmit Next Pointer Register + AT91_REG TDES_TNCR; // Transmit Next Counter Register + AT91_REG TDES_PTCR; // PDC Transfer Control Register + AT91_REG TDES_PTSR; // PDC Transfer Status Register +} AT91S_TDES, *AT91PS_TDES; + +// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- +#define AT91C_TDES_START ((unsigned int) 0x1 << 0) // (TDES) Starts Processing +#define AT91C_TDES_SWRST ((unsigned int) 0x1 << 8) // (TDES) Software Reset +// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- +#define AT91C_TDES_CIPHER ((unsigned int) 0x1 << 0) // (TDES) Processing Mode +#define AT91C_TDES_TDESMOD ((unsigned int) 0x1 << 1) // (TDES) Single or Triple DES Mode +#define AT91C_TDES_KEYMOD ((unsigned int) 0x1 << 4) // (TDES) Key Mode +#define AT91C_TDES_SMOD ((unsigned int) 0x3 << 8) // (TDES) Start Mode +#define AT91C_TDES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. +#define AT91C_TDES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). +#define AT91C_TDES_SMOD_PDC ((unsigned int) 0x2 << 8) // (TDES) PDC Mode (cf datasheet). +#define AT91C_TDES_OPMOD ((unsigned int) 0x3 << 12) // (TDES) Operation Mode +#define AT91C_TDES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode. +#define AT91C_TDES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode. +#define AT91C_TDES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode. +#define AT91C_TDES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode. +#define AT91C_TDES_LOD ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode +#define AT91C_TDES_CFBS ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size +#define AT91C_TDES_CFBS_64_BIT ((unsigned int) 0x0 << 16) // (TDES) 64-bit. +#define AT91C_TDES_CFBS_32_BIT ((unsigned int) 0x1 << 16) // (TDES) 32-bit. +#define AT91C_TDES_CFBS_16_BIT ((unsigned int) 0x2 << 16) // (TDES) 16-bit. +#define AT91C_TDES_CFBS_8_BIT ((unsigned int) 0x3 << 16) // (TDES) 8-bit. +// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- +#define AT91C_TDES_DATRDY ((unsigned int) 0x1 << 0) // (TDES) DATRDY +#define AT91C_TDES_ENDRX ((unsigned int) 0x1 << 1) // (TDES) PDC Read Buffer End +#define AT91C_TDES_ENDTX ((unsigned int) 0x1 << 2) // (TDES) PDC Write Buffer End +#define AT91C_TDES_RXBUFF ((unsigned int) 0x1 << 3) // (TDES) PDC Read Buffer Full +#define AT91C_TDES_TXBUFE ((unsigned int) 0x1 << 4) // (TDES) PDC Write Buffer Empty +#define AT91C_TDES_URAD ((unsigned int) 0x1 << 8) // (TDES) Unspecified Register Access Detection +// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- +// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- +// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- +#define AT91C_TDES_URAT ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status +#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode. +#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing. +#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing. +#define AT91C_TDES_URAT_WO_REG_READ ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access. + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 +// ***************************************************************************** +// ========== Register definition for SYS peripheral ========== +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register +#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register +#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register +#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register +#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register +// ========== Register definition for PIOB peripheral ========== +#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register +#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register +#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register +#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register +#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register +#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register +#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register +#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register +#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register +#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register +#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register +#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register +#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register +#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register +#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register +#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register +#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr +#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register +#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register +#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register +#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register +#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register +#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register +#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register +#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register +#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register +#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register +#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register +#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register +#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register +#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register +#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register +#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register +#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register +// ========== Register definition for VREG peripheral ========== +#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register +#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register +#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register +#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register +// ========== Register definition for PDC_SPI1 peripheral ========== +#define AT91C_SPI1_PTCR ((AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register +#define AT91C_SPI1_RPR ((AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register +#define AT91C_SPI1_TNCR ((AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register +#define AT91C_SPI1_TPR ((AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register +#define AT91C_SPI1_TNPR ((AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register +#define AT91C_SPI1_TCR ((AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register +#define AT91C_SPI1_RCR ((AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register +#define AT91C_SPI1_RNPR ((AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register +#define AT91C_SPI1_RNCR ((AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register +#define AT91C_SPI1_PTSR ((AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register +// ========== Register definition for SPI1 peripheral ========== +#define AT91C_SPI1_IMR ((AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register +#define AT91C_SPI1_IER ((AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register +#define AT91C_SPI1_MR ((AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register +#define AT91C_SPI1_RDR ((AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register +#define AT91C_SPI1_IDR ((AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register +#define AT91C_SPI1_SR ((AT91_REG *) 0xFFFE4010) // (SPI1) Status Register +#define AT91C_SPI1_TDR ((AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register +#define AT91C_SPI1_CR ((AT91_REG *) 0xFFFE4000) // (SPI1) Control Register +#define AT91C_SPI1_CSR ((AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register +// ========== Register definition for PDC_SPI0 peripheral ========== +#define AT91C_SPI0_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register +#define AT91C_SPI0_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register +#define AT91C_SPI0_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register +#define AT91C_SPI0_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register +#define AT91C_SPI0_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register +#define AT91C_SPI0_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register +#define AT91C_SPI0_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register +#define AT91C_SPI0_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register +#define AT91C_SPI0_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register +#define AT91C_SPI0_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register +// ========== Register definition for SPI0 peripheral ========== +#define AT91C_SPI0_IER ((AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register +#define AT91C_SPI0_SR ((AT91_REG *) 0xFFFE0010) // (SPI0) Status Register +#define AT91C_SPI0_IDR ((AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register +#define AT91C_SPI0_CR ((AT91_REG *) 0xFFFE0000) // (SPI0) Control Register +#define AT91C_SPI0_MR ((AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register +#define AT91C_SPI0_IMR ((AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register +#define AT91C_SPI0_TDR ((AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register +#define AT91C_SPI0_RDR ((AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register +#define AT91C_SPI0_CSR ((AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register +#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register +#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register +#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register +#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register +#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register +#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register +#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register +#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register +#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register +#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register +#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register +#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for CAN_MB0 peripheral ========== +#define AT91C_CAN_MB0_MDL ((AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register +#define AT91C_CAN_MB0_MAM ((AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register +#define AT91C_CAN_MB0_MCR ((AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register +#define AT91C_CAN_MB0_MID ((AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register +#define AT91C_CAN_MB0_MSR ((AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register +#define AT91C_CAN_MB0_MFID ((AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register +#define AT91C_CAN_MB0_MDH ((AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register +#define AT91C_CAN_MB0_MMR ((AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register +// ========== Register definition for CAN_MB1 peripheral ========== +#define AT91C_CAN_MB1_MDL ((AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register +#define AT91C_CAN_MB1_MID ((AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register +#define AT91C_CAN_MB1_MMR ((AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register +#define AT91C_CAN_MB1_MSR ((AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register +#define AT91C_CAN_MB1_MAM ((AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register +#define AT91C_CAN_MB1_MDH ((AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register +#define AT91C_CAN_MB1_MCR ((AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register +#define AT91C_CAN_MB1_MFID ((AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register +// ========== Register definition for CAN_MB2 peripheral ========== +#define AT91C_CAN_MB2_MCR ((AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register +#define AT91C_CAN_MB2_MDH ((AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register +#define AT91C_CAN_MB2_MID ((AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register +#define AT91C_CAN_MB2_MDL ((AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register +#define AT91C_CAN_MB2_MMR ((AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register +#define AT91C_CAN_MB2_MAM ((AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register +#define AT91C_CAN_MB2_MFID ((AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register +#define AT91C_CAN_MB2_MSR ((AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register +// ========== Register definition for CAN_MB3 peripheral ========== +#define AT91C_CAN_MB3_MFID ((AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register +#define AT91C_CAN_MB3_MAM ((AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register +#define AT91C_CAN_MB3_MID ((AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register +#define AT91C_CAN_MB3_MCR ((AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register +#define AT91C_CAN_MB3_MMR ((AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register +#define AT91C_CAN_MB3_MSR ((AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register +#define AT91C_CAN_MB3_MDL ((AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register +#define AT91C_CAN_MB3_MDH ((AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register +// ========== Register definition for CAN_MB4 peripheral ========== +#define AT91C_CAN_MB4_MID ((AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register +#define AT91C_CAN_MB4_MMR ((AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register +#define AT91C_CAN_MB4_MDH ((AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register +#define AT91C_CAN_MB4_MFID ((AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register +#define AT91C_CAN_MB4_MSR ((AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register +#define AT91C_CAN_MB4_MCR ((AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register +#define AT91C_CAN_MB4_MDL ((AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register +#define AT91C_CAN_MB4_MAM ((AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB5 peripheral ========== +#define AT91C_CAN_MB5_MSR ((AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register +#define AT91C_CAN_MB5_MCR ((AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register +#define AT91C_CAN_MB5_MFID ((AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register +#define AT91C_CAN_MB5_MDH ((AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register +#define AT91C_CAN_MB5_MID ((AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register +#define AT91C_CAN_MB5_MMR ((AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register +#define AT91C_CAN_MB5_MDL ((AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register +#define AT91C_CAN_MB5_MAM ((AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB6 peripheral ========== +#define AT91C_CAN_MB6_MFID ((AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register +#define AT91C_CAN_MB6_MID ((AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register +#define AT91C_CAN_MB6_MAM ((AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register +#define AT91C_CAN_MB6_MSR ((AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register +#define AT91C_CAN_MB6_MDL ((AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register +#define AT91C_CAN_MB6_MCR ((AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register +#define AT91C_CAN_MB6_MDH ((AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register +#define AT91C_CAN_MB6_MMR ((AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register +// ========== Register definition for CAN_MB7 peripheral ========== +#define AT91C_CAN_MB7_MCR ((AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register +#define AT91C_CAN_MB7_MDH ((AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register +#define AT91C_CAN_MB7_MFID ((AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register +#define AT91C_CAN_MB7_MDL ((AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register +#define AT91C_CAN_MB7_MID ((AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register +#define AT91C_CAN_MB7_MMR ((AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register +#define AT91C_CAN_MB7_MAM ((AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register +#define AT91C_CAN_MB7_MSR ((AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register +// ========== Register definition for CAN peripheral ========== +#define AT91C_CAN_TCR ((AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register +#define AT91C_CAN_IMR ((AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register +#define AT91C_CAN_IER ((AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register +#define AT91C_CAN_ECR ((AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register +#define AT91C_CAN_TIMESTP ((AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register +#define AT91C_CAN_MR ((AT91_REG *) 0xFFFD0000) // (CAN) Mode Register +#define AT91C_CAN_IDR ((AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register +#define AT91C_CAN_ACR ((AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register +#define AT91C_CAN_TIM ((AT91_REG *) 0xFFFD0018) // (CAN) Timer Register +#define AT91C_CAN_SR ((AT91_REG *) 0xFFFD0010) // (CAN) Status Register +#define AT91C_CAN_BR ((AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register +#define AT91C_CAN_VR ((AT91_REG *) 0xFFFD00FC) // (CAN) Version Register +// ========== Register definition for EMAC peripheral ========== +#define AT91C_EMAC_ISR ((AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register +#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes +#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes +#define AT91C_EMAC_ELE ((AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register +#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register +#define AT91C_EMAC_RLE ((AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register +#define AT91C_EMAC_WOL ((AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register +#define AT91C_EMAC_DTF ((AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register +#define AT91C_EMAC_TUND ((AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register +#define AT91C_EMAC_NCR ((AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register +#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes +#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register +#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes +#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register +#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register +#define AT91C_EMAC_RSE ((AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register +#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register +#define AT91C_EMAC_TID ((AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register +#define AT91C_EMAC_HRB ((AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] +#define AT91C_EMAC_TBQP ((AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer +#define AT91C_EMAC_USRIO ((AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register +#define AT91C_EMAC_PTR ((AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register +#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes +#define AT91C_EMAC_ROV ((AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register +#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register +#define AT91C_EMAC_RJA ((AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register +#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer +#define AT91C_EMAC_TPF ((AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register +#define AT91C_EMAC_NCFGR ((AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register +#define AT91C_EMAC_HRT ((AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32] +#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register +#define AT91C_EMAC_FCSE ((AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register +#define AT91C_EMAC_TPQ ((AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register +#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register +#define AT91C_EMAC_FTO ((AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register +#define AT91C_EMAC_REV ((AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register +#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register +#define AT91C_EMAC_SCF ((AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register +#define AT91C_EMAC_PFR ((AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register +#define AT91C_EMAC_MCF ((AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register +#define AT91C_EMAC_NSR ((AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register +#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes +#define AT91C_EMAC_FRO ((AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register +#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register +#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes +#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register +#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes +#define AT91C_EMAC_RRE ((AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register +#define AT91C_EMAC_STE ((AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register +#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register +// ========== Register definition for PDC_AES peripheral ========== +#define AT91C_AES_TPR ((AT91_REG *) 0xFFFA4108) // (PDC_AES) Transmit Pointer Register +#define AT91C_AES_PTCR ((AT91_REG *) 0xFFFA4120) // (PDC_AES) PDC Transfer Control Register +#define AT91C_AES_RNPR ((AT91_REG *) 0xFFFA4110) // (PDC_AES) Receive Next Pointer Register +#define AT91C_AES_TNCR ((AT91_REG *) 0xFFFA411C) // (PDC_AES) Transmit Next Counter Register +#define AT91C_AES_TCR ((AT91_REG *) 0xFFFA410C) // (PDC_AES) Transmit Counter Register +#define AT91C_AES_RCR ((AT91_REG *) 0xFFFA4104) // (PDC_AES) Receive Counter Register +#define AT91C_AES_RNCR ((AT91_REG *) 0xFFFA4114) // (PDC_AES) Receive Next Counter Register +#define AT91C_AES_TNPR ((AT91_REG *) 0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register +#define AT91C_AES_RPR ((AT91_REG *) 0xFFFA4100) // (PDC_AES) Receive Pointer Register +#define AT91C_AES_PTSR ((AT91_REG *) 0xFFFA4124) // (PDC_AES) PDC Transfer Status Register +// ========== Register definition for AES peripheral ========== +#define AT91C_AES_IVxR ((AT91_REG *) 0xFFFA4060) // (AES) Initialization Vector x Register +#define AT91C_AES_MR ((AT91_REG *) 0xFFFA4004) // (AES) Mode Register +#define AT91C_AES_VR ((AT91_REG *) 0xFFFA40FC) // (AES) AES Version Register +#define AT91C_AES_ODATAxR ((AT91_REG *) 0xFFFA4050) // (AES) Output Data x Register +#define AT91C_AES_IDATAxR ((AT91_REG *) 0xFFFA4040) // (AES) Input Data x Register +#define AT91C_AES_CR ((AT91_REG *) 0xFFFA4000) // (AES) Control Register +#define AT91C_AES_IDR ((AT91_REG *) 0xFFFA4014) // (AES) Interrupt Disable Register +#define AT91C_AES_IMR ((AT91_REG *) 0xFFFA4018) // (AES) Interrupt Mask Register +#define AT91C_AES_IER ((AT91_REG *) 0xFFFA4010) // (AES) Interrupt Enable Register +#define AT91C_AES_KEYWxR ((AT91_REG *) 0xFFFA4020) // (AES) Key Word x Register +#define AT91C_AES_ISR ((AT91_REG *) 0xFFFA401C) // (AES) Interrupt Status Register +// ========== Register definition for PDC_TDES peripheral ========== +#define AT91C_TDES_RNCR ((AT91_REG *) 0xFFFA8114) // (PDC_TDES) Receive Next Counter Register +#define AT91C_TDES_TCR ((AT91_REG *) 0xFFFA810C) // (PDC_TDES) Transmit Counter Register +#define AT91C_TDES_RCR ((AT91_REG *) 0xFFFA8104) // (PDC_TDES) Receive Counter Register +#define AT91C_TDES_TNPR ((AT91_REG *) 0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register +#define AT91C_TDES_RNPR ((AT91_REG *) 0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register +#define AT91C_TDES_RPR ((AT91_REG *) 0xFFFA8100) // (PDC_TDES) Receive Pointer Register +#define AT91C_TDES_TNCR ((AT91_REG *) 0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register +#define AT91C_TDES_TPR ((AT91_REG *) 0xFFFA8108) // (PDC_TDES) Transmit Pointer Register +#define AT91C_TDES_PTSR ((AT91_REG *) 0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register +#define AT91C_TDES_PTCR ((AT91_REG *) 0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register +// ========== Register definition for TDES peripheral ========== +#define AT91C_TDES_KEY2WxR ((AT91_REG *) 0xFFFA8028) // (TDES) Key 2 Word x Register +#define AT91C_TDES_KEY3WxR ((AT91_REG *) 0xFFFA8030) // (TDES) Key 3 Word x Register +#define AT91C_TDES_IDR ((AT91_REG *) 0xFFFA8014) // (TDES) Interrupt Disable Register +#define AT91C_TDES_VR ((AT91_REG *) 0xFFFA80FC) // (TDES) TDES Version Register +#define AT91C_TDES_IVxR ((AT91_REG *) 0xFFFA8060) // (TDES) Initialization Vector x Register +#define AT91C_TDES_ODATAxR ((AT91_REG *) 0xFFFA8050) // (TDES) Output Data x Register +#define AT91C_TDES_IMR ((AT91_REG *) 0xFFFA8018) // (TDES) Interrupt Mask Register +#define AT91C_TDES_MR ((AT91_REG *) 0xFFFA8004) // (TDES) Mode Register +#define AT91C_TDES_CR ((AT91_REG *) 0xFFFA8000) // (TDES) Control Register +#define AT91C_TDES_IER ((AT91_REG *) 0xFFFA8010) // (TDES) Interrupt Enable Register +#define AT91C_TDES_ISR ((AT91_REG *) 0xFFFA801C) // (TDES) Interrupt Status Register +#define AT91C_TDES_IDATAxR ((AT91_REG *) 0xFFFA8040) // (TDES) Input Data x Register +#define AT91C_TDES_KEY1WxR ((AT91_REG *) 0xFFFA8020) // (TDES) Key 1 Word x Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data +#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data +#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data +#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock +#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_NPCS00 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 +#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_NPCS01 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_NPCS02 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1 +#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_NPCS03 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input +#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_MISO0 ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave +#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_MOSI0 ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave +#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_SPCK0 ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock +#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive +#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PA2_NPCS11 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit +#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync +#define AT91C_PA21_NPCS10 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 +#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock +#define AT91C_PA22_SPCK1 ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock +#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data +#define AT91C_PA23_MOSI1 ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave +#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data +#define AT91C_PA24_MISO1 ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave +#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock +#define AT91C_PA25_NPCS11 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync +#define AT91C_PA26_NPCS12 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data +#define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3 +#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data +#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input +#define AT91C_PA29_NPCS13 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send +#define AT91C_PA3_NPCS12 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0 +#define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send +#define AT91C_PA4_NPCS13 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data +#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data +#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock +#define AT91C_PA7_NPCS01 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send +#define AT91C_PA8_NPCS02 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send +#define AT91C_PA9_NPCS03 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0 +#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock +#define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1 +#define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable +#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10 +#define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 +#define AT91C_PB10_NPCS11 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11 +#define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 +#define AT91C_PB11_NPCS12 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12 +#define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error +#define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input +#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13 +#define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 +#define AT91C_PB13_NPCS01 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14 +#define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 +#define AT91C_PB14_NPCS02 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15 +#define AT91C_PB15_ERXDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid +#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16 +#define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected +#define AT91C_PB16_NPCS13 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17 +#define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock +#define AT91C_PB17_NPCS03 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18 +#define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec +#define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger +#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19 +#define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0 +#define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input +#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2 +#define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 +#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20 +#define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1 +#define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21 +#define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2 +#define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22 +#define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3 +#define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23 +#define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect +#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24 +#define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready +#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25 +#define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready +#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26 +#define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator +#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27 +#define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0 +#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28 +#define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1 +#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29 +#define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1 +#define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2 +#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3 +#define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 +#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30 +#define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2 +#define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3 +#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4 +#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid +#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5 +#define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 +#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6 +#define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 +#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7 +#define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error +#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8 +#define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock +#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9 +#define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral +#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A +#define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B +#define AT91C_ID_SPI0 ((unsigned int) 4) // Serial Peripheral Interface 0 +#define AT91C_ID_SPI1 ((unsigned int) 5) // Serial Peripheral Interface 1 +#define AT91C_ID_US0 ((unsigned int) 6) // USART 0 +#define AT91C_ID_US1 ((unsigned int) 7) // USART 1 +#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface +#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller +#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port +#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0 +#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1 +#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2 +#define AT91C_ID_CAN ((unsigned int) 15) // Control Area Network Controller +#define AT91C_ID_EMAC ((unsigned int) 16) // Ethernet MAC +#define AT91C_ID_ADC ((unsigned int) 17) // Analog-to-Digital Converter +#define AT91C_ID_AES ((unsigned int) 18) // Advanced Encryption Standard 128-bit +#define AT91C_ID_TDES ((unsigned int) 19) // Triple Data Encryption Standard +#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved +#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved +#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved +#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved +#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved +#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved +#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved +#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved +#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved +#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved +#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1) + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address +#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address +#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address +#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address +#define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address +#define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address +#define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address +#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address +#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_CAN_MB0 ((AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address +#define AT91C_BASE_CAN_MB1 ((AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address +#define AT91C_BASE_CAN_MB2 ((AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address +#define AT91C_BASE_CAN_MB3 ((AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address +#define AT91C_BASE_CAN_MB4 ((AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address +#define AT91C_BASE_CAN_MB5 ((AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address +#define AT91C_BASE_CAN_MB6 ((AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address +#define AT91C_BASE_CAN_MB7 ((AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address +#define AT91C_BASE_CAN ((AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address +#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address +#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address +#define AT91C_BASE_PDC_AES ((AT91PS_PDC) 0xFFFA4100) // (PDC_AES) Base Address +#define AT91C_BASE_AES ((AT91PS_AES) 0xFFFA4000) // (AES) Base Address +#define AT91C_BASE_PDC_TDES ((AT91PS_PDC) 0xFFFA8100) // (PDC_TDES) Base Address +#define AT91C_BASE_TDES ((AT91PS_TDES) 0xFFFA8000) // (TDES) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte) +#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address +#define AT91C_IFLASH_SIZE ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte) + + + +// - Hardware register definition + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR System Peripherals +// - ***************************************************************************** + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// - ***************************************************************************** +// - -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#if 0 /*_RB_*/ +AT91C_AIC_PRIOR EQU (0x7 << 0) ;- (AIC) Priority Level +AT91C_AIC_PRIOR_LOWEST EQU (0x0) ;- (AIC) Lowest priority level +AT91C_AIC_PRIOR_HIGHEST EQU (0x7) ;- (AIC) Highest priority level +AT91C_AIC_SRCTYPE EQU (0x3 << 5) ;- (AIC) Interrupt Source Type +AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL EQU (0x0 << 5) ;- (AIC) Internal Sources Code Label High-level Sensitive +AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL EQU (0x0 << 5) ;- (AIC) External Sources Code Label Low-level Sensitive +AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE EQU (0x1 << 5) ;- (AIC) Internal Sources Code Label Positive Edge triggered +AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE EQU (0x1 << 5) ;- (AIC) External Sources Code Label Negative Edge triggered +AT91C_AIC_SRCTYPE_HIGH_LEVEL EQU (0x2 << 5) ;- (AIC) Internal Or External Sources Code Label High-level Sensitive +AT91C_AIC_SRCTYPE_POSITIVE_EDGE EQU (0x3 << 5) ;- (AIC) Internal Or External Sources Code Label Positive Edge triggered +// - -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +AT91C_AIC_NFIQ EQU (0x1 << 0) ;- (AIC) NFIQ Status +AT91C_AIC_NIRQ EQU (0x1 << 1) ;- (AIC) NIRQ Status +// - -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +AT91C_AIC_DCR_PROT EQU (0x1 << 0) ;- (AIC) Protection Mode +AT91C_AIC_DCR_GMSK EQU (0x1 << 1) ;- (AIC) General Mask +#endif +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// - ***************************************************************************** +// - -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +AT91C_PDC_RXTEN EQU (0x1 << 0) ;- (PDC) Receiver Transfer Enable +AT91C_PDC_RXTDIS EQU (0x1 << 1) ;- (PDC) Receiver Transfer Disable +AT91C_PDC_TXTEN EQU (0x1 << 8) ;- (PDC) Transmitter Transfer Enable +AT91C_PDC_TXTDIS EQU (0x1 << 9) ;- (PDC) Transmitter Transfer Disable +// - -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Debug Unit +// - ***************************************************************************** +// - -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +AT91C_US_RSTRX EQU (0x1 << 2) ;- (DBGU) Reset Receiver +AT91C_US_RSTTX EQU (0x1 << 3) ;- (DBGU) Reset Transmitter +AT91C_US_RXEN EQU (0x1 << 4) ;- (DBGU) Receiver Enable +AT91C_US_RXDIS EQU (0x1 << 5) ;- (DBGU) Receiver Disable +AT91C_US_TXEN EQU (0x1 << 6) ;- (DBGU) Transmitter Enable +AT91C_US_TXDIS EQU (0x1 << 7) ;- (DBGU) Transmitter Disable +AT91C_US_RSTSTA EQU (0x1 << 8) ;- (DBGU) Reset Status Bits +// - -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +AT91C_US_PAR EQU (0x7 << 9) ;- (DBGU) Parity type +AT91C_US_PAR_EVEN EQU (0x0 << 9) ;- (DBGU) Even Parity +AT91C_US_PAR_ODD EQU (0x1 << 9) ;- (DBGU) Odd Parity +AT91C_US_PAR_SPACE EQU (0x2 << 9) ;- (DBGU) Parity forced to 0 (Space) +AT91C_US_PAR_MARK EQU (0x3 << 9) ;- (DBGU) Parity forced to 1 (Mark) +AT91C_US_PAR_NONE EQU (0x4 << 9) ;- (DBGU) No Parity +AT91C_US_PAR_MULTI_DROP EQU (0x6 << 9) ;- (DBGU) Multi-drop mode +AT91C_US_CHMODE EQU (0x3 << 14) ;- (DBGU) Channel Mode +AT91C_US_CHMODE_NORMAL EQU (0x0 << 14) ;- (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +AT91C_US_CHMODE_AUTO EQU (0x1 << 14) ;- (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +AT91C_US_CHMODE_LOCAL EQU (0x2 << 14) ;- (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +AT91C_US_CHMODE_REMOTE EQU (0x3 << 14) ;- (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// - -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +AT91C_US_RXRDY EQU (0x1 << 0) ;- (DBGU) RXRDY Interrupt +AT91C_US_TXRDY EQU (0x1 << 1) ;- (DBGU) TXRDY Interrupt +AT91C_US_ENDRX EQU (0x1 << 3) ;- (DBGU) End of Receive Transfer Interrupt +AT91C_US_ENDTX EQU (0x1 << 4) ;- (DBGU) End of Transmit Interrupt +AT91C_US_OVRE EQU (0x1 << 5) ;- (DBGU) Overrun Interrupt +AT91C_US_FRAME EQU (0x1 << 6) ;- (DBGU) Framing Error Interrupt +AT91C_US_PARE EQU (0x1 << 7) ;- (DBGU) Parity Error Interrupt +AT91C_US_TXEMPTY EQU (0x1 << 9) ;- (DBGU) TXEMPTY Interrupt +AT91C_US_TXBUFE EQU (0x1 << 11) ;- (DBGU) TXBUFE Interrupt +AT91C_US_RXBUFF EQU (0x1 << 12) ;- (DBGU) RXBUFF Interrupt +AT91C_US_COMM_TX EQU (0x1 << 30) ;- (DBGU) COMM_TX Interrupt +AT91C_US_COMM_RX EQU (0x1 << 31) ;- (DBGU) COMM_RX Interrupt +// - -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// - -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// - -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// - -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +AT91C_US_FORCE_NTRST EQU (0x1 << 0) ;- (DBGU) Force NTRST in JTAG + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// - ***************************************************************************** + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Clock Generator Controler +// - ***************************************************************************** +// - -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +AT91C_CKGR_MOSCEN EQU (0x1 << 0) ;- (CKGR) Main Oscillator Enable +AT91C_CKGR_OSCBYPASS EQU (0x1 << 1) ;- (CKGR) Main Oscillator Bypass +AT91C_CKGR_OSCOUNT EQU (0xFF << 8) ;- (CKGR) Main Oscillator Start-up Time +// - -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +AT91C_CKGR_MAINF EQU (0xFFFF << 0) ;- (CKGR) Main Clock Frequency +AT91C_CKGR_MAINRDY EQU (0x1 << 16) ;- (CKGR) Main Clock Ready +// - -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +AT91C_CKGR_DIV EQU (0xFF << 0) ;- (CKGR) Divider Selected +AT91C_CKGR_DIV_0 EQU (0x0) ;- (CKGR) Divider output is 0 +AT91C_CKGR_DIV_BYPASS EQU (0x1) ;- (CKGR) Divider is bypassed +AT91C_CKGR_PLLCOUNT EQU (0x3F << 8) ;- (CKGR) PLL Counter +AT91C_CKGR_OUT EQU (0x3 << 14) ;- (CKGR) PLL Output Frequency Range +AT91C_CKGR_OUT_0 EQU (0x0 << 14) ;- (CKGR) Please refer to the PLL datasheet +AT91C_CKGR_OUT_1 EQU (0x1 << 14) ;- (CKGR) Please refer to the PLL datasheet +AT91C_CKGR_OUT_2 EQU (0x2 << 14) ;- (CKGR) Please refer to the PLL datasheet +AT91C_CKGR_OUT_3 EQU (0x3 << 14) ;- (CKGR) Please refer to the PLL datasheet +AT91C_CKGR_MUL EQU (0x7FF << 16) ;- (CKGR) PLL Multiplier +AT91C_CKGR_USBDIV EQU (0x3 << 28) ;- (CKGR) Divider for USB Clocks +AT91C_CKGR_USBDIV_0 EQU (0x0 << 28) ;- (CKGR) Divider output is PLL clock output +AT91C_CKGR_USBDIV_1 EQU (0x1 << 28) ;- (CKGR) Divider output is PLL clock output divided by 2 +AT91C_CKGR_USBDIV_2 EQU (0x2 << 28) ;- (CKGR) Divider output is PLL clock output divided by 4 + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Power Management Controler +// - ***************************************************************************** +// - -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +AT91C_PMC_PCK EQU (0x1 << 0) ;- (PMC) Processor Clock +AT91C_PMC_UDP EQU (0x1 << 7) ;- (PMC) USB Device Port Clock +AT91C_PMC_PCK0 EQU (0x1 << 8) ;- (PMC) Programmable Clock Output +AT91C_PMC_PCK1 EQU (0x1 << 9) ;- (PMC) Programmable Clock Output +AT91C_PMC_PCK2 EQU (0x1 << 10) ;- (PMC) Programmable Clock Output +AT91C_PMC_PCK3 EQU (0x1 << 11) ;- (PMC) Programmable Clock Output +// - -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// - -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// - -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// - -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// - -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// - -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +AT91C_PMC_CSS EQU (0x3 << 0) ;- (PMC) Programmable Clock Selection +AT91C_PMC_CSS_SLOW_CLK EQU (0x0) ;- (PMC) Slow Clock is selected +AT91C_PMC_CSS_MAIN_CLK EQU (0x1) ;- (PMC) Main Clock is selected +AT91C_PMC_CSS_PLL_CLK EQU (0x3) ;- (PMC) Clock from PLL is selected +AT91C_PMC_PRES EQU (0x7 << 2) ;- (PMC) Programmable Clock Prescaler +AT91C_PMC_PRES_CLK EQU (0x0 << 2) ;- (PMC) Selected clock +AT91C_PMC_PRES_CLK_2 EQU (0x1 << 2) ;- (PMC) Selected clock divided by 2 +AT91C_PMC_PRES_CLK_4 EQU (0x2 << 2) ;- (PMC) Selected clock divided by 4 +AT91C_PMC_PRES_CLK_8 EQU (0x3 << 2) ;- (PMC) Selected clock divided by 8 +AT91C_PMC_PRES_CLK_16 EQU (0x4 << 2) ;- (PMC) Selected clock divided by 16 +AT91C_PMC_PRES_CLK_32 EQU (0x5 << 2) ;- (PMC) Selected clock divided by 32 +AT91C_PMC_PRES_CLK_64 EQU (0x6 << 2) ;- (PMC) Selected clock divided by 64 +// - -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// - -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +AT91C_PMC_MOSCS EQU (0x1 << 0) ;- (PMC) MOSC Status/Enable/Disable/Mask +AT91C_PMC_LOCK EQU (0x1 << 2) ;- (PMC) PLL Status/Enable/Disable/Mask +AT91C_PMC_MCKRDY EQU (0x1 << 3) ;- (PMC) MCK_RDY Status/Enable/Disable/Mask +AT91C_PMC_PCK0RDY EQU (0x1 << 8) ;- (PMC) PCK0_RDY Status/Enable/Disable/Mask +AT91C_PMC_PCK1RDY EQU (0x1 << 9) ;- (PMC) PCK1_RDY Status/Enable/Disable/Mask +AT91C_PMC_PCK2RDY EQU (0x1 << 10) ;- (PMC) PCK2_RDY Status/Enable/Disable/Mask +AT91C_PMC_PCK3RDY EQU (0x1 << 11) ;- (PMC) PCK3_RDY Status/Enable/Disable/Mask +// - -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// - -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// - -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Reset Controller Interface +// - ***************************************************************************** +// - -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +AT91C_RSTC_PROCRST EQU (0x1 << 0) ;- (RSTC) Processor Reset +AT91C_RSTC_PERRST EQU (0x1 << 2) ;- (RSTC) Peripheral Reset +AT91C_RSTC_EXTRST EQU (0x1 << 3) ;- (RSTC) External Reset +AT91C_RSTC_KEY EQU (0xFF << 24) ;- (RSTC) Password +// - -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +AT91C_RSTC_URSTS EQU (0x1 << 0) ;- (RSTC) User Reset Status +AT91C_RSTC_BODSTS EQU (0x1 << 1) ;- (RSTC) Brownout Detection Status +AT91C_RSTC_RSTTYP EQU (0x7 << 8) ;- (RSTC) Reset Type +AT91C_RSTC_RSTTYP_POWERUP EQU (0x0 << 8) ;- (RSTC) Power-up Reset. VDDCORE rising. +AT91C_RSTC_RSTTYP_WAKEUP EQU (0x1 << 8) ;- (RSTC) WakeUp Reset. VDDCORE rising. +AT91C_RSTC_RSTTYP_WATCHDOG EQU (0x2 << 8) ;- (RSTC) Watchdog Reset. Watchdog overflow occured. +AT91C_RSTC_RSTTYP_SOFTWARE EQU (0x3 << 8) ;- (RSTC) Software Reset. Processor reset required by the software. +AT91C_RSTC_RSTTYP_USER EQU (0x4 << 8) ;- (RSTC) User Reset. NRST pin detected low. +AT91C_RSTC_RSTTYP_BROWNOUT EQU (0x5 << 8) ;- (RSTC) Brownout Reset occured. +AT91C_RSTC_NRSTL EQU (0x1 << 16) ;- (RSTC) NRST pin level +AT91C_RSTC_SRCMP EQU (0x1 << 17) ;- (RSTC) Software Reset Command in Progress. +// - -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +AT91C_RSTC_URSTEN EQU (0x1 << 0) ;- (RSTC) User Reset Enable +AT91C_RSTC_URSTIEN EQU (0x1 << 4) ;- (RSTC) User Reset Interrupt Enable +AT91C_RSTC_ERSTL EQU (0xF << 8) ;- (RSTC) User Reset Enable +AT91C_RSTC_BODIEN EQU (0x1 << 16) ;- (RSTC) Brownout Detection Interrupt Enable + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// - ***************************************************************************** +// - -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +AT91C_RTTC_RTPRES EQU (0xFFFF << 0) ;- (RTTC) Real-time Timer Prescaler Value +AT91C_RTTC_ALMIEN EQU (0x1 << 16) ;- (RTTC) Alarm Interrupt Enable +AT91C_RTTC_RTTINCIEN EQU (0x1 << 17) ;- (RTTC) Real Time Timer Increment Interrupt Enable +AT91C_RTTC_RTTRST EQU (0x1 << 18) ;- (RTTC) Real Time Timer Restart +// - -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +AT91C_RTTC_ALMV EQU (0x0 << 0) ;- (RTTC) Alarm Value +// - -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +AT91C_RTTC_CRTV EQU (0x0 << 0) ;- (RTTC) Current Real-time Value +// - -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +AT91C_RTTC_ALMS EQU (0x1 << 0) ;- (RTTC) Real-time Alarm Status +AT91C_RTTC_RTTINC EQU (0x1 << 1) ;- (RTTC) Real-time Timer Increment + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// - ***************************************************************************** +// - -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +AT91C_PITC_PIV EQU (0xFFFFF << 0) ;- (PITC) Periodic Interval Value +AT91C_PITC_PITEN EQU (0x1 << 24) ;- (PITC) Periodic Interval Timer Enabled +AT91C_PITC_PITIEN EQU (0x1 << 25) ;- (PITC) Periodic Interval Timer Interrupt Enable +// - -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +AT91C_PITC_PITS EQU (0x1 << 0) ;- (PITC) Periodic Interval Timer Status +// - -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +AT91C_PITC_CPIV EQU (0xFFFFF << 0) ;- (PITC) Current Periodic Interval Value +AT91C_PITC_PICNT EQU (0xFFF << 20) ;- (PITC) Periodic Interval Counter +// - -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// - ***************************************************************************** +// - -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +AT91C_WDTC_WDRSTT EQU (0x1 << 0) ;- (WDTC) Watchdog Restart +AT91C_WDTC_KEY EQU (0xFF << 24) ;- (WDTC) Watchdog KEY Password +// - -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +AT91C_WDTC_WDV EQU (0xFFF << 0) ;- (WDTC) Watchdog Timer Restart +AT91C_WDTC_WDFIEN EQU (0x1 << 12) ;- (WDTC) Watchdog Fault Interrupt Enable +AT91C_WDTC_WDRSTEN EQU (0x1 << 13) ;- (WDTC) Watchdog Reset Enable +AT91C_WDTC_WDRPROC EQU (0x1 << 14) ;- (WDTC) Watchdog Timer Restart +AT91C_WDTC_WDDIS EQU (0x1 << 15) ;- (WDTC) Watchdog Disable +AT91C_WDTC_WDD EQU (0xFFF << 16) ;- (WDTC) Watchdog Delta Value +AT91C_WDTC_WDDBGHLT EQU (0x1 << 28) ;- (WDTC) Watchdog Debug Halt +AT91C_WDTC_WDIDLEHLT EQU (0x1 << 29) ;- (WDTC) Watchdog Idle Halt +// - -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +AT91C_WDTC_WDUNF EQU (0x1 << 0) ;- (WDTC) Watchdog Underflow +AT91C_WDTC_WDERR EQU (0x1 << 1) ;- (WDTC) Watchdog Error + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface +// - ***************************************************************************** +// - -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- +AT91C_VREG_PSTDBY EQU (0x1 << 0) ;- (VREG) Voltage Regulator Power Standby Mode + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Memory Controller Interface +// - ***************************************************************************** +// - -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +AT91C_MC_RCB EQU (0x1 << 0) ;- (MC) Remap Command Bit +// - -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +AT91C_MC_UNDADD EQU (0x1 << 0) ;- (MC) Undefined Addess Abort Status +AT91C_MC_MISADD EQU (0x1 << 1) ;- (MC) Misaligned Addess Abort Status +AT91C_MC_ABTSZ EQU (0x3 << 8) ;- (MC) Abort Size Status +AT91C_MC_ABTSZ_BYTE EQU (0x0 << 8) ;- (MC) Byte +AT91C_MC_ABTSZ_HWORD EQU (0x1 << 8) ;- (MC) Half-word +AT91C_MC_ABTSZ_WORD EQU (0x2 << 8) ;- (MC) Word +AT91C_MC_ABTTYP EQU (0x3 << 10) ;- (MC) Abort Type Status +AT91C_MC_ABTTYP_DATAR EQU (0x0 << 10) ;- (MC) Data Read +AT91C_MC_ABTTYP_DATAW EQU (0x1 << 10) ;- (MC) Data Write +AT91C_MC_ABTTYP_FETCH EQU (0x2 << 10) ;- (MC) Code Fetch +AT91C_MC_MST0 EQU (0x1 << 16) ;- (MC) Master 0 Abort Source +AT91C_MC_MST1 EQU (0x1 << 17) ;- (MC) Master 1 Abort Source +AT91C_MC_SVMST0 EQU (0x1 << 24) ;- (MC) Saved Master 0 Abort Source +AT91C_MC_SVMST1 EQU (0x1 << 25) ;- (MC) Saved Master 1 Abort Source +// - -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +AT91C_MC_FRDY EQU (0x1 << 0) ;- (MC) Flash Ready +AT91C_MC_LOCKE EQU (0x1 << 2) ;- (MC) Lock Error +AT91C_MC_PROGE EQU (0x1 << 3) ;- (MC) Programming Error +AT91C_MC_NEBP EQU (0x1 << 7) ;- (MC) No Erase Before Programming +AT91C_MC_FWS EQU (0x3 << 8) ;- (MC) Flash Wait State +AT91C_MC_FWS_0FWS EQU (0x0 << 8) ;- (MC) 1 cycle for Read, 2 for Write operations +AT91C_MC_FWS_1FWS EQU (0x1 << 8) ;- (MC) 2 cycles for Read, 3 for Write operations +AT91C_MC_FWS_2FWS EQU (0x2 << 8) ;- (MC) 3 cycles for Read, 4 for Write operations +AT91C_MC_FWS_3FWS EQU (0x3 << 8) ;- (MC) 4 cycles for Read, 4 for Write operations +AT91C_MC_FMCN EQU (0xFF << 16) ;- (MC) Flash Microsecond Cycle Number +// - -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +AT91C_MC_FCMD EQU (0xF << 0) ;- (MC) Flash Command +AT91C_MC_FCMD_START_PROG EQU (0x1) ;- (MC) Starts the programming of th epage specified by PAGEN. +AT91C_MC_FCMD_LOCK EQU (0x2) ;- (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +AT91C_MC_FCMD_PROG_AND_LOCK EQU (0x3) ;- (MC) The lock sequence automatically happens after the programming sequence is completed. +AT91C_MC_FCMD_UNLOCK EQU (0x4) ;- (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +AT91C_MC_FCMD_ERASE_ALL EQU (0x8) ;- (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +AT91C_MC_FCMD_SET_GP_NVM EQU (0xB) ;- (MC) Set General Purpose NVM bits. +AT91C_MC_FCMD_CLR_GP_NVM EQU (0xD) ;- (MC) Clear General Purpose NVM bits. +AT91C_MC_FCMD_SET_SECURITY EQU (0xF) ;- (MC) Set Security Bit. +AT91C_MC_PAGEN EQU (0x3FF << 8) ;- (MC) Page Number +AT91C_MC_KEY EQU (0xFF << 24) ;- (MC) Writing Protect Key +// - -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- +AT91C_MC_SECURITY EQU (0x1 << 4) ;- (MC) Security Bit Status +AT91C_MC_GPNVM0 EQU (0x1 << 8) ;- (MC) Sector 0 Lock Status +AT91C_MC_GPNVM1 EQU (0x1 << 9) ;- (MC) Sector 1 Lock Status +AT91C_MC_GPNVM2 EQU (0x1 << 10) ;- (MC) Sector 2 Lock Status +AT91C_MC_GPNVM3 EQU (0x1 << 11) ;- (MC) Sector 3 Lock Status +AT91C_MC_GPNVM4 EQU (0x1 << 12) ;- (MC) Sector 4 Lock Status +AT91C_MC_GPNVM5 EQU (0x1 << 13) ;- (MC) Sector 5 Lock Status +AT91C_MC_GPNVM6 EQU (0x1 << 14) ;- (MC) Sector 6 Lock Status +AT91C_MC_GPNVM7 EQU (0x1 << 15) ;- (MC) Sector 7 Lock Status +AT91C_MC_LOCKS0 EQU (0x1 << 16) ;- (MC) Sector 0 Lock Status +AT91C_MC_LOCKS1 EQU (0x1 << 17) ;- (MC) Sector 1 Lock Status +AT91C_MC_LOCKS2 EQU (0x1 << 18) ;- (MC) Sector 2 Lock Status +AT91C_MC_LOCKS3 EQU (0x1 << 19) ;- (MC) Sector 3 Lock Status +AT91C_MC_LOCKS4 EQU (0x1 << 20) ;- (MC) Sector 4 Lock Status +AT91C_MC_LOCKS5 EQU (0x1 << 21) ;- (MC) Sector 5 Lock Status +AT91C_MC_LOCKS6 EQU (0x1 << 22) ;- (MC) Sector 6 Lock Status +AT91C_MC_LOCKS7 EQU (0x1 << 23) ;- (MC) Sector 7 Lock Status +AT91C_MC_LOCKS8 EQU (0x1 << 24) ;- (MC) Sector 8 Lock Status +AT91C_MC_LOCKS9 EQU (0x1 << 25) ;- (MC) Sector 9 Lock Status +AT91C_MC_LOCKS10 EQU (0x1 << 26) ;- (MC) Sector 10 Lock Status +AT91C_MC_LOCKS11 EQU (0x1 << 27) ;- (MC) Sector 11 Lock Status +AT91C_MC_LOCKS12 EQU (0x1 << 28) ;- (MC) Sector 12 Lock Status +AT91C_MC_LOCKS13 EQU (0x1 << 29) ;- (MC) Sector 13 Lock Status +AT91C_MC_LOCKS14 EQU (0x1 << 30) ;- (MC) Sector 14 Lock Status +AT91C_MC_LOCKS15 EQU (0x1 << 31) ;- (MC) Sector 15 Lock Status + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Serial Parallel Interface +// - ***************************************************************************** +// - -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +AT91C_SPI_SPIEN EQU (0x1 << 0) ;- (SPI) SPI Enable +AT91C_SPI_SPIDIS EQU (0x1 << 1) ;- (SPI) SPI Disable +AT91C_SPI_SWRST EQU (0x1 << 7) ;- (SPI) SPI Software reset +AT91C_SPI_LASTXFER EQU (0x1 << 24) ;- (SPI) SPI Last Transfer +// - -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +AT91C_SPI_MSTR EQU (0x1 << 0) ;- (SPI) Master/Slave Mode +AT91C_SPI_PS EQU (0x1 << 1) ;- (SPI) Peripheral Select +AT91C_SPI_PS_FIXED EQU (0x0 << 1) ;- (SPI) Fixed Peripheral Select +AT91C_SPI_PS_VARIABLE EQU (0x1 << 1) ;- (SPI) Variable Peripheral Select +AT91C_SPI_PCSDEC EQU (0x1 << 2) ;- (SPI) Chip Select Decode +AT91C_SPI_FDIV EQU (0x1 << 3) ;- (SPI) Clock Selection +AT91C_SPI_MODFDIS EQU (0x1 << 4) ;- (SPI) Mode Fault Detection +AT91C_SPI_LLB EQU (0x1 << 7) ;- (SPI) Clock Selection +AT91C_SPI_PCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select +AT91C_SPI_DLYBCS EQU (0xFF << 24) ;- (SPI) Delay Between Chip Selects +// - -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +AT91C_SPI_RD EQU (0xFFFF << 0) ;- (SPI) Receive Data +AT91C_SPI_RPCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status +// - -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +AT91C_SPI_TD EQU (0xFFFF << 0) ;- (SPI) Transmit Data +AT91C_SPI_TPCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status +// - -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +AT91C_SPI_RDRF EQU (0x1 << 0) ;- (SPI) Receive Data Register Full +AT91C_SPI_TDRE EQU (0x1 << 1) ;- (SPI) Transmit Data Register Empty +AT91C_SPI_MODF EQU (0x1 << 2) ;- (SPI) Mode Fault Error +AT91C_SPI_OVRES EQU (0x1 << 3) ;- (SPI) Overrun Error Status +AT91C_SPI_ENDRX EQU (0x1 << 4) ;- (SPI) End of Receiver Transfer +AT91C_SPI_ENDTX EQU (0x1 << 5) ;- (SPI) End of Receiver Transfer +AT91C_SPI_RXBUFF EQU (0x1 << 6) ;- (SPI) RXBUFF Interrupt +AT91C_SPI_TXBUFE EQU (0x1 << 7) ;- (SPI) TXBUFE Interrupt +AT91C_SPI_NSSR EQU (0x1 << 8) ;- (SPI) NSSR Interrupt +AT91C_SPI_TXEMPTY EQU (0x1 << 9) ;- (SPI) TXEMPTY Interrupt +AT91C_SPI_SPIENS EQU (0x1 << 16) ;- (SPI) Enable Status +// - -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// - -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// - -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// - -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +AT91C_SPI_CPOL EQU (0x1 << 0) ;- (SPI) Clock Polarity +AT91C_SPI_NCPHA EQU (0x1 << 1) ;- (SPI) Clock Phase +AT91C_SPI_CSAAT EQU (0x1 << 3) ;- (SPI) Chip Select Active After Transfer +AT91C_SPI_BITS EQU (0xF << 4) ;- (SPI) Bits Per Transfer +AT91C_SPI_BITS_8 EQU (0x0 << 4) ;- (SPI) 8 Bits Per transfer +AT91C_SPI_BITS_9 EQU (0x1 << 4) ;- (SPI) 9 Bits Per transfer +AT91C_SPI_BITS_10 EQU (0x2 << 4) ;- (SPI) 10 Bits Per transfer +AT91C_SPI_BITS_11 EQU (0x3 << 4) ;- (SPI) 11 Bits Per transfer +AT91C_SPI_BITS_12 EQU (0x4 << 4) ;- (SPI) 12 Bits Per transfer +AT91C_SPI_BITS_13 EQU (0x5 << 4) ;- (SPI) 13 Bits Per transfer +AT91C_SPI_BITS_14 EQU (0x6 << 4) ;- (SPI) 14 Bits Per transfer +AT91C_SPI_BITS_15 EQU (0x7 << 4) ;- (SPI) 15 Bits Per transfer +AT91C_SPI_BITS_16 EQU (0x8 << 4) ;- (SPI) 16 Bits Per transfer +AT91C_SPI_SCBR EQU (0xFF << 8) ;- (SPI) Serial Clock Baud Rate +AT91C_SPI_DLYBS EQU (0xFF << 16) ;- (SPI) Delay Before SPCK +AT91C_SPI_DLYBCT EQU (0xFF << 24) ;- (SPI) Delay Between Consecutive Transfers + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Usart +// - ***************************************************************************** +// - -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +AT91C_US_STTBRK EQU (0x1 << 9) ;- (USART) Start Break +AT91C_US_STPBRK EQU (0x1 << 10) ;- (USART) Stop Break +AT91C_US_STTTO EQU (0x1 << 11) ;- (USART) Start Time-out +AT91C_US_SENDA EQU (0x1 << 12) ;- (USART) Send Address +AT91C_US_RSTIT EQU (0x1 << 13) ;- (USART) Reset Iterations +AT91C_US_RSTNACK EQU (0x1 << 14) ;- (USART) Reset Non Acknowledge +AT91C_US_RETTO EQU (0x1 << 15) ;- (USART) Rearm Time-out +AT91C_US_DTREN EQU (0x1 << 16) ;- (USART) Data Terminal ready Enable +AT91C_US_DTRDIS EQU (0x1 << 17) ;- (USART) Data Terminal ready Disable +AT91C_US_RTSEN EQU (0x1 << 18) ;- (USART) Request to Send enable +AT91C_US_RTSDIS EQU (0x1 << 19) ;- (USART) Request to Send Disable +// - -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +AT91C_US_USMODE EQU (0xF << 0) ;- (USART) Usart mode +AT91C_US_USMODE_NORMAL EQU (0x0) ;- (USART) Normal +AT91C_US_USMODE_RS485 EQU (0x1) ;- (USART) RS485 +AT91C_US_USMODE_HWHSH EQU (0x2) ;- (USART) Hardware Handshaking +AT91C_US_USMODE_MODEM EQU (0x3) ;- (USART) Modem +AT91C_US_USMODE_ISO7816_0 EQU (0x4) ;- (USART) ISO7816 protocol: T = 0 +AT91C_US_USMODE_ISO7816_1 EQU (0x6) ;- (USART) ISO7816 protocol: T = 1 +AT91C_US_USMODE_IRDA EQU (0x8) ;- (USART) IrDA +AT91C_US_USMODE_SWHSH EQU (0xC) ;- (USART) Software Handshaking +AT91C_US_CLKS EQU (0x3 << 4) ;- (USART) Clock Selection (Baud Rate generator Input Clock +AT91C_US_CLKS_CLOCK EQU (0x0 << 4) ;- (USART) Clock +AT91C_US_CLKS_FDIV1 EQU (0x1 << 4) ;- (USART) fdiv1 +AT91C_US_CLKS_SLOW EQU (0x2 << 4) ;- (USART) slow_clock (ARM) +AT91C_US_CLKS_EXT EQU (0x3 << 4) ;- (USART) External (SCK) +AT91C_US_CHRL EQU (0x3 << 6) ;- (USART) Clock Selection (Baud Rate generator Input Clock +AT91C_US_CHRL_5_BITS EQU (0x0 << 6) ;- (USART) Character Length: 5 bits +AT91C_US_CHRL_6_BITS EQU (0x1 << 6) ;- (USART) Character Length: 6 bits +AT91C_US_CHRL_7_BITS EQU (0x2 << 6) ;- (USART) Character Length: 7 bits +AT91C_US_CHRL_8_BITS EQU (0x3 << 6) ;- (USART) Character Length: 8 bits +AT91C_US_SYNC EQU (0x1 << 8) ;- (USART) Synchronous Mode Select +AT91C_US_NBSTOP EQU (0x3 << 12) ;- (USART) Number of Stop bits +AT91C_US_NBSTOP_1_BIT EQU (0x0 << 12) ;- (USART) 1 stop bit +AT91C_US_NBSTOP_15_BIT EQU (0x1 << 12) ;- (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +AT91C_US_NBSTOP_2_BIT EQU (0x2 << 12) ;- (USART) 2 stop bits +AT91C_US_MSBF EQU (0x1 << 16) ;- (USART) Bit Order +AT91C_US_MODE9 EQU (0x1 << 17) ;- (USART) 9-bit Character length +AT91C_US_CKLO EQU (0x1 << 18) ;- (USART) Clock Output Select +AT91C_US_OVER EQU (0x1 << 19) ;- (USART) Over Sampling Mode +AT91C_US_INACK EQU (0x1 << 20) ;- (USART) Inhibit Non Acknowledge +AT91C_US_DSNACK EQU (0x1 << 21) ;- (USART) Disable Successive NACK +AT91C_US_MAX_ITER EQU (0x1 << 24) ;- (USART) Number of Repetitions +AT91C_US_FILTER EQU (0x1 << 28) ;- (USART) Receive Line Filter +// - -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +AT91C_US_RXBRK EQU (0x1 << 2) ;- (USART) Break Received/End of Break +AT91C_US_TIMEOUT EQU (0x1 << 8) ;- (USART) Receiver Time-out +AT91C_US_ITERATION EQU (0x1 << 10) ;- (USART) Max number of Repetitions Reached +AT91C_US_NACK EQU (0x1 << 13) ;- (USART) Non Acknowledge +AT91C_US_RIIC EQU (0x1 << 16) ;- (USART) Ring INdicator Input Change Flag +AT91C_US_DSRIC EQU (0x1 << 17) ;- (USART) Data Set Ready Input Change Flag +AT91C_US_DCDIC EQU (0x1 << 18) ;- (USART) Data Carrier Flag +AT91C_US_CTSIC EQU (0x1 << 19) ;- (USART) Clear To Send Input Change Flag +// - -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// - -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// - -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +AT91C_US_RI EQU (0x1 << 20) ;- (USART) Image of RI Input +AT91C_US_DSR EQU (0x1 << 21) ;- (USART) Image of DSR Input +AT91C_US_DCD EQU (0x1 << 22) ;- (USART) Image of DCD Input +AT91C_US_CTS EQU (0x1 << 23) ;- (USART) Image of CTS Input + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// - ***************************************************************************** +// - -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +AT91C_SSC_RXEN EQU (0x1 << 0) ;- (SSC) Receive Enable +AT91C_SSC_RXDIS EQU (0x1 << 1) ;- (SSC) Receive Disable +AT91C_SSC_TXEN EQU (0x1 << 8) ;- (SSC) Transmit Enable +AT91C_SSC_TXDIS EQU (0x1 << 9) ;- (SSC) Transmit Disable +AT91C_SSC_SWRST EQU (0x1 << 15) ;- (SSC) Software Reset +// - -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +AT91C_SSC_CKS EQU (0x3 << 0) ;- (SSC) Receive/Transmit Clock Selection +AT91C_SSC_CKS_DIV EQU (0x0) ;- (SSC) Divided Clock +AT91C_SSC_CKS_TK EQU (0x1) ;- (SSC) TK Clock signal +AT91C_SSC_CKS_RK EQU (0x2) ;- (SSC) RK pin +AT91C_SSC_CKO EQU (0x7 << 2) ;- (SSC) Receive/Transmit Clock Output Mode Selection +AT91C_SSC_CKO_NONE EQU (0x0 << 2) ;- (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +AT91C_SSC_CKO_CONTINOUS EQU (0x1 << 2) ;- (SSC) Continuous Receive/Transmit Clock RK pin: Output +AT91C_SSC_CKO_DATA_TX EQU (0x2 << 2) ;- (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +AT91C_SSC_CKI EQU (0x1 << 5) ;- (SSC) Receive/Transmit Clock Inversion +AT91C_SSC_START EQU (0xF << 8) ;- (SSC) Receive/Transmit Start Selection +AT91C_SSC_START_CONTINOUS EQU (0x0 << 8) ;- (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +AT91C_SSC_START_TX EQU (0x1 << 8) ;- (SSC) Transmit/Receive start +AT91C_SSC_START_LOW_RF EQU (0x2 << 8) ;- (SSC) Detection of a low level on RF input +AT91C_SSC_START_HIGH_RF EQU (0x3 << 8) ;- (SSC) Detection of a high level on RF input +AT91C_SSC_START_FALL_RF EQU (0x4 << 8) ;- (SSC) Detection of a falling edge on RF input +AT91C_SSC_START_RISE_RF EQU (0x5 << 8) ;- (SSC) Detection of a rising edge on RF input +AT91C_SSC_START_LEVEL_RF EQU (0x6 << 8) ;- (SSC) Detection of any level change on RF input +AT91C_SSC_START_EDGE_RF EQU (0x7 << 8) ;- (SSC) Detection of any edge on RF input +AT91C_SSC_START_0 EQU (0x8 << 8) ;- (SSC) Compare 0 +AT91C_SSC_STTDLY EQU (0xFF << 16) ;- (SSC) Receive/Transmit Start Delay +AT91C_SSC_PERIOD EQU (0xFF << 24) ;- (SSC) Receive/Transmit Period Divider Selection +// - -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +AT91C_SSC_DATLEN EQU (0x1F << 0) ;- (SSC) Data Length +AT91C_SSC_LOOP EQU (0x1 << 5) ;- (SSC) Loop Mode +AT91C_SSC_MSBF EQU (0x1 << 7) ;- (SSC) Most Significant Bit First +AT91C_SSC_DATNB EQU (0xF << 8) ;- (SSC) Data Number per Frame +AT91C_SSC_FSLEN EQU (0xF << 16) ;- (SSC) Receive/Transmit Frame Sync length +AT91C_SSC_FSOS EQU (0x7 << 20) ;- (SSC) Receive/Transmit Frame Sync Output Selection +AT91C_SSC_FSOS_NONE EQU (0x0 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +AT91C_SSC_FSOS_NEGATIVE EQU (0x1 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +AT91C_SSC_FSOS_POSITIVE EQU (0x2 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +AT91C_SSC_FSOS_LOW EQU (0x3 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +AT91C_SSC_FSOS_HIGH EQU (0x4 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +AT91C_SSC_FSOS_TOGGLE EQU (0x5 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +AT91C_SSC_FSEDGE EQU (0x1 << 24) ;- (SSC) Frame Sync Edge Detection +// - -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// - -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +AT91C_SSC_DATDEF EQU (0x1 << 5) ;- (SSC) Data Default Value +AT91C_SSC_FSDEN EQU (0x1 << 23) ;- (SSC) Frame Sync Data Enable +// - -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +AT91C_SSC_TXRDY EQU (0x1 << 0) ;- (SSC) Transmit Ready +AT91C_SSC_TXEMPTY EQU (0x1 << 1) ;- (SSC) Transmit Empty +AT91C_SSC_ENDTX EQU (0x1 << 2) ;- (SSC) End Of Transmission +AT91C_SSC_TXBUFE EQU (0x1 << 3) ;- (SSC) Transmit Buffer Empty +AT91C_SSC_RXRDY EQU (0x1 << 4) ;- (SSC) Receive Ready +AT91C_SSC_OVRUN EQU (0x1 << 5) ;- (SSC) Receive Overrun +AT91C_SSC_ENDRX EQU (0x1 << 6) ;- (SSC) End of Reception +AT91C_SSC_RXBUFF EQU (0x1 << 7) ;- (SSC) Receive Buffer Full +AT91C_SSC_TXSYN EQU (0x1 << 10) ;- (SSC) Transmit Sync +AT91C_SSC_RXSYN EQU (0x1 << 11) ;- (SSC) Receive Sync +AT91C_SSC_TXENA EQU (0x1 << 16) ;- (SSC) Transmit Enable +AT91C_SSC_RXENA EQU (0x1 << 17) ;- (SSC) Receive Enable +// - -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// - -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// - -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Two-wire Interface +// - ***************************************************************************** +// - -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +AT91C_TWI_START EQU (0x1 << 0) ;- (TWI) Send a START Condition +AT91C_TWI_STOP EQU (0x1 << 1) ;- (TWI) Send a STOP Condition +AT91C_TWI_MSEN EQU (0x1 << 2) ;- (TWI) TWI Master Transfer Enabled +AT91C_TWI_MSDIS EQU (0x1 << 3) ;- (TWI) TWI Master Transfer Disabled +AT91C_TWI_SWRST EQU (0x1 << 7) ;- (TWI) Software Reset +// - -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +AT91C_TWI_IADRSZ EQU (0x3 << 8) ;- (TWI) Internal Device Address Size +AT91C_TWI_IADRSZ_NO EQU (0x0 << 8) ;- (TWI) No internal device address +AT91C_TWI_IADRSZ_1_BYTE EQU (0x1 << 8) ;- (TWI) One-byte internal device address +AT91C_TWI_IADRSZ_2_BYTE EQU (0x2 << 8) ;- (TWI) Two-byte internal device address +AT91C_TWI_IADRSZ_3_BYTE EQU (0x3 << 8) ;- (TWI) Three-byte internal device address +AT91C_TWI_MREAD EQU (0x1 << 12) ;- (TWI) Master Read Direction +AT91C_TWI_DADR EQU (0x7F << 16) ;- (TWI) Device Address +// - -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +AT91C_TWI_CLDIV EQU (0xFF << 0) ;- (TWI) Clock Low Divider +AT91C_TWI_CHDIV EQU (0xFF << 8) ;- (TWI) Clock High Divider +AT91C_TWI_CKDIV EQU (0x7 << 16) ;- (TWI) Clock Divider +// - -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +AT91C_TWI_TXCOMP EQU (0x1 << 0) ;- (TWI) Transmission Completed +AT91C_TWI_RXRDY EQU (0x1 << 1) ;- (TWI) Receive holding register ReaDY +AT91C_TWI_TXRDY EQU (0x1 << 2) ;- (TWI) Transmit holding register ReaDY +AT91C_TWI_OVRE EQU (0x1 << 6) ;- (TWI) Overrun Error +AT91C_TWI_UNRE EQU (0x1 << 7) ;- (TWI) Underrun Error +AT91C_TWI_NACK EQU (0x1 << 8) ;- (TWI) Not Acknowledged +// - -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// - -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// - -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR PWMC Channel Interface +// - ***************************************************************************** +// - -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +AT91C_PWMC_CPRE EQU (0xF << 0) ;- (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +AT91C_PWMC_CPRE_MCK EQU (0x0) ;- (PWMC_CH) +AT91C_PWMC_CPRE_MCKA EQU (0xB) ;- (PWMC_CH) +AT91C_PWMC_CPRE_MCKB EQU (0xC) ;- (PWMC_CH) +AT91C_PWMC_CALG EQU (0x1 << 8) ;- (PWMC_CH) Channel Alignment +AT91C_PWMC_CPOL EQU (0x1 << 9) ;- (PWMC_CH) Channel Polarity +AT91C_PWMC_CPD EQU (0x1 << 10) ;- (PWMC_CH) Channel Update Period +// - -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +AT91C_PWMC_CDTY EQU (0x0 << 0) ;- (PWMC_CH) Channel Duty Cycle +// - -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +AT91C_PWMC_CPRD EQU (0x0 << 0) ;- (PWMC_CH) Channel Period +// - -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +AT91C_PWMC_CCNT EQU (0x0 << 0) ;- (PWMC_CH) Channel Counter +// - -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +AT91C_PWMC_CUPD EQU (0x0 << 0) ;- (PWMC_CH) Channel Update + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// - ***************************************************************************** +// - -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +AT91C_PWMC_DIVA EQU (0xFF << 0) ;- (PWMC) CLKA divide factor. +AT91C_PWMC_PREA EQU (0xF << 8) ;- (PWMC) Divider Input Clock Prescaler A +AT91C_PWMC_PREA_MCK EQU (0x0 << 8) ;- (PWMC) +AT91C_PWMC_DIVB EQU (0xFF << 16) ;- (PWMC) CLKB divide factor. +AT91C_PWMC_PREB EQU (0xF << 24) ;- (PWMC) Divider Input Clock Prescaler B +AT91C_PWMC_PREB_MCK EQU (0x0 << 24) ;- (PWMC) +// - -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +AT91C_PWMC_CHID0 EQU (0x1 << 0) ;- (PWMC) Channel ID 0 +AT91C_PWMC_CHID1 EQU (0x1 << 1) ;- (PWMC) Channel ID 1 +AT91C_PWMC_CHID2 EQU (0x1 << 2) ;- (PWMC) Channel ID 2 +AT91C_PWMC_CHID3 EQU (0x1 << 3) ;- (PWMC) Channel ID 3 +// - -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// - -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// - -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// - -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// - -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// - -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR USB Device Interface +// - ***************************************************************************** +// - -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +AT91C_UDP_FRM_NUM EQU (0x7FF << 0) ;- (UDP) Frame Number as Defined in the Packet Field Formats +AT91C_UDP_FRM_ERR EQU (0x1 << 16) ;- (UDP) Frame Error +AT91C_UDP_FRM_OK EQU (0x1 << 17) ;- (UDP) Frame OK +// - -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +AT91C_UDP_FADDEN EQU (0x1 << 0) ;- (UDP) Function Address Enable +AT91C_UDP_CONFG EQU (0x1 << 1) ;- (UDP) Configured +AT91C_UDP_ESR EQU (0x1 << 2) ;- (UDP) Enable Send Resume +AT91C_UDP_RSMINPR EQU (0x1 << 3) ;- (UDP) A Resume Has Been Sent to the Host +AT91C_UDP_RMWUPE EQU (0x1 << 4) ;- (UDP) Remote Wake Up Enable +// - -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +AT91C_UDP_FADD EQU (0xFF << 0) ;- (UDP) Function Address Value +AT91C_UDP_FEN EQU (0x1 << 8) ;- (UDP) Function Enable +// - -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +AT91C_UDP_EPINT0 EQU (0x1 << 0) ;- (UDP) Endpoint 0 Interrupt +AT91C_UDP_EPINT1 EQU (0x1 << 1) ;- (UDP) Endpoint 0 Interrupt +AT91C_UDP_EPINT2 EQU (0x1 << 2) ;- (UDP) Endpoint 2 Interrupt +AT91C_UDP_EPINT3 EQU (0x1 << 3) ;- (UDP) Endpoint 3 Interrupt +AT91C_UDP_EPINT4 EQU (0x1 << 4) ;- (UDP) Endpoint 4 Interrupt +AT91C_UDP_EPINT5 EQU (0x1 << 5) ;- (UDP) Endpoint 5 Interrupt +AT91C_UDP_RXSUSP EQU (0x1 << 8) ;- (UDP) USB Suspend Interrupt +AT91C_UDP_RXRSM EQU (0x1 << 9) ;- (UDP) USB Resume Interrupt +AT91C_UDP_EXTRSM EQU (0x1 << 10) ;- (UDP) USB External Resume Interrupt +AT91C_UDP_SOFINT EQU (0x1 << 11) ;- (UDP) USB Start Of frame Interrupt +AT91C_UDP_WAKEUP EQU (0x1 << 13) ;- (UDP) USB Resume Interrupt +// - -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// - -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// - -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +AT91C_UDP_ENDBUSRES EQU (0x1 << 12) ;- (UDP) USB End Of Bus Reset Interrupt +// - -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// - -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +AT91C_UDP_EP0 EQU (0x1 << 0) ;- (UDP) Reset Endpoint 0 +AT91C_UDP_EP1 EQU (0x1 << 1) ;- (UDP) Reset Endpoint 1 +AT91C_UDP_EP2 EQU (0x1 << 2) ;- (UDP) Reset Endpoint 2 +AT91C_UDP_EP3 EQU (0x1 << 3) ;- (UDP) Reset Endpoint 3 +AT91C_UDP_EP4 EQU (0x1 << 4) ;- (UDP) Reset Endpoint 4 +AT91C_UDP_EP5 EQU (0x1 << 5) ;- (UDP) Reset Endpoint 5 +// - -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +AT91C_UDP_TXCOMP EQU (0x1 << 0) ;- (UDP) Generates an IN packet with data previously written in the DPR +AT91C_UDP_RX_DATA_BK0 EQU (0x1 << 1) ;- (UDP) Receive Data Bank 0 +AT91C_UDP_RXSETUP EQU (0x1 << 2) ;- (UDP) Sends STALL to the Host (Control endpoints) +AT91C_UDP_ISOERROR EQU (0x1 << 3) ;- (UDP) Isochronous error (Isochronous endpoints) +AT91C_UDP_TXPKTRDY EQU (0x1 << 4) ;- (UDP) Transmit Packet Ready +AT91C_UDP_FORCESTALL EQU (0x1 << 5) ;- (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +AT91C_UDP_RX_DATA_BK1 EQU (0x1 << 6) ;- (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +AT91C_UDP_DIR EQU (0x1 << 7) ;- (UDP) Transfer Direction +AT91C_UDP_EPTYPE EQU (0x7 << 8) ;- (UDP) Endpoint type +AT91C_UDP_EPTYPE_CTRL EQU (0x0 << 8) ;- (UDP) Control +AT91C_UDP_EPTYPE_ISO_OUT EQU (0x1 << 8) ;- (UDP) Isochronous OUT +AT91C_UDP_EPTYPE_BULK_OUT EQU (0x2 << 8) ;- (UDP) Bulk OUT +AT91C_UDP_EPTYPE_INT_OUT EQU (0x3 << 8) ;- (UDP) Interrupt OUT +AT91C_UDP_EPTYPE_ISO_IN EQU (0x5 << 8) ;- (UDP) Isochronous IN +AT91C_UDP_EPTYPE_BULK_IN EQU (0x6 << 8) ;- (UDP) Bulk IN +AT91C_UDP_EPTYPE_INT_IN EQU (0x7 << 8) ;- (UDP) Interrupt IN +AT91C_UDP_DTGLE EQU (0x1 << 11) ;- (UDP) Data Toggle +AT91C_UDP_EPEDS EQU (0x1 << 15) ;- (UDP) Endpoint Enable Disable +AT91C_UDP_RXBYTECNT EQU (0x7FF << 16) ;- (UDP) Number Of Bytes Available in the FIFO +// - -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +AT91C_UDP_TXVDIS EQU (0x1 << 8) ;- (UDP) +AT91C_UDP_PUON EQU (0x1 << 9) ;- (UDP) Pull-up ON + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// - ***************************************************************************** +// - -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +AT91C_TC_CLKEN EQU (0x1 << 0) ;- (TC) Counter Clock Enable Command +AT91C_TC_CLKDIS EQU (0x1 << 1) ;- (TC) Counter Clock Disable Command +AT91C_TC_SWTRG EQU (0x1 << 2) ;- (TC) Software Trigger Command +// - -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +AT91C_TC_CLKS EQU (0x7 << 0) ;- (TC) Clock Selection +AT91C_TC_CLKS_TIMER_DIV1_CLOCK EQU (0x0) ;- (TC) Clock selected: TIMER_DIV1_CLOCK +AT91C_TC_CLKS_TIMER_DIV2_CLOCK EQU (0x1) ;- (TC) Clock selected: TIMER_DIV2_CLOCK +AT91C_TC_CLKS_TIMER_DIV3_CLOCK EQU (0x2) ;- (TC) Clock selected: TIMER_DIV3_CLOCK +AT91C_TC_CLKS_TIMER_DIV4_CLOCK EQU (0x3) ;- (TC) Clock selected: TIMER_DIV4_CLOCK +AT91C_TC_CLKS_TIMER_DIV5_CLOCK EQU (0x4) ;- (TC) Clock selected: TIMER_DIV5_CLOCK +AT91C_TC_CLKS_XC0 EQU (0x5) ;- (TC) Clock selected: XC0 +AT91C_TC_CLKS_XC1 EQU (0x6) ;- (TC) Clock selected: XC1 +AT91C_TC_CLKS_XC2 EQU (0x7) ;- (TC) Clock selected: XC2 +AT91C_TC_CLKI EQU (0x1 << 3) ;- (TC) Clock Invert +AT91C_TC_BURST EQU (0x3 << 4) ;- (TC) Burst Signal Selection +AT91C_TC_BURST_NONE EQU (0x0 << 4) ;- (TC) The clock is not gated by an external signal +AT91C_TC_BURST_XC0 EQU (0x1 << 4) ;- (TC) XC0 is ANDed with the selected clock +AT91C_TC_BURST_XC1 EQU (0x2 << 4) ;- (TC) XC1 is ANDed with the selected clock +AT91C_TC_BURST_XC2 EQU (0x3 << 4) ;- (TC) XC2 is ANDed with the selected clock +AT91C_TC_CPCSTOP EQU (0x1 << 6) ;- (TC) Counter Clock Stopped with RC Compare +AT91C_TC_LDBSTOP EQU (0x1 << 6) ;- (TC) Counter Clock Stopped with RB Loading +AT91C_TC_CPCDIS EQU (0x1 << 7) ;- (TC) Counter Clock Disable with RC Compare +AT91C_TC_LDBDIS EQU (0x1 << 7) ;- (TC) Counter Clock Disabled with RB Loading +AT91C_TC_ETRGEDG EQU (0x3 << 8) ;- (TC) External Trigger Edge Selection +AT91C_TC_ETRGEDG_NONE EQU (0x0 << 8) ;- (TC) Edge: None +AT91C_TC_ETRGEDG_RISING EQU (0x1 << 8) ;- (TC) Edge: rising edge +AT91C_TC_ETRGEDG_FALLING EQU (0x2 << 8) ;- (TC) Edge: falling edge +AT91C_TC_ETRGEDG_BOTH EQU (0x3 << 8) ;- (TC) Edge: each edge +AT91C_TC_EEVTEDG EQU (0x3 << 8) ;- (TC) External Event Edge Selection +AT91C_TC_EEVTEDG_NONE EQU (0x0 << 8) ;- (TC) Edge: None +AT91C_TC_EEVTEDG_RISING EQU (0x1 << 8) ;- (TC) Edge: rising edge +AT91C_TC_EEVTEDG_FALLING EQU (0x2 << 8) ;- (TC) Edge: falling edge +AT91C_TC_EEVTEDG_BOTH EQU (0x3 << 8) ;- (TC) Edge: each edge +AT91C_TC_EEVT EQU (0x3 << 10) ;- (TC) External Event Selection +AT91C_TC_EEVT_TIOB EQU (0x0 << 10) ;- (TC) Signal selected as external event: TIOB TIOB direction: input +AT91C_TC_EEVT_XC0 EQU (0x1 << 10) ;- (TC) Signal selected as external event: XC0 TIOB direction: output +AT91C_TC_EEVT_XC1 EQU (0x2 << 10) ;- (TC) Signal selected as external event: XC1 TIOB direction: output +AT91C_TC_EEVT_XC2 EQU (0x3 << 10) ;- (TC) Signal selected as external event: XC2 TIOB direction: output +AT91C_TC_ABETRG EQU (0x1 << 10) ;- (TC) TIOA or TIOB External Trigger Selection +AT91C_TC_ENETRG EQU (0x1 << 12) ;- (TC) External Event Trigger enable +AT91C_TC_WAVESEL EQU (0x3 << 13) ;- (TC) Waveform Selection +AT91C_TC_WAVESEL_UP EQU (0x0 << 13) ;- (TC) UP mode without atomatic trigger on RC Compare +AT91C_TC_WAVESEL_UPDOWN EQU (0x1 << 13) ;- (TC) UPDOWN mode without automatic trigger on RC Compare +AT91C_TC_WAVESEL_UP_AUTO EQU (0x2 << 13) ;- (TC) UP mode with automatic trigger on RC Compare +AT91C_TC_WAVESEL_UPDOWN_AUTO EQU (0x3 << 13) ;- (TC) UPDOWN mode with automatic trigger on RC Compare +AT91C_TC_CPCTRG EQU (0x1 << 14) ;- (TC) RC Compare Trigger Enable +AT91C_TC_WAVE EQU (0x1 << 15) ;- (TC) +AT91C_TC_ACPA EQU (0x3 << 16) ;- (TC) RA Compare Effect on TIOA +AT91C_TC_ACPA_NONE EQU (0x0 << 16) ;- (TC) Effect: none +AT91C_TC_ACPA_SET EQU (0x1 << 16) ;- (TC) Effect: set +AT91C_TC_ACPA_CLEAR EQU (0x2 << 16) ;- (TC) Effect: clear +AT91C_TC_ACPA_TOGGLE EQU (0x3 << 16) ;- (TC) Effect: toggle +AT91C_TC_LDRA EQU (0x3 << 16) ;- (TC) RA Loading Selection +AT91C_TC_LDRA_NONE EQU (0x0 << 16) ;- (TC) Edge: None +AT91C_TC_LDRA_RISING EQU (0x1 << 16) ;- (TC) Edge: rising edge of TIOA +AT91C_TC_LDRA_FALLING EQU (0x2 << 16) ;- (TC) Edge: falling edge of TIOA +AT91C_TC_LDRA_BOTH EQU (0x3 << 16) ;- (TC) Edge: each edge of TIOA +AT91C_TC_ACPC EQU (0x3 << 18) ;- (TC) RC Compare Effect on TIOA +AT91C_TC_ACPC_NONE EQU (0x0 << 18) ;- (TC) Effect: none +AT91C_TC_ACPC_SET EQU (0x1 << 18) ;- (TC) Effect: set +AT91C_TC_ACPC_CLEAR EQU (0x2 << 18) ;- (TC) Effect: clear +AT91C_TC_ACPC_TOGGLE EQU (0x3 << 18) ;- (TC) Effect: toggle +AT91C_TC_LDRB EQU (0x3 << 18) ;- (TC) RB Loading Selection +AT91C_TC_LDRB_NONE EQU (0x0 << 18) ;- (TC) Edge: None +AT91C_TC_LDRB_RISING EQU (0x1 << 18) ;- (TC) Edge: rising edge of TIOA +AT91C_TC_LDRB_FALLING EQU (0x2 << 18) ;- (TC) Edge: falling edge of TIOA +AT91C_TC_LDRB_BOTH EQU (0x3 << 18) ;- (TC) Edge: each edge of TIOA +AT91C_TC_AEEVT EQU (0x3 << 20) ;- (TC) External Event Effect on TIOA +AT91C_TC_AEEVT_NONE EQU (0x0 << 20) ;- (TC) Effect: none +AT91C_TC_AEEVT_SET EQU (0x1 << 20) ;- (TC) Effect: set +AT91C_TC_AEEVT_CLEAR EQU (0x2 << 20) ;- (TC) Effect: clear +AT91C_TC_AEEVT_TOGGLE EQU (0x3 << 20) ;- (TC) Effect: toggle +AT91C_TC_ASWTRG EQU (0x3 << 22) ;- (TC) Software Trigger Effect on TIOA +AT91C_TC_ASWTRG_NONE EQU (0x0 << 22) ;- (TC) Effect: none +AT91C_TC_ASWTRG_SET EQU (0x1 << 22) ;- (TC) Effect: set +AT91C_TC_ASWTRG_CLEAR EQU (0x2 << 22) ;- (TC) Effect: clear +AT91C_TC_ASWTRG_TOGGLE EQU (0x3 << 22) ;- (TC) Effect: toggle +AT91C_TC_BCPB EQU (0x3 << 24) ;- (TC) RB Compare Effect on TIOB +AT91C_TC_BCPB_NONE EQU (0x0 << 24) ;- (TC) Effect: none +AT91C_TC_BCPB_SET EQU (0x1 << 24) ;- (TC) Effect: set +AT91C_TC_BCPB_CLEAR EQU (0x2 << 24) ;- (TC) Effect: clear +AT91C_TC_BCPB_TOGGLE EQU (0x3 << 24) ;- (TC) Effect: toggle +AT91C_TC_BCPC EQU (0x3 << 26) ;- (TC) RC Compare Effect on TIOB +AT91C_TC_BCPC_NONE EQU (0x0 << 26) ;- (TC) Effect: none +AT91C_TC_BCPC_SET EQU (0x1 << 26) ;- (TC) Effect: set +AT91C_TC_BCPC_CLEAR EQU (0x2 << 26) ;- (TC) Effect: clear +AT91C_TC_BCPC_TOGGLE EQU (0x3 << 26) ;- (TC) Effect: toggle +AT91C_TC_BEEVT EQU (0x3 << 28) ;- (TC) External Event Effect on TIOB +AT91C_TC_BEEVT_NONE EQU (0x0 << 28) ;- (TC) Effect: none +AT91C_TC_BEEVT_SET EQU (0x1 << 28) ;- (TC) Effect: set +AT91C_TC_BEEVT_CLEAR EQU (0x2 << 28) ;- (TC) Effect: clear +AT91C_TC_BEEVT_TOGGLE EQU (0x3 << 28) ;- (TC) Effect: toggle +AT91C_TC_BSWTRG EQU (0x3 << 30) ;- (TC) Software Trigger Effect on TIOB +AT91C_TC_BSWTRG_NONE EQU (0x0 << 30) ;- (TC) Effect: none +AT91C_TC_BSWTRG_SET EQU (0x1 << 30) ;- (TC) Effect: set +AT91C_TC_BSWTRG_CLEAR EQU (0x2 << 30) ;- (TC) Effect: clear +AT91C_TC_BSWTRG_TOGGLE EQU (0x3 << 30) ;- (TC) Effect: toggle +// - -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +AT91C_TC_COVFS EQU (0x1 << 0) ;- (TC) Counter Overflow +AT91C_TC_LOVRS EQU (0x1 << 1) ;- (TC) Load Overrun +AT91C_TC_CPAS EQU (0x1 << 2) ;- (TC) RA Compare +AT91C_TC_CPBS EQU (0x1 << 3) ;- (TC) RB Compare +AT91C_TC_CPCS EQU (0x1 << 4) ;- (TC) RC Compare +AT91C_TC_LDRAS EQU (0x1 << 5) ;- (TC) RA Loading +AT91C_TC_LDRBS EQU (0x1 << 6) ;- (TC) RB Loading +AT91C_TC_ETRGS EQU (0x1 << 7) ;- (TC) External Trigger +AT91C_TC_CLKSTA EQU (0x1 << 16) ;- (TC) Clock Enabling +AT91C_TC_MTIOA EQU (0x1 << 17) ;- (TC) TIOA Mirror +AT91C_TC_MTIOB EQU (0x1 << 18) ;- (TC) TIOA Mirror +// - -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// - -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// - -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Timer Counter Interface +// - ***************************************************************************** +// - -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +AT91C_TCB_SYNC EQU (0x1 << 0) ;- (TCB) Synchro Command +// - -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +AT91C_TCB_TC0XC0S EQU (0x3 << 0) ;- (TCB) External Clock Signal 0 Selection +AT91C_TCB_TC0XC0S_TCLK0 EQU (0x0) ;- (TCB) TCLK0 connected to XC0 +AT91C_TCB_TC0XC0S_NONE EQU (0x1) ;- (TCB) None signal connected to XC0 +AT91C_TCB_TC0XC0S_TIOA1 EQU (0x2) ;- (TCB) TIOA1 connected to XC0 +AT91C_TCB_TC0XC0S_TIOA2 EQU (0x3) ;- (TCB) TIOA2 connected to XC0 +AT91C_TCB_TC1XC1S EQU (0x3 << 2) ;- (TCB) External Clock Signal 1 Selection +AT91C_TCB_TC1XC1S_TCLK1 EQU (0x0 << 2) ;- (TCB) TCLK1 connected to XC1 +AT91C_TCB_TC1XC1S_NONE EQU (0x1 << 2) ;- (TCB) None signal connected to XC1 +AT91C_TCB_TC1XC1S_TIOA0 EQU (0x2 << 2) ;- (TCB) TIOA0 connected to XC1 +AT91C_TCB_TC1XC1S_TIOA2 EQU (0x3 << 2) ;- (TCB) TIOA2 connected to XC1 +AT91C_TCB_TC2XC2S EQU (0x3 << 4) ;- (TCB) External Clock Signal 2 Selection +AT91C_TCB_TC2XC2S_TCLK2 EQU (0x0 << 4) ;- (TCB) TCLK2 connected to XC2 +AT91C_TCB_TC2XC2S_NONE EQU (0x1 << 4) ;- (TCB) None signal connected to XC2 +AT91C_TCB_TC2XC2S_TIOA0 EQU (0x2 << 4) ;- (TCB) TIOA0 connected to XC2 +AT91C_TCB_TC2XC2S_TIOA1 EQU (0x3 << 4) ;- (TCB) TIOA2 connected to XC2 + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface +// - ***************************************************************************** +// - -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- +AT91C_CAN_MTIMEMARK EQU (0xFFFF << 0) ;- (CAN_MB) Mailbox Timemark +AT91C_CAN_PRIOR EQU (0xF << 16) ;- (CAN_MB) Mailbox Priority +AT91C_CAN_MOT EQU (0x7 << 24) ;- (CAN_MB) Mailbox Object Type +AT91C_CAN_MOT_DIS EQU (0x0 << 24) ;- (CAN_MB) +AT91C_CAN_MOT_RX EQU (0x1 << 24) ;- (CAN_MB) +AT91C_CAN_MOT_RXOVERWRITE EQU (0x2 << 24) ;- (CAN_MB) +AT91C_CAN_MOT_TX EQU (0x3 << 24) ;- (CAN_MB) +AT91C_CAN_MOT_CONSUMER EQU (0x4 << 24) ;- (CAN_MB) +AT91C_CAN_MOT_PRODUCER EQU (0x5 << 24) ;- (CAN_MB) +// - -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- +AT91C_CAN_MIDvB EQU (0x3FFFF << 0) ;- (CAN_MB) Complementary bits for identifier in extended mode +AT91C_CAN_MIDvA EQU (0x7FF << 18) ;- (CAN_MB) Identifier for standard frame mode +AT91C_CAN_MIDE EQU (0x1 << 29) ;- (CAN_MB) Identifier Version +// - -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- +// - -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- +// - -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- +AT91C_CAN_MTIMESTAMP EQU (0xFFFF << 0) ;- (CAN_MB) Timer Value +AT91C_CAN_MDLC EQU (0xF << 16) ;- (CAN_MB) Mailbox Data Length Code +AT91C_CAN_MRTR EQU (0x1 << 20) ;- (CAN_MB) Mailbox Remote Transmission Request +AT91C_CAN_MABT EQU (0x1 << 22) ;- (CAN_MB) Mailbox Message Abort +AT91C_CAN_MRDY EQU (0x1 << 23) ;- (CAN_MB) Mailbox Ready +AT91C_CAN_MMI EQU (0x1 << 24) ;- (CAN_MB) Mailbox Message Ignored +// - -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- +// - -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- +// - -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- +AT91C_CAN_MACR EQU (0x1 << 22) ;- (CAN_MB) Abort Request for Mailbox +AT91C_CAN_MTCR EQU (0x1 << 23) ;- (CAN_MB) Mailbox Transfer Command + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Control Area Network Interface +// - ***************************************************************************** +// - -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- +AT91C_CAN_CANEN EQU (0x1 << 0) ;- (CAN) CAN Controller Enable +AT91C_CAN_LPM EQU (0x1 << 1) ;- (CAN) Disable/Enable Low Power Mode +AT91C_CAN_ABM EQU (0x1 << 2) ;- (CAN) Disable/Enable Autobaud/Listen Mode +AT91C_CAN_OVL EQU (0x1 << 3) ;- (CAN) Disable/Enable Overload Frame +AT91C_CAN_TEOF EQU (0x1 << 4) ;- (CAN) Time Stamp messages at each end of Frame +AT91C_CAN_TTM EQU (0x1 << 5) ;- (CAN) Disable/Enable Time Trigger Mode +AT91C_CAN_TIMFRZ EQU (0x1 << 6) ;- (CAN) Enable Timer Freeze +AT91C_CAN_DRPT EQU (0x1 << 7) ;- (CAN) Disable Repeat +// - -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- +AT91C_CAN_MB0 EQU (0x1 << 0) ;- (CAN) Mailbox 0 Flag +AT91C_CAN_MB1 EQU (0x1 << 1) ;- (CAN) Mailbox 1 Flag +AT91C_CAN_MB2 EQU (0x1 << 2) ;- (CAN) Mailbox 2 Flag +AT91C_CAN_MB3 EQU (0x1 << 3) ;- (CAN) Mailbox 3 Flag +AT91C_CAN_MB4 EQU (0x1 << 4) ;- (CAN) Mailbox 4 Flag +AT91C_CAN_MB5 EQU (0x1 << 5) ;- (CAN) Mailbox 5 Flag +AT91C_CAN_MB6 EQU (0x1 << 6) ;- (CAN) Mailbox 6 Flag +AT91C_CAN_MB7 EQU (0x1 << 7) ;- (CAN) Mailbox 7 Flag +AT91C_CAN_MB8 EQU (0x1 << 8) ;- (CAN) Mailbox 8 Flag +AT91C_CAN_MB9 EQU (0x1 << 9) ;- (CAN) Mailbox 9 Flag +AT91C_CAN_MB10 EQU (0x1 << 10) ;- (CAN) Mailbox 10 Flag +AT91C_CAN_MB11 EQU (0x1 << 11) ;- (CAN) Mailbox 11 Flag +AT91C_CAN_MB12 EQU (0x1 << 12) ;- (CAN) Mailbox 12 Flag +AT91C_CAN_MB13 EQU (0x1 << 13) ;- (CAN) Mailbox 13 Flag +AT91C_CAN_MB14 EQU (0x1 << 14) ;- (CAN) Mailbox 14 Flag +AT91C_CAN_MB15 EQU (0x1 << 15) ;- (CAN) Mailbox 15 Flag +AT91C_CAN_ERRA EQU (0x1 << 16) ;- (CAN) Error Active Mode Flag +AT91C_CAN_WARN EQU (0x1 << 17) ;- (CAN) Warning Limit Flag +AT91C_CAN_ERRP EQU (0x1 << 18) ;- (CAN) Error Passive Mode Flag +AT91C_CAN_BOFF EQU (0x1 << 19) ;- (CAN) Bus Off Mode Flag +AT91C_CAN_SLEEP EQU (0x1 << 20) ;- (CAN) Sleep Flag +AT91C_CAN_WAKEUP EQU (0x1 << 21) ;- (CAN) Wakeup Flag +AT91C_CAN_TOVF EQU (0x1 << 22) ;- (CAN) Timer Overflow Flag +AT91C_CAN_TSTP EQU (0x1 << 23) ;- (CAN) Timestamp Flag +AT91C_CAN_CERR EQU (0x1 << 24) ;- (CAN) CRC Error +AT91C_CAN_SERR EQU (0x1 << 25) ;- (CAN) Stuffing Error +AT91C_CAN_AERR EQU (0x1 << 26) ;- (CAN) Acknowledgment Error +AT91C_CAN_FERR EQU (0x1 << 27) ;- (CAN) Form Error +AT91C_CAN_BERR EQU (0x1 << 28) ;- (CAN) Bit Error +// - -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- +// - -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- +// - -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- +AT91C_CAN_RBSY EQU (0x1 << 29) ;- (CAN) Receiver Busy +AT91C_CAN_TBSY EQU (0x1 << 30) ;- (CAN) Transmitter Busy +AT91C_CAN_OVLY EQU (0x1 << 31) ;- (CAN) Overload Busy +// - -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- +AT91C_CAN_PHASE2 EQU (0x7 << 0) ;- (CAN) Phase 2 segment +AT91C_CAN_PHASE1 EQU (0x7 << 4) ;- (CAN) Phase 1 segment +AT91C_CAN_PROPAG EQU (0x7 << 8) ;- (CAN) Programmation time segment +AT91C_CAN_SYNC EQU (0x3 << 12) ;- (CAN) Re-synchronization jump width segment +AT91C_CAN_BRP EQU (0x7F << 16) ;- (CAN) Baudrate Prescaler +AT91C_CAN_SMP EQU (0x1 << 24) ;- (CAN) Sampling mode +// - -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- +AT91C_CAN_TIMER EQU (0xFFFF << 0) ;- (CAN) Timer field +// - -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- +// - -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- +AT91C_CAN_REC EQU (0xFF << 0) ;- (CAN) Receive Error Counter +AT91C_CAN_TEC EQU (0xFF << 16) ;- (CAN) Transmit Error Counter +// - -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- +AT91C_CAN_TIMRST EQU (0x1 << 31) ;- (CAN) Timer Reset Field +// - -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 +// - ***************************************************************************** +// - -------- EMAC_NCR : (EMAC Offset: 0x0) -------- +AT91C_EMAC_LB EQU (0x1 << 0) ;- (EMAC) Loopback. Optional. When set, loopback signal is at high level. +AT91C_EMAC_LLB EQU (0x1 << 1) ;- (EMAC) Loopback local. +AT91C_EMAC_RE EQU (0x1 << 2) ;- (EMAC) Receive enable. +AT91C_EMAC_TE EQU (0x1 << 3) ;- (EMAC) Transmit enable. +AT91C_EMAC_MPE EQU (0x1 << 4) ;- (EMAC) Management port enable. +AT91C_EMAC_CLRSTAT EQU (0x1 << 5) ;- (EMAC) Clear statistics registers. +AT91C_EMAC_INCSTAT EQU (0x1 << 6) ;- (EMAC) Increment statistics registers. +AT91C_EMAC_WESTAT EQU (0x1 << 7) ;- (EMAC) Write enable for statistics registers. +AT91C_EMAC_BP EQU (0x1 << 8) ;- (EMAC) Back pressure. +AT91C_EMAC_TSTART EQU (0x1 << 9) ;- (EMAC) Start Transmission. +AT91C_EMAC_THALT EQU (0x1 << 10) ;- (EMAC) Transmission Halt. +AT91C_EMAC_TPFR EQU (0x1 << 11) ;- (EMAC) Transmit pause frame +AT91C_EMAC_TZQ EQU (0x1 << 12) ;- (EMAC) Transmit zero quantum pause frame +// - -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- +AT91C_EMAC_SPD EQU (0x1 << 0) ;- (EMAC) Speed. +AT91C_EMAC_FD EQU (0x1 << 1) ;- (EMAC) Full duplex. +AT91C_EMAC_JFRAME EQU (0x1 << 3) ;- (EMAC) Jumbo Frames. +AT91C_EMAC_CAF EQU (0x1 << 4) ;- (EMAC) Copy all frames. +AT91C_EMAC_NBC EQU (0x1 << 5) ;- (EMAC) No broadcast. +AT91C_EMAC_MTI EQU (0x1 << 6) ;- (EMAC) Multicast hash event enable +AT91C_EMAC_UNI EQU (0x1 << 7) ;- (EMAC) Unicast hash enable. +AT91C_EMAC_BIG EQU (0x1 << 8) ;- (EMAC) Receive 1522 bytes. +AT91C_EMAC_EAE EQU (0x1 << 9) ;- (EMAC) External address match enable. +AT91C_EMAC_CLK EQU (0x3 << 10) ;- (EMAC) +AT91C_EMAC_CLK_HCLK_8 EQU (0x0 << 10) ;- (EMAC) HCLK divided by 8 +AT91C_EMAC_CLK_HCLK_16 EQU (0x1 << 10) ;- (EMAC) HCLK divided by 16 +AT91C_EMAC_CLK_HCLK_32 EQU (0x2 << 10) ;- (EMAC) HCLK divided by 32 +AT91C_EMAC_CLK_HCLK_64 EQU (0x3 << 10) ;- (EMAC) HCLK divided by 64 +AT91C_EMAC_RTY EQU (0x1 << 12) ;- (EMAC) +AT91C_EMAC_PAE EQU (0x1 << 13) ;- (EMAC) +AT91C_EMAC_RBOF EQU (0x3 << 14) ;- (EMAC) +AT91C_EMAC_RBOF_OFFSET_0 EQU (0x0 << 14) ;- (EMAC) no offset from start of receive buffer +AT91C_EMAC_RBOF_OFFSET_1 EQU (0x1 << 14) ;- (EMAC) one byte offset from start of receive buffer +AT91C_EMAC_RBOF_OFFSET_2 EQU (0x2 << 14) ;- (EMAC) two bytes offset from start of receive buffer +AT91C_EMAC_RBOF_OFFSET_3 EQU (0x3 << 14) ;- (EMAC) three bytes offset from start of receive buffer +AT91C_EMAC_RLCE EQU (0x1 << 16) ;- (EMAC) Receive Length field Checking Enable +AT91C_EMAC_DRFCS EQU (0x1 << 17) ;- (EMAC) Discard Receive FCS +AT91C_EMAC_EFRHD EQU (0x1 << 18) ;- (EMAC) +AT91C_EMAC_IRXFCS EQU (0x1 << 19) ;- (EMAC) Ignore RX FCS +// - -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- +AT91C_EMAC_LINKR EQU (0x1 << 0) ;- (EMAC) +AT91C_EMAC_MDIO EQU (0x1 << 1) ;- (EMAC) +AT91C_EMAC_IDLE EQU (0x1 << 2) ;- (EMAC) +// - -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- +AT91C_EMAC_UBR EQU (0x1 << 0) ;- (EMAC) +AT91C_EMAC_COL EQU (0x1 << 1) ;- (EMAC) +AT91C_EMAC_RLES EQU (0x1 << 2) ;- (EMAC) +AT91C_EMAC_TGO EQU (0x1 << 3) ;- (EMAC) Transmit Go +AT91C_EMAC_BEX EQU (0x1 << 4) ;- (EMAC) Buffers exhausted mid frame +AT91C_EMAC_COMP EQU (0x1 << 5) ;- (EMAC) +AT91C_EMAC_UND EQU (0x1 << 6) ;- (EMAC) +// - -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- +AT91C_EMAC_BNA EQU (0x1 << 0) ;- (EMAC) +AT91C_EMAC_REC EQU (0x1 << 1) ;- (EMAC) +AT91C_EMAC_OVR EQU (0x1 << 2) ;- (EMAC) +// - -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- +AT91C_EMAC_MFD EQU (0x1 << 0) ;- (EMAC) +AT91C_EMAC_RCOMP EQU (0x1 << 1) ;- (EMAC) +AT91C_EMAC_RXUBR EQU (0x1 << 2) ;- (EMAC) +AT91C_EMAC_TXUBR EQU (0x1 << 3) ;- (EMAC) +AT91C_EMAC_TUNDR EQU (0x1 << 4) ;- (EMAC) +AT91C_EMAC_RLEX EQU (0x1 << 5) ;- (EMAC) +AT91C_EMAC_TXERR EQU (0x1 << 6) ;- (EMAC) +AT91C_EMAC_TCOMP EQU (0x1 << 7) ;- (EMAC) +AT91C_EMAC_LINK EQU (0x1 << 9) ;- (EMAC) +AT91C_EMAC_ROVR EQU (0x1 << 10) ;- (EMAC) +AT91C_EMAC_HRESP EQU (0x1 << 11) ;- (EMAC) +AT91C_EMAC_PFRE EQU (0x1 << 12) ;- (EMAC) +AT91C_EMAC_PTZ EQU (0x1 << 13) ;- (EMAC) +// - -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- +// - -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- +// - -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- +// - -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- +AT91C_EMAC_DATA EQU (0xFFFF << 0) ;- (EMAC) +AT91C_EMAC_CODE EQU (0x3 << 16) ;- (EMAC) +AT91C_EMAC_REGA EQU (0x1F << 18) ;- (EMAC) +AT91C_EMAC_PHYA EQU (0x1F << 23) ;- (EMAC) +AT91C_EMAC_RW EQU (0x3 << 28) ;- (EMAC) +AT91C_EMAC_SOF EQU (0x3 << 30) ;- (EMAC) +// - -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- +AT91C_EMAC_RMII EQU (0x1 << 0) ;- (EMAC) Reduce MII +// - -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- +AT91C_EMAC_IP EQU (0xFFFF << 0) ;- (EMAC) ARP request IP address +AT91C_EMAC_MAG EQU (0x1 << 16) ;- (EMAC) Magic packet event enable +AT91C_EMAC_ARP EQU (0x1 << 17) ;- (EMAC) ARP request event enable +AT91C_EMAC_SA1 EQU (0x1 << 18) ;- (EMAC) Specific address register 1 event enable +// - -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- +AT91C_EMAC_REVREF EQU (0xFFFF << 0) ;- (EMAC) +AT91C_EMAC_PARTREF EQU (0xFFFF << 16) ;- (EMAC) + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// - ***************************************************************************** +// - -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +AT91C_ADC_SWRST EQU (0x1 << 0) ;- (ADC) Software Reset +AT91C_ADC_START EQU (0x1 << 1) ;- (ADC) Start Conversion +// - -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +AT91C_ADC_TRGEN EQU (0x1 << 0) ;- (ADC) Trigger Enable +AT91C_ADC_TRGEN_DIS EQU (0x0) ;- (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +AT91C_ADC_TRGEN_EN EQU (0x1) ;- (ADC) Hardware trigger selected by TRGSEL field is enabled. +AT91C_ADC_TRGSEL EQU (0x7 << 1) ;- (ADC) Trigger Selection +AT91C_ADC_TRGSEL_TIOA0 EQU (0x0 << 1) ;- (ADC) Selected TRGSEL = TIAO0 +AT91C_ADC_TRGSEL_TIOA1 EQU (0x1 << 1) ;- (ADC) Selected TRGSEL = TIAO1 +AT91C_ADC_TRGSEL_TIOA2 EQU (0x2 << 1) ;- (ADC) Selected TRGSEL = TIAO2 +AT91C_ADC_TRGSEL_TIOA3 EQU (0x3 << 1) ;- (ADC) Selected TRGSEL = TIAO3 +AT91C_ADC_TRGSEL_TIOA4 EQU (0x4 << 1) ;- (ADC) Selected TRGSEL = TIAO4 +AT91C_ADC_TRGSEL_TIOA5 EQU (0x5 << 1) ;- (ADC) Selected TRGSEL = TIAO5 +AT91C_ADC_TRGSEL_EXT EQU (0x6 << 1) ;- (ADC) Selected TRGSEL = External Trigger +AT91C_ADC_LOWRES EQU (0x1 << 4) ;- (ADC) Resolution. +AT91C_ADC_LOWRES_10_BIT EQU (0x0 << 4) ;- (ADC) 10-bit resolution +AT91C_ADC_LOWRES_8_BIT EQU (0x1 << 4) ;- (ADC) 8-bit resolution +AT91C_ADC_SLEEP EQU (0x1 << 5) ;- (ADC) Sleep Mode +AT91C_ADC_SLEEP_NORMAL_MODE EQU (0x0 << 5) ;- (ADC) Normal Mode +AT91C_ADC_SLEEP_MODE EQU (0x1 << 5) ;- (ADC) Sleep Mode +AT91C_ADC_PRESCAL EQU (0x3F << 8) ;- (ADC) Prescaler rate selection +AT91C_ADC_STARTUP EQU (0x1F << 16) ;- (ADC) Startup Time +AT91C_ADC_SHTIM EQU (0xF << 24) ;- (ADC) Sample & Hold Time +// - -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +AT91C_ADC_CH0 EQU (0x1 << 0) ;- (ADC) Channel 0 +AT91C_ADC_CH1 EQU (0x1 << 1) ;- (ADC) Channel 1 +AT91C_ADC_CH2 EQU (0x1 << 2) ;- (ADC) Channel 2 +AT91C_ADC_CH3 EQU (0x1 << 3) ;- (ADC) Channel 3 +AT91C_ADC_CH4 EQU (0x1 << 4) ;- (ADC) Channel 4 +AT91C_ADC_CH5 EQU (0x1 << 5) ;- (ADC) Channel 5 +AT91C_ADC_CH6 EQU (0x1 << 6) ;- (ADC) Channel 6 +AT91C_ADC_CH7 EQU (0x1 << 7) ;- (ADC) Channel 7 +// - -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// - -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// - -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +AT91C_ADC_EOC0 EQU (0x1 << 0) ;- (ADC) End of Conversion +AT91C_ADC_EOC1 EQU (0x1 << 1) ;- (ADC) End of Conversion +AT91C_ADC_EOC2 EQU (0x1 << 2) ;- (ADC) End of Conversion +AT91C_ADC_EOC3 EQU (0x1 << 3) ;- (ADC) End of Conversion +AT91C_ADC_EOC4 EQU (0x1 << 4) ;- (ADC) End of Conversion +AT91C_ADC_EOC5 EQU (0x1 << 5) ;- (ADC) End of Conversion +AT91C_ADC_EOC6 EQU (0x1 << 6) ;- (ADC) End of Conversion +AT91C_ADC_EOC7 EQU (0x1 << 7) ;- (ADC) End of Conversion +AT91C_ADC_OVRE0 EQU (0x1 << 8) ;- (ADC) Overrun Error +AT91C_ADC_OVRE1 EQU (0x1 << 9) ;- (ADC) Overrun Error +AT91C_ADC_OVRE2 EQU (0x1 << 10) ;- (ADC) Overrun Error +AT91C_ADC_OVRE3 EQU (0x1 << 11) ;- (ADC) Overrun Error +AT91C_ADC_OVRE4 EQU (0x1 << 12) ;- (ADC) Overrun Error +AT91C_ADC_OVRE5 EQU (0x1 << 13) ;- (ADC) Overrun Error +AT91C_ADC_OVRE6 EQU (0x1 << 14) ;- (ADC) Overrun Error +AT91C_ADC_OVRE7 EQU (0x1 << 15) ;- (ADC) Overrun Error +AT91C_ADC_DRDY EQU (0x1 << 16) ;- (ADC) Data Ready +AT91C_ADC_GOVRE EQU (0x1 << 17) ;- (ADC) General Overrun +AT91C_ADC_ENDRX EQU (0x1 << 18) ;- (ADC) End of Receiver Transfer +AT91C_ADC_RXBUFF EQU (0x1 << 19) ;- (ADC) RXBUFF Interrupt +// - -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +AT91C_ADC_LDATA EQU (0x3FF << 0) ;- (ADC) Last Data Converted +// - -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// - -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// - -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// - -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +AT91C_ADC_DATA EQU (0x3FF << 0) ;- (ADC) Converted Data +// - -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// - -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// - -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// - -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// - -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// - -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// - -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Advanced Encryption Standard +// - ***************************************************************************** +// - -------- AES_CR : (AES Offset: 0x0) Control Register -------- +AT91C_AES_START EQU (0x1 << 0) ;- (AES) Starts Processing +AT91C_AES_SWRST EQU (0x1 << 8) ;- (AES) Software Reset +AT91C_AES_LOADSEED EQU (0x1 << 16) ;- (AES) Random Number Generator Seed Loading +// - -------- AES_MR : (AES Offset: 0x4) Mode Register -------- +AT91C_AES_CIPHER EQU (0x1 << 0) ;- (AES) Processing Mode +AT91C_AES_PROCDLY EQU (0xF << 4) ;- (AES) Processing Delay +AT91C_AES_SMOD EQU (0x3 << 8) ;- (AES) Start Mode +AT91C_AES_SMOD_MANUAL EQU (0x0 << 8) ;- (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. +AT91C_AES_SMOD_AUTO EQU (0x1 << 8) ;- (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). +AT91C_AES_SMOD_PDC EQU (0x2 << 8) ;- (AES) PDC Mode (cf datasheet). +AT91C_AES_OPMOD EQU (0x7 << 12) ;- (AES) Operation Mode +AT91C_AES_OPMOD_ECB EQU (0x0 << 12) ;- (AES) ECB Electronic CodeBook mode. +AT91C_AES_OPMOD_CBC EQU (0x1 << 12) ;- (AES) CBC Cipher Block Chaining mode. +AT91C_AES_OPMOD_OFB EQU (0x2 << 12) ;- (AES) OFB Output Feedback mode. +AT91C_AES_OPMOD_CFB EQU (0x3 << 12) ;- (AES) CFB Cipher Feedback mode. +AT91C_AES_OPMOD_CTR EQU (0x4 << 12) ;- (AES) CTR Counter mode. +AT91C_AES_LOD EQU (0x1 << 15) ;- (AES) Last Output Data Mode +AT91C_AES_CFBS EQU (0x7 << 16) ;- (AES) Cipher Feedback Data Size +AT91C_AES_CFBS_128_BIT EQU (0x0 << 16) ;- (AES) 128-bit. +AT91C_AES_CFBS_64_BIT EQU (0x1 << 16) ;- (AES) 64-bit. +AT91C_AES_CFBS_32_BIT EQU (0x2 << 16) ;- (AES) 32-bit. +AT91C_AES_CFBS_16_BIT EQU (0x3 << 16) ;- (AES) 16-bit. +AT91C_AES_CFBS_8_BIT EQU (0x4 << 16) ;- (AES) 8-bit. +AT91C_AES_CKEY EQU (0xF << 20) ;- (AES) Countermeasure Key +AT91C_AES_CTYPE EQU (0x1F << 24) ;- (AES) Countermeasure Type +AT91C_AES_CTYPE_TYPE1_EN EQU (0x1 << 24) ;- (AES) Countermeasure type 1 is enabled. +AT91C_AES_CTYPE_TYPE2_EN EQU (0x2 << 24) ;- (AES) Countermeasure type 2 is enabled. +AT91C_AES_CTYPE_TYPE3_EN EQU (0x4 << 24) ;- (AES) Countermeasure type 3 is enabled. +AT91C_AES_CTYPE_TYPE4_EN EQU (0x8 << 24) ;- (AES) Countermeasure type 4 is enabled. +AT91C_AES_CTYPE_TYPE5_EN EQU (0x10 << 24) ;- (AES) Countermeasure type 5 is enabled. +// - -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- +AT91C_AES_DATRDY EQU (0x1 << 0) ;- (AES) DATRDY +AT91C_AES_ENDRX EQU (0x1 << 1) ;- (AES) PDC Read Buffer End +AT91C_AES_ENDTX EQU (0x1 << 2) ;- (AES) PDC Write Buffer End +AT91C_AES_RXBUFF EQU (0x1 << 3) ;- (AES) PDC Read Buffer Full +AT91C_AES_TXBUFE EQU (0x1 << 4) ;- (AES) PDC Write Buffer Empty +AT91C_AES_URAD EQU (0x1 << 8) ;- (AES) Unspecified Register Access Detection +// - -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- +// - -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- +// - -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- +AT91C_AES_URAT EQU (0x7 << 12) ;- (AES) Unspecified Register Access Type Status +AT91C_AES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (AES) Input data register written during the data processing in PDC mode. +AT91C_AES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (AES) Output data register read during the data processing. +AT91C_AES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (AES) Mode register written during the data processing. +AT91C_AES_URAT_OUT_DAT_READ_SUBKEY EQU (0x3 << 12) ;- (AES) Output data register read during the sub-keys generation. +AT91C_AES_URAT_MODEREG_WRITE_SUBKEY EQU (0x4 << 12) ;- (AES) Mode register written during the sub-keys generation. +AT91C_AES_URAT_WO_REG_READ EQU (0x5 << 12) ;- (AES) Write-only register read access. + +// - ***************************************************************************** +// - SOFTWARE API DEFINITION FOR Triple Data Encryption Standard +// - ***************************************************************************** +// - -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- +AT91C_TDES_START EQU (0x1 << 0) ;- (TDES) Starts Processing +AT91C_TDES_SWRST EQU (0x1 << 8) ;- (TDES) Software Reset +// - -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- +AT91C_TDES_CIPHER EQU (0x1 << 0) ;- (TDES) Processing Mode +AT91C_TDES_TDESMOD EQU (0x1 << 1) ;- (TDES) Single or Triple DES Mode +AT91C_TDES_KEYMOD EQU (0x1 << 4) ;- (TDES) Key Mode +AT91C_TDES_SMOD EQU (0x3 << 8) ;- (TDES) Start Mode +AT91C_TDES_SMOD_MANUAL EQU (0x0 << 8) ;- (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. +AT91C_TDES_SMOD_AUTO EQU (0x1 << 8) ;- (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). +AT91C_TDES_SMOD_PDC EQU (0x2 << 8) ;- (TDES) PDC Mode (cf datasheet). +AT91C_TDES_OPMOD EQU (0x3 << 12) ;- (TDES) Operation Mode +AT91C_TDES_OPMOD_ECB EQU (0x0 << 12) ;- (TDES) ECB Electronic CodeBook mode. +AT91C_TDES_OPMOD_CBC EQU (0x1 << 12) ;- (TDES) CBC Cipher Block Chaining mode. +AT91C_TDES_OPMOD_OFB EQU (0x2 << 12) ;- (TDES) OFB Output Feedback mode. +AT91C_TDES_OPMOD_CFB EQU (0x3 << 12) ;- (TDES) CFB Cipher Feedback mode. +AT91C_TDES_LOD EQU (0x1 << 15) ;- (TDES) Last Output Data Mode +AT91C_TDES_CFBS EQU (0x3 << 16) ;- (TDES) Cipher Feedback Data Size +AT91C_TDES_CFBS_64_BIT EQU (0x0 << 16) ;- (TDES) 64-bit. +AT91C_TDES_CFBS_32_BIT EQU (0x1 << 16) ;- (TDES) 32-bit. +AT91C_TDES_CFBS_16_BIT EQU (0x2 << 16) ;- (TDES) 16-bit. +AT91C_TDES_CFBS_8_BIT EQU (0x3 << 16) ;- (TDES) 8-bit. +// - -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- +AT91C_TDES_DATRDY EQU (0x1 << 0) ;- (TDES) DATRDY +AT91C_TDES_ENDRX EQU (0x1 << 1) ;- (TDES) PDC Read Buffer End +AT91C_TDES_ENDTX EQU (0x1 << 2) ;- (TDES) PDC Write Buffer End +AT91C_TDES_RXBUFF EQU (0x1 << 3) ;- (TDES) PDC Read Buffer Full +AT91C_TDES_TXBUFE EQU (0x1 << 4) ;- (TDES) PDC Write Buffer Empty +AT91C_TDES_URAD EQU (0x1 << 8) ;- (TDES) Unspecified Register Access Detection +// - -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- +// - -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- +// - -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- +AT91C_TDES_URAT EQU (0x3 << 12) ;- (TDES) Unspecified Register Access Type Status +AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (TDES) Input data register written during the data processing in PDC mode. +AT91C_TDES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (TDES) Output data register read during the data processing. +AT91C_TDES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (TDES) Mode register written during the data processing. +AT91C_TDES_URAT_WO_REG_READ EQU (0x3 << 12) ;- (TDES) Write-only register read access. + +// - ***************************************************************************** +// - REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 +// - ***************************************************************************** +// - ========== Register definition for SYS peripheral ========== +// - ========== Register definition for AIC peripheral ========== +AT91C_AIC_IVR EQU (0xFFFFF100) ;- (AIC) IRQ Vector Register +AT91C_AIC_SMR EQU (0xFFFFF000) ;- (AIC) Source Mode Register +AT91C_AIC_FVR EQU (0xFFFFF104) ;- (AIC) FIQ Vector Register +AT91C_AIC_DCR EQU (0xFFFFF138) ;- (AIC) Debug Control Register (Protect) +AT91C_AIC_EOICR EQU (0xFFFFF130) ;- (AIC) End of Interrupt Command Register +AT91C_AIC_SVR EQU (0xFFFFF080) ;- (AIC) Source Vector Register +AT91C_AIC_FFSR EQU (0xFFFFF148) ;- (AIC) Fast Forcing Status Register +AT91C_AIC_ICCR EQU (0xFFFFF128) ;- (AIC) Interrupt Clear Command Register +AT91C_AIC_ISR EQU (0xFFFFF108) ;- (AIC) Interrupt Status Register +AT91C_AIC_IMR EQU (0xFFFFF110) ;- (AIC) Interrupt Mask Register +AT91C_AIC_IPR EQU (0xFFFFF10C) ;- (AIC) Interrupt Pending Register +AT91C_AIC_FFER EQU (0xFFFFF140) ;- (AIC) Fast Forcing Enable Register +AT91C_AIC_IECR EQU (0xFFFFF120) ;- (AIC) Interrupt Enable Command Register +AT91C_AIC_ISCR EQU (0xFFFFF12C) ;- (AIC) Interrupt Set Command Register +AT91C_AIC_FFDR EQU (0xFFFFF144) ;- (AIC) Fast Forcing Disable Register +AT91C_AIC_CISR EQU (0xFFFFF114) ;- (AIC) Core Interrupt Status Register +AT91C_AIC_IDCR EQU (0xFFFFF124) ;- (AIC) Interrupt Disable Command Register +AT91C_AIC_SPU EQU (0xFFFFF134) ;- (AIC) Spurious Vector Register +// - ========== Register definition for PDC_DBGU peripheral ========== +AT91C_DBGU_TCR EQU (0xFFFFF30C) ;- (PDC_DBGU) Transmit Counter Register +AT91C_DBGU_RNPR EQU (0xFFFFF310) ;- (PDC_DBGU) Receive Next Pointer Register +AT91C_DBGU_TNPR EQU (0xFFFFF318) ;- (PDC_DBGU) Transmit Next Pointer Register +AT91C_DBGU_TPR EQU (0xFFFFF308) ;- (PDC_DBGU) Transmit Pointer Register +AT91C_DBGU_RPR EQU (0xFFFFF300) ;- (PDC_DBGU) Receive Pointer Register +AT91C_DBGU_RCR EQU (0xFFFFF304) ;- (PDC_DBGU) Receive Counter Register +AT91C_DBGU_RNCR EQU (0xFFFFF314) ;- (PDC_DBGU) Receive Next Counter Register +AT91C_DBGU_PTCR EQU (0xFFFFF320) ;- (PDC_DBGU) PDC Transfer Control Register +AT91C_DBGU_PTSR EQU (0xFFFFF324) ;- (PDC_DBGU) PDC Transfer Status Register +AT91C_DBGU_TNCR EQU (0xFFFFF31C) ;- (PDC_DBGU) Transmit Next Counter Register +// - ========== Register definition for DBGU peripheral ========== +AT91C_DBGU_EXID EQU (0xFFFFF244) ;- (DBGU) Chip ID Extension Register +AT91C_DBGU_BRGR EQU (0xFFFFF220) ;- (DBGU) Baud Rate Generator Register +AT91C_DBGU_IDR EQU (0xFFFFF20C) ;- (DBGU) Interrupt Disable Register +AT91C_DBGU_CSR EQU (0xFFFFF214) ;- (DBGU) Channel Status Register +AT91C_DBGU_CIDR EQU (0xFFFFF240) ;- (DBGU) Chip ID Register +AT91C_DBGU_MR EQU (0xFFFFF204) ;- (DBGU) Mode Register +AT91C_DBGU_IMR EQU (0xFFFFF210) ;- (DBGU) Interrupt Mask Register +AT91C_DBGU_CR EQU (0xFFFFF200) ;- (DBGU) Control Register +AT91C_DBGU_FNTR EQU (0xFFFFF248) ;- (DBGU) Force NTRST Register +AT91C_DBGU_THR EQU (0xFFFFF21C) ;- (DBGU) Transmitter Holding Register +AT91C_DBGU_RHR EQU (0xFFFFF218) ;- (DBGU) Receiver Holding Register +AT91C_DBGU_IER EQU (0xFFFFF208) ;- (DBGU) Interrupt Enable Register +// - ========== Register definition for PIOA peripheral ========== +AT91C_PIOA_ODR EQU (0xFFFFF414) ;- (PIOA) Output Disable Registerr +AT91C_PIOA_SODR EQU (0xFFFFF430) ;- (PIOA) Set Output Data Register +AT91C_PIOA_ISR EQU (0xFFFFF44C) ;- (PIOA) Interrupt Status Register +AT91C_PIOA_ABSR EQU (0xFFFFF478) ;- (PIOA) AB Select Status Register +AT91C_PIOA_IER EQU (0xFFFFF440) ;- (PIOA) Interrupt Enable Register +AT91C_PIOA_PPUDR EQU (0xFFFFF460) ;- (PIOA) Pull-up Disable Register +AT91C_PIOA_IMR EQU (0xFFFFF448) ;- (PIOA) Interrupt Mask Register +AT91C_PIOA_PER EQU (0xFFFFF400) ;- (PIOA) PIO Enable Register +AT91C_PIOA_IFDR EQU (0xFFFFF424) ;- (PIOA) Input Filter Disable Register +AT91C_PIOA_OWDR EQU (0xFFFFF4A4) ;- (PIOA) Output Write Disable Register +AT91C_PIOA_MDSR EQU (0xFFFFF458) ;- (PIOA) Multi-driver Status Register +AT91C_PIOA_IDR EQU (0xFFFFF444) ;- (PIOA) Interrupt Disable Register +AT91C_PIOA_ODSR EQU (0xFFFFF438) ;- (PIOA) Output Data Status Register +AT91C_PIOA_PPUSR EQU (0xFFFFF468) ;- (PIOA) Pull-up Status Register +AT91C_PIOA_OWSR EQU (0xFFFFF4A8) ;- (PIOA) Output Write Status Register +AT91C_PIOA_BSR EQU (0xFFFFF474) ;- (PIOA) Select B Register +AT91C_PIOA_OWER EQU (0xFFFFF4A0) ;- (PIOA) Output Write Enable Register +AT91C_PIOA_IFER EQU (0xFFFFF420) ;- (PIOA) Input Filter Enable Register +AT91C_PIOA_PDSR EQU (0xFFFFF43C) ;- (PIOA) Pin Data Status Register +AT91C_PIOA_PPUER EQU (0xFFFFF464) ;- (PIOA) Pull-up Enable Register +AT91C_PIOA_OSR EQU (0xFFFFF418) ;- (PIOA) Output Status Register +AT91C_PIOA_ASR EQU (0xFFFFF470) ;- (PIOA) Select A Register +AT91C_PIOA_MDDR EQU (0xFFFFF454) ;- (PIOA) Multi-driver Disable Register +AT91C_PIOA_CODR EQU (0xFFFFF434) ;- (PIOA) Clear Output Data Register +AT91C_PIOA_MDER EQU (0xFFFFF450) ;- (PIOA) Multi-driver Enable Register +AT91C_PIOA_PDR EQU (0xFFFFF404) ;- (PIOA) PIO Disable Register +AT91C_PIOA_IFSR EQU (0xFFFFF428) ;- (PIOA) Input Filter Status Register +AT91C_PIOA_OER EQU (0xFFFFF410) ;- (PIOA) Output Enable Register +AT91C_PIOA_PSR EQU (0xFFFFF408) ;- (PIOA) PIO Status Register +// - ========== Register definition for PIOB peripheral ========== +AT91C_PIOB_OWDR EQU (0xFFFFF6A4) ;- (PIOB) Output Write Disable Register +AT91C_PIOB_MDER EQU (0xFFFFF650) ;- (PIOB) Multi-driver Enable Register +AT91C_PIOB_PPUSR EQU (0xFFFFF668) ;- (PIOB) Pull-up Status Register +AT91C_PIOB_IMR EQU (0xFFFFF648) ;- (PIOB) Interrupt Mask Register +AT91C_PIOB_ASR EQU (0xFFFFF670) ;- (PIOB) Select A Register +AT91C_PIOB_PPUDR EQU (0xFFFFF660) ;- (PIOB) Pull-up Disable Register +AT91C_PIOB_PSR EQU (0xFFFFF608) ;- (PIOB) PIO Status Register +AT91C_PIOB_IER EQU (0xFFFFF640) ;- (PIOB) Interrupt Enable Register +AT91C_PIOB_CODR EQU (0xFFFFF634) ;- (PIOB) Clear Output Data Register +AT91C_PIOB_OWER EQU (0xFFFFF6A0) ;- (PIOB) Output Write Enable Register +AT91C_PIOB_ABSR EQU (0xFFFFF678) ;- (PIOB) AB Select Status Register +AT91C_PIOB_IFDR EQU (0xFFFFF624) ;- (PIOB) Input Filter Disable Register +AT91C_PIOB_PDSR EQU (0xFFFFF63C) ;- (PIOB) Pin Data Status Register +AT91C_PIOB_IDR EQU (0xFFFFF644) ;- (PIOB) Interrupt Disable Register +AT91C_PIOB_OWSR EQU (0xFFFFF6A8) ;- (PIOB) Output Write Status Register +AT91C_PIOB_PDR EQU (0xFFFFF604) ;- (PIOB) PIO Disable Register +AT91C_PIOB_ODR EQU (0xFFFFF614) ;- (PIOB) Output Disable Registerr +AT91C_PIOB_IFSR EQU (0xFFFFF628) ;- (PIOB) Input Filter Status Register +AT91C_PIOB_PPUER EQU (0xFFFFF664) ;- (PIOB) Pull-up Enable Register +AT91C_PIOB_SODR EQU (0xFFFFF630) ;- (PIOB) Set Output Data Register +AT91C_PIOB_ISR EQU (0xFFFFF64C) ;- (PIOB) Interrupt Status Register +AT91C_PIOB_ODSR EQU (0xFFFFF638) ;- (PIOB) Output Data Status Register +AT91C_PIOB_OSR EQU (0xFFFFF618) ;- (PIOB) Output Status Register +AT91C_PIOB_MDSR EQU (0xFFFFF658) ;- (PIOB) Multi-driver Status Register +AT91C_PIOB_IFER EQU (0xFFFFF620) ;- (PIOB) Input Filter Enable Register +AT91C_PIOB_BSR EQU (0xFFFFF674) ;- (PIOB) Select B Register +AT91C_PIOB_MDDR EQU (0xFFFFF654) ;- (PIOB) Multi-driver Disable Register +AT91C_PIOB_OER EQU (0xFFFFF610) ;- (PIOB) Output Enable Register +AT91C_PIOB_PER EQU (0xFFFFF600) ;- (PIOB) PIO Enable Register +// - ========== Register definition for CKGR peripheral ========== +AT91C_CKGR_MOR EQU (0xFFFFFC20) ;- (CKGR) Main Oscillator Register +AT91C_CKGR_PLLR EQU (0xFFFFFC2C) ;- (CKGR) PLL Register +AT91C_CKGR_MCFR EQU (0xFFFFFC24) ;- (CKGR) Main Clock Frequency Register +// - ========== Register definition for PMC peripheral ========== +AT91C_PMC_IDR EQU (0xFFFFFC64) ;- (PMC) Interrupt Disable Register +AT91C_PMC_MOR EQU (0xFFFFFC20) ;- (PMC) Main Oscillator Register +AT91C_PMC_PLLR EQU (0xFFFFFC2C) ;- (PMC) PLL Register +AT91C_PMC_PCER EQU (0xFFFFFC10) ;- (PMC) Peripheral Clock Enable Register +AT91C_PMC_PCKR EQU (0xFFFFFC40) ;- (PMC) Programmable Clock Register +AT91C_PMC_MCKR EQU (0xFFFFFC30) ;- (PMC) Master Clock Register +AT91C_PMC_SCDR EQU (0xFFFFFC04) ;- (PMC) System Clock Disable Register +AT91C_PMC_PCDR EQU (0xFFFFFC14) ;- (PMC) Peripheral Clock Disable Register +AT91C_PMC_SCSR EQU (0xFFFFFC08) ;- (PMC) System Clock Status Register +AT91C_PMC_PCSR EQU (0xFFFFFC18) ;- (PMC) Peripheral Clock Status Register +AT91C_PMC_MCFR EQU (0xFFFFFC24) ;- (PMC) Main Clock Frequency Register +AT91C_PMC_SCER EQU (0xFFFFFC00) ;- (PMC) System Clock Enable Register +AT91C_PMC_IMR EQU (0xFFFFFC6C) ;- (PMC) Interrupt Mask Register +AT91C_PMC_IER EQU (0xFFFFFC60) ;- (PMC) Interrupt Enable Register +AT91C_PMC_SR EQU (0xFFFFFC68) ;- (PMC) Status Register +// - ========== Register definition for RSTC peripheral ========== +AT91C_RSTC_RCR EQU (0xFFFFFD00) ;- (RSTC) Reset Control Register +AT91C_RSTC_RMR EQU (0xFFFFFD08) ;- (RSTC) Reset Mode Register +AT91C_RSTC_RSR EQU (0xFFFFFD04) ;- (RSTC) Reset Status Register +// - ========== Register definition for RTTC peripheral ========== +AT91C_RTTC_RTSR EQU (0xFFFFFD2C) ;- (RTTC) Real-time Status Register +AT91C_RTTC_RTMR EQU (0xFFFFFD20) ;- (RTTC) Real-time Mode Register +AT91C_RTTC_RTVR EQU (0xFFFFFD28) ;- (RTTC) Real-time Value Register +AT91C_RTTC_RTAR EQU (0xFFFFFD24) ;- (RTTC) Real-time Alarm Register +// - ========== Register definition for PITC peripheral ========== +AT91C_PITC_PIVR EQU (0xFFFFFD38) ;- (PITC) Period Interval Value Register +AT91C_PITC_PISR EQU (0xFFFFFD34) ;- (PITC) Period Interval Status Register +AT91C_PITC_PIIR EQU (0xFFFFFD3C) ;- (PITC) Period Interval Image Register +AT91C_PITC_PIMR EQU (0xFFFFFD30) ;- (PITC) Period Interval Mode Register +// - ========== Register definition for WDTC peripheral ========== +AT91C_WDTC_WDCR EQU (0xFFFFFD40) ;- (WDTC) Watchdog Control Register +AT91C_WDTC_WDSR EQU (0xFFFFFD48) ;- (WDTC) Watchdog Status Register +AT91C_WDTC_WDMR EQU (0xFFFFFD44) ;- (WDTC) Watchdog Mode Register +// - ========== Register definition for VREG peripheral ========== +AT91C_VREG_MR EQU (0xFFFFFD60) ;- (VREG) Voltage Regulator Mode Register +// - ========== Register definition for MC peripheral ========== +AT91C_MC_ASR EQU (0xFFFFFF04) ;- (MC) MC Abort Status Register +AT91C_MC_RCR EQU (0xFFFFFF00) ;- (MC) MC Remap Control Register +AT91C_MC_FCR EQU (0xFFFFFF64) ;- (MC) MC Flash Command Register +AT91C_MC_AASR EQU (0xFFFFFF08) ;- (MC) MC Abort Address Status Register +AT91C_MC_FSR EQU (0xFFFFFF68) ;- (MC) MC Flash Status Register +AT91C_MC_FMR EQU (0xFFFFFF60) ;- (MC) MC Flash Mode Register +// - ========== Register definition for PDC_SPI1 peripheral ========== +AT91C_SPI1_PTCR EQU (0xFFFE4120) ;- (PDC_SPI1) PDC Transfer Control Register +AT91C_SPI1_RPR EQU (0xFFFE4100) ;- (PDC_SPI1) Receive Pointer Register +AT91C_SPI1_TNCR EQU (0xFFFE411C) ;- (PDC_SPI1) Transmit Next Counter Register +AT91C_SPI1_TPR EQU (0xFFFE4108) ;- (PDC_SPI1) Transmit Pointer Register +AT91C_SPI1_TNPR EQU (0xFFFE4118) ;- (PDC_SPI1) Transmit Next Pointer Register +AT91C_SPI1_TCR EQU (0xFFFE410C) ;- (PDC_SPI1) Transmit Counter Register +AT91C_SPI1_RCR EQU (0xFFFE4104) ;- (PDC_SPI1) Receive Counter Register +AT91C_SPI1_RNPR EQU (0xFFFE4110) ;- (PDC_SPI1) Receive Next Pointer Register +AT91C_SPI1_RNCR EQU (0xFFFE4114) ;- (PDC_SPI1) Receive Next Counter Register +AT91C_SPI1_PTSR EQU (0xFFFE4124) ;- (PDC_SPI1) PDC Transfer Status Register +// - ========== Register definition for SPI1 peripheral ========== +AT91C_SPI1_IMR EQU (0xFFFE401C) ;- (SPI1) Interrupt Mask Register +AT91C_SPI1_IER EQU (0xFFFE4014) ;- (SPI1) Interrupt Enable Register +AT91C_SPI1_MR EQU (0xFFFE4004) ;- (SPI1) Mode Register +AT91C_SPI1_RDR EQU (0xFFFE4008) ;- (SPI1) Receive Data Register +AT91C_SPI1_IDR EQU (0xFFFE4018) ;- (SPI1) Interrupt Disable Register +AT91C_SPI1_SR EQU (0xFFFE4010) ;- (SPI1) Status Register +AT91C_SPI1_TDR EQU (0xFFFE400C) ;- (SPI1) Transmit Data Register +AT91C_SPI1_CR EQU (0xFFFE4000) ;- (SPI1) Control Register +AT91C_SPI1_CSR EQU (0xFFFE4030) ;- (SPI1) Chip Select Register +// - ========== Register definition for PDC_SPI0 peripheral ========== +AT91C_SPI0_PTCR EQU (0xFFFE0120) ;- (PDC_SPI0) PDC Transfer Control Register +AT91C_SPI0_TPR EQU (0xFFFE0108) ;- (PDC_SPI0) Transmit Pointer Register +AT91C_SPI0_TCR EQU (0xFFFE010C) ;- (PDC_SPI0) Transmit Counter Register +AT91C_SPI0_RCR EQU (0xFFFE0104) ;- (PDC_SPI0) Receive Counter Register +AT91C_SPI0_PTSR EQU (0xFFFE0124) ;- (PDC_SPI0) PDC Transfer Status Register +AT91C_SPI0_RNPR EQU (0xFFFE0110) ;- (PDC_SPI0) Receive Next Pointer Register +AT91C_SPI0_RPR EQU (0xFFFE0100) ;- (PDC_SPI0) Receive Pointer Register +AT91C_SPI0_TNCR EQU (0xFFFE011C) ;- (PDC_SPI0) Transmit Next Counter Register +AT91C_SPI0_RNCR EQU (0xFFFE0114) ;- (PDC_SPI0) Receive Next Counter Register +AT91C_SPI0_TNPR EQU (0xFFFE0118) ;- (PDC_SPI0) Transmit Next Pointer Register +// - ========== Register definition for SPI0 peripheral ========== +AT91C_SPI0_IER EQU (0xFFFE0014) ;- (SPI0) Interrupt Enable Register +AT91C_SPI0_SR EQU (0xFFFE0010) ;- (SPI0) Status Register +AT91C_SPI0_IDR EQU (0xFFFE0018) ;- (SPI0) Interrupt Disable Register +AT91C_SPI0_CR EQU (0xFFFE0000) ;- (SPI0) Control Register +AT91C_SPI0_MR EQU (0xFFFE0004) ;- (SPI0) Mode Register +AT91C_SPI0_IMR EQU (0xFFFE001C) ;- (SPI0) Interrupt Mask Register +AT91C_SPI0_TDR EQU (0xFFFE000C) ;- (SPI0) Transmit Data Register +AT91C_SPI0_RDR EQU (0xFFFE0008) ;- (SPI0) Receive Data Register +AT91C_SPI0_CSR EQU (0xFFFE0030) ;- (SPI0) Chip Select Register +// - ========== Register definition for PDC_US1 peripheral ========== +AT91C_US1_RNCR EQU (0xFFFC4114) ;- (PDC_US1) Receive Next Counter Register +AT91C_US1_PTCR EQU (0xFFFC4120) ;- (PDC_US1) PDC Transfer Control Register +AT91C_US1_TCR EQU (0xFFFC410C) ;- (PDC_US1) Transmit Counter Register +AT91C_US1_PTSR EQU (0xFFFC4124) ;- (PDC_US1) PDC Transfer Status Register +AT91C_US1_TNPR EQU (0xFFFC4118) ;- (PDC_US1) Transmit Next Pointer Register +AT91C_US1_RCR EQU (0xFFFC4104) ;- (PDC_US1) Receive Counter Register +AT91C_US1_RNPR EQU (0xFFFC4110) ;- (PDC_US1) Receive Next Pointer Register +AT91C_US1_RPR EQU (0xFFFC4100) ;- (PDC_US1) Receive Pointer Register +AT91C_US1_TNCR EQU (0xFFFC411C) ;- (PDC_US1) Transmit Next Counter Register +AT91C_US1_TPR EQU (0xFFFC4108) ;- (PDC_US1) Transmit Pointer Register +// - ========== Register definition for US1 peripheral ========== +AT91C_US1_IF EQU (0xFFFC404C) ;- (US1) IRDA_FILTER Register +AT91C_US1_NER EQU (0xFFFC4044) ;- (US1) Nb Errors Register +AT91C_US1_RTOR EQU (0xFFFC4024) ;- (US1) Receiver Time-out Register +AT91C_US1_CSR EQU (0xFFFC4014) ;- (US1) Channel Status Register +AT91C_US1_IDR EQU (0xFFFC400C) ;- (US1) Interrupt Disable Register +AT91C_US1_IER EQU (0xFFFC4008) ;- (US1) Interrupt Enable Register +AT91C_US1_THR EQU (0xFFFC401C) ;- (US1) Transmitter Holding Register +AT91C_US1_TTGR EQU (0xFFFC4028) ;- (US1) Transmitter Time-guard Register +AT91C_US1_RHR EQU (0xFFFC4018) ;- (US1) Receiver Holding Register +AT91C_US1_BRGR EQU (0xFFFC4020) ;- (US1) Baud Rate Generator Register +AT91C_US1_IMR EQU (0xFFFC4010) ;- (US1) Interrupt Mask Register +AT91C_US1_FIDI EQU (0xFFFC4040) ;- (US1) FI_DI_Ratio Register +AT91C_US1_CR EQU (0xFFFC4000) ;- (US1) Control Register +AT91C_US1_MR EQU (0xFFFC4004) ;- (US1) Mode Register +// - ========== Register definition for PDC_US0 peripheral ========== +AT91C_US0_TNPR EQU (0xFFFC0118) ;- (PDC_US0) Transmit Next Pointer Register +AT91C_US0_RNPR EQU (0xFFFC0110) ;- (PDC_US0) Receive Next Pointer Register +AT91C_US0_TCR EQU (0xFFFC010C) ;- (PDC_US0) Transmit Counter Register +AT91C_US0_PTCR EQU (0xFFFC0120) ;- (PDC_US0) PDC Transfer Control Register +AT91C_US0_PTSR EQU (0xFFFC0124) ;- (PDC_US0) PDC Transfer Status Register +AT91C_US0_TNCR EQU (0xFFFC011C) ;- (PDC_US0) Transmit Next Counter Register +AT91C_US0_TPR EQU (0xFFFC0108) ;- (PDC_US0) Transmit Pointer Register +AT91C_US0_RCR EQU (0xFFFC0104) ;- (PDC_US0) Receive Counter Register +AT91C_US0_RPR EQU (0xFFFC0100) ;- (PDC_US0) Receive Pointer Register +AT91C_US0_RNCR EQU (0xFFFC0114) ;- (PDC_US0) Receive Next Counter Register +// - ========== Register definition for US0 peripheral ========== +AT91C_US0_BRGR EQU (0xFFFC0020) ;- (US0) Baud Rate Generator Register +AT91C_US0_NER EQU (0xFFFC0044) ;- (US0) Nb Errors Register +AT91C_US0_CR EQU (0xFFFC0000) ;- (US0) Control Register +AT91C_US0_IMR EQU (0xFFFC0010) ;- (US0) Interrupt Mask Register +AT91C_US0_FIDI EQU (0xFFFC0040) ;- (US0) FI_DI_Ratio Register +AT91C_US0_TTGR EQU (0xFFFC0028) ;- (US0) Transmitter Time-guard Register +AT91C_US0_MR EQU (0xFFFC0004) ;- (US0) Mode Register +AT91C_US0_RTOR EQU (0xFFFC0024) ;- (US0) Receiver Time-out Register +AT91C_US0_CSR EQU (0xFFFC0014) ;- (US0) Channel Status Register +AT91C_US0_RHR EQU (0xFFFC0018) ;- (US0) Receiver Holding Register +AT91C_US0_IDR EQU (0xFFFC000C) ;- (US0) Interrupt Disable Register +AT91C_US0_THR EQU (0xFFFC001C) ;- (US0) Transmitter Holding Register +AT91C_US0_IF EQU (0xFFFC004C) ;- (US0) IRDA_FILTER Register +AT91C_US0_IER EQU (0xFFFC0008) ;- (US0) Interrupt Enable Register +// - ========== Register definition for PDC_SSC peripheral ========== +AT91C_SSC_TNCR EQU (0xFFFD411C) ;- (PDC_SSC) Transmit Next Counter Register +AT91C_SSC_RPR EQU (0xFFFD4100) ;- (PDC_SSC) Receive Pointer Register +AT91C_SSC_RNCR EQU (0xFFFD4114) ;- (PDC_SSC) Receive Next Counter Register +AT91C_SSC_TPR EQU (0xFFFD4108) ;- (PDC_SSC) Transmit Pointer Register +AT91C_SSC_PTCR EQU (0xFFFD4120) ;- (PDC_SSC) PDC Transfer Control Register +AT91C_SSC_TCR EQU (0xFFFD410C) ;- (PDC_SSC) Transmit Counter Register +AT91C_SSC_RCR EQU (0xFFFD4104) ;- (PDC_SSC) Receive Counter Register +AT91C_SSC_RNPR EQU (0xFFFD4110) ;- (PDC_SSC) Receive Next Pointer Register +AT91C_SSC_TNPR EQU (0xFFFD4118) ;- (PDC_SSC) Transmit Next Pointer Register +AT91C_SSC_PTSR EQU (0xFFFD4124) ;- (PDC_SSC) PDC Transfer Status Register +// - ========== Register definition for SSC peripheral ========== +AT91C_SSC_RHR EQU (0xFFFD4020) ;- (SSC) Receive Holding Register +AT91C_SSC_RSHR EQU (0xFFFD4030) ;- (SSC) Receive Sync Holding Register +AT91C_SSC_TFMR EQU (0xFFFD401C) ;- (SSC) Transmit Frame Mode Register +AT91C_SSC_IDR EQU (0xFFFD4048) ;- (SSC) Interrupt Disable Register +AT91C_SSC_THR EQU (0xFFFD4024) ;- (SSC) Transmit Holding Register +AT91C_SSC_RCMR EQU (0xFFFD4010) ;- (SSC) Receive Clock ModeRegister +AT91C_SSC_IER EQU (0xFFFD4044) ;- (SSC) Interrupt Enable Register +AT91C_SSC_TSHR EQU (0xFFFD4034) ;- (SSC) Transmit Sync Holding Register +AT91C_SSC_SR EQU (0xFFFD4040) ;- (SSC) Status Register +AT91C_SSC_CMR EQU (0xFFFD4004) ;- (SSC) Clock Mode Register +AT91C_SSC_TCMR EQU (0xFFFD4018) ;- (SSC) Transmit Clock Mode Register +AT91C_SSC_CR EQU (0xFFFD4000) ;- (SSC) Control Register +AT91C_SSC_IMR EQU (0xFFFD404C) ;- (SSC) Interrupt Mask Register +AT91C_SSC_RFMR EQU (0xFFFD4014) ;- (SSC) Receive Frame Mode Register +// - ========== Register definition for TWI peripheral ========== +AT91C_TWI_IER EQU (0xFFFB8024) ;- (TWI) Interrupt Enable Register +AT91C_TWI_CR EQU (0xFFFB8000) ;- (TWI) Control Register +AT91C_TWI_SR EQU (0xFFFB8020) ;- (TWI) Status Register +AT91C_TWI_IMR EQU (0xFFFB802C) ;- (TWI) Interrupt Mask Register +AT91C_TWI_THR EQU (0xFFFB8034) ;- (TWI) Transmit Holding Register +AT91C_TWI_IDR EQU (0xFFFB8028) ;- (TWI) Interrupt Disable Register +AT91C_TWI_IADR EQU (0xFFFB800C) ;- (TWI) Internal Address Register +AT91C_TWI_MMR EQU (0xFFFB8004) ;- (TWI) Master Mode Register +AT91C_TWI_CWGR EQU (0xFFFB8010) ;- (TWI) Clock Waveform Generator Register +AT91C_TWI_RHR EQU (0xFFFB8030) ;- (TWI) Receive Holding Register +// - ========== Register definition for PWMC_CH3 peripheral ========== +AT91C_PWMC_CH3_CUPDR EQU (0xFFFCC270) ;- (PWMC_CH3) Channel Update Register +AT91C_PWMC_CH3_Reserved EQU (0xFFFCC274) ;- (PWMC_CH3) Reserved +AT91C_PWMC_CH3_CPRDR EQU (0xFFFCC268) ;- (PWMC_CH3) Channel Period Register +AT91C_PWMC_CH3_CDTYR EQU (0xFFFCC264) ;- (PWMC_CH3) Channel Duty Cycle Register +AT91C_PWMC_CH3_CCNTR EQU (0xFFFCC26C) ;- (PWMC_CH3) Channel Counter Register +AT91C_PWMC_CH3_CMR EQU (0xFFFCC260) ;- (PWMC_CH3) Channel Mode Register +// - ========== Register definition for PWMC_CH2 peripheral ========== +AT91C_PWMC_CH2_Reserved EQU (0xFFFCC254) ;- (PWMC_CH2) Reserved +AT91C_PWMC_CH2_CMR EQU (0xFFFCC240) ;- (PWMC_CH2) Channel Mode Register +AT91C_PWMC_CH2_CCNTR EQU (0xFFFCC24C) ;- (PWMC_CH2) Channel Counter Register +AT91C_PWMC_CH2_CPRDR EQU (0xFFFCC248) ;- (PWMC_CH2) Channel Period Register +AT91C_PWMC_CH2_CUPDR EQU (0xFFFCC250) ;- (PWMC_CH2) Channel Update Register +AT91C_PWMC_CH2_CDTYR EQU (0xFFFCC244) ;- (PWMC_CH2) Channel Duty Cycle Register +// - ========== Register definition for PWMC_CH1 peripheral ========== +AT91C_PWMC_CH1_Reserved EQU (0xFFFCC234) ;- (PWMC_CH1) Reserved +AT91C_PWMC_CH1_CUPDR EQU (0xFFFCC230) ;- (PWMC_CH1) Channel Update Register +AT91C_PWMC_CH1_CPRDR EQU (0xFFFCC228) ;- (PWMC_CH1) Channel Period Register +AT91C_PWMC_CH1_CCNTR EQU (0xFFFCC22C) ;- (PWMC_CH1) Channel Counter Register +AT91C_PWMC_CH1_CDTYR EQU (0xFFFCC224) ;- (PWMC_CH1) Channel Duty Cycle Register +AT91C_PWMC_CH1_CMR EQU (0xFFFCC220) ;- (PWMC_CH1) Channel Mode Register +// - ========== Register definition for PWMC_CH0 peripheral ========== +AT91C_PWMC_CH0_Reserved EQU (0xFFFCC214) ;- (PWMC_CH0) Reserved +AT91C_PWMC_CH0_CPRDR EQU (0xFFFCC208) ;- (PWMC_CH0) Channel Period Register +AT91C_PWMC_CH0_CDTYR EQU (0xFFFCC204) ;- (PWMC_CH0) Channel Duty Cycle Register +AT91C_PWMC_CH0_CMR EQU (0xFFFCC200) ;- (PWMC_CH0) Channel Mode Register +AT91C_PWMC_CH0_CUPDR EQU (0xFFFCC210) ;- (PWMC_CH0) Channel Update Register +AT91C_PWMC_CH0_CCNTR EQU (0xFFFCC20C) ;- (PWMC_CH0) Channel Counter Register +// - ========== Register definition for PWMC peripheral ========== +AT91C_PWMC_IDR EQU (0xFFFCC014) ;- (PWMC) PWMC Interrupt Disable Register +AT91C_PWMC_DIS EQU (0xFFFCC008) ;- (PWMC) PWMC Disable Register +AT91C_PWMC_IER EQU (0xFFFCC010) ;- (PWMC) PWMC Interrupt Enable Register +AT91C_PWMC_VR EQU (0xFFFCC0FC) ;- (PWMC) PWMC Version Register +AT91C_PWMC_ISR EQU (0xFFFCC01C) ;- (PWMC) PWMC Interrupt Status Register +AT91C_PWMC_SR EQU (0xFFFCC00C) ;- (PWMC) PWMC Status Register +AT91C_PWMC_IMR EQU (0xFFFCC018) ;- (PWMC) PWMC Interrupt Mask Register +AT91C_PWMC_MR EQU (0xFFFCC000) ;- (PWMC) PWMC Mode Register +AT91C_PWMC_ENA EQU (0xFFFCC004) ;- (PWMC) PWMC Enable Register +// - ========== Register definition for UDP peripheral ========== +AT91C_UDP_IMR EQU (0xFFFB0018) ;- (UDP) Interrupt Mask Register +AT91C_UDP_FADDR EQU (0xFFFB0008) ;- (UDP) Function Address Register +AT91C_UDP_NUM EQU (0xFFFB0000) ;- (UDP) Frame Number Register +AT91C_UDP_FDR EQU (0xFFFB0050) ;- (UDP) Endpoint FIFO Data Register +AT91C_UDP_ISR EQU (0xFFFB001C) ;- (UDP) Interrupt Status Register +AT91C_UDP_CSR EQU (0xFFFB0030) ;- (UDP) Endpoint Control and Status Register +AT91C_UDP_IDR EQU (0xFFFB0014) ;- (UDP) Interrupt Disable Register +AT91C_UDP_ICR EQU (0xFFFB0020) ;- (UDP) Interrupt Clear Register +AT91C_UDP_RSTEP EQU (0xFFFB0028) ;- (UDP) Reset Endpoint Register +AT91C_UDP_TXVC EQU (0xFFFB0074) ;- (UDP) Transceiver Control Register +AT91C_UDP_GLBSTATE EQU (0xFFFB0004) ;- (UDP) Global State Register +AT91C_UDP_IER EQU (0xFFFB0010) ;- (UDP) Interrupt Enable Register +// - ========== Register definition for TC0 peripheral ========== +AT91C_TC0_SR EQU (0xFFFA0020) ;- (TC0) Status Register +AT91C_TC0_RC EQU (0xFFFA001C) ;- (TC0) Register C +AT91C_TC0_RB EQU (0xFFFA0018) ;- (TC0) Register B +AT91C_TC0_CCR EQU (0xFFFA0000) ;- (TC0) Channel Control Register +AT91C_TC0_CMR EQU (0xFFFA0004) ;- (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +AT91C_TC0_IER EQU (0xFFFA0024) ;- (TC0) Interrupt Enable Register +AT91C_TC0_RA EQU (0xFFFA0014) ;- (TC0) Register A +AT91C_TC0_IDR EQU (0xFFFA0028) ;- (TC0) Interrupt Disable Register +AT91C_TC0_CV EQU (0xFFFA0010) ;- (TC0) Counter Value +AT91C_TC0_IMR EQU (0xFFFA002C) ;- (TC0) Interrupt Mask Register +// - ========== Register definition for TC1 peripheral ========== +AT91C_TC1_RB EQU (0xFFFA0058) ;- (TC1) Register B +AT91C_TC1_CCR EQU (0xFFFA0040) ;- (TC1) Channel Control Register +AT91C_TC1_IER EQU (0xFFFA0064) ;- (TC1) Interrupt Enable Register +AT91C_TC1_IDR EQU (0xFFFA0068) ;- (TC1) Interrupt Disable Register +AT91C_TC1_SR EQU (0xFFFA0060) ;- (TC1) Status Register +AT91C_TC1_CMR EQU (0xFFFA0044) ;- (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +AT91C_TC1_RA EQU (0xFFFA0054) ;- (TC1) Register A +AT91C_TC1_RC EQU (0xFFFA005C) ;- (TC1) Register C +AT91C_TC1_IMR EQU (0xFFFA006C) ;- (TC1) Interrupt Mask Register +AT91C_TC1_CV EQU (0xFFFA0050) ;- (TC1) Counter Value +// - ========== Register definition for TC2 peripheral ========== +AT91C_TC2_CMR EQU (0xFFFA0084) ;- (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +AT91C_TC2_CCR EQU (0xFFFA0080) ;- (TC2) Channel Control Register +AT91C_TC2_CV EQU (0xFFFA0090) ;- (TC2) Counter Value +AT91C_TC2_RA EQU (0xFFFA0094) ;- (TC2) Register A +AT91C_TC2_RB EQU (0xFFFA0098) ;- (TC2) Register B +AT91C_TC2_IDR EQU (0xFFFA00A8) ;- (TC2) Interrupt Disable Register +AT91C_TC2_IMR EQU (0xFFFA00AC) ;- (TC2) Interrupt Mask Register +AT91C_TC2_RC EQU (0xFFFA009C) ;- (TC2) Register C +AT91C_TC2_IER EQU (0xFFFA00A4) ;- (TC2) Interrupt Enable Register +AT91C_TC2_SR EQU (0xFFFA00A0) ;- (TC2) Status Register +// - ========== Register definition for TCB peripheral ========== +AT91C_TCB_BMR EQU (0xFFFA00C4) ;- (TCB) TC Block Mode Register +AT91C_TCB_BCR EQU (0xFFFA00C0) ;- (TCB) TC Block Control Register +// - ========== Register definition for CAN_MB0 peripheral ========== +AT91C_CAN_MB0_MDL EQU (0xFFFD0214) ;- (CAN_MB0) MailBox Data Low Register +AT91C_CAN_MB0_MAM EQU (0xFFFD0204) ;- (CAN_MB0) MailBox Acceptance Mask Register +AT91C_CAN_MB0_MCR EQU (0xFFFD021C) ;- (CAN_MB0) MailBox Control Register +AT91C_CAN_MB0_MID EQU (0xFFFD0208) ;- (CAN_MB0) MailBox ID Register +AT91C_CAN_MB0_MSR EQU (0xFFFD0210) ;- (CAN_MB0) MailBox Status Register +AT91C_CAN_MB0_MFID EQU (0xFFFD020C) ;- (CAN_MB0) MailBox Family ID Register +AT91C_CAN_MB0_MDH EQU (0xFFFD0218) ;- (CAN_MB0) MailBox Data High Register +AT91C_CAN_MB0_MMR EQU (0xFFFD0200) ;- (CAN_MB0) MailBox Mode Register +// - ========== Register definition for CAN_MB1 peripheral ========== +AT91C_CAN_MB1_MDL EQU (0xFFFD0234) ;- (CAN_MB1) MailBox Data Low Register +AT91C_CAN_MB1_MID EQU (0xFFFD0228) ;- (CAN_MB1) MailBox ID Register +AT91C_CAN_MB1_MMR EQU (0xFFFD0220) ;- (CAN_MB1) MailBox Mode Register +AT91C_CAN_MB1_MSR EQU (0xFFFD0230) ;- (CAN_MB1) MailBox Status Register +AT91C_CAN_MB1_MAM EQU (0xFFFD0224) ;- (CAN_MB1) MailBox Acceptance Mask Register +AT91C_CAN_MB1_MDH EQU (0xFFFD0238) ;- (CAN_MB1) MailBox Data High Register +AT91C_CAN_MB1_MCR EQU (0xFFFD023C) ;- (CAN_MB1) MailBox Control Register +AT91C_CAN_MB1_MFID EQU (0xFFFD022C) ;- (CAN_MB1) MailBox Family ID Register +// - ========== Register definition for CAN_MB2 peripheral ========== +AT91C_CAN_MB2_MCR EQU (0xFFFD025C) ;- (CAN_MB2) MailBox Control Register +AT91C_CAN_MB2_MDH EQU (0xFFFD0258) ;- (CAN_MB2) MailBox Data High Register +AT91C_CAN_MB2_MID EQU (0xFFFD0248) ;- (CAN_MB2) MailBox ID Register +AT91C_CAN_MB2_MDL EQU (0xFFFD0254) ;- (CAN_MB2) MailBox Data Low Register +AT91C_CAN_MB2_MMR EQU (0xFFFD0240) ;- (CAN_MB2) MailBox Mode Register +AT91C_CAN_MB2_MAM EQU (0xFFFD0244) ;- (CAN_MB2) MailBox Acceptance Mask Register +AT91C_CAN_MB2_MFID EQU (0xFFFD024C) ;- (CAN_MB2) MailBox Family ID Register +AT91C_CAN_MB2_MSR EQU (0xFFFD0250) ;- (CAN_MB2) MailBox Status Register +// - ========== Register definition for CAN_MB3 peripheral ========== +AT91C_CAN_MB3_MFID EQU (0xFFFD026C) ;- (CAN_MB3) MailBox Family ID Register +AT91C_CAN_MB3_MAM EQU (0xFFFD0264) ;- (CAN_MB3) MailBox Acceptance Mask Register +AT91C_CAN_MB3_MID EQU (0xFFFD0268) ;- (CAN_MB3) MailBox ID Register +AT91C_CAN_MB3_MCR EQU (0xFFFD027C) ;- (CAN_MB3) MailBox Control Register +AT91C_CAN_MB3_MMR EQU (0xFFFD0260) ;- (CAN_MB3) MailBox Mode Register +AT91C_CAN_MB3_MSR EQU (0xFFFD0270) ;- (CAN_MB3) MailBox Status Register +AT91C_CAN_MB3_MDL EQU (0xFFFD0274) ;- (CAN_MB3) MailBox Data Low Register +AT91C_CAN_MB3_MDH EQU (0xFFFD0278) ;- (CAN_MB3) MailBox Data High Register +// - ========== Register definition for CAN_MB4 peripheral ========== +AT91C_CAN_MB4_MID EQU (0xFFFD0288) ;- (CAN_MB4) MailBox ID Register +AT91C_CAN_MB4_MMR EQU (0xFFFD0280) ;- (CAN_MB4) MailBox Mode Register +AT91C_CAN_MB4_MDH EQU (0xFFFD0298) ;- (CAN_MB4) MailBox Data High Register +AT91C_CAN_MB4_MFID EQU (0xFFFD028C) ;- (CAN_MB4) MailBox Family ID Register +AT91C_CAN_MB4_MSR EQU (0xFFFD0290) ;- (CAN_MB4) MailBox Status Register +AT91C_CAN_MB4_MCR EQU (0xFFFD029C) ;- (CAN_MB4) MailBox Control Register +AT91C_CAN_MB4_MDL EQU (0xFFFD0294) ;- (CAN_MB4) MailBox Data Low Register +AT91C_CAN_MB4_MAM EQU (0xFFFD0284) ;- (CAN_MB4) MailBox Acceptance Mask Register +// - ========== Register definition for CAN_MB5 peripheral ========== +AT91C_CAN_MB5_MSR EQU (0xFFFD02B0) ;- (CAN_MB5) MailBox Status Register +AT91C_CAN_MB5_MCR EQU (0xFFFD02BC) ;- (CAN_MB5) MailBox Control Register +AT91C_CAN_MB5_MFID EQU (0xFFFD02AC) ;- (CAN_MB5) MailBox Family ID Register +AT91C_CAN_MB5_MDH EQU (0xFFFD02B8) ;- (CAN_MB5) MailBox Data High Register +AT91C_CAN_MB5_MID EQU (0xFFFD02A8) ;- (CAN_MB5) MailBox ID Register +AT91C_CAN_MB5_MMR EQU (0xFFFD02A0) ;- (CAN_MB5) MailBox Mode Register +AT91C_CAN_MB5_MDL EQU (0xFFFD02B4) ;- (CAN_MB5) MailBox Data Low Register +AT91C_CAN_MB5_MAM EQU (0xFFFD02A4) ;- (CAN_MB5) MailBox Acceptance Mask Register +// - ========== Register definition for CAN_MB6 peripheral ========== +AT91C_CAN_MB6_MFID EQU (0xFFFD02CC) ;- (CAN_MB6) MailBox Family ID Register +AT91C_CAN_MB6_MID EQU (0xFFFD02C8) ;- (CAN_MB6) MailBox ID Register +AT91C_CAN_MB6_MAM EQU (0xFFFD02C4) ;- (CAN_MB6) MailBox Acceptance Mask Register +AT91C_CAN_MB6_MSR EQU (0xFFFD02D0) ;- (CAN_MB6) MailBox Status Register +AT91C_CAN_MB6_MDL EQU (0xFFFD02D4) ;- (CAN_MB6) MailBox Data Low Register +AT91C_CAN_MB6_MCR EQU (0xFFFD02DC) ;- (CAN_MB6) MailBox Control Register +AT91C_CAN_MB6_MDH EQU (0xFFFD02D8) ;- (CAN_MB6) MailBox Data High Register +AT91C_CAN_MB6_MMR EQU (0xFFFD02C0) ;- (CAN_MB6) MailBox Mode Register +// - ========== Register definition for CAN_MB7 peripheral ========== +AT91C_CAN_MB7_MCR EQU (0xFFFD02FC) ;- (CAN_MB7) MailBox Control Register +AT91C_CAN_MB7_MDH EQU (0xFFFD02F8) ;- (CAN_MB7) MailBox Data High Register +AT91C_CAN_MB7_MFID EQU (0xFFFD02EC) ;- (CAN_MB7) MailBox Family ID Register +AT91C_CAN_MB7_MDL EQU (0xFFFD02F4) ;- (CAN_MB7) MailBox Data Low Register +AT91C_CAN_MB7_MID EQU (0xFFFD02E8) ;- (CAN_MB7) MailBox ID Register +AT91C_CAN_MB7_MMR EQU (0xFFFD02E0) ;- (CAN_MB7) MailBox Mode Register +AT91C_CAN_MB7_MAM EQU (0xFFFD02E4) ;- (CAN_MB7) MailBox Acceptance Mask Register +AT91C_CAN_MB7_MSR EQU (0xFFFD02F0) ;- (CAN_MB7) MailBox Status Register +// - ========== Register definition for CAN peripheral ========== +AT91C_CAN_TCR EQU (0xFFFD0024) ;- (CAN) Transfer Command Register +AT91C_CAN_IMR EQU (0xFFFD000C) ;- (CAN) Interrupt Mask Register +AT91C_CAN_IER EQU (0xFFFD0004) ;- (CAN) Interrupt Enable Register +AT91C_CAN_ECR EQU (0xFFFD0020) ;- (CAN) Error Counter Register +AT91C_CAN_TIMESTP EQU (0xFFFD001C) ;- (CAN) Time Stamp Register +AT91C_CAN_MR EQU (0xFFFD0000) ;- (CAN) Mode Register +AT91C_CAN_IDR EQU (0xFFFD0008) ;- (CAN) Interrupt Disable Register +AT91C_CAN_ACR EQU (0xFFFD0028) ;- (CAN) Abort Command Register +AT91C_CAN_TIM EQU (0xFFFD0018) ;- (CAN) Timer Register +AT91C_CAN_SR EQU (0xFFFD0010) ;- (CAN) Status Register +AT91C_CAN_BR EQU (0xFFFD0014) ;- (CAN) Baudrate Register +AT91C_CAN_VR EQU (0xFFFD00FC) ;- (CAN) Version Register +// - ========== Register definition for EMAC peripheral ========== +AT91C_EMAC_ISR EQU (0xFFFDC024) ;- (EMAC) Interrupt Status Register +AT91C_EMAC_SA4H EQU (0xFFFDC0B4) ;- (EMAC) Specific Address 4 Top, Last 2 bytes +AT91C_EMAC_SA1L EQU (0xFFFDC098) ;- (EMAC) Specific Address 1 Bottom, First 4 bytes +AT91C_EMAC_ELE EQU (0xFFFDC078) ;- (EMAC) Excessive Length Errors Register +AT91C_EMAC_LCOL EQU (0xFFFDC05C) ;- (EMAC) Late Collision Register +AT91C_EMAC_RLE EQU (0xFFFDC088) ;- (EMAC) Receive Length Field Mismatch Register +AT91C_EMAC_WOL EQU (0xFFFDC0C4) ;- (EMAC) Wake On LAN Register +AT91C_EMAC_DTF EQU (0xFFFDC058) ;- (EMAC) Deferred Transmission Frame Register +AT91C_EMAC_TUND EQU (0xFFFDC064) ;- (EMAC) Transmit Underrun Error Register +AT91C_EMAC_NCR EQU (0xFFFDC000) ;- (EMAC) Network Control Register +AT91C_EMAC_SA4L EQU (0xFFFDC0B0) ;- (EMAC) Specific Address 4 Bottom, First 4 bytes +AT91C_EMAC_RSR EQU (0xFFFDC020) ;- (EMAC) Receive Status Register +AT91C_EMAC_SA3L EQU (0xFFFDC0A8) ;- (EMAC) Specific Address 3 Bottom, First 4 bytes +AT91C_EMAC_TSR EQU (0xFFFDC014) ;- (EMAC) Transmit Status Register +AT91C_EMAC_IDR EQU (0xFFFDC02C) ;- (EMAC) Interrupt Disable Register +AT91C_EMAC_RSE EQU (0xFFFDC074) ;- (EMAC) Receive Symbol Errors Register +AT91C_EMAC_ECOL EQU (0xFFFDC060) ;- (EMAC) Excessive Collision Register +AT91C_EMAC_TID EQU (0xFFFDC0B8) ;- (EMAC) Type ID Checking Register +AT91C_EMAC_HRB EQU (0xFFFDC090) ;- (EMAC) Hash Address Bottom[31:0] +AT91C_EMAC_TBQP EQU (0xFFFDC01C) ;- (EMAC) Transmit Buffer Queue Pointer +AT91C_EMAC_USRIO EQU (0xFFFDC0C0) ;- (EMAC) USER Input/Output Register +AT91C_EMAC_PTR EQU (0xFFFDC038) ;- (EMAC) Pause Time Register +AT91C_EMAC_SA2H EQU (0xFFFDC0A4) ;- (EMAC) Specific Address 2 Top, Last 2 bytes +AT91C_EMAC_ROV EQU (0xFFFDC070) ;- (EMAC) Receive Overrun Errors Register +AT91C_EMAC_ALE EQU (0xFFFDC054) ;- (EMAC) Alignment Error Register +AT91C_EMAC_RJA EQU (0xFFFDC07C) ;- (EMAC) Receive Jabbers Register +AT91C_EMAC_RBQP EQU (0xFFFDC018) ;- (EMAC) Receive Buffer Queue Pointer +AT91C_EMAC_TPF EQU (0xFFFDC08C) ;- (EMAC) Transmitted Pause Frames Register +AT91C_EMAC_NCFGR EQU (0xFFFDC004) ;- (EMAC) Network Configuration Register +AT91C_EMAC_HRT EQU (0xFFFDC094) ;- (EMAC) Hash Address Top[63:32] +AT91C_EMAC_USF EQU (0xFFFDC080) ;- (EMAC) Undersize Frames Register +AT91C_EMAC_FCSE EQU (0xFFFDC050) ;- (EMAC) Frame Check Sequence Error Register +AT91C_EMAC_TPQ EQU (0xFFFDC0BC) ;- (EMAC) Transmit Pause Quantum Register +AT91C_EMAC_MAN EQU (0xFFFDC034) ;- (EMAC) PHY Maintenance Register +AT91C_EMAC_FTO EQU (0xFFFDC040) ;- (EMAC) Frames Transmitted OK Register +AT91C_EMAC_REV EQU (0xFFFDC0FC) ;- (EMAC) Revision Register +AT91C_EMAC_IMR EQU (0xFFFDC030) ;- (EMAC) Interrupt Mask Register +AT91C_EMAC_SCF EQU (0xFFFDC044) ;- (EMAC) Single Collision Frame Register +AT91C_EMAC_PFR EQU (0xFFFDC03C) ;- (EMAC) Pause Frames received Register +AT91C_EMAC_MCF EQU (0xFFFDC048) ;- (EMAC) Multiple Collision Frame Register +AT91C_EMAC_NSR EQU (0xFFFDC008) ;- (EMAC) Network Status Register +AT91C_EMAC_SA2L EQU (0xFFFDC0A0) ;- (EMAC) Specific Address 2 Bottom, First 4 bytes +AT91C_EMAC_FRO EQU (0xFFFDC04C) ;- (EMAC) Frames Received OK Register +AT91C_EMAC_IER EQU (0xFFFDC028) ;- (EMAC) Interrupt Enable Register +AT91C_EMAC_SA1H EQU (0xFFFDC09C) ;- (EMAC) Specific Address 1 Top, Last 2 bytes +AT91C_EMAC_CSE EQU (0xFFFDC068) ;- (EMAC) Carrier Sense Error Register +AT91C_EMAC_SA3H EQU (0xFFFDC0AC) ;- (EMAC) Specific Address 3 Top, Last 2 bytes +AT91C_EMAC_RRE EQU (0xFFFDC06C) ;- (EMAC) Receive Ressource Error Register +AT91C_EMAC_STE EQU (0xFFFDC084) ;- (EMAC) SQE Test Error Register +// - ========== Register definition for PDC_ADC peripheral ========== +AT91C_ADC_PTSR EQU (0xFFFD8124) ;- (PDC_ADC) PDC Transfer Status Register +AT91C_ADC_PTCR EQU (0xFFFD8120) ;- (PDC_ADC) PDC Transfer Control Register +AT91C_ADC_TNPR EQU (0xFFFD8118) ;- (PDC_ADC) Transmit Next Pointer Register +AT91C_ADC_TNCR EQU (0xFFFD811C) ;- (PDC_ADC) Transmit Next Counter Register +AT91C_ADC_RNPR EQU (0xFFFD8110) ;- (PDC_ADC) Receive Next Pointer Register +AT91C_ADC_RNCR EQU (0xFFFD8114) ;- (PDC_ADC) Receive Next Counter Register +AT91C_ADC_RPR EQU (0xFFFD8100) ;- (PDC_ADC) Receive Pointer Register +AT91C_ADC_TCR EQU (0xFFFD810C) ;- (PDC_ADC) Transmit Counter Register +AT91C_ADC_TPR EQU (0xFFFD8108) ;- (PDC_ADC) Transmit Pointer Register +AT91C_ADC_RCR EQU (0xFFFD8104) ;- (PDC_ADC) Receive Counter Register +// - ========== Register definition for ADC peripheral ========== +AT91C_ADC_CDR2 EQU (0xFFFD8038) ;- (ADC) ADC Channel Data Register 2 +AT91C_ADC_CDR3 EQU (0xFFFD803C) ;- (ADC) ADC Channel Data Register 3 +AT91C_ADC_CDR0 EQU (0xFFFD8030) ;- (ADC) ADC Channel Data Register 0 +AT91C_ADC_CDR5 EQU (0xFFFD8044) ;- (ADC) ADC Channel Data Register 5 +AT91C_ADC_CHDR EQU (0xFFFD8014) ;- (ADC) ADC Channel Disable Register +AT91C_ADC_SR EQU (0xFFFD801C) ;- (ADC) ADC Status Register +AT91C_ADC_CDR4 EQU (0xFFFD8040) ;- (ADC) ADC Channel Data Register 4 +AT91C_ADC_CDR1 EQU (0xFFFD8034) ;- (ADC) ADC Channel Data Register 1 +AT91C_ADC_LCDR EQU (0xFFFD8020) ;- (ADC) ADC Last Converted Data Register +AT91C_ADC_IDR EQU (0xFFFD8028) ;- (ADC) ADC Interrupt Disable Register +AT91C_ADC_CR EQU (0xFFFD8000) ;- (ADC) ADC Control Register +AT91C_ADC_CDR7 EQU (0xFFFD804C) ;- (ADC) ADC Channel Data Register 7 +AT91C_ADC_CDR6 EQU (0xFFFD8048) ;- (ADC) ADC Channel Data Register 6 +AT91C_ADC_IER EQU (0xFFFD8024) ;- (ADC) ADC Interrupt Enable Register +AT91C_ADC_CHER EQU (0xFFFD8010) ;- (ADC) ADC Channel Enable Register +AT91C_ADC_CHSR EQU (0xFFFD8018) ;- (ADC) ADC Channel Status Register +AT91C_ADC_MR EQU (0xFFFD8004) ;- (ADC) ADC Mode Register +AT91C_ADC_IMR EQU (0xFFFD802C) ;- (ADC) ADC Interrupt Mask Register +// - ========== Register definition for PDC_AES peripheral ========== +AT91C_AES_TPR EQU (0xFFFA4108) ;- (PDC_AES) Transmit Pointer Register +AT91C_AES_PTCR EQU (0xFFFA4120) ;- (PDC_AES) PDC Transfer Control Register +AT91C_AES_RNPR EQU (0xFFFA4110) ;- (PDC_AES) Receive Next Pointer Register +AT91C_AES_TNCR EQU (0xFFFA411C) ;- (PDC_AES) Transmit Next Counter Register +AT91C_AES_TCR EQU (0xFFFA410C) ;- (PDC_AES) Transmit Counter Register +AT91C_AES_RCR EQU (0xFFFA4104) ;- (PDC_AES) Receive Counter Register +AT91C_AES_RNCR EQU (0xFFFA4114) ;- (PDC_AES) Receive Next Counter Register +AT91C_AES_TNPR EQU (0xFFFA4118) ;- (PDC_AES) Transmit Next Pointer Register +AT91C_AES_RPR EQU (0xFFFA4100) ;- (PDC_AES) Receive Pointer Register +AT91C_AES_PTSR EQU (0xFFFA4124) ;- (PDC_AES) PDC Transfer Status Register +// - ========== Register definition for AES peripheral ========== +AT91C_AES_IVxR EQU (0xFFFA4060) ;- (AES) Initialization Vector x Register +AT91C_AES_MR EQU (0xFFFA4004) ;- (AES) Mode Register +AT91C_AES_VR EQU (0xFFFA40FC) ;- (AES) AES Version Register +AT91C_AES_ODATAxR EQU (0xFFFA4050) ;- (AES) Output Data x Register +AT91C_AES_IDATAxR EQU (0xFFFA4040) ;- (AES) Input Data x Register +AT91C_AES_CR EQU (0xFFFA4000) ;- (AES) Control Register +AT91C_AES_IDR EQU (0xFFFA4014) ;- (AES) Interrupt Disable Register +AT91C_AES_IMR EQU (0xFFFA4018) ;- (AES) Interrupt Mask Register +AT91C_AES_IER EQU (0xFFFA4010) ;- (AES) Interrupt Enable Register +AT91C_AES_KEYWxR EQU (0xFFFA4020) ;- (AES) Key Word x Register +AT91C_AES_ISR EQU (0xFFFA401C) ;- (AES) Interrupt Status Register +// - ========== Register definition for PDC_TDES peripheral ========== +AT91C_TDES_RNCR EQU (0xFFFA8114) ;- (PDC_TDES) Receive Next Counter Register +AT91C_TDES_TCR EQU (0xFFFA810C) ;- (PDC_TDES) Transmit Counter Register +AT91C_TDES_RCR EQU (0xFFFA8104) ;- (PDC_TDES) Receive Counter Register +AT91C_TDES_TNPR EQU (0xFFFA8118) ;- (PDC_TDES) Transmit Next Pointer Register +AT91C_TDES_RNPR EQU (0xFFFA8110) ;- (PDC_TDES) Receive Next Pointer Register +AT91C_TDES_RPR EQU (0xFFFA8100) ;- (PDC_TDES) Receive Pointer Register +AT91C_TDES_TNCR EQU (0xFFFA811C) ;- (PDC_TDES) Transmit Next Counter Register +AT91C_TDES_TPR EQU (0xFFFA8108) ;- (PDC_TDES) Transmit Pointer Register +AT91C_TDES_PTSR EQU (0xFFFA8124) ;- (PDC_TDES) PDC Transfer Status Register +AT91C_TDES_PTCR EQU (0xFFFA8120) ;- (PDC_TDES) PDC Transfer Control Register +// - ========== Register definition for TDES peripheral ========== +AT91C_TDES_KEY2WxR EQU (0xFFFA8028) ;- (TDES) Key 2 Word x Register +AT91C_TDES_KEY3WxR EQU (0xFFFA8030) ;- (TDES) Key 3 Word x Register +AT91C_TDES_IDR EQU (0xFFFA8014) ;- (TDES) Interrupt Disable Register +AT91C_TDES_VR EQU (0xFFFA80FC) ;- (TDES) TDES Version Register +AT91C_TDES_IVxR EQU (0xFFFA8060) ;- (TDES) Initialization Vector x Register +AT91C_TDES_ODATAxR EQU (0xFFFA8050) ;- (TDES) Output Data x Register +AT91C_TDES_IMR EQU (0xFFFA8018) ;- (TDES) Interrupt Mask Register +AT91C_TDES_MR EQU (0xFFFA8004) ;- (TDES) Mode Register +AT91C_TDES_CR EQU (0xFFFA8000) ;- (TDES) Control Register +AT91C_TDES_IER EQU (0xFFFA8010) ;- (TDES) Interrupt Enable Register +AT91C_TDES_ISR EQU (0xFFFA801C) ;- (TDES) Interrupt Status Register +AT91C_TDES_IDATAxR EQU (0xFFFA8040) ;- (TDES) Input Data x Register +AT91C_TDES_KEY1WxR EQU (0xFFFA8020) ;- (TDES) Key 1 Word x Register + +// - ***************************************************************************** +// - PIO DEFINITIONS FOR AT91SAM7X256 +// - ***************************************************************************** +AT91C_PIO_PA0 EQU (1 << 0) ;- Pin Controlled by PA0 +AT91C_PA0_RXD0 EQU (AT91C_PIO_PA0) ;- USART 0 Receive Data +AT91C_PIO_PA1 EQU (1 << 1) ;- Pin Controlled by PA1 +AT91C_PA1_TXD0 EQU (AT91C_PIO_PA1) ;- USART 0 Transmit Data +AT91C_PIO_PA10 EQU (1 << 10) ;- Pin Controlled by PA10 +AT91C_PA10_TWD EQU (AT91C_PIO_PA10) ;- TWI Two-wire Serial Data +AT91C_PIO_PA11 EQU (1 << 11) ;- Pin Controlled by PA11 +AT91C_PA11_TWCK EQU (AT91C_PIO_PA11) ;- TWI Two-wire Serial Clock +AT91C_PIO_PA12 EQU (1 << 12) ;- Pin Controlled by PA12 +AT91C_PA12_NPCS00 EQU (AT91C_PIO_PA12) ;- SPI 0 Peripheral Chip Select 0 +AT91C_PIO_PA13 EQU (1 << 13) ;- Pin Controlled by PA13 +AT91C_PA13_NPCS01 EQU (AT91C_PIO_PA13) ;- SPI 0 Peripheral Chip Select 1 +AT91C_PA13_PCK1 EQU (AT91C_PIO_PA13) ;- PMC Programmable Clock Output 1 +AT91C_PIO_PA14 EQU (1 << 14) ;- Pin Controlled by PA14 +AT91C_PA14_NPCS02 EQU (AT91C_PIO_PA14) ;- SPI 0 Peripheral Chip Select 2 +AT91C_PA14_IRQ1 EQU (AT91C_PIO_PA14) ;- External Interrupt 1 +AT91C_PIO_PA15 EQU (1 << 15) ;- Pin Controlled by PA15 +AT91C_PA15_NPCS03 EQU (AT91C_PIO_PA15) ;- SPI 0 Peripheral Chip Select 3 +AT91C_PA15_TCLK2 EQU (AT91C_PIO_PA15) ;- Timer Counter 2 external clock input +AT91C_PIO_PA16 EQU (1 << 16) ;- Pin Controlled by PA16 +AT91C_PA16_MISO0 EQU (AT91C_PIO_PA16) ;- SPI 0 Master In Slave +AT91C_PIO_PA17 EQU (1 << 17) ;- Pin Controlled by PA17 +AT91C_PA17_MOSI0 EQU (AT91C_PIO_PA17) ;- SPI 0 Master Out Slave +AT91C_PIO_PA18 EQU (1 << 18) ;- Pin Controlled by PA18 +AT91C_PA18_SPCK0 EQU (AT91C_PIO_PA18) ;- SPI 0 Serial Clock +AT91C_PIO_PA19 EQU (1 << 19) ;- Pin Controlled by PA19 +AT91C_PA19_CANRX EQU (AT91C_PIO_PA19) ;- CAN Receive +AT91C_PIO_PA2 EQU (1 << 2) ;- Pin Controlled by PA2 +AT91C_PA2_SCK0 EQU (AT91C_PIO_PA2) ;- USART 0 Serial Clock +AT91C_PA2_NPCS11 EQU (AT91C_PIO_PA2) ;- SPI 1 Peripheral Chip Select 1 +AT91C_PIO_PA20 EQU (1 << 20) ;- Pin Controlled by PA20 +AT91C_PA20_CANTX EQU (AT91C_PIO_PA20) ;- CAN Transmit +AT91C_PIO_PA21 EQU (1 << 21) ;- Pin Controlled by PA21 +AT91C_PA21_TF EQU (AT91C_PIO_PA21) ;- SSC Transmit Frame Sync +AT91C_PA21_NPCS10 EQU (AT91C_PIO_PA21) ;- SPI 1 Peripheral Chip Select 0 +AT91C_PIO_PA22 EQU (1 << 22) ;- Pin Controlled by PA22 +AT91C_PA22_TK EQU (AT91C_PIO_PA22) ;- SSC Transmit Clock +AT91C_PA22_SPCK1 EQU (AT91C_PIO_PA22) ;- SPI 1 Serial Clock +AT91C_PIO_PA23 EQU (1 << 23) ;- Pin Controlled by PA23 +AT91C_PA23_TD EQU (AT91C_PIO_PA23) ;- SSC Transmit data +AT91C_PA23_MOSI1 EQU (AT91C_PIO_PA23) ;- SPI 1 Master Out Slave +AT91C_PIO_PA24 EQU (1 << 24) ;- Pin Controlled by PA24 +AT91C_PA24_RD EQU (AT91C_PIO_PA24) ;- SSC Receive Data +AT91C_PA24_MISO1 EQU (AT91C_PIO_PA24) ;- SPI 1 Master In Slave +AT91C_PIO_PA25 EQU (1 << 25) ;- Pin Controlled by PA25 +AT91C_PA25_RK EQU (AT91C_PIO_PA25) ;- SSC Receive Clock +AT91C_PA25_NPCS11 EQU (AT91C_PIO_PA25) ;- SPI 1 Peripheral Chip Select 1 +AT91C_PIO_PA26 EQU (1 << 26) ;- Pin Controlled by PA26 +AT91C_PA26_RF EQU (AT91C_PIO_PA26) ;- SSC Receive Frame Sync +AT91C_PA26_NPCS12 EQU (AT91C_PIO_PA26) ;- SPI 1 Peripheral Chip Select 2 +AT91C_PIO_PA27 EQU (1 << 27) ;- Pin Controlled by PA27 +AT91C_PA27_DRXD EQU (AT91C_PIO_PA27) ;- DBGU Debug Receive Data +AT91C_PA27_PCK3 EQU (AT91C_PIO_PA27) ;- PMC Programmable Clock Output 3 +AT91C_PIO_PA28 EQU (1 << 28) ;- Pin Controlled by PA28 +AT91C_PA28_DTXD EQU (AT91C_PIO_PA28) ;- DBGU Debug Transmit Data +AT91C_PIO_PA29 EQU (1 << 29) ;- Pin Controlled by PA29 +AT91C_PA29_FIQ EQU (AT91C_PIO_PA29) ;- AIC Fast Interrupt Input +AT91C_PA29_NPCS13 EQU (AT91C_PIO_PA29) ;- SPI 1 Peripheral Chip Select 3 +AT91C_PIO_PA3 EQU (1 << 3) ;- Pin Controlled by PA3 +AT91C_PA3_RTS0 EQU (AT91C_PIO_PA3) ;- USART 0 Ready To Send +AT91C_PA3_NPCS12 EQU (AT91C_PIO_PA3) ;- SPI 1 Peripheral Chip Select 2 +AT91C_PIO_PA30 EQU (1 << 30) ;- Pin Controlled by PA30 +AT91C_PA30_IRQ0 EQU (AT91C_PIO_PA30) ;- External Interrupt 0 +AT91C_PA30_PCK2 EQU (AT91C_PIO_PA30) ;- PMC Programmable Clock Output 2 +AT91C_PIO_PA4 EQU (1 << 4) ;- Pin Controlled by PA4 +AT91C_PA4_CTS0 EQU (AT91C_PIO_PA4) ;- USART 0 Clear To Send +AT91C_PA4_NPCS13 EQU (AT91C_PIO_PA4) ;- SPI 1 Peripheral Chip Select 3 +AT91C_PIO_PA5 EQU (1 << 5) ;- Pin Controlled by PA5 +AT91C_PA5_RXD1 EQU (AT91C_PIO_PA5) ;- USART 1 Receive Data +AT91C_PIO_PA6 EQU (1 << 6) ;- Pin Controlled by PA6 +AT91C_PA6_TXD1 EQU (AT91C_PIO_PA6) ;- USART 1 Transmit Data +AT91C_PIO_PA7 EQU (1 << 7) ;- Pin Controlled by PA7 +AT91C_PA7_SCK1 EQU (AT91C_PIO_PA7) ;- USART 1 Serial Clock +AT91C_PA7_NPCS01 EQU (AT91C_PIO_PA7) ;- SPI 0 Peripheral Chip Select 1 +AT91C_PIO_PA8 EQU (1 << 8) ;- Pin Controlled by PA8 +AT91C_PA8_RTS1 EQU (AT91C_PIO_PA8) ;- USART 1 Ready To Send +AT91C_PA8_NPCS02 EQU (AT91C_PIO_PA8) ;- SPI 0 Peripheral Chip Select 2 +AT91C_PIO_PA9 EQU (1 << 9) ;- Pin Controlled by PA9 +AT91C_PA9_CTS1 EQU (AT91C_PIO_PA9) ;- USART 1 Clear To Send +AT91C_PA9_NPCS03 EQU (AT91C_PIO_PA9) ;- SPI 0 Peripheral Chip Select 3 +AT91C_PIO_PB0 EQU (1 << 0) ;- Pin Controlled by PB0 +AT91C_PB0_ETXCK_EREFCK EQU (AT91C_PIO_PB0) ;- Ethernet MAC Transmit Clock/Reference Clock +AT91C_PB0_PCK0 EQU (AT91C_PIO_PB0) ;- PMC Programmable Clock Output 0 +AT91C_PIO_PB1 EQU (1 << 1) ;- Pin Controlled by PB1 +AT91C_PB1_ETXEN EQU (AT91C_PIO_PB1) ;- Ethernet MAC Transmit Enable +AT91C_PIO_PB10 EQU (1 << 10) ;- Pin Controlled by PB10 +AT91C_PB10_ETX2 EQU (AT91C_PIO_PB10) ;- Ethernet MAC Transmit Data 2 +AT91C_PB10_NPCS11 EQU (AT91C_PIO_PB10) ;- SPI 1 Peripheral Chip Select 1 +AT91C_PIO_PB11 EQU (1 << 11) ;- Pin Controlled by PB11 +AT91C_PB11_ETX3 EQU (AT91C_PIO_PB11) ;- Ethernet MAC Transmit Data 3 +AT91C_PB11_NPCS12 EQU (AT91C_PIO_PB11) ;- SPI 1 Peripheral Chip Select 2 +AT91C_PIO_PB12 EQU (1 << 12) ;- Pin Controlled by PB12 +AT91C_PB12_ETXER EQU (AT91C_PIO_PB12) ;- Ethernet MAC Transmikt Coding Error +AT91C_PB12_TCLK0 EQU (AT91C_PIO_PB12) ;- Timer Counter 0 external clock input +AT91C_PIO_PB13 EQU (1 << 13) ;- Pin Controlled by PB13 +AT91C_PB13_ERX2 EQU (AT91C_PIO_PB13) ;- Ethernet MAC Receive Data 2 +AT91C_PB13_NPCS01 EQU (AT91C_PIO_PB13) ;- SPI 0 Peripheral Chip Select 1 +AT91C_PIO_PB14 EQU (1 << 14) ;- Pin Controlled by PB14 +AT91C_PB14_ERX3 EQU (AT91C_PIO_PB14) ;- Ethernet MAC Receive Data 3 +AT91C_PB14_NPCS02 EQU (AT91C_PIO_PB14) ;- SPI 0 Peripheral Chip Select 2 +AT91C_PIO_PB15 EQU (1 << 15) ;- Pin Controlled by PB15 +AT91C_PB15_ERXDV EQU (AT91C_PIO_PB15) ;- Ethernet MAC Receive Data Valid +AT91C_PIO_PB16 EQU (1 << 16) ;- Pin Controlled by PB16 +AT91C_PB16_ECOL EQU (AT91C_PIO_PB16) ;- Ethernet MAC Collision Detected +AT91C_PB16_NPCS13 EQU (AT91C_PIO_PB16) ;- SPI 1 Peripheral Chip Select 3 +AT91C_PIO_PB17 EQU (1 << 17) ;- Pin Controlled by PB17 +AT91C_PB17_ERXCK EQU (AT91C_PIO_PB17) ;- Ethernet MAC Receive Clock +AT91C_PB17_NPCS03 EQU (AT91C_PIO_PB17) ;- SPI 0 Peripheral Chip Select 3 +AT91C_PIO_PB18 EQU (1 << 18) ;- Pin Controlled by PB18 +AT91C_PB18_EF100 EQU (AT91C_PIO_PB18) ;- Ethernet MAC Force 100 Mbits/sec +AT91C_PB18_ADTRG EQU (AT91C_PIO_PB18) ;- ADC External Trigger +AT91C_PIO_PB19 EQU (1 << 19) ;- Pin Controlled by PB19 +AT91C_PB19_PWM0 EQU (AT91C_PIO_PB19) ;- PWM Channel 0 +AT91C_PB19_TCLK1 EQU (AT91C_PIO_PB19) ;- Timer Counter 1 external clock input +AT91C_PIO_PB2 EQU (1 << 2) ;- Pin Controlled by PB2 +AT91C_PB2_ETX0 EQU (AT91C_PIO_PB2) ;- Ethernet MAC Transmit Data 0 +AT91C_PIO_PB20 EQU (1 << 20) ;- Pin Controlled by PB20 +AT91C_PB20_PWM1 EQU (AT91C_PIO_PB20) ;- PWM Channel 1 +AT91C_PB20_PCK0 EQU (AT91C_PIO_PB20) ;- PMC Programmable Clock Output 0 +AT91C_PIO_PB21 EQU (1 << 21) ;- Pin Controlled by PB21 +AT91C_PB21_PWM2 EQU (AT91C_PIO_PB21) ;- PWM Channel 2 +AT91C_PB21_PCK1 EQU (AT91C_PIO_PB21) ;- PMC Programmable Clock Output 1 +AT91C_PIO_PB22 EQU (1 << 22) ;- Pin Controlled by PB22 +AT91C_PB22_PWM3 EQU (AT91C_PIO_PB22) ;- PWM Channel 3 +AT91C_PB22_PCK2 EQU (AT91C_PIO_PB22) ;- PMC Programmable Clock Output 2 +AT91C_PIO_PB23 EQU (1 << 23) ;- Pin Controlled by PB23 +AT91C_PB23_TIOA0 EQU (AT91C_PIO_PB23) ;- Timer Counter 0 Multipurpose Timer I/O Pin A +AT91C_PB23_DCD1 EQU (AT91C_PIO_PB23) ;- USART 1 Data Carrier Detect +AT91C_PIO_PB24 EQU (1 << 24) ;- Pin Controlled by PB24 +AT91C_PB24_TIOB0 EQU (AT91C_PIO_PB24) ;- Timer Counter 0 Multipurpose Timer I/O Pin B +AT91C_PB24_DSR1 EQU (AT91C_PIO_PB24) ;- USART 1 Data Set ready +AT91C_PIO_PB25 EQU (1 << 25) ;- Pin Controlled by PB25 +AT91C_PB25_TIOA1 EQU (AT91C_PIO_PB25) ;- Timer Counter 1 Multipurpose Timer I/O Pin A +AT91C_PB25_DTR1 EQU (AT91C_PIO_PB25) ;- USART 1 Data Terminal ready +AT91C_PIO_PB26 EQU (1 << 26) ;- Pin Controlled by PB26 +AT91C_PB26_TIOB1 EQU (AT91C_PIO_PB26) ;- Timer Counter 1 Multipurpose Timer I/O Pin B +AT91C_PB26_RI1 EQU (AT91C_PIO_PB26) ;- USART 1 Ring Indicator +AT91C_PIO_PB27 EQU (1 << 27) ;- Pin Controlled by PB27 +AT91C_PB27_TIOA2 EQU (AT91C_PIO_PB27) ;- Timer Counter 2 Multipurpose Timer I/O Pin A +AT91C_PB27_PWM0 EQU (AT91C_PIO_PB27) ;- PWM Channel 0 +AT91C_PIO_PB28 EQU (1 << 28) ;- Pin Controlled by PB28 +AT91C_PB28_TIOB2 EQU (AT91C_PIO_PB28) ;- Timer Counter 2 Multipurpose Timer I/O Pin B +AT91C_PB28_PWM1 EQU (AT91C_PIO_PB28) ;- PWM Channel 1 +AT91C_PIO_PB29 EQU (1 << 29) ;- Pin Controlled by PB29 +AT91C_PB29_PCK1 EQU (AT91C_PIO_PB29) ;- PMC Programmable Clock Output 1 +AT91C_PB29_PWM2 EQU (AT91C_PIO_PB29) ;- PWM Channel 2 +AT91C_PIO_PB3 EQU (1 << 3) ;- Pin Controlled by PB3 +AT91C_PB3_ETX1 EQU (AT91C_PIO_PB3) ;- Ethernet MAC Transmit Data 1 +AT91C_PIO_PB30 EQU (1 << 30) ;- Pin Controlled by PB30 +AT91C_PB30_PCK2 EQU (AT91C_PIO_PB30) ;- PMC Programmable Clock Output 2 +AT91C_PB30_PWM3 EQU (AT91C_PIO_PB30) ;- PWM Channel 3 +AT91C_PIO_PB4 EQU (1 << 4) ;- Pin Controlled by PB4 +AT91C_PB4_ECRS_ECRSDV EQU (AT91C_PIO_PB4) ;- Ethernet MAC Carrier Sense/Carrier Sense and Data Valid +AT91C_PIO_PB5 EQU (1 << 5) ;- Pin Controlled by PB5 +AT91C_PB5_ERX0 EQU (AT91C_PIO_PB5) ;- Ethernet MAC Receive Data 0 +AT91C_PIO_PB6 EQU (1 << 6) ;- Pin Controlled by PB6 +AT91C_PB6_ERX1 EQU (AT91C_PIO_PB6) ;- Ethernet MAC Receive Data 1 +AT91C_PIO_PB7 EQU (1 << 7) ;- Pin Controlled by PB7 +AT91C_PB7_ERXER EQU (AT91C_PIO_PB7) ;- Ethernet MAC Receive Error +AT91C_PIO_PB8 EQU (1 << 8) ;- Pin Controlled by PB8 +AT91C_PB8_EMDC EQU (AT91C_PIO_PB8) ;- Ethernet MAC Management Data Clock +AT91C_PIO_PB9 EQU (1 << 9) ;- Pin Controlled by PB9 +AT91C_PB9_EMDIO EQU (AT91C_PIO_PB9) ;- Ethernet MAC Management Data Input/Output + +// - ***************************************************************************** +// - PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 +// - ***************************************************************************** +AT91C_ID_FIQ EQU ( 0) ;- Advanced Interrupt Controller (FIQ) +AT91C_ID_SYS EQU ( 1) ;- System Peripheral +AT91C_ID_PIOA EQU ( 2) ;- Parallel IO Controller A +AT91C_ID_PIOB EQU ( 3) ;- Parallel IO Controller B +AT91C_ID_SPI0 EQU ( 4) ;- Serial Peripheral Interface 0 +AT91C_ID_SPI1 EQU ( 5) ;- Serial Peripheral Interface 1 +AT91C_ID_US0 EQU ( 6) ;- USART 0 +AT91C_ID_US1 EQU ( 7) ;- USART 1 +AT91C_ID_SSC EQU ( 8) ;- Serial Synchronous Controller +AT91C_ID_TWI EQU ( 9) ;- Two-Wire Interface +AT91C_ID_PWMC EQU (10) ;- PWM Controller +AT91C_ID_UDP EQU (11) ;- USB Device Port +AT91C_ID_TC0 EQU (12) ;- Timer Counter 0 +AT91C_ID_TC1 EQU (13) ;- Timer Counter 1 +AT91C_ID_TC2 EQU (14) ;- Timer Counter 2 +AT91C_ID_CAN EQU (15) ;- Control Area Network Controller +AT91C_ID_EMAC EQU (16) ;- Ethernet MAC +AT91C_ID_ADC EQU (17) ;- Analog-to-Digital Converter +AT91C_ID_AES EQU (18) ;- Advanced Encryption Standard 128-bit +AT91C_ID_TDES EQU (19) ;- Triple Data Encryption Standard +AT91C_ID_20_Reserved EQU (20) ;- Reserved +AT91C_ID_21_Reserved EQU (21) ;- Reserved +AT91C_ID_22_Reserved EQU (22) ;- Reserved +AT91C_ID_23_Reserved EQU (23) ;- Reserved +AT91C_ID_24_Reserved EQU (24) ;- Reserved +AT91C_ID_25_Reserved EQU (25) ;- Reserved +AT91C_ID_26_Reserved EQU (26) ;- Reserved +AT91C_ID_27_Reserved EQU (27) ;- Reserved +AT91C_ID_28_Reserved EQU (28) ;- Reserved +AT91C_ID_29_Reserved EQU (29) ;- Reserved +AT91C_ID_IRQ0 EQU (30) ;- Advanced Interrupt Controller (IRQ0) +AT91C_ID_IRQ1 EQU (31) ;- Advanced Interrupt Controller (IRQ1) + +// - ***************************************************************************** +// - BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 +// - ***************************************************************************** +AT91C_BASE_SYS EQU (0xFFFFF000) ;- (SYS) Base Address +AT91C_BASE_AIC EQU (0xFFFFF000) ;- (AIC) Base Address +AT91C_BASE_PDC_DBGU EQU (0xFFFFF300) ;- (PDC_DBGU) Base Address +AT91C_BASE_DBGU EQU (0xFFFFF200) ;- (DBGU) Base Address +AT91C_BASE_PIOA EQU (0xFFFFF400) ;- (PIOA) Base Address +AT91C_BASE_PIOB EQU (0xFFFFF600) ;- (PIOB) Base Address +AT91C_BASE_CKGR EQU (0xFFFFFC20) ;- (CKGR) Base Address +AT91C_BASE_PMC EQU (0xFFFFFC00) ;- (PMC) Base Address +AT91C_BASE_RSTC EQU (0xFFFFFD00) ;- (RSTC) Base Address +AT91C_BASE_RTTC EQU (0xFFFFFD20) ;- (RTTC) Base Address +AT91C_BASE_PITC EQU (0xFFFFFD30) ;- (PITC) Base Address +AT91C_BASE_WDTC EQU (0xFFFFFD40) ;- (WDTC) Base Address +AT91C_BASE_VREG EQU (0xFFFFFD60) ;- (VREG) Base Address +AT91C_BASE_MC EQU (0xFFFFFF00) ;- (MC) Base Address +AT91C_BASE_PDC_SPI1 EQU (0xFFFE4100) ;- (PDC_SPI1) Base Address +AT91C_BASE_SPI1 EQU (0xFFFE4000) ;- (SPI1) Base Address +AT91C_BASE_PDC_SPI0 EQU (0xFFFE0100) ;- (PDC_SPI0) Base Address +AT91C_BASE_SPI0 EQU (0xFFFE0000) ;- (SPI0) Base Address +AT91C_BASE_PDC_US1 EQU (0xFFFC4100) ;- (PDC_US1) Base Address +AT91C_BASE_US1 EQU (0xFFFC4000) ;- (US1) Base Address +AT91C_BASE_PDC_US0 EQU (0xFFFC0100) ;- (PDC_US0) Base Address +AT91C_BASE_US0 EQU (0xFFFC0000) ;- (US0) Base Address +AT91C_BASE_PDC_SSC EQU (0xFFFD4100) ;- (PDC_SSC) Base Address +AT91C_BASE_SSC EQU (0xFFFD4000) ;- (SSC) Base Address +AT91C_BASE_TWI EQU (0xFFFB8000) ;- (TWI) Base Address +AT91C_BASE_PWMC_CH3 EQU (0xFFFCC260) ;- (PWMC_CH3) Base Address +AT91C_BASE_PWMC_CH2 EQU (0xFFFCC240) ;- (PWMC_CH2) Base Address +AT91C_BASE_PWMC_CH1 EQU (0xFFFCC220) ;- (PWMC_CH1) Base Address +AT91C_BASE_PWMC_CH0 EQU (0xFFFCC200) ;- (PWMC_CH0) Base Address +AT91C_BASE_PWMC EQU (0xFFFCC000) ;- (PWMC) Base Address +AT91C_BASE_UDP EQU (0xFFFB0000) ;- (UDP) Base Address +AT91C_BASE_TC0 EQU (0xFFFA0000) ;- (TC0) Base Address +AT91C_BASE_TC1 EQU (0xFFFA0040) ;- (TC1) Base Address +AT91C_BASE_TC2 EQU (0xFFFA0080) ;- (TC2) Base Address +AT91C_BASE_TCB EQU (0xFFFA0000) ;- (TCB) Base Address +AT91C_BASE_CAN_MB0 EQU (0xFFFD0200) ;- (CAN_MB0) Base Address +AT91C_BASE_CAN_MB1 EQU (0xFFFD0220) ;- (CAN_MB1) Base Address +AT91C_BASE_CAN_MB2 EQU (0xFFFD0240) ;- (CAN_MB2) Base Address +AT91C_BASE_CAN_MB3 EQU (0xFFFD0260) ;- (CAN_MB3) Base Address +AT91C_BASE_CAN_MB4 EQU (0xFFFD0280) ;- (CAN_MB4) Base Address +AT91C_BASE_CAN_MB5 EQU (0xFFFD02A0) ;- (CAN_MB5) Base Address +AT91C_BASE_CAN_MB6 EQU (0xFFFD02C0) ;- (CAN_MB6) Base Address +AT91C_BASE_CAN_MB7 EQU (0xFFFD02E0) ;- (CAN_MB7) Base Address +AT91C_BASE_CAN EQU (0xFFFD0000) ;- (CAN) Base Address +AT91C_BASE_EMAC EQU (0xFFFDC000) ;- (EMAC) Base Address +AT91C_BASE_PDC_ADC EQU (0xFFFD8100) ;- (PDC_ADC) Base Address +AT91C_BASE_ADC EQU (0xFFFD8000) ;- (ADC) Base Address +AT91C_BASE_PDC_AES EQU (0xFFFA4100) ;- (PDC_AES) Base Address +AT91C_BASE_AES EQU (0xFFFA4000) ;- (AES) Base Address +AT91C_BASE_PDC_TDES EQU (0xFFFA8100) ;- (PDC_TDES) Base Address +AT91C_BASE_TDES EQU (0xFFFA8000) ;- (TDES) Base Address + +// - ***************************************************************************** +// - MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 +// - ***************************************************************************** +AT91C_ISRAM EQU (0x00200000) ;- Internal SRAM base address +AT91C_ISRAM_SIZE EQU (0x00010000) ;- Internal SRAM size in byte (64 Kbyte) +AT91C_IFLASH EQU (0x00100000) ;- Internal ROM base address +AT91C_IFLASH_SIZE EQU (0x00040000) ;- Internal ROM size in byte (256 Kbyte) + + + +#endif /* AT91SAM7X256_H */ diff --git a/20080212/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c b/20080212/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c new file mode 100644 index 000000000..9cbd823c6 --- /dev/null +++ b/20080212/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c @@ -0,0 +1,51 @@ +//* ---------------------------------------------------------------------------- +//* ATMEL Microcontroller Software Support - ROUSSET - +//* ---------------------------------------------------------------------------- +//* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//* ---------------------------------------------------------------------------- +//* File Name : lib_AT91SAM7X256.h +//* Object : AT91SAM7X256 inlined functions +//* Generated : AT91 SW Application Group 05/20/2005 (16:22:29) +//* +//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// +//* CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005// +//* CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005// +//* CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004// +//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// +//* CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004// +//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// +//* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003// +//* CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004// +//* CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005// +//* CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005// +//* CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004// +//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003// +//* CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004// +//* CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005// +//* CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005// +//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// +//* CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004// +//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// +//* CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003// +//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// +//* CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002// +//* ---------------------------------------------------------------------------- + + +#include "AT91SAM7X256.h" + + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_ConfigureIt +//* \brief Interrupt Handler Initialization +//*---------------------------------------------------------------------------- + diff --git a/20080212/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h b/20080212/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h new file mode 100644 index 000000000..e66b4e1e1 --- /dev/null +++ b/20080212/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h @@ -0,0 +1,4558 @@ +//* ---------------------------------------------------------------------------- +//* ATMEL Microcontroller Software Support - ROUSSET - +//* ---------------------------------------------------------------------------- +//* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//* ---------------------------------------------------------------------------- +//* File Name : lib_AT91SAM7X256.h +//* Object : AT91SAM7X256 inlined functions +//* Generated : AT91 SW Application Group 05/20/2005 (16:22:29) +//* +//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// +//* CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005// +//* CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005// +//* CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004// +//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// +//* CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004// +//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// +//* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003// +//* CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004// +//* CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005// +//* CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005// +//* CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004// +//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003// +//* CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004// +//* CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005// +//* CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005// +//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// +//* CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004// +//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// +//* CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003// +//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// +//* CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002// +//* ---------------------------------------------------------------------------- + +#ifndef lib_AT91SAM7X256_H +#define lib_AT91SAM7X256_H + +/* ***************************************************************************** + SOFTWARE API FOR AIC + ***************************************************************************** */ +#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20] + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_ConfigureIt +//* \brief Interrupt Handler Initialization +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_ConfigureIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id, // \arg interrupt number to initialize + unsigned int priority, // \arg priority to give to the interrupt + unsigned int src_type, // \arg activation and sense of activation + void (*newHandler) (void) ) // \arg address of the interrupt handler +{ + unsigned int oldHandler; + unsigned int mask ; + + oldHandler = pAic->AIC_SVR[irq_id]; + + mask = 0x1 << irq_id ; + //* Disable the interrupt on the interrupt controller + pAic->AIC_IDCR = mask ; + //* Save the interrupt handler routine pointer and the interrupt priority + pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ; + //* Store the Source Mode Register + pAic->AIC_SMR[irq_id] = src_type | priority ; + //* Clear the interrupt on the interrupt controller + pAic->AIC_ICCR = mask ; + + return oldHandler; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_EnableIt +//* \brief Enable corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_EnableIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id ) // \arg interrupt number to initialize +{ + //* Enable the interrupt on the interrupt controller + pAic->AIC_IECR = 0x1 << irq_id ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_DisableIt +//* \brief Disable corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_DisableIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id ) // \arg interrupt number to initialize +{ + unsigned int mask = 0x1 << irq_id; + //* Disable the interrupt on the interrupt controller + pAic->AIC_IDCR = mask ; + //* Clear the interrupt on the Interrupt Controller ( if one is pending ) + pAic->AIC_ICCR = mask ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_ClearIt +//* \brief Clear corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_ClearIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg interrupt number to initialize +{ + //* Clear the interrupt on the Interrupt Controller ( if one is pending ) + pAic->AIC_ICCR = (0x1 << irq_id); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_AcknowledgeIt +//* \brief Acknowledge corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_AcknowledgeIt ( + AT91PS_AIC pAic) // \arg pointer to the AIC registers +{ + pAic->AIC_EOICR = pAic->AIC_EOICR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_SetExceptionVector +//* \brief Configure vector handler +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_SetExceptionVector ( + unsigned int *pVector, // \arg pointer to the AIC registers + void (*Handler) () ) // \arg Interrupt Handler +{ + unsigned int oldVector = *pVector; + + if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE) + *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE; + else + *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000; + + return oldVector; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_Trig +//* \brief Trig an IT +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_Trig ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg interrupt number +{ + pAic->AIC_ISCR = (0x1 << irq_id) ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_IsActive +//* \brief Test if an IT is active +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_IsActive ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg Interrupt Number +{ + return (pAic->AIC_ISR & (0x1 << irq_id)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_IsPending +//* \brief Test if an IT is pending +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_IsPending ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg Interrupt Number +{ + return (pAic->AIC_IPR & (0x1 << irq_id)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_Open +//* \brief Set exception vectors and AIC registers to default values +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_Open( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + void (*IrqHandler) (), // \arg Default IRQ vector exception + void (*FiqHandler) (), // \arg Default FIQ vector exception + void (*DefaultHandler) (), // \arg Default Handler set in ISR + void (*SpuriousHandler) (), // \arg Default Spurious Handler + unsigned int protectMode) // \arg Debug Control Register +{ + int i; + + // Disable all interrupts and set IVR to the default handler + for (i = 0; i < 32; ++i) { + AT91F_AIC_DisableIt(pAic, i); + AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler); + } + + // Set the IRQ exception vector + AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler); + // Set the Fast Interrupt exception vector + AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler); + + pAic->AIC_SPU = (unsigned int) SpuriousHandler; + pAic->AIC_DCR = protectMode; +} +/* ***************************************************************************** + SOFTWARE API FOR PDC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetNextRx +//* \brief Set the next receive transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetNextRx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be received + unsigned int bytes) // \arg number of bytes to be received +{ + pPDC->PDC_RNPR = (unsigned int) address; + pPDC->PDC_RNCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetNextTx +//* \brief Set the next transmit transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetNextTx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be transmitted + unsigned int bytes) // \arg number of bytes to be transmitted +{ + pPDC->PDC_TNPR = (unsigned int) address; + pPDC->PDC_TNCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetRx +//* \brief Set the receive transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetRx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be received + unsigned int bytes) // \arg number of bytes to be received +{ + pPDC->PDC_RPR = (unsigned int) address; + pPDC->PDC_RCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetTx +//* \brief Set the transmit transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetTx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be transmitted + unsigned int bytes) // \arg number of bytes to be transmitted +{ + pPDC->PDC_TPR = (unsigned int) address; + pPDC->PDC_TCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_EnableTx +//* \brief Enable transmit +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_EnableTx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_TXTEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_EnableRx +//* \brief Enable receive +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_EnableRx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_RXTEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_DisableTx +//* \brief Disable transmit +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_DisableTx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_TXTDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_DisableRx +//* \brief Disable receive +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_DisableRx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_RXTDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsTxEmpty +//* \brief Test if the current transfer descriptor has been sent +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_TCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsNextTxEmpty +//* \brief Test if the next transfer descriptor has been moved to the current td +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_TNCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsRxEmpty +//* \brief Test if the current transfer descriptor has been filled +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_RCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsNextRxEmpty +//* \brief Test if the next transfer descriptor has been moved to the current td +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_RNCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_Open +//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_Open ( + AT91PS_PDC pPDC) // \arg pointer to a PDC controller +{ + //* Disable the RX and TX PDC transfer requests + AT91F_PDC_DisableRx(pPDC); + AT91F_PDC_DisableTx(pPDC); + + //* Reset all Counter register Next buffer first + AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); + AT91F_PDC_SetTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetRx(pPDC, (char *) 0, 0); + + //* Enable the RX and TX PDC transfer requests + AT91F_PDC_EnableRx(pPDC); + AT91F_PDC_EnableTx(pPDC); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_Close +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_Close ( + AT91PS_PDC pPDC) // \arg pointer to a PDC controller +{ + //* Disable the RX and TX PDC transfer requests + AT91F_PDC_DisableRx(pPDC); + AT91F_PDC_DisableTx(pPDC); + + //* Reset all Counter register Next buffer first + AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); + AT91F_PDC_SetTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetRx(pPDC, (char *) 0, 0); + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SendFrame +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PDC_SendFrame( + AT91PS_PDC pPDC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + if (AT91F_PDC_IsTxEmpty(pPDC)) { + //* Buffer and next buffer can be initialized + AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer); + AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer); + return 2; + } + else if (AT91F_PDC_IsNextTxEmpty(pPDC)) { + //* Only one buffer can be initialized + AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer); + return 1; + } + else { + //* All buffer are in use... + return 0; + } +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_ReceiveFrame +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PDC_ReceiveFrame ( + AT91PS_PDC pPDC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + if (AT91F_PDC_IsRxEmpty(pPDC)) { + //* Buffer and next buffer can be initialized + AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer); + AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer); + return 2; + } + else if (AT91F_PDC_IsNextRxEmpty(pPDC)) { + //* Only one buffer can be initialized + AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer); + return 1; + } + else { + //* All buffer are in use... + return 0; + } +} +/* ***************************************************************************** + SOFTWARE API FOR DBGU + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_InterruptEnable +//* \brief Enable DBGU Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_InterruptEnable( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg dbgu interrupt to be enabled +{ + pDbgu->DBGU_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_InterruptDisable +//* \brief Disable DBGU Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_InterruptDisable( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg dbgu interrupt to be disabled +{ + pDbgu->DBGU_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_GetInterruptMaskStatus +//* \brief Return DBGU Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status + AT91PS_DBGU pDbgu) // \arg pointer to a DBGU controller +{ + return pDbgu->DBGU_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_IsInterruptMasked +//* \brief Test if DBGU Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_DBGU_IsInterruptMasked( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR PIO + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgPeriph +//* \brief Enable pins to be drived by peripheral +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgPeriph( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int periphAEnable, // \arg PERIPH A to enable + unsigned int periphBEnable) // \arg PERIPH B to enable + +{ + pPio->PIO_ASR = periphAEnable; + pPio->PIO_BSR = periphBEnable; + pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgOutput +//* \brief Enable PIO in output mode +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int pioEnable) // \arg PIO to be enabled +{ + pPio->PIO_PER = pioEnable; // Set in PIO mode + pPio->PIO_OER = pioEnable; // Configure in Output +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgInput +//* \brief Enable PIO in input mode +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgInput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int inputEnable) // \arg PIO to be enabled +{ + // Disable output + pPio->PIO_ODR = inputEnable; + pPio->PIO_PER = inputEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgOpendrain +//* \brief Configure PIO in open drain +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgOpendrain( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int multiDrvEnable) // \arg pio to be configured in open drain +{ + // Configure the multi-drive option + pPio->PIO_MDDR = ~multiDrvEnable; + pPio->PIO_MDER = multiDrvEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgPullup +//* \brief Enable pullup on PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgPullup( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int pullupEnable) // \arg enable pullup on PIO +{ + // Connect or not Pullup + pPio->PIO_PPUDR = ~pullupEnable; + pPio->PIO_PPUER = pullupEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgDirectDrive +//* \brief Enable direct drive on PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgDirectDrive( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int directDrive) // \arg PIO to be configured with direct drive + +{ + // Configure the Direct Drive + pPio->PIO_OWDR = ~directDrive; + pPio->PIO_OWER = directDrive; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgInputFilter +//* \brief Enable input filter on input PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgInputFilter( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int inputFilter) // \arg PIO to be configured with input filter + +{ + // Configure the Direct Drive + pPio->PIO_IFDR = ~inputFilter; + pPio->PIO_IFER = inputFilter; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInput +//* \brief Return PIO input value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInput( // \return PIO input + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PDSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInputSet +//* \brief Test if PIO is input flag is active +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInputSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInput(pPio) & flag); +} + + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_SetOutput +//* \brief Set to 1 output PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_SetOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be set +{ + pPio->PIO_SODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_ClearOutput +//* \brief Set to 0 output PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_ClearOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be cleared +{ + pPio->PIO_CODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_ForceOutput +//* \brief Force output when Direct drive option is enabled +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_ForceOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be forced +{ + pPio->PIO_ODSR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Enable +//* \brief Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_Enable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be enabled +{ + pPio->PIO_PER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Disable +//* \brief Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_Disable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be disabled +{ + pPio->PIO_PDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetStatus +//* \brief Return PIO Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsSet +//* \brief Test if PIO is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputEnable +//* \brief Output Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output to be enabled +{ + pPio->PIO_OER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputDisable +//* \brief Output Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output to be disabled +{ + pPio->PIO_ODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputStatus +//* \brief Return PIO Output Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_OSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOuputSet +//* \brief Test if PIO Output is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsOutputSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InputFilterEnable +//* \brief Input Filter Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InputFilterEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio input filter to be enabled +{ + pPio->PIO_IFER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InputFilterDisable +//* \brief Input Filter Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InputFilterDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio input filter to be disabled +{ + pPio->PIO_IFDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInputFilterStatus +//* \brief Return PIO Input Filter Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_IFSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInputFilterSet +//* \brief Test if PIO Input filter is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInputFilterSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInputFilterStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputDataStatus +//* \brief Return PIO Output Data Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ODSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InterruptEnable +//* \brief Enable PIO Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InterruptEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio interrupt to be enabled +{ + pPio->PIO_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InterruptDisable +//* \brief Disable PIO Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InterruptDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio interrupt to be disabled +{ + pPio->PIO_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInterruptMaskStatus +//* \brief Return PIO Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInterruptStatus +//* \brief Return PIO Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ISR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInterruptMasked +//* \brief Test if PIO Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInterruptMasked( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInterruptSet +//* \brief Test if PIO Interrupt is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInterruptSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInterruptStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_MultiDriverEnable +//* \brief Multi Driver Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_MultiDriverEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be enabled +{ + pPio->PIO_MDER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_MultiDriverDisable +//* \brief Multi Driver Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_MultiDriverDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be disabled +{ + pPio->PIO_MDDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetMultiDriverStatus +//* \brief Return PIO Multi Driver Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_MDSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsMultiDriverSet +//* \brief Test if PIO MultiDriver is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsMultiDriverSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_A_RegisterSelection +//* \brief PIO A Register Selection +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_A_RegisterSelection( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio A register selection +{ + pPio->PIO_ASR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_B_RegisterSelection +//* \brief PIO B Register Selection +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_B_RegisterSelection( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio B register selection +{ + pPio->PIO_BSR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Get_AB_RegisterStatus +//* \brief Return PIO Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ABSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsAB_RegisterSet +//* \brief Test if PIO AB Register is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsAB_RegisterSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputWriteEnable +//* \brief Output Write Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputWriteEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output write to be enabled +{ + pPio->PIO_OWER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputWriteDisable +//* \brief Output Write Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputWriteDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output write to be disabled +{ + pPio->PIO_OWDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputWriteStatus +//* \brief Return PIO Output Write Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_OWSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOutputWriteSet +//* \brief Test if PIO OutputWrite is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsOutputWriteSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetCfgPullup +//* \brief Return PIO Configuration Pullup +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PPUSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOutputDataStatusSet +//* \brief Test if PIO Output Data Status is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsOutputDataStatusSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputDataStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsCfgPullupStatusSet +//* \brief Test if PIO Configuration Pullup Status is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsCfgPullupStatusSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (~AT91F_PIO_GetCfgPullup(pPio) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR PMC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgSysClkEnableReg +//* \brief Configure the System Clock Enable Register of the PMC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgSysClkEnableReg ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int mode) +{ + //* Write to the SCER register + pPMC->PMC_SCER = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgSysClkDisableReg +//* \brief Configure the System Clock Disable Register of the PMC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgSysClkDisableReg ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int mode) +{ + //* Write to the SCDR register + pPMC->PMC_SCDR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetSysClkStatusReg +//* \brief Return the System Clock Status Register of the PMC controller +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetSysClkStatusReg ( + AT91PS_PMC pPMC // pointer to a CAN controller + ) +{ + return pPMC->PMC_SCSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnablePeriphClock +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_EnablePeriphClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int periphIds) // \arg IDs of peripherals to enable +{ + pPMC->PMC_PCER = periphIds; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisablePeriphClock +//* \brief Disable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_DisablePeriphClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int periphIds) // \arg IDs of peripherals to enable +{ + pPMC->PMC_PCDR = periphIds; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetPeriphClock +//* \brief Get peripheral clock status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetPeriphClock ( + AT91PS_PMC pPMC) // \arg pointer to PMC controller +{ + return pPMC->PMC_PCSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_CfgMainOscillatorReg +//* \brief Cfg the main oscillator +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_CfgMainOscillatorReg ( + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int mode) +{ + pCKGR->CKGR_MOR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_GetMainOscillatorReg +//* \brief Cfg the main oscillator +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CKGR_GetMainOscillatorReg ( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + return pCKGR->CKGR_MOR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_EnableMainOscillator +//* \brief Enable the main oscillator +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_EnableMainOscillator( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_DisableMainOscillator +//* \brief Disable the main oscillator +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_DisableMainOscillator ( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_CfgMainOscStartUpTime +//* \brief Cfg MOR Register according to the main osc startup time +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_CfgMainOscStartUpTime ( + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int startup_time, // \arg main osc startup time in microsecond (us) + unsigned int slowClock) // \arg slowClock in Hz +{ + pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT; + pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_GetMainClockFreqReg +//* \brief Cfg the main oscillator +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CKGR_GetMainClockFreqReg ( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + return pCKGR->CKGR_MCFR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_GetMainClock +//* \brief Return Main clock in Hz +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CKGR_GetMainClock ( + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int slowClock) // \arg slowClock in Hz +{ + return ((pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF) * slowClock) >> 4; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgMCKReg +//* \brief Cfg Master Clock Register +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgMCKReg ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int mode) +{ + pPMC->PMC_MCKR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetMCKReg +//* \brief Return Master Clock Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetMCKReg( + AT91PS_PMC pPMC) // \arg pointer to PMC controller +{ + return pPMC->PMC_MCKR; +} + +//*------------------------------------------------------------------------------ +//* \fn AT91F_PMC_GetMasterClock +//* \brief Return master clock in Hz which correponds to processor clock for ARM7 +//*------------------------------------------------------------------------------ +__inline unsigned int AT91F_PMC_GetMasterClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int slowClock) // \arg slowClock in Hz +{ + unsigned int reg = pPMC->PMC_MCKR; + unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2)); + unsigned int pllDivider, pllMultiplier; + + switch (reg & AT91C_PMC_CSS) { + case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected + return slowClock / prescaler; + case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected + return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler; + case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected + reg = pCKGR->CKGR_PLLR; + pllDivider = (reg & AT91C_CKGR_DIV); + pllMultiplier = ((reg & AT91C_CKGR_MUL) >> 16) + 1; + return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler; + } + return 0; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnablePCK +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_EnablePCK ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int pck, // \arg Peripheral clock identifier 0 .. 7 + unsigned int mode) +{ + pPMC->PMC_PCKR[pck] = mode; + pPMC->PMC_SCER = (1 << pck) << 8; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisablePCK +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_DisablePCK ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int pck) // \arg Peripheral clock identifier 0 .. 7 +{ + pPMC->PMC_SCDR = (1 << pck) << 8; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnableIt +//* \brief Enable PMC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_EnableIt ( + AT91PS_PMC pPMC, // pointer to a PMC controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pPMC->PMC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisableIt +//* \brief Disable PMC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_DisableIt ( + AT91PS_PMC pPMC, // pointer to a PMC controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pPMC->PMC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetStatus +//* \brief Return PMC Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status + AT91PS_PMC pPMC) // pointer to a PMC controller +{ + return pPMC->PMC_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetInterruptMaskStatus +//* \brief Return PMC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status + AT91PS_PMC pPMC) // pointer to a PMC controller +{ + return pPMC->PMC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_IsInterruptMasked +//* \brief Test if PMC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_IsInterruptMasked( + AT91PS_PMC pPMC, // \arg pointer to a PMC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_IsStatusSet +//* \brief Test if PMC Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_IsStatusSet( + AT91PS_PMC pPMC, // \arg pointer to a PMC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PMC_GetStatus(pPMC) & flag); +}/* ***************************************************************************** + SOFTWARE API FOR RSTC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTSoftReset +//* \brief Start Software Reset +//*---------------------------------------------------------------------------- +__inline void AT91F_RSTSoftReset( + AT91PS_RSTC pRSTC, + unsigned int reset) +{ + pRSTC->RSTC_RCR = (0xA5000000 | reset); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTSetMode +//* \brief Set Reset Mode +//*---------------------------------------------------------------------------- +__inline void AT91F_RSTSetMode( + AT91PS_RSTC pRSTC, + unsigned int mode) +{ + pRSTC->RSTC_RMR = (0xA5000000 | mode); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTGetMode +//* \brief Get Reset Mode +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_RSTGetMode( + AT91PS_RSTC pRSTC) +{ + return (pRSTC->RSTC_RMR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTGetStatus +//* \brief Get Reset Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_RSTGetStatus( + AT91PS_RSTC pRSTC) +{ + return (pRSTC->RSTC_RSR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTIsSoftRstActive +//* \brief Return !=0 if software reset is still not completed +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_RSTIsSoftRstActive( + AT91PS_RSTC pRSTC) +{ + return ((pRSTC->RSTC_RSR) & AT91C_RSTC_SRCMP); +} +/* ***************************************************************************** + SOFTWARE API FOR RTTC + ***************************************************************************** */ +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_SetRTT_TimeBase() +//* \brief Set the RTT prescaler according to the TimeBase in ms +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTSetTimeBase( + AT91PS_RTTC pRTTC, + unsigned int ms) +{ + if (ms > 2000) + return 1; // AT91C_TIME_OUT_OF_RANGE + pRTTC->RTTC_RTMR &= ~0xFFFF; + pRTTC->RTTC_RTMR |= (((ms << 15) /1000) & 0xFFFF); + return 0; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTTSetPrescaler() +//* \brief Set the new prescaler value +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTSetPrescaler( + AT91PS_RTTC pRTTC, + unsigned int rtpres) +{ + pRTTC->RTTC_RTMR &= ~0xFFFF; + pRTTC->RTTC_RTMR |= (rtpres & 0xFFFF); + return (pRTTC->RTTC_RTMR); +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTTRestart() +//* \brief Restart the RTT prescaler +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTRestart( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST; +} + + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_SetAlarmINT() +//* \brief Enable RTT Alarm Interrupt +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTSetAlarmINT( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_ClearAlarmINT() +//* \brief Disable RTT Alarm Interrupt +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTClearAlarmINT( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_SetRttIncINT() +//* \brief Enable RTT INC Interrupt +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTSetRttIncINT( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_ClearRttIncINT() +//* \brief Disable RTT INC Interrupt +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTClearRttIncINT( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_SetAlarmValue() +//* \brief Set RTT Alarm Value +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTSetAlarmValue( + AT91PS_RTTC pRTTC, unsigned int alarm) +{ + pRTTC->RTTC_RTAR = alarm; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_GetAlarmValue() +//* \brief Get RTT Alarm Value +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTGetAlarmValue( + AT91PS_RTTC pRTTC) +{ + return(pRTTC->RTTC_RTAR); +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTTGetStatus() +//* \brief Read the RTT status +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTGetStatus( + AT91PS_RTTC pRTTC) +{ + return(pRTTC->RTTC_RTSR); +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_ReadValue() +//* \brief Read the RTT value +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTReadValue( + AT91PS_RTTC pRTTC) +{ + register volatile unsigned int val1,val2; + do + { + val1 = pRTTC->RTTC_RTVR; + val2 = pRTTC->RTTC_RTVR; + } + while(val1 != val2); + return(val1); +} +/* ***************************************************************************** + SOFTWARE API FOR PITC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITInit +//* \brief System timer init : period in µsecond, system clock freq in MHz +//*---------------------------------------------------------------------------- +__inline void AT91F_PITInit( + AT91PS_PITC pPITC, + unsigned int period, + unsigned int pit_frequency) +{ + pPITC->PITC_PIMR = period? (period * pit_frequency + 8) >> 4 : 0; // +8 to avoid %10 and /10 + pPITC->PITC_PIMR |= AT91C_PITC_PITEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITSetPIV +//* \brief Set the PIT Periodic Interval Value +//*---------------------------------------------------------------------------- +__inline void AT91F_PITSetPIV( + AT91PS_PITC pPITC, + unsigned int piv) +{ + pPITC->PITC_PIMR = piv | (pPITC->PITC_PIMR & (AT91C_PITC_PITEN | AT91C_PITC_PITIEN)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITEnableInt +//* \brief Enable PIT periodic interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PITEnableInt( + AT91PS_PITC pPITC) +{ + pPITC->PITC_PIMR |= AT91C_PITC_PITIEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITDisableInt +//* \brief Disable PIT periodic interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PITDisableInt( + AT91PS_PITC pPITC) +{ + pPITC->PITC_PIMR &= ~AT91C_PITC_PITIEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITGetMode +//* \brief Read PIT mode register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PITGetMode( + AT91PS_PITC pPITC) +{ + return(pPITC->PITC_PIMR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITGetStatus +//* \brief Read PIT status register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PITGetStatus( + AT91PS_PITC pPITC) +{ + return(pPITC->PITC_PISR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITGetPIIR +//* \brief Read PIT CPIV and PICNT without ressetting the counters +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PITGetPIIR( + AT91PS_PITC pPITC) +{ + return(pPITC->PITC_PIIR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITGetPIVR +//* \brief Read System timer CPIV and PICNT without ressetting the counters +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PITGetPIVR( + AT91PS_PITC pPITC) +{ + return(pPITC->PITC_PIVR); +} +/* ***************************************************************************** + SOFTWARE API FOR WDTC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTSetMode +//* \brief Set Watchdog Mode Register +//*---------------------------------------------------------------------------- +__inline void AT91F_WDTSetMode( + AT91PS_WDTC pWDTC, + unsigned int Mode) +{ + pWDTC->WDTC_WDMR = Mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTRestart +//* \brief Restart Watchdog +//*---------------------------------------------------------------------------- +__inline void AT91F_WDTRestart( + AT91PS_WDTC pWDTC) +{ + pWDTC->WDTC_WDCR = 0xA5000001; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTSGettatus +//* \brief Get Watchdog Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_WDTSGettatus( + AT91PS_WDTC pWDTC) +{ + return(pWDTC->WDTC_WDSR & 0x3); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTGetPeriod +//* \brief Translate ms into Watchdog Compatible value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_WDTGetPeriod(unsigned int ms) +{ + if ((ms < 4) || (ms > 16000)) + return 0; + return((ms << 8) / 1000); +} +/* ***************************************************************************** + SOFTWARE API FOR VREG + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_VREG_Enable_LowPowerMode +//* \brief Enable VREG Low Power Mode +//*---------------------------------------------------------------------------- +__inline void AT91F_VREG_Enable_LowPowerMode( + AT91PS_VREG pVREG) +{ + pVREG->VREG_MR |= AT91C_VREG_PSTDBY; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_VREG_Disable_LowPowerMode +//* \brief Disable VREG Low Power Mode +//*---------------------------------------------------------------------------- +__inline void AT91F_VREG_Disable_LowPowerMode( + AT91PS_VREG pVREG) +{ + pVREG->VREG_MR &= ~AT91C_VREG_PSTDBY; +}/* ***************************************************************************** + SOFTWARE API FOR MC + ***************************************************************************** */ + +#define AT91C_MC_CORRECT_KEY ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_Remap +//* \brief Make Remap +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_Remap (void) // +{ + AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC; + + pMC->MC_RCR = AT91C_MC_RCB; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_CfgModeReg +//* \brief Configure the EFC Mode Register of the MC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_EFC_CfgModeReg ( + AT91PS_MC pMC, // pointer to a MC controller + unsigned int mode) // mode register +{ + // Write to the FMR register + pMC->MC_FMR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_GetModeReg +//* \brief Return MC EFC Mode Regsiter +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_GetModeReg( + AT91PS_MC pMC) // pointer to a MC controller +{ + return pMC->MC_FMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_ComputeFMCN +//* \brief Return MC EFC Mode Regsiter +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_ComputeFMCN( + int master_clock) // master clock in Hz +{ + return (master_clock/1000000 +2); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_PerformCmd +//* \brief Perform EFC Command +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_EFC_PerformCmd ( + AT91PS_MC pMC, // pointer to a MC controller + unsigned int transfer_cmd) +{ + pMC->MC_FCR = transfer_cmd; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_GetStatus +//* \brief Return MC EFC Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_GetStatus( + AT91PS_MC pMC) // pointer to a MC controller +{ + return pMC->MC_FSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_IsInterruptMasked +//* \brief Test if EFC MC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_IsInterruptMasked( + AT91PS_MC pMC, // \arg pointer to a MC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_MC_EFC_GetModeReg(pMC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_IsInterruptSet +//* \brief Test if EFC MC Interrupt is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_IsInterruptSet( + AT91PS_MC pMC, // \arg pointer to a MC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_MC_EFC_GetStatus(pMC) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR SPI + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Open +//* \brief Open a SPI Port +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_Open ( + const unsigned int null) // \arg +{ + /* NOT DEFINED AT THIS MOMENT */ + return ( 0 ); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgCs +//* \brief Configure SPI chip select register +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgCs ( + AT91PS_SPI pSPI, // pointer to a SPI controller + int cs, // SPI cs number (0 to 3) + int val) // chip select register +{ + //* Write to the CSR register + *(pSPI->SPI_CSR + cs) = val; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_EnableIt +//* \brief Enable SPI interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_EnableIt ( + AT91PS_SPI pSPI, // pointer to a SPI controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pSPI->SPI_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_DisableIt +//* \brief Disable SPI interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_DisableIt ( + AT91PS_SPI pSPI, // pointer to a SPI controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pSPI->SPI_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Reset +//* \brief Reset the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Reset ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Enable +//* \brief Enable the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Enable ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SPIEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Disable +//* \brief Disable the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Disable ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SPIDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgMode +//* \brief Enable the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgMode ( + AT91PS_SPI pSPI, // pointer to a SPI controller + int mode) // mode register +{ + //* Write to the MR register + pSPI->SPI_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgPCS +//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgPCS ( + AT91PS_SPI pSPI, // pointer to a SPI controller + char PCS_Device) // PCS of the Device +{ + //* Write to the MR register + pSPI->SPI_MR &= 0xFFF0FFFF; + pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS ); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_ReceiveFrame ( + AT91PS_SPI pSPI, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pSPI->SPI_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_SendFrame( + AT91PS_SPI pSPI, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pSPI->SPI_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Close +//* \brief Close SPI: disable IT disable transfert, close PDC +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Close ( + AT91PS_SPI pSPI) // \arg pointer to a SPI controller +{ + //* Reset all the Chip Select register + pSPI->SPI_CSR[0] = 0 ; + pSPI->SPI_CSR[1] = 0 ; + pSPI->SPI_CSR[2] = 0 ; + pSPI->SPI_CSR[3] = 0 ; + + //* Reset the SPI mode + pSPI->SPI_MR = 0 ; + + //* Disable all interrupts + pSPI->SPI_IDR = 0xFFFFFFFF ; + + //* Abort the Peripheral Data Transfers + AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR)); + + //* Disable receiver and transmitter and stop any activity immediately + pSPI->SPI_CR = AT91C_SPI_SPIDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_PutChar +//* \brief Send a character,does not check if ready to send +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_PutChar ( + AT91PS_SPI pSPI, + unsigned int character, + unsigned int cs_number ) +{ + unsigned int value_for_cs; + value_for_cs = (~(1 << cs_number)) & 0xF; //Place a zero among a 4 ONEs number + pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_GetChar +//* \brief Receive a character,does not check if a character is available +//*---------------------------------------------------------------------------- +__inline int AT91F_SPI_GetChar ( + const AT91PS_SPI pSPI) +{ + return((pSPI->SPI_RDR) & 0xFFFF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_GetInterruptMaskStatus +//* \brief Return SPI Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status + AT91PS_SPI pSpi) // \arg pointer to a SPI controller +{ + return pSpi->SPI_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_IsInterruptMasked +//* \brief Test if SPI Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_SPI_IsInterruptMasked( + AT91PS_SPI pSpi, // \arg pointer to a SPI controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR USART + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Baudrate +//* \brief Calculate the baudrate +//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_EXT ) + +//* Standard Synchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \ + AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//* SCK used Label +#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT) + +//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity +#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \ + AT91C_US_CLKS_CLOCK +\ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_EVEN + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CKLO +\ + AT91C_US_OVER) + +//* Standard IRDA mode +#define AT91C_US_ASYNC_IRDA_MODE ( AT91C_US_USMODE_IRDA + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Baudrate +//* \brief Caluculate baud_value according to the main clock and the baud rate +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_Baudrate ( + const unsigned int main_clock, // \arg peripheral clock + const unsigned int baud_rate) // \arg UART baudrate +{ + unsigned int baud_value = ((main_clock*10)/(baud_rate * 16)); + if ((baud_value % 10) >= 5) + baud_value = (baud_value / 10) + 1; + else + baud_value /= 10; + return baud_value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetBaudrate +//* \brief Set the baudrate according to the CPU clock +//*---------------------------------------------------------------------------- +__inline void AT91F_US_SetBaudrate ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int mainClock, // \arg peripheral clock + unsigned int speed) // \arg UART baudrate +{ + //* Define the baud rate divisor register + pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetTimeguard +//* \brief Set USART timeguard +//*---------------------------------------------------------------------------- +__inline void AT91F_US_SetTimeguard ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int timeguard) // \arg timeguard value +{ + //* Write the Timeguard Register + pUSART->US_TTGR = timeguard ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableIt +//* \brief Enable USART IT +//*---------------------------------------------------------------------------- +__inline void AT91F_US_EnableIt ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pUSART->US_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableIt +//* \brief Disable USART IT +//*---------------------------------------------------------------------------- +__inline void AT91F_US_DisableIt ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IER register + pUSART->US_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Configure +//* \brief Configure USART +//*---------------------------------------------------------------------------- +__inline void AT91F_US_Configure ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int mainClock, // \arg peripheral clock + unsigned int mode , // \arg mode Register to be programmed + unsigned int baudRate , // \arg baudrate to be programmed + unsigned int timeguard ) // \arg timeguard to be programmed +{ + //* Disable interrupts + pUSART->US_IDR = (unsigned int) -1; + + //* Reset receiver and transmitter + pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ; + + //* Define the baud rate divisor register + AT91F_US_SetBaudrate(pUSART, mainClock, baudRate); + + //* Write the Timeguard Register + AT91F_US_SetTimeguard(pUSART, timeguard); + + //* Clear Transmit and Receive Counters + AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR)); + + //* Define the USART mode + pUSART->US_MR = mode ; + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableRx +//* \brief Enable receiving characters +//*---------------------------------------------------------------------------- +__inline void AT91F_US_EnableRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Enable receiver + pUSART->US_CR = AT91C_US_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableTx +//* \brief Enable sending characters +//*---------------------------------------------------------------------------- +__inline void AT91F_US_EnableTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Enable transmitter + pUSART->US_CR = AT91C_US_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ResetRx +//* \brief Reset Receiver and re-enable it +//*---------------------------------------------------------------------------- +__inline void AT91F_US_ResetRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset receiver + pUSART->US_CR = AT91C_US_RSTRX; + //* Re-Enable receiver + pUSART->US_CR = AT91C_US_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ResetTx +//* \brief Reset Transmitter and re-enable it +//*---------------------------------------------------------------------------- +__inline void AT91F_US_ResetTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset transmitter + pUSART->US_CR = AT91C_US_RSTTX; + //* Enable transmitter + pUSART->US_CR = AT91C_US_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableRx +//* \brief Disable Receiver +//*---------------------------------------------------------------------------- +__inline void AT91F_US_DisableRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Disable receiver + pUSART->US_CR = AT91C_US_RXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableTx +//* \brief Disable Transmitter +//*---------------------------------------------------------------------------- +__inline void AT91F_US_DisableTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Disable transmitter + pUSART->US_CR = AT91C_US_TXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Close +//* \brief Close USART: disable IT disable receiver and transmitter, close PDC +//*---------------------------------------------------------------------------- +__inline void AT91F_US_Close ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset the baud rate divisor register + pUSART->US_BRGR = 0 ; + + //* Reset the USART mode + pUSART->US_MR = 0 ; + + //* Reset the Timeguard Register + pUSART->US_TTGR = 0; + + //* Disable all interrupts + pUSART->US_IDR = 0xFFFFFFFF ; + + //* Abort the Peripheral Data Transfers + AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR)); + + //* Disable receiver and transmitter and stop any activity immediately + pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_TxReady +//* \brief Return 1 if a character can be written in US_THR +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_TxReady ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & AT91C_US_TXRDY); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_RxReady +//* \brief Return 1 if a character can be read in US_RHR +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_RxReady ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & AT91C_US_RXRDY); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Error +//* \brief Return the error flag +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_Error ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & + (AT91C_US_OVRE | // Overrun error + AT91C_US_FRAME | // Framing error + AT91C_US_PARE)); // Parity error +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_PutChar +//* \brief Send a character,does not check if ready to send +//*---------------------------------------------------------------------------- +__inline void AT91F_US_PutChar ( + AT91PS_USART pUSART, + int character ) +{ + pUSART->US_THR = (character & 0x1FF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_GetChar +//* \brief Receive a character,does not check if a character is available +//*---------------------------------------------------------------------------- +__inline int AT91F_US_GetChar ( + const AT91PS_USART pUSART) +{ + return((pUSART->US_RHR) & 0x1FF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_SendFrame( + AT91PS_USART pUSART, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pUSART->US_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_ReceiveFrame ( + AT91PS_USART pUSART, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pUSART->US_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetIrdaFilter +//* \brief Set the value of IrDa filter tregister +//*---------------------------------------------------------------------------- +__inline void AT91F_US_SetIrdaFilter ( + AT91PS_USART pUSART, + unsigned char value +) +{ + pUSART->US_IF = value; +} + +/* ***************************************************************************** + SOFTWARE API FOR SSC + ***************************************************************************** */ +//* Define the standard I2S mode configuration + +//* Configuration to set in the SSC Transmit Clock Mode Register +//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits +//* nb_slot_by_frame : number of channels +#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ + AT91C_SSC_CKS_DIV +\ + AT91C_SSC_CKO_CONTINOUS +\ + AT91C_SSC_CKG_NONE +\ + AT91C_SSC_START_FALL_RF +\ + AT91C_SSC_STTOUT +\ + ((1<<16) & AT91C_SSC_STTDLY) +\ + ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24)) + + +//* Configuration to set in the SSC Transmit Frame Mode Register +//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits +//* nb_slot_by_frame : number of channels +#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ + (nb_bit_by_slot-1) +\ + AT91C_SSC_MSBF +\ + (((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB) +\ + (((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\ + AT91C_SSC_FSOS_NEGATIVE) + + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_SetBaudrate +//* \brief Set the baudrate according to the CPU clock +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_SetBaudrate ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int mainClock, // \arg peripheral clock + unsigned int speed) // \arg SSC baudrate +{ + unsigned int baud_value; + //* Define the baud rate divisor register + if (speed == 0) + baud_value = 0; + else + { + baud_value = (unsigned int) (mainClock * 10)/(2*speed); + if ((baud_value % 10) >= 5) + baud_value = (baud_value / 10) + 1; + else + baud_value /= 10; + } + + pSSC->SSC_CMR = baud_value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_Configure +//* \brief Configure SSC +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_Configure ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int syst_clock, // \arg System Clock Frequency + unsigned int baud_rate, // \arg Expected Baud Rate Frequency + unsigned int clock_rx, // \arg Receiver Clock Parameters + unsigned int mode_rx, // \arg mode Register to be programmed + unsigned int clock_tx, // \arg Transmitter Clock Parameters + unsigned int mode_tx) // \arg mode Register to be programmed +{ + //* Disable interrupts + pSSC->SSC_IDR = (unsigned int) -1; + + //* Reset receiver and transmitter + pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ; + + //* Define the Clock Mode Register + AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate); + + //* Write the Receive Clock Mode Register + pSSC->SSC_RCMR = clock_rx; + + //* Write the Transmit Clock Mode Register + pSSC->SSC_TCMR = clock_tx; + + //* Write the Receive Frame Mode Register + pSSC->SSC_RFMR = mode_rx; + + //* Write the Transmit Frame Mode Register + pSSC->SSC_TFMR = mode_tx; + + //* Clear Transmit and Receive Counters + AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR)); + + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableRx +//* \brief Enable receiving datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_EnableRx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Enable receiver + pSSC->SSC_CR = AT91C_SSC_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableRx +//* \brief Disable receiving datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_DisableRx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Disable receiver + pSSC->SSC_CR = AT91C_SSC_RXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableTx +//* \brief Enable sending datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_EnableTx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Enable transmitter + pSSC->SSC_CR = AT91C_SSC_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableTx +//* \brief Disable sending datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_DisableTx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Disable transmitter + pSSC->SSC_CR = AT91C_SSC_TXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableIt +//* \brief Enable SSC IT +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_EnableIt ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pSSC->SSC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableIt +//* \brief Disable SSC IT +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_DisableIt ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pSSC->SSC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SSC_ReceiveFrame ( + AT91PS_SSC pSSC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pSSC->SSC_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SSC_SendFrame( + AT91PS_SSC pSSC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pSSC->SSC_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_GetInterruptMaskStatus +//* \brief Return SSC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status + AT91PS_SSC pSsc) // \arg pointer to a SSC controller +{ + return pSsc->SSC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_IsInterruptMasked +//* \brief Test if SSC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_SSC_IsInterruptMasked( + AT91PS_SSC pSsc, // \arg pointer to a SSC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR TWI + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_EnableIt +//* \brief Enable TWI IT +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_EnableIt ( + AT91PS_TWI pTWI, // \arg pointer to a TWI controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pTWI->TWI_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_DisableIt +//* \brief Disable TWI IT +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_DisableIt ( + AT91PS_TWI pTWI, // \arg pointer to a TWI controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pTWI->TWI_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_Configure +//* \brief Configure TWI in master mode +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI ) // \arg pointer to a TWI controller +{ + //* Disable interrupts + pTWI->TWI_IDR = (unsigned int) -1; + + //* Reset peripheral + pTWI->TWI_CR = AT91C_TWI_SWRST; + + //* Set Master mode + pTWI->TWI_CR = AT91C_TWI_MSEN; + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_GetInterruptMaskStatus +//* \brief Return TWI Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status + AT91PS_TWI pTwi) // \arg pointer to a TWI controller +{ + return pTwi->TWI_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_IsInterruptMasked +//* \brief Test if TWI Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_TWI_IsInterruptMasked( + AT91PS_TWI pTwi, // \arg pointer to a TWI controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR PWMC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_GetStatus +//* \brief Return PWM Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status + AT91PS_PWMC pPWM) // pointer to a PWM controller +{ + return pPWM->PWMC_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_InterruptEnable +//* \brief Enable PWM Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_InterruptEnable( + AT91PS_PWMC pPwm, // \arg pointer to a PWM controller + unsigned int flag) // \arg PWM interrupt to be enabled +{ + pPwm->PWMC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_InterruptDisable +//* \brief Disable PWM Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_InterruptDisable( + AT91PS_PWMC pPwm, // \arg pointer to a PWM controller + unsigned int flag) // \arg PWM interrupt to be disabled +{ + pPwm->PWMC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_GetInterruptMaskStatus +//* \brief Return PWM Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status + AT91PS_PWMC pPwm) // \arg pointer to a PWM controller +{ + return pPwm->PWMC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_IsInterruptMasked +//* \brief Test if PWM Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_IsInterruptMasked( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_IsStatusSet +//* \brief Test if PWM Interrupt is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_IsStatusSet( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PWMC_GetStatus(pPWM) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_CfgChannel +//* \brief Test if PWM Interrupt is Set +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CfgChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int channelId, // \arg PWM channel ID + unsigned int mode, // \arg PWM mode + unsigned int period, // \arg PWM period + unsigned int duty) // \arg PWM duty cycle +{ + pPWM->PWMC_CH[channelId].PWMC_CMR = mode; + pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty; + pPWM->PWMC_CH[channelId].PWMC_CPRDR = period; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_StartChannel +//* \brief Enable channel +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_StartChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg Channels IDs to be enabled +{ + pPWM->PWMC_ENA = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_StopChannel +//* \brief Disable channel +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_StopChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg Channels IDs to be enabled +{ + pPWM->PWMC_DIS = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_UpdateChannel +//* \brief Update Period or Duty Cycle +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_UpdateChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int channelId, // \arg PWM channel ID + unsigned int update) // \arg Channels IDs to be enabled +{ + pPWM->PWMC_CH[channelId].PWMC_CUPDR = update; +} + +/* ***************************************************************************** + SOFTWARE API FOR UDP + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EnableIt +//* \brief Enable UDP IT +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EnableIt ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pUDP->UDP_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_DisableIt +//* \brief Disable UDP IT +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_DisableIt ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pUDP->UDP_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_SetAddress +//* \brief Set UDP functional address +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_SetAddress ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char address) // \arg new UDP address +{ + pUDP->UDP_FADDR = (AT91C_UDP_FEN | address); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EnableEp +//* \brief Enable Endpoint +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EnableEp ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] |= AT91C_UDP_EPEDS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_DisableEp +//* \brief Enable Endpoint +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_DisableEp ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] &= ~AT91C_UDP_EPEDS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_SetState +//* \brief Set UDP Device state +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_SetState ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg new UDP address +{ + pUDP->UDP_GLBSTATE &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG); + pUDP->UDP_GLBSTATE |= flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_GetState +//* \brief return UDP Device state +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state + AT91PS_UDP pUDP) // \arg pointer to a UDP controller +{ + return (pUDP->UDP_GLBSTATE & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_ResetEp +//* \brief Reset UDP endpoint +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_ResetEp ( // \return the UDP device state + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg Endpoints to be reset +{ + pUDP->UDP_RSTEP = flag; + pUDP->UDP_RSTEP = 0; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpStall +//* \brief Endpoint will STALL requests +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpStall( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpWrite +//* \brief Write value in the DPR +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpWrite( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned char value) // \arg value to be written in the DPR +{ + pUDP->UDP_FDR[endpoint] = value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpRead +//* \brief Return value from the DPR +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_EpRead( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + return pUDP->UDP_FDR[endpoint]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpEndOfWr +//* \brief Notify the UDP that values in DPR are ready to be sent +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpEndOfWr( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpClear +//* \brief Clear flag in the endpoint CSR register +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpClear( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned int flag) // \arg flag to be cleared +{ + pUDP->UDP_CSR[endpoint] &= ~(flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpSet +//* \brief Set flag in the endpoint CSR register +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpSet( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned int flag) // \arg flag to be cleared +{ + pUDP->UDP_CSR[endpoint] |= flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpStatus +//* \brief Return the endpoint CSR register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_EpStatus( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + return pUDP->UDP_CSR[endpoint]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_GetInterruptMaskStatus +//* \brief Return UDP Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status + AT91PS_UDP pUdp) // \arg pointer to a UDP controller +{ + return pUdp->UDP_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_IsInterruptMasked +//* \brief Test if UDP Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_UDP_IsInterruptMasked( + AT91PS_UDP pUdp, // \arg pointer to a UDP controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR TC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_InterruptEnable +//* \brief Enable TC Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TC_InterruptEnable( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg TC interrupt to be enabled +{ + pTc->TC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_InterruptDisable +//* \brief Disable TC Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TC_InterruptDisable( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg TC interrupt to be disabled +{ + pTc->TC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_GetInterruptMaskStatus +//* \brief Return TC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status + AT91PS_TC pTc) // \arg pointer to a TC controller +{ + return pTc->TC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_IsInterruptMasked +//* \brief Test if TC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_TC_IsInterruptMasked( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR CAN + ***************************************************************************** */ +#define STANDARD_FORMAT 0 +#define EXTENDED_FORMAT 1 + +//*---------------------------------------------------------------------------- +//* \fn AT91F_InitMailboxRegisters() +//* \brief Configure the corresponding mailbox +//*---------------------------------------------------------------------------- +__inline void AT91F_InitMailboxRegisters(AT91PS_CAN_MB CAN_Mailbox, + int mode_reg, + int acceptance_mask_reg, + int id_reg, + int data_low_reg, + int data_high_reg, + int control_reg) +{ + CAN_Mailbox->CAN_MB_MCR = 0x0; + CAN_Mailbox->CAN_MB_MMR = mode_reg; + CAN_Mailbox->CAN_MB_MAM = acceptance_mask_reg; + CAN_Mailbox->CAN_MB_MID = id_reg; + CAN_Mailbox->CAN_MB_MDL = data_low_reg; + CAN_Mailbox->CAN_MB_MDH = data_high_reg; + CAN_Mailbox->CAN_MB_MCR = control_reg; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_EnableCAN() +//* \brief +//*---------------------------------------------------------------------------- +__inline void AT91F_EnableCAN( + AT91PS_CAN pCAN) // pointer to a CAN controller +{ + pCAN->CAN_MR |= AT91C_CAN_CANEN; + + // Wait for WAKEUP flag raising <=> 11-recessive-bit were scanned by the transceiver + while( (pCAN->CAN_SR & AT91C_CAN_WAKEUP) != AT91C_CAN_WAKEUP ); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DisableCAN() +//* \brief +//*---------------------------------------------------------------------------- +__inline void AT91F_DisableCAN( + AT91PS_CAN pCAN) // pointer to a CAN controller +{ + pCAN->CAN_MR &= ~AT91C_CAN_CANEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_EnableIt +//* \brief Enable CAN interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_EnableIt ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pCAN->CAN_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_DisableIt +//* \brief Disable CAN interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_DisableIt ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pCAN->CAN_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetStatus +//* \brief Return CAN Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetStatus( // \return CAN Interrupt Status + AT91PS_CAN pCAN) // pointer to a CAN controller +{ + return pCAN->CAN_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetInterruptMaskStatus +//* \brief Return CAN Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetInterruptMaskStatus( // \return CAN Interrupt Mask Status + AT91PS_CAN pCAN) // pointer to a CAN controller +{ + return pCAN->CAN_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_IsInterruptMasked +//* \brief Test if CAN Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_IsInterruptMasked( + AT91PS_CAN pCAN, // \arg pointer to a CAN controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_CAN_GetInterruptMaskStatus(pCAN) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_IsStatusSet +//* \brief Test if CAN Interrupt is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_IsStatusSet( + AT91PS_CAN pCAN, // \arg pointer to a CAN controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_CAN_GetStatus(pCAN) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgModeReg +//* \brief Configure the Mode Register of the CAN controller +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgModeReg ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int mode) // mode register +{ + //* Write to the MR register + pCAN->CAN_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetModeReg +//* \brief Return the Mode Register of the CAN controller value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetModeReg ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_MR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgBaudrateReg +//* \brief Configure the Baudrate of the CAN controller for the network +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgBaudrateReg ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int baudrate_cfg) +{ + //* Write to the BR register + pCAN->CAN_BR = baudrate_cfg; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetBaudrate +//* \brief Return the Baudrate of the CAN controller for the network value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetBaudrate ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_BR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetInternalCounter +//* \brief Return CAN Timer Regsiter Value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetInternalCounter ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_TIM; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetTimestamp +//* \brief Return CAN Timestamp Register Value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetTimestamp ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_TIMESTP; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetErrorCounter +//* \brief Return CAN Error Counter Register Value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetErrorCounter ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_ECR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_InitTransferRequest +//* \brief Request for a transfer on the corresponding mailboxes +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_InitTransferRequest ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int transfer_cmd) +{ + pCAN->CAN_TCR = transfer_cmd; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_InitAbortRequest +//* \brief Abort the corresponding mailboxes +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_InitAbortRequest ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int abort_cmd) +{ + pCAN->CAN_ACR = abort_cmd; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageModeReg +//* \brief Program the Message Mode Register +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageModeReg ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int mode) +{ + CAN_Mailbox->CAN_MB_MMR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageModeReg +//* \brief Return the Message Mode Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageModeReg ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageIDReg +//* \brief Program the Message ID Register +//* \brief Version == 0 for Standard messsage, Version == 1 for Extended +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageIDReg ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int id, + unsigned char version) +{ + if(version==0) // IDvA Standard Format + CAN_Mailbox->CAN_MB_MID = id<<18; + else // IDvB Extended Format + CAN_Mailbox->CAN_MB_MID = id | (1<<29); // set MIDE bit +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageIDReg +//* \brief Return the Message ID Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageIDReg ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MID; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageAcceptanceMaskReg +//* \brief Program the Message Acceptance Mask Register +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageAcceptanceMaskReg ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int mask) +{ + CAN_Mailbox->CAN_MB_MAM = mask; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageAcceptanceMaskReg +//* \brief Return the Message Acceptance Mask Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageAcceptanceMaskReg ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MAM; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetFamilyID +//* \brief Return the Message ID Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetFamilyID ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MFID; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageCtrl +//* \brief Request and config for a transfer on the corresponding mailbox +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageCtrlReg ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int message_ctrl_cmd) +{ + CAN_Mailbox->CAN_MB_MCR = message_ctrl_cmd; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageStatus +//* \brief Return CAN Mailbox Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageStatus ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageDataLow +//* \brief Program data low value +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageDataLow ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int data) +{ + CAN_Mailbox->CAN_MB_MDL = data; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageDataLow +//* \brief Return data low value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageDataLow ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MDL; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageDataHigh +//* \brief Program data high value +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageDataHigh ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int data) +{ + CAN_Mailbox->CAN_MB_MDH = data; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageDataHigh +//* \brief Return data high value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageDataHigh ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MDH; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_Open +//* \brief Open a CAN Port +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_Open ( + const unsigned int null) // \arg +{ + /* NOT DEFINED AT THIS MOMENT */ + return ( 0 ); +} +/* ***************************************************************************** + SOFTWARE API FOR ADC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_EnableIt +//* \brief Enable ADC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_EnableIt ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pADC->ADC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_DisableIt +//* \brief Disable ADC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_DisableIt ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pADC->ADC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetStatus +//* \brief Return ADC Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status + AT91PS_ADC pADC) // pointer to a ADC controller +{ + return pADC->ADC_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetInterruptMaskStatus +//* \brief Return ADC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status + AT91PS_ADC pADC) // pointer to a ADC controller +{ + return pADC->ADC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_IsInterruptMasked +//* \brief Test if ADC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_IsInterruptMasked( + AT91PS_ADC pADC, // \arg pointer to a ADC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_IsStatusSet +//* \brief Test if ADC Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_IsStatusSet( + AT91PS_ADC pADC, // \arg pointer to a ADC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_ADC_GetStatus(pADC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgModeReg +//* \brief Configure the Mode Register of the ADC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgModeReg ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int mode) // mode register +{ + //* Write to the MR register + pADC->ADC_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetModeReg +//* \brief Return the Mode Register of the ADC controller value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetModeReg ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_MR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgTimings +//* \brief Configure the different necessary timings of the ADC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgTimings ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int mck_clock, // in MHz + unsigned int adc_clock, // in MHz + unsigned int startup_time, // in us + unsigned int sample_and_hold_time) // in ns +{ + unsigned int prescal,startup,shtim; + + prescal = mck_clock/(2*adc_clock) - 1; + startup = adc_clock*startup_time/8 - 1; + shtim = adc_clock*sample_and_hold_time/1000 - 1; + + //* Write to the MR register + pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_EnableChannel +//* \brief Return ADC Timer Register Value +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_EnableChannel ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int channel) // mode register +{ + //* Write to the CHER register + pADC->ADC_CHER = channel; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_DisableChannel +//* \brief Return ADC Timer Register Value +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_DisableChannel ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int channel) // mode register +{ + //* Write to the CHDR register + pADC->ADC_CHDR = channel; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetChannelStatus +//* \brief Return ADC Timer Register Value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetChannelStatus ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CHSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_StartConversion +//* \brief Software request for a analog to digital conversion +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_StartConversion ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + pADC->ADC_CR = AT91C_ADC_START; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_SoftReset +//* \brief Software reset +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_SoftReset ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + pADC->ADC_CR = AT91C_ADC_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetLastConvertedData +//* \brief Return the Last Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetLastConvertedData ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_LCDR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH0 +//* \brief Return the Channel 0 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH0 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR0; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH1 +//* \brief Return the Channel 1 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH1 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR1; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH2 +//* \brief Return the Channel 2 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH2 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR2; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH3 +//* \brief Return the Channel 3 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH3 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR3; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH4 +//* \brief Return the Channel 4 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH4 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR4; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH5 +//* \brief Return the Channel 5 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH5 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR5; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH6 +//* \brief Return the Channel 6 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH6 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR6; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH7 +//* \brief Return the Channel 7 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH7 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR7; +} + +/* ***************************************************************************** + SOFTWARE API FOR AES + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_EnableIt +//* \brief Enable AES interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_EnableIt ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pAES->AES_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_DisableIt +//* \brief Disable AES interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_DisableIt ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pAES->AES_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_GetStatus +//* \brief Return AES Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_GetStatus( // \return AES Interrupt Status + AT91PS_AES pAES) // pointer to a AES controller +{ + return pAES->AES_ISR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_GetInterruptMaskStatus +//* \brief Return AES Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_GetInterruptMaskStatus( // \return AES Interrupt Mask Status + AT91PS_AES pAES) // pointer to a AES controller +{ + return pAES->AES_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_IsInterruptMasked +//* \brief Test if AES Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_IsInterruptMasked( + AT91PS_AES pAES, // \arg pointer to a AES controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_AES_GetInterruptMaskStatus(pAES) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_IsStatusSet +//* \brief Test if AES Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_IsStatusSet( + AT91PS_AES pAES, // \arg pointer to a AES controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_AES_GetStatus(pAES) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_CfgModeReg +//* \brief Configure the Mode Register of the AES controller +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_CfgModeReg ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned int mode) // mode register +{ + //* Write to the MR register + pAES->AES_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_GetModeReg +//* \brief Return the Mode Register of the AES controller value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_GetModeReg ( + AT91PS_AES pAES // pointer to a AES controller + ) +{ + return pAES->AES_MR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_StartProcessing +//* \brief Start Encryption or Decryption +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_StartProcessing ( + AT91PS_AES pAES // pointer to a AES controller + ) +{ + pAES->AES_CR = AT91C_AES_START; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_SoftReset +//* \brief Reset AES +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_SoftReset ( + AT91PS_AES pAES // pointer to a AES controller + ) +{ + pAES->AES_CR = AT91C_AES_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_LoadNewSeed +//* \brief Load New Seed in the random number generator +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_LoadNewSeed ( + AT91PS_AES pAES // pointer to a AES controller + ) +{ + pAES->AES_CR = AT91C_AES_LOADSEED; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_SetCryptoKey +//* \brief Set Cryptographic Key x +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_SetCryptoKey ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned char index, + unsigned int keyword + ) +{ + pAES->AES_KEYWxR[index] = keyword; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_InputData +//* \brief Set Input Data x +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_InputData ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned char index, + unsigned int indata + ) +{ + pAES->AES_IDATAxR[index] = indata; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_GetOutputData +//* \brief Get Output Data x +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_GetOutputData ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned char index + ) +{ + return pAES->AES_ODATAxR[index]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_SetInitializationVector +//* \brief Set Initialization Vector (or Counter) x +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_SetInitializationVector ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned char index, + unsigned int initvector + ) +{ + pAES->AES_IVxR[index] = initvector; +} + +/* ***************************************************************************** + SOFTWARE API FOR TDES + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_EnableIt +//* \brief Enable TDES interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_EnableIt ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pTDES->TDES_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_DisableIt +//* \brief Disable TDES interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_DisableIt ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pTDES->TDES_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_GetStatus +//* \brief Return TDES Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_GetStatus( // \return TDES Interrupt Status + AT91PS_TDES pTDES) // pointer to a TDES controller +{ + return pTDES->TDES_ISR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_GetInterruptMaskStatus +//* \brief Return TDES Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_GetInterruptMaskStatus( // \return TDES Interrupt Mask Status + AT91PS_TDES pTDES) // pointer to a TDES controller +{ + return pTDES->TDES_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_IsInterruptMasked +//* \brief Test if TDES Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_IsInterruptMasked( + AT91PS_TDES pTDES, // \arg pointer to a TDES controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TDES_GetInterruptMaskStatus(pTDES) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_IsStatusSet +//* \brief Test if TDES Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_IsStatusSet( + AT91PS_TDES pTDES, // \arg pointer to a TDES controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TDES_GetStatus(pTDES) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_CfgModeReg +//* \brief Configure the Mode Register of the TDES controller +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_CfgModeReg ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned int mode) // mode register +{ + //* Write to the MR register + pTDES->TDES_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_GetModeReg +//* \brief Return the Mode Register of the TDES controller value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_GetModeReg ( + AT91PS_TDES pTDES // pointer to a TDES controller + ) +{ + return pTDES->TDES_MR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_StartProcessing +//* \brief Start Encryption or Decryption +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_StartProcessing ( + AT91PS_TDES pTDES // pointer to a TDES controller + ) +{ + pTDES->TDES_CR = AT91C_TDES_START; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SoftReset +//* \brief Reset TDES +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SoftReset ( + AT91PS_TDES pTDES // pointer to a TDES controller + ) +{ + pTDES->TDES_CR = AT91C_TDES_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SetCryptoKey1 +//* \brief Set Cryptographic Key 1 Word x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SetCryptoKey1 ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int keyword + ) +{ + pTDES->TDES_KEY1WxR[index] = keyword; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SetCryptoKey2 +//* \brief Set Cryptographic Key 2 Word x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SetCryptoKey2 ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int keyword + ) +{ + pTDES->TDES_KEY2WxR[index] = keyword; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SetCryptoKey3 +//* \brief Set Cryptographic Key 3 Word x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SetCryptoKey3 ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int keyword + ) +{ + pTDES->TDES_KEY3WxR[index] = keyword; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_InputData +//* \brief Set Input Data x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_InputData ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int indata + ) +{ + pTDES->TDES_IDATAxR[index] = indata; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_GetOutputData +//* \brief Get Output Data x +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_GetOutputData ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index + ) +{ + return pTDES->TDES_ODATAxR[index]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SetInitializationVector +//* \brief Set Initialization Vector x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SetInitializationVector ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int initvector + ) +{ + pTDES->TDES_IVxR[index] = initvector; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_CfgPMC +//* \brief Enable Peripheral clock in PMC for DBGU +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_CfgPIO +//* \brief Configure PIO controllers to drive DBGU signals +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA27_DRXD ) | + ((unsigned int) AT91C_PA28_DTXD ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgPMC +//* \brief Enable Peripheral clock in PMC for PMC +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgPIO +//* \brief Configure PIO controllers to drive PMC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB30_PCK2 ) | + ((unsigned int) AT91C_PB29_PCK1 ), // Peripheral A + ((unsigned int) AT91C_PB20_PCK0 ) | + ((unsigned int) AT91C_PB0_PCK0 ) | + ((unsigned int) AT91C_PB22_PCK2 ) | + ((unsigned int) AT91C_PB21_PCK1 )); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA30_PCK2 ) | + ((unsigned int) AT91C_PA13_PCK1 ) | + ((unsigned int) AT91C_PA27_PCK3 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_VREG_CfgPMC +//* \brief Enable Peripheral clock in PMC for VREG +//*---------------------------------------------------------------------------- +__inline void AT91F_VREG_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTC_CfgPMC +//* \brief Enable Peripheral clock in PMC for RSTC +//*---------------------------------------------------------------------------- +__inline void AT91F_RSTC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_CfgPMC +//* \brief Enable Peripheral clock in PMC for SSC +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SSC)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_CfgPIO +//* \brief Configure PIO controllers to drive SSC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA25_RK ) | + ((unsigned int) AT91C_PA22_TK ) | + ((unsigned int) AT91C_PA21_TF ) | + ((unsigned int) AT91C_PA24_RD ) | + ((unsigned int) AT91C_PA26_RF ) | + ((unsigned int) AT91C_PA23_TD ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTC_CfgPMC +//* \brief Enable Peripheral clock in PMC for WDTC +//*---------------------------------------------------------------------------- +__inline void AT91F_WDTC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US1_CfgPMC +//* \brief Enable Peripheral clock in PMC for US1 +//*---------------------------------------------------------------------------- +__inline void AT91F_US1_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_US1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US1_CfgPIO +//* \brief Configure PIO controllers to drive US1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_US1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PB26_RI1 ) | + ((unsigned int) AT91C_PB24_DSR1 ) | + ((unsigned int) AT91C_PB23_DCD1 ) | + ((unsigned int) AT91C_PB25_DTR1 )); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA7_SCK1 ) | + ((unsigned int) AT91C_PA8_RTS1 ) | + ((unsigned int) AT91C_PA6_TXD1 ) | + ((unsigned int) AT91C_PA5_RXD1 ) | + ((unsigned int) AT91C_PA9_CTS1 ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US0_CfgPMC +//* \brief Enable Peripheral clock in PMC for US0 +//*---------------------------------------------------------------------------- +__inline void AT91F_US0_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_US0)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US0_CfgPIO +//* \brief Configure PIO controllers to drive US0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_US0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA0_RXD0 ) | + ((unsigned int) AT91C_PA4_CTS0 ) | + ((unsigned int) AT91C_PA3_RTS0 ) | + ((unsigned int) AT91C_PA2_SCK0 ) | + ((unsigned int) AT91C_PA1_TXD0 ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI1_CfgPMC +//* \brief Enable Peripheral clock in PMC for SPI1 +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI1_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SPI1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI1_CfgPIO +//* \brief Configure PIO controllers to drive SPI1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PB16_NPCS13 ) | + ((unsigned int) AT91C_PB10_NPCS11 ) | + ((unsigned int) AT91C_PB11_NPCS12 )); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA4_NPCS13 ) | + ((unsigned int) AT91C_PA29_NPCS13 ) | + ((unsigned int) AT91C_PA21_NPCS10 ) | + ((unsigned int) AT91C_PA22_SPCK1 ) | + ((unsigned int) AT91C_PA25_NPCS11 ) | + ((unsigned int) AT91C_PA2_NPCS11 ) | + ((unsigned int) AT91C_PA24_MISO1 ) | + ((unsigned int) AT91C_PA3_NPCS12 ) | + ((unsigned int) AT91C_PA26_NPCS12 ) | + ((unsigned int) AT91C_PA23_MOSI1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI0_CfgPMC +//* \brief Enable Peripheral clock in PMC for SPI0 +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI0_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SPI0)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI0_CfgPIO +//* \brief Configure PIO controllers to drive SPI0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PB13_NPCS01 ) | + ((unsigned int) AT91C_PB17_NPCS03 ) | + ((unsigned int) AT91C_PB14_NPCS02 )); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA16_MISO0 ) | + ((unsigned int) AT91C_PA13_NPCS01 ) | + ((unsigned int) AT91C_PA15_NPCS03 ) | + ((unsigned int) AT91C_PA17_MOSI0 ) | + ((unsigned int) AT91C_PA18_SPCK0 ) | + ((unsigned int) AT91C_PA14_NPCS02 ) | + ((unsigned int) AT91C_PA12_NPCS00 ), // Peripheral A + ((unsigned int) AT91C_PA7_NPCS01 ) | + ((unsigned int) AT91C_PA9_NPCS03 ) | + ((unsigned int) AT91C_PA8_NPCS02 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITC_CfgPMC +//* \brief Enable Peripheral clock in PMC for PITC +//*---------------------------------------------------------------------------- +__inline void AT91F_PITC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_CfgPMC +//* \brief Enable Peripheral clock in PMC for AIC +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_FIQ) | + ((unsigned int) 1 << AT91C_ID_IRQ0) | + ((unsigned int) 1 << AT91C_ID_IRQ1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_CfgPIO +//* \brief Configure PIO controllers to drive AIC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA30_IRQ0 ) | + ((unsigned int) AT91C_PA29_FIQ ), // Peripheral A + ((unsigned int) AT91C_PA14_IRQ1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_CfgPMC +//* \brief Enable Peripheral clock in PMC for AES +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_AES)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_CfgPMC +//* \brief Enable Peripheral clock in PMC for TWI +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TWI)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_CfgPIO +//* \brief Configure PIO controllers to drive TWI signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA11_TWCK ) | + ((unsigned int) AT91C_PA10_TWD ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgPMC +//* \brief Enable Peripheral clock in PMC for ADC +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_ADC)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgPIO +//* \brief Configure PIO controllers to drive ADC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PB18_ADTRG )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH3_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH3 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH3_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB22_PWM3 ), // Peripheral A + ((unsigned int) AT91C_PB30_PWM3 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH2_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH2 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH2_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB21_PWM2 ), // Peripheral A + ((unsigned int) AT91C_PB29_PWM2 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH1_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB20_PWM1 ), // Peripheral A + ((unsigned int) AT91C_PB28_PWM1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH0_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB19_PWM0 ), // Peripheral A + ((unsigned int) AT91C_PB27_PWM0 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RTTC_CfgPMC +//* \brief Enable Peripheral clock in PMC for RTTC +//*---------------------------------------------------------------------------- +__inline void AT91F_RTTC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_CfgPMC +//* \brief Enable Peripheral clock in PMC for UDP +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_UDP)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_CfgPMC +//* \brief Enable Peripheral clock in PMC for TDES +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TDES)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_EMAC_CfgPMC +//* \brief Enable Peripheral clock in PMC for EMAC +//*---------------------------------------------------------------------------- +__inline void AT91F_EMAC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_EMAC)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_EMAC_CfgPIO +//* \brief Configure PIO controllers to drive EMAC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_EMAC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB2_ETX0 ) | + ((unsigned int) AT91C_PB12_ETXER ) | + ((unsigned int) AT91C_PB16_ECOL ) | + ((unsigned int) AT91C_PB11_ETX3 ) | + ((unsigned int) AT91C_PB6_ERX1 ) | + ((unsigned int) AT91C_PB15_ERXDV ) | + ((unsigned int) AT91C_PB13_ERX2 ) | + ((unsigned int) AT91C_PB3_ETX1 ) | + ((unsigned int) AT91C_PB8_EMDC ) | + ((unsigned int) AT91C_PB5_ERX0 ) | + //((unsigned int) AT91C_PB18_EF100 ) | + ((unsigned int) AT91C_PB14_ERX3 ) | + ((unsigned int) AT91C_PB4_ECRS_ECRSDV) | + ((unsigned int) AT91C_PB1_ETXEN ) | + ((unsigned int) AT91C_PB10_ETX2 ) | + ((unsigned int) AT91C_PB0_ETXCK_EREFCK) | + ((unsigned int) AT91C_PB9_EMDIO ) | + ((unsigned int) AT91C_PB7_ERXER ) | + ((unsigned int) AT91C_PB17_ERXCK ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC0_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC0 +//*---------------------------------------------------------------------------- +__inline void AT91F_TC0_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC0)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC0_CfgPIO +//* \brief Configure PIO controllers to drive TC0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TC0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB23_TIOA0 ) | + ((unsigned int) AT91C_PB24_TIOB0 ), // Peripheral A + ((unsigned int) AT91C_PB12_TCLK0 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC1_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC1 +//*---------------------------------------------------------------------------- +__inline void AT91F_TC1_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC1_CfgPIO +//* \brief Configure PIO controllers to drive TC1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TC1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB25_TIOA1 ) | + ((unsigned int) AT91C_PB26_TIOB1 ), // Peripheral A + ((unsigned int) AT91C_PB19_TCLK1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC2_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC2 +//*---------------------------------------------------------------------------- +__inline void AT91F_TC2_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC2)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC2_CfgPIO +//* \brief Configure PIO controllers to drive TC2 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TC2_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB28_TIOB2 ) | + ((unsigned int) AT91C_PB27_TIOA2 ), // Peripheral A + 0); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA15_TCLK2 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_CfgPMC +//* \brief Enable Peripheral clock in PMC for MC +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIOA_CfgPMC +//* \brief Enable Peripheral clock in PMC for PIOA +//*---------------------------------------------------------------------------- +__inline void AT91F_PIOA_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_PIOA)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIOB_CfgPMC +//* \brief Enable Peripheral clock in PMC for PIOB +//*---------------------------------------------------------------------------- +__inline void AT91F_PIOB_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_PIOB)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgPMC +//* \brief Enable Peripheral clock in PMC for CAN +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_CAN)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgPIO +//* \brief Configure PIO controllers to drive CAN signals +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA20_CANTX ) | + ((unsigned int) AT91C_PA19_CANRX ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CfgPMC +//* \brief Enable Peripheral clock in PMC for PWMC +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_PWMC)); +} + +#endif // lib_AT91SAM7X256_H diff --git a/20080212/Source/portable/GCC/ARM7_AT91SAM7S/port.c b/20080212/Source/portable/GCC/ARM7_AT91SAM7S/port.c new file mode 100644 index 000000000..5338999ce --- /dev/null +++ b/20080212/Source/portable/GCC/ARM7_AT91SAM7S/port.c @@ -0,0 +1,232 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the ARM7 port. + * + * Components that can be compiled to either ARM or THUMB mode are + * contained in this file. The ISR routines, which can only be compiled + * to ARM mode are contained in portISR.c. + *----------------------------------------------------------*/ + +/* + Changes from V2.5.2 + + + ulCriticalNesting is now saved as part of the task context, as is + therefore added to the initial task stack during pxPortInitialiseStack. +*/ + + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Processor constants. */ +#include "AT91SAM7X256.h" + +/* Constants required to setup the task context. */ +#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( portSTACK_TYPE ) 0x20 ) +#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 ) +#define portNO_CRITICAL_SECTION_NESTING ( ( portSTACK_TYPE ) 0 ) + +/* Constants required to setup the tick ISR. */ +#define portENABLE_TIMER ( ( unsigned portCHAR ) 0x01 ) +#define portPRESCALE_VALUE 0x00 +#define portINTERRUPT_ON_MATCH ( ( unsigned portLONG ) 0x01 ) +#define portRESET_COUNT_ON_MATCH ( ( unsigned portLONG ) 0x02 ) + +/* Constants required to setup the PIT. */ +#define portPIT_CLOCK_DIVISOR ( ( unsigned portLONG ) 16 ) +#define portPIT_COUNTER_VALUE ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_RATE_MS ) + +#define portINT_LEVEL_SENSITIVE 0 +#define portPIT_ENABLE ( ( unsigned portSHORT ) 0x1 << 24 ) +#define portPIT_INT_ENABLE ( ( unsigned portSHORT ) 0x1 << 25 ) +/*-----------------------------------------------------------*/ + +/* Setup the timer to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/* + * The scheduler can only be started from ARM mode, so + * vPortISRStartFirstSTask() is defined in portISR.c. + */ +extern void vPortISRStartFirstTask( void ); + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ +portSTACK_TYPE *pxOriginalTOS; + + pxOriginalTOS = pxTopOfStack; + + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. */ + + /* First on the stack is the return address - which in this case is the + start of the task. The offset is added to make the return address appear + as it would within an IRQ ISR. */ + *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( portSTACK_TYPE ) 0x00000000; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */ + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + R0. */ + *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The last thing onto the stack is the status register, which is set for + system mode, with interrupts enabled. */ + *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR; + + #ifdef THUMB_INTERWORK + { + /* We want the task to start in thumb mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + #endif + + pxTopOfStack--; + + /* Some optimisation levels use the stack differently to others. This + means the interrupt flags cannot always be stored on the stack and will + instead be stored in a variable, which is then saved as part of the + tasks context. */ + *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xPortStartScheduler( void ) +{ + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + vPortISRStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ARM port will require this function as there + is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +/* + * Setup the timer 0 to generate the tick interrupts at the required frequency. + */ +static void prvSetupTimerInterrupt( void ) +{ +AT91PS_PITC pxPIT = AT91C_BASE_PITC; + + /* Setup the AIC for PIT interrupts. The interrupt routine chosen depends + on whether the preemptive or cooperative scheduler is being used. */ + #if configUSE_PREEMPTION == 0 + + extern void ( vNonPreemptiveTick ) ( void ); + AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vNonPreemptiveTick ); + + #else + + extern void ( vPreemptiveTick )( void ); + AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vPreemptiveTick ); + + #endif + + /* Configure the PIT period. */ + pxPIT->PITC_PIMR = portPIT_ENABLE | portPIT_INT_ENABLE | portPIT_COUNTER_VALUE; + + /* Enable the interrupt. Global interrupts are disables at this point so + this is safe. */ + AT91C_BASE_AIC->AIC_IECR = 0x1 << AT91C_ID_SYS; +} +/*-----------------------------------------------------------*/ + + + diff --git a/20080212/Source/portable/GCC/ARM7_AT91SAM7S/portISR.c b/20080212/Source/portable/GCC/ARM7_AT91SAM7S/portISR.c new file mode 100644 index 000000000..84d6e821e --- /dev/null +++ b/20080212/Source/portable/GCC/ARM7_AT91SAM7S/portISR.c @@ -0,0 +1,241 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +/*----------------------------------------------------------- + * Components that can be compiled to either ARM or THUMB mode are + * contained in port.c The ISR routines, which can only be compiled + * to ARM mode, are contained in this file. + *----------------------------------------------------------*/ + +/* + Changes from V3.2.4 + + + The assembler statements are now included in a single asm block rather + than each line having its own asm block. +*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#include "AT91SAM7X256.h" + +/* Constants required to handle interrupts. */ +#define portTIMER_MATCH_ISR_BIT ( ( unsigned portCHAR ) 0x01 ) +#define portCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 ) + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 ) +volatile unsigned portLONG ulCriticalNesting = 9999UL; + +/*-----------------------------------------------------------*/ + +/* ISR to handle manual context switches (from a call to taskYIELD()). */ +void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked)); + +/* + * The scheduler can only be started from ARM mode, hence the inclusion of this + * function here. + */ +void vPortISRStartFirstTask( void ); +/*-----------------------------------------------------------*/ + +void vPortISRStartFirstTask( void ) +{ + /* Simply start the scheduler. This is included here as it can only be + called from ARM mode. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * Called by portYIELD() or taskYIELD() to manually force a context switch. + * + * When a context switch is performed from the task level the saved task + * context is made to look as if it occurred from within the tick ISR. This + * way the same restore context function can be used when restoring the context + * saved from the ISR or that saved from a call to vPortYieldProcessor. + */ +void vPortYieldProcessor( void ) +{ + /* Within an IRQ ISR the link register has an offset from the true return + address, but an SWI ISR does not. Add the offset manually so the same + ISR return code can be used in both cases. */ + asm volatile ( "ADD LR, LR, #4" ); + + /* Perform the context switch. First save the context of the current task. */ + portSAVE_CONTEXT(); + + /* Find the highest priority task that is ready to run. */ + vTaskSwitchContext(); + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * The ISR used for the scheduler tick depends on whether the cooperative or + * the preemptive scheduler is being used. + */ + +#if configUSE_PREEMPTION == 0 + + /* The cooperative scheduler requires a normal IRQ service routine to + simply increment the system tick. */ + void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ"))); + void vNonPreemptiveTick( void ) + { + unsigned portLONG ulDummy; + + /* Increment the tick count - which may wake some tasks but as the + preemptive scheduler is not being used any woken task is not given + processor time no matter what its priority. */ + vTaskIncrementTick(); + + /* Clear the PIT interrupt. */ + ulDummy = AT91C_BASE_PITC->PITC_PIVR; + + /* End the interrupt in the AIC. */ + AT91C_BASE_AIC->AIC_EOICR = ulDummy; + } + +#else + + /* The preemptive scheduler is defined as "naked" as the full context is + saved on entry as part of the context switch. */ + void vPreemptiveTick( void ) __attribute__((naked)); + void vPreemptiveTick( void ) + { + /* Save the context of the current task. */ + portSAVE_CONTEXT(); + + /* Increment the tick count - this may wake a task. */ + vTaskIncrementTick(); + + /* Find the highest priority task that is ready to run. */ + vTaskSwitchContext(); + + /* End the interrupt in the AIC. */ + AT91C_BASE_AIC->AIC_EOICR = AT91C_BASE_PITC->PITC_PIVR;; + + portRESTORE_CONTEXT(); + } + +#endif +/*-----------------------------------------------------------*/ + +/* + * The interrupt management utilities can only be called from ARM mode. When + * THUMB_INTERWORK is defined the utilities are defined as functions here to + * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then + * the utilities are defined as macros in portmacro.h - as per other ports. + */ +void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); +void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); + +void vPortDisableInterruptsFromThumb( void ) +{ + asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0} \n\t" /* Pop R0. */ + "BX R14" ); /* Return back to thumb. */ +} + +void vPortEnableInterruptsFromThumb( void ) +{ + asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0} \n\t" /* Pop R0. */ + "BX R14" ); /* Return back to thumb. */ +} + + +/* The code generated by the GCC compiler uses the stack in different ways at +different optimisation levels. The interrupt flags can therefore not always +be saved to the stack. Instead the critical section nesting level is stored +in a variable, which is then saved as part of the stack context. */ +void vPortEnterCritical( void ) +{ + /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ + asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0}" ); /* Pop R0. */ + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Enable interrupts as per portEXIT_CRITICAL(). */ + asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0}" ); /* Pop R0. */ + } + } +} + diff --git a/20080212/Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h b/20080212/Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h new file mode 100644 index 000000000..a6f67c792 --- /dev/null +++ b/20080212/Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h @@ -0,0 +1,260 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + Changes from V3.2.3 + + + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1. + + Changes from V3.2.4 + + + Removed the use of the %0 parameter within the assembler macros and + replaced them with hard coded registers. This will ensure the + assembler does not select the link register as the temp register as + was occasionally happening previously. + + + The assembler statements are now included in a single asm block rather + than each line having its own asm block. + + Changes from V4.5.0 + + + Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros + and replaced them with portYIELD_FROM_ISR() macro. Application code + should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT() + macros as per the V4.5.1 demo code. +*/ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned portLONG +#define portBASE_TYPE portLONG + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 4 +#define portNOP() asm volatile ( "NOP" ); +/*-----------------------------------------------------------*/ + + +/* Scheduler utilities. */ + +/* + * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR + * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but + * are included here for efficiency. An attempt to call one from + * THUMB mode code will result in a compile time error. + */ + +#define portRESTORE_CONTEXT() \ +{ \ +extern volatile void * volatile pxCurrentTCB; \ +extern volatile unsigned portLONG ulCriticalNesting; \ + \ + /* Set the LR to the task stack. */ \ + asm volatile ( \ + "LDR R0, =pxCurrentTCB \n\t" \ + "LDR R0, [R0] \n\t" \ + "LDR LR, [R0] \n\t" \ + \ + /* The critical nesting depth is the first item on the stack. */ \ + /* Load it into the ulCriticalNesting variable. */ \ + "LDR R0, =ulCriticalNesting \n\t" \ + "LDMFD LR!, {R1} \n\t" \ + "STR R1, [R0] \n\t" \ + \ + /* Get the SPSR from the stack. */ \ + "LDMFD LR!, {R0} \n\t" \ + "MSR SPSR, R0 \n\t" \ + \ + /* Restore all system mode registers for the task. */ \ + "LDMFD LR, {R0-R14}^ \n\t" \ + "NOP \n\t" \ + \ + /* Restore the return address. */ \ + "LDR LR, [LR, #+60] \n\t" \ + \ + /* And return - correcting the offset in the LR to obtain the */ \ + /* correct address. */ \ + "SUBS PC, LR, #4 \n\t" \ + ); \ + ( void ) ulCriticalNesting; \ + ( void ) pxCurrentTCB; \ +} +/*-----------------------------------------------------------*/ + +#define portSAVE_CONTEXT() \ +{ \ +extern volatile void * volatile pxCurrentTCB; \ +extern volatile unsigned portLONG ulCriticalNesting; \ + \ + /* Push R0 as we are going to use the register. */ \ + asm volatile ( \ + "STMDB SP!, {R0} \n\t" \ + \ + /* Set R0 to point to the task stack pointer. */ \ + "STMDB SP,{SP}^ \n\t" \ + "NOP \n\t" \ + "SUB SP, SP, #4 \n\t" \ + "LDMIA SP!,{R0} \n\t" \ + \ + /* Push the return address onto the stack. */ \ + "STMDB R0!, {LR} \n\t" \ + \ + /* Now we have saved LR we can use it instead of R0. */ \ + "MOV LR, R0 \n\t" \ + \ + /* Pop R0 so we can save it onto the system mode stack. */ \ + "LDMIA SP!, {R0} \n\t" \ + \ + /* Push all the system mode registers onto the task stack. */ \ + "STMDB LR,{R0-LR}^ \n\t" \ + "NOP \n\t" \ + "SUB LR, LR, #60 \n\t" \ + \ + /* Push the SPSR onto the task stack. */ \ + "MRS R0, SPSR \n\t" \ + "STMDB LR!, {R0} \n\t" \ + \ + "LDR R0, =ulCriticalNesting \n\t" \ + "LDR R0, [R0] \n\t" \ + "STMDB LR!, {R0} \n\t" \ + \ + /* Store the new top of stack for the task. */ \ + "LDR R0, =pxCurrentTCB \n\t" \ + "LDR R0, [R0] \n\t" \ + "STR LR, [R0] \n\t" \ + ); \ + ( void ) ulCriticalNesting; \ + ( void ) pxCurrentTCB; \ +} + + +#define portYIELD_FROM_ISR() vTaskSwitchContext() +#define portYIELD() asm volatile ( "SWI" ) +/*-----------------------------------------------------------*/ + + +/* Critical section management. */ + +/* + * The interrupt management utilities can only be called from ARM mode. When + * THUMB_INTERWORK is defined the utilities are defined as functions in + * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not + * defined then the utilities are defined as macros here - as per other ports. + */ + +#ifdef THUMB_INTERWORK + + extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); + extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); + + #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb() + #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb() + +#else + + #define portDISABLE_INTERRUPTS() \ + asm volatile ( \ + "STMDB SP!, {R0} \n\t" /* Push R0. */ \ + "MRS R0, CPSR \n\t" /* Get CPSR. */ \ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ + "LDMIA SP!, {R0} " ) /* Pop R0. */ + + #define portENABLE_INTERRUPTS() \ + asm volatile ( \ + "STMDB SP!, {R0} \n\t" /* Push R0. */ \ + "MRS R0, CPSR \n\t" /* Get CPSR. */ \ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ + "LDMIA SP!, {R0} " ) /* Pop R0. */ + +#endif /* THUMB_INTERWORK */ + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/20080212/Source/portable/GCC/ARM7_LPC2000/port.c b/20080212/Source/portable/GCC/ARM7_LPC2000/port.c new file mode 100644 index 000000000..d147064b6 --- /dev/null +++ b/20080212/Source/portable/GCC/ARM7_LPC2000/port.c @@ -0,0 +1,246 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the ARM7 port. + * + * Components that can be compiled to either ARM or THUMB mode are + * contained in this file. The ISR routines, which can only be compiled + * to ARM mode are contained in portISR.c. + *----------------------------------------------------------*/ + +/* + Changes from V2.5.2 + + + ulCriticalNesting is now saved as part of the task context, as is + therefore added to the initial task stack during pxPortInitialiseStack. + + Changes from V3.2.2 + + + Bug fix - The prescale value for the timer setup is now written to T0_PR + instead of T0_PC. This bug would have had no effect unless a prescale + value was actually used. +*/ + + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to setup the task context. */ +#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( portSTACK_TYPE ) 0x20 ) +#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 ) +#define portNO_CRITICAL_SECTION_NESTING ( ( portSTACK_TYPE ) 0 ) + +/* Constants required to setup the tick ISR. */ +#define portENABLE_TIMER ( ( unsigned portCHAR ) 0x01 ) +#define portPRESCALE_VALUE 0x00 +#define portINTERRUPT_ON_MATCH ( ( unsigned portLONG ) 0x01 ) +#define portRESET_COUNT_ON_MATCH ( ( unsigned portLONG ) 0x02 ) + +/* Constants required to setup the VIC for the tick ISR. */ +#define portTIMER_VIC_CHANNEL ( ( unsigned portLONG ) 0x0004 ) +#define portTIMER_VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x0010 ) +#define portTIMER_VIC_ENABLE ( ( unsigned portLONG ) 0x0020 ) + +/*-----------------------------------------------------------*/ + +/* Setup the timer to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/* + * The scheduler can only be started from ARM mode, so + * vPortISRStartFirstSTask() is defined in portISR.c. + */ +extern void vPortISRStartFirstTask( void ); + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ +portSTACK_TYPE *pxOriginalTOS; + + pxOriginalTOS = pxTopOfStack; + + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. */ + + /* First on the stack is the return address - which in this case is the + start of the task. The offset is added to make the return address appear + as it would within an IRQ ISR. */ + *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */ + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + R0. */ + *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The last thing onto the stack is the status register, which is set for + system mode, with interrupts enabled. */ + *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR; + + #ifdef THUMB_INTERWORK + { + /* We want the task to start in thumb mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + #endif + + pxTopOfStack--; + + /* Some optimisation levels use the stack differently to others. This + means the interrupt flags cannot always be stored on the stack and will + instead be stored in a variable, which is then saved as part of the + tasks context. */ + *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xPortStartScheduler( void ) +{ + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + vPortISRStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ARM port will require this function as there + is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +/* + * Setup the timer 0 to generate the tick interrupts at the required frequency. + */ +static void prvSetupTimerInterrupt( void ) +{ +unsigned portLONG ulCompareMatch; +extern void ( vTickISR )( void ); + + /* A 1ms tick does not require the use of the timer prescale. This is + defaulted to zero but can be used if necessary. */ + T0_PR = portPRESCALE_VALUE; + + /* Calculate the match value required for our wanted tick rate. */ + ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ; + + /* Protect against divide by zero. Using an if() statement still results + in a warning - hence the #if. */ + #if portPRESCALE_VALUE != 0 + { + ulCompareMatch /= ( portPRESCALE_VALUE + 1 ); + } + #endif + T0_MR0 = ulCompareMatch; + + /* Generate tick with timer 0 compare match. */ + T0_MCR = portRESET_COUNT_ON_MATCH | portINTERRUPT_ON_MATCH; + + /* Setup the VIC for the timer. */ + VICIntSelect &= ~( portTIMER_VIC_CHANNEL_BIT ); + VICIntEnable |= portTIMER_VIC_CHANNEL_BIT; + + /* The ISR installed depends on whether the preemptive or cooperative + scheduler is being used. */ + + VICVectAddr0 = ( portLONG ) vTickISR; + VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE; + + /* Start the timer - interrupts are disabled when this function is called + so it is okay to do this here. */ + T0_TCR = portENABLE_TIMER; +} +/*-----------------------------------------------------------*/ + + + diff --git a/20080212/Source/portable/GCC/ARM7_LPC2000/portISR.c b/20080212/Source/portable/GCC/ARM7_LPC2000/portISR.c new file mode 100644 index 000000000..ce5466039 --- /dev/null +++ b/20080212/Source/portable/GCC/ARM7_LPC2000/portISR.c @@ -0,0 +1,228 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +/*----------------------------------------------------------- + * Components that can be compiled to either ARM or THUMB mode are + * contained in port.c The ISR routines, which can only be compiled + * to ARM mode, are contained in this file. + *----------------------------------------------------------*/ + +/* + Changes from V2.5.2 + + + The critical section management functions have been changed. These no + longer modify the stack and are safe to use at all optimisation levels. + The functions are now also the same for both ARM and THUMB modes. + + Changes from V2.6.0 + + + Removed the 'static' from the definition of vNonPreemptiveTick() to + allow the demo to link when using the cooperative scheduler. + + Changes from V3.2.4 + + + The assembler statements are now included in a single asm block rather + than each line having its own asm block. +*/ + + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to handle interrupts. */ +#define portTIMER_MATCH_ISR_BIT ( ( unsigned portCHAR ) 0x01 ) +#define portCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 ) + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 ) +volatile unsigned portLONG ulCriticalNesting = 9999UL; + +/*-----------------------------------------------------------*/ + +/* ISR to handle manual context switches (from a call to taskYIELD()). */ +void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked)); + +/* + * The scheduler can only be started from ARM mode, hence the inclusion of this + * function here. + */ +void vPortISRStartFirstTask( void ); +/*-----------------------------------------------------------*/ + +void vPortISRStartFirstTask( void ) +{ + /* Simply start the scheduler. This is included here as it can only be + called from ARM mode. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * Called by portYIELD() or taskYIELD() to manually force a context switch. + * + * When a context switch is performed from the task level the saved task + * context is made to look as if it occurred from within the tick ISR. This + * way the same restore context function can be used when restoring the context + * saved from the ISR or that saved from a call to vPortYieldProcessor. + */ +void vPortYieldProcessor( void ) +{ + /* Within an IRQ ISR the link register has an offset from the true return + address, but an SWI ISR does not. Add the offset manually so the same + ISR return code can be used in both cases. */ + asm volatile ( "ADD LR, LR, #4" ); + + /* Perform the context switch. First save the context of the current task. */ + portSAVE_CONTEXT(); + + /* Find the highest priority task that is ready to run. */ + vTaskSwitchContext(); + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * The ISR used for the scheduler tick. + */ +void vTickISR( void ) __attribute__((naked)); +void vTickISR( void ) +{ + /* Save the context of the interrupted task. */ + portSAVE_CONTEXT(); + + /* Increment the RTOS tick count, then look for the highest priority + task that is ready to run. */ + vTaskIncrementTick(); + + #if configUSE_PREEMPTION == 1 + vTaskSwitchContext(); + #endif + + /* Ready for the next interrupt. */ + T0_IR = portTIMER_MATCH_ISR_BIT; + VICVectAddr = portCLEAR_VIC_INTERRUPT; + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * The interrupt management utilities can only be called from ARM mode. When + * THUMB_INTERWORK is defined the utilities are defined as functions here to + * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then + * the utilities are defined as macros in portmacro.h - as per other ports. + */ +#ifdef THUMB_INTERWORK + + void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); + void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); + + void vPortDisableInterruptsFromThumb( void ) + { + asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0} \n\t" /* Pop R0. */ + "BX R14" ); /* Return back to thumb. */ + } + + void vPortEnableInterruptsFromThumb( void ) + { + asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0} \n\t" /* Pop R0. */ + "BX R14" ); /* Return back to thumb. */ + } + +#endif /* THUMB_INTERWORK */ + +/* The code generated by the GCC compiler uses the stack in different ways at +different optimisation levels. The interrupt flags can therefore not always +be saved to the stack. Instead the critical section nesting level is stored +in a variable, which is then saved as part of the stack context. */ +void vPortEnterCritical( void ) +{ + /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ + asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0}" ); /* Pop R0. */ + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Enable interrupts as per portEXIT_CRITICAL(). */ + asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0}" ); /* Pop R0. */ + } + } +} diff --git a/20080212/Source/portable/GCC/ARM7_LPC2000/portmacro.h b/20080212/Source/portable/GCC/ARM7_LPC2000/portmacro.h new file mode 100644 index 000000000..a6f67c792 --- /dev/null +++ b/20080212/Source/portable/GCC/ARM7_LPC2000/portmacro.h @@ -0,0 +1,260 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + Changes from V3.2.3 + + + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1. + + Changes from V3.2.4 + + + Removed the use of the %0 parameter within the assembler macros and + replaced them with hard coded registers. This will ensure the + assembler does not select the link register as the temp register as + was occasionally happening previously. + + + The assembler statements are now included in a single asm block rather + than each line having its own asm block. + + Changes from V4.5.0 + + + Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros + and replaced them with portYIELD_FROM_ISR() macro. Application code + should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT() + macros as per the V4.5.1 demo code. +*/ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned portLONG +#define portBASE_TYPE portLONG + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 4 +#define portNOP() asm volatile ( "NOP" ); +/*-----------------------------------------------------------*/ + + +/* Scheduler utilities. */ + +/* + * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR + * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but + * are included here for efficiency. An attempt to call one from + * THUMB mode code will result in a compile time error. + */ + +#define portRESTORE_CONTEXT() \ +{ \ +extern volatile void * volatile pxCurrentTCB; \ +extern volatile unsigned portLONG ulCriticalNesting; \ + \ + /* Set the LR to the task stack. */ \ + asm volatile ( \ + "LDR R0, =pxCurrentTCB \n\t" \ + "LDR R0, [R0] \n\t" \ + "LDR LR, [R0] \n\t" \ + \ + /* The critical nesting depth is the first item on the stack. */ \ + /* Load it into the ulCriticalNesting variable. */ \ + "LDR R0, =ulCriticalNesting \n\t" \ + "LDMFD LR!, {R1} \n\t" \ + "STR R1, [R0] \n\t" \ + \ + /* Get the SPSR from the stack. */ \ + "LDMFD LR!, {R0} \n\t" \ + "MSR SPSR, R0 \n\t" \ + \ + /* Restore all system mode registers for the task. */ \ + "LDMFD LR, {R0-R14}^ \n\t" \ + "NOP \n\t" \ + \ + /* Restore the return address. */ \ + "LDR LR, [LR, #+60] \n\t" \ + \ + /* And return - correcting the offset in the LR to obtain the */ \ + /* correct address. */ \ + "SUBS PC, LR, #4 \n\t" \ + ); \ + ( void ) ulCriticalNesting; \ + ( void ) pxCurrentTCB; \ +} +/*-----------------------------------------------------------*/ + +#define portSAVE_CONTEXT() \ +{ \ +extern volatile void * volatile pxCurrentTCB; \ +extern volatile unsigned portLONG ulCriticalNesting; \ + \ + /* Push R0 as we are going to use the register. */ \ + asm volatile ( \ + "STMDB SP!, {R0} \n\t" \ + \ + /* Set R0 to point to the task stack pointer. */ \ + "STMDB SP,{SP}^ \n\t" \ + "NOP \n\t" \ + "SUB SP, SP, #4 \n\t" \ + "LDMIA SP!,{R0} \n\t" \ + \ + /* Push the return address onto the stack. */ \ + "STMDB R0!, {LR} \n\t" \ + \ + /* Now we have saved LR we can use it instead of R0. */ \ + "MOV LR, R0 \n\t" \ + \ + /* Pop R0 so we can save it onto the system mode stack. */ \ + "LDMIA SP!, {R0} \n\t" \ + \ + /* Push all the system mode registers onto the task stack. */ \ + "STMDB LR,{R0-LR}^ \n\t" \ + "NOP \n\t" \ + "SUB LR, LR, #60 \n\t" \ + \ + /* Push the SPSR onto the task stack. */ \ + "MRS R0, SPSR \n\t" \ + "STMDB LR!, {R0} \n\t" \ + \ + "LDR R0, =ulCriticalNesting \n\t" \ + "LDR R0, [R0] \n\t" \ + "STMDB LR!, {R0} \n\t" \ + \ + /* Store the new top of stack for the task. */ \ + "LDR R0, =pxCurrentTCB \n\t" \ + "LDR R0, [R0] \n\t" \ + "STR LR, [R0] \n\t" \ + ); \ + ( void ) ulCriticalNesting; \ + ( void ) pxCurrentTCB; \ +} + + +#define portYIELD_FROM_ISR() vTaskSwitchContext() +#define portYIELD() asm volatile ( "SWI" ) +/*-----------------------------------------------------------*/ + + +/* Critical section management. */ + +/* + * The interrupt management utilities can only be called from ARM mode. When + * THUMB_INTERWORK is defined the utilities are defined as functions in + * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not + * defined then the utilities are defined as macros here - as per other ports. + */ + +#ifdef THUMB_INTERWORK + + extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); + extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); + + #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb() + #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb() + +#else + + #define portDISABLE_INTERRUPTS() \ + asm volatile ( \ + "STMDB SP!, {R0} \n\t" /* Push R0. */ \ + "MRS R0, CPSR \n\t" /* Get CPSR. */ \ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ + "LDMIA SP!, {R0} " ) /* Pop R0. */ + + #define portENABLE_INTERRUPTS() \ + asm volatile ( \ + "STMDB SP!, {R0} \n\t" /* Push R0. */ \ + "MRS R0, CPSR \n\t" /* Get CPSR. */ \ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ + "LDMIA SP!, {R0} " ) /* Pop R0. */ + +#endif /* THUMB_INTERWORK */ + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/20080212/Source/portable/GCC/ARM7_LPC23xx/port.c b/20080212/Source/portable/GCC/ARM7_LPC23xx/port.c new file mode 100644 index 000000000..6af0eeea1 --- /dev/null +++ b/20080212/Source/portable/GCC/ARM7_LPC23xx/port.c @@ -0,0 +1,235 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the ARM7 port. + * + * Components that can be compiled to either ARM or THUMB mode are + * contained in this file. The ISR routines, which can only be compiled + * to ARM mode are contained in portISR.c. + *----------------------------------------------------------*/ + + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to setup the task context. */ +#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( portSTACK_TYPE ) 0x20 ) +#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 ) +#define portNO_CRITICAL_SECTION_NESTING ( ( portSTACK_TYPE ) 0 ) + +/* Constants required to setup the tick ISR. */ +#define portENABLE_TIMER ( ( unsigned portCHAR ) 0x01 ) +#define portPRESCALE_VALUE 0x00 +#define portINTERRUPT_ON_MATCH ( ( unsigned portLONG ) 0x01 ) +#define portRESET_COUNT_ON_MATCH ( ( unsigned portLONG ) 0x02 ) + +/* Constants required to setup the VIC for the tick ISR. */ +#define portTIMER_VIC_CHANNEL ( ( unsigned portLONG ) 0x0004 ) +#define portTIMER_VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x0010 ) +#define portTIMER_VIC_ENABLE ( ( unsigned portLONG ) 0x0020 ) + +/*-----------------------------------------------------------*/ + +/* Setup the timer to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/* + * The scheduler can only be started from ARM mode, so + * vPortISRStartFirstSTask() is defined in portISR.c. + */ +extern void vPortISRStartFirstTask( void ); + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ +portSTACK_TYPE *pxOriginalTOS; + + pxOriginalTOS = pxTopOfStack; + + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. */ + + /* First on the stack is the return address - which in this case is the + start of the task. The offset is added to make the return address appear + as it would within an IRQ ISR. */ + *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( portSTACK_TYPE ) 0x00000000; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */ + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + R0. */ + *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The last thing onto the stack is the status register, which is set for + system mode, with interrupts enabled. */ + *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR; + + #ifdef THUMB_INTERWORK + { + /* We want the task to start in thumb mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + #endif + + pxTopOfStack--; + + /* Some optimisation levels use the stack differently to others. This + means the interrupt flags cannot always be stored on the stack and will + instead be stored in a variable, which is then saved as part of the + tasks context. */ + *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xPortStartScheduler( void ) +{ + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + vPortISRStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ARM port will require this function as there + is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +/* + * Setup the timer 0 to generate the tick interrupts at the required frequency. + */ +static void prvSetupTimerInterrupt( void ) +{ +unsigned portLONG ulCompareMatch; + + PCLKSEL0 = (PCLKSEL0 & (~(0x3<<2))) | (0x01 << 2); + T0TCR = 2; /* Stop and reset the timer */ + T0CTCR = 0; /* Timer mode */ + + /* A 1ms tick does not require the use of the timer prescale. This is + defaulted to zero but can be used if necessary. */ + T0PR = portPRESCALE_VALUE; + + /* Calculate the match value required for our wanted tick rate. */ + ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ; + + /* Protect against divide by zero. Using an if() statement still results + in a warning - hence the #if. */ + #if portPRESCALE_VALUE != 0 + { + ulCompareMatch /= ( portPRESCALE_VALUE + 1 ); + } + #endif + T0MR1 = ulCompareMatch; + + /* Generate tick with timer 0 compare match. */ + T0MCR = (3 << 3); /* Reset timer on match and generate interrupt */ + + /* Setup the VIC for the timer. */ + VICIntEnable = 0x00000010; + + /* The ISR installed depends on whether the preemptive or cooperative + scheduler is being used. */ + #if configUSE_PREEMPTION == 1 + { + extern void ( vPreemptiveTick )( void ); + VICVectAddr4 = ( portLONG ) vPreemptiveTick; + } + #else + { + extern void ( vNonPreemptiveTick )( void ); + VICVectAddr4 = ( portLONG ) vNonPreemptiveTick; + } + #endif + + VICVectCntl4 = 1; + + /* Start the timer - interrupts are disabled when this function is called + so it is okay to do this here. */ + T0TCR = portENABLE_TIMER; +} +/*-----------------------------------------------------------*/ + + + diff --git a/20080212/Source/portable/GCC/ARM7_LPC23xx/portISR.c b/20080212/Source/portable/GCC/ARM7_LPC23xx/portISR.c new file mode 100644 index 000000000..779c5d9c9 --- /dev/null +++ b/20080212/Source/portable/GCC/ARM7_LPC23xx/portISR.c @@ -0,0 +1,217 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + + +/*----------------------------------------------------------- + * Components that can be compiled to either ARM or THUMB mode are + * contained in port.c The ISR routines, which can only be compiled + * to ARM mode, are contained in this file. + *----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to handle interrupts. */ +#define portTIMER_MATCH_ISR_BIT ( ( unsigned portCHAR ) 0x01 ) +#define portCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 ) + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 ) +volatile unsigned portLONG ulCriticalNesting = 9999UL; + +/*-----------------------------------------------------------*/ + +/* ISR to handle manual context switches (from a call to taskYIELD()). */ +void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked)); + +/* + * The scheduler can only be started from ARM mode, hence the inclusion of this + * function here. + */ +void vPortISRStartFirstTask( void ); +/*-----------------------------------------------------------*/ + +void vPortISRStartFirstTask( void ) +{ + /* Simply start the scheduler. This is included here as it can only be + called from ARM mode. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * Called by portYIELD() or taskYIELD() to manually force a context switch. + * + * When a context switch is performed from the task level the saved task + * context is made to look as if it occurred from within the tick ISR. This + * way the same restore context function can be used when restoring the context + * saved from the ISR or that saved from a call to vPortYieldProcessor. + */ +void vPortYieldProcessor( void ) +{ + /* Within an IRQ ISR the link register has an offset from the true return + address, but an SWI ISR does not. Add the offset manually so the same + ISR return code can be used in both cases. */ + asm volatile ( "ADD LR, LR, #4" ); + + /* Perform the context switch. First save the context of the current task. */ + portSAVE_CONTEXT(); + + /* Find the highest priority task that is ready to run. */ + vTaskSwitchContext(); + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * The ISR used for the scheduler tick depends on whether the cooperative or + * the preemptive scheduler is being used. + */ + + +#if configUSE_PREEMPTION == 0 + + /* The cooperative scheduler requires a normal IRQ service routine to + simply increment the system tick. */ + void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ"))); + void vNonPreemptiveTick( void ) + { + vTaskIncrementTick(); + T0IR = 2; + VICVectAddr = portCLEAR_VIC_INTERRUPT; + } + +#else + + /* The preemptive scheduler is defined as "naked" as the full context is + saved on entry as part of the context switch. */ + void vPreemptiveTick( void ) __attribute__((naked)); + void vPreemptiveTick( void ) + { + /* Save the context of the interrupted task. */ + portSAVE_CONTEXT(); + + /* Increment the RTOS tick count, then look for the highest priority + task that is ready to run. */ + vTaskIncrementTick(); + vTaskSwitchContext(); + + /* Ready for the next interrupt. */ + T0IR = 2; + VICVectAddr = portCLEAR_VIC_INTERRUPT; + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT(); + } + +#endif +/*-----------------------------------------------------------*/ + +/* + * The interrupt management utilities can only be called from ARM mode. When + * THUMB_INTERWORK is defined the utilities are defined as functions here to + * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then + * the utilities are defined as macros in portmacro.h - as per other ports. + */ +#ifdef THUMB_INTERWORK + + void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); + void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); + + void vPortDisableInterruptsFromThumb( void ) + { + asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0} \n\t" /* Pop R0. */ + "BX R14" ); /* Return back to thumb. */ + } + + void vPortEnableInterruptsFromThumb( void ) + { + asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0} \n\t" /* Pop R0. */ + "BX R14" ); /* Return back to thumb. */ + } + +#endif /* THUMB_INTERWORK */ + +/* The code generated by the GCC compiler uses the stack in different ways at +different optimisation levels. The interrupt flags can therefore not always +be saved to the stack. Instead the critical section nesting level is stored +in a variable, which is then saved as part of the stack context. */ +void vPortEnterCritical( void ) +{ + /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ + asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0}" ); /* Pop R0. */ + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Enable interrupts as per portEXIT_CRITICAL(). */ + asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0}" ); /* Pop R0. */ + } + } +} diff --git a/20080212/Source/portable/GCC/ARM7_LPC23xx/portmacro.h b/20080212/Source/portable/GCC/ARM7_LPC23xx/portmacro.h new file mode 100644 index 000000000..a5e0bd2f5 --- /dev/null +++ b/20080212/Source/portable/GCC/ARM7_LPC23xx/portmacro.h @@ -0,0 +1,250 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + *************************************************************************** +*/ + +/* + Changes from V3.2.3 + + + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1. + + Changes from V3.2.4 + + + Removed the use of the %0 parameter within the assembler macros and + replaced them with hard coded registers. This will ensure the + assembler does not select the link register as the temp register as + was occasionally happening previously. + + + The assembler statements are now included in a single asm block rather + than each line having its own asm block. + + Changes from V4.5.0 + + + Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros + and replaced them with portYIELD_FROM_ISR() macro. Application code + should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT() + macros as per the V4.5.1 demo code. +*/ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned portLONG +#define portBASE_TYPE portLONG + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 4 +#define portNOP() asm volatile ( "NOP" ); +/*-----------------------------------------------------------*/ + + +/* Scheduler utilities. */ + +/* + * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR + * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but + * are included here for efficiency. An attempt to call one from + * THUMB mode code will result in a compile time error. + */ + +#define portRESTORE_CONTEXT() \ +{ \ +extern volatile void * volatile pxCurrentTCB; \ +extern volatile unsigned portLONG ulCriticalNesting; \ + \ + /* Set the LR to the task stack. */ \ + asm volatile ( \ + "LDR R0, =pxCurrentTCB \n\t" \ + "LDR R0, [R0] \n\t" \ + "LDR LR, [R0] \n\t" \ + \ + /* The critical nesting depth is the first item on the stack. */ \ + /* Load it into the ulCriticalNesting variable. */ \ + "LDR R0, =ulCriticalNesting \n\t" \ + "LDMFD LR!, {R1} \n\t" \ + "STR R1, [R0] \n\t" \ + \ + /* Get the SPSR from the stack. */ \ + "LDMFD LR!, {R0} \n\t" \ + "MSR SPSR, R0 \n\t" \ + \ + /* Restore all system mode registers for the task. */ \ + "LDMFD LR, {R0-R14}^ \n\t" \ + "NOP \n\t" \ + \ + /* Restore the return address. */ \ + "LDR LR, [LR, #+60] \n\t" \ + \ + /* And return - correcting the offset in the LR to obtain the */ \ + /* correct address. */ \ + "SUBS PC, LR, #4 \n\t" \ + ); \ + ( void ) ulCriticalNesting; \ + ( void ) pxCurrentTCB; \ +} +/*-----------------------------------------------------------*/ + +#define portSAVE_CONTEXT() \ +{ \ +extern volatile void * volatile pxCurrentTCB; \ +extern volatile unsigned portLONG ulCriticalNesting; \ + \ + /* Push R0 as we are going to use the register. */ \ + asm volatile ( \ + "STMDB SP!, {R0} \n\t" \ + \ + /* Set R0 to point to the task stack pointer. */ \ + "STMDB SP,{SP}^ \n\t" \ + "NOP \n\t" \ + "SUB SP, SP, #4 \n\t" \ + "LDMIA SP!,{R0} \n\t" \ + \ + /* Push the return address onto the stack. */ \ + "STMDB R0!, {LR} \n\t" \ + \ + /* Now we have saved LR we can use it instead of R0. */ \ + "MOV LR, R0 \n\t" \ + \ + /* Pop R0 so we can save it onto the system mode stack. */ \ + "LDMIA SP!, {R0} \n\t" \ + \ + /* Push all the system mode registers onto the task stack. */ \ + "STMDB LR,{R0-LR}^ \n\t" \ + "NOP \n\t" \ + "SUB LR, LR, #60 \n\t" \ + \ + /* Push the SPSR onto the task stack. */ \ + "MRS R0, SPSR \n\t" \ + "STMDB LR!, {R0} \n\t" \ + \ + "LDR R0, =ulCriticalNesting \n\t" \ + "LDR R0, [R0] \n\t" \ + "STMDB LR!, {R0} \n\t" \ + \ + /* Store the new top of stack for the task. */ \ + "LDR R0, =pxCurrentTCB \n\t" \ + "LDR R0, [R0] \n\t" \ + "STR LR, [R0] \n\t" \ + ); \ + ( void ) ulCriticalNesting; \ + ( void ) pxCurrentTCB; \ +} + + +#define portYIELD_FROM_ISR() vTaskSwitchContext() +#define portYIELD() asm volatile ( "SWI" ) +/*-----------------------------------------------------------*/ + + +/* Critical section management. */ + +/* + * The interrupt management utilities can only be called from ARM mode. When + * THUMB_INTERWORK is defined the utilities are defined as functions in + * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not + * defined then the utilities are defined as macros here - as per other ports. + */ + +#ifdef THUMB_INTERWORK + + extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); + extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); + + #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb() + #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb() + +#else + + #define portDISABLE_INTERRUPTS() \ + asm volatile ( \ + "STMDB SP!, {R0} \n\t" /* Push R0. */ \ + "MRS R0, CPSR \n\t" /* Get CPSR. */ \ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ + "LDMIA SP!, {R0} " ) /* Pop R0. */ + + #define portENABLE_INTERRUPTS() \ + asm volatile ( \ + "STMDB SP!, {R0} \n\t" /* Push R0. */ \ + "MRS R0, CPSR \n\t" /* Get CPSR. */ \ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ + "LDMIA SP!, {R0} " ) /* Pop R0. */ + +#endif /* THUMB_INTERWORK */ + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/20080212/Source/portable/GCC/ARM_CM3/port.c b/20080212/Source/portable/GCC/ARM_CM3/port.c new file mode 100644 index 000000000..415bf3c02 --- /dev/null +++ b/20080212/Source/portable/GCC/ARM_CM3/port.c @@ -0,0 +1,330 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + Changes between V4.0.0 and V4.0.1 + + + Reduced the code used to setup the initial stack frame. + + The kernel no longer has to install or handle the fault interrupt. + + Change from V4.4.0: + + + Introduced usage of configKERNEL_INTERRUPT_PRIORITY macro to set the + interrupt priority used by the kernel. +*/ + + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the ARM CM3 port. + *----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is +defined. The value should also ensure backward compatibility. +FreeRTOS.org versions prior to V4.4.0 did not include this definition. */ +#ifndef configKERNEL_INTERRUPT_PRIORITY + #define configKERNEL_INTERRUPT_PRIORITY 255 +#endif + +/* Constants required to manipulate the NVIC. */ +#define portNVIC_SYSTICK_CTRL ( ( volatile unsigned portLONG *) 0xe000e010 ) +#define portNVIC_SYSTICK_LOAD ( ( volatile unsigned portLONG *) 0xe000e014 ) +#define portNVIC_INT_CTRL ( ( volatile unsigned portLONG *) 0xe000ed04 ) +#define portNVIC_SYSPRI2 ( ( volatile unsigned portLONG *) 0xe000ed20 ) +#define portNVIC_SYSTICK_CLK 0x00000004 +#define portNVIC_SYSTICK_INT 0x00000002 +#define portNVIC_SYSTICK_ENABLE 0x00000001 +#define portNVIC_PENDSVSET 0x10000000 +#define portNVIC_PENDSV_PRI ( ( ( unsigned portLONG ) configKERNEL_INTERRUPT_PRIORITY ) << 16 ) +#define portNVIC_SYSTICK_PRI ( ( ( unsigned portLONG ) configKERNEL_INTERRUPT_PRIORITY ) << 24 ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000 ) + +/* The priority used by the kernel is assigned to a variable to make access +from inline assembler easier. */ +const unsigned portLONG ulKernelPriority = configKERNEL_INTERRUPT_PRIORITY; + +/* Each task maintains its own interrupt status in the critical nesting +variable. */ +unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa; + +/* + * Setup the timer to generate the tick interrupts. + */ +static void prvSetupTimerInterrupt( void ); + +/* + * Exception handlers. + */ +void xPortPendSVHandler( void ) __attribute__ (( naked )); +void xPortSysTickHandler( void ) __attribute__ (( naked )); + +/* + * Set the MSP/PSP to a known value. + */ +void prvSetMSP( unsigned long ulValue ) __attribute__ (( naked )); +void prvSetPSP( unsigned long ulValue ) __attribute__ (( naked )); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ + /* Simulate the stack frame as it would be created by a context switch + interrupt. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = 0; /* LR */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ + pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ + *pxTopOfStack = 0x00000000; /* uxCriticalNesting. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +void prvSetPSP( unsigned long ulValue ) +{ + asm volatile( "msr psp, r0" ); + asm volatile( "bx lr" ); +} +/*-----------------------------------------------------------*/ + +void prvSetMSP( unsigned long ulValue ) +{ + asm volatile( "msr msp, r0" ); + asm volatile( "bx lr" ); +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +portBASE_TYPE xPortStartScheduler( void ) +{ + /* Make PendSV, CallSV and SysTick the same priroity as the kernel. */ + *(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI; + *(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI; + + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + prvSetPSP( 0 ); + prvSetMSP( *((unsigned portLONG *) 0 ) ); + *(portNVIC_INT_CTRL) |= portNVIC_PENDSVSET; + + /* Enable interrupts */ + portENABLE_INTERRUPTS(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the CM3 port will require this function as there + is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +void vPortYieldFromISR( void ) +{ + /* Set a PendSV to request a context switch. */ + *(portNVIC_INT_CTRL) |= portNVIC_PENDSVSET; + + /* This function is also called in response to a Yield(), so we want + the yield to occur immediately. */ + portENABLE_INTERRUPTS(); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + uxCriticalNesting--; + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void xPortPendSVHandler( void ) +{ + /* Start first task if the stack has not yet been setup. */ + __asm volatile + ( + " mrs r0, psp \n" + " cbz r0, no_save \n" + " \n" /* Save the context into the TCB. */ + " stmdb r0!, {r4-r11} \n" + " sub r0, #0x04 \n" + " ldr r1, uxCriticalNestingConst \n" + " ldr r2, pxCurrentTCBConst \n" + " ldr r1, [r1] \n" + " ldr r2, [r2] \n" + " str r1, [r0] \n" + " str r0, [r2] \n" + " \n" + "no_save:\n" + " push {r14} \n" + " bl vPortSwitchContext \n" + " pop {r14} \n" + " \n" /* Restore the context. */ + " ldr r1, pxCurrentTCBConst \n" + " ldr r1, [r1] \n" + " ldr r0, [r1] \n" + " ldmia r0!, {r1, r4-r11} \n" + " ldr r2, uxCriticalNestingConst \n" + " str r1, [r2] \n" + " msr psp, r0 \n" + " orr r14, #0xd \n" + " \n" /* Exit with interrupts in the state required by the task. */ + " cbnz r1, sv_disable_interrupts \n" + " bx r14 \n" + " \n" + "sv_disable_interrupts: \n" + " ldr r1, =ulKernelPriority \n" + " ldr r1, [r1] \n" + " msr basepri, r1 \n" + " bx r14 \n" + " \n" + " .align 2 \n" + "pxCurrentTCBConst: .word pxCurrentTCB \n" + "uxCriticalNestingConst: .word uxCriticalNesting \n" + ); +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + extern void vTaskIncrementTick( void ); + extern void vPortYieldFromISR( void ); + + /* Call the scheduler tick function. */ + __asm volatile + ( + " push {r14} \n" + " bl vPortIncrementTick \n" + " pop {r14}" + ); + + /* If using preemption, also force a context switch. */ + #if configUSE_PREEMPTION == 1 + __asm volatile + ( + " push {r14} \n" + " bl vPortYieldFromISR \n" + " pop {r14}" + ); + #endif + + /* Exit with interrupts in the correct state. */ + __asm volatile + ( + " ldr r2, uxCriticalNestingConst2 \n" + " ldr r2, [r2] \n" + " cbnz r2, tick_disable_interrupts \n" + " bx r14" + ); + + __asm volatile + ( + "tick_disable_interrupts: \n" + " ldr r1, =ulKernelPriority \n" + " ldr r1, [r1] \n" + " msr basepri, r1 \n" + " bx r14 \n" + " \n" + " .align 2 \n" + "uxCriticalNestingConst2: .word uxCriticalNesting" + ); +} +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +void prvSetupTimerInterrupt( void ) +{ + /* Configure SysTick to interrupt at the requested rate. */ + *(portNVIC_SYSTICK_LOAD) = configCPU_CLOCK_HZ / configTICK_RATE_HZ; + *(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE; +} +/*-----------------------------------------------------------*/ + +void vPortSwitchContext( void ) +{ + vPortSetInterruptMask(); + vTaskSwitchContext(); + vPortClearInterruptMask(); +} +/*-----------------------------------------------------------*/ + +void vPortIncrementTick( void ) +{ + vPortSetInterruptMask(); + vTaskIncrementTick(); + vPortClearInterruptMask(); +} + +/*-----------------------------------------------------------*/ + diff --git a/20080212/Source/portable/GCC/ARM_CM3/portmacro.h b/20080212/Source/portable/GCC/ARM_CM3/portmacro.h new file mode 100644 index 000000000..910c5ff2d --- /dev/null +++ b/20080212/Source/portable/GCC/ARM_CM3/portmacro.h @@ -0,0 +1,148 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + Change from V4.4.0: + + + Introduced usage of configKERNEL_INTERRUPT_PRIORITY macro to set the + interrupt priority used by the kernel. +*/ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned portLONG +#define portBASE_TYPE long + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 4 +/*-----------------------------------------------------------*/ + + +/* Scheduler utilities. */ +extern void vPortYieldFromISR( void ); + +#define portYIELD() vPortYieldFromISR() + +#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vPortYieldFromISR() +/*-----------------------------------------------------------*/ + + +/* Critical section management. */ + +#define vPortSetInterruptMask() \ + __asm volatile \ + ( \ + " push { r0 } \n" \ + " ldr r0, =ulKernelPriority \n" \ + " ldr r0, [r0] \n" \ + " msr basepri, r0 \n" \ + " pop { r0 } " \ + ) + +/*-----------------------------------------------------------*/ + +#define vPortClearInterruptMask() \ + __asm volatile \ + ( \ + " push { r0 } \n" \ + " mov r0, #0 \n" \ + " msr basepri, r0 \n" \ + " pop { r0 } " \ + ) + +/*-----------------------------------------------------------*/ + + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#define portDISABLE_INTERRUPTS() vPortSetInterruptMask(); +#define portENABLE_INTERRUPTS() vPortClearInterruptMask(); +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#define inline +#define portNOP() + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/20080212/Source/portable/GCC/ATMega323/port.c b/20080212/Source/portable/GCC/ATMega323/port.c new file mode 100644 index 000000000..9be0b614a --- /dev/null +++ b/20080212/Source/portable/GCC/ATMega323/port.c @@ -0,0 +1,439 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + +Changes from V2.6.0 + + + AVR port - Replaced the inb() and outb() functions with direct memory + access. This allows the port to be built with the 20050414 build of + WinAVR. +*/ + +#include +#include + +#include "FreeRTOS.h" +#include "task.h" + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the AVR port. + *----------------------------------------------------------*/ + +/* Start tasks with interrupts enables. */ +#define portFLAGS_INT_ENABLED ( ( portSTACK_TYPE ) 0x80 ) + +/* Hardware constants for timer 1. */ +#define portCLEAR_COUNTER_ON_MATCH ( ( unsigned portCHAR ) 0x08 ) +#define portPRESCALE_64 ( ( unsigned portCHAR ) 0x03 ) +#define portCLOCK_PRESCALER ( ( unsigned portLONG ) 64 ) +#define portCOMPARE_MATCH_A_INTERRUPT_ENABLE ( ( unsigned portCHAR ) 0x10 ) + +/*-----------------------------------------------------------*/ + +/* We require the address of the pxCurrentTCB variable, but don't want to know +any details of its type. */ +typedef void tskTCB; +extern volatile tskTCB * volatile pxCurrentTCB; + +/*-----------------------------------------------------------*/ + +/* + * Macro to save all the general purpose registers, the save the stack pointer + * into the TCB. + * + * The first thing we do is save the flags then disable interrupts. This is to + * guard our stack against having a context switch interrupt after we have already + * pushed the registers onto the stack - causing the 32 registers to be on the + * stack twice. + * + * r1 is set to zero as the compiler expects it to be thus, however some + * of the math routines make use of R1. + * + * The interrupts will have been disabled during the call to portSAVE_CONTEXT() + * so we need not worry about reading/writing to the stack pointer. + */ + +#define portSAVE_CONTEXT() \ + asm volatile ( "push r0 \n\t" \ + "in r0, __SREG__ \n\t" \ + "cli \n\t" \ + "push r0 \n\t" \ + "push r1 \n\t" \ + "clr r1 \n\t" \ + "push r2 \n\t" \ + "push r3 \n\t" \ + "push r4 \n\t" \ + "push r5 \n\t" \ + "push r6 \n\t" \ + "push r7 \n\t" \ + "push r8 \n\t" \ + "push r9 \n\t" \ + "push r10 \n\t" \ + "push r11 \n\t" \ + "push r12 \n\t" \ + "push r13 \n\t" \ + "push r14 \n\t" \ + "push r15 \n\t" \ + "push r16 \n\t" \ + "push r17 \n\t" \ + "push r18 \n\t" \ + "push r19 \n\t" \ + "push r20 \n\t" \ + "push r21 \n\t" \ + "push r22 \n\t" \ + "push r23 \n\t" \ + "push r24 \n\t" \ + "push r25 \n\t" \ + "push r26 \n\t" \ + "push r27 \n\t" \ + "push r28 \n\t" \ + "push r29 \n\t" \ + "push r30 \n\t" \ + "push r31 \n\t" \ + "lds r26, pxCurrentTCB \n\t" \ + "lds r27, pxCurrentTCB + 1 \n\t" \ + "in r0, 0x3d \n\t" \ + "st x+, r0 \n\t" \ + "in r0, 0x3e \n\t" \ + "st x+, r0 \n\t" \ + ); + +/* + * Opposite to portSAVE_CONTEXT(). Interrupts will have been disabled during + * the context save so we can write to the stack pointer. + */ + +#define portRESTORE_CONTEXT() \ + asm volatile ( "lds r26, pxCurrentTCB \n\t" \ + "lds r27, pxCurrentTCB + 1 \n\t" \ + "ld r28, x+ \n\t" \ + "out __SP_L__, r28 \n\t" \ + "ld r29, x+ \n\t" \ + "out __SP_H__, r29 \n\t" \ + "pop r31 \n\t" \ + "pop r30 \n\t" \ + "pop r29 \n\t" \ + "pop r28 \n\t" \ + "pop r27 \n\t" \ + "pop r26 \n\t" \ + "pop r25 \n\t" \ + "pop r24 \n\t" \ + "pop r23 \n\t" \ + "pop r22 \n\t" \ + "pop r21 \n\t" \ + "pop r20 \n\t" \ + "pop r19 \n\t" \ + "pop r18 \n\t" \ + "pop r17 \n\t" \ + "pop r16 \n\t" \ + "pop r15 \n\t" \ + "pop r14 \n\t" \ + "pop r13 \n\t" \ + "pop r12 \n\t" \ + "pop r11 \n\t" \ + "pop r10 \n\t" \ + "pop r9 \n\t" \ + "pop r8 \n\t" \ + "pop r7 \n\t" \ + "pop r6 \n\t" \ + "pop r5 \n\t" \ + "pop r4 \n\t" \ + "pop r3 \n\t" \ + "pop r2 \n\t" \ + "pop r1 \n\t" \ + "pop r0 \n\t" \ + "out __SREG__, r0 \n\t" \ + "pop r0 \n\t" \ + ); + +/*-----------------------------------------------------------*/ + +/* + * Perform hardware setup to enable ticks from timer 1, compare match A. + */ +static void prvSetupTimerInterrupt( void ); +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ +unsigned portSHORT usAddress; + + /* Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging. */ + + *pxTopOfStack = 0x11; + pxTopOfStack--; + *pxTopOfStack = 0x22; + pxTopOfStack--; + *pxTopOfStack = 0x33; + pxTopOfStack--; + + /* Simulate how the stack would look after a call to vPortYield() generated by + the compiler. */ + + /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */ + + /* The start of the task code will be popped off the stack last, so place + it on first. */ + usAddress = ( unsigned portSHORT ) pxCode; + *pxTopOfStack = ( portSTACK_TYPE ) ( usAddress & ( unsigned portSHORT ) 0x00ff ); + pxTopOfStack--; + + usAddress >>= 8; + *pxTopOfStack = ( portSTACK_TYPE ) ( usAddress & ( unsigned portSHORT ) 0x00ff ); + pxTopOfStack--; + + /* Next simulate the stack as if after a call to portSAVE_CONTEXT(). + portSAVE_CONTEXT places the flags on the stack immediately after r0 + to ensure the interrupts get disabled as soon as possible, and so ensuring + the stack use is minimal should a context switch interrupt occur. */ + *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* R0 */ + pxTopOfStack--; + *pxTopOfStack = portFLAGS_INT_ENABLED; + pxTopOfStack--; + + + /* Now the remaining registers. The compiler expects R1 to be 0. */ + *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x02; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x03; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x04; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x05; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x06; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x07; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x08; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x09; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x10; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x11; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x12; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x13; /* R13 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x14; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x15; /* R15 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x16; /* R16 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x17; /* R17 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x18; /* R18 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x19; /* R19 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x20; /* R20 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x21; /* R21 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x22; /* R22 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x23; /* R23 */ + pxTopOfStack--; + + /* Place the parameter on the stack in the expected location. */ + usAddress = ( unsigned portSHORT ) pvParameters; + *pxTopOfStack = ( portSTACK_TYPE ) ( usAddress & ( unsigned portSHORT ) 0x00ff ); + pxTopOfStack--; + + usAddress >>= 8; + *pxTopOfStack = ( portSTACK_TYPE ) ( usAddress & ( unsigned portSHORT ) 0x00ff ); + pxTopOfStack--; + + *pxTopOfStack = ( portSTACK_TYPE ) 0x26; /* R26 X */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x27; /* R27 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x28; /* R28 Y */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x29; /* R29 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x30; /* R30 Z */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x031; /* R31 */ + pxTopOfStack--; + + /*lint +e950 +e611 +e923 */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xPortStartScheduler( void ) +{ + /* Setup the hardware to generate the tick. */ + prvSetupTimerInterrupt(); + + /* Restore the context of the first task that is going to run. */ + portRESTORE_CONTEXT(); + + /* Simulate a function call end as generated by the compiler. We will now + jump to the start of the task the context of which we have just restored. */ + asm volatile ( "ret" ); + + /* Should not get here. */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the AVR port will get stopped. If required simply + disable the tick interrupt here. */ +} +/*-----------------------------------------------------------*/ + +/* + * Manual context switch. The first thing we do is save the registers so we + * can use a naked attribute. + */ +void vPortYield( void ) __attribute__ ( ( naked ) ); +void vPortYield( void ) +{ + portSAVE_CONTEXT(); + vTaskSwitchContext(); + portRESTORE_CONTEXT(); + + asm volatile ( "ret" ); +} +/*-----------------------------------------------------------*/ + +/* + * Context switch function used by the tick. This must be identical to + * vPortYield() from the call to vTaskSwitchContext() onwards. The only + * difference from vPortYield() is the tick count is incremented as the + * call comes from the tick ISR. + */ +void vPortYieldFromTick( void ) __attribute__ ( ( naked ) ); +void vPortYieldFromTick( void ) +{ + portSAVE_CONTEXT(); + vTaskIncrementTick(); + vTaskSwitchContext(); + portRESTORE_CONTEXT(); + + asm volatile ( "ret" ); +} +/*-----------------------------------------------------------*/ + +/* + * Setup timer 1 compare match A to generate a tick interrupt. + */ +static void prvSetupTimerInterrupt( void ) +{ +unsigned portLONG ulCompareMatch; +unsigned portCHAR ucHighByte, ucLowByte; + + /* Using 16bit timer 1 to generate the tick. Correct fuses must be + selected for the configCPU_CLOCK_HZ clock. */ + + ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ; + + /* We only have 16 bits so have to scale to get our required tick rate. */ + ulCompareMatch /= portCLOCK_PRESCALER; + + /* Adjust for correct value. */ + ulCompareMatch -= ( unsigned portLONG ) 1; + + /* Setup compare match value for compare match A. Interrupts are disabled + before this is called so we need not worry here. */ + ucLowByte = ( unsigned portCHAR ) ( ulCompareMatch & ( unsigned portLONG ) 0xff ); + ulCompareMatch >>= 8; + ucHighByte = ( unsigned portCHAR ) ( ulCompareMatch & ( unsigned portLONG ) 0xff ); + OCR1AH = ucHighByte; + OCR1AL = ucLowByte; + + /* Setup clock source and compare match behaviour. */ + ucLowByte = portCLEAR_COUNTER_ON_MATCH | portPRESCALE_64; + TCCR1B = ucLowByte; + + /* Enable the interrupt - this is okay as interrupt are currently globally + disabled. */ + ucLowByte = TIMSK; + ucLowByte |= portCOMPARE_MATCH_A_INTERRUPT_ENABLE; + TIMSK = ucLowByte; +} +/*-----------------------------------------------------------*/ + +#if configUSE_PREEMPTION == 1 + + /* + * Tick ISR for preemptive scheduler. We can use a naked attribute as + * the context is saved at the start of vPortYieldFromTick(). The tick + * count is incremented after the context is saved. + */ + void SIG_OUTPUT_COMPARE1A( void ) __attribute__ ( ( signal, naked ) ); + void SIG_OUTPUT_COMPARE1A( void ) + { + vPortYieldFromTick(); + asm volatile ( "reti" ); + } +#else + + /* + * Tick ISR for the cooperative scheduler. All this does is increment the + * tick count. We don't need to switch context, this can only be done by + * manual calls to taskYIELD(); + */ + void SIG_OUTPUT_COMPARE1A( void ) __attribute__ ( ( signal ) ); + void SIG_OUTPUT_COMPARE1A( void ) + { + vTaskIncrementTick(); + } +#endif + + + diff --git a/20080212/Source/portable/GCC/ATMega323/portmacro.h b/20080212/Source/portable/GCC/ATMega323/portmacro.h new file mode 100644 index 000000000..25c7f41d4 --- /dev/null +++ b/20080212/Source/portable/GCC/ATMega323/portmacro.h @@ -0,0 +1,118 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V1.2.3 + + + portCPU_CLOSK_HZ definition changed to 8MHz base 10, previously it + base 16. +*/ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE unsigned portCHAR +#define portBASE_TYPE char + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +#define portENTER_CRITICAL() asm volatile ( "in __tmp_reg__, __SREG__" :: ); \ + asm volatile ( "cli" :: ); \ + asm volatile ( "push __tmp_reg__" :: ) + +#define portEXIT_CRITICAL() asm volatile ( "pop __tmp_reg__" :: ); \ + asm volatile ( "out __SREG__, __tmp_reg__" :: ) + +#define portDISABLE_INTERRUPTS() asm volatile ( "cli" :: ); +#define portENABLE_INTERRUPTS() asm volatile ( "sei" :: ); +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 1 +#define portNOP() asm volatile ( "nop" ); +/*-----------------------------------------------------------*/ + +/* Kernel utilities. */ +extern void vPortYield( void ) __attribute__ ( ( naked ) ); +#define portYIELD() vPortYield() +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/20080212/Source/portable/GCC/AVR32_UC3/exception.S b/20080212/Source/portable/GCC/AVR32_UC3/exception.S new file mode 100644 index 000000000..9a2833f2e --- /dev/null +++ b/20080212/Source/portable/GCC/AVR32_UC3/exception.S @@ -0,0 +1,297 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Exception and interrupt vectors. + * + * This file maps all events supported by an AVR32UC. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: All AVR32UC devices with an INTC module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include +#include "intc.h" + + +//! @{ +//! \verbatim + + + .section .exception, "ax", @progbits + + +// Start of Exception Vector Table. + + // EVBA must be aligned with a power of two strictly greater than the EVBA- + // relative offset of the last vector. + .balign 0x200 + + // Export symbol. + .global _evba + .type _evba, @function +_evba: + + .org 0x000 + // Unrecoverable Exception. +_handle_Unrecoverable_Exception: + rjmp $ + + .org 0x004 + // TLB Multiple Hit: UNUSED IN AVR32UC. +_handle_TLB_Multiple_Hit: + rjmp $ + + .org 0x008 + // Bus Error Data Fetch. +_handle_Bus_Error_Data_Fetch: + rjmp $ + + .org 0x00C + // Bus Error Instruction Fetch. +_handle_Bus_Error_Instruction_Fetch: + rjmp $ + + .org 0x010 + // NMI. +_handle_NMI: + rjmp $ + + .org 0x014 + // Instruction Address. +_handle_Instruction_Address: + rjmp $ + + .org 0x018 + // ITLB Protection. +_handle_ITLB_Protection: + rjmp $ + + .org 0x01C + // Breakpoint. +_handle_Breakpoint: + rjmp $ + + .org 0x020 + // Illegal Opcode. +_handle_Illegal_Opcode: + rjmp $ + + .org 0x024 + // Unimplemented Instruction. +_handle_Unimplemented_Instruction: + rjmp $ + + .org 0x028 + // Privilege Violation. +_handle_Privilege_Violation: + rjmp $ + + .org 0x02C + // Floating-Point: UNUSED IN AVR32UC. +_handle_Floating_Point: + rjmp $ + + .org 0x030 + // Coprocessor Absent: UNUSED IN AVR32UC. +_handle_Coprocessor_Absent: + rjmp $ + + .org 0x034 + // Data Address (Read). +_handle_Data_Address_Read: + rjmp $ + + .org 0x038 + // Data Address (Write). +_handle_Data_Address_Write: + rjmp $ + + .org 0x03C + // DTLB Protection (Read). +_handle_DTLB_Protection_Read: + rjmp $ + + .org 0x040 + // DTLB Protection (Write). +_handle_DTLB_Protection_Write: + rjmp $ + + .org 0x044 + // DTLB Modified: UNUSED IN AVR32UC. +_handle_DTLB_Modified: + rjmp $ + + .org 0x050 + // ITLB Miss: UNUSED IN AVR32UC. +_handle_ITLB_Miss: + rjmp $ + + .org 0x060 + // DTLB Miss (Read): UNUSED IN AVR32UC. +_handle_DTLB_Miss_Read: + rjmp $ + + .org 0x070 + // DTLB Miss (Write): UNUSED IN AVR32UC. +_handle_DTLB_Miss_Write: + rjmp $ + + .org 0x100 + // Supervisor Call. +_handle_Supervisor_Call: + lda.w pc, SCALLYield + + +// Interrupt support. +// The interrupt controller must provide the offset address relative to EVBA. +// Important note: +// All interrupts call a C function named _get_interrupt_handler. +// This function will read group and interrupt line number to then return in +// R12 a pointer to a user-provided interrupt handler. + + .balign 4 + +_int0: + // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the + // CPU upon interrupt entry. +#if 1 // B1832: interrupt stack changed to exception stack if exception is detected. + mfsr r12, AVR32_SR + bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE + cp.w r12, 0b110 + brlo _int0_normal + lddsp r12, sp[0 * 4] + stdsp sp[6 * 4], r12 + lddsp r12, sp[1 * 4] + stdsp sp[7 * 4], r12 + lddsp r12, sp[3 * 4] + sub sp, -6 * 4 + rete +_int0_normal: +#endif + mov r12, 0 // Pass the int_lev parameter to the _get_interrupt_handler function. + call _get_interrupt_handler + cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function. + movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler. + rete // If this was a spurious interrupt (R12 == NULL), return from event handler. + +_int1: + // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the + // CPU upon interrupt entry. +#if 1 // B1832: interrupt stack changed to exception stack if exception is detected. + mfsr r12, AVR32_SR + bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE + cp.w r12, 0b110 + brlo _int1_normal + lddsp r12, sp[0 * 4] + stdsp sp[6 * 4], r12 + lddsp r12, sp[1 * 4] + stdsp sp[7 * 4], r12 + lddsp r12, sp[3 * 4] + sub sp, -6 * 4 + rete +_int1_normal: +#endif + mov r12, 1 // Pass the int_lev parameter to the _get_interrupt_handler function. + call _get_interrupt_handler + cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function. + movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler. + rete // If this was a spurious interrupt (R12 == NULL), return from event handler. + +_int2: + // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the + // CPU upon interrupt entry. +#if 1 // B1832: interrupt stack changed to exception stack if exception is detected. + mfsr r12, AVR32_SR + bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE + cp.w r12, 0b110 + brlo _int2_normal + lddsp r12, sp[0 * 4] + stdsp sp[6 * 4], r12 + lddsp r12, sp[1 * 4] + stdsp sp[7 * 4], r12 + lddsp r12, sp[3 * 4] + sub sp, -6 * 4 + rete +_int2_normal: +#endif + mov r12, 2 // Pass the int_lev parameter to the _get_interrupt_handler function. + call _get_interrupt_handler + cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function. + movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler. + rete // If this was a spurious interrupt (R12 == NULL), return from event handler. + +_int3: + // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the + // CPU upon interrupt entry. +#if 1 // B1832: interrupt stack changed to exception stack if exception is detected. + mfsr r12, AVR32_SR + bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE + cp.w r12, 0b110 + brlo _int3_normal + lddsp r12, sp[0 * 4] + stdsp sp[6 * 4], r12 + lddsp r12, sp[1 * 4] + stdsp sp[7 * 4], r12 + lddsp r12, sp[3 * 4] + sub sp, -6 * 4 + rete +_int3_normal: +#endif + mov r12, 3 // Pass the int_lev parameter to the _get_interrupt_handler function. + call _get_interrupt_handler + cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function. + movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler. + rete // If this was a spurious interrupt (R12 == NULL), return from event handler. + + +// Constant data area. + + .balign 4 + + // Values to store in the interrupt priority registers for the various interrupt priority levels. + // The interrupt priority registers contain the interrupt priority level and + // the EVBA-relative interrupt vector offset. + .global ipr_val + .type ipr_val, @object +ipr_val: + .word (INT0 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int0 - _evba),\ + (INT1 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int1 - _evba),\ + (INT2 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int2 - _evba),\ + (INT3 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int3 - _evba) + + +//! \endverbatim +//! @} diff --git a/20080212/Source/portable/GCC/AVR32_UC3/port.c b/20080212/Source/portable/GCC/AVR32_UC3/port.c new file mode 100644 index 000000000..e964407d7 --- /dev/null +++ b/20080212/Source/portable/GCC/AVR32_UC3/port.c @@ -0,0 +1,450 @@ +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief FreeRTOS port source for AVR32 UC3. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + *****************************************************************************/ + +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +/* Standard includes. */ +#include +#include +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* AVR32 UC3 includes. */ +#include +#include "gpio.h" +#if( configTICK_USE_TC==1 ) + #include "tc.h" +#endif + + +/* Constants required to setup the task context. */ +#define portINITIAL_SR ( ( portSTACK_TYPE ) 0x00400000 ) /* AVR32 : [M2:M0]=001 I1M=0 I0M=0, GM=0 */ +#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 0 ) + +/* Each task maintains its own critical nesting variable. */ +#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 ) +volatile unsigned portLONG ulCriticalNesting = 9999UL; + +#if( configTICK_USE_TC==0 ) + static void prvScheduleNextTick( void ); +#else + static void prvClearTcInt( void ); +#endif + +/* Setup the timer to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/*-----------------------------------------------------------*/ + +/* + * Low-level initialization routine called during startup, before the main + * function. + * This version comes in replacement to the default one provided by Newlib. + * Newlib's _init_startup only calls init_exceptions, but Newlib's exception + * vectors are not compatible with the SCALL management in the current FreeRTOS + * port. More low-level initializations are besides added here. + */ +void _init_startup(void) +{ + /* Import the Exception Vector Base Address. */ + extern void _evba; + + #if configHEAP_INIT + extern void __heap_start__; + extern void __heap_end__; + portBASE_TYPE *pxMem; + #endif + + /* Load the Exception Vector Base Address in the corresponding system register. */ + Set_system_register( AVR32_EVBA, ( int ) &_evba ); + + /* Enable exceptions. */ + ENABLE_ALL_EXCEPTIONS(); + + /* Initialize interrupt handling. */ + INTC_init_interrupts(); + + #if configHEAP_INIT + + /* Initialize the heap used by malloc. */ + for( pxMem = &__heap_start__; pxMem < ( portBASE_TYPE * )&__heap_end__; ) + { + *pxMem++ = 0xA5A5A5A5; + } + + #endif + + /* Give the used CPU clock frequency to Newlib, so it can work properly. */ + set_cpu_hz( configCPU_CLOCK_HZ ); + + /* Code section present if and only if the debug trace is activated. */ + #if configDBG + { + static const gpio_map_t DBG_USART_GPIO_MAP = + { + { configDBG_USART_RX_PIN, configDBG_USART_RX_FUNCTION }, + { configDBG_USART_TX_PIN, configDBG_USART_TX_FUNCTION } + }; + + /* Initialize the USART used for the debug trace with the configured parameters. */ + set_usart_base( ( void * ) configDBG_USART ); + gpio_enable_module( DBG_USART_GPIO_MAP, + sizeof( DBG_USART_GPIO_MAP ) / sizeof( DBG_USART_GPIO_MAP[0] ) ); + usart_init( configDBG_USART_BAUDRATE ); + } + #endif +} +/*-----------------------------------------------------------*/ + +/* + * malloc, realloc and free are meant to be called through respectively + * pvPortMalloc, pvPortRealloc and vPortFree. + * The latter functions call the former ones from within sections where tasks + * are suspended, so the latter functions are task-safe. __malloc_lock and + * __malloc_unlock use the same mechanism to also keep the former functions + * task-safe as they may be called directly from Newlib's functions. + * However, all these functions are interrupt-unsafe and SHALL THEREFORE NOT BE + * CALLED FROM WITHIN AN INTERRUPT, because __malloc_lock and __malloc_unlock do + * not call portENTER_CRITICAL and portEXIT_CRITICAL in order not to disable + * interrupts during memory allocation management as this may be a very time- + * consuming process. + */ + +/* + * Lock routine called by Newlib on malloc / realloc / free entry to guarantee a + * safe section as memory allocation management uses global data. + * See the aforementioned details. + */ +void __malloc_lock(struct _reent *ptr) +{ + vTaskSuspendAll(); +} + +/* + * Unlock routine called by Newlib on malloc / realloc / free exit to guarantee + * a safe section as memory allocation management uses global data. + * See the aforementioned details. + */ +void __malloc_unlock(struct _reent *ptr) +{ + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +/* Added as there is no such function in FreeRTOS. */ +void *pvPortRealloc( void *pv, size_t xWantedSize ) +{ +void *pvReturn; + + vTaskSuspendAll(); + { + pvReturn = realloc( pv, xWantedSize ); + } + xTaskResumeAll(); + + return pvReturn; +} +/*-----------------------------------------------------------*/ + +/* The cooperative scheduler requires a normal IRQ service routine to +simply increment the system tick. */ +/* The preemptive scheduler is defined as "naked" as the full context is saved +on entry as part of the context switch. */ +__attribute__((__naked__)) static void vTick( void ) +{ + /* Save the context of the interrupted task. */ + portSAVE_CONTEXT_OS_INT(); + + #if( configTICK_USE_TC==1 ) + /* Clear the interrupt flag. */ + prvClearTcInt(); + #else + /* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ) + clock cycles from now. */ + prvScheduleNextTick(); + #endif + + /* Because FreeRTOS is not supposed to run with nested interrupts, put all OS + calls in a critical section . */ + portENTER_CRITICAL(); + vTaskIncrementTick(); + portEXIT_CRITICAL(); + + /* Restore the context of the "elected task". */ + portRESTORE_CONTEXT_OS_INT(); +} +/*-----------------------------------------------------------*/ + +__attribute__((__naked__)) void SCALLYield( void ) +{ + /* Save the context of the interrupted task. */ + portSAVE_CONTEXT_SCALL(); + vTaskSwitchContext(); + portRESTORE_CONTEXT_SCALL(); +} +/*-----------------------------------------------------------*/ + +/* The code generated by the GCC compiler uses the stack in different ways at +different optimisation levels. The interrupt flags can therefore not always +be saved to the stack. Instead the critical section nesting level is stored +in a variable, which is then saved as part of the stack context. */ +__attribute__((__noinline__)) void vPortEnterCritical( void ) +{ + /* Disable interrupts */ + portDISABLE_INTERRUPTS(); + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +__attribute__((__noinline__)) void vPortExitCritical( void ) +{ + if(ulCriticalNesting > portNO_CRITICAL_NESTING) + { + ulCriticalNesting--; + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Enable all interrupt/exception. */ + portENABLE_INTERRUPTS(); + } + } +} +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. */ + + /* When the task starts, it will expect to find the function parameter in R12. */ + pxTopOfStack--; + *pxTopOfStack-- = ( portSTACK_TYPE ) 0x08080808; /* R8 */ + *pxTopOfStack-- = ( portSTACK_TYPE ) 0x09090909; /* R9 */ + *pxTopOfStack-- = ( portSTACK_TYPE ) 0x0A0A0A0A; /* R10 */ + *pxTopOfStack-- = ( portSTACK_TYPE ) 0x0B0B0B0B; /* R11 */ + *pxTopOfStack-- = ( portSTACK_TYPE ) pvParameters; /* R12 */ + *pxTopOfStack-- = ( portSTACK_TYPE ) 0xDEADBEEF; /* R14/LR */ + *pxTopOfStack-- = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; /* R15/PC */ + *pxTopOfStack-- = ( portSTACK_TYPE ) portINITIAL_SR; /* SR */ + *pxTopOfStack-- = ( portSTACK_TYPE ) 0xFF0000FF; /* R0 */ + *pxTopOfStack-- = ( portSTACK_TYPE ) 0x01010101; /* R1 */ + *pxTopOfStack-- = ( portSTACK_TYPE ) 0x02020202; /* R2 */ + *pxTopOfStack-- = ( portSTACK_TYPE ) 0x03030303; /* R3 */ + *pxTopOfStack-- = ( portSTACK_TYPE ) 0x04040404; /* R4 */ + *pxTopOfStack-- = ( portSTACK_TYPE ) 0x05050505; /* R5 */ + *pxTopOfStack-- = ( portSTACK_TYPE ) 0x06060606; /* R6 */ + *pxTopOfStack-- = ( portSTACK_TYPE ) 0x07070707; /* R7 */ + *pxTopOfStack = ( portSTACK_TYPE ) portNO_CRITICAL_NESTING; /* ulCriticalNesting */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xPortStartScheduler( void ) +{ + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + portRESTORE_CONTEXT(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the AVR32 port will require this function as there + is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +/* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ) +clock cycles from now. */ +#if( configTICK_USE_TC==0 ) + static void prvScheduleFirstTick(void) + { + unsigned long lCycles; + + lCycles = Get_system_register(AVR32_COUNT); + lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ); + // If lCycles ends up to be 0, make it 1 so that the COMPARE and exception + // generation feature does not get disabled. + if(0 == lCycles) + { + lCycles++; + } + Set_system_register(AVR32_COMPARE, lCycles); + } + + __attribute__((__noinline__)) static void prvScheduleNextTick(void) + { + unsigned long lCycles, lCount; + + lCycles = Get_system_register(AVR32_COMPARE); + lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ); + // If lCycles ends up to be 0, make it 1 so that the COMPARE and exception + // generation feature does not get disabled. + if(0 == lCycles) + { + lCycles++; + } + lCount = Get_system_register(AVR32_COUNT); + if( lCycles < lCount ) + { // We missed a tick, recover for the next. + lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ); + } + Set_system_register(AVR32_COMPARE, lCycles); + } +#else + __attribute__((__noinline__)) static void prvClearTcInt(void) + { + AVR32_TC.channel[configTICK_TC_CHANNEL].sr; + } +#endif +/*-----------------------------------------------------------*/ + +/* Setup the timer to generate the tick interrupts. */ +static void prvSetupTimerInterrupt(void) +{ +#if( configTICK_USE_TC==1 ) + + volatile avr32_tc_t *tc = &AVR32_TC; + + // Options for waveform genration. + tc_waveform_opt_t waveform_opt = + { + .channel = configTICK_TC_CHANNEL, /* Channel selection. */ + + .bswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOB. */ + .beevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOB. */ + .bcpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOB. */ + .bcpb = TC_EVT_EFFECT_NOOP, /* RB compare effect on TIOB. */ + + .aswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOA. */ + .aeevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOA. */ + .acpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOA: toggle. */ + .acpa = TC_EVT_EFFECT_NOOP, /* RA compare effect on TIOA: toggle (other possibilities are none, set and clear). */ + + .wavsel = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER,/* Waveform selection: Up mode without automatic trigger on RC compare. */ + .enetrg = FALSE, /* External event trigger enable. */ + .eevt = 0, /* External event selection. */ + .eevtedg = TC_SEL_NO_EDGE, /* External event edge selection. */ + .cpcdis = FALSE, /* Counter disable when RC compare. */ + .cpcstop = FALSE, /* Counter clock stopped with RC compare. */ + + .burst = FALSE, /* Burst signal selection. */ + .clki = FALSE, /* Clock inversion. */ + .tcclks = TC_CLOCK_SOURCE_TC2 /* Internal source clock 2. */ + }; + + tc_interrupt_t tc_interrupt = + { + .etrgs=0, + .ldrbs=0, + .ldras=0, + .cpcs =1, + .cpbs =0, + .cpas =0, + .lovrs=0, + .covfs=0, + }; + +#endif + + /* Disable all interrupt/exception. */ + portDISABLE_INTERRUPTS(); + + /* Register the compare interrupt handler to the interrupt controller and + enable the compare interrupt. */ + + #if( configTICK_USE_TC==1 ) + { + INTC_register_interrupt(&vTick, configTICK_TC_IRQ, INT0); + + /* Initialize the timer/counter. */ + tc_init_waveform(tc, &waveform_opt); + + /* Set the compare triggers. + Remember TC counter is 16-bits, so counting second is not possible! + That's why we configure it to count ms. */ + tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ / 4) / configTICK_RATE_HZ ); + + tc_configure_interrupts( tc, configTICK_TC_CHANNEL, &tc_interrupt ); + + /* Start the timer/counter. */ + tc_start(tc, configTICK_TC_CHANNEL); + } + #else + { + INTC_register_interrupt(&vTick, AVR32_CORE_COMPARE_IRQ, INT0); + prvScheduleFirstTick(); + } + #endif +} diff --git a/20080212/Source/portable/GCC/AVR32_UC3/portmacro.h b/20080212/Source/portable/GCC/AVR32_UC3/portmacro.h new file mode 100644 index 000000000..af85cfa37 --- /dev/null +++ b/20080212/Source/portable/GCC/AVR32_UC3/portmacro.h @@ -0,0 +1,678 @@ +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief FreeRTOS port source for AVR32 UC3. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + *****************************************************************************/ + +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ +#include +#include "intc.h" +#include "compiler.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned portLONG +#define portBASE_TYPE portLONG + +#define TASK_DELAY_MS(x) ( (x) /portTICK_RATE_MS ) +#define TASK_DELAY_S(x) ( (x)*1000 /portTICK_RATE_MS ) +#define TASK_DELAY_MIN(x) ( (x)*60*1000/portTICK_RATE_MS ) + +#define configTICK_TC_IRQ ATPASTE2(AVR32_TC_IRQ, configTICK_TC_CHANNEL) + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 4 +#define portNOP() {__asm__ __volatile__ ("nop");} +/*-----------------------------------------------------------*/ + + +/*-----------------------------------------------------------*/ + +/* INTC-specific. */ +#define DISABLE_ALL_EXCEPTIONS() Disable_global_exception() +#define ENABLE_ALL_EXCEPTIONS() Enable_global_exception() + +#define DISABLE_ALL_INTERRUPTS() Disable_global_interrupt() +#define ENABLE_ALL_INTERRUPTS() Enable_global_interrupt() + +#define DISABLE_INT_LEVEL(int_lev) Disable_interrupt_level(int_lev) +#define ENABLE_INT_LEVEL(int_lev) Enable_interrupt_level(int_lev) + + +/* + * Debug trace. + * Activated if and only if configDBG is nonzero. + * Prints a formatted string to stdout. + * The current source file name and line number are output with a colon before + * the formatted string. + * A carriage return and a linefeed are appended to the output. + * stdout is redirected to the USART configured by configDBG_USART. + * The parameters are the same as for the standard printf function. + * There is no return value. + * SHALL NOT BE CALLED FROM WITHIN AN INTERRUPT as fputs and printf use malloc, + * which is interrupt-unsafe with the current __malloc_lock and __malloc_unlock. + */ +#if configDBG +#define portDBG_TRACE(...) \ +{\ + fputs(__FILE__ ":" ASTRINGZ(__LINE__) ": ", stdout);\ + printf(__VA_ARGS__);\ + fputs("\r\n", stdout);\ +} +#else +#define portDBG_TRACE(...) +#endif + + +/* Critical section management. */ +#define portDISABLE_INTERRUPTS() DISABLE_ALL_INTERRUPTS() +#define portENABLE_INTERRUPTS() ENABLE_ALL_INTERRUPTS() + + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); + + +/* Added as there is no such function in FreeRTOS. */ +extern void *pvPortRealloc( void *pv, size_t xSize ); +/*-----------------------------------------------------------*/ + + +/*=============================================================================================*/ + +/* + * Restore Context for cases other than INTi. + */ +#define portRESTORE_CONTEXT() \ +{ \ + extern volatile unsigned portLONG ulCriticalNesting; \ + extern volatile void *volatile pxCurrentTCB; \ + \ + __asm__ __volatile__ ( \ + /* Set SP to point to new stack */ \ + "mov r8, LO(%[pxCurrentTCB]) \n\t"\ + "orh r8, HI(%[pxCurrentTCB]) \n\t"\ + "ld.w r0, r8[0] \n\t"\ + "ld.w sp, r0[0] \n\t"\ + \ + /* Restore ulCriticalNesting variable */ \ + "ld.w r0, sp++ \n\t"\ + "mov r8, LO(%[ulCriticalNesting]) \n\t"\ + "orh r8, HI(%[ulCriticalNesting]) \n\t"\ + "st.w r8[0], r0 \n\t"\ + \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t"\ + /* R0-R7 should not be used below this line */ \ + /* Skip PC and SR (will do it at the end) */ \ + "sub sp, -2*4 \n\t"\ + /* Restore R8..R12 and LR */ \ + "ldm sp++, r8-r12, lr \n\t"\ + /* Restore SR */ \ + "ld.w r0, sp[-8*4]\n\t" /* R0 is modified, is restored later. */ \ + "mtsr %[SR], r0 \n\t"\ + /* Restore r0 */ \ + "ld.w r0, sp[-9*4] \n\t"\ + /* Restore PC */ \ + "ld.w pc, sp[-7*4]" /* Get PC from stack - PC is the 7th register saved */ \ + : \ + : [ulCriticalNesting] "i" (&ulCriticalNesting), \ + [pxCurrentTCB] "i" (&pxCurrentTCB), \ + [SR] "i" (AVR32_SR) \ + ); \ +} + + +/* + * portSAVE_CONTEXT_INT() and portRESTORE_CONTEXT_INT(): for INT0..3 exceptions. + * portSAVE_CONTEXT_SCALL() and portRESTORE_CONTEXT_SCALL(): for the scall exception. + * + * Had to make different versions because registers saved on the system stack + * are not the same between INT0..3 exceptions and the scall exception. + */ + +// Task context stack layout: + // R8 (*) + // R9 (*) + // R10 (*) + // R11 (*) + // R12 (*) + // R14/LR (*) + // R15/PC (*) + // SR (*) + // R0 + // R1 + // R2 + // R3 + // R4 + // R5 + // R6 + // R7 + // ulCriticalNesting +// (*) automatically done for INT0..INT3, but not for SCALL + +/* + * The ISR used for the scheduler tick depends on whether the cooperative or + * the preemptive scheduler is being used. + */ +#if configUSE_PREEMPTION == 0 + +/* + * portSAVE_CONTEXT_OS_INT() for OS Tick exception. + */ +#define portSAVE_CONTEXT_OS_INT() \ +{ \ + /* Save R0..R7 */ \ + __asm__ __volatile__ ("stm --sp, r0-r7"); \ + \ + /* With the cooperative scheduler, as there is no context switch by interrupt, */ \ + /* there is also no context save. */ \ +} + +/* + * portRESTORE_CONTEXT_OS_INT() for Tick exception. + */ +#define portRESTORE_CONTEXT_OS_INT() \ +{ \ + __asm__ __volatile__ ( \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7\n\t" \ + \ + /* With the cooperative scheduler, as there is no context switch by interrupt, */ \ + /* there is also no context restore. */ \ + "rete" \ + ); \ +} + +#else + +/* + * portSAVE_CONTEXT_OS_INT() for OS Tick exception. + */ +#define portSAVE_CONTEXT_OS_INT() \ +{ \ + extern volatile unsigned portLONG ulCriticalNesting; \ + extern volatile void *volatile pxCurrentTCB; \ + \ + /* When we come here */ \ + /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \ + \ + __asm__ __volatile__ ( \ + /* Save R0..R7 */ \ + "stm --sp, r0-r7 \n\t"\ + \ + /* Save ulCriticalNesting variable - R0 is overwritten */ \ + "mov r8, LO(%[ulCriticalNesting])\n\t" \ + "orh r8, HI(%[ulCriticalNesting])\n\t" \ + "ld.w r0, r8[0] \n\t"\ + "st.w --sp, r0 \n\t"\ + \ + /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \ + /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ + /* level and allow other lower interrupt level to occur). */ \ + /* In this case we don't want to do a task switch because we don't know what the stack */ \ + /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \ + /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \ + /* will just be restoring the interrupt handler, no way!!! */ \ + /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \ + "ld.w r0, sp[9*4]\n\t" /* Read SR in stack */ \ + "bfextu r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */ \ + "cp.w r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */ \ + "brhi LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE] \n\t"\ + \ + /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \ + /* NOTE: we don't enter a critical section here because all interrupt handlers */ \ + /* MUST perform a SAVE_CONTEXT/RESTORE_CONTEXT in the same way as */ \ + /* portSAVE_CONTEXT_OS_INT/port_RESTORE_CONTEXT_OS_INT if they call OS functions. */ \ + /* => all interrupt handlers must use portENTER_SWITCHING_ISR/portEXIT_SWITCHING_ISR. */ \ + "mov r8, LO(%[pxCurrentTCB])\n\t" \ + "orh r8, HI(%[pxCurrentTCB])\n\t" \ + "ld.w r0, r8[0]\n\t" \ + "st.w r0[0], sp\n" \ + \ + "LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE]:" \ + : \ + : [ulCriticalNesting] "i" (&ulCriticalNesting), \ + [pxCurrentTCB] "i" (&pxCurrentTCB), \ + [LINE] "i" (__LINE__) \ + ); \ +} + +/* + * portRESTORE_CONTEXT_OS_INT() for Tick exception. + */ +#define portRESTORE_CONTEXT_OS_INT() \ +{ \ + extern volatile unsigned portLONG ulCriticalNesting; \ + extern volatile void *volatile pxCurrentTCB; \ + \ + /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \ + /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ + /* level and allow other lower interrupt level to occur). */ \ + /* In this case we don't want to do a task switch because we don't know what the stack */ \ + /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \ + /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \ + /* will just be restoring the interrupt handler, no way!!! */ \ + __asm__ __volatile__ ( \ + "ld.w r0, sp[9*4]\n\t" /* Read SR in stack */ \ + "bfextu r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */ \ + "cp.w r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */ \ + "brhi LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]" \ + : \ + : [LINE] "i" (__LINE__) \ + ); \ + \ + /* Else */ \ + /* because it is here safe, always call vTaskSwitchContext() since an OS tick occurred. */ \ + /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */\ + portENTER_CRITICAL(); \ + vTaskSwitchContext(); \ + portEXIT_CRITICAL(); \ + \ + /* Restore all registers */ \ + \ + __asm__ __volatile__ ( \ + /* Set SP to point to new stack */ \ + "mov r8, LO(%[pxCurrentTCB]) \n\t"\ + "orh r8, HI(%[pxCurrentTCB]) \n\t"\ + "ld.w r0, r8[0] \n\t"\ + "ld.w sp, r0[0] \n"\ + \ + "LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]: \n\t"\ + \ + /* Restore ulCriticalNesting variable */ \ + "ld.w r0, sp++ \n\t" \ + "mov r8, LO(%[ulCriticalNesting]) \n\t"\ + "orh r8, HI(%[ulCriticalNesting]) \n\t"\ + "st.w r8[0], r0 \n\t"\ + \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t"\ + \ + /* Now, the stack should be R8..R12, LR, PC and SR */ \ + "rete" \ + : \ + : [ulCriticalNesting] "i" (&ulCriticalNesting), \ + [pxCurrentTCB] "i" (&pxCurrentTCB), \ + [LINE] "i" (__LINE__) \ + ); \ +} + +#endif + + +/* + * portSAVE_CONTEXT_SCALL() for SupervisorCALL exception. + * + * NOTE: taskYIELD()(== SCALL) MUST NOT be called in a mode > supervisor mode. + * + */ +#define portSAVE_CONTEXT_SCALL() \ +{ \ + extern volatile unsigned portLONG ulCriticalNesting; \ + extern volatile void *volatile pxCurrentTCB; \ + \ + /* Warning: the stack layout after SCALL doesn't match the one after an interrupt. */ \ + /* If SR[M2:M0] == 001 */ \ + /* PC and SR are on the stack. */ \ + /* Else (other modes) */ \ + /* Nothing on the stack. */ \ + \ + /* WARNING NOTE: the else case cannot happen as it is strictly forbidden to call */ \ + /* vTaskDelay() and vTaskDelayUntil() OS functions (that result in a taskYield()) */ \ + /* in an interrupt|exception handler. */ \ + \ + __asm__ __volatile__ ( \ + /* in order to save R0-R7 */ \ + "sub sp, 6*4 \n\t"\ + /* Save R0..R7 */ \ + "stm --sp, r0-r7 \n\t"\ + \ + /* in order to save R8-R12 and LR */ \ + /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \ + "sub r7, sp,-16*4 \n\t"\ + /* Copy PC and SR in other places in the stack. */ \ + "ld.w r0, r7[-2*4] \n\t" /* Read SR */\ + "st.w r7[-8*4], r0 \n\t" /* Copy SR */\ + "ld.w r0, r7[-1*4] \n\t" /* Read PC */\ + "st.w r7[-7*4], r0 \n\t" /* Copy PC */\ + \ + /* Save R8..R12 and LR on the stack. */ \ + "stm --r7, r8-r12, lr \n\t"\ + \ + /* Arriving here we have the following stack organizations: */ \ + /* R8..R12, LR, PC, SR, R0..R7. */ \ + \ + /* Now we can finalize the save. */ \ + \ + /* Save ulCriticalNesting variable - R0 is overwritten */ \ + "mov r8, LO(%[ulCriticalNesting]) \n\t"\ + "orh r8, HI(%[ulCriticalNesting]) \n\t"\ + "ld.w r0, r8[0] \n\t"\ + "st.w --sp, r0" \ + : \ + : [ulCriticalNesting] "i" (&ulCriticalNesting) \ + ); \ + \ + /* Disable the its which may cause a context switch (i.e. cause a change of */ \ + /* pxCurrentTCB). */ \ + /* Basically, all accesses to the pxCurrentTCB structure should be put in a */ \ + /* critical section because it is a global structure. */ \ + portENTER_CRITICAL(); \ + \ + /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \ + __asm__ __volatile__ ( \ + "mov r8, LO(%[pxCurrentTCB]) \n\t"\ + "orh r8, HI(%[pxCurrentTCB]) \n\t"\ + "ld.w r0, r8[0] \n\t"\ + "st.w r0[0], sp" \ + : \ + : [pxCurrentTCB] "i" (&pxCurrentTCB) \ + ); \ +} + +/* + * portRESTORE_CONTEXT() for SupervisorCALL exception. + */ +#define portRESTORE_CONTEXT_SCALL() \ +{ \ + extern volatile unsigned portLONG ulCriticalNesting; \ + extern volatile void *volatile pxCurrentTCB; \ + \ + /* Restore all registers */ \ + \ + /* Set SP to point to new stack */ \ + __asm__ __volatile__ ( \ + "mov r8, LO(%[pxCurrentTCB]) \n\t"\ + "orh r8, HI(%[pxCurrentTCB]) \n\t"\ + "ld.w r0, r8[0] \n\t"\ + "ld.w sp, r0[0]" \ + : \ + : [pxCurrentTCB] "i" (&pxCurrentTCB) \ + ); \ + \ + /* Leave pxCurrentTCB variable access critical section */ \ + portEXIT_CRITICAL(); \ + \ + __asm__ __volatile__ ( \ + /* Restore ulCriticalNesting variable */ \ + "ld.w r0, sp++ \n\t"\ + "mov r8, LO(%[ulCriticalNesting]) \n\t"\ + "orh r8, HI(%[ulCriticalNesting]) \n\t"\ + "st.w r8[0], r0 \n\t"\ + \ + /* skip PC and SR */ \ + /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \ + "sub r7, sp, -10*4 \n\t"\ + /* Restore r8-r12 and LR */ \ + "ldm r7++, r8-r12, lr \n\t"\ + \ + /* RETS will take care of the extra PC and SR restore. */ \ + /* So, we have to prepare the stack for this. */ \ + "ld.w r0, r7[-8*4] \n\t" /* Read SR */\ + "st.w r7[-2*4], r0 \n\t" /* Copy SR */\ + "ld.w r0, r7[-7*4] \n\t" /* Read PC */\ + "st.w r7[-1*4], r0 \n\t" /* Copy PC */\ + \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t"\ + \ + "sub sp, -6*4 \n\t"\ + \ + "rets" \ + : \ + : [ulCriticalNesting] "i" (&ulCriticalNesting) \ + ); \ +} + + +/* + * The ISR used depends on whether the cooperative or + * the preemptive scheduler is being used. + */ +#if configUSE_PREEMPTION == 0 + +/* + * ISR entry and exit macros. These are only required if a task switch + * is required from the ISR. + */ +#define portENTER_SWITCHING_ISR() \ +{ \ + /* Save R0..R7 */ \ + __asm__ __volatile__ ("stm --sp, r0-r7"); \ + \ + /* With the cooperative scheduler, as there is no context switch by interrupt, */ \ + /* there is also no context save. */ \ +} + +/* + * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1 + */ +#define portEXIT_SWITCHING_ISR() \ +{ \ + __asm__ __volatile__ ( \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t"\ + \ + /* With the cooperative scheduler, as there is no context switch by interrupt, */ \ + /* there is also no context restore. */ \ + "rete" \ + ); \ +} + +#else + +/* + * ISR entry and exit macros. These are only required if a task switch + * is required from the ISR. + */ +#define portENTER_SWITCHING_ISR() \ +{ \ + extern volatile unsigned portLONG ulCriticalNesting; \ + extern volatile void *volatile pxCurrentTCB; \ + \ + /* When we come here */ \ + /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \ + \ + __asm__ __volatile__ ( \ + /* Save R0..R7 */ \ + "stm --sp, r0-r7 \n\t"\ + \ + /* Save ulCriticalNesting variable - R0 is overwritten */ \ + "mov r8, LO(%[ulCriticalNesting]) \n\t"\ + "orh r8, HI(%[ulCriticalNesting]) \n\t"\ + "ld.w r0, r8[0] \n\t"\ + "st.w --sp, r0 \n\t"\ + \ + /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \ + /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ + /* level and allow other lower interrupt level to occur). */ \ + /* In this case we don't want to do a task switch because we don't know what the stack */ \ + /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \ + /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \ + /* will just be restoring the interrupt handler, no way!!! */ \ + /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \ + "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\ + "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\ + "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\ + "brhi LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE] \n\t"\ + \ + /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \ + "mov r8, LO(%[pxCurrentTCB]) \n\t"\ + "orh r8, HI(%[pxCurrentTCB]) \n\t"\ + "ld.w r0, r8[0] \n\t"\ + "st.w r0[0], sp \n"\ + \ + "LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE]:" \ + : \ + : [ulCriticalNesting] "i" (&ulCriticalNesting), \ + [pxCurrentTCB] "i" (&pxCurrentTCB), \ + [LINE] "i" (__LINE__) \ + ); \ +} + +/* + * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1 + */ +#define portEXIT_SWITCHING_ISR() \ +{ \ + extern volatile unsigned portLONG ulCriticalNesting; \ + extern volatile void *volatile pxCurrentTCB; \ + \ + __asm__ __volatile__ ( \ + /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \ + /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ + /* level and allow other lower interrupt level to occur). */ \ + /* In this case it's of no use to switch context and restore a new SP because we purposedly */ \ + /* did not previously save SP in its TCB. */ \ + "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\ + "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\ + "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\ + "brhi LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE] \n\t"\ + \ + /* If a switch is required then we just need to call */ \ + /* vTaskSwitchContext() as the context has already been */ \ + /* saved. */ \ + "cp.w r12, 1 \n\t" /* Check if Switch context is required. */\ + "brne LABEL_ISR_RESTORE_CONTEXT_%[LINE]" \ + : \ + : [LINE] "i" (__LINE__) \ + ); \ + \ + /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */ \ + portENTER_CRITICAL(); \ + vTaskSwitchContext(); \ + portEXIT_CRITICAL(); \ + \ + __asm__ __volatile__ ( \ + "LABEL_ISR_RESTORE_CONTEXT_%[LINE]: \n\t"\ + /* Restore the context of which ever task is now the highest */ \ + /* priority that is ready to run. */ \ + \ + /* Restore all registers */ \ + \ + /* Set SP to point to new stack */ \ + "mov r8, LO(%[pxCurrentTCB]) \n\t"\ + "orh r8, HI(%[pxCurrentTCB]) \n\t"\ + "ld.w r0, r8[0] \n\t"\ + "ld.w sp, r0[0] \n"\ + \ + "LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE]: \n\t"\ + \ + /* Restore ulCriticalNesting variable */ \ + "ld.w r0, sp++ \n\t"\ + "mov r8, LO(%[ulCriticalNesting]) \n\t"\ + "orh r8, HI(%[ulCriticalNesting]) \n\t"\ + "st.w r8[0], r0 \n\t"\ + \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t"\ + \ + /* Now, the stack should be R8..R12, LR, PC and SR */ \ + "rete" \ + : \ + : [ulCriticalNesting] "i" (&ulCriticalNesting), \ + [pxCurrentTCB] "i" (&pxCurrentTCB), \ + [LINE] "i" (__LINE__) \ + ); \ +} + +#endif + + +#define portYIELD() {__asm__ __volatile__ ("scall");} + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ diff --git a/20080212/Source/portable/GCC/H8S2329/port.c b/20080212/Source/portable/GCC/H8S2329/port.c new file mode 100644 index 000000000..9e8d1230b --- /dev/null +++ b/20080212/Source/portable/GCC/H8S2329/port.c @@ -0,0 +1,316 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the H8S port. + *----------------------------------------------------------*/ + + +/*-----------------------------------------------------------*/ + +/* When the task starts interrupts should be enabled. */ +#define portINITIAL_CCR ( ( portSTACK_TYPE ) 0x00 ) + +/* Hardware specific constants used to generate the RTOS tick from the TPU. */ +#define portCLEAR_ON_TGRA_COMPARE_MATCH ( ( unsigned portCHAR ) 0x20 ) +#define portCLOCK_DIV_64 ( ( unsigned portCHAR ) 0x03 ) +#define portCLOCK_DIV ( ( unsigned portLONG ) 64 ) +#define portTGRA_INTERRUPT_ENABLE ( ( unsigned portCHAR ) 0x01 ) +#define portTIMER_CHANNEL ( ( unsigned portCHAR ) 0x02 ) +#define portMSTP13 ( ( unsigned portSHORT ) 0x2000 ) + +/* + * Setup TPU channel one for the RTOS tick at the requested frequency. + */ +static void prvSetupTimerInterrupt( void ); + +/* + * The ISR used by portYIELD(). This is installed as a trap handler. + */ +void vPortYield( void ) __attribute__ ( ( saveall, interrupt_handler ) ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ +unsigned portLONG ulValue; + + /* This requires an even address. */ + ulValue = ( unsigned portLONG ) pxTopOfStack; + if( ulValue & 1UL ) + { + pxTopOfStack = pxTopOfStack - 1; + } + + /* Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging. */ + pxTopOfStack--; + *pxTopOfStack = 0xaa; + pxTopOfStack--; + *pxTopOfStack = 0xbb; + pxTopOfStack--; + *pxTopOfStack = 0xcc; + pxTopOfStack--; + *pxTopOfStack = 0xdd; + + /* The initial stack mimics an interrupt stack. First there is the program + counter (24 bits). */ + ulValue = ( unsigned portLONG ) pxCode; + + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) ( ulValue & 0xff ); + pxTopOfStack--; + ulValue >>= 8UL; + *pxTopOfStack = ( portSTACK_TYPE ) ( ulValue & 0xff ); + pxTopOfStack--; + ulValue >>= 8UL; + *pxTopOfStack = ( portSTACK_TYPE ) ( ulValue & 0xff ); + + /* Followed by the CCR. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_CCR; + + /* Next all the general purpose registers - with the parameters being passed + in ER0. The parameter order must match that used by the compiler when the + "saveall" function attribute is used. */ + + /* ER6 */ + pxTopOfStack--; + *pxTopOfStack = 0x66; + pxTopOfStack--; + *pxTopOfStack = 0x66; + pxTopOfStack--; + *pxTopOfStack = 0x66; + pxTopOfStack--; + *pxTopOfStack = 0x66; + + /* ER0 */ + ulValue = ( unsigned portLONG ) pvParameters; + + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) ( ulValue & 0xff ); + pxTopOfStack--; + ulValue >>= 8UL; + *pxTopOfStack = ( portSTACK_TYPE ) ( ulValue & 0xff ); + pxTopOfStack--; + ulValue >>= 8UL; + *pxTopOfStack = ( portSTACK_TYPE ) ( ulValue & 0xff ); + pxTopOfStack--; + ulValue >>= 8UL; + *pxTopOfStack = ( portSTACK_TYPE ) ( ulValue & 0xff ); + + /* ER1 */ + pxTopOfStack--; + *pxTopOfStack = 0x11; + pxTopOfStack--; + *pxTopOfStack = 0x11; + pxTopOfStack--; + *pxTopOfStack = 0x11; + pxTopOfStack--; + *pxTopOfStack = 0x11; + + /* ER2 */ + pxTopOfStack--; + *pxTopOfStack = 0x22; + pxTopOfStack--; + *pxTopOfStack = 0x22; + pxTopOfStack--; + *pxTopOfStack = 0x22; + pxTopOfStack--; + *pxTopOfStack = 0x22; + + /* ER3 */ + pxTopOfStack--; + *pxTopOfStack = 0x33; + pxTopOfStack--; + *pxTopOfStack = 0x33; + pxTopOfStack--; + *pxTopOfStack = 0x33; + pxTopOfStack--; + *pxTopOfStack = 0x33; + + /* ER4 */ + pxTopOfStack--; + *pxTopOfStack = 0x44; + pxTopOfStack--; + *pxTopOfStack = 0x44; + pxTopOfStack--; + *pxTopOfStack = 0x44; + pxTopOfStack--; + *pxTopOfStack = 0x44; + + /* ER5 */ + pxTopOfStack--; + *pxTopOfStack = 0x55; + pxTopOfStack--; + *pxTopOfStack = 0x55; + pxTopOfStack--; + *pxTopOfStack = 0x55; + pxTopOfStack--; + *pxTopOfStack = 0x55; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xPortStartScheduler( void ) +{ +extern void * pxCurrentTCB; + + /* Setup the hardware to generate the tick. */ + prvSetupTimerInterrupt(); + + /* Restore the context of the first task that is going to run. This + mirrors the function epilogue code generated by the compiler when the + "saveall" function attribute is used. */ + asm volatile ( + "MOV.L @_pxCurrentTCB, ER6 \n\t" + "MOV.L @ER6, ER7 \n\t" + "LDM.L @SP+, (ER4-ER5) \n\t" + "LDM.L @SP+, (ER0-ER3) \n\t" + "MOV.L @ER7+, ER6 \n\t" + "RTE \n\t" + ); + + ( void ) pxCurrentTCB; + + /* Should not get here. */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the h8 port will get stopped. */ +} +/*-----------------------------------------------------------*/ + +/* + * Manual context switch. This is a trap handler. The "saveall" function + * attribute is used so the context is saved by the compiler prologue. All + * we have to do is save the stack pointer. + */ +void vPortYield( void ) +{ + portSAVE_STACK_POINTER(); + vTaskSwitchContext(); + portRESTORE_STACK_POINTER(); +} +/*-----------------------------------------------------------*/ + +/* + * The interrupt handler installed for the RTOS tick depends on whether the + * preemptive or cooperative scheduler is being used. + */ +#if( configUSE_PREEMPTION == 1 ) + + /* + * The preemptive scheduler is used so the ISR calls vTaskSwitchContext(). + * The function prologue saves the context so all we have to do is save + * the stack pointer. + */ + void vTickISR( void ) __attribute__ ( ( saveall, interrupt_handler ) ); + void vTickISR( void ) + { + portSAVE_STACK_POINTER(); + + vTaskIncrementTick(); + vTaskSwitchContext(); + + /* Clear the interrupt. */ + TSR1 &= ~0x01; + + portRESTORE_STACK_POINTER(); + } + +#else + + /* + * The cooperative scheduler is being used so all we have to do is + * periodically increment the tick. This can just be a normal ISR and + * the "saveall" attribute is not required. + */ + void vTickISR( void ) __attribute__ ( ( interrupt_handler ) ); + void vTickISR( void ) + { + vTaskIncrementTick(); + + /* Clear the interrupt. */ + TSR1 &= ~0x01; + } + +#endif +/*-----------------------------------------------------------*/ + +/* + * Setup timer 1 compare match to generate a tick interrupt. + */ +static void prvSetupTimerInterrupt( void ) +{ +const unsigned portLONG ulCompareMatch = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) / portCLOCK_DIV; + + /* Turn the module on. */ + MSTPCR &= ~portMSTP13; + + /* Configure timer 1. */ + TCR1 = portCLEAR_ON_TGRA_COMPARE_MATCH | portCLOCK_DIV_64; + + /* Configure the compare match value for a tick of configTICK_RATE_HZ. */ + TGR1A = ulCompareMatch; + + /* Start the timer and enable the interrupt - we can do this here as + interrupts are globally disabled when this function is called. */ + TIER1 |= portTGRA_INTERRUPT_ENABLE; + TSTR |= portTIMER_CHANNEL; +} +/*-----------------------------------------------------------*/ + + + diff --git a/20080212/Source/portable/GCC/H8S2329/portmacro.h b/20080212/Source/portable/GCC/H8S2329/portmacro.h new file mode 100644 index 000000000..d0ac16be4 --- /dev/null +++ b/20080212/Source/portable/GCC/H8S2329/portmacro.h @@ -0,0 +1,149 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned portCHAR +#define portBASE_TYPE char + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 2 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portYIELD() asm volatile( "TRAPA #0" ) +#define portNOP() asm volatile( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +#define portENABLE_INTERRUPTS() asm volatile( "ANDC #0x7F, CCR" ); +#define portDISABLE_INTERRUPTS() asm volatile( "ORC #0x80, CCR" ); + +/* Push the CCR then disable interrupts. */ +#define portENTER_CRITICAL() asm volatile( "STC CCR, @-ER7" ); \ + portDISABLE_INTERRUPTS(); + +/* Pop the CCR to set the interrupt masking back to its previous state. */ +#define portEXIT_CRITICAL() asm volatile( "LDC @ER7+, CCR" ); +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* Context switch macros. These macros are very simple as the context +is saved simply by selecting the saveall attribute of the context switch +interrupt service routines. These macros save and restore the stack +pointer to the TCB. */ + +#define portSAVE_STACK_POINTER() \ +extern void* pxCurrentTCB; \ + \ + asm volatile( \ + "MOV.L @_pxCurrentTCB, ER5 \n\t" \ + "MOV.L ER7, @ER5 \n\t" \ + ); \ + ( void ) pxCurrentTCB; + + +#define portRESTORE_STACK_POINTER() \ +extern void* pxCurrentTCB; \ + \ + asm volatile( \ + "MOV.L @_pxCurrentTCB, ER5 \n\t" \ + "MOV.L @ER5, ER7 \n\t" \ + ); \ + ( void ) pxCurrentTCB; + +/*-----------------------------------------------------------*/ + +/* Macros to allow a context switch from within an application ISR. */ + +#define portENTER_SWITCHING_ISR() portSAVE_STACK_POINTER(); { + +#define portEXIT_SWITCHING_ISR( x ) \ + if( x ) \ + { \ + extern void vTaskSwitchContext( void ); \ + vTaskSwitchContext(); \ + } \ + } portRESTORE_STACK_POINTER(); +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/20080212/Source/portable/GCC/HCS12/port.c b/20080212/Source/portable/GCC/HCS12/port.c new file mode 100644 index 000000000..0f8e2bbd0 --- /dev/null +++ b/20080212/Source/portable/GCC/HCS12/port.c @@ -0,0 +1,252 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* GCC/HCS12 port by Jefferson L Smith, 2005 */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Port includes */ +#include + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the HCS12 port. + *----------------------------------------------------------*/ + + +/* + * Configure a timer to generate the RTOS tick at the frequency specified + * within FreeRTOSConfig.h. + */ +static void prvSetupTimerInterrupt( void ); + +/* NOTE: Interrupt service routines must be in non-banked memory - as does the +scheduler startup function. */ +#define ATTR_NEAR __attribute__((near)) + +/* Manual context switch function. This is the SWI ISR. */ +// __attribute__((interrupt)) +void ATTR_NEAR vPortYield( void ); + +/* Tick context switch function. This is the timer ISR. */ +// __attribute__((interrupt)) +void ATTR_NEAR vPortTickInterrupt( void ); + +/* Function in non-banked memory which actually switches to first task. */ +portBASE_TYPE ATTR_NEAR xStartSchedulerNear( void ); + +/* Calls to portENTER_CRITICAL() can be nested. When they are nested the +critical section should not be left (i.e. interrupts should not be re-enabled) +until the nesting depth reaches 0. This variable simply tracks the nesting +depth. Each task maintains it's own critical nesting depth variable so +uxCriticalNesting is saved and restored from the task stack during a context +switch. */ +volatile unsigned portBASE_TYPE uxCriticalNesting = 0x80; // un-initialized + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ + + + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. In this case the stack as + expected by the HCS12 RTI instruction. */ + + + /* The address of the task function is placed in the stack byte at a time. */ + *pxTopOfStack = ( portSTACK_TYPE ) *( ((portSTACK_TYPE *) (&pxCode) ) + 1 ); + *--pxTopOfStack = ( portSTACK_TYPE ) *( ((portSTACK_TYPE *) (&pxCode) ) + 0 ); + + /* Next are all the registers that form part of the task context. */ + + /* Y register */ + *--pxTopOfStack = ( portSTACK_TYPE ) 0xff; + *--pxTopOfStack = ( portSTACK_TYPE ) 0xee; + + /* X register */ + *--pxTopOfStack = ( portSTACK_TYPE ) 0xdd; + *--pxTopOfStack = ( portSTACK_TYPE ) 0xcc; + + /* A register contains parameter high byte. */ + *--pxTopOfStack = ( portSTACK_TYPE ) *( ((portSTACK_TYPE *) (&pvParameters) ) + 0 ); + + /* B register contains parameter low byte. */ + *--pxTopOfStack = ( portSTACK_TYPE ) *( ((portSTACK_TYPE *) (&pvParameters) ) + 1 ); + + /* CCR: Note that when the task starts interrupts will be enabled since + "I" bit of CCR is cleared */ + *--pxTopOfStack = ( portSTACK_TYPE ) 0x80; // keeps Stop disabled (MCU default) + + /* tmp softregs used by GCC. Values right now don't matter. */ + __asm("\n\ + movw _.frame, 2,-%0 \n\ + movw _.tmp, 2,-%0 \n\ + movw _.z, 2,-%0 \n\ + movw _.xy, 2,-%0 \n\ + ;movw _.d2, 2,-%0 \n\ + ;movw _.d1, 2,-%0 \n\ + ": "=A"(pxTopOfStack) : "0"(pxTopOfStack) ); + + #ifdef BANKED_MODEL + /* The page of the task. */ + *--pxTopOfStack = 0x30; // can only directly start in PPAGE 0x30 + #endif + + /* The critical nesting depth is initialised with 0 (meaning not in + a critical section). */ + *--pxTopOfStack = ( portSTACK_TYPE ) 0x00; + + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the HCS12 port will get stopped. */ +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ + /* Enable hardware RTI timer */ + /* Ignores configTICK_RATE_HZ */ + RTICTL = 0x50; // 16 MHz xtal: 976.56 Hz, 1024mS + CRGINT |= 0x80; // RTIE +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xPortStartScheduler( void ) +{ + /* xPortStartScheduler() does not start the scheduler directly because + the header file containing the xPortStartScheduler() prototype is part + of the common kernel code, and therefore cannot use the CODE_SEG pragma. + Instead it simply calls the locally defined xNearStartScheduler() - + which does use the CODE_SEG pragma. */ + + short register d; + __asm ("jmp xStartSchedulerNear ; will never return": "=d"(d)); + return d; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xStartSchedulerNear( void ) +{ + /* Configure the timer that will generate the RTOS tick. Interrupts are + disabled when this function is called. */ + prvSetupTimerInterrupt(); + + /* Restore the context of the first task. */ + portRESTORE_CONTEXT(); + + portISR_TAIL(); + + /* Should not get here! */ + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +/* + * Context switch functions. These are interrupt service routines. + */ + +/* + * Manual context switch forced by calling portYIELD(). This is the SWI + * handler. + */ +void vPortYield( void ) +{ + portISR_HEAD(); + /* NOTE: This is the trap routine (swi) although not defined as a trap. + It will fill the stack the same way as an ISR in order to mix preemtion + and cooperative yield. */ + + portSAVE_CONTEXT(); + vTaskSwitchContext(); + portRESTORE_CONTEXT(); + + portISR_TAIL(); +} +/*-----------------------------------------------------------*/ + +/* + * RTOS tick interrupt service routine. If the cooperative scheduler is + * being used then this simply increments the tick count. If the + * preemptive scheduler is being used a context switch can occur. + */ +void vPortTickInterrupt( void ) +{ + portISR_HEAD(); + + /* Clear tick timer flag */ + CRGFLG = 0x80; + + #if configUSE_PREEMPTION == 1 + { + /* A context switch might happen so save the context. */ + portSAVE_CONTEXT(); + + /* Increment the tick ... */ + vTaskIncrementTick(); + + /* ... then see if the new tick value has necessitated a + context switch. */ + vTaskSwitchContext(); + + /* Restore the context of a task - which may be a different task + to that interrupted. */ + portRESTORE_CONTEXT(); + } + #else + { + vTaskIncrementTick(); + } + #endif + + portISR_TAIL(); +} + diff --git a/20080212/Source/portable/GCC/HCS12/portmacro.h b/20080212/Source/portable/GCC/HCS12/portmacro.h new file mode 100644 index 000000000..72ce1500e --- /dev/null +++ b/20080212/Source/portable/GCC/HCS12/portmacro.h @@ -0,0 +1,256 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned portCHAR +#define portBASE_TYPE char + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 1 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portYIELD() __asm( "swi" ); +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +#define portENABLE_INTERRUPTS() __asm( "cli" ) +#define portDISABLE_INTERRUPTS() __asm( "sei" ) + +/* + * Disable interrupts before incrementing the count of critical section nesting. + * The nesting count is maintained so we know when interrupts should be + * re-enabled. Once interrupts are disabled the nesting count can be accessed + * directly. Each task maintains its own nesting count. + */ +#define portENTER_CRITICAL() \ +{ \ + extern volatile unsigned portBASE_TYPE uxCriticalNesting; \ + \ + portDISABLE_INTERRUPTS(); \ + uxCriticalNesting++; \ +} + +/* + * Interrupts are disabled so we can access the nesting count directly. If the + * nesting is found to be 0 (no nesting) then we are leaving the critical + * section and interrupts can be re-enabled. + */ +#define portEXIT_CRITICAL() \ +{ \ + extern volatile unsigned portBASE_TYPE uxCriticalNesting; \ + \ + uxCriticalNesting--; \ + if( uxCriticalNesting == 0 ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ +} +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* + * These macros are very simple as the processor automatically saves and + * restores its registers as interrupts are entered and exited. In + * addition to the (automatically stacked) registers we also stack the + * critical nesting count. Each task maintains its own critical nesting + * count as it is legitimate for a task to yield from within a critical + * section. If the banked memory model is being used then the PPAGE + * register is also stored as part of the tasks context. + */ + +#ifdef BANKED_MODEL + /* + * Load the stack pointer for the task, then pull the critical nesting + * count and PPAGE register from the stack. The remains of the + * context are restored by the RTI instruction. + */ + #define portRESTORE_CONTEXT() \ + { \ + __asm( " \n\ + .globl pxCurrentTCB ; void * \n\ + .globl uxCriticalNesting ; char \n\ + \n\ + ldx pxCurrentTCB \n\ + lds 0,x ; Stack \n\ + \n\ + movb 1,sp+,uxCriticalNesting \n\ + movb 1,sp+,0x30 ; PPAGE \n\ + " ); \ + } + + /* + * By the time this macro is called the processor has already stacked the + * registers. Simply stack the nesting count and PPAGE value, then save + * the task stack pointer. + */ + #define portSAVE_CONTEXT() \ + { \ + __asm( " \n\ + .globl pxCurrentTCB ; void * \n\ + .globl uxCriticalNesting ; char \n\ + \n\ + movb 0x30, 1,-sp ; PPAGE \n\ + movb uxCriticalNesting, 1,-sp \n\ + \n\ + ldx pxCurrentTCB \n\ + sts 0,x ; Stack \n\ + " ); \ + } +#else + + /* + * These macros are as per the BANKED versions above, but without saving + * and restoring the PPAGE register. + */ + + #define portRESTORE_CONTEXT() \ + { \ + __asm( " \n\ + .globl pxCurrentTCB ; void * \n\ + .globl uxCriticalNesting ; char \n\ + \n\ + ldx pxCurrentTCB \n\ + lds 0,x ; Stack \n\ + \n\ + movb 1,sp+,uxCriticalNesting \n\ + " ); \ + } + + #define portSAVE_CONTEXT() \ + { \ + __asm( " \n\ + .globl pxCurrentTCB ; void * \n\ + .globl uxCriticalNesting ; char \n\ + \n\ + movb uxCriticalNesting, 1,-sp \n\ + \n\ + ldx pxCurrentTCB \n\ + sts 0,x ; Stack \n\ + " ); \ + } +#endif + +/* + * Utility macros to save/restore correct software registers for GCC. This is + * useful when GCC does not generate appropriate ISR head/tail code. + */ +#define portISR_HEAD() \ +{ \ + __asm(" \n\ + movw _.frame, 2,-sp \n\ + movw _.tmp, 2,-sp \n\ + movw _.z, 2,-sp \n\ + movw _.xy, 2,-sp \n\ + ;movw _.d2, 2,-sp \n\ + ;movw _.d1, 2,-sp \n\ + "); \ +} + +#define portISR_TAIL() \ +{ \ + __asm(" \n\ + movw 2,sp+, _.xy \n\ + movw 2,sp+, _.z \n\ + movw 2,sp+, _.tmp \n\ + movw 2,sp+, _.frame \n\ + ;movw 2,sp+, _.d1 \n\ + ;movw 2,sp+, _.d2 \n\ + rti \n\ + "); \ +} + +/* + * Utility macro to call macros above in correct order in order to perform a + * task switch from within a standard ISR. This macro can only be used if + * the ISR does not use any local (stack) variables. If the ISR uses stack + * variables portYIELD() should be used in it's place. + */ + +#define portTASK_SWITCH_FROM_ISR() \ + portSAVE_CONTEXT(); \ + vTaskSwitchContext(); \ + portRESTORE_CONTEXT(); + + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/20080212/Source/portable/GCC/MCF5235/port.c b/20080212/Source/portable/GCC/MCF5235/port.c new file mode 100644 index 000000000..9012f57e8 --- /dev/null +++ b/20080212/Source/portable/GCC/MCF5235/port.c @@ -0,0 +1,273 @@ +/* + FreeRTOS V4.1.1 - Copyright (C) 2003-2006 Richard Barry. + MCF5235 Port - Copyright (C) 2006 Christian Walter. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#include + +#include "FreeRTOS.h" +#include "FreeRTOSConfig.h" +#include "task.h" + +/* ------------------------ Types ----------------------------------------- */ +typedef volatile unsigned long vuint32; +typedef volatile unsigned short vuint16; +typedef volatile unsigned char vuint8; + +/* ------------------------ Defines --------------------------------------- */ +#define portVECTOR_TABLE __RAMVEC +#define portVECTOR_SYSCALL ( 32 + portTRAP_YIELD ) +#define portVECTOR_TIMER ( 64 + 36 ) + +#define MCF_PIT_PRESCALER 512UL +#define MCF_PIT_TIMER_TICKS ( FSYS_2 / MCF_PIT_PRESCALER ) +#define MCF_PIT_MODULUS_REGISTER(freq) ( MCF_PIT_TIMER_TICKS / ( freq ) - 1UL) + +#define MCF_PIT_PMR0 ( *( vuint16 * )( void * )( &__IPSBAR[ 0x150002 ] ) ) +#define MCF_PIT_PCSR0 ( *( vuint16 * )( void * )( &__IPSBAR[ 0x150000 ] ) ) +#define MCF_PIT_PCSR_PRE(x) ( ( ( x ) & 0x000F ) << 8 ) +#define MCF_PIT_PCSR_EN ( 0x0001 ) +#define MCF_PIT_PCSR_RLD ( 0x0002 ) +#define MCF_PIT_PCSR_PIF ( 0x0004 ) +#define MCF_PIT_PCSR_PIE ( 0x0008 ) +#define MCF_PIT_PCSR_OVW ( 0x0010 ) +#define MCF_INTC0_ICR36 ( *( vuint8 * )( void * )( &__IPSBAR[ 0x000C64 ] ) ) +#define MCF_INTC0_IMRH ( *( vuint32 * )( void * )( &__IPSBAR[ 0x000C08 ] ) ) +#define MCF_INTC0_IMRH_INT_MASK36 ( 0x00000010 ) +#define MCF_INTC0_IMRH_MASKALL ( 0x00000001 ) +#define MCF_INTC0_ICRn_IP(x) ( ( ( x ) & 0x07 ) << 0 ) +#define MCF_INTC0_ICRn_IL(x) ( ( ( x ) & 0x07 ) << 3 ) + +#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 ) +#define portINITIAL_CRITICAL_NESTING ( ( unsigned portLONG ) 10 ) + +/* ------------------------ Static variables ------------------------------ */ +volatile unsigned portLONG ulCriticalNesting = portINITIAL_CRITICAL_NESTING; + +/* ------------------------ Static functions ------------------------------ */ +#if configUSE_PREEMPTION == 0 +static void prvPortPreemptiveTick ( void ) __attribute__ ((interrupt_handler)); +#else +static void prvPortPreemptiveTick ( void ); +#endif + +/* ------------------------ Start implementation -------------------------- */ + +portSTACK_TYPE * +pxPortInitialiseStack( portSTACK_TYPE * pxTopOfStack, pdTASK_CODE pxCode, + void *pvParameters ) +{ + /* Place the parameter on the stack in the expected location. */ + *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; + pxTopOfStack--; + + /* Place dummy return address on stack. Tasks should never terminate so + * we can set this to anything. */ + *pxTopOfStack = ( portSTACK_TYPE ) 0; + pxTopOfStack--; + + /* Create a Motorola Coldfire exception stack frame. First comes the return + * address. */ + *pxTopOfStack = ( portSTACK_TYPE ) pxCode; + pxTopOfStack--; + + /* Format, fault-status, vector number for exception stack frame. Task + * run in supervisor mode. */ + *pxTopOfStack = 0x40002000UL | ( portVECTOR_SYSCALL + 32 ) << 18; + pxTopOfStack--; + + /* Set the initial critical section nesting counter to zero. This value + * is used to restore the value of ulCriticalNesting. */ + *pxTopOfStack = 0; + *pxTopOfStack--; + + *pxTopOfStack = ( portSTACK_TYPE ) 0xA6; /* A6 / FP */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xA5; /* A5 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xA4; /* A4 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xA3; /* A3 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xA2; /* A2 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xA1; /* A1 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xA0; /* A0 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xD7; /* D7 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xD6; /* D6 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xD5; /* D5 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xD4; /* D4 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xD3; /* D3 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xD2; /* D2 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xD1; /* D1 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xD0; /* D0 */ + + return pxTopOfStack; +} + +/* + * Called by portYIELD() or taskYIELD() to manually force a context switch. + */ +static void +prvPortYield( void ) +{ + asm volatile ( "move.w #0x2700, %sr\n\t" ); +#if _GCC_USES_FP == 1 + asm volatile ( "unlk %fp\n\t" ); +#endif + /* Perform the context switch. First save the context of the current task. */ + portSAVE_CONTEXT( ); + + /* Find the highest priority task that is ready to run. */ + vTaskSwitchContext( ); + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT( ); +} + +#if configUSE_PREEMPTION == 0 +/* + * The ISR used for the scheduler tick depends on whether the cooperative or + * the preemptive scheduler is being used. + */ +static void +prvPortPreemptiveTick ( void ) +{ + /* The cooperative scheduler requires a normal IRQ service routine to + * simply increment the system tick. + */ + + vTaskIncrementTick( ); + MCF_PIT_PCSR0 |= MCF_PIT_PCSR_PIF; +} + +#else + +static void +prvPortPreemptiveTick( void ) +{ + asm volatile ( "move.w #0x2700, %sr\n\t" ); +#if _GCC_USES_FP == 1 + asm volatile ( "unlk %fp\n\t" ); +#endif + portSAVE_CONTEXT( ); + MCF_PIT_PCSR0 |= MCF_PIT_PCSR_PIF; + vTaskIncrementTick( ); + vTaskSwitchContext( ); + portRESTORE_CONTEXT( ); +} +#endif + +void +vPortEnterCritical() +{ + /* FIXME: We should store the old IPL here - How are we supposed to do + * this. + */ + ( void )portSET_IPL( portIPL_MAX ); + + /* Now interrupts are disabled ulCriticalNesting can be accessed + * directly. Increment ulCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} + +void +vPortExitCritical() +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + ( void )portSET_IPL( 0 ); + } + } +} + +portBASE_TYPE +xPortStartScheduler( void ) +{ + extern void ( *portVECTOR_TABLE[ ] ) ( ); + + /* Add entry in vector table for yield system call. */ + portVECTOR_TABLE[ portVECTOR_SYSCALL ] = prvPortYield; + /* Add entry in vector table for periodic timer. */ + portVECTOR_TABLE[ portVECTOR_TIMER ] = prvPortPreemptiveTick; + + /* Configure the timer for the system clock. */ + if ( configTICK_RATE_HZ > 0) + { + /* Configure prescaler */ + MCF_PIT_PCSR0 = MCF_PIT_PCSR_PRE( 0x9 ) | MCF_PIT_PCSR_RLD | MCF_PIT_PCSR_OVW; + /* Initialize the periodic timer interrupt. */ + MCF_PIT_PMR0 = MCF_PIT_MODULUS_REGISTER( configTICK_RATE_HZ ); + /* Configure interrupt priority and level and unmask interrupt. */ + MCF_INTC0_ICR36 = MCF_INTC0_ICRn_IL( 0x1 ) | MCF_INTC0_ICRn_IP( 0x1 ); + MCF_INTC0_IMRH &= ~( MCF_INTC0_IMRH_INT_MASK36 | MCF_INTC0_IMRH_MASKALL ); + /* Enable interrupts */ + MCF_PIT_PCSR0 |= MCF_PIT_PCSR_PIE | MCF_PIT_PCSR_EN | MCF_PIT_PCSR_PIF; + } + + /* Restore the context of the first task that is going to run. */ + portRESTORE_CONTEXT( ); + + /* Should not get here. */ + return pdTRUE; +} + +void +vPortEndScheduler( void ) +{ +} diff --git a/20080212/Source/portable/GCC/MCF5235/portmacro.h b/20080212/Source/portable/GCC/MCF5235/portmacro.h new file mode 100644 index 000000000..47d05fdd7 --- /dev/null +++ b/20080212/Source/portable/GCC/MCF5235/portmacro.h @@ -0,0 +1,168 @@ +/* + FreeRTOS V4.1.1 - Copyright (C) 2003-2006 Richard Barry. + MCF5235 Port - Copyright (C) 2006 Christian Walter. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* ------------------------ Data types for Coldfire ----------------------- */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned int +#define portBASE_TYPE int + +#if( USE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif + +/* ------------------------ Architecture specifics ------------------------ */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 4 + +#define portTRAP_YIELD 0 /* Trap 0 */ +#define portIPL_MAX 7 /* Only NMI interrupt 7 allowed. */ + +/* ------------------------ FreeRTOS macros for port ---------------------- */ + +/* + * This function must be called when the current state of the active task + * should be stored. It must be called immediately after exception + * processing from the CPU, i.e. there exists a Coldfire exception frame at + * the current position in the stack. The function reserves space on + * the stack for the CPU registers and other task dependent values (e.g + * ulCriticalNesting) and updates the top of the stack in the TCB. + */ +#define portSAVE_CONTEXT() \ + asm volatile ( /* reserve space for task state. */ \ + "lea.l (-64, %sp), %sp\n\t" \ + /* push data register %d0-%d7/%a0-%a6 on stack. */ \ + "movem.l %d0-%d7/%a0-%a6, (%sp)\n\t" \ + /* push ulCriticalNesting counter on stack. */ \ + "lea.l (60, %sp), %a0\n\t" \ + "move.l ulCriticalNesting, (%a0)\n\t" \ + /* set the new top of the stack in the TCB. */ \ + "move.l pxCurrentTCB, %a0\n\t" \ + "move.l %sp, (%a0)"); + +/*. + * This function restores the current active and continues its execution. + * It loads the current TCB and restores the processor registers, the + * task dependent values (e.g ulCriticalNesting). Finally execution + * is continued by executing an rte instruction. + */ +#define portRESTORE_CONTEXT() \ + asm volatile ( "move.l pxCurrentTCB, %sp\n\t" \ + "move.l (%sp), %sp\n\t" \ + /* stack pointer now points to the saved registers. */ \ + "movem.l (%sp), %d0-%d7/%a0-%a6\n\t" \ + /* restore ulCriticalNesting counter from stack. */ \ + "lea.l (%sp, 60), %sp\n\t" \ + "move.l (%sp)+, ulCriticalNesting\n\t" \ + /* stack pointer now points to exception frame. */ \ + "rte\n\t" ); + +#define portENTER_CRITICAL() \ + vPortEnterCritical(); + +#define portEXIT_CRITICAL() \ + vPortExitCritical(); + +#define portSET_IPL( xIPL ) \ + asm_set_ipl( xIPL ) + +#define portDISABLE_INTERRUPTS() \ + do { ( void )portSET_IPL( portIPL_MAX ); } while( 0 ) +#define portENABLE_INTERRUPTS() \ + do { ( void )portSET_IPL( 0 ); } while( 0 ) + +#define portYIELD() \ + asm volatile ( " trap %0\n\t" : : "i"(portTRAP_YIELD) ) + +#define portNOP() \ + asm volatile ( "nop\n\t" ) + +#define portENTER_SWITCHING_ISR() \ + asm volatile ( "move.w #0x2700, %sr" ); \ + /* Save the context of the interrupted task. */ \ + portSAVE_CONTEXT( ); \ + { + +#define portEXIT_SWITCHING_ISR( SwitchRequired ) \ + /* If a switch is required we call vTaskSwitchContext(). */ \ + if( SwitchRequired ) \ + { \ + vTaskSwitchContext( ); \ + } \ + } \ + portRESTORE_CONTEXT( ); + +/* ------------------------ Function prototypes --------------------------- */ +void vPortEnterCritical( void ); +void vPortExitCritical( void ); +int asm_set_ipl( unsigned long int uiNewIPL ); + +/* ------------------------ Compiler specifics ---------------------------- */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) \ + void vFunction( void *pvParameters ) + +#define portTASK_FUNCTION( vFunction, pvParameters ) \ + void vFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif + + +#endif /* PORTMACRO_H */ + diff --git a/20080212/Source/portable/GCC/MSP430F449/port.c b/20080212/Source/portable/GCC/MSP430F449/port.c new file mode 100644 index 000000000..90e66851e --- /dev/null +++ b/20080212/Source/portable/GCC/MSP430F449/port.c @@ -0,0 +1,337 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + Changes from V2.5.2 + + + usCriticalNesting now has a volatile qualifier. +*/ + +/* Standard includes. */ +#include +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the MSP430 port. + *----------------------------------------------------------*/ + +/* Constants required for hardware setup. The tick ISR runs off the ACLK, +not the MCLK. */ +#define portACLK_FREQUENCY_HZ ( ( portTickType ) 32768 ) +#define portINITIAL_CRITICAL_NESTING ( ( unsigned portSHORT ) 10 ) +#define portFLAGS_INT_ENABLED ( ( portSTACK_TYPE ) 0x08 ) + +/* We require the address of the pxCurrentTCB variable, but don't want to know +any details of its type. */ +typedef void tskTCB; +extern volatile tskTCB * volatile pxCurrentTCB; + +/* Most ports implement critical sections by placing the interrupt flags on +the stack before disabling interrupts. Exiting the critical section is then +simply a case of popping the flags from the stack. As mspgcc does not use +a frame pointer this cannot be done as modifying the stack will clobber all +the stack variables. Instead each task maintains a count of the critical +section nesting depth. Each time a critical section is entered the count is +incremented. Each time a critical section is left the count is decremented - +with interrupts only being re-enabled if the count is zero. + +usCriticalNesting will get set to zero when the scheduler starts, but must +not be initialised to zero as this will cause problems during the startup +sequence. */ +volatile unsigned portSHORT usCriticalNesting = portINITIAL_CRITICAL_NESTING; +/*-----------------------------------------------------------*/ + +/* + * Macro to save a task context to the task stack. This simply pushes all the + * general purpose msp430 registers onto the stack, followed by the + * usCriticalNesting value used by the task. Finally the resultant stack + * pointer value is saved into the task control block so it can be retrieved + * the next time the task executes. + */ +#define portSAVE_CONTEXT() \ + asm volatile ( "push r4 \n\t" \ + "push r5 \n\t" \ + "push r6 \n\t" \ + "push r7 \n\t" \ + "push r8 \n\t" \ + "push r9 \n\t" \ + "push r10 \n\t" \ + "push r11 \n\t" \ + "push r12 \n\t" \ + "push r13 \n\t" \ + "push r14 \n\t" \ + "push r15 \n\t" \ + "mov.w usCriticalNesting, r14 \n\t" \ + "push r14 \n\t" \ + "mov.w pxCurrentTCB, r12 \n\t" \ + "mov.w r1, @r12 \n\t" \ + ); + +/* + * Macro to restore a task context from the task stack. This is effectively + * the reverse of portSAVE_CONTEXT(). First the stack pointer value is + * loaded from the task control block. Next the value for usCriticalNesting + * used by the task is retrieved from the stack - followed by the value of all + * the general purpose msp430 registers. + */ +#define portRESTORE_CONTEXT() \ + asm volatile ( "mov.w pxCurrentTCB, r12 \n\t" \ + "mov.w @r12, r1 \n\t" \ + "pop r15 \n\t" \ + "mov.w r15, usCriticalNesting \n\t" \ + "pop r15 \n\t" \ + "pop r14 \n\t" \ + "pop r13 \n\t" \ + "pop r12 \n\t" \ + "pop r11 \n\t" \ + "pop r10 \n\t" \ + "pop r9 \n\t" \ + "pop r8 \n\t" \ + "pop r7 \n\t" \ + "pop r6 \n\t" \ + "pop r5 \n\t" \ + "pop r4 \n\t" \ + "reti \n\t" \ + ); +/*-----------------------------------------------------------*/ + +/* + * Sets up the periodic ISR used for the RTOS tick. This uses timer 0, but + * could have alternatively used the watchdog timer or timer 1. + */ +static void prvSetupTimerInterrupt( void ); +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See the header file portable.h. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ + /* + Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging and can be included if required. + + *pxTopOfStack = ( portSTACK_TYPE ) 0x1111; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x2222; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x3333; + pxTopOfStack--; + */ + + /* The msp430 automatically pushes the PC then SR onto the stack before + executing an ISR. We want the stack to look just as if this has happened + so place a pointer to the start of the task on the stack first - followed + by the flags we want the task to use when it starts up. */ + *pxTopOfStack = ( portSTACK_TYPE ) pxCode; + pxTopOfStack--; + *pxTopOfStack = portFLAGS_INT_ENABLED; + pxTopOfStack--; + + /* Next the general purpose registers. */ + *pxTopOfStack = ( portSTACK_TYPE ) 0x4444; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x5555; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x6666; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x7777; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x8888; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x9999; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaa; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xbbbb; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xcccc; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xdddd; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xeeee; + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + R15. */ + *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; + pxTopOfStack--; + + /* The code generated by the mspgcc compiler does not maintain separate + stack and frame pointers. The portENTER_CRITICAL macro cannot therefore + use the stack as per other ports. Instead a variable is used to keep + track of the critical section nesting. This variable has to be stored + as part of the task context and is initially set to zero. */ + *pxTopOfStack = ( portSTACK_TYPE ) portNO_CRITICAL_SECTION_NESTING; + + /* Return a pointer to the top of the stack we have generated so this can + be stored in the task control block for the task. */ + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xPortStartScheduler( void ) +{ + /* Setup the hardware to generate the tick. Interrupts are disabled when + this function is called. */ + prvSetupTimerInterrupt(); + + /* Restore the context of the first task that is going to run. */ + portRESTORE_CONTEXT(); + + /* Should not get here as the tasks are now running! */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the MSP430 port will get stopped. If required simply + disable the tick interrupt here. */ +} +/*-----------------------------------------------------------*/ + +/* + * Manual context switch called by portYIELD or taskYIELD. + * + * The first thing we do is save the registers so we can use a naked attribute. + */ +void vPortYield( void ) __attribute__ ( ( naked ) ); +void vPortYield( void ) +{ + /* We want the stack of the task being saved to look exactly as if the task + was saved during a pre-emptive RTOS tick ISR. Before calling an ISR the + msp430 places the status register onto the stack. As this is a function + call and not an ISR we have to do this manually. */ + asm volatile ( "push r2" ); + _DINT(); + + /* Save the context of the current task. */ + portSAVE_CONTEXT(); + + /* Switch to the highest priority task that is ready to run. */ + vTaskSwitchContext(); + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * Hardware initialisation to generate the RTOS tick. This uses timer 0 + * but could alternatively use the watchdog timer or timer 1. + */ +static void prvSetupTimerInterrupt( void ) +{ + /* Ensure the timer is stopped. */ + TACTL = 0; + + /* Run the timer of the ACLK. */ + TACTL = TASSEL_1; + + /* Clear everything to start with. */ + TACTL |= TACLR; + + /* Set the compare match value according to the tick rate we want. */ + TACCR0 = portACLK_FREQUENCY_HZ / configTICK_RATE_HZ; + + /* Enable the interrupts. */ + TACCTL0 = CCIE; + + /* Start up clean. */ + TACTL |= TACLR; + + /* Up mode. */ + TACTL |= MC_1; +} +/*-----------------------------------------------------------*/ + +/* + * The interrupt service routine used depends on whether the pre-emptive + * scheduler is being used or not. + */ + +#if configUSE_PREEMPTION == 1 + + /* + * Tick ISR for preemptive scheduler. We can use a naked attribute as + * the context is saved at the start of vPortYieldFromTick(). The tick + * count is incremented after the context is saved. + */ + interrupt (TIMERA0_VECTOR) prvTickISR( void ) __attribute__ ( ( naked ) ); + interrupt (TIMERA0_VECTOR) prvTickISR( void ) + { + /* Save the context of the interrupted task. */ + portSAVE_CONTEXT(); + + /* Increment the tick count then switch to the highest priority task + that is ready to run. */ + vTaskIncrementTick(); + vTaskSwitchContext(); + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT(); + } + +#else + + /* + * Tick ISR for the cooperative scheduler. All this does is increment the + * tick count. We don't need to switch context, this can only be done by + * manual calls to taskYIELD(); + */ + interrupt (TIMERA0_VECTOR) prvTickISR( void ); + interrupt (TIMERA0_VECTOR) prvTickISR( void ) + { + vTaskIncrementTick(); + } +#endif + + + diff --git a/20080212/Source/portable/GCC/MSP430F449/portmacro.h b/20080212/Source/portable/GCC/MSP430F449/portmacro.h new file mode 100644 index 000000000..7ab707669 --- /dev/null +++ b/20080212/Source/portable/GCC/MSP430F449/portmacro.h @@ -0,0 +1,138 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE unsigned portSHORT +#define portBASE_TYPE portSHORT + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Interrupt control macros. */ +#define portDISABLE_INTERRUPTS() asm volatile ( "DINT" ) +#define portENABLE_INTERRUPTS() asm volatile ( "EINT" ) +/*-----------------------------------------------------------*/ + +/* Critical section control macros. */ +#define portNO_CRITICAL_SECTION_NESTING ( ( unsigned portSHORT ) 0 ) + +#define portENTER_CRITICAL() \ +{ \ +extern volatile unsigned portSHORT usCriticalNesting; \ + \ + portDISABLE_INTERRUPTS(); \ + \ + /* Now interrupts are disabled ulCriticalNesting can be accessed */ \ + /* directly. Increment ulCriticalNesting to keep a count of how many */ \ + /* times portENTER_CRITICAL() has been called. */ \ + usCriticalNesting++; \ +} + +#define portEXIT_CRITICAL() \ +{ \ +extern volatile unsigned portSHORT usCriticalNesting; \ + \ + if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ + { \ + /* Decrement the nesting count as we are leaving a critical section. */ \ + usCriticalNesting--; \ + \ + /* If the nesting level has reached zero then interrupts should be */ \ + /* re-enabled. */ \ + if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ + } \ +} +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +extern void vPortYield( void ) __attribute__ ( ( naked ) ); +#define portYIELD() vPortYield() +#define portNOP() asm volatile ( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Hardwware specifics. */ +#define portBYTE_ALIGNMENT 2 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/20080212/Source/portable/GCC/MicroBlaze/port.c b/20080212/Source/portable/GCC/MicroBlaze/port.c new file mode 100644 index 000000000..ebd5ed053 --- /dev/null +++ b/20080212/Source/portable/GCC/MicroBlaze/port.c @@ -0,0 +1,347 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the MicroBlaze port. + *----------------------------------------------------------*/ + + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Standard includes. */ +#include + +/* Hardware includes. */ +#include +#include +#include + +/* Tasks are started with interrupts enabled. */ +#define portINITIAL_MSR_STATE ( ( portSTACK_TYPE ) 0x02 ) + +/* Tasks are started with a critical section nesting of 0 - however prior +to the scheduler being commenced we don't want the critical nesting level +to reach zero, so it is initialised to a high value. */ +#define portINITIAL_NESTING_VALUE ( 0xff ) + +/* Our hardware setup only uses one counter. */ +#define portCOUNTER_0 0 + +/* The stack used by the ISR is filled with a known value to assist in +debugging. */ +#define portISR_STACK_FILL_VALUE 0x55555555 + +/* Counts the nesting depth of calls to portENTER_CRITICAL(). Each task +maintains it's own count, so this variable is saved as part of the task +context. */ +volatile unsigned portBASE_TYPE uxCriticalNesting = portINITIAL_NESTING_VALUE; + +/* To limit the amount of stack required by each task, this port uses a +separate stack for interrupts. */ +unsigned portLONG *pulISRStack; + +/*-----------------------------------------------------------*/ + +/* + * Sets up the periodic ISR used for the RTOS tick. This uses timer 0, but + * could have alternatively used the watchdog timer or timer 1. + */ +static void prvSetupTimerInterrupt( void ); +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been made. + * + * See the header file portable.h. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ +extern void *_SDA2_BASE_, *_SDA_BASE_; +const unsigned portLONG ulR2 = ( unsigned portLONG ) &_SDA2_BASE_; +const unsigned portLONG ulR13 = ( unsigned portLONG ) &_SDA_BASE_; + + /* Place a few bytes of known values on the bottom of the stack. + This is essential for the Microblaze port and these lines must + not be omitted. The parameter value will overwrite the + 0x22222222 value during the function prologue. */ + *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x22222222; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x33333333; + pxTopOfStack--; + + /* First stack an initial value for the critical section nesting. This + is initialised to zero as tasks are started with interrupts enabled. */ + *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* R0. */ + + /* Place an initial value for all the general purpose registers. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) ulR2; /* R2 - small data area. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x03; /* R3. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x04; /* R4. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) pvParameters;/* R5 contains the function call parameters. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x06; /* R6. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x07; /* R7. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x08; /* R8. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x09; /* R9. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x0a; /* R10. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x0b; /* R11. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x0c; /* R12. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) ulR13; /* R13 - small data read write area. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* R14. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x0f; /* R15. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x10; /* R16. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x11; /* R17. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x12; /* R18. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x13; /* R19. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x14; /* R20. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x15; /* R21. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x16; /* R22. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x17; /* R23. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x18; /* R24. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x19; /* R25. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x1a; /* R26. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x1b; /* R27. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x1c; /* R28. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x1d; /* R29. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x1e; /* R30. */ + pxTopOfStack--; + + /* The MSR is stacked between R30 and R31. */ + *pxTopOfStack = portINITIAL_MSR_STATE; + pxTopOfStack--; + + *pxTopOfStack = ( portSTACK_TYPE ) 0x1f; /* R31. */ + pxTopOfStack--; + + /* Return a pointer to the top of the stack we have generated so this can + be stored in the task control block for the task. */ + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xPortStartScheduler( void ) +{ +extern void ( __FreeRTOS_interrupt_Handler )( void ); +extern void ( vStartFirstTask )( void ); + + + /* Setup the FreeRTOS interrupt handler. Code copied from crt0.s. */ + asm volatile ( "la r6, r0, __FreeRTOS_interrupt_handler \n\t" \ + "sw r6, r1, r0 \n\t" \ + "lhu r7, r1, r0 \n\t" \ + "shi r7, r0, 0x12 \n\t" \ + "shi r6, r0, 0x16 " ); + + /* Setup the hardware to generate the tick. Interrupts are disabled when + this function is called. */ + prvSetupTimerInterrupt(); + + /* Allocate the stack to be used by the interrupt handler. */ + pulISRStack = ( unsigned portLONG * ) pvPortMalloc( configMINIMAL_STACK_SIZE * sizeof( portSTACK_TYPE ) ); + + /* Restore the context of the first task that is going to run. */ + if( pulISRStack != NULL ) + { + /* Fill the ISR stack with a known value to facilitate debugging. */ + memset( pulISRStack, portISR_STACK_FILL_VALUE, configMINIMAL_STACK_SIZE * sizeof( portSTACK_TYPE ) ); + pulISRStack += ( configMINIMAL_STACK_SIZE - 1 ); + + /* Kick off the first task. */ + vStartFirstTask(); + } + + /* Should not get here as the tasks are now running! */ + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented. */ +} +/*-----------------------------------------------------------*/ + +/* + * Manual context switch called by portYIELD or taskYIELD. + */ +void vPortYield( void ) +{ +extern void VPortYieldASM( void ); + + /* Perform the context switch in a critical section to assure it is + not interrupted by the tick ISR. It is not a problem to do this as + each task maintains it's own interrupt status. */ + portENTER_CRITICAL(); + /* Jump directly to the yield function to ensure there is no + compiler generated prologue code. */ + asm volatile ( "bralid r14, VPortYieldASM \n\t" \ + "or r0, r0, r0 \n\t" ); + portEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +/* + * Hardware initialisation to generate the RTOS tick. + */ +static void prvSetupTimerInterrupt( void ) +{ +XTmrCtr xTimer; +const unsigned portLONG ulCounterValue = configCPU_CLOCK_HZ / configTICK_RATE_HZ; +unsigned portBASE_TYPE uxMask; + + /* The OPB timer1 is used to generate the tick. Use the provided library + functions to enable the timer and set the tick frequency. */ + XTmrCtr_mDisable( XPAR_OPB_TIMER_1_BASEADDR, XPAR_OPB_TIMER_1_DEVICE_ID ); + XTmrCtr_Initialize( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID ); + XTmrCtr_mSetLoadReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCounterValue ); + XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_LOAD_MASK | XTC_CSR_INT_OCCURED_MASK ); + + /* Set the timer interrupt enable bit while maintaining the other bit + states. */ + uxMask = XIntc_In32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ) ); + uxMask |= XPAR_OPB_TIMER_1_INTERRUPT_MASK; + XIntc_Out32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ), ( uxMask ) ); + + XTmrCtr_Start( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID ); + XTmrCtr_mSetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK | XTC_CSR_INT_OCCURED_MASK ); + XIntc_mAckIntr( XPAR_INTC_SINGLE_BASEADDR, 1 ); +} +/*-----------------------------------------------------------*/ + +/* + * The interrupt handler placed in the interrupt vector when the scheduler is + * started. The task context has already been saved when this is called. + * This handler determines the interrupt source and calls the relevant + * peripheral handler. + */ +void vTaskISRHandler( void ) +{ +static unsigned portLONG ulPending; + + /* Which interrupts are pending? */ + ulPending = XIntc_In32( ( XPAR_INTC_SINGLE_BASEADDR + XIN_IVR_OFFSET ) ); + + if( ulPending < XPAR_INTC_MAX_NUM_INTR_INPUTS ) + { + static XIntc_VectorTableEntry *pxTablePtr; + static XIntc_Config *pxConfig; + static unsigned portLONG ulInterruptMask; + + ulInterruptMask = ( unsigned portLONG ) 1 << ulPending; + + /* Get the configuration data using the device ID */ + pxConfig = &XIntc_ConfigTable[ ( unsigned portLONG ) XPAR_INTC_SINGLE_DEVICE_ID ]; + + pxTablePtr = &( pxConfig->HandlerTable[ ulPending ] ); + if( pxConfig->AckBeforeService & ( ulInterruptMask ) ) + { + XIntc_mAckIntr( pxConfig->BaseAddress, ulInterruptMask ); + pxTablePtr->Handler( pxTablePtr->CallBackRef ); + } + else + { + pxTablePtr->Handler( pxTablePtr->CallBackRef ); + XIntc_mAckIntr( pxConfig->BaseAddress, ulInterruptMask ); + } + } +} +/*-----------------------------------------------------------*/ + +/* + * Handler for the timer interrupt. + */ +void vTickISR( void *pvBaseAddress ) +{ +unsigned portLONG ulCSR; + + /* Increment the RTOS tick - this might cause a task to unblock. */ + vTaskIncrementTick(); + + /* Clear the timer interrupt */ + ulCSR = XTmrCtr_mGetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, 0); + XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCSR ); + + /* If we are using the preemptive scheduler then we also need to determine + if this tick should cause a context switch. */ + #if configUSE_PREEMPTION == 1 + vTaskSwitchContext(); + #endif +} +/*-----------------------------------------------------------*/ + + + + + diff --git a/20080212/Source/portable/GCC/MicroBlaze/portasm.s b/20080212/Source/portable/GCC/MicroBlaze/portasm.s new file mode 100644 index 000000000..b818daa9e --- /dev/null +++ b/20080212/Source/portable/GCC/MicroBlaze/portasm.s @@ -0,0 +1,171 @@ + .extern pxCurrentTCB + .extern vTaskISRHandler + .extern vTaskSwitchContext + .extern uxCriticalNesting + .extern pulISRStack + + .global __FreeRTOS_interrupt_handler + .global VPortYieldASM + .global vStartFirstTask + + +.macro portSAVE_CONTEXT + /* Make room for the context on the stack. */ + addik r1, r1, -132 + /* Save r31 so it can then be used. */ + swi r31, r1, 4 + /* Copy the msr into r31 - this is stacked later. */ + mfs r31, rmsr + /* Stack general registers. */ + swi r30, r1, 12 + swi r29, r1, 16 + swi r28, r1, 20 + swi r27, r1, 24 + swi r26, r1, 28 + swi r25, r1, 32 + swi r24, r1, 36 + swi r23, r1, 40 + swi r22, r1, 44 + swi r21, r1, 48 + swi r20, r1, 52 + swi r19, r1, 56 + swi r18, r1, 60 + swi r17, r1, 64 + swi r16, r1, 68 + swi r15, r1, 72 + swi r13, r1, 80 + swi r12, r1, 84 + swi r11, r1, 88 + swi r10, r1, 92 + swi r9, r1, 96 + swi r8, r1, 100 + swi r7, r1, 104 + swi r6, r1, 108 + swi r5, r1, 112 + swi r4, r1, 116 + swi r3, r1, 120 + swi r2, r1, 124 + /* Stack the critical section nesting value. */ + lwi r3, r0, uxCriticalNesting + swi r3, r1, 128 + /* Save the top of stack value to the TCB. */ + lwi r3, r0, pxCurrentTCB + sw r1, r0, r3 + + .endm + +.macro portRESTORE_CONTEXT + /* Load the top of stack value from the TCB. */ + lwi r3, r0, pxCurrentTCB + lw r1, r0, r3 + /* Restore the general registers. */ + lwi r31, r1, 4 + lwi r30, r1, 12 + lwi r29, r1, 16 + lwi r28, r1, 20 + lwi r27, r1, 24 + lwi r26, r1, 28 + lwi r25, r1, 32 + lwi r24, r1, 36 + lwi r23, r1, 40 + lwi r22, r1, 44 + lwi r21, r1, 48 + lwi r20, r1, 52 + lwi r19, r1, 56 + lwi r18, r1, 60 + lwi r17, r1, 64 + lwi r16, r1, 68 + lwi r15, r1, 72 + lwi r14, r1, 76 + lwi r13, r1, 80 + lwi r12, r1, 84 + lwi r11, r1, 88 + lwi r10, r1, 92 + lwi r9, r1, 96 + lwi r8, r1, 100 + lwi r7, r1, 104 + lwi r6, r1, 108 + lwi r5, r1, 112 + lwi r4, r1, 116 + lwi r2, r1, 124 + + /* Load the critical nesting value. */ + lwi r3, r1, 128 + swi r3, r0, uxCriticalNesting + + /* Obtain the MSR value from the stack. */ + lwi r3, r1, 8 + + /* Are interrupts enabled in the MSR? If so return using an return from + interrupt instruction to ensure interrupts are enabled only once the task + is running again. */ + andi r3, r3, 2 + beqid r3, 36 + or r0, r0, r0 + + /* Reload the rmsr from the stack, clear the enable interrupt bit in the + value before saving back to rmsr register, then return enabling interrupts + as we return. */ + lwi r3, r1, 8 + andi r3, r3, ~2 + mts rmsr, r3 + lwi r3, r1, 120 + addik r1, r1, 132 + rtid r14, 0 + or r0, r0, r0 + + /* Reload the rmsr from the stack, place it in the rmsr register, and + return without enabling interrupts. */ + lwi r3, r1, 8 + mts rmsr, r3 + lwi r3, r1, 120 + addik r1, r1, 132 + rtsd r14, 0 + or r0, r0, r0 + + .endm + + .text + .align 2 + + +__FreeRTOS_interrupt_handler: + portSAVE_CONTEXT + /* Entered via an interrupt so interrupts must be enabled in msr. */ + ori r31, r31, 2 + /* Stack msr. */ + swi r31, r1, 8 + /* Stack the return address. As we entered via an interrupt we do + not need to modify the return address prior to stacking. */ + swi r14, r1, 76 + /* Now switch to use the ISR stack. */ + lwi r3, r0, pulISRStack + add r1, r3, r0 + bralid r15, vTaskISRHandler + or r0, r0, r0 + portRESTORE_CONTEXT + + +VPortYieldASM: + portSAVE_CONTEXT + /* Stack msr. */ + swi r31, r1, 8 + /* Modify the return address so we return to the instruction after the + exception. */ + addi r14, r14, 8 + swi r14, r1, 76 + /* Now switch to use the ISR stack. */ + lwi r3, r0, pulISRStack + add r1, r3, r0 + bralid r15, vTaskSwitchContext + or r0, r0, r0 + portRESTORE_CONTEXT + +vStartFirstTask: + portRESTORE_CONTEXT + + + + + + diff --git a/20080212/Source/portable/GCC/MicroBlaze/portmacro.h b/20080212/Source/portable/GCC/MicroBlaze/portmacro.h new file mode 100644 index 000000000..c80102975 --- /dev/null +++ b/20080212/Source/portable/GCC/MicroBlaze/portmacro.h @@ -0,0 +1,133 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned portLONG +#define portBASE_TYPE portLONG + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Interrupt control macros. */ +void microblaze_disable_interrupts( void ); +void microblaze_enable_interrupts( void ); +#define portDISABLE_INTERRUPTS() microblaze_disable_interrupts() +#define portENABLE_INTERRUPTS() microblaze_enable_interrupts() +/*-----------------------------------------------------------*/ + +/* Critical section macros. */ +void vPortEnterCritical( void ); +void vPortExitCritical( void ); +#define portENTER_CRITICAL() { \ + extern unsigned portBASE_TYPE uxCriticalNesting; \ + microblaze_disable_interrupts(); \ + uxCriticalNesting++; \ + } + +#define portEXIT_CRITICAL() { \ + extern unsigned portBASE_TYPE uxCriticalNesting; \ + /* Interrupts are disabled, so we can */ \ + /* access the variable directly. */ \ + uxCriticalNesting--; \ + if( uxCriticalNesting == 0 ) \ + { \ + /* The nesting has unwound and we \ + can enable interrupts again. */ \ + portENABLE_INTERRUPTS(); \ + } \ + } + +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +void vPortYield( void ); +#define portYIELD() vPortYield() + +void vTaskSwitchContext(); +#define portYIELD_FROM_ISR() vTaskSwitchContext() +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 4 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portNOP() asm volatile ( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/20080212/Source/portable/GCC/STR75x/port.c b/20080212/Source/portable/GCC/STR75x/port.c new file mode 100644 index 000000000..202afaf45 --- /dev/null +++ b/20080212/Source/portable/GCC/STR75x/port.c @@ -0,0 +1,208 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the ST STR75x ARM7 + * port. + *----------------------------------------------------------*/ + +/* Library includes. */ +#include "75x_tb.h" +#include "75x_eic.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to setup the initial stack. */ +#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( portSTACK_TYPE ) 0x20 ) +#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 ) + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 ) + +/* Prescale used on the timer clock when calculating the tick period. */ +#define portPRESCALE 20 + + +/*-----------------------------------------------------------*/ + +/* Setup the TB to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ +portSTACK_TYPE *pxOriginalTOS; + + pxOriginalTOS = pxTopOfStack; + + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. */ + + /* First on the stack is the return address - which in this case is the + start of the task. The offset is added to make the return address appear + as it would within an IRQ ISR. */ + *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */ + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + R0. */ + *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The status register is set for system mode, with interrupts enabled. */ + *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR; + + #ifdef THUMB_INTERWORK + { + /* We want the task to start in thumb mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + #endif + + pxTopOfStack--; + + /* Interrupt flags cannot always be stored on the stack and will + instead be stored in a variable, which is then saved as part of the + tasks context. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xPortStartScheduler( void ) +{ +extern void vPortISRStartFirstTask( void ); + + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + vPortISRStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ARM port will require this function as there + is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ +EIC_IRQInitTypeDef EIC_IRQInitStructure; +TB_InitTypeDef TB_InitStructure; + + /* Setup the EIC for the TB. */ + EIC_IRQInitStructure.EIC_IRQChannelCmd = ENABLE; + EIC_IRQInitStructure.EIC_IRQChannel = TB_IRQChannel; + EIC_IRQInitStructure.EIC_IRQChannelPriority = 1; + EIC_IRQInit(&EIC_IRQInitStructure); + + /* Setup the TB for the generation of the tick interrupt. */ + TB_InitStructure.TB_Mode = TB_Mode_Timing; + TB_InitStructure.TB_CounterMode = TB_CounterMode_Down; + TB_InitStructure.TB_Prescaler = portPRESCALE; + TB_InitStructure.TB_AutoReload = ( ( configCPU_CLOCK_HZ / ( portPRESCALE + 1 ) ) / configTICK_RATE_HZ ) + 1; + TB_Init(&TB_InitStructure); + + /* Enable TB Update interrupt */ + TB_ITConfig(TB_IT_Update, ENABLE); + + /* Clear TB Update interrupt pending bit */ + TB_ClearITPendingBit(TB_IT_Update); + + /* Enable TB */ + TB_Cmd(ENABLE); +} +/*-----------------------------------------------------------*/ + + + + + + + diff --git a/20080212/Source/portable/GCC/STR75x/portISR.c b/20080212/Source/portable/GCC/STR75x/portISR.c new file mode 100644 index 000000000..c86ee3e50 --- /dev/null +++ b/20080212/Source/portable/GCC/STR75x/portISR.c @@ -0,0 +1,198 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +/*----------------------------------------------------------- + * Components that can be compiled to either ARM or THUMB mode are + * contained in port.c The ISR routines, which can only be compiled + * to ARM mode, are contained in this file. + *----------------------------------------------------------*/ + +/* +*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 ) + +volatile unsigned portLONG ulCriticalNesting = 9999UL; + +/*-----------------------------------------------------------*/ + +/* + * The scheduler can only be started from ARM mode, hence the inclusion of this + * function here. + */ +void vPortISRStartFirstTask( void ); +/*-----------------------------------------------------------*/ + +void vPortISRStartFirstTask( void ) +{ + /* Simply start the scheduler. This is included here as it can only be + called from ARM mode. */ + asm volatile ( \ + "LDR R0, =pxCurrentTCB \n\t" \ + "LDR R0, [R0] \n\t" \ + "LDR LR, [R0] \n\t" \ + \ + /* The critical nesting depth is the first item on the stack. */ \ + /* Load it into the ulCriticalNesting variable. */ \ + "LDR R0, =ulCriticalNesting \n\t" \ + "LDMFD LR!, {R1} \n\t" \ + "STR R1, [R0] \n\t" \ + \ + /* Get the SPSR from the stack. */ \ + "LDMFD LR!, {R0} \n\t" \ + "MSR SPSR, R0 \n\t" \ + \ + /* Restore all system mode registers for the task. */ \ + "LDMFD LR, {R0-R14}^ \n\t" \ + "NOP \n\t" \ + \ + /* Restore the return address. */ \ + "LDR LR, [LR, #+60] \n\t" \ + \ + /* And return - correcting the offset in the LR to obtain the */ \ + /* correct address. */ \ + "SUBS PC, LR, #4 \n\t" \ + ); +} +/*-----------------------------------------------------------*/ + +void vPortTickISR( void ) +{ + /* Increment the RTOS tick count, then look for the highest priority + task that is ready to run. */ + vTaskIncrementTick(); + + #if configUSE_PREEMPTION == 1 + vTaskSwitchContext(); + #endif + + /* Ready for the next interrupt. */ + TB_ClearITPendingBit( TB_IT_Update ); +} + +/*-----------------------------------------------------------*/ + +/* + * The interrupt management utilities can only be called from ARM mode. When + * THUMB_INTERWORK is defined the utilities are defined as functions here to + * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then + * the utilities are defined as macros in portmacro.h - as per other ports. + */ +#ifdef THUMB_INTERWORK + + void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); + void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); + + void vPortDisableInterruptsFromThumb( void ) + { + asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0} \n\t" /* Pop R0. */ + "BX R14" ); /* Return back to thumb. */ + } + + void vPortEnableInterruptsFromThumb( void ) + { + asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0} \n\t" /* Pop R0. */ + "BX R14" ); /* Return back to thumb. */ + } + +#endif /* THUMB_INTERWORK */ +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ + asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0}" ); /* Pop R0. */ + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Enable interrupts as per portEXIT_CRITICAL(). */ + asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0}" ); /* Pop R0. */ + } + } +} + + + + + diff --git a/20080212/Source/portable/GCC/STR75x/portmacro.h b/20080212/Source/portable/GCC/STR75x/portmacro.h new file mode 100644 index 000000000..2b8abda4b --- /dev/null +++ b/20080212/Source/portable/GCC/STR75x/portmacro.h @@ -0,0 +1,155 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned portLONG +#define portBASE_TYPE portLONG + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 4 +#define portYIELD() asm volatile ( "SWI 0" ) +#define portNOP() asm volatile ( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +/* + * The interrupt management utilities can only be called from ARM mode. When + * THUMB_INTERWORK is defined the utilities are defined as functions in + * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not + * defined then the utilities are defined as macros here - as per other ports. + */ + +#ifdef THUMB_INTERWORK + + extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); + extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); + + #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb() + #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb() + +#else + + #define portDISABLE_INTERRUPTS() \ + asm volatile ( \ + "STMDB SP!, {R0} \n\t" /* Push R0. */ \ + "MRS R0, CPSR \n\t" /* Get CPSR. */ \ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ + "LDMIA SP!, {R0} " ) /* Pop R0. */ + + #define portENABLE_INTERRUPTS() \ + asm volatile ( \ + "STMDB SP!, {R0} \n\t" /* Push R0. */ \ + "MRS R0, CPSR \n\t" /* Get CPSR. */ \ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ + "LDMIA SP!, {R0} " ) /* Pop R0. */ + +#endif /* THUMB_INTERWORK */ + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ +{ \ +extern void vTaskSwitchContext( void ); \ + \ + if( xSwitchRequired ) \ + { \ + vTaskSwitchContext(); \ + } \ +} +/*-----------------------------------------------------------*/ + +/* Compiler specifics */ +#define inline + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + + diff --git a/20080212/Source/portable/IAR/ARM_CM3/port.c b/20080212/Source/portable/IAR/ARM_CM3/port.c new file mode 100644 index 000000000..acb1b8c40 --- /dev/null +++ b/20080212/Source/portable/IAR/ARM_CM3/port.c @@ -0,0 +1,214 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + Change from V4.2.1: + + + Introduced usage of configKERNEL_INTERRUPT_PRIORITY macro to set the + interrupt priority used by the kernel. +*/ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the ARM CM3 port. + *----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to manipulate the NVIC. */ +#define portNVIC_SYSTICK_CTRL ( ( volatile unsigned portLONG *) 0xe000e010 ) +#define portNVIC_SYSTICK_LOAD ( ( volatile unsigned portLONG *) 0xe000e014 ) +#define portNVIC_INT_CTRL ( ( volatile unsigned portLONG *) 0xe000ed04 ) +#define portNVIC_SYSPRI2 ( ( volatile unsigned portLONG *) 0xe000ed20 ) +#define portNVIC_SYSPRI1 ( ( volatile unsigned portLONG *) 0xe000ed1c ) +#define portNVIC_SYSTICK_CLK 0x00000004 +#define portNVIC_SYSTICK_INT 0x00000002 +#define portNVIC_SYSTICK_ENABLE 0x00000001 +#define portNVIC_PENDSVSET 0x10000000 +#define portNVIC_PENDSV_PRI ( ( ( unsigned portLONG ) configKERNEL_INTERRUPT_PRIORITY ) << 16 ) +#define portNVIC_SYSTICK_PRI ( ( ( unsigned portLONG ) configKERNEL_INTERRUPT_PRIORITY ) << 24 ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000 ) + +/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is +defined. The value 255 should also ensure backward compatibility. +FreeRTOS.org versions prior to V4.3.0 did not include this definition. */ +#ifndef configKERNEL_INTERRUPT_PRIORITY + #define configKERNEL_INTERRUPT_PRIORITY 0 +#endif + +/* Each task maintains its own interrupt status in the critical nesting +variable. */ +unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa; + +/* + * Setup the timer to generate the tick interrupts. + */ +static void prvSetupTimerInterrupt( void ); + +/* + * Set the MSP/PSP to a known value. + */ +extern void vSetMSP( unsigned long ulValue ); +extern void vSetPSP( unsigned long ulValue ); + +/* + * Utilities called from the assembler code. + */ +void vPortSwitchContext( void ); +void vPortIncrementTick( void ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ + /* Simulate the stack frame as it would be created by a context switch + interrupt. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = 0xfffffffd; /* LR */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ + pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ + *pxTopOfStack = 0x00000000; /* uxCriticalNesting. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +portBASE_TYPE xPortStartScheduler( void ) +{ + /* Make PendSV and SysTick the lowest priority interrupts. */ + *(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI; + *(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI; + + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + vSetPSP( 0 ); + vSetMSP( *((unsigned portLONG *) 0 ) ); + *(portNVIC_INT_CTRL) |= portNVIC_PENDSVSET; + + /* Enable interrupts */ + portENABLE_INTERRUPTS(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the CM3 port will require this function as there + is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +void vPortYieldFromISR( void ) +{ + /* Set a PendSV to request a context switch. */ + *(portNVIC_INT_CTRL) |= portNVIC_PENDSVSET; + + /* This function is also called in response to a Yield(), so we want + the yield to occur immediately. */ + portENABLE_INTERRUPTS(); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + uxCriticalNesting--; + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +void prvSetupTimerInterrupt( void ) +{ + /* Configure SysTick to interrupt at the requested rate. */ + *(portNVIC_SYSTICK_LOAD) = configCPU_CLOCK_HZ / configTICK_RATE_HZ; + *(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE; +} +/*-----------------------------------------------------------*/ + +void vPortSwitchContext( void ) +{ + vPortSetInterruptMask(); + vTaskSwitchContext(); + vPortClearInterruptMask(); +} +/*-----------------------------------------------------------*/ + +void vPortIncrementTick( void ) +{ + vPortSetInterruptMask(); + vTaskIncrementTick(); + vPortClearInterruptMask(); +} + + diff --git a/20080212/Source/portable/IAR/ARM_CM3/portasm.s b/20080212/Source/portable/IAR/ARM_CM3/portasm.s new file mode 100644 index 000000000..554764c31 --- /dev/null +++ b/20080212/Source/portable/IAR/ARM_CM3/portasm.s @@ -0,0 +1,175 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + Change from V4.2.1: + + + Introduced usage of configKERNEL_INTERRUPT_PRIORITY macro to set the + interrupt priority used by the kernel. +*/ + +#include + +/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is +defined. The value zero should also ensure backward compatibility. +FreeRTOS.org versions prior to V4.3.0 did not include this definition. */ +#ifndef configKERNEL_INTERRUPT_PRIORITY + #define configKERNEL_INTERRUPT_PRIORITY 0 +#endif + + + RSEG CODE:CODE(2) + thumb + + EXTERN vPortYieldFromISR + EXTERN vPortSwitchContext + EXTERN vPortIncrementTick + EXTERN uxCriticalNesting + EXTERN pxCurrentTCB + + PUBLIC vSetPSP + PUBLIC vSetMSP + PUBLIC xPortPendSVHandler + PUBLIC xPortSysTickHandler + PUBLIC vPortSetInterruptMask + PUBLIC vPortClearInterruptMask + + +vSetPSP: + msr psp, r0 + bx lr + +/*-----------------------------------------------------------*/ + +vSetMSP + msr msp, r0 + bx lr + +/*-----------------------------------------------------------*/ + +xPortPendSVHandler: + mrs r0, psp + cbz r0, no_save + /* Save the context into the TCB. */ + stmdb r0!, {r4-r11} + sub r0, r0, #0x04 + ldr r1, =uxCriticalNesting + ldr r2, =pxCurrentTCB + ldr r1, [r1] + ldr r2, [r2] + str r1, [r0] + str r0, [r2] + +no_save: + push {r14} + bl vPortSwitchContext + pop {r14} + /* Restore the context. */ + ldr r1, =pxCurrentTCB + ldr r1, [r1] + ldr r0, [r1] + ldmia r0!, {r1, r4-r11} + ldr r2, =uxCriticalNesting + str r1, [r2] + msr psp, r0 + orr r14, r14, #0xd + /* Exit with interrupts in the state required by the task. */ + cbnz r1, sv_disable_interrupts + bx r14 + +sv_disable_interrupts: + mov r1, #configKERNEL_INTERRUPT_PRIORITY + msr basepri, R1 + bx r14 + + +/*-----------------------------------------------------------*/ + +xPortSysTickHandler: + /* Call the scheduler tick function. */ + push {r14} + bl vPortIncrementTick + pop {r14} + + /* If using preemption, also force a context switch. */ + #if configUSE_PREEMPTION == 1 + push {r14} + bl vPortYieldFromISR + pop {r14} + #endif + + /* Exit with interrupts in the correct state. */ + ldr r2, =uxCriticalNesting + ldr r2, [r2] + cbnz r2, tick_disable_interrupts + bx r14 + +tick_disable_interrupts: + mov r1, #configKERNEL_INTERRUPT_PRIORITY + msr basepri, R1 + + bx r14 + +/*-----------------------------------------------------------*/ + +vPortSetInterruptMask: + push { r0 } + mov R0, #configKERNEL_INTERRUPT_PRIORITY + msr BASEPRI, R0 + pop { R0 } + + bx r14 + +/*-----------------------------------------------------------*/ + +vPortClearInterruptMask: + PUSH { r0 } + MOV R0, #0 + MSR BASEPRI, R0 + POP { R0 } + + bx r14 + +/*-----------------------------------------------------------*/ + + END + \ No newline at end of file diff --git a/20080212/Source/portable/IAR/ARM_CM3/portmacro.h b/20080212/Source/portable/IAR/ARM_CM3/portmacro.h new file mode 100644 index 000000000..0ff50124a --- /dev/null +++ b/20080212/Source/portable/IAR/ARM_CM3/portmacro.h @@ -0,0 +1,127 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + Change from V4.2.1: + + + Introduced usage of configKERNEL_INTERRUPT_PRIORITY macro to set the + interrupt priority used by the kernel. +*/ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned portLONG +#define portBASE_TYPE long + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 4 +/*-----------------------------------------------------------*/ + + +/* Scheduler utilities. */ +extern void vPortYieldFromISR( void ); + +#define portYIELD() vPortYieldFromISR() + +#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vPortYieldFromISR() +/*-----------------------------------------------------------*/ + + +/* Critical section management. */ + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +extern void vPortSetInterruptMask( void ); +extern void vPortClearInterruptMask( void ); + +#define portDISABLE_INTERRUPTS() vPortSetInterruptMask(); +#define portENABLE_INTERRUPTS() vPortClearInterruptMask(); +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#define inline +#define portNOP() + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/20080212/Source/portable/IAR/ATMega323/port.c b/20080212/Source/portable/IAR/ATMega323/port.c new file mode 100644 index 000000000..1381c6e94 --- /dev/null +++ b/20080212/Source/portable/IAR/ATMega323/port.c @@ -0,0 +1,355 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#include + +#include "FreeRTOS.h" +#include "task.h" + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the AVR/IAR port. + *----------------------------------------------------------*/ + +/* Start tasks with interrupts enables. */ +#define portFLAGS_INT_ENABLED ( ( portSTACK_TYPE ) 0x80 ) + +/* Hardware constants for timer 1. */ +#define portCLEAR_COUNTER_ON_MATCH ( ( unsigned portCHAR ) 0x08 ) +#define portPRESCALE_64 ( ( unsigned portCHAR ) 0x03 ) +#define portCLOCK_PRESCALER ( ( unsigned portLONG ) 64 ) +#define portCOMPARE_MATCH_A_INTERRUPT_ENABLE ( ( unsigned portCHAR ) 0x10 ) + +/* The number of bytes used on the hardware stack by the task start address. */ +#define portBYTES_USED_BY_RETURN_ADDRESS ( 2 ) +/*-----------------------------------------------------------*/ + +/* Stores the critical section nesting. This must not be initialised to 0. +It will be initialised when a task starts. */ +#define portNO_CRITICAL_NESTING ( ( unsigned portBASE_TYPE ) 0 ) +unsigned portBASE_TYPE uxCriticalNesting = 0x50; + + +/* + * Perform hardware setup to enable ticks from timer 1, compare match A. + */ +static void prvSetupTimerInterrupt( void ); + +/* + * The IAR compiler does not have full support for inline assembler, so + * these are defined in the portmacro assembler file. + */ +extern void vPortYieldFromTick( void ); +extern void vPortStart( void ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ +unsigned portSHORT usAddress; +portSTACK_TYPE *pxTopOfHardwareStack; + + /* Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging. */ + + *pxTopOfStack = 0x11; + pxTopOfStack--; + *pxTopOfStack = 0x22; + pxTopOfStack--; + *pxTopOfStack = 0x33; + pxTopOfStack--; + + /* Remember where the top of the hardware stack is - this is required + below. */ + pxTopOfHardwareStack = pxTopOfStack; + + + /* Simulate how the stack would look after a call to vPortYield(). */ + + /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */ + + + + /* The IAR compiler requires two stacks per task. First there is the + hardware call stack which uses the AVR stack pointer. Second there is the + software stack (local variables, parameter passing, etc.) which uses the + AVR Y register. + + This function places both stacks within the memory block passed in as the + first parameter. The hardware stack is placed at the bottom of the memory + block. A gap is then left for the hardware stack to grow. Next the software + stack is placed. The amount of space between the software and hardware + stacks is defined by configCALL_STACK_SIZE. + + + + The first part of the stack is the hardware stack. Place the start + address of the task on the hardware stack. */ + usAddress = ( unsigned portSHORT ) pxCode; + *pxTopOfStack = ( portSTACK_TYPE ) ( usAddress & ( unsigned portSHORT ) 0x00ff ); + pxTopOfStack--; + + usAddress >>= 8; + *pxTopOfStack = ( portSTACK_TYPE ) ( usAddress & ( unsigned portSHORT ) 0x00ff ); + pxTopOfStack--; + + + /* Leave enough space for the hardware stack before starting the software + stack. The '- 2' is because we have already used two spaces for the + address of the start of the task. */ + pxTopOfStack -= ( configCALL_STACK_SIZE - 2 ); + + + + /* Next simulate the stack as if after a call to portSAVE_CONTEXT(). + portSAVE_CONTEXT places the flags on the stack immediately after r0 + to ensure the interrupts get disabled as soon as possible, and so ensuring + the stack use is minimal should a context switch interrupt occur. */ + *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* R0 */ + pxTopOfStack--; + *pxTopOfStack = portFLAGS_INT_ENABLED; + pxTopOfStack--; + + /* Next place the address of the hardware stack. This is required so + the AVR stack pointer can be restored to point to the hardware stack. */ + pxTopOfHardwareStack -= portBYTES_USED_BY_RETURN_ADDRESS; + usAddress = ( unsigned portSHORT ) pxTopOfHardwareStack; + + /* SPL */ + *pxTopOfStack = ( portSTACK_TYPE ) ( usAddress & ( unsigned portSHORT ) 0x00ff ); + pxTopOfStack--; + + /* SPH */ + usAddress >>= 8; + *pxTopOfStack = ( portSTACK_TYPE ) ( usAddress & ( unsigned portSHORT ) 0x00ff ); + pxTopOfStack--; + + + + + /* Now the remaining registers. */ + *pxTopOfStack = ( portSTACK_TYPE ) 0x01; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x02; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x03; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x04; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x05; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x06; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x07; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x08; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x09; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x10; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x11; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x12; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x13; /* R13 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x14; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x15; /* R15 */ + pxTopOfStack--; + + /* Place the parameter on the stack in the expected location. */ + usAddress = ( unsigned portSHORT ) pvParameters; + *pxTopOfStack = ( portSTACK_TYPE ) ( usAddress & ( unsigned portSHORT ) 0x00ff ); + pxTopOfStack--; + + usAddress >>= 8; + *pxTopOfStack = ( portSTACK_TYPE ) ( usAddress & ( unsigned portSHORT ) 0x00ff ); + pxTopOfStack--; + + *pxTopOfStack = ( portSTACK_TYPE ) 0x18; /* R18 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x19; /* R19 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x20; /* R20 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x21; /* R21 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x22; /* R22 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x23; /* R23 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x24; /* R24 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x25; /* R25 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x26; /* R26 X */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x27; /* R27 */ + pxTopOfStack--; + + /* The Y register is not stored as it is used as the software stack and + gets saved into the task control block. */ + + *pxTopOfStack = ( portSTACK_TYPE ) 0x30; /* R30 Z */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x031; /* R31 */ + + pxTopOfStack--; + *pxTopOfStack = portNO_CRITICAL_NESTING; /* Critical nesting is zero when the task starts. */ + + /*lint +e950 +e611 +e923 */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xPortStartScheduler( void ) +{ + /* Setup the hardware to generate the tick. */ + prvSetupTimerInterrupt(); + + /* Restore the context of the first task that is going to run. + Normally we would just call portRESTORE_CONTEXT() here, but as the IAR + compiler does not fully support inline assembler we have to make a call.*/ + vPortStart(); + + + /* Should not get here! */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the AVR port will get stopped. If required simply + disable the tick interrupt here. */ +} +/*-----------------------------------------------------------*/ + +/* + * Setup timer 1 compare match A to generate a tick interrupt. + */ +static void prvSetupTimerInterrupt( void ) +{ +unsigned portLONG ulCompareMatch; +unsigned portCHAR ucHighByte, ucLowByte; + + /* Using 16bit timer 1 to generate the tick. Correct fuses must be + selected for the configCPU_CLOCK_HZ clock. */ + + ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ; + + /* We only have 16 bits so have to scale to get our required tick rate. */ + ulCompareMatch /= portCLOCK_PRESCALER; + + /* Adjust for correct value. */ + ulCompareMatch -= ( unsigned portLONG ) 1; + + /* Setup compare match value for compare match A. Interrupts are disabled + before this is called so we need not worry here. */ + ucLowByte = ( unsigned portCHAR ) ( ulCompareMatch & ( unsigned portLONG ) 0xff ); + ulCompareMatch >>= 8; + ucHighByte = ( unsigned portCHAR ) ( ulCompareMatch & ( unsigned portLONG ) 0xff ); + OCR1AH = ucHighByte; + OCR1AL = ucLowByte; + + /* Setup clock source and compare match behaviour. */ + ucLowByte = portCLEAR_COUNTER_ON_MATCH | portPRESCALE_64; + TCCR1B = ucLowByte; + + /* Enable the interrupt - this is okay as interrupt are currently globally + disabled. */ + TIMSK |= portCOMPARE_MATCH_A_INTERRUPT_ENABLE; +} +/*-----------------------------------------------------------*/ + +#if configUSE_PREEMPTION == 1 + + /* + * Tick ISR for preemptive scheduler. We can use a __task attribute as + * the context is saved at the start of vPortYieldFromTick(). The tick + * count is incremented after the context is saved. + */ + __task void SIG_OUTPUT_COMPARE1A( void ) + { + vPortYieldFromTick(); + asm( "reti" ); + } + +#else + + /* + * Tick ISR for the cooperative scheduler. All this does is increment the + * tick count. We don't need to switch context, this can only be done by + * manual calls to taskYIELD(); + * + * THE INTERRUPT VECTOR IS POPULATED IN portmacro.s90. DO NOT INSTALL + * IT HERE USING THE USUAL PRAGMA. + */ + __interrupt void SIG_OUTPUT_COMPARE1A( void ) + { + vTaskIncrementTick(); + } +#endif +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + uxCriticalNesting--; + if( uxCriticalNesting == portNO_CRITICAL_NESTING ) + { + portENABLE_INTERRUPTS(); + } +} + + diff --git a/20080212/Source/portable/IAR/ATMega323/portmacro.h b/20080212/Source/portable/IAR/ATMega323/portmacro.h new file mode 100644 index 000000000..204b33955 --- /dev/null +++ b/20080212/Source/portable/IAR/ATMega323/portmacro.h @@ -0,0 +1,126 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V1.2.3 + + + portCPU_CLOSK_HZ definition changed to 8MHz base 10, previously it + base 16. +*/ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE unsigned portCHAR +#define portBASE_TYPE portCHAR + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif + +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() + +#define portDISABLE_INTERRUPTS() asm( "cli" ) +#define portENABLE_INTERRUPTS() asm( "sei" ) +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 1 +#define portNOP() asm( "nop" ) +/*-----------------------------------------------------------*/ + +/* Kernel utilities. */ +void vPortYield( void ); +#define portYIELD() vPortYield() + +#ifdef IAR_MEGA_AVR + #define outb( PORT, VALUE ) PORT = VALUE +#endif +/*-----------------------------------------------------------*/ + +/* Compiler specifics. */ +#define inline +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + + diff --git a/20080212/Source/portable/IAR/ATMega323/portmacro.s90 b/20080212/Source/portable/IAR/ATMega323/portmacro.s90 new file mode 100644 index 000000000..55cdc26d0 --- /dev/null +++ b/20080212/Source/portable/IAR/ATMega323/portmacro.s90 @@ -0,0 +1,245 @@ +; FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. +; +; This file is part of the FreeRTOS.org distribution. +; +; FreeRTOS.org is free software; you can redistribute it and/or modify +; it under the terms of the GNU General Public License as published by +; the Free Software Foundation; either version 2 of the License, or +; (at your option) any later version. +; +; FreeRTOS.org is distributed in the hope that it will be useful, +; but WITHOUT ANY WARRANTY; without even the implied warranty of +; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +; GNU General Public License for more details. +; +; You should have received a copy of the GNU General Public License +; along with FreeRTOS.org; if not, write to the Free Software +; Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +; +; A special exception to the GPL can be applied should you wish to distribute +; a combined work that includes FreeRTOS.org, without being obliged to provide +; the source code for any proprietary components. See the licensing section +; of http://www.FreeRTOS.org for full details of how and when the exception +; can be applied. +; +; *************************************************************************** +; See http://www.FreeRTOS.org for documentation, latest information, license +; and contact details. Please ensure to read the configuration and relevant +; port sections of the online documentation. +; *************************************************************************** + +#include + +; Declare all extern symbols here - including any ISRs that are referenced in +; the vector table. + +; ISR functions +; ------------- +EXTERN SIG_OUTPUT_COMPARE1A +EXTERN SIG_UART_RECV +EXTERN SIG_UART_DATA + + +; Functions used by scheduler +; --------------------------- +EXTERN vTaskSwitchContext +EXTERN pxCurrentTCB +EXTERN vTaskIncrementTick +EXTERN uxCriticalNesting + +; Functions implemented in this file +; ---------------------------------- +PUBLIC vPortYield +PUBLIC vPortYieldFromTick +PUBLIC vPortStart + + +; Interrupt vector table. +; ----------------------- +; +; For simplicity the RTOS tick interrupt routine uses the __task keyword. +; As the IAR compiler does not permit a function to be declared using both +; __task and __interrupt, the use of __task necessitates that the interrupt +; vector table be setup manually. +; +; To write an ISR, implement the ISR function using the __interrupt keyword +; but do not install the interrupt using the "#pragma vector=ABC" method. +; Instead manually place the name of the ISR in the vector table using an +; ORG and jmp instruction as demonstrated below. +; You will also have to add an EXTERN statement at the top of the file. + + ASEG + + + ORG TIMER1_COMPA_vect ; Vector address + jmp SIG_OUTPUT_COMPARE1A ; ISR + + ORG USART_RXC_vect ; Vector address + jmp SIG_UART_RECV ; ISR + + ORG USART_UDRE_vect ; Vector address + jmp SIG_UART_DATA ; ISR + + + RSEG CODE + + + +; Saving and Restoring a Task Context and Task Switching +; ------------------------------------------------------ +; +; The IAR compiler does not fully support inline assembler, so saving and +; restoring a task context has to be written in an asm file. +; +; vPortYield() and vPortYieldFromTick() are usually written in C. Doing +; so in this case would required calls to be made to portSAVE_CONTEXT() and +; portRESTORE_CONTEXT(). This is dis-advantageous as the context switch +; function would require two extra jump and return instructions over the +; WinAVR equivalent. +; +; To avoid this I have opted to implement both vPortYield() and +; vPortYieldFromTick() in this assembly file. For convenience +; portSAVE_CONTEXT and portRESTORE_CONTEXT are implemented as macros. + +portSAVE_CONTEXT MACRO + st -y, r0 ; First save the r0 register - we need to use this. + in r0, SREG ; Obtain the SREG value so we can disable interrupts... + cli ; ... as soon as possible. + st -y, r0 ; Store the SREG as it was before we disabled interrupts. + + in r0, SPL ; Next store the hardware stack pointer. The IAR... + st -y, r0 ; ... compiler uses the hardware stack as a call stack ... + in r0, SPH ; ... only. + st -y, r0 + + st -y, r1 ; Now store the rest of the registers. Dont store the ... + st -y, r2 ; ... the Y register here as it is used as the software + st -y, r3 ; stack pointer and will get saved into the TCB. + st -y, r4 + st -y, r5 + st -y, r6 + st -y, r7 + st -y, r8 + st -y, r9 + st -y, r10 + st -y, r11 + st -y, r12 + st -y, r13 + st -y, r14 + st -y, r15 + st -y, r16 + st -y, r17 + st -y, r18 + st -y, r19 + st -y, r20 + st -y, r21 + st -y, r22 + st -y, r23 + st -y, r24 + st -y, r25 + st -y, r26 + st -y, r27 + st -y, r30 + st -y, r31 + lds r0, uxCriticalNesting + st -y, r0 ; Store the critical nesting counter. + + lds r26, pxCurrentTCB ; Finally save the software stack pointer (Y ... + lds r27, pxCurrentTCB + 1 ; ... register) into the TCB. + st x+, r28 + st x+, r29 + + ENDM + + +portRESTORE_CONTEXT MACRO + lds r26, pxCurrentTCB + lds r27, pxCurrentTCB + 1 ; Restore the software stack pointer from ... + ld r28, x+ ; the TCB into the software stack pointer (... + ld r29, x+ ; ... the Y register). + + ld r0, y+ + sts uxCriticalNesting, r0 + ld r31, y+ ; Restore the registers down to R0. The Y + ld r30, y+ ; register is missing from this list as it + ld r27, y+ ; has already been restored. + ld r26, y+ + ld r25, y+ + ld r24, y+ + ld r23, y+ + ld r22, y+ + ld r21, y+ + ld r20, y+ + ld r19, y+ + ld r18, y+ + ld r17, y+ + ld r16, y+ + ld r15, y+ + ld r14, y+ + ld r13, y+ + ld r12, y+ + ld r11, y+ + ld r10, y+ + ld r9, y+ + ld r8, y+ + ld r7, y+ + ld r6, y+ + ld r5, y+ + ld r4, y+ + ld r3, y+ + ld r2, y+ + ld r1, y+ + + ld r0, y+ ; The next thing on the stack is the ... + out SPH, r0 ; ... hardware stack pointer. + ld r0, y+ + out SPL, r0 + + ld r0, y+ ; Next there is the SREG register. + out SREG, r0 + + ld r0, y+ ; Finally we have finished with r0, so restore r0. + + ENDM + + + +; vPortYield() and vPortYieldFromTick() +; ------------------------------------- +; +; Manual and preemptive context switch functions respectively. +; The IAR compiler does not fully support inline assembler, +; so these are implemented here rather than the more usually +; place of within port.c. + +vPortYield: + portSAVE_CONTEXT ; Save the context of the current task. + call vTaskSwitchContext ; Call the scheduler. + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + ret ; ... scheduler decided should run. + +vPortYieldFromTick: + portSAVE_CONTEXT ; Save the context of the current task. + call vTaskIncrementTick ; Call the timer tick function. + call vTaskSwitchContext ; Call the scheduler. + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + ret ; ... scheduler decided should run. + +; vPortStart() +; ------------ +; +; Again due to the lack of inline assembler, this is required +; to get access to the portRESTORE_CONTEXT macro. + +vPortStart: + portRESTORE_CONTEXT + ret + + +; Just a filler for unused interrupt vectors. +vNoISR: + reti + + + END + diff --git a/20080212/Source/portable/IAR/AVR32_UC3/exception.s82 b/20080212/Source/portable/IAR/AVR32_UC3/exception.s82 new file mode 100644 index 000000000..2df712c40 --- /dev/null +++ b/20080212/Source/portable/IAR/AVR32_UC3/exception.s82 @@ -0,0 +1,310 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Exception and interrupt vectors. + * + * This file maps all events supported by an AVR32UC. + * + * - Compiler: IAR EWAVR32 + * - Supported devices: All AVR32UC devices with an INTC module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include +#include "intc.h" + + +//! @{ +//! \verbatim + + +// Start of Exception Vector Table. + + // EVBA must be aligned with a power of two strictly greater than the EVBA- + // relative offset of the last vector. + COMMON EVTAB:CODE:ROOT(9) + + + // Force EVBA initialization. + EXTERN ??init_EVBA + REQUIRE ??init_EVBA + + // Export symbol. + PUBLIC ??EVBA + PUBLIC _evba +??EVBA: +_evba: + + ORG 0x000 + // Unrecoverable Exception. +_handle_Unrecoverable_Exception: + rjmp $ + + ORG 0x004 + // TLB Multiple Hit: UNUSED IN AVR32UC. +_handle_TLB_Multiple_Hit: + rjmp $ + + ORG 0x008 + // Bus Error Data Fetch. +_handle_Bus_Error_Data_Fetch: + rjmp $ + + ORG 0x00C + // Bus Error Instruction Fetch. +_handle_Bus_Error_Instruction_Fetch: + rjmp $ + + ORG 0x010 + // NMI. +_handle_NMI: + rjmp $ + + ORG 0x014 + // Instruction Address. +_handle_Instruction_Address: + rjmp $ + + ORG 0x018 + // ITLB Protection. +_handle_ITLB_Protection: + rjmp $ + + ORG 0x01C + // Breakpoint. +_handle_Breakpoint: + rjmp $ + + ORG 0x020 + // Illegal Opcode. +_handle_Illegal_Opcode: + rjmp $ + + ORG 0x024 + // Unimplemented Instruction. +_handle_Unimplemented_Instruction: + rjmp $ + + ORG 0x028 + // Privilege Violation. +_handle_Privilege_Violation: + rjmp $ + + ORG 0x02C + // Floating-Point: UNUSED IN AVR32UC. +_handle_Floating_Point: + rjmp $ + + ORG 0x030 + // Coprocessor Absent: UNUSED IN AVR32UC. +_handle_Coprocessor_Absent: + rjmp $ + + ORG 0x034 + // Data Address (Read). +_handle_Data_Address_Read: + rjmp $ + + ORG 0x038 + // Data Address (Write). +_handle_Data_Address_Write: + rjmp $ + + ORG 0x03C + // DTLB Protection (Read). +_handle_DTLB_Protection_Read: + rjmp $ + + ORG 0x040 + // DTLB Protection (Write). +_handle_DTLB_Protection_Write: + rjmp $ + + ORG 0x044 + // DTLB Modified: UNUSED IN AVR32UC. +_handle_DTLB_Modified: + rjmp $ + + ORG 0x050 + // ITLB Miss: UNUSED IN AVR32UC. +_handle_ITLB_Miss: + rjmp $ + + ORG 0x060 + // DTLB Miss (Read): UNUSED IN AVR32UC. +_handle_DTLB_Miss_Read: + rjmp $ + + ORG 0x070 + // DTLB Miss (Write): UNUSED IN AVR32UC. +_handle_DTLB_Miss_Write: + rjmp $ + + ORG 0x100 + // Supervisor Call. +_handle_Supervisor_Call: + lddpc pc, __SCALLYield + + +// Interrupt support. +// The interrupt controller must provide the offset address relative to EVBA. +// Important note: +// All interrupts call a C function named _get_interrupt_handler. +// This function will read group and interrupt line number to then return in +// R12 a pointer to a user-provided interrupt handler. + + ALIGN 2 + +_int0: + // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the + // CPU upon interrupt entry. +#if 1 // B1832: interrupt stack changed to exception stack if exception is detected. + mfsr r12, AVR32_SR + bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE + cp.w r12, 110b + brlo _int0_normal + lddsp r12, sp[0 * 4] + stdsp sp[6 * 4], r12 + lddsp r12, sp[1 * 4] + stdsp sp[7 * 4], r12 + lddsp r12, sp[3 * 4] + sub sp, -6 * 4 + rete +_int0_normal: +#endif + mov r12, 0 // Pass the int_lev parameter to the _get_interrupt_handler function. + mcall __get_interrupt_handler + cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function. + movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler. + rete // If this was a spurious interrupt (R12 == NULL), return from event handler. + +_int1: + // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the + // CPU upon interrupt entry. +#if 1 // B1832: interrupt stack changed to exception stack if exception is detected. + mfsr r12, AVR32_SR + bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE + cp.w r12, 110b + brlo _int1_normal + lddsp r12, sp[0 * 4] + stdsp sp[6 * 4], r12 + lddsp r12, sp[1 * 4] + stdsp sp[7 * 4], r12 + lddsp r12, sp[3 * 4] + sub sp, -6 * 4 + rete +_int1_normal: +#endif + mov r12, 1 // Pass the int_lev parameter to the _get_interrupt_handler function. + mcall __get_interrupt_handler + cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function. + movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler. + rete // If this was a spurious interrupt (R12 == NULL), return from event handler. + +_int2: + // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the + // CPU upon interrupt entry. +#if 1 // B1832: interrupt stack changed to exception stack if exception is detected. + mfsr r12, AVR32_SR + bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE + cp.w r12, 110b + brlo _int2_normal + lddsp r12, sp[0 * 4] + stdsp sp[6 * 4], r12 + lddsp r12, sp[1 * 4] + stdsp sp[7 * 4], r12 + lddsp r12, sp[3 * 4] + sub sp, -6 * 4 + rete +_int2_normal: +#endif + mov r12, 2 // Pass the int_lev parameter to the _get_interrupt_handler function. + mcall __get_interrupt_handler + cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function. + movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler. + rete // If this was a spurious interrupt (R12 == NULL), return from event handler. + +_int3: + // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the + // CPU upon interrupt entry. +#if 1 // B1832: interrupt stack changed to exception stack if exception is detected. + mfsr r12, AVR32_SR + bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE + cp.w r12, 110b + brlo _int3_normal + lddsp r12, sp[0 * 4] + stdsp sp[6 * 4], r12 + lddsp r12, sp[1 * 4] + stdsp sp[7 * 4], r12 + lddsp r12, sp[3 * 4] + sub sp, -6 * 4 + rete +_int3_normal: +#endif + mov r12, 3 // Pass the int_lev parameter to the _get_interrupt_handler function. + mcall __get_interrupt_handler + cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function. + movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler. + rete // If this was a spurious interrupt (R12 == NULL), return from event handler. + + +// Constant data area. + + ALIGN 2 + + // Import symbols. + EXTERN SCALLYield + EXTERN _get_interrupt_handler +__SCALLYield: + DC32 SCALLYield +__get_interrupt_handler: + DC32 _get_interrupt_handler + + // Values to store in the interrupt priority registers for the various interrupt priority levels. + // The interrupt priority registers contain the interrupt priority level and + // the EVBA-relative interrupt vector offset. + PUBLIC ipr_val +ipr_val: + DC32 (INT0 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int0 - _evba),\ + (INT1 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int1 - _evba),\ + (INT2 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int2 - _evba),\ + (INT3 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int3 - _evba) + + + END + + +//! \endverbatim +//! @} diff --git a/20080212/Source/portable/IAR/AVR32_UC3/port.c b/20080212/Source/portable/IAR/AVR32_UC3/port.c new file mode 100644 index 000000000..91ca6a375 --- /dev/null +++ b/20080212/Source/portable/IAR/AVR32_UC3/port.c @@ -0,0 +1,421 @@ +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief FreeRTOS port source for AVR32 UC3. + * + * - Compiler: IAR EWAVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + *****************************************************************************/ + +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* AVR32 UC3 includes. */ +#include +#include +#include "gpio.h" + +#if configDBG + #include "usart.h" +#endif + +#if( configTICK_USE_TC==1 ) + #include "tc.h" +#endif + + +/* Constants required to setup the task context. */ +#define portINITIAL_SR ( ( portSTACK_TYPE ) 0x00400000 ) /* AVR32 : [M2:M0]=001 I1M=0 I0M=0, GM=0 */ +#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 0 ) + +/* Each task maintains its own critical nesting variable. */ +#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 ) +volatile unsigned portLONG ulCriticalNesting = 9999UL; + +#if( configTICK_USE_TC==0 ) + static void prvScheduleNextTick( void ); +#else + static void prvClearTcInt( void ); +#endif + +/* Setup the timer to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/*-----------------------------------------------------------*/ + +/* + * Low-level initialization routine called during startup, before the main + * function. + */ +int __low_level_init(void) +{ + #if configHEAP_INIT + #pragma segment = "HEAP" + portBASE_TYPE *pxMem; + #endif + + /* Enable exceptions. */ + ENABLE_ALL_EXCEPTIONS(); + + /* Initialize interrupt handling. */ + INTC_init_interrupts(); + + #if configHEAP_INIT + { + /* Initialize the heap used by malloc. */ + for( pxMem = __segment_begin( "HEAP" ); pxMem < ( portBASE_TYPE * ) __segment_end( "HEAP" ); ) + { + *pxMem++ = 0xA5A5A5A5; + } + } + #endif + + /* Code section present if and only if the debug trace is activated. */ + #if configDBG + { + static const gpio_map_t DBG_USART_GPIO_MAP = + { + { configDBG_USART_RX_PIN, configDBG_USART_RX_FUNCTION }, + { configDBG_USART_TX_PIN, configDBG_USART_TX_FUNCTION } + }; + + static const usart_options_t DBG_USART_OPTIONS = + { + .baudrate = configDBG_USART_BAUDRATE, + .charlength = 8, + .paritytype = USART_NO_PARITY, + .stopbits = USART_1_STOPBIT, + .channelmode = USART_NORMAL_CHMODE + }; + + /* Initialize the USART used for the debug trace with the configured parameters. */ + extern volatile avr32_usart_t *volatile stdio_usart_base; + stdio_usart_base = configDBG_USART; + gpio_enable_module( DBG_USART_GPIO_MAP, + sizeof( DBG_USART_GPIO_MAP ) / sizeof( DBG_USART_GPIO_MAP[0] ) ); + usart_init_rs232(configDBG_USART, &DBG_USART_OPTIONS, configCPU_CLOCK_HZ); + } + #endif + + /* Request initialization of data segments. */ + return 1; +} +/*-----------------------------------------------------------*/ + +/* Added as there is no such function in FreeRTOS. */ +void *pvPortRealloc( void *pv, size_t xWantedSize ) +{ +void *pvReturn; + + vTaskSuspendAll(); + { + pvReturn = realloc( pv, xWantedSize ); + } + xTaskResumeAll(); + + return pvReturn; +} +/*-----------------------------------------------------------*/ + +/* The cooperative scheduler requires a normal IRQ service routine to +simply increment the system tick. */ +/* The preemptive scheduler is defined as "naked" as the full context is saved +on entry as part of the context switch. */ +#pragma shadow_registers = full // Naked. +static void vTick( void ) +{ + /* Save the context of the interrupted task. */ + portSAVE_CONTEXT_OS_INT(); + + #if( configTICK_USE_TC==1 ) + /* Clear the interrupt flag. */ + prvClearTcInt(); + #else + /* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ) + clock cycles from now. */ + prvScheduleNextTick(); + #endif + + /* Because FreeRTOS is not supposed to run with nested interrupts, put all OS + calls in a critical section . */ + portENTER_CRITICAL(); + vTaskIncrementTick(); + portEXIT_CRITICAL(); + + /* Restore the context of the "elected task". */ + portRESTORE_CONTEXT_OS_INT(); +} +/*-----------------------------------------------------------*/ + +#pragma shadow_registers = full // Naked. +void SCALLYield( void ) +{ + /* Save the context of the interrupted task. */ + portSAVE_CONTEXT_SCALL(); + vTaskSwitchContext(); + portRESTORE_CONTEXT_SCALL(); +} +/*-----------------------------------------------------------*/ + +/* The code generated by the GCC compiler uses the stack in different ways at +different optimisation levels. The interrupt flags can therefore not always +be saved to the stack. Instead the critical section nesting level is stored +in a variable, which is then saved as part of the stack context. */ +#pragma optimize = no_inline +void vPortEnterCritical( void ) +{ + /* Disable interrupts */ + portDISABLE_INTERRUPTS(); + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +#pragma optimize = no_inline +void vPortExitCritical( void ) +{ + if(ulCriticalNesting > portNO_CRITICAL_NESTING) + { + ulCriticalNesting--; + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Enable all interrupt/exception. */ + portENABLE_INTERRUPTS(); + } + } +} +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. */ + + /* When the task starts, it will expect to find the function parameter in R12. */ + pxTopOfStack--; + *pxTopOfStack-- = ( portSTACK_TYPE ) 0x08080808; /* R8 */ + *pxTopOfStack-- = ( portSTACK_TYPE ) 0x09090909; /* R9 */ + *pxTopOfStack-- = ( portSTACK_TYPE ) 0x0A0A0A0A; /* R10 */ + *pxTopOfStack-- = ( portSTACK_TYPE ) 0x0B0B0B0B; /* R11 */ + *pxTopOfStack-- = ( portSTACK_TYPE ) pvParameters; /* R12 */ + *pxTopOfStack-- = ( portSTACK_TYPE ) 0xDEADBEEF; /* R14/LR */ + *pxTopOfStack-- = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; /* R15/PC */ + *pxTopOfStack-- = ( portSTACK_TYPE ) portINITIAL_SR; /* SR */ + *pxTopOfStack-- = ( portSTACK_TYPE ) 0xFF0000FF; /* R0 */ + *pxTopOfStack-- = ( portSTACK_TYPE ) 0x01010101; /* R1 */ + *pxTopOfStack-- = ( portSTACK_TYPE ) 0x02020202; /* R2 */ + *pxTopOfStack-- = ( portSTACK_TYPE ) 0x03030303; /* R3 */ + *pxTopOfStack-- = ( portSTACK_TYPE ) 0x04040404; /* R4 */ + *pxTopOfStack-- = ( portSTACK_TYPE ) 0x05050505; /* R5 */ + *pxTopOfStack-- = ( portSTACK_TYPE ) 0x06060606; /* R6 */ + *pxTopOfStack-- = ( portSTACK_TYPE ) 0x07070707; /* R7 */ + *pxTopOfStack = ( portSTACK_TYPE ) portNO_CRITICAL_NESTING; /* ulCriticalNesting */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xPortStartScheduler( void ) +{ + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + portRESTORE_CONTEXT(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the AVR32 port will require this function as there + is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +/* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ) +clock cycles from now. */ +#if( configTICK_USE_TC==0 ) + static void prvScheduleFirstTick(void) + { + unsigned long lCycles; + + lCycles = Get_system_register(AVR32_COUNT); + lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ); + // If lCycles ends up to be 0, make it 1 so that the COMPARE and exception + // generation feature does not get disabled. + if(0 == lCycles) + { + lCycles++; + } + Set_system_register(AVR32_COMPARE, lCycles); + } + + #pragma optimize = no_inline + static void prvScheduleNextTick(void) + { + unsigned long lCycles, lCount; + + lCycles = Get_system_register(AVR32_COMPARE); + lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ); + // If lCycles ends up to be 0, make it 1 so that the COMPARE and exception + // generation feature does not get disabled. + if(0 == lCycles) + { + lCycles++; + } + lCount = Get_system_register(AVR32_COUNT); + if( lCycles < lCount ) + { // We missed a tick, recover for the next. + lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ); + } + Set_system_register(AVR32_COMPARE, lCycles); + } +#else + #pragma optimize = no_inline + static void prvClearTcInt(void) + { + AVR32_TC.channel[configTICK_TC_CHANNEL].sr; + } +#endif +/*-----------------------------------------------------------*/ + +/* Setup the timer to generate the tick interrupts. */ +static void prvSetupTimerInterrupt(void) +{ + #if( configTICK_USE_TC==1 ) + + volatile avr32_tc_t *tc = &AVR32_TC; + + // Options for waveform genration. + tc_waveform_opt_t waveform_opt = + { + .channel = configTICK_TC_CHANNEL, /* Channel selection. */ + + .bswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOB. */ + .beevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOB. */ + .bcpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOB. */ + .bcpb = TC_EVT_EFFECT_NOOP, /* RB compare effect on TIOB. */ + + .aswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOA. */ + .aeevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOA. */ + .acpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOA: toggle. */ + .acpa = TC_EVT_EFFECT_NOOP, /* RA compare effect on TIOA: toggle (other possibilities are none, set and clear). */ + + .wavsel = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER,/* Waveform selection: Up mode without automatic trigger on RC compare. */ + .enetrg = FALSE, /* External event trigger enable. */ + .eevt = 0, /* External event selection. */ + .eevtedg = TC_SEL_NO_EDGE, /* External event edge selection. */ + .cpcdis = FALSE, /* Counter disable when RC compare. */ + .cpcstop = FALSE, /* Counter clock stopped with RC compare. */ + + .burst = FALSE, /* Burst signal selection. */ + .clki = FALSE, /* Clock inversion. */ + .tcclks = TC_CLOCK_SOURCE_TC2 /* Internal source clock 2. */ + }; + + tc_interrupt_t tc_interrupt = + { + .etrgs=0, + .ldrbs=0, + .ldras=0, + .cpcs =1, + .cpbs =0, + .cpas =0, + .lovrs=0, + .covfs=0, + }; + + #endif + + /* Disable all interrupt/exception. */ + portDISABLE_INTERRUPTS(); + + /* Register the compare interrupt handler to the interrupt controller and + enable the compare interrupt. */ + + #if( configTICK_USE_TC==1 ) + { + INTC_register_interrupt((__int_handler)&vTick, configTICK_TC_IRQ, INT0); + + /* Initialize the timer/counter. */ + tc_init_waveform(tc, &waveform_opt); + + /* Set the compare triggers. + Remember TC counter is 16-bits, so counting second is not possible! + That's why we configure it to count ms. */ + tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ / 4) / configTICK_RATE_HZ ); + + tc_configure_interrupts( tc, configTICK_TC_CHANNEL, &tc_interrupt ); + + /* Start the timer/counter. */ + tc_start(tc, configTICK_TC_CHANNEL); + } + #else + { + INTC_register_interrupt((__int_handler)&vTick, AVR32_CORE_COMPARE_IRQ, INT0); + prvScheduleFirstTick(); + } + #endif +} diff --git a/20080212/Source/portable/IAR/AVR32_UC3/portmacro.h b/20080212/Source/portable/IAR/AVR32_UC3/portmacro.h new file mode 100644 index 000000000..5b819dec4 --- /dev/null +++ b/20080212/Source/portable/IAR/AVR32_UC3/portmacro.h @@ -0,0 +1,666 @@ +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief FreeRTOS port header for AVR32 UC3. + * + * - Compiler: IAR EWAVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + *****************************************************************************/ + +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ +#include +#include "intc.h" +#include "compiler.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned portLONG +#define portBASE_TYPE portLONG + +#define TASK_DELAY_MS(x) ( (x) /portTICK_RATE_MS ) +#define TASK_DELAY_S(x) ( (x)*1000 /portTICK_RATE_MS ) +#define TASK_DELAY_MIN(x) ( (x)*60*1000/portTICK_RATE_MS ) + +#define configTICK_TC_IRQ ATPASTE2(AVR32_TC_IRQ, configTICK_TC_CHANNEL) + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 4 +#define portNOP() {__asm__ __volatile__ ("nop");} +/*-----------------------------------------------------------*/ + + +/*-----------------------------------------------------------*/ + +/* INTC-specific. */ +#define DISABLE_ALL_EXCEPTIONS() Disable_global_exception() +#define ENABLE_ALL_EXCEPTIONS() Enable_global_exception() + +#define DISABLE_ALL_INTERRUPTS() Disable_global_interrupt() +#define ENABLE_ALL_INTERRUPTS() Enable_global_interrupt() + +#define DISABLE_INT_LEVEL(int_lev) Disable_interrupt_level(int_lev) +#define ENABLE_INT_LEVEL(int_lev) Enable_interrupt_level(int_lev) + + +/* + * Debug trace. + * Activated if and only if configDBG is nonzero. + * Prints a formatted string to stdout. + * The current source file name and line number are output with a colon before + * the formatted string. + * A carriage return and a linefeed are appended to the output. + * stdout is redirected to the USART configured by configDBG_USART. + * The parameters are the same as for the standard printf function. + * There is no return value. + * SHALL NOT BE CALLED FROM WITHIN AN INTERRUPT as fputs and printf use malloc, + * which is interrupt-unsafe with the current __malloc_lock and __malloc_unlock. + */ +#if configDBG + #define portDBG_TRACE(...) \ + { \ + fputs(__FILE__ ":" ASTRINGZ(__LINE__) ": ", stdout); \ + printf(__VA_ARGS__); \ + fputs("\r\n", stdout); \ + } +#else + #define portDBG_TRACE(...) +#endif + + +/* Critical section management. */ +#define portDISABLE_INTERRUPTS() DISABLE_ALL_INTERRUPTS() +#define portENABLE_INTERRUPTS() ENABLE_ALL_INTERRUPTS() + + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); + + +/* Added as there is no such function in FreeRTOS. */ +extern void *pvPortRealloc( void *pv, size_t xSize ); +/*-----------------------------------------------------------*/ + + +/*=============================================================================================*/ + +/* + * Restore Context for cases other than INTi. + */ +#define portRESTORE_CONTEXT() \ +{ \ + extern volatile unsigned portLONG ulCriticalNesting; \ + extern volatile void *volatile pxCurrentTCB; \ + \ + __asm__ __volatile__ ( \ + /* Set SP to point to new stack */ \ + "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ + "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ + "ld.w r0, r8[0] \n\t"\ + "ld.w sp, r0[0] \n\t"\ + \ + /* Restore ulCriticalNesting variable */ \ + "ld.w r0, sp++ \n\t"\ + "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ + "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ + "st.w r8[0], r0 \n\t"\ + \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t"\ + /* R0-R7 should not be used below this line */ \ + /* Skip PC and SR (will do it at the end) */ \ + "sub sp, -2*4 \n\t"\ + /* Restore R8..R12 and LR */ \ + "ldm sp++, r8-r12, lr \n\t"\ + /* Restore SR */ \ + "ld.w r0, sp[-8*4] \n\t" /* R0 is modified, is restored later. */\ + "mtsr "ASTRINGZ(AVR32_SR)", r0 \n\t"\ + /* Restore r0 */ \ + "ld.w r0, sp[-9*4] \n\t"\ + /* Restore PC */ \ + "ld.w pc, sp[-7*4]" /* Get PC from stack - PC is the 7th register saved */ \ + ); \ + \ + /* Force import of global symbols from assembly */ \ + ulCriticalNesting; \ + pxCurrentTCB; \ +} + + +/* + * portSAVE_CONTEXT_INT() and portRESTORE_CONTEXT_INT(): for INT0..3 exceptions. + * portSAVE_CONTEXT_SCALL() and portRESTORE_CONTEXT_SCALL(): for the scall exception. + * + * Had to make different versions because registers saved on the system stack + * are not the same between INT0..3 exceptions and the scall exception. + */ + +// Task context stack layout: + // R8 (*) + // R9 (*) + // R10 (*) + // R11 (*) + // R12 (*) + // R14/LR (*) + // R15/PC (*) + // SR (*) + // R0 + // R1 + // R2 + // R3 + // R4 + // R5 + // R6 + // R7 + // ulCriticalNesting +// (*) automatically done for INT0..INT3, but not for SCALL + +/* + * The ISR used for the scheduler tick depends on whether the cooperative or + * the preemptive scheduler is being used. + */ +#if configUSE_PREEMPTION == 0 + +/* + * portSAVE_CONTEXT_OS_INT() for OS Tick exception. + */ +#define portSAVE_CONTEXT_OS_INT() \ +{ \ + /* Save R0..R7 */ \ + __asm__ __volatile__ ("stm --sp, r0-r7"); \ + \ + /* With the cooperative scheduler, as there is no context switch by interrupt, */ \ + /* there is also no context save. */ \ +} + +/* + * portRESTORE_CONTEXT_OS_INT() for Tick exception. + */ +#define portRESTORE_CONTEXT_OS_INT() \ +{ \ + __asm__ __volatile__ ( \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t"\ + \ + /* With the cooperative scheduler, as there is no context switch by interrupt, */ \ + /* there is also no context restore. */ \ + "rete" \ + ); \ +} + +#else + +/* + * portSAVE_CONTEXT_OS_INT() for OS Tick exception. + */ +#define portSAVE_CONTEXT_OS_INT() \ +{ \ + extern volatile unsigned portLONG ulCriticalNesting; \ + extern volatile void *volatile pxCurrentTCB; \ + \ + /* When we come here */ \ + /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \ + \ + __asm__ __volatile__ ( \ + /* Save R0..R7 */ \ + "stm --sp, r0-r7 \n\t"\ + \ + /* Save ulCriticalNesting variable - R0 is overwritten */ \ + "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ + "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ + "ld.w r0, r8[0] \n\t"\ + "st.w --sp, r0 \n\t"\ + \ + /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \ + /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ + /* level and allow other lower interrupt level to occur). */ \ + /* In this case we don't want to do a task switch because we don't know what the stack */ \ + /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \ + /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \ + /* will just be restoring the interrupt handler, no way!!! */ \ + /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \ + "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\ + "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\ + "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\ + "brhi LABEL_INT_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)" \n\t"\ + \ + /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \ + /* NOTE: we don't enter a critical section here because all interrupt handlers */ \ + /* MUST perform a SAVE_CONTEXT/RESTORE_CONTEXT in the same way as */ \ + /* portSAVE_CONTEXT_OS_INT/port_RESTORE_CONTEXT_OS_INT if they call OS functions. */ \ + /* => all interrupt handlers must use portENTER_SWITCHING_ISR/portEXIT_SWITCHING_ISR. */ \ + "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ + "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ + "ld.w r0, r8[0] \n\t"\ + "st.w r0[0], sp \n"\ + \ + "LABEL_INT_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)":" \ + ); \ +} + +/* + * portRESTORE_CONTEXT_OS_INT() for Tick exception. + */ +#define portRESTORE_CONTEXT_OS_INT() \ +{ \ + extern volatile unsigned portLONG ulCriticalNesting; \ + extern volatile void *volatile pxCurrentTCB; \ + \ + /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \ + /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ + /* level and allow other lower interrupt level to occur). */ \ + /* In this case we don't want to do a task switch because we don't know what the stack */ \ + /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \ + /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \ + /* will just be restoring the interrupt handler, no way!!! */ \ + __asm__ __volatile__ ( \ + "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\ + "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\ + "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\ + "brhi LABEL_INT_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__) \ + ); \ + \ + /* Else */ \ + /* because it is here safe, always call vTaskSwitchContext() since an OS tick occurred. */ \ + /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */\ + portENTER_CRITICAL(); \ + vTaskSwitchContext(); \ + portEXIT_CRITICAL(); \ + \ + /* Restore all registers */ \ + \ + __asm__ __volatile__ ( \ + /* Set SP to point to new stack */ \ + "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ + "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ + "ld.w r0, r8[0] \n\t"\ + "ld.w sp, r0[0] \n"\ + \ + "LABEL_INT_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)": \n\t"\ + \ + /* Restore ulCriticalNesting variable */ \ + "ld.w r0, sp++ \n\t"\ + "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ + "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ + "st.w r8[0], r0 \n\t"\ + \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t"\ + \ + /* Now, the stack should be R8..R12, LR, PC and SR */ \ + "rete" \ + ); \ + \ + /* Force import of global symbols from assembly */ \ + ulCriticalNesting; \ + pxCurrentTCB; \ +} + +#endif + + +/* + * portSAVE_CONTEXT_SCALL() for SupervisorCALL exception. + * + * NOTE: taskYIELD()(== SCALL) MUST NOT be called in a mode > supervisor mode. + * + */ +#define portSAVE_CONTEXT_SCALL() \ +{ \ + extern volatile unsigned portLONG ulCriticalNesting; \ + extern volatile void *volatile pxCurrentTCB; \ + \ + /* Warning: the stack layout after SCALL doesn't match the one after an interrupt. */ \ + /* If SR[M2:M0] == 001 */ \ + /* PC and SR are on the stack. */ \ + /* Else (other modes) */ \ + /* Nothing on the stack. */ \ + \ + /* WARNING NOTE: the else case cannot happen as it is strictly forbidden to call */ \ + /* vTaskDelay() and vTaskDelayUntil() OS functions (that result in a taskYield()) */ \ + /* in an interrupt|exception handler. */ \ + \ + __asm__ __volatile__ ( \ + /* in order to save R0-R7 */ \ + "sub sp, 6*4 \n\t"\ + /* Save R0..R7 */ \ + "stm --sp, r0-r7 \n\t"\ + \ + /* in order to save R8-R12 and LR */ \ + /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \ + "sub r7, sp,-16*4 \n\t"\ + /* Copy PC and SR in other places in the stack. */ \ + "ld.w r0, r7[-2*4] \n\t" /* Read SR */\ + "st.w r7[-8*4], r0 \n\t" /* Copy SR */\ + "ld.w r0, r7[-1*4] \n\t" /* Read PC */\ + "st.w r7[-7*4], r0 \n\t" /* Copy PC */\ + \ + /* Save R8..R12 and LR on the stack. */ \ + "stm --r7, r8-r12, lr \n\t"\ + \ + /* Arriving here we have the following stack organizations: */ \ + /* R8..R12, LR, PC, SR, R0..R7. */ \ + \ + /* Now we can finalize the save. */ \ + \ + /* Save ulCriticalNesting variable - R0 is overwritten */ \ + "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ + "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ + "ld.w r0, r8[0] \n\t"\ + "st.w --sp, r0" \ + ); \ + \ + /* Disable the its which may cause a context switch (i.e. cause a change of */ \ + /* pxCurrentTCB). */ \ + /* Basically, all accesses to the pxCurrentTCB structure should be put in a */ \ + /* critical section because it is a global structure. */ \ + portENTER_CRITICAL(); \ + \ + /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \ + __asm__ __volatile__ ( \ + "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ + "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ + "ld.w r0, r8[0] \n\t"\ + "st.w r0[0], sp" \ + ); \ +} + +/* + * portRESTORE_CONTEXT() for SupervisorCALL exception. + */ +#define portRESTORE_CONTEXT_SCALL() \ +{ \ + extern volatile unsigned portLONG ulCriticalNesting; \ + extern volatile void *volatile pxCurrentTCB; \ + \ + /* Restore all registers */ \ + \ + /* Set SP to point to new stack */ \ + __asm__ __volatile__ ( \ + "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ + "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ + "ld.w r0, r8[0] \n\t"\ + "ld.w sp, r0[0]" \ + ); \ + \ + /* Leave pxCurrentTCB variable access critical section */ \ + portEXIT_CRITICAL(); \ + \ + __asm__ __volatile__ ( \ + /* Restore ulCriticalNesting variable */ \ + "ld.w r0, sp++ \n\t"\ + "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ + "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ + "st.w r8[0], r0 \n\t"\ + \ + /* skip PC and SR */ \ + /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \ + "sub r7, sp, -10*4 \n\t"\ + /* Restore r8-r12 and LR */ \ + "ldm r7++, r8-r12, lr \n\t"\ + \ + /* RETS will take care of the extra PC and SR restore. */ \ + /* So, we have to prepare the stack for this. */ \ + "ld.w r0, r7[-8*4] \n\t" /* Read SR */\ + "st.w r7[-2*4], r0 \n\t" /* Copy SR */\ + "ld.w r0, r7[-7*4] \n\t" /* Read PC */\ + "st.w r7[-1*4], r0 \n\t" /* Copy PC */\ + \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t"\ + \ + "sub sp, -6*4 \n\t"\ + \ + "rets" \ + ); \ + \ + /* Force import of global symbols from assembly */ \ + ulCriticalNesting; \ + pxCurrentTCB; \ +} + + +/* + * The ISR used depends on whether the cooperative or + * the preemptive scheduler is being used. + */ +#if configUSE_PREEMPTION == 0 + +/* + * ISR entry and exit macros. These are only required if a task switch + * is required from the ISR. + */ +#define portENTER_SWITCHING_ISR() \ +{ \ + /* Save R0..R7 */ \ + __asm__ __volatile__ ("stm --sp, r0-r7"); \ + \ + /* With the cooperative scheduler, as there is no context switch by interrupt, */ \ + /* there is also no context save. */ \ +} + +/* + * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1 + */ +#define portEXIT_SWITCHING_ISR() \ +{ \ + __asm__ __volatile__ ( \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t"\ + \ + /* With the cooperative scheduler, as there is no context switch by interrupt, */ \ + /* there is also no context restore. */ \ + "rete" \ + ); \ +} + +#else + +/* + * ISR entry and exit macros. These are only required if a task switch + * is required from the ISR. + */ +#define portENTER_SWITCHING_ISR() \ +{ \ + extern volatile unsigned portLONG ulCriticalNesting; \ + extern volatile void *volatile pxCurrentTCB; \ + \ + /* When we come here */ \ + /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \ + \ + __asm__ __volatile__ ( \ + /* Save R0..R7 */ \ + "stm --sp, r0-r7 \n\t"\ + \ + /* Save ulCriticalNesting variable - R0 is overwritten */ \ + "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ + "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ + "ld.w r0, r8[0] \n\t"\ + "st.w --sp, r0 \n\t"\ + \ + /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \ + /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ + /* level and allow other lower interrupt level to occur). */ \ + /* In this case we don't want to do a task switch because we don't know what the stack */ \ + /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \ + /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \ + /* will just be restoring the interrupt handler, no way!!! */ \ + /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \ + "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\ + "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\ + "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\ + "brhi LABEL_ISR_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)" \n\t"\ + \ + /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \ + "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ + "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ + "ld.w r0, r8[0] \n\t"\ + "st.w r0[0], sp \n"\ + \ + "LABEL_ISR_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)":" \ + ); \ +} + + +/* + * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1 + */ +#define portEXIT_SWITCHING_ISR() \ +{ \ + extern volatile unsigned portLONG ulCriticalNesting; \ + extern volatile void *volatile pxCurrentTCB; \ + \ + __asm__ __volatile__ ( \ + /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \ + /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ + /* level and allow other lower interrupt level to occur). */ \ + /* In this case it's of no use to switch context and restore a new SP because we purposedly */ \ + /* did not previously save SP in its TCB. */ \ + "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\ + "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\ + "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\ + "brhi LABEL_ISR_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)" \n\t"\ + \ + /* If a switch is required then we just need to call */ \ + /* vTaskSwitchContext() as the context has already been */ \ + /* saved. */ \ + "cp.w r12, 1 \n\t" /* Check if Switch context is required. */\ + "brne LABEL_ISR_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)":C" \ + ); \ + \ + /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */\ + portENTER_CRITICAL(); \ + vTaskSwitchContext(); \ + portEXIT_CRITICAL(); \ + \ + __asm__ __volatile__ ( \ + "LABEL_ISR_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)": \n\t"\ + /* Restore the context of which ever task is now the highest */ \ + /* priority that is ready to run. */ \ + \ + /* Restore all registers */ \ + \ + /* Set SP to point to new stack */ \ + "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ + "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ + "ld.w r0, r8[0] \n\t"\ + "ld.w sp, r0[0] \n"\ + \ + "LABEL_ISR_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)": \n\t"\ + \ + /* Restore ulCriticalNesting variable */ \ + "ld.w r0, sp++ \n\t"\ + "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ + "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ + "st.w r8[0], r0 \n\t"\ + \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t"\ + \ + /* Now, the stack should be R8..R12, LR, PC and SR */ \ + "rete" \ + ); \ + \ + /* Force import of global symbols from assembly */ \ + ulCriticalNesting; \ + pxCurrentTCB; \ +} + +#endif + + +#define portYIELD() {__asm__ __volatile__ ("scall");} + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#define inline + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ diff --git a/20080212/Source/portable/IAR/AVR32_UC3/read.c b/20080212/Source/portable/IAR/AVR32_UC3/read.c new file mode 100644 index 000000000..925c196f7 --- /dev/null +++ b/20080212/Source/portable/IAR/AVR32_UC3/read.c @@ -0,0 +1,93 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief System-specific implementation of the \ref __read function used by + the standard library. + * + * - Compiler: IAR EWAVR32 + * - Supported devices: All AVR32 devices with a USART module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include +#include +#include "usart.h" + + +_STD_BEGIN + + +#pragma module_name = "?__read" + + +extern volatile avr32_usart_t *volatile stdio_usart_base; + + +/*! \brief Reads a number of bytes, at most \a size, into the memory area + * pointed to by \a buffer. + * + * \param handle File handle to read from. + * \param buffer Pointer to buffer to write read bytes to. + * \param size Number of bytes to read. + * + * \return The number of bytes read, \c 0 at the end of the file, or + * \c _LLIO_ERROR on failure. + */ +size_t __read(int handle, unsigned char *buffer, size_t size) +{ + int nChars = 0; + + // This implementation only reads from stdin. + // For all other file handles, it returns failure. + if (handle != _LLIO_STDIN) + { + return _LLIO_ERROR; + } + + for (; size > 0; --size) + { + int c = usart_getchar(stdio_usart_base); + if (c < 0) + break; + + *buffer++ = c; + ++nChars; + } + + return nChars; +} + + +_STD_END diff --git a/20080212/Source/portable/IAR/AVR32_UC3/write.c b/20080212/Source/portable/IAR/AVR32_UC3/write.c new file mode 100644 index 000000000..7dc8a71bb --- /dev/null +++ b/20080212/Source/portable/IAR/AVR32_UC3/write.c @@ -0,0 +1,103 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief System-specific implementation of the \ref __write function used by + the standard library. + * + * - Compiler: IAR EWAVR32 + * - Supported devices: All AVR32 devices with a USART module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include +#include +#include "usart.h" + + +_STD_BEGIN + + +#pragma module_name = "?__write" + + +//! Pointer to the base of the USART module instance to use for stdio. +__no_init volatile avr32_usart_t *volatile stdio_usart_base; + + +/*! \brief Writes a number of bytes, at most \a size, from the memory area + * pointed to by \a buffer. + * + * If \a buffer is zero then \ref __write performs flushing of internal buffers, + * if any. In this case, \a handle can be \c -1 to indicate that all handles + * should be flushed. + * + * \param handle File handle to write to. + * \param buffer Pointer to buffer to read bytes to write from. + * \param size Number of bytes to write. + * + * \return The number of bytes written, or \c _LLIO_ERROR on failure. + */ +size_t __write(int handle, const unsigned char *buffer, size_t size) +{ + size_t nChars = 0; + + if (buffer == 0) + { + // This means that we should flush internal buffers. + return 0; + } + + // This implementation only writes to stdout and stderr. + // For all other file handles, it returns failure. + if (handle != _LLIO_STDOUT && handle != _LLIO_STDERR) + { + return _LLIO_ERROR; + } + + for (; size != 0; --size) + { + if (usart_putchar(stdio_usart_base, *buffer++) < 0) + { + return _LLIO_ERROR; + } + + ++nChars; + } + + return nChars; +} + + +_STD_END diff --git a/20080212/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64.h b/20080212/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64.h new file mode 100644 index 000000000..8f9ddb43a --- /dev/null +++ b/20080212/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64.h @@ -0,0 +1,1914 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// The software is delivered "AS IS" without warranty or condition of any +// kind, either express, implied or statutory. This includes without +// limitation any warranty or condition with respect to merchantability or +// fitness for any particular purpose, or against the infringements of +// intellectual property rights of others. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM7S64.h +// Object : AT91SAM7S64 definitions +// Generated : AT91 SW Application Group 07/16/2004 (07:43:08) +// +// CVS Reference : /AT91SAM7S64.pl/1.12/Mon Jul 12 13:02:30 2004// +// CVS Reference : /SYSC_SAM7Sxx.pl/1.5/Mon Jul 12 16:22:12 2004// +// CVS Reference : /MC_SAM02.pl/1.3/Wed Mar 10 08:37:04 2004// +// CVS Reference : /UDP_1765B.pl/1.3/Fri Aug 2 14:45:38 2002// +// CVS Reference : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// +// CVS Reference : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004// +// CVS Reference : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// +// CVS Reference : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003// +// CVS Reference : /US_1739C.pl/1.2/Mon Jul 12 17:26:24 2004// +// CVS Reference : /SPI2.pl/1.2/Fri Oct 17 08:13:40 2003// +// CVS Reference : /SSC_1762A.pl/1.2/Fri Nov 8 13:26:40 2002// +// CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// +// CVS Reference : /TWI_1761B.pl/1.4/Fri Feb 7 10:30:08 2003// +// CVS Reference : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:24 2002// +// CVS Reference : /ADC_SAM.pl/1.7/Fri Oct 17 08:12:38 2003// +// CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// +// ---------------------------------------------------------------------------- + +#ifndef AT91SAM7S64_H +#define AT91SAM7S64_H + +typedef volatile unsigned int AT91_REG;// Hardware register definition + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** +typedef struct _AT91S_SYSC { + AT91_REG SYSC_AIC_SMR[32]; // Source Mode Register + AT91_REG SYSC_AIC_SVR[32]; // Source Vector Register + AT91_REG SYSC_AIC_IVR; // IRQ Vector Register + AT91_REG SYSC_AIC_FVR; // FIQ Vector Register + AT91_REG SYSC_AIC_ISR; // Interrupt Status Register + AT91_REG SYSC_AIC_IPR; // Interrupt Pending Register + AT91_REG SYSC_AIC_IMR; // Interrupt Mask Register + AT91_REG SYSC_AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG SYSC_AIC_IECR; // Interrupt Enable Command Register + AT91_REG SYSC_AIC_IDCR; // Interrupt Disable Command Register + AT91_REG SYSC_AIC_ICCR; // Interrupt Clear Command Register + AT91_REG SYSC_AIC_ISCR; // Interrupt Set Command Register + AT91_REG SYSC_AIC_EOICR; // End of Interrupt Command Register + AT91_REG SYSC_AIC_SPU; // Spurious Vector Register + AT91_REG SYSC_AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG SYSC_AIC_FFER; // Fast Forcing Enable Register + AT91_REG SYSC_AIC_FFDR; // Fast Forcing Disable Register + AT91_REG SYSC_AIC_FFSR; // Fast Forcing Status Register + AT91_REG Reserved2[45]; // + AT91_REG SYSC_DBGU_CR; // Control Register + AT91_REG SYSC_DBGU_MR; // Mode Register + AT91_REG SYSC_DBGU_IER; // Interrupt Enable Register + AT91_REG SYSC_DBGU_IDR; // Interrupt Disable Register + AT91_REG SYSC_DBGU_IMR; // Interrupt Mask Register + AT91_REG SYSC_DBGU_CSR; // Channel Status Register + AT91_REG SYSC_DBGU_RHR; // Receiver Holding Register + AT91_REG SYSC_DBGU_THR; // Transmitter Holding Register + AT91_REG SYSC_DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved3[7]; // + AT91_REG SYSC_DBGU_C1R; // Chip ID1 Register + AT91_REG SYSC_DBGU_C2R; // Chip ID2 Register + AT91_REG SYSC_DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved4[45]; // + AT91_REG SYSC_DBGU_RPR; // Receive Pointer Register + AT91_REG SYSC_DBGU_RCR; // Receive Counter Register + AT91_REG SYSC_DBGU_TPR; // Transmit Pointer Register + AT91_REG SYSC_DBGU_TCR; // Transmit Counter Register + AT91_REG SYSC_DBGU_RNPR; // Receive Next Pointer Register + AT91_REG SYSC_DBGU_RNCR; // Receive Next Counter Register + AT91_REG SYSC_DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG SYSC_DBGU_TNCR; // Transmit Next Counter Register + AT91_REG SYSC_DBGU_PTCR; // PDC Transfer Control Register + AT91_REG SYSC_DBGU_PTSR; // PDC Transfer Status Register + AT91_REG Reserved5[54]; // + AT91_REG SYSC_PIOA_PER; // PIO Enable Register + AT91_REG SYSC_PIOA_PDR; // PIO Disable Register + AT91_REG SYSC_PIOA_PSR; // PIO Status Register + AT91_REG Reserved6[1]; // + AT91_REG SYSC_PIOA_OER; // Output Enable Register + AT91_REG SYSC_PIOA_ODR; // Output Disable Registerr + AT91_REG SYSC_PIOA_OSR; // Output Status Register + AT91_REG Reserved7[1]; // + AT91_REG SYSC_PIOA_IFER; // Input Filter Enable Register + AT91_REG SYSC_PIOA_IFDR; // Input Filter Disable Register + AT91_REG SYSC_PIOA_IFSR; // Input Filter Status Register + AT91_REG Reserved8[1]; // + AT91_REG SYSC_PIOA_SODR; // Set Output Data Register + AT91_REG SYSC_PIOA_CODR; // Clear Output Data Register + AT91_REG SYSC_PIOA_ODSR; // Output Data Status Register + AT91_REG SYSC_PIOA_PDSR; // Pin Data Status Register + AT91_REG SYSC_PIOA_IER; // Interrupt Enable Register + AT91_REG SYSC_PIOA_IDR; // Interrupt Disable Register + AT91_REG SYSC_PIOA_IMR; // Interrupt Mask Register + AT91_REG SYSC_PIOA_ISR; // Interrupt Status Register + AT91_REG SYSC_PIOA_MDER; // Multi-driver Enable Register + AT91_REG SYSC_PIOA_MDDR; // Multi-driver Disable Register + AT91_REG SYSC_PIOA_MDSR; // Multi-driver Status Register + AT91_REG Reserved9[1]; // + AT91_REG SYSC_PIOA_PPUDR; // Pull-up Disable Register + AT91_REG SYSC_PIOA_PPUER; // Pull-up Enable Register + AT91_REG SYSC_PIOA_PPUSR; // Pad Pull-up Status Register + AT91_REG Reserved10[1]; // + AT91_REG SYSC_PIOA_ASR; // Select A Register + AT91_REG SYSC_PIOA_BSR; // Select B Register + AT91_REG SYSC_PIOA_ABSR; // AB Select Status Register + AT91_REG Reserved11[9]; // + AT91_REG SYSC_PIOA_OWER; // Output Write Enable Register + AT91_REG SYSC_PIOA_OWDR; // Output Write Disable Register + AT91_REG SYSC_PIOA_OWSR; // Output Write Status Register + AT91_REG Reserved12[469]; // + AT91_REG SYSC_PMC_SCER; // System Clock Enable Register + AT91_REG SYSC_PMC_SCDR; // System Clock Disable Register + AT91_REG SYSC_PMC_SCSR; // System Clock Status Register + AT91_REG Reserved13[1]; // + AT91_REG SYSC_PMC_PCER; // Peripheral Clock Enable Register + AT91_REG SYSC_PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG SYSC_PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved14[1]; // + AT91_REG SYSC_PMC_MOR; // Main Oscillator Register + AT91_REG SYSC_PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved15[1]; // + AT91_REG SYSC_PMC_PLLR; // PLL Register + AT91_REG SYSC_PMC_MCKR; // Master Clock Register + AT91_REG Reserved16[3]; // + AT91_REG SYSC_PMC_PCKR[8]; // Programmable Clock Register + AT91_REG SYSC_PMC_IER; // Interrupt Enable Register + AT91_REG SYSC_PMC_IDR; // Interrupt Disable Register + AT91_REG SYSC_PMC_SR; // Status Register + AT91_REG SYSC_PMC_IMR; // Interrupt Mask Register + AT91_REG Reserved17[36]; // + AT91_REG SYSC_RSTC_RCR; // Reset Control Register + AT91_REG SYSC_RSTC_RSR; // Reset Status Register + AT91_REG SYSC_RSTC_RMR; // Reset Mode Register + AT91_REG Reserved18[5]; // + AT91_REG SYSC_RTTC_RTMR; // Real-time Mode Register + AT91_REG SYSC_RTTC_RTAR; // Real-time Alarm Register + AT91_REG SYSC_RTTC_RTVR; // Real-time Value Register + AT91_REG SYSC_RTTC_RTSR; // Real-time Status Register + AT91_REG SYSC_PITC_PIMR; // Period Interval Mode Register + AT91_REG SYSC_PITC_PISR; // Period Interval Status Register + AT91_REG SYSC_PITC_PIVR; // Period Interval Value Register + AT91_REG SYSC_PITC_PIIR; // Period Interval Image Register + AT91_REG SYSC_WDTC_WDCR; // Watchdog Control Register + AT91_REG SYSC_WDTC_WDMR; // Watchdog Mode Register + AT91_REG SYSC_WDTC_WDSR; // Watchdog Status Register + AT91_REG Reserved19[5]; // + AT91_REG SYSC_SYSC_VRPM; // Voltage Regulator Power Mode Register +} AT91S_SYSC, *AT91PS_SYSC; + +// -------- VRPM : (SYSC Offset: 0xd60) Voltage Regulator Power Mode Register -------- +#define AT91C_SYSC_PSTDBY ((unsigned int) 0x1 << 0) // (SYSC) Voltage Regulator Power Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +typedef struct _AT91S_AIC { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register +} AT91S_AIC, *AT91PS_AIC; + +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive +#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +typedef struct _AT91S_DBGU { + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved0[7]; // + AT91_REG DBGU_C1R; // Chip ID1 Register + AT91_REG DBGU_C2R; // Chip ID2 Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved1[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register +} AT91S_DBGU, *AT91PS_DBGU; + +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral Data Controller +// ***************************************************************************** +typedef struct _AT91S_PDC { + AT91_REG PDC_RPR; // Receive Pointer Register + AT91_REG PDC_RCR; // Receive Counter Register + AT91_REG PDC_TPR; // Transmit Pointer Register + AT91_REG PDC_TCR; // Transmit Counter Register + AT91_REG PDC_RNPR; // Receive Next Pointer Register + AT91_REG PDC_RNCR; // Receive Next Counter Register + AT91_REG PDC_TNPR; // Transmit Next Pointer Register + AT91_REG PDC_TNCR; // Transmit Next Counter Register + AT91_REG PDC_PTCR; // PDC Transfer Control Register + AT91_REG PDC_PTSR; // PDC Transfer Status Register +} AT91S_PDC, *AT91PS_PDC; + +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +typedef struct _AT91S_PIO { + AT91_REG PIO_PER; // PIO Enable Register + AT91_REG PIO_PDR; // PIO Disable Register + AT91_REG PIO_PSR; // PIO Status Register + AT91_REG Reserved0[1]; // + AT91_REG PIO_OER; // Output Enable Register + AT91_REG PIO_ODR; // Output Disable Registerr + AT91_REG PIO_OSR; // Output Status Register + AT91_REG Reserved1[1]; // + AT91_REG PIO_IFER; // Input Filter Enable Register + AT91_REG PIO_IFDR; // Input Filter Disable Register + AT91_REG PIO_IFSR; // Input Filter Status Register + AT91_REG Reserved2[1]; // + AT91_REG PIO_SODR; // Set Output Data Register + AT91_REG PIO_CODR; // Clear Output Data Register + AT91_REG PIO_ODSR; // Output Data Status Register + AT91_REG PIO_PDSR; // Pin Data Status Register + AT91_REG PIO_IER; // Interrupt Enable Register + AT91_REG PIO_IDR; // Interrupt Disable Register + AT91_REG PIO_IMR; // Interrupt Mask Register + AT91_REG PIO_ISR; // Interrupt Status Register + AT91_REG PIO_MDER; // Multi-driver Enable Register + AT91_REG PIO_MDDR; // Multi-driver Disable Register + AT91_REG PIO_MDSR; // Multi-driver Status Register + AT91_REG Reserved3[1]; // + AT91_REG PIO_PPUDR; // Pull-up Disable Register + AT91_REG PIO_PPUER; // Pull-up Enable Register + AT91_REG PIO_PPUSR; // Pad Pull-up Status Register + AT91_REG Reserved4[1]; // + AT91_REG PIO_ASR; // Select A Register + AT91_REG PIO_BSR; // Select B Register + AT91_REG PIO_ABSR; // AB Select Status Register + AT91_REG Reserved5[9]; // + AT91_REG PIO_OWER; // Output Write Enable Register + AT91_REG PIO_OWDR; // Output Write Disable Register + AT91_REG PIO_OWSR; // Output Write Status Register +} AT91S_PIO, *AT91PS_PIO; + + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +typedef struct _AT91S_CKGR { + AT91_REG CKGR_MOR; // Main Oscillator Register + AT91_REG CKGR_MCFR; // Main Clock Frequency Register + AT91_REG Reserved0[1]; // + AT91_REG CKGR_PLLR; // PLL Register +} AT91S_CKGR, *AT91PS_CKGR; + +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +typedef struct _AT91S_PMC { + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved0[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved1[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved2[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved3[3]; // + AT91_REG PMC_PCKR[8]; // Programmable Clock Register + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register +} AT91S_PMC, *AT91PS_PMC; + +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +typedef struct _AT91S_RSTC { + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register +} AT91S_RSTC, *AT91PS_RSTC; + +// -------- SYSC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_SYSC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset +#define AT91C_SYSC_ICERST ((unsigned int) 0x1 << 1) // (RSTC) ICE Interface Reset +#define AT91C_SYSC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_SYSC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset +#define AT91C_SYSC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password +// -------- SYSC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_SYSC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status +#define AT91C_SYSC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brown-out Detection Status +#define AT91C_SYSC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type +#define AT91C_SYSC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_SYSC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_SYSC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_SYSC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_SYSC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brown-out Reset. +#define AT91C_SYSC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level +#define AT91C_SYSC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- SYSC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_SYSC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_SYSC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_SYSC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable +#define AT91C_SYSC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brown-out Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_RTTC { + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register +} AT91S_RTTC, *AT91PS_RTTC; + +// -------- SYSC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_SYSC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_SYSC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_SYSC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_SYSC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- SYSC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_SYSC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value +// -------- SYSC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_SYSC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value +// -------- SYSC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_SYSC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_SYSC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_PITC { + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register +} AT91S_PITC, *AT91PS_PITC; + +// -------- SYSC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_SYSC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_SYSC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_SYSC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- SYSC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_SYSC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- SYSC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_SYSC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_SYSC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- SYSC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_WDTC { + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register +} AT91S_WDTC, *AT91PS_WDTC; + +// -------- SYSC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_SYSC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart +// -------- SYSC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_SYSC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_SYSC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_SYSC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_SYSC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_SYSC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_SYSC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_SYSC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_SYSC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- SYSC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_SYSC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_SYSC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +typedef struct _AT91S_MC { + AT91_REG MC_RCR; // MC Remap Control Register + AT91_REG MC_ASR; // MC Abort Status Register + AT91_REG MC_AASR; // MC Abort Address Status Register + AT91_REG Reserved0[21]; // + AT91_REG MC_FMR; // MC Flash Mode Register + AT91_REG MC_FCR; // MC Flash Command Register + AT91_REG MC_FSR; // MC Flash Status Register +} AT91S_MC, *AT91PS_MC; + +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready +#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error +#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error +#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming +#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State +#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number +// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command +#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit. +#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number +#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key +// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- +#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status +#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +typedef struct _AT91S_SPI { + AT91_REG SPI_CR; // Control Register + AT91_REG SPI_MR; // Mode Register + AT91_REG SPI_RDR; // Receive Data Register + AT91_REG SPI_TDR; // Transmit Data Register + AT91_REG SPI_SR; // Status Register + AT91_REG SPI_IER; // Interrupt Enable Register + AT91_REG SPI_IDR; // Interrupt Disable Register + AT91_REG SPI_IMR; // Interrupt Mask Register + AT91_REG Reserved0[4]; // + AT91_REG SPI_CSR[4]; // Chip Select Register + AT91_REG Reserved1[48]; // + AT91_REG SPI_RPR; // Receive Pointer Register + AT91_REG SPI_RCR; // Receive Counter Register + AT91_REG SPI_TPR; // Transmit Pointer Register + AT91_REG SPI_TCR; // Transmit Counter Register + AT91_REG SPI_RNPR; // Receive Next Pointer Register + AT91_REG SPI_RNCR; // Receive Next Counter Register + AT91_REG SPI_TNPR; // Transmit Next Pointer Register + AT91_REG SPI_TNCR; // Transmit Next Counter Register + AT91_REG SPI_PTCR; // PDC Transfer Control Register + AT91_REG SPI_PTSR; // PDC Transfer Status Register +} AT91S_SPI, *AT91PS_SPI; + +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 2) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +typedef struct _AT91S_ADC { + AT91_REG ADC_CR; // ADC Control Register + AT91_REG ADC_MR; // ADC Mode Register + AT91_REG Reserved0[2]; // + AT91_REG ADC_CHER; // ADC Channel Enable Register + AT91_REG ADC_CHDR; // ADC Channel Disable Register + AT91_REG ADC_CHSR; // ADC Channel Status Register + AT91_REG ADC_SR; // ADC Status Register + AT91_REG ADC_LCDR; // ADC Last Converted Data Register + AT91_REG ADC_IER; // ADC Interrupt Enable Register + AT91_REG ADC_IDR; // ADC Interrupt Disable Register + AT91_REG ADC_IMR; // ADC Interrupt Mask Register + AT91_REG ADC_CDR0; // ADC Channel Data Register 0 + AT91_REG ADC_CDR1; // ADC Channel Data Register 1 + AT91_REG ADC_CDR2; // ADC Channel Data Register 2 + AT91_REG ADC_CDR3; // ADC Channel Data Register 3 + AT91_REG ADC_CDR4; // ADC Channel Data Register 4 + AT91_REG ADC_CDR5; // ADC Channel Data Register 5 + AT91_REG ADC_CDR6; // ADC Channel Data Register 6 + AT91_REG ADC_CDR7; // ADC Channel Data Register 7 + AT91_REG Reserved1[44]; // + AT91_REG ADC_RPR; // Receive Pointer Register + AT91_REG ADC_RCR; // Receive Counter Register + AT91_REG ADC_TPR; // Transmit Pointer Register + AT91_REG ADC_TCR; // Transmit Counter Register + AT91_REG ADC_RNPR; // Receive Next Pointer Register + AT91_REG ADC_RNCR; // Receive Next Counter Register + AT91_REG ADC_TNPR; // Transmit Next Pointer Register + AT91_REG ADC_TNCR; // Transmit Next Counter Register + AT91_REG ADC_PTCR; // PDC Transfer Control Register + AT91_REG ADC_PTSR; // PDC Transfer Status Register +} AT91S_ADC, *AT91PS_ADC; + +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +typedef struct _AT91S_SSC { + AT91_REG SSC_CR; // Control Register + AT91_REG SSC_CMR; // Clock Mode Register + AT91_REG Reserved0[2]; // + AT91_REG SSC_RCMR; // Receive Clock ModeRegister + AT91_REG SSC_RFMR; // Receive Frame Mode Register + AT91_REG SSC_TCMR; // Transmit Clock Mode Register + AT91_REG SSC_TFMR; // Transmit Frame Mode Register + AT91_REG SSC_RHR; // Receive Holding Register + AT91_REG SSC_THR; // Transmit Holding Register + AT91_REG Reserved1[2]; // + AT91_REG SSC_RSHR; // Receive Sync Holding Register + AT91_REG SSC_TSHR; // Transmit Sync Holding Register + AT91_REG SSC_RC0R; // Receive Compare 0 Register + AT91_REG SSC_RC1R; // Receive Compare 1 Register + AT91_REG SSC_SR; // Status Register + AT91_REG SSC_IER; // Interrupt Enable Register + AT91_REG SSC_IDR; // Interrupt Disable Register + AT91_REG SSC_IMR; // Interrupt Mask Register + AT91_REG Reserved2[44]; // + AT91_REG SSC_RPR; // Receive Pointer Register + AT91_REG SSC_RCR; // Receive Counter Register + AT91_REG SSC_TPR; // Transmit Pointer Register + AT91_REG SSC_TCR; // Transmit Counter Register + AT91_REG SSC_RNPR; // Receive Next Pointer Register + AT91_REG SSC_RNCR; // Receive Next Counter Register + AT91_REG SSC_TNPR; // Transmit Next Pointer Register + AT91_REG SSC_TNCR; // Transmit Next Counter Register + AT91_REG SSC_PTCR; // PDC Transfer Control Register + AT91_REG SSC_PTSR; // PDC Transfer Status Register +} AT91S_SSC, *AT91PS_SSC; + +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin +#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_CKG ((unsigned int) 0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection +#define AT91C_SSC_CKG_NONE ((unsigned int) 0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock +#define AT91C_SSC_CKG_LOW ((unsigned int) 0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low +#define AT91C_SSC_CKG_HIGH ((unsigned int) 0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High +#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STOP ((unsigned int) 0x1 << 12) // (SSC) Receive Stop Selection +#define AT91C_SSC_STTOUT ((unsigned int) 0x1 << 15) // (SSC) Receive/Transmit Start Output Selection +#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_CP0 ((unsigned int) 0x1 << 8) // (SSC) Compare 0 +#define AT91C_SSC_CP1 ((unsigned int) 0x1 << 9) // (SSC) Compare 1 +#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +typedef struct _AT91S_USART { + AT91_REG US_CR; // Control Register + AT91_REG US_MR; // Mode Register + AT91_REG US_IER; // Interrupt Enable Register + AT91_REG US_IDR; // Interrupt Disable Register + AT91_REG US_IMR; // Interrupt Mask Register + AT91_REG US_CSR; // Channel Status Register + AT91_REG US_RHR; // Receiver Holding Register + AT91_REG US_THR; // Transmitter Holding Register + AT91_REG US_BRGR; // Baud Rate Generator Register + AT91_REG US_RTOR; // Receiver Time-out Register + AT91_REG US_TTGR; // Transmitter Time-guard Register + AT91_REG Reserved0[5]; // + AT91_REG US_FIDI; // FI_DI_Ratio Register + AT91_REG US_NER; // Nb Errors Register + AT91_REG US_XXR; // XON_XOFF Register + AT91_REG US_IF; // IRDA_FILTER Register + AT91_REG Reserved1[44]; // + AT91_REG US_RPR; // Receive Pointer Register + AT91_REG US_RCR; // Receive Counter Register + AT91_REG US_TPR; // Transmit Pointer Register + AT91_REG US_TCR; // Transmit Counter Register + AT91_REG US_RNPR; // Receive Next Pointer Register + AT91_REG US_RNCR; // Receive Next Counter Register + AT91_REG US_TNPR; // Transmit Next Pointer Register + AT91_REG US_TNCR; // Transmit Next Counter Register + AT91_REG US_PTCR; // PDC Transfer Control Register + AT91_REG US_PTSR; // PDC Transfer Status Register +} AT91S_USART, *AT91PS_USART; + +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (USART) Reset Status Bits +#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +typedef struct _AT91S_TWI { + AT91_REG TWI_CR; // Control Register + AT91_REG TWI_MMR; // Master Mode Register + AT91_REG TWI_SMR; // Slave Mode Register + AT91_REG TWI_IADR; // Internal Address Register + AT91_REG TWI_CWGR; // Clock Waveform Generator Register + AT91_REG Reserved0[3]; // + AT91_REG TWI_SR; // Status Register + AT91_REG TWI_IER; // Interrupt Enable Register + AT91_REG TWI_IDR; // Interrupt Disable Register + AT91_REG TWI_IMR; // Interrupt Mask Register + AT91_REG TWI_RHR; // Receive Holding Register + AT91_REG TWI_THR; // Transmit Holding Register +} AT91S_TWI, *AT91PS_TWI; + +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SVEN ((unsigned int) 0x1 << 4) // (TWI) TWI Slave Transfer Enabled +#define AT91C_TWI_SVDIS ((unsigned int) 0x1 << 5) // (TWI) TWI Slave Transfer Disabled +#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address +// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- +#define AT91C_TWI_SADR ((unsigned int) 0x7F << 16) // (TWI) Slave Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_SVREAD ((unsigned int) 0x1 << 3) // (TWI) Slave Read +#define AT91C_TWI_SVACC ((unsigned int) 0x1 << 4) // (TWI) Slave Access +#define AT91C_TWI_GCACC ((unsigned int) 0x1 << 5) // (TWI) General Call Access +#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged +#define AT91C_TWI_ARBLST ((unsigned int) 0x1 << 9) // (TWI) Arbitration Lost +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +typedef struct _AT91S_TC { + AT91_REG TC_CCR; // Channel Control Register + AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) + AT91_REG Reserved0[2]; // + AT91_REG TC_CV; // Counter Value + AT91_REG TC_RA; // Register A + AT91_REG TC_RB; // Register B + AT91_REG TC_RC; // Register C + AT91_REG TC_SR; // Status Register + AT91_REG TC_IER; // Interrupt Enable Register + AT91_REG TC_IDR; // Interrupt Disable Register + AT91_REG TC_IMR; // Interrupt Mask Register +} AT91S_TC, *AT91PS_TC; + +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_NONE ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_RISING ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_FALLING ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_BOTH ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) +#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRCS ((unsigned int) 0x1 << 7) // (TC) External Trigger +#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +typedef struct _AT91S_TCB { + AT91S_TC TCB_TC0; // TC Channel 0 + AT91_REG Reserved0[4]; // + AT91S_TC TCB_TC1; // TC Channel 1 + AT91_REG Reserved1[4]; // + AT91S_TC TCB_TC2; // TC Channel 2 + AT91_REG Reserved2[4]; // + AT91_REG TCB_BCR; // TC Block Control Register + AT91_REG TCB_BMR; // TC Block Mode Register +} AT91S_TCB, *AT91PS_TCB; + +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S ((unsigned int) 0x1 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S ((unsigned int) 0x1 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S ((unsigned int) 0x1 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA2 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +typedef struct _AT91S_PWMC_CH { + AT91_REG PWMC_CMR; // Channel Mode Register + AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register + AT91_REG PWMC_CPRDR; // Channel Period Register + AT91_REG PWMC_CCNTR; // Channel Counter Register + AT91_REG PWMC_CUPDR; // Channel Update Register + AT91_REG PWMC_Reserved[3]; // Reserved +} AT91S_PWMC_CH, *AT91PS_PWMC_CH; + +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +typedef struct _AT91S_PWMC { + AT91_REG PWMC_MR; // PWMC Mode Register + AT91_REG PWMC_ENA; // PWMC Enable Register + AT91_REG PWMC_DIS; // PWMC Disable Register + AT91_REG PWMC_SR; // PWMC Status Register + AT91_REG PWMC_IER; // PWMC Interrupt Enable Register + AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register + AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register + AT91_REG PWMC_ISR; // PWMC Interrupt Status Register + AT91_REG Reserved0[55]; // + AT91_REG PWMC_VR; // PWMC Version Register + AT91_REG Reserved1[64]; // + AT91S_PWMC_CH PWMC_CH[32]; // PWMC Channel 0 +} AT91S_PWMC, *AT91PS_PWMC; + +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3 +#define AT91C_PWMC_CHID4 ((unsigned int) 0x1 << 4) // (PWMC) Channel ID 4 +#define AT91C_PWMC_CHID5 ((unsigned int) 0x1 << 5) // (PWMC) Channel ID 5 +#define AT91C_PWMC_CHID6 ((unsigned int) 0x1 << 6) // (PWMC) Channel ID 6 +#define AT91C_PWMC_CHID7 ((unsigned int) 0x1 << 7) // (PWMC) Channel ID 7 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +typedef struct _AT91S_UDP { + AT91_REG UDP_NUM; // Frame Number Register + AT91_REG UDP_GLBSTATE; // Global State Register + AT91_REG UDP_FADDR; // Function Address Register + AT91_REG Reserved0[1]; // + AT91_REG UDP_IER; // Interrupt Enable Register + AT91_REG UDP_IDR; // Interrupt Disable Register + AT91_REG UDP_IMR; // Interrupt Mask Register + AT91_REG UDP_ISR; // Interrupt Status Register + AT91_REG UDP_ICR; // Interrupt Clear Register + AT91_REG Reserved1[1]; // + AT91_REG UDP_RSTEP; // Reset Endpoint Register + AT91_REG Reserved2[1]; // + AT91_REG UDP_CSR[8]; // Endpoint Control and Status Register + AT91_REG UDP_FDR[8]; // Endpoint FIFO Data Register +} AT91S_UDP, *AT91PS_UDP; + +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured +#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 2) // (UDP) Remote Wake Up Enable +#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt +#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt +#define AT91C_UDP_EPINT6 ((unsigned int) 0x1 << 6) // (UDP) Endpoint 6 Interrupt +#define AT91C_UDP_EPINT7 ((unsigned int) 0x1 << 7) // (UDP) Endpoint 7 Interrupt +#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3 +#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4 +#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5 +#define AT91C_UDP_EP6 ((unsigned int) 0x1 << 6) // (UDP) Reset Endpoint 6 +#define AT91C_UDP_EP7 ((unsigned int) 0x1 << 7) // (UDP) Reset Endpoint 7 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7S64 +// ***************************************************************************** +// ========== Register definition for SYSC peripheral ========== +#define AT91C_SYSC_SYSC_VRPM ((AT91_REG *) 0xFFFFFD60) // (SYSC) Voltage Regulator Power Mode Register +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register +#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_C2R ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID2 Register +#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_C1R ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID1 Register +#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register +#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register +#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pad Pull-up Status Register +#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register +#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register +#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register +#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register +#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register +#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register +#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register +#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register +#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register +// ========== Register definition for PDC_SPI peripheral ========== +#define AT91C_SPI_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register +#define AT91C_SPI_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register +#define AT91C_SPI_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register +#define AT91C_SPI_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI) Transmit Pointer Register +#define AT91C_SPI_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI) Receive Pointer Register +#define AT91C_SPI_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register +#define AT91C_SPI_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register +#define AT91C_SPI_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register +#define AT91C_SPI_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register +#define AT91C_SPI_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register +// ========== Register definition for SPI peripheral ========== +#define AT91C_SPI_CSR ((AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register +#define AT91C_SPI_IDR ((AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register +#define AT91C_SPI_SR ((AT91_REG *) 0xFFFE0010) // (SPI) Status Register +#define AT91C_SPI_RDR ((AT91_REG *) 0xFFFE0008) // (SPI) Receive Data Register +#define AT91C_SPI_CR ((AT91_REG *) 0xFFFE0000) // (SPI) Control Register +#define AT91C_SPI_IMR ((AT91_REG *) 0xFFFE001C) // (SPI) Interrupt Mask Register +#define AT91C_SPI_IER ((AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register +#define AT91C_SPI_TDR ((AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register +#define AT91C_SPI_MR ((AT91_REG *) 0xFFFE0004) // (SPI) Mode Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register +#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register +#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_RC0R ((AT91_REG *) 0xFFFD4038) // (SSC) Receive Compare 0 Register +#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_RC1R ((AT91_REG *) 0xFFFD403C) // (SSC) Receive Compare 1 Register +#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register +#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_XXR ((AT91_REG *) 0xFFFC4048) // (US1) XON_XOFF Register +#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register +#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register +#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_XXR ((AT91_REG *) 0xFFFC0048) // (US0) XON_XOFF Register +#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register +#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register +#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_SMR ((AT91_REG *) 0xFFFB8008) // (TWI) Slave Mode Register +#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register +#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value +#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register +#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register +#define AT91C_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register +#define AT91C_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +#define AT91C_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register +#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register +#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7S64 +// ***************************************************************************** +#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_PWM0 ((unsigned int) AT91C_PIO_PA0) // PWM Channel 0 +#define AT91C_PA0_TIOA0 ((unsigned int) AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_PWM1 ((unsigned int) AT91C_PIO_PA1) // PWM Channel 1 +#define AT91C_PA1_TIOB0 ((unsigned int) AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_DTXD ((unsigned int) AT91C_PIO_PA10) // DBGU Debug Transmit Data +#define AT91C_PA10_NPCS2 ((unsigned int) AT91C_PIO_PA10) // SPI Peripheral Chip Select 2 +#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_NPCS0 ((unsigned int) AT91C_PIO_PA11) // SPI Peripheral Chip Select 0 +#define AT91C_PA11_PWM0 ((unsigned int) AT91C_PIO_PA11) // PWM Channel 0 +#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_MISO ((unsigned int) AT91C_PIO_PA12) // SPI Master In Slave +#define AT91C_PA12_PWM1 ((unsigned int) AT91C_PIO_PA12) // PWM Channel 1 +#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_MOSI ((unsigned int) AT91C_PIO_PA13) // SPI Master Out Slave +#define AT91C_PA13_PWM2 ((unsigned int) AT91C_PIO_PA13) // PWM Channel 2 +#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_SPCK ((unsigned int) AT91C_PIO_PA14) // SPI Serial Clock +#define AT91C_PA14_PWM3 ((unsigned int) AT91C_PIO_PA14) // PWM Channel 3 +#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_TF ((unsigned int) AT91C_PIO_PA15) // SSC Transmit Frame Sync +#define AT91C_PA15_TIOA1 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_TK ((unsigned int) AT91C_PIO_PA16) // SSC Transmit Clock +#define AT91C_PA16_TIOB1 ((unsigned int) AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_TD ((unsigned int) AT91C_PIO_PA17) // SSC Transmit data +#define AT91C_PA17_PCK1 ((unsigned int) AT91C_PIO_PA17) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_RD ((unsigned int) AT91C_PIO_PA18) // SSC Receive Data +#define AT91C_PA18_PCK2 ((unsigned int) AT91C_PIO_PA18) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_RK ((unsigned int) AT91C_PIO_PA19) // SSC Receive Clock +#define AT91C_PA19_FIQ ((unsigned int) AT91C_PIO_PA19) // AIC Fast Interrupt Input +#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_PWM2 ((unsigned int) AT91C_PIO_PA2) // PWM Channel 2 +#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_RF ((unsigned int) AT91C_PIO_PA20) // SSC Receive Frame Sync +#define AT91C_PA20_IRQ0 ((unsigned int) AT91C_PIO_PA20) // External Interrupt 0 +#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_RXD1 ((unsigned int) AT91C_PIO_PA21) // USART 1 Receive Data +#define AT91C_PA21_PCK1 ((unsigned int) AT91C_PIO_PA21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TXD1 ((unsigned int) AT91C_PIO_PA22) // USART 1 Transmit Data +#define AT91C_PA22_NPCS3 ((unsigned int) AT91C_PIO_PA22) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_SCK1 ((unsigned int) AT91C_PIO_PA23) // USART 1 Serial Clock +#define AT91C_PA23_PWM0 ((unsigned int) AT91C_PIO_PA23) // PWM Channel 0 +#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RTS1 ((unsigned int) AT91C_PIO_PA24) // USART 1 Ready To Send +#define AT91C_PA24_PWM1 ((unsigned int) AT91C_PIO_PA24) // PWM Channel 1 +#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_CTS1 ((unsigned int) AT91C_PIO_PA25) // USART 1 Clear To Send +#define AT91C_PA25_PWM2 ((unsigned int) AT91C_PIO_PA25) // PWM Channel 2 +#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_DCD1 ((unsigned int) AT91C_PIO_PA26) // USART 1 Data Carrier Detect +#define AT91C_PA26_TIOA2 ((unsigned int) AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DTR1 ((unsigned int) AT91C_PIO_PA27) // USART 1 Data Terminal ready +#define AT91C_PA27_TIOB2 ((unsigned int) AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DSR1 ((unsigned int) AT91C_PIO_PA28) // USART 1 Data Set ready +#define AT91C_PA28_TCLK1 ((unsigned int) AT91C_PIO_PA28) // Timer Counter 1 external clock input +#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_RI1 ((unsigned int) AT91C_PIO_PA29) // USART 1 Ring Indicator +#define AT91C_PA29_TCLK2 ((unsigned int) AT91C_PIO_PA29) // Timer Counter 2 external clock input +#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_TWD ((unsigned int) AT91C_PIO_PA3) // TWI Two-wire Serial Data +#define AT91C_PA3_NPCS3 ((unsigned int) AT91C_PIO_PA3) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ1 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 1 +#define AT91C_PA30_NPCS2 ((unsigned int) AT91C_PIO_PA30) // SPI Peripheral Chip Select 2 +#define AT91C_PIO_PA31 ((unsigned int) 1 << 31) // Pin Controlled by PA31 +#define AT91C_PA31_NPCS1 ((unsigned int) AT91C_PIO_PA31) // SPI Peripheral Chip Select 1 +#define AT91C_PA31_PCK2 ((unsigned int) AT91C_PIO_PA31) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_TWCK ((unsigned int) AT91C_PIO_PA4) // TWI Two-wire Serial Clock +#define AT91C_PA4_TCLK0 ((unsigned int) AT91C_PIO_PA4) // Timer Counter 0 external clock input +#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD0 ((unsigned int) AT91C_PIO_PA5) // USART 0 Receive Data +#define AT91C_PA5_NPCS3 ((unsigned int) AT91C_PIO_PA5) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD0 ((unsigned int) AT91C_PIO_PA6) // USART 0 Transmit Data +#define AT91C_PA6_PCK0 ((unsigned int) AT91C_PIO_PA6) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_RTS0 ((unsigned int) AT91C_PIO_PA7) // USART 0 Ready To Send +#define AT91C_PA7_PWM3 ((unsigned int) AT91C_PIO_PA7) // PWM Channel 3 +#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_CTS0 ((unsigned int) AT91C_PIO_PA8) // USART 0 Clear To Send +#define AT91C_PA8_ADTRG ((unsigned int) AT91C_PIO_PA8) // ADC External Trigger +#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_DRXD ((unsigned int) AT91C_PIO_PA9) // DBGU Debug Receive Data +#define AT91C_PA9_NPCS1 ((unsigned int) AT91C_PIO_PA9) // SPI Peripheral Chip Select 1 + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64 +// ***************************************************************************** +#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral +#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller +#define AT91C_ID_3_Reserved ((unsigned int) 3) // Reserved +#define AT91C_ID_ADC ((unsigned int) 4) // Analog-to-Digital Converter +#define AT91C_ID_SPI ((unsigned int) 5) // Serial Peripheral Interface +#define AT91C_ID_US0 ((unsigned int) 6) // USART 0 +#define AT91C_ID_US1 ((unsigned int) 7) // USART 1 +#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface +#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller +#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port +#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0 +#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1 +#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2 +#define AT91C_ID_15_Reserved ((unsigned int) 15) // Reserved +#define AT91C_ID_16_Reserved ((unsigned int) 16) // Reserved +#define AT91C_ID_17_Reserved ((unsigned int) 17) // Reserved +#define AT91C_ID_18_Reserved ((unsigned int) 18) // Reserved +#define AT91C_ID_19_Reserved ((unsigned int) 19) // Reserved +#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved +#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved +#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved +#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved +#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved +#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved +#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved +#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved +#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved +#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved +#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1) + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7S64 +// ***************************************************************************** +#define AT91C_BASE_SYSC ((AT91PS_SYSC) 0xFFFFF000) // (SYSC) Base Address +#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_PDC_SPI ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI) Base Address +#define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) // (SPI) Base Address +#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address +#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64 +// ***************************************************************************** +#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE ((unsigned int) 0x00004000) // Internal SRAM size in byte (16 Kbyte) +#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address +#define AT91C_IFLASH_SIZE ((unsigned int) 0x00010000) // Internal ROM size in byte (64 Kbyte) + +#endif diff --git a/20080212/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h b/20080212/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h new file mode 100644 index 000000000..7d2657a20 --- /dev/null +++ b/20080212/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h @@ -0,0 +1,1812 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// The software is delivered "AS IS" without warranty or condition of any +// kind, either express, implied or statutory. This includes without +// limitation any warranty or condition with respect to merchantability or +// fitness for any particular purpose, or against the infringements of +// intellectual property rights of others. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM7S64.h +// Object : AT91SAM7S64 definitions +// Generated : AT91 SW Application Group 07/16/2004 (07:43:09) +// +// CVS Reference : /AT91SAM7S64.pl/1.12/Mon Jul 12 13:02:30 2004// +// CVS Reference : /SYSC_SAM7Sxx.pl/1.5/Mon Jul 12 16:22:12 2004// +// CVS Reference : /MC_SAM02.pl/1.3/Wed Mar 10 08:37:04 2004// +// CVS Reference : /UDP_1765B.pl/1.3/Fri Aug 2 14:45:38 2002// +// CVS Reference : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// +// CVS Reference : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004// +// CVS Reference : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// +// CVS Reference : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003// +// CVS Reference : /US_1739C.pl/1.2/Mon Jul 12 17:26:24 2004// +// CVS Reference : /SPI2.pl/1.2/Fri Oct 17 08:13:40 2003// +// CVS Reference : /SSC_1762A.pl/1.2/Fri Nov 8 13:26:40 2002// +// CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// +// CVS Reference : /TWI_1761B.pl/1.4/Fri Feb 7 10:30:08 2003// +// CVS Reference : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:24 2002// +// CVS Reference : /ADC_SAM.pl/1.7/Fri Oct 17 08:12:38 2003// +// CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// +// ---------------------------------------------------------------------------- + +// Hardware register definition + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** +// *** Register offset in AT91S_SYSC structure *** +#define SYSC_AIC_SMR ( 0) // Source Mode Register +#define SYSC_AIC_SVR (128) // Source Vector Register +#define SYSC_AIC_IVR (256) // IRQ Vector Register +#define SYSC_AIC_FVR (260) // FIQ Vector Register +#define SYSC_AIC_ISR (264) // Interrupt Status Register +#define SYSC_AIC_IPR (268) // Interrupt Pending Register +#define SYSC_AIC_IMR (272) // Interrupt Mask Register +#define SYSC_AIC_CISR (276) // Core Interrupt Status Register +#define SYSC_AIC_IECR (288) // Interrupt Enable Command Register +#define SYSC_AIC_IDCR (292) // Interrupt Disable Command Register +#define SYSC_AIC_ICCR (296) // Interrupt Clear Command Register +#define SYSC_AIC_ISCR (300) // Interrupt Set Command Register +#define SYSC_AIC_EOICR (304) // End of Interrupt Command Register +#define SYSC_AIC_SPU (308) // Spurious Vector Register +#define SYSC_AIC_DCR (312) // Debug Control Register (Protect) +#define SYSC_AIC_FFER (320) // Fast Forcing Enable Register +#define SYSC_AIC_FFDR (324) // Fast Forcing Disable Register +#define SYSC_AIC_FFSR (328) // Fast Forcing Status Register +#define SYSC_DBGU_CR (512) // Control Register +#define SYSC_DBGU_MR (516) // Mode Register +#define SYSC_DBGU_IER (520) // Interrupt Enable Register +#define SYSC_DBGU_IDR (524) // Interrupt Disable Register +#define SYSC_DBGU_IMR (528) // Interrupt Mask Register +#define SYSC_DBGU_CSR (532) // Channel Status Register +#define SYSC_DBGU_RHR (536) // Receiver Holding Register +#define SYSC_DBGU_THR (540) // Transmitter Holding Register +#define SYSC_DBGU_BRGR (544) // Baud Rate Generator Register +#define SYSC_DBGU_C1R (576) // Chip ID1 Register +#define SYSC_DBGU_C2R (580) // Chip ID2 Register +#define SYSC_DBGU_FNTR (584) // Force NTRST Register +#define SYSC_DBGU_RPR (768) // Receive Pointer Register +#define SYSC_DBGU_RCR (772) // Receive Counter Register +#define SYSC_DBGU_TPR (776) // Transmit Pointer Register +#define SYSC_DBGU_TCR (780) // Transmit Counter Register +#define SYSC_DBGU_RNPR (784) // Receive Next Pointer Register +#define SYSC_DBGU_RNCR (788) // Receive Next Counter Register +#define SYSC_DBGU_TNPR (792) // Transmit Next Pointer Register +#define SYSC_DBGU_TNCR (796) // Transmit Next Counter Register +#define SYSC_DBGU_PTCR (800) // PDC Transfer Control Register +#define SYSC_DBGU_PTSR (804) // PDC Transfer Status Register +#define SYSC_PIOA_PER (1024) // PIO Enable Register +#define SYSC_PIOA_PDR (1028) // PIO Disable Register +#define SYSC_PIOA_PSR (1032) // PIO Status Register +#define SYSC_PIOA_OER (1040) // Output Enable Register +#define SYSC_PIOA_ODR (1044) // Output Disable Registerr +#define SYSC_PIOA_OSR (1048) // Output Status Register +#define SYSC_PIOA_IFER (1056) // Input Filter Enable Register +#define SYSC_PIOA_IFDR (1060) // Input Filter Disable Register +#define SYSC_PIOA_IFSR (1064) // Input Filter Status Register +#define SYSC_PIOA_SODR (1072) // Set Output Data Register +#define SYSC_PIOA_CODR (1076) // Clear Output Data Register +#define SYSC_PIOA_ODSR (1080) // Output Data Status Register +#define SYSC_PIOA_PDSR (1084) // Pin Data Status Register +#define SYSC_PIOA_IER (1088) // Interrupt Enable Register +#define SYSC_PIOA_IDR (1092) // Interrupt Disable Register +#define SYSC_PIOA_IMR (1096) // Interrupt Mask Register +#define SYSC_PIOA_ISR (1100) // Interrupt Status Register +#define SYSC_PIOA_MDER (1104) // Multi-driver Enable Register +#define SYSC_PIOA_MDDR (1108) // Multi-driver Disable Register +#define SYSC_PIOA_MDSR (1112) // Multi-driver Status Register +#define SYSC_PIOA_PPUDR (1120) // Pull-up Disable Register +#define SYSC_PIOA_PPUER (1124) // Pull-up Enable Register +#define SYSC_PIOA_PPUSR (1128) // Pad Pull-up Status Register +#define SYSC_PIOA_ASR (1136) // Select A Register +#define SYSC_PIOA_BSR (1140) // Select B Register +#define SYSC_PIOA_ABSR (1144) // AB Select Status Register +#define SYSC_PIOA_OWER (1184) // Output Write Enable Register +#define SYSC_PIOA_OWDR (1188) // Output Write Disable Register +#define SYSC_PIOA_OWSR (1192) // Output Write Status Register +#define SYSC_PMC_SCER (3072) // System Clock Enable Register +#define SYSC_PMC_SCDR (3076) // System Clock Disable Register +#define SYSC_PMC_SCSR (3080) // System Clock Status Register +#define SYSC_PMC_PCER (3088) // Peripheral Clock Enable Register +#define SYSC_PMC_PCDR (3092) // Peripheral Clock Disable Register +#define SYSC_PMC_PCSR (3096) // Peripheral Clock Status Register +#define SYSC_PMC_MOR (3104) // Main Oscillator Register +#define SYSC_PMC_MCFR (3108) // Main Clock Frequency Register +#define SYSC_PMC_PLLR (3116) // PLL Register +#define SYSC_PMC_MCKR (3120) // Master Clock Register +#define SYSC_PMC_PCKR (3136) // Programmable Clock Register +#define SYSC_PMC_IER (3168) // Interrupt Enable Register +#define SYSC_PMC_IDR (3172) // Interrupt Disable Register +#define SYSC_PMC_SR (3176) // Status Register +#define SYSC_PMC_IMR (3180) // Interrupt Mask Register +#define SYSC_RSTC_RCR (3328) // Reset Control Register +#define SYSC_RSTC_RSR (3332) // Reset Status Register +#define SYSC_RSTC_RMR (3336) // Reset Mode Register +#define SYSC_RTTC_RTMR (3360) // Real-time Mode Register +#define SYSC_RTTC_RTAR (3364) // Real-time Alarm Register +#define SYSC_RTTC_RTVR (3368) // Real-time Value Register +#define SYSC_RTTC_RTSR (3372) // Real-time Status Register +#define SYSC_PITC_PIMR (3376) // Period Interval Mode Register +#define SYSC_PITC_PISR (3380) // Period Interval Status Register +#define SYSC_PITC_PIVR (3384) // Period Interval Value Register +#define SYSC_PITC_PIIR (3388) // Period Interval Image Register +#define SYSC_WDTC_WDCR (3392) // Watchdog Control Register +#define SYSC_WDTC_WDMR (3396) // Watchdog Mode Register +#define SYSC_WDTC_WDSR (3400) // Watchdog Status Register +#define SYSC_SYSC_VRPM (3424) // Voltage Regulator Power Mode Register +// -------- VRPM : (SYSC Offset: 0xd60) Voltage Regulator Power Mode Register -------- +#define AT91C_SYSC_PSTDBY (0x1 << 0) // (SYSC) Voltage Regulator Power Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +// *** Register offset in AT91S_AIC structure *** +#define AIC_SMR ( 0) // Source Mode Register +#define AIC_SVR (128) // Source Vector Register +#define AIC_IVR (256) // IRQ Vector Register +#define AIC_FVR (260) // FIQ Vector Register +#define AIC_ISR (264) // Interrupt Status Register +#define AIC_IPR (268) // Interrupt Pending Register +#define AIC_IMR (272) // Interrupt Mask Register +#define AIC_CISR (276) // Core Interrupt Status Register +#define AIC_IECR (288) // Interrupt Enable Command Register +#define AIC_IDCR (292) // Interrupt Disable Command Register +#define AIC_ICCR (296) // Interrupt Clear Command Register +#define AIC_ISCR (300) // Interrupt Set Command Register +#define AIC_EOICR (304) // End of Interrupt Command Register +#define AIC_SPU (308) // Spurious Vector Register +#define AIC_DCR (312) // Debug Control Register (Protect) +#define AIC_FFER (320) // Fast Forcing Enable Register +#define AIC_FFDR (324) // Fast Forcing Disable Register +#define AIC_FFSR (328) // Fast Forcing Status Register +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE (0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive +#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED (0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL (0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE (0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +// *** Register offset in AT91S_DBGU structure *** +#define DBGU_CR ( 0) // Control Register +#define DBGU_MR ( 4) // Mode Register +#define DBGU_IER ( 8) // Interrupt Enable Register +#define DBGU_IDR (12) // Interrupt Disable Register +#define DBGU_IMR (16) // Interrupt Mask Register +#define DBGU_CSR (20) // Channel Status Register +#define DBGU_RHR (24) // Receiver Holding Register +#define DBGU_THR (28) // Transmitter Holding Register +#define DBGU_BRGR (32) // Baud Rate Generator Register +#define DBGU_C1R (64) // Chip ID1 Register +#define DBGU_C2R (68) // Chip ID2 Register +#define DBGU_FNTR (72) // Force NTRST Register +#define DBGU_RPR (256) // Receive Pointer Register +#define DBGU_RCR (260) // Receive Counter Register +#define DBGU_TPR (264) // Transmit Pointer Register +#define DBGU_TCR (268) // Transmit Counter Register +#define DBGU_RNPR (272) // Receive Next Pointer Register +#define DBGU_RNCR (276) // Receive Next Counter Register +#define DBGU_TNPR (280) // Transmit Next Pointer Register +#define DBGU_TNCR (284) // Transmit Next Counter Register +#define DBGU_PTCR (288) // PDC Transfer Control Register +#define DBGU_PTSR (292) // PDC Transfer Status Register +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral Data Controller +// ***************************************************************************** +// *** Register offset in AT91S_PDC structure *** +#define PDC_RPR ( 0) // Receive Pointer Register +#define PDC_RCR ( 4) // Receive Counter Register +#define PDC_TPR ( 8) // Transmit Pointer Register +#define PDC_TCR (12) // Transmit Counter Register +#define PDC_RNPR (16) // Receive Next Pointer Register +#define PDC_RNCR (20) // Receive Next Counter Register +#define PDC_TNPR (24) // Transmit Next Pointer Register +#define PDC_TNCR (28) // Transmit Next Counter Register +#define PDC_PTCR (32) // PDC Transfer Control Register +#define PDC_PTSR (36) // PDC Transfer Status Register +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +// *** Register offset in AT91S_PIO structure *** +#define PIO_PER ( 0) // PIO Enable Register +#define PIO_PDR ( 4) // PIO Disable Register +#define PIO_PSR ( 8) // PIO Status Register +#define PIO_OER (16) // Output Enable Register +#define PIO_ODR (20) // Output Disable Registerr +#define PIO_OSR (24) // Output Status Register +#define PIO_IFER (32) // Input Filter Enable Register +#define PIO_IFDR (36) // Input Filter Disable Register +#define PIO_IFSR (40) // Input Filter Status Register +#define PIO_SODR (48) // Set Output Data Register +#define PIO_CODR (52) // Clear Output Data Register +#define PIO_ODSR (56) // Output Data Status Register +#define PIO_PDSR (60) // Pin Data Status Register +#define PIO_IER (64) // Interrupt Enable Register +#define PIO_IDR (68) // Interrupt Disable Register +#define PIO_IMR (72) // Interrupt Mask Register +#define PIO_ISR (76) // Interrupt Status Register +#define PIO_MDER (80) // Multi-driver Enable Register +#define PIO_MDDR (84) // Multi-driver Disable Register +#define PIO_MDSR (88) // Multi-driver Status Register +#define PIO_PPUDR (96) // Pull-up Disable Register +#define PIO_PPUER (100) // Pull-up Enable Register +#define PIO_PPUSR (104) // Pad Pull-up Status Register +#define PIO_ASR (112) // Select A Register +#define PIO_BSR (116) // Select B Register +#define PIO_ABSR (120) // AB Select Status Register +#define PIO_OWER (160) // Output Write Enable Register +#define PIO_OWDR (164) // Output Write Disable Register +#define PIO_OWSR (168) // Output Write Status Register + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +// *** Register offset in AT91S_CKGR structure *** +#define CKGR_MOR ( 0) // Main Oscillator Register +#define CKGR_MCFR ( 4) // Main Clock Frequency Register +#define CKGR_PLLR (12) // PLL Register +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +// *** Register offset in AT91S_PMC structure *** +#define PMC_SCER ( 0) // System Clock Enable Register +#define PMC_SCDR ( 4) // System Clock Disable Register +#define PMC_SCSR ( 8) // System Clock Status Register +#define PMC_PCER (16) // Peripheral Clock Enable Register +#define PMC_PCDR (20) // Peripheral Clock Disable Register +#define PMC_PCSR (24) // Peripheral Clock Status Register +#define PMC_MOR (32) // Main Oscillator Register +#define PMC_MCFR (36) // Main Clock Frequency Register +#define PMC_PLLR (44) // PLL Register +#define PMC_MCKR (48) // Master Clock Register +#define PMC_PCKR (64) // Programmable Clock Register +#define PMC_IER (96) // Interrupt Enable Register +#define PMC_IDR (100) // Interrupt Disable Register +#define PMC_SR (104) // Status Register +#define PMC_IMR (108) // Interrupt Mask Register +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_RSTC structure *** +#define RSTC_RCR ( 0) // Reset Control Register +#define RSTC_RSR ( 4) // Reset Status Register +#define RSTC_RMR ( 8) // Reset Mode Register +// -------- SYSC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_SYSC_PROCRST (0x1 << 0) // (RSTC) Processor Reset +#define AT91C_SYSC_ICERST (0x1 << 1) // (RSTC) ICE Interface Reset +#define AT91C_SYSC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_SYSC_EXTRST (0x1 << 3) // (RSTC) External Reset +#define AT91C_SYSC_KEY (0xFF << 24) // (RSTC) Password +// -------- SYSC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_SYSC_URSTS (0x1 << 0) // (RSTC) User Reset Status +#define AT91C_SYSC_BODSTS (0x1 << 1) // (RSTC) Brown-out Detection Status +#define AT91C_SYSC_RSTTYP (0x7 << 8) // (RSTC) Reset Type +#define AT91C_SYSC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_SYSC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_SYSC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_SYSC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_SYSC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brown-out Reset. +#define AT91C_SYSC_NRSTL (0x1 << 16) // (RSTC) NRST pin level +#define AT91C_SYSC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- SYSC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_SYSC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_SYSC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_SYSC_ERSTL (0xF << 8) // (RSTC) User Reset Enable +#define AT91C_SYSC_BODIEN (0x1 << 16) // (RSTC) Brown-out Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_RTTC structure *** +#define RTTC_RTMR ( 0) // Real-time Mode Register +#define RTTC_RTAR ( 4) // Real-time Alarm Register +#define RTTC_RTVR ( 8) // Real-time Value Register +#define RTTC_RTSR (12) // Real-time Status Register +// -------- SYSC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_SYSC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_SYSC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_SYSC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_SYSC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- SYSC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_SYSC_ALMV (0x0 << 0) // (RTTC) Alarm Value +// -------- SYSC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_SYSC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value +// -------- SYSC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_SYSC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_SYSC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_PITC structure *** +#define PITC_PIMR ( 0) // Period Interval Mode Register +#define PITC_PISR ( 4) // Period Interval Status Register +#define PITC_PIVR ( 8) // Period Interval Value Register +#define PITC_PIIR (12) // Period Interval Image Register +// -------- SYSC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_SYSC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_SYSC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_SYSC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- SYSC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_SYSC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- SYSC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_SYSC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_SYSC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- SYSC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_WDTC structure *** +#define WDTC_WDCR ( 0) // Watchdog Control Register +#define WDTC_WDMR ( 4) // Watchdog Mode Register +#define WDTC_WDSR ( 8) // Watchdog Status Register +// -------- SYSC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_SYSC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart +// -------- SYSC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_SYSC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_SYSC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_SYSC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_SYSC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_SYSC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_SYSC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_SYSC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_SYSC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- SYSC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_SYSC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_SYSC_WDERR (0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_MC structure *** +#define MC_RCR ( 0) // MC Remap Control Register +#define MC_ASR ( 4) // MC Abort Status Register +#define MC_AASR ( 8) // MC Abort Address Status Register +#define MC_FMR (96) // MC Flash Mode Register +#define MC_FCR (100) // MC Flash Command Register +#define MC_FSR (104) // MC Flash Status Register +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready +#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error +#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error +#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming +#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State +#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number +// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command +#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit. +#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number +#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key +// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- +#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status +#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +// *** Register offset in AT91S_SPI structure *** +#define SPI_CR ( 0) // Control Register +#define SPI_MR ( 4) // Mode Register +#define SPI_RDR ( 8) // Receive Data Register +#define SPI_TDR (12) // Transmit Data Register +#define SPI_SR (16) // Status Register +#define SPI_IER (20) // Interrupt Enable Register +#define SPI_IDR (24) // Interrupt Disable Register +#define SPI_IMR (28) // Interrupt Mask Register +#define SPI_CSR (48) // Chip Select Register +#define SPI_RPR (256) // Receive Pointer Register +#define SPI_RCR (260) // Receive Counter Register +#define SPI_TPR (264) // Transmit Pointer Register +#define SPI_TCR (268) // Transmit Counter Register +#define SPI_RNPR (272) // Receive Next Pointer Register +#define SPI_RNCR (276) // Receive Next Counter Register +#define SPI_TNPR (280) // Transmit Next Pointer Register +#define SPI_TNCR (284) // Transmit Next Counter Register +#define SPI_PTCR (288) // PDC Transfer Control Register +#define SPI_PTSR (292) // PDC Transfer Status Register +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT (0x1 << 2) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +// *** Register offset in AT91S_ADC structure *** +#define ADC_CR ( 0) // ADC Control Register +#define ADC_MR ( 4) // ADC Mode Register +#define ADC_CHER (16) // ADC Channel Enable Register +#define ADC_CHDR (20) // ADC Channel Disable Register +#define ADC_CHSR (24) // ADC Channel Status Register +#define ADC_SR (28) // ADC Status Register +#define ADC_LCDR (32) // ADC Last Converted Data Register +#define ADC_IER (36) // ADC Interrupt Enable Register +#define ADC_IDR (40) // ADC Interrupt Disable Register +#define ADC_IMR (44) // ADC Interrupt Mask Register +#define ADC_CDR0 (48) // ADC Channel Data Register 0 +#define ADC_CDR1 (52) // ADC Channel Data Register 1 +#define ADC_CDR2 (56) // ADC Channel Data Register 2 +#define ADC_CDR3 (60) // ADC Channel Data Register 3 +#define ADC_CDR4 (64) // ADC Channel Data Register 4 +#define ADC_CDR5 (68) // ADC Channel Data Register 5 +#define ADC_CDR6 (72) // ADC Channel Data Register 6 +#define ADC_CDR7 (76) // ADC Channel Data Register 7 +#define ADC_RPR (256) // Receive Pointer Register +#define ADC_RCR (260) // Receive Counter Register +#define ADC_TPR (264) // Transmit Pointer Register +#define ADC_TCR (268) // Transmit Counter Register +#define ADC_RNPR (272) // Receive Next Pointer Register +#define ADC_RNCR (276) // Receive Next Counter Register +#define ADC_TNPR (280) // Transmit Next Pointer Register +#define ADC_TNCR (284) // Transmit Next Counter Register +#define ADC_PTCR (288) // PDC Transfer Control Register +#define ADC_PTSR (292) // PDC Transfer Status Register +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_SSC structure *** +#define SSC_CR ( 0) // Control Register +#define SSC_CMR ( 4) // Clock Mode Register +#define SSC_RCMR (16) // Receive Clock ModeRegister +#define SSC_RFMR (20) // Receive Frame Mode Register +#define SSC_TCMR (24) // Transmit Clock Mode Register +#define SSC_TFMR (28) // Transmit Frame Mode Register +#define SSC_RHR (32) // Receive Holding Register +#define SSC_THR (36) // Transmit Holding Register +#define SSC_RSHR (48) // Receive Sync Holding Register +#define SSC_TSHR (52) // Transmit Sync Holding Register +#define SSC_RC0R (56) // Receive Compare 0 Register +#define SSC_RC1R (60) // Receive Compare 1 Register +#define SSC_SR (64) // Status Register +#define SSC_IER (68) // Interrupt Enable Register +#define SSC_IDR (72) // Interrupt Disable Register +#define SSC_IMR (76) // Interrupt Mask Register +#define SSC_RPR (256) // Receive Pointer Register +#define SSC_RCR (260) // Receive Counter Register +#define SSC_TPR (264) // Transmit Pointer Register +#define SSC_TCR (268) // Transmit Counter Register +#define SSC_RNPR (272) // Receive Next Pointer Register +#define SSC_RNCR (276) // Receive Next Counter Register +#define SSC_TNPR (280) // Transmit Next Pointer Register +#define SSC_TNCR (284) // Transmit Next Counter Register +#define SSC_PTCR (288) // PDC Transfer Control Register +#define SSC_PTSR (292) // PDC Transfer Status Register +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin +#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_CKG (0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection +#define AT91C_SSC_CKG_NONE (0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock +#define AT91C_SSC_CKG_LOW (0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low +#define AT91C_SSC_CKG_HIGH (0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High +#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STOP (0x1 << 12) // (SSC) Receive Stop Selection +#define AT91C_SSC_STTOUT (0x1 << 15) // (SSC) Receive/Transmit Start Output Selection +#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_CP0 (0x1 << 8) // (SSC) Compare 0 +#define AT91C_SSC_CP1 (0x1 << 9) // (SSC) Compare 1 +#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +// *** Register offset in AT91S_USART structure *** +#define US_CR ( 0) // Control Register +#define US_MR ( 4) // Mode Register +#define US_IER ( 8) // Interrupt Enable Register +#define US_IDR (12) // Interrupt Disable Register +#define US_IMR (16) // Interrupt Mask Register +#define US_CSR (20) // Channel Status Register +#define US_RHR (24) // Receiver Holding Register +#define US_THR (28) // Transmitter Holding Register +#define US_BRGR (32) // Baud Rate Generator Register +#define US_RTOR (36) // Receiver Time-out Register +#define US_TTGR (40) // Transmitter Time-guard Register +#define US_FIDI (64) // FI_DI_Ratio Register +#define US_NER (68) // Nb Errors Register +#define US_XXR (72) // XON_XOFF Register +#define US_IF (76) // IRDA_FILTER Register +#define US_RPR (256) // Receive Pointer Register +#define US_RCR (260) // Receive Counter Register +#define US_TPR (264) // Transmit Pointer Register +#define US_TCR (268) // Transmit Counter Register +#define US_RNPR (272) // Receive Next Pointer Register +#define US_RNCR (276) // Receive Next Counter Register +#define US_TNPR (280) // Transmit Next Pointer Register +#define US_TNCR (284) // Transmit Next Counter Register +#define US_PTCR (288) // PDC Transfer Control Register +#define US_PTSR (292) // PDC Transfer Status Register +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTSTA (0x1 << 8) // (USART) Reset Status Bits +#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +// *** Register offset in AT91S_TWI structure *** +#define TWI_CR ( 0) // Control Register +#define TWI_MMR ( 4) // Master Mode Register +#define TWI_SMR ( 8) // Slave Mode Register +#define TWI_IADR (12) // Internal Address Register +#define TWI_CWGR (16) // Clock Waveform Generator Register +#define TWI_SR (32) // Status Register +#define TWI_IER (36) // Interrupt Enable Register +#define TWI_IDR (40) // Interrupt Disable Register +#define TWI_IMR (44) // Interrupt Mask Register +#define TWI_RHR (48) // Receive Holding Register +#define TWI_THR (52) // Transmit Holding Register +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SVEN (0x1 << 4) // (TWI) TWI Slave Transfer Enabled +#define AT91C_TWI_SVDIS (0x1 << 5) // (TWI) TWI Slave Transfer Disabled +#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address +// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- +#define AT91C_TWI_SADR (0x7F << 16) // (TWI) Slave Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_SVREAD (0x1 << 3) // (TWI) Slave Read +#define AT91C_TWI_SVACC (0x1 << 4) // (TWI) Slave Access +#define AT91C_TWI_GCACC (0x1 << 5) // (TWI) General Call Access +#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged +#define AT91C_TWI_ARBLST (0x1 << 9) // (TWI) Arbitration Lost +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +// *** Register offset in AT91S_TC structure *** +#define TC_CCR ( 0) // Channel Control Register +#define TC_CMR ( 4) // Channel Mode Register (Capture Mode / Waveform Mode) +#define TC_CV (16) // Counter Value +#define TC_RA (20) // Register A +#define TC_RB (24) // Register B +#define TC_RC (28) // Register C +#define TC_SR (32) // Status Register +#define TC_IER (36) // Interrupt Enable Register +#define TC_IDR (40) // Interrupt Disable Register +#define TC_IMR (44) // Interrupt Mask Register +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_NONE (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_RISING (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_FALLING (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_BOTH (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE (0x1 << 15) // (TC) +#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRCS (0x1 << 7) // (TC) External Trigger +#define AT91C_TC_ETRGS (0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +// *** Register offset in AT91S_TCB structure *** +#define TCB_TC0 ( 0) // TC Channel 0 +#define TCB_TC1 (64) // TC Channel 1 +#define TCB_TC2 (128) // TC Channel 2 +#define TCB_BCR (192) // TC Block Control Register +#define TCB_BMR (196) // TC Block Mode Register +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S (0x1 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S (0x1 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S (0x1 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA2 (0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +// *** Register offset in AT91S_PWMC_CH structure *** +#define PWMC_CMR ( 0) // Channel Mode Register +#define PWMC_CDTYR ( 4) // Channel Duty Cycle Register +#define PWMC_CPRDR ( 8) // Channel Period Register +#define PWMC_CCNTR (12) // Channel Counter Register +#define PWMC_CUPDR (16) // Channel Update Register +#define PWMC_Reserved (20) // Reserved +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_PWMC structure *** +#define PWMC_MR ( 0) // PWMC Mode Register +#define PWMC_ENA ( 4) // PWMC Enable Register +#define PWMC_DIS ( 8) // PWMC Disable Register +#define PWMC_SR (12) // PWMC Status Register +#define PWMC_IER (16) // PWMC Interrupt Enable Register +#define PWMC_IDR (20) // PWMC Interrupt Disable Register +#define PWMC_IMR (24) // PWMC Interrupt Mask Register +#define PWMC_ISR (28) // PWMC Interrupt Status Register +#define PWMC_VR (252) // PWMC Version Register +#define PWMC_CH (512) // PWMC Channel 0 +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 +#define AT91C_PWMC_CHID4 (0x1 << 4) // (PWMC) Channel ID 4 +#define AT91C_PWMC_CHID5 (0x1 << 5) // (PWMC) Channel ID 5 +#define AT91C_PWMC_CHID6 (0x1 << 6) // (PWMC) Channel ID 6 +#define AT91C_PWMC_CHID7 (0x1 << 7) // (PWMC) Channel ID 7 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +// *** Register offset in AT91S_UDP structure *** +#define UDP_NUM ( 0) // Frame Number Register +#define UDP_GLBSTATE ( 4) // Global State Register +#define UDP_FADDR ( 8) // Function Address Register +#define UDP_IER (16) // Interrupt Enable Register +#define UDP_IDR (20) // Interrupt Disable Register +#define UDP_IMR (24) // Interrupt Mask Register +#define UDP_ISR (28) // Interrupt Status Register +#define UDP_ICR (32) // Interrupt Clear Register +#define UDP_RSTEP (40) // Reset Endpoint Register +#define UDP_CSR (48) // Endpoint Control and Status Register +#define UDP_FDR (80) // Endpoint FIFO Data Register +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured +#define AT91C_UDP_RMWUPE (0x1 << 2) // (UDP) Remote Wake Up Enable +#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt +#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt +#define AT91C_UDP_EPINT6 (0x1 << 6) // (UDP) Endpoint 6 Interrupt +#define AT91C_UDP_EPINT7 (0x1 << 7) // (UDP) Endpoint 7 Interrupt +#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 +#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4 +#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5 +#define AT91C_UDP_EP6 (0x1 << 6) // (UDP) Reset Endpoint 6 +#define AT91C_UDP_EP7 (0x1 << 7) // (UDP) Reset Endpoint 7 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7S64 +// ***************************************************************************** +// ========== Register definition for SYSC peripheral ========== +#define AT91C_SYSC_SYSC_VRPM (0xFFFFFD60) // (SYSC) Voltage Regulator Power Mode Register +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_ICCR (0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_IECR (0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_SMR (0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_ISCR (0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_EOICR (0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_DCR (0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_FFER (0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_SVR (0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_SPU (0xFFFFF134) // (AIC) Spurious Vector Register +#define AT91C_AIC_FFDR (0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_FVR (0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_FFSR (0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_IMR (0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_ISR (0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IVR (0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_IDCR (0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_CISR (0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IPR (0xFFFFF10C) // (AIC) Interrupt Pending Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_C2R (0xFFFFF244) // (DBGU) Chip ID2 Register +#define AT91C_DBGU_THR (0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_CSR (0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_IDR (0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_MR (0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_FNTR (0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_C1R (0xFFFFF240) // (DBGU) Chip ID1 Register +#define AT91C_DBGU_BRGR (0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_RHR (0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IMR (0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_IER (0xFFFFF208) // (DBGU) Interrupt Enable Register +#define AT91C_DBGU_CR (0xFFFFF200) // (DBGU) Control Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TNCR (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +#define AT91C_DBGU_RNCR (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_RCR (0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_TCR (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RPR (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_TPR (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RNPR (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_IMR (0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_IER (0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_OWDR (0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_ISR (0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_PPUDR (0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_MDSR (0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_MDER (0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PER (0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_PSR (0xFFFFF408) // (PIOA) PIO Status Register +#define AT91C_PIOA_OER (0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_BSR (0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_PPUER (0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_MDDR (0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_PDR (0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_ODR (0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_IFDR (0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_ABSR (0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_ASR (0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_PPUSR (0xFFFFF468) // (PIOA) Pad Pull-up Status Register +#define AT91C_PIOA_ODSR (0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_SODR (0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_IFSR (0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_IFER (0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_OSR (0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_IDR (0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_PDSR (0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_CODR (0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_OWSR (0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_OWER (0xFFFFF4A0) // (PIOA) Output Write Enable Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_PLLR (0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR (0xFFFFFC24) // (CKGR) Main Clock Frequency Register +#define AT91C_CKGR_MOR (0xFFFFFC20) // (CKGR) Main Oscillator Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_SCSR (0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_SCER (0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR (0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IDR (0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_PCDR (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCDR (0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_SR (0xFFFFFC68) // (PMC) Status Register +#define AT91C_PMC_IER (0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_MCKR (0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_MOR (0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PCER (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCSR (0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_PLLR (0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_MCFR (0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_PCKR (0xFFFFFC40) // (PMC) Programmable Clock Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RSR (0xFFFFFD04) // (RSTC) Reset Status Register +#define AT91C_RSTC_RMR (0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RCR (0xFFFFFD00) // (RSTC) Reset Control Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR (0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTAR (0xFFFFFD24) // (RTTC) Real-time Alarm Register +#define AT91C_RTTC_RTVR (0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTMR (0xFFFFFD20) // (RTTC) Real-time Mode Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIIR (0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PISR (0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIVR (0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PIMR (0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDMR (0xFFFFFD44) // (WDTC) Watchdog Mode Register +#define AT91C_WDTC_WDSR (0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDCR (0xFFFFFD40) // (WDTC) Watchdog Control Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_FCR (0xFFFFFF64) // (MC) MC Flash Command Register +#define AT91C_MC_ASR (0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_FSR (0xFFFFFF68) // (MC) MC Flash Status Register +#define AT91C_MC_FMR (0xFFFFFF60) // (MC) MC Flash Mode Register +#define AT91C_MC_AASR (0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_RCR (0xFFFFFF00) // (MC) MC Remap Control Register +// ========== Register definition for PDC_SPI peripheral ========== +#define AT91C_SPI_PTCR (0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register +#define AT91C_SPI_TNPR (0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register +#define AT91C_SPI_RNPR (0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register +#define AT91C_SPI_TPR (0xFFFE0108) // (PDC_SPI) Transmit Pointer Register +#define AT91C_SPI_RPR (0xFFFE0100) // (PDC_SPI) Receive Pointer Register +#define AT91C_SPI_PTSR (0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register +#define AT91C_SPI_TNCR (0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register +#define AT91C_SPI_RNCR (0xFFFE0114) // (PDC_SPI) Receive Next Counter Register +#define AT91C_SPI_TCR (0xFFFE010C) // (PDC_SPI) Transmit Counter Register +#define AT91C_SPI_RCR (0xFFFE0104) // (PDC_SPI) Receive Counter Register +// ========== Register definition for SPI peripheral ========== +#define AT91C_SPI_CSR (0xFFFE0030) // (SPI) Chip Select Register +#define AT91C_SPI_IDR (0xFFFE0018) // (SPI) Interrupt Disable Register +#define AT91C_SPI_SR (0xFFFE0010) // (SPI) Status Register +#define AT91C_SPI_RDR (0xFFFE0008) // (SPI) Receive Data Register +#define AT91C_SPI_CR (0xFFFE0000) // (SPI) Control Register +#define AT91C_SPI_IMR (0xFFFE001C) // (SPI) Interrupt Mask Register +#define AT91C_SPI_IER (0xFFFE0014) // (SPI) Interrupt Enable Register +#define AT91C_SPI_TDR (0xFFFE000C) // (SPI) Transmit Data Register +#define AT91C_SPI_MR (0xFFFE0004) // (SPI) Mode Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTCR (0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR (0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_RNPR (0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_TPR (0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RPR (0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_PTSR (0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_TNCR (0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNCR (0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_TCR (0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_RCR (0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_IMR (0xFFFD802C) // (ADC) ADC Interrupt Mask Register +#define AT91C_ADC_CDR4 (0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR2 (0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR0 (0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR7 (0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR1 (0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_CDR3 (0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR5 (0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_MR (0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_CDR6 (0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_CR (0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CHER (0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR (0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_IER (0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_SR (0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CHDR (0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_IDR (0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_LCDR (0xFFFD8020) // (ADC) ADC Last Converted Data Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_PTCR (0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TNPR (0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_RNPR (0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TPR (0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_RPR (0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_PTSR (0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +#define AT91C_SSC_TNCR (0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RNCR (0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TCR (0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR (0xFFFD4104) // (PDC_SSC) Receive Counter Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RFMR (0xFFFD4014) // (SSC) Receive Frame Mode Register +#define AT91C_SSC_CMR (0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_IDR (0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_SR (0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_RC0R (0xFFFD4038) // (SSC) Receive Compare 0 Register +#define AT91C_SSC_RSHR (0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_RHR (0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_TCMR (0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_RCMR (0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_CR (0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR (0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_IER (0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_RC1R (0xFFFD403C) // (SSC) Receive Compare 1 Register +#define AT91C_SSC_TSHR (0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_THR (0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_TFMR (0xFFFD401C) // (SSC) Transmit Frame Mode Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_PTSR (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNCR (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_RNCR (0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_TCR (0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_RCR (0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_PTCR (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TNPR (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RNPR (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_TPR (0xFFFC4108) // (PDC_US1) Transmit Pointer Register +#define AT91C_US1_RPR (0xFFFC4100) // (PDC_US1) Receive Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_XXR (0xFFFC4048) // (US1) XON_XOFF Register +#define AT91C_US1_RHR (0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_IMR (0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_IER (0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_CR (0xFFFC4000) // (US1) Control Register +#define AT91C_US1_RTOR (0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_THR (0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_CSR (0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR (0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_FIDI (0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_BRGR (0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_TTGR (0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_IF (0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER (0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_MR (0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_PTCR (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_TNPR (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TPR (0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RPR (0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_PTSR (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_RNCR (0xFFFC0114) // (PDC_US0) Receive Next Counter Register +#define AT91C_US0_TCR (0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_RCR (0xFFFC0104) // (PDC_US0) Receive Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_TTGR (0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_BRGR (0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_RHR (0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IMR (0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_NER (0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_RTOR (0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_XXR (0xFFFC0048) // (US0) XON_XOFF Register +#define AT91C_US0_FIDI (0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_CR (0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IER (0xFFFC0008) // (US0) Interrupt Enable Register +#define AT91C_US0_IF (0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_MR (0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_IDR (0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_CSR (0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_THR (0xFFFC001C) // (US0) Transmitter Holding Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_RHR (0xFFFB8030) // (TWI) Receive Holding Register +#define AT91C_TWI_IDR (0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_SR (0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_CWGR (0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_SMR (0xFFFB8008) // (TWI) Slave Mode Register +#define AT91C_TWI_CR (0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_THR (0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IMR (0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_IER (0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_IADR (0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR (0xFFFB8004) // (TWI) Master Mode Register +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_IMR (0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_IER (0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_RC (0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_RA (0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_CMR (0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_IDR (0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_SR (0xFFFA00A0) // (TC2) Status Register +#define AT91C_TC2_RB (0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_CV (0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_CCR (0xFFFA0080) // (TC2) Channel Control Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_IMR (0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_IER (0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_RC (0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_RA (0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_CMR (0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_IDR (0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR (0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_RB (0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CV (0xFFFA0050) // (TC1) Counter Value +#define AT91C_TC1_CCR (0xFFFA0040) // (TC1) Channel Control Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_IMR (0xFFFA002C) // (TC0) Interrupt Mask Register +#define AT91C_TC0_IER (0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RC (0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RA (0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_CMR (0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IDR (0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_SR (0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RB (0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CV (0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_CCR (0xFFFA0000) // (TC0) Channel Control Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR (0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR (0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_CH3_CUPDR (0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_CH3_CPRDR (0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_CH3_CMR (0xFFFCC260) // (PWMC_CH3) Channel Mode Register +#define AT91C_CH3_Reserved (0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_CH3_CCNTR (0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_CH3_CDTYR (0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_CH2_CUPDR (0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_CH2_CPRDR (0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_CH2_CMR (0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_CH2_Reserved (0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_CH2_CCNTR (0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_CH2_CDTYR (0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_CH1_CUPDR (0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_CH1_CPRDR (0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_CH1_CMR (0xFFFCC220) // (PWMC_CH1) Channel Mode Register +#define AT91C_CH1_Reserved (0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_CH1_CCNTR (0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_CH1_CDTYR (0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_CH0_CUPDR (0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_CH0_CPRDR (0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_CH0_CMR (0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_CH0_Reserved (0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_CH0_CCNTR (0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +#define AT91C_CH0_CDTYR (0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_VR (0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR (0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_IDR (0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_SR (0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_ENA (0xFFFCC004) // (PWMC) PWMC Enable Register +#define AT91C_PWMC_IMR (0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR (0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_DIS (0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER (0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_ISR (0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_IDR (0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_GLBSTATE (0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_FDR (0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_CSR (0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_RSTEP (0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_ICR (0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_IMR (0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_IER (0xFFFB0010) // (UDP) Interrupt Enable Register +#define AT91C_UDP_FADDR (0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM (0xFFFB0000) // (UDP) Frame Number Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7S64 +// ***************************************************************************** +#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_PWM0 (AT91C_PIO_PA0) // PWM Channel 0 +#define AT91C_PA0_TIOA0 (AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_PWM1 (AT91C_PIO_PA1) // PWM Channel 1 +#define AT91C_PA1_TIOB0 (AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_DTXD (AT91C_PIO_PA10) // DBGU Debug Transmit Data +#define AT91C_PA10_NPCS2 (AT91C_PIO_PA10) // SPI Peripheral Chip Select 2 +#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_NPCS0 (AT91C_PIO_PA11) // SPI Peripheral Chip Select 0 +#define AT91C_PA11_PWM0 (AT91C_PIO_PA11) // PWM Channel 0 +#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_MISO (AT91C_PIO_PA12) // SPI Master In Slave +#define AT91C_PA12_PWM1 (AT91C_PIO_PA12) // PWM Channel 1 +#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_MOSI (AT91C_PIO_PA13) // SPI Master Out Slave +#define AT91C_PA13_PWM2 (AT91C_PIO_PA13) // PWM Channel 2 +#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_SPCK (AT91C_PIO_PA14) // SPI Serial Clock +#define AT91C_PA14_PWM3 (AT91C_PIO_PA14) // PWM Channel 3 +#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_TF (AT91C_PIO_PA15) // SSC Transmit Frame Sync +#define AT91C_PA15_TIOA1 (AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_TK (AT91C_PIO_PA16) // SSC Transmit Clock +#define AT91C_PA16_TIOB1 (AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_TD (AT91C_PIO_PA17) // SSC Transmit data +#define AT91C_PA17_PCK1 (AT91C_PIO_PA17) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_RD (AT91C_PIO_PA18) // SSC Receive Data +#define AT91C_PA18_PCK2 (AT91C_PIO_PA18) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_RK (AT91C_PIO_PA19) // SSC Receive Clock +#define AT91C_PA19_FIQ (AT91C_PIO_PA19) // AIC Fast Interrupt Input +#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_PWM2 (AT91C_PIO_PA2) // PWM Channel 2 +#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_RF (AT91C_PIO_PA20) // SSC Receive Frame Sync +#define AT91C_PA20_IRQ0 (AT91C_PIO_PA20) // External Interrupt 0 +#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_RXD1 (AT91C_PIO_PA21) // USART 1 Receive Data +#define AT91C_PA21_PCK1 (AT91C_PIO_PA21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TXD1 (AT91C_PIO_PA22) // USART 1 Transmit Data +#define AT91C_PA22_NPCS3 (AT91C_PIO_PA22) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_SCK1 (AT91C_PIO_PA23) // USART 1 Serial Clock +#define AT91C_PA23_PWM0 (AT91C_PIO_PA23) // PWM Channel 0 +#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RTS1 (AT91C_PIO_PA24) // USART 1 Ready To Send +#define AT91C_PA24_PWM1 (AT91C_PIO_PA24) // PWM Channel 1 +#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_CTS1 (AT91C_PIO_PA25) // USART 1 Clear To Send +#define AT91C_PA25_PWM2 (AT91C_PIO_PA25) // PWM Channel 2 +#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_DCD1 (AT91C_PIO_PA26) // USART 1 Data Carrier Detect +#define AT91C_PA26_TIOA2 (AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DTR1 (AT91C_PIO_PA27) // USART 1 Data Terminal ready +#define AT91C_PA27_TIOB2 (AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DSR1 (AT91C_PIO_PA28) // USART 1 Data Set ready +#define AT91C_PA28_TCLK1 (AT91C_PIO_PA28) // Timer Counter 1 external clock input +#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_RI1 (AT91C_PIO_PA29) // USART 1 Ring Indicator +#define AT91C_PA29_TCLK2 (AT91C_PIO_PA29) // Timer Counter 2 external clock input +#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_TWD (AT91C_PIO_PA3) // TWI Two-wire Serial Data +#define AT91C_PA3_NPCS3 (AT91C_PIO_PA3) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ1 (AT91C_PIO_PA30) // External Interrupt 1 +#define AT91C_PA30_NPCS2 (AT91C_PIO_PA30) // SPI Peripheral Chip Select 2 +#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31 +#define AT91C_PA31_NPCS1 (AT91C_PIO_PA31) // SPI Peripheral Chip Select 1 +#define AT91C_PA31_PCK2 (AT91C_PIO_PA31) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_TWCK (AT91C_PIO_PA4) // TWI Two-wire Serial Clock +#define AT91C_PA4_TCLK0 (AT91C_PIO_PA4) // Timer Counter 0 external clock input +#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD0 (AT91C_PIO_PA5) // USART 0 Receive Data +#define AT91C_PA5_NPCS3 (AT91C_PIO_PA5) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD0 (AT91C_PIO_PA6) // USART 0 Transmit Data +#define AT91C_PA6_PCK0 (AT91C_PIO_PA6) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_RTS0 (AT91C_PIO_PA7) // USART 0 Ready To Send +#define AT91C_PA7_PWM3 (AT91C_PIO_PA7) // PWM Channel 3 +#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_CTS0 (AT91C_PIO_PA8) // USART 0 Clear To Send +#define AT91C_PA8_ADTRG (AT91C_PIO_PA8) // ADC External Trigger +#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_DRXD (AT91C_PIO_PA9) // DBGU Debug Receive Data +#define AT91C_PA9_NPCS1 (AT91C_PIO_PA9) // SPI Peripheral Chip Select 1 + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64 +// ***************************************************************************** +#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ( 1) // System Peripheral +#define AT91C_ID_PIOA ( 2) // Parallel IO Controller +#define AT91C_ID_3_Reserved ( 3) // Reserved +#define AT91C_ID_ADC ( 4) // Analog-to-Digital Converter +#define AT91C_ID_SPI ( 5) // Serial Peripheral Interface +#define AT91C_ID_US0 ( 6) // USART 0 +#define AT91C_ID_US1 ( 7) // USART 1 +#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ( 9) // Two-Wire Interface +#define AT91C_ID_PWMC (10) // PWM Controller +#define AT91C_ID_UDP (11) // USB Device Port +#define AT91C_ID_TC0 (12) // Timer Counter 0 +#define AT91C_ID_TC1 (13) // Timer Counter 1 +#define AT91C_ID_TC2 (14) // Timer Counter 2 +#define AT91C_ID_15_Reserved (15) // Reserved +#define AT91C_ID_16_Reserved (16) // Reserved +#define AT91C_ID_17_Reserved (17) // Reserved +#define AT91C_ID_18_Reserved (18) // Reserved +#define AT91C_ID_19_Reserved (19) // Reserved +#define AT91C_ID_20_Reserved (20) // Reserved +#define AT91C_ID_21_Reserved (21) // Reserved +#define AT91C_ID_22_Reserved (22) // Reserved +#define AT91C_ID_23_Reserved (23) // Reserved +#define AT91C_ID_24_Reserved (24) // Reserved +#define AT91C_ID_25_Reserved (25) // Reserved +#define AT91C_ID_26_Reserved (26) // Reserved +#define AT91C_ID_27_Reserved (27) // Reserved +#define AT91C_ID_28_Reserved (28) // Reserved +#define AT91C_ID_29_Reserved (29) // Reserved +#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1) + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7S64 +// ***************************************************************************** +#define AT91C_BASE_SYSC (0xFFFFF000) // (SYSC) Base Address +#define AT91C_BASE_AIC (0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_DBGU (0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PDC_DBGU (0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_PIOA (0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_CKGR (0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC (0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC (0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC (0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC (0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC (0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_MC (0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_PDC_SPI (0xFFFE0100) // (PDC_SPI) Base Address +#define AT91C_BASE_SPI (0xFFFE0000) // (SPI) Base Address +#define AT91C_BASE_PDC_ADC (0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC (0xFFFD8000) // (ADC) Base Address +#define AT91C_BASE_PDC_SSC (0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC (0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_PDC_US1 (0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 (0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 (0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_TWI (0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_TC2 (0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TC1 (0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC0 (0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TCB (0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_PWMC_CH3 (0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 (0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 (0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 (0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC (0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP (0xFFFB0000) // (UDP) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64 +// ***************************************************************************** +#define AT91C_ISRAM (0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE (0x00004000) // Internal SRAM size in byte (16 Kbyte) +#define AT91C_IFLASH (0x00100000) // Internal ROM base address +#define AT91C_IFLASH_SIZE (0x00010000) // Internal ROM size in byte (64 Kbyte) + + diff --git a/20080212/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128.h b/20080212/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128.h new file mode 100644 index 000000000..ae4f35f81 --- /dev/null +++ b/20080212/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128.h @@ -0,0 +1,2715 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM7X128.h +// Object : AT91SAM7X128 definitions +// Generated : AT91 SW Application Group 05/20/2005 (16:22:23) +// +// CVS Reference : /AT91SAM7X128.pl/1.14/Tue May 10 12:12:05 2005// +// CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// +// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// +// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// +// CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// +// CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// +// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// +// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// +// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// +// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// +// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// +// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// +// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// +// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// +// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// +// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// +// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// +// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// +// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// +// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// +// CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// +// CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// +// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// +// CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// +// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// +// ---------------------------------------------------------------------------- + +#ifndef AT91SAM7X128_H +#define AT91SAM7X128_H + +typedef volatile unsigned int AT91_REG;// Hardware register definition + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** +typedef struct _AT91S_SYS { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register + AT91_REG Reserved2[45]; // + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved3[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved4[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register + AT91_REG Reserved5[54]; // + AT91_REG PIOA_PER; // PIO Enable Register + AT91_REG PIOA_PDR; // PIO Disable Register + AT91_REG PIOA_PSR; // PIO Status Register + AT91_REG Reserved6[1]; // + AT91_REG PIOA_OER; // Output Enable Register + AT91_REG PIOA_ODR; // Output Disable Registerr + AT91_REG PIOA_OSR; // Output Status Register + AT91_REG Reserved7[1]; // + AT91_REG PIOA_IFER; // Input Filter Enable Register + AT91_REG PIOA_IFDR; // Input Filter Disable Register + AT91_REG PIOA_IFSR; // Input Filter Status Register + AT91_REG Reserved8[1]; // + AT91_REG PIOA_SODR; // Set Output Data Register + AT91_REG PIOA_CODR; // Clear Output Data Register + AT91_REG PIOA_ODSR; // Output Data Status Register + AT91_REG PIOA_PDSR; // Pin Data Status Register + AT91_REG PIOA_IER; // Interrupt Enable Register + AT91_REG PIOA_IDR; // Interrupt Disable Register + AT91_REG PIOA_IMR; // Interrupt Mask Register + AT91_REG PIOA_ISR; // Interrupt Status Register + AT91_REG PIOA_MDER; // Multi-driver Enable Register + AT91_REG PIOA_MDDR; // Multi-driver Disable Register + AT91_REG PIOA_MDSR; // Multi-driver Status Register + AT91_REG Reserved9[1]; // + AT91_REG PIOA_PPUDR; // Pull-up Disable Register + AT91_REG PIOA_PPUER; // Pull-up Enable Register + AT91_REG PIOA_PPUSR; // Pull-up Status Register + AT91_REG Reserved10[1]; // + AT91_REG PIOA_ASR; // Select A Register + AT91_REG PIOA_BSR; // Select B Register + AT91_REG PIOA_ABSR; // AB Select Status Register + AT91_REG Reserved11[9]; // + AT91_REG PIOA_OWER; // Output Write Enable Register + AT91_REG PIOA_OWDR; // Output Write Disable Register + AT91_REG PIOA_OWSR; // Output Write Status Register + AT91_REG Reserved12[85]; // + AT91_REG PIOB_PER; // PIO Enable Register + AT91_REG PIOB_PDR; // PIO Disable Register + AT91_REG PIOB_PSR; // PIO Status Register + AT91_REG Reserved13[1]; // + AT91_REG PIOB_OER; // Output Enable Register + AT91_REG PIOB_ODR; // Output Disable Registerr + AT91_REG PIOB_OSR; // Output Status Register + AT91_REG Reserved14[1]; // + AT91_REG PIOB_IFER; // Input Filter Enable Register + AT91_REG PIOB_IFDR; // Input Filter Disable Register + AT91_REG PIOB_IFSR; // Input Filter Status Register + AT91_REG Reserved15[1]; // + AT91_REG PIOB_SODR; // Set Output Data Register + AT91_REG PIOB_CODR; // Clear Output Data Register + AT91_REG PIOB_ODSR; // Output Data Status Register + AT91_REG PIOB_PDSR; // Pin Data Status Register + AT91_REG PIOB_IER; // Interrupt Enable Register + AT91_REG PIOB_IDR; // Interrupt Disable Register + AT91_REG PIOB_IMR; // Interrupt Mask Register + AT91_REG PIOB_ISR; // Interrupt Status Register + AT91_REG PIOB_MDER; // Multi-driver Enable Register + AT91_REG PIOB_MDDR; // Multi-driver Disable Register + AT91_REG PIOB_MDSR; // Multi-driver Status Register + AT91_REG Reserved16[1]; // + AT91_REG PIOB_PPUDR; // Pull-up Disable Register + AT91_REG PIOB_PPUER; // Pull-up Enable Register + AT91_REG PIOB_PPUSR; // Pull-up Status Register + AT91_REG Reserved17[1]; // + AT91_REG PIOB_ASR; // Select A Register + AT91_REG PIOB_BSR; // Select B Register + AT91_REG PIOB_ABSR; // AB Select Status Register + AT91_REG Reserved18[9]; // + AT91_REG PIOB_OWER; // Output Write Enable Register + AT91_REG PIOB_OWDR; // Output Write Disable Register + AT91_REG PIOB_OWSR; // Output Write Status Register + AT91_REG Reserved19[341]; // + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved20[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved21[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved22[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved23[3]; // + AT91_REG PMC_PCKR[4]; // Programmable Clock Register + AT91_REG Reserved24[4]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register + AT91_REG Reserved25[36]; // + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register + AT91_REG Reserved26[5]; // + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register + AT91_REG Reserved27[5]; // + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_SYS, *AT91PS_SYS; + + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +typedef struct _AT91S_AIC { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register +} AT91S_AIC, *AT91PS_AIC; + +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// ***************************************************************************** +typedef struct _AT91S_PDC { + AT91_REG PDC_RPR; // Receive Pointer Register + AT91_REG PDC_RCR; // Receive Counter Register + AT91_REG PDC_TPR; // Transmit Pointer Register + AT91_REG PDC_TCR; // Transmit Counter Register + AT91_REG PDC_RNPR; // Receive Next Pointer Register + AT91_REG PDC_RNCR; // Receive Next Counter Register + AT91_REG PDC_TNPR; // Transmit Next Pointer Register + AT91_REG PDC_TNCR; // Transmit Next Counter Register + AT91_REG PDC_PTCR; // PDC Transfer Control Register + AT91_REG PDC_PTSR; // PDC Transfer Status Register +} AT91S_PDC, *AT91PS_PDC; + +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +typedef struct _AT91S_DBGU { + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved0[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved1[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register +} AT91S_DBGU, *AT91PS_DBGU; + +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable +#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +typedef struct _AT91S_PIO { + AT91_REG PIO_PER; // PIO Enable Register + AT91_REG PIO_PDR; // PIO Disable Register + AT91_REG PIO_PSR; // PIO Status Register + AT91_REG Reserved0[1]; // + AT91_REG PIO_OER; // Output Enable Register + AT91_REG PIO_ODR; // Output Disable Registerr + AT91_REG PIO_OSR; // Output Status Register + AT91_REG Reserved1[1]; // + AT91_REG PIO_IFER; // Input Filter Enable Register + AT91_REG PIO_IFDR; // Input Filter Disable Register + AT91_REG PIO_IFSR; // Input Filter Status Register + AT91_REG Reserved2[1]; // + AT91_REG PIO_SODR; // Set Output Data Register + AT91_REG PIO_CODR; // Clear Output Data Register + AT91_REG PIO_ODSR; // Output Data Status Register + AT91_REG PIO_PDSR; // Pin Data Status Register + AT91_REG PIO_IER; // Interrupt Enable Register + AT91_REG PIO_IDR; // Interrupt Disable Register + AT91_REG PIO_IMR; // Interrupt Mask Register + AT91_REG PIO_ISR; // Interrupt Status Register + AT91_REG PIO_MDER; // Multi-driver Enable Register + AT91_REG PIO_MDDR; // Multi-driver Disable Register + AT91_REG PIO_MDSR; // Multi-driver Status Register + AT91_REG Reserved3[1]; // + AT91_REG PIO_PPUDR; // Pull-up Disable Register + AT91_REG PIO_PPUER; // Pull-up Enable Register + AT91_REG PIO_PPUSR; // Pull-up Status Register + AT91_REG Reserved4[1]; // + AT91_REG PIO_ASR; // Select A Register + AT91_REG PIO_BSR; // Select B Register + AT91_REG PIO_ABSR; // AB Select Status Register + AT91_REG Reserved5[9]; // + AT91_REG PIO_OWER; // Output Write Enable Register + AT91_REG PIO_OWDR; // Output Write Disable Register + AT91_REG PIO_OWSR; // Output Write Status Register +} AT91S_PIO, *AT91PS_PIO; + + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +typedef struct _AT91S_CKGR { + AT91_REG CKGR_MOR; // Main Oscillator Register + AT91_REG CKGR_MCFR; // Main Clock Frequency Register + AT91_REG Reserved0[1]; // + AT91_REG CKGR_PLLR; // PLL Register +} AT91S_CKGR, *AT91PS_CKGR; + +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +typedef struct _AT91S_PMC { + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved0[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved1[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved2[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved3[3]; // + AT91_REG PMC_PCKR[4]; // Programmable Clock Register + AT91_REG Reserved4[4]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register +} AT91S_PMC, *AT91PS_PMC; + +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +typedef struct _AT91S_RSTC { + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register +} AT91S_RSTC, *AT91PS_RSTC; + +// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset +#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset +#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password +// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status +#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status +#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type +#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured. +#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level +#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable +#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_RTTC { + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register +} AT91S_RTTC, *AT91PS_RTTC; + +// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value +// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value +// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_PITC { + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register +} AT91S_PITC, *AT91PS_PITC; + +// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_WDTC { + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register +} AT91S_WDTC, *AT91PS_WDTC; + +// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart +#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password +// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface +// ***************************************************************************** +typedef struct _AT91S_VREG { + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_VREG, *AT91PS_VREG; + +// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- +#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +typedef struct _AT91S_MC { + AT91_REG MC_RCR; // MC Remap Control Register + AT91_REG MC_ASR; // MC Abort Status Register + AT91_REG MC_AASR; // MC Abort Address Status Register + AT91_REG Reserved0[21]; // + AT91_REG MC_FMR; // MC Flash Mode Register + AT91_REG MC_FCR; // MC Flash Command Register + AT91_REG MC_FSR; // MC Flash Status Register +} AT91S_MC, *AT91PS_MC; + +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready +#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error +#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error +#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming +#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State +#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number +// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command +#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit. +#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number +#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key +// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- +#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status +#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +typedef struct _AT91S_SPI { + AT91_REG SPI_CR; // Control Register + AT91_REG SPI_MR; // Mode Register + AT91_REG SPI_RDR; // Receive Data Register + AT91_REG SPI_TDR; // Transmit Data Register + AT91_REG SPI_SR; // Status Register + AT91_REG SPI_IER; // Interrupt Enable Register + AT91_REG SPI_IDR; // Interrupt Disable Register + AT91_REG SPI_IMR; // Interrupt Mask Register + AT91_REG Reserved0[4]; // + AT91_REG SPI_CSR[4]; // Chip Select Register + AT91_REG Reserved1[48]; // + AT91_REG SPI_RPR; // Receive Pointer Register + AT91_REG SPI_RCR; // Receive Counter Register + AT91_REG SPI_TPR; // Transmit Pointer Register + AT91_REG SPI_TCR; // Transmit Counter Register + AT91_REG SPI_RNPR; // Receive Next Pointer Register + AT91_REG SPI_RNCR; // Receive Next Counter Register + AT91_REG SPI_TNPR; // Transmit Next Pointer Register + AT91_REG SPI_TNCR; // Transmit Next Counter Register + AT91_REG SPI_PTCR; // PDC Transfer Control Register + AT91_REG SPI_PTSR; // PDC Transfer Status Register +} AT91S_SPI, *AT91PS_SPI; + +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK +#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +typedef struct _AT91S_USART { + AT91_REG US_CR; // Control Register + AT91_REG US_MR; // Mode Register + AT91_REG US_IER; // Interrupt Enable Register + AT91_REG US_IDR; // Interrupt Disable Register + AT91_REG US_IMR; // Interrupt Mask Register + AT91_REG US_CSR; // Channel Status Register + AT91_REG US_RHR; // Receiver Holding Register + AT91_REG US_THR; // Transmitter Holding Register + AT91_REG US_BRGR; // Baud Rate Generator Register + AT91_REG US_RTOR; // Receiver Time-out Register + AT91_REG US_TTGR; // Transmitter Time-guard Register + AT91_REG Reserved0[5]; // + AT91_REG US_FIDI; // FI_DI_Ratio Register + AT91_REG US_NER; // Nb Errors Register + AT91_REG Reserved1[1]; // + AT91_REG US_IF; // IRDA_FILTER Register + AT91_REG Reserved2[44]; // + AT91_REG US_RPR; // Receive Pointer Register + AT91_REG US_RCR; // Receive Counter Register + AT91_REG US_TPR; // Transmit Pointer Register + AT91_REG US_TCR; // Transmit Counter Register + AT91_REG US_RNPR; // Receive Next Pointer Register + AT91_REG US_RNCR; // Receive Next Counter Register + AT91_REG US_TNPR; // Transmit Next Pointer Register + AT91_REG US_TNCR; // Transmit Next Counter Register + AT91_REG US_PTCR; // PDC Transfer Control Register + AT91_REG US_PTSR; // PDC Transfer Status Register +} AT91S_USART, *AT91PS_USART; + +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +typedef struct _AT91S_SSC { + AT91_REG SSC_CR; // Control Register + AT91_REG SSC_CMR; // Clock Mode Register + AT91_REG Reserved0[2]; // + AT91_REG SSC_RCMR; // Receive Clock ModeRegister + AT91_REG SSC_RFMR; // Receive Frame Mode Register + AT91_REG SSC_TCMR; // Transmit Clock Mode Register + AT91_REG SSC_TFMR; // Transmit Frame Mode Register + AT91_REG SSC_RHR; // Receive Holding Register + AT91_REG SSC_THR; // Transmit Holding Register + AT91_REG Reserved1[2]; // + AT91_REG SSC_RSHR; // Receive Sync Holding Register + AT91_REG SSC_TSHR; // Transmit Sync Holding Register + AT91_REG Reserved2[2]; // + AT91_REG SSC_SR; // Status Register + AT91_REG SSC_IER; // Interrupt Enable Register + AT91_REG SSC_IDR; // Interrupt Disable Register + AT91_REG SSC_IMR; // Interrupt Mask Register + AT91_REG Reserved3[44]; // + AT91_REG SSC_RPR; // Receive Pointer Register + AT91_REG SSC_RCR; // Receive Counter Register + AT91_REG SSC_TPR; // Transmit Pointer Register + AT91_REG SSC_TCR; // Transmit Counter Register + AT91_REG SSC_RNPR; // Receive Next Pointer Register + AT91_REG SSC_RNCR; // Receive Next Counter Register + AT91_REG SSC_TNPR; // Transmit Next Pointer Register + AT91_REG SSC_TNCR; // Transmit Next Counter Register + AT91_REG SSC_PTCR; // PDC Transfer Control Register + AT91_REG SSC_PTSR; // PDC Transfer Status Register +} AT91S_SSC, *AT91PS_SSC; + +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin +#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +typedef struct _AT91S_TWI { + AT91_REG TWI_CR; // Control Register + AT91_REG TWI_MMR; // Master Mode Register + AT91_REG Reserved0[1]; // + AT91_REG TWI_IADR; // Internal Address Register + AT91_REG TWI_CWGR; // Clock Waveform Generator Register + AT91_REG Reserved1[3]; // + AT91_REG TWI_SR; // Status Register + AT91_REG TWI_IER; // Interrupt Enable Register + AT91_REG TWI_IDR; // Interrupt Disable Register + AT91_REG TWI_IMR; // Interrupt Mask Register + AT91_REG TWI_RHR; // Receive Holding Register + AT91_REG TWI_THR; // Transmit Holding Register +} AT91S_TWI, *AT91PS_TWI; + +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +typedef struct _AT91S_PWMC_CH { + AT91_REG PWMC_CMR; // Channel Mode Register + AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register + AT91_REG PWMC_CPRDR; // Channel Period Register + AT91_REG PWMC_CCNTR; // Channel Counter Register + AT91_REG PWMC_CUPDR; // Channel Update Register + AT91_REG PWMC_Reserved[3]; // Reserved +} AT91S_PWMC_CH, *AT91PS_PWMC_CH; + +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +typedef struct _AT91S_PWMC { + AT91_REG PWMC_MR; // PWMC Mode Register + AT91_REG PWMC_ENA; // PWMC Enable Register + AT91_REG PWMC_DIS; // PWMC Disable Register + AT91_REG PWMC_SR; // PWMC Status Register + AT91_REG PWMC_IER; // PWMC Interrupt Enable Register + AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register + AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register + AT91_REG PWMC_ISR; // PWMC Interrupt Status Register + AT91_REG Reserved0[55]; // + AT91_REG PWMC_VR; // PWMC Version Register + AT91_REG Reserved1[64]; // + AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel +} AT91S_PWMC, *AT91PS_PWMC; + +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +typedef struct _AT91S_UDP { + AT91_REG UDP_NUM; // Frame Number Register + AT91_REG UDP_GLBSTATE; // Global State Register + AT91_REG UDP_FADDR; // Function Address Register + AT91_REG Reserved0[1]; // + AT91_REG UDP_IER; // Interrupt Enable Register + AT91_REG UDP_IDR; // Interrupt Disable Register + AT91_REG UDP_IMR; // Interrupt Mask Register + AT91_REG UDP_ISR; // Interrupt Status Register + AT91_REG UDP_ICR; // Interrupt Clear Register + AT91_REG Reserved1[1]; // + AT91_REG UDP_RSTEP; // Reset Endpoint Register + AT91_REG Reserved2[1]; // + AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register + AT91_REG Reserved3[2]; // + AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register + AT91_REG Reserved4[3]; // + AT91_REG UDP_TXVC; // Transceiver Control Register +} AT91S_UDP, *AT91PS_UDP; + +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured +#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume +#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt +#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt +#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3 +#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4 +#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO +// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP) +#define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +typedef struct _AT91S_TC { + AT91_REG TC_CCR; // Channel Control Register + AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) + AT91_REG Reserved0[2]; // + AT91_REG TC_CV; // Counter Value + AT91_REG TC_RA; // Register A + AT91_REG TC_RB; // Register B + AT91_REG TC_RC; // Register C + AT91_REG TC_SR; // Status Register + AT91_REG TC_IER; // Interrupt Enable Register + AT91_REG TC_IDR; // Interrupt Disable Register + AT91_REG TC_IMR; // Interrupt Mask Register +} AT91S_TC, *AT91PS_TC; + +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) +#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger +#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +typedef struct _AT91S_TCB { + AT91S_TC TCB_TC0; // TC Channel 0 + AT91_REG Reserved0[4]; // + AT91S_TC TCB_TC1; // TC Channel 1 + AT91_REG Reserved1[4]; // + AT91S_TC TCB_TC2; // TC Channel 2 + AT91_REG Reserved2[4]; // + AT91_REG TCB_BCR; // TC Block Control Register + AT91_REG TCB_BMR; // TC Block Mode Register +} AT91S_TCB, *AT91PS_TCB; + +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface +// ***************************************************************************** +typedef struct _AT91S_CAN_MB { + AT91_REG CAN_MB_MMR; // MailBox Mode Register + AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register + AT91_REG CAN_MB_MID; // MailBox ID Register + AT91_REG CAN_MB_MFID; // MailBox Family ID Register + AT91_REG CAN_MB_MSR; // MailBox Status Register + AT91_REG CAN_MB_MDL; // MailBox Data Low Register + AT91_REG CAN_MB_MDH; // MailBox Data High Register + AT91_REG CAN_MB_MCR; // MailBox Control Register +} AT91S_CAN_MB, *AT91PS_CAN_MB; + +// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- +#define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark +#define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority +#define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type +#define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB) +// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- +#define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode +#define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode +#define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version +// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- +// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- +// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- +#define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value +#define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code +#define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request +#define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort +#define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready +#define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored +// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- +// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- +// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- +#define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox +#define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network Interface +// ***************************************************************************** +typedef struct _AT91S_CAN { + AT91_REG CAN_MR; // Mode Register + AT91_REG CAN_IER; // Interrupt Enable Register + AT91_REG CAN_IDR; // Interrupt Disable Register + AT91_REG CAN_IMR; // Interrupt Mask Register + AT91_REG CAN_SR; // Status Register + AT91_REG CAN_BR; // Baudrate Register + AT91_REG CAN_TIM; // Timer Register + AT91_REG CAN_TIMESTP; // Time Stamp Register + AT91_REG CAN_ECR; // Error Counter Register + AT91_REG CAN_TCR; // Transfer Command Register + AT91_REG CAN_ACR; // Abort Command Register + AT91_REG Reserved0[52]; // + AT91_REG CAN_VR; // Version Register + AT91_REG Reserved1[64]; // + AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0 + AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1 + AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2 + AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3 + AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4 + AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5 + AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6 + AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7 + AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8 + AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9 + AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10 + AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11 + AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12 + AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13 + AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14 + AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15 +} AT91S_CAN, *AT91PS_CAN; + +// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- +#define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable +#define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode +#define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode +#define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame +#define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame +#define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode +#define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze +#define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat +// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- +#define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag +#define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag +#define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag +#define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag +#define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag +#define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag +#define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag +#define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag +#define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag +#define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag +#define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag +#define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag +#define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag +#define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag +#define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag +#define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag +#define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag +#define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag +#define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag +#define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag +#define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag +#define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag +#define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag +#define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag +#define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error +#define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error +#define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error +#define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error +#define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error +// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- +// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- +// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- +#define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy +#define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy +#define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy +// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- +#define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment +#define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment +#define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment +#define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment +#define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler +#define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode +// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- +#define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field +// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- +// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- +#define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter +#define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter +// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- +#define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field +// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 +// ***************************************************************************** +typedef struct _AT91S_EMAC { + AT91_REG EMAC_NCR; // Network Control Register + AT91_REG EMAC_NCFGR; // Network Configuration Register + AT91_REG EMAC_NSR; // Network Status Register + AT91_REG Reserved0[2]; // + AT91_REG EMAC_TSR; // Transmit Status Register + AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer + AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer + AT91_REG EMAC_RSR; // Receive Status Register + AT91_REG EMAC_ISR; // Interrupt Status Register + AT91_REG EMAC_IER; // Interrupt Enable Register + AT91_REG EMAC_IDR; // Interrupt Disable Register + AT91_REG EMAC_IMR; // Interrupt Mask Register + AT91_REG EMAC_MAN; // PHY Maintenance Register + AT91_REG EMAC_PTR; // Pause Time Register + AT91_REG EMAC_PFR; // Pause Frames received Register + AT91_REG EMAC_FTO; // Frames Transmitted OK Register + AT91_REG EMAC_SCF; // Single Collision Frame Register + AT91_REG EMAC_MCF; // Multiple Collision Frame Register + AT91_REG EMAC_FRO; // Frames Received OK Register + AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register + AT91_REG EMAC_ALE; // Alignment Error Register + AT91_REG EMAC_DTF; // Deferred Transmission Frame Register + AT91_REG EMAC_LCOL; // Late Collision Register + AT91_REG EMAC_ECOL; // Excessive Collision Register + AT91_REG EMAC_TUND; // Transmit Underrun Error Register + AT91_REG EMAC_CSE; // Carrier Sense Error Register + AT91_REG EMAC_RRE; // Receive Ressource Error Register + AT91_REG EMAC_ROV; // Receive Overrun Errors Register + AT91_REG EMAC_RSE; // Receive Symbol Errors Register + AT91_REG EMAC_ELE; // Excessive Length Errors Register + AT91_REG EMAC_RJA; // Receive Jabbers Register + AT91_REG EMAC_USF; // Undersize Frames Register + AT91_REG EMAC_STE; // SQE Test Error Register + AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register + AT91_REG EMAC_TPF; // Transmitted Pause Frames Register + AT91_REG EMAC_HRB; // Hash Address Bottom[31:0] + AT91_REG EMAC_HRT; // Hash Address Top[63:32] + AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes + AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes + AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes + AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes + AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes + AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes + AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes + AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes + AT91_REG EMAC_TID; // Type ID Checking Register + AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register + AT91_REG EMAC_USRIO; // USER Input/Output Register + AT91_REG EMAC_WOL; // Wake On LAN Register + AT91_REG Reserved1[13]; // + AT91_REG EMAC_REV; // Revision Register +} AT91S_EMAC, *AT91PS_EMAC; + +// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- +#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. +#define AT91C_EMAC_LLB ((unsigned int) 0x1 << 1) // (EMAC) Loopback local. +#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable. +#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable. +#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable. +#define AT91C_EMAC_CLRSTAT ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers. +#define AT91C_EMAC_INCSTAT ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers. +#define AT91C_EMAC_WESTAT ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers. +#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure. +#define AT91C_EMAC_TSTART ((unsigned int) 0x1 << 9) // (EMAC) Start Transmission. +#define AT91C_EMAC_THALT ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. +#define AT91C_EMAC_TPFR ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame +#define AT91C_EMAC_TZQ ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame +// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- +#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed. +#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex. +#define AT91C_EMAC_JFRAME ((unsigned int) 0x1 << 3) // (EMAC) Jumbo Frames. +#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames. +#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast. +#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash event enable +#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable. +#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes. +#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable. +#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC) +#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8 +#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16 +#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32 +#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64 +#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC) +#define AT91C_EMAC_PAE ((unsigned int) 0x1 << 13) // (EMAC) +#define AT91C_EMAC_RBOF ((unsigned int) 0x3 << 14) // (EMAC) +#define AT91C_EMAC_RBOF_OFFSET_0 ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_1 ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_2 ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_3 ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer +#define AT91C_EMAC_RLCE ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable +#define AT91C_EMAC_DRFCS ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS +#define AT91C_EMAC_EFRHD ((unsigned int) 0x1 << 18) // (EMAC) +#define AT91C_EMAC_IRXFCS ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS +// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- +#define AT91C_EMAC_LINKR ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC) +// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- +#define AT91C_EMAC_UBR ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_RLES ((unsigned int) 0x1 << 2) // (EMAC) +#define AT91C_EMAC_TGO ((unsigned int) 0x1 << 3) // (EMAC) Transmit Go +#define AT91C_EMAC_BEX ((unsigned int) 0x1 << 4) // (EMAC) Buffers exhausted mid frame +#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC) +#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC) +// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- +#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 2) // (EMAC) +// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- +#define AT91C_EMAC_MFD ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_RCOMP ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_RXUBR ((unsigned int) 0x1 << 2) // (EMAC) +#define AT91C_EMAC_TXUBR ((unsigned int) 0x1 << 3) // (EMAC) +#define AT91C_EMAC_TUNDR ((unsigned int) 0x1 << 4) // (EMAC) +#define AT91C_EMAC_RLEX ((unsigned int) 0x1 << 5) // (EMAC) +#define AT91C_EMAC_TXERR ((unsigned int) 0x1 << 6) // (EMAC) +#define AT91C_EMAC_TCOMP ((unsigned int) 0x1 << 7) // (EMAC) +#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC) +#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC) +#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC) +#define AT91C_EMAC_PFRE ((unsigned int) 0x1 << 12) // (EMAC) +#define AT91C_EMAC_PTZ ((unsigned int) 0x1 << 13) // (EMAC) +// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- +// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- +// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- +// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- +#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC) +#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC) +#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC) +#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC) +#define AT91C_EMAC_SOF ((unsigned int) 0x3 << 30) // (EMAC) +// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- +#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 0) // (EMAC) Reduce MII +// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- +#define AT91C_EMAC_IP ((unsigned int) 0xFFFF << 0) // (EMAC) ARP request IP address +#define AT91C_EMAC_MAG ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable +#define AT91C_EMAC_ARP ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable +#define AT91C_EMAC_SA1 ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable +// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- +#define AT91C_EMAC_REVREF ((unsigned int) 0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_PARTREF ((unsigned int) 0xFFFF << 16) // (EMAC) + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +typedef struct _AT91S_ADC { + AT91_REG ADC_CR; // ADC Control Register + AT91_REG ADC_MR; // ADC Mode Register + AT91_REG Reserved0[2]; // + AT91_REG ADC_CHER; // ADC Channel Enable Register + AT91_REG ADC_CHDR; // ADC Channel Disable Register + AT91_REG ADC_CHSR; // ADC Channel Status Register + AT91_REG ADC_SR; // ADC Status Register + AT91_REG ADC_LCDR; // ADC Last Converted Data Register + AT91_REG ADC_IER; // ADC Interrupt Enable Register + AT91_REG ADC_IDR; // ADC Interrupt Disable Register + AT91_REG ADC_IMR; // ADC Interrupt Mask Register + AT91_REG ADC_CDR0; // ADC Channel Data Register 0 + AT91_REG ADC_CDR1; // ADC Channel Data Register 1 + AT91_REG ADC_CDR2; // ADC Channel Data Register 2 + AT91_REG ADC_CDR3; // ADC Channel Data Register 3 + AT91_REG ADC_CDR4; // ADC Channel Data Register 4 + AT91_REG ADC_CDR5; // ADC Channel Data Register 5 + AT91_REG ADC_CDR6; // ADC Channel Data Register 6 + AT91_REG ADC_CDR7; // ADC Channel Data Register 7 + AT91_REG Reserved1[44]; // + AT91_REG ADC_RPR; // Receive Pointer Register + AT91_REG ADC_RCR; // Receive Counter Register + AT91_REG ADC_TPR; // Transmit Pointer Register + AT91_REG ADC_TCR; // Transmit Counter Register + AT91_REG ADC_RNPR; // Receive Next Pointer Register + AT91_REG ADC_RNCR; // Receive Next Counter Register + AT91_REG ADC_TNPR; // Transmit Next Pointer Register + AT91_REG ADC_TNCR; // Transmit Next Counter Register + AT91_REG ADC_PTCR; // PDC Transfer Control Register + AT91_REG ADC_PTSR; // PDC Transfer Status Register +} AT91S_ADC, *AT91PS_ADC; + +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Encryption Standard +// ***************************************************************************** +typedef struct _AT91S_AES { + AT91_REG AES_CR; // Control Register + AT91_REG AES_MR; // Mode Register + AT91_REG Reserved0[2]; // + AT91_REG AES_IER; // Interrupt Enable Register + AT91_REG AES_IDR; // Interrupt Disable Register + AT91_REG AES_IMR; // Interrupt Mask Register + AT91_REG AES_ISR; // Interrupt Status Register + AT91_REG AES_KEYWxR[4]; // Key Word x Register + AT91_REG Reserved1[4]; // + AT91_REG AES_IDATAxR[4]; // Input Data x Register + AT91_REG AES_ODATAxR[4]; // Output Data x Register + AT91_REG AES_IVxR[4]; // Initialization Vector x Register + AT91_REG Reserved2[35]; // + AT91_REG AES_VR; // AES Version Register + AT91_REG AES_RPR; // Receive Pointer Register + AT91_REG AES_RCR; // Receive Counter Register + AT91_REG AES_TPR; // Transmit Pointer Register + AT91_REG AES_TCR; // Transmit Counter Register + AT91_REG AES_RNPR; // Receive Next Pointer Register + AT91_REG AES_RNCR; // Receive Next Counter Register + AT91_REG AES_TNPR; // Transmit Next Pointer Register + AT91_REG AES_TNCR; // Transmit Next Counter Register + AT91_REG AES_PTCR; // PDC Transfer Control Register + AT91_REG AES_PTSR; // PDC Transfer Status Register +} AT91S_AES, *AT91PS_AES; + +// -------- AES_CR : (AES Offset: 0x0) Control Register -------- +#define AT91C_AES_START ((unsigned int) 0x1 << 0) // (AES) Starts Processing +#define AT91C_AES_SWRST ((unsigned int) 0x1 << 8) // (AES) Software Reset +#define AT91C_AES_LOADSEED ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading +// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- +#define AT91C_AES_CIPHER ((unsigned int) 0x1 << 0) // (AES) Processing Mode +#define AT91C_AES_PROCDLY ((unsigned int) 0xF << 4) // (AES) Processing Delay +#define AT91C_AES_SMOD ((unsigned int) 0x3 << 8) // (AES) Start Mode +#define AT91C_AES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. +#define AT91C_AES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). +#define AT91C_AES_SMOD_PDC ((unsigned int) 0x2 << 8) // (AES) PDC Mode (cf datasheet). +#define AT91C_AES_OPMOD ((unsigned int) 0x7 << 12) // (AES) Operation Mode +#define AT91C_AES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode. +#define AT91C_AES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode. +#define AT91C_AES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode. +#define AT91C_AES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode. +#define AT91C_AES_OPMOD_CTR ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode. +#define AT91C_AES_LOD ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode +#define AT91C_AES_CFBS ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size +#define AT91C_AES_CFBS_128_BIT ((unsigned int) 0x0 << 16) // (AES) 128-bit. +#define AT91C_AES_CFBS_64_BIT ((unsigned int) 0x1 << 16) // (AES) 64-bit. +#define AT91C_AES_CFBS_32_BIT ((unsigned int) 0x2 << 16) // (AES) 32-bit. +#define AT91C_AES_CFBS_16_BIT ((unsigned int) 0x3 << 16) // (AES) 16-bit. +#define AT91C_AES_CFBS_8_BIT ((unsigned int) 0x4 << 16) // (AES) 8-bit. +#define AT91C_AES_CKEY ((unsigned int) 0xF << 20) // (AES) Countermeasure Key +#define AT91C_AES_CTYPE ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type +#define AT91C_AES_CTYPE_TYPE1_EN ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled. +#define AT91C_AES_CTYPE_TYPE2_EN ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled. +#define AT91C_AES_CTYPE_TYPE3_EN ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled. +#define AT91C_AES_CTYPE_TYPE4_EN ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled. +#define AT91C_AES_CTYPE_TYPE5_EN ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled. +// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- +#define AT91C_AES_DATRDY ((unsigned int) 0x1 << 0) // (AES) DATRDY +#define AT91C_AES_ENDRX ((unsigned int) 0x1 << 1) // (AES) PDC Read Buffer End +#define AT91C_AES_ENDTX ((unsigned int) 0x1 << 2) // (AES) PDC Write Buffer End +#define AT91C_AES_RXBUFF ((unsigned int) 0x1 << 3) // (AES) PDC Read Buffer Full +#define AT91C_AES_TXBUFE ((unsigned int) 0x1 << 4) // (AES) PDC Write Buffer Empty +#define AT91C_AES_URAD ((unsigned int) 0x1 << 8) // (AES) Unspecified Register Access Detection +// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- +// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- +// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- +#define AT91C_AES_URAT ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status +#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode. +#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing. +#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing. +#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation. +#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation. +#define AT91C_AES_URAT_WO_REG_READ ((unsigned int) 0x5 << 12) // (AES) Write-only register read access. + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard +// ***************************************************************************** +typedef struct _AT91S_TDES { + AT91_REG TDES_CR; // Control Register + AT91_REG TDES_MR; // Mode Register + AT91_REG Reserved0[2]; // + AT91_REG TDES_IER; // Interrupt Enable Register + AT91_REG TDES_IDR; // Interrupt Disable Register + AT91_REG TDES_IMR; // Interrupt Mask Register + AT91_REG TDES_ISR; // Interrupt Status Register + AT91_REG TDES_KEY1WxR[2]; // Key 1 Word x Register + AT91_REG TDES_KEY2WxR[2]; // Key 2 Word x Register + AT91_REG TDES_KEY3WxR[2]; // Key 3 Word x Register + AT91_REG Reserved1[2]; // + AT91_REG TDES_IDATAxR[2]; // Input Data x Register + AT91_REG Reserved2[2]; // + AT91_REG TDES_ODATAxR[2]; // Output Data x Register + AT91_REG Reserved3[2]; // + AT91_REG TDES_IVxR[2]; // Initialization Vector x Register + AT91_REG Reserved4[37]; // + AT91_REG TDES_VR; // TDES Version Register + AT91_REG TDES_RPR; // Receive Pointer Register + AT91_REG TDES_RCR; // Receive Counter Register + AT91_REG TDES_TPR; // Transmit Pointer Register + AT91_REG TDES_TCR; // Transmit Counter Register + AT91_REG TDES_RNPR; // Receive Next Pointer Register + AT91_REG TDES_RNCR; // Receive Next Counter Register + AT91_REG TDES_TNPR; // Transmit Next Pointer Register + AT91_REG TDES_TNCR; // Transmit Next Counter Register + AT91_REG TDES_PTCR; // PDC Transfer Control Register + AT91_REG TDES_PTSR; // PDC Transfer Status Register +} AT91S_TDES, *AT91PS_TDES; + +// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- +#define AT91C_TDES_START ((unsigned int) 0x1 << 0) // (TDES) Starts Processing +#define AT91C_TDES_SWRST ((unsigned int) 0x1 << 8) // (TDES) Software Reset +// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- +#define AT91C_TDES_CIPHER ((unsigned int) 0x1 << 0) // (TDES) Processing Mode +#define AT91C_TDES_TDESMOD ((unsigned int) 0x1 << 1) // (TDES) Single or Triple DES Mode +#define AT91C_TDES_KEYMOD ((unsigned int) 0x1 << 4) // (TDES) Key Mode +#define AT91C_TDES_SMOD ((unsigned int) 0x3 << 8) // (TDES) Start Mode +#define AT91C_TDES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. +#define AT91C_TDES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). +#define AT91C_TDES_SMOD_PDC ((unsigned int) 0x2 << 8) // (TDES) PDC Mode (cf datasheet). +#define AT91C_TDES_OPMOD ((unsigned int) 0x3 << 12) // (TDES) Operation Mode +#define AT91C_TDES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode. +#define AT91C_TDES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode. +#define AT91C_TDES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode. +#define AT91C_TDES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode. +#define AT91C_TDES_LOD ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode +#define AT91C_TDES_CFBS ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size +#define AT91C_TDES_CFBS_64_BIT ((unsigned int) 0x0 << 16) // (TDES) 64-bit. +#define AT91C_TDES_CFBS_32_BIT ((unsigned int) 0x1 << 16) // (TDES) 32-bit. +#define AT91C_TDES_CFBS_16_BIT ((unsigned int) 0x2 << 16) // (TDES) 16-bit. +#define AT91C_TDES_CFBS_8_BIT ((unsigned int) 0x3 << 16) // (TDES) 8-bit. +// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- +#define AT91C_TDES_DATRDY ((unsigned int) 0x1 << 0) // (TDES) DATRDY +#define AT91C_TDES_ENDRX ((unsigned int) 0x1 << 1) // (TDES) PDC Read Buffer End +#define AT91C_TDES_ENDTX ((unsigned int) 0x1 << 2) // (TDES) PDC Write Buffer End +#define AT91C_TDES_RXBUFF ((unsigned int) 0x1 << 3) // (TDES) PDC Read Buffer Full +#define AT91C_TDES_TXBUFE ((unsigned int) 0x1 << 4) // (TDES) PDC Write Buffer Empty +#define AT91C_TDES_URAD ((unsigned int) 0x1 << 8) // (TDES) Unspecified Register Access Detection +// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- +// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- +// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- +#define AT91C_TDES_URAT ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status +#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode. +#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing. +#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing. +#define AT91C_TDES_URAT_WO_REG_READ ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access. + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7X128 +// ***************************************************************************** +// ========== Register definition for SYS peripheral ========== +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register +#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register +#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register +#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register +#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register +// ========== Register definition for PIOB peripheral ========== +#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register +#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register +#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register +#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register +#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register +#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register +#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register +#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register +#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register +#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register +#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register +#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register +#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register +#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register +#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register +#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register +#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr +#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register +#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register +#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register +#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register +#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register +#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register +#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register +#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register +#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register +#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register +#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register +#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register +#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register +#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register +#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register +#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register +#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register +// ========== Register definition for VREG peripheral ========== +#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register +#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register +#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register +#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register +// ========== Register definition for PDC_SPI1 peripheral ========== +#define AT91C_SPI1_PTCR ((AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register +#define AT91C_SPI1_RPR ((AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register +#define AT91C_SPI1_TNCR ((AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register +#define AT91C_SPI1_TPR ((AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register +#define AT91C_SPI1_TNPR ((AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register +#define AT91C_SPI1_TCR ((AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register +#define AT91C_SPI1_RCR ((AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register +#define AT91C_SPI1_RNPR ((AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register +#define AT91C_SPI1_RNCR ((AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register +#define AT91C_SPI1_PTSR ((AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register +// ========== Register definition for SPI1 peripheral ========== +#define AT91C_SPI1_IMR ((AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register +#define AT91C_SPI1_IER ((AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register +#define AT91C_SPI1_MR ((AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register +#define AT91C_SPI1_RDR ((AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register +#define AT91C_SPI1_IDR ((AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register +#define AT91C_SPI1_SR ((AT91_REG *) 0xFFFE4010) // (SPI1) Status Register +#define AT91C_SPI1_TDR ((AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register +#define AT91C_SPI1_CR ((AT91_REG *) 0xFFFE4000) // (SPI1) Control Register +#define AT91C_SPI1_CSR ((AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register +// ========== Register definition for PDC_SPI0 peripheral ========== +#define AT91C_SPI0_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register +#define AT91C_SPI0_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register +#define AT91C_SPI0_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register +#define AT91C_SPI0_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register +#define AT91C_SPI0_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register +#define AT91C_SPI0_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register +#define AT91C_SPI0_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register +#define AT91C_SPI0_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register +#define AT91C_SPI0_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register +#define AT91C_SPI0_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register +// ========== Register definition for SPI0 peripheral ========== +#define AT91C_SPI0_IER ((AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register +#define AT91C_SPI0_SR ((AT91_REG *) 0xFFFE0010) // (SPI0) Status Register +#define AT91C_SPI0_IDR ((AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register +#define AT91C_SPI0_CR ((AT91_REG *) 0xFFFE0000) // (SPI0) Control Register +#define AT91C_SPI0_MR ((AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register +#define AT91C_SPI0_IMR ((AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register +#define AT91C_SPI0_TDR ((AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register +#define AT91C_SPI0_RDR ((AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register +#define AT91C_SPI0_CSR ((AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register +#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register +#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register +#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register +#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register +#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register +#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register +#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register +#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register +#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register +#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register +#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register +#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for CAN_MB0 peripheral ========== +#define AT91C_CAN_MB0_MDL ((AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register +#define AT91C_CAN_MB0_MAM ((AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register +#define AT91C_CAN_MB0_MCR ((AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register +#define AT91C_CAN_MB0_MID ((AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register +#define AT91C_CAN_MB0_MSR ((AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register +#define AT91C_CAN_MB0_MFID ((AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register +#define AT91C_CAN_MB0_MDH ((AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register +#define AT91C_CAN_MB0_MMR ((AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register +// ========== Register definition for CAN_MB1 peripheral ========== +#define AT91C_CAN_MB1_MDL ((AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register +#define AT91C_CAN_MB1_MID ((AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register +#define AT91C_CAN_MB1_MMR ((AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register +#define AT91C_CAN_MB1_MSR ((AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register +#define AT91C_CAN_MB1_MAM ((AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register +#define AT91C_CAN_MB1_MDH ((AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register +#define AT91C_CAN_MB1_MCR ((AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register +#define AT91C_CAN_MB1_MFID ((AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register +// ========== Register definition for CAN_MB2 peripheral ========== +#define AT91C_CAN_MB2_MCR ((AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register +#define AT91C_CAN_MB2_MDH ((AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register +#define AT91C_CAN_MB2_MID ((AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register +#define AT91C_CAN_MB2_MDL ((AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register +#define AT91C_CAN_MB2_MMR ((AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register +#define AT91C_CAN_MB2_MAM ((AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register +#define AT91C_CAN_MB2_MFID ((AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register +#define AT91C_CAN_MB2_MSR ((AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register +// ========== Register definition for CAN_MB3 peripheral ========== +#define AT91C_CAN_MB3_MFID ((AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register +#define AT91C_CAN_MB3_MAM ((AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register +#define AT91C_CAN_MB3_MID ((AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register +#define AT91C_CAN_MB3_MCR ((AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register +#define AT91C_CAN_MB3_MMR ((AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register +#define AT91C_CAN_MB3_MSR ((AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register +#define AT91C_CAN_MB3_MDL ((AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register +#define AT91C_CAN_MB3_MDH ((AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register +// ========== Register definition for CAN_MB4 peripheral ========== +#define AT91C_CAN_MB4_MID ((AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register +#define AT91C_CAN_MB4_MMR ((AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register +#define AT91C_CAN_MB4_MDH ((AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register +#define AT91C_CAN_MB4_MFID ((AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register +#define AT91C_CAN_MB4_MSR ((AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register +#define AT91C_CAN_MB4_MCR ((AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register +#define AT91C_CAN_MB4_MDL ((AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register +#define AT91C_CAN_MB4_MAM ((AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB5 peripheral ========== +#define AT91C_CAN_MB5_MSR ((AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register +#define AT91C_CAN_MB5_MCR ((AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register +#define AT91C_CAN_MB5_MFID ((AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register +#define AT91C_CAN_MB5_MDH ((AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register +#define AT91C_CAN_MB5_MID ((AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register +#define AT91C_CAN_MB5_MMR ((AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register +#define AT91C_CAN_MB5_MDL ((AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register +#define AT91C_CAN_MB5_MAM ((AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB6 peripheral ========== +#define AT91C_CAN_MB6_MFID ((AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register +#define AT91C_CAN_MB6_MID ((AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register +#define AT91C_CAN_MB6_MAM ((AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register +#define AT91C_CAN_MB6_MSR ((AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register +#define AT91C_CAN_MB6_MDL ((AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register +#define AT91C_CAN_MB6_MCR ((AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register +#define AT91C_CAN_MB6_MDH ((AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register +#define AT91C_CAN_MB6_MMR ((AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register +// ========== Register definition for CAN_MB7 peripheral ========== +#define AT91C_CAN_MB7_MCR ((AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register +#define AT91C_CAN_MB7_MDH ((AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register +#define AT91C_CAN_MB7_MFID ((AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register +#define AT91C_CAN_MB7_MDL ((AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register +#define AT91C_CAN_MB7_MID ((AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register +#define AT91C_CAN_MB7_MMR ((AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register +#define AT91C_CAN_MB7_MAM ((AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register +#define AT91C_CAN_MB7_MSR ((AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register +// ========== Register definition for CAN peripheral ========== +#define AT91C_CAN_TCR ((AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register +#define AT91C_CAN_IMR ((AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register +#define AT91C_CAN_IER ((AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register +#define AT91C_CAN_ECR ((AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register +#define AT91C_CAN_TIMESTP ((AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register +#define AT91C_CAN_MR ((AT91_REG *) 0xFFFD0000) // (CAN) Mode Register +#define AT91C_CAN_IDR ((AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register +#define AT91C_CAN_ACR ((AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register +#define AT91C_CAN_TIM ((AT91_REG *) 0xFFFD0018) // (CAN) Timer Register +#define AT91C_CAN_SR ((AT91_REG *) 0xFFFD0010) // (CAN) Status Register +#define AT91C_CAN_BR ((AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register +#define AT91C_CAN_VR ((AT91_REG *) 0xFFFD00FC) // (CAN) Version Register +// ========== Register definition for EMAC peripheral ========== +#define AT91C_EMAC_ISR ((AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register +#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes +#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes +#define AT91C_EMAC_ELE ((AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register +#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register +#define AT91C_EMAC_RLE ((AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register +#define AT91C_EMAC_WOL ((AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register +#define AT91C_EMAC_DTF ((AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register +#define AT91C_EMAC_TUND ((AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register +#define AT91C_EMAC_NCR ((AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register +#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes +#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register +#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes +#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register +#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register +#define AT91C_EMAC_RSE ((AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register +#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register +#define AT91C_EMAC_TID ((AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register +#define AT91C_EMAC_HRB ((AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] +#define AT91C_EMAC_TBQP ((AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer +#define AT91C_EMAC_USRIO ((AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register +#define AT91C_EMAC_PTR ((AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register +#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes +#define AT91C_EMAC_ROV ((AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register +#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register +#define AT91C_EMAC_RJA ((AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register +#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer +#define AT91C_EMAC_TPF ((AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register +#define AT91C_EMAC_NCFGR ((AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register +#define AT91C_EMAC_HRT ((AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32] +#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register +#define AT91C_EMAC_FCSE ((AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register +#define AT91C_EMAC_TPQ ((AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register +#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register +#define AT91C_EMAC_FTO ((AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register +#define AT91C_EMAC_REV ((AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register +#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register +#define AT91C_EMAC_SCF ((AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register +#define AT91C_EMAC_PFR ((AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register +#define AT91C_EMAC_MCF ((AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register +#define AT91C_EMAC_NSR ((AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register +#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes +#define AT91C_EMAC_FRO ((AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register +#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register +#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes +#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register +#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes +#define AT91C_EMAC_RRE ((AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register +#define AT91C_EMAC_STE ((AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register +#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register +// ========== Register definition for PDC_AES peripheral ========== +#define AT91C_AES_TPR ((AT91_REG *) 0xFFFA4108) // (PDC_AES) Transmit Pointer Register +#define AT91C_AES_PTCR ((AT91_REG *) 0xFFFA4120) // (PDC_AES) PDC Transfer Control Register +#define AT91C_AES_RNPR ((AT91_REG *) 0xFFFA4110) // (PDC_AES) Receive Next Pointer Register +#define AT91C_AES_TNCR ((AT91_REG *) 0xFFFA411C) // (PDC_AES) Transmit Next Counter Register +#define AT91C_AES_TCR ((AT91_REG *) 0xFFFA410C) // (PDC_AES) Transmit Counter Register +#define AT91C_AES_RCR ((AT91_REG *) 0xFFFA4104) // (PDC_AES) Receive Counter Register +#define AT91C_AES_RNCR ((AT91_REG *) 0xFFFA4114) // (PDC_AES) Receive Next Counter Register +#define AT91C_AES_TNPR ((AT91_REG *) 0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register +#define AT91C_AES_RPR ((AT91_REG *) 0xFFFA4100) // (PDC_AES) Receive Pointer Register +#define AT91C_AES_PTSR ((AT91_REG *) 0xFFFA4124) // (PDC_AES) PDC Transfer Status Register +// ========== Register definition for AES peripheral ========== +#define AT91C_AES_IVxR ((AT91_REG *) 0xFFFA4060) // (AES) Initialization Vector x Register +#define AT91C_AES_MR ((AT91_REG *) 0xFFFA4004) // (AES) Mode Register +#define AT91C_AES_VR ((AT91_REG *) 0xFFFA40FC) // (AES) AES Version Register +#define AT91C_AES_ODATAxR ((AT91_REG *) 0xFFFA4050) // (AES) Output Data x Register +#define AT91C_AES_IDATAxR ((AT91_REG *) 0xFFFA4040) // (AES) Input Data x Register +#define AT91C_AES_CR ((AT91_REG *) 0xFFFA4000) // (AES) Control Register +#define AT91C_AES_IDR ((AT91_REG *) 0xFFFA4014) // (AES) Interrupt Disable Register +#define AT91C_AES_IMR ((AT91_REG *) 0xFFFA4018) // (AES) Interrupt Mask Register +#define AT91C_AES_IER ((AT91_REG *) 0xFFFA4010) // (AES) Interrupt Enable Register +#define AT91C_AES_KEYWxR ((AT91_REG *) 0xFFFA4020) // (AES) Key Word x Register +#define AT91C_AES_ISR ((AT91_REG *) 0xFFFA401C) // (AES) Interrupt Status Register +// ========== Register definition for PDC_TDES peripheral ========== +#define AT91C_TDES_RNCR ((AT91_REG *) 0xFFFA8114) // (PDC_TDES) Receive Next Counter Register +#define AT91C_TDES_TCR ((AT91_REG *) 0xFFFA810C) // (PDC_TDES) Transmit Counter Register +#define AT91C_TDES_RCR ((AT91_REG *) 0xFFFA8104) // (PDC_TDES) Receive Counter Register +#define AT91C_TDES_TNPR ((AT91_REG *) 0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register +#define AT91C_TDES_RNPR ((AT91_REG *) 0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register +#define AT91C_TDES_RPR ((AT91_REG *) 0xFFFA8100) // (PDC_TDES) Receive Pointer Register +#define AT91C_TDES_TNCR ((AT91_REG *) 0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register +#define AT91C_TDES_TPR ((AT91_REG *) 0xFFFA8108) // (PDC_TDES) Transmit Pointer Register +#define AT91C_TDES_PTSR ((AT91_REG *) 0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register +#define AT91C_TDES_PTCR ((AT91_REG *) 0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register +// ========== Register definition for TDES peripheral ========== +#define AT91C_TDES_KEY2WxR ((AT91_REG *) 0xFFFA8028) // (TDES) Key 2 Word x Register +#define AT91C_TDES_KEY3WxR ((AT91_REG *) 0xFFFA8030) // (TDES) Key 3 Word x Register +#define AT91C_TDES_IDR ((AT91_REG *) 0xFFFA8014) // (TDES) Interrupt Disable Register +#define AT91C_TDES_VR ((AT91_REG *) 0xFFFA80FC) // (TDES) TDES Version Register +#define AT91C_TDES_IVxR ((AT91_REG *) 0xFFFA8060) // (TDES) Initialization Vector x Register +#define AT91C_TDES_ODATAxR ((AT91_REG *) 0xFFFA8050) // (TDES) Output Data x Register +#define AT91C_TDES_IMR ((AT91_REG *) 0xFFFA8018) // (TDES) Interrupt Mask Register +#define AT91C_TDES_MR ((AT91_REG *) 0xFFFA8004) // (TDES) Mode Register +#define AT91C_TDES_CR ((AT91_REG *) 0xFFFA8000) // (TDES) Control Register +#define AT91C_TDES_IER ((AT91_REG *) 0xFFFA8010) // (TDES) Interrupt Enable Register +#define AT91C_TDES_ISR ((AT91_REG *) 0xFFFA801C) // (TDES) Interrupt Status Register +#define AT91C_TDES_IDATAxR ((AT91_REG *) 0xFFFA8040) // (TDES) Input Data x Register +#define AT91C_TDES_KEY1WxR ((AT91_REG *) 0xFFFA8020) // (TDES) Key 1 Word x Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7X128 +// ***************************************************************************** +#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data +#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data +#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data +#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock +#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_NPCS00 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 +#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_NPCS01 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_NPCS02 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1 +#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_NPCS03 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input +#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_MISO0 ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave +#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_MOSI0 ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave +#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_SPCK0 ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock +#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive +#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PA2_NPCS11 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit +#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync +#define AT91C_PA21_NPCS10 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 +#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock +#define AT91C_PA22_SPCK1 ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock +#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data +#define AT91C_PA23_MOSI1 ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave +#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data +#define AT91C_PA24_MISO1 ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave +#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock +#define AT91C_PA25_NPCS11 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync +#define AT91C_PA26_NPCS12 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data +#define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3 +#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data +#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input +#define AT91C_PA29_NPCS13 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send +#define AT91C_PA3_NPCS12 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0 +#define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send +#define AT91C_PA4_NPCS13 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data +#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data +#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock +#define AT91C_PA7_NPCS01 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send +#define AT91C_PA8_NPCS02 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send +#define AT91C_PA9_NPCS03 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0 +#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock +#define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1 +#define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable +#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10 +#define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 +#define AT91C_PB10_NPCS11 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11 +#define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 +#define AT91C_PB11_NPCS12 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12 +#define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error +#define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input +#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13 +#define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 +#define AT91C_PB13_NPCS01 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14 +#define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 +#define AT91C_PB14_NPCS02 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15 +#define AT91C_PB15_ERXDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid +#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16 +#define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected +#define AT91C_PB16_NPCS13 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17 +#define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock +#define AT91C_PB17_NPCS03 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18 +#define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec +#define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger +#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19 +#define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0 +#define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input +#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2 +#define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 +#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20 +#define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1 +#define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21 +#define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2 +#define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22 +#define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3 +#define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23 +#define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect +#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24 +#define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready +#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25 +#define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready +#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26 +#define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator +#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27 +#define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0 +#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28 +#define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1 +#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29 +#define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1 +#define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2 +#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3 +#define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 +#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30 +#define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2 +#define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3 +#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4 +#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid +#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5 +#define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 +#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6 +#define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 +#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7 +#define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error +#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8 +#define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock +#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9 +#define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X128 +// ***************************************************************************** +#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral +#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A +#define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B +#define AT91C_ID_SPI0 ((unsigned int) 4) // Serial Peripheral Interface 0 +#define AT91C_ID_SPI1 ((unsigned int) 5) // Serial Peripheral Interface 1 +#define AT91C_ID_US0 ((unsigned int) 6) // USART 0 +#define AT91C_ID_US1 ((unsigned int) 7) // USART 1 +#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface +#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller +#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port +#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0 +#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1 +#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2 +#define AT91C_ID_CAN ((unsigned int) 15) // Control Area Network Controller +#define AT91C_ID_EMAC ((unsigned int) 16) // Ethernet MAC +#define AT91C_ID_ADC ((unsigned int) 17) // Analog-to-Digital Converter +#define AT91C_ID_AES ((unsigned int) 18) // Advanced Encryption Standard 128-bit +#define AT91C_ID_TDES ((unsigned int) 19) // Triple Data Encryption Standard +#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved +#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved +#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved +#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved +#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved +#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved +#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved +#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved +#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved +#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved +#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1) + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7X128 +// ***************************************************************************** +#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address +#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address +#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address +#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address +#define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address +#define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address +#define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address +#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address +#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_CAN_MB0 ((AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address +#define AT91C_BASE_CAN_MB1 ((AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address +#define AT91C_BASE_CAN_MB2 ((AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address +#define AT91C_BASE_CAN_MB3 ((AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address +#define AT91C_BASE_CAN_MB4 ((AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address +#define AT91C_BASE_CAN_MB5 ((AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address +#define AT91C_BASE_CAN_MB6 ((AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address +#define AT91C_BASE_CAN_MB7 ((AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address +#define AT91C_BASE_CAN ((AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address +#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address +#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address +#define AT91C_BASE_PDC_AES ((AT91PS_PDC) 0xFFFA4100) // (PDC_AES) Base Address +#define AT91C_BASE_AES ((AT91PS_AES) 0xFFFA4000) // (AES) Base Address +#define AT91C_BASE_PDC_TDES ((AT91PS_PDC) 0xFFFA8100) // (PDC_TDES) Base Address +#define AT91C_BASE_TDES ((AT91PS_TDES) 0xFFFA8000) // (TDES) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X128 +// ***************************************************************************** +#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE ((unsigned int) 0x00008000) // Internal SRAM size in byte (32 Kbyte) +#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address +#define AT91C_IFLASH_SIZE ((unsigned int) 0x00020000) // Internal ROM size in byte (128 Kbyte) + +#endif diff --git a/20080212/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h b/20080212/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h new file mode 100644 index 000000000..96b680a5e --- /dev/null +++ b/20080212/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h @@ -0,0 +1,2446 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM7X128.h +// Object : AT91SAM7X128 definitions +// Generated : AT91 SW Application Group 05/20/2005 (16:22:23) +// +// CVS Reference : /AT91SAM7X128.pl/1.14/Tue May 10 12:12:05 2005// +// CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// +// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// +// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// +// CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// +// CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// +// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// +// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// +// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// +// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// +// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// +// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// +// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// +// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// +// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// +// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// +// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// +// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// +// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// +// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// +// CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// +// CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// +// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// +// CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// +// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// +// ---------------------------------------------------------------------------- + +// Hardware register definition + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +// *** Register offset in AT91S_AIC structure *** +#define AIC_SMR ( 0) // Source Mode Register +#define AIC_SVR (128) // Source Vector Register +#define AIC_IVR (256) // IRQ Vector Register +#define AIC_FVR (260) // FIQ Vector Register +#define AIC_ISR (264) // Interrupt Status Register +#define AIC_IPR (268) // Interrupt Pending Register +#define AIC_IMR (272) // Interrupt Mask Register +#define AIC_CISR (276) // Core Interrupt Status Register +#define AIC_IECR (288) // Interrupt Enable Command Register +#define AIC_IDCR (292) // Interrupt Disable Command Register +#define AIC_ICCR (296) // Interrupt Clear Command Register +#define AIC_ISCR (300) // Interrupt Set Command Register +#define AIC_EOICR (304) // End of Interrupt Command Register +#define AIC_SPU (308) // Spurious Vector Register +#define AIC_DCR (312) // Debug Control Register (Protect) +#define AIC_FFER (320) // Fast Forcing Enable Register +#define AIC_FFDR (324) // Fast Forcing Disable Register +#define AIC_FFSR (328) // Fast Forcing Status Register +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// ***************************************************************************** +// *** Register offset in AT91S_PDC structure *** +#define PDC_RPR ( 0) // Receive Pointer Register +#define PDC_RCR ( 4) // Receive Counter Register +#define PDC_TPR ( 8) // Transmit Pointer Register +#define PDC_TCR (12) // Transmit Counter Register +#define PDC_RNPR (16) // Receive Next Pointer Register +#define PDC_RNCR (20) // Receive Next Counter Register +#define PDC_TNPR (24) // Transmit Next Pointer Register +#define PDC_TNCR (28) // Transmit Next Counter Register +#define PDC_PTCR (32) // PDC Transfer Control Register +#define PDC_PTSR (36) // PDC Transfer Status Register +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +// *** Register offset in AT91S_DBGU structure *** +#define DBGU_CR ( 0) // Control Register +#define DBGU_MR ( 4) // Mode Register +#define DBGU_IER ( 8) // Interrupt Enable Register +#define DBGU_IDR (12) // Interrupt Disable Register +#define DBGU_IMR (16) // Interrupt Mask Register +#define DBGU_CSR (20) // Channel Status Register +#define DBGU_RHR (24) // Receiver Holding Register +#define DBGU_THR (28) // Transmitter Holding Register +#define DBGU_BRGR (32) // Baud Rate Generator Register +#define DBGU_CIDR (64) // Chip ID Register +#define DBGU_EXID (68) // Chip ID Extension Register +#define DBGU_FNTR (72) // Force NTRST Register +#define DBGU_RPR (256) // Receive Pointer Register +#define DBGU_RCR (260) // Receive Counter Register +#define DBGU_TPR (264) // Transmit Pointer Register +#define DBGU_TCR (268) // Transmit Counter Register +#define DBGU_RNPR (272) // Receive Next Pointer Register +#define DBGU_RNCR (276) // Receive Next Counter Register +#define DBGU_TNPR (280) // Transmit Next Pointer Register +#define DBGU_TNCR (284) // Transmit Next Counter Register +#define DBGU_PTCR (288) // PDC Transfer Control Register +#define DBGU_PTSR (292) // PDC Transfer Status Register +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable +#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +// *** Register offset in AT91S_PIO structure *** +#define PIO_PER ( 0) // PIO Enable Register +#define PIO_PDR ( 4) // PIO Disable Register +#define PIO_PSR ( 8) // PIO Status Register +#define PIO_OER (16) // Output Enable Register +#define PIO_ODR (20) // Output Disable Registerr +#define PIO_OSR (24) // Output Status Register +#define PIO_IFER (32) // Input Filter Enable Register +#define PIO_IFDR (36) // Input Filter Disable Register +#define PIO_IFSR (40) // Input Filter Status Register +#define PIO_SODR (48) // Set Output Data Register +#define PIO_CODR (52) // Clear Output Data Register +#define PIO_ODSR (56) // Output Data Status Register +#define PIO_PDSR (60) // Pin Data Status Register +#define PIO_IER (64) // Interrupt Enable Register +#define PIO_IDR (68) // Interrupt Disable Register +#define PIO_IMR (72) // Interrupt Mask Register +#define PIO_ISR (76) // Interrupt Status Register +#define PIO_MDER (80) // Multi-driver Enable Register +#define PIO_MDDR (84) // Multi-driver Disable Register +#define PIO_MDSR (88) // Multi-driver Status Register +#define PIO_PPUDR (96) // Pull-up Disable Register +#define PIO_PPUER (100) // Pull-up Enable Register +#define PIO_PPUSR (104) // Pull-up Status Register +#define PIO_ASR (112) // Select A Register +#define PIO_BSR (116) // Select B Register +#define PIO_ABSR (120) // AB Select Status Register +#define PIO_OWER (160) // Output Write Enable Register +#define PIO_OWDR (164) // Output Write Disable Register +#define PIO_OWSR (168) // Output Write Status Register + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +// *** Register offset in AT91S_CKGR structure *** +#define CKGR_MOR ( 0) // Main Oscillator Register +#define CKGR_MCFR ( 4) // Main Clock Frequency Register +#define CKGR_PLLR (12) // PLL Register +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +// *** Register offset in AT91S_PMC structure *** +#define PMC_SCER ( 0) // System Clock Enable Register +#define PMC_SCDR ( 4) // System Clock Disable Register +#define PMC_SCSR ( 8) // System Clock Status Register +#define PMC_PCER (16) // Peripheral Clock Enable Register +#define PMC_PCDR (20) // Peripheral Clock Disable Register +#define PMC_PCSR (24) // Peripheral Clock Status Register +#define PMC_MOR (32) // Main Oscillator Register +#define PMC_MCFR (36) // Main Clock Frequency Register +#define PMC_PLLR (44) // PLL Register +#define PMC_MCKR (48) // Master Clock Register +#define PMC_PCKR (64) // Programmable Clock Register +#define PMC_IER (96) // Interrupt Enable Register +#define PMC_IDR (100) // Interrupt Disable Register +#define PMC_SR (104) // Status Register +#define PMC_IMR (108) // Interrupt Mask Register +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_RSTC structure *** +#define RSTC_RCR ( 0) // Reset Control Register +#define RSTC_RSR ( 4) // Reset Status Register +#define RSTC_RMR ( 8) // Reset Mode Register +// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset +#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset +#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password +// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status +#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status +#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type +#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured. +#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level +#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Enable +#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_RTTC structure *** +#define RTTC_RTMR ( 0) // Real-time Mode Register +#define RTTC_RTAR ( 4) // Real-time Alarm Register +#define RTTC_RTVR ( 8) // Real-time Value Register +#define RTTC_RTSR (12) // Real-time Status Register +// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value +// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value +// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_PITC structure *** +#define PITC_PIMR ( 0) // Period Interval Mode Register +#define PITC_PISR ( 4) // Period Interval Status Register +#define PITC_PIVR ( 8) // Period Interval Value Register +#define PITC_PIIR (12) // Period Interval Image Register +// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_WDTC structure *** +#define WDTC_WDCR ( 0) // Watchdog Control Register +#define WDTC_WDMR ( 4) // Watchdog Mode Register +#define WDTC_WDSR ( 8) // Watchdog Status Register +// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart +#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password +// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_VREG structure *** +#define VREG_MR ( 0) // Voltage Regulator Mode Register +// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- +#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_MC structure *** +#define MC_RCR ( 0) // MC Remap Control Register +#define MC_ASR ( 4) // MC Abort Status Register +#define MC_AASR ( 8) // MC Abort Address Status Register +#define MC_FMR (96) // MC Flash Mode Register +#define MC_FCR (100) // MC Flash Command Register +#define MC_FSR (104) // MC Flash Status Register +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready +#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error +#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error +#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming +#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State +#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number +// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command +#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit. +#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number +#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key +// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- +#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status +#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +// *** Register offset in AT91S_SPI structure *** +#define SPI_CR ( 0) // Control Register +#define SPI_MR ( 4) // Mode Register +#define SPI_RDR ( 8) // Receive Data Register +#define SPI_TDR (12) // Transmit Data Register +#define SPI_SR (16) // Status Register +#define SPI_IER (20) // Interrupt Enable Register +#define SPI_IDR (24) // Interrupt Disable Register +#define SPI_IMR (28) // Interrupt Mask Register +#define SPI_CSR (48) // Chip Select Register +#define SPI_RPR (256) // Receive Pointer Register +#define SPI_RCR (260) // Receive Counter Register +#define SPI_TPR (264) // Transmit Pointer Register +#define SPI_TCR (268) // Transmit Counter Register +#define SPI_RNPR (272) // Receive Next Pointer Register +#define SPI_RNCR (276) // Receive Next Counter Register +#define SPI_TNPR (280) // Transmit Next Pointer Register +#define SPI_TNCR (284) // Transmit Next Counter Register +#define SPI_PTCR (288) // PDC Transfer Control Register +#define SPI_PTSR (292) // PDC Transfer Status Register +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK +#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +// *** Register offset in AT91S_USART structure *** +#define US_CR ( 0) // Control Register +#define US_MR ( 4) // Mode Register +#define US_IER ( 8) // Interrupt Enable Register +#define US_IDR (12) // Interrupt Disable Register +#define US_IMR (16) // Interrupt Mask Register +#define US_CSR (20) // Channel Status Register +#define US_RHR (24) // Receiver Holding Register +#define US_THR (28) // Transmitter Holding Register +#define US_BRGR (32) // Baud Rate Generator Register +#define US_RTOR (36) // Receiver Time-out Register +#define US_TTGR (40) // Transmitter Time-guard Register +#define US_FIDI (64) // FI_DI_Ratio Register +#define US_NER (68) // Nb Errors Register +#define US_IF (76) // IRDA_FILTER Register +#define US_RPR (256) // Receive Pointer Register +#define US_RCR (260) // Receive Counter Register +#define US_TPR (264) // Transmit Pointer Register +#define US_TCR (268) // Transmit Counter Register +#define US_RNPR (272) // Receive Next Pointer Register +#define US_RNCR (276) // Receive Next Counter Register +#define US_TNPR (280) // Transmit Next Pointer Register +#define US_TNCR (284) // Transmit Next Counter Register +#define US_PTCR (288) // PDC Transfer Control Register +#define US_PTSR (292) // PDC Transfer Status Register +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_SSC structure *** +#define SSC_CR ( 0) // Control Register +#define SSC_CMR ( 4) // Clock Mode Register +#define SSC_RCMR (16) // Receive Clock ModeRegister +#define SSC_RFMR (20) // Receive Frame Mode Register +#define SSC_TCMR (24) // Transmit Clock Mode Register +#define SSC_TFMR (28) // Transmit Frame Mode Register +#define SSC_RHR (32) // Receive Holding Register +#define SSC_THR (36) // Transmit Holding Register +#define SSC_RSHR (48) // Receive Sync Holding Register +#define SSC_TSHR (52) // Transmit Sync Holding Register +#define SSC_SR (64) // Status Register +#define SSC_IER (68) // Interrupt Enable Register +#define SSC_IDR (72) // Interrupt Disable Register +#define SSC_IMR (76) // Interrupt Mask Register +#define SSC_RPR (256) // Receive Pointer Register +#define SSC_RCR (260) // Receive Counter Register +#define SSC_TPR (264) // Transmit Pointer Register +#define SSC_TCR (268) // Transmit Counter Register +#define SSC_RNPR (272) // Receive Next Pointer Register +#define SSC_RNCR (276) // Receive Next Counter Register +#define SSC_TNPR (280) // Transmit Next Pointer Register +#define SSC_TNCR (284) // Transmit Next Counter Register +#define SSC_PTCR (288) // PDC Transfer Control Register +#define SSC_PTSR (292) // PDC Transfer Status Register +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin +#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +// *** Register offset in AT91S_TWI structure *** +#define TWI_CR ( 0) // Control Register +#define TWI_MMR ( 4) // Master Mode Register +#define TWI_IADR (12) // Internal Address Register +#define TWI_CWGR (16) // Clock Waveform Generator Register +#define TWI_SR (32) // Status Register +#define TWI_IER (36) // Interrupt Enable Register +#define TWI_IDR (40) // Interrupt Disable Register +#define TWI_IMR (44) // Interrupt Mask Register +#define TWI_RHR (48) // Receive Holding Register +#define TWI_THR (52) // Transmit Holding Register +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +// *** Register offset in AT91S_PWMC_CH structure *** +#define PWMC_CMR ( 0) // Channel Mode Register +#define PWMC_CDTYR ( 4) // Channel Duty Cycle Register +#define PWMC_CPRDR ( 8) // Channel Period Register +#define PWMC_CCNTR (12) // Channel Counter Register +#define PWMC_CUPDR (16) // Channel Update Register +#define PWMC_Reserved (20) // Reserved +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_PWMC structure *** +#define PWMC_MR ( 0) // PWMC Mode Register +#define PWMC_ENA ( 4) // PWMC Enable Register +#define PWMC_DIS ( 8) // PWMC Disable Register +#define PWMC_SR (12) // PWMC Status Register +#define PWMC_IER (16) // PWMC Interrupt Enable Register +#define PWMC_IDR (20) // PWMC Interrupt Disable Register +#define PWMC_IMR (24) // PWMC Interrupt Mask Register +#define PWMC_ISR (28) // PWMC Interrupt Status Register +#define PWMC_VR (252) // PWMC Version Register +#define PWMC_CH (512) // PWMC Channel +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +// *** Register offset in AT91S_UDP structure *** +#define UDP_NUM ( 0) // Frame Number Register +#define UDP_GLBSTATE ( 4) // Global State Register +#define UDP_FADDR ( 8) // Function Address Register +#define UDP_IER (16) // Interrupt Enable Register +#define UDP_IDR (20) // Interrupt Disable Register +#define UDP_IMR (24) // Interrupt Mask Register +#define UDP_ISR (28) // Interrupt Status Register +#define UDP_ICR (32) // Interrupt Clear Register +#define UDP_RSTEP (40) // Reset Endpoint Register +#define UDP_CSR (48) // Endpoint Control and Status Register +#define UDP_FDR (80) // Endpoint FIFO Data Register +#define UDP_TXVC (116) // Transceiver Control Register +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured +#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume +#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt +#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt +#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 +#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4 +#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO +// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) +#define AT91C_UDP_PUON (0x1 << 9) // (UDP) Pull-up ON + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +// *** Register offset in AT91S_TC structure *** +#define TC_CCR ( 0) // Channel Control Register +#define TC_CMR ( 4) // Channel Mode Register (Capture Mode / Waveform Mode) +#define TC_CV (16) // Counter Value +#define TC_RA (20) // Register A +#define TC_RB (24) // Register B +#define TC_RC (28) // Register C +#define TC_SR (32) // Status Register +#define TC_IER (36) // Interrupt Enable Register +#define TC_IDR (40) // Interrupt Disable Register +#define TC_IMR (44) // Interrupt Mask Register +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE (0x1 << 15) // (TC) +#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger +#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +// *** Register offset in AT91S_TCB structure *** +#define TCB_TC0 ( 0) // TC Channel 0 +#define TCB_TC1 (64) // TC Channel 1 +#define TCB_TC2 (128) // TC Channel 2 +#define TCB_BCR (192) // TC Block Control Register +#define TCB_BMR (196) // TC Block Mode Register +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface +// ***************************************************************************** +// *** Register offset in AT91S_CAN_MB structure *** +#define CAN_MB_MMR ( 0) // MailBox Mode Register +#define CAN_MB_MAM ( 4) // MailBox Acceptance Mask Register +#define CAN_MB_MID ( 8) // MailBox ID Register +#define CAN_MB_MFID (12) // MailBox Family ID Register +#define CAN_MB_MSR (16) // MailBox Status Register +#define CAN_MB_MDL (20) // MailBox Data Low Register +#define CAN_MB_MDH (24) // MailBox Data High Register +#define CAN_MB_MCR (28) // MailBox Control Register +// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- +#define AT91C_CAN_MTIMEMARK (0xFFFF << 0) // (CAN_MB) Mailbox Timemark +#define AT91C_CAN_PRIOR (0xF << 16) // (CAN_MB) Mailbox Priority +#define AT91C_CAN_MOT (0x7 << 24) // (CAN_MB) Mailbox Object Type +#define AT91C_CAN_MOT_DIS (0x0 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RX (0x1 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RXOVERWRITE (0x2 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_TX (0x3 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_CONSUMER (0x4 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_PRODUCER (0x5 << 24) // (CAN_MB) +// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- +#define AT91C_CAN_MIDvB (0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode +#define AT91C_CAN_MIDvA (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode +#define AT91C_CAN_MIDE (0x1 << 29) // (CAN_MB) Identifier Version +// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- +// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- +// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- +#define AT91C_CAN_MTIMESTAMP (0xFFFF << 0) // (CAN_MB) Timer Value +#define AT91C_CAN_MDLC (0xF << 16) // (CAN_MB) Mailbox Data Length Code +#define AT91C_CAN_MRTR (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request +#define AT91C_CAN_MABT (0x1 << 22) // (CAN_MB) Mailbox Message Abort +#define AT91C_CAN_MRDY (0x1 << 23) // (CAN_MB) Mailbox Ready +#define AT91C_CAN_MMI (0x1 << 24) // (CAN_MB) Mailbox Message Ignored +// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- +// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- +// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- +#define AT91C_CAN_MACR (0x1 << 22) // (CAN_MB) Abort Request for Mailbox +#define AT91C_CAN_MTCR (0x1 << 23) // (CAN_MB) Mailbox Transfer Command + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network Interface +// ***************************************************************************** +// *** Register offset in AT91S_CAN structure *** +#define CAN_MR ( 0) // Mode Register +#define CAN_IER ( 4) // Interrupt Enable Register +#define CAN_IDR ( 8) // Interrupt Disable Register +#define CAN_IMR (12) // Interrupt Mask Register +#define CAN_SR (16) // Status Register +#define CAN_BR (20) // Baudrate Register +#define CAN_TIM (24) // Timer Register +#define CAN_TIMESTP (28) // Time Stamp Register +#define CAN_ECR (32) // Error Counter Register +#define CAN_TCR (36) // Transfer Command Register +#define CAN_ACR (40) // Abort Command Register +#define CAN_VR (252) // Version Register +#define CAN_MB0 (512) // CAN Mailbox 0 +#define CAN_MB1 (544) // CAN Mailbox 1 +#define CAN_MB2 (576) // CAN Mailbox 2 +#define CAN_MB3 (608) // CAN Mailbox 3 +#define CAN_MB4 (640) // CAN Mailbox 4 +#define CAN_MB5 (672) // CAN Mailbox 5 +#define CAN_MB6 (704) // CAN Mailbox 6 +#define CAN_MB7 (736) // CAN Mailbox 7 +#define CAN_MB8 (768) // CAN Mailbox 8 +#define CAN_MB9 (800) // CAN Mailbox 9 +#define CAN_MB10 (832) // CAN Mailbox 10 +#define CAN_MB11 (864) // CAN Mailbox 11 +#define CAN_MB12 (896) // CAN Mailbox 12 +#define CAN_MB13 (928) // CAN Mailbox 13 +#define CAN_MB14 (960) // CAN Mailbox 14 +#define CAN_MB15 (992) // CAN Mailbox 15 +// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- +#define AT91C_CAN_CANEN (0x1 << 0) // (CAN) CAN Controller Enable +#define AT91C_CAN_LPM (0x1 << 1) // (CAN) Disable/Enable Low Power Mode +#define AT91C_CAN_ABM (0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode +#define AT91C_CAN_OVL (0x1 << 3) // (CAN) Disable/Enable Overload Frame +#define AT91C_CAN_TEOF (0x1 << 4) // (CAN) Time Stamp messages at each end of Frame +#define AT91C_CAN_TTM (0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode +#define AT91C_CAN_TIMFRZ (0x1 << 6) // (CAN) Enable Timer Freeze +#define AT91C_CAN_DRPT (0x1 << 7) // (CAN) Disable Repeat +// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- +#define AT91C_CAN_MB0 (0x1 << 0) // (CAN) Mailbox 0 Flag +#define AT91C_CAN_MB1 (0x1 << 1) // (CAN) Mailbox 1 Flag +#define AT91C_CAN_MB2 (0x1 << 2) // (CAN) Mailbox 2 Flag +#define AT91C_CAN_MB3 (0x1 << 3) // (CAN) Mailbox 3 Flag +#define AT91C_CAN_MB4 (0x1 << 4) // (CAN) Mailbox 4 Flag +#define AT91C_CAN_MB5 (0x1 << 5) // (CAN) Mailbox 5 Flag +#define AT91C_CAN_MB6 (0x1 << 6) // (CAN) Mailbox 6 Flag +#define AT91C_CAN_MB7 (0x1 << 7) // (CAN) Mailbox 7 Flag +#define AT91C_CAN_MB8 (0x1 << 8) // (CAN) Mailbox 8 Flag +#define AT91C_CAN_MB9 (0x1 << 9) // (CAN) Mailbox 9 Flag +#define AT91C_CAN_MB10 (0x1 << 10) // (CAN) Mailbox 10 Flag +#define AT91C_CAN_MB11 (0x1 << 11) // (CAN) Mailbox 11 Flag +#define AT91C_CAN_MB12 (0x1 << 12) // (CAN) Mailbox 12 Flag +#define AT91C_CAN_MB13 (0x1 << 13) // (CAN) Mailbox 13 Flag +#define AT91C_CAN_MB14 (0x1 << 14) // (CAN) Mailbox 14 Flag +#define AT91C_CAN_MB15 (0x1 << 15) // (CAN) Mailbox 15 Flag +#define AT91C_CAN_ERRA (0x1 << 16) // (CAN) Error Active Mode Flag +#define AT91C_CAN_WARN (0x1 << 17) // (CAN) Warning Limit Flag +#define AT91C_CAN_ERRP (0x1 << 18) // (CAN) Error Passive Mode Flag +#define AT91C_CAN_BOFF (0x1 << 19) // (CAN) Bus Off Mode Flag +#define AT91C_CAN_SLEEP (0x1 << 20) // (CAN) Sleep Flag +#define AT91C_CAN_WAKEUP (0x1 << 21) // (CAN) Wakeup Flag +#define AT91C_CAN_TOVF (0x1 << 22) // (CAN) Timer Overflow Flag +#define AT91C_CAN_TSTP (0x1 << 23) // (CAN) Timestamp Flag +#define AT91C_CAN_CERR (0x1 << 24) // (CAN) CRC Error +#define AT91C_CAN_SERR (0x1 << 25) // (CAN) Stuffing Error +#define AT91C_CAN_AERR (0x1 << 26) // (CAN) Acknowledgment Error +#define AT91C_CAN_FERR (0x1 << 27) // (CAN) Form Error +#define AT91C_CAN_BERR (0x1 << 28) // (CAN) Bit Error +// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- +// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- +// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- +#define AT91C_CAN_RBSY (0x1 << 29) // (CAN) Receiver Busy +#define AT91C_CAN_TBSY (0x1 << 30) // (CAN) Transmitter Busy +#define AT91C_CAN_OVLY (0x1 << 31) // (CAN) Overload Busy +// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- +#define AT91C_CAN_PHASE2 (0x7 << 0) // (CAN) Phase 2 segment +#define AT91C_CAN_PHASE1 (0x7 << 4) // (CAN) Phase 1 segment +#define AT91C_CAN_PROPAG (0x7 << 8) // (CAN) Programmation time segment +#define AT91C_CAN_SYNC (0x3 << 12) // (CAN) Re-synchronization jump width segment +#define AT91C_CAN_BRP (0x7F << 16) // (CAN) Baudrate Prescaler +#define AT91C_CAN_SMP (0x1 << 24) // (CAN) Sampling mode +// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- +#define AT91C_CAN_TIMER (0xFFFF << 0) // (CAN) Timer field +// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- +// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- +#define AT91C_CAN_REC (0xFF << 0) // (CAN) Receive Error Counter +#define AT91C_CAN_TEC (0xFF << 16) // (CAN) Transmit Error Counter +// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- +#define AT91C_CAN_TIMRST (0x1 << 31) // (CAN) Timer Reset Field +// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 +// ***************************************************************************** +// *** Register offset in AT91S_EMAC structure *** +#define EMAC_NCR ( 0) // Network Control Register +#define EMAC_NCFGR ( 4) // Network Configuration Register +#define EMAC_NSR ( 8) // Network Status Register +#define EMAC_TSR (20) // Transmit Status Register +#define EMAC_RBQP (24) // Receive Buffer Queue Pointer +#define EMAC_TBQP (28) // Transmit Buffer Queue Pointer +#define EMAC_RSR (32) // Receive Status Register +#define EMAC_ISR (36) // Interrupt Status Register +#define EMAC_IER (40) // Interrupt Enable Register +#define EMAC_IDR (44) // Interrupt Disable Register +#define EMAC_IMR (48) // Interrupt Mask Register +#define EMAC_MAN (52) // PHY Maintenance Register +#define EMAC_PTR (56) // Pause Time Register +#define EMAC_PFR (60) // Pause Frames received Register +#define EMAC_FTO (64) // Frames Transmitted OK Register +#define EMAC_SCF (68) // Single Collision Frame Register +#define EMAC_MCF (72) // Multiple Collision Frame Register +#define EMAC_FRO (76) // Frames Received OK Register +#define EMAC_FCSE (80) // Frame Check Sequence Error Register +#define EMAC_ALE (84) // Alignment Error Register +#define EMAC_DTF (88) // Deferred Transmission Frame Register +#define EMAC_LCOL (92) // Late Collision Register +#define EMAC_ECOL (96) // Excessive Collision Register +#define EMAC_TUND (100) // Transmit Underrun Error Register +#define EMAC_CSE (104) // Carrier Sense Error Register +#define EMAC_RRE (108) // Receive Ressource Error Register +#define EMAC_ROV (112) // Receive Overrun Errors Register +#define EMAC_RSE (116) // Receive Symbol Errors Register +#define EMAC_ELE (120) // Excessive Length Errors Register +#define EMAC_RJA (124) // Receive Jabbers Register +#define EMAC_USF (128) // Undersize Frames Register +#define EMAC_STE (132) // SQE Test Error Register +#define EMAC_RLE (136) // Receive Length Field Mismatch Register +#define EMAC_TPF (140) // Transmitted Pause Frames Register +#define EMAC_HRB (144) // Hash Address Bottom[31:0] +#define EMAC_HRT (148) // Hash Address Top[63:32] +#define EMAC_SA1L (152) // Specific Address 1 Bottom, First 4 bytes +#define EMAC_SA1H (156) // Specific Address 1 Top, Last 2 bytes +#define EMAC_SA2L (160) // Specific Address 2 Bottom, First 4 bytes +#define EMAC_SA2H (164) // Specific Address 2 Top, Last 2 bytes +#define EMAC_SA3L (168) // Specific Address 3 Bottom, First 4 bytes +#define EMAC_SA3H (172) // Specific Address 3 Top, Last 2 bytes +#define EMAC_SA4L (176) // Specific Address 4 Bottom, First 4 bytes +#define EMAC_SA4H (180) // Specific Address 4 Top, Last 2 bytes +#define EMAC_TID (184) // Type ID Checking Register +#define EMAC_TPQ (188) // Transmit Pause Quantum Register +#define EMAC_USRIO (192) // USER Input/Output Register +#define EMAC_WOL (196) // Wake On LAN Register +#define EMAC_REV (252) // Revision Register +// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- +#define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. +#define AT91C_EMAC_LLB (0x1 << 1) // (EMAC) Loopback local. +#define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable. +#define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable. +#define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable. +#define AT91C_EMAC_CLRSTAT (0x1 << 5) // (EMAC) Clear statistics registers. +#define AT91C_EMAC_INCSTAT (0x1 << 6) // (EMAC) Increment statistics registers. +#define AT91C_EMAC_WESTAT (0x1 << 7) // (EMAC) Write enable for statistics registers. +#define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure. +#define AT91C_EMAC_TSTART (0x1 << 9) // (EMAC) Start Transmission. +#define AT91C_EMAC_THALT (0x1 << 10) // (EMAC) Transmission Halt. +#define AT91C_EMAC_TPFR (0x1 << 11) // (EMAC) Transmit pause frame +#define AT91C_EMAC_TZQ (0x1 << 12) // (EMAC) Transmit zero quantum pause frame +// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- +#define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed. +#define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex. +#define AT91C_EMAC_JFRAME (0x1 << 3) // (EMAC) Jumbo Frames. +#define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames. +#define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast. +#define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash event enable +#define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable. +#define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes. +#define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable. +#define AT91C_EMAC_CLK (0x3 << 10) // (EMAC) +#define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8 +#define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16 +#define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32 +#define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64 +#define AT91C_EMAC_RTY (0x1 << 12) // (EMAC) +#define AT91C_EMAC_PAE (0x1 << 13) // (EMAC) +#define AT91C_EMAC_RBOF (0x3 << 14) // (EMAC) +#define AT91C_EMAC_RBOF_OFFSET_0 (0x0 << 14) // (EMAC) no offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_1 (0x1 << 14) // (EMAC) one byte offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_2 (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_3 (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer +#define AT91C_EMAC_RLCE (0x1 << 16) // (EMAC) Receive Length field Checking Enable +#define AT91C_EMAC_DRFCS (0x1 << 17) // (EMAC) Discard Receive FCS +#define AT91C_EMAC_EFRHD (0x1 << 18) // (EMAC) +#define AT91C_EMAC_IRXFCS (0x1 << 19) // (EMAC) Ignore RX FCS +// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- +#define AT91C_EMAC_LINKR (0x1 << 0) // (EMAC) +#define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC) +#define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC) +// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- +#define AT91C_EMAC_UBR (0x1 << 0) // (EMAC) +#define AT91C_EMAC_COL (0x1 << 1) // (EMAC) +#define AT91C_EMAC_RLES (0x1 << 2) // (EMAC) +#define AT91C_EMAC_TGO (0x1 << 3) // (EMAC) Transmit Go +#define AT91C_EMAC_BEX (0x1 << 4) // (EMAC) Buffers exhausted mid frame +#define AT91C_EMAC_COMP (0x1 << 5) // (EMAC) +#define AT91C_EMAC_UND (0x1 << 6) // (EMAC) +// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- +#define AT91C_EMAC_BNA (0x1 << 0) // (EMAC) +#define AT91C_EMAC_REC (0x1 << 1) // (EMAC) +#define AT91C_EMAC_OVR (0x1 << 2) // (EMAC) +// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- +#define AT91C_EMAC_MFD (0x1 << 0) // (EMAC) +#define AT91C_EMAC_RCOMP (0x1 << 1) // (EMAC) +#define AT91C_EMAC_RXUBR (0x1 << 2) // (EMAC) +#define AT91C_EMAC_TXUBR (0x1 << 3) // (EMAC) +#define AT91C_EMAC_TUNDR (0x1 << 4) // (EMAC) +#define AT91C_EMAC_RLEX (0x1 << 5) // (EMAC) +#define AT91C_EMAC_TXERR (0x1 << 6) // (EMAC) +#define AT91C_EMAC_TCOMP (0x1 << 7) // (EMAC) +#define AT91C_EMAC_LINK (0x1 << 9) // (EMAC) +#define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC) +#define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC) +#define AT91C_EMAC_PFRE (0x1 << 12) // (EMAC) +#define AT91C_EMAC_PTZ (0x1 << 13) // (EMAC) +// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- +// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- +// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- +// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- +#define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_CODE (0x3 << 16) // (EMAC) +#define AT91C_EMAC_REGA (0x1F << 18) // (EMAC) +#define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC) +#define AT91C_EMAC_RW (0x3 << 28) // (EMAC) +#define AT91C_EMAC_SOF (0x3 << 30) // (EMAC) +// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- +#define AT91C_EMAC_RMII (0x1 << 0) // (EMAC) Reduce MII +// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- +#define AT91C_EMAC_IP (0xFFFF << 0) // (EMAC) ARP request IP address +#define AT91C_EMAC_MAG (0x1 << 16) // (EMAC) Magic packet event enable +#define AT91C_EMAC_ARP (0x1 << 17) // (EMAC) ARP request event enable +#define AT91C_EMAC_SA1 (0x1 << 18) // (EMAC) Specific address register 1 event enable +// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- +#define AT91C_EMAC_REVREF (0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_PARTREF (0xFFFF << 16) // (EMAC) + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +// *** Register offset in AT91S_ADC structure *** +#define ADC_CR ( 0) // ADC Control Register +#define ADC_MR ( 4) // ADC Mode Register +#define ADC_CHER (16) // ADC Channel Enable Register +#define ADC_CHDR (20) // ADC Channel Disable Register +#define ADC_CHSR (24) // ADC Channel Status Register +#define ADC_SR (28) // ADC Status Register +#define ADC_LCDR (32) // ADC Last Converted Data Register +#define ADC_IER (36) // ADC Interrupt Enable Register +#define ADC_IDR (40) // ADC Interrupt Disable Register +#define ADC_IMR (44) // ADC Interrupt Mask Register +#define ADC_CDR0 (48) // ADC Channel Data Register 0 +#define ADC_CDR1 (52) // ADC Channel Data Register 1 +#define ADC_CDR2 (56) // ADC Channel Data Register 2 +#define ADC_CDR3 (60) // ADC Channel Data Register 3 +#define ADC_CDR4 (64) // ADC Channel Data Register 4 +#define ADC_CDR5 (68) // ADC Channel Data Register 5 +#define ADC_CDR6 (72) // ADC Channel Data Register 6 +#define ADC_CDR7 (76) // ADC Channel Data Register 7 +#define ADC_RPR (256) // Receive Pointer Register +#define ADC_RCR (260) // Receive Counter Register +#define ADC_TPR (264) // Transmit Pointer Register +#define ADC_TCR (268) // Transmit Counter Register +#define ADC_RNPR (272) // Receive Next Pointer Register +#define ADC_RNCR (276) // Receive Next Counter Register +#define ADC_TNPR (280) // Transmit Next Pointer Register +#define ADC_TNCR (284) // Transmit Next Counter Register +#define ADC_PTCR (288) // PDC Transfer Control Register +#define ADC_PTSR (292) // PDC Transfer Status Register +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Encryption Standard +// ***************************************************************************** +// *** Register offset in AT91S_AES structure *** +#define AES_CR ( 0) // Control Register +#define AES_MR ( 4) // Mode Register +#define AES_IER (16) // Interrupt Enable Register +#define AES_IDR (20) // Interrupt Disable Register +#define AES_IMR (24) // Interrupt Mask Register +#define AES_ISR (28) // Interrupt Status Register +#define AES_KEYWxR (32) // Key Word x Register +#define AES_IDATAxR (64) // Input Data x Register +#define AES_ODATAxR (80) // Output Data x Register +#define AES_IVxR (96) // Initialization Vector x Register +#define AES_VR (252) // AES Version Register +#define AES_RPR (256) // Receive Pointer Register +#define AES_RCR (260) // Receive Counter Register +#define AES_TPR (264) // Transmit Pointer Register +#define AES_TCR (268) // Transmit Counter Register +#define AES_RNPR (272) // Receive Next Pointer Register +#define AES_RNCR (276) // Receive Next Counter Register +#define AES_TNPR (280) // Transmit Next Pointer Register +#define AES_TNCR (284) // Transmit Next Counter Register +#define AES_PTCR (288) // PDC Transfer Control Register +#define AES_PTSR (292) // PDC Transfer Status Register +// -------- AES_CR : (AES Offset: 0x0) Control Register -------- +#define AT91C_AES_START (0x1 << 0) // (AES) Starts Processing +#define AT91C_AES_SWRST (0x1 << 8) // (AES) Software Reset +#define AT91C_AES_LOADSEED (0x1 << 16) // (AES) Random Number Generator Seed Loading +// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- +#define AT91C_AES_CIPHER (0x1 << 0) // (AES) Processing Mode +#define AT91C_AES_PROCDLY (0xF << 4) // (AES) Processing Delay +#define AT91C_AES_SMOD (0x3 << 8) // (AES) Start Mode +#define AT91C_AES_SMOD_MANUAL (0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. +#define AT91C_AES_SMOD_AUTO (0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). +#define AT91C_AES_SMOD_PDC (0x2 << 8) // (AES) PDC Mode (cf datasheet). +#define AT91C_AES_OPMOD (0x7 << 12) // (AES) Operation Mode +#define AT91C_AES_OPMOD_ECB (0x0 << 12) // (AES) ECB Electronic CodeBook mode. +#define AT91C_AES_OPMOD_CBC (0x1 << 12) // (AES) CBC Cipher Block Chaining mode. +#define AT91C_AES_OPMOD_OFB (0x2 << 12) // (AES) OFB Output Feedback mode. +#define AT91C_AES_OPMOD_CFB (0x3 << 12) // (AES) CFB Cipher Feedback mode. +#define AT91C_AES_OPMOD_CTR (0x4 << 12) // (AES) CTR Counter mode. +#define AT91C_AES_LOD (0x1 << 15) // (AES) Last Output Data Mode +#define AT91C_AES_CFBS (0x7 << 16) // (AES) Cipher Feedback Data Size +#define AT91C_AES_CFBS_128_BIT (0x0 << 16) // (AES) 128-bit. +#define AT91C_AES_CFBS_64_BIT (0x1 << 16) // (AES) 64-bit. +#define AT91C_AES_CFBS_32_BIT (0x2 << 16) // (AES) 32-bit. +#define AT91C_AES_CFBS_16_BIT (0x3 << 16) // (AES) 16-bit. +#define AT91C_AES_CFBS_8_BIT (0x4 << 16) // (AES) 8-bit. +#define AT91C_AES_CKEY (0xF << 20) // (AES) Countermeasure Key +#define AT91C_AES_CTYPE (0x1F << 24) // (AES) Countermeasure Type +#define AT91C_AES_CTYPE_TYPE1_EN (0x1 << 24) // (AES) Countermeasure type 1 is enabled. +#define AT91C_AES_CTYPE_TYPE2_EN (0x2 << 24) // (AES) Countermeasure type 2 is enabled. +#define AT91C_AES_CTYPE_TYPE3_EN (0x4 << 24) // (AES) Countermeasure type 3 is enabled. +#define AT91C_AES_CTYPE_TYPE4_EN (0x8 << 24) // (AES) Countermeasure type 4 is enabled. +#define AT91C_AES_CTYPE_TYPE5_EN (0x10 << 24) // (AES) Countermeasure type 5 is enabled. +// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- +#define AT91C_AES_DATRDY (0x1 << 0) // (AES) DATRDY +#define AT91C_AES_ENDRX (0x1 << 1) // (AES) PDC Read Buffer End +#define AT91C_AES_ENDTX (0x1 << 2) // (AES) PDC Write Buffer End +#define AT91C_AES_RXBUFF (0x1 << 3) // (AES) PDC Read Buffer Full +#define AT91C_AES_TXBUFE (0x1 << 4) // (AES) PDC Write Buffer Empty +#define AT91C_AES_URAD (0x1 << 8) // (AES) Unspecified Register Access Detection +// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- +// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- +// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- +#define AT91C_AES_URAT (0x7 << 12) // (AES) Unspecified Register Access Type Status +#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (AES) Input data register written during the data processing in PDC mode. +#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (AES) Output data register read during the data processing. +#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (AES) Mode register written during the data processing. +#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY (0x3 << 12) // (AES) Output data register read during the sub-keys generation. +#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY (0x4 << 12) // (AES) Mode register written during the sub-keys generation. +#define AT91C_AES_URAT_WO_REG_READ (0x5 << 12) // (AES) Write-only register read access. + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard +// ***************************************************************************** +// *** Register offset in AT91S_TDES structure *** +#define TDES_CR ( 0) // Control Register +#define TDES_MR ( 4) // Mode Register +#define TDES_IER (16) // Interrupt Enable Register +#define TDES_IDR (20) // Interrupt Disable Register +#define TDES_IMR (24) // Interrupt Mask Register +#define TDES_ISR (28) // Interrupt Status Register +#define TDES_KEY1WxR (32) // Key 1 Word x Register +#define TDES_KEY2WxR (40) // Key 2 Word x Register +#define TDES_KEY3WxR (48) // Key 3 Word x Register +#define TDES_IDATAxR (64) // Input Data x Register +#define TDES_ODATAxR (80) // Output Data x Register +#define TDES_IVxR (96) // Initialization Vector x Register +#define TDES_VR (252) // TDES Version Register +#define TDES_RPR (256) // Receive Pointer Register +#define TDES_RCR (260) // Receive Counter Register +#define TDES_TPR (264) // Transmit Pointer Register +#define TDES_TCR (268) // Transmit Counter Register +#define TDES_RNPR (272) // Receive Next Pointer Register +#define TDES_RNCR (276) // Receive Next Counter Register +#define TDES_TNPR (280) // Transmit Next Pointer Register +#define TDES_TNCR (284) // Transmit Next Counter Register +#define TDES_PTCR (288) // PDC Transfer Control Register +#define TDES_PTSR (292) // PDC Transfer Status Register +// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- +#define AT91C_TDES_START (0x1 << 0) // (TDES) Starts Processing +#define AT91C_TDES_SWRST (0x1 << 8) // (TDES) Software Reset +// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- +#define AT91C_TDES_CIPHER (0x1 << 0) // (TDES) Processing Mode +#define AT91C_TDES_TDESMOD (0x1 << 1) // (TDES) Single or Triple DES Mode +#define AT91C_TDES_KEYMOD (0x1 << 4) // (TDES) Key Mode +#define AT91C_TDES_SMOD (0x3 << 8) // (TDES) Start Mode +#define AT91C_TDES_SMOD_MANUAL (0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. +#define AT91C_TDES_SMOD_AUTO (0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). +#define AT91C_TDES_SMOD_PDC (0x2 << 8) // (TDES) PDC Mode (cf datasheet). +#define AT91C_TDES_OPMOD (0x3 << 12) // (TDES) Operation Mode +#define AT91C_TDES_OPMOD_ECB (0x0 << 12) // (TDES) ECB Electronic CodeBook mode. +#define AT91C_TDES_OPMOD_CBC (0x1 << 12) // (TDES) CBC Cipher Block Chaining mode. +#define AT91C_TDES_OPMOD_OFB (0x2 << 12) // (TDES) OFB Output Feedback mode. +#define AT91C_TDES_OPMOD_CFB (0x3 << 12) // (TDES) CFB Cipher Feedback mode. +#define AT91C_TDES_LOD (0x1 << 15) // (TDES) Last Output Data Mode +#define AT91C_TDES_CFBS (0x3 << 16) // (TDES) Cipher Feedback Data Size +#define AT91C_TDES_CFBS_64_BIT (0x0 << 16) // (TDES) 64-bit. +#define AT91C_TDES_CFBS_32_BIT (0x1 << 16) // (TDES) 32-bit. +#define AT91C_TDES_CFBS_16_BIT (0x2 << 16) // (TDES) 16-bit. +#define AT91C_TDES_CFBS_8_BIT (0x3 << 16) // (TDES) 8-bit. +// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- +#define AT91C_TDES_DATRDY (0x1 << 0) // (TDES) DATRDY +#define AT91C_TDES_ENDRX (0x1 << 1) // (TDES) PDC Read Buffer End +#define AT91C_TDES_ENDTX (0x1 << 2) // (TDES) PDC Write Buffer End +#define AT91C_TDES_RXBUFF (0x1 << 3) // (TDES) PDC Read Buffer Full +#define AT91C_TDES_TXBUFE (0x1 << 4) // (TDES) PDC Write Buffer Empty +#define AT91C_TDES_URAD (0x1 << 8) // (TDES) Unspecified Register Access Detection +// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- +// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- +// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- +#define AT91C_TDES_URAT (0x3 << 12) // (TDES) Unspecified Register Access Type Status +#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode. +#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (TDES) Output data register read during the data processing. +#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (TDES) Mode register written during the data processing. +#define AT91C_TDES_URAT_WO_REG_READ (0x3 << 12) // (TDES) Write-only register read access. + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7X128 +// ***************************************************************************** +// ========== Register definition for SYS peripheral ========== +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_IVR (0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_SMR (0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_FVR (0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_DCR (0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_EOICR (0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_SVR (0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_FFSR (0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_ICCR (0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_ISR (0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IMR (0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_IPR (0xFFFFF10C) // (AIC) Interrupt Pending Register +#define AT91C_AIC_FFER (0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_IECR (0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_ISCR (0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_FFDR (0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_CISR (0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IDCR (0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_SPU (0xFFFFF134) // (AIC) Spurious Vector Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TCR (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RNPR (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +#define AT91C_DBGU_TPR (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RPR (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_RCR (0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_RNCR (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_TNCR (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_EXID (0xFFFFF244) // (DBGU) Chip ID Extension Register +#define AT91C_DBGU_BRGR (0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_IDR (0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_CSR (0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_CIDR (0xFFFFF240) // (DBGU) Chip ID Register +#define AT91C_DBGU_MR (0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_IMR (0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_CR (0xFFFFF200) // (DBGU) Control Register +#define AT91C_DBGU_FNTR (0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_THR (0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_RHR (0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IER (0xFFFFF208) // (DBGU) Interrupt Enable Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_ODR (0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_SODR (0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_ISR (0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_ABSR (0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_IER (0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_PPUDR (0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_IMR (0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_PER (0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_IFDR (0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_OWDR (0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_MDSR (0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_IDR (0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_ODSR (0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_PPUSR (0xFFFFF468) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_OWSR (0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_BSR (0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_OWER (0xFFFFF4A0) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IFER (0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_PDSR (0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_PPUER (0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_OSR (0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_ASR (0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_MDDR (0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_CODR (0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_MDER (0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PDR (0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_IFSR (0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_OER (0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_PSR (0xFFFFF408) // (PIOA) PIO Status Register +// ========== Register definition for PIOB peripheral ========== +#define AT91C_PIOB_OWDR (0xFFFFF6A4) // (PIOB) Output Write Disable Register +#define AT91C_PIOB_MDER (0xFFFFF650) // (PIOB) Multi-driver Enable Register +#define AT91C_PIOB_PPUSR (0xFFFFF668) // (PIOB) Pull-up Status Register +#define AT91C_PIOB_IMR (0xFFFFF648) // (PIOB) Interrupt Mask Register +#define AT91C_PIOB_ASR (0xFFFFF670) // (PIOB) Select A Register +#define AT91C_PIOB_PPUDR (0xFFFFF660) // (PIOB) Pull-up Disable Register +#define AT91C_PIOB_PSR (0xFFFFF608) // (PIOB) PIO Status Register +#define AT91C_PIOB_IER (0xFFFFF640) // (PIOB) Interrupt Enable Register +#define AT91C_PIOB_CODR (0xFFFFF634) // (PIOB) Clear Output Data Register +#define AT91C_PIOB_OWER (0xFFFFF6A0) // (PIOB) Output Write Enable Register +#define AT91C_PIOB_ABSR (0xFFFFF678) // (PIOB) AB Select Status Register +#define AT91C_PIOB_IFDR (0xFFFFF624) // (PIOB) Input Filter Disable Register +#define AT91C_PIOB_PDSR (0xFFFFF63C) // (PIOB) Pin Data Status Register +#define AT91C_PIOB_IDR (0xFFFFF644) // (PIOB) Interrupt Disable Register +#define AT91C_PIOB_OWSR (0xFFFFF6A8) // (PIOB) Output Write Status Register +#define AT91C_PIOB_PDR (0xFFFFF604) // (PIOB) PIO Disable Register +#define AT91C_PIOB_ODR (0xFFFFF614) // (PIOB) Output Disable Registerr +#define AT91C_PIOB_IFSR (0xFFFFF628) // (PIOB) Input Filter Status Register +#define AT91C_PIOB_PPUER (0xFFFFF664) // (PIOB) Pull-up Enable Register +#define AT91C_PIOB_SODR (0xFFFFF630) // (PIOB) Set Output Data Register +#define AT91C_PIOB_ISR (0xFFFFF64C) // (PIOB) Interrupt Status Register +#define AT91C_PIOB_ODSR (0xFFFFF638) // (PIOB) Output Data Status Register +#define AT91C_PIOB_OSR (0xFFFFF618) // (PIOB) Output Status Register +#define AT91C_PIOB_MDSR (0xFFFFF658) // (PIOB) Multi-driver Status Register +#define AT91C_PIOB_IFER (0xFFFFF620) // (PIOB) Input Filter Enable Register +#define AT91C_PIOB_BSR (0xFFFFF674) // (PIOB) Select B Register +#define AT91C_PIOB_MDDR (0xFFFFF654) // (PIOB) Multi-driver Disable Register +#define AT91C_PIOB_OER (0xFFFFF610) // (PIOB) Output Enable Register +#define AT91C_PIOB_PER (0xFFFFF600) // (PIOB) PIO Enable Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_MOR (0xFFFFFC20) // (CKGR) Main Oscillator Register +#define AT91C_CKGR_PLLR (0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR (0xFFFFFC24) // (CKGR) Main Clock Frequency Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_IDR (0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_MOR (0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PLLR (0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_PCER (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCKR (0xFFFFFC40) // (PMC) Programmable Clock Register +#define AT91C_PMC_MCKR (0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_SCDR (0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_PCDR (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCSR (0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_PCSR (0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_MCFR (0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_SCER (0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR (0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IER (0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_SR (0xFFFFFC68) // (PMC) Status Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RCR (0xFFFFFD00) // (RSTC) Reset Control Register +#define AT91C_RSTC_RMR (0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RSR (0xFFFFFD04) // (RSTC) Reset Status Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR (0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTMR (0xFFFFFD20) // (RTTC) Real-time Mode Register +#define AT91C_RTTC_RTVR (0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTAR (0xFFFFFD24) // (RTTC) Real-time Alarm Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIVR (0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PISR (0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIIR (0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PIMR (0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDCR (0xFFFFFD40) // (WDTC) Watchdog Control Register +#define AT91C_WDTC_WDSR (0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDMR (0xFFFFFD44) // (WDTC) Watchdog Mode Register +// ========== Register definition for VREG peripheral ========== +#define AT91C_VREG_MR (0xFFFFFD60) // (VREG) Voltage Regulator Mode Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_ASR (0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_RCR (0xFFFFFF00) // (MC) MC Remap Control Register +#define AT91C_MC_FCR (0xFFFFFF64) // (MC) MC Flash Command Register +#define AT91C_MC_AASR (0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_FSR (0xFFFFFF68) // (MC) MC Flash Status Register +#define AT91C_MC_FMR (0xFFFFFF60) // (MC) MC Flash Mode Register +// ========== Register definition for PDC_SPI1 peripheral ========== +#define AT91C_SPI1_PTCR (0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register +#define AT91C_SPI1_RPR (0xFFFE4100) // (PDC_SPI1) Receive Pointer Register +#define AT91C_SPI1_TNCR (0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register +#define AT91C_SPI1_TPR (0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register +#define AT91C_SPI1_TNPR (0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register +#define AT91C_SPI1_TCR (0xFFFE410C) // (PDC_SPI1) Transmit Counter Register +#define AT91C_SPI1_RCR (0xFFFE4104) // (PDC_SPI1) Receive Counter Register +#define AT91C_SPI1_RNPR (0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register +#define AT91C_SPI1_RNCR (0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register +#define AT91C_SPI1_PTSR (0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register +// ========== Register definition for SPI1 peripheral ========== +#define AT91C_SPI1_IMR (0xFFFE401C) // (SPI1) Interrupt Mask Register +#define AT91C_SPI1_IER (0xFFFE4014) // (SPI1) Interrupt Enable Register +#define AT91C_SPI1_MR (0xFFFE4004) // (SPI1) Mode Register +#define AT91C_SPI1_RDR (0xFFFE4008) // (SPI1) Receive Data Register +#define AT91C_SPI1_IDR (0xFFFE4018) // (SPI1) Interrupt Disable Register +#define AT91C_SPI1_SR (0xFFFE4010) // (SPI1) Status Register +#define AT91C_SPI1_TDR (0xFFFE400C) // (SPI1) Transmit Data Register +#define AT91C_SPI1_CR (0xFFFE4000) // (SPI1) Control Register +#define AT91C_SPI1_CSR (0xFFFE4030) // (SPI1) Chip Select Register +// ========== Register definition for PDC_SPI0 peripheral ========== +#define AT91C_SPI0_PTCR (0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register +#define AT91C_SPI0_TPR (0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register +#define AT91C_SPI0_TCR (0xFFFE010C) // (PDC_SPI0) Transmit Counter Register +#define AT91C_SPI0_RCR (0xFFFE0104) // (PDC_SPI0) Receive Counter Register +#define AT91C_SPI0_PTSR (0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register +#define AT91C_SPI0_RNPR (0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register +#define AT91C_SPI0_RPR (0xFFFE0100) // (PDC_SPI0) Receive Pointer Register +#define AT91C_SPI0_TNCR (0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register +#define AT91C_SPI0_RNCR (0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register +#define AT91C_SPI0_TNPR (0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register +// ========== Register definition for SPI0 peripheral ========== +#define AT91C_SPI0_IER (0xFFFE0014) // (SPI0) Interrupt Enable Register +#define AT91C_SPI0_SR (0xFFFE0010) // (SPI0) Status Register +#define AT91C_SPI0_IDR (0xFFFE0018) // (SPI0) Interrupt Disable Register +#define AT91C_SPI0_CR (0xFFFE0000) // (SPI0) Control Register +#define AT91C_SPI0_MR (0xFFFE0004) // (SPI0) Mode Register +#define AT91C_SPI0_IMR (0xFFFE001C) // (SPI0) Interrupt Mask Register +#define AT91C_SPI0_TDR (0xFFFE000C) // (SPI0) Transmit Data Register +#define AT91C_SPI0_RDR (0xFFFE0008) // (SPI0) Receive Data Register +#define AT91C_SPI0_CSR (0xFFFE0030) // (SPI0) Chip Select Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_RNCR (0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_PTCR (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TCR (0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_PTSR (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNPR (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RCR (0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_RNPR (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_RPR (0xFFFC4100) // (PDC_US1) Receive Pointer Register +#define AT91C_US1_TNCR (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_TPR (0xFFFC4108) // (PDC_US1) Transmit Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_IF (0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER (0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_RTOR (0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_CSR (0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR (0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_IER (0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_THR (0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_TTGR (0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_RHR (0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_BRGR (0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_IMR (0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_FIDI (0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_CR (0xFFFC4000) // (US1) Control Register +#define AT91C_US1_MR (0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_TNPR (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TCR (0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_PTCR (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_PTSR (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_TPR (0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RCR (0xFFFC0104) // (PDC_US0) Receive Counter Register +#define AT91C_US0_RPR (0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_RNCR (0xFFFC0114) // (PDC_US0) Receive Next Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_BRGR (0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_NER (0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_CR (0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IMR (0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_FIDI (0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_TTGR (0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_MR (0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_RTOR (0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_CSR (0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_RHR (0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IDR (0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_THR (0xFFFC001C) // (US0) Transmitter Holding Register +#define AT91C_US0_IF (0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_IER (0xFFFC0008) // (US0) Interrupt Enable Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_TNCR (0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RPR (0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_RNCR (0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TPR (0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_PTCR (0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TCR (0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR (0xFFFD4104) // (PDC_SSC) Receive Counter Register +#define AT91C_SSC_RNPR (0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TNPR (0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_PTSR (0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RHR (0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_RSHR (0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_TFMR (0xFFFD401C) // (SSC) Transmit Frame Mode Register +#define AT91C_SSC_IDR (0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_THR (0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_RCMR (0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_IER (0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_TSHR (0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_SR (0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_CMR (0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_TCMR (0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_CR (0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR (0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_RFMR (0xFFFD4014) // (SSC) Receive Frame Mode Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_IER (0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_CR (0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_SR (0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_IMR (0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_THR (0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IDR (0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_IADR (0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR (0xFFFB8004) // (TWI) Master Mode Register +#define AT91C_TWI_CWGR (0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_RHR (0xFFFB8030) // (TWI) Receive Holding Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_PWMC_CH3_CUPDR (0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_PWMC_CH3_Reserved (0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_PWMC_CH3_CPRDR (0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_PWMC_CH3_CDTYR (0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +#define AT91C_PWMC_CH3_CCNTR (0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_PWMC_CH3_CMR (0xFFFCC260) // (PWMC_CH3) Channel Mode Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_PWMC_CH2_Reserved (0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_PWMC_CH2_CMR (0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_PWMC_CH2_CCNTR (0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_PWMC_CH2_CPRDR (0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_PWMC_CH2_CUPDR (0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_PWMC_CH2_CDTYR (0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_PWMC_CH1_Reserved (0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_PWMC_CH1_CUPDR (0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_PWMC_CH1_CPRDR (0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_PWMC_CH1_CCNTR (0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_PWMC_CH1_CDTYR (0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +#define AT91C_PWMC_CH1_CMR (0xFFFCC220) // (PWMC_CH1) Channel Mode Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_PWMC_CH0_Reserved (0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_PWMC_CH0_CPRDR (0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_PWMC_CH0_CDTYR (0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +#define AT91C_PWMC_CH0_CMR (0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_PWMC_CH0_CUPDR (0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_PWMC_CH0_CCNTR (0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_IDR (0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_DIS (0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER (0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +#define AT91C_PWMC_VR (0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR (0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_SR (0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_IMR (0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR (0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_ENA (0xFFFCC004) // (PWMC) PWMC Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_IMR (0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_FADDR (0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM (0xFFFB0000) // (UDP) Frame Number Register +#define AT91C_UDP_FDR (0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_ISR (0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_CSR (0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_IDR (0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_ICR (0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_RSTEP (0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_TXVC (0xFFFB0074) // (UDP) Transceiver Control Register +#define AT91C_UDP_GLBSTATE (0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_IER (0xFFFB0010) // (UDP) Interrupt Enable Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_SR (0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RC (0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RB (0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CCR (0xFFFA0000) // (TC0) Channel Control Register +#define AT91C_TC0_CMR (0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IER (0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RA (0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_IDR (0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_CV (0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_IMR (0xFFFA002C) // (TC0) Interrupt Mask Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_RB (0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CCR (0xFFFA0040) // (TC1) Channel Control Register +#define AT91C_TC1_IER (0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_IDR (0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR (0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_CMR (0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_RA (0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_RC (0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_IMR (0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_CV (0xFFFA0050) // (TC1) Counter Value +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_CMR (0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_CCR (0xFFFA0080) // (TC2) Channel Control Register +#define AT91C_TC2_CV (0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_RA (0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_RB (0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_IDR (0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_IMR (0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_RC (0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_IER (0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_SR (0xFFFA00A0) // (TC2) Status Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR (0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR (0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for CAN_MB0 peripheral ========== +#define AT91C_CAN_MB0_MDL (0xFFFD0214) // (CAN_MB0) MailBox Data Low Register +#define AT91C_CAN_MB0_MAM (0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register +#define AT91C_CAN_MB0_MCR (0xFFFD021C) // (CAN_MB0) MailBox Control Register +#define AT91C_CAN_MB0_MID (0xFFFD0208) // (CAN_MB0) MailBox ID Register +#define AT91C_CAN_MB0_MSR (0xFFFD0210) // (CAN_MB0) MailBox Status Register +#define AT91C_CAN_MB0_MFID (0xFFFD020C) // (CAN_MB0) MailBox Family ID Register +#define AT91C_CAN_MB0_MDH (0xFFFD0218) // (CAN_MB0) MailBox Data High Register +#define AT91C_CAN_MB0_MMR (0xFFFD0200) // (CAN_MB0) MailBox Mode Register +// ========== Register definition for CAN_MB1 peripheral ========== +#define AT91C_CAN_MB1_MDL (0xFFFD0234) // (CAN_MB1) MailBox Data Low Register +#define AT91C_CAN_MB1_MID (0xFFFD0228) // (CAN_MB1) MailBox ID Register +#define AT91C_CAN_MB1_MMR (0xFFFD0220) // (CAN_MB1) MailBox Mode Register +#define AT91C_CAN_MB1_MSR (0xFFFD0230) // (CAN_MB1) MailBox Status Register +#define AT91C_CAN_MB1_MAM (0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register +#define AT91C_CAN_MB1_MDH (0xFFFD0238) // (CAN_MB1) MailBox Data High Register +#define AT91C_CAN_MB1_MCR (0xFFFD023C) // (CAN_MB1) MailBox Control Register +#define AT91C_CAN_MB1_MFID (0xFFFD022C) // (CAN_MB1) MailBox Family ID Register +// ========== Register definition for CAN_MB2 peripheral ========== +#define AT91C_CAN_MB2_MCR (0xFFFD025C) // (CAN_MB2) MailBox Control Register +#define AT91C_CAN_MB2_MDH (0xFFFD0258) // (CAN_MB2) MailBox Data High Register +#define AT91C_CAN_MB2_MID (0xFFFD0248) // (CAN_MB2) MailBox ID Register +#define AT91C_CAN_MB2_MDL (0xFFFD0254) // (CAN_MB2) MailBox Data Low Register +#define AT91C_CAN_MB2_MMR (0xFFFD0240) // (CAN_MB2) MailBox Mode Register +#define AT91C_CAN_MB2_MAM (0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register +#define AT91C_CAN_MB2_MFID (0xFFFD024C) // (CAN_MB2) MailBox Family ID Register +#define AT91C_CAN_MB2_MSR (0xFFFD0250) // (CAN_MB2) MailBox Status Register +// ========== Register definition for CAN_MB3 peripheral ========== +#define AT91C_CAN_MB3_MFID (0xFFFD026C) // (CAN_MB3) MailBox Family ID Register +#define AT91C_CAN_MB3_MAM (0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register +#define AT91C_CAN_MB3_MID (0xFFFD0268) // (CAN_MB3) MailBox ID Register +#define AT91C_CAN_MB3_MCR (0xFFFD027C) // (CAN_MB3) MailBox Control Register +#define AT91C_CAN_MB3_MMR (0xFFFD0260) // (CAN_MB3) MailBox Mode Register +#define AT91C_CAN_MB3_MSR (0xFFFD0270) // (CAN_MB3) MailBox Status Register +#define AT91C_CAN_MB3_MDL (0xFFFD0274) // (CAN_MB3) MailBox Data Low Register +#define AT91C_CAN_MB3_MDH (0xFFFD0278) // (CAN_MB3) MailBox Data High Register +// ========== Register definition for CAN_MB4 peripheral ========== +#define AT91C_CAN_MB4_MID (0xFFFD0288) // (CAN_MB4) MailBox ID Register +#define AT91C_CAN_MB4_MMR (0xFFFD0280) // (CAN_MB4) MailBox Mode Register +#define AT91C_CAN_MB4_MDH (0xFFFD0298) // (CAN_MB4) MailBox Data High Register +#define AT91C_CAN_MB4_MFID (0xFFFD028C) // (CAN_MB4) MailBox Family ID Register +#define AT91C_CAN_MB4_MSR (0xFFFD0290) // (CAN_MB4) MailBox Status Register +#define AT91C_CAN_MB4_MCR (0xFFFD029C) // (CAN_MB4) MailBox Control Register +#define AT91C_CAN_MB4_MDL (0xFFFD0294) // (CAN_MB4) MailBox Data Low Register +#define AT91C_CAN_MB4_MAM (0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB5 peripheral ========== +#define AT91C_CAN_MB5_MSR (0xFFFD02B0) // (CAN_MB5) MailBox Status Register +#define AT91C_CAN_MB5_MCR (0xFFFD02BC) // (CAN_MB5) MailBox Control Register +#define AT91C_CAN_MB5_MFID (0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register +#define AT91C_CAN_MB5_MDH (0xFFFD02B8) // (CAN_MB5) MailBox Data High Register +#define AT91C_CAN_MB5_MID (0xFFFD02A8) // (CAN_MB5) MailBox ID Register +#define AT91C_CAN_MB5_MMR (0xFFFD02A0) // (CAN_MB5) MailBox Mode Register +#define AT91C_CAN_MB5_MDL (0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register +#define AT91C_CAN_MB5_MAM (0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB6 peripheral ========== +#define AT91C_CAN_MB6_MFID (0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register +#define AT91C_CAN_MB6_MID (0xFFFD02C8) // (CAN_MB6) MailBox ID Register +#define AT91C_CAN_MB6_MAM (0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register +#define AT91C_CAN_MB6_MSR (0xFFFD02D0) // (CAN_MB6) MailBox Status Register +#define AT91C_CAN_MB6_MDL (0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register +#define AT91C_CAN_MB6_MCR (0xFFFD02DC) // (CAN_MB6) MailBox Control Register +#define AT91C_CAN_MB6_MDH (0xFFFD02D8) // (CAN_MB6) MailBox Data High Register +#define AT91C_CAN_MB6_MMR (0xFFFD02C0) // (CAN_MB6) MailBox Mode Register +// ========== Register definition for CAN_MB7 peripheral ========== +#define AT91C_CAN_MB7_MCR (0xFFFD02FC) // (CAN_MB7) MailBox Control Register +#define AT91C_CAN_MB7_MDH (0xFFFD02F8) // (CAN_MB7) MailBox Data High Register +#define AT91C_CAN_MB7_MFID (0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register +#define AT91C_CAN_MB7_MDL (0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register +#define AT91C_CAN_MB7_MID (0xFFFD02E8) // (CAN_MB7) MailBox ID Register +#define AT91C_CAN_MB7_MMR (0xFFFD02E0) // (CAN_MB7) MailBox Mode Register +#define AT91C_CAN_MB7_MAM (0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register +#define AT91C_CAN_MB7_MSR (0xFFFD02F0) // (CAN_MB7) MailBox Status Register +// ========== Register definition for CAN peripheral ========== +#define AT91C_CAN_TCR (0xFFFD0024) // (CAN) Transfer Command Register +#define AT91C_CAN_IMR (0xFFFD000C) // (CAN) Interrupt Mask Register +#define AT91C_CAN_IER (0xFFFD0004) // (CAN) Interrupt Enable Register +#define AT91C_CAN_ECR (0xFFFD0020) // (CAN) Error Counter Register +#define AT91C_CAN_TIMESTP (0xFFFD001C) // (CAN) Time Stamp Register +#define AT91C_CAN_MR (0xFFFD0000) // (CAN) Mode Register +#define AT91C_CAN_IDR (0xFFFD0008) // (CAN) Interrupt Disable Register +#define AT91C_CAN_ACR (0xFFFD0028) // (CAN) Abort Command Register +#define AT91C_CAN_TIM (0xFFFD0018) // (CAN) Timer Register +#define AT91C_CAN_SR (0xFFFD0010) // (CAN) Status Register +#define AT91C_CAN_BR (0xFFFD0014) // (CAN) Baudrate Register +#define AT91C_CAN_VR (0xFFFD00FC) // (CAN) Version Register +// ========== Register definition for EMAC peripheral ========== +#define AT91C_EMAC_ISR (0xFFFDC024) // (EMAC) Interrupt Status Register +#define AT91C_EMAC_SA4H (0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes +#define AT91C_EMAC_SA1L (0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes +#define AT91C_EMAC_ELE (0xFFFDC078) // (EMAC) Excessive Length Errors Register +#define AT91C_EMAC_LCOL (0xFFFDC05C) // (EMAC) Late Collision Register +#define AT91C_EMAC_RLE (0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register +#define AT91C_EMAC_WOL (0xFFFDC0C4) // (EMAC) Wake On LAN Register +#define AT91C_EMAC_DTF (0xFFFDC058) // (EMAC) Deferred Transmission Frame Register +#define AT91C_EMAC_TUND (0xFFFDC064) // (EMAC) Transmit Underrun Error Register +#define AT91C_EMAC_NCR (0xFFFDC000) // (EMAC) Network Control Register +#define AT91C_EMAC_SA4L (0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes +#define AT91C_EMAC_RSR (0xFFFDC020) // (EMAC) Receive Status Register +#define AT91C_EMAC_SA3L (0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes +#define AT91C_EMAC_TSR (0xFFFDC014) // (EMAC) Transmit Status Register +#define AT91C_EMAC_IDR (0xFFFDC02C) // (EMAC) Interrupt Disable Register +#define AT91C_EMAC_RSE (0xFFFDC074) // (EMAC) Receive Symbol Errors Register +#define AT91C_EMAC_ECOL (0xFFFDC060) // (EMAC) Excessive Collision Register +#define AT91C_EMAC_TID (0xFFFDC0B8) // (EMAC) Type ID Checking Register +#define AT91C_EMAC_HRB (0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] +#define AT91C_EMAC_TBQP (0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer +#define AT91C_EMAC_USRIO (0xFFFDC0C0) // (EMAC) USER Input/Output Register +#define AT91C_EMAC_PTR (0xFFFDC038) // (EMAC) Pause Time Register +#define AT91C_EMAC_SA2H (0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes +#define AT91C_EMAC_ROV (0xFFFDC070) // (EMAC) Receive Overrun Errors Register +#define AT91C_EMAC_ALE (0xFFFDC054) // (EMAC) Alignment Error Register +#define AT91C_EMAC_RJA (0xFFFDC07C) // (EMAC) Receive Jabbers Register +#define AT91C_EMAC_RBQP (0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer +#define AT91C_EMAC_TPF (0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register +#define AT91C_EMAC_NCFGR (0xFFFDC004) // (EMAC) Network Configuration Register +#define AT91C_EMAC_HRT (0xFFFDC094) // (EMAC) Hash Address Top[63:32] +#define AT91C_EMAC_USF (0xFFFDC080) // (EMAC) Undersize Frames Register +#define AT91C_EMAC_FCSE (0xFFFDC050) // (EMAC) Frame Check Sequence Error Register +#define AT91C_EMAC_TPQ (0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register +#define AT91C_EMAC_MAN (0xFFFDC034) // (EMAC) PHY Maintenance Register +#define AT91C_EMAC_FTO (0xFFFDC040) // (EMAC) Frames Transmitted OK Register +#define AT91C_EMAC_REV (0xFFFDC0FC) // (EMAC) Revision Register +#define AT91C_EMAC_IMR (0xFFFDC030) // (EMAC) Interrupt Mask Register +#define AT91C_EMAC_SCF (0xFFFDC044) // (EMAC) Single Collision Frame Register +#define AT91C_EMAC_PFR (0xFFFDC03C) // (EMAC) Pause Frames received Register +#define AT91C_EMAC_MCF (0xFFFDC048) // (EMAC) Multiple Collision Frame Register +#define AT91C_EMAC_NSR (0xFFFDC008) // (EMAC) Network Status Register +#define AT91C_EMAC_SA2L (0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes +#define AT91C_EMAC_FRO (0xFFFDC04C) // (EMAC) Frames Received OK Register +#define AT91C_EMAC_IER (0xFFFDC028) // (EMAC) Interrupt Enable Register +#define AT91C_EMAC_SA1H (0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes +#define AT91C_EMAC_CSE (0xFFFDC068) // (EMAC) Carrier Sense Error Register +#define AT91C_EMAC_SA3H (0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes +#define AT91C_EMAC_RRE (0xFFFDC06C) // (EMAC) Receive Ressource Error Register +#define AT91C_EMAC_STE (0xFFFDC084) // (EMAC) SQE Test Error Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTSR (0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_PTCR (0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR (0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_TNCR (0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNPR (0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_RNCR (0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_RPR (0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_TCR (0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_TPR (0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RCR (0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_CDR2 (0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR3 (0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR0 (0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR5 (0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_CHDR (0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_SR (0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CDR4 (0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR1 (0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_LCDR (0xFFFD8020) // (ADC) ADC Last Converted Data Register +#define AT91C_ADC_IDR (0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_CR (0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CDR7 (0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR6 (0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_IER (0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_CHER (0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR (0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_MR (0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_IMR (0xFFFD802C) // (ADC) ADC Interrupt Mask Register +// ========== Register definition for PDC_AES peripheral ========== +#define AT91C_AES_TPR (0xFFFA4108) // (PDC_AES) Transmit Pointer Register +#define AT91C_AES_PTCR (0xFFFA4120) // (PDC_AES) PDC Transfer Control Register +#define AT91C_AES_RNPR (0xFFFA4110) // (PDC_AES) Receive Next Pointer Register +#define AT91C_AES_TNCR (0xFFFA411C) // (PDC_AES) Transmit Next Counter Register +#define AT91C_AES_TCR (0xFFFA410C) // (PDC_AES) Transmit Counter Register +#define AT91C_AES_RCR (0xFFFA4104) // (PDC_AES) Receive Counter Register +#define AT91C_AES_RNCR (0xFFFA4114) // (PDC_AES) Receive Next Counter Register +#define AT91C_AES_TNPR (0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register +#define AT91C_AES_RPR (0xFFFA4100) // (PDC_AES) Receive Pointer Register +#define AT91C_AES_PTSR (0xFFFA4124) // (PDC_AES) PDC Transfer Status Register +// ========== Register definition for AES peripheral ========== +#define AT91C_AES_IVxR (0xFFFA4060) // (AES) Initialization Vector x Register +#define AT91C_AES_MR (0xFFFA4004) // (AES) Mode Register +#define AT91C_AES_VR (0xFFFA40FC) // (AES) AES Version Register +#define AT91C_AES_ODATAxR (0xFFFA4050) // (AES) Output Data x Register +#define AT91C_AES_IDATAxR (0xFFFA4040) // (AES) Input Data x Register +#define AT91C_AES_CR (0xFFFA4000) // (AES) Control Register +#define AT91C_AES_IDR (0xFFFA4014) // (AES) Interrupt Disable Register +#define AT91C_AES_IMR (0xFFFA4018) // (AES) Interrupt Mask Register +#define AT91C_AES_IER (0xFFFA4010) // (AES) Interrupt Enable Register +#define AT91C_AES_KEYWxR (0xFFFA4020) // (AES) Key Word x Register +#define AT91C_AES_ISR (0xFFFA401C) // (AES) Interrupt Status Register +// ========== Register definition for PDC_TDES peripheral ========== +#define AT91C_TDES_RNCR (0xFFFA8114) // (PDC_TDES) Receive Next Counter Register +#define AT91C_TDES_TCR (0xFFFA810C) // (PDC_TDES) Transmit Counter Register +#define AT91C_TDES_RCR (0xFFFA8104) // (PDC_TDES) Receive Counter Register +#define AT91C_TDES_TNPR (0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register +#define AT91C_TDES_RNPR (0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register +#define AT91C_TDES_RPR (0xFFFA8100) // (PDC_TDES) Receive Pointer Register +#define AT91C_TDES_TNCR (0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register +#define AT91C_TDES_TPR (0xFFFA8108) // (PDC_TDES) Transmit Pointer Register +#define AT91C_TDES_PTSR (0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register +#define AT91C_TDES_PTCR (0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register +// ========== Register definition for TDES peripheral ========== +#define AT91C_TDES_KEY2WxR (0xFFFA8028) // (TDES) Key 2 Word x Register +#define AT91C_TDES_KEY3WxR (0xFFFA8030) // (TDES) Key 3 Word x Register +#define AT91C_TDES_IDR (0xFFFA8014) // (TDES) Interrupt Disable Register +#define AT91C_TDES_VR (0xFFFA80FC) // (TDES) TDES Version Register +#define AT91C_TDES_IVxR (0xFFFA8060) // (TDES) Initialization Vector x Register +#define AT91C_TDES_ODATAxR (0xFFFA8050) // (TDES) Output Data x Register +#define AT91C_TDES_IMR (0xFFFA8018) // (TDES) Interrupt Mask Register +#define AT91C_TDES_MR (0xFFFA8004) // (TDES) Mode Register +#define AT91C_TDES_CR (0xFFFA8000) // (TDES) Control Register +#define AT91C_TDES_IER (0xFFFA8010) // (TDES) Interrupt Enable Register +#define AT91C_TDES_ISR (0xFFFA801C) // (TDES) Interrupt Status Register +#define AT91C_TDES_IDATAxR (0xFFFA8040) // (TDES) Input Data x Register +#define AT91C_TDES_KEY1WxR (0xFFFA8020) // (TDES) Key 1 Word x Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7X128 +// ***************************************************************************** +#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_RXD0 (AT91C_PIO_PA0) // USART 0 Receive Data +#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_TXD0 (AT91C_PIO_PA1) // USART 0 Transmit Data +#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_TWD (AT91C_PIO_PA10) // TWI Two-wire Serial Data +#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_TWCK (AT91C_PIO_PA11) // TWI Two-wire Serial Clock +#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_NPCS00 (AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 +#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_NPCS01 (AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PA13_PCK1 (AT91C_PIO_PA13) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_NPCS02 (AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PA14_IRQ1 (AT91C_PIO_PA14) // External Interrupt 1 +#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_NPCS03 (AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PA15_TCLK2 (AT91C_PIO_PA15) // Timer Counter 2 external clock input +#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_MISO0 (AT91C_PIO_PA16) // SPI 0 Master In Slave +#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_MOSI0 (AT91C_PIO_PA17) // SPI 0 Master Out Slave +#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_SPCK0 (AT91C_PIO_PA18) // SPI 0 Serial Clock +#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_CANRX (AT91C_PIO_PA19) // CAN Receive +#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PA2_NPCS11 (AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_CANTX (AT91C_PIO_PA20) // CAN Transmit +#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_TF (AT91C_PIO_PA21) // SSC Transmit Frame Sync +#define AT91C_PA21_NPCS10 (AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 +#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TK (AT91C_PIO_PA22) // SSC Transmit Clock +#define AT91C_PA22_SPCK1 (AT91C_PIO_PA22) // SPI 1 Serial Clock +#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_TD (AT91C_PIO_PA23) // SSC Transmit data +#define AT91C_PA23_MOSI1 (AT91C_PIO_PA23) // SPI 1 Master Out Slave +#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RD (AT91C_PIO_PA24) // SSC Receive Data +#define AT91C_PA24_MISO1 (AT91C_PIO_PA24) // SPI 1 Master In Slave +#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_RK (AT91C_PIO_PA25) // SSC Receive Clock +#define AT91C_PA25_NPCS11 (AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_RF (AT91C_PIO_PA26) // SSC Receive Frame Sync +#define AT91C_PA26_NPCS12 (AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DRXD (AT91C_PIO_PA27) // DBGU Debug Receive Data +#define AT91C_PA27_PCK3 (AT91C_PIO_PA27) // PMC Programmable Clock Output 3 +#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DTXD (AT91C_PIO_PA28) // DBGU Debug Transmit Data +#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_FIQ (AT91C_PIO_PA29) // AIC Fast Interrupt Input +#define AT91C_PA29_NPCS13 (AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_RTS0 (AT91C_PIO_PA3) // USART 0 Ready To Send +#define AT91C_PA3_NPCS12 (AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ0 (AT91C_PIO_PA30) // External Interrupt 0 +#define AT91C_PA30_PCK2 (AT91C_PIO_PA30) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_CTS0 (AT91C_PIO_PA4) // USART 0 Clear To Send +#define AT91C_PA4_NPCS13 (AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD1 (AT91C_PIO_PA5) // USART 1 Receive Data +#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD1 (AT91C_PIO_PA6) // USART 1 Transmit Data +#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_SCK1 (AT91C_PIO_PA7) // USART 1 Serial Clock +#define AT91C_PA7_NPCS01 (AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_RTS1 (AT91C_PIO_PA8) // USART 1 Ready To Send +#define AT91C_PA8_NPCS02 (AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_CTS1 (AT91C_PIO_PA9) // USART 1 Clear To Send +#define AT91C_PA9_NPCS03 (AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0 +#define AT91C_PB0_ETXCK_EREFCK (AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock +#define AT91C_PB0_PCK0 (AT91C_PIO_PB0) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1 +#define AT91C_PB1_ETXEN (AT91C_PIO_PB1) // Ethernet MAC Transmit Enable +#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10 +#define AT91C_PB10_ETX2 (AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 +#define AT91C_PB10_NPCS11 (AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11 +#define AT91C_PB11_ETX3 (AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 +#define AT91C_PB11_NPCS12 (AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12 +#define AT91C_PB12_ETXER (AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error +#define AT91C_PB12_TCLK0 (AT91C_PIO_PB12) // Timer Counter 0 external clock input +#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13 +#define AT91C_PB13_ERX2 (AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 +#define AT91C_PB13_NPCS01 (AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14 +#define AT91C_PB14_ERX3 (AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 +#define AT91C_PB14_NPCS02 (AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15 +#define AT91C_PB15_ERXDV (AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid +#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16 +#define AT91C_PB16_ECOL (AT91C_PIO_PB16) // Ethernet MAC Collision Detected +#define AT91C_PB16_NPCS13 (AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17 +#define AT91C_PB17_ERXCK (AT91C_PIO_PB17) // Ethernet MAC Receive Clock +#define AT91C_PB17_NPCS03 (AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18 +#define AT91C_PB18_EF100 (AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec +#define AT91C_PB18_ADTRG (AT91C_PIO_PB18) // ADC External Trigger +#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19 +#define AT91C_PB19_PWM0 (AT91C_PIO_PB19) // PWM Channel 0 +#define AT91C_PB19_TCLK1 (AT91C_PIO_PB19) // Timer Counter 1 external clock input +#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2 +#define AT91C_PB2_ETX0 (AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 +#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20 +#define AT91C_PB20_PWM1 (AT91C_PIO_PB20) // PWM Channel 1 +#define AT91C_PB20_PCK0 (AT91C_PIO_PB20) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21 +#define AT91C_PB21_PWM2 (AT91C_PIO_PB21) // PWM Channel 2 +#define AT91C_PB21_PCK1 (AT91C_PIO_PB21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22 +#define AT91C_PB22_PWM3 (AT91C_PIO_PB22) // PWM Channel 3 +#define AT91C_PB22_PCK2 (AT91C_PIO_PB22) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23 +#define AT91C_PB23_TIOA0 (AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PB23_DCD1 (AT91C_PIO_PB23) // USART 1 Data Carrier Detect +#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24 +#define AT91C_PB24_TIOB0 (AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PB24_DSR1 (AT91C_PIO_PB24) // USART 1 Data Set ready +#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25 +#define AT91C_PB25_TIOA1 (AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PB25_DTR1 (AT91C_PIO_PB25) // USART 1 Data Terminal ready +#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26 +#define AT91C_PB26_TIOB1 (AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PB26_RI1 (AT91C_PIO_PB26) // USART 1 Ring Indicator +#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27 +#define AT91C_PB27_TIOA2 (AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PB27_PWM0 (AT91C_PIO_PB27) // PWM Channel 0 +#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28 +#define AT91C_PB28_TIOB2 (AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PB28_PWM1 (AT91C_PIO_PB28) // PWM Channel 1 +#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29 +#define AT91C_PB29_PCK1 (AT91C_PIO_PB29) // PMC Programmable Clock Output 1 +#define AT91C_PB29_PWM2 (AT91C_PIO_PB29) // PWM Channel 2 +#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3 +#define AT91C_PB3_ETX1 (AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 +#define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30 +#define AT91C_PB30_PCK2 (AT91C_PIO_PB30) // PMC Programmable Clock Output 2 +#define AT91C_PB30_PWM3 (AT91C_PIO_PB30) // PWM Channel 3 +#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4 +#define AT91C_PB4_ECRS_ECRSDV (AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid +#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5 +#define AT91C_PB5_ERX0 (AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 +#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6 +#define AT91C_PB6_ERX1 (AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 +#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7 +#define AT91C_PB7_ERXER (AT91C_PIO_PB7) // Ethernet MAC Receive Error +#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8 +#define AT91C_PB8_EMDC (AT91C_PIO_PB8) // Ethernet MAC Management Data Clock +#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9 +#define AT91C_PB9_EMDIO (AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X128 +// ***************************************************************************** +#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ( 1) // System Peripheral +#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A +#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B +#define AT91C_ID_SPI0 ( 4) // Serial Peripheral Interface 0 +#define AT91C_ID_SPI1 ( 5) // Serial Peripheral Interface 1 +#define AT91C_ID_US0 ( 6) // USART 0 +#define AT91C_ID_US1 ( 7) // USART 1 +#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ( 9) // Two-Wire Interface +#define AT91C_ID_PWMC (10) // PWM Controller +#define AT91C_ID_UDP (11) // USB Device Port +#define AT91C_ID_TC0 (12) // Timer Counter 0 +#define AT91C_ID_TC1 (13) // Timer Counter 1 +#define AT91C_ID_TC2 (14) // Timer Counter 2 +#define AT91C_ID_CAN (15) // Control Area Network Controller +#define AT91C_ID_EMAC (16) // Ethernet MAC +#define AT91C_ID_ADC (17) // Analog-to-Digital Converter +#define AT91C_ID_AES (18) // Advanced Encryption Standard 128-bit +#define AT91C_ID_TDES (19) // Triple Data Encryption Standard +#define AT91C_ID_20_Reserved (20) // Reserved +#define AT91C_ID_21_Reserved (21) // Reserved +#define AT91C_ID_22_Reserved (22) // Reserved +#define AT91C_ID_23_Reserved (23) // Reserved +#define AT91C_ID_24_Reserved (24) // Reserved +#define AT91C_ID_25_Reserved (25) // Reserved +#define AT91C_ID_26_Reserved (26) // Reserved +#define AT91C_ID_27_Reserved (27) // Reserved +#define AT91C_ID_28_Reserved (28) // Reserved +#define AT91C_ID_29_Reserved (29) // Reserved +#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1) + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7X128 +// ***************************************************************************** +#define AT91C_BASE_SYS (0xFFFFF000) // (SYS) Base Address +#define AT91C_BASE_AIC (0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_PDC_DBGU (0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_DBGU (0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PIOA (0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_PIOB (0xFFFFF600) // (PIOB) Base Address +#define AT91C_BASE_CKGR (0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC (0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC (0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC (0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC (0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC (0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_VREG (0xFFFFFD60) // (VREG) Base Address +#define AT91C_BASE_MC (0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_PDC_SPI1 (0xFFFE4100) // (PDC_SPI1) Base Address +#define AT91C_BASE_SPI1 (0xFFFE4000) // (SPI1) Base Address +#define AT91C_BASE_PDC_SPI0 (0xFFFE0100) // (PDC_SPI0) Base Address +#define AT91C_BASE_SPI0 (0xFFFE0000) // (SPI0) Base Address +#define AT91C_BASE_PDC_US1 (0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 (0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 (0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_PDC_SSC (0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC (0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_TWI (0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_PWMC_CH3 (0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 (0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 (0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 (0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC (0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP (0xFFFB0000) // (UDP) Base Address +#define AT91C_BASE_TC0 (0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TC1 (0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC2 (0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TCB (0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_CAN_MB0 (0xFFFD0200) // (CAN_MB0) Base Address +#define AT91C_BASE_CAN_MB1 (0xFFFD0220) // (CAN_MB1) Base Address +#define AT91C_BASE_CAN_MB2 (0xFFFD0240) // (CAN_MB2) Base Address +#define AT91C_BASE_CAN_MB3 (0xFFFD0260) // (CAN_MB3) Base Address +#define AT91C_BASE_CAN_MB4 (0xFFFD0280) // (CAN_MB4) Base Address +#define AT91C_BASE_CAN_MB5 (0xFFFD02A0) // (CAN_MB5) Base Address +#define AT91C_BASE_CAN_MB6 (0xFFFD02C0) // (CAN_MB6) Base Address +#define AT91C_BASE_CAN_MB7 (0xFFFD02E0) // (CAN_MB7) Base Address +#define AT91C_BASE_CAN (0xFFFD0000) // (CAN) Base Address +#define AT91C_BASE_EMAC (0xFFFDC000) // (EMAC) Base Address +#define AT91C_BASE_PDC_ADC (0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC (0xFFFD8000) // (ADC) Base Address +#define AT91C_BASE_PDC_AES (0xFFFA4100) // (PDC_AES) Base Address +#define AT91C_BASE_AES (0xFFFA4000) // (AES) Base Address +#define AT91C_BASE_PDC_TDES (0xFFFA8100) // (PDC_TDES) Base Address +#define AT91C_BASE_TDES (0xFFFA8000) // (TDES) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X128 +// ***************************************************************************** +#define AT91C_ISRAM (0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE (0x00008000) // Internal SRAM size in byte (32 Kbyte) +#define AT91C_IFLASH (0x00100000) // Internal ROM base address +#define AT91C_IFLASH_SIZE (0x00020000) // Internal ROM size in byte (128 Kbyte) + + diff --git a/20080212/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256.h b/20080212/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256.h new file mode 100644 index 000000000..6b73f8a93 --- /dev/null +++ b/20080212/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256.h @@ -0,0 +1,2715 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM7X256.h +// Object : AT91SAM7X256 definitions +// Generated : AT91 SW Application Group 05/20/2005 (16:22:29) +// +// CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005// +// CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// +// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// +// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// +// CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// +// CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// +// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// +// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// +// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// +// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// +// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// +// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// +// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// +// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// +// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// +// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// +// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// +// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// +// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// +// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// +// CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// +// CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// +// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// +// CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// +// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// +// ---------------------------------------------------------------------------- + +#ifndef AT91SAM7X256_H +#define AT91SAM7X256_H + +typedef volatile unsigned int AT91_REG;// Hardware register definition + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** +typedef struct _AT91S_SYS { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register + AT91_REG Reserved2[45]; // + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved3[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved4[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register + AT91_REG Reserved5[54]; // + AT91_REG PIOA_PER; // PIO Enable Register + AT91_REG PIOA_PDR; // PIO Disable Register + AT91_REG PIOA_PSR; // PIO Status Register + AT91_REG Reserved6[1]; // + AT91_REG PIOA_OER; // Output Enable Register + AT91_REG PIOA_ODR; // Output Disable Registerr + AT91_REG PIOA_OSR; // Output Status Register + AT91_REG Reserved7[1]; // + AT91_REG PIOA_IFER; // Input Filter Enable Register + AT91_REG PIOA_IFDR; // Input Filter Disable Register + AT91_REG PIOA_IFSR; // Input Filter Status Register + AT91_REG Reserved8[1]; // + AT91_REG PIOA_SODR; // Set Output Data Register + AT91_REG PIOA_CODR; // Clear Output Data Register + AT91_REG PIOA_ODSR; // Output Data Status Register + AT91_REG PIOA_PDSR; // Pin Data Status Register + AT91_REG PIOA_IER; // Interrupt Enable Register + AT91_REG PIOA_IDR; // Interrupt Disable Register + AT91_REG PIOA_IMR; // Interrupt Mask Register + AT91_REG PIOA_ISR; // Interrupt Status Register + AT91_REG PIOA_MDER; // Multi-driver Enable Register + AT91_REG PIOA_MDDR; // Multi-driver Disable Register + AT91_REG PIOA_MDSR; // Multi-driver Status Register + AT91_REG Reserved9[1]; // + AT91_REG PIOA_PPUDR; // Pull-up Disable Register + AT91_REG PIOA_PPUER; // Pull-up Enable Register + AT91_REG PIOA_PPUSR; // Pull-up Status Register + AT91_REG Reserved10[1]; // + AT91_REG PIOA_ASR; // Select A Register + AT91_REG PIOA_BSR; // Select B Register + AT91_REG PIOA_ABSR; // AB Select Status Register + AT91_REG Reserved11[9]; // + AT91_REG PIOA_OWER; // Output Write Enable Register + AT91_REG PIOA_OWDR; // Output Write Disable Register + AT91_REG PIOA_OWSR; // Output Write Status Register + AT91_REG Reserved12[85]; // + AT91_REG PIOB_PER; // PIO Enable Register + AT91_REG PIOB_PDR; // PIO Disable Register + AT91_REG PIOB_PSR; // PIO Status Register + AT91_REG Reserved13[1]; // + AT91_REG PIOB_OER; // Output Enable Register + AT91_REG PIOB_ODR; // Output Disable Registerr + AT91_REG PIOB_OSR; // Output Status Register + AT91_REG Reserved14[1]; // + AT91_REG PIOB_IFER; // Input Filter Enable Register + AT91_REG PIOB_IFDR; // Input Filter Disable Register + AT91_REG PIOB_IFSR; // Input Filter Status Register + AT91_REG Reserved15[1]; // + AT91_REG PIOB_SODR; // Set Output Data Register + AT91_REG PIOB_CODR; // Clear Output Data Register + AT91_REG PIOB_ODSR; // Output Data Status Register + AT91_REG PIOB_PDSR; // Pin Data Status Register + AT91_REG PIOB_IER; // Interrupt Enable Register + AT91_REG PIOB_IDR; // Interrupt Disable Register + AT91_REG PIOB_IMR; // Interrupt Mask Register + AT91_REG PIOB_ISR; // Interrupt Status Register + AT91_REG PIOB_MDER; // Multi-driver Enable Register + AT91_REG PIOB_MDDR; // Multi-driver Disable Register + AT91_REG PIOB_MDSR; // Multi-driver Status Register + AT91_REG Reserved16[1]; // + AT91_REG PIOB_PPUDR; // Pull-up Disable Register + AT91_REG PIOB_PPUER; // Pull-up Enable Register + AT91_REG PIOB_PPUSR; // Pull-up Status Register + AT91_REG Reserved17[1]; // + AT91_REG PIOB_ASR; // Select A Register + AT91_REG PIOB_BSR; // Select B Register + AT91_REG PIOB_ABSR; // AB Select Status Register + AT91_REG Reserved18[9]; // + AT91_REG PIOB_OWER; // Output Write Enable Register + AT91_REG PIOB_OWDR; // Output Write Disable Register + AT91_REG PIOB_OWSR; // Output Write Status Register + AT91_REG Reserved19[341]; // + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved20[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved21[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved22[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved23[3]; // + AT91_REG PMC_PCKR[4]; // Programmable Clock Register + AT91_REG Reserved24[4]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register + AT91_REG Reserved25[36]; // + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register + AT91_REG Reserved26[5]; // + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register + AT91_REG Reserved27[5]; // + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_SYS, *AT91PS_SYS; + + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +typedef struct _AT91S_AIC { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register +} AT91S_AIC, *AT91PS_AIC; + +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// ***************************************************************************** +typedef struct _AT91S_PDC { + AT91_REG PDC_RPR; // Receive Pointer Register + AT91_REG PDC_RCR; // Receive Counter Register + AT91_REG PDC_TPR; // Transmit Pointer Register + AT91_REG PDC_TCR; // Transmit Counter Register + AT91_REG PDC_RNPR; // Receive Next Pointer Register + AT91_REG PDC_RNCR; // Receive Next Counter Register + AT91_REG PDC_TNPR; // Transmit Next Pointer Register + AT91_REG PDC_TNCR; // Transmit Next Counter Register + AT91_REG PDC_PTCR; // PDC Transfer Control Register + AT91_REG PDC_PTSR; // PDC Transfer Status Register +} AT91S_PDC, *AT91PS_PDC; + +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +typedef struct _AT91S_DBGU { + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved0[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved1[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register +} AT91S_DBGU, *AT91PS_DBGU; + +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable +#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +typedef struct _AT91S_PIO { + AT91_REG PIO_PER; // PIO Enable Register + AT91_REG PIO_PDR; // PIO Disable Register + AT91_REG PIO_PSR; // PIO Status Register + AT91_REG Reserved0[1]; // + AT91_REG PIO_OER; // Output Enable Register + AT91_REG PIO_ODR; // Output Disable Registerr + AT91_REG PIO_OSR; // Output Status Register + AT91_REG Reserved1[1]; // + AT91_REG PIO_IFER; // Input Filter Enable Register + AT91_REG PIO_IFDR; // Input Filter Disable Register + AT91_REG PIO_IFSR; // Input Filter Status Register + AT91_REG Reserved2[1]; // + AT91_REG PIO_SODR; // Set Output Data Register + AT91_REG PIO_CODR; // Clear Output Data Register + AT91_REG PIO_ODSR; // Output Data Status Register + AT91_REG PIO_PDSR; // Pin Data Status Register + AT91_REG PIO_IER; // Interrupt Enable Register + AT91_REG PIO_IDR; // Interrupt Disable Register + AT91_REG PIO_IMR; // Interrupt Mask Register + AT91_REG PIO_ISR; // Interrupt Status Register + AT91_REG PIO_MDER; // Multi-driver Enable Register + AT91_REG PIO_MDDR; // Multi-driver Disable Register + AT91_REG PIO_MDSR; // Multi-driver Status Register + AT91_REG Reserved3[1]; // + AT91_REG PIO_PPUDR; // Pull-up Disable Register + AT91_REG PIO_PPUER; // Pull-up Enable Register + AT91_REG PIO_PPUSR; // Pull-up Status Register + AT91_REG Reserved4[1]; // + AT91_REG PIO_ASR; // Select A Register + AT91_REG PIO_BSR; // Select B Register + AT91_REG PIO_ABSR; // AB Select Status Register + AT91_REG Reserved5[9]; // + AT91_REG PIO_OWER; // Output Write Enable Register + AT91_REG PIO_OWDR; // Output Write Disable Register + AT91_REG PIO_OWSR; // Output Write Status Register +} AT91S_PIO, *AT91PS_PIO; + + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +typedef struct _AT91S_CKGR { + AT91_REG CKGR_MOR; // Main Oscillator Register + AT91_REG CKGR_MCFR; // Main Clock Frequency Register + AT91_REG Reserved0[1]; // + AT91_REG CKGR_PLLR; // PLL Register +} AT91S_CKGR, *AT91PS_CKGR; + +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +typedef struct _AT91S_PMC { + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved0[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved1[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved2[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved3[3]; // + AT91_REG PMC_PCKR[4]; // Programmable Clock Register + AT91_REG Reserved4[4]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register +} AT91S_PMC, *AT91PS_PMC; + +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +typedef struct _AT91S_RSTC { + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register +} AT91S_RSTC, *AT91PS_RSTC; + +// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset +#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset +#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password +// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status +#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status +#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type +#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured. +#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level +#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable +#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_RTTC { + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register +} AT91S_RTTC, *AT91PS_RTTC; + +// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value +// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value +// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_PITC { + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register +} AT91S_PITC, *AT91PS_PITC; + +// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_WDTC { + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register +} AT91S_WDTC, *AT91PS_WDTC; + +// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart +#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password +// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface +// ***************************************************************************** +typedef struct _AT91S_VREG { + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_VREG, *AT91PS_VREG; + +// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- +#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +typedef struct _AT91S_MC { + AT91_REG MC_RCR; // MC Remap Control Register + AT91_REG MC_ASR; // MC Abort Status Register + AT91_REG MC_AASR; // MC Abort Address Status Register + AT91_REG Reserved0[21]; // + AT91_REG MC_FMR; // MC Flash Mode Register + AT91_REG MC_FCR; // MC Flash Command Register + AT91_REG MC_FSR; // MC Flash Status Register +} AT91S_MC, *AT91PS_MC; + +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready +#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error +#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error +#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming +#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State +#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number +// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command +#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit. +#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number +#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key +// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- +#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status +#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +typedef struct _AT91S_SPI { + AT91_REG SPI_CR; // Control Register + AT91_REG SPI_MR; // Mode Register + AT91_REG SPI_RDR; // Receive Data Register + AT91_REG SPI_TDR; // Transmit Data Register + AT91_REG SPI_SR; // Status Register + AT91_REG SPI_IER; // Interrupt Enable Register + AT91_REG SPI_IDR; // Interrupt Disable Register + AT91_REG SPI_IMR; // Interrupt Mask Register + AT91_REG Reserved0[4]; // + AT91_REG SPI_CSR[4]; // Chip Select Register + AT91_REG Reserved1[48]; // + AT91_REG SPI_RPR; // Receive Pointer Register + AT91_REG SPI_RCR; // Receive Counter Register + AT91_REG SPI_TPR; // Transmit Pointer Register + AT91_REG SPI_TCR; // Transmit Counter Register + AT91_REG SPI_RNPR; // Receive Next Pointer Register + AT91_REG SPI_RNCR; // Receive Next Counter Register + AT91_REG SPI_TNPR; // Transmit Next Pointer Register + AT91_REG SPI_TNCR; // Transmit Next Counter Register + AT91_REG SPI_PTCR; // PDC Transfer Control Register + AT91_REG SPI_PTSR; // PDC Transfer Status Register +} AT91S_SPI, *AT91PS_SPI; + +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK +#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +typedef struct _AT91S_USART { + AT91_REG US_CR; // Control Register + AT91_REG US_MR; // Mode Register + AT91_REG US_IER; // Interrupt Enable Register + AT91_REG US_IDR; // Interrupt Disable Register + AT91_REG US_IMR; // Interrupt Mask Register + AT91_REG US_CSR; // Channel Status Register + AT91_REG US_RHR; // Receiver Holding Register + AT91_REG US_THR; // Transmitter Holding Register + AT91_REG US_BRGR; // Baud Rate Generator Register + AT91_REG US_RTOR; // Receiver Time-out Register + AT91_REG US_TTGR; // Transmitter Time-guard Register + AT91_REG Reserved0[5]; // + AT91_REG US_FIDI; // FI_DI_Ratio Register + AT91_REG US_NER; // Nb Errors Register + AT91_REG Reserved1[1]; // + AT91_REG US_IF; // IRDA_FILTER Register + AT91_REG Reserved2[44]; // + AT91_REG US_RPR; // Receive Pointer Register + AT91_REG US_RCR; // Receive Counter Register + AT91_REG US_TPR; // Transmit Pointer Register + AT91_REG US_TCR; // Transmit Counter Register + AT91_REG US_RNPR; // Receive Next Pointer Register + AT91_REG US_RNCR; // Receive Next Counter Register + AT91_REG US_TNPR; // Transmit Next Pointer Register + AT91_REG US_TNCR; // Transmit Next Counter Register + AT91_REG US_PTCR; // PDC Transfer Control Register + AT91_REG US_PTSR; // PDC Transfer Status Register +} AT91S_USART, *AT91PS_USART; + +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +typedef struct _AT91S_SSC { + AT91_REG SSC_CR; // Control Register + AT91_REG SSC_CMR; // Clock Mode Register + AT91_REG Reserved0[2]; // + AT91_REG SSC_RCMR; // Receive Clock ModeRegister + AT91_REG SSC_RFMR; // Receive Frame Mode Register + AT91_REG SSC_TCMR; // Transmit Clock Mode Register + AT91_REG SSC_TFMR; // Transmit Frame Mode Register + AT91_REG SSC_RHR; // Receive Holding Register + AT91_REG SSC_THR; // Transmit Holding Register + AT91_REG Reserved1[2]; // + AT91_REG SSC_RSHR; // Receive Sync Holding Register + AT91_REG SSC_TSHR; // Transmit Sync Holding Register + AT91_REG Reserved2[2]; // + AT91_REG SSC_SR; // Status Register + AT91_REG SSC_IER; // Interrupt Enable Register + AT91_REG SSC_IDR; // Interrupt Disable Register + AT91_REG SSC_IMR; // Interrupt Mask Register + AT91_REG Reserved3[44]; // + AT91_REG SSC_RPR; // Receive Pointer Register + AT91_REG SSC_RCR; // Receive Counter Register + AT91_REG SSC_TPR; // Transmit Pointer Register + AT91_REG SSC_TCR; // Transmit Counter Register + AT91_REG SSC_RNPR; // Receive Next Pointer Register + AT91_REG SSC_RNCR; // Receive Next Counter Register + AT91_REG SSC_TNPR; // Transmit Next Pointer Register + AT91_REG SSC_TNCR; // Transmit Next Counter Register + AT91_REG SSC_PTCR; // PDC Transfer Control Register + AT91_REG SSC_PTSR; // PDC Transfer Status Register +} AT91S_SSC, *AT91PS_SSC; + +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin +#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +typedef struct _AT91S_TWI { + AT91_REG TWI_CR; // Control Register + AT91_REG TWI_MMR; // Master Mode Register + AT91_REG Reserved0[1]; // + AT91_REG TWI_IADR; // Internal Address Register + AT91_REG TWI_CWGR; // Clock Waveform Generator Register + AT91_REG Reserved1[3]; // + AT91_REG TWI_SR; // Status Register + AT91_REG TWI_IER; // Interrupt Enable Register + AT91_REG TWI_IDR; // Interrupt Disable Register + AT91_REG TWI_IMR; // Interrupt Mask Register + AT91_REG TWI_RHR; // Receive Holding Register + AT91_REG TWI_THR; // Transmit Holding Register +} AT91S_TWI, *AT91PS_TWI; + +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +typedef struct _AT91S_PWMC_CH { + AT91_REG PWMC_CMR; // Channel Mode Register + AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register + AT91_REG PWMC_CPRDR; // Channel Period Register + AT91_REG PWMC_CCNTR; // Channel Counter Register + AT91_REG PWMC_CUPDR; // Channel Update Register + AT91_REG PWMC_Reserved[3]; // Reserved +} AT91S_PWMC_CH, *AT91PS_PWMC_CH; + +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +typedef struct _AT91S_PWMC { + AT91_REG PWMC_MR; // PWMC Mode Register + AT91_REG PWMC_ENA; // PWMC Enable Register + AT91_REG PWMC_DIS; // PWMC Disable Register + AT91_REG PWMC_SR; // PWMC Status Register + AT91_REG PWMC_IER; // PWMC Interrupt Enable Register + AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register + AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register + AT91_REG PWMC_ISR; // PWMC Interrupt Status Register + AT91_REG Reserved0[55]; // + AT91_REG PWMC_VR; // PWMC Version Register + AT91_REG Reserved1[64]; // + AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel +} AT91S_PWMC, *AT91PS_PWMC; + +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +typedef struct _AT91S_UDP { + AT91_REG UDP_NUM; // Frame Number Register + AT91_REG UDP_GLBSTATE; // Global State Register + AT91_REG UDP_FADDR; // Function Address Register + AT91_REG Reserved0[1]; // + AT91_REG UDP_IER; // Interrupt Enable Register + AT91_REG UDP_IDR; // Interrupt Disable Register + AT91_REG UDP_IMR; // Interrupt Mask Register + AT91_REG UDP_ISR; // Interrupt Status Register + AT91_REG UDP_ICR; // Interrupt Clear Register + AT91_REG Reserved1[1]; // + AT91_REG UDP_RSTEP; // Reset Endpoint Register + AT91_REG Reserved2[1]; // + AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register + AT91_REG Reserved3[2]; // + AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register + AT91_REG Reserved4[3]; // + AT91_REG UDP_TXVC; // Transceiver Control Register +} AT91S_UDP, *AT91PS_UDP; + +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured +#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume +#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt +#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt +#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3 +#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4 +#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO +// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP) +#define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +typedef struct _AT91S_TC { + AT91_REG TC_CCR; // Channel Control Register + AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) + AT91_REG Reserved0[2]; // + AT91_REG TC_CV; // Counter Value + AT91_REG TC_RA; // Register A + AT91_REG TC_RB; // Register B + AT91_REG TC_RC; // Register C + AT91_REG TC_SR; // Status Register + AT91_REG TC_IER; // Interrupt Enable Register + AT91_REG TC_IDR; // Interrupt Disable Register + AT91_REG TC_IMR; // Interrupt Mask Register +} AT91S_TC, *AT91PS_TC; + +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) +#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger +#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +typedef struct _AT91S_TCB { + AT91S_TC TCB_TC0; // TC Channel 0 + AT91_REG Reserved0[4]; // + AT91S_TC TCB_TC1; // TC Channel 1 + AT91_REG Reserved1[4]; // + AT91S_TC TCB_TC2; // TC Channel 2 + AT91_REG Reserved2[4]; // + AT91_REG TCB_BCR; // TC Block Control Register + AT91_REG TCB_BMR; // TC Block Mode Register +} AT91S_TCB, *AT91PS_TCB; + +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface +// ***************************************************************************** +typedef struct _AT91S_CAN_MB { + AT91_REG CAN_MB_MMR; // MailBox Mode Register + AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register + AT91_REG CAN_MB_MID; // MailBox ID Register + AT91_REG CAN_MB_MFID; // MailBox Family ID Register + AT91_REG CAN_MB_MSR; // MailBox Status Register + AT91_REG CAN_MB_MDL; // MailBox Data Low Register + AT91_REG CAN_MB_MDH; // MailBox Data High Register + AT91_REG CAN_MB_MCR; // MailBox Control Register +} AT91S_CAN_MB, *AT91PS_CAN_MB; + +// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- +#define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark +#define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority +#define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type +#define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB) +// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- +#define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode +#define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode +#define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version +// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- +// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- +// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- +#define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value +#define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code +#define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request +#define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort +#define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready +#define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored +// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- +// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- +// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- +#define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox +#define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network Interface +// ***************************************************************************** +typedef struct _AT91S_CAN { + AT91_REG CAN_MR; // Mode Register + AT91_REG CAN_IER; // Interrupt Enable Register + AT91_REG CAN_IDR; // Interrupt Disable Register + AT91_REG CAN_IMR; // Interrupt Mask Register + AT91_REG CAN_SR; // Status Register + AT91_REG CAN_BR; // Baudrate Register + AT91_REG CAN_TIM; // Timer Register + AT91_REG CAN_TIMESTP; // Time Stamp Register + AT91_REG CAN_ECR; // Error Counter Register + AT91_REG CAN_TCR; // Transfer Command Register + AT91_REG CAN_ACR; // Abort Command Register + AT91_REG Reserved0[52]; // + AT91_REG CAN_VR; // Version Register + AT91_REG Reserved1[64]; // + AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0 + AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1 + AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2 + AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3 + AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4 + AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5 + AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6 + AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7 + AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8 + AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9 + AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10 + AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11 + AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12 + AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13 + AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14 + AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15 +} AT91S_CAN, *AT91PS_CAN; + +// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- +#define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable +#define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode +#define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode +#define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame +#define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame +#define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode +#define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze +#define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat +// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- +#define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag +#define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag +#define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag +#define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag +#define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag +#define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag +#define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag +#define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag +#define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag +#define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag +#define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag +#define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag +#define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag +#define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag +#define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag +#define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag +#define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag +#define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag +#define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag +#define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag +#define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag +#define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag +#define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag +#define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag +#define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error +#define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error +#define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error +#define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error +#define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error +// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- +// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- +// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- +#define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy +#define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy +#define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy +// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- +#define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment +#define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment +#define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment +#define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment +#define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler +#define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode +// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- +#define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field +// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- +// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- +#define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter +#define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter +// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- +#define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field +// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 +// ***************************************************************************** +typedef struct _AT91S_EMAC { + AT91_REG EMAC_NCR; // Network Control Register + AT91_REG EMAC_NCFGR; // Network Configuration Register + AT91_REG EMAC_NSR; // Network Status Register + AT91_REG Reserved0[2]; // + AT91_REG EMAC_TSR; // Transmit Status Register + AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer + AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer + AT91_REG EMAC_RSR; // Receive Status Register + AT91_REG EMAC_ISR; // Interrupt Status Register + AT91_REG EMAC_IER; // Interrupt Enable Register + AT91_REG EMAC_IDR; // Interrupt Disable Register + AT91_REG EMAC_IMR; // Interrupt Mask Register + AT91_REG EMAC_MAN; // PHY Maintenance Register + AT91_REG EMAC_PTR; // Pause Time Register + AT91_REG EMAC_PFR; // Pause Frames received Register + AT91_REG EMAC_FTO; // Frames Transmitted OK Register + AT91_REG EMAC_SCF; // Single Collision Frame Register + AT91_REG EMAC_MCF; // Multiple Collision Frame Register + AT91_REG EMAC_FRO; // Frames Received OK Register + AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register + AT91_REG EMAC_ALE; // Alignment Error Register + AT91_REG EMAC_DTF; // Deferred Transmission Frame Register + AT91_REG EMAC_LCOL; // Late Collision Register + AT91_REG EMAC_ECOL; // Excessive Collision Register + AT91_REG EMAC_TUND; // Transmit Underrun Error Register + AT91_REG EMAC_CSE; // Carrier Sense Error Register + AT91_REG EMAC_RRE; // Receive Ressource Error Register + AT91_REG EMAC_ROV; // Receive Overrun Errors Register + AT91_REG EMAC_RSE; // Receive Symbol Errors Register + AT91_REG EMAC_ELE; // Excessive Length Errors Register + AT91_REG EMAC_RJA; // Receive Jabbers Register + AT91_REG EMAC_USF; // Undersize Frames Register + AT91_REG EMAC_STE; // SQE Test Error Register + AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register + AT91_REG EMAC_TPF; // Transmitted Pause Frames Register + AT91_REG EMAC_HRB; // Hash Address Bottom[31:0] + AT91_REG EMAC_HRT; // Hash Address Top[63:32] + AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes + AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes + AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes + AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes + AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes + AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes + AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes + AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes + AT91_REG EMAC_TID; // Type ID Checking Register + AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register + AT91_REG EMAC_USRIO; // USER Input/Output Register + AT91_REG EMAC_WOL; // Wake On LAN Register + AT91_REG Reserved1[13]; // + AT91_REG EMAC_REV; // Revision Register +} AT91S_EMAC, *AT91PS_EMAC; + +// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- +#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. +#define AT91C_EMAC_LLB ((unsigned int) 0x1 << 1) // (EMAC) Loopback local. +#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable. +#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable. +#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable. +#define AT91C_EMAC_CLRSTAT ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers. +#define AT91C_EMAC_INCSTAT ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers. +#define AT91C_EMAC_WESTAT ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers. +#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure. +#define AT91C_EMAC_TSTART ((unsigned int) 0x1 << 9) // (EMAC) Start Transmission. +#define AT91C_EMAC_THALT ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. +#define AT91C_EMAC_TPFR ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame +#define AT91C_EMAC_TZQ ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame +// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- +#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed. +#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex. +#define AT91C_EMAC_JFRAME ((unsigned int) 0x1 << 3) // (EMAC) Jumbo Frames. +#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames. +#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast. +#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash event enable +#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable. +#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes. +#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable. +#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC) +#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8 +#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16 +#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32 +#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64 +#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC) +#define AT91C_EMAC_PAE ((unsigned int) 0x1 << 13) // (EMAC) +#define AT91C_EMAC_RBOF ((unsigned int) 0x3 << 14) // (EMAC) +#define AT91C_EMAC_RBOF_OFFSET_0 ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_1 ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_2 ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_3 ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer +#define AT91C_EMAC_RLCE ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable +#define AT91C_EMAC_DRFCS ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS +#define AT91C_EMAC_EFRHD ((unsigned int) 0x1 << 18) // (EMAC) +#define AT91C_EMAC_IRXFCS ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS +// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- +#define AT91C_EMAC_LINKR ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC) +// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- +#define AT91C_EMAC_UBR ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_RLES ((unsigned int) 0x1 << 2) // (EMAC) +#define AT91C_EMAC_TGO ((unsigned int) 0x1 << 3) // (EMAC) Transmit Go +#define AT91C_EMAC_BEX ((unsigned int) 0x1 << 4) // (EMAC) Buffers exhausted mid frame +#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC) +#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC) +// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- +#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 2) // (EMAC) +// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- +#define AT91C_EMAC_MFD ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_RCOMP ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_RXUBR ((unsigned int) 0x1 << 2) // (EMAC) +#define AT91C_EMAC_TXUBR ((unsigned int) 0x1 << 3) // (EMAC) +#define AT91C_EMAC_TUNDR ((unsigned int) 0x1 << 4) // (EMAC) +#define AT91C_EMAC_RLEX ((unsigned int) 0x1 << 5) // (EMAC) +#define AT91C_EMAC_TXERR ((unsigned int) 0x1 << 6) // (EMAC) +#define AT91C_EMAC_TCOMP ((unsigned int) 0x1 << 7) // (EMAC) +#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC) +#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC) +#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC) +#define AT91C_EMAC_PFRE ((unsigned int) 0x1 << 12) // (EMAC) +#define AT91C_EMAC_PTZ ((unsigned int) 0x1 << 13) // (EMAC) +// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- +// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- +// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- +// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- +#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC) +#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC) +#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC) +#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC) +#define AT91C_EMAC_SOF ((unsigned int) 0x3 << 30) // (EMAC) +// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- +#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 0) // (EMAC) Reduce MII +// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- +#define AT91C_EMAC_IP ((unsigned int) 0xFFFF << 0) // (EMAC) ARP request IP address +#define AT91C_EMAC_MAG ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable +#define AT91C_EMAC_ARP ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable +#define AT91C_EMAC_SA1 ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable +// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- +#define AT91C_EMAC_REVREF ((unsigned int) 0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_PARTREF ((unsigned int) 0xFFFF << 16) // (EMAC) + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +typedef struct _AT91S_ADC { + AT91_REG ADC_CR; // ADC Control Register + AT91_REG ADC_MR; // ADC Mode Register + AT91_REG Reserved0[2]; // + AT91_REG ADC_CHER; // ADC Channel Enable Register + AT91_REG ADC_CHDR; // ADC Channel Disable Register + AT91_REG ADC_CHSR; // ADC Channel Status Register + AT91_REG ADC_SR; // ADC Status Register + AT91_REG ADC_LCDR; // ADC Last Converted Data Register + AT91_REG ADC_IER; // ADC Interrupt Enable Register + AT91_REG ADC_IDR; // ADC Interrupt Disable Register + AT91_REG ADC_IMR; // ADC Interrupt Mask Register + AT91_REG ADC_CDR0; // ADC Channel Data Register 0 + AT91_REG ADC_CDR1; // ADC Channel Data Register 1 + AT91_REG ADC_CDR2; // ADC Channel Data Register 2 + AT91_REG ADC_CDR3; // ADC Channel Data Register 3 + AT91_REG ADC_CDR4; // ADC Channel Data Register 4 + AT91_REG ADC_CDR5; // ADC Channel Data Register 5 + AT91_REG ADC_CDR6; // ADC Channel Data Register 6 + AT91_REG ADC_CDR7; // ADC Channel Data Register 7 + AT91_REG Reserved1[44]; // + AT91_REG ADC_RPR; // Receive Pointer Register + AT91_REG ADC_RCR; // Receive Counter Register + AT91_REG ADC_TPR; // Transmit Pointer Register + AT91_REG ADC_TCR; // Transmit Counter Register + AT91_REG ADC_RNPR; // Receive Next Pointer Register + AT91_REG ADC_RNCR; // Receive Next Counter Register + AT91_REG ADC_TNPR; // Transmit Next Pointer Register + AT91_REG ADC_TNCR; // Transmit Next Counter Register + AT91_REG ADC_PTCR; // PDC Transfer Control Register + AT91_REG ADC_PTSR; // PDC Transfer Status Register +} AT91S_ADC, *AT91PS_ADC; + +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Encryption Standard +// ***************************************************************************** +typedef struct _AT91S_AES { + AT91_REG AES_CR; // Control Register + AT91_REG AES_MR; // Mode Register + AT91_REG Reserved0[2]; // + AT91_REG AES_IER; // Interrupt Enable Register + AT91_REG AES_IDR; // Interrupt Disable Register + AT91_REG AES_IMR; // Interrupt Mask Register + AT91_REG AES_ISR; // Interrupt Status Register + AT91_REG AES_KEYWxR[4]; // Key Word x Register + AT91_REG Reserved1[4]; // + AT91_REG AES_IDATAxR[4]; // Input Data x Register + AT91_REG AES_ODATAxR[4]; // Output Data x Register + AT91_REG AES_IVxR[4]; // Initialization Vector x Register + AT91_REG Reserved2[35]; // + AT91_REG AES_VR; // AES Version Register + AT91_REG AES_RPR; // Receive Pointer Register + AT91_REG AES_RCR; // Receive Counter Register + AT91_REG AES_TPR; // Transmit Pointer Register + AT91_REG AES_TCR; // Transmit Counter Register + AT91_REG AES_RNPR; // Receive Next Pointer Register + AT91_REG AES_RNCR; // Receive Next Counter Register + AT91_REG AES_TNPR; // Transmit Next Pointer Register + AT91_REG AES_TNCR; // Transmit Next Counter Register + AT91_REG AES_PTCR; // PDC Transfer Control Register + AT91_REG AES_PTSR; // PDC Transfer Status Register +} AT91S_AES, *AT91PS_AES; + +// -------- AES_CR : (AES Offset: 0x0) Control Register -------- +#define AT91C_AES_START ((unsigned int) 0x1 << 0) // (AES) Starts Processing +#define AT91C_AES_SWRST ((unsigned int) 0x1 << 8) // (AES) Software Reset +#define AT91C_AES_LOADSEED ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading +// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- +#define AT91C_AES_CIPHER ((unsigned int) 0x1 << 0) // (AES) Processing Mode +#define AT91C_AES_PROCDLY ((unsigned int) 0xF << 4) // (AES) Processing Delay +#define AT91C_AES_SMOD ((unsigned int) 0x3 << 8) // (AES) Start Mode +#define AT91C_AES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. +#define AT91C_AES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). +#define AT91C_AES_SMOD_PDC ((unsigned int) 0x2 << 8) // (AES) PDC Mode (cf datasheet). +#define AT91C_AES_OPMOD ((unsigned int) 0x7 << 12) // (AES) Operation Mode +#define AT91C_AES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode. +#define AT91C_AES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode. +#define AT91C_AES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode. +#define AT91C_AES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode. +#define AT91C_AES_OPMOD_CTR ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode. +#define AT91C_AES_LOD ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode +#define AT91C_AES_CFBS ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size +#define AT91C_AES_CFBS_128_BIT ((unsigned int) 0x0 << 16) // (AES) 128-bit. +#define AT91C_AES_CFBS_64_BIT ((unsigned int) 0x1 << 16) // (AES) 64-bit. +#define AT91C_AES_CFBS_32_BIT ((unsigned int) 0x2 << 16) // (AES) 32-bit. +#define AT91C_AES_CFBS_16_BIT ((unsigned int) 0x3 << 16) // (AES) 16-bit. +#define AT91C_AES_CFBS_8_BIT ((unsigned int) 0x4 << 16) // (AES) 8-bit. +#define AT91C_AES_CKEY ((unsigned int) 0xF << 20) // (AES) Countermeasure Key +#define AT91C_AES_CTYPE ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type +#define AT91C_AES_CTYPE_TYPE1_EN ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled. +#define AT91C_AES_CTYPE_TYPE2_EN ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled. +#define AT91C_AES_CTYPE_TYPE3_EN ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled. +#define AT91C_AES_CTYPE_TYPE4_EN ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled. +#define AT91C_AES_CTYPE_TYPE5_EN ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled. +// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- +#define AT91C_AES_DATRDY ((unsigned int) 0x1 << 0) // (AES) DATRDY +#define AT91C_AES_ENDRX ((unsigned int) 0x1 << 1) // (AES) PDC Read Buffer End +#define AT91C_AES_ENDTX ((unsigned int) 0x1 << 2) // (AES) PDC Write Buffer End +#define AT91C_AES_RXBUFF ((unsigned int) 0x1 << 3) // (AES) PDC Read Buffer Full +#define AT91C_AES_TXBUFE ((unsigned int) 0x1 << 4) // (AES) PDC Write Buffer Empty +#define AT91C_AES_URAD ((unsigned int) 0x1 << 8) // (AES) Unspecified Register Access Detection +// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- +// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- +// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- +#define AT91C_AES_URAT ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status +#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode. +#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing. +#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing. +#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation. +#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation. +#define AT91C_AES_URAT_WO_REG_READ ((unsigned int) 0x5 << 12) // (AES) Write-only register read access. + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard +// ***************************************************************************** +typedef struct _AT91S_TDES { + AT91_REG TDES_CR; // Control Register + AT91_REG TDES_MR; // Mode Register + AT91_REG Reserved0[2]; // + AT91_REG TDES_IER; // Interrupt Enable Register + AT91_REG TDES_IDR; // Interrupt Disable Register + AT91_REG TDES_IMR; // Interrupt Mask Register + AT91_REG TDES_ISR; // Interrupt Status Register + AT91_REG TDES_KEY1WxR[2]; // Key 1 Word x Register + AT91_REG TDES_KEY2WxR[2]; // Key 2 Word x Register + AT91_REG TDES_KEY3WxR[2]; // Key 3 Word x Register + AT91_REG Reserved1[2]; // + AT91_REG TDES_IDATAxR[2]; // Input Data x Register + AT91_REG Reserved2[2]; // + AT91_REG TDES_ODATAxR[2]; // Output Data x Register + AT91_REG Reserved3[2]; // + AT91_REG TDES_IVxR[2]; // Initialization Vector x Register + AT91_REG Reserved4[37]; // + AT91_REG TDES_VR; // TDES Version Register + AT91_REG TDES_RPR; // Receive Pointer Register + AT91_REG TDES_RCR; // Receive Counter Register + AT91_REG TDES_TPR; // Transmit Pointer Register + AT91_REG TDES_TCR; // Transmit Counter Register + AT91_REG TDES_RNPR; // Receive Next Pointer Register + AT91_REG TDES_RNCR; // Receive Next Counter Register + AT91_REG TDES_TNPR; // Transmit Next Pointer Register + AT91_REG TDES_TNCR; // Transmit Next Counter Register + AT91_REG TDES_PTCR; // PDC Transfer Control Register + AT91_REG TDES_PTSR; // PDC Transfer Status Register +} AT91S_TDES, *AT91PS_TDES; + +// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- +#define AT91C_TDES_START ((unsigned int) 0x1 << 0) // (TDES) Starts Processing +#define AT91C_TDES_SWRST ((unsigned int) 0x1 << 8) // (TDES) Software Reset +// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- +#define AT91C_TDES_CIPHER ((unsigned int) 0x1 << 0) // (TDES) Processing Mode +#define AT91C_TDES_TDESMOD ((unsigned int) 0x1 << 1) // (TDES) Single or Triple DES Mode +#define AT91C_TDES_KEYMOD ((unsigned int) 0x1 << 4) // (TDES) Key Mode +#define AT91C_TDES_SMOD ((unsigned int) 0x3 << 8) // (TDES) Start Mode +#define AT91C_TDES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. +#define AT91C_TDES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). +#define AT91C_TDES_SMOD_PDC ((unsigned int) 0x2 << 8) // (TDES) PDC Mode (cf datasheet). +#define AT91C_TDES_OPMOD ((unsigned int) 0x3 << 12) // (TDES) Operation Mode +#define AT91C_TDES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode. +#define AT91C_TDES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode. +#define AT91C_TDES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode. +#define AT91C_TDES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode. +#define AT91C_TDES_LOD ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode +#define AT91C_TDES_CFBS ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size +#define AT91C_TDES_CFBS_64_BIT ((unsigned int) 0x0 << 16) // (TDES) 64-bit. +#define AT91C_TDES_CFBS_32_BIT ((unsigned int) 0x1 << 16) // (TDES) 32-bit. +#define AT91C_TDES_CFBS_16_BIT ((unsigned int) 0x2 << 16) // (TDES) 16-bit. +#define AT91C_TDES_CFBS_8_BIT ((unsigned int) 0x3 << 16) // (TDES) 8-bit. +// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- +#define AT91C_TDES_DATRDY ((unsigned int) 0x1 << 0) // (TDES) DATRDY +#define AT91C_TDES_ENDRX ((unsigned int) 0x1 << 1) // (TDES) PDC Read Buffer End +#define AT91C_TDES_ENDTX ((unsigned int) 0x1 << 2) // (TDES) PDC Write Buffer End +#define AT91C_TDES_RXBUFF ((unsigned int) 0x1 << 3) // (TDES) PDC Read Buffer Full +#define AT91C_TDES_TXBUFE ((unsigned int) 0x1 << 4) // (TDES) PDC Write Buffer Empty +#define AT91C_TDES_URAD ((unsigned int) 0x1 << 8) // (TDES) Unspecified Register Access Detection +// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- +// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- +// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- +#define AT91C_TDES_URAT ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status +#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode. +#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing. +#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing. +#define AT91C_TDES_URAT_WO_REG_READ ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access. + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 +// ***************************************************************************** +// ========== Register definition for SYS peripheral ========== +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register +#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register +#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register +#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register +#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register +// ========== Register definition for PIOB peripheral ========== +#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register +#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register +#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register +#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register +#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register +#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register +#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register +#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register +#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register +#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register +#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register +#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register +#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register +#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register +#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register +#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register +#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr +#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register +#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register +#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register +#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register +#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register +#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register +#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register +#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register +#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register +#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register +#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register +#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register +#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register +#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register +#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register +#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register +#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register +// ========== Register definition for VREG peripheral ========== +#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register +#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register +#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register +#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register +// ========== Register definition for PDC_SPI1 peripheral ========== +#define AT91C_SPI1_PTCR ((AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register +#define AT91C_SPI1_RPR ((AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register +#define AT91C_SPI1_TNCR ((AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register +#define AT91C_SPI1_TPR ((AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register +#define AT91C_SPI1_TNPR ((AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register +#define AT91C_SPI1_TCR ((AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register +#define AT91C_SPI1_RCR ((AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register +#define AT91C_SPI1_RNPR ((AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register +#define AT91C_SPI1_RNCR ((AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register +#define AT91C_SPI1_PTSR ((AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register +// ========== Register definition for SPI1 peripheral ========== +#define AT91C_SPI1_IMR ((AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register +#define AT91C_SPI1_IER ((AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register +#define AT91C_SPI1_MR ((AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register +#define AT91C_SPI1_RDR ((AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register +#define AT91C_SPI1_IDR ((AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register +#define AT91C_SPI1_SR ((AT91_REG *) 0xFFFE4010) // (SPI1) Status Register +#define AT91C_SPI1_TDR ((AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register +#define AT91C_SPI1_CR ((AT91_REG *) 0xFFFE4000) // (SPI1) Control Register +#define AT91C_SPI1_CSR ((AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register +// ========== Register definition for PDC_SPI0 peripheral ========== +#define AT91C_SPI0_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register +#define AT91C_SPI0_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register +#define AT91C_SPI0_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register +#define AT91C_SPI0_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register +#define AT91C_SPI0_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register +#define AT91C_SPI0_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register +#define AT91C_SPI0_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register +#define AT91C_SPI0_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register +#define AT91C_SPI0_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register +#define AT91C_SPI0_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register +// ========== Register definition for SPI0 peripheral ========== +#define AT91C_SPI0_IER ((AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register +#define AT91C_SPI0_SR ((AT91_REG *) 0xFFFE0010) // (SPI0) Status Register +#define AT91C_SPI0_IDR ((AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register +#define AT91C_SPI0_CR ((AT91_REG *) 0xFFFE0000) // (SPI0) Control Register +#define AT91C_SPI0_MR ((AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register +#define AT91C_SPI0_IMR ((AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register +#define AT91C_SPI0_TDR ((AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register +#define AT91C_SPI0_RDR ((AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register +#define AT91C_SPI0_CSR ((AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register +#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register +#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register +#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register +#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register +#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register +#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register +#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register +#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register +#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register +#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register +#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register +#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for CAN_MB0 peripheral ========== +#define AT91C_CAN_MB0_MDL ((AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register +#define AT91C_CAN_MB0_MAM ((AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register +#define AT91C_CAN_MB0_MCR ((AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register +#define AT91C_CAN_MB0_MID ((AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register +#define AT91C_CAN_MB0_MSR ((AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register +#define AT91C_CAN_MB0_MFID ((AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register +#define AT91C_CAN_MB0_MDH ((AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register +#define AT91C_CAN_MB0_MMR ((AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register +// ========== Register definition for CAN_MB1 peripheral ========== +#define AT91C_CAN_MB1_MDL ((AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register +#define AT91C_CAN_MB1_MID ((AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register +#define AT91C_CAN_MB1_MMR ((AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register +#define AT91C_CAN_MB1_MSR ((AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register +#define AT91C_CAN_MB1_MAM ((AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register +#define AT91C_CAN_MB1_MDH ((AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register +#define AT91C_CAN_MB1_MCR ((AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register +#define AT91C_CAN_MB1_MFID ((AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register +// ========== Register definition for CAN_MB2 peripheral ========== +#define AT91C_CAN_MB2_MCR ((AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register +#define AT91C_CAN_MB2_MDH ((AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register +#define AT91C_CAN_MB2_MID ((AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register +#define AT91C_CAN_MB2_MDL ((AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register +#define AT91C_CAN_MB2_MMR ((AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register +#define AT91C_CAN_MB2_MAM ((AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register +#define AT91C_CAN_MB2_MFID ((AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register +#define AT91C_CAN_MB2_MSR ((AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register +// ========== Register definition for CAN_MB3 peripheral ========== +#define AT91C_CAN_MB3_MFID ((AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register +#define AT91C_CAN_MB3_MAM ((AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register +#define AT91C_CAN_MB3_MID ((AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register +#define AT91C_CAN_MB3_MCR ((AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register +#define AT91C_CAN_MB3_MMR ((AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register +#define AT91C_CAN_MB3_MSR ((AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register +#define AT91C_CAN_MB3_MDL ((AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register +#define AT91C_CAN_MB3_MDH ((AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register +// ========== Register definition for CAN_MB4 peripheral ========== +#define AT91C_CAN_MB4_MID ((AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register +#define AT91C_CAN_MB4_MMR ((AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register +#define AT91C_CAN_MB4_MDH ((AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register +#define AT91C_CAN_MB4_MFID ((AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register +#define AT91C_CAN_MB4_MSR ((AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register +#define AT91C_CAN_MB4_MCR ((AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register +#define AT91C_CAN_MB4_MDL ((AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register +#define AT91C_CAN_MB4_MAM ((AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB5 peripheral ========== +#define AT91C_CAN_MB5_MSR ((AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register +#define AT91C_CAN_MB5_MCR ((AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register +#define AT91C_CAN_MB5_MFID ((AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register +#define AT91C_CAN_MB5_MDH ((AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register +#define AT91C_CAN_MB5_MID ((AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register +#define AT91C_CAN_MB5_MMR ((AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register +#define AT91C_CAN_MB5_MDL ((AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register +#define AT91C_CAN_MB5_MAM ((AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB6 peripheral ========== +#define AT91C_CAN_MB6_MFID ((AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register +#define AT91C_CAN_MB6_MID ((AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register +#define AT91C_CAN_MB6_MAM ((AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register +#define AT91C_CAN_MB6_MSR ((AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register +#define AT91C_CAN_MB6_MDL ((AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register +#define AT91C_CAN_MB6_MCR ((AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register +#define AT91C_CAN_MB6_MDH ((AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register +#define AT91C_CAN_MB6_MMR ((AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register +// ========== Register definition for CAN_MB7 peripheral ========== +#define AT91C_CAN_MB7_MCR ((AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register +#define AT91C_CAN_MB7_MDH ((AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register +#define AT91C_CAN_MB7_MFID ((AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register +#define AT91C_CAN_MB7_MDL ((AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register +#define AT91C_CAN_MB7_MID ((AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register +#define AT91C_CAN_MB7_MMR ((AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register +#define AT91C_CAN_MB7_MAM ((AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register +#define AT91C_CAN_MB7_MSR ((AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register +// ========== Register definition for CAN peripheral ========== +#define AT91C_CAN_TCR ((AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register +#define AT91C_CAN_IMR ((AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register +#define AT91C_CAN_IER ((AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register +#define AT91C_CAN_ECR ((AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register +#define AT91C_CAN_TIMESTP ((AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register +#define AT91C_CAN_MR ((AT91_REG *) 0xFFFD0000) // (CAN) Mode Register +#define AT91C_CAN_IDR ((AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register +#define AT91C_CAN_ACR ((AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register +#define AT91C_CAN_TIM ((AT91_REG *) 0xFFFD0018) // (CAN) Timer Register +#define AT91C_CAN_SR ((AT91_REG *) 0xFFFD0010) // (CAN) Status Register +#define AT91C_CAN_BR ((AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register +#define AT91C_CAN_VR ((AT91_REG *) 0xFFFD00FC) // (CAN) Version Register +// ========== Register definition for EMAC peripheral ========== +#define AT91C_EMAC_ISR ((AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register +#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes +#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes +#define AT91C_EMAC_ELE ((AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register +#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register +#define AT91C_EMAC_RLE ((AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register +#define AT91C_EMAC_WOL ((AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register +#define AT91C_EMAC_DTF ((AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register +#define AT91C_EMAC_TUND ((AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register +#define AT91C_EMAC_NCR ((AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register +#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes +#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register +#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes +#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register +#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register +#define AT91C_EMAC_RSE ((AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register +#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register +#define AT91C_EMAC_TID ((AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register +#define AT91C_EMAC_HRB ((AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] +#define AT91C_EMAC_TBQP ((AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer +#define AT91C_EMAC_USRIO ((AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register +#define AT91C_EMAC_PTR ((AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register +#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes +#define AT91C_EMAC_ROV ((AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register +#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register +#define AT91C_EMAC_RJA ((AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register +#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer +#define AT91C_EMAC_TPF ((AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register +#define AT91C_EMAC_NCFGR ((AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register +#define AT91C_EMAC_HRT ((AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32] +#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register +#define AT91C_EMAC_FCSE ((AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register +#define AT91C_EMAC_TPQ ((AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register +#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register +#define AT91C_EMAC_FTO ((AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register +#define AT91C_EMAC_REV ((AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register +#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register +#define AT91C_EMAC_SCF ((AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register +#define AT91C_EMAC_PFR ((AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register +#define AT91C_EMAC_MCF ((AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register +#define AT91C_EMAC_NSR ((AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register +#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes +#define AT91C_EMAC_FRO ((AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register +#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register +#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes +#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register +#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes +#define AT91C_EMAC_RRE ((AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register +#define AT91C_EMAC_STE ((AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register +#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register +// ========== Register definition for PDC_AES peripheral ========== +#define AT91C_AES_TPR ((AT91_REG *) 0xFFFA4108) // (PDC_AES) Transmit Pointer Register +#define AT91C_AES_PTCR ((AT91_REG *) 0xFFFA4120) // (PDC_AES) PDC Transfer Control Register +#define AT91C_AES_RNPR ((AT91_REG *) 0xFFFA4110) // (PDC_AES) Receive Next Pointer Register +#define AT91C_AES_TNCR ((AT91_REG *) 0xFFFA411C) // (PDC_AES) Transmit Next Counter Register +#define AT91C_AES_TCR ((AT91_REG *) 0xFFFA410C) // (PDC_AES) Transmit Counter Register +#define AT91C_AES_RCR ((AT91_REG *) 0xFFFA4104) // (PDC_AES) Receive Counter Register +#define AT91C_AES_RNCR ((AT91_REG *) 0xFFFA4114) // (PDC_AES) Receive Next Counter Register +#define AT91C_AES_TNPR ((AT91_REG *) 0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register +#define AT91C_AES_RPR ((AT91_REG *) 0xFFFA4100) // (PDC_AES) Receive Pointer Register +#define AT91C_AES_PTSR ((AT91_REG *) 0xFFFA4124) // (PDC_AES) PDC Transfer Status Register +// ========== Register definition for AES peripheral ========== +#define AT91C_AES_IVxR ((AT91_REG *) 0xFFFA4060) // (AES) Initialization Vector x Register +#define AT91C_AES_MR ((AT91_REG *) 0xFFFA4004) // (AES) Mode Register +#define AT91C_AES_VR ((AT91_REG *) 0xFFFA40FC) // (AES) AES Version Register +#define AT91C_AES_ODATAxR ((AT91_REG *) 0xFFFA4050) // (AES) Output Data x Register +#define AT91C_AES_IDATAxR ((AT91_REG *) 0xFFFA4040) // (AES) Input Data x Register +#define AT91C_AES_CR ((AT91_REG *) 0xFFFA4000) // (AES) Control Register +#define AT91C_AES_IDR ((AT91_REG *) 0xFFFA4014) // (AES) Interrupt Disable Register +#define AT91C_AES_IMR ((AT91_REG *) 0xFFFA4018) // (AES) Interrupt Mask Register +#define AT91C_AES_IER ((AT91_REG *) 0xFFFA4010) // (AES) Interrupt Enable Register +#define AT91C_AES_KEYWxR ((AT91_REG *) 0xFFFA4020) // (AES) Key Word x Register +#define AT91C_AES_ISR ((AT91_REG *) 0xFFFA401C) // (AES) Interrupt Status Register +// ========== Register definition for PDC_TDES peripheral ========== +#define AT91C_TDES_RNCR ((AT91_REG *) 0xFFFA8114) // (PDC_TDES) Receive Next Counter Register +#define AT91C_TDES_TCR ((AT91_REG *) 0xFFFA810C) // (PDC_TDES) Transmit Counter Register +#define AT91C_TDES_RCR ((AT91_REG *) 0xFFFA8104) // (PDC_TDES) Receive Counter Register +#define AT91C_TDES_TNPR ((AT91_REG *) 0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register +#define AT91C_TDES_RNPR ((AT91_REG *) 0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register +#define AT91C_TDES_RPR ((AT91_REG *) 0xFFFA8100) // (PDC_TDES) Receive Pointer Register +#define AT91C_TDES_TNCR ((AT91_REG *) 0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register +#define AT91C_TDES_TPR ((AT91_REG *) 0xFFFA8108) // (PDC_TDES) Transmit Pointer Register +#define AT91C_TDES_PTSR ((AT91_REG *) 0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register +#define AT91C_TDES_PTCR ((AT91_REG *) 0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register +// ========== Register definition for TDES peripheral ========== +#define AT91C_TDES_KEY2WxR ((AT91_REG *) 0xFFFA8028) // (TDES) Key 2 Word x Register +#define AT91C_TDES_KEY3WxR ((AT91_REG *) 0xFFFA8030) // (TDES) Key 3 Word x Register +#define AT91C_TDES_IDR ((AT91_REG *) 0xFFFA8014) // (TDES) Interrupt Disable Register +#define AT91C_TDES_VR ((AT91_REG *) 0xFFFA80FC) // (TDES) TDES Version Register +#define AT91C_TDES_IVxR ((AT91_REG *) 0xFFFA8060) // (TDES) Initialization Vector x Register +#define AT91C_TDES_ODATAxR ((AT91_REG *) 0xFFFA8050) // (TDES) Output Data x Register +#define AT91C_TDES_IMR ((AT91_REG *) 0xFFFA8018) // (TDES) Interrupt Mask Register +#define AT91C_TDES_MR ((AT91_REG *) 0xFFFA8004) // (TDES) Mode Register +#define AT91C_TDES_CR ((AT91_REG *) 0xFFFA8000) // (TDES) Control Register +#define AT91C_TDES_IER ((AT91_REG *) 0xFFFA8010) // (TDES) Interrupt Enable Register +#define AT91C_TDES_ISR ((AT91_REG *) 0xFFFA801C) // (TDES) Interrupt Status Register +#define AT91C_TDES_IDATAxR ((AT91_REG *) 0xFFFA8040) // (TDES) Input Data x Register +#define AT91C_TDES_KEY1WxR ((AT91_REG *) 0xFFFA8020) // (TDES) Key 1 Word x Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data +#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data +#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data +#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock +#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_NPCS00 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 +#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_NPCS01 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_NPCS02 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1 +#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_NPCS03 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input +#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_MISO0 ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave +#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_MOSI0 ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave +#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_SPCK0 ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock +#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive +#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PA2_NPCS11 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit +#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync +#define AT91C_PA21_NPCS10 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 +#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock +#define AT91C_PA22_SPCK1 ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock +#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data +#define AT91C_PA23_MOSI1 ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave +#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data +#define AT91C_PA24_MISO1 ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave +#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock +#define AT91C_PA25_NPCS11 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync +#define AT91C_PA26_NPCS12 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data +#define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3 +#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data +#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input +#define AT91C_PA29_NPCS13 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send +#define AT91C_PA3_NPCS12 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0 +#define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send +#define AT91C_PA4_NPCS13 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data +#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data +#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock +#define AT91C_PA7_NPCS01 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send +#define AT91C_PA8_NPCS02 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send +#define AT91C_PA9_NPCS03 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0 +#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock +#define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1 +#define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable +#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10 +#define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 +#define AT91C_PB10_NPCS11 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11 +#define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 +#define AT91C_PB11_NPCS12 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12 +#define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error +#define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input +#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13 +#define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 +#define AT91C_PB13_NPCS01 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14 +#define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 +#define AT91C_PB14_NPCS02 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15 +#define AT91C_PB15_ERXDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid +#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16 +#define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected +#define AT91C_PB16_NPCS13 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17 +#define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock +#define AT91C_PB17_NPCS03 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18 +#define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec +#define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger +#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19 +#define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0 +#define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input +#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2 +#define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 +#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20 +#define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1 +#define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21 +#define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2 +#define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22 +#define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3 +#define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23 +#define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect +#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24 +#define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready +#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25 +#define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready +#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26 +#define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator +#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27 +#define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0 +#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28 +#define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1 +#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29 +#define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1 +#define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2 +#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3 +#define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 +#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30 +#define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2 +#define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3 +#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4 +#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid +#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5 +#define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 +#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6 +#define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 +#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7 +#define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error +#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8 +#define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock +#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9 +#define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral +#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A +#define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B +#define AT91C_ID_SPI0 ((unsigned int) 4) // Serial Peripheral Interface 0 +#define AT91C_ID_SPI1 ((unsigned int) 5) // Serial Peripheral Interface 1 +#define AT91C_ID_US0 ((unsigned int) 6) // USART 0 +#define AT91C_ID_US1 ((unsigned int) 7) // USART 1 +#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface +#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller +#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port +#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0 +#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1 +#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2 +#define AT91C_ID_CAN ((unsigned int) 15) // Control Area Network Controller +#define AT91C_ID_EMAC ((unsigned int) 16) // Ethernet MAC +#define AT91C_ID_ADC ((unsigned int) 17) // Analog-to-Digital Converter +#define AT91C_ID_AES ((unsigned int) 18) // Advanced Encryption Standard 128-bit +#define AT91C_ID_TDES ((unsigned int) 19) // Triple Data Encryption Standard +#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved +#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved +#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved +#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved +#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved +#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved +#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved +#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved +#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved +#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved +#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1) + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address +#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address +#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address +#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address +#define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address +#define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address +#define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address +#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address +#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_CAN_MB0 ((AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address +#define AT91C_BASE_CAN_MB1 ((AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address +#define AT91C_BASE_CAN_MB2 ((AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address +#define AT91C_BASE_CAN_MB3 ((AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address +#define AT91C_BASE_CAN_MB4 ((AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address +#define AT91C_BASE_CAN_MB5 ((AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address +#define AT91C_BASE_CAN_MB6 ((AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address +#define AT91C_BASE_CAN_MB7 ((AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address +#define AT91C_BASE_CAN ((AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address +#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address +#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address +#define AT91C_BASE_PDC_AES ((AT91PS_PDC) 0xFFFA4100) // (PDC_AES) Base Address +#define AT91C_BASE_AES ((AT91PS_AES) 0xFFFA4000) // (AES) Base Address +#define AT91C_BASE_PDC_TDES ((AT91PS_PDC) 0xFFFA8100) // (PDC_TDES) Base Address +#define AT91C_BASE_TDES ((AT91PS_TDES) 0xFFFA8000) // (TDES) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte) +#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address +#define AT91C_IFLASH_SIZE ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte) + +#endif diff --git a/20080212/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h b/20080212/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h new file mode 100644 index 000000000..5b8dfe811 --- /dev/null +++ b/20080212/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h @@ -0,0 +1,2446 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM7X256.h +// Object : AT91SAM7X256 definitions +// Generated : AT91 SW Application Group 05/20/2005 (16:22:29) +// +// CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005// +// CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// +// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// +// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// +// CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// +// CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// +// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// +// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// +// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// +// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// +// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// +// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// +// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// +// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// +// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// +// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// +// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// +// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// +// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// +// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// +// CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// +// CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// +// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// +// CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// +// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// +// ---------------------------------------------------------------------------- + +// Hardware register definition + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +// *** Register offset in AT91S_AIC structure *** +#define AIC_SMR ( 0) // Source Mode Register +#define AIC_SVR (128) // Source Vector Register +#define AIC_IVR (256) // IRQ Vector Register +#define AIC_FVR (260) // FIQ Vector Register +#define AIC_ISR (264) // Interrupt Status Register +#define AIC_IPR (268) // Interrupt Pending Register +#define AIC_IMR (272) // Interrupt Mask Register +#define AIC_CISR (276) // Core Interrupt Status Register +#define AIC_IECR (288) // Interrupt Enable Command Register +#define AIC_IDCR (292) // Interrupt Disable Command Register +#define AIC_ICCR (296) // Interrupt Clear Command Register +#define AIC_ISCR (300) // Interrupt Set Command Register +#define AIC_EOICR (304) // End of Interrupt Command Register +#define AIC_SPU (308) // Spurious Vector Register +#define AIC_DCR (312) // Debug Control Register (Protect) +#define AIC_FFER (320) // Fast Forcing Enable Register +#define AIC_FFDR (324) // Fast Forcing Disable Register +#define AIC_FFSR (328) // Fast Forcing Status Register +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// ***************************************************************************** +// *** Register offset in AT91S_PDC structure *** +#define PDC_RPR ( 0) // Receive Pointer Register +#define PDC_RCR ( 4) // Receive Counter Register +#define PDC_TPR ( 8) // Transmit Pointer Register +#define PDC_TCR (12) // Transmit Counter Register +#define PDC_RNPR (16) // Receive Next Pointer Register +#define PDC_RNCR (20) // Receive Next Counter Register +#define PDC_TNPR (24) // Transmit Next Pointer Register +#define PDC_TNCR (28) // Transmit Next Counter Register +#define PDC_PTCR (32) // PDC Transfer Control Register +#define PDC_PTSR (36) // PDC Transfer Status Register +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +// *** Register offset in AT91S_DBGU structure *** +#define DBGU_CR ( 0) // Control Register +#define DBGU_MR ( 4) // Mode Register +#define DBGU_IER ( 8) // Interrupt Enable Register +#define DBGU_IDR (12) // Interrupt Disable Register +#define DBGU_IMR (16) // Interrupt Mask Register +#define DBGU_CSR (20) // Channel Status Register +#define DBGU_RHR (24) // Receiver Holding Register +#define DBGU_THR (28) // Transmitter Holding Register +#define DBGU_BRGR (32) // Baud Rate Generator Register +#define DBGU_CIDR (64) // Chip ID Register +#define DBGU_EXID (68) // Chip ID Extension Register +#define DBGU_FNTR (72) // Force NTRST Register +#define DBGU_RPR (256) // Receive Pointer Register +#define DBGU_RCR (260) // Receive Counter Register +#define DBGU_TPR (264) // Transmit Pointer Register +#define DBGU_TCR (268) // Transmit Counter Register +#define DBGU_RNPR (272) // Receive Next Pointer Register +#define DBGU_RNCR (276) // Receive Next Counter Register +#define DBGU_TNPR (280) // Transmit Next Pointer Register +#define DBGU_TNCR (284) // Transmit Next Counter Register +#define DBGU_PTCR (288) // PDC Transfer Control Register +#define DBGU_PTSR (292) // PDC Transfer Status Register +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable +#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +// *** Register offset in AT91S_PIO structure *** +#define PIO_PER ( 0) // PIO Enable Register +#define PIO_PDR ( 4) // PIO Disable Register +#define PIO_PSR ( 8) // PIO Status Register +#define PIO_OER (16) // Output Enable Register +#define PIO_ODR (20) // Output Disable Registerr +#define PIO_OSR (24) // Output Status Register +#define PIO_IFER (32) // Input Filter Enable Register +#define PIO_IFDR (36) // Input Filter Disable Register +#define PIO_IFSR (40) // Input Filter Status Register +#define PIO_SODR (48) // Set Output Data Register +#define PIO_CODR (52) // Clear Output Data Register +#define PIO_ODSR (56) // Output Data Status Register +#define PIO_PDSR (60) // Pin Data Status Register +#define PIO_IER (64) // Interrupt Enable Register +#define PIO_IDR (68) // Interrupt Disable Register +#define PIO_IMR (72) // Interrupt Mask Register +#define PIO_ISR (76) // Interrupt Status Register +#define PIO_MDER (80) // Multi-driver Enable Register +#define PIO_MDDR (84) // Multi-driver Disable Register +#define PIO_MDSR (88) // Multi-driver Status Register +#define PIO_PPUDR (96) // Pull-up Disable Register +#define PIO_PPUER (100) // Pull-up Enable Register +#define PIO_PPUSR (104) // Pull-up Status Register +#define PIO_ASR (112) // Select A Register +#define PIO_BSR (116) // Select B Register +#define PIO_ABSR (120) // AB Select Status Register +#define PIO_OWER (160) // Output Write Enable Register +#define PIO_OWDR (164) // Output Write Disable Register +#define PIO_OWSR (168) // Output Write Status Register + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +// *** Register offset in AT91S_CKGR structure *** +#define CKGR_MOR ( 0) // Main Oscillator Register +#define CKGR_MCFR ( 4) // Main Clock Frequency Register +#define CKGR_PLLR (12) // PLL Register +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +// *** Register offset in AT91S_PMC structure *** +#define PMC_SCER ( 0) // System Clock Enable Register +#define PMC_SCDR ( 4) // System Clock Disable Register +#define PMC_SCSR ( 8) // System Clock Status Register +#define PMC_PCER (16) // Peripheral Clock Enable Register +#define PMC_PCDR (20) // Peripheral Clock Disable Register +#define PMC_PCSR (24) // Peripheral Clock Status Register +#define PMC_MOR (32) // Main Oscillator Register +#define PMC_MCFR (36) // Main Clock Frequency Register +#define PMC_PLLR (44) // PLL Register +#define PMC_MCKR (48) // Master Clock Register +#define PMC_PCKR (64) // Programmable Clock Register +#define PMC_IER (96) // Interrupt Enable Register +#define PMC_IDR (100) // Interrupt Disable Register +#define PMC_SR (104) // Status Register +#define PMC_IMR (108) // Interrupt Mask Register +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_RSTC structure *** +#define RSTC_RCR ( 0) // Reset Control Register +#define RSTC_RSR ( 4) // Reset Status Register +#define RSTC_RMR ( 8) // Reset Mode Register +// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset +#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset +#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password +// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status +#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status +#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type +#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured. +#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level +#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Enable +#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_RTTC structure *** +#define RTTC_RTMR ( 0) // Real-time Mode Register +#define RTTC_RTAR ( 4) // Real-time Alarm Register +#define RTTC_RTVR ( 8) // Real-time Value Register +#define RTTC_RTSR (12) // Real-time Status Register +// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value +// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value +// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_PITC structure *** +#define PITC_PIMR ( 0) // Period Interval Mode Register +#define PITC_PISR ( 4) // Period Interval Status Register +#define PITC_PIVR ( 8) // Period Interval Value Register +#define PITC_PIIR (12) // Period Interval Image Register +// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_WDTC structure *** +#define WDTC_WDCR ( 0) // Watchdog Control Register +#define WDTC_WDMR ( 4) // Watchdog Mode Register +#define WDTC_WDSR ( 8) // Watchdog Status Register +// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart +#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password +// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_VREG structure *** +#define VREG_MR ( 0) // Voltage Regulator Mode Register +// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- +#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_MC structure *** +#define MC_RCR ( 0) // MC Remap Control Register +#define MC_ASR ( 4) // MC Abort Status Register +#define MC_AASR ( 8) // MC Abort Address Status Register +#define MC_FMR (96) // MC Flash Mode Register +#define MC_FCR (100) // MC Flash Command Register +#define MC_FSR (104) // MC Flash Status Register +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready +#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error +#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error +#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming +#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State +#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number +// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command +#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit. +#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number +#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key +// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- +#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status +#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +// *** Register offset in AT91S_SPI structure *** +#define SPI_CR ( 0) // Control Register +#define SPI_MR ( 4) // Mode Register +#define SPI_RDR ( 8) // Receive Data Register +#define SPI_TDR (12) // Transmit Data Register +#define SPI_SR (16) // Status Register +#define SPI_IER (20) // Interrupt Enable Register +#define SPI_IDR (24) // Interrupt Disable Register +#define SPI_IMR (28) // Interrupt Mask Register +#define SPI_CSR (48) // Chip Select Register +#define SPI_RPR (256) // Receive Pointer Register +#define SPI_RCR (260) // Receive Counter Register +#define SPI_TPR (264) // Transmit Pointer Register +#define SPI_TCR (268) // Transmit Counter Register +#define SPI_RNPR (272) // Receive Next Pointer Register +#define SPI_RNCR (276) // Receive Next Counter Register +#define SPI_TNPR (280) // Transmit Next Pointer Register +#define SPI_TNCR (284) // Transmit Next Counter Register +#define SPI_PTCR (288) // PDC Transfer Control Register +#define SPI_PTSR (292) // PDC Transfer Status Register +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK +#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +// *** Register offset in AT91S_USART structure *** +#define US_CR ( 0) // Control Register +#define US_MR ( 4) // Mode Register +#define US_IER ( 8) // Interrupt Enable Register +#define US_IDR (12) // Interrupt Disable Register +#define US_IMR (16) // Interrupt Mask Register +#define US_CSR (20) // Channel Status Register +#define US_RHR (24) // Receiver Holding Register +#define US_THR (28) // Transmitter Holding Register +#define US_BRGR (32) // Baud Rate Generator Register +#define US_RTOR (36) // Receiver Time-out Register +#define US_TTGR (40) // Transmitter Time-guard Register +#define US_FIDI (64) // FI_DI_Ratio Register +#define US_NER (68) // Nb Errors Register +#define US_IF (76) // IRDA_FILTER Register +#define US_RPR (256) // Receive Pointer Register +#define US_RCR (260) // Receive Counter Register +#define US_TPR (264) // Transmit Pointer Register +#define US_TCR (268) // Transmit Counter Register +#define US_RNPR (272) // Receive Next Pointer Register +#define US_RNCR (276) // Receive Next Counter Register +#define US_TNPR (280) // Transmit Next Pointer Register +#define US_TNCR (284) // Transmit Next Counter Register +#define US_PTCR (288) // PDC Transfer Control Register +#define US_PTSR (292) // PDC Transfer Status Register +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_SSC structure *** +#define SSC_CR ( 0) // Control Register +#define SSC_CMR ( 4) // Clock Mode Register +#define SSC_RCMR (16) // Receive Clock ModeRegister +#define SSC_RFMR (20) // Receive Frame Mode Register +#define SSC_TCMR (24) // Transmit Clock Mode Register +#define SSC_TFMR (28) // Transmit Frame Mode Register +#define SSC_RHR (32) // Receive Holding Register +#define SSC_THR (36) // Transmit Holding Register +#define SSC_RSHR (48) // Receive Sync Holding Register +#define SSC_TSHR (52) // Transmit Sync Holding Register +#define SSC_SR (64) // Status Register +#define SSC_IER (68) // Interrupt Enable Register +#define SSC_IDR (72) // Interrupt Disable Register +#define SSC_IMR (76) // Interrupt Mask Register +#define SSC_RPR (256) // Receive Pointer Register +#define SSC_RCR (260) // Receive Counter Register +#define SSC_TPR (264) // Transmit Pointer Register +#define SSC_TCR (268) // Transmit Counter Register +#define SSC_RNPR (272) // Receive Next Pointer Register +#define SSC_RNCR (276) // Receive Next Counter Register +#define SSC_TNPR (280) // Transmit Next Pointer Register +#define SSC_TNCR (284) // Transmit Next Counter Register +#define SSC_PTCR (288) // PDC Transfer Control Register +#define SSC_PTSR (292) // PDC Transfer Status Register +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin +#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +// *** Register offset in AT91S_TWI structure *** +#define TWI_CR ( 0) // Control Register +#define TWI_MMR ( 4) // Master Mode Register +#define TWI_IADR (12) // Internal Address Register +#define TWI_CWGR (16) // Clock Waveform Generator Register +#define TWI_SR (32) // Status Register +#define TWI_IER (36) // Interrupt Enable Register +#define TWI_IDR (40) // Interrupt Disable Register +#define TWI_IMR (44) // Interrupt Mask Register +#define TWI_RHR (48) // Receive Holding Register +#define TWI_THR (52) // Transmit Holding Register +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +// *** Register offset in AT91S_PWMC_CH structure *** +#define PWMC_CMR ( 0) // Channel Mode Register +#define PWMC_CDTYR ( 4) // Channel Duty Cycle Register +#define PWMC_CPRDR ( 8) // Channel Period Register +#define PWMC_CCNTR (12) // Channel Counter Register +#define PWMC_CUPDR (16) // Channel Update Register +#define PWMC_Reserved (20) // Reserved +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_PWMC structure *** +#define PWMC_MR ( 0) // PWMC Mode Register +#define PWMC_ENA ( 4) // PWMC Enable Register +#define PWMC_DIS ( 8) // PWMC Disable Register +#define PWMC_SR (12) // PWMC Status Register +#define PWMC_IER (16) // PWMC Interrupt Enable Register +#define PWMC_IDR (20) // PWMC Interrupt Disable Register +#define PWMC_IMR (24) // PWMC Interrupt Mask Register +#define PWMC_ISR (28) // PWMC Interrupt Status Register +#define PWMC_VR (252) // PWMC Version Register +#define PWMC_CH (512) // PWMC Channel +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +// *** Register offset in AT91S_UDP structure *** +#define UDP_NUM ( 0) // Frame Number Register +#define UDP_GLBSTATE ( 4) // Global State Register +#define UDP_FADDR ( 8) // Function Address Register +#define UDP_IER (16) // Interrupt Enable Register +#define UDP_IDR (20) // Interrupt Disable Register +#define UDP_IMR (24) // Interrupt Mask Register +#define UDP_ISR (28) // Interrupt Status Register +#define UDP_ICR (32) // Interrupt Clear Register +#define UDP_RSTEP (40) // Reset Endpoint Register +#define UDP_CSR (48) // Endpoint Control and Status Register +#define UDP_FDR (80) // Endpoint FIFO Data Register +#define UDP_TXVC (116) // Transceiver Control Register +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured +#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume +#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt +#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt +#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 +#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4 +#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO +// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) +#define AT91C_UDP_PUON (0x1 << 9) // (UDP) Pull-up ON + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +// *** Register offset in AT91S_TC structure *** +#define TC_CCR ( 0) // Channel Control Register +#define TC_CMR ( 4) // Channel Mode Register (Capture Mode / Waveform Mode) +#define TC_CV (16) // Counter Value +#define TC_RA (20) // Register A +#define TC_RB (24) // Register B +#define TC_RC (28) // Register C +#define TC_SR (32) // Status Register +#define TC_IER (36) // Interrupt Enable Register +#define TC_IDR (40) // Interrupt Disable Register +#define TC_IMR (44) // Interrupt Mask Register +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE (0x1 << 15) // (TC) +#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger +#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +// *** Register offset in AT91S_TCB structure *** +#define TCB_TC0 ( 0) // TC Channel 0 +#define TCB_TC1 (64) // TC Channel 1 +#define TCB_TC2 (128) // TC Channel 2 +#define TCB_BCR (192) // TC Block Control Register +#define TCB_BMR (196) // TC Block Mode Register +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface +// ***************************************************************************** +// *** Register offset in AT91S_CAN_MB structure *** +#define CAN_MB_MMR ( 0) // MailBox Mode Register +#define CAN_MB_MAM ( 4) // MailBox Acceptance Mask Register +#define CAN_MB_MID ( 8) // MailBox ID Register +#define CAN_MB_MFID (12) // MailBox Family ID Register +#define CAN_MB_MSR (16) // MailBox Status Register +#define CAN_MB_MDL (20) // MailBox Data Low Register +#define CAN_MB_MDH (24) // MailBox Data High Register +#define CAN_MB_MCR (28) // MailBox Control Register +// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- +#define AT91C_CAN_MTIMEMARK (0xFFFF << 0) // (CAN_MB) Mailbox Timemark +#define AT91C_CAN_PRIOR (0xF << 16) // (CAN_MB) Mailbox Priority +#define AT91C_CAN_MOT (0x7 << 24) // (CAN_MB) Mailbox Object Type +#define AT91C_CAN_MOT_DIS (0x0 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RX (0x1 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RXOVERWRITE (0x2 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_TX (0x3 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_CONSUMER (0x4 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_PRODUCER (0x5 << 24) // (CAN_MB) +// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- +#define AT91C_CAN_MIDvB (0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode +#define AT91C_CAN_MIDvA (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode +#define AT91C_CAN_MIDE (0x1 << 29) // (CAN_MB) Identifier Version +// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- +// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- +// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- +#define AT91C_CAN_MTIMESTAMP (0xFFFF << 0) // (CAN_MB) Timer Value +#define AT91C_CAN_MDLC (0xF << 16) // (CAN_MB) Mailbox Data Length Code +#define AT91C_CAN_MRTR (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request +#define AT91C_CAN_MABT (0x1 << 22) // (CAN_MB) Mailbox Message Abort +#define AT91C_CAN_MRDY (0x1 << 23) // (CAN_MB) Mailbox Ready +#define AT91C_CAN_MMI (0x1 << 24) // (CAN_MB) Mailbox Message Ignored +// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- +// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- +// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- +#define AT91C_CAN_MACR (0x1 << 22) // (CAN_MB) Abort Request for Mailbox +#define AT91C_CAN_MTCR (0x1 << 23) // (CAN_MB) Mailbox Transfer Command + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network Interface +// ***************************************************************************** +// *** Register offset in AT91S_CAN structure *** +#define CAN_MR ( 0) // Mode Register +#define CAN_IER ( 4) // Interrupt Enable Register +#define CAN_IDR ( 8) // Interrupt Disable Register +#define CAN_IMR (12) // Interrupt Mask Register +#define CAN_SR (16) // Status Register +#define CAN_BR (20) // Baudrate Register +#define CAN_TIM (24) // Timer Register +#define CAN_TIMESTP (28) // Time Stamp Register +#define CAN_ECR (32) // Error Counter Register +#define CAN_TCR (36) // Transfer Command Register +#define CAN_ACR (40) // Abort Command Register +#define CAN_VR (252) // Version Register +#define CAN_MB0 (512) // CAN Mailbox 0 +#define CAN_MB1 (544) // CAN Mailbox 1 +#define CAN_MB2 (576) // CAN Mailbox 2 +#define CAN_MB3 (608) // CAN Mailbox 3 +#define CAN_MB4 (640) // CAN Mailbox 4 +#define CAN_MB5 (672) // CAN Mailbox 5 +#define CAN_MB6 (704) // CAN Mailbox 6 +#define CAN_MB7 (736) // CAN Mailbox 7 +#define CAN_MB8 (768) // CAN Mailbox 8 +#define CAN_MB9 (800) // CAN Mailbox 9 +#define CAN_MB10 (832) // CAN Mailbox 10 +#define CAN_MB11 (864) // CAN Mailbox 11 +#define CAN_MB12 (896) // CAN Mailbox 12 +#define CAN_MB13 (928) // CAN Mailbox 13 +#define CAN_MB14 (960) // CAN Mailbox 14 +#define CAN_MB15 (992) // CAN Mailbox 15 +// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- +#define AT91C_CAN_CANEN (0x1 << 0) // (CAN) CAN Controller Enable +#define AT91C_CAN_LPM (0x1 << 1) // (CAN) Disable/Enable Low Power Mode +#define AT91C_CAN_ABM (0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode +#define AT91C_CAN_OVL (0x1 << 3) // (CAN) Disable/Enable Overload Frame +#define AT91C_CAN_TEOF (0x1 << 4) // (CAN) Time Stamp messages at each end of Frame +#define AT91C_CAN_TTM (0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode +#define AT91C_CAN_TIMFRZ (0x1 << 6) // (CAN) Enable Timer Freeze +#define AT91C_CAN_DRPT (0x1 << 7) // (CAN) Disable Repeat +// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- +#define AT91C_CAN_MB0 (0x1 << 0) // (CAN) Mailbox 0 Flag +#define AT91C_CAN_MB1 (0x1 << 1) // (CAN) Mailbox 1 Flag +#define AT91C_CAN_MB2 (0x1 << 2) // (CAN) Mailbox 2 Flag +#define AT91C_CAN_MB3 (0x1 << 3) // (CAN) Mailbox 3 Flag +#define AT91C_CAN_MB4 (0x1 << 4) // (CAN) Mailbox 4 Flag +#define AT91C_CAN_MB5 (0x1 << 5) // (CAN) Mailbox 5 Flag +#define AT91C_CAN_MB6 (0x1 << 6) // (CAN) Mailbox 6 Flag +#define AT91C_CAN_MB7 (0x1 << 7) // (CAN) Mailbox 7 Flag +#define AT91C_CAN_MB8 (0x1 << 8) // (CAN) Mailbox 8 Flag +#define AT91C_CAN_MB9 (0x1 << 9) // (CAN) Mailbox 9 Flag +#define AT91C_CAN_MB10 (0x1 << 10) // (CAN) Mailbox 10 Flag +#define AT91C_CAN_MB11 (0x1 << 11) // (CAN) Mailbox 11 Flag +#define AT91C_CAN_MB12 (0x1 << 12) // (CAN) Mailbox 12 Flag +#define AT91C_CAN_MB13 (0x1 << 13) // (CAN) Mailbox 13 Flag +#define AT91C_CAN_MB14 (0x1 << 14) // (CAN) Mailbox 14 Flag +#define AT91C_CAN_MB15 (0x1 << 15) // (CAN) Mailbox 15 Flag +#define AT91C_CAN_ERRA (0x1 << 16) // (CAN) Error Active Mode Flag +#define AT91C_CAN_WARN (0x1 << 17) // (CAN) Warning Limit Flag +#define AT91C_CAN_ERRP (0x1 << 18) // (CAN) Error Passive Mode Flag +#define AT91C_CAN_BOFF (0x1 << 19) // (CAN) Bus Off Mode Flag +#define AT91C_CAN_SLEEP (0x1 << 20) // (CAN) Sleep Flag +#define AT91C_CAN_WAKEUP (0x1 << 21) // (CAN) Wakeup Flag +#define AT91C_CAN_TOVF (0x1 << 22) // (CAN) Timer Overflow Flag +#define AT91C_CAN_TSTP (0x1 << 23) // (CAN) Timestamp Flag +#define AT91C_CAN_CERR (0x1 << 24) // (CAN) CRC Error +#define AT91C_CAN_SERR (0x1 << 25) // (CAN) Stuffing Error +#define AT91C_CAN_AERR (0x1 << 26) // (CAN) Acknowledgment Error +#define AT91C_CAN_FERR (0x1 << 27) // (CAN) Form Error +#define AT91C_CAN_BERR (0x1 << 28) // (CAN) Bit Error +// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- +// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- +// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- +#define AT91C_CAN_RBSY (0x1 << 29) // (CAN) Receiver Busy +#define AT91C_CAN_TBSY (0x1 << 30) // (CAN) Transmitter Busy +#define AT91C_CAN_OVLY (0x1 << 31) // (CAN) Overload Busy +// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- +#define AT91C_CAN_PHASE2 (0x7 << 0) // (CAN) Phase 2 segment +#define AT91C_CAN_PHASE1 (0x7 << 4) // (CAN) Phase 1 segment +#define AT91C_CAN_PROPAG (0x7 << 8) // (CAN) Programmation time segment +#define AT91C_CAN_SYNC (0x3 << 12) // (CAN) Re-synchronization jump width segment +#define AT91C_CAN_BRP (0x7F << 16) // (CAN) Baudrate Prescaler +#define AT91C_CAN_SMP (0x1 << 24) // (CAN) Sampling mode +// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- +#define AT91C_CAN_TIMER (0xFFFF << 0) // (CAN) Timer field +// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- +// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- +#define AT91C_CAN_REC (0xFF << 0) // (CAN) Receive Error Counter +#define AT91C_CAN_TEC (0xFF << 16) // (CAN) Transmit Error Counter +// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- +#define AT91C_CAN_TIMRST (0x1 << 31) // (CAN) Timer Reset Field +// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 +// ***************************************************************************** +// *** Register offset in AT91S_EMAC structure *** +#define EMAC_NCR ( 0) // Network Control Register +#define EMAC_NCFGR ( 4) // Network Configuration Register +#define EMAC_NSR ( 8) // Network Status Register +#define EMAC_TSR (20) // Transmit Status Register +#define EMAC_RBQP (24) // Receive Buffer Queue Pointer +#define EMAC_TBQP (28) // Transmit Buffer Queue Pointer +#define EMAC_RSR (32) // Receive Status Register +#define EMAC_ISR (36) // Interrupt Status Register +#define EMAC_IER (40) // Interrupt Enable Register +#define EMAC_IDR (44) // Interrupt Disable Register +#define EMAC_IMR (48) // Interrupt Mask Register +#define EMAC_MAN (52) // PHY Maintenance Register +#define EMAC_PTR (56) // Pause Time Register +#define EMAC_PFR (60) // Pause Frames received Register +#define EMAC_FTO (64) // Frames Transmitted OK Register +#define EMAC_SCF (68) // Single Collision Frame Register +#define EMAC_MCF (72) // Multiple Collision Frame Register +#define EMAC_FRO (76) // Frames Received OK Register +#define EMAC_FCSE (80) // Frame Check Sequence Error Register +#define EMAC_ALE (84) // Alignment Error Register +#define EMAC_DTF (88) // Deferred Transmission Frame Register +#define EMAC_LCOL (92) // Late Collision Register +#define EMAC_ECOL (96) // Excessive Collision Register +#define EMAC_TUND (100) // Transmit Underrun Error Register +#define EMAC_CSE (104) // Carrier Sense Error Register +#define EMAC_RRE (108) // Receive Ressource Error Register +#define EMAC_ROV (112) // Receive Overrun Errors Register +#define EMAC_RSE (116) // Receive Symbol Errors Register +#define EMAC_ELE (120) // Excessive Length Errors Register +#define EMAC_RJA (124) // Receive Jabbers Register +#define EMAC_USF (128) // Undersize Frames Register +#define EMAC_STE (132) // SQE Test Error Register +#define EMAC_RLE (136) // Receive Length Field Mismatch Register +#define EMAC_TPF (140) // Transmitted Pause Frames Register +#define EMAC_HRB (144) // Hash Address Bottom[31:0] +#define EMAC_HRT (148) // Hash Address Top[63:32] +#define EMAC_SA1L (152) // Specific Address 1 Bottom, First 4 bytes +#define EMAC_SA1H (156) // Specific Address 1 Top, Last 2 bytes +#define EMAC_SA2L (160) // Specific Address 2 Bottom, First 4 bytes +#define EMAC_SA2H (164) // Specific Address 2 Top, Last 2 bytes +#define EMAC_SA3L (168) // Specific Address 3 Bottom, First 4 bytes +#define EMAC_SA3H (172) // Specific Address 3 Top, Last 2 bytes +#define EMAC_SA4L (176) // Specific Address 4 Bottom, First 4 bytes +#define EMAC_SA4H (180) // Specific Address 4 Top, Last 2 bytes +#define EMAC_TID (184) // Type ID Checking Register +#define EMAC_TPQ (188) // Transmit Pause Quantum Register +#define EMAC_USRIO (192) // USER Input/Output Register +#define EMAC_WOL (196) // Wake On LAN Register +#define EMAC_REV (252) // Revision Register +// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- +#define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. +#define AT91C_EMAC_LLB (0x1 << 1) // (EMAC) Loopback local. +#define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable. +#define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable. +#define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable. +#define AT91C_EMAC_CLRSTAT (0x1 << 5) // (EMAC) Clear statistics registers. +#define AT91C_EMAC_INCSTAT (0x1 << 6) // (EMAC) Increment statistics registers. +#define AT91C_EMAC_WESTAT (0x1 << 7) // (EMAC) Write enable for statistics registers. +#define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure. +#define AT91C_EMAC_TSTART (0x1 << 9) // (EMAC) Start Transmission. +#define AT91C_EMAC_THALT (0x1 << 10) // (EMAC) Transmission Halt. +#define AT91C_EMAC_TPFR (0x1 << 11) // (EMAC) Transmit pause frame +#define AT91C_EMAC_TZQ (0x1 << 12) // (EMAC) Transmit zero quantum pause frame +// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- +#define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed. +#define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex. +#define AT91C_EMAC_JFRAME (0x1 << 3) // (EMAC) Jumbo Frames. +#define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames. +#define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast. +#define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash event enable +#define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable. +#define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes. +#define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable. +#define AT91C_EMAC_CLK (0x3 << 10) // (EMAC) +#define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8 +#define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16 +#define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32 +#define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64 +#define AT91C_EMAC_RTY (0x1 << 12) // (EMAC) +#define AT91C_EMAC_PAE (0x1 << 13) // (EMAC) +#define AT91C_EMAC_RBOF (0x3 << 14) // (EMAC) +#define AT91C_EMAC_RBOF_OFFSET_0 (0x0 << 14) // (EMAC) no offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_1 (0x1 << 14) // (EMAC) one byte offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_2 (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_3 (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer +#define AT91C_EMAC_RLCE (0x1 << 16) // (EMAC) Receive Length field Checking Enable +#define AT91C_EMAC_DRFCS (0x1 << 17) // (EMAC) Discard Receive FCS +#define AT91C_EMAC_EFRHD (0x1 << 18) // (EMAC) +#define AT91C_EMAC_IRXFCS (0x1 << 19) // (EMAC) Ignore RX FCS +// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- +#define AT91C_EMAC_LINKR (0x1 << 0) // (EMAC) +#define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC) +#define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC) +// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- +#define AT91C_EMAC_UBR (0x1 << 0) // (EMAC) +#define AT91C_EMAC_COL (0x1 << 1) // (EMAC) +#define AT91C_EMAC_RLES (0x1 << 2) // (EMAC) +#define AT91C_EMAC_TGO (0x1 << 3) // (EMAC) Transmit Go +#define AT91C_EMAC_BEX (0x1 << 4) // (EMAC) Buffers exhausted mid frame +#define AT91C_EMAC_COMP (0x1 << 5) // (EMAC) +#define AT91C_EMAC_UND (0x1 << 6) // (EMAC) +// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- +#define AT91C_EMAC_BNA (0x1 << 0) // (EMAC) +#define AT91C_EMAC_REC (0x1 << 1) // (EMAC) +#define AT91C_EMAC_OVR (0x1 << 2) // (EMAC) +// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- +#define AT91C_EMAC_MFD (0x1 << 0) // (EMAC) +#define AT91C_EMAC_RCOMP (0x1 << 1) // (EMAC) +#define AT91C_EMAC_RXUBR (0x1 << 2) // (EMAC) +#define AT91C_EMAC_TXUBR (0x1 << 3) // (EMAC) +#define AT91C_EMAC_TUNDR (0x1 << 4) // (EMAC) +#define AT91C_EMAC_RLEX (0x1 << 5) // (EMAC) +#define AT91C_EMAC_TXERR (0x1 << 6) // (EMAC) +#define AT91C_EMAC_TCOMP (0x1 << 7) // (EMAC) +#define AT91C_EMAC_LINK (0x1 << 9) // (EMAC) +#define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC) +#define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC) +#define AT91C_EMAC_PFRE (0x1 << 12) // (EMAC) +#define AT91C_EMAC_PTZ (0x1 << 13) // (EMAC) +// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- +// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- +// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- +// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- +#define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_CODE (0x3 << 16) // (EMAC) +#define AT91C_EMAC_REGA (0x1F << 18) // (EMAC) +#define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC) +#define AT91C_EMAC_RW (0x3 << 28) // (EMAC) +#define AT91C_EMAC_SOF (0x3 << 30) // (EMAC) +// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- +#define AT91C_EMAC_RMII (0x1 << 0) // (EMAC) Reduce MII +// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- +#define AT91C_EMAC_IP (0xFFFF << 0) // (EMAC) ARP request IP address +#define AT91C_EMAC_MAG (0x1 << 16) // (EMAC) Magic packet event enable +#define AT91C_EMAC_ARP (0x1 << 17) // (EMAC) ARP request event enable +#define AT91C_EMAC_SA1 (0x1 << 18) // (EMAC) Specific address register 1 event enable +// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- +#define AT91C_EMAC_REVREF (0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_PARTREF (0xFFFF << 16) // (EMAC) + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +// *** Register offset in AT91S_ADC structure *** +#define ADC_CR ( 0) // ADC Control Register +#define ADC_MR ( 4) // ADC Mode Register +#define ADC_CHER (16) // ADC Channel Enable Register +#define ADC_CHDR (20) // ADC Channel Disable Register +#define ADC_CHSR (24) // ADC Channel Status Register +#define ADC_SR (28) // ADC Status Register +#define ADC_LCDR (32) // ADC Last Converted Data Register +#define ADC_IER (36) // ADC Interrupt Enable Register +#define ADC_IDR (40) // ADC Interrupt Disable Register +#define ADC_IMR (44) // ADC Interrupt Mask Register +#define ADC_CDR0 (48) // ADC Channel Data Register 0 +#define ADC_CDR1 (52) // ADC Channel Data Register 1 +#define ADC_CDR2 (56) // ADC Channel Data Register 2 +#define ADC_CDR3 (60) // ADC Channel Data Register 3 +#define ADC_CDR4 (64) // ADC Channel Data Register 4 +#define ADC_CDR5 (68) // ADC Channel Data Register 5 +#define ADC_CDR6 (72) // ADC Channel Data Register 6 +#define ADC_CDR7 (76) // ADC Channel Data Register 7 +#define ADC_RPR (256) // Receive Pointer Register +#define ADC_RCR (260) // Receive Counter Register +#define ADC_TPR (264) // Transmit Pointer Register +#define ADC_TCR (268) // Transmit Counter Register +#define ADC_RNPR (272) // Receive Next Pointer Register +#define ADC_RNCR (276) // Receive Next Counter Register +#define ADC_TNPR (280) // Transmit Next Pointer Register +#define ADC_TNCR (284) // Transmit Next Counter Register +#define ADC_PTCR (288) // PDC Transfer Control Register +#define ADC_PTSR (292) // PDC Transfer Status Register +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Encryption Standard +// ***************************************************************************** +// *** Register offset in AT91S_AES structure *** +#define AES_CR ( 0) // Control Register +#define AES_MR ( 4) // Mode Register +#define AES_IER (16) // Interrupt Enable Register +#define AES_IDR (20) // Interrupt Disable Register +#define AES_IMR (24) // Interrupt Mask Register +#define AES_ISR (28) // Interrupt Status Register +#define AES_KEYWxR (32) // Key Word x Register +#define AES_IDATAxR (64) // Input Data x Register +#define AES_ODATAxR (80) // Output Data x Register +#define AES_IVxR (96) // Initialization Vector x Register +#define AES_VR (252) // AES Version Register +#define AES_RPR (256) // Receive Pointer Register +#define AES_RCR (260) // Receive Counter Register +#define AES_TPR (264) // Transmit Pointer Register +#define AES_TCR (268) // Transmit Counter Register +#define AES_RNPR (272) // Receive Next Pointer Register +#define AES_RNCR (276) // Receive Next Counter Register +#define AES_TNPR (280) // Transmit Next Pointer Register +#define AES_TNCR (284) // Transmit Next Counter Register +#define AES_PTCR (288) // PDC Transfer Control Register +#define AES_PTSR (292) // PDC Transfer Status Register +// -------- AES_CR : (AES Offset: 0x0) Control Register -------- +#define AT91C_AES_START (0x1 << 0) // (AES) Starts Processing +#define AT91C_AES_SWRST (0x1 << 8) // (AES) Software Reset +#define AT91C_AES_LOADSEED (0x1 << 16) // (AES) Random Number Generator Seed Loading +// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- +#define AT91C_AES_CIPHER (0x1 << 0) // (AES) Processing Mode +#define AT91C_AES_PROCDLY (0xF << 4) // (AES) Processing Delay +#define AT91C_AES_SMOD (0x3 << 8) // (AES) Start Mode +#define AT91C_AES_SMOD_MANUAL (0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. +#define AT91C_AES_SMOD_AUTO (0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). +#define AT91C_AES_SMOD_PDC (0x2 << 8) // (AES) PDC Mode (cf datasheet). +#define AT91C_AES_OPMOD (0x7 << 12) // (AES) Operation Mode +#define AT91C_AES_OPMOD_ECB (0x0 << 12) // (AES) ECB Electronic CodeBook mode. +#define AT91C_AES_OPMOD_CBC (0x1 << 12) // (AES) CBC Cipher Block Chaining mode. +#define AT91C_AES_OPMOD_OFB (0x2 << 12) // (AES) OFB Output Feedback mode. +#define AT91C_AES_OPMOD_CFB (0x3 << 12) // (AES) CFB Cipher Feedback mode. +#define AT91C_AES_OPMOD_CTR (0x4 << 12) // (AES) CTR Counter mode. +#define AT91C_AES_LOD (0x1 << 15) // (AES) Last Output Data Mode +#define AT91C_AES_CFBS (0x7 << 16) // (AES) Cipher Feedback Data Size +#define AT91C_AES_CFBS_128_BIT (0x0 << 16) // (AES) 128-bit. +#define AT91C_AES_CFBS_64_BIT (0x1 << 16) // (AES) 64-bit. +#define AT91C_AES_CFBS_32_BIT (0x2 << 16) // (AES) 32-bit. +#define AT91C_AES_CFBS_16_BIT (0x3 << 16) // (AES) 16-bit. +#define AT91C_AES_CFBS_8_BIT (0x4 << 16) // (AES) 8-bit. +#define AT91C_AES_CKEY (0xF << 20) // (AES) Countermeasure Key +#define AT91C_AES_CTYPE (0x1F << 24) // (AES) Countermeasure Type +#define AT91C_AES_CTYPE_TYPE1_EN (0x1 << 24) // (AES) Countermeasure type 1 is enabled. +#define AT91C_AES_CTYPE_TYPE2_EN (0x2 << 24) // (AES) Countermeasure type 2 is enabled. +#define AT91C_AES_CTYPE_TYPE3_EN (0x4 << 24) // (AES) Countermeasure type 3 is enabled. +#define AT91C_AES_CTYPE_TYPE4_EN (0x8 << 24) // (AES) Countermeasure type 4 is enabled. +#define AT91C_AES_CTYPE_TYPE5_EN (0x10 << 24) // (AES) Countermeasure type 5 is enabled. +// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- +#define AT91C_AES_DATRDY (0x1 << 0) // (AES) DATRDY +#define AT91C_AES_ENDRX (0x1 << 1) // (AES) PDC Read Buffer End +#define AT91C_AES_ENDTX (0x1 << 2) // (AES) PDC Write Buffer End +#define AT91C_AES_RXBUFF (0x1 << 3) // (AES) PDC Read Buffer Full +#define AT91C_AES_TXBUFE (0x1 << 4) // (AES) PDC Write Buffer Empty +#define AT91C_AES_URAD (0x1 << 8) // (AES) Unspecified Register Access Detection +// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- +// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- +// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- +#define AT91C_AES_URAT (0x7 << 12) // (AES) Unspecified Register Access Type Status +#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (AES) Input data register written during the data processing in PDC mode. +#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (AES) Output data register read during the data processing. +#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (AES) Mode register written during the data processing. +#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY (0x3 << 12) // (AES) Output data register read during the sub-keys generation. +#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY (0x4 << 12) // (AES) Mode register written during the sub-keys generation. +#define AT91C_AES_URAT_WO_REG_READ (0x5 << 12) // (AES) Write-only register read access. + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard +// ***************************************************************************** +// *** Register offset in AT91S_TDES structure *** +#define TDES_CR ( 0) // Control Register +#define TDES_MR ( 4) // Mode Register +#define TDES_IER (16) // Interrupt Enable Register +#define TDES_IDR (20) // Interrupt Disable Register +#define TDES_IMR (24) // Interrupt Mask Register +#define TDES_ISR (28) // Interrupt Status Register +#define TDES_KEY1WxR (32) // Key 1 Word x Register +#define TDES_KEY2WxR (40) // Key 2 Word x Register +#define TDES_KEY3WxR (48) // Key 3 Word x Register +#define TDES_IDATAxR (64) // Input Data x Register +#define TDES_ODATAxR (80) // Output Data x Register +#define TDES_IVxR (96) // Initialization Vector x Register +#define TDES_VR (252) // TDES Version Register +#define TDES_RPR (256) // Receive Pointer Register +#define TDES_RCR (260) // Receive Counter Register +#define TDES_TPR (264) // Transmit Pointer Register +#define TDES_TCR (268) // Transmit Counter Register +#define TDES_RNPR (272) // Receive Next Pointer Register +#define TDES_RNCR (276) // Receive Next Counter Register +#define TDES_TNPR (280) // Transmit Next Pointer Register +#define TDES_TNCR (284) // Transmit Next Counter Register +#define TDES_PTCR (288) // PDC Transfer Control Register +#define TDES_PTSR (292) // PDC Transfer Status Register +// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- +#define AT91C_TDES_START (0x1 << 0) // (TDES) Starts Processing +#define AT91C_TDES_SWRST (0x1 << 8) // (TDES) Software Reset +// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- +#define AT91C_TDES_CIPHER (0x1 << 0) // (TDES) Processing Mode +#define AT91C_TDES_TDESMOD (0x1 << 1) // (TDES) Single or Triple DES Mode +#define AT91C_TDES_KEYMOD (0x1 << 4) // (TDES) Key Mode +#define AT91C_TDES_SMOD (0x3 << 8) // (TDES) Start Mode +#define AT91C_TDES_SMOD_MANUAL (0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. +#define AT91C_TDES_SMOD_AUTO (0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). +#define AT91C_TDES_SMOD_PDC (0x2 << 8) // (TDES) PDC Mode (cf datasheet). +#define AT91C_TDES_OPMOD (0x3 << 12) // (TDES) Operation Mode +#define AT91C_TDES_OPMOD_ECB (0x0 << 12) // (TDES) ECB Electronic CodeBook mode. +#define AT91C_TDES_OPMOD_CBC (0x1 << 12) // (TDES) CBC Cipher Block Chaining mode. +#define AT91C_TDES_OPMOD_OFB (0x2 << 12) // (TDES) OFB Output Feedback mode. +#define AT91C_TDES_OPMOD_CFB (0x3 << 12) // (TDES) CFB Cipher Feedback mode. +#define AT91C_TDES_LOD (0x1 << 15) // (TDES) Last Output Data Mode +#define AT91C_TDES_CFBS (0x3 << 16) // (TDES) Cipher Feedback Data Size +#define AT91C_TDES_CFBS_64_BIT (0x0 << 16) // (TDES) 64-bit. +#define AT91C_TDES_CFBS_32_BIT (0x1 << 16) // (TDES) 32-bit. +#define AT91C_TDES_CFBS_16_BIT (0x2 << 16) // (TDES) 16-bit. +#define AT91C_TDES_CFBS_8_BIT (0x3 << 16) // (TDES) 8-bit. +// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- +#define AT91C_TDES_DATRDY (0x1 << 0) // (TDES) DATRDY +#define AT91C_TDES_ENDRX (0x1 << 1) // (TDES) PDC Read Buffer End +#define AT91C_TDES_ENDTX (0x1 << 2) // (TDES) PDC Write Buffer End +#define AT91C_TDES_RXBUFF (0x1 << 3) // (TDES) PDC Read Buffer Full +#define AT91C_TDES_TXBUFE (0x1 << 4) // (TDES) PDC Write Buffer Empty +#define AT91C_TDES_URAD (0x1 << 8) // (TDES) Unspecified Register Access Detection +// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- +// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- +// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- +#define AT91C_TDES_URAT (0x3 << 12) // (TDES) Unspecified Register Access Type Status +#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode. +#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (TDES) Output data register read during the data processing. +#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (TDES) Mode register written during the data processing. +#define AT91C_TDES_URAT_WO_REG_READ (0x3 << 12) // (TDES) Write-only register read access. + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 +// ***************************************************************************** +// ========== Register definition for SYS peripheral ========== +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_IVR (0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_SMR (0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_FVR (0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_DCR (0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_EOICR (0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_SVR (0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_FFSR (0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_ICCR (0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_ISR (0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IMR (0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_IPR (0xFFFFF10C) // (AIC) Interrupt Pending Register +#define AT91C_AIC_FFER (0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_IECR (0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_ISCR (0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_FFDR (0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_CISR (0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IDCR (0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_SPU (0xFFFFF134) // (AIC) Spurious Vector Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TCR (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RNPR (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +#define AT91C_DBGU_TPR (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RPR (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_RCR (0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_RNCR (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_TNCR (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_EXID (0xFFFFF244) // (DBGU) Chip ID Extension Register +#define AT91C_DBGU_BRGR (0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_IDR (0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_CSR (0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_CIDR (0xFFFFF240) // (DBGU) Chip ID Register +#define AT91C_DBGU_MR (0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_IMR (0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_CR (0xFFFFF200) // (DBGU) Control Register +#define AT91C_DBGU_FNTR (0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_THR (0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_RHR (0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IER (0xFFFFF208) // (DBGU) Interrupt Enable Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_ODR (0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_SODR (0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_ISR (0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_ABSR (0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_IER (0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_PPUDR (0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_IMR (0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_PER (0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_IFDR (0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_OWDR (0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_MDSR (0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_IDR (0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_ODSR (0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_PPUSR (0xFFFFF468) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_OWSR (0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_BSR (0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_OWER (0xFFFFF4A0) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IFER (0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_PDSR (0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_PPUER (0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_OSR (0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_ASR (0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_MDDR (0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_CODR (0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_MDER (0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PDR (0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_IFSR (0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_OER (0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_PSR (0xFFFFF408) // (PIOA) PIO Status Register +// ========== Register definition for PIOB peripheral ========== +#define AT91C_PIOB_OWDR (0xFFFFF6A4) // (PIOB) Output Write Disable Register +#define AT91C_PIOB_MDER (0xFFFFF650) // (PIOB) Multi-driver Enable Register +#define AT91C_PIOB_PPUSR (0xFFFFF668) // (PIOB) Pull-up Status Register +#define AT91C_PIOB_IMR (0xFFFFF648) // (PIOB) Interrupt Mask Register +#define AT91C_PIOB_ASR (0xFFFFF670) // (PIOB) Select A Register +#define AT91C_PIOB_PPUDR (0xFFFFF660) // (PIOB) Pull-up Disable Register +#define AT91C_PIOB_PSR (0xFFFFF608) // (PIOB) PIO Status Register +#define AT91C_PIOB_IER (0xFFFFF640) // (PIOB) Interrupt Enable Register +#define AT91C_PIOB_CODR (0xFFFFF634) // (PIOB) Clear Output Data Register +#define AT91C_PIOB_OWER (0xFFFFF6A0) // (PIOB) Output Write Enable Register +#define AT91C_PIOB_ABSR (0xFFFFF678) // (PIOB) AB Select Status Register +#define AT91C_PIOB_IFDR (0xFFFFF624) // (PIOB) Input Filter Disable Register +#define AT91C_PIOB_PDSR (0xFFFFF63C) // (PIOB) Pin Data Status Register +#define AT91C_PIOB_IDR (0xFFFFF644) // (PIOB) Interrupt Disable Register +#define AT91C_PIOB_OWSR (0xFFFFF6A8) // (PIOB) Output Write Status Register +#define AT91C_PIOB_PDR (0xFFFFF604) // (PIOB) PIO Disable Register +#define AT91C_PIOB_ODR (0xFFFFF614) // (PIOB) Output Disable Registerr +#define AT91C_PIOB_IFSR (0xFFFFF628) // (PIOB) Input Filter Status Register +#define AT91C_PIOB_PPUER (0xFFFFF664) // (PIOB) Pull-up Enable Register +#define AT91C_PIOB_SODR (0xFFFFF630) // (PIOB) Set Output Data Register +#define AT91C_PIOB_ISR (0xFFFFF64C) // (PIOB) Interrupt Status Register +#define AT91C_PIOB_ODSR (0xFFFFF638) // (PIOB) Output Data Status Register +#define AT91C_PIOB_OSR (0xFFFFF618) // (PIOB) Output Status Register +#define AT91C_PIOB_MDSR (0xFFFFF658) // (PIOB) Multi-driver Status Register +#define AT91C_PIOB_IFER (0xFFFFF620) // (PIOB) Input Filter Enable Register +#define AT91C_PIOB_BSR (0xFFFFF674) // (PIOB) Select B Register +#define AT91C_PIOB_MDDR (0xFFFFF654) // (PIOB) Multi-driver Disable Register +#define AT91C_PIOB_OER (0xFFFFF610) // (PIOB) Output Enable Register +#define AT91C_PIOB_PER (0xFFFFF600) // (PIOB) PIO Enable Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_MOR (0xFFFFFC20) // (CKGR) Main Oscillator Register +#define AT91C_CKGR_PLLR (0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR (0xFFFFFC24) // (CKGR) Main Clock Frequency Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_IDR (0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_MOR (0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PLLR (0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_PCER (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCKR (0xFFFFFC40) // (PMC) Programmable Clock Register +#define AT91C_PMC_MCKR (0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_SCDR (0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_PCDR (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCSR (0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_PCSR (0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_MCFR (0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_SCER (0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR (0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IER (0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_SR (0xFFFFFC68) // (PMC) Status Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RCR (0xFFFFFD00) // (RSTC) Reset Control Register +#define AT91C_RSTC_RMR (0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RSR (0xFFFFFD04) // (RSTC) Reset Status Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR (0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTMR (0xFFFFFD20) // (RTTC) Real-time Mode Register +#define AT91C_RTTC_RTVR (0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTAR (0xFFFFFD24) // (RTTC) Real-time Alarm Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIVR (0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PISR (0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIIR (0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PIMR (0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDCR (0xFFFFFD40) // (WDTC) Watchdog Control Register +#define AT91C_WDTC_WDSR (0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDMR (0xFFFFFD44) // (WDTC) Watchdog Mode Register +// ========== Register definition for VREG peripheral ========== +#define AT91C_VREG_MR (0xFFFFFD60) // (VREG) Voltage Regulator Mode Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_ASR (0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_RCR (0xFFFFFF00) // (MC) MC Remap Control Register +#define AT91C_MC_FCR (0xFFFFFF64) // (MC) MC Flash Command Register +#define AT91C_MC_AASR (0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_FSR (0xFFFFFF68) // (MC) MC Flash Status Register +#define AT91C_MC_FMR (0xFFFFFF60) // (MC) MC Flash Mode Register +// ========== Register definition for PDC_SPI1 peripheral ========== +#define AT91C_SPI1_PTCR (0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register +#define AT91C_SPI1_RPR (0xFFFE4100) // (PDC_SPI1) Receive Pointer Register +#define AT91C_SPI1_TNCR (0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register +#define AT91C_SPI1_TPR (0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register +#define AT91C_SPI1_TNPR (0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register +#define AT91C_SPI1_TCR (0xFFFE410C) // (PDC_SPI1) Transmit Counter Register +#define AT91C_SPI1_RCR (0xFFFE4104) // (PDC_SPI1) Receive Counter Register +#define AT91C_SPI1_RNPR (0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register +#define AT91C_SPI1_RNCR (0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register +#define AT91C_SPI1_PTSR (0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register +// ========== Register definition for SPI1 peripheral ========== +#define AT91C_SPI1_IMR (0xFFFE401C) // (SPI1) Interrupt Mask Register +#define AT91C_SPI1_IER (0xFFFE4014) // (SPI1) Interrupt Enable Register +#define AT91C_SPI1_MR (0xFFFE4004) // (SPI1) Mode Register +#define AT91C_SPI1_RDR (0xFFFE4008) // (SPI1) Receive Data Register +#define AT91C_SPI1_IDR (0xFFFE4018) // (SPI1) Interrupt Disable Register +#define AT91C_SPI1_SR (0xFFFE4010) // (SPI1) Status Register +#define AT91C_SPI1_TDR (0xFFFE400C) // (SPI1) Transmit Data Register +#define AT91C_SPI1_CR (0xFFFE4000) // (SPI1) Control Register +#define AT91C_SPI1_CSR (0xFFFE4030) // (SPI1) Chip Select Register +// ========== Register definition for PDC_SPI0 peripheral ========== +#define AT91C_SPI0_PTCR (0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register +#define AT91C_SPI0_TPR (0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register +#define AT91C_SPI0_TCR (0xFFFE010C) // (PDC_SPI0) Transmit Counter Register +#define AT91C_SPI0_RCR (0xFFFE0104) // (PDC_SPI0) Receive Counter Register +#define AT91C_SPI0_PTSR (0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register +#define AT91C_SPI0_RNPR (0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register +#define AT91C_SPI0_RPR (0xFFFE0100) // (PDC_SPI0) Receive Pointer Register +#define AT91C_SPI0_TNCR (0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register +#define AT91C_SPI0_RNCR (0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register +#define AT91C_SPI0_TNPR (0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register +// ========== Register definition for SPI0 peripheral ========== +#define AT91C_SPI0_IER (0xFFFE0014) // (SPI0) Interrupt Enable Register +#define AT91C_SPI0_SR (0xFFFE0010) // (SPI0) Status Register +#define AT91C_SPI0_IDR (0xFFFE0018) // (SPI0) Interrupt Disable Register +#define AT91C_SPI0_CR (0xFFFE0000) // (SPI0) Control Register +#define AT91C_SPI0_MR (0xFFFE0004) // (SPI0) Mode Register +#define AT91C_SPI0_IMR (0xFFFE001C) // (SPI0) Interrupt Mask Register +#define AT91C_SPI0_TDR (0xFFFE000C) // (SPI0) Transmit Data Register +#define AT91C_SPI0_RDR (0xFFFE0008) // (SPI0) Receive Data Register +#define AT91C_SPI0_CSR (0xFFFE0030) // (SPI0) Chip Select Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_RNCR (0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_PTCR (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TCR (0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_PTSR (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNPR (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RCR (0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_RNPR (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_RPR (0xFFFC4100) // (PDC_US1) Receive Pointer Register +#define AT91C_US1_TNCR (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_TPR (0xFFFC4108) // (PDC_US1) Transmit Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_IF (0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER (0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_RTOR (0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_CSR (0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR (0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_IER (0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_THR (0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_TTGR (0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_RHR (0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_BRGR (0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_IMR (0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_FIDI (0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_CR (0xFFFC4000) // (US1) Control Register +#define AT91C_US1_MR (0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_TNPR (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TCR (0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_PTCR (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_PTSR (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_TPR (0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RCR (0xFFFC0104) // (PDC_US0) Receive Counter Register +#define AT91C_US0_RPR (0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_RNCR (0xFFFC0114) // (PDC_US0) Receive Next Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_BRGR (0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_NER (0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_CR (0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IMR (0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_FIDI (0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_TTGR (0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_MR (0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_RTOR (0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_CSR (0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_RHR (0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IDR (0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_THR (0xFFFC001C) // (US0) Transmitter Holding Register +#define AT91C_US0_IF (0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_IER (0xFFFC0008) // (US0) Interrupt Enable Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_TNCR (0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RPR (0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_RNCR (0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TPR (0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_PTCR (0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TCR (0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR (0xFFFD4104) // (PDC_SSC) Receive Counter Register +#define AT91C_SSC_RNPR (0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TNPR (0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_PTSR (0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RHR (0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_RSHR (0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_TFMR (0xFFFD401C) // (SSC) Transmit Frame Mode Register +#define AT91C_SSC_IDR (0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_THR (0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_RCMR (0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_IER (0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_TSHR (0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_SR (0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_CMR (0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_TCMR (0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_CR (0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR (0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_RFMR (0xFFFD4014) // (SSC) Receive Frame Mode Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_IER (0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_CR (0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_SR (0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_IMR (0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_THR (0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IDR (0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_IADR (0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR (0xFFFB8004) // (TWI) Master Mode Register +#define AT91C_TWI_CWGR (0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_RHR (0xFFFB8030) // (TWI) Receive Holding Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_PWMC_CH3_CUPDR (0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_PWMC_CH3_Reserved (0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_PWMC_CH3_CPRDR (0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_PWMC_CH3_CDTYR (0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +#define AT91C_PWMC_CH3_CCNTR (0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_PWMC_CH3_CMR (0xFFFCC260) // (PWMC_CH3) Channel Mode Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_PWMC_CH2_Reserved (0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_PWMC_CH2_CMR (0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_PWMC_CH2_CCNTR (0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_PWMC_CH2_CPRDR (0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_PWMC_CH2_CUPDR (0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_PWMC_CH2_CDTYR (0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_PWMC_CH1_Reserved (0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_PWMC_CH1_CUPDR (0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_PWMC_CH1_CPRDR (0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_PWMC_CH1_CCNTR (0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_PWMC_CH1_CDTYR (0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +#define AT91C_PWMC_CH1_CMR (0xFFFCC220) // (PWMC_CH1) Channel Mode Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_PWMC_CH0_Reserved (0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_PWMC_CH0_CPRDR (0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_PWMC_CH0_CDTYR (0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +#define AT91C_PWMC_CH0_CMR (0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_PWMC_CH0_CUPDR (0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_PWMC_CH0_CCNTR (0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_IDR (0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_DIS (0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER (0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +#define AT91C_PWMC_VR (0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR (0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_SR (0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_IMR (0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR (0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_ENA (0xFFFCC004) // (PWMC) PWMC Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_IMR (0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_FADDR (0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM (0xFFFB0000) // (UDP) Frame Number Register +#define AT91C_UDP_FDR (0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_ISR (0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_CSR (0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_IDR (0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_ICR (0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_RSTEP (0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_TXVC (0xFFFB0074) // (UDP) Transceiver Control Register +#define AT91C_UDP_GLBSTATE (0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_IER (0xFFFB0010) // (UDP) Interrupt Enable Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_SR (0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RC (0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RB (0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CCR (0xFFFA0000) // (TC0) Channel Control Register +#define AT91C_TC0_CMR (0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IER (0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RA (0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_IDR (0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_CV (0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_IMR (0xFFFA002C) // (TC0) Interrupt Mask Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_RB (0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CCR (0xFFFA0040) // (TC1) Channel Control Register +#define AT91C_TC1_IER (0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_IDR (0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR (0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_CMR (0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_RA (0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_RC (0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_IMR (0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_CV (0xFFFA0050) // (TC1) Counter Value +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_CMR (0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_CCR (0xFFFA0080) // (TC2) Channel Control Register +#define AT91C_TC2_CV (0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_RA (0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_RB (0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_IDR (0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_IMR (0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_RC (0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_IER (0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_SR (0xFFFA00A0) // (TC2) Status Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR (0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR (0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for CAN_MB0 peripheral ========== +#define AT91C_CAN_MB0_MDL (0xFFFD0214) // (CAN_MB0) MailBox Data Low Register +#define AT91C_CAN_MB0_MAM (0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register +#define AT91C_CAN_MB0_MCR (0xFFFD021C) // (CAN_MB0) MailBox Control Register +#define AT91C_CAN_MB0_MID (0xFFFD0208) // (CAN_MB0) MailBox ID Register +#define AT91C_CAN_MB0_MSR (0xFFFD0210) // (CAN_MB0) MailBox Status Register +#define AT91C_CAN_MB0_MFID (0xFFFD020C) // (CAN_MB0) MailBox Family ID Register +#define AT91C_CAN_MB0_MDH (0xFFFD0218) // (CAN_MB0) MailBox Data High Register +#define AT91C_CAN_MB0_MMR (0xFFFD0200) // (CAN_MB0) MailBox Mode Register +// ========== Register definition for CAN_MB1 peripheral ========== +#define AT91C_CAN_MB1_MDL (0xFFFD0234) // (CAN_MB1) MailBox Data Low Register +#define AT91C_CAN_MB1_MID (0xFFFD0228) // (CAN_MB1) MailBox ID Register +#define AT91C_CAN_MB1_MMR (0xFFFD0220) // (CAN_MB1) MailBox Mode Register +#define AT91C_CAN_MB1_MSR (0xFFFD0230) // (CAN_MB1) MailBox Status Register +#define AT91C_CAN_MB1_MAM (0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register +#define AT91C_CAN_MB1_MDH (0xFFFD0238) // (CAN_MB1) MailBox Data High Register +#define AT91C_CAN_MB1_MCR (0xFFFD023C) // (CAN_MB1) MailBox Control Register +#define AT91C_CAN_MB1_MFID (0xFFFD022C) // (CAN_MB1) MailBox Family ID Register +// ========== Register definition for CAN_MB2 peripheral ========== +#define AT91C_CAN_MB2_MCR (0xFFFD025C) // (CAN_MB2) MailBox Control Register +#define AT91C_CAN_MB2_MDH (0xFFFD0258) // (CAN_MB2) MailBox Data High Register +#define AT91C_CAN_MB2_MID (0xFFFD0248) // (CAN_MB2) MailBox ID Register +#define AT91C_CAN_MB2_MDL (0xFFFD0254) // (CAN_MB2) MailBox Data Low Register +#define AT91C_CAN_MB2_MMR (0xFFFD0240) // (CAN_MB2) MailBox Mode Register +#define AT91C_CAN_MB2_MAM (0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register +#define AT91C_CAN_MB2_MFID (0xFFFD024C) // (CAN_MB2) MailBox Family ID Register +#define AT91C_CAN_MB2_MSR (0xFFFD0250) // (CAN_MB2) MailBox Status Register +// ========== Register definition for CAN_MB3 peripheral ========== +#define AT91C_CAN_MB3_MFID (0xFFFD026C) // (CAN_MB3) MailBox Family ID Register +#define AT91C_CAN_MB3_MAM (0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register +#define AT91C_CAN_MB3_MID (0xFFFD0268) // (CAN_MB3) MailBox ID Register +#define AT91C_CAN_MB3_MCR (0xFFFD027C) // (CAN_MB3) MailBox Control Register +#define AT91C_CAN_MB3_MMR (0xFFFD0260) // (CAN_MB3) MailBox Mode Register +#define AT91C_CAN_MB3_MSR (0xFFFD0270) // (CAN_MB3) MailBox Status Register +#define AT91C_CAN_MB3_MDL (0xFFFD0274) // (CAN_MB3) MailBox Data Low Register +#define AT91C_CAN_MB3_MDH (0xFFFD0278) // (CAN_MB3) MailBox Data High Register +// ========== Register definition for CAN_MB4 peripheral ========== +#define AT91C_CAN_MB4_MID (0xFFFD0288) // (CAN_MB4) MailBox ID Register +#define AT91C_CAN_MB4_MMR (0xFFFD0280) // (CAN_MB4) MailBox Mode Register +#define AT91C_CAN_MB4_MDH (0xFFFD0298) // (CAN_MB4) MailBox Data High Register +#define AT91C_CAN_MB4_MFID (0xFFFD028C) // (CAN_MB4) MailBox Family ID Register +#define AT91C_CAN_MB4_MSR (0xFFFD0290) // (CAN_MB4) MailBox Status Register +#define AT91C_CAN_MB4_MCR (0xFFFD029C) // (CAN_MB4) MailBox Control Register +#define AT91C_CAN_MB4_MDL (0xFFFD0294) // (CAN_MB4) MailBox Data Low Register +#define AT91C_CAN_MB4_MAM (0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB5 peripheral ========== +#define AT91C_CAN_MB5_MSR (0xFFFD02B0) // (CAN_MB5) MailBox Status Register +#define AT91C_CAN_MB5_MCR (0xFFFD02BC) // (CAN_MB5) MailBox Control Register +#define AT91C_CAN_MB5_MFID (0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register +#define AT91C_CAN_MB5_MDH (0xFFFD02B8) // (CAN_MB5) MailBox Data High Register +#define AT91C_CAN_MB5_MID (0xFFFD02A8) // (CAN_MB5) MailBox ID Register +#define AT91C_CAN_MB5_MMR (0xFFFD02A0) // (CAN_MB5) MailBox Mode Register +#define AT91C_CAN_MB5_MDL (0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register +#define AT91C_CAN_MB5_MAM (0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB6 peripheral ========== +#define AT91C_CAN_MB6_MFID (0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register +#define AT91C_CAN_MB6_MID (0xFFFD02C8) // (CAN_MB6) MailBox ID Register +#define AT91C_CAN_MB6_MAM (0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register +#define AT91C_CAN_MB6_MSR (0xFFFD02D0) // (CAN_MB6) MailBox Status Register +#define AT91C_CAN_MB6_MDL (0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register +#define AT91C_CAN_MB6_MCR (0xFFFD02DC) // (CAN_MB6) MailBox Control Register +#define AT91C_CAN_MB6_MDH (0xFFFD02D8) // (CAN_MB6) MailBox Data High Register +#define AT91C_CAN_MB6_MMR (0xFFFD02C0) // (CAN_MB6) MailBox Mode Register +// ========== Register definition for CAN_MB7 peripheral ========== +#define AT91C_CAN_MB7_MCR (0xFFFD02FC) // (CAN_MB7) MailBox Control Register +#define AT91C_CAN_MB7_MDH (0xFFFD02F8) // (CAN_MB7) MailBox Data High Register +#define AT91C_CAN_MB7_MFID (0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register +#define AT91C_CAN_MB7_MDL (0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register +#define AT91C_CAN_MB7_MID (0xFFFD02E8) // (CAN_MB7) MailBox ID Register +#define AT91C_CAN_MB7_MMR (0xFFFD02E0) // (CAN_MB7) MailBox Mode Register +#define AT91C_CAN_MB7_MAM (0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register +#define AT91C_CAN_MB7_MSR (0xFFFD02F0) // (CAN_MB7) MailBox Status Register +// ========== Register definition for CAN peripheral ========== +#define AT91C_CAN_TCR (0xFFFD0024) // (CAN) Transfer Command Register +#define AT91C_CAN_IMR (0xFFFD000C) // (CAN) Interrupt Mask Register +#define AT91C_CAN_IER (0xFFFD0004) // (CAN) Interrupt Enable Register +#define AT91C_CAN_ECR (0xFFFD0020) // (CAN) Error Counter Register +#define AT91C_CAN_TIMESTP (0xFFFD001C) // (CAN) Time Stamp Register +#define AT91C_CAN_MR (0xFFFD0000) // (CAN) Mode Register +#define AT91C_CAN_IDR (0xFFFD0008) // (CAN) Interrupt Disable Register +#define AT91C_CAN_ACR (0xFFFD0028) // (CAN) Abort Command Register +#define AT91C_CAN_TIM (0xFFFD0018) // (CAN) Timer Register +#define AT91C_CAN_SR (0xFFFD0010) // (CAN) Status Register +#define AT91C_CAN_BR (0xFFFD0014) // (CAN) Baudrate Register +#define AT91C_CAN_VR (0xFFFD00FC) // (CAN) Version Register +// ========== Register definition for EMAC peripheral ========== +#define AT91C_EMAC_ISR (0xFFFDC024) // (EMAC) Interrupt Status Register +#define AT91C_EMAC_SA4H (0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes +#define AT91C_EMAC_SA1L (0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes +#define AT91C_EMAC_ELE (0xFFFDC078) // (EMAC) Excessive Length Errors Register +#define AT91C_EMAC_LCOL (0xFFFDC05C) // (EMAC) Late Collision Register +#define AT91C_EMAC_RLE (0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register +#define AT91C_EMAC_WOL (0xFFFDC0C4) // (EMAC) Wake On LAN Register +#define AT91C_EMAC_DTF (0xFFFDC058) // (EMAC) Deferred Transmission Frame Register +#define AT91C_EMAC_TUND (0xFFFDC064) // (EMAC) Transmit Underrun Error Register +#define AT91C_EMAC_NCR (0xFFFDC000) // (EMAC) Network Control Register +#define AT91C_EMAC_SA4L (0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes +#define AT91C_EMAC_RSR (0xFFFDC020) // (EMAC) Receive Status Register +#define AT91C_EMAC_SA3L (0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes +#define AT91C_EMAC_TSR (0xFFFDC014) // (EMAC) Transmit Status Register +#define AT91C_EMAC_IDR (0xFFFDC02C) // (EMAC) Interrupt Disable Register +#define AT91C_EMAC_RSE (0xFFFDC074) // (EMAC) Receive Symbol Errors Register +#define AT91C_EMAC_ECOL (0xFFFDC060) // (EMAC) Excessive Collision Register +#define AT91C_EMAC_TID (0xFFFDC0B8) // (EMAC) Type ID Checking Register +#define AT91C_EMAC_HRB (0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] +#define AT91C_EMAC_TBQP (0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer +#define AT91C_EMAC_USRIO (0xFFFDC0C0) // (EMAC) USER Input/Output Register +#define AT91C_EMAC_PTR (0xFFFDC038) // (EMAC) Pause Time Register +#define AT91C_EMAC_SA2H (0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes +#define AT91C_EMAC_ROV (0xFFFDC070) // (EMAC) Receive Overrun Errors Register +#define AT91C_EMAC_ALE (0xFFFDC054) // (EMAC) Alignment Error Register +#define AT91C_EMAC_RJA (0xFFFDC07C) // (EMAC) Receive Jabbers Register +#define AT91C_EMAC_RBQP (0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer +#define AT91C_EMAC_TPF (0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register +#define AT91C_EMAC_NCFGR (0xFFFDC004) // (EMAC) Network Configuration Register +#define AT91C_EMAC_HRT (0xFFFDC094) // (EMAC) Hash Address Top[63:32] +#define AT91C_EMAC_USF (0xFFFDC080) // (EMAC) Undersize Frames Register +#define AT91C_EMAC_FCSE (0xFFFDC050) // (EMAC) Frame Check Sequence Error Register +#define AT91C_EMAC_TPQ (0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register +#define AT91C_EMAC_MAN (0xFFFDC034) // (EMAC) PHY Maintenance Register +#define AT91C_EMAC_FTO (0xFFFDC040) // (EMAC) Frames Transmitted OK Register +#define AT91C_EMAC_REV (0xFFFDC0FC) // (EMAC) Revision Register +#define AT91C_EMAC_IMR (0xFFFDC030) // (EMAC) Interrupt Mask Register +#define AT91C_EMAC_SCF (0xFFFDC044) // (EMAC) Single Collision Frame Register +#define AT91C_EMAC_PFR (0xFFFDC03C) // (EMAC) Pause Frames received Register +#define AT91C_EMAC_MCF (0xFFFDC048) // (EMAC) Multiple Collision Frame Register +#define AT91C_EMAC_NSR (0xFFFDC008) // (EMAC) Network Status Register +#define AT91C_EMAC_SA2L (0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes +#define AT91C_EMAC_FRO (0xFFFDC04C) // (EMAC) Frames Received OK Register +#define AT91C_EMAC_IER (0xFFFDC028) // (EMAC) Interrupt Enable Register +#define AT91C_EMAC_SA1H (0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes +#define AT91C_EMAC_CSE (0xFFFDC068) // (EMAC) Carrier Sense Error Register +#define AT91C_EMAC_SA3H (0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes +#define AT91C_EMAC_RRE (0xFFFDC06C) // (EMAC) Receive Ressource Error Register +#define AT91C_EMAC_STE (0xFFFDC084) // (EMAC) SQE Test Error Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTSR (0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_PTCR (0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR (0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_TNCR (0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNPR (0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_RNCR (0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_RPR (0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_TCR (0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_TPR (0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RCR (0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_CDR2 (0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR3 (0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR0 (0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR5 (0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_CHDR (0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_SR (0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CDR4 (0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR1 (0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_LCDR (0xFFFD8020) // (ADC) ADC Last Converted Data Register +#define AT91C_ADC_IDR (0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_CR (0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CDR7 (0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR6 (0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_IER (0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_CHER (0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR (0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_MR (0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_IMR (0xFFFD802C) // (ADC) ADC Interrupt Mask Register +// ========== Register definition for PDC_AES peripheral ========== +#define AT91C_AES_TPR (0xFFFA4108) // (PDC_AES) Transmit Pointer Register +#define AT91C_AES_PTCR (0xFFFA4120) // (PDC_AES) PDC Transfer Control Register +#define AT91C_AES_RNPR (0xFFFA4110) // (PDC_AES) Receive Next Pointer Register +#define AT91C_AES_TNCR (0xFFFA411C) // (PDC_AES) Transmit Next Counter Register +#define AT91C_AES_TCR (0xFFFA410C) // (PDC_AES) Transmit Counter Register +#define AT91C_AES_RCR (0xFFFA4104) // (PDC_AES) Receive Counter Register +#define AT91C_AES_RNCR (0xFFFA4114) // (PDC_AES) Receive Next Counter Register +#define AT91C_AES_TNPR (0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register +#define AT91C_AES_RPR (0xFFFA4100) // (PDC_AES) Receive Pointer Register +#define AT91C_AES_PTSR (0xFFFA4124) // (PDC_AES) PDC Transfer Status Register +// ========== Register definition for AES peripheral ========== +#define AT91C_AES_IVxR (0xFFFA4060) // (AES) Initialization Vector x Register +#define AT91C_AES_MR (0xFFFA4004) // (AES) Mode Register +#define AT91C_AES_VR (0xFFFA40FC) // (AES) AES Version Register +#define AT91C_AES_ODATAxR (0xFFFA4050) // (AES) Output Data x Register +#define AT91C_AES_IDATAxR (0xFFFA4040) // (AES) Input Data x Register +#define AT91C_AES_CR (0xFFFA4000) // (AES) Control Register +#define AT91C_AES_IDR (0xFFFA4014) // (AES) Interrupt Disable Register +#define AT91C_AES_IMR (0xFFFA4018) // (AES) Interrupt Mask Register +#define AT91C_AES_IER (0xFFFA4010) // (AES) Interrupt Enable Register +#define AT91C_AES_KEYWxR (0xFFFA4020) // (AES) Key Word x Register +#define AT91C_AES_ISR (0xFFFA401C) // (AES) Interrupt Status Register +// ========== Register definition for PDC_TDES peripheral ========== +#define AT91C_TDES_RNCR (0xFFFA8114) // (PDC_TDES) Receive Next Counter Register +#define AT91C_TDES_TCR (0xFFFA810C) // (PDC_TDES) Transmit Counter Register +#define AT91C_TDES_RCR (0xFFFA8104) // (PDC_TDES) Receive Counter Register +#define AT91C_TDES_TNPR (0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register +#define AT91C_TDES_RNPR (0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register +#define AT91C_TDES_RPR (0xFFFA8100) // (PDC_TDES) Receive Pointer Register +#define AT91C_TDES_TNCR (0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register +#define AT91C_TDES_TPR (0xFFFA8108) // (PDC_TDES) Transmit Pointer Register +#define AT91C_TDES_PTSR (0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register +#define AT91C_TDES_PTCR (0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register +// ========== Register definition for TDES peripheral ========== +#define AT91C_TDES_KEY2WxR (0xFFFA8028) // (TDES) Key 2 Word x Register +#define AT91C_TDES_KEY3WxR (0xFFFA8030) // (TDES) Key 3 Word x Register +#define AT91C_TDES_IDR (0xFFFA8014) // (TDES) Interrupt Disable Register +#define AT91C_TDES_VR (0xFFFA80FC) // (TDES) TDES Version Register +#define AT91C_TDES_IVxR (0xFFFA8060) // (TDES) Initialization Vector x Register +#define AT91C_TDES_ODATAxR (0xFFFA8050) // (TDES) Output Data x Register +#define AT91C_TDES_IMR (0xFFFA8018) // (TDES) Interrupt Mask Register +#define AT91C_TDES_MR (0xFFFA8004) // (TDES) Mode Register +#define AT91C_TDES_CR (0xFFFA8000) // (TDES) Control Register +#define AT91C_TDES_IER (0xFFFA8010) // (TDES) Interrupt Enable Register +#define AT91C_TDES_ISR (0xFFFA801C) // (TDES) Interrupt Status Register +#define AT91C_TDES_IDATAxR (0xFFFA8040) // (TDES) Input Data x Register +#define AT91C_TDES_KEY1WxR (0xFFFA8020) // (TDES) Key 1 Word x Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_RXD0 (AT91C_PIO_PA0) // USART 0 Receive Data +#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_TXD0 (AT91C_PIO_PA1) // USART 0 Transmit Data +#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_TWD (AT91C_PIO_PA10) // TWI Two-wire Serial Data +#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_TWCK (AT91C_PIO_PA11) // TWI Two-wire Serial Clock +#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_NPCS00 (AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 +#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_NPCS01 (AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PA13_PCK1 (AT91C_PIO_PA13) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_NPCS02 (AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PA14_IRQ1 (AT91C_PIO_PA14) // External Interrupt 1 +#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_NPCS03 (AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PA15_TCLK2 (AT91C_PIO_PA15) // Timer Counter 2 external clock input +#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_MISO0 (AT91C_PIO_PA16) // SPI 0 Master In Slave +#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_MOSI0 (AT91C_PIO_PA17) // SPI 0 Master Out Slave +#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_SPCK0 (AT91C_PIO_PA18) // SPI 0 Serial Clock +#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_CANRX (AT91C_PIO_PA19) // CAN Receive +#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PA2_NPCS11 (AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_CANTX (AT91C_PIO_PA20) // CAN Transmit +#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_TF (AT91C_PIO_PA21) // SSC Transmit Frame Sync +#define AT91C_PA21_NPCS10 (AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 +#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TK (AT91C_PIO_PA22) // SSC Transmit Clock +#define AT91C_PA22_SPCK1 (AT91C_PIO_PA22) // SPI 1 Serial Clock +#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_TD (AT91C_PIO_PA23) // SSC Transmit data +#define AT91C_PA23_MOSI1 (AT91C_PIO_PA23) // SPI 1 Master Out Slave +#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RD (AT91C_PIO_PA24) // SSC Receive Data +#define AT91C_PA24_MISO1 (AT91C_PIO_PA24) // SPI 1 Master In Slave +#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_RK (AT91C_PIO_PA25) // SSC Receive Clock +#define AT91C_PA25_NPCS11 (AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_RF (AT91C_PIO_PA26) // SSC Receive Frame Sync +#define AT91C_PA26_NPCS12 (AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DRXD (AT91C_PIO_PA27) // DBGU Debug Receive Data +#define AT91C_PA27_PCK3 (AT91C_PIO_PA27) // PMC Programmable Clock Output 3 +#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DTXD (AT91C_PIO_PA28) // DBGU Debug Transmit Data +#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_FIQ (AT91C_PIO_PA29) // AIC Fast Interrupt Input +#define AT91C_PA29_NPCS13 (AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_RTS0 (AT91C_PIO_PA3) // USART 0 Ready To Send +#define AT91C_PA3_NPCS12 (AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ0 (AT91C_PIO_PA30) // External Interrupt 0 +#define AT91C_PA30_PCK2 (AT91C_PIO_PA30) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_CTS0 (AT91C_PIO_PA4) // USART 0 Clear To Send +#define AT91C_PA4_NPCS13 (AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD1 (AT91C_PIO_PA5) // USART 1 Receive Data +#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD1 (AT91C_PIO_PA6) // USART 1 Transmit Data +#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_SCK1 (AT91C_PIO_PA7) // USART 1 Serial Clock +#define AT91C_PA7_NPCS01 (AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_RTS1 (AT91C_PIO_PA8) // USART 1 Ready To Send +#define AT91C_PA8_NPCS02 (AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_CTS1 (AT91C_PIO_PA9) // USART 1 Clear To Send +#define AT91C_PA9_NPCS03 (AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0 +#define AT91C_PB0_ETXCK_EREFCK (AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock +#define AT91C_PB0_PCK0 (AT91C_PIO_PB0) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1 +#define AT91C_PB1_ETXEN (AT91C_PIO_PB1) // Ethernet MAC Transmit Enable +#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10 +#define AT91C_PB10_ETX2 (AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 +#define AT91C_PB10_NPCS11 (AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11 +#define AT91C_PB11_ETX3 (AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 +#define AT91C_PB11_NPCS12 (AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12 +#define AT91C_PB12_ETXER (AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error +#define AT91C_PB12_TCLK0 (AT91C_PIO_PB12) // Timer Counter 0 external clock input +#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13 +#define AT91C_PB13_ERX2 (AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 +#define AT91C_PB13_NPCS01 (AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14 +#define AT91C_PB14_ERX3 (AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 +#define AT91C_PB14_NPCS02 (AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15 +#define AT91C_PB15_ERXDV (AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid +#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16 +#define AT91C_PB16_ECOL (AT91C_PIO_PB16) // Ethernet MAC Collision Detected +#define AT91C_PB16_NPCS13 (AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17 +#define AT91C_PB17_ERXCK (AT91C_PIO_PB17) // Ethernet MAC Receive Clock +#define AT91C_PB17_NPCS03 (AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18 +#define AT91C_PB18_EF100 (AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec +#define AT91C_PB18_ADTRG (AT91C_PIO_PB18) // ADC External Trigger +#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19 +#define AT91C_PB19_PWM0 (AT91C_PIO_PB19) // PWM Channel 0 +#define AT91C_PB19_TCLK1 (AT91C_PIO_PB19) // Timer Counter 1 external clock input +#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2 +#define AT91C_PB2_ETX0 (AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 +#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20 +#define AT91C_PB20_PWM1 (AT91C_PIO_PB20) // PWM Channel 1 +#define AT91C_PB20_PCK0 (AT91C_PIO_PB20) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21 +#define AT91C_PB21_PWM2 (AT91C_PIO_PB21) // PWM Channel 2 +#define AT91C_PB21_PCK1 (AT91C_PIO_PB21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22 +#define AT91C_PB22_PWM3 (AT91C_PIO_PB22) // PWM Channel 3 +#define AT91C_PB22_PCK2 (AT91C_PIO_PB22) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23 +#define AT91C_PB23_TIOA0 (AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PB23_DCD1 (AT91C_PIO_PB23) // USART 1 Data Carrier Detect +#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24 +#define AT91C_PB24_TIOB0 (AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PB24_DSR1 (AT91C_PIO_PB24) // USART 1 Data Set ready +#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25 +#define AT91C_PB25_TIOA1 (AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PB25_DTR1 (AT91C_PIO_PB25) // USART 1 Data Terminal ready +#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26 +#define AT91C_PB26_TIOB1 (AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PB26_RI1 (AT91C_PIO_PB26) // USART 1 Ring Indicator +#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27 +#define AT91C_PB27_TIOA2 (AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PB27_PWM0 (AT91C_PIO_PB27) // PWM Channel 0 +#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28 +#define AT91C_PB28_TIOB2 (AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PB28_PWM1 (AT91C_PIO_PB28) // PWM Channel 1 +#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29 +#define AT91C_PB29_PCK1 (AT91C_PIO_PB29) // PMC Programmable Clock Output 1 +#define AT91C_PB29_PWM2 (AT91C_PIO_PB29) // PWM Channel 2 +#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3 +#define AT91C_PB3_ETX1 (AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 +#define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30 +#define AT91C_PB30_PCK2 (AT91C_PIO_PB30) // PMC Programmable Clock Output 2 +#define AT91C_PB30_PWM3 (AT91C_PIO_PB30) // PWM Channel 3 +#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4 +#define AT91C_PB4_ECRS_ECRSDV (AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid +#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5 +#define AT91C_PB5_ERX0 (AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 +#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6 +#define AT91C_PB6_ERX1 (AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 +#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7 +#define AT91C_PB7_ERXER (AT91C_PIO_PB7) // Ethernet MAC Receive Error +#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8 +#define AT91C_PB8_EMDC (AT91C_PIO_PB8) // Ethernet MAC Management Data Clock +#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9 +#define AT91C_PB9_EMDIO (AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ( 1) // System Peripheral +#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A +#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B +#define AT91C_ID_SPI0 ( 4) // Serial Peripheral Interface 0 +#define AT91C_ID_SPI1 ( 5) // Serial Peripheral Interface 1 +#define AT91C_ID_US0 ( 6) // USART 0 +#define AT91C_ID_US1 ( 7) // USART 1 +#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ( 9) // Two-Wire Interface +#define AT91C_ID_PWMC (10) // PWM Controller +#define AT91C_ID_UDP (11) // USB Device Port +#define AT91C_ID_TC0 (12) // Timer Counter 0 +#define AT91C_ID_TC1 (13) // Timer Counter 1 +#define AT91C_ID_TC2 (14) // Timer Counter 2 +#define AT91C_ID_CAN (15) // Control Area Network Controller +#define AT91C_ID_EMAC (16) // Ethernet MAC +#define AT91C_ID_ADC (17) // Analog-to-Digital Converter +#define AT91C_ID_AES (18) // Advanced Encryption Standard 128-bit +#define AT91C_ID_TDES (19) // Triple Data Encryption Standard +#define AT91C_ID_20_Reserved (20) // Reserved +#define AT91C_ID_21_Reserved (21) // Reserved +#define AT91C_ID_22_Reserved (22) // Reserved +#define AT91C_ID_23_Reserved (23) // Reserved +#define AT91C_ID_24_Reserved (24) // Reserved +#define AT91C_ID_25_Reserved (25) // Reserved +#define AT91C_ID_26_Reserved (26) // Reserved +#define AT91C_ID_27_Reserved (27) // Reserved +#define AT91C_ID_28_Reserved (28) // Reserved +#define AT91C_ID_29_Reserved (29) // Reserved +#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1) + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_BASE_SYS (0xFFFFF000) // (SYS) Base Address +#define AT91C_BASE_AIC (0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_PDC_DBGU (0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_DBGU (0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PIOA (0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_PIOB (0xFFFFF600) // (PIOB) Base Address +#define AT91C_BASE_CKGR (0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC (0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC (0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC (0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC (0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC (0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_VREG (0xFFFFFD60) // (VREG) Base Address +#define AT91C_BASE_MC (0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_PDC_SPI1 (0xFFFE4100) // (PDC_SPI1) Base Address +#define AT91C_BASE_SPI1 (0xFFFE4000) // (SPI1) Base Address +#define AT91C_BASE_PDC_SPI0 (0xFFFE0100) // (PDC_SPI0) Base Address +#define AT91C_BASE_SPI0 (0xFFFE0000) // (SPI0) Base Address +#define AT91C_BASE_PDC_US1 (0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 (0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 (0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_PDC_SSC (0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC (0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_TWI (0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_PWMC_CH3 (0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 (0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 (0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 (0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC (0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP (0xFFFB0000) // (UDP) Base Address +#define AT91C_BASE_TC0 (0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TC1 (0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC2 (0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TCB (0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_CAN_MB0 (0xFFFD0200) // (CAN_MB0) Base Address +#define AT91C_BASE_CAN_MB1 (0xFFFD0220) // (CAN_MB1) Base Address +#define AT91C_BASE_CAN_MB2 (0xFFFD0240) // (CAN_MB2) Base Address +#define AT91C_BASE_CAN_MB3 (0xFFFD0260) // (CAN_MB3) Base Address +#define AT91C_BASE_CAN_MB4 (0xFFFD0280) // (CAN_MB4) Base Address +#define AT91C_BASE_CAN_MB5 (0xFFFD02A0) // (CAN_MB5) Base Address +#define AT91C_BASE_CAN_MB6 (0xFFFD02C0) // (CAN_MB6) Base Address +#define AT91C_BASE_CAN_MB7 (0xFFFD02E0) // (CAN_MB7) Base Address +#define AT91C_BASE_CAN (0xFFFD0000) // (CAN) Base Address +#define AT91C_BASE_EMAC (0xFFFDC000) // (EMAC) Base Address +#define AT91C_BASE_PDC_ADC (0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC (0xFFFD8000) // (ADC) Base Address +#define AT91C_BASE_PDC_AES (0xFFFA4100) // (PDC_AES) Base Address +#define AT91C_BASE_AES (0xFFFA4000) // (AES) Base Address +#define AT91C_BASE_PDC_TDES (0xFFFA8100) // (PDC_TDES) Base Address +#define AT91C_BASE_TDES (0xFFFA8000) // (TDES) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_ISRAM (0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE (0x00010000) // Internal SRAM size in byte (64 Kbyte) +#define AT91C_IFLASH (0x00100000) // Internal ROM base address +#define AT91C_IFLASH_SIZE (0x00040000) // Internal ROM size in byte (256 Kbyte) + + diff --git a/20080212/Source/portable/IAR/AtmelSAM7S64/ISR_Support.h b/20080212/Source/portable/IAR/AtmelSAM7S64/ISR_Support.h new file mode 100644 index 000000000..4a32f3976 --- /dev/null +++ b/20080212/Source/portable/IAR/AtmelSAM7S64/ISR_Support.h @@ -0,0 +1,78 @@ + EXTERN pxCurrentTCB + EXTERN ulCriticalNesting + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Context save and restore macro definitions +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +portSAVE_CONTEXT MACRO + + ; Push R0 as we are going to use the register. + STMDB SP!, {R0} + + ; Set R0 to point to the task stack pointer. + STMDB SP, {SP}^ + NOP + SUB SP, SP, #4 + LDMIA SP!, {R0} + + ; Push the return address onto the stack. + STMDB R0!, {LR} + + ; Now we have saved LR we can use it instead of R0. + MOV LR, R0 + + ; Pop R0 so we can save it onto the system mode stack. + LDMIA SP!, {R0} + + ; Push all the system mode registers onto the task stack. + STMDB LR, {R0-LR}^ + NOP + SUB LR, LR, #60 + + ; Push the SPSR onto the task stack. + MRS R0, SPSR + STMDB LR!, {R0} + + LDR R0, =ulCriticalNesting + LDR R0, [R0] + STMDB LR!, {R0} + + ; Store the new top of stack for the task. + LDR R1, =pxCurrentTCB + LDR R0, [R1] + STR LR, [R0] + + ENDM + + +portRESTORE_CONTEXT MACRO + + ; Set the LR to the task stack. + LDR R1, =pxCurrentTCB + LDR R0, [R1] + LDR LR, [R0] + + ; The critical nesting depth is the first item on the stack. + ; Load it into the ulCriticalNesting variable. + LDR R0, =ulCriticalNesting + LDMFD LR!, {R1} + STR R1, [R0] + + ; Get the SPSR from the stack. + LDMFD LR!, {R0} + MSR SPSR_cxsf, R0 + + ; Restore all system mode registers for the task. + LDMFD LR, {R0-R14}^ + NOP + + ; Restore the return address. + LDR LR, [LR, #+60] + + ; And return - correcting the offset in the LR to obtain the + ; correct address. + SUBS PC, LR, #4 + + ENDM + diff --git a/20080212/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h b/20080212/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h new file mode 100644 index 000000000..9d012c4d7 --- /dev/null +++ b/20080212/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h @@ -0,0 +1,3265 @@ +//*---------------------------------------------------------------------------- +//* ATMEL Microcontroller Software Support - ROUSSET - +//*---------------------------------------------------------------------------- +//* The software is delivered "AS IS" without warranty or condition of any +//* kind, either express, implied or statutory. This includes without +//* limitation any warranty or condition with respect to merchantability or +//* fitness for any particular purpose, or against the infringements of +//* intellectual property rights of others. +//*---------------------------------------------------------------------------- +//* File Name : lib_AT91SAM7S64.h +//* Object : AT91SAM7S64 inlined functions +//* Generated : AT91 SW Application Group 07/16/2004 (07:43:09) +//* +//* CVS Reference : /lib_MC_SAM.h/1.3/Thu Mar 25 15:19:14 2004// +//* CVS Reference : /lib_pdc_1363d.h/1.2/Wed Feb 19 09:25:22 2003// +//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// +//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// +//* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 13:23:52 2003// +//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// +//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// +//* CVS Reference : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004// +//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 08:12:38 2003// +//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// +//* CVS Reference : /lib_twi.h/1.2/Fri Jan 31 12:19:38 2003// +//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// +//* CVS Reference : /lib_udp.h/1.3/Fri Jan 31 12:19:48 2003// +//* CVS Reference : /lib_aic.h/1.3/Fri Jul 12 07:46:12 2002// +//*---------------------------------------------------------------------------- + +#ifndef lib_AT91SAM7S64_H +#define lib_AT91SAM7S64_H + +/* ***************************************************************************** + SOFTWARE API FOR MC + ***************************************************************************** */ + +#define AT91C_MC_CORRECT_KEY ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_Remap +//* \brief Make Remap +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_Remap (void) // +{ + AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC; + + pMC->MC_RCR = AT91C_MC_RCB; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_CfgModeReg +//* \brief Configure the EFC Mode Register of the MC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_EFC_CfgModeReg ( + AT91PS_MC pMC, // pointer to a MC controller + unsigned int mode) // mode register +{ + // Write to the FMR register + pMC->MC_FMR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_GetModeReg +//* \brief Return MC EFC Mode Regsiter +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_GetModeReg( + AT91PS_MC pMC) // pointer to a MC controller +{ + return pMC->MC_FMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_ComputeFMCN +//* \brief Return MC EFC Mode Regsiter +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_ComputeFMCN( + int master_clock) // master clock in Hz +{ + return (master_clock/1000000 +2); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_PerformCmd +//* \brief Perform EFC Command +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_EFC_PerformCmd ( + AT91PS_MC pMC, // pointer to a MC controller + unsigned int transfer_cmd) +{ + pMC->MC_FCR = transfer_cmd; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_GetStatus +//* \brief Return MC EFC Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_GetStatus( + AT91PS_MC pMC) // pointer to a MC controller +{ + return pMC->MC_FSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_IsInterruptMasked +//* \brief Test if EFC MC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_IsInterruptMasked( + AT91PS_MC pMC, // \arg pointer to a MC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_MC_EFC_GetModeReg(pMC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_IsInterruptSet +//* \brief Test if EFC MC Interrupt is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_IsInterruptSet( + AT91PS_MC pMC, // \arg pointer to a MC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_MC_EFC_GetStatus(pMC) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR PDC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetNextRx +//* \brief Set the next receive transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetNextRx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be received + unsigned int bytes) // \arg number of bytes to be received +{ + pPDC->PDC_RNPR = (unsigned int) address; + pPDC->PDC_RNCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetNextTx +//* \brief Set the next transmit transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetNextTx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be transmitted + unsigned int bytes) // \arg number of bytes to be transmitted +{ + pPDC->PDC_TNPR = (unsigned int) address; + pPDC->PDC_TNCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetRx +//* \brief Set the receive transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetRx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be received + unsigned int bytes) // \arg number of bytes to be received +{ + pPDC->PDC_RPR = (unsigned int) address; + pPDC->PDC_RCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetTx +//* \brief Set the transmit transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetTx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be transmitted + unsigned int bytes) // \arg number of bytes to be transmitted +{ + pPDC->PDC_TPR = (unsigned int) address; + pPDC->PDC_TCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_EnableTx +//* \brief Enable transmit +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_EnableTx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_TXTEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_EnableRx +//* \brief Enable receive +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_EnableRx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_RXTEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_DisableTx +//* \brief Disable transmit +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_DisableTx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_TXTDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_DisableRx +//* \brief Disable receive +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_DisableRx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_RXTDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsTxEmpty +//* \brief Test if the current transfer descriptor has been sent +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_TCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsNextTxEmpty +//* \brief Test if the next transfer descriptor has been moved to the current td +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_TNCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsRxEmpty +//* \brief Test if the current transfer descriptor has been filled +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_RCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsNextRxEmpty +//* \brief Test if the next transfer descriptor has been moved to the current td +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_RNCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_Open +//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_Open ( + AT91PS_PDC pPDC) // \arg pointer to a PDC controller +{ + //* Disable the RX and TX PDC transfer requests + AT91F_PDC_DisableRx(pPDC); + AT91F_PDC_DisableTx(pPDC); + + //* Reset all Counter register Next buffer first + AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); + AT91F_PDC_SetTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetRx(pPDC, (char *) 0, 0); + + //* Enable the RX and TX PDC transfer requests + AT91F_PDC_EnableRx(pPDC); + AT91F_PDC_EnableTx(pPDC); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_Close +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_Close ( + AT91PS_PDC pPDC) // \arg pointer to a PDC controller +{ + //* Disable the RX and TX PDC transfer requests + AT91F_PDC_DisableRx(pPDC); + AT91F_PDC_DisableTx(pPDC); + + //* Reset all Counter register Next buffer first + AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); + AT91F_PDC_SetTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetRx(pPDC, (char *) 0, 0); + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SendFrame +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PDC_SendFrame( + AT91PS_PDC pPDC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + if (AT91F_PDC_IsTxEmpty(pPDC)) { + //* Buffer and next buffer can be initialized + AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer); + AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer); + return 2; + } + else if (AT91F_PDC_IsNextTxEmpty(pPDC)) { + //* Only one buffer can be initialized + AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer); + return 1; + } + else { + //* All buffer are in use... + return 0; + } +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_ReceiveFrame +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PDC_ReceiveFrame ( + AT91PS_PDC pPDC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + if (AT91F_PDC_IsRxEmpty(pPDC)) { + //* Buffer and next buffer can be initialized + AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer); + AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer); + return 2; + } + else if (AT91F_PDC_IsNextRxEmpty(pPDC)) { + //* Only one buffer can be initialized + AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer); + return 1; + } + else { + //* All buffer are in use... + return 0; + } +} +/* ***************************************************************************** + SOFTWARE API FOR DBGU + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_InterruptEnable +//* \brief Enable DBGU Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_InterruptEnable( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg dbgu interrupt to be enabled +{ + pDbgu->DBGU_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_InterruptDisable +//* \brief Disable DBGU Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_InterruptDisable( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg dbgu interrupt to be disabled +{ + pDbgu->DBGU_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_GetInterruptMaskStatus +//* \brief Return DBGU Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status + AT91PS_DBGU pDbgu) // \arg pointer to a DBGU controller +{ + return pDbgu->DBGU_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_IsInterruptMasked +//* \brief Test if DBGU Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_DBGU_IsInterruptMasked( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR SSC + ***************************************************************************** */ +//* Define the standard I2S mode configuration + +//* Configuration to set in the SSC Transmit Clock Mode Register +//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits +//* nb_slot_by_frame : number of channels +#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ + AT91C_SSC_CKS_DIV +\ + AT91C_SSC_CKO_CONTINOUS +\ + AT91C_SSC_CKG_NONE +\ + AT91C_SSC_START_FALL_RF +\ + AT91C_SSC_STTOUT +\ + ((1<<16) & AT91C_SSC_STTDLY) +\ + ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24)) + + +//* Configuration to set in the SSC Transmit Frame Mode Register +//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits +//* nb_slot_by_frame : number of channels +#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ + (nb_bit_by_slot-1) +\ + AT91C_SSC_MSBF +\ + (((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB) +\ + (((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\ + AT91C_SSC_FSOS_NEGATIVE) + + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_SetBaudrate +//* \brief Set the baudrate according to the CPU clock +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_SetBaudrate ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int mainClock, // \arg peripheral clock + unsigned int speed) // \arg SSC baudrate +{ + unsigned int baud_value; + //* Define the baud rate divisor register + if (speed == 0) + baud_value = 0; + else + { + baud_value = (unsigned int) (mainClock * 10)/(2*speed); + if ((baud_value % 10) >= 5) + baud_value = (baud_value / 10) + 1; + else + baud_value /= 10; + } + + pSSC->SSC_CMR = baud_value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_Configure +//* \brief Configure SSC +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_Configure ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int syst_clock, // \arg System Clock Frequency + unsigned int baud_rate, // \arg Expected Baud Rate Frequency + unsigned int clock_rx, // \arg Receiver Clock Parameters + unsigned int mode_rx, // \arg mode Register to be programmed + unsigned int clock_tx, // \arg Transmitter Clock Parameters + unsigned int mode_tx) // \arg mode Register to be programmed +{ + //* Disable interrupts + pSSC->SSC_IDR = (unsigned int) -1; + + //* Reset receiver and transmitter + pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ; + + //* Define the Clock Mode Register + AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate); + + //* Write the Receive Clock Mode Register + pSSC->SSC_RCMR = clock_rx; + + //* Write the Transmit Clock Mode Register + pSSC->SSC_TCMR = clock_tx; + + //* Write the Receive Frame Mode Register + pSSC->SSC_RFMR = mode_rx; + + //* Write the Transmit Frame Mode Register + pSSC->SSC_TFMR = mode_tx; + + //* Clear Transmit and Receive Counters + AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR)); + + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableRx +//* \brief Enable receiving datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_EnableRx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Enable receiver + pSSC->SSC_CR = AT91C_SSC_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableRx +//* \brief Disable receiving datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_DisableRx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Disable receiver + pSSC->SSC_CR = AT91C_SSC_RXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableTx +//* \brief Enable sending datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_EnableTx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Enable transmitter + pSSC->SSC_CR = AT91C_SSC_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableTx +//* \brief Disable sending datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_DisableTx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Disable transmitter + pSSC->SSC_CR = AT91C_SSC_TXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableIt +//* \brief Enable SSC IT +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_EnableIt ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pSSC->SSC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableIt +//* \brief Disable SSC IT +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_DisableIt ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pSSC->SSC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SSC_ReceiveFrame ( + AT91PS_SSC pSSC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pSSC->SSC_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SSC_SendFrame( + AT91PS_SSC pSSC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pSSC->SSC_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_GetInterruptMaskStatus +//* \brief Return SSC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status + AT91PS_SSC pSsc) // \arg pointer to a SSC controller +{ + return pSsc->SSC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_IsInterruptMasked +//* \brief Test if SSC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_SSC_IsInterruptMasked( + AT91PS_SSC pSsc, // \arg pointer to a SSC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR SPI + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Open +//* \brief Open a SPI Port +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_Open ( + const unsigned int null) // \arg +{ + /* NOT DEFINED AT THIS MOMENT */ + return ( 0 ); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgCs +//* \brief Configure SPI chip select register +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgCs ( + AT91PS_SPI pSPI, // pointer to a SPI controller + int cs, // SPI cs number (0 to 3) + int val) // chip select register +{ + //* Write to the CSR register + *(pSPI->SPI_CSR + cs) = val; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_EnableIt +//* \brief Enable SPI interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_EnableIt ( + AT91PS_SPI pSPI, // pointer to a SPI controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pSPI->SPI_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_DisableIt +//* \brief Disable SPI interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_DisableIt ( + AT91PS_SPI pSPI, // pointer to a SPI controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pSPI->SPI_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Reset +//* \brief Reset the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Reset ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Enable +//* \brief Enable the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Enable ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SPIEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Disable +//* \brief Disable the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Disable ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SPIDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgMode +//* \brief Enable the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgMode ( + AT91PS_SPI pSPI, // pointer to a SPI controller + int mode) // mode register +{ + //* Write to the MR register + pSPI->SPI_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgPCS +//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgPCS ( + AT91PS_SPI pSPI, // pointer to a SPI controller + char PCS_Device) // PCS of the Device +{ + //* Write to the MR register + pSPI->SPI_MR &= 0xFFF0FFFF; + pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS ); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_ReceiveFrame ( + AT91PS_SPI pSPI, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pSPI->SPI_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_SendFrame( + AT91PS_SPI pSPI, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pSPI->SPI_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Close +//* \brief Close SPI: disable IT disable transfert, close PDC +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Close ( + AT91PS_SPI pSPI) // \arg pointer to a SPI controller +{ + //* Reset all the Chip Select register + pSPI->SPI_CSR[0] = 0 ; + pSPI->SPI_CSR[1] = 0 ; + pSPI->SPI_CSR[2] = 0 ; + pSPI->SPI_CSR[3] = 0 ; + + //* Reset the SPI mode + pSPI->SPI_MR = 0 ; + + //* Disable all interrupts + pSPI->SPI_IDR = 0xFFFFFFFF ; + + //* Abort the Peripheral Data Transfers + AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR)); + + //* Disable receiver and transmitter and stop any activity immediately + pSPI->SPI_CR = AT91C_SPI_SPIDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_PutChar +//* \brief Send a character,does not check if ready to send +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_PutChar ( + AT91PS_SPI pSPI, + unsigned int character, + unsigned int cs_number ) +{ + unsigned int value_for_cs; + value_for_cs = (~(1 << cs_number)) & 0xF; //Place a zero among a 4 ONEs number + pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_GetChar +//* \brief Receive a character,does not check if a character is available +//*---------------------------------------------------------------------------- +__inline int AT91F_SPI_GetChar ( + const AT91PS_SPI pSPI) +{ + return((pSPI->SPI_RDR) & 0xFFFF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_GetInterruptMaskStatus +//* \brief Return SPI Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status + AT91PS_SPI pSpi) // \arg pointer to a SPI controller +{ + return pSpi->SPI_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_IsInterruptMasked +//* \brief Test if SPI Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_SPI_IsInterruptMasked( + AT91PS_SPI pSpi, // \arg pointer to a SPI controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR PWMC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_GetStatus +//* \brief Return PWM Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status + AT91PS_PWMC pPWM) // pointer to a PWM controller +{ + return pPWM->PWMC_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_InterruptEnable +//* \brief Enable PWM Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_InterruptEnable( + AT91PS_PWMC pPwm, // \arg pointer to a PWM controller + unsigned int flag) // \arg PWM interrupt to be enabled +{ + pPwm->PWMC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_InterruptDisable +//* \brief Disable PWM Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_InterruptDisable( + AT91PS_PWMC pPwm, // \arg pointer to a PWM controller + unsigned int flag) // \arg PWM interrupt to be disabled +{ + pPwm->PWMC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_GetInterruptMaskStatus +//* \brief Return PWM Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status + AT91PS_PWMC pPwm) // \arg pointer to a PWM controller +{ + return pPwm->PWMC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_IsInterruptMasked +//* \brief Test if PWM Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_IsInterruptMasked( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_IsStatusSet +//* \brief Test if PWM Interrupt is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_IsStatusSet( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PWMC_GetStatus(pPWM) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_CfgChannel +//* \brief Test if PWM Interrupt is Set +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CfgChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int channelId, // \arg PWM channel ID + unsigned int mode, // \arg PWM mode + unsigned int period, // \arg PWM period + unsigned int duty) // \arg PWM duty cycle +{ + pPWM->PWMC_CH[channelId].PWMC_CMR = mode; + pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty; + pPWM->PWMC_CH[channelId].PWMC_CPRDR = period; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_StartChannel +//* \brief Enable channel +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_StartChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg Channels IDs to be enabled +{ + pPWM->PWMC_ENA = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_StopChannel +//* \brief Disable channel +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_StopChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg Channels IDs to be enabled +{ + pPWM->PWMC_DIS = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_UpdateChannel +//* \brief Update Period or Duty Cycle +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_UpdateChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int channelId, // \arg PWM channel ID + unsigned int update) // \arg Channels IDs to be enabled +{ + pPWM->PWMC_CH[channelId].PWMC_CUPDR = update; +} + +/* ***************************************************************************** + SOFTWARE API FOR TC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_InterruptEnable +//* \brief Enable TC Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TC_InterruptEnable( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg TC interrupt to be enabled +{ + pTc->TC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_InterruptDisable +//* \brief Disable TC Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TC_InterruptDisable( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg TC interrupt to be disabled +{ + pTc->TC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_GetInterruptMaskStatus +//* \brief Return TC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status + AT91PS_TC pTc) // \arg pointer to a TC controller +{ + return pTc->TC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_IsInterruptMasked +//* \brief Test if TC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_TC_IsInterruptMasked( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR PMC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgSysClkEnableReg +//* \brief Configure the System Clock Enable Register of the PMC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgSysClkEnableReg ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int mode) +{ + //* Write to the SCER register + pPMC->PMC_SCER = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgSysClkDisableReg +//* \brief Configure the System Clock Disable Register of the PMC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgSysClkDisableReg ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int mode) +{ + //* Write to the SCDR register + pPMC->PMC_SCDR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetSysClkStatusReg +//* \brief Return the System Clock Status Register of the PMC controller +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetSysClkStatusReg ( + AT91PS_PMC pPMC // pointer to a CAN controller + ) +{ + return pPMC->PMC_SCSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnablePeriphClock +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_EnablePeriphClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int periphIds) // \arg IDs of peripherals to enable +{ + pPMC->PMC_PCER = periphIds; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisablePeriphClock +//* \brief Disable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_DisablePeriphClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int periphIds) // \arg IDs of peripherals to enable +{ + pPMC->PMC_PCDR = periphIds; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetPeriphClock +//* \brief Get peripheral clock status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetPeriphClock ( + AT91PS_PMC pPMC) // \arg pointer to PMC controller +{ + return pPMC->PMC_PCSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_CfgMainOscillatorReg +//* \brief Cfg the main oscillator +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_CfgMainOscillatorReg ( + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int mode) +{ + pCKGR->CKGR_MOR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_GetMainOscillatorReg +//* \brief Cfg the main oscillator +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CKGR_GetMainOscillatorReg ( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + return pCKGR->CKGR_MOR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_EnableMainOscillator +//* \brief Enable the main oscillator +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_EnableMainOscillator( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_DisableMainOscillator +//* \brief Disable the main oscillator +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_DisableMainOscillator ( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_CfgMainOscStartUpTime +//* \brief Cfg MOR Register according to the main osc startup time +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_CfgMainOscStartUpTime ( + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int startup_time, // \arg main osc startup time in microsecond (us) + unsigned int slowClock) // \arg slowClock in Hz +{ + pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT; + pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_GetMainClockFreqReg +//* \brief Cfg the main oscillator +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CKGR_GetMainClockFreqReg ( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + return pCKGR->CKGR_MCFR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_GetMainClock +//* \brief Return Main clock in Hz +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CKGR_GetMainClock ( + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int slowClock) // \arg slowClock in Hz +{ + return ((pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF) * slowClock) >> 4; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgMCKReg +//* \brief Cfg Master Clock Register +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgMCKReg ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int mode) +{ + pPMC->PMC_MCKR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetMCKReg +//* \brief Return Master Clock Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetMCKReg( + AT91PS_PMC pPMC) // \arg pointer to PMC controller +{ + return pPMC->PMC_MCKR; +} + +//*------------------------------------------------------------------------------ +//* \fn AT91F_PMC_GetMasterClock +//* \brief Return master clock in Hz which correponds to processor clock for ARM7 +//*------------------------------------------------------------------------------ +__inline unsigned int AT91F_PMC_GetMasterClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int slowClock) // \arg slowClock in Hz +{ + unsigned int reg = pPMC->PMC_MCKR; + unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2)); + unsigned int pllDivider, pllMultiplier; + + switch (reg & AT91C_PMC_CSS) { + case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected + return slowClock / prescaler; + case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected + return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler; + case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected + reg = pCKGR->CKGR_PLLR; + pllDivider = (reg & AT91C_CKGR_DIV); + pllMultiplier = ((reg & AT91C_CKGR_MUL) >> 16) + 1; + return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler; + } + return 0; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnablePCK +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_EnablePCK ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int pck, // \arg Peripheral clock identifier 0 .. 7 + unsigned int mode) +{ + pPMC->PMC_PCKR[pck] = mode; + pPMC->PMC_SCER = (1 << pck) << 8; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisablePCK +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_DisablePCK ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int pck) // \arg Peripheral clock identifier 0 .. 7 +{ + pPMC->PMC_SCDR = (1 << pck) << 8; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnableIt +//* \brief Enable PMC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_EnableIt ( + AT91PS_PMC pPMC, // pointer to a PMC controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pPMC->PMC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisableIt +//* \brief Disable PMC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_DisableIt ( + AT91PS_PMC pPMC, // pointer to a PMC controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pPMC->PMC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetStatus +//* \brief Return PMC Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status + AT91PS_PMC pPMC) // pointer to a PMC controller +{ + return pPMC->PMC_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetInterruptMaskStatus +//* \brief Return PMC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status + AT91PS_PMC pPMC) // pointer to a PMC controller +{ + return pPMC->PMC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_IsInterruptMasked +//* \brief Test if PMC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_IsInterruptMasked( + AT91PS_PMC pPMC, // \arg pointer to a PMC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_IsStatusSet +//* \brief Test if PMC Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_IsStatusSet( + AT91PS_PMC pPMC, // \arg pointer to a PMC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PMC_GetStatus(pPMC) & flag); +}/* ***************************************************************************** + SOFTWARE API FOR ADC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_EnableIt +//* \brief Enable ADC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_EnableIt ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pADC->ADC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_DisableIt +//* \brief Disable ADC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_DisableIt ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pADC->ADC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetStatus +//* \brief Return ADC Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status + AT91PS_ADC pADC) // pointer to a ADC controller +{ + return pADC->ADC_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetInterruptMaskStatus +//* \brief Return ADC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status + AT91PS_ADC pADC) // pointer to a ADC controller +{ + return pADC->ADC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_IsInterruptMasked +//* \brief Test if ADC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_IsInterruptMasked( + AT91PS_ADC pADC, // \arg pointer to a ADC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_IsStatusSet +//* \brief Test if ADC Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_IsStatusSet( + AT91PS_ADC pADC, // \arg pointer to a ADC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_ADC_GetStatus(pADC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgModeReg +//* \brief Configure the Mode Register of the ADC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgModeReg ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int mode) // mode register +{ + //* Write to the MR register + pADC->ADC_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetModeReg +//* \brief Return the Mode Register of the ADC controller value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetModeReg ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_MR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgTimings +//* \brief Configure the different necessary timings of the ADC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgTimings ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int mck_clock, // in MHz + unsigned int adc_clock, // in MHz + unsigned int startup_time, // in us + unsigned int sample_and_hold_time) // in ns +{ + unsigned int prescal,startup,shtim; + + prescal = mck_clock/(2*adc_clock) - 1; + startup = adc_clock*startup_time/8 - 1; + shtim = adc_clock*sample_and_hold_time/1000 - 1; + + //* Write to the MR register + pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_EnableChannel +//* \brief Return ADC Timer Register Value +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_EnableChannel ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int channel) // mode register +{ + //* Write to the CHER register + pADC->ADC_CHER = channel; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_DisableChannel +//* \brief Return ADC Timer Register Value +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_DisableChannel ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int channel) // mode register +{ + //* Write to the CHDR register + pADC->ADC_CHDR = channel; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetChannelStatus +//* \brief Return ADC Timer Register Value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetChannelStatus ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CHSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_StartConversion +//* \brief Software request for a analog to digital conversion +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_StartConversion ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + pADC->ADC_CR = AT91C_ADC_START; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_SoftReset +//* \brief Software reset +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_SoftReset ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + pADC->ADC_CR = AT91C_ADC_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetLastConvertedData +//* \brief Return the Last Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetLastConvertedData ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_LCDR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH0 +//* \brief Return the Channel 0 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH0 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR0; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH1 +//* \brief Return the Channel 1 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH1 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR1; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH2 +//* \brief Return the Channel 2 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH2 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR2; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH3 +//* \brief Return the Channel 3 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH3 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR3; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH4 +//* \brief Return the Channel 4 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH4 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR4; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH5 +//* \brief Return the Channel 5 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH5 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR5; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH6 +//* \brief Return the Channel 6 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH6 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR6; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH7 +//* \brief Return the Channel 7 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH7 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR7; +} + +/* ***************************************************************************** + SOFTWARE API FOR PIO + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgPeriph +//* \brief Enable pins to be drived by peripheral +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgPeriph( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int periphAEnable, // \arg PERIPH A to enable + unsigned int periphBEnable) // \arg PERIPH B to enable + +{ + pPio->PIO_ASR = periphAEnable; + pPio->PIO_BSR = periphBEnable; + pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgOutput +//* \brief Enable PIO in output mode +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int pioEnable) // \arg PIO to be enabled +{ + pPio->PIO_PER = pioEnable; // Set in PIO mode + pPio->PIO_OER = pioEnable; // Configure in Output +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgInput +//* \brief Enable PIO in input mode +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgInput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int inputEnable) // \arg PIO to be enabled +{ + // Disable output + pPio->PIO_ODR = inputEnable; + pPio->PIO_PER = inputEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgOpendrain +//* \brief Configure PIO in open drain +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgOpendrain( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int multiDrvEnable) // \arg pio to be configured in open drain +{ + // Configure the multi-drive option + pPio->PIO_MDDR = ~multiDrvEnable; + pPio->PIO_MDER = multiDrvEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgPullup +//* \brief Enable pullup on PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgPullup( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int pullupEnable) // \arg enable pullup on PIO +{ + // Connect or not Pullup + pPio->PIO_PPUDR = ~pullupEnable; + pPio->PIO_PPUER = pullupEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgDirectDrive +//* \brief Enable direct drive on PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgDirectDrive( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int directDrive) // \arg PIO to be configured with direct drive + +{ + // Configure the Direct Drive + pPio->PIO_OWDR = ~directDrive; + pPio->PIO_OWER = directDrive; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgInputFilter +//* \brief Enable input filter on input PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgInputFilter( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int inputFilter) // \arg PIO to be configured with input filter + +{ + // Configure the Direct Drive + pPio->PIO_IFDR = ~inputFilter; + pPio->PIO_IFER = inputFilter; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInput +//* \brief Return PIO input value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInput( // \return PIO input + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PDSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInputSet +//* \brief Test if PIO is input flag is active +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInputSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInput(pPio) & flag); +} + + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_SetOutput +//* \brief Set to 1 output PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_SetOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be set +{ + pPio->PIO_SODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_ClearOutput +//* \brief Set to 0 output PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_ClearOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be cleared +{ + pPio->PIO_CODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_ForceOutput +//* \brief Force output when Direct drive option is enabled +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_ForceOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be forced +{ + pPio->PIO_ODSR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Enable +//* \brief Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_Enable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be enabled +{ + pPio->PIO_PER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Disable +//* \brief Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_Disable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be disabled +{ + pPio->PIO_PDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetStatus +//* \brief Return PIO Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsSet +//* \brief Test if PIO is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputEnable +//* \brief Output Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output to be enabled +{ + pPio->PIO_OER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputDisable +//* \brief Output Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output to be disabled +{ + pPio->PIO_ODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputStatus +//* \brief Return PIO Output Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_OSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOuputSet +//* \brief Test if PIO Output is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsOutputSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InputFilterEnable +//* \brief Input Filter Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InputFilterEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio input filter to be enabled +{ + pPio->PIO_IFER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InputFilterDisable +//* \brief Input Filter Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InputFilterDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio input filter to be disabled +{ + pPio->PIO_IFDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInputFilterStatus +//* \brief Return PIO Input Filter Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_IFSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInputFilterSet +//* \brief Test if PIO Input filter is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInputFilterSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInputFilterStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputDataStatus +//* \brief Return PIO Output Data Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ODSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InterruptEnable +//* \brief Enable PIO Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InterruptEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio interrupt to be enabled +{ + pPio->PIO_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InterruptDisable +//* \brief Disable PIO Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InterruptDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio interrupt to be disabled +{ + pPio->PIO_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInterruptMaskStatus +//* \brief Return PIO Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInterruptStatus +//* \brief Return PIO Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ISR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInterruptMasked +//* \brief Test if PIO Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInterruptMasked( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInterruptSet +//* \brief Test if PIO Interrupt is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInterruptSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInterruptStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_MultiDriverEnable +//* \brief Multi Driver Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_MultiDriverEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be enabled +{ + pPio->PIO_MDER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_MultiDriverDisable +//* \brief Multi Driver Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_MultiDriverDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be disabled +{ + pPio->PIO_MDDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetMultiDriverStatus +//* \brief Return PIO Multi Driver Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_MDSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsMultiDriverSet +//* \brief Test if PIO MultiDriver is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsMultiDriverSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_A_RegisterSelection +//* \brief PIO A Register Selection +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_A_RegisterSelection( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio A register selection +{ + pPio->PIO_ASR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_B_RegisterSelection +//* \brief PIO B Register Selection +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_B_RegisterSelection( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio B register selection +{ + pPio->PIO_BSR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Get_AB_RegisterStatus +//* \brief Return PIO Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ABSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsAB_RegisterSet +//* \brief Test if PIO AB Register is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsAB_RegisterSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputWriteEnable +//* \brief Output Write Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputWriteEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output write to be enabled +{ + pPio->PIO_OWER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputWriteDisable +//* \brief Output Write Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputWriteDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output write to be disabled +{ + pPio->PIO_OWDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputWriteStatus +//* \brief Return PIO Output Write Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_OWSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOutputWriteSet +//* \brief Test if PIO OutputWrite is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsOutputWriteSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetCfgPullup +//* \brief Return PIO Configuration Pullup +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PPUSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOutputDataStatusSet +//* \brief Test if PIO Output Data Status is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsOutputDataStatusSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputDataStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsCfgPullupStatusSet +//* \brief Test if PIO Configuration Pullup Status is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsCfgPullupStatusSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (~AT91F_PIO_GetCfgPullup(pPio) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR TWI + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_EnableIt +//* \brief Enable TWI IT +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_EnableIt ( + AT91PS_TWI pTWI, // \arg pointer to a TWI controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pTWI->TWI_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_DisableIt +//* \brief Disable TWI IT +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_DisableIt ( + AT91PS_TWI pTWI, // \arg pointer to a TWI controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pTWI->TWI_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_Configure +//* \brief Configure TWI in master mode +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI ) // \arg pointer to a TWI controller +{ + //* Disable interrupts + pTWI->TWI_IDR = (unsigned int) -1; + + //* Reset peripheral + pTWI->TWI_CR = AT91C_TWI_SWRST; + + //* Set Master mode + pTWI->TWI_CR = AT91C_TWI_MSEN | AT91C_TWI_SVDIS; + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_GetInterruptMaskStatus +//* \brief Return TWI Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status + AT91PS_TWI pTwi) // \arg pointer to a TWI controller +{ + return pTwi->TWI_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_IsInterruptMasked +//* \brief Test if TWI Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_TWI_IsInterruptMasked( + AT91PS_TWI pTwi, // \arg pointer to a TWI controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR USART + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Baudrate +//* \brief Calculate the baudrate +//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_EXT ) + +//* Standard Synchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \ + AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//* SCK used Label +#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT) + +//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity +#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \ + AT91C_US_CLKS_CLOCK +\ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_EVEN + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CKLO +\ + AT91C_US_OVER) + +//* Standard IRDA mode +#define AT91C_US_ASYNC_IRDA_MODE ( AT91C_US_USMODE_IRDA + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Baudrate +//* \brief Caluculate baud_value according to the main clock and the baud rate +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_Baudrate ( + const unsigned int main_clock, // \arg peripheral clock + const unsigned int baud_rate) // \arg UART baudrate +{ + unsigned int baud_value = ((main_clock*10)/(baud_rate * 16)); + if ((baud_value % 10) >= 5) + baud_value = (baud_value / 10) + 1; + else + baud_value /= 10; + return baud_value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetBaudrate +//* \brief Set the baudrate according to the CPU clock +//*---------------------------------------------------------------------------- +__inline void AT91F_US_SetBaudrate ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int mainClock, // \arg peripheral clock + unsigned int speed) // \arg UART baudrate +{ + //* Define the baud rate divisor register + pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetTimeguard +//* \brief Set USART timeguard +//*---------------------------------------------------------------------------- +__inline void AT91F_US_SetTimeguard ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int timeguard) // \arg timeguard value +{ + //* Write the Timeguard Register + pUSART->US_TTGR = timeguard ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableIt +//* \brief Enable USART IT +//*---------------------------------------------------------------------------- +__inline void AT91F_US_EnableIt ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pUSART->US_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableIt +//* \brief Disable USART IT +//*---------------------------------------------------------------------------- +__inline void AT91F_US_DisableIt ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IER register + pUSART->US_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Configure +//* \brief Configure USART +//*---------------------------------------------------------------------------- +__inline void AT91F_US_Configure ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int mainClock, // \arg peripheral clock + unsigned int mode , // \arg mode Register to be programmed + unsigned int baudRate , // \arg baudrate to be programmed + unsigned int timeguard ) // \arg timeguard to be programmed +{ + //* Disable interrupts + pUSART->US_IDR = (unsigned int) -1; + + //* Reset receiver and transmitter + pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ; + + //* Define the baud rate divisor register + AT91F_US_SetBaudrate(pUSART, mainClock, baudRate); + + //* Write the Timeguard Register + AT91F_US_SetTimeguard(pUSART, timeguard); + + //* Clear Transmit and Receive Counters + AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR)); + + //* Define the USART mode + pUSART->US_MR = mode ; + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableRx +//* \brief Enable receiving characters +//*---------------------------------------------------------------------------- +__inline void AT91F_US_EnableRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Enable receiver + pUSART->US_CR = AT91C_US_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableTx +//* \brief Enable sending characters +//*---------------------------------------------------------------------------- +__inline void AT91F_US_EnableTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Enable transmitter + pUSART->US_CR = AT91C_US_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ResetRx +//* \brief Reset Receiver and re-enable it +//*---------------------------------------------------------------------------- +__inline void AT91F_US_ResetRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset receiver + pUSART->US_CR = AT91C_US_RSTRX; + //* Re-Enable receiver + pUSART->US_CR = AT91C_US_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ResetTx +//* \brief Reset Transmitter and re-enable it +//*---------------------------------------------------------------------------- +__inline void AT91F_US_ResetTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset transmitter + pUSART->US_CR = AT91C_US_RSTTX; + //* Enable transmitter + pUSART->US_CR = AT91C_US_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableRx +//* \brief Disable Receiver +//*---------------------------------------------------------------------------- +__inline void AT91F_US_DisableRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Disable receiver + pUSART->US_CR = AT91C_US_RXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableTx +//* \brief Disable Transmitter +//*---------------------------------------------------------------------------- +__inline void AT91F_US_DisableTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Disable transmitter + pUSART->US_CR = AT91C_US_TXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Close +//* \brief Close USART: disable IT disable receiver and transmitter, close PDC +//*---------------------------------------------------------------------------- +__inline void AT91F_US_Close ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset the baud rate divisor register + pUSART->US_BRGR = 0 ; + + //* Reset the USART mode + pUSART->US_MR = 0 ; + + //* Reset the Timeguard Register + pUSART->US_TTGR = 0; + + //* Disable all interrupts + pUSART->US_IDR = 0xFFFFFFFF ; + + //* Abort the Peripheral Data Transfers + AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR)); + + //* Disable receiver and transmitter and stop any activity immediately + pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_TxReady +//* \brief Return 1 if a character can be written in US_THR +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_TxReady ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & AT91C_US_TXRDY); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_RxReady +//* \brief Return 1 if a character can be read in US_RHR +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_RxReady ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & AT91C_US_RXRDY); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Error +//* \brief Return the error flag +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_Error ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & + (AT91C_US_OVRE | // Overrun error + AT91C_US_FRAME | // Framing error + AT91C_US_PARE)); // Parity error +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_PutChar +//* \brief Send a character,does not check if ready to send +//*---------------------------------------------------------------------------- +__inline void AT91F_US_PutChar ( + AT91PS_USART pUSART, + int character ) +{ + pUSART->US_THR = (character & 0x1FF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_GetChar +//* \brief Receive a character,does not check if a character is available +//*---------------------------------------------------------------------------- +__inline int AT91F_US_GetChar ( + const AT91PS_USART pUSART) +{ + return((pUSART->US_RHR) & 0x1FF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_SendFrame( + AT91PS_USART pUSART, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pUSART->US_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_ReceiveFrame ( + AT91PS_USART pUSART, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pUSART->US_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetIrdaFilter +//* \brief Set the value of IrDa filter tregister +//*---------------------------------------------------------------------------- +__inline void AT91F_US_SetIrdaFilter ( + AT91PS_USART pUSART, + unsigned char value +) +{ + pUSART->US_IF = value; +} + +/* ***************************************************************************** + SOFTWARE API FOR UDP + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EnableIt +//* \brief Enable UDP IT +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EnableIt ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pUDP->UDP_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_DisableIt +//* \brief Disable UDP IT +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_DisableIt ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pUDP->UDP_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_SetAddress +//* \brief Set UDP functional address +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_SetAddress ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char address) // \arg new UDP address +{ + pUDP->UDP_FADDR = (AT91C_UDP_FEN | address); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EnableEp +//* \brief Enable Endpoint +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EnableEp ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg endpoints to be enabled +{ + pUDP->UDP_GLBSTATE |= flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_DisableEp +//* \brief Enable Endpoint +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_DisableEp ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg endpoints to be enabled +{ + pUDP->UDP_GLBSTATE &= ~(flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_SetState +//* \brief Set UDP Device state +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_SetState ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg new UDP address +{ + pUDP->UDP_GLBSTATE &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG); + pUDP->UDP_GLBSTATE |= flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_GetState +//* \brief return UDP Device state +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state + AT91PS_UDP pUDP) // \arg pointer to a UDP controller +{ + return (pUDP->UDP_GLBSTATE & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_ResetEp +//* \brief Reset UDP endpoint +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_ResetEp ( // \return the UDP device state + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg Endpoints to be reset +{ + pUDP->UDP_RSTEP = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpStall +//* \brief Endpoint will STALL requests +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpStall( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpWrite +//* \brief Write value in the DPR +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpWrite( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned char value) // \arg value to be written in the DPR +{ + pUDP->UDP_FDR[endpoint] = value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpRead +//* \brief Return value from the DPR +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_EpRead( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + return pUDP->UDP_FDR[endpoint]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpEndOfWr +//* \brief Notify the UDP that values in DPR are ready to be sent +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpEndOfWr( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpClear +//* \brief Clear flag in the endpoint CSR register +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpClear( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned int flag) // \arg flag to be cleared +{ + pUDP->UDP_CSR[endpoint] &= ~(flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpSet +//* \brief Set flag in the endpoint CSR register +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpSet( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned int flag) // \arg flag to be cleared +{ + pUDP->UDP_CSR[endpoint] |= flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpStatus +//* \brief Return the endpoint CSR register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_EpStatus( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + return pUDP->UDP_CSR[endpoint]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_GetInterruptMaskStatus +//* \brief Return UDP Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status + AT91PS_UDP pUdp) // \arg pointer to a UDP controller +{ + return pUdp->UDP_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_IsInterruptMasked +//* \brief Test if UDP Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_UDP_IsInterruptMasked( + AT91PS_UDP pUdp, // \arg pointer to a UDP controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR AIC + ***************************************************************************** */ +#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20] + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_ConfigureIt +//* \brief Interrupt Handler Initialization +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_ConfigureIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id, // \arg interrupt number to initialize + unsigned int priority, // \arg priority to give to the interrupt + unsigned int src_type, // \arg activation and sense of activation + void (*newHandler) (void) ) // \arg address of the interrupt handler +{ + unsigned int oldHandler; + unsigned int mask ; + + oldHandler = pAic->AIC_SVR[irq_id]; + + mask = 0x1 << irq_id ; + //* Disable the interrupt on the interrupt controller + pAic->AIC_IDCR = mask ; + //* Save the interrupt handler routine pointer and the interrupt priority + pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ; + //* Store the Source Mode Register + pAic->AIC_SMR[irq_id] = src_type | priority ; + //* Clear the interrupt on the interrupt controller + pAic->AIC_ICCR = mask ; + + return oldHandler; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_EnableIt +//* \brief Enable corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_EnableIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id ) // \arg interrupt number to initialize +{ + //* Enable the interrupt on the interrupt controller + pAic->AIC_IECR = 0x1 << irq_id ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_DisableIt +//* \brief Disable corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_DisableIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id ) // \arg interrupt number to initialize +{ + unsigned int mask = 0x1 << irq_id; + //* Disable the interrupt on the interrupt controller + pAic->AIC_IDCR = mask ; + //* Clear the interrupt on the Interrupt Controller ( if one is pending ) + pAic->AIC_ICCR = mask ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_ClearIt +//* \brief Clear corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_ClearIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg interrupt number to initialize +{ + //* Clear the interrupt on the Interrupt Controller ( if one is pending ) + pAic->AIC_ICCR = (0x1 << irq_id); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_AcknowledgeIt +//* \brief Acknowledge corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_AcknowledgeIt ( + AT91PS_AIC pAic) // \arg pointer to the AIC registers +{ + pAic->AIC_EOICR = pAic->AIC_EOICR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_SetExceptionVector +//* \brief Configure vector handler +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_SetExceptionVector ( + unsigned int *pVector, // \arg pointer to the AIC registers + void (*Handler) () ) // \arg Interrupt Handler +{ + unsigned int oldVector = *pVector; + + if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE) + *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE; + else + *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000; + + return oldVector; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_Trig +//* \brief Trig an IT +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_Trig ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg interrupt number +{ + pAic->AIC_ISCR = (0x1 << irq_id) ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_IsActive +//* \brief Test if an IT is active +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_IsActive ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg Interrupt Number +{ + return (pAic->AIC_ISR & (0x1 << irq_id)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_IsPending +//* \brief Test if an IT is pending +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_IsPending ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg Interrupt Number +{ + return (pAic->AIC_IPR & (0x1 << irq_id)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_Open +//* \brief Set exception vectors and AIC registers to default values +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_Open( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + void (*IrqHandler) (), // \arg Default IRQ vector exception + void (*FiqHandler) (), // \arg Default FIQ vector exception + void (*DefaultHandler) (), // \arg Default Handler set in ISR + void (*SpuriousHandler) (), // \arg Default Spurious Handler + unsigned int protectMode) // \arg Debug Control Register +{ + int i; + + // Disable all interrupts and set IVR to the default handler + for (i = 0; i < 32; ++i) { + AT91F_AIC_DisableIt(pAic, i); + AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, DefaultHandler); + } + + // Set the IRQ exception vector + AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler); + // Set the Fast Interrupt exception vector + AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler); + + pAic->AIC_SPU = (unsigned int) SpuriousHandler; + pAic->AIC_DCR = protectMode; +} +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_CfgPMC +//* \brief Enable Peripheral clock in PMC for MC +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_CfgPMC +//* \brief Enable Peripheral clock in PMC for DBGU +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_CfgPIO +//* \brief Configure PIO controllers to drive DBGU signals +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA10_DTXD ) | + ((unsigned int) AT91C_PA9_DRXD ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH3_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH3 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH3_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA14_PWM3 ) | + ((unsigned int) AT91C_PA7_PWM3 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH2_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH2 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH2_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA2_PWM2 ), // Peripheral A + ((unsigned int) AT91C_PA25_PWM2 ) | + ((unsigned int) AT91C_PA13_PWM2 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH1_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA1_PWM1 ), // Peripheral A + ((unsigned int) AT91C_PA24_PWM1 ) | + ((unsigned int) AT91C_PA12_PWM1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH0_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA0_PWM0 ), // Peripheral A + ((unsigned int) AT91C_PA23_PWM0 ) | + ((unsigned int) AT91C_PA11_PWM0 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_CfgPMC +//* \brief Enable Peripheral clock in PMC for SSC +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SSC)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_CfgPIO +//* \brief Configure PIO controllers to drive SSC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA17_TD ) | + ((unsigned int) AT91C_PA15_TF ) | + ((unsigned int) AT91C_PA19_RK ) | + ((unsigned int) AT91C_PA18_RD ) | + ((unsigned int) AT91C_PA20_RF ) | + ((unsigned int) AT91C_PA16_TK ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgPMC +//* \brief Enable Peripheral clock in PMC for SPI +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SPI)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgPIO +//* \brief Configure PIO controllers to drive SPI signals +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA11_NPCS0 ) | + ((unsigned int) AT91C_PA13_MOSI ) | + ((unsigned int) AT91C_PA31_NPCS1 ) | + ((unsigned int) AT91C_PA12_MISO ) | + ((unsigned int) AT91C_PA14_SPCK ), // Peripheral A + ((unsigned int) AT91C_PA9_NPCS1 ) | + ((unsigned int) AT91C_PA30_NPCS2 ) | + ((unsigned int) AT91C_PA10_NPCS2 ) | + ((unsigned int) AT91C_PA22_NPCS3 ) | + ((unsigned int) AT91C_PA3_NPCS3 ) | + ((unsigned int) AT91C_PA5_NPCS3 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CfgPMC +//* \brief Enable Peripheral clock in PMC for PWMC +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_PWMC)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC2_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC2 +//*---------------------------------------------------------------------------- +__inline void AT91F_TC2_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC2)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC2_CfgPIO +//* \brief Configure PIO controllers to drive TC2 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TC2_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA26_TIOA2 ) | + ((unsigned int) AT91C_PA27_TIOB2 ) | + ((unsigned int) AT91C_PA29_TCLK2 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC1_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC1 +//*---------------------------------------------------------------------------- +__inline void AT91F_TC1_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC1_CfgPIO +//* \brief Configure PIO controllers to drive TC1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TC1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA15_TIOA1 ) | + ((unsigned int) AT91C_PA16_TIOB1 ) | + ((unsigned int) AT91C_PA28_TCLK1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC0_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC0 +//*---------------------------------------------------------------------------- +__inline void AT91F_TC0_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC0)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC0_CfgPIO +//* \brief Configure PIO controllers to drive TC0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TC0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA0_TIOA0 ) | + ((unsigned int) AT91C_PA1_TIOB0 ) | + ((unsigned int) AT91C_PA4_TCLK0 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgPMC +//* \brief Enable Peripheral clock in PMC for PMC +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgPIO +//* \brief Configure PIO controllers to drive PMC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA17_PCK1 ) | + ((unsigned int) AT91C_PA21_PCK1 ) | + ((unsigned int) AT91C_PA31_PCK2 ) | + ((unsigned int) AT91C_PA18_PCK2 ) | + ((unsigned int) AT91C_PA6_PCK0 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgPMC +//* \brief Enable Peripheral clock in PMC for ADC +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_ADC)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgPIO +//* \brief Configure PIO controllers to drive ADC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA8_ADTRG )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIOA_CfgPMC +//* \brief Enable Peripheral clock in PMC for PIOA +//*---------------------------------------------------------------------------- +__inline void AT91F_PIOA_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_PIOA)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_CfgPMC +//* \brief Enable Peripheral clock in PMC for TWI +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TWI)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_CfgPIO +//* \brief Configure PIO controllers to drive TWI signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA3_TWD ) | + ((unsigned int) AT91C_PA4_TWCK ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US1_CfgPMC +//* \brief Enable Peripheral clock in PMC for US1 +//*---------------------------------------------------------------------------- +__inline void AT91F_US1_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_US1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US1_CfgPIO +//* \brief Configure PIO controllers to drive US1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_US1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA21_RXD1 ) | + ((unsigned int) AT91C_PA27_DTR1 ) | + ((unsigned int) AT91C_PA26_DCD1 ) | + ((unsigned int) AT91C_PA22_TXD1 ) | + ((unsigned int) AT91C_PA24_RTS1 ) | + ((unsigned int) AT91C_PA23_SCK1 ) | + ((unsigned int) AT91C_PA28_DSR1 ) | + ((unsigned int) AT91C_PA29_RI1 ) | + ((unsigned int) AT91C_PA25_CTS1 ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US0_CfgPMC +//* \brief Enable Peripheral clock in PMC for US0 +//*---------------------------------------------------------------------------- +__inline void AT91F_US0_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_US0)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US0_CfgPIO +//* \brief Configure PIO controllers to drive US0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_US0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA5_RXD0 ) | + ((unsigned int) AT91C_PA6_TXD0 ) | + ((unsigned int) AT91C_PA7_RTS0 ) | + ((unsigned int) AT91C_PA8_CTS0 ), // Peripheral A + ((unsigned int) AT91C_PA2_SCK0 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_CfgPMC +//* \brief Enable Peripheral clock in PMC for UDP +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_UDP)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_CfgPMC +//* \brief Enable Peripheral clock in PMC for AIC +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_IRQ0) | + ((unsigned int) 1 << AT91C_ID_FIQ) | + ((unsigned int) 1 << AT91C_ID_IRQ1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_CfgPIO +//* \brief Configure PIO controllers to drive AIC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA30_IRQ1 ), // Peripheral A + ((unsigned int) AT91C_PA20_IRQ0 ) | + ((unsigned int) AT91C_PA19_FIQ )); // Peripheral B +} + +#endif // lib_AT91SAM7S64_H diff --git a/20080212/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h b/20080212/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h new file mode 100644 index 000000000..805a2bce9 --- /dev/null +++ b/20080212/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h @@ -0,0 +1,4558 @@ +//* ---------------------------------------------------------------------------- +//* ATMEL Microcontroller Software Support - ROUSSET - +//* ---------------------------------------------------------------------------- +//* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//* ---------------------------------------------------------------------------- +//* File Name : lib_AT91SAM7X128.h +//* Object : AT91SAM7X128 inlined functions +//* Generated : AT91 SW Application Group 05/20/2005 (16:22:23) +//* +//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// +//* CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005// +//* CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005// +//* CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004// +//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// +//* CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004// +//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// +//* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003// +//* CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004// +//* CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005// +//* CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005// +//* CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004// +//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003// +//* CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004// +//* CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005// +//* CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005// +//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// +//* CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004// +//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// +//* CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003// +//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// +//* CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002// +//* ---------------------------------------------------------------------------- + +#ifndef lib_AT91SAM7X128_H +#define lib_AT91SAM7X128_H + +/* ***************************************************************************** + SOFTWARE API FOR AIC + ***************************************************************************** */ +#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20] + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_ConfigureIt +//* \brief Interrupt Handler Initialization +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_ConfigureIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id, // \arg interrupt number to initialize + unsigned int priority, // \arg priority to give to the interrupt + unsigned int src_type, // \arg activation and sense of activation + void (*newHandler) (void) ) // \arg address of the interrupt handler +{ + unsigned int oldHandler; + unsigned int mask ; + + oldHandler = pAic->AIC_SVR[irq_id]; + + mask = 0x1 << irq_id ; + //* Disable the interrupt on the interrupt controller + pAic->AIC_IDCR = mask ; + //* Save the interrupt handler routine pointer and the interrupt priority + pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ; + //* Store the Source Mode Register + pAic->AIC_SMR[irq_id] = src_type | priority ; + //* Clear the interrupt on the interrupt controller + pAic->AIC_ICCR = mask ; + + return oldHandler; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_EnableIt +//* \brief Enable corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_EnableIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id ) // \arg interrupt number to initialize +{ + //* Enable the interrupt on the interrupt controller + pAic->AIC_IECR = 0x1 << irq_id ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_DisableIt +//* \brief Disable corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_DisableIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id ) // \arg interrupt number to initialize +{ + unsigned int mask = 0x1 << irq_id; + //* Disable the interrupt on the interrupt controller + pAic->AIC_IDCR = mask ; + //* Clear the interrupt on the Interrupt Controller ( if one is pending ) + pAic->AIC_ICCR = mask ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_ClearIt +//* \brief Clear corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_ClearIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg interrupt number to initialize +{ + //* Clear the interrupt on the Interrupt Controller ( if one is pending ) + pAic->AIC_ICCR = (0x1 << irq_id); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_AcknowledgeIt +//* \brief Acknowledge corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_AcknowledgeIt ( + AT91PS_AIC pAic) // \arg pointer to the AIC registers +{ + pAic->AIC_EOICR = pAic->AIC_EOICR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_SetExceptionVector +//* \brief Configure vector handler +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_SetExceptionVector ( + unsigned int *pVector, // \arg pointer to the AIC registers + void (*Handler) () ) // \arg Interrupt Handler +{ + unsigned int oldVector = *pVector; + + if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE) + *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE; + else + *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000; + + return oldVector; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_Trig +//* \brief Trig an IT +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_Trig ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg interrupt number +{ + pAic->AIC_ISCR = (0x1 << irq_id) ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_IsActive +//* \brief Test if an IT is active +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_IsActive ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg Interrupt Number +{ + return (pAic->AIC_ISR & (0x1 << irq_id)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_IsPending +//* \brief Test if an IT is pending +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_IsPending ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg Interrupt Number +{ + return (pAic->AIC_IPR & (0x1 << irq_id)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_Open +//* \brief Set exception vectors and AIC registers to default values +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_Open( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + void (*IrqHandler) (), // \arg Default IRQ vector exception + void (*FiqHandler) (), // \arg Default FIQ vector exception + void (*DefaultHandler) (), // \arg Default Handler set in ISR + void (*SpuriousHandler) (), // \arg Default Spurious Handler + unsigned int protectMode) // \arg Debug Control Register +{ + int i; + + // Disable all interrupts and set IVR to the default handler + for (i = 0; i < 32; ++i) { + AT91F_AIC_DisableIt(pAic, i); + AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler); + } + + // Set the IRQ exception vector + AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler); + // Set the Fast Interrupt exception vector + AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler); + + pAic->AIC_SPU = (unsigned int) SpuriousHandler; + pAic->AIC_DCR = protectMode; +} +/* ***************************************************************************** + SOFTWARE API FOR PDC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetNextRx +//* \brief Set the next receive transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetNextRx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be received + unsigned int bytes) // \arg number of bytes to be received +{ + pPDC->PDC_RNPR = (unsigned int) address; + pPDC->PDC_RNCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetNextTx +//* \brief Set the next transmit transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetNextTx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be transmitted + unsigned int bytes) // \arg number of bytes to be transmitted +{ + pPDC->PDC_TNPR = (unsigned int) address; + pPDC->PDC_TNCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetRx +//* \brief Set the receive transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetRx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be received + unsigned int bytes) // \arg number of bytes to be received +{ + pPDC->PDC_RPR = (unsigned int) address; + pPDC->PDC_RCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetTx +//* \brief Set the transmit transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetTx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be transmitted + unsigned int bytes) // \arg number of bytes to be transmitted +{ + pPDC->PDC_TPR = (unsigned int) address; + pPDC->PDC_TCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_EnableTx +//* \brief Enable transmit +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_EnableTx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_TXTEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_EnableRx +//* \brief Enable receive +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_EnableRx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_RXTEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_DisableTx +//* \brief Disable transmit +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_DisableTx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_TXTDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_DisableRx +//* \brief Disable receive +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_DisableRx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_RXTDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsTxEmpty +//* \brief Test if the current transfer descriptor has been sent +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_TCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsNextTxEmpty +//* \brief Test if the next transfer descriptor has been moved to the current td +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_TNCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsRxEmpty +//* \brief Test if the current transfer descriptor has been filled +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_RCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsNextRxEmpty +//* \brief Test if the next transfer descriptor has been moved to the current td +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_RNCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_Open +//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_Open ( + AT91PS_PDC pPDC) // \arg pointer to a PDC controller +{ + //* Disable the RX and TX PDC transfer requests + AT91F_PDC_DisableRx(pPDC); + AT91F_PDC_DisableTx(pPDC); + + //* Reset all Counter register Next buffer first + AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); + AT91F_PDC_SetTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetRx(pPDC, (char *) 0, 0); + + //* Enable the RX and TX PDC transfer requests + AT91F_PDC_EnableRx(pPDC); + AT91F_PDC_EnableTx(pPDC); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_Close +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_Close ( + AT91PS_PDC pPDC) // \arg pointer to a PDC controller +{ + //* Disable the RX and TX PDC transfer requests + AT91F_PDC_DisableRx(pPDC); + AT91F_PDC_DisableTx(pPDC); + + //* Reset all Counter register Next buffer first + AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); + AT91F_PDC_SetTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetRx(pPDC, (char *) 0, 0); + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SendFrame +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PDC_SendFrame( + AT91PS_PDC pPDC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + if (AT91F_PDC_IsTxEmpty(pPDC)) { + //* Buffer and next buffer can be initialized + AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer); + AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer); + return 2; + } + else if (AT91F_PDC_IsNextTxEmpty(pPDC)) { + //* Only one buffer can be initialized + AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer); + return 1; + } + else { + //* All buffer are in use... + return 0; + } +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_ReceiveFrame +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PDC_ReceiveFrame ( + AT91PS_PDC pPDC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + if (AT91F_PDC_IsRxEmpty(pPDC)) { + //* Buffer and next buffer can be initialized + AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer); + AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer); + return 2; + } + else if (AT91F_PDC_IsNextRxEmpty(pPDC)) { + //* Only one buffer can be initialized + AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer); + return 1; + } + else { + //* All buffer are in use... + return 0; + } +} +/* ***************************************************************************** + SOFTWARE API FOR DBGU + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_InterruptEnable +//* \brief Enable DBGU Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_InterruptEnable( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg dbgu interrupt to be enabled +{ + pDbgu->DBGU_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_InterruptDisable +//* \brief Disable DBGU Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_InterruptDisable( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg dbgu interrupt to be disabled +{ + pDbgu->DBGU_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_GetInterruptMaskStatus +//* \brief Return DBGU Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status + AT91PS_DBGU pDbgu) // \arg pointer to a DBGU controller +{ + return pDbgu->DBGU_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_IsInterruptMasked +//* \brief Test if DBGU Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_DBGU_IsInterruptMasked( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR PIO + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgPeriph +//* \brief Enable pins to be drived by peripheral +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgPeriph( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int periphAEnable, // \arg PERIPH A to enable + unsigned int periphBEnable) // \arg PERIPH B to enable + +{ + pPio->PIO_ASR = periphAEnable; + pPio->PIO_BSR = periphBEnable; + pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgOutput +//* \brief Enable PIO in output mode +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int pioEnable) // \arg PIO to be enabled +{ + pPio->PIO_PER = pioEnable; // Set in PIO mode + pPio->PIO_OER = pioEnable; // Configure in Output +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgInput +//* \brief Enable PIO in input mode +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgInput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int inputEnable) // \arg PIO to be enabled +{ + // Disable output + pPio->PIO_ODR = inputEnable; + pPio->PIO_PER = inputEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgOpendrain +//* \brief Configure PIO in open drain +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgOpendrain( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int multiDrvEnable) // \arg pio to be configured in open drain +{ + // Configure the multi-drive option + pPio->PIO_MDDR = ~multiDrvEnable; + pPio->PIO_MDER = multiDrvEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgPullup +//* \brief Enable pullup on PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgPullup( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int pullupEnable) // \arg enable pullup on PIO +{ + // Connect or not Pullup + pPio->PIO_PPUDR = ~pullupEnable; + pPio->PIO_PPUER = pullupEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgDirectDrive +//* \brief Enable direct drive on PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgDirectDrive( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int directDrive) // \arg PIO to be configured with direct drive + +{ + // Configure the Direct Drive + pPio->PIO_OWDR = ~directDrive; + pPio->PIO_OWER = directDrive; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgInputFilter +//* \brief Enable input filter on input PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgInputFilter( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int inputFilter) // \arg PIO to be configured with input filter + +{ + // Configure the Direct Drive + pPio->PIO_IFDR = ~inputFilter; + pPio->PIO_IFER = inputFilter; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInput +//* \brief Return PIO input value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInput( // \return PIO input + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PDSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInputSet +//* \brief Test if PIO is input flag is active +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInputSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInput(pPio) & flag); +} + + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_SetOutput +//* \brief Set to 1 output PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_SetOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be set +{ + pPio->PIO_SODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_ClearOutput +//* \brief Set to 0 output PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_ClearOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be cleared +{ + pPio->PIO_CODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_ForceOutput +//* \brief Force output when Direct drive option is enabled +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_ForceOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be forced +{ + pPio->PIO_ODSR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Enable +//* \brief Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_Enable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be enabled +{ + pPio->PIO_PER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Disable +//* \brief Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_Disable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be disabled +{ + pPio->PIO_PDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetStatus +//* \brief Return PIO Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsSet +//* \brief Test if PIO is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputEnable +//* \brief Output Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output to be enabled +{ + pPio->PIO_OER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputDisable +//* \brief Output Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output to be disabled +{ + pPio->PIO_ODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputStatus +//* \brief Return PIO Output Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_OSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOuputSet +//* \brief Test if PIO Output is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsOutputSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InputFilterEnable +//* \brief Input Filter Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InputFilterEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio input filter to be enabled +{ + pPio->PIO_IFER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InputFilterDisable +//* \brief Input Filter Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InputFilterDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio input filter to be disabled +{ + pPio->PIO_IFDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInputFilterStatus +//* \brief Return PIO Input Filter Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_IFSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInputFilterSet +//* \brief Test if PIO Input filter is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInputFilterSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInputFilterStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputDataStatus +//* \brief Return PIO Output Data Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ODSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InterruptEnable +//* \brief Enable PIO Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InterruptEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio interrupt to be enabled +{ + pPio->PIO_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InterruptDisable +//* \brief Disable PIO Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InterruptDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio interrupt to be disabled +{ + pPio->PIO_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInterruptMaskStatus +//* \brief Return PIO Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInterruptStatus +//* \brief Return PIO Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ISR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInterruptMasked +//* \brief Test if PIO Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInterruptMasked( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInterruptSet +//* \brief Test if PIO Interrupt is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInterruptSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInterruptStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_MultiDriverEnable +//* \brief Multi Driver Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_MultiDriverEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be enabled +{ + pPio->PIO_MDER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_MultiDriverDisable +//* \brief Multi Driver Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_MultiDriverDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be disabled +{ + pPio->PIO_MDDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetMultiDriverStatus +//* \brief Return PIO Multi Driver Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_MDSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsMultiDriverSet +//* \brief Test if PIO MultiDriver is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsMultiDriverSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_A_RegisterSelection +//* \brief PIO A Register Selection +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_A_RegisterSelection( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio A register selection +{ + pPio->PIO_ASR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_B_RegisterSelection +//* \brief PIO B Register Selection +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_B_RegisterSelection( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio B register selection +{ + pPio->PIO_BSR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Get_AB_RegisterStatus +//* \brief Return PIO Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ABSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsAB_RegisterSet +//* \brief Test if PIO AB Register is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsAB_RegisterSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputWriteEnable +//* \brief Output Write Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputWriteEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output write to be enabled +{ + pPio->PIO_OWER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputWriteDisable +//* \brief Output Write Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputWriteDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output write to be disabled +{ + pPio->PIO_OWDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputWriteStatus +//* \brief Return PIO Output Write Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_OWSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOutputWriteSet +//* \brief Test if PIO OutputWrite is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsOutputWriteSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetCfgPullup +//* \brief Return PIO Configuration Pullup +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PPUSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOutputDataStatusSet +//* \brief Test if PIO Output Data Status is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsOutputDataStatusSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputDataStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsCfgPullupStatusSet +//* \brief Test if PIO Configuration Pullup Status is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsCfgPullupStatusSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (~AT91F_PIO_GetCfgPullup(pPio) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR PMC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgSysClkEnableReg +//* \brief Configure the System Clock Enable Register of the PMC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgSysClkEnableReg ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int mode) +{ + //* Write to the SCER register + pPMC->PMC_SCER = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgSysClkDisableReg +//* \brief Configure the System Clock Disable Register of the PMC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgSysClkDisableReg ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int mode) +{ + //* Write to the SCDR register + pPMC->PMC_SCDR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetSysClkStatusReg +//* \brief Return the System Clock Status Register of the PMC controller +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetSysClkStatusReg ( + AT91PS_PMC pPMC // pointer to a CAN controller + ) +{ + return pPMC->PMC_SCSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnablePeriphClock +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_EnablePeriphClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int periphIds) // \arg IDs of peripherals to enable +{ + pPMC->PMC_PCER = periphIds; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisablePeriphClock +//* \brief Disable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_DisablePeriphClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int periphIds) // \arg IDs of peripherals to enable +{ + pPMC->PMC_PCDR = periphIds; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetPeriphClock +//* \brief Get peripheral clock status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetPeriphClock ( + AT91PS_PMC pPMC) // \arg pointer to PMC controller +{ + return pPMC->PMC_PCSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_CfgMainOscillatorReg +//* \brief Cfg the main oscillator +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_CfgMainOscillatorReg ( + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int mode) +{ + pCKGR->CKGR_MOR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_GetMainOscillatorReg +//* \brief Cfg the main oscillator +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CKGR_GetMainOscillatorReg ( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + return pCKGR->CKGR_MOR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_EnableMainOscillator +//* \brief Enable the main oscillator +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_EnableMainOscillator( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_DisableMainOscillator +//* \brief Disable the main oscillator +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_DisableMainOscillator ( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_CfgMainOscStartUpTime +//* \brief Cfg MOR Register according to the main osc startup time +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_CfgMainOscStartUpTime ( + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int startup_time, // \arg main osc startup time in microsecond (us) + unsigned int slowClock) // \arg slowClock in Hz +{ + pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT; + pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_GetMainClockFreqReg +//* \brief Cfg the main oscillator +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CKGR_GetMainClockFreqReg ( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + return pCKGR->CKGR_MCFR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_GetMainClock +//* \brief Return Main clock in Hz +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CKGR_GetMainClock ( + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int slowClock) // \arg slowClock in Hz +{ + return ((pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF) * slowClock) >> 4; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgMCKReg +//* \brief Cfg Master Clock Register +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgMCKReg ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int mode) +{ + pPMC->PMC_MCKR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetMCKReg +//* \brief Return Master Clock Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetMCKReg( + AT91PS_PMC pPMC) // \arg pointer to PMC controller +{ + return pPMC->PMC_MCKR; +} + +//*------------------------------------------------------------------------------ +//* \fn AT91F_PMC_GetMasterClock +//* \brief Return master clock in Hz which correponds to processor clock for ARM7 +//*------------------------------------------------------------------------------ +__inline unsigned int AT91F_PMC_GetMasterClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int slowClock) // \arg slowClock in Hz +{ + unsigned int reg = pPMC->PMC_MCKR; + unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2)); + unsigned int pllDivider, pllMultiplier; + + switch (reg & AT91C_PMC_CSS) { + case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected + return slowClock / prescaler; + case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected + return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler; + case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected + reg = pCKGR->CKGR_PLLR; + pllDivider = (reg & AT91C_CKGR_DIV); + pllMultiplier = ((reg & AT91C_CKGR_MUL) >> 16) + 1; + return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler; + } + return 0; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnablePCK +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_EnablePCK ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int pck, // \arg Peripheral clock identifier 0 .. 7 + unsigned int mode) +{ + pPMC->PMC_PCKR[pck] = mode; + pPMC->PMC_SCER = (1 << pck) << 8; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisablePCK +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_DisablePCK ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int pck) // \arg Peripheral clock identifier 0 .. 7 +{ + pPMC->PMC_SCDR = (1 << pck) << 8; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnableIt +//* \brief Enable PMC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_EnableIt ( + AT91PS_PMC pPMC, // pointer to a PMC controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pPMC->PMC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisableIt +//* \brief Disable PMC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_DisableIt ( + AT91PS_PMC pPMC, // pointer to a PMC controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pPMC->PMC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetStatus +//* \brief Return PMC Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status + AT91PS_PMC pPMC) // pointer to a PMC controller +{ + return pPMC->PMC_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetInterruptMaskStatus +//* \brief Return PMC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status + AT91PS_PMC pPMC) // pointer to a PMC controller +{ + return pPMC->PMC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_IsInterruptMasked +//* \brief Test if PMC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_IsInterruptMasked( + AT91PS_PMC pPMC, // \arg pointer to a PMC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_IsStatusSet +//* \brief Test if PMC Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_IsStatusSet( + AT91PS_PMC pPMC, // \arg pointer to a PMC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PMC_GetStatus(pPMC) & flag); +}/* ***************************************************************************** + SOFTWARE API FOR RSTC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTSoftReset +//* \brief Start Software Reset +//*---------------------------------------------------------------------------- +__inline void AT91F_RSTSoftReset( + AT91PS_RSTC pRSTC, + unsigned int reset) +{ + pRSTC->RSTC_RCR = (0xA5000000 | reset); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTSetMode +//* \brief Set Reset Mode +//*---------------------------------------------------------------------------- +__inline void AT91F_RSTSetMode( + AT91PS_RSTC pRSTC, + unsigned int mode) +{ + pRSTC->RSTC_RMR = (0xA5000000 | mode); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTGetMode +//* \brief Get Reset Mode +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_RSTGetMode( + AT91PS_RSTC pRSTC) +{ + return (pRSTC->RSTC_RMR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTGetStatus +//* \brief Get Reset Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_RSTGetStatus( + AT91PS_RSTC pRSTC) +{ + return (pRSTC->RSTC_RSR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTIsSoftRstActive +//* \brief Return !=0 if software reset is still not completed +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_RSTIsSoftRstActive( + AT91PS_RSTC pRSTC) +{ + return ((pRSTC->RSTC_RSR) & AT91C_RSTC_SRCMP); +} +/* ***************************************************************************** + SOFTWARE API FOR RTTC + ***************************************************************************** */ +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_SetRTT_TimeBase() +//* \brief Set the RTT prescaler according to the TimeBase in ms +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTSetTimeBase( + AT91PS_RTTC pRTTC, + unsigned int ms) +{ + if (ms > 2000) + return 1; // AT91C_TIME_OUT_OF_RANGE + pRTTC->RTTC_RTMR &= ~0xFFFF; + pRTTC->RTTC_RTMR |= (((ms << 15) /1000) & 0xFFFF); + return 0; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTTSetPrescaler() +//* \brief Set the new prescaler value +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTSetPrescaler( + AT91PS_RTTC pRTTC, + unsigned int rtpres) +{ + pRTTC->RTTC_RTMR &= ~0xFFFF; + pRTTC->RTTC_RTMR |= (rtpres & 0xFFFF); + return (pRTTC->RTTC_RTMR); +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTTRestart() +//* \brief Restart the RTT prescaler +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTRestart( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST; +} + + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_SetAlarmINT() +//* \brief Enable RTT Alarm Interrupt +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTSetAlarmINT( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_ClearAlarmINT() +//* \brief Disable RTT Alarm Interrupt +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTClearAlarmINT( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_SetRttIncINT() +//* \brief Enable RTT INC Interrupt +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTSetRttIncINT( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_ClearRttIncINT() +//* \brief Disable RTT INC Interrupt +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTClearRttIncINT( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_SetAlarmValue() +//* \brief Set RTT Alarm Value +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTSetAlarmValue( + AT91PS_RTTC pRTTC, unsigned int alarm) +{ + pRTTC->RTTC_RTAR = alarm; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_GetAlarmValue() +//* \brief Get RTT Alarm Value +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTGetAlarmValue( + AT91PS_RTTC pRTTC) +{ + return(pRTTC->RTTC_RTAR); +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTTGetStatus() +//* \brief Read the RTT status +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTGetStatus( + AT91PS_RTTC pRTTC) +{ + return(pRTTC->RTTC_RTSR); +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_ReadValue() +//* \brief Read the RTT value +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTReadValue( + AT91PS_RTTC pRTTC) +{ + register volatile unsigned int val1,val2; + do + { + val1 = pRTTC->RTTC_RTVR; + val2 = pRTTC->RTTC_RTVR; + } + while(val1 != val2); + return(val1); +} +/* ***************************************************************************** + SOFTWARE API FOR PITC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITInit +//* \brief System timer init : period in µsecond, system clock freq in MHz +//*---------------------------------------------------------------------------- +__inline void AT91F_PITInit( + AT91PS_PITC pPITC, + unsigned int period, + unsigned int pit_frequency) +{ + pPITC->PITC_PIMR = period? (period * pit_frequency + 8) >> 4 : 0; // +8 to avoid %10 and /10 + pPITC->PITC_PIMR |= AT91C_PITC_PITEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITSetPIV +//* \brief Set the PIT Periodic Interval Value +//*---------------------------------------------------------------------------- +__inline void AT91F_PITSetPIV( + AT91PS_PITC pPITC, + unsigned int piv) +{ + pPITC->PITC_PIMR = piv | (pPITC->PITC_PIMR & (AT91C_PITC_PITEN | AT91C_PITC_PITIEN)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITEnableInt +//* \brief Enable PIT periodic interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PITEnableInt( + AT91PS_PITC pPITC) +{ + pPITC->PITC_PIMR |= AT91C_PITC_PITIEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITDisableInt +//* \brief Disable PIT periodic interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PITDisableInt( + AT91PS_PITC pPITC) +{ + pPITC->PITC_PIMR &= ~AT91C_PITC_PITIEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITGetMode +//* \brief Read PIT mode register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PITGetMode( + AT91PS_PITC pPITC) +{ + return(pPITC->PITC_PIMR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITGetStatus +//* \brief Read PIT status register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PITGetStatus( + AT91PS_PITC pPITC) +{ + return(pPITC->PITC_PISR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITGetPIIR +//* \brief Read PIT CPIV and PICNT without ressetting the counters +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PITGetPIIR( + AT91PS_PITC pPITC) +{ + return(pPITC->PITC_PIIR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITGetPIVR +//* \brief Read System timer CPIV and PICNT without ressetting the counters +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PITGetPIVR( + AT91PS_PITC pPITC) +{ + return(pPITC->PITC_PIVR); +} +/* ***************************************************************************** + SOFTWARE API FOR WDTC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTSetMode +//* \brief Set Watchdog Mode Register +//*---------------------------------------------------------------------------- +__inline void AT91F_WDTSetMode( + AT91PS_WDTC pWDTC, + unsigned int Mode) +{ + pWDTC->WDTC_WDMR = Mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTRestart +//* \brief Restart Watchdog +//*---------------------------------------------------------------------------- +__inline void AT91F_WDTRestart( + AT91PS_WDTC pWDTC) +{ + pWDTC->WDTC_WDCR = 0xA5000001; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTSGettatus +//* \brief Get Watchdog Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_WDTSGettatus( + AT91PS_WDTC pWDTC) +{ + return(pWDTC->WDTC_WDSR & 0x3); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTGetPeriod +//* \brief Translate ms into Watchdog Compatible value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_WDTGetPeriod(unsigned int ms) +{ + if ((ms < 4) || (ms > 16000)) + return 0; + return((ms << 8) / 1000); +} +/* ***************************************************************************** + SOFTWARE API FOR VREG + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_VREG_Enable_LowPowerMode +//* \brief Enable VREG Low Power Mode +//*---------------------------------------------------------------------------- +__inline void AT91F_VREG_Enable_LowPowerMode( + AT91PS_VREG pVREG) +{ + pVREG->VREG_MR |= AT91C_VREG_PSTDBY; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_VREG_Disable_LowPowerMode +//* \brief Disable VREG Low Power Mode +//*---------------------------------------------------------------------------- +__inline void AT91F_VREG_Disable_LowPowerMode( + AT91PS_VREG pVREG) +{ + pVREG->VREG_MR &= ~AT91C_VREG_PSTDBY; +}/* ***************************************************************************** + SOFTWARE API FOR MC + ***************************************************************************** */ + +#define AT91C_MC_CORRECT_KEY ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_Remap +//* \brief Make Remap +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_Remap (void) // +{ + AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC; + + pMC->MC_RCR = AT91C_MC_RCB; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_CfgModeReg +//* \brief Configure the EFC Mode Register of the MC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_EFC_CfgModeReg ( + AT91PS_MC pMC, // pointer to a MC controller + unsigned int mode) // mode register +{ + // Write to the FMR register + pMC->MC_FMR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_GetModeReg +//* \brief Return MC EFC Mode Regsiter +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_GetModeReg( + AT91PS_MC pMC) // pointer to a MC controller +{ + return pMC->MC_FMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_ComputeFMCN +//* \brief Return MC EFC Mode Regsiter +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_ComputeFMCN( + int master_clock) // master clock in Hz +{ + return (master_clock/1000000 +2); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_PerformCmd +//* \brief Perform EFC Command +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_EFC_PerformCmd ( + AT91PS_MC pMC, // pointer to a MC controller + unsigned int transfer_cmd) +{ + pMC->MC_FCR = transfer_cmd; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_GetStatus +//* \brief Return MC EFC Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_GetStatus( + AT91PS_MC pMC) // pointer to a MC controller +{ + return pMC->MC_FSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_IsInterruptMasked +//* \brief Test if EFC MC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_IsInterruptMasked( + AT91PS_MC pMC, // \arg pointer to a MC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_MC_EFC_GetModeReg(pMC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_IsInterruptSet +//* \brief Test if EFC MC Interrupt is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_IsInterruptSet( + AT91PS_MC pMC, // \arg pointer to a MC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_MC_EFC_GetStatus(pMC) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR SPI + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Open +//* \brief Open a SPI Port +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_Open ( + const unsigned int null) // \arg +{ + /* NOT DEFINED AT THIS MOMENT */ + return ( 0 ); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgCs +//* \brief Configure SPI chip select register +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgCs ( + AT91PS_SPI pSPI, // pointer to a SPI controller + int cs, // SPI cs number (0 to 3) + int val) // chip select register +{ + //* Write to the CSR register + *(pSPI->SPI_CSR + cs) = val; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_EnableIt +//* \brief Enable SPI interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_EnableIt ( + AT91PS_SPI pSPI, // pointer to a SPI controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pSPI->SPI_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_DisableIt +//* \brief Disable SPI interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_DisableIt ( + AT91PS_SPI pSPI, // pointer to a SPI controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pSPI->SPI_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Reset +//* \brief Reset the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Reset ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Enable +//* \brief Enable the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Enable ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SPIEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Disable +//* \brief Disable the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Disable ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SPIDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgMode +//* \brief Enable the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgMode ( + AT91PS_SPI pSPI, // pointer to a SPI controller + int mode) // mode register +{ + //* Write to the MR register + pSPI->SPI_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgPCS +//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgPCS ( + AT91PS_SPI pSPI, // pointer to a SPI controller + char PCS_Device) // PCS of the Device +{ + //* Write to the MR register + pSPI->SPI_MR &= 0xFFF0FFFF; + pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS ); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_ReceiveFrame ( + AT91PS_SPI pSPI, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pSPI->SPI_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_SendFrame( + AT91PS_SPI pSPI, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pSPI->SPI_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Close +//* \brief Close SPI: disable IT disable transfert, close PDC +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Close ( + AT91PS_SPI pSPI) // \arg pointer to a SPI controller +{ + //* Reset all the Chip Select register + pSPI->SPI_CSR[0] = 0 ; + pSPI->SPI_CSR[1] = 0 ; + pSPI->SPI_CSR[2] = 0 ; + pSPI->SPI_CSR[3] = 0 ; + + //* Reset the SPI mode + pSPI->SPI_MR = 0 ; + + //* Disable all interrupts + pSPI->SPI_IDR = 0xFFFFFFFF ; + + //* Abort the Peripheral Data Transfers + AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR)); + + //* Disable receiver and transmitter and stop any activity immediately + pSPI->SPI_CR = AT91C_SPI_SPIDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_PutChar +//* \brief Send a character,does not check if ready to send +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_PutChar ( + AT91PS_SPI pSPI, + unsigned int character, + unsigned int cs_number ) +{ + unsigned int value_for_cs; + value_for_cs = (~(1 << cs_number)) & 0xF; //Place a zero among a 4 ONEs number + pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_GetChar +//* \brief Receive a character,does not check if a character is available +//*---------------------------------------------------------------------------- +__inline int AT91F_SPI_GetChar ( + const AT91PS_SPI pSPI) +{ + return((pSPI->SPI_RDR) & 0xFFFF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_GetInterruptMaskStatus +//* \brief Return SPI Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status + AT91PS_SPI pSpi) // \arg pointer to a SPI controller +{ + return pSpi->SPI_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_IsInterruptMasked +//* \brief Test if SPI Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_SPI_IsInterruptMasked( + AT91PS_SPI pSpi, // \arg pointer to a SPI controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR USART + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Baudrate +//* \brief Calculate the baudrate +//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_EXT ) + +//* Standard Synchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \ + AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//* SCK used Label +#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT) + +//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity +#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \ + AT91C_US_CLKS_CLOCK +\ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_EVEN + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CKLO +\ + AT91C_US_OVER) + +//* Standard IRDA mode +#define AT91C_US_ASYNC_IRDA_MODE ( AT91C_US_USMODE_IRDA + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Baudrate +//* \brief Caluculate baud_value according to the main clock and the baud rate +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_Baudrate ( + const unsigned int main_clock, // \arg peripheral clock + const unsigned int baud_rate) // \arg UART baudrate +{ + unsigned int baud_value = ((main_clock*10)/(baud_rate * 16)); + if ((baud_value % 10) >= 5) + baud_value = (baud_value / 10) + 1; + else + baud_value /= 10; + return baud_value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetBaudrate +//* \brief Set the baudrate according to the CPU clock +//*---------------------------------------------------------------------------- +__inline void AT91F_US_SetBaudrate ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int mainClock, // \arg peripheral clock + unsigned int speed) // \arg UART baudrate +{ + //* Define the baud rate divisor register + pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetTimeguard +//* \brief Set USART timeguard +//*---------------------------------------------------------------------------- +__inline void AT91F_US_SetTimeguard ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int timeguard) // \arg timeguard value +{ + //* Write the Timeguard Register + pUSART->US_TTGR = timeguard ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableIt +//* \brief Enable USART IT +//*---------------------------------------------------------------------------- +__inline void AT91F_US_EnableIt ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pUSART->US_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableIt +//* \brief Disable USART IT +//*---------------------------------------------------------------------------- +__inline void AT91F_US_DisableIt ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IER register + pUSART->US_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Configure +//* \brief Configure USART +//*---------------------------------------------------------------------------- +__inline void AT91F_US_Configure ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int mainClock, // \arg peripheral clock + unsigned int mode , // \arg mode Register to be programmed + unsigned int baudRate , // \arg baudrate to be programmed + unsigned int timeguard ) // \arg timeguard to be programmed +{ + //* Disable interrupts + pUSART->US_IDR = (unsigned int) -1; + + //* Reset receiver and transmitter + pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ; + + //* Define the baud rate divisor register + AT91F_US_SetBaudrate(pUSART, mainClock, baudRate); + + //* Write the Timeguard Register + AT91F_US_SetTimeguard(pUSART, timeguard); + + //* Clear Transmit and Receive Counters + AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR)); + + //* Define the USART mode + pUSART->US_MR = mode ; + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableRx +//* \brief Enable receiving characters +//*---------------------------------------------------------------------------- +__inline void AT91F_US_EnableRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Enable receiver + pUSART->US_CR = AT91C_US_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableTx +//* \brief Enable sending characters +//*---------------------------------------------------------------------------- +__inline void AT91F_US_EnableTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Enable transmitter + pUSART->US_CR = AT91C_US_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ResetRx +//* \brief Reset Receiver and re-enable it +//*---------------------------------------------------------------------------- +__inline void AT91F_US_ResetRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset receiver + pUSART->US_CR = AT91C_US_RSTRX; + //* Re-Enable receiver + pUSART->US_CR = AT91C_US_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ResetTx +//* \brief Reset Transmitter and re-enable it +//*---------------------------------------------------------------------------- +__inline void AT91F_US_ResetTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset transmitter + pUSART->US_CR = AT91C_US_RSTTX; + //* Enable transmitter + pUSART->US_CR = AT91C_US_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableRx +//* \brief Disable Receiver +//*---------------------------------------------------------------------------- +__inline void AT91F_US_DisableRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Disable receiver + pUSART->US_CR = AT91C_US_RXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableTx +//* \brief Disable Transmitter +//*---------------------------------------------------------------------------- +__inline void AT91F_US_DisableTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Disable transmitter + pUSART->US_CR = AT91C_US_TXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Close +//* \brief Close USART: disable IT disable receiver and transmitter, close PDC +//*---------------------------------------------------------------------------- +__inline void AT91F_US_Close ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset the baud rate divisor register + pUSART->US_BRGR = 0 ; + + //* Reset the USART mode + pUSART->US_MR = 0 ; + + //* Reset the Timeguard Register + pUSART->US_TTGR = 0; + + //* Disable all interrupts + pUSART->US_IDR = 0xFFFFFFFF ; + + //* Abort the Peripheral Data Transfers + AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR)); + + //* Disable receiver and transmitter and stop any activity immediately + pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_TxReady +//* \brief Return 1 if a character can be written in US_THR +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_TxReady ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & AT91C_US_TXRDY); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_RxReady +//* \brief Return 1 if a character can be read in US_RHR +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_RxReady ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & AT91C_US_RXRDY); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Error +//* \brief Return the error flag +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_Error ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & + (AT91C_US_OVRE | // Overrun error + AT91C_US_FRAME | // Framing error + AT91C_US_PARE)); // Parity error +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_PutChar +//* \brief Send a character,does not check if ready to send +//*---------------------------------------------------------------------------- +__inline void AT91F_US_PutChar ( + AT91PS_USART pUSART, + int character ) +{ + pUSART->US_THR = (character & 0x1FF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_GetChar +//* \brief Receive a character,does not check if a character is available +//*---------------------------------------------------------------------------- +__inline int AT91F_US_GetChar ( + const AT91PS_USART pUSART) +{ + return((pUSART->US_RHR) & 0x1FF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_SendFrame( + AT91PS_USART pUSART, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pUSART->US_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_ReceiveFrame ( + AT91PS_USART pUSART, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pUSART->US_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetIrdaFilter +//* \brief Set the value of IrDa filter tregister +//*---------------------------------------------------------------------------- +__inline void AT91F_US_SetIrdaFilter ( + AT91PS_USART pUSART, + unsigned char value +) +{ + pUSART->US_IF = value; +} + +/* ***************************************************************************** + SOFTWARE API FOR SSC + ***************************************************************************** */ +//* Define the standard I2S mode configuration + +//* Configuration to set in the SSC Transmit Clock Mode Register +//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits +//* nb_slot_by_frame : number of channels +#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ + AT91C_SSC_CKS_DIV +\ + AT91C_SSC_CKO_CONTINOUS +\ + AT91C_SSC_CKG_NONE +\ + AT91C_SSC_START_FALL_RF +\ + AT91C_SSC_STTOUT +\ + ((1<<16) & AT91C_SSC_STTDLY) +\ + ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24)) + + +//* Configuration to set in the SSC Transmit Frame Mode Register +//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits +//* nb_slot_by_frame : number of channels +#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ + (nb_bit_by_slot-1) +\ + AT91C_SSC_MSBF +\ + (((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB) +\ + (((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\ + AT91C_SSC_FSOS_NEGATIVE) + + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_SetBaudrate +//* \brief Set the baudrate according to the CPU clock +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_SetBaudrate ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int mainClock, // \arg peripheral clock + unsigned int speed) // \arg SSC baudrate +{ + unsigned int baud_value; + //* Define the baud rate divisor register + if (speed == 0) + baud_value = 0; + else + { + baud_value = (unsigned int) (mainClock * 10)/(2*speed); + if ((baud_value % 10) >= 5) + baud_value = (baud_value / 10) + 1; + else + baud_value /= 10; + } + + pSSC->SSC_CMR = baud_value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_Configure +//* \brief Configure SSC +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_Configure ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int syst_clock, // \arg System Clock Frequency + unsigned int baud_rate, // \arg Expected Baud Rate Frequency + unsigned int clock_rx, // \arg Receiver Clock Parameters + unsigned int mode_rx, // \arg mode Register to be programmed + unsigned int clock_tx, // \arg Transmitter Clock Parameters + unsigned int mode_tx) // \arg mode Register to be programmed +{ + //* Disable interrupts + pSSC->SSC_IDR = (unsigned int) -1; + + //* Reset receiver and transmitter + pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ; + + //* Define the Clock Mode Register + AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate); + + //* Write the Receive Clock Mode Register + pSSC->SSC_RCMR = clock_rx; + + //* Write the Transmit Clock Mode Register + pSSC->SSC_TCMR = clock_tx; + + //* Write the Receive Frame Mode Register + pSSC->SSC_RFMR = mode_rx; + + //* Write the Transmit Frame Mode Register + pSSC->SSC_TFMR = mode_tx; + + //* Clear Transmit and Receive Counters + AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR)); + + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableRx +//* \brief Enable receiving datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_EnableRx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Enable receiver + pSSC->SSC_CR = AT91C_SSC_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableRx +//* \brief Disable receiving datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_DisableRx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Disable receiver + pSSC->SSC_CR = AT91C_SSC_RXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableTx +//* \brief Enable sending datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_EnableTx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Enable transmitter + pSSC->SSC_CR = AT91C_SSC_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableTx +//* \brief Disable sending datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_DisableTx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Disable transmitter + pSSC->SSC_CR = AT91C_SSC_TXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableIt +//* \brief Enable SSC IT +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_EnableIt ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pSSC->SSC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableIt +//* \brief Disable SSC IT +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_DisableIt ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pSSC->SSC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SSC_ReceiveFrame ( + AT91PS_SSC pSSC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pSSC->SSC_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SSC_SendFrame( + AT91PS_SSC pSSC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pSSC->SSC_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_GetInterruptMaskStatus +//* \brief Return SSC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status + AT91PS_SSC pSsc) // \arg pointer to a SSC controller +{ + return pSsc->SSC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_IsInterruptMasked +//* \brief Test if SSC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_SSC_IsInterruptMasked( + AT91PS_SSC pSsc, // \arg pointer to a SSC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR TWI + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_EnableIt +//* \brief Enable TWI IT +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_EnableIt ( + AT91PS_TWI pTWI, // \arg pointer to a TWI controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pTWI->TWI_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_DisableIt +//* \brief Disable TWI IT +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_DisableIt ( + AT91PS_TWI pTWI, // \arg pointer to a TWI controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pTWI->TWI_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_Configure +//* \brief Configure TWI in master mode +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI ) // \arg pointer to a TWI controller +{ + //* Disable interrupts + pTWI->TWI_IDR = (unsigned int) -1; + + //* Reset peripheral + pTWI->TWI_CR = AT91C_TWI_SWRST; + + //* Set Master mode + pTWI->TWI_CR = AT91C_TWI_MSEN; + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_GetInterruptMaskStatus +//* \brief Return TWI Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status + AT91PS_TWI pTwi) // \arg pointer to a TWI controller +{ + return pTwi->TWI_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_IsInterruptMasked +//* \brief Test if TWI Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_TWI_IsInterruptMasked( + AT91PS_TWI pTwi, // \arg pointer to a TWI controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR PWMC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_GetStatus +//* \brief Return PWM Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status + AT91PS_PWMC pPWM) // pointer to a PWM controller +{ + return pPWM->PWMC_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_InterruptEnable +//* \brief Enable PWM Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_InterruptEnable( + AT91PS_PWMC pPwm, // \arg pointer to a PWM controller + unsigned int flag) // \arg PWM interrupt to be enabled +{ + pPwm->PWMC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_InterruptDisable +//* \brief Disable PWM Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_InterruptDisable( + AT91PS_PWMC pPwm, // \arg pointer to a PWM controller + unsigned int flag) // \arg PWM interrupt to be disabled +{ + pPwm->PWMC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_GetInterruptMaskStatus +//* \brief Return PWM Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status + AT91PS_PWMC pPwm) // \arg pointer to a PWM controller +{ + return pPwm->PWMC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_IsInterruptMasked +//* \brief Test if PWM Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_IsInterruptMasked( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_IsStatusSet +//* \brief Test if PWM Interrupt is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_IsStatusSet( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PWMC_GetStatus(pPWM) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_CfgChannel +//* \brief Test if PWM Interrupt is Set +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CfgChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int channelId, // \arg PWM channel ID + unsigned int mode, // \arg PWM mode + unsigned int period, // \arg PWM period + unsigned int duty) // \arg PWM duty cycle +{ + pPWM->PWMC_CH[channelId].PWMC_CMR = mode; + pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty; + pPWM->PWMC_CH[channelId].PWMC_CPRDR = period; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_StartChannel +//* \brief Enable channel +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_StartChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg Channels IDs to be enabled +{ + pPWM->PWMC_ENA = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_StopChannel +//* \brief Disable channel +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_StopChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg Channels IDs to be enabled +{ + pPWM->PWMC_DIS = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_UpdateChannel +//* \brief Update Period or Duty Cycle +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_UpdateChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int channelId, // \arg PWM channel ID + unsigned int update) // \arg Channels IDs to be enabled +{ + pPWM->PWMC_CH[channelId].PWMC_CUPDR = update; +} + +/* ***************************************************************************** + SOFTWARE API FOR UDP + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EnableIt +//* \brief Enable UDP IT +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EnableIt ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pUDP->UDP_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_DisableIt +//* \brief Disable UDP IT +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_DisableIt ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pUDP->UDP_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_SetAddress +//* \brief Set UDP functional address +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_SetAddress ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char address) // \arg new UDP address +{ + pUDP->UDP_FADDR = (AT91C_UDP_FEN | address); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EnableEp +//* \brief Enable Endpoint +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EnableEp ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] |= AT91C_UDP_EPEDS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_DisableEp +//* \brief Enable Endpoint +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_DisableEp ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] &= ~AT91C_UDP_EPEDS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_SetState +//* \brief Set UDP Device state +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_SetState ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg new UDP address +{ + pUDP->UDP_GLBSTATE &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG); + pUDP->UDP_GLBSTATE |= flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_GetState +//* \brief return UDP Device state +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state + AT91PS_UDP pUDP) // \arg pointer to a UDP controller +{ + return (pUDP->UDP_GLBSTATE & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_ResetEp +//* \brief Reset UDP endpoint +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_ResetEp ( // \return the UDP device state + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg Endpoints to be reset +{ + pUDP->UDP_RSTEP = flag; + pUDP->UDP_RSTEP = 0; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpStall +//* \brief Endpoint will STALL requests +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpStall( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpWrite +//* \brief Write value in the DPR +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpWrite( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned char value) // \arg value to be written in the DPR +{ + pUDP->UDP_FDR[endpoint] = value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpRead +//* \brief Return value from the DPR +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_EpRead( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + return pUDP->UDP_FDR[endpoint]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpEndOfWr +//* \brief Notify the UDP that values in DPR are ready to be sent +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpEndOfWr( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpClear +//* \brief Clear flag in the endpoint CSR register +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpClear( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned int flag) // \arg flag to be cleared +{ + pUDP->UDP_CSR[endpoint] &= ~(flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpSet +//* \brief Set flag in the endpoint CSR register +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpSet( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned int flag) // \arg flag to be cleared +{ + pUDP->UDP_CSR[endpoint] |= flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpStatus +//* \brief Return the endpoint CSR register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_EpStatus( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + return pUDP->UDP_CSR[endpoint]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_GetInterruptMaskStatus +//* \brief Return UDP Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status + AT91PS_UDP pUdp) // \arg pointer to a UDP controller +{ + return pUdp->UDP_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_IsInterruptMasked +//* \brief Test if UDP Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_UDP_IsInterruptMasked( + AT91PS_UDP pUdp, // \arg pointer to a UDP controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR TC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_InterruptEnable +//* \brief Enable TC Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TC_InterruptEnable( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg TC interrupt to be enabled +{ + pTc->TC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_InterruptDisable +//* \brief Disable TC Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TC_InterruptDisable( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg TC interrupt to be disabled +{ + pTc->TC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_GetInterruptMaskStatus +//* \brief Return TC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status + AT91PS_TC pTc) // \arg pointer to a TC controller +{ + return pTc->TC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_IsInterruptMasked +//* \brief Test if TC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_TC_IsInterruptMasked( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR CAN + ***************************************************************************** */ +#define STANDARD_FORMAT 0 +#define EXTENDED_FORMAT 1 + +//*---------------------------------------------------------------------------- +//* \fn AT91F_InitMailboxRegisters() +//* \brief Configure the corresponding mailbox +//*---------------------------------------------------------------------------- +__inline void AT91F_InitMailboxRegisters(AT91PS_CAN_MB CAN_Mailbox, + int mode_reg, + int acceptance_mask_reg, + int id_reg, + int data_low_reg, + int data_high_reg, + int control_reg) +{ + CAN_Mailbox->CAN_MB_MCR = 0x0; + CAN_Mailbox->CAN_MB_MMR = mode_reg; + CAN_Mailbox->CAN_MB_MAM = acceptance_mask_reg; + CAN_Mailbox->CAN_MB_MID = id_reg; + CAN_Mailbox->CAN_MB_MDL = data_low_reg; + CAN_Mailbox->CAN_MB_MDH = data_high_reg; + CAN_Mailbox->CAN_MB_MCR = control_reg; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_EnableCAN() +//* \brief +//*---------------------------------------------------------------------------- +__inline void AT91F_EnableCAN( + AT91PS_CAN pCAN) // pointer to a CAN controller +{ + pCAN->CAN_MR |= AT91C_CAN_CANEN; + + // Wait for WAKEUP flag raising <=> 11-recessive-bit were scanned by the transceiver + while( (pCAN->CAN_SR & AT91C_CAN_WAKEUP) != AT91C_CAN_WAKEUP ); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DisableCAN() +//* \brief +//*---------------------------------------------------------------------------- +__inline void AT91F_DisableCAN( + AT91PS_CAN pCAN) // pointer to a CAN controller +{ + pCAN->CAN_MR &= ~AT91C_CAN_CANEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_EnableIt +//* \brief Enable CAN interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_EnableIt ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pCAN->CAN_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_DisableIt +//* \brief Disable CAN interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_DisableIt ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pCAN->CAN_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetStatus +//* \brief Return CAN Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetStatus( // \return CAN Interrupt Status + AT91PS_CAN pCAN) // pointer to a CAN controller +{ + return pCAN->CAN_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetInterruptMaskStatus +//* \brief Return CAN Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetInterruptMaskStatus( // \return CAN Interrupt Mask Status + AT91PS_CAN pCAN) // pointer to a CAN controller +{ + return pCAN->CAN_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_IsInterruptMasked +//* \brief Test if CAN Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_IsInterruptMasked( + AT91PS_CAN pCAN, // \arg pointer to a CAN controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_CAN_GetInterruptMaskStatus(pCAN) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_IsStatusSet +//* \brief Test if CAN Interrupt is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_IsStatusSet( + AT91PS_CAN pCAN, // \arg pointer to a CAN controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_CAN_GetStatus(pCAN) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgModeReg +//* \brief Configure the Mode Register of the CAN controller +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgModeReg ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int mode) // mode register +{ + //* Write to the MR register + pCAN->CAN_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetModeReg +//* \brief Return the Mode Register of the CAN controller value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetModeReg ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_MR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgBaudrateReg +//* \brief Configure the Baudrate of the CAN controller for the network +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgBaudrateReg ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int baudrate_cfg) +{ + //* Write to the BR register + pCAN->CAN_BR = baudrate_cfg; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetBaudrate +//* \brief Return the Baudrate of the CAN controller for the network value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetBaudrate ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_BR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetInternalCounter +//* \brief Return CAN Timer Regsiter Value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetInternalCounter ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_TIM; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetTimestamp +//* \brief Return CAN Timestamp Register Value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetTimestamp ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_TIMESTP; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetErrorCounter +//* \brief Return CAN Error Counter Register Value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetErrorCounter ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_ECR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_InitTransferRequest +//* \brief Request for a transfer on the corresponding mailboxes +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_InitTransferRequest ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int transfer_cmd) +{ + pCAN->CAN_TCR = transfer_cmd; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_InitAbortRequest +//* \brief Abort the corresponding mailboxes +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_InitAbortRequest ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int abort_cmd) +{ + pCAN->CAN_ACR = abort_cmd; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageModeReg +//* \brief Program the Message Mode Register +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageModeReg ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int mode) +{ + CAN_Mailbox->CAN_MB_MMR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageModeReg +//* \brief Return the Message Mode Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageModeReg ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageIDReg +//* \brief Program the Message ID Register +//* \brief Version == 0 for Standard messsage, Version == 1 for Extended +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageIDReg ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int id, + unsigned char version) +{ + if(version==0) // IDvA Standard Format + CAN_Mailbox->CAN_MB_MID = id<<18; + else // IDvB Extended Format + CAN_Mailbox->CAN_MB_MID = id | (1<<29); // set MIDE bit +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageIDReg +//* \brief Return the Message ID Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageIDReg ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MID; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageAcceptanceMaskReg +//* \brief Program the Message Acceptance Mask Register +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageAcceptanceMaskReg ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int mask) +{ + CAN_Mailbox->CAN_MB_MAM = mask; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageAcceptanceMaskReg +//* \brief Return the Message Acceptance Mask Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageAcceptanceMaskReg ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MAM; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetFamilyID +//* \brief Return the Message ID Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetFamilyID ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MFID; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageCtrl +//* \brief Request and config for a transfer on the corresponding mailbox +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageCtrlReg ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int message_ctrl_cmd) +{ + CAN_Mailbox->CAN_MB_MCR = message_ctrl_cmd; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageStatus +//* \brief Return CAN Mailbox Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageStatus ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageDataLow +//* \brief Program data low value +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageDataLow ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int data) +{ + CAN_Mailbox->CAN_MB_MDL = data; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageDataLow +//* \brief Return data low value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageDataLow ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MDL; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageDataHigh +//* \brief Program data high value +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageDataHigh ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int data) +{ + CAN_Mailbox->CAN_MB_MDH = data; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageDataHigh +//* \brief Return data high value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageDataHigh ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MDH; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_Open +//* \brief Open a CAN Port +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_Open ( + const unsigned int null) // \arg +{ + /* NOT DEFINED AT THIS MOMENT */ + return ( 0 ); +} +/* ***************************************************************************** + SOFTWARE API FOR ADC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_EnableIt +//* \brief Enable ADC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_EnableIt ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pADC->ADC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_DisableIt +//* \brief Disable ADC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_DisableIt ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pADC->ADC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetStatus +//* \brief Return ADC Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status + AT91PS_ADC pADC) // pointer to a ADC controller +{ + return pADC->ADC_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetInterruptMaskStatus +//* \brief Return ADC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status + AT91PS_ADC pADC) // pointer to a ADC controller +{ + return pADC->ADC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_IsInterruptMasked +//* \brief Test if ADC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_IsInterruptMasked( + AT91PS_ADC pADC, // \arg pointer to a ADC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_IsStatusSet +//* \brief Test if ADC Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_IsStatusSet( + AT91PS_ADC pADC, // \arg pointer to a ADC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_ADC_GetStatus(pADC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgModeReg +//* \brief Configure the Mode Register of the ADC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgModeReg ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int mode) // mode register +{ + //* Write to the MR register + pADC->ADC_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetModeReg +//* \brief Return the Mode Register of the ADC controller value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetModeReg ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_MR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgTimings +//* \brief Configure the different necessary timings of the ADC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgTimings ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int mck_clock, // in MHz + unsigned int adc_clock, // in MHz + unsigned int startup_time, // in us + unsigned int sample_and_hold_time) // in ns +{ + unsigned int prescal,startup,shtim; + + prescal = mck_clock/(2*adc_clock) - 1; + startup = adc_clock*startup_time/8 - 1; + shtim = adc_clock*sample_and_hold_time/1000 - 1; + + //* Write to the MR register + pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_EnableChannel +//* \brief Return ADC Timer Register Value +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_EnableChannel ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int channel) // mode register +{ + //* Write to the CHER register + pADC->ADC_CHER = channel; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_DisableChannel +//* \brief Return ADC Timer Register Value +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_DisableChannel ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int channel) // mode register +{ + //* Write to the CHDR register + pADC->ADC_CHDR = channel; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetChannelStatus +//* \brief Return ADC Timer Register Value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetChannelStatus ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CHSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_StartConversion +//* \brief Software request for a analog to digital conversion +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_StartConversion ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + pADC->ADC_CR = AT91C_ADC_START; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_SoftReset +//* \brief Software reset +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_SoftReset ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + pADC->ADC_CR = AT91C_ADC_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetLastConvertedData +//* \brief Return the Last Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetLastConvertedData ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_LCDR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH0 +//* \brief Return the Channel 0 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH0 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR0; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH1 +//* \brief Return the Channel 1 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH1 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR1; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH2 +//* \brief Return the Channel 2 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH2 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR2; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH3 +//* \brief Return the Channel 3 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH3 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR3; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH4 +//* \brief Return the Channel 4 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH4 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR4; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH5 +//* \brief Return the Channel 5 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH5 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR5; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH6 +//* \brief Return the Channel 6 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH6 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR6; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH7 +//* \brief Return the Channel 7 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH7 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR7; +} + +/* ***************************************************************************** + SOFTWARE API FOR AES + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_EnableIt +//* \brief Enable AES interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_EnableIt ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pAES->AES_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_DisableIt +//* \brief Disable AES interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_DisableIt ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pAES->AES_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_GetStatus +//* \brief Return AES Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_GetStatus( // \return AES Interrupt Status + AT91PS_AES pAES) // pointer to a AES controller +{ + return pAES->AES_ISR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_GetInterruptMaskStatus +//* \brief Return AES Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_GetInterruptMaskStatus( // \return AES Interrupt Mask Status + AT91PS_AES pAES) // pointer to a AES controller +{ + return pAES->AES_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_IsInterruptMasked +//* \brief Test if AES Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_IsInterruptMasked( + AT91PS_AES pAES, // \arg pointer to a AES controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_AES_GetInterruptMaskStatus(pAES) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_IsStatusSet +//* \brief Test if AES Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_IsStatusSet( + AT91PS_AES pAES, // \arg pointer to a AES controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_AES_GetStatus(pAES) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_CfgModeReg +//* \brief Configure the Mode Register of the AES controller +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_CfgModeReg ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned int mode) // mode register +{ + //* Write to the MR register + pAES->AES_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_GetModeReg +//* \brief Return the Mode Register of the AES controller value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_GetModeReg ( + AT91PS_AES pAES // pointer to a AES controller + ) +{ + return pAES->AES_MR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_StartProcessing +//* \brief Start Encryption or Decryption +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_StartProcessing ( + AT91PS_AES pAES // pointer to a AES controller + ) +{ + pAES->AES_CR = AT91C_AES_START; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_SoftReset +//* \brief Reset AES +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_SoftReset ( + AT91PS_AES pAES // pointer to a AES controller + ) +{ + pAES->AES_CR = AT91C_AES_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_LoadNewSeed +//* \brief Load New Seed in the random number generator +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_LoadNewSeed ( + AT91PS_AES pAES // pointer to a AES controller + ) +{ + pAES->AES_CR = AT91C_AES_LOADSEED; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_SetCryptoKey +//* \brief Set Cryptographic Key x +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_SetCryptoKey ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned char index, + unsigned int keyword + ) +{ + pAES->AES_KEYWxR[index] = keyword; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_InputData +//* \brief Set Input Data x +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_InputData ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned char index, + unsigned int indata + ) +{ + pAES->AES_IDATAxR[index] = indata; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_GetOutputData +//* \brief Get Output Data x +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_GetOutputData ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned char index + ) +{ + return pAES->AES_ODATAxR[index]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_SetInitializationVector +//* \brief Set Initialization Vector (or Counter) x +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_SetInitializationVector ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned char index, + unsigned int initvector + ) +{ + pAES->AES_IVxR[index] = initvector; +} + +/* ***************************************************************************** + SOFTWARE API FOR TDES + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_EnableIt +//* \brief Enable TDES interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_EnableIt ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pTDES->TDES_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_DisableIt +//* \brief Disable TDES interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_DisableIt ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pTDES->TDES_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_GetStatus +//* \brief Return TDES Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_GetStatus( // \return TDES Interrupt Status + AT91PS_TDES pTDES) // pointer to a TDES controller +{ + return pTDES->TDES_ISR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_GetInterruptMaskStatus +//* \brief Return TDES Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_GetInterruptMaskStatus( // \return TDES Interrupt Mask Status + AT91PS_TDES pTDES) // pointer to a TDES controller +{ + return pTDES->TDES_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_IsInterruptMasked +//* \brief Test if TDES Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_IsInterruptMasked( + AT91PS_TDES pTDES, // \arg pointer to a TDES controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TDES_GetInterruptMaskStatus(pTDES) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_IsStatusSet +//* \brief Test if TDES Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_IsStatusSet( + AT91PS_TDES pTDES, // \arg pointer to a TDES controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TDES_GetStatus(pTDES) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_CfgModeReg +//* \brief Configure the Mode Register of the TDES controller +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_CfgModeReg ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned int mode) // mode register +{ + //* Write to the MR register + pTDES->TDES_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_GetModeReg +//* \brief Return the Mode Register of the TDES controller value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_GetModeReg ( + AT91PS_TDES pTDES // pointer to a TDES controller + ) +{ + return pTDES->TDES_MR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_StartProcessing +//* \brief Start Encryption or Decryption +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_StartProcessing ( + AT91PS_TDES pTDES // pointer to a TDES controller + ) +{ + pTDES->TDES_CR = AT91C_TDES_START; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SoftReset +//* \brief Reset TDES +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SoftReset ( + AT91PS_TDES pTDES // pointer to a TDES controller + ) +{ + pTDES->TDES_CR = AT91C_TDES_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SetCryptoKey1 +//* \brief Set Cryptographic Key 1 Word x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SetCryptoKey1 ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int keyword + ) +{ + pTDES->TDES_KEY1WxR[index] = keyword; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SetCryptoKey2 +//* \brief Set Cryptographic Key 2 Word x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SetCryptoKey2 ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int keyword + ) +{ + pTDES->TDES_KEY2WxR[index] = keyword; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SetCryptoKey3 +//* \brief Set Cryptographic Key 3 Word x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SetCryptoKey3 ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int keyword + ) +{ + pTDES->TDES_KEY3WxR[index] = keyword; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_InputData +//* \brief Set Input Data x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_InputData ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int indata + ) +{ + pTDES->TDES_IDATAxR[index] = indata; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_GetOutputData +//* \brief Get Output Data x +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_GetOutputData ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index + ) +{ + return pTDES->TDES_ODATAxR[index]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SetInitializationVector +//* \brief Set Initialization Vector x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SetInitializationVector ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int initvector + ) +{ + pTDES->TDES_IVxR[index] = initvector; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_CfgPMC +//* \brief Enable Peripheral clock in PMC for DBGU +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_CfgPIO +//* \brief Configure PIO controllers to drive DBGU signals +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA27_DRXD ) | + ((unsigned int) AT91C_PA28_DTXD ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgPMC +//* \brief Enable Peripheral clock in PMC for PMC +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgPIO +//* \brief Configure PIO controllers to drive PMC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB30_PCK2 ) | + ((unsigned int) AT91C_PB29_PCK1 ), // Peripheral A + ((unsigned int) AT91C_PB20_PCK0 ) | + ((unsigned int) AT91C_PB0_PCK0 ) | + ((unsigned int) AT91C_PB22_PCK2 ) | + ((unsigned int) AT91C_PB21_PCK1 )); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA30_PCK2 ) | + ((unsigned int) AT91C_PA13_PCK1 ) | + ((unsigned int) AT91C_PA27_PCK3 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_VREG_CfgPMC +//* \brief Enable Peripheral clock in PMC for VREG +//*---------------------------------------------------------------------------- +__inline void AT91F_VREG_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTC_CfgPMC +//* \brief Enable Peripheral clock in PMC for RSTC +//*---------------------------------------------------------------------------- +__inline void AT91F_RSTC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_CfgPMC +//* \brief Enable Peripheral clock in PMC for SSC +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SSC)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_CfgPIO +//* \brief Configure PIO controllers to drive SSC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA25_RK ) | + ((unsigned int) AT91C_PA22_TK ) | + ((unsigned int) AT91C_PA21_TF ) | + ((unsigned int) AT91C_PA24_RD ) | + ((unsigned int) AT91C_PA26_RF ) | + ((unsigned int) AT91C_PA23_TD ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTC_CfgPMC +//* \brief Enable Peripheral clock in PMC for WDTC +//*---------------------------------------------------------------------------- +__inline void AT91F_WDTC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US1_CfgPMC +//* \brief Enable Peripheral clock in PMC for US1 +//*---------------------------------------------------------------------------- +__inline void AT91F_US1_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_US1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US1_CfgPIO +//* \brief Configure PIO controllers to drive US1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_US1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PB26_RI1 ) | + ((unsigned int) AT91C_PB24_DSR1 ) | + ((unsigned int) AT91C_PB23_DCD1 ) | + ((unsigned int) AT91C_PB25_DTR1 )); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA7_SCK1 ) | + ((unsigned int) AT91C_PA8_RTS1 ) | + ((unsigned int) AT91C_PA6_TXD1 ) | + ((unsigned int) AT91C_PA5_RXD1 ) | + ((unsigned int) AT91C_PA9_CTS1 ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US0_CfgPMC +//* \brief Enable Peripheral clock in PMC for US0 +//*---------------------------------------------------------------------------- +__inline void AT91F_US0_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_US0)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US0_CfgPIO +//* \brief Configure PIO controllers to drive US0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_US0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA0_RXD0 ) | + ((unsigned int) AT91C_PA4_CTS0 ) | + ((unsigned int) AT91C_PA3_RTS0 ) | + ((unsigned int) AT91C_PA2_SCK0 ) | + ((unsigned int) AT91C_PA1_TXD0 ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI1_CfgPMC +//* \brief Enable Peripheral clock in PMC for SPI1 +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI1_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SPI1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI1_CfgPIO +//* \brief Configure PIO controllers to drive SPI1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PB16_NPCS13 ) | + ((unsigned int) AT91C_PB10_NPCS11 ) | + ((unsigned int) AT91C_PB11_NPCS12 )); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA4_NPCS13 ) | + ((unsigned int) AT91C_PA29_NPCS13 ) | + ((unsigned int) AT91C_PA21_NPCS10 ) | + ((unsigned int) AT91C_PA22_SPCK1 ) | + ((unsigned int) AT91C_PA25_NPCS11 ) | + ((unsigned int) AT91C_PA2_NPCS11 ) | + ((unsigned int) AT91C_PA24_MISO1 ) | + ((unsigned int) AT91C_PA3_NPCS12 ) | + ((unsigned int) AT91C_PA26_NPCS12 ) | + ((unsigned int) AT91C_PA23_MOSI1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI0_CfgPMC +//* \brief Enable Peripheral clock in PMC for SPI0 +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI0_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SPI0)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI0_CfgPIO +//* \brief Configure PIO controllers to drive SPI0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PB13_NPCS01 ) | + ((unsigned int) AT91C_PB17_NPCS03 ) | + ((unsigned int) AT91C_PB14_NPCS02 )); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA16_MISO0 ) | + ((unsigned int) AT91C_PA13_NPCS01 ) | + ((unsigned int) AT91C_PA15_NPCS03 ) | + ((unsigned int) AT91C_PA17_MOSI0 ) | + ((unsigned int) AT91C_PA18_SPCK0 ) | + ((unsigned int) AT91C_PA14_NPCS02 ) | + ((unsigned int) AT91C_PA12_NPCS00 ), // Peripheral A + ((unsigned int) AT91C_PA7_NPCS01 ) | + ((unsigned int) AT91C_PA9_NPCS03 ) | + ((unsigned int) AT91C_PA8_NPCS02 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITC_CfgPMC +//* \brief Enable Peripheral clock in PMC for PITC +//*---------------------------------------------------------------------------- +__inline void AT91F_PITC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_CfgPMC +//* \brief Enable Peripheral clock in PMC for AIC +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_FIQ) | + ((unsigned int) 1 << AT91C_ID_IRQ0) | + ((unsigned int) 1 << AT91C_ID_IRQ1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_CfgPIO +//* \brief Configure PIO controllers to drive AIC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA30_IRQ0 ) | + ((unsigned int) AT91C_PA29_FIQ ), // Peripheral A + ((unsigned int) AT91C_PA14_IRQ1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_CfgPMC +//* \brief Enable Peripheral clock in PMC for AES +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_AES)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_CfgPMC +//* \brief Enable Peripheral clock in PMC for TWI +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TWI)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_CfgPIO +//* \brief Configure PIO controllers to drive TWI signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA11_TWCK ) | + ((unsigned int) AT91C_PA10_TWD ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgPMC +//* \brief Enable Peripheral clock in PMC for ADC +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_ADC)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgPIO +//* \brief Configure PIO controllers to drive ADC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PB18_ADTRG )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH3_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH3 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH3_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB22_PWM3 ), // Peripheral A + ((unsigned int) AT91C_PB30_PWM3 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH2_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH2 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH2_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB21_PWM2 ), // Peripheral A + ((unsigned int) AT91C_PB29_PWM2 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH1_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB20_PWM1 ), // Peripheral A + ((unsigned int) AT91C_PB28_PWM1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH0_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB19_PWM0 ), // Peripheral A + ((unsigned int) AT91C_PB27_PWM0 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RTTC_CfgPMC +//* \brief Enable Peripheral clock in PMC for RTTC +//*---------------------------------------------------------------------------- +__inline void AT91F_RTTC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_CfgPMC +//* \brief Enable Peripheral clock in PMC for UDP +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_UDP)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_CfgPMC +//* \brief Enable Peripheral clock in PMC for TDES +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TDES)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_EMAC_CfgPMC +//* \brief Enable Peripheral clock in PMC for EMAC +//*---------------------------------------------------------------------------- +__inline void AT91F_EMAC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_EMAC)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_EMAC_CfgPIO +//* \brief Configure PIO controllers to drive EMAC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_EMAC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB2_ETX0 ) | + ((unsigned int) AT91C_PB12_ETXER ) | + ((unsigned int) AT91C_PB16_ECOL ) | + ((unsigned int) AT91C_PB11_ETX3 ) | + ((unsigned int) AT91C_PB6_ERX1 ) | + ((unsigned int) AT91C_PB15_ERXDV ) | + ((unsigned int) AT91C_PB13_ERX2 ) | + ((unsigned int) AT91C_PB3_ETX1 ) | + ((unsigned int) AT91C_PB8_EMDC ) | + ((unsigned int) AT91C_PB5_ERX0 ) | + //((unsigned int) AT91C_PB18_EF100 ) | + ((unsigned int) AT91C_PB14_ERX3 ) | + ((unsigned int) AT91C_PB4_ECRS_ECRSDV) | + ((unsigned int) AT91C_PB1_ETXEN ) | + ((unsigned int) AT91C_PB10_ETX2 ) | + ((unsigned int) AT91C_PB0_ETXCK_EREFCK) | + ((unsigned int) AT91C_PB9_EMDIO ) | + ((unsigned int) AT91C_PB7_ERXER ) | + ((unsigned int) AT91C_PB17_ERXCK ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC0_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC0 +//*---------------------------------------------------------------------------- +__inline void AT91F_TC0_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC0)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC0_CfgPIO +//* \brief Configure PIO controllers to drive TC0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TC0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB23_TIOA0 ) | + ((unsigned int) AT91C_PB24_TIOB0 ), // Peripheral A + ((unsigned int) AT91C_PB12_TCLK0 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC1_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC1 +//*---------------------------------------------------------------------------- +__inline void AT91F_TC1_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC1_CfgPIO +//* \brief Configure PIO controllers to drive TC1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TC1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB25_TIOA1 ) | + ((unsigned int) AT91C_PB26_TIOB1 ), // Peripheral A + ((unsigned int) AT91C_PB19_TCLK1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC2_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC2 +//*---------------------------------------------------------------------------- +__inline void AT91F_TC2_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC2)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC2_CfgPIO +//* \brief Configure PIO controllers to drive TC2 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TC2_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB28_TIOB2 ) | + ((unsigned int) AT91C_PB27_TIOA2 ), // Peripheral A + 0); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA15_TCLK2 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_CfgPMC +//* \brief Enable Peripheral clock in PMC for MC +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIOA_CfgPMC +//* \brief Enable Peripheral clock in PMC for PIOA +//*---------------------------------------------------------------------------- +__inline void AT91F_PIOA_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_PIOA)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIOB_CfgPMC +//* \brief Enable Peripheral clock in PMC for PIOB +//*---------------------------------------------------------------------------- +__inline void AT91F_PIOB_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_PIOB)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgPMC +//* \brief Enable Peripheral clock in PMC for CAN +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_CAN)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgPIO +//* \brief Configure PIO controllers to drive CAN signals +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA20_CANTX ) | + ((unsigned int) AT91C_PA19_CANRX ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CfgPMC +//* \brief Enable Peripheral clock in PMC for PWMC +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_PWMC)); +} + +#endif // lib_AT91SAM7X128_H diff --git a/20080212/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h b/20080212/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h new file mode 100644 index 000000000..02ee9008d --- /dev/null +++ b/20080212/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h @@ -0,0 +1,4558 @@ +//* ---------------------------------------------------------------------------- +//* ATMEL Microcontroller Software Support - ROUSSET - +//* ---------------------------------------------------------------------------- +//* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//* ---------------------------------------------------------------------------- +//* File Name : lib_AT91SAM7X256.h +//* Object : AT91SAM7X256 inlined functions +//* Generated : AT91 SW Application Group 05/20/2005 (16:22:29) +//* +//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// +//* CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005// +//* CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005// +//* CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004// +//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// +//* CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004// +//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// +//* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003// +//* CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004// +//* CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005// +//* CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005// +//* CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004// +//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003// +//* CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004// +//* CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005// +//* CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005// +//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// +//* CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004// +//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// +//* CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003// +//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// +//* CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002// +//* ---------------------------------------------------------------------------- + +#ifndef lib_AT91SAM7X256_H +#define lib_AT91SAM7X256_H + +/* ***************************************************************************** + SOFTWARE API FOR AIC + ***************************************************************************** */ +#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20] + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_ConfigureIt +//* \brief Interrupt Handler Initialization +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_ConfigureIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id, // \arg interrupt number to initialize + unsigned int priority, // \arg priority to give to the interrupt + unsigned int src_type, // \arg activation and sense of activation + void (*newHandler) (void) ) // \arg address of the interrupt handler +{ + unsigned int oldHandler; + unsigned int mask ; + + oldHandler = pAic->AIC_SVR[irq_id]; + + mask = 0x1 << irq_id ; + //* Disable the interrupt on the interrupt controller + pAic->AIC_IDCR = mask ; + //* Save the interrupt handler routine pointer and the interrupt priority + pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ; + //* Store the Source Mode Register + pAic->AIC_SMR[irq_id] = src_type | priority ; + //* Clear the interrupt on the interrupt controller + pAic->AIC_ICCR = mask ; + + return oldHandler; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_EnableIt +//* \brief Enable corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_EnableIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id ) // \arg interrupt number to initialize +{ + //* Enable the interrupt on the interrupt controller + pAic->AIC_IECR = 0x1 << irq_id ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_DisableIt +//* \brief Disable corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_DisableIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id ) // \arg interrupt number to initialize +{ + unsigned int mask = 0x1 << irq_id; + //* Disable the interrupt on the interrupt controller + pAic->AIC_IDCR = mask ; + //* Clear the interrupt on the Interrupt Controller ( if one is pending ) + pAic->AIC_ICCR = mask ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_ClearIt +//* \brief Clear corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_ClearIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg interrupt number to initialize +{ + //* Clear the interrupt on the Interrupt Controller ( if one is pending ) + pAic->AIC_ICCR = (0x1 << irq_id); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_AcknowledgeIt +//* \brief Acknowledge corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_AcknowledgeIt ( + AT91PS_AIC pAic) // \arg pointer to the AIC registers +{ + pAic->AIC_EOICR = pAic->AIC_EOICR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_SetExceptionVector +//* \brief Configure vector handler +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_SetExceptionVector ( + unsigned int *pVector, // \arg pointer to the AIC registers + void (*Handler) () ) // \arg Interrupt Handler +{ + unsigned int oldVector = *pVector; + + if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE) + *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE; + else + *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000; + + return oldVector; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_Trig +//* \brief Trig an IT +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_Trig ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg interrupt number +{ + pAic->AIC_ISCR = (0x1 << irq_id) ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_IsActive +//* \brief Test if an IT is active +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_IsActive ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg Interrupt Number +{ + return (pAic->AIC_ISR & (0x1 << irq_id)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_IsPending +//* \brief Test if an IT is pending +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_IsPending ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg Interrupt Number +{ + return (pAic->AIC_IPR & (0x1 << irq_id)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_Open +//* \brief Set exception vectors and AIC registers to default values +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_Open( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + void (*IrqHandler) (), // \arg Default IRQ vector exception + void (*FiqHandler) (), // \arg Default FIQ vector exception + void (*DefaultHandler) (), // \arg Default Handler set in ISR + void (*SpuriousHandler) (), // \arg Default Spurious Handler + unsigned int protectMode) // \arg Debug Control Register +{ + int i; + + // Disable all interrupts and set IVR to the default handler + for (i = 0; i < 32; ++i) { + AT91F_AIC_DisableIt(pAic, i); + AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler); + } + + // Set the IRQ exception vector + AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler); + // Set the Fast Interrupt exception vector + AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler); + + pAic->AIC_SPU = (unsigned int) SpuriousHandler; + pAic->AIC_DCR = protectMode; +} +/* ***************************************************************************** + SOFTWARE API FOR PDC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetNextRx +//* \brief Set the next receive transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetNextRx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be received + unsigned int bytes) // \arg number of bytes to be received +{ + pPDC->PDC_RNPR = (unsigned int) address; + pPDC->PDC_RNCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetNextTx +//* \brief Set the next transmit transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetNextTx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be transmitted + unsigned int bytes) // \arg number of bytes to be transmitted +{ + pPDC->PDC_TNPR = (unsigned int) address; + pPDC->PDC_TNCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetRx +//* \brief Set the receive transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetRx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be received + unsigned int bytes) // \arg number of bytes to be received +{ + pPDC->PDC_RPR = (unsigned int) address; + pPDC->PDC_RCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetTx +//* \brief Set the transmit transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetTx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be transmitted + unsigned int bytes) // \arg number of bytes to be transmitted +{ + pPDC->PDC_TPR = (unsigned int) address; + pPDC->PDC_TCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_EnableTx +//* \brief Enable transmit +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_EnableTx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_TXTEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_EnableRx +//* \brief Enable receive +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_EnableRx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_RXTEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_DisableTx +//* \brief Disable transmit +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_DisableTx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_TXTDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_DisableRx +//* \brief Disable receive +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_DisableRx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_RXTDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsTxEmpty +//* \brief Test if the current transfer descriptor has been sent +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_TCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsNextTxEmpty +//* \brief Test if the next transfer descriptor has been moved to the current td +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_TNCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsRxEmpty +//* \brief Test if the current transfer descriptor has been filled +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_RCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsNextRxEmpty +//* \brief Test if the next transfer descriptor has been moved to the current td +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_RNCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_Open +//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_Open ( + AT91PS_PDC pPDC) // \arg pointer to a PDC controller +{ + //* Disable the RX and TX PDC transfer requests + AT91F_PDC_DisableRx(pPDC); + AT91F_PDC_DisableTx(pPDC); + + //* Reset all Counter register Next buffer first + AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); + AT91F_PDC_SetTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetRx(pPDC, (char *) 0, 0); + + //* Enable the RX and TX PDC transfer requests + AT91F_PDC_EnableRx(pPDC); + AT91F_PDC_EnableTx(pPDC); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_Close +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_Close ( + AT91PS_PDC pPDC) // \arg pointer to a PDC controller +{ + //* Disable the RX and TX PDC transfer requests + AT91F_PDC_DisableRx(pPDC); + AT91F_PDC_DisableTx(pPDC); + + //* Reset all Counter register Next buffer first + AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); + AT91F_PDC_SetTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetRx(pPDC, (char *) 0, 0); + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SendFrame +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PDC_SendFrame( + AT91PS_PDC pPDC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + if (AT91F_PDC_IsTxEmpty(pPDC)) { + //* Buffer and next buffer can be initialized + AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer); + AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer); + return 2; + } + else if (AT91F_PDC_IsNextTxEmpty(pPDC)) { + //* Only one buffer can be initialized + AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer); + return 1; + } + else { + //* All buffer are in use... + return 0; + } +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_ReceiveFrame +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PDC_ReceiveFrame ( + AT91PS_PDC pPDC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + if (AT91F_PDC_IsRxEmpty(pPDC)) { + //* Buffer and next buffer can be initialized + AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer); + AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer); + return 2; + } + else if (AT91F_PDC_IsNextRxEmpty(pPDC)) { + //* Only one buffer can be initialized + AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer); + return 1; + } + else { + //* All buffer are in use... + return 0; + } +} +/* ***************************************************************************** + SOFTWARE API FOR DBGU + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_InterruptEnable +//* \brief Enable DBGU Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_InterruptEnable( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg dbgu interrupt to be enabled +{ + pDbgu->DBGU_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_InterruptDisable +//* \brief Disable DBGU Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_InterruptDisable( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg dbgu interrupt to be disabled +{ + pDbgu->DBGU_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_GetInterruptMaskStatus +//* \brief Return DBGU Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status + AT91PS_DBGU pDbgu) // \arg pointer to a DBGU controller +{ + return pDbgu->DBGU_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_IsInterruptMasked +//* \brief Test if DBGU Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_DBGU_IsInterruptMasked( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR PIO + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgPeriph +//* \brief Enable pins to be drived by peripheral +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgPeriph( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int periphAEnable, // \arg PERIPH A to enable + unsigned int periphBEnable) // \arg PERIPH B to enable + +{ + pPio->PIO_ASR = periphAEnable; + pPio->PIO_BSR = periphBEnable; + pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgOutput +//* \brief Enable PIO in output mode +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int pioEnable) // \arg PIO to be enabled +{ + pPio->PIO_PER = pioEnable; // Set in PIO mode + pPio->PIO_OER = pioEnable; // Configure in Output +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgInput +//* \brief Enable PIO in input mode +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgInput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int inputEnable) // \arg PIO to be enabled +{ + // Disable output + pPio->PIO_ODR = inputEnable; + pPio->PIO_PER = inputEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgOpendrain +//* \brief Configure PIO in open drain +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgOpendrain( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int multiDrvEnable) // \arg pio to be configured in open drain +{ + // Configure the multi-drive option + pPio->PIO_MDDR = ~multiDrvEnable; + pPio->PIO_MDER = multiDrvEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgPullup +//* \brief Enable pullup on PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgPullup( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int pullupEnable) // \arg enable pullup on PIO +{ + // Connect or not Pullup + pPio->PIO_PPUDR = ~pullupEnable; + pPio->PIO_PPUER = pullupEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgDirectDrive +//* \brief Enable direct drive on PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgDirectDrive( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int directDrive) // \arg PIO to be configured with direct drive + +{ + // Configure the Direct Drive + pPio->PIO_OWDR = ~directDrive; + pPio->PIO_OWER = directDrive; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgInputFilter +//* \brief Enable input filter on input PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgInputFilter( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int inputFilter) // \arg PIO to be configured with input filter + +{ + // Configure the Direct Drive + pPio->PIO_IFDR = ~inputFilter; + pPio->PIO_IFER = inputFilter; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInput +//* \brief Return PIO input value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInput( // \return PIO input + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PDSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInputSet +//* \brief Test if PIO is input flag is active +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInputSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInput(pPio) & flag); +} + + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_SetOutput +//* \brief Set to 1 output PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_SetOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be set +{ + pPio->PIO_SODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_ClearOutput +//* \brief Set to 0 output PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_ClearOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be cleared +{ + pPio->PIO_CODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_ForceOutput +//* \brief Force output when Direct drive option is enabled +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_ForceOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be forced +{ + pPio->PIO_ODSR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Enable +//* \brief Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_Enable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be enabled +{ + pPio->PIO_PER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Disable +//* \brief Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_Disable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be disabled +{ + pPio->PIO_PDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetStatus +//* \brief Return PIO Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsSet +//* \brief Test if PIO is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputEnable +//* \brief Output Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output to be enabled +{ + pPio->PIO_OER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputDisable +//* \brief Output Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output to be disabled +{ + pPio->PIO_ODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputStatus +//* \brief Return PIO Output Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_OSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOuputSet +//* \brief Test if PIO Output is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsOutputSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InputFilterEnable +//* \brief Input Filter Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InputFilterEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio input filter to be enabled +{ + pPio->PIO_IFER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InputFilterDisable +//* \brief Input Filter Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InputFilterDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio input filter to be disabled +{ + pPio->PIO_IFDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInputFilterStatus +//* \brief Return PIO Input Filter Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_IFSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInputFilterSet +//* \brief Test if PIO Input filter is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInputFilterSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInputFilterStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputDataStatus +//* \brief Return PIO Output Data Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ODSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InterruptEnable +//* \brief Enable PIO Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InterruptEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio interrupt to be enabled +{ + pPio->PIO_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InterruptDisable +//* \brief Disable PIO Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InterruptDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio interrupt to be disabled +{ + pPio->PIO_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInterruptMaskStatus +//* \brief Return PIO Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInterruptStatus +//* \brief Return PIO Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ISR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInterruptMasked +//* \brief Test if PIO Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInterruptMasked( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInterruptSet +//* \brief Test if PIO Interrupt is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInterruptSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInterruptStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_MultiDriverEnable +//* \brief Multi Driver Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_MultiDriverEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be enabled +{ + pPio->PIO_MDER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_MultiDriverDisable +//* \brief Multi Driver Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_MultiDriverDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be disabled +{ + pPio->PIO_MDDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetMultiDriverStatus +//* \brief Return PIO Multi Driver Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_MDSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsMultiDriverSet +//* \brief Test if PIO MultiDriver is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsMultiDriverSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_A_RegisterSelection +//* \brief PIO A Register Selection +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_A_RegisterSelection( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio A register selection +{ + pPio->PIO_ASR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_B_RegisterSelection +//* \brief PIO B Register Selection +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_B_RegisterSelection( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio B register selection +{ + pPio->PIO_BSR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Get_AB_RegisterStatus +//* \brief Return PIO Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ABSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsAB_RegisterSet +//* \brief Test if PIO AB Register is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsAB_RegisterSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputWriteEnable +//* \brief Output Write Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputWriteEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output write to be enabled +{ + pPio->PIO_OWER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputWriteDisable +//* \brief Output Write Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputWriteDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output write to be disabled +{ + pPio->PIO_OWDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputWriteStatus +//* \brief Return PIO Output Write Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_OWSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOutputWriteSet +//* \brief Test if PIO OutputWrite is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsOutputWriteSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetCfgPullup +//* \brief Return PIO Configuration Pullup +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PPUSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOutputDataStatusSet +//* \brief Test if PIO Output Data Status is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsOutputDataStatusSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputDataStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsCfgPullupStatusSet +//* \brief Test if PIO Configuration Pullup Status is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsCfgPullupStatusSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (~AT91F_PIO_GetCfgPullup(pPio) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR PMC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgSysClkEnableReg +//* \brief Configure the System Clock Enable Register of the PMC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgSysClkEnableReg ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int mode) +{ + //* Write to the SCER register + pPMC->PMC_SCER = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgSysClkDisableReg +//* \brief Configure the System Clock Disable Register of the PMC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgSysClkDisableReg ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int mode) +{ + //* Write to the SCDR register + pPMC->PMC_SCDR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetSysClkStatusReg +//* \brief Return the System Clock Status Register of the PMC controller +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetSysClkStatusReg ( + AT91PS_PMC pPMC // pointer to a CAN controller + ) +{ + return pPMC->PMC_SCSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnablePeriphClock +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_EnablePeriphClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int periphIds) // \arg IDs of peripherals to enable +{ + pPMC->PMC_PCER = periphIds; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisablePeriphClock +//* \brief Disable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_DisablePeriphClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int periphIds) // \arg IDs of peripherals to enable +{ + pPMC->PMC_PCDR = periphIds; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetPeriphClock +//* \brief Get peripheral clock status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetPeriphClock ( + AT91PS_PMC pPMC) // \arg pointer to PMC controller +{ + return pPMC->PMC_PCSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_CfgMainOscillatorReg +//* \brief Cfg the main oscillator +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_CfgMainOscillatorReg ( + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int mode) +{ + pCKGR->CKGR_MOR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_GetMainOscillatorReg +//* \brief Cfg the main oscillator +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CKGR_GetMainOscillatorReg ( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + return pCKGR->CKGR_MOR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_EnableMainOscillator +//* \brief Enable the main oscillator +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_EnableMainOscillator( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_DisableMainOscillator +//* \brief Disable the main oscillator +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_DisableMainOscillator ( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_CfgMainOscStartUpTime +//* \brief Cfg MOR Register according to the main osc startup time +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_CfgMainOscStartUpTime ( + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int startup_time, // \arg main osc startup time in microsecond (us) + unsigned int slowClock) // \arg slowClock in Hz +{ + pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT; + pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_GetMainClockFreqReg +//* \brief Cfg the main oscillator +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CKGR_GetMainClockFreqReg ( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + return pCKGR->CKGR_MCFR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_GetMainClock +//* \brief Return Main clock in Hz +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CKGR_GetMainClock ( + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int slowClock) // \arg slowClock in Hz +{ + return ((pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF) * slowClock) >> 4; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgMCKReg +//* \brief Cfg Master Clock Register +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgMCKReg ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int mode) +{ + pPMC->PMC_MCKR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetMCKReg +//* \brief Return Master Clock Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetMCKReg( + AT91PS_PMC pPMC) // \arg pointer to PMC controller +{ + return pPMC->PMC_MCKR; +} + +//*------------------------------------------------------------------------------ +//* \fn AT91F_PMC_GetMasterClock +//* \brief Return master clock in Hz which correponds to processor clock for ARM7 +//*------------------------------------------------------------------------------ +__inline unsigned int AT91F_PMC_GetMasterClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int slowClock) // \arg slowClock in Hz +{ + unsigned int reg = pPMC->PMC_MCKR; + unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2)); + unsigned int pllDivider, pllMultiplier; + + switch (reg & AT91C_PMC_CSS) { + case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected + return slowClock / prescaler; + case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected + return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler; + case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected + reg = pCKGR->CKGR_PLLR; + pllDivider = (reg & AT91C_CKGR_DIV); + pllMultiplier = ((reg & AT91C_CKGR_MUL) >> 16) + 1; + return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler; + } + return 0; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnablePCK +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_EnablePCK ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int pck, // \arg Peripheral clock identifier 0 .. 7 + unsigned int mode) +{ + pPMC->PMC_PCKR[pck] = mode; + pPMC->PMC_SCER = (1 << pck) << 8; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisablePCK +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_DisablePCK ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int pck) // \arg Peripheral clock identifier 0 .. 7 +{ + pPMC->PMC_SCDR = (1 << pck) << 8; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnableIt +//* \brief Enable PMC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_EnableIt ( + AT91PS_PMC pPMC, // pointer to a PMC controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pPMC->PMC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisableIt +//* \brief Disable PMC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_DisableIt ( + AT91PS_PMC pPMC, // pointer to a PMC controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pPMC->PMC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetStatus +//* \brief Return PMC Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status + AT91PS_PMC pPMC) // pointer to a PMC controller +{ + return pPMC->PMC_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetInterruptMaskStatus +//* \brief Return PMC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status + AT91PS_PMC pPMC) // pointer to a PMC controller +{ + return pPMC->PMC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_IsInterruptMasked +//* \brief Test if PMC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_IsInterruptMasked( + AT91PS_PMC pPMC, // \arg pointer to a PMC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_IsStatusSet +//* \brief Test if PMC Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_IsStatusSet( + AT91PS_PMC pPMC, // \arg pointer to a PMC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PMC_GetStatus(pPMC) & flag); +}/* ***************************************************************************** + SOFTWARE API FOR RSTC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTSoftReset +//* \brief Start Software Reset +//*---------------------------------------------------------------------------- +__inline void AT91F_RSTSoftReset( + AT91PS_RSTC pRSTC, + unsigned int reset) +{ + pRSTC->RSTC_RCR = (0xA5000000 | reset); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTSetMode +//* \brief Set Reset Mode +//*---------------------------------------------------------------------------- +__inline void AT91F_RSTSetMode( + AT91PS_RSTC pRSTC, + unsigned int mode) +{ + pRSTC->RSTC_RMR = (0xA5000000 | mode); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTGetMode +//* \brief Get Reset Mode +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_RSTGetMode( + AT91PS_RSTC pRSTC) +{ + return (pRSTC->RSTC_RMR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTGetStatus +//* \brief Get Reset Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_RSTGetStatus( + AT91PS_RSTC pRSTC) +{ + return (pRSTC->RSTC_RSR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTIsSoftRstActive +//* \brief Return !=0 if software reset is still not completed +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_RSTIsSoftRstActive( + AT91PS_RSTC pRSTC) +{ + return ((pRSTC->RSTC_RSR) & AT91C_RSTC_SRCMP); +} +/* ***************************************************************************** + SOFTWARE API FOR RTTC + ***************************************************************************** */ +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_SetRTT_TimeBase() +//* \brief Set the RTT prescaler according to the TimeBase in ms +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTSetTimeBase( + AT91PS_RTTC pRTTC, + unsigned int ms) +{ + if (ms > 2000) + return 1; // AT91C_TIME_OUT_OF_RANGE + pRTTC->RTTC_RTMR &= ~0xFFFF; + pRTTC->RTTC_RTMR |= (((ms << 15) /1000) & 0xFFFF); + return 0; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTTSetPrescaler() +//* \brief Set the new prescaler value +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTSetPrescaler( + AT91PS_RTTC pRTTC, + unsigned int rtpres) +{ + pRTTC->RTTC_RTMR &= ~0xFFFF; + pRTTC->RTTC_RTMR |= (rtpres & 0xFFFF); + return (pRTTC->RTTC_RTMR); +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTTRestart() +//* \brief Restart the RTT prescaler +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTRestart( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST; +} + + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_SetAlarmINT() +//* \brief Enable RTT Alarm Interrupt +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTSetAlarmINT( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_ClearAlarmINT() +//* \brief Disable RTT Alarm Interrupt +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTClearAlarmINT( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_SetRttIncINT() +//* \brief Enable RTT INC Interrupt +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTSetRttIncINT( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_ClearRttIncINT() +//* \brief Disable RTT INC Interrupt +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTClearRttIncINT( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_SetAlarmValue() +//* \brief Set RTT Alarm Value +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTSetAlarmValue( + AT91PS_RTTC pRTTC, unsigned int alarm) +{ + pRTTC->RTTC_RTAR = alarm; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_GetAlarmValue() +//* \brief Get RTT Alarm Value +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTGetAlarmValue( + AT91PS_RTTC pRTTC) +{ + return(pRTTC->RTTC_RTAR); +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTTGetStatus() +//* \brief Read the RTT status +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTGetStatus( + AT91PS_RTTC pRTTC) +{ + return(pRTTC->RTTC_RTSR); +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_ReadValue() +//* \brief Read the RTT value +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTReadValue( + AT91PS_RTTC pRTTC) +{ + register volatile unsigned int val1,val2; + do + { + val1 = pRTTC->RTTC_RTVR; + val2 = pRTTC->RTTC_RTVR; + } + while(val1 != val2); + return(val1); +} +/* ***************************************************************************** + SOFTWARE API FOR PITC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITInit +//* \brief System timer init : period in µsecond, system clock freq in MHz +//*---------------------------------------------------------------------------- +__inline void AT91F_PITInit( + AT91PS_PITC pPITC, + unsigned int period, + unsigned int pit_frequency) +{ + pPITC->PITC_PIMR = period? (period * pit_frequency + 8) >> 4 : 0; // +8 to avoid %10 and /10 + pPITC->PITC_PIMR |= AT91C_PITC_PITEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITSetPIV +//* \brief Set the PIT Periodic Interval Value +//*---------------------------------------------------------------------------- +__inline void AT91F_PITSetPIV( + AT91PS_PITC pPITC, + unsigned int piv) +{ + pPITC->PITC_PIMR = piv | (pPITC->PITC_PIMR & (AT91C_PITC_PITEN | AT91C_PITC_PITIEN)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITEnableInt +//* \brief Enable PIT periodic interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PITEnableInt( + AT91PS_PITC pPITC) +{ + pPITC->PITC_PIMR |= AT91C_PITC_PITIEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITDisableInt +//* \brief Disable PIT periodic interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PITDisableInt( + AT91PS_PITC pPITC) +{ + pPITC->PITC_PIMR &= ~AT91C_PITC_PITIEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITGetMode +//* \brief Read PIT mode register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PITGetMode( + AT91PS_PITC pPITC) +{ + return(pPITC->PITC_PIMR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITGetStatus +//* \brief Read PIT status register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PITGetStatus( + AT91PS_PITC pPITC) +{ + return(pPITC->PITC_PISR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITGetPIIR +//* \brief Read PIT CPIV and PICNT without ressetting the counters +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PITGetPIIR( + AT91PS_PITC pPITC) +{ + return(pPITC->PITC_PIIR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITGetPIVR +//* \brief Read System timer CPIV and PICNT without ressetting the counters +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PITGetPIVR( + AT91PS_PITC pPITC) +{ + return(pPITC->PITC_PIVR); +} +/* ***************************************************************************** + SOFTWARE API FOR WDTC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTSetMode +//* \brief Set Watchdog Mode Register +//*---------------------------------------------------------------------------- +__inline void AT91F_WDTSetMode( + AT91PS_WDTC pWDTC, + unsigned int Mode) +{ + pWDTC->WDTC_WDMR = Mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTRestart +//* \brief Restart Watchdog +//*---------------------------------------------------------------------------- +__inline void AT91F_WDTRestart( + AT91PS_WDTC pWDTC) +{ + pWDTC->WDTC_WDCR = 0xA5000001; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTSGettatus +//* \brief Get Watchdog Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_WDTSGettatus( + AT91PS_WDTC pWDTC) +{ + return(pWDTC->WDTC_WDSR & 0x3); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTGetPeriod +//* \brief Translate ms into Watchdog Compatible value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_WDTGetPeriod(unsigned int ms) +{ + if ((ms < 4) || (ms > 16000)) + return 0; + return((ms << 8) / 1000); +} +/* ***************************************************************************** + SOFTWARE API FOR VREG + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_VREG_Enable_LowPowerMode +//* \brief Enable VREG Low Power Mode +//*---------------------------------------------------------------------------- +__inline void AT91F_VREG_Enable_LowPowerMode( + AT91PS_VREG pVREG) +{ + pVREG->VREG_MR |= AT91C_VREG_PSTDBY; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_VREG_Disable_LowPowerMode +//* \brief Disable VREG Low Power Mode +//*---------------------------------------------------------------------------- +__inline void AT91F_VREG_Disable_LowPowerMode( + AT91PS_VREG pVREG) +{ + pVREG->VREG_MR &= ~AT91C_VREG_PSTDBY; +}/* ***************************************************************************** + SOFTWARE API FOR MC + ***************************************************************************** */ + +#define AT91C_MC_CORRECT_KEY ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_Remap +//* \brief Make Remap +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_Remap (void) // +{ + AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC; + + pMC->MC_RCR = AT91C_MC_RCB; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_CfgModeReg +//* \brief Configure the EFC Mode Register of the MC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_EFC_CfgModeReg ( + AT91PS_MC pMC, // pointer to a MC controller + unsigned int mode) // mode register +{ + // Write to the FMR register + pMC->MC_FMR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_GetModeReg +//* \brief Return MC EFC Mode Regsiter +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_GetModeReg( + AT91PS_MC pMC) // pointer to a MC controller +{ + return pMC->MC_FMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_ComputeFMCN +//* \brief Return MC EFC Mode Regsiter +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_ComputeFMCN( + int master_clock) // master clock in Hz +{ + return (master_clock/1000000 +2); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_PerformCmd +//* \brief Perform EFC Command +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_EFC_PerformCmd ( + AT91PS_MC pMC, // pointer to a MC controller + unsigned int transfer_cmd) +{ + pMC->MC_FCR = transfer_cmd; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_GetStatus +//* \brief Return MC EFC Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_GetStatus( + AT91PS_MC pMC) // pointer to a MC controller +{ + return pMC->MC_FSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_IsInterruptMasked +//* \brief Test if EFC MC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_IsInterruptMasked( + AT91PS_MC pMC, // \arg pointer to a MC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_MC_EFC_GetModeReg(pMC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_IsInterruptSet +//* \brief Test if EFC MC Interrupt is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_IsInterruptSet( + AT91PS_MC pMC, // \arg pointer to a MC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_MC_EFC_GetStatus(pMC) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR SPI + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Open +//* \brief Open a SPI Port +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_Open ( + const unsigned int null) // \arg +{ + /* NOT DEFINED AT THIS MOMENT */ + return ( 0 ); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgCs +//* \brief Configure SPI chip select register +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgCs ( + AT91PS_SPI pSPI, // pointer to a SPI controller + int cs, // SPI cs number (0 to 3) + int val) // chip select register +{ + //* Write to the CSR register + *(pSPI->SPI_CSR + cs) = val; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_EnableIt +//* \brief Enable SPI interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_EnableIt ( + AT91PS_SPI pSPI, // pointer to a SPI controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pSPI->SPI_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_DisableIt +//* \brief Disable SPI interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_DisableIt ( + AT91PS_SPI pSPI, // pointer to a SPI controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pSPI->SPI_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Reset +//* \brief Reset the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Reset ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Enable +//* \brief Enable the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Enable ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SPIEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Disable +//* \brief Disable the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Disable ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SPIDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgMode +//* \brief Enable the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgMode ( + AT91PS_SPI pSPI, // pointer to a SPI controller + int mode) // mode register +{ + //* Write to the MR register + pSPI->SPI_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgPCS +//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgPCS ( + AT91PS_SPI pSPI, // pointer to a SPI controller + char PCS_Device) // PCS of the Device +{ + //* Write to the MR register + pSPI->SPI_MR &= 0xFFF0FFFF; + pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS ); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_ReceiveFrame ( + AT91PS_SPI pSPI, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pSPI->SPI_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_SendFrame( + AT91PS_SPI pSPI, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pSPI->SPI_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Close +//* \brief Close SPI: disable IT disable transfert, close PDC +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Close ( + AT91PS_SPI pSPI) // \arg pointer to a SPI controller +{ + //* Reset all the Chip Select register + pSPI->SPI_CSR[0] = 0 ; + pSPI->SPI_CSR[1] = 0 ; + pSPI->SPI_CSR[2] = 0 ; + pSPI->SPI_CSR[3] = 0 ; + + //* Reset the SPI mode + pSPI->SPI_MR = 0 ; + + //* Disable all interrupts + pSPI->SPI_IDR = 0xFFFFFFFF ; + + //* Abort the Peripheral Data Transfers + AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR)); + + //* Disable receiver and transmitter and stop any activity immediately + pSPI->SPI_CR = AT91C_SPI_SPIDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_PutChar +//* \brief Send a character,does not check if ready to send +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_PutChar ( + AT91PS_SPI pSPI, + unsigned int character, + unsigned int cs_number ) +{ + unsigned int value_for_cs; + value_for_cs = (~(1 << cs_number)) & 0xF; //Place a zero among a 4 ONEs number + pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_GetChar +//* \brief Receive a character,does not check if a character is available +//*---------------------------------------------------------------------------- +__inline int AT91F_SPI_GetChar ( + const AT91PS_SPI pSPI) +{ + return((pSPI->SPI_RDR) & 0xFFFF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_GetInterruptMaskStatus +//* \brief Return SPI Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status + AT91PS_SPI pSpi) // \arg pointer to a SPI controller +{ + return pSpi->SPI_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_IsInterruptMasked +//* \brief Test if SPI Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_SPI_IsInterruptMasked( + AT91PS_SPI pSpi, // \arg pointer to a SPI controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR USART + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Baudrate +//* \brief Calculate the baudrate +//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_EXT ) + +//* Standard Synchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \ + AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//* SCK used Label +#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT) + +//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity +#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \ + AT91C_US_CLKS_CLOCK +\ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_EVEN + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CKLO +\ + AT91C_US_OVER) + +//* Standard IRDA mode +#define AT91C_US_ASYNC_IRDA_MODE ( AT91C_US_USMODE_IRDA + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Baudrate +//* \brief Caluculate baud_value according to the main clock and the baud rate +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_Baudrate ( + const unsigned int main_clock, // \arg peripheral clock + const unsigned int baud_rate) // \arg UART baudrate +{ + unsigned int baud_value = ((main_clock*10)/(baud_rate * 16)); + if ((baud_value % 10) >= 5) + baud_value = (baud_value / 10) + 1; + else + baud_value /= 10; + return baud_value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetBaudrate +//* \brief Set the baudrate according to the CPU clock +//*---------------------------------------------------------------------------- +__inline void AT91F_US_SetBaudrate ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int mainClock, // \arg peripheral clock + unsigned int speed) // \arg UART baudrate +{ + //* Define the baud rate divisor register + pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetTimeguard +//* \brief Set USART timeguard +//*---------------------------------------------------------------------------- +__inline void AT91F_US_SetTimeguard ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int timeguard) // \arg timeguard value +{ + //* Write the Timeguard Register + pUSART->US_TTGR = timeguard ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableIt +//* \brief Enable USART IT +//*---------------------------------------------------------------------------- +__inline void AT91F_US_EnableIt ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pUSART->US_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableIt +//* \brief Disable USART IT +//*---------------------------------------------------------------------------- +__inline void AT91F_US_DisableIt ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IER register + pUSART->US_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Configure +//* \brief Configure USART +//*---------------------------------------------------------------------------- +__inline void AT91F_US_Configure ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int mainClock, // \arg peripheral clock + unsigned int mode , // \arg mode Register to be programmed + unsigned int baudRate , // \arg baudrate to be programmed + unsigned int timeguard ) // \arg timeguard to be programmed +{ + //* Disable interrupts + pUSART->US_IDR = (unsigned int) -1; + + //* Reset receiver and transmitter + pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ; + + //* Define the baud rate divisor register + AT91F_US_SetBaudrate(pUSART, mainClock, baudRate); + + //* Write the Timeguard Register + AT91F_US_SetTimeguard(pUSART, timeguard); + + //* Clear Transmit and Receive Counters + AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR)); + + //* Define the USART mode + pUSART->US_MR = mode ; + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableRx +//* \brief Enable receiving characters +//*---------------------------------------------------------------------------- +__inline void AT91F_US_EnableRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Enable receiver + pUSART->US_CR = AT91C_US_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableTx +//* \brief Enable sending characters +//*---------------------------------------------------------------------------- +__inline void AT91F_US_EnableTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Enable transmitter + pUSART->US_CR = AT91C_US_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ResetRx +//* \brief Reset Receiver and re-enable it +//*---------------------------------------------------------------------------- +__inline void AT91F_US_ResetRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset receiver + pUSART->US_CR = AT91C_US_RSTRX; + //* Re-Enable receiver + pUSART->US_CR = AT91C_US_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ResetTx +//* \brief Reset Transmitter and re-enable it +//*---------------------------------------------------------------------------- +__inline void AT91F_US_ResetTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset transmitter + pUSART->US_CR = AT91C_US_RSTTX; + //* Enable transmitter + pUSART->US_CR = AT91C_US_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableRx +//* \brief Disable Receiver +//*---------------------------------------------------------------------------- +__inline void AT91F_US_DisableRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Disable receiver + pUSART->US_CR = AT91C_US_RXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableTx +//* \brief Disable Transmitter +//*---------------------------------------------------------------------------- +__inline void AT91F_US_DisableTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Disable transmitter + pUSART->US_CR = AT91C_US_TXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Close +//* \brief Close USART: disable IT disable receiver and transmitter, close PDC +//*---------------------------------------------------------------------------- +__inline void AT91F_US_Close ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset the baud rate divisor register + pUSART->US_BRGR = 0 ; + + //* Reset the USART mode + pUSART->US_MR = 0 ; + + //* Reset the Timeguard Register + pUSART->US_TTGR = 0; + + //* Disable all interrupts + pUSART->US_IDR = 0xFFFFFFFF ; + + //* Abort the Peripheral Data Transfers + AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR)); + + //* Disable receiver and transmitter and stop any activity immediately + pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_TxReady +//* \brief Return 1 if a character can be written in US_THR +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_TxReady ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & AT91C_US_TXRDY); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_RxReady +//* \brief Return 1 if a character can be read in US_RHR +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_RxReady ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & AT91C_US_RXRDY); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Error +//* \brief Return the error flag +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_Error ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & + (AT91C_US_OVRE | // Overrun error + AT91C_US_FRAME | // Framing error + AT91C_US_PARE)); // Parity error +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_PutChar +//* \brief Send a character,does not check if ready to send +//*---------------------------------------------------------------------------- +__inline void AT91F_US_PutChar ( + AT91PS_USART pUSART, + int character ) +{ + pUSART->US_THR = (character & 0x1FF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_GetChar +//* \brief Receive a character,does not check if a character is available +//*---------------------------------------------------------------------------- +__inline int AT91F_US_GetChar ( + const AT91PS_USART pUSART) +{ + return((pUSART->US_RHR) & 0x1FF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_SendFrame( + AT91PS_USART pUSART, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pUSART->US_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_ReceiveFrame ( + AT91PS_USART pUSART, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pUSART->US_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetIrdaFilter +//* \brief Set the value of IrDa filter tregister +//*---------------------------------------------------------------------------- +__inline void AT91F_US_SetIrdaFilter ( + AT91PS_USART pUSART, + unsigned char value +) +{ + pUSART->US_IF = value; +} + +/* ***************************************************************************** + SOFTWARE API FOR SSC + ***************************************************************************** */ +//* Define the standard I2S mode configuration + +//* Configuration to set in the SSC Transmit Clock Mode Register +//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits +//* nb_slot_by_frame : number of channels +#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ + AT91C_SSC_CKS_DIV +\ + AT91C_SSC_CKO_CONTINOUS +\ + AT91C_SSC_CKG_NONE +\ + AT91C_SSC_START_FALL_RF +\ + AT91C_SSC_STTOUT +\ + ((1<<16) & AT91C_SSC_STTDLY) +\ + ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24)) + + +//* Configuration to set in the SSC Transmit Frame Mode Register +//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits +//* nb_slot_by_frame : number of channels +#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ + (nb_bit_by_slot-1) +\ + AT91C_SSC_MSBF +\ + (((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB) +\ + (((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\ + AT91C_SSC_FSOS_NEGATIVE) + + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_SetBaudrate +//* \brief Set the baudrate according to the CPU clock +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_SetBaudrate ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int mainClock, // \arg peripheral clock + unsigned int speed) // \arg SSC baudrate +{ + unsigned int baud_value; + //* Define the baud rate divisor register + if (speed == 0) + baud_value = 0; + else + { + baud_value = (unsigned int) (mainClock * 10)/(2*speed); + if ((baud_value % 10) >= 5) + baud_value = (baud_value / 10) + 1; + else + baud_value /= 10; + } + + pSSC->SSC_CMR = baud_value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_Configure +//* \brief Configure SSC +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_Configure ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int syst_clock, // \arg System Clock Frequency + unsigned int baud_rate, // \arg Expected Baud Rate Frequency + unsigned int clock_rx, // \arg Receiver Clock Parameters + unsigned int mode_rx, // \arg mode Register to be programmed + unsigned int clock_tx, // \arg Transmitter Clock Parameters + unsigned int mode_tx) // \arg mode Register to be programmed +{ + //* Disable interrupts + pSSC->SSC_IDR = (unsigned int) -1; + + //* Reset receiver and transmitter + pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ; + + //* Define the Clock Mode Register + AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate); + + //* Write the Receive Clock Mode Register + pSSC->SSC_RCMR = clock_rx; + + //* Write the Transmit Clock Mode Register + pSSC->SSC_TCMR = clock_tx; + + //* Write the Receive Frame Mode Register + pSSC->SSC_RFMR = mode_rx; + + //* Write the Transmit Frame Mode Register + pSSC->SSC_TFMR = mode_tx; + + //* Clear Transmit and Receive Counters + AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR)); + + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableRx +//* \brief Enable receiving datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_EnableRx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Enable receiver + pSSC->SSC_CR = AT91C_SSC_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableRx +//* \brief Disable receiving datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_DisableRx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Disable receiver + pSSC->SSC_CR = AT91C_SSC_RXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableTx +//* \brief Enable sending datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_EnableTx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Enable transmitter + pSSC->SSC_CR = AT91C_SSC_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableTx +//* \brief Disable sending datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_DisableTx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Disable transmitter + pSSC->SSC_CR = AT91C_SSC_TXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableIt +//* \brief Enable SSC IT +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_EnableIt ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pSSC->SSC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableIt +//* \brief Disable SSC IT +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_DisableIt ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pSSC->SSC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SSC_ReceiveFrame ( + AT91PS_SSC pSSC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pSSC->SSC_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SSC_SendFrame( + AT91PS_SSC pSSC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pSSC->SSC_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_GetInterruptMaskStatus +//* \brief Return SSC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status + AT91PS_SSC pSsc) // \arg pointer to a SSC controller +{ + return pSsc->SSC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_IsInterruptMasked +//* \brief Test if SSC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_SSC_IsInterruptMasked( + AT91PS_SSC pSsc, // \arg pointer to a SSC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR TWI + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_EnableIt +//* \brief Enable TWI IT +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_EnableIt ( + AT91PS_TWI pTWI, // \arg pointer to a TWI controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pTWI->TWI_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_DisableIt +//* \brief Disable TWI IT +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_DisableIt ( + AT91PS_TWI pTWI, // \arg pointer to a TWI controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pTWI->TWI_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_Configure +//* \brief Configure TWI in master mode +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI ) // \arg pointer to a TWI controller +{ + //* Disable interrupts + pTWI->TWI_IDR = (unsigned int) -1; + + //* Reset peripheral + pTWI->TWI_CR = AT91C_TWI_SWRST; + + //* Set Master mode + pTWI->TWI_CR = AT91C_TWI_MSEN; + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_GetInterruptMaskStatus +//* \brief Return TWI Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status + AT91PS_TWI pTwi) // \arg pointer to a TWI controller +{ + return pTwi->TWI_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_IsInterruptMasked +//* \brief Test if TWI Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_TWI_IsInterruptMasked( + AT91PS_TWI pTwi, // \arg pointer to a TWI controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR PWMC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_GetStatus +//* \brief Return PWM Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status + AT91PS_PWMC pPWM) // pointer to a PWM controller +{ + return pPWM->PWMC_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_InterruptEnable +//* \brief Enable PWM Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_InterruptEnable( + AT91PS_PWMC pPwm, // \arg pointer to a PWM controller + unsigned int flag) // \arg PWM interrupt to be enabled +{ + pPwm->PWMC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_InterruptDisable +//* \brief Disable PWM Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_InterruptDisable( + AT91PS_PWMC pPwm, // \arg pointer to a PWM controller + unsigned int flag) // \arg PWM interrupt to be disabled +{ + pPwm->PWMC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_GetInterruptMaskStatus +//* \brief Return PWM Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status + AT91PS_PWMC pPwm) // \arg pointer to a PWM controller +{ + return pPwm->PWMC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_IsInterruptMasked +//* \brief Test if PWM Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_IsInterruptMasked( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_IsStatusSet +//* \brief Test if PWM Interrupt is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_IsStatusSet( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PWMC_GetStatus(pPWM) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_CfgChannel +//* \brief Test if PWM Interrupt is Set +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CfgChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int channelId, // \arg PWM channel ID + unsigned int mode, // \arg PWM mode + unsigned int period, // \arg PWM period + unsigned int duty) // \arg PWM duty cycle +{ + pPWM->PWMC_CH[channelId].PWMC_CMR = mode; + pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty; + pPWM->PWMC_CH[channelId].PWMC_CPRDR = period; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_StartChannel +//* \brief Enable channel +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_StartChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg Channels IDs to be enabled +{ + pPWM->PWMC_ENA = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_StopChannel +//* \brief Disable channel +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_StopChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg Channels IDs to be enabled +{ + pPWM->PWMC_DIS = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_UpdateChannel +//* \brief Update Period or Duty Cycle +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_UpdateChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int channelId, // \arg PWM channel ID + unsigned int update) // \arg Channels IDs to be enabled +{ + pPWM->PWMC_CH[channelId].PWMC_CUPDR = update; +} + +/* ***************************************************************************** + SOFTWARE API FOR UDP + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EnableIt +//* \brief Enable UDP IT +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EnableIt ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pUDP->UDP_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_DisableIt +//* \brief Disable UDP IT +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_DisableIt ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pUDP->UDP_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_SetAddress +//* \brief Set UDP functional address +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_SetAddress ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char address) // \arg new UDP address +{ + pUDP->UDP_FADDR = (AT91C_UDP_FEN | address); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EnableEp +//* \brief Enable Endpoint +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EnableEp ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] |= AT91C_UDP_EPEDS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_DisableEp +//* \brief Enable Endpoint +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_DisableEp ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] &= ~AT91C_UDP_EPEDS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_SetState +//* \brief Set UDP Device state +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_SetState ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg new UDP address +{ + pUDP->UDP_GLBSTATE &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG); + pUDP->UDP_GLBSTATE |= flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_GetState +//* \brief return UDP Device state +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state + AT91PS_UDP pUDP) // \arg pointer to a UDP controller +{ + return (pUDP->UDP_GLBSTATE & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_ResetEp +//* \brief Reset UDP endpoint +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_ResetEp ( // \return the UDP device state + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg Endpoints to be reset +{ + pUDP->UDP_RSTEP = flag; + pUDP->UDP_RSTEP = 0; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpStall +//* \brief Endpoint will STALL requests +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpStall( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpWrite +//* \brief Write value in the DPR +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpWrite( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned char value) // \arg value to be written in the DPR +{ + pUDP->UDP_FDR[endpoint] = value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpRead +//* \brief Return value from the DPR +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_EpRead( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + return pUDP->UDP_FDR[endpoint]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpEndOfWr +//* \brief Notify the UDP that values in DPR are ready to be sent +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpEndOfWr( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpClear +//* \brief Clear flag in the endpoint CSR register +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpClear( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned int flag) // \arg flag to be cleared +{ + pUDP->UDP_CSR[endpoint] &= ~(flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpSet +//* \brief Set flag in the endpoint CSR register +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpSet( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned int flag) // \arg flag to be cleared +{ + pUDP->UDP_CSR[endpoint] |= flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpStatus +//* \brief Return the endpoint CSR register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_EpStatus( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + return pUDP->UDP_CSR[endpoint]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_GetInterruptMaskStatus +//* \brief Return UDP Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status + AT91PS_UDP pUdp) // \arg pointer to a UDP controller +{ + return pUdp->UDP_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_IsInterruptMasked +//* \brief Test if UDP Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_UDP_IsInterruptMasked( + AT91PS_UDP pUdp, // \arg pointer to a UDP controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR TC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_InterruptEnable +//* \brief Enable TC Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TC_InterruptEnable( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg TC interrupt to be enabled +{ + pTc->TC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_InterruptDisable +//* \brief Disable TC Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TC_InterruptDisable( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg TC interrupt to be disabled +{ + pTc->TC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_GetInterruptMaskStatus +//* \brief Return TC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status + AT91PS_TC pTc) // \arg pointer to a TC controller +{ + return pTc->TC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_IsInterruptMasked +//* \brief Test if TC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_TC_IsInterruptMasked( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR CAN + ***************************************************************************** */ +#define STANDARD_FORMAT 0 +#define EXTENDED_FORMAT 1 + +//*---------------------------------------------------------------------------- +//* \fn AT91F_InitMailboxRegisters() +//* \brief Configure the corresponding mailbox +//*---------------------------------------------------------------------------- +__inline void AT91F_InitMailboxRegisters(AT91PS_CAN_MB CAN_Mailbox, + int mode_reg, + int acceptance_mask_reg, + int id_reg, + int data_low_reg, + int data_high_reg, + int control_reg) +{ + CAN_Mailbox->CAN_MB_MCR = 0x0; + CAN_Mailbox->CAN_MB_MMR = mode_reg; + CAN_Mailbox->CAN_MB_MAM = acceptance_mask_reg; + CAN_Mailbox->CAN_MB_MID = id_reg; + CAN_Mailbox->CAN_MB_MDL = data_low_reg; + CAN_Mailbox->CAN_MB_MDH = data_high_reg; + CAN_Mailbox->CAN_MB_MCR = control_reg; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_EnableCAN() +//* \brief +//*---------------------------------------------------------------------------- +__inline void AT91F_EnableCAN( + AT91PS_CAN pCAN) // pointer to a CAN controller +{ + pCAN->CAN_MR |= AT91C_CAN_CANEN; + + // Wait for WAKEUP flag raising <=> 11-recessive-bit were scanned by the transceiver + while( (pCAN->CAN_SR & AT91C_CAN_WAKEUP) != AT91C_CAN_WAKEUP ); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DisableCAN() +//* \brief +//*---------------------------------------------------------------------------- +__inline void AT91F_DisableCAN( + AT91PS_CAN pCAN) // pointer to a CAN controller +{ + pCAN->CAN_MR &= ~AT91C_CAN_CANEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_EnableIt +//* \brief Enable CAN interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_EnableIt ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pCAN->CAN_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_DisableIt +//* \brief Disable CAN interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_DisableIt ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pCAN->CAN_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetStatus +//* \brief Return CAN Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetStatus( // \return CAN Interrupt Status + AT91PS_CAN pCAN) // pointer to a CAN controller +{ + return pCAN->CAN_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetInterruptMaskStatus +//* \brief Return CAN Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetInterruptMaskStatus( // \return CAN Interrupt Mask Status + AT91PS_CAN pCAN) // pointer to a CAN controller +{ + return pCAN->CAN_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_IsInterruptMasked +//* \brief Test if CAN Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_IsInterruptMasked( + AT91PS_CAN pCAN, // \arg pointer to a CAN controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_CAN_GetInterruptMaskStatus(pCAN) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_IsStatusSet +//* \brief Test if CAN Interrupt is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_IsStatusSet( + AT91PS_CAN pCAN, // \arg pointer to a CAN controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_CAN_GetStatus(pCAN) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgModeReg +//* \brief Configure the Mode Register of the CAN controller +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgModeReg ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int mode) // mode register +{ + //* Write to the MR register + pCAN->CAN_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetModeReg +//* \brief Return the Mode Register of the CAN controller value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetModeReg ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_MR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgBaudrateReg +//* \brief Configure the Baudrate of the CAN controller for the network +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgBaudrateReg ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int baudrate_cfg) +{ + //* Write to the BR register + pCAN->CAN_BR = baudrate_cfg; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetBaudrate +//* \brief Return the Baudrate of the CAN controller for the network value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetBaudrate ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_BR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetInternalCounter +//* \brief Return CAN Timer Regsiter Value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetInternalCounter ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_TIM; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetTimestamp +//* \brief Return CAN Timestamp Register Value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetTimestamp ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_TIMESTP; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetErrorCounter +//* \brief Return CAN Error Counter Register Value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetErrorCounter ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_ECR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_InitTransferRequest +//* \brief Request for a transfer on the corresponding mailboxes +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_InitTransferRequest ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int transfer_cmd) +{ + pCAN->CAN_TCR = transfer_cmd; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_InitAbortRequest +//* \brief Abort the corresponding mailboxes +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_InitAbortRequest ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int abort_cmd) +{ + pCAN->CAN_ACR = abort_cmd; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageModeReg +//* \brief Program the Message Mode Register +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageModeReg ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int mode) +{ + CAN_Mailbox->CAN_MB_MMR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageModeReg +//* \brief Return the Message Mode Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageModeReg ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageIDReg +//* \brief Program the Message ID Register +//* \brief Version == 0 for Standard messsage, Version == 1 for Extended +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageIDReg ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int id, + unsigned char version) +{ + if(version==0) // IDvA Standard Format + CAN_Mailbox->CAN_MB_MID = id<<18; + else // IDvB Extended Format + CAN_Mailbox->CAN_MB_MID = id | (1<<29); // set MIDE bit +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageIDReg +//* \brief Return the Message ID Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageIDReg ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MID; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageAcceptanceMaskReg +//* \brief Program the Message Acceptance Mask Register +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageAcceptanceMaskReg ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int mask) +{ + CAN_Mailbox->CAN_MB_MAM = mask; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageAcceptanceMaskReg +//* \brief Return the Message Acceptance Mask Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageAcceptanceMaskReg ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MAM; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetFamilyID +//* \brief Return the Message ID Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetFamilyID ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MFID; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageCtrl +//* \brief Request and config for a transfer on the corresponding mailbox +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageCtrlReg ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int message_ctrl_cmd) +{ + CAN_Mailbox->CAN_MB_MCR = message_ctrl_cmd; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageStatus +//* \brief Return CAN Mailbox Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageStatus ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageDataLow +//* \brief Program data low value +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageDataLow ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int data) +{ + CAN_Mailbox->CAN_MB_MDL = data; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageDataLow +//* \brief Return data low value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageDataLow ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MDL; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageDataHigh +//* \brief Program data high value +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageDataHigh ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int data) +{ + CAN_Mailbox->CAN_MB_MDH = data; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageDataHigh +//* \brief Return data high value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageDataHigh ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MDH; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_Open +//* \brief Open a CAN Port +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_Open ( + const unsigned int null) // \arg +{ + /* NOT DEFINED AT THIS MOMENT */ + return ( 0 ); +} +/* ***************************************************************************** + SOFTWARE API FOR ADC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_EnableIt +//* \brief Enable ADC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_EnableIt ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pADC->ADC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_DisableIt +//* \brief Disable ADC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_DisableIt ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pADC->ADC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetStatus +//* \brief Return ADC Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status + AT91PS_ADC pADC) // pointer to a ADC controller +{ + return pADC->ADC_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetInterruptMaskStatus +//* \brief Return ADC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status + AT91PS_ADC pADC) // pointer to a ADC controller +{ + return pADC->ADC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_IsInterruptMasked +//* \brief Test if ADC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_IsInterruptMasked( + AT91PS_ADC pADC, // \arg pointer to a ADC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_IsStatusSet +//* \brief Test if ADC Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_IsStatusSet( + AT91PS_ADC pADC, // \arg pointer to a ADC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_ADC_GetStatus(pADC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgModeReg +//* \brief Configure the Mode Register of the ADC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgModeReg ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int mode) // mode register +{ + //* Write to the MR register + pADC->ADC_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetModeReg +//* \brief Return the Mode Register of the ADC controller value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetModeReg ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_MR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgTimings +//* \brief Configure the different necessary timings of the ADC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgTimings ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int mck_clock, // in MHz + unsigned int adc_clock, // in MHz + unsigned int startup_time, // in us + unsigned int sample_and_hold_time) // in ns +{ + unsigned int prescal,startup,shtim; + + prescal = mck_clock/(2*adc_clock) - 1; + startup = adc_clock*startup_time/8 - 1; + shtim = adc_clock*sample_and_hold_time/1000 - 1; + + //* Write to the MR register + pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_EnableChannel +//* \brief Return ADC Timer Register Value +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_EnableChannel ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int channel) // mode register +{ + //* Write to the CHER register + pADC->ADC_CHER = channel; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_DisableChannel +//* \brief Return ADC Timer Register Value +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_DisableChannel ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int channel) // mode register +{ + //* Write to the CHDR register + pADC->ADC_CHDR = channel; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetChannelStatus +//* \brief Return ADC Timer Register Value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetChannelStatus ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CHSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_StartConversion +//* \brief Software request for a analog to digital conversion +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_StartConversion ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + pADC->ADC_CR = AT91C_ADC_START; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_SoftReset +//* \brief Software reset +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_SoftReset ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + pADC->ADC_CR = AT91C_ADC_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetLastConvertedData +//* \brief Return the Last Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetLastConvertedData ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_LCDR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH0 +//* \brief Return the Channel 0 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH0 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR0; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH1 +//* \brief Return the Channel 1 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH1 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR1; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH2 +//* \brief Return the Channel 2 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH2 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR2; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH3 +//* \brief Return the Channel 3 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH3 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR3; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH4 +//* \brief Return the Channel 4 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH4 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR4; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH5 +//* \brief Return the Channel 5 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH5 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR5; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH6 +//* \brief Return the Channel 6 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH6 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR6; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH7 +//* \brief Return the Channel 7 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH7 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR7; +} + +/* ***************************************************************************** + SOFTWARE API FOR AES + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_EnableIt +//* \brief Enable AES interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_EnableIt ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pAES->AES_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_DisableIt +//* \brief Disable AES interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_DisableIt ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pAES->AES_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_GetStatus +//* \brief Return AES Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_GetStatus( // \return AES Interrupt Status + AT91PS_AES pAES) // pointer to a AES controller +{ + return pAES->AES_ISR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_GetInterruptMaskStatus +//* \brief Return AES Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_GetInterruptMaskStatus( // \return AES Interrupt Mask Status + AT91PS_AES pAES) // pointer to a AES controller +{ + return pAES->AES_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_IsInterruptMasked +//* \brief Test if AES Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_IsInterruptMasked( + AT91PS_AES pAES, // \arg pointer to a AES controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_AES_GetInterruptMaskStatus(pAES) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_IsStatusSet +//* \brief Test if AES Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_IsStatusSet( + AT91PS_AES pAES, // \arg pointer to a AES controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_AES_GetStatus(pAES) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_CfgModeReg +//* \brief Configure the Mode Register of the AES controller +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_CfgModeReg ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned int mode) // mode register +{ + //* Write to the MR register + pAES->AES_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_GetModeReg +//* \brief Return the Mode Register of the AES controller value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_GetModeReg ( + AT91PS_AES pAES // pointer to a AES controller + ) +{ + return pAES->AES_MR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_StartProcessing +//* \brief Start Encryption or Decryption +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_StartProcessing ( + AT91PS_AES pAES // pointer to a AES controller + ) +{ + pAES->AES_CR = AT91C_AES_START; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_SoftReset +//* \brief Reset AES +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_SoftReset ( + AT91PS_AES pAES // pointer to a AES controller + ) +{ + pAES->AES_CR = AT91C_AES_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_LoadNewSeed +//* \brief Load New Seed in the random number generator +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_LoadNewSeed ( + AT91PS_AES pAES // pointer to a AES controller + ) +{ + pAES->AES_CR = AT91C_AES_LOADSEED; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_SetCryptoKey +//* \brief Set Cryptographic Key x +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_SetCryptoKey ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned char index, + unsigned int keyword + ) +{ + pAES->AES_KEYWxR[index] = keyword; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_InputData +//* \brief Set Input Data x +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_InputData ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned char index, + unsigned int indata + ) +{ + pAES->AES_IDATAxR[index] = indata; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_GetOutputData +//* \brief Get Output Data x +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_GetOutputData ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned char index + ) +{ + return pAES->AES_ODATAxR[index]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_SetInitializationVector +//* \brief Set Initialization Vector (or Counter) x +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_SetInitializationVector ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned char index, + unsigned int initvector + ) +{ + pAES->AES_IVxR[index] = initvector; +} + +/* ***************************************************************************** + SOFTWARE API FOR TDES + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_EnableIt +//* \brief Enable TDES interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_EnableIt ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pTDES->TDES_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_DisableIt +//* \brief Disable TDES interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_DisableIt ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pTDES->TDES_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_GetStatus +//* \brief Return TDES Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_GetStatus( // \return TDES Interrupt Status + AT91PS_TDES pTDES) // pointer to a TDES controller +{ + return pTDES->TDES_ISR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_GetInterruptMaskStatus +//* \brief Return TDES Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_GetInterruptMaskStatus( // \return TDES Interrupt Mask Status + AT91PS_TDES pTDES) // pointer to a TDES controller +{ + return pTDES->TDES_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_IsInterruptMasked +//* \brief Test if TDES Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_IsInterruptMasked( + AT91PS_TDES pTDES, // \arg pointer to a TDES controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TDES_GetInterruptMaskStatus(pTDES) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_IsStatusSet +//* \brief Test if TDES Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_IsStatusSet( + AT91PS_TDES pTDES, // \arg pointer to a TDES controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TDES_GetStatus(pTDES) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_CfgModeReg +//* \brief Configure the Mode Register of the TDES controller +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_CfgModeReg ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned int mode) // mode register +{ + //* Write to the MR register + pTDES->TDES_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_GetModeReg +//* \brief Return the Mode Register of the TDES controller value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_GetModeReg ( + AT91PS_TDES pTDES // pointer to a TDES controller + ) +{ + return pTDES->TDES_MR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_StartProcessing +//* \brief Start Encryption or Decryption +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_StartProcessing ( + AT91PS_TDES pTDES // pointer to a TDES controller + ) +{ + pTDES->TDES_CR = AT91C_TDES_START; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SoftReset +//* \brief Reset TDES +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SoftReset ( + AT91PS_TDES pTDES // pointer to a TDES controller + ) +{ + pTDES->TDES_CR = AT91C_TDES_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SetCryptoKey1 +//* \brief Set Cryptographic Key 1 Word x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SetCryptoKey1 ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int keyword + ) +{ + pTDES->TDES_KEY1WxR[index] = keyword; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SetCryptoKey2 +//* \brief Set Cryptographic Key 2 Word x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SetCryptoKey2 ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int keyword + ) +{ + pTDES->TDES_KEY2WxR[index] = keyword; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SetCryptoKey3 +//* \brief Set Cryptographic Key 3 Word x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SetCryptoKey3 ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int keyword + ) +{ + pTDES->TDES_KEY3WxR[index] = keyword; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_InputData +//* \brief Set Input Data x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_InputData ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int indata + ) +{ + pTDES->TDES_IDATAxR[index] = indata; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_GetOutputData +//* \brief Get Output Data x +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_GetOutputData ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index + ) +{ + return pTDES->TDES_ODATAxR[index]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SetInitializationVector +//* \brief Set Initialization Vector x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SetInitializationVector ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int initvector + ) +{ + pTDES->TDES_IVxR[index] = initvector; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_CfgPMC +//* \brief Enable Peripheral clock in PMC for DBGU +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_CfgPIO +//* \brief Configure PIO controllers to drive DBGU signals +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA27_DRXD ) | + ((unsigned int) AT91C_PA28_DTXD ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgPMC +//* \brief Enable Peripheral clock in PMC for PMC +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgPIO +//* \brief Configure PIO controllers to drive PMC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB30_PCK2 ) | + ((unsigned int) AT91C_PB29_PCK1 ), // Peripheral A + ((unsigned int) AT91C_PB20_PCK0 ) | + ((unsigned int) AT91C_PB0_PCK0 ) | + ((unsigned int) AT91C_PB22_PCK2 ) | + ((unsigned int) AT91C_PB21_PCK1 )); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA30_PCK2 ) | + ((unsigned int) AT91C_PA13_PCK1 ) | + ((unsigned int) AT91C_PA27_PCK3 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_VREG_CfgPMC +//* \brief Enable Peripheral clock in PMC for VREG +//*---------------------------------------------------------------------------- +__inline void AT91F_VREG_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTC_CfgPMC +//* \brief Enable Peripheral clock in PMC for RSTC +//*---------------------------------------------------------------------------- +__inline void AT91F_RSTC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_CfgPMC +//* \brief Enable Peripheral clock in PMC for SSC +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SSC)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_CfgPIO +//* \brief Configure PIO controllers to drive SSC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA25_RK ) | + ((unsigned int) AT91C_PA22_TK ) | + ((unsigned int) AT91C_PA21_TF ) | + ((unsigned int) AT91C_PA24_RD ) | + ((unsigned int) AT91C_PA26_RF ) | + ((unsigned int) AT91C_PA23_TD ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTC_CfgPMC +//* \brief Enable Peripheral clock in PMC for WDTC +//*---------------------------------------------------------------------------- +__inline void AT91F_WDTC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US1_CfgPMC +//* \brief Enable Peripheral clock in PMC for US1 +//*---------------------------------------------------------------------------- +__inline void AT91F_US1_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_US1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US1_CfgPIO +//* \brief Configure PIO controllers to drive US1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_US1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PB26_RI1 ) | + ((unsigned int) AT91C_PB24_DSR1 ) | + ((unsigned int) AT91C_PB23_DCD1 ) | + ((unsigned int) AT91C_PB25_DTR1 )); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA7_SCK1 ) | + ((unsigned int) AT91C_PA8_RTS1 ) | + ((unsigned int) AT91C_PA6_TXD1 ) | + ((unsigned int) AT91C_PA5_RXD1 ) | + ((unsigned int) AT91C_PA9_CTS1 ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US0_CfgPMC +//* \brief Enable Peripheral clock in PMC for US0 +//*---------------------------------------------------------------------------- +__inline void AT91F_US0_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_US0)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US0_CfgPIO +//* \brief Configure PIO controllers to drive US0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_US0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA0_RXD0 ) | + ((unsigned int) AT91C_PA4_CTS0 ) | + ((unsigned int) AT91C_PA3_RTS0 ) | + ((unsigned int) AT91C_PA2_SCK0 ) | + ((unsigned int) AT91C_PA1_TXD0 ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI1_CfgPMC +//* \brief Enable Peripheral clock in PMC for SPI1 +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI1_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SPI1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI1_CfgPIO +//* \brief Configure PIO controllers to drive SPI1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PB16_NPCS13 ) | + ((unsigned int) AT91C_PB10_NPCS11 ) | + ((unsigned int) AT91C_PB11_NPCS12 )); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA4_NPCS13 ) | + ((unsigned int) AT91C_PA29_NPCS13 ) | + ((unsigned int) AT91C_PA21_NPCS10 ) | + ((unsigned int) AT91C_PA22_SPCK1 ) | + ((unsigned int) AT91C_PA25_NPCS11 ) | + ((unsigned int) AT91C_PA2_NPCS11 ) | + ((unsigned int) AT91C_PA24_MISO1 ) | + ((unsigned int) AT91C_PA3_NPCS12 ) | + ((unsigned int) AT91C_PA26_NPCS12 ) | + ((unsigned int) AT91C_PA23_MOSI1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI0_CfgPMC +//* \brief Enable Peripheral clock in PMC for SPI0 +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI0_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SPI0)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI0_CfgPIO +//* \brief Configure PIO controllers to drive SPI0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PB13_NPCS01 ) | + ((unsigned int) AT91C_PB17_NPCS03 ) | + ((unsigned int) AT91C_PB14_NPCS02 )); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA16_MISO0 ) | + ((unsigned int) AT91C_PA13_NPCS01 ) | + ((unsigned int) AT91C_PA15_NPCS03 ) | + ((unsigned int) AT91C_PA17_MOSI0 ) | + ((unsigned int) AT91C_PA18_SPCK0 ) | + ((unsigned int) AT91C_PA14_NPCS02 ) | + ((unsigned int) AT91C_PA12_NPCS00 ), // Peripheral A + ((unsigned int) AT91C_PA7_NPCS01 ) | + ((unsigned int) AT91C_PA9_NPCS03 ) | + ((unsigned int) AT91C_PA8_NPCS02 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITC_CfgPMC +//* \brief Enable Peripheral clock in PMC for PITC +//*---------------------------------------------------------------------------- +__inline void AT91F_PITC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_CfgPMC +//* \brief Enable Peripheral clock in PMC for AIC +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_FIQ) | + ((unsigned int) 1 << AT91C_ID_IRQ0) | + ((unsigned int) 1 << AT91C_ID_IRQ1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_CfgPIO +//* \brief Configure PIO controllers to drive AIC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA30_IRQ0 ) | + ((unsigned int) AT91C_PA29_FIQ ), // Peripheral A + ((unsigned int) AT91C_PA14_IRQ1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_CfgPMC +//* \brief Enable Peripheral clock in PMC for AES +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_AES)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_CfgPMC +//* \brief Enable Peripheral clock in PMC for TWI +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TWI)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_CfgPIO +//* \brief Configure PIO controllers to drive TWI signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA11_TWCK ) | + ((unsigned int) AT91C_PA10_TWD ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgPMC +//* \brief Enable Peripheral clock in PMC for ADC +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_ADC)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgPIO +//* \brief Configure PIO controllers to drive ADC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PB18_ADTRG )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH3_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH3 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH3_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB22_PWM3 ), // Peripheral A + ((unsigned int) AT91C_PB30_PWM3 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH2_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH2 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH2_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB21_PWM2 ), // Peripheral A + ((unsigned int) AT91C_PB29_PWM2 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH1_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB20_PWM1 ), // Peripheral A + ((unsigned int) AT91C_PB28_PWM1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH0_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB19_PWM0 ), // Peripheral A + ((unsigned int) AT91C_PB27_PWM0 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RTTC_CfgPMC +//* \brief Enable Peripheral clock in PMC for RTTC +//*---------------------------------------------------------------------------- +__inline void AT91F_RTTC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_CfgPMC +//* \brief Enable Peripheral clock in PMC for UDP +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_UDP)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_CfgPMC +//* \brief Enable Peripheral clock in PMC for TDES +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TDES)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_EMAC_CfgPMC +//* \brief Enable Peripheral clock in PMC for EMAC +//*---------------------------------------------------------------------------- +__inline void AT91F_EMAC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_EMAC)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_EMAC_CfgPIO +//* \brief Configure PIO controllers to drive EMAC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_EMAC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB2_ETX0 ) | + ((unsigned int) AT91C_PB12_ETXER ) | + ((unsigned int) AT91C_PB16_ECOL ) | + ((unsigned int) AT91C_PB11_ETX3 ) | + ((unsigned int) AT91C_PB6_ERX1 ) | + ((unsigned int) AT91C_PB15_ERXDV ) | + ((unsigned int) AT91C_PB13_ERX2 ) | + ((unsigned int) AT91C_PB3_ETX1 ) | + ((unsigned int) AT91C_PB8_EMDC ) | + ((unsigned int) AT91C_PB5_ERX0 ) | + //((unsigned int) AT91C_PB18_EF100 ) | + ((unsigned int) AT91C_PB14_ERX3 ) | + ((unsigned int) AT91C_PB4_ECRS_ECRSDV) | + ((unsigned int) AT91C_PB1_ETXEN ) | + ((unsigned int) AT91C_PB10_ETX2 ) | + ((unsigned int) AT91C_PB0_ETXCK_EREFCK) | + ((unsigned int) AT91C_PB9_EMDIO ) | + ((unsigned int) AT91C_PB7_ERXER ) | + ((unsigned int) AT91C_PB17_ERXCK ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC0_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC0 +//*---------------------------------------------------------------------------- +__inline void AT91F_TC0_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC0)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC0_CfgPIO +//* \brief Configure PIO controllers to drive TC0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TC0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB23_TIOA0 ) | + ((unsigned int) AT91C_PB24_TIOB0 ), // Peripheral A + ((unsigned int) AT91C_PB12_TCLK0 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC1_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC1 +//*---------------------------------------------------------------------------- +__inline void AT91F_TC1_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC1_CfgPIO +//* \brief Configure PIO controllers to drive TC1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TC1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB25_TIOA1 ) | + ((unsigned int) AT91C_PB26_TIOB1 ), // Peripheral A + ((unsigned int) AT91C_PB19_TCLK1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC2_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC2 +//*---------------------------------------------------------------------------- +__inline void AT91F_TC2_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC2)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC2_CfgPIO +//* \brief Configure PIO controllers to drive TC2 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TC2_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB28_TIOB2 ) | + ((unsigned int) AT91C_PB27_TIOA2 ), // Peripheral A + 0); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA15_TCLK2 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_CfgPMC +//* \brief Enable Peripheral clock in PMC for MC +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIOA_CfgPMC +//* \brief Enable Peripheral clock in PMC for PIOA +//*---------------------------------------------------------------------------- +__inline void AT91F_PIOA_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_PIOA)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIOB_CfgPMC +//* \brief Enable Peripheral clock in PMC for PIOB +//*---------------------------------------------------------------------------- +__inline void AT91F_PIOB_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_PIOB)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgPMC +//* \brief Enable Peripheral clock in PMC for CAN +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_CAN)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgPIO +//* \brief Configure PIO controllers to drive CAN signals +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA20_CANTX ) | + ((unsigned int) AT91C_PA19_CANRX ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CfgPMC +//* \brief Enable Peripheral clock in PMC for PWMC +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_PWMC)); +} + +#endif // lib_AT91SAM7X256_H diff --git a/20080212/Source/portable/IAR/AtmelSAM7S64/port.c b/20080212/Source/portable/IAR/AtmelSAM7S64/port.c new file mode 100644 index 000000000..6bcb9eacc --- /dev/null +++ b/20080212/Source/portable/IAR/AtmelSAM7S64/port.c @@ -0,0 +1,262 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the Atmel ARM7 port. + *----------------------------------------------------------*/ + + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to setup the initial stack. */ +#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */ +#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 ) + +/* Constants required to setup the PIT. */ +#define portPIT_CLOCK_DIVISOR ( ( unsigned portLONG ) 16 ) +#define portPIT_COUNTER_VALUE ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_RATE_MS ) + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 ) + + +#define portINT_LEVEL_SENSITIVE 0 +#define portPIT_ENABLE ( ( unsigned portSHORT ) 0x1 << 24 ) +#define portPIT_INT_ENABLE ( ( unsigned portSHORT ) 0x1 << 25 ) +/*-----------------------------------------------------------*/ + +/* Setup the PIT to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/* ulCriticalNesting will get set to zero when the first task starts. It +cannot be initialised to 0 as this will cause interrupts to be enabled +during the kernel initialisation process. */ +unsigned portLONG ulCriticalNesting = ( unsigned portLONG ) 9999; + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ +portSTACK_TYPE *pxOriginalTOS; + + pxOriginalTOS = pxTopOfStack; + + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. */ + + /* First on the stack is the return address - which in this case is the + start of the task. The offset is added to make the return address appear + as it would within an IRQ ISR. */ + *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */ + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + R0. */ + *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The status register is set for system mode, with interrupts enabled. */ + *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR; + pxTopOfStack--; + + /* Interrupt flags cannot always be stored on the stack and will + instead be stored in a variable, which is then saved as part of the + tasks context. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xPortStartScheduler( void ) +{ +extern void vPortStartFirstTask( void ); + + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ARM port will require this function as there + is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +#if configUSE_PREEMPTION == 0 + + /* The cooperative scheduler requires a normal IRQ service routine to + simply increment the system tick. */ + static __arm __irq void vPortNonPreemptiveTick( void ); + static __arm __irq void vPortNonPreemptiveTick( void ) + { + unsigned portLONG ulDummy; + + /* Increment the tick count - which may wake some tasks but as the + preemptive scheduler is not being used any woken task is not given + processor time no matter what its priority. */ + vTaskIncrementTick(); + + /* Clear the PIT interrupt. */ + ulDummy = AT91C_BASE_PITC->PITC_PIVR; + + /* End the interrupt in the AIC. */ + AT91C_BASE_AIC->AIC_EOICR = ulDummy; + } + +#else + + /* Currently the IAR port requires the preemptive tick function to be + defined in an asm file. */ + +#endif + +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ +AT91PS_PITC pxPIT = AT91C_BASE_PITC; + + /* Setup the AIC for PIT interrupts. The interrupt routine chosen depends + on whether the preemptive or cooperative scheduler is being used. */ + #if configUSE_PREEMPTION == 0 + + AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vPortNonPreemptiveTick ); + + #else + + extern void ( vPortPreemptiveTick )( void ); + AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vPortPreemptiveTick ); + + #endif + + /* Configure the PIT period. */ + pxPIT->PITC_PIMR = portPIT_ENABLE | portPIT_INT_ENABLE | portPIT_COUNTER_VALUE; + + /* Enable the interrupt. Global interrupts are disables at this point so + this is safe. */ + AT91F_AIC_EnableIt( AT91C_BASE_AIC, AT91C_ID_SYS ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + /* Disable interrupts first! */ + __disable_interrupt(); + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + __enable_interrupt(); + } + } +} +/*-----------------------------------------------------------*/ + + + + + + diff --git a/20080212/Source/portable/IAR/AtmelSAM7S64/portasm.s79 b/20080212/Source/portable/IAR/AtmelSAM7S64/portasm.s79 new file mode 100644 index 000000000..691b95be4 --- /dev/null +++ b/20080212/Source/portable/IAR/AtmelSAM7S64/portasm.s79 @@ -0,0 +1,59 @@ + RSEG ICODE:CODE + CODE32 + + EXTERN vTaskSwitchContext + EXTERN vTaskIncrementTick + + PUBLIC vPortYieldProcessor + PUBLIC vPortPreemptiveTick + PUBLIC vPortStartFirstTask + +#include "AT91SAM7S64_inc.h" +#include "ISR_Support.h" + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Starting the first task is just a matter of restoring the context that +; was created by pxPortInitialiseStack(). +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortStartFirstTask: + portRESTORE_CONTEXT + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Manual context switch function. This is the SWI hander. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortYieldProcessor: + ADD LR, LR, #4 ; Add 4 to the LR to make the LR appear exactly + ; as if the context was saved during and IRQ + ; handler. + + portSAVE_CONTEXT ; Save the context of the current task... + LDR R0, =vTaskSwitchContext ; before selecting the next task to execute. + mov lr, pc + BX R0 + portRESTORE_CONTEXT ; Restore the context of the selected task. + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Preemptive context switch function. This will only ever get installed if +; portUSE_PREEMPTION is set to 1 in portmacro.h. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortPreemptiveTick: + portSAVE_CONTEXT ; Save the context of the current task. + + LDR R0, =vTaskIncrementTick ; Increment the tick count - this may wake a task. + mov lr, pc + BX R0 + LDR R0, =vTaskSwitchContext ; Select the next task to execute. + mov lr, pc + BX R0 + + LDR R14, =AT91C_BASE_PITC ; Clear the PIT interrupt + LDR R0, [R14, #PITC_PIVR ] + + LDR R14, =AT91C_BASE_AIC ; Mark the End of Interrupt on the AIC + STR R14, [R14, #AIC_EOICR] + + portRESTORE_CONTEXT ; Restore the context of the selected task. + + + END + diff --git a/20080212/Source/portable/IAR/AtmelSAM7S64/portmacro.h b/20080212/Source/portable/IAR/AtmelSAM7S64/portmacro.h new file mode 100644 index 000000000..f174fa59d --- /dev/null +++ b/20080212/Source/portable/IAR/AtmelSAM7S64/portmacro.h @@ -0,0 +1,125 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned portLONG +#define portBASE_TYPE portLONG + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 4 +#define portYIELD() asm ( "SWI 0" ) +#define portNOP() asm ( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +__arm __interwork void vPortDisableInterruptsFromThumb( void ); +__arm __interwork void vPortEnableInterruptsFromThumb( void ); +__arm __interwork void vPortEnterCritical( void ); +__arm __interwork void vPortExitCritical( void ); + +#define portDISABLE_INTERRUPTS() __disable_interrupt() +#define portENABLE_INTERRUPTS() __enable_interrupt() +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ +{ \ +extern void vTaskSwitchContext( void ); \ + \ + if( xSwitchRequired ) \ + { \ + vTaskSwitchContext(); \ + } \ +} +/*-----------------------------------------------------------*/ + +/* Compiler specifics. */ +#define inline +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + + diff --git a/20080212/Source/portable/IAR/LPC2000/ISR_Support.h b/20080212/Source/portable/IAR/LPC2000/ISR_Support.h new file mode 100644 index 000000000..4a32f3976 --- /dev/null +++ b/20080212/Source/portable/IAR/LPC2000/ISR_Support.h @@ -0,0 +1,78 @@ + EXTERN pxCurrentTCB + EXTERN ulCriticalNesting + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Context save and restore macro definitions +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +portSAVE_CONTEXT MACRO + + ; Push R0 as we are going to use the register. + STMDB SP!, {R0} + + ; Set R0 to point to the task stack pointer. + STMDB SP, {SP}^ + NOP + SUB SP, SP, #4 + LDMIA SP!, {R0} + + ; Push the return address onto the stack. + STMDB R0!, {LR} + + ; Now we have saved LR we can use it instead of R0. + MOV LR, R0 + + ; Pop R0 so we can save it onto the system mode stack. + LDMIA SP!, {R0} + + ; Push all the system mode registers onto the task stack. + STMDB LR, {R0-LR}^ + NOP + SUB LR, LR, #60 + + ; Push the SPSR onto the task stack. + MRS R0, SPSR + STMDB LR!, {R0} + + LDR R0, =ulCriticalNesting + LDR R0, [R0] + STMDB LR!, {R0} + + ; Store the new top of stack for the task. + LDR R1, =pxCurrentTCB + LDR R0, [R1] + STR LR, [R0] + + ENDM + + +portRESTORE_CONTEXT MACRO + + ; Set the LR to the task stack. + LDR R1, =pxCurrentTCB + LDR R0, [R1] + LDR LR, [R0] + + ; The critical nesting depth is the first item on the stack. + ; Load it into the ulCriticalNesting variable. + LDR R0, =ulCriticalNesting + LDMFD LR!, {R1} + STR R1, [R0] + + ; Get the SPSR from the stack. + LDMFD LR!, {R0} + MSR SPSR_cxsf, R0 + + ; Restore all system mode registers for the task. + LDMFD LR, {R0-R14}^ + NOP + + ; Restore the return address. + LDR LR, [LR, #+60] + + ; And return - correcting the offset in the LR to obtain the + ; correct address. + SUBS PC, LR, #4 + + ENDM + diff --git a/20080212/Source/portable/IAR/LPC2000/port.c b/20080212/Source/portable/IAR/LPC2000/port.c new file mode 100644 index 000000000..0a43fdeeb --- /dev/null +++ b/20080212/Source/portable/IAR/LPC2000/port.c @@ -0,0 +1,323 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the Philips ARM7 port. + *----------------------------------------------------------*/ + +/* + Changes from V3.2.2 + + + Bug fix - The prescale value for the timer setup is now written to T0PR + instead of T0PC. This bug would have had no effect unless a prescale + value was actually used. +*/ + +/* Standard includes. */ +#include +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to setup the tick ISR. */ +#define portENABLE_TIMER ( ( unsigned portCHAR ) 0x01 ) +#define portPRESCALE_VALUE 0x00 +#define portINTERRUPT_ON_MATCH ( ( unsigned portLONG ) 0x01 ) +#define portRESET_COUNT_ON_MATCH ( ( unsigned portLONG ) 0x02 ) + +/* Constants required to setup the initial stack. */ +#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */ +#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 ) + +/* Constants required to setup the PIT. */ +#define portPIT_CLOCK_DIVISOR ( ( unsigned portLONG ) 16 ) +#define portPIT_COUNTER_VALUE ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_RATE_MS ) + +/* Constants required to handle interrupts. */ +#define portTIMER_MATCH_ISR_BIT ( ( unsigned portCHAR ) 0x01 ) +#define portCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 ) + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 ) + + +#define portINT_LEVEL_SENSITIVE 0 +#define portPIT_ENABLE ( ( unsigned portSHORT ) 0x1 << 24 ) +#define portPIT_INT_ENABLE ( ( unsigned portSHORT ) 0x1 << 25 ) + +/* Constants required to setup the VIC for the tick ISR. */ +#define portTIMER_VIC_CHANNEL ( ( unsigned portLONG ) 0x0004 ) +#define portTIMER_VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x0010 ) +#define portTIMER_VIC_ENABLE ( ( unsigned portLONG ) 0x0020 ) + +/*-----------------------------------------------------------*/ + +/* Setup the PIT to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/* ulCriticalNesting will get set to zero when the first task starts. It +cannot be initialised to 0 as this will cause interrupts to be enabled +during the kernel initialisation process. */ +unsigned portLONG ulCriticalNesting = ( unsigned portLONG ) 9999; + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ +portSTACK_TYPE *pxOriginalTOS; + + pxOriginalTOS = pxTopOfStack; + + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. */ + + /* First on the stack is the return address - which in this case is the + start of the task. The offset is added to make the return address appear + as it would within an IRQ ISR. */ + *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */ + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + R0. */ + *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The status register is set for system mode, with interrupts enabled. */ + *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR; + pxTopOfStack--; + + /* Interrupt flags cannot always be stored on the stack and will + instead be stored in a variable, which is then saved as part of the + tasks context. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xPortStartScheduler( void ) +{ +extern void vPortStartFirstTask( void ); + + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ARM port will require this function as there + is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +#if configUSE_PREEMPTION == 0 + + /* The cooperative scheduler requires a normal IRQ service routine to + simply increment the system tick. */ + static __arm __irq void vPortNonPreemptiveTick( void ); + static __arm __irq void vPortNonPreemptiveTick( void ) + { + /* Increment the tick count - which may wake some tasks but as the + preemptive scheduler is not being used any woken task is not given + processor time no matter what its priority. */ + vTaskIncrementTick(); + + /* Ready for the next interrupt. */ + T0IR = portTIMER_MATCH_ISR_BIT; + VICVectAddr = portCLEAR_VIC_INTERRUPT; + } + +#else + + /* This function is called from an asm wrapper, so does not require the __irq + keyword. */ + void vPortPreemptiveTick( void ); + void vPortPreemptiveTick( void ) + { + /* Increment the tick counter. */ + vTaskIncrementTick(); + + /* The new tick value might unblock a task. Ensure the highest task that + is ready to execute is the task that will execute when the tick ISR + exits. */ + vTaskSwitchContext(); + + /* Ready for the next interrupt. */ + T0IR = portTIMER_MATCH_ISR_BIT; + VICVectAddr = portCLEAR_VIC_INTERRUPT; + } + +#endif + +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ +unsigned portLONG ulCompareMatch; + + /* A 1ms tick does not require the use of the timer prescale. This is + defaulted to zero but can be used if necessary. */ + T0PR = portPRESCALE_VALUE; + + /* Calculate the match value required for our wanted tick rate. */ + ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ; + + /* Protect against divide by zero. Using an if() statement still results + in a warning - hence the #if. */ + #if portPRESCALE_VALUE != 0 + { + ulCompareMatch /= ( portPRESCALE_VALUE + 1 ); + } + #endif + + T0MR0 = ulCompareMatch; + + /* Generate tick with timer 0 compare match. */ + T0MCR = portRESET_COUNT_ON_MATCH | portINTERRUPT_ON_MATCH; + + /* Setup the VIC for the timer. */ + VICIntSelect &= ~( portTIMER_VIC_CHANNEL_BIT ); + VICIntEnable |= portTIMER_VIC_CHANNEL_BIT; + + /* The ISR installed depends on whether the preemptive or cooperative + scheduler is being used. */ + #if configUSE_PREEMPTION == 1 + { + extern void ( vPortPreemptiveTickEntry )( void ); + + VICVectAddr0 = ( unsigned portLONG ) vPortPreemptiveTickEntry; + } + #else + { + extern void ( vNonPreemptiveTick )( void ); + + VICVectAddr0 = ( portLONG ) vPortNonPreemptiveTick; + } + #endif + + VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE; + + /* Start the timer - interrupts are disabled when this function is called + so it is okay to do this here. */ + T0TCR = portENABLE_TIMER; +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + /* Disable interrupts first! */ + __disable_interrupt(); + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + __enable_interrupt(); + } + } +} +/*-----------------------------------------------------------*/ + + + + + + diff --git a/20080212/Source/portable/IAR/LPC2000/portasm.s79 b/20080212/Source/portable/IAR/LPC2000/portasm.s79 new file mode 100644 index 000000000..d679660f2 --- /dev/null +++ b/20080212/Source/portable/IAR/LPC2000/portasm.s79 @@ -0,0 +1,50 @@ + RSEG ICODE:CODE + CODE32 + + EXTERN vTaskSwitchContext + EXTERN vTaskIncrementTick + EXTERN vPortPreemptiveTick + + PUBLIC vPortPreemptiveTickEntry + PUBLIC vPortYieldProcessor + PUBLIC vPortStartFirstTask + +#include "FreeRTOSConfig.h" +#include "ISR_Support.h" + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Starting the first task is just a matter of restoring the context that +; was created by pxPortInitialiseStack(). +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortStartFirstTask: + portRESTORE_CONTEXT + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Manual context switch function. This is the SWI hander. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortYieldProcessor: + ADD LR, LR, #4 ; Add 4 to the LR to make the LR appear exactly + ; as if the context was saved during and IRQ + ; handler. + + portSAVE_CONTEXT ; Save the context of the current task... + LDR R0, =vTaskSwitchContext ; before selecting the next task to execute. + mov lr, pc + BX R0 + portRESTORE_CONTEXT ; Restore the context of the selected task. + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Preemptive context switch function. This will only ever get installed if +; portUSE_PREEMPTION is set to 1 in portmacro.h. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortPreemptiveTickEntry: +#if configUSE_PREEMPTION == 1 + portSAVE_CONTEXT ; Save the context of the current task... + LDR R0, =vPortPreemptiveTick; before selecting the next task to execute. + mov lr, pc + BX R0 + portRESTORE_CONTEXT ; Restore the context of the selected task. +#endif + + END + diff --git a/20080212/Source/portable/IAR/LPC2000/portmacro.h b/20080212/Source/portable/IAR/LPC2000/portmacro.h new file mode 100644 index 000000000..7f19513b2 --- /dev/null +++ b/20080212/Source/portable/IAR/LPC2000/portmacro.h @@ -0,0 +1,127 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned portLONG +#define portBASE_TYPE portLONG + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 4 +#define portYIELD() asm ( "SWI 0" ) +#define portNOP() asm ( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +__arm __interwork void vPortDisableInterruptsFromThumb( void ); +__arm __interwork void vPortEnableInterruptsFromThumb( void ); +__arm __interwork void vPortEnterCritical( void ); +__arm __interwork void vPortExitCritical( void ); + +#define portDISABLE_INTERRUPTS() __disable_interrupt() +#define portENABLE_INTERRUPTS() __enable_interrupt() +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ +{ \ +extern void vTaskSwitchContext( void ); \ + \ + if( xSwitchRequired ) \ + { \ + vTaskSwitchContext(); \ + } \ +} +/*-----------------------------------------------------------*/ + +/* Compiler specifics. */ +#define inline +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + + diff --git a/20080212/Source/portable/IAR/STR71x/ISR_Support.h b/20080212/Source/portable/IAR/STR71x/ISR_Support.h new file mode 100644 index 000000000..4a32f3976 --- /dev/null +++ b/20080212/Source/portable/IAR/STR71x/ISR_Support.h @@ -0,0 +1,78 @@ + EXTERN pxCurrentTCB + EXTERN ulCriticalNesting + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Context save and restore macro definitions +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +portSAVE_CONTEXT MACRO + + ; Push R0 as we are going to use the register. + STMDB SP!, {R0} + + ; Set R0 to point to the task stack pointer. + STMDB SP, {SP}^ + NOP + SUB SP, SP, #4 + LDMIA SP!, {R0} + + ; Push the return address onto the stack. + STMDB R0!, {LR} + + ; Now we have saved LR we can use it instead of R0. + MOV LR, R0 + + ; Pop R0 so we can save it onto the system mode stack. + LDMIA SP!, {R0} + + ; Push all the system mode registers onto the task stack. + STMDB LR, {R0-LR}^ + NOP + SUB LR, LR, #60 + + ; Push the SPSR onto the task stack. + MRS R0, SPSR + STMDB LR!, {R0} + + LDR R0, =ulCriticalNesting + LDR R0, [R0] + STMDB LR!, {R0} + + ; Store the new top of stack for the task. + LDR R1, =pxCurrentTCB + LDR R0, [R1] + STR LR, [R0] + + ENDM + + +portRESTORE_CONTEXT MACRO + + ; Set the LR to the task stack. + LDR R1, =pxCurrentTCB + LDR R0, [R1] + LDR LR, [R0] + + ; The critical nesting depth is the first item on the stack. + ; Load it into the ulCriticalNesting variable. + LDR R0, =ulCriticalNesting + LDMFD LR!, {R1} + STR R1, [R0] + + ; Get the SPSR from the stack. + LDMFD LR!, {R0} + MSR SPSR_cxsf, R0 + + ; Restore all system mode registers for the task. + LDMFD LR, {R0-R14}^ + NOP + + ; Restore the return address. + LDR LR, [LR, #+60] + + ; And return - correcting the offset in the LR to obtain the + ; correct address. + SUBS PC, LR, #4 + + ENDM + diff --git a/20080212/Source/portable/IAR/STR71x/port.c b/20080212/Source/portable/IAR/STR71x/port.c new file mode 100644 index 000000000..67014e49f --- /dev/null +++ b/20080212/Source/portable/IAR/STR71x/port.c @@ -0,0 +1,262 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the ST STR71x ARM7 + * port. + *----------------------------------------------------------*/ + +/* Library includes. */ +#include "wdg.h" +#include "eic.h" + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to setup the initial stack. */ +#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */ +#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 ) + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 ) + +#define portMICROS_PER_SECOND 1000000 + +/*-----------------------------------------------------------*/ + +/* Setup the watchdog to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/* ulCriticalNesting will get set to zero when the first task starts. It +cannot be initialised to 0 as this will cause interrupts to be enabled +during the kernel initialisation process. */ +unsigned portLONG ulCriticalNesting = ( unsigned portLONG ) 9999; + +/* Tick interrupt routines for cooperative and preemptive operation +respectively. The preemptive version is not defined as __irq as it is called +from an asm wrapper function. */ +__arm __irq void vPortNonPreemptiveTick( void ); +void vPortPreemptiveTick( void ); + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ +portSTACK_TYPE *pxOriginalTOS; + + pxOriginalTOS = pxTopOfStack; + + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. */ + + /* First on the stack is the return address - which in this case is the + start of the task. The offset is added to make the return address appear + as it would within an IRQ ISR. */ + *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */ + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + R0. */ + *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The status register is set for system mode, with interrupts enabled. */ + *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR; + pxTopOfStack--; + + /* Interrupt flags cannot always be stored on the stack and will + instead be stored in a variable, which is then saved as part of the + tasks context. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xPortStartScheduler( void ) +{ +extern void vPortStartFirstTask( void ); + + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ARM port will require this function as there + is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +/* The cooperative scheduler requires a normal IRQ service routine to +simply increment the system tick. */ +__arm __irq void vPortNonPreemptiveTick( void ) +{ + /* Increment the tick count - which may wake some tasks but as the + preemptive scheduler is not being used any woken task is not given + processor time no matter what its priority. */ + vTaskIncrementTick(); + + /* Clear the interrupt in the watchdog and EIC. */ + WDG->SR = 0x0000; + portCLEAR_EIC(); +} +/*-----------------------------------------------------------*/ + +/* This function is called from an asm wrapper, so does not require the __irq +keyword. */ +void vPortPreemptiveTick( void ) +{ + /* Increment the tick counter. */ + vTaskIncrementTick(); + + /* The new tick value might unblock a task. Ensure the highest task that + is ready to execute is the task that will execute when the tick ISR + exits. */ + vTaskSwitchContext(); + + /* Clear the interrupt in the watchdog and EIC. */ + WDG->SR = 0x0000; + portCLEAR_EIC(); +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ + /* Set the watchdog up to generate a periodic tick. */ + WDG_ECITConfig( DISABLE ); + WDG_CntOnOffConfig( DISABLE ); + WDG_PeriodValueConfig( portMICROS_PER_SECOND / configTICK_RATE_HZ ); + + /* Setup the tick interrupt in the EIC. */ + EIC_IRQChannelPriorityConfig( WDG_IRQChannel, 1 ); + EIC_IRQChannelConfig( WDG_IRQChannel, ENABLE ); + EIC_IRQConfig( ENABLE ); + WDG_ECITConfig( ENABLE ); + + /* Start the timer - interrupts are actually disabled at this point so + it is safe to do this here. */ + WDG_CntOnOffConfig( ENABLE ); +} +/*-----------------------------------------------------------*/ + +__arm __interwork void vPortEnterCritical( void ) +{ + /* Disable interrupts first! */ + __disable_interrupt(); + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +__arm __interwork void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + __enable_interrupt(); + } + } +} +/*-----------------------------------------------------------*/ + + + + + + diff --git a/20080212/Source/portable/IAR/STR71x/portasm.s79 b/20080212/Source/portable/IAR/STR71x/portasm.s79 new file mode 100644 index 000000000..d9f0fc347 --- /dev/null +++ b/20080212/Source/portable/IAR/STR71x/portasm.s79 @@ -0,0 +1,49 @@ + RSEG ICODE:CODE + CODE32 + + EXTERN vPortPreemptiveTick + EXTERN vTaskSwitchContext + + PUBLIC vPortYieldProcessor + PUBLIC vPortStartFirstTask + PUBLIC vPortPreemptiveTickISR + +#include "ISR_Support.h" + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Starting the first task is just a matter of restoring the context that +; was created by pxPortInitialiseStack(). +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortStartFirstTask: + portRESTORE_CONTEXT + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Manual context switch function. This is the SWI hander. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortYieldProcessor: + ADD LR, LR, #4 ; Add 4 to the LR to make the LR appear exactly + ; as if the context was saved during and IRQ + ; handler. + + portSAVE_CONTEXT ; Save the context of the current task... + LDR R0, =vTaskSwitchContext ; before selecting the next task to execute. + mov lr, pc + BX R0 + portRESTORE_CONTEXT ; Restore the context of the selected task. + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Preemptive context switch function. This will only ever get used if +; portUSE_PREEMPTION is set to 1 in portmacro.h. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortPreemptiveTickISR: + portSAVE_CONTEXT ; Save the context of the current task. + + LDR R0, =vPortPreemptiveTick ; Increment the tick count - this may wake a task. + MOV lr, pc + BX R0 + + portRESTORE_CONTEXT ; Restore the context of the selected task. + + + END + diff --git a/20080212/Source/portable/IAR/STR71x/portmacro.h b/20080212/Source/portable/IAR/STR71x/portmacro.h new file mode 100644 index 000000000..ba6666fbf --- /dev/null +++ b/20080212/Source/portable/IAR/STR71x/portmacro.h @@ -0,0 +1,134 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned portLONG +#define portBASE_TYPE portLONG + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 4 +#define portYIELD() asm ( "SWI 0" ) +#define portNOP() asm ( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +__arm __interwork void vPortDisableInterruptsFromThumb( void ); +__arm __interwork void vPortEnableInterruptsFromThumb( void ); +__arm __interwork void vPortEnterCritical( void ); +__arm __interwork void vPortExitCritical( void ); + +#define portDISABLE_INTERRUPTS() __disable_interrupt() +#define portENABLE_INTERRUPTS() __enable_interrupt() +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ +{ \ +extern void vTaskSwitchContext( void ); \ + \ + if( xSwitchRequired ) \ + { \ + vTaskSwitchContext(); \ + } \ +} +/*-----------------------------------------------------------*/ + +/* EIC utilities. */ +#define portEIC_CICR_ADDR *( ( unsigned portLONG * ) 0xFFFFF804 ) +#define portEIC_IPR_ADDR *( ( unsigned portLONG * ) 0xFFFFF840 ) +#define portCLEAR_EIC() portEIC_IPR_ADDR = 0x01 << portEIC_CICR_ADDR + +/*-----------------------------------------------------------*/ + +/* Compiler specifics */ +#define inline + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + + diff --git a/20080212/Source/portable/IAR/STR75x/ISR_Support.h b/20080212/Source/portable/IAR/STR75x/ISR_Support.h new file mode 100644 index 000000000..a0337890d --- /dev/null +++ b/20080212/Source/portable/IAR/STR75x/ISR_Support.h @@ -0,0 +1,108 @@ +; FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. +; +; This file is part of the FreeRTOS.org distribution. +; +; FreeRTOS.org is free software; you can redistribute it and/or modify +; it under the terms of the GNU General Public License as published by +; the Free Software Foundation; either version 2 of the License, or +; (at your option) any later version. +; +; FreeRTOS.org is distributed in the hope that it will be useful, +; but WITHOUT ANY WARRANTY; without even the implied warranty of +; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +; GNU General Public License for more details. +; +; You should have received a copy of the GNU General Public License +; along with FreeRTOS.org; if not, write to the Free Software +; Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +; +; A special exception to the GPL can be applied should you wish to distribute +; a combined work that includes FreeRTOS.org, without being obliged to provide +; the source code for any proprietary components. See the licensing section +; of http://www.FreeRTOS.org for full details of how and when the exception +; can be applied. +; +; *************************************************************************** +; See http://www.FreeRTOS.org for documentation, latest information, license +; and contact details. Please ensure to read the configuration and relevant +; port sections of the online documentation. +; *************************************************************************** + + EXTERN pxCurrentTCB + EXTERN ulCriticalNesting + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Context save and restore macro definitions +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +portSAVE_CONTEXT MACRO + + ; Push R0 as we are going to use the register. + STMDB SP!, {R0} + + ; Set R0 to point to the task stack pointer. + STMDB SP, {SP}^ + NOP + SUB SP, SP, #4 + LDMIA SP!, {R0} + + ; Push the return address onto the stack. + STMDB R0!, {LR} + + ; Now we have saved LR we can use it instead of R0. + MOV LR, R0 + + ; Pop R0 so we can save it onto the system mode stack. + LDMIA SP!, {R0} + + ; Push all the system mode registers onto the task stack. + STMDB LR, {R0-LR}^ + NOP + SUB LR, LR, #60 + + ; Push the SPSR onto the task stack. + MRS R0, SPSR + STMDB LR!, {R0} + + LDR R0, =ulCriticalNesting + LDR R0, [R0] + STMDB LR!, {R0} + + ; Store the new top of stack for the task. + LDR R1, =pxCurrentTCB + LDR R0, [R1] + STR LR, [R0] + + ENDM + + +portRESTORE_CONTEXT MACRO + + ; Set the LR to the task stack. + LDR R1, =pxCurrentTCB + LDR R0, [R1] + LDR LR, [R0] + + ; The critical nesting depth is the first item on the stack. + ; Load it into the ulCriticalNesting variable. + LDR R0, =ulCriticalNesting + LDMFD LR!, {R1} + STR R1, [R0] + + ; Get the SPSR from the stack. + LDMFD LR!, {R0} + MSR SPSR_cxsf, R0 + + ; Restore all system mode registers for the task. + LDMFD LR, {R0-R14}^ + NOP + + ; Restore the return address. + LDR LR, [LR, #+60] + + ; And return - correcting the offset in the LR to obtain the + ; correct address. + SUBS PC, LR, #4 + + ENDM + diff --git a/20080212/Source/portable/IAR/STR75x/port.c b/20080212/Source/portable/IAR/STR75x/port.c new file mode 100644 index 000000000..786be45e1 --- /dev/null +++ b/20080212/Source/portable/IAR/STR75x/port.c @@ -0,0 +1,251 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the ST STR75x ARM7 + * port. + *----------------------------------------------------------*/ + +/* Library includes. */ +#include "75x_tb.h" +#include "75x_eic.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to setup the initial stack. */ +#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */ +#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 ) + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 ) + +/* Prescale used on the timer clock when calculating the tick period. */ +#define portPRESCALE 20 + + +/*-----------------------------------------------------------*/ + +/* Setup the TB to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/* ulCriticalNesting will get set to zero when the first task starts. It +cannot be initialised to 0 as this will cause interrupts to be enabled +during the kernel initialisation process. */ +unsigned portLONG ulCriticalNesting = ( unsigned portLONG ) 9999; + +/* Tick interrupt routines for preemptive operation. */ +__arm void vPortPreemptiveTick( void ); + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ +portSTACK_TYPE *pxOriginalTOS; + + pxOriginalTOS = pxTopOfStack; + + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. */ + + /* First on the stack is the return address - which in this case is the + start of the task. The offset is added to make the return address appear + as it would within an IRQ ISR. */ + *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */ + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + R0. */ + *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The status register is set for system mode, with interrupts enabled. */ + *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR; + pxTopOfStack--; + + /* Interrupt flags cannot always be stored on the stack and will + instead be stored in a variable, which is then saved as part of the + tasks context. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xPortStartScheduler( void ) +{ +extern void vPortStartFirstTask( void ); + + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ARM port will require this function as there + is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +__arm void vPortPreemptiveTick( void ) +{ + /* Increment the tick counter. */ + vTaskIncrementTick(); + + /* The new tick value might unblock a task. Ensure the highest task that + is ready to execute is the task that will execute when the tick ISR + exits. */ + #if configUSE_PREEMPTION == 1 + vTaskSwitchContext(); + #endif + + TB_ClearITPendingBit( TB_IT_Update ); +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ +EIC_IRQInitTypeDef EIC_IRQInitStructure; +TB_InitTypeDef TB_InitStructure; + + /* Setup the EIC for the TB. */ + EIC_IRQInitStructure.EIC_IRQChannelCmd = ENABLE; + EIC_IRQInitStructure.EIC_IRQChannel = TB_IRQChannel; + EIC_IRQInitStructure.EIC_IRQChannelPriority = 1; + EIC_IRQInit(&EIC_IRQInitStructure); + + /* Setup the TB for the generation of the tick interrupt. */ + TB_InitStructure.TB_Mode = TB_Mode_Timing; + TB_InitStructure.TB_CounterMode = TB_CounterMode_Down; + TB_InitStructure.TB_Prescaler = portPRESCALE; + TB_InitStructure.TB_AutoReload = ( ( configCPU_CLOCK_HZ / ( portPRESCALE + 1 ) ) / configTICK_RATE_HZ ) + 1; + TB_Init(&TB_InitStructure); + + /* Enable TB Update interrupt */ + TB_ITConfig(TB_IT_Update, ENABLE); + + /* Clear TB Update interrupt pending bit */ + TB_ClearITPendingBit(TB_IT_Update); + + /* Enable TB */ + TB_Cmd(ENABLE); +} +/*-----------------------------------------------------------*/ + +__arm __interwork void vPortEnterCritical( void ) +{ + /* Disable interrupts first! */ + __disable_interrupt(); + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +__arm __interwork void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + __enable_interrupt(); + } + } +} +/*-----------------------------------------------------------*/ + + + + + + diff --git a/20080212/Source/portable/IAR/STR75x/portasm.s79 b/20080212/Source/portable/IAR/STR75x/portasm.s79 new file mode 100644 index 000000000..49d247baf --- /dev/null +++ b/20080212/Source/portable/IAR/STR75x/portasm.s79 @@ -0,0 +1,66 @@ +; FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. +; +; This file is part of the FreeRTOS.org distribution. +; +; FreeRTOS.org is free software; you can redistribute it and/or modify +; it under the terms of the GNU General Public License as published by +; the Free Software Foundation; either version 2 of the License, or +; (at your option) any later version. +; +; FreeRTOS.org is distributed in the hope that it will be useful, +; but WITHOUT ANY WARRANTY; without even the implied warranty of +; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +; GNU General Public License for more details. +; +; You should have received a copy of the GNU General Public License +; along with FreeRTOS.org; if not, write to the Free Software +; Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +; +; A special exception to the GPL can be applied should you wish to distribute +; a combined work that includes FreeRTOS.org, without being obliged to provide +; the source code for any proprietary components. See the licensing section +; of http://www.FreeRTOS.org for full details of how and when the exception +; can be applied. +; +; *************************************************************************** +; See http://www.FreeRTOS.org for documentation, latest information, license +; and contact details. Please ensure to read the configuration and relevant +; port sections of the online documentation. +; *************************************************************************** + + RSEG ICODE:CODE + CODE32 + + EXTERN vPortPreemptiveTick + EXTERN vTaskSwitchContext + + PUBLIC vPortYieldProcessor + PUBLIC vPortStartFirstTask + +#include "ISR_Support.h" + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Starting the first task is just a matter of restoring the context that +; was created by pxPortInitialiseStack(). +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortStartFirstTask: + portRESTORE_CONTEXT + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Manual context switch function. This is the SWI hander. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortYieldProcessor: + ADD LR, LR, #4 ; Add 4 to the LR to make the LR appear exactly + ; as if the context was saved during and IRQ + ; handler. + + portSAVE_CONTEXT ; Save the context of the current task... + LDR R0, =vTaskSwitchContext ; before selecting the next task to execute. + mov lr, pc + BX R0 + portRESTORE_CONTEXT ; Restore the context of the selected task. + + + + END + diff --git a/20080212/Source/portable/IAR/STR75x/portmacro.h b/20080212/Source/portable/IAR/STR75x/portmacro.h new file mode 100644 index 000000000..8557ddff6 --- /dev/null +++ b/20080212/Source/portable/IAR/STR75x/portmacro.h @@ -0,0 +1,124 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned portLONG +#define portBASE_TYPE portLONG + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 4 +#define portYIELD() asm ( "SWI 0" ) +#define portNOP() asm ( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +__arm __interwork void vPortEnterCritical( void ); +__arm __interwork void vPortExitCritical( void ); + +#define portDISABLE_INTERRUPTS() __disable_interrupt() +#define portENABLE_INTERRUPTS() __enable_interrupt() +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ +{ \ +extern void vTaskSwitchContext( void ); \ + \ + if( xSwitchRequired ) \ + { \ + vTaskSwitchContext(); \ + } \ +} +/*-----------------------------------------------------------*/ + +/* Compiler specifics */ +#define inline + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + + diff --git a/20080212/Source/portable/IAR/STR91x/ISR_Support.h b/20080212/Source/portable/IAR/STR91x/ISR_Support.h new file mode 100644 index 000000000..c4eefffff --- /dev/null +++ b/20080212/Source/portable/IAR/STR91x/ISR_Support.h @@ -0,0 +1,120 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + EXTERN pxCurrentTCB + EXTERN ulCriticalNesting + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Context save and restore macro definitions +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +portSAVE_CONTEXT MACRO + + ; Push R0 as we are going to use the register. + STMDB SP!, {R0} + + ; Set R0 to point to the task stack pointer. + STMDB SP, {SP}^ + NOP + SUB SP, SP, #4 + LDMIA SP!, {R0} + + ; Push the return address onto the stack. + STMDB R0!, {LR} + + ; Now we have saved LR we can use it instead of R0. + MOV LR, R0 + + ; Pop R0 so we can save it onto the system mode stack. + LDMIA SP!, {R0} + + ; Push all the system mode registers onto the task stack. + STMDB LR, {R0-LR}^ + NOP + SUB LR, LR, #60 + + ; Push the SPSR onto the task stack. + MRS R0, SPSR + STMDB LR!, {R0} + + LDR R0, =ulCriticalNesting + LDR R0, [R0] + STMDB LR!, {R0} + + ; Store the new top of stack for the task. + LDR R1, =pxCurrentTCB + LDR R0, [R1] + STR LR, [R0] + + ENDM + + +portRESTORE_CONTEXT MACRO + + ; Set the LR to the task stack. + LDR R1, =pxCurrentTCB + LDR R0, [R1] + LDR LR, [R0] + + ; The critical nesting depth is the first item on the stack. + ; Load it into the ulCriticalNesting variable. + LDR R0, =ulCriticalNesting + LDMFD LR!, {R1} + STR R1, [R0] + + ; Get the SPSR from the stack. + LDMFD LR!, {R0} + MSR SPSR_cxsf, R0 + + ; Restore all system mode registers for the task. + LDMFD LR, {R0-R14}^ + NOP + + ; Restore the return address. + LDR LR, [LR, #+60] + + ; And return - correcting the offset in the LR to obtain the + ; correct address. + SUBS PC, LR, #4 + + ENDM + diff --git a/20080212/Source/portable/IAR/STR91x/port.c b/20080212/Source/portable/IAR/STR91x/port.c new file mode 100644 index 000000000..acde59bbd --- /dev/null +++ b/20080212/Source/portable/IAR/STR91x/port.c @@ -0,0 +1,442 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the ST STR91x ARM9 + * port. + *----------------------------------------------------------*/ + +/* Library includes. */ +#include "91x_lib.h" + +/* Standard includes. */ +#include +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#ifndef configUSE_WATCHDOG_TICK + #error configUSE_WATCHDOG_TICK must be set to either 1 or 0 in FreeRTOSConfig.h to use either the Watchdog or timer 2 to generate the tick interrupt respectively. +#endif + +/* Constants required to setup the initial stack. */ +#ifndef _RUN_TASK_IN_ARM_MODE_ + #define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */ +#else + #define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#endif + +#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 ) + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 ) + +#ifndef abs + #define abs(x) ((x)>0 ? (x) : -(x)) +#endif + +/** + * Toggle a led using the following algorithm: + * if ( GPIO_ReadBit(GPIO9, GPIO_Pin_2) ) + * { + * GPIO_WriteBit( GPIO9, GPIO_Pin_2, Bit_RESET ); + * } + * else + * { + * GPIO_WriteBit( GPIO9, GPIO_Pin_2, Bit_RESET ); + * } + * + */ +#define TOGGLE_LED(port,pin) \ + if ( ((((port)->DR[(pin)<<2])) & (pin)) != Bit_RESET ) \ + { \ + (port)->DR[(pin) <<2] = 0x00; \ + } \ + else \ + { \ + (port)->DR[(pin) <<2] = (pin); \ + } + + +/*-----------------------------------------------------------*/ + +/* Setup the watchdog to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/* ulCriticalNesting will get set to zero when the first task starts. It +cannot be initialised to 0 as this will cause interrupts to be enabled +during the kernel initialisation process. */ +unsigned portLONG ulCriticalNesting = ( unsigned portLONG ) 9999; + +/* Tick interrupt routines for cooperative and preemptive operation +respectively. The preemptive version is not defined as __irq as it is called +from an asm wrapper function. */ +void WDG_IRQHandler( void ); + +/* VIC interrupt default handler. */ +static void prvDefaultHandler( void ); + +#if configUSE_WATCHDOG_TICK == 0 + /* Used to update the OCR timer register */ + static u16 s_nPulseLength; +#endif + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ + portSTACK_TYPE *pxOriginalTOS; + + pxOriginalTOS = pxTopOfStack; + + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. */ + + /* First on the stack is the return address - which in this case is the + start of the task. The offset is added to make the return address appear + as it would within an IRQ ISR. */ + *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */ + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + R0. */ + *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The status register is set for system mode, with interrupts enabled. */ + *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR; + pxTopOfStack--; + + /* Interrupt flags cannot always be stored on the stack and will + instead be stored in a variable, which is then saved as part of the + tasks context. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xPortStartScheduler( void ) +{ +extern void vPortStartFirstTask( void ); + + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ARM port will require this function as there + is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +/* This function is called from an asm wrapper, so does not require the __irq +keyword. */ +#if configUSE_WATCHDOG_TICK == 1 + + static void prvFindFactors(u32 n, u16 *a, u32 *b) + { + /* This function is copied from the ST STR7 library and is + copyright STMicroelectronics. Reproduced with permission. */ + + u32 b0; + u16 a0; + long err, err_min=n; + + *a = a0 = ((n-1)/65536ul) + 1; + *b = b0 = n / *a; + + for (; *a <= 256; (*a)++) + { + *b = n / *a; + err = (long)*a * (long)*b - (long)n; + if (abs(err) > (*a / 2)) + { + (*b)++; + err = (long)*a * (long)*b - (long)n; + } + if (abs(err) < abs(err_min)) + { + err_min = err; + a0 = *a; + b0 = *b; + if (err == 0) break; + } + } + + *a = a0; + *b = b0; + } + /*-----------------------------------------------------------*/ + + static void prvSetupTimerInterrupt( void ) + { + WDG_InitTypeDef xWdg; + unsigned portSHORT a; + unsigned portLONG n = configCPU_PERIPH_HZ / configTICK_RATE_HZ, b; + + /* Configure the watchdog as a free running timer that generates a + periodic interrupt. */ + + SCU_APBPeriphClockConfig( __WDG, ENABLE ); + WDG_DeInit(); + WDG_StructInit(&xWdg); + prvFindFactors( n, &a, &b ); + xWdg.WDG_Prescaler = a - 1; + xWdg.WDG_Preload = b - 1; + WDG_Init( &xWdg ); + WDG_ITConfig(ENABLE); + + /* Configure the VIC for the WDG interrupt. */ + VIC_Config( WDG_ITLine, VIC_IRQ, 10 ); + VIC_ITCmd( WDG_ITLine, ENABLE ); + + /* Install the default handlers for both VIC's. */ + VIC0->DVAR = ( unsigned portLONG ) prvDefaultHandler; + VIC1->DVAR = ( unsigned portLONG ) prvDefaultHandler; + + WDG_Cmd(ENABLE); + } + /*-----------------------------------------------------------*/ + + void WDG_IRQHandler( void ) + { + { + /* Increment the tick counter. */ + vTaskIncrementTick(); + + #if configUSE_PREEMPTION == 1 + { + /* The new tick value might unblock a task. Ensure the highest task that + is ready to execute is the task that will execute when the tick ISR + exits. */ + vTaskSwitchContext(); + } + #endif /* configUSE_PREEMPTION. */ + + /* Clear the interrupt in the watchdog. */ + WDG->SR &= ~0x0001; + } + } + +#else + + static void prvFindFactors(u32 n, u8 *a, u16 *b) + { + /* This function is copied from the ST STR7 library and is + copyright STMicroelectronics. Reproduced with permission. */ + + u16 b0; + u8 a0; + long err, err_min=n; + + + *a = a0 = ((n-1)/256) + 1; + *b = b0 = n / *a; + + for (; *a <= 256; (*a)++) + { + *b = n / *a; + err = (long)*a * (long)*b - (long)n; + if (abs(err) > (*a / 2)) + { + (*b)++; + err = (long)*a * (long)*b - (long)n; + } + if (abs(err) < abs(err_min)) + { + err_min = err; + a0 = *a; + b0 = *b; + if (err == 0) break; + } + } + + *a = a0; + *b = b0; + } + /*-----------------------------------------------------------*/ + + static void prvSetupTimerInterrupt( void ) + { + unsigned portCHAR a; + unsigned portSHORT b; + unsigned portLONG n = configCPU_PERIPH_HZ / configTICK_RATE_HZ; + + TIM_InitTypeDef timer; + + SCU_APBPeriphClockConfig( __TIM23, ENABLE ); + TIM_DeInit(TIM2); + TIM_StructInit(&timer); + prvFindFactors( n, &a, &b ); + + timer.TIM_Mode = TIM_OCM_CHANNEL_1; + timer.TIM_OC1_Modes = TIM_TIMING; + timer.TIM_Clock_Source = TIM_CLK_APB; + timer.TIM_Clock_Edge = TIM_CLK_EDGE_RISING; + timer.TIM_Prescaler = a-1; + timer.TIM_Pulse_Level_1 = TIM_HIGH; + timer.TIM_Pulse_Length_1 = s_nPulseLength = b-1; + + TIM_Init (TIM2, &timer); + TIM_ITConfig(TIM2, TIM_IT_OC1, ENABLE); + /* Configure the VIC for the WDG interrupt. */ + VIC_Config( TIM2_ITLine, VIC_IRQ, 10 ); + VIC_ITCmd( TIM2_ITLine, ENABLE ); + + /* Install the default handlers for both VIC's. */ + VIC0->DVAR = ( unsigned portLONG ) prvDefaultHandler; + VIC1->DVAR = ( unsigned portLONG ) prvDefaultHandler; + + TIM_CounterCmd(TIM2, TIM_CLEAR); + TIM_CounterCmd(TIM2, TIM_START); + } + /*-----------------------------------------------------------*/ + + void TIM2_IRQHandler( void ) + { + /* Reset the timer counter to avioid overflow. */ + TIM2->OC1R += s_nPulseLength; + + /* Increment the tick counter. */ + vTaskIncrementTick(); + + #if configUSE_PREEMPTION == 1 + { + /* The new tick value might unblock a task. Ensure the highest task that + is ready to execute is the task that will execute when the tick ISR + exits. */ + vTaskSwitchContext(); + } + #endif + + /* Clear the interrupt in the watchdog. */ + TIM2->SR &= ~TIM_FLAG_OC1; + } + +#endif /* USE_WATCHDOG_TICK */ + +/*-----------------------------------------------------------*/ + +__arm __interwork void vPortEnterCritical( void ) +{ + /* Disable interrupts first! */ + portDISABLE_INTERRUPTS(); + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +__arm __interwork void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + portENABLE_INTERRUPTS(); + } + } +} +/*-----------------------------------------------------------*/ + +static void prvDefaultHandler( void ) +{ +} + + + + + diff --git a/20080212/Source/portable/IAR/STR91x/portasm.s79 b/20080212/Source/portable/IAR/STR91x/portasm.s79 new file mode 100644 index 000000000..fb2ee8bc1 --- /dev/null +++ b/20080212/Source/portable/IAR/STR91x/portasm.s79 @@ -0,0 +1,75 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + RSEG ICODE:CODE + CODE32 + + EXTERN vTaskSwitchContext + + PUBLIC vPortYieldProcessor + PUBLIC vPortStartFirstTask + +#include "ISR_Support.h" + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Starting the first task is just a matter of restoring the context that +; was created by pxPortInitialiseStack(). +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortStartFirstTask: + portRESTORE_CONTEXT + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Manual context switch function. This is the SWI hander. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortYieldProcessor: + ADD LR, LR, #4 ; Add 4 to the LR to make the LR appear exactly + ; as if the context was saved during and IRQ + ; handler. + + portSAVE_CONTEXT ; Save the context of the current task... + LDR R0, =vTaskSwitchContext ; before selecting the next task to execute. + MOV lr, pc + BX R0 + portRESTORE_CONTEXT ; Restore the context of the selected task. + + END + diff --git a/20080212/Source/portable/IAR/STR91x/portmacro.h b/20080212/Source/portable/IAR/STR91x/portmacro.h new file mode 100644 index 000000000..a06b1071a --- /dev/null +++ b/20080212/Source/portable/IAR/STR91x/portmacro.h @@ -0,0 +1,126 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned portLONG +#define portBASE_TYPE portLONG + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 4 +#define portYIELD() asm ( "SWI 0" ) +#define portNOP() asm ( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +__arm __interwork void vPortEnterCritical( void ); +__arm __interwork void vPortExitCritical( void ); +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() + +#define portDISABLE_INTERRUPTS() __disable_interrupt() +#define portENABLE_INTERRUPTS() __enable_interrupt() + + +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ +{ \ +extern void vTaskSwitchContext( void ); \ + \ + if( xSwitchRequired ) \ + { \ + vTaskSwitchContext(); \ + } \ +} +/*-----------------------------------------------------------*/ + +/* Compiler specifics */ +#define inline + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + + diff --git a/20080212/Source/portable/Keil/ARM7/port.c b/20080212/Source/portable/Keil/ARM7/port.c new file mode 100644 index 000000000..5a96ee345 --- /dev/null +++ b/20080212/Source/portable/Keil/ARM7/port.c @@ -0,0 +1,252 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the ARM7 port + * using the Keil compiler. + * + * Components that can be compiled to either ARM or THUMB mode are + * contained in this file. The ISR routines, which can only be compiled + * to ARM mode are contained in portISR.c. + *----------------------------------------------------------*/ + +/* + Changes from V3.2.2 + + + Bug fix - The prescale value for the timer setup is now written to T0PR + instead of T0PC. This bug would have had no effect unless a prescale + value was actually used. +*/ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to setup the initial task context. */ +#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( portSTACK_TYPE ) 0x20 ) +#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 ) +#define portNO_CRITICAL_SECTION_NESTING ( ( portSTACK_TYPE ) 0 ) + +/* Constants required to setup the tick ISR. */ +#define portENABLE_TIMER ( ( unsigned portCHAR ) 0x01 ) +#define portPRESCALE_VALUE 0x00 +#define portINTERRUPT_ON_MATCH ( ( unsigned portLONG ) 0x01 ) +#define portRESET_COUNT_ON_MATCH ( ( unsigned portLONG ) 0x02 ) + +/* Constants required to setup the VIC for the tick ISR. */ +#define portTIMER_VIC_CHANNEL ( ( unsigned portLONG ) 0x0004 ) +#define portTIMER_VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x0010 ) +#define portTIMER_VIC_ENABLE ( ( unsigned portLONG ) 0x0020 ) + +/*-----------------------------------------------------------*/ + +/* Setup the timer to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/* + * The scheduler can only be started from ARM mode, so + * vPortISRStartFirstSTask() is defined in portISR.c. + */ +extern void vPortISRStartFirstTask( void ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ +portSTACK_TYPE *pxOriginalTOS; + + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. + + Remember where the top of the (simulated) stack is before we place + anything on it. */ + pxOriginalTOS = pxTopOfStack; + + /* First on the stack is the return address - which in this case is the + start of the task. The offset is added to make the return address appear + as it would within an IRQ ISR. */ + *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The last thing onto the stack is the status register, which is set for + system mode, with interrupts enabled. */ + *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR; + + #ifdef KEIL_THUMB_INTERWORK + { + /* We want the task to start in thumb mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + #endif + + pxTopOfStack--; + + /* The code generated by the Keil compiler does not maintain separate + stack and frame pointers. The portENTER_CRITICAL macro cannot therefore + use the stack as per other ports. Instead a variable is used to keep + track of the critical section nesting. This variable has to be stored + as part of the task context and is initially set to zero. */ + *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xPortStartScheduler( void ) +{ + /* Start the timer that generates the tick ISR. */ + prvSetupTimerInterrupt(); + + /* Start the first task. This is done from portISR.c as ARM mode must be + used. */ + vPortISRStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ARM port will require this function as there + is nothing to return to. If this is required - stop the tick ISR then + return back to main. */ +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ +unsigned portLONG ulCompareMatch; + + /* A 1ms tick does not require the use of the timer prescale. This is + defaulted to zero but can be used if necessary. */ + T0PR = portPRESCALE_VALUE; + + /* Calculate the match value required for our wanted tick rate. */ + ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ; + + /* Protect against divide by zero. Using an if() statement still results + in a warning - hence the #if. */ + #if portPRESCALE_VALUE != 0 + { + ulCompareMatch /= ( portPRESCALE_VALUE + 1 ); + } + #endif + + T0MR0 = ulCompareMatch; + + /* Generate tick with timer 0 compare match. */ + T0MCR = portRESET_COUNT_ON_MATCH | portINTERRUPT_ON_MATCH; + + /* Setup the VIC for the timer. */ + VICIntSelect &= ~( portTIMER_VIC_CHANNEL_BIT ); + VICIntEnable |= portTIMER_VIC_CHANNEL_BIT; + + /* The ISR installed depends on whether the preemptive or cooperative + scheduler is being used. */ + #if configUSE_PREEMPTION == 1 + { + #ifdef KEIL_THUMB_INTERWORK + extern void ( vPreemptiveTick )( void ) __arm __task; + #else + extern void ( vPreemptiveTick )( void ) __task; + #endif + + VICVectAddr0 = ( unsigned portLONG ) vPreemptiveTick; + } + #else + { + extern void ( vNonPreemptiveTick )( void ) __irq; + + VICVectAddr0 = ( portLONG ) vNonPreemptiveTick; + } + #endif + + VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE; + + /* Start the timer - interrupts are disabled when this function is called + so it is okay to do this here. */ + T0TCR = portENABLE_TIMER; +} +/*-----------------------------------------------------------*/ + + + diff --git a/20080212/Source/portable/Keil/ARM7/portISR.c b/20080212/Source/portable/Keil/ARM7/portISR.c new file mode 100644 index 000000000..5a8f808a5 --- /dev/null +++ b/20080212/Source/portable/Keil/ARM7/portISR.c @@ -0,0 +1,254 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +/*----------------------------------------------------------- + * Components that can be compiled to either ARM or THUMB mode are + * contained in port.c The ISR routines, which can only be compiled + * to ARM mode, are contained in this file. + *----------------------------------------------------------*/ + +/* This file must always be compiled to ARM mode as it contains ISR +definitions. */ +#pragma ARM + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to handle interrupts. */ +#define portTIMER_MATCH_ISR_BIT ( ( unsigned portCHAR ) 0x01 ) +#define portCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 ) + +/*-----------------------------------------------------------*/ + +/* The code generated by the Keil compiler does not maintain separate +stack and frame pointers. The portENTER_CRITICAL macro cannot therefore +use the stack as per other ports. Instead a variable is used to keep +track of the critical section nesting. This variable has to be stored +as part of the task context and must be initialised to a non zero value. */ + +#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 ) +volatile unsigned portLONG ulCriticalNesting = 9999UL; + +/*-----------------------------------------------------------*/ + +/* ISR to handle manual context switches (from a call to taskYIELD()). */ +void vPortYieldProcessor( void ); + +/* + * The scheduler can only be started from ARM mode, hence the inclusion of this + * function here. + */ +void vPortISRStartFirstTask( void ); + +/*-----------------------------------------------------------*/ + +void vPortISRStartFirstTask( void ) +{ + /* Simply start the scheduler. This is included here as it can only be + called from ARM mode. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * Interrupt service routine for the SWI interrupt. The vector table is + * configured within startup.s. + * + * vPortYieldProcessor() is used to manually force a context switch. The + * SWI interrupt is generated by a call to taskYIELD() or portYIELD(). + */ +void vPortYieldProcessor( void ) __task +{ + /* Within an IRQ ISR the link register has an offset from the true return + address, but an SWI ISR does not. Add the offset manually so the same + ISR return code can be used in both cases. */ + __asm{ ADD LR, LR, #4 }; + + /* Perform the context switch. */ + portSAVE_CONTEXT(); + vTaskSwitchContext(); + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * The ISR used for the scheduler tick depends on whether the cooperative or + * the preemptive scheduler is being used. + */ + +#if configUSE_PREEMPTION == 0 + + /* + * The cooperative scheduler requires a normal IRQ service routine to + * simply increment the system tick. + */ + void vNonPreemptiveTick( void ); + void vNonPreemptiveTick( void ) __irq + { + /* Increment the tick count - this may make a delaying task ready + to run - but a context switch is not performed. */ + vTaskIncrementTick(); + + /* Ready for the next interrupt. */ + T0IR = portTIMER_MATCH_ISR_BIT; + VICVectAddr = portCLEAR_VIC_INTERRUPT; + } + +#else + + /* + * The preemptive scheduler ISR is defined as "naked" as the full context + * is saved on entry as part of the context switch. + */ + void vPreemptiveTick( void ); + void vPreemptiveTick( void ) __task + { + /* Save the context of the current task. */ + portSAVE_CONTEXT(); + + /* Increment the tick count - this may make a delayed task ready to + run. */ + vTaskIncrementTick(); + + /* Find the highest priority task that is ready to run. */ + vTaskSwitchContext(); + + /* Ready for the next interrupt. */ + T0IR = portTIMER_MATCH_ISR_BIT; + VICVectAddr = portCLEAR_VIC_INTERRUPT; + + /* Restore the context of the highest priority task that is ready to + run. */ + portRESTORE_CONTEXT(); + } +#endif +/*-----------------------------------------------------------*/ + +/* + * The interrupt management utilities can only be called from ARM mode. When + * KEIL_THUMB_INTERWORK is defined the utilities are defined as functions here + * to ensure a switch to ARM mode. When KEIL_THUMB_INTERWORK is not defined + * then the utilities are defined as macros in portmacro.h - as per other + * ports. + */ +#ifdef KEIL_THUMB_INTERWORK + + void vPortDisableInterruptsFromThumb( void ) __task; + void vPortEnableInterruptsFromThumb( void ) __task; + + void vPortDisableInterruptsFromThumb( void ) __task + { + __asm{ STMDB SP!, {R0} }; /* Push R0. */ + __asm{ MRS R0, CPSR }; /* Get CPSR. */ + __asm{ ORR R0, R0, #0xC0 }; /* Disable IRQ, FIQ. */ + __asm{ MSR CPSR_CXSF, R0 }; /* Write back modified value. */ + __asm{ LDMIA SP!, {R0} }; /* Pop R0. */ + __asm{ BX R14 }; /* Return back to thumb. */ + } + + void vPortEnableInterruptsFromThumb( void ) __task + { + __asm{ STMDB SP!, {R0} }; /* Push R0. */ + __asm{ MRS R0, CPSR }; /* Get CPSR. */ + __asm{ BIC R0, R0, #0xC0 }; /* Enable IRQ, FIQ. */ + __asm{ MSR CPSR_CXSF, R0 }; /* Write back modified value. */ + __asm{ LDMIA SP!, {R0} }; /* Pop R0. */ + __asm{ BX R14 }; /* Return back to thumb. */ + } + +#endif /* KEIL_THUMB_INTERWORK */ + + + +/* The code generated by the Keil compiler does not maintain separate +stack and frame pointers. The portENTER_CRITICAL macro cannot therefore +use the stack as per other ports. Instead a variable is used to keep +track of the critical section nesting. This necessitates the use of a +function in place of the macro. */ + +void vPortEnterCritical( void ) +{ + /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ + __asm{ STMDB SP!, {R0} }; /* Push R0. */ + __asm{ MRS R0, CPSR }; /* Get CPSR. */ + __asm{ ORR R0, R0, #0xC0 }; /* Disable IRQ, FIQ. */ + __asm{ MSR CPSR_CXSF, R0 }; /* Write back modified value. */ + __asm{ LDMIA SP!, {R0} }; /* Pop R0. */ + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Enable interrupts as per portEXIT_CRITICAL(). */ + __asm{ STMDB SP!, {R0} }; /* Push R0. */ + __asm{ MRS R0, CPSR }; /* Get CPSR. */ + __asm{ BIC R0, R0, #0xC0 }; /* Enable IRQ, FIQ. */ + __asm{ MSR CPSR_CXSF, R0 }; /* Write back modified value. */ + __asm{ LDMIA SP!, {R0} }; /* Pop R0. */ + } + } +} + + + + + + + + + + diff --git a/20080212/Source/portable/Keil/ARM7/portmacro.h b/20080212/Source/portable/Keil/ARM7/portmacro.h new file mode 100644 index 000000000..0c054cd14 --- /dev/null +++ b/20080212/Source/portable/Keil/ARM7/portmacro.h @@ -0,0 +1,242 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned portLONG +#define portBASE_TYPE portLONG + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 4 +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +#define portRESTORE_CONTEXT() \ +{ \ +extern volatile unsigned portLONG ulCriticalNesting; \ +extern volatile void * volatile pxCurrentTCB; \ + \ + __asm{ LDR R1, =pxCurrentTCB };/* Set the LR to the task stack. The location was ... */ \ + __asm{ LDR R0, [R1] }; /* ... stored in pxCurrentTCB. */ \ + __asm{ LDR LR, [R0] }; \ + \ + __asm{ LDR R0, =ulCriticalNesting }; /* The critical nesting depth is the first item on ... */ \ + __asm{ LDMFD LR!, {R1 } } /* ... the stack. Load it into the ulCriticalNesting var. */ \ + __asm{ STR R1, [R0] } \ + \ + __asm{ LDMFD LR!, {R0} }; /* Get the SPSR from the stack. */ \ + __asm{ MSR SPSR_CXSF, R0 }; \ + \ + __asm{ LDMFD LR, {R0-R14}^ }; /* Restore all system mode registers for the task. */ \ + __asm{ NOP }; \ + \ + __asm{ LDR LR, [LR, #+60] }; /* Restore the return address. */ \ + \ + /* And return - correcting the offset in the LR to obtain ... */ \ + __asm{ SUBS PC, LR, #4 }; /* ... the correct address. */ \ +} +/*----------------------------------------------------------*/ + +#define portSAVE_CONTEXT() \ +{ \ +extern volatile unsigned portLONG ulCriticalNesting; \ +extern volatile void * volatile pxCurrentTCB; \ + \ + __asm{ STMDB SP!, {R0} }; /* Store R0 first as we need to use it. */ \ + \ + __asm{ STMDB SP,{SP}^ }; /* Set R0 to point to the task stack pointer. */ \ + __asm{ NOP }; \ + __asm{ SUB SP, SP, #4 }; \ + __asm{ LDMIA SP!,{R0} }; \ + \ + __asm{ STMDB R0!, {LR} }; /* Push the return address onto the stack. */ \ + __asm{ MOV LR, R0 }; /* Now we have saved LR we can use it instead of R0. */ \ + __asm{ LDMIA SP!, {R0} }; /* Pop R0 so we can save it onto the system mode stack. */ \ + \ + __asm{ STMDB LR,{R0-LR}^ }; /* Push all the system mode registers onto the task stack. */ \ + __asm{ NOP }; \ + __asm{ SUB LR, LR, #60 }; \ + \ + __asm{ MRS R0, SPSR }; /* Push the SPSR onto the task stack. */ \ + __asm{ STMDB LR!, {R0} }; \ + \ + __asm{ LDR R0, =ulCriticalNesting }; \ + __asm{ LDR R0, [R0] }; \ + __asm{ STMDB LR!, {R0} }; \ + \ + __asm{ LDR R0, =pxCurrentTCB };/* Store the new top of stack for the task. */ \ + __asm{ LDR R1, [R0] }; \ + __asm{ STR LR, [R1] }; \ +} + +/*----------------------------------------------------------- + * ISR entry and exit macros. These are only required if a task switch + * is required from an ISR. + *----------------------------------------------------------*/ + +#define portENTER_SWITCHING_ISR() \ + portSAVE_CONTEXT(); \ + { + +#define portEXIT_SWITCHING_ISR( SwitchRequired ) \ + /* If a switch is required then we just need to call */ \ + /* vTaskSwitchContext() as the context has already been */ \ + /* saved. */ \ + if( SwitchRequired ) \ + { \ + vTaskSwitchContext(); \ + } \ + } \ + /* Restore the context of which ever task is now the highest */ \ + /* priority that is ready to run. */ \ + portRESTORE_CONTEXT(); + + +/* Yield the processor - force a context switch. */ +#define portYIELD() __asm{ SWI 0 }; +/*-----------------------------------------------------------*/ + +/* Critical section management. */ + +/*----------------------------------------------------------- + * Interrupt control macros. + * + * The interrupt management utilities can only be called from ARM mode. When + * KEIL_THUMB_INTERWORK is defined the utilities are defined as functions in + * portISR.c to ensure a switch to ARM mode. When KEIL_THUMB_INTERWORK is not + * defined then the utilities are defined as macros here - as per other ports. + *----------------------------------------------------------*/ + +#ifdef KEIL_THUMB_INTERWORK + + extern void vPortDisableInterruptsFromThumb( void ) __task; + extern void vPortEnableInterruptsFromThumb( void ) __task; + + #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb() + #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb() + +#else + + /*-----------------------------------------------------------*/ + + #define portDISABLE_INTERRUPTS() \ + __asm{ STMDB SP!, {R0} }; /* Push R0. */ \ + __asm{ MRS R0, CPSR }; /* Get CPSR. */ \ + __asm{ ORR R0, R0, #0xC0 }; /* Disable IRQ, FIQ. */ \ + __asm{ MSR CPSR_CXSF, R0 }; /* Write back modified value. */ \ + __asm{ LDMIA SP!, {R0} } /* Pop R0. */ + + #define portENABLE_INTERRUPTS() \ + __asm{ STMDB SP!, {R0} }; /* Push R0. */ \ + __asm{ MRS R0, CPSR }; /* Get CPSR. */ \ + __asm{ BIC R0, R0, #0xC0 }; /* Enable IRQ, FIQ. */ \ + __asm{ MSR CPSR_CXSF, R0 }; /* Write back modified value. */ \ + __asm{ LDMIA SP!, {R0} } /* Pop R0. */ + +#endif /* KEIL_THUMB_INTERWORK */ + +/*----------------------------------------------------------- + * Critical section control + * + * The code generated by the Keil compiler does not maintain separate + * stack and frame pointers. The portENTER_CRITICAL macro cannot therefore + * use the stack as per other ports. Instead a variable is used to keep + * track of the critical section nesting. This necessitates the use of a + * function in place of the macro. + *----------------------------------------------------------*/ + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); +/*-----------------------------------------------------------*/ + +/* Compiler specifics. */ +#define inline +#define register +#define portNOP() __asm{ NOP } +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __task +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/20080212/Source/portable/MPLAB/PIC18F/port.c b/20080212/Source/portable/MPLAB/PIC18F/port.c new file mode 100644 index 000000000..d6d5e1e63 --- /dev/null +++ b/20080212/Source/portable/MPLAB/PIC18F/port.c @@ -0,0 +1,633 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes between V1.2.4 and V1.2.5 + + + Introduced portGLOBAL_INTERRUPT_FLAG definition to test the global + interrupt flag setting. Using the two bits defined within + portINITAL_INTERRUPT_STATE was causing the w register to get clobbered + before the test was performed. + +Changes from V1.2.5 + + + Set the interrupt vector address to 0x08. Previously it was at the + incorrect address for compatibility mode of 0x18. + +Changes from V2.1.1 + + + PCLATU and PCLATH are now saved as part of the context. This allows + function pointers to be used within tasks. Thanks to Javier Espeche + for the enhancement. + +Changes from V2.3.1 + + + TABLAT is now saved as part of the task context. + +Changes from V3.2.0 + + + TBLPTRU is now initialised to zero as the MPLAB compiler expects this + value and does not write to the register. +*/ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPLAB library include file. */ +#include "timers.h" + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the PIC port. + *----------------------------------------------------------*/ + +/* Hardware setup for tick. */ +#define portTIMER_FOSC_SCALE ( ( unsigned portLONG ) 4 ) + +/* Initial interrupt enable state for newly created tasks. This value is +copied into INTCON when a task switches in for the first time. */ +#define portINITAL_INTERRUPT_STATE 0xc0 + +/* Just the bit within INTCON for the global interrupt flag. */ +#define portGLOBAL_INTERRUPT_FLAG 0x80 + +/* Constant used for context switch macro when we require the interrupt +enable state to be unchanged when the interrupted task is switched back in. */ +#define portINTERRUPTS_UNCHANGED 0x00 + +/* Some memory areas get saved as part of the task context. These memory +area's get used by the compiler for temporary storage, especially when +performing mathematical operations, or when using 32bit data types. This +constant defines the size of memory area which must be saved. */ +#define portCOMPILER_MANAGED_MEMORY_SIZE ( ( unsigned portCHAR ) 0x13 ) + +/* We require the address of the pxCurrentTCB variable, but don't want to know +any details of its type. */ +typedef void tskTCB; +extern volatile tskTCB * volatile pxCurrentTCB; + +/* IO port constants. */ +#define portBIT_SET ( ( unsigned portCHAR ) 1 ) +#define portBIT_CLEAR ( ( unsigned portCHAR ) 0 ) + +/* + * The serial port ISR's are defined in serial.c, but are called from portable + * as they use the same vector as the tick ISR. + */ +void vSerialTxISR( void ); +void vSerialRxISR( void ); + +/* + * Perform hardware setup to enable ticks. + */ +static void prvSetupTimerInterrupt( void ); + +/* + * ISR to maintain the tick, and perform tick context switches if the + * preemptive scheduler is being used. + */ +static void prvTickISR( void ); + +/* + * ISR placed on the low priority vector. This calls the appropriate ISR for + * the actual interrupt. + */ +static void prvLowInterrupt( void ); + +/* + * Macro that pushes all the registers that make up the context of a task onto + * the stack, then saves the new top of stack into the TCB. + * + * If this is called from an ISR then the interrupt enable bits must have been + * set for the ISR to ever get called. Therefore we want to save the INTCON + * register with the enable bits forced to be set - and ucForcedInterruptFlags + * must contain these bit settings. This means the interrupts will again be + * enabled when the interrupted task is switched back in. + * + * If this is called from a manual context switch (i.e. from a call to yield), + * then we want to save the INTCON so it is restored with its current state, + * and ucForcedInterruptFlags must be 0. This allows a yield from within + * a critical section. + * + * The compiler uses some locations at the bottom of the memory for temporary + * storage during math and other computations. This is especially true if + * 32bit data types are utilised (as they are by the scheduler). The .tmpdata + * and MATH_DATA sections have to be stored in there entirety as part of a task + * context. This macro stores from data address 0x00 to + * portCOMPILER_MANAGED_MEMORY_SIZE. This is sufficient for the demo + * applications but you should check the map file for your project to ensure + * this is sufficient for your needs. It is not clear whether this size is + * fixed for all compilations or has the potential to be program specific. + */ +#define portSAVE_CONTEXT( ucForcedInterruptFlags ) \ +{ \ + _asm \ + /* Save the status and WREG registers first, as these will get modified \ + by the operations below. */ \ + MOVFF WREG, PREINC1 \ + MOVFF STATUS, PREINC1 \ + /* Save the INTCON register with the appropriate bits forced if \ + necessary - as described above. */ \ + MOVFF INTCON, WREG \ + IORLW ucForcedInterruptFlags \ + MOVFF WREG, PREINC1 \ + _endasm \ + \ + portDISABLE_INTERRUPTS(); \ + \ + _asm \ + /* Store the necessary registers to the stack. */ \ + MOVFF BSR, PREINC1 \ + MOVFF FSR2L, PREINC1 \ + MOVFF FSR2H, PREINC1 \ + MOVFF FSR0L, PREINC1 \ + MOVFF FSR0H, PREINC1 \ + MOVFF TABLAT, PREINC1 \ + MOVFF TBLPTRU, PREINC1 \ + MOVFF TBLPTRH, PREINC1 \ + MOVFF TBLPTRL, PREINC1 \ + MOVFF PRODH, PREINC1 \ + MOVFF PRODL, PREINC1 \ + MOVFF PCLATU, PREINC1 \ + MOVFF PCLATH, PREINC1 \ + /* Store the .tempdata and MATH_DATA areas as described above. */ \ + CLRF FSR0L, 0 \ + CLRF FSR0H, 0 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF INDF0, PREINC1 \ + MOVFF FSR0L, PREINC1 \ + MOVFF FSR0H, PREINC1 \ + /* Store the hardware stack pointer in a temp register before we \ + modify it. */ \ + MOVFF STKPTR, FSR0L \ + _endasm \ + \ + /* Store each address from the hardware stack. */ \ + while( STKPTR > ( unsigned portCHAR ) 0 ) \ + { \ + _asm \ + MOVFF TOSL, PREINC1 \ + MOVFF TOSH, PREINC1 \ + MOVFF TOSU, PREINC1 \ + POP \ + _endasm \ + } \ + \ + _asm \ + /* Store the number of addresses on the hardware stack (from the \ + temporary register). */ \ + MOVFF FSR0L, PREINC1 \ + MOVF PREINC1, 1, 0 \ + _endasm \ + \ + /* Save the new top of the software stack in the TCB. */ \ + _asm \ + MOVFF pxCurrentTCB, FSR0L \ + MOVFF pxCurrentTCB + 1, FSR0H \ + MOVFF FSR1L, POSTINC0 \ + MOVFF FSR1H, POSTINC0 \ + _endasm \ +} +/*-----------------------------------------------------------*/ + +/* + * This is the reverse of portSAVE_CONTEXT. See portSAVE_CONTEXT for more + * details. + */ +#define portRESTORE_CONTEXT() \ +{ \ + _asm \ + /* Set FSR0 to point to pxCurrentTCB->pxTopOfStack. */ \ + MOVFF pxCurrentTCB, FSR0L \ + MOVFF pxCurrentTCB + 1, FSR0H \ + \ + /* De-reference FSR0 to set the address it holds into FSR1. \ + (i.e. *( pxCurrentTCB->pxTopOfStack ) ). */ \ + MOVFF POSTINC0, FSR1L \ + MOVFF POSTINC0, FSR1H \ + \ + /* How many return addresses are there on the hardware stack? Discard \ + the first byte as we are pointing to the next free space. */ \ + MOVFF POSTDEC1, FSR0L \ + MOVFF POSTDEC1, FSR0L \ + _endasm \ + \ + /* Fill the hardware stack from our software stack. */ \ + STKPTR = 0; \ + \ + while( STKPTR < FSR0L ) \ + { \ + _asm \ + PUSH \ + MOVF POSTDEC1, 0, 0 \ + MOVWF TOSU, 0 \ + MOVF POSTDEC1, 0, 0 \ + MOVWF TOSH, 0 \ + MOVF POSTDEC1, 0, 0 \ + MOVWF TOSL, 0 \ + _endasm \ + } \ + \ + _asm \ + /* Restore the .tmpdata and MATH_DATA memory. */ \ + MOVFF POSTDEC1, FSR0H \ + MOVFF POSTDEC1, FSR0L \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, INDF0 \ + /* Restore the other registers forming the tasks context. */ \ + MOVFF POSTDEC1, PCLATH \ + MOVFF POSTDEC1, PCLATU \ + MOVFF POSTDEC1, PRODL \ + MOVFF POSTDEC1, PRODH \ + MOVFF POSTDEC1, TBLPTRL \ + MOVFF POSTDEC1, TBLPTRH \ + MOVFF POSTDEC1, TBLPTRU \ + MOVFF POSTDEC1, TABLAT \ + MOVFF POSTDEC1, FSR0H \ + MOVFF POSTDEC1, FSR0L \ + MOVFF POSTDEC1, FSR2H \ + MOVFF POSTDEC1, FSR2L \ + MOVFF POSTDEC1, BSR \ + /* The next byte is the INTCON register. Read this into WREG as some \ + manipulation is required. */ \ + MOVFF POSTDEC1, WREG \ + _endasm \ + \ + /* From the INTCON register, only the interrupt enable bits form part \ + of the tasks context. It is perfectly legitimate for another task to \ + have modified any other bits. We therefore only restore the top two bits. \ + */ \ + if( WREG & portGLOBAL_INTERRUPT_FLAG ) \ + { \ + _asm \ + MOVFF POSTDEC1, STATUS \ + MOVFF POSTDEC1, WREG \ + /* Return enabling interrupts. */ \ + RETFIE 0 \ + _endasm \ + } \ + else \ + { \ + _asm \ + MOVFF POSTDEC1, STATUS \ + MOVFF POSTDEC1, WREG \ + /* Return without effecting interrupts. The context may have \ + been saved from a critical region. */ \ + RETURN 0 \ + _endasm \ + } \ +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ +unsigned portLONG ulAddress; +unsigned portCHAR ucBlock; + + /* Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging. */ + + *pxTopOfStack = 0x11; + pxTopOfStack++; + *pxTopOfStack = 0x22; + pxTopOfStack++; + *pxTopOfStack = 0x33; + pxTopOfStack++; + + + /* Simulate how the stack would look after a call to vPortYield() generated + by the compiler. + + First store the function parameters. This is where the task will expect to + find them when it starts running. */ + ulAddress = ( unsigned portLONG ) pvParameters; + *pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned portLONG ) 0x00ff ); + pxTopOfStack++; + + ulAddress >>= 8; + *pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned portLONG ) 0x00ff ); + pxTopOfStack++; + + /* Next we just leave a space. When a context is saved the stack pointer + is incremented before it is used so as not to corrupt whatever the stack + pointer is actually pointing to. This is especially necessary during + function epilogue code generated by the compiler. */ + *pxTopOfStack = 0x44; + pxTopOfStack++; + + /* Next are all the registers that form part of the task context. */ + + *pxTopOfStack = ( portSTACK_TYPE ) 0x66; /* WREG. */ + pxTopOfStack++; + + *pxTopOfStack = ( portSTACK_TYPE ) 0xcc; /* Status. */ + pxTopOfStack++; + + /* INTCON is saved with interrupts enabled. */ + *pxTopOfStack = ( portSTACK_TYPE ) portINITAL_INTERRUPT_STATE; /* INTCON */ + pxTopOfStack++; + + *pxTopOfStack = ( portSTACK_TYPE ) 0x11; /* BSR. */ + pxTopOfStack++; + + *pxTopOfStack = ( portSTACK_TYPE ) 0x22; /* FSR2L. */ + pxTopOfStack++; + + *pxTopOfStack = ( portSTACK_TYPE ) 0x33; /* FSR2H. */ + pxTopOfStack++; + + *pxTopOfStack = ( portSTACK_TYPE ) 0x44; /* FSR0L. */ + pxTopOfStack++; + + *pxTopOfStack = ( portSTACK_TYPE ) 0x55; /* FSR0H. */ + pxTopOfStack++; + + *pxTopOfStack = ( portSTACK_TYPE ) 0x66; /* TABLAT. */ + pxTopOfStack++; + + *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* TBLPTRU. */ + pxTopOfStack++; + + *pxTopOfStack = ( portSTACK_TYPE ) 0x88; /* TBLPTRUH. */ + pxTopOfStack++; + + *pxTopOfStack = ( portSTACK_TYPE ) 0x99; /* TBLPTRUL. */ + pxTopOfStack++; + + *pxTopOfStack = ( portSTACK_TYPE ) 0xaa; /* PRODH. */ + pxTopOfStack++; + + *pxTopOfStack = ( portSTACK_TYPE ) 0xbb; /* PRODL. */ + pxTopOfStack++; + + *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* PCLATU. */ + pxTopOfStack++; + + *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* PCLATH. */ + pxTopOfStack++; + + /* Next the .tmpdata and MATH_DATA sections. */ + for( ucBlock = 0; ucBlock <= portCOMPILER_MANAGED_MEMORY_SIZE; ucBlock++ ) + { + *pxTopOfStack = ( portSTACK_TYPE ) ucBlock; + *pxTopOfStack++; + } + + /* Store the top of the global data section. */ + *pxTopOfStack = ( portSTACK_TYPE ) portCOMPILER_MANAGED_MEMORY_SIZE; /* Low. */ + pxTopOfStack++; + + *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* High. */ + pxTopOfStack++; + + /* The only function return address so far is the address of the + task. */ + ulAddress = ( unsigned portLONG ) pxCode; + + /* TOS low. */ + *pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned portLONG ) 0x00ff ); + pxTopOfStack++; + ulAddress >>= 8; + + /* TOS high. */ + *pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned portLONG ) 0x00ff ); + pxTopOfStack++; + ulAddress >>= 8; + + /* TOS even higher. */ + *pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned portLONG ) 0x00ff ); + pxTopOfStack++; + + /* Store the number of return addresses on the hardware stack - so far only + the address of the task entry point. */ + *pxTopOfStack = ( portSTACK_TYPE ) 1; + pxTopOfStack++; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xPortStartScheduler( void ) +{ + /* Setup a timer for the tick ISR is using the preemptive scheduler. */ + prvSetupTimerInterrupt(); + + /* Restore the context of the first task to run. */ + portRESTORE_CONTEXT(); + + /* Should not get here. Use the function name to stop compiler warnings. */ + ( void ) prvLowInterrupt; + ( void ) prvTickISR; + + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the scheduler for the PIC port will get stopped + once running. If required disable the tick interrupt here, then return + to xPortStartScheduler(). */ +} +/*-----------------------------------------------------------*/ + +/* + * Manual context switch. This is similar to the tick context switch, + * but does not increment the tick count. It must be identical to the + * tick context switch in how it stores the stack of a task. + */ +void vPortYield( void ) +{ + /* This can get called with interrupts either enabled or disabled. We + will save the INTCON register with the interrupt enable bits unmodified. */ + portSAVE_CONTEXT( portINTERRUPTS_UNCHANGED ); + + /* Switch to the highest priority task that is ready to run. */ + vTaskSwitchContext(); + + /* Start executing the task we have just switched to. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * Vector for ISR. Nothing here must alter any registers! + */ +#pragma code high_vector=0x08 +static void prvLowInterrupt( void ) +{ + /* Was the interrupt the tick? */ + if( PIR1bits.CCP1IF ) + { + _asm + goto prvTickISR + _endasm + } + + /* Was the interrupt a byte being received? */ + if( PIR1bits.RCIF ) + { + _asm + goto vSerialRxISR + _endasm + } + + /* Was the interrupt the Tx register becoming empty? */ + if( PIR1bits.TXIF ) + { + if( PIE1bits.TXIE ) + { + _asm + goto vSerialTxISR + _endasm + } + } +} +#pragma code + +/*-----------------------------------------------------------*/ + +/* + * ISR for the tick. + * This increments the tick count and, if using the preemptive scheduler, + * performs a context switch. This must be identical to the manual + * context switch in how it stores the context of a task. + */ +static void prvTickISR( void ) +{ + /* Interrupts must have been enabled for the ISR to fire, so we have to + save the context with interrupts enabled. */ + portSAVE_CONTEXT( portGLOBAL_INTERRUPT_FLAG ); + PIR1bits.CCP1IF = 0; + + /* Maintain the tick count. */ + vTaskIncrementTick(); + + #if configUSE_PREEMPTION == 1 + { + /* Switch to the highest priority task that is ready to run. */ + vTaskSwitchContext(); + } + #endif + + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * Setup a timer for a regular tick. + */ +static void prvSetupTimerInterrupt( void ) +{ +const unsigned portLONG ulConstCompareValue = ( ( configCPU_CLOCK_HZ / portTIMER_FOSC_SCALE ) / configTICK_RATE_HZ ); +unsigned portLONG ulCompareValue; +unsigned portCHAR ucByte; + + /* Interrupts are disabled when this function is called. + + Setup CCP1 to provide the tick interrupt using a compare match on timer + 1. + + Clear the time count then setup timer. */ + TMR1H = ( unsigned portCHAR ) 0x00; + TMR1L = ( unsigned portCHAR ) 0x00; + + /* Set the compare match value. */ + ulCompareValue = ulConstCompareValue; + CCPR1L = ( unsigned portCHAR ) ( ulCompareValue & ( unsigned portLONG ) 0xff ); + ulCompareValue >>= ( unsigned portLONG ) 8; + CCPR1H = ( unsigned portCHAR ) ( ulCompareValue & ( unsigned portLONG ) 0xff ); + + CCP1CONbits.CCP1M0 = portBIT_SET; /*< Compare match mode. */ + CCP1CONbits.CCP1M1 = portBIT_SET; /*< Compare match mode. */ + CCP1CONbits.CCP1M2 = portBIT_CLEAR; /*< Compare match mode. */ + CCP1CONbits.CCP1M3 = portBIT_SET; /*< Compare match mode. */ + PIE1bits.CCP1IE = portBIT_SET; /*< Interrupt enable. */ + + /* We are only going to use the global interrupt bit, so set the peripheral + bit to true. */ + INTCONbits.GIEL = portBIT_SET; + + /* Provided library function for setting up the timer that will produce the + tick. */ + OpenTimer1( T1_16BIT_RW & T1_SOURCE_INT & T1_PS_1_1 & T1_CCP1_T3_CCP2 ); +} + diff --git a/20080212/Source/portable/MPLAB/PIC18F/portmacro.h b/20080212/Source/portable/MPLAB/PIC18F/portmacro.h new file mode 100644 index 000000000..c9274ddaa --- /dev/null +++ b/20080212/Source/portable/MPLAB/PIC18F/portmacro.h @@ -0,0 +1,120 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE unsigned char +#define portBASE_TYPE char + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 1 +#define portGLOBAL_INT_ENABLE_BIT 0x80 +#define portSTACK_GROWTH 1 +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +#define portDISABLE_INTERRUPTS() INTCONbits.GIEH = 0; +#define portENABLE_INTERRUPTS() INTCONbits.GIEH = 1; + +/* Push the INTCON register onto the stack, then disable interrupts. */ +#define portENTER_CRITICAL() POSTINC1 = INTCON; \ + INTCONbits.GIEH = 0; + +/* Retrieve the INTCON register from the stack, and enable interrupts +if they were saved as being enabled. Don't modify any other bits +within the INTCON register as these may have lagitimately have been +modified within the critical region. */ +#define portEXIT_CRITICAL() _asm \ + MOVF POSTDEC1, 1, 0 \ + _endasm \ + if( INDF1 & portGLOBAL_INT_ENABLE_BIT ) \ + { \ + portENABLE_INTERRUPTS(); \ + } +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +extern void vPortYield( void ); +#define portYIELD() vPortYield() +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +/*-----------------------------------------------------------*/ + +/* Compiler specifics. */ +#define inline + +#define portNOP() _asm \ + NOP \ + _endasm + +#endif /* PORTMACRO_H */ + diff --git a/20080212/Source/portable/MPLAB/PIC18F/stdio.h b/20080212/Source/portable/MPLAB/PIC18F/stdio.h new file mode 100644 index 000000000..e69de29bb diff --git a/20080212/Source/portable/MPLAB/PIC24_dsPIC/port.c b/20080212/Source/portable/MPLAB/PIC24_dsPIC/port.c new file mode 100644 index 000000000..36ffb8e7c --- /dev/null +++ b/20080212/Source/portable/MPLAB/PIC24_dsPIC/port.c @@ -0,0 +1,375 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + Changes from V4.2.1 + + + Introduced the configKERNEL_INTERRUPT_PRIORITY definition. +*/ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the PIC24 port. + *----------------------------------------------------------*/ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Hardware specifics. */ +#define portBIT_SET 1 +#define portTIMER_PRESCALE 8 +#define portINITIAL_SR 0 + +/* Defined for backward compatability with project created prior to +FreeRTOS.org V4.3.0. */ +#ifndef configKERNEL_INTERRUPT_PRIORITY + #define configKERNEL_INTERRUPT_PRIORITY 1 +#endif + +/* The program counter is only 23 bits. */ +#define portUNUSED_PR_BITS 0x7f + +/* Records the nesting depth of calls to portENTER_CRITICAL(). */ +unsigned portBASE_TYPE uxCriticalNesting = 0xef; + +#if configKERNEL_INTERRUPT_PRIORITY != 1 + #error If configKERNEL_INTERRUPT_PRIORITY is not 1 then the #32 in the following macros needs changing to equal the portINTERRUPT_BITS value, which is ( configKERNEL_INTERRUPT_PRIORITY << 5 ) +#endif + +#ifdef MPLAB_PIC24_PORT + + #define portRESTORE_CONTEXT() \ + asm volatile( "MOV _pxCurrentTCB, W0 \n" /* Restore the stack pointer for the task. */ \ + "MOV [W0], W15 \n" \ + "POP W0 \n" /* Restore the critical nesting counter for the task. */ \ + "MOV W0, _uxCriticalNesting \n" \ + "POP PSVPAG \n" \ + "POP CORCON \n" \ + "POP TBLPAG \n" \ + "POP RCOUNT \n" /* Restore the registers from the stack. */ \ + "POP W14 \n" \ + "POP.D W12 \n" \ + "POP.D W10 \n" \ + "POP.D W8 \n" \ + "POP.D W6 \n" \ + "POP.D W4 \n" \ + "POP.D W2 \n" \ + "POP.D W0 \n" \ + "POP SR " ); + + + #define portSAVE_CONTEXT() \ + asm volatile( "PUSH SR \n" /* Save the SR used by the task.... */ \ + "PUSH W0 \n" /* ....then disable interrupts. */ \ + "MOV #32, W0 \n" \ + "MOV W0, SR \n" \ + "PUSH W1 \n" /* Save registers to the stack. */ \ + "PUSH.D W2 \n" \ + "PUSH.D W4 \n" \ + "PUSH.D W6 \n" \ + "PUSH.D W8 \n" \ + "PUSH.D W10 \n" \ + "PUSH.D W12 \n" \ + "PUSH W14 \n" \ + "PUSH RCOUNT \n" \ + "PUSH TBLPAG \n" \ + "PUSH CORCON \n" \ + "PUSH PSVPAG \n" \ + "MOV _uxCriticalNesting, W0 \n" /* Save the critical nesting counter for the task. */ \ + "PUSH W0 \n" \ + "MOV _pxCurrentTCB, W0 \n" /* Save the new top of stack into the TCB. */ \ + "MOV W15, [W0] "); + +#endif /* MPLAB_PIC24_PORT */ + +#ifdef MPLAB_DSPIC_PORT + + #define portRESTORE_CONTEXT() \ + asm volatile( "MOV _pxCurrentTCB, W0 \n" /* Restore the stack pointer for the task. */ \ + "MOV [W0], W15 \n" \ + "POP W0 \n" /* Restore the critical nesting counter for the task. */ \ + "MOV W0, _uxCriticalNesting \n" \ + "POP PSVPAG \n" \ + "POP CORCON \n" \ + "POP DOENDH \n" \ + "POP DOENDL \n" \ + "POP DOSTARTH \n" \ + "POP DOSTARTL \n" \ + "POP DCOUNT \n" \ + "POP ACCBU \n" \ + "POP ACCBH \n" \ + "POP ACCBL \n" \ + "POP ACCAU \n" \ + "POP ACCAH \n" \ + "POP ACCAL \n" \ + "POP TBLPAG \n" \ + "POP RCOUNT \n" /* Restore the registers from the stack. */ \ + "POP W14 \n" \ + "POP.D W12 \n" \ + "POP.D W10 \n" \ + "POP.D W8 \n" \ + "POP.D W6 \n" \ + "POP.D W4 \n" \ + "POP.D W2 \n" \ + "POP.D W0 \n" \ + "POP SR " ); + + + #define portSAVE_CONTEXT() \ + asm volatile( "PUSH SR \n" /* Save the SR used by the task.... */ \ + "PUSH W0 \n" /* ....then disable interrupts. */ \ + "MOV #32, W0 \n" \ + "MOV W0, SR \n" \ + "PUSH W1 \n" /* Save registers to the stack. */ \ + "PUSH.D W2 \n" \ + "PUSH.D W4 \n" \ + "PUSH.D W6 \n" \ + "PUSH.D W8 \n" \ + "PUSH.D W10 \n" \ + "PUSH.D W12 \n" \ + "PUSH W14 \n" \ + "PUSH RCOUNT \n" \ + "PUSH TBLPAG \n" \ + "PUSH ACCAL \n" \ + "PUSH ACCAH \n" \ + "PUSH ACCAU \n" \ + "PUSH ACCBL \n" \ + "PUSH ACCBH \n" \ + "PUSH ACCBU \n" \ + "PUSH DCOUNT \n" \ + "PUSH DOSTARTL \n" \ + "PUSH DOSTARTH \n" \ + "PUSH DOENDL \n" \ + "PUSH DOENDH \n" \ + "PUSH CORCON \n" \ + "PUSH PSVPAG \n" \ + "MOV _uxCriticalNesting, W0 \n" /* Save the critical nesting counter for the task. */ \ + "PUSH W0 \n" \ + "MOV _pxCurrentTCB, W0 \n" /* Save the new top of stack into the TCB. */ \ + "MOV W15, [W0] " ); + +#endif /* MPLAB_DSPIC_PORT */ + +/* + * Setup the timer used to generate the tick interrupt. + */ +static void prvSetupTimerInterrupt( void ); + +/* + * See header file for description. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ +unsigned portSHORT usCode; +portBASE_TYPE i; + +const portSTACK_TYPE xInitialStack[] = +{ + 0x1111, /* W1 */ + 0x2222, /* W2 */ + 0x3333, /* W3 */ + 0x4444, /* W4 */ + 0x5555, /* W5 */ + 0x6666, /* W6 */ + 0x7777, /* W7 */ + 0x8888, /* W8 */ + 0x9999, /* W9 */ + 0xaaaa, /* W10 */ + 0xbbbb, /* W11 */ + 0xcccc, /* W12 */ + 0xdddd, /* W13 */ + 0xeeee, /* W14 */ + 0xcdce, /* RCOUNT */ + 0xabac, /* TBLPAG */ + + /* dsPIC specific registers. */ + #ifdef MPLAB_DSPIC_PORT + 0x0202, /* ACCAL */ + 0x0303, /* ACCAH */ + 0x0404, /* ACCAU */ + 0x0505, /* ACCBL */ + 0x0606, /* ACCBH */ + 0x0707, /* ACCBU */ + 0x0808, /* DCOUNT */ + 0x090a, /* DOSTARTL */ + 0x1010, /* DOSTARTH */ + 0x1110, /* DOENDL */ + 0x1212, /* DOENDH */ + #endif +}; + + /* Setup the stack as if a yield had occurred. + + Save the low bytes of the program counter. */ + usCode = ( unsigned portSHORT ) pxCode; + *pxTopOfStack = ( portSTACK_TYPE ) usCode; + pxTopOfStack++; + + /* Save the high byte of the program counter. This will always be zero + here as it is passed in a 16bit pointer. If the address is greater than + 16 bits then the pointer will point to a jump table. */ + *pxTopOfStack = ( portSTACK_TYPE ) 0; + pxTopOfStack++; + + /* Status register with interrupts enabled. */ + *pxTopOfStack = portINITIAL_SR; + pxTopOfStack++; + + /* Parameters are passed in W0. */ + *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; + pxTopOfStack++; + + for( i = 0; i < ( sizeof( xInitialStack ) / sizeof( portSTACK_TYPE ) ); i++ ) + { + *pxTopOfStack = xInitialStack[ i ]; + pxTopOfStack++; + } + + *pxTopOfStack = CORCON; + pxTopOfStack++; + *pxTopOfStack = PSVPAG; + pxTopOfStack++; + + /* Finally the critical nesting depth. */ + *pxTopOfStack = 0x00; + pxTopOfStack++; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xPortStartScheduler( void ) +{ + /* Setup a timer for the tick ISR. */ + prvSetupTimerInterrupt(); + + /* Restore the context of the first task to run. */ + portRESTORE_CONTEXT(); + + /* Simulate the end of the yield function. */ + asm volatile ( "return" ); + + /* Should not reach here. */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the scheduler for the PIC port will get stopped + once running. If required disable the tick interrupt here, then return + to xPortStartScheduler(). */ +} +/*-----------------------------------------------------------*/ + +/* + * Manual context switch. This is similar to the tick context switch, + * but does not increment the tick count. It must be identical to the + * tick context switch in how it stores the stack of a task. + */ +void vPortYield( void ) +{ + portSAVE_CONTEXT(); + vTaskSwitchContext(); + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * Setup a timer for a regular tick. + */ +static void prvSetupTimerInterrupt( void ) +{ +const unsigned portLONG ulCompareMatch = ( configCPU_CLOCK_HZ / portTIMER_PRESCALE ) / configTICK_RATE_HZ; + + /* Prescale of 8. */ + T1CON = 0; + TMR1 = 0; + + PR1 = ( unsigned portSHORT ) ulCompareMatch; + + /* Setup timer 1 interrupt priority. */ + IPC0bits.T1IP = configKERNEL_INTERRUPT_PRIORITY; + + /* Clear the interrupt as a starting condition. */ + IFS0bits.T1IF = 0; + + /* Enable the interrupt. */ + IEC0bits.T1IE = 1; + + /* Setup the prescale value. */ + T1CONbits.TCKPS0 = 1; + T1CONbits.TCKPS1 = 0; + + /* Start the timer. */ + T1CONbits.TON = 1; +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + uxCriticalNesting--; + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void __attribute__((__interrupt__, auto_psv)) _T1Interrupt( void ) +{ + vTaskIncrementTick(); + + /* Clear the timer interrupt. */ + IFS0bits.T1IF = 0; + + #if configUSE_PREEMPTION == 1 + portYIELD(); + #endif +} diff --git a/20080212/Source/portable/MPLAB/PIC24_dsPIC/portmacro.h b/20080212/Source/portable/MPLAB/PIC24_dsPIC/portmacro.h new file mode 100644 index 000000000..92b5735ff --- /dev/null +++ b/20080212/Source/portable/MPLAB/PIC24_dsPIC/portmacro.h @@ -0,0 +1,119 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned short +#define portBASE_TYPE short + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 2 +#define portSTACK_GROWTH 1 +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +#define portINTERRUPT_BITS ( ( unsigned portSHORT ) configKERNEL_INTERRUPT_PRIORITY << ( unsigned portSHORT ) 5 ) + +#define portDISABLE_INTERRUPTS() SR |= portINTERRUPT_BITS +#define portENABLE_INTERRUPTS() SR &= ~portINTERRUPT_BITS + +/* Note that exiting a critical sectino will set the IPL bits to 0, nomatter +what their value was prior to entering the critical section. */ +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +extern void vPortYield( void ); +#define portYIELD() asm volatile ( "CALL _vPortYield \n" \ + "NOP " ); +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +/*-----------------------------------------------------------*/ + +/* Compiler specifics. */ +#define inline + +#define portNOP() asm volatile ( "NOP" ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/20080212/Source/portable/MPLAB/PIC32MX/ISR_Support.h b/20080212/Source/portable/MPLAB/PIC32MX/ISR_Support.h new file mode 100644 index 000000000..7d53cedee --- /dev/null +++ b/20080212/Source/portable/MPLAB/PIC32MX/ISR_Support.h @@ -0,0 +1,197 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#include "FreeRTOSConfig.h" + +#define portCONTEXT_SIZE 136 +#define portEXL_AND_IE_BITS 0x03 + +#define portEPC_STACK_LOCATION 124 +#define portSTATUS_STACK_LOCATION 128 +#define portCAUSE_STACK_LOCATION 132 + +/******************************************************************/ +.macro portSAVE_CONTEXT + + /* Make room for the context. */ + addiu sp, sp, -portCONTEXT_SIZE + + /* Get interrupts above the kernel priority enabled again ASAP. First + save the current status so we can manipulate it, and the cause and EPC + registers so we capture their original values in case of interrupt nesting. */ + + mfc0 k0, _CP0_CAUSE + sw k0, portCAUSE_STACK_LOCATION(sp) + mfc0 k1, _CP0_STATUS + sw k1, portSTATUS_STACK_LOCATION(sp) + + /* Also save s6 so we can use it during this interrupt. Any + nesting interrupts should maintain the values of this register + accross the ISR. */ + sw s6, 44(sp) + + /* s6 holds the EPC value, we may want this during the context switch. */ + mfc0 s6, _CP0_EPC + + /* Enable interrupts above the kernel priority. */ + addiu k0, zero, configKERNEL_INTERRUPT_PRIORITY + ins k1, k0, 10, 6 + ins k1, zero, 1, 4 + mtc0 k1, _CP0_STATUS + + /* Save the context into the space just created. s6 is saved again + here as it now contains the EPC value. */ + sw ra, 120(sp) + sw s8, 116(sp) + sw t9, 112(sp) + sw t8, 108(sp) + sw t7, 104(sp) + sw t6, 100(sp) + sw t5, 96(sp) + sw t4, 92(sp) + sw t3, 88(sp) + sw t2, 84(sp) + sw t1, 80(sp) + sw t0, 76(sp) + sw a3, 72(sp) + sw a2, 68(sp) + sw a1, 64(sp) + sw a0, 60(sp) + sw v1, 56(sp) + sw v0, 52(sp) + sw s7, 48(sp) + sw s6, portEPC_STACK_LOCATION(sp) + sw s5, 40(sp) + sw s4, 36(sp) + sw s3, 32(sp) + sw s2, 28(sp) + sw s1, 24(sp) + sw s0, 20(sp) + sw $1, 16(sp) + + /* s7 is used as a scratch register. */ + mfhi s7 + sw s7, 12(sp) + mflo s7 + sw s7, 8(sp) + + /* Each task maintains its own nesting count. */ + la s7, uxCriticalNesting + lw s7, (s7) + sw s7, 4(sp) + + /* Update the TCB stack pointer value */ + la s7, pxCurrentTCB + lw s7, (s7) + sw sp, (s7) + + /* Switch to the ISR stack, saving the current stack in s5. This might + be used to determine the cause of a general exception. */ + add s5, zero, sp + la s7, xISRStackTop + lw sp, (s7) + + .endm + +/******************************************************************/ +.macro portRESTORE_CONTEXT + + /* Restore the stack pointer from the TCB */ + la s0, pxCurrentTCB + lw s1, (s0) + lw sp, (s1) + + /* Restore the context, the first item of which is the critical nesting + depth. */ + la s0, uxCriticalNesting + lw s1, 4(sp) + sw s1, (s0) + + /* Restore the rest of the context. */ + lw s0, 8(sp) + mtlo s0 + lw s0, 12(sp) + mthi s0 + lw $1, 16(sp) + lw s0, 20(sp) + lw s1, 24(sp) + lw s2, 28(sp) + lw s3, 32(sp) + lw s4, 36(sp) + lw s5, 40(sp) + lw s6, 44(sp) + lw s7, 48(sp) + lw v0, 52(sp) + lw v1, 56(sp) + lw a0, 60(sp) + lw a1, 64(sp) + lw a2, 68(sp) + lw a3, 72(sp) + lw t0, 76(sp) + lw t1, 80(sp) + lw t2, 84(sp) + lw t3, 88(sp) + lw t4, 92(sp) + lw t5, 96(sp) + lw t6, 100(sp) + lw t7, 104(sp) + lw t8, 108(sp) + lw t9, 112(sp) + lw s8, 116(sp) + lw ra, 120(sp) + + /* Protect access to the k registers. */ + di + lw k1, portSTATUS_STACK_LOCATION(sp) + lw k0, portEPC_STACK_LOCATION(sp) + + /* Leave the stack how we found it. */ + addiu sp, sp, portCONTEXT_SIZE + + mtc0 k1, _CP0_STATUS + ehb + mtc0 k0, _CP0_EPC + eret + nop + + .endm + diff --git a/20080212/Source/portable/MPLAB/PIC32MX/port.c b/20080212/Source/portable/MPLAB/PIC32MX/port.c new file mode 100644 index 000000000..089b62244 --- /dev/null +++ b/20080212/Source/portable/MPLAB/PIC32MX/port.c @@ -0,0 +1,198 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the PIC32MX port. + *----------------------------------------------------------*/ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Hardware specifics. */ +#define portTIMER_PRESCALE 8 + +/* Bits within various registers. */ +#define portIE_BIT ( 0x00000001 ) +#define portEXL_BIT ( 0x00000002 ) +#define portIPL_SHIFT ( 10 ) +#define portALL_IPL_BITS ( 0x1f << portIPL_SHIFT ) + +/* The EXL bit is set to ensure interrupts do not occur while the context of +the first task is being restored. */ +#define portINITIAL_SR ( portIE_BIT | portEXL_BIT ) + +/* Records the nesting depth of calls to portENTER_CRITICAL(). */ +unsigned portBASE_TYPE uxCriticalNesting = 0x55555555; + +/* The stack used by interrupt service routines that cause a context switch. */ +portSTACK_TYPE xISRStack[ configISR_STACK_SIZE ] = { 0 }; + +/* The top of stack value ensures there is enough space to store 6 registers on +the callers stack, as some functions seem to want to do this. */ +const portBASE_TYPE * const xISRStackTop = &( xISRStack[ configISR_STACK_SIZE - 7 ] ); + +/* Place the prototype here to ensure the interrupt vector is correctly installed. */ +extern void __attribute__( (interrupt(ipl1), vector(_TIMER_1_VECTOR))) vT1InterruptHandler( void ); + +/* + * General exception handler that will be called for all general exceptions + * other than SYS. This should be overridden by a user provided handler. + */ +void vApplicationGeneralExceptionHandler( unsigned portLONG ulCause, unsigned portLONG ulStatus ) __attribute__((weak)); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ + *pxTopOfStack = (portSTACK_TYPE) 0xDEADBEEF; + pxTopOfStack--; + + *pxTopOfStack = (portSTACK_TYPE) 0x12345678; /* Word to which the stack pointer will be left pointing after context restore. */ + pxTopOfStack--; + + *pxTopOfStack = (portSTACK_TYPE) _CP0_GET_CAUSE(); + pxTopOfStack--; + + *pxTopOfStack = (portSTACK_TYPE) portINITIAL_SR; /* CP0_STATUS */ + pxTopOfStack--; + + *pxTopOfStack = (portSTACK_TYPE) pxCode; /* CP0_EPC */ + pxTopOfStack--; + + *pxTopOfStack = (portSTACK_TYPE) NULL; /* ra */ + pxTopOfStack -= 15; + + *pxTopOfStack = (portSTACK_TYPE) pvParameters; /* Parameters to pass in */ + pxTopOfStack -= 14; + + *pxTopOfStack = (portSTACK_TYPE) 0x00000000; /* critical nesting level */ + pxTopOfStack--; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +/* + * Setup a timer for a regular tick. + */ +void prvSetupTimerInterrupt( void ) +{ +const unsigned portLONG ulCompareMatch = (configPERIPHERAL_CLOCK_HZ / portTIMER_PRESCALE) / configTICK_RATE_HZ; + + OpenTimer1( ( T1_ON | T1_PS_1_8 | T1_SOURCE_INT ), ulCompareMatch ); + ConfigIntTimer1( T1_INT_ON | configKERNEL_INTERRUPT_PRIORITY ); +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler(void) +{ + /* It is unlikely that the scheduler for the PIC port will get stopped + once running. If required disable the tick interrupt here, then return + to xPortStartScheduler(). */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical(void) +{ +unsigned portLONG ulStatus; + + /* Mask interrupts at and below the kernel interrupt priority. */ + ulStatus = _CP0_GET_STATUS(); + ulStatus |= ( configKERNEL_INTERRUPT_PRIORITY << portIPL_SHIFT ); + _CP0_SET_STATUS( ulStatus ); + + /* Once interrupts are disabled we can access the nesting count directly. */ + uxCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical(void) +{ +unsigned portLONG ulStatus; + + /* If we are in a critical section then we can access the nesting count + directly. */ + uxCriticalNesting--; + + /* Has the nesting unwound? */ + if( uxCriticalNesting == 0 ) + { + /* Unmask all interrupts. */ + ulStatus = _CP0_GET_STATUS(); + ulStatus &= ~portALL_IPL_BITS; + _CP0_SET_STATUS( ulStatus ); + } +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xPortStartScheduler( void ) +{ +extern void vPortStartFirstTask( void ); + + /* Setup the timer to generate the tick. Interrupts will have been + disabled by the time we get here. */ + prvSetupTimerInterrupt(); + + /* Kick off the highest priority task that has been created so far. */ + vPortStartFirstTask(); + + /* Should never get here as the tasks will now be executing. */ + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +void vApplicationGeneralExceptionHandler( unsigned portLONG ulCause, unsigned portLONG ulStatus ) +{ + /* This function is declared weak and should be overridden by the users + application. */ + while( 1 ); +} + + + + + diff --git a/20080212/Source/portable/MPLAB/PIC32MX/port_asm.S b/20080212/Source/portable/MPLAB/PIC32MX/port_asm.S new file mode 100644 index 000000000..670a7b0a4 --- /dev/null +++ b/20080212/Source/portable/MPLAB/PIC32MX/port_asm.S @@ -0,0 +1,163 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#include +#include +#include "ISR_Support.h" + +#define portEXC_CODE_MASK ( 0x1f << 2 ) + + .set nomips16 + .set noreorder + + .extern pxCurrentTCB + .extern uxCriticalNesting + .extern vTaskSwitchContext + .extern vTaskIncrementTick + .extern vApplicationGeneralExceptionHandler + .extern xISRStackTop + + .global vPortStartFirstTask + .global _general_exception_context + .global vT1InterruptHandler + + +/******************************************************************/ + + .section .FreeRTOS, "ax", @progbits + .set noreorder + .set noat + .ent vT1InterruptHandler + +vT1InterruptHandler: + + portSAVE_CONTEXT + + jal vTaskIncrementTick + nop + + /* If we are using the preemptive scheduler then we might want to select + a different task to execute. */ + #if configUSE_PREEMPTION == 1 + jal vTaskSwitchContext + nop + #endif /* configUSE_PREEMPTION */ + + /* Clear timer 0 interrupt. */ + la s1, IFS0CLR + addiu s0,zero,_IFS0_T1IF_MASK + sw s0, 0(s1) + + portRESTORE_CONTEXT + + .end vT1InterruptHandler + +/******************************************************************/ + + .section .FreeRTOS, "ax", @progbits + .set noreorder + .set noat + .ent xPortStartScheduler + +vPortStartFirstTask: + + /* Simply restore the context of the highest priority task that has been + created so far. */ + portRESTORE_CONTEXT + + .end xPortStartScheduler + +/*******************************************************************/ + + .section .FreeRTOS, "ax", @progbits + .set noreorder + .set noat + .ent _general_exception_context + +_general_exception_context: + + /* Save the context of the current task. */ + portSAVE_CONTEXT + + /* Was this handler caused by a syscall? The original Cause + value was saved to the stack as it could change as interrupts + nest. Use of k registers must be protected from use by nesting + interrupts. */ + lw s7, portCAUSE_STACK_LOCATION(s5) + andi s7, s7, portEXC_CODE_MASK + addi s7, s7, -( _EXCCODE_SYS << 2 ) + + /* Yes - call the SYSCALL handler to select a new task to execute. */ + beq s7, zero, SyscallHandler + nop + + /* No - call the application handler to handle all other types of + exception. Pass the status and cause to the application provided + handler. Interrupts are disabled during the execution of the user + defined handler. */ + di + lw a1, portSTATUS_STACK_LOCATION(s5) + lw a0, portCAUSE_STACK_LOCATION(s5) + jal vApplicationGeneralExceptionHandler + nop + ei + beq zero, zero, FinishExceptionHandler + nop + +SyscallHandler: + + /* Adjust the return that was placed onto the stack to be the + address of the instruction following the syscall. s6 already + contains the EPC value. */ + addi s6, 4 + sw s6, portEPC_STACK_LOCATION(s5) + + jal vTaskSwitchContext + nop + +FinishExceptionHandler: + portRESTORE_CONTEXT + + .end _general_exception_context + + + diff --git a/20080212/Source/portable/MPLAB/PIC32MX/portmacro.h b/20080212/Source/portable/MPLAB/PIC32MX/portmacro.h new file mode 100644 index 000000000..40eeabd65 --- /dev/null +++ b/20080212/Source/portable/MPLAB/PIC32MX/portmacro.h @@ -0,0 +1,117 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* System include files */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned long +#define portBASE_TYPE long + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 4 +#define portSTACK_GROWTH -4 +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +#define portDISABLE_INTERRUPTS() INTDisableInterrupts() +#define portENABLE_INTERRUPTS() INTEnableInterrupts() + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +#define portYIELD() asm volatile ( "ehb \r\n" \ + "SYSCALL \r\n" ) + +#define portNOP() asm volatile ( "nop" ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn)) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +/*-----------------------------------------------------------*/ + +#define portEND_SWITCHING_ISR( vSwitchRequired ) if( vSwitchRequired ) vTaskSwitchContext() + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/20080212/Source/portable/MemMang/heap_1.c b/20080212/Source/portable/MemMang/heap_1.c new file mode 100644 index 000000000..6a2394395 --- /dev/null +++ b/20080212/Source/portable/MemMang/heap_1.c @@ -0,0 +1,147 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + +Changes between V2.5.1 and V2.5.1 + + + The memory pool has been defined within a struct to ensure correct memory + alignment on 32bit systems. + +Changes between V2.6.1 and V3.0.0 + + + An overflow check has been added to ensure the next free byte variable + does not wrap around. +*/ + + +/* + * The simplest possible implementation of pvPortMalloc(). Note that this + * implementation does NOT allow allocated memory to be freed again. + * + * See heap_2.c and heap_3.c for alternative implementations, and the memory + * management pages of http://www.FreeRTOS.org for more information. + */ +#include +#include "FreeRTOS.h" +#include "task.h" + +/* Setup the correct byte alignment mask for the defined byte alignment. */ + +#if portBYTE_ALIGNMENT == 8 + #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0007 ) +#endif + +#if portBYTE_ALIGNMENT == 4 + #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0003 ) +#endif + +#if portBYTE_ALIGNMENT == 2 + #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0001 ) +#endif + +#if portBYTE_ALIGNMENT == 1 + #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0000 ) +#endif + +#ifndef heapBYTE_ALIGNMENT_MASK + #error "Invalid portBYTE_ALIGNMENT definition" +#endif + +/* Allocate the memory for the heap. The struct is used to force byte +alignment without using any non-portable code. */ +static struct xRTOS_HEAP +{ + unsigned portLONG ulDummy; + unsigned portCHAR ucHeap[ configTOTAL_HEAP_SIZE ]; +} xHeap; + +static size_t xNextFreeByte = ( size_t ) 0; +/*-----------------------------------------------------------*/ + +void *pvPortMalloc( size_t xWantedSize ) +{ +void *pvReturn = NULL; + + /* Ensure that blocks are always aligned to the required number of bytes. */ + #if portBYTE_ALIGNMENT != 1 + if( xWantedSize & heapBYTE_ALIGNMENT_MASK ) + { + /* Byte alignment required. */ + xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & heapBYTE_ALIGNMENT_MASK ) ); + } + #endif + + vTaskSuspendAll(); + { + /* Check there is enough room left for the allocation. */ + if( ( ( xNextFreeByte + xWantedSize ) < configTOTAL_HEAP_SIZE ) && + ( ( xNextFreeByte + xWantedSize ) > xNextFreeByte ) )/* Check for overflow. */ + { + /* Return the next free byte then increment the index past this + block. */ + pvReturn = &( xHeap.ucHeap[ xNextFreeByte ] ); + xNextFreeByte += xWantedSize; + } + } + xTaskResumeAll(); + + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void *pv ) +{ + /* Memory cannot be freed using this scheme. See heap_2.c and heap_3.c + for alternative implementations, and the memory management pages of + http://www.FreeRTOS.org for more information. */ + ( void ) pv; +} +/*-----------------------------------------------------------*/ + +void vPortInitialiseBlocks( void ) +{ + /* Only required when static memory is not cleared. */ + xNextFreeByte = ( size_t ) 0; +} + + diff --git a/20080212/Source/portable/MemMang/heap_2.c b/20080212/Source/portable/MemMang/heap_2.c new file mode 100644 index 000000000..20e5b82c8 --- /dev/null +++ b/20080212/Source/portable/MemMang/heap_2.c @@ -0,0 +1,251 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + * A sample implementation of pvPortMalloc() and vPortFree() that permits + * allocated blocks to be freed, but does not combine adjacent free blocks + * into a single larger block. + * + * See heap_1.c and heap_3.c for alternative implementations, and the memory + * management pages of http://www.FreeRTOS.org for more information. + */ +#include + +#include "FreeRTOS.h" +#include "task.h" + +/* Setup the correct byte alignment mask for the defined byte alignment. */ + +#if portBYTE_ALIGNMENT == 8 + #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0007 ) +#endif + +#if portBYTE_ALIGNMENT == 4 + #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0003 ) +#endif + +#if portBYTE_ALIGNMENT == 2 + #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0001 ) +#endif + +#if portBYTE_ALIGNMENT == 1 + #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0000 ) +#endif + +#ifndef heapBYTE_ALIGNMENT_MASK + #error "Invalid portBYTE_ALIGNMENT definition" +#endif + +/* Allocate the memory for the heap. The struct is used to force byte +alignment without using any non-portable code. */ +static struct xRTOS_HEAP +{ + unsigned portLONG ulDummy; + unsigned portCHAR ucHeap[ configTOTAL_HEAP_SIZE ]; +} xHeap; + +/* Define the linked list structure. This is used to link free blocks in order +of their size. */ +typedef struct A_BLOCK_LINK +{ + struct A_BLOCK_LINK *pxNextFreeBlock; /*<< The next free block in the list. */ + size_t xBlockSize; /*<< The size of the free block. */ +} xBlockLink; + + +static const unsigned portSHORT heapSTRUCT_SIZE = ( sizeof( xBlockLink ) + ( sizeof( xBlockLink ) % portBYTE_ALIGNMENT ) ); +#define heapMINIMUM_BLOCK_SIZE ( ( size_t ) ( heapSTRUCT_SIZE * 2 ) ) + +/* Create a couple of list links to mark the start and end of the list. */ +static xBlockLink xStart, xEnd; + +/* STATIC FUNCTIONS ARE DEFINED AS MACROS TO MINIMIZE THE FUNCTION CALL DEPTH. */ + +/* + * Insert a block into the list of free blocks - which is ordered by size of + * the block. Small blocks at the start of the list and large blocks at the end + * of the list. + */ +#define prvInsertBlockIntoFreeList( pxBlockToInsert ) \ +{ \ +xBlockLink *pxIterator; \ +size_t xBlockSize; \ + \ + xBlockSize = pxBlockToInsert->xBlockSize; \ + \ + /* Iterate through the list until a block is found that has a larger size */ \ + /* than the block we are inserting. */ \ + for( pxIterator = &xStart; pxIterator->pxNextFreeBlock->xBlockSize < xBlockSize; pxIterator = pxIterator->pxNextFreeBlock ) \ + { \ + /* There is nothing to do here - just iterate to the correct position. */ \ + } \ + \ + /* Update the list to include the block being inserted in the correct */ \ + /* position. */ \ + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; \ + pxIterator->pxNextFreeBlock = pxBlockToInsert; \ +} +/*-----------------------------------------------------------*/ + +#define prvHeapInit() \ +{ \ +xBlockLink *pxFirstFreeBlock; \ + \ + /* xStart is used to hold a pointer to the first item in the list of free */ \ + /* blocks. The void cast is used to prevent compiler warnings. */ \ + xStart.pxNextFreeBlock = ( void * ) xHeap.ucHeap; \ + xStart.xBlockSize = ( size_t ) 0; \ + \ + /* xEnd is used to mark the end of the list of free blocks. */ \ + xEnd.xBlockSize = configTOTAL_HEAP_SIZE; \ + xEnd.pxNextFreeBlock = NULL; \ + \ + /* To start with there is a single free block that is sized to take up the \ + entire heap space. */ \ + pxFirstFreeBlock = ( void * ) xHeap.ucHeap; \ + pxFirstFreeBlock->xBlockSize = configTOTAL_HEAP_SIZE; \ + pxFirstFreeBlock->pxNextFreeBlock = &xEnd; \ +} +/*-----------------------------------------------------------*/ + +void *pvPortMalloc( size_t xWantedSize ) +{ +xBlockLink *pxBlock, *pxPreviousBlock, *pxNewBlockLink; +static portBASE_TYPE xHeapHasBeenInitialised = pdFALSE; +void *pvReturn = NULL; + + vTaskSuspendAll(); + { + /* If this is the first call to malloc then the heap will require + initialisation to setup the list of free blocks. */ + if( xHeapHasBeenInitialised == pdFALSE ) + { + prvHeapInit(); + xHeapHasBeenInitialised = pdTRUE; + } + + /* The wanted size is increased so it can contain a xBlockLink + structure in addition to the requested amount of bytes. */ + if( xWantedSize > 0 ) + { + xWantedSize += heapSTRUCT_SIZE; + + /* Ensure that blocks are always aligned to the required number of bytes. */ + if( xWantedSize & heapBYTE_ALIGNMENT_MASK ) + { + /* Byte alignment required. */ + xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & heapBYTE_ALIGNMENT_MASK ) ); + } + } + + if( ( xWantedSize > 0 ) && ( xWantedSize < configTOTAL_HEAP_SIZE ) ) + { + /* Blocks are stored in byte order - traverse the list from the start + (smallest) block until one of adequate size is found. */ + pxPreviousBlock = &xStart; + pxBlock = xStart.pxNextFreeBlock; + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock ) ) + { + pxPreviousBlock = pxBlock; + pxBlock = pxBlock->pxNextFreeBlock; + } + + /* If we found the end marker then a block of adequate size was not found. */ + if( pxBlock != &xEnd ) + { + /* Return the memory space - jumping over the xBlockLink structure + at its start. */ + pvReturn = ( void * ) ( ( ( unsigned portCHAR * ) pxPreviousBlock->pxNextFreeBlock ) + heapSTRUCT_SIZE ); + + /* This block is being returned for use so must be taken our of the + list of free blocks. */ + pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; + + /* If the block is larger than required it can be split into two. */ + if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE ) + { + /* This block is to be split into two. Create a new block + following the number of bytes requested. The void cast is + used to prevent byte alignment warnings from the compiler. */ + pxNewBlockLink = ( void * ) ( ( ( unsigned portCHAR * ) pxBlock ) + xWantedSize ); + + /* Calculate the sizes of two blocks split from the single + block. */ + pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; + pxBlock->xBlockSize = xWantedSize; + + /* Insert the new block into the list of free blocks. */ + prvInsertBlockIntoFreeList( ( pxNewBlockLink ) ); + } + } + } + } + xTaskResumeAll(); + + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void *pv ) +{ +unsigned portCHAR *puc = ( unsigned portCHAR * ) pv; +xBlockLink *pxLink; + + if( pv ) + { + /* The memory being freed will have an xBlockLink structure immediately + before it. */ + puc -= heapSTRUCT_SIZE; + + /* This casting is to keep the compiler from issuing warnings. */ + pxLink = ( void * ) puc; + + vTaskSuspendAll(); + { + /* Add this block to the list of free blocks. */ + prvInsertBlockIntoFreeList( ( ( xBlockLink * ) pxLink ) ); + } + xTaskResumeAll(); + } +} +/*-----------------------------------------------------------*/ + diff --git a/20080212/Source/portable/MemMang/heap_3.c b/20080212/Source/portable/MemMang/heap_3.c new file mode 100644 index 000000000..a8fb535c8 --- /dev/null +++ b/20080212/Source/portable/MemMang/heap_3.c @@ -0,0 +1,89 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +/* + * Implementation of pvPortMalloc() and vPortFree() that relies on the + * compilers own malloc() and free() implementations. + * + * This file can only be used if the linker is configured to to generate + * a heap memory area. + * + * See heap_2.c and heap_1.c for alternative implementations, and the memory + * management pages of http://www.FreeRTOS.org for more information. + */ + +#include + +#include "FreeRTOS.h" +#include "task.h" + +/*-----------------------------------------------------------*/ + +void *pvPortMalloc( size_t xWantedSize ) +{ +void *pvReturn; + + vTaskSuspendAll(); + { + pvReturn = malloc( xWantedSize ); + } + xTaskResumeAll(); + + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void *pv ) +{ + if( pv ) + { + vTaskSuspendAll(); + { + free( pv ); + } + xTaskResumeAll(); + } +} + + + diff --git a/20080212/Source/portable/Paradigm/Tern_EE/large_untested/port.c b/20080212/Source/portable/Paradigm/Tern_EE/large_untested/port.c new file mode 100644 index 000000000..0287426cc --- /dev/null +++ b/20080212/Source/portable/Paradigm/Tern_EE/large_untested/port.c @@ -0,0 +1,252 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the Tern EE 186 + * port. + *----------------------------------------------------------*/ + +/* Library includes. */ +#include +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "portasm.h" + +/* The timer increments every four clocks, hence the divide by 4. */ +#define portTIMER_COMPARE ( unsigned portSHORT ) ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) / ( unsigned portLONG ) 4 ) + +/* From the RDC data sheet. */ +#define portENABLE_TIMER_AND_INTERRUPT ( unsigned portSHORT ) 0xe001 + +/* Interrupt control. */ +#define portEIO_REGISTER 0xff22 +#define portCLEAR_INTERRUPT 0x0008 + +/* Setup the hardware to generate the required tick frequency. */ +static void prvSetupTimerInterrupt( void ); + +/* The ISR used depends on whether the preemptive or cooperative scheduler +is being used. */ +#if( configUSE_PREEMPTION == 1 ) + /* Tick service routine used by the scheduler when preemptive scheduling is + being used. */ + static void __interrupt __far prvPreemptiveTick( void ); +#else + /* Tick service routine used by the scheduler when cooperative scheduling is + being used. */ + static void __interrupt __far prvNonPreemptiveTick( void ); +#endif + +/* Trap routine used by taskYIELD() to manually cause a context switch. */ +static void __interrupt __far prvYieldProcessor( void ); + +/* The timer initialisation functions leave interrupts enabled, +which is not what we want. This ISR is installed temporarily in case +the timer fires before we get a change to disable interrupts again. */ +static void __interrupt __far prvDummyISR( void ); + +/*-----------------------------------------------------------*/ +/* See header file for description. */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ +portSTACK_TYPE DS_Reg = 0; + + /* Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging. */ + + *pxTopOfStack = 0x1111; + pxTopOfStack--; + *pxTopOfStack = 0x2222; + pxTopOfStack--; + *pxTopOfStack = 0x3333; + pxTopOfStack--; + + /* We are going to start the scheduler using a return from interrupt + instruction to load the program counter, so first there would be the + function call with parameters preamble. */ + + *pxTopOfStack = FP_SEG( pvParameters ); + pxTopOfStack--; + *pxTopOfStack = FP_OFF( pvParameters ); + pxTopOfStack--; + *pxTopOfStack = FP_SEG( pxCode ); + pxTopOfStack--; + *pxTopOfStack = FP_OFF( pxCode ); + pxTopOfStack--; + + /* Next the status register and interrupt return address. */ + *pxTopOfStack = portINITIAL_SW; + pxTopOfStack--; + *pxTopOfStack = FP_SEG( pxCode ); + pxTopOfStack--; + *pxTopOfStack = FP_OFF( pxCode ); + pxTopOfStack--; + + /* The remaining registers would be pushed on the stack by our context + switch function. These are loaded with values simply to make debugging + easier. */ + *pxTopOfStack = ( portSTACK_TYPE ) 0xAAAA; /* AX */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xBBBB; /* BX */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xCCCC; /* CX */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xDDDD; /* DX */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xEEEE; /* ES */ + pxTopOfStack--; + + /* We need the true data segment. */ + __asm{ MOV DS_Reg, DS }; + + *pxTopOfStack = DS_Reg; /* DS */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x0123; /* SI */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xDDDD; /* DI */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xBBBB; /* BP */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xPortStartScheduler( void ) +{ + /* This is called with interrupts already disabled. */ + + /* Put our manual switch (yield) function on a known + vector. */ + setvect( portSWITCH_INT_NUMBER, prvYieldProcessor ); + + /* Setup the tick interrupt. */ + prvSetupTimerInterrupt(); + + /* Kick off the scheduler by setting up the context of the first task. */ + portFIRST_CONTEXT(); + + /* Should not get here! */ + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +static void __interrupt __far prvDummyISR( void ) +{ + /* The timer initialisation functions leave interrupts enabled, + which is not what we want. This ISR is installed temporarily in case + the timer fires before we get a change to disable interrupts again. */ + outport( portEIO_REGISTER, portCLEAR_INTERRUPT ); +} +/*-----------------------------------------------------------*/ + +/* The ISR used depends on whether the preemptive or cooperative scheduler +is being used. */ +#if( configUSE_PREEMPTION == 1 ) + static void __interrupt __far prvPreemptiveTick( void ) + { + /* Get the scheduler to update the task states following the tick. */ + vTaskIncrementTick(); + + /* Switch in the context of the next task to be run. */ + portSWITCH_CONTEXT(); + + /* Reset interrupt. */ + outport( portEIO_REGISTER, portCLEAR_INTERRUPT ); + } +#else + static void __interrupt __far prvNonPreemptiveTick( void ) + { + /* Same as preemptive tick, but the cooperative scheduler is being used + so we don't have to switch in the context of the next task. */ + vTaskIncrementTick(); + /* Reset interrupt. */ + outport( portEIO_REGISTER, portCLEAR_INTERRUPT ); + } +#endif +/*-----------------------------------------------------------*/ + +static void __interrupt __far prvYieldProcessor( void ) +{ + /* Switch in the context of the next task to be run. */ + portSWITCH_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented. */ +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ +const unsigned portSHORT usTimerACompare = portTIMER_COMPARE, usTimerAMode = portENABLE_TIMER_AND_INTERRUPT; +const unsigned portSHORT usT2_IRQ = 0x13; + + /* Configure the timer, the dummy handler is used here as the init + function leaves interrupts enabled. */ + t2_init( usTimerAMode, usTimerACompare, prvDummyISR ); + + /* Disable interrupts again before installing the real handlers. */ + portDISABLE_INTERRUPTS(); + + #if( configUSE_PREEMPTION == 1 ) + /* Tick service routine used by the scheduler when preemptive scheduling is + being used. */ + setvect( usT2_IRQ, prvPreemptiveTick ); + #else + /* Tick service routine used by the scheduler when cooperative scheduling is + being used. */ + setvect( usT2_IRQ, prvNonPreemptiveTick ); + #endif +} + + + + + + + diff --git a/20080212/Source/portable/Paradigm/Tern_EE/large_untested/portasm.h b/20080212/Source/portable/Paradigm/Tern_EE/large_untested/portasm.h new file mode 100644 index 000000000..d6247a5b2 --- /dev/null +++ b/20080212/Source/portable/Paradigm/Tern_EE/large_untested/portasm.h @@ -0,0 +1,91 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +typedef void tskTCB; +extern volatile tskTCB * volatile pxCurrentTCB; +extern void vTaskSwitchContext( void ); + +/* + * Saves the stack pointer for one task into its TCB, calls + * vTaskSwitchContext() to update the TCB being used, then restores the stack + * from the new TCB read to run the task. + */ +void portSWITCH_CONTEXT( void ); + +/* + * Load the stack pointer from the TCB of the task which is going to be first + * to execute. Then force an IRET so the registers and IP are popped off the + * stack. + */ +void portFIRST_CONTEXT( void ); + +#define portSWITCH_CONTEXT() \ + asm { mov ax, seg pxCurrentTCB } \ + asm { mov ds, ax } \ + asm { les bx, pxCurrentTCB } /* Save the stack pointer into the TCB. */ \ + asm { mov es:0x2[ bx ], ss } \ + asm { mov es:[ bx ], sp } \ + asm { call far ptr vTaskSwitchContext } /* Perform the switch. */ \ + asm { mov ax, seg pxCurrentTCB } /* Restore the stack pointer from the TCB. */ \ + asm { mov ds, ax } \ + asm { les bx, dword ptr pxCurrentTCB } \ + asm { mov ss, es:[ bx + 2 ] } \ + asm { mov sp, es:[ bx ] } + +#define portFIRST_CONTEXT() \ + asm { mov ax, seg pxCurrentTCB } \ + asm { mov ds, ax } \ + asm { les bx, dword ptr pxCurrentTCB } \ + asm { mov ss, es:[ bx + 2 ] } \ + asm { mov sp, es:[ bx ] } \ + asm { pop bp } \ + asm { pop di } \ + asm { pop si } \ + asm { pop ds } \ + asm { pop es } \ + asm { pop dx } \ + asm { pop cx } \ + asm { pop bx } \ + asm { pop ax } \ + asm { iret } + + diff --git a/20080212/Source/portable/Paradigm/Tern_EE/large_untested/portmacro.h b/20080212/Source/portable/Paradigm/Tern_EE/large_untested/portmacro.h new file mode 100644 index 000000000..8bf705803 --- /dev/null +++ b/20080212/Source/portable/Paradigm/Tern_EE/large_untested/portmacro.h @@ -0,0 +1,117 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE long +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE unsigned portSHORT +#define portBASE_TYPE portSHORT + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +#define portENTER_CRITICAL() __asm{ pushf } \ + __asm{ cli } \ + +#define portEXIT_CRITICAL() __asm{ popf } + +#define portDISABLE_INTERRUPTS() __asm{ cli } + +#define portENABLE_INTERRUPTS() __asm{ sti } +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portNOP() __asm{ nop } +#define portSTACK_GROWTH ( -1 ) +#define portSWITCH_INT_NUMBER 0x80 +#define portYIELD() __asm{ int portSWITCH_INT_NUMBER } +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 2 +#define portINITIAL_SW ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */ +/*-----------------------------------------------------------*/ + +/* Compiler specifics. */ +#define portINPUT_BYTE( xAddr ) inp( xAddr ) +#define portOUTPUT_BYTE( xAddr, ucValue ) outp( xAddr, ucValue ) +#define portINPUT_WORD( xAddr ) inpw( xAddr ) +#define portOUTPUT_WORD( xAddr, usValue ) outpw( xAddr, usValue ) +#define inline +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters ) +#define portTASK_FUNCTION( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif + + +#endif /* PORTMACRO_H */ + diff --git a/20080212/Source/portable/Paradigm/Tern_EE/small/port.c b/20080212/Source/portable/Paradigm/Tern_EE/small/port.c new file mode 100644 index 000000000..c5f7f27d7 --- /dev/null +++ b/20080212/Source/portable/Paradigm/Tern_EE/small/port.c @@ -0,0 +1,232 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the Tern EE 186 + * port. + *----------------------------------------------------------*/ + +/* Library includes. */ +#include +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "portasm.h" + +/* The timer increments every four clocks, hence the divide by 4. */ +#define portPRESCALE_VALUE ( 16 ) +#define portTIMER_COMPARE ( configCPU_CLOCK_HZ / ( configTICK_RATE_HZ * 4UL ) ) + +/* From the RDC data sheet. */ +#define portENABLE_TIMER_AND_INTERRUPT ( unsigned portSHORT ) 0xe00b +#define portENABLE_TIMER ( unsigned portSHORT ) 0xC001 + +/* Interrupt control. */ +#define portEIO_REGISTER 0xff22 +#define portCLEAR_INTERRUPT 0x0008 + +/* Setup the hardware to generate the required tick frequency. */ +static void prvSetupTimerInterrupt( void ); + +/* The ISR used depends on whether the preemptive or cooperative scheduler +is being used. */ +#if( configUSE_PREEMPTION == 1 ) + /* Tick service routine used by the scheduler when preemptive scheduling is + being used. */ + static void __interrupt __far prvPreemptiveTick( void ); +#else + /* Tick service routine used by the scheduler when cooperative scheduling is + being used. */ + static void __interrupt __far prvNonPreemptiveTick( void ); +#endif + +/* Trap routine used by taskYIELD() to manually cause a context switch. */ +static void __interrupt __far prvYieldProcessor( void ); + +/*-----------------------------------------------------------*/ +/* See header file for description. */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ +portSTACK_TYPE DS_Reg = 0; + + /* We need the true data segment. */ + __asm{ MOV DS_Reg, DS }; + + /* Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging. */ + + *pxTopOfStack = 0x1111; + pxTopOfStack--; + *pxTopOfStack = 0x2222; + pxTopOfStack--; + *pxTopOfStack = 0x3333; + pxTopOfStack--; + + /* We are going to start the scheduler using a return from interrupt + instruction to load the program counter, so first there would be the + function call with parameters preamble. */ + + *pxTopOfStack = FP_OFF( pvParameters ); + pxTopOfStack--; + *pxTopOfStack = FP_OFF( pxCode ); + pxTopOfStack--; + + /* Next the status register and interrupt return address. */ + *pxTopOfStack = portINITIAL_SW; + pxTopOfStack--; + *pxTopOfStack = FP_SEG( pxCode ); + pxTopOfStack--; + *pxTopOfStack = FP_OFF( pxCode ); + pxTopOfStack--; + + /* The remaining registers would be pushed on the stack by our context + switch function. These are loaded with values simply to make debugging + easier. */ + *pxTopOfStack = ( portSTACK_TYPE ) 0xAAAA; /* AX */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xBBBB; /* BX */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xCCCC; /* CX */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xDDDD; /* DX */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xEEEE; /* ES */ + pxTopOfStack--; + + *pxTopOfStack = DS_Reg; /* DS */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x0123; /* SI */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xDDDD; /* DI */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xBBBB; /* BP */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xPortStartScheduler( void ) +{ + /* This is called with interrupts already disabled. */ + + /* Put our manual switch (yield) function on a known + vector. */ + setvect( portSWITCH_INT_NUMBER, prvYieldProcessor ); + + /* Setup the tick interrupt. */ + prvSetupTimerInterrupt(); + + /* Kick off the scheduler by setting up the context of the first task. */ + portFIRST_CONTEXT(); + + /* Should not get here! */ + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +/* The ISR used depends on whether the preemptive or cooperative scheduler +is being used. */ +#if( configUSE_PREEMPTION == 1 ) + static void __interrupt __far prvPreemptiveTick( void ) + { + /* Get the scheduler to update the task states following the tick. */ + vTaskIncrementTick(); + + /* Switch in the context of the next task to be run. */ + portEND_SWITCHING_ISR(); + + /* Reset interrupt. */ + outport( portEIO_REGISTER, portCLEAR_INTERRUPT ); + } +#else + static void __interrupt __far prvNonPreemptiveTick( void ) + { + /* Same as preemptive tick, but the cooperative scheduler is being used + so we don't have to switch in the context of the next task. */ + vTaskIncrementTick(); + /* Reset interrupt. */ + outport( portEIO_REGISTER, portCLEAR_INTERRUPT ); + } +#endif +/*-----------------------------------------------------------*/ + +static void __interrupt __far prvYieldProcessor( void ) +{ + /* Switch in the context of the next task to be run. */ + portEND_SWITCHING_ISR(); +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented. */ +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ +const unsigned portLONG ulCompareValue = portTIMER_COMPARE; +unsigned portSHORT usTimerCompare; + + usTimerCompare = ( unsigned portSHORT ) ( ulCompareValue >> 4 ); + t2_init( portENABLE_TIMER, portPRESCALE_VALUE, NULL ); + + #if( configUSE_PREEMPTION == 1 ) + /* Tick service routine used by the scheduler when preemptive scheduling is + being used. */ + t1_init( portENABLE_TIMER_AND_INTERRUPT, usTimerCompare, usTimerCompare, prvPreemptiveTick ); + #else + /* Tick service routine used by the scheduler when cooperative scheduling is + being used. */ + t1_init( portENABLE_TIMER_AND_INTERRUPT, usTimerCompare, usTimerCompare, prvNonPreemptiveTick ); + #endif +} + + + + + + + diff --git a/20080212/Source/portable/Paradigm/Tern_EE/small/portasm.h b/20080212/Source/portable/Paradigm/Tern_EE/small/portasm.h new file mode 100644 index 000000000..98ce1735f --- /dev/null +++ b/20080212/Source/portable/Paradigm/Tern_EE/small/portasm.h @@ -0,0 +1,87 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef PORT_ASM_H +#define PORT_ASM_H + +typedef void tskTCB; +extern volatile tskTCB * volatile pxCurrentTCB; +extern void vTaskSwitchContext( void ); + +/* + * Saves the stack pointer for one task into its TCB, calls + * vTaskSwitchContext() to update the TCB being used, then restores the stack + * from the new TCB read to run the task. + */ +void portEND_SWITCHING_ISR( void ); + +/* + * Load the stack pointer from the TCB of the task which is going to be first + * to execute. Then force an IRET so the registers and IP are popped off the + * stack. + */ +void portFIRST_CONTEXT( void ); + +#define portEND_SWITCHING_ISR() \ + asm { mov bx, [pxCurrentTCB] } \ + asm { mov word ptr [bx], sp } \ + asm { call far ptr vTaskSwitchContext } \ + asm { mov bx, [pxCurrentTCB] } \ + asm { mov sp, [bx] } + +#define portFIRST_CONTEXT() \ + asm { mov bx, [pxCurrentTCB] } \ + asm { mov sp, [bx] } \ + asm { pop bp } \ + asm { pop di } \ + asm { pop si } \ + asm { pop ds } \ + asm { pop es } \ + asm { pop dx } \ + asm { pop cx } \ + asm { pop bx } \ + asm { pop ax } \ + asm { iret } + + +#endif + diff --git a/20080212/Source/portable/Paradigm/Tern_EE/small/portmacro.h b/20080212/Source/portable/Paradigm/Tern_EE/small/portmacro.h new file mode 100644 index 000000000..ecad7c4a5 --- /dev/null +++ b/20080212/Source/portable/Paradigm/Tern_EE/small/portmacro.h @@ -0,0 +1,118 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE long +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE unsigned portSHORT +#define portBASE_TYPE portSHORT + +typedef void ( __interrupt __far *pxISR )(); + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +#define portENTER_CRITICAL() __asm{ pushf } \ + __asm{ cli } \ + +#define portEXIT_CRITICAL() __asm{ popf } + +#define portDISABLE_INTERRUPTS() __asm{ cli } + +#define portENABLE_INTERRUPTS() __asm{ sti } +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portNOP() __asm{ nop } +#define portSTACK_GROWTH ( -1 ) +#define portSWITCH_INT_NUMBER 0x80 +#define portYIELD() __asm{ int portSWITCH_INT_NUMBER } +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 2 +#define portINITIAL_SW ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */ +/*-----------------------------------------------------------*/ + +/* Compiler specifics. */ +#define portINPUT_BYTE( xAddr ) inp( xAddr ) +#define portOUTPUT_BYTE( xAddr, ucValue ) outp( xAddr, ucValue ) +#define portINPUT_WORD( xAddr ) inpw( xAddr ) +#define portOUTPUT_WORD( xAddr, usValue ) outpw( xAddr, usValue ) +#define inline +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters ) +#define portTASK_FUNCTION( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/20080212/Source/portable/RVDS/ARM_CM3/port.c b/20080212/Source/portable/RVDS/ARM_CM3/port.c new file mode 100644 index 000000000..3832190c7 --- /dev/null +++ b/20080212/Source/portable/RVDS/ARM_CM3/port.c @@ -0,0 +1,309 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* + Changes between V4.0.0 and V4.0.1 + + + Reduced the code used to setup the initial stack frame. + + The kernel no longer has to install or handle the fault interrupt. +*/ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the ARM CM3 port. + *----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to manipulate the NVIC. */ +#define portNVIC_SYSTICK_CTRL ( ( volatile unsigned portLONG *) 0xe000e010 ) +#define portNVIC_SYSTICK_LOAD ( ( volatile unsigned portLONG *) 0xe000e014 ) +#define portNVIC_INT_CTRL ( ( volatile unsigned portLONG *) 0xe000ed04 ) +#define portNVIC_SYSPRI2 ( ( volatile unsigned portLONG *) 0xe000ed20 ) +#define portNVIC_SYSPRI1 ( ( volatile unsigned portLONG *) 0xe000ed1c ) +#define portNVIC_HARD_FAULT_STATUS 0xe000ed2c +#define portNVIC_FORCED_FAULT_BIT 0x40000000 +#define portNVIC_SYSTICK_CLK 0x00000004 +#define portNVIC_SYSTICK_INT 0x00000002 +#define portNVIC_SYSTICK_ENABLE 0x00000001 +#define portNVIC_PENDSVSET 0x10000000 +#define portNVIC_PENDSV_PRI 0x00ff0000 +#define portNVIC_SVCALL_PRI 0xff000000 +#define portNVIC_SYSTICK_PRI 0xff000000 + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000 ) + +/* Each task maintains its own interrupt status in the critical nesting +variable. */ +unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa; + +/* Constant hardware definitions to assist asm code. */ +const unsigned long ulHardFaultStatus = portNVIC_HARD_FAULT_STATUS; +const unsigned long ulNVICIntCtrl = ( unsigned long ) 0xe000ed04; +const unsigned long ulForceFaultBit = portNVIC_FORCED_FAULT_BIT; +const unsigned long ulPendSVBit = portNVIC_PENDSVSET; + +/* + * Setup the timer to generate the tick interrupts. + */ +static void prvSetupTimerInterrupt( void ); + +/* + * Set the MSP/PSP to a known value. + */ +void prvSetMSP( unsigned long ulValue ); +void prvSetPSP( unsigned long ulValue ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ + /* Simulate the stack frame as it would be created by a context switch + interrupt. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = 0xfffffffd; /* LR */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ + pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ + *pxTopOfStack = 0x00000000; /* uxCriticalNesting. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +__asm void prvSetPSP( unsigned long ulValue ) +{ + PRESERVE8 + msr psp, r0 + bx lr; +} +/*-----------------------------------------------------------*/ + +__asm void prvSetMSP( unsigned long ulValue ) +{ + PRESERVE8 + msr msp, r0 + bx lr; +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +portBASE_TYPE xPortStartScheduler( void ) +{ + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + prvSetupTimerInterrupt(); + + /* Make PendSV, CallSV and SysTick the lowest priority interrupts. */ + *(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI; + *(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI; + *(portNVIC_SYSPRI1) |= portNVIC_SVCALL_PRI; + + /* Start the first task. */ + prvSetPSP( 0 ); + prvSetMSP( *((unsigned portLONG *) 0 ) ); + *(portNVIC_INT_CTRL) |= portNVIC_PENDSVSET; + + /* Enable interrupts */ + portENABLE_INTERRUPTS(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the CM3 port will require this function as there + is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +void vPortYieldFromISR( void ) +{ + /* Set a PendSV to request a context switch. */ + *(portNVIC_INT_CTRL) |= portNVIC_PENDSVSET; + portENABLE_INTERRUPTS(); +} +/*-----------------------------------------------------------*/ + +__asm void vPortDisableInterrupts( void ) +{ + PRESERVE8 + cpsid i; + bx lr; +} +/*-----------------------------------------------------------*/ + +__asm void vPortEnableInterrupts( void ) +{ + PRESERVE8 + cpsie i; + bx lr; +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + vPortDisableInterrupts(); + uxCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + uxCriticalNesting--; + if( uxCriticalNesting == 0 ) + { + vPortEnableInterrupts(); + } +} +/*-----------------------------------------------------------*/ + +__asm void xPortPendSVHandler( void ) +{ + extern uxCriticalNesting; + extern pxCurrentTCB; + extern vTaskSwitchContext; + + PRESERVE8 + + /* Start first task if the stack has not yet been setup. */ + mrs r0, psp + cbz r0, no_save + + /* Save the context into the TCB. */ + stmdb r0!, {r4-r11} + sub r0, r0, #0x04 + ldr r1, =uxCriticalNesting + ldr r2, =pxCurrentTCB + ldr r1, [r1] + ldr r2, [r2] + str r1, [r0] + str r0, [r2] + +no_save; + + /* Find the task to execute. */ + push {r14} + cpsid i + bl vTaskSwitchContext + cpsie i + pop {r14} + + /* Restore the context. */ + ldr r1, =pxCurrentTCB + ldr r1, [r1]; + ldr r0, [r1]; + ldmia r0!, {r1, r4-r11} + ldr r2, =uxCriticalNesting + str r1, [r2] + ldr r2, [r2] + msr psp, r0 + orr r14, #0xd + + /* Exit with interrupts in the state required by the task. */ + cbnz r2, sv_disable_interrupts + + bx r14 + +sv_disable_interrupts; + cpsid i + bx r14 +} +/*-----------------------------------------------------------*/ + +__asm void xPortSysTickHandler( void ) +{ + extern vTaskIncrementTick + PRESERVE8 + + /* Call the scheduler tick function. */ + push {r14} + cpsid i + bl vTaskIncrementTick + cpsie i + pop {r14} + + /* If using preemption, also force a context switch. */ + #if configUSE_PREEMPTION == 1 + extern vPortYieldFromISR + push {r14} + bl vPortYieldFromISR + pop {r14} + #endif + + /* Exit with interrupts in the correct state. */ + ldr r2, =uxCriticalNesting + ldr r2, [r2] + cbnz r2, tick_disable_interrupts + + bx r14 + +tick_disable_interrupts; + cpsid i + bx r14 +} +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +void prvSetupTimerInterrupt( void ) +{ + /* Configure SysTick to interrupt at the requested rate. */ + *(portNVIC_SYSTICK_LOAD) = configCPU_CLOCK_HZ / configTICK_RATE_HZ; + *(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE; +} + + diff --git a/20080212/Source/portable/RVDS/ARM_CM3/portmacro.h b/20080212/Source/portable/RVDS/ARM_CM3/portmacro.h new file mode 100644 index 000000000..32a191f44 --- /dev/null +++ b/20080212/Source/portable/RVDS/ARM_CM3/portmacro.h @@ -0,0 +1,120 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned portLONG +#define portBASE_TYPE long + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 4 +/*-----------------------------------------------------------*/ + + +/* Scheduler utilities. */ +extern void vPortYield( void ); +extern void vPortYieldFromISR( void ); + +#define portYIELD() vPortYieldFromISR() +#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vPortYieldFromISR() +/*-----------------------------------------------------------*/ + + +/* Critical section management. */ + +extern void vPortDisableInterrupts( void ); +extern void vPortEnableInterrupts( void ); +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#define portDISABLE_INTERRUPTS() vPortDisableInterrupts() +#define portENABLE_INTERRUPTS() vPortEnableInterrupts() +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#define inline +#define portNOP() + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/20080212/Source/portable/Rowley/ARM7/readme.txt b/20080212/Source/portable/Rowley/ARM7/readme.txt new file mode 100644 index 000000000..8d3e87f57 --- /dev/null +++ b/20080212/Source/portable/Rowley/ARM7/readme.txt @@ -0,0 +1 @@ +The Rowley ARM7 demo uses the GCC ARM7 port files. \ No newline at end of file diff --git a/20080212/Source/portable/Rowley/MSP430F449/Port1/port.c b/20080212/Source/portable/Rowley/MSP430F449/Port1/port.c new file mode 100644 index 000000000..6195dbe4b --- /dev/null +++ b/20080212/Source/portable/Rowley/MSP430F449/Port1/port.c @@ -0,0 +1,187 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the MSP430 port. + *----------------------------------------------------------*/ + +/* Constants required for hardware setup. The tick ISR runs off the ACLK, +not the MCLK. */ +#define portACLK_FREQUENCY_HZ ( ( portTickType ) 32768 ) +#define portINITIAL_CRITICAL_NESTING ( ( unsigned portSHORT ) 10 ) +#define portFLAGS_INT_ENABLED ( ( portSTACK_TYPE ) 0x08 ) + +/* We require the address of the pxCurrentTCB variable, but don't want to know +any details of its type. */ +typedef void tskTCB; +extern volatile tskTCB * volatile pxCurrentTCB; + +/* Each task maintains a count of the critical section nesting depth. Each +time a critical section is entered the count is incremented. Each time a +critical section is exited the count is decremented - with interrupts only +being re-enabled if the count is zero. + +usCriticalNesting will get set to zero when the scheduler starts, but must +not be initialised to zero as this will cause problems during the startup +sequence. */ +volatile unsigned portSHORT usCriticalNesting = portINITIAL_CRITICAL_NESTING; +/*-----------------------------------------------------------*/ + + +/* + * Sets up the periodic ISR used for the RTOS tick. This uses timer 0, but + * could have alternatively used the watchdog timer or timer 1. + */ +void prvSetupTimerInterrupt( void ); +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See the header file portable.h. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ + /* + Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging and can be included if required. + + *pxTopOfStack = ( portSTACK_TYPE ) 0x1111; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x2222; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x3333; + pxTopOfStack--; + */ + + /* The msp430 automatically pushes the PC then SR onto the stack before + executing an ISR. We want the stack to look just as if this has happened + so place a pointer to the start of the task on the stack first - followed + by the flags we want the task to use when it starts up. */ + *pxTopOfStack = ( portSTACK_TYPE ) pxCode; + pxTopOfStack--; + *pxTopOfStack = portFLAGS_INT_ENABLED; + pxTopOfStack--; + + /* Next the general purpose registers. */ + *pxTopOfStack = ( portSTACK_TYPE ) 0x4444; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x5555; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x6666; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x7777; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x8888; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x9999; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaa; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xbbbb; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xcccc; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xdddd; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xeeee; + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + R15. */ + *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; + pxTopOfStack--; + + /* A variable is used to keep track of the critical section nesting. + This variable has to be stored as part of the task context and is + initially set to zero. */ + *pxTopOfStack = ( portSTACK_TYPE ) portNO_CRITICAL_SECTION_NESTING; + + /* Return a pointer to the top of the stack we have generated so this can + be stored in the task control block for the task. */ + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the MSP430 port will get stopped. If required simply + disable the tick interrupt here. */ +} +/*-----------------------------------------------------------*/ + +/* + * Hardware initialisation to generate the RTOS tick. This uses timer 0 + * but could alternatively use the watchdog timer or timer 1. + */ +void prvSetupTimerInterrupt( void ) +{ + /* Ensure the timer is stopped. */ + TACTL = 0; + + /* Run the timer of the ACLK. */ + TACTL = TASSEL_1; + + /* Clear everything to start with. */ + TACTL |= TACLR; + + /* Set the compare match value according to the tick rate we want. */ + TACCR0 = portACLK_FREQUENCY_HZ / configTICK_RATE_HZ; + + /* Enable the interrupts. */ + TACCTL0 = CCIE; + + /* Start up clean. */ + TACTL |= TACLR; + + /* Up mode. */ + TACTL |= MC_1; +} +/*-----------------------------------------------------------*/ + + + diff --git a/20080212/Source/portable/Rowley/MSP430F449/Port1/portext.asm b/20080212/Source/portable/Rowley/MSP430F449/Port1/portext.asm new file mode 100644 index 000000000..4bf0aeb06 --- /dev/null +++ b/20080212/Source/portable/Rowley/MSP430F449/Port1/portext.asm @@ -0,0 +1,116 @@ +#include "FreeRTOSConfig.h" + +portSAVE_CONTEXT macro + push r4 + push r5 + push r6 + push r7 + push r8 + push r9 + push r10 + push r11 + push r12 + push r13 + push r14 + push r15 + mov.w &_usCriticalNesting, r14 + push r14 + mov.w &_pxCurrentTCB, r12 + mov.w r1, @r12 + endm +/*-----------------------------------------------------------*/ + +portRESTORE_CONTEXT macro + mov.w &_pxCurrentTCB, r12 + mov.w @r12, r1 + pop r15 + mov.w r15, &_usCriticalNesting + pop r15 + pop r14 + pop r13 + pop r12 + pop r11 + pop r10 + pop r9 + pop r8 + pop r7 + pop r6 + pop r5 + pop r4 + reti + endm +/*-----------------------------------------------------------*/ + + +.CODE + +/* + * The RTOS tick ISR. + * + * If the cooperative scheduler is in use this simply increments the tick + * count. + * + * If the preemptive scheduler is in use a context switch can also occur. + */ +_vTickISR: + portSAVE_CONTEXT + + call #_vTaskIncrementTick + + #if configUSE_PREEMPTION == 1 + call #_vTaskSwitchContext + #endif + + portRESTORE_CONTEXT +/*-----------------------------------------------------------*/ + + +/* + * Manual context switch called by the portYIELD() macro. + */ +_vPortYield:: + + /* Mimic an interrupt by pushing the SR. */ + push SR + + /* Now the SR is stacked we can disable interrupts. */ + dint + + /* Save the context of the current task. */ + portSAVE_CONTEXT + + /* Switch to the highest priority task that is ready to run. */ + call #_vTaskSwitchContext + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT +/*-----------------------------------------------------------*/ + + +/* + * Start off the scheduler by initialising the RTOS tick timer, then restoring + * the context of the first task. + */ +_xPortStartScheduler:: + + /* Setup the hardware to generate the tick. Interrupts are disabled + when this function is called. */ + call #_prvSetupTimerInterrupt + + /* Restore the context of the first task that is going to run. */ + portRESTORE_CONTEXT +/*-----------------------------------------------------------*/ + + + /* Place the tick ISR in the correct vector. */ + .VECTORS + + .KEEP + + ORG TIMERA0_VECTOR + DW _vTickISR + + + + END + diff --git a/20080212/Source/portable/Rowley/MSP430F449/Port1/portmacro.h b/20080212/Source/portable/Rowley/MSP430F449/Port1/portmacro.h new file mode 100644 index 000000000..675a50ed2 --- /dev/null +++ b/20080212/Source/portable/Rowley/MSP430F449/Port1/portmacro.h @@ -0,0 +1,144 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE unsigned portSHORT +#define portBASE_TYPE portSHORT + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif + +/*-----------------------------------------------------------*/ + +/* Interrupt control macros. */ +#define portDISABLE_INTERRUPTS() _DINT(); +#define portENABLE_INTERRUPTS() _EINT(); +/*-----------------------------------------------------------*/ + +/* Critical section control macros. */ +#define portNO_CRITICAL_SECTION_NESTING ( ( unsigned portSHORT ) 0 ) + +#define portENTER_CRITICAL() \ +{ \ +extern volatile unsigned portSHORT usCriticalNesting; \ + \ + portDISABLE_INTERRUPTS(); \ + \ + /* Now interrupts are disabled usCriticalNesting can be accessed */ \ + /* directly. Increment ulCriticalNesting to keep a count of how many */ \ + /* times portENTER_CRITICAL() has been called. */ \ + usCriticalNesting++; \ +} + +#define portEXIT_CRITICAL() \ +{ \ +extern volatile unsigned portSHORT usCriticalNesting; \ + \ + if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ + { \ + /* Decrement the nesting count as we are leaving a critical section. */ \ + usCriticalNesting--; \ + \ + /* If the nesting level has reached zero then interrupts should be */ \ + /* re-enabled. */ \ + if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ + } \ +} +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* + * Manual context switch called by portYIELD or taskYIELD. + */ +extern void vPortYield( void ); +#define portYIELD() vPortYield() +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 2 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) __toplevel + +/* Compiler specifics. */ +#define inline + +/* Just used by the demo application to indicate which form of interrupt +service routine should be used. See the online port documentation for more +information. */ +#define MSP_ROWLEY_RB_PORT + +#define portNOP() + +#endif /* PORTMACRO_H */ + diff --git a/20080212/Source/portable/Rowley/MSP430F449/Port2/port.c b/20080212/Source/portable/Rowley/MSP430F449/Port2/port.c new file mode 100644 index 000000000..a3ba656a0 --- /dev/null +++ b/20080212/Source/portable/Rowley/MSP430F449/Port2/port.c @@ -0,0 +1,231 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +/* + * Milos Prokic + * + * File adopted from the MSP430 GCC port + * Interrupt handling, xPortStartScheduler, vPortYield, portSAVE_CONTEXT(), portRESTORE_CONTEXT() +/* Standard includes. */ + +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the MSP430 port. + *----------------------------------------------------------*/ + +/* Constants required for hardware setup. The tick ISR runs off the ACLK, +not the MCLK. */ +#define portACLK_FREQUENCY_HZ ( ( portTickType ) 32768 ) +#define portINITIAL_CRITICAL_NESTING ( ( unsigned portSHORT ) 10 ) +#define portFLAGS_INT_ENABLED ( ( portSTACK_TYPE ) 0x08 ) + +/* We require the address of the pxCurrentTCB variable, but don't want to know +any details of its type. */ +typedef void tskTCB; +extern volatile tskTCB * volatile pxCurrentTCB; + +unsigned portCHAR ucReschedule; + +/* Each task maintains a count of the critical section nesting depth. Each +time a critical section is entered the count is incremented. Each time a +critical section is exited the count is decremented - with interrupts only +being re-enabled if the count is zero. + +usCriticalNesting will get set to zero when the scheduler starts, but must +not be initialised to zero as this will cause problems during the startup +sequence. */ +volatile unsigned portSHORT usCriticalNesting = portINITIAL_CRITICAL_NESTING; +/*-----------------------------------------------------------*/ + +/* + * Sets up the periodic ISR used for the RTOS tick. This uses timer 0, but + * could have alternatively used the watchdog timer or timer 1. + */ +void prvSetupTimerInterrupt( void ); +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See the header file portable.h. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ + /* + Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging and can be included if required. + + *pxTopOfStack = ( portSTACK_TYPE ) 0x1111; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x2222; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x3333; + pxTopOfStack--; + */ + + /* The msp430 automatically pushes the PC then SR onto the stack before + executing an ISR. We want the stack to look just as if this has happened + so place a pointer to the start of the task on the stack first - followed + by the flags we want the task to use when it starts up. */ + *pxTopOfStack = ( portSTACK_TYPE ) pxCode; + pxTopOfStack--; + *pxTopOfStack = portFLAGS_INT_ENABLED; + pxTopOfStack--; + + /* Next the general purpose registers. */ + *pxTopOfStack = ( portSTACK_TYPE ) 0x4444; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x5555; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x6666; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x7777; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x8888; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x9999; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaa; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xbbbb; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xcccc; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xdddd; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xeeee; + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + R15. */ + *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; + pxTopOfStack--; + + /* A variable is used to keep track of the critical section nesting. + This variable has to be stored as part of the task context and is + initially set to zero. */ + *pxTopOfStack = ( portSTACK_TYPE ) portNO_CRITICAL_SECTION_NESTING; + + /* Return a pointer to the top of the stack we have generated so this can + be stored in the task control block for the task. */ + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the MSP430 port will get stopped. If required simply + disable the tick interrupt here. */ +} +/*-----------------------------------------------------------*/ + +/* + * Hardware initialisation to generate the RTOS tick. This uses timer 0 + * but could alternatively use the watchdog timer or timer 1. + */ +void prvSetupTimerInterrupt( void ) +{ + /* Ensure the timer is stopped. */ + TACTL = 0; + + /* Run the timer of the ACLK. */ + TACTL = TASSEL_1; + + /* Clear everything to start with. */ + TACTL |= TACLR; + + /* Set the compare match value according to the tick rate we want. */ + TACCR0 = portACLK_FREQUENCY_HZ / configTICK_RATE_HZ; + + /* Enable the interrupts. */ + TACCTL0 = CCIE; + + /* Start up clean. */ + TACTL |= TACLR; + + /* Up mode. */ + TACTL |= MC_1; +} +/*-----------------------------------------------------------*/ + +/* + * The interrupt service routine used depends on whether the pre-emptive + * scheduler is being used or not. + */ + +#if configUSE_PREEMPTION == 1 + + /* + * Tick ISR for preemptive scheduler. We can use a naked attribute as + * the context is saved at the start of vPortYieldFromTick(). The tick + * count is incremented after the context is saved. + */ + void ISROsTick( void ) + { + /* Increment the tick count then switch to the highest priority task + that is ready to run. */ + vTaskIncrementTick(); + vTaskSwitchContext(); + } + +#else + + /* + * Tick ISR for the cooperative scheduler. All this does is increment the + * tick count. We don't need to switch context, this can only be done by + * manual calls to taskYIELD(); + */ + void ISROsTick( void ) + { + vTaskIncrementTick(); + } +#endif + + + diff --git a/20080212/Source/portable/Rowley/MSP430F449/Port2/portext.asm b/20080212/Source/portable/Rowley/MSP430F449/Port2/portext.asm new file mode 100644 index 000000000..0eb8b6bf3 --- /dev/null +++ b/20080212/Source/portable/Rowley/MSP430F449/Port2/portext.asm @@ -0,0 +1,147 @@ +#include + +/* + * Milos Prokic + */ + +/********************************************************** +All Interrupts should follow the naming convention : ISR"name" and declared +as a normal function in C. + +One must not forget to allocate interrupts below (see the line "MSPINT OsTick" +below for an example). + +By default the ISR will not cause the context switch, but if called in +conjunction with portENTER_SWITCHING_ISR/portEXIT_SWITCHING_ISR(wakeup), where +wakeup = TRUE upon exit the ISR will force the context switch via the +ucReschedule global variable. +**********************************************************/ +MSPINT macro name +_##name:: + call #_portSAVE_CONTEXT + call #_ISR##name + br #_portSWITCH_EXIT + endm + + +/********************************************************** +API code +**********************************************************/ + + .CODE +_vPortYield:: + /* Mimic an INT call by pushing SR. */ + push SR + /* no INTs !! */ + dint + /* Save the context of the current task. */ + call #_portSAVE_CONTEXT + /* Switch to the highest priority task that is ready to run. */ + call #_vTaskSwitchContext + /* Restore the context of the new task. */ + br #_portSWITCH_EXIT + +_xPortStartScheduler:: + /* Setup the hardware to generate the tick. Interrupts are disabled when + this function is called. */ + call #_prvSetupTimerInterrupt + + /* Restore the context of the first task that is going to run. */ + jmp _portRESTORE_CONTEXT + +_portSAVE_CONTEXT:: + /* Function to save the context. When this function is called the + return address will appear on the stack. This does not need to be + saved so is overwritten by R4 - hence R4 is not saved initially. + + Save the general purpose registers. */ + push R5 + push R6 + push R7 + push R8 + push R9 + push R10 + push R11 + push R12 + push R13 + push R14 + push R15 + + /* Now R10 has been saved we can use it to hold the return address, + which is about to be overwritten. */ + mov 22(R1),R10 + + /* Store R4 where the return address was on the stack. */ + mov R4,22(R1) + + /* Save the critical nesting depth. */ + mov.w &_usCriticalNesting, R14 + push R14 + + /* Finally save the new top of stack. */ + mov.w &_pxCurrentTCB, R12 + mov.w R1, @R12 + + /* No rescheduling by default. */ + mov.b #0,&_ucReschedule + + /* Return using the saved return address. */ + br R10 + + +_portSWITCH_EXIT:: + /* Check ucReschedule to see if a context switch is required. */ + tst.b &_ucReschedule + jz _portRESTORE_CONTEXT + call #_vTaskSwitchContext +_portRESTORE_CONTEXT:: + /* Restore the context in the opposite order to the save. */ + mov.w &_pxCurrentTCB, R12 + mov.w @R12, R1 + pop R15 + mov.w R15, &_usCriticalNesting + pop R15 + pop R14 + pop R13 + pop R12 + pop R11 + pop R10 + pop R9 + pop R8 + pop R7 + pop R6 + pop R5 + pop R4 + reti + + +/********************************************************** +Allocate Interrupts using the MSPINT macro (defined at the top of this file. +ex: MSPINT "name" +**********************************************************/ + + MSPINT OsTick + MSPINT Com1Rx + MSPINT Com1Tx + + +/********************************************************* +Interrupt Vectors +Timer_A0 +ex: PORT1 would look like: +ORG PORT1_VECTOR +DW _"name" +**********************************************************/ + .VECTORS + .KEEP + + ORG TIMERA0_VECTOR + DW _OsTick + + ORG UART1RX_VECTOR + DW _Com1Rx + + ORG UART1TX_VECTOR + DW _Com1Tx + + END diff --git a/20080212/Source/portable/Rowley/MSP430F449/Port2/portmacro.h b/20080212/Source/portable/Rowley/MSP430F449/Port2/portmacro.h new file mode 100644 index 000000000..d13675b5f --- /dev/null +++ b/20080212/Source/portable/Rowley/MSP430F449/Port2/portmacro.h @@ -0,0 +1,154 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE unsigned portSHORT +#define portBASE_TYPE portSHORT + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Interrupt control macros. */ +#define portDISABLE_INTERRUPTS() _DINT(); +#define portENABLE_INTERRUPTS() _EINT(); +/*-----------------------------------------------------------*/ + +/* Critical section control macros. */ +#define portNO_CRITICAL_SECTION_NESTING ( ( unsigned portSHORT ) 0 ) + +#define portENTER_CRITICAL() \ +{ \ +extern volatile unsigned portSHORT usCriticalNesting; \ + \ + portDISABLE_INTERRUPTS(); \ + \ + /* Now interrupts are disabled ulCriticalNesting can be accessed */ \ + /* directly. Increment ulCriticalNesting to keep a count of how many */ \ + /* times portENTER_CRITICAL() has been called. */ \ + usCriticalNesting++; \ +} + +#define portEXIT_CRITICAL() \ +{ \ +extern volatile unsigned portSHORT usCriticalNesting; \ + \ + if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ + { \ + /* Decrement the nesting count as we are leaving a critical section. */ \ + usCriticalNesting--; \ + \ + /* If the nesting level has reached zero then interrupts should be */ \ + /* re-enabled. */ \ + if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ + } \ +} +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* + * Manual context switch called by portYIELD or taskYIELD. + */ +extern void vPortYield( void ); + +#define portYIELD() vPortYield() +/*-----------------------------------------------------------*/ + +#define portENTER_SWITCHING_ISR() +#define portEXIT_SWITCHING_ISR( SwitchRequired ) \ + { \ + extern unsigned portCHAR ucReschedule; \ + if( SwitchRequired ) \ + { \ + ucReschedule = 1; \ + } \ + } + +/* Hardwware specifics. */ +#define portBYTE_ALIGNMENT 2 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) __toplevel + +/* Compiler specifics. */ +#define inline +#define portNOP() + + +/* Just used by the demo application to indicate which form of interrupt +service routine should be used. See the online port documentation for more +information. */ +#define MSP_ROWLEY_MP_PORT + +#endif /* PORTMACRO_H */ + diff --git a/20080212/Source/portable/Rowley/MSP430F449/port.c b/20080212/Source/portable/Rowley/MSP430F449/port.c new file mode 100644 index 000000000..6195dbe4b --- /dev/null +++ b/20080212/Source/portable/Rowley/MSP430F449/port.c @@ -0,0 +1,187 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the MSP430 port. + *----------------------------------------------------------*/ + +/* Constants required for hardware setup. The tick ISR runs off the ACLK, +not the MCLK. */ +#define portACLK_FREQUENCY_HZ ( ( portTickType ) 32768 ) +#define portINITIAL_CRITICAL_NESTING ( ( unsigned portSHORT ) 10 ) +#define portFLAGS_INT_ENABLED ( ( portSTACK_TYPE ) 0x08 ) + +/* We require the address of the pxCurrentTCB variable, but don't want to know +any details of its type. */ +typedef void tskTCB; +extern volatile tskTCB * volatile pxCurrentTCB; + +/* Each task maintains a count of the critical section nesting depth. Each +time a critical section is entered the count is incremented. Each time a +critical section is exited the count is decremented - with interrupts only +being re-enabled if the count is zero. + +usCriticalNesting will get set to zero when the scheduler starts, but must +not be initialised to zero as this will cause problems during the startup +sequence. */ +volatile unsigned portSHORT usCriticalNesting = portINITIAL_CRITICAL_NESTING; +/*-----------------------------------------------------------*/ + + +/* + * Sets up the periodic ISR used for the RTOS tick. This uses timer 0, but + * could have alternatively used the watchdog timer or timer 1. + */ +void prvSetupTimerInterrupt( void ); +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See the header file portable.h. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ + /* + Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging and can be included if required. + + *pxTopOfStack = ( portSTACK_TYPE ) 0x1111; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x2222; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x3333; + pxTopOfStack--; + */ + + /* The msp430 automatically pushes the PC then SR onto the stack before + executing an ISR. We want the stack to look just as if this has happened + so place a pointer to the start of the task on the stack first - followed + by the flags we want the task to use when it starts up. */ + *pxTopOfStack = ( portSTACK_TYPE ) pxCode; + pxTopOfStack--; + *pxTopOfStack = portFLAGS_INT_ENABLED; + pxTopOfStack--; + + /* Next the general purpose registers. */ + *pxTopOfStack = ( portSTACK_TYPE ) 0x4444; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x5555; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x6666; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x7777; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x8888; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x9999; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaa; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xbbbb; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xcccc; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xdddd; + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xeeee; + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + R15. */ + *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; + pxTopOfStack--; + + /* A variable is used to keep track of the critical section nesting. + This variable has to be stored as part of the task context and is + initially set to zero. */ + *pxTopOfStack = ( portSTACK_TYPE ) portNO_CRITICAL_SECTION_NESTING; + + /* Return a pointer to the top of the stack we have generated so this can + be stored in the task control block for the task. */ + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the MSP430 port will get stopped. If required simply + disable the tick interrupt here. */ +} +/*-----------------------------------------------------------*/ + +/* + * Hardware initialisation to generate the RTOS tick. This uses timer 0 + * but could alternatively use the watchdog timer or timer 1. + */ +void prvSetupTimerInterrupt( void ) +{ + /* Ensure the timer is stopped. */ + TACTL = 0; + + /* Run the timer of the ACLK. */ + TACTL = TASSEL_1; + + /* Clear everything to start with. */ + TACTL |= TACLR; + + /* Set the compare match value according to the tick rate we want. */ + TACCR0 = portACLK_FREQUENCY_HZ / configTICK_RATE_HZ; + + /* Enable the interrupts. */ + TACCTL0 = CCIE; + + /* Start up clean. */ + TACTL |= TACLR; + + /* Up mode. */ + TACTL |= MC_1; +} +/*-----------------------------------------------------------*/ + + + diff --git a/20080212/Source/portable/Rowley/MSP430F449/portext.asm b/20080212/Source/portable/Rowley/MSP430F449/portext.asm new file mode 100644 index 000000000..4bf0aeb06 --- /dev/null +++ b/20080212/Source/portable/Rowley/MSP430F449/portext.asm @@ -0,0 +1,116 @@ +#include "FreeRTOSConfig.h" + +portSAVE_CONTEXT macro + push r4 + push r5 + push r6 + push r7 + push r8 + push r9 + push r10 + push r11 + push r12 + push r13 + push r14 + push r15 + mov.w &_usCriticalNesting, r14 + push r14 + mov.w &_pxCurrentTCB, r12 + mov.w r1, @r12 + endm +/*-----------------------------------------------------------*/ + +portRESTORE_CONTEXT macro + mov.w &_pxCurrentTCB, r12 + mov.w @r12, r1 + pop r15 + mov.w r15, &_usCriticalNesting + pop r15 + pop r14 + pop r13 + pop r12 + pop r11 + pop r10 + pop r9 + pop r8 + pop r7 + pop r6 + pop r5 + pop r4 + reti + endm +/*-----------------------------------------------------------*/ + + +.CODE + +/* + * The RTOS tick ISR. + * + * If the cooperative scheduler is in use this simply increments the tick + * count. + * + * If the preemptive scheduler is in use a context switch can also occur. + */ +_vTickISR: + portSAVE_CONTEXT + + call #_vTaskIncrementTick + + #if configUSE_PREEMPTION == 1 + call #_vTaskSwitchContext + #endif + + portRESTORE_CONTEXT +/*-----------------------------------------------------------*/ + + +/* + * Manual context switch called by the portYIELD() macro. + */ +_vPortYield:: + + /* Mimic an interrupt by pushing the SR. */ + push SR + + /* Now the SR is stacked we can disable interrupts. */ + dint + + /* Save the context of the current task. */ + portSAVE_CONTEXT + + /* Switch to the highest priority task that is ready to run. */ + call #_vTaskSwitchContext + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT +/*-----------------------------------------------------------*/ + + +/* + * Start off the scheduler by initialising the RTOS tick timer, then restoring + * the context of the first task. + */ +_xPortStartScheduler:: + + /* Setup the hardware to generate the tick. Interrupts are disabled + when this function is called. */ + call #_prvSetupTimerInterrupt + + /* Restore the context of the first task that is going to run. */ + portRESTORE_CONTEXT +/*-----------------------------------------------------------*/ + + + /* Place the tick ISR in the correct vector. */ + .VECTORS + + .KEEP + + ORG TIMERA0_VECTOR + DW _vTickISR + + + + END + diff --git a/20080212/Source/portable/Rowley/MSP430F449/portmacro.h b/20080212/Source/portable/Rowley/MSP430F449/portmacro.h new file mode 100644 index 000000000..249a7e4ea --- /dev/null +++ b/20080212/Source/portable/Rowley/MSP430F449/portmacro.h @@ -0,0 +1,143 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE unsigned portSHORT +#define portBASE_TYPE portSHORT + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif + +/*-----------------------------------------------------------*/ + +/* Interrupt control macros. */ +#define portDISABLE_INTERRUPTS() _DINT(); +#define portENABLE_INTERRUPTS() _EINT(); +/*-----------------------------------------------------------*/ + +/* Critical section control macros. */ +#define portNO_CRITICAL_SECTION_NESTING ( ( unsigned portSHORT ) 0 ) + +#define portENTER_CRITICAL() \ +{ \ +extern volatile unsigned portSHORT usCriticalNesting; \ + \ + portDISABLE_INTERRUPTS(); \ + \ + /* Now interrupts are disabled usCriticalNesting can be accessed */ \ + /* directly. Increment ulCriticalNesting to keep a count of how many */ \ + /* times portENTER_CRITICAL() has been called. */ \ + usCriticalNesting++; \ +} + +#define portEXIT_CRITICAL() \ +{ \ +extern volatile unsigned portSHORT usCriticalNesting; \ + \ + if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ + { \ + /* Decrement the nesting count as we are leaving a critical section. */ \ + usCriticalNesting--; \ + \ + /* If the nesting level has reached zero then interrupts should be */ \ + /* re-enabled. */ \ + if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ + } \ +} +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* + * Manual context switch called by portYIELD or taskYIELD. + */ +extern void vPortYield( void ); +#define portYIELD() vPortYield() +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 2 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portNOP() +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) __toplevel + +/* Compiler specifics. */ +#define inline + +/* Just used by the demo application to indicate which form of interrupt +service routine should be used. See the online port documentation for more +information. */ +#define MSP_ROWLEY_RB_PORT + +#endif /* PORTMACRO_H */ + diff --git a/20080212/Source/portable/Rowley/MSP430F449/readme.txt b/20080212/Source/portable/Rowley/MSP430F449/readme.txt new file mode 100644 index 000000000..f438b3642 --- /dev/null +++ b/20080212/Source/portable/Rowley/MSP430F449/readme.txt @@ -0,0 +1,5 @@ +To use Port1, copy the three files from the Port1 directory into this directory. + +To use Port2, copy the three files from the Port2 directory into this directory. + +Ensure to perform a complete rebuild. \ No newline at end of file diff --git a/20080212/Source/portable/SDCC/Cygnal/port.c b/20080212/Source/portable/SDCC/Cygnal/port.c new file mode 100644 index 000000000..d86523179 --- /dev/null +++ b/20080212/Source/portable/SDCC/Cygnal/port.c @@ -0,0 +1,437 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the Cygnal port. + *----------------------------------------------------------*/ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to setup timer 2 to produce the RTOS tick. */ +#define portCLOCK_DIVISOR ( ( unsigned portLONG ) 12 ) +#define portMAX_TIMER_VALUE ( ( unsigned portLONG ) 0xffff ) +#define portENABLE_TIMER ( ( unsigned portCHAR ) 0x04 ) +#define portTIMER_2_INTERRUPT_ENABLE ( ( unsigned portCHAR ) 0x20 ) + +/* The value used in the IE register when a task first starts. */ +#define portGLOBAL_INTERRUPT_BIT ( ( portSTACK_TYPE ) 0x80 ) + +/* The value used in the PSW register when a task first starts. */ +#define portINITIAL_PSW ( ( portSTACK_TYPE ) 0x00 ) + +/* Macro to clear the timer 2 interrupt flag. */ +#define portCLEAR_INTERRUPT_FLAG() TMR2CN &= ~0x80; + +/* Used during a context switch to store the size of the stack being copied +to or from XRAM. */ +data static unsigned portCHAR ucStackBytes; + +/* Used during a context switch to point to the next byte in XRAM from/to which +a RAM byte is to be copied. */ +xdata static portSTACK_TYPE * data pxXRAMStack; + +/* Used during a context switch to point to the next byte in RAM from/to which +an XRAM byte is to be copied. */ +data static portSTACK_TYPE * data pxRAMStack; + +/* We require the address of the pxCurrentTCB variable, but don't want to know +any details of its type. */ +typedef void tskTCB; +extern volatile tskTCB * volatile pxCurrentTCB; + +/* + * Setup the hardware to generate an interrupt off timer 2 at the required + * frequency. + */ +static void prvSetupTimerInterrupt( void ); + +/*-----------------------------------------------------------*/ +/* + * Macro that copies the current stack from internal RAM to XRAM. This is + * required as the 8051 only contains enough internal RAM for a single stack, + * but we have a stack for every task. + */ +#define portCOPY_STACK_TO_XRAM() \ +{ \ + /* pxCurrentTCB points to a TCB which itself points to the location into \ + which the first stack byte should be copied. Set pxXRAMStack to point \ + to the location into which the first stack byte is to be copied. */ \ + pxXRAMStack = ( xdata portSTACK_TYPE * ) *( ( xdata portSTACK_TYPE ** ) pxCurrentTCB ); \ + \ + /* Set pxRAMStack to point to the first byte to be coped from the stack. */ \ + pxRAMStack = ( data portSTACK_TYPE * data ) configSTACK_START; \ + \ + /* Calculate the size of the stack we are about to copy from the current \ + stack pointer value. */ \ + ucStackBytes = SP - ( configSTACK_START - 1 ); \ + \ + /* Before starting to copy the stack, store the calculated stack size so \ + the stack can be restored when the task is resumed. */ \ + *pxXRAMStack = ucStackBytes; \ + \ + /* Copy each stack byte in turn. pxXRAMStack is incremented first as we \ + have already stored the stack size into XRAM. */ \ + while( ucStackBytes ) \ + { \ + pxXRAMStack++; \ + *pxXRAMStack = *pxRAMStack; \ + pxRAMStack++; \ + ucStackBytes--; \ + } \ +} +/*-----------------------------------------------------------*/ + +/* + * Macro that copies the stack of the task being resumed from XRAM into + * internal RAM. + */ +#define portCOPY_XRAM_TO_STACK() \ +{ \ + /* Setup the pointers as per portCOPY_STACK_TO_XRAM(), but this time to \ + copy the data back out of XRAM and into the stack. */ \ + pxXRAMStack = ( xdata portSTACK_TYPE * ) *( ( xdata portSTACK_TYPE ** ) pxCurrentTCB ); \ + pxRAMStack = ( data portSTACK_TYPE * data ) ( configSTACK_START - 1 ); \ + \ + /* The first value stored in XRAM was the size of the stack - i.e. the \ + number of bytes we need to copy back. */ \ + ucStackBytes = pxXRAMStack[ 0 ]; \ + \ + /* Copy the required number of bytes back into the stack. */ \ + do \ + { \ + pxXRAMStack++; \ + pxRAMStack++; \ + *pxRAMStack = *pxXRAMStack; \ + ucStackBytes--; \ + } while( ucStackBytes ); \ + \ + /* Restore the stack pointer ready to use the restored stack. */ \ + SP = ( unsigned portCHAR ) pxRAMStack; \ +} +/*-----------------------------------------------------------*/ + +/* + * Macro to push the current execution context onto the stack, before the stack + * is moved to XRAM. + */ +#define portSAVE_CONTEXT() \ +{ \ + _asm \ + /* Push ACC first, as when restoring the context it must be restored \ + last (it is used to set the IE register). */ \ + push ACC \ + /* Store the IE register then disable interrupts. */ \ + push IE \ + clr _EA \ + push DPL \ + push DPH \ + push b \ + push ar2 \ + push ar3 \ + push ar4 \ + push ar5 \ + push ar6 \ + push ar7 \ + push ar0 \ + push ar1 \ + push PSW \ + _endasm; \ + PSW = 0; \ + _asm \ + push _bp \ + _endasm; \ +} +/*-----------------------------------------------------------*/ + +/* + * Macro that restores the execution context from the stack. The execution + * context was saved into the stack before the stack was copied into XRAM. + */ +#define portRESTORE_CONTEXT() \ +{ \ + _asm \ + pop _bp \ + pop PSW \ + pop ar1 \ + pop ar0 \ + pop ar7 \ + pop ar6 \ + pop ar5 \ + pop ar4 \ + pop ar3 \ + pop ar2 \ + pop b \ + pop DPH \ + pop DPL \ + /* The next byte of the stack is the IE register. Only the global \ + enable bit forms part of the task context. Pop off the IE then set \ + the global enable bit to match that of the stored IE register. */ \ + pop ACC \ + JB ACC.7,0098$ \ + CLR IE.7 \ + LJMP 0099$ \ + 0098$: \ + SETB IE.7 \ + 0099$: \ + /* Finally pop off the ACC, which was the first register saved. */ \ + pop ACC \ + reti \ + _endasm; \ +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ +unsigned portLONG ulAddress; +portSTACK_TYPE *pxStartOfStack; + + /* Leave space to write the size of the stack as the first byte. */ + pxStartOfStack = pxTopOfStack; + pxTopOfStack++; + + /* Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging and can be uncommented if required. + *pxTopOfStack = 0x11; + pxTopOfStack++; + *pxTopOfStack = 0x22; + pxTopOfStack++; + *pxTopOfStack = 0x33; + pxTopOfStack++; + */ + + /* Simulate how the stack would look after a call to the scheduler tick + ISR. + + The return address that would have been pushed by the MCU. */ + ulAddress = ( unsigned portLONG ) pxCode; + *pxTopOfStack = ( portSTACK_TYPE ) ulAddress; + ulAddress >>= 8; + pxTopOfStack++; + *pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress ); + pxTopOfStack++; + + /* Next all the registers will have been pushed by portSAVE_CONTEXT(). */ + *pxTopOfStack = 0xaa; /* acc */ + pxTopOfStack++; + + /* We want tasks to start with interrupts enabled. */ + *pxTopOfStack = portGLOBAL_INTERRUPT_BIT; + pxTopOfStack++; + + /* The function parameters will be passed in the DPTR and B register as + a three byte generic pointer is used. */ + ulAddress = ( unsigned portLONG ) pvParameters; + *pxTopOfStack = ( portSTACK_TYPE ) ulAddress; /* DPL */ + ulAddress >>= 8; + *pxTopOfStack++; + *pxTopOfStack = ( portSTACK_TYPE ) ulAddress; /* DPH */ + ulAddress >>= 8; + pxTopOfStack++; + *pxTopOfStack = ( portSTACK_TYPE ) ulAddress; /* b */ + pxTopOfStack++; + + /* The remaining registers are straight forward. */ + *pxTopOfStack = 0x02; /* R2 */ + pxTopOfStack++; + *pxTopOfStack = 0x03; /* R3 */ + pxTopOfStack++; + *pxTopOfStack = 0x04; /* R4 */ + pxTopOfStack++; + *pxTopOfStack = 0x05; /* R5 */ + pxTopOfStack++; + *pxTopOfStack = 0x06; /* R6 */ + pxTopOfStack++; + *pxTopOfStack = 0x07; /* R7 */ + pxTopOfStack++; + *pxTopOfStack = 0x00; /* R0 */ + pxTopOfStack++; + *pxTopOfStack = 0x01; /* R1 */ + pxTopOfStack++; + *pxTopOfStack = 0x00; /* PSW */ + pxTopOfStack++; + *pxTopOfStack = 0xbb; /* BP */ + + /* Dont increment the stack size here as we don't want to include + the stack size byte as part of the stack size count. + + Finally we place the stack size at the beginning. */ + *pxStartOfStack = ( portSTACK_TYPE ) ( pxTopOfStack - pxStartOfStack ); + + /* Unlike most ports, we return the start of the stack as this is where the + size of the stack is stored. */ + return pxStartOfStack; +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +portBASE_TYPE xPortStartScheduler( void ) +{ + /* Setup timer 2 to generate the RTOS tick. */ + prvSetupTimerInterrupt(); + + /* Make sure we start with the expected SFR page. This line should not + really be required. */ + SFRPAGE = 0; + + /* Copy the stack for the first task to execute from XRAM into the stack, + restore the task context from the new stack, then start running the task. */ + portCOPY_XRAM_TO_STACK(); + portRESTORE_CONTEXT(); + + /* Should never get here! */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented for this port. */ +} +/*-----------------------------------------------------------*/ + +/* + * Manual context switch. The first thing we do is save the registers so we + * can use a naked attribute. + */ +void vPortYield( void ) _naked +{ + /* Save the execution context onto the stack, then copy the entire stack + to XRAM. This is necessary as the internal RAM is only large enough to + hold one stack, and we want one per task. + + PERFORMANCE COULD BE IMPROVED BY ONLY COPYING TO XRAM IF A TASK SWITCH + IS REQUIRED. */ + portSAVE_CONTEXT(); + portCOPY_STACK_TO_XRAM(); + + /* Call the standard scheduler context switch function. */ + vTaskSwitchContext(); + + /* Copy the stack of the task about to execute from XRAM into RAM and + restore it's context ready to run on exiting. */ + portCOPY_XRAM_TO_STACK(); + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +#if configUSE_PREEMPTION == 1 + void vTimer2ISR( void ) interrupt 5 _naked + { + /* Preemptive context switch function triggered by the timer 2 ISR. + This does the same as vPortYield() (see above) with the addition + of incrementing the RTOS tick count. */ + + portSAVE_CONTEXT(); + portCOPY_STACK_TO_XRAM(); + + vTaskIncrementTick(); + vTaskSwitchContext(); + + portCLEAR_INTERRUPT_FLAG(); + portCOPY_XRAM_TO_STACK(); + portRESTORE_CONTEXT(); + } +#else + void vTimer2ISR( void ) interrupt 5 + { + /* When using the cooperative scheduler the timer 2 ISR is only + required to increment the RTOS tick count. */ + + vTaskIncrementTick(); + portCLEAR_INTERRUPT_FLAG(); + } +#endif +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ +unsigned portCHAR ucOriginalSFRPage; + +/* Constants calculated to give the required timer capture values. */ +const unsigned portLONG ulTicksPerSecond = configCPU_CLOCK_HZ / portCLOCK_DIVISOR; +const unsigned portLONG ulCaptureTime = ulTicksPerSecond / configTICK_RATE_HZ; +const unsigned portLONG ulCaptureValue = portMAX_TIMER_VALUE - ulCaptureTime; +const unsigned portCHAR ucLowCaptureByte = ( unsigned portCHAR ) ( ulCaptureValue & ( unsigned portLONG ) 0xff ); +const unsigned portCHAR ucHighCaptureByte = ( unsigned portCHAR ) ( ulCaptureValue >> ( unsigned portLONG ) 8 ); + + /* NOTE: This uses a timer only present on 8052 architecture. */ + + /* Remember the current SFR page so we can restore it at the end of the + function. */ + ucOriginalSFRPage = SFRPAGE; + SFRPAGE = 0; + + /* TMR2CF can be left in its default state. */ + TMR2CF = ( unsigned portCHAR ) 0; + + /* Setup the overflow reload value. */ + RCAP2L = ucLowCaptureByte; + RCAP2H = ucHighCaptureByte; + + /* The initial load is performed manually. */ + TMR2L = ucLowCaptureByte; + TMR2H = ucHighCaptureByte; + + /* Enable the timer 2 interrupts. */ + IE |= portTIMER_2_INTERRUPT_ENABLE; + + /* Interrupts are disabled when this is called so the timer can be started + here. */ + TMR2CN = portENABLE_TIMER; + + /* Restore the original SFR page. */ + SFRPAGE = ucOriginalSFRPage; +} + + + + diff --git a/20080212/Source/portable/SDCC/Cygnal/portmacro.h b/20080212/Source/portable/SDCC/Cygnal/portmacro.h new file mode 100644 index 000000000..a01fe77ef --- /dev/null +++ b/20080212/Source/portable/SDCC/Cygnal/portmacro.h @@ -0,0 +1,128 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#if configUSE_PREEMPTION == 0 + void vTimer2ISR( void ) interrupt 5; +#else + void vTimer2ISR( void ) interrupt 5 _naked; +#endif + +void vSerialISR( void ) interrupt 4; + + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE float +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned portCHAR +#define portBASE_TYPE char + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +#define portENTER_CRITICAL() _asm \ + push ACC \ + push IE \ + _endasm; \ + EA = 0; + +#define portEXIT_CRITICAL() _asm \ + pop ACC \ + _endasm; \ + ACC &= 0x80; \ + IE |= ACC; \ + _asm \ + pop ACC \ + _endasm; + +#define portDISABLE_INTERRUPTS() EA = 0; +#define portENABLE_INTERRUPTS() EA = 1; +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 1 +#define portSTACK_GROWTH ( 1 ) +#define portTICK_RATE_MS ( ( unsigned portLONG ) 1000 / configTICK_RATE_HZ ) +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +void vPortYield( void ) _naked; +#define portYIELD() vPortYield(); +/*-----------------------------------------------------------*/ + +/* Compiler specifics. */ +#define inline +#define portNOP() _asm \ + nop \ + _endasm; + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#endif /* PORTMACRO_H */ + + diff --git a/20080212/Source/portable/Softune/MB91460/__STD_LIB_sbrk.c b/20080212/Source/portable/Softune/MB91460/__STD_LIB_sbrk.c new file mode 100644 index 000000000..fe70d4872 --- /dev/null +++ b/20080212/Source/portable/Softune/MB91460/__STD_LIB_sbrk.c @@ -0,0 +1,23 @@ +#include "FreeRTOSConfig.h" +#include + + static long brk_siz = 0; +// #if configTOTAL_HEAP_SIZE != 0 + typedef int _heep_t; + #define ROUNDUP(s) (((s)+sizeof(_heep_t)-1)&~(sizeof(_heep_t)-1)) + static _heep_t _heep[ROUNDUP(configTOTAL_HEAP_SIZE)/sizeof(_heep_t)]; + #define _heep_size ROUNDUP(configTOTAL_HEAP_SIZE) +/* #else + extern char *_heep; + extern long _heep_size; + #endif +*/ + extern char *sbrk(int size) + { + if (brk_siz + size > _heep_size || brk_siz + size < 0) + + return((char*)-1); + brk_siz += size; + return( (char*)_heep + brk_siz - size); + } + diff --git a/20080212/Source/portable/Softune/MB91460/port.c b/20080212/Source/portable/Softune/MB91460/port.c new file mode 100644 index 000000000..969f39826 --- /dev/null +++ b/20080212/Source/portable/Softune/MB91460/port.c @@ -0,0 +1,397 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#include "FreeRTOS.h" +#include "task.h" +#include "mb91467d.h" + +/*-----------------------------------------------------------*/ + +/* We require the address of the pxCurrentTCB variable, but don't want to know +any details of its type. */ +typedef void tskTCB; +extern volatile tskTCB * volatile pxCurrentTCB; + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( unsigned portBASE_TYPE ) 0 ) +volatile unsigned portLONG ulCriticalNesting = 9999UL; + +/*-----------------------------------------------------------*/ + + + +#pragma asm +#macro SaveContext + ORCCR #0x20 ;Switch to user stack + ST RP,@-R15 ;Store RP + STM0 (R7,R6,R5,R4,R3,R2,R1,R0) ;Store R7-R0 + STM1 (R14,R13,R12,R11,R10,R9,R8) ;Store R14-R8 + ST MDH, @-R15 ;Store MDH + ST MDL, @-R15 ;Store MDL + + LDI #_ulCriticalNesting, R0 ;Get the address of the critical nesting counter + LD @R0, R0 ;Get the value of the critical nesting counter + ST R0, @-R15 ;Store the critical nesting value to the user stack. + + ANDCCR #0xDF ;Switch back to system stack + LD @R15+,R0 ;Store PC to R0 + ORCCR #0x20 ;Switch to user stack + ST R0,@-R15 ;Store PC to User stack + + ANDCCR #0xDF ;Switch back to system stack + LD @R15+,R0 ;Store PS to R0 + ORCCR #0x20 ;Switch to user stack + ST R0,@-R15 ;Store PS to User stack + + LDI #_pxCurrentTCB, R0 ;Get pxCurrentTCB address + LD @R0, R0 ;Get the pxCurrentTCB->pxTopOfStack address + ST R15,@R0 ;Store USP to pxCurrentTCB->pxTopOfStack + + ANDCCR #0xDF ;Switch back to system stack for the rest of tick ISR +#endm + +#macro RestoreContext + LDI #_pxCurrentTCB, R0 ;Get pxCurrentTCB address + LD @R0, R0 ;Get the pxCurrentTCB->pxTopOfStack address + ORCCR #0x20 ;Switch to user stack + LD @R0, R15 ;Restore USP from pxCurrentTCB->pxTopOfStack + + LD @R15+,R0 ;Store PS to R0 + ANDCCR #0xDF ;Switch to system stack + ST R0,@-R15 ;Store PS to system stack + + ORCCR #0x20 ;Switch to user stack + LD @R15+,R0 ;Store PC to R0 + ANDCCR #0xDF ;Switch to system stack + ST R0,@-R15 ;Store PC to system stack + + ORCCR #0x20 ;Switch back to retreive the remaining context + + LDI #_ulCriticalNesting, R0 ;Get the address of the critical nesting counter + LD @R15+, R1 ;Get the saved critical nesting value + ST R1, @R0 ;Save the critical nesting value into the ulCriticalNesting variable + + LD @R15+, MDL ;Restore MDL + LD @R15+, MDH ;Restore MDH + LDM1 (R14,R13,R12,R11,R10,R9,R8) ;Restore R14-R8 + LDM0 (R7,R6,R5,R4,R3,R2,R1,R0) ;Restore R7-R0 + LD @R15+, RP ;Restore RP + + ANDCCR #0xDF ;Switch back to system stack for the rest of tick ISR +#endm +#pragma endasm + +/*-----------------------------------------------------------*/ + +/* + * Perform hardware setup to enable ticks from timer 1, + */ +static void prvSetupTimerInterrupt( void ); +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See the header file portable.h. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ + /* Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging. */ + + *pxTopOfStack = 0x11111111; + pxTopOfStack--; + *pxTopOfStack = 0x22222222; + pxTopOfStack--; + *pxTopOfStack = 0x33333333; + pxTopOfStack--; + + /* This is a redundant push to the stack, it may be required if in some implentation of the compiler + the parameter to the task is passed on to the stack rather than in R4 register*/ + *pxTopOfStack = (portSTACK_TYPE)(pvParameters); + pxTopOfStack--; + + *pxTopOfStack = ( portSTACK_TYPE ) 0x00000000; /* RP */ + pxTopOfStack--; + + *pxTopOfStack = ( portSTACK_TYPE ) 0x00007777; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x00006666; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x00005555; /* R5 */ + pxTopOfStack--; + + /* In the current implemention of the compiler the first + parameter to the task(or function) is passed via R4 parameter + to the task, hennce the pvParameters pointer is copied in R4 + regsiter. See compiler manual section 4.6.2 for more information.*/ + *pxTopOfStack = ( portSTACK_TYPE ) (pvParameters); /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x00003333; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x00002222; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x00001111; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x00000001; /* R0 */ + pxTopOfStack--; + + *pxTopOfStack = ( portSTACK_TYPE ) 0x0000EEEE; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x0000DDDD; /* R13 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x0000CCCC; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x0000BBBB; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x0000AAAA; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x00009999; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x00008888; /* R8 */ + pxTopOfStack--; + + *pxTopOfStack = ( portSTACK_TYPE ) 0x11110000; /* MDH */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x22220000; /* MDL */ + pxTopOfStack--; + + /* The task starts with its ulCriticalNesting variable set to 0, interrupts + being enabled. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + pxTopOfStack--; + + /* The start of the task code. */ + *pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* PC */ + pxTopOfStack--; + + /* PS - User Mode, USP, ILM=31, Interrupts enabled */ + *pxTopOfStack = ( portSTACK_TYPE ) 0x001F0030; /* PS */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xPortStartScheduler( void ) +{ + /* Setup the hardware to generate the tick. */ + prvSetupTimerInterrupt(); + + /* Restore the context of the first task that is going to run. */ +#pragma asm + RestoreContext +#pragma endasm + + /* Simulate a function call end as generated by the compiler. We will now + jump to the start of the task the context of which we have just restored. */ + + __asm(" reti "); + + + /* Should not get here. */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented - unlikely to ever be required as there is nothing to + return to. */ +} +/*-----------------------------------------------------------*/ + +/* + * Setup RLT0 to generate a tick interrupt. + */ +static void prvSetupTimerInterrupt( void ) +{ +/* The peripheral clock divided by 32 is used by the timer. */ +const unsigned portSHORT usReloadValue = ( unsigned portSHORT ) ( ( ( configPER_CLOCK_HZ / configTICK_RATE_HZ ) / 32UL ) - 1UL ); + + TMCSR0_CNTE=0; /* Count Disable */ + TMCSR0_CSL=0x2; /* CLKP/32 */ + TMCSR0_MOD=0; /* Software trigger */ + TMCSR0_RELD=1; /* Reload */ + + TMCSR0_UF=0; /* Clear underflow flag */ + TMRLR0=usReloadValue; + TMCSR0_INTE=1; /* Interrupt Enable */ + TMCSR0_CNTE=1; /* Count Enable */ + TMCSR0_TRG=1; /* Trigger */ + + PORTEN = 0x3; /* Port Enable */ +} +/*-----------------------------------------------------------*/ + +#if configUSE_PREEMPTION == 1 + + /* + * Tick ISR for preemptive scheduler. The tick count is incremented + * after the context is saved. Then the context is switched if required, + * at last the context of the task which is to be resume is restored. + */ + + #pragma asm + + .global _ReloadTimer0_IRQHandler + _ReloadTimer0_IRQHandler: + + ANDCCR #0xEF ;Disable Interrupts + + SaveContext ;Save context + + ORCCR #0x10 ;Re-enable Interrupts + + LDI #0xFFFB,R1 + LDI #_tmcsr0, R0 + AND R1,@R0 ;Clear RLT0 interrupt flag + + CALL32 _vTaskIncrementTick,R12 ;Increment Tick + + CALL32 _vTaskSwitchContext,R12 ;Switch context if required + + ANDCCR #0xEF ;Disable Interrupts + + RestoreContext ;Restore context + + ORCCR #0x10 ;Re-enable Interrupts + + RETI + + #pragma endasm + +#else + + /* + * Tick ISR for the cooperative scheduler. All this does is increment the + * tick count. We don't need to switch context, this can only be done by + * manual calls to taskYIELD(); + */ + __interrupt void ReloadTimer0_IRQHandler( void ) + { + /* Clear RLT0 interrupt flag */ + TMCSR0_UF = 0; + vTaskIncrementTick(); + } + +#endif + + /* + * Manual context switch. We can use a __nosavereg attribute as the context + * would be saved by PortSAVE_CONTEXT(). The context is switched and then + * the context of the new task is restored saved. + */ +#pragma asm + + .global _vPortYieldDelayed + _vPortYieldDelayed: + + ANDCCR #0xEF ;Disable Interrupts + + SaveContext ;Save context + + ORCCR #0x10 ;Re-enable Interrupts + + LDI #_dicr, R0 + BANDL #0x0E, @R0 ;Clear Delayed interrupt flag + + CALL32 _vTaskSwitchContext,R12 ;Switch context if required + + ANDCCR #0xEF ;Disable Interrupts + + RestoreContext ;Restore context + + ORCCR #0x10 ;Re-enable Interrupts + + RETI + +#pragma endasm + + /* + * Manual context switch. We can use a __nosavereg attribute as the context + * would be saved by PortSAVE_CONTEXT(). The context is switched and then + * the context of the new task is restored saved. + */ + +#pragma asm + + .global _vPortYield + _vPortYield: + + SaveContext ;Save context + + CALL32 _vTaskSwitchContext,R12 ;Switch context if required + + RestoreContext ;Restore context + + RETI + +#pragma endasm + +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + /* Disable interrupts */ + portDISABLE_INTERRUPTS(); + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + ulCriticalNesting--; + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Enable all interrupt/exception. */ + portENABLE_INTERRUPTS(); + } + } +} +/*-----------------------------------------------------------*/ diff --git a/20080212/Source/portable/Softune/MB91460/portmacro.h b/20080212/Source/portable/Softune/MB91460/portmacro.h new file mode 100644 index 000000000..5b4ba3136 --- /dev/null +++ b/20080212/Source/portable/Softune/MB91460/portmacro.h @@ -0,0 +1,111 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#include "mb91467d.h" +#include + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned portLONG +#define portBASE_TYPE long + +/* This is required since SOFTUNE doesn't support inline directive as is. */ +#define inline + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +void vPortEnterCritical( void ); +void vPortExitCritical( void ); +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +#define portDISABLE_INTERRUPTS() __DI(); +#define portENABLE_INTERRUPTS() __EI(); + +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 4 +#define portNOP() __asm( " nop " ); +/*-----------------------------------------------------------*/ + +/* portYIELD() uses SW interrupt */ +#define portYIELD() __asm( " INT #40H " ); + +/* portYIELD_FROM_ISR() uses delayed interrupt */ +#define portYIELD_FROM_ISR() DICR_DLYI = 1 +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#define portMINIMAL_STACK_SIZE configMINIMAL_STACK_SIZE + +#endif /* PORTMACRO_H */ + diff --git a/20080212/Source/portable/Softune/MB96340/__STD_LIB_sbrk.c b/20080212/Source/portable/Softune/MB96340/__STD_LIB_sbrk.c new file mode 100644 index 000000000..3e8f577b6 --- /dev/null +++ b/20080212/Source/portable/Softune/MB96340/__STD_LIB_sbrk.c @@ -0,0 +1,33 @@ +/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ +/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ +/* ELIGIBILITY FOR ANY PURPOSES. */ +/* (C) Fujitsu Microelectronics Europe GmbH */ +/*--------------------------------------------------------------------------- + __STD_LIB_sbrk.C + - Used by heap_3.c for memory accocation and deletion. + +/*---------------------------------------------------------------------------*/ + +#include "FreeRTOSConfig.h" +#include + + static long brk_siz = 0; +// #if configTOTAL_HEAP_SIZE != 0 + typedef int _heep_t; + #define ROUNDUP(s) (((s)+sizeof(_heep_t)-1)&~(sizeof(_heep_t)-1)) + static _heep_t _heep[ROUNDUP(configTOTAL_HEAP_SIZE)/sizeof(_heep_t)]; + #define _heep_size ROUNDUP(configTOTAL_HEAP_SIZE) +/* #else + extern char *_heep; + extern long _heep_size; + #endif +*/ + extern char *sbrk(int size) + { + if (brk_siz + size > _heep_size || brk_siz + size < 0) + + return((char*)-1); + brk_siz += size; + return( (char*)_heep + brk_siz - size); + } + diff --git a/20080212/Source/portable/Softune/MB96340/port.c b/20080212/Source/portable/Softune/MB96340/port.c new file mode 100644 index 000000000..6ab130b80 --- /dev/null +++ b/20080212/Source/portable/Softune/MB96340/port.c @@ -0,0 +1,589 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#include "FreeRTOS.h" +#include "task.h" +#include "mb96348hs.h" + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the 16FX port. + *----------------------------------------------------------*/ + +/* + * Get current value of DPR and ADB registers + */ +portSTACK_TYPE xGet_DPR_ADB_bank( void ); + +/* + * Get current value of DTB and PCB registers + */ +portSTACK_TYPE xGet_DTB_PCB_bank( void ); + +/* + * Get current register pointer + */ +portCHAR xGet_RP( void ); + +/* + * Sets up the periodic ISR used for the RTOS tick. This uses RLT0, but + * can be done using any given RLT. + */ +static void prvSetupRLT0Interrupt( void ); + +/*-----------------------------------------------------------*/ + +/* + * We require the address of the pxCurrentTCB variable, but don't want to know + * any details of its type. + */ +typedef void tskTCB; +extern volatile tskTCB * volatile pxCurrentTCB; + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( unsigned portBASE_TYPE ) 0 ) +volatile unsigned portBASE_TYPE uxCriticalNesting = 9999UL; + +/*-----------------------------------------------------------*/ + +/* + * Macro to save a task context to the task stack. This macro copies the + * saved context (AH:AL, DPR:ADB, DTB:PCB , PC and PS) from the system + * stack to task stack pointed by user stack pointer ( USP for SMALL and + * MEDIUM memory model amd USB:USP for COMPACT and LARGE memory model ), + * then it pushes the general purpose registers RW0-RW7 on to the task + * stack. Finally the resultant stack pointer value is saved into the + * task control block so it can be retrieved the next time the task + * executes. + */ + +#if( ( configMEMMODEL == portSMALL ) || ( configMEMMODEL == portMEDIUM ) ) + + #define portSAVE_CONTEXT() \ + { __asm(" POPW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" PUSHW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" POPW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" PUSHW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" POPW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" PUSHW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" POPW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" PUSHW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" POPW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" PUSHW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" POPW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" PUSHW A "); \ + __asm(" PUSHW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) "); \ + \ + /* Save the critical nesting count to the stack. */ \ + __asm(" MOVW RW0, _uxCriticalNesting "); \ + __asm(" PUSHW (RW0) "); \ + \ + __asm(" MOVW A, _pxCurrentTCB "); \ + __asm(" MOVW A, SP "); \ + __asm(" SWAPW "); \ + __asm(" MOVW @AL, AH "); \ + __asm(" OR CCR,#H'20 "); \ + } + + /* + * Macro to restore a task context from the task stack. This is effecti- + * vely the reverse of SAVE_CONTEXT(). First the stack pointer value + * (USP for SMALL and MEDIUM memory model amd USB:USP for COMPACT and + * LARGE memory model ) is loaded from the task control block. Next the + * value of all the general purpose registers RW0-RW7 is retrieved. Fina- + * lly it copies of the context ( AH:AL, DPR:ADB, DTB:PCB, PC and PS) of + * the task to be executed upon RETI from user stack to system stack. + */ + + #define portRESTORE_CONTEXT() \ + { __asm(" MOVW A, _pxCurrentTCB "); \ + __asm(" MOVW A, @A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" MOVW SP, A "); \ + \ + /* Load the saved uxCriticalNesting value into RW0. */ \ + __asm(" POPW (RW0) "); \ + \ + /* Save the loaded value into the uxCriticalNesting variable. */ \ + __asm(" MOVW _uxCriticalNesting, RW0 "); \ + \ + __asm(" POPW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) "); \ + __asm(" POPW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" PUSHW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" POPW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" PUSHW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" POPW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" PUSHW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" POPW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" PUSHW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" POPW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" PUSHW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" POPW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" PUSHW A "); \ + } + +#elif (configMEMMODEL == portCOMPACT || configMEMMODEL == portLARGE) + + #define portSAVE_CONTEXT() \ + { __asm(" POPW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" PUSHW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" POPW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" PUSHW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" POPW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" PUSHW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" POPW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" PUSHW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" POPW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" PUSHW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" POPW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" PUSHW A "); \ + __asm(" PUSHW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) "); \ + __asm(" MOVL A, _pxCurrentTCB "); \ + __asm(" MOVL RL2, A "); \ + __asm(" MOVW A, SP "); \ + __asm(" MOVW @RL2+0, A "); \ + __asm(" MOV A, USB "); \ + __asm(" MOV @RL2+2, A "); \ + } + + #define portRESTORE_CONTEXT() \ + { __asm(" MOVL A, _pxCurrentTCB "); \ + __asm(" MOVL RL2, A "); \ + __asm(" MOVW A, @RL2+0 "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" MOVW SP, A "); \ + __asm(" MOV A, @RL2+2 "); \ + __asm(" MOV USB, A "); \ + __asm(" POPW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) "); \ + __asm(" POPW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" PUSHW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" POPW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" PUSHW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" POPW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" PUSHW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" POPW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" PUSHW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" POPW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" PUSHW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" POPW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" PUSHW A "); \ + } +#endif + +/*-----------------------------------------------------------*/ + +/* + * The below are the functions for getting the current value of DPR:ADB, + * DTB:PCB bank registers + */ + +#pragma asm + + .GLOBAL _xGet_DPR_ADB_bank + .GLOBAL _xGet_DTB_PCB_bank + .GLOBAL _xGet_RP + .SECTION CODE, CODE, ALIGN=1 + +_xGet_DPR_ADB_bank: + + MOV A, DPR + SWAP + MOV A, ADB + ORW A + #if configMEMMODEL == portMEDIUM || configMEMMODEL == portLARGE + RETP + #elif configMEMMODEL == portSMALL || configMEMMODEL == portCOMPACT + RET + #endif + + +_xGet_DTB_PCB_bank: + + MOV A, DTB + SWAP + MOV A, PCB + ORW A + #if configMEMMODEL == portMEDIUM || configMEMMODEL == portLARGE + RETP + #elif configMEMMODEL == portSMALL || configMEMMODEL == portCOMPACT + RET + #endif + + +_xGet_RP: + + PUSHW PS + POPW A + SWAP + ANDW A,#0x1f + #if configMEMMODEL == portMEDIUM || configMEMMODEL == portLARGE + RETP + #elif configMEMMODEL == portSMALL || configMEMMODEL == portCOMPACT + RET + #endif + + +#pragma endasm +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See the header file portable.h. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ + /* Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging. */ + *pxTopOfStack = 0x1111; + pxTopOfStack--; + *pxTopOfStack = 0x2222; + pxTopOfStack--; + *pxTopOfStack = 0x3333; + pxTopOfStack--; + + /* Once the task is called the task would push the pointer to the + parameter on to the stack. Hence here the pointer would be copied first + to the stack. In case of COMPACT or LARGE memory model such pointer + would be 24 bit and in case of SMALL or MEDIUM memory model such pointer + would be 16 bit */ + #if( ( configMEMMODEL == portCOMPACT ) || ( configMEMMODEL == portLARGE ) ) + { + *pxTopOfStack = ( portSTACK_TYPE ) ( ( unsigned portLONG ) ( pvParameters ) >> 16 ); + pxTopOfStack--; + } + #endif + + *pxTopOfStack = ( portSTACK_TYPE ) ( pvParameters ); + pxTopOfStack--; + + /* This is redundant push to the stack. This is required in order to introduce + an offset so that the task accesses a parameter correctly that is passed on to + the task stack. */ + #if( ( configMEMMODEL == portMEDIUM ) || ( configMEMMODEL == portLARGE ) ) + { + *pxTopOfStack = ( xGet_DTB_PCB_bank() & 0xff00 ) | ( ( ( portLONG ) ( pxCode ) >> 16 ) & 0xff ); + pxTopOfStack--; + } + #endif + + /* This is redundant push to the stack. This is required in order to introduce + an offset so that the task accesses a parameter correctly that is passed on to + the task stack. */ + *pxTopOfStack = ( portSTACK_TYPE ) ( pxCode ); + pxTopOfStack--; + + /* PS - User Mode, ILM=7, RB=0, Interrupts enabled,USP */ + *pxTopOfStack = 0xE0C0; + pxTopOfStack--; + + /* PC */ + *pxTopOfStack = ( portSTACK_TYPE ) ( pxCode ); + pxTopOfStack--; + + /* DTB | PCB */ + #if configMEMMODEL == portSMALL || configMEMMODEL == portCOMPACT + { + *pxTopOfStack = xGet_DTB_PCB_bank(); + pxTopOfStack--; + } + #endif + + /* DTB | PCB, in case of portMEDIUM or portLARGE memory model PCB would be used + along with PC to indicate the start address of the functiom */ + #if( ( configMEMMODEL == portMEDIUM ) || ( configMEMMODEL == portLARGE ) ) + { + *pxTopOfStack = ( xGet_DTB_PCB_bank() & 0xff00 ) | ( ( ( portLONG ) ( pxCode ) >> 16 ) & 0xff ); + pxTopOfStack--; + } + #endif + + /* DPR | ADB */ + *pxTopOfStack = xGet_DPR_ADB_bank(); + pxTopOfStack--; + + /* AL */ + *pxTopOfStack = ( portSTACK_TYPE ) 0x9999; + pxTopOfStack--; + + /* AH */ + *pxTopOfStack = ( portSTACK_TYPE ) 0xAAAA; + pxTopOfStack--; + + /* Next the general purpose registers. */ + *pxTopOfStack = ( portSTACK_TYPE ) 0x7777; /* RW7 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x6666; /* RW6 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x5555; /* RW5 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x4444; /* RW4 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x3333; /* RW3 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x2222; /* RW2 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x1111; /* RW1 */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x8888; /* RW0 */ + pxTopOfStack--; + + /* The task starts with its uxCriticalNesting variable set to 0, interrupts + being enabled. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvSetupRLT0Interrupt( void ) +{ + /* set reload value = 34999+1, TICK Interrupt after 10 ms @ 56MHz of CLKP1 */ + TMRLR0 = 0x88B7; + + /* prescaler 1:16, reload, interrupt enable, count enable, trigger */ + TMCSR0 = 0x041B; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xPortStartScheduler( void ) +{ + /* Setup the hardware to generate the tick. */ + prvSetupRLT0Interrupt(); + + /* Restore the context of the first task that is going to run. */ + portRESTORE_CONTEXT(); + + /* Simulate a function call end as generated by the compiler. We will now + jump to the start of the task the context of which we have just restored. */ + + __asm(" reti "); + + + /* Should not get here. */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented - unlikely to ever be required as there is nothing to + return to. */ +} + +/*-----------------------------------------------------------*/ + +/* + * The interrupt service routine used depends on whether the pre-emptive + * scheduler is being used or not. + */ + +#if configUSE_PREEMPTION == 1 + + /* + * Tick ISR for preemptive scheduler. We can use a __nosavereg attribute + * as the context would be saved by PortSAVE_CONTEXT(). The tick count + * is incremented after the context is saved. + */ + __nosavereg __interrupt void prvRLT0_TICKISR( void ) + { + /* Disable interrupts so that portSAVE_CONTEXT() is not interrupted */ + __DI(); + + /* Save the context of the interrupted task. */ + portSAVE_CONTEXT(); + + /* Enable interrupts */ + __EI(); + + /* Clear RLT0 interrupt flag */ + TMCSR0_UF = 0; + + /* Increment the tick count then switch to the highest priority task + that is ready to run. */ + vTaskIncrementTick(); + vTaskSwitchContext(); + + /* Disable interrupts so that portRESTORE_CONTEXT() is not interrupted */ + __DI(); + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT(); + + /* Enable interrupts */ + __EI(); + } + +#else + + /* + * Tick ISR for the cooperative scheduler. All this does is increment the + * tick count. We don't need to switch context, this can only be done by + * manual calls to taskYIELD(); + */ + __interrupt void prvRLT0_TICKISR( void ) + { + /* Clear RLT0 interrupt flag */ + TMCSR0_UF = 0; + + vTaskIncrementTick(); + } + +#endif + +/*-----------------------------------------------------------*/ + +/* + * Manual context switch. We can use a __nosavereg attribute as the context + * would be saved by PortSAVE_CONTEXT(). The context is switched and then + * the context of the new task is restored saved. + */ +__nosavereg __interrupt void vPortYield( void ) +{ + /* Save the context of the interrupted task. */ + portSAVE_CONTEXT(); + + /* Switch to the highest priority task that is ready to run. */ + vTaskSwitchContext(); + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +__nosavereg __interrupt void vPortYieldDelayed( void ) +{ + /* Disable interrupts so that portSAVE_CONTEXT() is not interrupted */ + __DI(); + + /* Save the context of the interrupted task. */ + portSAVE_CONTEXT(); + + /* Enable interrupts */ + __EI(); + + /* Clear delayed interrupt flag */ + __asm (" CLRB 03A4H:0 "); + + /* Switch to the highest priority task that is ready to run. */ + vTaskSwitchContext(); + + /* Disable interrupts so that portSAVE_CONTEXT() is not interrupted */ + __DI(); + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT(); + + /* Enable interrupts */ + __EI(); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + /* Disable interrupts */ + portDISABLE_INTERRUPTS(); + + /* Now interrupts are disabled uxCriticalNesting can be accessed + directly. Increment uxCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + uxCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + if( uxCriticalNesting > portNO_CRITICAL_NESTING ) + { + uxCriticalNesting--; + if( uxCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Enable all interrupt/exception. */ + portENABLE_INTERRUPTS(); + } + } +} +/*-----------------------------------------------------------*/ diff --git a/20080212/Source/portable/Softune/MB96340/portmacro.h b/20080212/Source/portable/Softune/MB96340/portmacro.h new file mode 100644 index 000000000..cd7b60fa2 --- /dev/null +++ b/20080212/Source/portable/Softune/MB96340/portmacro.h @@ -0,0 +1,116 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#include "mb96348hs.h" +#include + +#define portSMALL 0 +#define portMEDIUM 1 +#define portCOMPACT 2 +#define portLARGE 3 + + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned portSHORT +#define portBASE_TYPE portSHORT + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +#define portDISABLE_INTERRUPTS() __DI(); +#define portENABLE_INTERRUPTS() __EI(); +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() + +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 2 +#define portNOP() __asm( " NOP " ); +/*-----------------------------------------------------------*/ + +/* portYIELD() uses SW interrupt */ +#define portYIELD() __asm( " INT #122 " ); + +/* portYIELD_FROM_ISR() uses delayed interrupt */ +#define portYIELD_FROM_ISR() __asm( " SETB 03A4H:0 " ); +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#define portMINIMAL_STACK_SIZE configMINIMAL_STACK_SIZE + +/* Remove the inline declaration from within the kernel code. */ +#define inline + +#endif /* PORTMACRO_H */ + diff --git a/20080212/Source/portable/WizC/PIC18/Drivers/Tick/Tick.c b/20080212/Source/portable/WizC/PIC18/Drivers/Tick/Tick.c new file mode 100644 index 000000000..4f32aab7d --- /dev/null +++ b/20080212/Source/portable/WizC/PIC18/Drivers/Tick/Tick.c @@ -0,0 +1,153 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + + ISRcode is pulled inline and portTICKisr() is therefore + deleted from this file. + + + Prescaler logic for Timer1 added to allow for a wider + range of TickRates. + +Changes from V3.0.1 +*/ + +#include +#include + +/* IO port constants. */ +#define portBIT_SET (1) +#define portBIT_CLEAR (0) + +/* + * Hardware setup for the tick. + * We use a compare match on timer1. Depending on MPU-frequency + * and requested tickrate, a prescaled value with a matching + * prescaler are determined. + */ +#define portTIMER_COMPARE_BASE ((APROCFREQ/4)/configTICK_RATE_HZ) + +#if portTIMER_COMPARE_BASE < 0x10000 + #define portTIMER_COMPARE_VALUE (portTIMER_COMPARE_BASE) + #define portTIMER_COMPARE_PS1 (portBIT_CLEAR) + #define portTIMER_COMPARE_PS0 (portBIT_CLEAR) +#elif portTIMER_COMPARE_BASE < 0x20000 + #define portTIMER_COMPARE_VALUE (portTIMER_COMPARE_BASE / 2) + #define portTIMER_COMPARE_PS1 (portBIT_CLEAR) + #define portTIMER_COMPARE_PS0 (portBIT_SET) +#elif portTIMER_COMPARE_BASE < 0x40000 + #define portTIMER_COMPARE_VALUE (portTIMER_COMPARE_BASE / 4) + #define portTIMER_COMPARE_PS1 (portBIT_SET) + #define portTIMER_COMPARE_PS0 (portBIT_CLEAR) +#elif portTIMER_COMPARE_BASE < 0x80000 + #define portTIMER_COMPARE_VALUE (portTIMER_COMPARE_BASE / 8) + #define portTIMER_COMPARE_PS1 (portBIT_SET) + #define portTIMER_COMPARE_PS0 (portBIT_SET) +#else + #error "TickRate out of range" +#endif + +/*-----------------------------------------------------------*/ + +/* + * Setup a timer for a regular tick. + */ +void portSetupTick( void ) +{ + /* + * Interrupts are disabled when this function is called. + */ + + /* + * Setup CCP1 + * Provide the tick interrupt using a compare match on timer1. + */ + + /* + * Set the compare match value. + */ + CCPR1H = ( unsigned portCHAR ) ( ( portTIMER_COMPARE_VALUE >> 8 ) & 0xff ); + CCPR1L = ( unsigned portCHAR ) ( portTIMER_COMPARE_VALUE & 0xff ); + + /* + * Set Compare Special Event Trigger Mode + */ + bCCP1M3 = portBIT_SET; + bCCP1M2 = portBIT_CLEAR; + bCCP1M1 = portBIT_SET; + bCCP1M0 = portBIT_SET; + + /* + * Enable CCP1 interrupt + */ + bCCP1IE = portBIT_SET; + + /* + * We are only going to use the global interrupt bit, so disable + * interruptpriorities and enable peripheral interrupts. + */ + bIPEN = portBIT_CLEAR; + bPEIE = portBIT_SET; + + /* + * Set up timer1 + * It will produce the system tick. + */ + + /* + * Clear the time count + */ + TMR1H = ( unsigned portCHAR ) 0x00; + TMR1L = ( unsigned portCHAR ) 0x00; + + /* + * Setup the timer + */ + bRD16 = portBIT_SET; // 16-bit + bT1CKPS1 = portTIMER_COMPARE_PS1; // prescaler + bT1CKPS0 = portTIMER_COMPARE_PS0; // prescaler + bT1OSCEN = portBIT_SET; // Oscillator enable + bT1SYNC = portBIT_SET; // No external clock sync + bTMR1CS = portBIT_CLEAR; // Internal clock + + bTMR1ON = portBIT_SET; // Start timer1 +} diff --git a/20080212/Source/portable/WizC/PIC18/Drivers/Tick/isrTick.c b/20080212/Source/portable/WizC/PIC18/Drivers/Tick/isrTick.c new file mode 100644 index 000000000..21dcbd27e --- /dev/null +++ b/20080212/Source/portable/WizC/PIC18/Drivers/Tick/isrTick.c @@ -0,0 +1,96 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + + ISRcode pulled inline to reduce stack-usage. + + + Added functionality to only call vTaskSwitchContext() once + when handling multiple interruptsources in a single interruptcall. + + + Filename changed to a .c extension to allow stepping through code + using F7. + +Changes from V3.0.1 +*/ + +/* + * ISR for the tick. + * This increments the tick count and, if using the preemptive scheduler, + * performs a context switch. This must be identical to the manual + * context switch in how it stores the context of a task. + */ + +#ifndef _FREERTOS_DRIVERS_TICK_ISRTICK_C +#define _FREERTOS_DRIVERS_TICK_ISRTICK_C + +{ + /* + * Was the interrupt the SystemClock? + */ + if( bCCP1IF && bCCP1IE ) + { + /* + * Reset the interrupt flag + */ + bCCP1IF = 0; + + /* + * Maintain the tick count. + */ + vTaskIncrementTick(); + + #if configUSE_PREEMPTION == 1 + { + /* + * Ask for a switch to the highest priority task + * that is ready to run. + */ + uxSwitchRequested = pdTRUE; + } + #endif + } +} + +#pragma wizcpp uselib "$__PATHNAME__/Tick.c" + +#endif /* _FREERTOS_DRIVERS_TICK_ISRTICK_C */ diff --git a/20080212/Source/portable/WizC/PIC18/Install.bat b/20080212/Source/portable/WizC/PIC18/Install.bat new file mode 100644 index 000000000..590092856 --- /dev/null +++ b/20080212/Source/portable/WizC/PIC18/Install.bat @@ -0,0 +1,171 @@ +@echo off +cls + +SET PACKAGENAME=the FreeRTOS port for fedC and wizC + +echo. +echo Hello, I'm the installationscript for %PACKAGENAME%. +echo. + +:CHECKFEDC + set FED=C:\Program Files\FED\PIC_C + echo. + echo I'm checking your system for fedC + if not exist "%FED%" goto NOFEDC + echo YES, I found a fedC-installation! + goto FOUNDFED +:NOFEDC + echo I could not find a fedC-installation. + + +:CHECKWIZC + set FED=C:\Program Files\FED\PIXIE + echo. + echo I'm checking your system for wizC + if not exist "%FED%" goto NOWIZC + echo YES, I found a wizC-installation! + goto FOUNDFED +:noWIZC + echo I could not find a wizC-installation. + + +:ERROR + echo. + echo. + echo I could not find a FED C-compiler installation on your system. + echo. + echo Perhaps I got confused because you installed fedC or wizC in a non-default directory. + echo If this is the case, please change the path at the top of this install-script. + echo After that rerun the script and I will be happy to try again. + echo. + goto ENDIT + + +:FOUNDFED + echo. + echo. + + set FEDLIBS=%FED%\Libs + set FEDLIBSUSER=%FEDLIBS%\LibsUser + + if exist "%FEDLIBS%" goto INSTALL + echo The FED installationdirectory "%FED%" + echo contains no Libs subdirectory. This is weird! + echo. + echo Installation is aborted, sorry... + goto ENDIT + + +:INSTALL + echo I am about to install %PACKAGENAME% + echo into directory %FEDLIBSUSER% + echo. + echo Press 'enter' to let me do my thing + echo Press 'ctrl-c' to stop me + pause >nul + echo. + echo Installing... + + +:RESET_READONLY + echo. + echo Removing ReadOnly attributes + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Modules\Croutine.c" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Modules\Port.c" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Modules\List.c" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Modules\Queue.c" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Modules\Tasks.c" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\Tick.c" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\isrTick.c" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Portmacro.h" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Croutine.h" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\List.h" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Portable.h" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Projdefs.h" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Queue.h" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Semphr.h" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Task.h" >nul + attrib -R "%FEDLIBSUSER%\FreeRTOS.h" >nul + echo Done + +:CREATE_DIRECTORIES + echo. + echo Creating directories (if necessary)... + if not exist "%FEDLIBSUSER%" mkdir "%FEDLIBSUSER%" + if not exist "%FEDLIBSUSER%\libFreeRTOS" mkdir "%FEDLIBSUSER%\libFreeRTOS" + if not exist "%FEDLIBSUSER%\libFreeRTOS\Drivers" mkdir "%FEDLIBSUSER%\libFreeRTOS\Drivers" + if not exist "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick" mkdir "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick" + if not exist "%FEDLIBSUSER%\libFreeRTOS\Include" mkdir "%FEDLIBSUSER%\libFreeRTOS\Include" + if not exist "%FEDLIBSUSER%\libFreeRTOS\Modules" mkdir "%FEDLIBSUSER%\libFreeRTOS\Modules" + echo Done + + + echo. + echo Copying Files... +:COPY_MODULES + echo Modules... + copy /V /Y "Port.c" "%FEDLIBSUSER%\libFreeRTOS\Modules\Port.c" >nul + copy /V /Y "..\..\..\Croutine.c" "%FEDLIBSUSER%\libFreeRTOS\Modules\Croutine.c" >nul + copy /V /Y "..\..\..\List.c" "%FEDLIBSUSER%\libFreeRTOS\Modules\List.c" >nul + copy /V /Y "..\..\..\Queue.c" "%FEDLIBSUSER%\libFreeRTOS\Modules\Queue.c" >nul + copy /V /Y "..\..\..\Tasks.c" "%FEDLIBSUSER%\libFreeRTOS\Modules\Tasks.c" >nul + +:COPY_DRIVERS + echo Drivers... + copy /V /Y "Drivers\Tick\Tick.c" "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\Tick.c" >nul + copy /V /Y "Drivers\Tick\isrTick.c" "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\isrTick.c" >nul + +:COPY_HEADERS + echo Headers... + copy /V /Y "portmacro.h" "%FEDLIBSUSER%\libFreeRTOS\Include\Portmacro.h" >nul + copy /V /Y "..\..\..\include\Croutine.h" "%FEDLIBSUSER%\libFreeRTOS\Include\Croutine.h" >nul + copy /V /Y "..\..\..\include\List.h" "%FEDLIBSUSER%\libFreeRTOS\Include\List.h" >nul + copy /V /Y "..\..\..\include\Portable.h" "%FEDLIBSUSER%\libFreeRTOS\Include\Portable.h" >nul + copy /V /Y "..\..\..\include\Projdefs.h" "%FEDLIBSUSER%\libFreeRTOS\Include\Projdefs.h" >nul + copy /V /Y "..\..\..\include\Queue.h" "%FEDLIBSUSER%\libFreeRTOS\Include\Queue.h" >nul + copy /V /Y "..\..\..\include\Semphr.h" "%FEDLIBSUSER%\libFreeRTOS\Include\Semphr.h" >nul + copy /V /Y "..\..\..\include\Task.h" "%FEDLIBSUSER%\libFreeRTOS\Include\Task.h" >nul + copy /V /Y "addFreeRTOS.h" + "..\..\..\include\FreeRTOS.h" "%FEDLIBSUSER%\FreeRTOS.h" >nul + + + echo Done + + +:SET_READONLY + echo. + echo Setting files to ReadOnly + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Modules\Port.c" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Modules\Croutine.c" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Modules\List.c" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Modules\Queue.c" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Modules\Tasks.c" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\Tick.c" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\isrTick.c" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Portmacro.h" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Croutine.h" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\List.h" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Portable.h" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Projdefs.h" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Queue.h" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Semphr.h" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Task.h" >nul + attrib +R "%FEDLIBSUSER%\FreeRTOS.h" >nul + echo Done + + +:FINISHED + echo. + echo The installation of %PACKAGENAME% is completed. + echo. + echo Please review the installation instructions as additional libraries + echo and fedC/wizC configuration settings may be needed for FreeRTOS + echo to function correctly. + + goto ENDIT + + +:ENDIT + echo. + echo. + echo Press 'enter' to close this window + pause >nul diff --git a/20080212/Source/portable/WizC/PIC18/addFreeRTOS.h b/20080212/Source/portable/WizC/PIC18/addFreeRTOS.h new file mode 100644 index 000000000..b57e65540 --- /dev/null +++ b/20080212/Source/portable/WizC/PIC18/addFreeRTOS.h @@ -0,0 +1,68 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + +Changes from V3.0.1 + +Changes from V4.0.1 + Uselib pragma added for Croutine.c +*/ + +/* + * The installation script will automatically prepend this file to the default FreeRTOS.h. + */ + +#ifndef WIZC_FREERTOS_H +#define WIZC_FREERTOS_H + +#pragma noheap +#pragma wizcpp expandnl on +#pragma wizcpp searchpath "$__PATHNAME__/libFreeRTOS/Include/" +#pragma wizcpp uselib "$__PATHNAME__/libFreeRTOS/Modules/Croutine.c" +#pragma wizcpp uselib "$__PATHNAME__/libFreeRTOS/Modules/Tasks.c" +#pragma wizcpp uselib "$__PATHNAME__/libFreeRTOS/Modules/Queue.c" +#pragma wizcpp uselib "$__PATHNAME__/libFreeRTOS/Modules/List.c" +#pragma wizcpp uselib "$__PATHNAME__/libFreeRTOS/Modules/Port.c" + +#endif /* WIZC_FREERTOS_H */ diff --git a/20080212/Source/portable/WizC/PIC18/port.c b/20080212/Source/portable/WizC/PIC18/port.c new file mode 100644 index 000000000..bc4981e2d --- /dev/null +++ b/20080212/Source/portable/WizC/PIC18/port.c @@ -0,0 +1,323 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V3.2.1 + + CallReturn Depth increased from 8 to 10 levels to accomodate wizC/fedC V12. + +Changes from V3.2.0 + + TBLPTRU is now initialised to zero during the initial stack creation of a new task. This solves + an error on devices with more than 64kB ROM. + +Changes from V3.0.0 + + ucCriticalNesting is now initialised to 0x7F to prevent interrupts from being + handled before the scheduler is started. + +Changes from V3.0.1 +*/ + +/* Scheduler include files. */ +#include +#include + +#include + +/*--------------------------------------------------------------------------- + * Implementation of functions defined in portable.h for the WizC PIC18 port. + *---------------------------------------------------------------------------*/ + +/* + * We require the address of the pxCurrentTCB variable, but don't want to + * know any details of its type. + */ +typedef void tskTCB; +extern volatile tskTCB * volatile pxCurrentTCB; + +/* + * Define minimal-stack constants + * ----- + * FSR's: + * STATUS, WREG, BSR, PRODH, PRODL, FSR0H, FSR0L, + * FSR1H, FSR1L,TABLAT, (TBLPTRU), TBLPTRH, TBLPTRL, + * (PCLATU), PCLATH + * sfr's within parenthesis only on devices > 64kB + * ----- + * Call/Return stack: + * 2 bytes per entry on devices <= 64kB + * 3 bytes per entry on devices > 64kB + * ----- + * Other bytes: + * 2 bytes: FunctionParameter for initial taskcode + * 1 byte : Number of entries on call/return stack + * 1 byte : ucCriticalNesting + * 16 bytes: Free space on stack + */ +#if _ROMSIZE > 0x8000 + #define portSTACK_FSR_BYTES ( 15 ) + #define portSTACK_CALLRETURN_ENTRY_SIZE ( 3 ) +#else + #define portSTACK_FSR_BYTES ( 13 ) + #define portSTACK_CALLRETURN_ENTRY_SIZE ( 2 ) +#endif + +#define portSTACK_MINIMAL_CALLRETURN_DEPTH ( 10 ) +#define portSTACK_OTHER_BYTES ( 20 ) + +unsigned portSHORT usCalcMinStackSize = 0; + +/*-----------------------------------------------------------*/ + +/* + * We initialise ucCriticalNesting to the middle value an + * unsigned char can contain. This way portENTER_CRITICAL() + * and portEXIT_CRITICAL() can be called without interrupts + * being enabled before the scheduler starts. + */ +register unsigned portCHAR ucCriticalNesting = 0x7F; + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a new task. + * See portSAVE_CONTEXT macro for description. + */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ +unsigned portCHAR ucScratch; + /* + * Get the size of the RAMarea in page 0 used by the compiler + * We do this here already to avoid W-register conflicts. + */ + _Pragma("asm") + movlw OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE + movwf PRODL,ACCESS ; PRODL is used as temp register + _Pragma("asmend") + ucScratch = PRODL; + + /* + * Place a few bytes of known values on the bottom of the stack. + * This is just useful for debugging. + */ +// *pxTopOfStack-- = 0x11; +// *pxTopOfStack-- = 0x22; +// *pxTopOfStack-- = 0x33; + + /* + * Simulate how the stack would look after a call to vPortYield() + * generated by the compiler. + */ + + /* + * First store the function parameters. This is where the task expects + * to find them when it starts running. + */ + *pxTopOfStack-- = ( portSTACK_TYPE ) ( (( unsigned portSHORT ) pvParameters >> 8) & 0x00ff ); + *pxTopOfStack-- = ( portSTACK_TYPE ) ( ( unsigned portSHORT ) pvParameters & 0x00ff ); + + /* + * Next are all the registers that form part of the task context. + */ + *pxTopOfStack-- = ( portSTACK_TYPE ) 0x11; /* STATUS. */ + *pxTopOfStack-- = ( portSTACK_TYPE ) 0x22; /* WREG. */ + *pxTopOfStack-- = ( portSTACK_TYPE ) 0x33; /* BSR. */ + *pxTopOfStack-- = ( portSTACK_TYPE ) 0x44; /* PRODH. */ + *pxTopOfStack-- = ( portSTACK_TYPE ) 0x55; /* PRODL. */ + *pxTopOfStack-- = ( portSTACK_TYPE ) 0x66; /* FSR0H. */ + *pxTopOfStack-- = ( portSTACK_TYPE ) 0x77; /* FSR0L. */ + *pxTopOfStack-- = ( portSTACK_TYPE ) 0x88; /* FSR1H. */ + *pxTopOfStack-- = ( portSTACK_TYPE ) 0x99; /* FSR1L. */ + *pxTopOfStack-- = ( portSTACK_TYPE ) 0xAA; /* TABLAT. */ +#if _ROMSIZE > 0x8000 + *pxTopOfStack-- = ( portSTACK_TYPE ) 0x00; /* TBLPTRU. */ +#endif + *pxTopOfStack-- = ( portSTACK_TYPE ) 0xCC; /* TBLPTRH. */ + *pxTopOfStack-- = ( portSTACK_TYPE ) 0xDD; /* TBLPTRL. */ +#if _ROMSIZE > 0x8000 + *pxTopOfStack-- = ( portSTACK_TYPE ) 0xEE; /* PCLATU. */ +#endif + *pxTopOfStack-- = ( portSTACK_TYPE ) 0xFF; /* PCLATH. */ + + /* + * Next the compiler's scratchspace. + */ + while(ucScratch-- > 0) + { + *pxTopOfStack-- = ( portSTACK_TYPE ) 0; + } + + /* + * The only function return address so far is the address of the task entry. + * The order is TOSU/TOSH/TOSL. For devices > 64kB, TOSU is put on the + * stack, too. TOSU is always written as zero here because wizC does not allow + * functionpointers to point above 64kB in ROM. + */ +#if _ROMSIZE > 0x8000 + *pxTopOfStack-- = ( portSTACK_TYPE ) 0; +#endif + *pxTopOfStack-- = ( portSTACK_TYPE ) ( ( ( unsigned portSHORT ) pxCode >> 8 ) & 0x00ff ); + *pxTopOfStack-- = ( portSTACK_TYPE ) ( ( unsigned portSHORT ) pxCode & 0x00ff ); + + /* + * Store the number of return addresses on the hardware stack. + * So far only the address of the task entry point. + */ + *pxTopOfStack-- = ( portSTACK_TYPE ) 1; + + /* + * The code generated by wizC does not maintain separate + * stack and frame pointers. Therefore the portENTER_CRITICAL macro cannot + * use the stack as per other ports. Instead a variable is used to keep + * track of the critical section nesting. This variable has to be stored + * as part of the task context and is initially set to zero. + */ + *pxTopOfStack-- = ( portSTACK_TYPE ) portNO_CRITICAL_SECTION_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +unsigned portSHORT usPortCALCULATE_MINIMAL_STACK_SIZE( void ) +{ + /* + * Fetch the size of compiler's scratchspace. + */ + _Pragma("asm") + movlw OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE + movlb usCalcMinStackSize>>8 + movwf usCalcMinStackSize,BANKED + _Pragma("asmend") + + /* + * Add minimum needed stackspace + */ + usCalcMinStackSize += ( portSTACK_FSR_BYTES ) + + ( portSTACK_MINIMAL_CALLRETURN_DEPTH * portSTACK_CALLRETURN_ENTRY_SIZE ) + + ( portSTACK_OTHER_BYTES ); + + return(usCalcMinStackSize); +} + +/*-----------------------------------------------------------*/ + +portBASE_TYPE xPortStartScheduler( void ) +{ + extern void portSetupTick( void ); + + /* + * Setup a timer for the tick ISR for the preemptive scheduler. + */ + portSetupTick(); + + /* + * Restore the context of the first task to run. + */ + portRESTORE_CONTEXT(); + + /* + * This point should never be reached during execution. + */ + return pdTRUE; +} + +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* + * It is unlikely that the scheduler for the PIC port will get stopped + * once running. When called a reset is done which is probably the + * most valid action. + */ + _Pragma(asmline reset); +} + +/*-----------------------------------------------------------*/ + +/* + * Manual context switch. This is similar to the tick context switch, + * but does not increment the tick count. It must be identical to the + * tick context switch in how it stores the stack of a task. + */ +void vPortYield( void ) +{ + /* + * Save the context of the current task. + */ + portSAVE_CONTEXT( portINTERRUPTS_UNCHANGED ); + + /* + * Switch to the highest priority task that is ready to run. + */ + vTaskSwitchContext(); + + /* + * Start executing the task we have just switched to. + */ + portRESTORE_CONTEXT(); +} + +/*-----------------------------------------------------------*/ + +void *pvPortMalloc( unsigned portSHORT usWantedSize ) +{ +void *pvReturn; + + vTaskSuspendAll(); + { + pvReturn = malloc( ( malloc_t ) usWantedSize ); + } + xTaskResumeAll(); + + return pvReturn; +} + +void vPortFree( void *pv ) +{ + if( pv ) + { + vTaskSuspendAll(); + { + free( pv ); + } + xTaskResumeAll(); + } +} diff --git a/20080212/Source/portable/WizC/PIC18/portmacro.h b/20080212/Source/portable/WizC/PIC18/portmacro.h new file mode 100644 index 000000000..dbbce4a11 --- /dev/null +++ b/20080212/Source/portable/WizC/PIC18/portmacro.h @@ -0,0 +1,433 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V3.0.0 + +Changes from V3.0.1 +*/ +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#if !defined(_SERIES) || _SERIES != 18 + #error "WizC supports FreeRTOS on the Microchip PIC18-series only" +#endif + +#if !defined(QUICKCALL) || QUICKCALL != 1 + #error "QuickCall must be enabled (see ProjectOptions/Optimisations)" +#endif + +#include +#include + +#define portCHAR char +#define portFLOAT float +#define portDOUBLE portFLOAT +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned char +#define portBASE_TYPE char + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) ( 0xFFFF ) +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) ( 0xFFFFFFFF ) +#endif + +#define portBYTE_ALIGNMENT 1 + +/*-----------------------------------------------------------*/ + +/* + * Constant used for context switch macro when we require the interrupt + * enable state to be forced when the interrupted task is switched back in. + */ +#define portINTERRUPTS_FORCED (0x01) + +/* + * Constant used for context switch macro when we require the interrupt + * enable state to be unchanged when the interrupted task is switched back in. + */ +#define portINTERRUPTS_UNCHANGED (0x00) + +/* Initial interrupt enable state for newly created tasks. This value is + * used when a task switches in for the first time. + */ +#define portINTERRUPTS_INITIAL_STATE (portINTERRUPTS_FORCED) + +/* + * Macros to modify the global interrupt enable bit in INTCON. + */ +#define portDISABLE_INTERRUPTS() \ + do \ + { \ + bGIE=0; \ + } while(bGIE) // MicroChip recommends this check! + +#define portENABLE_INTERRUPTS() \ + do \ + { \ + bGIE=1; \ + } while(0) + +/*-----------------------------------------------------------*/ + +/* + * Critical section macros. + */ +extern unsigned portCHAR ucCriticalNesting; + +#define portNO_CRITICAL_SECTION_NESTING ( ( unsigned portCHAR ) 0 ) + +#define portENTER_CRITICAL() \ + do \ + { \ + portDISABLE_INTERRUPTS(); \ + \ + /* \ + * Now interrupts are disabled ucCriticalNesting \ + * can be accessed directly. Increment \ + * ucCriticalNesting to keep a count of how \ + * many times portENTER_CRITICAL() has been called. \ + */ \ + ucCriticalNesting++; \ + } while(0) + +#define portEXIT_CRITICAL() \ + do \ + { \ + if(ucCriticalNesting > portNO_CRITICAL_SECTION_NESTING) \ + { \ + /* \ + * Decrement the nesting count as we are leaving a \ + * critical section. \ + */ \ + ucCriticalNesting--; \ + } \ + \ + /* \ + * If the nesting level has reached zero then \ + * interrupts should be re-enabled. \ + */ \ + if( ucCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ + } while(0) + +/*-----------------------------------------------------------*/ + +/* + * The minimal stacksize is calculated on the first reference of + * portMINIMAL_STACK_SIZE. Some input to this calculation is + * compiletime determined, other input is port-defined (see port.c) + */ +extern unsigned portSHORT usPortCALCULATE_MINIMAL_STACK_SIZE( void ); +extern unsigned portSHORT usCalcMinStackSize; + +#define portMINIMAL_STACK_SIZE \ + ((usCalcMinStackSize == 0) \ + ? usPortCALCULATE_MINIMAL_STACK_SIZE() \ + : usCalcMinStackSize ) + +/* + * WizC uses a downgrowing stack + */ +#define portSTACK_GROWTH ( -1 ) + +/*-----------------------------------------------------------*/ + +/* + * Macro's that pushes all the registers that make up the context of a task onto + * the stack, then saves the new top of stack into the TCB. TOSU and TBLPTRU + * are only saved/restored on devices with more than 64kB (32k Words) ROM. + * + * The stackpointer is helt by WizC in FSR2 and points to the first free byte. + * WizC uses a "downgrowing" stack. There is no framepointer. + * + * We keep track of the interruptstatus using ucCriticalNesting. When this + * value equals zero, interrupts have to be enabled upon exit from the + * portRESTORE_CONTEXT macro. + * + * If this is called from an ISR then the interrupt enable bits must have been + * set for the ISR to ever get called. Therefore we want to save + * ucCriticalNesting with value zero. This means the interrupts will again be + * re-enabled when the interrupted task is switched back in. + * + * If this is called from a manual context switch (i.e. from a call to yield), + * then we want to keep the current value of ucCritialNesting so it is restored + * with its current value. This allows a yield from within a critical section. + * + * The compiler uses some locations at the bottom of RAM for temporary + * storage. The compiler may also have been instructed to optimize + * function-parameters and local variables to global storage. The compiler + * uses an area called LocOpt for this wizC feature. + * The total overheadstorage has to be saved in it's entirety as part of + * a task context. These macro's store/restore from data address 0x0000 to + * (OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE - 1). + * OVERHEADPAGE0, LOCOPTSIZE and MAXLOCOPTSIZE are compiler-generated + * assembler definitions. + */ + +#define portSAVE_CONTEXT( ucInterruptForced ) \ + do \ + { \ + portDISABLE_INTERRUPTS(); \ + \ + _Pragma("asm") \ + ; \ + ; Push the relevant SFR's onto the task's stack \ + ; \ + movff STATUS,POSTDEC2 \ + movff WREG,POSTDEC2 \ + movff BSR,POSTDEC2 \ + movff PRODH,POSTDEC2 \ + movff PRODL,POSTDEC2 \ + movff FSR0H,POSTDEC2 \ + movff FSR0L,POSTDEC2 \ + movff FSR1H,POSTDEC2 \ + movff FSR1L,POSTDEC2 \ + movff TABLAT,POSTDEC2 \ + if __ROMSIZE > 0x8000 \ + movff TBLPTRU,POSTDEC2 \ + endif \ + movff TBLPTRH,POSTDEC2 \ + movff TBLPTRL,POSTDEC2 \ + if __ROMSIZE > 0x8000 \ + movff PCLATU,POSTDEC2 \ + endif \ + movff PCLATH,POSTDEC2 \ + ; \ + ; Store the compiler-scratch-area as described above. \ + ; \ + movlw OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE \ + clrf FSR0L,ACCESS \ + clrf FSR0H,ACCESS \ + _rtos_S1: \ + movff POSTINC0,POSTDEC2 \ + decfsz WREG,W,ACCESS \ + SMARTJUMP _rtos_S1 \ + ; \ + ; Save the pic call/return-stack belonging to the \ + ; current task by copying it to the task's software- \ + ; stack. We save the hardware stack pointer (which \ + ; is the number of addresses on the stack) in the \ + ; W-register first because we need it later and it \ + ; is modified in the save-loop by executing pop's. \ + ; After the loop the W-register is stored on the \ + ; stack, too. \ + ; \ + movf STKPTR,W,ACCESS \ + bz _rtos_s3 \ + _rtos_S2: \ + if __ROMSIZE > 0x8000 \ + movff TOSU,POSTDEC2 \ + endif \ + movff TOSH,POSTDEC2 \ + movff TOSL,POSTDEC2 \ + pop \ + tstfsz STKPTR,ACCESS \ + SMARTJUMP _rtos_S2 \ + _rtos_s3: \ + movwf POSTDEC2,ACCESS \ + ; \ + ; Next the value for ucCriticalNesting used by the \ + ; task is stored on the stack. When \ + ; (ucInterruptForced == portINTERRUPTS_FORCED), we save \ + ; it as 0 (portNO_CRITICAL_SECTION_NESTING). \ + ; \ + if ucInterruptForced == portINTERRUPTS_FORCED \ + clrf POSTDEC2,ACCESS \ + else \ + movff ucCriticalNesting,POSTDEC2 \ + endif \ + ; \ + ; Save the new top of the software stack in the TCB. \ + ; \ + movff pxCurrentTCB,FSR0L \ + movff pxCurrentTCB+1,FSR0H \ + movff FSR2L,POSTINC0 \ + movff FSR2H,POSTINC0 \ + _Pragma("asmend") \ + } while(0) + +/************************************************************/ + +/* + * This is the reverse of portSAVE_CONTEXT. + */ +#define portRESTORE_CONTEXT() \ + do \ + { \ + _Pragma("asm") \ + ; \ + ; Set FSR0 to point to pxCurrentTCB->pxTopOfStack. \ + ; \ + movff pxCurrentTCB,FSR0L \ + movff pxCurrentTCB+1,FSR0H \ + ; \ + ; De-reference FSR0 to set the address it holds into \ + ; FSR2 (i.e. *( pxCurrentTCB->pxTopOfStack ) ). FSR2 \ + ; is used by wizC as stackpointer. \ + ; \ + movff POSTINC0,FSR2L \ + movff POSTINC0,FSR2H \ + ; \ + ; Next, the value for ucCriticalNesting used by the \ + ; task is retrieved from the stack. \ + ; \ + movff PREINC2,ucCriticalNesting \ + ; \ + ; Rebuild the pic call/return-stack. The number of \ + ; return addresses is the next item on the task stack. \ + ; Save this number in PRODL. Then fetch the addresses \ + ; and store them on the hardwarestack. \ + ; The datasheets say we can't use movff here... \ + ; \ + movff PREINC2,PRODL // Use PRODL as tempregister \ + clrf STKPTR,ACCESS \ + _rtos_R1: \ + push \ + movf PREINC2,W,ACCESS \ + movwf TOSL,ACCESS \ + movf PREINC2,W,ACCESS \ + movwf TOSH,ACCESS \ + if __ROMSIZE > 0x8000 \ + movf PREINC2,W,ACCESS \ + movwf TOSU,ACCESS \ + else \ + clrf TOSU,ACCESS \ + endif \ + decfsz PRODL,F,ACCESS \ + SMARTJUMP _rtos_R1 \ + ; \ + ; Restore the compiler's working storage area to page 0 \ + ; \ + movlw OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE \ + movwf FSR0L,ACCESS \ + clrf FSR0H,ACCESS \ + _rtos_R2: \ + decf FSR0L,F,ACCESS \ + movff PREINC2,INDF0 \ + tstfsz FSR0L,ACCESS \ + SMARTJUMP _rtos_R2 \ + ; \ + ; Restore the sfr's forming the tasks context. \ + ; We cannot yet restore bsr, w and status because \ + ; we need these registers for a final test. \ + ; \ + movff PREINC2,PCLATH \ + if __ROMSIZE > 0x8000 \ + movff PREINC2,PCLATU \ + else \ + clrf PCLATU,ACCESS \ + endif \ + movff PREINC2,TBLPTRL \ + movff PREINC2,TBLPTRH \ + if __ROMSIZE > 0x8000 \ + movff PREINC2,TBLPTRU \ + else \ + clrf TBLPTRU,ACCESS \ + endif \ + movff PREINC2,TABLAT \ + movff PREINC2,FSR1L \ + movff PREINC2,FSR1H \ + movff PREINC2,FSR0L \ + movff PREINC2,FSR0H \ + movff PREINC2,PRODL \ + movff PREINC2,PRODH \ + ; \ + ; The return from portRESTORE_CONTEXT() depends on \ + ; the value of ucCriticalNesting. When it is zero, \ + ; interrupts need to be enabled. This is done via a \ + ; retfie instruction because we need the \ + ; interrupt-enabling and the return to the restored \ + ; task to be uninterruptable. \ + ; Because bsr, status and W are affected by the test \ + ; they are restored after the test. \ + ; \ + movlb ucCriticalNesting>>8 \ + tstfsz ucCriticalNesting,BANKED \ + SMARTJUMP _rtos_R4 \ + _rtos_R3: \ + movff PREINC2,BSR \ + movff PREINC2,WREG \ + movff PREINC2,STATUS \ + retfie 0 ; Return enabling interrupts \ + _rtos_R4: \ + movff PREINC2,BSR \ + movff PREINC2,WREG \ + movff PREINC2,STATUS \ + return 0 ; Return without affecting interrupts \ + _Pragma("asmend") \ + } while(0) + +/*-----------------------------------------------------------*/ + +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) + +/*-----------------------------------------------------------*/ + +extern void vPortYield( void ); +#define portYIELD() vPortYield() + +#define portNOP() _Pragma("asm") \ + nop \ + _Pragma("asmend") + +/*-----------------------------------------------------------*/ + +#define portTASK_FUNCTION( xFunction, pvParameters ) \ + void pointed xFunction( void *pvParameters ) \ + _Pragma(asmfunc xFunction) + +#define portTASK_FUNCTION_PROTO portTASK_FUNCTION +/*-----------------------------------------------------------*/ + +#define inline +#define volatile +#define register + +#endif /* PORTMACRO_H */ + diff --git a/20080212/Source/portable/oWatcom/16BitDOS/Flsh186/port.c b/20080212/Source/portable/oWatcom/16BitDOS/Flsh186/port.c new file mode 100644 index 000000000..b5194ce77 --- /dev/null +++ b/20080212/Source/portable/oWatcom/16BitDOS/Flsh186/port.c @@ -0,0 +1,265 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V1.00: + + + Call to taskYIELD() from within tick ISR has been replaced by the more + efficient portSWITCH_CONTEXT(). + + ISR function definitions renamed to include the prv prefix. + +Changes from V1.2.0: + + + portRESET_PIC() is now called last thing before the end of the preemptive + tick routine. + +Changes from V2.6.1 + + + Replaced the sUsingPreemption variable with the configUSE_PREEMPTION + macro to be consistent with the later ports. +*/ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the Flashlite 186 + * port. + *----------------------------------------------------------*/ + +#include +#include +#include +#include + +#include "FreeRTOS.h" +#include "task.h" +#include "portasm.h" + +/*lint -e950 Non ANSI reserved words okay in this file only. */ + +#define portTIMER_EOI_TYPE ( 8 ) +#define portRESET_PIC() portOUTPUT_WORD( ( unsigned portSHORT ) 0xff22, portTIMER_EOI_TYPE ) +#define portTIMER_INT_NUMBER 0x12 + +#define portTIMER_1_CONTROL_REGISTER ( ( unsigned portSHORT ) 0xff5e ) +#define portTIMER_0_CONTROL_REGISTER ( ( unsigned portSHORT ) 0xff56 ) +#define portTIMER_INTERRUPT_ENABLE ( ( unsigned portSHORT ) 0x2000 ) + +/* Setup the hardware to generate the required tick frequency. */ +static void prvSetTickFrequency( unsigned portLONG ulTickRateHz ); + +/* Set the hardware back to the state as per before the scheduler started. */ +static void prvExitFunction( void ); + +#if configUSE_PREEMPTION == 1 + /* Tick service routine used by the scheduler when preemptive scheduling is + being used. */ + static void __interrupt __far prvPreemptiveTick( void ); +#else + /* Tick service routine used by the scheduler when cooperative scheduling is + being used. */ + static void __interrupt __far prvNonPreemptiveTick( void ); +#endif + +/* Trap routine used by taskYIELD() to manually cause a context switch. */ +static void __interrupt __far prvYieldProcessor( void ); + +/*lint -e956 File scopes necessary here. */ + +/* Set true when the vectors are set so the scheduler will service the tick. */ +static portSHORT sSchedulerRunning = pdFALSE; + +/* Points to the original routine installed on the vector we use for manual context switches. This is then used to restore the original routine during prvExitFunction(). */ +static void ( __interrupt __far *pxOldSwitchISR )(); + +/* Used to restore the original DOS context when the scheduler is ended. */ +static jmp_buf xJumpBuf; + +/*lint +e956 */ + +/*-----------------------------------------------------------*/ +portBASE_TYPE xPortStartScheduler( void ) +{ + /* This is called with interrupts already disabled. */ + + /* Remember what was on the interrupts we are going to use + so we can put them back later if required. */ + pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER ); + + /* Put our manual switch (yield) function on a known + vector. */ + _dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor ); + + #if configUSE_PREEMPTION == 1 + { + /* Put our tick switch function on the timer interrupt. */ + _dos_setvect( portTIMER_INT_NUMBER, prvPreemptiveTick ); + } + #else + { + /* We want the timer interrupt to just increment the tick count. */ + _dos_setvect( portTIMER_INT_NUMBER, prvNonPreemptiveTick ); + } + #endif + + prvSetTickFrequency( configTICK_RATE_HZ ); + + /* Clean up function if we want to return to DOS. */ + if( setjmp( xJumpBuf ) != 0 ) + { + prvExitFunction(); + sSchedulerRunning = pdFALSE; + } + else + { + sSchedulerRunning = pdTRUE; + + /* Kick off the scheduler by setting up the context of the first task. */ + portFIRST_CONTEXT(); + } + + return sSchedulerRunning; +} +/*-----------------------------------------------------------*/ + +/* The tick ISR used depend on whether or not the preemptive or cooperative +kernel is being used. */ +#if configUSE_PREEMPTION == 1 + static void __interrupt __far prvPreemptiveTick( void ) + { + /* Get the scheduler to update the task states following the tick. */ + vTaskIncrementTick(); + + /* Switch in the context of the next task to be run. */ + portSWITCH_CONTEXT(); + + /* Reset the PIC ready for the next time. */ + portRESET_PIC(); + } +#else + static void __interrupt __far prvNonPreemptiveTick( void ) + { + /* Same as preemptive tick, but the cooperative scheduler is being used + so we don't have to switch in the context of the next task. */ + vTaskIncrementTick(); + portRESET_PIC(); + } +#endif +/*-----------------------------------------------------------*/ + +static void __interrupt __far prvYieldProcessor( void ) +{ + /* Switch in the context of the next task to be run. */ + portSWITCH_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Jump back to the processor state prior to starting the + scheduler. This means we are not going to be using a + task stack frame so the task can be deleted. */ + longjmp( xJumpBuf, 1 ); +} +/*-----------------------------------------------------------*/ + +static void prvExitFunction( void ) +{ +const unsigned portSHORT usTimerDisable = 0x0000; +unsigned portSHORT usTimer0Control; + + /* Interrupts should be disabled here anyway - but no + harm in making sure. */ + portDISABLE_INTERRUPTS(); + if( sSchedulerRunning == pdTRUE ) + { + /* Put back the switch interrupt routines that was in place + before the scheduler started. */ + _dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR ); + } + + /* Disable the timer used for the tick to ensure the scheduler is + not called before restoring interrupts. There was previously nothing + on this timer so there is no old ISR to restore. */ + portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerDisable ); + + /* Restart the DOS tick. */ + usTimer0Control = portINPUT_WORD( portTIMER_0_CONTROL_REGISTER ); + usTimer0Control |= portTIMER_INTERRUPT_ENABLE; + portOUTPUT_WORD( portTIMER_0_CONTROL_REGISTER, usTimer0Control ); + + + portENABLE_INTERRUPTS(); + + /* This will free up all the memory used by the scheduler. + exiting back to dos with INT21 AH=4CH will do this anyway so + it is not necessary to call this. */ + vTaskCleanUpResources(); +} +/*-----------------------------------------------------------*/ + +static void prvSetTickFrequency( unsigned portLONG ulTickRateHz ) +{ +const unsigned portSHORT usMaxCountRegister = 0xff5a; +const unsigned portSHORT usTimerPriorityRegister = 0xff32; +const unsigned portSHORT usTimerEnable = 0xC000; +const unsigned portSHORT usRetrigger = 0x0001; +const unsigned portSHORT usTimerHighPriority = 0x0000; +unsigned portSHORT usTimer0Control; + +/* ( CPU frequency / 4 ) / clock 2 max count [inpw( 0xff62 ) = 7] */ + +const unsigned portLONG ulClockFrequency = 0x7f31a0; + +unsigned portLONG ulTimerCount = ulClockFrequency / ulTickRateHz; + + portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerEnable | portTIMER_INTERRUPT_ENABLE | usRetrigger ); + portOUTPUT_WORD( usMaxCountRegister, ( unsigned portSHORT ) ulTimerCount ); + portOUTPUT_WORD( usTimerPriorityRegister, usTimerHighPriority ); + + /* Stop the DOS tick - don't do this if you want to maintain a TOD clock. */ + usTimer0Control = portINPUT_WORD( portTIMER_0_CONTROL_REGISTER ); + usTimer0Control &= ~portTIMER_INTERRUPT_ENABLE; + portOUTPUT_WORD( portTIMER_0_CONTROL_REGISTER, usTimer0Control ); +} + + +/*lint +e950 */ + diff --git a/20080212/Source/portable/oWatcom/16BitDOS/Flsh186/portmacro.h b/20080212/Source/portable/oWatcom/16BitDOS/Flsh186/portmacro.h new file mode 100644 index 000000000..b02927627 --- /dev/null +++ b/20080212/Source/portable/oWatcom/16BitDOS/Flsh186/portmacro.h @@ -0,0 +1,121 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE long +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE unsigned portSHORT +#define portBASE_TYPE portSHORT + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +void portENTER_CRITICAL( void ); +#pragma aux portENTER_CRITICAL = "pushf" \ + "cli"; + +void portEXIT_CRITICAL( void ); +#pragma aux portEXIT_CRITICAL = "popf"; + +void portDISABLE_INTERRUPTS( void ); +#pragma aux portDISABLE_INTERRUPTS = "cli"; + +void portENABLE_INTERRUPTS( void ); +#pragma aux portENABLE_INTERRUPTS = "sti"; +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portSWITCH_INT_NUMBER 0x80 +#define portYIELD() __asm{ int portSWITCH_INT_NUMBER } +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 2 +#define portINITIAL_SW ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */ +#define portNOP() __asm{ nop } +/*-----------------------------------------------------------*/ + +/* Compiler specifics. */ +#define portINPUT_BYTE( xAddr ) inp( xAddr ) +#define portOUTPUT_BYTE( xAddr, ucValue ) outp( xAddr, ucValue ) +#define portINPUT_WORD( xAddr ) inpw( xAddr ) +#define portOUTPUT_WORD( xAddr, usValue ) outpw( xAddr, usValue ) +#define inline +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/20080212/Source/portable/oWatcom/16BitDOS/PC/port.c b/20080212/Source/portable/oWatcom/16BitDOS/PC/port.c new file mode 100644 index 000000000..528c70734 --- /dev/null +++ b/20080212/Source/portable/oWatcom/16BitDOS/PC/port.c @@ -0,0 +1,321 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V1.00: + + + Call to taskYIELD() from within tick ISR has been replaced by the more + efficient portSWITCH_CONTEXT(). + + ISR function definitions renamed to include the prv prefix. + +Changes from V1.2.0: + + + prvPortResetPIC() is now called last thing before the end of the + preemptive tick routine. + +Changes from V2.6.1 + + + Replaced the sUsingPreemption variable with the configUSE_PREEMPTION + macro to be consistent with the later ports. + +Changes from V4.0.1 + + + Add function prvSetTickFrequencyDefault() to set the DOS tick back to + its proper value when the scheduler exits. +*/ + +#include +#include +#include +#include +#include + +#include "FreeRTOS.h" +#include "task.h" +#include "portasm.h" + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the industrial + * PC port. + *----------------------------------------------------------*/ + +/*lint -e950 Non ANSI reserved words okay in this file only. */ + +#define portTIMER_INT_NUMBER 0x08 + +/* Setup hardware for required tick interrupt rate. */ +static void prvSetTickFrequency( unsigned portLONG ulTickRateHz ); + +/* Restore hardware to as it was prior to starting the scheduler. */ +static void prvExitFunction( void ); + +/* Either chain to the DOS tick (which itself clears the PIC) or clear the PIC +directly. We chain to the DOS tick as close as possible to the standard DOS +tick rate. */ +static void prvPortResetPIC( void ); + +/* The tick ISR used depends on whether the preemptive or cooperative scheduler +is being used. */ +#if configUSE_PREEMPTION == 1 + /* Tick service routine used by the scheduler when preemptive scheduling is + being used. */ + static void __interrupt __far prvPreemptiveTick( void ); +#else + /* Tick service routine used by the scheduler when cooperative scheduling is + being used. */ + static void __interrupt __far prvNonPreemptiveTick( void ); +#endif +/* Trap routine used by taskYIELD() to manually cause a context switch. */ +static void __interrupt __far prvYieldProcessor( void ); + +/* Set the tick frequency back so the floppy drive works correctly when the +scheduler exits. */ +static void prvSetTickFrequencyDefault( void ); + +/*lint -e956 File scopes necessary here. */ + +/* Used to signal when to chain to the DOS tick, and when to just clear the PIC ourselves. */ +static portSHORT sDOSTickCounter; + +/* Set true when the vectors are set so the scheduler will service the tick. */ +static portSHORT sSchedulerRunning = pdFALSE; + +/* Points to the original routine installed on the vector we use for manual context switches. This is then used to restore the original routine during prvExitFunction(). */ +static void ( __interrupt __far *pxOldSwitchISR )(); + +/* Points to the original routine installed on the vector we use to chain to the DOS tick. This is then used to restore the original routine during prvExitFunction(). */ +static void ( __interrupt __far *pxOldSwitchISRPlus1 )(); + +/* Used to restore the original DOS context when the scheduler is ended. */ +static jmp_buf xJumpBuf; + +/*lint +e956 */ + +/*-----------------------------------------------------------*/ +portBASE_TYPE xPortStartScheduler( void ) +{ +pxISR pxOriginalTickISR; + + /* This is called with interrupts already disabled. */ + + /* Remember what was on the interrupts we are going to use + so we can put them back later if required. */ + pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER ); + pxOriginalTickISR = _dos_getvect( portTIMER_INT_NUMBER ); + pxOldSwitchISRPlus1 = _dos_getvect( portSWITCH_INT_NUMBER + 1 ); + + prvSetTickFrequency( configTICK_RATE_HZ ); + + /* Put our manual switch (yield) function on a known + vector. */ + _dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor ); + + /* Put the old tick on a different interrupt number so we can + call it when we want. */ + _dos_setvect( portSWITCH_INT_NUMBER + 1, pxOriginalTickISR ); + + #if configUSE_PREEMPTION == 1 + { + /* Put our tick switch function on the timer interrupt. */ + _dos_setvect( portTIMER_INT_NUMBER, prvPreemptiveTick ); + } + #else + { + /* We want the timer interrupt to just increment the tick count. */ + _dos_setvect( portTIMER_INT_NUMBER, prvNonPreemptiveTick ); + } + #endif + + /* Setup a counter that is used to call the DOS interrupt as close + to it's original frequency as can be achieved given our chosen tick + frequency. */ + sDOSTickCounter = portTICKS_PER_DOS_TICK; + + /* Clean up function if we want to return to DOS. */ + if( setjmp( xJumpBuf ) != 0 ) + { + prvExitFunction(); + sSchedulerRunning = pdFALSE; + } + else + { + sSchedulerRunning = pdTRUE; + + /* Kick off the scheduler by setting up the context of the first task. */ + portFIRST_CONTEXT(); + } + + return sSchedulerRunning; +} +/*-----------------------------------------------------------*/ + +/* The tick ISR used depends on whether the preemptive or cooperative scheduler +is being used. */ +#if configUSE_PREEMPTION == 1 + /* Tick service routine used by the scheduler when preemptive scheduling is + being used. */ + static void __interrupt __far prvPreemptiveTick( void ) + { + /* Get the scheduler to update the task states following the tick. */ + vTaskIncrementTick(); + + /* Switch in the context of the next task to be run. */ + portSWITCH_CONTEXT(); + + /* Reset the PIC ready for the next time. */ + prvPortResetPIC(); + } +#else + static void __interrupt __far prvNonPreemptiveTick( void ) + { + /* Same as preemptive tick, but the cooperative scheduler is being used + so we don't have to switch in the context of the next task. */ + vTaskIncrementTick(); + prvPortResetPIC(); + } +#endif +/*-----------------------------------------------------------*/ + + +static void __interrupt __far prvYieldProcessor( void ) +{ + /* Switch in the context of the next task to be run. */ + portSWITCH_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +static void prvPortResetPIC( void ) +{ + /* We are going to call the DOS tick interrupt at as close a + frequency to the normal DOS tick as possible. */ + + /* WE SHOULD NOT DO THIS IF YIELD WAS CALLED. */ + --sDOSTickCounter; + if( sDOSTickCounter <= 0 ) + { + sDOSTickCounter = ( portSHORT ) portTICKS_PER_DOS_TICK; + __asm{ int portSWITCH_INT_NUMBER + 1 }; + } + else + { + /* Reset the PIC as the DOS tick is not being called to + do it. */ + __asm + { + mov al, 20H + out 20H, al + }; + } +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Jump back to the processor state prior to starting the + scheduler. This means we are not going to be using a + task stack frame so the task can be deleted. */ + longjmp( xJumpBuf, 1 ); +} +/*-----------------------------------------------------------*/ + +static void prvExitFunction( void ) +{ +void ( __interrupt __far *pxOriginalTickISR )(); + + /* Interrupts should be disabled here anyway - but no + harm in making sure. */ + portDISABLE_INTERRUPTS(); + if( sSchedulerRunning == pdTRUE ) + { + /* Set the DOS tick back onto the timer ticker. */ + pxOriginalTickISR = _dos_getvect( portSWITCH_INT_NUMBER + 1 ); + _dos_setvect( portTIMER_INT_NUMBER, pxOriginalTickISR ); + prvSetTickFrequencyDefault(); + + /* Put back the switch interrupt routines that was in place + before the scheduler started. */ + _dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR ); + _dos_setvect( portSWITCH_INT_NUMBER + 1, pxOldSwitchISRPlus1 ); + } + /* The tick timer is back how DOS wants it. We can re-enable + interrupts without the scheduler being called. */ + portENABLE_INTERRUPTS(); + + /* This will free up all the memory used by the scheduler. + exiting back to dos with INT21 AH=4CH will do this anyway so + it is not necessary to call this. */ + vTaskCleanUpResources(); +} +/*-----------------------------------------------------------*/ + +static void prvSetTickFrequency( unsigned portLONG ulTickRateHz ) +{ +const unsigned portSHORT usPIT_MODE = ( unsigned portSHORT ) 0x43; +const unsigned portSHORT usPIT0 = ( unsigned portSHORT ) 0x40; +const unsigned portLONG ulPIT_CONST = ( unsigned portLONG ) 1193180; +const unsigned portSHORT us8254_CTR0_MODE3 = ( unsigned portSHORT ) 0x36; +unsigned portLONG ulOutput; + + /* Setup the 8245 to tick at the wanted frequency. */ + portOUTPUT_BYTE( usPIT_MODE, us8254_CTR0_MODE3 ); + ulOutput = ulPIT_CONST / ulTickRateHz; + + portOUTPUT_BYTE( usPIT0, ( unsigned portSHORT )( ulOutput & ( unsigned portLONG ) 0xff ) ); + ulOutput >>= 8; + portOUTPUT_BYTE( usPIT0, ( unsigned portSHORT ) ( ulOutput & ( unsigned portLONG ) 0xff ) ); +} +/*-----------------------------------------------------------*/ + +static void prvSetTickFrequencyDefault( void ) +{ +const unsigned portSHORT usPIT_MODE = ( unsigned portSHORT ) 0x43; +const unsigned portSHORT usPIT0 = ( unsigned portSHORT ) 0x40; +const unsigned portSHORT us8254_CTR0_MODE3 = ( unsigned portSHORT ) 0x36; + + portOUTPUT_BYTE( usPIT_MODE, us8254_CTR0_MODE3 ); + portOUTPUT_BYTE( usPIT0,0 ); + portOUTPUT_BYTE( usPIT0,0 ); +} + + +/*lint +e950 */ + diff --git a/20080212/Source/portable/oWatcom/16BitDOS/PC/portmacro.h b/20080212/Source/portable/oWatcom/16BitDOS/PC/portmacro.h new file mode 100644 index 000000000..0d92d839e --- /dev/null +++ b/20080212/Source/portable/oWatcom/16BitDOS/PC/portmacro.h @@ -0,0 +1,119 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE unsigned portSHORT +#define portBASE_TYPE portSHORT + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned portSHORT portTickType; + #define portMAX_DELAY ( portTickType ) 0xffff +#else + typedef unsigned portLONG portTickType; + #define portMAX_DELAY ( portTickType ) 0xffffffff +#endif +/*-----------------------------------------------------------*/ + +/* Critical section definitions. */ +void portENTER_CRITICAL( void ); +#pragma aux portENTER_CRITICAL = "pushf" \ + "cli"; +void portEXIT_CRITICAL( void ); +#pragma aux portEXIT_CRITICAL = "popf"; + +void portDISABLE_INTERRUPTS( void ); +#pragma aux portDISABLE_INTERRUPTS = "cli"; + +void portENABLE_INTERRUPTS( void ); +#pragma aux portENABLE_INTERRUPTS = "sti"; +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portSWITCH_INT_NUMBER 0x80 +#define portYIELD() __asm{ int portSWITCH_INT_NUMBER } +#define portDOS_TICK_RATE ( 18.20648 ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portTICKS_PER_DOS_TICK ( ( unsigned portSHORT ) ( ( ( portDOUBLE ) configTICK_RATE_HZ / portDOS_TICK_RATE ) + 0.5 ) ) +#define portINITIAL_SW ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */ +/*-----------------------------------------------------------*/ + +/* Compiler specifics. */ +#define portINPUT_BYTE( xAddr ) inp( xAddr ) +#define portOUTPUT_BYTE( xAddr, ucValue ) outp( xAddr, ucValue ) +#define inline +#define portNOP() __asm{ nop } +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vTaskFunction, pvParameters ) void vTaskFunction( void *pvParameters ) +#define portTASK_FUNCTION( vTaskFunction, pvParameters ) void vTaskFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif + + +#endif /* PORTMACRO_H */ + diff --git a/20080212/Source/portable/oWatcom/16BitDOS/common/portasm.h b/20080212/Source/portable/oWatcom/16BitDOS/common/portasm.h new file mode 100644 index 000000000..8566a7b75 --- /dev/null +++ b/20080212/Source/portable/oWatcom/16BitDOS/common/portasm.h @@ -0,0 +1,125 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +typedef void tskTCB; +extern volatile tskTCB * volatile pxCurrentTCB; +extern void vTaskSwitchContext( void ); + +/* + * Saves the stack pointer for one task into its TCB, calls + * vTaskSwitchContext() to update the TCB being used, then restores the stack + * from the new TCB read to run the task. + */ +void portSWITCH_CONTEXT( void ); + +/* + * Load the stack pointer from the TCB of the task which is going to be first + * to execute. Then force an IRET so the registers and IP are popped off the + * stack. + */ +void portFIRST_CONTEXT( void ); + +/* There are slightly different versions depending on whether you are building +to include debugger information. If debugger information is used then there +are a couple of extra bytes left of the ISR stack (presumably for use by the +debugger). The true stack pointer is then stored in the bp register. We add +2 to the stack pointer to remove the extra bytes before we restore our context. */ + +#ifdef DEBUG_BUILD + + #pragma aux portSWITCH_CONTEXT = "mov ax, seg pxCurrentTCB" \ + "mov ds, ax" \ + "les bx, pxCurrentTCB" /* Save the stack pointer into the TCB. */ \ + "mov es:0x2[ bx ], ss" \ + "mov es:[ bx ], sp" \ + "call vTaskSwitchContext" /* Perform the switch. */ \ + "mov ax, seg pxCurrentTCB" /* Restore the stack pointer from the TCB. */ \ + "mov ds, ax" \ + "les bx, dword ptr pxCurrentTCB" \ + "mov ss, es:[ bx + 2 ]" \ + "mov sp, es:[ bx ]" \ + "mov bp, sp" /* Prepair the bp register for the restoration of the SP in the compiler generated portion of the ISR */ \ + "add bp, 0x0002" + + + + #pragma aux portFIRST_CONTEXT = "mov ax, seg pxCurrentTCB" \ + "mov ds, ax" \ + "les bx, dword ptr pxCurrentTCB" \ + "mov ss, es:[ bx + 2 ]" \ + "mov sp, es:[ bx ]" \ + "add sp, 0x0002" /* Remove the extra bytes that exist in debug builds before restoring the context. */ \ + "pop ax" \ + "pop ax" \ + "pop es" \ + "pop ds" \ + "popa" \ + "iret" +#else + + #pragma aux portSWITCH_CONTEXT = "mov ax, seg pxCurrentTCB" \ + "mov ds, ax" \ + "les bx, pxCurrentTCB" /* Save the stack pointer into the TCB. */ \ + "mov es:0x2[ bx ], ss" \ + "mov es:[ bx ], sp" \ + "call vTaskSwitchContext" /* Perform the switch. */ \ + "mov ax, seg pxCurrentTCB" /* Restore the stack pointer from the TCB. */ \ + "mov ds, ax" \ + "les bx, dword ptr pxCurrentTCB" \ + "mov ss, es:[ bx + 2 ]" \ + "mov sp, es:[ bx ]" + + + #pragma aux portFIRST_CONTEXT = "mov ax, seg pxCurrentTCB" \ + "mov ds, ax" \ + "les bx, dword ptr pxCurrentTCB" \ + "mov ss, es:[ bx + 2 ]" \ + "mov sp, es:[ bx ]" \ + "pop ax" \ + "pop ax" \ + "pop es" \ + "pop ds" \ + "popa" \ + "iret" +#endif + + diff --git a/20080212/Source/portable/oWatcom/16BitDOS/common/portcomn.c b/20080212/Source/portable/oWatcom/16BitDOS/common/portcomn.c new file mode 100644 index 000000000..48e76b171 --- /dev/null +++ b/20080212/Source/portable/oWatcom/16BitDOS/common/portcomn.c @@ -0,0 +1,156 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V1.00: + + + pxPortInitialiseStack() now initialises the stack of new tasks to the + same format used by the compiler. This allows the compiler generated + interrupt mechanism to be used for context switches. + +Changes from V2.4.2: + + + pvPortMalloc and vPortFree have been removed. The projects now use + the definitions from the source/portable/MemMang directory. + +Changes from V2.6.1: + + + usPortCheckFreeStackSpace() has been moved to tasks.c. +*/ + + + +#include +#include "FreeRTOS.h" + +/*-----------------------------------------------------------*/ + +/* See header file for description. */ +portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) +{ +portSTACK_TYPE DS_Reg = 0, *pxOriginalSP; + + /* Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging. */ + + *pxTopOfStack = 0x1111; + pxTopOfStack--; + *pxTopOfStack = 0x2222; + pxTopOfStack--; + *pxTopOfStack = 0x3333; + pxTopOfStack--; + *pxTopOfStack = 0x4444; + pxTopOfStack--; + *pxTopOfStack = 0x5555; + pxTopOfStack--; + + + /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */ + + /* We are going to start the scheduler using a return from interrupt + instruction to load the program counter, so first there would be the + status register and interrupt return address. We make this the start + of the task. */ + *pxTopOfStack = portINITIAL_SW; + pxTopOfStack--; + *pxTopOfStack = FP_SEG( pxCode ); + pxTopOfStack--; + *pxTopOfStack = FP_OFF( pxCode ); + pxTopOfStack--; + + /* We are going to setup the stack for the new task to look like + the stack frame was setup by a compiler generated ISR. We need to know + the address of the existing stack top to place in the SP register within + the stack frame. pxOriginalSP holds SP before (simulated) pusha was + called. */ + pxOriginalSP = pxTopOfStack; + + /* The remaining registers would be pushed on the stack by our context + switch function. These are loaded with values simply to make debugging + easier. */ + *pxTopOfStack = FP_OFF( pvParameters ); /* AX */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xCCCC; /* CX */ + pxTopOfStack--; + *pxTopOfStack = FP_SEG( pvParameters ); /* DX */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xBBBB; /* BX */ + pxTopOfStack--; + *pxTopOfStack = FP_OFF( pxOriginalSP ); /* SP */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xBBBB; /* BP */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0x0123; /* SI */ + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xDDDD; /* DI */ + + /* We need the true data segment. */ + __asm{ MOV DS_Reg, DS }; + + pxTopOfStack--; + *pxTopOfStack = DS_Reg; /* DS */ + + pxTopOfStack--; + *pxTopOfStack = ( portSTACK_TYPE ) 0xEEEE; /* ES */ + + /* The AX register is pushed again twice - don't know why. */ + pxTopOfStack--; + *pxTopOfStack = FP_OFF( pvParameters ); /* AX */ + pxTopOfStack--; + *pxTopOfStack = FP_OFF( pvParameters ); /* AX */ + + + #ifdef DEBUG_BUILD + /* The compiler adds space to each ISR stack if building to + include debug information. Presumably this is used by the + debugger - we don't need to initialise it to anything just + make sure it is there. */ + pxTopOfStack--; + #endif + + /*lint +e950 +e611 +e923 */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + + diff --git a/20080212/Source/portable/readme.txt b/20080212/Source/portable/readme.txt new file mode 100644 index 000000000..a20d687e0 --- /dev/null +++ b/20080212/Source/portable/readme.txt @@ -0,0 +1,19 @@ +Each real time kernel port consists of three files that contain the core kernel +components and are common to every port, and one or more files that are +specific to a particular microcontroller and/or compiler. + + ++ The FreeRTOS/Source/Portable/MemMang directory contains the three sample +memory allocators as described on the http://www.FreeRTOS.org WEB site. + ++ The other directories each contain files specific to a particular +microcontroller or compiler. + + + +For example, if you are interested in the GCC port for the ATMega323 +microcontroller then the port specific files are contained in +FreeRTOS/Source/Portable/GCC/ATMega323 directory. If this is the only +port you are interested in then all the other directories can be +ignored. + diff --git a/20080212/Source/queue.c b/20080212/Source/queue.c new file mode 100644 index 000000000..dd5ec8649 --- /dev/null +++ b/20080212/Source/queue.c @@ -0,0 +1,1322 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +#include +#include +#include "FreeRTOS.h" +#include "task.h" +#include "croutine.h" + +/*----------------------------------------------------------- + * PUBLIC LIST API documented in list.h + *----------------------------------------------------------*/ + +/* Constants used with the cRxLock and cTxLock structure members. */ +#define queueUNLOCKED ( ( signed portBASE_TYPE ) -1 ) +#define queueERRONEOUS_UNBLOCK ( -1 ) + +/* For internal use only. */ +#define queueSEND_TO_BACK ( 0 ) +#define queueSEND_TO_FRONT ( 1 ) + +/* Effectively make a union out of the xQUEUE structure. */ +#define pxMutexHolder pcTail +#define uxQueueType pcHead +#define uxRecursiveCallCount pcReadFrom +#define queueQUEUE_IS_MUTEX NULL + +/* Semaphores do not actually store or copy data, so have an items size of +zero. */ +#define queueSEMAPHORE_QUEUE_ITEM_LENGTH ( 0 ) +#define queueDONT_BLOCK ( ( portTickType ) 0 ) +#define queueMUTEX_GIVE_BLOCK_TIME ( ( portTickType ) 0 ) +/* + * Definition of the queue used by the scheduler. + * Items are queued by copy, not reference. + */ +typedef struct QueueDefinition +{ + signed portCHAR *pcHead; /*< Points to the beginning of the queue storage area. */ + signed portCHAR *pcTail; /*< Points to the byte at the end of the queue storage area. Once more byte is allocated than necessary to store the queue items, this is used as a marker. */ + + signed portCHAR *pcWriteTo; /*< Points to the free next place in the storage area. */ + signed portCHAR *pcReadFrom; /*< Points to the last place that a queued item was read from. */ + + xList xTasksWaitingToSend; /*< List of tasks that are blocked waiting to post onto this queue. Stored in priority order. */ + xList xTasksWaitingToReceive; /*< List of tasks that are blocked waiting to read from this queue. Stored in priority order. */ + + volatile unsigned portBASE_TYPE uxMessagesWaiting;/*< The number of items currently in the queue. */ + unsigned portBASE_TYPE uxLength; /*< The length of the queue defined as the number of items it will hold, not the number of bytes. */ + unsigned portBASE_TYPE uxItemSize; /*< The size of each items that the queue will hold. */ + + signed portBASE_TYPE xRxLock; /*< Stores the number of items received from the queue (removed from the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */ + signed portBASE_TYPE xTxLock; /*< Stores the number of items transmitted to the queue (added to the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */ +} xQUEUE; +/*-----------------------------------------------------------*/ + +/* + * Inside this file xQueueHandle is a pointer to a xQUEUE structure. + * To keep the definition private the API header file defines it as a + * pointer to void. + */ +typedef xQUEUE * xQueueHandle; + +/* + * Prototypes for public functions are included here so we don't have to + * include the API header file (as it defines xQueueHandle differently). These + * functions are documented in the API header file. + */ +xQueueHandle xQueueCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize ); +signed portBASE_TYPE xQueueGenericSend( xQueueHandle xQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition ); +unsigned portBASE_TYPE uxQueueMessagesWaiting( const xQueueHandle pxQueue ); +void vQueueDelete( xQueueHandle xQueue ); +signed portBASE_TYPE xQueueGenericSendFromISR( xQueueHandle pxQueue, const void * const pvItemToQueue, signed portBASE_TYPE xTaskPreviouslyWoken, portBASE_TYPE xCopyPosition ); +signed portBASE_TYPE xQueueGenericReceive( xQueueHandle pxQueue, const void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking ); +signed portBASE_TYPE xQueueReceiveFromISR( xQueueHandle pxQueue, const void * const pvBuffer, signed portBASE_TYPE *pxTaskWoken ); +xQueueHandle xQueueCreateMutex( void ); +xQueueHandle xQueueCreateCountingSemaphore( unsigned portBASE_TYPE uxCountValue, unsigned portBASE_TYPE uxInitialCount ); +portBASE_TYPE xQueueTakeMutexRecursive( xQueueHandle xMutex, portTickType xBlockTime ); +portBASE_TYPE xQueueGiveMutexRecursive( xQueueHandle xMutex ); +signed portBASE_TYPE xQueueAltGenericSend( xQueueHandle pxQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition ); +signed portBASE_TYPE xQueueAltGenericReceive( xQueueHandle pxQueue, const void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking ); + +#if configUSE_CO_ROUTINES == 1 + signed portBASE_TYPE xQueueCRSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xCoRoutinePreviouslyWoken ); + signed portBASE_TYPE xQueueCRReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken ); + signed portBASE_TYPE xQueueCRSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait ); + signed portBASE_TYPE xQueueCRReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait ); +#endif + +/* + * Unlocks a queue locked by a call to prvLockQueue. Locking a queue does not + * prevent an ISR from adding or removing items to the queue, but does prevent + * an ISR from removing tasks from the queue event lists. If an ISR finds a + * queue is locked it will instead increment the appropriate queue lock count + * to indicate that a task may require unblocking. When the queue in unlocked + * these lock counts are inspected, and the appropriate action taken. + */ +static void prvUnlockQueue( xQueueHandle pxQueue ); + +/* + * Uses a critical section to determine if there is any data in a queue. + * + * @return pdTRUE if the queue contains no items, otherwise pdFALSE. + */ +static signed portBASE_TYPE prvIsQueueEmpty( const xQueueHandle pxQueue ); + +/* + * Uses a critical section to determine if there is any space in a queue. + * + * @return pdTRUE if there is no space, otherwise pdFALSE; + */ +static signed portBASE_TYPE prvIsQueueFull( const xQueueHandle pxQueue ); + +/* + * Copies an item into the queue, either at the front of the queue or the + * back of the queue. + */ +static void prvCopyDataToQueue( xQUEUE *pxQueue, const void *pvItemToQueue, portBASE_TYPE xPosition ); + +/* + * Copies an item out of a queue. + */ +static void prvCopyDataFromQueue( xQUEUE * const pxQueue, const void *pvBuffer ); +/*-----------------------------------------------------------*/ + +/* + * Macro to mark a queue as locked. Locking a queue prevents an ISR from + * accessing the queue event lists. + */ +#define prvLockQueue( pxQueue ) \ +{ \ + taskENTER_CRITICAL(); \ + ++( pxQueue->xRxLock ); \ + ++( pxQueue->xTxLock ); \ + taskEXIT_CRITICAL(); \ +} +/*-----------------------------------------------------------*/ + + +/*----------------------------------------------------------- + * PUBLIC QUEUE MANAGEMENT API documented in queue.h + *----------------------------------------------------------*/ + +xQueueHandle xQueueCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize ) +{ +xQUEUE *pxNewQueue; +size_t xQueueSizeInBytes; + + /* Allocate the new queue structure. */ + if( uxQueueLength > ( unsigned portBASE_TYPE ) 0 ) + { + pxNewQueue = ( xQUEUE * ) pvPortMalloc( sizeof( xQUEUE ) ); + if( pxNewQueue != NULL ) + { + /* Create the list of pointers to queue items. The queue is one byte + longer than asked for to make wrap checking easier/faster. */ + xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ) + ( size_t ) 1; + + pxNewQueue->pcHead = ( signed portCHAR * ) pvPortMalloc( xQueueSizeInBytes ); + if( pxNewQueue->pcHead != NULL ) + { + /* Initialise the queue members as described above where the + queue type is defined. */ + pxNewQueue->pcTail = pxNewQueue->pcHead + ( uxQueueLength * uxItemSize ); + pxNewQueue->uxMessagesWaiting = 0; + pxNewQueue->pcWriteTo = pxNewQueue->pcHead; + pxNewQueue->pcReadFrom = pxNewQueue->pcHead + ( ( uxQueueLength - 1 ) * uxItemSize ); + pxNewQueue->uxLength = uxQueueLength; + pxNewQueue->uxItemSize = uxItemSize; + pxNewQueue->xRxLock = queueUNLOCKED; + pxNewQueue->xTxLock = queueUNLOCKED; + + /* Likewise ensure the event queues start with the correct state. */ + vListInitialise( &( pxNewQueue->xTasksWaitingToSend ) ); + vListInitialise( &( pxNewQueue->xTasksWaitingToReceive ) ); + + return pxNewQueue; + } + else + { + vPortFree( pxNewQueue ); + } + } + } + + /* Will only reach here if we could not allocate enough memory or no memory + was required. */ + return NULL; +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_MUTEXES == 1 ) + + xQueueHandle xQueueCreateMutex( void ) + { + xQUEUE *pxNewQueue; + + /* Allocate the new queue structure. */ + pxNewQueue = ( xQUEUE * ) pvPortMalloc( sizeof( xQUEUE ) ); + if( pxNewQueue != NULL ) + { + /* Information required for priority inheritance. */ + pxNewQueue->pxMutexHolder = NULL; + pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX; + + /* Queues used as a mutex no data is actually copied into or out + of the queue. */ + pxNewQueue->pcWriteTo = NULL; + pxNewQueue->pcReadFrom = NULL; + + /* Each mutex has a length of 1 (like a binary semaphore) and + an item size of 0 as nothing is actually copied into or out + of the mutex. */ + pxNewQueue->uxMessagesWaiting = 0; + pxNewQueue->uxLength = 1; + pxNewQueue->uxItemSize = 0; + pxNewQueue->xRxLock = queueUNLOCKED; + pxNewQueue->xTxLock = queueUNLOCKED; + + /* Ensure the event queues start with the correct state. */ + vListInitialise( &( pxNewQueue->xTasksWaitingToSend ) ); + vListInitialise( &( pxNewQueue->xTasksWaitingToReceive ) ); + + /* Start with the semaphore in the expected state. */ + xQueueGenericSend( pxNewQueue, NULL, 0, queueSEND_TO_BACK ); + } + + return pxNewQueue; + } + +#endif /* configUSE_MUTEXES */ +/*-----------------------------------------------------------*/ + +#if configUSE_RECURSIVE_MUTEXES == 1 + + portBASE_TYPE xQueueGiveMutexRecursive( xQueueHandle pxMutex ) + { + portBASE_TYPE xReturn; + + /* If this is the task that holds the mutex then pxMutexHolder will not + change outside of this task. If this task does not hold the mutex then + pxMutexHolder can never coincidentally equal the tasks handle, and as + this is the only condition we are interested in it does not matter if + pxMutexHolder is accessed simultaneously by another task. Therefore no + mutual exclusion is required to test the pxMutexHolder variable. */ + if( pxMutex->pxMutexHolder == xTaskGetCurrentTaskHandle() ) + { + /* uxRecursiveCallCount cannot be zero if pxMutexHolder is equal to + the task handle, therefore no underflow check is required. Also, + uxRecursiveCallCount is only modified by the mutex holder, and as + there can only be one, no mutual exclusion is required to modify the + uxRecursiveCallCount member. */ + ( pxMutex->uxRecursiveCallCount )--; + + /* Have we unwound the call count? */ + if( pxMutex->uxRecursiveCallCount == 0 ) + { + /* Return the mutex. This will automatically unblock any other + task that might be waiting to access the mutex. */ + xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK ); + } + + xReturn = pdPASS; + } + else + { + /* We cannot give the mutex because we are not the holder. */ + xReturn = pdFAIL; + } + + return xReturn; + } + +#endif /* configUSE_RECURSIVE_MUTEXES */ +/*-----------------------------------------------------------*/ + +#if configUSE_RECURSIVE_MUTEXES == 1 + + portBASE_TYPE xQueueTakeMutexRecursive( xQueueHandle pxMutex, portTickType xBlockTime ) + { + portBASE_TYPE xReturn; + + /* Comments regarding mutual exclusion as per those within + xQueueGiveMutexRecursive(). */ + + if( pxMutex->pxMutexHolder == xTaskGetCurrentTaskHandle() ) + { + ( pxMutex->uxRecursiveCallCount )++; + xReturn = pdPASS; + } + else + { + xReturn = xQueueGenericReceive( pxMutex, NULL, xBlockTime, pdFALSE ); + + /* pdPASS will only be returned if we successfully obtained the mutex, + we may have blocked to reach here. */ + if( xReturn == pdPASS ) + { + ( pxMutex->uxRecursiveCallCount )++; + } + } + + return xReturn; + } + +#endif /* configUSE_RECURSIVE_MUTEXES */ +/*-----------------------------------------------------------*/ + +#if configUSE_COUNTING_SEMAPHORES == 1 + + xQueueHandle xQueueCreateCountingSemaphore( unsigned portBASE_TYPE uxCountValue, unsigned portBASE_TYPE uxInitialCount ) + { + xQueueHandle pxHandle; + + pxHandle = xQueueCreate( ( unsigned portBASE_TYPE ) uxCountValue, queueSEMAPHORE_QUEUE_ITEM_LENGTH ); + + if( pxHandle != NULL ) + { + pxHandle->uxMessagesWaiting = uxInitialCount; + } + + return pxHandle; + } + +#endif /* configUSE_COUNTING_SEMAPHORES */ +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xQueueGenericSend( xQueueHandle pxQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition ) +{ +signed portBASE_TYPE xReturn = pdPASS; +xTimeOutType xTimeOut; + + /* Make sure other tasks do not access the queue. */ + vTaskSuspendAll(); + + /* Capture the current time status for future reference. */ + vTaskSetTimeOutState( &xTimeOut ); + + /* It is important that this is the only thread/ISR that modifies the + ready or delayed lists until xTaskResumeAll() is called. Places where + the ready/delayed lists are modified include: + + + vTaskDelay() - Nothing can call vTaskDelay as the scheduler is + suspended, vTaskDelay() cannot be called from an ISR. + + vTaskPrioritySet() - Has a critical section around the access. + + vTaskSwitchContext() - This will not get executed while the scheduler + is suspended. + + prvCheckDelayedTasks() - This will not get executed while the + scheduler is suspended. + + xTaskCreate() - Has a critical section around the access. + + vTaskResume() - Has a critical section around the access. + + xTaskResumeAll() - Has a critical section around the access. + + xTaskRemoveFromEventList - Checks to see if the scheduler is + suspended. If so then the TCB being removed from the event is + removed from the event and added to the xPendingReadyList. + */ + + /* Make sure interrupts do not access the queue event list. */ + prvLockQueue( pxQueue ); + + /* It is important that interrupts to not access the event list of the + queue being modified here. Places where the event list is modified + include: + + + xQueueGenericSendFromISR(). This checks the lock on the queue to see + if it has access. If the queue is locked then the Tx lock count is + incremented to signify that a task waiting for data can be made ready + once the queue lock is removed. If the queue is not locked then + a task can be moved from the event list, but will not be removed + from the delayed list or placed in the ready list until the scheduler + is unlocked. + + + xQueueReceiveFromISR(). As per xQueueGenericSendFromISR(). + */ + + /* If the queue is already full we may have to block. */ + do + { + if( prvIsQueueFull( pxQueue ) ) + { + /* The queue is full - do we want to block or just leave without + posting? */ + if( xTicksToWait > ( portTickType ) 0 ) + { + /* We are going to place ourselves on the xTasksWaitingToSend event + list, and will get woken should the delay expire, or space become + available on the queue. + + As detailed above we do not require mutual exclusion on the event + list as nothing else can modify it or the ready lists while we + have the scheduler suspended and queue locked. + + It is possible that an ISR has removed data from the queue since we + checked if any was available. If this is the case then the data + will have been copied from the queue, and the queue variables + updated, but the event list will not yet have been checked to see if + anything is waiting as the queue is locked. */ + vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait ); + + /* Force a context switch now as we are blocked. We can do + this from within a critical section as the task we are + switching to has its own context. When we return here (i.e. we + unblock) we will leave the critical section as normal. + + It is possible that an ISR has caused an event on an unrelated and + unlocked queue. If this was the case then the event list for that + queue will have been updated but the ready lists left unchanged - + instead the readied task will have been added to the pending ready + list. */ + taskENTER_CRITICAL(); + { + /* We can safely unlock the queue and scheduler here as + interrupts are disabled. We must not yield with anything + locked, but we can yield from within a critical section. + + Tasks that have been placed on the pending ready list cannot + be tasks that are waiting for events on this queue. See + in comment xTaskRemoveFromEventList(). */ + prvUnlockQueue( pxQueue ); + + /* Resuming the scheduler may cause a yield. If so then there + is no point yielding again here. */ + if( !xTaskResumeAll() ) + { + taskYIELD(); + } + + /* We want to check to see if the queue is still full + before leaving the critical section. This is to prevent + this task placing an item into the queue due to an + interrupt making space on the queue between critical + sections (when there might be a higher priority task + blocked on the queue that cannot run yet because the + scheduler gets suspended). */ + if( pxQueue->uxMessagesWaiting == pxQueue->uxLength ) + { + /* We unblocked but there is no space in the queue, + we probably timed out. */ + xReturn = errQUEUE_FULL; + } + + /* Before leaving the critical section we have to ensure + exclusive access again. */ + vTaskSuspendAll(); + prvLockQueue( pxQueue ); + } + taskEXIT_CRITICAL(); + } + } + + /* If xReturn is errQUEUE_FULL then we unblocked when the queue + was still full. Don't check it again now as it is possible that + an interrupt has removed an item from the queue since we left the + critical section and we don't want to write to the queue in case + there is a task of higher priority blocked waiting for space to + be available on the queue. If this is the case the higher priority + task will execute when the scheduler is unsupended. */ + if( xReturn != errQUEUE_FULL ) + { + /* When we are here it is possible that we unblocked as space became + available on the queue. It is also possible that an ISR posted to the + queue since we left the critical section, so it may be that again there + is no space. This would only happen if a task and ISR post onto the + same queue. */ + taskENTER_CRITICAL(); + { + if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) + { + /* There is room in the queue, copy the data into the queue. */ + prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); + xReturn = pdPASS; + + /* Update the TxLock count so prvUnlockQueue knows to check for + tasks waiting for data to become available in the queue. */ + ++( pxQueue->xTxLock ); + } + else + { + xReturn = errQUEUE_FULL; + } + } + taskEXIT_CRITICAL(); + } + + if( xReturn == errQUEUE_FULL ) + { + if( xTicksToWait > 0 ) + { + if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) + { + xReturn = queueERRONEOUS_UNBLOCK; + } + } + } + } + while( xReturn == queueERRONEOUS_UNBLOCK ); + + prvUnlockQueue( pxQueue ); + xTaskResumeAll(); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +#if configUSE_ALTERNATIVE_API == 1 + + signed portBASE_TYPE xQueueAltGenericSend( xQueueHandle pxQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition ) + { + signed portBASE_TYPE xReturn; + xTimeOutType xTimeOut; + + /* The source code that implements the alternative (Alt) API is much + simpler because it executes everything from within a critical section. + This is the approach taken by many other RTOSes, but FreeRTOS.org has the + preferred fully featured API too. The fully featured API has more + complex code that takes longer to execute, but makes much less use of + critical sections. Therefore the alternative API sacrifices interrupt + responsiveness to gain execution speed, whereas the fully featured API + sacrifices execution speed to ensure better interrupt responsiveness. */ + + taskENTER_CRITICAL(); + { + /* Capture the current time status for future reference. */ + vTaskSetTimeOutState( &xTimeOut ); + + /* If the queue is already full we may have to block. */ + do + { + if( pxQueue->uxMessagesWaiting == pxQueue->uxLength ) + { + /* The queue is full - do we want to block or just leave without + posting? */ + if( xTicksToWait > ( portTickType ) 0 ) + { + /* We are going to place ourselves on the xTasksWaitingToSend + event list, and will get woken should the delay expire, or + space become available on the queue. */ + vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait ); + + /* Force a context switch now as we are blocked. We can do + this from within a critical section as the task we are + switching to has its own context. When we return here (i.e. + we unblock) we will leave the critical section as normal. */ + taskYIELD(); + } + } + + if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) + { + /* There is room in the queue, copy the data into the queue. */ + prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); + xReturn = pdPASS; + + if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The task waiting has a higher priority. */ + taskYIELD(); + } + } + } + else + { + xReturn = errQUEUE_FULL; + + if( xTicksToWait > 0 ) + { + if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) + { + /* Another task must have accessed the queue between + this task unblocking and actually executing. */ + xReturn = queueERRONEOUS_UNBLOCK; + } + } + } + } + while( xReturn == queueERRONEOUS_UNBLOCK ); + } + taskEXIT_CRITICAL(); + + return xReturn; + } + +#endif /* configUSE_ALTERNATIVE_API */ +/*-----------------------------------------------------------*/ + +#if configUSE_ALTERNATIVE_API == 1 + + signed portBASE_TYPE xQueueAltGenericReceive( xQueueHandle pxQueue, const void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking ) + { + signed portBASE_TYPE xReturn = pdTRUE; + xTimeOutType xTimeOut; + signed portCHAR *pcOriginalReadPosition; + + /* The source code that implements the alternative (Alt) API is much + simpler because it executes everything from within a critical section. + This is the approach taken by many other RTOSes, but FreeRTOS.org has the + preferred fully featured API too. The fully featured API has more + complex code that takes longer to execute, but makes much less use of + critical sections. Therefore the alternative API sacrifices interrupt + responsiveness to gain execution speed, whereas the fully featured API + sacrifices execution speed to ensure better interrupt responsiveness. */ + + taskENTER_CRITICAL(); + { + /* Capture the current time status for future reference. */ + vTaskSetTimeOutState( &xTimeOut ); + + do + { + /* If there are no messages in the queue we may have to block. */ + if( pxQueue->uxMessagesWaiting == ( unsigned portBASE_TYPE ) 0 ) + { + /* There are no messages in the queue, do we want to block or just + leave with nothing? */ + if( xTicksToWait > ( portTickType ) 0 ) + { + #if ( configUSE_MUTEXES == 1 ) + { + if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) + { + vTaskPriorityInherit( ( void * const ) pxQueue->pxMutexHolder ); + } + } + #endif + + vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); + taskYIELD(); + } + } + + if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 ) + { + /* Remember our read position in case we are just peeking. */ + pcOriginalReadPosition = pxQueue->pcReadFrom; + + prvCopyDataFromQueue( pxQueue, pvBuffer ); + + if( xJustPeeking == pdFALSE ) + { + /* We are actually removing data. */ + --( pxQueue->uxMessagesWaiting ); + + #if ( configUSE_MUTEXES == 1 ) + { + if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) + { + /* Record the information required to implement + priority inheritance should it become necessary. */ + pxQueue->pxMutexHolder = xTaskGetCurrentTaskHandle(); + } + } + #endif + + if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + { + /* The task waiting has a higher priority. */ + taskYIELD(); + } + } + } + else + { + /* We are not removing the data, so reset our read + pointer. */ + pxQueue->pcReadFrom = pcOriginalReadPosition; + } + + xReturn = pdPASS; + } + else + { + xReturn = errQUEUE_EMPTY; + + if( xTicksToWait > 0 ) + { + if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) + { + xReturn = queueERRONEOUS_UNBLOCK; + } + } + } + + } while( xReturn == queueERRONEOUS_UNBLOCK ); + } + taskEXIT_CRITICAL(); + + return xReturn; + } + +#endif /* configUSE_ALTERNATIVE_API */ +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xQueueGenericSendFromISR( xQueueHandle pxQueue, const void * const pvItemToQueue, signed portBASE_TYPE xTaskPreviouslyWoken, portBASE_TYPE xCopyPosition ) +{ + /* Similar to xQueueGenericSend, except we don't block if there is no room + in the queue. Also we don't directly wake a task that was blocked on a + queue read, instead we return a flag to say whether a context switch is + required or not (i.e. has a task with a higher priority than us been woken + by this post). */ + if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) + { + prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); + + /* If the queue is locked we do not alter the event list. This will + be done when the queue is unlocked later. */ + if( pxQueue->xTxLock == queueUNLOCKED ) + { + /* We only want to wake one task per ISR, so check that a task has + not already been woken. */ + if( !xTaskPreviouslyWoken ) + { + if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The task waiting has a higher priority so record that a + context switch is required. */ + return pdTRUE; + } + } + } + } + else + { + /* Increment the lock count so the task that unlocks the queue + knows that data was posted while it was locked. */ + ++( pxQueue->xTxLock ); + } + } + + return xTaskPreviouslyWoken; +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xQueueGenericReceive( xQueueHandle pxQueue, const void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking ) +{ +signed portBASE_TYPE xReturn = pdTRUE; +xTimeOutType xTimeOut; +signed portCHAR *pcOriginalReadPosition; + + /* This function is very similar to xQueueGenericSend(). See comments + within xQueueGenericSend() for a more detailed explanation. + + Make sure other tasks do not access the queue. */ + vTaskSuspendAll(); + + /* Capture the current time status for future reference. */ + vTaskSetTimeOutState( &xTimeOut ); + + /* Make sure interrupts do not access the queue. */ + prvLockQueue( pxQueue ); + + do + { + /* If there are no messages in the queue we may have to block. */ + if( prvIsQueueEmpty( pxQueue ) ) + { + /* There are no messages in the queue, do we want to block or just + leave with nothing? */ + if( xTicksToWait > ( portTickType ) 0 ) + { + #if ( configUSE_MUTEXES == 1 ) + { + if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) + { + portENTER_CRITICAL(); + vTaskPriorityInherit( ( void * const ) pxQueue->pxMutexHolder ); + portEXIT_CRITICAL(); + } + } + #endif + + vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); + taskENTER_CRITICAL(); + { + prvUnlockQueue( pxQueue ); + if( !xTaskResumeAll() ) + { + taskYIELD(); + } + + if( pxQueue->uxMessagesWaiting == ( unsigned portBASE_TYPE ) 0 ) + { + /* We unblocked but the queue is empty. We probably + timed out. */ + xReturn = errQUEUE_EMPTY; + } + + vTaskSuspendAll(); + prvLockQueue( pxQueue ); + } + taskEXIT_CRITICAL(); + } + } + + if( xReturn != errQUEUE_EMPTY ) + { + taskENTER_CRITICAL(); + { + if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 ) + { + /* Remember our read position in case we are just peeking. */ + pcOriginalReadPosition = pxQueue->pcReadFrom; + + prvCopyDataFromQueue( pxQueue, pvBuffer ); + + if( xJustPeeking == pdFALSE ) + { + /* We are actually removing data. */ + --( pxQueue->uxMessagesWaiting ); + + /* Increment the lock count so prvUnlockQueue knows to check for + tasks waiting for space to become available on the queue. */ + ++( pxQueue->xRxLock ); + + #if ( configUSE_MUTEXES == 1 ) + { + if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) + { + /* Record the information required to implement + priority inheritance should it become necessary. */ + pxQueue->pxMutexHolder = xTaskGetCurrentTaskHandle(); + } + } + #endif + } + else + { + /* We are not removing the data, so reset our read + pointer. */ + pxQueue->pcReadFrom = pcOriginalReadPosition; + + /* The data is being left in the queue, so increment the + lock count so prvUnlockQueue knows to check for other + tasks waiting for the data to be available. */ + ++( pxQueue->xTxLock ); + } + + xReturn = pdPASS; + } + else + { + xReturn = errQUEUE_EMPTY; + } + } + taskEXIT_CRITICAL(); + } + + if( xReturn == errQUEUE_EMPTY ) + { + if( xTicksToWait > 0 ) + { + if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) + { + xReturn = queueERRONEOUS_UNBLOCK; + } + } + } + } while( xReturn == queueERRONEOUS_UNBLOCK ); + + /* We no longer require exclusive access to the queue. */ + prvUnlockQueue( pxQueue ); + xTaskResumeAll(); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xQueueReceiveFromISR( xQueueHandle pxQueue, const void * const pvBuffer, signed portBASE_TYPE *pxTaskWoken ) +{ +signed portBASE_TYPE xReturn; + + /* We cannot block from an ISR, so check there is data available. */ + if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 ) + { + prvCopyDataFromQueue( pxQueue, pvBuffer ); + --( pxQueue->uxMessagesWaiting ); + + /* If the queue is locked we will not modify the event list. Instead + we update the lock count so the task that unlocks the queue will know + that an ISR has removed data while the queue was locked. */ + if( pxQueue->xRxLock == queueUNLOCKED ) + { + /* We only want to wake one task per ISR, so check that a task has + not already been woken. */ + if( !( *pxTaskWoken ) ) + { + if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + { + /* The task waiting has a higher priority than us so + force a context switch. */ + *pxTaskWoken = pdTRUE; + } + } + } + } + else + { + /* Increment the lock count so the task that unlocks the queue + knows that data was removed while it was locked. */ + ++( pxQueue->xRxLock ); + } + + xReturn = pdPASS; + } + else + { + xReturn = pdFAIL; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +unsigned portBASE_TYPE uxQueueMessagesWaiting( const xQueueHandle pxQueue ) +{ +unsigned portBASE_TYPE uxReturn; + + taskENTER_CRITICAL(); + uxReturn = pxQueue->uxMessagesWaiting; + taskEXIT_CRITICAL(); + + return uxReturn; +} +/*-----------------------------------------------------------*/ + +void vQueueDelete( xQueueHandle pxQueue ) +{ + vPortFree( pxQueue->pcHead ); + vPortFree( pxQueue ); +} +/*-----------------------------------------------------------*/ + +static void prvCopyDataToQueue( xQUEUE *pxQueue, const void *pvItemToQueue, portBASE_TYPE xPosition ) +{ + if( pxQueue->uxItemSize == 0 ) + { + #if ( configUSE_MUTEXES == 1 ) + { + if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) + { + /* The mutex is no longer being held. */ + vTaskPriorityDisinherit( ( void * const ) pxQueue->pxMutexHolder ); + pxQueue->pxMutexHolder = NULL; + } + } + #endif + } + else if( xPosition == queueSEND_TO_BACK ) + { + memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( unsigned ) pxQueue->uxItemSize ); + pxQueue->pcWriteTo += pxQueue->uxItemSize; + if( pxQueue->pcWriteTo >= pxQueue->pcTail ) + { + pxQueue->pcWriteTo = pxQueue->pcHead; + } + } + else + { + memcpy( ( void * ) pxQueue->pcReadFrom, pvItemToQueue, ( unsigned ) pxQueue->uxItemSize ); + pxQueue->pcReadFrom -= pxQueue->uxItemSize; + if( pxQueue->pcReadFrom < pxQueue->pcHead ) + { + pxQueue->pcReadFrom = ( pxQueue->pcTail - pxQueue->uxItemSize ); + } + } + + ++( pxQueue->uxMessagesWaiting ); +} +/*-----------------------------------------------------------*/ + +static void prvCopyDataFromQueue( xQUEUE * const pxQueue, const void *pvBuffer ) +{ + if( pxQueue->uxQueueType != queueQUEUE_IS_MUTEX ) + { + pxQueue->pcReadFrom += pxQueue->uxItemSize; + if( pxQueue->pcReadFrom >= pxQueue->pcTail ) + { + pxQueue->pcReadFrom = pxQueue->pcHead; + } + memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); + } +} +/*-----------------------------------------------------------*/ + +static void prvUnlockQueue( xQueueHandle pxQueue ) +{ + /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. */ + + /* The lock counts contains the number of extra data items placed or + removed from the queue while the queue was locked. When a queue is + locked items can be added or removed, but the event lists cannot be + updated. */ + taskENTER_CRITICAL(); + { + --( pxQueue->xTxLock ); + + /* See if data was added to the queue while it was locked. */ + if( pxQueue->xTxLock > queueUNLOCKED ) + { + pxQueue->xTxLock = queueUNLOCKED; + + /* Data was posted while the queue was locked. Are any tasks + blocked waiting for data to become available? */ + if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) ) + { + /* Tasks that are removed from the event list will get added to + the pending ready list as the scheduler is still suspended. */ + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The task waiting has a higher priority so record that a + context switch is required. */ + vTaskMissedYield(); + } + } + } + } + taskEXIT_CRITICAL(); + + /* Do the same for the Rx lock. */ + taskENTER_CRITICAL(); + { + --( pxQueue->xRxLock ); + + if( pxQueue->xRxLock > queueUNLOCKED ) + { + pxQueue->xRxLock = queueUNLOCKED; + + if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + { + vTaskMissedYield(); + } + } + } + } + taskEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +static signed portBASE_TYPE prvIsQueueEmpty( const xQueueHandle pxQueue ) +{ +signed portBASE_TYPE xReturn; + + taskENTER_CRITICAL(); + xReturn = ( pxQueue->uxMessagesWaiting == ( unsigned portBASE_TYPE ) 0 ); + taskEXIT_CRITICAL(); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +static signed portBASE_TYPE prvIsQueueFull( const xQueueHandle pxQueue ) +{ +signed portBASE_TYPE xReturn; + + taskENTER_CRITICAL(); + xReturn = ( pxQueue->uxMessagesWaiting == pxQueue->uxLength ); + taskEXIT_CRITICAL(); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +#if configUSE_CO_ROUTINES == 1 +signed portBASE_TYPE xQueueCRSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait ) +{ +signed portBASE_TYPE xReturn; + + /* If the queue is already full we may have to block. A critical section + is required to prevent an interrupt removing something from the queue + between the check to see if the queue is full and blocking on the queue. */ + portDISABLE_INTERRUPTS(); + { + if( prvIsQueueFull( pxQueue ) ) + { + /* The queue is full - do we want to block or just leave without + posting? */ + if( xTicksToWait > ( portTickType ) 0 ) + { + /* As this is called from a coroutine we cannot block directly, but + return indicating that we need to block. */ + vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToSend ) ); + portENABLE_INTERRUPTS(); + return errQUEUE_BLOCKED; + } + else + { + portENABLE_INTERRUPTS(); + return errQUEUE_FULL; + } + } + } + portENABLE_INTERRUPTS(); + + portNOP(); + + portDISABLE_INTERRUPTS(); + { + if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) + { + /* There is room in the queue, copy the data into the queue. */ + prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK ); + xReturn = pdPASS; + + /* Were any co-routines waiting for data to become available? */ + if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) ) + { + /* In this instance the co-routine could be placed directly + into the ready list as we are within a critical section. + Instead the same pending ready list mechanism is used as if + the event were caused from within an interrupt. */ + if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The co-routine waiting has a higher priority so record + that a yield might be appropriate. */ + xReturn = errQUEUE_YIELD; + } + } + } + else + { + xReturn = errQUEUE_FULL; + } + } + portENABLE_INTERRUPTS(); + + return xReturn; +} +#endif +/*-----------------------------------------------------------*/ + +#if configUSE_CO_ROUTINES == 1 +signed portBASE_TYPE xQueueCRReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait ) +{ +signed portBASE_TYPE xReturn; + + /* If the queue is already empty we may have to block. A critical section + is required to prevent an interrupt adding something to the queue + between the check to see if the queue is empty and blocking on the queue. */ + portDISABLE_INTERRUPTS(); + { + if( pxQueue->uxMessagesWaiting == ( unsigned portBASE_TYPE ) 0 ) + { + /* There are no messages in the queue, do we want to block or just + leave with nothing? */ + if( xTicksToWait > ( portTickType ) 0 ) + { + /* As this is a co-routine we cannot block directly, but return + indicating that we need to block. */ + vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToReceive ) ); + portENABLE_INTERRUPTS(); + return errQUEUE_BLOCKED; + } + else + { + portENABLE_INTERRUPTS(); + return errQUEUE_FULL; + } + } + } + portENABLE_INTERRUPTS(); + + portNOP(); + + portDISABLE_INTERRUPTS(); + { + if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 ) + { + /* Data is available from the queue. */ + pxQueue->pcReadFrom += pxQueue->uxItemSize; + if( pxQueue->pcReadFrom >= pxQueue->pcTail ) + { + pxQueue->pcReadFrom = pxQueue->pcHead; + } + --( pxQueue->uxMessagesWaiting ); + memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); + + xReturn = pdPASS; + + /* Were any co-routines waiting for space to become available? */ + if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) ) + { + /* In this instance the co-routine could be placed directly + into the ready list as we are within a critical section. + Instead the same pending ready list mechanism is used as if + the event were caused from within an interrupt. */ + if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + { + xReturn = errQUEUE_YIELD; + } + } + } + else + { + xReturn = pdFAIL; + } + } + portENABLE_INTERRUPTS(); + + return xReturn; +} +#endif +/*-----------------------------------------------------------*/ + + + +#if configUSE_CO_ROUTINES == 1 +signed portBASE_TYPE xQueueCRSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xCoRoutinePreviouslyWoken ) +{ + /* Cannot block within an ISR so if there is no space on the queue then + exit without doing anything. */ + if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) + { + prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK ); + + /* We only want to wake one co-routine per ISR, so check that a + co-routine has not already been woken. */ + if( !xCoRoutinePreviouslyWoken ) + { + if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) ) + { + if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + return pdTRUE; + } + } + } + } + + return xCoRoutinePreviouslyWoken; +} +#endif +/*-----------------------------------------------------------*/ + +#if configUSE_CO_ROUTINES == 1 +signed portBASE_TYPE xQueueCRReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxCoRoutineWoken ) +{ +signed portBASE_TYPE xReturn; + + /* We cannot block from an ISR, so check there is data available. If + not then just leave without doing anything. */ + if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 ) + { + /* Copy the data from the queue. */ + pxQueue->pcReadFrom += pxQueue->uxItemSize; + if( pxQueue->pcReadFrom >= pxQueue->pcTail ) + { + pxQueue->pcReadFrom = pxQueue->pcHead; + } + --( pxQueue->uxMessagesWaiting ); + memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); + + if( !( *pxCoRoutineWoken ) ) + { + if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) ) + { + if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + { + *pxCoRoutineWoken = pdTRUE; + } + } + } + + xReturn = pdPASS; + } + else + { + xReturn = pdFAIL; + } + + return xReturn; +} +#endif +/*-----------------------------------------------------------*/ + diff --git a/20080212/Source/readme.txt b/20080212/Source/readme.txt new file mode 100644 index 000000000..01a878152 --- /dev/null +++ b/20080212/Source/readme.txt @@ -0,0 +1,15 @@ +Each real time kernel port consists of three files that contain the core kernel +components and are common to every port, and one or more files that are +specific to a particular microcontroller and or compiler. + ++ The FreeRTOS/Source directory contains the three files that are common to +every port. The kernel is contained within these three files. + ++ The FreeRTOS/Source/Portable directory contains the files that are specific to +a particular microcontroller and or compiler. + ++ The FreeRTOS/Source/include directory contains the real time kernel header +files. + +See the readme file in the FreeRTOS/Source/Portable directory for more +information. \ No newline at end of file diff --git a/20080212/Source/tasks.c b/20080212/Source/tasks.c new file mode 100644 index 000000000..7063ab80c --- /dev/null +++ b/20080212/Source/tasks.c @@ -0,0 +1,2046 @@ +/* + FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + +++ http://www.FreeRTOS.org +++ + Documentation, latest information, license and contact details. + + +++ http://www.SafeRTOS.com +++ + A version that is certified for use in safety critical systems. + + +++ http://www.OpenRTOS.com +++ + Commercial support, development, porting, licensing and training services. + + *************************************************************************** +*/ + +/* +Changes from V1.00: + + + Call to portRESTORE_CONTEXT has been removed. The first context + switch is now performed within sPortStartScheduler(). + +Changes from V1.01: + + + More use of 8bit data types. + + Function name prefixes changed where the data type returned has changed. + + configUSE_TRACE_FACILITY is no longer defined by default. + +Changes from V1.2.0 + + + Introduced ucTopReadyPriority. This tracks the highest priority ready + queue that contains a valid TCB and thus makes the context switch + slightly faster. + + + prvAddTaskToReadyQueue() has been made a macro. + +Changes from V1.2.6 + + + Added conditional compilation directives. + + Extended API. + + Rearranged function order. + + Creating a task now causes a context switch if the task being created + has a higher priority than the calling task - assuming the kernel is + running. + + vTaskDelete() now only causes a context switch if the calling task is + the task being deleted. + +Changes from V2.0.0 + + + Allow the type of the tick count to be 16 or 32 bits. + + Introduce xPendingReadyList feature to allow the time interrupts have to + be disabled to be minimised. + + Remove the #if( INCLUDE_vTaskSuspendAll ) statements. vTaskSuspendAll() + is now always included as it is used by the scheduler itself. + +Changes from V2.1.0 + + + Bug fix - pxCurrentTCB is now initialised before the call to + prvInitializeTaskLists(). Previously pxCurrentTCB could be accessed + while null. + +Changed from V2.1.1 + + + Change to where lStackSize is declared within sTaskCreate() to prevent + compiler warnings with 8051 port. + +Changes from V2.2.0 + + + Explicit use of 'signed' qualifier on portCHAR types added. + + Changed odd calculation of initial pxTopOfStack value when + portSTACK_GROWTH < 0. + + Removed pcVersionNumber definition. + +Changes from V2.5.3 + + + cTaskResumeAll() modified to ensure it can be called prior to the task + lists being initialised. + +Changes from V2.5.5 + + + Added API function vTaskDelayUntil(). + + Added INCLUDE_vTaskDelay conditional compilation. + +Changes from V2.6.0 + + + Updated the vWriteTraceToBuffer macro to always be 4 byte aligned so it + can be used on ARM architectures. + + tskMAX_TASK_NAME_LEN definition replaced with the port specific + configMAX_TASK_NAME_LEN definition. + + Removed the call to strcpy when copying across the task name into the + TCB. + + Added ucTasksDeleted variable to prevent vTaskSuspendAll() being called + too often in the idle task. + +Changes between V3.0.0 and V2.6.1 + + + When resuming the scheduler a yield is performed if either a tick has + been missed, or a task is moved from the pending ready list into a ready + list. Previously a yield was not performed on this second condition. + + Introduced the type portBASE_TYPE. This necessitates several API + changes. + + Removed the sUsingPreemption variable. The constant defined in + portmacro.h is now used directly. + + The idle task can now include an optional hook function - and no longer + completes its time slice if other tasks with equal priority to it are + ready to run. + + See the FreeRTOS.org documentation for more information on V2.x.x to + V3.x.x modifications. + +Changes from V3.1.1 + + + Modified vTaskPrioritySet() and vTaskResume() to allow these functions to + be called while the scheduler is suspended. + + Corrected the task ordering within event lists. + +Changes from V3.2.0 + + + Added function xTaskGetCurrentTaskHandle(). + +Changes from V3.2.4 + + + Changed the volatile declarations on some variables to reflect the + changes to the list definitions. + + Changed the order of the TCB definition so there is commonality between + the task control block and a co-routine control block. + + Allow the scheduler to be started even if no tasks other than the idle + task has been created. This allows co-routines to run even when no tasks + have been created. + + The need for a context switch is now signalled if a task woken by an + event has a priority greater or equal to the currently running task. + Previously this was only greater than. + +Changes from V4.0.0 + + + Added the xMissedYield handling. + +Changes from V4.0.1 + + + The function vTaskList() now suspends the scheduler rather than disabling + interrupts during the creation of the task list. + + Allow a task to delete itself by passing in its own handle. Previously + this could only be done by passing in NULL. + + The tick hook function is now called only within a tick isr. Previously + it was also called when the tick function was called during the scheduler + unlocking process. + +Changes from V4.0.3 + + + Extra checks have been placed in vTaskPrioritySet() to avoid unnecessary + yields. + +Changed from V4.0.4 + + + Bug fix: The 'value' of the event list item is updated when the priority + of a task is changed. Previously only the priority of the TCB itself was + changed. + + When resuming a task a check is first made to see if the task is actually + suspended. + + vTaskPrioritySet() and vTaskResume() no longer use the event list item. + This has not been necessary since V4.0.1 when the xMissedYield handling + was added. + + Implement xTaskResumeFromISR(). + +Changes from V4.0.5 + + + Added utility functions and xOverflowCount variable to facilitate the + queue.c changes. + +Changes from V4.1.2 + + + Tasks that block on events with a timeout of portMAX_DELAY are now + blocked indefinitely if configINCLUDE_vTaskSuspend is defined. + Previously portMAX_DELAY was just the longest block time possible. + +Changes from V4.1.3 + + + Very small change made to xTaskCheckForTimeout() as a result of the + SafeRTOS testing. This corrects the case where the function can return an + invalid value - but only in an extremely unlikely scenario. + +Changes since V4.3.1: + + + Added xTaskGetSchedulerState() function. + + Added prvIsTaskSuspended() to take into account the Occurrence of + vTaskResume() or vTaskResumeFromISR() being called passing in the + handle of a task that appears in the Suspended list only because it + is blocked on an event without a timeout being specified. + + Updated xTaskCheckForTimeout() to take into account that tasks blocked + using the Suspended list should never time out. +*/ + +#include +#include +#include + +#include "FreeRTOS.h" +#include "task.h" + +/* + * Macro to define the amount of stack available to the idle task. + */ +#define tskIDLE_STACK_SIZE configMINIMAL_STACK_SIZE + + +/* + * Default a definitions for backwards compatibility with old + * portmacro.h files. + */ +#ifndef configMAX_TASK_NAME_LEN + #define configMAX_TASK_NAME_LEN 16 +#endif + +#ifndef configIDLE_SHOULD_YIELD + #define configIDLE_SHOULD_YIELD 1 +#endif + +#if configMAX_TASK_NAME_LEN < 1 + #undef configMAX_TASK_NAME_LEN + #define configMAX_TASK_NAME_LEN 1 +#endif + +#ifndef INCLUDE_xTaskResumeFromISR + #define INCLUDE_xTaskResumeFromISR 1 +#endif + +#ifndef INCLUDE_xTaskGetSchedulerState + #define INCLUDE_xTaskGetSchedulerState 0 +#endif + +/* + * Task control block. A task control block (TCB) is allocated to each task, + * and stores the context of the task. + */ +typedef struct tskTaskControlBlock +{ + volatile portSTACK_TYPE *pxTopOfStack; /*< Points to the location of the last item placed on the tasks stack. THIS MUST BE THE FIRST MEMBER OF THE STRUCT. */ + xListItem xGenericListItem; /*< List item used to place the TCB in ready and blocked queues. */ + xListItem xEventListItem; /*< List item used to place the TCB in event lists. */ + unsigned portBASE_TYPE uxPriority; /*< The priority of the task where 0 is the lowest priority. */ + portSTACK_TYPE *pxStack; /*< Points to the start of the stack. */ + signed portCHAR pcTaskName[ configMAX_TASK_NAME_LEN ];/*< Descriptive name given to the task when created. Facilitates debugging only. */ + + #if ( configUSE_TRACE_FACILITY == 1 ) + unsigned portBASE_TYPE uxTCBNumber; /*< This is used for tracing the scheduler and making debugging easier only. */ + #endif + + #if ( configUSE_MUTEXES == 1 ) + unsigned portBASE_TYPE uxBasePriority; + #endif + +} tskTCB; + +/*lint -e956 */ + +tskTCB * volatile pxCurrentTCB = NULL; + +/* Lists for ready and blocked tasks. --------------------*/ + +static xList pxReadyTasksLists[ configMAX_PRIORITIES ]; /*< Prioritised ready tasks. */ +static xList xDelayedTaskList1; /*< Delayed tasks. */ +static xList xDelayedTaskList2; /*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */ +static xList * volatile pxDelayedTaskList; /*< Points to the delayed task list currently being used. */ +static xList * volatile pxOverflowDelayedTaskList; /*< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */ +static xList xPendingReadyList; /*< Tasks that have been readied while the scheduler was suspended. They will be moved to the ready queue when the scheduler is resumed. */ + +#if ( INCLUDE_vTaskDelete == 1 ) + + static volatile xList xTasksWaitingTermination; /*< Tasks that have been deleted - but the their memory not yet freed. */ + static volatile unsigned portBASE_TYPE uxTasksDeleted = ( unsigned portBASE_TYPE ) 0; + +#endif + +#if ( INCLUDE_vTaskSuspend == 1 ) + + static xList xSuspendedTaskList; /*< Tasks that are currently suspended. */ + +#endif + +/* File private variables. --------------------------------*/ +static volatile unsigned portBASE_TYPE uxCurrentNumberOfTasks = ( unsigned portBASE_TYPE ) 0; +static volatile portTickType xTickCount = ( portTickType ) 0; +static unsigned portBASE_TYPE uxTopUsedPriority = tskIDLE_PRIORITY; +static volatile unsigned portBASE_TYPE uxTopReadyPriority = tskIDLE_PRIORITY; +static volatile signed portBASE_TYPE xSchedulerRunning = pdFALSE; +static volatile unsigned portBASE_TYPE uxSchedulerSuspended = ( unsigned portBASE_TYPE ) pdFALSE; +static volatile unsigned portBASE_TYPE uxMissedTicks = ( unsigned portBASE_TYPE ) 0; +static volatile portBASE_TYPE xMissedYield = ( portBASE_TYPE ) pdFALSE; +static volatile portBASE_TYPE xNumOfOverflows = ( portBASE_TYPE ) 0; +/* Debugging and trace facilities private variables and macros. ------------*/ + +/* + * The value used to fill the stack of a task when the task is created. This + * is used purely for checking the high water mark for tasks. + */ +#define tskSTACK_FILL_BYTE ( 0xa5 ) + +/* + * Macros used by vListTask to indicate which state a task is in. + */ +#define tskBLOCKED_CHAR ( ( signed portCHAR ) 'B' ) +#define tskREADY_CHAR ( ( signed portCHAR ) 'R' ) +#define tskDELETED_CHAR ( ( signed portCHAR ) 'D' ) +#define tskSUSPENDED_CHAR ( ( signed portCHAR ) 'S' ) + +/* + * Macros and private variables used by the trace facility. + */ +#if ( configUSE_TRACE_FACILITY == 1 ) + + #define tskSIZE_OF_EACH_TRACE_LINE ( ( unsigned portLONG ) ( sizeof( unsigned portLONG ) + sizeof( unsigned portLONG ) ) ) + static volatile signed portCHAR * volatile pcTraceBuffer; + static signed portCHAR *pcTraceBufferStart; + static signed portCHAR *pcTraceBufferEnd; + static signed portBASE_TYPE xTracing = pdFALSE; + +#endif + +/* + * Macro that writes a trace of scheduler activity to a buffer. This trace + * shows which task is running when and is very useful as a debugging tool. + * As this macro is called each context switch it is a good idea to undefine + * it if not using the facility. + */ +#if ( configUSE_TRACE_FACILITY == 1 ) + + #define vWriteTraceToBuffer() \ + { \ + if( xTracing ) \ + { \ + static unsigned portBASE_TYPE uxPreviousTask = 255; \ + \ + if( uxPreviousTask != pxCurrentTCB->uxTCBNumber ) \ + { \ + if( ( pcTraceBuffer + tskSIZE_OF_EACH_TRACE_LINE ) < pcTraceBufferEnd ) \ + { \ + uxPreviousTask = pxCurrentTCB->uxTCBNumber; \ + *( unsigned portLONG * ) pcTraceBuffer = ( unsigned portLONG ) xTickCount; \ + pcTraceBuffer += sizeof( unsigned portLONG ); \ + *( unsigned portLONG * ) pcTraceBuffer = ( unsigned portLONG ) uxPreviousTask; \ + pcTraceBuffer += sizeof( unsigned portLONG ); \ + } \ + else \ + { \ + xTracing = pdFALSE; \ + } \ + } \ + } \ + } + +#else + + #define vWriteTraceToBuffer() + +#endif + + +/* + * Place the task represented by pxTCB into the appropriate ready queue for + * the task. It is inserted at the end of the list. One quirk of this is + * that if the task being inserted is at the same priority as the currently + * executing task, then it will only be rescheduled after the currently + * executing task has been rescheduled. + */ +#define prvAddTaskToReadyQueue( pxTCB ) \ +{ \ + if( pxTCB->uxPriority > uxTopReadyPriority ) \ + { \ + uxTopReadyPriority = pxTCB->uxPriority; \ + } \ + vListInsertEnd( ( xList * ) &( pxReadyTasksLists[ pxTCB->uxPriority ] ), &( pxTCB->xGenericListItem ) ); \ +} + +/* + * Macro that looks at the list of tasks that are currently delayed to see if + * any require waking. + * + * Tasks are stored in the queue in the order of their wake time - meaning + * once one tasks has been found whose timer has not expired we need not look + * any further down the list. + */ +#define prvCheckDelayedTasks() \ +{ \ +register tskTCB *pxTCB; \ + \ + while( ( pxTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ) ) != NULL ) \ + { \ + if( xTickCount < listGET_LIST_ITEM_VALUE( &( pxTCB->xGenericListItem ) ) ) \ + { \ + break; \ + } \ + vListRemove( &( pxTCB->xGenericListItem ) ); \ + /* Is the task waiting on an event also? */ \ + if( pxTCB->xEventListItem.pvContainer ) \ + { \ + vListRemove( &( pxTCB->xEventListItem ) ); \ + } \ + prvAddTaskToReadyQueue( pxTCB ); \ + } \ +} + +/* + * Several functions take an xTaskHandle parameter that can optionally be NULL, + * where NULL is used to indicate that the handle of the currently executing + * task should be used in place of the parameter. This macro simply checks to + * see if the parameter is NULL and returns a pointer to the appropriate TCB. + */ +#define prvGetTCBFromHandle( pxHandle ) ( ( pxHandle == NULL ) ? ( tskTCB * ) pxCurrentTCB : ( tskTCB * ) pxHandle ) + + +/* File private functions. --------------------------------*/ + +/* + * Utility to ready a TCB for a given task. Mainly just copies the parameters + * into the TCB structure. + */ +static void prvInitialiseTCBVariables( tskTCB *pxTCB, const signed portCHAR * const pcName, unsigned portBASE_TYPE uxPriority ); + +/* + * Utility to ready all the lists used by the scheduler. This is called + * automatically upon the creation of the first task. + */ +static void prvInitialiseTaskLists( void ); + +/* + * The idle task, which as all tasks is implemented as a never ending loop. + * The idle task is automatically created and added to the ready lists upon + * creation of the first user task. + * + * The portTASK_FUNCTION_PROTO() macro is used to allow port/compiler specific + * language extensions. The equivalent prototype for this function is: + * + * void prvIdleTask( void *pvParameters ); + * + */ +static portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters ); + +/* + * Utility to free all memory allocated by the scheduler to hold a TCB, + * including the stack pointed to by the TCB. + * + * This does not free memory allocated by the task itself (i.e. memory + * allocated by calls to pvPortMalloc from within the tasks application code). + */ +#if ( ( INCLUDE_vTaskDelete == 1 ) || ( INCLUDE_vTaskCleanUpResources == 1 ) ) + static void prvDeleteTCB( tskTCB *pxTCB ); +#endif + +/* + * Used only by the idle task. This checks to see if anything has been placed + * in the list of tasks waiting to be deleted. If so the task is cleaned up + * and its TCB deleted. + */ +static void prvCheckTasksWaitingTermination( void ); + +/* + * Allocates memory from the heap for a TCB and associated stack. Checks the + * allocation was successful. + */ +static tskTCB *prvAllocateTCBAndStack( unsigned portSHORT usStackDepth ); + +/* + * Called from vTaskList. vListTasks details all the tasks currently under + * control of the scheduler. The tasks may be in one of a number of lists. + * prvListTaskWithinSingleList accepts a list and details the tasks from + * within just that list. + * + * THIS FUNCTION IS INTENDED FOR DEBUGGING ONLY, AND SHOULD NOT BE CALLED FROM + * NORMAL APPLICATION CODE. + */ +#if ( configUSE_TRACE_FACILITY == 1 ) + + static void prvListTaskWithinSingleList( const signed portCHAR *pcWriteBuffer, xList *pxList, signed portCHAR cStatus ); + +#endif + +/* + * When a task is created, the stack of the task is filled with a known value. + * This function determines the 'high water mark' of the task stack by + * determining how much of the stack remains at the original preset value. + */ +#if ( configUSE_TRACE_FACILITY == 1 ) + + unsigned portSHORT usTaskCheckFreeStackSpace( const unsigned portCHAR * pucStackByte ); + +#endif + +/* + * Checks that a task being resumed (unsuspended) is actually in the Suspended + * state. + */ +#if ( INCLUDE_vTaskSuspend == 1 ) + + static portBASE_TYPE prvIsTaskSuspended( const tskTCB * const pxTCB ); + +#endif + +/*lint +e956 */ + + + + + +/*----------------------------------------------------------- + * TASK CREATION API documented in task.h + *----------------------------------------------------------*/ + +signed portBASE_TYPE xTaskCreate( pdTASK_CODE pvTaskCode, const signed portCHAR * const pcName, unsigned portSHORT usStackDepth, void *pvParameters, unsigned portBASE_TYPE uxPriority, xTaskHandle *pxCreatedTask ) +{ +signed portBASE_TYPE xReturn; +tskTCB * pxNewTCB; +#if ( configUSE_TRACE_FACILITY == 1 ) + static unsigned portBASE_TYPE uxTaskNumber = 0; /*lint !e956 Static is deliberate - this is guarded before use. */ +#endif + + /* Allocate the memory required by the TCB and stack for the new task. + checking that the allocation was successful. */ + pxNewTCB = prvAllocateTCBAndStack( usStackDepth ); + + if( pxNewTCB != NULL ) + { + portSTACK_TYPE *pxTopOfStack; + + /* Setup the newly allocated TCB with the initial state of the task. */ + prvInitialiseTCBVariables( pxNewTCB, pcName, uxPriority ); + + /* Calculate the top of stack address. This depends on whether the + stack grows from high memory to low (as per the 80x86) or visa versa. + portSTACK_GROWTH is used to make the result positive or negative as + required by the port. */ + #if portSTACK_GROWTH < 0 + { + pxTopOfStack = pxNewTCB->pxStack + ( usStackDepth - 1 ); + } + #else + { + pxTopOfStack = pxNewTCB->pxStack; + } + #endif + + /* Initialize the TCB stack to look as if the task was already running, + but had been interrupted by the scheduler. The return address is set + to the start of the task function. Once the stack has been initialised + the top of stack variable is updated. */ + pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pvTaskCode, pvParameters ); + + /* We are going to manipulate the task queues to add this task to a + ready list, so must make sure no interrupts occur. */ + portENTER_CRITICAL(); + { + uxCurrentNumberOfTasks++; + if( uxCurrentNumberOfTasks == ( unsigned portBASE_TYPE ) 1 ) + { + /* As this is the first task it must also be the current task. */ + pxCurrentTCB = pxNewTCB; + + /* This is the first task to be created so do the preliminary + initialisation required. We will not recover if this call + fails, but we will report the failure. */ + prvInitialiseTaskLists(); + } + else + { + /* If the scheduler is not already running, make this task the + current task if it is the highest priority task to be created + so far. */ + if( xSchedulerRunning == pdFALSE ) + { + if( pxCurrentTCB->uxPriority <= uxPriority ) + { + pxCurrentTCB = pxNewTCB; + } + } + } + + /* Remember the top priority to make context switching faster. Use + the priority in pxNewTCB as this has been capped to a valid value. */ + if( pxNewTCB->uxPriority > uxTopUsedPriority ) + { + uxTopUsedPriority = pxNewTCB->uxPriority; + } + + #if ( configUSE_TRACE_FACILITY == 1 ) + { + /* Add a counter into the TCB for tracing only. */ + pxNewTCB->uxTCBNumber = uxTaskNumber; + uxTaskNumber++; + } + #endif + + prvAddTaskToReadyQueue( pxNewTCB ); + + xReturn = pdPASS; + } + portEXIT_CRITICAL(); + } + else + { + xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; + } + + if( xReturn == pdPASS ) + { + if( ( void * ) pxCreatedTask != NULL ) + { + /* Pass the TCB out - in an anonymous way. The calling function/ + task can use this as a handle to delete the task later if + required.*/ + *pxCreatedTask = ( xTaskHandle ) pxNewTCB; + } + + if( xSchedulerRunning != pdFALSE ) + { + /* If the created task is of a higher priority than the current task + then it should run now. */ + if( pxCurrentTCB->uxPriority < uxPriority ) + { + taskYIELD(); + } + } + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskDelete == 1 ) + + void vTaskDelete( xTaskHandle pxTaskToDelete ) + { + tskTCB *pxTCB; + + taskENTER_CRITICAL(); + { + /* Ensure a yield is performed if the current task is being + deleted. */ + if( pxTaskToDelete == pxCurrentTCB ) + { + pxTaskToDelete = NULL; + } + + /* If null is passed in here then we are deleting ourselves. */ + pxTCB = prvGetTCBFromHandle( pxTaskToDelete ); + + /* Remove task from the ready list and place in the termination list. + This will stop the task from be scheduled. The idle task will check + the termination list and free up any memory allocated by the + scheduler for the TCB and stack. */ + vListRemove( &( pxTCB->xGenericListItem ) ); + + /* Is the task waiting on an event also? */ + if( pxTCB->xEventListItem.pvContainer ) + { + vListRemove( &( pxTCB->xEventListItem ) ); + } + + vListInsertEnd( ( xList * ) &xTasksWaitingTermination, &( pxTCB->xGenericListItem ) ); + + /* Increment the ucTasksDeleted variable so the idle task knows + there is a task that has been deleted and that it should therefore + check the xTasksWaitingTermination list. */ + ++uxTasksDeleted; + } + taskEXIT_CRITICAL(); + + /* Force a reschedule if we have just deleted the current task. */ + if( xSchedulerRunning != pdFALSE ) + { + if( ( void * ) pxTaskToDelete == NULL ) + { + taskYIELD(); + } + } + } + +#endif + + + + + + +/*----------------------------------------------------------- + * TASK CONTROL API documented in task.h + *----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskDelayUntil == 1 ) + + void vTaskDelayUntil( portTickType * const pxPreviousWakeTime, portTickType xTimeIncrement ) + { + portTickType xTimeToWake; + portBASE_TYPE xAlreadyYielded, xShouldDelay = pdFALSE; + + vTaskSuspendAll(); + { + /* Generate the tick time at which the task wants to wake. */ + xTimeToWake = *pxPreviousWakeTime + xTimeIncrement; + + if( xTickCount < *pxPreviousWakeTime ) + { + /* The tick count has overflowed since this function was + lasted called. In this case the only time we should ever + actually delay is if the wake time has also overflowed, + and the wake time is greater than the tick time. When this + is the case it is as if neither time had overflowed. */ + if( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xTickCount ) ) + { + xShouldDelay = pdTRUE; + } + } + else + { + /* The tick time has not overflowed. In this case we will + delay if either the wake time has overflowed, and/or the + tick time is less than the wake time. */ + if( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xTickCount ) ) + { + xShouldDelay = pdTRUE; + } + } + + /* Update the wake time ready for the next call. */ + *pxPreviousWakeTime = xTimeToWake; + + if( xShouldDelay ) + { + /* We must remove ourselves from the ready list before adding + ourselves to the blocked list as the same list item is used for + both lists. */ + vListRemove( ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); + + /* The list item will be inserted in wake time order. */ + listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake ); + + if( xTimeToWake < xTickCount ) + { + /* Wake time has overflowed. Place this item in the + overflow list. */ + vListInsert( ( xList * ) pxOverflowDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); + } + else + { + /* The wake time has not overflowed, so we can use the + current block list. */ + vListInsert( ( xList * ) pxDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); + } + } + } + xAlreadyYielded = xTaskResumeAll(); + + /* Force a reschedule if xTaskResumeAll has not already done so, we may + have put ourselves to sleep. */ + if( !xAlreadyYielded ) + { + taskYIELD(); + } + } + +#endif +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskDelay == 1 ) + + void vTaskDelay( portTickType xTicksToDelay ) + { + portTickType xTimeToWake; + signed portBASE_TYPE xAlreadyYielded = pdFALSE; + + /* A delay time of zero just forces a reschedule. */ + if( xTicksToDelay > ( portTickType ) 0 ) + { + vTaskSuspendAll(); + { + /* A task that is removed from the event list while the + scheduler is suspended will not get placed in the ready + list or removed from the blocked list until the scheduler + is resumed. + + This task cannot be in an event list as it is the currently + executing task. */ + + /* Calculate the time to wake - this may overflow but this is + not a problem. */ + xTimeToWake = xTickCount + xTicksToDelay; + + /* We must remove ourselves from the ready list before adding + ourselves to the blocked list as the same list item is used for + both lists. */ + vListRemove( ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); + + /* The list item will be inserted in wake time order. */ + listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake ); + + if( xTimeToWake < xTickCount ) + { + /* Wake time has overflowed. Place this item in the + overflow list. */ + vListInsert( ( xList * ) pxOverflowDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); + } + else + { + /* The wake time has not overflowed, so we can use the + current block list. */ + vListInsert( ( xList * ) pxDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); + } + } + xAlreadyYielded = xTaskResumeAll(); + } + + /* Force a reschedule if xTaskResumeAll has not already done so, we may + have put ourselves to sleep. */ + if( !xAlreadyYielded ) + { + taskYIELD(); + } + } + +#endif +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_uxTaskPriorityGet == 1 ) + + unsigned portBASE_TYPE uxTaskPriorityGet( xTaskHandle pxTask ) + { + tskTCB *pxTCB; + unsigned portBASE_TYPE uxReturn; + + taskENTER_CRITICAL(); + { + /* If null is passed in here then we are changing the + priority of the calling function. */ + pxTCB = prvGetTCBFromHandle( pxTask ); + uxReturn = pxTCB->uxPriority; + } + taskEXIT_CRITICAL(); + + return uxReturn; + } + +#endif +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskPrioritySet == 1 ) + + void vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority ) + { + tskTCB *pxTCB; + unsigned portBASE_TYPE uxCurrentPriority, xYieldRequired = pdFALSE; + + /* Ensure the new priority is valid. */ + if( uxNewPriority >= configMAX_PRIORITIES ) + { + uxNewPriority = configMAX_PRIORITIES - 1; + } + + taskENTER_CRITICAL(); + { + /* If null is passed in here then we are changing the + priority of the calling function. */ + pxTCB = prvGetTCBFromHandle( pxTask ); + + #if ( configUSE_MUTEXES == 1 ) + { + uxCurrentPriority = pxTCB->uxBasePriority; + } + #else + { + uxCurrentPriority = pxTCB->uxPriority; + } + #endif + + if( uxCurrentPriority != uxNewPriority ) + { + /* The priority change may have readied a task of higher + priority than the calling task. */ + if( uxNewPriority > uxCurrentPriority ) + { + if( pxTask != NULL ) + { + /* The priority of another task is being raised. If we + were raising the priority of the currently running task + there would be no need to switch as it must have already + been the highest priority task. */ + xYieldRequired = pdTRUE; + } + } + else if( pxTask == NULL ) + { + /* Setting our own priority down means there may now be another + task of higher priority that is ready to execute. */ + xYieldRequired = pdTRUE; + } + + + + #if ( configUSE_MUTEXES == 1 ) + { + /* Only change the priority being used if the task is not + currently using an inherited priority. */ + if( pxTCB->uxBasePriority == pxTCB->uxPriority ) + { + pxTCB->uxPriority = uxNewPriority; + } + + /* The base priority gets set whatever. */ + pxTCB->uxBasePriority = uxNewPriority; + } + #else + { + pxTCB->uxPriority = uxNewPriority; + } + #endif + + listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( configMAX_PRIORITIES - ( portTickType ) uxNewPriority ) ); + + /* If the task is in the blocked or suspended list we need do + nothing more than change it's priority variable. However, if + the task is in a ready list it needs to be removed and placed + in the queue appropriate to its new priority. */ + if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxCurrentPriority ] ), &( pxTCB->xGenericListItem ) ) ) + { + /* The task is currently in its ready list - remove before adding + it to it's new ready list. As we are in a critical section we + can do this even if the scheduler is suspended. */ + vListRemove( &( pxTCB->xGenericListItem ) ); + prvAddTaskToReadyQueue( pxTCB ); + } + + if( xYieldRequired == pdTRUE ) + { + taskYIELD(); + } + } + } + taskEXIT_CRITICAL(); + } + +#endif +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskSuspend == 1 ) + + void vTaskSuspend( xTaskHandle pxTaskToSuspend ) + { + tskTCB *pxTCB; + + taskENTER_CRITICAL(); + { + /* Ensure a yield is performed if the current task is being + suspended. */ + if( pxTaskToSuspend == pxCurrentTCB ) + { + pxTaskToSuspend = NULL; + } + + /* If null is passed in here then we are suspending ourselves. */ + pxTCB = prvGetTCBFromHandle( pxTaskToSuspend ); + + /* Remove task from the ready/delayed list and place in the suspended list. */ + vListRemove( &( pxTCB->xGenericListItem ) ); + + /* Is the task waiting on an event also? */ + if( pxTCB->xEventListItem.pvContainer ) + { + vListRemove( &( pxTCB->xEventListItem ) ); + } + + vListInsertEnd( ( xList * ) &xSuspendedTaskList, &( pxTCB->xGenericListItem ) ); + } + taskEXIT_CRITICAL(); + + /* We may have just suspended the current task. */ + if( ( void * ) pxTaskToSuspend == NULL ) + { + taskYIELD(); + } + } + +#endif +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskSuspend == 1 ) + + static portBASE_TYPE prvIsTaskSuspended( const tskTCB * const pxTCB ) + { + portBASE_TYPE xReturn = pdFALSE; + + /* Is the task we are attempting to resume actually in the + suspended list? */ + if( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xGenericListItem ) ) != pdFALSE ) + { + /* Has the task already been resumed from within an ISR? */ + if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) != pdTRUE ) + { + /* Is it in the suspended list because it is in the + Suspended state? It is possible to be in the suspended + list because it is blocked on a task with no timeout + specified. */ + if( listIS_CONTAINED_WITHIN( NULL, &( pxTCB->xEventListItem ) ) == pdTRUE ) + { + xReturn = pdTRUE; + } + } + } + + return xReturn; + } + +#endif +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskSuspend == 1 ) + + void vTaskResume( xTaskHandle pxTaskToResume ) + { + tskTCB *pxTCB; + + /* Remove the task from whichever list it is currently in, and place + it in the ready list. */ + pxTCB = ( tskTCB * ) pxTaskToResume; + + /* The parameter cannot be NULL as it is impossible to resume the + currently executing task. */ + if( pxTCB != NULL ) + { + taskENTER_CRITICAL(); + { + if( prvIsTaskSuspended( pxTCB ) == pdTRUE ) + { + /* As we are in a critical section we can access the ready + lists even if the scheduler is suspended. */ + vListRemove( &( pxTCB->xGenericListItem ) ); + prvAddTaskToReadyQueue( pxTCB ); + + /* We may have just resumed a higher priority task. */ + if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) + { + /* This yield may not cause the task just resumed to run, but + will leave the lists in the correct state for the next yield. */ + taskYIELD(); + } + } + } + taskEXIT_CRITICAL(); + } + } + +#endif + +/*-----------------------------------------------------------*/ + +#if ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) + + portBASE_TYPE xTaskResumeFromISR( xTaskHandle pxTaskToResume ) + { + portBASE_TYPE xYieldRequired = pdFALSE; + tskTCB *pxTCB; + + pxTCB = ( tskTCB * ) pxTaskToResume; + + if( prvIsTaskSuspended( pxTCB ) == pdTRUE ) + { + if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE ) + { + xYieldRequired = ( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ); + vListRemove( &( pxTCB->xGenericListItem ) ); + prvAddTaskToReadyQueue( pxTCB ); + } + else + { + /* We cannot access the delayed or ready lists, so will hold this + task pending until the scheduler is resumed, at which point a + yield will be performed if necessary. */ + vListInsertEnd( ( xList * ) &( xPendingReadyList ), &( pxTCB->xEventListItem ) ); + } + } + + return xYieldRequired; + } + +#endif + + + + +/*----------------------------------------------------------- + * PUBLIC SCHEDULER CONTROL documented in task.h + *----------------------------------------------------------*/ + + +void vTaskStartScheduler( void ) +{ +portBASE_TYPE xReturn; + + /* Add the idle task at the lowest priority. */ + xReturn = xTaskCreate( prvIdleTask, ( signed portCHAR * ) "IDLE", tskIDLE_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL ); + + if( xReturn == pdPASS ) + { + /* Interrupts are turned off here, to ensure a tick does not occur + before or during the call to xPortStartScheduler(). The stacks of + the created tasks contain a status word with interrupts switched on + so interrupts will automatically get re-enabled when the first task + starts to run. + + STEPPING THROUGH HERE USING A DEBUGGER CAN CAUSE BIG PROBLEMS IF THE + DEBUGGER ALLOWS INTERRUPTS TO BE PROCESSED. */ + portDISABLE_INTERRUPTS(); + + xSchedulerRunning = pdTRUE; + xTickCount = ( portTickType ) 0; + + /* Setting up the timer tick is hardware specific and thus in the + portable interface. */ + if( xPortStartScheduler() ) + { + /* Should not reach here as if the scheduler is running the + function will not return. */ + } + else + { + /* Should only reach here if a task calls xTaskEndScheduler(). */ + } + } +} +/*-----------------------------------------------------------*/ + +void vTaskEndScheduler( void ) +{ + /* Stop the scheduler interrupts and call the portable scheduler end + routine so the original ISRs can be restored if necessary. The port + layer must ensure interrupts enable bit is left in the correct state. */ + portDISABLE_INTERRUPTS(); + xSchedulerRunning = pdFALSE; + vPortEndScheduler(); +} +/*----------------------------------------------------------*/ + +void vTaskSuspendAll( void ) +{ + portENTER_CRITICAL(); + ++uxSchedulerSuspended; + portEXIT_CRITICAL(); +} +/*----------------------------------------------------------*/ + +signed portBASE_TYPE xTaskResumeAll( void ) +{ +register tskTCB *pxTCB; +signed portBASE_TYPE xAlreadyYielded = pdFALSE; + + /* It is possible that an ISR caused a task to be removed from an event + list while the scheduler was suspended. If this was the case then the + removed task will have been added to the xPendingReadyList. Once the + scheduler has been resumed it is safe to move all the pending ready + tasks from this list into their appropriate ready list. */ + portENTER_CRITICAL(); + { + --uxSchedulerSuspended; + + if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE ) + { + if( uxCurrentNumberOfTasks > ( unsigned portBASE_TYPE ) 0 ) + { + portBASE_TYPE xYieldRequired = pdFALSE; + + /* Move any readied tasks from the pending list into the + appropriate ready list. */ + while( ( pxTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( ( ( xList * ) &xPendingReadyList ) ) ) != NULL ) + { + vListRemove( &( pxTCB->xEventListItem ) ); + vListRemove( &( pxTCB->xGenericListItem ) ); + prvAddTaskToReadyQueue( pxTCB ); + + /* If we have moved a task that has a priority higher than + the current task then we should yield. */ + if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) + { + xYieldRequired = pdTRUE; + } + } + + /* If any ticks occurred while the scheduler was suspended then + they should be processed now. This ensures the tick count does not + slip, and that any delayed tasks are resumed at the correct time. */ + if( uxMissedTicks > ( unsigned portBASE_TYPE ) 0 ) + { + while( uxMissedTicks > ( unsigned portBASE_TYPE ) 0 ) + { + vTaskIncrementTick(); + --uxMissedTicks; + } + + /* As we have processed some ticks it is appropriate to yield + to ensure the highest priority task that is ready to run is + the task actually running. */ + #if configUSE_PREEMPTION == 1 + { + xYieldRequired = pdTRUE; + } + #endif + } + + if( ( xYieldRequired == pdTRUE ) || ( xMissedYield == pdTRUE ) ) + { + xAlreadyYielded = pdTRUE; + xMissedYield = pdFALSE; + taskYIELD(); + } + } + } + } + portEXIT_CRITICAL(); + + return xAlreadyYielded; +} + + + + + + +/*----------------------------------------------------------- + * PUBLIC TASK UTILITIES documented in task.h + *----------------------------------------------------------*/ + + + +portTickType xTaskGetTickCount( void ) +{ +portTickType xTicks; + + /* Critical section required if running on a 16 bit processor. */ + taskENTER_CRITICAL(); + { + xTicks = xTickCount; + } + taskEXIT_CRITICAL(); + + return xTicks; +} +/*-----------------------------------------------------------*/ + +unsigned portBASE_TYPE uxTaskGetNumberOfTasks( void ) +{ +unsigned portBASE_TYPE uxNumberOfTasks; + + taskENTER_CRITICAL(); + uxNumberOfTasks = uxCurrentNumberOfTasks; + taskEXIT_CRITICAL(); + + return uxNumberOfTasks; +} +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_vTaskDelete == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) + + void vTaskList( signed portCHAR *pcWriteBuffer ) + { + unsigned portBASE_TYPE uxQueue; + + /* This is a VERY costly function that should be used for debug only. + It leaves interrupts disabled for a LONG time. */ + + vTaskSuspendAll(); + { + /* Run through all the lists that could potentially contain a TCB and + report the task name, state and stack high water mark. */ + + pcWriteBuffer[ 0 ] = ( signed portCHAR ) 0x00; + strcat( ( portCHAR * ) pcWriteBuffer, ( const portCHAR * ) "\r\n" ); + + uxQueue = uxTopUsedPriority + 1; + + do + { + uxQueue--; + + if( !listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxQueue ] ) ) ) + { + prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) &( pxReadyTasksLists[ uxQueue ] ), tskREADY_CHAR ); + } + }while( uxQueue > ( unsigned portSHORT ) tskIDLE_PRIORITY ); + + if( !listLIST_IS_EMPTY( pxDelayedTaskList ) ) + { + prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) pxDelayedTaskList, tskBLOCKED_CHAR ); + } + + if( !listLIST_IS_EMPTY( pxOverflowDelayedTaskList ) ) + { + prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) pxOverflowDelayedTaskList, tskBLOCKED_CHAR ); + } + + if( !listLIST_IS_EMPTY( &xTasksWaitingTermination ) ) + { + prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) &xTasksWaitingTermination, tskDELETED_CHAR ); + } + + if( !listLIST_IS_EMPTY( &xSuspendedTaskList ) ) + { + prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) &xSuspendedTaskList, tskSUSPENDED_CHAR ); + } + } + xTaskResumeAll(); + } + +#endif +/*----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + void vTaskStartTrace( signed portCHAR * pcBuffer, unsigned portLONG ulBufferSize ) + { + portENTER_CRITICAL(); + { + pcTraceBuffer = ( volatile signed portCHAR * volatile )pcBuffer; + pcTraceBufferStart = pcBuffer; + pcTraceBufferEnd = pcBuffer + ( ulBufferSize - tskSIZE_OF_EACH_TRACE_LINE ); + xTracing = pdTRUE; + } + portEXIT_CRITICAL(); + } + +#endif +/*----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + unsigned portLONG ulTaskEndTrace( void ) + { + unsigned portLONG ulBufferLength; + + portENTER_CRITICAL(); + xTracing = pdFALSE; + portEXIT_CRITICAL(); + + ulBufferLength = ( unsigned portLONG ) ( pcTraceBuffer - pcTraceBufferStart ); + + return ulBufferLength; + } + +#endif + + + +/*----------------------------------------------------------- + * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES + * documented in task.h + *----------------------------------------------------------*/ + + +inline void vTaskIncrementTick( void ) +{ + /* Called by the portable layer each time a tick interrupt occurs. + Increments the tick then checks to see if the new tick value will cause any + tasks to be unblocked. */ + if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE ) + { + ++xTickCount; + if( xTickCount == ( portTickType ) 0 ) + { + xList *pxTemp; + + /* Tick count has overflowed so we need to swap the delay lists. + If there are any items in pxDelayedTaskList here then there is + an error! */ + pxTemp = pxDelayedTaskList; + pxDelayedTaskList = pxOverflowDelayedTaskList; + pxOverflowDelayedTaskList = pxTemp; + xNumOfOverflows++; + } + + /* See if this tick has made a timeout expire. */ + prvCheckDelayedTasks(); + } + else + { + ++uxMissedTicks; + + /* The tick hook gets called at regular intervals, even if the + scheduler is locked. */ + #if ( configUSE_TICK_HOOK == 1 ) + { + extern void vApplicationTickHook( void ); + + vApplicationTickHook(); + } + #endif + } + + #if ( configUSE_TICK_HOOK == 1 ) + { + extern void vApplicationTickHook( void ); + + /* Guard against the tick hook being called when the missed tick + count is being unwound (when the scheduler is being unlocked. */ + if( uxMissedTicks == 0 ) + { + vApplicationTickHook(); + } + } + #endif +} +/*-----------------------------------------------------------*/ + +#if ( ( INCLUDE_vTaskCleanUpResources == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) + + void vTaskCleanUpResources( void ) + { + unsigned portSHORT usQueue; + volatile tskTCB *pxTCB; + + usQueue = ( unsigned portSHORT ) uxTopUsedPriority + ( unsigned portSHORT ) 1; + + /* Remove any TCB's from the ready queues. */ + do + { + usQueue--; + + while( !listLIST_IS_EMPTY( &( pxReadyTasksLists[ usQueue ] ) ) ) + { + listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &( pxReadyTasksLists[ usQueue ] ) ); + vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) ); + + prvDeleteTCB( ( tskTCB * ) pxTCB ); + } + }while( usQueue > ( unsigned portSHORT ) tskIDLE_PRIORITY ); + + /* Remove any TCB's from the delayed queue. */ + while( !listLIST_IS_EMPTY( &xDelayedTaskList1 ) ) + { + listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &xDelayedTaskList1 ); + vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) ); + + prvDeleteTCB( ( tskTCB * ) pxTCB ); + } + + /* Remove any TCB's from the overflow delayed queue. */ + while( !listLIST_IS_EMPTY( &xDelayedTaskList2 ) ) + { + listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &xDelayedTaskList2 ); + vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) ); + + prvDeleteTCB( ( tskTCB * ) pxTCB ); + } + + while( !listLIST_IS_EMPTY( &xSuspendedTaskList ) ) + { + listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &xSuspendedTaskList ); + vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) ); + + prvDeleteTCB( ( tskTCB * ) pxTCB ); + } + } + +#endif +/*-----------------------------------------------------------*/ + +void vTaskSwitchContext( void ) +{ + if( uxSchedulerSuspended != ( unsigned portBASE_TYPE ) pdFALSE ) + { + /* The scheduler is currently suspended - do not allow a context + switch. */ + xMissedYield = pdTRUE; + return; + } + + /* Find the highest priority queue that contains ready tasks. */ + while( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopReadyPriority ] ) ) ) + { + --uxTopReadyPriority; + } + + /* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the tasks of the + same priority get an equal share of the processor time. */ + listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopReadyPriority ] ) ); + vWriteTraceToBuffer(); +} +/*-----------------------------------------------------------*/ + +void vTaskPlaceOnEventList( const xList * const pxEventList, portTickType xTicksToWait ) +{ +portTickType xTimeToWake; + + /* THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED OR THE + SCHEDULER SUSPENDED. */ + + /* Place the event list item of the TCB in the appropriate event list. + This is placed in the list in priority order so the highest priority task + is the first to be woken by the event. */ + vListInsert( ( xList * ) pxEventList, ( xListItem * ) &( pxCurrentTCB->xEventListItem ) ); + + /* We must remove ourselves from the ready list before adding ourselves + to the blocked list as the same list item is used for both lists. We have + exclusive access to the ready lists as the scheduler is locked. */ + vListRemove( ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); + + + #if ( INCLUDE_vTaskSuspend == 1 ) + { + if( xTicksToWait == portMAX_DELAY ) + { + /* Add ourselves to the suspended task list instead of a delayed task + list to ensure we are not woken by a timing event. We will block + indefinitely. */ + vListInsertEnd( ( xList * ) &xSuspendedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); + } + else + { + /* Calculate the time at which the task should be woken if the event does + not occur. This may overflow but this doesn't matter. */ + xTimeToWake = xTickCount + xTicksToWait; + + listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake ); + + if( xTimeToWake < xTickCount ) + { + /* Wake time has overflowed. Place this item in the overflow list. */ + vListInsert( ( xList * ) pxOverflowDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); + } + else + { + /* The wake time has not overflowed, so we can use the current block list. */ + vListInsert( ( xList * ) pxDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); + } + } + } + #else + { + /* Calculate the time at which the task should be woken if the event does + not occur. This may overflow but this doesn't matter. */ + xTimeToWake = xTickCount + xTicksToWait; + + listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake ); + + if( xTimeToWake < xTickCount ) + { + /* Wake time has overflowed. Place this item in the overflow list. */ + vListInsert( ( xList * ) pxOverflowDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); + } + else + { + /* The wake time has not overflowed, so we can use the current block list. */ + vListInsert( ( xList * ) pxDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); + } + } + #endif +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xTaskRemoveFromEventList( const xList * const pxEventList ) +{ +tskTCB *pxUnblockedTCB; +portBASE_TYPE xReturn; + + /* THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED OR THE + SCHEDULER SUSPENDED. It can also be called from within an ISR. */ + + /* The event list is sorted in priority order, so we can remove the + first in the list, remove the TCB from the delayed list, and add + it to the ready list. + + If an event is for a queue that is locked then this function will never + get called - the lock count on the queue will get modified instead. This + means we can always expect exclusive access to the event list here. */ + pxUnblockedTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); + vListRemove( &( pxUnblockedTCB->xEventListItem ) ); + + if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE ) + { + vListRemove( &( pxUnblockedTCB->xGenericListItem ) ); + prvAddTaskToReadyQueue( pxUnblockedTCB ); + } + else + { + /* We cannot access the delayed or ready lists, so will hold this + task pending until the scheduler is resumed. */ + vListInsertEnd( ( xList * ) &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) ); + } + + if( pxUnblockedTCB->uxPriority >= pxCurrentTCB->uxPriority ) + { + /* Return true if the task removed from the event list has + a higher priority than the calling task. This allows + the calling task to know if it should force a context + switch now. */ + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +void vTaskSetTimeOutState( xTimeOutType * const pxTimeOut ) +{ + pxTimeOut->xOverflowCount = xNumOfOverflows; + pxTimeOut->xTimeOnEntering = xTickCount; +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xTaskCheckForTimeOut( xTimeOutType * const pxTimeOut, portTickType * const pxTicksToWait ) +{ +portBASE_TYPE xReturn; + + #if ( INCLUDE_vTaskSuspend == 1 ) + /* If INCLUDE_vTaskSuspend is set to 1 and the block time specified is + the maximum block time then the task should block indefinitely, and + therefore never time out. */ + if( *pxTicksToWait == portMAX_DELAY ) + { + xReturn = pdFALSE; + } + else /* We are not blocking indefinitely, perform the checks below. */ + #endif + + if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xTickCount >= pxTimeOut->xTimeOnEntering ) ) + { + /* The tick count is greater than the time at which vTaskSetTimeout() + was called, but has also overflowed since vTaskSetTimeOut() was called. + It must have wrapped all the way around and gone past us again. This + passed since vTaskSetTimeout() was called. */ + xReturn = pdTRUE; + } + else if( ( xTickCount - pxTimeOut->xTimeOnEntering ) < *pxTicksToWait ) + { + /* Not a genuine timeout. Adjust parameters for time remaining. */ + *pxTicksToWait -= ( xTickCount - pxTimeOut->xTimeOnEntering ); + vTaskSetTimeOutState( pxTimeOut ); + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +void vTaskMissedYield( void ) +{ + xMissedYield = pdTRUE; +} + +/* + * ----------------------------------------------------------- + * The Idle task. + * ---------------------------------------------------------- + * + * The portTASK_FUNCTION() macro is used to allow port/compiler specific + * language extensions. The equivalent prototype for this function is: + * + * void prvIdleTask( void *pvParameters ); + * + */ +static portTASK_FUNCTION( prvIdleTask, pvParameters ) +{ + /* Stop warnings. */ + ( void ) pvParameters; + + for( ;; ) + { + /* See if any tasks have been deleted. */ + prvCheckTasksWaitingTermination(); + + #if ( configUSE_PREEMPTION == 0 ) + { + /* If we are not using preemption we keep forcing a task switch to + see if any other task has become available. If we are using + preemption we don't need to do this as any task becoming available + will automatically get the processor anyway. */ + taskYIELD(); + } + #endif + + #if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) + { + /* When using preemption tasks of equal priority will be + timesliced. If a task that is sharing the idle priority is ready + to run then the idle task should yield before the end of the + timeslice. + + A critical region is not required here as we are just reading from + the list, and an occasional incorrect value will not matter. If + the ready list at the idle priority contains more than one task + then a task other than the idle task is ready to execute. */ + if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( unsigned portBASE_TYPE ) 1 ) + { + taskYIELD(); + } + } + #endif + + #if ( configUSE_IDLE_HOOK == 1 ) + { + extern void vApplicationIdleHook( void ); + + /* Call the user defined function from within the idle task. This + allows the application designer to add background functionality + without the overhead of a separate task. + NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES, + CALL A FUNCTION THAT MIGHT BLOCK. */ + vApplicationIdleHook(); + } + #endif + } +} /*lint !e715 pvParameters is not accessed but all task functions require the same prototype. */ + + + + + + + +/*----------------------------------------------------------- + * File private functions documented at the top of the file. + *----------------------------------------------------------*/ + + + +static void prvInitialiseTCBVariables( tskTCB *pxTCB, const signed portCHAR * const pcName, unsigned portBASE_TYPE uxPriority ) +{ + /* Store the function name in the TCB. */ + strncpy( ( char * ) pxTCB->pcTaskName, ( const char * ) pcName, ( unsigned portSHORT ) configMAX_TASK_NAME_LEN ); + pxTCB->pcTaskName[ ( unsigned portSHORT ) configMAX_TASK_NAME_LEN - ( unsigned portSHORT ) 1 ] = '\0'; + + /* This is used as an array index so must ensure it's not too large. */ + if( uxPriority >= configMAX_PRIORITIES ) + { + uxPriority = configMAX_PRIORITIES - 1; + } + + pxTCB->uxPriority = uxPriority; + #if ( configUSE_MUTEXES == 1 ) + { + pxTCB->uxBasePriority = uxPriority; + } + #endif + + vListInitialiseItem( &( pxTCB->xGenericListItem ) ); + vListInitialiseItem( &( pxTCB->xEventListItem ) ); + + /* Set the pxTCB as a link back from the xListItem. This is so we can get + back to the containing TCB from a generic item in a list. */ + listSET_LIST_ITEM_OWNER( &( pxTCB->xGenericListItem ), pxTCB ); + + /* Event lists are always in priority order. */ + listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), configMAX_PRIORITIES - ( portTickType ) uxPriority ); + listSET_LIST_ITEM_OWNER( &( pxTCB->xEventListItem ), pxTCB ); +} +/*-----------------------------------------------------------*/ + +static void prvInitialiseTaskLists( void ) +{ +unsigned portBASE_TYPE uxPriority; + + for( uxPriority = 0; uxPriority < configMAX_PRIORITIES; uxPriority++ ) + { + vListInitialise( ( xList * ) &( pxReadyTasksLists[ uxPriority ] ) ); + } + + vListInitialise( ( xList * ) &xDelayedTaskList1 ); + vListInitialise( ( xList * ) &xDelayedTaskList2 ); + vListInitialise( ( xList * ) &xPendingReadyList ); + + #if ( INCLUDE_vTaskDelete == 1 ) + { + vListInitialise( ( xList * ) &xTasksWaitingTermination ); + } + #endif + + #if ( INCLUDE_vTaskSuspend == 1 ) + { + vListInitialise( ( xList * ) &xSuspendedTaskList ); + } + #endif + + /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList + using list2. */ + pxDelayedTaskList = &xDelayedTaskList1; + pxOverflowDelayedTaskList = &xDelayedTaskList2; +} +/*-----------------------------------------------------------*/ + +static void prvCheckTasksWaitingTermination( void ) +{ + #if ( INCLUDE_vTaskDelete == 1 ) + { + portBASE_TYPE xListIsEmpty; + + /* ucTasksDeleted is used to prevent vTaskSuspendAll() being called + too often in the idle task. */ + if( uxTasksDeleted > ( unsigned portBASE_TYPE ) 0 ) + { + vTaskSuspendAll(); + xListIsEmpty = listLIST_IS_EMPTY( &xTasksWaitingTermination ); + xTaskResumeAll(); + + if( !xListIsEmpty ) + { + tskTCB *pxTCB; + + portENTER_CRITICAL(); + { + pxTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( ( ( xList * ) &xTasksWaitingTermination ) ); + vListRemove( &( pxTCB->xGenericListItem ) ); + --uxCurrentNumberOfTasks; + --uxTasksDeleted; + } + portEXIT_CRITICAL(); + + prvDeleteTCB( pxTCB ); + } + } + } + #endif +} +/*-----------------------------------------------------------*/ + +static tskTCB *prvAllocateTCBAndStack( unsigned portSHORT usStackDepth ) +{ +tskTCB *pxNewTCB; + + /* Allocate space for the TCB. Where the memory comes from depends on + the implementation of the port malloc function. */ + pxNewTCB = ( tskTCB * ) pvPortMalloc( sizeof( tskTCB ) ); + + if( pxNewTCB != NULL ) + { + /* Allocate space for the stack used by the task being created. + The base of the stack memory stored in the TCB so the task can + be deleted later if required. */ + pxNewTCB->pxStack = ( portSTACK_TYPE * ) pvPortMalloc( ( ( size_t )usStackDepth ) * sizeof( portSTACK_TYPE ) ); + + if( pxNewTCB->pxStack == NULL ) + { + /* Could not allocate the stack. Delete the allocated TCB. */ + vPortFree( pxNewTCB ); + pxNewTCB = NULL; + } + else + { + /* Just to help debugging. */ + memset( pxNewTCB->pxStack, tskSTACK_FILL_BYTE, usStackDepth * sizeof( portSTACK_TYPE ) ); + } + } + + return pxNewTCB; +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + static void prvListTaskWithinSingleList( const signed portCHAR *pcWriteBuffer, xList *pxList, signed portCHAR cStatus ) + { + volatile tskTCB *pxNextTCB, *pxFirstTCB; + static portCHAR pcStatusString[ 50 ]; + unsigned portSHORT usStackRemaining; + + /* Write the details of all the TCB's in pxList into the buffer. */ + listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); + do + { + listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); + usStackRemaining = usTaskCheckFreeStackSpace( ( unsigned portCHAR * ) pxNextTCB->pxStack ); + sprintf( pcStatusString, ( portCHAR * ) "%s\t\t%c\t%u\t%u\t%u\r\n", pxNextTCB->pcTaskName, cStatus, ( unsigned int ) pxNextTCB->uxPriority, usStackRemaining, ( unsigned int ) pxNextTCB->uxTCBNumber ); + strcat( ( portCHAR * ) pcWriteBuffer, ( portCHAR * ) pcStatusString ); + + } while( pxNextTCB != pxFirstTCB ); + } + +#endif +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + unsigned portSHORT usTaskCheckFreeStackSpace( const unsigned portCHAR * pucStackByte ) + { + register unsigned portSHORT usCount = 0; + + while( *pucStackByte == tskSTACK_FILL_BYTE ) + { + pucStackByte -= portSTACK_GROWTH; + usCount++; + } + + usCount /= sizeof( portSTACK_TYPE ); + + return usCount; + } +#endif +/*-----------------------------------------------------------*/ + + + +#if ( ( INCLUDE_vTaskDelete == 1 ) || ( INCLUDE_vTaskCleanUpResources == 1 ) ) + + static void prvDeleteTCB( tskTCB *pxTCB ) + { + /* Free up the memory allocated by the scheduler for the task. It is up to + the task to free any memory allocated at the application level. */ + vPortFree( pxTCB->pxStack ); + vPortFree( pxTCB ); + } + +#endif + + +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) + + xTaskHandle xTaskGetCurrentTaskHandle( void ) + { + xTaskHandle xReturn; + + portENTER_CRITICAL(); + { + xReturn = ( xTaskHandle ) pxCurrentTCB; + } + portEXIT_CRITICAL(); + + return xReturn; + } + +#endif + +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_xTaskGetSchedulerState == 1 ) + + portBASE_TYPE xTaskGetSchedulerState( void ) + { + portBASE_TYPE xReturn; + + if( xSchedulerRunning == pdFALSE ) + { + xReturn = taskSCHEDULER_NOT_STARTED; + } + else + { + if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE ) + { + xReturn = taskSCHEDULER_RUNNING; + } + else + { + xReturn = taskSCHEDULER_SUSPENDED; + } + } + + return xReturn; + } + +#endif + +#if ( configUSE_MUTEXES == 1 ) + + void vTaskPriorityInherit( xTaskHandle * const pxMutexHolder ) + { + tskTCB * const pxTCB = ( tskTCB * ) pxMutexHolder; + + if( pxTCB->uxPriority < pxCurrentTCB->uxPriority ) + { + /* Adjust the mutex holder state to account for its new priority. */ + listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), configMAX_PRIORITIES - ( portTickType ) pxCurrentTCB->uxPriority ); + + /* If the task being modified is in the ready state it will need to + be moved in to a new list. */ + if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxTCB->uxPriority ] ), &( pxTCB->xGenericListItem ) ) ) + { + vListRemove( &( pxTCB->xGenericListItem ) ); + + /* Inherit the priority before being moved into the new list. */ + pxTCB->uxPriority = pxCurrentTCB->uxPriority; + prvAddTaskToReadyQueue( pxTCB ); + } + else + { + /* Just inherit the priority. */ + pxTCB->uxPriority = pxCurrentTCB->uxPriority; + } + } + } + +#endif + +#if ( configUSE_MUTEXES == 1 ) + + void vTaskPriorityDisinherit( xTaskHandle * const pxMutexHolder ) + { + tskTCB * const pxTCB = ( tskTCB * ) pxMutexHolder; + + if( pxMutexHolder != NULL ) + { + if( pxTCB->uxPriority != pxTCB->uxBasePriority ) + { + /* We must be the running task to be able to give the mutex back. + Remove ourselves from the ready list we currently appear in. */ + vListRemove( &( pxTCB->xGenericListItem ) ); + + /* Disinherit the priority before adding ourselves into the new + ready list. */ + pxTCB->uxPriority = pxTCB->uxBasePriority; + listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), configMAX_PRIORITIES - ( portTickType ) pxTCB->uxPriority ); + prvAddTaskToReadyQueue( pxTCB ); + } + } + } + +#endif + + + + + diff --git a/20080212/TraceCon/readme.txt b/20080212/TraceCon/readme.txt new file mode 100644 index 000000000..ae78ac933 --- /dev/null +++ b/20080212/TraceCon/readme.txt @@ -0,0 +1,6 @@ +Tracecon.exe is a very simplistic utility for converting the trace data captured by the scheduler into a tab delimited text file. The text file can be opened using a spread sheet program as described on www.FreeRTOS.org. + +Tracecon should be executed from a command prompt. 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See http://www.freertos.org/a00017.html for full details of the +directory structure and information on locating the files you require. + +The easiest way to use FreeRTOS is start start with one of the demo application +projects. Once this is running the project can be modified to include your own +source files. This way the correct files and compiler options will be +automatically included in your application. + ++ The Source directory contains the real time kernel source files for every +port. The kernel itself is only 3 files. + ++ The Demo directory contains the demo application source files for every +port. + ++ The TraceCon directory contains the trace visualisation exe file. + +See the readme files in the respective directories for further information. +